From 4d4f592e91539b0ce647dc1456c0110c31c22bf4 Mon Sep 17 00:00:00 2001 From: Alex Brudner <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Tue, 30 Jan 2024 10:11:22 -0700 Subject: [PATCH 01/13] Add WIP Variant. --- boards.txt | 48 + bootloaders/THINGPLUS_RA6M5/README.md | 27 + bootloaders/THINGPLUS_RA6M5/dfu.elf | Bin 0 -> 665152 bytes bootloaders/THINGPLUS_RA6M5/dfu.hex | 860 ++++++++++++ .../SparkFun_ThingPlus_RA6M5/.api_xml | 2 + .../SparkFun_ThingPlus_RA6M5/.cproject | 470 +++++++ .../SparkFun_ThingPlus_RA6M5/.gitignore | 8 + .../SparkFun_ThingPlus_RA6M5/.project | 39 + .../SparkFun_ThingPlus_RA6M5/.secure_azone | 116 ++ .../SparkFun_ThingPlus_RA6M5/.secure_xml | 108 ++ .../.settings/.gitignore | 1 + .../com.renesas.cdt.ddsc.content.prefs | 2 + ....renesas.cdt.ddsc.contentgen.options.prefs | 2 + ...enesas.cdt.ddsc.packs.componentfiles.prefs | 71 + .../com.renesas.cdt.ddsc.settingseditor.prefs | 2 + ...enesas.cdt.ddsc.threads.configurator.prefs | 12 + .../com.renesas.cdt.managedbuild.gnuarm.prefs | 4 + .../.settings/language.settings.xml | 25 + .../.settings/org.eclipse.cdt.core.prefs | 197 +++ .../org.eclipse.cdt.managedbuilder.core.prefs | 13 + .../org.eclipse.core.resources.prefs | 2 + ...SparkFun_ThingPlus_RA6M5 Debug_Flat.launch | 115 ++ .../configuration.xml | 1210 +++++++++++++++++ .../fsp_to_arduino.sh | 162 +++ .../SparkFun_ThingPlus_RA6M5/ra_cfg.txt | 881 ++++++++++++ extras/package_sfe.sh | 36 + post_install.sh | 1 + tmp/.portenta_only | 0 tmp/fsp.ld | 609 +++++++++ tmp/memory_regions.ld | 26 + tmp/pinmux.inc | 406 ++++++ tmp/pins_arduino.h | 168 +++ tmp/tusb_config.h | 102 ++ tmp/variant.cpp | 131 ++ 34 files changed, 5856 insertions(+) create mode 100644 bootloaders/THINGPLUS_RA6M5/README.md create mode 100644 bootloaders/THINGPLUS_RA6M5/dfu.elf create mode 100644 bootloaders/THINGPLUS_RA6M5/dfu.hex create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.api_xml create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.gitignore create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.project create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/.gitignore create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.content.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.contentgen.options.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.packs.componentfiles.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.threads.configurator.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.core.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.managedbuilder.core.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.core.resources.prefs create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/SparkFun_ThingPlus_RA6M5 Debug_Flat.launch create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/fsp_to_arduino.sh create mode 100644 extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt create mode 100644 extras/package_sfe.sh create mode 100644 tmp/.portenta_only create mode 100644 tmp/fsp.ld create mode 100644 tmp/memory_regions.ld create mode 100644 tmp/pinmux.inc create mode 100644 tmp/pins_arduino.h create mode 100644 tmp/tusb_config.h create mode 100644 tmp/variant.cpp diff --git a/boards.txt b/boards.txt index e4297279..6ea266d2 100644 --- a/boards.txt +++ b/boards.txt @@ -206,3 +206,51 @@ muxto.upload.maximum_size=262144 muxto.upload.maximum_data_size=32768 ############################################################## + +thingplus_ra6m5.name=SparkFun Thing Plus RA6M5 +thingplus_ra6m5.build.core=arduino +thingplus_ra6m5.build.crossprefix=arm-none-eabi- +thingplus_ra6m5.build.compiler_path={runtime.tools.arm-none-eabi-gcc-7-2017q4.path}/bin/ + +thingplus_ra6m5.build.variant=THINGPLUS_RA6M5 +thingplus_ra6m5.build.mcu=cortex-m33 +thingplus_ra6m5.build.architecture=cortex-m33 +thingplus_ra6m5.build.fpu=-mfpu=fpv5-sp-d16 +thingplus_ra6m5.build.float-abi=-mfloat-abi=hard + +thingplus_ra6m5.build.board=THINGPLUS_RA6M5 +thingplus_ra6m5.build.defines=-DF_CPU=200000000 +thingplus_ra6m5.vid.0=0x1b4f +thingplus_ra6m5.pid.0=0x0036 +thingplus_ra6m5.vid.1=0x1b4f +thingplus_ra6m5.pid.1=0x0037 +thingplus_ra6m5.upload_port.0.vid=0x1b4f +thingplus_ra6m5.upload_port.0.pid=0x0036 +thingplus_ra6m5.upload_port.1.vid=0x1b4f +thingplus_ra6m5.upload_port.1.pid=0x0037 + +thingplus_ra6m5.compiler.fsp.defines={build.variant.path}/defines.txt +thingplus_ra6m5.compiler.fsp.ldflags={build.variant.path}/ldflags.txt +thingplus_ra6m5.compiler.fsp.cflags=-mthumb "@{compiler.fsp.defines}" +thingplus_ra6m5.compiler.fsp.cxxflags=-mthumb "@{compiler.fsp.defines}" +thingplus_ra6m5.compiler.tinyusb.cflags=-DCFG_TUSB_MCU=OPT_MCU_RAXXX +thingplus_ra6m5.compiler.tinyusb.cxxflags=-DCFG_TUSB_MCU=OPT_MCU_RAXXX +thingplus_ra6m5.compiler.fsp.includes={build.variant.path}/includes.txt +thingplus_ra6m5.compiler.fsp.extra_ldflags=-lstdc++ -lsupc++ -lm -lc -lgcc -lnosys +thingplus_ra6m5.compiler.fsp="{build.variant.path}/libs/libfsp.a" + +thingplus_ra6m5.upload.tool=dfu-util +thingplus_ra6m5.upload.tool.default=dfu-util +thingplus_ra6m5.upload.protocol= +thingplus_ra6m5.upload.transport= +thingplus_ra6m5.upload.vid=0x1b4f +thingplus_ra6m5.upload.pid=0x0036 +thingplus_ra6m5.upload.address=0x00010000 +thingplus_ra6m5.upload.interface=0 +thingplus_ra6m5.upload.use_1200bps_touch=false +thingplus_ra6m5.upload.wait_for_upload_port=false +thingplus_ra6m5.upload.native_usb=true +thingplus_ra6m5.upload.maximum_size=2097152 +thingplus_ra6m5.upload.maximum_data_size=523624 + +############################################################## diff --git a/bootloaders/THINGPLUS_RA6M5/README.md b/bootloaders/THINGPLUS_RA6M5/README.md new file mode 100644 index 00000000..0664431f --- /dev/null +++ b/bootloaders/THINGPLUS_RA6M5/README.md @@ -0,0 +1,27 @@ +:floppy_disk: `bootloaders/THINGPLUS_RA6M5` +==================================== +Compiled with +```bash +git clone https://github.com/arduino/arduino-renesas-bootloader +git clone https://github.com/hathach/tinyusb +cd tinyusb +# This step is temporary +patch -p1 < ../arduino-renesas-bootloader/0001-fix-arduino-bootloaders.patch +python tools/get_deps.py ra +cd .. +cd arduino-renesas-bootloader +TINYUSB_ROOT=$PWD/../tinyusb make -f Makefile.thingplus +``` + +:rocket: `How to load bootloader` +==================================== + +Hold the boot button down and plug in the Thing Plus RA6M5. +The board will enumerate as Renesas RA USB Boot. + +Then flash the bootloader with [`rfp-cli`](https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui#download) +``` +rfp-cli -device ra -port $portname -p dfu_c33.hex +``` + +Otherwise, the same hex file can be loaded through the SWD port (using a Jlink for example) diff --git a/bootloaders/THINGPLUS_RA6M5/dfu.elf b/bootloaders/THINGPLUS_RA6M5/dfu.elf new file mode 100644 index 0000000000000000000000000000000000000000..b6ecfd5697c83a6c773e7942be269033e88b11b2 GIT binary patch literal 665152 zcmeFX3wTsT)-GK8mhN02of{;b0Da*Sk^l_>MbV+@Bn?Re2^U8})P#UG7p3K*5gq9e zV1kMQK?g~25O4$$B*8c`8iU|C%BYj(qFhwspf(UkJ0#GX1k&eSI{}^fJkNRl|2zNx zobx;tSbMK`tyQb4-d($P?drWOXS`Do1a|#TWT}kMP77nhab9bVU`%GpaAsm*@bzZB zG(YP)QaSyQPEiQJ-kD7#U?SfWaFG0)|7G}JMkpj6fh01O=qf)P{^9VEko~$`_p_}i zzZJod2KY&SS-z`I6V4{M*wt4U+E0I-tzp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?( z3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk z&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u z;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp z0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n z8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+R zz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zpfg22z>|&;!7RFXfjJ1pZRc-`A zx$Y+$>CY>S)x|QV^knQ6==&hQ{ClwvW4A+kMKG2W`AZMi|93GE`fvV4xDMA$QEes#`lt8ZEGoM$Yxi^`0w zRh*&V3nAHAQk@FztB|!k)hPueDJvjKRuT~ zt$|dcU2Q(Wx>aRE#k`8bxI(n(fM91HW)E{!sQnGbxr*yxi#T(NYPKDY;^TNm1 zs2!QZRRgQ6$!hJFWxc?pt+14$tf7w8r>;glXlDtyvQgd@oq4-;p9tNF5%4ag4&kz*!U%m3&|JBk{-oi+T%mE=y^ ze|w(KV>kOeMz=7`Sm;F-X1Zm9xqNxeI!E3Kt)G_Vuo~U5)rh&(SZH(`_uE{jJYLHw z5A~w%ocdgTfa%YuZ?4V1@VAI!_bsZJE;U66tIO9pditiQ5w^%S{bece_LP0i-es3- zo>$))9_!0=g!=?jD7Yd-xOdh{^_^Lv;G~egS$VU3~;-{)L8`KO$WlV7OJyFEwWBnxRLUTNyC>}isvjO^_-n`>$v zsr4hA>CR8jGcgprc{-5+qJqs@za&fc7EZf9wd&}Iln8veZOGp=b7z!#q*t~Gj^|fuXnIhA6TZ($w{qu zIww{aFEzX40zx!vju$hX-Edbu8FJ=~tj}*{S+6vODagu3)<3@DJMUM1VO=P=^_uYF z&}?(z4}O}*qO7QG?C^=QQ)(BA_o-ptZqB!xS+vnNv|4DsSsbp$+NR0v$HE%(1C7?B zYT))0I(D4B7iDHv!89RjVbY>Irg$nmM?2g1`=@c|d1s0%x2Ushd)4_{`m{aOW?dr% zqNUA_Hed0YO8M&XhMcj^)cQM}&sFCKqQb-5l`COQ;nLkpf2)QYs3&rBqBzPK-(Ui3 ziJ?1lZqxcwypmb1D@|(*foRt5i!uxC%IqCYI^9p+_x&a(^=t%sc1yMsS-#c!rgJ5i zlsUpqhPhaioh7?z=Jkw?uV*G{9L+CV(Eln(${@!6?iO<+iv)8b?Au|JoKl{lB(gdb z>|YlO-dZ;jHqj!wrhA#i_^@Yefezyu*ys%fTk2W8hH>v)st<*pe#}!Vq{sUH{+O5^ z?PJzN=bDmF9uqT+zU7Ya6J0!ZGXwtz;* z7LV41r+rd?bEYj*R)yPN#=T-NT=W_0^tA$*wRhCF-1nSd5dwXrO?Fp!C6k&9v!qK! zS%*}w*;uHr6D(QbEYOFEZ7d+?nKB)!mHqt0!TgNpjp5C3fi)Lqe_SJ9D#~7=vN$Ps z4DRK7RM`~@97ozUXs@A8s7$UFDuq!(MKkiWd0PEwYvVHe&9!C!r5)eQGd`SDnCP5|c5M5Vb{H`4 zymBoR+zEO4+N~~{ql|N69)G`uv5$56$12neLxq}Vf5wr}P@xWDrfPAZ=$mXkx-hD- zLQOUJJQZrXNw~EPN5qXPP;*@t-h`2Ex8Zk!|B;+-K3OPV=-X7Zd9o}c^` z>QMXqYGGiRI+V#ili4_D-NKM5;9tAYI9Eu!;=AN8c5j z_W{=iQJ?}RLUNlRnKdSoF!a9Gzatbw6lt_VpNEM!1 zKeeA(^e*GWn@Z#~(I;6pc|2ovX;*#5lGuP89bX@2(OX*mbkFE(r4k`M%qQhWmM7zm zKO17!NUy%`YdoJ9)ed(JAODs66+A(Wb8p>W0ah*h_5E#m_ZG%JZd}MLuQ=AIGFzi6 zhB9@qX{c}7yvOzlJ6|jk%_obJmI?!PzA|;7X}Y@%{7hzLYAVeexC(t2os3CS8AwBbzC2|0GK?7^gLrg4w2^UEJ%bW7@SwDO1uM zAuXyN;|@6nnhyW!*lYBwPcc*0u-qx*X`U0ZE_e<0))gK*<|E9Csp4rNFBFW!%5XfM zyR@#c=X;&HriQo*b%6b8XFS%sJ)HR$8jO(**Jq%UI_VheYjV>1guQpgKO%3v%GM&@ zG|uV3dbkYQP>iEn3PQmRZQb^>_d5Lal)1ejzjZ}%`ik^tHicb1KF~FN=}X=PElixg z@M|v{JgVW4%Jx#+u!dT-(3U7m$7|K8wxqBD$FA3WN}Kz}VLqGO#xm-Bx~2$;>Yarw zRBNZcT+^?YIj!4)C)lh0S5%WX{h7+JtH<8=(^@&}s?hfpwb1^BzqjXJ&r6=KJ&IMc z*go@riE%>Dfa~jjTW#WmUG4|nRSyj+kp^w77l!Mrw>VOc-aYS#Zfd=RIrUJBoFxs? zolFid!x$d7f7^c1>MFF=Nr5QI*k_7k%9vLF7Kd<@rC;<()@DCtVa*|%9#3YLajv1& zPy7dJg@B}!hD146?$tF6nJ5IJ#6|Apk}%A6mi@}!KwU(&gcbWR_dwSs$7SC>_uUT( znPraVqxpf*FlH5ZetKTCTAadK%wwS%xAbDdJYnPh{qX^PbX2`)m96msFL|iy`2Rj&VlSdrb!L z{^@(6kl{_q88)7|EzW6f=^(Rwa9*^~GbFJj6!hcyO3!4qR$86Cy0T__&C2p^4qDOW zL~U!5qpGrLoi;ls%-Q<{GwGa?Q+95^$}8S^d(s<@bYE=p`kGs-D`1Ip9!y;87~r#J zSJez%ZE^0^R$`~xY^7@5-B_`0cC?>-#Swkd=HBLDO_FW|)(Sru&lytT237$=RAsj;14{EX=GQCj_=%Ggv}q9kf4Qt2^hh#{l7M)XCOa8 zP{(R%wF6A7uUS=I0VWPMImJq2WnyK`OAgt&yQb%f1CJdDkN0`%D$%Qbj`kz}EH}9i zwsgmvsl{*B zSVH%t(L?7kI8TFC)Uq5}UzgdL=pNQ+M$B>DEywYs4#?s~f3Li_k`ub2$Kz09xfJKQ z;12~ywwtQ6=EPMOxlJWtU_@rgxtcP^#UrtZou*4htgy2)nprBIb!}XIa&^TOW_RGtz@C;`Z?~|F z?x)Hfu?;V}BgYBrg}|3ry{7P7VH2&b=?PR`SMH$ovgBjtR=?NO?iX?cej0mK8t<~R z#{}jc?2L34xpx&xA2Rd#(r?P2!pMqnz6K4?-f9=M&vHZ!3_79{j^S$IExR54e=C$) zEtrCS6Grrt9V%A)o$Kk-x*sqyns9$mJ-XU8Dl@H71)DJW65(q7yh?V-@1^MU-;dqcq~S39BcGGAa_5``YBdr$EW9&J9N*lQ4^5Atz(1B`0VVK3B!!5 z{v^j7UpF!H+0Ak{L`we=`CUgQ#bsu$YLs=y<$y;rrL({n-g{3N(w8(?ltIVO>g>%w zdcD*#Q%_yLt(ser?3f_06pgO;`vCwOo z<*F=4Sy9=cs|W?3>-a{AK7Oz3-tniN-KRPWy)->T_hznDc_IZbS^J+R*!PVZ#T z6{gD#aVO+Jp=3|5#2UV{1u}Zy$AydZe)@ zh0L(@fRFV<^uko<(20Mn`I9=!^C#8KC<0O-WJaX7_%>qxNW(m_qCIo96wpbuDGZwQn&2V;5XQN>HZ{KodR22V3|0&wci`es+g(2 zYt$$kt_LL6M(nRqyBX*@NjvqHFpUQxFsl8iKOXfiYrW+SU7pSy`wW$g4VbXP@>&>O zF9Yf}=_>m984I`5JLfYvKLqK4_pW%HUugT&r6@~n+saGWH*>@-JssYwVW4x`xKMDf zy0$vXDzz(Fo63`xo-S8*95pfvYOv^#IT4u?kXd`DwMuQurT!O`uw;Lpiw(M~p+*hc z`&x~0MF0FzOwT=$LOy5w01gn zHR*--b9`Rm#5*}}o?w=FS>Gi7b84RFDbHcgM!)2==CUTeSmBU-QI@$`+X}wGQzY?# zgr`WWf1i5q+WVdf4=fA+xlM1P7uVZGEz&j2TxxP3(e*@|CgIt+Rsy)e5S(h{7JvV^C~$=??vE05fTcXs-wB& z_j{{d%+$-B?%p_d=jx`_t7|H2Qdhr-XUw4{yLi|*IdMZx6;?XRky1xSeYi0^@#&hT z(v6P(C+Du7bNvYuBkd3ZgWH6@=kbh9MUIYOYAD@(4o{kmV_60ZRF!R3yWvehm(DIa z%FdjN3q-OcW|#hme^%C8+A1X*D{GGWH>*)B6ujeVJVyC5809f-n=wB;<=W)g)#V$j z`BuUwwY}_LG5(CIUv4cyxdM7~uzEJA18jJDNh@&f)R%YZsa^I|*hwdQDrVb{Fyc{* zO$ro>g=sOq>+|$UZKcV~)TWN0>zcPqb6%V6x2JXU-S1-QKQ##ERHytJrw#IJsm=~O zFV6T`T0LT7Y~kteoDjB7R;__hGGqUO^hspwWY_sP^j*eI+fUG?B*wya#hsTJdUIaP zw3d8yo(bCiuP54HjHhaZO|W!pju2$b2pg^{;4-$bxa1`V3w-P?E;)pq`e{Mf45nPGW*C|d3A#-dTG_Xs(l4CHkbu=c@Y_5EjgoZ+-nWkzgpm~SZ?z1uHpfBOou5C?`;vZ`6Yg?__(Vz1jEOl2ynfq4fG$*al z^r^R={Jmr3QD%v1tW?DV!m#4(scmH~6{>XL-R4mA^LVS1yhm#`<@|KwuI#&VVotn- z-KMOZ)kiB`8y)?QWR*mwOZ8I8T2nTtYxx&W8%v#O)x_*4y9LzJ{v9%6oLoaj z>=dRgYu&&51-#Q9Y_W@Ir|C7!-(HMoTJO@C{$_NYlW?9K#!Ll}0LJ~Bc;{!OOrRLz zg{9x_d(u6ZoG@r zn*_a=??;}|tslRhi@S~Z9DS{G=B2s#gl_bucVA!e{R_ILW1TJ9@QZAYfOsPt?JazP z*~?%U>kvnUkYktsErZE46o@dW0LRo@$`hSmMAa1+jO)~VuKSq z(brew%Pu|nI(zT&Z%4S2tIcQ~-3`_`G{P3XE@5^boVRi8{BJj0Vc<}AdW)N`*X-Aa zIn#1k;LVP$?z5|hWoKq@E&OMBCEoDPmI@7{2Pd4c&dJpm5f|8 zu9~$u)!gQV?fAE$;Fc>*{u57h1Yf#3?#A0r=T3)CTb;^tlu8;K^eoykw%@mU%srNG z0L%&+iiTeiT&KeO04d?lZ(@%PSVb9L@s^{ zb&IWyGvl)UUPu;Jf6X6C`=KEe478uac%$E9C@=dLYm`}=;;HQjCbY-p##vY&IcVQipyY?K_RM zvq0v1;vl`R-@FH_yDS#FnFSKxi@@)e$1oE_)l2=vek{JE2Bj5C(w*VhZnHx!HwQI?mySWmS7>8~ED>A!9P$q{178j7VSHW2364 zl*nd=tHP|atVc>FH7e$IKYHPde~e{}YLKl7tMR*1`R#de-m#YtEW~vveo=_MP!^Zq zTlm(&?V|Ye-;$Vb^B9HDuzDahc_5&cy72 zxI@og%`ESQ-{ER6vHTHU1(`xYU1;W8%$fk^KNM6krI}!$4)cW z3{qmf4)-UG*-$Y3Z7HJ(E&ZWdhj_~JZ3nXSkIn4}9=hsscQ2%0EcW7e$&TRN?S=`1 zA8~2FT(DHKOm1h^^d(lmX#L2~`u4$?r+w&2kjao4kn3aX`naNT`CM&&t4BQOIym8w zT5j50n0HZ{a$x-Xx!dvkbVo2nt#_SKJ%{S^&ZzUx9y-qs;@#14=)7n)7QK^q=)CgJ zj$m&*MOUbC!^3ghigmAdc;tKWZvR^rKp| zXem<{m_EeuQA9q9Cu6-9v5X=LFNe4L@>}~kwy7P~boaJP-YI1*5#`IqdGm%kV~s4( z(*ESQWqHeTNpEbw+4k{hkjpdqBZ8{MNKW?OU)x z?TdN7-A89yLBnQy81?lvJ+H%aSiW*hK;&?4$W3j!gr&{a5o)2xs=$|CGwfi3O*ocLvRzzF=VKet-m zIUV1kEEj1$(X|PI$!b)J`2rIhI18DD=}kW2#e%#^u9ye#n_aBCIET$+c-_Z`VzEM^%=v&S4LH zTAFuJoJ`k&S+IkTJ&ew)GT3Ew=b^Si<6uQ?vqKqZ!$)4LJ1d6;-tZ#VqO*mmF4nKO zP_Pcjvo79RIJ@YB^I><;w-NLOh}C7BV`;@+WKr^*+(vo^(esSHGhjD8B+&OKEOsel zDHFTXH!J2?yl=v`7|$$3naHmn!Wf;kSR1}epl=hr%>Fj5o4!Fle0yL=d=)U2WlV1$ zQMyPs61KOoj-oy6130sdJ?zYmvV(>S>|j&m)XDh;w6{%PX=wd*XJ2;NjfJ=e#cgh3 z=T|eoD&9Qn)J)7H4r9^uqD@7)m!B8!nYnr9S4F*MZn}T^{n)S1Ov5(>!ibJwL;F^@ zP?_qSGP`27SeXN+R19SjhL*IxCK_k`(|xK?Ff&s}u&&+eo-r;fN3K71UK}>PaJuX6@mYn~TX@8} zgr0?h^{xpk)gHss=icHTH1`m`4Wciaa9;G+7IF3|yU?bz6y!G9pK|=>WPYxAX|YAT zINDOv-h5HIwAdhBj$ zV`LMGrkXn~V~TFe?TRbPzF5!|H)iI@E~_x}rd(GRjpai{BV1Bp`ncf}@QZdEey=d6 zj$?tew)B!vdLJL{!Vdxd<_fb6cAYBSR5}RXH4SoEs|Ssv_1_>@VqyCDK+Uz_@eoV3 z2d0!>UoUok4beZp|HL!u7B6KJ8ajg0L$|s!-A9bYX_ro(P?>#JrhwH-W?@ILXL~Q~ zm9sP!c(U}(OKl6hfhDEbL-OEv>f(>^2Kbf#4pkn7RpHGw-_hD)JB>@s{WQiy`rEOY z9nD6*Av5pS(QHdlViR);@@YLr>$_B(>Ae>vw0D9kU|O%uhcqJBIGig~L;Od&@ME|` zC*cl_`{n)l@`Sngjgc-s5?m1xX@2QIFHhMf&)rQR2D?=IeY z);%R>X+wHRpY%sh*e`~Lp0t0gTX;OCB&mA+70JZX=AXid*W=kONtd3Pk}O(_cDef% z78j;J{((BuYhBnhr?@zM?%878;oi<~r4T=+%=J8eTbb@Qw?#EuE(qfE!n@t{y;Q(r zbx)gXol}M#2P=LDeY(UlhrVr#^R!v4b2dGkS7Mzr-4h9GCCdt!q|-G=AI^KsI>)&1 zFg%+UM?Pkma~d82o+%5hRA!-d&i#31YB%qk$I(l64d2eq%p=_ZeQgM{Px%Mu_2nzn zLEaD4s4Xkh!QK_>5Qxp|HCN&8_)#^PU&8r<`dfUnwC_^evi753cPcYs9>~F*Hgpoc zQs~G!s4@lTDUojMcVz8rX7?>?ePlOz(D!Gta*28dJW4Qxg>lnSp@=40o@rD^nzW%MeT$pa?L z@O>BHcLR)?zSyla6}5zk+i+$U+NaNNy~kl(C0J+|T>HfVzZs$i{MKOfUJEX7pZERt zOKr0-%I$N%$80oH2HM~tyzKJKJy=J2Fh3PP{yqIJy=9fayv8s_zg5#bOXFCZ=do8w zzgo@<;cq_ebkU!qYMseSMG zrZ{eeQ+T&@;W67NP zi%pNtS?o4Vp8e45MMaBDV`e>4^ic8aStjTF*(Gyk&Yx|Xvf%#3j}|SQZ7L`#o>%n1 zY||sN7cQE!;2~3Ijxh^oEt&Js0yf1{v~Zqt$wQ{8?l})VU@DluWRYp|n42byFl9UM zVD_v9vt~Qz7cFv|hS*AMU4KJHrj2wJW!#jRmO0Gz0JCQoEiU>wXk=#;f`-B=Ffm*X zWH9y?g!YAw;d}+c|2PAj0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hC zGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mE zI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwt zfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X z1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@N zXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5S za0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$@6|BiwD*0eE( zT4u^`eIeVBSEH`5ZBa``y`r~m=*e_l( z#03n|`g&#(_j<+(mC4mYr7%jU_`x4940vEJldsSdY| ztV7$-E?aH4@nv(nO|TZ5tm&QxNZH(^Y-wKUOktE%Y;eZzx7FFIg^|a!K3_S`OqbEK z)=qBFw_vU8OmJHEXQ3t3rs^x_OlRks^Cs%!icPNfTgD2Bo+J-5KkG2~8qClJW%!CI z)+Sh{g-d}xlGrA-^vrXpW?NFDX^yaV%Uo8T=mp2ju0$N$GFKQX+P2JWoGaQIXPV{- zBTdC8{KCeuy@fxp)Fxkizf`BRH&Dk0U1<<*@4PbVan`SexTot!{C~q54Yl1}DNlSG z7JmGw>b1|3#p5YYu)ZmaaRuX9BkK#REfVa+J5BqeszX5~WO5qnWapKxJa$W5ZP^^d zIHAJe5{iu;y~XHZmhQPjRna93)2F3)ulO2ZYtVQS!IQYxQ1|nAxOja$bhYVLg_#yy z7&FOGyWqm4N%@yUi*+u?g#$KwYrvl3o#8#1?~N^Fxt5m^-K(1 zj+UJp_vc@@YnaXXSY#+TC={McJr8x5or#uE@H9$?f`_kl_SodCI~OR`?jy8Ut<^cZ zIeWmLrnUFp>R4A!>nAze)N=));NBZ$)H;JDWR4og0>jj?mqQB^0zx!Kz@o(ZIA>U% zF88Q+ByxP%RpVCFct&e4@nSzp z0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n z8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+R zz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB__jf1iQSul)V5vQm-%Rm}e_{?N5wA>jW@EFcf^Kpn38T-iaa}z~b*Ca3|>UH1XByE2KE`$unNvN6zll&%3 zooR4B05A}~eh}pofC4Ca1Wo`fhw=m@EOH-XdZZDwBP>jKBXKKEatb_eLwSpgx^Gda zJK_=n2B0$KI~e`}@OOyP41g5uDo$Z(C`h4#c7%lqHO5Og$v4AeL6`}`^uzZumZHVc zF@oaWjFJmry#@Xe5IGy*ZYb2ft`hwbE3(cbO1#xs!h?W^u9sK^WrbEkIdju{6_@SI7AfihVC`sff-2tpndJ!-J%z`qLK!1Q`P#%To zm((zJFBCyL(xni-?Iy2+_0O=@LU7?4US(`P)C{djzlA1$1=D9x4nxAfK%dDkYDW`A zNs=U=g}DXhpCJ0%su_C(O6Rc$&hovIoC|BB#8^B8e^M>dZbVe)5cv_Bd=RElaNi6G ze-A0iFKWj$6cKc&=`hTN@Xvtg&B(b`tBH;##K@zmOr*$#CrT&~m%#QlY((ijKij&gz;xwV_Zf*$@kd9YN*egChPvQ76p6kG zCZT|JA5+U%8^TZzBD+73i1P5Kb{1^!DX`QVumPH)N5pN2zLiQy7tI1IfLR;VRZY;M zJ77X)DH1mTG240hJqVZMV44CYpFkgg5-5uyN;<%1C@&JY8Q||w>Iq~4d;~TRLX>=f z$S~9kQSJuFgOW|)0f3cImO;8bfoiF-Ou83$S2?tJtv~B1;ar#+5%o2MNrTo2tO@~l zX#pcpiF^x8K{#6=N)AAZ4#N#%c(5y&QiJ7OvqJ9f?#Tx47e3xl6It; z5N)9B_rWt6K?M}3r?^JMbsmw8b-zc^V%+fGuO*Z82%?cu0Jl(e6j`FzgG>>Vm+k%*vw1isg+O$YIYOR~A?77~$S_JK*K&^E)G)iD} z)LOT+vvq%m|6?tgH0_eWvf)d`$Puc-^$5HlrhmfwHAGni5C$uQC|-aOP=-QcpKiqk zq^!&aiLMrv7tj`YBh1s_p8|;?kMasEAX@tXnaIEv{0Nl%e&K!8CDkd^>$2kfrF*ATCi!n6Rf z4?^N!gO5gTw;Cwa7$!Ami0myOx_^YK5LF=#64@$*FNZ`&0|=Ak6r6SezY0+X0yIGR z1d@0Yz=udcedu{J0Fox+!TT9(2eqWHMZ((`rpt)`5hB|FM#7pwo?8LRp)4oh1b7=t z4MdqtWuSaZ;9h|0D8_a}lz9M0q5K14`0W5ut4(5Vs;@($hRP4YdI|1kh+GUXup6E; zkQj{JPct;e+BA+0gcYF*fUbXYASpd#;4$31u=dOz>+C$EyXlS37UTod^>LV z(U?lCX6(o$YDc<9Fy+R7L-}gqI*HgXAo4DNAEEpJ=`1xJ!2+YBR!R{fd*VWArKD)M zAX=$JC_NyoM;(Zqua%-BB@!Y8shCO~hiedm(y7#800$I1B%uVMG?b%+N#esePNszc zi!6YdmXRw_8grcVI~E3?v~CtoQz#_C-4$`eJ4q~|^4DV)BaIZjo3XVBoKKCZDx<+- zf~g2K-vLP(1P~^@tuWIcd)^9N8H>Yicy>XQsQ?F|93W5xa1zRKNbK+5VC;3|71$2S zJVHnuK)L?_vw%SpLJW%~?%zU?$PQ4@O+w-%1R05Ujkz9(jHe+Mc?3~(b3P0|&FGJ6 zL_8W#eSHLd4Zu%qfF$Z3IyT~UEZ?DgNtvsn=n^_%8i8~JA@US}bx@W;ltO@bJmE!1 z&j$gNr8s;AbQ+@k9^f*R0D%nvqhgT>(qjSo+ynEepdEWtT^>QXwHqo}1J_E#EQ82i zfEp-!Ac>m*`lApH0HqS(2&@ed7#EgJoLPC0s6JaRb3oXKA)H>RML@<+IsAAD5Gajaizo-3Ru>f(w5HurN3L8%#s`=oFY}VLtTV zT-`sqOJu1?)7gFL4Zx8%;Cw3h4opHpHwUb@05j=T7{&pCYt*$Cw%!u~$3daXK1w_Y9M%fx2lT zJA#-7iZcucszRK=0u)nkdkitg99Uz>&~q|0q)WhQi19gSA09taeWz91 zfNE)V*?H9B4qHB^xNqROikLQvOMHeJi#S|urmO*o!^>$5y`VCw>2Z;LqUF#A4d#aE z7MSRz=vs=zK7-4GIH9TlE;+oH#D<_?IwU#)K$sNQ2PZvdEyV=o4mc)2;?e+2u%@I_ z6ox00)HMC!W^sZ3&pK*Irqs>xLAAein)Tp<;_72tU&&p}eg0*LF}%2b^H2E+RhCVjbFVjGZR zs+OXHQv3_1OK>(rENuXIgVo9|j(@$Y>iD;Av|;QqiJiOAhR-R%RG5;IFybI`5x_Vo z4oJ#F0Mv%Zab60;VhEG=9F{8JI@oRJdd#t^91BZaz67G@fG z0ylIUIxVe2=0vpd0L(&_j&7a`n51Mth_VGB1xgPRVz9T?Av$UddZg@!kWyoCEMjsX zEOrb^^+gDlQPlHAlF~#$6Jahyz;sC8y8%wXOS7&r1K?>`S3}~nQIf_Jvo@orleG#} z%5zK#mpfqEil~<$F=SODQT7v{0}%YhQ`@wT)B6i4-JXI%3@~X4o+KxLQUQdj;plF^ zdY&>fGIfzQH}6nR|WTqyay%=sxd<3zW~gHG98lgA%M7Ue!s0a z>r=NK$ApDe_Pj&7o92Tzfj1+plFEGs@MkEs1l|W|fbtn6hKi(|h9yi=pTfG?at=C6 zrfgX1FyoU#q?YP?1b<7VDHZF*SO)=0l?2ce5<~GlDOFD`2fC1I`5f)DJ>H0u9tDuq&AuPJ#o=8SUc z=N(A72|z`at<;7$0s3N%Y=X$|1B`=`P2g34g;3m(7%H6d87y7=X&HA=Mw1w;WvoZo zJ5-J`HbLa&oO!rP^u}SBA*3V1^;r$jlYC41iep0oCA^$E|A$(xUfdRIMSxfMwn_)b`M1P7r=2SMk zq%+tWjl$Bov-|^?BIO@oYDf4bh|I*9xLz;{s2 z5SR`SYr(w>ktYBQgJOfkPy(eCmI*+)5an5b2cgV^418)QItA*5wNlhFs$&NXE8y`$ za91;YWj-XnJcZMe`56D`=5z<|FU0gsS;8G2IQ*Rd_E# zqTK-47F&W-ZePa6K$PVGE1{GTcn)AIl#K+cD7qhGL4fFq09|9d?@s783Cko@pzHzo zJ)+7W$~yqNpu7TMi5~;eu1*Aiav0zg%*V*Zq!*URtO~wk09agU6AetU{Sgk4-v^is zB@d!}22c)V6(r>}KvzqYbI`ZJSV@jc0OGnri%5I6N_QOp1#=T5`qiJy=#t@RMa}fs zQBbdv0)spNh$Qj?Ty#6q>*B;Jd*8grQ(s?T<uPj*Hyk~C=i|*e7KeVQ-3pPz07gT(9bzO;@8u{mzjH1TY?w*t zi8+9By-%qr#7Kph^eJpB5R40k{31=S=V7`BneL?2UjaM~Wi_PtRs>Sp`oDz(=BNTB zr35i3W~4|ay|x=S6~eY^`8rHU@c~S4p!hb*_YZ&&lq&?j1jxjiAswQe2UrH>K?0Wn zvIa6X8lp&hFi$}#g2;b{XFZg)kb!6WV=;+gB^U(h4VqlrVb}xDYZMv)XoT`PB!Tc2+$^~ z3gt2cf7%{s7;auY740D>tf7X`9%ytrMjzxCd!Y2=SZq(Za}P8VzCkzq$VB^a$IuAM zB*Y5wXDAbG0o{wJ84ztZZV{A+A#C7dV15fS3UPuo!i0)e!XWR&p&b5IRA4i}D^Ol0 zunyp_P!2(2sGw2{%hy0BAU*2=x?1u5^;Yy0B4;DB){4jsEW;sMD@;&&LpodWHnk#A zP~Ji8&#f2%e06{| zgrqM5n2GR=Wl#pK!69-w!fDHLD$F!tBk$maWV=4e_oYG&=))U`P!>~}K~NxZlqEpD z^Fp}=mYX4oly(L(P`8w40Vcva9)dqBweSfzF#<5T#Jw(bGg1p9S5W~sW9K`Yp-5lq zmLuHh&VVMXt9-_Mduov}pM|~aW zzS0CkF+4>O7QY8B8s;Fg6g9h1ejMskRsobD;&DjgI)GUSq=`>i5AY7G`yugeSZVMh z=w;Yf0aCJ*tpMV>S;^E7FLK7slf$(>G@#UH5Umg2L;02f^`RZg6-W%l_oP11pOn%= z(iEy&sOmu5JtEXz|X_=zD3DbU**#}V$0Q?KeS%|y?V8l>R4H=T2j~~}ilEzm2v|bOOsGI{^ zKAaOE@+g4&q0EA?Aq7AeV>*{b@kP4B6uttspb^T~ zkc6u-H#(w7RoXp@Ux^lnVH%49N3>#K1E^PLQG=0M%%pxerouT(>*VWL8_8o}x{7=% zM4mwYVF-uF(*T}=vWmb6fZb4bL9`zKCbp}`3wlqZJk;aA!TDE+*5j|BoQANzvr%>< zuH|CHDRTi@VGfW>w;Je?SnMePtcBb56bymWW!@(-q+qAZoUjpb!k zIDZDiCy<0Uk(VgMTu93#TI~G}V6t!%_@#=oP@R#AU|YYZ$lgW#IP_MissN?RKA6rS z&-W0++uQJF0>8laB0~39$%~MFe}$FBkY(r*QdziNIRhnxBJGeKx4#O$Pz*n2;z;96 zI4bErr*7uK)n_-ysVX_V;Ge^F6p9DQPu)iKB6W-lpz4K zp%hcGq>(i^#$h~D{Ao#XQ~V4Vm%;rzh+F{hJd_Fo*#Nts?1ZGa0mOCV6X?e)dNk1U zZ{7I*Rp=_sd|K|b>$$&`ln<`wejlalDIMkh0?Kg$l>1*$njklF(@$K#lDo$vyD+%n z>pT`v>my`cA*~?G;F3nb08!QgBthv3N!bh_uFFn-uNpMdmHPlIh<^fP!aEcqe-7Y+ zGM2z$fCr(>gTzpL%8#&6kKaViopV2Wtc{d)*)&o{QiEd0pqgP-sfHxaK}D%l_!wIF3cyFOeh86Y1o#@tmju@Q5|jd5 zParS(g(rqGrBuU0ZU4)!Gm6&ge!y6K4{oe`Sg&-nsTqb=RCEy%?%auqT%(+hcqe2+ z4_PNqfjJzvhz_C@0`!5>i@<{bw?MfWqFV}Z4CQ*DoSt$&4#Pxv#zVCJ7Eph0!_E)& z*A46a5UsyYLV1D!^>+i5^#rKDJE6QvfckqqEQT`O=z*&kbpGo0Cgq< z^fbd{z8Q=_}lV=D6wNR9rE6AIu*3=R;y>0!TRk%k|F#K83EF!eJBK8zDXYWNF3W4WQi+Mc9o& z2IU|``$k}kR*MO_gnS{F5vYA9(D~zZEWMF@ zucfk6s=EZ;aY{w+B@wrvi4g7mWH^*z1nA9R5|jx9=*{49D33v6?m`0X&0r(YdPvus zLBe~;Pp`BzZ7-#18=q73*U|brs_W7w(Wk=C;_A>kL&y=6;;=L|(pSPP_8r`OpKBM+ zLoJ*r#_bx6s!ziFS5$HcB7XvK3d#vc423D*!_o?L5z?~-Kw+H zP=AOr0ALK1Q4sB8g0E4hz~~r7je0>ytV5%;j|m<^%zTLUF+mxWQb^~=1Q)bU(9uAp z{vb##REj<(*o>e`Dn%a?)Iiy*m7;e@Js9dd>Z#NwAt?!c{Lkw&SG!L1(TVV~p!*%M zK-cLrq&ZA^={-_~a+v^Kr-V`HE=0RdW1!ql21=k^r`bUFL9Sn?j2qXfKwkImGTL-e zq7rfQ{n{lPNb}$hYRgnnvEq)@=7#l1w-%z!4LhLxi2%(F??HK&0L=|Yq4)^U+;BZC zhO*t58$JMqzcx1{RKY=?+t7OvPSmzR2)3a_Gu(KGWLYWtpQq~}@( zl&b{jxfXvL1{vhWbL}RS|CO3!XJLkL!iO1zy8WXR{w}RUABH&tu94gqa~+X6s~Yvm&t z9)fE=xs%#KKW&H#M{QE~yUKnX%peoMu#uK*~)t77L0AnrFP4AE8qgP;r`Kr4V5P^Lp-0*Jr9 z0*L$(4W;XM-%zcwzgYJq{07bYpDqs2hxiX;F{1QPXoaYK=s1Ah5w{|hkzNLwc?&+B z(f7n8t3wm3QnKLq3rxn{IK=%82l^5^j}`--cBg5LOQ>Xya|N`Mn{^qV|NJM zODP3?ANd}F-i2u2M;?XpKRA02@T!U}?t8b%$;rvdISEN92@oLEgep>`NEZ>2qKFlw zsYnw+0SjQ^+Qr_mcfBGO?7d>g3YKf{yt(jR< zc0I3aYHQ?im-@_On64$l5*wo!nJP*vVTq=I`(=B&Q zOudMi=bfpCk?=ho)jKj(fn3FUfd9KGiCa@;Zx0JRRwPvXKoc~|1i1n3xpJN=fO6U0G@{Rq}W!+ zXxQ=7VvQCCM&|*|q{B-!8P16;O#buI2xXfCd_=kTNTw4+NNf3|%G>BIiTd^!QJ~Sv zpt+$?^a!jbk|BBJry^vpB2xG}i_9S+${|i7 zvw~!8&a9U2I!3bDK5V(f*}M*!Ye-(@gi)xlf;w8k4q?lyB{&_{0|?zG!LkKVbFHA> zIB3){Z263YmH}@-;3WyAdg8;s5fah4H}hd%fZ*&==@A2ChHu#@@EY|GTSj{We~R$O zq-Z+CpJaX~nZqG+!|8vLIS!&Dnf4@HIUTZ~xf=9JxiT^=ZAUvr7XuGNVh}019^w!( zGfAZqGk1a<3w1QfJPL6kne$0)>aJx3ppQrAq;H@x(Qu%(@Yax`J`m54d4g0b5i=g- zYp5?tW->&{2vm@2XG8pe$S2g^%z@|vT2JyaWtd=2@&1OzfVGe0jth>4QwvAeFv_S# z%<(EFf_>vR(DJVACA_`}oHqv2IJ#R{dZsG=4)6p_j3Y%~K+GmHi&QEx^9#rdsAVJ* zaKHLeG8dC7u0_{(*xk+>f(lEk*xbl)Z!GWiD#sd3r$g`NZ)> zMDa@cUr}74vSLd6B97y@t*Twa*<-27H@kDmkJ4OzR#h$wGL`Juqu+s_L-l&8Pwhsq ze}@q5>2-r$Jr;m)@@mf|(}#ll3%w{tE4-!+SBu;wfKg~UP;6LN(wb8S&<4{0KE%NL zq}urqW6|WZFEooFeg)l3DhsdYKsf?QF5VO5e$WOx51ieF1%Om4j%g0EBUBx!wgbd+ zQ0>f3M~I_Ak0Q0X9`sW`PHd%~o&GdGsSE=(av5Y-h zfn{NnizQ&s!rJH^O+BmTd-uxe6T)iyg627BKa*r%(7cPxT9W={njoxLeh(dS&wCZU zz+5a7BE-fZ5KZlggxBVZq3jO;nN6_M=*b`#Jp}Y7YG0L|wGh9P*-R>xNaN=~%tj6^ zcBLXD^9jU6GUEmG;aN~AjE^$fXhFE=5%hAik+8f*5$nYlX^I&#CsX7&k|~3Dfy{al zEg`-k^OcBt2tz#m1Ce?NVk+9Tz`m@=c^IH4+#V#ab~04H2qOx&=@4UpN0ZFq5HrXe zL`t0vQPa%xYADmKKiqQw{srd*Qj^OPF5}5FmqXkDdL0R~Ygz@~AWHHYVi9H@2-BZY zKDr6)-1T{7Mi5~U*Vy4G( zVGT3H(d5VL>3FY6UurxFChmD=AjD0myn$5Jo;7C>aHD^P`KS-X!=Mk6N`;!?+aQ$H zzp{IV1m4XkL!}D79%QNp(Gcr_-=W|ur05NZHf+VJNTm`pAAuYWbpXkH5AhF~?@3Kx zVBub4^`Y&hu!C648Rc81|78sojFg`55ZJrr-EP z?-{_Sk&5;sM7L0wQ$~Bl%Eqv(S9=yhCsSgIO00so0qN^VnS!c#@|y@p?a3@#uE!4B z9fFcn3q%W{)Qe}RY#V?FDR)1qaW{zaa@akr@a~X$sIoP}A4_;Vz#9m@Ofr)p%oqk1 z$&RvGM5&BD;%5}Kd5c2vC@b#?JWyJj97DN*P{%`<6%bV@Xi92x4iA5e!^Ei0sfv0; zYk+#g+kq5a4KbO_-lS5AnEOF4g*u;PBL$3-Yz&xie1Y9)o3LqTiH!F-!PCFgeXL34%mL#eUK)hfhXH!+ zL1&T7^AP)x*^6X%eG>I;frtW){t2q)QOE|~5@e1d#ar8nR`6c6cv+Y|PeNMU&qCk~ z38glndI~}X5NlvpzXhPxx4a#wUE+I@*>;JK7x&D*tl1N(*te8w7~A&s5rt*NjWp0> z&12TtW7}m~FfO$$)V{%PaRUy0GlZJG4RJe;TthOSLo{RGP)IVHA?_q|1F38VJBBSN zW8bK%v<@=+QaU;VI5Q4mQgksyKQg^VtbmwCW*-rYAZ{dcEvfb%hz=QoXfWj-gm?k; zX;S$hD)e1IY|O=1-41&ek#-M|!EyT(j|p|A1$CEBwGoKD-K{tk(j%xG8&nq4e=T*K{0`&QR^Fm>Cm-GAC9ZCa)c{*yS$ z`@mGKQInw6GD_Ob{U22AH&VR0e@?aWrbwu1(CS(VX>(sf+!ZVK8u^?*E{1IaGHroc zky1H`%Q0Jm$XgULd4St*fn%nIq&dAPhMQPv9W8uz5xbHwY9@^_ zw0%kc`(`2oB=ZMpfw@x3w72uutjnOcaY zWEP0%4)F+?2T0{VQ7R}Svn9!7iaC!M--ss&(2|U=@;umsSS+t3Be%+H$f%9H@J`pCcpD;%mno9@9AYOjy+mw=m`P?Tsq7?N9Ao=5 zU(Cw3EImS}htc`K7r;M{S{6Xetk{9-eT1e3wZBd_difDJB zc6-s~q-bA=kz|I6I2d9cnL|m{3n6%rq;>^=yHU5tFl&y7xEk(7B(G9$J*`1GO9jVr zpr(;Y|0e(R>eCkpeL}LYK9x*l7?C(vL{=T?g;QzCi>T^i2)@&z6P|fMLlGN5sy+t7 z-^-lBpTnW&k<0}U=a4y(RH@d#90k5T7RZ5z(<2U3E!6{GBJ(-PtG$L&BdLVWxy-c? z-rnr8U}YYrxLWiYIO-C;usP1}sl~XPmwgVdI?OAV8TDcLjbzkceLo=65#%jfa$Hb2 zNYnKKM1F#!kjq9jNk4|ap2j;X%shk8<*)9|JQk&B%UaxMLCTdw@ThPr{!D}(OEO&` zR+2fMR6d5n3T!W2gR1?Z)W81flcnkrpqr4ojugEB@e-NmNY!sa1ZOX7@)>{UQ%Li# z`5fXmxZjgdxCC-7JWag*>W8FoB~TB>cNbE0F2vqsCXjMhLTC~?=u`$Wg$}WW{#Ky{ zK*u1nnACb1gjan!N6eT1jiepCg-ptE=MO^BNT{8xf>SubipBw5PT@;P=0J$&$UG?G zFo@RsFdj&mv6PaRqbZY&`^qwiOgpr~<*eRt6k5wHCwa2iAL*4Zg%M8-FY&xm zzQ*(VTUQE4G36DW5_(ezn2L6OQLZUOLHNnZyl4;&BHs@$b|ghRKpaPADJj>^O1)Qz zRH=$q@4mHI>wU?4E&5cgNHrl=e*rqyV}=&!yP^HCF^>rr|o$+U%do6M^s zdO(!!i#bx}N=oTc>U7Fjo&A$rHSvRm1HH`kNT{tA#}ZnMGi$&Uf#)}1w3R7dbrs_% zb2m&i*BZ;*rnw%35jWQ*bSh6()=aVf9=03)-U8GCk7`NLy%3|wj1ch@#5^*Gk<6`8it`3r0Cxe{aF|KkfM7bR**S>RQn{v zVtTXvXuNz1qEgSr6|~Y`Lq~0aD%<;QE8sWNgKzdxxM>HlWhB{$9a) zq}0O@cc7#mB|6`1{0P8K2eX3{s@+aSf8SJ|%LCeX0r1TmjvWLK^m7kUAi5S-(PYjQ zNYTR(wPae0xE-QDnLZ@*Jj84=vqWrySV`tYQln2H)>Ciu6`9LHE+JLCiyaNfh5@U9 z(w10V-^vH*%z3~EPGQ`TY=4Lwz^&Nd4{ZfUI^aM* zEPH^@gN+B^Uly5zebZ5Xz5smG6wg~kDiz1PwGCoEgE$-3S)}r*(ub$z3zH04*|1F` z-P<=!`SKc;;vDHzGCIMWjYYak&zjn^O#7-u=JAAkO3c+6oK8V4vwQ>0x}g|)J5iST zhKxqxGY#UlzxY;FO*~TDt!tN*ZqW;;^k`&a6xe4T>&84Z*3)crBY&bYpj)P}LX)DF z5dR^wQA9mN?jX8=)VME%8Np#VR6mlL0I`zHiKGmlma=o=2vjC>VrC+kHUWnu*pYC? zMMrr9+RD=flsXUz&G#oYlu~7iyV?1ECQQwjms{pIyZ;%l<#9HQc)nl5+O-^t$fY`S z$KmuNK$qds#iZy3h)2jgAmS~EPsn^gGM_<|P9>xCGsFR8_9JCZN1tZ*Jla%~qiFpr z6N{O<$Y@#9={rml?zG*qHpt6tKtffT)KGkDl`42D^M95ABwOvej;BvrqcE*nd^HW* z!yb$w?#B_7JOsM`o&>1!W-P3QI69wHxj$ciyO*N8;=r+)&oqAVRM zm6uK6ML^g*OTlqDP~m;PDW$`zZ-T}9$c@+WxArj(SK`!pQt>pz2^3#OYP133UO46z zGS`D#O)~$1c!|t<5|#cMasxuQsrU~Nsp(w(7ccc+sQ0if2VW9<3&1Y0cP4q6rLa`T zk6@|t)G>1=m;%|yO<`xxra_XoKKgqV(&n0A2gJW<6N|UC;^TCBSiTudYeu=+ThWqH zBgxQiiBdJD+GHC|JiW&yh|PeJeR(lG)RgKa#(uj3AHuw5#*tY*o%OoDs&3C@m3o*XzsL3q{7h*x|n1Ow;)qZYOKN)#cg?(%-DwH0$69PGK8To~;EdM^TZlL{+;=W!F5;Z~7T!l*syOR!%cMLi+DAoH1s!4R&n83Pf_WE8+@ zydOm4Lv&cA!|^(trNe3tY1!GSt-R8)h`+g|yeKZ+^=RlsY9_1Jz%ZyGq{cE}qTuo~ zrZA83a2zC$4BsK#8~8K?P9a6pA+95H4apo1@d%lRL>ve47MYDAPJ{TK%(o&gf=C@o zM(H|;He{NMxC3G@GUG_qk3cY!nHTtbB)~#a>MaO)vjzu8>OA#5fHUEoN^1Jyl9(H* zy01jWAkp|IK(Fc39IvOKV|9QPy#{z21#cyJog^~4-BuCHehStTVtZv>F*O@LG0&i_ zYG%wFDd`XVHWHg8Ra-_A&WC-CoNElR8Tcns#myAe7cVqHvn~9Y$==xS5zu|-!P6VZ zFH;JBShU+{&EW0}bKAasoOu;leeqy(EQ_vqvTqkmmqvZ3z{|Xy2sI@ZV}laH>^4Fb zA0AKe0qBj2O<}#xzvqCqM4~yVR1C8eq#smoTP}YHo5yYx<4bue_D(o| ze~K*uoq@nKQnV6c8JS~ArIIq|f?Nu9A<0|`@f4XSNa?93a#Co$(D7!xX?izRJ_7h1 z_;0Dea)>|3{4C-Oh#s>EMv}P%VmXE>3~y7R?iYLN0IEm{HB$m_mx#u$O%)$yW#!v?Mu)zkvW}IDu($LEfnywC^<0)fQeoE) zu>>wAa?LLZqd}m(VD}_3`Zr+aA`HAhaq|kqMDQ`BM(;wbg=79h=4_BNNU5(NdZMm` z!uPAp*8sP}xsBvibb+NCTpFN9%0SuIH}D8pCuP^G9@qQfB31r(;O8mwEU8o+V{YWp zMX2{l9e-HMqo|<%vq3mm@`bna1`C`&NYNI!rSn(>Nu?4q<*?gBwIvb71JJ&2ow7O> z@z?*G_jX1B?~KF%l6^aEFESHs5ig@g(w6i>%;En3;ceyCNX$iIjgz=iH#sW~!NfPL zH59V9={3rZP7f&vLvl{VBRQ?)>yUE-oVlBiAWS%3Lhaf&7 z^MQ!xAWG)rJ*h&2Kxh57eKls7<9*!{)`^bYPHn~!#uZ2H04g31T24W|wo|nzXif6+ zAM5i<9p&Ifd1M|BFFlBGU;idw!vl?v-RO|UOpWPX5HKxRIv z@fH|7u zz4VW-F*(8a?Qww=rP=)a4crrn9;7J4M~udh8BH=xAPyljla$FbL>m)S|H5#5A;+tz zPOyZQm6p2SI|`i53`hA=@pMt%ZiFqWckwHp4c?Id>a}B0el*D|n90<5jFr)mA>>uO zlv>H2B3c0FTx8BBnd2aCA#;<6Qz0HD^RS2uwjokiL+Aq;j0S?hj{QalNj; zVdrkgKG5`5%SHHlIP7^6>95Pe_ahNNR7?x|>u&pluEg}P|98-jI(kO9!)W9;IC@SP z?F0QUG@WD(X0#d6ymJ$l?A)foy4}>18ANG)EbX~iBuKB;rY*g^UEApdVjr(UK_UUo zUFplkEUa-%ylk(}V*NqkX8PEb*Ir+_Dx_#LeZk6WuW$1xD4XfCIbO|<8$&P#f1NOW zWX-E?#KkKUE@lf^J-LRHyl_fA=yIE#uIyDdJ4@NjITG-=x>w!UX7kFnvDu!=c8vwD zCfhF-P<9ua9i;38n;oX?WSbqS>|r)LTG^v)c8anm*z9y=&$8J=l)cnuXDfSy%`R8= zPMck&>?1b&sIt%7?32oFwAuB_er&TZDEr<5E?0+xXvpfP`YT(_J+|uOXc!YNWSyx# zqf*(Poe`K+#$**P@1iW@(uC&;Er^@%Qe+S2PFs9Iv3eobZzy&O=!d03b?>hF+c?Xt zUHym6zAJPx7t~ESmg~ROlXh2D9{{KxQ>|im@%_5$l{Pz;2fC_f+3XMUp@+@xFCTub zlI(J2`&$iqcBpznTp^*$Hp`v0DmI~)vfbp_mQ~6w7W$6Ob`ZK_rO;!f;UC*N_e#T# zwwkmPckiv<)e=}~vs%Qf-?!N&s?e)8%Nxlx)je$XT~+8to9!d?cH5})6>_KArXDSH zfz9fRebu)-pqRW!=*3o6*JP@%v)Mr^R%-j=TA{{fwG>uQw^@Dft$M!A>cpsey6r5T zzE{t;**-!~yGADT{#kX8yOjL^f%e*X?0ztkYpvvLB)#_9QOpteyah+9_$HhE0IS}B zqb^_6bxdZ(j_7*O>=}!@OkJ>O`rH`{x(=H+ZPA<=a~B@bb(cdIj$Aag z>)-{`7aclx-q3jqW^`UKWA2P24mzUijKvEV@MqznbC)bSVrthT7EJ3pf8K(H2Th$l zqpOoy0H;US>C>i9wz)3Tya5%LH=4g--n1D<95H$Rq4Q^So4k1Dj0N6++~rw`)U+B< zGiI;RqrHKX80SiDTBQe0=C4wlmTA2cW#1sEIidN$iR6`Pj%_h8#b2eGlba9ZkNwxC zV|w7zK9__^H5WA+$dw#Vsm0|5181U7sdiAc_sl5Gzf(hw{z|ao5!^V@PY<;p%e)$y zL+38!E=EB*!#*Q0H!wTecMAOuO=K#J%-vc36q?)l6WzClNw7;3+TJsxITUa$!z)lO z^b1p{h(E*Kz3C~Em@DQ|9h3`$)Pyt=lh>l7XVY6Gu}aLO8C8q$5sAkvL7=cgA|fT!>ZjM*BDbT2JyfE3uz!%m=4ca_zKQ1Ksj(8zTkb_) z0Rr2G`p-$YIxpd`XmCG$Y_Z(94kS#^uAxflMlET9^oQ6gNY_%oRQhz*mBRGf z9_3tI{W1YC=9T!tr+%2mo7~P^!3nNY%gIZ4Hp!N=lh<|xCttW zjPl~}u=H1em3QBZz?@>`y~=;?fS4P%VP5JBDhK0dxTs<&?83?!bZvN~C5rGuO%@$b zwZdb=>ybw5vh+^0b>&9{MYzH$@+wc1Psdv#sQeh~;R!`@JF3(h{o#q0DDshpWxkfK=6pb_bC8WxBI24V~YjyxGjP@~G1n;G3 zYTvx->s8kN46&aj{Km6q%;m*!TOd+_DW(ShD$`FOb5O~2s^V4t#vqKQW^I+dCWXJ?HtWGFUP80!o40}Dr{WLun4J=u z@!y0W<_SMWviap4n(aA$xMv2~xT3ktj%l4}<)z7Myyy5ax&vZWdC{ZljX}1kkq{v}QhEJaAncY&QpwcwXERv?tbdwn$m!uWt z?3nO;mBf=h;*w)jazaY_9GJM4 zGbN#my^7YVpXM3eEnPV`uw0RN;*|`vH4qN50)QGS}p?&f)cOd1zA`c(|(pmeelH`lhD-bbw$mw z37z&Tri;HUDUT9tFA8gLxv73C%N*HUnwxHrhs#s)Nw!y-osg(_kGM4dN^~**QTBvz zf0f-!bv`jEOO4DaDd|+%v&^q5`;7ct6_*Y1bDrAooTUBek98}d&rN9j{ze|0m(cjV zkNWHUgr+~9tbx8Dq3MqWG_kobp$oi<@0f1PMG0-ZiXG(D#R*L-rgyCm@`+#G&Jw&`Fs*DZ}#!)q=L()D<%komRg-C{ivd-RNKKiS~X zbLn~{D%)r*JfC>9Lc|MOJ$fd!i?pnfmi4hmQY()hGY62%%KM{lMs5$jHw*cf{>p1IU)YVhd2^utJ0c9z8ZiAVpS-+ZvuqjyqoNy{rW!0*N$ zNv%A3!+cLJF9*E5G+B>c4U5p%RK09oi#?JC^~slJA*_mz*qfNI8hX59;7-urB+)~3 zUaq3wC3MPbvHOs{xw;n9LFBa zcWWzmoMsx&Pss_dC@?ACoPsp)uRM!5eoXI)~_G7(j z&|TsHe$>h~N6rCk&}@6;9e@WVT&m{l19*_ruk0D)$8MHu=#}!LlyKx`W8eHCH*KRd z@f%ttV_T(J0{Fc8W1FSQnZTxPmud&ZHp~661#y`xQ_EB&HubSL)7($V8`*5*8$Co4 zH%)D#prL8nIgPGqIwU|t({ywau4y_sz%@;s16uX6+`%_G--w&0=l?cMum5eD-p+(;nm!JQZFcj+zNpKcA~W3+o9nS<`uZt(Bbz(> z<^|cT)LJ#zDM)#l0qVCQ4&aoc85>bE)B%PMwyMZ52M|U*Br)6pwAGb_rWxS?x^zEP ze-{Vf_hji9>44bp{(ktQ{GKh|fW+^18biDKDb+}R@8O&4b>cK#^Y>V%Am?S?)bcpq z0U16?tzekofFduGm79AyAnj#RoQ;`@4xsLX6ij2l^@1Sv8yC8{H7el&bnOodRmcl`A$Z z4k+<5Cuqey!~t0z!;{TJ9l+2(4xMI}189t?j0kg>189sl)ULA~Kx6b)>&$ULp_kc5 ztuxmFv`#38=Q#i$82VHFQ0Kk5zM9#mB{h3Nf`|Jl)mb$=$~XI>EYnA=$**o{Nez5z zwugdpi36zF`3jt+4xnaLa`R{hP_tdttH(Hin(e7RJJtcztiQtkI0sO(E((=p4xnbC zx?#Bks98=E^9l#VHCyP1%Wyh3OQE|cso4zeVo&f>s=}7=x&x@$_bPIR1E|^8>Y_6pK+PVNS7$kZn$>frXI43Yn!T(pI@Au$s5_^XF~U&RWkZbJ9D#B zKx-bW=(@!LwC3+}{ZX!u z#DmHvCVM~#5j96)2}?ApBH0O}smz~)T{Q1=5B2%8*0RadF*Z#jUfj#B%* z;{a;*f*gC-0ddWq_e1r5Zj1E4kksrM_1=H{lKN_n89- zzNghApF4nl-=uN*g#+mKBQ(){=>QtT*EIH(189uLG-$qd0FCjb`s^DA5E%>AI^Q~g z*7-<%_MHRbq5PpA)>4n$+v0tc)J#9EX@2lis^e2x9}b{q*Gcc64xnatYnu441E|?jZ)GVzA{o4W5Y?NZ^9|usg zDQZwJNY;h8W?X~&TQ%#f8FzD1vyXM676d8PSv4!Zu?GfN86P60KmM!*y~fSTzu zS0>{CYWAlFO|b*0*%Zz5SqD%v{fe$BaR4>@NIjBs05v;G?&KXn%_gXIN*zGWisVO` z1LB&QAl!sExvy&A6$J5axvg}U2PxHAHER}_N`fe}L4i{h#JlATqkoJ{G$xNZ5gCwTqfEE<`9{9Sti;gCNzz$Q~Y$;USsPZJVP3v zk;XQO#&y!zF-XalGG-?}xkM%+LzBF3l&WXk)8t^@X zlx#_3zrYluEc2PVuYaPTke2ooR0A9k*Sb#-c1Jk(s9L0NqVYqG`GG-7wxn@bV0M?r z8`Lv=wR9=4e%nAU4GzKuQm}@D8ImaIt-(DaNJ+I6j1J71Qt*`Kx81i_uxk+BDFqiR zmPWZcDcr{dDXEr%Jp=Qy6wFdx_u5{;xFFmt1qUeV$0rK*(5Rdkq@-F3_76-CqM+rl zUB|P5OceM;>`$75r#OIC`awP(6X1OyPS9N|6>T@EwJx2sQV_l&1(vrmQP4<{a9WVEUn)VtIf2=m0LTnd=$*S&LEPi# zIUik*U*G`O;}<%Bmbh0_<3$c&P3ErWnNTw-K1_x%arGm%m2yBPn{SfM3sU83<+wbz3|O17l&@xb&UAmc!OB2l0~wsHHEix(HS zPdmWH?K94%i`(@Mptru%sCm`_^w!4;!si^ImQZiK;FP*Re$hz~$P4Hm^OBQrf&8)q zs6|Pcc_auApcc8!Quk=kc#epBHPALNQ}NfUS;|3htNX|la!yOWM(uO_R*?31J234S zv6(Crta-=z!5aLlCZBg5Km*OAPt1QDKp)(u*nH0ctiiwP6zF{i5Z~V_Kt6B)ZCaz1 zdg?#3Y84IgudYKGdBbZl2e>1RPo)ltWO7np-pk;$5` zzjr3+5F+F2AUs_P9;$)&O`_m^MaGXoN~)#ckHFj~1vjZp|JupHfi%9i(JS8ck@bv6z{xW=MtcVii#9=^Ao{3BZDyDW?)9odA)BTsixU za4@BF!&K2QY&=dxH_bJfFf|b(?qk8WkJDTTB3~oFW^M(GA|CrN>i{yf@~=_YbhXEA zF25ybqyowv(89}Hp%$)iKy%hv0hJD*vq~b93&Xcjm-|Dt$cOeiZf=AIU6U{+%c^_J z(ELg^lM~)5shJ-)UUe8&5j(k4G?_FH<1N&s5^NKuq*@C20h-C| z?k@!+nX*m$M8R1grgNB*YANU$n(xVGCJEosDIl`%Qi%0(0FnJ~Oq$*fAhJIc(8mEp z_6Z8Az78O=Kh-JiP7WZlN5~2v)?9{h-LlK{RZk6YKpe>3!?3(He&44q?UDE$X-w=K zrc@*OJt8zGA(Yvq=H11az;Au@$c#*Y05=~}MRs)(xM@#VM$xP z@kt3z4^y%wjk7{?nKbGmh&jypNW1JLKjt`qX85TFV6L;tG<=w5yZH`49X1aR!^dTF znS>8XZ0@5LJv>aw8`)eEn%1@0>@T6Ei2|)BT{Uu!b^uOXuBq-=XM)aoLS7x00P38# zG=DBjfH3ZyBg1eP^yj{i@KK2qt=Z?96=6#5$%%i3<^qITP8heBXHE{AY3>hnpQzlXce??u@hKDcIDiniz6Rhv2jD~t z1?K$@z=_V90UvZR!K`tshV(-Yh-ZyE!f+G@bBAi6+?jO8k12>p!j$}#S5JlJD0wwO zE%CHdfL9$gy*%Rp>=D_Ihv8~zY%B9mBpUY<@oboqEw%nDp&8U3jpt~Qc-6HntHwFn zD!k?ZRt^0IuzAA))huV~$TuBOMU;*0#>(v)I|r~kz*`QWt$tT{z2gAd>LYdfyAGhO zBK5<24v0JK#W0+KkGVqDJo9px(#n>5LN)#XBB{t{p=s8Eiu_ps{<-sticD7jeBl5p zGE9y7l>-R0o@$e?9YCP9Qy+Zm00QlEZC}54UeVsisRw^>05$8RQT>wxs9BYY{OkZ~ z)=0oF4v1^^aTxB5)43`c{3Hp*cSZabrc`IIbzx-oN$Up^^Lh}&%j*$`Ag_lNqP!j( zD9GzPs<3jU9Js7XD^pQk_tlFl|5D@LV4;%AMQVl{t26}jdEMGB&+B$_le})>R_AqJ zwkEGTqOFVXQ+ouym95R|zGa8JZVPtG>qcFDUiZPeaOGcye zy1X(vuPY#9^15m&xchnBRbn}qbbOX+Gqf?MAj%shr+QtUcUXK@HYbf z=TLJGgI%p|1$j|YKMiV2uW%sW4?0{01z66dj#J_loFWq-A~tbW=#K$ zOzKU)tRI9|{4=ttjegl6s6oXC(59(PF>iVCu>sUuG4IjZB@CO?+etaUR+B;Mour^& zo5ioxyGcpER*%f2{*x5-Yu98T-%H8{wR(Id^?p(|sMP>ZeUOw5YCDVjVNy2eu>&9Y)@o)+ee9R%hcthPYX1=ViC?DH=U$NQ1=Y;&$IbrTB)NPI+UL+sA0NDedND`YJz}e9i0)BA-3*Yquesur~$gKi?a{vp-T>^f0KvQ-N0{(CSE6U>n{&YZN zE}#kcuLCOCx-jYsw>Y4JyG~3*g?~GsoO@dWybeiS8gZ*uK;VEfFSECR$N{CSjsglC zkoPj0TM7#uz{<8*5=9PRWm_(w*a4i7bWo8J2eAK~E+Fp!ZNmhVIe@iqp@4D+=qihV zN(Zn_ezpdni38Xpy(OTT1GvhfUlT5@b^xc-=L=}z0Cv{Tg#a}UV84Gpt7Kto2XNWt zTS?S9fXgnw2x#X3VxlA}{HDEmolwc`%Fv3Z+ALt91Bj>p3RvU-;wfOkDLm2v#8XX#CHUTF)fOxt`z^M)(o*of!x&w%(gR%f;I)HdORKO|+5Ko5-IL86R(-Hya zIe>UtA>aZB5KpHFxX1y-)7b(paRBjjv4GVMAfB!gaJd7Br<(*^=>XzMpJOPz+5yDV zMFOsMKpaoAI+%roN^T#;)9fUk=CNxoyuL$5k*0XMwL|)fUWzAm+igyP;z__-2PmEd z-0lFylYl!Mpm-8+rvnsE0`78v;;9;7odXn40`7Kz;z__g4p2M^xYq&1)72VW_c?%g z+LN6{;R6m(JPCNn0mRdE0gpIh@&aRBjjxq$Z_Ks>$5_OkFp2M|wh3;5UpaXj7B!8}Q* z1nG_WM4>)1&IPA3E5rn%zG=Bj85|5Kp?RQ}~kuh^IFM z{OkbY>0JSv9Y8#NEZ`Rh5KmtT_|*Z#(~kmva{%%5yMW&vKs@~;;1357Pwmv?e>#A8 zdWloY!YvLUp57Gjw*!c$_XKzylgbfK*Q-GT2M|vW2#6d&JZ%tA-~i(3FXZVsURj?&Jn zy8~#y_MDa%?%)9Go{9i^CIIK+T>L8R*fD*voOq1$k;1x;)k}eMOB5qJcFf5=?exCr zVAharuE=gKcf6wV!mrw=Helnu4s9(A>{K_(CpKQ?`!qn&fJ_ha zkr#DiPg^uFkeV9F4kOijoo}QKigvH+3soLvMuhr>p%ydda|%!*Em2_;uf@!nUS?!W z`WPrL&J0f9hFs&Ri{K0`*<{UaBycjrvU63c^78v3hFhW_KNeYDI@7P)XLhp|$}h@{ zO}__R$-~xOW_(_Gud(b-$b3hBu~#Dt%Gy)5v{y4)iu)zBpPa}=zp&6{_6#3Du**k; ze`aDM2_Pw~XE*uj{Ka{B&4wGyHCPvkRhyY;?bw*($R> z%!||G&?CBO`)^;l+TnO1M{vO{DnAiPe(hln4;w}0kCGSOJStId_3SZs5sXezr5OAx zjb5+gs|bULAimpN;P-bX*M$1n8n2t)dV{mWR{LwiQfq(O!UbOD_OMcA6213_)}Yib zrEu5JrS_VzVAlq<*M!Zts=X%cETV_ibX}~e$NWR5Gj7AO>*07i{#uEK3&H{orF9Kj zE(lv~)p9}DT|_U%!Uf?7E7hXP7Mq|hk6Z1Mq}A~GvanF{ZQ($EFo-{E>8&CmM6q*>2+<+ z{vtCkEO@BF(7d?mdK}6IFf6t)(cSj(Lf3aY)~MII#dV)E(AB+LQuh|kEO)Rtv4=fl z4`VeuCVp6Vdu{7(@0jSWSA#Qs63(3Y1m{i(VJk8;A#6qVOoC$C%!4_xcmCRb8@9FI zuHv#!*8`bwGHt_xOBy_G8@FjM-p+*4Nqz2heT>N_(=sf0yg{sGEEdo6w2%+o=^4GpZPgT`CE zT_4yfqi6TqTOjvp5Wm9d^`47+2FB?pQgFXuJxG#n#)v*)% zu%Jw3;*m5wu*0hR7cZl2L|~@}W&+Lgy>Hjr&@0I120IJAf(~12*e6kHi}sC+_Uvv= z^a~ov1a}0=*j{JqgRDYup7hv>ygsP6Q~Xt$tm=bas&YKv)(5-ELN`0L)Cc=+5@Dy7 z`rt54Ej{e;>Jq!{_4!- zlV`S1KJ%@wNgRFeCvjBsA)=D9i+7nbnWQWm%ezC;78hJX1oHZYMeL6Kk$*Q;+?w2AP zFsu9yYKAzpSNXkdXxnO?jFv$wT8Cy5c;(MN7;Z1J|nmN;W)X+|3r8#}MT z*eJiFjKv)`I_|I@wr0C;tACF~rLEc6ZHZhJxz%}$nI%oJz<5$TcLk6ZI<{4DR8>)`v3&*Lh7pv-8YITi@zHYw^~I^XlsN1 zo%$W6C1y+ZZ;1XjuC{cOivzH=Ww1>3x2CpCkfr|C(w3<*)WsV5Ya2V>wsykAPQQoP z$7X)WjvL_&{9q@d0XEWp=%YZ3P5dxgCI;AW{9!)@6(5=7VLNT51}>Pvn*UpcwBY(A zj{Ul5XR;xCZ-e3uc3y}TZ|J*K@rK>ED&DZa6n9xtMcLQw3N&!$%s!l=Th(1^Xtd0S zWzvb6sWNkB0nk(BA2*nJs+VmbJM}#^TkNd2EqG#O3>Rm5cA(vngmZ2)6O#g?xiT{Z?|Rt-o<)v`)Q4xZwA`A|28`T_Z(<< zf_K<$_dx64oyit_=kW&B*VJh0y|2OUHGQ`_c+E(u9%z^2>#8K@?OfTELYG*7K58g* ziFI~>Re#CQxK@ABMVX^ZMf4kqvvyZ^bgk$eN&p73j4#W_t9XlqJ}IHQB=pHK-BYq> z#(8hh{!KUun%Sve4^E$o4(hbOl&e*W4jQIb@%kOi9;WDkPKz2C2MmoFS$eW)&ra7j zF!mg7+p(F&$7}KJa?H=j>=mC}^zO|-NX<)EK1PXdSJhaehi+ziy&o)u+BIGIZUbxA zba%@dJPgN**M?PtC$RS@zAmilcOCH_eb{N}u8FJBhjw|j9T2fH5K%U@iGGWanL|b@pN_G#p^S zVyM9?GGGb0-IeqDG@%`Wd|;*Y3q;*crWC+|I`#1Sq-dZZ6WCM8Rj}={2rxu7?WJ)6 zv4;q+PYV{BpdgmLO{#YOzyfhd4gCeD`A%#%eQhabc|pwbDuJjl!!-Gn)n~MhK4q2J zlQRGRK4qo3EctfT|9qfofjIxCFH$8Rph`YJ#rsA5(i&<7x~vlPFP=%>E6`{)88=PU$;c zL0t79{uoyjw=Uq9SndL&rtL=J_0Ib2UlAHw0EoLAJj z4HA>`YKFq1Y7qz4SfWs4Q8m^_)V-XSdXzuKZ6tAgE8*EArF=|5_CWm|P~hpCXpy%o zQ$rF9AJoP*?m7{HBo<gcdZW6bkL?qxm^^oNwoqGQsxY&H$_9VMRB`bHeu^{T1VNJd;-R8ALl9M- z87xUo5e8wPNoJiWKd`*oOr5A8raEMvmW42;>NDqviejo;<_SrfnChANUY-@iRG-ZA zl1#-^|I8Xm76xVeVsB99h;~rvz}9GFX0yr_#nkA`^^(j4WebrUo0%r6I4I+@*4~uN zGm^~4l8cLn?n#YGV(OSop(JxLwLG(rB=fQL6EiDBmB!S`nP(+g7E`BZ^i)aEC@9l~ z(^XkL`Vo}JJWT1KlAt0ey9QXDP6X;5}2 zWk(0u5whAW);u=I>XDP6D(3DPWcL%dI_6FavNuXq^O)Q}$i64CMNCc!vWwKTEn{+e zkku2bK}}2^5@hvoaL_6yX9w9cM7EB}`9XGp$Tl&#ke_)~U@8c5DDg5};wE461o^!j z$Zt^$CtoPQa^^V>AMKqijsVL!#c_<6ULuZw5(Tvy(3;pUrqw8xE{W+U98IV`+y)nG zgK$0NO0S@<1uaUYqbvxgnzSB`$o#}mNgYXDJVAn_E=;6v8%3MEi-A#md;u|W;& zwRiy~x5DY}IMkpO`9c9@yu;ineF(Wm&86>%PE~3gpBH=@wG*(=0Rbb(4`+8WXCPd$ zRJ^&J8cVohg@_|NW%|L9#^XAr@0Z4ZQKxW)Q{eMcG}J3R-T?@sacL*>zBKMB;bRhw zFN!#!Q%1I=@w86qV&gQP=@dAPXE`9&_^(c;JHi!j*P`T4Y)RwAozlBY z<3BCIFHIEic(z^gCoL)pp!EVL*k8JC#*K z`IV}Dn9(Dj;Ypp!)Gbk^{5P3JHDKp-YSasf0y_-Db2~MXL`kLm$;G{VMW+^DL*==9 zf}pZ4RAn>&U-@!nr%+xtK9$x_`GaI+V@Ydj(Bwc6uSv+!Z*o{Iapk3MYYY3`@GljZ zLg~1G=~%Ll3hV^pHIWIw$yF2!ntYCY$j7llL}m+XiH5R|Ha%;`|tjr1pvP zYo&JIIR7u<``LWSY;@m47+~{ka;$Q1= z?FjrPVO8}T=qA%W#^2hH=J6srELlPI5T|xi{r90Y{y*#)_CR^0HQo&8knA49WbIQ6 zL@dR;VH3NPot!*R=APkX-ps$wvZgdA`UPbNI~fKjH}Z|8TH{N4vtsypyAH0`%QYlfI5z zX6G){ZGov$>)7vZ?$!g~2vapm06!y`Ii1!E7C8y-Z+EW*eiAiDuWg zhd0+Wmb&cc10fch%tQ$l1;H$n{*r8o40}0^%wVZ0vxdBU?_rQfn^0;ZiQ(j_CdGXeCf1}>~LX+C4@Wjin%2Pd0m63%v0_0BfA|H>p9FEZIf zrEv#oyd+V;{!9waGwCy>VDJEV7bFUfQtelpoK#EbM8gZBj1u`(Dpk^YgUN0noB2@I zZraAr2ZsRMvb~?zuxcQjJ)kGN>k>0ZX>e%@};y#m;YWaDU;bkXWlwYM%C9O}I?8#)yMvm|91y66|=Q7oDeF6l5S2lKc zFL*AY`2?smK5EjpQn=Chk!*AxPs~<#rr--ECtI@cn#n#(Hgk6e@He*i`(=~<4qkS5 z`Ta_w;3oCtMw63jS$UXO1tVORpQTbItsj{zKVQg=sg4MLvW?%Z)Zm|P^;;U=GwHn$ z&hD(H`yeqhfq)D?=Y2gm()gXp9xjbL$p0U<_wy^0zCa2l$j@&Q1xKnvKbf3V%gVdP z+(Ncgew9j>G;&(@c|B6fcir3GF0{oo-dPf%xzZvrv!r9hb*9rbGl{Q}M z<&R&Gk#1g52$q}lQsV~8@uuu72(Lt88sxN$1y{raC@fJ(L^&;E!GkeoO4Qs1IlHHP z+mx-LY^p?6E6Ule0)sN z{J$Ua*QzO^f>3pjUP0bYQ$IURCA??!Ez^D*PGjlHCi=f+gt}>gY!14xH z#WUq2>h@i#GEyxM##W_Uv0i3oD(c2>^&oSjf_hH}AVQr+SJ}^xX4k2{V-lBos!kKD zGP1=FzWYI&s`S0c$J1`xszxtDcok|W_C+?7x>q$i7%K29RQt%cZ^Hxwsv3QcXn|j$ zDpmXTTam%8RgDxM&3*f!#$Z%cBfZet!mp6qgV+#A(|Yo@>y~*&wj%+S^O55e@xF*S z0xV~XB ztk#zk9S~2Ti|fpHc#wTt(XzBI9`LCS5G(64yTFl~tLm~vT-eCiMd+NmmcxP7v(X7}#S7G#bvCTBc7ZytE+^GeaA{q3e<`qQ=4FY3hBfnw1W4A*3+vJ=r13GibaA4w zy`uK2x}0pu?5TC;0k^Is41sv4E+<>^^ZGh75TR1}RVv*w zv%W67ugus*=eh0ue6lXBH*wFGqPU65X=%Sn|KyjGWekZinWzOjv;cFo+F0B+5E zE1{D$^X0nqhq5r5ZVX;YEc~hVeWxxb+w%MII`b>pQu$dbTQd7uUABx<_KaPGzS!RH zkLuF;_C>rveUfOk3)EM2IjNF@AM3Icq~Ip4ML#DBk~!$xy7Xcx=-(0E_lbhL6~n*O z<)m6}eNbo4AX_RoN~KC#|E^2lPc~kOz4~}&Q*_ytI7k3mLmK|9Gy1YX_OecB-clD& zb!`SinEH%#OJlY^UCd4}UNdvsXtZl)X#yl`X1d;VM>u<~e9hFy8fPjf%Ih<-rOC6p zK7AlUW&3EC)1p3}|Md#+d`Xf{-M@wZ)c1PA{C&}(N+8vJC z-tl4e>0_nU@T@zK$A{D#J^5BDM@wZ)cBj>6OG~i(z9#1x+dDqFKHUpm*76QYw02fR z99*B1Dk+#-pFI(wc-YS0#&J7r4^IF$Y!^7cT@M`LfY`@b_34{rvYp29?8M}E9UvCg z=j4nkazMR#m~5#WFO_lmv8+D(HrdQ>oe^G>`&fMP5mGx=8K#{#g1N-De;}`W1XVvFqOMWh?H!~3`m0zXO zEi;$Y|3B2d2b2`W_CMa;)3w_*Jw3y2GrJ2*8nUpf$imL<&Z002h=58mU;+`rfPti- zB1kY`7En~4h#=;SqKFAFCrp?F3X1WW(=+@&pRTTD7MFKC{@?qa_vajDyFXR+xwmdr zSKq!Jt~VQ-igigtJufSh*OPS$kCDY8>j69^FD*-uiUcdmysg+&E5i*TLH){bV+hdT z!4$u_q2kw;NxsSM&E$Bm2t{1Mom|_8k83?6p@=6npmch;Os=PhgQ)AH zp@_@qr9D-apl~XFXPI~%n*~&~fWo*;y;A0VhfSsUrm{AHn~IMPaaGz_CY#|gBJb;N zAbLrySl*jFaNaCSkctGG%RGK+M6Gilh6MHN+!hTe#&^o(abz5u2FZINCxDiu(T0#cDRS}sokSlDOpeu&AJ zt1}V&xxzXEo(A%8ElVJ-0r+!6xmF}JV53IA;fT+NfUSh)m5U|R>>^$TI_2tAQ^!#* zD0it2m1tHjck?lK_DKRS)r@c|XTb-tT4(@HB`ZPKvsO7CR37y*^My*SN_L%nBm0q#)lvPaZ=*K)~M zDco0CshcK%-VRR`-8G;XyOaw);_oe_CCWm^?{>vbMY&5^oQ#=rxsHtOc>?KG-r%Au zT`oQ*!7rT6)#d6O>+&4ir#yIjfCK}|Wuz&_b6Ed6!x|V8aHeBk_AM8kQRc;Hk^UjU zr?kdC<-wZ*?9+&HxjzZ|^c{#RpRfygFx%|l;vod!nQ%%CDHr^jjyIM*{9T3R z$LV`H>Jt1Xg~>R*s;IgI&o2vPxN-VLu|#lhrbuC4oSscQPIsV5f*%yHdaIIxIM1|& z34ScVIz(Z9oF}cO34RX1Iz?g0I8P8oiJr}XU8=C+IM?2i1Yh;HZdX{dIG45NiLpH6 zJ*%+NIG2zXxXFb}y~O@xh?ED{fvppK+269ugDc23aUPj%6UPzr%Y)vui}OHfpE#LV zC)KJ$f-m`7omH!jaZbt3i6D(YPt|IdI44z?IA=y#oWr|og0KBshm^M%h(Xyc!599m zL(5wnkAdoz2*QttmA7DencfM$_-`Fv-l8xMFX2O=TWauZY&T(cVrz7Hgfj^fuy=)g3~=FoefkQ9^>j6|$%p$Iu#1^L@7y6b?Gju=Wf0aRp4m z0Tm*Hx?WIsU`V*M2O18ka4Cv}2Up1PB>bT>@I!YXJggz%0TtqW5(ae-3JJ&Yh&a5$ zr6>}PtB^O4@NjB=bV$IPGtg*Eg?Nqx>Fy{S8xm}zH*;)-OKK8KtdO6O;7w{YdAmj= zIKD!}OF-~2r`(Al!EAccQ!89jli>6U89eJ4<9d2VLxO1)f=_yT&sCu8)R3SPjXA5r zB{d1ou8_`e78t8gibgjZKczK7)2aWTH80bzGsh&N=svO-j#vKLfd5;C4f z#%n8F$|B=U6>>i^?!ha~TedUO$}20x6cT*T)%=E#z@X^cDqK>N;NA*(F*emyzONy{ zT@~UU5^UngtO^MRa%o>v;gZ^jzG2l=$VoW*;yfV2rL%uUArj{qW}I`}R?*9075;<3 zL}CmV^Whafh8|1f)Hc`~QQ@ycnT&G^$5a$^bVcFWp!MRMg^$EJl^%_AKCFv#P}j#f zG8@#=y11fn8R|Y3r*Su`rFBI`;S=C|F;4TmqL$V>Dhm0T_gCZW@#`w?IU5awL;WtK zzrnUmAP9Lb(ItpnozD^iO?pFbYi&h@hQYb)-JbG&z=it_f#=)4dBfz?9_ZK?q{Qg09_(f}Mlewo24 z(EuDkewo2)t^qiJ{4#^pLIZFB`DF&Hl?LF+@XHKV8x3GS@#zAqtp+eBVz#xdr`R7; z#p9P5tWSHE%mnQ5%M4cgN|!T@^Qmj4e2w#I1?O3LND$#{A+VbUF!Wav*j)n{$3+Ax zG*Dm^X6ptSR!D#YIdp=zf#Q~cvZ7YrBd@qa%U=Cc7W?p zwo;a0{0jFcLBC3MN)2O|dsK>EDDxhyM4R4~>XbU1>(E}6E~!bdU!@$0N^Y9OLp1>o zcdUeiD#aNjXvfQqeL{jWxMU8mbV5`fR(<|kEsH8MFEhG?_Ko9fOH6sK<&v$C2;B@vL2;7B3CC6)3;609Kcf`$Ya zREi%+5R_dM5*$NEd~u~qY7#81l!a|T5T&t}H6*yIQlwGlJw&1Z2nl-9ddn+aQj_48 zN;#YaSMLe@wuS^ZRElXN7{pW9O(B6#gWOT+l9~kfRmz1V7{Y$8X-KfDQru61p*1MG zHza6F4c1n=q$a`oO8F`Yn(^fDSVMw`E5$D)aM^`NLxPTJ>^xEFlA3ex`AS)o0>R8) zz&D07%jM*?tfwnQ24&uFEPFPbS>37X%atyvsll6-ay|*}=G1(m%}Lk0?rtlZA*unT zqm>r-l5sXq=5|^wJcS%ce3F{7$XJ+`FOji537TpGbx_CC;ztr(NEft8NN_9JiqbBr zIry#9vS&LG@Ow>GD!qN-8A|K73jr=X&rx)T5C|8Z(zG}jt-U{J^p9I~ zoL>f4?ja2s2c*RjWK6IZ14G6)J7Q;O+6|uE0^`WEoI%E8sN*4;Kn>OYX>lzHzT$j5 zFeKQ>`FL2`B{fwVo0boe;JUuR$2BAvofaRGU@p5cCL|cm-at;eYtji)li>Qa#|PuwLpb<1HY8Y{mYq@Ny+HEoLV`;; zBsZrMq~`3oEG>GWQUTQ{AQf5fPRo&Gt>BsPo`(IpJuS{4Ygs>(-5K_4Qg7_6PP?Qc z!6Rw!N)jxj=yeU%TAP*+lb|D4jfXhB-_#nQd6y$)8ZCv7Ep}>Qjztm zv}6dz9ncq*zfmpCa29-?7GI#u+p{;yz6{NMFm?Pc?UITFzounZ99{06!AicJz?J<` z(WnYnW}H24;vryGh0m!eoqkG-A!zMoI9R`gB97urwW?eSrwF&oyO1Idrk%a2`kCs^ z68#;88dwBEL%BO%YwlDwRIo&s>WNsuC1V5hYdL*A(#qLj=up zL=53!*CI#6m%RbBY$&2>l`O)H@=l z1JM1BW7Rn{7R>MN!PZ@JtmksZb!}+9wpHRn%Dt9TqJ5P*uhoLuDywoSj3RngdCyYB z2|W7JIbEB|d0(B=wXRg6reW81uaaL=#LXO_im+=3ab3w&B`BOCvQ^%0D0jQ_)Y&&= z;XHC7-3-LY`!YgmP1~(m_=T3ZsZoRbCXG zaNpuud_<0jn>hE5%n@-m=ibr=j0eqOp@^om(ot0j3TM{_SBbu;RKTtj zP#EPNUnOT#?yFo}PgE^=T)IPXP*@W~fOGyi9%qvpPK;x!#PyWB0M@dO3nxZT8f9{o zOJTgCJiSWt0>*ubQ|*kZ?GcK%3Cz?0zokWBmIhivYulPuC8C%>UJvSXYL&Vg97!|J zu5u}yy*RH*4nQS$1g&?0RvH)ETdB)M8oEiqBD@Kv#wHko+zop*GHK6pqtV(o%O5Q{YTpa2>i!HCKa@iy5eM^<>L%q|SeYa_X z{Gj7ER0)1c)SJ(~-V_onBEcP1E~zu}__=UCQG1-tN_M z2_~@Hl>=8%U4H}BEhA8=0nEUgc^p@101?g6JiBEy043h$k+6pbFyZLrSiLoX#p)`m zQl|kdR&R0j>aPJz$!9oU2510Nax-fT)Bu!56r#LZJPKLfLDX@#YIT{p4L!03RlDpn zZ8f4=zQdlipsfzrZYz$~kZNJU)$=~!XblTZa}HO*kr-~YBEb(P)@?~rm_U$(US6P|>k0b1}-@dpc(-R^uU_7N-{6xk}spIsJ z@iO*$PPI!})Ny{b>;R`->3IH*I$oefC>_tL76Vb)EAI`Gb3(=zJd!V}b}5UDmsQJC zP)X^ySQBU+mo(Jz(rU4UjPp2C7KV)dIccx1b}5Tzjq9uBTtM#4^j2=H-hR@*maT5q z08SDcSmPEA;3V-Jfm=0zlf+Rx-fq(XP7<3~<8}?;B=H`BJ2Zfk#5MwVY5*sRuL<0x z0h}a0=D@Gg0L}?t5x7SKI47741+CTq?jS@7+^2y!2F$jutrj<;pWgADFDt5*d$Nv; z-kNHcW}-3HRZEF;fg7QS4VnO_P@ll#8h|lM2|TF*^nDW#wx>0Kjtpi;p3y*2pu|Jf zVps5cU$gQfp%P0mw$^jiF4dzFo2tD->XmrCy3I_$!Hpu9GT+cZtAO#PYB`IHuff5x zUQyD#12}8ms!mWA89%7@9;#>Dq6yHgfN`q^;28w{{73`Jv3s{#en=5pc|vE*?=%4W24nhz2K1Qzr~#~@ zJ_q?H4PXszLEvW%;I7d11b)!~!fbaC_?HH7SLl8MziI%Uz&ZlIX}}4(_Ib7V5WVp3 z<{9YAaL~GA##n#gzznM^N&`4Kt|d^T0lF2o6{!(7V~D)IT=zwdS^+w6 zz7bMLSkm+EnqA6X-Laqf2Ej60-8IY&IVO`@A{SP1Z1 z?|H5rhiiZ$Ol$udv4A4FU}{7k5V0xD-wi<7(vX6j8~u_R%3h5P8O9AT{C@ z67-`H$A$!pdB7iAKN^ zqTaJ>WNY-xy@U8%O#r;uHdF>a~h^MH;RLZ?1RN@l$=c*c)>QRYnYh(#} zd|m>ofo*erCs4Y5+=%qC0WD26#l`v6&jt3-!DilzB}kb0e*AV~tB~ zDD#dQxiOGQrSH-Nkohhr+T9v}%th?@Dh)s;Pg~YK8bHT?=0v+!0~j!y##^lc4A|!c z?$ZDUY#_(@ehsJryQM~aPrXObJhz2<|IQAssd3pO>iuYqy399F*OkD)_O-Yp!K#jp!F6S(0b=-K1CASp)uzXDbz4xH4nrZ-g zzf0$~NCRpbc^NUCBBqlykx^&4cd^J@B^j5(DWXkAuB3=7Xxp}$03sIf2y3qaRK{x5 zA|swbWiOw{R;!S)fX8Nsj7wQ$EX&A`vFV=5Ik9U<5Qb7ZXG9F+?)BvK=n@iq#Z{_X z#w9fg(iu4cmE5HyuGShrrE7UKWi)_Z&mgde1~6Kyc#QYa07k2heeb6M@S_(M8F2}f z7)n$043*fG$KhTXm+Dc8eKYb_Dlwc#(-2LN9}o=8h?ht(iUfnTVL3*_GA^k}a7ad` zpq|@?N8jO^04g;jFe(J_s)$=kn$fxj=1Y>+IYI+U=>syNKj^&iJR}baWgf;O9mZxZG_{; zy_<}uYrqW5FeM}3AmdOno~)#K+i1r#G6~8eSK4K?|s80l6t=QN}yIUd-h=Vjg4bD?%Wm7%s_3 z1|__4?B#+`%orN|s!W31WV|-xJxs=cV1*{Y91BcweM7~s&d4ofe1ZqYH6h~#ypFyh zlb|dreo;pJjLiZnT0m}!xice=hRa$wjPGyUty%_4({r5tt2BVg-k+}SJsN-_d7MbA zLxArb4ci+hW?ca$F}I z-~bGC+Mofg(_HSRoV?rF6H#1^6 z2_|DoS#M{;uN08rgN#dR5`2=850hXXC(36HHQ1UFTS#yaSBsBB4Qy8YBIA;p1V3iH z5#V$WApWzSKrri1oQJZ_6)O!Mpj}@y;P!`30oe}S2vw(dqAUDM{t(CuG(>;t9E>bP|B^EYlQY%t>fi);A ztX1c!<~)U$)Vic1L7Q6H3zghrE_rQ3g7Epl7PVpw39g}9twMqgRI7chOKKAAS}V^W z!5AJj-5L^fsTIpf@DvHkLW29b#-M7lj0ebjHqA_$FUSu)J38HxLAO@wi^831FpiTH<;QU_sr4}1R{TsQ_Gj6hp%RzT5^HN+sz)W(*UFKD zpu`H!z{fNJlo-Ql@VEwGnp@cNNew`Wce((0N&`@0S2lTC14@a9YsDGh_dcS=kA_MN z;Q{n)txNT&#LKmEEtOz~Nb6Ni03|FA{3Z=RiSudw*EApkW4}-2%G=PpjM2?R& zpgR6`tvCe&z1P{NcSEf<&}5&~y406ieN`*BQL9B9;BPbmv^t8*?6(?#RwwY_`A!4S zsvVX1UIWnT4tiQYXaHKJxD@@U0j1UFwZhv6T8$&!m!VeYvf|IRF7>5WMlU%CmE1q* zq~O~uJXHlg(P8XoL<7*urc7G{YB+wa6(>=|`)vJtC}K7Hlh@0oaEkDH$;}jTRXOm4 zCP2rJW5p&KfQTv7v_J#s_`}q;Py^`rYAWGt03H7Vew5Wz1FGY)m&n@}S}}i+<@Qo1 zxdTa6)XSy5)T(7K*%p=DJ#f;q+Gqkhm}Sj+iM>cLisM-t5_I9A)wY*QY7&(7l1GxD zFBjWgLjnh7B`{>?UgBIb1chCC6<^7n@2PzEUhYyd@Vd?*-0W&>{DDs@vq3)P-jRbg zHS(=ZJ!Q-N^;=J`_w>^yTEzK6P)xn`w6$mOnq*wP=k!rezdLF)iSq@Y7ID6o(I(Ef z9@?vSp7yQ`UZCs{=Zg#-)w@mmE38wT?nelSHY?OCq$?`}eR{-)qei8Ah4d~ZAst@`tSbI0eyihr8oegY zN6Kr}OQj#HTD{_Y`epUU1d&L^pR$NBVgAN87PNjl)qsuxU~r32mi#`$>jfH2TF*Xq*r64vX_i+~Mjq z(__#?n;}16_GW12eR0m^pbD}@@ zx>oyTd4_RIoR2d+k|<@XeX4{0u1oCBy?v|wcIfYhI3Ekx80WqH7Zc;z_Gne_rNkue z9aHVMLcLewyjTBzocGr^$9YfugE;SFf0&rTTGv$j-Ep{WN%BtgBaxzW2(GOT%(o$u z?Gs3`F4_FQO8a) zFe&XMV}(&W8HC>KBqLcdyXZ{(v6^Rsf$;3)O6Hz>A~yb3R|i>_szn^ntZc9K`v&Fv&FYD?{+ zTUq$5Dr{jVd0E-gPV(Zgm7U}zUTeGPKGykX#?NB$Y-1;R)zcdU_|wNOTF=7fwSfj% z5bR|beeI&>iFT|FW=TK0=uPy&>ZB_5w~MxNw{xvO7^64<($HoWq~Xt*cF|0ph4xf+ zXWK>dx!b$eZ)zIGTsz5&hKuc@I67(#t_=)#iJjz?z@>IkGoptmsSE6)_S`+R*6$3x z7urdB`*+w$y6AV>NxIQ@*+sjt&KyN_x1FSKyvi=BA$o~I@3E8gZ|}8>`VswyLRZ^K zI<5EFNxF^q+etcZYwRRlrw8mL-J7*`lK#Ylc9JLXhwLOzvJcxyp4A?)i&|oItoFSE z6Fq7db>?n|Uh1f^iz>L=v6ugoz+q!2c_K4}kv|uI%3-zORn>b9!PAaSASl^Omw1Lq zvxGpCcRBTY^osDTg}dx6vhq~G___x^yU;3If9sj|JWH}-DayPHd!kA6th(pfln!E> zta~_0NYE)O*N}jpZP=w@`*vCJ9^3Cm-=ss>{!y*~U9&Ek*}i*L{=)VMM_N6?_Esw% z57w?((fRh^+jT?Ssz-9NAETL$e}vAPC|(F<6I(1lF$DIV$Ut zngkQFavxN3gS)~fY$pg_NIx;$&o2o~dURGyBB9M=?%0rU885XaW?hOx21d&&%F1W4 z9p}t2;v8N(&Ovh2*8{7v{!ko$u{aIiJ5KBMjnf7Llz($@*58cggOltRzF1D}Y<%mO z)Aem^2h(+eAt=Kp(4-@6GC3QeZsB+P!w>d1zYSxTZ|;Ytk@w|Nq_k*EfUQ5t-jxpY}a67fZph|wb7 zz8WP?o%tH7wd^5aqHF@|XBz`)E=yxgA=zmD3{MI{uS6>Dj0DqqXl#^rhXQ8laXj;s zehDN}8pm|CjfljlMRbmkvw4%w^^Lp4hqCd>=mS)$V&i?#L#uQ;wj-s#gU&9!4Tvb+ zh@}&~l2}SaMWiX3wf==`f#}&}9(LMXkM4?eEAkm_{sCKxs#es@G$MS$NmNG;!(RSm z6feU@Fo=0ZDvHA)ufi(01X$ZAK%Vz_eqOs3V9vWYKg!x4qNM$8U&%2)Wno{WH zc{Rb#ORz)U;&5jI1}*Q3yc#xYe-`_2rP_gRn2kn<6&QxRIeB?clIPfTuu~Rvvh5b` z-E8OWat75n)b@69so+}?uR}Z9YH=iQ&qL5Eu+!p5TefOH0UixX0+rieMME!+^riGv zi{98-76~kvI)OI3F5C%vwlWeAde-3{%*?#Wk-YKb4(KLFItAPT-Q-BMsyBoEbRv1P zQ7`p4Ef7_FMu*{u(Dwe%$+cH2Nza_eOOi__%k&tRVUe z-eXbR@Vnij!FRj!+QG-LtwFJMsF;7iVAS5HAkZF$aXy6a9K0Xw?CV%u|1hW8P7SD|LYEkN&@xD(Km0{3_vPlfJkwDsLhn5s?P&A^lH z7pPO@cEws-?DocQi8~dtnz^q)dUJO_)G2kJMx7S!h2U@H7GaoLyHDV^jr$poYquPl zw{?esznyz7MyI`dAMDV<9S6y*ImunYcSDnW^4jlb~9slp!&sT>|)sJ5;K+sxWJ5^ ziasqgV^>0@MQ9E^E;C~{L$%Az*b%VLVly@ZoL88!Q=r$CX6#rrzsijDLCx>X*hsK^ zZ^q^T{K1T+A@)Zzwg}))sEK)TkQJK@aIF>l0c6`Eu^H&^Cz05E80*tWYzW$Y7Ky!% zvd;mc<`D&0_T2q zY&H5Y1b-lQs2%$X5{B8a_RwXx9lHeP9AU@4ISlDB>{x%;i$SHPBGv{9CPmBw=QI(^hw{@!>>$|eR1sT* zx$w4#(KmfZ#Nv?fu82L4!Ff-_+M)UTBDMqrwpqj`;Lisl_5}L3F+a914vrV|V;_O# zrTo}t)OzLp+2G+p|IJ? zMC>WlJjaiH3$vc<$F4*3CY@qeqelguVp&KysW>(p%1uRn_3)u6E#mRjy($VoKhTn4Mv_;9BW5o6~`V#k4`O)9RejzD~@e|^wW!D5|*D) z92^UUJd3bgCJB=#mO(Pv4FC;04=*heVqyCfC|OTQ(t zCaBVXNo*xp_F5AA2bvFAA2ZSEq3dHSF>OYF8aofhI^xsVQW$y6r?F2_<;YKCH=yrh zKaF`1d(@|~(=lzveH!ZyaQvs4f2WHXb)>l;>Ojmz+`T`j22V4u>ozS za-%Pfx0AW?J>;FjjW=P@Y24Tygwwe(0z9X3;~{8x8aL*{LZ@?MHq@KJjS{pvgBxc; z)=X}cL5*3#26{QG3dk79I+GhQjNNQ*+y&-2+_(dZ&E>}TXf=-;mqPkk+(@A7XLBQh z=9i4Z#ylXGa$^CEx_}$wVdRC}=mN_u;>P<_{zzX_VE3_^<= zTQE@~+?WZ(=EhcR2yPsN36jT+CFo#2H|E0#4mVCgFC;fk#-K*Iu|GCkZd9Ohj2pus z)Z@l7w2E`%I+!lOjV2g^Cfw+b0WaW2TgWQpMk)01xgnu^Q*IoO?j*U<3q{o0`<@;z zH(r1Zk!#8DZh-U%H;zOHZEmDTvlrOt3!!=3mxG;N8DNwL-c}Q3q;I$A&QMUsz!}xb1^F z5)UeL)fMXKnxn$U15n}6j>MaO0@cJWdDF2STv*$ydu{_s@(9cbd-a}^z?+ooxjihv zpJFdpAH{8>XdxQgi}EgIV}Wt87qxkl1;zhDuk4dto|128;TY(aQVf^pNHN~8st%yhGHgc{3hCYU+IZdHITXmf|g z&dax_5UexT;7`83^lf!Nzvcw~niKeIPT;ROfxqSi{+bi`Yfj*=If1|C1pb;6 z_-jt!uQ`Fg<^=wl6ZmUR;IBD>zvcw~niKeIPT;ROfxqSi{+bi`Yfj*=If1|C1pb;6 z_-jt!uQ`Fg<^=wl6ZmUR;IBD>zvcw~niKeIPT;ROfxjk|zb2KxCY8S?mA@vHzb2Kx zCNIX|USdk+uSw;vN#(Ce<*!NQuSw;vN#(Ce<*&(O(fle?Dt}EXe@)H-_=72xzb2Kx zCY8S?mA@vHzb2KxCY8S?hoIeO5vlw&sr)r*0sJx|mA@vHzb2KxCY8S?mA@vHzb2Kx zCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S? zmA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCLe-bHswp@ zuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;v zN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce z<*!NQugN!Ii9SoD^4FyD*QD~-r1ICK^4FyD*QD~-r1ICK^4FyD*QD~-r1ICK^4FyD z*QD~-qS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvgEvo&ssP@;Q+Fy%me=Vy0 zwW#*jqS{}Jmf_?@e=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q+Fy%me=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q+Fy%me=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q_5PYmf6aowcAbF}{apN9gcF*_lN%D0&BV4%ASk&}moUK(O9%u%v3{t} zd@e!5gkdwmOKc{+k*S5QL6K&p zFeUONq)1k7nhG9pD44*VmMNElkWDbsDJB0vrNmLxYnN0D@WB5`7>RKNx@aJ7Brb$& z80o43&q#bjnPnP?8HxJ|lxx5>5}OF@rU7XrCXu6?1{@;RfOUJY z?-d#lM&cuK^w5B9BsNk?PYpzj#2IW-sR0Z~mQAWOKzqW!zA5!q9IZ2vKtBz@I#*MP{u+RFPNSjs(g3Wph`<01z&bCJ zW1!Xw)|tZ^gERo^Od&8>1F+83w9Y;nfOT#s$G#eXb@nH)p9Wx^Hwg^U0IbuCnhw_7dvNE(luNte z26|*#N}h`Ai^QH(^VC%REzU%OjHhX!m62#h;B*bNG!pFy%+Np!7=yqW8YndqX#z7f z(A-G$Auvk=%`g!t_Dl_w7>PlwF1gV4o(3>mrg4#8S+Rf;7ucP6ao(3&v9V zl9bDd#p$y=CEwxnxsLdCnxM6j_?aSBY5>z`Z>o8N23iIpmZpT2fQUl2UKWbjpF20F zTngtI?e3J^4V4lYn(%D)XAXm1wtWY*0rVQz=W0jg4W z6VLQx_rR2YH!Afoi%HzuEMZEA$V62sYnCvZLu69QZwYaI&0;QX*Ov69`Iv z*Coi^_a#dR1SKWtQqZOd(GyyefO{Zk$Y-et$F1SR0r`{0BhD4vMz_o2D^S^Sff&x) zXkt3Wm^qenFlVJR3%KpH#c!T-Gmv~|BI-EKT-1?H1~Vt>EX1$t3`d=qvj}xOrxZxS zh%81WyEf7b0wS9M*?kJuV!N5W4!_Nx!%r!N8?ig^`wspGok$oho&bv|D`bt978;82 zc})=TYV{4bj|uK;w{COHq=|-@P!cd0sfQp-?C&zjRE?@_gVOzXWof$}L0N{fjrOa_ zk?~Z8%xM_4M1OFo6(FfO?#YX7@%TH|p^#L4m45PtsMZPbQil6NO0T8Eg; zaam~O&&E%rgKs>H)zCI(Z`W%i79Z-h30?Ykdi|e<`Iemym8}WvZ@0LIneO~P4?E6X zr*JwwbR2N!C2U8Wt@yQ_pYSUjcN!;^K(l3XEuJDIBOBMZR1>a0&bx?$zw6-&bMeXM$K|3dm2_1XW-Fz+SiEysdAP=!)oU(7(3(qir-r2 z0%+CSS%$WKoHh8(I(=psMxE0g+kKru`0eN1IUV<#oH1bD%h@>9Fa|iwAaQT!i{tUE zu9F8n2RS!G&%w^FK=yI=!tcJ$0E=pjCH!eGDkT#%)#9)XAz`~clLqiM>~H&`Y}!#__2-$iN`sW=*t9W05m_| zx$Z1H(d%r1!s zgzc-Gf1&0Q=ODDb+PMq-OPwDkVL5ev#rDn4Mre48(-PxytJD8PJgn%9!tY(qH2mJ} zT!Ppz~-$$MEFhkZkEAYGC zc@V!FoK5(B%-INr$DJzZ{DkvQAWu4Zkp7g@3BOM}Yr*r3^D2Iyb-u*!b58!*xJ~ao z0xP}XOupCnd9#y*{vSA_VaYAdw~)Kl`55E%kz>HZ zA3IG^bDL9+-%p&=!ThPS3giBna~wwGbLVrk`oi%rSHE<+qwPPPLHPa38H?Yqof-K3 z#&MwMx6V-fe&;*^iQhY2(dq~1C20GjGa7Awa;D?=XJ;R1@{6+s+y8Pd#C-eJnT4MI z=4^wk-<{vk_7B+#^U5&gdi*g>*$MOAGG%Z4iI{RE{@AAUF%g6*Q((w5<<)0k`7q_f z_#;jEDGto2DI?f(P1yo}Vy3(dv(7W+%b4_WQx;*I6Q*2*ngyo37k>&(*#tx3n{pTY zX^J2_{v=I#2>ukAatX{*Y|1+Hr^J+pVge2^2bn3qf%I{ZfW7giJOEZd+LR~Y&oQWpS$M1|&*Y(I$_d~+(Ugy&V>3+oHvXIe z2{?#mnzAiw&NAhXFu|Fod=-6|jgDdX=a_ObRGJH8q4_*h4#!+M%aq@O^K4UYK!bCj z1e%{~$|(A9zA0bA5L{r&BQOsxH03n(;UZHuMe|Ed`3B@IFy&~dyAWnYgGHuXgPND2 z3dk0lavP*yVanIg;7U`@#vj~S*a{_5c_ zc^>3FVamIq#FM7n8=AEz9D8qu?M!bfY2FGOnx0pP z-M7P*rbjp1ekW{ddbhdQeK%}tdGzD$_rkW8*Mn`}58EQmAWJugZLRp;Lxvgl2WH_w z>KpOs-rFCVh5KRmE8F{-yIagctPMDLjRgO)XHBlg212Opasn1Ms<(sua=k&i0#^Db z-aBGpP;0bC>ntPMrUcwuO`A@90@gNWXb#g5$79@zqla)ZOL4uZqe(D7uTQWzXgGB_*{9H!l9 z9R!CbV&U-_92PmjVV}WakrN#D85|Zz=m@K4_zVt1!N2oB%T1lD12SmXqUeFld`PH@;~a9HF7hy8X0a)QG? zgTo>xIP5bxEOLUwK7+#|CphdgI4p94!#;z@zqla)QG? zgTo>xIP7mDkP{sC85|Zl!C{}lVUZIY_8A-&Il*C{!C{dT9QGL;7CFITpTS{~6CCy# z92PmjVV}WakrN#D85|Zl!C}8M#pVQueFld`PH@;~a9HF7hkXWzMNV+oXK+~L1c!YF zheb|s*k^E905FCCLGb731un2?0Nd|`ng2S9xoIcA_(l5aDVQ^UF z1c!YFheb|s*k^E9R-bv`#WOES9O@aFW4cf#5KO^Nfbz@KF@O;IPOE4*LuM zi`?Ka&L#*B&nIJ076ylt3=RtfhbfCI!iJPwNk#^TMQ(5y2MvP5&yaw@VG#z0lMD_E z1cyn@UL!dCBMBHB7CFJ;A_Rv;Zg9A18-d_(3;0Y)28RWL!}I`>3=Rtfhgo7ID6kA$ zp<@66@2BK30DK0AMNV)y5Relb_8A-&xxwM$S*Ad6_#%pAa9AKXyp%f(4hsZ_gE(2> zix3V(A~?+Y3F@$FJLt}`g_)Akrnpq1PhrFu92N);w+7Ut8Bh9#=`lDg>Vw09uPN$- z!+~=t5FD;X6WeUYvv?aba4M0%D~KSsH3KhFAUOO8+>Q2TGoH-4nSu8x>Vv}`&vpXA z;m1&^huMs4dT-NXa9Gp_hdl;|1%kuFA+E34j7!@!W;0IF6{g4Fut0ElB^Yinn{ie> zVtNb?i~8WO$KbH24-R__4hsZ_k3cUsn9VqE49jD1SkwoHJqCvbg2Q{El5I8P+?Zu~ z3=Rtfhs%LpV>RP|A~+m)Z_Q~yINR98z#=2tXvM*e-Cc7n7931IDha&0B32SmEm8DYY}|*E4&-n5|_%hn3)w%qIL4O zlTdc1dOI$8A1>I$xmouplu*PaS(%rFh#!vyzCaVSHvB&bEYtu*i?c3;Q^eA&+>0XK!v&;R782Mk0v)f)iU}lW#$Bok5-dIjWjBTdMclbP>ynxT_h#i&B>0qS-q(=euB`Zy z1i#Qqt3rZ%Xr(n-m((O!mzB{X5WJ6zL$M(wXoBeoGe49SyP+)k^zkTrBqVs1BldXK zB{d12%gR9{*v2lr&`^V?vf?BXJjp?QCM39&Y%gYAQj_5ItUR9t^QHrTGbC_unFI}9 z$%;Eku$65#g#_+Y?7W?INlk(ev+_9-e9NV9YeNm*%ZhJE@D(-K91=XsQTRCPl9~ix zX61dwAXt1d@UJyN0&YB8eX9XDT3@o0-)SIb_zzRD?=|2W{sh|bM-Ai~{u{V@6hCPo z&+tE{0e{heZTN4K^j{i?82&DtpucLsGW<#^{F??$!;jKdziR-!fUQ2wig(b99V#CkQ1rXOjk>Ss0-xC^08va@AND~b-HT<7u11Qjdj~AUtTBw0S!;f?J`Wh$* zx@y&lC((v@&B=qI<;~?~?b4g8t+B$hX35Ib}?V)X;mWQf3@hl1U=Wy4A1W$1W_pWnEO@h7Z z;64ccR522alVI=4m5=0SK6NBnpQj=gro!kYL{C%j|0U<$naPC(p_9ek5 z(@-`vBp5pnI|tRdq$a`WI(aM!&LY8>h8i4FCoUqvCeDh(LV~+F@5a`-q$a_HI(ah* z4kms=Lk*6u6B|j;mt8nEBzR^Hb|%)jq$a`iI{7&X4xI)3w1yf?trG>MAh5V9o)Qx5 z$%-@TTvC%@UY#sQCI5oyz|U?-aAuttMuJ|PNOMAh15d-w{5qG^hHK}E8CiK$3wS3y z<%QnKd0GDjiIZaq&rwZEcp7OM3tW`zvi>rZl$7wy(5-~adym-EHlSRa^=G4`s)Q?c z?-DM%eM`7@4k+OQIJktX*pLz);3Hy;mWkpze+gO~RKg?Sq!Lc&DJ7hf(_)O5iOM?v zR48_OGfp$ZY{toAhknjJb^h;Y>zK_r1G<^bIF3C+cV}FkzYqTi$#!3cIx=-s)Nmetuov zE!b}TBIa!V0r6n_QIO@2Yql16n~U(1I>yK!>0=o-+O{6J0cD35aVIqfLFxQa!8U3x z4Qq}MY8q|XYNFa!!A0@~x>!a#8_O-i{=HxqV;KCb@YeF|voVb=+@CudeKqqW2Hvv7 z_2`ua2g0KP#GUx_mu}(WNHgpM@FU>RVM)M`W#tdYsOz_RFJuiY3Ap%Wp`HJcNfG&* z@h7jrd%gMRqQV;dcb4M^LwXbb*aU)-S9A&DpD+;OmMp;~j`5`~L7R73LLg}4KuExb zc<4_oA@CP|f}HVuSxBqWlkEruw0QMQl^}|_A4>=XCDV0@jo1iF2m~bybO}7R% zl-#OI^5Ge>gn$gv(Qm<4^slC)ml)K>)6uU64L)DPbo4!JtU)>*Jx8QLI(h{lVZ~xB z5KKp}03@u?>F5=Zla5{iNLXF5=Zla5{iIqB#XkduyH0XgaD6@bJKvs!V|R)(F+Nk^}0F5=Zla5{i_;%YHZNPza^a{YY+jKg51>oClizo%@=oNr( zx9N2B3c$D97UiP`($OmbUq1dK0s!gg6@afZ>vZ%Az?{HGT#$}_q>cHc)6ui6J{>)0 z8s`(z(Z7XC_37vXg4}fU3c%3obo2_yNk^}M0wbEOQ|agx;2BY!j$Q%6i0X9o3c!?x znn*`)2x#_0C-e#F=vn3+*%LcRN6!x6hOC8j^es>+x|4MDeMrz~I(kx*0O{xt!{*M? z(a$D9qv_~L%|jXK=pP}$-%dxrl_DBVM^E9@5$Wj7Jc!`O$QnsU-w|bvr=uq|36PF{ zI0@_u5d4L7^wY@LXgYezA|uk#FC^orZeaX#I{N!b(5nl|c1%Z4Y7!tF{i`I{Njmyp zNYH3HdQy`B>FA3v{dbm*K7+Ex)6tWf1V~4JAPKJC6KeiB9sTJf7*vO{9n;a1ngmEk zznBC=*v~(wqkoVDLu*jBV>)_LlK|=H-yp$G($W7;0(TD(?3j+8)SP=rM<3ju-AOw7 zJ>kJLo{pZ>)Bx$|FGQvPU^@D{DYMaZ^wfqjk&gar$~?aldiHnH(HFr5X*?Z0g;NC5 z(bu8UUrtAVG#MLBM^9N~L^}FKWc;h?=+}^Oc3<>x$8_|RMMk8f-$cfpq@({A2^vjD zPihW6($QB(LGZWJ(I1Z1ji;lhaO#M3^ruq9PSVjYB|)R<=t)fiq@(|m1pm2o^gevr z#?#SL8_GmF`rfGYm($T7MaD+c(Nh)~k&gaMGVUZD{YnyiRgJOUF&#arNq}_p>qxMZ zbo3vSU~U!!JEo&2H3^W8K7y;fou#AijIzel(UY14NJrn71UpGbe+&s4O-D~^5+EJ@ zJQ7@72{r$mj{YVRG@6c{)FePU`o~GIlXUc-k)Y9Z^rR*M($VMR+GS_y=*v*ncshDg z^Q+@XN8bmP;#4C}DzYLS{b6L?Njm!3WG(B5KJS>0o>U}2I{K?gu#

q*dPI(kx* z0O{!8Bf(D6(c8Fx(0Dp}QnO!3N8b#U;#4C}DzYLSeNTWpOGke&S^wbKZO3%FA%u=FZa5e~mJ4&)!gL$8_|hA_3CT z^AY;LpN^idQ#78Ap28^t>F6(|h`*hVelv~D~dJ%!VHNJoD>D#h8AIE7Iz($U{cxtVfw?eC3GanvR~r zctweH^q)|KPDdYH>zO*AInvQ901*nEj$Q!>d*Nyj>FDD=MD(E7h;;NU^K?3T3TH2n zj(#vI{rzF9TXN{y$ZXOE~i($V*$-aAQ0e=G?a zO-D~^4jF5=Zla5{i2r%h%^a?! z9lZi_($Omb0j9RyFlyWJEgpYsk2hbo7srpwV>nq$UB< z(etk5Urt9~jGG^gr=zDVG9n#)1uE?<9sNNhXfz!?sY!rz^ixQ%lXUb~kie~i1$RtG zPihh%9sT1Z_^avYKO^J$yMS@Wbo7+P>pi5SzXoyG|KFvfe+)`Do{pY>`^z+H$9830H} zuYjC%^a{X9;;1UrKstH_;3T2b(JKHa37w8!0XgaD6@Zh3PDihRoOJXG$Vo@9fSh#n z3ec&`k&a#gxM+ZTf^_t^qM!BY=vn5i<0U=P(bG&kg(4ljhkJ4L>F5;!jN#X!BGS<- z0LIYi=oNsz>vZ%AKt~4CTu4W+04#e@0_o_xgTFoY8Ff1PfKjKTrz|oe9sRm`#x0saGj7#@P7D8$29#rmbo3ungic2v zh|uZiDV%yB9X;>O#;JLn!YCK%=+}XxJ{^6-o**5)0<>JDqgMdztJBddK#wWX(JKIF zah;A{0XgaD6_AsTUIDl(q|?zWASWHY0&>#PD*(YtbPeg~KSnR=)6uic)9L8hX?7Lq z=;z~ZP<=XjMF11)bo2^9S9Lmi1)!_T$}mxoj$Q#d>F5=Jx%CXEDbmp^0LPV1N3Q@J zS2`WN0&>#PD*)3`r=wRuPC9x8~foS3piWdIjX9qgOyqI(h}jGGPCEL_DWcJI^b}4JNJoD+ zMO1c%h(D*Jf1L!4rlTh{36PHdxD+RRcM$x~q@%wWDm9*to;{-8NJrnUE%d%)SLppe zla77>RBAjOJ$ppGk&gZb>iu6#NBF9r^-i@ZCXOE~i($Sya9=7`5N=JVuRBAjOJ$ppGk&eEg1N8nc zrlYR}f8*)ssUDR;I{JB3;y;&;{wB(7G#x#)p-iNs@6{19PhbG+ejDGJRLo$Nq}_pC!x}RGadaRDlxPgz1T4wJ=LQU zNJoDsmDou-`b{KgG#x#uNq}_p9dLd4A52F-5Oj^Fqo+2MiFEYiD03(2=+7fTqv_~L zO#-B&zmEiiXqvx}j{Y4oHkyu}vdD;Z^ilX|e>olfZm8UNI(o`t>>ugq`=U~uipI%J zF-S*0v0ltyNJoDe#f)PwcT7i5ZZaYr{dzL~)pYdR$oK>gj2+X_Qx+9RI{M$R8KCfrtJ3yS*p*M`TV>)_jOP!F8z7HzxEFJwg5*%9rf*sS*lbQrbM?aecJ4r`>Jqadf zL9k;wdQy`B>F9Y;xwCZi+epx8I(kx*0O{yi{+~!kAKft>eYEj(^fMr@@pSZ5mr5ZW z{Y_Nruco7afsD&*VW%C_(Nh+uInvQ@!DgI&jgy;VkdEHK<;2d?(RV;uoR0o_5;U5Qp422jI{Nh_xDH22BkAb3 zk>F^0;5(+HCp8I>j^5r41UpGbzYEG5Pe)H`5+EIYKN4KQAmX3X(H~2KM$^%gngmEk ze>n+$hJW!_($TLa<0y>4pVHA&78#L_p7*`}emeTrh&MN$j-J9P0_o@(l-^l7`q3n4 zG#x#uNq}_p7m(nurlY@$jPp6lJEo(jEHWY;{qtnpNjmy(NziCIdQy`B>F9@J9{xAe z(N6<^ZARYZ9 zR3eK-@o%N0-%1gUrlY5Dia_c6`?l#ZUlDFW%}w^GDaT-^ST($Pop+<)Wg=&3KYLOS}6 zsI;?m^n*yyXgYdQlK|=H$CKbs>F5)9?+NMXFCc?XM}IYUzUQ;qNJqb%47{#02sc@d zjX&^NC^pEa+*LVf0X}Dmbo42B0flG9&>rdNyW#e|;q!%{SRr2wv~)W9!l`YrhjjE^ zQP$-DvG?9#QWWdkaCcYt%+&Pk%x=%@?kv08yF=b3NZbrA2!eh(*9XS@ej%}6n}7*@$^H2^=Xuw?dSt?95`k>`YZ$H8v-&MIA%NgEMwrCvJ7Nz z&N3RkCCiZVwt&P3j@gbr%aHGpSw>}Von<6-dzR79qXIG@IA%NgfXoLDwxd52wvEX$ zym@?<5y%q)k{~!{JNhhxiYEqSLU7D>^Z^+V9J3vLmLb5C1JWQkW;^;UgLrq!G7@*^ zfK&($wxjP2&+ZZ|X3lI!pJk}+{#nM$P7f}lMP@tt;1brucJz1z85~9hqey-oh+H(T>V8YU}7MBe0GM z=CXy^jy^b=Ic!H?fSrr744_&PnCPB`eU^b0R|jT0`U$Y>nk-`_t_#d|^gqC^ z>$41hxH;HjJNjVTtzj#+qdx(yZp|{BVM9<^2h40oADHdvt59QOmSF)eXZdaam0*kQ z=mWDIeL3pAmgTql53>Be{$ZBi#5ZU89s8reY)9XK)9vFNzeH~krDi*Nx^JV%@ssS+ zBFB%A&x;(tD84L8&35$o`6;%e&++5i2cmR#J50rP^lzc%$D;K6dSpAcqt9h(xgC9O zJ`ym;-HpU{bNq_oxH*0l5N?j|*j+crx7?naQ`*h(jZwzU@x4#6o8z0861Vg$R_)l1KF8N7S-12O zq8;1O=lH^-%+2w=LAjgbQ+VDjy_$78wxiGS3A-C+P=8P=W3zh}c5FwV<6~vDo8!Y_ z=;ru{SL2r6$2!=K{x0~g*3I#$ryT+Y;&gXQA7^35cJw(umyB^sUnJVG9ewHBqmb>` zj=t1vM?V>(I3C*2<|JrCve+#>kyoLP?dVIFGK=l#i=g~eH^+yDbKTM{x1-PTN#K09 zbj$7NOMCJO7TeKZil!I3Io|Ex>E?KgzQ)b*Hu^5Nbj$7NbG$dc$1UA*JNg{&Z`Zk{ zTW&|6<4x;*ZjQH&>)jl0-0pXCymflO&GGi;K{vX9<%kAh(hi(Jgu^s(P*uK%t@j`}QxT)Wu4u;p%Z(Xq+Juf>h0adcSDZzI1tt=r> zwu$E`wxj1&YfB>O^3Gpai@NmXsGL{7u+FPrSm#$`$~t-d3u|%M8JO@*;xJT-Plqx0 z;y_s;EcXT+SM0k43I}G1$LFBJKRYXUPvf{-EhM;u%ZXPG;PI?jdIT(P(c~4rXR-Y$z*DV1u#4J1dRXm8$nbf%m>$ISIAG19gT}(3rVB(B6C0u3@gW zCl)d9aXY1oz`6=?Ru(I0^h@hB77zZ?dgLMK^Z)Qm>;D6Zw==9_4`}%RO5*(^G}@=` zvNM{-%9i4I`R?lYQ{w0Ctd0fowR@=JRvtgJw>rLzbso|9Z9INdA8+9C1rL zZ{hL#>ew1}Al*Ez)6F}ar`!{>R_4 z|99)bUVB>Lpe`Lx4(k7IJ&3KM|GV{I{J&cd{&(v^>%UtMS|HQ@|HsyYU|jis*?JJX z3@hTeTypEd)NEWXAIE{(U!462jni|yrwgK?F0V)A(w}U1AFaY)hJLYo8_|pK` z6Kwr*0Dnh-gZ;erycB@tX|)cv?;6WYL+jp&54Ztx#F|_OewZZ_{zRO9Yh8F>z z;Ded?&XwFkFSwh%_`y}YY{3OrA(QYj+-RGdMU{IM51>*;^}WLD&pT+f^`Po|H?RL} z1*D_CSDG3{QQxZ#;75HA4UmlbUSj}k2&Vd8hyVwhd8xj4HvsnTQho1XnqcoP)%TtT zfH5VG$a`hu!SuRqAa6U6JuhxE)iL@4iHd*Ml9ga_p?beYb{q z6^A8F$A@|S@Yct&ZS1?HIzHU%H$efhsN)T$h8K0b$p9kic(Vb}3pMC12EZ+Si7f_t zr58bAFyJ=WGsx>hg~63qBGcwo(o#HOi#o65F;vR(<(%jj8J#_{7P}Q&5_GG{;}-F1W(i=<4(dKICytYF2Yg9TZXbd zJ-t;Y986#A?0KtE7WC!Gv8$(c#SE@oiOk-fzaL7h^3!dxqo;n%u19c+7yOe2c?vzv zwo((2c@@VMXog)QERV0-Tq6F*xS1DIJwYArd-#KiKHZZE%!KUsJh^6iInEhW9f?Ot zaeybjVO3U8a_ezmmYHrib_u9IYOUGM6oa~{nI#0&`ZU9o;Dp|pB?MHP<4p-jo#wKH zfGWAflz`Of43-d3C2LFxNS#)*gaAfwLS514IMU0}#5%olfM8Rf#XA@P{lhHTwoVom z!PjG#p{L{P^fGWEeLblz^8m!qJGrSO#7tu$KX_alu;z_BH_a z1$>{tJ_f+PfS(YUY5?pD_yvJ!2Ee-T9f5rffOX+N1okrkHVXWc!2SlnSt)qdOg8}d z-WtyVFv9@YC~zc!nFhexGM2yr1_1l)L;|x6fYWqm0<#T(#bz%82O5C>bHvVdMLWPX zfm$JVts`x<6@0i96%VS*(zEp6VRa=3X5haWT&d?90o+%Sz!3(3|K<`{U;y|pe+hsi z4FLbmXN`phfd7snaFhYyzeNO&HURuLjxvrh0Q|R@HI6j^{5O#`jxzxK_uUl$78wBk z`wxNR4FLcBN#Fznz<+{g`H2RA|0IEv3;_RS2rM>$_TQYkqUCT+H+Ait7y0k}3JGV{Nxv8aHj%S`SzRS72TQr!omZEkY>wV#btSz^An{$E6<5@$ONF`!ZYFT0 z0Wf->6If{gjNaD-t}*~d??(cw41m%5jlgOHVDv0%zuEv8y%>RO41m!~5xCX>7`=eN zbq2ubt>gG!Zvc$mLj-Ox07h>kfg25g(YuLbbCUrude5=O%?7~e{e!?Q2B7~OadBPI z_Ha$0e0ynK4X>iXB6jK4x-30Q|J_|zG7H}eG6&PiYmETR{=*2YGXVUzkifkLfd3W| zxX%Fa-^m2l8vy=WLg0P_z<*~Gc)$Sg--QGoGywc}8G(lk0ROEb@UQ{kzlWCtc*Fqk z-(NhTHy8l^dxA9{H30lKiPx&f3;_S_O5kw=z<>J?*k}OlzdP!RmcccFx~o_d`LB+$ zpQy{yvz*Zv*2$|;DaT1@<>*Q^`_HKJ?!|E_XL~87uL)=q|8G5&g}n-b(O3f;GL*OF=VD#=K@Ua0fdJhr!!~ht*#|eCD0F2%<1U@qW zM(-s8pBn(9cP0nxUk1SFolD@~2EgcDLf{JnVDwfJ_|gCvz3T{kWdMv`Etk8m4M6`n z;;p)(?Q(FL^6fiyHEQj@kJqMe>az4K{r7WS$;?vt?;jlgUyK0E{(lnq)d29{CIY`1 z0RH=!!0!ft|Nc$j4+Fq|-xB!K0Px?>1pYDr{PzcezYPHYIqZm4AB`jYmmpvp0R9`p zrNA)&{I@*;VF37VCjzbk;J-Zycm{y~_9GB80Q@(bK->V@f8W;?oe9?jYO?+q`ESrU zsFE&Fo_Uj9yRH=xYFsUOj<217P$95vVr+Mz4WDKLcR& z&Sww$8vvuXg1`U+VDwfI7-#^D-VFq{G5|*Jb^?P8fYDn^V6Xw`KSxy67mb5!0_EGV zUf=oTc_|uFpQUH%zvlXq>3R51-UhtY2*B*m5NI<1{8vg~gaP2cN&+Jd0RI&TY;6Ge zuMdHC1HgY5aqSvq0Qj$wHAWi%{u@DH8w0?9+YlII0Qj$(w?bnL0RQzQu&n{$zkUS9 z836tpLSVcB;J;=9+Zh1x<5SYXUV{8zcW6dlo8gU!SFCIitJP%ay2< z<0Q0lbfud8MfKj@I4imZYB_}OSTESL za)S_i*DFr)U^Xg=sr9uL_--AvaRjH;*Z$jwl+@n%OISVbq%D_3NsY%!G``JiiDw%DM&daJ&=Sw6_lBZ!@HRe?i!&pMzf<+O^*(h`;);5?BPIS_1N`zx zfD=pF*83D~rTdD5>*aem%+Ytzn~9_AgRN3{^^jxlg?{iq ztv;B53T}?}d;0PJ{QB&Hs29sJ5=UH6uQsGk=afDAq4ui!@GI0Wwo;|2!b3HtJ|2N_ z?Eg+%R@DnyiSu^TaM`~SwMh&tJ{(@9uln%Li(^o4vjJcRR)V*Ods9$3=sz4~?+(wa z>)_VRd^Ftu8v;3#K@7a88r~r>u=skoT5i>Av@dW|FTODVHcKZlumCYIZ%16a+RBg^ zSbS%ID(vY_;Clm9S{V`p3lIbACU~z#Vqo#30q|ap#K7Vw1LUpDV+4LSKsjzK2>izY zWme`&j^i%|D77+MhX8&v0N%}wBk+d-vQ}nC0)H6*FY9(EU^PUB;bq-#1RMk4v1C29 zxCX$=crZxH}7u$F<9k;K3vZvd=}BnB2B2G%vOGLjfrR2cy0JBfh>h=Fwt ztc)ZE79a-J0Or$A1iBjlBaSOGh=EsQsstnk7XKcuHd_exP9oE@!RJild;&3W4>%@s zE$7*QNC1d|GglGV$^aO85(A6D2EaI8L|~`^O0441+iY)%;Re9VOA-T%Mg!ob9*KcP zvjJ>nCWwK@!-9aszyid;>{CEuU;$!ac7Tflh=FIKQZb2v#n=YD6bcHk#mENlObQ?| zuxM}4E8ort+7RO!e2S(35CdO_!%QOuPcZ^KC1Cpo?^y~UF|gPn5^zE*GCMc;6wOl^ z#K4If2p}=AnA)IEWxNs2T-^j<-w3cVYe>s0_K$!VS7*HXY48T1bwFZZv1fxmw~wqt zW_E*5<+KsRz}ry;iGjsok&V&Iyn`FOc@%JJJ<8@pHvWUQ%x~~1ngT!!d^rUu3%U>k zXCB!K6_1Z3!Xmou$Odl%C6X9e92H6I*%z4;8hq-aL=XeNONk@~7F~&fA>iZ&&#r|4 z5(A5f7&w?c5}Bn9K1EXih=Hq7DMRvKalw{-THfG|rT|rTPGrGBqfznF2H!>r1%McM z8V)l_I&1Zo0xoaxPC;4lFqK{z2^dcAUDM!GGzEYd_$mrmxi#>v#K7pnjSb#L3Lr7C zh=_rMEFE%ZgHO>E0Ak<|D1gMkqAM{l1l-erT`VDh#K0mV1`fK@f(ILXilzV%0~b&! zLtka3@l!bW|r@%ne}V~HlBlk zKUwyCG_!`#)K?pPilzl127ZGA?&j2dx1rkv!0J8xi*(8d2Ef`goWN!SV5vERC(K6% zu+`Lgqrv-~I$vVte>Rj+T(CdSo=+NlT0@;625#;Sog@YpU5J4*ak}Tb$PGA$Gl#I{ z_r@=14afeg!JCHG!S~H5`@+n3PNE+gd@8335Cboxif?!x{1FLo(ThGj&Hma_;?E7< zos>voVDU>NaZh^f?*^Z`C=tZK?@=O&fkmRR<9&K2q#Ke3&^9`ap3?&oPv*ruA_fiu z4y51cQx_$I7&t_w42gk7&IrJQj!vc zLSyH`Glkyo5dmCyUZCn;5fCjrm5tu@RPi^RUfrk{o<*aO>C@;_Ic)?n@MBa#Vqh_7 zOB?GOz0W9s#K59|WaBZkaY&<2(G&n;;D(+MKw@Cg)+r!!BTX6^0S+#9hjXmAHZ?F* zPg2xq13(=7($MJb4ROJb>|s-+^FO1J*{0E_HPi`W;3d@AM(0h61PG|Wo@bVryrsnP zjoxjPNMc|yA(HrZZ)B!4`qV{=tiHSDFDR4XHfu&fyLr21svDtt)T!C1B>G$0so*mr#Jc( zO#vVVet`l=3@o}51H*!4jo$YZKw@CAJQ8pyNBDw9pQ0%M#K39zHA7-xv9hsdEMObM z!Y*9eD2JjfAThAGOj{RB;G|pCn4xG205R~66tFi3|E4VkT+=8QP{2zReqAKsJPye% zjTwrj77zoUiNjKwQA$yi3S!{vaF`)6uvi;8CNk@eM(VJXch zr6@`TF>nqiM`k?FgzvX>_m_=cGs=Rk+ffz~0|$H2#vdDfilP7z10O{JYt%~KDIg=a zMMbMATA6Y6;O{Dh-BihokZt1+Z2G0qyMiiOIat3%GxY$@RHwtr}6yHL;yr)_Th?B+*H$5MZ8J=O%)^t7E;?2{K~bcq$xw?Q~_e(5ttJh5(A4a z#K4)!JngEwsQ9`aK=qa?a!qnNS_kuZhglY>xS7)@Y|2nMy9#39qfn`oT`8q9>IE_I zTI&6gW7Riu7T3m+Y+c{Qdp>7ezb(Djy~%rCbQ-;c^0>r?_Q3Z*C#h6GU zFYhBMaoa8`_NAC{2GEWf2_8$TDCZPxk5qim%=o4ZmD775240K9Qg)@3%BUB_z(3$H zLtviRhRWGB5Cfl!!%}vol**_V z#K14&FhgQsaj0&|)j2Z-=bbn_0yyVi;CVKG%ZYJNllKE!2P6g-heQ)&IGu7tlTT%Q zq69JUU`&AwiGjrlP0=$d0)5^k0Ak=1QO~vUhJwVv;v@r9!)jN67?^}~0f~VHh=Ex- zATh8wxyh$;_5#Gf7gEJ8^xkq~G#<7;X$NqQ0r0T>G;5q^0JMf<&S>)1Qw52EMMMl7 z^yPVQev?n-Q~_e(i5ULOgB-Xki~y)u!d6!r04fF(SZM&bavX>7Dg$7;4&~Xu$^dwt z|BTDTY6IXVyPlr7+5qtW548Il18BQ1Zt@O?Nx|V%cxmMQli2dQCZ9c`-5>^DPP<7A zEN(Xf;;Q2}HhFhZ0EvOc&5?kMDB#W}pQ1T@AO_wQkRCn|1MAT;!v|vEEr$=pz#70S zgKsJ7Ap_tA)3-F@VFTa=6Muan9x(u3Fp(HoY%l=cGLRTpJZb>EV9FDC%m8@7L}Fk8 zVqmQnFPK*FEZArOyqH)`e?MUWykL5O{(jN`c)|1}fu{_B7fi1Zc-jDX!SpVHXAFQB zOg~b~a|Xb3KZ$|G3kJZupq~i5WB|MivN%w$7yxsJ#J~c?z}j@o9TEeJ*9?G}L1JJ5 zVqjeZGlRsy;-3b<@ufqsoSpnNlK34* z#cuYgixNQ$d>keArvSfM-xS~qp)QQg-YN#JA|7DG|gtTsBL01yK|NC6}U z7UhwE=(ez=+53YjBq=KCiQOKqEBJ7 z$F(3JF|de;frD?^r@qZTb@6!*#K50ZVm}Vt&}RL-XXA}#e*z5#zzn>F=W&w(@J4e# zUfo&^03+VznK04-m~gzw5$y)RVs$x9*~S1^tlr`3wXFd#C7bJtgswX777ST}+7s+96~~B(aKT@;S{ubx|USfgi`Awy_H_u(q))F);jiezW&EC6X9eM8v?s zww$ypn|85nxpj#SBNNRSv<++hG*BuES_?lb@{5}y-TV*p$vNDM6QG5{_TpK;*tF#xU!-x64B z09+GDA}j7S0M5500T2UgJJJ|1SAZD!C-gIz%lUF`v%WofjEf$Kf$1hX1H{0);#!aq zRI$+rfHO!8EIr>t0F3ad6U4w82$e(-13yoRBnB3*X>9>-g~U6}8S0`$5CbQ% zsOfHj7d2@!!>0S^6k3pqUT3$+J z)C*$ZBu)vf_j}_C(-RN_Z>bl=z(%hg)1M7s#uUWBx(3!z5(A5041hJXiomZ1z*nIg z2>fOMyk;XYu=w2o_$suXz#j&{oxo!R{xm>Bbq&P8TcH=h-Mj*Q9Ss_ZfyLiAF{7@6 z82BHU{h1|neX=Do6I~@Sut*sI_s%2+7HI?EyjsmBAO_Yw!+CWhfxrNmThDQtf*4rW zz zXVMS@U>r#dEQT8ZS4$EDizWl$;z(j((P9AJR=5Jh!2iJz1!K7Gdo6keATh8Q(c*K2 zc?}0K@b0)0W=ISyx)1|ro+B`!CAz4??oSC!G62l{g20XjfSGaV6;oO&r$e-Zxx~xu z=oW7gEe0hZF|e2!3AmIe z{J||gMNSdn>;fX7?W_ZyO~#>f;yooN8reJ+JAH2~~B zgY#{f0kqvGw0P&DVXzDBJ}I*MB6{tt7N0$$-5>`3mUfdESX^WTVD4Abs*4Q(yWgYT zmlyzcU&p(iOAP?KU*njqFo3>mKc~ejg|PvNfki|N9Gu7gT;Af-JQ@LF;F+kDAu+JH z)(C(RNzVQ23;-j3Wyh~K0F2m|w-YxQfM=vFRLqq`6TXEt%7-EAa7=SA%JJqCczk2ulR8UP*tl@o290We@Lop-MRFkoL2xX%C> zun8RF^#;%bc590_3MK_41{SwRcK^i=-rwT0N30buv5 zob68-0CwL^Bc3z>?B?VZPZLLi}x$-9>cl+ zNM!daJmZPyT7341c7qt0Z*4Lp1{SXw0kHdTUjJV=0POyh{(i#%u=_Snv^Na^yWi%R z{nG$?qP^JSodEg4Z2INp$cX(pFmJc`G>=Ar7?|J0G9(5T9~l8KBFk=lYycQhLNh-x z0F0Q;aro2#dZNA8;(bq@BnB4mM>;Q{wV${6w1zrC41C(w&`Dxo(S;Z|b1yygy^#o= z12|uQFaUJ^!twdh0O+3|J$_;6DbyfHkA*;uizx0sErGyBQ`0 zv-yi-PqlQ7+BjaTBEClvD-C(vD-6%u{&k}V|UyD#_ogx zjNQ@z+U`GEyy-A0IE;4x71{kDGs#w;J)+$p2400qnM(9SWQ_of@kshAX8_o}i8r@p z2GG-}sMULdDo6}0B4XfR6E037-|A0C2~~g?_g_=R!#O?bBLUxXl^WFQ zQ#1vD82CO4xQc?CjRi32YMxE420*WmCos|g7_EDFj*l_`Mr#}PeXId=FNU^y@6iYn z1B-|lI2g$Da9pcT^JoN!fq$hDBnB3fjexjv!-Q5Zgyw+6z+z(5i%lG(omzd0rT`EF z&qbw7EziDbMgUBzAh2%)IG8V$6tkbHf%#HO@9b{?ZS-!f-ucuyo2TR+kdmKw@CAP-_c5ryoyf%}^I5f*6=@@-yG{27X2)0KYHQDwZ0F zx|54rZ0Kw1|Ew_r8KmZvZ)5d!1v&=n8d*1ZZqbX>@RTk-(vtw_HB8qyVd|O zB*uw!ZvK?W|&rh<(;UdpUDd2PdOt=?NSbSS6M9nmZpM|a=f>eD*f1Y+Rv=!mwd z3o)>^X`_*7Yf(+ z>U~22M_|&5h!{BNPXU`-eTt?45Ci*wGN*B(e6ghkpR{^|P!^C3S9}(^)n&!6T78P9 z01yMOqJZ6q|7s=>hWZ!I!`}=5w|>Y@{$T)|ET^)@p9a8ClNeb1WdMvdh=Il5CJ%k+ z)eo(b@o&M;yxjk!4Gy}~LaQx9b7>Tafxo9wBnB3;Ejqzr)JJTUG(b#A6m7D693+w$ zSVY9Y!Bbf9M5--AT~rHV;Qpvo%D$FTHr0R_cs#(&RC>6qOuEfCT z!lX9uE(#zqu$UYP7)2lK+2&I;1%Md%eF`8kusFb2fce!xO|wm(P#F@ZwR!G#kVs-+ zv0o(dF*@bIHlMmE5yZfwQ7IE=#}79WF@1hxtN8}NoZgQ$7PM{g&ESwWZ#GrjLp$e2 zDz4%+Xuna4K(7dc9gA-jCh`-eruag^JoN!for#i5o@>}tu+ELcDvRA zxYqzM!lHZcGXRWuhYus`4FDrv=9zQ90kjc!w0UD8KOix%SQ8m>F+K5Mn@{s-1c-sJ zqY>9~20mc~z=-Lb22UCQuDO*hpEdxDc&{G7GX{VW1KH$R185^2Y4e_?5ueiHMr?Hi7;X`$Lw_@07f_*_%{pyBhI4t-!y=yoc&UpHvp{z5(A4@A{CYF z&s%Lil~Verb&3l|y{gZv#6j`;AF8f!TPkU(vM(RxCCWp<)3oEinK({s^rN41kW`OCz!dK*ztr4W7suKzCe@@Nhe31td%q{s?`M z+nu7yM)r>yP(q4#Dufj!28n^$AVs}@bV19lxBxNm zLA#otAb}Xzqm~?h5R}qCK{CX^`o~8g2DVV6IL9COROR@yjM^N3_0UuQ9LW#^=lDa0 z-dPd@3quT?<8KrC=J@l0`rPIC+b>IEU;$#_Q=znfj#2!Ba@Dn#H8?j7e}`mA3@i*W zaF)ct!Vm-Ju0oB5EQx`IAqLKU0IVs;K=$SwqtRP(3@LBRk{DPRV&EJ@zDMR5mA!S2 zk<{%uMn8|rk{DPRV&E)^fdzt1{Q`GILA=i{d0_$ot`Bz zurS2HSrP*a5CdO`Rx@)9h@F#T;OX2PgGlG)CgQ|CG{@M;!*YysJUmNcU}1=Xa|~Tv zkYn)PkvRt9EzB_#?Wi21wvNs*0_&J8iGhV72F{WgSb!M#XJ}lMV*u5XEQx`|sZGjD zXJttYEDSMlj`2_DXGsh!E^JaiWV;~8fTas_4F9<(yMndvYRb-rhcC`CqUX{qiGjs? z8oMIL=#Z5;Ms!@2V_3$jEQx`IXjalz=NMRVb(X}yBGViUOMw_T$5@H$vLpr;Rn6I_ zVe9odhCke#B{8t5Z&p8;yCq9vU;$#_lhNwd9K#tlWJwGx3^8z)#K2-wbM`yP*qCEj zz{@#)+kYiXVqkG#v$FgjSrP+_gPOBnqTXvceyjf=$M5SO=J-u~bB^D!Kgu4@TB|@r zjMMGoJikP55LF}w77sQn_iYq;ev*A!*o2E+jH}L z@f>sWe2*J<^L#CuaPxdIDcwBZ6(-&M2x#=({3;|Vw`wuTzehIh=G7Y`H_!Jz z#crN&UP|1mvskr*7&y<@DOtDb5~3Z%z$`4paatFC694r1UupRl{R zc|O!ux>dKau!9&l&&SGYH_wN|(9QD^ug0yqk99x{ybgn0>*o2?(+&YhM!8jwv#^60 zIM3&jF>ck1L_3Iqt4ItiI*5U*NDM6cg0UB)I3C*2<|JqvZ-E%N>O@|JI*5U*NDM4M z47@pRffzW?hlX?ADiQ;WiEU~IpXcWJByhf4RY7#`HZ?adaH~iREIZtro99jI zeQut&jqBY!Z`|&8^SpI>z|Hga=0P{l`-z9#JTKr6yLnz@A93@%s%>zqNDM4`j!?!v z>Q<2$So9j9&W6X_DiQ+=5Cczw?Hk=ZFJzWyDITL^;5GGIR1gF6vf~m^B^Q_y5CfmW z5(54vPJIvq^QyHaF>t(-7}%{#e}u}3mL5=)P{hEA)mQ?ZgeC@#=dZ@3ws)i%!_v-f zsC3`itoq4SI4$sKw;Tmcf->T-F2x^b4y%q%pUJ9kT!)P8a|Qm|@)Kqp`Q&X#gxrCk zE4}NHcrwQ%CVMc6%Y9gukVBZ0^1&OBB;|8VeEBw$lq_C`q)7gYxisFG+zKf>i!_wR zFJ0AP#%}4pQz7Y=b5JYsDE``sH}Tg=e1*RvAPxdi$gIU9-Z z$m5Zu9C-nfB1hhYB<;vYkYpS=?NaCyasd*AHe;U_!1!&K2@YYBHNK!Fbwi5bc@&x44F?k`9 zOibR41gF&oBz9cBfy9Z+FOi72bZ&yaxXdH*;&LF8SX_=l5|7KhkR;;rFeEZAuSAlJ z%e#^Iarq3AR9wD~q$nKh9AwNY@l#n-~N;)AQMv_U$np>bx z%Hc?CDYr+0xxPOVA>~m>Tq&0$@ua*4NleQ1Na9kygd`#5CrG4}4Yxv{loOHoQcg#b z!s2r|^htR%a%m~gMv{^846F>OdL)D8 z%gsoHFMmPe`Z9eX^!c(Ul9(@Bki>mC8A-yIvyez%zK$g6%P)}lzO=C8 zkfeRN4U&v6hhu?2=RZMWr{wlXoRr)jiAc$#khm$i9Eq2b*C2_d>}9{iBlw7kcc8V z8HrmYXCd*5H5+^OkA`xl1Hxf534@csq<@+4Jv^)d3cv@bGB$1YPBavx& zDi)7qT3&|4Ps=-zq|)+9Bt>cYE|PRwevc%BUCl3B1!=qC3(amwc}c2XGaE;H+ucrt zCE~AT(9#;9(28G+DHeA*;IWbEkETK4Gf-zG=5ozQKFup5tWK`R{89&}>Vtf8XI@v) zljOnrKqR-u)WAPCSq_=_=Otgqkl77@FI5ML)cEHo z7i*=dWW_3lq>`uObjQD<q7vNtyS&GF9|1!xv*csf?CVQfr_*as= z7;^#tg5>U4?C>v}+)=m6B^PVsb4j7=lqN6LNNMtSoTm6!mb^nFWywXD%J^5FT!a-7 z|MJPLbgPQwXsxs&xp0*#>X!UWYp+T^sf((UGq9H6Uv=_$eGn#3)Xi&>FW@x9zt9Rd zu7dMp|1S3T#Xa%#-{HJ3%a34L?O_MavtnPBb2wc~90CW#z7`xYk9EVlpe7Ofu6PU^ z{s;Yw{Sb15t(q&C`7vaHYZcsbq~dx`fuBSbj=c%^)BOnyL+tl-I1gfm#r`VpvmgAl z_-TM~JD7rumCbKNE@KC?kaM%I!z-~eU6#nc$6RO!r=cvBErRP}z3t#;P*vk*50kqE*P0=}f=+(jvv`P1)?}^u(9Hqe_L|Cris<%$^vC0ZTEKiE-MP z`#Ovn=d{xp?Yi+!yK>zS3f|6XSFU>*r)6S-&eSXY6T9l)A<8J5CwH}Zm#$9TFLLUD zci5dkn=xdj@k!u}==4e8?5=!rJ$({5b9pk=x6+JUq-@a-$dq=~obRf+s;lN6M)LqV zO(zo1$$RHp}>Fiaos3PgCsem7mnPKE>X* z(@#_E1#0fAKJU`izflBr@_CL*T8n(4LuA?>+Uel5y@PV_5>Dr|Jwr`rWq*klX$`!UE6HXxGkedrtgX~K zv3Uq(3{s2V=7|(BXvVDBsJ9oFzCKFACu&yqxr|nPQ^rN7&wD)nwv0Cd*1$h-HAp<6 z1n=D;_z7j)R%$JKV)C|7qJ=%JgjoY`Vc&05jZW=obmL%JqbuGVRczp7U8X9o@2I$J z5G!iw%Xa9LzFarz`}@VXFs-r6UPFs|?#kq?vpv0-FMwk2JiF|hj-rdBqQUD{q3A$c zT^`a0Myn@)R{F*2%e|T;_G+p_QQd($Geij;!o8X#_G)6To_jS(?A4@-thcLq;VUY~ zU;A_icProBj$1<ukS#Xq%?B)l~!aT4(lk#k+|pm_^e_Jt~QcYr;fE2`F@ z%D^;5iAo;ND#rAs4aKlQZDSQ#tbe#GWR1UxRzrb%B?&UE#Ohk;2dNwW_DLTMn`CU98y2Q5LZr z{&vWp66L`O<4>_-r80(X?qLNnewyWf7Jqi!wz;u#wz&% z9*Mna2YVscUNW^Ca{tt2CzTuz>9MzT*@oblG;(i8?d;%4ig_n$Xa_~`e(c?-rL8vj zjJ+2%wS(I+Nn)F#wvO8BGxmPe)(M8O?FUg?M{V>O`!H(jWVf4)VcBd4$I)J)w)u>G zWCtf9`>h-NN~=D$15O;g0L?LF&q{G+K&(QHUCz-V2X}%w&Q6LeW2J9wE5<@q>pX*Q zgILU3+;PP|vE6;(hvK81*e|w>#o)7xdjS8<4qUk0D*2eX-?as9$?{&v{h@P-lEpY9 zVt?vfs(j~d(38J(uDE;~=Kj{XT*)Zbw49&}3i2gunX?_$tDYtOm~(WlZ^@I?Aat&O z$@$E=Iyb1~an|&7Zdl1Tv@E7`O(oB?>Zvsi0C zwS*r+V=C?%}uKSg8}7fI{^83d$+dI@+D! zYG%uIc8nAJi`l%+j*sS5g%g~OwiBITTWam5B~NzrysFftyEp-4=pAi)L}`Q6axZX~_dzKOPtQ{442>Gb^@H=iKt$MoqM0 zPv~5ta5@1fN{J-B1ot0XF!B0OvZ7HfGRoGl!R9NV3rV2CHxj1c_Dr(O9&+Gc)TFr z#ZhX?bX=%pq4FtMYa?tib=Ls^d;>UE>RHw(iU2MWMa6MZ@azPFDUO(lGOtk1K2$u) zis^#S5-Yb7PzjEd@(fj$737WpQb*4~y}S_^w^D1UvRfCG&rnj8sX>)?JScbzs8X_W zu24>cE9Nj$UGS+0pFQGz3UV%P7E%Y$uDU`MuhHDCAT^6Xy#dlz>g-tn`Wc|eN_|hA z{SAQY;d%lC4B%U-HwbKH0BNP>Q^p_zB&^iF)H2ur=-I^C0EQR<-W|ri4>bV30e(su z!wleBsh6o`xB-NfI)P0Z41fU{%_dC-pm&^jkAinTI$m)y%X$^^?0Cf^%rqB#`i1n0C?vP%9vyTcxP7vI~oAqd7Hpw1Hd~YXz3IKz&mp|20I%- zduL?9yAvI+P$soU-g%ayb}9Ju8@)5NAaBBgoQhGvzJnlJ0>>Mm3eF&Kf&nV6R3m{C4baU> zjUsT80V*&NsCKad@>Xhl);QS!xW8S(zMo=%GAs2DHaXP*rB>=a0;d@uXQhrIaJm7q zR_b#CXBZ%`Qa=z_Vt^7W^%sFN4FEprA_7YdfR*Mz+Of<4m@P+hl+H2$X3J7eyyXVK zY`LDkKHC78Eos&`*8rF;qLvE`fZ4K?4!Y0)m@T)n$wdah zY&oB5FE#*X%k|W9i2*QMCQ;}L17KsRp{#Ma0XTi!_=190g!|TtMwTrsWhV z1)md()90Fk+#Z!u*Ac(Y2*C9Dl`5_`0H)7&H1kFS;8_VOt}1wkQANPkt0NV=GILA8 zr*d9i?k>nHsp41KvDREX;F?qE&3g?HQ&*Ea3f^OssLIwvSCi|h`u>7XU0e}17UU*M zoJfgJMoWr}s|9yM!4nw>_~}@bJr*q~2hpQX7kr9luU{!hZZ@BqN()|%`h@uF|p0XI;K*A%kPGp8T9;d`yaIfhCId}(gGjD;~v{QT*$6~){S-*=MC=g8TA-{R#(C^4+9?K z&lR#KqLS-Wac-RC1PpeJzg@^40Cbg8#R0X1zI)pV<|)^=T5SK~RoqRrio2;+aW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z z9d{GzxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$C zZbBV*6Y98|P{-YbI_@UaaW|oky9ssNO{n8;!Z+Y%AwnH@6Ml)DCqf-}6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCbX{QiWcg)n^4EyggWjf)NwbVj=KqU+)b$CZo*;L;XLp{9d{GzxSLSN-Gn;s zCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98| zP{-YbI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{Gz zxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV* z6Y98|P{-YbI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z z9d{GzxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$C zZbBV*6Y98|P{-YbI_@UaaW~;hc$=R{g*xsg)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCe(2^;n-`io~1(_cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zQQS@DGOUgX#N9m2>ywVG;j2$MGW`p#q}3|2rdmbT)R@Sc8WUMlV;XQ)41)YD{EJjft$OF_ASj6)+V4QZ**Bre+h|f`3IdCbFi+ zMAp=p$eJ1xSyN*oYidknO^u1HsWFi?H72sA#zfZCn8=zM6IoMZB5P_)WKE5Utf?`P zH8m!(re@(PWns4(6IoMZB5P_)WKE5Utf?`PH8mZPHHjs76Bc*Xcs!rxPa&$mSObaG zhv2VU{WMCg>OXJ89bolYK#Hq3-Hsc*>UR8XufFUK+z*A{vW^>80J0L{$Ea(i!b*H+ zLGmJH6^A#oN^STH>RW@tGg-4eY-ZU>HGNrT;XPID##Im?|6P0wtSB(ZM}Aq(mvUBj ze)yALmGgEc3i6R(3mO||-C7moBfl&Dm<<`^BYy~AVZ#E0eB_TI3tX#*doNNIex;hZk>C$ z4?tOt(sxD`bpz;H@ojM2YX~~)_pKq`>tE=9YIx<(sMl+M^gh*GQxClNm2g4osw^MG z`fO&MGTS>1nd?#57jMFlFJ|8AQ_5Bugpa~sn@nlOE@5fk!wx-yg_SI{EmWWqk^m0;=$Omj)I4DLH|cta9xr^FyKWVuZ|6T zh26PSdF5#|*lPNbvyku3k=bg_0rPO&PxW-5M|J0`ir;lqJU<-KQStmfy5by4K1*py z(s)px|xB|SGeKFLri94rB#oX z_~eIq7k%9wgCXbF-SQ(jiDMEEThXW7=v!^{VOD)xwFlh(CN>yWh&kT=C_z8)0?rci60B#%-oFP$GZ^D$eTV;v ztyy(OE%TCNFJ|;VnfRLz5N|pZ$MN|yEio(3Dpu@zA3uwjs@nIqP5Y^Z&h}G>DqOXn zx;5M5OLKozO(w$ zIGsFs9gvv(6n_!tejggkktmh&c(^(#m)?yzu527m>W>Rk~^S@4e`z%wmcBy=^ug%inEuUYDcN% z5661p?5%UQ|0!miGgapt|5;e)Ow&2x9}98LzB=dn2Q#;y&Ut0T8Q^!~}JY zFaTS}or7#yj^WWAJ47prIyOh=Z2upq;LOuG$A1k2?Hp-)$3lSchv$$x%1&`ky8b^f zA)KRiO}wET=OTNIwl79CpkN#*+i{Rlr_rF&gU}2OhoGBcuv3Q;_a*pT46WG%$Hgw| zx@q)U?A~o6j?<2Nn79xJC3n=Im1kx$@5cx3< zGV3rm+_@WO>SY{N@;UkqQlC*`Eo?M1M$BR{zYJ0up zAat>$+oPDFeR2~~fx9=AEPoLBzEM7ga&*tDi}D@>48$ON_0G?blC`~o;$TS0eSnU8 zTV<#w_X8yi(#MZrCV7L^v6aqy{pD+@ota2=u%ktWa{tb~S%RQZKMmaRC*gX=1UG@sP5xdk* za-FG1HxN*b>>wWI=~!f%Z$Mf8VK^3<39MLg3FO2svs27K5{)k_MgL<*X-P*%l8&;6 zQ&PoFEIUTesBRUUCkPTzv!)_<8 z?V4dvp(&N~4_IKuW@|mL>uFS|DyxJ$V%uv`q|h>RN2csyOey;} zt!}r~bZddW>bL303SD?| zR9Ip6R8o~W74{&Wc~Hs5;(P9UrNV z=keGI_o1poT3Rv4N`aTNHNFLo_5hY5V*KE_K(dS?%NAuVxld*5ha&JtsVMzrOR`d=%RJUpyyF zfC9G}f1-y46@`hr-PwRVo{j39HzA_Y-R`L@ve@b9kC6c>f@|;yLq^EK~On(IZD9);$OK4gWIbD}(wQa4uvT&x6H$x~_5$tvR{KZ0wW zQ<68Jx|@8MZBJF11bCl9|QJpHE5M5M0sWaIb2<#P4MXpfy94H&YGQ_;G%LnM1B{%s+B;gAu?3D0@)0Yx-v#%Xxl$G0-ir;dS^G=DHz2&s1W<38; zHpVD^%h^>s-~sA-O*gtPYV?|;tyPU)b2_Yj&DmNvx`5KwY6HKC8m)~CRE^elHSmGR zz)bfC(QKs?OJG5zS5`V|vRS#;DeqD(uUAxfsW!sO4P&=X&=!u43Qus<*(IlDY42gqJ)=hCE=Ku?(a+X03|_9te5N&W;VWLPwbTNl0AbG z^c;KL?s9Iw5oK!Oae=^Xip}qaKY?0cKCp9~k5-=F<%4Ib{|~!NLD3w|Inf+VxnpVL zLb_m`w(+OP#&x#trJAYh?2cZpv$s<=s#R{Ct!7V&TIJT+vpTI`XP->#_4;#PWUyLt zp3)hsyp@)%w2R(`2|LH5nPB%;o>5v?+JorZ5~XUTy^WHtRIRjkVMa?|)m8efM*5MQ zN@v;XBv=|rKP&2!5_p!~L>YR8KHD^F;5x8aH(Q5hCA>xfsAS#ZgJvGhOh0C<@{z1N zO}ov8&;}G|J5vxdDS=U(KpJHs#|&d ztvaVG z&$5D@Wl?YirS-IPyqgK$W3^s(sk+DDb@W)E6*saApXC_E$c}xcF5J3fpAAtRn}5I@ z;QD${aR{qlQnWAb<5>NYE`GRVD9=~=;gYec?`qw@WJ;$WE}7fuhZSA?a9I~WT+zi3 zS9bBkD(#1=ec6l0l^d#+8=lr)sIuAD=X%kyD&>S1ln<(u4_;O-sQR2ve5KO^C(;A2 zv*CHU3!^Tb*TngvxFrh$nF|G zvg9C=MG#Sv2#SIT5)=ef%os7Ef*3I8gbBeMQ4|zWF(WEQFyno{tNX0%=llCT&%J-$ z%k$9N^{T2G1X`Z>(q>Q!Zb?2f}#^=iDykYEl+F0kb z5*jBxj-$6Q=+#ryWoZ*GG))5~&r8rw&}b=(P4JJzopB&`LR%UwXl_Ei(aAJ1A!wp0 z%TFpdT{le}w@(w(_ibWk*hIxr4r4EK1-%8$(3ZU_xx}Q*^{H2Dnm%PFc`tLDlj1FH zv{&HO=8mP;kz1*4<{S)&Q)st&9dhzdgl8hro7J1}LxM;QH{B{(i4HrS-GQlZ8_Ih2 zAoj|2TKYdUbu%I4zCT=>i8;p{Ln%j%v)0c#=dPQ#~x%}>Ltq4GC#al`t5|2??# zM-$u_k1V?ex;DHMS7t9xhp)zS8eWa>L?O?-8u!eranHOO_Zq(%-+)3=rMq1M7x2tG zZ_m8*_8PzQ-m_2PW9<7_*u3-h%sX$-yz}Y%sX$- zyz}Y%sX$-yz}LXpj zr&nP$FP+aZ*oj9J+grfL5$_g|s5h;Weo_c`bG=WBQP*pZfsK0?;weRWTXC+vNpXnt zF3f`fuRms7ZiDb;b~g(D>?sPr1xMR!u^z%33M{uLv%v4`Sm05(knJtSKu0_m#i9+x zuD35@vD>knTHamgiS0d#DiLov7ubekpU2j)*l8$G=~Y5beM8pw_Pfj)f{x(3cuY6{ z!L3rndj`r!z2`t2%eetHBfBG%BIEO${TC~mO#(02B*+aNC*QXDM#jrLOQEZwknJ76 zo5L#74? zDL2uXC5Hs5Si-!W9~z|M3FkTF4GU8E;meaTmXYChlnTbE0+hkd#(}sS3zU(ajX)XM z*+?|n*+?|n*+?|n*+?|n*+?|n*+?|n*+?|r*~pWfjr*w@74pr_#`!qQ|L>iR{QutB z$p0TZ8@}1u_`0EEva=C%Om;RBjdnJIvBS>BKvat+8trT(8t-i6$<7A#i?JDBMQ*V5 zsqmg)Bv;yAy@h{4gR6p+op_#}usTRZ5<{Lt>gFI7P2596-WsHw#AK#!3sP=k6zi=C zQnAEwwBsE?3STWdfJN`b?|4!fs?dZ@UyYLju5@`E%P(zrGeG_&l_>j_ZFUoE{FXuf z?R?9$BLoq=>l|EUTam9rV55Ga9r*&nQM;&H3Waytamp?##uXy+ZLpoh{(o-kUYO{` zY{yDW<{OLe1J|&lS&LEQOOtO}7IgOrnKhw_o1f)u{Ab}}x*k)MMGV-)C|i!~zJ zJbwbtl`{p$rl;Ugf>(%mRN#it^++cFYeOi>DW@N zXO7jBsD$dE7cA;r4Kun6BY!a4M<3lqsXpM!>40On)Wo{jS0Uwf$EaA|Aqg%g+c;oe zbDwL}%~aC6x`a#d*|=SfdDo*jKHgOcLEfRb1=3cj9UJKKJ2T77Tk6A#cxi*qPHd?A zJaJ3dDmE;Cet=bMw9BtMEi>=LkIb(pE@PZPY>Y|RDf3qTC{w|)N>yx}TZXpF^ahj} zpP-?vvR`qjh)wWmCC5suSpVoalqvs?cu<_3syJo(WGgm2M%BviK-Xd;(=>Sbz36Og zY>c{<|3s&r7^6Z~CfAAe(igBPZjinoH@J`LnuqtSNNj{D zRZU(WWH@Dv2vW6qCm^B9s-MTPF7FZ~a?3g~aX=nlQs<}Gdv##mD@YVsOkcH?@=Qk9pM|KI5$R3Iu<(w>q*rX939C+O;G4@u@mB?yJ zErP6&t_5)3$H=IIqMxDTv5f$sQ|d0UJxF==Se5?4!0OuQICxs}7o_z8O$R~&?t>zTZcrRU3wrAEvB>o^V}FcrvmqMEjg0_T2Nlgb1O|^ z0CTFYXT1fkc>&aF($txjUKk{*|3n*A+_ln++-P%@wW<@WVbJ0bwGNU?!X&!6$2jg% z6mQXzgE>7=gWS$0apF3Y=tb|Zp54&QDUF+%CC#*{q1Q}yV|O)( zo$OXnQd>OpA)~EXgWDwNY$M#*-wnk^1jT~ZN4OnWCm4h=`wqfUK_cwlC~3FFnH@BaSledms?3WfzV!Vr+3uY@k{{{Kp--B&`L zNZ7>wXWiI~4HB~Zb}YMZ$6D?yp;aiMMLu1rH0X(sbvfussayW99;I&kfAvW3E2Uhd zjG?Ff?if#7)*$6~C;P9I-yLJ(wzy8BWM5ON0{0k5jG(!L(f`}o#|8HWiRy)r7&ut8 zu_F|^uJK6t8!x;q_Hsbq3DjtsC!Kl6*{3t_IHof#c}IYv^}Ho$Y4mu<8Tzjt@9nF{ z`=K5&hz#`j#0jQC=omjZp&l(hqd{H{G??0;!OPA*j`6ayk7K;PZ#!=Ui7M{s>NlMt z3P9JmM74OBtI!jH;PnlHpKy$~2Ojr?vyU6E-&gR4eFZ-k3T{!k4kGUlMCRjC9hm<9 zaJ0 zM2A4gbYs_nL1GaTty@jC^m&d~jw-FIOz$pmvZi+*HT3SH(2${Bmx*0zhM}m~<^rx| zr#Z1EP0(=HA5Ee(SY&=;pX;2`DaCII7cqer=2LPYm6Oa&&%FoewFzc$ju=q6;@z1`+^PPQ*<0GG8@jfiR23JI#a+=bP=d3K@nb9%J89;I8Fn}F%jIwq>RQ_Y#t7A#g}ykmZ}kW#A{?V(Q#64g(z zQFF06B`TA4@j4VZBkCJD3{%k;N2_?-Rke~rFN>NNlvO=A=$8k@s-tY?d}f~&ZF>O{ zR&`S%BYIghSOBVL5gChK8O_q7Rfn^KR|f-F-LIj>RpB5Sx4b`EOjTM}{kRT=AB-l4 znv@a!NYo34kNJi?A2vqkxGT!znYj09*PnhgHDX+(qF9D*YOvKGxX9GV2)ao1n+DPi+LFV2euepwwUlD=LZ(Lt4BB4d(UB8By+VpR`lKzBt< zC#nx5;j@Td8!_+or5Ddd@+`4KmP17`LZfv1R0wYjm?k!qHgW{jin$=rJbOxg8DluErxKy`aIxhJ-doQ2R=*E$eJ^Y47kVm%p{PpO2@=U6{Dyypx3A!0I4=<1egXS6JxpB6#FQ|Rpbq20#O>_y z7%8?6iIHLA2i6%HCQ4aspq+phTOE&LVs~41u@|1!JGExJyAPp`S!4QNGt9F(ZbVD& z+BUT4coy7^wZdK7k2mjD$Fb{>xZPyl*N}O8UuJgVo~(QOk%sf?;@*BNg=Cjt61ev& z<04rOuKRE>PFN%!fsp+={sG5yZ!l7SYmj=wfPbalF!DjP-sveyy5U%QULbX~k!p2J zP_3&wvqCW%=yVY5?p{5TZ!@gUeb|A^+H_!s>C9z)OlLZu%4RQU)3+hxf?g)0-6#x1 zPM&STl_n#%E%z({2C;8eM;}9(b4mMpoS(_M{Y|=unS>qxKx;V{o6MCBnHL9{?e>kh zdIq^ICF05mZntm5)kh84h`0)}CE|+Llboc~M#L4ft0dyeT*KP!8&cJpWxH+1b7?G$ zo9ZGVRopQMvMdRy%3|GitO3n%48B-z96W`aC_iG{{|`1%xL&&)qyPFG!Bp~53*|`u!axbZb zR{Ol{%;n3@=#GD1cINVBXLR3}oxUB#%g)uPo#4yPC|-85wFF;wM&)Ivr=ob-`7L-J z+d(7<)}W}o?9AuO&M01Xa*!kWeAyYr%TA`8e7@|A;$5G^O4oq4F&hN-6a6BZOJ@5~wM}8ZehlA@@+eaX!$2^a+x+#u}5MAW9 z*EfMS<+a7_SjN_@rhMda_sexzxv7tmZfB!gZqv`0=wcFyraRGw+qJ9{isf5Q9kXhp zY@;Oc0?z9)lx)^xhFB%(CEcvDfh>1W;aVUkRmH@u_(D0$Vr+lfgt*_@ydFig1v3)Y{l^Sx<_Zd09=jMBm6K=Sv^#riHJeXvn%WxuX9o(F|JguJ3v>)Suqf0xJC#iy z;j?eu8k#(!C7UdHiTxN|Fp1}8_{MnTR%#s4JJg?`HH z^(wR1tIS@nGJCzs?DZ6Q8?ZVYZCoD?WS+S`sMU~bD|3BN!Sx~dG}i_c`G4ip zTvXSkLijY-M%(R*Wx*f+GREUA*@cVa3*%n|cv}EI-qo5VHVJSo|3!j#1mN>tsaFBs z4FM)AKCu*e(~k1HQ}fI|@n$>DjexwDFt(BR!ks*f&nvd(K5Q^PuLXN};fKOr4|nwP zsb$1FoLYSlT+X6ijHzuw%Jn|NjEsC3r0^w8Wo+c5pm~?#(OX=o@!sF^d7<8SSJMCQ zT}l6c>`J09xKOu5?L66)+`x`C+Lg>PyOPsUD4*?EUZY(}Pj)4_YDGNRm1N5CWLJ_Y ze3XqBYVJz1L6-u<3w0A`BSx@^b2?DyoY6M+y-2BL@LOBGi6g%jGPrrEN$gCf{N=4KSEUSt^ z9OdKORp+BjObtS#aWxSFmHG|2T5ZQMM;(i!r%po2Ty+D^eYFSY3DpMYd6qK@f1=}~ zz0p`fEIL*1#Yv%0c!F1tj#-5}P&_)#V+OW4AU}Gd$#Dv=V?R$a2{*VEO2qKA!8?rz zZhu&BdUPG?H67?Uo%J$g7QPGW1fPMkO2$u{WjS4q0K1SM(ROO{IHr+8zGiUh@;L_4 z!lh`(IZ!Re@HmB6eTm~i!OdFXmQo}RHVIX_0OQ~sQo&}N+&~}m^`pU^Px6fyz`I4u zm|b=!%l7EV{M5lbf5G-CpWhN{Zi4_?u>a=zjKsiY$W0p^U$Dnh$+Xe&1$#D?OuvXB zL$RgizGyckzGNpk99F6)8(tO2pVlCMmA#*le@u|u{olq`*~hW5it=xnbt?iE(LlLr z;5IwK1|YOA4B;#Ygg)CKbiuwt7ufpDAl6{5Z`=tY+nRhtQ$J#M|p;*wpW9^ny z4BzX(E^Uf&j4Bmw!Fa3aY^r8vGt-4lb>^J+Z_cKpgAUAMrB-&?B$PtEITXJphtv0~ z1{rIb)g#^PBNkoL_gu(t#t)u3YmQ{OvLDys{BConQ}#6L-(%dRjIZmQ`;6tw^2s-} zpvQ|a*b*%YARR5Y-k(QykrlKDCR*O8^sh6MP^RtWRXLgEv$u0T(3^0fZNMkTT ztJJ;^!{b5H@-S>lrS^RoUeu6{hv6Vw9)|Bi7XJse@i5Hna(NhL4jMG~j#p-(oi(`y zj=?S4CAcl*W&D!`n1%lvpA{MmS>~fOZf~6Z*9V5CF>@piE)W0pfuS>qd z@yCSXNA$&l=3K#IhbE@Pv938sA))p^f-CLihk>hG#$kO>gE6R%N}#-}EirO-qy{~atB*)!4P${^)%G%gf9a?@k?xd3C8MD z{0t)C<+h%WK3!q!YoXF|REHi{+WJnYc9pHiV|=c*^$5tk#@2J7*R^<_NA>G$-5n)= z!S5zQ%5Gbq3AhKb259zITQ3Lv4JC);aWbM$0emu|_dwW=s9u2nevMx|#9-}=>LIB2 zO;o>!yl(+f@;m%wA>gj4u0ylmNA(>r%nwoh7)JERsNR6?4|Mde_;Z+}Z$pJaj(!L- z2Rr&v^kE48pxL30{sAovb98g)GThOZVmL=Q`lqq@IG>~YU|dEz`Z0{_5sp5WdOCUn z#&oo!+d#^Zj;_PFjB)fEsBn~{`(kwOb963LDsput6fAai1TyEkIu7OMxq1}FY`&|P z!xy%>n!iQ*p{o;U;UibSf$AT-x(d~|yLtr-_KB;f;m@b8ei8lK7}tZ2!4LVy^_P(H zc3gjglAGds2dcjl*S#_F@5c4hXm)d4pAWbtuJbS;@5S}!5dD5!e*`Iyd3r8Xdfd}# zD8JUzM`3uL@bpQjurg0~gXmRx`dxJMraXN&imcAlk7Fcm&eLB)>s#{lP>k8FdHQ9P zJhxE)jA1>mP~U>;`K|N~=uwkax(8aAQKFYX`IAd@CnzzqL_Y*2PASm|^kG(sz6WDA zyF_nA$x}=8vlyN^C3*`6d2WfW;$W5Nr_iJMC3*~$IIToKht^Lo(HbMaphO>vk_$_8 zA4oZ)L{EZ(i%PVOl8a09&8SzuLT|-LbYG#jphAxo`b*^XTA>q=(tCx@N0B}&^sSK6 zcZI$l)rV}*yu%y1LEj3u8MjkkfWaESQ{RX|p0HEzM3IR*^&0ej(oXH8*<*L=)8RIg zck0f7$L-8{9vz#}1m8BX4Z=_6Nppn^0pGPo6`a**xim`F1K#cB8#H zJlTp7oy(K`AaEW}MnKMdo;(c=Pvgn?7@^a7vIOca;0eEbWFb!$qpdS|(hh1YGAHQe zqB@WXXlpS~a$&nAJb3_;&*aH{Q0y$8>_)A#d2$(AU&@m_bp0HjL{a_HV{mdd$Ynga z9D{l}PmaSNU%`_$7@6ff*-qsr;^aHDKA$HC!bPwcTRG>U48P$a=V}Oy@Z@tiN|YyO zfH*w)0w*p{M!`X1JXwJb#(8o+20`&;4tk+^aw?3P!;`~t;_;*l3g_}<7#j6?vI?~l zJh=r!m&cQQm>{1goni1MJjtT10-mIxPa#hH&N41#@&djJp~&#Y7=y8qwYb;wyGK>+p8X@;ku#* zOu;^dih|Us8=>I=>Vx^Xw^4uLc(A$%TGgvnsM}qw#j%I#zQD42s?Ip?r4Gfhx4M5G zrmUI($$izv*_PE$twM|a)psXa)&LcQo`^(l@M6n{8pqFRZ*Oj2zyGRLYlXJUa+%hAel>M&?NMg4=;r>a`; zJQd;aTbm=sa6hVGK`IXJVY^sO{+KT=f?8 zpQqYD+I;mjB%G$YLc#)dFEn4MqL6=vNI<~KL=DIJnd&(3vs5|8{A~3rB%H4n zL;eNoZPdL;bwMw#RZrvmI`t;_XhO<Xr8zffPn zUSBE;Bm9*rLdhMfJ&s?i(;<1MdI)y^Mx6kQe5<}it?!f%U)`lTqwe?WP#k|ylW_b| zEx_?7rJ(1}YABAss29=VZq*jG_Ncd^?XPMa>i(wY;rP2c44V9*R^a?kwG96Dms*6L z{;hVPt-b1R)cr?Sz^}05vH^eaquH(C@A%Q|di=qUW{<`n{AhL|905O?-3$`&quDns z#PVV5XYdEVmc0`b6Tg-nMGC)`oyH&hTK1LjI{aGpCOAEQExRe~j9<%Mj*?Am{RsXP z*g7AkD8#RG<4+OpEAgk;)?@IesjXLFSW0Z&6a7If>QQjOA-JJLy>a;EZkT+$t3$!Gzo<7_<=qdo;c*^NK=Zltd8!sBhdm{Se+xR5#B z*3YA33v9g&e-@$zOrkSvokht-w*D1Eu-Mk`q7O^ZF_`~MTb}}z&ca}!`q{P~4qsVn z>z^U>99ut!3g6_33+~a0jUksVI*m^S5z17xJG03;!`@sO$*m?n!xC0%75_j6V97^0} z>kQoOZq$R6dtg5(ai6U}hf4RO0$k_;?3tn7gSMWC-adqmL5W9fJsYVTn1}SUtAc1;M+WJ=fdCJyL;?L6<9{hO*72wkAY<&lseb(0JBDEgwhCdr@eKk7v zoUJ#*w$H;VQ2qs5Ux4;rwDp5f;w4-6hcmov>*g2`yzm@|PQPmFJm~ToJQ*clw{IK&pyyUwFU1gifFHcN1=>eP+0of?{GEq-PN!mCZrz<4fu8}coFJZ|InEsd zsQ70y{T9xecpFjc?`A2MHQ%>2aTCB^0nqUU%KfKVFb1}ZUc3rmWkcXtO?tD0Eg)(o zdJY_H#UcVCR+F795fxxtiT*wDdumz$+Qz{C+RWVpm5Tp-1BHKYW`?$S8f)fcy+e>g zy_;n9Bv>*r9KWwtB=uufVi<v%2FE-hVO|}f1%rMb0>rojtS(DXA6~KB=y$xO`0^nh9ybf@H z09fw|mN-xVv^s_0;1EQiM4Qb3|B(`b5}mW|V#qIU&vy3@mDt7sIwb2+Ju1;Vt0RTz z_nxx=_i*Yx zMga8QMbA7+033Z#AGq;Y0nqzF`o_@$p!XJnV*~_x56ikAQ}66s$Qu#rJ)fgHF6*&J z)cd%s9#RCo-=GpxMF8|}%?=(f0D8|MI6(mPZpJFp1VHa+srN|&pymWR-V6bORui-C zY&2NBngexgsMTQ{lasR^^`%yGvsx8Ht8Nr9Uj#s_YuM�-)6)9NyCfK&t}?76^b= zuTsWB0T|6;{V|$n2!NW$vBV+)ST;tm#9{$~-m|i9d#F@Akb0jQ>OG8!C0UO>qTc6a z^$pZ}3diaK5dghUB)Cuj^qxs@kpQeDeS6{>uuK4^aj*Wptk@+2u$1&0j1rd#2(&so z>u#V{m$BF9gjy9-_T^cR`ckWFv-=Qjy}YhJ(-t7V=BYG0Xk=R>37Tj`othiaE{FmKL! z>=4zyE32^GS+U0( z3wRLg9|cUKfQLf?b2&gyWIc+efc05jT7rQq=YT#J3J9;yPiNi#Ag|cutqTQ=VZrCI zc7+07%j(e-a5?+=Mz+jc{z3sSW!;4oVDetcHf3IMoOXOO>rpf{*pk&BQNRW4+WRu9 zaHxEO4+Oxgk2oCb<2C^>#7}JVLjmyWBMygGe9q@ZwTl$+0u(La6~HOr3hNedy^0lZeTWxuwy6Sow{AMT zJANGU)@*N>E{!I#K#DW4^qOfFXE^5D(EjR!z6%}xBn-;KlC01buh?UKa z40b4~kvE?!>#l5+eF(qjxYTi)Ch=0=slu@={F*Ya8$2oA+HO(~=(fcn73@yUp9GKNov#=`KY9$;J@2Z-jo<1@987uhzwlgEqjTL@EAxj+&x3Sd?&;~#C z3!!M|75vc)qD3ea?*%o&c9tZLXSI_}wJXsYUW?5_ZGB$!P!?_ZuSypsu4B>NAeL$Z zl_F{Yj*$H^WnUFNl@%7D(NOlai5FPmY}1Ep*>!v+8b|1s=xxZTSOAo-*W?$au<>#z zO6fZir$D%sxeGb^PLpsl{h^z_%Oq50`er2VHi=v-+L5VyqHjZ5rK6wJ*FsXW(Hx-l zSq_ICaU#tIQ`qy(*-zV!MzZ|gaQ$+cy4iLl(riC!|5_D0XX903v#HeNEvX-E*7Y%@ z-zld(P(0eK=SN6yDW_RcK8mlS*K6G;(Q@-^Dd|10lIIUo>#YT*KNT-PWWIhZ-$}#! zsic+J3m?@VrgA`>%npwDN2yYJN+!wnKP#DlQn?v!o9i7Wk${`$u{fo)h<0E%zmBru ziaa!?^mqBakdrwNM$tc(@Z8Ewp&CCIunImR>g3~Z^Z_>TOEishcK{CYA`D|_vtJYQ zLDYlL&Qd4Byf7^&QnH{V0*z#x@hatvD0z3qbAkylhw$#EGHj^<#rPY!u=q%)Eo+|Qg+T~nUQ1?A27B%L0T zLq&re4pu8JE3J-$NC-Mg%20h%25^x;>K#<%&>?5JyU zL_4~an!W>4y&6`{)syY~Oa+ECwi5YM>@@p>PrqM;)KojoE;%KeY5(KxGz%&S{DcB$ za`a9>3@;LH3*^L~!uk@demUI|$AaX%1^-yN6mQdaLBb*gS>$|yT3iqDWobCe=@qSI z%>?WjctuX%#3gK{j{cxJa9OdUC&1Zr4vn77qMx%7v)<(lN<7P=m!J__-Hu~K{eTKs zCBBEeoZ-1|=0lPCL%}J;-Ct|R3rl#4G+}2ZP zOtW&1H+B4s4Q+BxNb}7?BGZzIX(o}E*+yw6nnZr4Ck32j5=}C5m^ir^6)4J#VPd99 zlxFsygv4xr2XfLu-%d62uhLA$oOveE92V;gP1<~lVy$=p;AkYBEl5NU=IG9k`Z#xY z;gEFxFh_Q>Vl(Ve@Ab$(x*0l5ukdh&vRPHtu; z1bF=mSwBB>4HEqt=iknLhw(EZr1OEsZLQN*aH{^@3dbNarR;B9zifiIf zV&Scz>)eJCacGEpDgI7Gq_nUe3B86GK4`^xW_~3i(!A(MW^Evat6ApfAtIfMW|6*6 z`UMX>3l}5TVQqZ2g1Se$Cx+SZ9}{KhnJ7cgL>YP}%Fr`WhMtKs^h}hYXQB)}6J_X` zC_^uZG8BPB63U^9e+b##_#w+{Ei>Q@AyIdjvvJD_(A-RAH?tYLHv#%#P9e){Ei>Q@AyIdjvvJD z_!EXQe#Z~ucl;oJ#}DFn{2+eE58`+HN+?+D`a%4TAH?tYLHv%td@$p8{2+eEPmE^# zjvvJD_(A-Rzhan$_#Hop-|>U^9Y2WQ@q_psKZxJ)gZLdkh~M#_Mzfpaeh|Oo=fTC^ zi~B+RjvvJD_(A-RAH?tYLHv$?5|mh(=LhjSeh|Oo2k|?85WnLG@jHGHzvBn-JAM$q z;|K9Oeh|Oo2k|?85WnLG@jHGHzvBn-JAM$q;|K9Oeh|Oo2k|?85WnLG@jHGHzvBn- zJAM$q_??8r?<6FCCn51W35nlHNc>J>F-*?*orJ{iB-&xD7{8N{_??8r z?<6FCCn51W35nlHNc>Jh;&&1fzmt&oorJ{iBqV+(A@Mtj?Z*W1I|+&3Nl5%oLgIH4 z62Fs>_??8r?<6FCCn51W35nlHNc>Jh;&&1fzmqr|^NR6135nlHNc>Jh;&&1fzmt&o zorJ{iBqV+(A@Ms2iQh>`{7ypRcM=l6laTnGgv9S8Bz`AR3m0VkPD0{$5)!|YkocX1 z#P1{;;&<{GzvCc&hnLRWRh5uoA7J6wD)9rZZ24yAFyHJP=9`_ve6w?ye?tLcJ@U=Y zVZPZp%r`rS`DW)Z|60gdm>=vMItMp_xc#HoL0pr$kr?7ACwaKzxv~m3a(~zbJJFg| z@Hta|+6BC2a0)JJfz)3?N);?_j?~{lDz|WWPrNMK8>I3JdouM;kSZ$Z&XRcbHVX}u z7Cg+99WgSS7qn#xznaVzstaCV3(+9euHZ7JoFLVyU;|6KL2Cbk@2OcVNYxd*%98OQ zb#TEwEU6*|%g|nZ!6_|~(h<|6eg(g0aT0>FgLGq|b(ML>H1j%ucqS+kU zOpu%uDSCo+D}&^eNYNk`ZWbh`MT#zBG8-gkM2coISrsH_MXX}ps?rIX@-EG@jK>wz z)6Nr!k9W<(xhDAcV9MMrWujL6dS(-tgUNnPvRy0wBy$MNq4<5Yz(F<5jRKO zO{omA&#)dr@fXPXT5?=G0}yi1_X;m7McAz)1p9Rx<7Y%t)n- zP?e7t;ZA%~%6$~=r4IWQd6QG6%u7xC42hX3FN+*1H7}(<&BMEeJ6Y&7kqE6GAXq2> zT0Ks%SOBzIM{t$^X!Rn&IRc>78wBSID8u*F5nLo7X(hK2Tq2;s;Ct~1ZV}MLN}fuvMnJxmTu5-I zfINI*HNias@FI2@!Tkb!D|scsLjrQGPuspl;)9e&PoqD5n$n$d8BI>u3;wwXfIm$o z_(}l$X$HYg0r00e1m6jOKP@EqK>+;eY=WN!z@IK8*dqY`bUDHA0^m>A68t3q{E13m_bq{I0Lf9g))3V=WLCr|?5PeTbj0r02M1PKA~r||?$1i+uB5)=u5Kb=fa zA^`q0kDyEd{An>kxd8anB?OfM;7?Z*R0)7Ttt4nE0RFUwptS(_(|rW(1i+sjBj_jq z{Li*G8 z(4W5g3yEH7kDf+0*Kf0^m=7QNM)(;7`90ED`{J>h>qV5&`h1T7t6#z@MtV2Uscq{*)p(R{;FU;#L2A z0rV&8aiIYC(}_|qJM%LTxn77|<` z0RD6~!Eyocr&-$ot`Y#7;leW`?Jk1NQcJl|%uEM2GWnc$SEoIioQAzIt@kg5Vdwk+ zzDfkZuqP4RBmjoJhG4Y-81@o^n+3qI?-JZ10ET^y;8p=Jtojk)HUTi~KP<6E01P|u z4}jYRz_7gt?i2vS7O=|Q0$|u2f_nvUq4)&gegQD-(*zF+fMM5jxqMgv47--#Q2{XQ zA`a-|0$|v42-XVVjSRsP0$|wX1WyWpVOJ15B>;w9P4Kh;81@c=X9U2o_Yjeacy)NyJhRssvVbdaheQ4N6=n@;!9!*ZezLM4*%V5}!ywiA11i-K@30@Zf!%if4 zLjVkWB*B{kVAv-JHVS}YA0T*301Uf{;B5gg>?;JD1i-MlT%6t!0K+;2n+3qIeSQac zPXG*i2*FkXFl@{30JaH$VJiqe5&**b`-%50Wj<_1YZk)VJ8#p6ad4XNbrpS7&gUck#9qQ5ZGi}u0Fe@ z1lIRe#{v8-ATa$4X?FyyntJ(bM{eg|d$lJ@8nH2t4xtns(d6W~t5e=-)%b9?O+2Q|{5^G;GUq%~*xxfo!5$B*L)!5wsQn!#+mPMgR=E zkf5yq7jdouz_7m%bPxc;enZev01O+Uew_rsuz%2pI}3ne*YgUxzW^9^ zEkTU{7m=T-gp50K=9M93lXQJ)YNydI2!($pqa6z_4=(dI*4F z&mib20ES&k&`SUedl5lz0WjWL1@@)xf`p1VYku?nwJMx z;ScGW1Ij&`oQ54%u5Zu4u*JLw8zB;5*j$3c1;DVq2#yc{!yZI1N&pOd48f5CVAzoa zV+6pk&l8Ll0K?u*aI^pz_7&dej1vIEPUmVhK>!SU-o02nrp zV734lwkg4>0$|v3f;j?|nV^T2yKlfmsZyG5aA?O9Ig{s=d$cg^xVT)O+zfUspbwuZ z0$|6#{{%Qo0PNU~C6)?+9jge=5db^RCOA(3>^P0!d;zfI{R9^ZfF19n|6L>ic0A=5 zfQtpdj$;Te6#zS~V3o@Sz>ZfCEEfPf-bXLLN&xJ5)mDIO1i+4m?g6+?0PNV4;CcbD zV?VBHHwu6q2NSFm06UH(SS0{<97}MM0N8O7!D<1p;|T;e3xFMG65JvHcAQ6WtAN0c zr9F6>q09fpLHv6prc>I5O^YNX?fP?e5o#VSg z;KDf<@JagzsRCbojyJ?V3Q$n22Ne5B0A2xH!OPmuA&6l7td9YHkrKEgoKGA4E&vbs zJ*meZQU!yDJBjzo-8mS%R5PlyH5}ny+mZOQ+~e4Dgd-JtbqkE}#T*Q`BD@pB=v+Y% z7XW|0hCmCzaNR)Q3BYizCh!GdxYiKl3BYh|p?#YOzyk3hL4g2_-#NUKC=`GN;v=qY z#RA}v_x=q~A^;Bg<7WU#0l8Lb-(lDxNQVF)u1Y>gU#O50ctP?$y(J?6rTP=qj6NbX81fbs?m-yM)N;SH zKk|0w2mu(syEuNMLlD8}+)r?%01U>EVYtnbG%iOcP~W3O1eSo_TrrQ45^&J_;1uzR zQUWvnP?k7WN?^1eVTq|y!Zs6pK!rOB{Z8$m%?E~q)0CIG6Dm9o8wcl<3hlRsKVHWX zoGk+2kH7y8aH;_K<0_VzBLMz*8^K%w7@XbogLwkrk9V`gd;##ssa$JL3qb_#cLu@f zA)x!U;99m&s$h{gpJ0)ICZ=a6Rk)p@bgGCwn-TWxL@KR+MrN zGnL|6bY+Fd9IKcOJcs{guhON!>nrqjfMkZla^t=No%l5suG7=h2B8{o!EuljRowgaQ$`=VDf$l1(Z?MUn@L{rhvT_ z`Y04C9nlN72397#W?<6JpaFaxjSbt)PC23J6dnGJtbxQp55o7D5Ku+53A z8P9mshHWM?`g)uuuct@khXN{*hv}4)ao1CT$;-_ISH3O07&Xaw6ior88T}CjTtxw8 zjRh2C+-Q3UFnLWw0sHYTCYA9hngX&Jok5{MgXWC|RAk&<6fl6-6$H=oDw>)@?{AUu zD4GJ=W%M`-=*2=E8Vjh-xMx#<$!ik|c$W)W$BakO6i}Pdt8iL6eDH89en2L;oJH_V zhcW1!abKW-@?TMB|4hkFYVa7B_JcAWMN>e}jQ$j-$t*SN9csXUa|k#jbXo8VZ00$q%@u3>S%f;9!Z7QUceZDD5#yO2kc@12XPu zZ1d*r$Qu~8IgO&mWISraHYaBE-)u9Vqj9WAM4QKQy*n-h4p#H?z5$q;32r7F+&dgV z6CN*Bpv3pQH#$+O;8n;)-vXQ@0Qas3?gE%DGN1v5=ID%@?Fcnj^Zt5VsOBCH^o)$h z4p7ax8T~K{C9gFXols&F*QwulVOSslH$f{|Vvzt`bZ#X$QvmKee_>ab3cwxBT`X~) z09>P=BDhchF3FD)EE5o1fltY}TdDV59NyWX-sf?aU6S$GBkFy1M#nor@8-PFT`K~h z_jv@@3rL!gxIE*wL*dlJl(;;U*p^R@D>EM3qQo^BeGesm$zI$c0wD1_g1ZG^Bns)D z_X)sAzna2g7;{yqv6cBWLb;jL9HTQ7nZwb|G!`7e4c4f&^QRxdM9+&kDr4hLm( z*u+4(^!AL$#@WQz8GTG=G%=M;ebbK+vj{umHL?% zCbu%Uc2se7DXa82D(riRJUd@XP%8jy*lLd7fdVi(w-X#J z0Hd>oLw<+=OsjKf@OlAwce9M3hXA~;_>wYu3Bbe4MRb_H0x-h$T=M$~z{AVUT<`ja zAc7VC4uSy!BF6tJDqW{5Y!KnlRE9Pf$eBE_(xY`~gW;8WKNL#t`3?N=Pyk=|WVy^7 zA;2>d2UofyDe-BJ%g|8bl^n*=l^)xo#0i!9;TlMMWDEGDPym;MCkZACfK}HMOc4O9 zzC>`m09f@6f@uPv)jI?y34m1-TvBETz+5dRm?;2rwZnG+vjkvP{D%gZ6M_h?s1NcI zJ6B4;s=Ig-IbQ&*`U}D70$|lY2o?%}RUfB}MFL<|MgLnO09LKzR5(ijR{d@SO9kM% zJ)1**t^nBm;>`dTgaAh6b$e{3yA{KmTE`XVn9v4~@DB9CN{`mDN`8n>Na>Ds`1l=z zH?1_IC7m>5+*F#8Nx5mpljNrvd{C6;PIYOTo0jP`cepCk+zx4;=F9ZzG+)KGOY=o$ zr!?OS?w{tntGYB_xE!43JAnE$A9j1C`C!;D&8NG8X+DxoO7ppDN}3Nx)6#sxnUUsW z%B(b>HRh)Iz;Jq+cm0dfymdb-&HL|j)4U_TFwNWAOVYeIy&}yU%&XJ9OI(rWt=`Hs z@7Hcl^A2iFnl~tSrFpr(FU?EzLupfg2gn*_km0x&bKW{F<}U}oG% zuv-9T#;pW<1Yl;|P4KG#%#4Q!eiMM1@dUx|0x&by6Z|0nGvj4~KLuckydItq|4RU_ z7u|4U9^WefYi3^p_z52l92@Tz1`|XCU=clnz!88&^bdlV0L;I~*@_Z?`8Ss(as*)h zEh5MjfcaO=DhUCYf0GFE1z`S7BPbAn`8SK8NC4*F=>$y$VE(;KyO#>U{Cl6EOaRv1 zi&!Ns05@vO2`U6&A$}zaP$>W};g;j6Af6R~*Gk{9L~{Xn@41_xr2vd0X8E_R+;wo3 zRDVp}_^wvL^>Yk8wz}GzQHMhCr;gS7n}gv`&n3b469HIhUnS@)0RHqgK^Fn=r}qi= z7XW|SPS8~V{OK!#8UgU9T?DlP;7_{=>IA@_{vtR)0Q@P6r6qo#0Ql2v7vLZP@TUa? z{}BLxI-8)I0Ql2I1lYNC5ol zDuN{f;7>OaoFxGMbQ{4^0r01L3CQ5nL?*{&Xq9wF2Nz*AT1_0DoFVaDxE&)9nN+1;C#! z;l=1C0r01*32qh;_|x&#?l`zgYBc?6TIf&HaaR$)wc4Yn(VyYgPXzZ1pg$2jAb|cv@Sp(t6Tw3Q=ufzVi9alW{zUMI0QwWbqXOtp1dj=TKi$O1 z^|%1|(+J!&#h(yBe?SIe{{3t;ncq!$T(6aasEgWx9t@TYePeii_K z+D7n;0Ql2q1iJ;mpLP=L5deSsk>FPW@TcDheiHzH`iJ0m0r01m9P&Q|z@OeI0r*P* z{An}6UIFkYexX?0Y8`eC{&Xt`G$H{0^aOz;0RFU*ASM9*^fzTF0q`f6H+DG!;7?z% zO0EF-)0Zrf5CDJLMUXE5{eIM9o6o&I4!4Vms1_9q$s|#mEM5U zG#?kNG;i{pG%w96%>^|#O|kh_-sRM@u62|G(4UXG>c4STI(P`SFh1#O+Kbp2p*KL| zp9)~Rk@(iGZnih{X@^Ii__nU4M!9ZGeAd<5hzgu>-*(l9^~DI8Czf4Z|Lck6djXhn z=85G80hn>-iRDKDm~rNb-iDkC{%sBJJvPS@BoOxpT zRRCt3d1CoZ0A`$dV);V=W}JCq`AYz1oOxo|D*!XjJh50cVQ(?x%o9sQ0A`$dVsQk( zW6TpvOaMH_Jh3PN@EG&Nk|O{!&OEW?3c!prPb>)mm~rNbC0_t$oOxm?5CE?;Pb@_O zFyr2@gaMlhz>G6bETsZ4T^)1^kIu9PzO=!Bl4C!%cMn z$ArL!*En4O#)lw=mqeJ`N7T4`*~IA1$QxY~%4<_0LSSB7 z+40#m?xmFYd>`b^2_-hKMq*)&$F?YOX^p;{5|80UQ zzs93z3b?dJ@1lU4Dfsfn0xqg?`QAtXbQNoMt4M^WKL`FRgDE) zSL5ZX#>8tv4Dqa+|3j)6qkkgBcXsSHF&bdqi71)P@{jMfF$Nz{Q1TL zo~dz54ut@ZU3fMW(6SbZ7i&CNrLO1g1K?)_sNoexN@d5enEye;ixu zQ8Wcis?{G*z%A_4KiEF61H+_C;+2M4KAp4H&8%(E_N4%0;bc#m)Cj}O#v%v{f{YNEtjAhYBRx= zIuLMmt#*b$z$NVVwSn-|06N{u+B}M;fZJ;QN)$?tq495TEMRr5?o9!2Qur;QfJmG^Ia;i~IQIz^%tv(f}$u1pH_~FL=y0_N74tc3|bdLMOe$A{$;?Y`< zq9|ZptiktQ0j1w{fD)A6h#4_*ZLPzz+E)>myHE%uhkDxzy^BLr=fsit|U8Z^C+5XZK`!& z#%Vd#D5oe&{h?NWfzxC^&V-+Wns(?$-`2W0!yvU=J@R&i!+j)m{H4~TC<^$iR`)}p z)A z`FFC3BRS4~U4y44&*uEk3jv?jj^c`vUzgdpiFlpf$R^rQst)u?{m!+hNnIWrXA`A$ zequP9_;f$;vVEEu!fBV@r-@zl0OgIFD5}$4P&;)J?=YK&P255Esi@0i;~ajs&h3Xn z-5t9McJ2zIZ?FHb|+m)I-O32WSFHBAQ^^51Z8Jt5^!V_0g+WeRAdto z1(8Km5D*naToDC9WEa5=H^c=|_z?FUP!Vwf6h*-u{nUF-RSMy|f9~aZNOhg6I`3O= zRabR)I&*0EXO30Fe6YASwqxr?$3@TKj63Fur$k=)i=+|=*6o6oTJTPV*Jg)?|)*~dQ{lopmj3NO}1y=ZiZ1BP!Xds zniyQ+Hs}WvpKvW6a-4~^oO{ELGck*EZ}^EO236SI(K^|iC(ZeJ6NQY@h>94EvuoWe z#1K@f#jez%G1|SX!oDAer5|!}9jjXMye#d-tF&=>fOGy$o@ZB_I59?5h^=UyoX2%; zbbeyAVo=6cI5fsP$|)7L?;MzTk5ld1ihrL_>?SZx1AN9zV7dls!E3zVRv{Xob+RS> zxw=B#4Gv_Oud8rqoV~cY!X7~reHp!5w9~js+ecq+(*SO^x3k6_8bE6VW>$rmLldK0 zqwJ=9FBDq#4 z|56R$cI-e)0LwIhi|j^>#BvQF`ajX{6&g@}-(4Zv!=>an8eEX~dpcXLs&LpN`u$La zeF6P$!`b(UCQ#QfYbwM{63k&=*X9Z4li;xmhtwRtXDaOa1NHDds|N>P5y;_tP6K-Q zp4R{#85}0n3mU)!ro(h%lLqjB=?~U;Q3H6uWO3WttN}b_h!S{719-qxLf~Z$-~m$^ zfh`)q1Ez&M3$|(i4wLN1m(@-7rMS?mP{j&YvSOp3$FFI2>V4gfA=X$sEUTIDz;5I}u9vaFsov z0lz#YKC2M-kx^FuJU=rIb0Pnx!l5lP9Tz zEi&4bc6Ty1CV^9_E(+vNjj=ISig6^kj2l<5Qte`OxKX&34yj2{v(mnW1n=@1pg2#E zzfP%9DIO<*!|gYbC-|1`c$E&RNl;d4e@21>>{EH3fH#a+(WUy8C-kXyrLYEpaV|;H zdB(%+Q^QJ!ws^nStkT|yN~I@P0&h{7e`bs)nvDsx)&OSUI-bWB8o(1xKCBLAH2^1e z^Gs-`0Zh0$>}RzGuvjgkD;+d|#p)BTUY#|7DfxO8fG!%ql>D4Ex@rJU<0(XwO0kDM z8$cgVtyH&}U-L}uR_U%_hdRB@$=Yil0j#lq{XlA!TW*~+; zPcQ_-jY_2xNHFYQg3^E3tq~faOJ?vqj6WGa<#fFu&zPm}7gaj6MVH1_+DpiIBN@l# z2{5NiJJ9zlG^3D=qbtQ0GGChG#@2<4(!lCkUfhN#CE{u=3wce>q#N(*QP!t*r5o2CzxIN#J1(V3QcZ^X(B0V3XLv8jorKo5W`X z9@79eiLVK)*8nz&BLp7T05*vOIRH;;0DHn=0#9iGdxF^(zy=NAdKyGJa9%esYZQD@}lINydE|z?FgQ=Y9>;k|y?4 z+Qx-2v5yHSkfxgcVTJsjj{DTt{{bN@{RrZRZ=;~~SK3w(hX*8Z|LPP`T z>eU3I8bDWl$pN z0gU4c0*y7my^z2u8o)SKasO?q0gU4!o=MF$fN@+wpp^!&TRuskLIcmIZC@qM0)H~V3+#?nYP(&*y|;IjL-)AK53I6prW1`g z;|5i!izDuBSMW07{5-&Wy|=h_T%ZA(FoXT7#A7tkh*!1!tJLLFTV@7VIW$fa7ggDB z&_rwQ+85^u1V z;PhJVI1@F1!P!k;CTRdyEj!@ovZ;|x$NW4a+L*&NR z4Z!abIx$-V@Vgl!c9RC+_w6K|qXGCmi}USf4Jf~_trA1vQnD}oo}Tx6KBG3b%3+V_ z_q;0mCHg&^<1k+n!0%f0>TV6d?@#IXJsN=Dt9aG3Km+jm1CH534fy4(xvfgJa_AnN_`J$q zLMIk*qJ60e;6#Gm`bqTu(^Q|`cVV0*@W};Ck?>n?;M|>HGqzv$4UH)1~6drNcyV=Fko#s z2ESKZJK>IB;p#2VLK>Hokfc8720qwV~0p<69t3(U9l)RjN|DE^yd1k^{hdrX-HL~_N z`kibCJfR5??{!`1tV828kjkC5j8jM$SPMne_$UjPHm=!0X zEZK_FqfwsVFjuLjS%=glXp^;XBEkJ6uGAjDrR6-EvKm0IrxIwV0gTp@JjYMh07k0= z``$?dsuwM?;t@L0i=k+hcj6SDhi7CRx<@B^WbN1JL?50_JvBj4F3MfA;s+88CP8-{ zSdLNetV3!N49eQ=E(JlFXWs>y04|jh7@P-um@i4vT&QbczSLxNhG;-JeNI*k16^_? zPsss!o9FWk8J2bE4Q-Cj+S6!rA5XT+w26RpdSq6tB*AI)b5x$-D~|futV3!NOwPLR zlAs%1x+bf>HZtMk6J(sC0aG$g$lAY>u@@O9DQn5E8OLk0G1?;I4OzGDWner~ANZ_1 z0bkpZCgx~H)yWxIy9+8O8*zHi%rmwi{mt1JZSmsmimW&vm1@z^TI8mg`B`_)F*ElZ zXXZa_y)X~pydc9JS^H6%xrn`-mp3z%L0^=Ok(-Rmv+iy(N`jS|0CP-+;(-$#Uy`-W zF<^X!C&tn|<1L+$S(A;?7R}z46-B62i;mVJH_fci+BX0!p~`pg3Dr`*z49h!|C1WP zWal672tK6&I1=DQ+K>k@k-&kCSy#Z{+v$ymG8=VX`S5U7tfiwZIE^07&w?`;?q{|4Q_@_=g4%*3a3=|7rjy%k`}Bmj*D@o%!eL z{?-8E+7o~G?H`?oJQ`>}zbJ>3W%SU<#po`b3g+A`bZRGiYv=N3Je>NH zt-=}zNJf9o{+f&{xXg;2+((nIa3hc8VzfoGN3!BC9M)oAYmu8~3UhYpIG8z~5iU|K z&HScNkQ41tmXu}joZ6>6Zs8?4hg2j;=j?MyP<#sTvOEEHc3Mp3#558trCYW01Y7A= zdCnm<2~Nq`i%2lE8Sthj5;V$*%_Ml01da0q8@c2)&pD(fL1oU~O@dWC53?tBp;b

-WCPD9< zeE|s;a%=9JCkUYoG3b#KGfD7%N0jx<6P(T%49q#CCc)60{TK<3)(1X9dw}`XnwCcD zJ}Jfva^gcW4(5!xFwgihgK}}sp)E3w&DoSoEe$pYK29@Y`uxFGS7-op`a;&2kUQZ! zgV8xrf!4_<>E~s66ZdmZnv`>BoF=B`?7lS7fpMRv8P&*Nl@nKyfWOuaUXv#{+5(vw zIfv9Fn3J@VWmIlvc1aw`f33@f&jDbu!MOwOM(_w;CXGTh5^^GTxK350G(Y zGvEs~fpTeHPDCbvpan;Hex6`ZLu3}^98!~DMb5qyl}aDydA(W_AWBUbi3c=*1$774 z!8IDd<->Z;ss}ZIvD?=Iz*-IXA~^IO-4O9J)s*p2*op=*0S# zz@O3t7`uL)gc~#fCk%%784bXRPk1x3Q3G(|9iBPQYCt*hXigMOgcJQ(wm$E~-HgQZ zIfw4ii7h#M5-OFhlkp2p024MVeyIVNIEDTEN&|@gvz!zAG=PqOM~?j( zK*u+co-lLp|` z7@j;oYXDx=r4zqs0A4-DE3IEO0IxD!ihk38^6I;sXas}Fi%9o<-m9Bf@o3JWzx2vz zYhO&S{%H!_*Y@Arwe#6ezXsryMVpoe)NuSaCvKsMy=?t=-oys>C(zcRahh=3+JDo; zB6d8c3DEJ;tXQA{n3zCMYiIx+f05qCHGqz9pc4rVpyP*l(^04a)p5J6s5=>6oz0WY zX{$E5{-i2u>(F0%RjaLi8Y-2x>kK@t2`o9wO52LzBpA%`Oy&t1@zg47>yVlRjoaGO zNzjpt?J0SJ5Xx#BzF@<)Vl^3LVWYOi8<_cp&NpxCJWqz2PvV1comx2f$24p;N_VH6} zXqV4yuDL=6Sq%%5=$;=lXxs*7=7b2m>aE_E==)N+aW2wFFQ1TFFl&AN`}Sn zVZEE$Bo-h7!&7`A_RWUO!U7V2O z%X<@3d=YO_im#$wnc`bplT&;H>#F!=Y%#GyM&#=FWacJSB-X*tDJi}{H9J0&*!2}M zN^|44GIxWje|w7WKiwIh!kKwjg^bp`6kk}nE5+A;=EoPZ_T#Gd-6_7&vmic;wLewZ z;uPNwS(4%#9rvgBTE^1&ohpx?*2c5E7Hw21$7o%=Gjk_bCTh9-OCWrmVRJmmR%cbp{=OV<#$1oe#AQD14+3o(caiL+n;ZJ{pLvOE6v9#39IlPq9d}><3cOV2OdRMn$Hc2tu*h# zORU1>tg}wFEVa_S!}hE+Z)%fP;lnI^Llvg1G;b?wS!v!J*0$2T#j9f#KEpacWD}z+ zuuxfP-t|<2U>r_&t8fboy`1!*JqUnyvV;XY;?<`SbY zid|q0ZKlH-k{MRvv?eG#P1U{5DxAY?buPib6>zu8=7rm{R+^Vi&sk|+-aK!mc|GxhmF5P% z$x3sRebGvDSKDkA*6IMZ^0qQWFIj~RnXT7Woi$cr3uf!LP55zQZMD+e$PA(W#!Xj5 zP5$+pr}3R7j%@-p52C_wUE*S@u!KNt&uO4)+1AfpE3#lIGCs^xBXmwQdLt&|y4#R( zUc#s8?8K+fIfPHY0SUZV7e2K1Wk7i zl91^xMPi$-aVspDZV?j4bQ>dyKrbDMYq|rFL``=Ll9=fZoDX|GcPtXq=iY$C=W`b! z@%!BMNGzZG3KHRSKSdJoxj!KZ`ds^N*z>t{kk~%A*FCW3b4Ma^eC|{v5uZB`iR*J8 zL=yG6FCvNg+zS@Kp5L8-#Pqv!kof%Wj-|l-?o#9|zxy3>!teT)!JglJ8eq`xzJVm< zcfUYl``w!N!X9d(isN_NA{X(yeUP|*cNCH+nlFbvzuN$bVYzLQn3mfIiO+IJA@N)8 zG$fYg&PO6FcO8;|<-UX@Xt_I)ge>MOHWE{~Es^+y+ZBmlxECU^ggXg|5bi+?V?elbkqZiUIg*fYpFv^^_w?1U zC*1x>9O1so@e}S1$hpE@gd{55^+;mEeFKRRaKAue2Hf9~_yTV90oV(;m&1Y;aLbVs z0k;ZCAmH{y5)8PH-3NOC_afx%fSX$bdjYpM5+~qZj3g3piza-T)wgxq(KL_+R^^~|~-Tz4Ik zi0i(D#C6@BNTRNL2uaL!{VQNE>Xsrgqwc9ld{MU(5`WYkgv5%vdrzg z77ckeS`#f?XZ$ej{2R{vH`;(&zlV?H~tv6+V5=jGy3=VJ-LqRnPDzQ8m)<@Ug~S zqgS%=j!)Ta-2pT+tUvxh)gJx;uNAZ(=d(8fABTxYg^Iplz!x z#3loxAE6**SoeL4+(7?K6h-EIe9YD*QF9ioy!Kz(diE$?{OJf??6Lj0PRHE}v@l#NGo`{5Gy z&MG?HOf9_=E>OM5N>|US`J5M zgBzP|7=`@HAu;`g}2ZQ^(e+-U;HBl<83_c?b z5h@j)@Tt*JK%DXDg5lhNPt*AUG50xVe!{@m2vx}WOa`eEqZ2YBEirug#-~STv++n& zHJk;%$q8}jPXw!zpRAEI_#oeg((swl^KU|>pLen948+KE&e}~o76M^8_k2e?_rp$s zbN*h$)_D(gs-0P&p6)J3kqV45D+KBd%2h~P&xICDS`rBbEJl}s8 zI+ZyBSAF3H1$Ur7Wv8&<-kS8tDEkESKfI_WV}diI`(ET0`$wT#JuAG@o;3##9yaU; z_&|}I9r&}P^*@A(@PjIEmKyb&V~&N_=JO>+gRw(K7~ysKe6dk~0Y)zTkjg`FrhXGd zIQ&SyJZ{tW{@3g*T|YPZ;%QBEI2``Es98ezvH7(%`Ueo_U9>Qq9yr-eXX;lxYioc| zIIXY{1r4h+PtVu=ud=a&{^Td;ThTT*qgm~*+4y@HFr9gz@Hq+0LCYxv5tg5~=-P+= z0IEiYfhga2S9A;;--UD0aNY-n>8!!A&v_o7SRpqu4tx9^*sRrmk2U)|x{A#2MFT;3Qmm#%F9tQBSj!6UB(%2PoXj zEUiBqt>a7IMXtA5%8H@*1cWEtN7anP&*x0;YnF0LDu{EP44-4Fg))BeJIM7nYjHs= ziGQ#VxdCRa#W0Y<5_oC_uL0m{c%bQDOOLu?tx1Q^GYew3!Uy9w6kT9u)<}<Ui=lV6_=P9 z&YfiZajcZ#(JGfRVwZA)UTXSt2wjlfI{90;&@?>OEU0}OI=LK!5FTe1aTPP-jp)!7 zD(8!T^&N8K%_6SYR{X_pk(;1$p}5Pki7FR~Pa(@Bl`Du3!Bh-iW5&r+ z61Oo)!_!nQ6`#j;*O?wq?{qv#>o=%eCO)6Dc9to3!?O4vJU?fvT-|sfId3xM=2#xT zgh8F7a`oc((E810IlI>|ZZI5k&2p|XjWOscgdld5@w>(JXOIb&qh2J1Ii=1DCmS6E z#3}v*0db}r7mRl{327Es7^j6y z7h|$G6a7orayepC;7l$s?m)|L5DMq&ns1=MD6`q}8ks?OUSMvDe;0}xSFqnRqnXW^ zAR*_*f*jlO8q}Gc;1H;*Q|Bgmb&6#z*$nT^-g%j_0xGU z{ymP3vIiXW@!5EM9$kDOjLa+XX2^ufCNpv$#VsWN|OL@*5H#GEPob9DB*b+Bq}UElat=;IacW_9`Wo(F#?QlS!K=t z=$eeE>J}HGayd(d^@A>EP*pLfZ2599l)sH5u<_`n1cSI&Q6CaUstek4m ziBv~7195CD1h^anZaP6Mfj;N1opQ~*?swGh?4OTHnGTq09V2HJY?zNZ{TVWmZrme~ z;q^hJdr~@4wj8HwYqo z4#Lqz%Vd!gouQ0IqNPhE5{cgUpgeG+d*~aSk1kMkqS3eRmq;{P^FDbHiw;;K4+^5? zxVFN-8qvEK$%A;bKYEORiRjs?Rbh07a=tL?S9NMe7bv7=^v`v&a#8eAg%m}nU<~lD zI6CD4c~BBPRkbROwpT_=qm!1(A}@MCSx-f`siIoZVQXbkt>{#BP&+zJHLnwWlczSn zh>y&E?AUm`5xtw^@$Gt)IHU1tIonZcIDf$*)0qpTz}fQ%uELyZd{#U6K8h;`_b}^N zZYdz#Vt+;FBX06>nY=}=0(UK|q}|_9-)QRI#G2J^CCjEq8?p>n6-H+3QV!I?f=%$E zZ0Mhu4&N2aGr7s-qsAD~L&f~M1Uv9(j79W&Kb;M-Zsu|HI21in@EaTchEPX;s?GUs zlr3iF=h`gb1;cAhS0hl-U;J<5IQSPnGCwaw^H{Tj)=1?R8EYYLMb*w9Ybp0?*li8F zu~vRQ2&_q_-Z+ro1A(YLj+>napWWN)5N}5R-Ni{8$4!Tzr|!}c@;B{+P19X2%Hdt} z;O{uzXa<&}phb_M$xPjk=y>x6So+*`X5a-BwR|1tn)|SskVUP&B=bBou#ZJsuqwIp zP3dpz;iIlF+`G*hTn~)qv%W{sOfz8It0`_YBZ_?t*{7I+B#PP$!S`s$)RC}Oz+?p@qGNxFaY)3UU+^dvjzW8{Px$SvZS{2geB`fWdana3U?j@K)SzC`BN zK)X5&`QgB6zkh)A32EtkRIWbDhy1%{vwv9c^`La<^f&%OW~G~(_$|_YftSfzX=8Bv z)udO=9%SW9bf2s`xp1|6RhF6-FQ#hLe*KiRQQ5e`=Qlbw3i$3cldSp)O9#fSA|rkP~# zbnYzVJ~NYzS#+_=G?zu4>%xnIm&`iMbwhE>@}B@~$xo$DucMa*x0=a|*zyhRDaf26 zTb^+Zi{4J2F%_qM!Pev%TToh~Rlqo6@ofC#WPF-8B7%``@YBdR4mQBB&kWcO5}$Y= zg~Sq1qaVJISdYZN5i5szN=a9^VpZb9XNH2P>>mRQX0y_v#Cs9<1^d{*2V-q9Tb52F zWCizQk@1CspCb{L7&T@B!EcfC*Lepe?-tKty^wWQF+yl@%>;h|_~miH;(8SfnzZg8 zY@UgRp`}m3K&aIQwwsPmf9QN5R%k0Gnh31|5(w?bXE4<98B`CoL#Z8_`Xu(&(3~f* zw1zG~X)NSNX+h|D;F-|tz%!v9_$&+EfzrC6Gk}+e?f_@K&}YD#hRW~>vDv&ctIgeX z=75i%AN)g?{>HH{WFoNs(6_v23+=?G2n_@h2<=0iV5lpOL!p=OX@{=CXE?M8xD$E@ zZ6l$RaO{Q_<2V{>jkdAS?f5JRy@b!*p)gAKhN{r&hmeQQzeD3t^Pgiby>9+SXF9&d zn6%msmkc}ZuV>oZFwWu8SS2GzVtLoUT} ziUIe=u0?80>!rT(h`Q`npA@1TjCX^N&%Md)_a34}ho0Bu8&-l!gWy(d?^Bt|bBI;97fm#ff|Na(*fc0-f8;aV*8Bx=S& zHM(;RytE&taOkpgFzG@Y&^8g;aV|n1`W$%8&>_?*3Y~m520K)Z&yvtY*eVTu0P9}p zY}84HUPGN!=vMI84iyc;T~X*2e5OO+!p}^o2|OMwhn!}H~O?w?&yT`PL zAU+FByDvBwn)a3O>t55o1kD$j_UWkkvuO_m%P*!q6X36=-3DfVGwt~Re@D$ehB3fr zj|cd?&;Au;U;FK;=?Wgmux-j-bsU;0=!|2B1B z%l;9kUq8$4jJTX*+0P)Z{VjVo{j}_%i0MGfZUmNdExQ778D!aSp}~2UeFmcYm}N)c zQlYTZaImJZec+rd>>!-KO4tJsv#W(YA9G>1u=$s$KNWTq7WN4HEj0g3*mco-udo+m zz&;oDrAWRI_ABV$J3+h0V7v$!wD*JMy`cR$YQ7(|zee*9f_5iF{==ZX31)W$?KuE< z2JILEvMXqR1?rE2_8zc2{Un?iUu;LwhY7{@BZ%3=V*6v%oK$STgz#KhZ0|&nCl}jw8LVRa1@!3Z zVtWvrxTe_N3hPsfZ5xrFT5NYi&1;M8&S05VY!8Qn(~E5rHD?stE77icvHdY3ar$C= zCmOV0Z0|=|$HjIOES(nH1*p<_vAr5BXDqhwL-U?nY!jXCwZ&eIX>;L0`(^}d$U*yl z1bOH|`yi?eJ7}*#--jQxU6>tl(4K;6bJ0P&Ilz$z!~a3YF0X;>lHDL5$AfZ2;|d-u zK?KJ0;C-~1z=N%5Gm!@!alTFB!7s3PB@aGEL?`p083?c90sr9m)jZe)53k|D97Jde z53YlIQ+ZH=R@d@i25e2^L1VZvT^^v9(<^`sg{>Jph+yols9;Mny%_yw(Q z;K7}+ej^WJ==v-k_|g21!8o`9$elcxhoH{m!AJ!8E*>;OWajf=FP$HTgF~=>H4myV zMR;Kqz6o`>cZU~%(8q(XFj4$GmJ(}ZBaz8!@qQ9FL3ZSV(8<+8d&%9U>G`R@u1Cx>;(=w!f1d8lVOXs!oOpf za6yKb&Tv}zcyIolve}m|rAo^8Ziuo0}A&JQqX_LXs ziac9@X%$%#$DE3EieN%T#?-)Uikwu4`4ZWNno}b8g6G;uSs1g!@aItMZ|T1Ybb_3& zWlb^t4}=h-GyC*5tZU8aWLUK9Vk1^}Jr1Vjfgs){IHQwcP0#18h!H!56=rAv?;Z3t ztn2bw{2(QICh{}$d3@0x?PXZk>tejFaE@W!ptHDq>|j_o>MY)BIM=Xd=`618dl=Si zorQx1mUXphZ-?JCh8osQruYG!sd1%Y%`qeFfZ<&G7@WIV^(}5itq)9lla0~+I}Ln? z8Gj2IBk>c$V(m2J?;}^8INw8Vmnxf{n2M_&>myaRx$vqeav$g0nS~Qc^GUv;S?FR2 ztljyRW?>d%VSSo!Y8F1?AiF2u)>p_MYFMA;+xiMyvhCh{TVEl6reS@aZ|kdhW={;u z7iRot`s**`k2I_=&G=Dd4_k#tnf=O)^I{3pyof1#R=frWF~ee)ix`kE{{@S9VMe+V zR{8-qT`ZKf!U%^%JNOJIT>|cXru8ABTyztvHbAK)#`R(`14lrXoUTj!hG@nT0`fx^ zU#N?PA$qcefcz-EzaFM~?HY8k=u&*#tgFJtHLOKIlC07tK10lB34#Cr56N{zb43jC zIcW$Kb%lKg(bs+alO+UX#Omo1gtaC?#u|U&Nma)?8;uAuPG@Vd*bt}T*dicHM(L8; zh8V~a0>d!wNm>4DkazB1Kq3>Lh-w$el~PX@nxyq9CJ1{o~`zmCfUj~EhF|9zHk!< zN|TI@Y5I*=A3XmP-{=}Z3rz7@spyZ^_@ibh`@FQ6t-YasWDb@(Khq#g{8Vbsr-=uN z|EdXKq6cmMrU96!L*S?el!+fo1%EB&y-$CRKXRCBdJJQZi5QF#A*2b4bl$I@z<=;xJa9 zR+@MzjwJ=JqTMs|v-1_6LtA7#-LwBo#`DS8 z;eQ#sp2*nN6B#Ti-gYvcmS^n1PImJg+9G2g&+dUrv0-HF_rHwioyd5$C&rWU9WwUH zGfo!BobNfb#juU=>_IUwj>gTVxY$ebEVA(KSgZ>xUZMePO6Sn#Xblt@v7P|{mujG< z5qpgNzf1##Mr=8OF&aqVOG3IbRs(S(_C0~iHBiHdy^b?qjMD&Qyv||>#(OE{m}A5a zk#s_SfX%QGyNa$))HQ4)_C6h(qydZ==FkvNOh-Sxx7mwfUNPys{;W9J!`lNYywf~; z6N7Ob8E5<(-q;)hvowJHR?dmJC&v34Pkc!eUC25$AMa7LcZ=uHI7jeq&o02FL+o+l z3pAsiWlK(Eywek{P}#G{cvqhBONQ)z&!H_cuJP=lWW0po<;6Wd9!h@)n?1SodrL^L&2vc2S^2hS*F&Y)BlPUu z{A@_zB)~|%?uo7>sAiit^CP*7{rS*yNKJy>p1qI+2Z-;<6F8WoZ;|nf6MXxQU$+ zNr$$`=qBxJQ7PKz^gdWQlWI+aQkG(@c_O2o6f4NMojy8AwWfW_9v3AY+A`el#3!Zp zTwLNNC><_7ElqUB`D!G&gB2tw8ZN#oP-As)u@@^ z)tLB8)hJ4G|0qfD8cf)pnoEQ|$>AmV!&u>Xi3gCTlH4wuCb{OfOz`KiqMnyn z3lA!iT*f;l_+wa6rP_8*@JFvA>m`=K`7TK=%aarQ>8m(P)wnvzg>_1TKYA5|6?Scs zOXKt;*M#d6{OPN>O_ki3;7?!0?OuZG$m}Ff>A4C1^i?cVHEvBzVs5#Y=mwu|Px2I9 zn&6LK#UrZ5^2EKg|EQOE4nD0+@|1fgaSv-er~3bHfG1#dcNW z!vue`HRx?@n?q?oIHAtKv6R{za10>#GERzAA!A8P)wsPLQt?{Q0UV zQP@FsVYC=-$qO>a5FB%hfV?JpT9<^eh_Hl!vxX;RY0}S0gt>Qe(*6c;?3_kmZjzsS z*iYs5nH15Qm}-L>pzNglRJ*YSGN&e;H_?g&ZIX5)REoWN3h>Gk30fq@*(8u71lPTSmOSDe5NezD4@{sh3QQ zLdHljP=;A3PoQRM5PW8ey|>g2k7%1r%tY0InPQhx>PAPLnUp6=EmPjvh_1=ReW+C1 zOwsLXQ(f2(2PDUF8hpmFML=HiU#m+nj$>FtK$a}fB?X3<%@P96o2}8C0ZBjmiTDOH z_94KrUPA%f85Ljrm7Lh)BLFxWz`Mh*v4)!m@Ku6QP$2vn5idr(#t%oC$Q1J`-+PG_ zqZx-KM$w~SFT;`aK1P#88TvB|?wuS65#W#aWT=^bbCRWhY?4VpAXJR@$PNt=}m zGiuN;Wu{ifp&<@>gN%JG?!RIq=+{Y^W7mPPiwHE*0Dcy8>qP)g)_`loex%LD8o+(} zMgmPVfQy$M1Wwfeu2rreM^g=8*B(qO%`||Xb;ot5Xs!W7wb_LHNf25?>f z4z0A(0Iut=Ws}w#z<{)8lL`$mIzCZ1BUYf}-gPXimr?8gi_BDJ9L9~&X`itdV~L7g zPR5QIwI$)Kj*TPGNdt(^5<1aY1BlKw4D=ZqKy>C4=%N8c=Y4W?)m|YwGg+gX26#C6aUssTjj0=hm%11dTLGvYIJ+~XHZVo*k1SGHqjY{p^Scu_VvV;@Z+I;YXit262z z&#Ys_Vr0BV1GSA0^lr8BrV0TfH_co0L&^_`_*^amL}q;`CXOvCl)L*ec?y zGy$g1QJPq-0ZgAW>E;>@pbbpipAj=?BF@&!@+SH*vo7P%IJcK4GWH`hag=^Mr8f_R z=6XhRg9ZX}H+eK8-Y26hTc6)eR@3ye8HcvGB5cjrKajCI8Moz^6gwyv+|3zLSQ`Yt zT#d4q^GnJoMs$0|AvJsbZpN-grP%rO;Qf4`@Q^rqW^df_=sxnYDlOj3h!G_0!hpP; zDd96R?{_xbm2p^N6w%;B{Fhs5kOuZQ++e+|SovTFx4fG*UUZi?L* zu?wxeOK4?JrsQj8hBEU_#yNzHdRj+VnjDPByf`kR4}bj&#;04t%-DU>xS8NJMg9h( zAd|QlP(g~DzP>=JlaUuaX8y`3osk!^zWgOoCX=`hO)N9TT|Aw?GRmq-Wu|<{D{`5{ zqqrEBxZK;{!6kTZ+%KMFnGl@&Uu*OVrR&6#5JMfiCr>IH34~Ltd;8 zgL^XcS?p;zwg||Qsk$V9$2Ke>AU|aBVqIK>wTC4Hoc^39-)8(AJXvjvt`@`t0ahb` znGeDBKX4SK;JSd|I_5Q=r(pr0;JSd|x&naW+5>{?b@084N5ORg!F85-6kHb&Tz?ZZ zoT(68?^+i#m4fR6g6r1@tx`5!i z0;oXD7Y>lxUK-~9~4{{5L{OP_74iK3ka?&0Q(08*98RE6@dL?BdtJi zT>;oXD7Y>lxUK-~AJYjya9sh|KPb2^Ah@mo>>m_d7Z6-m0QL_Gt_ujRD*%t#D7Y>l zxUK+fC=^^55L{OPHk4N}P6C4K3c#xQ5djFUD*zh`1=j@x*A;*bg@Wq>g6j&vhVq&p z00h?+fDL6n78(J;bp>EUIm8+eTvq_*69v}=1lJXSIf2z4g6m^3RlGB?FbW8+v&xNm8VIf{pay>L z+o2mSxi#Qoc_skCbyWl3!BKEsKyY0FxCw%r5L_=Rhi4RA7Z6-$nKz8aAh^yBa8rWd zdUI5YQgB^BaJ>^?DY%Y18VIiUCjkZ51q9bw=Jjcc3xw|Y z15-e7eE|t5xGo^LE(s{OE+Dv0YM#mvT;D+g3a$$XuFEqQkC9@_D*!-nT>>U%4du=S z1lJ`H@X2!n!uid6y5tb=o2$1lQN%FgBRsgy1?W@oycI0D|jpqs*h=x`5z1%e;~8kb&SjsYw9A z^>1+)TS;OFuCtORfZ%#TeYBBf5L}l8quQe)1lLJT0tl`*Mx_`9*98REk0*fOI$ziI zD7Y>lxGo7=F?tYOCp8HmxPBQ4mYfD0g6qc0D|kJCIJN3e;`3AN(BVhk0*fOdSL?)P;gy9 za9t8ma9u!foz$Fr5L|DHO0j8efkSY8Bw!x}*Rg9raJ?T1D7Y>lxXv=KIbDU|I;rUa z1lL#MFh;?30m1dIfH?{=3a*R28o=5^!F2(_byWjP4F%T)1lJY7Q`Qs^Tz{1|DYz~m zxXv@}V|#exhE1lJXS#fyUL0)p!jfCZX>;Cf@U z_I|8H83fl^=2386KyaPLX##@l18L$1o(B+Imjo7iLBVwa!S&-AA-H}m85?sdLvUR( z4rJ6IxK3MSgy8x*GE#6|KyY0VAW#%s7Z6-Oo)LoUl-%~N>xeQ4u1iJ=t_ujR(-s*a zxc(g(%SiyibUCvB>@H31q9bg&B2G@`q`)y<6Dseg6ksz`?&B> za9u!fT>@NqD7Y>lxGsVG!UMte2{b{$bpgS3mU&Z7M+SoHG)^BOxPCiL9O?`lg6qfo z2*LHINI=1L0l{_YBL&w51lLJT0tl{KjX*Gi6BmN(njl8ObpgS33E(Y^7zNh_1lLs! z4AnMLL2z9GphH|BxPB7oJPNK02(Gitqu{!L;5xmbO$e^@v1*Kh>jHx7l7REe;K~ib z_2U^KxPA>8DYz~mxGotfxGo^LPFrMz;QBpe97P`?xUL9-(j^G4KTiS*t_ujRO9Bp& zfZ#f*NdUq1T_jk=K0$E(cmfEn|3!l9*$oJ;O9Be63ka^0ngkGBFU3H`#&E15xGo7o zC__*nxK5#AZy~oi2(C*43a$$Xu9KPs5L`c(1Qc8s5L`c=0D|k&NI=1L0l{@iK*4nZ z!F5uT0D|j_NN_u?KyY0WlxGo7OxGo^LPHGZBaD6ukD7Y>lxPCkV z1lP^RAh?~~hTys+=*me4!F5uT0D|kaP$@QugAc*=;|U=!D+Jdm$>KEzC?L2lS+A%@27>FPA^`-~ zpCrLuG!4P^;|UlxPCk<1lNP;r*~R4${@HdSt+lxPHt81=j@x z*N>T?;JSd|dRH`rN!e`(uD?kW6kHb&T$d&&xGo^LPUAEI!F7rk#J*?-9D?h|O!VYw z2f_7YCcdu*0KxU+O+awHDO!7Dc!deUb!mcv>jHx7G|uotaJ>_t+U!bg8lznZuFu3_ zjDqU|g6qfZwqt7ut{=1OpqYT+`tf!lxV{GUJPNK02(C-JIj(gOT&FRbfZ#d>vttxo z7Z6-OW?~{{rhwr3F%u`#2?(wqZvukr4rZ*kt`W*0xGqf$;JO0AbsDD$2(F)rN-+wq z3ka@DMsDw1tONwtkC~w0x`5!i0#slixITs^ia7-#xGqgla9u!foyHkG2(Hh>VQqG$ zHjU9P1lM1}VT^+70)p$3l{-tk8UO^>kJ+W*x`5#N@m+)9`hK+bD7Y>lxGwEx7$pd< z(-=)aaJ?LJB1XY=0m1cSCMdWrAh>?a#4OG|2(BM*Vo-&BCR%&FdD1{|U79FllpwfH zswD;2V-#E$5L`cI_f4K>5L`drE(F(KqTP91 z=ODN)?Y3f2Ah=FryrYER`ad*5!F2(__3Hu4CltF0KyY0FctXLTi|HDu1+VdZyh4=Y zl=oWF9|*3qvPZ#n0l{?|XD=YQJ`|N=eHlFnt}CZ;mA0=Mz-=19&GvTIfZ)2Sfz}8N z1lMQL1O?Xx1lMIR8uC1V;5v=d1O(STtdz0mIdBkMKW1V!TS0JL0Wd+qbpgS31t64X za0nr|t^iC|3a$$Xt}6hyV-#E$%QS$CYznRm2(GIdSk!)^-w<3^fbtuH>!-mbkAmw0 zg6k~vrn4mk*V!Zb4Z-z6^qYd~0)p#`KwZN?aD6%n=CH32T$cnCTo({rCpCu;g6nlL zlhp7*aQ(#LgW&p!!w1221>lhZ1=j@x*A;*VOcY!f5L{OP9xzdGT|jVM0eHYf!F91& z19-|1B>=&7RRa&0D7Y>lxUK*^U@9X3!F2`T0nqTsrK z;JO0vfN2{62(Bvt518I10Ks(y-~kf_*98RE6@Uj!Khp{X*A;-v?}I$wAh@moJPV@W zx`5!i0{B%F2MU7g3c&QF;JSd|x&knFD7Y>lxUK-q3<|Cb2(BvtGlPQb0)p!bz}|y% z1cK{bV9TT6x`5z1%RCCM3ka@rggFr)xIU5N_zfp81lRRMi0$Dj3&C{-_~j`9!F4{~ z@nmHPuFIK0!F2(_b=o2$1lOM?BL&w51lJ`21z~VbL2&&O5>RkmKyY0WJjKpHaGlg7 z__M;sk0kN+5SJDRu4{rA1=j@x*VS61T!P?w6Tlt?*98RECF2o}3Ix|_i;NIlKa-4& zNdUoh$%q|-E$JuDJqWHpjY_eTIdBkM9|@T6V8$r8E+DwB0L;L3JdYu`t^hpIq~N-M;JO0f#BQDm z5L{OPCLH$_0l{?zV6j?6S0K2q04!D%To({rR{*9Y1=j@x*A;*%`8jJqa9siL4o@K< zxX!K28$cf+xXv<+CaQ1;O>-*fR>Q3ka_3SaGxjHx7njrQMy9L2@1<)l^KyaNGPTr@St`J<8j1*iK5L~A%GD2{D z5g94CE+Dur3HbU(2l@`db;T$oBLvqslQGLO2(C-U!@Nj<;5u!Q5rXT7a2TcFx`5!i zBEatvD7Y>lxUMEdKr&ugDdLEjcPD*>;JRd_;JSd|I&F~=g6pTDlJXIP>yq)9j}Tl} zCWK^!;QDYfHmL>)1lJ{Fif1we*J+E45M1X?lkyRQ>xw}82*LH^eT3lp(`2OJx`5!i zWbDjI3&C~T;;sR~^(B}mF$%5=2(GK;3SUc5a9u!fT>;o6wz38U*A;+Gf`aP;g6j&v zCPBe<0l{?zV3VNWx`5!i0;o6D7Y>lxUK+f5)@n)5L{OPHi-iqcnGd5 z0DA%j*98RE6@Wc~;@kp)>k7d6M!|If!F2^h5nf9`aD5B<>0QS80>O2bc`tL(gWx*D z#9%;hy)Nv>D7Y>lxUL8gj06D)t}6h+py0ZI;JO0PcM7fx2(Bvt9iia5fZ)0Uilh?| zT<-$dqu{!L;5y5^`*8svAh=HV=mZ4UCmwSGg6oO^PEa0QKyY0FwIw42*Y73cPF`3; za9uKfNzC15`f^k0&pcj!F2(_bp_!0 z4Y~%w^}o;y?+NZe5L{=ON5ORg!F6_;U4`KKQe5lCD7Y>lxULA$)$v>tAh@moTsvP) z0D|iZKv$Qs2?W;_fb)ui>msfJ%q&`JW)gtlx&mqs9E}Clq z<4D1E0l{@u1G^;!*98RE6@bl=g6jf;>k6>sI6`op`jQ?6*98RES?1N_fJ1PdBg{P< zg6s8gJr?8B3<1G)wN=9J*9kyyT>)(@rg6jf; z>ylsrPk0EflbQq&T%S?R2~Q6oxUM|FSWs|XKyY0FaGHYaVxk5xIJ@b~Bn{xog@Wti zN)6!3g@Ws1vIcPFLcw(b!F5H7j(6a!f#A9VRL3E>z8Wrh6kHb&TxXd_!F2(_b@qsU zLvXzk z0KX}?F6L+eep7H=KyY2vP<}&j{Q|h;QE**AaGhn|d`1m|>+BKzhT!@p`aPTDFkchE zZwju9yEOp6Kc(OIXaIgwa9u3W0Q{!lx`5!i_M5W?g6m(>iHWoe!FA~b1=j@x*XbUe zfZ%#_u*WF4E>>y+I1%RDU!?&!LBVwa!F6Q1Y7K?4}D?+84j0Sp)g*98RE6)9YT-w<4n;kwVG;JSd|I?KGj*+B@dvq$tBg6qps zDMrC{TzdTLHwD+lRt>=K_c`1DqXGE+1f783y0QtsDYz~mxUK;BJqbqwg6j%^-wQ|z z!F2_|?~6DhuW3N}4Z-zS=yylXeF(0zvbU6X_7GfWkLWi9*BfA&iBWJ}KyY0#BHk2S z7awW>e(z_zcW3~9Q*d4E)ByaZ;JVnQ0ly3$1lPNR-y6xeKyY0;LBVwa!F9SvCm^`K zh)(bkynx{PF()XvF22$LoS@*k*rx$FLBVwa!FAO{O*9CuZ>CKOt_ujROPllPEda9siD_<5Yfzi0phM!|LQ zs|GM&6kHd-X#fLO$(7-E4ZtN#GzhLw2B$X?VG$5qC%;F*bpgS3_K1E%aNWU0t@0a! z>&giXnDiTh>k80*LvURI+Hd^mKmpos2(BwY`whW$1!%t^xUK;0Hw4!ep!|m5dQ-UM zQE**AaGhly1=j@x*V!Zb4Z-y>^qYd~0)p#`0DiY)tRT3q0QkL!7q<{xSAbuJ27>GJ zXyPieLU5gB9tGD01lMVtCLp-JnI;x8wh&xDW?~-CFbJ+I0F@DJ2(IrVV-TQ#;JRd_ z;JSd|I&F~=g6rlPV7!`h0)p$309!K&Ah=#1WnL>z4+ySHg2P;;Ah=Fy5}^`3a*Pz8c@A};QBf`(Tkyg;JS2z zg6jf;>vWG!KydvPIzhp80l{_c1bYF&_3ub9m;?}9mjrt_Mi5*lH3=ZNp6vnx3a$$X zt}6n#R7wDX>k@z_bu3952(GIdm@hRMogo@fPD610LeTvm_TD@?s-kQA?x~VK=_DPJ z7?M7nPSOMjLU+Q{%n-sn&oYT9$RvY+D4>Xdh=7PVpg5o)h^XK^fFt5OB8q@Gp`aqS zpa`O(;(J|HXD8ua>t5geJ?s7FU5~D1==xRFu3c68)EWA8T_FmtD+sRZHYvESAh=F% z*d_$mxq(KIg6j%`>!t}a^blNMO9K>KR}fs+1}M0$Ah=G`GyuW%_i3O9U4r1caS1+B zWn4jU-2k_qObD(Yr$q{`D+sP@i-$Ol5L{voUu4{miphXC-bK{`U z8-NOe>)PV=h-U@Cb+*Mq5M1Yrtr0pJp=~w;!Sw}z=@eX75L`D_5$qHKydwjG#6^jFoNJZ^Fm!X+z?#X zuie5Y2(IV!5T78pZVZS|5L`Dve0oiQ_yoaqT|#_<;JT^d_yoaqlQup(9g6qaWvL09nuFs)?i@1o3p%1=ke>*O?ch;JSj~I!)661lK>Ifom8j5L~bB0R-1i z(*On66$IC{2NYaa5L~Be8i3&Xl%6m^!F2_}buke9jd2LUbptT0U$K)ATsHs*%R-ib z;JN{rY6`9^2(BA|afRTzg5bJIqdmkM1lMmydm#$0D+sPLFGRt01;KT?OQ#^XzKu>% za9u%g-59`JQ*d2DaNU3;Z4rX&-_Rlj*A)cUwZ%7hB8T8Q+hVg2Tt9`65%x7g+iV7c z>p8v93`Nxy1lP4y=cE9^^;XCW={yLoYpWDoR}fsMDH?#_`d}KM;JSj~x^c_QKLpq3 z&;SM36$IC{fmi7k1lMVr1|Yb;iUvmUsDa>mbpsGwe}M+xq5%l5YXe)kz~j71=ke>*R=ts3lLmCO#|b(`ay7A8=&C2g5Ww$(*Ok5L%m_3bpvn+u2=T}g6r*& z7n;jahv2$4K*4nd!F8IZ0SK-SrvVDCD+sP@1AgRT)FHS&j|M)%C69vOx;D_BV*tT* znx+8=u5YFR3a%>%t{V>!Uld$d5M0;5V=O{&{X<$D8ABcf*R@3ot}6(xvn^VL;Ce0AiYg>k5MF=D0IgC=gt4irOIxt}6(x>n85uISGR6Y@AI% zaJ?U!py0ZK;JP%yUPEx5I~9f2vNZ^*A2kjeZ%fT zaNPh*9-M&S`f@t)NjdT$xX!%LyPS0huG2j_0m1d7bmB3tM-W^$1~7Mn7=#d9Hvmq! zIJ^*CHvmpha9u%g-2ga2!F2_}bpwnO5M0mdhjuBrt{}M1ywI&22?(y!Jvsrw^-EAF zNWpal!F6K*PEc@NL2%sw1kfhdgy6aXaN=`L5d_x_fD;s4R}fq`z&HWH^;L9&g6j%` z>&y#La9u%go$k>I2(Is@6MX+leJlpx1O?X>1lNs4I6=X61;KR#lpbsduK&R%hBibV z1lM&F6kJyjTxa8K0)p$@crLh&79qH944?@Lt}6(x8-OM#xUL|$ZU9FAS;hne*9}0& zDY&j6xNZPC{vvHaaNPjYaR{#8hz3J@*(V6DGcWWihYW)2^p{>iaNRQiUQuveL2%s| zfL9b;R}fq`0A5jWT|sc&0C+{gbp^q71K=y@KHS7fZ+O4HbKF4 z1;KUZg($eLAh^!P*#rdF|6mh$vf~h3HwMteL>7eLx&df{g6j%`>jt3X6kJyjTsHt6 zr{KDR;JN|m_z~W8Kycjv({Tu{7Y>9Y6kJyjTxVWrFik;lo&M4*2(GtApPR$9=zF%j#Xs{Y3QRjiQ1cHgc>GhN9Fg6qwO%g?wVxc*rR>f5IZv6-6L zCjx@&lYr9AJ`oUH--8kvHhT=5GM%n_VOzxV{AW4Q#%}UuN@F{DwB)r*CBTm4M(n>o+$0NjVVX>03veuQzwK`37=#v-bo9*J-VX&6kRMnq4O#xK7r~>^cF# zbz16e^A+H}X4eS_uCqixn=kS9xA`XS0J8%H1lK=Iak&PXy(b{J&T{A5eAV^>oA1kx zGW$?KaGg1$%?=b0TyKC{7utLwc9PA7Z?esoNT=9*S@U9>??z6w`JUr6vr7d8*Xh-C zo3Ad;u=(=dr8Zy0yUgaRXftiTwKdD;8(6c=9u^Q>XN}9v9u^Q>e-ACrvH1ekVzX}r z1lKuA%gl}y5L{<@?4^O|y~*rY0l{^8eY4FMmTs~6`p?R&+e4TY2(GjAtv282S(SAy z;~0YLWOvzoJLGPgZ*<&a^Rk5MF+~Iqj&37g4%c9`A zg5dfJ_`1R7>kkiRQE**BaGiA@%IeG%1lKpA)+U>;Gi=MUSqp;eY<+uHL#80O{w8d^ zYV);#4{Uz7zcY)1>k5MFEcap7bfzG<{tC+NviV*8ew*K~e`WJK@vm)uk9{DEg6j%` z>pgL}9SrlE=xs)DT|sc2!}qE;%&%nM^oIE*=4!F77{r#H-Rc20Z4{BFhN3-kLAw=X=u9B*m(!u(Re>kIQ4yU!QqQ*H=l z@xgPFFU;q-$-Xcji~4vgPOiD@4_9ybp^q7 z*39#Td50bHg?Ur!2(Bv#t}`?23-h)z-xuc1VZ;~aEuJH|t{}MnW+4_TUzm42IkkY2(HttBe=4!FAGSd|_U+Zt;bA*|^mg z=7rm{zA!JHp7VuydGow4%l<5nNXgT&J~{jo`Y1;5xg# z-3YEL2(DirKur6>Jdxp6RsROH3r0=<#`S63Ug5KkK<8W_IcfMJkvRkb3a%>%uJf#g zub#sd)-Ay4oqBh`4Pu4!oo4}KP32aot;h>4=Qkmt3iF+3HZKqhD+05SLj!dytX(wF z8TIR(S-)0=`knPld2LeLssD04BAlC2H8~Z$!pXor$3UxURw7}7(S~~{%@&cfuB0$qL(5=E+ zNduixzsH&NJ5{J>S^r)fiK>fJ|1^$Z)vF>v%d9`J!upu?JD~nKXLg`(g*wIhzc)aY z{!aa?m>5zKpk>y-pu)--f%<*g<2l9XGaWd$LbXC(D7`-FoaY$u;4GuYR0L?61}0Tl z<4`E5zZITRWgxxBU_8Ne(#g4cNXJ*GWi;sHh4V#@!L_{AnpP2DQ?5+EN99yl-{P~) z$Z*-5UZ2fL@|(S{npb3p}bKuKuj$TKbW6;%H-wdnB`UBN_hS@KdCrs~r9ut%& z@mYuKBwVMH69npTOfISL(l%CmVk*!~f2&@$>p#jjHv6V}X*x z$E6XgRr>uPeyv~V*ZPHiqhIK4`6(9fa_<6GF#3h`%Ic85mlgIMqgPtL&~Nk$z0@zX zx_X~r1*2c6EA&W@jYLtcU+CBRg?_DH=-2v%{(JVZV?Td~G4XrwH_5N{3;jmF&`bS7 z>m2Vv8a4Wb)9A&}^z&)-^CL_&{SAM&S^H7cHP7Wu`Vs6rZwnMiHu{Cyj|Am z=r{U>Ug{TGW4x1)QKuw&C2M<>fi50?&W7O!&O8PL+c8i@VmS(Fg3?p4_UP+VrX5RUZ_P3twkBv zv#u7>UYx~wa24&k9VM1zF@sI7!oP}%Vz2*mQFqc#N%tyP)a54lDW1r4p+bxvl{ z+Xs-iL+51S6;Q2{Q6~o5b@>PW-44@=pQFAg{(4vKM}<4R_Yt=RDAc-!*4-H;qu|{9 zH<9~5W`BHk6;apFdN%ViBz#5GHMHKyT#1Cgh`NT>Cz-Dzky=DuL+fDX_ef+EQP_JGnyp$nK>FnKzLWLc^#u*}|TgKZs zPKqc)n9{?Zg?3y;tFK3*r_Cwz72S)2Ev1*v@fT5sFr~Lnq!v+zFr|-9WE4?`Fr}|f zWEW9}Fr}YPZ5A`j2!A=p|U;wk6m^LQ_Jc_~AfGQ#^MD&ph8W zDFgc>#c1N}04shQVx4-Mu>oe_Xl^ce{fXGEGVn`uD9W!`>vBhZ3(=w)fMkQ+um^F_ ztk^+pQy8d7$>d?Q208JhHOQ$*>AeAoQc8yfI;I4fTeg>`yQb8n6~qH)PO(bEA#6W2 zCGALM{nV5SZA|OJrlt(xnp(EvFIY}bvAI^2DO}43GE?+`xf(U1=_jqEwqudCiRPZM z^g>#uEj(-KRk>6vzCLdSxk8p{M_;rG*-&HS>AO}9c!jHTX5J+=RhS+7r0 zPcC4_|9(l;{J+#`O#8pmgY3=q zz5wU2^LUQJE{x^%zV=+&<2<7VmiyXsVT$wg9Js;Po(oi*$6jECuRRwk6Bal5bXd5W zq~qik7-mdfRcUgVuMtg}vgewzrmq+Hw3n_X+vrORQ}Ln7iY_-p&D*rfp;KP%ym9Dnuj9~MhTwKnadc(H z?cNUBp;qkYE8Y%V)Z?=lFRyw#aB(-yzh2$sJ7RJor}|D~@`g&2cY3Q0&T3Q9)ucE5 zo^Hy%Sy^_vw{4Z*GpaXonKV+u!D($O+80TOTYFn;zoEJ23bgUI)^XTsKSs5!Nf^J& ztDCG4ld1H@YfMh5H0kv=(1#~CrXd*_L%1Nk#&!!S=EuX#?!3o$Xe@Z#v{x4 zvd&X&rq_G)OgAnYzz#g)$)fGXWt8>`Z1L2j3H%q;npRC}aTTa(e7L#NhngNeb>`@< z>FK3?&k73kROwLf-(L-V0uuSLtWl{KjNp}&`2tM!5Mk-t~ffwIfriwBB1 z-1hjjl`_4&oiqtoESu4BuQB;UrOA8!-Ly#^!|VLrbjNiJuQ!RZ5gdgLe!bQi`wvvN z|CHE&k_X~6a}usSnH{Ig)2g3@FR6YKp6Q%~V|Q}ITA1_FO_dc}B$sQ)^m(a8_487T z>gT0a)z3@i&UuM9Zh`jIPf{b~B<1EPOfrl7JC%)1Qe8ISjAFVs#aZO_@XdAB_1L`} zhEArUZ;EuUQ}we$m+BSIaVj=!#i_i+pVoqv&gURq;%}=%N{{&^{sB6n$NUoicpbH| z>v(wfvh@7VuWYTC)mM*6%;a9cvSn|)jn4M5^c9VBqz$&Rv>8{d7Nb4ec>M2?c`nqz^;%{>PUiA&t-O%2= z>YJin(-&K>`;2R)6L2v3#IXf*EZI!@fJ&3e$=$R`J%P!|!>UXsCts|)6g$ZdbTwf- z9Tm+LT~EKcqKi$XGbJYb#>(sllKm<>dD1ldc4f0CliP4yO|Sh=5@SF)nS7HvP-@hZ54{TyE(u~)F{vB-&W5`|2_rZ1l z_MG!7Gq$&6MvG@3!~Mwit~A$zmkj>xLutU({0%Ht{)cm}uB`BIb5^LAe;S1z*9WYt z`3}sne|64Xm4#L}GtGTYUzX;)T$!=7ZB^~%PVM$=;^Lg2D+^uRq{^p@E2@0Dc!2R~ z1+5OrsfkB7rguY{@gmjuG|I91*duVTb52=hq0R{way2hvbBUZml^Kavx;fqLL>Jve zOaIw;bo978C-w{mIw|4~(Tnw{5`VZoaw6^ye3(`?sRTQ?Qjx-F@#n+k2+Rl6a<`{5jPhfh<#-bKU&!4Kgb{s~{Ey0ym$3wIzqInB z;-`O;e_X{9SF*$s{^6(pLjG|xi}gsKkKy=7{_!9A$1eDi`XBknf8-zkk$?P0{_+1s z`Nt=5I!j(#i1VMwKOVrD?f;_u<8qi&v}xoYH{q(GQvQ*r+%x1KHAt?Kf7I#f@{a~o z%0KEPeh4G-k2>wClz%kYmGX}!StOH!u zb2uP}s-S*-j^=V%i1Lrj)TM$c4y`W#xDO+kgG)dcU&Ydfq2d_EXCHyiq5P80fiz=+ zIRyHTZj3MSh)09)S-W|;Kqx12dva~)27ypcyb7Ov1Ulyd$$@g>?aU$2IeafkTZeMu z6U-sNTZYhup?2f{ToB6jIlht)$@Cj#XZmeN?n*Q z(eb>i@k~HDx-fa73&U~a=s*`{Z#qWjf1@tUU+8#VbzPV|(S_l-;Y3JXn3^>(I_>!V z8gyZn0P9`zL>I;Y?EE3RFa}`fk6Ijc=)xF)oj+m((1kGoJAX7IfG&&y*!iP90d!#u zz|J3{3u6Fw{^-FH(1kGoJAW+Z>H}RE1F-Xl=)xF)oj*hu#sKX6A-XUIVCN6fg)yL- zE{p-ybYTprrVC>LcF-74KcEX^0Cvz2T^Iwf^M~ld7=SG`HjG0R=)xF)Ej7})LP8hD zfNHuh22|69F#zwp^ZP&Q!We*e-bEM20KD@qx-bUdop;fNF#zwpi!O`-_{FH`!We*G zwTdo`0SE!SdSpJOE)4VXL>GpE#qfbH%;gLp(Si?t*(+GKa z)pcR=CU7F53q#ZFHFROlqXE%{(S53>3uF2iL>~*O3v)FMiY^SV0P=ogAV3#}Ij$Tw zcr*Ujr&Q5}`2e6&7v_uxzL97^REjQ)X%Ux$A)^a(61DS07bYnSiBW74x-bDG%(V!y zZW6jMET2Ok>?-K!!c5BsF3cjJj4)67E=M@;|5F!c4XXGc`GQ5c@IUIpP_D5U zk}p`B{CzV-A7N zc}j9133DHF2r4CEIB$r|pXyq_;;E;RY5BRXvuxma)G{r{1>ksGm5X>dAppy{mTCD# z0G4wt({fS(mh;W5@~Z$W=US%aHvw4AwM@(J0u$*g|mJ9({&b3TSrT~#?$rd0oEja>2rX^PZ*7r{e(c6#!tnXT;B`g5zyOwE* z2*CQTWm*aaV0~YS<6cDtV0}O01t=DP^jBVXej{kbg2SpB>?esB|#ejh^K1^+6h2BT~E+n z0ODySK?ebdr_}_V1R$R7Bj_Rk@wAzsn*hYqQv^K(Af8?z=p_L0^k5P|9|4G`#|iog zKs-H5FhBq|cq14j0P*xT!C(Q1rw<8+3P3#VBN#3K@$@yp2my$v!vrG*AfA3ExIh5n z=_3Z%XaR_)PYK2dF!5BsL`}l%)+H0f?tR2rdzaU0f?vB1h)u4Jk2M# zRRH2?3Bf7>h^HF~?ht@@x}D%I0f?uy1a}KSJUu|LMgZbz1C4+l8ZI6fn#uLG#0vJyOj|pHr5j-w{ z@kH>10LBx+lL8n|VSuLuFrEmW7QlESct!x@iC~KW#M8YzxV8#FJPpKkfqG5=;%Njf zDb#xc5KqY#zzzY3r%5caQvl*A$Pyn3Ks?Q6iH`*!p5_zm5rBBAAoxT8;%Pa-rvea9 zw-S6V0P%D;!IuIMPaooJrM?n?c-lvBK!Ay-2TD{bR-?QN7*7v5@$@$fep3=)q%oe3 zmZUW+L_BTdwEa|4Xs)XfPj3($6M%SnpWtT!h^LPUjtf9MeMWFX0OIKY!7l<3PlpLk z3P3y^BluMS;^{Yn-vl6@{wDZc0OF|*hy0WP#MAp&YSo_t5Kp@aP76RheL>)==X4J7 zw1ETa5rBAlj=(1X@$>;fk^schU$o&DfOt~8I7|_Mc>0c2QUxHMzGaDY0f?ug1Q`Ml zPbUd71t6YI6J!fOJSFk`pCbVAlunQ<0P(c(EP#*z#M8~V%vWInh^LoWA|e3s6r+to z0f?teb}lLa@f0E`7GUD(aEWy;LM3lMPjNq(Sj)SIS6+4M1sQ3))r{3kd!F&Ms0h5Y zUg0=ky{Yyx7AzBh@tcXe1l3Rg#;-2cHPu)E`mQ(RY~lbsp5}&}_3Bw)!G7M$xEE9P z>*?J)^JX(fn$`=_JznV@Dp4o#F`tp0Pj_5t+3Ijzi&}g(Zx>uPFYzU z70P9}0yopo=JmWZfSd8@v9t$KE4@Px{Mc+pte_JryFE$RWx6j;y-pgt1O!t*L%quc z;ERvGy>RB0G`{(uGUY5u{b0Mn~GV%7+>Ut>TAbl@(h z>+@To?TxV@-KUd}#L_;mbn-FBK&6w9i$!tr2?36iPfFTx@+nD+lTQl}C!Y~uoO~!| zd5SSV?lcU+X2;37oS!YRAl>Kutct0cD3s6P%%{8bd|S+F446K!Bf7W!%=vjfriLJ| zhR%D@nV(Ix`bsQ7Q#9~yEbU+T7#zr^-xs&I+c{Kt)Q*@Vt%3;~yc>h|fdG7I*tZkf z+$mKs7M%$`6o54gdrad@D*$WO#UI1QE&*7xt|RzZfa&O)F)O1sr)&Vsz3q%f<`*cq zI~HV*==bNbv>Q<SL+ZUVbe=ygVR4ygVpCy!=K0=d5FA{OnQyyj;S5d?&zo z`AN)r8V=-r!?69-@iNE*>`*L7|LNtAv9xY=WOR>-0U6!nu}F86bGv19fBE;(Jtjt>#jSdE zF(eh_!MNFBgqt(oUIUs0Q2%2OEeZ>{Eoy`QVINC%Dh6y?>D%bHjM|^Bl_JsZbeZjSjfR^>lpAVJ!j41 zxYvh)yXjy{$3R^+T^HP8Mg+VjYDYwwz*JOiI3=3E4DOG0IypH;Lx8hfI&!83j|gYgaa7)k7fb?{VSO!bWi~*I zI`56R&AhykZ1LTAkoIWcqj=iQC=~3#4H>cjibuNxbE=G& zM+7)t{v>Jf@|Xbe@@E0!<#7Sx0~eHYhf+`O-uI2q5P|Mc>& zc#X^HWovr*w`0JW{@>$i_t3y@*7?IR@Cf6?SDHoBoQwl;>uG$n*;kiMTYCCmiQ|e1 zlg^pW=WONE6kALywSK_IV0$hx!BTS?bXv4ZaUMjAIxkRaPGPsPU`Ah!C&^>m$Ua3{H6iZlV+;h|~)rY^naeSHQt(XAZI9|(&aRIn-{GBCA1>nZ}CYEUE z03Yro!;I_30@x46SyKV@(xYmZs@8CzMrU5$*Dcjr4|z6Yuz6{K{?p5LrPdgFi6ZSw z^}*y(0bDaf%1M%5ZLL+Qq5x@)&b+v3Q(AKp>gNriwH~DbwnJEEe%#pgnJnhYK)G^e$CL*hEiW-1c>vI5iptN0tWIIGY$-YFT*MKRBH|9`E!R zhc3;WTtt>B$y=t zrIwmfmQ4h61mKL>fc?Bu0K%shLvyYGc!2PkQmQ_N2YIiv3sar&Ig9RGRT^Li z=;oqQi`t9n?YSB4V#fe3XVTku$1X2R#3GLU_5)F3sg%HNRC_8&T_+_>n+r-6_YlkL z#by>dZGOrV$+FS_ysqCN`H^ zy&7R$DmvrJ;1Mx^WBV!k@~8l`*`Hl~%mE%8B$y^UJwK5)-zlYUXnJs><+}`$u`Y8_(}3)sZljsfQq>eW(}(^&i17~6QtK(Tl4Vlo{AAC+1I zQ7Gu)xO`k?AXq`LTL1>?E)LXQ0X!DnYDcM>%_jPC@!07!(V{JU+*cZ4XQtL3A z=){;fAO8?EnuktWOAlS4Zj9F9P7z&2-|V0C@E!!LI_~ z)pLyO-vk)1j+CnV=+%IM@ao4>b8q*>5Af<#X@LIHD|eZd(-dAUqgURts(ZU2$I2%F zUOmpCQ3BxAOtzUM0A9Vt63GJKmCdp83ou^&RjOK{!Ms;l_-|*dW-^gd7NEcMDznUb zpI+s&iEJ@|8C=eSX9<8;D+zK0z^i(!Qd0oDDkI1h0IyDQ@bUy;b!^5GApuw&C$sOi z0Jwz6OD|K$>Gwhw&L}fy_)}~>Toz!D=y#nmYf%Dz58(`!hynOLlAxXd_&t{3Yyt3l zGC_R-@OuV90|D^+3WAsb_`QH2E&zTnAt)7K{En8Xhu~6P1zjz6{Qi+4S5_8akLY*v zGV2Zc-2(@yYAFWH3frVi{eZk00~y>2$H3SFDA>9zK+`nPq0BnF84NtnvF+p-;N!R* zY_^M7M7K`R$F2^*kMcOS?aEXi)UGj*&tKa+O^l+C-OB=O+?CcuT@Wlmud4tEz9PWQnt-2ksO;>5VafidVZPZpYY*S?Ogb=m4BGlE_)4;FU{Ix&W${L*p3TrdJL@?P zRK&3QS^bzQFsTMv*YId9G^v=)kc($+V9+))tkmXomf4(>hFPgB-P7bW$~wer%U&kc z*cIr{rhAupIRVZNWf7n6d5pBPO<4{<@5BGjJ6#3bUCgQ%d>g26$cGr{F6qf7J7xcz zr0(f?EimGxAE7V)?fC2VZ~uU{+u|?w&-oQ+l%&z#qo|%d{N2iGzlI)QD+N|}1tn+*fCd`Zt+pW#FCP!7=cD2K!C@p+2-(AaCm z?5Er9_2?bBlHLl_H@Dm4DQ-yb->t>YxjimV@dSFZQ|fz*n{GjRS3c(h#l6Mcej;g4 zKBpDsy{5CrXh<{Gsxwk{oftuq`DmA(%7l}hUk?tz-ox|d^qWGttH_pC(?`7*nLA2;k zI+Af6a-!VKBKOf){ebMwKS=WtdVFXsgpaCx}Disg&dr|CNDROyObpjb7!8_ zhTD&Eo3f-)Ca=(S_IxbMlToSuCHylNf6&8kF_73zpC4DVgR}HUx~t36Ia6MbPl<1d zS&6*+Xs`Al-CGiq`&@Ci8#cSTy_JBdPp zV$Q^9w^u8r+Tab=VOCR<#=0}cB9)c22KnRNVfM$B#T_$}Cb+}wk}qpF=l>#im<9bX zSb~28(>Zz*-QE}yY7+h=zko$1*|!<>liQ_l0!i74_*k>Z?MgWc3-dxru9R<3tGptJ z&=`hK$sN6OSu-8;X`&*zOZpxVe{;rzKhCwq<(-I#PwwH}f(*snMdk0h|ny&-eDn=c2W+QIb45 zqjx*h8~hdOjSb^aM&fN+9~b8M_@bE{gz@1kk>QU{#uOz_2(yQ&F>ddde37n`7Ink( z^hlxo#5sZFDYm;>%BiexmrszbC=u9T2714q0=x`>c>qKsp+aV=insyO# z!e$&U(?@NgK7^BJ>qIf;c{V(Wk3_Nh`~$#|Q~X@w8;HN&)|{Bjy-SIw0u;W36I=4U z^rAwXISZ4o&iEV94BHKv^~%}({ZFFG>dYZX_@dlEFnN2tjh?%sF%4Z1hpNYmg;fs!EohCY=T;5I0 zYU=%t?Tkn8m;0M%JYRu!xFq;nMmT&f9k>2g5yq`g$F0A0L?5?$vi)szPHJ=wjkS%i zeufTWe|eBWoUMb{-(Dxq(n0L6(21Pr?X1%&$Z^k&j@p4l=OEh&M^EDD_IJ^V!st%s zbk&LCXfC_ZU3Z}*dJt=kzlToLi;iHio;q=M^cW5F(uw-fcbU^$CmQIe^!Lr0jX{q^ zS23rbPQ+u}$IjnhCrYEAazqE{L|L>H)8Zef6AhzVa3uH#=|rPwCr-&ZI?-4kZT_M9 zXloMXeq;V&Q656g^`YkvQ_R+}~xtz);FVxeXu3jHh%}Y3HIuBc2kF=s5}r__rNp6f+v$11D4Jsk8-^ zrRrgyOqOc+0S)}_OM9>~>vx~dYTO%p&!qg}(*y2mxQOMJ`O-eDEVs zFDVy$3mAuulh&Y%Q@sW3maFNlEH}uTG_JDTxz)>!aLP5ji_ZJJX$vZw@_DuMu7*=M zs@pwj&s1h@_jIDajd=VZXA+mC#)~jdDX)4WEQX=w3^#nAt#9z8?X9f3!DB|XX$h^K z=Sd3TUd2qyd7gx}st4gb&)_@^LSt@|m~y_Skjr#qZj+dDp-0D>tJyJ5S)nIWU&v@H zI2HiPxl}fKatjhgp7H@qOnefFsHdE3S))GLs8`EV&R8;|Roi1mtN9k1Jme10$-A~zJs(w{jb%(p9_J(_=A@^LagvQQJW5?Be zG0qVwYfQx^ojDln#u|4gU6CiYl(p_oTxJ{b1fO!RyAzk&MtYCUb?#1Fc8$sV#N=Z% zIoFuHw$kKWcL!~fC+L)`+#U2_@C2PQ&)tCwys@&tSV?e|NLlC(ax7fU6^^!)F~;N* zl_tkjADMB|{5Y2FY|18eksft6WgGGOJ*A5~Q8h7L-3jdr7patP?gYIY!4r5^V8w854- zu-`kMaos9u4UF&5lio_l_&y!tP5>m~%Uq0)%hj4&GFdxvdFA^$?6uMR7w>5EV=^+^ za!V#_d(N+w8QWVjqb0XwvbJ}niI$vQYx__daJA)bOV;X~jILs7bu(j$yDeEubDCCW zEN#n-R@|$}TCVT!Ty44Al67&;*vdi|H>qmw;)<%~E*@Z-<8DjVkeur(D-3DI#l%=0 zCs@eUmb)!kiJZ48GZL+IbGk=~F1m?k+#V@_?U7jJ5K1=Y_DBJ2 zkHifFTZacLbgWMz<=`n6rYcaB3b{8;JAK8udUP-UGQ+0N^Y@@`K z$-*{DI?FX`Ezat$;wJcOwoz)7XSPx5a}zInldJ&#@u>U5_{XQ7PQyQb^%(x~ZiScb zcrMQ=Rof`xkw!9Vc&A`Q+zs<4G4mY!QKRtZ-!@NL&df`gc@_Wg(|@sf(mEFFkv|7@Pr<)6)y2Dx1SY@YPb=1Ko-p7j6X=1C9Ybe6of5a&PHJn0jh+5RtXp0p6= z6m6Q#lkUYeMdjv6JmsFTd6EXzHc!&&>YFDSP`P=MPP*~tQn!IF-_`DPovzwE$zziKYn)s+UI_2t@-31izAGQ*@?9%QyvESm0=pHstdJBoF&6D0os%rBj=2dN;#JsA_lXShR&69M+s?C#h&8p3l zbk(ZOlXTsx&69N9s?C#h-Kx!#bls}WlYXSXRhuWBK(gBANxWEcVe=&ZOFK1rMTE_h z*yS7!$QM;m?`K4Fxh(V}Hcw)vE~Qc&T7C1R4={o`3sE$RTx}TNU1j34k3j#?+3h9U zi}#b5L!fi`J7ir^;RPY)5a>U7_tZwHM{3Z;oN@TGNQ$D3%UFs)8(AYc*q~_za|r%_ z{n6jWenbaa|s?2fY;v^5j-pa@BA$% zcuWA^`MZ_iNdb80?|Fh}1mMSZ&G!O4D*!*XdzB?#5P)~;-X+*30Ivy_v&t(1@OH#5 zmUvwN-WvFf;4J}oJK`Y0y8`eU!4CvG1mNw669gX$z}pewZvj3QfVU%x3HAy=s34v$ zwbcTIO6Vre$V?}mKKlWQPwfCBjq&ugZEZ&Q1xMjlT^$qyh^Gkz-w8lGO(i%i0P!@F z;D`Xk(_Dg|1R$QSAvi7o@wANKqyWUz%>=&-Ks?<+@TUO8(^`VR1t6YUdPHX|fOr~8kS+l6bOAvP0f?sw1la-*Ptyo$3P3!~CI|^YJk2M_ z7l3$LK~N|F@wAGdmH@=l8iG0k5KkKk>IpzRJxb6(0ODy2L8$=5(>8)e0uWDc5;PTn zc=~{#xd6n|UV>Hv5KsC00on>cJk=&>FTljp7qrgq%od) zgss0a5l?Hs0Phtx3!EGAbU#6F0f?u~1bqY`o}M7+D**Adm7t#h#M4Uz{RJSNULzPF z0P*w=!9W3sr=0|Y1R$RF5S$|b@$?E0oxuVSPj3?p5rBBwNib9Z;%P6zFae0CFA0VV zKs052qyWUz^IS^K7l3%G#S_m30uWDU6O0mocxp&6 zS^(myIl+Yj5Krw0#t1+>btV`q0P)m|V4MKN(?Ejp0uWEb2_^_YJY|0ZaFGDS(*%~7 zC;;&^m0*$p6Hi^jDw>6O8h;3R-NH4m0uIgEkHq9~fRV;{nh~~kXCt1nzXrcd0uu4$ zBA6)v@zj!FmH@<4KEZ4Oh^MgxmkU5VjUc!}0ODx_!5jgIryB^a6o7d8lm5*WfOtAV zFi!yDsofs{3j`pZnh`7%fOx9)Bfug7h$ow1u>i!Ai)a0%0vJ#9W0?TN)4-nrmJ2{U z4JWuk0ODyB!3qJ0rwIf%3P3zfCAdid;%O$q%>ocla|vz{fOxuwV5I=W(~QpmZWDkx z!-;2VSp9)H3oYV8F+FT9WHNZ%tqKP?<($}i!qy`>nAn*=fv*(XU}D!1yeI$@`yjzf0x+?U5o{BHi472J7hop#&am2rISVbp z7q4oyGqF!IBwh&zIOUw!x5L(hxtQ2eUTM551~9R82;LKbi5*Swz5q<@FoGQdFtN`O zd>{Z5`#8Z)0hrj22tE{miG7>kBLSG$R4z`t1Ylx)1iJ-bVmtp1uvY*kwk^Rv0hri2 zM*uz(fQgL|d?5f6JB~BGUjQa{B*E7LFtOc_0~{29iJko^z&8RgvGWMN6@ZED$12|m zz{CzAI3xfQJCfjg0hrja1cwD+VkZ;)O8_R;=Do-d4#2M)g7vxj9F-DS-`9=>wDzA=}i40+CC8uFeo_ne}t{8Lzw#edA<6V7{JuuO>kNOre5)6_qPB{ z{huu1%6G2nF!fDY!Yu$(-+;g)08>Acz$*Y#KbF8J08{@U2NaiNJhS-RnEHDOk_BMu zJ8_A!1Yqjh5CjBZ>iZoANE3jm??w<5fT=&qm92&VF4hED0xfT>?jkRt$7 zzmlM)08IT|1i1n*_3H@o1YqhPBnSz>)IUaG3&7OdzX5~=VCug=3XtyrpHDB=zlPOD z%voqRBl>q|V#jc0E65LU$~m!h@~v~jnAnzVqC_lWVjB|F6M%``LU6VKOzd2O`T{Vq zy9pWyz{I{s5EFojJwXr`fQkJVL8$;ttcU)U3BbgjVhlGDfQjACGiVb5nAm3t5&|%> zi~a;?E&vldm!PEpOl*`ZTWbNB*bqTm0hri}c#bF+fQg+(&|Uy0b{0W}08H#v1RVrm zViyr~6o84no}iNeOzbTLodsZG?{+}98z>erv8e=u1Ylx25)2lAiETwNL;xmsB*8ENnAmd&h6}*N zzD6)Y048=b!Fd8Ov2XJ_=X?Q}*o(PZjS_%~9d;VvLIGT?3C0S*#OCo_KVASPwg$mP z0x+=+xY$e*fQc<8m?8iZ`vaSuDgYCEoM4&&OzbIw=>jmZZrZp+04CN?Fhc+)Hb`)( z08DHS!DRw4vH1iu1^D#=+ACjm!xV*bzd&9eXC5c>NS>V^;0$vf=jU5L6kr}R8N*kL z0nFoHe*i2LfO%}d5{m?29%~U?D**F&DZvr}n8!&3O9fyaA0t>M0Q2}L-*h+$#X{cpm`c)hF!7>zvWePCw3L<1gk1*hBW?^?Yk$5&AI*Exai$7BG#C0p1dTa7^bJ`5kEi z^U?V;fOn+?=3_j;djjC)ZVuoFQU!Ock8si0DJ9_c(*z$1@M*VS&c`m&aQkyc)hmwM z4R~~XoF8C^==Nv%)_YMLMt|{y^MzwT;Sl(UL-(av#367oFYgWrz#;JL=Ku!<#AY4KF^9hz$g|m&e3W z2jFMK!7F*E{gYHdEWXMM;$s5v{ZXF^IQFvuJOa3dr?uk_z*k5?*Ove%qy(-AFXtTm zE&w<99q7j?se-}7ZQtH}^)m)9R798dIV0S0KN5fB2RQZ|VNb-06k~*M;9#go)uq`j z1jzyr&$km;0x(>669fccxYiM*3BYh|BnS$?aP8sz))0UN;&Xyb0T{n)c_oo001Lzy zT-(kPfPj4DFMyf?5Rk`sl;jCW#THln@eM)P0sLXu6O4t3l)wX$PZ%u)0x*7u2nq$@ z0m)h#EfQb`^mM-JfUyegXJJ>woWW1>G!TshIMf`_dJ&5|;sm$;0$yJXV8wWmpn(7! zYOfH)1YqTVlOQetEB|{0r2-K49}<)aK-drG;o49D!u|q+Mgp+%U%_ReaU{GD?)ki! zw)+`f%^cvykbl7;Z!T3ZG)w~CJV0dqeA5rRf|U@0J<06!ldAOJ)D?H<@3Bmk?#vC{y9 z1z`L(ar}llz=P3wj9{1m3`Sr4vT(ShaXOkvf6o;YSOPk6#T+Rm5TK9pI%Bkyz!Ber zCB{ezjMmdEF+obW^#R^JqCP^uLx(u$J)ObH;i+z7B%t?d!r)vIu@=`wJl@F>yi^Pz z9)JHG;4%S-$F(dmQvl-eeu7y7FgU+34rU8LJZ@%*%LO1FCvdH~!T}zH-&F*29Ki6a z&9!W4d}dU9RtsCkz5uD&@>I)9I;YLU?BfH@RijKf(vbh%B z8VNARmBR+w;gj2dj#9*!iLVf)A4BhK@?mQ3D68Zx<6vw zMFU;_0Ds_21M4E#E)@oJ-hGaNt9YnB7zxlc4LlyPKBs|E?9!8G8rU4c{+KYJ^B!>w zoZ|BER3t#tH1Ism2PhP5&ZG0iGYxEss17us^PY7Kgg8YnMFKQU18+pEku-z3Ldajf?Z!IGP;;A4aS-G*E{Z4ZF@X@Loi{Mgux;hhyMNUL5R>1ZbKb zd>*mBqJeUD;mb1(d=gPfXTyNb`_wVemd`2nM*=iW1BW736orD#t0eZtW z(+jNJ`fz$RBO=2wP>4KSN~9F1HpmO+cEGl7qrrX08P_CvjQuOLg@qgV9SaY1?F_-!My;+pizNp zPXqbCqE3?nEddde+JD0AIJ!K-&VffCdVgSMGQ)^e_@# z3Ia4u1APjtoivb4-p?@r4}za^O&K5-dBedH=ST^hhrFDRAyOh)x7ocwon)Kq_am>T z)8-_a8eR~fH*9lsfi)|JHZwRHW5gob9K-c)oCADV&6oTOU_ybpnDF7+p#`V#BB=r= ze&n^$WT}EjA=m!^Fhu~aU0bsI7mE#efT20BK&^%cp>@2zKHqWkBnNtGL4X~go3je6 zvN+tlL!WdUi(Z_ke&dPZN&&bCTEi0a1mL8zf#7NZxb8f`t}YUQE1FF#u|xpQ(Jv4z z6M$3lGX%>8m^1Jt1!@pn3T@)>Uh4S0gh$zmf&hC&zgHDl3+Q(-Pjq*P0rMbzlq6M*BVE5R2INcHI^b`_}Fs2xh-pzL;<=*f`Y zUl3s9Y~uR@Yag4Kz^4Bt7SY5sf+GTO{LCi!Q2;tVpWv7PTv06{I4%I|`Hcj>2*7$? zaTMTJ0hrR;S>ksAI4IW={2>56dw}3C0Xe#72Mg5S?AZgnviR2N*_B);U4;SmnLYCt zTDu#fXRkAAQVOe1I|n#}0RiaQES5+WfS#rEGC55EdbW)vf&$>x=d_U_0FyqQC29yj zZ2D;nv^abC_6faT_XmZ&KJ_Z=>l$Q57$$6KiWK(|82d16w9=Im9A zt4pXbz)@k}qlMP6#^`$s22QaUz^t|-s3QP<@5)Q@5&`J@**rk%2|(W)64V!fS?xp{ zF#(v>{%pO>0UiuSJ{Rvs0?_xR`vICt72G@DNYG3G*06OPzm@_pIu8)E7J$*&!y#`g z0EgAJobYl1cy_a#ph5s1SA0tw9R=X#<$4B87XcXIaxVE@1>ojoJ=eQ#4&WwJ4-#}2 z;L-6HDO6WsctaizO`$UfJ%2)?XJLS|!#NmGXl>#gocs-ZkYj+4d!k%s1`7yii+u{! zPFj4CNucq@l-XkmbD(c-8=tE?$3KD`J0LdO7?gXamx3c##xCm1gPv-&2%MFKFZ z?-NWC0IzltOc8)tP3Mv_RRE6Fvk0aOz_A)X0x&}Wj*2#%fSC@!29Lofc#54RB`~W; zc@cTJ0L(tEUL&3c##xrHy$4FspvX-vR-c)#f}D77D%j!J=HSblE}L&l z`fR@A=C}D~QmW1ONiuA{e2{JPo9bMfUs{H3e#2F0^Xrgen-9}V>?aFdt_C(AWR}@{ zF4)B8v#aJdAGox(`3#`k=FM(Ln>U7CZQkAWw0TQ*q0RfM@iuRcCfU5hnQHSkWrodr zjafEt80Of#>Yr!x(tV-L>+i)juZWk~ysTYe^V;+ln-`d?Y+fbaW%E*Rjm_(|^)|1d zHrl*E*<|x{|ESGV^piHvfLm;ylb$!*_k3ND)j7rG+Gg`4@`23-cURV5ASzs#RTuy6 zwYd=Ow|OWW%(@hPR>KRk7Gm%Y*$n0%T!DRzyyb;n4nB57f?(<|7~%i9U}~rtCQ$@a z`9^R^1XG#g%6SIXxxbI|qA;3-VCr~)|G8l5^=z`bU}{JNQ`r!=IfP*9qULBq1XD)= z>+K`QUWneGT@*F|N5t~60QCjni1-;jzu;L>Cu@+&`AJB=WaUDSpY`oiZK9P z1YmSl5_A=S(fNorx{FsBovT@*hX9Pu41%5lFgka0bb1NE=sZFjy#-)&1`+fTfYI4U z&{qIPrwu*rCxFigIR^s-n9*rlq~1cuL)s+>rs~lV!BmbLM+btb+goCEl4xLLk=`d* zk4`ed`2sjP?8pTIFgiEUiBSSDIvoi{3&7~a2*wD&=q%<$jTL~=aj}(g0x&vXvcz}+ z7@fyyV}byT&P0~DNB~A>6iZALfYIs95uPLfqjMfzpCZ7F&d?(D9XcKo!Bo_7g+wrw zn%i)}(M)c~9oMKIL>oE1ed)c~9oMKIL> zoE1ed)c~9oMKIL>oE1ed)c{-`iD0S$xK+}B7&&~AX-E))c}0OA%dv}FnqLNY8^yI zNCZ=v7ZSl#1{T8yf~glWd_*wS7{Eo92&Ni<@DagO1M+nf5KLXdCNddGYm3a)xCo}Q zah}m2nEEuE_-_SMKc&U$f~lbm9Morv0&I&b0t8ckrNy2c{nwo(#o07>TagO4g#i&v zMG;qM0uMI`rqVQf4Z+l|C{!t!s{2$;FxB)ih&~olFqIqAghVivzo!X_V5;7-CWj4P ziU0K}RRmL?Wdpa^rikOsby@IX|GV5(^`8P`hl-0HI;wVzFjVCqjyjN%Fl!PH-n zFhAlU)=fe%mF08jgKAd^9l_M$<+xPiHAR(R>QtbNe4g}O|4}fNtBuF}5KI*nWi3S& zpF5vt@xm&>R2GW5vtt+&)w(F_K3wt?yYqQ6t0tJrLXF(ntyySrQPzVf)Wn_7HNCt_ zFqMTW+}XQuNvWn6Wj%oAI=b_@w5@UHGeoNircwreqdT8bwe3F&rqbYcclMw>7<{oP zYc^Vc)t%3{aa9SXvXIA5$K$2Bqs?^k(fiE|LE-Xk`2|=TbM&oshY~k)5YGAV##=EfW-(9xX@E|bwFHQ zmkWoXr)t6mhpXtR8i2!9^i&PNYA<@K24J-pJyip++KZm50a)!tPt^dd_M)e109Jd^ zQ#Amq{abVlda4FswHG~A1F+hQo~i*@?Yl%!#Z}@|!D=shs-^^1`@t;XlM-0%PZ2;* z)s(<$zqJ4Wda4HCxDq{81F+i9V-@JB8i3Va^i&PNYJXt?N)bqNmEd5P!C)pr`tAIZ}ux=&3^Zs!C7Q7(hI|!y^KE zssNx`Pt^d#)0G6!Q#AnbBzmd_Af7}|)d0lPN>=G0RS-|B381HHN+6y@Pt^d#ljx}$ zfOvX}RiLM80OIKd0_dq4fOvW^2>^Pk1|XguCxD)+0f;BjQ#Anbw4EiOr)mJ=>1_h& zsTzQI`j7y6ssj8;^}9C3j`pZL{HU}Ksi2!=41~8ropr>j8;|WixsHbWGp6=zr1wB;*5KjZ~V2paI1~8ropr>j8;z{&W4M04Jo~i+e zC(%da4E>o}m`VEktC$_sj`24MW^<^w=a z)d2Ke^i(zQ(+RDodYDeUj9U=usWLA#n}G*CRl3I;edwwFjgJvVc7*P@jGk&qFWmU? zcEM%yBF|^@)afpP`_&GJeI`>z26aSel39QdepwA z>RJ>IHNcZ=^;uK%^sXHf2bu<&B8NxZ4^6Gd`(T9h9m~;`AMhM*xmEeaGSxfFn-d zu_OsV#OON~zW_vxzGF!dfFn-dv7`#X5vT81(gom%(|0Tx0&v9XJC;lVh&p}8k}Uv7 zoW5hp5r893-?8Khz!9hKSV97D#OXVhumBu!`i>=#mJ~G!67gSfAo!uo(^a69c%% zfbK<)gmU$Rfm*GR*UK?5w-pit5&@d#p*%ccwMC)eANT@GjYyb7neVvX+ZUlcoBH5W9Ut+=Fnzoz zq1MyD!n2V#$?@?+`Z7HcplKSIov?P&fcD@D$ACfry;O>VS2_S5(c+~Eb&?ie>x{ga zj>X~O5bC9KT;usD*#x%f<%79>>xH#i0+RG{FhM1ZDg;GTqa3k{@ju-2Yw;Le2FN&_#l(bbNDrX0O> zi2zO0z@~)tF%8_^4*cOW4Qx!PQ#8;6tGas7F_6Upc{CBAX&Ts)uyO{#KwtLr*)t71 znNY2e7wU(nZ|Z5sK$IRlp9s)24ZM=D2Gc+u&Kl~qGY!0yP;+P?z%IP(7^s6MiRz6+ zfTkIH?WHq9zA0+}bO%L`Ztki)p@I+(q z&k|LtX76)Q_6xw;)0E(A0a$7-;Q@0%01sKW+MQ4hVJ@_Th4&`(HcFujc=UXe2+$k0 zc_d+7%r=+txc<@UHGjmL%;7mE0E^c|*8Ew<1+~${_X%|ioA|i}^8V$F%ZCi2(P@TL7Kx*;wEZDT0yWWZc;1{d>4T2DNs?8rnqL0v>FO~=}ZSWAF10nmfG zDD9j~fD7tSSKXE}9##TI5KtW7y-^?GiJH~ zGdLcPNGAwQfaB7!(+O}a`+B|$5JerFa!lH}kpP#DLfsq}U@aL>N+$?SfYZ{k^#oYQ z0dRT{;FPrU0Rh&eQTJ;X;6<8qb~-_50$iAmg{K2x8MQ2T0pL|yaDLk9kGhJ%oa}z< z0?c6#uSh2dO@J%Xg%b#{j#JQ8>0WTSWxD{Y)3GB7u#C;VOoLbK!JxZ3T})^K+>|an zivatx^M4lvxGo*Lg#dph_zf<=a(2n@)5V0QnXA&yBPdqUj4DDA^{#a64HSzmv$~ev5IC?5sIj< zr3>#uvG{JzYHtKl|C)}yin@xQxVpXKqE4po-%J-1iU9AX3%?@3t?cmkg8-Y;u^#&Y z;BiLN+b%#?&LkhEiwRA${*rcvfT@aRR1u1(Thg&TKrG&kBVntSlqmQl?aU$S*e29{ z=DK@7+W1vEK_~)jOUG^_z#VEP_W_Dy3>UoEq~glP>TwH)fSqywnxwYr+qCl{RW!1* zzIRm|#z+li5>!qViA-V1{!p`kR?W`O#7088 zVjxjt+MbHlxGU(Q^niEK(8=VG;`SXG*o=n1VUv{MOh}cnktUXpst&% z;ueNaRi>EA>3%2U+=gNmn^Hw()Y~r;`xwRIuh>`pU1xD_97E}WhW8STxE+Ju>z#2* z4uIZk84|S_y{=_B*A2=fsEjH`W(xNPQ}MC&pr?(d9nZM0H=4F1jc5oqZCEBYpDKRO z4jSP$ZF&P98Z*UIP8H)ag?CWJ@R6WTa1pt@k0IhjL&d>_*;NSIF=H~Zm#Kn({lRH+ zRcz(MZkb{#r}uWsI3J@}#imqI8TGbi3I`kry^V~lHW!uND{TT{s;EI={K(Fq7Hrzy znb_Wtt|;Xq+wAJCp_is-im8k$4$c%VrHVH=7yrsoaZ472Lktz?G=gwwP{sb4*d0{S z%0Y9WtD=lvIxJI6l`h~aar8LUD|OjfieFq z$JxAKU>uoo20*%E1?Rb=+`t$~r_9eJsEjAdQ!}wyRPiE1ZBfR*q1Z&iX+q!~GYN}@ zPzkH?{!PYNN)>gqXJJO42KOCDrYOs&%~aliZ*)hw_-GQY46dN3x$Bg_LJmT zE(A!!G3R8Q&#B@lhWEK{EBbRBT$D*rIaOSiiJfsUR6NLzyFvh(Xf3*;B9Q%ON#5F>|CVL<~ajg*G{V!?vbwbc~ugW+#!K8}gsBpDw z_hL%kkV&vbwENaf>~Y$iX7sHQ0KJE~Ipcgtfb-baTU>yP32=KRL1=d0eVN$#zmo1- zC!K=}Ce?ip2tm5e}PD{A?Z5OD7Qh~w>9A>c0PpCtTQ2)GNf*ikPC0kM-H;YA@JcDj-9 zk`NFXH6*+&1VqLm90#uo!B%5rZN|ABT~slN!|)z=j1-T>!yB0ddzgXnPA2vy`;mX~ z(0R`fgyOe2%YGn)uo@D7%Q&H#Kvc|scOzp9C-Q$}64XV+Etyyqn2N{H6I)#X{0=$C z)F&BdJOQrYy7rk1a5o$CRVG1b0{klzn@fNXIko)Y0~9YL<4+m)SgK9>CgWU8#NV=! z-?@liuvhH*1a%QHRv){Ah=T}_sMnhUtPnKGsdxA$YsE2Kxbo}uD%Oh&MPYq{&;;mO zAL9$L#V>FV(A@=acdK3Mo$iMKAi?D~=>mLAb1Lc+geE}m`q%_86@S1s)w%#YFrG}4 z`qc;8R8{XBNyMcDsdf>!uuc8z6V%1?-mv;u)uBM#ksUXp-n}!%jpiT{MhO8C_99*=wQ@5R!jlyzC|fgyi4J zv4;>~G;SdV*E{23bj5VqxKq78W`4+#x@UcYZKki<>SKI!xVR^MHP!bOd#kzLIgIxG%aJH3aw-x|;wC2yloGQ2Y~{b(j!nlI(6i^tRUd4lLD#G~q+{$Q?XWZf~+ecU80KtQ;Nr_{&z#$M3` z{+ab(3jn_Se6M}>#*s_{B2OWnSnn((;zhLaWEXK2Tm75*1a;BI^Xg+ap{Q+Knrq{4 zMTMgf&#rf#A>!aBfGlwl`AWWXVSR$Sh`6dg_8p4a#?=BKHeM05@uGUC>Tn>Q#YkD{ zB2Hw`UR9r2|Qok1h7KshyxK#*PB-EduyiEvLBo5#8-)O8q)2#D2x$Au9BfYu0S)2bX?6Z2gl@`+hwGi&X~Y*~e$+Lhod>07>k~AO zM!Z~K_@-yXtM&dzvkB^aO$b#A@x}UB=m;Rb!j1JyT3f|bM$H@b#neT_x9ba=z@(e? zt^lA}3h_N5U}vD(`MwbJ#_p~9*kM%h-VQ+B?5b$y{PbacF_qK3&tp8GSVhaLsEm5I z)W@2R6un!;6{7b`A&B0ugaH4lKK)t<(x=}D0dr`Qo&2p3Fo*Ue;X5JVQ=ywk_+ALO zX1kq)e+dDf3f)h_HX&dqu%3h;gb-Ct`=s7E46UfRi!0D)Zl?|BVf-fyOt-1ghFJ6{ zG<6AGA8+u7(R|Jc1wuem7m`pU1T^&;ij)We(~xVFuk0K$PTfoHwvICmT*1gfx|DGg57qoHCTceT?R z^!8~q9}aFvP&ri`-VhrGrs7fkK|jI;P&d!EGqb^&N`PJH#6w+x)g17%8xn*jz;O++ ze-K~^EtoGBpf6tG$XFl*7<~&@oa2Rn&e=p;P7nfiE?e2-Ckg>Omme6cCkX*Nm-o1` zoGb)1d_1FOp%8S#k7;m|RFD^MnAq&tbfsF9dD(q6TLp z?QWypi(R`frq`A>B-kR_y`mx3?^ybq{cy1W!0t*~wMq!E`%T(?i4b7-4czst76R;k ziG6md5W*^IE^Ki21b)Tw)Vtg@VmaG$c|(Hc(THmsVwcf~3kQLIy#T<7_+Suj5CV+& zjt#$22rz=bnCRRj1dd4CxvIf=ggSpsomaa$pQjgo*N~t!)OmYDtaT1`(&#${06O1d zpxq?|=)9N>Un>OYe20N{w-C_q?-*$J2mu`yq4Vw)0y^vy67CZMI&2U2@%=)8NwE9Y z2IoYWRMAHFta0uBkqunekYI~w_hSvQ_*~e1BAFf+0NA~ruGt_2*!>qq`yYh>yYHeA z8-)P7t7*g&LV(>T>;l4*LV(??3Hp=}VE5tdk*9^A?S81i*$F09Oc;W?M_jwF=E?p~ z4GFf0cE8vVyO4G-W1zhx0I>TfuK#}(0_=XD{(e~qu=_R!+ABhU-LJFHUKN54wC5U} zwKQTD{qnqP#IM*fuQw!U9*y{WLo9q8j9AS;dq)6ZM3T*VR|qho3(b5_2ryz6`{8{d z=sd$=+{C(ho#vE-v|L6R?nH?TOsHU`?$f`OuJ|Cl<}!+_XE5y z_^u(r7SV32F*bjm*d1!rs|63T%I>fb#O{a?#BN6jVt1Yp#O{0{h}}^kh}|(EXuG#H zIICe&#a!C`qigqre26zD*dp59r7`w0?M{sWJt+XNdklS5CIs01){Y=_6M_z-!bay` zRBdAr%hA**1ho3sB#aRPdTTAm_|8H=Z;fZ$cM*ba#fU~Hxd2AA&=n(HBZdse!>)}9 znnxq{Zj9{&rsByQP0a$3uO_!W8l5%*987>o;#l@kYh!}Y1lYeZb{zq#hk<^O0KlXk zBpmD#LWq|XVP*&i;-zaH2)`17HhOBK^CWf7;*gx~>O7Dm7ZFbtg00-J zpfR>T5nG6Og4R~?A^o_hv6#AucvfTK5+Z)l5A<_f0KT@PRGcS>x{;?h#%?3xK!*2k zT*MKCKfkeT>q2`a2zSJdPTo7S-W3221s5zXi zT;ZyjS%-(q8;gle#A_Q1cLr0j0=QlP5M#;}Hw6v9sxfvr5uf0|xY|YhEzi+6Hx^SD z)n3@>oPuH%4Xq+J)!fk-`v}FN*4^M&~-()VB#{JmT84nVx*QF+po-(_b26kDyq* zCzrdw3Vm&dqI4x~%^j;HU&%EB~^hI68 ze9kAE8udFrg9z|;V}j5G_(x-GX9AqXK>0Xm!F!F);RKk@+2RA&f(RKuZA=iF0N*qg zzD$6rq<<#?1h;<6IQ(7+aO>aM$ZbNvU^$Zd--=E|e`p~K` z8)N^XQD1Yp|ED&%qBkwHvc)u)M&)M<`=1P>USVrvS$D+4sCOt87ebyw3}<6|fw|&3 zPP0x{t)mrBa3L?q7E>41e$nX61XC5;T19NCDa*zdQO$w$a5pV!yNg0e*13+Ts;)Gv z*Qp9F;pN!`p$Jf&jXgqu?ws;^y8sv`)YvoYyi0(qX;zgBuz_aPW)p-az>sXrS_pud z95q9O00Xm5U({7RMSwvr!2O)^hG!FmCO~~Qwle{4;5cjyHeqDeIh+7TaP~{P0Ka2f zM`sg+CcwmO>aud0<>mhj}ze14CrkxfI2l} zy~;Wt65ua9|2De-JJSdIW)p-az|3r{>nQ;Et{>=!i3NzSQPea`+5~2J^`NZN0OpE= z88I_lME)kOb3`^lT|}Idjh#fqd^Y?zK}7g`PpNrAKupgd$AWC&GlQeD&XrWLmUbTF zs%Yn$bV4>kp{O!0N|y;^u$d<@414|7Y=Y*|h`X|}slSF1cW^$sTL92^Qy7Hz z3IRq~bnksafDvzu0^xokz=-FwAgmLDHsTLi=M>;qOkv#}t`V!~i3hU@nnxoZ&&J-M z5!W*U|0n=3VkX02qY&VlTPgXZ5Macc?4qZH03(J_1}LhSgLg#aU#()+In!BNisbJjV8D)wbGyx^)xu|2Qh z_t;TG6`QlMm#E@VBEBsEP!S{JJ3@epA#CTnLV)+zF(%#<0vi4aG2Ryf8vZabJ`jR# z_@=D$9j$tmZFK2?191 zp%MQS0<5}y3n5$cQxL3hWtth1FWHdFdXSH-<-Pu}PRl~YCG=-45Pq2h8jyjTFx z@T16BA_S;dKufy_0S$kI)|LtZ4ZoL0B!z&6f67BgnGkftW22oVP*|}K2U}vaUgV|` zs@v!U?WI+fqhr_8sxcEmuNHuain1P~ou>$JF#9v*0u1EP>ODF^XaWox9ea-e_`YkL zyUvrsr~hataXJuG<-pP1d-8!_5#bCUov6Ws{>!i=mtTjcpYX?WDbS62ha1#V zE8lr}WUT!h`I?AVMDgF+?j!E?;5{pNv zZ^s&x;#>SfQ+ySFSc>n{4^Q4-1o<0AC5bsAslH9(#!k{=@j3A z&!qSwdwq&;qc^1ZN_jS^zGC77%{4m3SH8!j_*VAV6yKz7O7ZRIos%Pb0INK$@W&;G z#PHN3t!$f+;_J=3rT7N&9?3&Fm)E6LOZQCirQ%7+DU{tMtt{OuIfG9VHPYTGz5?8w zR9`qTSxdE~_!4hxif`ghPM$#S+3Dny@N8T1bUq!Wk!Ga$s_m~*d|!5E@-kYqMAsaW zyo7w`rjvspb!dt%gEi>Jq=_!8-{sWbMqtT`#Z8#y<{_Z*K)&a8mM*V?LiDZaY6 zAjOyWj!*GLyc1G<745_n-`YAU#W%1{P98&v<1@-53zH}D>4Z%3acDd>#TTfSB!5HN znHlA!rO6BUbe85{mg4(Q7bQ<+WUkC8Z>>o2g{74#zW#G@@=|i&skv9B_(sp_Pi zQ`4?U@$HbSQhcMMJ;m2Du1;RW`f$BMyC%gKE3QpmNm_Az=_j!3x)k4)xFK1>wXbJ= z@_f*4O!4)HTat}qK^s`F`snw`iG13zKDinZbZd&QGd!A1QEIPx)!y~VVSL)VKKU>( zHl+Ak!1F17w*NwM7G;mnd@m;F@#)C=ddd`rlLhO#JN>KgWJ2`D=1r zU7uWw;r4DNKZ$-cT(*S72kVvlHiRqrk?fP~Tqlh2_ScZ0TtmbDn#kewbWJ8dv3$7GU1G?zUNF@&q%OYh( z<3OF1RgPO8spLuEqDWZ}Quo(dS47Hc`FKD!c_EBh8L8xM|Mo~Fx9E37D!GlmGg7t_ zd48jT?ut}$Z@e~A)pbEgwb`4LV@RTi{@E%2XQ26CHDfashAZCTX{~oM+ zhc7}!^`akOXso4VD;{cIx)c>{NtUgeRTZ`so06pNNKKR?(~B^?tf5;|#SSSNb}nRW)L7AmUN-d~Sq8RQ;ZjuOpZB_F>g=M0 zWPN%Ym8|=YE&TEews5z%(8B2W*XZ8oKzE{5@Isyy-uNwapBx@dpj`p#>O8gR1_I40 zr_S57&hsmwb8+}=vhDy+x~#t`$~zBC&u^v9ckt7WevO}@XpCNs_W37uo`IiE^cL!j z*1iMT=q{gwJ-Q0+j73lX3bT|IehZ}7vhW>HP+ic~hErFR>j;#V&W98h#4q#;ypLLZ*6OG$tBrFFAz(kIe$xHA%`?HRs=hhij8`YQzd3 zk%G*1;mMSF5dlygyRoGE`CuClm&I-_r9&;P=eBaKbSE@Ewx(P)yXJiaO6(7+rl4jT z8W_8?xE>-UHKWk}*j?(OOU>(iSX=yBzGaox)L|ux-CH;qYRYuPtSevw=)8S>P6_Dp|M9wzQRMz=})5esnV*Y zG`=E&hZjpn;2~0Tavbe_Lp?-mo_`oM@2ZD_nz4`I;ZyZcQuF6m@$j{JC`;z`fK1pf z-3tii$*%NRiCua$o_Z!jFN3kdE?thN>g3mSK&@SR51wk1!#={(FuU}1JoQhOZ@^Qd ztuO~!JDdntL{ZVNh(CJZ2bva#w;fV@N5-NZPEr-wB*o7rD1Ow}qO6FtN`tVgP*X28 zw9v2V=T=Xa>a)G-r6@s=!RCnK`+bYP>enA7 z@H~jB#GLMMS=J6uV4F6BlHVWWP7k2?PDMNY7Ot3&c(bBs;inz_90NEM-Te&?ofrmF zH2OC+jOsDeqgMDv#Cbdu-b$cjt7Oo|8;jZqv=0KI$;z+8eB)}^xoAEsW&zKNuKq^N zV4waAV{Vr)B^=h~S3`4tHDb;;>yPt6ckT-KFktL6>N+VRV~vgtOy1R~U}0HTvNgLp-FUvTt~ z#IKJny3n!)-1|O=H+55EA76<*;IGgW|DAredsqX8W7>+};y#yK1LyqeFf0Ch_qn?@ zU^Tireye`QA3GZ`7>6Z-CPpYyE&bI?`sd-XGZCvw1V;O6-KZhgoaFpK)ux%F_xj*<8^&edq? zpf8ee|8=Eo>7b27c_6Wp&Z_<%aTkfVm#hU>icW#Aj(r6T4}~e1zv)LW);1J<0ZQ}* zNLbOm)e`jUcflU*0zfA^602yw6`sf$|4-pZDV#ui+(3PH(J9MUN2h+0O`Av4wym z@G}yv{Td)v;!^O&tL*R!3OZqa5{mv4b5uCG2@Q`# z-@sPKiGGfGEH8R-HwZ`ja_x=|s>Y-leTQ>h^hNL|qW6QpAbJJ(3!~3~zbHBt{Ke5- zup*U2w_uynC3+Rqmqw>RV=~$s^s?xqpm&W<0=-+b8uaebRlq5aP5^R`=pZ0hL{C9& zD*6U&>lxh>$d%E*gR?3+5}duF@1eFD`jN#a*x_f`%tyQpT6|Z#=r3&Mc#y26U2^aW9H6*3$D8dQ^Wjb_c_n6`c#GYGOI;*+^$U1vwR?~; znp}YBici*@1<3>9^LU%xgWJ)PBsUT9skYulB#(F=Pt)v5?hwk8+=a%c+m+l@^u!{> zZ-Gw~p!?$c+TqQ#Xiv=8)$s%Dl3iB92J0JC9c0(kD~pEn>0rBtn-x2GB!}t@yM}`+ zlx)PniT}#3;g|_0yO49HUBgiuNiO+2o({2V*sf@D3PyVTQ2kVpoc$V}4%1I1$;pVD z_~H7gEO|R(K0eE?VYrtkzeFU*kFaYP!#$E`GqjGhYZ!nP$tOO?(`>tjLob!Q6YEX< zDE-vaN*vAceY72(2iG}l){u{3!qE5}yQJ-6H1b+>Li{+p+Y(M`$$>Ozo_-1?-^Dr+ zpKo{Lx)(`4!Wn*neu^dwS$DjCDoCD6loRw*NpdFV@)Pw_S#k)5XZ#fGlYmm5jA7u$ zPt#95lPf59hF!tgu{xQe_OtX;P4Z%ns?N8*y?u$M7r665mohRuU) zB9ostdjmHBxMt8jgII5>~!i<#-KQ4XG#c3Lk=0ng=#KjHT6D>oX?AiyESi$BD#W^Ry>M zok+dQ@(K$s0Ycu@s9Khnp+y>QS>E0}0H%5VL(M@P9d*ml*5E~ceL+9=%qvp+ zvypYTGNkHs9XpyKII0UFK5_~VqFNOeA2~a{hj}W!?haV@ku#b$q&ffLVQ*d!po?ki zYfjtu<;G+p!^1cp9*D)rQD8{PL_ zbsXM_nT{IX4Wo!(hHy!|fIlq>1FeSLNqUJfQ0M4yZa9FXk4W0nQ9C@VVGc>p(U~nS zX=L4a4&I|&A^3Jb`u0j%bwi|Z9RzfPZ-_Mb4Zb0Am}>A7M88`%%gUTgFD;L#^Y3e( z;POZd1+7tkV>PbV?8^l6^vEQIxs0wlBQi-frExHQ)jN{lp)k9QPWU3M9*&`)8dP6| z2lJ$;$N!gMHJC>nHgBGl_$r*DobHNkVciwVd3HoOPYwBmYjXBM`rXbb)sV8Xr?TCp8s#t#r8JyTC}}z@8P0J3m@a2um4!2E z#Hpd(&GiUpx1M1gXHSun zYeK`7Bh>7>CZuN@)%M#B#Crv#JH5VKgZ$P5SsoguK>qPKI&*obnTLAa&=nfQ%3jFM zoUH{ndxEn=J1N0)87#9ylXzvI1&`K(b!vz&a2v#nsl@SO%ROw+x3+Tn@mGqAzO|K$ z^u+qDy(cGD-2>m+$MB)<1j_x(PWj!u%~st}H;CPcqpg}))vVDaq-G5j>s?(d)I`%m zKa8yF%28hxa#z0W`J9q&(?-4Q8Fibj9i$p?o4uQ|LwWfRTD4Mex2+@LLt;FjA4clA z=viA7e9ypGsudJnC9Pg+D@SVIU0`6Y)G$`|9k%TtEw|8@dvoR;t9s!{ z)&FBv!~db$JyuP1U#pqUYC1I!JGMWUbLBe%U^{b>jQ)8v*GOyJ>$v=juJ3lKSFyf< z6=S$~M%V8~$Bp6I8C}1xS~|x)5re>*ZV!6`YcdoVTlpiH?o=^gjr(&1OjmY$#bdfM zt<}9rTh8mY&8s+Xj4yqGE4?#S%;`4xYB6?Boo~~ealTD+CTp9P5p{aER!?Ahnv1!% zX{L*M#~)ze#BN7YIOwXN>)C{wv>RKQvfJ_0#ZFQ2KY>!WXblKSyZG^_ zWm)5Ygpz^>!m05S3h@EL?I=v{hQbZu)TsT=LE&$9YR7A!`w0CooEof5A6QWEnB9v{ zd!V|m_Dc{Rw+mGDgvZg71%q_8t{UQ2S#}q@Z&5N4E=mE6XI>5lVUt(8cO0SSk> zA@;D6E_P{NQ~4$1de}*vgB)vENvQk15YS1Wr2I`e*K(Acyz}+}Pve~@TbQLv~uhPBN zn}|KZ(Z{paS68bW$hP*SJ>=_0*A7c6*X}?#*7owaENXUPM?N=3p!NUis&Dv3VArhkx7MubQ%s~K|zGPhNP~MC?XbCFfK-Uj`ACf zuiio{p&`RcpI&dcm^clrHe1seR|IUBj2h+n(W4NEm?wu=V|!$K99tAFYDhFD>fuRq zgqfoYqdn{ov`9BgM0ST}XQag}ub;~Di!mTEdLs6iL?W?!QbW_iSbvDIzv4+dkpSJP zS23F?)Npv*J()-pCJGW6a21$j5(-_liVwr4djO@_WXISkgf*1vLVIXmX;*s(H7g_? zWoVge1sYE4y1MdsG_B}nl8M(Hgs5(mR#5KR;o|f#1#shIvh&IZMlZ41dY8Ya=}gpM zAklP;Ayd+KOD~t4MVra4lWGX>8AdsdP)ya`cN3CBrpPYR0U85)gYqqOI&`iFy3&hWs)$ghS+0!C?4q0 zT{P4&LP8BLsi$X#L!MorT7c1&uxVLc!p3L{VriG)+iOk!^boXHi)(Eelb}WFY2xn5 zI#}B<60K--Sqs-B|E#1$^+Qu^n=dv zL9_nb(HRW$Jh%6iWsK*137jZ)g8|4g#ypj$|)G1L6>ZAF5yaT z#ypm3cWS{buS+2`Fc``ijgsiwzz4i8a4^Bv%stx3y?xibkbWy-JWSV)102k zI+zqRKB{NGm^PGC8wZ^`S^`rWz0FC@3tbWlb4O#5G__dTQxcr_x&)iY0afbuv8y#{ zV)`>jS#ZLX3C|rxnCSF;*1faopj_te9)1vDa%0G(yf{$7%c0oQjRY6E(&JE(LXIl8 z5iUnBJ%p=4^}K_v0Y`Lia};d9>pF=l-7${tm^?qm%!t=hWoJy)g;%I41jeL81tHmaGj1 zQr{pC_4Jbo0~^2Ktlr-wXt)8vS$2EVKqs-JgUIoN2#26xgY$D6jL+JF95IsvyP(dz zo)E7Wh-VAM*G0i;pjgjNCDQ)Dw16o=rjevfBW0fR)F?d1R-2)&!AZMYkcl4d9wcc` z{sPzeKEn}AX5rnFdU46?7+m?%;HbF3-#7+Mp>>I%{T&x2Q|JF?`sl3Rw5=Fp+E$D{ z{QYR`cCj5w1pBQ(I;K!MrYJbo1SSiA7AOf$HC^0bQiB`ajYn^e@P(4W5#Q<50i%Oc z2MCxt^rTX5s^O&4L*flDvFV*qN^hre4m3L#+t`ksC9}So6mTx&{4R68OT%%{T&s1o z^+qSNbuLezV4v5z16_snf78W&gyxx(l#bARbHV!sVZYtg=VyjbFlrLPNx$RSD7T-m z_V@w8jw_b9E0MVCBJ=JZFaQxwdXs@uk`Ay6J&mP;(Zfv*0!p@<2&P~? zHW0x$;Z)GeO_=vCdL z=;JQIDB+~w9(1(Vv6Ik+GI4)k6R36(!MOX6o5A3iuLyR5zco~2lbs}6Lw6`+k`NR1 zY*OWpZFgSlW!Cf5!Rf+l(=QtA9hdN+vHy!$_?ct-f4wwx9${UAD@Gt1a8sBY96Ba2 z`KukJUKG3~g`3vy!RXRsnM;DqBXZZ__FXC%rMScLdyb(dV_LE6$+jwYSH;^7_jXE0 zF87t*aHdr?GM0P0k&DQ}26#4%8rp~gss?&>;9IiWy zTD_0K{ZA*CbzW5Xvsqw4^2vq45DY9zn8t#0O-V4m0y`Y`bRd8kK!Jl131u=Dca^!g zo5W_v!;sngI{M`5&h5>LVEm?J@-l5D5Rb1Z%Nw~ZVqWIx#;K=nI zP&o7?oISNU!OZv`5gc80X1KF{WbnT17fjYU(NBZ&I%@+qdZsU;!4Vn@j?g&!XnRKF zTqF7O5_SJiZ_7C>3WB33a0lU!L^))j59m%gWT+k@ihqtY1J#$u;B)s7?vQqYuxj{$ zsc+G}Kp?Jvpfsk$?!h=McU|p{J6tjO3k5EjIMH%{=uJD=MbQ0$y@QU!oL!+N_6l}g zwX01v9qWgy&3(j&Pi7SOw-Tt=JCs_PWctb^(@*a-}1?DNXN_KiBBY{w1->cbpk$%G`k6BP`{b#=wLo_qu~W* zhogfVB&KevtTt8tyRQ2$M!UE^rZ2g16O{Y$i+>Mf)WK=AtkCUw_mPXLwN<0f8EqQgUueO@@K;N%^sJtG@JX38Lk39hQp>?4%d0n9 zMg-Mue;WGtvFzTYyPHRM8ZzQjrXra=%(!-gmG>A%jQ#v=qZi?7?b1^iKI0YtXhN6Z zQdlbEEa^u=nGV{n!Jw53Fcq{6M!XOqo>nm~gGHZpzz{g;s&LCW?CM_4J?`o#sbZAi zXlvedsW~S&tJUQ0z2vhH)v;PZA9lFhfO(OFS0jAS{BOFuV?X{U79dcE4o`Jlr*A_oOeNUlH?0X(^BpgxuWCj*~v=hS?jN4ybUwv6wV4B7w*K&Nx~QM_p>sz%VZr4+=+E| z4`L!R8p`!lXk3k}&#qI(us~1I{T(mK{XjwtO@7d&z>;bNOl^9!(cR%&&#KWYq$YPDljlRLbxEve!zJPSGp=L( zNTn+STP|K`bd})L_ZVQ|C7coLoSeL1_q$p)VQQ}N$-L1pgt-OtW@QAY91Y|JBybxa z7x$8@6kNe!xrKE#UTnCIW8irazy_&nI0imG$mNvXHyFSDOn%?Y9o$B#xbVsSgYnBi z^pqhC1GiXiuE{(OSkcDVr$WqL@A za06cT171;b1>DEL%S!apDAaqsiT7rMvol^(GV%3NfO!S4D0w5tMQ$_+{B%9*$-=4H zHomfC_)onJC_+A^6Vp+SGyHPfK zqDjztb`7pmzhF)3c+D?!Kz_&h*x$kghm{=B{m`BWy+P7+spiT zQx3#R92-Un2>*6DIQ`-P%+Bbg_ZmOrep$l4k2&S(yXD+@ub(X8vgrHs;DBH_%7-9s zL-4YvS;(F-!iy0vn1j7L3b;b?2lft)??`X^@A zAYBiWk$OTJWo{&Njm)g>V38L<)fgaVeQ<8X{3;(&l+^mV>3VNGCH!dK}rUi_CNI*yj$Sj+v4g##zB2hn3JcNfxe z40pa0@rIxpM!Ja&!GY9h&K7D{B94+%a_)=N=GdhN#s-ICQ_#5ozgYb*hN9U?dN6Hw zu?h}Tb#UOx;J;t2I7DjA6|1kTO}MMzXxYJEn{YN&#~H*MLnCk?@CWC>&d2PI!7)21 zIA#ZTcA6NHJ5Xgfs@2LnB$xwIUOZPzMdwF^-~yO?MBo^e1x$gkrCh#@HB^=_Rj@_8v@4!o)H2& z1w?`R7s786A=y?lvpS@R^`+g6U&l25fm))NT9^q_OOQ$7)GD^-e#rXkA~P*9_v+I; ziLgSa$^xW33%`JRT17j{J&|l{GBb+h!i8(gDok(nM6(Zq^KrUsKHP1@-js8^8 z&L>(DBZel40CTFSMuIkG!W8TnGVP|ATA2w`t7n5&rg0{V4Q!{jpjFEk5Ta-BzR7SYWLS#<9c}Vahv(-pJhp{e)X=w*0YB&MZCFHgyGb2;Tnj0~d5&bH~ z(#-4`qz=lI2?o>p4opP67SubDpo|%ra+MMNFN&p^+4o36WyJBBT1=*3DBv50A^f_= zV)m6Pwtb6?uz?ud48r?JF>Agxq9Xni1{4+Pe?u_hnvrbF>ls!Y0MbE<+{|nVQb$wC zG*dCPFcT)ah4{$aT4o4y6s)0Z`V z(^tvoebYDfjir9H(=sZq?Ax0TF$9STHwH!!~3?g6(=cxW*@*C%s7wY zA1$C)^R)YwhmX)Q%-F+GX_Xg5@qlQF7X7C0H-pf7-wdkqx~YrXO-7Z3O{stybqZDe zSO&FMC@Z{}A)TZb6}g$&S4hDa4PkO3)3r!+2y=27ezR;6nG9lB5pD)CWDWD0Y2)j> z`5oQ?R;nQ6_lkLFJM&SPVQj0-v)?9>$smRm0ruvo7z#>Vjy!-SfYhqU&CHHQcN<_} z2!*Ugs92+U@By0Drg)l}O+^Y@b8W9F;IgKB>}_Q42nn7&z+?%Y0OC;js#d{6OoEA8ad;SsD+n$ z_W_Xm&z_4~CZn0GItipxHJRB;q~M@}IiTI4Sp<#wJs>@*$;_TZ%9Yei_bH}UX2N9d zVelpAsCiN|J?%0D_99vTIGvXdHD?H%aC%~C{`1pOjWlq>!ym+ zm<`obX2h_qY0Q>rDl?60#4|B{i&|-sYsI0y72f94Z$X2?oXm`T^w{KfUm`H!akJ(B zqj40=w^l@2Rzy}r_%H@3ZcSbhS`kt-J~JgqYcq&VAQt$<=_?|nOjOh*J@^i*S4k{?TVpja!d!Ah}b4DBbPDVU@le8 zZUQ;a+B%WT=VFxEEAlL8l|>{$_foog-kct!&2^1M79GqvXy7*;@Qab`0@Zl7Q2E0 zXn4USdXt}R?FX(IiqjJ}iQX`>RVXbCVw%L9A+3GGxVlQoG&8$Z6{j(KK~tH1q^Zn4 z*HmWPG*x_z8PFqo3m^WFgGcn*gblkQ6B>JG%$C&x?LG>otqdZrG0%mRBI07n6HYUy zVMFm{MUY`ONfq0eU8bqb)@v%W4VudARZTU~f@Na&R7@?*`l;d+W_6m%EUT%^sFgEc zOFK(TRYeQ4b*eap8Ew!!ENK(GDTB@m{u2`tI7Vcvl>2(Oi!ll7c%LX{1vtgP0H>H* zKvO+XF*zVF#s}o389{kzPJq>K%nYx!`}stcPC~`QNSLdb5vDu#ODEyKrafzWFH}DV z>Lb1A0Iz^(ml1@v#tk>|`AS9ey+nYga%h627o~2frGK&c5I1AkigS&f4%x|U1fPxy zZ{+HTAu-RoDzfEMYqPJa4OF@$0O%9F^Grx_%?)yzM1zxDbOdG$Q6xFz?0r?$%S;q#&v=MHN#EGhy8YxWe(KM@kZ}LXn%9^+)PxLo=u|H50REI$?_7CepH2DW;YyTqdL2 zsEZu8D2`TU0^?iB)tgL*B89BuLd?nKa0vGChP~R?;tb@o4s9pvu}IiLoPlhaE;3t* zgbPCdJcMP>{g(@Hf|6<`z-nD&OK#Q0wa7N=qR89U)gIAXE+dw3q6wZZM_IQB?72}M zR>oeWkUfyFLu4kyhoK0OnQ+bKc%kH2_kl#ya-nJGbD)2Mgdk(KMHi(7YQF?mlItZT zhA8v*k)oI-7Fa#|MBDjfQt}mrP(F_!GH1;)TEeNmX7-^f8cPUyNc>jwFe}GR6?UD>da7bh3w`z$Vb>=65;-P+0@Qp3HJLmWy2y+Q zU~-0L=zjx2$tZ>#wX7bBiZ)d_c{;Lry0`$@1-f_m4MBBJRwJo9(1Ov>~ z2levr{}MffC3_RFw<`R}o$4=wK^=_3vI-HS1y5@Pu}h!L$a6MQ*oyts&H~$tb}*xW zqKimKk)Bf=#CK2p?tv>Q2KZu{_sCnk2j- zYq-(E;f7%*&rpLWxV6*GBU&3$7~XGZVLB4L%IroYG@;~t{3!+$X`o^g>(qmIiTNa# zOUxEVdG3t&-!((<7(s&7Su|KpV@0d9C@}D5^ldyE(c0tL*CaD?E(h9d)S|ZgNgQl5C;SA<1 zO44!+TRsXW^9GQqNOs_4Wqak>bJbXCsh*MB>JPd7d)PJ0aLg<_r+?tncrs#2+db z#6ZmhW{u`J6EaH`STnP0RB?XSelvTm9RLKS(z#} zGaIg{%rctFY!6K}(KOz-3a^D3foN7sJ4;%k!-`HD-c~ZL%tWSD$&6E4TA5Kicccfk z)04Mi%VR)bC&y%w~F&SQH_#b!HbEuDaP_WhhQk-ZBZ8jDGg z*;lGKS-fP7U0ZcAU57BpuQ9@aTL`+IF2g#oCqhK2rA~Pkv&gIeB%)Q#X}9N1G*XG@C>=4@wv;b-FkTnYPF1`j=n}!y{miPxNl$ zG#6XOSu5u?J6*Y1!L(3?9%IJ1l<{JGM5FynL@hXtf=x(a>qNVq1&w0Nw(o;k$EeX@ zpJ*5>!;UZ1bTF2cTeY!%d>h7!aEH?c2eKAyrr>VMSiE_}0tZAu;A=2P6wz?EPYi5; zCxNd`12DTCDLD7y5(TeE2phMa7Tb=-|< zwJ&P{X3;J=VIe3q?{&r3!fX?go|0MmQdcmG06QJfW zyfI+slgMOvJ8Td=$J*Ar;L`RO@nYFj`IZ8hycrp}jQK6xnHVpze6$vVeubo4Cw|eA zqz6WmRI?!sNU)pPI8|(8HeFMht=Cj$FKMcXYhkhnePm#DWW^DvJZc`@)OA9eupo&wNoq!a!j_S^x=jfqXb3ym+jVKCkI>M6sn)kL3zf3xmM>EkoCKjGVrb6FP|o}++~~Ah1GfgOpj3`#A>({{MZR%` zN~f?1Ly^!O%$BO6F`fF3)4Zb;LkqJ5RBFQm>ug?uryy+Fr%W5kwR-G zDyCLu!sG{stqdj|e!sh4!0%&R;gGce?~lkoq2>fbGni?)3`p92sPQb~%&G1!B>0Hg zIwYE&^Sd#M?N-Is!i=npMpMN9NKNAtd9@O0Wu`@bt#Z-gw_QxRObJY8CQSaou$394 z!$G5W2smgXs81 z$}iMhe&~VjGNj;iE}TB2q|cVP&-=jB6wd#GUjqDsxC;!+pxFXnxK6?)wGY)e<Ds`D{cKtZv=R2J9SICS=K{Hoyolq`bXQT z^Y!DGC4hYulDcRc(*7<)C>rQ*_>-zwCk-bL`$e7wGHhM#*4Wm*Lc}J>BYHQ|{G63! zHUO(4Z)L@1_ff>{Ffo~OwGo3tpBZ&qQSQt#TXE7Q`FLF}uskzf445*`jRuT*_Kfjh za;(%0#HTeFUPSm7N&OlI3p$RCdHiMgosJFMRSU6WTcxJcSVC`mXolnQw{%<;p5wKl zWvJLu>278=1PQa=gQv|#LEGdRYO4SwykV$M>}V)izYns9lzAj}WXJU=l%9Yjb&Fgh zAIs4FnQO`b%uM!<4Y=J3}yi`Q9u%#u>*+}XgG8VLtjEQay+NLKQ zb9wQp=1fWI?+Im)P&t_`dzRi@U zwC38b&Eas~P;hCR+I;hjxql++b;lWVRc{a}7-)!3G#cU)4a`vx&1tf2lSm7KUbX2u zk_}b(d(`+xB8@`@17wvhu13b7G}-gWsxdqx!b&!$Vfw8sg8oOZ(*pj}IG&p|5o^7Q z1V*_Lv|(l0H6Y@UIZ0UYYa5_EltWcb6c+uUA{lrc{uPwt;}Rr*R?aZ0*IV7_oNMY;L)7n|kSO@r62M8APh2S_FDGwV@dXVMo zkxHzSty8V46RqBTqCwws0$SusVK|FG+z=22wqnd_0meF{HL+DVxmJ<`w)98WWNIB}q zJ=o&G*x`x_c@}&>7YXzLncEcne#~Yd@o2#Oa80Iit#v;iL3gZcVyAX(1F#nJW(8Lq zc$C0!V73w|Y@KYkvp|8cb&~nfCq2TL?zr0Ifw>gPSW2j&3?yxsa@eYl9MvH8SLDfA zkJ*S7sgGKxgjU+~aY&Pfvoo6@!cKvEKj()W^bZ>%&%(=Gc+pm2GiCu@@7n5%QONbI z5KX;Ufqbk$AW(>w!680}7w)(fK;7A@-iu#NSgMEy)^reNDxx7iqa#soJ!$1FsQg8n zjaO4N)EfkPuG2W%+jQkYL`}Hd&QLx$`--!S{C3Z($&`sBVWcxlD)D)Cdo>CJHJ#ZA zp^rgfcTMM(>2O_S#w}CWf++V)>ouL(pM-805GbzotZAk-Gyz>j1E>{6>YS*H%%~o_ zkXGtHNt2nmTeeoJr_Mn9uYnG>IzS|W$_--3+6ICJ@s88PGob43F?zoY#Gbj@*gO*1 z1{}@%A?uF>$OAYN)uGHb8G3zw{+6Wgp6Os?J0aSPbv`iS2;usojXbUcj9sP1A>Yq; zpRb#xJs`^+GABRgdn3W@TanSvffgL?5sg)TE{Inn;qqhI>6STzX+=a@i-h=NwoVmW znLUhz_dQN)XF)47CL^5Uu|=##!jXYlUnFyHO89=D4OJ}7%=Cf8JI~ry8Hj{2db$@Qa#wUVzztFeckoD9>W;IAaYpz4Sn%KnNU8+6knM)Rcp>eVZjkd955#!U*wjVpN(XU7~5hTv5OH$q6fbp z2Ljz|5Lqc+1OPqwa1hI}t^$Ex&fO4%Rn*Yl+!}Zf)NC)R%4vnR#;~=s&)fe4Qz)#K z!D<`_s(DIaJ{`$GB?8I)6?yV-WD|8!W5Y6lkb?=Y>RWpnFgX+5X0Uvwq??%yv8ieb zvpS>>4ZzE0*e9W;D-vvCh8+L5F~j#RRP$x=xky8Y=x<>ljab1J*xf+trOA|J3UJJZ zhZiX?8y4>kLbD=zi;3PfutIZBWp=veIRn{hRSX38RFDorlH&{6&NH4pH=;n^IY==K z!-A%{Tdaz9K{ZI8M3{y!1=@mFEz!I--9%;!kUIEQG3}w4T9^q_?&}wIsGF+TTBjpB zTos#-KsH+!#Tw=WIYX0~;Y&l|X2YYJW0m4)VMY#`maCOOXDPN;W?!q~lx@fg6s9*8 z+;!Ntt;x~jM|%! za=I2c?!W6%xlu8+F?&k$K8@^EO=b2sO{F@knqY0r!m8Lz#d$8((*JCwm(V$S9|mc? zCX2l}99Uz~HG8SAvW{Z%pmp-kXg)=nW^`goMx~HbWPg9jc0L%#P7id^u+I$-2mFu__v_UkHL$?9G;1WAAEwB8F68h2L6YRlBe1 zk2Y=bHq&3zDr^}61)fO_80WM=rTNq~7hK~A5eML1|!u*-d>R+Gtp z(M_z^y2-u?iEUv1ITG5y>}yqQ!*^p==P6^FnN_J`8?zlWbs#crt^vmhB`mGf70j;kDp-10S1{Y?Rj~ADUBT>muY#rbbp^A} zyb6{|YLs$jJ(09>mhRIP%!+zT1xrJaU@o&!UIk0L>I!BHy$Y6Y))kiVkL{j{gw=={ zIXd>Z!QW|-AcrHNE0~?Fic^@KtBTFc#HFq6EM2B5rZBrw6`PrfcU#+8x?NSYGFz{T zQ;i|1un2l7$W@h53)^?T-RTWd1iKANEeMfmiBV^?P zAAj}^8>R38<}0|mCW)Gmb$rNj|M^tR1TEnAEAX)bn9oGgJ-h^^66n`Y!e_e$;l(f| z<8~WM1Y;;u+!t-5=tW35+ntj@q9GxxuKhgZOBG9t*nl4Mh{nO$l=4}Hn$un^*}!0T zqrhlg)cJi9}(nV(TRMGI>(H=3d^srs$E8b>iAF5*D?%wBU5e_;c*esu^ z)nxKp;xzz*Q^5rwQ2|AnuMe`2^(v6ARpeG?_aHeqqK))FM%Teez8l@jeJa{nT!VxugPDk- zM)bpU{<9uL^^-`nf%%K7JglAh>#97wo%vU)?7vel&3_B@w^iNHcIKZT!H>+gBB|!H zKzYNz_^f`QWxaw_f}4T7rU|vZDw=k$9bkT-j9)5%P(fccSzN(8Y%xAi({z4d&bE{k zI}B5ds$-a~-O+y*l+bqZ12rA+DNn1)kudGAcCZosrZ2y@o_}Sao#YB6w3gXGB=ycG z3qz3dta)X5eauVg{%%dk8tXL?m-j9;@J&`>YZS;6kj!Z^;!&l|(nh}q7g>3}(g+xc z^mF`VTMe$xAO=27@5C0L+qBT927XP+C-a`oH_xY=1K6ixf~XGuqE#zQIReR4swoRW zgRv~fx&f5KOU};lL&_GnCP#+U_wh?iuxV0Ivr+S?X)VVZ z>s*_Zlwnf<#kQ7g2R~2~zz4D~v)I(^*O-2_75}x6$!$ZRCP&9*;MXz**6MEl$L+`Q4fTT0kbp;@Lo=OmNdC)QHtI-rt(x<9wGJ@ptiRWAt$VosGJy71Gdl<~Jg7 z_HC+dXK@3Pu_qIWbs*DQ%%4^)#u`YXHqPHIv3uFj8<8l;{7@xmY^zDUMKKIBtegb4 z<{&G+ml}jcNV%N@08nWGwkx!j|3WGjD|YC}?$^LK)q8tdX)fdU=R{+8yXbyR5Z$Mn z5vLYwSMRsb4Vhkhx3g3R%dvN4)(z?Zu=gf_b!K(l|GhamxBHr;`*M?Z+RoB!O*^fm zok{M!Y0_q!dy_81$R$maHcXp@EHl$#78sBhQTc=N2Sr4L5d{$eSCm~uL=;2?MaAK- zuZr?VK;cC|d_Ujcd7hh_w4LRpGl1_r?aA{zXFtF5+s}Ej%EsUIIo0 zsKj}a9v~ptbbH8hPOG3EUmRXlP>-)9@SATY9A^{kuAkFbLVXv=p!U}!rr!6W!~9;) zt?jF#pXiCZwVI^Lc`0!ZSMka0yo9)qp&yS>?>uFrlL(EwBGFwotYgI7K0j+R5l6}s z-hJK8a~e~{yrjh!F+ZJ+tg#fxOnBssyj|Uwj)4xR> z$Iy3#5JH>hp!dv24&F&`f0R6EH>6e*=*=Fqo6?AqFO2ezjyq z3!yA)g+*++!U*Q2Ea>OksbsOWStiZ%M92UtpY~+pK4JtQbd=U|9pw|meTp!Tr71%8 z)4WI|98oVKsAkqsAVW0?oSf)+J#v|lxk3Ix`zhKYE$IHmZ7}1w-NJB z0zcO`*YIx;@!OWQ9K|%YKeMbQ+gm?oC+rmAtrPVGT zOLvx*LJbIh5IM0Yy7zNm%KIJMRnJSfS95U(_G>^`u!}_1^bmN<-f<{W#_J+ zH(Jg8VeTur>o<(pDque@^Fi+V;g1X4^=lG;&0WX&tDVZlp{U*Ot=DnaG3k4_>k#st+;y_I?mA3c@X?{y1Kf2|wcfWdm~U~{ z$;v1OlyMJfHNGI{S zh_*}c;L_d>)t%0Ae{FPsguCk1CX+k3w8=1 zN8!=Zbwc^q2si~3m4x_I^0>a8#OWOF`26oU{#N3$gtrpjO?WRsv=m?Q`Q0j~Gq&UF zA9(&J!WR_>jm6hCo?8e92nPv2Kxiezm(H?&v~=aYl@K33{eGTB!|`<_N{>%$UYH&q zfxIw&igGiA_^jfE>G7ep@nN-bdw0MubS!Rsu55g;YMdUQxw`B_NlWh^nz#)FeGR^c&`2oHw-Q{^#&?CA*n6s=@5~gc zk@?y_s?DX^c`6+szE)FiEuosA?_>4tu0Gg}ukv(#vmIZ09wnS7=qu}m<>IfM7skh* z2``K*BgH!`C{_Dln`HE=lL6Yrw^3`eS)~K9(~prU;3PIVY)sTjIU;%<9X~ai&q^p z1brr0-Y_Xy$tBj`K6`1+cj`P%5)Y{l26`S{YudisVh{<^L_ULW2qjNd@q7DAeE z!xhpMzlWd??DPp%e8pdz#h;qR@%n-+ZsYa(a3i`D-%HRJU2%FZ=>vrFdsjBr=(C3M{Q6WQ{^Ubx@ug1^ z6iyNJX+nIpGB3hu&7nRHD5uj8meFaP?rzd5+UxgPrnv!UqZ3CmhHB8hN#2RhwhAD>lB?rlAkQPJ(Qb z_wRvTaMCI0<{j}X2{t=m^#p+3cF_rY>Po)BMJhF5qwLCfLs_2WEiS^hNyt)R!3@_dx=F@l!H<4a?Z zZ!Y%1$`2a{x&9R5G0Ll^pk>AQ(wcI-uB^4$_}apXW6?j>lwC%%4? z=hqOlMx_;>-y&$$C%&|Nv6HZiprwZRDvy&tI=DL%(nksM ze#e*U`~u;N1bHUoD~^j{_gL_gi>w@O<>lpXR=WJ&@l`?GmEz^Aj^qECGVvArtyPb_ z)$#QOp1(+tW4W68*Ae6bj<51`xtHThZ3qwI`B&e{`>*tDlzxJHe0A`wa?c{1A)FO1{PA;yXP~pNhh3 zxhp&p1^M1oMm{$^%Lk_*-<#rArx_2=^1&&{2d5w(oPvCC3i7=vZ#O~D^1&%I;&W4+ zxM6U5WNNx$=)%Z7^=GDL z&yJ5wHDo7-XD^P7&rCNQ9h>Q#J=4%Ob#``ad?GV3HL`bVWPD_LXu4tKo|!3bGh^eI zW~a|IOiv9rOioPA44t_!(h%pFBBeQT?Hd}NxOj15{2Et$VeCvprl-(VDDDsU2939& zYkc^^?AeiP+}QcM8_rBmHcSm&`+6@9&z2@&)Y@p!O%tRhhc8Z#O*dpm?iw2&X~^e# zbA`4-Lt$ceYWPVQ<5l`HHa^@iG&$B#U$6gh&y;!S!iA?CBHxX6r;1|}BA07CSb_4a zP3;q@cqou}Oxk4<>E1<$BQq$vP6vG#Wrl%Xuj?P}=x}mD8V4MImRUD<= z^TqR%PjR!;!(+v<=4%be#~SRp$tMH5CZ>n3HHBV#91Gkv(Qtm^;)sd1hI7Ni3VVm9 zF76$l7$4a?GIVBaZ&PFazP-(j%}w=9jScgX8embz_7i7^&lXLN)ek3-{xgWQ;>@MV zk?H#L2^2hg5ArBPSl;5)5N~83MuZfHFYepNE2^F`-y$6eucJd3$1Yr=Vzj;KOVcwW z7kNgbo1Ph(nwgypFEH(5sR7hFd%rL-eCIUjsCRllJ91%2^+d1drY2@5i(^yIor{_p zIX6ZFQ^m=tiJ6h%nX!rSkQj3!-q7V#+1LcViyBfL_G0549UGk>AHxO;XL&-e&=dU| zpP8Dt5MnM4jj3)lJt&;6Nz(9+wg(ZYSH)rAVHpI>vm?{PQ)81e6H^)xrRM0Acl5xi zVnjf^q6SVC!E7GU0LwsQV;6E3HNEs1MUbiEfj+A9lt34>ep}p`3D_QyD1tWV7+BLY zQ)A=jD2FC!W1GBdCe)Jf$%N;WQ8cQzCX?P(`Sq!!-%#sUZ}%?MP+8&kx=&Y-P@PIv zCR6Us_a}WSm8|zZRZC){`{Pm~QSKci@1lb0?S5CSuWlu-!Ebh>szBvb%r8$R)Aea( z-Z%$~2QJb6ZeMqV;^`{ioT{gr?bUus+Pjvx zXNOglU#cc*DO0Vc?oL-aU+-?TF|vcYzB1{TxdH1@RYj#5ybegn7IH73w5zJD^f$QA z+-n7HNF`gnOILcoF6I7Z4UNUaX{_>l$$nef@2&SY*894&zflc02wsfl*QcZ5?4ovA zSnh`|tNq6E+J9_qdF^GD*HOP}K3=L-RPdZrrLeYy!WQky9!s-87wN7Su1mGD*0cW^st7%M&Hc%A#UjCPmBCMb5`G&7_^ktAE9?D= z6g_2FVuA2s-|p6=Tm7b#n@D;<=zY3A<$n6XWL0%_jUg>5J0O1=+y%B zZ36yg_YnqeaJI;IJqRxpoa+suk^oEK2)g^!KEK88w^%{2kaG1@mUPFGe1g5oZ-T&> z*OxOS(PA={O!ZkezFgJ~5T(2u&kfz!Q{IcyQ71$cJAB$2y*2bpQM;@^W&N`Ltd05u zzFw?v?8_SHnSH2d9Yo_tMer*WE%sm8%P^u>ei$`=@50J0bq!hm!$4y!mIt@UYm%Mk`wJI_v;S=Gh(#XD)Q|?>$BFSnZ-J_1wnnN_zq-+v#?!TyqZm2f*j(gMAz{h<( z)Kw>5ztp|=d9+qt1x{_E?R(TwRU^{4C2H&z63LXR!y8d#; zE}iD5Am4n_j{wY&@K1^4?bK4`m+vKC5cAU4l=+qOGBcw8Kao5xDih>)*zg|~e5-A) zSB$Eyr2DITlL8H+_z%cSqhO}0-9J?(_ohvN+Z@YL>wZadTqP;F+HYy}$!&g19aYyw z!;<<39&Kk($I0W?*-$RF`Zex{=o;-pa`be>{h$*AjqZ}CeTME!!c=1O#rRF zl`3le_S6c2VM#p+F#VlDriUuDAmAR+5UVP|3HPh_nJO*PNz=-~l>3-80;n1Uu5fd0 zYZbwLbFrnNAA7%}-ltZlwn^QuPt^o|2V0_>ru2Tzy2<24ifviaw=GHNe|g%M78FCg zQ=^tA+=nEPQ6FJjt9|VeX;jv~kVPvO?xzB5lw}PdxFx8xA%m7Q+#4-Jc{#0cxL>sB znyTt55Z5@E+ruPPAQcb#FQdTfsxz1!^h5OchN%F3?ykD#jrz)e83$Xc&^B6>c^iMJ;6T# zW$mt0^;VS)1Gw8uwO^+DP2m;#*W1nz=_G6{SDpUWi2C$k+OQ>*TDM&8cOJAB^e6eK z5OHBPa@55OY71l+po?)S+Si7Cg?^G?@zaH>$6i ztls_nrTSnFcbGXWTX@uX-}~vvI(Lpj>ky^eDSOX~PW(ZL_lr5)~9 zA58n&wCJ6`u#6?g$n=}av`%6`4h;7r6o#BV7Jg8lC=Z0S9O!b$7=Haj>v$%!()NBkbhY#YSId{yIL~2Sqvp2m#fj; z#;L211|xKn4NhyDrkccqt9!J;X;ABHCDUu&uH-FO98Xs~p3s06P2HbUE*Lo;JFeUB z(K}wJHGYHp3P2y9j{6Ea;(WUDc6#go-a#r4X_iq*Q8GCeu_Mu()Q7b(v#B-Tj|0MMqIU>huUbK-Ct0JOe(C=0B|9i3|Q-D9d)_g!oSmM!tKUL zA&sYXX^q%daU;dOl~VNi{U}{>t1)qSha?fnI&;iFgQuHR!!1_#3Ir={U~;6~r|(a? zSId)vr$ji2a8o};^Rl71%cyq$1W;DEufX%jC|!dA;$_+>Ew#>|soX-9C8=8kd2EWPbq<|2hIygR=A(nD66r%h-U!c zzSImbYx(Fp>DM0Ffu1XKr>-@8~1K4zZ zK;X@&7`{TgH{9o8s*CYDV+0%tAgi*u(UuPPr%M2t+5{O=ZW$w5Ue&J|b9D9cb8oMDlu7gI|m}bR_lAjJov(2PmkL{8Z_0Xz_br=>7TB zL)5{fd<7T#ng&&{NDx|k#INe{YmfV-J1`W2(;+}Y`&QgHmT9o~pYXtMZ^U=3xd10& zjf-2v$68wa@@>AQ?pD8ipWoWV;FhNjXr8v$?c{~w*RW>b&cJf(nW4R4!ZVoo7Wo2} zV{>m&&AYIacA%V%q~obr##Cs-jQd}VhGhhb`DRe<5(K>8ch&iw+kHRdhWMM9!@qF!~zppY*z8G@XtSx`0-?!g)T<_cV`DYB---FD~V!E@N zaXr(o#ae2X-L$yLH&8R6xovxcW!d7Z_xoM+eJ7|nkq-7rwXdeX+Subh06SZ{&ac^y z4VoGi+F`1YsNFv94@7N1WlJ4W{4lQJCckuVs?|`;uupq|+>cd|3v+yV%6-G9Yq!_> znp*JdJ@?Y;b%&aO;!VtlkY$B?*Ml# zmQCfhs{NFC3r5@v9|TF~BP295g~5q9(tbowGH>R5|#kzdhtc~ zDmXcaShY>S+1|{g($}rKxnI&;`|8bp>n=)c!yj_5&{_3uNV$KQSPn5q(ji)^RmT_O%1T=I%Bi&ZPTq~H(b@4aif&m9hnUv5P2gjq24#@CAGzz zRM1LL?oDUcxH}=xCCSsLDX;aBij|tq;P28VE%zEQa|0>pymAq&-HAWx;ZWJEy%%c1f`sTH6e#g-u|Rm!US{d>grwz_vMLUB6cm;9{7euzfsda6B@o*@~O zdp~VCm!q7kji{~69RIQ=t*S}@LSJ*u=`=0{+2%IHYNILbn{%HM<@rX2*a6qx>9^is zPN?^T$j3yXDVK%iHxcPryh)uR4lV0EZ;jzYJYn>*sIe}EfyOA2WsBT%!G9)c1AmudTlgEH&A^al z5c>*k_;bH!{BR@uaC1XLEx^LH?Kf}r8yo%7Ccp6}zZ3vO-i1YeC&jcs5ZNj~p$Fr_ zJq&;w_CtZJ)&P{{sdc{ZR==jpqwXvhhlN@;){3{HCvI>beE^8DGAkn8$kQ#{Swc&> z-+~&pu>kgEh}<>E>E}*Ms%>(wpxV?A`a|`8cfDo#{AF20JE=bJk5kd+Q3)_0`nKoc zD8xYwi(A`>M5C;8uX{k1E_a^;?-w;%)X$Vh;q1N9FQV%=_%-{jwO2oY1U+pXYN&TB z#VJ|ZrqZfLEnNeE(A>}6SC2%bxdtot=KIrX$-BQq>(Rh|;eH0z;+$B-Mc`Bb?*1kJE|JN{KKty*OTrSE~#w{XDCM%{_Q0sblfpg zwz*%SLhqhCs?q-|-C2`bci6A3m5ASrzYi(TL#-Z`xA`jEY_;f&xisRsp@Dffj|7<< zcE?gm?cI)llO(_S2G+Cp`;~WCyMJ=uL#%roms+wkDJS6~EyKQ?MmL~&0D!}u?U|PK zeduyYpLQQ`Vdma<-)PypbML?JSlX|`@!U|ajH}$+83CPt_w$ZHAnUD;S3jVnW$yFn zhZ?rMyDzdRzs>#l1E)|V8a_paE$%~<-RORrac^<|ll2kmc{MK^Q|s{6G`sga7@#hL zZB3(i-9J2Vj3O!Xh51@vd)WK!zOj~8oO>lYE9#E>LNt3XyB{S4YvLxqy(yZ&71rXC zRs_ys_j;Hq4gN0ZEe@^)1%4z`#WlP4Ln;a*CGm^qKe(nAZrS>q#ZM(WX{cv z*A{6nb%~osVZ)J^7OM>lHd>UC-liBW_uvzsdI&}0;|ymx=&%79(OR$Qx6pMBeS`ZH z^t7%XpaHH=qTdKy8^KqK>~XKeu-M4L7+S48ZyB_9*SLQ%0LhkmWikm=VS$YMBgEFn zKK^Lj?~47^OThg(A3p>3?lv2(3>(>dF7-@W1_Lf1&S4vlPn`~f!ctn{eo`xGe#rqF z&*$iQ7|+k5C$2;7Pf4B!&0d?Q-Cr7Sb*Ze@Vr3*ElN@_uB&n9MPey|9hLn33h{b9r zs5VBAYEb3SanTD>?#DsE4Yo8S(-Ua@opkwXn^dgChcWjrU#!{z+<_sQ`={xl=9ZP3 zXw)!ucQycA3Bm}u2ci`&GGh2z0oj#wV6{3#nL)dQ31JZm1F_oumd%IXO-|(VZn~nC zi>2-(Nke$4odTha`P0uEWk4(3n=7?Sg%?!wx0Ug*T6TjB+A!=jfEU;-cJHICPh}{x z37~%^xDf=lhfC#CsRBWA0>ZubbKHLHtQGupBvWX>+kjF>#F z8V^$=`L|GVo!mIox5@p#Hb+}YsfXWy`dei?%5$-gdY7cm`2*2?{`(l+`mABJb?Ys- zOPDU41=4hwkxw~@V5R#;ax|G7Mc7`Sa&MyR%c@V49~$}i{jE{Xm$@W-ltx(8NVZm6 zbw6j-Q4@OiXI<#&8}3s9rs}ikg_?NxDm)D|_0_~NbC40eDD`4A0QI{OqS@#NbXOcgwwY&Gvy+Px{6Y!#z$f5Tj>hD9v!EL;4r_2%2Q(y8U7!*x`% z-95juo`fy#KUukiGgWDhh4${-jx{$q{g$K-^LH8g(k||Bjb-p4_eXpyAmEB1$^DyP zwPtS_$S6+|ir5O=AmTx*)7YK3Z?u|g`U22J`rd#xi_ETZYcRSRL8wW13rp~U46ZXZ z6Z7MP3_{CYt5OX|)E&71*O@16Rq7TQKfeU|Zh%k!2Vzz$xbD^D-l3VV+Ua-PfMDIw z>TW*v5ON{qeg!a#6N{tDMI;`Q!gmnX;MUeQ_%+6$ZI!?l4H%yavV=igqjt6kXD#mA zU?4t4HjOb-F_ju5lxX-kGWpd(6%WWzt4W3lq})HEiK}5i9g5U(zp?bH=&%MC?r5FB z>{T-QQpv?@8DO>hH>x;@&cY<$*z6Y}wHuE4rFDwi=r$sN(EzvlWjp+?SwR#>b$#V_ zu+sfMbZISuesP^J$h+sOPmAT}Z)0rh;c>*f&s5a&wi*;iwu@r_timc->^_2eQ`7BN zH2K5zqgLW?fxv3id#jEmnAY?uA;WJ+bGA(WfAJ%T2A3hjCUGXMS^GL9btqL0X5Z#M zaLHP7?t{Qp5%0TXRXX>%I|XO;AIyhlUD?0D@WQOR|z0vz^>*f@45%J7i(8Y1z09e$z)pLg3(>A+Y#bqtKM zE8Q2Y6N}w{-h*CxL_!=K0b`dmrdu1%og4L=*Li=7U&r1(zpa(K-<)ReBV`x4{}6HR zR@eN>9y1=^dVdlZ;{jHfYK)$irJlw6&1LWMb+rL2`17*V3#nvzy)l4SK)Q1b0Q&wC z=5A}XJl!Jq!^vY<2s~q*h%j$Wj@mjqahHtrUudKsAo!n^ff2p%d1$*vHN-?z6_zTX zH)f4iR%=f7y3d0=^IHE&AJ)=7YZM_yqnar2a}lZFoerd8v2W&QXz1#ZRuHGz{rUZ) zA@iFnU}21af?@d>2X?Ymv&RH}*W2@A#HEp}}-0&A6v}LmgEyCY6 zTnziIggpITu8LJ|0;bmE7iH27tn6)&poQyv5Rf-Aie=DA+D_A!Bu{ExmDIjge*_9- zZ_+8qhc2=PClF$!Qzd$fBoHkil`7UsUku&{eQ4)i$ZP|>MZooErCe1h5y?(2#k~PD zhz-|lpGw>NFFgQns}Z_<&h*apa75Kdqsv2%*I6whD55u-#cOJO6B~i+-1AxGr8#Zz zdw9woz58q2nQ6o+{>F5zR%_Pmm1A6ceU$HK<9weZADfmIZ=+)GzIri@VwZBiY;;N| zZDvyIgNLiumI!Sp#NS9avfVya(Q;*3;@^ctxoN5*$6Z*=q-fgx>MAIthO!$#fTX(% z#SAAba``5|q0R5O9s;SWVcjQKE5Mpg;71RuH%%f>aRHpWwwo3hofatzTDC_8GEZsi zZCG_d?uGodbDlsOg+6$6AETpTq0Dc?JF;2cYpK#&Efb|{xo;UbVRyM;aPim*&1zh< z&(Zu$m93{<7p(lbRtGViHM20U|X>sgIn=U#j_ zZD{X;M!_QO52Sr9o@?QPHgQ#@S*8aKevf5V$qk&FT5Z*=?hux;2E!9?3`;wtkQg{* zw1cXGNG-)xxQi@v*aK>G$P@NhDMxre%qI$=gzd9od%5jQAstAv9%dRf8!DRxUvwg3 zpW7P2ci)xZy9W3gWcBGTelR9h#JbAYG5$bZ((7%_x={j%D#I2A6unjME~81NK|YBU z^1s|_U=tG#;M)U+FQsUxz@{ z`;I6+PM?2I)*_|ZHLQIX5;JV`s1e&+AGV(EvEC)Ms%X)2Rm)3*WE3GR*!m%BOWWlc zX$z0=(DE%HU<#2o(s&C9BXw_?eTdd2sNkNIfW057O+R zx2(xRaSRxW7F(g&hxoYLvGXjd(GOpz8Ru`^UOxoHfmEHZ6aQ#Batqa{!`-@TabicQ z!enY=tD%oR7B?*_uCPu$EWywigS(rt%E-rrtCuqg-Yev_nz?B#lG;&Eee%|5XlFIF zM!>Ss->8+TRjg3+#OAUM`$=imSe0c=4{7|IHbi}|?mmVRVc&+V@z*!_Cnl?zQ0kbKR_0qBlS=L2n5APgR7* zFcDX{X9@w_@?-2Kqmn9Z^U60FZ4}&42RrIUQy$6M_ z#*gA!PWx8^fu*f}K&BaqjY?$mPi?JiEac&GmOm@_O%3f>Oj4IlNpOFP!6d5EmJSD^ z;kiW|*$o=4V1bCkhj_r%7;Y(x25$6G{LKsO&y1AyTUbf5O}2P%SY~l@gi0DGv3PMR zoUsu9HNhx(TMT-20Xsnx)w`wTmp z*lG1zDwTIcTPjucPTj%FeNlGS{emgAEOmrI0r)k?;v{SPlsaIWD(%(&%)Q!%(`rDy z)cW~R#$_8b<G` zjqw!;@KAS?4N&h=Jt|0P`kq7!`UmZhSMe=p zjW|H~fKun7Xp($&M$m}Rxnxj;9ND-K>a%gUl*+VHhCRlNc(7Szc!Huo% zr*W=J>ylO} z`N6}tazAC88F$d{Eyn>zYwmZZlc@tX_3vPVn|I66t3VS} z9iQ6YXsnp|WdOKKQ9Q7jNjS&AZysgfwtTe4O&W%*t`GY{0afK<_s;41BWih5(9mmT ze72ggRLA~8jHNpE8Iq`O?Q~09Ybxb)d#P;6_3hCFJiF?4Rk2yQR%BUA6s*l39xV!SpI_yOYZ4{gg9^6P)_ z5owM45??bd0sy}Zo8eP7O}>P#d`0f{u(nmOn(LSbpV~C;H)B6H){`G5^Xz0LMBv`N zUgdfJ(0N6ybnjh13KRBg+kAuji|4_k+%Mw5(KG&L-riD~Y>29O51Upn7n9b=SF92C zXr`_gwCa+l;A)H9YcX@EZV^5p7B62=!8%4*q?AKcWaA(Z^nhck1n(w}YxOlB_jR*k zZ&aK<@Z$M7GfTB^cx{p1OByuNar!49v+6}l()|Ne0H{+-zGc0Bw z_Ij<~w8K*?cG7ilBp8L0igCRguUEw=#VvAk>~O#MAUyXkNNU>Cz$@hi#8+ zn(@02A3p{H{NY_-ETCeIjx{pF+zs6lzU-;2&g$#*#n<_pTMqMS#d<~WYGgAa5`G6u zwL!{!6WlV$f10I2)~*maRqpdhNCEEEu+|p5Yq5mZ7x-1U&L9_!r%L_@JvA|}?rX60 z?U35~CO$A_U)h)0Yz{vN`=x7{(`r+pSGsd)2Z6BBYo$960B&#_a4Aq=gt@P-iZjv? zL^b;DQgZx{S-Kk{80UWf16xo9>wRmp-O`df8wH~Et^QdpKArZ@0zq(M?)J}W2 zkHa2Q?ms~XS6yS(e3h8+{aUFulsxSkk)wXO99WJyiJs7y#4&sYULEMSqLEHBFAz1X zk|jqzXyv^Ul9pXoiD1Xy!KZbt$O>519pa?$NI=Xkwd*j|DsEg$yPMp5#2y&Jw*cs6 zjG-YghV^PiA86tA-UK`Q777f5+Hm@Xr%#{ri+_kUGVSkP4+f)}`YLw)?A%^kyW_^% z1|#rKChJA@_VI`NdB7*C|EuJ0*HaragNIyrh7{W-C*rdG+EUE&<|eQh*A9Q-$&evW z8#&a05414i!Gi1jvhBXQR=Zy|KEpR#JQj(N>)s9Q*0C?PS-b# zGLb)hU$U{G`NjsgDjs|Hjt7&+ZHCSqOJR)JCx#>}LD>=<{!J^vfrD-UKB&^}Wo#>2 z>%Jri!b<~BHPF@jLnH#=BP?q@cnoODrSIGqD-0mV5Fh_b%7Ob~H(Jl;kH8yi+}ADg zB@T?Mq2~XH6o}vR6np3MlJ0YC+L~3`8m+4Ol}AuBt>T9(So4wcY|C{xk86d{-u()T zyI%V5>SuEnN{#z9+e5J$R|o6m8r2(lAR*;ge$-B#jqYWvLTx^6Ku0^!!plY$bq`aW zbMK?L@_e9zEofDJp1&KO#p{RpVD6g{{G#B_Is1xW4g zk=o9dEiCd?T7L^TE!-``Vbhi$;e?0E#Ao;mL;c!U=ARSzgicY?DSDi5wBR%)9kf*6 zR611Y+MWn_^@Fgke9qhzPr!T9j`_RFfn--BWt9p-x(RQqE^o#ZUZfyT^GV z-BpgR!--uBkN@JZg}Gy~&gii%}(Ql@2E3wftx?YMOs8 z8C^@@iGs!x{QW+paZUc?oue`^0mJYX9iTQWs3z7KBvyZaLgMP&PA~#v9`%IJ%Mg0* zs5wDqiOB)?v>bTKPKbOe<-m7_I@eZcKZZ=Y3{T4$CEV-^jIwk_BG@a&d8HE%jg3Yp zEgFX{ow^8TEa#wNm@k7ODibf^@Ao0Yy!u>U8RP!1Q;Mz*pqP)w%GhPN_?;l1Fq4Xl z9Df`%07VSP$9aN<<=CmTaI~i(ZsLStWdAk5$SWUq`os=Q{a#e{pGv;{l(qHf2njZD zzIX91j&awauIHuXDI)O01&C$`r*rBl{EZ`+N2YYNDSA-iR>Q0xxCWT@y@(YH4jO-& z*XiW>d8fi(mDep`L36Le!n1N_mH4>f&>uXFLr)oFxUwjZ=knSrY*&|;Q7@jdQ9n96 zgqvN){lL^K$n3dOvQ4@QwdbOYMJ9g2EX5!D?`A1}Z{W>i&ZB0;4kL%9M9;%=nk0V6 z%+v?}JDRECCo%YY1qMAebl~Ftr;N<5j3iIX&a2AKYs+t+sDUg38M&Yz7Ko@tR>s&k z2liV`x&4fPvYZ`0s=W;BG}5!<@zEON7gIA6e`O;7&z~0g-({+Nszv@n*8SZ@{c>cE zkpHUAAK~wn5>1_5=mA=8;$M#Q|5hHLg|ipjWfK=mfYA?e0LX=lABlf8x%>J5j&k?% zpQCzO(v>9LQ?22vy|HnYCdP+Hrk^s_Dzb=w4d)s+`b35Kyh@U&8v*#u+%ue$QPfv<69-6!M!;pp$|12Ze6`L1NEBW^8mESwg zjVF`!Jr);YtzmR%_QFi*_svjzO3&y6#h?%bgQDy=(4bF9u)B?7*8BSW1OfReyqz_TlsIMso~NulYotzrGYiLG4WEaJtk|TuYZ|l+Q^63o;|MmTe%4M^AWuT4f7Y9o) zDB7#pCYJ+(V=4i}x1L7x%YK*nN!vAN^mFBjTY&A%VT`?VQ(8_2q=wCNF+I#9fU+NA zB;9_*(LBMIW5In!4tG6`1y{p@%ciSbY#2PtrtWgMm;KadJX0m1D|U3j;6M6(4F4zT zw}~H<)x}^3to&|jV0!a@Ks6Esb4m_56Tb}MR3?6bzu%vl%%j*P->XX@sOZ;N7kNzc z1Fxl?XM||~U%4V1gzuHRqu^8JToE3qQsy!zC+u(RVu|-rW%$kc z@MTYN6j+{*_@bqSi1U;1KltRup|Np{b^9Uvu?c;&Ql2-&gq#a}?Pk{4Z__8b&6e%p z?{~^1zdQb^C&c5FdFaB0YfRWrHr79Jr_^I%eL(QJZ_Tc1n1P{z03x(4H^4w5sAqb3 zYHV_5VoD3SplD(c`gGA-XF{B#8G>BoeG&rAnkt?$QcIlonP#NQlQClycgOBTOXC7g1MSrcM>(G-C`4Si`SS2aDYdc_MpcrDh|^#Qx`_YS(QFp zW^@!MX3k?gPfw1FoYivC=-9d0sUaPDQ5-(AFmG@k6rVdgbYX0CjAEB(IWsY>*w&$` z8L|wI4P7{rINCdyKHAmO-1arDB((9GVU zGh>I(V|^)Na`y1(ldJ3n4mKIGdn&#c5Zy+Y?|{> z?Cg<|vy(H8Yze}V%=}DToV+kH!#=)?<1-Dz4TF4JI*nC7a!>u4sjJZH)$QTL#gU8C zBQv@UPhPV1UVJEg3(cko`gLw(Mt#c{a`_XvY?C2Frs?KK#e^qmn&-{&=;+kQh$e+I zV>AU%c+M`&Ogx^MOZ0d3=WcG#_4FtDyPGlt`R=CTnZ(KLK(?!p$QOGG1O3H;OOqoB zJ!SGa5(fqg?Zs?YzSz~980^UR^bYnYHdh$v>B}mEvbHrJOq|J$pPigwj@!CYd}osLdgxj1ol_QHtpVrnLFW_I*oLLCh? zWINiryA!#-j$A%(gE*ktb75DDycR{U&{{9fB(j07obdXAn7xo%<$-MNz;jg8U0DN!tnDvHHK`(WW@Ti1Z9&F5~jDx1~K zoMASjFP>)>FN{ouUK*&gI*2#&C*1FHk%s&DH8dUIgQTn695+rr+YJ< z#g2SiPcG3mFp%j?fVKVE#L4bl@6mzI#0jP@XZS!xnt8R?9N;gw74IGzn<J2x!d_(3&HlK_8-%_U1#0Y`n+`Fp-Fb~0m{?z%0-mYcjl%v!76i}a+o;R%83M`np%7igw290N6S5qZJT?;M$(w1REwVrc?xo-%zBmjg^}qi99_ zDWAWAuAW@q;6NB)MCI*JdD}of*WV*t%yb-O*n@?9v)~@s|HYwu<{`NaK~wbvcQvR>r8-UJpmNf>8?UwrZeBy+c#J! z8)qRmFxU@5W^!E!hD3YUQBi27peX=e8i3&5WZa`z>^;$yDdxt9&RiJj%HNjg>KZta zIMX#gGctA85Z#D#2Bu(`96DGS1XER~vJ?mMVXh;j%7RRW&4vD4E?eyGJ88)|aF8(s ziPaPnTUp<`dQY@Au5SyV<4|Vbq=&;1`_?9rw8&~Jw;xQ(odZ%VVW@;p=+3)CZn+_+~Uo#awE1LgozEws>~%iM2l#nM$U=OLjF{) zx2Ml~*&c+>&4xBHV9Ta6QJSq`)Xc=0i}^4|CWGVrEu|^hpJ?yM=Sr_Pm!1v=@@mXW ze$0-e%t_%gM%Hv7^rX{>s4?hgW8)DmGXp}!{#?EbQ0TEa%z`9{O^yl4uC{hqkx5E1 z8F)#eyU>$ADYe1Sdm%LsW{w9|p3QXhSiK_cSh$@Xn@XUl@`=uL5tN&qjPa=0J~0vK zr`S{&D7FuFA6M_iJ|b;xL&=Y-J*`m5IbwCK6kjNNi;yv6YF$RtA|cr_a*`5jjI- zxFz)|LLXDS1o}q9c@uVxiQK8Kn5oN>fCV8M$}vKcFicBOHH$rM1*TpyBLn7{$czC4 z^yVOgP?sJ7xFhrgKSL=xREA?loYG3W3jKk;TLNx$_e(hp;EIG-2H|B~!8l_;P^_mB zOo+23>^oq}j^)Gj8OKyAB^|=y&Q32u0S;tUw>2dSoddmX#}kEtu6(IuC4^1%oa#rB zgOkA4)c>Y@u>%2xMqtPiYtoVE$p#FN?1{KtbZ?LDndqJkwKW4nG@{()g0wg~I!6wg z(m6fBByy+WU81`Qe5E^Rn&QPh85`XJo8!B?#?Ox2BW9t=7fzH0z)KsFA#i|$fd&NG zax4}%Z>MX4l$eaU{zz{@phK<^59^VpY|0BADoBeC%>AGdkWqYKUxEK*N{T*RFAPw3 zqk50ldWxQ%$o5DXElpeV{$f-4OPK;Cz@SkNAifhls7zCrdWOc~J@Oz00cFagO{aD# z7e_8m&Ri-@^PF&<9GV)s7!QIz1XCcF=sY=ys-yvk6~kf?>2q*U^VwV>lke&u=*uU> z>w=jkGQ?6*Mes`lldc)o zt-W`kyEGP!v9WlD0VX=4r=m5+?Dd}C9hYoNCfst+1c$DkN5Ew_Y87b#>TvnGrF8{Pv`&%)Hv zM|%T-WFwZIZ3-+s3rjEL`!g7P($Es^v(sh3>gqtunal_pq%`ULV80oGJsAKM)NjOh z+YH{6GqW>%dm0Qx5@mUnVK*@Whf(FsE+rz^wPC^<1C_M5L9a)l{f@3v%rbTi7#wn# zHUS=Lv@q-#Zed~!a3QHNF$JZay(h}qtQrEp$VPlW3*Q%EL^&c@L`**m(^o|~AZL1H zaLYw_f^0N0Zxo+m2q7m-aiD+}-FKofQH0Q==tDM3`@+aHVfIMVvUiY$3+&pSu1p>) zBN(@Z6B$(dh{$?|?&&wfxFEY&HAO53Xv@r_BbiKpw{hj^iBX&aCMa$0Bv@po6b8Yb z-fT|^aKisNM-(2isAEAjGJUAT(jtFIz`t1WHhCRj7)g*U5+pO2R|f;^(0HVG%XT#x zFK}h@X3vr*)__fB=3*a%5F>jO9RYPUWFjWOOzhHt*VzNd!bj4UABZp|0hi0kl7y)Y zw)gjuAeP>XK4D-8UGMBV+Nqoa(vf?6+D$xIGp2Z{L_l$ySFmgj{Y@zg(FbFX5Twy<#4pb&gR0cfcxCSJz8B9>KR9@gj~p++=-pfa1Wn;3;#j-Y+dO633sbXG8sS#LDQ z5I|`f$Gw0$)P*{fhm+<+eFZX|iS%ikoJ?M{8q851P)3ba&&==Ye2#SzK0FvxFV>0~ zz%WDj*WFV?lQAh%T{#&R&rIP!i0PvwX@bdJ;&0Y`f-kX)XNIPO%Pkk-PY(Ra_RE&f z$X2(po01qffPpLaIE~E&-R$hdtdzotDa*2n(G4y#D9fy~E1wvboo?@m)ZBs7Oo~bu z)n;H8f!*X_z07Biw7S^6K;O;6HZ#bCswwpovjGdt`w`jJrlQRx+VVZcOiwY}nJMHW zO?mSCCG-rSb0%`1sd-cS5`*Xvi4iM07I+lq1<RMY69c@8!v;}LREf@oB!4_x> zoo@@4K-;0o z3I=LBR8mgl5sRYTT{3N$h8N^wFk(xM?SI0B^Dsp9y!Dg;iE^9n$x$(&e9&fF*$W3 z*9#CZ(P1t|wU%WlceAS;+14!waRSl~=w&)4`a~{Y8X(}0N5u@39-HSL=b*(@lrms9 zm)u~H%rHoqvXQv^#L$J=kwm@|OzO(Y5otz>K>;;Fz03rdWCBbwk#QMdl8H>q$g&JD z$wYSLp~TDt{;cAeOHw3)T_fHayU2jYJWoOK3|JofMHwwhRp_a4Rnv{od%Akzo;``t zQF#Pp!Z#**C&qh*rtdU2R;$_vViF;m^&EoS8k> zGXa(1HZ>F6rYDS_^%Z*y89~jVxjpxiHRL7-uewGZ)603**d%apuA}b77phL-X9I9c^9mf=jsJ>wr}YsZOG@ z+FTw8%2Oaj`kw1&A?As!nLUp6ZS97;@=^H>8vT@9VXWo`5zp+GJAq?eNRwf_M6A%< zAEr4-5y*7s+RzpwGs?J@*^jX=E-~2OkIE9*QPAik&4uwALFF}-0*$@4MFOWS5;$#< z|E3LvH8MfVoF--S))r~~ZHS)iKzDCR6^L+NXP<#h8goflClDuaTkams*~CFRX92Cm#p8#7ByBLTeq0y$@MSBT5&@R{eySuw$y&p`ESCKjfdo#t1 z767y6OvvWR#flQ70i(D$HcodU0g)IRFOE%5MH~xi@1@}q29|hxNlU_StF^;P^qJu? z7SW|=vXWRh5x7~lUt;e>ShbRe15KUo2k%1S z3~(@_Madn=_jM=o1DW8&H8IM_G^iAP=Iok6&9BD_L(Ml{ool*=Qhir6ANu2To_8dG8{(1GiSmLbgsCl#> z*l55Eox&9kgFRO~KZ0#hES|ut$X0wJv_(XVT*G&owVcl#E%xX826CB!V&-TD%*+%{ zCi+j}M!{gnp~sIDwS!068-|H?geXs!GUZQVERnCj4bN(SM**Z%5*{bqW&MLJB=wx= zz)_~ZSRqkLk@~<)^^sNZLZ&@9pfW5xQ40-&JWQVYX4Wm*@LOeJYba*L z{+_NvCaNG)Pz_=Q<%8<$DdL7I;sqH12dSoLx;!5#P7PhsT0ibo2HTbCf-MY^YHnrX z=^T*^W>C#_6=+sY15zf#*_!~-WYosE6CzNoLzoylS>XY|Y- zhk*#uDc{t60%6iVz#}pMUwTuQWLO9I*`Mz^fr5n1$jV1oZ?UhCNt~c;7s@sTGd*~V z5{2H|(W5e=N+O%Paz{gA9)E12YhQ*nH_{UwnKoSgSnQTP*Naa9-`8!8WEaS-l|s~5 zXJ4i-kvVQ_`pUGQOnHn0psL<0e_{5F;Q$kRX6yofx0CFXQ12W2=sbO-XJJsd?I_g_ zdueWCdx!Q}4QRqourAxwEei&?WV=pKAPk@*kw4HvcCv<9UN^% zFWzWv71?<8+~QqB7?YyiFq2KuO!nk@Oi!V4%>^4EY;2i+v;|vAXNlFypT9SeYX^!p z{#+*0tX)bdFxJPm?g7liyg{_U?v#G`PIH1>+Qvd(=-fbm$?RmZVl8FgzQob~ff!hGT2l9k_2loNYlmJlL1kvcMu%{W?E%fzk5)Fd{ zq(PQ;I}*KpIP@}&*vTi4Gl{d4P+-}BGnuvyq)(Xdrf9xx)i=R_vO?UfM%I)NjtTnY z#iGXNttGlb7cz#JfMXr{Ffzk|ej{O1MQO%VCYS5a;J57n8w?pDz-qFf3)bHccHW-o z$q0%O>f0`#1C62wmgdWlo;_czM;&KB+lgX}fujs}OVCc_vu&pZ;X+?Fe@W{6(I~T*Ca*zkI2V4oobNTZrEZT)?1Y>(=KhK)cN zcaO~x4~7Ib65+AI5fFsoX$x9gzDtFlYF#GUNiMx+?q_JgD8VS(+avB|i{jw+>45za z-HH*A(kz@4uMwo@5S;-FE#Y!Jw z$%v@|^vuaZhYoAzX}%`yp?HqjtmY-)Br6k1v1? z6`9nbdl4apS_}cjSm_e{2O*uu(^W=fL5vxQNZP0LmPk-(PBk^%*^UV3iHOlcv`YU1 z+Xx(s^|;>KtwFZz%6qQ?9RRbCIvAA3MdT?5e1V&g3rO_z^;jWB(q!Xl>M)i+Il{-S z>@df-7P!BpH!b9{5~>VTL}m0BaT3@BGj0i+B#^wdOJ z0>sAKX#F8K8>EgWVEipSqoHUDs0u`9-UI&PL=YX_S;Y5yL5jQ42HD%PO@loH+Cmw` zp30U$1}cmGq?k-j4Nny(rpC^R=dc>ARXKH+l^m0w28iYk5EJV!9yNL9h8;(0mLk~l z6tgxPoFSA^w(+e1MRxPD{vWFwHfQJ|ImREyHJ6_Dm7eyOo>(=ERF#`cPprpAafb|e z@Cu;Sl)*3wcTC+p>lkbb&SYSJ*3mF`%{;Sr(pa=%f*6pdN(9u1q*|!m4w`6-hAj0U z((drZ4P@FxnRW+dMR|h%0+mgzMYBgyo4g27Oa(GlW~zf4&v)dpr=c;x2<9cn$OTI8bPE(s-smn3409c-i2mlWfek`rgy zWG%JzBpQ_zu_g`C?qYj|lQz>a_;IqewPla>t1D14^+q~OImwsHRr%Q2XPa>7^<@(VYbfu!2OH zu6O?4;^YLoAlYy?&bosTx{=}Q2Iqy-8oOp+26Bw*Ix@$5I&VjZ3~Z3GNS!fWIw!3K zwRU`Yl6v-+5rJz>FzasiV57TJ(`0dC7~2R62l$!^b+u=(yEH{5mc$lvR_?=Y%n0g~ z59$XGC4p-ekG|^&Ly567Odkqz&`0OQV?NQ*f~pi%DKd%lC7w!J4bV~p3;H^Zzfl86 z!c4LnA8WnARG7n3gCi{0*aY;_*?0o99z+i^t|KroF)>8+7{t631g5!da6s746Mbxw z5)I+?h3c9imrx1vUj~-&3ZzAW4Yi)cwv&Ddb5pmJhP|c4>ESye%i$@b@SMb=2@IAe z`%e~5ib|xhq6mk0vA-C}dDK{%aom}1-Ke2Nj0v}M>2Z#&;e0N|?icg!K@AihO2?+U z0BC#EAVKUzPJbD+Aymjje{$9_&q*2h? zwEt%2ZvpoR7NAj2qCa!IO@G?;hb>-I0AD(N^6~~i-Gz7vQI*luzA$V1-~$o3n&-fU z@3|B^2QJn>OR;n8KkPzb1K2=D711H-TWq~tFb*4X%;7a{rW`c$M5Ta_zY_B{5j_LI zf!%7^W2)9_HS!i~kCmKQ#!@6E^hAFl=oK+!n~gQXjf#PgB9|7JB7p&_fZ=!snq^NK z9<>Chv~)xk7`>B@BGa~Tx)0=yaM?IGiDvT%AA_}}`T|;)mMv;gFm~!q9pg=iQqpaiQGPKzy4IDHP8R;A0W=Z0K zk>NwFMj!yFQ|3^2ro9i&hXC!J6W7pywTelKv=_WhYr?#MnS-lfgEW=F-VSJS0VoQC zXhPceV2t#rS?j^@iTxw6Kdpb1jU_Owxsn1l?ADM8ZB-g{KvL^iL;nX5v}D#lrFa;2bx+$Hud}%mpzJNdes>6VKKR^{#zwx<`f`ONHV6pa~nee{6%B z^b&s=xLxW_XP(Ui!Dn*Nti66_yc_4bv^#PIjlw#;584be3{aGaWV$4Cr9;k`E@Hz6 z{**U>z*S{=CGZ@zpYEq;Qr4nY*^F*1uQ3ua<}rx4V3fpIf!RS#_HlNTQfr`9Szb0} zHe)tkmJP!_9u)g9Lqr4^mI)&d(Z2Yhl=VOyQ_6ENj$so^r<8Hpj*3V3rs&=r-H{8{ zNzFK>Joya~QK<^qHoQo|!HP~CzAG^K4omtH0mIW z&1q`jjo5P&{5dj2fo=pMEG=mp%(Su|3V3%2P#Qj%dJwBRY~h7@+TSonbm-^-tTR17 z7e~aP0?(o>F{t!)fiO`+7blKtSL-)}Kn4x_8~jPl_RJSVSek)=jeCn;=b62C%6Dyo zMZ0=!*sx+q9lagVui{0T&y~FgsQ{%gT@{d?MQ_PdSxu!%*dV7 zhGLHg3PN*XWyWTGt8|x$YP@%6qmSn>=7(IHVa`Rc@+yg zX)~n^b3@%XxA$w`+^F}>je6gq1nXS#NeBPGIpZ_(%y-^h<*w4iKis^qXC+<8hT^~wHyL5PJmRwSs~mBUT7tm=#^g|Ca^DvUg^7okykzV zzrw@-CJ}WDgry@6br^cIo)Y=I42|S`rQ!vgAzF7CDPFN;U<#)DHJa{M;*r!8#D|(ZZku4ygrIS?M0BlZIjJ3SQ0;WI&hj^&i@B9d5( zi)l3`+Q?aoY9?mfjLt|GIu6J!5On{Df8xBOZCky}L`MRcz%f=ERVu;{#HV#{Z(K5e_#fiybe8`eCk+UI2qcVu4Aj4EQ?^k;#MAaf}bV+bQP8Eq<<>_D3tMRl8h2jySrV+%Zey_(mKeL@Ig zg3eMJZ`{-1!HbG$O-O|Tsm6`Ub`WnxB6VePyaYE=tXYH<3WYfexTl5}tkTQq1gh}S z=1A^Iiw=tycw_>`25*Bw-mc zBfC)sGK!>`s_Hk7mAQ|)RmIffs%};Hj4XWSR@JTUV(K-ws`?@1DQ7;Iq^TaIN%ut*{XSdoK>Wh@*_P{3LZ4oJ zPknpuvmf97Ui;gxF<&*&vYj9_8aM%xz+Jq z6#Li+C$>+NT4co5oHZue8?!k|!A>)fRRL+D;9@PbydrNj*`$s@wVM~cZv@^4ko(hVNkda!#8KbaMAr>ZLM`#W%(U~MH)=VgmE!t}{wXiA$ z;INjXFXkVZQynF?6K&3L)C8NYzM#|d`@6gQdn^Ep)f`I_VsZ(dymw`u&4+bF#~$y9 zS?I<#bQxorOkkj-!s)lT|M{R#%rUTumfC)^&7cGzT4QA4qAZGq zUUSFZtC2JCYilj6pa3M%n{s+n)H%XmZ>8!E-vQOZ;$a$OdO zdTK9q*)*LgloER>*@W6BSxgu^SfWb}GlDHbLyK2t*Z|Q>Dosb$v@(kq+W8ff-%MQI zn7PnuF1q8g;v-Q8$U8pSkx#aQ1$I7JYhU3NzE9arG(muEm7iQK{N62)jSAX zVoO%UOG>695tR8NXIQ!IQly%n=YXP|F+@JqOf-^eqncLqS8P{nVGRx9`yFCw`T#+; zwt(nfs?v$cw@xGFdso-mVxU5N`)5%l$wY~+Iy#iJo;Snse7S=~fg~)ISFGq_Z#GCr zqmZJ6#Tj&@wXI&p+?Bck!FB7r7? zSgr@hW>h)DaEI)#iPE&Y7aOyjmBeE6$1z;Yu0^)Reh^_(*6_Vjo zHFoPM)ObwbNFxw(g~^NLq6^~#?9I|zHR{#3wozGjaI8-xytw->hBvynHJ_MAKj=_{ z7&^by!-Qb*xulnwMKLC6$lS`~1xxzjX=4(Vbv)=Zr&^RySRPKKb$Th;P~wykR6fhp zR`GT0LB@~tSH~9s7qLbqGznAK1Xz_e=wFQQq;D*_3`AIu(;Zqt>KECSb!oG$Ahr>a zjU09wt?Dt1V4Z1aeK?}43PTbO>%wH0mlsy4Xp!wouYo!?ENduKtvYxRW6nI$;!v$b z#*IiZqvaJS(`6j8rI9TOO0Su+`qWXo4UTVjXBVv!vXNqfFVp_sy~f|s5wGW2GPH*wcq zfj85!g+<0Zjd^1|VqkNHlLS_m7)2G0WJA_|IsPmXYA{x|qZoe{W49_dxn#L4`@LSN z&>PZj9oV%#hDID|;Mqjt)MatB0qTw51UryeG$2NYf}&h0P-eux2D^8eCP#0w1N8~) zteVLfaEDNEp;LTbT1v{<#%4ua!QyO&q2HZ4>WtoCi_c1>XRSsvw;N8E%;tmJVBTWX`i+-0aZqU)_Pj00{b|2Vdh zP3Tg{r6r&?3(IU-GEYS;k|PLW8>Mkf{PyN_a7PU0u&@TLHaAHT7^o9AXC%fM6)|xL zkC>=fi)p99ClxIfJt1yn*x5QU%P~QQ0Mvp`9-&oqKeFWx9kaU32(htb!(z z*=bcZRylry9x#j*clc0SRK7Nn5v`2ZuqpZq zQV!OA1!3_>%%Uo?>+Ag=BUN6_+P2oLR0azb^P-16Rra_^nnu?OpyEqaXIddr#&LKc z7TH)UGpmV6NFpj4!6nED&T!N+=p_#u;?$dyWJXWScNiQ;Efe=DM`RS^HDjIK{x>J8 z#M&9%259-BDDeJdgPRAXvNx_wP{`;qT9ic|L3FwmIO2vYDvM-+LFGuh6OwcuZC+tL=h1MI zYaDUaI2;7@MtCj?O!xoP9bD>~m}$Ldte@q91!3W&+(^#qtjf66TCZe@FMF!MO^IJ7 z5^SJ7V(eOBg*3IHLMcq6`50tU^fSfUBz?>XW^SHQHppATk&}#L3gV0i@gX16_H|`h zRNLw_USx`DW%9?&3hFC9jxlRpc~Wz?#md;iCorA*1fsGMA{Lg%7{KV**(JF(ikz7J zh{*JDXvB)GpO3&;-&U+*V`Y{jk&--PHOBghOPMcojiHC1>T-OT?H%Ul&vIzXA?Ls9 zcV~b9K*#SsbG$v|h)JE0cm6DHa$CCj1@#>J{i_=`HRKCPt;W=C;}$0`d!;#4m|EMa z4R%7tRU=zRH&~e3*6LF=n571}ePgZ7H#lh_&O&lho2BKwVEZxy%$dzrQGU~+Si2bpq?!>W zQWM8Ik1b=fKpxK_P;2LUp>^r!4A$BH7A$F0BEzOi_N?MHuTO8GfiIQ>i*|^YA%q`I zeyTytbW#yTQ7UKxfn-DszpB?Lieko`!zyQqiq_}qva7>=PVD7`huluHCr4r^h#52` z0TX4)kZv7<+1s^)IYOpShxg z$;*r<%RgO%v;4CBkn=@C?D^uai5!74r-uBZb}MZ{fZc#VFvf-8y?a-;HTsiN2*FVf(2EQ+PAwis{2$CRSNYPA>p zqPJO!E#YWu^?Zl@)uGXLrBLg3!{J(}q;eD;Sd7=ZI7lQv*gCus4rSzQt}i4xaO>_y zHnYG{{C3+!2hp#?*yoclmI_bW>^P&tcHT^4Sd%vms?)?Q9-lNDPIK|BW-4;7M6_=g z!EW#IUv%mb-4>^mtg*INE0lXoM|7v8WwaZ`7yMe-gLEudJJYd@1_>APl_%yyb-1R%YG66bplx&(kc?9`JmKA$w2G7& zLDuI~L{ca6K9jGKcbSTyi?zHcWlA{jtUQqYmqfls40t}CTD9Un8hxiQj)CKBl{6toK=Zhw59## z{$^RE!7Ror2!~=v(5>p$YSM-jG>j0XG7-UTC!Q5+yinP!d)Q0!6x!?Uy;SQPRRNFI zsx3ruhN7Or{u$G+*&;%PoOK3USzVc1sG=zj-eS$r@R+M>xHjq-jd&{@$D#V@5RUR2 z&|hz2$mV>KDg<3ff?&h*ICr}`hr4KfC1)XTzRlvKvNS$Ad*_eTT~+kT)U1(%5qQLS zT4p7pCScCj@}(~4?pT+x3DQiB1aDIfni(h}{lbwJB5FbnY=#I9pD=+`?cK_^tnaoY zIsvWMh^iq3rWm1rr;WHgeOjidsVFo3rV^1>pUf`QM1~`2e2YMD(V_|slo2)JC?ira zEdc~6)dkuUQz(=9C)k)>Ff6qZD{{FB7C|wqRK}asu96p@jFM#9XipFtQmb#-%V~Y* zmo*m=6k%GuN<=DXDiLRr22~=?CK1%C?7XyBD-o$AtVGn>QD();U{irI;F97@##a?I zhE$IGYM#A)C4$i)Fl(wkdhNOS#YHLp_WW{^($I?TEx)BRFV+}c{VS7!-)h1Tnj*JM zn_{*MP0>o>=W_}dWg$kByd6t-5Nl%-u)WYFJ?n!RBrYIgHA+MDhj$aS%CN0sRmESZ z5w?lDD{HB$qYaZawiDKB3WD*COO0x4WJJ~Y!P7-4!&$O!{#3scD~|ncE~HOu2vVl+ z#O$8YIGafQ<9uB2VGphMrH9t~lCtmIW1|UD4%aOF7-8W?jCnOHb(3DJno<~Q)_S{` zt3uG{OzF7hHiJGvvKR<=Hje)C6HMg9mYDCkIg!LmW>+O4xR)5Jqu4uDH!m4ULXj}G zhR*VABqh=T_2!TxmAErTM-!wN4fIg2Q`rtmJzpc~N;}4M2l1DRc8-Y`Gu2H!_I3$d zcnQj)jlrrqz|2cCRUB(N-KPA2f+Zhs-S#mRgyoNyyVODGgE|Bc^+`pu2=#hNAsrFM{FkOQSa5Ef{pN^(q~*;CttdqVF;t9 z5(NZZsI$|u^%?}LA-KrZNO%SszUu4Y&9?P}51CuiDIPmIRx`-lI*KnAy>}b3Id3dQ zaT=ee#(JPRH|vDodm%-g zStV6btby|Ef+i%(?|q2O=rN3%ZcE{!ICpHPU$^GZjt(6z6cwuVei>2g{W2nL0_4x& z5029xCmOl7_#a{;1(I6^9f@^D@;Gwj6+M_r)b`;81|Px3s*> zieVaO_rbBV-+TfoF`4?1L2#c?{bKU`$Ei7 zSE<{jYTZoFRVjNJaZod%%t@qFu0X2eZYpu6#{UGFmm+7GMOBHykM)si#p{_Ma>fl7 zcKp;Fb!TgN(pwllcQz766QtUn`kt*(T}7tWNT3w9HQ821q!OyC^v(ZecuduVdD2|W z6|+bQE~wz8I*#SntRmOzd}l;Z#aaRlz0i;?6uYX$B`Fnx!PQt1d_l*i`iyd?G+Hdb zlO_zZ0{P4=eG(_LzQL}v)TJpajoU(zDoe%k+%h*2g8MSv)m#%PlpqT|DS`@>7U>w9 zhWK-;Fp?n7b|haHa-8+Ty(FBk&`~w)rTjWJL6ga!H61isl@b~x$;kFd&MVQ$a24h@ zL0ZMVQPOxpF_{;FqKde>r`szTj0K@UEa^k9UW2(BLS#Zo(7LRgq2i$l2{NF_x>K7V zEY*ta4i?eHLnI2h0_BAOAbOH_^U z%&40-l?~KaLj)h)jHe}8F1L+0r@QTZNvbZRg$hFPDYuoODR-5jsl8Z+rWRuvn%azI zXlgZahR4!D0VU_g~nB#X85m zB!PkhwVEvn7aib@uh9W?cd;fMDG)j+3dA_rI6h?mT69BIdC{!93f+<=3ZWwRtRJhR zM^arHC8v@aO6qpGRnx|f6(iQN>1MD-TRs&oZyZ(2;9Udg+masW_EpSPbD!b(TrVH- z+a$p$`H7F}E*13y^O3cF2m|D5VW#lMwWku{)(z|`e~geJGF-&A97S*0;u5_T^vTfn zp-_rG6BaQds@)nmesoaFDMG1UucW(egb!xa9-p7AD{Y9#H9^@3f-q|#NHc4T zxvJ68jrswBR_h0Mw~S1mQeBOsN1IiNNZG9tQEOnCRR^boo#(sD^<1nbuuYFEgR9%D zv>JB(LXU6roh^BuZnhdUp19bRn6SR91Y;v))<_aYL?)e3fbBzw)mQVrb|u+CyTyf>4h zK~tka)1yIWlAr_6Y$MGqhNZd1ur#|EcIFG)7hojz$05DoOIk`iRhkxBo3<oXQT?^xD>rOxm+(6U5#dfZOxSb_P(x5^Ao$dea_YbZNrHK@@?Bz z-;I3BibU>BYOmnF!XKd1!$@iCapsrVbIl~4O4g+~qvc9rWy=1#-9Fgmlo8H*vKN&W z#HV_l<@TsOUzet=XrD^7UlQ`S7r`9}{LNit{GPX8-3HlSxoE$aiUw}!63FiE9_P_j zYC6dngToHW4z`N~hTN$%~$&ugV_b=ba( zN$_VUMf<0*DJ8w5xpb3!rN+!ddapqwBQ540BNkfX^r?IjI-1il*_UXQ64OvOxTVD4 z_MWxcvLNr#Y#1V{)tapd<~QnjA;cG4$Nnv=^+8udnxybQ+Itm2#?;tT1V1^1~oW zD4z*H4+FDnI&?=5% z4mBbQX=`jBLN8WZ9zriwLSv6q+ZIEsZHuARR>aV1E2hqlBl?)O+KL!jt#1q+TVHzq z&(f6RrX-VNkH$YR8Ach26^*P*< z7U$)jGt`@pY(nTufW-xENaP zxENZ)@7T6Yh0tm%VraD$F|^u>7+P&b46U{zhE`hTqY`nV=w$hg78!772@zj3W5^bBEfcz_5#Lgv=>9i_Ir)?V%jRkVrUg( zF?5{GA!9$K$bf}f&0=V^W-+u{hZtI|Lkz_kyUaZxX_1p>#xg+&tri*6R>>!ZR*Q_G z)y|Kh)y|KhH4+|Mv#GH)i=ow;#n2jxLJrmX#24!B=I{k*wDq>=u zV-ZuQ$&f>pKtf|{rNz){X)$zsX=AyCb*o%B+cJ!p<0`wnFopRvMrCn<0Q(sm-8pXA z^?{fV=`{k-u&mb2E*GgcN5_nHEiBH%s$ zDbAiL&YmgGo+-|rDbAiL&K|<6?BX~omqM+zVR9<^4JzbQcOX>JjVTjoE{sP>K11GP znyT4|F~K_RQ2yjI`MLZ;E-DWh%Ii2LJ;TImdx9H=J^?-a+6a@L(BJeKzjPVD<0zsv zvqokzqs;%y(zj#-D$)))0x*rvF3S6@{n^xG&H`$n6n3E zXm26Te$n0hjq2tX&CM@rieKgk`DKF(zf9-yEAP~bybmKdOtEAmD%D)Q>Qx^_hWtKr zz05i^B&r!6!Flf9L&^-jE?-mR74tR~b>R+x!$C?v^5ys`+#`L_W&?hd=k6@A(;}P( z^ZhLqaY#v~0HU8m*9eZb#5YHWT3L#I4o%uF&DIT$ky4)pe8mPEb48tB$WI>gXw9b#y;4l%S^hsod_uM$BFtr9^Dt=1uiR_hQ$t96K>|&TW#&+g|WVb5L)Zq5LzoOgw}dDgx2a1 zLdVyk&LCd1TAzm;YJ3|)$58^q%GxZEC$1wngpO@8bW`E1kald7>zozR)|wpVq-snR zLThyhp%=$+eRsCOS+L`V4jxksFc~G(hn1df9StFLY!&Kg2x+-ws+e)cM$&*9Td8K% zRq*FSY%bs%7g{Siq^E1;3gzFo!L_nltbLpWG(q&b42OK)FryD-mdJ6CZ$Z$Bb5@dchub(>j&5Z)t_^Uq5~E5_ zou}4zPXYmhz5e>v+gY<|9hd+3;y?%0(?W9=P3(io_0| zs&u$F_{?+doBtdhp4#!N^5Zrv%_1gv)s*(=+eT&Cj#*r zcQ}|*$3@$rGHLzfQVXQ4tCk{Bq#lwAF9g&Z&WtQs@iusx-r3*UqUw+;7bjgGY)+Pc z7JRFW8k}glOg-$5gQB>Wd*RGEWZso}6}beAGo*AvS>V=e?)>&7gdo2bU|?x5f% zR+Kt*`T9(uGR?tpv@+kjEsDzW=a)FnJv*?D%(ctbx-6-0kN_Mp9&p8qP%arCW?R=b zcm8x(%IFw&q6^lKx3X>4*51VTNB`_{QC)v~H^gY|TDCX1k?$Te<&kZ2&mz>tSTe8|-1&NRoExQX4i1j4alYf>M!tQtmF*w)cRVBdeQ+?nIlP{&%7fRQ z(e6PG4&z{Y&acnsd&_iA+pcW!g~v-eyR%H&>JhxunV;oUemmB4{npW7D%0<@{ho;x z9I}78k3X;cmR(`oM}j{r=Y;X)*1TshI1nPNx#ArTX;h_SyQpuO0fqa)*GX7X`7sqQ z5!5?gZ|!hZ7|Y;5GUrKxs=+453B`IEjt&RA{ex@!TzI}Y5RX*KF6y6=(NV4*;5f}( zZ9gPC>Ml7z*5y||4zwl>_Bg|`=r0v-!ADwz7wh5#P<|c{PvvCcm?U(+@$=_b<{u6> z9#tzK&awu}tFxlfYx{>Hoc!=$P-$O@l3M-TA6g6Kkj7&z21Y}cC4?R&^8-#^92^-X zT)P3K3qKdL^~Me~zSln*pn8sUvl+P>>b9^;3P5YQ6RO!ig5r0W#E6N*-`3>`4y_jx zX_m9ZQIWnZOsn+wH}-dmx`sx%L;fv0Oe1aOd-Rr*dV#Pr<3BKQ zQWjX{@wAq!Pj+XLnl+bu^$bm2msxSkfDTqK18Dz9SUAuAjcd5|J32RUw|~>R&!vM4 zu#!1By0*W$IZQG|%X2)E3o);J5*c!5AD~_1#|3P$gYipm=kO4BfWk8l%pE*vwJ}XcrZd?Lt>@B2|;Sg;l?mOI2x)bxP5gG38IiQ z)67612u-X@q7b@Ue8X9|Xr-9LKB{1AXa5FW3)AMuOq5}{QiLjSaJ;jV?`6ZAR$B3m zGh~r~ximzWA@RnrPst|4wl{B1E1&-6b(=o-`tM=Z9v@Oq1Casfn`*u}MstxNH!)I! z8~ejeNyVg@Rt4I5w0pp>Fz2OO1st8Rg|Pxo&BjZpJForWHM-XKLbaB=PqOd1Wtol7 z!TKR)z?5n}yjj#;GQ&&Q-rL$Qf$`Uge~pJx+95`M$(>N7!aRYlqhD;Oa%HXwj%BZ_(nSAnKM)!sr%_p#Nu zX>-x0a2h40;V;bG7U*%Ln{W>C2ee z=MK2G$t25Jv`7PYQ)XfTIs=DT>5ct_VI!ez?1u`m!D(NssMLc;!~Gp_@XRp>Qga^R z_5G(=U?Q6$MrOGg5zlbMG-n8-N;loazyRH00OS&h4W#)>tBWZwkyQ%|%Fq;9IP4IN zSWZC=+23AjunA*=;WeAg^C}z~syv-k4xu&+@LX(0zM`be9ubU!P_n<5JI zU^+qg=*%?i%th|zTjq@RD~-oz*vp)Y3qm8k<9*)M2Mi_V;@2~6u*#*ks|o5&uhG@V z3{R1m^g0)$%81eCuO!{};eJjV_BXf_*?b1!Om+@SpE~d992+!2tPpx*yF;tgTr!Tf zYZVQl5PFntL;)Y(6>ec#g^sBbsv@Bfsaf_CVJLgyj?K@%!RL*7R2_;WuzuyZ^e}!e z==pfhD4JnIu&H8OWxawCrg%|2C?p*(pJ;j;DR2X)PKHf;R=pwuIo>(q>w*l7Eec)h zr1A_KwYImmk^UvoIk}Z^G~u7os4aB%we73dB0;ANuz^@X-%EHV%%+^~r1`nKe+19%-%+m^-G6$m|@?L6dLw4ET_2a`^ zwX*G)us6nrZnDza`8ZIJ7 zYbU$Q@B-UWf~<0^xnJJUUb!r1qTkmUCGg;S+2X?fu6Cncd8EFEboO+97yV+xZG~-a zAI4yTCKjVe>u=slItc-fCt$s^Jv=-rI$lU)4{m;=|MY+p@*!K}qcDOjiUb4J+aLxm zvum+cTIFL$joI~XEgO@v1cS@OWZ`m~gqWQ{ShaaN@w+4?D_&|g2{S>8NW5MQdL-bD z7}@jO<}z|s#_a3JX(mq@>kYRLj<}9To-$E#i6X{A3Cp?qh8dNJm)tvCda=2IwzWNM z(V4ow*uUA8P)e%D_44>6ViiOz!|SxNf}H&D_`p=D5t7@$<-n^YCjL_}%o0f~;*qg| zM84T)ETOThVLgOPlN3aZL3gk-fGjrFtBI_4Hgq+D7ByKWrXgFaD+^He*u-N3qgfzd zpD|jQ3I4szmp{=5R|mN&Tg}1M7I-{5d`mUP#cQm3ymtXt!#*BL?^3;DuIjO(_1@t} zHpW*grFGH-3L_xj9qevk#~o(Ah1P=GowaxtmfzW%DTJ%TIN%EAw;RLRhtH+Ekvw<% zd)r$Q@1oN{Y*w>B1tKuR?$OPyWBtd=A^Qs|5TKH^p!ufc?#3pyzU)_=Vz}S*iVZBG z?C8K@H&%!Jy+g3klQ%JKdV5KC=~jZcpVY7784eD1ZmG4QvD`=MhhE=k503g9*H%%M ztQWM8*SdBmuW1k?IPEH5+b(>^KnnaWkT>^HncN0}PRMPFui<%TWv z%>3d^T8!G@myA_P;-V=|$xWJIX2lkxgKG>Vk#{4z^*L;ZOAhUls-x&i8wr9crQy&HMP$6E^K2M(uK7?#_9G?X!<->HVmk zS|FD`&Zu@*m;!UU%b4)tparFi{F<%b=R|nPIQN6Kbpnbpl#3AiThl(47IF@SN0d4R8p>Ej9gN}4{TtTPsSK=P zGhPP9>H|C7UViQE=?(3?(7af@TF0)Whmeq`X)J~&7XZ!ZXIT^D<%bL>x%{TpTA5}+ zPiGPD^SO!a3+QSt<5LUG-nYG;-mEZ6cY;IVO_&G-S+J}{|1tJK;~CSVJM z-Ntf->!X*_kIZ41)KxZU^kdM#!wo7*OOVetytA3*qC_;H+}SLO$5lq#m~ETM(4aD% zG=SC^`sQ}oq%`v)ld{_2v}i5YlVUB~W#q+G_J=!tTmdx25E<{p>K$qcK7nnOw~-&je3Q(J zWcU*0fGv6^jYFXo74Vt=b{ViT)5YbH!?9f6?DxI@#3V(qxhNw-Q;H%n zSBySB!+lJR-jljTp~X58;~0M1ww@%-$d)&>7FVX|%z3@-m!%o}eTM6`=IM`Be#rAm zw?q<(oq?NSz}jo(7Y+8RjBgqP42Eq!&nL>8lJHUImC5aP)wA9=MO!1K7;9L^Mu}V_4dZtk(`;weWJYLY%h~Yv$U&&vJ zk7{R@oa;!-b|n%08>2-CMw1-8@H*2Hq|t4p1l8YL z=is?!86NA&_TLcBn|#Ci{{E3k|KX#Wz*0+KseI$i8Air&MxQ8g~rn3HYSCWTvawYP5WEd*flyj zw7by}pEWui_!TUM!>ig&F1~G11lZ)DT~5xNpPfbfvc$~s>ZYWk{$C~H;9r&|tWHmb z_t{Wq9n83}YPAhlJ;VIVt#)Q(a5&txH?3aZ;mo+!wSn#sZ7rbpjna+}8c5Eb-{|0I za48^f0^_sXG!0+&ZuAc_U5z+(3382S-H_+lq#E;vU9LcFw!7Fh{LV1x#;mDT!>|x; z*0y6WTikN7(ww6$dM{YM)0eW1{=pI4j2l6|dh0h_D(&9v>dI`R6aT<6$MX@!OyIR4 zLmc-Q%WQj3E-rGJJBvZPR~8XG7{F$Sp&c*}SwI)^Xm+^#lOr-4{%ZQG<*&BCX8aXW zazCI|1I6c%47Vbj_J*D!#09_zFd+iPa|fm)+~az`OB*b@p~k!hO9jJbu$IhCtDOxlXOvb@Gh$<F@rpU(T80on38n6N&bt z)1lLxp50t+JKj2@t!NajFwCxG`|F!qE;F*FP7^0V*9qTVO@~_kYWr)(UmbtV`fDy= zKk6`-sayk#d=;PJ3cPw1S~?0XW{QgA7FhVMpM_-xf$f65S&ewG6Y{IrihLcXJLz-0 zdYeq3+5GMp8Y^*h{w&yM#HDY8u_mujTAo&Wi2gEjXf9CX(>ax7_g$R*(viJqXA0`FKz6LaO@ z2J3vmgoOO0i+UH#_It*D&)V-f`#o>J7wq?<{azBSE?H~fon{Ad;_n5uZV9zZJC~cL zpKik#?)l_aQJkHHfN~F-aSNMX{B4SGxyx1~hpC^qX^I-!n>yN?TH2d>+MAl%n*#@A z1)zHbPKRt=zXFGBr$e^WA=~MY?R3a?I%GQ?vPFsYk6C%LSCON}?d70HG+}h;>u8?d z4zu@=zg6Z;sLUBwF9-LO%>)$UMcCvr4Cg+)%WO3d8}>(}8aE*XsWz)S%K2t{vjq+H zus>Ui^hm>B&B%}D;t@0S7NxFc=2sWyG4%Wo%(~U(1$3Y^jnqmp1BJd(*+xtVu3n>w zPS)B{&UJZH#ue(O@BIxm)P-*|_jU8PSM4~E65Vcc1xs?ZtJ}kja+zD*$)2M1hUWp@$A7SlVj`g_rwvAIvTk3tyslN%WbcG;*hBZ|McStD8?h2XlTFk57jqpJRJ*uNDLVxzb%5aqjnkHxawL_v4_6>Xp3 zi)sYxjq3Qvk{+5}!W%|UTQ}f!FpIg_k;UA^V)hvGM_@DeT1GO4`eR##G8XewVzAaK zl1slR@fJ#PM7~A|h7?+DxlFy%6@B0^WsR6QN>R*p;^TfL+qA)Wu!(EaI*|K3G~Dko ztN3(R3#OU3B0eqqt(YAyL`VfCGWKvg%5KcNiVHQUEsT&D*3mZCM}uH}6a6t1#FI zf8ghW4;%Iy$6zL&8H<^Y;2lbF-2fbNcijLSaz{6KrZ)OeF$hwP9I;vLwdSpH@xQW) z`1kanC;SnH7c06mNn6Q5)GEFt&ENKSSG24#?!)sBU~3~%%&icB=nmFR(P6emEOc13 zG{V@>+-muuhJG^m`u4jH>KO)t1-(GIUf@D6P@xz2)(dp&1wQlw*?L{9s74JlTZ>$@ z=O!XbiZPVZNh9m!`3u*AJb!6pL7u(u;|W4 z!u-MfhYcwcS$~cuRgF5=JsUV;52ZuPxX46S>9%76n%Cdnd4Znks2xF#R3s(R?sFxNp znjb_o69xK-1wlp#MS2FZTWvFm5Q>v}K)qTax;-Md5s}@i!Uv*HH)h8fJ0y_(Wu)Bh z&FeV$iX6Q?PPN03Pgjj8SDVH5Pusd^OklNbVoO)7@1PwJ9eZ2rSZL9>p-~KeO|ttN zqhUeW>$gdq5K1eR*}*<5(rq9iHxhFM{7TojejI5*)GT>I6dX>aU41gJ`JJ70)R0WJr4H8+*{^&SZi@I@CU$Rm)wCWoG+r^p8;A1pwiBoEU>Jq# zs2WvsDTJbN)Tf|pw4=hV$E2AJJ0mz|;Y2~Iw7`bz?4 z>nXH{a{uTYloH4AQrnoeG-oOpKG-f&c;*m^7>_FgWVmRatO;8jGA$kTwO=^0*z0CY z0dDO;5=qT8(28bl+W$c)EMqHnnBQjiOw2CYe3I_1C>g>ZQSt|Sa0R+FW@8ye;ezm_ zh==fpxU;#?8K)l_z9co^V0!*?wd(SR6cR0DhivhDjoLL5b`Z`8f2fW~M`~~CBR0$3 zKIJf_uqukB8yY;wTVm~YqL%s2r4>?)_(FnV;&yAWKAUb^*h^e$ULAY29h&i1$6q@0 zh9q<2MG`Iyqv#gOu8hAv-`LV`&HgkVegpre* zf+_|)BTe?luKS({9ri z&Q%(PV4h?pjrJIZ4ow{zG+jdj`5^tx(7Zc^ z>k;Or&{aD%uQWgPoF#Qi%H!{hyV>}nhbBcv2yt{Pw~6^U?2;oA5$P$R+VF>L3Ga1(FKATfov0NBL2US`4XmqaHEgy@ zBQ+=KLUp>62o)vjuCfHjE8r$yW3mtCqF0rI`3iG>=%t}`E6##NMPiP!aaLVW;NsoT z&#Z}Aor!#C6FUV1t#%e>1GSnfRPz$vYli0FgL97rbYWv=e`{96tEg9#S!Blwi?95T zYX{j(b9DjdFx5x2VaDmD#+WR$SBS%$Q=t3;yk`A17rtLJvsjL+;2H4U8WQ*|91#47 z(sXb{L~M|JwuEzp6|uEPxN|h<>}b%%qAxXxA$1zOPL%7UB>%d6$GUu5`iHhqKfMAp z(-xRhuq5Lc_U$ajUzqRYN$+)NJyR z-kF+YK!tvQko4oUb>LCxbycY<`|6^ZAjNpFo!&r5B!Qe3BR zG%f=rGJ0p0rov~w<rgnPa`FM7&dC8#E%9@U@m+g zxVmu5FMzz_P!L3oIl&~1bj>X+EJ5UNV>B=Y&5RNF4GunOV>4^6PR@0IYyBadi=5p( z054&pv)g-8C72(VYHj%0GRbUOlqWWPl;I}(Vu6bAtCM_@EcUBqdu&@(z?%JDHrv6b zB(a5;w-%$HEcC0hPL<@7gK*hCa(wlgv9Z%>GJQmadn_<=dZE_)>(c!33z&+rjt$iO ztuYT{aS@HCvx8iW2GtnOD<=af!Uk{hpQ!PU^K!z_#%ShT!h>KwCV%0F5ENWK!LJnD zO2O|FoJzs#b1B34V?-iRCSSFTHk=S_Ok}I({;|#?I%1c*O(NNxH0IB0*JfwUI^?J= z*2#^rE8VK(qFzoB!u8;*=5=C>b!i!^ro z6yIk#QxRO1K2Xv`6rV~Q&x^k``BT_S&ey(1hd3s_p>7DfCRvP78ZIJT(kY~g!b8CZ z^&f|A6cq@--)=MA)}g6+3&%RbQ^N>HV^}kxp_8rfuv(=~m$44lI4CwX9$7oc5(}#? zMX1hKI7%0qQnKMFg&@6QDW-L&s#OcsGWDm?U=Zjm1NXy$WiiT<^!Gx=+$o#YcKv9t zCRQgJvE?te*9c-!zFu0NVA|4Nb15gWK1@PJBe7y0-p+pr#}F7bWA4%QO-=4$cea@? zaIpqcN~$5yB|KQ6XoKruqCz%Mr4ty6qqq`5Yt_bU>mx z17k+$VA+-$V)=U^$b$Mj5;g60rKXs&2$|sPgW62(_H;B{rAjD={nBkYrE61D^QY-?5pz#ekhcdiig6g*NQwVOh+m;VgPLTj9 z9wk?3W~S48k_d|@5G;cvV}nB5l|B&-q=;kOpc!pbTg-<$WNK@q_pMc9?4>>0 zzj-k`-rHsmH5-KE$uZp_t0CF`X&#SaGcV?nFCO(REjV>pA9s~$IqhKd(T&X2(j#95=>&W$4^ISIKV14oV`};I=>(7y?T=I;q9cOO+xP=b0x>(rel@0l5KsmQ|Sn z7wSi8=rjd~{pPkKzJd(cGIR`e@-j`uvGAc34|? z_%?K1RlL0!wrUprSR88<55Vv(y0j>%ukQmaF&Y|MoRN?wH7cm_OvsbQZCqpRlkGQ8 zz9~9cb7y5QuPucxWGI*f>%8UY$;dgZ!;HznO|JaJUt%g*3ZhkdtYKL%6J{2r3tf=q%1?4<#jbdhF&gKMCLHj9H+>z) zu+kpB^UIF8vh3qsxCIjYx-?(I(NlR%6*ozFoJm9WjE95vUq9N~xf+U#VYEv4NU^#$ zZdlyu+2Z*GZOrDoq%Jg)?0q*|LQ~1rjwT*H6E0OLn#$Te|Clu@zHTk+Fi=R4pDhB%d@mV%T=_}lC>MY+|Bz&DDGN4)k{6r8W*4XaKpw?3H|hnbvKSQ?S`=PQ-|J_ z(RX1M5TqB7MJhQBTk|@A16u-O+C%+@p?kT+YL2`d_x+*3mnveU8%BfYH+cGeF!Z?SFca0vak z9&hl?5F=%uE%2#CN~#YPcGZW@bl_a)xpF|s{;@2PY7-gX`YA9z=7+jE2%+$v%5L;&fvbc_-joVyV9O;GBtoFpHt|`(Ww9)=PNb4} zaWAVzI0cQhu#c18NTsBcU1#CSj8)YUp|dj#G|p)S4r-@)G~-SO5nJ58fJdz$O~*bB zD{9dW8z6#QGU~oEBUwYS-u_Z7ZU2c(j)8|0t5e-NqZBsIC(bO&;a)*7li8QKB~s zl+ZCj8zkMctkbOM2)SV-SoxEcK}mv^9e^WVMsc=Gqav!!Z{?~f(?X=&4i)ke!L?;b zdWcfmpvkHzZVTWSkBSRO5=oO6g|hz0bTi>)dsE}v1&ix0sZJ~a3G1|~&2le|%Uy0B zWS=-Ya3nK(^S%p~{cntcIdCECu+waAfgJFY<=QU??!$7>R%ddtwSeP*<+dF&9lAJ+ zds%O(V|jHK^=dudWuH0s^kGs+Vz7{sMmJ~MizUfTSXe z?1?D$Upcd&dY1tnAelipv(YXTG%vXF#ArF12Paurgz@@eH-#Pm~1b zz?A1&FvCdQlvF3S82uVmsd?;j!~e|$Vi)Tr`6g^ScBE(>GmJgoVIa&PE9-T7eD?%n zX>L+mUIFE0H5=NPWZ8)(m9=V0ts|=xdsm@*PA|ce18q|K73D0B6U+n!MI(e3RgT6A zWeKkIdp}pAj`8rd^qHv<5wtZe)c3~WWY<;u z4GXOqygneu8pLbbA<+us8nQ!td9jBxJ~q18o2#DlD-@JHGiLInI~nmQW#A%VPFh69I+J+@ zLF}$@As9J@bi{)zE%CE7gs_$eO13I>@aou~=!!)$vrLUSrDRCfZs|Cvmay$TQ=alt zk%&e&MZZb-=%h%WfQk*1Uy}?`u!+dtag;#|l%&gf{a(8fjC(9KpC>MoR8$c1tu zD~d~yI)M|do0_b4 zIXB60kEsO~;n=>xzHdMFnE+PnMj!rQr+-2+kT<8%9jrJ@Hmo@gSWl5`efd+ zm0C8hwK6k1-;)QESxT+yVHjXu{oB@$8-rCpwMlck)p_ZIB+`SZy5~t zT{dv2X`DETo3K<4Ymql}mIE%NVoBYdyKCBd+t<*PH_m8IJD{_%xv}cobxQ%@Hf`kZ zL!Y^_wFmTt^Kx0fyM7$A;#`s#TSt%Tosl>xa&kIX`FBigUHCaT(mxNQXpoM*z%RCf z`9aEd2mGbuC6n>%LB`*?DMma-I&^i!^tO(m!!r}I?iJ%gB`mn!2!h+af~#R{Il7c7 zE>()kL7D(TVPxb-D=@QK>A{o!tkIu>r)Nj-y>kL?ar!B#sv2^(`R++<<+8e5zp zJnpVdam@a9aI8xU5Msk@OGhP#6#zQlDXeb8UCRzxW@@`ki=b0=_toKN zGOoINGQ!4Iu)xP9;X_I4s(mtN{L7M{)og!vlbZ*^mc)2l?VYo=j&Ll8(I28OsNmbG zqBHiDuqDp1!xvq=QFgL?EgZ~s$7W4iH!DeVt)r98I?J>r@2>T9bdthb-k0iHZuYQ+ zRE3eGft6Rju%Mt4r-0pE^qVY3g!%C%h~eyg%dnl2=>bjXZ!$r8$68LAadO8b)~8BQ z@1Cj2vV(41+uqP^9SM@|T=2B@y0fbKFsuxdKz4-Ds9-t6QzFJ^k?P(%R|9aQF1g?)qSp!w65W?(gr|0i36&CLcNT zhUv-asYj+JUu)1KQ>O(_UYtIA`r&Xv!E3X|g)GbZgZ}zEIzWxVV&8F zU-6Q~m!7!q-Y+@%%84(V_=*z`Onl|UUzm7s;xC?j&BP-UBz+nGU*MU@?s@B}m%ZFz zg0k$MEIZ5V0R#9O_#%HdPTl{ulW#xq9rt|iM3HufxYrY>y!5;$eEX1t*@uB2;cveE z_LFZr@piuL-S^xtf9QWWl{LSJ@c5mQlk~RmzbEo!8h;|o9!}tgYj79%z9jz5z-c|- z0sKnh^fuG>rICbya)V|pEPZ8d=@Rxb*`8&3)O@$r?k z=ZoL*qVGES-6#Hf1xGKc*5xMfgX9z2{%+v=fn%9J27JoOy!YG5r~MqrifR82aVZ}D z9bQ-4`1Jv9oI3foiNz18JFU<4eu}uWyc?$;aGJV&->H{1zNm&ydztgg4P0s^l@S2iZm1$iLzBtRigmf{_w*jjj);Et=`{pN!`%#N~;M-qZ z=9--*OwR(1+T@+c!j0#C<(Dm!nE%g{=80;W;`@7Fk!2sYxYGsh{&K)wfp_9n-$;9> z`CHFN_;!`I%BH1Ppo?bc!lG>t^I@%iMSuQR#69BQfA7TVsgti)raT`YeD0+9Y;>APJV^Up!og0z<&hq-{$+rPW;9R%OJMzQ-6{2C^ynoq!HDHY7{gh zSo|Eni7xVu%(k@xrsxJKv!k@D6qOE3E5R@&P2Hyze1mABi@I6=j zb^s!yGZFI-{1eb zEc;6S?gaW1-KOaTKSsLeNQVfx<8vZI`1x~MuM?(?EFi!b9(n?yoG{L?5H*GLD0+Vm z^g3ajg1&o^i<%P|49WAJ0>0Pan}0pVQ&FCqKNMkEOTd3C!U%JJ?86hWx8LU#KanB8 zdCnFv!dOoMBS`i9XiQ(l$cYSLmOLj+;*|j>vM((G{yI@mmj|E7zN{Ai+VqJ?}~4m0sf#e*nZ);N@!wj5m7m5={!C==BmM_~C23-QKa#{Ny~bAlOk}@6 z`X2|DUn2cC z)Y88>iT__~@sb5;dgZ6FXUy+QAnZPH)E|o1*fYkzj`$w{UL_#n>-Um)rPo;0p9zy4 zp8!tt(^xdduae)Zfj>h)%7a^M)R`aY1vE4{|a{!C<_R{6jhH^=fH3T9X2e~p)8`Y%QHoCCf_ zKurIhBwqPz4DHWEc9HZy4EzxSV)|>rjEnheEFIJT71BQg%<$3DD?g2`{h2UX|90Sq z2#ERpSQ4-F8gKhEk$pe;{S@$z5}@>o*Ld5XiR@>IUj*JHAm;ZYNxaf)?CsA)_D@Lv z3&2rdDqiF77%$oUQs5605c7K=iC6ju6IlK8s|l=ljmiC)$o>ua{WIW{Urq}-_IP_V zK9BH=5LB-PPTTX2BwqPz%pTLfn)KfT{0IRNKN`Eo__M_SBVdi?V|%U@X0n(6Yyum9 z6lSx>Yiu9$TOhv|0h3)(p2qqyzEAv1fi?Dz<-IM5SN-3e!20uNq%7_6@;;KlivLJq zmV5js6Ik&dEX;I||4afa{sS^5>E-i?=|4sKW8j}8Af~?`A47~+dig*6naJ*ij{YX_O#)(l?mZo%Gw(0?JUrw? z_T{91HSl8u#QdK~;+4OAA-s4_WUnXvHvy;k`LQHk>E#Wf5pEyiC-jMaEyNvnDNMIl^fFw2ITSY8K0as5cp}*3w|X5N`D>rmw?|B zV3jAB7mt76eQ^nY3+WA>D9h`O*N;(-_VI@agCN&NQ`FZi(#|HHr^1D4+*rWXvz z>?cSsIJW<913w7-LE_{0f-QOY{$mOJ->W>}dy@1<@AiS0_dD+>znASU zIHvz!fIkjAk$f-MJ`d&nUIPC%=>@lw^bdbmnf~{Q7tE`u|6~&X?}!i_+pGRLo5a6D zwlVOtR7mZA82J6)otfu~3>_%UK5{w@Z8p3-ZqAULhxV@Z66c)@A> zToV76i5HyKe<6wACSLIAr2L&Een`CF^!tM({;v`*IE{a}px+bOcM~rdla2PBu(1a= z>1ohqu<-e{N%|ipz2KN$@e4`(2Z$H^aQOaLfRBJtOGSSC8J>ykw}>}?C>c)R)lh!X zUy7xZY3yUL#lO_zqrWxFUXuMG@q%S?OaSZq`+t-_?YTeuH1UGH{r6k^JCpcRjEw}R z@sB0(4-qdojc+IM7l;>}#?K}3-$=aRG=3q8|0d!Er|}<5;tz-yoW_4BiT`%u1*h@9 zn#BJg@q*L%4=3?IMZDlN{{Htx{JlK;0P%u7{^f?hEQx=Pc)^wUB>#V*_*(wYCh?yn zUT|9eQ%U>@#*%{5_{}8#D~K1I#$QX~Uq`&)G=3+E|1XIboW@80y1Z09;styBsjLtD zNu(*GRr zv%ng1s62iD?&SM_K)hg=FCPEiB>q>47o5ibSQ7tR#0z$P=imQQ692ywFZhE=`8PEf zvWFTm))t)R|7;R}ig>}3q>uIg`6OOrd%-RrLitJj2UR|Bn*Rrr_({GOd^*Yh<4OEQ z;sv|B^87!U#Lp8iIPIS}KO--z@cq>5`LSmrdy@2mogOB#tH7JUvHoub{$}7d>0^8U z{%QZ(LugL|{|(Z|C(eIp&dZ;P?8nE%YpyHC|J<1P-$~+QO1+i8-rsUfzj}NieHV6Y z+{MRTdJrXiq4^6f<0HmK{5|#l7~=T53x96-h^Zq!SAH>uI6m*f zcg9DIjre=_2V#ih?=E~7AC7_X^boNV>E{_uM%m-(@4}y7eAMy%`md_ye;2+pKI-^8 zeoZy~UHEguM;)IZVnWCt=l?(Na2-Ey)}k|e96xvAJL98{zrVCvO@9~u-0)Gy=XbrU z`u(4GxQ?Gset#7|cj3GEa2j#>eU~1p^ib!YbAM8ezYE{RN6J6{U+JMvZ(sT<&35T= z{=5r+ZuoHAmGd!;udIH57ru)RrxE9`&y^nP^!0ULUB%~J_%1$D`ug)u4|RT-pQ_Tw zUHC3OQhvEh5C8wBhq^rY-fyh7_b&W}#Yeq=-oIR}&t3RGZG6=G@9LA)`rd{AZ1GX= zkBPTd%fAcX#fQ^~k4OJgr-wQ{Kl^}IYwPj)--W-h`0&0c{a?qguGZ%+d>0>1BhIgP z>ESLt{8`dNT|Vu9Ulsp%;k)=q>G3W-+?gKg{Pg!eT1|f!zKf5PpYGDbU3$0^J*4vF zAF=X)W0U=)O8=PzzE1iH@SCR3YWRLx0>6v&uc)QJ zKZ#fV4<_*6CjD2{(w|P^mHzb!{2b}0YUwAFc%}dP1pa-}H)`o0OX8J&A%Q1Oah_c* zeK(0$`Zp)=Ye^r^Gq|7g40Kl5Z-o8l_k*M_|`9Xv4J?-%G zFZ^^R{`nVvQE)-e&%f|t;I#bz6FBat7ybWR;P(W1b3eQKf44Ym%<*xOgAUT~AM~@< z3j97Mxaf~B&fetls-EF<-{Av?U!46wE&gYL)BOLT$3NxiPiDVX`~Fk4?@#K8*!LOcsB=z5+l0!Ue$}bdFK_rpFiUxdt59U#LI+DsWoA_j!6%&*wUt65L=k@to;CSBl{haSG2mEY7PtU*bS8C~R2>zL}|Go|QgP{PG z|A&U(GX7n}M|(v0`)_Lb{j}hsyq9OcT#28^eiJz5_dftW3g`KVUp`ey&k5vymSCWF z=&?9k(A)cP4ZZ*z_g@KLU5^j){bkuI@-_43SpW4szM$842rl^jRQBHqewP0{!pDzP z(xaaoF5;i7z!Ta3R)L>?;ok}_@bkslDHLklFQNMWw>s#@P6P4sUPpY{pU=P027c=O zRvd>?y&}6Jh3v<1Qok2xyAD64K+*HJIV{lX|Gk0}dHF-Y7mNCw%HCf~|0}@19_%I2 z|F2nmDKGyIPha%U%Q$Ex{}cz=>Ofd_@A!8C$fJG{1_QN z3(d;Dc+TUki2FI1^>+kcG|=$z`@khW@5`PCF6o)W=#bZOzp3#1<-nype@XVANuDSC z@pTpXej;0T__RtCe{59ZpMT-6)!^^1!M_L`*Wal8U#`V}%;7-K&%f|*fKz^YDT+A7 z|9@VbWvTkymz@XxU{U{xtnKkn#rj@$xZsDq%J(a=5UE zUT*wt$*q204IKA>2!EF<@h7s!f#d#p#rJ_z{Qk8{`sZKxu^Rjfz;S<@zW<2F7yR}| z4j1+Nj}903f5ofmtuSA%@4pH-&Q}P&0L&BUIbXydAL$Gg7Icd!GldM zuH)v*ot>;b*y7tsib*e`Jzt z?e3g{3$t%=b?9zue>mXo){Upv4!ELvkgXqb&moug9qw-(*@eNIcG2|CK9@uu-pCWk zOX!7kb{}-Mv^ZbX+T&LSSM7?@uHO$B?z9^l7ccf5=G*%R``i$Iz`f(#Sh%;feUecOyrwh~^ zAFgk48|&oOHh14%3$zsirz(N{&FlR=?p)mFR>7O2R-TbBntNxA#0r1g;La zp&5FBa<})c?>{}rHy|0q>Cte1C!;IQvm_3t*f`A;PJ8Q(a|)jy?6By$n}s* zTlWv(!S$>AWy#yq8!m||Nyc1cT8XdUZCQ!5?lWnn4zEPnJ)~o9ey$`My^}PJeuQTB zX@!vlSKvY!$i18WjiVSN9ME2oQb-hIOzzrE_Xj3+q0<=U{Cqs@>pt*6UPrB`k$pThK^AE;oxBBmhK1^Wgj2LYB;x{2?oRAG4j63g;4$R?w|-% zLy!80Pv?W1M~@tEaVcnt1h6?cLIUR->sditP?atnB{jTKgdXai-2_r?;73GF8S31& zwPE<6W=3koH-lmSaFDM{T9===b`w%E`);^-%PF+@4E=!YA-DbEVfkIPAGjL6AJAWZ zXOcJel%;Uo4~~wLmK2<{5jd&LV5^d)*VL*Xd!c{4;aAI+^;+-mJ)Ixk=qDwRu{AxB zJCW>6(xtfXZ)^;Za5oT``!{mQuA(|YybY;+Zmn70-#@CW!7T3|97Lg+{0*TW?;T~i z-BhenA;gVMeg=mdP@_Pk!N$?eEH}2abhIsin}h4&uV>BoVoaF<#5;DwRkK{OUIZO%9o|5?`+ddSLJVW=4G#N>Uje zQW@<(*tVu*rf4ny;;&Tm9USjKayPa&kFGt!rR!X$YiZ#n^z-f^d~j%HM1F*RJ4~7u z{v2LYwp4Tsxf#vw<`Rq>TUWE)Jjz(=iUGt&yZ!Awu{!jAHNQ51CdjC`{To2m%5Z-- z7ttIJkV1ovv7y3Vk@f&tHrSXP4HCj@sisGR&Wr@@jOMj7n%B-~UOQ=Co5y`{oz`@J z>oCn3aH`hA5R`s&us+(p7?xHlhNZQNVQIA>qO8@svf7$^)#-KT^Y+Z;d2XSfvbwA+FXl5w z6KR%{vE<$U%`!i$lH+|t)`u!Y&QHvDX<%!4sohw4GVd)cujccMjoFzjEsbm9xz>DP zW@&bHE^9Yd8+m7;(VL4QISML-EcIG>Z?&)iF7JsZ?EmzP%?&4roJFD^E+H;Nd%7m~iQtUPons9u$H=KR+5bpHY+ zRp}%p1nbtBrFNQg?8z#v3)lHIw7FCE;Z^erY!9EIsOhP}=DBm{``)NtTR80jY#wdw z7N)t8bQRlP(!6zqkxw0U1y!jo*aHdgg?emJqg)KUu)T|64N<~wUPTeym^RoKRg6^0 zRSng*waP#ZJrT0Xh=lLtA^cU5Ji^}v2h=_d+?8us06km9$qT+ux>^D#t?*Q2b#G@W zWT>K(YQS5q1w~=oMZb7kofQHDQ?~U|tmT5l{`6|JGXxJ691gI_6g~qIlFQ0(&iNDg*#j>HP#5^X0;zi zbCD0H&aL+^PELvbYk252%C2llD$eg&lU=ALBGa)W>(5+V%5>xWxvj}Fm$DUej6~nu zd^>L~w`Zc@sHy_xQuYy=yuf~>Q{j-z2h$g(x27%*GUw&xmHF9u^}W@oN~1wxq~dxi zmL4sb-QE2?a^0A`aAD)pxl37hW%(OtTB{QLYb!`Hyk`pyiR_h`-ptD78Hqu9o&e~4 zTqMTC^A!y0y?&@%#(V&aA{^a!f)L`p8<+SBv z=$H#>=Jx8>`!wxu@~<_J=G8Q9tV4=zWeS-O=YNdT3aWqzcAc$%hvwY!& zTA@Wl((>wZ-my_7x{9K%ejJe}3aOZRJ%$k1&E&+zw7w(e5s9j!0}bd?ba2V5{JFQE z@P&GuVVTQ-3zKKp&z{*jQzqj3k%mVB64)bY*E95>&N3ogzvt zN;hpnZT*e)txHn_HM?L4Pvo7R7^CB;Ak;+tZ;D)bHcOOQGsfcdOrnSt zpZ4HnVrh`l4Vg^73xr3$apnwdncmpAaB1`6Me|d+`A_J@jdPQmXD^8NRJ%K9N;6l$ z_r}xF!l5MBd6J2dEQ;zTxKTWb#ZapG7&Rg)lBpAPXeo2OWAs&>J0byA5K&kpmBGiz zr>bO1=#!D+eBc}Fn2c9~SX-E1oL`-32MJQJB8^L$TeLCAfJ$BJ>gxY#?D}1!2%_*K zB6pWwt03n;Fy@jo#}x_z8v{lVw6HMj=6)FPE@AHuj9R1-1g(Q;A(}=j{|Fnw<~kb@ zYr(==3%~EpyuH~wSA3A$`SIDf$pSVY{nwL{BR}T4^_fGFTY9X=CGJv>k%b-Syoy%n;!XzSu^r*L)b_dGhxmS2FSXBC_E* zw#}}hh3cdj0zI4B7#@-hwtM&WMh06XN>Ai5vB4P8o?S=6m}( z7Ll7*iosYyTd;3oad>|ar-nr20OM?@GZ_pH#bKW@*r7EoZ*~>8f1sNbuqljb7lO5I zA&lm+dE9U@2q7Kr@?!Y+_RXE7X$HG+h=EQ$=&O?f4(?1Yrtea~>3!th;6TiRDBD0}E5?ySFo&~rlOpb*40j(m=7C=qkkj+% z^eH_D9$uA@tQ^5-IC6W4`|{Xh_-i-@8IBxh;y_}^#mf6M#=R`ZJqM0u;-7MmO3Hf@ z;oz*6mG^zXY3-83^?FIqxk9jtmE!|^Op`crA)CNi9D(Nk47cS^Icg>O`yOzbF1a=6 zFHR#o-*=0&euFB2PTuQI#6*@*M8h*NW^MFQ&T{aH}Ee_M|G?b<^V0qVMJ$?kx^P zzdBQ=c_Qu(e$eBTtHbD@z;QU45JMRTeclKD>TxYPlYQ2{#7EU2&tBE!TZ-=y5Wa_T n%$8yI#*uBkXvOKg%#F_ICQ*G#7 literal 0 HcmV?d00001 diff --git a/bootloaders/THINGPLUS_RA6M5/dfu.hex b/bootloaders/THINGPLUS_RA6M5/dfu.hex new file mode 100644 index 00000000..47049a1a --- /dev/null +++ b/bootloaders/THINGPLUS_RA6M5/dfu.hex @@ -0,0 +1,860 @@ +:1000000078AB0020A922000089030000FB02000059 +:10001000FB020000FB020000FB020000FB020000EC +:10002000000000000000000000000000FB020000D3 +:10003000FB02000000000000FB020000950500002C +:10004000BD12000005170000A5050000B305000063 +:10005000000000000000000000000000991F0000E8 +:100060003D1F00001D0A0000190B000000000000E9 +:100070000000000000000000000000000000000080 +:100080000000000000000000000000000000000070 +:100090000000000000000000000000000000000060 +:1000A0000000000000000000000000000000000050 +:1000B0000000000000000000000000000000000040 +:1000C0000000000000000000000000000000000030 +:1000D0000000000000000000000000000000000020 +:1000E0000000000000000000000000000000000010 +:1000F0000000000000000000000000000000000000 +:1001000000000000000000000000000000000000EF +:1001100000000000000000000000000000000000DF +:1001200000000000000000000000000000000000CF +:1001300000000000000000000000000000000000BF +:1001400000000000000000000000000000000000AF +:10015000000000000000000000000000000000009F +:10016000000000000000000000000000000000008F +:10017000000000000000000000000000000000007F +:10018000000000000000000000000000000000006F +:10019000000000000000000000000000000000005F +:1001A000000000000000000000000000000000004F +:1001B000000000000000000000000000000000003F +:1001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F +:1001D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F +:1001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F +:1001F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F +:100200000A4BCAB253F8300011F07F030BD00849F3 +:10021000D20901EB0211194491F878301BB1373340 +:1002200000EB430070476030704700BFE02E0000D5 +:10023000B805002070B50C4C5D08A042104623F0B4 +:10024000010404BF033002320C44A14207D16FF015 +:10025000010202FB05330BB10B78037070BD31F85E +:10026000026B1680F1E700BF00101140084B03EB52 +:10027000C000426853B2002B08DB012102F01F02CC +:1002800001FA02F203495B0941F82320704700BFDD +:10029000E02E000000E100E00A4B03EBC0004268E2 +:1002A00053B2002B0DDB012102F01F0201FA02F212 +:1002B0005B090549203341F82320BFF34F8FBFF37B +:1002C0006F8F7047E02E000000E100E038B5054672 +:1002D000FFF796FF044678B12846FFF7DDFF238835 +:1002E000284603F0030343F0020323800223238004 +:1002F000BDE83840FFF7BABF38BD00BE7047FFFF0A +:100300000123074AA2F80431B2F804319BB2002B52 +:10031000FAD10123A2F80031024A936013607047BA +:1003200000C0014000700040064B93F826101A6A86 +:10033000054BC2F3026253F82130D340034A1360E5 +:10034000704700BF00E001407C05002098050020B8 +:10035000A0F101000028FBD17047FFFF48434FF494 +:100360007A71074BA0FB01011B680649B1FBF3F151 +:10037000B0FBF1F0800801D0FFF7EABF704700BF83 +:100380009805002000CA9A3B034AB2F840319BB25C +:10039000A2F83031704700BF0060004010B5EFF3A5 +:1003A0001081012383F310880F4A32F810309BB27A +:1003B0002BB132F81030013B9BB222F8103032F8EA +:1003C00010309BB263B9094A094CB2F8FE3334F8D5 +:1003D00010009BB243F4254323EA0003A2F8FE3346 +:1003E00081F3108810BD00BF2889002000E0014083 +:1003F000782E000030B5EFF31084012383F31088CA +:100400000D4A32F810309BB263B90C490C4DB1F86B +:10041000FE3335F810509BB22B4343F425439BB277 +:10042000A1F8FE3332F8103001339BB222F81030BD +:1004300084F3108830BD00BF2889002000E001400F +:10044000782E00002DE9F84F044600274FF0010BED +:10045000414D23889F422AD3EFF31080012383F379 +:1004600010883E4B196819B93D4AD1704021D170AE +:100470001A6801321A6080F310880020394D2188F3 +:1004800082B291424AD8EFF31081012282F31088A0 +:100490001A6812B11A68013A1A601A681AB9304B10 +:1004A000DA708022DA7081F31088BDE8F88F4FF09F +:1004B0000008DFF8B4904FEAC70A636839F8022BE6 +:1004C00003EB0A018988914217D153F80A300BFADD +:1004D00008F603F0B853B3F1807FF6B295F8BB3459 +:1004E00012D1334209D10120FFF784FF95F8BB34C4 +:1004F0001E4385F8BB64FFF751FF08F10108B8F10E +:10050000030FDAD10137A4E73342F6D00120FFF719 +:1005100071FF95F8BB3423EA0606EAE7666882B203 +:1005200006EBC201898856F832600A0A16F4803F49 +:10053000C9B24FEA02120AD0571855F827C06FF314 +:10054000104C45F827C026F4803C45F827C00A44E3 +:1005500045F82260013092E700E001403089002038 +:10056000000D084000080840B02E0000EFF30380A3 +:10057000103840B27047FFFF054BC03053F82020C1 +:100580006FF3104243F8202053F82030704700BF2B +:1005900000600040024A136801331360704700BFD7 +:1005A000708B002008B5FFF7E1FFBDE80840FFF7BA +:1005B000E3BFFFF7F7BF0A4492B291424FEA40000F +:1005C00001D8824201DB121A92B2104670472DE91F +:1005D000F341B1F808C04C891FFA8CFCA4B2B1F801 +:1005E00004E0A44536BFC4EB4E05ACEB04056544FE +:1005F000ADB2AE450F461E4608D27546F4452CBF37 +:10060000ACEB0E040CEB0E04A4B24C813DB92C46AD +:10061000A846294614E0ACEB0E0C1FFA8CFCE6450C +:10062000F9D9A6452CD9D7F80080A44508EB0401D8 +:100630002AD8A5EB0E05AEEB04032C44A4B29DB260 +:10064000B54228BF35462B46CDE90002FFF7F2FD43 +:10065000DDE90002731B9BB243B19C4228BF1C46DC +:1006600041462346FFF7E6FD2544ADB279892A4687 +:10067000B88889B2FFF79FFF788102B0BDE8F081AA +:10068000A4EB0E04A4B2CCE74FF000084446D7E731 +:100690002DE9F341184C0746E5883DB90120257046 +:1006A0006570A570E57002B0BDE8F081B0F85E80BD +:1006B0002E4608F07F08454528BF46464EB1637A6E +:1006C000216813F0010F00F1140233460DD0FFF73B +:1006D0007EFF464538BF4FF40043A5EB06054FF0BB +:1006E000000038BF7B84E580DDE70191FFF7A2FDC4 +:1006F000019931442160ECE7B80500200C232DE975 +:10070000F347344E044603FB0163B3F806800D46FD +:10071000B8F1000F1AD131B101F1370234F81230BB +:100720005904FBD406E04FF0E023D3F8F03DD8079E +:1007300000D500BE0C21002301204D4372197355D2 +:1007400053709370D37002B0BDE8F0878BB243F45E +:1007500080620285A0F86430B0F86CA01FFA8AFAB3 +:10076000238D03F00F039D42FAD1638D9B04FCD5CA +:10077000D045474628BF57468FB14FF00C0909FBBB +:1007800005F906EB09035B7A56F8091013F0010F1F +:1007900004F118023B4614D02046FFF718FF5745D6 +:1007A0003CBF4FF40043638500232385208D10F068 +:1007B0000F00FBD10C2101FB0565A8EB0707EF80BB +:1007C000C1E720460191FFF735FD0199394446F80C +:1007D0000910E4E7B8050020074B1B78834206D9CF +:1007E000064B00EB40001B6803EBC000704714BFD2 +:1007F00000200348704700BFA00500209C05002092 +:100800001C2D0000CB6802490B610121184700BF75 +:10081000A40500200346034A10780BB1FFF726BD5C +:10082000FFF73ABD380500200222024B5A80002211 +:100830001A717047500700200022024B1A80FFF700 +:10084000F3BF00BF500700200020FFF7F5BFFFFFF8 +:100850008B7970B5012B12D1CB79022B0FD10023EC +:1008600018468D78CC79022C1AD1824209D84FF0E3 +:10087000E023D3F8F00D10F0010024D000BE0020DA +:1008800021E08C78AC42F2D1CE78DCB2A642EED137 +:100890000C780133214420448C7980B2012CE1D0C2 +:1008A0004B78212BE3D1084B8A7809301A70B1F8C4 +:1008B000053080B2402B06D94FF0E023D3F8F03D4D +:1008C000DB0700D500BE70BD50070020704710B593 +:1008D00001F1080400F00F02D3B2092ACCBF37336C +:1008E000303304F8013DA1424FEA1010F2D110BD9F +:1008F00008B50146FFF740FEBFF35F8F012201F00C +:100900001F039A404B099B0003F1604303F56143C9 +:10091000C3F880211A6008BD0122430900F01F00BE +:1009200002FA00F0044A203342F82300BFF34F8F4D +:10093000BFF36F8F704700BF00E100E010B4090102 +:1009400000F16044C9B204F5614484F8001303491E +:1009500041F820205DF8044BFFF7CABF348900201E +:1009600037B5C36B04460A466D468BB193E8030066 +:1009700085E803001A70226C18465A60A26B9047F3 +:10098000E36B1BB195E8030083E8030003B030BDBF +:100990002B46EFE74FF4964313B5019343680446A3 +:1009A0001A7842B193F91100FFF7A2FF636893F937 +:1009B0001300FFF79DFF4AF680230A4AA2F884300D +:1009C000B2F884309BB2802B02D1002002B010BD5F +:1009D000019B1BB1019B013B0193F1E74FF4FA70BE +:1009E000F4E700BF00E07F4037B5836B04460A465A +:1009F0006D468BB193E8030085E80300E16B1A7143 +:100A000019601846626B9047A36B1BB195E8030011 +:100A100083E8030003B030BD2B46EFE710B5FFF7C6 +:100A2000A5FDFFF7A9FDFFF7A1FD3A4B53F82030D4 +:100A30001A69117BC1F30000C9074FD493F82C1039 +:100A400093F82A408C4215D093F82D0020B102294A +:100A500002D15223D3720CE093F82810D17093F88E +:100A60002B20013A83F82B2093F82C20013283F8B5 +:100A70002C2010BD196A41B393F82D404CB95A6A25 +:100A800098690139805C013219625A621B69D87019 +:100A9000EFE793F831406CB1012983F8310004D1BC +:100AA00020211A699172FF20F0E790721A6A012AD8 +:100AB000F9D1F5E7507999695A6A88541A6A013A66 +:100AC0001A625A6A01325A62F0E793F82E1081B125 +:100AD0005221D172012283F83020CAE793F82D10F9 +:100AE00011B193F8311031B100211962012183F85D +:100AF0002F105423AEE7507999695A6A88541A6ABC +:100B000093F82E10013A1A625A6A01325A621A692F +:100B1000DDE700BF3489002010B5FFF727FD2D4B1E +:100B200053F820000269D37A6FF3C303D37290F8AD +:100B30002F2002F0FF0332B1F02201210369DA72A3 +:100B4000FFF752FF1BE090F82A1090F82C209142FA +:100B500029D0D2B901290CBF90F8283090F829305B +:100B600000210269D1720269D37090F82B30013BE9 +:100B700080F82B3090F82C30013380F82C30FFF7C0 +:100B8000F5FCBDE81040FFF7F7BC90F82D1001F020 +:100B9000FF0431B1022AE3D190F8293043F0010378 +:100BA000DEE72346DCE7026A002AE8D190F82D3020 +:100BB00090F83040002B14BF0221032103690CB1CF +:100BC000DA72BDE7F022DA720269937803F0CF039C +:100BD0009370B5E7348900200022084B1A719A7887 +:100BE000042A02D103229A707047072AFCD11A788E +:100BF00012F0040F14BF06220822F4E75007002069 +:100C000008B50378012B06D103490B881BB1FFF708 +:100C1000E3FF00230B8008BDDE88002073B5344B52 +:100C2000344CDD68A54209D11A6A3AB993F83020EC +:100C300022B90826304A5E60127B1A720022A54251 +:100C40008DF804008DF8051083F82E2031D1596BF2 +:100C500079B301A999610221D961197A012907D1D2 +:100C600083F829205A6883F82A10520083F8282034 +:100C70000022022183F82D2083F82F2083F83120D1 +:100C800083F8332083F82C205A62196293F82D20C0 +:100C900093F82A1083F82B1012B1012283F8312027 +:100CA000B4211A69917093F830204AB951221B6916 +:100CB000DA724FF47A710520FFF750FB02B070BD75 +:100CC000002283F8302093F82A201969012A0CBFEA +:100CD00093F8282093F82920CA7093F82B20013A22 +:100CE00083F82B2093F82C20013283F82C20E0E7A6 +:100CF000F88A0020433249534C050020030143EA9F +:100D0000801040F4847040F001007047002802DB3E +:100D1000014AFFF713BE70474C8B00202DE9F84FB6 +:100D2000404F804607EBD01393F827408B4614F0D2 +:100D3000010416464FEAD01A0BD04FF0E023D3F847 +:100D4000F03DD90703D400242046BDE8F88F00BE4B +:100D5000F9E7354A92F8009093F82720484642F088 +:100D6000010283F82720314B53F83950FFF794FAEA +:100D70000DB900BEFEE7B8F1000F3DD04FF484631B +:100D80002B842B8C9A06FCD5294B5A7A9E806FF3C4 +:100D900000025A72DE80002E3BD0C3F800B0B8F1DA +:100DA000000F32D0B5F86030180403D5B5F85430D0 +:100DB000190627D44FF0E023D3F8F03DDA0700D529 +:100DC00000BE4846FFF752FA002CBDD107EB0A03DC +:100DD00093F8272064F3000283F8272093F8272054 +:100DE00064F3820283F827204FF0E023D3F8F03D2C +:100DF000DB07A8D500BEA7E7A5F820802B8C9B06B3 +:100E0000FCD4C1E72846FFF743FC0124A5F8604065 +:100E1000D7E71E705E709E70DE7005230124A5F872 +:100E20006030CEE7DC07002038050020E02E00000F +:100E3000B805002030B5184DAB686D689C6E2D78F4 +:100E4000032D98BF013408B1A0421CD35B6BD207BD +:100E500054BF03F01F03C3F30443032D07D91B0939 +:100E600083F0010348B9A3B902234B6030BD03F0FE +:100E70000C031A1F53425341F4E7A04201D3002B45 +:100E8000F2D10323F1E7032D98BF00F1FF30086092 +:100E9000ECE7002CE8D0F4E74C8B0020F0B501F033 +:100EA0000307032F0C4685B007D02F4E01F00C022C +:100EB00073681B78062B02D122B905B0F0BD0AB1C8 +:100EC000032BFAD13268294B9A42F6D1B3685B6E94 +:100ED00001338342F1D34FF0FF32002302A9CDE961 +:100EE000022322460190FFF7A5FFB2680399156B14 +:100EF0000198B9B914F0080F0CBF0223042314F0B1 +:100F0000020F08BFDB19DDF808C00BBF123302EB7C +:100F1000830302EB8303C3F84CC00CBFC3F804C0C7 +:100F2000C3F850C0630642BF136C43F480031364DC +:100F3000012F15D025F44035022C45EA01450AD190 +:100F400019B1012202A9FFF775FF039B25F0407537 +:100F500045EA036501E0002FF7D1B3681D63ACE7F4 +:100F6000022CEDD0F1E700BF4C8B0020545047001D +:100F7000002210F0800F11460CBF80201046FFF7B2 +:100F8000CDBEFFFF10B40346064C006822465968E8 +:100F900003C20022C4E902225DF8044B1878FFF76F +:100FA000E7BF00BFA4050020F8B5038944899BB2C0 +:100FB000A4B28588A34236BFC4EB450CA3EB040C56 +:100FC0009C441FFA8CFC654506461ED80020074647 +:100FD00003460446944228BF14463D19AF422BD124 +:100FE000121B92B23AB1934228BF1346C2189042E4 +:100FF00027D123449CB231892246B08889B2FFF7B9 +:10100000DAFA3081F8BD5B1B9BB29D42FBD9A54249 +:101010000FD93068A34200EB030735BF0020EC1A5C +:10102000E31AA3EB0C0335BF9CB2A4B203469BB2F8 +:10103000D0E7641BA4B2EAE791F800C007F801CB3F +:10104000CCE70D7800F8015BD1E7FFFF70B50546EE +:101050000024134EE0B2FFF7BFFB38B94FF0E02396 +:10106000D3F8F03DDB0700D500BE70BD43682846CD +:10107000984701343278E3B29A42EBD23B22002106 +:10108000084801F0A4FD1022FF21074801F09FFD50 +:10109000BDE870401422FF21044801F098BD00BF54 +:1010A000A0050020DC070020DF070020EF0700205C +:1010B00070B50589038942899BB292B286889342B2 +:1010C00036BFC2EB46029B1A9B189BB29E42044657 +:1010D000ADB217D8C079C00914D170BD9B1B9BB2AB +:1010E000B342FBD2E2882068C2F30E0202FB030087 +:1010F00001F060FD01222946A088FFF75CFA2081FB +:101100000120EAE72B46EBE77FB543780446023B34 +:10111000032B12D8DFE803F00255151D00212A4BDE +:101120001A786FF300021A701A786FF341021A707E +:1011300059701A7861F382021A70244B214618689C +:1011400032E0214B1A78D50739D51A7842F00402DB +:10115000F2E71D4A1378D80731D513786FF382036D +:101160001370EAE7FFF738FB20B1436913B16168F8 +:101170002078984701353378E8B28342F2D2124A98 +:10118000137859071BD5137801A96FF382031370E5 +:101190000023CDE90133039323788DF80430052330 +:1011A0008DF80530094B18680430FFF781FF30B91E +:1011B0004FF0E023D3F8F03DDB0700D500BE04B0CC +:1011C00070BD0025024ED6E7DC070020180800207D +:1011D000A005002013B5124B9889D98993F90040D6 +:1011E000421A92B2402A28BF4022002C0EDA8842CE +:1011F00012D099680B48019201F0DCFC802009496B +:10120000019A02B0BDE81040FFF788BD88424FF058 +:10121000000003D10021F4E78020FBE70149F0E75B +:10122000A40500209C07002070B50446164D0068F8 +:101230002E460B466168AB6003C60021E981E18858 +:101240008A4228BF0A46AA81E18881B152B14BB9CE +:101250004FF0E022D2F8F02DD20701D4002070BD6B +:1012600000BEFBE7FFF7B6FF28B10120F7E72078C3 +:10127000FFF77EFEF8E74FF0E023D3F8F03DDB0701 +:10128000ECD500BEEBE700BFA405002007B58DF844 +:1012900000208DF801301A0A1B0C8DF80330002352 +:1012A0008DF802208DF80410062269468DF805306D +:1012B000FFF7BAFF03B05DF804FBFFFF2DE9F04F25 +:1012C00089B0FFF753F9FFF757F9A74BB3F8401070 +:1012D000CA4362F4784292B2A3F840200A048CB266 +:1012E0000CD5B3F8402012F0800FC2F3C0111A8859 +:1012F00014BF42F0100261F304121A8067040ED585 +:101300000025052305A8CDE9055507958DF815306D +:10131000FFF7FAFE944B1A8E65F34D321A86A60437 +:1013200011D5914E338E9D040DD50025032305A8BC +:10133000CDE9055507958DF81530FFF7E5FE338E9D +:1013400065F34D333386E00407D504F07003202B9A +:1013500000F0D7805ED8102B75D022052DD5E3077D +:1013600040F1EE80804BB3F84020170725D54FF4AD +:1013700080425A84B3F8542003A9ADF80C20B3F886 +:10138000562006A8ADF80E20B3F85820ADF810206E +:10139000B3F85A20ADF812204FF6F772A3F84020A8 +:1013A0000023CDE905330793062308228DF8153075 +:1013B00001F000FC05A8FFF7A7FE660515D5002281 +:1013C0006948B0F84A30A0F84A20DD070DD5FFF78C +:1013D0005FF950B14FF4E0608022644B9B88CDE907 +:1013E000050205A80793FFF78FFEE1050FD55E4BB9 +:1013F0005E4CDA8EB3F84660DFF880A1B6B21640D4 +:10140000F24392B2A3F84620002E40F0B98009B012 +:10141000BDE8F08F602B04D013D804F06003402B9C +:101420009BD10023CDE905330793042305A88DF84C +:101430001530FFF769FE4C4A138E43F400531386B0 +:101440008BE7702BECE70122474B5A87DA864FF483 +:1014500080425A8400221A851A8D12F00F02FBD1A5 +:101460009A859A8D12F00F02FBD1012394464FF416 +:1014700000774FF480763E4D3E493B481FFA83FE8D +:10148000A0F864E0A0F868C021F8137021F81320D8 +:1014900025F823600133062BF0D100254FF40072AC +:1014A0002846314E9FB2A6F86470A6F8680021F86D +:1014B000132021F8135001330A2BF3D19822002175 +:1014C0002A4801F084FB338903F00703013B9BB2F8 +:1014D000022B0DD8284ACDE90555D35C012207958A +:1014E0008DF815208DF8183005A8FFF70DFE34E7AC +:1014F0004FF0E023D3F8F03DD9077FF52EAF00BEC3 +:101500002BE7194BB3F8503013F07F023FF425AFAF +:1015100000230521CDE905338DF80C30ADF81030EE +:10152000ADF81230079306238DF80D10ADF80E209C +:1015300003A9082206A88DF8153001F03BFBD3E77C +:1015400014F007037FF439AF074A0721128CCDE965 +:10155000053312F0200F14BF802200228DF81510E1 +:101560008DF81820079325E700000940B8050020F2 +:101570008C0009406E000940162D0000140009403F +:1015800096FAA6F50C22B5FA85F502FB0542137A08 +:10159000DB091DD029465948FFF7B0F890B10C235C +:1015A00003FB05439A88197ADB8805A8D31A002221 +:1015B000CDE9052207228DF818108DF81520079324 +:1015C000FFF7A2FD012303FA05F526EA05061BE74E +:1015D0004A4B002D58D0B2F806B0AAB21A85A3F82B +:1015E0006420B3F86C901FFA89F91A8D02F00F028B +:1015F0009542FAD15A8D9204FCD55F8D0C23C7F326 +:101600000B074F4528BF4F46BB45D84628BFB846B5 +:101610006B43E058E218B8F1000F08D0537ADB07AB +:1016200023D5424636490190FFF7BEFC0198C145DB +:1016300088BF4FF48042314B88BF5A8500221A85FB +:101640001A8D1107FCD10C2303FB0542ABEB0801FB +:10165000C145D18001D8BB45B4D800226B43E11805 +:10166000E2544A708A70CA7098E70346234900EB37 +:101670000802934203D10C226A43A350D7E791F8A2 +:1016800018C003F801CBF4E7B3F85E905F8C09F063 +:101690007F09C7F30B074F4528BF4F46B4F806B084 +:1016A000BB45D84628BFB846B8F1000F07D0627ACC +:1016B0002068D20717D542465146FFF775FCC14551 +:1016C00082BF4FF480420D4B5A84ABEB0803C145F7 +:1016D000E38002D8BB453FF675AF002323706370EB +:1016E000A370E3705BE700EB0802904201D1206039 +:1016F000E5E7197D00F8011BF7E700BF000009408E +:1017000018000940FFF7DABD2DE9F04F87B0B14B63 +:1017100000201D682B689847A989EB8989B29BB284 +:101720002889994236BFC3EB4002CA1A521894B2B4 +:101730009CB1A04205D281422CBF091A09188BB274 +:10174000EB81984226D96A896968C2F30E0202FBCE +:10175000031103A801F02EFA0124E9892246288901 +:1017600089B2FEF728FF2B68E88101209847002CFA +:1017700000F09C839DF80D30013B072B00F2428363 +:10178000DFE813F00B00190040039F039F032300C1 +:101790001E03A2031B1A9BB2D3E79DF80C00FFF7B0 +:1017A00055FC142200218C4801F011FA9DF81020FC +:1017B0008A4B9A70ABE79DF80C00FFF747FC1422A8 +:1017C0000021854801F003FAA1E7844CDFF8088284 +:1017D00023789DF80C5043F00103237094F82730D0 +:1017E0006FF3000384F8273094F827306FF38203F7 +:1017F00084F8273094F828306FF3000384F82830F9 +:1018000094F828306FF3820384F828300023C8F856 +:1018100010309DF8103003F06002602A11D14FF0B3 +:10182000E023D3F8F03DD90700D500BE00219DF894 +:101830000C00FEF74BFD80219DF80C00FEF746FDE5 +:1018400065E7402A0DD1664B002BEFD001212846D9 +:1018500004AAC8F8103000E000BF00287FF457AF9A +:10186000E4E703F01F07012F00F0D481022F00F0FE +:10187000FA81002FD3D1202A0FD19DF814300F2BDD +:10188000D4D82344D878FEF7A7FF01460028CDD04E +:1018900004AA2846FEF7B6FFDFE7002ABFD19DF86D +:1018A0001130092BBBD801A252F823F0FF1B000016 +:1018B000ED1B00001F180000D91B00001F180000BE +:1018C000D5180000AB1A00001F180000EF18000028 +:1018D0000319000006AB13E903000023C8E9023333 +:1018E0002378C8E9000143F0020323700FE763780F +:1018F0008DF80A3001220DF10A0104A8FFF794FCCB +:1019000005E79DF8126063789E4200F0C980637815 +:10191000C3B12846FEF7C0FC4FF00C094FF00A0C8B +:101920004FF0010E4FF000082E4FBCF1010C21D1F9 +:101930002846FEF79BFC94F802802846FFF786FBBA +:1019400084F80280002E00F0AB804FF0010A23786B +:10195000DFF898B023F0300323709BF80130042B9C +:1019600046D04FF0E023D3F8F03DDA077FF557AFCC +:1019700000BE54E709FB0C731B7A002BD5D01A4A22 +:1019800003F07F0ADB0952F83520190107EB031336 +:10199000534493F87830D08E0EFA03FB80B220EADD +:1019A0000B00D0869BB103F1370002EB4000A0F89A +:1019B000008098B209FB037339448A44A2F864009A +:1019C000A2F8688083F808808AF87880ADE702F191 +:1019D0006000ECE718080020A4050020DC070020C8 +:1019E00000000000B8050020E02E0000652D00007A +:1019F0004FF00009B14BA3EB0B0297B25FFA89F8E5 +:101A00004046FEF7E9FE0028ABD083683A465946C7 +:101A10002846984708283AD9874238D300220CE054 +:101A20009BF802C00132634454FA83F393F803C075 +:101A3000BCF1FF0F95D183F80380D3B29A45EFD85C +:101A40005844584511D89E4B1B78434589D39B4B2E +:101A5000984225D243780B2B03BF037890F803A05C +:101A6000C0184FF0010A834677E79BF80130052B39 +:101A700009D19BF8022002F07F0304EB430303EB40 +:101A8000D21383F813809BF800309B44D9E78C4B2A +:101A900009F1010918785FFA89F39842AED260E73C +:101AA000667004A8FFF76EFA31E6BDF81200030A6B +:101AB0005A1EC0B20E2A3FF6B9AE01A151F822F06B +:101AC000FD1A0000211B00003F1B00002D18000024 +:101AD0002D180000C11B0000211B00002D18000064 +:101AE0002D1800002D1800002D1800002D180000E2 +:101AF0002D1800002D180000091B0000122271494A +:101B000004A8FFF791FBA8E66F4B002B3FF48EAEC5 +:101B100000E000BF014600283FF481AE4A88EFE7AD +:101B2000022B01D16949F9E7694B002B3FF47EAEE6 +:101B300000E000BF00283FF472AE0146EEE770B946 +:101B400002226449644801F035F801204000821CFB +:101B5000624942F440730B8002F0FE02D0E7052890 +:101B60003FF664AE5E4B5F4C53F820602378BBB900 +:101B70005D4D2146D5F89000FEF7A9FED5F89400FA +:101B800004F10801FEF7A3FED5F8980004F1100156 +:101B9000FEF79DFED5F89C0004F11801FEF797FEB4 +:101BA000304601F01CF800234C49C0B2DAB2904232 +:101BB00003F10103CAD9541CB25C21F81420F5E7E3 +:101BC0004A4B002B3FF432AE00E000BF0146002834 +:101BD0003FF42CAE027893E7BDF81230012B7FF46E +:101BE00025AE237843F0080323705AE7BDF812307E +:101BF000012B7FF41BAE23786FF3C303F4E7237844 +:101C0000C3F340129B0803F002031343ADF80A30FC +:101C1000022270E69DF814200F2A3FF607AE2244F8 +:101C2000D078FEF7D9FD014600283FF4FFAD2846E5 +:101C300004AAFEF7E7FD00287FF469AD9DF81020A7 +:101C400012F060027FF4F2AD9DF81110A1F10A00CC +:101C500001283FF6EBAD0A29C8F810207FF421AF28 +:101C60008DF80A2046E69DF814B00BF07F06092E89 +:101C70003FF6D5AD730004EB460606EBDB16F07CB1 +:101C80000093FEF7A9FD4FEADB1A81462AB100282E +:101C90003FF4CCAD014604AAFBE59DF8112002F00B +:101CA000FD00012824D0002A7FF4B9AD96F8272042 +:101CB000C2F34002ADF80A20AAE700BF802D000061 +:101CC000A0050020802D0000000000005C2D000019 +:101CD00000000000192D00005206002050060020D0 +:101CE000F02E0000B48A00200081000100000000F6 +:101CF000BDF81230002B3DD1774B012A06F12006AA +:101D00001F78F27948D1930734D559463846FEF703 +:101D100077FA0646F8B1714A384652F837200192F0 +:101D2000FEF7BAFA4FF48070019A3080BAF1000FD2 +:101D300002D0012232800BE06949594491F87810B1 +:101D4000A2F86410B2F86820C2F38132012AF0D1FF +:101D50003846FEF78BFA009B2344534493F8272020 +:101D60006FF3410283F8272093F827206FF30002D6 +:101D700083F82720B9F1000F3FF4C9AC4946284643 +:101D800004AAFEF73FFD0023C8F8103094F828306D +:101D9000D8073FF5BCAC84E69607EBD459463846E5 +:101DA000FEF794FA009B2344534493F8272042F013 +:101DB000020283F8272093F8272042F00102D7E798 +:101DC0009DF81010474B01F07F0403EB440303EB35 +:101DD000D11393F827004FEAD11C6FF3000083F86A +:101DE000270093F827006FF3820083F82700002C68 +:101DF00051D13D4C9DF80C502378059EBCEBD31F70 +:101E000018D046B14FF0E023D3F8F03DDB077FF563 +:101E10007EAC00BE7BE4354B1BB12146284600E07A +:101E200000BF2369002B3FF472AC032128462E4AE1 +:101E300098476CE494F90030002B07DBA068002879 +:101E40003FF465AC32462A4900F0B4FEA268E3894B +:101E500032443344A260E2889BB29A42E38101D0CB +:101E60003F2E15D8236933B92078FFF781F8002871 +:101E70007FF44DACC6E7022128461B4A984701462D +:101E80000028F1D12846FEF721FA80212846D5E422 +:101E9000FFF7A0F9EBE7D87CFEF79EFC48B94FF0BE +:101EA000E023D3F8F03DDA0700D500BE07B0BDE867 +:101EB000F08F0469059B9DF811209DF80C00A04748 +:101EC00025E4084B1B7822E4049B002B3FF41FAC55 +:101ED000059898471BE400BF38050020E02E00005D +:101EE000B8050020DC070020A40500200000000049 +:101EF0009C07002008B50D4C0D4E256832782368EC +:101F00005B1B632B0CD9BFF34F8F0A490A4BCA687E +:101F100002F4E0621343CB60BFF34F8F00BFFDE7D5 +:101F2000FF2AECD0FFF7F0FBE8E700BF708B002042 +:101F30003805002000ED00E00400FA0570B5FEF75A +:101F400015FB1349134B0A7C53F820600546100714 +:101F5000D1F88010D3B214D41A0614D4DB0614D5E9 +:101F600011F4405F14BF07240624304600F060FEE1 +:101F70002846FEF701FB21463046BDE87040FEF7DB +:101F8000EFBC0424F1E70524EFE70724EDE700BFE9 +:101F900000E07F403489002038B5FEF7E7FA1A4B9D +:101FA00053F82040FEF7E8FA94F83450012D0CD194 +:101FB000236BE3B100220421204600F019FE08B390 +:101FC0002046BDE8384000F033BE022D08D1256B15 +:101FD0006DB12046BDE838400022402100F018BE17 +:101FE0000A4B93F8D430012B0CBF0325022500F0D7 +:101FF00017FE002384F8343029462046BDE83840D7 +:10200000FEF7AEBC38BD00BF3489002000E07F4041 +:10201000094B0A481A880A4B03EA8213094A03F556 +:102020008033128852080263074AC0E90A2300235A +:1020300080F8343000F0E4BDDC080020E4880020A3 +:102040000080FFFFDE880020DE08002070B51378D6 +:102050000C4603F01F010129154640F0108113F0D2 +:1020600060031CD152780A2A0FD00B2A40F0078156 +:10207000012C40F0CE806A88824B5A70FEF7D4FB68 +:102080002846BDE87040FEF77DBF012C40F0C180BE +:1020900022467D492846BDE87040FFF7C5B8202B91 +:1020A00040F0ED805378062B00F2E980DFE803F082 +:1020B00004361F5610161000012C04D12846FEF7D6 +:1020C00061FF204670BD032C40F0A380FFF712FF94 +:1020D000012C40F09E80FEF7A7FBEFE7012C40F0BB +:1020E0009880224628466949FFF79EF8E9E7012CC7 +:1020F00040F08F80634E347814F00204E1D0EC8815 +:10210000402C00F2BC8069882246614306F10C0035 +:1021100000F050FD224606F10C01BBE7012C78D1FE +:10212000584B1C7814F00104CBD09A78022A02D0C4 +:10213000052A40F0A480EA88402A00F2A08001220B +:102140001A716A88DA80EA881A81EA881AB103214A +:1021500099704F499EE706229A7091E7494A917813 +:10216000032905D0062956D0012C52D1002309E0BD +:10217000012C0BD113793BB153780421002B0CBFF8 +:1021800000236423D27851E00521FBE7032C40D1E2 +:102190001479002C3BD0042315899370D3883D4AD1 +:1021A000138047F6C07203F58063990112EA831326 +:1021B00015D172B6384A384882F8343021F4001309 +:1021C000B3F5803F38BF21F4FF514FF0010234BF17 +:1021D00021F01F0101F4FF0100F032FD62B62F4E25 +:1021E0002F4833882A461844294900F0E3FC3388F5 +:1021F0001D44ADB2B5F5004F358005D172B6FFF77D +:1022000007FF62B600233380FEF7E6FC59E705239B +:102210009370012455E7012C0DD11379D278002B4E +:1022200008BF02214FF0000318BF07212846BDE870 +:102230007040FFF72BB8032CEBD11479ECB10723D6 +:10224000937072B6FFF7E4FE62B600261249FEF7FD +:10225000C3FC4B680E6093F91100B04201DBFEF73E +:102260005BFB104D2E764B6893F91300002801DBC1 +:10227000FEF752FB00232B7523E70223C8E7002457 +:102280001FE700BF50070020510700205207002021 +:102290005C070020DC080020E4880020DE880020A5 +:1022A000DE08002000E07F408FB54FF47002C24B83 +:1022B000C24DC3F888209D604AF20353C04CC14907 +:1022C000A4F8FE33FEF71CF8BF4BDFF870C3BF4A1B +:1022D000DFF86CE3C3E900C24FF40042C3E9022116 +:1022E0001A61BB4AC3E905E2FEF71EF8002384F831 +:1022F0001334092384F8A23094F8803433B90121CF +:1023000040F2C44084F88014FEF728F80023AC485B +:1023100084F8813484F8803484F8323090F83C308A +:102320001F07FBD542F2017343F20212A0F84830B6 +:10233000002380F84A30028580F82A3090F83C303B +:102340009E06FBD50322A34B83F81C21A24B0362FC +:10235000052380F82630FDF7E7FF012380F83030B1 +:1023600080F8523090F8743043F0400380F87430B5 +:10237000934B93F87420D209FBD00622462183F8B0 +:102380006C2083F8741083F8742093F87420D209B9 +:10239000FBD193F8772042F0400283F87720884BF6 +:1023A00093F87720D209FBD0022283F86F20C6224F +:1023B00083F8772093F8772002F0BF0283F8772024 +:1023C0007F4B93F87760F609FBD14FF42542A3F8D1 +:1023D000FE232B68A3F5805383F30A887F48804A45 +:1023E0003146121A00F0F3FB7E487F4A7F49121AE9 +:1023F00000F0E0FB37467E4D7E4C641BA410BC42CF +:1024000000F3458200257C4CFDF78EFFC82001219A +:1024100084F82850FDF7A2FF84F8245094F8243063 +:10242000002BFBD194F8243043F0020384F82430CD +:10243000714B93F824209507C2F34004F9D401208E +:1024400083F82240FDF7D6FF5D4B83F8BB44FDF7D0 +:10245000A5FF0320FDF7CEFF23464FF6FF70674A26 +:1024600003F108010133092B22F81100F8D10320F0 +:10247000FDF794FF0320FDF7BDFF6FF0FF02604BF7 +:10248000604C9A64FF210C2201A800F0A0FB2546B5 +:102490000023012735F8022B6AB104A95A0901EB80 +:1024A000820203F01F0107FA01F052F80C1C21EA26 +:1024B000000142F80C1C0133602BEBD10199504A0A +:1024C000514B1167C3F88012029903205167C3F87A +:1024D000841203999167C3F88812FDF75FFF002308 +:1024E0004A4A03F1C00134F8020B0133602B42F871 +:1024F0002100F6D162B6464CDFF8489123684B457F +:1025000004D04448C4F80090FDF79CFF4FF47A7261 +:10251000414F3B68B3FBF2F3013BB3F1807F0AD23A +:102520004FF0E022F0215361234B83F82310002366 +:1025300093610723136123684B4502BF4FF4800268 +:10254000364B9A621E4B364AD3F80015914240F042 +:10255000CD814AF20252A3F8FE230022C3F80025DF +:102560004FF42542A3F8FE232E4B1A684A4504D0A7 +:102570002D48C3F80090FDF765FF2C4CDFF8C880AC +:102580002368434500F0AF804FF48073E360284B2D +:10259000002563600123274A2374A2606561C4E9B2 +:1025A0000655EFF3108183F31088234B1A6922F448 +:1025B00000021A611B6949E000ED00E00000000024 +:1025C00000E0014000366E017C05002000127A0018 +:1025D000001C4E0E00C00140211201209805002071 +:1025E000748B0020000000207C050020082F0000D4 +:1025F0007C0500207C05002000300840000D0840CC +:1026000000800040B82D000000E100E000600040C4 +:10261000408B00209C2D0000980500200000084001 +:1026200035817307388B0020B82E00004C8B0020BA +:10263000C02E00000098164000400840002D3101D7 +:1026400000C2EB0B54524F505450470081F3108896 +:102650004FF42542A36844F64B401A604FF4000241 +:10266000A36801A9DD62DD639D64DA624FF0004278 +:102670001A615A619A6149F695025D629D62DD6157 +:102680001D629A665A664FF0FF332A46CDE901353E +:10269000FEF7D0FBA268019B284653659365029B19 +:1026A000190641EA0341FEF729FB4FF4AA0395639B +:1026B000C2F888501364E3680004D36041F0030358 +:1026C00041F001015063136328461163FF21FEF7B7 +:1026D0001DFB29462846FEF719FB29462846FEF72A +:1026E00015FBC4F8008044F61F6344F6206261685D +:1026F0000878032898BF1A46A3689A66097819B91A +:1027000042F20F7159659965D96ACD0705D45A66A9 +:102710004FF4AA021A64E268DA6001210020FEF791 +:10272000BDFB23685C48434504BFD4E902325A60CC +:102730005A4B5B4C436000232376237580F834307A +:102740000123584D85F816342B6A39682D6AC3F376 +:10275000026201FA02F2C3F30273C5F30265DA40C2 +:1027600001FA05F35049EB408A423ED94F4902F540 +:10277000742202F23F22B2FBF1F203F5742303F25A +:102780003F23B3FBF1F343F6B85102F5F05292B296 +:10279000A4F8E42006225943B1FBF2F1816040F62F +:1027A000D8615943B1FBF2F1C1605900B1FBF2F1BC +:1027B000016154215943B1FBF2F141613C49594354 +:1027C000B1FBF2F1816144F250615943B1FBF2F186 +:1027D000416238495943B1FBF2F1016236494B433A +:1027E000B3FBF2F3C361354B03602B48344D00F06B +:1027F0001FFA01220221284800F02AFA2B78FF2B29 +:102800001FD13B2200212F4800F0E1F900222E4B7E +:10281000DA819A812D4A13602D4B23B12D4800E0B7 +:1028200000BF2D4B18602B4CF0B2FDF7D5FF0028F0 +:1028300040F053814FF0E023D3F8F03DD80700D5A6 +:1028400000BE264F264EDFF8A0802B78FF2B01D04C +:10285000FEF75AFF3A683368D21A632AF5D9D8F8D6 +:1028600000406433012120463360FEF717FB1D4B07 +:102870001A78002A00F07E81B4F5FA6F80F0758135 +:1028800000221A704FF4FA63C8F80030DDE755F8FB +:10289000043B98470137B2E5E4880020A42D0000EE +:1028A00000E07F4000E00140FF083D0040420F0093 +:1028B00038AF040080DE0F00A0F703004E45504FF4 +:1028C00038050020DC07002028050020180800201B +:1028D00000000000A00500209C050020708B002057 +:1028E0006C8B0020E0880020488B002093F81014A7 +:1028F000C80709D44AF20251A3F8FE13C3F8002511 +:102900004FF42542A3F8FE23A14D6A6A002A00F085 +:1029100093806B689F498B4203D09F498B4240F064 +:102920008B8095F90F30002BC0F2868095F910301E +:10293000002BC0F28180994CDFF874A2E368534504 +:102940007AD02B781F2B77D840F2FF31D940C907B6 +:1029500072D5117819B192F90320002A6CDA4FF080 +:10296000000803F5800303F58C531B022361AB6859 +:10297000256063602B7BC4F838802372EB69636346 +:102980002B6AE363EFF31080012383F310884FF089 +:102990000041834B95F800C05A6821FA0CF122EAF5 +:1029A00001025A605B6880F31088F0222368596A3C +:1029B000236983F802802369DA728B78226903F035 +:1029C00003031370FA2223699A714A7823695A70B3 +:1029D0000B7822699B0043F02003DBB2D3714A7964 +:1029E00023691A72CA7823699A740B792269DB0009 +:1029F00043F00103DBB25372232223699A722369E5 +:102A0000664A83F80D80697B95F90F00FDF796FF04 +:102A1000624A697B95F91000FDF790FFC4E90688CA +:102A2000C4E9088884F82D80C4F80CA084F82E80AE +:102A300084F82F8084F8308080219C20FEF7EEF807 +:102A400020219E20FEF7EAF8564A1368B3F5FA7F74 +:102A5000FBD34AF2025400204FF425454FF4803155 +:102A6000514AA2F8FE43C2F80005A2F8FE530B68D3 +:102A700003F07F43B3F1005F7FF476ADA2F8FE432D +:102A8000EFF3108E4FF0010C8CF31088444B5C6810 +:102A900044F400645C605C688EF31088EFF3108E81 +:102AA0008CF310885C6844F480545C605B688EF33F +:102AB0001088A2F8FE5380F30A8872B6BFF34F8FD6 +:102AC000BFF36F8F4FF0E0231861C3F8081D0B6848 +:102AD00083F308884B68984746E5036898470136B2 +:102AE0002278F3B29A42BFF49FAE00232C4A2B7097 +:102AF000536823F4006353602C4B1A8842F48062BD +:102B00001A801A885105FCD51A8840216FF34512A6 +:102B10001A801A8800206FF386121A801A8842F0F1 +:102B200001021A800522C3F8F020D3F800246FF3C5 +:102B30000412C3F80024B3F85E2061F30602A3F880 +:102B40005E200022A3F840204FF45D421A86012245 +:102B50005A87DA86B3F84020120642BF1A8842F03C +:102B600010021A80FDF782FB6BE6A4F5FA64C8F840 +:102B700000406AE644F61F6204F5FA649442C8F81D +:102B800000407FF662AE01221A7044F620637BE6B5 +:102B90004C050020A0860100801A0600F88A00205B +:102BA00000400840708B002000E001400000094018 +:102BB000433249530A44431E914200D1704710B535 +:102BC00011F8014B914203F8014FF9D110BD0244B5 +:102BD0000346934200D1704703F8011BF9E703460F +:102BE00013F8012B002AFBD1181A01387047FFFF98 +:102BF00001B40248844601BC604700BF7501002053 +:102C000001B40248844601BC604700BF490300206C +:102C100001B40248844601BC604700BF3501002072 +:102C200001B40248844601BC604700BF0100002097 +:102C300001B40248844601BC604700BFE1000020A7 +:102C400001B40248844601BC604700BFD1030020A4 +:102C500001B40248844601BC604700BF81040020E3 +:102C600000000504342E352E30004275696C742046 +:102C7000776974682052656E65736173204164766C +:102C8000616E63656420466C657869626C6520538B +:102C90006F667477617265205061636B6167652050 +:102CA00076657273696F6E20342E352E3000417256 +:102CB0006475696E6F00537061726B46756E205457 +:102CC00068696E6720506C7573205241364D35200F +:102CD0004446550040436F6465466C617368202F1D +:102CE000307830303030303030302F382A384B6147 +:102CF0002C36332A33324B67004044617461466C92 +:102D0000617368202F307830383030303030302FD9 +:102D1000382A314B67000100020904FF490800000E +:102D200039080000510800004D200000000000009C +:102D30000000000004000000060100000000000088 +:102D400008040000000C011307040000000C01132C +:102D500000050000000C0113010500000902240019 +:102D600001010080320904000000FE010204090490 +:102D7000000100FE010205092107E80340000101EE +:102D800012010002000000404F1B3600000101024A +:102D90000301FFFF00000103060100000500000021 +:102DA000342D000000000000010C000000000000B5 +:102DB00000000000020702086D006E006B006C004E +:102DC0000000000000003100300093019401000079 +:102DD00000000000000000000000000000000000F3 +:102DE00000000000000000000000000000000000E3 +:102DF00000000000000000000000000000000000D3 +:102E000000000000000000000000000000000000C2 +:102E100000000000000000000000000000000000B2 +:102E200000000000000000000000000000000000A2 +:102E30000000000000000000000000000000000092 +:102E40000000000000000000000000000000000082 +:102E50000000000000000000000000000000000072 +:102E60000000000000000000000000000000000062 +:102E70000000000000000000010002000800100037 +:102E80000000010000000000000000000000000041 +:102E90000000000000000000000000000000000032 +:102EA0000000000000000000000000000000000022 +:102EB000020403040404FFFF01000000942D00003D +:102EC0000200000096980000010000004B4C00003A +:102ED00008FF00000000000000000000802E00003D +:102EE0000000094000000000001011400400000034 +:102EF000192D0000AE2C0000B62C0000B48A002072 +:082F0000D42C0000F92C0000A4 +:102F08004FF42A4110B500204FF49644104AB2F805 +:102F18008430A2F884109BB2B2F8841089B241B907 +:102F2800012B0CD14DF60113A2F8443000F064FADD +:102F380010BD002C08BF4FF4FA70013CECE7802B61 +:102F4800F6D10122034B5A605A68002AFCD1EFE7F8 +:102F580000E07F40007000404FF49643B32282B0F7 +:102F680001930C4B1A700C4AD2F880301B0408D518 +:102F7800137C40F2F51013F0100F08BF002002B0C8 +:102F88007047019B1BB1019B013B0193ECE71420A7 +:102F9800F5E700BF00007E4000E07F404FF4964315 +:102FA800502282B001930C4B1A700C4AD2F8803030 +:102FB8001B0408D5137C40F2F51013F0100F08BF5E +:102FC800002002B07047019B1BB1019B013B01939C +:102FD800ECE71420F5E700BF00007E4000E07F40EA +:102FE80038B5436805461A7842B193F9110000F0E4 +:102FF800FBF96B6893F9130000F0F6F90C4BB3F882 +:1030080084309BB213B9284600F0FEF9FFF7A4FFFD +:103018000446FFF7C3FF002C08BF0446FFF770FF04 +:1030280000239C4218BF204685F8343038BD00BFC5 +:1030380000E07F4030B50D4C836A0D4D236320239B +:103048002B70D0232B70836A1944036B8162013B78 +:103058000363104612B930BD30B10138D4F880305E +:103068001B04F9D50020F6E71420F4E700E07F40C0 +:1030780000007E40F7B50446154622B9436893F927 +:10308800110000F0B1F9E820E36A214A4E08136301 +:10309800204BC1F347011870197000218E4210D1DE +:1030A800D0211970002D2CD1636893F911300122B9 +:1030B800590903F01F0302FA03F3174A42F82130B3 +:1030C80019E020690190A06A00881880D2F8800071 +:1030D80040050AD4A06A01310230A062E06A0230D9 +:1030E800E062206B01382063D8E70198471E0197FA +:1030F8000028EBD11425284603B0F0BD002DF9D0E7 +:10310800013DD2F880301B04F8D50025F3E700BF55 +:1031180000E07F4000007E4000E100E010B50E4B6B +:103128001C7CE40609D5D3F88040640402D51C7CD5 +:1031380000241C7440F2F51400E00024D3F8803019 +:103148000B4218BF144620B90CB1FFF705FF204603 +:1031580010BD0446F9E700BF00E07F40402213B5E8 +:10316800836910480193104B01631A7008221A7082 +:1031780000220E4931F8024B0132082A1C80F9D18D +:10318800D0221A70D0F880301B0402D5002002B07B +:1031980010BD019B1BB1019B013B0193F2E7142079 +:1031A800F5E700BF00E07F4000007E403A050020C0 +:1031B8006FEA415110B56FEA51514FF6FF74074B52 +:1031C80042EAC03040F4F0401C805C80D88099808E +:1031D8001C815C819C81DC8110BD00BF3A05002008 +:1031E8004FF4964307B500220193154B01461A6028 +:1031F80043681A7842B193F9110000F0F5F84B686A +:1032080093F9130000F0F0F84FF459430D4AA2F86F +:1032180044304AF60123A2F88430B2F884309BB2D5 +:10322800012B03D1002003B05DF804FB019B1BB107 +:10323800019B013B0193F0E74FF4FA70F3E700BFFD +:103248000070004000E07F4038B50546FFF7C8FF32 +:10325800044668B1204638BD6CB98021AA68284662 +:10326800FFF708FF18224FF4A041FFF757FF044665 +:103278002B6B002BF0D1FFF743FE002C08BF044650 +:10328800E8E710B50F4B0446D3F890310E4803F029 +:103298000703DB430E2220F8023BFF2100F0BCF8B5 +:1032A8002046FFF79DFF20460849FFF757FF1822E1 +:1032B8000021FFF733FF0446FFF722FE002C18BF5A +:1032C800204610BD00A000013A05002090A1000191 +:1032D80038B5816202630546FFF782FF044650B99C +:1032E8000122124BA3F8E0202B6B33B9FFF708FE3D +:1032F800002C08BF0446204638BD002CF6D1D5E97D +:103308000712AB6A284623F40013B3F5803F36BF93 +:103318000A464FF400414FF40051FFF78BFE192283 +:103328004FF4C041FFF7FAFE0446DDE700E07F40B6 +:103338002DE9F041104B0546D3F8DC600F46904666 +:10334800FFF74EFFF60F044698B94FEA5832304659 +:10335800790BFFF72DFF09492846FFF7FFFE2146A5 +:103368001822FFF7DBFE0446FFF7CAFD002C08BF52 +:1033780004462046BDE8F08100E07F4030A100010E +:10338800F8B507460D461646FFF72AFF044650B91A +:103398005EB1124B45F4CC45A3F8E850FFF7B0FDF9 +:1033A800002C08BF04462046F8BD1022FF210C4817 +:1033B80000F032F847F6FF7215F0010F4FF6FF7371 +:1033C80018BF1346064A0749D3803846FFF7C6FE9A +:1033D80021461822FFF7A2FE0446DFE700E07F40FF +:1033E8003A05002030A1000101B40248844601BC1E +:1033F800604700BF1909000001B40248844601BCB7 +:10340800604700BF0103000001B40248844601BCC4 +:10341800604700BF9509000001B40248844601BC1A +:10342800604700BFCF2B0000150800001C080020D3 +:1034380010000C0000000000FF00FFFF000000006B +:103448000000000000000000000000000300000071 +:10345800A086010000000000010C00090A0000001D +:103468000000000000000000CD0800004C0500200E +:0C34780074050020000E00FF0F01000092 +:020000040100F9 +:10A10000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F +:04A11000FFFFFFFF4F +:04A13400FFFFFFFF2B +:10A20000FFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFF60 +:10A21000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4E +:10A22000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E +:10A23000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2E +:10A24000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1E +:10A25000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0E +:10A26000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE +:10A27000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEE +:10A28000F8F8FFFFFFFFFFFFFFFFFFFFFFFFFFFFEC +:10A29000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCE +:10A2A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE +:10A2B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAE +:10A2C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9E +:04000003000022A92E +:00000001FF diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.api_xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.api_xml new file mode 100644 index 00000000..fc9bf0b3 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.api_xml @@ -0,0 +1,2 @@ + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject new file mode 100644 index 00000000..627cb454 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject @@ -0,0 +1,470 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.gitignore b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.gitignore new file mode 100644 index 00000000..9319fb47 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.gitignore @@ -0,0 +1,8 @@ +src +script +ra_gen +ra_cfg +ra +Debug +*.d +*.o diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.project b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.project new file mode 100644 index 00000000..27ce0519 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.project @@ -0,0 +1,39 @@ + + + SparkFun_ThingPlus_RA6M5 + + + + + + com.renesas.cdt.ddsc.contentgen.ddscBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + com.renesas.cdt.ddsc.contentgen.ddscInterlockBundleBuilder + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.renesas.cdt.ddsc.contentgen.ddscNature + com.renesas.cdt.ra.contentgen.raNature + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone new file mode 100644 index 00000000..1b5d1ad1 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml new file mode 100644 index 00000000..8f7a2445 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml @@ -0,0 +1,108 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/.gitignore b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/.gitignore new file mode 100644 index 00000000..63b586fc --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/.gitignore @@ -0,0 +1 @@ +/e2studio_project.prefs diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.content.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.content.prefs new file mode 100644 index 00000000..cce6e837 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.content.prefs @@ -0,0 +1,2 @@ +com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.ld +eclipse.preferences.version=1 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.contentgen.options.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.contentgen.options.prefs new file mode 100644 index 00000000..b58c21e7 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.contentgen.options.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +options/suppresswarningspaths=ra/arm diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.packs.componentfiles.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.packs.componentfiles.prefs new file mode 100644 index 00000000..317784b5 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.packs.componentfiles.prefs @@ -0,0 +1,71 @@ +Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.0.0/all=1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h +Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.0.0/libraries= +Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.0.0/all= +Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.0.0/libraries= +Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.0.0/all=3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +Renesas\#\#BSP\#\#ra6m5\#\#device\#\#\#\#4.0.0/libraries= +Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5AH3CFP\#\#4.0.0/all= +Renesas\#\#BSP\#\#ra6m5\#\#device\#\#R7FA6M5AH3CFP\#\#4.0.0/libraries= +Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.0.0/all=685401113,ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h|2691744783,ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h|54555052,ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +Renesas\#\#BSP\#\#ra6m5\#\#fsp\#\#\#\#4.0.0/libraries= +Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.0.0/all=3581562463,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h|3081439153,ra/fsp/src/bsp/mcu/all/bsp_common.h|3759750755,ra/fsp/inc/api/r_ioport_api.h|1716413299,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|1856421676,ra/fsp/src/bsp/mcu/all/bsp_io.h|4244247716,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h|1551502070,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|969398837,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h|2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1425039890,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h|3340291051,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|4195603704,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1885639365,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|4237066482,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|4073922953,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|4138496331,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h|3604770955,ra/fsp/src/bsp/mcu/all/bsp_security.c|2015535075,ra/fsp/inc/fsp_common_api.h|3102191275,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h|3108886471,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h|2162306140,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h|1799272679,ra/fsp/inc/fsp_features.h|1211846894,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3088682327,ra/fsp/inc/fsp_version.h|2027396638,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|4202124312,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h|1803108733,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|1422656163,ra/fsp/src/bsp/mcu/all/bsp_delay.h|925252786,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h|2023808024,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1533566537,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2344654655,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|3873606974,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2159626279,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3066054229,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3360147982,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2455688865,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h|715820739,ra/fsp/inc/api/bsp_api.h|4168946909,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h|2490905981,ra/fsp/inc/instances/r_ioport.h|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c +Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#4.0.0/all=2978087792,ra/fsp/inc/api/r_elc_api.h|2915671340,ra/fsp/inc/api/r_adc_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|2065369618,ra/fsp/src/r_adc/r_adc.c|2592638374,ra/fsp/inc/instances/r_adc.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_adc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_agt\#\#\#\#4.0.0/all=1805157745,ra/fsp/inc/instances/r_agt.h|1385984689,ra/fsp/inc/api/r_timer_api.h|3586857181,ra/fsp/src/r_agt/r_agt.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_agt\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ble_all\#\#\#\#4.0.0/all=1004293289,ra/fsp/src/r_ble/r_ble.c|640123063,ra/fsp/inc/api/r_ble_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ble_all\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_cgc\#\#\#\#4.0.0/all=915802890,ra/fsp/inc/api/r_cgc_api.h|432412330,ra/fsp/inc/instances/r_cgc.h|699719569,ra/fsp/src/r_cgc/r_cgc.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_cgc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_crc\#\#\#\#4.0.0/all=2061051029,ra/fsp/inc/api/r_crc_api.h|89845629,ra/fsp/src/r_crc/r_crc.c|2206201561,ra/fsp/inc/instances/r_crc.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_crc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dac\#\#\#\#4.0.0/all=4193050144,ra/fsp/inc/api/r_dac_api.h|2385623637,ra/fsp/inc/instances/r_dac.h|2387772377,ra/fsp/src/r_dac/r_dac.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dac\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dmac\#\#\#\#4.0.0/all=650669250,ra/fsp/src/r_dmac/r_dmac.c|183147201,ra/fsp/inc/instances/r_dmac.h|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dmac\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.0.0/all=428353588,ra/fsp/inc/instances/r_dtc.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|1261122503,ra/fsp/src/r_dtc/r_dtc.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_elc\#\#\#\#4.0.0/all=3723981064,ra/fsp/inc/instances/r_elc.h|2112694741,ra/fsp/src/r_elc/r_elc.c|2978087792,ra/fsp/inc/api/r_elc_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_elc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#4.0.0/all=915802890,ra/fsp/inc/api/r_cgc_api.h|1976517121,ra/fsp/inc/api/r_flash_api.h|842716288,ra/fsp/src/r_flash_hp/r_flash_hp.c|2876379499,ra/fsp/inc/instances/r_flash_hp.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_flash_hp\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#4.0.0/all=3417329805,ra/fsp/src/r_gpt/r_gpt.c|1385984689,ra/fsp/inc/api/r_timer_api.h|1101069320,ra/fsp/inc/instances/r_gpt.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_gpt\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#4.0.0/all=1175293790,ra/fsp/inc/instances/r_icu.h|1002305543,ra/fsp/inc/api/r_external_irq_api.h|1806776990,ra/fsp/src/r_icu/r_icu.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_iic_master\#\#\#\#4.0.0/all=1587407673,ra/fsp/inc/api/r_i2c_master_api.h|1163980116,ra/fsp/src/r_iic_master/r_iic_master.c|1116392784,ra/fsp/inc/instances/r_iic_master.h|2978087792,ra/fsp/inc/api/r_elc_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_iic_master\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_iic_slave\#\#\#\#4.0.0/all=2106851309,ra/fsp/inc/instances/r_iic_slave.h|554131841,ra/fsp/inc/api/r_i2c_slave_api.h|1333618936,ra/fsp/src/r_iic_slave/r_iic_slave.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_iic_slave\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.0.0/all=500387124,ra/fsp/src/r_ioport/r_ioport.c|3759750755,ra/fsp/inc/api/r_ioport_api.h|2490905981,ra/fsp/inc/instances/r_ioport.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_lpm\#\#\#\#4.0.0/all=1178531853,ra/fsp/inc/api/r_lpm_api.h|1404317373,ra/fsp/src/r_lpm/r_lpm.c|178427390,ra/fsp/inc/instances/r_lpm.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_lpm\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_qspi\#\#\#\#4.0.0/all=702051868,ra/fsp/inc/instances/r_qspi.h|2068507610,ra/fsp/inc/api/r_spi_flash_api.h|3903125740,ra/fsp/src/r_qspi/r_qspi.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_qspi\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_rtc\#\#\#\#4.0.0/all=3195700237,ra/fsp/inc/instances/r_rtc.h|1927924220,ra/fsp/src/r_rtc/r_rtc.c|915802890,ra/fsp/inc/api/r_cgc_api.h|1090805371,ra/fsp/inc/api/r_rtc_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_rtc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sce9_ra6_protected\#\#\#\#4.0.0/all=2329881314,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func313.c|2670225476,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func061.c|711961166,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p8f.c|3282759739,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func080.c|3357392705,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36a.c|3718774333,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c|397166016,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce.c|4175008399,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34f.c|455789550,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29t.c|3379946355,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4u.c|2425071969,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p81.c|826946694,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func317.c|3301247821,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func102.c|2043528082,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36i.c|1484653247,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p20.c|4112295990,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4i.c|2904780031,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe8.c|3800900745,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func008.c|2716043193,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95f.c|325209459,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc04.c|1485559359,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h|598011109,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c|3879778740,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func027.c|1648356293,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func069.c|402611851,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe0.c|3452131033,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func023.c|2462591830,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe4.c|1201298227,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func004.c|3646427797,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func325.c|417094889,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func302.c|3250935756,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1u.c|2158572701,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func053.c|793900332,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func030.c|552490517,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func321.c|2686118887,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5a.c|433217649,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76u.c|386123104,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h|598274033,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p92.c|73038435,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p54.c|243323724,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf9.c|1346143175,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/r_sce_private.c|4201334807,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1i.c|3226294969,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98f.c|791457805,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32t.c|2818731793,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_sha.c|1912403183,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf1.c|4287231587,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func200.c|2016309664,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func057.c|3655650982,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func011.c|3426236823,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h|495907630,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf5.c|2297496517,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func076.c|1228964485,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p6f.c|3957921251,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func314.c|2861638853,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func062.c|2638818651,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func081.c|532268222,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf0.c|3445914380,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func310.c|1440364303,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29u.c|281973942,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36f.c|4094624133,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pdf.c|459037420,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func318.c|1048822930,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/s_flash2.c|3182204649,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func103.c|2050759839,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa4f.c|3317955873,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func009.c|2125664832,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p00.c|1768790990,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func001.c|1438581093,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe3.c|1173215098,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc01.c|2677170705,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func028.c|969729683,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func043.c|3330521712,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func005.c|4138692966,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe7.c|859960623,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41f.c|4218492138,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p08.c|3192088613,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func303.c|2911744307,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5d.c|2874220348,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func050.c|2127026430,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func073.c|2735981480,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func322.c|1270016773,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29a.c|3381662451,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_ecc.c|3882757865,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func307.c|686144321,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29i.c|2416920891,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func205.c|3407405717,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pa1f.c|989137654,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p57.c|2718451925,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p72.c|4219055341,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p53.c|3183066690,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf4.c|1781321531,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32u.c|2509884533,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44f.c|4268713480,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34t.c|3362849315,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func077.c|2051118608,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func054.c|1418286871,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func040.c|3064606294,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func063.c|2886287696,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98u.c|3727696463,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func311.c|627302949,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32a.c|4193015785,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h|1959554264,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func319.c|418574873,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func100.c|2192864910,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32i.c|1802429362,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50f.c|4017026864,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func315.c|1585645912,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76f.c|1063698648,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func002.c|560565578,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func025.c|1671900882,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func048.c|4287957782,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe2.c|1985018607,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p26.c|580273970,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_tls.c|1201684797,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47f.c|3224421952,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe6.c|3337895680,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func006.c|804628732,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func044.c|390812503,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p07.c|636246294,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func074.c|3398814750,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41i.c|1734422546,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func323.c|2381174767,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func300.c|2766912261,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func051.c|2026674365,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func070.c|1627612466,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5c.c|2226138357,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p9e.c|1935683883,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p7b.c|2253508786,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func308.c|3282912264,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p90.c|2261475037,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p41u.c|3514536236,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func304.c|4239569623,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func206.c|652783645,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p56.c|2650203987,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p79.c|1949288078,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36t.c|1963949205,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p29f.c|2715149732,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_rsa.c|1010986654,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34u.c|208558540,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func059.c|1695948213,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func202.c|1808684698,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44i.c|2995163339,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func064.c|3099575607,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50u.c|3983672542,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func312.c|772340586,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func060.c|3402834229,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h|1768565709,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c|804752664,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34a.c|3755214449,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func101.c|2508908046,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p82.c|4070729622,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p44u.c|4134871861,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p50i.c|837847686,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p32f.c|358529407,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p34i.c|440559865,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func316.c|1094444090,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p76i.c|1556806415,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe9.c|3159780913,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_subprc03.c|1267947874,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func007.c|2659875179,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p40.c|3913661410,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p21.c|1332983451,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47i.c|819903673,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func049.c|2920109981,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe1.c|1359785052,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c|3184980228,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func068.c|3314367186,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func022.c|1105382959,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pe5.c|1976114165,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func003.c|2146706177,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func052.c|3884065532,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func075.c|318448564,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5aIA.c|858919356,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func324.c|49409175,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func301.c|39591218,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p47u.c|105602913,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func071.c|2181334248,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func320.c|1950801905,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95u.c|174306931,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p5b.c|3359995090,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p95i.c|3968356842,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func309.c|379368160,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func305.c|375660805,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func207.c|2822737026,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p36u.c|179597367,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p98i.c|2233541783,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func010.c|2176182241,ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_pf6.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sce9_ra6_protected\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_i2c\#\#\#\#4.0.0/all=1587407673,ra/fsp/inc/api/r_i2c_master_api.h|684803572,ra/fsp/inc/instances/r_sci_i2c.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|744381531,ra/fsp/src/r_sci_i2c/r_sci_i2c.c +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_i2c\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.0.0/all=57267461,ra/fsp/inc/instances/r_sci_spi.h|2516469150,ra/fsp/inc/api/r_spi_api.h|2999473418,ra/fsp/src/r_sci_spi/r_sci_spi.c|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.0.0/all=3958601320,ra/fsp/inc/instances/r_sci_uart.h|1053173491,ra/fsp/src/r_sci_uart/r_sci_uart.c|134969800,ra/fsp/inc/api/r_uart_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sdhi\#\#\#\#4.0.0/all=2205041427,ra/fsp/inc/instances/r_sdhi.h|3324834867,ra/fsp/src/r_sdhi/r_sdhi.c|1769066384,ra/fsp/inc/api/r_sdmmc_api.h|2978087792,ra/fsp/inc/api/r_elc_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|3273088393,ra/fsp/src/r_sdhi/r_sdhi_private.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_sdhi\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#4.0.0/all=1717775098,ra/fsp/src/r_spi/r_spi.c|2516469150,ra/fsp/inc/api/r_spi_api.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|1862694493,ra/fsp/inc/instances/r_spi.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ssi\#\#\#\#4.0.0/all=3508173574,ra/fsp/inc/api/r_i2s_api.h|2428497272,ra/fsp/src/r_ssi/r_ssi.c|1385984689,ra/fsp/inc/api/r_timer_api.h|2978087792,ra/fsp/inc/api/r_elc_api.h|2096260039,ra/fsp/inc/instances/r_ssi.h|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_ssi\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_basic\#\#\#\#4.0.0/all=136800880,ra/fsp/src/r_usb_basic/src/driver/r_usb_clibusbip.c|3048946461,ra/fsp/src/r_usb_basic/r_usb_basic.c|1197902290,ra/fsp/src/r_usb_basic/src/driver/r_usb_cstd_rtos.c|3686785491,ra/fsp/src/r_usb_basic/src/hw/r_usb_hostelectrical.c|1769437146,ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c|281453534,ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h|1057668898,ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_abs.c|1180787286,ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h|2807041958,ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c|1705260814,ra/fsp/inc/instances/r_usb_basic.h|2635238596,ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h|3405305039,ra/fsp/src/r_usb_basic/src/driver/r_usb_pinthandler_usbip0.c|3570366557,ra/fsp/src/r_usb_basic/src/driver/r_usb_plibusbip.c|2854132102,ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_abs.c|495815098,ra/fsp/src/r_usb_basic/src/driver/r_usb_hscheduler.c|3943290117,ra/fsp/src/r_usb_basic/src/driver/r_usb_pcontrolrw.c|869433368,ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c|2533514321,ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c|2093730444,ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h|1258411609,ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h|2646087786,ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip0.c|107260058,ra/fsp/src/r_usb_basic/src/driver/r_usb_pintfifo.c|2477175694,ra/fsp/src/r_usb_basic/src/driver/r_usb_hinthandler_usbip1.c|4237829907,ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdfunction.c|3326560148,ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c|884045313,ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h|1422247075,ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_abs.c|3696884123,ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c|4048195589,ra/fsp/src/r_usb_basic/src/driver/r_usb_hintfifo.c|1241406792,ra/fsp/src/r_usb_basic/src/driver/r_usb_pstdrequest.c|1961640883,ra/fsp/src/r_usb_basic/src/driver/r_usb_hbc.c|3601262871,ra/fsp/src/r_usb_basic/src/driver/r_usb_hstdfunction.c|2590633241,ra/fsp/src/r_usb_basic/src/driver/r_usb_hsignal.c|176599803,ra/fsp/src/r_usb_basic/src/driver/r_usb_pdriver.c|1601939624,ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c|1630855743,ra/fsp/src/r_usb_basic/src/driver/r_usb_psignal.c|637483320,ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c|1640032,ra/fsp/inc/api/r_usb_basic_api.h|383802279,ra/fsp/src/r_usb_basic/src/driver/r_usb_hmanager.c|2524774844,ra/fsp/src/r_usb_basic/src/driver/r_usb_pbc.c|4287506155,ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h|2481030592,ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c|555858210,ra/fsp/src/r_usb_basic/src/driver/r_usb_hhubsys.c|2970687511,ra/fsp/inc/api/r_transfer_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_basic\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_composite\#\#\#\#4.0.0/all=737325267,ra/fsp/src/r_usb_composite/r_usb_phid_pmsc_descriptor.c.template|1906037992,ra/fsp/src/r_usb_composite/r_usb_pcdc_pcdc_descriptor.c.template|2392622759,ra/fsp/src/r_usb_composite/r_usb_pcdc_pmsc_descriptor.c.template|3377217428,ra/fsp/src/r_usb_composite/r_usb_phid_phid_descriptor.c.template|1640032,ra/fsp/inc/api/r_usb_basic_api.h|2228678530,ra/fsp/src/r_usb_composite/r_usb_pcdc_phid_descriptor.c.template +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_composite\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_pcdc\#\#\#\#4.0.0/all=1825496630,ra/fsp/src/r_usb_pcdc/src/r_usb_pcdc_driver.c|2298650489,ra/fsp/inc/api/r_usb_pcdc_api.h|906325334,ra/fsp/src/r_usb_pcdc/r_usb_pcdc_descriptor.c.template|1839514706,ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_usb_pcdc\#\#\#\#4.0.0/libraries= +Renesas\#\#HAL\ Drivers\#\#all\#\#r_wdt\#\#\#\#4.0.0/all=3424779918,ra/fsp/src/r_wdt/r_wdt.c|3549284757,ra/fsp/inc/instances/r_wdt.h|2639470834,ra/fsp/inc/api/r_wdt_api.h +Renesas\#\#HAL\ Drivers\#\#all\#\#r_wdt\#\#\#\#4.0.0/libraries= +eclipse.preferences.version=1 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs new file mode 100644 index 00000000..2e1942fa --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs @@ -0,0 +1,2 @@ +com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +eclipse.preferences.version=1 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.threads.configurator.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.threads.configurator.prefs new file mode 100644 index 00000000..15f26966 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.threads.configurator.prefs @@ -0,0 +1,12 @@ +collapse/module.driver.basic_on_usb.283002553=false +collapse/module.driver.i2c_on_iic_master.857983463=false +collapse/module.driver.i2c_on_sci_i2c.66231608=false +collapse/module.driver.i2s_on_ssi.803618372=false +collapse/module.driver.pcdc_on_usb.592586967=false +collapse/module.driver.sdmmc_on_sdmmc.61359805=false +collapse/module.driver.spi_on_sci_spi.786111052=false +collapse/module.driver.spi_on_spi.1145449710=false +collapse/module.driver.uart_on_sci_uart.1673971705=false +collapse/module.driver.uart_on_sci_uart.623240377=false +collapse/module.driver.usb_composite.845210554=false +eclipse.preferences.version=1 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs new file mode 100644 index 00000000..0c9b5d05 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.managedbuild.gnuarm.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +is.toolchain.version=true +store.version=2 +toolchain.version=10.3.1.20210824 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml new file mode 100644 index 00000000..15c805e4 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.core.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..e17ec917 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,197 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.core.formatter.align_composite_type_declarators=false +org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=18 +org.eclipse.cdt.core.formatter.alignment_for_assignment=16 +org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=82 +org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16 +org.eclipse.cdt.core.formatter.alignment_for_compact_if=0 +org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=82 +org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18 +org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0 +org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16 +org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48 +org.eclipse.cdt.core.formatter.alignment_for_expression_list=0 +org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=82 +org.eclipse.cdt.core.formatter.alignment_for_lambda_expression=20 +org.eclipse.cdt.core.formatter.alignment_for_member_access=0 +org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16 +org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16 +org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16 +org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block=next_line +org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line +org.eclipse.cdt.core.formatter.brace_position_for_linkage_declaration=end_of_line +org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line +org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line +org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line +org.eclipse.cdt.core.formatter.comment.line_up_line_comment_in_blocks_on_first_column=false +org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1 +org.eclipse.cdt.core.formatter.comment.never_indent_line_comments_on_first_column=true +org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=true +org.eclipse.cdt.core.formatter.comment_formatter_off_tag=@formatter\:off +org.eclipse.cdt.core.formatter.comment_formatter_on_tag=@formatter\:on +org.eclipse.cdt.core.formatter.compact_else_if=true +org.eclipse.cdt.core.formatter.continuation_indentation=2 +org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2 +org.eclipse.cdt.core.formatter.format_block_comment=true +org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false +org.eclipse.cdt.core.formatter.format_header_comment=true +org.eclipse.cdt.core.formatter.format_line_comment=true +org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false +org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0 +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_linkage=false +org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false +org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=false +org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false +org.eclipse.cdt.core.formatter.indent_empty_lines=false +org.eclipse.cdt.core.formatter.indent_label_compare_to_statements=true +org.eclipse.cdt.core.formatter.indent_preprocessor_directives=false +org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true +org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true +org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=true +org.eclipse.cdt.core.formatter.indentation.size=4 +org.eclipse.cdt.core.formatter.insert_new_line_after_colon_in_constructor_initializer_list=insert +org.eclipse.cdt.core.formatter.insert_new_line_after_label=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_after_template_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_at_end_of_file_if_missing=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_catch_in_try_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_before_closing_brace_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_colon_in_constructor_initializer_list=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_else_in_if_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_before_identifier_in_function_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_new_line_before_while_in_do_statement=insert +org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block=insert +org.eclipse.cdt.core.formatter.insert_space_after_assignment_operator=insert +org.eclipse.cdt.core.formatter.insert_space_after_binary_operator=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_brace_in_block=insert +org.eclipse.cdt.core.formatter.insert_space_after_closing_paren_in_cast=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_base_clause=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_after_colon_in_labeled_statement=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_expression_list=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_throws=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_structured_binding_name_list=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments=insert +org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_parameters=insert +org.eclipse.cdt.core.formatter.insert_space_after_lambda_return=insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_cast=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_catch=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_parenthesized_expression=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_switch=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_while=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_opening_structured_binding_name_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_pointer_in_declarator_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_pointer_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_postfix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_prefix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_after_question_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_after_semicolon_in_for=insert +org.eclipse.cdt.core.formatter.insert_space_after_unary_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_assignment_operator=insert +org.eclipse.cdt.core.formatter.insert_space_before_binary_operator=insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_cast=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_catch=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_for=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_if=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_switch=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_while=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_closing_structured_binding_name_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_colon_in_base_clause=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_colon_in_case=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_colon_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_before_colon_in_default=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_colon_in_labeled_statement=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_declarator_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_enum_declarations=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_expression_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_throws=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_invocation_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_structured_binding_name_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_cast=insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_in_method_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_declarator_list=insert +org.eclipse.cdt.core.formatter.insert_space_before_identifier_in_declarator_list=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_lambda_return=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_arguments=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_parameters=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_array_initializer=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_linkage_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_namespace_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_switch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_type_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_bracket=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_catch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_exception_specification=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_for=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_if=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_switch=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_while=insert +org.eclipse.cdt.core.formatter.insert_space_before_opening_structured_binding_name_list=insert +org.eclipse.cdt.core.formatter.insert_space_before_pointer_in_declarator_list=insert +org.eclipse.cdt.core.formatter.insert_space_before_pointer_in_method_declaration=insert +org.eclipse.cdt.core.formatter.insert_space_before_postfix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_prefix_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert +org.eclipse.cdt.core.formatter.insert_space_before_ref_qualifier_in_structured_binding=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_semicolon=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_semicolon_in_for=do not insert +org.eclipse.cdt.core.formatter.insert_space_before_unary_operator=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_declaration=do not insert +org.eclipse.cdt.core.formatter.insert_space_between_pointer_operators_in_expression=do not insert +org.eclipse.cdt.core.formatter.join_wrapped_lines=true +org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false +org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false +org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false +org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false +org.eclipse.cdt.core.formatter.lineSplit=120 +org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1 +org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true +org.eclipse.cdt.core.formatter.tabulation.char=space +org.eclipse.cdt.core.formatter.tabulation.size=4 +org.eclipse.cdt.core.formatter.use_comment_formatter_tag=true +org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..24962bba --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,13 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPATH/delimiter=; +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPATH/operation=remove +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPLUS_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/CPLUS_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/append=true +environment/buildEnvironmentInclude/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/appendContributed=true +environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/append=true +environment/buildEnvironmentLibrary/com.renesas.cdt.managedbuild.gnuarm.config.elf.debug.723498862/appendContributed=true diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.core.resources.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..99f26c02 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/SparkFun_ThingPlus_RA6M5 Debug_Flat.launch b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/SparkFun_ThingPlus_RA6M5 Debug_Flat.launch new file mode 100644 index 00000000..49855809 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/SparkFun_ThingPlus_RA6M5 Debug_Flat.launch @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml new file mode 100644 index 00000000..c984b25c --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml @@ -0,0 +1,1210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board Support Package Common Files + Renesas.RA.4.0.0.pack + + + I/O Port + Renesas.RA.4.0.0.pack + + + Arm CMSIS Version 5 - Core (M) + Arm.CMSIS5.5.9.0+renesas.0.fsp.4.0.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.4.0.0.pack + + + Board support package for R7FA6M5AH3CFP + Renesas.RA_mcu_ra6m5.4.0.0.pack + + + Board support package for RA6M5 + Renesas.RA_mcu_ra6m5.4.0.0.pack + + + Board support package for RA6M5 - FSP Data + Renesas.RA_mcu_ra6m5.4.0.0.pack + + + A/D Converter + Renesas.RA.4.0.0.pack + + + Asynchronous General Purpose Timer + Renesas.RA.4.0.0.pack + + + Bluetooth Low Energy Library + Renesas.RA.4.0.0.pack + + + Clock Generation Circuit + Renesas.RA.4.0.0.pack + + + Cyclic Redundancy Check + Renesas.RA.4.0.0.pack + + + 12-bit D/A Converter + Renesas.RA.4.0.0.pack + + + Direct Memory Access Controller + Renesas.RA.4.0.0.pack + + + Data Transfer Controller + Renesas.RA.4.0.0.pack + + + Event Link Controller + Renesas.RA.4.0.0.pack + + + Flash Memory High Performance + Renesas.RA.4.0.0.pack + + + General PWM Timer + Renesas.RA.4.0.0.pack + + + External Interrupt + Renesas.RA.4.0.0.pack + + + I2C Master Interface + Renesas.RA.4.0.0.pack + + + I2C Slave Interface + Renesas.RA.4.0.0.pack + + + Low Power Modes + Renesas.RA.4.0.0.pack + + + Quad Serial Peripheral Interface Flash + Renesas.RA.4.0.0.pack + + + Real Time Clock + Renesas.RA.4.0.0.pack + + + Secure Cryptography Engine on RA6 Protected Mode + Renesas.RA.4.0.0.pack + + + SCI UART + Renesas.RA.4.0.0.pack + + + SD/MMC Host Interface + Renesas.RA.4.0.0.pack + + + Serial Sound Interface + Renesas.RA.4.0.0.pack + + + USB Basic + Renesas.RA.4.0.0.pack + + + USB Peripheral Communications Device Class + Renesas.RA.4.0.0.pack + + + USB Composite + Renesas.RA.4.0.0.pack + + + Watchdog Timer + Renesas.RA.4.0.0.pack + + + Serial Peripheral Interface on Serial Communications Interface + Renesas.RA.4.0.0.pack + + + Serial Peripheral Interface + Renesas.RA.4.0.0.pack + + + SCI I2C Master Interface + Renesas.RA.4.0.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/fsp_to_arduino.sh b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/fsp_to_arduino.sh new file mode 100644 index 00000000..d9dc51f4 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/fsp_to_arduino.sh @@ -0,0 +1,162 @@ +#!/bin/bash + +CORE_PATH=$(pwd -P)/../../../ +TARGET=THINGPLUS_RA6M5 + +# this part changes the makefile generated by e2studio (removing ra_gen from the build) +# then it cleans the build and re-build all again + +if ! grep -q "#\-include ra_gen\/subdir.mk" ./Debug/makefile; then + sed -i 's/-include ra_gen\/subdir.mk/#-include ra_gen\/subdir.mk/g' ./Debug/makefile + echo "not commented" +else + echo "already commented!" +fi + +mkdir -p fsp_patched +cd fsp_patched +ln -s ../../../fsp/ra/ . +cd .. + +set +e +find ra -type f | xargs -I{} cp fsp_patched/{} {} +set -e + +cd Debug +make clean +make -j$(nproc) +cd .. +echo `pwd` + + +LIBRARY=`find . | grep "\.a$"` + +echo Copying ${LIBRARY} to ${CORE_PATH}/variants/${TARGET}/libs/libfsp.a +if [ ! -d ${CORE_PATH}/variants/${TARGET}/libs ] +then + mkdir ${CORE_PATH}/variants/${TARGET}/libs +fi +cp ${LIBRARY} ${CORE_PATH}/variants/${TARGET}/libs/libfsp.a + +LINKER_SCRIPTS=`find . | grep "\.ld$"` +# cp ${LINKER_SCRIPTS} ${CORE_PATH}/variants/${TARGET}/ + +#----------------------------------------------------------------------- +# TEMPORARY CHANGE - TO BE REMOVED - used to copy temporary some genrated files +# those are the files that have been removed from the build at the beginning +# and now are copied to a temporary path (so that we can continue to build) +#------------------------------------------------------------------------ +if [ ! -d ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files ] +then + mkdir ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files +fi + +cp ./ra_gen/*.c ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/ +# no more need of the following file +if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/vector_data.c"; then + echo "removed" + rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/vector_data.c +fi +if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/elc_data.c"; then + echo "removed" + rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/elc_data.c +fi +if test -f "${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/hal_data.c"; then + echo "removed" + rm ${CORE_PATH}/variants/${TARGET}/tmp_gen_c_files/hal_data.c +fi + +#------------------------------------------------------------------------- + + +FILE_MK=`find . | grep all/subdir.mk` + +CCCOMMAND=`cat $FILE_MK | grep \$\(file | cut -f2 -d","` + +echo $CCCOMMAND + +DEFINES=() +INCLUDES=() +FLAGS=() + +OIFS=$IFS +IFS=' ' +tokens=$CCCOMMAND +for x in $tokens +do + if [[ $x == -D* ]]; then DEFINES+=( $x ); fi + if [[ $x == -I* ]]; then INCLUDES+=( $x ); fi + if [[ $x == -m* ]]; then FLAGS+=( $x ); fi + if [[ $x == -f* ]]; then FLAGS+=( $x ); fi + if [[ $x == -W* ]]; then FLAGS+=( $x ); fi +done +IFS=$OIFS + +# Clean files +rm ${CORE_PATH}/variants/${TARGET}/defines.txt +rm ${CORE_PATH}/variants/${TARGET}/includes.txt +rm ${CORE_PATH}/variants/${TARGET}/cflags.txt +rm ${CORE_PATH}/variants/${TARGET}/cxxflags.txt + +for value in "${DEFINES[@]}" +do + echo $value >> ${CORE_PATH}/variants/${TARGET}/defines.txt +done + +echo ${INCLUDES[@]} + +if [ ! -d ${CORE_PATH}/variants/${TARGET}/includes/ ] +then + mkdir ${CORE_PATH}/variants/${TARGET}/includes/ +else + rm -r ${CORE_PATH}/variants/${TARGET}/includes/* +fi + +for value in "${INCLUDES[@]}" +do + INCLUDE_PATH=`echo $value | cut -f2 -d"\"" | cut -f1 -d"\""` + echo $INCLUDE_PATH + PROJECT_FOLDER=$(pwd -P) + # temporarily, copy everything staring with "ra_" in variant/includes/ , everything with ra in core folder + if [[ $INCLUDE_PATH == */ra* ]]; then + INCLUDE_PATH_REL=`echo ${INCLUDE_PATH} | sed 's/.*ra//'` + INCLUDE_PATH_REL=ra${INCLUDE_PATH_REL} + #cp -r --parent $INCLUDE_PATH ${CORE_PATH}/variants/${TARGET}/includes/ + echo "-iwithprefixbefore/variants/${TARGET}/includes/$INCLUDE_PATH_REL" >> ${CORE_PATH}/variants/${TARGET}/includes.txt + fi + #rel_path=`echo $value | sed -e "s#-I$PWD#-iwithprefixbefore/fsp#g"` + #echo $rel_path >> ${CORE_PATH}/variants/${TARGET}/includes.txt + + # TODO: check how many include folders are generated and if it makes sense to track them manually +done + +rm -rf ${CORE_PATH}/variants/${TARGET}/includes/ra/* +rm -rf ${CORE_PATH}/variants/${TARGET}/includes/ra_gen/* + +RA_INCLUDES=`find ra/ -iname *.h` +cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/ + +RA_INCLUDES=`find ra_gen/ -iname *.h` +cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/ + +RA_INCLUDES=`find ra_cfg/ -iname *.h` +cp --parent $RA_INCLUDES ${CORE_PATH}/variants/${TARGET}/includes/ + +if test -f "${CORE_PATH}/variants/${TARGET}/elc_defines.h"; then + echo "${CORE_PATH}/variants/${TARGET}/elc_defines.h exists. -> deleting it" + rm "${CORE_PATH}/variants/${TARGET}/elc_defines.h" +fi + +ELC_TABLE=`find ra/ | grep bsp_elc.h` +ELC_ENTRIES=`cat ${ELC_TABLE} | grep "ELC_EVENT" | cut -f1 -d "="` +for entry in $ELC_ENTRIES +do + #echo "$entry" + echo "#define $entry $entry" >> ${CORE_PATH}/variants/${TARGET}/elc_defines.h +done + +for value in "${FLAGS[@]}" +do + echo $value >> ${CORE_PATH}/variants/${TARGET}/cflags.txt + echo $value >> ${CORE_PATH}/variants/${TARGET}/cxxflags.txt +done diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt new file mode 100644 index 00000000..e6f543a8 --- /dev/null +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt @@ -0,0 +1,881 @@ +FSP Configuration + Board "Custom User Board (Any Device)" + R7FA6M5AH3CFP + part_number: R7FA6M5AH3CFP + rom_size_bytes: 2097152 + ram_size_bytes: 524288 + data_flash_size_bytes: 8192 + package_style: LQFP + package_pins: 100 + + RA6M5 + series: 6 + + RA6M5 Family + Security: Exceptions: Exception Response: Non-Maskable Interrupt + Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State + Security: System Reset Request Accessibility: Secure State + Security: Exceptions: Prioritize Secure Exceptions: Disabled + Security: Cache Accessibility: Both Secure and Non-Secure State + Security: System Reset Status Accessibility: Both Secure and Non-Secure State + Security: Battery Backup Accessibility: Both Secure and Non-Secure State + Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State + Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State + Security: SRAM Accessibility: Standby RAM: Regions 7-0 are all Secure. + Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State + Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State + Startup C-Cache Line Size: 32 Bytes + OFS0 register settings: Independent WDT: Start Mode: IWDT is Disabled + OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles + OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128 + OFS0 register settings: Independent WDT: Window End Position: 0% (no window end position) + OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position) + OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled + OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby + OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode) + OFS0 register settings: WDT: Timeout Period: 16384 cycles + OFS0 register settings: WDT: Clock Frequency Division Ratio: 128 + OFS0 register settings: WDT: Window End Position: 0% (no window end position) + OFS0 register settings: WDT: Window Start Position: 100% (no window start position) + OFS0 register settings: WDT: Reset Interrupt Request: Reset + OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode + OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset + OFS1 register settings: Voltage Detection 0 Level: 2.80 V + OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset + Block Protection Settings (BPS): BPS0: + Block Protection Settings (BPS): BPS1: + Block Protection Settings (BPS): BPS2: + Permanent Block Protection Settings (PBPS): PBPS0: + Permanent Block Protection Settings (PBPS): PBPS1: + Permanent Block Protection Settings (PBPS): PBPS2: + Dual Bank Mode: Disabled + Clocks: HOCO FLL Function: Disabled + Main Oscillator Wait Time: 8163 cycles + + RA Common + Main stack size (bytes): 0x400 + Heap size (bytes): 0 + MCU Vcc (mV): 3300 + Parameter checking: Disabled + Assert Failures: Return FSP_ERR_ASSERTION + Error Log: No Error Log + Clock Registers not Reset Values during Startup: Disabled + Main Oscillator Populated: Populated + PFS Protect: Enabled + C Runtime Initialization : Enabled + Early BSP Initialization : Disabled + Main Oscillator Clock Source: Crystal or Resonator + Subclock Populated: Populated + Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode + Subclock Stabilization Time (ms): 1000 + + Clocks + XTAL 24000000Hz + HOCO 20MHz + PLL Src: XTAL + PLL Div /3 + PLL Mul x25.0 + PLL2 Src: XTAL + PLL2 Div /2 + PLL2 Mul x20.0 + Clock Src: PLL + CLKOUT Disabled + UCLK Src: PLL2 + OCTASPICLK Disabled + CANFDCLK Disabled + ICLK Div /1 + PCLKA Div /2 + PCLKB Div /4 + PCLKC Div /4 + PCLKD Div /2 + BCLK Div /2 + BCLK/2 + FCLK Div /4 + CLKOUT Div /1 + UCLK Div /5 + OCTASPICLK Div /1 + CANFDCLK Div /6 + + Pin Configurations + R7FA6M5AH3CFP.pincfg -> g_bsp_pin_cfg + AVCC0 88 ANALOG0_AVCC0 - - - - - - - - IO "Read only" - + AVSS0 89 ANALOG0_AVSS0 - - - - - - - - IO "Read only" - + P000 100 - - - - Disabled - - "ADC0: AN000; ADC1: AN100; ICU0: IRQ06" - None - - + P001 99 - - - - Disabled - - "ADC0: AN001; ADC1: AN101; ICU0: IRQ07" - None - - + P002 98 - - - - Disabled - - "ADC0: AN002; ADC1: AN102; ICU0: IRQ08" - None - - + P003 97 - - - - Disabled - - "ADC0: AN003" - None - - + P004 96 - - - - Disabled - - "ADC0: AN004; ICU0: IRQ09" - None - - + P005 95 - - - - Disabled - - "ADC0: AN005; ICU0: IRQ10" - None - - + P006 94 - - - - Disabled - - "ADC0: AN006; ICU0: IRQ11" - None - - + P007 93 - - - - Disabled - - "ADC0: AN007" - None - - + P008 92 - - - - Disabled - - "ADC0: AN008; ICU0: IRQ12" - None - - + P014 85 DAC0_DA0 - - - "Analog mode" - None "ADC0: AN012; DAC0: DA0" - IO - - + P015 84 DAC1_DA1 - - - "Analog mode" - None "ADC0: AN013; DAC1: DA1; ICU0: IRQ13" - IO - - + P100 75 QSPI0_QSPCLK - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; BUS_ASYNCH0: D00; GPT_POEG0: GTETRGA; GPT5: GTIOC5B; ICU0: IRQ02; OSPI0: OMSCLK; QSPI0: QSPCLK; SCI0: RXD0; SCI0: SCL0; SCI1: SCK1; SPI1: MISOB" - IO - - + P101 74 QSPI0_QIO1 - Low None "Peripheral mode" CMOS None "AGT0: AGTEE0; BUS_ASYNCH0: D01; GPT_POEG1: GTETRGB; GPT5: GTIOC5A; ICU0: IRQ01; OSPI0: OMSIO7; QSPI0: QIO1; SCI0: SDA0; SCI0: TXD0; SCI1: CTSRTS1; SPI1: MOSIB" - IO - - + P102 73 QSPI0_QIO0 - Low - "Peripheral mode" CMOS None "ADC0: ADTRG0; AGT0: AGTO0; BUS_ASYNCH0: D02; CAN0: CRX0; GPT_OPS0: GTOWLO; GPT2: GTIOC2B; OSPI0: OMSIO1; QSPI0: QIO0; SCI0: SCK0; SPI1: RSPCKB" - IO - - + P103 72 QSPI0_QIO3 - Low - "Peripheral mode" CMOS None "AGT2: AGTIO2; BUS_ASYNCH0: D03; CAN0: CTX0; GPT_OPS0: GTOWUP; GPT2: GTIOC2A; OSPI0: OMSIO6; QSPI0: QIO3; SCI0: CTSRTS0; SPI1: SSLB0" - IO - - + P104 71 QSPI0_QIO2 - Low None "Peripheral mode" CMOS None "AGT2: AGTEE2; BUS_ASYNCH0: D04; GPT_POEG1: GTETRGB; GPT1: GTIOC1B; ICU0: IRQ01; OSPI0: OMDQS; QSPI0: QIO2; SCI8: RXD8; SCI8: SCL8; SPI1: SSLB1" - IO - - + P105 70 - - - - Disabled - - "AGT2: AGTO2; BUS_ASYNCH0: D05; GPT_POEG0: GTETRGA; GPT1: GTIOC1A; ICU0: IRQ00; OSPI0: OMSIO5; SCI8: SDA8; SCI8: TXD8; SPI1: SSLB2" - None - - + P106 69 - - - - Disabled - - "AGT0: AGTOB0; BUS_ASYNCH0: D06; GPT8: GTIOC8B; OSPI0: OMSIO0; SCI8: SCK8; SPI1: SSLB3" - None - - + P107 68 - - - - Disabled - - "AGT0: AGTOA0; BUS_ASYNCH0: D07; GPT8: GTIOC8A; OSPI0: OMSIO3; SCI8: CTSRTS8" - None - - + P108 51 DEBUG0_SWDIO - Low - "Peripheral mode" CMOS None "AGT3: AGTOA3; DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOC0B; SCI9: CTSRTS9; SPI0: SSLA0" - IO - - + P109 52 DEBUG0_TRACESWO - Low - "Peripheral mode" CMOS None "AGT3: AGTOB3; CAN1: CTX1; CGC0: CLKOUT; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOC1A; SCI9: SDA9; SCI9: TXD9; SPI0: MOSIA" - IO - - + P110 53 SPI0_MISOA - Low None "Peripheral mode" CMOS None "AGT3: AGTEE3; CAN1: CRX1; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOC1B; ICU0: IRQ03; SCI2: CTSRTS2; SCI9: RXD9; SCI9: SCL9; SPI0: MISOA" - IO - - + P111 54 SPI0_RSPCKA - Low None "Peripheral mode" CMOS None "AGT5: AGTOA5; BUS_ASYNCH0: A05; GPT3: GTIOC3A; ICU0: IRQ04; SCI2: SCK2; SCI9: SCK9; SPI0: RSPCKA" - IO - - + P112 55 SPI0_SSLA0 - Low - "Peripheral mode" CMOS None "AGT5: AGTOB5; BUS_ASYNCH0: A04; GPT3: GTIOC3B; OSPI0: OMCS1; QSPI0: QSSL; SCI1: SCK1; SCI2: SDA2; SCI2: TXD2; SPI0: SSLA0; SSI0: SSIBCK0" - IO - - + P113 56 - - - - Disabled - - "AGT5: AGTEE5; BUS_ASYNCH0: A03; GPT2: GTIOC2A; SCI2: RXD2; SCI2: SCL2; SSI0: SSILRCK0" - None - - + P114 57 - - - - Disabled - - "AGT5: AGTIO5; BUS_ASYNCH0: A02; GPT2: GTIOC2B; SCI9: CTS9; SSI0: SSIRXD0" - None - - + P115 58 - - - - Disabled - - "BUS_ASYNCH0: A01; GPT4: GTIOC4A; SSI0: SSITXD0" - None - - + P200 40 ICU0_NMI - - NMI "IRQ mode" - None "ICU0: NMI" - IO - - + P201 39 SYSTEM0_MD - - - "Peripheral mode" - - "SYSTEM0: MD" - IO - - + P205 32 SDHI0_SD0DAT3 - Low None "Peripheral mode" CMOS None "AGT1: AGTO1; BUS_ASYNCH0: A16; CGC0: CLKOUT; CTSU0: TS01; ETHERC_MII0: ET0_WOL; ETHERC_RMII0: ET0_WOL; GPT_OPS0: GTIV; GPT4: GTIOC4A; ICU0: IRQ01; IIC1: SCL1; SCI4: SDA4; SCI4: TXD4; SCI9: CTSRTS9; SDHI0: SD0DAT3; SPI0: SSLA0; SSI0: SSILRCK0; USB_FS0: USB_OVRCURA" - IO - - + P206 31 SDHI0_SD0DAT2 - Low None "Peripheral mode" CMOS None "BUS_ASYNCH0: WAIT; CEC0: CECIO; CTSU0: TS02; ETHERC_MII0: ET0_LINKSTA; ETHERC_RMII0: ET0_LINKSTA; GPT_OPS0: GTIU; ICU0: IRQ00; IIC1: SDA1; SCI4: RXD4; SCI4: SCL4; SCI9: CTS9; SDHI0: SD0DAT2; SPI0: SSLA1; SSI0: SSIDATA0; USB_FS0: USB_VBUSEN" - IO - - + P207 30 - - - - Disabled - - "BUS_ASYNCH0: A17; CTSU0: TSCAP; QSPI0: QSSL; SCI4: SDA4; SCI4: TXD4; SPI0: SSLA2" - None - - + P208 37 SDHI0_SD0DAT0 - Low - "Peripheral mode" CMOS None "BUS_ASYNCH0: CS4; DEBUG_TRACE0: TDATA3; ETHERC_MII0: ET0_LINKSTA; ETHERC_RMII0: ET0_LINKSTA; GPT_OPS0: GTOVLO; QSPI0: QIO3; SDHI0: SD0DAT0" - IO - - + P209 36 - - - - Disabled - - "AGT5: AGTEE5; BUS_ASYNCH0: CS5; DEBUG_TRACE0: TDATA2; ETHERC_MII0: ET0_EXOUT; ETHERC_RMII0: ET0_EXOUT; GPT_OPS0: GTOVUP; QSPI0: QIO2; SDHI0: SD0WP" - None - - + P210 35 SDHI0_SD0CD - Low - "Peripheral mode" CMOS None "AGT5: AGTOB5; BUS_ASYNCH0: CS6; DEBUG_TRACE0: TDATA1; ETHERC_MII0: ET0_WOL; ETHERC_RMII0: ET0_WOL; GPT_OPS0: GTIW; QSPI0: QIO1; SDHI0: SD0CD" - IO - - + P211 34 SDHI0_SD0CMD - Low - "Peripheral mode" CMOS None "AGT5: AGTOA5; BUS_ASYNCH0: CS7; DEBUG_TRACE0: TDATA0; ETHERC_MII0: ET0_MDIO; ETHERC_RMII0: ET0_MDIO; GPT_OPS0: GTIV; QSPI0: QIO0; SDHI0: SD0CMD" - IO - - + P212 14 CGC0_EXTAL - Low None "Peripheral mode" CMOS None "AGT1: AGTEE1; CGC0: EXTAL; GPT_POEG3: GTETRGD; GPT0: GTIOC0B; ICU0: IRQ03; SCI1: RXD1; SCI1: SCL1" - IO - - + P213 13 CGC0_XTAL - Low None "Peripheral mode" CMOS None "ADC1: ADTRG1; AGT2: AGTEE2; CGC0: XTAL; GPT_POEG2: GTETRGC; GPT0: GTIOC0A; ICU0: IRQ02; SCI1: SDA1; SCI1: TXD1" - IO - - + P214 33 SDHI0_SD0CLK - Low - "Peripheral mode" CMOS None "AGT5: AGTO5; DEBUG_TRACE0: TCLK; ETHERC_MII0: ET0_MDC; ETHERC_RMII0: ET0_MDC; GPT_OPS0: GTIU; QSPI0: QSPCLK; SDHI0: SD0CLK" - IO - - + P300 50 DEBUG0_SWCLK - Low - "Peripheral mode" CMOS None "DEBUG0: SWCLK; DEBUG0: TCK; GPT_OPS0: GTOUUP; GPT0: GTIOC0A; SPI0: SSLA1" - IO - - + P301 49 SCI9_CTSRTS9 - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; BUS_ASYNCH0: A06; GPT_OPS0: GTOULO; GPT4: GTIOC4B; ICU0: IRQ06; SCI2: RXD2; SCI2: SCL2; SCI9: CTSRTS9; SPI0: SSLA2" - IO - - + P302 48 - - - - Disabled - - "BUS_ASYNCH0: A07; GPT_OPS0: GTOUUP; GPT4: GTIOC4A; ICU0: IRQ05; SCI2: SDA2; SCI2: TXD2; SPI0: SSLA3" - None - - + P303 47 SCI9_CTS9 - Low - "Peripheral mode" CMOS None "BUS_ASYNCH0: A08; GPT7: GTIOC7B; SCI9: CTS9" - IO - - + P304 44 - - - - Disabled - - "AGT2: AGTEE2; BUS_ASYNCH0: A09; GPT_OPS0: GTOWLO; GPT7: GTIOC7A; ICU0: IRQ09; SCI6: RXD6; SCI6: SCL6" - None - - + P305 43 - - - - Disabled - - "AGT2: AGTOB2; BUS_ASYNCH0: A10; GPT_OPS0: GTOWUP; ICU0: IRQ08; QSPI0: QSPCLK; SCI6: SDA6; SCI6: TXD6" - None - - + P306 42 - - - - Disabled - - "AGT2: AGTOA2; BUS_ASYNCH0: A11; GPT_OPS0: GTOULO; QSPI0: QSSL; SCI6: SCK6" - None - - + P307 41 - - - - Disabled - - "AGT4: AGTEE4; BUS_ASYNCH0: A12; GPT_OPS0: GTOUUP; QSPI0: QIO0; SCI6: CTSRTS6" - None - - + P400 1 IIC0_SCL0 - Medium None "Peripheral mode" CMOS None "ADC1: ADTRG1; AGT1: AGTIO1; ETHERC_MII0: ET0_WOL; ETHERC_RMII0: ET0_WOL; GPT6: GTIOC6A; ICU0: IRQ00; IIC0: SCL0; SCI4: SCK4; SCI7: SCK7; SSI_COMMON0: AUDIO_CLK" - IO - - + P401 2 IIC0_SDA0 - Medium None "Peripheral mode" CMOS None "CAN0: CTX0; ETHERC_MII0: ET0_MDC; ETHERC_RMII0: ET0_MDC; GPT_POEG0: GTETRGA; GPT6: GTIOC6B; ICU0: IRQ05; IIC0: SDA0; SCI4: CTSRTS4; SCI7: SDA7; SCI7: TXD7" - IO - - + P402 3 SSI_COMMON0_AUDIO_CLK - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; CAC0: CACREF; CAN0: CRX0; ETHERC_MII0: ET0_MDIO; ETHERC_RMII0: ET0_MDIO; ICU0: IRQ04; RTC0: RTCIC0; SCI4: CTS4; SCI7: RXD7; SCI7: SCL7; SSI_COMMON0: AUDIO_CLK" - IO - - + P403 4 SSI0_SSIBCK0 - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; ETHERC_MII0: ET0_LINKSTA; ETHERC_RMII0: ET0_LINKSTA; GPT3: GTIOC3A; ICU0: IRQ14; RTC0: RTCIC1; SCI7: CTSRTS7; SSI0: SSIBCK0" - IO - - + P404 5 SSI0_SSILRCK0 - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; ETHERC_MII0: ET0_EXOUT; ETHERC_RMII0: ET0_EXOUT; GPT3: GTIOC3B; ICU0: IRQ15; RTC0: RTCIC2; SCI7: CTS7; SSI0: SSILRCK0" - IO - - + P405 6 SSI0_SSITXD0 - Low - "Peripheral mode" CMOS None "ETHERC_MII0: ET0_TX_EN; ETHERC_RMII0: RMII_TXD_EN; GPT1: GTIOC1A; SSI0: SSITXD0" - IO - - + P406 7 SSI0_SSIRXD0 - Low - "Peripheral mode" CMOS None "AGT5: AGTO5; ETHERC_MII0: ET0_RX_ER; ETHERC_RMII0: RMII_TXD1; GPT1: GTIOC1B; SPI0: SSLA3; SSI0: SSIRXD0" - IO - - + P407 25 USB_FS0_USB_VBUS - Low - "Peripheral mode" CMOS None "ADC0: ADTRG0; AGT0: AGTIO0; CTSU0: TS03; ETHERC_MII0: ET0_EXOUT; ETHERC_RMII0: ET0_EXOUT; GPT6: GTIOC6A; IIC0: SDA0; RTC0: RTCOUT; SCI4: CTSRTS4; SPI0: SSLA3; USB_FS0: USB_VBUS" - IO - - + P408 24 SCI3_RXD3 - Low None "Peripheral mode" CMOS None "AGT2: AGTOB2; CTSU0: TS04; ETHERC_MII0: ET0_CRS; ETHERC_RMII0: RMII_CRS_DV; GPT_OPS0: GTOWLO; GPT6: GTIOC6B; ICU0: IRQ07; IIC0: SCL0; SCI3: RXD3; SCI3: SCL3; SCI4: CTS4; USB_FS0: USB_ID; USB_HS0: USBHS_ID" - IO - - + P409 23 SCI3_TXD3 - Low None "Peripheral mode" CMOS None "AGT2: AGTOA2; CTSU0: TS05; ETHERC_MII0: ET0_RX_CLK; ETHERC_RMII0: RMII_RX_ER; GPT_OPS0: GTOWUP; ICU0: IRQ06; IIC2: SDA2; SCI3: SDA3; SCI3: TXD3; USB_FS0: USB_EXICEN; USB_HS0: USBHS_EXICEN" - IO - - + P410 22 SDHI0_SD0DAT1 - Low None "Peripheral mode" CMOS None "AGT1: AGTOB1; CTSU0: TS06; ETHERC_MII0: ET0_ERXD0; ETHERC_RMII0: RMII_RXD1; GPT_OPS0: GTOVLO; GPT9: GTIOC9B; ICU0: IRQ05; IIC2: SCL2; SCI0: RXD0; SCI0: SCL0; SCI3: SCK3; SDHI0: SD0DAT1; SPI1: MISOB" - IO - - + P411 21 - - - - Disabled - - "AGT1: AGTOA1; CTSU0: TS07; ETHERC_MII0: ET0_ERXD1; ETHERC_RMII0: RMII_RXD0; GPT_OPS0: GTOVUP; GPT9: GTIOC9A; ICU0: IRQ04; SCI0: SDA0; SCI0: TXD0; SCI3: CTSRTS3; SDHI0: SD0DAT0; SPI1: MOSIB" - None - - + P412 20 - - - - Disabled - - "AGT1: AGTEE1; CTSU0: TS08; ETHERC_MII0: ET0_ETXD0; ETHERC_RMII0: REF50CK; GPT_OPS0: GTOULO; SCI0: SCK0; SCI3: CTS3; SDHI0: SD0CMD; SPI1: RSPCKB" - None - - + P413 19 - - - - Disabled - - "AGT3: AGTEE3; CTSU0: TS09; ETHERC_MII0: ET0_ETXD1; ETHERC_RMII0: RMII_TXD0; GPT_OPS0: GTOUUP; SCI0: CTSRTS0; SDHI0: SD0CLK; SPI1: SSLB0" - None - - + P414 18 - - - - Disabled - - "AGT5: AGTIO5; CTSU0: TS10; ETHERC_MII0: ET0_RX_ER; ETHERC_RMII0: RMII_TXD1; GPT0: GTIOC0B; ICU0: IRQ09; IIC2: SDA2; SCI0: CTS0; SDHI0: SD0WP; SPI1: SSLB1" - None - - + P415 17 - - - - Disabled - - "AGT4: AGTIO4; CTSU0: TS11; ETHERC_MII0: ET0_TX_EN; ETHERC_RMII0: RMII_TXD_EN; GPT0: GTIOC0A; ICU0: IRQ08; IIC2: SCL2; SDHI0: SD0CD; SPI1: SSLB2; USB_FS0: USB_VBUSEN" - None - - + P500 76 - - - - Disabled - - "ADC1: AN116; AGT0: AGTOA0; CAC0: CACREF; GPT_OPS0: GTIU; QSPI0: QSPCLK; SCI5: CTS5; USB_FS0: USB_VBUSEN" - None - - + P501 77 QSPI0_QSSL - Low None "Peripheral mode" CMOS None "ADC1: AN117; AGT0: AGTOB0; GPT_OPS0: GTIV; ICU0: IRQ11; QSPI0: QSSL; SCI5: SDA5; SCI5: TXD5; USB_FS0: USB_OVRCURA" - IO - - + P502 78 ADC1_AN118 - - - "Analog mode" - None "ADC1: AN118; AGT2: AGTOA2; GPT_OPS0: GTIW; ICU0: IRQ12; QSPI0: QIO0; SCI5: RXD5; SCI5: SCL5; SCI6: CTS6; USB_FS0: USB_OVRCURB" - IO - - + P503 79 ADC1_AN119 - - - "Analog mode" - None "ADC1: AN119; AGT2: AGTOB2; GPT_POEG2: GTETRGC; QSPI0: QIO1; SCI5: SCK5; SCI6: CTSRTS6; USB_FS0: USB_EXICEN" - IO - - + P504 80 ADC1_AN120 - - - "Analog mode" - None "ADC1: AN120; AGT3: AGTOA3; BUS_ASYNCH0: ALE; GPT_POEG3: GTETRGD; QSPI0: QIO2; SCI5: CTSRTS5; SCI6: SCK6; USB_FS0: USB_ID" - IO - - + P505 81 ADC1_AN121 - - - "Analog mode" - None "ADC1: AN121; AGT3: AGTOB3; ICU0: IRQ14; QSPI0: QIO3; SCI6: RXD6; SCI6: SCL6" - IO - - + P600 67 - - - - Disabled - - "AGT3: AGTIO3; BUS_ASYNCH0: RD; CAC0: CACREF; CGC0: CLKOUT; GPT6: GTIOC6B; OSPI0: OMSIO4; SCI9: SCK9" - None - - + P601 66 SCI9_RXD9 - Low - "Peripheral mode" CMOS None "AGT3: AGTEE3; BUS_ASYNCH0: WR; GPT6: GTIOC6A; OSPI0: OMSIO2; SCI9: RXD9; SCI9: SCL9" - IO - - + P602 65 SCI9_TXD9 - Low - "Peripheral mode" CMOS None "AGT3: AGTO3; BUS_ASYNCH0: EBCLK; GPT7: GTIOC7B; OSPI0: OMCS1; SCI9: SDA9; SCI9: TXD9" - IO - - + P608 59 - - - - Disabled - - "BUS_ASYNCH0: A00; GPT4: GTIOC4B" - None - - + P609 60 - - - - Disabled - - "AGT5: AGTO5; BUS_ASYNCH0: CS1; CAN1: CTX1; GPT5: GTIOC5A" - None - - + P610 61 - - - - Disabled - - "AGT4: AGTO4; BUS_ASYNCH0: CS0; CAN1: CRX1; GPT5: GTIOC5B; OSPI0: OMCS0; SCI7: CTS7" - None - - + P708 16 - - - - Disabled - - "CAC0: CACREF; CEC0: CECIO; CTSU0: TS12; ETHERC_MII0: ET0_ETXD3; ICU0: IRQ11; SCI1: RXD1; SCI1: SCL1; SPI1: SSLB3; SSI_COMMON0: AUDIO_CLK" - None - - + RES 38 SYSTEM0_RES - - - - - - - - IO "Read only" - + USBDM 27 USB_FS0_USB_DM - - - - - - - - IO "Read only" - + USBDP 28 USB_FS0_USB_DP - - - - - - - - IO "Read only" - + VBATT 8 SYSTEM0_VBATT - - - - - - - - IO "Read only" - + VCC 15 SYSTEM0_VCC - - - - - - - - IO "Read only" - + VCC 46 SYSTEM0_VCC - - - - - - - - IO "Read only" - + VCC 62 SYSTEM0_VCC - - - - - - - - IO "Read only" - + VCC 82 SYSTEM0_VCC - - - - - - - - IO "Read only" - + VCCUSB 29 USB_FS0_VCC_USB - - - - - - - - IO "Read only" - + VCL 64 SYSTEM0_VCL - - - - - - - - IO "Read only" - + VCL0 9 SYSTEM0_VCL0 - - - - - - - - IO "Read only" - + VREFH 87 ANALOG0_VREFH - - - - - - - - IO "Read only" - + VREFH0 91 ANALOG0_VREFH0 - - - - - - - - IO "Read only" - + VREFL 86 ANALOG0_VREFL - - - - - - - - IO "Read only" - + VREFL0 90 ANALOG0_VREFL0 - - - - - - - - IO "Read only" - + VSS 12 SYSTEM0_VSS - - - - - - - - IO "Read only" - + VSS 45 SYSTEM0_VSS - - - - - - - - IO "Read only" - + VSS 63 SYSTEM0_VSS - - - - - - - - IO "Read only" - + VSS 83 SYSTEM0_VSS - - - - - - - - IO "Read only" - + VSSUSB 26 USB_FS0_VSS_USB - - - - - - - - IO "Read only" - + XCIN 10 CGC0_XCIN - - - - - - - - IO "Read only" - + XCOUT 11 CGC0_XCOUT - - - - - - - - IO "Read only" - + + User Events + + User Event Links + + Module "I/O Port (r_ioport)" + Parameter Checking: Default (BSP) + + Module "ADC (r_adc)" + Parameter Checking: Default (BSP) + + Module "DAC (r_dac)" + Parameter Checking: Default (BSP) + + Module "I2C Master (r_iic_master)" + Parameter Checking: Default (BSP) + DTC on Transmission and Reception: Enabled + 10-bit slave addressing: Disabled + + Module "I2C Slave (r_iic_slave)" + Parameter Checking: Default (BSP) + + Module "I2S (r_ssi)" + Parameter Checking: Default (BSP) + DTC Support: Enabled + + Module "Transfer (r_dtc)" + Parameter Checking: Default (BSP) + Linker section to keep DTC vector table: .fsp_dtc_vector_table + + Module "UART (r_sci_uart)" + Parameter Checking: Default (BSP) + FIFO Support: Disable + DTC Support: Enable + Flow Control Support: Disable + RS-485 Support: Disable + + Module "USB Composite (r_usb_composite)" + Module "USB PCDC (r_usb_pcdc)" + Bulk In Pipe: USB PIPE1 + Bulk Out Pipe: USB PIPE2 + Interrupt Out Pipe: USB PIPE6 + + Module "USB (r_usb_basic)" + Parameter Checking: Default (BSP) + PLL Frequency: 24MHz + CPU Bus Access Wait Cycles: 9 cycles + Battery Charging: Enabled + Power IC Shutdown Polarity: Active High + Dedicated Charging Port (DCP) Mode: Disabled + Notifications for SET_INTERFACE/SET_FEATURE/CLEAR_FEATURE: Enabled + Double Buffering: Enabled + Continuous Transfer Mode: Disabled + LDO Regulator: Not Supported + DMA Support: Disabled + DMA Source Address: DMA Disabled + DMA Destination Address: DMA Disabled + USB Compliance Test mode: Disabled + USB TPL table name: NULL + + Module "External IRQ (r_icu)" + Parameter Checking: Default (BSP) + + Module "CRC (r_crc)" + Parameter Checking: Default (BSP) + + Module "Low Power Modes (r_lpm)" + Parameter Checking: Default (BSP) + Standby Limit: Disabled + + Module "SCE Protected Mode" + RSA: RSA key generation retry count: 10240 + Hash: SHA-384: User Implementation (Software): Disabled + Hash: SHA-384: User Implementation Function: crypto_sha384_user_function + + Module "QSPI (r_qspi)" + Parameter Checking: Default (BSP) + Support Multiple Line Program in Extended SPI Mode: Disabled + + Module "SD/MMC (r_sdhi)" + Parameter Checking: Default (BSP) + Unaligned Access Support: Enabled + SD Support: Enabled + eMMC Support: Disabled + + Module "Clock Generation Circuit (r_cgc)" + Parameter Checking: Default (BSP) + + Module "Event Link Controller (r_elc)" + Parameter Checking: Default (BSP) + + Module "Realtime Clock (r_rtc)" + Parameter Checking: Default (BSP) + Set Source Clock in Open: Enabled + + Module "Flash (r_flash_hp)" + Parameter Checking: Default (BSP) + Code Flash Programming Enable: Enabled + Data Flash Programming Enable: Enabled + + Module "Watchdog (r_wdt)" + Parameter Checking: Default (BSP) + Register Start NMI Support: Disabled + + Module "SPI (r_spi)" + Parameter Checking: Default (BSP) + Enable Support for using a transfer API: Enabled + Enable Transmitting from RXI Interrupt: Disabled + + Module "SPI (r_sci_spi)" + Parameter Checking: Default (BSP) + DTC Support: Enabled + + Module "Transfer (r_dmac)" + Parameter Checking: Default (BSP) + + Module "Timer, General PWM (r_gpt)" + Parameter Checking: Default (BSP) + Pin Output Support: Enabled with Extra Features + Write Protect Enable: Disabled + Clock Source: PCLKD + + Module "Timer, Low-Power (r_agt)" + Parameter Checking: Default (BSP) + Pin Output Support: Enabled + Pin Input Support: Disabled + + Module "I2C Master (r_sci_i2c)" + Parameter Checking: Default (BSP) + DTC on Transmission and Reception: Disabled + 10-bit slave addressing: Disabled + + HAL + Instance "g_ioport I/O Port (r_ioport)" + Name: g_ioport + Port 1 ELC Trigger Source: Disabled + Port 2 ELC Trigger Source: Disabled + Port 3 ELC Trigger Source: Disabled + Port 4 ELC Trigger Source: Disabled + Port B ELC Trigger Source: Disabled + Port C ELC Trigger Source: Disabled + Port D ELC Trigger Source: Disabled + Port E ELC Trigger Source: Disabled + Pin Configuration Name: g_bsp_pin_cfg + + Instance "g_adc0 ADC (r_adc)" + General: Name: g_adc0 + General: Unit: 0 + General: Resolution: 12-Bit + General: Alignment: Right + General: Clear after read: On + General: Mode: Single Scan + General: Double-trigger: Disabled + Input: Channel Scan Mask (channel availability varies by MCU): + Input: Group B Scan Mask (channel availability varies by MCU): + Interrupts: Normal/Group A Trigger: Software + Interrupts: Group B Trigger: Disabled + Interrupts: Group Priority (Valid only in Group Scan Mode): Group A cannot interrupt Group B + Input: Add/Average Count: Disabled + Input: Reference Voltage control: VREFH0/VREFH + Input: Addition/Averaging Mask (channel availability varies by MCU and unit): + Input: Sample and Hold: Sample and Hold Channels (Available only on selected MCUs): + Input: Sample and Hold: Sample Hold States (Applies only to channels 0, 1, 2): 24 + Input: Window Compare: Window Mode: Disabled + Input: Window Compare: Event Output: OR + Input: Window Compare: Window A: Enable: Disabled + Input: Window Compare: Window A: Channels to compare (channel availability varies by MCU and unit): + Input: Window Compare: Window A: Channel comparison mode (channel availability varies by MCU and unit): + Input: Window Compare: Window A: Lower Reference: 0 + Input: Window Compare: Window A: Upper Reference: 0 + Input: Window Compare: Window B: Enable: Disabled + Input: Window Compare: Window B: Channel to compare (channel availability varies by MCU and unit): Channel 0 + Input: Window Compare: Window B: Comparison mode: Less Than or Outside Window + Input: Window Compare: Window B: Lower Reference: 0 + Input: Window Compare: Window B: Upper Reference: 0 + Interrupts: Callback: NULL + Interrupts: Scan End Interrupt Priority: Disabled + Interrupts: Scan End Group B Interrupt Priority: Disabled + Interrupts: Window Compare A Interrupt Priority: Disabled + Interrupts: Window Compare B Interrupt Priority: Disabled + Extra: ADC Ring Buffer: Disabled + + Instance "g_dac0 DAC (r_dac)" + Name: g_dac0 + Channel: 0 + Synchronize with ADC: Disabled + Data Format: Right Justified + Output Amplifier: Disabled + Charge Pump (Requires MOCO active): Disabled + Internal Output: Enabled by default + ELC Trigger Source: Disabled + + Instance "g_i2c_master0 I2C Master (r_iic_master)" + Name: g_i2c_master0 + Channel: 0 + Rate: Fast-mode + Rise Time (ns): 120 + Fall Time (ns): 120 + Duty Cycle (%): 50 + Slave Address: 0x00 + Address Mode: 7-Bit + Timeout Mode: Short Mode + Timeout during SCL Low: Enabled + Callback: NULL + Interrupt Priority Level: Priority 12 + + Instance "g_i2c_slave0 I2C Slave (r_iic_slave)" + Name: g_i2c_slave0 + Channel: 0 + Rate: Standard + Internal Reference Clock: PCLKB / 1 + Digital Noise Filter Stage Select: 3-stage filter + Slave Address: 0x08 + General Call: Disabled + Address Mode: 7-Bit + Clock Stretching: Disabled + Callback: NULL + Interrupt Priority Level: Transmit, Receive, and Transmit End: Priority 12 + Interrupt Priority Level: Error: Priority 12 + + Instance "g_i2s0 I2S (r_ssi)" + Name: g_i2s0 + Channel: 0 + Operating Mode (Master/Slave): Master Mode + Bit Depth: 16 Bits + Word Length: 16 Bits + WS Continue Mode: Disabled + Bit Clock Source: External AUDIO_CLK + Bit Clock Divider: Audio Clock / 1 + Callback: NULL + Transmit Interrupt Priority: Priority 2 + Receive Interrupt Priority: Disabled + Idle/Error Interrupt Priority: Priority 2 + + Instance "g_transfer0 Transfer (r_dtc) SSI0 TXI (Transmit data empty)" + Name: g_transfer0 + Mode: Block + Transfer Size: 4 Bytes + Destination Address Mode: Fixed + Source Address Mode: Incremented + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SSI0 TXI (Transmit data empty) + + Instance "g_uart0 UART (r_sci_uart)" + General: Name: g_uart0 + General: Channel: 3 + General: Data Bits: 8bits + General: Parity: None + General: Stop Bits: 1bit + Baud: Baud Rate: 115200 + Baud: Baud Rate Modulation: Disabled + Baud: Max Error (%): 5 + Flow Control: CTS/RTS Selection: Hardware RTS + Flow Control: Software RTS Port: Disabled + Flow Control: Software RTS Pin: Disabled + Extra: Clock Source: Internal Clock + Extra: Start bit detection: Falling Edge + Extra: Noise Filter: Disable + Extra: Receive FIFO Trigger Level: Max + Extra: RS-485: DE Pin: Disable + Extra: RS-485: DE Pin Polarity: Active High + Extra: RS-485: DE Port Number: Disabled + Extra: RS-485: DE Pin Number: Disabled + Interrupts: Callback: NULL + Interrupts: Receive Interrupt Priority: Priority 12 + Interrupts: Transmit Data Empty Interrupt Priority: Priority 12 + Interrupts: Transmit End Interrupt Priority: Priority 12 + Interrupts: Error Interrupt Priority: Priority 12 + + Instance "g_r_usb_composite0 USB Composite (r_usb_composite)" + Name: g_r_usb_composite0 + + Instance "g_pcdc0 USB PCDC (r_usb_pcdc)" + Name: g_pcdc0 + + Instance "g_basic0 USB (r_usb_basic)" + Name: g_basic0 + USB Mode: Peri mode + USB Speed: Full Speed + USB Module Number: USB_IP0 Port + USB Device Class: Peripheral Communications Device Class + USB Descriptor: g_usb_descriptor + USB Compliance Callback: NULL + USBFS Interrupt Priority: Priority 12 + USBFS Resume Priority: Priority 12 + USBFS D0FIFO Interrupt Priority: Priority 12 + USBFS D1FIFO Interrupt Priority: Priority 12 + USBHS Interrupt Priority: Priority 12 + USBHS D0FIFO Interrupt Priority: Priority 12 + USBHS D1FIFO Interrupt Priority: Priority 12 + USB RTOS Callback: NULL + USB Callback Context: NULL + + Instance "g_external_irq0 External IRQ (r_icu)" + Name: g_external_irq0 + Channel: 0 + Trigger: Rising + Digital Filtering: Disabled + Digital Filtering Sample Clock (Only valid when Digital Filtering is Enabled): PCLK / 64 + Callback: NULL + Pin Interrupt Priority: Priority 12 + + Instance "g_crc0 CRC (r_crc)" + Name: g_crc0 + CRC Polynomial: CRC-32C + Bit Order: MSB + Snoop Address: NONE + + Instance "g_lpm0 Low Power Modes (r_lpm)" + General: Name: g_lpm0 + General: Low Power Mode: Sleep mode + General: Output port state in standby and deep standby: No change + Standby Options: Wake Sources: + Standby Options: Snooze Request Source: RXD0 falling edge + Standby Options: Snooze End Sources: + Standby Options: DTC state in Snooze Mode: Disabled + Standby Options: Snooze Cancel Source: None + Deep Standby Options: I/O Port Retention: Maintain the IO port states + Deep Standby Options: Power-Supply Control: Supply power to the Standby SRAM, low-speed on-chip oscillator, AGTn (n = 0-3) and USBFS/HS resume detecting unit + Deep Standby Options: Cancel Sources: + Deep Standby Options: Cancel Edges: + + Instance "SCE Protected Mode" + General: Name: sce + + Instance "g_qspi0 QSPI (r_qspi)" + General: Name: g_qspi0 + General: SPI Protocol: QPI + General: Address Bytes: 3 + General: Read Mode: Fast Read Quad I/O + General: Dummy Clocks for Fast Read: 8 + General: Page Size Bytes: 256 + Command Definitions: Page Program Command: 0x02 + Command Definitions: Page Program Address Lines: 1 + Command Definitions: Write Enable Command: 0x06 + Command Definitions: Status Command: 0x05 + Command Definitions: Write Status Bit: 0 + Command Definitions: Sector Erase Command: 0x20 + Command Definitions: Sector Erase Size: 4096 + Command Definitions: Block Erase Command: 0xD8 + Command Definitions: Block Erase Size: 65536 + Command Definitions: Block Erase 32KB Command: 0x52 + Command Definitions: Block Erase 32KB Size: 32768 + Command Definitions: Chip Erase Command: 0xC7 + Command Definitions: XIP Enter M7-M0: 0xFF + Command Definitions: XIP Exit M7-M0: 0xFF + Bus Timing: QSPKCLK Divisor: 2 + Bus Timing: Minimum QSSL Deselect Cycles: 2 QSPCLK + + Instance "g_sdmmc0 SD/MMC (r_sdhi)" + Name: g_sdmmc0 + Channel: 0 + Bus Width: 4 Bits + Block Size: 512 + Card Detection: CD Pin + Write Protection: Not Used + Callback: NULL + Access Interrupt Priority: Priority 12 + Card Interrupt Priority: Disabled + DTC Interrupt Priority: Priority 12 + + Instance "g_transfer3 Transfer (r_dtc) SDHIMMC0 DMA REQ (DMA transfer request)" + Name: g_transfer3 + Mode: Normal + Transfer Size: 4 Bytes + Destination Address Mode: Fixed + Source Address Mode: Incremented + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 128 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SDHIMMC0 DMA REQ (DMA transfer request) + + Instance "g_cgc0 Clock Generation Circuit (r_cgc)" + Name: g_cgc0 + NMI Callback: NULL + + Instance "g_elc Event Link Controller (r_elc)" + Name: g_elc + + Instance "g_rtc0 Realtime Clock (r_rtc)" + Name: g_rtc0 + Clock Source: LOCO + Frequency Comparision Value (LOCO): 255 + Automatic Adjustment Mode: Enabled + Automatic Adjustment Period: 10 Seconds + Adjustment Type (Plus-Minus): NONE + Error Adjustment Value: 0 + Callback: NULL + Alarm Interrupt Priority: Disabled + Period Interrupt Priority: Disabled + Carry Interrupt Priority: Priority 12 + + Instance "g_flash0 Flash (r_flash_hp)" + Name: g_flash0 + Data Flash Background Operation: Enabled + Callback: NULL + Flash Ready Interrupt Priority: Disabled + Flash Error Interrupt Priority: Disabled + + Instance "g_wdt0 Watchdog (r_wdt)" + Name: g_wdt0 + Timeout: 16,384 Cycles + Clock Division Ratio: PCLK/8192 + Window Start Position: 100% (Window Position Not Specified) + Window End Position: 0% (Window Position Not Specified) + Reset Control: Reset Output + Stop Control: WDT Count Disabled in Low Power Mode + NMI Callback: NULL + + Instance "g_uart1 UART (r_sci_uart)" + General: Name: g_uart1 + General: Channel: 9 + General: Data Bits: 8bits + General: Parity: None + General: Stop Bits: 1bit + Baud: Baud Rate: 115200 + Baud: Baud Rate Modulation: Disabled + Baud: Max Error (%): 5 + Flow Control: CTS/RTS Selection: Hardware CTS and Hardware RTS + Flow Control: Software RTS Port: Disabled + Flow Control: Software RTS Pin: Disabled + Extra: Clock Source: Internal Clock + Extra: Start bit detection: Falling Edge + Extra: Noise Filter: Disable + Extra: Receive FIFO Trigger Level: Max + Extra: RS-485: DE Pin: Disable + Extra: RS-485: DE Pin Polarity: Active High + Extra: RS-485: DE Port Number: Disabled + Extra: RS-485: DE Pin Number: Disabled + Interrupts: Callback: NULL + Interrupts: Receive Interrupt Priority: Priority 12 + Interrupts: Transmit Data Empty Interrupt Priority: Priority 12 + Interrupts: Transmit End Interrupt Priority: Priority 12 + Interrupts: Error Interrupt Priority: Priority 12 + + Instance "g_transfer5 Transfer (r_dtc) SCI9 TXI (Transmit data empty)" + Name: g_transfer5 + Mode: Normal + Transfer Size: 1 Byte + Destination Address Mode: Fixed + Source Address Mode: Incremented + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SCI9 TXI (Transmit data empty) + + Instance "g_transfer6 Transfer (r_dtc) SCI9 RXI (Received data full)" + Name: g_transfer6 + Mode: Normal + Transfer Size: 1 Byte + Destination Address Mode: Incremented + Source Address Mode: Fixed + Repeat Area (Unused in Normal Mode): Destination + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SCI9 RXI (Received data full) + + Instance "g_spi0 SPI (r_spi)" + Name: g_spi0 + Channel: 0 + Receive Interrupt Priority: Priority 12 + Transmit Buffer Empty Interrupt Priority: Priority 12 + Transfer Complete Interrupt Priority: Priority 12 + Error Interrupt Priority: Priority 12 + Operating Mode: Master + Clock Phase: Data sampling on odd edge, data variation on even edge + Clock Polarity: Low when idle + Mode Fault Error: Disable + Bit Order: MSB First + Callback: spi_callback + SPI Mode: Clock Synchronous Operation + Full or Transmit Only Mode: Full Duplex + Slave Select Polarity: Active Low + Select SSL(Slave Select): SSL0 + MOSI Idle State: MOSI Idle Value Fixing Disable + Parity Mode: Disabled + Byte Swapping: Disable + Bitrate: 16000000 + Clock Delay: 1 Clock + SSL Negation Delay: 1 Clock + Next Access Delay: 1 Clock + + Instance "g_transfer1 Transfer (r_dtc) SPI0 TXI (Transmit buffer empty)" + Name: g_transfer1 + Mode: Normal + Transfer Size: 2 Bytes + Destination Address Mode: Fixed + Source Address Mode: Incremented + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SPI0 TXI (Transmit buffer empty) + + Instance "g_transfer2 Transfer (r_dtc) SPI0 RXI (Receive buffer full)" + Name: g_transfer2 + Mode: Normal + Transfer Size: 2 Bytes + Destination Address Mode: Incremented + Source Address Mode: Fixed + Repeat Area (Unused in Normal Mode): Destination + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SPI0 RXI (Receive buffer full) + + Instance "g_spi1 SPI (r_sci_spi)" + Name: g_spi1 + Channel: 0 + Operating Mode: Master + Clock Phase: Data sampling on odd edge, data variation on even edge + Clock Polarity: Low when idle + Mode Fault Error: Disable + Bit Order: MSB First + Callback: sci_spi_callback + Receive Interrupt Priority: Priority 12 + Transmit Interrupt Priority: Priority 12 + Transmit End Interrupt Priority: Priority 12 + Error Interrupt Priority: Priority 12 + Bitrate: 8000000 + Bitrate Modulation: Disabled + + Instance "g_transfer4 Transfer (r_dtc) SCI0 TXI (Transmit data empty)" + Name: g_transfer4 + Mode: Normal + Transfer Size: 1 Byte + Destination Address Mode: Fixed + Source Address Mode: Incremented + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SCI0 TXI (Transmit data empty) + + Instance "g_transfer11 Transfer (r_dtc) SCI0 RXI (Receive data full)" + Name: g_transfer11 + Mode: Normal + Transfer Size: 1 Byte + Destination Address Mode: Incremented + Source Address Mode: Fixed + Repeat Area (Unused in Normal Mode): Destination + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SCI0 RXI (Receive data full) + + Instance "g_transfer12 Transfer (r_dmac) No ELC Trigger" + Name: g_transfer12 + Channel: 0 + Mode: Normal + Transfer Size: 2 Bytes + Destination Address Mode: Fixed + Source Address Mode: Fixed + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Number of Transfers: 1 + Number of Blocks (Valid only in Repeat,Block or Repeat-Block Mode): 0 + Activation Source: No ELC Trigger + Callback: NULL + Context: NULL + Transfer End Interrupt Priority: Disabled + Interrupt Frequency: Interrupt after all transfers have completed + Offset value (Valid only when address mode is \'Offset\'): 1 + Source Buffer Size: 1 + + Instance "g_transfer7 Transfer (r_dtc) SPI0 ERI (Error)" + Name: g_transfer7 + Mode: Normal + Transfer Size: 2 Bytes + Destination Address Mode: Fixed + Source Address Mode: Fixed + Repeat Area (Unused in Normal Mode): Source + Destination Pointer: NULL + Source Pointer: NULL + Interrupt Frequency: After all transfers have completed + Number of Transfers: 0 + Number of Blocks (Valid only in Block Mode): 0 + Activation Source: SPI0 ERI (Error) + + Instance "g_timer0 Timer, General PWM (r_gpt)" + General: Name: g_timer0 + General: Channel: 0 + General: Mode: Periodic + General: Period: 0x100000000 + General: Period Unit: Raw Counts + Output: Custom Waveform: GTIOA: Initial Output Level: Pin Level Low + Output: Custom Waveform: GTIOA: Cycle End Output Level: Pin Level Retain + Output: Custom Waveform: GTIOA: Compare Match Output Level: Pin Level Retain + Output: Custom Waveform: GTIOA: Retain Output Level at Count Stop: Disabled + Output: Custom Waveform: GTIOB: Initial Output Level: Pin Level Low + Output: Custom Waveform: GTIOB: Cycle End Output Level: Pin Level Retain + Output: Custom Waveform: GTIOB: Compare Match Output Level: Pin Level Retain + Output: Custom Waveform: GTIOB: Retain Output Level at Count Stop: Disabled + Output: Custom Waveform: Custom Waveform Enable: Disabled + Output: Duty Cycle Percent (only applicable in PWM mode): 50 + Output: GTIOCA Output Enabled: False + Output: GTIOCA Stop Level: Pin Level Low + Output: GTIOCB Output Enabled: False + Output: GTIOCB Stop Level: Pin Level Low + Input: Count Up Source: + Input: Count Down Source: + Input: Start Source: + Input: Stop Source: + Input: Clear Source: + Input: Capture A Source: + Input: Capture B Source: + Input: Noise Filter A Sampling Clock Select: No Filter + Input: Noise Filter B Sampling Clock Select: No Filter + Interrupts: Callback: NULL + Interrupts: Overflow/Crest Interrupt Priority: Disabled + Interrupts: Capture A Interrupt Priority: Disabled + Interrupts: Capture B Interrupt Priority: Disabled + Interrupts: Underflow/Trough Interrupt Priority: Disabled + Extra Features: Extra Features: Disabled + Extra Features: Output Disable: POEG Link: POEG Channel 0 + Extra Features: Output Disable: Output Disable POEG Trigger: + Extra Features: ADC Trigger: Start Event Trigger (Channels with GTINTAD only): + Extra Features: Dead Time: Dead Time Count Up (Raw Counts): 0 + Extra Features: Dead Time: Dead Time Count Down (Raw Counts) (Channels with GTDVD only): 0 + Extra Features: ADC Trigger (Channels with GTADTRA only): ADC A Compare Match (Raw Counts): 0 + Extra Features: ADC Trigger (Channels with GTADTRB only): ADC B Compare Match (Raw Counts): 0 + Extra Features: Interrupt Skipping (Channels with GTITC only): Interrupt to Count: None + Extra Features: Interrupt Skipping (Channels with GTITC only): Interrupt Skip Count: 0 + Extra Features: Interrupt Skipping (Channels with GTITC only): Skip ADC Events: None + Extra Features: Output Disable: GTIOCA Disable Setting: Disable Prohibited + Extra Features: Output Disable: GTIOCB Disable Setting: Disable Prohibited + + Instance "g_timer1 Timer, Low-Power (r_agt)" + General: Name: g_timer1 + General: Channel: 0 + General: Mode: Periodic + General: Period: 0x10000 + General: Period Unit: Raw Counts + Output: Duty Cycle Percent (only applicable in PWM mode): 50 + General: Count Source: PCLKB + Output: AGTOA Output: Disabled + Output: AGTOB Output: Disabled + Output: AGTO Output: Disabled + Input: Measurement Mode: Measure Disabled + Input: Input Filter: No Filter + Input: Enable Pin: Enable Pin Not Used + Input: Trigger Edge: Trigger Edge Rising + Interrupts: Callback: NULL + Interrupts: Underflow Interrupt Priority: Disabled + + Instance "g_i2c0 I2C Master (r_sci_i2c)" + Name: g_i2c0 + Channel: 0 + Slave Address : 0x00 + Address Mode: 7-Bit + Rate: Standard + SDA Output Delay (nano seconds): 300 + Noise filter setting: Use clock signal divided by 1 with noise filter + Bit Rate Modulation: Enable + Callback: sci_i2c_master_callback + Interrupt Priority Level: Priority 12 + RX Interrupt Priority Level [Only used when DTC is enabled]: Disabled + diff --git a/extras/package_sfe.sh b/extras/package_sfe.sh new file mode 100644 index 00000000..fe913244 --- /dev/null +++ b/extras/package_sfe.sh @@ -0,0 +1,36 @@ +#!/bin/bash + +if [ ! -f platform.txt ]; then + echo Launch this script from the root core folder as ./extras/package_sfe.sh + exit 2 +fi + +if [ ! -d ../ArduinoCore-API ]; then + git checkout https://github.com/arduino/ArduinoCore-API.git ../ArduinoCore-API +fi + +VERSION=`cat platform.txt | grep "version=" | cut -f2 -d"="` +echo $VERSION + +# Thing Plus RA6M5 + +VARIANT=thingplus +EXCLUDE_TAGS=--exclude-tag-all=.unor4_only + +FILENAME=ArduinoCore-renesas_$VARIANT-$VERSION.tar.bz2 + +git checkout platform.txt + +sed -i 's/minima./#minima./g' boards.txt +sed -i 's/unor4wifi./#unor4wifi./g' boards.txt +sed -i 's/muxto./#muxto./g' boards.txt +sed -i 's/portenta_c33./#portenta_c33./g' boards.txt +sed -i 's/Arduino Renesas fsp Boards/SparkFun Renesas Thing Plus Boards/g' platform.txt + +CORE_BASE=`basename $PWD` +cd .. +tar $EXCLUDE_TAGS --exclude='*.vscode*' --exclude='*.tar.*' --exclude='*.json*' --exclude '*.git*' --exclude='*e2studio*' --exclude='*extras*' -cjhvf $FILENAME $CORE_BASE +cd - + +mv ../$FILENAME . + diff --git a/post_install.sh b/post_install.sh index b99435e2..65e7e679 100755 --- a/post_install.sh +++ b/post_install.sh @@ -6,6 +6,7 @@ arduino_renesas_core_rules () { echo "" cat < FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + + /* TrustZone Secure Gateway Stubs Section. */ + + /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */ + /* 1. Get the address to the next block after the .data section in FLASH. */ + DATA_END = LOADADDR(.data) + SIZEOF(.data); + /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024); + /* 3. Manually specify the start location for .gnu.sgstubs */ + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__); + .qspi_non_retentive : AT (__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__); + .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__); + .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + KEEP(*(.ns_buffer*)) + } > RAM + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + end = .; + KEEP(*(.heap)) + } > RAM + + __StackTop = ORIGIN(RAM) + LENGTH(RAM) - VECTOR_TABLE_LENGTH; + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy ABSOLUTE(__StackTop - BSP_CFG_STACK_MAIN_BYTES) (NOLOAD): + { + . = ALIGN(8); + __HeapLimit = .; + __StackLimit = .; + KEEP(*(.stack)) + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + .vector_table ABSOLUTE(__StackTop) (NOLOAD): + { + . = ALIGN(4); + APPLICATION_VECTOR_TABLE_ADDRESS_RAM = .; + . = ABSOLUTE(RAM_START + RAM_LENGTH); + } > RAM + + PROVIDE(__stack = __StackTop); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_N = __ID_Code_End; + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING); + + .option_setting : + { + __OPTION_SETTING_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start; + KEEP(*(.option_setting_dualsel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = OPTION_SETTING_START_NS; + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/tmp/memory_regions.ld b/tmp/memory_regions.ld new file mode 100644 index 00000000..9e19f9d2 --- /dev/null +++ b/tmp/memory_regions.ld @@ -0,0 +1,26 @@ +/* generated memory regions file - do not edit */ +RAM_START = 0x20000000; +RAM_LENGTH = 0x80000; +FLASH_START = 0x00000000; +FLASH_LENGTH = 0x200000; +DATA_FLASH_START = 0x08000000; +DATA_FLASH_LENGTH = 0x2000; +OPTION_SETTING_START = 0x0100A100; +OPTION_SETTING_LENGTH = 0x100; +OPTION_SETTING_S_START = 0x0100A200; +OPTION_SETTING_S_LENGTH = 0x100; +ID_CODE_START = 0x00000000; +ID_CODE_LENGTH = 0x0; +SDRAM_START = 0x90000000; +SDRAM_LENGTH = 0x0; +QSPI_FLASH_START = 0x60000000; +QSPI_FLASH_LENGTH = 0x4000000; +OSPI_DEVICE_0_START = 0x68000000; +OSPI_DEVICE_0_LENGTH = 0x8000000; +OSPI_DEVICE_1_START = 0x70000000; +OSPI_DEVICE_1_LENGTH = 0x10000000; +RAM_NS_BUFFER_LENGTH = 0x6800; +FLASH_IMAGE_START = 0x10000; +VECTOR_TABLE_LENGTH = 0x200; +BSP_CFG_STACK_MAIN_BYTES = 0x1000; +MAIN_THREAD_STACK_LENGTH = 0x4000; diff --git a/tmp/pinmux.inc b/tmp/pinmux.inc new file mode 100644 index 00000000..4f8fe111 --- /dev/null +++ b/tmp/pinmux.inc @@ -0,0 +1,406 @@ +const uint16_t P109[] = { +PIN_CAN_TX|CHANNEL_1, +PIN_PWM|CHANNEL_1|PWM_CHANNEL_A|GPT_ODD_CFG, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_9|SCI_ODD_CFG, +PIN_MOSI|CHANNEL_0|LAST_ITEM_GUARD +}; + +const uint16_t P407[] = { +PIN_PWM|CHANNEL_6|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_SDA|CHANNEL_0, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_4|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P301[] = { +PIN_PWM|CHANNEL_4|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_6, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_2|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P303[] = { +PIN_PWM|CHANNEL_7|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P306[] = { +SCI_CHANNEL|PIN_SCK|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P113[] = { +PIN_PWM|CHANNEL_2|PWM_CHANNEL_A|GPT_ODD_CFG, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_2|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P409[] = { +PIN_INTERRUPT|CHANNEL_6, +PIN_SDA|CHANNEL_2, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_3|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P112[] = { +PIN_PWM|CHANNEL_3|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_1|SCI_ODD_CFG, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_2|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P302[] = { +PIN_PWM|CHANNEL_4|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_5, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_2|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P304[] = { +PIN_PWM|CHANNEL_7|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_9, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P305[] = { +PIN_INTERRUPT|CHANNEL_8, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P115[] = { +PIN_PWM|CHANNEL_4|PWM_CHANNEL_A|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P207[] = { +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_4|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P410[] = { +PIN_PWM|CHANNEL_9|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_5, +PIN_SCL|CHANNEL_2, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_0|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_3|SCI_ODD_CFG, +PIN_MISO|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P411[] = { +PIN_PWM|CHANNEL_9|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_4, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_0|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_3|SCI_ODD_CFG, +PIN_MOSI|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P114[] = { +PIN_PWM|CHANNEL_2|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P108[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P300[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_A|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P307[] = { +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P200[] = { +PIN_INTERRUPT|CHANNEL_0|LAST_ITEM_GUARD +}; + +const uint16_t P609[] = { +PIN_CAN_TX|CHANNEL_1, +PIN_PWM|CHANNEL_5|PWM_CHANNEL_A|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P206[] = { +PIN_INTERRUPT|CHANNEL_0, +PIN_SDA|CHANNEL_1, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_4|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P408[] = { +PIN_PWM|CHANNEL_6|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_7, +PIN_SCL|CHANNEL_0, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_3|SCI_ODD_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_4|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P412[] = { +SCI_CHANNEL|PIN_SCK|CHANNEL_0|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_3|SCI_ODD_CFG, +PIN_SCK|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P414[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_9, +PIN_SDA|CHANNEL_2, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_0|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P608[] = { +PIN_PWM|CHANNEL_4|PWM_CHANNEL_B|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P110[] = { +PIN_CAN_RX|CHANNEL_1, +PIN_PWM|CHANNEL_1|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_3, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_2|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_9|SCI_ODD_CFG, +PIN_MISO|CHANNEL_0|LAST_ITEM_GUARD +}; + +const uint16_t P111[] = { +PIN_PWM|CHANNEL_3|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_4, +SCI_CHANNEL|PIN_SCK|CHANNEL_2|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_9|SCI_ODD_CFG, +PIN_SCK|CHANNEL_0|LAST_ITEM_GUARD +}; + +const uint16_t P205[] = { +PIN_PWM|CHANNEL_4|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_1, +PIN_SCL|CHANNEL_1, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_4|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P413[] = { +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_0|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P415[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_8, +PIN_SCL|CHANNEL_2|LAST_ITEM_GUARD +}; + +const uint16_t P708[] = { +PIN_INTERRUPT|CHANNEL_11, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_1|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P610[] = { +PIN_CAN_RX|CHANNEL_1, +PIN_PWM|CHANNEL_5|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P213[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_2, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_1|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P212[] = { +PIN_PWM|CHANNEL_0|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_3, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_1|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P602[] = { +PIN_PWM|CHANNEL_7|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P601[] = { +PIN_PWM|CHANNEL_6|PWM_CHANNEL_A|GPT_ODD_CFG, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P600[] = { +PIN_PWM|CHANNEL_6|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_9|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P107[] = { +PIN_PWM|CHANNEL_8|PWM_CHANNEL_A|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_8|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P105[] = { +PIN_PWM|CHANNEL_1|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_0, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_8|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P106[] = { +PIN_PWM|CHANNEL_8|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_8|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P403[] = { +PIN_PWM|CHANNEL_3|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_14, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P404[] = { +PIN_PWM|CHANNEL_3|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_15, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P104[] = { +PIN_PWM|CHANNEL_1|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_1, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_8|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P102[] = { +PIN_CAN_RX|CHANNEL_0, +PIN_PWM|CHANNEL_2|PWM_CHANNEL_B|GPT_ODD_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_0|SCI_EVEN_CFG, +PIN_SCK|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P003[] = { +PIN_ANALOG|CHANNEL_3|ADC_0|LAST_ITEM_GUARD +}; + +const uint16_t P007[] = { +PIN_ANALOG|CHANNEL_7|ADC_0|LAST_ITEM_GUARD +}; + +const uint16_t P103[] = { +PIN_CAN_TX|CHANNEL_0, +PIN_PWM|CHANNEL_2|PWM_CHANNEL_A|GPT_ODD_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_0|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P006[] = { +PIN_ANALOG|CHANNEL_6|ADC_0, +PIN_INTERRUPT|CHANNEL_11|LAST_ITEM_GUARD +}; + +const uint16_t P001[] = { +PIN_ANALOG|CHANNEL_1|ADC_0, +PIN_ANALOG|CHANNEL_1|ADC_1, +PIN_INTERRUPT|CHANNEL_7|LAST_ITEM_GUARD +}; + +const uint16_t P400[] = { +PIN_PWM|CHANNEL_6|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_0, +PIN_SCL|CHANNEL_0, +SCI_CHANNEL|PIN_SCK|CHANNEL_4|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P406[] = { +PIN_PWM|CHANNEL_1|PWM_CHANNEL_B|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P101[] = { +PIN_PWM|CHANNEL_5|PWM_CHANNEL_A|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_1, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_0|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_1|SCI_ODD_CFG, +PIN_MOSI|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P503[] = { +PIN_ANALOG|CHANNEL_19|ADC_1, +SCI_CHANNEL|PIN_SCK|CHANNEL_5|SCI_ODD_CFG, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P100[] = { +PIN_PWM|CHANNEL_5|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_2, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_0|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_1|SCI_ODD_CFG, +PIN_MISO|CHANNEL_1|LAST_ITEM_GUARD +}; + +const uint16_t P008[] = { +PIN_ANALOG|CHANNEL_8|ADC_0, +PIN_INTERRUPT|CHANNEL_12|LAST_ITEM_GUARD +}; + +const uint16_t P004[] = { +PIN_ANALOG|CHANNEL_4|ADC_0, +PIN_INTERRUPT|CHANNEL_9|LAST_ITEM_GUARD +}; + +const uint16_t P402[] = { +PIN_CAN_RX|CHANNEL_0, +PIN_INTERRUPT|CHANNEL_4, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_4|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P405[] = { +PIN_PWM|CHANNEL_1|PWM_CHANNEL_A|GPT_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P501[] = { +PIN_ANALOG|CHANNEL_17|ADC_1, +PIN_INTERRUPT|CHANNEL_11, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_5|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P504[] = { +PIN_ANALOG|CHANNEL_20|ADC_1, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_5|SCI_ODD_CFG, +SCI_CHANNEL|PIN_SCK|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P505[] = { +PIN_ANALOG|CHANNEL_21|ADC_1, +PIN_INTERRUPT|CHANNEL_14, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P015[] = { +PIN_ANALOG|CHANNEL_13|ADC_0, +PIN_INTERRUPT|CHANNEL_13|LAST_ITEM_GUARD +}; + +const uint16_t P005[] = { +PIN_ANALOG|CHANNEL_5|ADC_0, +PIN_INTERRUPT|CHANNEL_10|LAST_ITEM_GUARD +}; + +const uint16_t P002[] = { +PIN_ANALOG|CHANNEL_2|ADC_0, +PIN_ANALOG|CHANNEL_2|ADC_1, +PIN_INTERRUPT|CHANNEL_8|LAST_ITEM_GUARD +}; + +const uint16_t P000[] = { +PIN_ANALOG|CHANNEL_0|ADC_0, +PIN_ANALOG|CHANNEL_0|ADC_1, +PIN_INTERRUPT|CHANNEL_6|LAST_ITEM_GUARD +}; + +const uint16_t P401[] = { +PIN_CAN_TX|CHANNEL_0, +PIN_PWM|CHANNEL_6|PWM_CHANNEL_B|GPT_ODD_CFG, +PIN_INTERRUPT|CHANNEL_5, +PIN_SDA|CHANNEL_0, +SCI_CHANNEL|PIN_CTSRTS|CHANNEL_4|SCI_EVEN_CFG, +SCI_CHANNEL|PIN_TX_MOSI_SDA|CHANNEL_7|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P500[] = { +PIN_ANALOG|CHANNEL_16|ADC_1, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_5|SCI_ODD_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P502[] = { +PIN_ANALOG|CHANNEL_18|ADC_1, +PIN_INTERRUPT|CHANNEL_12, +SCI_CHANNEL|PIN_RX_MISO_SCL|CHANNEL_5|SCI_ODD_CFG, +SCI_CHANNEL|PIN_CTS_RTS_SS|CHANNEL_6|SCI_EVEN_CFG|LAST_ITEM_GUARD +}; + +const uint16_t P014[] = { +PIN_ANALOG|CHANNEL_12|ADC_0|LAST_ITEM_GUARD +}; + diff --git a/tmp/pins_arduino.h b/tmp/pins_arduino.h new file mode 100644 index 00000000..712a1b7f --- /dev/null +++ b/tmp/pins_arduino.h @@ -0,0 +1,168 @@ +#pragma once + +#define PIN(X,Y) (X * 16 + Y) + +// Pin count +// ---- +#ifdef __cplusplus +extern "C" unsigned int PINCOUNT_fn(); +#endif +#define PINS_COUNT (PINCOUNT_fn()) +#define NUM_DIGITAL_PINS (45u) +#define NUM_ANALOG_INPUTS (6u) +#define NUM_ANALOG_OUTPUTS (2u) + +#define PIN_A0 (7u) +#define PIN_A1 (8u) +#define PIN_A2 (9u) +#define PIN_A3 (10u) +#define PIN_A4 (11u) +#define PIN_A5 (12u) + + +#define DAC8_HOWMANY (0) +#define DAC12_HOWMANY (2) +#define DAC 7 +#define DAC1 8 +#define IS_DAC(x) (x == DAC || x == DAC1) +#define DAC_ADDRESS_12_CH0 R_DAC_BASE +// TODO: check if true +#define DAC_ADDRESS_12_CH1 (R_DAC_BASE+2) + +static const uint8_t A0 = PIN_A0; +static const uint8_t A1 = PIN_A1; +static const uint8_t A2 = PIN_A2; +static const uint8_t A3 = PIN_A3; +static const uint8_t A4 = PIN_A4; +static const uint8_t A5 = PIN_A5; + +// Digital pins +// ----------- +#define PIN_D0 (0u) +#define PIN_D1 (1u) +#define PIN_D2 (2u) +#define PIN_D3 (3u) +#define PIN_D4 (4u) +#define PIN_D5 (5u) +#define PIN_D6 (6u) + +#undef D0 +#undef D1 +#undef D2 +#undef D3 +#undef D4 +#undef D5 +#undef D6 +#undef D7 +static const uint8_t D0 = PIN_D0; +static const uint8_t D1 = PIN_D1; +static const uint8_t D2 = PIN_D2; +static const uint8_t D3 = PIN_D3; +static const uint8_t D4 = PIN_D4; +static const uint8_t D5 = PIN_D5; +static const uint8_t D6 = PIN_D6; + +// LEDs +// ---- +#define PIN_LED (14u) +#define LED_BUILTIN PIN_LED +#define LED_RGB (13u) + + +/****** RTC CORE DEFINES *******/ +#define RTC_HOWMANY 1 + +/****** UART CORE DEFINES ******/ + +#define SERIAL_HOWMANY 2 +#define UART1_TX_PIN 20 +#define UART1_RX_PIN 21 +#define UART2_TX_PIN 31 +#define UART2_RX_PIN 32 +#define UART2_RTS_PIN 33 +#define UART2_CTS_PIN 34 + +/****** WIRE CORE DEFINES ******/ + +#define WIRE_HOWMANY 1 +#define WIRE_SDA_PIN 15 +#define WIRE_SCL_PIN 16 + +/****** SPI CORE DEFINES ******/ + +#define SPI_HOWMANY 1 + +#define PIN_SPI_MOSI 18 +#define PIN_SPI_MISO 17 +#define PIN_SPI_SCK 19 +#define PIN_SPI_CS 6 +#define FORCE_SPI_MODE (MODE_SCI) + +static const uint8_t MOSI = PIN_SPI_MOSI; +static const uint8_t MISO = PIN_SPI_MISO; +static const uint8_t SCK = PIN_SPI_SCK; +static const uint8_t CS = PIN_SPI_CS; +static const uint8_t SS = PIN_SPI_CS; + +static const uint8_t POCI = PIN_SPI_MISO; +static const uint8_t PICO = PIN_SPI_MOSI; + +// /****** CAN CORE DEFINES ******/ + +#define CANFD_HOWMANY 0 + +// /****** GTP CORE DEFINES *******/ + +#define GTP32_HOWMANY 4 +#define GTP16_HOWMANY 6 +#define GPT_HOWMANY 10 + +// /****** AGT CORE DEFINES *******/ +#define AGT_HOWMANY 6 + +/****** ETHERNET CORE DEFINES *******/ +#define ETHERNET_HOWMANY 0 + +/****** SDCARD CORE DEFINES *******/ +#define SDCARD_HOWMANY 1 + + +#define EXT_INTERRUPTS_HOWMANY 14 + +#define USE_4BIT_SDCARD 1 + +#define USB_VID (0x1b4f) +#define USB_PID (0x0036) +#define USB_NAME "SparkFun Thing Plus RA6M5" + +#define ARDUINO_FLASH_TYPE HP_FLASH +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_TOTAL_SIZE 0x2000 +#define FLASH_BLOCK_SIZE 0x40 + +#define PIN_QSPI_CLK (40u) +#define PIN_QSPI_SS (41u) +#define PIN_QSPI_D0 (42u) +#define PIN_QSPI_D1 (43u) +#define PIN_QSPI_D2 (44u) +#define PIN_QSPI_D3 (45u) + +#define HAS_QSPI + +#define QSPI_TOTAL_SIZE (0x1000000) +#define QSPI_READ_BLOCK_SIZE (0x1) +#define QSPI_ERASE_BLOCK_SIZE (0x1000) +#define QSPI_WRITE_BLOCK_SIZE (0x1) + +#define HAS_SDHI + +#define PIN_SDHI_CLK (22u) +#define PIN_SDHI_CMD (23u) +#define PIN_SDHI_D0 (24u) +#define PIN_SDHI_D1 (25u) +#define PIN_SDHI_D2 (26u) +#define PIN_SDHI_D3 (27u) +#define PIN_SDHI_CD (28u) +#define PIN_SDHI_WP (29u) + +#define RTC_CLOCK_SOURCE RTC_CLOCK_SOURCE_SUBCLK diff --git a/tmp/tusb_config.h b/tmp/tusb_config.h new file mode 100644 index 00000000..46609ce0 --- /dev/null +++ b/tmp/tusb_config.h @@ -0,0 +1,102 @@ +/* + * tusb_config.h + * + * Created on: May 5, 2021 + * Author: Jeremiah McCarthy + */ + +#ifndef TUSB_CONFIG_H_ +#define TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * USB PORT 0 CONFIGURATION: HOST, FULL SPEED + */ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT +#define BOARD_TUD_RHPORT 0 +#endif + +#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_FULL_SPEED) + +#ifndef BOARD_TUD_MAX_SPEED +#define BOARD_TUD_MAX_SPEED OPT_MODE_FULL_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU +#error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 1 +#define CFG_TUD_MSC 1 +#define CFG_TUD_HID 1 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 +#define CFG_TUD_DFU_RUNTIME 1 + +// CDC FIFO size of TX and RX +#define CFG_TUD_CDC_RX_BUFSIZE (4096) +#define CFG_TUD_CDC_TX_BUFSIZE (64) + +// CDC Endpoint transfer buffer size, more is faster +#define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +// MSC Buffer size of Device Mass storage +#define CFG_TUD_MSC_EP_BUFSIZE 512 + +#ifdef __cplusplus + } +#endif + +#endif /* TUSB_CONFIG_H_ */ diff --git a/tmp/variant.cpp b/tmp/variant.cpp new file mode 100644 index 00000000..91163193 --- /dev/null +++ b/tmp/variant.cpp @@ -0,0 +1,131 @@ +#include "Arduino.h" +#include "pinmux.inc" + +// pins not yet handled by the script +const uint16_t P208[] = { LAST_ITEM_GUARD }; + +const uint16_t P209[] = { LAST_ITEM_GUARD }; + +const uint16_t P210[] = { + PIN_PWM_AGT|CHANNEL_5|PWM_CHANNEL_B|LAST_ITEM_GUARD, +}; + +const uint16_t P211[] = { LAST_ITEM_GUARD }; + +const uint16_t P214[] = { LAST_ITEM_GUARD }; + + +const uint16_t P015_b[] = { + PIN_DAC|CHANNEL_1, + PIN_ANALOG|CHANNEL_13|ADC_0, + PIN_INTERRUPT|CHANNEL_13|LAST_ITEM_GUARD +}; +#define P015 P015_b + +const uint16_t P014_b[] = { + PIN_DAC|CHANNEL_0, + PIN_ANALOG|CHANNEL_12|ADC_0|LAST_ITEM_GUARD +}; +#define P014 P014_b + +extern "C" const PinMuxCfg_t g_pin_cfg[] = { + + // Thing Plus Form Factor + { BSP_IO_PORT_01_PIN_12, P112 }, /* D0 | CS0 */ + { BSP_IO_PORT_04_PIN_06, P406 }, /* D1 | SSI SDI */ + { BSP_IO_PORT_04_PIN_05, P405 }, /* D2 | SSI SDO */ + { BSP_IO_PORT_04_PIN_04, P404 }, /* D3 | SSI WS/IRQ */ + { BSP_IO_PORT_04_PIN_03, P403 }, /* D4 | SSI CK/IRQ */ + { BSP_IO_PORT_04_PIN_02, P402 }, /* D5 | AUD_CLK/IRQ */ + { BSP_IO_PORT_02_PIN_07, P207 }, /* D6 | */ + + // Analog + { BSP_IO_PORT_00_PIN_14, P014 }, /* D7 | A0/DAC0 */ + { BSP_IO_PORT_00_PIN_15, P015 }, /* D8 | A1/DAC1/IRQ */ + { BSP_IO_PORT_05_PIN_05, P505 }, /* D9 | A2/IRQ */ + { BSP_IO_PORT_05_PIN_04, P504 }, /* D10 | A3 */ + { BSP_IO_PORT_05_PIN_03, P503 }, /* D11 | A4 */ + { BSP_IO_PORT_05_PIN_02, P502 }, /* D12 | A5/IRQ */ + + // LEDS + { BSP_IO_PORT_01_PIN_05, P105 }, /* D13 | RGB */ + { BSP_IO_PORT_01_PIN_06, P106 }, /* D14 | STAT */ + + // I2C pins + { BSP_IO_PORT_04_PIN_01, P401 }, /* D15 | SDA0/IRQ */ + { BSP_IO_PORT_04_PIN_00, P400 }, /* D16 | SCL0/IRQ */ + + // SPI pins + { BSP_IO_PORT_01_PIN_10, P110 }, /* D17 | POCI0 */ + { BSP_IO_PORT_01_PIN_09, P109 }, /* D18 | PICO0/IRQ */ + { BSP_IO_PORT_01_PIN_11, P111 }, /* D19 | SCK0/IRQ */ + + // UART pins + { BSP_IO_PORT_04_PIN_09, P409 }, /* D20 | TX0/IRQ */ + { BSP_IO_PORT_04_PIN_08, P408 }, /* D21 | RX0/IRQ */ + + // SDCARD + { BSP_IO_PORT_02_PIN_14, P214 }, /* D22 | SDHI CLK */ + { BSP_IO_PORT_02_PIN_12, P211 }, /* D23 | SDHI CMD */ + { BSP_IO_PORT_02_PIN_08, P208 }, /* D24 | SDHI D0 */ + { BSP_IO_PORT_04_PIN_10, P410 }, /* D25 | SDHI D1 */ + { BSP_IO_PORT_02_PIN_06, P206 }, /* D26 | SDHI D2 */ + { BSP_IO_PORT_02_PIN_05, P205 }, /* D27 | SDHI D3 */ + { BSP_IO_PORT_02_PIN_10, P210 }, /* D28 | SDHI CD */ + { BSP_IO_PORT_04_PIN_14, P414 }, /* D29 | SDHI WP */ + + // Other GPIO + { BSP_IO_PORT_03_PIN_04, P304 }, /* D30 | FREE/IRQ */ + + /// ###### FROM HERE, INTERNAL STUFF ONLY + + // DA14531 BLE UART + { BSP_IO_PORT_06_PIN_02, P602 }, /* D31 | TX1 */ + { BSP_IO_PORT_06_PIN_01, P601 }, /* D32 | RX1 */ + { BSP_IO_PORT_03_PIN_01, P301 }, /* D33 | RTS1 */ + { BSP_IO_PORT_03_PIN_03, P303 }, /* D34 | CTS1 */ + + // Dedicated GPIO pins + { BSP_IO_PORT_07_PIN_08, P708 }, /* D35 | !SDEN */ + { BSP_IO_PORT_01_PIN_15, P115 }, /* D36 | BLE !RESET */ + { BSP_IO_PORT_05_PIN_00, P500 }, /* D37 | VREF_EN */ + { BSP_IO_PORT_00_PIN_01, P001 }, /* D38 | PWR_STATUS */ + + // Onboard Interrupts + { BSP_IO_PORT_00_PIN_00, P000 }, /* D39 | !FUEL_GAUGE/IRQ */ + + // QSPI + { BSP_IO_PORT_01_PIN_00, P100 }, /* D40 | QSPI CLK */ + { BSP_IO_PORT_05_PIN_01, P501 }, /* D41 | QSPI SS */ + { BSP_IO_PORT_01_PIN_02, P102 }, /* D42 | QSPI IO0 */ + { BSP_IO_PORT_01_PIN_01, P101 }, /* D43 | QSPI IO1 */ + { BSP_IO_PORT_01_PIN_04, P104 }, /* D44 | QSPI IO2 */ + { BSP_IO_PORT_01_PIN_03, P103 }, /* D45 | QSPI IO3 */ +}; + +extern "C" { + unsigned int PINCOUNT_fn() { + return (sizeof(g_pin_cfg) / sizeof(g_pin_cfg[0])); + } +} + +int32_t getPinIndex(bsp_io_port_pin_t p) { + int max_index = PINS_COUNT; + int rv = -1; + for(int i = 0; i < max_index; i++) { + if(g_pin_cfg[i].pin == p) { + rv = i; + break; + } + } + return rv; +} + + +void initVariant() { + // bootloader configures LED_BUILTIN as PWM output, deconfigure it to avoid spurious signals + pinMode(LED_BUILTIN, INPUT); + + // We're using an extenal reference voltage, so set that here. NOTE: AREF = 3.3V + analogReference(AR_EXTERNAL); +} From cc3ebf1f5ca667dbdf4bcc00cec0b5147b5d2f69 Mon Sep 17 00:00:00 2001 From: SFE-Brudnerd <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Thu, 1 Feb 2024 12:50:00 -0700 Subject: [PATCH 02/13] working. --- .../SparkFun_ThingPlus_RA6M5/.cproject | 13 + .../SparkFun_ThingPlus_RA6M5/.secure_xml | 2 +- ...enesas.cdt.ddsc.packs.componentfiles.prefs | 60 +- .../.settings/language.settings.xml | 4 +- .../configuration.xml | 8 +- .../fsp_to_arduino.sh | 6 +- .../SparkFun_ThingPlus_RA6M5/ra_cfg.txt | 4 +- extras/package.sh | 36 +- extras/package_index.json.template | 156 + extras/package_sfe.sh | 17 +- .../ESPhost/.thingplus_exclude | 0 libraries/Ethernet/.thingplus_exclude | 0 libraries/SE05X/.thingplus_exclude | 0 libraries/SFU/.thingplus_exclude | 0 libraries/SSLClient/.thingplus_exclude | 0 libraries/UsbHostMsd/.thingplus_exclude | 0 libraries/WiFi/.thingplus_exclude | 0 libraries/lwIpWrapper/.thingplus_exclude | 0 variants/PORTENTA_C33/.thingplus_exclude | 0 variants/THINGPLUS_RA6M5/.portenta_exclude | 0 variants/THINGPLUS_RA6M5/.portenta_only | 0 variants/THINGPLUS_RA6M5/cflags.txt | 19 + variants/THINGPLUS_RA6M5/cxxflags.txt | 19 + variants/THINGPLUS_RA6M5/defines.txt | 3 + variants/THINGPLUS_RA6M5/elc_defines.h | 291 + {tmp => variants/THINGPLUS_RA6M5}/fsp.ld | 0 variants/THINGPLUS_RA6M5/includes.txt | 12 + .../CMSIS/Core/Include/cachel1_armv7.h | 411 + .../CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h | 888 + .../CMSIS/Core/Include/cmsis_armclang.h | 1503 + .../CMSIS/Core/Include/cmsis_armclang_ltm.h | 1928 + .../CMSIS/Core/Include/cmsis_compiler.h | 283 + .../CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h | 2211 ++ .../CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h | 1002 + .../CMSIS/Core/Include/cmsis_version.h | 39 + .../CMSIS/Core/Include/core_armv81mml.h | 4228 +++ .../CMSIS/Core/Include/core_armv8mbl.h | 2222 ++ .../CMSIS/Core/Include/core_armv8mml.h | 3209 ++ .../arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h | 952 + .../CMSIS_5/CMSIS/Core/Include/core_cm0plus.h | 1087 + .../arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h | 979 + .../CMSIS_5/CMSIS/Core/Include/core_cm23.h | 2297 ++ .../arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h | 1943 + .../CMSIS_5/CMSIS/Core/Include/core_cm33.h | 3277 ++ .../CMSIS_5/CMSIS/Core/Include/core_cm35p.h | 3277 ++ .../arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h | 2129 ++ .../CMSIS_5/CMSIS/Core/Include/core_cm55.h | 4817 +++ .../arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h | 2366 ++ .../CMSIS_5/CMSIS/Core/Include/core_cm85.h | 4672 +++ .../CMSIS_5/CMSIS/Core/Include/core_sc000.h | 1030 + .../CMSIS_5/CMSIS/Core/Include/core_sc300.h | 1917 + .../CMSIS_5/CMSIS/Core/Include/core_starmc1.h | 3592 ++ .../CMSIS_5/CMSIS/Core/Include/mpu_armv7.h | 275 + .../CMSIS_5/CMSIS/Core/Include/mpu_armv8.h | 352 + .../CMSIS_5/CMSIS/Core/Include/pac_armv81.h | 206 + .../CMSIS_5/CMSIS/Core/Include/pmu_armv8.h | 337 + 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mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_elc_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_flash_hp_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_gpt_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_icu_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_master_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_slave_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_lpm_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_rtc_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sce_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_i2c_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_spi_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_uart_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sdhi_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_spi_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ssi_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_basic_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_class_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_pcdc_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_wdt_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_gen/bsp_clock_cfg.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_gen/common_data.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_gen/hal_data.h create mode 100644 variants/THINGPLUS_RA6M5/includes/ra_gen/vector_data.h create mode 100644 variants/THINGPLUS_RA6M5/libs/libfsp.a rename {tmp => variants/THINGPLUS_RA6M5}/memory_regions.ld (96%) rename {tmp => variants/THINGPLUS_RA6M5}/pinmux.inc (100%) rename {tmp => variants/THINGPLUS_RA6M5}/pins_arduino.h (100%) create mode 100644 variants/THINGPLUS_RA6M5/tmp_gen_c_files/common_data.c create mode 100644 variants/THINGPLUS_RA6M5/tmp_gen_c_files/main.c create mode 100644 variants/THINGPLUS_RA6M5/tmp_gen_c_files/pin_data.c rename {tmp => variants/THINGPLUS_RA6M5}/tusb_config.h (100%) rename {tmp => variants/THINGPLUS_RA6M5}/variant.cpp (100%) diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject index 627cb454..bb919db9 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject @@ -67,6 +67,7 @@ @@ -90,6 +92,7 @@ @@ -113,6 +117,7 @@ @@ -290,6 +296,7 @@ @@ -313,6 +321,7 @@ @@ -336,6 +346,7 @@ @@ -467,4 +479,5 @@ + \ No newline at end of file diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml index 8f7a2445..2c582d12 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml @@ -1,5 +1,5 @@ - +

+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_err_rsp_evt_t + */ + BLE_GATTC_EVENT_ERROR_RSP = 0x4001, //!< BLE_GATTC_EVENT_ERROR_RSP + + /** + * @brief This event notifies the application layer that a MTU Exchange Response PDU has been received + * from a GATT Server. + * + * ## Event Code: 0x4003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response + * since GATT Client sent a Exchange MTU Request PDU to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_ex_mtu_rsp_evt_t + */ + BLE_GATTC_EVENT_EX_MTU_RSP = 0x4003, //!< BLE_GATTC_EVENT_EX_MTU_RSP + + /** + * @brief When the read of Characteristic specified by UUID has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x4009 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a Exchange MTU Response + * since GATT Client sent a Exchange MTU Request PDU to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP = 0x4009, //!< BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP + + /** + * @brief When the read of Characteristic/Characteristic Descriptor has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x400B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadCharUsingUuid() + * to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_READ_RSP = 0x400B, //!< BLE_GATTC_EVENT_CHAR_READ_RSP + + /** + * @brief After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer + * that the partial contents of Long Characteristic/Long Characteristic Descriptor + * has been received from the GATT Server. + * + * ## Event Code: 0x400D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadLongChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_PART_READ_RSP = 0x400D, //!< BLE_GATTC_EVENT_CHAR_PART_READ_RSP + + /** + * @brief This event notifies the application layer that + * the read of multiple Characteristics has been completed. + * + * ## Event Code: 0x400F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a read response + * since GATT Client sent a request for read by R_BLE_GATTC_ReadMultiChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_rd_multi_char_evt_t + */ + BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP = 0x400F, //!< BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP + + /** + * @brief This event notifies the application layer that the write of + * Characteristic/Characteristic Descriptor has been completed. + * + * ## Event Code: 0x4013 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a write response + * since GATT Client sent a request for write by R_BLE_GATTC_WriteChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_wr_char_evt_t + */ + BLE_GATTC_EVENT_CHAR_WRITE_RSP = 0x4013, //!< BLE_GATTC_EVENT_CHAR_WRITE_RSP + + /** + * @brief This event notifies the application layer of the one of the following. + * - A segmentation to be written to Long Characteristic/Long Characteristic Descriptor + * has been sent to the GATT Server. + * - The data written to one Characteristic by Reliable Writes has been sent to the GATT Server. + * + * ## Event Code: 0x4017 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a + * request for segmentation write by R_BLE_GATTC_WriteLongChar(), + * or 1 Characteristic write by R_BLE_GATTC_ReliableWrites() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_part_wr_evt_t + */ + BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP = 0x4017, //!< BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP + + /** + * @brief This event notifies the application layer that a Notification has been received from a GATT Server. + * + * ## Event Code: 0x401B + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_ntf_evt_t + */ + BLE_GATTC_EVENT_HDL_VAL_NTF = 0x401B, //!< BLE_GATTC_EVENT_HDL_VAL_NTF + + /** + * @brief This event notifies the application layer that a Indication has been received from a GATT Server. + * @details When the GATT Client has received a Indication, host stack automatically sends a Confirmation + * to the GATT Server. + * + * ## Event Code: 0x401D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_MEM_ALLOC_FAILED(0x000C)Insufficient resource is needed to generate the confirmation packet.
+ *
+ * + * ## Event Data: + * st_ble_gattc_ind_evt_t + */ + BLE_GATTC_EVENT_HDL_VAL_IND = 0x401D, //!< BLE_GATTC_EVENT_HDL_VAL_IND + + /** + * @brief This event notifies the application layer that the link with the GATT Server has been established. + * + * ## Event Code: 0x4081 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_conn_evt_t + */ + BLE_GATTC_EVENT_CONN_IND = 0x4081, //!< BLE_GATTC_EVENT_CONN_IND + + /** + * @brief This event notifies the application layer that the link with the GATT Server has been disconnected. + * + * ## Event Code: 0x4082 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_disconn_evt_t + */ + BLE_GATTC_EVENT_DISCONN_IND = 0x4082, //!< BLE_GATTC_EVENT_DISCONN_IND + + /** + * @brief This event notifies the application layer that 16-bit UUID Primary Service has been discovered. + * + * ## Event Code: 0x40E0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_16_evt_t + */ + BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND = 0x40E0, //!< BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Primary Service has been discovered. + * + * ## Event Code: 0x40E1 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_128_evt_t + */ + BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND = 0x40E1, //!< BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscAllPrimServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E2 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP = 0x40E2, //!< BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscPrimServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E3 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP = 0x40E3, //!< BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Secondary Service has been discovered. + * + * ## Event Code: 0x40E4 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_16_evt_t + */ + BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND = 0x40E4, //!< BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Secondary Service has been discovered. + * + * ## Event Code: 0x40E5 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_serv_128_evt_t + */ + BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND = 0x40E5, //!< BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND + + /** + * @brief When the Primary Service discovery by R_BLE_GATTC_DiscAllSecondServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E6 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP = 0x40E6, //!< BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that Included Service that + * includes 16-bit UUID Service has been discovered. + * + * ## Event Code: 0x40E7 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_inc_serv_16_evt_t + */ + BLE_GATTC_EVENT_INC_SERV_16_DISC_IND = 0x40E7, //!< BLE_GATTC_EVENT_INC_SERV_16_DISC_IND + + /** + * @brief This event notifies the application layer that Included Service that + * includes 128-bit UUID Service has been discovered. + * + * ## Event Code: 0x40E8 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_inc_serv_128_evt_t + */ + BLE_GATTC_EVENT_INC_SERV_128_DISC_IND = 0x40E8, //!< BLE_GATTC_EVENT_INC_SERV_128_DISC_IND + + /** + * @brief When the Included Service discovery by R_BLE_GATTC_DiscIncServ() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40E9 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_INC_SERV_DISC_COMP = 0x40E9, //!< BLE_GATTC_EVENT_INC_SERV_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Characteristic has been discovered. + * + * ## Event Code: 0x40EA + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_16_evt_t + */ + BLE_GATTC_EVENT_CHAR_16_DISC_IND = 0x40EA, //!< BLE_GATTC_EVENT_CHAR_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Characteristic has been discovered. + * + * ## Event Code: 0x40EB + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_128_evt_t + */ + BLE_GATTC_EVENT_CHAR_128_DISC_IND = 0x40EB, //!< BLE_GATTC_EVENT_CHAR_128_DISC_IND + + /** + * @brief When the Characteristic discovery by R_BLE_GATTC_DiscAllChar() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40EC + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP = 0x40EC, //!< BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP + + /** + * @brief When the Characteristic discovery by R_BLE_GATTC_DiscCharByUuid() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40ED + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_CHAR_DISC_COMP = 0x40ED, //!< BLE_GATTC_EVENT_CHAR_DISC_COMP + + /** + * @brief This event notifies the application layer that 16-bit UUID Characteristic Descriptor + * has been discovered. + * + * ## Event Code: 0x40EE + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_desc_16_evt_t + */ + BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND = 0x40EE, //!< BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND + + /** + * @brief This event notifies the application layer that 128-bit UUID Characteristic Descriptor + * has been discovered. + * + * ## Event Code: 0x40EF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gattc_char_desc_128_evt_t + */ + BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND = 0x40EF, //!< BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND + + /** + * @brief When the Characteristic Descriptor discovery by R_BLE_GATTC_DiscAllCharDesc() has been completed, + * this event is notified to the application layer. + * + * ## Event Code: 0x40F0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP = 0x40F0, //!< BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP + + /** + * @brief After calling R_BLE_GATTC_ReadLongChar(), this event notifies the application layer that all of + * the contents of the Characteristic/Long Characteristic Descriptor has been received + * from the GATT Server. + * + * ## Event Code: 0x40F1 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_LONG_CHAR_READ_COMP = 0x40F1, //!< BLE_GATTC_EVENT_LONG_CHAR_READ_COMP + + /** + * @brief This event notifies that the application layer that the write of + * Long Characteristic/Long Characteristic Descriptor has been completed. + * + * ## Event Code: 0x40F2 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent + * a request for write by R_BLE_GATTC_WriteLongChar() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP = 0x40F2, //!< BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP + + /** + * @brief This event notifies that the application layer that + * the GATT Server has received the data to be written to the Characteristics. + * + * ## Event Code: 0x40F3 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP = 0x40F3, //!< BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP + + /** + * @brief This event notifies the application layer that the Reliable Writes has been completed. + * + * ## Event Code: 0x40F4 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)30 seconds or more have passed without receiving a response since GATT Client sent a + * request for execute write by R_BLE_GATTC_ReliableWrites() or + * R_BLE_GATTC_ExecWrite() to the GATT Server. + *
+ *
+ * + * ## Event Data: + * st_ble_gattc_reliable_writes_comp_evt_t + */ + BLE_GATTC_EVENT_RELIABLE_WRITES_COMP = 0x40F4, //!< BLE_GATTC_EVENT_RELIABLE_WRITES_COMP + + /** + * @brief Invalid GATT Client Event. + * + * ## Event Code: 0x40FF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GATTC_EVENT_INVALID = 0x40FF //!< BLE_GATTC_EVENT_INVALID +} e_r_ble_gattc_evt_t; + +/*@}*/ + +/* ================================================== L2CAP Macro =================================================== */ + +/** @addtogroup L2CAP_API + * @ingroup BLE_API + * @{ + */ + +/** + * @ingroup l2cap_api + * @def BLE_L2CAP_MAX_CBFC_PSM + * @brief The maximum number of callbacks that host stack can register. + */ +#define BLE_L2CAP_MAX_CBFC_PSM (2) + +/** + * @def BLE_L2CAP_CF_RSP_SUCCESS + * @brief Notify the remote device that the connection can be established. + */ +#define BLE_L2CAP_CF_RSP_SUCCESS (0x0000) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH + * @brief Notify the remote device that the connection can not be established because of insufficient authentication. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH (0x0005) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ + * @brief Notify the remote device that the connection can not be established because of insufficient Authorization. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ (0x0006) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY + * @brief Notify the remote device that the connection can not be established because of Encryption Key Size. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY (0x0007) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_INSF_ENC + * @brief Notify the remote device that the connection can not be established because of Encryption. + */ +#define BLE_L2CAP_CF_RSP_RFSD_INSF_ENC (0x0008) + +/** + * @def BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM + * @brief Notify the remote device that the connection can not be established + * because the parameters is unacceptable to local device. + */ +#define BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM (0x000B) + +/*@}*/ + +/* ============================================= Vendor Specific Macro ============================================== */ + +/** @addtogroup VS_API + * @ingroup BLE_API + * @{ + */ + +/** + * @ingroup vs_api + * @def BLE_VS_TX_POWER_HIGH + * @brief High power level. + */ +#define BLE_VS_TX_POWER_HIGH (0x00) + +/** + * @def BLE_VS_TX_POWER_MID + * @brief Middle power level. + */ +#define BLE_VS_TX_POWER_MID (0x01) + +/** + * @def BLE_VS_TX_POWER_LOW + * @brief Low power level. + */ +#define BLE_VS_TX_POWER_LOW (0x02) + +/** + * @def BLE_VS_ADDR_AREA_REG + * @brief Address in register is written or read. + */ +#define BLE_VS_ADDR_AREA_REG (0x00) + +/** + * @def BLE_VS_ADDR_AREA_DATA_FLASH + * @brief Address in DataFlash is written or read. + */ +#define BLE_VS_ADDR_AREA_DATA_FLASH (0x01) + +/** + * @def BLE_VS_EH_TX_PL_PRBS9 + * @brief PRBS9 sequence '11111111100000111101..'. + */ +#define BLE_VS_EH_TX_PL_PRBS9 (0x00) + +/** + * @def BLE_VS_EH_TX_PL_11110000 + * @brief Repeated '11110000' + */ +#define BLE_VS_EH_TX_PL_11110000 (0x01) + +/** + * @def BLE_VS_EH_TX_PL_10101010 + * @brief Repeated '10101010' + */ +#define BLE_VS_EH_TX_PL_10101010 (0x02) + +/** + * @def BLE_VS_EH_TX_PL_PRBS15 + * @brief PRBS15 sequence + */ +#define BLE_VS_EH_TX_PL_PRBS15 (0x03) + +/** + * @def BLE_VS_EH_TX_PL_11111111 + * @brief Repeated '11111111' + */ +#define BLE_VS_EH_TX_PL_11111111 (0x04) + +/** + * @def BLE_VS_EH_TX_PL_00000000 + * @brief Repeated '00000000' + */ +#define BLE_VS_EH_TX_PL_00000000 (0x05) + +/** + * @def BLE_VS_EH_TX_PL_00001111 + * @brief Repeated '00001111' + */ +#define BLE_VS_EH_TX_PL_00001111 (0x06) + +/** + * @def BLE_VS_EH_TX_PL_01010101 + * @brief Repeated '01010101' + */ +#define BLE_VS_EH_TX_PL_01010101 (0x07) + +/** + * @def BLE_VS_EH_TEST_PHY_1M + * @brief 1M PHY used in Transmitter/Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_1M (0x01) + +/** + * @def BLE_VS_EH_TEST_PHY_2M + * @brief 2M PHY used in Transmitter/Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_2M (0x02) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED + * @brief Coded PHY used in Receiver test. + */ +#define BLE_VS_EH_TEST_PHY_CODED (0x03) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED_S_8 + * @brief Coded PHY(S=8) used in Transmitter test. + */ +#define BLE_VS_EH_TEST_PHY_CODED_S_8 (0x03) + +/** + * @def BLE_VS_EH_TEST_PHY_CODED_S_2 + * @brief Coded PHY(S=2) used in Transmitter test. + */ +#define BLE_VS_EH_TEST_PHY_CODED_S_2 (0x04) + +/** + * @def BLE_VS_RF_OFF + * @brief RF power off. + */ +#define BLE_VS_RF_OFF (0x00) + +/** + * @def BLE_VS_RF_ON + * @brief RF power on. + */ +#define BLE_VS_RF_ON (0x01) + +/** + * @def BLE_VS_RF_INIT_PARAM_NOT_CHG + * @brief The parameters are not changed in RF power on. + */ +#define BLE_VS_RF_INIT_PARAM_NOT_CHG (0x00) + +/** + * @def BLE_VS_RF_INIT_PARAM_CHG + * @brief The parameters are changed in RF power on. + */ +#define BLE_VS_RF_INIT_PARAM_CHG (0x01) + +/** + * @def BLE_VS_CS_PRIM_ADV_S_8 + * @brief Coding scheme for Primary Advertising PHY(S=8). + */ +#define BLE_VS_CS_PRIM_ADV_S_8 (0x00) + +/** + * @def BLE_VS_CS_PRIM_ADV_S_2 + * @brief Coding scheme for Primary Advertising PHY(S=2). + */ +#define BLE_VS_CS_PRIM_ADV_S_2 (0x01) + +/** + * @def BLE_VS_CS_SECOND_ADV_S_8 + * @brief Coding scheme for Secondary Advertising PHY(S=8). + */ +#define BLE_VS_CS_SECOND_ADV_S_8 (0x00) + +/** + * @def BLE_VS_CS_SECOND_ADV_S_2 + * @brief Coding scheme for Secondary Advertising PHY(S=2). + */ +#define BLE_VS_CS_SECOND_ADV_S_2 (0x02) + +/** + * @def BLE_VS_CS_CONN_S_8 + * @brief Coding scheme for request for link establishment(S=8). + */ +#define BLE_VS_CS_CONN_S_8 (0x00) + +/** + * @def BLE_VS_CS_CONN_S_2 + * @brief Coding scheme for request for link establishment(S=2). + */ +#define BLE_VS_CS_CONN_S_2 (0x04) + +/** + * @def BLE_VS_TX_FLOW_CTL_ON + * @brief It means that the number of buffer has reached the High Water Mark from flow off state. + */ +#define BLE_VS_TX_FLOW_CTL_ON (0x00) + +/** + * @def BLE_VS_TX_FLOW_CTL_OFF + * @brief It means that the number of buffer has reached the Low Water Mark from flow on state. + */ +#define BLE_VS_TX_FLOW_CTL_OFF (0x01) + +/*@}*/ + +/* ============================================== Event Notification Definitions ========================================== */ + +#define BLE_EVENT_NOTIFY_CONNECTION_START_POS (0) +#define BLE_EVENT_NOTIFY_ADVERTISING_POS (1) +#define BLE_EVENT_NOTIFY_SCANNING_POS (2) +#define BLE_EVENT_NOTIFY_INITIATING_START_POS (3) +#define BLE_EVENT_NOTIFY_CONNECTION_CLOSE_POS (4) +#define BLE_EVENT_NOTIFY_ADVERTISING_CLOSE_POS (5) +#define BLE_EVENT_NOTIFY_SCANNING_CLOSE_POS (6) +#define BLE_EVENT_NOTIFY_INITIATING_CLOSE_POS (7) +#define BLE_EVENT_NOTIFY_DEEP_SLEEP_START_POS (8) +#define BLE_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP_POS (9) + +/******************************************************************************************************************//** + * @typedef ble_mcu_clock_change_cb_t + * @brief ble_mcu_clock_change_cb_t is the callback function type to use CLKOUT_RF as the MCU main clock source. + * @param none + * @return none + **********************************************************************************************************************/ +typedef void (* ble_mcu_clock_change_cb_t)(void); + +/******************************************************************************************************************//** + * @typedef ble_rf_notify_cb_t + * @brief ble_rf_notify_cb_t is the RF event notify callback function type. + * @param[in] uint32_t The information of RF event notification. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_rf_notify_cb_t)(uint32_t); + +/******************************************************************************************************************//** + * @struct st_ble_rf_notify_t + * @brief This structure is RF event notify management. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Set enable/disable of each RF event notification + * @details + * Bit0 Notify Connection event start(0:Disable/1:Enable)\n + * Bit1 Notify Advertising event start(0:Disable/1:Enable)\n + * Bit2 Notify Scanning event start(0:Disable/1:Enable)\n + * Bit3 Notify Initiating event start(0:Disable/1:Enable)\n + * Bit4 Notify Connection event close(0:Disable/1:Enable)\n + * Bit5 Notify Advertising event close(0:Disable/1:Enable)\n + * Bit6 Notify Scanning event close(0:Disable/1:Enable)\n + * Bit7 Notify Initiating event close(0:Disable/1:Enable)\n + * Bit8 Notify RF_DEEP_SLEEP event start(0:Disable/1:Enable)\n + * Bit9 Notify RF_DEEP_SLEEP event close(0:Disable/1:Enable)\n + * Other Bit: Reserved for future use.\n + */ + uint32_t enable; + + /** + * @brief Set callback function pointer for RF event start + */ + ble_rf_notify_cb_t start_cb; + + /** + * @brief Set callback function pointer for RF event close + */ + ble_rf_notify_cb_t close_cb; + + /** + * @brief Set callback function pointer for RF_DEEP_SLEEP + */ + ble_rf_notify_cb_t dsleep_cb; +} st_ble_rf_notify_t; + +/*@}*/ + +/* ============================================== GAP Type Definitions ============================================== */ + +/** @addtogroup GAP_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @struct st_ble_evt_data_t + * @brief st_ble_evt_data_t is the type of the data notified in a GAP Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The size of GAP Event parameters. + */ + uint16_t param_len; + + /** + * @brief GAP Event parameters. This parameter differs in each GAP Event. + */ + void * p_param; +} st_ble_evt_data_t; + +/******************************************************************************************************************//** + * @struct st_ble_dev_addr_t + * @brief st_ble_dev_addr_t is the type of bluetooth device address(BD_ADDR). + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief BD_ADDR. + */ + uint8_t addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Bluetooth address type. + * @details + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address. | + * | BLE_GAP_ADDR_RAND(0x01) | Random Address. | + */ + uint8_t type; +} st_ble_dev_addr_t; + +/******************************************************************************************************************//** + * @typedef ble_gap_app_cb_t + * @brief ble_gap_app_cb_t is the GAP Event callback function type. + * @param[in] event_type The type of GAP Event. + * @param[in] event_result The result of API call which generates the GAP Event. + * @param[in] p_event_data Data notified in the GAP Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gap_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_evt_data_t * p_event_data); + +/******************************************************************************************************************//** + * @typedef ble_gap_del_bond_cb_t + * @brief ble_gap_del_bond_cb_t is the type of the callback function for delete bonding information + * stored in non-volatile area. \n This type is used in R_BLE_GAP_DeleteBondInfo(). + * @param[in] p_addr The parameter returns the address of the remote device whose keys are deleted + * by R_BLE_GAP_DeleteBondInfo(). \n + * If R_BLE_GAP_DeleteBondInfo() deletes the keys of all remote devices, the parameter returns NULL. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gap_del_bond_cb_t)(st_ble_dev_addr_t * p_addr); + +/* =========================================== GAP API Params Definitions =========================================== */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_adv_param_t + * @brief Advertising parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be set the advertising parameters. + * @details + * Valid range is 0x00 - 0x03.\n + * In the first advertising parameters setting, the advertising set specified by adv_hdl is generated.\n + * The Advertising Set ID(Advertising SID) of the advertising set is same as adv_hdl. + */ + uint8_t adv_hdl; + + /** + * @brief Advertising packet type. + * @details + * Legacy advertising PDU type, or bitwise or of Extended advertising PDU type and Extended advertising option. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
categorymacrodescription
Legacy Advertising PDU typeBLE_GAP_LEGACY_PROP_ADV_IND(0x0013)Connectable and scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_DIRECT_IND(0x0015)Connectable directed (low duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_HDC_DIRECT_IND(0x001D)Connectable directed (high duty cycle) Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_SCAN_IND(0x0012)Scannable undirected Legacy Advertising Packet
BLE_GAP_LEGACY_PROP_ADV_NONCONN_IND(0x0010)Non-connectable and non-scannable undirected Legacy Advertising Packet
Extended Advertising PDU typeBLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_UNDIRECT(0x0001)Connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_DIRECT(0x0005)Connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_CONN_NOSCAN_HDC_DIRECT(0x000D)Connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_UNDIRECT(0x0002)Non-connectable and scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_DIRECT(0x0006)Non-connectable and scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_SCAN_HDC_DIRECT(0x000E)Non-connectable and scannable directed (high duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_UNDIRECT(0x0000)Non-connectable and non-scannable undirected Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_DIRECT(0x0004)Non-connectable and non-scannable directed (low duty cycle) Extended Advertising Packet
BLE_GAP_EXT_PROP_ADV_NOCONN_NOSCAN_HDC_DIRECT(0x000C)Non-connectable and non-scannable directed (high duty cycle) Extended Advertising Packet
Extended Advertising OptionBLE_GAP_EXT_PROP_ADV_ANONYMOUS(0x0020)Omit the advertiser address from Extended Advertising Packet.
BLE_GAP_EXT_PROP_ADV_INCLUDE_TX_POWER(0x0040)Indicate that the advertising data includes TX Power.
+ */ + uint16_t adv_prop_type; + + /** + * @brief Minimum advertising interval. + * @details + * Time(ms) = adv_intv_min * 0.625.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t adv_intv_min; + + /** + * @brief Maximum Advertising interval. + * @details + * Time(ms) = adv_intv_max * 0.625.\n + * Valid range is 0x00000020 - 0x00FFFFFF. + */ + uint32_t adv_intv_max; + + /** + * @brief The adv_ch_map is channels used in advertising with primary advertising channels. + * @details + * It is a bitwise OR of the following values. + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADV_CH_37(0x01) | Use 37 CH. | + * | BLE_GAP_ADV_CH_38(0x02) | Use 38 CH. | + * | BLE_GAP_ADV_CH_39(0x04) | Use 39 CH. | + * | BLE_GAP_ADV_CH_ALL(0x07) | Use 37 - 39 CH. | + */ + uint8_t adv_ch_map; + + /** + * @brief Own BD Address Type. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * the random address specified by the o_addr field is used. + *
+ */ + uint8_t o_addr_type; + + /** + * @brief Random address set to the advertising set, when the o_addr_type field is BLE_GAP_ADDR_RAND. + * @details When the o_addr_type field is other than BLE_GAP_ADDR_RAND, this field is ignored. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t o_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Peer address type. + * @details + * When the Advertising PDU type is other than directed or the o_addr_type is BLE_GAP_ADDR_PUBLIC or + * BLE_GAP_ADDR_RAND,this field is ignored. + * | macro | description | + * |:------------------------- |:----------------- | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public Address | + * | BLE_GAP_ADDR_RAND(0x01) | Random Address | + */ + uint8_t p_addr_type; + + /** + * @brief Peer address. + * @details When the Advertising PDU type is other than directed or + * the o_addr_type is BLE_GAP_ADDR_PUBLIC or BLE_GAP_ADDR_RAND,this field is ignored. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t p_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Advertising Filter Policy. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_ANY(0x00)Process scan and connection requests from all devices.
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_ANY(0x01) + * Process connection requests from all devices and scan requests + * from only devices that are in the White List. + *
BLE_GAP_ADV_ALLOW_SCAN_ANY_CONN_WLST(0x02) + * Process scan requests from all devices and connection requests from + * only devices that are in the White List. + *
BLE_GAP_ADV_ALLOW_SCAN_WLST_CONN_WLST(0x03)Process scan and connection requests from only devices in the White List.
+ */ + uint8_t filter_policy; + + /** + * @brief Primary ADV PHY. + * @details + * In this parameter, only 1M PHY and Coded PHY can be specified, and 2M PHY cannot be specified. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADV_PHY_1M(0x01) + * Use 1M PHY as Primary Advertising PHY.
+ * When the adv_prop_type field is Legacy Advertising PDU type,
+ * this field shall be set to BLE_GAP_ADV_PHY_1M. + *
BLE_GAP_ADV_PHY_CD(0x03)Use Coded PHY(S=8) as Primary Advertising PHY. + * Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme().
+ */ + uint8_t adv_phy; + + /** + * @brief Secondary ADV Max Skip. + * @details + * Valid range is 0x00 - 0xFF.\n + * When this field is 0x00, AUX_ADV_IND is sent before the next advertising event.\n + * When the adv_prop_type field is Legacy Advertising PDU, this field is ignored. + */ + uint8_t sec_adv_max_skip; + + /** + * @brief Secondary ADV Phy. + * @details + * When the adv_prop_type is Legacy Advertising PDU, this field is ignored. + * | macro | description | + * |:------------------------- |:------------------------------------------------ | + * | BLE_GAP_ADV_PHY_1M(0x01) | Use 1M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_2M(0x02) | Use 2M PHY as Secondary Advertising PHY. | + * | BLE_GAP_ADV_PHY_CD(0x03) | Use Coded PHY(S=8) as Secondary Advertising PHY. | + * + * Coding scheme is configured by @ref R_BLE_VS_SetCodingScheme(). + */ + uint8_t sec_adv_phy; + + /** + * @brief Scan Request Notifications Flag. + * @details + * When the adv_prop_type field is non-scannable Advertising PDU, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_REQ_NTF_DISABLE(0x00)Disable Scan Request Notification.
BLE_GAP_SCAN_REQ_NTF_ENABLE(0x01) + * Enable Scan Request Notification.
+ * When a Scan Request Packet from Scanner has been received, + * the BLE_GAP_EVENT_SCAN_REQ_RECV event is notified. + *
+ */ + uint8_t scan_req_ntf_flag; +} st_ble_gap_ext_adv_param_t; + +/******************************************************************************************************************//** + * @brief Advertising parameters. + * @sa st_ble_gap_ext_adv_param_t + **********************************************************************************************************************/ +typedef st_ble_gap_ext_adv_param_t st_ble_gap_adv_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_data_t + * @brief Advertising data/scan response data/periodic advertising data. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be + * set advertising data/scan response/periodic advertising data. + * @details + * Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief Data type. + * @details + * | macro | description | + * |:---------------------------------- |:-------------------------- | + * | BLE_GAP_ADV_DATA_MODE (0x00) | Advertising data. | + * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data. | + * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data. | + */ + uint8_t data_type; + + /** + * @brief The length of advertising data/scan response data/periodic advertising data (in bytes). + * @details + * In case of Legacy Advertising PDU, the length is 0 - 31 bytes.\n + * In case of Extended Advertising PDU, the length is 0 - 1650 bytes.\n + * Note that the length of the advertising data/scan response data in + * the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of the advertising sets may not exceed + * the buffer size(4250 bytes) in Controller. \n + * \n + * In case of periodic advertising data, the length is 0 - 1650 bytes.\n + * Note that the length of the periodic advertising data in the BLE_MAX_NO_OF_ADV_SETS_SUPPORTED number of + * the advertising sets may not exceed the buffer size(4306 bytes) in Controller.\n + * \n + * When this field is 0, the operations specified by the zero_length_flag is executed. + */ + uint16_t data_length; + + /** + * @brief Advertising data/scan response data/periodic advertising data. + * @details + * When the data_length field is 0, this field is ignored. + */ + uint8_t * p_data; + + /** + * @brief Operation when the data_length field is 0. + * @details + * If the data_length is other than 0, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_DATA_0_CLEAR(0x01) + * Clear the advertising data/scan response data/periodic advertising data + * in the advertising set. + *
BLE_GAP_DATA_0_DID_UPD(0x02)Update Advertising DID without changing advertising data. + * If the data_type field is BLE_GAP_ADV_DATA_MODE, this value is allowed. + *
+ */ + uint8_t zero_length_flag; +} st_ble_gap_adv_data_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_adv_param_t + * @brief Periodic advertising parameter. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to be set periodic advertising parameter. + * @details + * Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief Periodic ADV Properties. + * @details + * The prop_type field is set to the following values.\n + * If the type of the periodic advertising data cannot be applied from the following, set 0x0000. + * | macro | description | + * |:---------------------------------- |:------------------------------------------------------------ | + * | BLE_GAP_PERD_PROP_TX_POWER(0x0040) | Indicate that periodic advertising data includes Tx Power. | + */ + uint16_t prop_type; + + /** + * @brief Minimum Periodic Advertising Interval. + * @details + * Time(ms) = perd_intv_min * 1.25.\n + * Valid range is 0x0006 - 0xFFFF. + */ + uint16_t perd_intv_min; + + /** + * @brief Maximum Periodic Advertising Interval. + * @details + * Time(ms) = perd_intv_max * 1.25.\n + * Valid range is 0x0006 - 0xFFFF. + */ + uint16_t perd_intv_max; +} st_ble_gap_perd_adv_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_phy_param_t + * @brief Scan parameters per scan PHY. + * @details In case of start scanning with both 1M PHY and Coded PHY, + * adjust scan windows and scan intervals according to the following.\n + * ``` p_phy_param_1M->scan_window / p_phy_param_1M->scan_intv + + * p_phy_param_coded->scan_window / p_phy_param_coded->scan_intv <= 1 ``` + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Scan type. + * @details + * | macro | description | + * |:-------------------------------|:--------------------------- | + * | BLE_GAP_SCAN_PASSIVE(0x00) | Passive Scan. | + * | BLE_GAP_SCAN_ACTIVE(0x01) | Active Scan. | + */ + uint8_t scan_type; + + /** + * @brief Scan interval. + * @details + * interval(ms) = scan_intv * 0.625.\n + * Valid range is 0x0000 and 0x0004 - 0xFFFF. + */ + uint16_t scan_intv; + + /** + * @brief Scan window. + * @details + * window(ms) = scan_window * 0.625.\n + * Valid range is 0x0000 and 0x0004 - 0xFFFF. + */ + uint16_t scan_window; +} st_ble_gap_scan_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_scan_param_t + * @brief Scan parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Own BD Address Type. + * @details + * In case of passive scan, this field is ignored. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.
+ * If the IRK of local device has not been registered in Resolving List, + * the random address set by R_BLE_GAP_SetRandAddr() is used. + *
+ */ + uint8_t o_addr_type; + + /** + * @brief Scan Filter Policy. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_ALLOW_ADV_ALL(0x00) + * Accept all advertising and scan response PDUs except directed advertising + * PDUs not addressed to local device. + *
BLE_GAP_SCAN_ALLOW_ADV_WLST(0x01) + * Accept only advertising and scan response PDUs from remote devices + * whose address is registered in the White List.
+ * Directed advertising PDUs which are not addressed to local device is ignored. + *
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED(0x02) + * Accept all advertising and scan response PDUs except directed advertising + * PDUs whose the target address is identity address but doesn't address local device. + * However directed advertising PDUs whose the target address is the local resolvable private address + * are accepted. + *
BLE_GAP_SCAN_ALLOW_ADV_EXCEPT_DIRECTED_WLST(0x03)Accept all advertising and scan response PDUs.
+ * The following are excluded.
+ *
    + *
  • + * Advertising and scan response PDUs where the advertiser's + * identity address is not in the White List. + *
    • + *
  • + * Directed advertising PDUs whose the target address is identity address + * but doesn't address local device. + * However directed advertising PDUs whose the target address is the local + * resolvable private address are accepted. + *
    • + *
+ *
+ */ + uint8_t filter_policy; + + /** + * @brief Scan parameters 1M PHY. + * @details When this field is NULL, Controller doesn't set the scan parameters for 1M PHY. + */ + st_ble_gap_scan_phy_param_t * p_phy_param_1M; + + /** + * @brief Scan parameters Coded PHY. + * @details When this field is NULL, Controller doesn't set the scan parameters for Coded PHY. + */ + st_ble_gap_scan_phy_param_t * p_phy_param_coded; +} st_ble_gap_ext_scan_param_t; + +/******************************************************************************************************************//** + * @brief Scan parameters. + * @sa st_ble_gap_ext_scan_param_t + **********************************************************************************************************************/ +typedef st_ble_gap_ext_scan_param_t st_ble_gap_scan_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_on_t + * @brief Parameters configured when scanning starts. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Procedure type. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SC_PROC_OBS(0x00) + * Observation Procedure.
+ * Notify all advertising PDUs. + *
BLE_GAP_SC_PROC_LIM(0x01) + * Limited Discovery Procedure.
+ * Notify advertising PDUs from only devices in the limited discoverable mode. + *
BLE_GAP_SC_PROC_GEN(0x02) + * General Discovery Procedure.
+ * Notify advertising PDUs from devices in the limited discoverable mode and + * the general discoverable mode. + *
+ */ + uint8_t proc_type; + + /** + * @brief Filter duplicates. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_SCAN_FILT_DUPLIC_DISABLE(0x00)Duplicate filter disabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE(0x01)Duplicate filter enabled.
BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02)Duplicate filtering enabled, reset for each scan period
+ */ + uint8_t filter_dups; + + /** + * @brief Scan duration. + * @details Time(ms) = duration * 10.\n + * Valid range is 0x0000 - 0xFFFF.\n + * If this field is set to 0x0000, scanning is continued until R_BLE_GAP_StopScan() is called.\n + * When the period field is zero and the time specified the duration field expires, + * BLE_GAP_EVENT_SCAN_TO event notifies the application layer that scanning stops. + */ + uint16_t duration; + + /** + * @brief Scan period. + * @details Time(s) = N * 1.28.\n + * Valid range is 0x0000 - 0xFFFF.\n + * If the duration field is set to 0x0000, this field is ignored. + */ + uint16_t period; +} st_ble_gap_scan_on_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_param_t + * @brief Connection parameters included in connection interval, slave latency, supervision timeout, ce length. + * @details This structure is used in R_BLE_GAP_CreateConn() and R_BLE_GAP_UpdConn(). + * + * Set the fields in this structure to match the following condition. + * + * Supervision_timeout(ms) >= (1 + conn_latency) * conn_intv_max_Time(ms) + * + * conn_intv_max_Time(ms) = conn_intv_max * 1.25 + * Supervision_timeout(ms) = sup_to * 10 + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Minimum connection interval. + * @details + * Time(ms) = conn_intv_min * 1.25.\n + * Valid range is 0x0006 - 0x0C80. + */ + uint16_t conn_intv_min; + + /** + * @brief Maximum connection interval. + * @details + * Time(ms) = conn_intv_max * 1.25.\n + * Valid range is 0x0006 - 0x0C80. + */ + uint16_t conn_intv_max; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Time(ms) = sup_to * 10.\n + * Valid range is 0x000A - 0x0C80. + */ + uint16_t sup_to; + + /** + * @brief Minimum CE Length. + * @details + * Valid range is 0x0000 - 0xFFFF. + */ + uint16_t min_ce_length; + + /** + * @brief Maximum CE Length. + * @details + * Valid range is 0x0000 - 0xFFFF. + */ + uint16_t max_ce_length; +} st_ble_gap_conn_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_phy_param_t + * @brief Connection parameters per PHY. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Scan interval. + * @details + * Time(ms) = scan_intv * 0.625.\n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t scan_intv; + + /** + * @brief Scan window. + * @details + * Time(ms) = scan_window * 0.625.\n + * Valid range is 0x0004 - 0xFFFF. + */ + uint16_t scan_window; + + /** + * @brief Connection interval, slave latency, supervision timeout, and CE length. + */ + st_ble_gap_conn_param_t * p_conn_param; +} st_ble_gap_conn_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_create_conn_param_t + * @brief Connection parameters used in R_BLE_GAP_CreateConn(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field specifies whether the White List is used or not, when connecting with a remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_INIT_FILT_USE_ADDR(0x00)White List is not used.
+ * The remote device to be connected is specified by the remote_bd_addr field and
+ * the remote_bd_addr_type field is used. + *
BLE_GAP_INIT_FILT_USE_WLST(0x01)White List is used.
+ * The remote device registered in White List is connected with local device.
+ * The remote_bd_addr field and the remote_bd_addr_type field are ignored. + *
+ */ + uint8_t init_filter_policy; + + /** + * @brief Address of the device to be connected. + * @note The BD address setting format is little endian. \n + * If the address is "AA:BB:CC:DD:EE:FF", set the byte array in the order + * {0xFF, 0xEE, 0xDD, 0xCC, 0xBB, 0xAA}. + */ + uint8_t remote_bd_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Address type of the device to be connected. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address or Public Identity Address
BLE_GAP_ADDR_RAND(0x01)Random Address or Random (Static) Identity Address
+ */ + uint8_t remote_bd_addr_type; + + /** + * @brief Address type which local device uses in creating a link with the remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_ADDR_PUBLIC(0x00)Public Address
BLE_GAP_ADDR_RAND(0x01)Random Address
BLE_GAP_ADDR_RPA_ID_PUBLIC(0x02) + * Resolvable Private Address.\n + * If the IRK of local device has not been registered in Resolving List, + * public address is used. + *
BLE_GAP_ADDR_RPA_ID_RANDOM(0x03) + * Resolvable Private Address.\n + * If the IRK of local device has not been registered in Resolving List, + * the random address set by R_BLE_GAP_SetRandAddr(). + *
+ */ + uint8_t own_addr_type; + + /** + * @brief Connection parameters for 1M PHY. + * @details If this field is set to NULL, 1M PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_1M; + + /** + * @brief Connection parameters for 2M PHY. + * @details If this field is set to NULL, 2M PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_2M; + + /** + * @brief Connection parameters for Coded PHY. + * @details If this field is set to NULL, Coded PHY is not used in connecting. + */ + st_ble_gap_conn_phy_param_t * p_conn_param_coded; +} st_ble_gap_create_conn_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_rslv_list_key_set_t + * @brief IRK of a remote device and IRK type of local device used in R_BLE_GAP_ConfRslvList(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief IRK of a remote device to be registered in the Resolving List. + */ + uint8_t remote_irk[BLE_GAP_IRK_SIZE]; + + /** + * @brief IRK type of the local device to be registered in the Resolving List. + * @details + * | macro | description | + * |:------------------------------------- |:-------------------------------------------------- | + * | BLE_GAP_RL_LOC_KEY_ALL_ZERO(0x00) | All-zero IRK. | + * | BLE_GAP_RL_LOC_KEY_REGISTERED(0x01) | The IRK registered by R_BLE_GAP_SetLocIdInfo(). | + */ + uint8_t local_irk_type; +} st_ble_gap_rslv_list_key_set_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_phy_param_t + * @brief PHY configuration parameters used in R_BLE_GAP_SetPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Transmitter PHY preference. + * @details The tx_phys field is set to a bitwise OR of the following values. All other values are ignored. + * | macro | description | + * |:------------------------------------- |:---------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Use 1M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Use 2M PHY for Transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Use Coded PHY for Transmitter PHY. | + */ + uint8_t tx_phys; + + /** + * @brief Receiver PHY preference. + * @details The rx_phys field is set to a bitwise OR of the following values. All other values are ignored. + * | macro | description | + * |:------------------------------------- |:---------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Use 1M PHY for Receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Use 2M PHY for Receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Use Coded PHY for Receiver PHY. | + */ + uint8_t rx_phys; + + /** + * @brief Coding scheme used in Coded PHY. + * @details Select one of the following. + * | macro | description | + * |:---------------------------------------- |:----------------------- | + * | BLE_GAP_SET_PHYS_OP_HOST_NO_PREF(0x00) | No preferred coding. | + * | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_2(0x01) | Use S=2 coding. | + * | BLE_GAP_SET_PHYS_OP_HOST_PREF_S_8(0x02) | Use S=8 coding. | + */ + uint16_t phy_options; +} st_ble_gap_set_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_def_phy_param_t + * @brief PHY preferences which allows a remote device to set used in R_BLE_GAP_SetDefPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Transmitter PHY preferences which a remote device may change. + * @details The tx_phys field is set to a bitwise OR of the following values. + * All other values are ignored. + * | macro | description | + * |:------------------------------------- |:----------------------------------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Allow a remote device to set 1M PHY for transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Allow a remote device to set 2M PHY for transmitter PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Allow a remote device to set Coded PHY for transmitter PHY. | + */ + uint8_t tx_phys; + + /** + * @brief Receiver PHY preferences which a remote device may change. + * @details The rx_phys field is set to a bitwise OR of the following values. + * All other values are ignored. + * | macro | description | + * |:------------------------------------- |:-------------------------------------------------------- | + * | BLE_GAP_SET_PHYS_HOST_PREF_1M(0x01) | Allow a remote device to set 1M PHY for receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_2M(0x02) | Allow a remote device to set 2M PHY for receiver PHY. | + * | BLE_GAP_SET_PHYS_HOST_PREF_CD(0x04) | Allow a remote device to set Coded PHY for receiver PHY. | + */ + uint8_t rx_phys; +} st_ble_gap_set_def_phy_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_auth_info_t + * @brief Pairing parameters required from a remote device or + * information about keys distributed from a remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Security level. + * @details + * | value | description | + * |:--------|:----------------------------------------------------- | + * | 0x01 | The remote device requests Unauthenticated pairing. | + * | 0x02 | The remote device requests Authenticated pairing. | + */ + uint8_t security; + + /** + * @brief Pairing mode. + * @details + * | value | description | + * |:--------|:----------------------------------------------------- | + * | 0x01 | The remote device requests Legacy pairing. | + * | 0x02 | The remote device requests Secure Connections. | + */ + uint8_t pair_mode; + + /** + * @brief Bonding policy. + * @details + * | value | description | + * |:--------|:--------------------------------------------------------------- | + * | 0x00 | The remote device does not store the Bonding information. | + * | 0x01 | The remote device stores the Bonding information. | + */ + uint8_t bonding; + + /** + * @brief Encryption key size. + */ + uint8_t ekey_size; +} st_ble_gap_auth_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_dist_t + * @brief Keys distributed from a remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief LTK. + */ + uint8_t enc_info[BLE_GAP_LTK_SIZE]; + + /** + * @brief Ediv and rand. + * The first two bytes is ediv, the remaining bytes are rand. + */ + uint8_t mid_info[BLE_GAP_EDIV_SIZE + BLE_GAP_RAND_64_BIT_SIZE]; + + /** + * @brief IRK + */ + uint8_t id_info[BLE_GAP_IRK_SIZE]; + + /** + * @brief Identity address. The first byte is address type. The remaining bytes are device address. + */ + uint8_t id_addr_info[BLE_GAP_ID_ADDR_SIZE]; + + /** + * @brief CSRK + */ + uint8_t sign_info[BLE_GAP_CSRK_SIZE]; +} st_ble_gap_key_dist_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_ex_param_t + * @brief This structure includes the distributed keys and negotiated LTK size. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Key information. + */ + st_ble_gap_key_dist_t * p_keys_info; + + /** + * @brief Type of the distributed keys. + * @details + * This field is a bitwise OR of the following values. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Bit Numberdescription
0 + * LTK and Master Identification.
+ * LTK is distributed in Secure Connections, even if the bit is 1. + *
1IRK and Identity Address Information.
2CSRK
+ */ + uint8_t keys; + + /** + * @brief The negotiated LTK size. + */ + uint8_t ekey_size; +} st_ble_gap_key_ex_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_param_t + * @brief Pairing parameters used in R_BLE_GAP_SetPairingParams(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief IO capabilities of local device. + * @details + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_IOCAP_DISPLAY_ONLY(0x00) + * Output function : Local device has the ability to display a 6 digit decimal number.
+ * Input function : None
+ *
BLE_GAP_IOCAP_DISPLAY_YESNO(0x01) + * Output function : Output function : Local device has the ability to + * display a 6 digit decimal number.
+ * Input function : Local device has the ability to indicate 'yes' or 'no'
+ *
BLE_GAP_IOCAP_KEYBOARD_ONLY(0x02) + * Output function : None
+ * Input function : Local device has the ability to input the number '0' - '9'.
+ *
BLE_GAP_IOCAP_NOINPUT_NOOUTPUT(0x03) + * Output function : None
+ * Input function : None
+ *
BLE_GAP_IOCAP_KEYBOARD_DISPLAY(0x04) + * Output function : Output function : Local device has the ability to + * display a 6 digit decimal number.
+ * Input function : Local device has the ability to input the number '0' - '9'.
+ *
+ */ + uint8_t iocap; + + /** + * @brief MITM protection policy. + * @details + * Select one of the following. + * | macro | description | + * |:---------------------------------- |:------------------------------ | + * | BLE_GAP_SEC_MITM_BEST_EFFORT(0x00) | MITM Protection not required. | + * | BLE_GAP_SEC_MITM_STRICT (0x01) | MITM Protection required. | + */ + uint8_t mitm; + + /** + * @brief Bonding policy. + * @details + * | macro | description | + * |:---------------------------------- |:------------------------------------------------- | + * | BLE_GAP_BONDING_NONE(0x00) | Local device doesn't stores Bonding information. | + * | BLE_GAP_BONDING (0x01) | Local device stores Bonding information. | + */ + uint8_t bonding; + + /** + * @brief Maximum LTK size(in bytes). + * @details + * Valid range is 7 - 16.\n + * This field shall be set to a value not less than the min_key_size field. + */ + uint8_t max_key_size; + + /** + * @brief Minimum LTK size(in bytes). + * @details + * Valid range is 7 - 16.\n + * This field shall be set to a value not more than the max_key_size field. + */ + uint8_t min_key_size; + + /** + * @brief Type of keys to be distributed from local device. + * @details + * The loc_key_dist field is set to a bitwise OR of the following values. + * | macro | description | + * |:-------------------------------|:--------------------------- | + * | BLE_GAP_KEY_DIST_ENCKEY(0x01) | LTK | + * | BLE_GAP_KEY_DIST_IDKEY(0x02) | IRK and Identity Address. | + * | BLE_GAP_KEY_DIST_SIGNKEY(0x04) | CSRK | + */ + uint8_t loc_key_dist; + + /** + * @brief Type of keys which local device requests a remote device to distribute. + * @details + * The rem_key_dist field is set to a bitwise OR of the following values. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GAP_KEY_DIST_ENCKEY(0x01) + * LTK. In case of Secure Connections, LTK is notified even if this bit is not set. + *
BLE_GAP_KEY_DIST_IDKEY(0x02) + * IRK and Identity Address. + *
BLE_GAP_KEY_DIST_SIGNKEY(0x04) + * CSRK + *
+ */ + uint8_t rem_key_dist; + + /** + * @brief Support for Key Press Notification in Passkey Entry. + * @details + * | macro | description | + * |:-----------------------------------------|:---------------------------------------- | + * | BLE_GAP_SC_KEY_PRESS_NTF_NOT_SPRT(0x00) | Not support for Key Press Notification. | + * | BLE_GAP_SC_KEY_PRESS_NTF_SPRT(0x01) | Support for Key Press Notification. | + */ + uint8_t key_notf; + + /** + * @brief Determine whether to accept only Secure Connections or not. + * @details + * | macro | description | + * |:------------------------------|:--------------------------------------------- | + * | BLE_GAP_SC_BEST_EFFORT(0x00) | Accept Legacy pairing and Secure Connections. | + * | BLE_GAP_SC_STRICT(0x01) | Accept only Secure Connections. | + */ + uint8_t sec_conn_only; +} st_ble_gap_pairing_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_oob_data_t + * @brief Oob data received from the remote device. This is used in R_BLE_GAP_SetRemOobData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief OOB data used in Legacy Pairing. + */ + uint8_t legacy_oob[BLE_GAP_LEGACY_OOB_SIZE]; + + /** + * @brief OOB confirmation value used in Secure Connections. + */ + uint8_t sc_cnf_val[BLE_GAP_OOB_CONFIRM_VAL_SIZE]; + + /** + * @brief OOB rand used in Secure Connections. + */ + uint8_t sc_rand[BLE_GAP_OOB_RANDOM_VAL_SIZE]; +} st_ble_gap_oob_data_t; + +/* ============================================== GAP Event Parameters ============================================== */ + +/* Event Code : BLE_GAP_EVENT_STACK_ON : none */ + +/* Event Code : BLE_GAP_EVENT_STACK_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_LOC_VER_INFO : st_ble_gap_loc_dev_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ver_num_t + * @brief Version number of host stack. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Major version number. + */ + uint8_t major; + + /** + * @brief Minor version number. + */ + uint8_t minor; + + /** + * @brief Subminor version number. + */ + uint8_t subminor; +} st_ble_gap_ver_num_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_loc_ver_info_t + * @brief Version number of Controller. + * @details Refer Bluetooth SIG Assigned Number(https://www.bluetooth.com/specifications/assigned-numbers). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Bluetooth HCI version. + */ + uint8_t hci_ver; + + /** + * @brief Bluetooth HCI revision. + */ + uint16_t hci_rev; + + /** + * @brief Link Layer revision. + */ + uint8_t lmp_ver; + + /** + * @brief Manufacturer ID. + */ + uint16_t mnf_name; + + /** + * @brief Link Layer subversion. + */ + uint16_t lmp_sub_ver; +} st_ble_gap_loc_ver_info_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_loc_dev_info_evt_t + * @brief Version information of local device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Bluetooth Device Address. + */ + st_ble_dev_addr_t l_dev_addr; + + /** + * @brief Version number of host stack in local device. + */ + st_ble_gap_ver_num_t l_ver_num; + + /** + * @brief Version number of Controller in local device. + */ + st_ble_gap_loc_ver_info_t l_bt_info; +} st_ble_gap_loc_dev_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_HW_ERR : st_ble_gap_hw_err_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_hw_err_evt_t + * @brief Hardware error that is notified from Controller. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The hw_code field indicates the cause of the hardware error. + */ + uint8_t hw_code; +} st_ble_gap_hw_err_evt_t; + +/* Event Code : BLE_GAP_EVENT_CMD_ERR: st_ble_gap_cmd_err_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_cmd_err_evt_t + * @brief HCI Command error. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The opcode of HCI Command which caused the error. + */ + uint16_t op_code; + + /** + * @brief Module ID which caused the error. + */ + uint32_t module_id; +} st_ble_gap_cmd_err_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_REPT_IND: st_ble_gap_adv_rept_evt_t */ +/* ADV report related Event defines */ +/* Legacy ADV Report related structure */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_rept_t + * @brief Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Advertising Reports received. + */ + uint8_t num; + + /** + * @brief Type of Advertising Packet. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuerdescription
0x00Connectable and scannable undirected advertising(ADV_IND).
0x01Connectable directed advertising(ADV_DIRECT_IND).
0x02Scannable undirected advertising(ADV_SCAN_IND).
0x03Non-connectable undirected advertising(ADV_NONCONN_IND).
0x04Scan response(SCAN_RSP).
+ */ + uint8_t adv_type; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_addr; + + /** + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 31. + */ + uint8_t len; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Advertising data/Scan Response Data. + */ + uint8_t * p_data; +} st_ble_gap_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_ext_adv_rept_t + * @brief Extended Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Advertising Reports received. + */ + uint8_t num; + + /** + * @brief Type of Advertising Packet. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Bit Numberdescription
0Connectable advertising.
1Scannable advertising.
2Directed advertising.
3Scan response.
4Legacy advertising PDU.
5-6The status of Advertising Data/Scan Response Data.
+ * Data Status:
+ * 00b = Complete
+ * 01b = Incomplete, more data come
+ * 10b = Incomplete, data truncated, no more to come
+ *
All other bitsReserved for future use
+ */ + uint16_t adv_type; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFF | Anonymous advertisement. | + */ + uint8_t addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_addr; + + /** + * @brief The primary PHY configuration of the advertiser. + * @details + * The primary PHY configuration of the advertiser. + * | value | description | + * |:--------- |:------------------------ | + * | 0x01 | 1M PHY | + * | 0x03 | Coded PHY | + */ + uint8_t adv_phy; + + /** + * @brief The secondary PHY configuration of the advertiser. + * @details + * | value | description | + * |:--------- |:---------------------------------------------------------------- | + * | 0x00 | Nothing has been received with Secondary Advertising Channel. | + * | 0x01 | The Secondary Advertising PHY configuration was 1M PHY. | + * | 0x02 | The Secondary Advertising PHY configuration was 2M PHY. | + * | 0x03 | The Secondary Advertising PHY configuration was Coded PHY. | + */ + uint8_t sec_adv_phy; + + /** + * @brief Advertising SID included in the received Advertising Report. + * @details Valid range is 0 <= adv_sid <= 0x0F and 0xFF.\n + * If the adv_sid is 0xFF, there is no field which includes SID. + */ + uint8_t adv_sid; + + /** + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that Tx power could not be retrieved. + */ + int8_t tx_pwr; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If the tx_pwr is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Periodic Advertising interval. + * @details If the perd_adv_intv is 0x0000, it means that this advertising is not periodic advertising.\n + * If the perd_adv_intv is 0x0006 - 0xFFFF, + * it means that this field is the Periodic Advertising interval.\n + * Periodic Advertising interval = per_adv_intr * 1.25ms. + */ + uint16_t perd_adv_intv; + + /** + * @brief The address type of Direct Advertising PDU. + * @details + * | value | description | + * |:--------- |:--------------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + * | 0xFE | Resolvable Privacy Address which could not be resolved in Controller. | + */ + uint8_t dir_addr_type; + + /** + * @brief Address of Direct Advertising PDU. + * @note The BD address setting format is little endian. + */ + uint8_t * p_dir_addr; + + /** + * @brief Length of Advertising data(in bytes). + * @details Valid range is 0 - 229. + */ + uint8_t len; + + /** + * @brief Advertising data/Scan Response Data. + */ + uint8_t * p_data; +} st_ble_gap_ext_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_adv_rept_t + * @brief Periodic Advertising Report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle. + * @details Valid range is 0x0000 - 0x0EFF. + */ + uint16_t sync_hdl; + + /** + * @brief TX power(in dBm). + * @details Valid range is -127 <= tx_pwr <= 20 and 127.\n + * If tx_pwr is 127, it means that Tx power could not be retrieved. + */ + int8_t tx_pwr; + + /** + * @brief RSSI(in dBm). + * @details Valid range is -127 <= rssi <= 20 and 127.\n + * If rssi is 127, it means that RSSI could not be retrieved. + */ + int8_t rssi; + + /** + * @brief Reserved for future use. + */ + uint8_t rfu; + + /** + * @brief Reserved for future use. + * @details + * | value | description | + * |:--------- |:------------------------------------------------------- | + * | 0x00 | Data Complete. | + * | 0x01 | Data incomplete, more data to come. | + * | 0x02 | Data incomplete, data truncated, no more to come. | + */ + uint8_t data_status; + + /** + * @brief Length of Periodic Advertising data(in bytes). + * @details Valid range is 0 - 247. + */ + uint8_t len; + + /** + * @brief Periodic Advertising data. + */ + uint8_t * p_data; +} st_ble_gap_perd_adv_rept_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_rept_evt_t + * @brief Advertising report. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Data type. + * @details + * | value | description | + * |:-------------------- |:---------------------------------- | + * | 0x00 | Advertising Report. | + * | 0x01 | Extended Advertising Report. | + * | 0x02 | Periodic Advertising Report. | + * + * If the BLE Protocol Stack library type is "extended", + * the adv_rpt_type field in a Legacy Advertising Report event is 0x01. + */ + uint8_t adv_rpt_type; + + /** + * @brief Advertising Report. + */ + union + { + /** + * @brief Advertising Report. + */ + st_ble_gap_adv_rept_t * p_adv_rpt; + + /** + * @brief Extended Advertising Report. + */ + st_ble_gap_ext_adv_rept_t * p_ext_adv_rpt; + + /** + * @brief Periodic Advertising Report. + */ + st_ble_gap_perd_adv_rept_t * p_per_adv_rpt; + } param; +} st_ble_gap_adv_rept_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_ON : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_OFF : st_ble_gap_adv_set_evt_t */ +/* Event Code : BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP : st_ble_gap_adv_set_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_set_evt_t + * @brief Advertising handle. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle specifying the advertising set configured advertising parameters. + */ + uint8_t adv_hdl; +} st_ble_gap_adv_set_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_OFF : st_ble_gap_adv_off_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_off_evt_t + * @brief Information about the advertising set which stops advertising. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set which has stopped advertising. + * @details Valid range is 0x00 - 0x03. + */ + uint8_t adv_hdl; + + /** + * @brief The reason for stopping advertising. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x01 + * Advertising has been stopped by R_BLE_GAP_StopAdv(). + *
0x02 + * Because the duration specified by R_BLE_GAP_StartAdv() was expired, + * advertising has terminated. + *
0x03 + * Because the max_extd_adv_evts parameter specified by R_BLE_GAP_StartAdv() was reached, + * advertising has terminated. + *
0x04 + * Because the connection was established with the remote device, advertising has terminated. + *
+ */ + uint8_t reason; + + /** + * @brief Connection handle. + * @details If the reason field is 0x04, this field indicates connection handle identifying + * the remote device connected with local device. + * If other reasons, ignore this field. + */ + uint16_t conn_hdl; + + /** + * @brief The number of the advertising event that has been received until advertising has terminated. + * @details If max_extd_adv_evts by R_BLE_GAP_StartAdv() is not 0, this parameter is valid. + */ + uint8_t num_comp_ext_adv_evts; +} st_ble_gap_adv_off_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_DATA_UPD_COMP : st_ble_gap_adv_data_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_adv_data_evt_t + * @brief This structure notifies that advertising data has been set to Controller by R_BLE_GAP_SetAdvSresData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set to + * which advertising data/scan response data/periodic advertising data is set. + */ + uint8_t adv_hdl; + + /** + * @brief Type of the data set to the advertising set. + * @details + * | value | description | + * |:------------------------------------ |:--------------------------- | + * | BLE_GAP_ADV_DATA_MODE(0x00) | Advertising data | + * | BLE_GAP_SCAN_RSP_DATA_MODE(0x01) | Scan response data | + * | BLE_GAP_PERD_ADV_DATA_MODE(0x02) | Periodic advertising data | + */ + uint8_t data_type; +} st_ble_gap_adv_data_evt_t; + +/* Event Code : BLE_GAP_EVENT_ADV_SET_REMOVE_COMP : st_ble_gap_rem_adv_set_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rem_adv_set_evt_t + * @brief This structure notifies that an advertising set has been removed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field indicates that the advertising set has been removed or cleared. + * @details + * | value | description | + * |:-------- |:--------------------------------------- | + * | 0x01 | The advertising set has been removed. | + * | 0x02 | The advertising set has been cleared. | + */ + uint8_t remove_op; + + /** + * @brief Advertising handle identifying the advertising set which has been removed. + * @details If the advertising set has been cleared, this field is ignored. + */ + uint8_t adv_hdl; +} st_ble_gap_rem_adv_set_evt_t; + +/* Event Code : BLE_GAP_EVENT_SCAN_ON : none */ +/* Event Code : BLE_GAP_EVENT_SCAN_OFF : none */ + +/* Event Code : BLE_GAP_EVENT_CONN_IND : st_ble_gap_conn_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_evt_t + * @brief This structure notifies that a link has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the created link. + */ + uint16_t conn_hdl; + + /** + * @brief The role of the link. + * @details + * | value | description | + * |:-------- |:-------------- | + * | 0x00 | Master | + * | 0x01 | Slave | + */ + uint8_t role; + + /** + * @brief Address type of the remote device. + * @details + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
valuedescription
0x00Public Address
0x01Random Address
0x02Public Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + *
0x03Random Identity Address.
+ * It indicates that the Controller could resolve the resolvable private address of the remote device. + * 		+ *
+ */ + uint8_t remote_addr_type; + + /** + * @brief Address of the remote device. + * @note The BD address setting format is little endian. + */ + uint8_t remote_addr[BLE_BD_ADDR_LEN]; + + /** + * @brief Resolvable private address that local device used in connection procedure. + * @details + * The local device address used in creating the link when the address type was set to + * BLE_GAP_ADDR_RPA_ID_PUBLIC or BLE_GAP_ADDR_RPA_ID_RANDOM by R_BLE_GAP_SetAdvParam() or + * R_BLE_GAP_CreateConn(). + * If the address type was set to other than BLE_GAP_ADDR_RPA_ID_PUBLIC and + * BLE_GAP_ADDR_RPA_ID_RANDOM, this field is set to all-zero. + * @note The BD address setting format is little endian. + */ + uint8_t local_rpa[BLE_BD_ADDR_LEN]; + + /** + * @brief Resolvable private address that the remote device used in connection procedure. + * @details + * This field indicates the remote resolvable private address when remote_addr_type is 0x02 or 0x03. + * If remote_addr_type is other than 0x02 and 0x03, this field is set to all-zero. + * @note The BD address setting format is little endian. + */ + uint8_t remote_rpa[BLE_BD_ADDR_LEN]; + + /** + * @brief Connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.Time(ms) = sup_to * 10. + */ + uint16_t sup_to; + + /** + * @brief Master_Clock_Accuracy. + * @details + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | + */ + uint8_t clk_acc; +} st_ble_gap_conn_evt_t; + +/* Event Code : BLE_GAP_EVENT_DISCONN_IND : st_ble_gap_disconn_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_disconn_evt_t + * @brief This structure notifies that a link has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link disconnected. + */ + uint16_t conn_hdl; + + /** + * @brief The reason for disconnection. + * @details + * Refer Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + */ + uint8_t reason; +} st_ble_gap_disconn_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_CANCEL_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_WHITE_LIST_CONF_COMP : st_ble_gap_white_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RAND_ADDR_SET_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_CH_MAP_RD_COMP : st_ble_gap_rd_ch_map_evt_t */ +/* Read Channel MAP */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_ch_map_evt_t + * @brief This structure notifies that Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link whose Channel Map was retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Channel Map. + */ + uint8_t ch_map[BLE_GAP_CH_MAP_SIZE]; +} st_ble_gap_rd_ch_map_evt_t; + +/* Event Code : BLE_GAP_EVENT_CH_MAP_SET_COMP : none */ + +/* Event Code : BLE_GAP_EVENT_RSSI_RD_COMP : st_ble_gap_rd_rssi_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_rssi_evt_t + * @brief This structure notifies that RSSI has been retrieved by R_BLE_GAP_ReadRssi(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link whose RSSI was retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief RSSI(in dBm). + * @details + * Valid range is -127 < rssi < 20 and 127.\n + * If this field is 127, it indicates that RSSI could not be retrieved. + */ + int8_t rssi; +} st_ble_gap_rd_rssi_evt_t; + +/* Event Code : BLE_GAP_EVENT_GET_REM_DEV_INFO : st_ble_gap_dev_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_dev_info_evt_t + * @brief This structure notifies that information about remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device whose information has been retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Information about the remote device. This field is a bitwise OR of the following values. + * @details + * | Bit Number | description | + * |:-------------------|:------------------------------- | + * | bit0 | Address | + * | bit1 | Version, company_id, subversion | + * | bit2 | Feature | + * | All other bits | Reserved for future use | + */ + uint8_t get_status; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t addr; + + /** + * @brief The version of Link Layer of the remote device. + * @details + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + */ + uint8_t version; + + /** + * @brief The manufacturer ID of the remote device. + * @details + * Refer to Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers) regarding defined number. + */ + uint16_t company_id; + + /** + * @brief The subversion of Link Layer. + */ + uint16_t subversion; + + /** + * @brief LE feature supported in the remote device. + * @details + * Refer to Core Spec Vol 6, Part B 4.6 FEATURE SUPPORT. + */ + uint8_t features[BLE_GAP_REM_FEATURE_SIZE]; +} st_ble_gap_dev_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_COMP : st_ble_gap_conn_upd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_upd_evt_t + * @brief This structure notifies that connection parameters has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the connection whose parameters has been updated. + */ + uint16_t conn_hdl; + + /** + * @brief Updated Connection Interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv * 1.25. + */ + uint16_t conn_intv; + + /** + * @brief Updated slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Updated supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10. + */ + uint16_t sup_to; +} st_ble_gap_conn_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_CONN_PARAM_UPD_REQ : st_ble_gap_conn_upd_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_upd_req_evt_t + * @brief This structure notifies that a request for connection parameters update has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that was requested to update connection parameters. + */ + uint16_t conn_hdl; + + /** + * @brief Minimum connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_min * 1.25. + */ + uint16_t conn_intv_min; + + /** + * @brief Maximum connection interval. + * @details + * Valid range is 0x0006 - 0x0C80.\n + * Time(ms) = conn_intv_max * 1.25. + */ + uint16_t conn_intv_max; + + /** + * @brief Slave latency. + * @details + * Valid range is 0x0000 - 0x01F3. + */ + uint16_t conn_latency; + + /** + * @brief Supervision timeout. + * @details + * Valid range is 0x000A - 0x0C80.\n + * Time(ms) = sup_to * 10 + */ + uint16_t sup_to; +} st_ble_gap_conn_upd_req_evt_t; + +/* Event Code : RBLE_GAP_EVENT_CONN_PARAM_UPD_RSP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED : st_ble_gap_conn_hdl_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_conn_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only connection handle has occurred. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle. + */ + uint16_t conn_hdl; +} st_ble_gap_conn_hdl_evt_t; + +/* Event Code : BLE_GAP_EVENT_DATA_LEN_CHG : st_ble_gap_data_len_chg_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_data_len_chg_evt_t + * @brief This structure notifies that the packet data length has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that updated Data Length. + */ + uint16_t conn_hdl; + + /** + * @brief Updated transmission packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. + */ + uint16_t tx_octets; + + /** + * @brief Updated transmission time(us). + * @details + * Valid range is 0x0148 - 0x4290. + */ + uint16_t tx_time; + + /** + * @brief Updated receive packet size(in bytes). + * @details + * Valid range is 0x001B - 0x00FB. + */ + uint16_t rx_octets; + + /** + * @brief Updated receive time(us). + * @details + * Valid range is 0x0148 - 0x4290. + */ + uint16_t rx_time; +} st_ble_gap_data_len_chg_evt_t; + +/* Event Code : BLE_GAP_EVENT_RSLV_LIST_CONF_COMP : st_ble_gap_rslv_list_conf_evt_t */ + +/* Event Code : BLE_GAP_EVENT_RPA_EN_COMP : none */ +/* Event Code : BLE_GAP_EVENT_SET_RPA_TO_COMP : none */ +/* Event Code : BLE_GAP_EVENT_RD_RPA_COMP : st_ble_gap_rd_rpa_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_rd_rpa_evt_t + * @brief This structure notifies that the local resolvable private address has been retrieved by R_BLE_GAP_ReadRpa(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The resolvable private address of local device. + */ + st_ble_dev_addr_t addr; +} st_ble_gap_rd_rpa_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_UPD : st_ble_gap_phy_upd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_phy_upd_evt_t + * @brief This structure notifies that PHY for a connection has been updated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been updated. + */ + uint16_t conn_hdl; + + /** + * @brief Transmitter PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + */ + uint8_t tx_phy; + + /** + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | + */ + uint8_t rx_phy; +} st_ble_gap_phy_upd_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_RD_COMP : st_ble_gap_phy_rd_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_phy_rd_evt_t + * @brief This structure notifies that the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been retrieved the PHY settings. + */ + uint16_t conn_hdl; + + /** + * @brief Transmitter PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The transmitter PHY has been updated to 1M PHY. | + * | 0x02 | The transmitter PHY has been updated to 2M PHY. | + * | 0x03 | The transmitter PHY has been updated to Coded PHY. | + */ + uint8_t tx_phy; + + /** + * @brief Receiver PHY. + * @details + * | value | description | + * |:-----------|:------------------------------------------------------------ | + * | 0x01 | The receiver PHY has been updated to 1M PHY. | + * | 0x02 | The receiver PHY has been updated to 2M PHY. | + * | 0x03 | The receiver PHY has been updated to Coded PHY. | + */ + uint8_t rx_phy; +} st_ble_gap_phy_rd_evt_t; + +/* Event Code : BLE_GAP_EVENT_PHY_SET_COMP : st_ble_gap_conn_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SCAN_REQ_RECV : st_ble_gap_scan_req_recv_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_scan_req_recv_evt_t + * @brief This structure notifies that a Scan Request packet has been received from a Scanner. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Advertising handle identifying the advertising set that has received the Scan Request. + */ + uint8_t adv_hdl; + + /** + * @brief Address type of the Scanner. + * @details + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t scanner_addr_type; + + /** + * @brief Address of the Scanner. + * @note The BD address setting format is little endian. + */ + uint8_t scanner_addr[BLE_BD_ADDR_LEN]; +} st_ble_gap_scan_req_recv_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_EST : st_ble_gap_sync_est_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sync_est_evt_t + * @brief This structure notifies that a Periodic sync has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle identifying the Periodic Sync that has been established. + */ + uint16_t sync_hdl; + + /** + * @brief Advertising SID identifying the advertising set that has established the Periodic Sync. + */ + uint8_t adv_sid; + + /** + * @brief Address type of the advertiser. + * @details + * | value | description | + * |:-----------|:-------------------------------------------------------------- | + * | 0x00 | Public Address. | + * | 0x01 | Random Address. | + * | 0x02 | Public Identity Address which could be resolved in Controller. | + * | 0x03 | Random Identity Address which could be resolved in Controller. | + */ + uint8_t adv_addr_type; + + /** + * @brief Address of the advertiser. + * @note The BD address setting format is little endian. + */ + uint8_t * p_adv_addr; + + /** + * @brief Advertising PHY. + * @details + * | value | description | + * |:-----------|:---------------------------- | + * | 0x01 | Advertiser PHY is 1M PHY. | + * | 0x02 | Advertiser PHY is 2M PHY. | + * | 0x03 | Advertiser PHY is Coded PHY. | + */ + uint8_t adv_phy; + + /** + * @brief Periodic Advertising Interval. + * @details + * Valid range is 0x0006 - 0xFFFF.\n + * Time(ms) = perd_adv_intv * 1.25. + */ + uint16_t perd_adv_intv; + + /** + * @brief Advertiser Clock Accuracy. + * @details + * | value | description | + * |:---------|:--------------------------- | + * | 0x00 | 500ppm | + * | 0x01 | 250ppm | + * | 0x02 | 150ppm | + * | 0x03 | 100ppm | + * | 0x04 | 75ppm | + * | 0x05 | 50ppm | + * | 0x06 | 30ppm | + * | 0x07 | 20ppm | + */ + uint8_t adv_clk_acc; +} st_ble_gap_sync_est_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_TERM : st_ble_gap_sync_hdl_evt_t */ +/* Event Code : BLE_GAP_EVENT_SYNC_LOST : st_ble_gap_sync_hdl_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sync_hdl_evt_t + * @brief This structure notifies that a GAP Event that includes only sync handle has occurred. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Sync handle. + */ + uint16_t sync_hdl; +} st_ble_gap_sync_hdl_evt_t; + +/* Event Code : BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP : none */ +/* Event Code : BLE_GAP_EVENT_PERD_LIST_CONF_COMP : st_ble_gap_perd_list_conf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_white_list_conf_evt_t + * @brief This structure notifies that White List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for White List. + * @details + * | value | description | + * |:---------|:---------------------------------------- | + * | 0x01 | A device was added to White List. | + * | 0x02 | A device was deleted from White List. | + * | 0x03 | White List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from White List. + */ + uint8_t num; +} st_ble_gap_white_list_conf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_rslv_list_conf_evt_t + * @brief This structure notifies that Resolving List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for Resolving List. + * @details + * | value | description | + * |:---------|:-------------------------------------------- | + * | 0x01 | A device was added to Resolving List. | + * | 0x02 | A device was deleted from Resolving List. | + * | 0x03 | Resolving List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from Resolving List. + */ + uint8_t num; +} st_ble_gap_rslv_list_conf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_perd_list_conf_evt_t + * @brief This structure notifies that Periodic Advertiser List has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The operation for Periodic Advertiser List. + * @details + * | value | description | + * |:---------|:------------------------------------------------------ | + * | 0x01 | A device was added to Periodic Advertiser List. | + * | 0x02 | A device was deleted from Periodic Advertiser List. | + * | 0x03 | Periodic Advertiser List was cleared. | + */ + uint8_t op_code; + + /** + * @brief The number or devices which have been added to or deleted from Periodic Advertiser List. + */ + uint8_t num; +} st_ble_gap_perd_list_conf_evt_t; + +/* Event Code : BLE_GAP_EVENT_PRIV_MODE_SET_COMP : st_ble_gap_set_priv_mode_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_set_priv_mode_evt_t + * @brief This structure notifies that Privacy Mode has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number or devices which have been set privacy mode. + */ + uint8_t num; +} st_ble_gap_set_priv_mode_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_REQ : st_ble_gap_pairing_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_req_evt_t + * @brief This structure notifies that a pairing request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that sent the pairing request. + */ + uint16_t conn_hdl; + + /** + * @brief The address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief The Pairing parameters of the remote device. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_PASSKEY_ENTRY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ : st_ble_gap_passkey_display_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_passkey_display_evt_t + * @brief This structure notifies that a request for Passkey display in pairing has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that requested Passkey display. + */ + uint16_t conn_hdl; + + /** + * @brief Passkey. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t passkey; +} st_ble_gap_passkey_display_evt_t; + +/* Event Code : BLE_GAP_EVENT_NUM_COMP_REQ : st_ble_gap_num_comp_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_num_comp_evt_t + * @brief This structure notifies that a request for Numeric Comparison in pairing has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that requested Numeric Comparison. + */ + uint16_t conn_hdl; + + /** + * @brief The number to be confirmed in Numeric Comparison. + * @details This field is a 6 digit decimal number(000000-999999). + */ + uint32_t numeric; +} st_ble_gap_num_comp_evt_t; + +/* Event Code : BLE_GAP_EVENT_KEY_PRESS_NTF : st_ble_gap_key_press_ntf_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_key_press_ntf_evt_t + * @brief This structure notifies that the remote device has input a key in Passkey Entry + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that input a key. + */ + uint16_t conn_hdl; + + /** + * @brief Type of the key that the remote device input. + * @details + * | value | description | + * |:---------|:----------------------------- | + * | 0x00 | Passkey entry started. | + * | 0x01 | Passkey digit entered. | + * | 0x02 | Passkey digit erased. | + * | 0x03 | Passkey cleared. | + * | 0x04 | Passkey entry completed. | + */ + uint8_t key_type; +} st_ble_gap_key_press_ntf_evt_t; + +/* Event Code : BLE_GAP_EVENT_PAIRING_COMP : st_ble_gap_pairing_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_pairing_info_evt_t + * @brief This structure notifies that the pairing has completed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that the pairing has been done with. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Key information exchanged in pairing. + * @details If local device supports bonding, store the information in non-volatile memory + * in order to set it to host stack after power re-supply. + */ + st_ble_gap_auth_info_t auth_info; +} st_ble_gap_pairing_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_ENC_CHG : st_ble_gap_enc_chg_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_enc_chg_evt_t + * @brief This structure notifies that the encryption status of a link has been changed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the link that has been changed. + */ + uint16_t conn_hdl; + + /** + * @brief Encryption Status. + * @details + * | value | description | + * |:---------|:-------------------------------------------------------- | + * | 0x00 | Encryption OFF. | + * | 0x01 | Encryption ON. | + * | 0x03 | Encryption updated by Encryption Key Refresh Completed. | + */ + uint8_t enc_status; +} st_ble_gap_enc_chg_evt_t; + +/* Event Code : BLE_GAP_EVENT_PEER_KEY_INFO : st_ble_gap_peer_key_info_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_peer_key_info_evt_t + * @brief This structure notifies that the remote device has distributed the keys. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device that has distributed the keys. + */ + uint16_t conn_hdl; + + /** + * @brief Address of the remote device. + */ + st_ble_dev_addr_t bd_addr; + + /** + * @brief Distributed keys. + * @details + * If local device supports bonding, store the keys in non-volatile memory and + * at power re-supply set to the host stack by R_BLE_GAP_SetBondInfo(). + */ + st_ble_gap_key_ex_param_t key_ex_param; +} st_ble_gap_peer_key_info_evt_t; + +/* Event Code : BLE_GAP_EVENT_EX_KEY_REQ : st_ble_gap_conn_hdl_evt_t */ + +/* Event Code : BLE_GAP_EVENT_LTK_REQ : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_req_evt_t + * @brief This structure notifies that a LTK request from a remote device has been received. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device which requests for the LTK. + */ + uint16_t conn_hdl; + + /** + * @brief Ediv. + */ + uint16_t ediv; + + /** + * @brief Rand. + */ + uint8_t * p_peer_rand; +} st_ble_gap_ltk_req_evt_t; + +/* Event Code : BLE_GAP_EVENT_LTK_RSP_COMP : st_ble_gap_ltk_req_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_ltk_rsp_evt_t + * @brief This structure notifies that local device has replied to the LTK request from the remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device to be sent the response to the LTK request. + */ + uint16_t conn_hdl; + + /** + * @brief The response to the LTK request. + * @details + * | value | description | + * |:---------|:----------------------------------------------------------------------- | + * | 0x00 | Local device replied with the stored LTK. | + * | 0x01 | Local device rejected the LTK request, because the LTK was not found. | + */ + uint8_t response; +} st_ble_gap_ltk_rsp_evt_t; + +/* Event Code : BLE_GAP_EVENT_SC_OOB_CREATE_COMP : st_ble_gap_sc_oob_data_evt_t */ + +/******************************************************************************************************************//** + * @struct st_ble_gap_sc_oob_data_evt_t + * @brief This structure notifies that OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Confirmation value(16 bytes) of OOB Data. + */ + uint8_t * p_sc_oob_conf; + + /** + * @brief Rand(16bytes) of OOB Data. + */ + uint8_t * p_sc_oob_rand; +} st_ble_gap_sc_oob_data_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gap_bond_info_t + * @brief Bonding information used in R_BLE_GAP_SetBondInfo(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the device which exchanged the keys. + */ + st_ble_dev_addr_t * p_addr; + + /** + * @brief Information about the keys. + */ + st_ble_gap_auth_info_t * p_auth_info; + + /** + * @brief Keys distributed from the remote device in paring. + */ + st_ble_gap_key_ex_param_t * p_keys; +} st_ble_gap_bond_info_t; + +/*@}*/ + +/* ================================================= GAP Event Code ================================================= */ + +/** @addtogroup GAP_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @enum e_ble_gap_evt_t + * @brief GAP Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief Invalid GAP Event. + * + * ## Event Code: 0x1001 + * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_INVALID = 0x1001, + + /* Range for Generic events - 0x01 to 0x0F */ + + /** + * @brief Host Stack has been initialized. + * @details + * When initializing host stack by R_BLE_GAP_Init() has been completed, + * BLE_GAP_EVENT_STACK_ON event is notified. + * + * ## Event Code: 0x1002 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_ON, + + /** + * @brief Host Stack has been terminated. + * @details + * When terminating host stack by R_BLE_GAP_Terminate() has been completed, + * BLE_GAP_EVENT_STACK_OFF event is notified. + * + * ## Event Code: 0x1003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008)When function was called, host stack has not yet been initialized.
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_STACK_OFF, + + /** + * @brief Version information of local device. + * @details + * When version information of local device has been retrieved by R_BLE_GAP_GetVerInfo(), + * BLE_GAP_EVENT_LOC_VER_INFO event is notified. + * + * ## Event Code: 0x1004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_loc_dev_info_evt_t + */ + BLE_GAP_EVENT_LOC_VER_INFO, + + /** + * @brief Hardware Error. + * @details + * When hardware error has been received from Controller, BLE_GAP_EVENT_HW_ERR event is notified. + * + * ## Event Code: 0x1005 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_hw_err_evt_t + */ + BLE_GAP_EVENT_HW_ERR, + + /** + * @brief Command Status Error. + * @details + * When the error of HCI Command has occurred after a R_BLE GAP API call, BLE_GAP_EVENT_CMD_ERR event is notified. + * + * ## Event Code: 0x1101 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_cmd_err_evt_t + */ + BLE_GAP_EVENT_CMD_ERR = 0x1101, + + /** + * @brief Advertising Report. + * @details + * When advertising PDUs has been received after scanning was started by R_BLE_GAP_StartScan(). + * + * ## Event Code: 0x1102 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_rept_evt_t + */ + BLE_GAP_EVENT_ADV_REPT_IND, + + /** + * @brief Advertising parameters have been set. + * @details + * Advertising parameters have been configured by R_BLE_GAP_SetAdvParam(). + * + * ## Event Code: 0x1103 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising type that doesn't support advertising data/scan response data was + * specified to the advertising set which has already set + * advertising data/scan response data. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - Advertising parameters were configured to the advertising set in advertising.
+ * - The sec_adv_phy field in adv_paran was not specified + * when Periodic Advertising was started. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_PARAM_SET_COMP, + + /** + * @brief Advertising data has been set. + * @details + * This event notifies that Advertising Data/Scan Response Data/Periodic Advertising Data has been + * set to the advertising set by R_BLE_GAP_SetAdvSresData(). + * + * ## Event Code: 0x1104 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * The reason for this error is as follows.
+ * - The advertising set that doesn't support advertising data/scan response data + * was set to the data.
+ * - The advertising set that supports legacy advertising was set to + * advertising data/scan response data larger than 31 bytes.
+ * - The advertising set that has advertising data/scan response data greater + * than or equal to 252 bytes was set the data in advertising.
+ * - The advertising set that has periodic advertising data greater than or equal to + * 253 bytes was set the data in advertising. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Length exceeded the length that the advertising set could be set. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetAdvSresData() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_data_evt_t + */ + BLE_GAP_EVENT_ADV_DATA_UPD_COMP, + + /** + * @brief Advertising has started. + * @details + * When advertising has been started by R_BLE_GAP_StartAdv(), this event is notified to the application layer. + * + * ## Event Code: 0x1105 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows.
+ * - The advertising data length set to the advertising set + * for connectable extended advertising was invalid.
+ * - If o_addr_type field in adv_param used in R_BLE_GAP_SetAdvParam() is 0x03, + * the address which is set in o_addr field of adv_param + * has not been registered in Resolving List. + *
BLE_ERR_INVALID_OPERATION(0x0009)Setting of advertising data/scan response data has not been completed.
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StartAdv() has not been created. + *
BLE_ERR_LIMIT_EXCEEDED(0x0010)When the maximum connections are established, a new connectable advertising tried starting.
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_ON, + + /** + * @brief Advertising has stopped. + * @details + * This event notifies the application layer that advertising has stopped. + * + * ## Event Code: 0x1106 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StopAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_off_evt_t + */ + BLE_GAP_EVENT_ADV_OFF, + + /** + * @brief Periodic advertising parameters have been set. + * @details + * This event notifies the application layer that Periodic Advertising Parameters + * has been configured by R_BLE_GAP_SetPerdAdvParam(). + * + * ## Event Code: 0x1107 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertising set was the setting for anonymous advertising. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * The advertising set was configured to the parameters in periodic advertising. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_SetPerdAdvParam() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP, + + /** + * @brief Periodic advertising has started. + * @details + * When Periodic Advertising has been started by R_BLE_GAP_StartPerdAdv(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1108 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * The periodic advertising data set in the advertising set has not been completed. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StartPerdAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_ON, + + /** + * @brief Periodic advertising has stopped. + * @details + * When Periodic Advertising has terminated by R_BLE_GAP_StopPerdAdv(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1109 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_StopPerdAdv() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_adv_set_evt_t + */ + BLE_GAP_EVENT_PERD_ADV_OFF, + + /** + * @brief Advertising set has been deleted. + * @details + * When the advertising set has been removed by R_BLE_GAP_RemoveAdvSet(), + * this event is notified to the application layer. + * + * ## Event Code: 0x110A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When the advertising set was in advertising, R_BLE_GAP_RemoveAdvSet() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The advertising set specified by R_BLE_GAP_RemoveAdvSet() has not been created. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rem_adv_set_evt_t + */ + BLE_GAP_EVENT_ADV_SET_REMOVE_COMP, + + /** + * @brief Scanning has started. + * @details + * When scanning has started by R_BLE_GAP_StartScan(), + * this event is notified to the application layer. + * + * ## Event Code: 0x110B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows:
+ * - Scan interval or scan window was invalid. + * - When filter_dup field in scan_enable was BLE_GAP_SCAN_FILT_DUPLIC_ENABLE_FOR_PERIOD(0x02), + * period field in scan_enable was 0. + * - duration field in scan_enable was larger than period in scan_enable. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * In scanning, R_BLE_GAP_StartScan() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_ON, + + /** + * @brief Scanning has stopped. + * @details + * When scanning has been stopped by R_BLE_GAP_StopScan(), this event is notified to the application layer. + * + * ## Event Code: 0x110C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_OFF, + + /** + * @brief Scanning has stopped, because duration specified by API expired. + * @details + * When the scan duration specified by R_BLE_GAP_StartScan() has expired, + * this event notifies scanning has stopped. + * + * ## Event Code: 0x110D + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SCAN_TO, + + /** + * @brief Connection Request has been sent to Controller. + * @details + * This event notifies a request for a connection has been sent to Controller. + * + * ## Event Code: 0x110E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The reason for this error is as follows:
+ * - Scan interval or scan windows specified by R_BLE_GAP_CreateConn() is invalid. + * - Although the own_addr_type field in p_param was set to 0x03, + * random address had not been registered in Resolving List. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * R_BLE_GAP_CreateConn() was called while creating a link + * by previous R_BLE_GAP_CreateConn() call . + *
BLE_ERR_LIMIT_EXCEEDED(0x0010) + * When the maximum connections are established, R_BLE_GAP_CreateConn() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CREATE_CONN_COMP, + + /** + * @brief Link has been established. + * @details + * This event notifies a link has been established. + * + * ## Event Code: 0x110F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_evt_t + */ + BLE_GAP_EVENT_CONN_IND, + + /** + * @brief Link has been disconnected. + * @details + * This event notifies a link has been disconnected. + * + * ## Event Code: 0x1110 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_disconn_evt_t + */ + BLE_GAP_EVENT_DISCONN_IND, + + /** + * @brief Connection Cancel Request has been sent to Controller. + * @details + * This event notifies the request for a connection has been cancelled by R_BLE_GAP_CancelCreateConn(). + * + * ## Event Code: 0x1111 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When a request for a connection has not been sent to Controller, + * R_BLE_GAP_CancelCreateConn() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CONN_CANCEL_COMP, + + /** + * @brief The White List has been configured. + * @details + * When White List has been configured, this event is notified to the application layer. + * + * ## Event Code: 0x1112 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * While doing advertising or scanning or creating a link with the White List, + * R_BLE_GAP_ConfWhiteList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * White List has already registered the maximum number of devices. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_white_list_conf_evt_t + */ + BLE_GAP_EVENT_WHITE_LIST_CONF_COMP, + + /** + * @brief Random address has been set to Controller. + * @details + * This event notifies Controller has been set the random address by R_BLE_GAP_SetRandAddr(). + * + * ## Event Code: 0x1113 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When local device was in legacy advertising, R_BLE_GAP_SetRandAddr() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_RAND_ADDR_SET_COMP, + + /** + * @brief Channel Map has been retrieved. + * @details + * This event notifies Channel Map has been retrieved by R_BLE_GAP_ReadChMap(). + * + * ## Event Code: 0x1114 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_ReadChMap() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_ch_map_evt_t + */ + BLE_GAP_EVENT_CH_MAP_RD_COMP, + + /** + * @brief Channel Map has set. + * @details + * This event notifies Channel Map has been configured by R_BLE_GAP_SetChMap(). + * + * ## Event Code: 0x1115 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The channel map specified by R_BLE_GAP_SetChMap() was all-zero. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CH_MAP_SET_COMP, + + /** + * @brief RSSl has been retrieved. + * @details + * This event notifies RSSI has been retrieved by R_BLE_GAP_ReadRssi(). + * + * ## Event Code: 0x1116 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_ReadRssi() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_rssi_evt_t + */ + BLE_GAP_EVENT_RSSI_RD_COMP, + + /** + * @brief Information about the remote device has been retrieved. + * @details + * This event notifies information about the remote device has been retrieved by R_BLE_GAP_GetRemDevInfo(). + * + * ## Event Code: 0x1117 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_dev_info_evt_t + */ + BLE_GAP_EVENT_GET_REM_DEV_INFO, + + /** + * @brief Connection parameters has been configured. + * @details + * This event notifies the connection parameters has been updated. + * + * ## Event Code: 0x1118 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_DATA(0x0002) + * Local device rejected the request for updating connection parameters. + *
BLE_ERR_INVALID_ARG(0x0003) + * The remote device rejected the connection parameters suggested from local device. + *
BLE_ERR_UNSUPPORTED(0x0007) + * The remote device doesn't support connection parameters update feature. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_upd_evt_t + */ + BLE_GAP_EVENT_CONN_PARAM_UPD_COMP, + + /** + * @brief Local device has received the request for configuration of connection parameters. + * @details + * This event notifies the request for connection parameters update has been received. + * + * ## Event Code: 0x1119 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_upd_req_evt_t + */ + BLE_GAP_EVENT_CONN_PARAM_UPD_REQ, + + /** + * @brief Authenticated Payload Timeout. + * @details + * This event notifies Authenticated Payload Timeout has occurred. + * + * ## Event Code: 0x111A + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_AUTH_PL_TO_EXPIRED, + + /** + * @brief The request for update transmission packet size and transmission time have been sent to Controller. + * @details + * This event notifies a request for updating packet data length and transmission timer has been sent to Controller. + * + * ## Event Code: 0x111B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The tx_octets or tx_time parameter specified by R_BLE_GAP_SetDataLen() is invalid. + *
BLE_ERR_UNSUPPORTED(0x0007) + * The remote device does not support updating packet data length and transmission time. + *
BLE_ERR_INVALID_HDL(0x000E) + * When R_BLE_GAP_SetDataLen() was called, the connection was not established. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_SET_DATA_LEN_COMP, + + /** + * @brief Transmission packet size and transmission time have been changed. + * @details + * This event notifies packet data length and transmission time have been updated. + * + * ## Event Code: 0x111C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_data_len_chg_evt_t + */ + BLE_GAP_EVENT_DATA_LEN_CHG, + + /** + * @brief The Resolving List has been configured. + * @details + * When Resolving List has been configured by R_BLE_GAP_ConfRslvList(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111D + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, + * before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * While doing advertising or scanning or creating a link with resolvable private address, + * R_BLE_GAP_ConfRslvList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Resolving List has already registered the maximum number of devices. + *
BLE_ERR_INVALID_HDL(0x000E) + * The specified Identity Address was not found in Resolving List. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rslv_list_conf_evt_t + */ + BLE_GAP_EVENT_RSLV_LIST_CONF_COMP, + + /** + * @brief Resolvable private address function has been enabled or disabled. + * @details + * When Resolvable Private Address function in Controller has been enabled by R_BLE_GAP_EnableRpa(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_EnableRpa() was called. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_RPA_EN_COMP, + + /** + * @brief The update time of resolvable private address has been changed. + * @details + * When Resolvable Private Address Timeout in Controller has been updated by R_BLE_GAP_SetRpaTo(), + * this event is notified to the application layer. + * + * ## Event Code: 0x111F + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The rpa_timeout parameter specified by R_BLE_GAP_SetRpaTo() is out of range. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SET_RPA_TO_COMP, + + /** + * @brief The resolvable private address of local device has been retrieved. + * @details + * When the resolvable private address of local device has been retrieved by R_BLE_GAP_ReadRpa(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1120 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The identity address specified by R_BLE_GAP_ReadRpa() was not registered in Resolving List. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_rd_rpa_evt_t + */ + BLE_GAP_EVENT_RD_RPA_COMP, + + /** + * @brief PHY for connection has been changed. + * @details + * This event notifies the application layer that PHY for a connection has been updated. + * + * ## Event Code: 0x1121 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_phy_upd_evt_t + */ + BLE_GAP_EVENT_PHY_UPD, + + /** + * @brief The request for updating PHY for connection has been sent to Controller. + * @details + * When Controller has received a request for updating PHY for a connection by R_BLE_GAP_SetPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1122 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The remote device specified by R_BLE_GAP_SetPhy() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PHY_SET_COMP, + + /** + * @brief The request for setting default PHY has been sent to Controller. + * @details + * When the PHY preferences which a remote device may change has been configured by R_BLE_GAP_SetDefPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1123 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_DEF_PHY_SET_COMP, + + /** + * @brief PHY configuration has been retrieved. + * @details + * When the PHY settings has been retrieved by R_BLE_GAP_ReadPhy(), + * this event is notified to the application layer. + * + * ## Event Code: 0x1124 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E) + * The link specified by R_BLE_GAP_ReadPhy() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_phy_rd_evt_t + */ + BLE_GAP_EVENT_PHY_RD_COMP, + + /** + * @brief Scan Request has been received. + * @details + * This event notifies the application layer that a Scan Request packet has been received from a Scanner. + * + * ## Event Code: 0x1125 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_scan_req_recv_evt_t + */ + BLE_GAP_EVENT_SCAN_REQ_RECV, + + /** + * @brief The request for establishing a periodic sync has been sent to Controller. + * @details + * This event notifies the application layer that Controller has received a request + * for a Periodic Sync establishment. + * + * ## Event Code: 0x1126 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When R_BLE_GAP_CreateSync() was called, + * this event for previous the API call has not been received. + *
BLE_ERR_ALREADY_IN_PROGRESS(0x000A) + * The advertising set specified by R_BLE_GAP_CreateSync() has already established + * a periodic sync. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_CREATE_SYNC_COMP, + + /** + * @brief The periodic advertising sync has been established. + * @details + * This event notifies the application layer that a Periodic sync has been established. + * + * ## Event Code: 0x1127 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_NOT_YET_READY(0x0012) + * The request for a Periodic Sync establishment was cancelled by R_BLE_GAP_CancelCreateSync(). + *
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_est_evt_t + */ + BLE_GAP_EVENT_SYNC_EST, + + /** + * @brief The periodic advertising sync has been terminated. + * @details + * This event notifies the application layer that the Periodic Sync has been terminated + * by R_BLE_GAP_TerminateSync(). + * + * ## Event Code: 0x1128 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * While establishing a Periodic Sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_TerminateSync() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The sync handle specified by R_BLE_GAP_TerminateSync() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_SYNC_TERM, + + /** + * @brief The periodic advertising sync has been lost. + * @details + * This event notifies the application layer that the Periodic Sync has been lost. + * + * ## Event Code: 0x1129 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_sync_hdl_evt_t + */ + BLE_GAP_EVENT_SYNC_LOST, + + /** + * @brief The request for cancel of establishing a periodic advertising sync has been sent to Controller. + * @details + * This event notifies the request for a Periodic Sync establishment has been cancelled + * by R_BLE_GAP_CancelCreateSync(). + * + * ## Event Code: 0x112A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_OPERATION(0x0009) + * When R_BLE_GAP_CancelCreateSync() was called, + * a request for a Periodic Sync establishment by R_BLE_GAP_CreateSync() + * has not been sent to Controller. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP, + + /** + * @brief The Periodic Advertiser list has been configured. + * @details + * When Periodic Advertiser List has been configured by R_BLE_GAP_ConfPerdAdvList(), + * this event is notified to the application layer. + * + * ## Event Code: 0x112B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003) + * The advertiser has already been registered in Periodic Advertiser List. + *
BLE_ERR_INVALID_STATE(0x0008) + * The add or delete operation was called, before the previous clear operation has been completed. + *
BLE_ERR_INVALID_OPERATION(0x0009) + * When establishing a periodic sync by R_BLE_GAP_CreateSync(), + * R_BLE_GAP_ConfPerdAdvList() was called. + *
BLE_ERR_MEM_ALLOC_FAILED(0x000C) + * Periodic Advertiser List has already registered the maximum number of devices. + *
BLE_ERR_INVALID_HDL(0x000E) + * The device specified by R_BLE_GAP_ConfPerdAdvList() was not found. + *
+ *
+ * + * ## Event Data: + * st_ble_gap_perd_list_conf_evt_t + */ + BLE_GAP_EVENT_PERD_LIST_CONF_COMP, + + /** + * @brief Privacy Mode has been configured. + * @details + * This event notifies the application layer that the Privacy Mode has been configured by R_BLE_GAP_SetPrivMode(). + * + * ## Event Code: 0x112B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)Address type or privacy mode is out of range.
BLE_ERR_INVALID_OPERATION(0x0009) + * While advertising, scanning, or establishing a link with resolvable private address, + * R_BLE_GAP_SetPrivMode() was called. + *
BLE_ERR_INVALID_HDL(0x000E) + * The address specified by R_BLE_GAP_SetPrivMode() has not been registered + * in Resolving List. + *
+ *
+ * + * ## Event Data: + * none + */ + BLE_GAP_EVENT_PRIV_MODE_SET_COMP, + + /** + * @brief The pairing request from a remote device has been received. + * @details + * This event notifies the application layer that a pairing request from a remote device has been received. + * + * ## Event Code: 0x1401 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_pairing_info_evt_t + */ + BLE_GAP_EVENT_PAIRING_REQ = 0x1401, + + /** + * @brief The request for input passkey has been received. + * @details + * This event notifies that a request for Passkey input in pairing has been received. + * + * ## Event Code: 0x1402 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_PASSKEY_ENTRY_REQ, + + /** + * @brief The request for displaying a passkey has been received. + * @details + * This event notifies that a request for Passkey display in pairing has been received. + * + * ## Event Code: 0x1403 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_passkey_display_evt_t + */ + BLE_GAP_EVENT_PASSKEY_DISPLAY_REQ, + + /** + * @brief The request for confirmation with Numeric Comparison has received. + * @details + * This event notifies that a request for Numeric Comparison in pairing has been received. + * + * ## Event Code: 0x1404 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_num_comp_evt_t + */ + BLE_GAP_EVENT_NUM_COMP_REQ, + + /** + * @brief Key Notification from a remote device has been received. + * @details + * This event notifies the application layer that the remote device has input a key in Passkey Entry. + * + * ## Event Code: 0x1405 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_key_press_ntf_evt_t + */ + BLE_GAP_EVENT_KEY_PRESS_NTF, + + /** + * @brief Pairing has been completed. + * @details + * This event notifies the application layer that the pairing has completed. + * + * ## Event Code: 0x1406 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_SMP_LE_PASSKEY_ENTRY_FAIL(0x2001)PassKey Entry is failed.
BLE_ERR_SMP_LE_OOB_DATA_NOT_AVAILABLE(0x2002)OOB Data is not available.
BLE_ERR_SMP_LE_AUTH_REQ_NOT_MET(0x2003)The requested pairing can not be performed because of IO Capability.
BLE_ERR_SMP_LE_CONFIRM_VAL_NOT_MATCH(0x2004)Confirmation value does not match.
BLE_ERR_SMP_LE_PAIRING_NOT_SPRT(0x2005)Pairing is not supported.
BLE_ERR_SMP_LE_INSUFFICIENT_ENC_KEY_SIZE(0x2006)Encryption Key Size is insufficient.
BLE_ERR_SMP_LE_CMD_NOT_SPRT(0x2007)The pairing command received is not supported.
BLE_ERR_SMP_LE_UNSPECIFIED_REASON(0x2008)Pairing failed with an unspecified reason.
BLE_ERR_SMP_LE_REPEATED_ATTEMPTS(0x2009)The number of repetition exceeded the upper limit.
BLE_ERR_SMP_LE_INVALID_PARAM(0x200A)Invalid parameter is set.
BLE_ERR_SMP_LE_DHKEY_CHECK_FAIL(0x200B)DHKey Check error.
BLE_ERR_SMP_LE_NUM_COMP_FAIL(0x200C)Numeric Comparison failure.
BLE_ERR_SMP_LE_DISCONNECTED(0x200F)Disconnection in pairing.
BLE_ERR_SMP_LE_TO(0x2011) Failure due to timeout.
BLE_ERR_SMP_LE_LOC_KEY_MISSING(0x2014)Pairing/Encryption failure because local device lost the LTK.
+ *
+ * + * ## Event Data: + * st_ble_gap_pairing_info_evt_t + */ + BLE_GAP_EVENT_PAIRING_COMP, + + /** + * @brief Key Notification from a remote device has been received. + * @details + * This event notifies the application layer that the encryption status of a link has been changed. + * + * ## Event Code: 0x1407 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_enc_chg_evt_t + */ + BLE_GAP_EVENT_ENC_CHG, + + /** + * @brief Keys has been received from a remote device. + * @details + * This event notifies the application layer that the remote device has distributed the keys. + * + * ## Event Code: 0x1408 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_peer_key_info_evt_t + */ + BLE_GAP_EVENT_PEER_KEY_INFO, + + /** + * @brief The request for key distribution has been received. + * @details + * When local device has been received a request for key distribution to remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x1409 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_conn_hdl_evt_t + */ + BLE_GAP_EVENT_EX_KEY_REQ, + + /** + * @brief LTK has been request from a remote device. + * @details + * When local device has been received a LTK request from a remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x140A + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_ltk_req_evt_t + */ + BLE_GAP_EVENT_LTK_REQ, + + /** + * @brief LTK reply has been sent to Controller. + * @details + * When local device has replied to the LTK request from the remote device, + * this event is notified to the application layer. + * + * ## Event Code: 0x140B + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_ltk_rsp_evt_t + */ + BLE_GAP_EVENT_LTK_RSP_COMP, + + /** + * @brief The authentication data to be used in Secure Connections OOB has been created. + * @details + * This event notifies OOB data for Secure Connections has been generated by R_BLE_GAP_CreateScOobData(). + * + * ## Event Code: 0x140C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_gap_sc_oob_data_evt_t + */ + BLE_GAP_EVENT_SC_OOB_CREATE_COMP, +} e_ble_gap_evt_t; + +/*@}*/ + +/* ========================================== GATT Server Type Definitions ========================================== */ + +/** @addtogroup GATT_SERVER_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_value_t + * @brief Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Length of the attribute value. + */ + uint16_t value_len; + + /** + * @brief Attribute Value. + */ + uint8_t * p_value; +} st_ble_gatt_value_t; + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_hdl_value_pair_t + * @brief Attribute handle and attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle + */ + uint16_t attr_hdl; + + /** + * @brief Attribute Value + */ + st_ble_gatt_value_t value; +} st_ble_gatt_hdl_value_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_att_val_t + * @brief Queued writes Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Value for Queued Write . + */ + uint8_t * p_value; + + /** + * @brief Length of the attribute value. + */ + uint16_t value_len; + + /** + * @brief padding. + */ + uint16_t padding; +} st_ble_gatt_queue_att_val_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_pair_t + * @brief Queued writes Attribute Value. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Value for Queued Write + */ + st_ble_gatt_queue_att_val_t queue_value; + + /** + * @brief Attribute Handle + */ + uint16_t attr_hdl; +} st_ble_gatt_queue_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_queue_elm_t + * @brief Prepare Write Queue element for long chracteristic. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Part of Long Characteristic Value and Characteristic Value Handle. + */ + st_ble_gatt_queue_pair_t queue_value_pair; + + /** + * @brief Offset that indicates the location to be written. + */ + uint16_t offset; +} st_ble_gatt_queue_elm_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatt_pre_queue_t + * @brief Prepare Write Queue for long chracteristic. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Buffer start address for Write Long Characteristic Request. + */ + uint8_t * p_buf_start; + + /** + * @brief Prepare Write Queue for Long Characteristic Value. + */ + st_ble_gatt_queue_elm_t * p_queue; + + /** + * @brief Buffer length. + */ + uint16_t buffer_len; + + /** + * @brief Connection Handle. + */ + uint16_t conn_hdl; + + /** + * @brief Current buffer offset. + */ + uint16_t buf_offset; + + /** + * @brief Number of elements in the prepare write queue. + */ + uint8_t queue_size; + + /** + * @brief Index of Prepare Write Queue. + */ + uint8_t queue_idx; +} st_ble_gatt_pre_queue_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_params_t + * @brief Attribute value to be set to or retrieved from the GATT Database and the access type from the GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute value to be set to or retrieved from the GATT Database. + * Note that the address of the value field in the value field is invalid in case of read access. + */ + st_ble_gatt_value_t value; + + /** + * @brief Attribute handle identifying the attribute to be set or retrieved. + */ + uint16_t attr_hdl; + + /** + * @brief Type of the access to GATT Database from the GATT Client. + * @sa access_type_to_gatt_database + */ + uint8_t db_op; +} st_ble_gatts_db_params_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_conn_hdl_t + * @brief Information about the service or the characteristic that the attribute belongs to. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Client that accesses to the GATT DataBase. + */ + uint16_t conn_hdl; + + /** + * @brief ID of the service that the attribute belongs to. + */ + uint8_t service_id; + + /** + * @brief ID of the Characteristic that the attribute belongs to. + */ + uint8_t char_id; +} st_ble_gatts_db_conn_hdl_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_access_evt_t + * @brief This structure notifies that the GATT Database has been accessed from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Information about the service or the characteristic that the attribute belongs to. + */ + st_ble_gatts_db_conn_hdl_t * p_handle; + + /** + * @brief Attribute value to be set to or retrieved from the GATT Database + * and the access type from the GATT Client. + */ + st_ble_gatts_db_params_t * p_params; +} st_ble_gatts_db_access_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_conn_evt_t + * @brief This structure notifies that the link with the GATT Client has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Client. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gatts_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_disconn_evt_t + * @brief This structure notifies that the link with the GATT Client has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Client. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gatts_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_ex_mtu_req_evt_t + * @brief This structure notifies that a MTU Exchange Request PDU has been received from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Maximum receive MTU size by GATT Client. + */ + uint16_t mtu; +} st_ble_gatts_ex_mtu_req_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_cfm_evt_t + * @brief This structure notifies that a Confirmation PDU has been received from a GATT Client. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic sent by the Indication PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_cfm_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_by_type_rsp_evt_t + * @brief This structure notifies that a Read By Type Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read By Type Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_by_type_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_rsp_evt_t + * @brief This structure notifies that a Read Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_blob_rsp_evt_t + * @brief This structure notifies that a Read Blob Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic read by the Read Blob Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_read_blob_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_read_multi_rsp_evt_t + * @brief This structure notifies that a Read Multiple Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of attribute read by the Read Multiple Request PDU. + */ + uint8_t count; + + /** + * @brief The list of attribute read by the Read Multiple Request PDU. + */ + uint16_t * p_attr_hdl_list; +} st_ble_gatts_read_multi_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_write_rsp_evt_t + * @brief This structure notifies that a Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic written by the Write Request PDU. + */ + uint16_t attr_hdl; +} st_ble_gatts_write_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_prepare_write_rsp_evt_t + * @brief This structure notifies that a Prepare Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle identifying the Characteristic written by the Prepare Write Request PDU. + */ + uint16_t attr_hdl; + + /** + * @brief The length of written bytes by the Prepare Write Request PDU. + */ + uint16_t length; + + /** + * @brief The offset of the first octet to be written. + */ + uint16_t offset; +} st_ble_gatts_prepare_write_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_exe_write_rsp_evt_t + * @brief This structure notifies that a Execute Write Response PDU has been sent from GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The flag that indicates whether execution or cancellation. + * @details + * | value | description | + * |:-----------|:----------------- | + * | 0x00 | Cancellation. | + * | 0x01 | Execution. | + */ + uint8_t exe_flag; +} st_ble_gatts_exe_write_rsp_evt_t; + +/* GATT DB Structure */ + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_uuid_cfg_t + * @brief A structure that defines the information on the position where UUIDs are used. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The position of the defined UUID is specified by offset value in uuid_table of st_ble_gatts_db_cfg_t. + */ + uint16_t offset; + + /** + * @brief The attribute handle that indicates the first position in st_ble_gatts_db_attr_cfg_t + * for the defined UUID is specified. + */ + uint16_t first; + + /** + * @brief The attribute handle that indicates the last position in st_ble_gatts_db_attr_cfg_t + * for the defined UUID is specified. + */ + uint16_t last; +} st_ble_gatts_db_uuid_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_attr_cfg_t + * @brief A structure that defines the detailed information of the attributes. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The properties of attribute are specified. + * @details Set the following properties by a bitwise OR. + * | macro | description | + * |:------------------------------------------|:-------------------------------------- | + * | BLE_GATT_DB_READ(0x01) | Allow clients to read. | + * | BLE_GATT_DB_WRITE(0x02) | Allow clients to write. | + * | BLE_GATT_DB_WRITE_WITHOUT_RSP(0x04) | Allow clients to write. | + * | BLE_GATT_DB_READ_WRITE(0x07) | Allow clients to access of all. | + */ + uint8_t desc_prop; + + /** + * @brief The auxiliary properties of attribute are specified. + * @details Set the following properties by a bitwise OR. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_NO_AUXILIARY_PROPERTY(0x00) + * No auxiliary properties.\n + * It is invalid when used with other properties at the same time. + *
BLE_GATT_DB_FIXED_LENGTH_PROPERTY(0x01) + * Fixed length attribute value. + *
BLE_GATT_DB_AUTHORIZATION_PROPERTY(0x02) + * Attributes requiring authorization. + *
BLE_GATT_DB_ATTR_DISABLED(0x10) + * The attribute is disabled. + * If this value is set, the attribute cannot be found and accessed by a GATT Client. + * It is invalid when used with other properties at the same time. + *
BLE_GATT_DB_128_BIT_UUID_FORMAT(0x20) + * Attribute with 128 bit UUID.\n + * If this macro is not set, the attribute value is 16-bits UUID. + *
BLE_GATT_DB_PEER_SPECIFIC_VAL_PROPERTY(0x40) + * Attribute managed by each GATT Client. + *
BLE_GATT_DB_CONST_ATTR_VAL_PROPERTY(0x80) + * Fixed attribute value.\n + * Writing from Client and setting from Server are prohibited. + *
+ */ + uint8_t aux_prop; + + /** + * @brief The length of the attribute value is specified. + */ + uint16_t length; + + /** + * @brief The position of the next attribute with the same UUID + * as the defined attribute is specified by an attribute handle. + */ + uint16_t next; + + /** + * @brief The storage area of attribute value. + * @details UUID of the defined attribute is set by specifying the position of the UUID registered + * in uuid_table of st_ble_gatts_db_cfg_t with the array offset value. + */ + uint16_t uuid_offset; + + /** + * @brief Storage area of attribute value. + * @details The address in the array registered in No.1-No.4 is specified to set the attribute value storage area of the defined attribute. + */ + uint8_t * p_data_offset; +} st_ble_gatts_db_attr_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_attr_list_t + * @brief The number of attributes are stored. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of the services or the characteristics. + */ + uint8_t count; +} st_ble_gatts_db_attr_list_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_char_cfg_t + * @brief A structure that defines the detailed information of the characteristics. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The total number of attributes in the defined characteristic is specified. + */ + st_ble_gatts_db_attr_list_t list; + + /** + * @brief The first attribute handle of the characteristic is specified. + */ + uint16_t start_hdl; + + /** + * @brief The index of service to which the characteristic belongs is specified. + */ + uint8_t service_id; +} st_ble_gatts_db_char_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_serv_cfg_t + * @brief A structure that defines the detailed information of the characteristics. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The total number of service declarations in the defined service is specified. + */ + st_ble_gatts_db_attr_list_t list; + + /** + * @brief The properties of the defined service are specified. + * @details Set the security level, the security mode and the key size with a bitwise OR. + * The bit0-bit3 are specified as the security level. + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_SECURITY_UNAUTH(0x00000001)Unauthenticated pairing(Security Mode1 Security Level 2, Security Mode 2 Security Level 1)
+ * Unauthenticated pairing is required to access the service. + *
BLE_GATT_DB_SER_SECURITY_AUTH(0x00000002)Authenticated pairing(Security Mode1 Security Level 3, Security Mode 2 Security Level 2)
+ * Authenticated pairing is required to access the service. + *
BLE_GATT_DB_SER_SECURITY_SECONN(0x00000004)Authenticated LE secure connections that generates 16bytes LTK(Security Mode1 Security Level 4)
+ * Authenticated LE secure connections pairing that generates 16bytes LTK is required to access the service. If this bit is set, bit24-27 are ignored. + *
+ *
+ * The bit4 is specified as the security mode.
+ * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_SECURITY_ENC(0x00000010)Encryption
+ * Encryption by the LTK exchanged in pairing is required to access.
+ *
+ * If the security requirement of the service is not needed, + * specify the bit0-bit4 to BLE_GATT_DB_SER_NO_SECURITY_PROPERTY(0x00000000).(Security Mode1 Security Level 1)
+ * The bit24-bit27 are specified as the key size required by the defined service.
+ * Select one of the following.
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_7(0x01000000)7-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_8(0x02000000)8-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_9(0x03000000)9-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_10(0x04000000)10-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_11(0x05000000)11-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_12(0x06000000)12-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_13(0x07000000)13-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_14(0x08000000)14-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_15(0x09000000)15-byte encryption key.
BLE_GATT_DB_SER_ENCRYPT_KEY_SIZE_16(0x0A000000)16-byte encryption key.
BLE_GATT_DB_SER_ENC_KEY_SIZE_DONT_CARE(0x00000000)7-byte or larger encryption key.
+ *
+ * Other bits are reserved.
+ */ + uint32_t desc; + + /** + * @brief The start attribute handle of the defined service is specified. + */ + uint16_t start_hdl; + + /** + * @brief The end attribute handle of the defined service is specified. + */ + uint16_t end_hdl; + + /** + * @brief The start index of the characteristic that belongs to the defined service is specified. + */ + uint8_t char_start_idx; + + /** + * @brief The end index of the characteristic that belongs to the defined service is specified. + */ + uint8_t char_end_idx; +} st_ble_gatts_db_serv_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_db_cfg_t + * @brief This is the structure of GATT Database that is specified in R_BLE_GATTS_SetDbInst(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The array to register the UUID to be used. + */ + const uint8_t * p_uuid_table; + + /** + * @brief The array to register variable attribute values. + */ + uint8_t * p_attr_val_table; + + /** + * @brief The array to register fixed attribute values. + */ + const uint8_t * p_const_attr_val_table; + + /** + * @brief The array to manage the attribute values handled for each GATT client. + */ + uint8_t * p_rem_spec_val_table; + + /** + * @brief The array to register the default of the attribute value handled by each GATT client. + */ + const uint8_t * p_const_rem_spec_val_table; + + /** + * @brief The array to register information on the position where UUIDs are used. + */ + const st_ble_gatts_db_uuid_cfg_t * p_uuid_cfg; + + /** + * @brief The array to register the detailed information of attributes. + */ + const st_ble_gatts_db_attr_cfg_t * p_attr_cfg; + + /** + * @brief The array to register the detailed information of characteristics. + */ + const st_ble_gatts_db_char_cfg_t * p_char_cfg; + + /** + * @brief The array to register the detailed information of services. + */ + const st_ble_gatts_db_serv_cfg_t * p_serv_cfg; + + /** + * @brief The number of services included in the GATT Database. + */ + uint8_t serv_cnt; + + /** + * @brief The number of characteristics included in the GATT Database. + */ + uint8_t char_cnt; + + /** + * @brief The number of UUIDs included in the GATT Database. + */ + uint8_t uuid_type_cnt; + + /** + * @brief The total size of attribute value that needs to be managed for each GATT client. + */ + uint8_t peer_spec_val_cnt; +} st_ble_gatts_db_cfg_t; + +/******************************************************************************************************************//** + * @struct st_ble_gatts_evt_data_t + * @brief st_ble_gatts_evt_data_t is the type of the data notified in a GATT Server Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Client. + */ + uint16_t conn_hdl; + + /** + * @brief The size of GATT Server Event parameters. + */ + uint16_t param_len; + + /** + * @brief GATT Server Event parameters. This parameter differs in each GATT Server Event. + */ + void * p_param; +} st_ble_gatts_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_gatts_app_cb_t + * @brief ble_gatts_app_cb_t is the GATT Server Event callback function type. + * @param[in] event_type The type of GATT Server Event. + * @param[in] event_result The result of GATT Server Event + * @param[in] p_event_data Data notified by GATT Server Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gatts_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gatts_evt_data_t * p_event_data); + +/*@}*/ + +/* ========================================== GATT Client Type Definitions ========================================== */ + +/** @addtogroup GATT_CLIENT_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @struct st_ble_gatt_hdl_range_t + * @brief Attribute handle range. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Start Attribute Handle. + */ + uint16_t start_hdl; + + /** + * @brief End Attribute Handle. + */ + uint16_t end_hdl; +} st_ble_gatt_hdl_range_t; + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @struct st_ble_gattc_reliable_writes_char_pair_t + * @brief This is used in R_BLE_GATTC_ReliableWrites() to specify the pair of Characteristic Value and + * Characteristic Value Handle. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Pair of Characteristic Value and Characteristic Value Handle. + */ + st_ble_gatt_hdl_value_pair_t write_data; + + /** + * @brief Offset that indicates the location to be written. + * @details Normally, set 0 to this parameter.\n + * If this parameter sets to a value other than 0,Adjust the offset parameter and the length of + * the value to be written not to exceed the length of the Characteristic. + */ + uint16_t offset; +} st_ble_gattc_reliable_writes_char_pair_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_conn_evt_t + * @brief This structure notifies that the link with the GATT Server has been established. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Server. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gattc_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_disconn_evt_t + * @brief This structure notifies that the link with the GATT Server has been disconnected. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Address of the GATT Server. + */ + st_ble_dev_addr_t * p_addr; +} st_ble_gattc_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ex_mtu_rsp_evt_t + * @brief This structure notifies that a MTU Exchange Response PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief MTU size(in bytes) that GATT Server can receive. + */ + uint16_t mtu; +} st_ble_gattc_ex_mtu_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_serv_16_evt_t + * @brief This structure notifies that a 16-bit UUID Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle range of the 16-bit UUID service. + */ + st_ble_gatt_hdl_range_t range; + + /** + * @brief Service UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_serv_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_serv_128_evt_t + * @brief This structure notifies that a 128-bit UUID Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle range of the 128-bit UUID service. + */ + st_ble_gatt_hdl_range_t range; + + /** + * @brief Service UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_serv_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_inc_serv_16_evt_t + * @brief This structure notifies that a 16-bit UUID Included Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Service Declaration handle of the 16-bit UUID Included Service. + */ + uint16_t decl_hdl; + + /** + * @brief The contents of the Included Service. + */ + st_ble_gattc_serv_16_evt_t service; +} st_ble_gattc_inc_serv_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_inc_serv_128_evt_t + * @brief This structure notifies that a 128-bit UUID Included Service has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Service Declaration handle of the 128-bit UUID Included Service. + */ + uint16_t decl_hdl; + + /** + * @brief The contents of the Included Service. + */ + st_ble_gattc_serv_128_evt_t service; +} st_ble_gattc_inc_serv_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_16_evt_t + * @brief This structure notifies that a 16-bit UUID Characteristic has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute handle of Characteristic Declaration. + */ + uint16_t decl_hdl; + + /** + * @brief Characteristic Properties. + * @details It is a bitwise OR of the following values.\n + * Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties" + * regarding the details of the Characteristic Properties. + * | value | description | + * |:-----------|:------------------------------------ | + * | 0x01 | Broadcast property | + * | 0x02 | Read property | + * | 0x04 | Write Without Response property | + * | 0x08 | Write property | + * | 0x10 | Notify property | + * | 0x20 | Indicate property | + * | 0x40 | Authenticated Signed Writes property | + * | 0x80 | Extended Properties property | + */ + uint8_t cproperty; + + /** + * @brief Value Handle of the Characteristic. + */ + uint16_t value_hdl; + + /** + * @brief Characteristic UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_char_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_128_evt_t + * @brief This structure notifies that a 128-bit UUID Characteristic has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Declaration. + */ + uint16_t decl_hdl; + + /** + * @brief Characteristic Properties. + * @details It is a bitwise OR of the following values.\n + * Refer to Core Spec [Vol.3] Generic Attribute Profile(GATT) "3.3.1.1 Characteristic Properties" + * regarding the details of the Characteristic Properties. + * | value | description | + * |:-----------|:------------------------------------ | + * | 0x01 | Broadcast property | + * | 0x02 | Read property | + * | 0x04 | Write Without Response property | + * | 0x08 | Write property | + * | 0x10 | Notify property | + * | 0x20 | Indicate property | + * | 0x40 | Authenticated Signed Writes property | + * | 0x80 | Extended Properties property | + */ + uint8_t cproperty; + + /** + * @brief Value Handle of the Characteristic. + */ + uint16_t value_hdl; + + /** + * @brief Characteristic UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_char_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_desc_16_evt_t + * @brief This structure notifies that a 16-bit UUID Characteristic Descriptor has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Descriptor. + */ + uint16_t desc_hdl; + + /** + * @brief Characteristic Descriptor UUID. + */ + uint16_t uuid_16; +} st_ble_gattc_char_desc_16_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_desc_128_evt_t + * @brief This structure notifies that a 128-bit UUID Characteristic Descriptor has been discovered. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Attribute Handle of Characteristic Descriptor. + */ + uint16_t desc_hdl; + + /** + * @brief Characteristic Descriptor UUID. + */ + uint8_t uuid_128[BLE_GATT_128_BIT_UUID_SIZE]; +} st_ble_gattc_char_desc_128_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_err_rsp_evt_t + * @brief This structure notifies that a Error Response PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The op code of the ATT Request that causes the Error Response. + * | op_code | + * |:--------------------------------------| + * | Exchange MTU Request(0x02) | + * | Find Information Request(0x04) | + * | Find By Type Value Request(0x06) | + * | Read By Type Request(0x08) | + * | Read Request(0x0A) | + * | Read Blob Request(0x0C) | + * | Read Multiple Request(0x0E) | + * | Read by Group Type Request(0x10) | + * | Write Request(0x12) | + * | Prepare Write Request(0x16) | + * | Execute Write Request(0x18) | + */ + uint8_t op_code; + + /** + * @brief Attribute handle that is target for the request. + */ + uint16_t attr_hdl; + + /** + * @brief The error codes notified from the GATT Server. + * @details It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined in + * Core Spec and Core Spec Supplement. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred, the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute. + *
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported. + *
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient. + *
0x3080 - 0x309F + * Application Error. + * The upper layer defines the error codes. + *
0x30E0 - 0x30FF + * The error code defined in Common Profile and + * Service Error Core Specification Supplement(CSS).
+ * CSS ver.7 defines the error codes from 0x30FC to 0x30FF. + *
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC) + * The Write Request has not been completed due to the reason other than Permission. + *
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.
+ */ + uint16_t rsp_code; +} st_ble_gattc_err_rsp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ntf_evt_t + * @brief This structure notifies that a Notification PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Characteristic that causes the Notification. + */ + st_ble_gatt_hdl_value_pair_t data; +} st_ble_gattc_ntf_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_ind_evt_t + * @brief This structure notifies that a Indication PDU has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Characteristic that causes the Indication. + */ + st_ble_gatt_hdl_value_pair_t data; +} st_ble_gattc_ind_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_char_evt_t + * @brief This structure notifies that read response to R_BLE_GATTC_ReadChar() or R_BLE_GATTC_ReadCharUsingUuid() + * has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The contents of the Characteristic that has been read. + */ + st_ble_gatt_hdl_value_pair_t read_data; +} st_ble_gattc_rd_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_wr_char_evt_t + * @brief This structure notifies that write response to R_BLE_GATTC_WriteChar() has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Value Handle of the Characteristic/Characteristic Descriptor that has been written. + */ + uint16_t value_hdl; +} st_ble_gattc_wr_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_multi_char_evt_t + * @brief This structure notifies that read response to R_BLE_GATTC_ReadMultiChar() has been received + * from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of Value Handles of the Characteristics that has been read. + */ + uint16_t value_hdl_num; + + /** + * @brief The contents of multiple Characteristics that have been read. + */ + st_ble_gatt_value_t multi_char_val; +} st_ble_gattc_rd_multi_char_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_char_part_wr_evt_t + * @brief This structure notifies that write response to R_BLE_GATTC_WriteLongChar() or R_BLE_GATTC_ReliableWrites() + * has been received from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The data to be written to the Characteristic/Long Characteristic/Long Characteristic Descriptor. + */ + st_ble_gatt_hdl_value_pair_t write_data; + + /** + * @brief Offset that indicates the location to be written. + */ + uint16_t offset; +} st_ble_gattc_char_part_wr_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_reliable_writes_comp_evt_t + * @brief This structure notifies that a response to R_BLE_GATTC_ExecWrite() has been received + * from a GATT Server. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief This field indicates the command of the Execute Write that has been done. + * @details + * | value | description | + * |:-----------|:------------------- | + * | 0x00 | Cancel the write. | + * | 0x01 | Execute the write. | + */ + uint8_t exe_flag; +} st_ble_gattc_reliable_writes_comp_evt_t; + +/* RBLE GATT Client Command Parameters */ + +/******************************************************************************************************************//** + * @struct st_ble_gattc_rd_multi_req_param_t + * @brief This is used in R_BLE_GATTC_ReadMultiChar() to specify multiple Characteristics to be read. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief List of Value Handles that point the Characteristics to be read. + */ + uint16_t * p_hdl_list; + + /** + * @brief The number of Value Handles included in the hdl_list parameter. + */ + uint16_t list_count; +} st_ble_gattc_rd_multi_req_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_gattc_evt_data_t + * @brief st_ble_gattc_evt_data_t is the type of the data notified in a GATT Client Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the GATT Server. + */ + uint16_t conn_hdl; + + /** + * @brief The size of GATT Client Event parameters. + */ + uint16_t param_len; + + /** + * @brief GATT Client Event parameters. This parameter differs in each GATT Client Event. + */ + void * p_param; +} st_ble_gattc_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_gattc_app_cb_t + * @brief ble_gattc_app_cb_t is the GATT Client Event callback function type. + * @param[in] event_type The type of GATT Client Event. + * @param[in] event_result The result of GATT Client Event + * @param[in] p_event_data Data notified by GATT Client Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_gattc_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_gattc_evt_data_t * p_event_data); + +/*@}*/ + +/* ============================================= L2CAP Type Definitions ============================================= */ + +/** @addtogroup L2CAP_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @struct st_ble_l2cap_conn_req_param_t + * @brief L2CAP CBFC Channel connection request parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on local device. + */ + uint16_t local_psm; + + /** + * @brief Identifier indicating the protocol/profile that uses L2CAP CBFC Channel on remote device. + */ + uint16_t remote_psm; + + /** + * @brief MTU size(byte) receivable on L2CAP CBFC Channel. + */ + uint16_t mtu; + + /** + * @brief MPS size(byte) receivable on L2CAP CBFC Channel. + */ + uint16_t mps; + + /** + * @brief The number of LE-Frame that local device can receive. + */ + uint16_t credit; +} st_ble_l2cap_conn_req_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_conn_rsp_param_t + * @brief L2CAP CBFC Channel connection response parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel on local device. + * The valid range is 0x40-0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1. + */ + uint16_t lcid; + + /** + * @brief The response to the connection request. Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_L2CAP_CF_RSP_SUCCESS(0x0000)Notify the remote device that the connection can be established.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTH(0x0005)Notify the remote device that the connection can not be established + * because of insufficient authentication.
BLE_L2CAP_CF_RSP_RFSD_INSF_AUTRZ(0x0006)Notify the remote device that the connection can not be established + * because of insufficient Authorization.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC_KEY(0x0007)Notify the remote device that the connection can not be established + * because of Encryption Key Size.
BLE_L2CAP_CF_RSP_RFSD_INSF_ENC(0x0008)Notify the remote device that the connection can not be established + * because of Encryption.
BLE_L2CAP_CF_RSP_RFSD_UNAC_PARAM(0x000B)Notify the remote device that the connection can not be established + * because the parameters is unacceptable to local device.
+ */ + uint16_t response; + + /** + * @brief MTU(byte) of packet that L2CAP CBFC Channel on local device can receive. + */ + uint16_t mtu; + + /** + * @brief MPS(byte) of packet that L2CAP CBFC Channel on local device can receive. + */ + uint16_t mps; + + /** + * @brief The number of LE-Frame that L2CAP CBFC Channel on local device can receive. + */ + uint16_t credit; +} st_ble_l2cap_conn_rsp_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_conn_evt_t + * @brief L2CAP CBFC Channel connection parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel. + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief MTU of local/remote device. + */ + uint16_t mtu; + + /** + * @brief MPS of local/remote device. + */ + uint16_t mps; + + /** + * @brief Credit of local/remote device. + */ + uint16_t credit; +} st_ble_l2cap_cf_conn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_data_evt_t + * @brief Sent/Received Data parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel that has sent or received the data . + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief Data length. + */ + uint16_t data_len; + + /** + * @brief Sent/Received data. + */ + uint8_t * p_data; +} st_ble_l2cap_cf_data_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_credit_evt_t + * @brief Credit parameters of local or remote device. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel. + */ + uint16_t cid; + + /** + * @brief PSM allocated by the cid field. + */ + uint16_t psm; + + /** + * @brief Current credit of local/remote device. + */ + uint16_t credit; +} st_ble_l2cap_cf_credit_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_disconn_evt_t + * @brief Disconnection parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief CID identifying the L2CAP CBFC Channel that has been disconnected. + */ + uint16_t cid; +} st_ble_l2cap_cf_disconn_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_rej_evt_t + * @brief Command Reject parameters. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The reason that the remote device has sent Command Reject. + */ + uint16_t reason; + + /** + * @brief Optional information about the reason that the remote device has sent Command Reject. + */ + uint16_t data_1; + + /** + * @brief Optional information about the reason that the remote device has sent Command Reject. + */ + uint16_t data_2; +} st_ble_l2cap_rej_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_l2cap_cf_evt_data_t + * @brief st_ble_l2cap_cf_evt_data_t is the type of the data notified in a L2CAP Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle identifying the remote device. + */ + uint16_t conn_hdl; + + /** + * @brief The size of L2CAP Event parameters. + */ + uint16_t param_len; + + /** + * @brief L2CAP Event parameters. This parameter differs in each L2CAP Event. + */ + void * p_param; +} st_ble_l2cap_cf_evt_data_t; + +/******************************************************************************************************************//** + * @typedef ble_l2cap_cf_app_cb_t + * @brief ble_l2cap_cf_app_cb_t is the L2CAP Event callback function type. + * @param[in] event_type The type of L2CAP Event. + * @param[in] event_result The result of L2CAP Event + * @param[in] p_event_data Data notified by L2CAP Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_l2cap_cf_app_cb_t)(uint16_t event_type, ble_status_t event_result, + st_ble_l2cap_cf_evt_data_t * p_event_data); + +/*@}*/ + +/* ================================================ L2CAP Event Code ================================================ */ + +/** @addtogroup L2CAP_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @enum e_r_ble_l2cap_cf_evt_t + * @brief L2CAP Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief After the connection request for L2CAP CBFC Channel has been sent with R_BLE_L2CAP_ReqCfConn(), + * when the L2CAP CBFC Channel connection response has been received, + * BLE_L2CAP_EVENT_CF_CONN_CNF event occurs. + * + * ## Event Code: 0x5001 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_RSP_TIMEOUT(0x0011)L2CAP Command timeout.
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.
BLE_ERR_L2CAP_NO_RESOURCE(0x4004)No resource for connection.
BLE_ERR_L2CAP_INSUF_AUTHEN(0x4005)Insufficient authentication.
BLE_ERR_L2CAP_INSUF_AUTHOR(0x4006)Insufficient authorization.
BLE_ERR_L2CAP_INSUF_ENC_KEY_SIZE(0x4007)Insufficient encryption key size.
BLE_ERR_L2CAP_REFUSE_INSUF_ENC(0x4008)Insufficient encryption.
BLE_ERR_L2CAP_REFUSE_INVALID_SCID(0x4009) Invalid Source CID.
BLE_ERR_L2CAP_REFUSE_SCID_ALREADY_ALLOC(0x400A)Source CID already allocated.
BLE_ERR_L2CAP_REFUSE_UNACCEPTABLE_PARAM(0x400B)Unacceptable parameters.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_conn_evt_t + */ + BLE_L2CAP_EVENT_CF_CONN_CNF = 0x5001, + + /** + * @brief When a connection request for L2CPA CBFC Channel has been received from a remote device, + * BLE_L2CAP_EVENT_CF_CONN_IND event occurs. + * + * ## Event Code: 0x5002 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_NOT_FOUND(0x000D)CF connection request has not been received or lcid not found.
BLE_ERR_L2CAP_PSM_NOT_SUPPORTED(0x4002)PSM specified by R_BLE_L2CAP_ReqCfConn() is not supported.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_conn_evt_t + */ + BLE_L2CAP_EVENT_CF_CONN_IND = 0x5002, + + /** + * @brief After local device has sent a disconnection request for L2CAP CBFC Channel by + * R_BLE_L2CAP_DisconnectCf(), when the local device has received the response, + * BLE_L2CAP_EVENT_CF_DISCONN_CNF event occurs. + * + * ## Event Code: 0x5003 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_disconn_evt_t + */ + BLE_L2CAP_EVENT_CF_DISCONN_CNF = 0x5003, + + /** + * @brief When local device has received a disconnection request for L2CAP CBFC Channel from the remote device, + * BLE_L2CAP_EVENT_CF_DISCONN_IND event occurs.\n + * Host stack automatically replies the to the disconnection request. + * + * ## Event Code: 0x5004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_disconn_evt_t + */ + BLE_L2CAP_EVENT_CF_DISCONN_IND = 0x5004, + + /** + * @brief When local device has received data on L2CAP CBFC Channel, BLE_L2CAP_EVENT_CF_RX_DATA_IND event occurs. + * + * ## Event Code: 0x5005 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_data_evt_t + */ + BLE_L2CAP_EVENT_CF_RX_DATA_IND = 0x5005, + + /** + * @brief When the credit of the L2CAP CBFC Channel has reached the Low Water Mark, + * BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event occurs. + * + * ## Event Code: 0x5006 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_credit_evt_t + */ + BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND = 0x5006, + + /** + * @brief When local device has received credit from a remote device, BLE_L2CAP_EVENT_CF_TX_CRD_IND event occurs. + * + * ## Event Code: 0x5007 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_credit_evt_t + */ + BLE_L2CAP_EVENT_CF_TX_CRD_IND = 0x5007, + + /** + * @brief When the data transmission has been completed from host stack to Controller, + * BLE_L2CAP_EVENT_CF_TX_DATA_CNF event occurs. + * + * ## Event Code: 0x5008 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_DISCONNECTED(0x000F) While transmitting data, L2CAP CBFC Channel has been disconnected.
+ *
+ * + * ## Event Data: + * st_ble_l2cap_cf_data_evt_t + */ + BLE_L2CAP_EVENT_CF_TX_DATA_CNF = 0x5008, + + /** + * @brief When local device has received Command Reject PDU, BLE_L2CAP_EVENT_CMD_REJ event occurs. + * + * ## Event Code: 0x5009 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_l2cap_rej_evt_t + */ + BLE_L2CAP_EVENT_CMD_REJ = 0x5009 +} e_r_ble_l2cap_cf_evt_t; + +/*@}*/ + +/* ======================================== Vendor Specific Type Definitions ======================================== */ + +/** @addtogroup VS_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @struct st_ble_vs_tx_test_param_t + * @brief This is the extended transmitter test parameters used in R_BLE_VS_StartTxTest(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Channel used in Tx test. + */ + uint8_t ch; + + /** + * @brief Length(in bytes) of the packet used in Tx Test. + */ + uint8_t test_data_len; + + /** + * @brief Packet Payload. + */ + uint8_t packet_payload; + + /** + * @brief Transmitter PHY used in test. + */ + uint8_t phy; + + /** + * @brief Tx Power Level used in DTM Tx Test. + */ + uint8_t tx_power; + + /** + * @brief Option. + */ + uint8_t option; + + /** + * @brief The number of packet to be sent. + */ + uint16_t num_of_packet; +} st_ble_vs_tx_test_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_rx_test_param_t + * @brief This is the extended receiver test parameters used in R_BLE_VS_StartRxTest(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Channel used in Rx test. + */ + uint8_t ch; + + /** + * @brief Receiver PHY used in the test. + */ + uint8_t phy; +} st_ble_vs_rx_test_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_rf_ctrl_param_t + * @brief This is the RF parameters used in R_BLE_VS_SetRfControl(). + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief RF power on/off. + */ + uint8_t power; + + /** + * @brief This field indicates whether the parameters change in RF power on. + */ + uint8_t option; + + /** + * @brief RF rapid clock frequency adjust value(OSC internal CL adjust). + */ + uint8_t clval; + + /** + * @brief RF slow clock configurations. + */ + uint8_t slow_clock; + + /** + * @brief Set tx power in power on. + */ + uint8_t tx_power; + + /** + * @brief Set RF option. + */ + uint8_t rf_option; +} st_ble_vs_set_rf_ctrl_param_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_test_end_evt_t + * @brief This structure notifies that the extended test has been terminated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The number of packet successfully received in the receiver test. + */ + uint16_t num_of_packet; + + /** + * @brief The number of CRC error packets in the receiver test. + */ + uint16_t num_of_crc_err_packet; + + /** + * @brief Average RSSI(dBm) in the receiver test. + */ + int8_t ave_rssi; + + /** + * @brief Maximum RSSI(dBm) in the receiver test. + */ + int8_t max_rssi; + + /** + * @brief Minimum RSSI(dBm) in the receiver test. + */ + int8_t min_rssi; +} st_ble_vs_test_end_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_tx_pwr_comp_evt_t + * @brief This structure notifies that tx power has been set. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle that identifying the link whose tx power has been set. + */ + uint16_t conn_hdl; + + /** + * @brief Tx power that has been set(dBm). + */ + int8_t curr_tx_pwr; +} st_ble_vs_set_tx_pwr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_tx_pwr_comp_evt_t + * @brief This structure notifies that tx power has been retrieved. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Connection handle that identifying the link whose tx power has been retrieved. + */ + uint16_t conn_hdl; + + /** + * @brief Current tx power(dBm). + */ + int8_t curr_tx_pwr; + + /** + * @brief Maximum tx power(dBm). + */ + int8_t max_tx_pwr; +} st_ble_vs_get_tx_pwr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_set_rf_ctrl_comp_evt_t + * @brief This structure notifies that RF has been configured. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The result of RF power control. + */ + uint8_t ctrl; +} st_ble_vs_set_rf_ctrl_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_bd_addr_comp_evt_t + * @brief This structure notifies that BD_ADDR has been retrieved. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The area that public/random address has been retrieved. + * | value | description | + * |:------------------------------------|:------------------- | + * | BLE_VS_ADDR_AREA_REG(0x00) | Register. | + * | BLE_VS_ADDR_AREA_DATA_FLASH(0x01) | Data Flash. | + */ + uint8_t area; + + /** + * @brief The address that has been retrieved. + */ + st_ble_dev_addr_t addr; +} st_ble_vs_get_bd_addr_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_rand_comp_evt_t + * @brief This structure notifies that random number has been generated. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief Length of random number. + */ + uint8_t rand_size; + + /** + * @brief Random number. + */ + uint8_t * p_rand; +} st_ble_vs_get_rand_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_tx_flow_chg_evt_t + * @brief This structure notifies that the state transition of TxFlow has been changed. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The state of the flow control. + * | value | description | + * |:---------------------------- |:-------------------------------------------------------------------------- | + * | BLE_VS_TX_FLOW_CTL_ON(0x00) | The number of buffer has reached the High Water Mark from flow off state. | + * | BLE_VS_TX_FLOW_CTL_OFF(0x01) | The number of buffer has reached the Low Water Mark from flow on state. | + */ + uint8_t state; + + /** + * @brief The number of the current transmission buffers. + */ + uint32_t buffer_num; +} st_ble_vs_tx_flow_chg_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_evt_data_t + * @brief st_ble_vs_evt_data_t is the type of the data notified in a Vendor Specific Event. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The size of Vendor Specific Event parameters. + */ + uint16_t param_len; + + /** + * @brief Vendor Specific Event parameters. This parameter differs in each Vendor Specific Event. + */ + void * p_param; +} st_ble_vs_evt_data_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_scan_ch_map_comp_evt_t + * @brief This structure notifies that current scan channel map. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The result of current scan channel map. + */ + uint8_t ch_map; +} st_ble_vs_get_scan_ch_map_comp_evt_t; + +/******************************************************************************************************************//** + * @struct st_ble_vs_get_fw_version_comp_evt_t + * @brief This structure notifies the current firmware version. + **********************************************************************************************************************/ +typedef struct +{ + /** + * @brief The result of get firmware version. + */ + uint8_t major; + uint8_t minor; + uint8_t special; +} st_ble_vs_get_fw_version_comp_evt_t; + +/******************************************************************************************************************//** + * @typedef ble_vs_app_cb_t + * @brief ble_vs_app_cb_t is the Vendor Specific Event callback function type. + * @param[in] event_type The type of Vendor Specific Event. + * @param[in] event_result The result of API call which generates the Vendor Specific Event. + * @param[in] p_event_data Data notified in the Vendor Specific Event. + * @return none + **********************************************************************************************************************/ +typedef void (* ble_vs_app_cb_t)(uint16_t event_type, ble_status_t event_result, st_ble_vs_evt_data_t * p_event_data); + +/*@}*/ + +/* =========================================== Vendor Specific Event Code =========================================== */ + +/** @addtogroup VS_API + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @enum e_r_ble_vs_evt_t + * @brief Vendor Specific Event Identifier + **********************************************************************************************************************/ +typedef enum +{ + /** + * @brief This event notifies that the tx power has been set by R_BLE_VS_SetTxPower(). + * + * ## Event Code: 0x8001 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The tx_power parameter specified by R_BLE_VS_SetTxPower() is out of range.
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_SetTxPower() is not found.
+ *
+ * + * ## Event Data: + * st_ble_vs_set_tx_pwr_comp_evt_t + */ + BLE_VS_EVENT_SET_TX_POWER = 0x8001, + + /** + * @brief This event notifies that the tx power has been retrieved by R_BLE_VS_GetTxPower(). + * + * ## Event Code: 0x8002 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_HDL(0x000E)The link identified with the conn_hdl specified by R_BLE_VS_GetTxPower() is not found.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_tx_pwr_comp_evt_t + */ + BLE_VS_EVENT_GET_TX_POWER = 0x8002, + + /** + * @brief This event notifies that the extended transmitter test has been started by R_BLE_VS_StartTxTest(). + * + * ## Event Code: 0x8003 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartTxTest() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_TX_TEST_START = 0x8003, + + /** + * @brief This event notifies that the number specified by R_BLE_VS_StartTxTest() of packets has been sent. + * + * ## Event Code: 0x8004 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_TX_TEST_TERM = 0x8004, + + /** + * @brief This event notifies that the extended receiver test has been started by R_BLE_VS_StartRxTest(). + * + * ## Event Code: 0x8005 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_StartRxTest() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_RX_TEST_START = 0x8005, + + /** + * @brief This event notifies that the extended test has been terminated by R_BLE_VS_EndTest(). + * + * ## Event Code: 0x8006 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_test_end_evt_t + */ + BLE_VS_EVENT_TEST_END = 0x8006, + + /** + * @brief This event notifies that the coding scheme has been configured by R_BLE_VS_SetCodingScheme(). + * + * ## Event Code: 0x8007 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The coding_scheme parameter specified by R_BLE_VS_SetCodingScheme() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_CODING_SCHEME_COMP = 0x8007, + + /** + * @brief This event notifies that the RF has been configured by R_BLE_VS_SetRfControl(). + * + * ## Event Code: 0x8008 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The parameter specified by R_BLE_VS_SetRfControl() is out of range.
BLE_ERR_INVALID_OPERATION(0x0009)During the power on or the power off, the same power state is specified + * by R_BLE_VS_SetRfControl().
+ *
+ * + * ## Event Data: + * st_ble_vs_set_rf_ctrl_comp_evt_t + */ + BLE_VS_EVENT_RF_CONTROL_COMP = 0x8008, + + /** + * @brief This event notifies that public/random address has been set by R_BLE_VS_SetBdAddr(). + * + * ## Event Code: 0x8009 + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified + * by R_BLE_VS_SetBdAddr() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_ADDR_COMP = 0x8009, + + /** + * @brief This event notifies that public/random address has been retrieved by R_BLE_VS_GetBdAddr(). + * + * ## Event Code: 0x800A + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The area parameter or the type field in the p_addr parameter specified + * by R_BLE_VS_GetBdAddr() is out of range.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_bd_addr_comp_evt_t + */ + BLE_VS_EVENT_GET_ADDR_COMP = 0x800A, + + /** + * @brief This event notifies the application layer that random number has been generated by R_BLE_VS_GetRand(). + * + * ## Event Code: 0x800B + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The rand_size parameter specified by R_BLE_VS_GetRand() is out of range.
+ *
+ * + * ## Event Data: + * st_ble_vs_get_rand_comp_evt_t + */ + BLE_VS_EVENT_GET_RAND = 0x800B, + + /** + * @brief This event notifies the application layer of the state transition of TxFlow. + * + * ## Event Code: 0x800C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_tx_flow_chg_evt_t + */ + BLE_VS_EVENT_TX_FLOW_STATE_CHG = 0x800C, + + /** + * @brief This event notifies a failure occurs in RF. After receiving the event, reset MCU or RF. + * + * ## Event Code: 0x800D + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * None + */ + BLE_VS_EVENT_FAIL_DETECT = 0x800D, + + /** + * @brief This event notifies that scan channel map has been set by R_BLE_VS_SetScanChMap(). + * + * ## Event Code: 0x800E + * + * ## result: + *
+ * + * + * + * + * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
BLE_ERR_INVALID_ARG(0x0003)The ch_map parameter specified by R_BLE_VS_SetScanChMap() is out of range.
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SET_SCAN_CH_MAP = 0x800E, + + /** + * @brief This event notifies that scan channel map has been retrieved by R_BLE_VS_GetScanChMap(). + * + * ## Event Code: 0x800F + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_get_scan_ch_map_comp_evt_t + */ + BLE_VS_EVENT_GET_SCAN_CH_MAP = 0x800F, + + /** + * @brief This event notifies that START_FW_UPDATE command has completed. + * + * ## Event Code: 0x072C + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_START_FW_UPDATE_COMP = 0x072C, + + /** + * @brief This event notifies that SEND_FW_DATA command has completed. + * + * ## Event Code: 0x072D + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_SEND_FW_DATA_COMP = 0x072D, + + /** + * @brief This event notifies that END_FW_UPDATE command has completed. + * + * ## Event Code: 0x072E + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_END_FW_UPDATE_COMP = 0x072E, + + /** + * @brief This event notifies that END_FW_UPDATE command has completed. + * + * ## Event Code: 0x0772 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * st_ble_vs_get_fw_version_comp_evt_t + */ + BLE_VS_EVENT_GET_FW_VERSION_COMP = 0x0772, + + /** + * @brief This event notifies that module is ready. + * + * ## Event Code: 0x0746 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_MODULE_READY_COMP = 0x0746, + + /** + * @brief This event notifies that OTA firmware update has been started. + * + * ## Event Code: 0x09B0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_OTA_START_NOTIFY = 0x09B0, + + /** + * @brief This event notifies that OTA firmware update has been completed successfully. + * + * ## Event Code: 0x09C0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_OTA_END_NOTIFY = 0x09C0, + + /** + * @brief This event notifies that OTA firmware update has failed. + * + * ## Event Code: 0x09D0 + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_OTA_ERROR_NOTIFY = 0x09D0, + + /** + * @brief Invalid VS Event. + * + * ## Event Code: 0x80FF + * + * ## result: + *
+ * + * + * + * + * + *
BLE_SUCCESS(0x0000)Success
+ *
+ * + * ## Event Data: + * none + */ + BLE_VS_EVENT_INVALID = 0x80FF +} e_r_ble_vs_evt_t; + +/*@}*/ + +/* ============================================= APP Callback Definition ============================================ */ + +typedef void (* ble_app_init_cb_t)(uint8_t param); + +/* ============================================ Event Callback Definition =========================================== */ + +/******************************************************************************************************************//** + * @ingroup BLE_API + * @typedef ble_event_cb_t + * @brief ble_event_cb_t is the callback function type for R_BLE_SetEvent(). + * @param[in] void + * @return none + **********************************************************************************************************************/ +typedef void (* ble_event_cb_t)(void); + +/* ============================================== MAIN API Declarations ============================================== */ + +/** @addtogroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Open(void) + * @brief Open the BLE protocol stack. + * @details This function should be called once before using the BLE protocol stack. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Open(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Close(void) + * @brief Close the BLE protocol stack. + * @details This function should be called once to close the BLE protocol stack. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Close(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_Execute(void) + * @brief Execute the BLE task. + * @details This handles all the task queued in the BLE protocol stack internal task queue and return. + * This function should be called repeatedly in the main loop. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_Execute(void); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_IsTaskFree(void) + * @brief Check the BLE task queue is free or not. + * @details This function returns the BLE task queue free status. + * When this function returns 0x0, call R_BLE_Execute() to execute the BLE task. + * @retval 0x0 BLE task queue is not free + * @retval 0x1 BLE task queue is free + **********************************************************************************************************************/ +uint32_t R_BLE_IsTaskFree(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_SetEvent(ble_event_cb_t cb) + * @brief Set event. + * @details This function add an event in the BLE protocol stack internal queue. The event is handled in R_BLE_Execute + * just like Bluetooth event. This function is intended to be called in hardware interrupt context. + * Even if calling this function with the same cb before the cb is invoked, only one event is registered. + * The maximum number of the events can be registered at a time is eight. + * @param cb The callback for the event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) The event already registered with the callback. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) No free slot for the event. + **********************************************************************************************************************/ +ble_status_t R_BLE_SetEvent(ble_event_cb_t cb); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_GetVersion(void) + * @brief Get the BLE FIT module version. + * @details This function returns the BLE FIT module version. \n + * The major version(BLE_VERSION_MAJOR) is contained in the two most significant bytes, + * and the minor version(BLE_VERSION_MINOR) occupies the remaining two bytes. + * @retval "BLE_VERSION_MAJOR | BLE_VERSION_MINOR" + **********************************************************************************************************************/ +uint32_t R_BLE_GetVersion(void); + +/******************************************************************************************************************//** + * @fn uint32_t R_BLE_GetLibType(void) + * @brief Get the type of BLE protocol stack library. + * @details This function returns the type of BLE protocol stack library. + * @retval BLE_LIB_EXTENDED(0x00) Extended + * @retval BLE_LIB_BALANCE(0x01) Balance + * @retval BLE_LIB_COMPACT(0x02) Compact + **********************************************************************************************************************/ +uint32_t R_BLE_GetLibType(void); + +/*@}*/ + +/* ============================================== GAP API Declarations ============================================== */ + +/** @defgroup GAP_API GAP + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GAP_API + * @fn ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb) + * @brief Initialize the Host Stack. + * @details Host stack is initialized with this function. Before using All the R_BLE APIs, + * it's necessary to call this function. A callback function is registered with this function. + * In order to receive the GAP event, it's necessary to register a callback function. + * The result of this API call is notified in BLE_GAP_EVENT_STACK_ON event. + * @param[in] gap_cb A callback function registered with this function. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) gap_cb is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - Host Stack was already initialized. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Init(ble_gap_app_cb_t gap_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_Terminate(void) + * @brief Terminate the Host Stack. + * @details Host stack is terminated with this function. + * In order to reset all the Bluetooth functions, it's necessary to call this function. + * The result of this API call is notified in BLE_GAP_EVENT_STACK_OFF event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) Host stack hasn't been initialized. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Terminate(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_UpdConn(uint16_t conn_hdl, + * uint8_t mode, + * uint16_t accept, + * st_ble_gap_conn_param_t * p_conn_updt_param + * ) + * @brief Update the connection parameters. + * @details This function updates the connection parameters or replies a request for + * updating connection parameters notified by BLE_GAP_EVENT_CONN_PARAM_UPD_REQ event. + * When the connection parameters has been updated, + * BLE_GAP_EVENT_CONN_PARAM_UPD_COMP event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link to be updated. + * @param[in] mode Connection parameter update request or response. + * | macro | description | + * |:-------------------------------------- |:---------------------------------------------------- | + * | BLE_GAP_CONN_UPD_MODE_REQ (0x01) | Request for updating the connection parameters. | + * | BLE_GAP_CONN_UPD_MODE_RSP (0x02) | Reply a connection parameter update request. | + * + * @param[in] accept When mode is BLE_GAP_CONN_UPD_MODE_RSP, + * accept or reject the connection parameters update request. + * If mode is BLE_GAP_CONN_UPD_MODE_REQ, accept is ignored. + * | macro | description | + * |:-------------------------------------- |:--------------------------------- | + * | BLE_GAP_CONN_UPD_ACCEPT (0x0000) | Accept the update request. | + * | BLE_GAP_CONN_UPD_REJECT (0x0001) | Reject the update request. | + * + * @param[in] p_conn_updt_param Connection parameters to be updated. + * When mode is BLE_GAP_CONN_UPD_MODE_RSP and + * accept is BLE_GAP_CONN_UPD_REJECT, p_conn_updt_param is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When accept is BLE_GAP_CONN_UPD_ACCEPT, + * p_conn_updt_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following is out of range. + * - mode + * - accept + * - conn_intv_min field in p_conn_updt_param + * - conn_intv_max field in p_conn_updt_param + * - conn_latency in p_conn_updt_param + * - sup_to in p_conn_updt_param + * - conn_hdl + * @retval BLE_ERR_INVALID_STATE(0x0008) Not connected with the remote device. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Sending a L2CAP command, an error occurred. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_UpdConn(uint16_t conn_hdl, + uint8_t mode, + uint16_t accept, + st_ble_gap_conn_param_t * p_conn_updt_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time) + * @brief Update the packet size and the packet transmit time. + * @details This function requests for changing the maximum transmission packet size + * and the maximum packet transmission time. + * When Controller has received the request from host stack, + * BLE_GAP_EVENT_SET_DATA_LEN_COMP event is notified to the application layer. + * When the transmission packet size or the transmission time has been changed, + * BLE_GAP_EVENT_DATA_LEN_CHG event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link whose the transmission packet size or + * the transmission time to be changed. + * @param[in] tx_octets Maximum transmission packet size. + * Valid range is 0x001B - 0x00FB. + * @param[in] tx_time Maximum transmission time(us). + * Valid range is 0x0148 - 0x4290. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDataLen(uint16_t conn_hdl, uint16_t tx_octets, uint16_t tx_time); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason) + * @brief Disconnect the link. + * @details This function disconnects a link. + * When the link has disconnected, BLE_GAP_EVENT_DISCONN_IND event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the link to be disconnected. + * @param[in] reason The reason for disconnection. + * Usually, set 0x13 which indicates that a user disconnects the link. + * If setting other than 0x13, refer the error code described + * in Core Specification Vol.2 Part D ,"2 Error Code Descriptions". + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_Disconnect(uint16_t conn_hdl, uint8_t reason); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param) + * @brief Set the phy for connection. + * @details This function sets the PHY preferences for the connection. + * The result of this API call is notified in BLE_GAP_EVENT_PHY_SET_COMP event. + * When the PHY has been updated, BLE_GAP_EVENT_PHY_UPD event is notified to the application layer. + * + * After PHY update, the PHY accept configuration of local device is the same as the values + * in BLE_GAP_EVENT_PHY_UPD event. \n + * For example, after calling R_BLE_GAP_SetPhy(), if tx_phy, + * rx_phy by BLE_GAP_EVENT_PHY_UPD event are updated to 2M PHY, + * the PHY accept configuration is 2M PHY only. \n + * Therefore after receiving BLE_GAP_EVENT_PHY_UPD event, if local device wants to accept the other PHY + * configuration, it needs to call R_BLE_GAP_SetPhy() with the desired PHY accept configuration. + * + * Because the maximum transmission packet size or the maximum transmission time might be updated by + * PHY update, if the same packet size or transmission time as the previous one is desired, + * change the maximum transmission packet size or the maximum transmission time by @ref R_BLE_GAP_SetDataLen(). + * + * @param[in] conn_hdl Connection handle identifying the link whose PHY to be updated. + * @param[in] p_phy_param PHY preferences. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_phy_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl or option field in p_phy_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPhy(uint16_t conn_hdl, st_ble_gap_set_phy_param_t * p_phy_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param) + * @brief Set the default phy which allows remote device to change. + * @details This function sets the PHY preferences which a remote device may change. + * The result of this API call is notified in BLE_GAP_EVENT_DEF_PHY_SET_COMP event. + * @param[in] p_def_phy_param The PHY preference which a remote device may change. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_def_phy_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) tx_phys or tx_phys field in p_def_phy_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetDefPhy(st_ble_gap_set_def_phy_param_t * p_def_phy_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr, + * uint8_t * p_privacy_mode, + * uint8_t device_num + * ) + * @brief Set the privacy mode. + * @details This function sets privacy mode for the remote device registered in Resolving List. + * By default, Network Privacy Mode is set.\n + * The result of this API call is notified in BLE_GAP_EVENT_PRIV_MODE_SET_COMP event. + * @param[in] p_addr An array of identity address of the remote device to set privacy mode. + * The number of elements is specified by device_num.\n\n + * @param[in] p_privacy_mode An array of privacy mode to set to remote device. + * The number of elements is specified by device_num.\n + * The following value is set as the privacy mode. + * | macro | description | + * |:-------------------------------------- |:--------------------------------- | + * | BLE_GAP_NET_PRIV_MODE (0x00) | Network Privacy Mode. | + * | BLE_GAP_DEV_PRIV_MODE (0x01) | Device Privacy Mode. | + * @param[in] device_num The number of devices to set privacy mode. + * Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr or p_privacy_mode is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range. + * - The address type in p_addr. + * - The privacy mode specified by p_privacy_mode. + * - device_num + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While configuring privacy mode, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPrivMode(st_ble_dev_addr_t * p_addr, uint8_t * p_privacy_mode, uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num) + * @brief Set White List. + * @details This function supports the following operations regarding White List. + * - Add the device to White List. + * - Delete the device from White List. + * - Clear White List. + * + * The total number of White List entries is defined as BLE_GAP_WHITE_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_WHITE_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for White List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of device address to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_WHITE_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV, + * p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating White List, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the White List. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfWhiteList(uint8_t op_code, st_ble_dev_addr_t * p_addr, uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetVerInfo(void) + * @brief Get the version number of the Controller and the host stack. + * @details This function retrieves the version information of local device. + * The result of this API call is notified in BLE_GAP_EVENT_LOC_VER_INFO event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetVerInfo(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl) + * @brief Get the phy settings. + * @details This function gets the PHY settings for the connection. + * The result of this API call is notified in BLE_GAP_EVENT_PHY_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose PHY settings to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadPhy(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfRslvList(uint8_t op_code, + * st_ble_dev_addr_t * p_addr, + * st_ble_gap_rslv_list_key_set_t * p_peer_irk, + * uint8_t device_num + * ) + * @brief Set Resolving List. + * @details This function supports the following operations regarding Resolving List. + * - Add the device to Resolving List. + * - Delete the device from Resolving List. + * - Clear Resolving List. + * + * In order to generate a resolvable private address, + * a local IRK needs to be registered by R_BLE_GAP_SetLocIdInfo(). + * If communicating with the identity address, register all-zero IRK as local IRK. + * In order to resolve resolvable private address of the remote device, + * the IRK distributed from the remote device needs to be added to Resolving List. + * The total number of Resolving List entries is defined as BLE_GAP_RESOLV_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_RSLV_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for Resolving List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of Identity Addresses to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] p_peer_irk The remote IRK and the type of local IRK added to Resolving List. + * If op_code is other than BLE_GAP_LIST_ADD_DEV, p_peer_irk is ignored. + * The number of elements is specified by device_num. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_RSLV_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - When added to or deleted from the list, p_addr is specified as NULL. + * - When added to the list, p_peer_irk is specified as NULL. + * + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - op_code is out of range. + * - When op_code is BLE_GAP_LIST_ADD_DEV or + * BLE_GAP_LIST_REM_DEV, device_num is out of range. + * - When op_code is BLE_GAP_LIST_ADD_DEV or + * BLE_GAP_LIST_REM_DEV, address type field in p_addr is out of range. + * + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating Resolving List, this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating the Resolving List. + * @retval BLE_ERR_INVALID_HDL(0x000E) The specified Identity Address was not found in Resolving List. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfRslvList(uint8_t op_code, + st_ble_dev_addr_t * p_addr, + st_ble_gap_rslv_list_key_set_t * p_peer_irk, + uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable) + * @brief Enable/Disable address resolution and generation of a resolvable private address. + * @details This function enables or disables RPA functionality. The RPA functionality includes the following. + * - Generation of local resolvable private address + * - Resolution of remote resolvable private address + * + * In order to do advertising, scanning or creating a link with local resolvable private address, + * the RPA functionality needs to be enabled. + * After enabling the RPA functionality and the identity address of remote device and + * the IRKs of local/remote device is registered, + * local device can generate own resolvable private address in the time interval set by R_BLE_GAP_SetRpaTo(), + * and can resolve a resolvable private address of a remote device. + * It is recommended that the RPA functionality is called immediately + * after the initialization by R_BLE_GAP_Init(). + * The result of this API call is notified in BLE_GAP_EVENT_RPA_EN_COMP event. + * @param[in] enable Enable or disable address resolution function. + * | macro | description | + * |:------------------------------- |:----------------------------------------- | + * | BLE_GAP_RPA_DISABLED(0x00) | Disable RPA generation/resolution. | + * | BLE_GAP_RPA_ENABLED(0x01) | Enable RPA generation/resolution. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) enable is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_EnableRpa(uint8_t enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout) + * @brief Set the update time of resolvable private address. + * @details This function sets the time interval to update the resolvable private address. + * The result of this API call is notified in BLE_GAP_EVENT_SET_RPA_TO_COMP event. + * @param[in] rpa_timeout Time interval to update resolvable private address in seconds. + * Valid range is 0x003C - 0xA1B8. + * Default is 900s. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRpaTo(uint16_t rpa_timeout); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr) + * @brief Get the resolvable private address of local device. + * @details This function retrieves the local resolvable private address. + * Before getting the address, enable the resolvable private address function by R_BLE_GAP_EnableRpa(). + * The result of this API call is notified in BLE_GAP_EVENT_RD_RPA_COMP event. + * @param[in] p_addr Identity address registered in Resolving List. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) Address type in p_addr is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows. + * - When retrieving the local resolvable private address, + * this function was called. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadRpa(st_ble_dev_addr_t * p_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl) + * @brief Get RSSI. + * @details This function retrieves RSSI. + * The result of this API call is notified in BLE_GAP_EVENT_RSSI_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose RSSI to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadRssi(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl) + * @brief Get the Channel Map. + * @details This function retrieves the channel map. + * The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_RD_COMP event. + * @param[in] conn_hdl Connection handle identifying the link whose channel map to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) conn_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReadChMap(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr) + * @brief Set a random address. + * @details This function sets static address or non-resolvable private address to Controller. + * Refer to Core Specification Vol 6, PartB, + * "1.3.2 Random Device Address" regarding the format of the random address. + * Resolvable private address cannot set by this API. + * The result of this API call is notified in BLE_GAP_EVENT_RAND_ADDR_SET_COMP event. + * @param[in] p_random_addr Static address or non-resolvable private address. \n + * The BD address setting format is little endian. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_random_addr is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRandAddr(uint8_t * p_random_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param) + * @brief Set advertising parameters. + * @details This function sets advertising parameters. + * It's possible to do advertising where the advertising parameters are different every each advertising set. + * The number of advertising set in the Controller is defined as BLE_MAX_NO_OF_ADV_SETS_SUPPORTED. + * Each advertising set is identified with advertising handle (0x00-0x03). + * Create an advertising set with this function before start advertising, + * setting periodic advertising parameters, start periodic advertising, + * setting advertising data/scan response data/periodic advertising data. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_PARAM_SET_COMP event. + * @param[in] p_adv_param Advertising parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_adv_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The below p_adv_param field value is out of range. + * - adv_handle + * - adv_intv_min/adv_intv_max + * - adv_ch_map + * - o_addr_type + * - p_addr_type + * - adv_phy + * - sec_adv_phy + * - scan_req_ntf_flag + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetAdvParam(st_ble_gap_adv_param_t * p_adv_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data) + * @brief Set advertising data/scan response data/periodic advertising data. + * @details This function sets advertising data/scan response data/periodic advertising data to the advertising set. + * It is necessary to create an advertising set by R_BLE_GAP_SetAdvParam(), before calling this function. + * Set advertising data/scan response data/periodic advertising data, after allocating the memory for the data. + * The following shall be applied regarding the adv_prop_type field and the data_type field in + * st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam(). + * + * The following shall be applied regarding the adv_prop_type field and the data_type field in + * st_ble_gap_adv_param_t parameter specified in R_BLE_GAP_SetAdvParam(). + * - When adv_prop_type is Legacy Advertising PDU type, + * - it's possible to set advertising data/scan response data up to 31 bytes. + * - advertising data/scan response data can be updated by this function in advertising. + * - When adv_prop_type is Extended Advertising PDU type, + * - it's possible to set at most 1650 bytes of data as advertising data/scan response data + * per 1 advertising set. + * - the total buffer size in Controller for advertising data/scan response data is 4250 bytes. + * Therefore please note that more than 4250 bytes of advertising data/scan response data + * can not be set to all the advertising sets. + * Please refer to Figure 1.1 and Figure 1.2 about examples of setting advertising data/scan response data. + * - it's possible to update advertising data/scan response data in advertising, + * if the data_length field in st_ble_gap_adv_data_t parameter is up to 251 bytes. + * @image html "adv_data_alloc_fail_en.svg" "Figure 1.1" width=700px + * @image html "adv_data_alloc_success_en.svg" "Figure 1.2" width=700px + * - When periodic advertising data is set, + * - At most 1650 bytes of data can be set to 1 advertising set. + * - The total buffer size in Controller for periodic advertising data is 4306 bytes. + * Therefore please note that more than 4306 bytes of periodic advertising data can not be + * set to all the advertising sets. + * - it's possible to update periodic advertising data in advertising, + * if the data_length field in st_ble_gap_adv_data_t parameter is up to 252 bytes. + * + * The result of this API call is notified in @ref BLE_GAP_EVENT_ADV_DATA_UPD_COMP event. + * + * @param[in] p_adv_srsp_data Advertising data/scan response data/periodic advertising data. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_adv_srsp_data is specified as NULL. + * - data_length field in p_adv_srsp_data parameter is not 0 and p_data field is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in p_adv_srsp_data parameter is out of range. + * - adv_hdl + * - data_type + * - data_length + * - zero_length_flag + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetAdvSresData(st_ble_gap_adv_data_t * p_adv_srsp_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts) + * @brief Start advertising. + * @details This function starts advertising. + * Create the advertising set specified with adv_hdl by R_BLE_GAP_SetAdvParam(), + * before calling this function. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_ON event. + * @param[in] adv_hdl + * The advertising handle pointing to the advertising set which starts advertising. + * The valid range is 0x00 - 0x03. + * @param[in] duration + * The duration for which the advertising set identified by adv_hdl is enabled. + * Time = duration * 10ms. + * When the duration expires, BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped. + * The valid range is 0x0000 - 0xFFFF. + * The duration parameter is ignored when the value is set to 0x0000. + * @param[in] max_extd_adv_evts + * The maximum number of advertising events that be sent during advertising. + * When all the advertising events(max_extd_adv_evts) have been sent, + * BLE_GAP_EVENT_ADV_OFF event notifies that advertising is stopped. + * The max_extd_adv_evts parameter is ignored when the value is set to 0x00. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartAdv(uint8_t adv_hdl, uint16_t duration, uint8_t max_extd_adv_evts); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl) + * @brief Stop advertising. + * @details This function stops advertising. The result of this API call is notified in BLE_GAP_EVENT_ADV_OFF event. + * @param[in] adv_hdl + * The advertising handle pointing to the advertising set which stops advertising. + * The valid range is 0x00 - 0x03. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param) + * @brief Set periodic advertising parameters. + * @details This function sets periodic advertising parameters. + * Create the advertising set which supports Non-Connectable, + * Non-Scannable advertising by R_BLE_GAP_SetAdvParam() before setting periodic advertising parameters. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_PARAM_SET_COMP event. + * @param[in] p_perd_adv_param Periodic advertising parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_perd_adv_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in the p_perd_adv_param parameter is out of range. + * - adv_hdl + * - perd_intv_min or perd_intv_max + * - prop_type is neither 0x0000 nor 0x0040(BLE_GAP_PERD_PROP_TX_POWER) + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPerdAdvParam(st_ble_gap_perd_adv_param_t * p_perd_adv_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl) + * @brief Start periodic advertising. + * @details This function starts periodic advertising. + * Set periodic advertising parameters to the advertising set, before starting periodic advertising. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_ADV_ON event. + * @param[in] adv_hdl Advertising handle identifying the advertising set which starts periodic advertising. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPerdAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl) + * @brief Stop periodic advertising. + * @details This function stops periodic advertising. + * If the return value of this API is BLE_SUCCESS, the result is notified in BLE_GAP_EVENT_PERD_ADV_OFF event. + * @param[in] adv_hdl Specify the handle of Advertising Set to stop Periodic Advertising. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopPerdAdv(uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size, + * uint16_t * p_remain_perd_adv_data_size + * ) + * @brief Get buffer size for advertising data/scan response data/periodic advertising data in the Controller. + * @details This function gets the total size of advertising data/scan response data/periodic advertising data + * which can be currently set to Controller(all of the advertising sets). + * The application layer gets the data sizes via the parameters. + * By this API function call, no events occur. + * @param[out] p_remain_adv_data_size + * The free buffer size of Controller to which advertising data/scan response data can be currently set. + * @param[out] p_remain_perd_adv_data_size + * The free buffer size of Controller to which periodic advertising data can be currently set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_remain_adv_data_size or p_remain_perd_adv_data_size is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetRemainAdvBufSize(uint16_t * p_remain_adv_data_size, uint16_t * p_remain_perd_adv_data_size); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl) + * @brief Delete advertising set. + * @details This function deletes an advertising set or deletes all the advertising sets. + * The result of this API call is notified in BLE_GAP_EVENT_ADV_SET_REMOVE_COMP event. + * @param[in] op_code The operation for delete or clear. + * | macro | description | + * |:-------------------------------- |:-------------------------------- | + * | BLE_GAP_RMV_ADV_SET_REM_OP(0x01) | Delete an advertising set. | + * | BLE_GAP_RMV_ADV_SET_CLR_OP(0x02) | Delete all the advertising sets. | + * @param[in] adv_hdl + * Advertising handle identifying the advertising set deleted. + * If op_code is BLE_GAP_RMV_ADV_SET_CLR_OP, adv_hdl is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - op_code is out of range. + * - When op_code is BLE_GAP_RMV_ADV_SET_REM_OP(0x01), adv_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_RemoveAdvSet(uint8_t op_code, uint8_t adv_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param) + * @brief Request for a link establishment. + * @details This function sends a connection request to a remote device to create a link. + * When Controller has received a request for establishment of a link from host stack, + * BLE_GAP_EVENT_CREATE_CONN_COMP event is notified to the application layer. + * When the link is established, BLE_GAP_EVENT_CONN_IND event is notified to the application layer. + * @param[in] p_param Connection parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_param is specified as NULL. + * - p_conn_param_1M field and p_conn_param_2M and + * p_conn_param_coded field in p_param are specified as NULL. + * - When creating a link with 1M PHY, p_conn_param + * in p_conn_param_1M field in p_param is specified as NULL. + * - When creating a link with 2M PHY, + * p_conn_param in p_conn_param_2M field in p_param is specified as NULL. + * - When creating a link with coded MPHY, + * p_conn_param in p_conn_param_coded field in p_param is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - init_filter_policy in p_param is out of range. + * - remote_bd_addr_type field or own_addr_type address field + * in p_param is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateConn(st_ble_gap_create_conn_param_t * p_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CancelCreateConn(void) + * @brief Cancel the request for a link establishment. + * @details This function cancels a request for establishing a link. + * When Controller has received the cancel request from host stack, + * BLE_GAP_EVENT_CONN_CANCEL_COMP event is notified to the application layer. + * When the cancel procedure has completed, + * BLE_GAP_EVENT_CONN_IND event is notified to the application layer. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CancelCreateConn(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map) + * @brief Set the Channel Map. + * @details This function sets the channel map. + * The result of this API call is notified in BLE_GAP_EVENT_CH_MAP_SET_COMP event. + * @param[in] p_channel_map Channel map. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_channel_map is specified as NULL. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetChMap(uint8_t * p_channel_map); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param, + * st_ble_gap_scan_on_t * p_scan_enable + * ) + * @brief Set scan parameter and start scan. + * @details This function starts scanning. + * When scanning for the first time, set the p_scan_param. + * Setting scan parameters can be omitted by specifying p_scan_param as NULL after next time. + * The result of this API call is notified in BLE_GAP_EVENT_SCAN_ON event. + * Advertising report is notified in BLE_GAP_EVENT_ADV_REPT_IND event. + * Figure 1.3 shows the relationship between scan period, scan duration, scan interval and scan window. + * @image html "scan_period_en.svg" "Figure 1.3" + * + * When scan duration is non-zero, scan period is zero and scan duration expires, + * BLE_GAP_EVENT_SCAN_TO event is notified to the application layer. + * @param[in] p_scan_param + * Scan parameter. + * When p_scan_param is specified as NULL, + * host stack doesn't set scan parameters and start scanning with the previous parameters. + * @param[in] p_scan_enable + * Scan period, scan duration, duplicate filter and procedure type. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - p_scan_enable is specified as NULL. + * - p_phy_param_1M field and p_phy_param_coded field in + * p_scan_param are specified as NULL. + * + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - proc_type field in p_scan_enable is out of range. + * - filter_dups in p_scan_enable is out of range. + * - o_addr_type in p_scan_param is out of range. + * - filter_policy in p_scan_param is out of range. + * - scan_type of p_scan_param's p_phy_param_1M or p_phy_param_coded is out of range. + * + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartScan(st_ble_gap_scan_param_t * p_scan_param, st_ble_gap_scan_on_t * p_scan_enable); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StopScan(void) + * @brief Stop scan. + * @details This function stops scanning. + * The result of this API call is notified in BLE_GAP_EVENT_SCAN_OFF event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StopScan(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr, + * uint8_t adv_sid, + * uint16_t skip, + * uint16_t sync_to + * ) + * @brief Request for a periodic sync establishment. + * @details This function sends a request for establishment of a periodic sync to a advertiser. + * In order to create a periodic sync, scan needs to be starting by R_BLE_GAP_StartScan(). + * When Controller has received the request from host stack, + * BLE_GAP_EVENT_CREATE_SYNC_COMP event is notified to the application layer. + * When the periodic sync is established, BLE_GAP_EVENT_SYNC_EST event is notified to the application layer. + * @param[in] p_addr + * The address of periodic advertiser.When p_addr is specified as NULL, + * local device creates a periodic sync with the advertiser registered in Periodic Advertiser List. + * @param[in] adv_sid + * Advertising SID. When p_addr is specified as NULL, adv_sid is ignored. + * Valid range is 0x00 - 0x0F. + * @param[in] skip + * The number of consecutive periodic advertising packets + * that local device may skip after receiving a periodic advertising packet. + * Valid range is 0x0000 - 0x01F3. + * @param[in] sync_to + * The maximum permitted time between successful receives.When sync_to expires, + * the periodic sync is lost. + * Time(ms) = sync_to * 10. + * Valid range is 0x000A - 0x4000. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_addr is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The following parameter is out of range. + * - address type in p_addr + * - adv_sid + * - skip + * - sync_to + * + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateSync(st_ble_dev_addr_t * p_addr, uint8_t adv_sid, uint16_t skip, uint16_t sync_to); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CancelCreateSync(void) + * @brief Cancel the request for a periodic sync establishment. + * @details This function cancels a request for establishing a periodic sync. + * The result of this API call is notified in BLE_GAP_EVENT_SYNC_CREATE_CANCEL_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CancelCreateSync(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl) + * @brief Terminate the periodic sync. + * @details This function terminates a periodic sync. + * The result of this API call is notified in BLE_GAP_EVENT_SYNC_TERM event. + * @param[in] sync_hdl Sync handle identifying the periodic sync to be terminated. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) sync_hdl is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_TerminateSync(uint16_t sync_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t op_code, + * st_ble_dev_addr_t * p_addr, + * uint8_t * p_adv_sid_set, + * uint8_t device_num + * ) + * @brief Set Periodic Advertiser List. + * @details This function supports the following operations regarding Periodic Advertiser List. + * - Add the device to Periodic Advertiser List. + * - Delete the device from Periodic Advertiser List. + * - Clear Periodic Advertiser List. + * + * The total number of Periodic Advertiser List entries is defined as BLE_GAP_PERD_LIST_MAX_ENTRY. + * The result of this API call is notified in BLE_GAP_EVENT_PERD_LIST_CONF_COMP event. + * @param[in] op_code + * The operation for Periodic Advertiser List. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_LIST_ADD_DEV(0x01) | Add the device to the list. | + * | BLE_GAP_LIST_REM_DEV(0x02) | Delete the device from the list. | + * | BLE_GAP_LIST_CLR(0x03) | Clear the list. | + * @param[in] p_addr An array of device address to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_addr is ignored. + * @param[in] p_adv_sid_set An array of SID of the advertiser to add / delete to the list. + * The number of elements is specified by device_num. + * If op_code is BLE_GAP_LIST_CLR, p_adv_sid_set is ignored. + * @param[in] device_num The number of devices add / delete to the list. + * Valid range is 1-BLE_GAP_PERD_LIST_MAX_ENTRY. + * If op_code is BLE_GAP_LIST_CLR, device_num is ignored. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) When op_code is BLE_GAP_LIST_ADD_DEV or BLE_GAP_LIST_REM_DEV, + * p_addr or p_adv_sid_set is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) op_code or address type field in p_addr or p_adv_sid_set or + * device_num is out of range. + * @retval BLE_ERR_UNSUPPORTED(0x0007) Not supported. + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - While operating Periodic Advertiser List, this function was called. + * - The task for host stack is not running. + * + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for operating periodic advertiser. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ConfPerdAdvList(uint8_t op_code, + st_ble_dev_addr_t * p_addr, + uint8_t * p_adv_sid_set, + uint8_t device_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag) + * @brief Authorize a remote device. + * @details User authorizes a remote device by this function. + * This function is used when a remote device accesses a GATT Characteristic + * in local device which requests user authorization. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device to be authorized or not by user. + * @param[in] author_flag Authorize or not the remote device. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_NOT_AUTHORIZED(0x00) | Not authorize the remote device. | + * | BLE_GAP_AUTHORIZED(0x01) | Authorize the remote device. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) author_flag is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_AuthorizeDev(uint16_t conn_hdl, uint8_t author_flag); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl) + * @brief Get the information about remote device. + * @details This function retrieves information about the remote device. + * The information includes BD_ADDR, the version number and LE features. + * The result of this API call is notified in BLE_GAP_EVENT_GET_REM_DEV_INFO event. + * @param[in] conn_hdl Connection handle identifying the remote device whose information to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetRemDevInfo(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param) + * @brief Set the parameters using pairing. + * @details This function sets the parameters used in pairing. + * The parameters set by this API are sent to the remote device when pairing occurred. + * The result of this API call is returned by a return value. + * @param[in] p_pair_param Pairing parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The following field in p_pair_param is out of range. + * - iocap + * - max_key_size + * - mitm + * - bonding + * - key_notf + * - sec_conn_only + * + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetPairingParams(st_ble_gap_pairing_param_t * p_pair_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk) + * @brief Set the IRK and the identity address distributed to a remote device. + * @details This function registers local IRK and identity address of local device in host stack. + * The IRK and the identity address are distributed to a remote device in pairing. + * The result of this API call is returned by a return value. + * @param[in] p_lc_id_addr Identity address to be registered in host stack. + * @param[in] p_lc_irk IRK to be registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_lc_id_addr or p_lc_irk is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) Address type field in p_lc_id_addr is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetLocIdInfo(st_ble_dev_addr_t * p_lc_id_addr, uint8_t * p_lc_irk); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk) + * @brief Set the CSRK distributed to a remote device. + * @details This function registers local CSRK in host stack. + * The CSRK is distributed to a remote device in pairing. + * The result of this API call is returned by a return value. + * @param[in] p_local_csrk CSRK to be registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_local_csrk is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetLocCsrk(uint8_t * p_local_csrk); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl) + * @brief Start pairing. + * @details This function starts pairing with a remote device. + * The result of this API call is returned by a return value. + * The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event. + * @param[in] conn_hdl Connection handle identifying the remote device which local device starts pairing with. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) While pairing, this function was called. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartPairing(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response) + * @brief Reply the pairing request from a remote device. + * @details This function replies to the pairing request from the remote device. + * The pairing request from the remote device is notified in BLE_GAP_EVENT_PAIRING_REQ event. + * The result of this API call is returned by a return value. + * The result of pairing is notified in BLE_GAP_EVENT_PAIRING_COMP event. + * @param[in] conn_hdl Connection handle identifying the remote device which local device starts pairing with. + * @param[in] response Accept or reject the pairing request from the remote device. + * | macro | description | + * |:----------------------------- |:-------------------------------- | + * | BLE_GAP_PAIRING_ACCEPT(0x00) | Accept the pairing request. | + * | BLE_GAP_PAIRING_REJECT(0x01) | Reject the pairing request. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) While generating OOB data, this function was called. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, + * host stack has not yet received BLE_GAP_EVENT_PAIRING_REQ event. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyPairing(uint16_t conn_hdl, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl) + * @brief Encryption the link. + * @details This function starts encryption of the link. + * In case of master device, the local device requests for the encryption to a remote device. + * In case of slave device, the local device sends a Security Request to a remote device. + * After receiving the Security Request, the remote device requests for the encryption to the local device. + * The result of the encryption is returned in BLE_GAP_EVENT_ENC_CHG event. + * @param[in] conn_hdl Connection handle identifying the link which is encrypted. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - Pairing has not been completed. + * - The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_StartEnc(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response) + * @brief Reply the passkey entry request. + * @details When BLE_GAP_EVENT_PASSKEY_ENTRY_REQ event is notified, + * the response to passkey entry is sent by this function. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device which the reply to passkey entry is sent. + * @param[in] passkey Passkey. + * The valid range is 000000 - 999999 in decimal. + * @param[in] response Active or negative reply to passkey entry. + * | macro | description | + * |:----------------------------- |:---------------------------------- | + * | BLE_GAP_PAIRING_ACCEPT(0x00) | Accept the passkey entry pairing. | + * | BLE_GAP_PAIRING_REJECT(0x01) | Reject the passkey entry pairing. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) passkey or response is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyPasskeyEntry(uint16_t conn_hdl, uint32_t passkey, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response) + * @brief Reply the numeric comparison request. + * @details When BLE_GAP_EVENT_NUM_COMP_REQ event is notified, + * the response to Numeric Comparison is sent by this function. + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device which the reply to Numeric Comparison is sent. + * @param[in] response Active or negative reply in Numeric Comparison. + * | macro | description | + * |:-------------------------- |:----------------------------------------------------------------------- | + * |BLE_GAP_PAIRING_ACCEPT(0x00)| The number displayed in the local is the same as the one of the remote. | + * |BLE_GAP_PAIRING_REJECT(0x01)| The number displayed in the local is differs from the one of the remote.| + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) When this function was called, + * host stack has not yet received @ref BLE_GAP_EVENT_NUM_COMP_REQ event. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyNumComp(uint16_t conn_hdl, uint8_t response); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press) + * @brief Notify the input key type which a remote device inputs in the passkey entry. + * @details This function notifies the input key type to the remote device in passkey entry. + * The result is returned from this API. + * @param[in] conn_hdl Connection handle identifying the remote device to which the key notification is sent. + * @param[in] key_press Input key type. + * | macro | description | + * |:------------------------------------------ |:------------------------------------- | + * | BLE_GAP_LESC_PASSKEY_ENTRY_STARTED(0x00) | Notify that passkey entry started. | + * | BLE_GAP_LESC_PASSKEY_DIGIT_ENTERED(0x01) | Notify that passkey digit entered. | + * | BLE_GAP_LESC_PASSKEY_DIGIT_ERASED(0x02) | Notify that passkey digit erased. | + * | BLE_GAP_LESC_PASSKEY_CLEARED(0x03) | Notify that passkey cleared. | + * | BLE_GAP_LESC_PASSKEY_ENTRY_COMPLETED(0x04) | Notify that passkey entry completed. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) key_press parameter is out of range. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_NotifyKeyPress(uint16_t conn_hdl, uint8_t key_press); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info) + * @brief Get the security information about the remote device. + * @details This function gets the parameters which has been negotiated with the remote device in pairing. + * The parameters can be retrieved after pairing. + * The result is returned by p_sec_info. + * @param[in] conn_hdl Connection handle identifying the remote device whose bonding information is retrieved. + * @param[in] p_sec_info Return the security information which has been negotiated in pairing. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_sec_info is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The remote device bonding information has not been set to host stack. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_GetDevSecInfo(uint16_t conn_hdl, st_ble_gap_auth_info_t * p_sec_info); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl) + * @brief Distribute the keys of local device. + * @details When key exchange request is notified by BLE_GAP_EVENT_EX_KEY_REQ event at pairing, + * keys of the local device are distributed. + * The result is returned from this API. + * @param[in] conn_hdl Connection handle identifying the remote device to which the key is distributed. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) When this function was called, pairing has not yet started. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyExKeyInfoReq(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetRemOobData( st_ble_dev_addr_t * p_addr, + * uint8_t oob_data_flag, + * st_ble_gap_oob_data_t * p_oob + * ) + * @brief Set the oob data from a remote device. + * @details This function registers the OOB data received from a remote device. + * When oob_data_flag indicates that the OOB data has been received, + * the setting regarding OOB data is reflected in pairing. + * In order to do OOB pairing, set the OOB data received from the remote device before pairing. + * The result is returned from this API. + * @param[in] p_addr The remote device address. + * @param[in] oob_data_flag This parameter indicates whether the local device has received the OOB data + * from the remote device or not. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_OOB_DATA_NOT_PRESENT(0x00)| Reply that No OOB data has been received when pairing. | + * | BLE_GAP_OOB_DATA_PRESENT(0x01) | Reply that the OOB data has been received when pairing. | + * @param[in] p_oob The OOB data received from the remote device. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows. + * - p_addr is specified as NULL. + * - oob_data_flag is BLE_GAP_OOB_DATA_PRESENT and p_oob is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) oob_data_flag is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) There is no room to register the OOB data received from a remote device. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetRemOobData(st_ble_dev_addr_t * p_addr, uint8_t oob_data_flag, st_ble_gap_oob_data_t * p_oob); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_CreateScOobData(void) + * @brief Create data for oob in secure connection. + * @details This function generates the OOB data distributed to a remote device in Secure Connections. + * The result of this API call is notified in BLE_GAP_EVENT_SC_OOB_CREATE_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The reason for this error is as follows: + * - This function was called in pairing. + * - The task for host stack is not running. + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) This function was called in creating OOB data. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_CreateScOobData(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info, + * uint8_t device_num, + * uint8_t * p_set_num + * ) + * @brief Set the bonding information stored in non-volatile memory to the host stack. + * @details Set the bonding information of the remote device in the host stack. + * After power re-supply, when the remote device bonding information stored in non-volatile memory is + * set to host stack, this function is used. + * Host stack can be set the number specified by the device_num parameter of bonding information. + * @param[in] p_bond_info An array of bonding information. The number of elements is specified by device_num. + * @param[in] device_num The number of the devices of which host stack registers bonding information. + * @param[in] p_set_num The number of the devices whose bonding information was registered in host stack. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_bond_info or p_set_num is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) device_num is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack already has the maximum number of bonding information. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_SetBondInfo(st_ble_gap_bond_info_t * p_bond_info, uint8_t device_num, uint8_t * p_set_num); + +/******************************************************************************************************************//** + * @fn void R_BLE_GAP_DeleteBondInfo(int32_t local, + * int32_t remote, + * st_ble_dev_addr_t * p_addr, + * ble_gap_del_bond_cb_t gap_del_bond_cb) + * @brief This function deletes the bonding information in Host Stack.\n + * When a function for deleting the bonding information stored in non-volatile area is registered by the + * gap_del_bond_cb parameter, it is deleted as well as the bonding information in Host Stack. + * + * @param[in] local The type of the local bonding information to be deleted. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_SEC_DEL_LOC_NONE(0x00) | Delete no local keys. | + * | BLE_GAP_SEC_DEL_LOC_IRK(0x01) | Delete local IRK and identity address. | + * | BLE_GAP_SEC_DEL_LOC_CSRK(0x02) | Delete local CSRK. | + * | BLE_GAP_SEC_DEL_LOC_ALL(0x03) | Delete all local keys. | + * @param[in] remote The type of the remote bonding information to be deleted. + * | macro | description | + * |:--------------------------------- |:------------------------------------------------------- | + * | BLE_GAP_SEC_DEL_REM_NONE(0x00) | Delete no remote device keys. | + * | BLE_GAP_SEC_DEL_REM_SA(0x01) | Delete the keys specified by the p_addr parameter. | + * | BLE_GAP_SEC_DEL_REM_NOT_CONN(0x02)| Delete keys of not connected remote devices. | + * | BLE_GAP_SEC_DEL_REM_ALL(0x03) | Delete all remote device keys. | + * \n\n + * @param[in] p_addr p_addr is specified as the address of the remote device whose keys are deleted + * when the rem_info parameter is set to @ref BLE_GAP_SEC_DEL_REM_SA(0x01). + * \n\n + * @param[in] gap_del_bond_cb This parameter is a callback function which deletes the bonding information stored + * in non-volatile area. \n After deleting the bonding information stored in Host Stack, + * the callback function is called. If no bonding information is stored in + * non-volatile area, specify the parameter as NULL. + * @retval none + **********************************************************************************************************************/ +void R_BLE_GAP_DeleteBondInfo(int32_t local, + int32_t remote, + st_ble_dev_addr_t * p_addr, + ble_gap_del_bond_cb_t gap_del_bond_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, + * uint16_t ediv, + * uint8_t * p_peer_rand, + * uint8_t response + * ) + * @brief Reply the LTK request from a remote device. + * @details This function replies to the LTK request in BLE_GAP_EVENT_LTK_REQ event from a remote device. + * The result of the LTK reply is returned in BLE_GAP_EVENT_LTK_RSP_COMP event. + * When the link encryption has completed, BLE_GAP_EVENT_ENC_CHG event is notified. + * @param[in] conn_hdl Connection handle identifying the remote device which sent the LTK request. + * @param[in] ediv Ediv notified in BLE_GAP_EVENT_LTK_REQ event. + * @param[in] p_peer_rand Rand notified in BLE_GAP_EVENT_LTK_REQ event. + * @param[in] response Response to the LTK request. + * If "BLE_GAP_LTK_REQ_ACCEPT" is specified, + * when no LTK has been exchanged in pairing, reject the LTK request. + * | macro | description | + * |:----------------------------- |:---------------------------------- | + * | BLE_GAP_LTK_REQ_ACCEPT(0x00) | Reply for the LTK request. | + * | BLE_GAP_LTK_REQ_DENY(0x01) | Reject the LTK request. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) p_peer_rand is specified as NULL in case of legacy pairing. + * @retval BLE_ERR_INVALID_ARG(0x0003) response is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GAP_ReplyLtkReq(uint16_t conn_hdl, uint16_t ediv, uint8_t * p_peer_rand, uint8_t response); + +/*@}*/ + +/* ========================================== GATT Common API Declarations ========================================== */ + +/** @defgroup GATT_COMMON_API GATT_COMMON + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_COMMON_API + * @fn ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu) + * @brief This function gets the current MTU used in GATT communication. + * @details Both GATT server and GATT Client can use this function. \n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the GATT Server or the GATT Client. + * @param[in] p_mtu The Current MTU. Before MTU exchange, this parameter is 23 bytes. \n + * After MTU exchange, this parameter is the negotiated MTU. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The mtu parameter is NULL. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server or the GATT Client specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATT_GetMtu(uint16_t conn_hdl, uint16_t * p_mtu); + +/*@}*/ + +/* ========================================== GATT Server API Declarations ========================================== */ + +/** @defgroup GATT_SERVER_API GATT_SERVER + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_SERVER_API + * @fn ble_status_t R_BLE_GATTS_Init(uint8_t cb_num) + * @brief This function initializes the GATT Server and registers the number of the callbacks for GATT Server event. + * @details Specify the cb_num parameter to a value between 1 and BLE_GATTS_MAX_CB.\n + * R_BLE_GATTS_RegisterCb() registers the callback.\n + * The result of this API call is returned by a return value. + * @param[in] cb_num The number of callbacks to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Init(uint8_t cb_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst) + * @brief This function sets GATT Database to host stack. + * @details The result of this API call is returned by a return value. + * @param[in] p_db_inst GATT Database to be set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows. + * - The db_inst parameter is specified as NULL. + * - The array in the db_inst is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetDbInst(st_ble_gatts_db_cfg_t * p_db_inst); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority) + * @brief This function registers a callback for GATT Server event. + * @details The number of the callback that may be registered by this function is the value specified + * by R_BLE_GATTS_Init().\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for GATT Server event. + * @param[in] priority The priority of the callback function.\n + * Valid range is 1 <= priority <= BLE_GATTS_MAX_CB.\n + * A lower priority number means a higher priority level. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_RegisterCb(ble_gatts_app_cb_t cb, uint8_t priority); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb) + * @brief This function deregisters the callback function for GATT Server event. + * @details The result of this API call is returned by a return value. + * @param[in] cb The callback function to be deregistered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_DeregisterCb(ble_gatts_app_cb_t cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data) + * @brief This function sends a notification of an attribute's value. + * @details The maximum length of the attribute value that can be sent with notification is MTU-3.\n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the notification. + * @param[in] p_ntf_data The attribute value to send. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_ntf_data parameter or the value field in the value field in + * the p_ntf_data parameter is NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ntf_data parameter is 0 + * or the attr_hdl field in the p_ntf_data parameters is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Notification(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ntf_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data) + * @brief This function sends a indication of an attribute's value. + * @details The maximum length of the attribute value that can be sent with indication is MTU-3.\n + * The result of this API call is returned by a return value.\n + * The remote device that receives a indication sends a confirmation.\n + * BLE_GATTS_EVENT_HDL_VAL_CNF event notifies the application layer that the confirmation has been received. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the indication. + * @param[in] p_ind_data The attribute value to send. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_ind_data parameter or the value field in the value field in + * the p_ind_data parameter is NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The value_len field in the value field in the p_ind_data parameter is 0 + * or the attr_hdl field in the p_ind_data parameters is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_Indication(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_ind_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value) + * @brief This function gets a attribute value from the GATT Database. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved, + * specify the remote device with the conn_hdl parameter. + * When information about the remote device is not required, + * set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL. + * @param[in] attr_hdl The attribute handle of the attribute value to be retrieved. + * @param[out] p_value The attribute value to be retrieved. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_value parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle + * of GATT Database. + * @retval BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be read. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be read. + * @retval BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to + * any services or characteristics. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_GetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value) + * @brief This function sets an attribute value to the GATT Database. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl If the attribute value that has information about the remote device is retrieved, + * specify the remote device with the conn_hdl parameter. + * When information about the remote device is not required, + * set the conn_hdl parameter to BLE_GAP_INVALID_CONN_HDL. + * @param[in] attr_hdl The attribute handle of the attribute value to be set. + * @param[in] p_value The attribute value to be set. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_value parameter is specified as NULL. + * @retval BLE_ERR_INVALID_DATA(0x0002) The write size is larger than the length of the attribute value. + * @retval BLE_ERR_INVALID_ARG(0x0003) The attr_hdl parameter is 0 or larger than the last attribute handle + * of GATT Database. + * @retval BLE_ERR_INVALID_STATE(0x0008) The attribute is not in a state to be written. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The attribute cannot be written. + * @retval BLE_ERR_NOT_FOUND(0x000D) The attribute specified by the attr_hdl parameter is not belonging to + * any services or characteristics. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetAttr(uint16_t conn_hdl, uint16_t attr_hdl, st_ble_gatt_value_t * p_value); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code) + * @brief This function sends an error response to a remote device. + * @details The result is returned from the API.\n + * The error code specified in the callback is notified as Error Response to the remote device.\n + * The result of this API call is returned by a return value. + * @param[in] error_code The error codes to be notified the client.\n + * It is a bitwise OR of GATT Error Group ID : 0x3000 and the following error codes defined + * in Core Spec and Core Spec Supplement. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
Error Codedescription
BLE_ERR_GATT_INVALID_HANDLE(0x3001)Invalid attribute handle
BLE_ERR_GATT_READ_NOT_PERMITTED(0x3002)The attribute cannot be read.
BLE_ERR_GATT_WRITE_NOT_PERMITTED(0x3003)The attribute cannot be written.
BLE_ERR_GATT_INVALID_PDU(0x3004)Invalid PDU.
BLE_ERR_GATT_INSUFFICIENT_AUTHENTICATION(0x3005)The authentication to access the attribute is insufficient.
BLE_ERR_GATT_REQUEST_NOT_SUPPORTED(0x3006)The request is not supported.
BLE_ERR_GATT_INVALID_OFFSET(0x3007)The specified offset is larger than the length of the attribute value.
BLE_ERR_GATT_INSUFFICIENT_AUTHORIZATION(0x3008)Authorization is required to access the attribute.
BLE_ERR_GATT_PREPARE_WRITE_QUEUE_FULL(0x3009)The Write Queue in the GATT Server is full.
BLE_ERR_GATT_ATTRIBUTE_NOT_FOUND(0x300A)The specified attribute is not found.
BLE_ERR_GATT_ATTRIBUTE_NOT_LONG(0x300B)The attribute cannot be read by Read Blob Request.
BLE_ERR_GATT_INSUFFICIENT_ENC_KEY_SIZE(0x300C)The Encryption Key Size is insufficient.
BLE_ERR_GATT_INVALID_ATTRIBUTE_LEN(0x300D)The length of the specified attribute is invalid.
BLE_ERR_GATT_UNLIKELY_ERROR(0x300E)Because an error has occurred, the process cannot be advanced.
BLE_ERR_GATT_INSUFFICIENT_ENCRYPTION(0x300F)Encryption is required to access the attribute. + *
BLE_ERR_GATT_UNSUPPORTED_GROUP_TYPE(0x3010)The type of the specified attribute is not supported. + *
BLE_ERR_GATT_INSUFFICIENT_RESOURCES(0x3011)The resource to complete the request is insufficient. + *
0x3080 - 0x309FApplication Error. + * The upper layer defines the error codes.
0x30E0 - 0x30FF + * The error code defined in Common Profile and Service Error + * Core Specification Supplement(CSS).
+ * CSS ver.7 defines the error codes from 0x30FC to 0x30FF. + *
BLE_ERR_GATT_WRITE_REQ_REJECTED(0x30FC)The Write Request has not been completed due to the reason other than Permission. + *
BLE_ERR_GATT_CCCD_IMPROPERLY_CFG(0x30FD)The CCCD is set to be invalid.
BLE_ERR_GATT_PROC_ALREADY_IN_PROGRESS(0x30FE)The request is now in progress.
BLE_ERR_GATT_OUT_OF_RANGE(0x30FF)The attribute value is out of range.
+ * + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The Group ID of the error_code parameter is not 0x3000, or it is 0x3000. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other error response,this function was called. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SendErrRsp(uint16_t error_code); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu) + * @brief This function replies to a MTU Exchange Request from a remote device. + * @details BLE_GATTS_EVENT_EX_MTU_REQ event notifies the application layer + * that a MTU Exchange Request has been received. + * Therefore when the callback has received the event, call this function.\n + * The new MTU is the minimum of the mtu parameter specified by this function + * and the mtu field in BLE_GATTS_EVENT_EX_MTU_REQ event.\n + * Default MTU size is 23 bytes.\n + * The result of this API call is returned by a return value.\n + * @param[in] conn_hdl Connection handle identifying the remote device to be sent MTU Exchange Response. + * @param[in] mtu The maximum size(in bytes) of the GATT PDU that GATT Server can receive.\n + * Valid range is 23 <= mtu <= 247. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_RspExMtu(uint16_t conn_hdl, uint16_t mtu); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num) + * @brief Register prepare queue and buffer in Host Stack. + * @details This function registers the prepare queue and buffer for long chracteristic write and reliable writes. + * The result of this API call is returned by a return value.\n + * @param[in] p_pre_queues The prepare write queues to be registered. + * @param[in] queue_num The number of prepare write queues to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_pre_queue parameter is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTS_SetPrepareQueue(st_ble_gatt_pre_queue_t * p_pre_queues, uint8_t queue_num); + +/*@}*/ + +/* ========================================== GATT Client API Declarations ========================================== */ + +/** @defgroup GATT_CLIENT_API GATT_CLIENT + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup GATT_CLIENT_API + * @fn ble_status_t R_BLE_GATTC_Init(uint8_t cb_num) + * @brief This function initializes the GATT Client and registers the number of the callbacks for GATT Client event. + * @details Specify the cb_num parameter to a value between 1 and BLE_GATTC_MAX_CB.\n + * R_BLE_GATTC_RegisterCb() registers the callback.\n + * The result of this API call is returned by a return value. + * @param[in] cb_num The number of callbacks to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The cb_num parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_Init(uint8_t cb_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority) + * @brief This function registers a callback function for GATT Client event. + * @details The number of the callback that may be registered by this function is the value specified + * by R_BLE_GATTC_Init().\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for GATT Client event. + * @param[in] priority The priority of the callback function.\n + * Valid range is 1 <= priority <= BLE_GATTC_MAX_CB.\n + * A lower priority number means a higher priority level. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The priority parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Host stack has already registered the maximum number of callbacks. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_RegisterCb(ble_gattc_app_cb_t cb, uint8_t priority); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb) + * @brief This function deregisters the callback function for GATT Client event. + * @details The result of this API call is returned by a return value. + * @param[in] cb The callback function to be deregistered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback has not been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DeregisterCb(ble_gattc_app_cb_t cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu) + * @brief This function sends a MTU Exchange Request PDU to a GATT Server in order to change the current MTU. + * @details MTU Exchange Response is notified by BLE_GATTC_EVENT_EX_MTU_RSP event.\n + * The new MTU is the minimum value of the mtu parameter specified by this function and + * the mtu field in BLE_GATTC_EVENT_EX_MTU_RSP event. + * Default MTU size is 23 bytes.\n + * The result of this API call is returned by a return value.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be sent. + * @param[in] mtu The maximum size(in bytes) of the GATT PDU that GATT Client can receive. \n + * Valid range is 23 <= mtu <= 247. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReqExMtu(uint16_t conn_hdl, uint16_t mtu); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl) + * @brief This function discovers all Primary Services in a GATT Server. + * @details When 16-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Primary Service has been discovered, BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event + * is notified to the application layer.\n + * When the Primary Service discovery has been completed, BLE_GATTC_EVENT_ALL_PRIM_SERV_DISC_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) This function was called while processing other request. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllPrimServ(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type) + * @brief This function discovers Primary Service specified by p_uuid in a GATT Server. + * @details When Primary Service whose uuid is the same as the specified uuid has been discovered, + * BLE_GATTC_EVENT_PRIM_SERV_16_DISC_IND event or BLE_GATTC_EVENT_PRIM_SERV_128_DISC_IND event is + * notified to the application layer.\n + * When the Primary Service discovery has been completed, BLE_GATTC_EVENT_PRIM_SERV_DISC_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_uuid UUID of Primary Service to be discovered. + * @param[in] uuid_type UUID type(16-bit or 128-bit). + * | macro | description | + * |:---------------------------------- |:---------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | 16-bit UUID | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | 128-bit UUID | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscPrimServ(uint16_t conn_hdl, uint8_t * p_uuid, uint8_t uuid_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllSecondServ( uint16_t conn_hdl) + * @brief This function discovers all Secondary Services in a GATT Server. + * @details When a 16-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_16_DISC_IND event + * is notified to the application layer.\n + * When a 128-bit UUID Secondary Service has been discovered, BLE_GATTC_EVENT_SECOND_SERV_128_DISC_IND event + * is notified to the application layer.\n + * When the Secondary Service discovery has been completed, BLE_GATTC_EVENT_ALL_SECOND_SERV_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllSecondServ(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Included Services within the specified attribute handle range in a GATT Server. + * @details When Included Service that includes 16-bit UUID Service has been discovered, + * BLE_GATTC_EVENT_INC_SERV_16_DISC_IND event is notified to the application layer.\n + * When Included Service that includes 128-bit UUID Service has been discovered, + * BLE_GATTC_EVENT_INC_SERV_128_DISC_IND event is notified to the application layer.\n + * When the Included Service discovery has been completed, + * BLE_GATTC_EVENT_INC_SERV_DISC_COMP event is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Included Service. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscIncServ(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Characteristic within the specified attribute handle range in a GATT Server. + * @details When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event + * is notified to the application layer.\n + * When the Characteristic discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllChar(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t conn_hdl, + * uint8_t * p_uuid, + * uint8_t uuid_type, + * st_ble_gatt_hdl_range_t * p_range + * ) + * @brief This function discovers Characteristic specified by uuid within the specified attribute handle range + * in a GATT Server. + * @details When 16-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_16_DISC_IND event + * is notified to the application layer.\n + * When 128-bit UUID Characteristic has been discovered, BLE_GATTC_EVENT_CHAR_128_DISC_IND event + * is notified to the application layer.\n + * When the Characteristic discovery has been completed, BLE_GATTC_EVENT_CHAR_DISC_COMP event + * is notified to the application layer.\n + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_uuid UUID of Characteristic to be discovered. + * @param[in] uuid_type UUID type of Characteristic to be discovered. + * | macro | description | + * |:---------------------------------- |:------------------------------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | The p_uuid parameter is 16-bit UUID. | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. | + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscCharByUuid(uint16_t conn_hdl, + uint8_t * p_uuid, + uint8_t uuid_type, + st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range) + * @brief This function discovers Characteristic Descriptor within the specified attribute handle range + * in a GATT Server. + * @details When 16-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_16_DISC_IND + * event is notified to the application layer. + * When 128-bit UUID Characteristic Descriptor has been discovered, BLE_GATTC_EVENT_CHAR_DESC_128_DISC_IND + * event is notified to the application layer. + * When the Characteristic Descriptor discovery has been completed, BLE_GATTC_EVENT_ALL_CHAR_DESC_DISC_COMP + * event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be discovered. + * @param[in] p_range Retrieval range of Characteristic Descriptor. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_DiscAllCharDesc(uint16_t conn_hdl, st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl) + * @brief This function reads a Characteristic/Characteristic Descriptor in a GATT Server. + * @details The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_RSP event. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be read. + * @param[in] value_hdl Value handle of the Characteristic/Characteristic Descriptor to be read. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadChar(uint16_t conn_hdl, uint16_t value_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t conn_hdl, + * uint8_t * p_uuid, + * uint8_t uuid_type, + * st_ble_gatt_hdl_range_t * p_range + * ); + * @brief This function reads a Characteristic in a GATT Server using a specified UUID. + * @details The result of the read is notified in BLE_GATTC_EVENT_CHAR_READ_BY_UUID_RSP event. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_uuid UUID of the Characteristic to be read. + * @param[in] uuid_type UUID type of the Characteristic to be read. + * | macro | description | + * |:---------------------------------- |:------------------------------------- | + * | BLE_GATT_16_BIT_UUID_FORMAT(0x01) | The p_uuid parameter is 16-bit UUID. | + * | BLE_GATT_128_BIT_UUID_FORMAT(0x02) | The p_uuid parameter is 128-bit UUID. | + * @param[in] p_range Retrieval range of Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_uuid parameter or the p_range parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The uuid_type parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadCharUsingUuid(uint16_t conn_hdl, + uint8_t * p_uuid, + uint8_t uuid_type, + st_ble_gatt_hdl_range_t * p_range); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset) + * @brief This function reads a Long Characteristic in a GATT Server. + * @details The contents of the Long Characteristic that has been read is notified every MTU-1 bytes to + * the application layer by BLE_GATTC_EVENT_CHAR_READ_RSP event.\n + * When all of the contents has been received in GATT Client, BLE_GATTC_EVENT_LONG_CHAR_READ_COMP event + * is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be read. + * @param[in] value_hdl Value handle of the Long Characteristic to be read. + * @param[in] offset Offset that indicates the location to be read.\n + * Normally, set 0 to this parameter. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the value_hdl parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadLongChar(uint16_t conn_hdl, uint16_t value_hdl, uint16_t offset); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list) + * @brief This function reads multiple Characteristics in a GATT Server. + * @details The contents of the multiple Characteristics that has been read is notified to the application layer + * by BLE_GATTC_EVENT_MULTI_CHAR_READ_RSP event. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_list List of Value Handles that point the Characteristics to be read. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_list parameter or the p_hdl_list field in the p_list parameter is + * specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) 0 is specified in the list_count field in the p_list parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReadMultiChar(uint16_t conn_hdl, st_ble_gattc_rd_multi_req_param_t * p_list); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes a Characteristic in a GATT Server without response. + * @details The result is returned from the API. + * @param[in] conn_hdl Connection handle that identifies Characteristic to be read to GATT Server. + * @param[in] p_write_data Value to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the p_value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteCharWithoutRsp(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes Signed Data to a Characteristic in a GATT Server without response. + * @details The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Signed Data to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or Signed Data. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_SignedWriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data) + * @brief This function writes a Characteristic in a GATT Server. + * @details The result of the write is notified in BLE_GATTC_EVENT_CHAR_WRITE_RSP event. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Value to be written to the Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field + * in the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - 0 is specified in the value_len field in the value field in the p_write_data parameter. + * - 0 is specified in the attr_hdl field in the p_write_data parameter. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl, + * st_ble_gatt_hdl_value_pair_t * p_write_data, + * uint16_t offset + * ) + * @brief This function writes a Long Characteristic in a GATT Server. + * @details The result of a write that has been done every segmentation is notified to the application layer + * in BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP event.\n + * The maximum writable size to a Long Characteristic with this function is 512 bytes.\n + * When all of the contents has been written to the Long Characteristic, BLE_GATTC_EVENT_LONG_CHAR_WRITE_COMP + * event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_write_data Value to be written to the Long Characteristic. + * @param[in] offset Offset that indicates the location to be written. + * Normally, set 0 to this parameter.\n + * If this parameter sets to a value other than 0, adjust the offset parameter and + * the length of the value to be written not to exceed the length of the Long Characteristic. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_write_data parameter or the p_value field in the value field in + * the p_write_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - The value_len field in the value field in the p_write_data parameter is 0. + * - The sum of the value_len field in the value field in the p_write_data parameter + * and the offset parameter larger than 512. + * - The attr_hdl field in the p_write_data parameter is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_WriteLongChar(uint16_t conn_hdl, st_ble_gatt_hdl_value_pair_t * p_write_data, uint16_t offset); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t conn_hdl, + * st_ble_gattc_reliable_writes_char_pair_t * p_char_pair, + * uint8_t pair_num, + * uint8_t auto_flag + * ) + * @brief This function performs the Reliable Writes procedure described in GATT Specification. + * @details When the data written to the Characteristic has been transmitted, BLE_GATTC_EVENT_CHAR_PART_WRITE_RSP + * event is notified to the application layer.\n + * If the data included in the event is different from the data that GATT Client has sent, + * host stack automatically cancels the Reliable Writes.\n + * After all of the contents has been sent to the GATT Server, if the auto_flag parameter has been set to + * BLE_GATTC_EXEC_AUTO, the GATT Server automatically writes the data to the Characteristic.\n + * If the auto_flag parameter has been set to BLE_GATTC_EXEC_NOT_AUTO, BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP + * event notifies the application layer in GATT Client that all of the contents has been sent to + * the GATT Server. Then GATT Client requests for writing the data to the Characteristic to the GATT Server + * with R_BLE_GATTC_ExecWrite().\n + * When the write has been done, BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event is notified to + * the application layer. + * @param[in] conn_hdl Connection handle identifying the GATT Server to be written. + * @param[in] p_char_pair Pair of Characteristic Value and Characteristic Value Handle identifying the Characteristic + * to be written by Reliable Writes. + * @param[in] pair_num The number of the pairs specified by the p_char_pair parameter.\n + * Valid range is 0 < pair_num <= BLE_GATTC_RELIABLE_WRITES_MAX_CHAR_PAIR. + * @param[in] auto_flag The flag that indicates whether auto execution or not. + * | macro | description | + * |:------------------------------ |:------------------- | + * | BLE_GATTC_EXEC_AUTO(0x01) | Auto execution. | + * | BLE_GATTC_EXEC_NOT_AUTO (0x02) | Not auto execution. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The reason for this error is as follows: + * - The p_char_pair parameter is specified as NULL. + * - The p_value field in the value field in the write_data field in the p_char_pair parameter + * is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The reason for this error is as follows: + * - The pair_num parameter or the auto_flag parameter is out of range. + * - The value_len field in the value field in the write_data field in the p_char_pair parameter is 0. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) While processing other request, this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function or + * to store the temporary write data. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ReliableWrites(uint16_t conn_hdl, + st_ble_gattc_reliable_writes_char_pair_t * p_char_pair, + uint8_t pair_num, + uint8_t auto_flag); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag) + * @brief If the auto execute of Reliable Writes is not specified by R_BLE_GATTC_ReliableWrites(), + * this function is used to execute a write to Characteristic. + * @details When all of the contents has been sent to the GATT Server, BLE_GATTC_EVENT_RELIABLE_WRITES_TX_COMP event + * notifies the application layer.\n + * After this event has been received, execute the write by this function.\n + * The result of the write is notified by BLE_GATTC_EVENT_RELIABLE_WRITES_COMP event. + * @param[in] conn_hdl Connection handle identifying the target GATT Server. + * @param[in] exe_flag The flag that indicates whether execution or cancellation. + * | macro | description | + * |:------------------------------------------- |:------------------- | + * | BLE_GATTC_EXECUTE_WRITE_CANCEL_FLAG(0x00) | Execute the write. | + * | BLE_GATTC_EXECUTE_WRITE_EXEC_FLAG(0x01) | Cancel the write. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The exe_flag parameter is out of range. + * @retval BLE_ERR_INVALID_OPERATION(0x0009) The reason for this error is as follows: + * - GATT Client has not requested for Reliable Writes by R_BLE_GATTC_ReliableWrites(). + * - Although auto execution has been specified by R_BLE_GATTC_ReliableWrites(), this function was called. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The GATT Server specified by conn_hdl was not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_GATTC_ExecWrite(uint16_t conn_hdl, uint8_t exe_flag); + +/*@}*/ + +/* ============================================= L2CAP API Declarations ============================================= */ + +/** @defgroup L2CAP_API L2CAP + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup L2CAP_API + * @fn ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm) + * @brief This function registers PSM that uses L2CAP CBFC Channel and a callback for L2CAP event. + * @details Only one callback is available per PSM. Configure in each PSM the Low Water Mark of the LE-Frames + * that the local device can receive.\n + * When the number of the credit reaches the Low Water Mark, BLE_L2CAP_EVENT_CF_LOW_RX_CRD_IND event is + * notified to the application layer.\n + * The number of PSM is defined as BLE_L2CAP_MAX_CBFC_PSM.\n + * The result of this API call is returned by a return value. + * @param[in] cb Callback function for L2CAP event. + * @param[in] psm Identifier indicating the protocol/profile that uses L2CAP CBFC Channel. + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
typerangedescription
Fixed, SIG assigned0x0001 - 0x007FPSM defined by SIG. For more information on PSM, refer Bluetooth SIG Assigned Number + * (https://www.bluetooth.com/specifications/assigned-numbers). + *
Dynamic0x0080 - 0x00FF + * Statically allocated PSM by custom protocol or dynamically allocated PSM by GATT Service. + *
+ * @param[in] lwm Low Water Mark that indicates the LE-Frame numbers that the local device can receive. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The cb parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The psm parameter is out of range. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) More than BLE_L2CAP_MAX_CBFC_PSM+1 PSMs, callbacks has been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_RegisterCfPsm(ble_l2cap_cf_app_cb_t cb, uint16_t psm, uint16_t lwm); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm) + * @brief This function stops the use of the L2CAP CBFC Channel specified by the psm parameter and + * deregisters the callback function for L2CAP event. + * @details The result of this API call is returned by a return value. + * @param[in] psm PSM that is to be stopped to use the L2CAP CBFC Channel.\n + * Set the PSM registered by R_BLE_L2CAP_RegisterCfPsm(). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_NOT_FOUND(0x000D) The callback function allocated by the psm parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_DeregisterCfPsm(uint16_t psm); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param) + * @brief This function sends a connection request for L2CAP CBFC Channel. + * @details The connection response is notified by BLE_L2CAP_EVENT_CF_CONN_CNF event.\n + * The result of this API call is returned by a return value. + * @param[in] conn_hdl Connection handle identifying the remote device that the connection request is sent to. + * @param[in] p_conn_req_param Connection request parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_conn_req_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The mtu parameter or the mps parameter is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) New CF Channel can not be registered or other L2CAP Command is processing. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) Insufficient memory is needed to generate this function. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by conn_hdl is not found. + * @retval BLE_ERR_NOT_YET_READY(0x0012) The psm parameter is not registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_ReqCfConn(uint16_t conn_hdl, st_ble_l2cap_conn_req_param_t * p_conn_req_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param) + * @brief This function replies to the connection request for L2CAP CBFC Channel from the remote device. + * @details The connection request is notified by BLE_L2CAP_EVENT_CF_CONN_IND event. + * The result of this API call is returned by a return value. + * @param[in] p_conn_rsp_param Connection response parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_conn_rsp_param parameter is specified as NULL. + * @retval BLE_ERR_NOT_FOUND(0x000D) A connection request for L2CAP CBFC Channel has not been received, + * or CID specified by the lcid field in the p_conn_rsp_param parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_RspCfConn(st_ble_l2cap_conn_rsp_param_t * p_conn_rsp_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid) + * @brief This function sends a disconnection request for L2CAP CBFC Channel. + * @details When L2CAP CBFC Channel has been disconnected, + * BLE_L2CAP_EVENT_CF_DISCONN_CNF event is notified to the application layer. + * @param[in] lcid CID identifying the L2CAP CBFC Channel that has been disconnected.\n + * The valid range is 0x40 - (0x40 + BLE_L2CAP_MAX_CBFC_PSM - 1). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_OPERATION(0x0009) CF Channel connection has not been established. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + * @retval BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_DisconnectCf(uint16_t lcid); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit) + * @brief This function sends credit to a remote device. + * @details In L2CAP CBFC communication, if credit is 0, the remote device stops data transmission.\n + * Therefore when processing the received data has been completed and local device affords to receive data, + * the remote device is notified of the number of LE-Frame that local device can receive + * by this function and local device can continue to receive data from the remote device.\n + * The result of this API call is returned by a return value. + * @param[in] lcid CID identifying the L2CAP CBFC Channel on local device that sends credit. + * @param[in] credit Credit to be sent to the remote device. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The credit parameter is set to 0. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) This function was called while processing other L2CAP command. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_SendCfCredit(uint16_t lcid, uint16_t credit); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu) + * @brief This function sends the data to a remote device via L2CAP CBFC Channel. + * @details When the data transmission to Controller has been completed, + * BLE_L2CAP_EVENT_CF_TX_DATA_CNF event is notified to the application layer. + * @param[in] conn_hdl Connection handle identifying the remote device to be sent the data. + * @param[in] lcid CID identifying the L2CAP CBFC Channel on local device used in the data transmission. + * @param[in] data_len Length of the data. + * @param[in] p_sdu Service Data Unit. \n + * Input the data length specified by the data_len parameter to the first 2 bytes (Little Endian). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_data parameter is specified as NULL. + * @retval BLE_ERR_INVALID_ARG(0x0003) The length parameter is out of range. + * @retval BLE_ERR_INVALID_STATE(0x0008) CF Channel connection has not been established or the data whose length + * exceeds the MTU has been sent. + * @retval BLE_ERR_ALREADY_IN_PROGRESS(0x000A) Data transmission has been already started. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) L2CAP task queue is full. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for L2CAP Command. + * @retval BLE_ERR_NOT_FOUND(0x000D) CID specified the lcid parameter is not found. + * @retval BLE_ERR_INVALID_HDL(0x000E) The remote device specified by the conn_hdl parameter is not found. + **********************************************************************************************************************/ +ble_status_t R_BLE_L2CAP_SendCfData(uint16_t conn_hdl, uint16_t lcid, uint16_t data_len, uint8_t * p_sdu); + +/*@}*/ + +/* ======================================== Vendor Specific API Declarations ======================================== */ + +/** @defgroup VS_API VS + * @ingroup BLE_API + * @{ + */ + +/******************************************************************************************************************//** + * @ingroup VS_API + * @fn ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb) + * @brief This function initializes Vendor Specific API and registers a callback function for Vendor Specific Event. + * @details The result of this API call is returned by a return value. + * @param[in] vs_cb Callback function to be registered. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The vs_cb parameter is specified as NULL. + * @retval BLE_ERR_CONTEXT_FULL(0x000B) Callback function has already been registered. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_Init(ble_vs_app_cb_t vs_cb); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param) + * @brief This function starts extended Transmitter Test. + * @details The following extended transmitter test functions of DTM Tx are supported by this function. + * - Tx Power + * - Tx Modulation Enable/Modulation Disable + * - Tx packet transmission/continuous transmission + * - Tx packets count + * + * The result of this API call is notified in BLE_VS_EVENT_TX_TEST_START event.\n + * If the num_of_packet field in the p_tx_test_param parameter is other than 0x0000, + * BLE_VS_EVENT_TX_TEST_TERM event notifies the application layer that the number of packet has been sent.\n + * If R_BLE_VS_EndTest() is called before the specified number of packets completions, + * BLE_VS_EVENT_TX_TEST_TERM event is not notified to the application layer. + * + * The condition that phy field in the p_tx_test_param parameter is @ref BLE_VS_EH_TEST_PHY_CODED_S_8(0x03) + * and option field is modulation(bit0:0) & continuous transmission(bit1:1) is not supported. + * + * @param[in] p_tx_test_param Tx Test parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_tx_test_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartTxTest(st_ble_vs_tx_test_param_t * p_tx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param) + * @brief This function starts extended Receiver Test. + * @details The result of this API call is notified in BLE_VS_EVENT_RX_TEST_START event. + * The following extended receiver test functions of DTM Rx are supported by this function. + * - Calculating the maximum, the minimum and the average of RSSI in the receiver test. + * - The number of CRC error packets in the receiver test. + * + * The transmitter is configured to one of the following, the receiver can't receive the packets by this function.\n + * - Tx Non-Modulation Enable + * - Tx continuous transmission + * \n + * After R_BLE_VS_EndTest() has been called, + * the receiver test result value are notified in BLE_VS_EVENT_TEST_END event. + * + * @param[in] p_rx_test_param The extended receiver test parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_rx_test_param parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartRxTest(st_ble_vs_rx_test_param_t * p_rx_test_param); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_EndTest(void) + * @brief This function terminates the extended transmitter or receiver test. + * @details The result of this API call is notified in BLE_VS_EVENT_TEST_END event. + * In case of extended receiver test, this event notifies the application layer of + * the result of the extended receiver test. + * + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_EndTest(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power) + * @brief This function configures transmit power. + * @details This function configures the following transmit power. + * - The transmit power used in sending advertising PDU, scan request PDU, + * connection request PDU (in not connected state) + * - The transmit power used in sending PDU in connected state. + * When configuring the transmit power used in not connected state, set the conn_hdl parameter + * to BLE_GAP_INIT_CONN_HDL(0xFFFF).\n + * When the transmit power used in connected state is configured, set the conn_hdl parameter + * to the connection handle of the link.\n + * Select one of the following transmit power levels. + * - High + * - Middle + * - Low + * + * Max transmit power of "High" is dependent on the configuration of the firmware. + * The result of this API call is notified in BLE_VS_EVENT_SET_TX_POWER event. + * + * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be configured. + * If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF). + * @param[in] tx_power Transmission power. Select one of the following. + * - BLE_VS_TX_POWER_HIGH(0x00) + * - BLE_VS_TX_POWER_MID(0x01) + * - BLE_VS_TX_POWER_LOW(0x02) + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetTxPower(uint16_t conn_hdl, uint8_t tx_power); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl) + * @brief This function gets transmit power. + * @details This function gets the following transmit power. + * - The transmit power used in sending advertising PDU, scan request PDU, + * connection request PDU (in not connected state) + * - The transmit power used in sending PDU in connected state. + * When getting the transmit power used in not connected state, set the conn_hdl parameter to + * BLE_GAP_INIT_CONN_HDL(0xFFFF).\n + * When the transmit power used in connected state is retrieved, set the conn_hdl parameter to + * the connection handle of the link. + * The result of this API call is notified in BLE_VS_EVENT_GET_TX_POWER event. + * + * @param[in] conn_hdl Connection handle identifying the link whose transmit power to be retrieved. + * If non connected state, set BLE_GAP_INIT_CONN_HDL(0xFFFF). + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetTxPower(uint16_t conn_hdl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme) + * @brief This function configure default Coding scheme(S=8 or S=2) that is used in the case of selecting Coded PHY + * in Primary advertising PHY or Secondary advertising PHY advertising or request for link establishment. + * @details After setting the default Coding scheme by this function, configure the advertising parameters + * by R_BLE_GAP_SetAdvParam() or send a request for link establishment.\n + * The result of this API call is notified in BLE_VS_EVENT_SET_CODING_SCHEME_COMP event. + * @param[in] coding_scheme Coding scheme for Primary advertising PHY, Secondary advertising PHY, + * request for link establishment.The coding_scheme field is set to a bitwise OR + * of the following values. + * | bit | description | + * |:-------------- |:-------------------------------------------------------------- | + * | bit0 | Coding scheme for Primary Advertising PHY(0:S=8/1:S=2). | + * | bit1 | Coding scheme for Secondary Advertising PHY(0:S=8/1:S=2). | + * | bit2 | Coding scheme for request for link establishment(0:S=8/1:S=2). | + * | All other bits | Reserved for future use. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetCodingScheme(uint8_t coding_scheme); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl) + * @brief This function performs power control on RF. + * @details If BLE communication is not used for a long time, RF reduces the power consumption by moving to + * the RF Power-Down Mode.\n + * When RF power on, RF initialization processing is executed.\n + * After RF power off by this function, API functions other than this are not available + * until RF power on again.\n + * The result of this API call is notified in BLE_VS_EVENT_RF_CONTROL_COMP event. + * After RF power on again with this function, call R_BLE_GAP_Terminate(), + * R_BLE_GAP_Init() in order to restart the host stack. + * @param[in] p_rf_ctrl RF parameters. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_rf_ctrl parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetRfControl(st_ble_vs_set_rf_ctrl_param_t * p_rf_ctrl); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr) + * @brief This function sets public/random address of local device to the area specified by the parameter. + * @details If the address is written in non-volatile area, the address is used as default address + * on the next MCU reset.\n + * For more information on the random address, refer to Core Specification Vol 6, PartB, + * "1.3.2 Random Device Address".\n + * The result of this API call is notified in BLE_VS_EVENT_SET_ADDR_COMP event. + * @param[in] area The area that the address is to be written in.\n + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_VS_ADDR_AREA_REG(0x00) + * Address writing to non-volatile area is not performed.
+ * Only the address in register is written. + *
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Address wiring to DataFlash area is performed.
+ * @param[in] p_addr The address to be set to the area. + * Set BLE_GAP_ADDR_PUBLIC(0x00) or BLE_GAP_ADDR_RAND(0x01) to the type field in the p_addr parameter. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_addr parameter is specified as NULL. + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetBdAddr(uint8_t area, st_ble_dev_addr_t * p_addr); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type) + * @brief This function gets currently configured public/random address. + * @details The area parameter specifies the place where this function retrieves public/random address.\n + * The result of this API call is notified in BLE_VS_EVENT_GET_ADDR_COMP event. + * @param[in] area The area that the address is to be retrieved.\n + * Select one of the following. + * + * + * + * + * + * + * + * + * + * + * + * + * + *
macrodescription
BLE_VS_ADDR_AREA_REG(0x00)Retrieve the address in register.
BLE_VS_ADDR_AREA_DATA_FLASH(0x01)Retrieve the address in DataFlash area.
+ * @param[in] addr_type The address type that is type of the address to be retrieved. + * | macro | description | + * |:------------------------- |:------------------ | + * | BLE_GAP_ADDR_PUBLIC(0x00) | Public address. | + * | BLE_GAP_ADDR_RAND(0x01) | Random address. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetBdAddr(uint8_t area, uint8_t addr_type); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetRand(uint8_t rand_size) + * @brief This function generates 4-16 bytes of random number used in creating keys. + * @details The result of this API call is notified in BLE_VS_EVENT_GET_RAND event. + * @param[in] rand_size Length of the random number (byte).\n + * The valid range is 4<=rand_size<=16. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_STATE(0x0008) The task for host stack is not running. + * @retval BLE_ERR_MEM_ALLOC_FAILED(0x000C) There are no memories for Vendor Specific Command. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetRand(uint8_t rand_size); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void) + * @brief This function starts the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of + * the state transition of TxFlow. + * @details If the number of the available transmission packet buffers is the following, + * BLE_VS_EVENT_TX_FLOW_STATE_CHG event notifies the application layer of the state of the TxFlow. + * - The number of the available transmission packet buffers is less than Low Water Mark. + * - The number of the available transmission packet buffers is more than High Water Mark. + * The result of this API call is returned by a return value. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartTxFlowEvtNtf(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void) + * @brief This function stops the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) of + * the state transition of TxFlow. + * @details The result of this API call is returned by a return value. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StopTxFlowEvtNtf(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num) + * @brief This function retrieves the number of the available transmission packet buffers. + * @details The maximum number of the available buffers is 10.\n + * The result of this API call is returned by a return value. + * @param[out] p_buffer_num The number of the available transmission packet buffers. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_PTR(0x0001) The p_buffer_num parameter is specified as NULL. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetTxBufferNum(uint32_t * p_buffer_num); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm) + * @brief This function sets the threshold for notifying the application layer of the TxFlow state. + * @details Call this function before the notification(BLE_VS_EVENT_TX_FLOW_STATE_CHG event) has been started + * by R_BLE_VS_StartTxFlowEvtNtf(). \n + * The result is returned from this API.\n + * Vendor Specific API supports the flow control function(TxFlow) for the transmission + * on L2CAP fixed channel in Basic Mode such as GATT.\n + * Host stack has 10 transmission packet buffers for the transmission.\n + * When the number of the available transmission packet buffers has been less than Low Water Mark, + * the state of TxFlow transmits into the TxFlow OFF state from the TxFlow ON state + * that is the initial state and host stack notifies the application layer of + * timing to stop packet transmission.\n + * When host stack has sent the transmission packets to Controller and the number of the available + * transmission packet buffers has been more than High Water Mark, the state of TxFlow transmits into + * the TxFlow ON state from the TxFlow OFF state and host stack notifies the application layer of + * timing to restart packet transmission.\n + * It is possible to perform flow control on a fixed channel by using the event notification. + * @param[in] tx_queue_lwm Low Water Mark. + * Set 0-9 less than tx_queue_hwm to the parameter. + * When the number of the available transmission packet buffers has been less than the value + * specified by the tx_queue_lwm parameter, host stack notifies the application layer of + * the timing to stop packet transmission. + * @param[in] tx_queue_hwm High Water Mark. + * Set 1-10 more than tx_queue_lwm to the parameter. + * When the number of the available transmission packet buffers has been more than + * the value specified by the tx_queue_hwm parameter, host stack notifies + * the application layer of the timing to restart packet transmission. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The tx_queue_lwm parameter or the tx_queue_hwm parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetTxLimit(uint32_t tx_queue_lwm, uint32_t tx_queue_hwm); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SetScanChMap(uint16_t ch_map) + * @brief This function sets the scan channel map. + * @details Set specify the scan channel for use.\n + * At least one channel must be enabled. + * @note Calling this API while Scan is already running will not change the channel map. + * @param[in] ch_map Specify the channel map for use. + * | bit | description | + * |:-------------- |:-------------------------------------------------- | + * | bit0 | Enable channel 37 for use (0:disable, 1:enable) | + * | bit1 | Enable channel 38 for use (0:disable, 1:enable) | + * | bit2 | Enable channel 39 for use (0:disable, 1:enable) | + * | All other bits | Reserved for future use. | + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG(0x0003) The ch_map parameter is out of range. + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SetScanChMap(uint16_t ch_map); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetScanChMap(void) + * @brief This function gets currently scan channel map. + * @details The result of this API call is notified in BLE_VS_EVENT_GET_SCAN_CH_MAP event. + * @retval BLE_SUCCESS(0x0000) Success + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetScanChMap(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_StartFirmwareUpdate(void) + * @brief This function starts the firmware update procedure. + * @details The result of this API call is notified in BLE_VS_EVENT_START_FW_UPDATE_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_StartFirmwareUpdate(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_SendFirmwareData(uint16_t index, uint16_t length, uint8_t const * const p_data) + * @brief This function sends a firmware update data frame. + * @param[in] index The index of the current data frame. + * @param[in] length The length of the current data frame. + * @param[in] p_data A pointer to the data frame. + * @details The result of this API call is notified in BLE_VS_EVENT_SEND_FW_DATA_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG An input parameter was invalid + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_SendFirmwareData(uint16_t index, uint16_t length, uint8_t const * const p_data); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_EndFirmwareUpdate(uint16_t end_index) + * @brief This function ends the firmware update procedure. + * @param[in] end_index The index of the last data frame. + * @details The result of this API call is notified in BLE_VS_EVENT_END_FW_UPDATE_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_EndFirmwareUpdate(uint16_t end_index); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_GetFirmwareVersion() + * @brief This function requests the BLE module firmware version. + * @details The result of this API call is notified in BLE_VS_EVENT_GET_FW_VERSION_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_GetFirmwareVersion(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_RestartModule(void) + * @brief This function restarts the module. + * @details The result of this API call is notified in BLE_VS_EVENT_MODULE_READY_COMP event. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_RSP_TIMEOUT A command did not receive a response + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_RestartModule(void); + +/******************************************************************************************************************//** + * @fn ble_status_t R_BLE_VS_UpdateModuleFirmware(void) + * @brief This function starts the firmware update procedure and blocks until the procedure has completed. + * @param[in] p_firmware_image The index of the current data frame. + * @param[in] firmware_image_size The length of the current data frame. + * @retval BLE_SUCCESS(0x0000) Success + * @retval BLE_ERR_INVALID_ARG An input parameter was invalid + * @retval BLE_ERR_RSP_TIMEOUT A command did not receive a response + * @retval BLE_ERR_INVALID_MODE A command was sent from an invalid mode + * @retval BLE_ERR_UNSUPPORTED This API does not support + **********************************************************************************************************************/ +ble_status_t R_BLE_VS_UpdateModuleFirmware(uint8_t const * const p_firmware_image, uint32_t firmware_image_size); + +/*@}*/ + +/*******************************************************************************************************************//** + * @} (end addtogroup BLE_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_cgc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_cgc_api.h new file mode 100644 index 00000000..cd6572c7 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_cgc_api.h @@ -0,0 +1,364 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CGC_API_H +#define R_CGC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup CGC_API CGC Interface + * @brief Interface for clock generation. + * + * @section CGC_API_SUMMARY Summary + * + * The CGC interface provides the ability to configure and use all of the CGC module's capabilities. Among the + * capabilities is the selection of several clock sources to use as the system clock source. Additionally, the + * system clocks can be divided down to provide a wide range of frequencies for various system and peripheral needs. + * + * Clock stability can be checked and clocks may also be stopped to save power when not needed. The API has a function + * to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect + * when the main oscillator has stopped, with the option of calling a user provided callback function. + * + * The CGC interface is implemented by: + * - @ref CGC + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events that can trigger a callback function */ +typedef enum e_cgc_event +{ + CGC_EVENT_OSC_STOP_DETECT ///< Oscillator stop detection has caused the event +} cgc_event_t; + +/** Callback function parameter data */ +typedef struct st_cgc_callback_args +{ + cgc_event_t event; ///< The event can be used to identify what caused the callback + void const * p_context; ///< Placeholder for user data +} cgc_callback_args_t; + +/** System clock source identifiers - The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock + * divider */ +typedef enum e_cgc_clock +{ + CGC_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + CGC_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + CGC_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + CGC_CLOCK_MAIN_OSC = 3, ///< The main oscillator + CGC_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + CGC_CLOCK_PLL = 5, ///< The PLL oscillator + CGC_CLOCK_PLL2 = 6, ///< The PLL2 oscillator +} cgc_clock_t; + +/** PLL divider values */ +typedef enum e_cgc_pll_div +{ + CGC_PLL_DIV_1 = 0, ///< PLL divider of 1 + CGC_PLL_DIV_2 = 1, ///< PLL divider of 2 + CGC_PLL_DIV_3 = 2, ///< PLL divider of 3 (S7, S5 only) + CGC_PLL_DIV_4 = 3, ///< PLL divider of 4 (S3 only) +} cgc_pll_div_t; + +/** PLL multiplier values */ +typedef enum e_cgc_pll_mul +{ + CGC_PLL_MUL_8_0 = 0xF, ///< PLL multiplier of 8.0 + CGC_PLL_MUL_9_0 = 0x11, ///< PLL multiplier of 9.0 + CGC_PLL_MUL_10_0 = 0x13, ///< PLL multiplier of 10.0 + CGC_PLL_MUL_10_5 = 0x14, ///< PLL multiplier of 10.5 + CGC_PLL_MUL_11_0 = 0x15, ///< PLL multiplier of 11.0 + CGC_PLL_MUL_11_5 = 0x16, ///< PLL multiplier of 11.5 + CGC_PLL_MUL_12_0 = 0x17, ///< PLL multiplier of 12.0 + CGC_PLL_MUL_12_5 = 0x18, ///< PLL multiplier of 12.5 + CGC_PLL_MUL_13_0 = 0x19, ///< PLL multiplier of 13.0 + CGC_PLL_MUL_13_5 = 0x1A, ///< PLL multiplier of 13.5 + CGC_PLL_MUL_14_0 = 0x1B, ///< PLL multiplier of 14.0 + CGC_PLL_MUL_14_5 = 0x1D, ///< PLL multiplier of 14.5 + CGC_PLL_MUL_15_0 = 0x1D, ///< PLL multiplier of 15.0 + CGC_PLL_MUL_15_5 = 0x1E, ///< PLL multiplier of 15.5 + CGC_PLL_MUL_16_0 = 0x1F, ///< PLL multiplier of 16.0 + CGC_PLL_MUL_16_5 = 0x20, ///< PLL multiplier of 16.5 + CGC_PLL_MUL_17_0 = 0x21, ///< PLL multiplier of 17.0 + CGC_PLL_MUL_17_5 = 0x22, ///< PLL multiplier of 17.5 + CGC_PLL_MUL_18_0 = 0x23, ///< PLL multiplier of 18.0 + CGC_PLL_MUL_18_5 = 0x24, ///< PLL multiplier of 18.5 + CGC_PLL_MUL_19_0 = 0x25, ///< PLL multiplier of 19.0 + CGC_PLL_MUL_19_5 = 0x26, ///< PLL multiplier of 19.5 + CGC_PLL_MUL_20_0 = 0x27, ///< PLL multiplier of 20.0 + CGC_PLL_MUL_20_5 = 0x28, ///< PLL multiplier of 20.5 + CGC_PLL_MUL_21_0 = 0x29, ///< PLL multiplier of 21.0 + CGC_PLL_MUL_21_5 = 0x2A, ///< PLL multiplier of 21.5 + CGC_PLL_MUL_22_0 = 0x2B, ///< PLL multiplier of 22.0 + CGC_PLL_MUL_22_5 = 0x2C, ///< PLL multiplier of 22.5 + CGC_PLL_MUL_23_0 = 0x2D, ///< PLL multiplier of 23.0 + CGC_PLL_MUL_23_5 = 0x2E, ///< PLL multiplier of 23.5 + CGC_PLL_MUL_24_0 = 0x2F, ///< PLL multiplier of 24.0 + CGC_PLL_MUL_24_5 = 0x30, ///< PLL multiplier of 24.5 + CGC_PLL_MUL_25_0 = 0x31, ///< PLL multiplier of 25.0 + CGC_PLL_MUL_25_5 = 0x32, ///< PLL multiplier of 25.5 + CGC_PLL_MUL_26_0 = 0x33, ///< PLL multiplier of 26.0 + CGC_PLL_MUL_26_5 = 0x34, ///< PLL multiplier of 26.5 + CGC_PLL_MUL_27_0 = 0x35, ///< PLL multiplier of 27.0 + CGC_PLL_MUL_27_5 = 0x36, ///< PLL multiplier of 27.5 + CGC_PLL_MUL_28_0 = 0x37, ///< PLL multiplier of 28.0 + CGC_PLL_MUL_28_5 = 0x38, ///< PLL multiplier of 28.5 + CGC_PLL_MUL_29_0 = 0x39, ///< PLL multiplier of 29.0 + CGC_PLL_MUL_29_5 = 0x3A, ///< PLL multiplier of 29.5 + CGC_PLL_MUL_30_0 = 0x3B, ///< PLL multiplier of 30.0 + CGC_PLL_MUL_31_0 = 0x3D, ///< PLL multiplier of 31.0 +} cgc_pll_mul_t; + +/** System clock divider vlues - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, + * PCLKS A-D. */ +typedef enum e_cgc_sys_clock_div +{ + CGC_SYS_CLOCK_DIV_1 = 0, ///< System clock divided by 1 + CGC_SYS_CLOCK_DIV_2 = 1, ///< System clock divided by 2 + CGC_SYS_CLOCK_DIV_4 = 2, ///< System clock divided by 4 + CGC_SYS_CLOCK_DIV_8 = 3, ///< System clock divided by 8 + CGC_SYS_CLOCK_DIV_16 = 4, ///< System clock divided by 16 + CGC_SYS_CLOCK_DIV_32 = 5, ///< System clock divided by 32 + CGC_SYS_CLOCK_DIV_64 = 6, ///< System clock divided by 64 +} cgc_sys_clock_div_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ +typedef struct st_cgc_pll_cfg +{ + cgc_clock_t source_clock; ///< PLL source clock (main oscillator or HOCO) + cgc_pll_div_t divider; ///< PLL divider + cgc_pll_mul_t multiplier; ///< PLL multiplier +} cgc_pll_cfg_t; + +/** Clock configuration structure - Used as an input parameter to the @ref cgc_api_t::systemClockSet and @ref cgc_api_t::systemClockGet + * functions. */ +typedef union u_cgc_divider_cfg +{ + uint32_t sckdivcr_w; ///< (@ 0x4001E020) System clock Division control register + + struct + { + cgc_sys_clock_div_t pclkd_div : 3; ///< Divider value for PCLKD + uint32_t : 1; + cgc_sys_clock_div_t pclkc_div : 3; ///< Divider value for PCLKC + uint32_t : 1; + cgc_sys_clock_div_t pclkb_div : 3; ///< Divider value for PCLKB + uint32_t : 1; + cgc_sys_clock_div_t pclka_div : 3; ///< Divider value for PCLKA + uint32_t : 1; + cgc_sys_clock_div_t bclk_div : 3; ///< Divider value for BCLK + uint32_t : 5; + cgc_sys_clock_div_t iclk_div : 3; ///< Divider value for ICLK + uint32_t : 1; + cgc_sys_clock_div_t fclk_div : 3; ///< Divider value for FCLK + uint32_t : 1; + } sckdivcr_b; +} cgc_divider_cfg_t; + +/** USB clock divider values */ +typedef enum e_cgc_usb_clock_div +{ + CGC_USB_CLOCK_DIV_3 = 2, ///< Divide USB source clock by 3 + CGC_USB_CLOCK_DIV_4 = 3, ///< Divide USB source clock by 4 + CGC_USB_CLOCK_DIV_5 = 4, ///< Divide USB source clock by 5 +} cgc_usb_clock_div_t; + +/** Clock options */ +typedef enum e_cgc_clock_change +{ + CGC_CLOCK_CHANGE_START = 0, ///< Start the clock + CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock + CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock +} cgc_clock_change_t; + +/** CGC control block. Allocate an instance specific control block to pass into the CGC API calls. + * @par Implemented as + * - cgc_instance_ctrl_t + */ +typedef void cgc_ctrl_t; + +/** Configuration options. */ +typedef struct s_cgc_cfg +{ + void (* p_callback)(cgc_callback_args_t * p_args); + void const * p_context; +} cgc_cfg_t; + +/** Clock configuration */ +typedef struct st_cgc_clocks_cfg +{ + cgc_clock_t system_clock; ///< System clock source enumeration + cgc_pll_cfg_t pll_cfg; ///< PLL configuration structure + cgc_pll_cfg_t pll2_cfg; ///< PLL2 configuration structure + cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure + cgc_clock_change_t loco_state; ///< State of LOCO + cgc_clock_change_t moco_state; ///< State of MOCO + cgc_clock_change_t hoco_state; ///< State of HOCO + cgc_clock_change_t mainosc_state; ///< State of Main oscillator + cgc_clock_change_t pll_state; ///< State of PLL + cgc_clock_change_t pll2_state; ///< State of PLL2 +} cgc_clocks_cfg_t; + +/** CGC functions implemented at the HAL layer follow this API. */ +typedef struct +{ + /** Initial configuration + * @par Implemented as + * - @ref R_CGC_Open() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_cfg Pointer to configuration + */ + fsp_err_t (* open)(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg); + + /** Configure all system clocks. + * @par Implemented as + * - @ref R_CGC_ClocksCfg() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_clock_cfg Pointer to desired configuration of system clocks + */ + fsp_err_t (* clocksCfg)(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg); + + /** Start a clock. + * @par Implemented as + * - @ref R_CGC_ClockStart() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to start + * @param[in] p_pll_cfg Pointer to PLL configuration, can be NULL if clock_source is not CGC_CLOCK_PLL or + * CGC_CLOCK_PLL2 + */ + fsp_err_t (* clockStart)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_pll_cfg_t const * const p_pll_cfg); + + /** Stop a clock. + * @par Implemented as + * - @ref R_CGC_ClockStop() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source The clock source to stop + */ + fsp_err_t (* clockStop)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Check the stability of the selected clock. + * @par Implemented as + * - @ref R_CGC_ClockCheck() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Which clock source to check for stability + */ + fsp_err_t (* clockCheck)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); + + /** Set the system clock. + * @par Implemented as + * - @ref R_CGC_SystemClockSet() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] clock_source Clock source to set as system clock + * @param[in] p_divider_cfg Pointer to the clock divider configuration + */ + fsp_err_t (* systemClockSet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, + cgc_divider_cfg_t const * const p_divider_cfg); + + /** Get the system clock information. + * @par Implemented as + * - @ref R_CGC_SystemClockGet() + * @param[in] p_ctrl Pointer to instance control block + * @param[out] p_clock_source Returns the current system clock + * @param[out] p_divider_cfg Returns the current system clock dividers + */ + fsp_err_t (* systemClockGet)(cgc_ctrl_t * const p_ctrl, cgc_clock_t * const p_clock_source, + cgc_divider_cfg_t * const p_divider_cfg); + + /** Enable and optionally register a callback for Main Oscillator stop detection. + * @par Implemented as + * - @ref R_CGC_OscStopDetectEnable() + * @param[in] p_ctrl Pointer to instance control block + * @param[in] p_callback Callback function that will be called by the NMI interrupt when an oscillation stop is + * detected. If the second argument is "false", then this argument can be NULL. + * @param[in] enable Enable/disable Oscillation Stop Detection + */ + fsp_err_t (* oscStopDetectEnable)(cgc_ctrl_t * const p_ctrl); + + /** Disable Main Oscillator stop detection. + * @par Implemented as + * - @ref R_CGC_OscStopDetectDisable() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopDetectDisable)(cgc_ctrl_t * const p_ctrl); + + /** Clear the oscillator stop detection flag. + * @par Implemented as + * - @ref R_CGC_OscStopStatusClear() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* oscStopStatusClear)(cgc_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_CGC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the CGC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(cgc_ctrl_t * const p_api_ctrl, void (* p_callback)(cgc_callback_args_t *), + void const * const p_context, cgc_callback_args_t * const p_callback_memory); + + /** Close the CGC driver. + * @par Implemented as + * - @ref R_CGC_Close() + * @param[in] p_ctrl Pointer to instance control block + */ + fsp_err_t (* close)(cgc_ctrl_t * const p_ctrl); +} cgc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_cgc_instance +{ + cgc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + cgc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + cgc_api_t const * p_api; ///< Pointer to the API structure for this instance +} cgc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CGC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_CGC_API_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_crc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_crc_api.h new file mode 100644 index 00000000..530a059e --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_crc_api.h @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CRC_API_H +#define R_CRC_API_H + +/*******************************************************************************************************************//** + * @defgroup CRC_API CRC Interface + * @ingroup RENESAS_INTERFACES + * + * @brief Interface for cyclic redundancy checking. + * + * @section CRC_API_SUMMARY Summary + * The CRC (Cyclic Redundancy Check) calculator generates CRC codes using five different polynomials including 8 bit, + * 16 bit, and 32 bit variations. Calculation can be performed by sending data to the block using the CPU or by snooping + * on read or write activity on one of 10 SCI channels. + * + * Implemented by: + * - @ref CRC + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CRC Generating Polynomial Switching (GPS). */ +typedef enum e_crc_polynomial +{ + CRC_POLYNOMIAL_CRC_8 = 1, ///< 8-bit CRC-8 (X^8 + X^2 + X + 1) + CRC_POLYNOMIAL_CRC_16, ///< 16-bit CRC-16 (X^16 + X^15 + X^2 + 1) + CRC_POLYNOMIAL_CRC_CCITT, ///< 16-bit CRC-CCITT (X^16 + X^12 + X^5 + 1) + + /** 32-bit CRC-32 (X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 + X^8 + X^7 + X^5 + X^4 + X^2 + X + 1) */ + CRC_POLYNOMIAL_CRC_32, + + /** 32-bit CRC-32C (X^32 + X^28 + X^27 + X^26 + X^25 + X^23 + X^22 + X^20 + X^19 + X^18 + X^14 + X^13 + X^11 + X^10 + X^9 + X^8 + + * X^6 + 1) */ + CRC_POLYNOMIAL_CRC_32C, +} crc_polynomial_t; + +/** CRC Calculation Switching (LMS) */ +typedef enum e_crc_bit_order +{ + CRC_BIT_ORDER_LMS_LSB = 0, ///< Generates CRC for LSB first communication + CRC_BIT_ORDER_LMS_MSB, ///< Generates CRC for MSB first communication +} crc_bit_order_t; + +/** Snoop-On-Write/Read Switch (CRCSWR) */ +typedef enum e_crc_snoop_direction +{ + CRC_SNOOP_DIRECTION_RECEIVE = 0, ///< Snoop-on-read + CRC_SNOOP_DIRECTION_TRANSMIT, ///< Snoop-on-write +} crc_snoop_direction_t; + +/** Snoop SCI register Address (lower 14 bits) */ +typedef enum e_snoop_address_sci +{ + CRC_SNOOP_ADDRESS_NONE = 0x00, ///< Snoop mode disabled + CRC_SNOOP_ADDRESS_SCI0_TDR = 0x003, ///< Snoop SCI0 transmit data register + CRC_SNOOP_ADDRESS_SCI1_TDR = 0x023, ///< Snoop SCI1 transmit data register + CRC_SNOOP_ADDRESS_SCI2_TDR = 0x043, ///< Snoop SCI2 transmit data register + CRC_SNOOP_ADDRESS_SCI3_TDR = 0x063, ///< Snoop SCI3 transmit data register + CRC_SNOOP_ADDRESS_SCI4_TDR = 0x083, ///< Snoop SCI4 transmit data register + CRC_SNOOP_ADDRESS_SCI5_TDR = 0x0A3, ///< Snoop SCI5 transmit data register + CRC_SNOOP_ADDRESS_SCI6_TDR = 0x0C3, ///< Snoop SCI6 transmit data register + CRC_SNOOP_ADDRESS_SCI7_TDR = 0x0E3, ///< Snoop SCI7 transmit data register + CRC_SNOOP_ADDRESS_SCI8_TDR = 0x103, ///< Snoop SCI8 transmit data register + CRC_SNOOP_ADDRESS_SCI9_TDR = 0x123, ///< Snoop SCI9 transmit data register + CRC_SNOOP_ADDRESS_SCI0_FTDRL = 0x00F, ///< Snoop SCI0 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI1_FTDRL = 0x02F, ///< Snoop SCI1 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI2_FTDRL = 0x04F, ///< Snoop SCI2 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI3_FTDRL = 0x06F, ///< Snoop SCI3 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI4_FTDRL = 0x08F, ///< Snoop SCI4 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI5_FTDRL = 0x0AF, ///< Snoop SCI5 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI6_FTDRL = 0x0CF, ///< Snoop SCI6 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI7_FTDRL = 0x0EF, ///< Snoop SCI7 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI8_FTDRL = 0x10F, ///< Snoop SCI8 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI9_FTDRL = 0x12F, ///< Snoop SCI9 transmit FIFO data register + CRC_SNOOP_ADDRESS_SCI0_RDR = 0x005, ///< Snoop SCI0 receive data register + CRC_SNOOP_ADDRESS_SCI1_RDR = 0x025, ///< Snoop SCI1 receive data register + CRC_SNOOP_ADDRESS_SCI2_RDR = 0x045, ///< Snoop SCI2 receive data register + CRC_SNOOP_ADDRESS_SCI3_RDR = 0x065, ///< Snoop SCI3 receive data register + CRC_SNOOP_ADDRESS_SCI4_RDR = 0x085, ///< Snoop SCI4 receive data register + CRC_SNOOP_ADDRESS_SCI5_RDR = 0x0A5, ///< Snoop SCI5 receive data register + CRC_SNOOP_ADDRESS_SCI6_RDR = 0x0C5, ///< Snoop SCI6 receive data register + CRC_SNOOP_ADDRESS_SCI7_RDR = 0x0E5, ///< Snoop SCI7 receive data register + CRC_SNOOP_ADDRESS_SCI8_RDR = 0x105, ///< Snoop SCI8 receive data register + CRC_SNOOP_ADDRESS_SCI9_RDR = 0x125, ///< Snoop SCI9 receive data register + CRC_SNOOP_ADDRESS_SCI0_FRDRL = 0x011, ///< Snoop SCI0 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI1_FRDRL = 0x031, ///< Snoop SCI1 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI2_FRDRL = 0x051, ///< Snoop SCI2 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI3_FRDRL = 0x071, ///< Snoop SCI3 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI4_FRDRL = 0x091, ///< Snoop SCI4 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI5_FRDRL = 0x0B1, ///< Snoop SCI5 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI6_FRDRL = 0x0D1, ///< Snoop SCI6 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI7_FRDRL = 0x0F1, ///< Snoop SCI7 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI8_FRDRL = 0x111, ///< Snoop SCI8 receive FIFO data register + CRC_SNOOP_ADDRESS_SCI9_FRDRL = 0x131, ///< Snoop SCI9 receive FIFO data register +} crc_snoop_address_t; + +/** Structure for CRC inputs */ +typedef struct st_crc_input_t +{ + uint32_t num_bytes; // Length of input buffer + uint32_t crc_seed; // CRC seed value + void * p_input_buffer; // Pointer to input buffer +} crc_input_t; + +/** CRC control block. Allocate an instance specific control block to pass into the CRC API calls. + * @par Implemented as + * - crc_instance_ctrl_t + */ +typedef void crc_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_crc_cfg +{ + crc_polynomial_t polynomial; ///< CRC Generating Polynomial Switching (GPS) + crc_bit_order_t bit_order; ///< CRC Calculation Switching (LMS) + crc_snoop_address_t snoop_address; ///< Register Snoop Address (CRCSA) + void const * p_extend; ///< CRC Hardware Dependent Configuration +} crc_cfg_t; + +/** CRC driver structure. General CRC functions implemented at the HAL layer will follow this API. */ +typedef struct st_crc_api +{ + /** Open the CRC driver module. + * @par Implemented as + * - @ref R_CRC_Open() + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[in] p_cfg Pointer to a configuration structure. + **/ + fsp_err_t (* open)(crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg); + + /** Close the CRC module driver + * @par Implemented as + * - @ref R_CRC_Close() + * + * @param[in] p_ctrl Pointer to crc device handle + * @retval FSP_SUCCESS Configuration was successful. + **/ + fsp_err_t (* close)(crc_ctrl_t * const p_ctrl); + + /** Return the current calculated value. + * @par Implemented as + * - @ref R_CRC_CalculatedValueGet() + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[out] crc_result The calculated value from the last CRC calculation. + **/ + fsp_err_t (* crcResultGet)(crc_ctrl_t * const p_ctrl, uint32_t * crc_result); + + /** Configure and Enable snooping. + * @par Implemented as + * - @ref R_CRC_SnoopEnable() + * + * @param[in] p_ctrl Pointer to CRC device handle. + * @param[in] crc_seed CRC seed. + **/ + fsp_err_t (* snoopEnable)(crc_ctrl_t * const p_ctrl, uint32_t crc_seed); + + /** Disable snooping. + * @par Implemented as + * - @ref R_CRC_SnoopDisable() + * + * @param[in] p_ctrl Pointer to CRC device handle. + **/ + fsp_err_t (* snoopDisable)(crc_ctrl_t * const p_ctrl); + + /** Perform a CRC calculation on a block of data. + * @par Implemented as + * - @ref R_CRC_Calculate() + * + * @param[in] p_ctrl Pointer to crc device handle. + * @param[in] p_crc_input A pointer to structure for CRC inputs + * @param[out] crc_result The calculated value of the CRC calculation. + **/ + fsp_err_t (* calculate)(crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_input, uint32_t * p_crc_result); +} crc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_crc_instance +{ + crc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + crc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + crc_api_t const * p_api; ///< Pointer to the API structure for this instance +} crc_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup CRC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_dac_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_dac_api.h new file mode 100644 index 00000000..63b14b8f --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_dac_api.h @@ -0,0 +1,152 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup DAC_API DAC Interface + * @brief Interface for D/A converters. + * + * @section DAC_API_SUMMARY Summary + * The DAC interface provides standard Digital/Analog Converter functionality. A DAC application writes digital + * sample data to the device and generates analog output on the DAC output pin. + * + * Implemented by: + * - @ref DAC + * - @ref DAC8 + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_DAC_API_H +#define R_DAC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DAC Open API data format settings. */ +typedef enum e_dac_data_format +{ + DAC_DATA_FORMAT_FLUSH_RIGHT = 0, ///< LSB of data is flush to the right leaving the top 4 bits unused. + DAC_DATA_FORMAT_FLUSH_LEFT = 1 ///< MSB of data is flush to the left leaving the bottom 4 bits unused. +} dac_data_format_t; + +/** DAC information structure to store various information for a DAC */ +typedef struct dac_info +{ + uint8_t bit_width; ///< Resolution of the DAC. +} dac_info_t; + +/** DAC Open API configuration parameter */ +typedef struct st_dac_cfg +{ + uint8_t channel; ///< ID associated with this DAC channel + bool ad_da_synchronized; ///< AD/DA synchronization + void const * p_extend; +} dac_cfg_t; + +/** DAC control block. Allocate an instance specific control block to pass into the DAC API calls. + * @par Implemented as + * - dac_instance_ctrl_t + * - dac8_instance_ctrl_t + */ +typedef void dac_ctrl_t; + +/** DAC driver structure. General DAC functions implemented at the HAL layer follow this API. */ +typedef struct st_dac_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_DAC_Open() + * - @ref R_DAC8_Open() + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(dac_ctrl_t * const p_ctrl, dac_cfg_t const * const p_cfg); + + /** Close the D/A Converter. + * @par Implemented as + * - @ref R_DAC_Close() + * - @ref R_DAC8_Close() + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* close)(dac_ctrl_t * const p_ctrl); + + /** Write sample value to the D/A Converter. + * @par Implemented as + * - @ref R_DAC_Write() + * - @ref R_DAC8_Write() + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + * @param[in] value Sample value to be written to the D/A Converter. + */ + fsp_err_t (* write)(dac_ctrl_t * const p_ctrl, uint16_t value); + + /** Start the D/A Converter if it has not been started yet. + * @par Implemented as + * - @ref R_DAC_Start() + * - @ref R_DAC8_Start() + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* start)(dac_ctrl_t * const p_ctrl); + + /** Stop the D/A Converter if the converter is running. + * @par Implemented as + * - @ref R_DAC_Stop() + * - @ref R_DAC8_Stop() + * + * @param[in] p_ctrl Control block set in @ref dac_api_t::open call for this timer. + */ + fsp_err_t (* stop)(dac_ctrl_t * const p_ctrl); +} dac_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_dac_instance +{ + dac_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + dac_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + dac_api_t const * p_api; ///< Pointer to the API structure for this instance +} dac_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup DAC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_elc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_elc_api.h new file mode 100644 index 00000000..8e885b65 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_elc_api.h @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup ELC_API ELC Interface + * @brief Interface for the Event Link Controller. + * + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_ELC_API_H +#define R_ELC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef ELC_PERIPHERAL_NUM + #define ELC_PERIPHERAL_NUM (23U) +#endif + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#ifndef BSP_OVERRIDE_ELC_PERIPHERAL_T + +/** Possible peripherals to be linked to event signals (not all available on all MCUs) */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_GPT_A = (0), + ELC_PERIPHERAL_GPT_B = (1), + ELC_PERIPHERAL_GPT_C = (2), + ELC_PERIPHERAL_GPT_D = (3), + ELC_PERIPHERAL_GPT_E = (4), + ELC_PERIPHERAL_GPT_F = (5), + ELC_PERIPHERAL_GPT_G = (6), + ELC_PERIPHERAL_GPT_H = (7), + ELC_PERIPHERAL_ADC0 = (8), + ELC_PERIPHERAL_ADC0_B = (9), + ELC_PERIPHERAL_ADC1 = (10), + ELC_PERIPHERAL_ADC1_B = (11), + ELC_PERIPHERAL_DAC0 = (12), + ELC_PERIPHERAL_DAC1 = (13), + ELC_PERIPHERAL_IOPORT1 = (14), + ELC_PERIPHERAL_IOPORT2 = (15), + ELC_PERIPHERAL_IOPORT3 = (16), + ELC_PERIPHERAL_IOPORT4 = (17), + ELC_PERIPHERAL_CTSU = (18), + ELC_PERIPHERAL_DA8_0 = (19), + ELC_PERIPHERAL_DA8_1 = (20), + ELC_PERIPHERAL_SDADC0 = (22), +} elc_peripheral_t; + +#endif + +/** ELC control block. Allocate an instance specific control block to pass into the ELC API calls. + * @par Implemented as + * - elc_instance_ctrl_t + */ +typedef void elc_ctrl_t; + +/** Main configuration structure for the Event Link Controller */ +typedef struct st_elc_cfg +{ + elc_event_t const link[ELC_PERIPHERAL_NUM]; ///< Event link register (ELSR) settings +} elc_cfg_t; + +/** Software event number */ +typedef enum e_elc_software_event +{ + ELC_SOFTWARE_EVENT_0, ///< Software event 0 + ELC_SOFTWARE_EVENT_1, ///< Software event 1 +} elc_software_event_t; + +/** ELC driver structure. General ELC functions implemented at the HAL layer follow this API. */ +typedef struct st_elc_api +{ + /** Initialize all links in the Event Link Controller. + * @par Implemented as + * - @ref R_ELC_Open() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. + **/ + fsp_err_t (* open)(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg); + + /** Disable all links in the Event Link Controller and close the API. + * @par Implemented as + * - @ref R_ELC_Close() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(elc_ctrl_t * const p_ctrl); + + /** Generate a software event in the Event Link Controller. + * @par Implemented as + * - @ref R_ELC_SoftwareEventGenerate() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] eventNum Software event number to be generated. + **/ + fsp_err_t (* softwareEventGenerate)(elc_ctrl_t * const p_ctrl, elc_software_event_t event_num); + + /** Create a single event link. + * @par Implemented as + * - @ref R_ELC_LinkSet() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] peripheral The peripheral block that will receive the event signal. + * @param[in] signal The event signal. + **/ + fsp_err_t (* linkSet)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal); + + /** Break an event link. + * @par Implemented as + * - @ref R_ELC_LinkBreak() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] peripheral The peripheral that should no longer be linked. + **/ + fsp_err_t (* linkBreak)(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral); + + /** Enable the operation of the Event Link Controller. + * @par Implemented as + * - @ref R_ELC_Enable() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* enable)(elc_ctrl_t * const p_ctrl); + + /** Disable the operation of the Event Link Controller. + * @par Implemented as + * - @ref R_ELC_Disable() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* disable)(elc_ctrl_t * const p_ctrl); +} elc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_elc_instance +{ + elc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + elc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + elc_api_t const * p_api; ///< Pointer to the API structure for this instance +} elc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup ELC_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_external_irq_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_external_irq_api.h new file mode 100644 index 00000000..f8b7e043 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_external_irq_api.h @@ -0,0 +1,177 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup EXTERNAL_IRQ_API External IRQ Interface + * @brief Interface for detecting external interrupts. + * + * @section EXTERNAL_IRQ_API_Summary Summary + * The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an + * external IRQ pin. + * + * The External IRQ Interface can be implemented by: + * - @ref ICU + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_EXTERNAL_IRQ_API_H +#define R_EXTERNAL_IRQ_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Callback function parameter data */ +typedef struct st_external_irq_callback_args +{ + /** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */ + void const * p_context; + uint32_t channel; ///< The physical hardware channel that caused the interrupt. +} external_irq_callback_args_t; + +/** Condition that will trigger an interrupt when detected. */ +typedef enum e_external_irq_trigger +{ + EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger + EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger + EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger + EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger +} external_irq_trigger_t; + +/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger + * conditions that are shorter than 3 periods of the filter clock. + */ +typedef enum e_external_irq_pclk_div +{ + EXTERNAL_IRQ_PCLK_DIV_BY_1 = 0, ///< Filter using PCLK divided by 1 + EXTERNAL_IRQ_PCLK_DIV_BY_8 = 1, ///< Filter using PCLK divided by 8 + EXTERNAL_IRQ_PCLK_DIV_BY_32 = 2, ///< Filter using PCLK divided by 32 + EXTERNAL_IRQ_PCLK_DIV_BY_64 = 3, ///< Filter using PCLK divided by 64 +} external_irq_pclk_div_t; + +/** User configuration structure, used in open function */ +typedef struct st_external_irq_cfg +{ + uint8_t channel; ///< Hardware channel used. + uint8_t ipl; ///< Interrupt priority + IRQn_Type irq; ///< NVIC interrupt number assigned to this instance + external_irq_trigger_t trigger; ///< Trigger setting. + external_irq_pclk_div_t pclk_div; ///< Digital filter clock divisor setting. + bool filter_enable; ///< Digital filter enable/disable setting. + + /** Callback provided external input trigger occurs. */ + void (* p_callback)(external_irq_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< External IRQ hardware dependent configuration. +} external_irq_cfg_t; + +/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls. + * @par Implemented as + * - icu_instance_ctrl_t + */ +typedef void external_irq_ctrl_t; + +/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */ +typedef struct st_external_irq_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_ICU_ExternalIrqOpen() + * + * @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user. + */ + fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg); + + /** Enable callback when an external trigger condition occurs. + * @par Implemented as + * - @ref R_ICU_ExternalIrqEnable() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl); + + /** Disable callback when external trigger condition occurs. + * @par Implemented as + * - @ref R_ICU_ExternalIrqDisable() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_ICU_ExternalIrqCallbackSet() + * + * @param[in] p_ctrl Pointer to the Extneral IRQ control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void const * const p_context, + external_irq_callback_args_t * const p_callback_memory); + + /** Allow driver to be reconfigured. May reduce power consumption. + * @par Implemented as + * - @ref R_ICU_ExternalIrqClose() + * + * @param[in] p_ctrl Control block set in Open call for this external interrupt. + */ + fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl); +} external_irq_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_external_irq_instance +{ + external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance +} external_irq_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end defgroup EXTERNAL_IRQ_API) + **********************************************************************************************************************/ + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_flash_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_flash_api.h new file mode 100644 index 00000000..4c9c7236 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_flash_api.h @@ -0,0 +1,366 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup FLASH_API Flash Interface + * @brief Interface for the Flash Memory. + * + * @section FLASH_API_SUMMARY Summary + * + * The Flash interface provides the ability to read, write, erase, and blank check the code flash and data flash + * regions. + * + * The Flash interface is implemented by: + * - @ref FLASH_LP + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_FLASH_API_H +#define R_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** Result type for certain operations */ +typedef enum e_flash_result +{ + FLASH_RESULT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_NOT_BLANK, ///< Return status for Blank Check Function + FLASH_RESULT_BGO_ACTIVE ///< Flash is configured for BGO mode. Result is returned in callback. +} flash_result_t; + +/** Parameter for specifying the startup area swap being requested by startupAreaSelect() */ +typedef enum e_flash_startup_area_swap +{ + FLASH_STARTUP_AREA_BTFLG = 0, ///< Startup area will be set based on the value of the BTFLG + FLASH_STARTUP_AREA_BLOCK0 = 0x2, ///< Startup area will be set to Block 0 + FLASH_STARTUP_AREA_BLOCK1 = 0x3, ///< Startup area will be set to Block 1 +} flash_startup_area_swap_t; + +/** Event types returned by the ISR callback when used in Data Flash BGO mode */ +typedef enum e_flash_event +{ + FLASH_EVENT_ERASE_COMPLETE, ///< Erase operation successfully completed + FLASH_EVENT_WRITE_COMPLETE, ///< Write operation successfully completed + FLASH_EVENT_BLANK, ///< Blank check operation successfully completed. Specified area is blank + FLASH_EVENT_NOT_BLANK, ///< Blank check operation successfully completed. Specified area is NOT blank + FLASH_EVENT_ERR_DF_ACCESS, ///< Data Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CF_ACCESS, ///< Code Flash operation failed. Can occur when writing an unerased section. + FLASH_EVENT_ERR_CMD_LOCKED, ///< Operation failed, FCU is in Locked state (often result of an illegal command) + FLASH_EVENT_ERR_FAILURE, ///< Erase or Program Operation failed + FLASH_EVENT_ERR_ONE_BIT ///< A 1-bit error has been corrected when reading the flash memory area by the sequencer. +} flash_event_t; + +/** ID Code Modes for writing to ID code registers */ +typedef enum e_flash_id_code_mode +{ + FLASH_ID_CODE_MODE_UNLOCKED = 0, ///< ID code is ignored + FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT = 0xC000U, ///< ID code is checked. All erase is available. + FLASH_ID_CODE_MODE_LOCKED = 0x8000U ///< ID code is checked. +} flash_id_code_mode_t; + +/** Flash status */ +typedef enum e_flash_status +{ + FLASH_STATUS_IDLE, ///< The flash is idle. + FLASH_STATUS_BUSY ///< The flash is currently processing a command. +} flash_status_t; + +/** Flash block details stored in factory flash. */ +typedef struct st_flash_block_info +{ + uint32_t block_section_st_addr; ///< Starting address for this block section (blocks of this size) + uint32_t block_section_end_addr; ///< Ending address for this block section (blocks of this size) + uint32_t block_size; ///< Flash erase block size + uint32_t block_size_write; ///< Flash write block size +} flash_block_info_t; + +/** Flash block details */ +typedef struct st_flash_regions +{ + uint32_t num_regions; ///< Length of block info array + flash_block_info_t const * p_block_array; ///< Block info array base address +} flash_regions_t; + +/** Information about the flash blocks */ +typedef struct st_flash_info +{ + flash_regions_t code_flash; ///< Information about the code flash regions + flash_regions_t data_flash; ///< Information about the code flash regions +} flash_info_t; + +/** Flash control block. Allocate an instance specific control block to pass into the flash API calls. + * @par Implemented as + * - flash_lp_instance_ctrl_t + * - flash_hp_instance_ctrl_t + */ +typedef void flash_ctrl_t; + +/** Callback function parameter data */ +typedef struct st_flash_user_cb_data +{ + flash_event_t event; ///< Event can be used to identify what caused the callback (flash ready or error). + void const * p_context; ///< Placeholder for user data. Set in @ref flash_api_t::open function in::flash_cfg_t. +} flash_callback_args_t; + +/** FLASH Configuration */ +typedef struct st_flash_cfg +{ + bool data_flash_bgo; ///< True if BGO (Background Operation) is enabled for Data Flash. + + /* Configuration for FLASH Event processing */ + void (* p_callback)(flash_callback_args_t * p_args); ///< Callback provided when a Flash interrupt ISR occurs. + + /* Pointer to FLASH peripheral specific configuration */ + void const * p_extend; ///< FLASH hardware dependent configuration + void const * p_context; ///< Placeholder for user data. Passed to user callback in @ref flash_callback_args_t. + uint8_t ipl; ///< Flash ready interrupt priority + IRQn_Type irq; ///< Flash ready interrupt number + uint8_t err_ipl; ///< Flash error interrupt priority (unused in r_flash_lp) + IRQn_Type err_irq; ///< Flash error interrupt number (unused in r_flash_lp) +} flash_cfg_t; + +/** Shared Interface definition for FLASH */ +typedef struct st_flash_api +{ + /** Open FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Open() + * - @ref R_FLASH_HP_Open() + * + * @param[out] p_ctrl Pointer to FLASH device control. Must be declared by user. Value set here. + * @param[in] flash_cfg_t Pointer to FLASH configuration structure. All elements of this structure + * must be set by the user. + */ + fsp_err_t (* open)(flash_ctrl_t * const p_ctrl, flash_cfg_t const * const p_cfg); + + /** Write FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Write() + * - @ref R_FLASH_HP_Write() + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] src_address Address of the buffer containing the data to write to Flash. + * @param[in] flash_address Code Flash or Data Flash address to write. The address must be on a + * programming line boundary. + * @param[in] num_bytes The number of bytes to write. This number must be a multiple + * of the programming size. For Code Flash this is FLASH_MIN_PGM_SIZE_CF. + * For Data Flash this is FLASH_MIN_PGM_SIZE_DF. + * @warning Specifying a number that is not a multiple of the programming size + * will result in SF_FLASH_ERR_BYTES being returned and no data written. + */ + fsp_err_t (* write)(flash_ctrl_t * const p_ctrl, uint32_t const src_address, uint32_t const flash_address, + uint32_t const num_bytes); + + /** Erase FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Erase() + * - @ref R_FLASH_HP_Erase() + * + * @param[in] p_ctrl Control for the FLASH device. + * @param[in] address The block containing this address is the first block erased. + * @param[in] num_blocks Specifies the number of blocks to be erased, the starting block determined + * by the block_erase_address. + */ + fsp_err_t (* erase)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_blocks); + + /** Blank check FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_BlankCheck() + * - @ref R_FLASH_HP_BlankCheck() + * + * @param[in] p_ctrl Control for the FLASH device context. + * @param[in] address The starting address of the Flash area to blank check. + * @param[in] num_bytes Specifies the number of bytes that need to be checked. + * See the specific handler for details. + * @param[out] p_blank_check_result Pointer that will be populated by the API with the results of the blank check + * operation in non-BGO (blocking) mode. In this case the blank check operation + * completes here and the result is returned. In Data Flash BGO mode the blank + * check operation is only started here and the result obtained later when the + * supplied callback routine is called. In this case FLASH_RESULT_BGO_ACTIVE will + * be returned in p_blank_check_result. + */ + fsp_err_t (* blankCheck)(flash_ctrl_t * const p_ctrl, uint32_t const address, uint32_t const num_bytes, + flash_result_t * const p_blank_check_result); + + /** Close FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_InfoGet() + * - @ref R_FLASH_HP_InfoGet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_info Pointer to FLASH info structure. + */ + fsp_err_t (* infoGet)(flash_ctrl_t * const p_ctrl, flash_info_t * const p_info); + + /** Close FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Close() + * - @ref R_FLASH_HP_Close() + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* close)(flash_ctrl_t * const p_ctrl); + + /** Get Status for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_StatusGet() + * - @ref R_FLASH_HP_StatusGet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[out] p_ctrl Pointer to the current flash status. + */ + fsp_err_t (* statusGet)(flash_ctrl_t * const p_ctrl, flash_status_t * const p_status); + + /** Set Access Window for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_AccessWindowSet() + * - @ref R_FLASH_HP_AccessWindowSet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. This address will not be + * within the access window. + */ + fsp_err_t (* accessWindowSet)(flash_ctrl_t * const p_ctrl, uint32_t const start_addr, uint32_t const end_addr); + + /** Clear any existing Code Flash access window for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_AccessWindowClear() + * - @ref R_FLASH_HP_AccessWindowClear() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] start_addr Determines the Starting block for the Code Flash access window. + * @param[in] end_addr Determines the Ending block for the Code Flash access window. + */ + fsp_err_t (* accessWindowClear)(flash_ctrl_t * const p_ctrl); + + /** Set ID Code for FLASH device. Setting the ID code can restrict access to the device. The ID code will be + * required to connect to the device. Bits 126 and 127 are set based on the mode. + * + * For example, uint8_t id_bytes[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + * 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0x00}; + * with mode FLASH_ID_CODE_MODE_LOCKED_WITH_ALL_ERASE_SUPPORT + * will result in an ID code of 00112233445566778899aabbccddeec0 + * + * With mode FLASH_ID_CODE_MODE_LOCKED, it + * will result in an ID code of 00112233445566778899aabbccddee80 + * + * @par Implemented as + * - @ref R_FLASH_LP_IdCodeSet() + * - @ref R_FLASH_HP_IdCodeSet() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] p_id_bytes Ponter to the ID Code to be written. + * @param[in] mode Mode used for checking the ID code. + */ + fsp_err_t (* idCodeSet)(flash_ctrl_t * const p_ctrl, uint8_t const * const p_id_bytes, flash_id_code_mode_t mode); + + /** Reset function for FLASH device. + * @par Implemented as + * - @ref R_FLASH_LP_Reset() + * - @ref R_FLASH_HP_Reset() + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* reset)(flash_ctrl_t * const p_ctrl); + + /** Update Flash clock frequency (FCLK) and recalculate timeout values + * @par Implemented as + * - @ref R_FLASH_LP_UpdateFlashClockFreq() + * - @ref R_FLASH_HP_UpdateFlashClockFreq() + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* updateFlashClockFreq)(flash_ctrl_t * const p_ctrl); + + /** Select which block - Default (Block 0) or Alternate (Block 1) is used as the start-up area block. + * @par Implemented as + * - @ref R_FLASH_LP_StartUpAreaSelect() + * - @ref R_FLASH_HP_StartUpAreaSelect() + * + * @param[in] p_ctrl Pointer to FLASH device control. + * @param[in] swap_type FLASH_STARTUP_AREA_BLOCK0, FLASH_STARTUP_AREA_BLOCK1 or FLASH_STARTUP_AREA_BTFLG. + * @param[in] is_temporary True or false. See table below. + * + * | swap_type | is_temporary | Operation | + * |-----------------------|-----------------|-------------| + * | FLASH_STARTUP_AREA_BLOCK0 | false | On next reset Startup area will be Block 0. | + * | FLASH_STARTUP_AREA_BLOCK1 | true | Startup area is immediately, but temporarily switched to Block 1. | + * | FLASH_STARTUP_AREA_BTFLG | true | Startup area is immediately, but temporarily switched to the Block determined by the Configuration BTFLG. | + * + */ + fsp_err_t (* startupAreaSelect)(flash_ctrl_t * const p_ctrl, flash_startup_area_swap_t swap_type, + bool is_temporary); + + /** Swap the bank used as the startup area. Only valid in dual bank mode. + * @par Implemented as + * - @ref R_FLASH_HP_BankSwap() + * + * @param[in] p_ctrl Pointer to FLASH device control. + */ + fsp_err_t (* bankSwap)(flash_ctrl_t * const p_ctrl); + + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_FLASH_HP_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref flash_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(flash_ctrl_t * const p_api_ctrl, void (* p_callback)(flash_callback_args_t *), + void const * const p_context, flash_callback_args_t * const p_callback_memory); +} flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_flash_instance +{ + flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} flash_instance_t; + +/******************************************************************************************************************//** + * @} (end defgroup FLASH_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_master_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_master_api.h new file mode 100644 index 00000000..d9f60b36 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_master_api.h @@ -0,0 +1,256 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_I2C_MASTER_API_H +#define R_I2C_MASTER_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup I2C_MASTER_API I2C Master Interface + * @brief Interface for I2C master communication. + * + * @section I2C_MASTER_API_SUMMARY Summary + * The I2C master interface provides a common API for I2C HAL drivers. The I2C master interface supports: + * - Interrupt driven transmit/receive processing + * - Callback function support which can return an event code + * + * Implemented by: + * - @ref IIC_MASTER + * - @ref SCI_I2C + * - @ref IIC_B_MASTER + * - @ref SCI_B_I2C + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Communication speed options */ +typedef enum e_i2c_master_rate +{ + I2C_MASTER_RATE_STANDARD = 100000, ///< 100 kHz + I2C_MASTER_RATE_FAST = 400000, ///< 400 kHz + I2C_MASTER_RATE_FASTPLUS = 1000000 ///< 1 MHz +} i2c_master_rate_t; + +/** Addressing mode options */ +typedef enum e_i2c_master_addr_mode +{ + I2C_MASTER_ADDR_MODE_7BIT = 1, ///< Use 7-bit addressing mode + I2C_MASTER_ADDR_MODE_10BIT = 2, ///< Use 10-bit addressing mode +} i2c_master_addr_mode_t; + +/** Callback events */ +typedef enum e_i2c_master_event +{ + I2C_MASTER_EVENT_ABORTED = 1, ///< A transfer was aborted + I2C_MASTER_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully + I2C_MASTER_EVENT_TX_COMPLETE = 3 ///< A transmit operation was completed successfully +} i2c_master_event_t; + +/** I2C callback parameter definition */ +typedef struct st_i2c_master_callback_args +{ + void const * p_context; ///< Pointer to user-provided context + i2c_master_event_t event; ///< Event code +} i2c_master_callback_args_t; + +/** I2C status indicators */ +typedef struct st_i2c_master_status +{ + bool open; ///< True if driver is open +} i2c_master_status_t; + +/** I2C configuration block */ +typedef struct st_i2c_master_cfg +{ + /** Generic configuration */ + uint8_t channel; ///< Identifier recognizable by implementation + i2c_master_rate_t rate; ///< Device's maximum clock rate from enum i2c_rate_t + uint32_t slave; ///< The address of the slave device + i2c_master_addr_mode_t addr_mode; ///< Indicates how slave fields should be interpreted + uint8_t ipl; ///< Interrupt priority level. Same for RXI, TXI, TEI and ERI. + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type tei_irq; ///< Transmit end IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + + /** DTC support */ + transfer_instance_t const * p_transfer_tx; ///< DTC instance for I2C transmit.Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< DTC instance for I2C receive. Set to NULL if unused. + + /** Parameters to control software behavior */ + void (* p_callback)(i2c_master_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< Pointer to the user-provided context + + /** Implementation-specific configuration */ + void const * p_extend; ///< Any configuration data needed by the hardware +} i2c_master_cfg_t; + +/** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. + * @par Implemented as + * - iic_master_instance_ctrl_t + */ +typedef void i2c_master_ctrl_t; + +/** Interface definition for I2C access as master */ +typedef struct st_i2c_master_api +{ + /** Opens the I2C Master driver and initializes the hardware. + * @par Implemented as + * - @ref R_IIC_MASTER_Open() + * - @ref R_SCI_I2C_Open() + * - @ref R_IIC_B_MASTER_Open() + * - @ref R_SCI_B_I2C_Open() + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(i2c_master_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg); + + /** Performs a read operation on an I2C Master device. + * @par Implemented as + * - @ref R_SCI_I2C_Read() + * - @ref R_IIC_MASTER_Read() + * - @ref R_IIC_B_MASTER_Read() + * - @ref R_SCI_B_I2C_Read() + * + * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_dest Pointer to the location to store read data. + * @param[in] bytes Number of bytes to read. + * @param[in] restart Specify if the restart condition should be issued after reading. + */ + fsp_err_t (* read)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes, + bool const restart); + + /** Performs a write operation on an I2C Master device. + * @par Implemented as + * - @ref R_IIC_MASTER_Write() + * - @ref R_SCI_I2C_Write() + * - @ref R_IIC_B_MASTER_Write() + * - @ref R_SCI_B_I2C_Write() + * + * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] p_src Pointer to the location to get write data from. + * @param[in] bytes Number of bytes to write. + * @param[in] restart Specify if the restart condition should be issued after writing. + */ + fsp_err_t (* write)(i2c_master_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes, + bool const restart); + + /** Performs a reset of the peripheral. + * @par Implemented as + * - @ref R_IIC_MASTER_Abort() + * - @ref R_SCI_I2C_Abort() + * - @ref R_IIC_B_MASTER_Abort() + * - @ref R_SCI_B_I2C_Abort() + * + * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + */ + fsp_err_t (* abort)(i2c_master_ctrl_t * const p_ctrl); + + /** Sets address of the slave device without reconfiguring the bus. + * @par Implemented as + * - @ref R_IIC_MASTER_SlaveAddressSet() + * - @ref R_SCI_I2C_SlaveAddressSet() + * - @ref R_IIC_B_MASTER_SlaveAddressSet() + * - @ref R_SCI_B_I2C_SlaveAddressSet() + * + * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + * @param[in] slave_address Address of the slave device. + * @param[in] address_mode Addressing mode. + */ + fsp_err_t (* slaveAddressSet)(i2c_master_ctrl_t * const p_ctrl, uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_IIC_MASTER_CallbackSet() + * - @ref R_SCI_I2C_CallbackSet() + * - @ref R_IIC_B_MASTER_CallbackSet() + * - @ref R_SCI_B_I2C_CallbackSet() + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_master_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_master_callback_args_t *), + void const * const p_context, i2c_master_callback_args_t * const p_callback_memory); + + /** Gets the status of the configured I2C device. + * @par Implemented as + * - @ref R_IIC_MASTER_StatusGet() + * - @ref R_SCI_I2C_StatusGet() + * - @ref R_IIC_B_MASTER_StatusGet() + * - @ref R_SCI_B_I2C_StatusGet() + * + * @param[in] p_ctrl Pointer to the IIC Master control block. + * @param[out] p_status Pointer to store current status. + */ + fsp_err_t (* statusGet)(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + + /** Closes the driver and releases the I2C Master device. + * @par Implemented as + * - @ref R_IIC_MASTER_Close() + * - @ref R_SCI_I2C_Close() + * - @ref R_IIC_B_MASTER_Close() + * - @ref R_SCI_B_I2C_Close() + * + * @param[in] p_ctrl Pointer to control block set in i2c_api_master_t::open call. + */ + fsp_err_t (* close)(i2c_master_ctrl_t * const p_ctrl); +} i2c_master_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2c_master_instance +{ + i2c_master_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2c_master_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2c_master_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2c_master_instance_t; + +/******************************************************************************************************************//** + * @} (end addtogroup I2C_MASTER_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_slave_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_slave_api.h new file mode 100644 index 00000000..4339c908 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2c_slave_api.h @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_I2C_SLAVE_API_H +#define R_I2C_SLAVE_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup I2C_SLAVE_API I2C Slave Interface + * @brief Interface for I2C slave communication. + * + * @section I2C_SLAVE_API_SUMMARY Summary + * The I2C slave interface provides a common API for I2C HAL drivers. The I2C slave interface supports: + * - Interrupt driven transmit/receive processing + * - Callback function support which returns a event codes + * + * Implemented by: + * - @ref IIC_SLAVE + * - @ref IIC_B_SLAVE + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Communication speed options */ +typedef enum e_i2c_slave_rate +{ + I2C_SLAVE_RATE_STANDARD = 100000, ///< 100 kHz + I2C_SLAVE_RATE_FAST = 400000, ///< 400 kHz + I2C_SLAVE_RATE_FASTPLUS = 1000000 ///< 1 MHz +} i2c_slave_rate_t; + +/** Addressing mode options */ +typedef enum e_i2c_slave_addr_mode +{ + I2C_SLAVE_ADDR_MODE_7BIT = 1, ///< Use 7-bit addressing mode + I2C_SLAVE_ADDR_MODE_10BIT ///< Use 10-bit addressing mode +} i2c_slave_addr_mode_t; + +/** Callback events */ +typedef enum e_i2c_slave_event +{ + I2C_SLAVE_EVENT_ABORTED = 1, ///< A transfer was aborted + I2C_SLAVE_EVENT_RX_COMPLETE = 2, ///< A receive operation was completed successfully + I2C_SLAVE_EVENT_TX_COMPLETE = 3, ///< A transmit operation was completed successfully + I2C_SLAVE_EVENT_RX_REQUEST = 4, ///< A read operation expected from slave. Detected a write from master + I2C_SLAVE_EVENT_TX_REQUEST = 5, ///< A write operation expected from slave. Detected a read from master + I2C_SLAVE_EVENT_RX_MORE_REQUEST = 6, ///< A read operation expected from slave. Master sends out more data than configured to be read in slave. + I2C_SLAVE_EVENT_TX_MORE_REQUEST = 7, ///< A write operation expected from slave. Master requests more data than configured to be written by slave. + I2C_SLAVE_EVENT_GENERAL_CALL = 8, ///< General Call address received from Master. Detected a write from master +} i2c_slave_event_t; + +/** I2C callback parameter definition */ +typedef struct st_i2c_slave_callback_args +{ + void const * p_context; ///< Pointer to user-provided context + uint32_t bytes; ///< Number of received/transmitted bytes in buffer + i2c_slave_event_t event; ///< Event code +} i2c_slave_callback_args_t; + +/** I2C configuration block */ +typedef struct st_i2c_slave_cfg +{ + /** Generic configuration */ + uint8_t channel; ///< Identifier recognizable by implementation + i2c_slave_rate_t rate; ///< Device's maximum clock rate from enum i2c_rate_t + uint16_t slave; ///< The address of the slave device + i2c_slave_addr_mode_t addr_mode; ///< Indicates how slave fields should be interpreted + bool general_call_enable; ///< Allow a General call from master + + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type tei_irq; ///< Transmit end IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t ipl; ///< Interrupt priority level for RXI, TXI and TER interrupts + uint8_t eri_ipl; ///< Interrupt priority level for ERI interrupt + bool clock_stretching_enable; ///< Low Hold SCL during reception for the period between the 9th and the 1st clock cycle + + /** Parameters to control software behavior */ + void (* p_callback)(i2c_slave_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< Pointer to the user-provided context + + /** Implementation-specific configuration */ + void const * p_extend; ///< Any configuration data needed by the hardware +} i2c_slave_cfg_t; + +/** I2C control block. Allocate an instance specific control block to pass into the I2C API calls. + * @par Implemented as + * - iic_slave_instance_ctrl_t + */ +typedef void i2c_slave_ctrl_t; + +/** Interface definition for I2C access as slave */ +typedef struct st_i2c_slave_api +{ + /** Opens the I2C Slave driver and initializes the hardware. + * @par Implemented as + * - @ref R_IIC_SLAVE_Open() + * - @ref R_IIC_B_SLAVE_Open() + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements are set here. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(i2c_slave_ctrl_t * const p_ctrl, i2c_slave_cfg_t const * const p_cfg); + + /** Performs a read operation on an I2C Slave device. + * @par Implemented as + * - @ref R_IIC_SLAVE_Read() + * - @ref R_IIC_B_SLAVE_Read() + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + * @param[in] p_dest Pointer to the location to store read data. + * @param[in] bytes Number of bytes to read. + */ + fsp_err_t (* read)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Performs a write operation on an I2C Slave device. + * @par Implemented as + * - @ref R_IIC_SLAVE_Write() + * - @ref R_IIC_B_SLAVE_Write() + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + * @param[in] p_src Pointer to the location to get write data from. + * @param[in] bytes Number of bytes to write. + */ + fsp_err_t (* write)(i2c_slave_ctrl_t * const p_ctrl, uint8_t * const p_src, uint32_t const bytes); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_IIC_SLAVE_CallbackSet() + * - @ref R_IIC_B_SLAVE_CallbackSet() + * + * @param[in] p_ctrl Pointer to the IIC Slave control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2c_slave_ctrl_t * const p_api_ctrl, void (* p_callback)(i2c_slave_callback_args_t *), + void const * const p_context, i2c_slave_callback_args_t * const p_callback_memory); + + /** Closes the driver and releases the I2C Slave device. + * @par Implemented as + * - @ref R_IIC_SLAVE_Close() + * - @ref R_IIC_B_SLAVE_Close() + * + * @param[in] p_ctrl Pointer to control block set in @ref i2c_slave_api_t::open call. + */ + fsp_err_t (* close)(i2c_slave_ctrl_t * const p_ctrl); +} i2c_slave_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2c_slave_instance +{ + i2c_slave_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2c_slave_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2c_slave_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2c_slave_instance_t; + +/******************************************************************************************************************//** + * @} (end addtogroup I2C_SLAVE_API) + *********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2s_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2s_api.h new file mode 100644 index 00000000..c19e9956 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_i2s_api.h @@ -0,0 +1,285 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup I2S_API I2S Interface + * @brief Interface for I2S audio communication. + * + * @section I2S_API_SUMMARY Summary + * @brief The I2S (Inter-IC Sound) interface provides APIs and definitions for I2S audio communication. + * + * @section I2S_API_INSTANCES Known Implementations + * @ref SSI + * @{ + **********************************************************************************************************************/ + +#ifndef R_I2S_API_H +#define R_I2S_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_timer_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Audio PCM width */ +typedef enum e_i2s_pcm_width +{ + I2S_PCM_WIDTH_8_BITS = 0, ///< Using 8-bit PCM + I2S_PCM_WIDTH_16_BITS = 1, ///< Using 16-bit PCM + I2S_PCM_WIDTH_18_BITS = 2, ///< Using 18-bit PCM + I2S_PCM_WIDTH_20_BITS = 3, ///< Using 20-bit PCM + I2S_PCM_WIDTH_22_BITS = 4, ///< Using 22-bit PCM + I2S_PCM_WIDTH_24_BITS = 5, ///< Using 24-bit PCM + I2S_PCM_WIDTH_32_BITS = 6, ///< Using 24-bit PCM +} i2s_pcm_width_t; + +/** Audio system word length. */ +typedef enum e_i2s_word_length +{ + I2S_WORD_LENGTH_8_BITS = 0, ///< Using 8-bit system word length + I2S_WORD_LENGTH_16_BITS = 1, ///< Using 16-bit system word length + I2S_WORD_LENGTH_24_BITS = 2, ///< Using 24-bit system word length + I2S_WORD_LENGTH_32_BITS = 3, ///< Using 32-bit system word length + I2S_WORD_LENGTH_48_BITS = 4, ///< Using 48-bit system word length + I2S_WORD_LENGTH_64_BITS = 5, ///< Using 64-bit system word length + I2S_WORD_LENGTH_128_BITS = 6, ///< Using 128-bit system word length + I2S_WORD_LENGTH_256_BITS = 7, ///< Using 256-bit system word length +} i2s_word_length_t; + +/** Events that can trigger a callback function */ +typedef enum e_i2s_event +{ + I2S_EVENT_IDLE, ///< Communication is idle + I2S_EVENT_TX_EMPTY, ///< Transmit buffer is below FIFO trigger level + I2S_EVENT_RX_FULL, ///< Receive buffer is above FIFO trigger level +} i2s_event_t; + +/** I2S communication mode */ +typedef enum e_i2s_mode +{ + I2S_MODE_SLAVE = 0, ///< Slave mode + I2S_MODE_MASTER = 1, ///< Master mode +} i2s_mode_t; + +/** Mute audio samples. */ +typedef enum e_i2s_mute +{ + I2S_MUTE_OFF = 0, ///< Disable mute + I2S_MUTE_ON = 1, ///< Enable mute +} i2s_mute_t; + +/** Whether to continue WS (word select line) transmission during idle state. */ +typedef enum e_i2s_ws_continue +{ + I2S_WS_CONTINUE_ON = 0, ///< Enable WS continue mode + I2S_WS_CONTINUE_OFF = 1, ///< Disable WS continue mode +} i2s_ws_continue_t; + +/** Possible status values returned by @ref i2s_api_t::statusGet. */ +typedef enum e_i2s_state +{ + I2S_STATE_IN_USE, ///< I2S is in use + I2S_STATE_STOPPED ///< I2S is stopped +} i2s_state_t; + +/** Callback function parameter data */ +typedef struct st_i2s_callback_args +{ + /** Placeholder for user data. Set in @ref i2s_api_t::open function in @ref i2s_cfg_t. */ + void const * p_context; + i2s_event_t event; ///< The event can be used to identify what caused the callback (overflow or error). +} i2s_callback_args_t; + +/** I2S control block. Allocate an instance specific control block to pass into the I2S API calls. + * @par Implemented as + * - ssi_instance_ctrl_t + */ +typedef void i2s_ctrl_t; + +/** I2S status. */ +typedef struct st_i2s_status +{ + i2s_state_t state; ///< Current I2S state +} i2s_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_i2s_cfg +{ + /** Select a channel corresponding to the channel number of the hardware. */ + uint32_t channel; + i2s_pcm_width_t pcm_width; ///< Audio PCM data width + i2s_word_length_t word_length; ///< Audio word length, bits must be >= i2s_cfg_t::pcm_width bits + i2s_ws_continue_t ws_continue; ///< Whether to continue WS transmission during idle state. + i2s_mode_t operating_mode; ///< Master or slave mode + + /** To use DTC during write, link a DTC instance here. Set to NULL if unused. */ + transfer_instance_t const * p_transfer_tx; + + /** To use DTC during read, link a DTC instance here. Set to NULL if unused. */ + transfer_instance_t const * p_transfer_rx; + + /** Callback provided when an I2S ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(i2s_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref i2s_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. + uint8_t rxi_ipl; ///< Receive interrupt priority + uint8_t txi_ipl; ///< Transmit interrupt priority + uint8_t idle_err_ipl; ///< Idle/Error interrupt priority + IRQn_Type txi_irq; ///< Transmit IRQ number + IRQn_Type rxi_irq; ///< Receive IRQ number + IRQn_Type int_irq; ///< Idle/Error IRQ number +} i2s_cfg_t; + +/** I2S functions implemented at the HAL layer will follow this API. */ +typedef struct st_i2s_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_SSI_Open() + * + * @pre Peripheral clocks and any required output pins should be configured prior to calling this function. + * @note To reconfigure after calling this function, call @ref i2s_api_t::close first. + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg); + + /** Stop communication. Communication is stopped when callback is called with I2S_EVENT_IDLE. + * + * @par Implemented as + * - @ref R_SSI_Stop() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + */ + fsp_err_t (* stop)(i2s_ctrl_t * const p_ctrl); + + /** Enable or disable mute. + * @par Implemented as + * - @ref R_SSI_Mute() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] mute_enable Whether to enable or disable mute. + */ + fsp_err_t (* mute)(i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable); + + /** Write I2S data. All transmit data is queued when callback is called with I2S_EVENT_TX_EMPTY. + * Transmission is complete when callback is called with I2S_EVENT_IDLE. + * @par Implemented as + * - @ref R_SSI_Write() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffer. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, padding 0s will be added to transmission to make it a multiple of 8. + */ + fsp_err_t (* write)(i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes); + + /** Read I2S data. Reception is complete when callback is called with I2S_EVENT_RX_EMPTY. + * @par Implemented as + * - @ref R_SSI_Read() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffer. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, receive will stop at the multiple of 8 below requested bytes. + */ + fsp_err_t (* read)(i2s_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); + + /** Simultaneously write and read I2S data. Transmission and reception are complete when + * callback is called with I2S_EVENT_IDLE. + * @par Implemented as + * - @ref R_SSI_WriteRead() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[in] p_src Buffer of PCM samples. Must be 4 byte aligned. + * @param[in] p_dest Buffer to store PCM samples. Must be 4 byte aligned. + * @param[in] bytes Number of bytes in the buffers. Recommended requesting a multiple of 8 bytes. If not + * a multiple of 8, padding 0s will be added to transmission to make it a multiple of 8, + * and receive will stop at the multiple of 8 below requested bytes. + */ + fsp_err_t (* writeRead)(i2s_ctrl_t * const p_ctrl, void const * const p_src, void * const p_dest, + uint32_t const bytes); + + /** Get current status and store it in provided pointer p_status. + * @par Implemented as + * - @ref R_SSI_StatusGet() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + * @param[out] p_status Current status of the driver. + */ + fsp_err_t (* statusGet)(i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status); + + /** Allows driver to be reconfigured and may reduce power consumption. + * @par Implemented as + * - @ref R_SSI_Close() + * + * @param[in] p_ctrl Control block set in @ref i2s_api_t::open call for this instance. + */ + fsp_err_t (* close)(i2s_ctrl_t * const p_ctrl); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SSI_CallbackSet() + * + * @param[in] p_ctrl Pointer to the I2S control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(i2s_ctrl_t * const p_api_ctrl, void (* p_callback)(i2s_callback_args_t *), + void const * const p_context, i2s_callback_args_t * const p_callback_memory); +} i2s_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_i2s_instance +{ + i2s_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + i2s_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + i2s_api_t const * p_api; ///< Pointer to the API structure for this instance +} i2s_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup I2S_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_ioport_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_ioport_api.h new file mode 100644 index 00000000..ae2a2d59 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,359 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * IOPORT Interface description: @ref IOPORT + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define IOPORT_PRV_PFS_PSEL_OFFSET (24) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size on this device + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_peripheral +{ + /** Pin will functions as an IO pin */ + IOPORT_PERIPHERAL_IO = 0x00, + + /** Pin will function as a DEBUG pin */ + IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral pin */ + IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a SPI peripheral pin */ + IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a IIC peripheral pin */ + IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a KEY peripheral pin */ + IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a clock/comparator/RTC peripheral pin */ + IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC/ADC peripheral pin */ + IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a BUS peripheral pin */ + IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CTSU peripheral pin */ + IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CMPHS peripheral pin */ + IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a segment LCD peripheral pin */ + IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI peripheral DEn pin */ + IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a DALI peripheral pin */ + IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SCI DEn peripheral pin */ + IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAN peripheral pin */ + IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a QSPI peripheral pin */ + IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SSI peripheral pin */ + IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB full speed peripheral pin */ + IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a USB high speed peripheral pin */ + IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an SD/MMC peripheral pin */ + IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet MMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a GPT peripheral pin */ + IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an Ethernet RMMI peripheral pin */ + IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PDC peripheral pin */ + IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a graphics LCD peripheral pin */ + IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CAC peripheral pin */ + IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a debug trace peripheral pin */ + IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a OSPI peripheral pin */ + IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a CEC peripheral pin */ + IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as a PGAOUT peripheral pin */ + IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET), +} ioport_peripheral_t; + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high + IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up + IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput + IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed + IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port + IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin +} ioport_cfg_options_t; + +/* PFS writing enable/disable. */ +typedef enum e_ioport_pwpr +{ + IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access + IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access +} ioport_pwpr_t; + +/** Pin identifier and pin PFS pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + * @par Implemented as + * - ioport_instance_ctrl_t + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * @par Implemented as + * - @ref R_IOPORT_Open() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * @par Implemented as + * - @ref R_IOPORT_Close() + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * @par Implemented as + * - @ref R_IOPORT_PinsCfg() + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * @par Implemented as + * - @ref R_IOPORT_PinCfg() + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * @par Implemented as + * - @ref R_IOPORT_PinEventInputRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * @par Implemented as + * - @ref R_IOPORT_PinEventOutputWrite() + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * @par Implemented as + * - @ref R_IOPORT_PinRead() + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * @par Implemented as + * - @ref R_IOPORT_PinWrite() + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortDirectionSet() + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input). + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventInputRead() + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * @par Implemented as + * - @ref R_IOPORT_PortEventOutputWrite() + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * @par Implemented as + * - @ref R_IOPORT_PortRead() + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * @par Implemented as + * - @ref R_IOPORT_PortWrite() + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_lpm_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_lpm_api.h new file mode 100644 index 00000000..bd6796a8 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_lpm_api.h @@ -0,0 +1,437 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup LPM_API Low Power Modes Interface + * @brief Interface for accessing low power modes. + * + * @section LPM_API_SUMMARY Summary + * This section defines the API for the LPM (Low Power Mode) Driver. + * The LPM Driver provides functions for controlling power consumption by configuring + * and transitioning to a low power mode. + * The LPM driver supports configuration of MCU low power modes using the LPM hardware + * peripheral. The LPM driver supports low power modes deep standby, standby, sleep, and snooze. + * + * @note Not all low power modes are available on all MCUs. + * + * The LPM interface is implemented by: + * - @ref LPM + * + * @{ + **********************************************************************************************************************/ +#ifndef R_LPM_API_H +#define R_LPM_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Low power modes */ +typedef enum e_lpm_mode +{ + LPM_MODE_SLEEP, ///< Sleep mode + LPM_MODE_STANDBY, ///< Software Standby mode + LPM_MODE_STANDBY_SNOOZE, ///< Software Standby mode with Snooze mode enabled + LPM_MODE_DEEP, ///< Deep Software Standby mode +} lpm_mode_t; + +/** Snooze request sources */ +typedef enum e_lpm_snooze_request +{ + LPM_SNOOZE_REQUEST_RXD0_FALLING = 0x00000000ULL, ///< Enable RXD0 falling edge snooze request + LPM_SNOOZE_REQUEST_IRQ0 = 0x00000001ULL, ///< Enable IRQ0 pin snooze request + LPM_SNOOZE_REQUEST_IRQ1 = 0x00000002ULL, ///< Enable IRQ1 pin snooze request + LPM_SNOOZE_REQUEST_IRQ2 = 0x00000004ULL, ///< Enable IRQ2 pin snooze request + LPM_SNOOZE_REQUEST_IRQ3 = 0x00000008ULL, ///< Enable IRQ3 pin snooze request + LPM_SNOOZE_REQUEST_IRQ4 = 0x00000010ULL, ///< Enable IRQ4 pin snooze request + LPM_SNOOZE_REQUEST_IRQ5 = 0x00000020ULL, ///< Enable IRQ5 pin snooze request + LPM_SNOOZE_REQUEST_IRQ6 = 0x00000040ULL, ///< Enable IRQ6 pin snooze request + LPM_SNOOZE_REQUEST_IRQ7 = 0x00000080ULL, ///< Enable IRQ7 pin snooze request + LPM_SNOOZE_REQUEST_IRQ8 = 0x00000100ULL, ///< Enable IRQ8 pin snooze request + LPM_SNOOZE_REQUEST_IRQ9 = 0x00000200ULL, ///< Enable IRQ9 pin snooze request + LPM_SNOOZE_REQUEST_IRQ10 = 0x00000400ULL, ///< Enable IRQ10 pin snooze request + LPM_SNOOZE_REQUEST_IRQ11 = 0x00000800ULL, ///< Enable IRQ11 pin snooze request + LPM_SNOOZE_REQUEST_IRQ12 = 0x00001000ULL, ///< Enable IRQ12 pin snooze request + LPM_SNOOZE_REQUEST_IRQ13 = 0x00002000ULL, ///< Enable IRQ13 pin snooze request + LPM_SNOOZE_REQUEST_IRQ14 = 0x00004000ULL, ///< Enable IRQ14 pin snooze request + LPM_SNOOZE_REQUEST_IRQ15 = 0x00008000ULL, ///< Enable IRQ15 pin snooze request + LPM_SNOOZE_REQUEST_KEY = 0x00020000ULL, ///< Enable KR snooze request + LPM_SNOOZE_REQUEST_ACMPHS0 = 0x00400000ULL, ///< Enable High-speed analog comparator 0 snooze request + LPM_SNOOZE_REQUEST_RTC_ALARM = 0x01000000ULL, ///< Enable RTC alarm snooze request + LPM_SNOOZE_REQUEST_RTC_PERIOD = 0x02000000ULL, ///< Enable RTC period snooze request + LPM_SNOOZE_REQUEST_AGT1_UNDERFLOW = 0x10000000ULL, ///< Enable AGT1 underflow snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_A = 0x20000000ULL, ///< Enable AGT1 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT1_COMPARE_B = 0x40000000ULL, ///< Enable AGT1 compare match B snooze request + LPM_SNOOZE_REQUEST_AGT3_UNDERFLOW = 0x100000000ULL, ///< Enable AGT3 underflow snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_A = 0x200000000ULL, ///< Enable AGT3 compare match A snooze request + LPM_SNOOZE_REQUEST_AGT3_COMPARE_B = 0x400000000ULL, ///< Enable AGT3 compare match B snooze request +} lpm_snooze_request_t; + +/** Snooze end control */ +typedef enum e_lpm_snooze_end +{ + LPM_SNOOZE_END_STANDBY_WAKE_SOURCES = 0x00U, ///< Transition from Snooze to Normal mode directly + LPM_SNOOZE_END_AGT1_UNDERFLOW = 0x01U, ///< AGT1 underflow + LPM_SNOOZE_END_DTC_TRANS_COMPLETE = 0x02U, ///< Last DTC transmission completion + LPM_SNOOZE_END_DTC_TRANS_COMPLETE_NEGATED = 0x04U, ///< Not Last DTC transmission completion + LPM_SNOOZE_END_ADC0_COMPARE_MATCH = 0x08U, ///< ADC Channel 0 compare match + LPM_SNOOZE_END_ADC0_COMPARE_MISMATCH = 0x10U, ///< ADC Channel 0 compare mismatch + LPM_SNOOZE_END_ADC1_COMPARE_MATCH = 0x20U, ///< ADC 1 compare match + LPM_SNOOZE_END_ADC1_COMPARE_MISMATCH = 0x40U, ///< ADC 1 compare mismatch + LPM_SNOOZE_END_SCI0_ADDRESS_MATCH = 0x80U, ///< SCI0 address mismatch + LPM_SNOOZE_END_AGT3_UNDERFLOW = 0x100U, ///< AGT3 underflow +} lpm_snooze_end_t; + +typedef uint16_t lpm_snooze_end_bits_t; + +/** Snooze cancel control */ +typedef enum e_lpm_snooze_cancel +{ + LPM_SNOOZE_CANCEL_SOURCE_NONE = ELC_EVENT_NONE, ///< No snooze cancel source + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPM = ELC_EVENT_ADC0_COMPARE_MATCH, ///< ADC Channel 0 window compare match +#if (2U != BSP_FEATURE_ELC_VERSION) + LPM_SNOOZE_CANCEL_SOURCE_ADC0_WCMPUM = ELC_EVENT_ADC0_COMPARE_MISMATCH, ///< ADC Channel 0 window compare mismatch +#endif +#if BSP_FEATURE_ADC_VALID_UNIT_MASK & (1U << 1) // If ADC has unit 1 + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPM = ELC_EVENT_ADC1_COMPARE_MATCH, ///< ADC Channel 1 window compare match + #if (2U != BSP_FEATURE_ELC_VERSION) + LPM_SNOOZE_CANCEL_SOURCE_ADC1_WCMPUM = ELC_EVENT_ADC1_COMPARE_MISMATCH, ///< ADC Channel 1 window compare mismatch + #endif +#endif +#if (BSP_FEATURE_SCI_CHANNELS & (1U << 0)) && (2U != BSP_FEATURE_ELC_VERSION) // If SCI has channel 0 + LPM_SNOOZE_CANCEL_SOURCE_SCI0_AM = ELC_EVENT_SCI0_AM, ///< SCI0 address match event + LPM_SNOOZE_CANCEL_SOURCE_SCI0_RXI_OR_ERI = ELC_EVENT_SCI0_RXI_OR_ERI, ///< SCI0 receive error +#endif + LPM_SNOOZE_CANCEL_SOURCE_DTC_COMPLETE = ELC_EVENT_DTC_COMPLETE, ///< DTC transfer completion + LPM_SNOOZE_CANCEL_SOURCE_DOC_DOPCI = ELC_EVENT_DOC_INT, ///< Data operation circuit interrupt +#if BSP_FEATURE_CTSU_VERSION + LPM_SNOOZE_CANCEL_SOURCE_CTSU_CTSUFN = ELC_EVENT_CTSU_END, ///< CTSU measurement end interrupt +#endif +} lpm_snooze_cancel_t; + +/** DTC Enable in Snooze Mode */ +typedef enum e_lpm_snooze_dtc +{ + LPM_SNOOZE_DTC_DISABLE = 0U, ///< Disable DTC operation + LPM_SNOOZE_DTC_ENABLE = 1U, ///< Enable DTC operation +} lpm_snooze_dtc_t; + +/** Wake from standby mode sources, does not apply to sleep or deep standby modes */ +typedef enum e_lpm_standby_wake_source +{ + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 compare match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 compare match B interrupt +} lpm_standby_wake_source_t; + +typedef uint64_t lpm_standby_wake_source_bits_t; + +/** I/O port state after Deep Software Standby mode */ +typedef enum e_lpm_io_port +{ + /** + * When the Deep Software Standby mode is canceled, the I/O ports are in the reset state + */ + LPM_IO_PORT_RESET = 0U, + + /** + * When the Deep Software Standby mode is canceled, the I/O ports are in the same state as + * in the Deep Software Standby mode + */ + LPM_IO_PORT_NO_CHANGE = 1U, +} lpm_io_port_t; + +/** Power supply control */ +typedef enum e_lpm_power_supply +{ + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is supplied in deep software standby mode + */ + LPM_POWER_SUPPLY_DEEPCUT0 = 0U, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is not supplied in deep software standby mode + */ + LPM_POWER_SUPPLY_DEEPCUT1 = 1U, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, AGTn, and USBFS/HS resume + * detecting unit is not supplied in deep software standby mode. In addition, LVD is + * disabled and the low power function in a poweron reset circuit is enabled + */ + LPM_POWER_SUPPLY_DEEPCUT3 = 3UL, +} lpm_power_supply_t; + +/** Deep Standby Interrupt Edge */ +typedef enum e_lpm_deep_standby_cancel_edge +{ + LPM_DEEP_STANDBY_CANCEL_SOURCE_EDGE_NONE = 0U, ///< No options for a deep standby cancel source + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_RISING = 0x00000001U, ///< IRQ0-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0_FALLING = 0U, ///< IRQ0-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_RISING = 0x00000002U, ///< IRQ1-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1_FALLING = 0U, ///< IRQ1-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_RISING = 0x00000004U, ///< IRQ2-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2_FALLING = 0U, ///< IRQ2-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_RISING = 0x00000008U, ///< IRQ3-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3_FALLING = 0U, ///< IRQ3-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_RISING = 0x00000010U, ///< IRQ4-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4_FALLING = 0U, ///< IRQ4-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_RISING = 0x00000020U, ///< IRQ5-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5_FALLING = 0U, ///< IRQ5-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_RISING = 0x00000040U, ///< IRQ6-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6_FALLING = 0U, ///< IRQ6-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_RISING = 0x00000080U, ///< IRQ7-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7_FALLING = 0U, ///< IRQ7-DS Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_RISING = 0x00000100U, ///< IRQ8-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8_FALLING = 0U, ///< IRQ8-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_RISING = 0x00000200U, ///< IRQ9-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9_FALLING = 0U, ///< IRQ9-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_RISING = 0x00000400U, ///< IRQ10-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10_FALLING = 0U, ///< IRQ10-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_RISING = 0x00000800U, ///< IRQ11-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11_FALLING = 0U, ///< IRQ11-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_RISING = 0x00001000U, ///< IRQ12-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12_FALLING = 0U, ///< IRQ12-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_RISING = 0x00002000U, ///< IRQ13-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13_FALLING = 0U, ///< IRQ13-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_RISING = 0x00004000U, ///< IRQ14-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_RISING = 0x00008000U, ///< IRQ14-DS Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15_FALLING = 0U, ///< IRQ14-DS Pin Falling Edge + + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_RISING = 0x00010000U, ///< LVD1 Rising Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1_FALLING = 0U, ///< LVD1 Falling Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_RISING = 0x00020000U, ///< LVD2 Rising Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2_FALLING = 0U, ///< LVD2 Falling Slope + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_RISING = 0x00100000U, ///< NMI Pin Rising Edge + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI_FALLING = 0U, ///< NMI Pin Falling Edge +} lpm_deep_standby_cancel_edge_t; + +typedef uint32_t lpm_deep_standby_cancel_edge_bits_t; + +/** Deep Standby cancel sources */ +typedef enum e_lpm_deep_standby_cancel_source +{ + LPM_DEEP_STANDBY_CANCEL_SOURCE_RESET_ONLY = 0U, ///< Cancel deep standby only by reset + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ0 = 0x00000001U, ///< IRQ0 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ1 = 0x00000002U, ///< IRQ1 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ2 = 0x00000004U, ///< IRQ2 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ3 = 0x00000008U, ///< IRQ3 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ4 = 0x00000010U, ///< IRQ4 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ5 = 0x00000020U, ///< IRQ5 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ6 = 0x00000040U, ///< IRQ6 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ7 = 0x00000080U, ///< IRQ7 + + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ8 = 0x00000100U, ///< IRQ8 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ9 = 0x00000200U, ///< IRQ9 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ10 = 0x00000400U, ///< IRQ10 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ11 = 0x00000800U, ///< IRQ11 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ12 = 0x00001000U, ///< IRQ12 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ13 = 0x00002000U, ///< IRQ13 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ14 = 0x00004000U, ///< IRQ14 + LPM_DEEP_STANDBY_CANCEL_SOURCE_IRQ15 = 0x00008000U, ///< IRQ15 + + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD1 = 0x00010000U, ///< LVD1 + LPM_DEEP_STANDBY_CANCEL_SOURCE_LVD2 = 0x00020000U, ///< LVD2 + LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_INTERVAL = 0x00040000U, ///< RTC Interval Interrupt + LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_ALARM = 0x00080000U, ///< RTC Alarm Interrupt + LPM_DEEP_STANDBY_CANCEL_SOURCE_NMI = 0x00100000U, ///< NMI + + LPM_DEEP_STANDBY_CANCEL_SOURCE_USBFS = 0x01000000U, ///< USBFS Suspend/Resume + LPM_DEEP_STANDBY_CANCEL_SOURCE_USBHS = 0x02000000U, ///< USBHS Suspend/Resume + LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT1 = 0x04000000U, ///< AGT1 Underflow +} lpm_deep_standby_cancel_source_t; + +typedef uint32_t lpm_deep_standby_cancel_source_bits_t; + +/** Output port enable */ +typedef enum e_lpm_output_port_enable +{ + /** + * 0: In Software Standby Mode or Deep Software Standby Mode, the + * address output pins, data output pins, and other bus control signal + * output pins are set to the high-impedance state. In Snooze, the + * status of the address bus and bus control signals are same as + * before entering Software Standby Mode. + */ + LPM_OUTPUT_PORT_ENABLE_HIGH_IMPEDANCE = 0U, + + /** + * 1: In Software Standby Mode, the address output pins, data output + * pins, and other bus control signal output pins retain the + * output state. + */ + LPM_OUTPUT_PORT_ENABLE_RETAIN = 1U, +} lpm_output_port_enable_t; + +/** User configuration structure, used in open function */ +typedef struct st_lpm_cfg +{ + /** Low Power Mode */ + lpm_mode_t low_power_mode; + + /** Bitwise list of sources to wake from standby */ + lpm_standby_wake_source_bits_t standby_wake_sources; + + /** Snooze request source */ + lpm_snooze_request_t snooze_request_source; + + /** Bitwise list of snooze end sources */ + lpm_snooze_end_bits_t snooze_end_sources; + + /** List of snooze cancel sources */ + lpm_snooze_cancel_t snooze_cancel_sources; + + /** State of DTC in snooze mode, enabled or disabled */ + lpm_snooze_dtc_t dtc_state_in_snooze; +#if BSP_FEATURE_LPM_HAS_SBYCR_OPE + + /** Output port enabled/disabled in standby and deep standby */ + lpm_output_port_enable_t output_port_enable; +#endif +#if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + + /** IO port state in deep standby (maintained or reset) */ + lpm_io_port_t io_port_state; + + /** Internal power supply state in standby and deep standby (deepcut) */ + lpm_power_supply_t power_supply_state; + + /** Sources that can trigger exit from deep standby */ + lpm_deep_standby_cancel_source_bits_t deep_standby_cancel_source; + + /** Signal edges for the sources that can trigger exit from deep standby */ + lpm_deep_standby_cancel_edge_bits_t deep_standby_cancel_edge; +#endif + + /** Placeholder for extension. */ + void const * p_extend; +} lpm_cfg_t; + +/** LPM control block. Allocate an instance specific control block to pass into the LPM API calls. + * @par Implemented as + * - lpm_instance_ctrl_t + */ +typedef void lpm_ctrl_t; + +/** LPM driver structure. General LPM functions implemented at the HAL layer will follow this API. */ +typedef struct st_lpm_api +{ + /** Initialization function + * @par Implemented as + * - @ref R_LPM_Open() + **/ + + fsp_err_t (* open)(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); + + /** Initialization function + * @par Implemented as + * - @ref R_LPM_Close() + **/ + fsp_err_t (* close)(lpm_ctrl_t * const p_api_ctrl); + + /** Configure a low power mode. + * @par Implemented as + * - @ref R_LPM_LowPowerReconfigure() + * + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + **/ + fsp_err_t (* lowPowerReconfigure)(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); + + /** Enter low power mode (sleep/standby/deep standby) using WFI macro. + * Function will return after waking from low power mode. + * @par Implemented as + * - @ref R_LPM_LowPowerModeEnter() + **/ + fsp_err_t (* lowPowerModeEnter)(lpm_ctrl_t * const p_api_ctrl); + + /** Clear the IOKEEP bit after deep software standby. + * * @par Implemented as + * - @ref R_LPM_IoKeepClear() + **/ + fsp_err_t (* ioKeepClear)(lpm_ctrl_t * const p_api_ctrl); +} lpm_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_lpm_instance +{ + lpm_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + lpm_cfg_t const * const p_cfg; ///< Pointer to the configuration structure for this instance + lpm_api_t const * const p_api; ///< Pointer to the API structure for this instance +} lpm_instance_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LPM_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_rtc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_rtc_api.h new file mode 100644 index 00000000..b61e643c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_rtc_api.h @@ -0,0 +1,306 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_RTC_API_H +#define R_RTC_API_H + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup RTC_API RTC Interface + * @brief Interface for accessing the Realtime Clock. + * + * + * @section RTC_API_Summary Summary + * The RTC Interface is for configuring Real Time Clock (RTC) functionality including alarm, periodic notiification and + * error adjustment. + * + * The Real Time Clock Interface can be implemented by: + * - @ref RTC + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Use of time structure, tm */ +#include + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events that can trigger a callback function */ +typedef enum e_rtc_event +{ + RTC_EVENT_ALARM_IRQ, ///< Real Time Clock ALARM IRQ + RTC_EVENT_PERIODIC_IRQ, ///< Real Time Clock PERIODIC IRQ +} rtc_event_t; + +/** Callback function parameter data */ +typedef struct st_rtc_callback_args +{ + rtc_event_t event; ///< The event can be used to identify what caused the callback (compare match or error). + void const * p_context; ///< Placeholder for user data. +} rtc_callback_args_t; + +/** Clock source for the RTC block */ +typedef enum e_rtc_count_source +{ + RTC_CLOCK_SOURCE_SUBCLK = 0, ///< Sub-clock oscillator + RTC_CLOCK_SOURCE_LOCO = 1 ///< Low power On Chip Oscillator +} rtc_clock_source_t; + +/** RTC run state */ +typedef enum e_rtc_status +{ + RTC_STATUS_STOPPED = 0, ///< RTC counter is stopped + RTC_STATUS_RUNNING = 1 ///< RTC counter is running +} rtc_status_t; + +/** Time error adjustment settings */ +typedef enum e_rtc_error_adjustment +{ + RTC_ERROR_ADJUSTMENT_NONE = 0, ///< Adjustment is not performed + RTC_ERROR_ADJUSTMENT_ADD_PRESCALER = 1, ///< Adjustment is performed by the addition to the prescaler + RTC_ERROR_ADJUSTMENT_SUBTRACT_PRESCALER = 2, ///< Adjustment is performed by the subtraction from the prescaler +} rtc_error_adjustment_t; + +/** Time error adjustment mode settings */ +typedef enum e_rtc_error_adjustment_mode +{ + RTC_ERROR_ADJUSTMENT_MODE_MANUAL = 0, ///< Adjustment mode is set to manual + RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC = 1, ///< Adjustment mode is set to automatic +} rtc_error_adjustment_mode_t; + +/** Time error adjustment period settings */ +typedef enum e_rtc_error_adjustment_period +{ + RTC_ERROR_ADJUSTMENT_PERIOD_1_MINUTE = 0, ///< Adjustment period is set to every one minute + RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND = 1, ///< Adjustment period is set to every ten second + RTC_ERROR_ADJUSTMENT_PERIOD_NONE = 2, ///< Adjustment period not supported in manual mode +} rtc_error_adjustment_period_t; + +/** Time error adjustment value configuration */ +typedef struct st_rtc_error_adjustment_cfg +{ + rtc_error_adjustment_mode_t adjustment_mode; ///< Automatic Adjustment Enable/Disable + rtc_error_adjustment_period_t adjustment_period; ///< Error Adjustment period + rtc_error_adjustment_t adjustment_type; ///< Time error adjustment setting + uint32_t adjustment_value; ///< Value of the prescaler for error adjustment +} rtc_error_adjustment_cfg_t; + +/** Periodic Interrupt select */ +typedef enum e_rtc_periodic_irq_select +{ + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_256_SECOND = 6, ///< A periodic irq is generated every 1/256 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_128_SECOND = 7, ///< A periodic irq is generated every 1/128 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_64_SECOND = 8, ///< A periodic irq is generated every 1/64 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_32_SECOND = 9, ///< A periodic irq is generated every 1/32 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_16_SECOND = 10, ///< A periodic irq is generated every 1/16 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_8_SECOND = 11, ///< A periodic irq is generated every 1/8 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_4_SECOND = 12, ///< A periodic irq is generated every 1/4 second + RTC_PERIODIC_IRQ_SELECT_1_DIV_BY_2_SECOND = 13, ///< A periodic irq is generated every 1/2 second + RTC_PERIODIC_IRQ_SELECT_1_SECOND = 14, ///< A periodic irq is generated every 1 second + RTC_PERIODIC_IRQ_SELECT_2_SECOND = 15, ///< A periodic irq is generated every 2 seconds +} rtc_periodic_irq_select_t; + +/** Date and time structure defined in C standard library */ +typedef struct tm rtc_time_t; + +/** Alarm time setting structure */ +typedef struct st_rtc_alarm_time +{ + rtc_time_t time; ///< Time structure + bool sec_match; ///< Enable the alarm based on a match of the seconds field + bool min_match; ///< Enable the alarm based on a match of the minutes field + bool hour_match; ///< Enable the alarm based on a match of the hours field + bool mday_match; ///< Enable the alarm based on a match of the days field + bool mon_match; ///< Enable the alarm based on a match of the months field + bool year_match; ///< Enable the alarm based on a match of the years field + bool dayofweek_match; ///< Enable the alarm based on a match of the dayofweek field +} rtc_alarm_time_t; + +/** RTC Information Structure for information returned by infoGet() */ +typedef struct st_rtc_info +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + rtc_status_t status; ///< RTC run status +} rtc_info_t; + +/** User configuration structure, used in open function */ +typedef struct st_rtc_cfg +{ + rtc_clock_source_t clock_source; ///< Clock source for the RTC block + uint32_t freq_compare_value_loco; ///< The frequency comparison value for LOCO + rtc_error_adjustment_cfg_t const * const p_err_cfg; ///< Pointer to Error Adjustment configuration + uint8_t alarm_ipl; ///< Alarm interrupt priority + IRQn_Type alarm_irq; ///< Alarm interrupt vector + uint8_t periodic_ipl; ///< Periodic interrupt priority + IRQn_Type periodic_irq; ///< Periodic interrupt vector + uint8_t carry_ipl; ///< Carry interrupt priority + IRQn_Type carry_irq; ///< Carry interrupt vector + void (* p_callback)(rtc_callback_args_t * p_args); ///< Called from the ISR. + void const * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< RTC hardware dependant configuration. +} rtc_cfg_t; + +/** RTC control block. Allocate an instance specific control block to pass into the RTC API calls. + * @par Implemented as + * - @ref rtc_instance_ctrl_t + */ +typedef void rtc_ctrl_t; + +/** RTC driver structure. General RTC functions implemented at the HAL layer follow this API. */ +typedef struct st_rtc_api +{ + /** Open the RTC driver. + * @par Implemented as + * - @ref R_RTC_Open() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_cfg Pointer to the configuration structure + */ + fsp_err_t (* open)(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); + + /** Close the RTC driver. + * @par Implemented as + * - @ref R_RTC_Close() + * + * @param[in] p_ctrl Pointer to RTC device handle. + */ + fsp_err_t (* close)(rtc_ctrl_t * const p_ctrl); + + /** Sets the RTC clock source. + * @par Implemented as + * - @ref R_RTC_ClockSourceSet() + * + * @param[in] p_ctrl Pointer to RTC device handle + */ + fsp_err_t (* clockSourceSet)(rtc_ctrl_t * const p_ctrl); + + /** Set the calendar time and start the calender counter + * @par Implemented as + * - @ref R_RTC_CalendarTimeSet() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_time Pointer to a time structure that contains the time to set + * @param[in] clock_start Flag that starts the clock right after it is set + */ + fsp_err_t (* calendarTimeSet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Get the calendar time. + * @par Implemented as + * - @ref R_RTC_CalendarTimeGet() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_time Pointer to a time structure that contains the time to get + */ + fsp_err_t (* calendarTimeGet)(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); + + /** Set the calendar alarm time and enable the alarm interrupt. + * @par Implemented as + * - @ref R_RTC_CalendarAlarmSet() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] p_alarm Pointer to an alarm structure that contains the alarm time to set + * @param[in] irq_enable_flag Enable the ALARM irq if set + */ + fsp_err_t (* calendarAlarmSet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Get the calendar alarm time. + * @par Implemented as + * - @ref R_RTC_CalendarAlarmGet() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[out] p_alarm Pointer to an alarm structure to fill up with the alarm time + */ + fsp_err_t (* calendarAlarmGet)(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); + + /** Set the periodic irq rate + * @par Implemented as + * - @ref R_RTC_PeriodicIrqRateSet() + * + * @param[in] p_ctrl Pointer to RTC device handle + * @param[in] rate Rate of periodic interrupts + */ + fsp_err_t (* periodicIrqRateSet)(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); + + /** Set time error adjustment. + * + * @par Implemented as + * - @ref R_RTC_ErrorAdjustmentSet() + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[in] err_adj_cfg Pointer to the Error Adjustment Config + */ + fsp_err_t (* errorAdjustmentSet)(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_RTC_CallbackSet() + * + * @param[in] p_ctrl Pointer to the RTC control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated + */ + fsp_err_t (* callbackSet)(rtc_ctrl_t * const p_ctrl, void (* p_callback)(rtc_callback_args_t *), + void const * const p_context, rtc_callback_args_t * const p_callback_memory); + + /** Return the currently configure clock source for the RTC + * + * @par Implemented as + * - @ref R_RTC_InfoGet() + * + * @param[in] p_ctrl Pointer to control handle structure + * @param[out] p_rtc_info Pointer to RTC information structure + */ + fsp_err_t (* infoGet)(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); +} rtc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_rtc_instance +{ + rtc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + rtc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + rtc_api_t const * p_api; ///< Pointer to the API structure for this instance +} rtc_instance_t; + +/*******************************************************************************************************************//** + * @} (end addtogroup RTC_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_sdmmc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_sdmmc_api.h new file mode 100644 index 00000000..ebb756f6 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_sdmmc_api.h @@ -0,0 +1,540 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SDMMC_API_H +#define R_SDMMC_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup SDMMC_API SD/MMC Interface + * @brief Interface for accessing SD, eMMC, and SDIO devices. + * + * @section SDMMC_API_SUMMARY Summary + * The r_sdhi interface provides standard SD and eMMC media functionality. This interface also supports SDIO. + * + * The SD/MMC interface is implemented by: + * - @ref SDHI + * + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** SD/MMC media uses SD protocol or MMC protocol. */ +typedef enum e_sdmmc_card_type +{ + SDMMC_CARD_TYPE_MMC = 0, ///< The media is an eMMC device. + SDMMC_CARD_TYPE_SD = 1, ///< The media is an SD card. + SDMMC_CARD_TYPE_SDIO = 2, ///< The media is an SDIO card. +} sdmmc_card_type_t; + +/** SD/MMC data bus is 1, 4 or 8 bits wide. */ +typedef enum e_sdmmc_bus_width +{ + SDMMC_BUS_WIDTH_1_BIT = 1, ///< Data bus is 1 bit wide. + SDMMC_BUS_WIDTH_4_BITS = 4, ///< Data bus is 4 bits wide. + SDMMC_BUS_WIDTH_8_BITS = 8, ///< Data bus is 8 bits wide. +} sdmmc_bus_width_t; + +/** SDIO transfer mode, configurable in SDIO read/write extended commands. */ +typedef enum e_sdmmc_io_transfer_mode +{ + SDMMC_IO_MODE_TRANSFER_BYTE = 0, ///< SDIO byte transfer mode + SDMMC_IO_MODE_TRANSFER_BLOCK ///< SDIO block transfer mode +} sdmmc_io_transfer_mode_t; + +/** SDIO address mode, configurable in SDIO read/write extended commands. */ +typedef enum e_sdmmc_io_address_mode +{ + SDMMC_IO_ADDRESS_MODE_FIXED = 0, ///< Write all data to the same address + SDMMC_IO_ADDRESS_MODE_INCREMENT ///< Increment destination address after each write +} sdmmc_io_address_mode_t; + +/** Controls the RAW (read after write) flag of CMD52. Used to read back the status after writing a control register. */ +typedef enum e_sdmmc_io_write_mode +{ + SDMMC_IO_WRITE_MODE_NO_READ = 0, ///< Write only (do not read back) + SDMMC_IO_WRITE_READ_AFTER_WRITE ///< Read back the register after write +} sdmmc_io_write_mode_t; + +/** Events that can trigger a callback function */ +typedef enum e_sdmmc_event +{ + SDMMC_EVENT_CARD_REMOVED = 1U << 0, ///< Card removed event. + SDMMC_EVENT_CARD_INSERTED = 1U << 1, ///< Card inserted event. + SDMMC_EVENT_RESPONSE = 1U << 3, ///< Response event. + SDMMC_EVENT_SDIO = 1U << 4, ///< IO event. + SDMMC_EVENT_TRANSFER_COMPLETE = 1U << 5, ///< Read or write complete. + SDMMC_EVENT_TRANSFER_ERROR = 1U << 6, ///< Read or write failed. + SDMMC_EVENT_ERASE_COMPLETE = 1U << 7, ///< Erase completed. + SDMMC_EVENT_ERASE_BUSY = 1U << 8, ///< Erase timeout, poll @ref sdmmc_api_t::statusGet. +} sdmmc_event_t; + +/** Card detection configuration options. */ +/* Card detection using DAT3 is not supported. */ +typedef enum e_sdmmc_card_detect +{ + SDMMC_CARD_DETECT_NONE, ///< Card detection unused. + SDMMC_CARD_DETECT_CD, ///< Card detection using the CD pin +} sdmmc_card_detect_t; + +/** Write protection configuration options. */ +typedef enum e_sdmmc_write_protect +{ + SDMMC_WRITE_PROTECT_NONE, ///< Write protection unused. + SDMMC_WRITE_PROTECT_WP, ///< Write protection using WP pin +} sdmmc_write_protect_t; + +/** Card state when receiving the prior command. */ +typedef enum e_sdmmc_r1_state +{ + SDMMC_R1_STATE_IDLE = 0, ///< Idle State + SDMMC_R1_STATE_READY = 0, ///< Ready State + SDMMC_R1_STATE_IDENT = 0, ///< Identification State + SDMMC_R1_STATE_STBY = 0, ///< Stand-by State + SDMMC_R1_STATE_TRAN = 0, ///< Transfer State + SDMMC_R1_STATE_DATA = 0, ///< Sending-data State + SDMMC_R1_STATE_RCV = 0, ///< Receive-data State + SDMMC_R1_STATE_PRG = 0, ///< Programming State + SDMMC_R1_STATE_DIS = 0, ///< Disconnect State (between programming and stand-by) + SDMMC_R1_STATE_IO = 15, ///< This is an I/O card and memory states do not apply +} sdmmc_r1_state_t; + +/* Structure for decoding the response of a command. For advanced use only. */ +typedef union u_sdmmc_response +{ + uint32_t status; + + /** SDIO Card Status Register. */ + struct + { + uint32_t : 3; + uint32_t ake_seq_error : 1; // Error in the sequence of the authentication process + uint32_t : 1; + uint32_t app_cmd : 1; // The card will expect ACMD, or an indication that the command has been interpreted as ACMD + uint32_t fx_event : 1; // Extension Functions may set this bit to get host to deal with events + uint32_t switch_error : 1; // + uint32_t ready_for_data : 1; // Corresponds to the buffer empty signaling on the bus + + /* The state of the card when receiving the command. If the command execution causes a state change, it will be + * visible to the host in the response to the next command. */ + sdmmc_r1_state_t current_state : 4; + uint32_t erase_reset : 1; // An erase sequence was cleared before executing because an out of erase sequence command was received. + uint32_t card_ecc_disabled : 1; // The command has been executed without using the internal ECC. + uint32_t wp_erase_skip : 1; // Set when only partial address space was erased due to existing write protected blocks or the temporary or permanent write protected card was erased. + uint32_t csd_overwrite : 1; // The read only section of the CSD does not match the card content or an attempt to reverse the copy or permanent WP bits was made. + uint32_t : 2; + uint32_t error : 1; // A general or unknown error occurred during the operation. + uint32_t cc_error : 1; // Internal card controller error. + uint32_t card_ecc_failed : 1; // Card internal ECC was applied but failed to correct the data. + uint32_t illegal_command : 1; // Command not legal for the card state. + uint32_t com_crc_error : 1; // The CRC check of the previous command failed. + uint32_t lock_unlock_failed : 1; // Set when a sequence or password error has been detected in the lock/unlock command. + uint32_t device_is_locked : 1; // When set, signals that the card is locked by the host. + uint32_t wp_violation : 1; // Set when the host attempts to write to a protected block or to the temporary or permanent write protected card. + uint32_t erase_param : 1; // An invalid selection of write-blocks for erase occurred. + uint32_t erase_seq_error : 1; // An error in the sequence of erase commands occurred. + uint32_t block_len_error : 1; // The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. + uint32_t address_error : 1; // A misaligned address which did not match the block length was used in the command. + uint32_t out_of_range : 1; // The command's argument was out of the allowed range for this card. + } status_b; + + struct + { + uint32_t reserved_0 : 7; + + uint32_t reserved_lvr : 1; + uint32_t reserved_8 : 7; + uint32_t v_27_28 : 1; + uint32_t v_28_29 : 1; + uint32_t v_29_30 : 1; + uint32_t v_30_31 : 1; + uint32_t v_31_32 : 1; + uint32_t v_32_33 : 1; + uint32_t v_33_34 : 1; + uint32_t v_34_35 : 1; + uint32_t v_35_36 : 1; + uint32_t s18A : 1; + uint32_t reserved_25 : 5; + uint32_t card_capacity_status : 1; + uint32_t power_up_status : 1; + } r3; + + struct + { + uint32_t ocr : 24; + + uint32_t reserved_24 : 3; + uint32_t memory : 1; + uint32_t io_functions : 3; + uint32_t ready : 1; + } r4; + + struct + { + uint32_t read_write_data : 8; + + uint32_t out_of_range : 1; + uint32_t invalid_function : 1; + uint32_t rfu : 1; + uint32_t error : 1; + uint32_t current_state : 2; + uint32_t illegal_command : 1; + uint32_t crc_error : 1; + uint32_t reserved_16 : 16; + } r5; + + struct + { + uint32_t reserved_0 : 3; + + uint32_t ake_seq_error : 1; + uint32_t reserved_4 : 1; + uint32_t app_cmd : 1; + uint32_t reserved_6 : 2; + uint32_t ready_for_data : 1; + sdmmc_r1_state_t current_state : 4; + uint32_t error : 1; + uint32_t illegal_command : 1; + uint32_t com_crc_error : 1; + uint32_t rca : 16; + } r6; + + struct + { + uint32_t check_pattern : 8; + + uint32_t voltage_accepted : 4; + uint32_t reserved_11 : 20; + } r7; +} sdmmc_response_t; + +/** Current status. */ +typedef struct s_sdmmc_status +{ + /** False if card was removed (only applies if MCU supports card detection and SDnCD pin is connected), true otherwise. + * + * If ready is false, call @ref sdmmc_api_t::mediaInit to reinitialize it + */ + bool initialized; + bool transfer_in_progress; ///< true = Card is busy + bool card_inserted; ///< Card detect status, true if card detect is not used +} sdmmc_status_t; + +/** Information obtained from the media device. */ +typedef struct s_sdmmc_device +{ + sdmmc_card_type_t card_type; ///< SD, eMMC, or SDIO + bool write_protected; ///< true = Card is write protected + uint32_t clock_rate; ///< Current clock rate + uint32_t sector_count; ///< Sector count + uint32_t sector_size_bytes; ///< Sector size + uint32_t erase_sector_count; ///< Minimum erasable unit (in 512 byte sectors) +} sdmmc_device_t; + +/** Callback function parameter data */ +typedef struct st_sdmmc_callback_args +{ + sdmmc_event_t event; ///< The event can be used to identify what caused the callback. + sdmmc_response_t response; ///< Response from card, only valid if SDMMC_EVENT_RESPONSE is set in event. + void const * p_context; ///< Placeholder for user data. +} sdmmc_callback_args_t; + +/** Non-secure arguments for writeIo guard function */ +typedef struct st_sdmmc_write_io_args_t +{ + uint8_t * const p_data; + uint32_t function; + uint32_t address; + sdmmc_io_write_mode_t read_after_write; +} sdmmc_write_io_args_t; + +/** Non-secure arguments for readIoExt guard function */ +typedef struct st_sdmmc_read_io_ext_args_t +{ + uint8_t * const p_dest; + uint32_t function; + uint32_t address; + uint32_t * const count; + sdmmc_io_transfer_mode_t transfer_mode; + sdmmc_io_address_mode_t address_mode; +} sdmmc_read_io_ext_args_t; + +/** Non-secure arguments for writeIoExt guard function */ +typedef struct st_sdmmc_write_io_ext_args_t +{ + uint8_t const * const p_source; + uint32_t function; + uint32_t address; + uint32_t count; + sdmmc_io_transfer_mode_t transfer_mode; + sdmmc_io_address_mode_t address_mode; +} sdmmc_write_io_ext_args_t; + +/** SD/MMC Configuration */ +typedef struct st_sdmmc_cfg +{ + /* SD/MMC generic configuration */ + uint8_t channel; ///< Channel of SD/MMC host interface. + sdmmc_bus_width_t bus_width; ///< Device bus width is 1, 4 or 8 bits wide. + transfer_instance_t const * p_lower_lvl_transfer; ///< Transfer instance used to move data with DMA or DTC + + /* Configuration for SD/MMC Event processing */ + void (* p_callback)(sdmmc_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< User defined context passed into callback function + + /* Pointer to SD/MMC peripheral specific configuration */ + void const * p_extend; ///< SD/MMC hardware dependent configuration + + /** Block size in bytes. Block size must be 512 bytes for SD cards and eMMC devices. Block size can be 1-512 + * bytes for SDIO. */ + uint32_t block_size; + + /** Whether or not card detection is used. */ + sdmmc_card_detect_t card_detect; + + /** Select whether or not to use the write protect pin. Select Not Used if the MCU or device does not have a write protect pin. */ + sdmmc_write_protect_t write_protect; + IRQn_Type access_irq; ///< Access IRQ number + IRQn_Type sdio_irq; ///< SDIO IRQ number + IRQn_Type card_irq; ///< Card IRQ number + IRQn_Type dma_req_irq; ///< DMA request IRQ number + uint8_t access_ipl; ///< Access interrupt priority + uint8_t sdio_ipl; ///< SDIO interrupt priority + uint8_t card_ipl; ///< Card interrupt priority + uint8_t dma_req_ipl; ///< DMA request interrupt priority +} sdmmc_cfg_t; + +/** SD/MMC control block. Allocate an instance specific control block to pass into the SD/MMC API calls. + * @par Implemented as + * - sdmmc_instance_ctrl_t + */ +typedef void sdmmc_ctrl_t; + +/** SD/MMC functions implemented at the HAL layer API. */ +typedef struct st_sdmmc_api +{ + /** Open the SD/MMC driver. + * + * @par Implemented as + * - @ref R_SDHI_Open() + * + * @param[in] p_ctrl Pointer to SD/MMC instance control block. + * @param[in] p_cfg Pointer to SD/MMC instance configuration structure. + */ + fsp_err_t (* open)(sdmmc_ctrl_t * const p_ctrl, sdmmc_cfg_t const * const p_cfg); + + /** Initializes an SD/MMC device. If the device is a card, the card must be plugged in prior to calling this API. + * This API blocks until the device initialization procedure is complete. + * + * @par Implemented as + * - @ref R_SDHI_MediaInit() + * + * @param[in] p_ctrl Pointer to SD/MMC instance control block. + * @param[out] p_device Pointer to store device information. + */ + fsp_err_t (* mediaInit)(sdmmc_ctrl_t * const p_ctrl, sdmmc_device_t * const p_device); + + /** Read data from an SD/MMC channel. + * This API is not supported for SDIO devices. + * + * @par Implemented as + * - @ref R_SDHI_Read() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_dest Pointer to data buffer to read data to. + * @param[in] start_sector First sector address to read. + * @param[in] sector_count Number of sectors to read. All sectors must be in the range of + * sdmmc_device_t::sector_count. + */ + fsp_err_t (* read)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const start_sector, + uint32_t const sector_count); + + /** Write data to SD/MMC channel. + * This API is not supported for SDIO devices. + * + * @par Implemented as + * - @ref R_SDHI_Write() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] p_source Pointer to data buffer to write data from. + * @param[in] start_sector First sector address to write to. + * @param[in] sector_count Number of sectors to write. All sectors must be in the range of + * sdmmc_device_t::sector_count. + */ + fsp_err_t (* write)(sdmmc_ctrl_t * const p_ctrl, uint8_t const * const p_source, uint32_t const start_sector, + uint32_t const sector_count); + + /** Read one byte of I/O data from an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * @par Implemented as + * - @ref R_SDHI_ReadIo() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_data Pointer to location to store data byte. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + */ + fsp_err_t (* readIo)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t const function, + uint32_t const address); + + /** Write one byte of I/O data to an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * @par Implemented as + * - @ref R_SDHI_WriteIo() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in,out] p_data Pointer to data byte to write. Read data is also provided here if + * read_after_write is true. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] read_after_write Whether or not to read back the same register after writing + */ + fsp_err_t (* writeIo)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_data, uint32_t const function, + uint32_t const address, sdmmc_io_write_mode_t const read_after_write); + + /** Read multiple bytes or blocks of I/O data from an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * @par Implemented as + * - @ref R_SDHI_ReadIoExt() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_dest Pointer to data buffer to read data to. + * @param[in] function SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] count Number of bytes or blocks to read, maximum 512 bytes or 511 blocks. + * @param[in] transfer_mode Byte or block mode + * @param[in] address_mode Fixed or incrementing address mode + */ + fsp_err_t (* readIoExt)(sdmmc_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const function, + uint32_t const address, uint32_t * const count, sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); + + /** Write multiple bytes or blocks of I/O data to an SDIO device. + * This API is not supported for SD or eMMC memory devices. + * + * @par Implemented as + * - @ref R_SDHI_WriteIoExt() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] p_source Pointer to data buffer to write data from. + * @param[in] function_number SDIO Function Number. + * @param[in] address SDIO register address. + * @param[in] count Number of bytes or blocks to write, maximum 512 bytes or 511 blocks. + * @param[in] transfer_mode Byte or block mode + * @param[in] address_mode Fixed or incrementing address mode + */ + fsp_err_t (* writeIoExt)(sdmmc_ctrl_t * const p_ctrl, uint8_t const * const p_source, uint32_t const function, + uint32_t const address, uint32_t const count, sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); + + /** Enables SDIO interrupt for SD/MMC instance. + * This API is not supported for SD or eMMC memory devices. + * + * @par Implemented as + * - @ref R_SDHI_IoIntEnable + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] enable Interrupt enable = true, interrupt disable = false. + */ + fsp_err_t (* ioIntEnable)(sdmmc_ctrl_t * const p_ctrl, bool enable); + + /** Get SD/MMC device status. + * + * @par Implemented as + * - @ref R_SDHI_StatusGet() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[out] p_status Pointer to current driver status. + */ + fsp_err_t (* statusGet)(sdmmc_ctrl_t * const p_ctrl, sdmmc_status_t * const p_status); + + /** Erase SD/MMC sectors. The sector size for erase is fixed at 512 bytes. + * This API is not supported for SDIO devices. + * + * @par Implemented as + * - @ref R_SDHI_Erase + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + * @param[in] start_sector First sector to erase. Must be a multiple of sdmmc_device_t::erase_sector_count. + * @param[in] sector_count Number of sectors to erase. Must be a multiple of sdmmc_device_t::erase_sector_count. + * All sectors must be in the range of sdmmc_device_t::sector_count. + */ + fsp_err_t (* erase)(sdmmc_ctrl_t * const p_ctrl, uint32_t const start_sector, uint32_t const sector_count); + + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_SDHI_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref sdmmc_api_t::open call. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(sdmmc_ctrl_t * const p_api_ctrl, void (* p_callback)(sdmmc_callback_args_t *), + void const * const p_context, sdmmc_callback_args_t * const p_callback_memory); + + /** Close open SD/MMC device. + * + * @par Implemented as + * - @ref R_SDHI_Close() + * + * @param[in] p_ctrl Pointer to an open SD/MMC instance control block. + */ + fsp_err_t (* close)(sdmmc_ctrl_t * const p_ctrl); +} sdmmc_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_sdmmc_instance +{ + sdmmc_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + sdmmc_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + sdmmc_api_t const * p_api; ///< Pointer to the API structure for this instance +} sdmmc_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup SDMMC_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_api.h new file mode 100644 index 00000000..bc5ab3e7 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_api.h @@ -0,0 +1,299 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SPI_API_H +#define R_SPI_API_H + +/*****************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup SPI_API SPI Interface + * @brief Interface for SPI communications. + * + * @section SPI_API_SUMMARY Summary + * Provides a common interface for communication using the SPI Protocol. + * + * Implemented by: + * - @ref SPI + * - @ref SCI_SPI + * + * @{ + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Includes + ********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + ********************************************************************************************************************/ + +/** Data bit width */ +typedef enum e_spi_bit_width +{ + SPI_BIT_WIDTH_4_BITS = (3), ///< Data bit width is 4 bits (byte) + SPI_BIT_WIDTH_5_BITS = (4), ///< Data bit width is 5 bits (byte) + SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits (byte) + SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits (byte) + SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits (byte) + SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits (word) + SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits (word) + SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits (word) + SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits (word) + SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits (word) + SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits (word) + SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits (word) + SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits (word) + SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits (word) + SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits (word) + SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits (word) + SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits (longword) + SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits (word) + SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits (word) + SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits (longword) + SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits (longword) + SPI_BIT_WIDTH_25_BITS = (25), ///< Data bit width is 25 bits (longword) + SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits (word) + SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits (word) + SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits (word) + SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits (word) + SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits (longword) + SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits (longword) + SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits (longword) +} spi_bit_width_t; + +/** Master or slave operating mode */ +typedef enum e_spi_mode +{ + SPI_MODE_MASTER, ///< Channel operates as SPI master + SPI_MODE_SLAVE ///< Channel operates as SPI slave +} spi_mode_t; + +/** Clock phase */ +typedef enum e_spi_clk_phase +{ + SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge + SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge +} spi_clk_phase_t; + +/** Clock polarity */ +typedef enum e_spi_clk_polarity +{ + SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle + SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle +} spi_clk_polarity_t; + +/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be + * controlled by the master. This usually happens when the connecting device is also acting as master. + * A similar situation can also happen when configured as a slave. */ +typedef enum e_spi_mode_fault +{ + SPI_MODE_FAULT_ERROR_ENABLE, ///< Mode fault error flag on + SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off +} spi_mode_fault_t; + +/** Bit order */ +typedef enum e_spi_bit_order +{ + SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission + SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission +} spi_bit_order_t; + +/** SPI events */ +typedef enum e_spi_event +{ + SPI_EVENT_TRANSFER_COMPLETE = 1, ///< The data transfer was completed + SPI_EVENT_TRANSFER_ABORTED, ///< The data transfer was aborted + SPI_EVENT_ERR_MODE_FAULT, ///< Mode fault error + SPI_EVENT_ERR_READ_OVERFLOW, ///< Read overflow error + SPI_EVENT_ERR_PARITY, ///< Parity error + SPI_EVENT_ERR_OVERRUN, ///< Overrun error + SPI_EVENT_ERR_FRAMING, ///< Framing error + SPI_EVENT_ERR_MODE_UNDERRUN ///< Underrun error +} spi_event_t; + +/** Common callback parameter definition */ +typedef struct st_spi_callback_args +{ + uint32_t channel; ///< Device channel number + spi_event_t event; ///< Event code + void const * p_context; ///< Context provided to user during callback +} spi_callback_args_t; + +/** Non-secure arguments for write-read guard function */ +typedef struct st_spi_write_read_guard_args +{ + void const * p_src; + void * p_dest; + uint32_t const length; + spi_bit_width_t const bit_width; +} spi_write_read_guard_args_t; + +/** SPI interface configuration */ +typedef struct st_spi_cfg +{ + uint8_t channel; ///< Channel number to be used + + IRQn_Type rxi_irq; ///< Receive Buffer Full IRQ number + IRQn_Type txi_irq; ///< Transmit Buffer Empty IRQ number + IRQn_Type tei_irq; ///< Transfer Complete IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t rxi_ipl; ///< Receive Interrupt priority + uint8_t txi_ipl; ///< Transmit Interrupt priority + uint8_t tei_ipl; ///< Transfer Complete Interrupt priority + uint8_t eri_ipl; ///< Error Interrupt priority + spi_mode_t operating_mode; ///< Select master or slave operating mode + spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge + spi_clk_polarity_t clk_polarity; ///< Clock level when idle + spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag + spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first + transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here. Set to NULL if unused. + void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function + void const * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extended SPI hardware dependent configuration +} spi_cfg_t; + +/** SPI control block. Allocate an instance specific control block to pass into the SPI API calls. + * @par Implemented as + * - spi_instance_ctrl_t + * - spi_b_instance_ctrl_t + * - sci_spi_instance_ctrl_t + */ +typedef void spi_ctrl_t; + +/** Shared Interface definition for SPI */ +typedef struct st_spi_api +{ + /** Initialize a channel for SPI communication mode. + * @par Implemented as + * - @ref R_SPI_Open() + * - @ref R_SPI_B_Open() + * - @ref R_SCI_SPI_Open() + * + * @param[in, out] p_ctrl Pointer to user-provided storage for the control block. + * @param[in] p_cfg Pointer to SPI configuration structure. + */ + fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg); + + /** Receive data from a SPI device. + * @par Implemented as + * - @ref R_SPI_Read() + * - @ref R_SPI_B_Read() + * - @ref R_SCI_SPI_Read() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. + */ + fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Transmit data to a SPI device. + * @par Implemented as + * - @ref R_SPI_Write() + * - @ref R_SPI_B_Write() + * - @ref R_SCI_SPI_Write() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex). + * @par Implemented as + * - @ref R_SPI_WriteRead() + * - @ref R_SPI_B_WriteRead() + * - @ref R_SCI_SPI_WriteRead() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_SPI_CallbackSet() + * - @ref R_SPI_B_CallbackSet() + * - @ref R_SCI_SPI_CallbackSet() + * + * @param[in] p_ctrl Pointer to the SPI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *), + void const * const p_context, spi_callback_args_t * const p_callback_memory); + + /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. + * @par Implemented as + * - @ref R_SPI_Close() + * - @ref R_SPI_B_Close() + * - @ref R_SCI_SPI_Close() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + */ + fsp_err_t (* close)(spi_ctrl_t * const p_ctrl); +} spi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_instance +{ + spi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*****************************************************************************************************************//** + * @} (end defgroup SPI_API) + ********************************************************************************************************************/ + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_flash_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_flash_api.h new file mode 100644 index 00000000..ea304d1d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_spi_flash_api.h @@ -0,0 +1,353 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup SPI_FLASH_API SPI Flash Interface + * @brief Interface for accessing external SPI flash devices. + * + * @section SPI_FLASH_API_SUMMARY Summary + * The SPI flash API provides an interface that configures, writes, and erases sectors in SPI flash devices. + * + * Implemented by: + * - @ref OSPI + * - @ref QSPI + * @{ + **********************************************************************************************************************/ + +#ifndef R_SPI_FLASH_API_H +#define R_SPI_FLASH_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SPI_FLASH_ERASE_SIZE_CHIP_ERASE (UINT32_MAX) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Read mode. */ +typedef enum e_spi_flash_read_mode +{ + SPI_FLASH_READ_MODE_STANDARD = 0, ///< Standard Read Mode (no dummy cycles) + SPI_FLASH_READ_MODE_FAST_READ = 1, ///< Fast Read Mode (dummy cycles between address and data) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_OUTPUT = 2, ///< Fast Read Dual Output Mode (data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_DUAL_IO = 3, ///< Fast Read Dual I/O Mode (address and data on 2 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_OUTPUT = 4, ///< Fast Read Quad Output Mode (data on 4 lines) + SPI_FLASH_READ_MODE_FAST_READ_QUAD_IO = 5, ///< Fast Read Quad I/O Mode (address and data on 4 lines) +} spi_flash_read_mode_t; + +/** SPI protocol. */ +typedef enum e_spi_flash_protocol +{ + SPI_FLASH_PROTOCOL_EXTENDED_SPI = 0, ///< Extended SPI mode (commands on 1 line) + + /** QPI mode (commands on 4 lines). Note that the application must ensure the device is in QPI mode. */ + SPI_FLASH_PROTOCOL_QPI = 2, + + /** SOPI mode (command and data on 8 lines). Note that the application must ensure the device is in SOPI mode. */ + SPI_FLASH_PROTOCOL_SOPI = 3, + + /** DOPI mode (command and data on 8 lines, dual data rate). Note that the application must ensure the device is in DOPI mode. */ + SPI_FLASH_PROTOCOL_DOPI = 4, +} spi_flash_protocol_t; + +/** Number of bytes in the address. */ +typedef enum e_spi_flash_address_bytes +{ + SPI_FLASH_ADDRESS_BYTES_3 = 2, ///< 3 address bytes + + /** 4 address bytes with standard commands. If this option is selected, the application must issue the EN4B + * command using @ref spi_flash_api_t::directWrite() if required by the device. */ + SPI_FLASH_ADDRESS_BYTES_4 = 3, + + /** 4 address bytes using standard 4-byte command set. */ + SPI_FLASH_ADDRESS_BYTES_4_4BYTE_READ_CODE = 0x13, +} spi_flash_address_bytes_t; + +/** Number of data lines used. */ +typedef enum e_spi_flash_data_lines +{ + SPI_FLASH_DATA_LINES_1 = 0, ///< 1 data line + SPI_FLASH_DATA_LINES_2 = 1, ///< 2 data lines + SPI_FLASH_DATA_LINES_4 = 2, ///< 4 data lines +} spi_flash_data_lines_t; + +/** Number of dummy cycles for fast read operations. */ +typedef enum e_spi_flash_dummy_clocks +{ + /** Default is 6 clocks for Fast Read Quad I/O, 4 clocks for Fast Read Dual I/O, and 8 clocks for other + * fast read instructions including Fast Read Quad Output, Fast Read Dual Output, and Fast Read. */ + SPI_FLASH_DUMMY_CLOCKS_DEFAULT, + SPI_FLASH_DUMMY_CLOCKS_3, ///< 3 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_4, ///< 4 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_5, ///< 5 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_6, ///< 6 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_7, ///< 7 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_8, ///< 8 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_9, ///< 9 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_10, ///< 10 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_11, ///< 11 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_12, ///< 12 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_13, ///< 13 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_14, ///< 14 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_15, ///< 15 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_16, ///< 16 dummy clocks + SPI_FLASH_DUMMY_CLOCKS_17, ///< 17 dummy clocks +} spi_flash_dummy_clocks_t; + +/** Direct Read and Write direction */ +typedef enum e_spi_flash_direct_transfer_dir_option +{ + SPI_FLASH_DIRECT_TRANSFER_DIR_READ = 0x0, + SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE = 0x1 +} spi_flash_direct_transfer_dir_t; + +/** Structure to define an erase command and associated erase size. */ +typedef struct st_spi_flash_erase_command +{ + uint16_t command; ///< Erase command + uint32_t size; ///< Size of erase for associated command, set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE for chip erase +} spi_flash_erase_command_t; + +/** Structure to define a direct transfer. */ +typedef struct st_spi_flash_direct_transfer +{ + uint32_t address; ///< Starting address + uint32_t data; ///< Data + uint16_t command; ///< Transfer command + uint8_t dummy_cycles; ///< Number of dummy cycles + uint8_t command_length; ///< Command length + uint8_t address_length; ///< Address lengrh + uint8_t data_length; ///< Data length +} spi_flash_direct_transfer_t; + +/** User configuration structure used by the open function */ +typedef struct st_spi_flash_cfg +{ + spi_flash_protocol_t spi_protocol; ///< Initial SPI protocol. SPI protocol can be changed in @ref spi_flash_api_t::spiProtocolSet. + spi_flash_read_mode_t read_mode; ///< Read mode + spi_flash_address_bytes_t address_bytes; ///< Number of bytes used to represent the address + spi_flash_dummy_clocks_t dummy_clocks; ///< Number of dummy clocks to use for fast read operations + + /** Number of lines used to send address for page program command. This should either be 1 or match the number of lines used in + * the selected read mode. */ + spi_flash_data_lines_t page_program_address_lines; + uint8_t write_status_bit; ///< Which bit determines write status + uint8_t write_enable_bit; ///< Which bit determines write status + uint32_t page_size_bytes; ///< Page size in bytes (maximum number of bytes for page program). Used to specify single continuous write size (bytes) in case of OSPI RAM. + uint8_t page_program_command; ///< Page program command + uint8_t write_enable_command; ///< Command to enable write or erase, typically 0x06 + uint8_t status_command; ///< Command to read the write status + uint8_t read_command; ///< Read command - OSPI SPI mode only + uint8_t xip_enter_command; ///< Command to enter XIP mode + uint8_t xip_exit_command; ///< Command to exit XIP mode + uint8_t erase_command_list_length; ///< Length of erase command list + spi_flash_erase_command_t const * p_erase_command_list; ///< List of all erase commands and associated sizes + void const * p_extend; ///< Pointer to implementation specific extended configurations +} spi_flash_cfg_t; + +/** SPI flash control block. Allocate an instance specific control block to pass into the SPI flash API calls. + * @par Implemented as + * - qspi_instance_ctrl_t + * - ospi_instance_ctrl_t + */ +typedef void spi_flash_ctrl_t; + +/** Status. */ +typedef struct st_spi_flash_status +{ + /** Whether or not a write is in progress. This is determined by reading the @ref spi_flash_cfg_t::write_status_bit + * from the @ref spi_flash_cfg_t::status_command. */ + bool write_in_progress; +} spi_flash_status_t; + +/** SPI flash implementations follow this API. */ +typedef struct st_spi_flash_api +{ + /** Open the SPI flash driver module. + * @par Implemented as + * - @ref R_OSPI_Open() + * - @ref R_QSPI_Open() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_cfg Pointer to a configuration structure + **/ + fsp_err_t (* open)(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); + + /** Write raw data to the SPI flash. + * @par Implemented as + * - @ref R_OSPI_DirectWrite() + * - @ref R_QSPI_DirectWrite() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src Pointer to raw data to write, must include any required command/address + * @param[in] bytes Number of bytes to write + * @param[in] read_after_write If true, the slave select remains asserted and the peripheral does not return + * to direct communications mode. If false, the slave select is deasserted and + * memory mapped access is possible after this function returns if the device + * is not busy. + **/ + fsp_err_t (* directWrite)(spi_flash_ctrl_t * p_ctrl, uint8_t const * const p_src, uint32_t const bytes, + bool const read_after_write); + + /** Read raw data from the SPI flash. Must follow a call to @ref spi_flash_api_t::directWrite. + * @par Implemented as + * - @ref R_OSPI_DirectRead() + * - @ref R_QSPI_DirectRead() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_dest Pointer to read raw data into + * @param[in] bytes Number of bytes to read + **/ + fsp_err_t (* directRead)(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Direct Read/Write raw data to the SPI flash. + * @par Implemented as + * - @ref R_OSPI_DirectTransfer() + * - @ref R_QSPI_DirectTransfer() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_data Pointer to command, address and data values and lengths + * @param[in] direction Direct Read/Write + **/ + fsp_err_t (* directTransfer)(spi_flash_ctrl_t * p_ctrl, spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); + + /** Change the SPI protocol in the driver. The application must change the SPI protocol on the device. + * @par Implemented as + * - @ref R_OSPI_SpiProtocolSet() + * - @ref R_QSPI_SpiProtocolSet() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] spi_protocol Desired SPI protocol + **/ + fsp_err_t (* spiProtocolSet)(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); + + /** Program a page of data to the flash. + * @par Implemented as + * - @ref R_OSPI_Write() + * - @ref R_QSPI_Write() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_src The memory address of the data to write to the flash device + * @param[in] p_dest The location in the flash device address space to write the data to + * @param[in] byte_count The number of bytes to write + **/ + fsp_err_t (* write)(spi_flash_ctrl_t * p_ctrl, uint8_t const * const p_src, uint8_t * const p_dest, + uint32_t byte_count); + + /** Erase a certain number of bytes of the flash. + * @par Implemented as + * - @ref R_OSPI_Erase() + * - @ref R_QSPI_Erase() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] p_device_address The location in the flash device address space to start the erase from + * @param[in] byte_count The number of bytes to erase. Set to SPI_FLASH_ERASE_SIZE_CHIP_ERASE to erase entire + * chip. + **/ + fsp_err_t (* erase)(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); + + /** Get the write or erase status of the flash. + * @par Implemented as + * - @ref R_OSPI_StatusGet() + * - @ref R_QSPI_StatusGet() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[out] p_status Current status of the SPI flash device stored here. + **/ + fsp_err_t (* statusGet)(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); + + /** Enter XIP mode. + * @par Implemented as + * - @ref R_OSPI_XipEnter() + * - @ref R_QSPI_XipEnter() + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipEnter)(spi_flash_ctrl_t * p_ctrl); + + /** Exit XIP mode. + * @par Implemented as + * - @ref R_OSPI_XipExit() + * - @ref R_QSPI_XipExit() + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* xipExit)(spi_flash_ctrl_t * p_ctrl); + + /** Select the bank to access. See implementation for details. + * @par Implemented as + * - @ref R_OSPI_BankSet() + * - @ref R_QSPI_BankSet() + * + * @param[in] p_ctrl Pointer to a driver handle + * @param[in] bank The bank number + **/ + fsp_err_t (* bankSet)(spi_flash_ctrl_t * p_ctrl, uint32_t bank); + + /** AutoCalibrate the SPI flash driver module. Expected to be used when auto-calibrating OSPI RAM device. + * @par Implemented as + * - @ref R_OSPI_AutoCalibrate() + * - @ref R_QSPI_AutoCalibrate() + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* autoCalibrate)(spi_flash_ctrl_t * p_ctrl); + + /** Close the SPI flash driver module. + * @par Implemented as + * - @ref R_OSPI_Close() + * - @ref R_QSPI_Close() + * + * @param[in] p_ctrl Pointer to a driver handle + **/ + fsp_err_t (* close)(spi_flash_ctrl_t * p_ctrl); +} spi_flash_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_flash_instance +{ + spi_flash_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_flash_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_flash_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_flash_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup SPI_FLASH_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_timer_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_timer_api.h new file mode 100644 index 00000000..57ef0c80 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_timer_api.h @@ -0,0 +1,333 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_TIMER_API_H +#define R_TIMER_API_H + +/*******************************************************************************************************************//** + * @defgroup TIMER_API Timer Interface + * @ingroup RENESAS_INTERFACES + * @brief Interface for timer functions. + * + * @section TIMER_API_SUMMARY Summary + * The general timer interface provides standard timer functionality including periodic mode, one-shot mode, PWM output, + * and free-running timer mode. After each timer cycle (overflow or underflow), an interrupt can be triggered. + * + * If an instance supports output compare mode, it is provided in the extension configuration + * timer_on__cfg_t defined in r_.h. + * + * Implemented by: + * - @ref GPT + * - @ref AGT + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standard violation. */ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Events that can trigger a callback function */ +typedef enum e_timer_event +{ + TIMER_EVENT_CYCLE_END, ///< Requested timer delay has expired or timer has wrapped around + TIMER_EVENT_CREST = TIMER_EVENT_CYCLE_END, ///< Timer crest event (counter is at a maximum, triangle-wave PWM only) + TIMER_EVENT_CAPTURE_A, ///< A capture has occurred on signal A + TIMER_EVENT_CAPTURE_B, ///< A capture has occurred on signal B + TIMER_EVENT_TROUGH, ///< Timer trough event (counter is 0, triangle-wave PWM only +} timer_event_t; + +/** Timer variant types. */ +typedef enum e_timer_variant +{ + TIMER_VARIANT_32_BIT, ///< 32-bit timer + TIMER_VARIANT_16_BIT ///< 16-bit timer +} timer_variant_t; + +/** Callback function parameter data */ +typedef struct st_timer_callback_args +{ + /** Placeholder for user data. Set in @ref timer_api_t::open function in @ref timer_cfg_t. */ + void const * p_context; + timer_event_t event; ///< The event can be used to identify what caused the callback. + + /** Most recent capture, only valid if event is TIMER_EVENT_CAPTURE_A or TIMER_EVENT_CAPTURE_B. */ + uint32_t capture; +} timer_callback_args_t; + +/** Timer control block. Allocate an instance specific control block to pass into the timer API calls. + * @par Implemented as + * - gpt_instance_ctrl_t + * - agt_instance_ctrl_t + */ +typedef void timer_ctrl_t; + +/** Possible status values returned by @ref timer_api_t::statusGet. */ +typedef enum e_timer_state +{ + TIMER_STATE_STOPPED = 0, ///< Timer is stopped + TIMER_STATE_COUNTING = 1, ///< Timer is running +} timer_state_t; + +/** Timer operational modes */ +typedef enum e_timer_mode +{ + TIMER_MODE_PERIODIC, ///< Timer restarts after period elapses. + TIMER_MODE_ONE_SHOT, ///< Timer stops after period elapses. + TIMER_MODE_PWM, ///< Timer generates saw-wave PWM output. + TIMER_MODE_ONE_SHOT_PULSE, ///< Saw-wave one-shot pulse mode (fixed buffer operation). + TIMER_MODE_TRIANGLE_WAVE_SYMMETRIC_PWM = 4U, ///< Timer generates symmetric triangle-wave PWM output. + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM = 5U, ///< Timer generates asymmetric triangle-wave PWM output. + + /** + * Timer generates Asymmetric Triangle-wave PWM output. In PWM mode 3, the duty cycle does + * not need to be updated at each tough/crest interrupt. Instead, the trough and crest duty cycle values can be + * set once and only need to be updated when the application needs to change the duty cycle. + */ + TIMER_MODE_TRIANGLE_WAVE_ASYMMETRIC_PWM_MODE3 = 6U, +} timer_mode_t; + +/** Direction of timer count */ +typedef enum e_timer_direction +{ + TIMER_DIRECTION_DOWN = 0, ///< Timer count goes up + TIMER_DIRECTION_UP = 1 ///< Timer count goes down +} timer_direction_t; + +/** PCLK divisors */ +typedef enum e_timer_source_div +{ + TIMER_SOURCE_DIV_1 = 0, ///< Timer clock source divided by 1 + TIMER_SOURCE_DIV_2 = 1, ///< Timer clock source divided by 2 + TIMER_SOURCE_DIV_4 = 2, ///< Timer clock source divided by 4 + TIMER_SOURCE_DIV_8 = 3, ///< Timer clock source divided by 8 + TIMER_SOURCE_DIV_16 = 4, ///< Timer clock source divided by 16 + TIMER_SOURCE_DIV_32 = 5, ///< Timer clock source divided by 32 + TIMER_SOURCE_DIV_64 = 6, ///< Timer clock source divided by 64 + TIMER_SOURCE_DIV_128 = 7, ///< Timer clock source divided by 128 + TIMER_SOURCE_DIV_256 = 8, ///< Timer clock source divided by 256 + TIMER_SOURCE_DIV_512 = 9, ///< Timer clock source divided by 512 + TIMER_SOURCE_DIV_1024 = 10, ///< Timer clock source divided by 1024 +} timer_source_div_t; + +/** Timer information structure to store various information for a timer resource */ +typedef struct st_timer_info +{ + timer_direction_t count_direction; ///< Clock counting direction of the timer. + uint32_t clock_frequency; ///< Clock frequency of the timer counter. + + /** Period in raw timer counts. + * @note For triangle wave PWM modes, the full period is double this value. + */ + uint32_t period_counts; +} timer_info_t; + +/** Current timer status. */ +typedef struct st_timer_status +{ + uint32_t counter; ///< Current counter value + timer_state_t state; ///< Current timer state (running or stopped) +} timer_status_t; + +/** User configuration structure, used in open function */ +typedef struct st_timer_cfg +{ + timer_mode_t mode; ///< Select enumerated value from @ref timer_mode_t + + /* Period in raw timer counts. + * @note For triangle wave PWM modes, enter the period of half the triangle wave, or half the desired period. + */ + uint32_t period_counts; ///< Period in raw timer counts + timer_source_div_t source_div; ///< Source clock divider + uint32_t duty_cycle_counts; ///< Duty cycle in counts + + /** Select a channel corresponding to the channel number of the hardware. */ + uint8_t channel; + uint8_t cycle_end_ipl; ///< Cycle end interrupt priority + IRQn_Type cycle_end_irq; ///< Cycle end interrupt + + /** Callback provided when a timer ISR occurs. Set to NULL for no CPU interrupt. */ + void (* p_callback)(timer_callback_args_t * p_args); + + /** Placeholder for user data. Passed to the user callback in @ref timer_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< Extension parameter for hardware specific settings. +} timer_cfg_t; + +/** Timer API structure. General timer functions implemented at the HAL layer follow this API. */ +typedef struct st_timer_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_GPT_Open() + * - @ref R_AGT_Open() + * + * @param[in] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure must be set by user. + */ + fsp_err_t (* open)(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); + + /** Start the counter. + * @par Implemented as + * - @ref R_GPT_Start() + * - @ref R_AGT_Start() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* start)(timer_ctrl_t * const p_ctrl); + + /** Stop the counter. + * @par Implemented as + * - @ref R_GPT_Stop() + * - @ref R_AGT_Stop() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* stop)(timer_ctrl_t * const p_ctrl); + + /** Reset the counter to the initial value. + * @par Implemented as + * - @ref R_GPT_Reset() + * - @ref R_AGT_Reset() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* reset)(timer_ctrl_t * const p_ctrl); + + /** Enables input capture. + * @par Implemented as + * - @ref R_GPT_Enable() + * - @ref R_AGT_Enable() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* enable)(timer_ctrl_t * const p_ctrl); + + /** Disables input capture. + * @par Implemented as + * - @ref R_GPT_Disable() + * - @ref R_AGT_Disable() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* disable)(timer_ctrl_t * const p_ctrl); + + /** Set the time until the timer expires. See implementation for details of period update timing. + * + * @par Implemented as + * - @ref R_GPT_PeriodSet() + * - @ref R_AGT_PeriodSet() + * + * @note Timer expiration may or may not generate a CPU interrupt based on how the timer is configured in + * @ref timer_api_t::open. + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_period Time until timer should expire. + */ + fsp_err_t (* periodSet)(timer_ctrl_t * const p_ctrl, uint32_t const period); + + /** Sets the number of counts for the pin level to be high. If the timer is counting, the updated duty cycle is + * reflected after the next timer expiration. + * + * @par Implemented as + * - @ref R_GPT_DutyCycleSet() + * - @ref R_AGT_DutyCycleSet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] duty_cycle_counts Time until duty cycle should expire. + * @param[in] pin Which output pin to update. See implementation for details. + */ + fsp_err_t (* dutyCycleSet)(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); + + /** Stores timer information in p_info. + * @par Implemented as + * - @ref R_GPT_InfoGet() + * - @ref R_AGT_InfoGet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_info Collection of information for this timer. + */ + fsp_err_t (* infoGet)(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); + + /** Get the current counter value and timer state and store it in p_status. + * @par Implemented as + * - @ref R_GPT_StatusGet() + * - @ref R_AGT_StatusGet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[out] p_status Current status of this timer. + */ + fsp_err_t (* statusGet)(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); + + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_GPT_CallbackSet() + * - @ref R_AGT_CallbackSet() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(timer_ctrl_t * const p_api_ctrl, void (* p_callback)(timer_callback_args_t *), + void const * const p_context, timer_callback_args_t * const p_callback_memory); + + /** Allows driver to be reconfigured and may reduce power consumption. + * @par Implemented as + * - @ref R_GPT_Close() + * - @ref R_AGT_Close() + * + * @param[in] p_ctrl Control block set in @ref timer_api_t::open call for this timer. + */ + fsp_err_t (* close)(timer_ctrl_t * const p_ctrl); +} timer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_timer_instance +{ + timer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + timer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + timer_api_t const * p_api; ///< Pointer to the API structure for this instance +} timer_instance_t; + +/*******************************************************************************************************************//** + * @} (end defgroup TIMER_API) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_transfer_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_transfer_api.h new file mode 100644 index 00000000..2902df47 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,372 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * Implemented by: + * - @ref DTC + * - @ref DMAC + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + * @par Implemented as + * - dtc_instance_ctrl_t + * - dmac_instance_ctrl_t + */ +typedef void transfer_ctrl_t; + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value +} transfer_size_t; + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * @par Implemented as + * - @ref R_DTC_Open() + * - @ref R_DMAC_Open() + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * @par Implemented as + * - @ref R_DTC_Reconfigure() + * - @ref R_DMAC_Reconfigure() + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * @par Implemented as + * - @ref R_DTC_Reset() + * - @ref R_DMAC_Reset() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source). + * @par Implemented as + * - @ref R_DTC_Enable() + * - @ref R_DMAC_Enable() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * @par Implemented as + * - @ref R_DTC_Disable() + * - @ref R_DMAC_Disable() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. + * @note Not supported for DTC. + * @par Implemented as + * - @ref R_DMAC_SoftwareStart() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source. + * @par Implemented as + * - @ref R_DMAC_SoftwareStop() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * @par Implemented as + * - @ref R_DTC_InfoGet() + * - @ref R_DMAC_InfoGet() + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * @par Implemented as + * - @ref R_DTC_Close() + * - @ref R_DMAC_Close() + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_uart_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_uart_api.h new file mode 100644 index 00000000..8c130dbb --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_uart_api.h @@ -0,0 +1,293 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * Implemented by: + * - @ref SCI_UART + * - @ref SCI_B_UART + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void const * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + * @par Implemented as + * - sci_uart_instance_ctrl_t + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * @par Implemented as + * - @ref R_SCI_UART_Open() + * - @ref R_SCI_B_UART_Open() + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * @par Implemented as + * - @ref R_SCI_UART_Read() + * - @ref R_SCI_B_UART_Read() + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * @par Implemented as + * - @ref R_SCI_UART_Write() + * - @ref R_SCI_B_UART_Write() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * @par Implemented as + * - @ref R_SCI_UART_BaudSet() + * - @ref R_SCI_B_UART_BaudSet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * @par Implemented as + * - @ref R_SCI_UART_InfoGet() + * - @ref R_SCI_B_UART_InfoGet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] baudrate Baud rate in bps. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * @par Implemented as + * - @ref R_SCI_UART_Abort() + * - @ref R_SCI_B_UART_Abort() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - R_SCI_Uart_CallbackSet() + * - R_SCI_B_Uart_CallbackSet() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *), + void const * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * @par Implemented as + * - @ref R_SCI_UART_Close() + * - @ref R_SCI_B_UART_Close() + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * @par Implemented as + * - @ref R_SCI_UART_ReadStop() + * - @ref R_SCI_B_UART_ReadStop() + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_basic_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_basic_api.h new file mode 100644 index 00000000..deb0f741 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_basic_api.h @@ -0,0 +1,726 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup USB_API USB Interface + * @brief Interface for USB functions. + * + * @section USB_API_Summary Summary + * The USB interface provides USB functionality. + * + * The USB interface can be implemented by: + * - @ref USB + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_USB_API_H +#define R_USB_API_H + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include "bsp_api.h" +#include "r_transfer_api.h" +#include "../../src/r_usb_basic/src/driver/inc/r_usb_basic_define.h" + +#if (BSP_CFG_RTOS == 2) + #include "FreeRTOS.h" + #include "task.h" + #include "queue.h" + #include "timers.h" + #include "semphr.h" +#elif (BSP_CFG_RTOS == 1) + #include "tx_api.h" +#endif /* #if (BSP_CFG_RTOS == 2) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* USB Request Type Register */ +#define USB_BREQUEST (0xFF00U) ///< b15-8 + +/* USB Standard request */ +#define USB_GET_STATUS (0x0000U) ///< USB Standard request Get Status +#define USB_CLEAR_FEATURE (0x0100U) ///< USB Standard request Clear Feature +#define USB_REQRESERVED (0x0200U) ///< USB Standard request Reqreserved +#define USB_SET_FEATURE (0x0300U) ///< USB Standard request Set Feature +#define USB_REQRESERVED1 (0x0400U) ///< USB Standard request Reqreserved1 +#define USB_SET_ADDRESS (0x0500U) ///< USB Standard request Set Address +#define USB_GET_DESCRIPTOR (0x0600U) ///< USB Standard request Get Descriptor +#define USB_SET_DESCRIPTOR (0x0700U) ///< USB Standard request Set Descriptor +#define USB_GET_CONFIGURATION (0x0800U) ///< USB Standard request Get Configuration +#define USB_SET_CONFIGURATION (0x0900U) ///< USB Standard request Set Configuration +#define USB_GET_INTERFACE (0x0A00U) ///< USB Standard request Get Interface +#define USB_SET_INTERFACE (0x0B00U) ///< USB Standard request Set Interface +#define USB_SYNCH_FRAME (0x0C00U) ///< USB Standard request Synch Frame + +/* USB_BMREQUESTTYPEDIR 0x0080u(b7) */ +#define USB_HOST_TO_DEV (0x0000U) ///< From host to device. +#define USB_DEV_TO_HOST (0x0080U) ///< From device to host. + +/* USB_BMREQUESTTYPETYPE 0x0060u(b6-5) */ +#define USB_STANDARD (0x0000U) ///< Standard Request +#define USB_CLASS (0x0020U) ///< Class Request +#define USB_VENDOR (0x0040U) ///< Vendor Request + +/* USB_BMREQUESTTYPERECIP 0x001Fu(b4-0) */ +#define USB_DEVICE (0x0000U) ///< Device +#define USB_INTERFACE (0x0001U) ///< Interface +#define USB_ENDPOINT (0x0002U) ///< End Point +#define USB_OTHER (0x0003U) ///< Other + +#define USB_NULL (0x0U) ///< NULL pointer + +#define USB_IP0 (0) ///< USB0 module +#define USB_IP1 (1) ///< USB1 module + +/* USB pipe number */ +#define USB_PIPE0 (0x0U) ///< Pipe Number0 +#define USB_PIPE1 (0x1U) ///< Pipe Number1 +#define USB_PIPE2 (0x2U) ///< Pipe Number2 +#define USB_PIPE3 (0x3U) ///< Pipe Number3 +#define USB_PIPE4 (0x4U) ///< Pipe Number4 +#define USB_PIPE5 (0x5U) ///< Pipe Number5 +#define USB_PIPE6 (0x6U) ///< Pipe Number6 +#define USB_PIPE7 (0x7U) ///< Pipe Number7 +#define USB_PIPE8 (0x8U) ///< Pipe Number8 +#define USB_PIPE9 (0x9U) ///< Pipe Number9 + +#define USB_EP0 (0x0U) ///< End Point Number0 +#define USB_EP1 (0x1U) ///< End Point Number1 +#define USB_EP2 (0x2U) ///< End Point Number2 +#define USB_EP3 (0x3U) ///< End Point Number3 +#define USB_EP4 (0x4U) ///< End Point Number4 +#define USB_EP5 (0x5U) ///< End Point Number5 +#define USB_EP6 (0x6U) ///< End Point Number6 +#define USB_EP7 (0x7U) ///< End Point Number7 +#define USB_EP8 (0x8U) ///< End Point Number8 +#define USB_EP9 (0x9U) ///< End Point Number9 +#define USB_EP10 (0xAU) ///< End Point Number10 +#define USB_EP11 (0xBU) ///< End Point Number11 +#define USB_EP12 (0xCU) ///< End Point Number12 +#define USB_EP13 (0xDU) ///< End Point Number13 +#define USB_EP14 (0xEU) ///< End Point Number14 +#define USB_EP15 (0xFU) ///< End Point Number15 + +/* Endpoint Direction */ +#define USB_EP_DIR (0x0080U) ///< b7: Endpoint Direction +#define USB_EP_DIR_IN (0x0080U) ///< b7: Endpoint Direction In +#define USB_EP_DIR_OUT (0x0000U) ///< b7: Endpoint Direction Out + +/* Descriptor type Define */ +#define USB_DT_DEVICE (0x01U) ///< Device Descriptor +#define USB_DT_CONFIGURATION (0x02U) ///< Configuration Descriptor +#define USB_DT_STRING (0x03U) ///< String Descriptor +#define USB_DT_INTERFACE (0x04U) ///< Interface Descriptor +#define USB_DT_ENDPOINT (0x05U) ///< Endpoint Descriptor +#define USB_DT_DEVICE_QUALIFIER (0x06U) ///< Device Qualifier Descriptor +#define USB_DT_OTHER_SPEED_CONF (0x07U) ///< Other Speed Configuration Descriptor +#define USB_DT_INTERFACE_POWER (0x08U) ///< Interface Power Descriptor +#define USB_DT_OTGDESCRIPTOR (0x09U) ///< OTG Descriptor +#define USB_DT_HUBDESCRIPTOR (0x29U) ///< HUB descriptor + +/* Interface class Define */ +#define USB_IFCLS_NOT (0x00U) ///< Un corresponding Class +#define USB_IFCLS_AUD (0x01U) ///< Audio Class +#define USB_IFCLS_CDC (0x02U) ///< CDC Class +#define USB_IFCLS_CDCC (0x02U) ///< CDC-Control Class +#define USB_IFCLS_HID (0x03U) ///< HID Class +#define USB_IFCLS_PHY (0x05U) ///< Physical Class +#define USB_IFCLS_IMG (0x06U) ///< Image Class +#define USB_IFCLS_PRN (0x07U) ///< Printer Class +#define USB_IFCLS_MAS (0x08U) ///< Mass Storage Class +#define USB_IFCLS_HUB (0x09U) ///< HUB Class +#define USB_IFCLS_CDCD (0x0AU) ///< CDC-Data Class +#define USB_IFCLS_CHIP (0x0BU) ///< Chip/Smart Card Class +#define USB_IFCLS_CNT (0x0CU) ///< Content-Security Class +#define USB_IFCLS_VID (0x0DU) ///< Video Class +#define USB_IFCLS_DIAG (0xDCU) ///< Diagnostic Device +#define USB_IFCLS_WIRE (0xE0U) ///< Wireless Controller +#define USB_IFCLS_APL (0xFEU) ///< Application-Specific +#define USB_IFCLS_VEN (0xFFU) ///< Vendor-Specific Class + +/* Endpoint Descriptor Define */ +#define USB_EP_IN (0x80U) ///< In Endpoint +#define USB_EP_OUT (0x00U) ///< Out Endpoint +#define USB_EP_ISO (0x01U) ///< Isochronous Transfer +#define USB_EP_BULK (0x02U) ///< Bulk Transfer +#define USB_EP_INT (0x03U) ///< Interrupt Transfer + +/* Configuration descriptor bit define */ +#define USB_CF_RESERVED (0x80U) ///< Reserved(set to 1) +#define USB_CF_SELFP (0x40U) ///< Self Powered +#define USB_CF_BUSP (0x00U) ///< Bus Powered +#define USB_CF_RWUPON (0x20U) ///< Remote Wake up ON +#define USB_CF_RWUPOFF (0x00U) ///< Remote Wake up OFF + +/* Descriptor length Define */ +#define USB_DD_BLENGTH (18U) ///< Device Descriptor Length +#define USB_CD_BLENGTH (9U) ///< Configuration Descriptor Length +#define USB_ID_BLENGTH (9U) ///< Interface Descriptor Length +#define USB_ED_BLENGTH (7U) ///< Endpoint Descriptor Length + +/***************************************************************************** + * Typedef definitions + ******************************************************************************/ + +/** USB speed type */ +typedef enum e_usb_speed +{ + USB_SPEED_LS = 0, ///< Low speed operation + USB_SPEED_FS, ///< Full speed operation + USB_SPEED_HS, ///< Hi speed operation +} usb_speed_t; + +/** USB request result */ +typedef enum e_usb_setup_status +{ + USB_SETUP_STATUS_ACK = 0, ///< ACK response + USB_SETUP_STATUS_STALL, ///< STALL response +} usb_setup_status_t; + +/** USB driver status */ +typedef enum e_usb_status +{ + USB_STATUS_POWERED = 0, ///< Powered State + USB_STATUS_DEFAULT, ///< Default State + USB_STATUS_ADDRESS, ///< Address State + USB_STATUS_CONFIGURED, ///< Configured State + USB_STATUS_SUSPEND, ///< Suspend State + USB_STATUS_RESUME, ///< Resume State + USB_STATUS_DETACH, ///< Detach State + USB_STATUS_REQUEST, ///< Request State + USB_STATUS_REQUEST_COMPLETE, ///< Request Complete State + USB_STATUS_READ_COMPLETE, ///< Read Complete State + USB_STATUS_WRITE_COMPLETE, ///< Write Complete State + USB_STATUS_BC, ///< battery Charge State + USB_STATUS_OVERCURRENT, ///< Over Current state + USB_STATUS_NOT_SUPPORT, ///< Device Not Support + USB_STATUS_NONE, ///< None Status + USB_STATUS_MSC_CMD_COMPLETE, ///< MSC_CMD Complete +} usb_status_t; + +/** USB class type */ +typedef enum e_usb_class +{ + USB_CLASS_PCDC = 0x80, ///< PCDC Class + USB_CLASS_PCDCC, ///< PCDCC Class + USB_CLASS_PCDC2, ///< PCDC2 Class + USB_CLASS_PCDCC2, ///< PCDCC2 Class + USB_CLASS_PHID, ///< PHID Class + USB_CLASS_PHID2, ///< PHID2 Class + USB_CLASS_PAUD, ///< PAUD Class + USB_CLASS_PPRN, ///< PPRN Class + USB_CLASS_PVND, ///< PVND Class + USB_CLASS_HCDC, ///< HCDC Class + USB_CLASS_HCDCC, ///< HCDCC Class + USB_CLASS_HHID, ///< HHID Class + USB_CLASS_HVND, ///< HVND Class + USB_CLASS_HMSC, ///< HMSC Class + USB_CLASS_PMSC, ///< PMSC Class + USB_CLASS_HPRN, ///< HPRN Class + USB_CLASS_REQUEST, ///< USB Class Request + USB_CLASS_END ///< USB Class End Code +} usb_class_t; + +/** USB battery charging type */ +typedef enum e_usb_bcport +{ + USB_BCPORT_SDP = 0, ///< SDP port settings + USB_BCPORT_CDP, ///< CDP port settings + USB_BCPORT_DCP, ///< DCP port settings +} usb_bcport_t; + +/** USB status */ +typedef enum e_usb_onoff +{ + USB_OFF = 0, ///< USB Off State + USB_ON, ///< USB On State +} usb_onoff_t; + +/** USB read/write type */ +typedef enum e_usb_transfer +{ + USB_TRANSFER_READ = 0, ///< Data Receive communication + USB_TRANSFER_WRITE, ///< Data transmission communication +} usb_transfer_t; + +/** USB transfer type */ +typedef enum e_usb_transfer_type +{ + USB_TRANSFER_TYPE_BULK = 0, ///< Bulk communication + USB_TRANSFER_TYPE_INT, ///< Interrupt communication + USB_TRANSFER_TYPE_ISO, ///< Isochronous communication +} usb_transfer_type_t; + +/* H/W function type */ +typedef enum e_usb_mode +{ + USB_MODE_HOST = 1, ///< Host mode + USB_MODE_PERI, ///< Peripheral mode +} usb_mode_t; + +typedef enum e_usb_compliancetest_status +{ + USB_COMPLIANCETEST_ATTACH, ///< Device Attach Detection + USB_COMPLIANCETEST_DETACH, ///< Device Detach Detection + USB_COMPLIANCETEST_TPL, ///< TPL device connect + USB_COMPLIANCETEST_NOTTPL, ///< Not TPL device connect + USB_COMPLIANCETEST_HUB, ///< USB Hub connect + USB_COMPLIANCETEST_OVRC, ///< Over current + USB_COMPLIANCETEST_NORES, ///< Response Time out for Control Read Transfer + USB_COMPLIANCETEST_SETUP_ERR, ///< Setup Transaction Error +} usb_compliancetest_status_t; + +typedef enum e_usb_address +{ + USB_ADDRESS1 = 1, + USB_ADDRESS2, + USB_ADDRESS3, + USB_ADDRESS4, + USB_ADDRESS5, +} usb_address_t; + +/** USB control block. Allocate an instance specific control block to pass into the USB API calls. + * @par Implemented as + * - usb_instance_ctrl_t + */ +typedef void usb_ctrl_t; +typedef void (usb_compliance_cb_t)(void *); + +typedef struct st_usb_descriptor +{ + uint8_t * p_device; ///< Pointer to the device descriptor + uint8_t * p_config_f; ///< Pointer to the configuration descriptor for Full-speed + uint8_t * p_config_h; ///< Pointer to the configuration descriptor for Hi-speed + uint8_t * p_qualifier; ///< Pointer to the qualifier descriptor + uint8_t ** p_string; ///< Pointer to the string descriptor table + uint8_t num_string; ///< Num entry String Descriptor +} usb_descriptor_t; + +typedef struct st_usb_setup +{ + uint16_t request_type; ///< USB standard/class request type + uint16_t request_value; ///< Request value + uint16_t request_index; ///< Request index + uint16_t request_length; ///< Request length +} usb_setup_t; + +typedef struct st_usb_pipe +{ + uint8_t endpoint; ///< Endpoint number + uint8_t transfer_type; ///< Transfer type (USB_BULK/USB_INT etc) + uint16_t maxpacketsize; ///< Max packet size +} usb_pipe_t; + +typedef struct st_usb_info +{ + uint8_t class_type; ///< USB device class type + uint8_t speed; ///< USB speed + uint8_t device_status; ///< USB device status + uint8_t bcport; ///< Battery charging information +} usb_info_t; + +typedef struct st_usb_compliance +{ + usb_compliancetest_status_t status; ///< USB Status + uint16_t vid; ///< Vendor ID + uint16_t pid; ///< Product ID +} usb_compliance_t; + +typedef struct st_usb_event_info +{ + uint8_t module_number; ///< USB module number (USB_IP0/USB_IP1) + uint8_t device_address; ///< USB device address + uint8_t pipe; ///< USB pipe number + usb_class_t type; ///< USB device class etc + uint16_t status; ///< USB device state etc + usb_status_t event; ///< USB event + uint32_t data_size; ///< Read data size + usb_setup_t setup; ///< usb_setup_t structure area + void * p_data; ///< Other information + void * p_context; ///< Other Context + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context +} usb_event_info_t; + +#if (BSP_CFG_RTOS == 0) +typedef void (usb_callback_t)(void *); +#endif +#if (BSP_CFG_RTOS == 1) +typedef TX_THREAD * usb_hdl_t; +typedef void (usb_callback_t)(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif +#if (BSP_CFG_RTOS == 2) +typedef TaskHandle_t usb_hdl_t; +typedef void (usb_callback_t)(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif /* #if (BSP_CFG_RTOS == 2) */ + +#if (BSP_CFG_RTOS != 1) +typedef uint32_t ULONG; +#endif + +typedef void (usb_otg_callback_t)(ULONG); + +/** USB configuration. */ +typedef struct st_usb_cfg +{ + usb_mode_t usb_mode; ///< USB_MODE_HOST/USB_MODE_PERI + usb_speed_t usb_speed; ///< USB speed (USB_HS/USB_FS/USB_LS) + uint8_t module_number; ///< USB module number (USB_IP0/USB_IP1) + usb_class_t type; ///< USB device class etc + usb_descriptor_t * p_usb_reg; ///< Pointer to the usb_decriptor_t structure area + usb_compliance_cb_t * usb_complience_cb; + IRQn_Type irq; ///< USBI dedicated interrupt number storage variable. + IRQn_Type irq_r; ///< USBR dedicated interrupt number storage variable. + IRQn_Type irq_d0; ///< FS D0FIFO dedicated interrupt number storage variable. + IRQn_Type irq_d1; ///< FS D1FIFO dedicated interrupt number storage variable. + IRQn_Type hsirq; ///< USBIR dedicated interrupt number storage variable. + IRQn_Type hsirq_d0; ///< HS D0FIFO dedicated interrupt number storage variable. + IRQn_Type hsirq_d1; ///< HS D1FIFO dedicated interrupt number storage variable. + uint8_t ipl; ///< Variable to store the interrupt priority of USBI + uint8_t ipl_r; ///< Variable to store the interrupt priority of USBR. + uint8_t ipl_d0; ///< Variable to store the interrupt priority of FS D0FIFO. + uint8_t ipl_d1; ///< Variable to store the interrupt priority of FS D1FIFO. + uint8_t hsipl; ///< Variable to store the interrupt priority of USBIR. + uint8_t hsipl_d0; ///< Variable to store the interrupt priority of HS D0FIFO. + uint8_t hsipl_d1; ///< Variable to store the interrupt priority of HS D1FIFO. + usb_callback_t * p_usb_apl_callback; ///< Application Callback + void const * p_context; ///< Other Context + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context +} usb_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_usb_api +{ + /** Start the USB module + * @par Implemented as + * - @ref R_USB_Open() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to configuration structure. + */ + fsp_err_t (* open)(usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_cfg); + + /** Stop the USB module + * @par Implemented as + * - @ref R_USB_Close() + * + * @param[in] p_api_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(usb_ctrl_t * const p_api_ctrl); + + /** Request USB data read + * @par Implemented as + * - @ref R_USB_Read() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores read data. + * @param[in] size Read request size. + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* read)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); + + /** Request USB data write + * @par Implemented as + * - @ref R_USB_Write() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores write data. + * @param[in] size Read request size. + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* write)(usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); + + /** Stop USB data read/write processing + * @par Implemented as + * - @ref R_USB_Stop() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] direction Receive (USB_TRANSFER_READ) or send (USB_TRANSFER_WRITE). + * @param[in] destination In Host mode, it represents the device address, and in Peripheral mode, it represents the device class. + */ + fsp_err_t (* stop)(usb_ctrl_t * const p_api_ctrl, usb_transfer_t direction, uint8_t destination); + + /** Request suspend + * @par Implemented as + * - @ref R_USB_Suspend() + * + * @param[in] p_api_ctrl Pointer to control structure. + */ + fsp_err_t (* suspend)(usb_ctrl_t * const p_api_ctrl); + + /** Request resume + * @par Implemented as + * - @ref R_USB_Resume() + * + * @param[in] p_api_ctrl Pointer to control structure. + */ + fsp_err_t (* resume)(usb_ctrl_t * const p_api_ctrl); + + /** Sets VBUS supply start/stop. + * @par Implemented as + * - @ref R_USB_VbusSet() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] state VBUS supply start/stop specification + */ + fsp_err_t (* vbusSet)(usb_ctrl_t * const p_api_ctrl, uint16_t state); + + /** Get information on USB device. + * @par Implemented as + * - @ref R_USB_InfoGet() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_info_t structure area. + * @param[in] destination Device address for Host. + */ + fsp_err_t (* infoGet)(usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uint8_t destination); + + /** Request data read from specified pipe + * @par Implemented as + * - @ref R_USB_PipeRead() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores read data. + * @param[in] size Read request size. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeRead)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + + /** Request data write to specified pipe + * @par Implemented as + * - @ref R_USB_PipeWrite() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_buf Pointer to area that stores write data. + * @param[in] size Read request size. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeWrite)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + + /** Stop USB data read/write processing to specified pipe + * @par Implemented as + * - @ref R_USB_PipeStop() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeStop)(usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number); + + /** Get pipe number + * @par Implemented as + * - @ref R_USB_UsedPipesGet() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_pipe Pointer to area that stores the selected pipe number (bit map information). + * @param[in] destination Device address for Host. + */ + fsp_err_t (* usedPipesGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * p_pipe, uint8_t destination); + + /** Get pipe information + * @par Implemented as + * - @ref R_USB_PipeInfoGet() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] p_info Pointer to usb_pipe_t structure area. + * @param[in] pipe_number Pipe Number. + */ + fsp_err_t (* pipeInfoGet)(usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); + + /** Return USB-related completed events (OS less only) + * @par Implemented as + * - @ref R_USB_EventGet() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[out] event Pointer to event. + */ + fsp_err_t (* eventGet)(usb_ctrl_t * const p_api_ctrl, usb_status_t * event); + + /** Register a callback function to be called upon completion of a USB related event. (RTOS only) + * @par Implemented as + * - @ref R_USB_Callback() + * + * @param[in] p_callback Pointer to Callback function. + */ + fsp_err_t (* callback)(usb_callback_t * p_callback); + + /** Pull-up enable/disable setting of D+/D- line. + * @par Implemented as + * - @ref R_USB_PullUp() + * + * @param[in] p_api_ctrl Pointer to control structure. + * @param[in] state Pull-up enable/disable setting. + */ + fsp_err_t (* pullUp)(usb_ctrl_t * const p_api_ctrl, uint8_t state); + + /** Performs settings and transmission processing when transmitting a setup packet. + * @par Implemented as + * - @ref R_USB_HostControlTransfer() + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] p_setup Setup packet information. + * @param[in] p_buf Transfer area information. + * @param[in] device_address Device address information. + */ + fsp_err_t (* hostControlTransfer)(usb_ctrl_t * const p_api_ctrl, usb_setup_t * p_setup, uint8_t * p_buf, + uint8_t device_address); + + /** Receives data sent by control transfer. + * @par Implemented as + * - @ref R_USB_PeriControlDataGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] p_buf Data reception area information. + * @param[in] size Data reception size information. + */ + fsp_err_t (* periControlDataGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + + /** Performs transfer processing for control transfer. + * @par Implemented as + * - @ref R_USB_PeriControlDataSet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] p_buf Area information for data transfer. + * @param[in] size Transfer size information. + */ + fsp_err_t (* periControlDataSet)(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + + /** Set the response to the setup packet. + * @par Implemented as + * - @ref R_USB_PeriControlStatusSet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] status USB port startup information. + */ + fsp_err_t (* periControlStatusSet)(usb_ctrl_t * const p_api_ctrl, usb_setup_status_t status); + + /** Sends a remote wake-up signal to the connected Host. + * @par Implemented as + * - @ref R_USB_RemoteWakeup() + * + * @param[in] p_api_ctrl USB control structure. + */ + fsp_err_t (* remoteWakeup)(usb_ctrl_t * const p_api_ctrl); + + /** This API gets the module number. + * @par Implemented as + * - @ref R_USB_ModuleNumberGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] module_number Module number to get. + */ + fsp_err_t (* moduleNumberGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * module_number); + + /** This API gets the module number. + * @par Implemented as + * - @ref R_USB_ClassTypeGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] class_type Class type to get. + */ + fsp_err_t (* classTypeGet)(usb_ctrl_t * const p_api_ctrl, usb_class_t * class_type); + + /** This API gets the device address. + * @par Implemented as + * - @ref R_USB_DeviceAddressGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] device_address Device address to get. + */ + fsp_err_t (* deviceAddressGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * device_address); + + /** This API gets the pipe number. + * @par Implemented as + * - @ref R_USB_PipeNumberGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] pipe_number Pipe number to get. + */ + fsp_err_t (* pipeNumberGet)(usb_ctrl_t * const p_api_ctrl, uint8_t * pipe_number); + + /** This API gets the state of the device. + * @par Implemented as + * - @ref R_USB_DeviceStateGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] state Device state to get. + */ + fsp_err_t (* deviceStateGet)(usb_ctrl_t * const p_api_ctrl, uint16_t * state); + + /** This API gets the data size. + * @par Implemented as + * - @ref R_USB_DataSizeGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] data_size Data size to get. + */ + fsp_err_t (* dataSizeGet)(usb_ctrl_t * const p_api_ctrl, uint32_t * data_size); + + /** This API gets the setup type. + * @par Implemented as + * - @ref R_USB_SetupGet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[out] setup Setup type to get. + */ + fsp_err_t (* setupGet)(usb_ctrl_t * const p_api_ctrl, usb_setup_t * setup); + + /** This API sets the callback function for OTG. + * @par Implemented as + * - @ref R_USB_OtgCallbackSet() + * + * @param[in] p_api_ctrl USB control structure. + * @param[in] p_callback Pointer to the callback function for OTG. + */ + fsp_err_t (* otgCallbackSet)(usb_ctrl_t * const p_api_ctrl, usb_otg_callback_t * p_callback); + + /** This API starts SRP processing for OTG. + * @par Implemented as + * - @ref R_USB_OtgSRP() + * + * @param[in] p_api_ctrl USB control structure. + */ + fsp_err_t (* otgSRP)(usb_ctrl_t * const p_api_ctrl); +} usb_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_usb_instance +{ + usb_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + usb_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + usb_api_t const * p_api; ///< Pointer to the API structure for this instance +} usb_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup USB_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_pcdc_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_pcdc_api.h new file mode 100644 index 00000000..3dde6338 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_usb_pcdc_api.h @@ -0,0 +1,108 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup USB_PCDC_API USB PCDC Interface + * @brief Interface for USB PCDC functions. + * + * @section USB_PCDC_API_Summary Summary + * The USB PCDC interface provides USB PCDC functionality. + * + * The USB PCDC interface can be implemented by: + * - @ref USB_PCDC + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_USB_PCDC_API_H +#define R_USB_PCDC_API_H + +/****************************************************************************** + * Includes , "Project Includes" + ******************************************************************************/ +#include "r_usb_basic_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* CDC Class Requests IDs*/ +#define USB_PCDC_SET_LINE_CODING (0x2000U) ///< Set Line Coding +#define USB_PCDC_GET_LINE_CODING (0x2100U) ///< Get Line Coding +#define USB_PCDC_SET_CONTROL_LINE_STATE (0x2200U) ///< Control Line State + +#define USB_PCDC_SERIAL_STATE (0x20) ///< Serial State Code + +#define USB_PCDC_SETUP_TBL_BSIZE (10U) ///< Setup packet table size (uint16_t * 5) + +/******************************************************************************* + * Typedef definitions + *******************************************************************************/ + +/** Virtual UART signal state */ +typedef struct +{ + uint16_t b_rx_carrier : 1; ///< DCD signal + uint16_t b_tx_carrier : 1; ///< DSR signal + uint16_t b_break : 1; ///< Break signal + uint16_t b_ring_signal : 1; ///< Ring signal + uint16_t b_framing : 1; ///< Framing error + uint16_t b_parity : 1; ///< Parity error + uint16_t b_over_run : 1; ///< Overrun error + uint16_t rsv : 9; ///< Reserved +} usb_serial_state_bitmap_t; + +/** Class Notification Serial State */ +typedef union +{ + uint32_t word; ///< Word Access + usb_serial_state_bitmap_t bit; ///< Bit Access +} usb_sci_serialstate_t; + +/** Virtual UART communication settings */ +typedef struct +{ + uint32_t dw_dte_rate; ///< Bitrate + uint8_t b_char_format; ///< Stop bits + uint8_t b_parity_type; ///< Parity + uint8_t b_data_bits; ///< Data bits + uint8_t rsv; ///< Reserved +} usb_pcdc_linecoding_t; + +/** Virtual UART control line state */ +typedef struct +{ + uint16_t bdtr : 1; ///< DTR + uint16_t brts : 1; ///< RTS + uint16_t rsv : 14; ///< Reserved +} usb_pcdc_ctrllinestate_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_PCDC_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup USB_PCDC_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_wdt_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_wdt_api.h new file mode 100644 index 00000000..0d320559 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/api/r_wdt_api.h @@ -0,0 +1,253 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup WDT_API WDT Interface + * @brief Interface for watch dog timer functions. + * + * @section WDT_API_Summary Summary + * The WDT interface for the Watchdog Timer (WDT) peripheral provides watchdog functionality including resetting the + * device or generating an interrupt. + * + * The watchdog timer interface can be implemented by: + * - @ref WDT + * - @ref IWDT + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDT_API_H +#define R_WDT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** WDT time-out periods. */ +typedef enum e_wdt_timeout +{ + WDT_TIMEOUT_128 = 0, ///< 128 clock cycles + WDT_TIMEOUT_512, ///< 512 clock cycles + WDT_TIMEOUT_1024, ///< 1024 clock cycles + WDT_TIMEOUT_2048, ///< 2048 clock cycles + WDT_TIMEOUT_4096, ///< 4096 clock cycles + WDT_TIMEOUT_8192, ///< 8192 clock cycles + WDT_TIMEOUT_16384, ///< 16384 clock cycles +} wdt_timeout_t; + +/** WDT clock division ratio. */ +typedef enum e_wdt_clock_division +{ + WDT_CLOCK_DIVISION_1 = 0, ///< CLK/1 + WDT_CLOCK_DIVISION_4 = 1, ///< CLK/4 + WDT_CLOCK_DIVISION_16 = 2, ///< CLK/16 + WDT_CLOCK_DIVISION_32 = 3, ///< CLK/32 + WDT_CLOCK_DIVISION_64 = 4, ///< CLK/64 + WDT_CLOCK_DIVISION_128 = 15, ///< CLK/128 + WDT_CLOCK_DIVISION_256 = 5, ///< CLK/256 + WDT_CLOCK_DIVISION_512 = 6, ///< CLK/512 + WDT_CLOCK_DIVISION_2048 = 7, ///< CLK/2048 + WDT_CLOCK_DIVISION_8192 = 8, ///< CLK/8192 +} wdt_clock_division_t; + +/** WDT refresh permitted period window start position. */ +typedef enum e_wdt_window_start +{ + WDT_WINDOW_START_25 = 0, ///< Start position = 25% + WDT_WINDOW_START_50 = 1, ///< Start position = 50% + WDT_WINDOW_START_75 = 2, ///< Start position = 75% + WDT_WINDOW_START_100 = 3, ///< Start position = 100% +} wdt_window_start_t; + +/** WDT refresh permitted period window end position. */ +typedef enum e_wdt_window_end +{ + WDT_WINDOW_END_75 = 0, ///< End position = 75% + WDT_WINDOW_END_50 = 1, ///< End position = 50% + WDT_WINDOW_END_25 = 2, ///< End position = 25% + WDT_WINDOW_END_0 = 3, ///< End position = 0% +} wdt_window_end_t; + +/** WDT Counter underflow and refresh error control. */ +typedef enum e_wdt_reset_control +{ + WDT_RESET_CONTROL_NMI = 0, ///< NMI request when counter underflows. + WDT_RESET_CONTROL_RESET = 1, ///< Reset request when counter underflows. +} wdt_reset_control_t; + +/** WDT Counter operation in sleep mode. */ +typedef enum e_wdt_stop_control +{ + WDT_STOP_CONTROL_DISABLE = 0, ///< Count will not stop when device enters sleep mode. + WDT_STOP_CONTROL_ENABLE = 1, ///< Count will automatically stop when device enters sleep mode. +} wdt_stop_control_t; + +/** WDT status */ +typedef enum e_wdt_status +{ + WDT_STATUS_NO_ERROR = 0, ///< No status flags set. + WDT_STATUS_UNDERFLOW_ERROR = 1, ///< Underflow flag set. + WDT_STATUS_REFRESH_ERROR = 2, ///< Refresh error flag set. Refresh outside of permitted window. + WDT_STATUS_UNDERFLOW_AND_REFRESH_ERROR = 3, ///< Underflow and refresh error flags set. +} wdt_status_t; + +/** Callback function parameter data */ +typedef struct st_wdt_callback_args +{ + void const * p_context; ///< Placeholder for user data. Set in @ref wdt_api_t::open function in @ref wdt_cfg_t. +} wdt_callback_args_t; + +/** WDT timeout data. Used to return frequency of WDT clock and timeout period */ +typedef struct st_wdt_timeout_values +{ + uint32_t clock_frequency_hz; ///< Frequency of watchdog clock after divider. + uint32_t timeout_clocks; ///< Timeout period in units of watchdog clock ticks. +} wdt_timeout_values_t; + +/** WDT control block. Allocate an instance specific control block to pass into the WDT API calls. + * @par Implemented as + * - wdt_instance_ctrl_t + * - iwdt_instance_ctrl_t + */ +typedef void wdt_ctrl_t; + +/** WDT configuration parameters. */ +typedef struct st_wdt_cfg +{ + wdt_timeout_t timeout; ///< Timeout period. + wdt_clock_division_t clock_division; ///< Clock divider. + wdt_window_start_t window_start; ///< Refresh permitted window start position. + wdt_window_end_t window_end; ///< Refresh permitted window end position. + wdt_reset_control_t reset_control; ///< Select NMI or reset generated on underflow. + wdt_stop_control_t stop_control; ///< Select whether counter operates in sleep mode. + void (* p_callback)(wdt_callback_args_t * p_args); ///< Callback provided when a WDT NMI ISR occurs. + + /** Placeholder for user data. Passed to the user callback in wdt_callback_args_t. */ + void const * p_context; + void const * p_extend; ///< Placeholder for user extension. +} wdt_cfg_t; + +/** WDT functions implemented at the HAL layer will follow this API. */ +typedef struct st_wdt_api +{ + /** Initialize the WDT in register start mode. In auto-start mode with NMI output it registers the NMI callback. + * @par Implemented as + * - @ref R_WDT_Open() + * - @ref R_IWDT_Open() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + fsp_err_t (* open)(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + + /** Refresh the watchdog timer. + * @par Implemented as + * - @ref R_WDT_Refresh() + * - @ref R_IWDT_Refresh() + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* refresh)(wdt_ctrl_t * const p_ctrl); + + /** Read the status of the WDT. + * @par Implemented as + * - @ref R_WDT_StatusGet() + * - @ref R_IWDT_StatusGet() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_status Pointer to variable to return status information through. + */ + fsp_err_t (* statusGet)(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + + /** Clear the status flags of the WDT. + * @par Implemented as + * - @ref R_WDT_StatusClear() + * - @ref R_IWDT_StatusClear() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] status Status condition(s) to clear. + */ + fsp_err_t (* statusClear)(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + + /** Read the current WDT counter value. + * @par Implemented as + * - @ref R_WDT_CounterGet() + * - @ref R_IWDT_CounterGet() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_count Pointer to variable to return current WDT counter value. + */ + fsp_err_t (* counterGet)(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + + /** Read the watchdog timeout values. + * @par Implemented as + * - @ref R_WDT_TimeoutGet() + * - @ref R_IWDT_TimeoutGet() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[out] p_timeout Pointer to structure to return timeout values. + */ + fsp_err_t (* timeoutGet)(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + + /** Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_WDT_CallbackSet() + * + * @param[in] p_ctrl Pointer to the WDT control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(wdt_ctrl_t * const p_api_ctrl, void (* p_callback)(wdt_callback_args_t *), + void const * const p_context, wdt_callback_args_t * const p_callback_memory); +} wdt_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_wdt_instance +{ + wdt_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + wdt_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + wdt_api_t const * p_api; ///< Pointer to the API structure for this instance +} wdt_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end addtogroup WDT_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_common_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_common_api.h new file mode 100644 index 00000000..ee0f4dec --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_common_api.h @@ -0,0 +1,377 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_features.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_features.h new file mode 100644 index 00000000..70ee51cd --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_features.h @@ -0,0 +1,300 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CFLASH = 0, ///< Code Flash + FSP_IP_DFLASH = 1, ///< Data Flash + FSP_IP_RAM = 2, ///< RAM + FSP_IP_LVD = 3, ///< Low Voltage Detection + FSP_IP_CGC = 3, ///< Clock Generation Circuit + FSP_IP_LPM = 3, ///< Low Power Modes + FSP_IP_FCU = 4, ///< Flash Control Unit + FSP_IP_ICU = 6, ///< Interrupt Control Unit + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_DTC = 8, ///< Data Transfer Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_PFS = 10, ///< Pin Function Select + FSP_IP_ELC = 11, ///< Event Link Controller + FSP_IP_MPU = 13, ///< Memory Protection Unit + FSP_IP_MSTP = 14, ///< Module Stop + FSP_IP_MMF = 15, ///< Memory Mirror Function + FSP_IP_KEY = 16, ///< Key Interrupt Function + FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit + FSP_IP_DOC = 18, ///< Data Operation Circuit + FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator + FSP_IP_SCI = 20, ///< Serial Communications Interface + FSP_IP_IIC = 21, ///< I2C Bus Interface + FSP_IP_SPI = 22, ///< Serial Peripheral Interface + FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit + FSP_IP_SCE = 24, ///< Secure Cryptographic Engine + FSP_IP_SLCDC = 25, ///< Segment LCD Controller + FSP_IP_AES = 26, ///< Advanced Encryption Standard + FSP_IP_TRNG = 27, ///< True Random Number Generator + FSP_IP_FCACHE = 30, ///< Flash Cache + FSP_IP_SRAM = 31, ///< SRAM + FSP_IP_ADC = 32, ///< A/D Converter + FSP_IP_DAC = 33, ///< 12-Bit D/A Converter + FSP_IP_TSN = 34, ///< Temperature Sensor + FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit + FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator + FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator + FSP_IP_OPAMP = 38, ///< Operational Amplifier + FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter + FSP_IP_RTC = 40, ///< Real Time Clock + FSP_IP_WDT = 41, ///< Watch Dog Timer + FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer + FSP_IP_GPT = 43, ///< General PWM Timer + FSP_IP_POEG = 44, ///< Port Output Enable for GPT + FSP_IP_OPS = 45, ///< Output Phase Switch + FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer + FSP_IP_CAN = 48, ///< Controller Area Network + FSP_IP_IRDA = 49, ///< Infrared Data Association + FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface + FSP_IP_USBFS = 51, ///< USB Full Speed + FSP_IP_SDHI = 52, ///< SD/MMC Host Interface + FSP_IP_SRC = 53, ///< Sampling Rate Converter + FSP_IP_SSI = 54, ///< Serial Sound Interface + FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface + FSP_IP_ETHER = 64, ///< Ethernet MAC Controller + FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller + FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller + FSP_IP_PDC = 66, ///< Parallel Data Capture Unit + FSP_IP_GLCDC = 67, ///< Graphics LCD Controller + FSP_IP_DRW = 68, ///< 2D Drawing Engine + FSP_IP_JPEG = 69, ///< JPEG + FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter + FSP_IP_USBHS = 71, ///< USB High Speed + FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface + FSP_IP_CEC = 73, ///< HDMI CEC + FSP_IP_TFU = 74, ///< Trigonometric Function Unit + FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator + FSP_IP_CANFD = 76, ///< CAN-FD +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH + FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH + FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END + FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B + FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A + FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B + FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ + FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ + FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A + FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B + FSP_SIGNAL_AGT_INT, ///< AGT INT + FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR + FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END + FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW + FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR + FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX + FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX + FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX + FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX + FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP + FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST + FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 + FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 + FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD + FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT + FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT + FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT + FSP_SIGNAL_CTSU_END = 0, ///< CTSU END + FSP_SIGNAL_CTSU_READ, ///< CTSU READ + FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE + FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI + FSP_SIGNAL_DALI_CLI, ///< DALI CLI + FSP_SIGNAL_DALI_SDI, ///< DALI SDI + FSP_SIGNAL_DALI_BPI, ///< DALI BPI + FSP_SIGNAL_DALI_FEI, ///< DALI FEI + FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI + FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT + FSP_SIGNAL_DOC_INT = 0, ///< DOC INT + FSP_SIGNAL_DRW_INT = 0, ///< DRW INT + FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE + FSP_SIGNAL_DTC_END, ///< DTC END + FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT + FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 + FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 + FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS + FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT + FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT + FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL + FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE + FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL + FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE + FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL + FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE + FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL + FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE + FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL + FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE + FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL + FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE + FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR + FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI + FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT + FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 + FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 + FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A + FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B + FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C + FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D + FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E + FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F + FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW + FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW + FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A + FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B + FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE + FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 + FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 + FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 + FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 + FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 + FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 + FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 + FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 + FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 + FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 + FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 + FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 + FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 + FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 + FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 + FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 + FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL + FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI + FSP_SIGNAL_IIC_RXI, ///< IIC RXI + FSP_SIGNAL_IIC_TEI, ///< IIC TEI + FSP_SIGNAL_IIC_TXI, ///< IIC TXI + FSP_SIGNAL_IIC_WUI, ///< IIC WUI + FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 + FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 + FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 + FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 + FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B + FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C + FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D + FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E + FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW + FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI + FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI + FSP_SIGNAL_KEY_INT = 0, ///< KEY INT + FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END + FSP_SIGNAL_PDC_INT, ///< PDC INT + FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY + FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT + FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT + FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM + FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD + FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY + FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY + FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY + FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG + FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY + FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 + FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 + FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK + FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY + FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 + FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 + FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 + FSP_SIGNAL_SCI_AM = 0, ///< SCI AM + FSP_SIGNAL_SCI_ERI, ///< SCI ERI + FSP_SIGNAL_SCI_RXI, ///< SCI RXI + FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI + FSP_SIGNAL_SCI_TEI, ///< SCI TEI + FSP_SIGNAL_SCI_TXI, ///< SCI TXI + FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI + FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND + FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND + FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS + FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD + FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ + FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO + FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI + FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE + FSP_SIGNAL_SPI_RXI, ///< SPI RXI + FSP_SIGNAL_SPI_TEI, ///< SPI TEI + FSP_SIGNAL_SPI_TXI, ///< SPI TXI + FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END + FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY + FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL + FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW + FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW + FSP_SIGNAL_SSI_INT = 0, ///< SSI INT + FSP_SIGNAL_SSI_RXI, ///< SSI RXI + FSP_SIGNAL_SSI_TXI, ///< SSI TXI + FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI + FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ + FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 + FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 + FSP_SIGNAL_USB_INT, ///< USB INT + FSP_SIGNAL_USB_RESUME, ///< USB RESUME + FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME + FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_version.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_version.h new file mode 100644 index 00000000..c5b941f4 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/fsp_version.h @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_VERSION_H + #define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ + #include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + + #ifdef __cplusplus +extern "C" { + #endif + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ + #define FSP_VERSION_MAJOR (4U) + +/** FSP pack minor version. */ + #define FSP_VERSION_MINOR (0U) + +/** FSP pack patch version. */ + #define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ + #define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ + #define FSP_VERSION_STRING ("4.0.0") + +/** Unique FSP version ID. */ + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.0.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** + * Code version parameters, little endian order. + */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_adc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_adc.h new file mode 100644 index 00000000..82fc564d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_adc.h @@ -0,0 +1,359 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_ADC_H +#define R_ADC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include + +/* Fixed width integer support. */ +#include + +/* bool support */ +#include +#include "bsp_api.h" +#include "r_adc_cfg.h" +#include "r_adc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup ADC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Typical values that can be used to modify the sample states. + * The minimum sample state count value is either 6 or 7 depending on the clock ratios. + * It is fixed to 7 based on the fact that at the lowest ADC conversion clock supported (1 MHz) + * this extra state will lead to at worst a "1 microsecond" increase in conversion time. + * At 60 MHz the extra sample state will add 16.7 ns to the conversion time. + */ +#define ADC_SAMPLE_STATE_COUNT_MIN (7U) +#define ADC_SAMPLE_STATE_COUNT_MAX (255U) + +/* Typical values that can be used for the sample and hold counts for the channels 0-2*/ +/* Minimum sample and hold states */ +#define ADC_SAMPLE_STATE_HOLD_COUNT_MIN (4U) + +/* Default sample and hold states */ +#define ADC_SAMPLE_STATE_HOLD_COUNT_DEFAULT (24U) + +/** For ADC Scan configuration adc_channel_cfg_t::scan_mask, adc_channel_cfg_t::scan_mask_group_b, + * adc_channel_cfg_t::add_mask and adc_channel_cfg_t::sample_hold_mask. + * Use bitwise OR to combine these masks for desired channels and sensors. */ +typedef enum e_adc_mask +{ + ADC_MASK_OFF = (0U), ///< No channels selected + ADC_MASK_CHANNEL_0 = (1U << 0U), ///< Channel 0 mask + ADC_MASK_CHANNEL_1 = (1U << 1U), ///< Channel 1 mask + ADC_MASK_CHANNEL_2 = (1U << 2U), ///< Channel 2 mask + ADC_MASK_CHANNEL_3 = (1U << 3U), ///< Channel 3 mask + ADC_MASK_CHANNEL_4 = (1U << 4U), ///< Channel 4 mask + ADC_MASK_CHANNEL_5 = (1U << 5U), ///< Channel 5 mask + ADC_MASK_CHANNEL_6 = (1U << 6U), ///< Channel 6 mask + ADC_MASK_CHANNEL_7 = (1U << 7U), ///< Channel 7 mask + ADC_MASK_CHANNEL_8 = (1U << 8U), ///< Channel 8 mask + ADC_MASK_CHANNEL_9 = (1U << 9U), ///< Channel 9 mask + ADC_MASK_CHANNEL_10 = (1U << 10U), ///< Channel 10 mask + ADC_MASK_CHANNEL_11 = (1U << 11U), ///< Channel 11 mask + ADC_MASK_CHANNEL_12 = (1U << 12U), ///< Channel 12 mask + ADC_MASK_CHANNEL_13 = (1U << 13U), ///< Channel 13 mask + ADC_MASK_CHANNEL_14 = (1U << 14U), ///< Channel 14 mask + ADC_MASK_CHANNEL_15 = (1U << 15U), ///< Channel 15 mask + ADC_MASK_CHANNEL_16 = (1U << 16U), ///< Channel 16 mask + ADC_MASK_CHANNEL_17 = (1U << 17U), ///< Channel 17 mask + ADC_MASK_CHANNEL_18 = (1U << 18U), ///< Channel 18 mask + ADC_MASK_CHANNEL_19 = (1U << 19U), ///< Channel 19 mask + ADC_MASK_CHANNEL_20 = (1U << 20U), ///< Channel 20 mask + ADC_MASK_CHANNEL_21 = (1U << 21U), ///< Channel 21 mask + ADC_MASK_CHANNEL_22 = (1U << 22U), ///< Channel 22 mask + ADC_MASK_CHANNEL_23 = (1U << 23U), ///< Channel 23 mask + ADC_MASK_CHANNEL_24 = (1U << 24U), ///< Channel 24 mask + ADC_MASK_CHANNEL_25 = (1U << 25U), ///< Channel 25 mask + ADC_MASK_CHANNEL_26 = (1U << 26U), ///< Channel 26 mask + ADC_MASK_CHANNEL_27 = (1U << 27U), ///< Channel 27 mask + ADC_MASK_TEMPERATURE = (1U << 28UL), ///< Temperature sensor channel mask + ADC_MASK_VOLT = (1U << 29UL), ///< Voltage reference channel mask + ADC_MASK_SENSORS = (ADC_MASK_TEMPERATURE | ADC_MASK_VOLT), ///< All sensor channel mask +} adc_mask_t; + +/** ADC data sample addition and averaging options */ +typedef enum e_adc_add +{ + ADC_ADD_OFF = 0, ///< Addition turned off for channels/sensors + ADC_ADD_TWO = 1, ///< Add two samples + ADC_ADD_THREE = 2, ///< Add three samples + ADC_ADD_FOUR = 3, ///< Add four samples + ADC_ADD_SIXTEEN = 5, ///< Add sixteen samples + ADC_ADD_AVERAGE_TWO = 0x81, ///< Average two samples + ADC_ADD_AVERAGE_FOUR = 0x83, ///< Average four samples + ADC_ADD_AVERAGE_EIGHT = 0x84, ///< Average eight samples + ADC_ADD_AVERAGE_SIXTEEN = 0x85, ///< Add sixteen samples +} adc_add_t; + +/** ADC clear after read definitions */ +typedef enum e_adc_clear +{ + ADC_CLEAR_AFTER_READ_OFF = 0, ///< Clear after read off + ADC_CLEAR_AFTER_READ_ON = 1 ///< Clear after read on +} adc_clear_t; + +/* VREF configuration options, not all options are available on all MCUs. If the MCU does not have VREFAMPCNT or + * ADHVREFCNT. */ +typedef enum e_adc_vref_control +{ + /* Available selections on MCUs with VREFAMPCNT. + * Reference Table 32.12 "VREFADC output voltage control list" in the RA2A1 manual R01UH0888EJ0100.*/ + + ADC_VREF_CONTROL_VREFH = 0, ///< VREFAMPCNT reset value. VREFADC Output voltage is Hi-Z + ADC_VREF_CONTROL_1_5V_OUTPUT = 25, ///< BGR turn ON. VREFADC Output voltage is 1.5 V + ADC_VREF_CONTROL_2_0V_OUTPUT = 29, ///< BGR turn ON. VREFADC Output voltage is 2.0 V + ADC_VREF_CONTROL_2_5V_OUTPUT = 31, ///< BGR turn ON. VREFADC Output voltage is 2.5 V + + /* Available selections on MCUs with ADHVREFCNT. + * Reference Section 35.2.31 "A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT)" + * in the RA4M1 manual R01UH0887EJ0100.*/ + + ADC_VREF_CONTROL_AVCC0_AVSS0 = 0x0, ///< High potential is AVCC0, low potential is AVSS0 + ADC_VREF_CONTROL_VREFH0_AVSS0 = 0x1, ///< High potential is VREFH0, low potential is AVSS0 + + /** High potential is internal reference voltage, low potential is AVSS0. When the high potential is set to the + * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */ + ADC_VREF_CONTROL_IVREF_AVSS0 = 0x2, + ADC_VREF_CONTROL_AVCC0_VREFL0 = 0x10, ///< High potential is AVCC0, low potential is VREFL0 + ADC_VREF_CONTROL_VREFH0_VREFL0 = 0x11, ///< High potential is VREFH0, low potential is VREFL0 + + /** High potential is internal reference voltage, low potential is VREFL0. When the high potential is set to the + * internal reference voltage, wait 5 us after R_ADC_Open() to start an ADC measurement. */ + ADC_VREF_CONTROL_IVREF_VREFL0 = 0x12, +} adc_vref_control_t; + +/** ADC sample state registers */ +typedef enum e_adc_sample_state_reg +{ + ADC_SAMPLE_STATE_CHANNEL_0 = 0, ///< Sample state register channel 0 + ADC_SAMPLE_STATE_CHANNEL_1, ///< Sample state register channel 1 + ADC_SAMPLE_STATE_CHANNEL_2, ///< Sample state register channel 2 + ADC_SAMPLE_STATE_CHANNEL_3, ///< Sample state register channel 3 + ADC_SAMPLE_STATE_CHANNEL_4, ///< Sample state register channel 4 + ADC_SAMPLE_STATE_CHANNEL_5, ///< Sample state register channel 5 + ADC_SAMPLE_STATE_CHANNEL_6, ///< Sample state register channel 6 + ADC_SAMPLE_STATE_CHANNEL_7, ///< Sample state register channel 7 + ADC_SAMPLE_STATE_CHANNEL_8, ///< Sample state register channel 8 + ADC_SAMPLE_STATE_CHANNEL_9, ///< Sample state register channel 9 + ADC_SAMPLE_STATE_CHANNEL_10, ///< Sample state register channel 10 + ADC_SAMPLE_STATE_CHANNEL_11, ///< Sample state register channel 11 + ADC_SAMPLE_STATE_CHANNEL_12, ///< Sample state register channel 12 + ADC_SAMPLE_STATE_CHANNEL_13, ///< Sample state register channel 13 + ADC_SAMPLE_STATE_CHANNEL_14, ///< Sample state register channel 14 + ADC_SAMPLE_STATE_CHANNEL_15, ///< Sample state register channel 15 + ADC_SAMPLE_STATE_CHANNEL_16_TO_31 = -3, ///< Sample state register channel 16 to 31 +} adc_sample_state_reg_t; + +/** ADC comparison settings */ +typedef enum e_adc_compare_cfg +{ + ADC_COMPARE_CFG_EVENT_OUTPUT_OR = 0, + ADC_COMPARE_CFG_EVENT_OUTPUT_XOR = 1, + ADC_COMPARE_CFG_EVENT_OUTPUT_AND = 2, + ADC_COMPARE_CFG_A_ENABLE = R_ADC0_ADCMPCR_CMPAE_Msk | R_ADC0_ADCMPCR_CMPAIE_Msk, + ADC_COMPARE_CFG_B_ENABLE = R_ADC0_ADCMPCR_CMPBE_Msk | R_ADC0_ADCMPCR_CMPBIE_Msk, + ADC_COMPARE_CFG_WINDOW_ENABLE = R_ADC0_ADCMPCR_WCMPE_Msk, +} adc_compare_cfg_t; + +/** ADC Window B channel */ +typedef enum e_adc_window_b_channel +{ + ADC_WINDOW_B_CHANNEL_0 = 0, + ADC_WINDOW_B_CHANNEL_1, + ADC_WINDOW_B_CHANNEL_2, + ADC_WINDOW_B_CHANNEL_3, + ADC_WINDOW_B_CHANNEL_4, + ADC_WINDOW_B_CHANNEL_5, + ADC_WINDOW_B_CHANNEL_6, + ADC_WINDOW_B_CHANNEL_7, + ADC_WINDOW_B_CHANNEL_8, + ADC_WINDOW_B_CHANNEL_9, + ADC_WINDOW_B_CHANNEL_10, + ADC_WINDOW_B_CHANNEL_11, + ADC_WINDOW_B_CHANNEL_12, + ADC_WINDOW_B_CHANNEL_13, + ADC_WINDOW_B_CHANNEL_14, + ADC_WINDOW_B_CHANNEL_15, + ADC_WINDOW_B_CHANNEL_16, + ADC_WINDOW_B_CHANNEL_17, + ADC_WINDOW_B_CHANNEL_18, + ADC_WINDOW_B_CHANNEL_19, + ADC_WINDOW_B_CHANNEL_20, + ADC_WINDOW_B_CHANNEL_21, + ADC_WINDOW_B_CHANNEL_22, + ADC_WINDOW_B_CHANNEL_23, + ADC_WINDOW_B_CHANNEL_24, + ADC_WINDOW_B_CHANNEL_25, + ADC_WINDOW_B_CHANNEL_26, + ADC_WINDOW_B_CHANNEL_27, + ADC_WINDOW_B_CHANNEL_TEMPERATURE = 32, + ADC_WINDOW_B_CHANNEL_VOLT = 33, +} adc_window_b_channel_t; + +/** ADC Window B comparison mode */ +typedef enum e_adc_window_b_mode +{ + ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE = 0, + ADC_WINDOW_B_MODE_GREATER_THAN_OR_INSIDE = R_ADC0_ADCMPBNSR_CMPLB_Msk, +} adc_window_b_mode_t; + +/** ADC action for group A interrupts group B scan. + * This enumeration is used to specify the priority between Group A and B in group mode. */ +typedef enum e_adc_group_a +{ + ADC_GROUP_A_PRIORITY_OFF = 0, ///< Group A ignored and does not interrupt ongoing group B scan + ADC_GROUP_A_GROUP_B_WAIT_FOR_TRIGGER = 1, ///< Group A interrupts Group B(single scan) which restarts at next Group B trigger + ADC_GROUP_A_GROUP_B_RESTART_SCAN = 3, ///< Group A interrupts Group B(single scan) which restarts immediately after Group A scan is complete + ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN = 0x8001, ///< Group A interrupts Group B(continuous scan) which continues scanning without a new Group B trigger +} adc_group_a_t; + +/** ADC double-trigger mode definitions */ +typedef enum e_adc_double_trigger +{ + ADC_DOUBLE_TRIGGER_DISABLED = 0, ///< Double-triggering disabled + ADC_DOUBLE_TRIGGER_ENABLED = 1, ///< Double-triggering enabled + ADC_DOUBLE_TRIGGER_ENABLED_EXTENDED = 2, ///< Double-triggering enabled on both ADC ELC events +} adc_double_trigger_t; + +/** ADC sample state configuration */ +typedef struct st_adc_sample_state +{ + adc_sample_state_reg_t reg_id; ///< Sample state register ID + uint8_t num_states; ///< Number of sampling states for conversion. Ch16-20/21 use the same value. +} adc_sample_state_t; + +/** ADC Window Compare configuration */ +typedef struct st_adc_window_cfg +{ + uint32_t compare_mask; ///< Channel mask to compare with Window A + uint32_t compare_mode_mask; ///< Per-channel condition mask for Window A + adc_compare_cfg_t compare_cfg; ///< Window Compare configuration + uint16_t compare_ref_low; ///< Window A lower reference value + uint16_t compare_ref_high; ///< Window A upper reference value + uint16_t compare_b_ref_low; ///< Window B lower reference value + uint16_t compare_b_ref_high; ///< Window A upper reference value + adc_window_b_channel_t compare_b_channel; ///< Window B channel + adc_window_b_mode_t compare_b_mode; ///< Window B condition setting +} adc_window_cfg_t; + +/** Extended configuration structure for ADC. */ +typedef struct st_adc_extended_cfg +{ + adc_add_t add_average_count; ///< Add or average samples + adc_clear_t clearing; ///< Clear after read + adc_trigger_t trigger_group_b; ///< Group B trigger source; valid only for group mode + adc_double_trigger_t double_trigger_mode; ///< Double-trigger mode setting + adc_vref_control_t adc_vref_control; ///< VREFADC output voltage control + uint8_t enable_adbuf; ///< Enable ADC Ring Buffer, Valid only to use along with DMAC transfer + IRQn_Type window_a_irq; ///< IRQ number for Window Compare A interrupts + IRQn_Type window_b_irq; ///< IRQ number for Window Compare B interrupts + uint8_t window_a_ipl; ///< Priority for Window Compare A interrupts + uint8_t window_b_ipl; ///< Priority for Window Compare B interrupts +} adc_extended_cfg_t; + +/** ADC channel(s) configuration */ +typedef struct st_adc_channel_cfg +{ + uint32_t scan_mask; ///< Channels/bits: bit 0 is ch0; bit 15 is ch15. + uint32_t scan_mask_group_b; ///< Valid for group modes. + uint32_t add_mask; ///< Valid if add enabled in Open(). + adc_window_cfg_t * p_window_cfg; ///< Pointer to Window Compare configuration + adc_group_a_t priority_group_a; ///< Valid for group modes. + uint8_t sample_hold_mask; ///< Channels/bits 0-2. + uint8_t sample_hold_states; ///< Number of states to be used for sample and hold. Affects channels 0-2. +} adc_channel_cfg_t; + +/* Sample and hold Channel mask. Sample and hold is only available for channel 0,1,2*/ +#define ADC_SAMPLE_HOLD_CHANNELS (0x07U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ADC instance control block. DO NOT INITIALIZE. Initialized in @ref adc_api_t::open(). */ +typedef struct +{ + R_ADC0_Type * p_reg; // Base register for this unit + adc_cfg_t const * p_cfg; + uint32_t opened; // Boolean to verify that the Unit has been initialized + uint32_t initialized; // Initialized status of ADC + uint32_t scan_mask; // Scan mask used for Normal scan + uint16_t scan_start_adcsr; + + void (* p_callback)(adc_callback_args_t *); // Pointer to callback that is called when an adc_event_t occurs. + adc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} adc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Interface Structure for user access */ +extern const adc_api_t g_adc_on_adc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ADC_Open(adc_ctrl_t * p_ctrl, adc_cfg_t const * const p_cfg); +fsp_err_t R_ADC_ScanCfg(adc_ctrl_t * p_ctrl, void const * const p_channel_cfg); +fsp_err_t R_ADC_InfoGet(adc_ctrl_t * p_ctrl, adc_info_t * p_adc_info); +fsp_err_t R_ADC_ScanStart(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_ScanGroupStart(adc_ctrl_t * p_ctrl, adc_group_mask_t group_id); +fsp_err_t R_ADC_ScanStop(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_StatusGet(adc_ctrl_t * p_ctrl, adc_status_t * p_status); +fsp_err_t R_ADC_Read(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint16_t * const p_data); +fsp_err_t R_ADC_Read32(adc_ctrl_t * p_ctrl, adc_channel_t const reg_id, uint32_t * const p_data); +fsp_err_t R_ADC_SampleStateCountSet(adc_ctrl_t * p_ctrl, adc_sample_state_t * p_sample); +fsp_err_t R_ADC_Close(adc_ctrl_t * p_ctrl); +fsp_err_t R_ADC_OffsetSet(adc_ctrl_t * const p_ctrl, adc_channel_t const reg_id, int32_t offset); +fsp_err_t R_ADC_Calibrate(adc_ctrl_t * const p_ctrl, void const * p_extend); +fsp_err_t R_ADC_CallbackSet(adc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(adc_callback_args_t *), + void const * const p_context, + adc_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup ADC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_agt.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_agt.h new file mode 100644 index 00000000..e55060d1 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_agt.h @@ -0,0 +1,202 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_AGT_H +#define R_AGT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_agt_cfg.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Leading zeroes removed to avoid coding standards violation. */ + +/** Maximum number of clock counts in 16 bit timer. */ +#if BSP_FEATURE_AGT_HAS_AGTW + #define AGT_MAX_CLOCK_COUNTS (UINT32_MAX) +#else + #define AGT_MAX_CLOCK_COUNTS (UINT16_MAX) +#endif + +/** Maximum period value allowed for AGT. */ +#if BSP_FEATURE_AGT_HAS_AGTW + #define AGT_MAX_PERIOD (UINT32_MAX) +#else + #define AGT_MAX_PERIOD (UINT16_MAX + 1U) +#endif + +/*******************************************************************************************************************//** + * @addtogroup AGT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Count source */ +typedef enum e_agt_clock +{ + AGT_CLOCK_PCLKB = 0x00, ///< PCLKB count source, division by 1, 2, or 8 allowed + AGT_CLOCK_LOCO = 0x40, ///< LOCO count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_AGT_UNDERFLOW = 0x50, ///< Underflow event signal from next lowest AGT channel, division must be 1 + AGT_CLOCK_SUBCLOCK = 0x60, ///< Subclock count source, division by 1, 2, 4, 8, 16, 32, 64, or 128 allowed + AGT_CLOCK_P402 = 0x92, ///< Counts events on P402, events are counted in deep software standby mode + AGT_CLOCK_P403 = 0x93, ///< Counts events on P403, events are counted in deep software standby mode + AGT_CLOCK_AGTIO = 0x80, ///< Counts events on AGTIOn, events are not counted in software standby modes +} agt_clock_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_measure +{ + AGT_MEASURE_DISABLED = 1U, ///< AGT used as a counter + AGT_MEASURE_PULSE_WIDTH_LOW_LEVEL = 3U, ///< AGT used to measure low level pulse width + AGT_MEASURE_PULSE_WIDTH_HIGH_LEVEL = 0x13U, ///< AGT used to measure high level pulse width + AGT_MEASURE_PULSE_PERIOD = 4U, ///< AGT used to measure pulse period +} agt_measure_t; + +/** Input filter, applies AGTIO in pulse period measurement, pulse width measurement, or event counter mode. The filter + * requires the signal to be at the same level for 3 successive reads at the specified filter frequency. */ +typedef enum e_agt_agtio_filter +{ + AGT_AGTIO_FILTER_NONE = 0x00U, ///< No filter + AGT_AGTIO_FILTER_PCLKB = 0x10U, ///< Filter at PCLKB + AGT_AGTIO_FILTER_PCLKB_DIV_8 = 0x20U, ///< Filter at PCLKB / 8 + AGT_AGTIO_FILTER_PCLKB_DIV_32 = 0x30U, ///< Filter at PCLKB / 32 +} agt_agtio_filter_t; + +/** Enable pin for event counting mode. */ +typedef enum e_agt_enable_pin +{ + AGT_ENABLE_PIN_NOT_USED = 0U, ///< AGTEE/AGTWEE is not used + AGT_ENABLE_PIN_ACTIVE_LOW = 0x40U, ///< Events are only counted when AGTEE/AGTWEE is low + AGT_ENABLE_PIN_ACTIVE_HIGH = 0x44U, ///< Events are only counted when AGTEE/AGTWEE is high +} agt_enable_pin_t; + +/** Trigger edge for pulse period measurement mode and event counting mode. */ +typedef enum e_agt_trigger_edge +{ + AGT_TRIGGER_EDGE_RISING = 0U, ///< Measurement starts or events are counted on rising edge + AGT_TRIGGER_EDGE_FALLING = 1U, ///< Measurement starts or events are counted on falling edge + AGT_TRIGGER_EDGE_BOTH = 8U, ///< Events are counted on both edges (n/a for pulse period mode) +} agt_trigger_edge_t; + +/** Output pins, used to select which duty cycle to update in R_AGT_DutyCycleSet(). */ +typedef enum e_agt_output_pin +{ + AGT_OUTPUT_PIN_AGTOA = 0, ///< AGTOA + AGT_OUTPUT_PIN_AGTOB = 1, ///< AGTOB +} agt_output_pin_t; + +/** Level of AGT pin */ +typedef enum e_agt_pin_cfg +{ + AGT_PIN_CFG_DISABLED = 0, ///< Not used as output pin + AGT_PIN_CFG_START_LEVEL_LOW = 3, ///< Pin level low + AGT_PIN_CFG_START_LEVEL_HIGH = 7, ///< Pin level high +} agt_pin_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_agt_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations +#if BSP_FEATURE_AGT_HAS_AGTW + R_AGTW0_Type * p_reg; // Base register for this channel +#else + R_AGT0_Type * p_reg; // Base register for this channel +#endif + uint32_t period; // Current timer period (counts) + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback that is called when a timer_event_t occurs. + timer_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void const * p_context; // Pointer to context to be passed into callback function +} agt_instance_ctrl_t; + +/** Optional AGT extension data structure.*/ +typedef struct st_agt_extended_cfg +{ + agt_clock_t count_source; ///< AGT channel clock source. Valid values are: AGT_CLOCK_PCLKB, AGT_CLOCK_LOCO, AGT_CLOCK_FSUB + + /* Output pin settings. */ + union + { + uint8_t agtoab_settings; + + struct + { + agt_pin_cfg_t agtoa : 3; ///< Configure AGTOA/AGTWOA pin + uint8_t : 1; + agt_pin_cfg_t agtob : 3; ///< Configure AGTOB/AGTWOB pin + } agtoab_settings_b; + }; + agt_pin_cfg_t agto : 3; ///< Configure AGTO pin @note AGTIO polarity is opposite AGTO + + /* Input pin settings. */ + agt_measure_t measurement_mode; ///< Measurement mode + agt_agtio_filter_t agtio_filter; ///< Input filter for AGTIO + agt_enable_pin_t enable_pin; ///< Enable pin (event counting only) + agt_trigger_edge_t trigger_edge; ///< Trigger edge to start pulse period measurement or count external event +} agt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_agt; + +/** @endcond */ + +fsp_err_t R_AGT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_AGT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_AGT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_AGT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_AGT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_AGT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_AGT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end defgroup AGT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ + +FSP_FOOTER + +#endif // R_AGT_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_cgc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_cgc.h new file mode 100644 index 00000000..986f5bd4 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_cgc.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CGC_H +#define R_CGC_H + +/*******************************************************************************************************************//** + * @addtogroup CGC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_cgc_cfg.h" +#include "r_cgc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** CGC private control block. DO NOT MODIFY. Initialization occurs when R_CGC_Open() is called. */ +typedef struct st_cgc_instance_ctrl +{ + uint32_t open; + + cgc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + void (* p_callback)(cgc_callback_args_t * p_args); // Pointer to callback that is called when a cgc_event_t occurs. + + /** Placeholder for user data. Passed to the user callback in ::cgc_callback_args_t. */ + void const * p_context; +} cgc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const cgc_api_t g_cgc_on_cgc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CGC_Open(cgc_ctrl_t * const p_ctrl, cgc_cfg_t const * const p_cfg); +fsp_err_t R_CGC_ClocksCfg(cgc_ctrl_t * const p_ctrl, cgc_clocks_cfg_t const * const p_clock_cfg); +fsp_err_t R_CGC_ClockStart(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const * const p_pll_cfg); +fsp_err_t R_CGC_ClockStop(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); +fsp_err_t R_CGC_ClockCheck(cgc_ctrl_t * const p_ctrl, cgc_clock_t clock_source); +fsp_err_t R_CGC_SystemClockSet(cgc_ctrl_t * const p_ctrl, + cgc_clock_t clock_source, + cgc_divider_cfg_t const * const p_divider_cfg); +fsp_err_t R_CGC_SystemClockGet(cgc_ctrl_t * const p_ctrl, + cgc_clock_t * const p_clock_source, + cgc_divider_cfg_t * const p_divider_cfg); +fsp_err_t R_CGC_OscStopDetectEnable(cgc_ctrl_t * const p_ctrl); +fsp_err_t R_CGC_OscStopDetectDisable(cgc_ctrl_t * const p_ctrl); +fsp_err_t R_CGC_OscStopStatusClear(cgc_ctrl_t * const p_ctrl); +fsp_err_t R_CGC_CallbackSet(cgc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(cgc_callback_args_t *), + void const * const p_context, + cgc_callback_args_t * const p_callback_memory); +fsp_err_t R_CGC_Close(cgc_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup CGC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/* R_CGC_H */ +#endif // R_CGC_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_crc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_crc.h new file mode 100644 index 00000000..d68a84bf --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_crc.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_CRC_H +#define R_CRC_H + +/*******************************************************************************************************************//** + * @addtogroup CRC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_crc_cfg.h" +#include "r_crc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Driver instance control structure. */ +typedef struct st_crc_instance_ctrl +{ + uint32_t open; + const crc_cfg_t * p_cfg; // Pointer to initial configurations +} crc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const crc_api_t g_crc_on_crc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_CRC_Open(crc_ctrl_t * const p_ctrl, crc_cfg_t const * const p_cfg); +fsp_err_t R_CRC_Close(crc_ctrl_t * const p_ctrl); +fsp_err_t R_CRC_Calculate(crc_ctrl_t * const p_ctrl, crc_input_t * const p_crc_input, uint32_t * calculatedValue); +fsp_err_t R_CRC_CalculatedValueGet(crc_ctrl_t * const p_ctrl, uint32_t * calculatedValue); +fsp_err_t R_CRC_SnoopEnable(crc_ctrl_t * const p_ctrl, uint32_t crc_seed); +fsp_err_t R_CRC_SnoopDisable(crc_ctrl_t * const p_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup CRC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dac.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dac.h new file mode 100644 index 00000000..1defc8db --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dac.h @@ -0,0 +1,94 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_DAC_H +#define R_DAC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +#include "bsp_api.h" +#include "r_dac_cfg.h" +#include "r_dac_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup DAC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DAC instance control block. */ +typedef struct st_dac_instance_ctrl +{ + uint8_t channel; // DAC channel number + uint8_t channel_index; // Channel index to access bits + uint32_t channel_opened; // DAC Driver ID + bool output_amplifier_enabled; // DAC Output amplifier (on selected MCUs) enabled/disabled. + bool internal_output_enabled; // Output provided to internal modules (on selected MCUs) enabled/disabled. + R_DAC_Type * p_reg; // Base register for this channel +} dac_instance_ctrl_t; + +/** DAC extended configuration */ +typedef struct st_dac_extended_cfg +{ + bool enable_charge_pump; ///< Enable DAC charge pump available on selected MCUs. + bool output_amplifier_enabled; ///< Output amplifier enable available on selected MCUs. + bool internal_output_enabled; ///< Internal output enable available on selected MCUs. + dac_data_format_t data_format; ///< Data format +} dac_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const dac_api_t g_dac_on_dac; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_DAC_Open(dac_ctrl_t * p_api_ctrl, dac_cfg_t const * const p_cfg); +fsp_err_t R_DAC_Write(dac_ctrl_t * p_api_ctrl, uint16_t value); +fsp_err_t R_DAC_Start(dac_ctrl_t * p_api_ctrl); +fsp_err_t R_DAC_Stop(dac_ctrl_t * p_api_ctrl); +fsp_err_t R_DAC_Close(dac_ctrl_t * p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup DAC) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_DAC_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dmac.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dmac.h new file mode 100644 index 00000000..9b436c1a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dmac.h @@ -0,0 +1,140 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup DMAC + * @{ + **********************************************************************************************************************/ + +#ifndef R_DMAC_H +#define R_DMAC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Max configurable number of transfers in TRANSFER_MODE_NORMAL. */ +#define DMAC_MAX_NORMAL_TRANSFER_LENGTH (0xFFFF) + +/** Max number of transfers per repeat for TRANSFER_MODE_REPEAT. */ +#define DMAC_MAX_REPEAT_TRANSFER_LENGTH (0x400) + +/** Max number of transfers per block in TRANSFER_MODE_BLOCK */ +#define DMAC_MAX_BLOCK_TRANSFER_LENGTH (0x400) + +/** Max configurable number of repeats to trasnfer in TRANSFER_MODE_REPEAT */ +#define DMAC_MAX_REPEAT_COUNT (0x10000) + +/** Max configurable number of blocks to transfer in TRANSFER_MODE_BLOCK */ +#define DMAC_MAX_BLOCK_COUNT (0x10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */ +typedef struct st_dmac_instance_ctrl +{ + uint32_t open; // Driver ID + + transfer_cfg_t const * p_cfg; + + /* Pointer to base register. */ + R_DMAC0_Type * p_reg; +} dmac_instance_ctrl_t; + +/** Callback function parameter data. */ +typedef struct st_dmac_callback_args_t +{ + void const * p_context; ///< Placeholder for user data. Set in r_transfer_t::open function in ::transfer_cfg_t. +} dmac_callback_args_t; + +/** DMAC transfer configuration extension. This extension is required. */ +typedef struct st_dmac_extended_cfg +{ + uint8_t channel; ///< Channel number, does not apply to all HAL drivers. + IRQn_Type irq; ///< DMAC interrupt number + uint8_t ipl; ///< DMAC interrupt priority + int32_t offset; ///< Offset value used with transfer_addr_mode_t::TRANSFER_ADDR_MODE_OFFSET. + + /** Source ring buffer size for @ref TRANSFER_MODE_REPEAT_BLOCK. */ + uint16_t src_buffer_size; + + /** Select which event will trigger the transfer. + * @note Select ELC_EVENT_NONE for software activation in order to use softwareStart and softwareStart to trigger + * transfers. */ + elc_event_t activation_source; + + /** Callback for transfer end interrupt. */ + void (* p_callback)(dmac_callback_args_t * cb_data); + + /** Placeholder for user data. Passed to the user p_callback in ::dmac_callback_args_t. */ + void const * p_context; +} dmac_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const transfer_api_t g_transfer_on_dmac; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_DMAC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg); +fsp_err_t R_DMAC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info); +fsp_err_t R_DMAC_Reset(transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers); +fsp_err_t R_DMAC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode); +fsp_err_t R_DMAC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DMAC_Enable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DMAC_Disable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DMAC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_info); +fsp_err_t R_DMAC_Close(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DMAC_BlockReset(transfer_ctrl_t * const p_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const length, + transfer_size_t size, + uint16_t const num_transfers); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup DMAC) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dtc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dtc.h new file mode 100644 index 00000000..84749411 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_dtc.h @@ -0,0 +1,106 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup DTC + * @{ + **********************************************************************************************************************/ + +#ifndef R_DTC_H +#define R_DTC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_transfer_api.h" +#include "r_dtc_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Max configurable number of transfers in NORMAL MODE */ +#define DTC_MAX_NORMAL_TRANSFER_LENGTH (0x10000) + +/** Max number of transfers per repeat for REPEAT MODE */ +#define DTC_MAX_REPEAT_TRANSFER_LENGTH (0x100) + +/** Max number of transfers per block in BLOCK MODE */ +#define DTC_MAX_BLOCK_TRANSFER_LENGTH (0x100) + +/** Max configurable number of blocks to transfer in BLOCK MODE */ +#define DTC_MAX_BLOCK_COUNT (0x10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DTC transfer configuration extension. This extension is required. */ +typedef struct st_dtc_extended_cfg +{ + /** Select which IRQ will trigger the transfer. */ + IRQn_Type activation_source; +} dtc_extended_cfg_t; + +/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */ +typedef struct st_dtc_instance_ctrl +{ + uint32_t open; // Driver ID + IRQn_Type irq; // Transfer activation IRQ number. +} dtc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const transfer_api_t g_transfer_on_dtc; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_DTC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg); +fsp_err_t R_DTC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info); +fsp_err_t R_DTC_Reset(transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers); +fsp_err_t R_DTC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode); +fsp_err_t R_DTC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_Enable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_Disable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties); +fsp_err_t R_DTC_Close(transfer_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup DTC) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_elc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_elc.h new file mode 100644 index 00000000..093d51c6 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_elc.h @@ -0,0 +1,83 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup ELC + * @{ + **********************************************************************************************************************/ + +#ifndef R_ELC_H +#define R_ELC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_elc_cfg.h" +#include "r_elc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ELC private control block. DO NOT MODIFY. Initialization occurs when R_ELC_Open() is called. */ +typedef struct st_elc_instance_ctrl +{ + uint32_t open; + void const * p_context; +} elc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const elc_api_t g_elc_on_elc; + +/** @endcond */ + +/********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_ELC_Open(elc_ctrl_t * const p_ctrl, elc_cfg_t const * const p_cfg); +fsp_err_t R_ELC_Close(elc_ctrl_t * const p_ctrl); +fsp_err_t R_ELC_SoftwareEventGenerate(elc_ctrl_t * const p_ctrl, elc_software_event_t event_number); +fsp_err_t R_ELC_LinkSet(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal); +fsp_err_t R_ELC_LinkBreak(elc_ctrl_t * const p_ctrl, elc_peripheral_t peripheral); +fsp_err_t R_ELC_Enable(elc_ctrl_t * const p_ctrl); +fsp_err_t R_ELC_Disable(elc_ctrl_t * const p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ELC_H + +/*******************************************************************************************************************//** + * @} (end defgroup ELC) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_flash_hp.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_flash_hp.h new file mode 100644 index 00000000..46c638ed --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_flash_hp.h @@ -0,0 +1,156 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#ifndef R_FLASH_HP_H +#define R_FLASH_HP_H + +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_flash_api.h" +#include "r_flash_hp_cfg.h" + +/*******************************************************************************************************************//** + * @ingroup HAL_Library + * @addtogroup FLASH_HP + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* If Code Flash programming is enabled, then all API functions must execute out of RAM. */ +#if (FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE == 1) + #if defined(__ICCARM__) + #pragma section=".code_in_ram" + #endif + #if defined(__ARMCC_VERSION) || defined(__GNUC__) + #define PLACE_IN_RAM_SECTION __attribute__((noinline)) BSP_PLACE_IN_SECTION(".code_in_ram") + #else + #define PLACE_IN_RAM_SECTION BSP_PLACE_IN_SECTION(".code_in_ram") + #endif +#else + #define PLACE_IN_RAM_SECTION +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Possible Flash operation states */ +typedef enum e_flash_bgo_operation +{ + FLASH_OPERATION_NON_BGO, + FLASH_OPERATION_DF_BGO_WRITE, + FLASH_OPERATION_DF_BGO_ERASE, + FLASH_OPERATION_DF_BGO_BLANKCHECK, +} flash_bgo_operation_t; + +/** Flash HP instance control block. DO NOT INITIALIZE. */ +typedef struct st_flash_hp_instance_ctrl +{ + uint32_t opened; ///< To check whether api has been opened or not. + flash_cfg_t const * p_cfg; + uint32_t timeout_write_cf; + uint32_t timeout_write_df; + uint32_t timeout_dbfull; + uint32_t timeout_blank_check; + uint32_t timeout_write_config; + uint32_t timeout_erase_cf_small_block; + uint32_t timeout_erase_cf_large_block; + uint32_t timeout_erase_df_block; + uint32_t source_start_address; + uint32_t dest_end_address; + uint32_t operations_remaining; + flash_bgo_operation_t current_operation; ///< Operation in progress, for example, FLASH_OPERATION_CF_ERASE + + void (* p_callback)(flash_callback_args_t *); // Pointer to callback + flash_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function +} flash_hp_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const flash_api_t g_flash_on_flash_hp; + +/** @endcond */ + +fsp_err_t R_FLASH_HP_Open(flash_ctrl_t * const p_api_ctrl, flash_cfg_t const * const p_cfg); + +fsp_err_t R_FLASH_HP_Write(flash_ctrl_t * const p_api_ctrl, + uint32_t const src_address, + uint32_t flash_address, + uint32_t const num_bytes); + +fsp_err_t R_FLASH_HP_Erase(flash_ctrl_t * const p_api_ctrl, uint32_t const address, uint32_t const num_blocks); + +fsp_err_t R_FLASH_HP_BlankCheck(flash_ctrl_t * const p_api_ctrl, + uint32_t const address, + uint32_t num_bytes, + flash_result_t * blank_check_result); + +fsp_err_t R_FLASH_HP_Close(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_FLASH_HP_StatusGet(flash_ctrl_t * const p_api_ctrl, flash_status_t * const p_status); + +fsp_err_t R_FLASH_HP_AccessWindowSet(flash_ctrl_t * const p_api_ctrl, uint32_t const start_addr, + uint32_t const end_addr); + +fsp_err_t R_FLASH_HP_AccessWindowClear(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_FLASH_HP_IdCodeSet(flash_ctrl_t * const p_api_ctrl, + uint8_t const * const p_id_code, + flash_id_code_mode_t mode); + +fsp_err_t R_FLASH_HP_Reset(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_FLASH_HP_UpdateFlashClockFreq(flash_ctrl_t * const p_api_ctrl); + +fsp_err_t R_FLASH_HP_StartUpAreaSelect(flash_ctrl_t * const p_api_ctrl, + flash_startup_area_swap_t swap_type, + bool is_temporary); +fsp_err_t R_FLASH_HP_CallbackSet(flash_ctrl_t * const p_api_ctrl, + void ( * p_callback)(flash_callback_args_t *), + void const * const p_context, + flash_callback_args_t * const p_callback_memory); +fsp_err_t R_FLASH_HP_BankSwap(flash_ctrl_t * const p_api_ctrl); +fsp_err_t R_FLASH_HP_InfoGet(flash_ctrl_t * const p_api_ctrl, flash_info_t * const p_info); + +/*******************************************************************************************************************//** + * @} (end defgroup FLASH_HP) + **********************************************************************************************************************/ +#if !BSP_FEATURE_FLASH_HP_VERSION + #error "r_flash_hp is not a supported module for this board type." +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_gpt.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_gpt.h new file mode 100644 index 00000000..b4556430 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_gpt.h @@ -0,0 +1,446 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_GPT_H +#define R_GPT_H + +/*******************************************************************************************************************//** + * @addtogroup GPT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_timer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ +typedef enum e_gpt_io_pin +{ + GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA + GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB + GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB + GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. + GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. + GPT_IO_PIN_ONE_SHOT_LEADING_EDGE = 4, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected. + GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE = 8, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected. +} gpt_io_pin_t; + +/** Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet(). */ +typedef enum e_gpt_buffer_force_push +{ + GPT_BUFFER_FORCE_PUSH = 64, ///< Used in @ref R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected. +} gpt_buffer_force_push; + +/** Level of GPT pin */ +typedef enum e_gpt_pin_level +{ + GPT_PIN_LEVEL_LOW = 0, ///< Pin level low + GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high +} gpt_pin_level_t; + +/** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent + * a bitmask. Multiple sources can be ORed together. */ +typedef enum e_gpt_source +{ + /** No active event sources. */ + GPT_SOURCE_NONE = 0U, + + /** Action performed on GTETRGA rising edge. **/ + GPT_SOURCE_GTETRGA_RISING = (1U << 0), + + /** Action performed on GTETRGA falling edge. **/ + GPT_SOURCE_GTETRGA_FALLING = (1U << 1), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGB_RISING = (1U << 2), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGB_FALLING = (1U << 3), + + /** Action performed on GTETRGC rising edge. **/ + GPT_SOURCE_GTETRGC_RISING = (1U << 4), + + /** Action performed on GTETRGC falling edge. **/ + GPT_SOURCE_GTETRGC_FALLING = (1U << 5), + + /** Action performed on GTETRGB rising edge. **/ + GPT_SOURCE_GTETRGD_RISING = (1U << 6), + + /** Action performed on GTETRGB falling edge. **/ + GPT_SOURCE_GTETRGD_FALLING = (1U << 7), + + /** Action performed when GTIOCA input rises while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), + + /** Action performed when GTIOCA input rises while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), + + /** Action performed when GTIOCA input falls while GTIOCB is low. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), + + /** Action performed when GTIOCA input falls while GTIOCB is high. **/ + GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), + + /** Action performed when GTIOCB input rises while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), + + /** Action performed when GTIOCB input rises while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), + + /** Action performed when GTIOCB input falls while GTIOCA is low. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), + + /** Action performed when GTIOCB input falls while GTIOCA is high. **/ + GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), + + /** Action performed on ELC GPTA event. **/ + GPT_SOURCE_GPT_A = (1U << 16), + + /** Action performed on ELC GPTB event. **/ + GPT_SOURCE_GPT_B = (1U << 17), + + /** Action performed on ELC GPTC event. **/ + GPT_SOURCE_GPT_C = (1U << 18), + + /** Action performed on ELC GPTD event. **/ + GPT_SOURCE_GPT_D = (1U << 19), + + /** Action performed on ELC GPTE event. **/ + GPT_SOURCE_GPT_E = (1U << 20), + + /** Action performed on ELC GPTF event. **/ + GPT_SOURCE_GPT_F = (1U << 21), + + /** Action performed on ELC GPTG event. **/ + GPT_SOURCE_GPT_G = (1U << 22), + + /** Action performed on ELC GPTH event. **/ + GPT_SOURCE_GPT_H = (1U << 23), +} gpt_source_t; + +/** Configurations for output pins. */ +typedef struct s_gpt_output_pin +{ + bool output_enabled; ///< Set to true to enable output, false to disable output + gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t +} gpt_output_pin_t; + +/** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */ +typedef struct s_gpt_gtior_setting +{ + union + { + uint32_t gtior; + struct + { + /* Settings for GTIOCxA pin. */ + uint32_t gtioa : 5; ///< GTIOCA Pin Function Select. + uint32_t : 1; // Reserved + uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop. + uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count. + uint32_t oae : 1; ///< GTIOCA Pin Output Enable + uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting. + uint32_t : 2; /// Reserved + uint32_t nfaen : 1; /// Noise Filter A Enable. + uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select. + + /* Settings for GTIOCxB pin. */ + uint32_t gtiob : 5; ///< GTIOCB Pin Function Select. + uint32_t : 1; // Reserved + uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop. + uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count. + uint32_t obe : 1; ///< GTIOCB Pin Output Enable + uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting. + uint32_t : 2; /// Reserved + uint32_t nfben : 1; /// Noise Filter B Enable. + uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select. + } gtior_b; + }; +} gpt_gtior_setting_t; + +/** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. + * The noise filter samples the external signal at intervals of the PCLK divided by one of the values. + * When 3 consecutive samples are at the same level (high or low), then that level is passed on as + * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. + */ +typedef enum e_gpt_capture_filter +{ + GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering + GPT_CAPTURE_FILTER_PCLKD_DIV_1 = 1U, ///< PCLK/1 - fast sampling + GPT_CAPTURE_FILTER_PCLKD_DIV_4 = 3U, ///< PCLK/4 + GPT_CAPTURE_FILTER_PCLKD_DIV_16 = 5U, ///< PCLK/16 + GPT_CAPTURE_FILTER_PCLKD_DIV_64 = 7U, ///< PCLK/64 - slow sampling +} gpt_capture_filter_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_trigger +{ + GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match + GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match + GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match +} gpt_adc_trigger_t; + +/** POEG channel to link to this channel. */ +typedef enum e_gpt_poeg_link +{ + GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) + GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) + GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) + GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) +} gpt_poeg_link_t; + +/** Select trigger to send output disable request to POEG. */ +typedef enum e_gpt_output_disable +{ + GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request + GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time + GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time +} gpt_output_disable_t; + +/** Disable level options for GTIOC pins. */ +typedef enum e_gpt_gtioc_disable +{ + GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable + GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled + GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled + GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled +} gpt_gtioc_disable_t; + +/** Trigger options to start A/D conversion. */ +typedef enum e_gpt_adc_compare_match +{ + GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A + GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B +} gpt_adc_compare_match_t; + +/** Interrupt skipping modes */ +typedef enum e_gpt_interrupt_skip_source +{ + GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts + + /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, + + /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in + * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough + * interrupt. */ + GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, +} gpt_interrupt_skip_source_t; + +/** Number of interrupts to skip between events */ +typedef enum e_gpt_interrupt_skip_count +{ + GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts + GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt + GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts + GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts + GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts + GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts + GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts + GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts +} gpt_interrupt_skip_count_t; + +/** ADC events to skip during interrupt skipping */ +typedef enum e_gpt_interrupt_skip_adc +{ + GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events + GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events + GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events + GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events +} gpt_interrupt_skip_adc_t; + +/** Delay setting for the PWM Delay Generation Circuit (PDG). */ +typedef enum e_gpt_pwm_output_delay_setting +{ + GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied. + GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied. + GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit. +} gpt_pwm_output_delay_setting_t; + +/** Select which PWM Output Delay setting to apply. */ +typedef enum e_gpt_pwm_output_delay_edge +{ + GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge. + GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge. +} gpt_pwm_output_delay_edge_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ +typedef struct st_gpt_instance_ctrl +{ + uint32_t open; // Whether or not channel is open + const timer_cfg_t * p_cfg; // Pointer to initial configurations + R_GPT0_Type * p_reg; // Base register for this channel + uint32_t channel_mask; // Channel bitmask + timer_variant_t variant; // Timer variant + + void (* p_callback)(timer_callback_args_t *); // Pointer to callback + timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function +} gpt_instance_ctrl_t; + +/** GPT extension for advanced PWM features. */ +typedef struct st_gpt_extended_pwm_cfg +{ + uint8_t trough_ipl; ///< Trough interrupt priority + IRQn_Type trough_irq; ///< Trough interrupt + gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel + gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG + gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion + uint32_t dead_time_count_up; ///< Set a dead time value for counting up + uint32_t dead_time_count_down; ///< Set a dead time value for counting down (available on GPT32E and GPT32EH only) + uint32_t adc_a_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_A + uint32_t adc_b_compare_match; ///< Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT_AD_TRIG_B + gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping + gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events + gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled + gpt_gtioc_disable_t gtioca_disable_setting; ///< DEPRECATED - Select how to configure GTIOCA when output is disabled + gpt_gtioc_disable_t gtiocb_disable_setting; ///< DEPRECATED - Select how to configure GTIOCB when output is disabled +} gpt_extended_pwm_cfg_t; + +/** GPT extension configures the output pins for GPT. */ +typedef struct st_gpt_extended_cfg +{ + gpt_output_pin_t gtioca; ///< DEPRECATED - Configuration for GPT I/O pin A + gpt_output_pin_t gtiocb; ///< DEPRECATED - Configuration for GPT I/O pin B + gpt_source_t start_source; ///< Event sources that trigger the timer to start + gpt_source_t stop_source; ///< Event sources that trigger the timer to stop + gpt_source_t clear_source; ///< Event sources that trigger the timer to clear + gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA + gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB + + /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_up_source; + + /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source + * and count_down_source, then the timer count source is PCLK. */ + gpt_source_t count_down_source; + + /* Debounce filter for GTIOCxA input signal pin (DEPRECATED). */ + gpt_capture_filter_t capture_filter_gtioca; + + /* Debounce filter for GTIOCxB input signal pin (DEPRECATED). */ + gpt_capture_filter_t capture_filter_gtiocb; + + uint8_t capture_a_ipl; ///< Capture A interrupt priority + uint8_t capture_b_ipl; ///< Capture B interrupt priority + IRQn_Type capture_a_irq; ///< Capture A interrupt + IRQn_Type capture_b_irq; ///< Capture B interrupt + gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional + gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. +} gpt_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const timer_api_t g_timer_on_gpt; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); +fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); +fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); +fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); +fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); +fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); +fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); +fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, + gpt_adc_compare_match_t which_compare_match, + uint32_t compare_match_value); +fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl, + gpt_pwm_output_delay_edge_t edge, + gpt_pwm_output_delay_setting_t delay_setting, + uint32_t const pin); +fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, + void ( * p_callback)(timer_callback_args_t *), + void const * const p_context, + timer_callback_args_t * const p_callback_memory); +fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); +fsp_err_t R_GPT_PwmOutputDelayInitialize(); + +/*******************************************************************************************************************//** + * @} (end defgroup GPT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_icu.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_icu.h new file mode 100644 index 00000000..c265d895 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_icu.h @@ -0,0 +1,95 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup ICU + * @{ + **********************************************************************************************************************/ + +#ifndef R_ICU_H +#define R_ICU_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_external_irq_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + *********************************************************************************************************************/ + +/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ +typedef struct st_icu_instance_ctrl +{ + uint32_t open; ///< Used to determine if channel control block is in use + IRQn_Type irq; ///< NVIC interrupt number + uint8_t channel; ///< Channel + +#if BSP_TZ_SECURE_BUILD + external_irq_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +#endif + void (* p_callback)(external_irq_callback_args_t * p_args); // Pointer to callback that is called when an edge is detected on the external irq pin. + + /** Placeholder for user data. Passed to the user callback in ::external_irq_callback_args_t. */ + void const * p_context; +} icu_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const external_irq_api_t g_external_irq_on_icu; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_ICU_ExternalIrqOpen(external_irq_ctrl_t * const p_api_ctrl, external_irq_cfg_t const * const p_cfg); + +fsp_err_t R_ICU_ExternalIrqEnable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqDisable(external_irq_ctrl_t * const p_api_ctrl); + +fsp_err_t R_ICU_ExternalIrqCallbackSet(external_irq_ctrl_t * const p_api_ctrl, + void ( * p_callback)(external_irq_callback_args_t *), + void const * const p_context, + external_irq_callback_args_t * const p_callback_memory); + +fsp_err_t R_ICU_ExternalIrqClose(external_irq_ctrl_t * const p_api_ctrl); + +/*******************************************************************************************************************//** + * @} (end defgroup ICU) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_ICU_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_master.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_master.h new file mode 100644 index 00000000..012a39da --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_master.h @@ -0,0 +1,153 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IIC_MASTER + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIC_MASTER_H +#define R_IIC_MASTER_H + +#include "bsp_api.h" +#include "r_iic_master_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C Timeout mode parameter definition */ +typedef enum e_iic_master_timeout_mode +{ + IIC_MASTER_TIMEOUT_MODE_LONG = 0, ///< Timeout Detection Time Select: Long Mode -> TMOS = 0 + IIC_MASTER_TIMEOUT_MODE_SHORT = 1 ///< Timeout Detection Time Select: Short Mode -> TMOS = 1 +} iic_master_timeout_mode_t; + +typedef enum e_iic_master_timeout_scl_low +{ + IIC_MASTER_TIMEOUT_SCL_LOW_DISABLED = 0, ///< Timeout detection during SCL low disabled + IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED = 1 ///< Timeout detection during SCL low enabled +} iic_master_timeout_scl_low_t; + +/** I2C clock settings */ +typedef struct iic_master_clock_settings +{ + uint8_t cks_value; ///< Internal Reference Clock Select + uint8_t brh_value; ///< High-level period of SCL clock + uint8_t brl_value; ///< Low-level period of SCL clock +} iic_master_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_iic_master_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + + uint32_t open; // Flag to determine if the device is open + R_IIC0_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t remain; // Tracks the remaining data bytes to transfer + uint32_t loaded; // Tracks the number of data bytes written to the register + + uint8_t addr_low; // Holds the last address byte to issue + uint8_t addr_high; // Holds the first address byte to issue in 10-bit mode + uint8_t addr_total; // Holds the total number of address bytes to transfer + uint8_t addr_remain; // Tracks the remaining address bytes to transfer + uint8_t addr_loaded; // Tracks the number of address bytes written to the register + + volatile bool read; // Holds the direction of the data byte transfer + volatile bool restart; // Holds whether or not the restart should be issued when done + volatile bool err; // Tracks whether or not an error occurred during processing + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer + volatile bool dummy_read_completed; // Tracks whether the dummy read is performed + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt + volatile bool address_restarted; // Tracks whether the restart condition is send on 10 bit read + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} iic_master_instance_ctrl_t; + +/** R_IIC extended configuration */ +typedef struct st_iic_master_extended_cfg +{ + iic_master_timeout_mode_t timeout_mode; ///< Timeout Detection Time Select: Long Mode = 0 and Short Mode = 1. + iic_master_timeout_scl_low_t timeout_scl_low; ///< Allows timeouts to occur when SCL is held low. + iic_master_clock_settings_t clock_settings; ///< I2C Clock settings +} iic_master_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_iic; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_IIC_MASTER_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); + +fsp_err_t R_IIC_MASTER_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_MASTER_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_IIC_MASTER_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_MASTER_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_IIC_MASTER_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_MASTER_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_IIC_MASTER_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIC_MASTER_H + +/*******************************************************************************************************************//** + * @} (end defgroup IIC_MASTER) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_slave.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_slave.h new file mode 100644 index 00000000..b160fb07 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_iic_slave.h @@ -0,0 +1,123 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IIC_SLAVE + * @{ + **********************************************************************************************************************/ + +#ifndef R_IIC_SLAVE_H +#define R_IIC_SLAVE_H + +#include "bsp_api.h" +#include "r_iic_slave_cfg.h" +#include "r_i2c_slave_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + ***********************************************************************************************************************/ + +/* IIC Slave transaction enumeration */ +typedef enum e_iic_slave_transfer_dir_option +{ + IIC_SLAVE_TRANSFER_DIR_MASTER_READ_SLAVE_WRITE = 0x0, + IIC_SLAVE_TRANSFER_DIR_MASTER_WRITE_SLAVE_READ = 0x1, + IIC_SLAVE_TRANSFER_DIR_NOT_ESTABLISHED = 0x2 +} iic_slave_transfer_dir_t; + +/** I2C clock settings */ +typedef struct iic_slave_clock_settings +{ + uint8_t cks_value; ///< Internal Reference Clock Select + uint8_t brl_value; ///< Low-level period of SCL clock + uint8_t digital_filter_stages; ///< Number of digital filter stages based on brl_value +} iic_slave_clock_settings_t; + +/* I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_iic_slave_instance_ctrl +{ + i2c_slave_cfg_t const * p_cfg; // Information describing I2C device + uint32_t open; // Flag to determine if the device is open + R_IIC0_Type * p_reg; // Base register for this channel + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer + uint32_t total; // Holds the total number of data bytes to transfer + uint32_t remain; // Tracks the remaining data bytes to transfer + uint32_t loaded; // Tracks the number of data bytes written to the register + uint32_t transaction_count; // Tracks the actual number of transactions + volatile bool notify_request; // Track whether the master request is notified to the application + volatile iic_slave_transfer_dir_t direction; // Holds the direction of the data byte transfer + volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX + volatile bool start_interrupt_enabled; // Tracks whether the start interrupt is enabled + volatile bool transaction_completed; // Tracks whether previous transaction restarted + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_slave_callback_args_t *); + i2c_slave_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} iic_slave_instance_ctrl_t; + +/** R_IIC_SLAVE extended configuration */ +typedef struct st_iic_slave_extended_cfg +{ + iic_slave_clock_settings_t clock_settings; ///< I2C Clock settings +} iic_slave_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + ***********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_slave_api_t const g_i2c_slave_on_iic; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_IIC_SLAVE_Open(i2c_slave_ctrl_t * const p_api_ctrl, i2c_slave_cfg_t const * const p_cfg); +fsp_err_t R_IIC_SLAVE_Read(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_IIC_SLAVE_Write(i2c_slave_ctrl_t * const p_api_ctrl, uint8_t * const p_src, uint32_t const bytes); +fsp_err_t R_IIC_SLAVE_Close(i2c_slave_ctrl_t * const p_api_ctrl); +fsp_err_t R_IIC_SLAVE_CallbackSet(i2c_slave_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_slave_callback_args_t *), + void const * const p_context, + i2c_slave_callback_args_t * const p_callback_memory); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IIC_SLAVE_H + +/*******************************************************************************************************************//** + * @} (end defgroup IIC_SLAVE) + ***********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ioport.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ioport.h new file mode 100644 index 00000000..95e9cf7d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ioport.h @@ -0,0 +1,356 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#include "r_ioport_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; + void const * p_context; +} ioport_instance_ctrl_t; + +/* This typedef is here temporarily. See SWFLEX-144 for details. */ +/** Superset list of all possible IO port pins. */ +typedef enum e_ioport_port_pin_t +{ + IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 +} ioport_port_pin_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_lpm.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_lpm.h new file mode 100644 index 00000000..86b11b9a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_lpm.h @@ -0,0 +1,77 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup LPM + * @{ + **********************************************************************************************************************/ + +#ifndef R_LPM_H +#define R_LPM_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_lpm_cfg.h" +#include "r_lpm_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** LPM private control block. DO NOT MODIFY. Initialization occurs when R_LPM_Open() is called. */ +typedef struct st_lpm_instance_ctrl +{ + uint32_t lpm_open; // Indicates whether the open() API has been successfully called. + lpm_cfg_t const * p_cfg; // Pointer to initial configurations +} lpm_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const lpm_api_t g_lpm_on_lpm; + +/** @endcond */ + +fsp_err_t R_LPM_Open(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); +fsp_err_t R_LPM_Close(lpm_ctrl_t * const p_api_ctrl); +fsp_err_t R_LPM_LowPowerReconfigure(lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t const * const p_cfg); +fsp_err_t R_LPM_LowPowerModeEnter(lpm_ctrl_t * const p_api_ctrl); +fsp_err_t R_LPM_IoKeepClear(lpm_ctrl_t * const p_api_ctrl); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup LPM) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_qspi.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_qspi.h new file mode 100644 index 00000000..7b67669f --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_qspi.h @@ -0,0 +1,163 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup QSPI + * @{ + **********************************************************************************************************************/ + +#ifndef R_QSPI_H +#define R_QSPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include +#include "r_qspi_cfg.h" +#include "r_spi_flash_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define QSPI_DEVICE_START_ADDRESS (0x60000000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Minimum QSPCLK cycles for QSSL to remain high between operations. */ +typedef enum e_qspi_qssl_min_high_level +{ + QSPI_QSSL_MIN_HIGH_LEVEL_1_QSPCLK, ///< QSSL deselected for at least 1 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_2_QSPCLK, ///< QSSL deselected for at least 2 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_3_QSPCLK, ///< QSSL deselected for at least 3 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_4_QSPCLK, ///< QSSL deselected for at least 4 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_5_QSPCLK, ///< QSSL deselected for at least 5 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_6_QSPCLK, ///< QSSL deselected for at least 6 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_7_QSPCLK, ///< QSSL deselected for at least 7 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_8_QSPCLK, ///< QSSL deselected for at least 8 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK, ///< QSSL deselected for at least 9 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_10_QSPCLK, ///< QSSL deselected for at least 10 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_11_QSPCLK, ///< QSSL deselected for at least 11 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_12_QSPCLK, ///< QSSL deselected for at least 12 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_13_QSPCLK, ///< QSSL deselected for at least 13 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_14_QSPCLK, ///< QSSL deselected for at least 14 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_15_QSPCLK, ///< QSSL deselected for at least 15 QSPCLK + QSPI_QSSL_MIN_HIGH_LEVEL_16_QSPCLK, ///< QSSL deselected for at least 16 QSPCLK +} qspi_qssl_min_high_level_t; + +/* QSPCLK divider. */ +typedef enum e_qspi_qspclk_div +{ + QSPI_QSPCLK_DIV_2 = 0x0, ///< QSPCLK = PCLK / 2 + QSPI_QSPCLK_DIV_3 = 0x1, ///< QSPCLK = PCLK / 3 + QSPI_QSPCLK_DIV_4 = 0x2, ///< QSPCLK = PCLK / 4 + QSPI_QSPCLK_DIV_5 = 0x3, ///< QSPCLK = PCLK / 5 + QSPI_QSPCLK_DIV_6 = 0x4, ///< QSPCLK = PCLK / 6 + QSPI_QSPCLK_DIV_7 = 0x5, ///< QSPCLK = PCLK / 7 + QSPI_QSPCLK_DIV_8 = 0x6, ///< QSPCLK = PCLK / 8 + QSPI_QSPCLK_DIV_9 = 0x7, ///< QSPCLK = PCLK / 9 + QSPI_QSPCLK_DIV_10 = 0x8, ///< QSPCLK = PCLK / 10 + QSPI_QSPCLK_DIV_11 = 0x9, ///< QSPCLK = PCLK / 11 + QSPI_QSPCLK_DIV_12 = 0xA, ///< QSPCLK = PCLK / 12 + QSPI_QSPCLK_DIV_13 = 0xB, ///< QSPCLK = PCLK / 13 + QSPI_QSPCLK_DIV_14 = 0xC, ///< QSPCLK = PCLK / 14 + QSPI_QSPCLK_DIV_15 = 0xD, ///< QSPCLK = PCLK / 15 + QSPI_QSPCLK_DIV_16 = 0xE, ///< QSPCLK = PCLK / 16 + QSPI_QSPCLK_DIV_17 = 0xF, ///< QSPCLK = PCLK / 17 + QSPI_QSPCLK_DIV_18 = 0x10, ///< QSPCLK = PCLK / 18 + QSPI_QSPCLK_DIV_20 = 0x11, ///< QSPCLK = PCLK / 20 + QSPI_QSPCLK_DIV_22 = 0x12, ///< QSPCLK = PCLK / 22 + QSPI_QSPCLK_DIV_24 = 0x13, ///< QSPCLK = PCLK / 24 + QSPI_QSPCLK_DIV_26 = 0x14, ///< QSPCLK = PCLK / 26 + QSPI_QSPCLK_DIV_28 = 0x15, ///< QSPCLK = PCLK / 28 + QSPI_QSPCLK_DIV_30 = 0x16, ///< QSPCLK = PCLK / 30 + QSPI_QSPCLK_DIV_32 = 0x17, ///< QSPCLK = PCLK / 32 + QSPI_QSPCLK_DIV_34 = 0x18, ///< QSPCLK = PCLK / 34 + QSPI_QSPCLK_DIV_36 = 0x19, ///< QSPCLK = PCLK / 36 + QSPI_QSPCLK_DIV_38 = 0x1A, ///< QSPCLK = PCLK / 38 + QSPI_QSPCLK_DIV_40 = 0x1B, ///< QSPCLK = PCLK / 40 + QSPI_QSPCLK_DIV_42 = 0x1C, ///< QSPCLK = PCLK / 42 + QSPI_QSPCLK_DIV_44 = 0x1D, ///< QSPCLK = PCLK / 44 + QSPI_QSPCLK_DIV_46 = 0x1E, ///< QSPCLK = PCLK / 46 + QSPI_QSPCLK_DIV_48 = 0x1F, ///< QSPCLK = PCLK / 48 +} qspi_qspclk_div_t; + +/* Extended configuration. */ +typedef struct st_qspi_extended_cfg +{ + qspi_qssl_min_high_level_t min_qssl_deselect_cycles; ///< Minimum QSSL deselect time + qspi_qspclk_div_t qspclk_div; ///< QSPCLK divider +} qspi_extended_cfg_t; + +/** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ +typedef struct st_qspi_instance_ctrl +{ + spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration + spi_flash_data_lines_t data_lines; // Data lines + uint32_t total_size_bytes; // Total size of the flash in bytes + uint32_t open; // Whether or not driver is open +} qspi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_flash_api_t g_qspi_on_spi_flash; + +/** @endcond */ + +fsp_err_t R_QSPI_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); +fsp_err_t R_QSPI_Close(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint32_t const bytes, + bool const read_after_write); +fsp_err_t R_QSPI_DirectRead(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_QSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); +fsp_err_t R_QSPI_XipEnter(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_XipExit(spi_flash_ctrl_t * p_ctrl); +fsp_err_t R_QSPI_Write(spi_flash_ctrl_t * p_ctrl, + uint8_t const * const p_src, + uint8_t * const p_dest, + uint32_t byte_count); +fsp_err_t R_QSPI_Erase(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); +fsp_err_t R_QSPI_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); +fsp_err_t R_QSPI_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank); +fsp_err_t R_QSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl, + spi_flash_direct_transfer_t * const p_transfer, + spi_flash_direct_transfer_dir_t direction); +fsp_err_t R_QSPI_AutoCalibrate(spi_flash_ctrl_t * p_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup QSPI) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_rtc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_rtc.h new file mode 100644 index 00000000..7222c8d4 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_rtc.h @@ -0,0 +1,98 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_RTC_H +#define R_RTC_H + +/*******************************************************************************************************************//** + * @addtogroup RTC RTC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_rtc_cfg.h" +#include "r_rtc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Counting mode */ +#define RTC_CALENDAR_MODE (0) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref rtc_api_t::open is called */ +typedef struct st_rtc_ctrl +{ + uint32_t open; ///< Whether or not driver is open + const rtc_cfg_t * p_cfg; ///< Pointer to initial configurations + volatile bool carry_isr_triggered; ///< Was the carry isr triggered + + void (* p_callback)(rtc_callback_args_t *); // Pointer to callback that is called when a rtc_event_t occurs. + rtc_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + void const * p_context; // Pointer to context to be passed into callback function +} rtc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const rtc_api_t g_rtc_on_rtc; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_RTC_Open(rtc_ctrl_t * const p_ctrl, rtc_cfg_t const * const p_cfg); +fsp_err_t R_RTC_Close(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_ClockSourceSet(rtc_ctrl_t * const p_ctrl); +fsp_err_t R_RTC_CalendarTimeSet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_CalendarTimeGet(rtc_ctrl_t * const p_ctrl, rtc_time_t * const p_time); +fsp_err_t R_RTC_CalendarAlarmSet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_CalendarAlarmGet(rtc_ctrl_t * const p_ctrl, rtc_alarm_time_t * const p_alarm); +fsp_err_t R_RTC_PeriodicIrqRateSet(rtc_ctrl_t * const p_ctrl, rtc_periodic_irq_select_t const rate); +fsp_err_t R_RTC_ErrorAdjustmentSet(rtc_ctrl_t * const p_ctrl, rtc_error_adjustment_cfg_t const * const err_adj_cfg); +fsp_err_t R_RTC_InfoGet(rtc_ctrl_t * const p_ctrl, rtc_info_t * const p_rtc_info); +fsp_err_t R_RTC_CallbackSet(rtc_ctrl_t * const p_ctrl, + void ( * p_callback)(rtc_callback_args_t *), + void const * const p_context, + rtc_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_RTC_H + +/*******************************************************************************************************************//** + * @} (end addtogroup RTC) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_i2c.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_i2c.h new file mode 100644 index 00000000..b1f4fe53 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_i2c.h @@ -0,0 +1,142 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SCI_I2C + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCI_I2C_H +#define R_SCI_I2C_H + +#include "bsp_api.h" +#include "r_sci_i2c_cfg.h" +#include "r_i2c_master_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** I2C clock settings */ +typedef struct sci_i2c_clock_settings +{ + bool bitrate_modulation; ///< Bit-rate Modulation Function enable or disable + uint8_t brr_value; ///< Bit rate register settings + uint8_t clk_divisor_value; ///< Clock Select settings + uint8_t mddr_value; ///< Modulation Duty Register settings + uint8_t cycles_value; ///< SDA Delay Output Cycles Select + uint8_t snfr_value; ///< Noise Filter Setting Register value +} sci_i2c_clock_settings_t; + +/** I2C control structure. DO NOT INITIALIZE. */ +typedef struct st_sci_i2c_instance_ctrl +{ + i2c_master_cfg_t const * p_cfg; // Pointer to the configuration structure + uint32_t slave; // The address of the slave device + i2c_master_addr_mode_t addr_mode; // Indicates how slave fields should be interpreted + uint32_t open; // Flag to determine if the device is open + R_SCI0_Type * p_reg; // Base register for this channel + + IRQn_Type rxi_irq; // Receive IRQ number + IRQn_Type txi_irq; // Transmit IRQ number + IRQn_Type tei_irq; // Transmit end IRQ number + + /* Current transfer information. */ + uint8_t * p_buff; // Holds the data associated with the transfer */ + uint32_t total; // Holds the total number of data bytes to transfer */ + uint32_t remain; // Tracks the remaining data bytes to transfer */ + uint32_t loaded; // Tracks the number of data bytes written to the register */ + + uint8_t addr_low; // Holds the last address byte to issue */ + uint8_t addr_high; // Holds the first address byte to issue in 10-bit mode */ + uint8_t addr_total; // Holds the total number of address bytes to transfer */ + uint8_t addr_remain; // Tracks the remaining address bytes to transfer */ + uint8_t addr_loaded; // Tracks the number of address bytes written to the register */ + + volatile bool read; // Holds the direction of the data byte transfer */ + volatile bool restart; // Holds whether or not the restart should be issued when done */ + volatile bool err; // Tracks whether or not an error occurred during processing */ + volatile bool restarted; // Tracks whether or not a restart was issued during the previous transfer */ + volatile bool do_dummy_read; // Tracks whether a dummy read is issued on the first RX */ + volatile bool activation_on_rxi; // Tracks whether the transfer is activated on RXI interrupt */ + volatile bool activation_on_txi; // Tracks whether the transfer is activated on TXI interrupt */ + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2c_master_callback_args_t *); + i2c_master_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} sci_i2c_instance_ctrl_t; + +/** SCI I2C extended configuration */ +typedef struct st_sci_i2c_extended_cfg +{ + sci_i2c_clock_settings_t clock_settings; ///< I2C Clock settings +} sci_i2c_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern i2c_master_api_t const g_i2c_master_on_sci; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SCI_I2C_Open(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_cfg_t const * const p_cfg); +fsp_err_t R_SCI_I2C_Close(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_I2C_Read(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SCI_I2C_Write(i2c_master_ctrl_t * const p_api_ctrl, + uint8_t * const p_src, + uint32_t const bytes, + bool const restart); +fsp_err_t R_SCI_I2C_Abort(i2c_master_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_I2C_SlaveAddressSet(i2c_master_ctrl_t * const p_api_ctrl, + uint32_t const slave, + i2c_master_addr_mode_t const addr_mode); +fsp_err_t R_SCI_I2C_CallbackSet(i2c_master_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2c_master_callback_args_t *), + void const * const p_context, + i2c_master_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_I2C_StatusGet(i2c_master_ctrl_t * const p_api_ctrl, i2c_master_status_t * p_status); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup SCI_I2C) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_spi.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_spi.h new file mode 100644 index 00000000..5ccdccae --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_spi.h @@ -0,0 +1,120 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SCI_SPI_H +#define R_SCI_SPI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*****************************************************************************************************************//** + * @ingroup SCI_SPI + * @{ + ********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Settings for adjusting the SPI CLK. */ +typedef struct +{ + uint8_t brr; + uint8_t cks : 2; + uint8_t mddr; ///< Set to 0 to disable MDDR. +} sci_spi_div_setting_t; + +/** SCI SPI extended configuration */ +typedef struct st_sci_spi_extended_cfg +{ + sci_spi_div_setting_t clk_div; +} sci_spi_extended_cfg_t; + +/** SPI instance control block. DO NOT INITIALIZE. */ +typedef struct st_sci_spi_instance_ctrl +{ + uint32_t open; + spi_cfg_t const * p_cfg; + R_SCI0_Type * p_reg; + uint8_t * p_src; + uint8_t * p_dest; + uint32_t tx_count; + uint32_t rx_count; + uint32_t count; + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} sci_spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_sci; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_SCI_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); +fsp_err_t R_SCI_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); +fsp_err_t R_SCI_SPI_Close(spi_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_SPI_CalculateBitrate(uint32_t bitrate, sci_spi_div_setting_t * sclk_div, bool use_mddr); +fsp_err_t R_SCI_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end ingroup SCI_SPI) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_uart.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_uart.h new file mode 100644 index 00000000..d83b397c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sci_uart.h @@ -0,0 +1,215 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SCI_UART_H +#define R_SCI_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_clk_src +{ + SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_clk_src_t; + +/** UART flow control mode definition */ +typedef enum e_sci_uart_flow_control +{ + SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use SCI pin for RTS + SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use SCI pin for CTS + SCI_UART_FLOW_CONTROL_CTSRTS = 3U, ///< Use SCI pin for CTS, external pin for RTS + SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 8U, ///< Use CTSn_RTSn pin for RTS and CTSn pin for CTS. Available only for some channels on selected MCUs. See hardware manual for channel specific options +} sci_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} sci_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_uart_rx_fifo_trigger +{ + SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_uart_start_bit_t +{ + SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_uart_start_bit_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_uart_noise_cancellation +{ + SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation +} sci_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_uart_rs485_enable +{ + SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_uart_rs485_de_polarity +{ + SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_uart_rs485_de_polarity_t; + +/** Register settings to acheive a desired baud rate and modulation duty. */ +typedef struct st_baud_setting_t +{ + union + { + uint8_t semr_baudrate_bits; + + struct + { + uint8_t : 2; + uint8_t brme : 1; ///< Bit Rate Modulation Enable + uint8_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint8_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint8_t : 1; + uint8_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint8_t : 1; + } semr_baudrate_bits_b; + }; + uint8_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint8_t brr; ///< Bit Rate Register setting + uint8_t mddr; ///< Modulation Duty Register setting +} baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_uart_rs485_setting +{ + sci_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + bsp_io_port_pin_t de_control_pin; ///< UART Driver Enable pin. +} sci_uart_rs485_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_uart_extended_cfg +{ + sci_clk_src_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge + sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DTC is used. + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_uart_flow_control_t flow_control; ///< CTS/RTS function of the SSn pin + sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. +} sci_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci; + +/** @endcond */ + +fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_api_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_api_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_api_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_api_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_api_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_api_ctrl); +fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_api_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_UART_BaudCalculate(uint32_t baudrate, + bool bitrate_modulation, + uint32_t baud_rate_error_x_1000, + baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_api_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_api_ctrl, uint32_t * remaining_bytes); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sdhi.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sdhi.h new file mode 100644 index 00000000..c38fb20c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_sdhi.h @@ -0,0 +1,173 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SDHI_H +#define R_SDHI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sdhi_cfg.h" +#include "r_sdmmc_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup SDHI + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SDHI_MAX_BLOCK_SIZE (512U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* Private enumeration used in sdhi_instance_ctrl_t. */ +typedef enum e_sdhi_transfer_dir +{ + SDHI_TRANSFER_DIR_NONE, + SDHI_TRANSFER_DIR_READ, + SDHI_TRANSFER_DIR_WRITE +} sdhi_transfer_dir_t; + +/* Private structure used in sdhi_instance_ctrl_t. */ +typedef union +{ + uint32_t word; + + struct s_sdhi_event_type + { + uint32_t response_end : 1; // < response end detected + uint32_t reserved_1 : 1; + uint32_t access_end : 1; // < access end detected + uint32_t card_removed : 1; // < card removal detected by cd pin + uint32_t card_inserted : 1; // < card insertion detected by cd pin + uint32_t reserved_5 : 3; + uint32_t card_dat3_removed : 1; // < card removal detected by dat3 pin + uint32_t card_dat3_inserted : 1; // < card inserion detected by dat3 pin + uint32_t reservered_10 : 6; + uint32_t cmd_err : 1; // < command error + uint32_t crc_err : 1; // < crc error + uint32_t end_err : 1; // < end bit error + uint32_t dto : 1; // < data timeout + uint32_t ilw : 1; // < illegal write address + uint32_t ilr : 1; // < illegal read address + uint32_t rspt : 1; // < response timeout + uint32_t event_error : 1; // < all error flags combined + uint32_t bre : 1; // < buffer read enable + uint32_t bwe : 1; // < buffer write enable + uint32_t reserved_26 : 5; + uint32_t ila_err : 1; // < illegal access + } bit; +} sdhi_event_t; + +/** SDMMC instance control block. This is private to the FSP and should not be used or modified by the application. */ +typedef struct st_sdmmc_instance_ctrl +{ + uint32_t open; + sdmmc_cfg_t const * p_cfg; + sdmmc_device_t device; + bool sector_addressing; + bool transfer_in_progress; + bool initialized; + R_SDHI0_Type * p_reg; + volatile sdhi_event_t sdhi_event; + sdhi_transfer_dir_t transfer_dir; + uint8_t * p_transfer_data; + uint32_t transfer_blocks_total; + uint32_t transfer_block_current; + uint32_t transfer_block_size; + uint32_t aligned_buff[SDHI_MAX_BLOCK_SIZE / sizeof(uint32_t)]; + + void (* p_callback)(sdmmc_callback_args_t *); // Pointer to callback + sdmmc_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory + void const * p_context; // Pointer to context to be passed into callback function +} sdhi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const sdmmc_api_t g_sdmmc_on_sdhi; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_SDHI_Open(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_cfg_t const * const p_cfg); +fsp_err_t R_SDHI_MediaInit(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_device_t * const p_device); +fsp_err_t R_SDHI_Read(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const start_sector, + uint32_t const sector_count); +fsp_err_t R_SDHI_Write(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const start_sector, + uint32_t const sector_count); +fsp_err_t R_SDHI_ReadIo(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address); +fsp_err_t R_SDHI_WriteIo(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_data, + uint32_t const function, + uint32_t const address, + sdmmc_io_write_mode_t const read_after_write); +fsp_err_t R_SDHI_ReadIoExt(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t * const p_dest, + uint32_t const function, + uint32_t const address, + uint32_t * const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); +fsp_err_t R_SDHI_WriteIoExt(sdmmc_ctrl_t * const p_api_ctrl, + uint8_t const * const p_source, + uint32_t const function, + uint32_t const address, + uint32_t const count, + sdmmc_io_transfer_mode_t transfer_mode, + sdmmc_io_address_mode_t address_mode); +fsp_err_t R_SDHI_IoIntEnable(sdmmc_ctrl_t * const p_api_ctrl, bool enable); +fsp_err_t R_SDHI_StatusGet(sdmmc_ctrl_t * const p_api_ctrl, sdmmc_status_t * const p_status); +fsp_err_t R_SDHI_Erase(sdmmc_ctrl_t * const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count); +fsp_err_t R_SDHI_CallbackSet(sdmmc_ctrl_t * const p_api_ctrl, + void ( * p_callback)(sdmmc_callback_args_t *), + void const * const p_context, + sdmmc_callback_args_t * const p_callback_memory); +fsp_err_t R_SDHI_Close(sdmmc_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SDHI_H + +/*******************************************************************************************************************//** + * @} (end addtogroup SDHI) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_spi.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_spi.h new file mode 100644 index 00000000..076d03d0 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_spi.h @@ -0,0 +1,201 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SPI_H +#define R_SPI_H + +/*******************************************************************************************************************//** + * @addtogroup SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/************************************************************************************************* + * Type defines for the SPI interface API + *************************************************************************************************/ + +/** 3-Wire or 4-Wire mode. */ +typedef enum e_spi_ssl_mode +{ + SPI_SSL_MODE_SPI, ///< SPI operation (4-wire method) + SPI_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method) +} spi_ssl_mode_t; + +/** Transmit Only (Half Duplex), or Full Duplex. */ +typedef enum e_spi_communication +{ + SPI_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication + SPI_COMMUNICATION_TRANSMIT_ONLY ///< Transit only serial communication +} spi_communication_t; + +/** Slave Select Polarity. */ +typedef enum e_spi_sslp +{ + SPI_SSLP_LOW, ///< SSLP signal polarity active low + SPI_SSLP_HIGH ///< SSLP signal polarity active high +} spi_ssl_polarity_t; + +/** The Slave Select Line */ +typedef enum e_spi_ssl_select +{ + SPI_SSL_SELECT_SSL0, ///< Select SSL0 + SPI_SSL_SELECT_SSL1, ///< Select SSL1 + SPI_SSL_SELECT_SSL2, ///< Select SSL2 + SPI_SSL_SELECT_SSL3 ///< Select SSL3 +} spi_ssl_select_t; + +/** MOSI Idle Behavior. */ +typedef enum e_spi_mosi_idle_value_fixing +{ + SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit + SPI_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling + SPI_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling +} spi_mosi_idle_value_fixing_t; + +/** Parity Mode */ +typedef enum e_spi_parity_mode +{ + SPI_PARITY_MODE_DISABLE, ///< Disable parity + SPI_PARITY_MODE_ODD, ///< Select even parity + SPI_PARITY_MODE_EVEN ///< Select odd parity +} spi_parity_t; + +/** Byte Swapping Enable/Disable. */ +typedef enum +{ + SPI_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers + SPI_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers +} spi_byte_swap_t; + +/** Delay count for SPI delay settings. */ +typedef enum e_spi_clock_delay_count +{ + SPI_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK + SPI_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK + SPI_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK + SPI_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK + SPI_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK + SPI_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK + SPI_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK + SPI_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK +} spi_delay_count_t; + +/** SPI Clock Divider settings. */ +typedef struct +{ + uint8_t spbr; ///< SPBR register setting + uint8_t brdv : 2; ///< BRDV setting in SPCMD0 +} rspck_div_setting_t; + +/** Extended SPI interface configuration */ +typedef struct st_spi_extended_cfg +{ + spi_ssl_mode_t spi_clksyn; ///< Select spi or clock syn mode operation + spi_communication_t spi_comm; ///< Select full-duplex or transmit-only communication + spi_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity + spi_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3 + spi_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection + spi_parity_t parity; ///< Select parity and enable/disable parity + spi_byte_swap_t byte_swap; ///< Select byte swap mode + rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider. + spi_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting + spi_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting + spi_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting +} spi_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ +typedef struct st_spi_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration + R_SPI0_Type * p_regs; ///< Base register for this channel + void const * p_tx_data; ///< Buffer to transmit + void * p_rx_data; ///< Buffer to receive + uint32_t tx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_spi; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); + +fsp_err_t R_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl); + +fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div); +fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end ingroup SPI) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ssi.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ssi.h new file mode 100644 index 00000000..264e99de --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_ssi.h @@ -0,0 +1,137 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SSI + * @{ + **********************************************************************************************************************/ + +#ifndef R_SSI_H +#define R_SSI_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_i2s_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Audio clock source. */ +typedef enum e_ssi_audio_clock +{ + SSI_AUDIO_CLOCK_EXTERNAL = 0, ///< Audio clock source is the AUDIO_CLK input pin + SSI_AUDIO_CLOCK_INTERNAL = 1, ///< Audio clock source is internal connection to a MCU specific GPT channel output +} ssi_audio_clock_t; + +/** Bit clock division ratio. Bit clock frequency = audio clock frequency / bit clock division ratio. */ +typedef enum e_ssi_clock_div +{ + SSI_CLOCK_DIV_1 = 0, ///< Clock divisor 1 + SSI_CLOCK_DIV_2 = 1, ///< Clock divisor 2 + SSI_CLOCK_DIV_4 = 2, ///< Clock divisor 4 + SSI_CLOCK_DIV_6 = 8, ///< Clock divisor 6 + SSI_CLOCK_DIV_8 = 3, ///< Clock divisor 8 + SSI_CLOCK_DIV_12 = 9, ///< Clock divisor 12 + SSI_CLOCK_DIV_16 = 4, ///< Clock divisor 16 + SSI_CLOCK_DIV_24 = 10, ///< Clock divisor 24 + SSI_CLOCK_DIV_32 = 5, ///< Clock divisor 32 + SSI_CLOCK_DIV_48 = 11, ///< Clock divisor 48 + SSI_CLOCK_DIV_64 = 6, ///< Clock divisor 64 + SSI_CLOCK_DIV_96 = 12, ///< Clock divisor 96 + SSI_CLOCK_DIV_128 = 7, ///< Clock divisor 128 +} ssi_clock_div_t; + +/** Channel instance control block. DO NOT INITIALIZE. Initialization occurs when @ref i2s_api_t::open is called. */ +typedef struct st_ssi_instance_ctrl +{ + uint32_t open; // Whether or not this control block is initialized + i2s_cfg_t const * p_cfg; // Initial configurations. + R_SSI0_Type * p_reg; // Pointer to SSI register base address + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + void const * p_tx_src; + + /* Size of source buffer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_samples; + + /* Destination buffer pointer used to fill from hardware FIFO in receive ISR. */ + void * p_rx_dest; + + /* Size of destination buffer used to fill from hardware FIFO in receive ISR. */ + uint32_t rx_dest_samples; + transfer_size_t fifo_access_size; // Access the FIFO as 1 byte, 2 bytes, or 4 bytes + + /* Pointer to callback and optional working memory */ + void (* p_callback)(i2s_callback_args_t *); + i2s_callback_args_t * p_callback_memory; + void const * p_context; // < User defined context passed into callback function +} ssi_instance_ctrl_t; + +/** SSI configuration extension. This extension is optional. */ +typedef struct st_ssi_extended_cfg +{ + ssi_audio_clock_t audio_clock; ///< Audio clock source, default is SSI_AUDIO_CLOCK_EXTERNAL + ssi_clock_div_t bit_clock_div; ///< Select bit clock division ratio +} ssi_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const i2s_api_t g_i2s_on_ssi; + +/** @endcond */ + +/********************************************************************************************************************** + * Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_SSI_Open(i2s_ctrl_t * const p_ctrl, i2s_cfg_t const * const p_cfg); +fsp_err_t R_SSI_Stop(i2s_ctrl_t * const p_ctrl); +fsp_err_t R_SSI_StatusGet(i2s_ctrl_t * const p_ctrl, i2s_status_t * const p_status); +fsp_err_t R_SSI_Write(i2s_ctrl_t * const p_ctrl, void const * const p_src, uint32_t const bytes); +fsp_err_t R_SSI_Read(i2s_ctrl_t * const p_ctrl, void * const p_dest, uint32_t const bytes); +fsp_err_t R_SSI_WriteRead(i2s_ctrl_t * const p_ctrl, void const * const p_src, void * const p_dest, + uint32_t const bytes); +fsp_err_t R_SSI_Mute(i2s_ctrl_t * const p_ctrl, i2s_mute_t const mute_enable); +fsp_err_t R_SSI_Close(i2s_ctrl_t * const p_ctrl); +fsp_err_t R_SSI_CallbackSet(i2s_ctrl_t * const p_api_ctrl, + void ( * p_callback)(i2s_callback_args_t *), + void const * const p_context, + i2s_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SSI_H + +/*******************************************************************************************************************//** + * @} (end defgroup SSI) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_usb_basic.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_usb_basic.h new file mode 100644 index 00000000..efff1162 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_usb_basic.h @@ -0,0 +1,133 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup USB USB + * @{ + **********************************************************************************************************************/ + +#ifndef R_USB_H +#define R_USB_H + +#include "bsp_api.h" +#include "r_usb_basic_cfg.h" +#include "r_usb_basic_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ + +typedef usb_event_info_t usb_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +extern const usb_api_t g_usb_on_usb; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ + +fsp_err_t R_USB_Open(usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const cfg); + +fsp_err_t R_USB_Close(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_Read(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination); + +fsp_err_t R_USB_Write(usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_buf, uint32_t size, uint8_t destination); + +fsp_err_t R_USB_Stop(usb_ctrl_t * const p_api_ctrl, usb_transfer_t direction, uint8_t destination); + +fsp_err_t R_USB_Suspend(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_Resume(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_VbusSet(usb_ctrl_t * const p_api_ctrl, uint16_t state); + +fsp_err_t R_USB_InfoGet(usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uint8_t destination); + +fsp_err_t R_USB_PipeRead(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + +fsp_err_t R_USB_PipeWrite(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number); + +fsp_err_t R_USB_PipeStop(usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number); + +fsp_err_t R_USB_UsedPipesGet(usb_ctrl_t * const p_api_ctrl, uint16_t * p_pipe, uint8_t destination); + +fsp_err_t R_USB_PipeInfoGet(usb_ctrl_t * const p_api_ctrl, usb_pipe_t * p_info, uint8_t pipe_number); + +fsp_err_t R_USB_PullUp(usb_ctrl_t * const p_api_ctrl, uint8_t state); + +fsp_err_t R_USB_EventGet(usb_ctrl_t * const p_api_ctrl, usb_status_t * event); + +fsp_err_t R_USB_Callback(usb_callback_t * p_callback); + +fsp_err_t R_USB_HostControlTransfer(usb_ctrl_t * const p_api_ctrl, + usb_setup_t * p_setup, + uint8_t * p_buf, + uint8_t device_address); + +fsp_err_t R_USB_PeriControlDataGet(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + +fsp_err_t R_USB_PeriControlDataSet(usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size); + +fsp_err_t R_USB_PeriControlStatusSet(usb_ctrl_t * const p_api_ctrl, usb_setup_status_t status); + +fsp_err_t R_USB_RemoteWakeup(usb_ctrl_t * const p_api_ctrl); + +fsp_err_t R_USB_ModuleNumberGet(usb_ctrl_t * const p_api_ctrl, uint8_t * module_number); + +fsp_err_t R_USB_ClassTypeGet(usb_ctrl_t * const p_api_ctrl, usb_class_t * class_type); + +fsp_err_t R_USB_DeviceAddressGet(usb_ctrl_t * const p_api_ctrl, uint8_t * device_address); + +fsp_err_t R_USB_PipeNumberGet(usb_ctrl_t * const p_api_ctrl, uint8_t * pipe_number); + +fsp_err_t R_USB_DeviceStateGet(usb_ctrl_t * const p_api_ctrl, uint16_t * state); + +fsp_err_t R_USB_DataSizeGet(usb_ctrl_t * const p_api_ctrl, uint32_t * data_size); + +fsp_err_t R_USB_SetupGet(usb_ctrl_t * const p_api_ctrl, usb_setup_t * setup); + +fsp_err_t R_USB_OtgCallbackSet(usb_ctrl_t * const p_api_ctrl, usb_otg_callback_t * p_callback); + +fsp_err_t R_USB_OtgSRP(usb_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_USB_H + +/*******************************************************************************************************************//** + * @} (end addtogroup USB) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_wdt.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_wdt.h new file mode 100644 index 00000000..de3eea73 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/inc/instances/r_wdt.h @@ -0,0 +1,93 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup WDT WDT + * @{ + **********************************************************************************************************************/ + +#ifndef R_WDT_H +#define R_WDT_H + +#include "bsp_api.h" + +#include "r_wdt_cfg.h" +#include "r_wdt_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** WDT private control block. DO NOT MODIFY. Initialization occurs when R_WDT_Open() is called. */ +typedef struct st_wdt_instance_ctrl +{ + uint32_t wdt_open; // Indicates whether the open() API has been successfully + // called. + void const * p_context; // Placeholder for user data. Passed to the user callback in + // wdt_callback_args_t. + void (* p_callback)(wdt_callback_args_t * p_args); // Callback provided when a WDT NMI ISR occurs. + wdt_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. +} wdt_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const wdt_api_t g_wdt_on_wdt; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_WDT_Refresh(wdt_ctrl_t * const p_ctrl); + +fsp_err_t R_WDT_Open(wdt_ctrl_t * const p_ctrl, wdt_cfg_t const * const p_cfg); + +fsp_err_t R_WDT_StatusClear(wdt_ctrl_t * const p_ctrl, const wdt_status_t status); + +fsp_err_t R_WDT_StatusGet(wdt_ctrl_t * const p_ctrl, wdt_status_t * const p_status); + +fsp_err_t R_WDT_CounterGet(wdt_ctrl_t * const p_ctrl, uint32_t * const p_count); + +fsp_err_t R_WDT_TimeoutGet(wdt_ctrl_t * const p_ctrl, wdt_timeout_values_t * const p_timeout); + +fsp_err_t R_WDT_CallbackSet(wdt_ctrl_t * const p_ctrl, + void ( * p_callback)(wdt_callback_args_t *), + void const * const p_context, + wdt_callback_args_t * const p_callback_memory); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_WDT_H + +/*******************************************************************************************************************//** + * @} (end addtogroup WDT) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h new file mode 100644 index 00000000..24f360cb --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h @@ -0,0 +1,17461 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA2A1AB.h + * @brief CMSIS HeaderFile + * @version 1.1 + * @date 16. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 16.06.2022 17:21:32 + * from File 'svd-test/R7FA2A1AB.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA2A1AB + * @{ + */ + +#ifndef R7FA2A1AB_H + #define R7FA2A1AB_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M23 Processor and Core Peripherals =========================== */ + #define __CM23_REV 0x0100U /*!< CM23 Core Revision */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 0 /*!< FPU present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm23.h" /*!< ARM Cortex-M23 processor and core peripherals */ + #include "system.h" /*!< R7FA2A1AB System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) + */ +typedef struct +{ + __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ + __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ + __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ +} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ + +/** + * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ + + struct + { + __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ + uint8_t : 3; + } P_b; + }; + + union + { + __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ + + struct + { + __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ + uint8_t : 3; + } N_b; + }; +} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 8-Bit D/A Converter (R_DAC8) + */ + +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ +{ + union + { + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + + struct + { + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + + struct + { + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + + struct + { + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; + }; + + union + { + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; + }; +} R_DAC8_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Operational Amplifier (R_OPAMP) + */ + +typedef struct /*!< (@ 0x400867F8) R_OPAMP Structure */ +{ + __IM uint8_t RESERVED[8]; + + union + { + __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ + + struct + { + __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ + uint8_t : 4; + __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ + } AMPMC_b; + }; + + union + { + __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + + struct + { + __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger + * control */ + } AMPTRM_b; + }; + + union + { + __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select + * Register */ + + struct + { + __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the + * AMPTRS register after setting the AMPTRM register. */ + uint8_t : 6; + } AMPTRS_b; + }; + + union + { + __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ + + struct + { + __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ + __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ + __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ + __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ + uint8_t : 3; + __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference + * current circuit */ + } AMPC_b; + }; + + union + { + __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + + struct + { + __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ + __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ + __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ + __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ + uint8_t : 4; + } AMPMON_b; + }; + __IM uint8_t RESERVED1; + __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier + * [0..3] */ + + union + { + __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control + * register */ + + struct + { + __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ + __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ + __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ + uint8_t : 5; + } AMPCPC_b; + }; + __IM uint8_t RESERVED2[4]; + + union + { + __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable + * Register */ + + struct + { + __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ + __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ + __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ + uint8_t : 5; + } AMPUOTE_b; + }; + __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ +} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_SDADC0 (R_SDADC0) + */ + +typedef struct /*!< (@ 0x4009C000) R_SDADC0 Structure */ +{ + union + { + __IOM uint16_t STC1; /*!< (@ 0x00000000) Startup Control Register 1 */ + + struct + { + __IOM uint16_t CLKDIV : 4; /*!< [3..0] SDADC24 Reference Clock Division */ + uint16_t : 3; + __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select */ + __IOM uint16_t VSBIAS : 4; /*!< [11..8] Reference voltage select */ + uint16_t : 3; + __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select */ + } STC1_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t STC2; /*!< (@ 0x00000004) Startup Control Register 2 */ + + struct + { + __IOM uint8_t BGRPON : 1; /*!< [0..0] BGR part power control */ + __IOM uint8_t ADCPON : 1; /*!< [1..1] ADREG forced power-down */ + __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part */ + uint8_t : 5; + } STC2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint32_t PGAC[5]; /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register */ + + struct + { + __IOM uint32_t PGAGC : 5; /*!< [4..0] Gain selection of a programmable gain instrumentation + * amplifier ( Gset1, Gset2, Gtotal ) */ + __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select */ + __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select */ + uint32_t : 1; + __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select */ + __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select */ + __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count + * (N) in AUTOSCAN */ + __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged */ + __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing */ + __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select */ + uint32_t : 1; + __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable */ + __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of + * A/D conversions in ADSCAN */ + } PGAC_b[5]; + }; + + union + { + __IOM uint32_t ADC1; /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1 */ + + struct + { + __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode */ + uint32_t : 3; + __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal */ + uint32_t : 3; + __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer */ + uint32_t : 3; + __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection */ + __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting */ + uint32_t : 2; + __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable */ + uint32_t : 11; + } ADC1_b; + }; + + union + { + __IOM uint8_t ADC2; /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2 */ + + struct + { + __IOM uint8_t SDADST : 1; /*!< [0..0] Control of A/D conversion */ + uint8_t : 7; + } ADC2_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint32_t ADCR; /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register */ + + struct + { + __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result */ + __IM uint32_t SDADCRS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADCRC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADCR_b; + }; + + union + { + __IM uint32_t ADAR; /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register */ + + struct + { + __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value */ + __IM uint32_t SDADMVS : 1; /*!< [24..24] Status of an A/D conversion result */ + __IM uint32_t SDADMVC : 3; /*!< [27..25] Channel number for an A/D conversion result */ + uint32_t : 4; + } ADAR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t CLBC; /*!< (@ 0x00000030) Calibration Control Register */ + + struct + { + __IOM uint8_t CLBMD : 2; /*!< [1..0] These bits are read as 0. The write value should be 0. */ + uint8_t : 6; + } CLBC_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t CLBSTR; /*!< (@ 0x00000034) Calibration Start Control Register */ + + struct + { + __IOM uint8_t CLBST : 1; /*!< [0..0] Calibration start control */ + uint8_t : 7; + } CLBSTR_b; + }; + __IM uint8_t RESERVED8; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10; + + union + { + __IM uint8_t CLBSSR; /*!< (@ 0x0000003C) Calibration Status Register */ + + struct + { + __IM uint8_t CLBSS : 1; /*!< [0..0] Calibration status */ + uint8_t : 7; + } CLBSSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; +} R_SDADC0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DAC8_BASE 0x4009E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_OPAMP_BASE 0x400867F8UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDADC0_BASE 0x4009C000UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDADC0 ((R_SDADC0_Type *) R_SDADC0_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ AMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OS =========================================================== */ +/* ========================================================== PS =========================================================== */ +/* ========================================================== MS =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ AMPOT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_OPAMP_AMPOT_P_TRMP_Pos (0UL) /*!< TRMP (Bit 0) */ + #define R_OPAMP_AMPOT_P_TRMP_Msk (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f) */ +/* =========================================================== N =========================================================== */ + #define R_OPAMP_AMPOT_N_TRMN_Pos (0UL) /*!< TRMN (Bit 0) */ + #define R_OPAMP_AMPOT_N_TRMN_Msk (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DAM ========================================================== */ + #define R_DAC8_DAM_DACE1_Pos (5UL) /*!< DACE1 (Bit 5) */ + #define R_DAC8_DAM_DACE1_Msk (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DACE0_Pos (4UL) /*!< DACE0 (Bit 4) */ + #define R_DAC8_DAM_DACE0_Msk (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD1_Pos (1UL) /*!< DAMD1 (Bit 1) */ + #define R_DAC8_DAM_DAMD1_Msk (0x2UL) /*!< DAMD1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD0_Pos (0UL) /*!< DAMD0 (Bit 0) */ + #define R_DAC8_DAM_DAMD0_Msk (0x1UL) /*!< DAMD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= DACS ========================================================== */ + #define R_DAC8_DACS_DACS_Pos (0UL) /*!< DACS (Bit 0) */ + #define R_DAC8_DACS_DACS_Msk (0xffUL) /*!< DACS (Bitfield-Mask: 0xff) */ +/* ======================================================= DACADSCR ======================================================== */ + #define R_DAC8_DACADSCR_DACADST_Pos (0UL) /*!< DACADST (Bit 0) */ + #define R_DAC8_DACADSCR_DACADST_Msk (0x1UL) /*!< DACADST (Bitfield-Mask: 0x01) */ +/* ========================================================= DACPC ========================================================= */ + #define R_DAC8_DACPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC8_DACPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AMPMC ========================================================= */ + #define R_OPAMP_AMPMC_AMPSP_Pos (7UL) /*!< AMPSP (Bit 7) */ + #define R_OPAMP_AMPMC_AMPSP_Msk (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPMC_AMPPC_Pos (0UL) /*!< AMPPC (Bit 0) */ + #define R_OPAMP_AMPMC_AMPPC_Msk (0x1UL) /*!< AMPPC (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPTRM ========================================================= */ + #define R_OPAMP_AMPTRM_AMPTRM_Pos (0UL) /*!< AMPTRM (Bit 0) */ + #define R_OPAMP_AMPTRM_AMPTRM_Msk (0x3UL) /*!< AMPTRM (Bitfield-Mask: 0x03) */ +/* ======================================================== AMPTRS ========================================================= */ + #define R_OPAMP_AMPTRS_AMPTRS_Pos (0UL) /*!< AMPTRS (Bit 0) */ + #define R_OPAMP_AMPTRS_AMPTRS_Msk (0x3UL) /*!< AMPTRS (Bitfield-Mask: 0x03) */ +/* ========================================================= AMPC ========================================================== */ + #define R_OPAMP_AMPC_IREFE_Pos (7UL) /*!< IREFE (Bit 7) */ + #define R_OPAMP_AMPC_IREFE_Msk (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPC_AMPE_Pos (0UL) /*!< AMPE (Bit 0) */ + #define R_OPAMP_AMPC_AMPE_Msk (0x1UL) /*!< AMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPMON ========================================================= */ + #define R_OPAMP_AMPMON_AMPMON_Pos (0UL) /*!< AMPMON (Bit 0) */ + #define R_OPAMP_AMPMON_AMPMON_Msk (0x1UL) /*!< AMPMON (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPCPC ========================================================= */ + #define R_OPAMP_AMPCPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_OPAMP_AMPCPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPUOTE ======================================================== */ + #define R_OPAMP_AMPUOTE_AMPTE_Pos (0UL) /*!< AMPTE (Bit 0) */ + #define R_OPAMP_AMPUOTE_AMPTE_Msk (0x1UL) /*!< AMPTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STC1 ========================================================== */ + #define R_SDADC0_STC1_VSBIAS_Pos (8UL) /*!< VSBIAS (Bit 8) */ + #define R_SDADC0_STC1_VSBIAS_Msk (0xf00UL) /*!< VSBIAS (Bitfield-Mask: 0x0f) */ + #define R_SDADC0_STC1_CLKDIV_Pos (0UL) /*!< CLKDIV (Bit 0) */ + #define R_SDADC0_STC1_CLKDIV_Msk (0xfUL) /*!< CLKDIV (Bitfield-Mask: 0x0f) */ + #define R_SDADC0_STC1_SDADLPM_Pos (7UL) /*!< SDADLPM (Bit 7) */ + #define R_SDADC0_STC1_SDADLPM_Msk (0x80UL) /*!< SDADLPM (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC1_VREFSEL_Pos (15UL) /*!< VREFSEL (Bit 15) */ + #define R_SDADC0_STC1_VREFSEL_Msk (0x8000UL) /*!< VREFSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= STC2 ========================================================== */ + #define R_SDADC0_STC2_BGRPON_Pos (0UL) /*!< BGRPON (Bit 0) */ + #define R_SDADC0_STC2_BGRPON_Msk (0x1UL) /*!< BGRPON (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC2_ADFPWDS_Pos (2UL) /*!< ADFPWDS (Bit 2) */ + #define R_SDADC0_STC2_ADFPWDS_Msk (0x4UL) /*!< ADFPWDS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_STC2_ADCPON_Pos (1UL) /*!< ADCPON (Bit 1) */ + #define R_SDADC0_STC2_ADCPON_Msk (0x2UL) /*!< ADCPON (Bitfield-Mask: 0x01) */ +/* ========================================================= PGAC ========================================================== */ + #define R_SDADC0_PGAC_PGAASN_Pos (31UL) /*!< PGAASN (Bit 31) */ + #define R_SDADC0_PGAC_PGAASN_Msk (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGACVE_Pos (30UL) /*!< PGACVE (Bit 30) */ + #define R_SDADC0_PGAC_PGACVE_Msk (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAREV_Pos (28UL) /*!< PGAREV (Bit 28) */ + #define R_SDADC0_PGAC_PGAREV_Msk (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAAVE_Pos (26UL) /*!< PGAAVE (Bit 26) */ + #define R_SDADC0_PGAC_PGAAVE_Msk (0xc000000UL) /*!< PGAAVE (Bitfield-Mask: 0x03) */ + #define R_SDADC0_PGAC_PGAAVN_Pos (24UL) /*!< PGAAVN (Bit 24) */ + #define R_SDADC0_PGAC_PGAAVN_Msk (0x3000000UL) /*!< PGAAVN (Bitfield-Mask: 0x03) */ + #define R_SDADC0_PGAC_PGACTN_Pos (21UL) /*!< PGACTN (Bit 21) */ + #define R_SDADC0_PGAC_PGACTN_Msk (0xe00000UL) /*!< PGACTN (Bitfield-Mask: 0x07) */ + #define R_SDADC0_PGAC_PGACTM_Pos (16UL) /*!< PGACTM (Bit 16) */ + #define R_SDADC0_PGAC_PGACTM_Msk (0x1f0000UL) /*!< PGACTM (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_PGAC_PGASEL_Pos (15UL) /*!< PGASEL (Bit 15) */ + #define R_SDADC0_PGAC_PGASEL_Msk (0x8000UL) /*!< PGASEL (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAPOL_Pos (14UL) /*!< PGAPOL (Bit 14) */ + #define R_SDADC0_PGAC_PGAPOL_Msk (0x4000UL) /*!< PGAPOL (Bitfield-Mask: 0x01) */ + #define R_SDADC0_PGAC_PGAOFS_Pos (8UL) /*!< PGAOFS (Bit 8) */ + #define R_SDADC0_PGAC_PGAOFS_Msk (0x1f00UL) /*!< PGAOFS (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_PGAC_PGAOSR_Pos (5UL) /*!< PGAOSR (Bit 5) */ + #define R_SDADC0_PGAC_PGAOSR_Msk (0xe0UL) /*!< PGAOSR (Bitfield-Mask: 0x07) */ + #define R_SDADC0_PGAC_PGAGC_Pos (0UL) /*!< PGAGC (Bit 0) */ + #define R_SDADC0_PGAC_PGAGC_Msk (0x1fUL) /*!< PGAGC (Bitfield-Mask: 0x1f) */ +/* ========================================================= ADC1 ========================================================== */ + #define R_SDADC0_ADC1_PGASLFT_Pos (20UL) /*!< PGASLFT (Bit 20) */ + #define R_SDADC0_ADC1_PGASLFT_Msk (0x100000UL) /*!< PGASLFT (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_PGADISC_Pos (17UL) /*!< PGADISC (Bit 17) */ + #define R_SDADC0_ADC1_PGADISC_Msk (0x20000UL) /*!< PGADISC (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_PGADISA_Pos (16UL) /*!< PGADISA (Bit 16) */ + #define R_SDADC0_ADC1_PGADISA_Msk (0x10000UL) /*!< PGADISA (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_SDADBMP_Pos (8UL) /*!< SDADBMP (Bit 8) */ + #define R_SDADC0_ADC1_SDADBMP_Msk (0x1f00UL) /*!< SDADBMP (Bitfield-Mask: 0x1f) */ + #define R_SDADC0_ADC1_SDADTMD_Pos (4UL) /*!< SDADTMD (Bit 4) */ + #define R_SDADC0_ADC1_SDADTMD_Msk (0x10UL) /*!< SDADTMD (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADC1_SDADSCM_Pos (0UL) /*!< SDADSCM (Bit 0) */ + #define R_SDADC0_ADC1_SDADSCM_Msk (0x1UL) /*!< SDADSCM (Bitfield-Mask: 0x01) */ +/* ========================================================= ADC2 ========================================================== */ + #define R_SDADC0_ADC2_SDADST_Pos (0UL) /*!< SDADST (Bit 0) */ + #define R_SDADC0_ADC2_SDADST_Msk (0x1UL) /*!< SDADST (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCR ========================================================== */ + #define R_SDADC0_ADCR_SDADCRC_Pos (25UL) /*!< SDADCRC (Bit 25) */ + #define R_SDADC0_ADCR_SDADCRC_Msk (0xe000000UL) /*!< SDADCRC (Bitfield-Mask: 0x07) */ + #define R_SDADC0_ADCR_SDADCRS_Pos (24UL) /*!< SDADCRS (Bit 24) */ + #define R_SDADC0_ADCR_SDADCRS_Msk (0x1000000UL) /*!< SDADCRS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADCR_SDADCRD_Pos (0UL) /*!< SDADCRD (Bit 0) */ + #define R_SDADC0_ADCR_SDADCRD_Msk (0xffffffUL) /*!< SDADCRD (Bitfield-Mask: 0xffffff) */ +/* ========================================================= ADAR ========================================================== */ + #define R_SDADC0_ADAR_SDADMVC_Pos (25UL) /*!< SDADMVC (Bit 25) */ + #define R_SDADC0_ADAR_SDADMVC_Msk (0xe000000UL) /*!< SDADMVC (Bitfield-Mask: 0x07) */ + #define R_SDADC0_ADAR_SDADMVS_Pos (24UL) /*!< SDADMVS (Bit 24) */ + #define R_SDADC0_ADAR_SDADMVS_Msk (0x1000000UL) /*!< SDADMVS (Bitfield-Mask: 0x01) */ + #define R_SDADC0_ADAR_SDADMVD_Pos (0UL) /*!< SDADMVD (Bit 0) */ + #define R_SDADC0_ADAR_SDADMVD_Msk (0xffffffUL) /*!< SDADMVD (Bitfield-Mask: 0xffffff) */ +/* ========================================================= CLBC ========================================================== */ + #define R_SDADC0_CLBC_CLBMD_Pos (0UL) /*!< CLBMD (Bit 0) */ + #define R_SDADC0_CLBC_CLBMD_Msk (0x3UL) /*!< CLBMD (Bitfield-Mask: 0x03) */ +/* ======================================================== CLBSTR ========================================================= */ + #define R_SDADC0_CLBSTR_CLBST_Pos (0UL) /*!< CLBST (Bit 0) */ + #define R_SDADC0_CLBSTR_CLBST_Msk (0x1UL) /*!< CLBST (Bitfield-Mask: 0x01) */ +/* ======================================================== CLBSSR ========================================================= */ + #define R_SDADC0_CLBSSR_CLBSS_Pos (0UL) /*!< CLBSS (Bit 0) */ + #define R_SDADC0_CLBSSR_CLBSS_Msk (0x1UL) /*!< CLBSS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA2A1AB_H */ + +/** @} */ /* End of group R7FA2A1AB */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h new file mode 100644 index 00000000..b923e93c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h @@ -0,0 +1,14460 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA2E1A9.h + * @brief CMSIS HeaderFile + * @version 1.20.01 + * @date 16. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 16.06.2022 17:21:33 + * from File 'svd-test/R7FA2E1A9.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA2E1A9 + * @{ + */ + +#ifndef R7FA2E1A9_H + #define R7FA2E1A9_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M23 Processor and Core Peripherals =========================== */ + #define __CM23_REV 0x0100U /*!< CM23 Core Revision */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 0 /*!< FPU present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm23.h" /*!< ARM Cortex-M23 processor and core peripherals */ + #include "system.h" /*!< R7FA2E1A9 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU2) + */ + +typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ +{ + union + { + union + { + __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ + __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ + __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ + __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power On Control */ + __IOM uint32_t CSW : 1; /*!< [9..9] TSCAP Pin Enable */ + __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ + __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ + __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ + __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ + __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ + __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ + __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ + __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Load Control During Measurement */ + __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ + __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ + __IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */ + __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ + __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ + __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ + } CTSUCRA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ + }; + }; + + union + { + __IOM uint16_t CTSUCRAH; /*!< (@ 0x00000002) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ + __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control */ + __IOM uint32_t PRMODE : 2; /*!< [5..4] Phase Control Period */ + __IOM uint32_t SOFF : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable */ + __IOM uint32_t PROFF : 1; /*!< [7..7] Drive Pulse Phase Control */ + __IOM uint32_t SST : 8; /*!< [15..8] Wait Time Sensor Stabilization */ + uint32_t : 8; + __IOM uint32_t SSMOD : 3; /*!< [26..24] Spread Spectrum Modulation Frequency */ + uint32_t : 1; + __IOM uint32_t SSCNT : 2; /*!< [29..28] Adjusting the SUCLK frequency */ + uint32_t : 2; + } CTSUCRB_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ + }; + }; + + union + { + __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ + + struct + { + __IM uint8_t RESERVED; + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ + uint32_t : 2; + __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ + uint32_t : 2; + __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ + uint32_t : 12; + } CTSUMCH_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ + }; + }; + + union + { + __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ + uint32_t : 2; + __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ + } CTSUCHACA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + + struct + { + __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ + uint32_t : 28; + } CTSUCHACB_b; + }; + __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ + uint32_t : 2; + __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ + } CTSUCHTRCA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + + struct + { + __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ + uint32_t : 28; + } CTSUCHTRCB_b; + }; + __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + }; + + union + { + union + { + __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ + uint32_t : 3; + __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ + __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ + __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ + __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ + uint32_t : 1; + __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ + __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ + __IOM uint32_t SUOVF : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag */ + __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ + __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ + uint32_t : 10; + } CTSUSR_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ + }; + }; + + union + { + __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ + __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ + __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ + uint32_t : 2; + __IOM uint32_t SSDIV : 4; /*!< [23..20] Spread Spectrum Frequency */ + __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ + } CTSUSO_b; + }; + + struct + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + + struct + { + __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ + __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter */ + } CTSUSCNT_b; + }; + __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + }; + + union + { + union + { + __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TSOD : 1; /*!< [2..2] TS Pins Fixed Output */ + __IOM uint32_t DRV : 1; /*!< [3..3] Power Supply Calibration Select */ + __IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select */ + __IOM uint32_t SUCLKEN : 1; /*!< [6..6] SUCLK Forced Oscillation Control */ + __IOM uint32_t TSOC : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit */ + __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter */ + __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */ + __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */ + __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */ + uint32_t : 4; + __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */ + __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */ + uint32_t : 1; + __IOM uint32_t DACMSEL : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select */ + __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration */ + __IOM uint32_t SUMSEL : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration + * Select */ + __IOM uint32_t SUCARRY : 1; /*!< [27..27] Current Control Oscillator Input Current Adjustment + * for SUCLK */ + __IOM uint32_t DACCLK : 1; /*!< [28..28] Modulation Clock Select for Offset Current Circuits */ + __IOM uint32_t CCOCLK : 1; /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator + * Input Current of SUCLK */ + __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator + * for Measurement */ + __IOM uint32_t TXREV : 1; /*!< [31..31] Transmit Pin Inverted Output */ + } CTSUCALIB_b; + }; + + struct + { + __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + + struct + { + __IOM uint32_t SUADJ0 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ1 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKA_b; + }; + + struct + { + __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + + struct + { + __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKB_b; + }; + + struct + { + __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + + struct + { + __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ + uint32_t : 16; + } CTSUCFCCNT_b; + }; + __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + }; +} R_CTSU2_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSUTRIM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CTSU Trimming Registers (R_CTSUTRIM) + */ + +typedef struct /*!< (@ 0x407EC000) R_CTSUTRIM Structure */ +{ + __IM uint32_t RESERVED[233]; + + union + { + __IOM uint32_t CTSUTRIMA; /*!< (@ 0x000003A4) CTSU Trimming Register A */ + + struct + { + __IOM uint32_t RTRIM : 8; /*!< [7..0] CTSU Reference Resistance Adjustment */ + __IOM uint32_t DACTRIM : 8; /*!< [15..8] Linearity Adjustment of Offset Current */ + __IOM uint32_t SUADJD : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (120k) */ + } CTSUTRIMA_b; + }; + + union + { + __IOM uint32_t CTSUTRIMB; /*!< (@ 0x000003A8) CTSU Trimming Register B */ + + struct + { + __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance + * (7.5k) */ + __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance + * (15k) */ + __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance + * (30k) */ + __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (60k) */ + } CTSUTRIMB_b; + }; +} R_CTSUTRIM_Type; /*!< Size = 940 (0x3ac) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU2_BASE 0x40082000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_CTSUTRIM_BASE 0x407EC000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCRA ======================================================== */ + #define R_CTSU2_CTSUCRA_STRT_Pos (0UL) /*!< STRT (Bit 0) */ + #define R_CTSU2_CTSUCRA_STRT_Msk (0x1UL) /*!< STRT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CAP_Pos (1UL) /*!< CAP (Bit 1) */ + #define R_CTSU2_CTSUCRA_CAP_Msk (0x2UL) /*!< CAP (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_SNZ_Pos (2UL) /*!< SNZ (Bit 2) */ + #define R_CTSU2_CTSUCRA_SNZ_Msk (0x4UL) /*!< SNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CFCON_Pos (3UL) /*!< CFCON (Bit 3) */ + #define R_CTSU2_CTSUCRA_CFCON_Msk (0x8UL) /*!< CFCON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_INIT_Pos (4UL) /*!< INIT (Bit 4) */ + #define R_CTSU2_CTSUCRA_INIT_Msk (0x10UL) /*!< INIT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_PUMPON_Pos (5UL) /*!< PUMPON (Bit 5) */ + #define R_CTSU2_CTSUCRA_PUMPON_Msk (0x20UL) /*!< PUMPON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Pos (6UL) /*!< TXVSEL (Bit 6) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Msk (0xc0UL) /*!< TXVSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_PON_Pos (8UL) /*!< PON (Bit 8) */ + #define R_CTSU2_CTSUCRA_PON_Msk (0x100UL) /*!< PON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CSW_Pos (9UL) /*!< CSW (Bit 9) */ + #define R_CTSU2_CTSUCRA_CSW_Msk (0x200UL) /*!< CSW (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Pos (10UL) /*!< ATUNE0 (Bit 10) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Msk (0x400UL) /*!< ATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Pos (11UL) /*!< ATUNE1 (Bit 11) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Msk (0x800UL) /*!< ATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CLK_Pos (12UL) /*!< CLK (Bit 12) */ + #define R_CTSU2_CTSUCRA_CLK_Msk (0x3000UL) /*!< CLK (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_MD0_Pos (14UL) /*!< MD0 (Bit 14) */ + #define R_CTSU2_CTSUCRA_MD0_Msk (0x4000UL) /*!< MD0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD1_Pos (15UL) /*!< MD1 (Bit 15) */ + #define R_CTSU2_CTSUCRA_MD1_Msk (0x8000UL) /*!< MD1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD2_Pos (16UL) /*!< MD2 (Bit 16) */ + #define R_CTSU2_CTSUCRA_MD2_Msk (0x10000UL) /*!< MD2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Pos (17UL) /*!< ATUNE2 (Bit 17) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Msk (0x20000UL) /*!< ATUNE2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_LOAD_Pos (18UL) /*!< LOAD (Bit 18) */ + #define R_CTSU2_CTSUCRA_LOAD_Msk (0xc0000UL) /*!< LOAD (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_POSEL_Pos (20UL) /*!< POSEL (Bit 20) */ + #define R_CTSU2_CTSUCRA_POSEL_Msk (0x300000UL) /*!< POSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Pos (22UL) /*!< SDPSEL (Bit 22) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Msk (0x400000UL) /*!< SDPSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_PCSEL_Pos (23UL) /*!< PCSEL (Bit 23) */ + #define R_CTSU2_CTSUCRA_PCSEL_Msk (0x800000UL) /*!< PCSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_STCLK_Pos (24UL) /*!< STCLK (Bit 24) */ + #define R_CTSU2_CTSUCRA_STCLK_Msk (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUCRA_DCMODE_Pos (30UL) /*!< DCMODE (Bit 30) */ + #define R_CTSU2_CTSUCRA_DCMODE_Msk (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_DCBACK_Pos (31UL) /*!< DCBACK (Bit 31) */ + #define R_CTSU2_CTSUCRA_DCBACK_Msk (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCRAL ======================================================== */ +/* ======================================================== CTSUCR0 ======================================================== */ +/* ======================================================== CTSUCR1 ======================================================== */ +/* ======================================================= CTSUCRAH ======================================================== */ +/* ======================================================== CTSUCR2 ======================================================== */ +/* ======================================================== CTSUCR3 ======================================================== */ +/* ======================================================== CTSUCRB ======================================================== */ + #define R_CTSU2_CTSUCRB_PRRATIO_Pos (0UL) /*!< PRRATIO (Bit 0) */ + #define R_CTSU2_CTSUCRB_PRRATIO_Msk (0xfUL) /*!< PRRATIO (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUCRB_PRMODE_Pos (4UL) /*!< PRMODE (Bit 4) */ + #define R_CTSU2_CTSUCRB_PRMODE_Msk (0x30UL) /*!< PRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRB_SOFF_Pos (6UL) /*!< SOFF (Bit 6) */ + #define R_CTSU2_CTSUCRB_SOFF_Msk (0x40UL) /*!< SOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_PROFF_Pos (7UL) /*!< PROFF (Bit 7) */ + #define R_CTSU2_CTSUCRB_PROFF_Msk (0x80UL) /*!< PROFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_SST_Pos (8UL) /*!< SST (Bit 8) */ + #define R_CTSU2_CTSUCRB_SST_Msk (0xff00UL) /*!< SST (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUCRB_SSMOD_Pos (24UL) /*!< SSMOD (Bit 24) */ + #define R_CTSU2_CTSUCRB_SSMOD_Msk (0x7000000UL) /*!< SSMOD (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUCRB_SSCNT_Pos (28UL) /*!< SSCNT (Bit 28) */ + #define R_CTSU2_CTSUCRB_SSCNT_Msk (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= CTSUCRBL ======================================================== */ +/* ======================================================= CTSUSDPRS ======================================================= */ +/* ======================================================== CTSUSST ======================================================== */ +/* ======================================================= CTSUCRBH ======================================================== */ +/* ======================================================= CTSUDCLKC ======================================================= */ +/* ======================================================== CTSUMCH ======================================================== */ + #define R_CTSU2_CTSUMCH_MCH0_Pos (0UL) /*!< MCH0 (Bit 0) */ + #define R_CTSU2_CTSUMCH_MCH0_Msk (0x3fUL) /*!< MCH0 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCH1_Pos (8UL) /*!< MCH1 (Bit 8) */ + #define R_CTSU2_CTSUMCH_MCH1_Msk (0x3f00UL) /*!< MCH1 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCA0_Pos (16UL) /*!< MCA0 (Bit 16) */ + #define R_CTSU2_CTSUMCH_MCA0_Msk (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA1_Pos (17UL) /*!< MCA1 (Bit 17) */ + #define R_CTSU2_CTSUMCH_MCA1_Msk (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA2_Pos (18UL) /*!< MCA2 (Bit 18) */ + #define R_CTSU2_CTSUMCH_MCA2_Msk (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA3_Pos (19UL) /*!< MCA3 (Bit 19) */ + #define R_CTSU2_CTSUMCH_MCA3_Msk (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUMCHL ======================================================== */ +/* ======================================================= CTSUMCH0 ======================================================== */ +/* ======================================================= CTSUMCH1 ======================================================== */ +/* ======================================================= CTSUMCHH ======================================================== */ +/* ======================================================= CTSUMFAF ======================================================== */ +/* ======================================================= CTSUCHACA ======================================================= */ + #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */ + #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Msk (0x20UL) /*!< CHAC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Pos (6UL) /*!< CHAC06 (Bit 6) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Msk (0x40UL) /*!< CHAC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Pos (7UL) /*!< CHAC07 (Bit 7) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Msk (0x80UL) /*!< CHAC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Pos (8UL) /*!< CHAC08 (Bit 8) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Msk (0x100UL) /*!< CHAC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Pos (9UL) /*!< CHAC09 (Bit 9) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Msk (0x200UL) /*!< CHAC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Pos (10UL) /*!< CHAC10 (Bit 10) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Msk (0x400UL) /*!< CHAC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Pos (11UL) /*!< CHAC11 (Bit 11) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Msk (0x800UL) /*!< CHAC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Pos (12UL) /*!< CHAC12 (Bit 12) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Msk (0x1000UL) /*!< CHAC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Pos (13UL) /*!< CHAC13 (Bit 13) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Msk (0x2000UL) /*!< CHAC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Pos (14UL) /*!< CHAC14 (Bit 14) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Msk (0x4000UL) /*!< CHAC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Pos (15UL) /*!< CHAC15 (Bit 15) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Msk (0x8000UL) /*!< CHAC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Pos (16UL) /*!< CHAC16 (Bit 16) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Msk (0x10000UL) /*!< CHAC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Pos (17UL) /*!< CHAC17 (Bit 17) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Msk (0x20000UL) /*!< CHAC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Pos (18UL) /*!< CHAC18 (Bit 18) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Msk (0x40000UL) /*!< CHAC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Pos (21UL) /*!< CHAC21 (Bit 21) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Msk (0x200000UL) /*!< CHAC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Pos (22UL) /*!< CHAC22 (Bit 22) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Msk (0x400000UL) /*!< CHAC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Pos (23UL) /*!< CHAC23 (Bit 23) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Msk (0x800000UL) /*!< CHAC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Pos (24UL) /*!< CHAC24 (Bit 24) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Msk (0x1000000UL) /*!< CHAC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Pos (25UL) /*!< CHAC25 (Bit 25) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Msk (0x2000000UL) /*!< CHAC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Pos (26UL) /*!< CHAC26 (Bit 26) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Msk (0x4000000UL) /*!< CHAC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Pos (27UL) /*!< CHAC27 (Bit 27) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Msk (0x8000000UL) /*!< CHAC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Pos (28UL) /*!< CHAC28 (Bit 28) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Msk (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Pos (29UL) /*!< CHAC29 (Bit 29) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Msk (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Pos (30UL) /*!< CHAC30 (Bit 30) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Msk (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Pos (31UL) /*!< CHAC31 (Bit 31) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Msk (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACAL ======================================================= */ +/* ======================================================= CTSUCHAC0 ======================================================= */ +/* ======================================================= CTSUCHAC1 ======================================================= */ +/* ====================================================== CTSUCHACAH ======================================================= */ +/* ======================================================= CTSUCHAC2 ======================================================= */ +/* ======================================================= CTSUCHAC3 ======================================================= */ +/* ======================================================= CTSUCHACB ======================================================= */ + #define R_CTSU2_CTSUCHACB_CHAC32_Pos (0UL) /*!< CHAC32 (Bit 0) */ + #define R_CTSU2_CTSUCHACB_CHAC32_Msk (0x1UL) /*!< CHAC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Pos (1UL) /*!< CHAC33 (Bit 1) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Msk (0x2UL) /*!< CHAC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Pos (2UL) /*!< CHAC34 (Bit 2) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Msk (0x4UL) /*!< CHAC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Pos (3UL) /*!< CHAC35 (Bit 3) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Msk (0x8UL) /*!< CHAC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACBL ======================================================= */ +/* ======================================================= CTSUCHAC4 ======================================================= */ +/* ====================================================== CTSUCHTRCA ======================================================= */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk (0x20UL) /*!< CHTRC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos (6UL) /*!< CHTRC06 (Bit 6) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk (0x40UL) /*!< CHTRC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos (7UL) /*!< CHTRC07 (Bit 7) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk (0x80UL) /*!< CHTRC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos (8UL) /*!< CHTRC08 (Bit 8) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk (0x100UL) /*!< CHTRC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos (9UL) /*!< CHTRC09 (Bit 9) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk (0x200UL) /*!< CHTRC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos (10UL) /*!< CHTRC10 (Bit 10) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk (0x400UL) /*!< CHTRC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos (11UL) /*!< CHTRC11 (Bit 11) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk (0x800UL) /*!< CHTRC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos (12UL) /*!< CHTRC12 (Bit 12) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk (0x1000UL) /*!< CHTRC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos (13UL) /*!< CHTRC13 (Bit 13) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk (0x2000UL) /*!< CHTRC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos (14UL) /*!< CHTRC14 (Bit 14) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk (0x4000UL) /*!< CHTRC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos (15UL) /*!< CHTRC15 (Bit 15) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk (0x8000UL) /*!< CHTRC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos (16UL) /*!< CHTRC16 (Bit 16) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk (0x10000UL) /*!< CHTRC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos (17UL) /*!< CHTRC17 (Bit 17) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk (0x20000UL) /*!< CHTRC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos (18UL) /*!< CHTRC18 (Bit 18) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk (0x40000UL) /*!< CHTRC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos (21UL) /*!< CHTRC21 (Bit 21) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk (0x200000UL) /*!< CHTRC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos (22UL) /*!< CHTRC22 (Bit 22) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk (0x400000UL) /*!< CHTRC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos (23UL) /*!< CHTRC23 (Bit 23) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk (0x800000UL) /*!< CHTRC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos (24UL) /*!< CHTRC24 (Bit 24) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk (0x1000000UL) /*!< CHTRC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos (25UL) /*!< CHTRC25 (Bit 25) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk (0x2000000UL) /*!< CHTRC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos (26UL) /*!< CHTRC26 (Bit 26) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk (0x4000000UL) /*!< CHTRC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos (27UL) /*!< CHTRC27 (Bit 27) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk (0x8000000UL) /*!< CHTRC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos (28UL) /*!< CHTRC28 (Bit 28) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos (29UL) /*!< CHTRC29 (Bit 29) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos (30UL) /*!< CHTRC30 (Bit 30) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos (31UL) /*!< CHTRC31 (Bit 31) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCAL ====================================================== */ +/* ====================================================== CTSUCHTRC0 ======================================================= */ +/* ====================================================== CTSUCHTRC1 ======================================================= */ +/* ====================================================== CTSUCHTRCAH ====================================================== */ +/* ====================================================== CTSUCHTRC2 ======================================================= */ +/* ====================================================== CTSUCHTRC3 ======================================================= */ +/* ====================================================== CTSUCHTRCB ======================================================= */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos (0UL) /*!< CHTRC32 (Bit 0) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk (0x1UL) /*!< CHTRC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos (1UL) /*!< CHTRC33 (Bit 1) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk (0x2UL) /*!< CHTRC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos (2UL) /*!< CHTRC34 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk (0x4UL) /*!< CHTRC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos (3UL) /*!< CHTRC35 (Bit 3) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk (0x8UL) /*!< CHTRC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCBL ====================================================== */ +/* ====================================================== CTSUCHTRC4 ======================================================= */ +/* ======================================================== CTSUSR ========================================================= */ + #define R_CTSU2_CTSUSR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_CTSU2_CTSUSR_MFC_Msk (0x3UL) /*!< MFC (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Pos (5UL) /*!< ICOMPRST (Bit 5) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Msk (0x20UL) /*!< ICOMPRST (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP1_Pos (6UL) /*!< ICOMP1 (Bit 6) */ + #define R_CTSU2_CTSUSR_ICOMP1_Msk (0x40UL) /*!< ICOMP1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP0_Pos (7UL) /*!< ICOMP0 (Bit 7) */ + #define R_CTSU2_CTSUSR_ICOMP0_Msk (0x80UL) /*!< ICOMP0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_STC_Pos (8UL) /*!< STC (Bit 8) */ + #define R_CTSU2_CTSUSR_STC_Msk (0x700UL) /*!< STC (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUSR_DTSR_Pos (12UL) /*!< DTSR (Bit 12) */ + #define R_CTSU2_CTSUSR_DTSR_Msk (0x1000UL) /*!< DTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_SENSOVF_Pos (13UL) /*!< SENSOVF (Bit 13) */ + #define R_CTSU2_CTSUSR_SENSOVF_Msk (0x2000UL) /*!< SENSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_SUOVF_Pos (14UL) /*!< SUOVF (Bit 14) */ + #define R_CTSU2_CTSUSR_SUOVF_Msk (0x4000UL) /*!< SUOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_CTSU2_CTSUSR_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Pos (16UL) /*!< CFCRDCH (Bit 16) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Msk (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f) */ +/* ======================================================== CTSUSRL ======================================================== */ +/* ======================================================== CTSUSR0 ======================================================== */ +/* ======================================================== CTSUST ========================================================= */ +/* ======================================================== CTSUSRH ======================================================== */ +/* ======================================================== CTSUSR2 ======================================================== */ +/* ======================================================== CTSUSO ========================================================= */ + #define R_CTSU2_CTSUSO_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUSO_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUSO_SNUM_Pos (10UL) /*!< SNUM (Bit 10) */ + #define R_CTSU2_CTSUSO_SNUM_Msk (0x3fc00UL) /*!< SNUM (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSO_SSDIV_Pos (20UL) /*!< SSDIV (Bit 20) */ + #define R_CTSU2_CTSUSO_SSDIV_Msk (0xf00000UL) /*!< SSDIV (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUSO_SDPA_Pos (24UL) /*!< SDPA (Bit 24) */ + #define R_CTSU2_CTSUSO_SDPA_Msk (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSO0 ======================================================== */ +/* ======================================================== CTSUSO1 ======================================================== */ +/* ======================================================= CTSUSCNT ======================================================== */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Pos (0UL) /*!< SENSCNT (Bit 0) */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Msk (0xffffUL) /*!< SENSCNT (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos (16UL) /*!< SUCKCNT (Bit 16) */ + #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSUSC ========================================================= */ +/* ======================================================= CTSUCALIB ======================================================= */ + #define R_CTSU2_CTSUCALIB_TSOD_Pos (2UL) /*!< TSOD (Bit 2) */ + #define R_CTSU2_CTSUCALIB_TSOD_Msk (0x4UL) /*!< TSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DRV_Pos (3UL) /*!< DRV (Bit 3) */ + #define R_CTSU2_CTSUCALIB_DRV_Msk (0x8UL) /*!< DRV (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_CTSU2_CTSUCALIB_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos (6UL) /*!< SUCLKEN (Bit 6) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk (0x40UL) /*!< SUCLKEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_TSOC_Pos (7UL) /*!< TSOC (Bit 7) */ + #define R_CTSU2_CTSUCALIB_TSOC_Msk (0x80UL) /*!< TSOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos (8UL) /*!< CNTRDSEL (Bit 8) */ + #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk (0x100UL) /*!< CNTRDSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_IOC_Pos (9UL) /*!< IOC (Bit 9) */ + #define R_CTSU2_CTSUCALIB_IOC_Msk (0x200UL) /*!< IOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos (10UL) /*!< CFCRDMD (Bit 10) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCSEL_Pos (16UL) /*!< CFCSEL (Bit 16) */ + #define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Msk (0x400000UL) /*!< CFCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACMSEL_Pos (24UL) /*!< DACMSEL (Bit 24) */ + #define R_CTSU2_CTSUCALIB_DACMSEL_Msk (0x1000000UL) /*!< DACMSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Pos (25UL) /*!< DACCARRY (Bit 25) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Msk (0x2000000UL) /*!< DACCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUMSEL_Pos (26UL) /*!< SUMSEL (Bit 26) */ + #define R_CTSU2_CTSUCALIB_SUMSEL_Msk (0x4000000UL) /*!< SUMSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Pos (27UL) /*!< SUCARRY (Bit 27) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Msk (0x8000000UL) /*!< SUCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Pos (28UL) /*!< DACCLK (Bit 28) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Msk (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Pos (29UL) /*!< CCOCLK (Bit 29) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Msk (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos (30UL) /*!< CCOCALIB (Bit 30) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_TXREV_Pos (31UL) /*!< TXREV (Bit 31) */ + #define R_CTSU2_CTSUCALIB_TXREV_Msk (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDBGR0 ======================================================= */ +/* ======================================================= CTSUDBGR1 ======================================================= */ +/* ====================================================== CTSUSUCLKA ======================================================= */ + #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos (0UL) /*!< SUADJ0 (Bit 0) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk (0xffUL) /*!< SUADJ0 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos (8UL) /*!< SUMULTI0 (Bit 8) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk (0xff00UL) /*!< SUMULTI0 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos (16UL) /*!< SUADJ1 (Bit 16) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk (0xff0000UL) /*!< SUADJ1 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos (24UL) /*!< SUMULTI1 (Bit 24) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTSUSUCLK0 ======================================================= */ +/* ====================================================== CTSUSUCLK1 ======================================================= */ +/* ====================================================== CTSUSUCLKB ======================================================= */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos (0UL) /*!< SUADJ2 (Bit 0) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk (0xffUL) /*!< SUADJ2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos (8UL) /*!< SUMULTI2 (Bit 8) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk (0xff00UL) /*!< SUMULTI2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos (16UL) /*!< SUADJ3 (Bit 16) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk (0xff0000UL) /*!< SUADJ3 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos (24UL) /*!< SUMULTI3 (Bit 24) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTSUSUCLK2 ======================================================= */ +/* ====================================================== CTSUSUCLK3 ======================================================= */ +/* ====================================================== CTSUCFCCNT ======================================================= */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUCFCCNTL ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_CTSUTRIM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CTSUTRIMA ======================================================= */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos (24UL) /*!< SUADJTRIM (Bit 24) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos (16UL) /*!< SUADJD (Bit 16) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk (0xff0000UL) /*!< SUADJD (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos (8UL) /*!< DACTRIM (Bit 8) */ + #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk (0xff00UL) /*!< DACTRIM (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos (0UL) /*!< RTRIM (Bit 0) */ + #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk (0xffUL) /*!< RTRIM (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUTRIMB ======================================================= */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos (24UL) /*!< TRESULT3 (Bit 24) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos (16UL) /*!< TRESULT2 (Bit 16) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk (0xff0000UL) /*!< TRESULT2 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos (8UL) /*!< TRESULT1 (Bit 8) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk (0xff00UL) /*!< TRESULT1 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos (0UL) /*!< TRESULT0 (Bit 0) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk (0xffUL) /*!< TRESULT0 (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA2E1A9_H */ + +/** @} */ /* End of group R7FA2E1A9 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h new file mode 100644 index 00000000..b7a11de8 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h @@ -0,0 +1,14219 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA2E2A7.h + * @brief CMSIS HeaderFile + * @version 1.00.00 + * @date 17. June 2022 + * @note Generated by SVDConv V3.3.35 on Friday, 17.06.2022 18:23:08 + * from File 'svd-test/R7FA2E2A7.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA2E2A7 + * @{ + */ + +#ifndef R7FA2E2A7_H + #define R7FA2E2A7_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M23 Processor and Core Peripherals =========================== */ + #define __CM23_REV 0x0100U /*!< CM23 Core Revision */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 0 /*!< FPU present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm23.h" /*!< ARM Cortex-M23 processor and core peripherals */ + #include "system.h" /*!< R7FA2E2A7 System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTW0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGTW0 Structure */ +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + __IM uint8_t RESERVED; +} R_AGTW0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x40083000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED30[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGTW0_BASE 0x40084000UL + #define R_AGTW1_BASE 0x40084100UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CRC_BASE 0x40074000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_I3C0_BASE 0x40083000UL + #define R_I3C1_BASE 0x40083400UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE) + #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTW0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTW0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTW0_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTW0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTW0_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTW0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTW0_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTW0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTW0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTW0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTW0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTW0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTW0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTW0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTW0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTW0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTW0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTW0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTW0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTW0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTW0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTW0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTW0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTW0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTW0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTW0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTW0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTW0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTW0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTW0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTW0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTW0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTW0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTW0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTW0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTW0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTW0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTW0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTW0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTW0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTW0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA2E2A7_H */ + +/** @} */ /* End of group R7FA2E2A7 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h new file mode 100644 index 00000000..8fa45d40 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h @@ -0,0 +1,15596 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA2L1AB.h + * @brief CMSIS HeaderFile + * @version 0.50.00 + * @date 16. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 16.06.2022 17:21:35 + * from File 'svd-test/R7FA2L1AB.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA2L1AB + * @{ + */ + +#ifndef R7FA2L1AB_H + #define R7FA2L1AB_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M23 Processor and Core Peripherals =========================== */ + #define __CM23_REV 0x0100U /*!< CM23 Core Revision */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 0 /*!< FPU present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm23.h" /*!< ARM Cortex-M23 processor and core peripherals */ + #include "system.h" /*!< R7FA2L1AB System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU2) + */ + +typedef struct /*!< (@ 0x40082000) R_CTSU2 Structure */ +{ + union + { + union + { + __IOM uint32_t CTSUCRA; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint32_t STRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint32_t CAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint32_t SNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint32_t CFCON : 1; /*!< [3..3] CTSU CFC Power on Control */ + __OM uint32_t INIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control */ + __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection */ + __IOM uint32_t PON : 1; /*!< [8..8] CTSU Power On Control */ + __IOM uint32_t CSW : 1; /*!< [9..9] TSCAP Pin Enable */ + __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting */ + __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment */ + __IOM uint32_t CLK : 2; /*!< [13..12] CTSU Operating Clock Select */ + __IOM uint32_t MD0 : 1; /*!< [14..14] CTSU Measurement Mode Select 0 */ + __IOM uint32_t MD1 : 1; /*!< [15..15] CTSU Measurement Mode Select 1 */ + __IOM uint32_t MD2 : 1; /*!< [16..16] CTSU Measurement Mode Select 2 */ + __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment */ + __IOM uint32_t LOAD : 2; /*!< [19..18] CTSU Load Control During Measurement */ + __IOM uint32_t POSEL : 2; /*!< [21..20] CTSU Non-measured Channel Output Select */ + __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select */ + __IOM uint32_t PCSEL : 1; /*!< [23..23] CTSU Boost Circuit Clock Select */ + __IOM uint32_t STCLK : 6; /*!< [29..24] CTSU STCLK Select */ + __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select */ + __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select */ + } CTSUCRA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRAL; /*!< (@ 0x00000000) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A */ + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A */ + }; + }; + + union + { + __IOM uint16_t CTSUCRAH; /*!< (@ 0x00000002) CTSU Control Register A */ + + struct + { + __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A */ + __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCRB; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control */ + __IOM uint32_t PRMODE : 2; /*!< [5..4] Phase Control Period */ + __IOM uint32_t SOFF : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable */ + __IOM uint32_t PROFF : 1; /*!< [7..7] Drive Pulse Phase Control */ + __IOM uint32_t SST : 8; /*!< [15..8] Wait Time Sensor Stabilization */ + uint32_t : 8; + __IOM uint32_t SSMOD : 3; /*!< [26..24] Spread Spectrum Modulation Frequency */ + uint32_t : 1; + __IOM uint32_t SSCNT : 2; /*!< [29..28] Adjusting the SUCLK frequency */ + uint32_t : 2; + } CTSUCRB_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCRBL; /*!< (@ 0x00000004) CTSU Control Register B */ + + struct + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B */ + __IOM uint8_t CTSUSST; /*!< (@ 0x00000005) CTSU Control Register B */ + }; + }; + + union + { + __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B */ + + struct + { + __IM uint8_t RESERVED; + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUMCH; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0 */ + uint32_t : 2; + __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1 */ + uint32_t : 2; + __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control */ + __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control */ + uint32_t : 12; + } CTSUMCH_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUMCHL; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + + struct + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register */ + }; + }; + + union + { + __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + __IOM uint8_t CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACA; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A */ + uint32_t : 1; + __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A */ + uint32_t : 2; + __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A */ + __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A */ + } CTSUCHACA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHACAL; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHACAH; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + + struct + { + __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A */ + __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHACB; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + + struct + { + __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B */ + __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B */ + uint32_t : 28; + } CTSUCHACB_b; + }; + __IOM uint16_t CTSUCHACBL; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + __IOM uint8_t CTSUCHAC4; /*!< (@ 0x00000010) CTSU Channel Enable Control Register B */ + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCA; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint32_t CHTRC : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A */ + uint32_t : 1; + __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A */ + uint32_t : 2; + __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A */ + __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A */ + } CTSUCHTRCA_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUCHTRCAL; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + + union + { + __IOM uint16_t CTSUCHTRCAH; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + + struct + { + __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register + * A */ + __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register + * A */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUCHTRCB; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + + struct + { + __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B */ + __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B */ + uint32_t : 28; + } CTSUCHTRCB_b; + }; + __IOM uint16_t CTSUCHTRCBL; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + __IOM uint8_t CTSUCHTRC4; /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register + * B */ + }; + + union + { + union + { + __IOM uint32_t CTSUSR; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint32_t MFC : 2; /*!< [1..0] CTSU Multi-clock Counter */ + uint32_t : 3; + __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset */ + __IM uint32_t ICOMP1 : 1; /*!< [6..6] CTSU Sense Current Error Monitor */ + __IM uint32_t ICOMP0 : 1; /*!< [7..7] TSCAP Voltage Error Monitor */ + __IM uint32_t STC : 3; /*!< [10..8] CTSU Measurement Status Counter */ + uint32_t : 1; + __IM uint32_t DTSR : 1; /*!< [12..12] CTSU Data Transfer Status Flag */ + __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag */ + __IOM uint32_t SUOVF : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag */ + __IM uint32_t PS : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag */ + __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select */ + uint32_t : 10; + } CTSUSR_b; + }; + + struct + { + union + { + __IOM uint16_t CTSUSRL; /*!< (@ 0x0000001C) CTSU Status Register */ + + struct + { + __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register */ + __IOM uint8_t CTSUST; /*!< (@ 0x0000001D) CTSU Status Register */ + }; + }; + + union + { + __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register */ + __IOM uint8_t CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register */ + }; + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSO; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + + struct + { + __IOM uint32_t SO : 10; /*!< [9..0] CTSU Sensor Offset Adjustment */ + __IOM uint32_t SNUM : 8; /*!< [17..10] CTSU Measurement Count Setting */ + uint32_t : 2; + __IOM uint32_t SSDIV : 4; /*!< [23..20] Spread Spectrum Frequency */ + __IOM uint32_t SDPA : 8; /*!< [31..24] CTSU Base Clock Setting */ + } CTSUSO_b; + }; + + struct + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000020) CTSU Sensor Offset Register */ + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000022) CTSU Sensor Offset Register */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUSCNT; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + + struct + { + __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter */ + __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter */ + } CTSUSCNT_b; + }; + __IM uint16_t CTSUSC; /*!< (@ 0x00000024) CTSU Sensor Counter Register */ + }; + + union + { + union + { + __IOM uint32_t CTSUCALIB; /*!< (@ 0x00000028) CTSU Calibration Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TSOD : 1; /*!< [2..2] TS Pins Fixed Output */ + __IOM uint32_t DRV : 1; /*!< [3..3] Power Supply Calibration Select */ + __IOM uint32_t CLKSEL : 2; /*!< [5..4] Observation Clock Select */ + __IOM uint32_t SUCLKEN : 1; /*!< [6..6] SUCLK Forced Oscillation Control */ + __IOM uint32_t TSOC : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit */ + __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter */ + __IOM uint32_t IOC : 1; /*!< [9..9] TS Pin Fixed Output Value Set */ + __IOM uint32_t CFCRDMD : 1; /*!< [10..10] CFC Counter Read Mode Select */ + __IOM uint32_t DCOFF : 1; /*!< [11..11] Down Converter Control */ + uint32_t : 4; + __IOM uint32_t CFCSEL : 6; /*!< [21..16] Observation CFC Clock Select */ + __IOM uint32_t CFCMODE : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select */ + uint32_t : 1; + __IOM uint32_t DACMSEL : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select */ + __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration */ + __IOM uint32_t SUMSEL : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration + * Select */ + __IOM uint32_t SUCARRY : 1; /*!< [27..27] Current Control Oscillator Input Current Adjustment + * for SUCLK */ + __IOM uint32_t DACCLK : 1; /*!< [28..28] Modulation Clock Select for Offset Current Circuits */ + __IOM uint32_t CCOCLK : 1; /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator + * Input Current of SUCLK */ + __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator + * for Measurement */ + __IOM uint32_t TXREV : 1; /*!< [31..31] Transmit Pin Inverted Output */ + } CTSUCALIB_b; + }; + + struct + { + __IOM uint16_t CTSUDBGR0; /*!< (@ 0x00000028) CTSU Calibration Register */ + __IOM uint16_t CTSUDBGR1; /*!< (@ 0x0000002A) CTSU Calibration Register */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSUCLKA; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + + struct + { + __IOM uint32_t SUADJ0 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ1 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKA_b; + }; + + struct + { + __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A */ + __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A */ + }; + }; + + union + { + union + { + __IOM uint32_t CTSUSUCLKB; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + + struct + { + __IOM uint32_t SUADJ2 : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting */ + __IOM uint32_t SUADJ3 : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting */ + } CTSUSUCLKB_b; + }; + + struct + { + __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B */ + __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B */ + }; + }; + + union + { + union + { + __IM uint32_t CTSUCFCCNT; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + + struct + { + __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter */ + uint32_t : 16; + } CTSUCFCCNT_b; + }; + __IM uint16_t CTSUCFCCNTL; /*!< (@ 0x00000034) CTSU CFC Counter Register */ + }; +} R_CTSU2_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSUTRIM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CTSU Trimming Registers (R_CTSUTRIM) + */ + +typedef struct /*!< (@ 0x407EC000) R_CTSUTRIM Structure */ +{ + __IM uint32_t RESERVED[233]; + + union + { + __IOM uint32_t CTSUTRIMA; /*!< (@ 0x000003A4) CTSU Trimming Register A */ + + struct + { + __IOM uint32_t RTRIM : 8; /*!< [7..0] CTSU Reference Resistance Adjustment */ + __IOM uint32_t DACTRIM : 8; /*!< [15..8] Linearity Adjustment of Offset Current */ + __IOM uint32_t SUADJD : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment */ + __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (120k) */ + } CTSUTRIMA_b; + }; + + union + { + __IOM uint32_t CTSUTRIMB; /*!< (@ 0x000003A8) CTSU Trimming Register B */ + + struct + { + __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance + * (7.5k) */ + __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance + * (15k) */ + __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance + * (30k) */ + __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance + * (60k) */ + } CTSUTRIMB_b; + }; +} R_CTSUTRIM_Type; /*!< Size = 940 (0x3ac) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU2_BASE 0x40082000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_CTSUTRIM_BASE 0x407EC000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU2_Type *) R_CTSU2_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_CTSUTRIM ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCRA ======================================================== */ + #define R_CTSU2_CTSUCRA_STRT_Pos (0UL) /*!< STRT (Bit 0) */ + #define R_CTSU2_CTSUCRA_STRT_Msk (0x1UL) /*!< STRT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CAP_Pos (1UL) /*!< CAP (Bit 1) */ + #define R_CTSU2_CTSUCRA_CAP_Msk (0x2UL) /*!< CAP (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_SNZ_Pos (2UL) /*!< SNZ (Bit 2) */ + #define R_CTSU2_CTSUCRA_SNZ_Msk (0x4UL) /*!< SNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CFCON_Pos (3UL) /*!< CFCON (Bit 3) */ + #define R_CTSU2_CTSUCRA_CFCON_Msk (0x8UL) /*!< CFCON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_INIT_Pos (4UL) /*!< INIT (Bit 4) */ + #define R_CTSU2_CTSUCRA_INIT_Msk (0x10UL) /*!< INIT (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_PUMPON_Pos (5UL) /*!< PUMPON (Bit 5) */ + #define R_CTSU2_CTSUCRA_PUMPON_Msk (0x20UL) /*!< PUMPON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Pos (6UL) /*!< TXVSEL (Bit 6) */ + #define R_CTSU2_CTSUCRA_TXVSEL_Msk (0xc0UL) /*!< TXVSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_PON_Pos (8UL) /*!< PON (Bit 8) */ + #define R_CTSU2_CTSUCRA_PON_Msk (0x100UL) /*!< PON (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CSW_Pos (9UL) /*!< CSW (Bit 9) */ + #define R_CTSU2_CTSUCRA_CSW_Msk (0x200UL) /*!< CSW (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Pos (10UL) /*!< ATUNE0 (Bit 10) */ + #define R_CTSU2_CTSUCRA_ATUNE0_Msk (0x400UL) /*!< ATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Pos (11UL) /*!< ATUNE1 (Bit 11) */ + #define R_CTSU2_CTSUCRA_ATUNE1_Msk (0x800UL) /*!< ATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_CLK_Pos (12UL) /*!< CLK (Bit 12) */ + #define R_CTSU2_CTSUCRA_CLK_Msk (0x3000UL) /*!< CLK (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_MD0_Pos (14UL) /*!< MD0 (Bit 14) */ + #define R_CTSU2_CTSUCRA_MD0_Msk (0x4000UL) /*!< MD0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD1_Pos (15UL) /*!< MD1 (Bit 15) */ + #define R_CTSU2_CTSUCRA_MD1_Msk (0x8000UL) /*!< MD1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_MD2_Pos (16UL) /*!< MD2 (Bit 16) */ + #define R_CTSU2_CTSUCRA_MD2_Msk (0x10000UL) /*!< MD2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Pos (17UL) /*!< ATUNE2 (Bit 17) */ + #define R_CTSU2_CTSUCRA_ATUNE2_Msk (0x20000UL) /*!< ATUNE2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_LOAD_Pos (18UL) /*!< LOAD (Bit 18) */ + #define R_CTSU2_CTSUCRA_LOAD_Msk (0xc0000UL) /*!< LOAD (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_POSEL_Pos (20UL) /*!< POSEL (Bit 20) */ + #define R_CTSU2_CTSUCRA_POSEL_Msk (0x300000UL) /*!< POSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Pos (22UL) /*!< SDPSEL (Bit 22) */ + #define R_CTSU2_CTSUCRA_SDPSEL_Msk (0x400000UL) /*!< SDPSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_PCSEL_Pos (23UL) /*!< PCSEL (Bit 23) */ + #define R_CTSU2_CTSUCRA_PCSEL_Msk (0x800000UL) /*!< PCSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_STCLK_Pos (24UL) /*!< STCLK (Bit 24) */ + #define R_CTSU2_CTSUCRA_STCLK_Msk (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUCRA_DCMODE_Pos (30UL) /*!< DCMODE (Bit 30) */ + #define R_CTSU2_CTSUCRA_DCMODE_Msk (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRA_DCBACK_Pos (31UL) /*!< DCBACK (Bit 31) */ + #define R_CTSU2_CTSUCRA_DCBACK_Msk (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCRAL ======================================================== */ +/* ======================================================== CTSUCR0 ======================================================== */ +/* ======================================================== CTSUCR1 ======================================================== */ +/* ======================================================= CTSUCRAH ======================================================== */ +/* ======================================================== CTSUCR2 ======================================================== */ +/* ======================================================== CTSUCR3 ======================================================== */ +/* ======================================================== CTSUCRB ======================================================== */ + #define R_CTSU2_CTSUCRB_PRRATIO_Pos (0UL) /*!< PRRATIO (Bit 0) */ + #define R_CTSU2_CTSUCRB_PRRATIO_Msk (0xfUL) /*!< PRRATIO (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUCRB_PRMODE_Pos (4UL) /*!< PRMODE (Bit 4) */ + #define R_CTSU2_CTSUCRB_PRMODE_Msk (0x30UL) /*!< PRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCRB_SOFF_Pos (6UL) /*!< SOFF (Bit 6) */ + #define R_CTSU2_CTSUCRB_SOFF_Msk (0x40UL) /*!< SOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_PROFF_Pos (7UL) /*!< PROFF (Bit 7) */ + #define R_CTSU2_CTSUCRB_PROFF_Msk (0x80UL) /*!< PROFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCRB_SST_Pos (8UL) /*!< SST (Bit 8) */ + #define R_CTSU2_CTSUCRB_SST_Msk (0xff00UL) /*!< SST (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUCRB_SSMOD_Pos (24UL) /*!< SSMOD (Bit 24) */ + #define R_CTSU2_CTSUCRB_SSMOD_Msk (0x7000000UL) /*!< SSMOD (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUCRB_SSCNT_Pos (28UL) /*!< SSCNT (Bit 28) */ + #define R_CTSU2_CTSUCRB_SSCNT_Msk (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03) */ +/* ======================================================= CTSUCRBL ======================================================== */ +/* ======================================================= CTSUSDPRS ======================================================= */ +/* ======================================================== CTSUSST ======================================================== */ +/* ======================================================= CTSUCRBH ======================================================== */ +/* ======================================================= CTSUDCLKC ======================================================= */ +/* ======================================================== CTSUMCH ======================================================== */ + #define R_CTSU2_CTSUMCH_MCH0_Pos (0UL) /*!< MCH0 (Bit 0) */ + #define R_CTSU2_CTSUMCH_MCH0_Msk (0x3fUL) /*!< MCH0 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCH1_Pos (8UL) /*!< MCH1 (Bit 8) */ + #define R_CTSU2_CTSUMCH_MCH1_Msk (0x3f00UL) /*!< MCH1 (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUMCH_MCA0_Pos (16UL) /*!< MCA0 (Bit 16) */ + #define R_CTSU2_CTSUMCH_MCA0_Msk (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA1_Pos (17UL) /*!< MCA1 (Bit 17) */ + #define R_CTSU2_CTSUMCH_MCA1_Msk (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA2_Pos (18UL) /*!< MCA2 (Bit 18) */ + #define R_CTSU2_CTSUMCH_MCA2_Msk (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUMCH_MCA3_Pos (19UL) /*!< MCA3 (Bit 19) */ + #define R_CTSU2_CTSUMCH_MCA3_Msk (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUMCHL ======================================================== */ +/* ======================================================= CTSUMCH0 ======================================================== */ +/* ======================================================= CTSUMCH1 ======================================================== */ +/* ======================================================= CTSUMCHH ======================================================== */ +/* ======================================================= CTSUMFAF ======================================================== */ +/* ======================================================= CTSUCHACA ======================================================= */ + #define R_CTSU2_CTSUCHACA_CHAC00_Pos (0UL) /*!< CHAC00 (Bit 0) */ + #define R_CTSU2_CTSUCHACA_CHAC00_Msk (0x1UL) /*!< CHAC00 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Pos (2UL) /*!< CHAC02 (Bit 2) */ + #define R_CTSU2_CTSUCHACA_CHAC02_Msk (0x4UL) /*!< CHAC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Pos (4UL) /*!< CHAC04 (Bit 4) */ + #define R_CTSU2_CTSUCHACA_CHAC04_Msk (0x10UL) /*!< CHAC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Pos (5UL) /*!< CHAC05 (Bit 5) */ + #define R_CTSU2_CTSUCHACA_CHAC05_Msk (0x20UL) /*!< CHAC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Pos (6UL) /*!< CHAC06 (Bit 6) */ + #define R_CTSU2_CTSUCHACA_CHAC06_Msk (0x40UL) /*!< CHAC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Pos (7UL) /*!< CHAC07 (Bit 7) */ + #define R_CTSU2_CTSUCHACA_CHAC07_Msk (0x80UL) /*!< CHAC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Pos (8UL) /*!< CHAC08 (Bit 8) */ + #define R_CTSU2_CTSUCHACA_CHAC08_Msk (0x100UL) /*!< CHAC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Pos (9UL) /*!< CHAC09 (Bit 9) */ + #define R_CTSU2_CTSUCHACA_CHAC09_Msk (0x200UL) /*!< CHAC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Pos (10UL) /*!< CHAC10 (Bit 10) */ + #define R_CTSU2_CTSUCHACA_CHAC10_Msk (0x400UL) /*!< CHAC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Pos (11UL) /*!< CHAC11 (Bit 11) */ + #define R_CTSU2_CTSUCHACA_CHAC11_Msk (0x800UL) /*!< CHAC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Pos (12UL) /*!< CHAC12 (Bit 12) */ + #define R_CTSU2_CTSUCHACA_CHAC12_Msk (0x1000UL) /*!< CHAC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Pos (13UL) /*!< CHAC13 (Bit 13) */ + #define R_CTSU2_CTSUCHACA_CHAC13_Msk (0x2000UL) /*!< CHAC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Pos (14UL) /*!< CHAC14 (Bit 14) */ + #define R_CTSU2_CTSUCHACA_CHAC14_Msk (0x4000UL) /*!< CHAC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Pos (15UL) /*!< CHAC15 (Bit 15) */ + #define R_CTSU2_CTSUCHACA_CHAC15_Msk (0x8000UL) /*!< CHAC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Pos (16UL) /*!< CHAC16 (Bit 16) */ + #define R_CTSU2_CTSUCHACA_CHAC16_Msk (0x10000UL) /*!< CHAC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Pos (17UL) /*!< CHAC17 (Bit 17) */ + #define R_CTSU2_CTSUCHACA_CHAC17_Msk (0x20000UL) /*!< CHAC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Pos (18UL) /*!< CHAC18 (Bit 18) */ + #define R_CTSU2_CTSUCHACA_CHAC18_Msk (0x40000UL) /*!< CHAC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Pos (21UL) /*!< CHAC21 (Bit 21) */ + #define R_CTSU2_CTSUCHACA_CHAC21_Msk (0x200000UL) /*!< CHAC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Pos (22UL) /*!< CHAC22 (Bit 22) */ + #define R_CTSU2_CTSUCHACA_CHAC22_Msk (0x400000UL) /*!< CHAC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Pos (23UL) /*!< CHAC23 (Bit 23) */ + #define R_CTSU2_CTSUCHACA_CHAC23_Msk (0x800000UL) /*!< CHAC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Pos (24UL) /*!< CHAC24 (Bit 24) */ + #define R_CTSU2_CTSUCHACA_CHAC24_Msk (0x1000000UL) /*!< CHAC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Pos (25UL) /*!< CHAC25 (Bit 25) */ + #define R_CTSU2_CTSUCHACA_CHAC25_Msk (0x2000000UL) /*!< CHAC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Pos (26UL) /*!< CHAC26 (Bit 26) */ + #define R_CTSU2_CTSUCHACA_CHAC26_Msk (0x4000000UL) /*!< CHAC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Pos (27UL) /*!< CHAC27 (Bit 27) */ + #define R_CTSU2_CTSUCHACA_CHAC27_Msk (0x8000000UL) /*!< CHAC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Pos (28UL) /*!< CHAC28 (Bit 28) */ + #define R_CTSU2_CTSUCHACA_CHAC28_Msk (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Pos (29UL) /*!< CHAC29 (Bit 29) */ + #define R_CTSU2_CTSUCHACA_CHAC29_Msk (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Pos (30UL) /*!< CHAC30 (Bit 30) */ + #define R_CTSU2_CTSUCHACA_CHAC30_Msk (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Pos (31UL) /*!< CHAC31 (Bit 31) */ + #define R_CTSU2_CTSUCHACA_CHAC31_Msk (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACAL ======================================================= */ +/* ======================================================= CTSUCHAC0 ======================================================= */ +/* ======================================================= CTSUCHAC1 ======================================================= */ +/* ====================================================== CTSUCHACAH ======================================================= */ +/* ======================================================= CTSUCHAC2 ======================================================= */ +/* ======================================================= CTSUCHAC3 ======================================================= */ +/* ======================================================= CTSUCHACB ======================================================= */ + #define R_CTSU2_CTSUCHACB_CHAC32_Pos (0UL) /*!< CHAC32 (Bit 0) */ + #define R_CTSU2_CTSUCHACB_CHAC32_Msk (0x1UL) /*!< CHAC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Pos (1UL) /*!< CHAC33 (Bit 1) */ + #define R_CTSU2_CTSUCHACB_CHAC33_Msk (0x2UL) /*!< CHAC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Pos (2UL) /*!< CHAC34 (Bit 2) */ + #define R_CTSU2_CTSUCHACB_CHAC34_Msk (0x4UL) /*!< CHAC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Pos (3UL) /*!< CHAC35 (Bit 3) */ + #define R_CTSU2_CTSUCHACB_CHAC35_Msk (0x8UL) /*!< CHAC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHACBL ======================================================= */ +/* ======================================================= CTSUCHAC4 ======================================================= */ +/* ====================================================== CTSUCHTRCA ======================================================= */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos (0UL) /*!< CHTRC (Bit 0) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk (0x1UL) /*!< CHTRC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos (2UL) /*!< CHTRC02 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk (0x4UL) /*!< CHTRC02 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos (4UL) /*!< CHTRC04 (Bit 4) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk (0x10UL) /*!< CHTRC04 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos (5UL) /*!< CHTRC05 (Bit 5) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk (0x20UL) /*!< CHTRC05 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos (6UL) /*!< CHTRC06 (Bit 6) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk (0x40UL) /*!< CHTRC06 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos (7UL) /*!< CHTRC07 (Bit 7) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk (0x80UL) /*!< CHTRC07 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos (8UL) /*!< CHTRC08 (Bit 8) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk (0x100UL) /*!< CHTRC08 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos (9UL) /*!< CHTRC09 (Bit 9) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk (0x200UL) /*!< CHTRC09 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos (10UL) /*!< CHTRC10 (Bit 10) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk (0x400UL) /*!< CHTRC10 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos (11UL) /*!< CHTRC11 (Bit 11) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk (0x800UL) /*!< CHTRC11 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos (12UL) /*!< CHTRC12 (Bit 12) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk (0x1000UL) /*!< CHTRC12 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos (13UL) /*!< CHTRC13 (Bit 13) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk (0x2000UL) /*!< CHTRC13 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos (14UL) /*!< CHTRC14 (Bit 14) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk (0x4000UL) /*!< CHTRC14 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos (15UL) /*!< CHTRC15 (Bit 15) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk (0x8000UL) /*!< CHTRC15 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos (16UL) /*!< CHTRC16 (Bit 16) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk (0x10000UL) /*!< CHTRC16 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos (17UL) /*!< CHTRC17 (Bit 17) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk (0x20000UL) /*!< CHTRC17 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos (18UL) /*!< CHTRC18 (Bit 18) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk (0x40000UL) /*!< CHTRC18 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos (21UL) /*!< CHTRC21 (Bit 21) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk (0x200000UL) /*!< CHTRC21 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos (22UL) /*!< CHTRC22 (Bit 22) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk (0x400000UL) /*!< CHTRC22 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos (23UL) /*!< CHTRC23 (Bit 23) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk (0x800000UL) /*!< CHTRC23 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos (24UL) /*!< CHTRC24 (Bit 24) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk (0x1000000UL) /*!< CHTRC24 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos (25UL) /*!< CHTRC25 (Bit 25) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk (0x2000000UL) /*!< CHTRC25 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos (26UL) /*!< CHTRC26 (Bit 26) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk (0x4000000UL) /*!< CHTRC26 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos (27UL) /*!< CHTRC27 (Bit 27) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk (0x8000000UL) /*!< CHTRC27 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos (28UL) /*!< CHTRC28 (Bit 28) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos (29UL) /*!< CHTRC29 (Bit 29) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos (30UL) /*!< CHTRC30 (Bit 30) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos (31UL) /*!< CHTRC31 (Bit 31) */ + #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCAL ====================================================== */ +/* ====================================================== CTSUCHTRC0 ======================================================= */ +/* ====================================================== CTSUCHTRC1 ======================================================= */ +/* ====================================================== CTSUCHTRCAH ====================================================== */ +/* ====================================================== CTSUCHTRC2 ======================================================= */ +/* ====================================================== CTSUCHTRC3 ======================================================= */ +/* ====================================================== CTSUCHTRCB ======================================================= */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos (0UL) /*!< CHTRC32 (Bit 0) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk (0x1UL) /*!< CHTRC32 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos (1UL) /*!< CHTRC33 (Bit 1) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk (0x2UL) /*!< CHTRC33 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos (2UL) /*!< CHTRC34 (Bit 2) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk (0x4UL) /*!< CHTRC34 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos (3UL) /*!< CHTRC35 (Bit 3) */ + #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk (0x8UL) /*!< CHTRC35 (Bitfield-Mask: 0x01) */ +/* ====================================================== CTSUCHTRCBL ====================================================== */ +/* ====================================================== CTSUCHTRC4 ======================================================= */ +/* ======================================================== CTSUSR ========================================================= */ + #define R_CTSU2_CTSUSR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_CTSU2_CTSUSR_MFC_Msk (0x3UL) /*!< MFC (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Pos (5UL) /*!< ICOMPRST (Bit 5) */ + #define R_CTSU2_CTSUSR_ICOMPRST_Msk (0x20UL) /*!< ICOMPRST (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP1_Pos (6UL) /*!< ICOMP1 (Bit 6) */ + #define R_CTSU2_CTSUSR_ICOMP1_Msk (0x40UL) /*!< ICOMP1 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_ICOMP0_Pos (7UL) /*!< ICOMP0 (Bit 7) */ + #define R_CTSU2_CTSUSR_ICOMP0_Msk (0x80UL) /*!< ICOMP0 (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_STC_Pos (8UL) /*!< STC (Bit 8) */ + #define R_CTSU2_CTSUSR_STC_Msk (0x700UL) /*!< STC (Bitfield-Mask: 0x07) */ + #define R_CTSU2_CTSUSR_DTSR_Pos (12UL) /*!< DTSR (Bit 12) */ + #define R_CTSU2_CTSUSR_DTSR_Msk (0x1000UL) /*!< DTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_SENSOVF_Pos (13UL) /*!< SENSOVF (Bit 13) */ + #define R_CTSU2_CTSUSR_SENSOVF_Msk (0x2000UL) /*!< SENSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_SUOVF_Pos (14UL) /*!< SUOVF (Bit 14) */ + #define R_CTSU2_CTSUSR_SUOVF_Msk (0x4000UL) /*!< SUOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_CTSU2_CTSUSR_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Pos (16UL) /*!< CFCRDCH (Bit 16) */ + #define R_CTSU2_CTSUSR_CFCRDCH_Msk (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f) */ +/* ======================================================== CTSUSRL ======================================================== */ +/* ======================================================== CTSUSR0 ======================================================== */ +/* ======================================================== CTSUST ========================================================= */ +/* ======================================================== CTSUSRH ======================================================== */ +/* ======================================================== CTSUSR2 ======================================================== */ +/* ======================================================== CTSUSO ========================================================= */ + #define R_CTSU2_CTSUSO_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_CTSU2_CTSUSO_SO_Msk (0x3ffUL) /*!< SO (Bitfield-Mask: 0x3ff) */ + #define R_CTSU2_CTSUSO_SNUM_Pos (10UL) /*!< SNUM (Bit 10) */ + #define R_CTSU2_CTSUSO_SNUM_Msk (0x3fc00UL) /*!< SNUM (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSO_SSDIV_Pos (20UL) /*!< SSDIV (Bit 20) */ + #define R_CTSU2_CTSUSO_SSDIV_Msk (0xf00000UL) /*!< SSDIV (Bitfield-Mask: 0x0f) */ + #define R_CTSU2_CTSUSO_SDPA_Pos (24UL) /*!< SDPA (Bit 24) */ + #define R_CTSU2_CTSUSO_SDPA_Msk (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSO0 ======================================================== */ +/* ======================================================== CTSUSO1 ======================================================== */ +/* ======================================================= CTSUSCNT ======================================================== */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Pos (0UL) /*!< SENSCNT (Bit 0) */ + #define R_CTSU2_CTSUSCNT_SENSCNT_Msk (0xffffUL) /*!< SENSCNT (Bitfield-Mask: 0xffff) */ + #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos (16UL) /*!< SUCKCNT (Bit 16) */ + #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSUSC ========================================================= */ +/* ======================================================= CTSUCALIB ======================================================= */ + #define R_CTSU2_CTSUCALIB_TSOD_Pos (2UL) /*!< TSOD (Bit 2) */ + #define R_CTSU2_CTSUCALIB_TSOD_Msk (0x4UL) /*!< TSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DRV_Pos (3UL) /*!< DRV (Bit 3) */ + #define R_CTSU2_CTSUCALIB_DRV_Msk (0x8UL) /*!< DRV (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_CTSU2_CTSUCALIB_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos (6UL) /*!< SUCLKEN (Bit 6) */ + #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk (0x40UL) /*!< SUCLKEN (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_TSOC_Pos (7UL) /*!< TSOC (Bit 7) */ + #define R_CTSU2_CTSUCALIB_TSOC_Msk (0x80UL) /*!< TSOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos (8UL) /*!< CNTRDSEL (Bit 8) */ + #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk (0x100UL) /*!< CNTRDSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_IOC_Pos (9UL) /*!< IOC (Bit 9) */ + #define R_CTSU2_CTSUCALIB_IOC_Msk (0x200UL) /*!< IOC (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos (10UL) /*!< CFCRDMD (Bit 10) */ + #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk (0x400UL) /*!< CFCRDMD (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Pos (11UL) /*!< DCOFF (Bit 11) */ + #define R_CTSU2_CTSUCALIB_DCOFF_Msk (0x800UL) /*!< DCOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CFCSEL_Pos (16UL) /*!< CFCSEL (Bit 16) */ + #define R_CTSU2_CTSUCALIB_CFCSEL_Msk (0x3f0000UL) /*!< CFCSEL (Bitfield-Mask: 0x3f) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Pos (22UL) /*!< CFCMODE (Bit 22) */ + #define R_CTSU2_CTSUCALIB_CFCMODE_Msk (0x400000UL) /*!< CFCMODE (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACMSEL_Pos (24UL) /*!< DACMSEL (Bit 24) */ + #define R_CTSU2_CTSUCALIB_DACMSEL_Msk (0x1000000UL) /*!< DACMSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Pos (25UL) /*!< DACCARRY (Bit 25) */ + #define R_CTSU2_CTSUCALIB_DACCARRY_Msk (0x2000000UL) /*!< DACCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUMSEL_Pos (26UL) /*!< SUMSEL (Bit 26) */ + #define R_CTSU2_CTSUCALIB_SUMSEL_Msk (0x4000000UL) /*!< SUMSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Pos (27UL) /*!< SUCARRY (Bit 27) */ + #define R_CTSU2_CTSUCALIB_SUCARRY_Msk (0x8000000UL) /*!< SUCARRY (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Pos (28UL) /*!< DACCLK (Bit 28) */ + #define R_CTSU2_CTSUCALIB_DACCLK_Msk (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Pos (29UL) /*!< CCOCLK (Bit 29) */ + #define R_CTSU2_CTSUCALIB_CCOCLK_Msk (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos (30UL) /*!< CCOCALIB (Bit 30) */ + #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01) */ + #define R_CTSU2_CTSUCALIB_TXREV_Pos (31UL) /*!< TXREV (Bit 31) */ + #define R_CTSU2_CTSUCALIB_TXREV_Msk (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDBGR0 ======================================================= */ +/* ======================================================= CTSUDBGR1 ======================================================= */ +/* ====================================================== CTSUSUCLKA ======================================================= */ + #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos (0UL) /*!< SUADJ0 (Bit 0) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk (0xffUL) /*!< SUADJ0 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos (8UL) /*!< SUMULTI0 (Bit 8) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk (0xff00UL) /*!< SUMULTI0 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos (16UL) /*!< SUADJ1 (Bit 16) */ + #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk (0xff0000UL) /*!< SUADJ1 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos (24UL) /*!< SUMULTI1 (Bit 24) */ + #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTSUSUCLK0 ======================================================= */ +/* ====================================================== CTSUSUCLK1 ======================================================= */ +/* ====================================================== CTSUSUCLKB ======================================================= */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos (0UL) /*!< SUADJ2 (Bit 0) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk (0xffUL) /*!< SUADJ2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos (8UL) /*!< SUMULTI2 (Bit 8) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk (0xff00UL) /*!< SUMULTI2 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos (16UL) /*!< SUADJ3 (Bit 16) */ + #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk (0xff0000UL) /*!< SUADJ3 (Bitfield-Mask: 0xff) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos (24UL) /*!< SUMULTI3 (Bit 24) */ + #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff) */ +/* ====================================================== CTSUSUCLK2 ======================================================= */ +/* ====================================================== CTSUSUCLK3 ======================================================= */ +/* ====================================================== CTSUCFCCNT ======================================================= */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos (0UL) /*!< CFCCNT (Bit 0) */ + #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk (0xffffUL) /*!< CFCCNT (Bitfield-Mask: 0xffff) */ +/* ====================================================== CTSUCFCCNTL ====================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_CTSUTRIM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= CTSUTRIMA ======================================================= */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos (24UL) /*!< SUADJTRIM (Bit 24) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos (16UL) /*!< SUADJD (Bit 16) */ + #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk (0xff0000UL) /*!< SUADJD (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos (8UL) /*!< DACTRIM (Bit 8) */ + #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk (0xff00UL) /*!< DACTRIM (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos (0UL) /*!< RTRIM (Bit 0) */ + #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk (0xffUL) /*!< RTRIM (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUTRIMB ======================================================= */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos (24UL) /*!< TRESULT3 (Bit 24) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos (16UL) /*!< TRESULT2 (Bit 16) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk (0xff0000UL) /*!< TRESULT2 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos (8UL) /*!< TRESULT1 (Bit 8) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk (0xff00UL) /*!< TRESULT1 (Bitfield-Mask: 0xff) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos (0UL) /*!< TRESULT0 (Bit 0) */ + #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk (0xffUL) /*!< TRESULT0 (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA2L1AB_H */ + +/** @} */ /* End of group R7FA2L1AB */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h new file mode 100644 index 00000000..89f76d58 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -0,0 +1,17430 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA4E10D.h + * @brief CMSIS HeaderFile + * @version 1.10.00 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:53 + * from File 'svd-test/R7FA4E10D.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA4E10D + * @{ + */ + +#ifndef R7FA4E10D_H + #define R7FA4E10D_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA4E10D System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CPSCU_BASE 0x40008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4E10D_H */ + +/** @} */ /* End of group R7FA4E10D */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h new file mode 100644 index 00000000..c3d059bc --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h @@ -0,0 +1,17830 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA4M1AB.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:54 + * from File 'svd-test/R7FA4M1AB.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA4M1AB + * @{ + */ + +#ifndef R7FA4M1AB_H + #define R7FA4M1AB_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA4M1AB System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) + */ +typedef struct +{ + __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ + __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ + __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ +} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ + +/** + * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ + + struct + { + __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ + uint8_t : 3; + } P_b; + }; + + union + { + __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ + + struct + { + __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ + uint8_t : 3; + } N_b; + }; +} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 8-Bit D/A Converter (R_DAC8) + */ + +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ +{ + union + { + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + + struct + { + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + + struct + { + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + + struct + { + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; + }; + + union + { + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; + }; +} R_DAC8_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Operational Amplifier (R_OPAMP) + */ + +typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */ +{ + __IM uint8_t RESERVED[8]; + + union + { + __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ + + struct + { + __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ + uint8_t : 4; + __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ + } AMPMC_b; + }; + + union + { + __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + + struct + { + __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger + * control */ + } AMPTRM_b; + }; + + union + { + __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select + * Register */ + + struct + { + __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the + * AMPTRS register after setting the AMPTRM register. */ + uint8_t : 6; + } AMPTRS_b; + }; + + union + { + __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ + + struct + { + __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ + __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ + __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ + __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ + uint8_t : 3; + __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference + * current circuit */ + } AMPC_b; + }; + + union + { + __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + + struct + { + __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ + __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ + __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ + __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ + uint8_t : 4; + } AMPMON_b; + }; + __IM uint8_t RESERVED1; + __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier + * [0..3] */ + + union + { + __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control + * register */ + + struct + { + __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ + __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ + __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ + uint8_t : 5; + } AMPCPC_b; + }; + __IM uint8_t RESERVED2[4]; + + union + { + __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable + * Register */ + + struct + { + __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ + __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ + __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ + uint8_t : 5; + } AMPUOTE_b; + }; + __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ +} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Segment LCD Controller/Driver (R_SLCDC) + */ + +typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */ +{ + union + { + __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */ + + struct + { + __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */ + __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */ + __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */ + __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */ + } LCDM0_b; + }; + + union + { + __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */ + + struct + { + __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */ + uint8_t : 2; + __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */ + __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */ + __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation + * enable/disable */ + __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */ + __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */ + } LCDM1_b; + }; + + union + { + __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */ + + struct + { + __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */ + uint8_t : 2; + } LCDC0_b; + }; + + union + { + __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */ + + struct + { + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 3; + } VLCD_b; + }; + __IM uint8_t RESERVED[252]; + + union + { + __IOM uint8_t SEG[64]; /*!< (@ 0x00000100) LCD Display Data Array */ + + struct + { + __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */ + __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */ + } SEG_b[64]; + }; +} R_SLCDC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DAC8_BASE 0x4009E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_OPAMP_BASE 0x40086000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SLCDC_BASE 0x40082000UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ AMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OS =========================================================== */ +/* ========================================================== PS =========================================================== */ +/* ========================================================== MS =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ AMPOT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_OPAMP_AMPOT_P_TRMP_Pos (0UL) /*!< TRMP (Bit 0) */ + #define R_OPAMP_AMPOT_P_TRMP_Msk (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f) */ +/* =========================================================== N =========================================================== */ + #define R_OPAMP_AMPOT_N_TRMN_Pos (0UL) /*!< TRMN (Bit 0) */ + #define R_OPAMP_AMPOT_N_TRMN_Msk (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DAM ========================================================== */ + #define R_DAC8_DAM_DACE1_Pos (5UL) /*!< DACE1 (Bit 5) */ + #define R_DAC8_DAM_DACE1_Msk (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DACE0_Pos (4UL) /*!< DACE0 (Bit 4) */ + #define R_DAC8_DAM_DACE0_Msk (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD1_Pos (1UL) /*!< DAMD1 (Bit 1) */ + #define R_DAC8_DAM_DAMD1_Msk (0x2UL) /*!< DAMD1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD0_Pos (0UL) /*!< DAMD0 (Bit 0) */ + #define R_DAC8_DAM_DAMD0_Msk (0x1UL) /*!< DAMD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= DACS ========================================================== */ + #define R_DAC8_DACS_DACS_Pos (0UL) /*!< DACS (Bit 0) */ + #define R_DAC8_DACS_DACS_Msk (0xffUL) /*!< DACS (Bitfield-Mask: 0xff) */ +/* ======================================================= DACADSCR ======================================================== */ + #define R_DAC8_DACADSCR_DACADST_Pos (0UL) /*!< DACADST (Bit 0) */ + #define R_DAC8_DACADSCR_DACADST_Msk (0x1UL) /*!< DACADST (Bitfield-Mask: 0x01) */ +/* ========================================================= DACPC ========================================================= */ + #define R_DAC8_DACPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC8_DACPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AMPMC ========================================================= */ + #define R_OPAMP_AMPMC_AMPSP_Pos (7UL) /*!< AMPSP (Bit 7) */ + #define R_OPAMP_AMPMC_AMPSP_Msk (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPMC_AMPPC_Pos (0UL) /*!< AMPPC (Bit 0) */ + #define R_OPAMP_AMPMC_AMPPC_Msk (0x1UL) /*!< AMPPC (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPTRM ========================================================= */ + #define R_OPAMP_AMPTRM_AMPTRM_Pos (0UL) /*!< AMPTRM (Bit 0) */ + #define R_OPAMP_AMPTRM_AMPTRM_Msk (0x3UL) /*!< AMPTRM (Bitfield-Mask: 0x03) */ +/* ======================================================== AMPTRS ========================================================= */ + #define R_OPAMP_AMPTRS_AMPTRS_Pos (0UL) /*!< AMPTRS (Bit 0) */ + #define R_OPAMP_AMPTRS_AMPTRS_Msk (0x3UL) /*!< AMPTRS (Bitfield-Mask: 0x03) */ +/* ========================================================= AMPC ========================================================== */ + #define R_OPAMP_AMPC_IREFE_Pos (7UL) /*!< IREFE (Bit 7) */ + #define R_OPAMP_AMPC_IREFE_Msk (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPC_AMPE_Pos (0UL) /*!< AMPE (Bit 0) */ + #define R_OPAMP_AMPC_AMPE_Msk (0x1UL) /*!< AMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPMON ========================================================= */ + #define R_OPAMP_AMPMON_AMPMON_Pos (0UL) /*!< AMPMON (Bit 0) */ + #define R_OPAMP_AMPMON_AMPMON_Msk (0x1UL) /*!< AMPMON (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPCPC ========================================================= */ + #define R_OPAMP_AMPCPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_OPAMP_AMPCPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPUOTE ======================================================== */ + #define R_OPAMP_AMPUOTE_AMPTE_Pos (0UL) /*!< AMPTE (Bit 0) */ + #define R_OPAMP_AMPUOTE_AMPTE_Msk (0x1UL) /*!< AMPTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LCDM0 ========================================================= */ + #define R_SLCDC_LCDM0_MDSET_Pos (6UL) /*!< MDSET (Bit 6) */ + #define R_SLCDC_LCDM0_MDSET_Msk (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03) */ + #define R_SLCDC_LCDM0_LWAVE_Pos (5UL) /*!< LWAVE (Bit 5) */ + #define R_SLCDC_LCDM0_LWAVE_Msk (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM0_LDTY_Pos (2UL) /*!< LDTY (Bit 2) */ + #define R_SLCDC_LCDM0_LDTY_Msk (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07) */ + #define R_SLCDC_LCDM0_LBAS_Pos (0UL) /*!< LBAS (Bit 0) */ + #define R_SLCDC_LCDM0_LBAS_Msk (0x3UL) /*!< LBAS (Bitfield-Mask: 0x03) */ +/* ========================================================= LCDM1 ========================================================= */ + #define R_SLCDC_LCDM1_LCDON_Pos (7UL) /*!< LCDON (Bit 7) */ + #define R_SLCDC_LCDM1_LCDON_Msk (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_SCOC_Pos (6UL) /*!< SCOC (Bit 6) */ + #define R_SLCDC_LCDM1_SCOC_Msk (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_VLCON_Pos (5UL) /*!< VLCON (Bit 5) */ + #define R_SLCDC_LCDM1_VLCON_Msk (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_BLON_Pos (4UL) /*!< BLON (Bit 4) */ + #define R_SLCDC_LCDM1_BLON_Msk (0x10UL) /*!< BLON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDSEL_Pos (3UL) /*!< LCDSEL (Bit 3) */ + #define R_SLCDC_LCDM1_LCDSEL_Msk (0x8UL) /*!< LCDSEL (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDVLM_Pos (0UL) /*!< LCDVLM (Bit 0) */ + #define R_SLCDC_LCDM1_LCDVLM_Msk (0x1UL) /*!< LCDVLM (Bitfield-Mask: 0x01) */ +/* ========================================================= LCDC0 ========================================================= */ + #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */ + #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */ +/* ========================================================= VLCD ========================================================== */ + #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */ + #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */ +/* ========================================================== SEG ========================================================== */ + #define R_SLCDC_SEG_A_Pos (0UL) /*!< A (Bit 0) */ + #define R_SLCDC_SEG_A_Msk (0xfUL) /*!< A (Bitfield-Mask: 0x0f) */ + #define R_SLCDC_SEG_B_Pos (4UL) /*!< B (Bit 4) */ + #define R_SLCDC_SEG_B_Msk (0xf0UL) /*!< B (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4M1AB_H */ + +/** @} */ /* End of group R7FA4M1AB */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h new file mode 100644 index 00000000..461f5a7d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h @@ -0,0 +1,18948 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA4M2AD.h + * @brief CMSIS HeaderFile + * @version 1.10.03 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:56 + * from File 'svd-test/R7FA4M2AD.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA4M2AD + * @{ + */ + +#ifndef R7FA4M2AD_H + #define R7FA4M2AD_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA4M2AD System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x400F3228) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_CTSU_BASE 0x400D0000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x400F3228UL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CPSCU_BASE 0x40008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4M2AD_H */ + +/** @} */ /* End of group R7FA4M2AD */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h new file mode 100644 index 00000000..906511c2 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -0,0 +1,19084 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA4M3AF.h + * @brief CMSIS HeaderFile + * @version 1.30.00 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:58 + * from File 'svd-test/R7FA4M3AF.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA4M3AF + * @{ + */ + +#ifndef R7FA4M3AF_H + #define R7FA4M3AF_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA4M3AF System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_CTSU_BASE 0x400D0000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4M3AF_H */ + +/** @} */ /* End of group R7FA4M3AF */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h new file mode 100644 index 00000000..6c7ed53d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h @@ -0,0 +1,17562 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA4W1AD.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:59 + * from File 'svd-test/R7FA4W1AD.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA4W1AD + * @{ + */ + +#ifndef R7FA4W1AD_H + #define R7FA4W1AD_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA4W1AD System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3]) + */ +typedef struct +{ + __IOM uint8_t OS; /*!< (@ 0x00000000) Output Select Register */ + __IOM uint8_t MS; /*!< (@ 0x00000001) Minus Input Select Register */ + __IOM uint8_t PS; /*!< (@ 0x00000002) Plus Input Select Register */ +} R_OPAMP_AMP_Type; /*!< Size = 3 (0x3) */ + +/** + * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register */ + + struct + { + __IOM uint8_t TRMP : 5; /*!< [4..0] AMPn input offset trimming Pch side */ + uint8_t : 3; + } P_b; + }; + + union + { + __IOM uint8_t N; /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register */ + + struct + { + __IOM uint8_t TRMN : 5; /*!< [4..0] AMPn input offset trimming Nch side */ + uint8_t : 3; + } N_b; + }; +} R_OPAMP_AMPOT_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Low-Power Analog Comparator (R_ACMPLP) + */ + +typedef struct /*!< (@ 0x40085E00) R_ACMPLP Structure */ +{ + union + { + __IOM uint8_t COMPMDR; /*!< (@ 0x00000000) ACMPLP Mode Setting Register */ + + struct + { + __IOM uint8_t C0ENB : 1; /*!< [0..0] ACMPLP0 Operation Enable */ + __IOM uint8_t C0WDE : 1; /*!< [1..1] ACMPLP0 Window Function Mode Enable */ + __IOM uint8_t C0VRF : 1; /*!< [2..2] ACMPLP0 Reference Voltage Selection */ + __IM uint8_t C0MON : 1; /*!< [3..3] ACMPLP0 Monitor Flag */ + __IOM uint8_t C1ENB : 1; /*!< [4..4] ACMPLP1 Operation Enable */ + __IOM uint8_t C1WDE : 1; /*!< [5..5] ACMPLP1 Window Function Mode Enable */ + __IOM uint8_t C1VRF : 1; /*!< [6..6] ACMPLP1 Reference Voltage Selection */ + __IM uint8_t C1MON : 1; /*!< [7..7] ACMPLP1 Monitor Flag */ + } COMPMDR_b; + }; + + union + { + __IOM uint8_t COMPFIR; /*!< (@ 0x00000001) ACMPLP Filter Control Register */ + + struct + { + __IOM uint8_t C0FCK : 2; /*!< [1..0] ACMPLP0 Filter Select */ + __IOM uint8_t C0EPO : 1; /*!< [2..2] ACMPLP0 Edge Polarity Switching */ + __IOM uint8_t C0EDG : 1; /*!< [3..3] ACMPLP0 Edge Detection Selection */ + __IOM uint8_t C1FCK : 2; /*!< [5..4] ACMPLP1 Filter Select */ + __IOM uint8_t C1EPO : 1; /*!< [6..6] ACMPLP1 Edge Polarity Switching */ + __IOM uint8_t C1EDG : 1; /*!< [7..7] ACMPLP1 Edge Detection Selection */ + } COMPFIR_b; + }; + + union + { + __IOM uint8_t COMPOCR; /*!< (@ 0x00000002) ACMPLP Output Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t C0OE : 1; /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable */ + __IOM uint8_t C0OP : 1; /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection */ + uint8_t : 2; + __IOM uint8_t C1OE : 1; /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable */ + __IOM uint8_t C1OP : 1; /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection */ + __IOM uint8_t SPDMD : 1; /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection */ + } COMPOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t COMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t IVCMP0 : 3; /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection */ + uint8_t : 1; + __IOM uint8_t IVCMP1 : 3; /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection */ + uint8_t : 1; + } COMPSEL0_b; + }; + + union + { + __IOM uint8_t COMPSEL1; /*!< (@ 0x00000005) Comparator Reference voltage Select Register */ + + struct + { + __IOM uint8_t IVREF0 : 3; /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection */ + uint8_t : 1; + __IOM uint8_t IVREF1 : 3; /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection */ + __IOM uint8_t C1VRF2 : 1; /*!< [7..7] ACMPLP1 Reference Voltage Selection */ + } COMPSEL1_b; + }; +} R_ACMPLP_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 8-Bit D/A Converter (R_DAC8) + */ + +typedef struct /*!< (@ 0x4009E000) R_DAC8 Structure */ +{ + union + { + __IOM uint8_t DACS[2]; /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1] */ + + struct + { + __IOM uint8_t DACS : 8; /*!< [7..0] DACS D/A conversion store data */ + } DACS_b[2]; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DAM; /*!< (@ 0x00000003) D/A Converter Mode Register */ + + struct + { + __IOM uint8_t DAMD0 : 1; /*!< [0..0] D/A operation mode select 0 */ + __IOM uint8_t DAMD1 : 1; /*!< [1..1] D/A operation mode select 1 */ + uint8_t : 2; + __IOM uint8_t DACE0 : 1; /*!< [4..4] D/A operation enable 0 */ + __IOM uint8_t DACE1 : 1; /*!< [5..5] D/A operation enable 1 */ + uint8_t : 2; + } DAM_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t DACADSCR; /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register */ + + struct + { + __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion */ + uint8_t : 7; + } DACADSCR_b; + }; + + union + { + __IOM uint8_t DACPC; /*!< (@ 0x00000007) D/A SW Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge pump enable */ + uint8_t : 7; + } DACPC_b; + }; +} R_DAC8_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_LP) + */ + +typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure */ +{ + __IM uint32_t RESERVED[36]; + __IOM uint8_t DFLCTL; /*!< (@ 0x00000090) Flash P/E Mode Control Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[27]; + + union + { + __IOM uint8_t FPMCR; /*!< (@ 0x00000100) Flash P/E Mode Control Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t FMS0 : 1; /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode + * 011: Discharge mode 1 111: Discharge mode 2 101: Code Flash + * P/E mode 010: Data flash P/E mode Others: Setting prohibited. */ + uint8_t : 1; + __IOM uint8_t RPDIS : 1; /*!< [3..3] Code Flash P/E Disable */ + __IOM uint8_t FMS1 : 1; /*!< [4..4] The bit to make data flash a programming modeRefer to + * the description of the FMS0 bit. */ + uint8_t : 1; + __IOM uint8_t VLPE : 1; /*!< [6..6] Low-Voltage P/E Mode Enable */ + __IOM uint8_t FMS2 : 1; /*!< [7..7] Flash Operating Mode Select 2.Refer to the description + * of the FMS0 bit. */ + } FPMCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IOM uint8_t FASR; /*!< (@ 0x00000104) Flash Area Select Register */ + + struct + { + __IOM uint8_t EXS : 1; /*!< [0..0] Extra area select */ + uint8_t : 7; + } FASR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t FSARL; /*!< (@ 0x00000108) Flash Processing Start Address Register L */ + + struct + { + __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address */ + } FSARL_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t FSARH; /*!< (@ 0x00000110) Flash Processing Start Address Register H */ + + struct + { + __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address */ + uint16_t : 4; + __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address */ + } FSARH_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint8_t FCR; /*!< (@ 0x00000114) Flash Control Register */ + + struct + { + __IOM uint8_t CMD : 4; /*!< [3..0] Software Command Setting */ + __IOM uint8_t DRC : 1; /*!< [4..4] Data Read Completion */ + uint8_t : 1; + __IOM uint8_t STOP : 1; /*!< [6..6] Forced Processing Stop */ + __IOM uint8_t OPST : 1; /*!< [7..7] Processing Start */ + } FCR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t FEARL; /*!< (@ 0x00000118) Flash Processing End Address Register L */ + + struct + { + __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address */ + } FEARL_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t FEARH; /*!< (@ 0x00000120) Flash Processing End Address Register H */ + + struct + { + __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address */ + uint32_t : 4; + __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address */ + uint32_t : 16; + } FEARH_b; + }; + + union + { + __IOM uint32_t FRESETR; /*!< (@ 0x00000124) Flash Reset Register */ + + struct + { + __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers */ + uint32_t : 31; + } FRESETR_b; + }; + + union + { + __IM uint32_t FSTATR00; /*!< (@ 0x00000128) Flash Status Register00 */ + + struct + { + __IM uint32_t ERERR0 : 1; /*!< [0..0] Erase Error Flag0 */ + __IM uint32_t PRGERR0 : 1; /*!< [1..1] Program Error Flag0 */ + __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR0 : 1; /*!< [3..3] Blank Check Error Flag0 */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR00_b; + }; + + union + { + __IM uint32_t FSTATR1; /*!< (@ 0x0000012C) Flash Status Register1 */ + + struct + { + uint32_t : 1; + __IM uint32_t DRRDY : 1; /*!< [1..1] Data read request */ + uint32_t : 4; + __IM uint32_t FRDY : 1; /*!< [6..6] End status signal of a sequencer */ + __IM uint32_t EXRDY : 1; /*!< [7..7] End status signal of a Extra programming sequencer */ + uint32_t : 24; + } FSTATR1_b; + }; + + union + { + __IOM uint32_t FWBL0; /*!< (@ 0x00000130) Flash Write Buffer Register L0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL0_b; + }; + __IM uint32_t RESERVED15; + + union + { + __IOM uint32_t FWBH0; /*!< (@ 0x00000138) Flash Write Buffer Register H0 */ + + struct + { + __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH0_b; + }; + + union + { + __IM uint32_t FSTATR01; /*!< (@ 0x0000013C) Flash Status Register01 */ + + struct + { + __IM uint32_t ERERR1 : 1; /*!< [0..0] Erase Error Flag1 */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1 */ + uint32_t : 1; + __IM uint32_t BCERR1 : 1; /*!< [3..3] Blank Check Error Flag1 */ + uint32_t : 28; + } FSTATR01_b; + }; + + union + { + __IOM uint32_t FWBL1; /*!< (@ 0x00000140) Flash Write Buffer Register L1 */ + + struct + { + __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBL1_b; + }; + + union + { + __IOM uint32_t FWBH1; /*!< (@ 0x00000144) Flash Write Buffer Register H1 */ + + struct + { + __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command */ + uint32_t : 16; + } FWBH1_b; + }; + + union + { + __IM uint32_t FRBL1; /*!< (@ 0x00000148) Flash Read Buffer Register L1 */ + + struct + { + __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL1_b; + }; + + union + { + __IM uint32_t FRBH1; /*!< (@ 0x0000014C) Flash Read Buffer Register H1 */ + + struct + { + __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH1_b; + }; + __IM uint32_t RESERVED16[12]; + + union + { + __OM uint32_t FPR; /*!< (@ 0x00000180) Protection Unlock Register */ + + struct + { + __OM uint32_t FPR : 8; /*!< [7..0] Protection Unlock Register */ + uint32_t : 24; + } FPR_b; + }; + + union + { + __IM uint32_t FPSR; /*!< (@ 0x00000184) Protection Unlock Status Register */ + + struct + { + __IM uint32_t PERR : 1; /*!< [0..0] Protect Error Flag */ + uint32_t : 31; + } FPSR_b; + }; + + union + { + __IM uint32_t FRBL0; /*!< (@ 0x00000188) Flash Read Buffer Register L0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBL0_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IM uint32_t FRBH0; /*!< (@ 0x00000190) Flash Read Buffer Register H0 */ + + struct + { + __IM uint32_t RDATA : 16; /*!< [15..0] Read data of the consecutive read command */ + uint32_t : 16; + } FRBH0_b; + }; + __IM uint32_t RESERVED18[11]; + + union + { + __IM uint32_t FSCMR; /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SASMF : 1; /*!< [8..8] Start-up Area Setting Monitor Flag */ + uint32_t : 5; + __IM uint32_t FSPR : 1; /*!< [14..14] Access Window Protection Flag */ + uint32_t : 17; + } FSCMR_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IM uint32_t FAWSMR; /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register */ + + struct + { + __IM uint32_t FAWS : 12; /*!< [11..0] Flash Access Window Start Address */ + uint32_t : 20; + } FAWSMR_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IM uint32_t FAWEMR; /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register */ + + struct + { + __IM uint32_t FAWE : 12; /*!< [11..0] Flash Access Window End Address */ + uint32_t : 20; + } FAWEMR_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t FISR; /*!< (@ 0x000001D8) Flash Initial Setting Register */ + + struct + { + __IOM uint32_t PCKA : 6; /*!< [5..0] Peripheral Clock Notification */ + __IOM uint32_t SAS : 2; /*!< [7..6] Temporary boot swap mode */ + uint32_t : 24; + } FISR_b; + }; + + union + { + __IOM uint32_t FEXCR; /*!< (@ 0x000001DC) Flash Extra Area Control Register */ + + struct + { + __IOM uint32_t CMD : 3; /*!< [2..0] Processing Start) */ + uint32_t : 4; + __IOM uint32_t OPST : 1; /*!< [7..7] Software Command Setting */ + uint32_t : 24; + } FEXCR_b; + }; + + union + { + __IM uint32_t FEAML; /*!< (@ 0x000001E0) Flash Error Address Monitor Register L */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAML_b; + }; + __IM uint32_t RESERVED22; + + union + { + __IM uint32_t FEAMH; /*!< (@ 0x000001E8) Flash Error Address Monitor Register H */ + + struct + { + __IM uint32_t FEAM : 16; /*!< [15..0] Flash Error Address Monitor Register */ + uint32_t : 16; + } FEAMH_b; + }; + __IM uint32_t RESERVED23; + + union + { + __IM uint32_t FSTATR2; /*!< (@ 0x000001F0) Flash Status Register2 */ + + struct + { + __IM uint32_t ERERR : 1; /*!< [0..0] Erase Error Flag */ + __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag */ + __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01 */ + __IM uint32_t BCERR : 1; /*!< [3..3] Blank Check Error Flag */ + __IM uint32_t ILGLERR : 1; /*!< [4..4] Illegal Command Error Flag */ + __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag */ + uint32_t : 26; + } FSTATR2_b; + }; + __IM uint32_t RESERVED24[3951]; + __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ + __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ + __IM uint32_t RESERVED25[3]; + __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ + __IM uint8_t RESERVED26; + __IM uint16_t RESERVED27; + __IM uint32_t RESERVED28; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; +} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Operational Amplifier (R_OPAMP) + */ + +typedef struct /*!< (@ 0x40086000) R_OPAMP Structure */ +{ + __IM uint8_t RESERVED[8]; + + union + { + __IOM uint8_t AMPMC; /*!< (@ 0x00000008) Operational amplifier mode control register */ + + struct + { + __IOM uint8_t AMPPC0 : 1; /*!< [0..0] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC1 : 1; /*!< [1..1] Operational amplifier precharge control status */ + __IOM uint8_t AMPPC2 : 1; /*!< [2..2] Operational amplifier precharge control status */ + uint8_t : 4; + __IOM uint8_t AMPSP : 1; /*!< [7..7] Operation mode selection */ + } AMPMC_b; + }; + + union + { + __IOM uint8_t AMPTRM; /*!< (@ 0x00000009) Operational amplifier trigger mode control register */ + + struct + { + __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger + * control */ + __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger + * control */ + } AMPTRM_b; + }; + + union + { + __IOM uint8_t AMPTRS; /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select + * Register */ + + struct + { + __IOM uint8_t AMPTRS : 2; /*!< [1..0] ELC trigger selection Do not change the value of the + * AMPTRS register after setting the AMPTRM register. */ + uint8_t : 6; + } AMPTRS_b; + }; + + union + { + __IOM uint8_t AMPC; /*!< (@ 0x0000000B) Operational amplifier control register */ + + struct + { + __IOM uint8_t AMPE0 : 1; /*!< [0..0] Operation control of operational amplifier */ + __IOM uint8_t AMPE1 : 1; /*!< [1..1] Operation control of operational amplifier */ + __IOM uint8_t AMPE2 : 1; /*!< [2..2] Operation control of operational amplifier */ + __IOM uint8_t AMPE3 : 1; /*!< [3..3] Operation control of operational amplifier */ + uint8_t : 3; + __IOM uint8_t IREFE : 1; /*!< [7..7] Operation control of operational amplifier reference + * current circuit */ + } AMPC_b; + }; + + union + { + __IM uint8_t AMPMON; /*!< (@ 0x0000000C) Operational amplifier monitor register */ + + struct + { + __IM uint8_t AMPMON0 : 1; /*!< [0..0] Operational amplifier status */ + __IM uint8_t AMPMON1 : 1; /*!< [1..1] Operational amplifier status */ + __IM uint8_t AMPMON2 : 1; /*!< [2..2] Operational amplifier status */ + __IM uint8_t AMPMON3 : 1; /*!< [3..3] Operational amplifier status */ + uint8_t : 4; + } AMPMON_b; + }; + __IM uint8_t RESERVED1; + __IOM R_OPAMP_AMP_Type AMP[4]; /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier + * [0..3] */ + + union + { + __IOM uint8_t AMPCPC; /*!< (@ 0x0000001A) Operational amplifier switch charge pump control + * register */ + + struct + { + __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable */ + __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable */ + __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable */ + uint8_t : 5; + } AMPCPC_b; + }; + __IM uint8_t RESERVED2[4]; + + union + { + __IOM uint8_t AMPUOTE; /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable + * Register */ + + struct + { + __IOM uint8_t AMP0TE : 1; /*!< [0..0] AMP0OT write enable */ + __IOM uint8_t AMP1TE : 1; /*!< [1..1] AMP1OT write enable */ + __IOM uint8_t AMP2TE : 1; /*!< [2..2] AMP2OT write enable */ + uint8_t : 5; + } AMPUOTE_b; + }; + __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers */ +} R_OPAMP_Type; /*!< Size = 38 (0x26) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Segment LCD Controller/Driver (R_SLCDC) + */ + +typedef struct /*!< (@ 0x40082000) R_SLCDC Structure */ +{ + union + { + __IOM uint8_t LCDM0; /*!< (@ 0x00000000) LCD Mode Register 0 */ + + struct + { + __IOM uint8_t LBAS : 2; /*!< [1..0] LCD Display Bias Method Select */ + __IOM uint8_t LDTY : 3; /*!< [4..2] Time Slice of LCD Display Select */ + __IOM uint8_t LWAVE : 1; /*!< [5..5] LCD display waveform selection */ + __IOM uint8_t MDSET : 2; /*!< [7..6] LCD drive voltage generator selection */ + } LCDM0_b; + }; + + union + { + __IOM uint8_t LCDM1; /*!< (@ 0x00000001) LCD Mode Register 1 */ + + struct + { + __IOM uint8_t LCDVLM : 1; /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control */ + uint8_t : 2; + __IOM uint8_t LCDSEL : 1; /*!< [3..3] Display data area control */ + __IOM uint8_t BLON : 1; /*!< [4..4] Display data area control */ + __IOM uint8_t VLCON : 1; /*!< [5..5] Voltage boost circuit or capacitor split circuit operation + * enable/disable */ + __IOM uint8_t SCOC : 1; /*!< [6..6] LCD Display Enable/Disable */ + __IOM uint8_t LCDON : 1; /*!< [7..7] LCD Display Enable/Disable */ + } LCDM1_b; + }; + + union + { + __IOM uint8_t LCDC0; /*!< (@ 0x00000002) LCD Clock Control Register 0 */ + + struct + { + __IOM uint8_t LCDC : 6; /*!< [5..0] LCD clock (LCDCL) */ + uint8_t : 2; + } LCDC0_b; + }; + + union + { + __IOM uint8_t VLCD; /*!< (@ 0x00000003) LCD Boost Level Control Register */ + + struct + { + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 3; + } VLCD_b; + }; + __IM uint8_t RESERVED[252]; + + union + { + __IOM uint8_t SEG[64]; /*!< (@ 0x00000100) LCD Display Data Array */ + + struct + { + __IOM uint8_t A : 4; /*!< [3..0] A-Pattern Area */ + __IOM uint8_t B : 4; /*!< [7..4] B-Pattern Area */ + } SEG_b[64]; + }; +} R_SLCDC_Type; /*!< Size = 320 (0x140) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN) + */ + +typedef struct /*!< (@ 0x407EC000) R_TSN Structure */ +{ + __IM uint8_t RESERVED[552]; + + union + { + __IM uint8_t TSCDRL; /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register + * L */ + + struct + { + __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */ + } TSCDRL_b; + }; + + union + { + __IM uint8_t TSCDRH; /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register + * H */ + + struct + { + __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the + * convertedvalue. */ + } TSCDRH_b; + }; +} R_TSN_Type; /*!< Size = 554 (0x22a) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPLP_BASE 0x40085E00UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DAC8_BASE 0x4009E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_LP_BASE 0x407EC000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_OPAMP_BASE 0x40086000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SLCDC_BASE 0x40082000UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_BASE 0x407EC000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPLP ((R_ACMPLP_Type *) R_ACMPLP_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC8 ((R_DAC8_Type *) R_DAC8_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_LP ((R_FACI_LP_Type *) R_FACI_LP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_OPAMP ((R_OPAMP_Type *) R_OPAMP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SLCDC ((R_SLCDC_Type *) R_SLCDC_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN ((R_TSN_Type *) R_TSN_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ AMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OS =========================================================== */ +/* ========================================================== PS =========================================================== */ +/* ========================================================== MS =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ AMPOT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_OPAMP_AMPOT_P_TRMP_Pos (0UL) /*!< TRMP (Bit 0) */ + #define R_OPAMP_AMPOT_P_TRMP_Msk (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f) */ +/* =========================================================== N =========================================================== */ + #define R_OPAMP_AMPOT_N_TRMN_Pos (0UL) /*!< TRMN (Bit 0) */ + #define R_OPAMP_AMPOT_N_TRMN_Msk (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPLP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== COMPMDR ======================================================== */ + #define R_ACMPLP_COMPMDR_C1MON_Pos (7UL) /*!< C1MON (Bit 7) */ + #define R_ACMPLP_COMPMDR_C1MON_Msk (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1VRF_Pos (6UL) /*!< C1VRF (Bit 6) */ + #define R_ACMPLP_COMPMDR_C1VRF_Msk (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1WDE_Pos (5UL) /*!< C1WDE (Bit 5) */ + #define R_ACMPLP_COMPMDR_C1WDE_Msk (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C1ENB_Pos (4UL) /*!< C1ENB (Bit 4) */ + #define R_ACMPLP_COMPMDR_C1ENB_Msk (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0MON_Pos (3UL) /*!< C0MON (Bit 3) */ + #define R_ACMPLP_COMPMDR_C0MON_Msk (0x8UL) /*!< C0MON (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0WDE_Pos (1UL) /*!< C0WDE (Bit 1) */ + #define R_ACMPLP_COMPMDR_C0WDE_Msk (0x2UL) /*!< C0WDE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0VRF_Pos (2UL) /*!< C0VRF (Bit 2) */ + #define R_ACMPLP_COMPMDR_C0VRF_Msk (0x4UL) /*!< C0VRF (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPMDR_C0ENB_Pos (0UL) /*!< C0ENB (Bit 0) */ + #define R_ACMPLP_COMPMDR_C0ENB_Msk (0x1UL) /*!< C0ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== COMPFIR ======================================================== */ + #define R_ACMPLP_COMPFIR_C1EDG_Pos (7UL) /*!< C1EDG (Bit 7) */ + #define R_ACMPLP_COMPFIR_C1EDG_Msk (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1EPO_Pos (6UL) /*!< C1EPO (Bit 6) */ + #define R_ACMPLP_COMPFIR_C1EPO_Msk (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C1FCK_Pos (4UL) /*!< C1FCK (Bit 4) */ + #define R_ACMPLP_COMPFIR_C1FCK_Msk (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03) */ + #define R_ACMPLP_COMPFIR_C0EDG_Pos (3UL) /*!< C0EDG (Bit 3) */ + #define R_ACMPLP_COMPFIR_C0EDG_Msk (0x8UL) /*!< C0EDG (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0EPO_Pos (2UL) /*!< C0EPO (Bit 2) */ + #define R_ACMPLP_COMPFIR_C0EPO_Msk (0x4UL) /*!< C0EPO (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPFIR_C0FCK_Pos (0UL) /*!< C0FCK (Bit 0) */ + #define R_ACMPLP_COMPFIR_C0FCK_Msk (0x3UL) /*!< C0FCK (Bitfield-Mask: 0x03) */ +/* ======================================================== COMPOCR ======================================================== */ + #define R_ACMPLP_COMPOCR_SPDMD_Pos (7UL) /*!< SPDMD (Bit 7) */ + #define R_ACMPLP_COMPOCR_SPDMD_Msk (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OP_Pos (6UL) /*!< C1OP (Bit 6) */ + #define R_ACMPLP_COMPOCR_C1OP_Msk (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C1OE_Pos (5UL) /*!< C1OE (Bit 5) */ + #define R_ACMPLP_COMPOCR_C1OE_Msk (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OP_Pos (2UL) /*!< C0OP (Bit 2) */ + #define R_ACMPLP_COMPOCR_C0OP_Msk (0x4UL) /*!< C0OP (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPOCR_C0OE_Pos (1UL) /*!< C0OE (Bit 1) */ + #define R_ACMPLP_COMPOCR_C0OE_Msk (0x2UL) /*!< C0OE (Bitfield-Mask: 0x01) */ +/* ======================================================= COMPSEL0 ======================================================== */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Pos (4UL) /*!< IVCMP1 (Bit 4) */ + #define R_ACMPLP_COMPSEL0_IVCMP1_Msk (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Pos (0UL) /*!< IVCMP0 (Bit 0) */ + #define R_ACMPLP_COMPSEL0_IVCMP0_Msk (0x7UL) /*!< IVCMP0 (Bitfield-Mask: 0x07) */ +/* ======================================================= COMPSEL1 ======================================================== */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Pos (7UL) /*!< C1VRF2 (Bit 7) */ + #define R_ACMPLP_COMPSEL1_C1VRF2_Msk (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Pos (4UL) /*!< IVREF1 (Bit 4) */ + #define R_ACMPLP_COMPSEL1_IVREF1_Msk (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Pos (0UL) /*!< IVREF0 (Bit 0) */ + #define R_ACMPLP_COMPSEL1_IVREF0_Msk (0x7UL) /*!< IVREF0 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DAM ========================================================== */ + #define R_DAC8_DAM_DACE1_Pos (5UL) /*!< DACE1 (Bit 5) */ + #define R_DAC8_DAM_DACE1_Msk (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DACE0_Pos (4UL) /*!< DACE0 (Bit 4) */ + #define R_DAC8_DAM_DACE0_Msk (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD1_Pos (1UL) /*!< DAMD1 (Bit 1) */ + #define R_DAC8_DAM_DAMD1_Msk (0x2UL) /*!< DAMD1 (Bitfield-Mask: 0x01) */ + #define R_DAC8_DAM_DAMD0_Pos (0UL) /*!< DAMD0 (Bit 0) */ + #define R_DAC8_DAM_DAMD0_Msk (0x1UL) /*!< DAMD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= DACS ========================================================== */ + #define R_DAC8_DACS_DACS_Pos (0UL) /*!< DACS (Bit 0) */ + #define R_DAC8_DACS_DACS_Msk (0xffUL) /*!< DACS (Bitfield-Mask: 0xff) */ +/* ======================================================= DACADSCR ======================================================== */ + #define R_DAC8_DACADSCR_DACADST_Pos (0UL) /*!< DACADST (Bit 0) */ + #define R_DAC8_DACADSCR_DACADST_Msk (0x1UL) /*!< DACADST (Bitfield-Mask: 0x01) */ +/* ========================================================= DACPC ========================================================= */ + #define R_DAC8_DACPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC8_DACPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_LP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DFLCTL ========================================================= */ +/* ========================================================= FPMCR ========================================================= */ + #define R_FACI_LP_FPMCR_FMS2_Pos (7UL) /*!< FMS2 (Bit 7) */ + #define R_FACI_LP_FPMCR_FMS2_Msk (0x80UL) /*!< FMS2 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_VLPE_Pos (6UL) /*!< VLPE (Bit 6) */ + #define R_FACI_LP_FPMCR_VLPE_Msk (0x40UL) /*!< VLPE (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS1_Pos (4UL) /*!< FMS1 (Bit 4) */ + #define R_FACI_LP_FPMCR_FMS1_Msk (0x10UL) /*!< FMS1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_RPDIS_Pos (3UL) /*!< RPDIS (Bit 3) */ + #define R_FACI_LP_FPMCR_RPDIS_Msk (0x8UL) /*!< RPDIS (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FPMCR_FMS0_Pos (1UL) /*!< FMS0 (Bit 1) */ + #define R_FACI_LP_FPMCR_FMS0_Msk (0x2UL) /*!< FMS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FASR ========================================================== */ + #define R_FACI_LP_FASR_EXS_Pos (0UL) /*!< EXS (Bit 0) */ + #define R_FACI_LP_FASR_EXS_Msk (0x1UL) /*!< EXS (Bitfield-Mask: 0x01) */ +/* ========================================================= FSARL ========================================================= */ + #define R_FACI_LP_FSARL_FSAR15_0_Pos (0UL) /*!< FSAR15_0 (Bit 0) */ + #define R_FACI_LP_FSARL_FSAR15_0_Msk (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSARH ========================================================= */ + #define R_FACI_LP_FSARH_FSAR31_25_Pos (9UL) /*!< FSAR31_25 (Bit 9) */ + #define R_FACI_LP_FSARH_FSAR31_25_Msk (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FSARH_FSAR20_16_Pos (0UL) /*!< FSAR20_16 (Bit 0) */ + #define R_FACI_LP_FSARH_FSAR20_16_Msk (0x1fUL) /*!< FSAR20_16 (Bitfield-Mask: 0x1f) */ +/* ========================================================== FCR ========================================================== */ + #define R_FACI_LP_FCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_STOP_Pos (6UL) /*!< STOP (Bit 6) */ + #define R_FACI_LP_FCR_STOP_Msk (0x40UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_DRC_Pos (4UL) /*!< DRC (Bit 4) */ + #define R_FACI_LP_FCR_DRC_Msk (0x10UL) /*!< DRC (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FCR_CMD_Msk (0xfUL) /*!< CMD (Bitfield-Mask: 0x0f) */ +/* ========================================================= FEARL ========================================================= */ + #define R_FACI_LP_FEARL_FEAR15_0_Pos (0UL) /*!< FEAR15_0 (Bit 0) */ + #define R_FACI_LP_FEARL_FEAR15_0_Msk (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEARH ========================================================= */ + #define R_FACI_LP_FEARH_FEAR31_25_Pos (9UL) /*!< FEAR31_25 (Bit 9) */ + #define R_FACI_LP_FEARH_FEAR31_25_Msk (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f) */ + #define R_FACI_LP_FEARH_FEAR20_16_Pos (0UL) /*!< FEAR20_16 (Bit 0) */ + #define R_FACI_LP_FEARH_FEAR20_16_Msk (0x1fUL) /*!< FEAR20_16 (Bitfield-Mask: 0x1f) */ +/* ======================================================== FRESETR ======================================================== */ + #define R_FACI_LP_FRESETR_FRESET_Pos (0UL) /*!< FRESET (Bit 0) */ + #define R_FACI_LP_FRESETR_FRESET_Msk (0x1UL) /*!< FRESET (Bitfield-Mask: 0x01) */ +/* ======================================================= FSTATR00 ======================================================== */ + #define R_FACI_LP_FSTATR00_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR00_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR00_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_BCERR0_Pos (3UL) /*!< BCERR0 (Bit 3) */ + #define R_FACI_LP_FSTATR00_BCERR0_Msk (0x8UL) /*!< BCERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR00_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Pos (1UL) /*!< PRGERR0 (Bit 1) */ + #define R_FACI_LP_FSTATR00_PRGERR0_Msk (0x2UL) /*!< PRGERR0 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR00_ERERR0_Pos (0UL) /*!< ERERR0 (Bit 0) */ + #define R_FACI_LP_FSTATR00_ERERR0_Msk (0x1UL) /*!< ERERR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR1 ======================================================== */ + #define R_FACI_LP_FSTATR1_EXRDY_Pos (7UL) /*!< EXRDY (Bit 7) */ + #define R_FACI_LP_FSTATR1_EXRDY_Msk (0x80UL) /*!< EXRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_FRDY_Pos (6UL) /*!< FRDY (Bit 6) */ + #define R_FACI_LP_FSTATR1_FRDY_Msk (0x40UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR1_DRRDY_Pos (1UL) /*!< DRRDY (Bit 1) */ + #define R_FACI_LP_FSTATR1_DRRDY_Msk (0x2UL) /*!< DRRDY (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL0 ========================================================= */ + #define R_FACI_LP_FWBL0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBL0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH0 ========================================================= */ + #define R_FACI_LP_FWBH0_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_FACI_LP_FWBH0_WDATA_Msk (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= FSTATR01 ======================================================== */ + #define R_FACI_LP_FSTATR01_BCERR1_Pos (3UL) /*!< BCERR1 (Bit 3) */ + #define R_FACI_LP_FSTATR01_BCERR1_Msk (0x8UL) /*!< BCERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR01_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR01_ERERR1_Pos (0UL) /*!< ERERR1 (Bit 0) */ + #define R_FACI_LP_FSTATR01_ERERR1_Msk (0x1UL) /*!< ERERR1 (Bitfield-Mask: 0x01) */ +/* ========================================================= FWBL1 ========================================================= */ + #define R_FACI_LP_FWBL1_WDATA47_32_Pos (0UL) /*!< WDATA47_32 (Bit 0) */ + #define R_FACI_LP_FWBL1_WDATA47_32_Msk (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FWBH1 ========================================================= */ + #define R_FACI_LP_FWBH1_WDATA63_48_Pos (0UL) /*!< WDATA63_48 (Bit 0) */ + #define R_FACI_LP_FWBH1_WDATA63_48_Msk (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBL1 ========================================================= */ + #define R_FACI_LP_FRBL1_RDATA47_32_Pos (0UL) /*!< RDATA47_32 (Bit 0) */ + #define R_FACI_LP_FRBL1_RDATA47_32_Msk (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH1 ========================================================= */ + #define R_FACI_LP_FRBH1_RDATA63_48_Pos (0UL) /*!< RDATA63_48 (Bit 0) */ + #define R_FACI_LP_FRBH1_RDATA63_48_Msk (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff) */ +/* ========================================================== FPR ========================================================== */ + #define R_FACI_LP_FPR_FPR_Pos (0UL) /*!< FPR (Bit 0) */ + #define R_FACI_LP_FPR_FPR_Msk (0xffUL) /*!< FPR (Bitfield-Mask: 0xff) */ +/* ========================================================= FPSR ========================================================== */ + #define R_FACI_LP_FPSR_PERR_Pos (0UL) /*!< PERR (Bit 0) */ + #define R_FACI_LP_FPSR_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= FRBL0 ========================================================= */ + #define R_FACI_LP_FRBL0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBL0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FRBH0 ========================================================= */ + #define R_FACI_LP_FRBH0_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_FACI_LP_FRBH0_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= FSCMR ========================================================= */ + #define R_FACI_LP_FSCMR_FSPR_Pos (14UL) /*!< FSPR (Bit 14) */ + #define R_FACI_LP_FSCMR_FSPR_Msk (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSCMR_SASMF_Pos (8UL) /*!< SASMF (Bit 8) */ + #define R_FACI_LP_FSCMR_SASMF_Msk (0x100UL) /*!< SASMF (Bitfield-Mask: 0x01) */ +/* ======================================================== FAWSMR ========================================================= */ + #define R_FACI_LP_FAWSMR_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_LP_FAWSMR_FAWS_Msk (0xfffUL) /*!< FAWS (Bitfield-Mask: 0xfff) */ +/* ======================================================== FAWEMR ========================================================= */ + #define R_FACI_LP_FAWEMR_FAWE_Pos (0UL) /*!< FAWE (Bit 0) */ + #define R_FACI_LP_FAWEMR_FAWE_Msk (0xfffUL) /*!< FAWE (Bitfield-Mask: 0xfff) */ +/* ========================================================= FISR ========================================================== */ + #define R_FACI_LP_FISR_SAS_Pos (6UL) /*!< SAS (Bit 6) */ + #define R_FACI_LP_FISR_SAS_Msk (0xc0UL) /*!< SAS (Bitfield-Mask: 0x03) */ + #define R_FACI_LP_FISR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_LP_FISR_PCKA_Msk (0x3fUL) /*!< PCKA (Bitfield-Mask: 0x3f) */ +/* ========================================================= FEXCR ========================================================= */ + #define R_FACI_LP_FEXCR_OPST_Pos (7UL) /*!< OPST (Bit 7) */ + #define R_FACI_LP_FEXCR_OPST_Msk (0x80UL) /*!< OPST (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FEXCR_CMD_Pos (0UL) /*!< CMD (Bit 0) */ + #define R_FACI_LP_FEXCR_CMD_Msk (0x7UL) /*!< CMD (Bitfield-Mask: 0x07) */ +/* ========================================================= FEAML ========================================================= */ + #define R_FACI_LP_FEAML_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAML_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FEAMH ========================================================= */ + #define R_FACI_LP_FEAMH_FEAM_Pos (0UL) /*!< FEAM (Bit 0) */ + #define R_FACI_LP_FEAMH_FEAM_Msk (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff) */ +/* ======================================================== FSTATR2 ======================================================== */ + #define R_FACI_LP_FSTATR2_EILGLERR_Pos (5UL) /*!< EILGLERR (Bit 5) */ + #define R_FACI_LP_FSTATR2_EILGLERR_Msk (0x20UL) /*!< EILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Pos (4UL) /*!< ILGLERR (Bit 4) */ + #define R_FACI_LP_FSTATR2_ILGLERR_Msk (0x10UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_BCERR_Pos (3UL) /*!< BCERR (Bit 3) */ + #define R_FACI_LP_FSTATR2_BCERR_Msk (0x8UL) /*!< BCERR (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Pos (2UL) /*!< PRGERR01 (Bit 2) */ + #define R_FACI_LP_FSTATR2_PRGERR01_Msk (0x4UL) /*!< PRGERR01 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Pos (1UL) /*!< PRGERR1 (Bit 1) */ + #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ + #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ====================================================== FENTRYR_MF4 ====================================================== */ +/* ======================================================== FENTRYR ======================================================== */ +/* ======================================================== FLWAITR ======================================================== */ +/* ========================================================= PFBER ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OPAMP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= AMPMC ========================================================= */ + #define R_OPAMP_AMPMC_AMPSP_Pos (7UL) /*!< AMPSP (Bit 7) */ + #define R_OPAMP_AMPMC_AMPSP_Msk (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPMC_AMPPC_Pos (0UL) /*!< AMPPC (Bit 0) */ + #define R_OPAMP_AMPMC_AMPPC_Msk (0x1UL) /*!< AMPPC (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPTRM ========================================================= */ + #define R_OPAMP_AMPTRM_AMPTRM_Pos (0UL) /*!< AMPTRM (Bit 0) */ + #define R_OPAMP_AMPTRM_AMPTRM_Msk (0x3UL) /*!< AMPTRM (Bitfield-Mask: 0x03) */ +/* ======================================================== AMPTRS ========================================================= */ + #define R_OPAMP_AMPTRS_AMPTRS_Pos (0UL) /*!< AMPTRS (Bit 0) */ + #define R_OPAMP_AMPTRS_AMPTRS_Msk (0x3UL) /*!< AMPTRS (Bitfield-Mask: 0x03) */ +/* ========================================================= AMPC ========================================================== */ + #define R_OPAMP_AMPC_IREFE_Pos (7UL) /*!< IREFE (Bit 7) */ + #define R_OPAMP_AMPC_IREFE_Msk (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01) */ + #define R_OPAMP_AMPC_AMPE_Pos (0UL) /*!< AMPE (Bit 0) */ + #define R_OPAMP_AMPC_AMPE_Msk (0x1UL) /*!< AMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPMON ========================================================= */ + #define R_OPAMP_AMPMON_AMPMON_Pos (0UL) /*!< AMPMON (Bit 0) */ + #define R_OPAMP_AMPMON_AMPMON_Msk (0x1UL) /*!< AMPMON (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPCPC ========================================================= */ + #define R_OPAMP_AMPCPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_OPAMP_AMPCPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== AMPUOTE ======================================================== */ + #define R_OPAMP_AMPUOTE_AMPTE_Pos (0UL) /*!< AMPTE (Bit 0) */ + #define R_OPAMP_AMPUOTE_AMPTE_Msk (0x1UL) /*!< AMPTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SLCDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LCDM0 ========================================================= */ + #define R_SLCDC_LCDM0_MDSET_Pos (6UL) /*!< MDSET (Bit 6) */ + #define R_SLCDC_LCDM0_MDSET_Msk (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03) */ + #define R_SLCDC_LCDM0_LWAVE_Pos (5UL) /*!< LWAVE (Bit 5) */ + #define R_SLCDC_LCDM0_LWAVE_Msk (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM0_LDTY_Pos (2UL) /*!< LDTY (Bit 2) */ + #define R_SLCDC_LCDM0_LDTY_Msk (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07) */ + #define R_SLCDC_LCDM0_LBAS_Pos (0UL) /*!< LBAS (Bit 0) */ + #define R_SLCDC_LCDM0_LBAS_Msk (0x3UL) /*!< LBAS (Bitfield-Mask: 0x03) */ +/* ========================================================= LCDM1 ========================================================= */ + #define R_SLCDC_LCDM1_LCDON_Pos (7UL) /*!< LCDON (Bit 7) */ + #define R_SLCDC_LCDM1_LCDON_Msk (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_SCOC_Pos (6UL) /*!< SCOC (Bit 6) */ + #define R_SLCDC_LCDM1_SCOC_Msk (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_VLCON_Pos (5UL) /*!< VLCON (Bit 5) */ + #define R_SLCDC_LCDM1_VLCON_Msk (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_BLON_Pos (4UL) /*!< BLON (Bit 4) */ + #define R_SLCDC_LCDM1_BLON_Msk (0x10UL) /*!< BLON (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDSEL_Pos (3UL) /*!< LCDSEL (Bit 3) */ + #define R_SLCDC_LCDM1_LCDSEL_Msk (0x8UL) /*!< LCDSEL (Bitfield-Mask: 0x01) */ + #define R_SLCDC_LCDM1_LCDVLM_Pos (0UL) /*!< LCDVLM (Bit 0) */ + #define R_SLCDC_LCDM1_LCDVLM_Msk (0x1UL) /*!< LCDVLM (Bitfield-Mask: 0x01) */ +/* ========================================================= LCDC0 ========================================================= */ + #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */ + #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */ +/* ========================================================= VLCD ========================================================== */ + #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */ + #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */ +/* ========================================================== SEG ========================================================== */ + #define R_SLCDC_SEG_A_Pos (0UL) /*!< A (Bit 0) */ + #define R_SLCDC_SEG_A_Msk (0xfUL) /*!< A (Bitfield-Mask: 0x0f) */ + #define R_SLCDC_SEG_B_Pos (4UL) /*!< B (Bit 4) */ + #define R_SLCDC_SEG_B_Msk (0xf0UL) /*!< B (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TSCDRH ========================================================= */ + #define R_TSN_TSCDRH_TSCDRH_Pos (0UL) /*!< TSCDRH (Bit 0) */ + #define R_TSN_TSCDRH_TSCDRH_Msk (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff) */ +/* ======================================================== TSCDRL ========================================================= */ + #define R_TSN_TSCDRL_TSCDRL_Pos (0UL) /*!< TSCDRL (Bit 0) */ + #define R_TSN_TSCDRL_TSCDRL_Msk (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA4W1AD_H */ + +/** @} */ /* End of group R7FA4W1AD */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h new file mode 100644 index 00000000..ac3e59b9 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h @@ -0,0 +1,19595 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA6E10F.h + * @brief CMSIS HeaderFile + * @version 1.10.00 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:50:60 + * from File 'svd-test/R7FA6E10F.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA6E10F + * @{ + */ + +#ifndef R7FA6E10F_H + #define R7FA6E10F_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA6E10F System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_ETHERC0_BASE 0x40114100UL + #define R_ETHERC_EDMAC_BASE 0x40114000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6E10F_H */ + +/** @} */ /* End of group R7FA6E10F */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h new file mode 100644 index 00000000..809ff39b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h @@ -0,0 +1,20311 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA6M1AD.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:51:02 + * from File 'svd-test/R7FA6M1AD.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA6M1AD + * @{ + */ + +#ifndef R7FA6M1AD_H + #define R7FA6M1AD_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA6M1AD System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDHI0_BASE 0x40062000UL + #define R_SDHI1_BASE 0x40062400UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + #define R_USB_HS0_BASE 0x40060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M1AD_H */ + +/** @} */ /* End of group R7FA6M1AD */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h new file mode 100644 index 00000000..c7437f3d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h @@ -0,0 +1,23295 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA6M2AF.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:51:03 + * from File 'svd-test/R7FA6M2AF.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA6M2AF + * @{ + */ + +#ifndef R7FA6M2AF_H + #define R7FA6M2AF_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA6M2AF System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x40083000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED30[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Data Capture Unit (R_PDC) + */ + +typedef struct /*!< (@ 0x40094000) R_PDC Structure */ +{ + union + { + __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + + struct + { + __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ + __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ + __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ + __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ + __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ + __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ + __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ + __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ + __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ + __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ + __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ + __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ + __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ + uint32_t : 17; + } PCCR0_b; + }; + + union + { + __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + + struct + { + __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ + uint32_t : 31; + } PCCR1_b; + }; + + union + { + __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + + struct + { + __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ + __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ + __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ + __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ + __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ + __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ + __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ + uint32_t : 25; + } PCSR_b; + }; + + union + { + __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + + struct + { + __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ + __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ + uint32_t : 30; + } PCMONR_b; + }; + + union + { + __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + + struct + { + __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the + * storage of captured data. The PCDR register is a 4-byte + * space to which the FIFO is mapped, and four bytes of data + * are read from the PCDR register at a time. */ + } PCDR_b; + }; + + union + { + __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + + struct + { + __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line + * where capture is to start. */ + uint32_t : 4; + __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ + uint32_t : 4; + } VCR_b; + }; + + union + { + __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + + struct + { + __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position + * in bytes where capture is to start. */ + uint32_t : 4; + __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture + * horizontally. */ + uint32_t : 4; + } HCR_b; + }; +} R_PDC_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_ETHERC0_BASE 0x40064100UL + #define R_ETHERC_EDMAC_BASE 0x40064000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_I3C0_BASE 0x40083000UL + #define R_I3C1_BASE 0x40083400UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PDC_BASE 0x40094000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDHI0_BASE 0x40062000UL + #define R_SDHI1_BASE 0x40062400UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + #define R_USB_HS0_BASE 0x40060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PDC ((R_PDC_Type *) R_PDC_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCCR0 ========================================================= */ + #define R_PDC_PCCR0_EDS_Pos (14UL) /*!< EDS (Bit 14) */ + #define R_PDC_PCCR0_EDS_Msk (0x4000UL) /*!< EDS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKDIV_Pos (11UL) /*!< PCKDIV (Bit 11) */ + #define R_PDC_PCCR0_PCKDIV_Msk (0x3800UL) /*!< PCKDIV (Bitfield-Mask: 0x07) */ + #define R_PDC_PCCR0_PCKOE_Pos (10UL) /*!< PCKOE (Bit 10) */ + #define R_PDC_PCCR0_PCKOE_Msk (0x400UL) /*!< PCKOE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HERIE_Pos (9UL) /*!< HERIE (Bit 9) */ + #define R_PDC_PCCR0_HERIE_Msk (0x200UL) /*!< HERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VERIE_Pos (8UL) /*!< VERIE (Bit 8) */ + #define R_PDC_PCCR0_VERIE_Msk (0x100UL) /*!< VERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_UDRIE_Pos (7UL) /*!< UDRIE (Bit 7) */ + #define R_PDC_PCCR0_UDRIE_Msk (0x80UL) /*!< UDRIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_OVIE_Pos (6UL) /*!< OVIE (Bit 6) */ + #define R_PDC_PCCR0_OVIE_Msk (0x40UL) /*!< OVIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_FEIE_Pos (5UL) /*!< FEIE (Bit 5) */ + #define R_PDC_PCCR0_FEIE_Msk (0x20UL) /*!< FEIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_DFIE_Pos (4UL) /*!< DFIE (Bit 4) */ + #define R_PDC_PCCR0_DFIE_Msk (0x10UL) /*!< DFIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PRST_Pos (3UL) /*!< PRST (Bit 3) */ + #define R_PDC_PCCR0_PRST_Msk (0x8UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HPS_Pos (2UL) /*!< HPS (Bit 2) */ + #define R_PDC_PCCR0_HPS_Msk (0x4UL) /*!< HPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VPS_Pos (1UL) /*!< VPS (Bit 1) */ + #define R_PDC_PCCR0_VPS_Msk (0x2UL) /*!< VPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKE_Pos (0UL) /*!< PCKE (Bit 0) */ + #define R_PDC_PCCR0_PCKE_Msk (0x1UL) /*!< PCKE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCCR1 ========================================================= */ + #define R_PDC_PCCR1_PCE_Pos (0UL) /*!< PCE (Bit 0) */ + #define R_PDC_PCCR1_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCSR ========================================================== */ + #define R_PDC_PCSR_HERF_Pos (6UL) /*!< HERF (Bit 6) */ + #define R_PDC_PCSR_HERF_Msk (0x40UL) /*!< HERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_VERF_Pos (5UL) /*!< VERF (Bit 5) */ + #define R_PDC_PCSR_VERF_Msk (0x20UL) /*!< VERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_PDC_PCSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_OVRF_Pos (3UL) /*!< OVRF (Bit 3) */ + #define R_PDC_PCSR_OVRF_Msk (0x8UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEF_Pos (2UL) /*!< FEF (Bit 2) */ + #define R_PDC_PCSR_FEF_Msk (0x4UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEMPF_Pos (1UL) /*!< FEMPF (Bit 1) */ + #define R_PDC_PCSR_FEMPF_Msk (0x2UL) /*!< FEMPF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FBSY_Pos (0UL) /*!< FBSY (Bit 0) */ + #define R_PDC_PCSR_FBSY_Msk (0x1UL) /*!< FBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PCMONR ========================================================= */ + #define R_PDC_PCMONR_HSYNC_Pos (1UL) /*!< HSYNC (Bit 1) */ + #define R_PDC_PCMONR_HSYNC_Msk (0x2UL) /*!< HSYNC (Bitfield-Mask: 0x01) */ + #define R_PDC_PCMONR_VSYNC_Pos (0UL) /*!< VSYNC (Bit 0) */ + #define R_PDC_PCMONR_VSYNC_Msk (0x1UL) /*!< VSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PCDR ========================================================== */ + #define R_PDC_PCDR_PCDR_Pos (0UL) /*!< PCDR (Bit 0) */ + #define R_PDC_PCDR_PCDR_Msk (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== VCR ========================================================== */ + #define R_PDC_VCR_VSZ_Pos (16UL) /*!< VSZ (Bit 16) */ + #define R_PDC_VCR_VSZ_Msk (0xfff0000UL) /*!< VSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_VCR_VST_Pos (0UL) /*!< VST (Bit 0) */ + #define R_PDC_VCR_VST_Msk (0xfffUL) /*!< VST (Bitfield-Mask: 0xfff) */ +/* ========================================================== HCR ========================================================== */ + #define R_PDC_HCR_HSZ_Pos (16UL) /*!< HSZ (Bit 16) */ + #define R_PDC_HCR_HSZ_Msk (0xfff0000UL) /*!< HSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_HCR_HST_Pos (0UL) /*!< HST (Bit 0) */ + #define R_PDC_HCR_HST_Msk (0xfffUL) /*!< HST (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M2AF_H */ + +/** @} */ /* End of group R7FA6M2AF */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h new file mode 100644 index 00000000..2041059f --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -0,0 +1,26930 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file svd-test/R7FA6M3AH.h + * @brief CMSIS HeaderFile + * @version 1.2 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:51:05 + * from File 'svd-test/R7FA6M3AH.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA6M3AH + * @{ + */ + +#ifndef R7FA6M3AH_H + #define R7FA6M3AH_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA6M3AH System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_TM [TM] (Timer Setting Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t STTRU; /*!< (@ 0x00000000) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the start time of the pulse output timer in nanoseconds. */ + } STTRU_b; + }; + + union + { + __IOM uint32_t STTRL; /*!< (@ 0x00000004) Timer Start Time Setting Register */ + + struct + { + __IOM uint32_t TMSTTRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the start time of the pulse output timer in nanoseconds. */ + } STTRL_b; + }; + + union + { + __IOM uint32_t CYCR; /*!< (@ 0x00000008) Timer Cycle Setting Registers */ + + struct + { + __IOM uint32_t TMCYCR : 30; /*!< [29..0] These bits set the cycle of the pulse output timer in + * nanoseconds. Set a value that is equivalent to at least + * four cycles of the STCA clock. */ + uint32_t : 2; + } CYCR_b; + }; + + union + { + __IOM uint32_t PLSR; /*!< (@ 0x0000000C) Timer Pulse Width Setting Register */ + + struct + { + __IOM uint32_t TMPLSR : 29; /*!< [28..0] These bits set the width at high level of the pulse + * signal from the timer in nanoseconds. Set a value that + * is equivalent to at least two cycles of the STCA clock. */ + uint32_t : 3; + } PLSR_b; + }; +} R_ETHERC_EPTPC_COMMON_TM_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ETHERC_EPTPC_COMMON_PR [PR] (Local MAC Address Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t MACRU; /*!< (@ 0x00000000) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRU_b; + }; + + union + { + __IOM uint32_t MACRL; /*!< (@ 0x00000004) Channel Local MAC Address Register */ + + struct + { + __IOM uint32_t PRMACRL : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address for Ethernet port 0. */ + uint32_t : 8; + } MACRL_b; + }; +} R_ETHERC_EPTPC_COMMON_PR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_GLCDC_BG [BG] (Background Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) Background Plane Setting Operation Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation enable */ + uint32_t : 7; + __IOM uint32_t VEN : 1; /*!< [8..8] Control of LCDC internal register value reflection to + * internal operations */ + uint32_t : 7; + __IOM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset control */ + uint32_t : 15; + } EN_b; + }; + + union + { + __IOM uint32_t PERI; /*!< (@ 0x00000004) Background Plane Setting Free-Running Period + * Register */ + + struct + { + __IOM uint32_t FH : 11; /*!< [10..0] Background plane horizontal synchronization signal period + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + __IOM uint32_t FV : 11; /*!< [26..16] Background plane vertical synchronization signal period + * on the basis of line. */ + uint32_t : 5; + } PERI_b; + }; + + union + { + __IOM uint32_t SYNC; /*!< (@ 0x00000008) Background Plane Setting Synchronization Position + * Register */ + + struct + { + __IOM uint32_t HP : 4; /*!< [3..0] Background plane horizontal synchronization signal assertion + * position on the basis of pixel clock (PXCLK). */ + uint32_t : 12; + __IOM uint32_t VP : 4; /*!< [19..16] Background plane vertical synchronization signal assertion + * position on the basis of line. */ + uint32_t : 12; + } SYNC_b; + }; + + union + { + __IOM uint32_t VSIZE; /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical + * Size Register */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] Background plane vertical valid pixel width on the basis + * of line */ + uint32_t : 5; + __IOM uint32_t VP : 11; /*!< [26..16] Background plane vertical valid pixel start position + * on the basis of line */ + uint32_t : 5; + } VSIZE_b; + }; + + union + { + __IOM uint32_t HSIZE; /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal + * Size Register */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] Background plane horizontall valid pixel width on the + * basis of pixel clock (PXCLK) Note: When serial RGB is selected + * as the output format for the output control block, add + * two to the horizontal enable signal width and set the resulting + * value to this field. */ + uint32_t : 5; + __IOM uint32_t HP : 11; /*!< [26..16] Background plane horizontal valid pixel start position + * on the basis of pixel clock (PXCLK). */ + uint32_t : 5; + } HSIZE_b; + }; + + union + { + __IOM uint32_t BGC; /*!< (@ 0x00000014) Background Plane Setting Background Color Register */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t G : 8; /*!< [15..8] G value for background plane valid pixel area Unsigned; + * 8-bit integer */ + __IOM uint32_t R : 8; /*!< [23..16] R value for background plane valid pixel area. Unsigned; + * 8-bit integer. */ + uint32_t : 8; + } BGC_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Background plane generation module operation state monitor. */ + uint32_t : 7; + __IM uint32_t VEN : 1; /*!< [8..8] Entire module internal operation reflection control signal + * monitor. The signal state for controlling reflection of + * the register values to the internal operations upon assertion + * of the vertical synchronization signal. */ + uint32_t : 7; + __IM uint32_t SWRST : 1; /*!< [16..16] Entire module SW reset state monitor. */ + uint32_t : 15; + } MON_b; + }; +} R_GLCDC_BG_Type; /*!< Size = 28 (0x1c) */ + +/** + * @brief R_GLCDC_GR [GR] (Layer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VEN; /*!< (@ 0x00000000) Graphics Register Update Control Register */ + + struct + { + __IOM uint32_t PVEN : 1; /*!< [0..0] Control of graphics n module register value reflection + * to internal operations. Reflection of the register values + * to the internal operation at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VEN_b; + }; + + union + { + __IOM uint32_t FLMRD; /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register */ + + struct + { + __IOM uint32_t RENB : 1; /*!< [0..0] Graphics data (frame buffer data) read enable. */ + uint32_t : 31; + } FLMRD_b; + }; + + union + { + __IM uint32_t FLM1; /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1 */ + + struct + { + __IM uint32_t BSTMD : 2; /*!< [1..0] Burst transfer control for graphics data (frame buffer + * data) access */ + uint32_t : 30; + } FLM1_b; + }; + + union + { + __IOM uint32_t FLM2; /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2 */ + + struct + { + __IOM uint32_t BASE : 32; /*!< [31..0] Base address for accessing graphics data (frame buffer + * data) Set the head address in the frame buffer where graphics + * data is to be stored. GRn_FLM2.BASE[5:0] should be fixed + * to 0 during 64-byte burst transfer. */ + } FLM2_b; + }; + + union + { + __IOM uint32_t FLM3; /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3 */ + + struct + { + uint32_t : 16; + __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data + * (frame buffer data) Signed; 16-bit integer */ + } FLM3_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t FLM5; /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5 */ + + struct + { + __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing + * graphics data (frame buffer data), where one transfer is + * defined as 16-beat burst access (64-byte boundary) */ + __IOM uint32_t LNNUM : 11; /*!< [26..16] Number of lines per frame for accessing graphics data + * (frame buffer data). */ + uint32_t : 5; + } FLM5_b; + }; + + union + { + __IOM uint32_t FLM6; /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6 */ + + struct + { + uint32_t : 28; + __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer + * data). */ + uint32_t : 1; + } FLM6_b; + }; + + union + { + __IOM uint32_t AB1; /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1 */ + + struct + { + __IOM uint32_t DISPSEL : 2; /*!< [1..0] Graphics display plane control. */ + uint32_t : 2; + __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control. */ + uint32_t : 3; + __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area + * alpha blending. */ + uint32_t : 3; + __IOM uint32_t ARCON : 1; /*!< [12..12] Rectangular area alpha blending control. */ + uint32_t : 19; + } AB1_b; + }; + + union + { + __IOM uint32_t AB2; /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2 */ + + struct + { + __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area. */ + uint32_t : 5; + } AB2_b; + }; + + union + { + __IOM uint32_t AB3; /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3 */ + + struct + { + __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area. */ + uint32_t : 5; + __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area. */ + uint32_t : 5; + } AB3_b; + }; + + union + { + __IOM uint32_t AB4; /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4 */ + + struct + { + __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image + * area. */ + uint32_t : 5; + __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending + * image area */ + uint32_t : 5; + } AB4_b; + }; + + union + { + __IOM uint32_t AB5; /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5 */ + + struct + { + __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending + * image area. */ + uint32_t : 5; + __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha + * blending image area. */ + uint32_t : 5; + } AB5_b; + }; + + union + { + __IOM uint32_t AB6; /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6 */ + + struct + { + __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area. */ + uint32_t : 8; + __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular + * area (-255 to 255). [8]: Sign (0: addition, 1: subtraction) + * [7:0]: Variation (absolute value) */ + uint32_t : 7; + } AB6_b; + }; + + union + { + __IOM uint32_t AB7; /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7 */ + + struct + { + __IOM uint32_t CKON : 1; /*!< [0..0] RGB-index chroma-key processing control. */ + uint32_t : 15; + __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular + * area. */ + uint32_t : 8; + } AB7_b; + }; + + union + { + __IOM uint32_t AB8; /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8 */ + + struct + { + __IOM uint32_t CKKR : 8; /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKB : 8; /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + __IOM uint32_t CKKG : 8; /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned; + * 8 bits. */ + uint32_t : 8; + } AB8_b; + }; + + union + { + __IOM uint32_t AB9; /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9 */ + + struct + { + __IOM uint32_t CKR : 8; /*!< [7..0] R value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKB : 8; /*!< [15..8] B value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKG : 8; /*!< [23..16] G value after RGB-index chroma-key processing replacement + * Unsigned; 8 bits. */ + __IOM uint32_t CKA : 8; /*!< [31..24] A value after RGB-index chroma-key processing replacement. */ + } AB9_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t BASE; /*!< (@ 0x0000004C) Graphics Background Color Control Register */ + + struct + { + __IOM uint32_t R : 8; /*!< [7..0] Background color R value Unsigned; 8 bits */ + __IOM uint32_t B : 8; /*!< [15..8] Background color B value Unsigned; 8 bits */ + __IOM uint32_t G : 8; /*!< [23..16] Background color G value Unsigned; 8 bits */ + uint32_t : 8; + } BASE_b; + }; + + union + { + __IOM uint32_t CLUTINT; /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register */ + + struct + { + __IOM uint32_t LINE : 11; /*!< [10..0] Number of detection lines */ + uint32_t : 5; + __IOM uint32_t SEL : 1; /*!< [16..16] CLUT table control */ + uint32_t : 15; + } CLUTINT_b; + }; + + union + { + __IM uint32_t MON; /*!< (@ 0x00000054) Graphics Status Monitor Register */ + + struct + { + __IM uint32_t ARCST : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area */ + uint32_t : 15; + __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow */ + uint32_t : 15; + } MON_b; + }; + __IM uint32_t RESERVED2[42]; +} R_GLCDC_GR_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_GLCDC_GAM [GAM] (Gamma Settings) + */ +typedef struct +{ + union + { + __IOM uint32_t LATCH; /*!< (@ 0x00000000) Gamma Register Update Control Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of gamma correction x module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } LATCH_b; + }; + + union + { + __IOM uint32_t GAM_SW; /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register */ + + struct + { + __IOM uint32_t GAMON : 1; /*!< [0..0] Gamma correction on/off control */ + uint32_t : 31; + } GAM_SW_b; + }; + + union + { + __IOM uint32_t LUT[8]; /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + __IOM uint32_t _LOW : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point. */ + uint32_t : 5; + } LUT_b[8]; + }; + + union + { + __IOM uint32_t AREA[5]; /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register */ + + struct + { + __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _MID : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer */ + __IOM uint32_t _LOW : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer */ + uint32_t : 2; + } AREA_b[5]; + }; + __IM uint32_t RESERVED; +} R_GLCDC_GAM_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_GLCDC_OUT [OUT] (Output Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t VLATCH; /*!< (@ 0x00000000) Output Control Block Register Update Control + * Register */ + + struct + { + __IOM uint32_t VEN : 1; /*!< [0..0] Control of output control module register value reflection + * to internal operations. The register values to be reflected + * to the internal operations at the assertion of the vertical + * synchronization signal (VS). */ + uint32_t : 31; + } VLATCH_b; + }; + + union + { + __IOM uint32_t SET; /*!< (@ 0x00000004) Output Control Block Output Interface Register */ + + struct + { + __IOM uint32_t PHASE : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK) */ + uint32_t : 2; + __IOM uint32_t DIRSEL : 1; /*!< [4..4] Invalid data position control in serial RGB format */ + uint32_t : 3; + __IOM uint32_t FRQSEL : 2; /*!< [9..8] Clock frequency division control */ + uint32_t : 2; + __IOM uint32_t FORMAT : 2; /*!< [13..12] Output format select */ + uint32_t : 10; + __IOM uint32_t SWAPON : 1; /*!< [24..24] Pixel order control */ + uint32_t : 3; + __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control */ + uint32_t : 3; + } SET_b; + }; + + union + { + __IOM uint32_t BRIGHT1; /*!< (@ 0x00000008) Output Control Block Brightness Correction Register + * 1 */ + + struct + { + __IOM uint32_t BRTG : 10; /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 22; + } BRIGHT1_b; + }; + + union + { + __IOM uint32_t BRIGHT2; /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register + * 2 */ + + struct + { + __IOM uint32_t BRTR : 10; /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits; + +512 with offset; integer */ + uint32_t : 6; + __IOM uint32_t BRTB : 10; /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10 + * bits; +512 with offset; integer */ + uint32_t : 6; + } BRIGHT2_b; + }; + + union + { + __IOM uint32_t CONTRAST; /*!< (@ 0x00000010) Output Control Block Contrast Correction Register */ + + struct + { + __IOM uint32_t CONTR : 8; /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTB : 8; /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits + * fixed point */ + __IOM uint32_t CONTG : 8; /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8 + * bits fixed point. */ + uint32_t : 8; + } CONTRAST_b; + }; + + union + { + __IOM uint32_t PDTHA; /*!< (@ 0x00000014) Output Control Block Panel Dither Correction + * Register */ + + struct + { + __IOM uint32_t PD : 2; /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PC : 2; /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PB : 2; /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit + * integer */ + uint32_t : 2; + __IOM uint32_t PA : 2; /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned + * 2-bit integer */ + uint32_t : 2; + __IOM uint32_t FORM : 2; /*!< [17..16] Output format select */ + uint32_t : 2; + __IOM uint32_t SEL : 2; /*!< [21..20] Operation mode */ + uint32_t : 10; + } PDTHA_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CLKPHASE; /*!< (@ 0x00000024) Output Control Block Output Phase Control Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control */ + __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control */ + __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control */ + __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control */ + uint32_t : 1; + __IOM uint32_t LCDEDGE : 1; /*!< [8..8] LCD_DATA Output Phase Control */ + uint32_t : 3; + __IOM uint32_t FRONTGAM : 1; /*!< [12..12] Correction control */ + uint32_t : 19; + } CLKPHASE_b; + }; +} R_GLCDC_OUT_Type; /*!< Size = 40 (0x28) */ + +/** + * @brief R_GLCDC_TCON [TCON] (Timing Control Registers) + */ +typedef struct +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t TIM; /*!< (@ 0x00000004) TCON Reference Timing Setting Register */ + + struct + { + __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference + * timing Sets the offset from the assertion of the internal + * horizontal synchronization signal in terms of pixels. */ + uint32_t : 5; + __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing + * Sets the delay from the assertion of the internal horizontal + * synchronization signal in terms of pixels. */ + uint32_t : 5; + } TIM_b; + }; + + union + { + __IOM uint32_t STVA1; /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVA1_b; + }; + + union + { + __IOM uint32_t STVA2; /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVA2_b; + }; + + union + { + __IOM uint32_t STVB1; /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1 */ + + struct + { + __IOM uint32_t VW : 11; /*!< [10..0] STVx1 second change timing Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t VS : 11; /*!< [26..16] STVx1 first change timing */ + uint32_t : 5; + } STVB1_b; + }; + + union + { + __IOM uint32_t STVB2; /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for VSOUT (controlled by + * TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2 + * register) pin */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control */ + uint32_t : 27; + } STVB2_b; + }; + + union + { + __IOM uint32_t STHA1; /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHA1_b; + }; + + union + { + __IOM uint32_t STHA2; /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHA2_b; + }; + + union + { + __IOM uint32_t STHB1; /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1 */ + + struct + { + __IOM uint32_t HW : 11; /*!< [10..0] STHx1 second change timing. Sets the signal assertion + * width. */ + uint32_t : 5; + __IOM uint32_t HS : 11; /*!< [26..16] STHx1 first change timing */ + uint32_t : 5; + } STHB1_b; + }; + + union + { + __IOM uint32_t STHB2; /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2 */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Output signal select control for LCD_TCON2 (controlled + * by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2 + * register) pin. */ + uint32_t : 1; + __IOM uint32_t INV : 1; /*!< [4..4] STVx signal polarity inversion control. */ + uint32_t : 3; + __IOM uint32_t HSSEL : 1; /*!< [8..8] STHx signal generation reference timing control. */ + uint32_t : 23; + } STHB2_b; + }; + + union + { + __IOM uint32_t DE; /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register */ + + struct + { + __IOM uint32_t INV : 1; /*!< [0..0] DE signal polarity inversion control. */ + uint32_t : 31; + } DE_b; + }; +} R_GLCDC_TCON_Type; /*!< Size = 44 (0x2c) */ + +/** + * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DTCTEN; /*!< (@ 0x00000000) System control block State Detection Control + * Register */ + + struct + { + __IOM uint32_t VPOSDTC : 1; /*!< [0..0] Specified line detection control */ + __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control */ + __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control */ + uint32_t : 29; + } DTCTEN_b; + }; + + union + { + __IOM uint32_t INTEN; /*!< (@ 0x00000004) System control block Interrupt Request Enable + * Control Register */ + + struct + { + __IOM uint32_t VPOSINTEN : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control. */ + __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control. */ + __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control. */ + uint32_t : 29; + } INTEN_b; + }; + + union + { + __IOM uint32_t STCLR; /*!< (@ 0x00000008) System control block Status Clear Register */ + + struct + { + __IOM uint32_t VPOSCLR : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field */ + __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field */ + __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field */ + uint32_t : 29; + } STCLR_b; + }; + + union + { + __IM uint32_t STMON; /*!< (@ 0x0000000C) System control block Status Monitor Register */ + + struct + { + __IM uint32_t VPOS : 1; /*!< [0..0] Graphics 2 specified line detection flag */ + __IM uint32_t L1UNDF : 1; /*!< [1..1] Graphics 1 underflow detection flag */ + __IM uint32_t L2UNDF : 1; /*!< [2..2] Graphics 2 underflow detection flag */ + uint32_t : 29; + } STMON_b; + }; + + union + { + __IOM uint32_t PANEL_CLK; /*!< (@ 0x00000010) System control block Version and Panel Clock + * Control Register */ + + struct + { + __IOM uint32_t DCDR : 6; /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1 + * for details about setting value. Note: Settings that are + * not listed in table 2.7.1 are prohibited. */ + __IOM uint32_t CLKEN : 1; /*!< [6..6] Panel clock output enable control Note: Before changing + * the PIXSEL,CLKSEL or DCDR bit, this bit must be set to + * 0. */ + uint32_t : 1; + __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select */ + uint32_t : 3; + __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same + * value as OUT_SET.FRQSEL[1]. */ + uint32_t : 3; + __IM uint32_t VER : 16; /*!< [31..16] Version information Version information of the GLCDC */ + } PANEL_CLK_b; + }; +} R_GLCDC_SYSCNT_Type; /*!< Size = 20 (0x14) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x40081000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 2D Drawing Engine (R_DRW) + */ + +typedef struct /*!< (@ 0x400E4000) R_DRW Structure */ +{ + union + { + union + { + __OM uint32_t CONTROL; /*!< (@ 0x00000000) Geometry Control Register */ + + struct + { + __OM uint32_t LIM1ENABLE : 1; /*!< [0..0] Enable limiter 1 */ + __OM uint32_t LIM2ENABLE : 1; /*!< [1..1] Enable limiter 2 */ + __OM uint32_t LIM3ENABLE : 1; /*!< [2..2] Enable limiter 3 */ + __OM uint32_t LIM4ENABLE : 1; /*!< [3..3] Enable limiter 4 */ + __OM uint32_t LIM5ENABLE : 1; /*!< [4..4] Enable limiter 5 */ + __OM uint32_t LIM6ENABLE : 1; /*!< [5..5] Enable limiter 6 */ + __OM uint32_t QUAD1ENABLE : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2 */ + __OM uint32_t QUAD2ENABLE : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4 */ + __OM uint32_t QUAD3ENABLE : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6 */ + __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode */ + __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode */ + __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode */ + __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode */ + __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode */ + __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode */ + __OM uint32_t BAND1ENABLE : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t BAND2ENABLE : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND) */ + __OM uint32_t UNION12 : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A) */ + __OM uint32_t UNION34 : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B) */ + __OM uint32_t UNION56 : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D) */ + __OM uint32_t UNIONAB : 1; /*!< [20..20] Combine outputs A & B as union (output is called C) */ + __OM uint32_t UNIONCD : 1; /*!< [21..21] Combine outputs C & D as union (output is final) */ + __OM uint32_t SPANABORT : 1; /*!< [22..22] Shape is horizontally convex, only a single span per + * scanline */ + __OM uint32_t SPANSTORE : 1; /*!< [23..23] Nextline span start is always equal or left to current-line + * span start */ + uint32_t : 8; + } CONTROL_b; + }; + + union + { + __IM uint32_t STATUS; /*!< (@ 0x00000000) Status Control Register */ + + struct + { + __IM uint32_t BUSYENUM : 1; /*!< [0..0] Enumeration unit status */ + __IM uint32_t BUSYWRITE : 1; /*!< [1..1] Framebuffer writeback status */ + __IM uint32_t CACHEDIRTY : 1; /*!< [2..2] Framebuffer cache status */ + __IM uint32_t DLISTACTIVE : 1; /*!< [3..3] Display list reader status */ + __IM uint32_t ENUMIRQ : 1; /*!< [4..4] enumeration finished interrupt triggered */ + __IM uint32_t DLISTIRQ : 1; /*!< [5..5] display list finished interrupt triggered */ + __IM uint32_t BUSIRQ : 1; /*!< [6..6] bus error interrupt triggered */ + uint32_t : 1; + __IM uint32_t BUSERRMFB : 1; /*!< [8..8] framebuffer bus error interrupt triggered */ + __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered */ + __IM uint32_t BUSERRMDL : 1; /*!< [10..10] display list bus error interrupt triggered */ + uint32_t : 21; + } STATUS_b; + }; + }; + + union + { + union + { + __OM uint32_t CONTROL2; /*!< (@ 0x00000004) Surface Control Register */ + + struct + { + __OM uint32_t PATTERNENABLE : 1; /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and + * COLOR2 depending on PATTERN and pattern index) */ + __OM uint32_t TEXTUREENABLE : 1; /*!< [1..1] Pixel source is read from texture and used as an alpha + * to blend between COLOR1 and COLOR2 */ + __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default + * U limiter.Limiter 5 can be combined with limiter 6 to form + * a quadratic limiter which can be used to make quadratic + * pattern functions to draw radial patterns. */ + __OM uint32_t USEACB : 1; /*!< [3..3] Alpha blend mode */ + __OM uint32_t READFORMAT32 : 2; /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT + * above for description */ + __OM uint32_t BSFA : 1; /*!< [6..6] Blend source factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t BDFA : 1; /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel + * blending mode (USEACB = 1) */ + __OM uint32_t WRITEFORMAT2 : 1; /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above + * description. */ + __OM uint32_t BSF : 1; /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per + * default) */ + __OM uint32_t BDF : 1; /*!< [10..10] Blend destination factordst factor is alpha (factor + * is 1 per default) */ + __OM uint32_t BSI : 1; /*!< [11..11] Blend source factor is invertedsrc factor will be inverted + * (meaning 1-a or 1-1 depending on BSF) */ + __OM uint32_t BDI : 1; /*!< [12..12] Blend destination factor is inverteddst factor will + * be inverted (meaning 1-a or 1-1 depending on BDF) */ + __OM uint32_t BC2 : 1; /*!< [13..13] Blend color 2 instead of framebuffer pixel */ + __OM uint32_t TEXTURECLAMPX : 1; /*!< [14..14] Calculating U limiter outside use textureThe bit describes + * what happens if the U limiter (x direction in texture space) + * calculates a U value outside of the used texture */ + __OM uint32_t TEXTURECLAMPY : 1; /*!< [15..15] Calculating V limiter outside use textureThe bit describes + * what happens if the V limiter (y direction in texture space) + * calculates a V value outside of the used texture */ + __OM uint32_t TEXTUREFILTERX : 1; /*!< [16..16] Linear filtering on texture U axis */ + __OM uint32_t TEXTUREFILTERY : 1; /*!< [17..17] Linear filtering on texture V axis */ + __OM uint32_t READFORMAT10 : 2; /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000: + * 8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011: + * 16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44) + * 4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8), + * 8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4), + * 4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2), + * 2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1), + * 1 bit indexed color/luminance */ + __OM uint32_t WRITEFORMAT10 : 2; /*!< [21..20] Pixel format of the framebuffer */ + __OM uint32_t WRITEALPHA : 2; /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha + * source' for the framebuffer(USEACB = 0)Blend alpha in color + * 2 instead of framebuffer alpha((USEACB = 1))In not alpha + * channel blending mode (USEACB = 0):Set the 'alpha source' + * for the framebuffer.In alpha channel blending mode (USEACB + * = 1):Blend alpha in color 2 instead of framebuffer alpha00B: + * BC2A = 1: use alpha from framebuffer as destination (DST_A)else: + * BC2A = 0: use alpha in color 2 as destination (DST_A) */ + __OM uint32_t RLEENABLE : 1; /*!< [24..24] RLE enable */ + __OM uint32_t CLUTENABLE : 1; /*!< [25..25] CLUT enable */ + __OM uint32_t COLKEYENABLE : 1; /*!< [26..26] color keying enable */ + __OM uint32_t CLUTFORMAT : 1; /*!< [27..27] Format of the CLUT */ + __OM uint32_t BSIA : 1; /*!< [28..28] Blend source factor inverted in alpha channel (USEACB + * = 1) */ + __OM uint32_t BDIA : 1; /*!< [29..29] Blend destination factor inverted in alpha channel + * (USEACB = 1) */ + __OM uint32_t RLEPIXELWIDTH : 2; /*!< [31..30] Texel width for RLE unit */ + } CONTROL2_b; + }; + + union + { + __IM uint32_t HWREVISION; /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register */ + + struct + { + __IM uint32_t REV : 12; /*!< [11..0] Revision number */ + uint32_t : 5; + __IM uint32_t DLR : 1; /*!< [17..17] Display list reader feature */ + __IM uint32_t FBCACHE : 1; /*!< [18..18] Framebuffer cache feature */ + __IM uint32_t TXCACHE : 1; /*!< [19..19] Texture cache feature */ + __IM uint32_t PERFCOUNT : 1; /*!< [20..20] Two performance counter feature */ + __IM uint32_t TEXCLU : 1; /*!< [21..21] Texture CLUT with 16 or 256 entries feature */ + uint32_t : 1; + __IM uint32_t RLEUNIT : 1; /*!< [23..23] RLE unit feature */ + __IM uint32_t TEXCLUT256 : 1; /*!< [24..24] Texture CLUT feature */ + __IM uint32_t COLORKEY : 1; /*!< [25..25] Colorkey feature */ + uint32_t : 1; + __IM uint32_t ACBLEND : 1; /*!< [27..27] Alpha channel blending feature */ + uint32_t : 4; + } HWREVISION_b; + }; + }; + __IM uint32_t RESERVED[2]; + + union + { + __OM uint32_t L1START; /*!< (@ 0x00000010) Limiter 1 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L1START_b; + }; + + union + { + __OM uint32_t L2START; /*!< (@ 0x00000014) Limiter 2 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L2START_b; + }; + + union + { + __OM uint32_t L3START; /*!< (@ 0x00000018) Limiter 3 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L3START_b; + }; + + union + { + __OM uint32_t L4START; /*!< (@ 0x0000001C) Limiter 4 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L4START_b; + }; + + union + { + __OM uint32_t L5START; /*!< (@ 0x00000020) Limiter 5 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L5START_b; + }; + + union + { + __OM uint32_t L6START; /*!< (@ 0x00000024) Limiter 6 Start Value Register */ + + struct + { + __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6) */ + } L6START_b; + }; + + union + { + __OM uint32_t L1XADD; /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L1XADD_b; + }; + + union + { + __OM uint32_t L2XADD; /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L2XADD_b; + }; + + union + { + __OM uint32_t L3XADD; /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L3XADD_b; + }; + + union + { + __OM uint32_t L4XADD; /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L4XADD_b; + }; + + union + { + __OM uint32_t L5XADD; /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L5XADD_b; + }; + + union + { + __OM uint32_t L6XADD; /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register */ + + struct + { + __OM uint32_t LXADD : 32; /*!< [31..0] X-axis increment */ + } L6XADD_b; + }; + + union + { + __OM uint32_t L1YADD; /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L1YADD_b; + }; + + union + { + __OM uint32_t L2YADD; /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L2YADD_b; + }; + + union + { + __OM uint32_t L3YADD; /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L3YADD_b; + }; + + union + { + __OM uint32_t L4YADD; /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L4YADD_b; + }; + + union + { + __OM uint32_t L5YADD; /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L5YADD_b; + }; + + union + { + __OM uint32_t L6YADD; /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register */ + + struct + { + __OM uint32_t LYADD : 32; /*!< [31..0] Y-axis increment */ + } L6YADD_b; + }; + + union + { + __OM uint32_t L1BAND; /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L1BAND_b; + }; + + union + { + __OM uint32_t L2BAND; /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register */ + + struct + { + __OM uint32_t LBAND : 32; /*!< [31..0] Limiter m band width parameter */ + } L2BAND_b; + }; + __IM uint32_t RESERVED1; + + union + { + __OM uint32_t COLOR1; /*!< (@ 0x00000064) Base Color Register */ + + struct + { + __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1 */ + __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1 */ + __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1 */ + __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR1_b; + }; + + union + { + __OM uint32_t COLOR2; /*!< (@ 0x00000068) Secondary Color Register */ + + struct + { + __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2 */ + __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2 */ + __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2 */ + __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF: + * opaque) */ + } COLOR2_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __OM uint32_t PATTERN; /*!< (@ 0x00000074) Pattern Register */ + + struct + { + __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern */ + uint32_t : 24; + } PATTERN_b; + }; + + union + { + __OM uint32_t SIZE; /*!< (@ 0x00000078) Bounding Box Dimension Register */ + + struct + { + __OM uint32_t SIZEX : 16; /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to + * 1024 */ + __OM uint32_t SIZEY : 16; /*!< [31..16] Height of the bounding box in pixelsvalid range: 0 + * to 1024 */ + } SIZE_b; + }; + + union + { + __OM uint32_t PITCH; /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register */ + + struct + { + __OM uint32_t PITCH : 16; /*!< [15..0] pitch of the framebuffer. A negative width can be used + * to render bottom-up instead of top-down */ + __OM uint32_t SSD : 16; /*!< [31..16] Spanstore delay */ + } PITCH_b; + }; + + union + { + __OM uint32_t ORIGIN; /*!< (@ 0x00000080) Framebuffer Base Address Register */ + + struct + { + __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer */ + } ORIGIN_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __OM uint32_t LUSTART; /*!< (@ 0x00000090) U Limiter Start Value Register */ + + struct + { + __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value */ + } LUSTART_b; + }; + + union + { + __OM uint32_t LUXADD; /*!< (@ 0x00000094) U Limiter X-Axis Increment Register */ + + struct + { + __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment */ + } LUXADD_b; + }; + + union + { + __OM uint32_t LUYADD; /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register */ + + struct + { + __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment */ + } LUYADD_b; + }; + + union + { + __OM uint32_t LVSTARTI; /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register */ + + struct + { + __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part */ + } LVSTARTI_b; + }; + + union + { + __OM uint32_t LVSTARTF; /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register */ + + struct + { + __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part */ + uint32_t : 16; + } LVSTARTF_b; + }; + + union + { + __OM uint32_t LVXADDI; /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part */ + } LVXADDI_b; + }; + + union + { + __OM uint32_t LVYADDI; /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register */ + + struct + { + __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part */ + } LVYADDI_b; + }; + + union + { + __OM uint32_t LVYXADDF; /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register */ + + struct + { + __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part */ + __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part */ + } LVYXADDF_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t TEXPITCH; /*!< (@ 0x000000B4) Texels Per Texture Line Register */ + + struct + { + __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048 */ + } TEXPITCH_b; + }; + + union + { + __OM uint32_t TEXMASK; /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register */ + + struct + { + __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture + * wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width + * must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX + * = 1):all widths up to 2048 are allowed. */ + __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height + * - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY = + * 0): texture_height must be a power of 2In texture clamping + * mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024 + * are allowed. */ + } TEXMASK_b; + }; + + union + { + __OM uint32_t TEXORIGIN; /*!< (@ 0x000000BC) Texture Base Address Register */ + + struct + { + __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address */ + } TEXORIGIN_b; + }; + + union + { + __OM uint32_t IRQCTL; /*!< (@ 0x000000C0) Interrupt Control Register */ + + struct + { + __OM uint32_t ENUMIRQEN : 1; /*!< [0..0] ENUMIRQ interrupt mask enable */ + __OM uint32_t DLISTIRQEN : 1; /*!< [1..1] DLISTIRQ interrupt mask enable */ + __OM uint32_t ENUMIRQCLR : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ */ + __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ */ + __OM uint32_t BUSIRQEN : 1; /*!< [4..4] BUSIRQ interrupt mask enable */ + __OM uint32_t BUSIRQCLR : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ */ + uint32_t : 26; + } IRQCTL_b; + }; + + union + { + __OM uint32_t CACHECTL; /*!< (@ 0x000000C4) Cache Control Register */ + + struct + { + __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable */ + __OM uint32_t CFLUSHFX : 1; /*!< [1..1] Flush framebuffer cache */ + __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable */ + __OM uint32_t CFLUSHTX : 1; /*!< [3..3] Flush texture cache */ + uint32_t : 28; + } CACHECTL_b; + }; + + union + { + __OM uint32_t DLISTSTART; /*!< (@ 0x000000C8) Display List Start Address Register */ + + struct + { + __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address */ + } DLISTSTART_b; + }; + + union + { + __IOM uint32_t PERFCOUNT1; /*!< (@ 0x000000CC) Performance Counter 1 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT1_b; + }; + + union + { + __IOM uint32_t PERFCOUNT2; /*!< (@ 0x000000D0) Performance Counter 2 */ + + struct + { + __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT + * = 0000 0000H. */ + } PERFCOUNT2_b; + }; + + union + { + __OM uint32_t PERFTRIGGER; /*!< (@ 0x000000D4) Performance Counters Control Register */ + + struct + { + __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1 + * register. */ + __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2 + * register */ + } PERFTRIGGER_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t TEXCLADDR; /*!< (@ 0x000000DC) CLUT Start Address Register */ + + struct + { + __OM uint32_t CLADDR : 8; /*!< [7..0] Texture CLUT start address for indexed texture format */ + uint32_t : 24; + } TEXCLADDR_b; + }; + + union + { + __OM uint32_t TEXCLDATA; /*!< (@ 0x000000E0) CLUT Data Register */ + + struct + { + __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format */ + } TEXCLDATA_b; + }; + + union + { + __OM uint32_t TEXCLOFFSET; /*!< (@ 0x000000E4) CLUT Offset Register */ + + struct + { + __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0] + * is or'ed with the original index */ + uint32_t : 24; + } TEXCLOFFSET_b; + }; + + union + { + __OM uint32_t COLKEY; /*!< (@ 0x000000E8) Color Key Register */ + + struct + { + __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key */ + __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key */ + __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key */ + uint32_t : 8; + } COLKEY_b; + }; +} R_DRW_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40064100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40064000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller (R_ETHERC_EPTPC) + */ + +typedef struct /*!< (@ 0x40065800) R_ETHERC_EPTPC Structure */ +{ + union + { + __IOM uint32_t SYSR; /*!< (@ 0x00000000) SYNFP Status Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] offsetFromMaster Value Update Flag */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] Receive logMessageInterval Value Change Detection Flag */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] meanPathDelay Value Update Flag */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] Delay_Resp/Pdelay_Resp Reception Timeout Detection Flag */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] Receive logMessageInterval Value Out-of-Range Flag */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] Delay_Req Reception FIFO Overflow Detection Flag */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] Loop Reception Detection Flag */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] Control Information Abnormality Detection Flag */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] Response Stop Completion Detection Flag */ + __IOM uint32_t GENDN : 1; /*!< [17..17] Generation Stop Completion Detection Flag */ + uint32_t : 14; + } SYSR_b; + }; + + union + { + __IOM uint32_t SYIPR; /*!< (@ 0x00000004) SYNFP Status Notification Permission Register */ + + struct + { + __IOM uint32_t OFMUD : 1; /*!< [0..0] SYSR.OFMUD Status Notification Permission */ + __IOM uint32_t INTCHG : 1; /*!< [1..1] SYSR.INTCHG Status Notification Permission */ + __IOM uint32_t MPDUD : 1; /*!< [2..2] SYSR.MPDUD Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t DRPTO : 1; /*!< [4..4] SYSR.DRPTO Status Notification Permission */ + __IOM uint32_t INTDEV : 1; /*!< [5..5] SYSR.INTDEV Status Notification Permission */ + __IOM uint32_t DRQOVR : 1; /*!< [6..6] SYSR.DRQOVR Status Notification Permission */ + uint32_t : 5; + __IOM uint32_t RECLP : 1; /*!< [12..12] SYSR.RECLP Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t INFABT : 1; /*!< [14..14] SYSR.INFABT Status Notification Permission */ + uint32_t : 1; + __IOM uint32_t RESDN : 1; /*!< [16..16] SYSR.RESDN Status Notification Permission */ + __IOM uint32_t GENDN : 1; /*!< [17..17] SYSR.GENDN Status Notification Permission */ + uint32_t : 14; + } SYIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SYMACRU; /*!< (@ 0x00000010) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the local MAC address. */ + uint32_t : 8; + } SYMACRU_b; + }; + + union + { + __IOM uint32_t SYMACRL; /*!< (@ 0x00000014) SYNFP MAC Address Registers */ + + struct + { + __IOM uint32_t SYMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the local MAC address. */ + uint32_t : 8; + } SYMACRL_b; + }; + + union + { + __IOM uint32_t SYLLCCTLR; /*!< (@ 0x00000018) SYNFP LLC-CTL Value Register */ + + struct + { + __IOM uint32_t CTL : 8; /*!< [7..0] LLC-CTL FieldThese bits specify the value used for the + * control field in the LLC sublayer when generating IEEE802.3 + * frames. */ + uint32_t : 24; + } SYLLCCTLR_b; + }; + + union + { + __IOM uint32_t SYIPADDRR; /*!< (@ 0x0000001C) SYNFP Local IP Address Register */ + + struct + { + __IOM uint32_t SYIPADDRR : 32; /*!< [31..0] These bits hold the setting for the local IP address. */ + } SYIPADDRR_b; + }; + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t SYSPVRR; /*!< (@ 0x00000040) SYNFP Specification Version Setting Register */ + + struct + { + __IOM uint32_t VER : 4; /*!< [3..0] versionPTP Field ValueThese bits are used to set the + * versionPTP field value of the PTP v2 header.When a message + * is received, this value is compared with the versionPTP + * field of the received frame.In generating messages, the + * value is used for the versionPTP field of the frame for + * transmission.Set these bits to 0010b (PTP v2). */ + __IOM uint32_t TRSP : 4; /*!< [7..4] transportSpecific Field ValueThese bits are used to set + * the transportSpecific field value of the PTP v2 header.When + * a message is received, this value is compared with the + * transportSpecific field of the received frame.In generating + * messages, the value is used for the transportSpecific field + * of the frame for transmission.Set these bits to 0000b (IEEE + * 1588). */ + uint32_t : 24; + } SYSPVRR_b; + }; + + union + { + __IOM uint32_t SYDOMR; /*!< (@ 0x00000044) SYNFP Domain Number Setting Register */ + + struct + { + __IOM uint32_t DNUM : 8; /*!< [7..0] domainNumber Field Value SettingThese bits are used to + * set the domainNumber field value of the PTP v2 header.When + * a message is received, this value is compared with the + * domainNumber field of the received frame as a condition + * for PTP reception processing.In generating messages, the + * value is used for the domainNumber field of the frame for + * transmission. */ + uint32_t : 24; + } SYDOMR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ANFR; /*!< (@ 0x00000050) Announce Message Flag Field Setting Register */ + + struct + { + __IOM uint32_t FLAG0 : 1; /*!< [0..0] leap61This bit is used to set the logical value of the + * leap61 member of timePropertiesDS. */ + __IOM uint32_t FLAG1 : 1; /*!< [1..1] leap59This bit is used to set the logical value of the + * leap59 member of timePropertiesDS. */ + __IOM uint32_t FLAG2 : 1; /*!< [2..2] currentUtcOffsetValidThis bit is used to set the logical + * value of the currentUtcOffsetValid member of timePropertiesDS. */ + __IOM uint32_t FLAG3 : 1; /*!< [3..3] ptpTimescaleThis bit is used to set the logical value + * of the ptpTimescale member of timePropertiesDS. */ + __IOM uint32_t FLAG4 : 1; /*!< [4..4] timeTraceableThis bit is used to set the logical value + * of the timeTraceable member of timePropertiesDS. */ + __IOM uint32_t FLAG5 : 1; /*!< [5..5] frequencyTraceableThis bit is used to set the logical + * value of the frequencyTraceable member of timePropertiesDS. */ + uint32_t : 2; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + uint32_t : 1; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } ANFR_b; + }; + + union + { + __IOM uint32_t SYNFR; /*!< (@ 0x00000054) Sync Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] twoStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } SYNFR_b; + }; + + union + { + __IOM uint32_t DYRQFR; /*!< (@ 0x00000058) Delay_Req Message Flag Field Setting Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRQFR_b; + }; + + union + { + __IOM uint32_t DYRPFR; /*!< (@ 0x0000005C) Delay_Resp Message Flag Field Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FLAG8 : 1; /*!< [8..8] alternateMasterFlag */ + __IOM uint32_t FLAG9 : 1; /*!< [9..9] woStepFlag */ + __IOM uint32_t FLAG10 : 1; /*!< [10..10] unicastFlag */ + uint32_t : 2; + __IOM uint32_t FLAG13 : 1; /*!< [13..13] PTP profile Specific 1 */ + __IOM uint32_t FLAG14 : 1; /*!< [14..14] PTP profile Specific 2 */ + uint32_t : 17; + } DYRPFR_b; + }; + + union + { + __IOM uint32_t SYCIDRU; /*!< (@ 0x00000060) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of your port. */ + } SYCIDRU_b; + }; + + union + { + __IOM uint32_t SYCIDRL; /*!< (@ 0x00000064) SYNFP Local Clock ID Registers */ + + struct + { + __IOM uint32_t SYCIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of your port. */ + } SYCIDRL_b; + }; + + union + { + __IOM uint32_t SYPNUMR; /*!< (@ 0x00000068) SYNFP Local Port Number Register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Local Port Number SettingThese bits hold the setting + * for the port number of the local port. */ + uint32_t : 16; + } SYPNUMR_b; + }; + __IM uint32_t RESERVED3[5]; + + union + { + __OM uint32_t SYRVLDR; /*!< (@ 0x00000080) SYNFP Register Value Load Directive Register */ + + struct + { + __OM uint32_t BMUP : 1; /*!< [0..0] BMC Update */ + __OM uint32_t STUP : 1; /*!< [1..1] State Update */ + __OM uint32_t ANUP : 1; /*!< [2..2] Announce Message Generation Information Update */ + uint32_t : 29; + } SYRVLDR_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SYRFL1R; /*!< (@ 0x00000090) SYNFP Reception Filter Register 1 */ + + struct + { + __IOM uint32_t ANCE0 : 1; /*!< [0..0] Announce Message Processing */ + __IOM uint32_t ANCE1 : 1; /*!< [1..1] Announce Message Processing */ + uint32_t : 2; + __IOM uint32_t SYNC0 : 1; /*!< [4..4] Sync Message Processing */ + __IOM uint32_t SYNC1 : 1; /*!< [5..5] Sync Message Processing */ + __IOM uint32_t SYNC2 : 1; /*!< [6..6] Sync Message Processing */ + uint32_t : 1; + __IOM uint32_t FUP0 : 1; /*!< [8..8] Follow_Up Message Processing */ + __IOM uint32_t FUP1 : 1; /*!< [9..9] Follow_Up Message Processing */ + __IOM uint32_t FUP2 : 1; /*!< [10..10] Follow_Up Message Processing */ + uint32_t : 1; + __IOM uint32_t DRQ0 : 1; /*!< [12..12] Delay_Req Message Processing */ + __IOM uint32_t DRQ1 : 1; /*!< [13..13] Delay_Req Message Processing */ + __IOM uint32_t DRQ2 : 1; /*!< [14..14] Delay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t DRP0 : 1; /*!< [16..16] Delay_Resp Message Processing */ + __IOM uint32_t DRP1 : 1; /*!< [17..17] Delay_Resp Message Processing */ + __IOM uint32_t DRP2 : 1; /*!< [18..18] Delay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRQ0 : 1; /*!< [20..20] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ1 : 1; /*!< [21..21] Pdelay_Req Message Processing */ + __IOM uint32_t PDRQ2 : 1; /*!< [22..22] Pdelay_Req Message Processing */ + uint32_t : 1; + __IOM uint32_t PDRP0 : 1; /*!< [24..24] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP1 : 1; /*!< [25..25] Pdelay_Resp Message Processing */ + __IOM uint32_t PDRP2 : 1; /*!< [26..26] Pdelay_Resp Message Processing */ + uint32_t : 1; + __IOM uint32_t PDFUP0 : 1; /*!< [28..28] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP1 : 1; /*!< [29..29] Pdelay_Resp_Follow_Up Message Processing */ + __IOM uint32_t PDFUP2 : 1; /*!< [30..30] Pdelay_Resp_Follow_Up Message Processing */ + uint32_t : 1; + } SYRFL1R_b; + }; + + union + { + __IOM uint32_t SYRFL2R; /*!< (@ 0x00000094) SYNFP Reception Filter Register 2 */ + + struct + { + __IOM uint32_t MAN0 : 1; /*!< [0..0] Management Message Processing Setting */ + __IOM uint32_t MAN1 : 1; /*!< [1..1] Management Message Processing Setting */ + uint32_t : 2; + __IOM uint32_t SIG0 : 1; /*!< [4..4] Signaling Message Processing Setting */ + __IOM uint32_t SIG1 : 1; /*!< [5..5] Signaling Message Processing Setting */ + uint32_t : 22; + __IOM uint32_t ILL0 : 1; /*!< [28..28] Illegal Message Processing Setting */ + __IOM uint32_t ILL1 : 1; /*!< [29..29] Illegal Message Processing Setting */ + uint32_t : 2; + } SYRFL2R_b; + }; + + union + { + __IOM uint32_t SYTRENR; /*!< (@ 0x00000098) SYNFP Transmission Enable Register */ + + struct + { + __IOM uint32_t ANCE : 1; /*!< [0..0] Announce Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t SYNC : 1; /*!< [4..4] Sync Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t DRQ : 1; /*!< [8..8] Delay_Req Message Transmission Enable */ + uint32_t : 3; + __IOM uint32_t PDRQ : 1; /*!< [12..12] Pdelay_Req Message Transmission Enable */ + uint32_t : 19; + } SYTRENR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t MTCIDU; /*!< (@ 0x000000A0) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the clock-ID of the master clock. */ + } MTCIDU_b; + }; + + union + { + __IOM uint32_t MTCIDL; /*!< (@ 0x000000A4) Master Clock ID Registers */ + + struct + { + __IOM uint32_t MTCIDL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the clock-ID of the master clock. */ + } MTCIDL_b; + }; + + union + { + __IOM uint32_t MTPID; /*!< (@ 0x000000A8) Master clock port number register */ + + struct + { + __IOM uint32_t PNUM : 16; /*!< [15..0] Master Clock Port Number SettingThese bits hold the + * setting for the port number of the master clock. */ + uint32_t : 16; + } MTPID_b; + }; + __IM uint32_t RESERVED6[5]; + + union + { + __IOM uint32_t SYTLIR; /*!< (@ 0x000000C0) SYNFP Transmission Interval Setting Register */ + + struct + { + __IOM uint32_t ANCE : 8; /*!< [7..0] Announce Message Transmission Interval SettingThese bits + * set the interval for the transmission of Announce messages. */ + __IOM uint32_t SYNC : 8; /*!< [15..8] Sync Message Transmission Interval SettingThese bits + * set the interval for the transmission of Sync messages. + * The setting is also placed in the logMessageInterval field + * of transmitted Sync messages. */ + __IOM uint32_t DREQ : 8; /*!< [23..16] Delay_Req Transmission Interval Average Value/ Pdelay_Req + * Transmission Interval SettingThe bits set the average interval + * for the transmission of Delay_Req messages and the interval + * for the transmission of Pdelay_Req messages.The setting + * is also placed in the logMessageInterval field of Delay_Resp + * messages. */ + uint32_t : 8; + } SYTLIR_b; + }; + + union + { + __IM uint32_t SYRLIR; /*!< (@ 0x000000C4) SYNFP Received logMessageInterval Value Indication + * Register */ + + struct + { + __IM uint32_t ANCE : 8; /*!< [7..0] Announce Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Announce message. */ + __IM uint32_t SYNC : 8; /*!< [15..8] Sync Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Sync message. */ + __IM uint32_t DRESP : 8; /*!< [23..16] Delay_Resp Message logMessageInterval Field IndicationThese + * bits indicate the logMessageInterval field value of a received + * Delay_Resp message. */ + uint32_t : 8; + } SYRLIR_b; + }; + + union + { + __IM uint32_t OFMRU; /*!< (@ 0x000000C8) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated offsetFromMaster value. */ + } OFMRU_b; + }; + + union + { + __IM uint32_t OFMRL; /*!< (@ 0x000000CC) offsetFromMaster Value Registers */ + + struct + { + __IM uint32_t OFMRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * offsetFromMaster value. */ + } OFMRL_b; + }; + + union + { + __IM uint32_t MPDRU; /*!< (@ 0x000000D0) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRU : 32; /*!< [31..0] These bits indicate the higher-order 32 bits of the + * calculated meanPathDelay value. */ + } MPDRU_b; + }; + + union + { + __IM uint32_t MPDRL; /*!< (@ 0x000000D4) meanPathDelay Value Registers */ + + struct + { + __IM uint32_t MPDRL : 32; /*!< [31..0] These bits indicate the lower-order 32 bits of the calculated + * meanPathDelay value. */ + } MPDRL_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint32_t GMPR; /*!< (@ 0x000000E0) grandmasterPriority Field Setting Register */ + + struct + { + __IOM uint32_t GMPR2 : 8; /*!< [7..0] grandmasterPriority2 Field Value SettingThese bits are + * used to set the value of the grandmasterPriority2 fields + * of Announce messages. */ + uint32_t : 8; + __IOM uint32_t GMPR1 : 8; /*!< [23..16] grandmasterPriority1 Field Value SettingThese bits + * are used to set the value of the grandmasterPriority1 fields + * of Announce messages. */ + uint32_t : 8; + } GMPR_b; + }; + + union + { + __IOM uint32_t GMCQR; /*!< (@ 0x000000E4) grandmasterClockQuality Field Setting Register */ + + struct + { + __IOM uint32_t GMCQR : 32; /*!< [31..0] These bits are used to set the value of the grandmasterClockQuality + * fields of Announce messages. The correspondence between + * bits and the grandmasterClockQuality fields is as listed + * below.b31 to b24: clockClassb23 to b16: clockAccuracyb15 + * to b0: offsetScaledLogVariance */ + } GMCQR_b; + }; + + union + { + __IOM uint32_t GMIDRU; /*!< (@ 0x000000E8) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the value of the grandmasterIdentity fields of + * Announce messages. */ + } GMIDRU_b; + }; + + union + { + __IOM uint32_t GMIDRL; /*!< (@ 0x000000EC) grandmasterIdentity Field Setting Registers */ + + struct + { + __IOM uint32_t GMIDRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the value of the grandmasterIdentity fields of Announce + * messages. */ + } GMIDRL_b; + }; + + union + { + __IOM uint32_t CUOTSR; /*!< (@ 0x000000F0) currentUtcOffset/timeSource Field Setting Register */ + + struct + { + __IOM uint32_t TSRC : 8; /*!< [7..0] timeSource Field SettingThese bits set the value of the + * timeSource fields of Announce messages. */ + uint32_t : 8; + __IOM uint32_t CUTO : 16; /*!< [31..16] currentUtcOffset Field SettingThese bits set the value + * of the currentUtcOffset fields of Announce messages. */ + } CUOTSR_b; + }; + + union + { + __IOM uint32_t SRR; /*!< (@ 0x000000F4) stepsRemoved Field Setting Register */ + + struct + { + __IOM uint32_t SRMV : 16; /*!< [15..0] stepsRemoved Field Value SettingThese bits set the value + * of the stepsRemoved fields of Announce messages. */ + uint32_t : 16; + } SRR_b; + }; + __IM uint32_t RESERVED8[2]; + + union + { + __IOM uint32_t PPMACRU; /*!< (@ 0x00000100) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRU_b; + }; + + union + { + __IOM uint32_t PPMACRL; /*!< (@ 0x00000104) PTP-primary Message Destination MAC Address Setting + * Registers */ + + struct + { + __IOM uint32_t PPMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-primary messages. */ + uint32_t : 8; + } PPMACRL_b; + }; + + union + { + __IOM uint32_t PDMACRU; /*!< (@ 0x00000108) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRU : 24; /*!< [23..0] These bits hold the setting for the higher-order 24 + * bits of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRU_b; + }; + + union + { + __IOM uint32_t PDMACRL; /*!< (@ 0x0000010C) PTP-pdelay Message MAC Address Setting Registers */ + + struct + { + __IOM uint32_t PDMACRL : 24; /*!< [23..0] These bits hold the setting for the lower-order 24 bits + * of the destination MAC address for PTP-pdelay messages. */ + uint32_t : 8; + } PDMACRL_b; + }; + + union + { + __IOM uint32_t PETYPER; /*!< (@ 0x00000110) PTP Message EtherType Setting Register */ + + struct + { + __IOM uint32_t TYPE : 16; /*!< [15..0] PTP Message EtherType Value SettingThese bits hold the + * setting for the EtherType field value for frames in the + * Ethernet II format. */ + uint32_t : 16; + } PETYPER_b; + }; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint32_t PPIPR; /*!< (@ 0x00000120) PTP-primary Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PPIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPprimary messages. */ + } PPIPR_b; + }; + + union + { + __IOM uint32_t PDIPR; /*!< (@ 0x00000124) PTP-pdelay Message Destination IP Address Setting + * Register */ + + struct + { + __IOM uint32_t PDIPR : 32; /*!< [31..0] These bits hold the setting for the destination IP address + * for PTPpdelay messages. */ + } PDIPR_b; + }; + + union + { + __IOM uint32_t PETOSR; /*!< (@ 0x00000128) PTP Event Message TOS Setting Register */ + + struct + { + __IOM uint32_t EVTO : 8; /*!< [7..0] PTP Event Message TOS Field Value SettingThese bits hold + * the setting for the value of the TOS field within the IPv4 + * headers of PTP event messages. */ + uint32_t : 24; + } PETOSR_b; + }; + + union + { + __IOM uint32_t PGTOSR; /*!< (@ 0x0000012C) PTP general Message TOS Setting Register */ + + struct + { + __IOM uint32_t GETO : 8; /*!< [7..0] PTP general Message TOS Field Value SettingThese bits + * hold the setting for the value of the TOS field within + * the IPv4 headers of PTP general messages. */ + uint32_t : 24; + } PGTOSR_b; + }; + + union + { + __IOM uint32_t PPTTLR; /*!< (@ 0x00000130) PTP-primary Message TTL Setting Register */ + + struct + { + __IOM uint32_t PRTL : 8; /*!< [7..0] PTP-primary Message TTL Field Value SettingThese bits + * hold the setting for the value of the TTL field within + * the IPv4 headers of PTP-primary messages. */ + uint32_t : 24; + } PPTTLR_b; + }; + + union + { + __IOM uint32_t PDTTLR; /*!< (@ 0x00000134) PTP-pdelay Message TTL Setting Register */ + + struct + { + __IOM uint32_t PDTL : 8; /*!< [7..0] PTP-pdelay Message TTL Field ValueThese bits hold the + * setting for the value of the TTL field within the IPv4 + * headers of PTP-pdelay messages. */ + uint32_t : 24; + } PDTTLR_b; + }; + + union + { + __IOM uint32_t PEUDPR; /*!< (@ 0x00000138) PTP Event Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t EVUPT : 16; /*!< [15..0] PTP Event Message Destination Port Number SettingThese + * bits hold the setting for the value of the destination + * port number field within the UDP headers of PTP event messages. */ + uint32_t : 16; + } PEUDPR_b; + }; + + union + { + __IOM uint32_t PGUDPR; /*!< (@ 0x0000013C) PTP general Message UDP Destination Port Number + * Setting Register */ + + struct + { + __IOM uint32_t GEUPT : 16; /*!< [15..0] PTP general Message Destination Port NumberThese bits + * hold the setting for the value of the destination port + * number field within the UDP headers of PTP general messages. */ + uint32_t : 16; + } PGUDPR_b; + }; + + union + { + __IOM uint32_t FFLTR; /*!< (@ 0x00000140) Frame Reception Filter Setting Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Receive MAC Address SelectNOTE: The setting of these + * bits is only effective when EXTPRM=0, ENB=1and RPT=1. */ + __IOM uint32_t PRT : 1; /*!< [1..1] Frame Reception EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0 and ENB=1. */ + __IOM uint32_t ENB : 1; /*!< [2..2] Reception Filter EnableNOTE: The setting of these bits + * is only effective when EXTPRM=0. */ + uint32_t : 13; + __IOM uint32_t EXTPRM : 1; /*!< [16..16] Extended Promiscuous ModeSetting */ + uint32_t : 15; + } FFLTR_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t FMAC0RU; /*!< (@ 0x00000160) Frame Reception Filter MAC Address 0 Setting + * Register Upper */ + + struct + { + __IOM uint32_t FMAC0RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC0RU_b; + }; + + union + { + __IOM uint32_t FMAC0RL; /*!< (@ 0x00000164) Frame Reception Filter MAC Address 0 Setting + * Register Lower */ + + struct + { + __IOM uint32_t FMAC0RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC0RL_b; + }; + + union + { + __IOM uint32_t FMAC1RU; /*!< (@ 0x00000168) Frame Reception Filter MAC Address 1 Setting + * Register Upper */ + + struct + { + __IOM uint32_t FMAC1RU : 24; /*!< [23..0] These bits specify the upper-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC1RU_b; + }; + + union + { + __IOM uint32_t FMAC1RL; /*!< (@ 0x0000016C) Frame Reception Filter MAC Address 1 Setting + * Register Lower */ + + struct + { + __IOM uint32_t FMAC1RL : 24; /*!< [23..0] These bits specify the lower-order 24 bits of the destination + * MAC address for received multicast frames. */ + uint32_t : 8; + } FMAC1RL_b; + }; + __IM uint32_t RESERVED11[20]; + + union + { + __IOM uint32_t DASYMRU; /*!< (@ 0x000001C0) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the asymmetric delay value. */ + uint32_t : 16; + } DASYMRU_b; + }; + + union + { + __IOM uint32_t DASYMRL; /*!< (@ 0x000001C4) Asymmetric Delay Setting Registers */ + + struct + { + __IOM uint32_t DASYMRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the asymmetric delay value. */ + } DASYMRL_b; + }; + + union + { + __IOM uint32_t TSLATR; /*!< (@ 0x000001C8) Timestamp Latency Setting Register */ + + struct + { + __IOM uint32_t EGP : 16; /*!< [15..0] Input Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the input + * ports. */ + __IOM uint32_t INGP : 16; /*!< [31..16] Output Port Timestamp Latency SettingThese bits hold + * the setting for the time stamp latency (ns) for the output + * ports. */ + } TSLATR_b; + }; + + union + { + __IOM uint32_t SYCONFR; /*!< (@ 0x000001CC) SYNFP Operation Setting Register */ + + struct + { + __IOM uint32_t TCYC : 8; /*!< [7..0] PTP Message Transmission Interval SettingThese bits are + * used to set the time from the completion of one transmission + * to the start of the next in cycles of the transmission + * clock. A value n in these bits means that a transmission + * interval of n cycles will be secured.No interval is secured + * if the setting is 00h.We recommend the setting 28h (40 + * cycles). */ + uint32_t : 4; + __IOM uint32_t SBDIS : 1; /*!< [12..12] Sync Message Transmission Bandwidth Securing Disable */ + uint32_t : 3; + __IOM uint32_t FILDIS : 1; /*!< [16..16] Receive Message domainNumber Filter Disable */ + uint32_t : 3; + __IOM uint32_t TCMOD : 1; /*!< [20..20] TC Mode Setting */ + uint32_t : 11; + } SYCONFR_b; + }; + + union + { + __IOM uint32_t SYFORMR; /*!< (@ 0x000001D0) SYNFP Frame Format Setting Register */ + + struct + { + __IOM uint32_t FORM0 : 1; /*!< [0..0] Ethernet/UDP Encapsulation */ + __IOM uint32_t FORM1 : 1; /*!< [1..1] Ethernet Frame Format Setting */ + uint32_t : 30; + } SYFORMR_b; + }; + + union + { + __IOM uint32_t RSTOUTR; /*!< (@ 0x000001D4) Response Message Reception Timeout Register */ + + struct + { + __IOM uint32_t RSTOUTR : 32; /*!< [31..0] Response Message Reception Timeout Time SettingA response + * message not being received within n x 1024 (ns), where + * n is the setting, is judged to represent a timeout. */ + } RSTOUTR_b; + }; +} R_ETHERC_EPTPC_Type; /*!< Size = 472 (0x1d8) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Configuration (R_ETHERC_EPTPC_CFG) + */ + +typedef struct /*!< (@ 0x40064500) R_ETHERC_EPTPC_CFG Structure */ +{ + union + { + __IOM uint32_t PTRSTR; /*!< (@ 0x00000000) EPTPC Reset Register */ + + struct + { + __IOM uint32_t RESET : 1; /*!< [0..0] EPTPC Software Reset */ + uint32_t : 31; + } PTRSTR_b; + }; + + union + { + __IOM uint32_t STCSELR; /*!< (@ 0x00000004) STCA Clock Select Register */ + + struct + { + __IOM uint32_t SCLKDIV : 3; /*!< [2..0] PCLKA Clock Frequency Division */ + uint32_t : 5; + __IOM uint32_t SCLKSEL : 3; /*!< [10..8] STCA Clock Select */ + uint32_t : 21; + } STCSELR_b; + }; + + union + { + __IOM uint32_t BYPASS; /*!< (@ 0x00000008) Bypass 1588 module Register */ + + struct + { + __IOM uint32_t BYPASS0 : 1; /*!< [0..0] Bypass 1588 module for Ether 0ch */ + uint32_t : 15; + __IOM uint32_t BYPASS1 : 1; /*!< [16..16] Bypass 1588 module for Ether 1ch */ + uint32_t : 15; + } BYPASS_b; + }; +} R_ETHERC_EPTPC_CFG_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet PTP Controller Common (R_ETHERC_EPTPC_COMMON) + */ + +typedef struct /*!< (@ 0x40065000) R_ETHERC_EPTPC_COMMON Structure */ +{ + union + { + __IOM uint32_t MIESR; /*!< (@ 0x00000000) MINT Interrupt Source Status Register */ + + struct + { + __IM uint32_t ST : 1; /*!< [0..0] STCA Status Flag */ + __IM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Flag */ + __IM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Flag */ + __IM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Flag */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Flag */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Flag */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Flag */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Flag */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Flag */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Flag */ + uint32_t : 10; + } MIESR_b; + }; + + union + { + __IOM uint32_t MIEIPR; /*!< (@ 0x00000004) MINT Interrupt Request Permission Register */ + + struct + { + __IOM uint32_t ST : 1; /*!< [0..0] STCA Status Interrupt Request Permission */ + __IOM uint32_t SY0 : 1; /*!< [1..1] SYNFP0 Status Interrupt Request Permission */ + __IOM uint32_t SY1 : 1; /*!< [2..2] SYNFP1 Status Interrupt Request Permission */ + __IOM uint32_t PRC : 1; /*!< [3..3] PRC-TC Status Interrupt Request Permission */ + uint32_t : 12; + __IOM uint32_t CYC0 : 1; /*!< [16..16] Pulse Output Timer 0 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC1 : 1; /*!< [17..17] Pulse Output Timer 1 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC2 : 1; /*!< [18..18] Pulse Output Timer 2 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC3 : 1; /*!< [19..19] Pulse Output Timer 3 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC4 : 1; /*!< [20..20] Pulse Output Timer 4 Rising Edge Detection Interrupt + * Request Permission */ + __IOM uint32_t CYC5 : 1; /*!< [21..21] Pulse Output Timer 5 Rising Edge Detection Interrupt + * Request Permission */ + uint32_t : 10; + } MIEIPR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t ELIPPR; /*!< (@ 0x00000010) ELC Output/ETHER_IPLS Interrupt Request Permission + * Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] Pulse Output Timer 0 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] Pulse Output Timer 1 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] Pulse Output Timer 2 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] Pulse Output Timer 3 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] Pulse Output Timer 4 Rising Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] Pulse Output Timer 5 Rising Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] Pulse Output Timer 0 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] Pulse Output Timer 1 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] Pulse Output Timer 2 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] Pulse Output Timer 3 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] Pulse Output Timer 4 Falling Edge Detection Event Output + * Enable */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] Pulse Output Timer 5 Falling Edge Detection Event Output + * Enable */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] Pulse Output Timer Rising Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] Pulse Output Timer Falling Edge Detection IPLS Interrupt + * Request Permission */ + uint32_t : 7; + } ELIPPR_b; + }; + + union + { + __IOM uint32_t ELIPACR; /*!< (@ 0x00000014) ELC Output/IPLS Interrupt Permission Automatic + * Clearing Register */ + + struct + { + __IOM uint32_t CYCP0 : 1; /*!< [0..0] ELIPPR.CYCP0 Bit Automatic Clearing */ + __IOM uint32_t CYCP1 : 1; /*!< [1..1] ELIPPR.CYCP1 Bit Automatic Clearing */ + __IOM uint32_t CYCP2 : 1; /*!< [2..2] ELIPPR.CYCP2 Bit Automatic Clearing */ + __IOM uint32_t CYCP3 : 1; /*!< [3..3] ELIPPR.CYCP3 Bit Automatic Clearing */ + __IOM uint32_t CYCP4 : 1; /*!< [4..4] ELIPPR.CYCP4 Bit Automatic Clearing */ + __IOM uint32_t CYCP5 : 1; /*!< [5..5] ELIPPR.CYCP5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t CYCN0 : 1; /*!< [8..8] ELIPPR.CYCN0 Bit Automatic Clearing */ + __IOM uint32_t CYCN1 : 1; /*!< [9..9] ELIPPR.CYCN1 Bit Automatic Clearing */ + __IOM uint32_t CYCN2 : 1; /*!< [10..10] ELIPPR.CYCN2 Bit Automatic Clearing */ + __IOM uint32_t CYCN3 : 1; /*!< [11..11] ELIPPR.CYCN3 Bit Automatic Clearing */ + __IOM uint32_t CYCN4 : 1; /*!< [12..12] ELIPPR.CYCN4 Bit Automatic Clearing */ + __IOM uint32_t CYCN5 : 1; /*!< [13..13] ELIPPR.CYCN5 Bit Automatic Clearing */ + uint32_t : 2; + __IOM uint32_t PLSP : 1; /*!< [16..16] ELIPPR.PLSP Bit Automatic Clearing */ + uint32_t : 7; + __IOM uint32_t PLSN : 1; /*!< [24..24] ELIPPR.PLSN Bit Automatic Clearing */ + uint32_t : 7; + } ELIPACR_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t STSR; /*!< (@ 0x00000040) STCA Status Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] Synchronized State Detection Flag */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] Synchronization Loss Detection Flag */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] Sync Message Reception Timeout Detection Flag */ + __IOM uint32_t W10D : 1; /*!< [4..4] Worst 10 Acquisition Completion Flag */ + uint32_t : 27; + } STSR_b; + }; + + union + { + __IOM uint32_t STIPR; /*!< (@ 0x00000044) STCA Status Notification Permission Register */ + + struct + { + __IOM uint32_t SYNC : 1; /*!< [0..0] SYNC Status Notification Enable */ + __IOM uint32_t SYNCOUT : 1; /*!< [1..1] SYNCOUT Status Notification Enable */ + uint32_t : 1; + __IOM uint32_t SYNTOUT : 1; /*!< [3..3] SYNTOUT Status Notification Enable */ + __IOM uint32_t W10D : 1; /*!< [4..4] W10D Status Notification Enable */ + uint32_t : 27; + } STIPR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t STCFR; /*!< (@ 0x00000050) STCA Clock Frequency Setting Register */ + + struct + { + __IOM uint32_t STCF : 2; /*!< [1..0] STCA Clock Frequency */ + uint32_t : 30; + } STCFR_b; + }; + + union + { + __IOM uint32_t STMR; /*!< (@ 0x00000054) STCA Operating Mode Register */ + + struct + { + __IOM uint32_t WINT : 8; /*!< [7..0] Worst 10 Acquisition Time */ + uint32_t : 5; + __IOM uint32_t CMOD : 1; /*!< [13..13] Time Synchronization Correction Mode */ + uint32_t : 1; + __IOM uint32_t W10S : 1; /*!< [15..15] Worst 10 Acquisition Control Select */ + __IOM uint32_t SYTH : 4; /*!< [19..16] Synchronized State Detection Threshold Setting */ + __IOM uint32_t DVTH : 4; /*!< [23..20] Synchronization Loss Detection Threshold Setting */ + uint32_t : 4; + __IOM uint32_t ALEN0 : 1; /*!< [28..28] Alarm Detection Enable 0 */ + __IOM uint32_t ALEN1 : 1; /*!< [29..29] Alarm Detection Enable 1 */ + uint32_t : 2; + } STMR_b; + }; + + union + { + __IOM uint32_t SYNTOR; /*!< (@ 0x00000058) Sync Message Reception Timeout Register */ + + struct + { + __IOM uint32_t SYNTOR : 32; /*!< [31..0] A Sync message not being received within 1024 x n (ns), + * where n is the setting, leads to a timeout for reception + * of Sync messages, leading to the STSR.SYNTOUT flag being + * set to 1. */ + } SYNTOR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t IPTSELR; /*!< (@ 0x00000060) IPLS Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t IPTSEL0 : 1; /*!< [0..0] Pulse Output Timer 0 Select */ + __IOM uint32_t IPTSEL1 : 1; /*!< [1..1] Pulse Output Timer 1 Select */ + __IOM uint32_t IPTSEL2 : 1; /*!< [2..2] Pulse Output Timer 2 Select */ + __IOM uint32_t IPTSEL3 : 1; /*!< [3..3] Pulse Output Timer 3 Select */ + __IOM uint32_t IPTSEL4 : 1; /*!< [4..4] Pulse Output Timer 4 Select */ + __IOM uint32_t IPTSEL5 : 1; /*!< [5..5] Pulse Output Timer 5 Select */ + uint32_t : 26; + } IPTSELR_b; + }; + + union + { + __IOM uint32_t MITSELR; /*!< (@ 0x00000064) MINT Interrupt Request Timer Select Register */ + + struct + { + __IOM uint32_t MINTEN0 : 1; /*!< [0..0] Pulse Output Timer 0 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN1 : 1; /*!< [1..1] Pulse Output Timer 1 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN2 : 1; /*!< [2..2] Pulse Output Timer 2 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN3 : 1; /*!< [3..3] Pulse Output Timer 3 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN4 : 1; /*!< [4..4] Pulse Output Timer 4 MINT Interrupt Output Enable */ + __IOM uint32_t MINTEN5 : 1; /*!< [5..5] Pulse Output Timer 5 MINT Interrupt Output Enable */ + uint32_t : 26; + } MITSELR_b; + }; + + union + { + __IOM uint32_t ELTSELR; /*!< (@ 0x00000068) ELC Output Timer Select Register */ + + struct + { + __IOM uint32_t ELTDIS0 : 1; /*!< [0..0] Pulse Output Timer 0 Event Generation Disable */ + __IOM uint32_t ELTDIS1 : 1; /*!< [1..1] Pulse Output Timer 1 Event Generation Disable */ + __IOM uint32_t ELTDIS2 : 1; /*!< [2..2] Pulse Output Timer 2 Event Generation Disable */ + __IOM uint32_t ELTDIS3 : 1; /*!< [3..3] Pulse Output Timer 3 Event Generation Disable */ + __IOM uint32_t ELTDIS4 : 1; /*!< [4..4] Pulse Output Timer 4 Event Generation Disable */ + __IOM uint32_t ELTDIS5 : 1; /*!< [5..5] Pulse Output Timer 5 Event Generation Disable */ + uint32_t : 26; + } ELTSELR_b; + }; + + union + { + __IOM uint32_t STCHSELR; /*!< (@ 0x0000006C) Time Synchronization Channel Select Register */ + + struct + { + __IOM uint32_t SYSEL : 1; /*!< [0..0] Timer Information Input SelectNOTE: Do not change the + * value of this bit while the SYNSTARTR.STR bit is 1. */ + uint32_t : 31; + } STCHSELR_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t SYNSTARTR; /*!< (@ 0x00000080) Slave Time Synchronization Start Register */ + + struct + { + __IOM uint32_t STR : 1; /*!< [0..0] Slave Time Synchronization Control */ + uint32_t : 31; + } SYNSTARTR_b; + }; + + union + { + __OM uint32_t LCIVLDR; /*!< (@ 0x00000084) Local Time Counter Initial Value Load Directive + * Register */ + + struct + { + __OM uint32_t LOAD : 1; /*!< [0..0] Local Time Counter Initial Value Load Directive */ + uint32_t : 31; + } LCIVLDR_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SYNTDARU; /*!< (@ 0x00000090) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of loss of synchronization. */ + } SYNTDARU_b; + }; + + union + { + __IOM uint32_t SYNTDARL; /*!< (@ 0x00000094) Synchronization Loss Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDARL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of loss of synchronization. */ + } SYNTDARL_b; + }; + + union + { + __IOM uint32_t SYNTDBRU; /*!< (@ 0x00000098) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRU : 32; /*!< [31..0] These bits hold the setting for the higher-order 32 + * bits of the threshold for detection of synchronization. */ + } SYNTDBRU_b; + }; + + union + { + __IOM uint32_t SYNTDBRL; /*!< (@ 0x0000009C) Synchronization Detection Threshold Registers */ + + struct + { + __IOM uint32_t SYNTDBRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the threshold for detection of synchronization. */ + } SYNTDBRL_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t LCIVRU; /*!< (@ 0x000000B0) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRU : 16; /*!< [15..0] These bits hold the setting for the higher-order 16 + * bits of the integer portion of the initial value for the + * local timer counter. */ + uint32_t : 16; + } LCIVRU_b; + }; + + union + { + __IOM uint32_t LCIVRM; /*!< (@ 0x000000B4) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRM : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the integer portion of the initial value for the local + * timer counter. */ + } LCIVRM_b; + }; + + union + { + __IOM uint32_t LCIVRL; /*!< (@ 0x000000B8) Local Time Counter Initial Value Registers */ + + struct + { + __IOM uint32_t LCIVRL : 32; /*!< [31..0] These bits hold the setting for the fractional portion + * of the initial value of the local timer counter in nanoseconds. */ + } LCIVRL_b; + }; + __IM uint32_t RESERVED7[26]; + + union + { + __IOM uint32_t GETW10R; /*!< (@ 0x00000124) Worst 10 Acquisition Directive Register */ + + struct + { + __IOM uint32_t GW10 : 1; /*!< [0..0] Worst 10 Acquisition Directive */ + uint32_t : 31; + } GETW10R_b; + }; + + union + { + __IOM uint32_t PLIMITRU; /*!< (@ 0x00000128) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the positive gradient. */ + uint32_t : 1; + } PLIMITRU_b; + }; + + union + { + __IOM uint32_t PLIMITRM; /*!< (@ 0x0000012C) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the positive gradient. */ + } PLIMITRM_b; + }; + + union + { + __IOM uint32_t PLIMITRL; /*!< (@ 0x00000130) Positive Gradient Limit Registers */ + + struct + { + __IOM uint32_t PLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the positive gradient. */ + } PLIMITRL_b; + }; + + union + { + __IOM uint32_t MLIMITRU; /*!< (@ 0x00000134) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRU : 31; /*!< [30..0] These bits hold the setting for the higher-order 31 + * bits of the limit for the negative gradient. */ + uint32_t : 1; + } MLIMITRU_b; + }; + + union + { + __IOM uint32_t MLIMITRM; /*!< (@ 0x00000138) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRM : 32; /*!< [31..0] These bits hold the setting for the middle-order 32 + * bits of the limit for the negative gradient. */ + } MLIMITRM_b; + }; + + union + { + __IOM uint32_t MLIMITRL; /*!< (@ 0x0000013C) Negative Gradient Limit Registers */ + + struct + { + __IOM uint32_t MLIMITRL : 32; /*!< [31..0] These bits hold the setting for the lower-order 32 bits + * of the limit for the negative gradient. */ + } MLIMITRL_b; + }; + + union + { + __IOM uint32_t GETINFOR; /*!< (@ 0x00000140) Statistical Information Retention Control Register */ + + struct + { + __IOM uint32_t INFO : 1; /*!< [0..0] Information Retention ControlNOTE: Once information fetching + * is directed, values of various statistical information + * read before completion of information fetching are not + * guaranteed. */ + uint32_t : 31; + } GETINFOR_b; + }; + __IM uint32_t RESERVED8[11]; + + union + { + __IM uint32_t LCCVRU; /*!< (@ 0x00000170) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRU : 16; /*!< [15..0] These bits are for reading the higher-order 16 bits + * of the integer portion of the local timer counter's value. */ + uint32_t : 16; + } LCCVRU_b; + }; + + union + { + __IM uint32_t LCCVRM; /*!< (@ 0x00000174) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRM : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the integer portion of the local timer counter's value. */ + } LCCVRM_b; + }; + + union + { + __IM uint32_t LCCVRL; /*!< (@ 0x00000178) Local Time Counters */ + + struct + { + __IM uint32_t LCCVRL : 32; /*!< [31..0] These bits are for reading the fractional portion of + * the local timer counter's value (in nanoseconds). */ + } LCCVRL_b; + }; + __IM uint32_t RESERVED9[37]; + + union + { + __IM uint32_t PW10VRU; /*!< (@ 0x00000210) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the positive gradient value. */ + } PW10VRU_b; + }; + + union + { + __IM uint32_t PW10VRM; /*!< (@ 0x00000214) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the positive gradient value. */ + } PW10VRM_b; + }; + + union + { + __IM uint32_t PW10VRL; /*!< (@ 0x00000218) Positive Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t PW10VRL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the positive gradient value. */ + } PW10VRL_b; + }; + __IM uint32_t RESERVED10[45]; + + union + { + __IM uint32_t MW10RU; /*!< (@ 0x000002D0) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RU : 32; /*!< [31..0] These bits are for reading the higher-order 32 bits + * of the negative gradient value. */ + } MW10RU_b; + }; + + union + { + __IM uint32_t MW10RM; /*!< (@ 0x000002D4) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RM : 32; /*!< [31..0] These bits are for reading the middle-order 32 bits + * of the negative gradient value. */ + } MW10RM_b; + }; + + union + { + __IM uint32_t MW10RL; /*!< (@ 0x000002D8) Negative Gradient Worst 10 Value Registers */ + + struct + { + __IM uint32_t MW10RL : 32; /*!< [31..0] These bits are for reading the lower-order 32 bits of + * the negative gradient value. */ + } MW10RL_b; + }; + __IM uint32_t RESERVED11[9]; + __IOM R_ETHERC_EPTPC_COMMON_TM_Type TM[6]; /*!< (@ 0x00000300) Timer Setting Registers */ + __IM uint32_t RESERVED12[7]; + + union + { + __IOM uint32_t TMSTARTR; /*!< (@ 0x0000037C) Timer Start Register */ + + struct + { + __IOM uint32_t EN0 : 1; /*!< [0..0] Pulse Output Timer 0 Start */ + __IOM uint32_t EN1 : 1; /*!< [1..1] Pulse Output Timer 1 Start */ + __IOM uint32_t EN2 : 1; /*!< [2..2] Pulse Output Timer 2 Start */ + __IOM uint32_t EN3 : 1; /*!< [3..3] Pulse Output Timer 3 Start */ + __IOM uint32_t EN4 : 1; /*!< [4..4] Pulse Output Timer 4 Start */ + __IOM uint32_t EN5 : 1; /*!< [5..5] Pulse Output Timer 5 Start */ + uint32_t : 26; + } TMSTARTR_b; + }; + __IM uint32_t RESERVED13[32]; + + union + { + __IOM uint32_t PRSR; /*!< (@ 0x00000400) PRC-TC Status Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] Relay Packet Overflow Detection Flag 0 */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] Relay Packet Overflow Detection Flag 1 */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] Relay Packet Overflow Detection Flag 2 */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] Relay Packet Overflow Detection Flag 3 */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] Originating MAC Address Mismatch Detection Flag */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] Relay Packet Underflow Detection Flag 0 */ + __IOM uint32_t URE1 : 1; /*!< [29..29] Relay Packet Underflow Detection Flag 1 */ + uint32_t : 2; + } PRSR_b; + }; + + union + { + __IOM uint32_t PRIPR; /*!< (@ 0x00000404) PRC-TC Status Notification Permission Register */ + + struct + { + __IOM uint32_t OVRE0 : 1; /*!< [0..0] PRSR.OVRE0 Status Notification Permission */ + __IOM uint32_t OVRE1 : 1; /*!< [1..1] PRSR.OVRE1 Status Notification Permission */ + __IOM uint32_t OVRE2 : 1; /*!< [2..2] PRSR.OVRE2 Status Notification Permission */ + __IOM uint32_t OVRE3 : 1; /*!< [3..3] PRSR.OVRE3 Status Notification Permission */ + uint32_t : 4; + __IOM uint32_t MACE : 1; /*!< [8..8] PRSR.MACE Status Notification Permission */ + uint32_t : 19; + __IOM uint32_t URE0 : 1; /*!< [28..28] PRSR.URE0 Status Notification Permission */ + __IOM uint32_t URE1 : 1; /*!< [29..29] PRSR.URE1 Status Notification Permission */ + uint32_t : 2; + } PRIPR_b; + }; + __IM uint32_t RESERVED14[2]; + __IOM R_ETHERC_EPTPC_COMMON_PR_Type PR[2]; /*!< (@ 0x00000410) Local MAC Address Registers */ + + union + { + __IOM uint32_t TRNDISR; /*!< (@ 0x00000420) Packet Transmission Control Register */ + + struct + { + __IOM uint32_t TDIS : 2; /*!< [1..0] Packet Transmission Control */ + uint32_t : 30; + } TRNDISR_b; + }; + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint32_t TRNMR; /*!< (@ 0x00000430) Relay Mode Register */ + + struct + { + __IOM uint32_t MOD : 1; /*!< [0..0] Cut-Through Mode */ + uint32_t : 7; + __IOM uint32_t FWD0 : 1; /*!< [8..8] Channel 0 Relay Enable */ + __IOM uint32_t FWD1 : 1; /*!< [9..9] Channel 1 Relay Enable */ + uint32_t : 22; + } TRNMR_b; + }; + + union + { + __IOM uint32_t TRNCTTDR; /*!< (@ 0x00000434) Cut-Through Transfer Start Threshold Register */ + + struct + { + __IOM uint32_t THVAL : 11; /*!< [10..0] FIFO Read Start ThresholdThreshold for starting to read + * data from the relay FIFO in cut-through mode (specified + * as the number of bytes)NOTE1: A value cannot be set in + * the lower-order 2 bits. These bits are fixed to 0.NOTE2: + * A value of less than 96 bytes cannot be set. */ + uint32_t : 21; + } TRNCTTDR_b; + }; +} R_ETHERC_EPTPC_COMMON_Type; /*!< Size = 1080 (0x438) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Graphics LCD Controller (R_GLCDC) + */ + +typedef struct /*!< (@ 0x400E0000) R_GLCDC Structure */ +{ + union + { + __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR1_CLUT1_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT0_b[256]; + }; + + union + { + __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane */ + + struct + { + __IOM uint32_t B : 8; /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t G : 8; /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t R : 8; /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane */ + __IOM uint32_t A : 8; /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics + * m Plane */ + } GR2_CLUT1_b[256]; + }; + __IOM R_GLCDC_BG_Type BG; /*!< (@ 0x00001000) Background Registers */ + __IM uint32_t RESERVED[57]; + __IOM R_GLCDC_GR_Type GR[2]; /*!< (@ 0x00001100) Layer Registers */ + __IOM R_GLCDC_GAM_Type GAM[3]; /*!< (@ 0x00001300) Gamma Settings */ + __IOM R_GLCDC_OUT_Type OUT; /*!< (@ 0x000013C0) Output Control Registers */ + __IM uint32_t RESERVED1[6]; + __IOM R_GLCDC_TCON_Type TCON; /*!< (@ 0x00001400) Timing Control Registers */ + __IM uint32_t RESERVED2[5]; + __IOM R_GLCDC_SYSCNT_Type SYSCNT; /*!< (@ 0x00001440) GLCDC System Control Registers */ +} R_GLCDC_Type; /*!< Size = 5204 (0x1454) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief JPEG Codec (R_JPEG) + */ + +typedef struct /*!< (@ 0x400E6000) R_JPEG Structure */ +{ + union + { + __IOM uint8_t JCMOD; /*!< (@ 0x00000000) JPEG Code Mode Register */ + + struct + { + __IOM uint8_t REDU : 3; /*!< [2..0] Pixel FormatNOTE: Read-only in Decompression. */ + __IOM uint8_t DSP : 1; /*!< [3..3] Compression/Decompression Set Note: When changing between + * processing for compression and for decompression, be sure + * to reset this module in advance by setting the JCUSRST + * bit in the software reset control register 2 (SWRSTCR2) + * of the power-downmodes. */ + uint8_t : 4; + } JCMOD_b; + }; + + union + { + __OM uint8_t JCCMD; /*!< (@ 0x00000001) JPEG Code Command Register */ + + struct + { + __OM uint8_t JSRT : 1; /*!< [0..0] JPEG Core Process Start CommandTo start JPEG core processing, + * set this bit to 1. Do not write this bit to 1 again while + * this module is in operation. */ + __OM uint8_t JRST : 1; /*!< [1..1] JPEG Core Process Stop Clear CommandTo clear the process-stopped + * state caused by requests to read the image size and pixel + * format (enabled by the INT3 bit in JINTE0), set this bit + * to 1. */ + __OM uint8_t JEND : 1; /*!< [2..2] Interrupt Request Clear Command This bit is valid only + * for the interrupt sources corresponding to bits INS6, INS5, + * and INS3 in JINTS0. To clear an interrupt request, set + * this bit to 1 */ + uint8_t : 4; + __OM uint8_t BRST : 1; /*!< [7..7] Bus Reset. NOTE: When this module is in operation, the + * bus reset command should not be issued. */ + } JCCMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t JCQTN; /*!< (@ 0x00000003) JPEG Code Quantization Table Number Register */ + + struct + { + __IOM uint8_t QT1 : 2; /*!< [1..0] Quantization table number for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t QT2 : 2; /*!< [3..2] Quantization table number for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t QT3 : 2; /*!< [5..4] Quantization table number for the third color component + * NOTE: Read-only in Decompression. */ + uint8_t : 2; + } JCQTN_b; + }; + + union + { + __IOM uint8_t JCHTN; /*!< (@ 0x00000004) JPEG Code Huffman Table Number Register */ + + struct + { + __IOM uint8_t HTD1 : 1; /*!< [0..0] Huffman table number (DC) for the first color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA1 : 1; /*!< [1..1] Huffman table number (AC) for the first color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD2 : 1; /*!< [2..2] Huffman table number (DC) for the second color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA2 : 1; /*!< [3..3] Huffman table number (AC) for the second color componentNOTE: + * Read-only in Decompression. */ + __IOM uint8_t HTD3 : 1; /*!< [4..4] Huffman table number (DC) for the third color component + * NOTE: Read-only in Decompression. */ + __IOM uint8_t HTA3 : 1; /*!< [5..5] Huffman table number (AC) for the third color componentNOTE: + * Read-only in Decompression. */ + uint8_t : 2; + } JCHTN_b; + }; + + union + { + __IOM uint8_t JCDRIU; /*!< (@ 0x00000005) JPEG Code DRI Upper Register */ + + struct + { + __IOM uint8_t DRIU : 8; /*!< [7..0] Upper Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRIU_b; + }; + + union + { + __IOM uint8_t JCDRID; /*!< (@ 0x00000006) JPEG Code DRI Lower Register */ + + struct + { + __IOM uint8_t DRID : 8; /*!< [7..0] Lower Bytes of MCUs Preceding RST MarkerWhen both upper + * and lower bytes are set to 00h, neither a DRI nor an RST + * marker is placed.NOTE: Read-only in Decompression. */ + } JCDRID_b; + }; + + union + { + __IOM uint8_t JCVSZU; /*!< (@ 0x00000007) JPEG Code Vertical Size Upper Register */ + + struct + { + __IOM uint8_t VSZU : 8; /*!< [7..0] Upper Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZU_b; + }; + + union + { + __IOM uint8_t JCVSZD; /*!< (@ 0x00000008) JPEG Code Vertical Size Lower Register */ + + struct + { + __IOM uint8_t VSZD : 8; /*!< [7..0] Lower Bytes of Vertical Image SizeIn decompression process, + * a downloaded value from the JPEG coded data is set. NOTE: + * Read-only in Decompression. */ + } JCVSZD_b; + }; + + union + { + __IOM uint8_t JCHSZU; /*!< (@ 0x00000009) JPEG Code Horizontal Size Upper Register */ + + struct + { + __IOM uint8_t HSZU : 8; /*!< [7..0] Upper Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZU_b; + }; + + union + { + __IOM uint8_t JCHSZD; /*!< (@ 0x0000000A) JPEG Coded Horizontal Size Lower Register */ + + struct + { + __IOM uint8_t HSZD : 8; /*!< [7..0] Lower Bytes of Horizontal Image SizeIn decompression + * process, a downloaded value from the JPEG coded data is + * set. NOTE: Read-only in Decompression. */ + } JCHSZD_b; + }; + + union + { + __IM uint8_t JCDTCU; /*!< (@ 0x0000000B) JPEG Code Data Count Upper Register */ + + struct + { + __IM uint8_t DCU : 8; /*!< [7..0] Upper bytes of the counted amount of data to be compressed + * The values of this register are reset before compression + * starts.NOTE: Read-only in Decompression. */ + } JCDTCU_b; + }; + + union + { + __IM uint8_t JCDTCM; /*!< (@ 0x0000000C) JPEG Code Data Count Middle Register */ + + struct + { + __IM uint8_t DCM : 8; /*!< [7..0] Middle bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts. + * NOTE: Read-only in Decompression. */ + } JCDTCM_b; + }; + + union + { + __IM uint8_t JCDTCD; /*!< (@ 0x0000000D) JPEG Code Data Count Lower Register */ + + struct + { + __IM uint8_t DCD : 8; /*!< [7..0] Lower bytes of the counted amount of data to be compressedThe + * values of this register are reset before compression starts.NOTE: + * Read-only in Decompression. */ + } JCDTCD_b; + }; + + union + { + __IOM uint8_t JINTE0; /*!< (@ 0x0000000E) JPEG Interrupt Enable Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INT3 : 1; /*!< [3..3] This bit enables an interrupt to be generated when it + * has been determined that the image size and the subsampling + * setting of the compressed data can be read through analyzing + * the data. */ + uint8_t : 1; + __IOM uint8_t INT5 : 1; /*!< [5..5] This bit enables an interrupt to be generated when the + * final number of MCU data in the Huffman-coding segment + * is not correct in decompression. When this bit is not set + * to enable interrupt generation, an error code is not returned. */ + __IOM uint8_t INT6 : 1; /*!< [6..6] This bit enables an interrupt to be generated when the + * total number of data in the Huffman-coding segment is not + * correct in decompression. When this bit is not set to enable + * interrupt generation, an error code is not returned. */ + __IOM uint8_t INT7 : 1; /*!< [7..7] This bit enables an interrupt to be generated when the + * number of data in the restart interval of the Huffman-coding + * segment is not correct in decompression.When this bit is + * not set to enable interrupt generation, an error code is + * not returned. */ + } JINTE0_b; + }; + + union + { + __IOM uint8_t JINTS0; /*!< (@ 0x0000000F) JPEG Interrupt Status Register 0 */ + + struct + { + uint8_t : 3; + __IOM uint8_t INS3 : 1; /*!< [3..3] This bit is set to 1 when the image size and pixel format + * can be read. When an interrupt occurs, this module stops + * processing and the state is indicated by the JCRST register. + * To make this module resume processing, set the JPEG core + * process stop clear command bit (JRST) in JCCMD. */ + uint8_t : 1; + __IOM uint8_t INS5 : 1; /*!< [5..5] This bit is set to 1 when a compressed data error occurs. */ + __IOM uint8_t INS6 : 1; /*!< [6..6] This bit is set to 1 when this module completes compression + * process normally. */ + uint8_t : 1; + } JINTS0_b; + }; + + union + { + __IOM uint8_t JCDERR; /*!< (@ 0x00000010) JPEG Code Decode Error Register */ + + struct + { + __IOM uint8_t ERR : 4; /*!< [3..0] Error Code (See tables )Identify the type of the error + * which has occurred in the compressed data analysis for + * decompression. */ + uint8_t : 4; + } JCDERR_b; + }; + + union + { + __IM uint8_t JCRST; /*!< (@ 0x00000011) JPEG Code Reset Register */ + + struct + { + __IM uint8_t RST : 1; /*!< [0..0] Operating State */ + uint8_t : 7; + } JCRST_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[11]; + + union + { + __IOM uint32_t JIFECNT; /*!< (@ 0x00000040) JPEG Interface Compression Control Register */ + + struct + { + __IOM uint32_t DINSWAP : 3; /*!< [2..0] Byte/Halfword Swap */ + uint32_t : 1; + __IOM uint32_t DINLC : 1; /*!< [4..4] Count Mode Setting for Stopping Input Image Data Lines */ + __OM uint32_t DINRCMD : 1; /*!< [5..5] Input Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the input of image + * data lines is on. Setting this bit to 1 resumes reading + * input image data. This bit is always read as 0. */ + __IOM uint32_t DINRINI : 1; /*!< [6..6] Address Initialization when Resuming Input of Image Data + * Lines This bit is only valid when the count mode for stopping + * the input of image data lines is on. Set this bit before + * writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JOUTSWAP : 3; /*!< [10..8] Byte/Halfword/Word Swap Output coded data in compression + * is swapped. */ + uint32_t : 21; + } JIFECNT_b; + }; + + union + { + __IOM uint32_t JIFESA; /*!< (@ 0x00000044) JPEG Interface Compression Source Address Register */ + + struct + { + __IOM uint32_t ESA : 32; /*!< [31..0] Input Image Data Source Address (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFESA_b; + }; + + union + { + __IOM uint32_t JIFESOFST; /*!< (@ 0x00000048) JPEG Interface Compression Line Offset Register */ + + struct + { + __IOM uint32_t ESMW : 15; /*!< [14..0] Input Image Data Lines Offset(in 8-byte units)The lower + * three bits should be set to 0. */ + uint32_t : 17; + } JIFESOFST_b; + }; + + union + { + __IOM uint32_t JIFEDA; /*!< (@ 0x0000004C) JPEG Interface Compression Destination Address + * Register */ + + struct + { + __IOM uint32_t EDA : 32; /*!< [31..0] Input Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + } JIFEDA_b; + }; + + union + { + __IOM uint32_t JIFESLC; /*!< (@ 0x00000050) JPEG Interface Compression Source Line Count + * Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Data Lines to be Read (in 8-line + * units) The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFESLC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t JIFDCNT; /*!< (@ 0x00000058) JPEG Interface Decompression Control Register */ + + struct + { + __IOM uint32_t DOUTSWAP : 3; /*!< [2..0] Byte/Word Swap Output image data in decompression is + * swapped. */ + uint32_t : 1; + __IOM uint32_t DOUTLC : 1; /*!< [4..4] Count Mode for Stopping Output Image Data Lines */ + __OM uint32_t DOUTRCMD : 1; /*!< [5..5] Output Image Data Lines Resume Command This bit is valid + * only when the count mode for stopping the output of image + * data lines is on. Setting this bit to 1 resumes writing + * image data. This bit is always read as 0. */ + __IOM uint32_t DOUTRINI : 1; /*!< [6..6] Address Initialization when Resuming Output of Image + * Data Lines This bit is only valid when the count mode for + * stopping the output of image data lines is on. Set this + * bit before writing 1 to the data-line resume command bit. */ + uint32_t : 1; + __IOM uint32_t JINSWAP : 3; /*!< [10..8] Byte/Word/Longword Swap Input coded data in decompression + * is swapped. */ + uint32_t : 1; + __IOM uint32_t JINC : 1; /*!< [12..12] Count Mode Setting for Stopping Input Coded Data */ + __OM uint32_t JINRCMD : 1; /*!< [13..13] Input Coded Data Resume CommandThis bit is valid only + * when the count mode for stopping the input of coded data + * is on. Setting this bit to 1 resumes reading input coded + * data. This bit is always read as 0. */ + __IOM uint32_t JINRINI : 1; /*!< [14..14] Address Initialization when Input Coded Data is Resumed + * This bit is only valid when the count mode for stopping + * the input of coded data is on. Set this bit before writing + * 1 to the data resume command bit. */ + uint32_t : 9; + __IOM uint32_t OPF : 2; /*!< [25..24] Specifies output image data pixel format. */ + __IOM uint32_t HINTER : 2; /*!< [27..26] Horizontal Subsampling Subsamples horizontal output + * image data. */ + __IOM uint32_t VINTER : 2; /*!< [29..28] Vertical SubsamplingSubsamples vertical output image + * data. */ + uint32_t : 2; + } JIFDCNT_b; + }; + + union + { + __IOM uint32_t JIFDSA; /*!< (@ 0x0000005C) JPEG Interface Decompression Source Address Register */ + + struct + { + __IOM uint32_t DSA : 32; /*!< [31..0] Input Coded Data Source AddressInput Coded Data Source + * Address (in 8-byte units) The lower three bits should be + * set to 0. */ + } JIFDSA_b; + }; + + union + { + __IOM uint32_t JIFDDOFST; /*!< (@ 0x00000060) JPEG Interface Decompression Line Offset Register */ + + struct + { + __IOM uint32_t DDMW : 15; /*!< [14..0] Output Image Data Lines Offset (in 8-byte units) The + * lower three bits should be set to 0. */ + uint32_t : 17; + } JIFDDOFST_b; + }; + + union + { + __IOM uint32_t JIFDDA; /*!< (@ 0x00000064) JPEG Interface Decompression Destination Address + * Register */ + + struct + { + __IOM uint32_t DDA : 32; /*!< [31..0] Output Image Data Destination Address (in 8-byte units) + * The lower three bits should be set to 0. */ + } JIFDDA_b; + }; + + union + { + __IOM uint32_t JIFDSDC; /*!< (@ 0x00000068) JPEG Interface Decompression Source Data Count + * Register */ + + struct + { + __IOM uint32_t JDATAS : 16; /*!< [15..0] Amount of Input Coded Data to be Read (in 8-byte units) + * The lower three bits should be set to 0. */ + uint32_t : 16; + } JIFDSDC_b; + }; + + union + { + __IOM uint32_t JIFDDLC; /*!< (@ 0x0000006C) JPEG Interface Decompression Destination Line + * Count Register */ + + struct + { + __IOM uint32_t LINES : 16; /*!< [15..0] Number of Input Image Lines to Be ReadThe lower three + * bits should be set to 0. These bits are read as0.Number + * of input image data lines to be read, in 8-line units. */ + uint32_t : 16; + } JIFDDLC_b; + }; + + union + { + __IOM uint32_t JIFDADT; /*!< (@ 0x00000070) JPEG Interface Decompression alpha Set Register */ + + struct + { + __IOM uint32_t ALPHA : 8; /*!< [7..0] Setting of the alpha value for output in ARGB8888 format. */ + uint32_t : 24; + } JIFDADT_b; + }; + __IM uint32_t RESERVED4[6]; + + union + { + __IOM uint32_t JINTE1; /*!< (@ 0x0000008C) JPEG Interrupt Enable Register 1 */ + + struct + { + __IOM uint32_t DOUTLEN : 1; /*!< [0..0] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DOUTLF bit in JINTS1 is set to + * 1 */ + __IOM uint32_t JINEN : 1; /*!< [1..1] Enables or disables a data transfer processing interrupt + * request (JDTI) when the JINF bit in JINTS1 is set to 1. */ + __IOM uint32_t DBTEN : 1; /*!< [2..2] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DBTF bit in JINTS1 is set to 1. */ + uint32_t : 2; + __IOM uint32_t DINLEN : 1; /*!< [5..5] Enables or disables a data transfer processing interrupt + * request (JDTI) when the DINLF bit in JINTS1 is set to 1. */ + __IOM uint32_t CBTEN : 1; /*!< [6..6] Enables or disables a data transfer processing interrupt + * request (JDTI) when the CBTF bit in JINTS1 is set to 1. */ + uint32_t : 25; + } JINTE1_b; + }; + + union + { + __IOM uint32_t JINTS1; /*!< (@ 0x00000090) JPEG Interrupt Status Register 1 */ + + struct + { + __IOM uint32_t DOUTLF : 1; /*!< [0..0] In decompression, this bit is set to 1 when the number + * of lines of output image data indicated by JIFDDLC have + * been written. This bit is only valid when the DOUTLC bit + * in JIFDCNT is set to 1. */ + __IOM uint32_t JINF : 1; /*!< [1..1] This bit is set to 1 when the amount of input coded data + * indicated by JIFDSDC is read in decompression. This bit + * is valid only when the JINC bit in JIFDCNT is set to 1. */ + __IOM uint32_t DBTF : 1; /*!< [2..2] This bit is set to 1 when the last output image data + * is written in decompression. */ + uint32_t : 2; + __IOM uint32_t DINLF : 1; /*!< [5..5] This bit is set to 1 when the number of input image data + * lines indicated by JIFESLC is read in compression. This + * bit is valid only when the DINLC bit in JIFECNT is set + * to 1. */ + __IOM uint32_t CBTF : 1; /*!< [6..6] This bit is set to 1 when the last output coded data + * is written in compression. */ + uint32_t : 25; + } JINTS1_b; + }; + __IM uint32_t RESERVED5[27]; + __OM uint8_t JCQTBL0[64]; /*!< (@ 0x00000100) Quantization Table 0 */ + __OM uint8_t JCQTBL1[64]; /*!< (@ 0x00000140) Quantization Table 1 */ + __OM uint8_t JCQTBL2[64]; /*!< (@ 0x00000180) Quantization Table 2 */ + __OM uint8_t JCQTBL3[64]; /*!< (@ 0x000001C0) Quantization Table 3 */ + __IOM uint8_t JCHTBD0[28]; /*!< (@ 0x00000200) DC Huffman Table 0 */ + __IM uint32_t RESERVED6; + __IOM uint8_t JCHTBA0[178]; /*!< (@ 0x00000220) AC Huffman Table 0 */ + __IM uint16_t RESERVED7; + __IM uint32_t RESERVED8[11]; + __IOM uint8_t JCHTBD1[28]; /*!< (@ 0x00000300) DC Huffman Table 1 */ + __IM uint32_t RESERVED9; + __IOM uint8_t JCHTBA1[178]; /*!< (@ 0x00000320) DC Huffman Table 1 */ + __IM uint16_t RESERVED10; +} R_JPEG_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Data Capture Unit (R_PDC) + */ + +typedef struct /*!< (@ 0x40094000) R_PDC Structure */ +{ + union + { + __IOM uint32_t PCCR0; /*!< (@ 0x00000000) PDC Control Register 0 */ + + struct + { + __IOM uint32_t PCKE : 1; /*!< [0..0] Channel 0 GTCNT Count Clear */ + __IOM uint32_t VPS : 1; /*!< [1..1] VSYNC Signal Polarity Select */ + __IOM uint32_t HPS : 1; /*!< [2..2] HSYNC Signal Polarity Select */ + __OM uint32_t PRST : 1; /*!< [3..3] PDC Reset */ + __IOM uint32_t DFIE : 1; /*!< [4..4] Receive Data Ready Interrupt Enable */ + __IOM uint32_t FEIE : 1; /*!< [5..5] Frame End Interrupt Enable */ + __IOM uint32_t OVIE : 1; /*!< [6..6] Overrun Interrupt Enable */ + __IOM uint32_t UDRIE : 1; /*!< [7..7] Underrun Interrupt Enable */ + __IOM uint32_t VERIE : 1; /*!< [8..8] Vertical Line Number Setting Error Interrupt Enable */ + __IOM uint32_t HERIE : 1; /*!< [9..9] Horizontal Byte Number Setting Error Interrupt Enable */ + __IOM uint32_t PCKOE : 1; /*!< [10..10] PCKO Output Enable */ + __IOM uint32_t PCKDIV : 3; /*!< [13..11] PCKO Frequency Division Ratio Select */ + __IOM uint32_t EDS : 1; /*!< [14..14] Endian Select */ + uint32_t : 17; + } PCCR0_b; + }; + + union + { + __IOM uint32_t PCCR1; /*!< (@ 0x00000004) PDC Control Register 1 */ + + struct + { + __IOM uint32_t PCE : 1; /*!< [0..0] PDC Operation Enable */ + uint32_t : 31; + } PCCR1_b; + }; + + union + { + __IOM uint32_t PCSR; /*!< (@ 0x00000008) PDC Status Register */ + + struct + { + __IM uint32_t FBSY : 1; /*!< [0..0] Frame Busy Flag */ + __IM uint32_t FEMPF : 1; /*!< [1..1] FIFO Empty Flag */ + __IOM uint32_t FEF : 1; /*!< [2..2] Frame End Flag */ + __IOM uint32_t OVRF : 1; /*!< [3..3] Overrun Flag */ + __IOM uint32_t UDRF : 1; /*!< [4..4] Underrun Flag */ + __IOM uint32_t VERF : 1; /*!< [5..5] Vertical Line Number Setting Error Flag */ + __IOM uint32_t HERF : 1; /*!< [6..6] Horizontal Byte Number Setting Error Flag */ + uint32_t : 25; + } PCSR_b; + }; + + union + { + __IM uint32_t PCMONR; /*!< (@ 0x0000000C) PDC Pin Monitor Register */ + + struct + { + __IM uint32_t VSYNC : 1; /*!< [0..0] VSYNC Signal Status Flag */ + __IM uint32_t HSYNC : 1; /*!< [1..1] HSYNC Signal Status Flag */ + uint32_t : 30; + } PCMONR_b; + }; + + union + { + __IM uint32_t PCDR; /*!< (@ 0x00000010) PDC Receive Data Register */ + + struct + { + __IM uint32_t PCDR : 32; /*!< [31..0] The PDC includes a 32-bit-wide, 22-stage FIFO for the + * storage of captured data. The PCDR register is a 4-byte + * space to which the FIFO is mapped, and four bytes of data + * are read from the PCDR register at a time. */ + } PCDR_b; + }; + + union + { + __IOM uint32_t VCR; /*!< (@ 0x00000014) Vertical Capture Register */ + + struct + { + __IOM uint32_t VST : 12; /*!< [11..0] Vertical Capture Start Line PositionNumber of the line + * where capture is to start. */ + uint32_t : 4; + __IOM uint32_t VSZ : 12; /*!< [27..16] Vertical Capture Size Number of lines to be captured. */ + uint32_t : 4; + } VCR_b; + }; + + union + { + __IOM uint32_t HCR; /*!< (@ 0x00000018) Horizontal Capture Register */ + + struct + { + __IOM uint32_t HST : 12; /*!< [11..0] Horizontal Capture Start Byte Position Horizontal position + * in bytes where capture is to start. */ + uint32_t : 4; + __IOM uint32_t HSZ : 12; /*!< [27..16] Horizontal Capture Size Number of bytes to capture + * horizontally. */ + uint32_t : 4; + } HCR_b; + }; +} R_PDC_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40062000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4004E000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_CTSU_BASE 0x40081000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DRW_BASE 0x400E4000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_ETHERC0_BASE 0x40064100UL + #define R_ETHERC_EDMAC_BASE 0x40064000UL + #define R_PTP_EDMAC_BASE 0x40064400UL + #define R_ETHERC_EPTPC_BASE 0x40065800UL + #define R_ETHERC_EPTPC1_BASE 0x40065C00UL + #define R_ETHERC_EPTPC_CFG_BASE 0x40064500UL + #define R_ETHERC_EPTPC_COMMON_BASE 0x40065000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GLCDC_BASE 0x400E0000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_JPEG_BASE 0x400E6000UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PDC_BASE 0x40094000UL + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SDHI0_BASE 0x40062000UL + #define R_SDHI1_BASE 0x40062400UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SSI0_BASE 0x4004E000UL + #define R_SSI1_BASE 0x4004E100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40044200UL + #define R_USB_HS0_BASE 0x40060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DRW ((R_DRW_Type *) R_DRW_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_PTP_EDMAC ((R_ETHERC_EDMAC_Type *) R_PTP_EDMAC_BASE) + #define R_ETHERC_EPTPC ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC_BASE) + #define R_ETHERC_EPTPC1 ((R_ETHERC_EPTPC_Type *) R_ETHERC_EPTPC1_BASE) + #define R_ETHERC_EPTPC_CFG ((R_ETHERC_EPTPC_CFG_Type *) R_ETHERC_EPTPC_CFG_BASE) + #define R_ETHERC_EPTPC_COMMON ((R_ETHERC_EPTPC_COMMON_Type *) R_ETHERC_EPTPC_COMMON_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GLCDC ((R_GLCDC_Type *) R_GLCDC_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_JPEG ((R_JPEG_Type *) R_JPEG_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PDC ((R_PDC_Type *) R_PDC_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ TM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STTRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Pos (0UL) /*!< TMSTTRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRU_TMSTTRU_Msk (0xffffffffUL) /*!< TMSTTRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STTRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Pos (0UL) /*!< TMSTTRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_STTRL_TMSTTRL_Msk (0xffffffffUL) /*!< TMSTTRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CYCR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Pos (0UL) /*!< TMCYCR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_CYCR_TMCYCR_Msk (0x3fffffffUL) /*!< TMCYCR (Bitfield-Mask: 0x3fffffff) */ +/* ========================================================= PLSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Pos (0UL) /*!< TMPLSR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TM_PLSR_TMPLSR_Msk (0x1fffffffUL) /*!< TMPLSR (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ PR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MACRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Pos (0UL) /*!< PRMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRU_PRMACRU_Msk (0xffffffUL) /*!< PRMACRU (Bitfield-Mask: 0xffffff) */ +/* ========================================================= MACRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Pos (0UL) /*!< PRMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PR_MACRL_PRMACRL_Msk (0xffffffUL) /*!< PRMACRL (Bitfield-Mask: 0xffffff) */ + +/* =========================================================================================================================== */ +/* ================ BG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_GLCDC_BG_EN_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_EN_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_EN_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_EN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_EN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ +/* ========================================================= PERI ========================================================== */ + #define R_GLCDC_BG_PERI_FV_Pos (16UL) /*!< FV (Bit 16) */ + #define R_GLCDC_BG_PERI_FV_Msk (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_PERI_FH_Pos (0UL) /*!< FH (Bit 0) */ + #define R_GLCDC_BG_PERI_FH_Msk (0x7ffUL) /*!< FH (Bitfield-Mask: 0x7ff) */ +/* ========================================================= SYNC ========================================================== */ + #define R_GLCDC_BG_SYNC_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_SYNC_VP_Msk (0xf0000UL) /*!< VP (Bitfield-Mask: 0x0f) */ + #define R_GLCDC_BG_SYNC_HP_Pos (0UL) /*!< HP (Bit 0) */ + #define R_GLCDC_BG_SYNC_HP_Msk (0xfUL) /*!< HP (Bitfield-Mask: 0x0f) */ +/* ========================================================= VSIZE ========================================================= */ + #define R_GLCDC_BG_VSIZE_VP_Pos (16UL) /*!< VP (Bit 16) */ + #define R_GLCDC_BG_VSIZE_VP_Msk (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_VSIZE_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_BG_VSIZE_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= HSIZE ========================================================= */ + #define R_GLCDC_BG_HSIZE_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_GLCDC_BG_HSIZE_HP_Msk (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_BG_HSIZE_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_BG_HSIZE_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== BGC ========================================================== */ + #define R_GLCDC_BG_BGC_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_BG_BGC_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_BG_BGC_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_BG_BGC_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_BG_BGC_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_BG_MON_SWRST_Pos (16UL) /*!< SWRST (Bit 16) */ + #define R_GLCDC_BG_MON_SWRST_Msk (0x10000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_VEN_Pos (8UL) /*!< VEN (Bit 8) */ + #define R_GLCDC_BG_MON_VEN_Msk (0x100UL) /*!< VEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_BG_MON_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GLCDC_BG_MON_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== VEN ========================================================== */ + #define R_GLCDC_GR_VEN_PVEN_Pos (0UL) /*!< PVEN (Bit 0) */ + #define R_GLCDC_GR_VEN_PVEN_Msk (0x1UL) /*!< PVEN (Bitfield-Mask: 0x01) */ +/* ========================================================= FLMRD ========================================================= */ + #define R_GLCDC_GR_FLMRD_RENB_Pos (0UL) /*!< RENB (Bit 0) */ + #define R_GLCDC_GR_FLMRD_RENB_Msk (0x1UL) /*!< RENB (Bitfield-Mask: 0x01) */ +/* ========================================================= FLM1 ========================================================== */ + #define R_GLCDC_GR_FLM1_BSTMD_Pos (0UL) /*!< BSTMD (Bit 0) */ + #define R_GLCDC_GR_FLM1_BSTMD_Msk (0x3UL) /*!< BSTMD (Bitfield-Mask: 0x03) */ +/* ========================================================= FLM2 ========================================================== */ + #define R_GLCDC_GR_FLM2_BASE_Pos (0UL) /*!< BASE (Bit 0) */ + #define R_GLCDC_GR_FLM2_BASE_Msk (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FLM3 ========================================================== */ + #define R_GLCDC_GR_FLM3_LNOFF_Pos (16UL) /*!< LNOFF (Bit 16) */ + #define R_GLCDC_GR_FLM3_LNOFF_Msk (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM5 ========================================================== */ + #define R_GLCDC_GR_FLM5_LNNUM_Pos (16UL) /*!< LNNUM (Bit 16) */ + #define R_GLCDC_GR_FLM5_LNNUM_Msk (0x7ff0000UL) /*!< LNNUM (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_FLM5_DATANUM_Pos (0UL) /*!< DATANUM (Bit 0) */ + #define R_GLCDC_GR_FLM5_DATANUM_Msk (0xffffUL) /*!< DATANUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= FLM6 ========================================================== */ + #define R_GLCDC_GR_FLM6_FORMAT_Pos (28UL) /*!< FORMAT (Bit 28) */ + #define R_GLCDC_GR_FLM6_FORMAT_Msk (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07) */ +/* ========================================================== AB1 ========================================================== */ + #define R_GLCDC_GR_AB1_ARCON_Pos (12UL) /*!< ARCON (Bit 12) */ + #define R_GLCDC_GR_AB1_ARCON_Msk (0x1000UL) /*!< ARCON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Pos (8UL) /*!< ARCDISPON (Bit 8) */ + #define R_GLCDC_GR_AB1_ARCDISPON_Msk (0x100UL) /*!< ARCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Pos (4UL) /*!< GRCDISPON (Bit 4) */ + #define R_GLCDC_GR_AB1_GRCDISPON_Msk (0x10UL) /*!< GRCDISPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_AB1_DISPSEL_Pos (0UL) /*!< DISPSEL (Bit 0) */ + #define R_GLCDC_GR_AB1_DISPSEL_Msk (0x3UL) /*!< DISPSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== AB2 ========================================================== */ + #define R_GLCDC_GR_AB2_GRCVS_Pos (16UL) /*!< GRCVS (Bit 16) */ + #define R_GLCDC_GR_AB2_GRCVS_Msk (0x7ff0000UL) /*!< GRCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB2_GRCVW_Pos (0UL) /*!< GRCVW (Bit 0) */ + #define R_GLCDC_GR_AB2_GRCVW_Msk (0x7ffUL) /*!< GRCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB3 ========================================================== */ + #define R_GLCDC_GR_AB3_GRCHS_Pos (16UL) /*!< GRCHS (Bit 16) */ + #define R_GLCDC_GR_AB3_GRCHS_Msk (0x7ff0000UL) /*!< GRCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB3_GRCHW_Pos (0UL) /*!< GRCHW (Bit 0) */ + #define R_GLCDC_GR_AB3_GRCHW_Msk (0x7ffUL) /*!< GRCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB4 ========================================================== */ + #define R_GLCDC_GR_AB4_ARCVS_Pos (16UL) /*!< ARCVS (Bit 16) */ + #define R_GLCDC_GR_AB4_ARCVS_Msk (0x7ff0000UL) /*!< ARCVS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB4_ARCVW_Pos (0UL) /*!< ARCVW (Bit 0) */ + #define R_GLCDC_GR_AB4_ARCVW_Msk (0x7ffUL) /*!< ARCVW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB5 ========================================================== */ + #define R_GLCDC_GR_AB5_ARCHS_Pos (16UL) /*!< ARCHS (Bit 16) */ + #define R_GLCDC_GR_AB5_ARCHS_Msk (0x7ff0000UL) /*!< ARCHS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_GR_AB5_ARCHW_Pos (0UL) /*!< ARCHW (Bit 0) */ + #define R_GLCDC_GR_AB5_ARCHW_Msk (0x7ffUL) /*!< ARCHW (Bitfield-Mask: 0x7ff) */ +/* ========================================================== AB6 ========================================================== */ + #define R_GLCDC_GR_AB6_ARCCOEF_Pos (16UL) /*!< ARCCOEF (Bit 16) */ + #define R_GLCDC_GR_AB6_ARCCOEF_Msk (0x1ff0000UL) /*!< ARCCOEF (Bitfield-Mask: 0x1ff) */ + #define R_GLCDC_GR_AB6_ARCRATE_Pos (0UL) /*!< ARCRATE (Bit 0) */ + #define R_GLCDC_GR_AB6_ARCRATE_Msk (0xffUL) /*!< ARCRATE (Bitfield-Mask: 0xff) */ +/* ========================================================== AB7 ========================================================== */ + #define R_GLCDC_GR_AB7_ARCDEF_Pos (16UL) /*!< ARCDEF (Bit 16) */ + #define R_GLCDC_GR_AB7_ARCDEF_Msk (0xff0000UL) /*!< ARCDEF (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB7_CKON_Pos (0UL) /*!< CKON (Bit 0) */ + #define R_GLCDC_GR_AB7_CKON_Msk (0x1UL) /*!< CKON (Bitfield-Mask: 0x01) */ +/* ========================================================== AB8 ========================================================== */ + #define R_GLCDC_GR_AB8_CKKG_Pos (16UL) /*!< CKKG (Bit 16) */ + #define R_GLCDC_GR_AB8_CKKG_Msk (0xff0000UL) /*!< CKKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKB_Pos (8UL) /*!< CKKB (Bit 8) */ + #define R_GLCDC_GR_AB8_CKKB_Msk (0xff00UL) /*!< CKKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB8_CKKR_Pos (0UL) /*!< CKKR (Bit 0) */ + #define R_GLCDC_GR_AB8_CKKR_Msk (0xffUL) /*!< CKKR (Bitfield-Mask: 0xff) */ +/* ========================================================== AB9 ========================================================== */ + #define R_GLCDC_GR_AB9_CKA_Pos (24UL) /*!< CKA (Bit 24) */ + #define R_GLCDC_GR_AB9_CKA_Msk (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKG_Pos (16UL) /*!< CKG (Bit 16) */ + #define R_GLCDC_GR_AB9_CKG_Msk (0xff0000UL) /*!< CKG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKB_Pos (8UL) /*!< CKB (Bit 8) */ + #define R_GLCDC_GR_AB9_CKB_Msk (0xff00UL) /*!< CKB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_AB9_CKR_Pos (0UL) /*!< CKR (Bit 0) */ + #define R_GLCDC_GR_AB9_CKR_Msk (0xffUL) /*!< CKR (Bitfield-Mask: 0xff) */ +/* ========================================================= BASE ========================================================== */ + #define R_GLCDC_GR_BASE_G_Pos (16UL) /*!< G (Bit 16) */ + #define R_GLCDC_GR_BASE_G_Msk (0xff0000UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_B_Pos (8UL) /*!< B (Bit 8) */ + #define R_GLCDC_GR_BASE_B_Msk (0xff00UL) /*!< B (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR_BASE_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_GLCDC_GR_BASE_R_Msk (0xffUL) /*!< R (Bitfield-Mask: 0xff) */ +/* ======================================================== CLUTINT ======================================================== */ + #define R_GLCDC_GR_CLUTINT_SEL_Pos (16UL) /*!< SEL (Bit 16) */ + #define R_GLCDC_GR_CLUTINT_SEL_Msk (0x10000UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_CLUTINT_LINE_Pos (0UL) /*!< LINE (Bit 0) */ + #define R_GLCDC_GR_CLUTINT_LINE_Msk (0x7ffUL) /*!< LINE (Bitfield-Mask: 0x7ff) */ +/* ========================================================== MON ========================================================== */ + #define R_GLCDC_GR_MON_UNDFLST_Pos (16UL) /*!< UNDFLST (Bit 16) */ + #define R_GLCDC_GR_MON_UNDFLST_Msk (0x10000UL) /*!< UNDFLST (Bitfield-Mask: 0x01) */ + #define R_GLCDC_GR_MON_ARCST_Pos (0UL) /*!< ARCST (Bit 0) */ + #define R_GLCDC_GR_MON_ARCST_Msk (0x1UL) /*!< ARCST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ GAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= LATCH ========================================================= */ + #define R_GLCDC_GAM_LATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_GAM_LATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ======================================================== GAM_SW ========================================================= */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Pos (0UL) /*!< GAMON (Bit 0) */ + #define R_GLCDC_GAM_GAM_SW_GAMON_Msk (0x1UL) /*!< GAMON (Bitfield-Mask: 0x01) */ +/* ========================================================== LUT ========================================================== */ + #define R_GLCDC_GAM_LUT___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_LUT___Msk (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff) */ +/* ========================================================= AREA ========================================================== */ + #define R_GLCDC_GAM_AREA___Pos (0UL) /*!< _ (Bit 0) */ + #define R_GLCDC_GAM_AREA___Msk (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ OUT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VLATCH ========================================================= */ + #define R_GLCDC_OUT_VLATCH_VEN_Pos (0UL) /*!< VEN (Bit 0) */ + #define R_GLCDC_OUT_VLATCH_VEN_Msk (0x1UL) /*!< VEN (Bitfield-Mask: 0x01) */ +/* ========================================================== SET ========================================================== */ + #define R_GLCDC_OUT_SET_ENDIANON_Pos (28UL) /*!< ENDIANON (Bit 28) */ + #define R_GLCDC_OUT_SET_ENDIANON_Msk (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_SWAPON_Pos (24UL) /*!< SWAPON (Bit 24) */ + #define R_GLCDC_OUT_SET_SWAPON_Msk (0x1000000UL) /*!< SWAPON (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_FORMAT_Pos (12UL) /*!< FORMAT (Bit 12) */ + #define R_GLCDC_OUT_SET_FORMAT_Msk (0x3000UL) /*!< FORMAT (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_FRQSEL_Pos (8UL) /*!< FRQSEL (Bit 8) */ + #define R_GLCDC_OUT_SET_FRQSEL_Msk (0x300UL) /*!< FRQSEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_SET_DIRSEL_Pos (4UL) /*!< DIRSEL (Bit 4) */ + #define R_GLCDC_OUT_SET_DIRSEL_Msk (0x10UL) /*!< DIRSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_SET_PHASE_Pos (0UL) /*!< PHASE (Bit 0) */ + #define R_GLCDC_OUT_SET_PHASE_Msk (0x3UL) /*!< PHASE (Bitfield-Mask: 0x03) */ +/* ======================================================== BRIGHT1 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos (0UL) /*!< BRTG (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk (0x3ffUL) /*!< BRTG (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BRIGHT2 ======================================================== */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos (16UL) /*!< BRTB (Bit 16) */ + #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk (0x3ff0000UL) /*!< BRTB (Bitfield-Mask: 0x3ff) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos (0UL) /*!< BRTR (Bit 0) */ + #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk (0x3ffUL) /*!< BRTR (Bitfield-Mask: 0x3ff) */ +/* ======================================================= CONTRAST ======================================================== */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Pos (16UL) /*!< CONTG (Bit 16) */ + #define R_GLCDC_OUT_CONTRAST_CONTG_Msk (0xff0000UL) /*!< CONTG (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Pos (8UL) /*!< CONTB (Bit 8) */ + #define R_GLCDC_OUT_CONTRAST_CONTB_Msk (0xff00UL) /*!< CONTB (Bitfield-Mask: 0xff) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Pos (0UL) /*!< CONTR (Bit 0) */ + #define R_GLCDC_OUT_CONTRAST_CONTR_Msk (0xffUL) /*!< CONTR (Bitfield-Mask: 0xff) */ +/* ========================================================= PDTHA ========================================================= */ + #define R_GLCDC_OUT_PDTHA_SEL_Pos (20UL) /*!< SEL (Bit 20) */ + #define R_GLCDC_OUT_PDTHA_SEL_Msk (0x300000UL) /*!< SEL (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_FORM_Pos (16UL) /*!< FORM (Bit 16) */ + #define R_GLCDC_OUT_PDTHA_FORM_Msk (0x30000UL) /*!< FORM (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PA_Pos (12UL) /*!< PA (Bit 12) */ + #define R_GLCDC_OUT_PDTHA_PA_Msk (0x3000UL) /*!< PA (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PB_Pos (8UL) /*!< PB (Bit 8) */ + #define R_GLCDC_OUT_PDTHA_PB_Msk (0x300UL) /*!< PB (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PC_Pos (4UL) /*!< PC (Bit 4) */ + #define R_GLCDC_OUT_PDTHA_PC_Msk (0x30UL) /*!< PC (Bitfield-Mask: 0x03) */ + #define R_GLCDC_OUT_PDTHA_PD_Pos (0UL) /*!< PD (Bit 0) */ + #define R_GLCDC_OUT_PDTHA_PD_Msk (0x3UL) /*!< PD (Bitfield-Mask: 0x03) */ +/* ======================================================= CLKPHASE ======================================================== */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos (12UL) /*!< FRONTGAM (Bit 12) */ + #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk (0x1000UL) /*!< FRONTGAM (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos (8UL) /*!< LCDEDGE (Bit 8) */ + #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk (0x100UL) /*!< LCDEDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos (6UL) /*!< TCON0EDGE (Bit 6) */ + #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk (0x40UL) /*!< TCON0EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos (5UL) /*!< TCON1EDGE (Bit 5) */ + #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk (0x20UL) /*!< TCON1EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos (4UL) /*!< TCON2EDGE (Bit 4) */ + #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk (0x10UL) /*!< TCON2EDGE (Bitfield-Mask: 0x01) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos (3UL) /*!< TCON3EDGE (Bit 3) */ + #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk (0x8UL) /*!< TCON3EDGE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ TCON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TIM ========================================================== */ + #define R_GLCDC_TCON_TIM_HALF_Pos (16UL) /*!< HALF (Bit 16) */ + #define R_GLCDC_TCON_TIM_HALF_Msk (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_TIM_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_GLCDC_TCON_TIM_OFFSET_Msk (0x7ffUL) /*!< OFFSET (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA1 ========================================================= */ + #define R_GLCDC_TCON_STVA1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVA1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVA1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVA1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVB1 ========================================================= */ + #define R_GLCDC_TCON_STVB1_VS_Pos (16UL) /*!< VS (Bit 16) */ + #define R_GLCDC_TCON_STVB1_VS_Msk (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STVB1_VW_Pos (0UL) /*!< VW (Bit 0) */ + #define R_GLCDC_TCON_STVB1_VW_Msk (0x7ffUL) /*!< VW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STVA2 ========================================================= */ + #define R_GLCDC_TCON_STVA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STVB2 ========================================================= */ + #define R_GLCDC_TCON_STVB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STVB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STVB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STVB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHA1 ========================================================= */ + #define R_GLCDC_TCON_STHA1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHA1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHA1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHA1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHB1 ========================================================= */ + #define R_GLCDC_TCON_STHB1_HS_Pos (16UL) /*!< HS (Bit 16) */ + #define R_GLCDC_TCON_STHB1_HS_Msk (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff) */ + #define R_GLCDC_TCON_STHB1_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_GLCDC_TCON_STHB1_HW_Msk (0x7ffUL) /*!< HW (Bitfield-Mask: 0x7ff) */ +/* ========================================================= STHA2 ========================================================= */ + #define R_GLCDC_TCON_STHA2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHA2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHA2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHA2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHA2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================= STHB2 ========================================================= */ + #define R_GLCDC_TCON_STHB2_HSSEL_Pos (8UL) /*!< HSSEL (Bit 8) */ + #define R_GLCDC_TCON_STHB2_HSSEL_Msk (0x100UL) /*!< HSSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_INV_Pos (4UL) /*!< INV (Bit 4) */ + #define R_GLCDC_TCON_STHB2_INV_Msk (0x10UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GLCDC_TCON_STHB2_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_GLCDC_TCON_STHB2_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ +/* ========================================================== DE =========================================================== */ + #define R_GLCDC_TCON_DE_INV_Pos (0UL) /*!< INV (Bit 0) */ + #define R_GLCDC_TCON_DE_INV_Msk (0x1UL) /*!< INV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SYSCNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DTCTEN ========================================================= */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos (2UL) /*!< L2UNDFDTC (Bit 2) */ + #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk (0x4UL) /*!< L2UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos (1UL) /*!< L1UNDFDTC (Bit 1) */ + #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk (0x2UL) /*!< L1UNDFDTC (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos (0UL) /*!< VPOSDTC (Bit 0) */ + #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk (0x1UL) /*!< VPOSDTC (Bitfield-Mask: 0x01) */ +/* ========================================================= INTEN ========================================================= */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos (2UL) /*!< L2UNDFINTEN (Bit 2) */ + #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk (0x4UL) /*!< L2UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos (1UL) /*!< L1UNDFINTEN (Bit 1) */ + #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk (0x2UL) /*!< L1UNDFINTEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos (0UL) /*!< VPOSINTEN (Bit 0) */ + #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk (0x1UL) /*!< VPOSINTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STCLR ========================================================= */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos (2UL) /*!< L2UNDFCLR (Bit 2) */ + #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk (0x4UL) /*!< L2UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos (1UL) /*!< L1UNDFCLR (Bit 1) */ + #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk (0x2UL) /*!< L1UNDFCLR (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos (0UL) /*!< VPOSCLR (Bit 0) */ + #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk (0x1UL) /*!< VPOSCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= STMON ========================================================= */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos (2UL) /*!< L2UNDF (Bit 2) */ + #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk (0x4UL) /*!< L2UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos (1UL) /*!< L1UNDF (Bit 1) */ + #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk (0x2UL) /*!< L1UNDF (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Pos (0UL) /*!< VPOS (Bit 0) */ + #define R_GLCDC_SYSCNT_STMON_VPOS_Msk (0x1UL) /*!< VPOS (Bitfield-Mask: 0x01) */ +/* ======================================================= PANEL_CLK ======================================================= */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos (16UL) /*!< VER (Bit 16) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos (12UL) /*!< PIXSEL (Bit 12) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk (0x1000UL) /*!< PIXSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk (0x100UL) /*!< CLKSEL (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos (6UL) /*!< CLKEN (Bit 6) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk (0x40UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos (0UL) /*!< DCDR (Bit 0) */ + #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk (0x3fUL) /*!< DCDR (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DRW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CONTROL ======================================================== */ + #define R_DRW_CONTROL_SPANSTORE_Pos (23UL) /*!< SPANSTORE (Bit 23) */ + #define R_DRW_CONTROL_SPANSTORE_Msk (0x800000UL) /*!< SPANSTORE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_SPANABORT_Pos (22UL) /*!< SPANABORT (Bit 22) */ + #define R_DRW_CONTROL_SPANABORT_Msk (0x400000UL) /*!< SPANABORT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONCD_Pos (21UL) /*!< UNIONCD (Bit 21) */ + #define R_DRW_CONTROL_UNIONCD_Msk (0x200000UL) /*!< UNIONCD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNIONAB_Pos (20UL) /*!< UNIONAB (Bit 20) */ + #define R_DRW_CONTROL_UNIONAB_Msk (0x100000UL) /*!< UNIONAB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION56_Pos (19UL) /*!< UNION56 (Bit 19) */ + #define R_DRW_CONTROL_UNION56_Msk (0x80000UL) /*!< UNION56 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION34_Pos (18UL) /*!< UNION34 (Bit 18) */ + #define R_DRW_CONTROL_UNION34_Msk (0x40000UL) /*!< UNION34 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_UNION12_Pos (17UL) /*!< UNION12 (Bit 17) */ + #define R_DRW_CONTROL_UNION12_Msk (0x20000UL) /*!< UNION12 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND2ENABLE_Pos (16UL) /*!< BAND2ENABLE (Bit 16) */ + #define R_DRW_CONTROL_BAND2ENABLE_Msk (0x10000UL) /*!< BAND2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_BAND1ENABLE_Pos (15UL) /*!< BAND1ENABLE (Bit 15) */ + #define R_DRW_CONTROL_BAND1ENABLE_Msk (0x8000UL) /*!< BAND1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Pos (14UL) /*!< LIM6THRESHOLD (Bit 14) */ + #define R_DRW_CONTROL_LIM6THRESHOLD_Msk (0x4000UL) /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Pos (13UL) /*!< LIM5THRESHOLD (Bit 13) */ + #define R_DRW_CONTROL_LIM5THRESHOLD_Msk (0x2000UL) /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Pos (12UL) /*!< LIM4THRESHOLD (Bit 12) */ + #define R_DRW_CONTROL_LIM4THRESHOLD_Msk (0x1000UL) /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Pos (11UL) /*!< LIM3THRESHOLD (Bit 11) */ + #define R_DRW_CONTROL_LIM3THRESHOLD_Msk (0x800UL) /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Pos (10UL) /*!< LIM2THRESHOLD (Bit 10) */ + #define R_DRW_CONTROL_LIM2THRESHOLD_Msk (0x400UL) /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Pos (9UL) /*!< LIM1THRESHOLD (Bit 9) */ + #define R_DRW_CONTROL_LIM1THRESHOLD_Msk (0x200UL) /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Pos (8UL) /*!< QUAD3ENABLE (Bit 8) */ + #define R_DRW_CONTROL_QUAD3ENABLE_Msk (0x100UL) /*!< QUAD3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Pos (7UL) /*!< QUAD2ENABLE (Bit 7) */ + #define R_DRW_CONTROL_QUAD2ENABLE_Msk (0x80UL) /*!< QUAD2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Pos (6UL) /*!< QUAD1ENABLE (Bit 6) */ + #define R_DRW_CONTROL_QUAD1ENABLE_Msk (0x40UL) /*!< QUAD1ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM6ENABLE_Pos (5UL) /*!< LIM6ENABLE (Bit 5) */ + #define R_DRW_CONTROL_LIM6ENABLE_Msk (0x20UL) /*!< LIM6ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM5ENABLE_Pos (4UL) /*!< LIM5ENABLE (Bit 4) */ + #define R_DRW_CONTROL_LIM5ENABLE_Msk (0x10UL) /*!< LIM5ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM4ENABLE_Pos (3UL) /*!< LIM4ENABLE (Bit 3) */ + #define R_DRW_CONTROL_LIM4ENABLE_Msk (0x8UL) /*!< LIM4ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM3ENABLE_Pos (2UL) /*!< LIM3ENABLE (Bit 2) */ + #define R_DRW_CONTROL_LIM3ENABLE_Msk (0x4UL) /*!< LIM3ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM2ENABLE_Pos (1UL) /*!< LIM2ENABLE (Bit 1) */ + #define R_DRW_CONTROL_LIM2ENABLE_Msk (0x2UL) /*!< LIM2ENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL_LIM1ENABLE_Pos (0UL) /*!< LIM1ENABLE (Bit 0) */ + #define R_DRW_CONTROL_LIM1ENABLE_Msk (0x1UL) /*!< LIM1ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================= CONTROL2 ======================================================== */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos (30UL) /*!< RLEPIXELWIDTH (Bit 30) */ + #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_BDIA_Pos (29UL) /*!< BDIA (Bit 29) */ + #define R_DRW_CONTROL2_BDIA_Msk (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSIA_Pos (28UL) /*!< BSIA (Bit 28) */ + #define R_DRW_CONTROL2_BSIA_Msk (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Pos (27UL) /*!< CLUTFORMAT (Bit 27) */ + #define R_DRW_CONTROL2_CLUTFORMAT_Msk (0x8000000UL) /*!< CLUTFORMAT (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Pos (26UL) /*!< COLKEYENABLE (Bit 26) */ + #define R_DRW_CONTROL2_COLKEYENABLE_Msk (0x4000000UL) /*!< COLKEYENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_CLUTENABLE_Pos (25UL) /*!< CLUTENABLE (Bit 25) */ + #define R_DRW_CONTROL2_CLUTENABLE_Msk (0x2000000UL) /*!< CLUTENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_RLEENABLE_Pos (24UL) /*!< RLEENABLE (Bit 24) */ + #define R_DRW_CONTROL2_RLEENABLE_Msk (0x1000000UL) /*!< RLEENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEALPHA_Pos (22UL) /*!< WRITEALPHA (Bit 22) */ + #define R_DRW_CONTROL2_WRITEALPHA_Msk (0xc00000UL) /*!< WRITEALPHA (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Pos (20UL) /*!< WRITEFORMAT10 (Bit 20) */ + #define R_DRW_CONTROL2_WRITEFORMAT10_Msk (0x300000UL) /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_READFORMAT10_Pos (18UL) /*!< READFORMAT10 (Bit 18) */ + #define R_DRW_CONTROL2_READFORMAT10_Msk (0xc0000UL) /*!< READFORMAT10 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos (17UL) /*!< TEXTUREFILTERY (Bit 17) */ + #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk (0x20000UL) /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos (16UL) /*!< TEXTUREFILTERX (Bit 16) */ + #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk (0x10000UL) /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos (15UL) /*!< TEXTURECLAMPY (Bit 15) */ + #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk (0x8000UL) /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos (14UL) /*!< TEXTURECLAMPX (Bit 14) */ + #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk (0x4000UL) /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BC2_Pos (13UL) /*!< BC2 (Bit 13) */ + #define R_DRW_CONTROL2_BC2_Msk (0x2000UL) /*!< BC2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDI_Pos (12UL) /*!< BDI (Bit 12) */ + #define R_DRW_CONTROL2_BDI_Msk (0x1000UL) /*!< BDI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSI_Pos (11UL) /*!< BSI (Bit 11) */ + #define R_DRW_CONTROL2_BSI_Msk (0x800UL) /*!< BSI (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDF_Pos (10UL) /*!< BDF (Bit 10) */ + #define R_DRW_CONTROL2_BDF_Msk (0x400UL) /*!< BDF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSF_Pos (9UL) /*!< BSF (Bit 9) */ + #define R_DRW_CONTROL2_BSF_Msk (0x200UL) /*!< BSF (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Pos (8UL) /*!< WRITEFORMAT2 (Bit 8) */ + #define R_DRW_CONTROL2_WRITEFORMAT2_Msk (0x100UL) /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BDFA_Pos (7UL) /*!< BDFA (Bit 7) */ + #define R_DRW_CONTROL2_BDFA_Msk (0x80UL) /*!< BDFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_BSFA_Pos (6UL) /*!< BSFA (Bit 6) */ + #define R_DRW_CONTROL2_BSFA_Msk (0x40UL) /*!< BSFA (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_READFORMAT32_Pos (4UL) /*!< READFORMAT32 (Bit 4) */ + #define R_DRW_CONTROL2_READFORMAT32_Msk (0x30UL) /*!< READFORMAT32 (Bitfield-Mask: 0x03) */ + #define R_DRW_CONTROL2_USEACB_Pos (3UL) /*!< USEACB (Bit 3) */ + #define R_DRW_CONTROL2_USEACB_Msk (0x8UL) /*!< USEACB (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos (2UL) /*!< PATTERNSOURCEL5 (Bit 2) */ + #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk (0x4UL) /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Pos (1UL) /*!< TEXTUREENABLE (Bit 1) */ + #define R_DRW_CONTROL2_TEXTUREENABLE_Msk (0x2UL) /*!< TEXTUREENABLE (Bitfield-Mask: 0x01) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Pos (0UL) /*!< PATTERNENABLE (Bit 0) */ + #define R_DRW_CONTROL2_PATTERNENABLE_Msk (0x1UL) /*!< PATTERNENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== IRQCTL ========================================================= */ + #define R_DRW_IRQCTL_BUSIRQCLR_Pos (5UL) /*!< BUSIRQCLR (Bit 5) */ + #define R_DRW_IRQCTL_BUSIRQCLR_Msk (0x20UL) /*!< BUSIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_BUSIRQEN_Pos (4UL) /*!< BUSIRQEN (Bit 4) */ + #define R_DRW_IRQCTL_BUSIRQEN_Msk (0x10UL) /*!< BUSIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Pos (3UL) /*!< DLISTIRQCLR (Bit 3) */ + #define R_DRW_IRQCTL_DLISTIRQCLR_Msk (0x8UL) /*!< DLISTIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Pos (2UL) /*!< ENUMIRQCLR (Bit 2) */ + #define R_DRW_IRQCTL_ENUMIRQCLR_Msk (0x4UL) /*!< ENUMIRQCLR (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Pos (1UL) /*!< DLISTIRQEN (Bit 1) */ + #define R_DRW_IRQCTL_DLISTIRQEN_Msk (0x2UL) /*!< DLISTIRQEN (Bitfield-Mask: 0x01) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Pos (0UL) /*!< ENUMIRQEN (Bit 0) */ + #define R_DRW_IRQCTL_ENUMIRQEN_Msk (0x1UL) /*!< ENUMIRQEN (Bitfield-Mask: 0x01) */ +/* ======================================================= CACHECTL ======================================================== */ + #define R_DRW_CACHECTL_CFLUSHTX_Pos (3UL) /*!< CFLUSHTX (Bit 3) */ + #define R_DRW_CACHECTL_CFLUSHTX_Msk (0x8UL) /*!< CFLUSHTX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLETX_Pos (2UL) /*!< CENABLETX (Bit 2) */ + #define R_DRW_CACHECTL_CENABLETX_Msk (0x4UL) /*!< CENABLETX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CFLUSHFX_Pos (1UL) /*!< CFLUSHFX (Bit 1) */ + #define R_DRW_CACHECTL_CFLUSHFX_Msk (0x2UL) /*!< CFLUSHFX (Bitfield-Mask: 0x01) */ + #define R_DRW_CACHECTL_CENABLEFX_Pos (0UL) /*!< CENABLEFX (Bit 0) */ + #define R_DRW_CACHECTL_CENABLEFX_Msk (0x1UL) /*!< CENABLEFX (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_DRW_STATUS_BUSERRMDL_Pos (10UL) /*!< BUSERRMDL (Bit 10) */ + #define R_DRW_STATUS_BUSERRMDL_Msk (0x400UL) /*!< BUSERRMDL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Pos (9UL) /*!< BUSERRMTXMRL (Bit 9) */ + #define R_DRW_STATUS_BUSERRMTXMRL_Msk (0x200UL) /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSERRMFB_Pos (8UL) /*!< BUSERRMFB (Bit 8) */ + #define R_DRW_STATUS_BUSERRMFB_Msk (0x100UL) /*!< BUSERRMFB (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSIRQ_Pos (6UL) /*!< BUSIRQ (Bit 6) */ + #define R_DRW_STATUS_BUSIRQ_Msk (0x40UL) /*!< BUSIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTIRQ_Pos (5UL) /*!< DLISTIRQ (Bit 5) */ + #define R_DRW_STATUS_DLISTIRQ_Msk (0x20UL) /*!< DLISTIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_ENUMIRQ_Pos (4UL) /*!< ENUMIRQ (Bit 4) */ + #define R_DRW_STATUS_ENUMIRQ_Msk (0x10UL) /*!< ENUMIRQ (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_DLISTACTIVE_Pos (3UL) /*!< DLISTACTIVE (Bit 3) */ + #define R_DRW_STATUS_DLISTACTIVE_Msk (0x8UL) /*!< DLISTACTIVE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_CACHEDIRTY_Pos (2UL) /*!< CACHEDIRTY (Bit 2) */ + #define R_DRW_STATUS_CACHEDIRTY_Msk (0x4UL) /*!< CACHEDIRTY (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYWRITE_Pos (1UL) /*!< BUSYWRITE (Bit 1) */ + #define R_DRW_STATUS_BUSYWRITE_Msk (0x2UL) /*!< BUSYWRITE (Bitfield-Mask: 0x01) */ + #define R_DRW_STATUS_BUSYENUM_Pos (0UL) /*!< BUSYENUM (Bit 0) */ + #define R_DRW_STATUS_BUSYENUM_Msk (0x1UL) /*!< BUSYENUM (Bitfield-Mask: 0x01) */ +/* ====================================================== HWREVISION ======================================================= */ + #define R_DRW_HWREVISION_ACBLEND_Pos (27UL) /*!< ACBLEND (Bit 27) */ + #define R_DRW_HWREVISION_ACBLEND_Msk (0x8000000UL) /*!< ACBLEND (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_COLORKEY_Pos (25UL) /*!< COLORKEY (Bit 25) */ + #define R_DRW_HWREVISION_COLORKEY_Msk (0x2000000UL) /*!< COLORKEY (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLUT256_Pos (24UL) /*!< TEXCLUT256 (Bit 24) */ + #define R_DRW_HWREVISION_TEXCLUT256_Msk (0x1000000UL) /*!< TEXCLUT256 (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_RLEUNIT_Pos (23UL) /*!< RLEUNIT (Bit 23) */ + #define R_DRW_HWREVISION_RLEUNIT_Msk (0x800000UL) /*!< RLEUNIT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TEXCLU_Pos (21UL) /*!< TEXCLU (Bit 21) */ + #define R_DRW_HWREVISION_TEXCLU_Msk (0x200000UL) /*!< TEXCLU (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_PERFCOUNT_Pos (20UL) /*!< PERFCOUNT (Bit 20) */ + #define R_DRW_HWREVISION_PERFCOUNT_Msk (0x100000UL) /*!< PERFCOUNT (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_TXCACHE_Pos (19UL) /*!< TXCACHE (Bit 19) */ + #define R_DRW_HWREVISION_TXCACHE_Msk (0x80000UL) /*!< TXCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_FBCACHE_Pos (18UL) /*!< FBCACHE (Bit 18) */ + #define R_DRW_HWREVISION_FBCACHE_Msk (0x40000UL) /*!< FBCACHE (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_DLR_Pos (17UL) /*!< DLR (Bit 17) */ + #define R_DRW_HWREVISION_DLR_Msk (0x20000UL) /*!< DLR (Bitfield-Mask: 0x01) */ + #define R_DRW_HWREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_DRW_HWREVISION_REV_Msk (0xfffUL) /*!< REV (Bitfield-Mask: 0xfff) */ +/* ======================================================== COLOR1 ========================================================= */ + #define R_DRW_COLOR1_COLOR1A_Pos (24UL) /*!< COLOR1A (Bit 24) */ + #define R_DRW_COLOR1_COLOR1A_Msk (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1R_Pos (16UL) /*!< COLOR1R (Bit 16) */ + #define R_DRW_COLOR1_COLOR1R_Msk (0xff0000UL) /*!< COLOR1R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1G_Pos (8UL) /*!< COLOR1G (Bit 8) */ + #define R_DRW_COLOR1_COLOR1G_Msk (0xff00UL) /*!< COLOR1G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR1_COLOR1B_Pos (0UL) /*!< COLOR1B (Bit 0) */ + #define R_DRW_COLOR1_COLOR1B_Msk (0xffUL) /*!< COLOR1B (Bitfield-Mask: 0xff) */ +/* ======================================================== COLOR2 ========================================================= */ + #define R_DRW_COLOR2_COLOR2A_Pos (24UL) /*!< COLOR2A (Bit 24) */ + #define R_DRW_COLOR2_COLOR2A_Msk (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2R_Pos (16UL) /*!< COLOR2R (Bit 16) */ + #define R_DRW_COLOR2_COLOR2R_Msk (0xff0000UL) /*!< COLOR2R (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2G_Pos (8UL) /*!< COLOR2G (Bit 8) */ + #define R_DRW_COLOR2_COLOR2G_Msk (0xff00UL) /*!< COLOR2G (Bitfield-Mask: 0xff) */ + #define R_DRW_COLOR2_COLOR2B_Pos (0UL) /*!< COLOR2B (Bit 0) */ + #define R_DRW_COLOR2_COLOR2B_Msk (0xffUL) /*!< COLOR2B (Bitfield-Mask: 0xff) */ +/* ======================================================== PATTERN ======================================================== */ + #define R_DRW_PATTERN_PATTERN_Pos (0UL) /*!< PATTERN (Bit 0) */ + #define R_DRW_PATTERN_PATTERN_Msk (0xffUL) /*!< PATTERN (Bitfield-Mask: 0xff) */ +/* ======================================================== L1START ======================================================== */ + #define R_DRW_L1START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L1START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2START ======================================================== */ + #define R_DRW_L2START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L2START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3START ======================================================== */ + #define R_DRW_L3START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L3START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4START ======================================================== */ + #define R_DRW_L4START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L4START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5START ======================================================== */ + #define R_DRW_L5START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L5START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6START ======================================================== */ + #define R_DRW_L6START_LSTART_Pos (0UL) /*!< LSTART (Bit 0) */ + #define R_DRW_L6START_LSTART_Msk (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1XADD ========================================================= */ + #define R_DRW_L1XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L1XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2XADD ========================================================= */ + #define R_DRW_L2XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L2XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3XADD ========================================================= */ + #define R_DRW_L3XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L3XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4XADD ========================================================= */ + #define R_DRW_L4XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L4XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5XADD ========================================================= */ + #define R_DRW_L5XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L5XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6XADD ========================================================= */ + #define R_DRW_L6XADD_LXADD_Pos (0UL) /*!< LXADD (Bit 0) */ + #define R_DRW_L6XADD_LXADD_Msk (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1YADD ========================================================= */ + #define R_DRW_L1YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L1YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2YADD ========================================================= */ + #define R_DRW_L2YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L2YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L3YADD ========================================================= */ + #define R_DRW_L3YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L3YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L4YADD ========================================================= */ + #define R_DRW_L4YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L4YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L5YADD ========================================================= */ + #define R_DRW_L5YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L5YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L6YADD ========================================================= */ + #define R_DRW_L6YADD_LYADD_Pos (0UL) /*!< LYADD (Bit 0) */ + #define R_DRW_L6YADD_LYADD_Msk (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L1BAND ========================================================= */ + #define R_DRW_L1BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L1BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== L2BAND ========================================================= */ + #define R_DRW_L2BAND_LBAND_Pos (0UL) /*!< LBAND (Bit 0) */ + #define R_DRW_L2BAND_LBAND_Msk (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXORIGIN ======================================================= */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Pos (0UL) /*!< TEXORIGIN (Bit 0) */ + #define R_DRW_TEXORIGIN_TEXORIGIN_Msk (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TEXPITCH ======================================================== */ + #define R_DRW_TEXPITCH_TEXPITCH_Pos (0UL) /*!< TEXPITCH (Bit 0) */ + #define R_DRW_TEXPITCH_TEXPITCH_Msk (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TEXMASK ======================================================== */ + #define R_DRW_TEXMASK_TEXVMASK_Pos (11UL) /*!< TEXVMASK (Bit 11) */ + #define R_DRW_TEXMASK_TEXVMASK_Msk (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff) */ + #define R_DRW_TEXMASK_TEXUMASK_Pos (0UL) /*!< TEXUMASK (Bit 0) */ + #define R_DRW_TEXMASK_TEXUMASK_Msk (0x7ffUL) /*!< TEXUMASK (Bitfield-Mask: 0x7ff) */ +/* ======================================================== LUSTART ======================================================== */ + #define R_DRW_LUSTART_LUSTART_Pos (0UL) /*!< LUSTART (Bit 0) */ + #define R_DRW_LUSTART_LUSTART_Msk (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUXADD ========================================================= */ + #define R_DRW_LUXADD_LUXADD_Pos (0UL) /*!< LUXADD (Bit 0) */ + #define R_DRW_LUXADD_LUXADD_Msk (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LUYADD ========================================================= */ + #define R_DRW_LUYADD_LUYADD_Pos (0UL) /*!< LUYADD (Bit 0) */ + #define R_DRW_LUYADD_LUYADD_Msk (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTI ======================================================== */ + #define R_DRW_LVSTARTI_LVSTARTI_Pos (0UL) /*!< LVSTARTI (Bit 0) */ + #define R_DRW_LVSTARTI_LVSTARTI_Msk (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVSTARTF ======================================================== */ + #define R_DRW_LVSTARTF_LVSTARTF_Pos (0UL) /*!< LVSTARTF (Bit 0) */ + #define R_DRW_LVSTARTF_LVSTARTF_Msk (0xffffUL) /*!< LVSTARTF (Bitfield-Mask: 0xffff) */ +/* ======================================================== LVXADDI ======================================================== */ + #define R_DRW_LVXADDI_LVXADDI_Pos (0UL) /*!< LVXADDI (Bit 0) */ + #define R_DRW_LVXADDI_LVXADDI_Msk (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LVYADDI ======================================================== */ + #define R_DRW_LVYADDI_LVYADDI_Pos (0UL) /*!< LVYADDI (Bit 0) */ + #define R_DRW_LVYADDI_LVYADDI_Msk (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= LVYXADDF ======================================================== */ + #define R_DRW_LVYXADDF_LVYADDF_Pos (16UL) /*!< LVYADDF (Bit 16) */ + #define R_DRW_LVYXADDF_LVYADDF_Msk (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff) */ + #define R_DRW_LVYXADDF_LVXADDF_Pos (0UL) /*!< LVXADDF (Bit 0) */ + #define R_DRW_LVYXADDF_LVXADDF_Msk (0xffffUL) /*!< LVXADDF (Bitfield-Mask: 0xffff) */ +/* ======================================================= TEXCLADDR ======================================================= */ + #define R_DRW_TEXCLADDR_CLADDR_Pos (0UL) /*!< CLADDR (Bit 0) */ + #define R_DRW_TEXCLADDR_CLADDR_Msk (0xffUL) /*!< CLADDR (Bitfield-Mask: 0xff) */ +/* ======================================================= TEXCLDATA ======================================================= */ + #define R_DRW_TEXCLDATA_CLDATA_Pos (0UL) /*!< CLDATA (Bit 0) */ + #define R_DRW_TEXCLDATA_CLDATA_Msk (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TEXCLOFFSET ====================================================== */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos (0UL) /*!< CLOFFSET (Bit 0) */ + #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk (0xffUL) /*!< CLOFFSET (Bitfield-Mask: 0xff) */ +/* ======================================================== COLKEY ========================================================= */ + #define R_DRW_COLKEY_COLKEYR_Pos (16UL) /*!< COLKEYR (Bit 16) */ + #define R_DRW_COLKEY_COLKEYR_Msk (0xff0000UL) /*!< COLKEYR (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYG_Pos (8UL) /*!< COLKEYG (Bit 8) */ + #define R_DRW_COLKEY_COLKEYG_Msk (0xff00UL) /*!< COLKEYG (Bitfield-Mask: 0xff) */ + #define R_DRW_COLKEY_COLKEYB_Pos (0UL) /*!< COLKEYB (Bit 0) */ + #define R_DRW_COLKEY_COLKEYB_Msk (0xffUL) /*!< COLKEYB (Bitfield-Mask: 0xff) */ +/* ========================================================= SIZE ========================================================== */ + #define R_DRW_SIZE_SIZEY_Pos (16UL) /*!< SIZEY (Bit 16) */ + #define R_DRW_SIZE_SIZEY_Msk (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff) */ + #define R_DRW_SIZE_SIZEX_Pos (0UL) /*!< SIZEX (Bit 0) */ + #define R_DRW_SIZE_SIZEX_Msk (0xffffUL) /*!< SIZEX (Bitfield-Mask: 0xffff) */ +/* ========================================================= PITCH ========================================================= */ + #define R_DRW_PITCH_SSD_Pos (16UL) /*!< SSD (Bit 16) */ + #define R_DRW_PITCH_SSD_Msk (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff) */ + #define R_DRW_PITCH_PITCH_Pos (0UL) /*!< PITCH (Bit 0) */ + #define R_DRW_PITCH_PITCH_Msk (0xffffUL) /*!< PITCH (Bitfield-Mask: 0xffff) */ +/* ======================================================== ORIGIN ========================================================= */ + #define R_DRW_ORIGIN_ORIGIN_Pos (0UL) /*!< ORIGIN (Bit 0) */ + #define R_DRW_ORIGIN_ORIGIN_Msk (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLISTSTART ======================================================= */ + #define R_DRW_DLISTSTART_DLISTSTART_Pos (0UL) /*!< DLISTSTART (Bit 0) */ + #define R_DRW_DLISTSTART_DLISTSTART_Msk (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFTRIGGER ====================================================== */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos (16UL) /*!< PERFTRIGGER2 (Bit 16) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos (0UL) /*!< PERFTRIGGER1 (Bit 0) */ + #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk (0xffffUL) /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff) */ +/* ====================================================== PERFCOUNT1 ======================================================= */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PERFCOUNT2 ======================================================= */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos (0UL) /*!< PERFCOUNT (Bit 0) */ + #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SYSR ========================================================== */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYSR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYSR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYSR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYSR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYSR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYSR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYSR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYSR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYSR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYSR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ========================================================= SYIPR ========================================================= */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Pos (17UL) /*!< GENDN (Bit 17) */ + #define R_ETHERC_EPTPC_SYIPR_GENDN_Msk (0x20000UL) /*!< GENDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Pos (16UL) /*!< RESDN (Bit 16) */ + #define R_ETHERC_EPTPC_SYIPR_RESDN_Msk (0x10000UL) /*!< RESDN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Pos (14UL) /*!< INFABT (Bit 14) */ + #define R_ETHERC_EPTPC_SYIPR_INFABT_Msk (0x4000UL) /*!< INFABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Pos (12UL) /*!< RECLP (Bit 12) */ + #define R_ETHERC_EPTPC_SYIPR_RECLP_Msk (0x1000UL) /*!< RECLP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Pos (6UL) /*!< DRQOVR (Bit 6) */ + #define R_ETHERC_EPTPC_SYIPR_DRQOVR_Msk (0x40UL) /*!< DRQOVR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Pos (5UL) /*!< INTDEV (Bit 5) */ + #define R_ETHERC_EPTPC_SYIPR_INTDEV_Msk (0x20UL) /*!< INTDEV (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Pos (4UL) /*!< DRPTO (Bit 4) */ + #define R_ETHERC_EPTPC_SYIPR_DRPTO_Msk (0x10UL) /*!< DRPTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Pos (2UL) /*!< MPDUD (Bit 2) */ + #define R_ETHERC_EPTPC_SYIPR_MPDUD_Msk (0x4UL) /*!< MPDUD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Pos (1UL) /*!< INTCHG (Bit 1) */ + #define R_ETHERC_EPTPC_SYIPR_INTCHG_Msk (0x2UL) /*!< INTCHG (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Pos (0UL) /*!< OFMUD (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPR_OFMUD_Msk (0x1UL) /*!< OFMUD (Bitfield-Mask: 0x01) */ +/* ======================================================== SYMACRU ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Pos (0UL) /*!< SYMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRU_SYMACRU_Msk (0xffffffUL) /*!< SYMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SYMACRL ======================================================== */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Pos (0UL) /*!< SYMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYMACRL_SYMACRL_Msk (0xffffffUL) /*!< SYMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================= SYLLCCTLR ======================================================= */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Pos (0UL) /*!< CTL (Bit 0) */ + #define R_ETHERC_EPTPC_SYLLCCTLR_CTL_Msk (0xffUL) /*!< CTL (Bitfield-Mask: 0xff) */ +/* ======================================================= SYIPADDRR ======================================================= */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Pos (0UL) /*!< SYIPADDRR (Bit 0) */ + #define R_ETHERC_EPTPC_SYIPADDRR_SYIPADDRR_Msk (0xffffffffUL) /*!< SYIPADDRR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYSPVRR ======================================================== */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Pos (4UL) /*!< TRSP (Bit 4) */ + #define R_ETHERC_EPTPC_SYSPVRR_TRSP_Msk (0xf0UL) /*!< TRSP (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_ETHERC_EPTPC_SYSPVRR_VER_Msk (0xfUL) /*!< VER (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYDOMR ========================================================= */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Pos (0UL) /*!< DNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYDOMR_DNUM_Msk (0xffUL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ========================================================= ANFR ========================================================== */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_ANFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_ANFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_ANFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_ANFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Pos (5UL) /*!< FLAG5 (Bit 5) */ + #define R_ETHERC_EPTPC_ANFR_FLAG5_Msk (0x20UL) /*!< FLAG5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Pos (4UL) /*!< FLAG4 (Bit 4) */ + #define R_ETHERC_EPTPC_ANFR_FLAG4_Msk (0x10UL) /*!< FLAG4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Pos (3UL) /*!< FLAG3 (Bit 3) */ + #define R_ETHERC_EPTPC_ANFR_FLAG3_Msk (0x8UL) /*!< FLAG3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Pos (2UL) /*!< FLAG2 (Bit 2) */ + #define R_ETHERC_EPTPC_ANFR_FLAG2_Msk (0x4UL) /*!< FLAG2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Pos (1UL) /*!< FLAG1 (Bit 1) */ + #define R_ETHERC_EPTPC_ANFR_FLAG1_Msk (0x2UL) /*!< FLAG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Pos (0UL) /*!< FLAG0 (Bit 0) */ + #define R_ETHERC_EPTPC_ANFR_FLAG0_Msk (0x1UL) /*!< FLAG0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SYNFR ========================================================= */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_SYNFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRQFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRQFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ +/* ======================================================== DYRPFR ========================================================= */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Pos (14UL) /*!< FLAG14 (Bit 14) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG14_Msk (0x4000UL) /*!< FLAG14 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Pos (13UL) /*!< FLAG13 (Bit 13) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG13_Msk (0x2000UL) /*!< FLAG13 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Pos (10UL) /*!< FLAG10 (Bit 10) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG10_Msk (0x400UL) /*!< FLAG10 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Pos (9UL) /*!< FLAG9 (Bit 9) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG9_Msk (0x200UL) /*!< FLAG9 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Pos (8UL) /*!< FLAG8 (Bit 8) */ + #define R_ETHERC_EPTPC_DYRPFR_FLAG8_Msk (0x100UL) /*!< FLAG8 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYCIDRU ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Pos (0UL) /*!< SYCIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRU_SYCIDRU_Msk (0xffffffffUL) /*!< SYCIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYCIDRL ======================================================== */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Pos (0UL) /*!< SYCIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_SYCIDRL_SYCIDRL_Msk (0xffffffffUL) /*!< SYCIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SYPNUMR ======================================================== */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_SYPNUMR_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYRVLDR ======================================================== */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Pos (2UL) /*!< ANUP (Bit 2) */ + #define R_ETHERC_EPTPC_SYRVLDR_ANUP_Msk (0x4UL) /*!< ANUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Pos (1UL) /*!< STUP (Bit 1) */ + #define R_ETHERC_EPTPC_SYRVLDR_STUP_Msk (0x2UL) /*!< STUP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Pos (0UL) /*!< BMUP (Bit 0) */ + #define R_ETHERC_EPTPC_SYRVLDR_BMUP_Msk (0x1UL) /*!< BMUP (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL1R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Pos (30UL) /*!< PDFUP2 (Bit 30) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP2_Msk (0x40000000UL) /*!< PDFUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Pos (29UL) /*!< PDFUP1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP1_Msk (0x20000000UL) /*!< PDFUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Pos (28UL) /*!< PDFUP0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDFUP0_Msk (0x10000000UL) /*!< PDFUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Pos (26UL) /*!< PDRP2 (Bit 26) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP2_Msk (0x4000000UL) /*!< PDRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Pos (25UL) /*!< PDRP1 (Bit 25) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP1_Msk (0x2000000UL) /*!< PDRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Pos (24UL) /*!< PDRP0 (Bit 24) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRP0_Msk (0x1000000UL) /*!< PDRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Pos (22UL) /*!< PDRQ2 (Bit 22) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ2_Msk (0x400000UL) /*!< PDRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Pos (21UL) /*!< PDRQ1 (Bit 21) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ1_Msk (0x200000UL) /*!< PDRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Pos (20UL) /*!< PDRQ0 (Bit 20) */ + #define R_ETHERC_EPTPC_SYRFL1R_PDRQ0_Msk (0x100000UL) /*!< PDRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Pos (18UL) /*!< DRP2 (Bit 18) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP2_Msk (0x40000UL) /*!< DRP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Pos (17UL) /*!< DRP1 (Bit 17) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP1_Msk (0x20000UL) /*!< DRP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Pos (16UL) /*!< DRP0 (Bit 16) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRP0_Msk (0x10000UL) /*!< DRP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Pos (14UL) /*!< DRQ2 (Bit 14) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ2_Msk (0x4000UL) /*!< DRQ2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Pos (13UL) /*!< DRQ1 (Bit 13) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ1_Msk (0x2000UL) /*!< DRQ1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Pos (12UL) /*!< DRQ0 (Bit 12) */ + #define R_ETHERC_EPTPC_SYRFL1R_DRQ0_Msk (0x1000UL) /*!< DRQ0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Pos (10UL) /*!< FUP2 (Bit 10) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP2_Msk (0x400UL) /*!< FUP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Pos (9UL) /*!< FUP1 (Bit 9) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP1_Msk (0x200UL) /*!< FUP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Pos (8UL) /*!< FUP0 (Bit 8) */ + #define R_ETHERC_EPTPC_SYRFL1R_FUP0_Msk (0x100UL) /*!< FUP0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Pos (6UL) /*!< SYNC2 (Bit 6) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC2_Msk (0x40UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Pos (5UL) /*!< SYNC1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC1_Msk (0x20UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Pos (4UL) /*!< SYNC0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL1R_SYNC0_Msk (0x10UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Pos (1UL) /*!< ANCE1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE1_Msk (0x2UL) /*!< ANCE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Pos (0UL) /*!< ANCE0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL1R_ANCE0_Msk (0x1UL) /*!< ANCE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYRFL2R ======================================================== */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Pos (29UL) /*!< ILL1 (Bit 29) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL1_Msk (0x20000000UL) /*!< ILL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Pos (28UL) /*!< ILL0 (Bit 28) */ + #define R_ETHERC_EPTPC_SYRFL2R_ILL0_Msk (0x10000000UL) /*!< ILL0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Pos (5UL) /*!< SIG1 (Bit 5) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG1_Msk (0x20UL) /*!< SIG1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Pos (4UL) /*!< SIG0 (Bit 4) */ + #define R_ETHERC_EPTPC_SYRFL2R_SIG0_Msk (0x10UL) /*!< SIG0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Pos (1UL) /*!< MAN1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN1_Msk (0x2UL) /*!< MAN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Pos (0UL) /*!< MAN0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYRFL2R_MAN0_Msk (0x1UL) /*!< MAN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SYTRENR ======================================================== */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Pos (12UL) /*!< PDRQ (Bit 12) */ + #define R_ETHERC_EPTPC_SYTRENR_PDRQ_Msk (0x1000UL) /*!< PDRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Pos (8UL) /*!< DRQ (Bit 8) */ + #define R_ETHERC_EPTPC_SYTRENR_DRQ_Msk (0x100UL) /*!< DRQ (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Pos (4UL) /*!< SYNC (Bit 4) */ + #define R_ETHERC_EPTPC_SYTRENR_SYNC_Msk (0x10UL) /*!< SYNC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTRENR_ANCE_Msk (0x1UL) /*!< ANCE (Bitfield-Mask: 0x01) */ +/* ======================================================== MTCIDU ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Pos (0UL) /*!< MTCIDU (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDU_MTCIDU_Msk (0xffffffffUL) /*!< MTCIDU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MTCIDL ========================================================= */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Pos (0UL) /*!< MTCIDL (Bit 0) */ + #define R_ETHERC_EPTPC_MTCIDL_MTCIDL_Msk (0xffffffffUL) /*!< MTCIDL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MTPID ========================================================= */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Pos (0UL) /*!< PNUM (Bit 0) */ + #define R_ETHERC_EPTPC_MTPID_PNUM_Msk (0xffffUL) /*!< PNUM (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYTLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Pos (16UL) /*!< DREQ (Bit 16) */ + #define R_ETHERC_EPTPC_SYTLIR_DREQ_Msk (0xff0000UL) /*!< DREQ (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYTLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYTLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ======================================================== SYRLIR ========================================================= */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Pos (16UL) /*!< DRESP (Bit 16) */ + #define R_ETHERC_EPTPC_SYRLIR_DRESP_Msk (0xff0000UL) /*!< DRESP (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Pos (8UL) /*!< SYNC (Bit 8) */ + #define R_ETHERC_EPTPC_SYRLIR_SYNC_Msk (0xff00UL) /*!< SYNC (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Pos (0UL) /*!< ANCE (Bit 0) */ + #define R_ETHERC_EPTPC_SYRLIR_ANCE_Msk (0xffUL) /*!< ANCE (Bitfield-Mask: 0xff) */ +/* ========================================================= OFMRU ========================================================= */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Pos (0UL) /*!< OFMRU (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRU_OFMRU_Msk (0xffffffffUL) /*!< OFMRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= OFMRL ========================================================= */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Pos (0UL) /*!< OFMRL (Bit 0) */ + #define R_ETHERC_EPTPC_OFMRL_OFMRL_Msk (0xffffffffUL) /*!< OFMRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRU ========================================================= */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Pos (0UL) /*!< MPDRU (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRU_MPDRU_Msk (0xffffffffUL) /*!< MPDRU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MPDRL ========================================================= */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Pos (0UL) /*!< MPDRL (Bit 0) */ + #define R_ETHERC_EPTPC_MPDRL_MPDRL_Msk (0xffffffffUL) /*!< MPDRL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GMPR ========================================================== */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Pos (16UL) /*!< GMPR1 (Bit 16) */ + #define R_ETHERC_EPTPC_GMPR_GMPR1_Msk (0xff0000UL) /*!< GMPR1 (Bitfield-Mask: 0xff) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Pos (0UL) /*!< GMPR2 (Bit 0) */ + #define R_ETHERC_EPTPC_GMPR_GMPR2_Msk (0xffUL) /*!< GMPR2 (Bitfield-Mask: 0xff) */ +/* ========================================================= GMCQR ========================================================= */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Pos (0UL) /*!< GMCQR (Bit 0) */ + #define R_ETHERC_EPTPC_GMCQR_GMCQR_Msk (0xffffffffUL) /*!< GMCQR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRU ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Pos (0UL) /*!< GMIDRU (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRU_GMIDRU_Msk (0xffffffffUL) /*!< GMIDRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GMIDRL ========================================================= */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Pos (0UL) /*!< GMIDRL (Bit 0) */ + #define R_ETHERC_EPTPC_GMIDRL_GMIDRL_Msk (0xffffffffUL) /*!< GMIDRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CUOTSR ========================================================= */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Pos (16UL) /*!< CUTO (Bit 16) */ + #define R_ETHERC_EPTPC_CUOTSR_CUTO_Msk (0xffff0000UL) /*!< CUTO (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Pos (0UL) /*!< TSRC (Bit 0) */ + #define R_ETHERC_EPTPC_CUOTSR_TSRC_Msk (0xffUL) /*!< TSRC (Bitfield-Mask: 0xff) */ +/* ========================================================== SRR ========================================================== */ + #define R_ETHERC_EPTPC_SRR_SRMV_Pos (0UL) /*!< SRMV (Bit 0) */ + #define R_ETHERC_EPTPC_SRR_SRMV_Msk (0xffffUL) /*!< SRMV (Bitfield-Mask: 0xffff) */ +/* ======================================================== PPMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Pos (0UL) /*!< PPMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRU_PPMACRU_Msk (0xffffffUL) /*!< PPMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PPMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Pos (0UL) /*!< PPMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PPMACRL_PPMACRL_Msk (0xffffffUL) /*!< PPMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRU ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Pos (0UL) /*!< PDMACRU (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRU_PDMACRU_Msk (0xffffffUL) /*!< PDMACRU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PDMACRL ======================================================== */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Pos (0UL) /*!< PDMACRL (Bit 0) */ + #define R_ETHERC_EPTPC_PDMACRL_PDMACRL_Msk (0xffffffUL) /*!< PDMACRL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== PETYPER ======================================================== */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ETHERC_EPTPC_PETYPER_TYPE_Msk (0xffffUL) /*!< TYPE (Bitfield-Mask: 0xffff) */ +/* ========================================================= PPIPR ========================================================= */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Pos (0UL) /*!< PPIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PPIPR_PPIPR_Msk (0xffffffffUL) /*!< PPIPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PDIPR ========================================================= */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Pos (0UL) /*!< PDIPR (Bit 0) */ + #define R_ETHERC_EPTPC_PDIPR_PDIPR_Msk (0xffffffffUL) /*!< PDIPR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PETOSR ========================================================= */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Pos (0UL) /*!< EVTO (Bit 0) */ + #define R_ETHERC_EPTPC_PETOSR_EVTO_Msk (0xffUL) /*!< EVTO (Bitfield-Mask: 0xff) */ +/* ======================================================== PGTOSR ========================================================= */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Pos (0UL) /*!< GETO (Bit 0) */ + #define R_ETHERC_EPTPC_PGTOSR_GETO_Msk (0xffUL) /*!< GETO (Bitfield-Mask: 0xff) */ +/* ======================================================== PPTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Pos (0UL) /*!< PRTL (Bit 0) */ + #define R_ETHERC_EPTPC_PPTTLR_PRTL_Msk (0xffUL) /*!< PRTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PDTTLR ========================================================= */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Pos (0UL) /*!< PDTL (Bit 0) */ + #define R_ETHERC_EPTPC_PDTTLR_PDTL_Msk (0xffUL) /*!< PDTL (Bitfield-Mask: 0xff) */ +/* ======================================================== PEUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Pos (0UL) /*!< EVUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PEUDPR_EVUPT_Msk (0xffffUL) /*!< EVUPT (Bitfield-Mask: 0xffff) */ +/* ======================================================== PGUDPR ========================================================= */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Pos (0UL) /*!< GEUPT (Bit 0) */ + #define R_ETHERC_EPTPC_PGUDPR_GEUPT_Msk (0xffffUL) /*!< GEUPT (Bitfield-Mask: 0xffff) */ +/* ========================================================= FFLTR ========================================================= */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Pos (16UL) /*!< EXTPRM (Bit 16) */ + #define R_ETHERC_EPTPC_FFLTR_EXTPRM_Msk (0x10000UL) /*!< EXTPRM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Pos (2UL) /*!< ENB (Bit 2) */ + #define R_ETHERC_EPTPC_FFLTR_ENB_Msk (0x4UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Pos (1UL) /*!< PRT (Bit 1) */ + #define R_ETHERC_EPTPC_FFLTR_PRT_Msk (0x2UL) /*!< PRT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_ETHERC_EPTPC_FFLTR_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ +/* ======================================================== FMAC0RU ======================================================== */ + #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Pos (0UL) /*!< FMAC0RU (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC0RU_FMAC0RU_Msk (0xffffffUL) /*!< FMAC0RU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC0RL ======================================================== */ + #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Pos (0UL) /*!< FMAC0RL (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC0RL_FMAC0RL_Msk (0xffffffUL) /*!< FMAC0RL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC1RU ======================================================== */ + #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Pos (0UL) /*!< FMAC1RU (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC1RU_FMAC1RU_Msk (0xffffffUL) /*!< FMAC1RU (Bitfield-Mask: 0xffffff) */ +/* ======================================================== FMAC1RL ======================================================== */ + #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Pos (0UL) /*!< FMAC1RL (Bit 0) */ + #define R_ETHERC_EPTPC_FMAC1RL_FMAC1RL_Msk (0xffffffUL) /*!< FMAC1RL (Bitfield-Mask: 0xffffff) */ +/* ======================================================== DASYMRU ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Pos (0UL) /*!< DASYMRU (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRU_DASYMRU_Msk (0xffffUL) /*!< DASYMRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== DASYMRL ======================================================== */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Pos (0UL) /*!< DASYMRL (Bit 0) */ + #define R_ETHERC_EPTPC_DASYMRL_DASYMRL_Msk (0xffffffffUL) /*!< DASYMRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSLATR ========================================================= */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Pos (16UL) /*!< INGP (Bit 16) */ + #define R_ETHERC_EPTPC_TSLATR_INGP_Msk (0xffff0000UL) /*!< INGP (Bitfield-Mask: 0xffff) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Pos (0UL) /*!< EGP (Bit 0) */ + #define R_ETHERC_EPTPC_TSLATR_EGP_Msk (0xffffUL) /*!< EGP (Bitfield-Mask: 0xffff) */ +/* ======================================================== SYCONFR ======================================================== */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Pos (20UL) /*!< TCMOD (Bit 20) */ + #define R_ETHERC_EPTPC_SYCONFR_TCMOD_Msk (0x100000UL) /*!< TCMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Pos (16UL) /*!< FILDIS (Bit 16) */ + #define R_ETHERC_EPTPC_SYCONFR_FILDIS_Msk (0x10000UL) /*!< FILDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Pos (12UL) /*!< SBDIS (Bit 12) */ + #define R_ETHERC_EPTPC_SYCONFR_SBDIS_Msk (0x1000UL) /*!< SBDIS (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Pos (0UL) /*!< TCYC (Bit 0) */ + #define R_ETHERC_EPTPC_SYCONFR_TCYC_Msk (0xffUL) /*!< TCYC (Bitfield-Mask: 0xff) */ +/* ======================================================== SYFORMR ======================================================== */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Pos (1UL) /*!< FORM1 (Bit 1) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM1_Msk (0x2UL) /*!< FORM1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Pos (0UL) /*!< FORM0 (Bit 0) */ + #define R_ETHERC_EPTPC_SYFORMR_FORM0_Msk (0x1UL) /*!< FORM0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTOUTR ======================================================== */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Pos (0UL) /*!< RSTOUTR (Bit 0) */ + #define R_ETHERC_EPTPC_RSTOUTR_RSTOUTR_Msk (0xffffffffUL) /*!< RSTOUTR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_CFG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PTRSTR ========================================================= */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Pos (0UL) /*!< RESET (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_PTRSTR_RESET_Msk (0x1UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ======================================================== STCSELR ======================================================== */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Pos (8UL) /*!< SCLKSEL (Bit 8) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKSEL_Msk (0x700UL) /*!< SCLKSEL (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Pos (0UL) /*!< SCLKDIV (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_STCSELR_SCLKDIV_Msk (0x7UL) /*!< SCLKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== BYPASS ========================================================= */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Pos (16UL) /*!< BYPASS1 (Bit 16) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS1_Msk (0x10000UL) /*!< BYPASS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Pos (0UL) /*!< BYPASS0 (Bit 0) */ + #define R_ETHERC_EPTPC_CFG_BYPASS_BYPASS0_Msk (0x1UL) /*!< BYPASS0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EPTPC_COMMON ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MIESR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIESR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== MIEIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Pos (21UL) /*!< CYC5 (Bit 21) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC5_Msk (0x200000UL) /*!< CYC5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Pos (20UL) /*!< CYC4 (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC4_Msk (0x100000UL) /*!< CYC4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Pos (19UL) /*!< CYC3 (Bit 19) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC3_Msk (0x80000UL) /*!< CYC3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Pos (18UL) /*!< CYC2 (Bit 18) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC2_Msk (0x40000UL) /*!< CYC2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Pos (17UL) /*!< CYC1 (Bit 17) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC1_Msk (0x20000UL) /*!< CYC1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Pos (16UL) /*!< CYC0 (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_CYC0_Msk (0x10000UL) /*!< CYC0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Pos (3UL) /*!< PRC (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_PRC_Msk (0x8UL) /*!< PRC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Pos (2UL) /*!< SY1 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY1_Msk (0x4UL) /*!< SY1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Pos (1UL) /*!< SY0 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_SY0_Msk (0x2UL) /*!< SY0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Pos (0UL) /*!< ST (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MIEIPR_ST_Msk (0x1UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPPR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELIPACR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Pos (24UL) /*!< PLSN (Bit 24) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSN_Msk (0x1000000UL) /*!< PLSN (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Pos (16UL) /*!< PLSP (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_PLSP_Msk (0x10000UL) /*!< PLSP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Pos (13UL) /*!< CYCN5 (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN5_Msk (0x2000UL) /*!< CYCN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Pos (12UL) /*!< CYCN4 (Bit 12) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN4_Msk (0x1000UL) /*!< CYCN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Pos (11UL) /*!< CYCN3 (Bit 11) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN3_Msk (0x800UL) /*!< CYCN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Pos (10UL) /*!< CYCN2 (Bit 10) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN2_Msk (0x400UL) /*!< CYCN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Pos (9UL) /*!< CYCN1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN1_Msk (0x200UL) /*!< CYCN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Pos (8UL) /*!< CYCN0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCN0_Msk (0x100UL) /*!< CYCN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Pos (5UL) /*!< CYCP5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP5_Msk (0x20UL) /*!< CYCP5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Pos (4UL) /*!< CYCP4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP4_Msk (0x10UL) /*!< CYCP4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Pos (3UL) /*!< CYCP3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP3_Msk (0x8UL) /*!< CYCP3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Pos (2UL) /*!< CYCP2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP2_Msk (0x4UL) /*!< CYCP2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Pos (1UL) /*!< CYCP1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP1_Msk (0x2UL) /*!< CYCP1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Pos (0UL) /*!< CYCP0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELIPACR_CYCP0_Msk (0x1UL) /*!< CYCP0 (Bitfield-Mask: 0x01) */ +/* ========================================================= STSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STSR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STSR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Pos (4UL) /*!< W10D (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_W10D_Msk (0x10UL) /*!< W10D (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Pos (3UL) /*!< SYNTOUT (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNTOUT_Msk (0x8UL) /*!< SYNTOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Pos (1UL) /*!< SYNCOUT (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNCOUT_Msk (0x2UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Pos (0UL) /*!< SYNC (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STIPR_SYNC_Msk (0x1UL) /*!< SYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= STCFR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Pos (0UL) /*!< STCF (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCFR_STCF_Msk (0x3UL) /*!< STCF (Bitfield-Mask: 0x03) */ +/* ========================================================= STMR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Pos (29UL) /*!< ALEN1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN1_Msk (0x20000000UL) /*!< ALEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Pos (28UL) /*!< ALEN0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_STMR_ALEN0_Msk (0x10000000UL) /*!< ALEN0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Pos (20UL) /*!< DVTH (Bit 20) */ + #define R_ETHERC_EPTPC_COMMON_STMR_DVTH_Msk (0xf00000UL) /*!< DVTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Pos (16UL) /*!< SYTH (Bit 16) */ + #define R_ETHERC_EPTPC_COMMON_STMR_SYTH_Msk (0xf0000UL) /*!< SYTH (Bitfield-Mask: 0x0f) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Pos (15UL) /*!< W10S (Bit 15) */ + #define R_ETHERC_EPTPC_COMMON_STMR_W10S_Msk (0x8000UL) /*!< W10S (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Pos (13UL) /*!< CMOD (Bit 13) */ + #define R_ETHERC_EPTPC_COMMON_STMR_CMOD_Msk (0x2000UL) /*!< CMOD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Pos (0UL) /*!< WINT (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STMR_WINT_Msk (0xffUL) /*!< WINT (Bitfield-Mask: 0xff) */ +/* ======================================================== SYNTOR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Pos (0UL) /*!< SYNTOR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTOR_SYNTOR_Msk (0xffffffffUL) /*!< SYNTOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== IPTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Pos (5UL) /*!< IPTSEL5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL5_Msk (0x20UL) /*!< IPTSEL5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Pos (4UL) /*!< IPTSEL4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL4_Msk (0x10UL) /*!< IPTSEL4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Pos (3UL) /*!< IPTSEL3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL3_Msk (0x8UL) /*!< IPTSEL3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Pos (2UL) /*!< IPTSEL2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL2_Msk (0x4UL) /*!< IPTSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Pos (1UL) /*!< IPTSEL1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL1_Msk (0x2UL) /*!< IPTSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Pos (0UL) /*!< IPTSEL0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_IPTSELR_IPTSEL0_Msk (0x1UL) /*!< IPTSEL0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MITSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Pos (5UL) /*!< MINTEN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN5_Msk (0x20UL) /*!< MINTEN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Pos (4UL) /*!< MINTEN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN4_Msk (0x10UL) /*!< MINTEN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Pos (3UL) /*!< MINTEN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN3_Msk (0x8UL) /*!< MINTEN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Pos (2UL) /*!< MINTEN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN2_Msk (0x4UL) /*!< MINTEN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Pos (1UL) /*!< MINTEN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN1_Msk (0x2UL) /*!< MINTEN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Pos (0UL) /*!< MINTEN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MITSELR_MINTEN0_Msk (0x1UL) /*!< MINTEN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELTSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Pos (5UL) /*!< ELTDIS5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS5_Msk (0x20UL) /*!< ELTDIS5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Pos (4UL) /*!< ELTDIS4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS4_Msk (0x10UL) /*!< ELTDIS4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Pos (3UL) /*!< ELTDIS3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS3_Msk (0x8UL) /*!< ELTDIS3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Pos (2UL) /*!< ELTDIS2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS2_Msk (0x4UL) /*!< ELTDIS2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Pos (1UL) /*!< ELTDIS1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS1_Msk (0x2UL) /*!< ELTDIS1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Pos (0UL) /*!< ELTDIS0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_ELTSELR_ELTDIS0_Msk (0x1UL) /*!< ELTDIS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= STCHSELR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Pos (0UL) /*!< SYSEL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_STCHSELR_SYSEL_Msk (0x1UL) /*!< SYSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNSTARTR ======================================================= */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNSTARTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ======================================================== LCIVLDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Pos (0UL) /*!< LOAD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVLDR_LOAD_Msk (0x1UL) /*!< LOAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SYNTDARU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Pos (0UL) /*!< SYNTDARU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARU_SYNTDARU_Msk (0xffffffffUL) /*!< SYNTDARU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDARL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Pos (0UL) /*!< SYNTDARL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDARL_SYNTDARL_Msk (0xffffffffUL) /*!< SYNTDARL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Pos (0UL) /*!< SYNTDBRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRU_SYNTDBRU_Msk (0xffffffffUL) /*!< SYNTDBRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SYNTDBRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Pos (0UL) /*!< SYNTDBRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_SYNTDBRL_SYNTDBRL_Msk (0xffffffffUL) /*!< SYNTDBRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Pos (0UL) /*!< LCIVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRU_LCIVRU_Msk (0xffffUL) /*!< LCIVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCIVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Pos (0UL) /*!< LCIVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRM_LCIVRM_Msk (0xffffffffUL) /*!< LCIVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCIVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Pos (0UL) /*!< LCIVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCIVRL_LCIVRL_Msk (0xffffffffUL) /*!< LCIVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GETW10R ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Pos (0UL) /*!< GW10 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETW10R_GW10_Msk (0x1UL) /*!< GW10 (Bitfield-Mask: 0x01) */ +/* ======================================================= PLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Pos (0UL) /*!< PLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRU_PLIMITRU_Msk (0x7fffffffUL) /*!< PLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= PLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Pos (0UL) /*!< PLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRM_PLIMITRM_Msk (0xffffffffUL) /*!< PLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Pos (0UL) /*!< PLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PLIMITRL_PLIMITRL_Msk (0xffffffffUL) /*!< PLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Pos (0UL) /*!< MLIMITRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRU_MLIMITRU_Msk (0x7fffffffUL) /*!< MLIMITRU (Bitfield-Mask: 0x7fffffff) */ +/* ======================================================= MLIMITRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Pos (0UL) /*!< MLIMITRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRM_MLIMITRM_Msk (0xffffffffUL) /*!< MLIMITRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= MLIMITRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Pos (0UL) /*!< MLIMITRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MLIMITRL_MLIMITRL_Msk (0xffffffffUL) /*!< MLIMITRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GETINFOR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Pos (0UL) /*!< INFO (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_GETINFOR_INFO_Msk (0x1UL) /*!< INFO (Bitfield-Mask: 0x01) */ +/* ======================================================== LCCVRU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Pos (0UL) /*!< LCCVRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRU_LCCVRU_Msk (0xffffUL) /*!< LCCVRU (Bitfield-Mask: 0xffff) */ +/* ======================================================== LCCVRM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Pos (0UL) /*!< LCCVRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRM_LCCVRM_Msk (0xffffffffUL) /*!< LCCVRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LCCVRL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Pos (0UL) /*!< LCCVRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_LCCVRL_LCCVRL_Msk (0xffffffffUL) /*!< LCCVRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRU ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Pos (0UL) /*!< PW10VRU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRU_PW10VRU_Msk (0xffffffffUL) /*!< PW10VRU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRM ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Pos (0UL) /*!< PW10VRM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRM_PW10VRM_Msk (0xffffffffUL) /*!< PW10VRM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== PW10VRL ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Pos (0UL) /*!< PW10VRL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PW10VRL_PW10VRL_Msk (0xffffffffUL) /*!< PW10VRL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RU ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Pos (0UL) /*!< MW10RU (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RU_MW10RU_Msk (0xffffffffUL) /*!< MW10RU (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RM ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Pos (0UL) /*!< MW10RM (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RM_MW10RM_Msk (0xffffffffUL) /*!< MW10RM (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MW10RL ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Pos (0UL) /*!< MW10RL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_MW10RL_MW10RL_Msk (0xffffffffUL) /*!< MW10RL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TMSTARTR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Pos (5UL) /*!< EN5 (Bit 5) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN5_Msk (0x20UL) /*!< EN5 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Pos (4UL) /*!< EN4 (Bit 4) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN4_Msk (0x10UL) /*!< EN4 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Pos (3UL) /*!< EN3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN3_Msk (0x8UL) /*!< EN3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Pos (2UL) /*!< EN2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN2_Msk (0x4UL) /*!< EN2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TMSTARTR_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSR ========================================================== */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRSR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PRIPR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Pos (29UL) /*!< URE1 (Bit 29) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE1_Msk (0x20000000UL) /*!< URE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Pos (28UL) /*!< URE0 (Bit 28) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_URE0_Msk (0x10000000UL) /*!< URE0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Pos (8UL) /*!< MACE (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_MACE_Msk (0x100UL) /*!< MACE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Pos (3UL) /*!< OVRE3 (Bit 3) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE3_Msk (0x8UL) /*!< OVRE3 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Pos (2UL) /*!< OVRE2 (Bit 2) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE2_Msk (0x4UL) /*!< OVRE2 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Pos (1UL) /*!< OVRE1 (Bit 1) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE1_Msk (0x2UL) /*!< OVRE1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Pos (0UL) /*!< OVRE0 (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_PRIPR_OVRE0_Msk (0x1UL) /*!< OVRE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRNDISR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Pos (0UL) /*!< TDIS (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNDISR_TDIS_Msk (0x3UL) /*!< TDIS (Bitfield-Mask: 0x03) */ +/* ========================================================= TRNMR ========================================================= */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Pos (9UL) /*!< FWD1 (Bit 9) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD1_Msk (0x200UL) /*!< FWD1 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Pos (8UL) /*!< FWD0 (Bit 8) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_FWD0_Msk (0x100UL) /*!< FWD0 (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Pos (0UL) /*!< MOD (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNMR_MOD_Msk (0x1UL) /*!< MOD (Bitfield-Mask: 0x01) */ +/* ======================================================= TRNCTTDR ======================================================== */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Pos (0UL) /*!< THVAL (Bit 0) */ + #define R_ETHERC_EPTPC_COMMON_TRNCTTDR_THVAL_Msk (0x7ffUL) /*!< THVAL (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GLCDC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GR1_CLUT0 ======================================================= */ + #define R_GLCDC_GR1_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR1_CLUT1 ======================================================= */ + #define R_GLCDC_GR1_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR1_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR1_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR1_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR1_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR1_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT0 ======================================================= */ + #define R_GLCDC_GR2_CLUT0_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT0_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT0_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT0_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT0_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT0_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ +/* ======================================================= GR2_CLUT1 ======================================================= */ + #define R_GLCDC_GR2_CLUT1_A_Pos (24UL) /*!< A (Bit 24) */ + #define R_GLCDC_GR2_CLUT1_A_Msk (0xff000000UL) /*!< A (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_R_Pos (16UL) /*!< R (Bit 16) */ + #define R_GLCDC_GR2_CLUT1_R_Msk (0xff0000UL) /*!< R (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_G_Pos (8UL) /*!< G (Bit 8) */ + #define R_GLCDC_GR2_CLUT1_G_Msk (0xff00UL) /*!< G (Bitfield-Mask: 0xff) */ + #define R_GLCDC_GR2_CLUT1_B_Pos (0UL) /*!< B (Bit 0) */ + #define R_GLCDC_GR2_CLUT1_B_Msk (0xffUL) /*!< B (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_JPEG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= JCMOD ========================================================= */ + #define R_JPEG_JCMOD_DSP_Pos (3UL) /*!< DSP (Bit 3) */ + #define R_JPEG_JCMOD_DSP_Msk (0x8UL) /*!< DSP (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCMOD_REDU_Pos (0UL) /*!< REDU (Bit 0) */ + #define R_JPEG_JCMOD_REDU_Msk (0x7UL) /*!< REDU (Bitfield-Mask: 0x07) */ +/* ========================================================= JCCMD ========================================================= */ + #define R_JPEG_JCCMD_BRST_Pos (7UL) /*!< BRST (Bit 7) */ + #define R_JPEG_JCCMD_BRST_Msk (0x80UL) /*!< BRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JEND_Pos (2UL) /*!< JEND (Bit 2) */ + #define R_JPEG_JCCMD_JEND_Msk (0x4UL) /*!< JEND (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JRST_Pos (1UL) /*!< JRST (Bit 1) */ + #define R_JPEG_JCCMD_JRST_Msk (0x2UL) /*!< JRST (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCCMD_JSRT_Pos (0UL) /*!< JSRT (Bit 0) */ + #define R_JPEG_JCCMD_JSRT_Msk (0x1UL) /*!< JSRT (Bitfield-Mask: 0x01) */ +/* ========================================================= JCQTN ========================================================= */ + #define R_JPEG_JCQTN_QT3_Pos (4UL) /*!< QT3 (Bit 4) */ + #define R_JPEG_JCQTN_QT3_Msk (0x30UL) /*!< QT3 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT2_Pos (2UL) /*!< QT2 (Bit 2) */ + #define R_JPEG_JCQTN_QT2_Msk (0xcUL) /*!< QT2 (Bitfield-Mask: 0x03) */ + #define R_JPEG_JCQTN_QT1_Pos (0UL) /*!< QT1 (Bit 0) */ + #define R_JPEG_JCQTN_QT1_Msk (0x3UL) /*!< QT1 (Bitfield-Mask: 0x03) */ +/* ========================================================= JCHTN ========================================================= */ + #define R_JPEG_JCHTN_HTA3_Pos (5UL) /*!< HTA3 (Bit 5) */ + #define R_JPEG_JCHTN_HTA3_Msk (0x20UL) /*!< HTA3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD3_Pos (4UL) /*!< HTD3 (Bit 4) */ + #define R_JPEG_JCHTN_HTD3_Msk (0x10UL) /*!< HTD3 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA2_Pos (3UL) /*!< HTA2 (Bit 3) */ + #define R_JPEG_JCHTN_HTA2_Msk (0x8UL) /*!< HTA2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD2_Pos (2UL) /*!< HTD2 (Bit 2) */ + #define R_JPEG_JCHTN_HTD2_Msk (0x4UL) /*!< HTD2 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTA1_Pos (1UL) /*!< HTA1 (Bit 1) */ + #define R_JPEG_JCHTN_HTA1_Msk (0x2UL) /*!< HTA1 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JCHTN_HTD1_Pos (0UL) /*!< HTD1 (Bit 0) */ + #define R_JPEG_JCHTN_HTD1_Msk (0x1UL) /*!< HTD1 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDRIU ========================================================= */ + #define R_JPEG_JCDRIU_DRIU_Pos (0UL) /*!< DRIU (Bit 0) */ + #define R_JPEG_JCDRIU_DRIU_Msk (0xffUL) /*!< DRIU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDRID ========================================================= */ + #define R_JPEG_JCDRID_DRID_Pos (0UL) /*!< DRID (Bit 0) */ + #define R_JPEG_JCDRID_DRID_Msk (0xffUL) /*!< DRID (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZU ========================================================= */ + #define R_JPEG_JCVSZU_VSZU_Pos (0UL) /*!< VSZU (Bit 0) */ + #define R_JPEG_JCVSZU_VSZU_Msk (0xffUL) /*!< VSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCVSZD ========================================================= */ + #define R_JPEG_JCVSZD_VSZD_Pos (0UL) /*!< VSZD (Bit 0) */ + #define R_JPEG_JCVSZD_VSZD_Msk (0xffUL) /*!< VSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZU ========================================================= */ + #define R_JPEG_JCHSZU_HSZU_Pos (0UL) /*!< HSZU (Bit 0) */ + #define R_JPEG_JCHSZU_HSZU_Msk (0xffUL) /*!< HSZU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCHSZD ========================================================= */ + #define R_JPEG_JCHSZD_HSZD_Pos (0UL) /*!< HSZD (Bit 0) */ + #define R_JPEG_JCHSZD_HSZD_Msk (0xffUL) /*!< HSZD (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCU ========================================================= */ + #define R_JPEG_JCDTCU_DCU_Pos (0UL) /*!< DCU (Bit 0) */ + #define R_JPEG_JCDTCU_DCU_Msk (0xffUL) /*!< DCU (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCM ========================================================= */ + #define R_JPEG_JCDTCM_DCM_Pos (0UL) /*!< DCM (Bit 0) */ + #define R_JPEG_JCDTCM_DCM_Msk (0xffUL) /*!< DCM (Bitfield-Mask: 0xff) */ +/* ======================================================== JCDTCD ========================================================= */ + #define R_JPEG_JCDTCD_DCD_Pos (0UL) /*!< DCD (Bit 0) */ + #define R_JPEG_JCDTCD_DCD_Msk (0xffUL) /*!< DCD (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE0 ========================================================= */ + #define R_JPEG_JINTE0_INT7_Pos (7UL) /*!< INT7 (Bit 7) */ + #define R_JPEG_JINTE0_INT7_Msk (0x80UL) /*!< INT7 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT6_Pos (6UL) /*!< INT6 (Bit 6) */ + #define R_JPEG_JINTE0_INT6_Msk (0x40UL) /*!< INT6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT5_Pos (5UL) /*!< INT5 (Bit 5) */ + #define R_JPEG_JINTE0_INT5_Msk (0x20UL) /*!< INT5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE0_INT3_Pos (3UL) /*!< INT3 (Bit 3) */ + #define R_JPEG_JINTE0_INT3_Msk (0x8UL) /*!< INT3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS0 ========================================================= */ + #define R_JPEG_JINTS0_INS6_Pos (6UL) /*!< INS6 (Bit 6) */ + #define R_JPEG_JINTS0_INS6_Msk (0x40UL) /*!< INS6 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS5_Pos (5UL) /*!< INS5 (Bit 5) */ + #define R_JPEG_JINTS0_INS5_Msk (0x20UL) /*!< INS5 (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS0_INS3_Pos (3UL) /*!< INS3 (Bit 3) */ + #define R_JPEG_JINTS0_INS3_Msk (0x8UL) /*!< INS3 (Bitfield-Mask: 0x01) */ +/* ======================================================== JCDERR ========================================================= */ + #define R_JPEG_JCDERR_ERR_Pos (0UL) /*!< ERR (Bit 0) */ + #define R_JPEG_JCDERR_ERR_Msk (0xfUL) /*!< ERR (Bitfield-Mask: 0x0f) */ +/* ========================================================= JCRST ========================================================= */ + #define R_JPEG_JCRST_RST_Pos (0UL) /*!< RST (Bit 0) */ + #define R_JPEG_JCRST_RST_Msk (0x1UL) /*!< RST (Bitfield-Mask: 0x01) */ +/* ======================================================== JIFECNT ======================================================== */ + #define R_JPEG_JIFECNT_JOUTSWAP_Pos (8UL) /*!< JOUTSWAP (Bit 8) */ + #define R_JPEG_JIFECNT_JOUTSWAP_Msk (0x700UL) /*!< JOUTSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFECNT_DINRINI_Pos (6UL) /*!< DINRINI (Bit 6) */ + #define R_JPEG_JIFECNT_DINRINI_Msk (0x40UL) /*!< DINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINRCMD_Pos (5UL) /*!< DINRCMD (Bit 5) */ + #define R_JPEG_JIFECNT_DINRCMD_Msk (0x20UL) /*!< DINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINLC_Pos (4UL) /*!< DINLC (Bit 4) */ + #define R_JPEG_JIFECNT_DINLC_Msk (0x10UL) /*!< DINLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFECNT_DINSWAP_Pos (0UL) /*!< DINSWAP (Bit 0) */ + #define R_JPEG_JIFECNT_DINSWAP_Msk (0x7UL) /*!< DINSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFESA ========================================================= */ + #define R_JPEG_JIFESA_ESA_Pos (0UL) /*!< ESA (Bit 0) */ + #define R_JPEG_JIFESA_ESA_Msk (0xffffffffUL) /*!< ESA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFESOFST ======================================================= */ + #define R_JPEG_JIFESOFST_ESMW_Pos (0UL) /*!< ESMW (Bit 0) */ + #define R_JPEG_JIFESOFST_ESMW_Msk (0x7fffUL) /*!< ESMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFEDA ========================================================= */ + #define R_JPEG_JIFEDA_EDA_Pos (0UL) /*!< EDA (Bit 0) */ + #define R_JPEG_JIFEDA_EDA_Msk (0xffffffffUL) /*!< EDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFESLC ======================================================== */ + #define R_JPEG_JIFESLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFESLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDCNT ======================================================== */ + #define R_JPEG_JIFDCNT_VINTER_Pos (28UL) /*!< VINTER (Bit 28) */ + #define R_JPEG_JIFDCNT_VINTER_Msk (0x30000000UL) /*!< VINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_HINTER_Pos (26UL) /*!< HINTER (Bit 26) */ + #define R_JPEG_JIFDCNT_HINTER_Msk (0xc000000UL) /*!< HINTER (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_OPF_Pos (24UL) /*!< OPF (Bit 24) */ + #define R_JPEG_JIFDCNT_OPF_Msk (0x3000000UL) /*!< OPF (Bitfield-Mask: 0x03) */ + #define R_JPEG_JIFDCNT_JINRINI_Pos (14UL) /*!< JINRINI (Bit 14) */ + #define R_JPEG_JIFDCNT_JINRINI_Msk (0x4000UL) /*!< JINRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINRCMD_Pos (13UL) /*!< JINRCMD (Bit 13) */ + #define R_JPEG_JIFDCNT_JINRCMD_Msk (0x2000UL) /*!< JINRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINC_Pos (12UL) /*!< JINC (Bit 12) */ + #define R_JPEG_JIFDCNT_JINC_Msk (0x1000UL) /*!< JINC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_JINSWAP_Pos (8UL) /*!< JINSWAP (Bit 8) */ + #define R_JPEG_JIFDCNT_JINSWAP_Msk (0x700UL) /*!< JINSWAP (Bitfield-Mask: 0x07) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Pos (6UL) /*!< DOUTRINI (Bit 6) */ + #define R_JPEG_JIFDCNT_DOUTRINI_Msk (0x40UL) /*!< DOUTRINI (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Pos (5UL) /*!< DOUTRCMD (Bit 5) */ + #define R_JPEG_JIFDCNT_DOUTRCMD_Msk (0x20UL) /*!< DOUTRCMD (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTLC_Pos (4UL) /*!< DOUTLC (Bit 4) */ + #define R_JPEG_JIFDCNT_DOUTLC_Msk (0x10UL) /*!< DOUTLC (Bitfield-Mask: 0x01) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Pos (0UL) /*!< DOUTSWAP (Bit 0) */ + #define R_JPEG_JIFDCNT_DOUTSWAP_Msk (0x7UL) /*!< DOUTSWAP (Bitfield-Mask: 0x07) */ +/* ======================================================== JIFDSA ========================================================= */ + #define R_JPEG_JIFDSA_DSA_Pos (0UL) /*!< DSA (Bit 0) */ + #define R_JPEG_JIFDSA_DSA_Msk (0xffffffffUL) /*!< DSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= JIFDDOFST ======================================================= */ + #define R_JPEG_JIFDDOFST_DDMW_Pos (0UL) /*!< DDMW (Bit 0) */ + #define R_JPEG_JIFDDOFST_DDMW_Msk (0x7fffUL) /*!< DDMW (Bitfield-Mask: 0x7fff) */ +/* ======================================================== JIFDDA ========================================================= */ + #define R_JPEG_JIFDDA_DDA_Pos (0UL) /*!< DDA (Bit 0) */ + #define R_JPEG_JIFDDA_DDA_Msk (0xffffffffUL) /*!< DDA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== JIFDSDC ======================================================== */ + #define R_JPEG_JIFDSDC_JDATAS_Pos (0UL) /*!< JDATAS (Bit 0) */ + #define R_JPEG_JIFDSDC_JDATAS_Msk (0xffffUL) /*!< JDATAS (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDDLC ======================================================== */ + #define R_JPEG_JIFDDLC_LINES_Pos (0UL) /*!< LINES (Bit 0) */ + #define R_JPEG_JIFDDLC_LINES_Msk (0xffffUL) /*!< LINES (Bitfield-Mask: 0xffff) */ +/* ======================================================== JIFDADT ======================================================== */ + #define R_JPEG_JIFDADT_ALPHA_Pos (0UL) /*!< ALPHA (Bit 0) */ + #define R_JPEG_JIFDADT_ALPHA_Msk (0xffUL) /*!< ALPHA (Bitfield-Mask: 0xff) */ +/* ======================================================== JINTE1 ========================================================= */ + #define R_JPEG_JINTE1_CBTEN_Pos (6UL) /*!< CBTEN (Bit 6) */ + #define R_JPEG_JINTE1_CBTEN_Msk (0x40UL) /*!< CBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DINLEN_Pos (5UL) /*!< DINLEN (Bit 5) */ + #define R_JPEG_JINTE1_DINLEN_Msk (0x20UL) /*!< DINLEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DBTEN_Pos (2UL) /*!< DBTEN (Bit 2) */ + #define R_JPEG_JINTE1_DBTEN_Msk (0x4UL) /*!< DBTEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_JINEN_Pos (1UL) /*!< JINEN (Bit 1) */ + #define R_JPEG_JINTE1_JINEN_Msk (0x2UL) /*!< JINEN (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTE1_DOUTLEN_Pos (0UL) /*!< DOUTLEN (Bit 0) */ + #define R_JPEG_JINTE1_DOUTLEN_Msk (0x1UL) /*!< DOUTLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== JINTS1 ========================================================= */ + #define R_JPEG_JINTS1_CBTF_Pos (6UL) /*!< CBTF (Bit 6) */ + #define R_JPEG_JINTS1_CBTF_Msk (0x40UL) /*!< CBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DINLF_Pos (5UL) /*!< DINLF (Bit 5) */ + #define R_JPEG_JINTS1_DINLF_Msk (0x20UL) /*!< DINLF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DBTF_Pos (2UL) /*!< DBTF (Bit 2) */ + #define R_JPEG_JINTS1_DBTF_Msk (0x4UL) /*!< DBTF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_JINF_Pos (1UL) /*!< JINF (Bit 1) */ + #define R_JPEG_JINTS1_JINF_Msk (0x2UL) /*!< JINF (Bitfield-Mask: 0x01) */ + #define R_JPEG_JINTS1_DOUTLF_Pos (0UL) /*!< DOUTLF (Bit 0) */ + #define R_JPEG_JINTS1_DOUTLF_Msk (0x1UL) /*!< DOUTLF (Bitfield-Mask: 0x01) */ +/* ======================================================== JCQTBL0 ======================================================== */ +/* ======================================================== JCQTBL1 ======================================================== */ +/* ======================================================== JCQTBL2 ======================================================== */ +/* ======================================================== JCQTBL3 ======================================================== */ +/* ======================================================== JCHTBD0 ======================================================== */ +/* ======================================================== JCHTBD1 ======================================================== */ +/* ======================================================== JCHTBA0 ======================================================== */ +/* ======================================================== JCHTBA1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PCCR0 ========================================================= */ + #define R_PDC_PCCR0_EDS_Pos (14UL) /*!< EDS (Bit 14) */ + #define R_PDC_PCCR0_EDS_Msk (0x4000UL) /*!< EDS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKDIV_Pos (11UL) /*!< PCKDIV (Bit 11) */ + #define R_PDC_PCCR0_PCKDIV_Msk (0x3800UL) /*!< PCKDIV (Bitfield-Mask: 0x07) */ + #define R_PDC_PCCR0_PCKOE_Pos (10UL) /*!< PCKOE (Bit 10) */ + #define R_PDC_PCCR0_PCKOE_Msk (0x400UL) /*!< PCKOE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HERIE_Pos (9UL) /*!< HERIE (Bit 9) */ + #define R_PDC_PCCR0_HERIE_Msk (0x200UL) /*!< HERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VERIE_Pos (8UL) /*!< VERIE (Bit 8) */ + #define R_PDC_PCCR0_VERIE_Msk (0x100UL) /*!< VERIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_UDRIE_Pos (7UL) /*!< UDRIE (Bit 7) */ + #define R_PDC_PCCR0_UDRIE_Msk (0x80UL) /*!< UDRIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_OVIE_Pos (6UL) /*!< OVIE (Bit 6) */ + #define R_PDC_PCCR0_OVIE_Msk (0x40UL) /*!< OVIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_FEIE_Pos (5UL) /*!< FEIE (Bit 5) */ + #define R_PDC_PCCR0_FEIE_Msk (0x20UL) /*!< FEIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_DFIE_Pos (4UL) /*!< DFIE (Bit 4) */ + #define R_PDC_PCCR0_DFIE_Msk (0x10UL) /*!< DFIE (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PRST_Pos (3UL) /*!< PRST (Bit 3) */ + #define R_PDC_PCCR0_PRST_Msk (0x8UL) /*!< PRST (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_HPS_Pos (2UL) /*!< HPS (Bit 2) */ + #define R_PDC_PCCR0_HPS_Msk (0x4UL) /*!< HPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_VPS_Pos (1UL) /*!< VPS (Bit 1) */ + #define R_PDC_PCCR0_VPS_Msk (0x2UL) /*!< VPS (Bitfield-Mask: 0x01) */ + #define R_PDC_PCCR0_PCKE_Pos (0UL) /*!< PCKE (Bit 0) */ + #define R_PDC_PCCR0_PCKE_Msk (0x1UL) /*!< PCKE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCCR1 ========================================================= */ + #define R_PDC_PCCR1_PCE_Pos (0UL) /*!< PCE (Bit 0) */ + #define R_PDC_PCCR1_PCE_Msk (0x1UL) /*!< PCE (Bitfield-Mask: 0x01) */ +/* ========================================================= PCSR ========================================================== */ + #define R_PDC_PCSR_HERF_Pos (6UL) /*!< HERF (Bit 6) */ + #define R_PDC_PCSR_HERF_Msk (0x40UL) /*!< HERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_VERF_Pos (5UL) /*!< VERF (Bit 5) */ + #define R_PDC_PCSR_VERF_Msk (0x20UL) /*!< VERF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_PDC_PCSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_OVRF_Pos (3UL) /*!< OVRF (Bit 3) */ + #define R_PDC_PCSR_OVRF_Msk (0x8UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEF_Pos (2UL) /*!< FEF (Bit 2) */ + #define R_PDC_PCSR_FEF_Msk (0x4UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FEMPF_Pos (1UL) /*!< FEMPF (Bit 1) */ + #define R_PDC_PCSR_FEMPF_Msk (0x2UL) /*!< FEMPF (Bitfield-Mask: 0x01) */ + #define R_PDC_PCSR_FBSY_Pos (0UL) /*!< FBSY (Bit 0) */ + #define R_PDC_PCSR_FBSY_Msk (0x1UL) /*!< FBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PCMONR ========================================================= */ + #define R_PDC_PCMONR_HSYNC_Pos (1UL) /*!< HSYNC (Bit 1) */ + #define R_PDC_PCMONR_HSYNC_Msk (0x2UL) /*!< HSYNC (Bitfield-Mask: 0x01) */ + #define R_PDC_PCMONR_VSYNC_Pos (0UL) /*!< VSYNC (Bit 0) */ + #define R_PDC_PCMONR_VSYNC_Msk (0x1UL) /*!< VSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= PCDR ========================================================== */ + #define R_PDC_PCDR_PCDR_Pos (0UL) /*!< PCDR (Bit 0) */ + #define R_PDC_PCDR_PCDR_Msk (0xffffffffUL) /*!< PCDR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== VCR ========================================================== */ + #define R_PDC_VCR_VSZ_Pos (16UL) /*!< VSZ (Bit 16) */ + #define R_PDC_VCR_VSZ_Msk (0xfff0000UL) /*!< VSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_VCR_VST_Pos (0UL) /*!< VST (Bit 0) */ + #define R_PDC_VCR_VST_Msk (0xfffUL) /*!< VST (Bitfield-Mask: 0xfff) */ +/* ========================================================== HCR ========================================================== */ + #define R_PDC_HCR_HSZ_Pos (16UL) /*!< HSZ (Bit 16) */ + #define R_PDC_HCR_HSZ_Msk (0xfff0000UL) /*!< HSZ (Bitfield-Mask: 0xfff) */ + #define R_PDC_HCR_HST_Pos (0UL) /*!< HST (Bit 0) */ + #define R_PDC_HCR_HST_Msk (0xfffUL) /*!< HST (Bitfield-Mask: 0xfff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M3AH_H */ + +/** @} */ /* End of group R7FA6M3AH */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h new file mode 100644 index 00000000..c326adc0 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h @@ -0,0 +1,22202 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA6M4AF.h + * @brief CMSIS HeaderFile + * @version 1.20.00 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:51:07 + * from File 'svd-test/R7FA6M4AF.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA6M4AF + * @{ + */ + +#ifndef R7FA6M4AF_H + #define R7FA6M4AF_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA6M4AF System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Octa Serial Peripheral Interface (R_OSPI) + */ + +typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ +{ + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ + + struct + { + __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ + __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ + uint32_t : 16; + } DCR_b; + }; + + union + { + __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ + + struct + { + __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ + __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ + __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ + __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ + } DAR_b; + }; + + union + { + __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ + + struct + { + __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ + __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ + uint32_t : 3; + __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ + __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ + __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ + __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ + __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ + __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ + __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ + uint32_t : 2; + } DCSR_b; + }; + + union + { + __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ + + struct + { + __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ + __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ + } DSR_b[2]; + }; + + union + { + __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ + + struct + { + __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ + __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ + __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ + __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ + __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ + uint32_t : 4; + } MDTR_b; + }; + + union + { + __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ + + struct + { + __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ + } ACTR_b; + }; + + union + { + __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ + + struct + { + __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ + } ACAR_b[2]; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting + * Register */ + + struct + { + __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ + __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ + __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ + __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ + __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DRCSTR_b; + }; + + union + { + __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting + * Register */ + + struct + { + __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ + __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ + __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ + __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ + __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DWCSTR_b; + }; + + union + { + __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ + __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ + __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ + uint32_t : 16; + } DCSTR_b; + }; + + union + { + __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ + + struct + { + __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ + __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ + __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ + __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ + uint32_t : 4; + __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device + * 0 */ + __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device + * 1 */ + __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ + uint32_t : 17; + __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ + } CDSR_b; + }; + + union + { + __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ + + struct + { + __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ + __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ + __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ + __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ + } MDLR_b; + }; + + union + { + __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ + + struct + { + __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ + __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ + __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ + __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ + } MRWCR_b[2]; + }; + + union + { + __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ + + struct + { + __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ + __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ + __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ + __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ + __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ + __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ + __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ + uint32_t : 1; + __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ + __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ + __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ + __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ + __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ + __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ + __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ + uint32_t : 1; + } MRWCSR_b; + }; + + union + { + __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ + + struct + { + __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ + __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ + uint32_t : 16; + } ESR_b; + }; + + union + { + __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ + + struct + { + __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ + } CWNDR_b; + }; + + union + { + __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ + + struct + { + __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ + __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ + __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ + __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ + } CWDR_b; + }; + + union + { + __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ + + struct + { + __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ + __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ + __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ + __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ + } CRR_b; + }; + + union + { + __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ + + struct + { + __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ + __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ + uint32_t : 26; + } ACSR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ + + struct + { + __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are + * Low in single continuous write of OctaRAM. */ + uint32_t : 7; + __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 + * are Low in single continuous read of OctaRAM. */ + uint32_t : 7; + } DCSMXR_b; + }; + + union + { + __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating + * size Register */ + + struct + { + __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single + * continuous write of device 0. */ + uint32_t : 5; + __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single + * continuous write of device 1. */ + uint32_t : 5; + } DWSCTSR_b; + }; +} R_OSPI_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CRC_BASE 0x40108000UL + #define R_CTSU_BASE 0x400D0000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_ETHERC0_BASE 0x40114100UL + #define R_ETHERC_EDMAC_BASE 0x40114000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + #define R_OSPI_BASE 0x400A6000UL + #define R_USB_HS0_BASE 0x40111000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DCR ========================================================== */ + #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ + #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ + #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ +/* ========================================================== DAR ========================================================== */ + #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ + #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ + #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ + #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ + #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= DCSR ========================================================== */ + #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ + #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ + #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ + #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ + #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ + #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ + #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ + #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ + #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ + #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DSR ========================================================== */ + #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ + #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ + #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ + #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ +/* ========================================================= MDTR ========================================================== */ + #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ + #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ + #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ + #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ + #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ + #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ +/* ========================================================= ACTR ========================================================== */ + #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ + #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ACAR ========================================================== */ + #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ + #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DRCSTR ========================================================= */ + #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ + #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ + #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ + #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ + #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ + #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ + #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ + #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ + #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ +/* ======================================================== DWCSTR ========================================================= */ + #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ + #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ + #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ + #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ + #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ + #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ + #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ + #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ + #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ + #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ + #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ +/* ========================================================= DCSTR ========================================================= */ + #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ + #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ + #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ + #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ +/* ========================================================= CDSR ========================================================== */ + #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ + #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ + #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ + #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ + #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ + #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ + #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ + #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ + #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ +/* ========================================================= MDLR ========================================================== */ + #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ + #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ + #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ + #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ + #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ +/* ========================================================= MRWCR ========================================================= */ + #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ + #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ + #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ + #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ + #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ +/* ======================================================== MRWCSR ========================================================= */ + #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ + #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ + #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ + #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ + #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ + #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ + #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ + #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ + #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ + #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ + #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ + #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ + #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ + #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ + #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ESR ========================================================== */ + #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ + #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ + #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ + #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ +/* ========================================================= CWNDR ========================================================= */ + #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ + #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CWDR ========================================================== */ + #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ + #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ + #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ + #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ + #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ +/* ========================================================== CRR ========================================================== */ + #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ + #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ + #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ + #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ + #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= ACSR ========================================================== */ + #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ + #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ + #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ +/* ======================================================== DCSMXR ========================================================= */ + #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ + #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ + #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ + #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DWSCTSR ======================================================== */ + #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ + #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ + #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ + #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M4AF_H */ + +/** @} */ /* End of group R7FA6M4AF */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h new file mode 100644 index 00000000..b1bf2554 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -0,0 +1,27152 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file svd-test/R7FA6M5BH.h + * @brief CMSIS HeaderFile + * @version 1.10.08 + * @date 23. June 2022 + * @note Generated by SVDConv V3.3.35 on Thursday, 23.06.2022 19:51:09 + * from File 'svd-test/R7FA6M5BH.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA6M5BH + * @{ + */ + +#ifndef R7FA6M5BH_H + #define R7FA6M5BH_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA6M5BH System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ + __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ + __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register) + */ +typedef struct +{ + union + { + __IOM uint8_t RTCCR; /*!< (@ 0x00000000) Time Capture Control Register */ + + struct + { + __IOM uint8_t TCCT : 2; /*!< [1..0] Time Capture Control */ + __IM uint8_t TCST : 1; /*!< [2..2] Time Capture Status */ + uint8_t : 1; + __IOM uint8_t TCNF : 2; /*!< [5..4] Time Capture Noise Filter Control */ + uint8_t : 2; + } RTCCR_b; + }; + __IM uint8_t RESERVED; +} R_RTC_RTCCR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_RTC_CP [CP] (Capture registers) + */ +typedef struct +{ + __IM uint8_t RESERVED[2]; + + union + { + union + { + __IM uint8_t RSEC; /*!< (@ 0x00000002) Second Capture Register */ + + struct + { + __IM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Capture Capture value for the ones place of + * seconds */ + __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of + * seconds */ + uint8_t : 1; + } RSEC_b; + }; + + union + { + __IM uint8_t BCNT0; /*!< (@ 0x00000002) BCNT0 Capture Register */ + + struct + { + __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0 + * value when a time capture event is detected. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IM uint8_t RMIN; /*!< (@ 0x00000004) Minute Capture Register */ + + struct + { + __IM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + uint8_t : 1; + } RMIN_b; + }; + + union + { + __IM uint8_t BCNT1; /*!< (@ 0x00000004) BCNT1 Capture Register */ + + struct + { + __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1 + * value when a time capture event is detected. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IM uint8_t RHR; /*!< (@ 0x00000006) Hour Capture Register */ + + struct + { + __IM uint8_t HR1 : 4; /*!< [3..0] 1-Minute Capture Capture value for the ones place of + * minutes */ + __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of + * minutes */ + __IM uint8_t PM : 1; /*!< [6..6] A.m./p.m. select for time counter setting. */ + uint8_t : 1; + } RHR_b; + }; + + union + { + __IM uint8_t BCNT2; /*!< (@ 0x00000006) BCNT2 Capture Register */ + + struct + { + __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2 + * value when a time capture event is detected. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3[3]; + + union + { + union + { + __IM uint8_t RDAY; /*!< (@ 0x0000000A) Date Capture Register */ + + struct + { + __IM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes */ + __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes */ + uint8_t : 2; + } RDAY_b; + }; + + union + { + __IM uint8_t BCNT3; /*!< (@ 0x0000000A) BCNT3 Capture Register */ + + struct + { + __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3 + * value when a time capture event is detected. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IM uint8_t RMON; /*!< (@ 0x0000000C) Month Capture Register */ + + struct + { + __IM uint8_t MON1 : 4; /*!< [3..0] 1-Month Capture Capture value for the ones place of months */ + __IM uint8_t MON10 : 1; /*!< [4..4] 10-Month Capture Capture value for the tens place of + * months */ + uint8_t : 3; + } RMON_b; + }; + __IM uint8_t RESERVED5[3]; +} R_RTC_CP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) Pipe Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USB_FS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows + * clearing the transaction counter to 0. */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter EnableEnables or disables the transaction + * counter function. */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPE Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number + * of total packets (number of transactions) to be received + * by the relevant PIPE.When read from: When TRENB = 0: Indicate + * the specified number of transactions.When TRENB = 1: Indicate + * the number of currently counted transactions. */ + } N_b; + }; +} R_USB_HS0_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED[25]; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 2; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ + uint32_t : 14; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ + __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + uint32_t : 1; + __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ + __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ + uint32_t : 6; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement + * Registers */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; + + union + { + __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint32_t RESERVED6[18]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint32_t RESERVED8[288]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint32_t RESERVED9[288]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ + uint32_t : 24; + } CFDTMTRSTS_b[4]; + }; + __IM uint32_t RESERVED10[36]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 24; + } CFDTMTARSTS_b[4]; + }; + __IM uint32_t RESERVED11[36]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 24; + } CFDTMTCSTS_b[4]; + }; + __IM uint32_t RESERVED12[36]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ + uint32_t : 24; + } CFDTMTASTS_b[4]; + }; + __IM uint32_t RESERVED13[36]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ + uint32_t : 24; + } CFDTMIEC_b[4]; + }; + __IM uint32_t RESERVED14[40]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS0_b[2]; + }; + __IM uint32_t RESERVED16[6]; + + union + { + __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS1_b[2]; + }; + __IM uint32_t RESERVED19[6]; + + union + { + __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint32_t RESERVED20[6]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS2_b[2]; + }; + __IM uint32_t RESERVED22[6]; + + union + { + __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint32_t RESERVED24[6]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 13; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; + + union + { + __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint32_t RESERVED26[6]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint32_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint32_t RESERVED29[6]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint32_t RESERVED30[6]; + + union + { + __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint32_t RESERVED31[46]; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + + union + { + __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */ + + struct + { + __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */ + uint32_t : 31; + } CFDGCRCCFG_b; + }; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + + union + { + __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ + + struct + { + __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ + uint32_t : 7; + __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ + __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ + __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ + __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ + uint32_t : 16; + } CFDGLOTB_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ + uint32_t : 7; + __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ + uint32_t : 13; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + __IM uint32_t RESERVED34; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint32_t RESERVED37[10]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED38[31]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED39[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED40[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED41[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED42[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED43[252]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED44[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Capacitive Touch Sensing Unit (R_CTSU) + */ + +typedef struct /*!< (@ 0x400D0000) R_CTSU Structure */ +{ + union + { + __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register 0 */ + + struct + { + __IOM uint8_t CTSUSTRT : 1; /*!< [0..0] CTSU Measurement Operation Start */ + __IOM uint8_t CTSUCAP : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select */ + __IOM uint8_t CTSUSNZ : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable */ + __IOM uint8_t CTSUIOC : 1; /*!< [3..3] CTSU Transmit Pin Control */ + __IOM uint8_t CTSUINIT : 1; /*!< [4..4] CTSU Control Block Initialization */ + uint8_t : 2; + __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection */ + } CTSUCR0_b; + }; + + union + { + __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register 1 */ + + struct + { + __IOM uint8_t CTSUPON : 1; /*!< [0..0] CTSU Power Supply Enable */ + __IOM uint8_t CTSUCSW : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control */ + __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting */ + __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment */ + __IOM uint8_t CTSUCLK : 2; /*!< [5..4] CTSU Operating Clock Select */ + __IOM uint8_t CTSUMD : 2; /*!< [7..6] CTSU Measurement Mode Select */ + } CTSUCR1_b; + }; + + union + { + __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register */ + + struct + { + __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended + * setting: 3 (0011b) */ + __IOM uint8_t CTSUPRMODE : 2; /*!< [5..4] CTSU Base Period and Pulse Count Setting */ + __IOM uint8_t CTSUSOFF : 1; /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting */ + uint8_t : 1; + } CTSUSDPRS_b; + }; + + union + { + __IOM uint8_t CTSUSST; /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register */ + + struct + { + __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value + * of these bits should be fixed to 00010000b. */ + } CTSUSST_b; + }; + + union + { + __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000004) CTSU Measurement Channel Register 0 */ + + struct + { + __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits + * is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] + * bits = 00b).Note2: If the value of CTSUMCH0 was set to + * b'111111 in mode other than self-capacitor single scan + * mode, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH0_b; + }; + + union + { + __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000005) CTSU Measurement Channel Register 1 */ + + struct + { + __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 + * was set to b'111111, the measurement is stopped. */ + uint8_t : 2; + } CTSUMCH1_b; + }; + + union + { + __IOM uint8_t CTSUCHAC[5]; /*!< (@ 0x00000006) CTSU Channel Enable Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Enable Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Enable Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Enable Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Enable Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Enable Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Enable Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Enable Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Enable Control */ + } CTSUCHAC_b[5]; + }; + + union + { + __IOM uint8_t CTSUCHTRC[5]; /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register */ + + struct + { + __IOM uint8_t TS0 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS1 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS2 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS3 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS4 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS5 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS6 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control */ + __IOM uint8_t TS7 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control */ + } CTSUCHTRC_b[5]; + }; + + union + { + __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register */ + + struct + { + __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should + * be set to 00b. */ + uint8_t : 2; + __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should + * be set to 11b. */ + uint8_t : 2; + } CTSUDCLKC_b; + }; + + union + { + __IOM uint8_t CTSUST; /*!< (@ 0x00000011) CTSU Status Register */ + + struct + { + __IM uint8_t CTSUSTC : 3; /*!< [2..0] CTSU Measurement Status Counter */ + uint8_t : 1; + __IM uint8_t CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag */ + __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag */ + __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag */ + __IM uint8_t CTSUPS : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag */ + } CTSUST_b; + }; + + union + { + __IOM uint16_t CTSUSSC; /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion + * Control Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting */ + uint16_t : 4; + } CTSUSSC_b; + }; + + union + { + __IOM uint16_t CTSUSO0; /*!< (@ 0x00000014) CTSU Sensor Offset Register 0 */ + + struct + { + __IOM uint16_t CTSUSO : 10; /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is + * CTSUSO ( 0 to 1023 ) */ + __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting */ + } CTSUSO0_b; + }; + + union + { + __IOM uint16_t CTSUSO1; /*!< (@ 0x00000016) CTSU Sensor Offset Register 1 */ + + struct + { + __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount + * is CTSUSO ( 0 to 255 ) */ + __IOM uint16_t CTSUSDPA : 5; /*!< [12..8] CTSU Base Clock SettingOperating clock divided by ( + * CTSUSDPA + 1 ) x 2 */ + __IOM uint16_t CTSUICOG : 2; /*!< [14..13] CTSU ICO Gain Adjustment */ + uint16_t : 1; + } CTSUSO1_b; + }; + + union + { + __IM uint16_t CTSUSC; /*!< (@ 0x00000018) CTSU Sensor Counter */ + + struct + { + __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement + * result of the CTSU. These bits indicate FFFFh when an overflow + * occurs. */ + } CTSUSC_b; + }; + + union + { + __IM uint16_t CTSURC; /*!< (@ 0x0000001A) CTSU Reference Counter */ + + struct + { + __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement + * result of the reference ICO.These bits indicate FFFFh when + * an overflow occurs. */ + } CTSURC_b; + }; + + union + { + __IM uint16_t CTSUERRS; /*!< (@ 0x0000001C) CTSU Error Status Register */ + + struct + { + __IOM uint16_t CTSUSPMD : 2; /*!< [1..0] Calibration Mode */ + __IOM uint16_t CTSUTSOD : 1; /*!< [2..2] TS Pin Fixed Output */ + __IOM uint16_t CTSUDRV : 1; /*!< [3..3] Calibration Setting 1 */ + uint16_t : 2; + __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3 */ + __IOM uint16_t CTSUTSOC : 1; /*!< [7..7] Calibration Setting 2 */ + uint16_t : 7; + __IM uint16_t CTSUICOMP : 1; /*!< [15..15] TSCAP Voltage Error Monitor */ + } CTSUERRS_b; + }; + __IM uint16_t RESERVED; + __IOM uint8_t CTSUTRMR; /*!< (@ 0x00000020) CTSU Reference Current Calibration Register */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_CTSU_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40171000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC Controller (R_ETHERC0) + */ + +typedef struct /*!< (@ 0x40114100) R_ETHERC0 Structure */ +{ + union + { + __IOM uint32_t ECMR; /*!< (@ 0x00000000) ETHERC Mode Register */ + + struct + { + __IOM uint32_t PRM : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t DM : 1; /*!< [1..1] Duplex Mode */ + __IOM uint32_t RTM : 1; /*!< [2..2] Bit Rate */ + __IOM uint32_t ILB : 1; /*!< [3..3] Internal Loopback Mode */ + uint32_t : 1; + __IOM uint32_t TE : 1; /*!< [5..5] Transmission Enable */ + __IOM uint32_t RE : 1; /*!< [6..6] Reception Enable */ + uint32_t : 2; + __IOM uint32_t MPDE : 1; /*!< [9..9] Magic Packet Detection Enable */ + uint32_t : 2; + __IOM uint32_t PRCEF : 1; /*!< [12..12] CRC Error Frame Receive Mode */ + uint32_t : 3; + __IOM uint32_t TXF : 1; /*!< [16..16] Transmit Flow Control Operating Mode */ + __IOM uint32_t RXF : 1; /*!< [17..17] Receive Flow Control Operating Mode */ + __IOM uint32_t PFR : 1; /*!< [18..18] PAUSE Frame Receive Mode */ + __IOM uint32_t ZPF : 1; /*!< [19..19] 0 Time PAUSE Frame Enable */ + __IOM uint32_t TPC : 1; /*!< [20..20] PAUSE Frame Transmit */ + uint32_t : 11; + } ECMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RFLR; /*!< (@ 0x00000008) Receive Frame Maximum Length Register */ + + struct + { + __IOM uint32_t RFL : 12; /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the + * maximum frame length. The minimum value that can be set + * is 1,518 bytes, and the maximum value that can be set is + * 2,048 bytes. Values that are less than 1,518 bytes are + * regarded as 1,518 bytes, and values larger than 2,048 bytes + * are regarded as 2,048 bytes. */ + uint32_t : 20; + } RFLR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t ECSR; /*!< (@ 0x00000010) ETHERC Status Register */ + + struct + { + __IOM uint32_t ICD : 1; /*!< [0..0] False Carrier Detect Flag */ + __IOM uint32_t MPD : 1; /*!< [1..1] Magic Packet Detect Flag */ + __IOM uint32_t LCHNG : 1; /*!< [2..2] LCHNG Link Signal Change Flag */ + uint32_t : 1; + __IOM uint32_t PSRTO : 1; /*!< [4..4] PAUSE Frame Retransmit Over Flag */ + __IOM uint32_t BFR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Flag */ + uint32_t : 26; + } ECSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ECSIPR; /*!< (@ 0x00000018) ETHERC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ICDIP : 1; /*!< [0..0] False Carrier Detect Interrupt Enable */ + __IOM uint32_t MPDIP : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable */ + __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable */ + __IOM uint32_t BFSIPR : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable */ + uint32_t : 26; + } ECSIPR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PIR; /*!< (@ 0x00000020) PHY Interface Register */ + + struct + { + __IOM uint32_t MDC : 1; /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output + * from the ETn_MDC pin to supply the management data clock + * to the MII or RMII. */ + __IOM uint32_t MMD : 1; /*!< [1..1] MII/RMII Management Mode */ + __IOM uint32_t MDO : 1; /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output + * from the ETn_MDIO pin when the MMD bit is 1 (write). The + * value is not output when the MMD bit is 0 (read). */ + __IM uint32_t MDI : 1; /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level + * of the ETn_MDIO pin. The write value should be 0. */ + uint32_t : 28; + } PIR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t PSR; /*!< (@ 0x00000028) PHY Status Register */ + + struct + { + __IM uint32_t LMON : 1; /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read + * by connecting the link signal output from the PHY-LSI to + * the ETn_LINKSTA pin. For details on the polarity, refer + * to the specifications of the connected PHY-LSI. */ + uint32_t : 31; + } PSR_b; + }; + __IM uint32_t RESERVED5[5]; + + union + { + __IOM uint32_t RDMLR; /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit + * Setting Register */ + + struct + { + __IOM uint32_t RMD : 20; /*!< [19..0] Random Number Generation Counter */ + uint32_t : 12; + } RDMLR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t IPGR; /*!< (@ 0x00000050) IPG Register */ + + struct + { + __IOM uint32_t IPG : 5; /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)' */ + uint32_t : 27; + } IPGR_b; + }; + + union + { + __IOM uint32_t APR; /*!< (@ 0x00000054) Automatic PAUSE Frame Register */ + + struct + { + __IOM uint32_t AP : 16; /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value + * of the pause_time parameter for a PAUSE frame that is automatically + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. */ + uint32_t : 16; + } APR_b; + }; + + union + { + __OM uint32_t MPR; /*!< (@ 0x00000058) Manual PAUSE Frame Register */ + + struct + { + __OM uint32_t MP : 16; /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of + * the pause_time parameter for a PAUSE frame that is manually + * transmitted. Transmission is not performed until the set + * value multiplied by 512 bit time has elapsed. The read + * value is undefined. */ + uint32_t : 16; + } MPR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IM uint32_t RFCF; /*!< (@ 0x00000060) Received PAUSE Frame Counter */ + + struct + { + __IM uint32_t RPAUSE : 8; /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames */ + uint32_t : 24; + } RFCF_b; + }; + + union + { + __IOM uint32_t TPAUSER; /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register */ + + struct + { + __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting */ + uint32_t : 16; + } TPAUSER_b; + }; + __IM uint32_t TPAUSECR; /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter */ + + union + { + __IOM uint32_t BCFRR; /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register */ + + struct + { + __IOM uint32_t BCF : 16; /*!< [15..0] Broadcast Frame Continuous Receive Count Setting */ + uint32_t : 16; + } BCFRR_b; + }; + __IM uint32_t RESERVED8[20]; + + union + { + __IOM uint32_t MAHR; /*!< (@ 0x000000C0) MAC Address Upper Bit Register */ + + struct + { + __IOM uint32_t MAHR : 32; /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets + * the upper 32 bits (b47 to b16) of the 48-bit MAC address. */ + } MAHR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t MALR; /*!< (@ 0x000000C8) MAC Address Lower Bit Register */ + + struct + { + __IOM uint32_t MALR : 16; /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets + * the lower 16 bits of the 48-bit MAC address. */ + uint32_t : 16; + } MALR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t TROCR; /*!< (@ 0x000000D0) Transmit Retry Over Counter Register */ + + struct + { + __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register + * is a counter indicating the number of frames that fail + * to be retransmitted. */ + } TROCR_b; + }; + __IOM uint32_t CDCR; /*!< (@ 0x000000D4) Late Collision Detect Counter Register */ + + union + { + __IOM uint32_t LCCR; /*!< (@ 0x000000D8) Lost Carrier Counter Register */ + + struct + { + __IOM uint32_t LCCR : 32; /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a + * counter indicating the number of times a loss of carrier + * is detected during frame transmission. */ + } LCCR_b; + }; + + union + { + __IOM uint32_t CNDCR; /*!< (@ 0x000000DC) Carrier Not Detect Counter Register */ + + struct + { + __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register + * is a counter indicating the number of times a carrier is + * not detected during preamble transmission. */ + } CNDCR_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t CEFCR; /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register */ + + struct + { + __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register + * is a counter indicating the number of received frames where + * a CRC error has been detected. */ + } CEFCR_b; + }; + + union + { + __IOM uint32_t FRECR; /*!< (@ 0x000000E8) Frame Receive Error Counter Register */ + + struct + { + __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register + * is a counter indicating the number of times a frame receive + * error has occurred. */ + } FRECR_b; + }; + + union + { + __IOM uint32_t TSFRCR; /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register + * is a counter indicating the number of times a short frame + * that is shorter than 64 bytes has been received. */ + } TSFRCR_b; + }; + + union + { + __IOM uint32_t TLFRCR; /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register */ + + struct + { + __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register + * is a counter indicating the number of times a long frame + * that is longer than the RFLR register value has been received. */ + } TLFRCR_b; + }; + + union + { + __IOM uint32_t RFCR; /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register */ + + struct + { + __IOM uint32_t RFCR : 32; /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR + * register is a counter indicating the number of times a + * frame has been received with the alignment error (frame + * is not an integral number of octets). */ + } RFCR_b; + }; + + union + { + __IOM uint32_t MAFCR; /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register */ + + struct + { + __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe + * MAFCR register is a counter indicating the number of times + * a frame where the multicast address is set has been received. */ + } MAFCR_b; + }; +} R_ETHERC0_Type; /*!< Size = 252 (0xfc) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet DMA Controller (R_ETHERC_EDMAC) + */ + +typedef struct /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure */ +{ + union + { + __IOM uint32_t EDMR; /*!< (@ 0x00000000) EDMAC Mode Register */ + + struct + { + __OM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + uint32_t : 3; + __IOM uint32_t DL : 2; /*!< [5..4] Transmit/Receive DescriptorLength */ + __IOM uint32_t DE : 1; /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting + * applies to data for the transmit/receive buffer. It does + * not apply to transmit/receive descriptors and registers. */ + uint32_t : 25; + } EDMR_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t EDTRR; /*!< (@ 0x00000008) EDMAC Transmit Request Register */ + + struct + { + __OM uint32_t TR : 1; /*!< [0..0] Transmit Request */ + uint32_t : 31; + } EDTRR_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t EDRRR; /*!< (@ 0x00000010) EDMAC Receive Request Register */ + + struct + { + __IOM uint32_t RR : 1; /*!< [0..0] Receive Request */ + uint32_t : 31; + } EDRRR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t TDLAR; /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } TDLAR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t RDLAR; /*!< (@ 0x00000020) Receive Descriptor List Start Address Register */ + + struct + { + __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is + * set. Set the start address according to the descriptor + * length selected by the EDMR.DL[1:0] bits.16-byte boundary: + * Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte + * boundary: Lower 6 bits = 000000b */ + } RDLAR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t EESR; /*!< (@ 0x00000028) ETHERC/EDMAC Status Register */ + + struct + { + __IOM uint32_t CERF : 1; /*!< [0..0] CRC Error Flag */ + __IOM uint32_t PRE : 1; /*!< [1..1] PHY-LSI Receive Error Flag */ + __IOM uint32_t RTSF : 1; /*!< [2..2] Frame-Too-Short Error Flag */ + __IOM uint32_t RTLF : 1; /*!< [3..3] Frame-Too-Long Error Flag */ + __IOM uint32_t RRF : 1; /*!< [4..4] Alignment Error Flag */ + uint32_t : 2; + __IOM uint32_t RMAF : 1; /*!< [7..7] Multicast Address Frame Receive Flag */ + __IOM uint32_t TRO : 1; /*!< [8..8] Transmit Retry Over Flag */ + __IOM uint32_t CD : 1; /*!< [9..9] Late Collision Detect Flag */ + __IOM uint32_t DLC : 1; /*!< [10..10] Loss of Carrier Detect Flag */ + __IOM uint32_t CND : 1; /*!< [11..11] Carrier Not Detect Flag */ + uint32_t : 4; + __IOM uint32_t RFOF : 1; /*!< [16..16] Receive FIFO Overflow Flag */ + __IOM uint32_t RDE : 1; /*!< [17..17] Receive Descriptor Empty Flag */ + __IOM uint32_t FR : 1; /*!< [18..18] Frame Receive Flag */ + __IOM uint32_t TFUF : 1; /*!< [19..19] Transmit FIFO Underflow Flag */ + __IOM uint32_t TDE : 1; /*!< [20..20] Transmit Descriptor Empty Flag */ + __IOM uint32_t TC : 1; /*!< [21..21] Frame Transfer Complete Flag */ + __IM uint32_t ECI : 1; /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source + * in the ETHERCn.ECSR register is cleared, the ECI flag is + * also cleared. */ + __IOM uint32_t ADE : 1; /*!< [23..23] Address Error Flag */ + __IOM uint32_t RFCOF : 1; /*!< [24..24] Receive Frame Counter Overflow Flag */ + __IOM uint32_t RABT : 1; /*!< [25..25] Receive Abort Detect Flag */ + __IOM uint32_t TABT : 1; /*!< [26..26] Transmit Abort Detect Flag */ + uint32_t : 3; + __IOM uint32_t TWB : 1; /*!< [30..30] Write-Back Complete Flag */ + uint32_t : 1; + } EESR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t EESIPR; /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register */ + + struct + { + __IOM uint32_t CERFIP : 1; /*!< [0..0] CRC Error Interrupt Request Enable */ + __IOM uint32_t PREIP : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable */ + __IOM uint32_t RTSFIP : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable */ + __IOM uint32_t RTLFIP : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable */ + __IOM uint32_t RRFIP : 1; /*!< [4..4] Alignment Error Interrupt Request Enable */ + uint32_t : 2; + __IOM uint32_t RMAFIP : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable */ + __IOM uint32_t TROIP : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable */ + __IOM uint32_t CDIP : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable */ + __IOM uint32_t DLCIP : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable */ + __IOM uint32_t CNDIP : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable */ + uint32_t : 4; + __IOM uint32_t RFOFIP : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable */ + __IOM uint32_t RDEIP : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t FRIP : 1; /*!< [18..18] Frame Receive Interrupt Request Enable */ + __IOM uint32_t TFUFIP : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable */ + __IOM uint32_t TDEIP : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable */ + __IOM uint32_t TCIP : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable */ + __IOM uint32_t ECIIP : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable */ + __IOM uint32_t ADEIP : 1; /*!< [23..23] Address Error Interrupt Request Enable */ + __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable */ + __IOM uint32_t RABTIP : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable */ + __IOM uint32_t TABTIP : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable */ + uint32_t : 3; + __IOM uint32_t TWBIP : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable */ + uint32_t : 1; + } EESIPR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t TRSCER; /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable + * Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t RRFCE : 1; /*!< [4..4] RRF Flag Copy Enable */ + uint32_t : 2; + __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable */ + uint32_t : 24; + } TRSCER_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t RMFCR; /*!< (@ 0x00000040) Missed-Frame Counter Register */ + + struct + { + __IOM uint32_t MFC : 16; /*!< [15..0] Missed-Frame CounterThese bits indicate the number of + * frames that are discarded and not transferred to the receive + * buffer during reception. */ + uint32_t : 16; + } RMFCR_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t TFTR; /*!< (@ 0x00000048) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t TFT : 11; /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is + * the set value multiplied by 4. Example: 00Dh: 52 bytes + * 040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes */ + uint32_t : 21; + } TFTR_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t FDR; /*!< (@ 0x00000050) Transmit FIFO Threshold Register */ + + struct + { + __IOM uint32_t RFD : 5; /*!< [4..0] Transmit FIFO Depth */ + uint32_t : 3; + __IOM uint32_t TFD : 5; /*!< [12..8] Receive FIFO Depth */ + uint32_t : 19; + } FDR_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t RMCR; /*!< (@ 0x00000058) Receive Method Control Register */ + + struct + { + __IOM uint32_t RNR : 1; /*!< [0..0] Receive Request Reset */ + uint32_t : 31; + } RMCR_b; + }; + __IM uint32_t RESERVED11[2]; + + union + { + __IOM uint32_t TFUCR; /*!< (@ 0x00000064) Transmit FIFO Underflow Counter */ + + struct + { + __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how + * many times the transmit FIFO has underflowed. The counter + * stops when the counter value reaches FFFFh. */ + uint32_t : 16; + } TFUCR_b; + }; + + union + { + __IOM uint32_t RFOCR; /*!< (@ 0x00000068) Receive FIFO Overflow Counter */ + + struct + { + __IOM uint32_t OVER : 16; /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many + * times the receive FIFO has overflowed. The counter stops + * when the counter value reaches FFFFh. */ + uint32_t : 16; + } RFOCR_b; + }; + + union + { + __IOM uint32_t IOSR; /*!< (@ 0x0000006C) Independent Output Signal Setting Register */ + + struct + { + __IOM uint32_t ELB : 1; /*!< [0..0] External Loopback Mode */ + uint32_t : 31; + } IOSR_b; + }; + + union + { + __IOM uint32_t FCFTR; /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register */ + + struct + { + __IOM uint32_t RFDO : 3; /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32 + * bytes of data is stored in the receive FIFO.) */ + uint32_t : 13; + __IOM uint32_t RFFO : 3; /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2) + * receive frames have been stored in the receive FIFO.) */ + uint32_t : 13; + } FCFTR_b; + }; + __IM uint32_t RESERVED12; + + union + { + __IOM uint32_t RPADIR; /*!< (@ 0x00000078) Receive Data Padding Insert Register */ + + struct + { + __IOM uint32_t PADR : 6; /*!< [5..0] Padding Slot */ + uint32_t : 10; + __IOM uint32_t PADS : 2; /*!< [17..16] Padding Size */ + uint32_t : 14; + } RPADIR_b; + }; + + union + { + __IOM uint32_t TRIMD; /*!< (@ 0x0000007C) Transmit Interrupt Setting Register */ + + struct + { + __IOM uint32_t TIS : 1; /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in + * the mode selected by the TIM bit to notify an interrupt. */ + uint32_t : 3; + __IOM uint32_t TIM : 1; /*!< [4..4] Transmit Interrupt Mode */ + uint32_t : 27; + } TRIMD_b; + }; + __IM uint32_t RESERVED13[18]; + + union + { + __IOM uint32_t RBWAR; /*!< (@ 0x000000C8) Receive Buffer Write Address Register */ + + struct + { + __IM uint32_t RBWAR : 32; /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register + * indicates the last address that the EDMAC has written data + * to when writing to the receive buffer.Refer to the address + * indicated by the RBWAR register to recognize which address + * in the receive buffer the EDMAC is writing data to. Note + * that the address that the EDMAC is outputting to the receive + * buffer may not match the read value of the RBWAR register + * during data reception. */ + } RBWAR_b; + }; + + union + { + __IOM uint32_t RDFAR; /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t RDFAR : 32; /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register + * indicates the start address of the last fetched receive + * descriptor when the EDMAC fetches descriptor information + * from the receive descriptor.Refer to the address indicated + * by the RDFAR register to recognize which receive descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the receive descriptor that the + * EDMAC fetches may not match the read value of the RDFAR + * register during data reception. */ + } RDFAR_b; + }; + __IM uint32_t RESERVED14; + + union + { + __IOM uint32_t TBRAR; /*!< (@ 0x000000D4) Transmit Buffer Read Address Register */ + + struct + { + __IM uint32_t TBRAR : 32; /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register + * indicates the last address that the EDMAC has read data + * from when reading data from the transmit buffer.Refer to + * the address indicated by the TBRAR register to recognize + * which address in the transmit buffer the EDMAC is reading + * from. Note that the address that the EDMAC is outputting + * to the transmit buffer may not match the read value of + * the TBRAR register. */ + } TBRAR_b; + }; + + union + { + __IM uint32_t TDFAR; /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register */ + + struct + { + __IM uint32_t TDFAR : 32; /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR + * register indicates the start address of the last fetched + * transmit descriptor when the EDMAC fetches descriptor information + * from the transmit descriptor.Refer to the address indicated + * by the TDFAR register to recognize which transmit descriptor + * information the EDMAC is using for the current processing. + * Note that the address of the transmit descriptor that the + * EDMAC fetches may not match the read value of the TDFAR + * register. */ + } TDFAR_b; + }; +} R_ETHERC_EDMAC_Type; /*!< Size = 220 (0xdc) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED30[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40080000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40080D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Quad Serial Peripheral Interface (R_QSPI) + */ + +typedef struct /*!< (@ 0x64000000) R_QSPI Structure */ +{ + union + { + __IOM uint32_t SFMSMD; /*!< (@ 0x00000000) Transfer Mode Control Register */ + + struct + { + __IOM uint32_t SFMRM : 3; /*!< [2..0] Serial interface read mode selection */ + uint32_t : 1; + __IOM uint32_t SFMSE : 2; /*!< [5..4] Selection of the prefetch function */ + __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function */ + __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations + * other than on byte boundaries */ + __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by + * input to CFGMD3. */ + __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for + * the serial interface */ + __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission */ + __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission */ + uint32_t : 3; + __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection. */ + uint32_t : 16; + } SFMSMD_b; + }; + + union + { + __IOM uint32_t SFMSSC; /*!< (@ 0x00000004) Chip Selection Control Register */ + + struct + { + __IOM uint32_t SFMSW : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal */ + __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection */ + __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection */ + uint32_t : 26; + } SFMSSC_b; + }; + + union + { + __IOM uint32_t SFMSKC; /*!< (@ 0x00000008) Clock Control Register */ + + struct + { + __IOM uint32_t SFMDV : 5; /*!< [4..0] Serial interface reference cycle selection (* Pay attention + * to the irregularity.)NOTE: When PCLKA multiplied by an + * odd number is selected, the high-level width of the SCK + * signal is longer than the low-level width by 1 x PCLKA + * before duty ratio correction. */ + __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the + * SCK signal */ + uint32_t : 26; + } SFMSKC_b; + }; + + union + { + __IM uint32_t SFMSST; /*!< (@ 0x0000000C) Status Register */ + + struct + { + __IM uint32_t PFCNT : 5; /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010 + * (No combination other than the above is available.) */ + uint32_t : 1; + __IM uint32_t PFFUL : 1; /*!< [6..6] Prefetch buffer state */ + __IM uint32_t PFOFF : 1; /*!< [7..7] Prefetch function operation state */ + uint32_t : 24; + } SFMSST_b; + }; + + union + { + __IOM uint32_t SFMCOM; /*!< (@ 0x00000010) Communication Port Register */ + + struct + { + __IOM uint32_t SFMD : 8; /*!< [7..0] Port for direct communication with the SPI bus.Input/output + * to and from this port is converted to a SPIbus cycle. This + * port is accessible in the direct communication mode (DCOM=1) + * only.Access to this port is ignored in the ROM access mode. */ + uint32_t : 24; + } SFMCOM_b; + }; + + union + { + __IOM uint32_t SFMCMD; /*!< (@ 0x00000014) Communication Mode Control Register */ + + struct + { + __IOM uint32_t DCOM : 1; /*!< [0..0] Selection of a mode of communication with the SPI bus */ + uint32_t : 31; + } SFMCMD_b; + }; + + union + { + __IOM uint32_t SFMCST; /*!< (@ 0x00000018) Communication Status Register */ + + struct + { + __IM uint32_t COMBSY : 1; /*!< [0..0] SPI bus cycle completion state in direct communication */ + uint32_t : 6; + __IM uint32_t EROMR : 1; /*!< [7..7] Status of ROM access detection in the direct communication + * modeNOTE: Writing of 0 only is possible. Writing of 1 is + * ignored. */ + uint32_t : 24; + } SFMCST_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SFMSIC; /*!< (@ 0x00000020) Instruction Code Register */ + + struct + { + __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute */ + uint32_t : 24; + } SFMSIC_b; + }; + + union + { + __IOM uint32_t SFMSAC; /*!< (@ 0x00000024) Address Mode Control Register */ + + struct + { + __IOM uint32_t SFMAS : 2; /*!< [1..0] Selection the number of address bits of the serial interface */ + uint32_t : 2; + __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial + * Interface address width is selected 4 bytes. */ + uint32_t : 27; + } SFMSAC_b; + }; + + union + { + __IOM uint32_t SFMSDC; /*!< (@ 0x00000028) Dummy Cycle Control Register */ + + struct + { + __IOM uint32_t SFMDN : 4; /*!< [3..0] Selection of the number of dummy cycles of Fast Read + * instructions */ + uint32_t : 2; + __IM uint32_t SFMXST : 1; /*!< [6..6] XIP mode status */ + __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission */ + __IOM uint32_t SFMXD : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode) */ + uint32_t : 16; + } SFMSDC_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t SFMSPC; /*!< (@ 0x00000030) SPI Protocol Control Register */ + + struct + { + __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol + * is required to be set by software separately. */ + uint32_t : 2; + __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch, + * when Dual SPI protocol or Quad SPI protocol is selected. */ + uint32_t : 27; + } SFMSPC_b; + }; + + union + { + __IOM uint32_t SFMPMD; /*!< (@ 0x00000034) Port Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin */ + uint32_t : 29; + } SFMPMD_b; + }; + __IM uint32_t RESERVED2[499]; + + union + { + __IOM uint32_t SFMCNT1; /*!< (@ 0x00000804) External QSPI Address Register 1 */ + + struct + { + uint32_t : 26; + __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000 + * to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order + * 6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited. */ + } SFMCNT1_b; + }; +} R_QSPI_Type; /*!< Size = 2056 (0x808) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40083000) R_RTC Structure */ +{ + union + { + __IM uint8_t R64CNT; /*!< (@ 0x00000000) 64-Hz Counter */ + + struct + { + __IM uint8_t F64HZ : 1; /*!< [0..0] 64Hz */ + __IM uint8_t F32HZ : 1; /*!< [1..1] 32Hz */ + __IM uint8_t F16HZ : 1; /*!< [2..2] 16Hz */ + __IM uint8_t F8HZ : 1; /*!< [3..3] 8Hz */ + __IM uint8_t F4HZ : 1; /*!< [4..4] 4Hz */ + __IM uint8_t F2HZ : 1; /*!< [5..5] 2Hz */ + __IM uint8_t F1HZ : 1; /*!< [6..6] 1Hz */ + uint8_t : 1; + } R64CNT_b; + }; + __IM uint8_t RESERVED; + + union + { + union + { + __IOM uint8_t RSECCNT; /*!< (@ 0x00000002) Second Counter */ + + struct + { + __IOM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting. */ + uint8_t : 1; + } RSECCNT_b; + }; + + union + { + __IOM uint8_t BCNT0; /*!< (@ 0x00000002) Binary Counter 0 */ + + struct + { + __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary + * counter b7 to b0. */ + } BCNT0_b; + }; + }; + __IM uint8_t RESERVED1; + + union + { + union + { + __IOM uint8_t RMINCNT; /*!< (@ 0x00000004) Minute Counter */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting. */ + uint8_t : 1; + } RMINCNT_b; + }; + + union + { + __IOM uint8_t BCNT1; /*!< (@ 0x00000004) Binary Counter 1 */ + + struct + { + __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary + * counter b15 to b8. */ + } BCNT1_b; + }; + }; + __IM uint8_t RESERVED2; + + union + { + union + { + __IOM uint8_t RHRCNT; /*!< (@ 0x00000006) Hour Counter */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from + * the ones place. */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + uint8_t : 1; + } RHRCNT_b; + }; + + union + { + __IOM uint8_t BCNT2; /*!< (@ 0x00000006) Binary Counter 2 */ + + struct + { + __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2_b; + }; + }; + __IM uint8_t RESERVED3; + + union + { + union + { + __IOM uint8_t RWKCNT; /*!< (@ 0x00000008) Day-of-Week Counter */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 5; + } RWKCNT_b; + }; + + union + { + __IOM uint8_t BCNT3; /*!< (@ 0x00000008) Binary Counter 3 */ + + struct + { + __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3_b; + }; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t RDAYCNT; /*!< (@ 0x0000000A) Day Counter */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry + * is generated, 1 is added to the tens place. */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the + * ones place. */ + uint8_t : 2; + } RDAYCNT_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t RMONCNT; /*!< (@ 0x0000000C) Month Counter */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When + * a carry is generated, 1 is added to the tens place. */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from + * the ones place. */ + uint8_t : 3; + } RMONCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint16_t RYRCNT; /*!< (@ 0x0000000E) Year Counter */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a + * carry is generated, 1 is added to the tens place. */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from + * ones place. When a carry is generated in the tens place, + * 1 is added to the hundreds place. */ + uint16_t : 8; + } RYRCNT_b; + }; + + union + { + union + { + __IOM uint8_t RSECAR; /*!< (@ 0x00000010) Second Alarm Register */ + + struct + { + __OM uint8_t SEC1 : 4; /*!< [3..0] 1-Second Value for the ones place of seconds */ + __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RSECAR_b; + }; + + union + { + __IOM uint8_t BCNT0AR; /*!< (@ 0x00000010) Binary Counter 0 Alarm Register */ + + struct + { + __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b7 to b0. */ + } BCNT0AR_b; + }; + }; + __IM uint8_t RESERVED7; + + union + { + union + { + __IOM uint8_t RMINAR; /*!< (@ 0x00000012) Minute Alarm Register */ + + struct + { + __IOM uint8_t MIN1 : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes */ + __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMINAR_b; + }; + + union + { + __IOM uint8_t BCNT1AR; /*!< (@ 0x00000012) Binary Counter 1 Alarm Register */ + + struct + { + __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register + * corresponding to 32-bit binary counter b15 to b8. */ + } BCNT1AR_b; + }; + }; + __IM uint8_t RESERVED8; + + union + { + union + { + __IOM uint8_t RHRAR; /*!< (@ 0x00000014) Hour Alarm Register */ + + struct + { + __IOM uint8_t HR1 : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours */ + __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours */ + __IOM uint8_t PM : 1; /*!< [6..6] Time Counter Setting for a.m./p.m. */ + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RHRAR_b; + }; + + union + { + __IOM uint8_t BCNT2AR; /*!< (@ 0x00000014) Binary Counter 2 Alarm Register */ + + struct + { + __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary + * counter b23 to b16. */ + } BCNT2AR_b; + }; + }; + __IM uint8_t RESERVED9; + + union + { + union + { + __IOM uint8_t RWKAR; /*!< (@ 0x00000016) Day-of-Week Alarm Register */ + + struct + { + __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting */ + uint8_t : 4; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RWKAR_b; + }; + + union + { + __IOM uint8_t BCNT3AR; /*!< (@ 0x00000016) Binary Counter 3 Alarm Register */ + + struct + { + __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary + * counter b31 to b24. */ + } BCNT3AR_b; + }; + }; + __IM uint8_t RESERVED10; + + union + { + union + { + __IOM uint8_t RDAYAR; /*!< (@ 0x00000018) Date Alarm Register */ + + struct + { + __IOM uint8_t DATE1 : 4; /*!< [3..0] 1 Day Value for the ones place of days */ + __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days */ + uint8_t : 1; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RDAYAR_b; + }; + + union + { + __IOM uint8_t BCNT0AER; /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b7 to b0. */ + } BCNT0AER_b; + }; + }; + __IM uint8_t RESERVED11; + + union + { + union + { + __IOM uint8_t RMONAR; /*!< (@ 0x0000001A) Month Alarm Register */ + + struct + { + __IOM uint8_t MON1 : 4; /*!< [3..0] 1 Month Value for the ones place of months */ + __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months */ + uint8_t : 2; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RMONAR_b; + }; + + union + { + __IOM uint8_t BCNT1AER; /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b15 to b8. */ + } BCNT1AER_b; + }; + }; + __IM uint8_t RESERVED12; + + union + { + union + { + __IOM uint16_t RYRAR; /*!< (@ 0x0000001C) Year Alarm Register */ + + struct + { + __IOM uint16_t YR1 : 4; /*!< [3..0] 1 Year Value for the ones place of years */ + __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years */ + uint16_t : 8; + } RYRAR_b; + }; + + union + { + __IOM uint16_t BCNT2AER; /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register */ + + struct + { + __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b23 to b16. */ + uint16_t : 8; + } BCNT2AER_b; + }; + }; + + union + { + union + { + __IOM uint8_t RYRAREN; /*!< (@ 0x0000001E) Year Alarm Enable Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable */ + } RYRAREN_b; + }; + + union + { + __IOM uint8_t BCNT3AER; /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register */ + + struct + { + __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register + * for setting the alarm enable corresponding to 32-bit binary + * counter b31 to b24. */ + } BCNT3AER_b; + }; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t RCR1; /*!< (@ 0x00000022) RTC Control Register 1 */ + + struct + { + __IOM uint8_t AIE : 1; /*!< [0..0] Alarm Interrupt Enable */ + __IOM uint8_t CIE : 1; /*!< [1..1] Carry Interrupt Enable */ + __IOM uint8_t PIE : 1; /*!< [2..2] Periodic Interrupt Enable */ + __IOM uint8_t RTCOS : 1; /*!< [3..3] RTCOUT Output Select */ + __IOM uint8_t PES : 4; /*!< [7..4] Periodic Interrupt Select */ + } RCR1_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) RTC Control Register 2 */ + + struct + { + __IOM uint8_t START : 1; /*!< [0..0] Start */ + __IOM uint8_t RESET : 1; /*!< [1..1] RTC Software Reset */ + __IOM uint8_t ADJ30 : 1; /*!< [2..2] 30-Second Adjustment */ + __IOM uint8_t RTCOE : 1; /*!< [3..3] RTCOUT Output Enable */ + __IOM uint8_t AADJE : 1; /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected, + * the setting of this bit is disabled.) */ + __IOM uint8_t AADJP : 1; /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock + * is selected, the setting of this bit is disabled.) */ + __IOM uint8_t HR24 : 1; /*!< [6..6] Hours Mode */ + __IOM uint8_t CNTMD : 1; /*!< [7..7] Count Mode Select */ + } RCR2_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 6; + __IOM uint8_t ROPSEL : 1; /*!< [7..7] RTC Operation Mode Select */ + } RCR4_b; + }; + __IM uint8_t RESERVED18; + + union + { + __IOM uint16_t RFRH; /*!< (@ 0x0000002A) Frequency Register H */ + + struct + { + __IOM uint16_t RFC16 : 1; /*!< [0..0] Frequency Comparison Value (b16) To generate the operating + * clock from the LOCOclock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + uint16_t : 15; + } RFRH_b; + }; + + union + { + __IOM uint16_t RFRL; /*!< (@ 0x0000002C) Frequency Register L */ + + struct + { + __IOM uint16_t RFC : 16; /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating + * clock from the main clock, this bit sets the comparison + * value of the 128-Hz clock cycle. */ + } RFRL_b; + }; + + union + { + __IOM uint8_t RADJ; /*!< (@ 0x0000002E) Time Error Adjustment Register */ + + struct + { + __IOM uint8_t ADJ : 6; /*!< [5..0] Adjustment Value These bits specify the adjustment value + * from the prescaler. */ + __IOM uint8_t PMADJ : 2; /*!< [7..6] Plus-Minus */ + } RADJ_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20[8]; + __IOM R_RTC_RTCCR_Type RTCCR[3]; /*!< (@ 0x00000040) Time Capture Control Register */ + __IM uint16_t RESERVED21[5]; + __IOM R_RTC_CP_Type CP[3]; /*!< (@ 0x00000050) Capture registers */ +} R_RTC_Type; /*!< Size = 128 (0x80) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SD/MMC Host Interface (R_SDHI0) + */ + +typedef struct /*!< (@ 0x40092000) R_SDHI0 Structure */ +{ + union + { + __IOM uint32_t SD_CMD; /*!< (@ 0x00000000) Command Type Register */ + + struct + { + __IOM uint32_t CMDIDX : 6; /*!< [5..0] Command IndexThese bits specify Command Format[45:40] + * (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18: + * SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101 */ + __IOM uint32_t ACMD : 2; /*!< [7..6] Command Type Select */ + __IOM uint32_t RSPTP : 3; /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used + * in normal mode, see section 1.4.10, Example of SD_CMD Register + * Setting to select mode/response type. */ + __IOM uint32_t CMDTP : 1; /*!< [11..11] Data Mode (Command Type) */ + __IOM uint32_t CMDRW : 1; /*!< [12..12] Write/Read Mode (enabled when the command with data + * is handled) */ + __IOM uint32_t TRSTP : 1; /*!< [13..13] Single/Multiple Block Transfer (enabled when the command + * with data is handled) */ + __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block + * transfer) */ + uint32_t : 16; + } SD_CMD_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SD_ARG; /*!< (@ 0x00000008) SD Command Argument Register */ + + struct + { + __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument) */ + } SD_ARG_b; + }; + + union + { + __IOM uint32_t SD_ARG1; /*!< (@ 0x0000000C) SD Command Argument Register 1 */ + + struct + { + __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument) */ + uint32_t : 16; + } SD_ARG1_b; + }; + + union + { + __IOM uint32_t SD_STOP; /*!< (@ 0x00000010) Data Stop Register */ + + struct + { + __IOM uint32_t STP : 1; /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer, + * CMD12 is issued to halt the transfer through the SD host + * interface.However, if a command sequence is halted because + * of a communications error or timeout, CMD12 is not issued. + * Although continued buffer access is possible even after + * STP has been set to 1, the buffer access error bit (ERR5 + * or ERR4) in SD_INFO2 will be set accordingly.- When STP + * has been set to 1 during transfer for single block write, + * the access end flag is set when SD_BUF becomes e */ + uint32_t : 7; + __IOM uint32_t SEC : 1; /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When + * SD_CMD is set as follows to start the command sequence + * while SEC is set to 1, CMD12 is automatically issued to + * stop multi-block transfer with the number of blocks which + * is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8] + * = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is + * automatically issued, multiple block transfer)When the + * command sequence is halted because of a communications + * error or timeout, CMD12 is not automatically */ + uint32_t : 23; + } SD_STOP_b; + }; + + union + { + __IOM uint32_t SD_SECCNT; /*!< (@ 0x00000014) Block Count Register */ + + struct + { + __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value + * of this bit when the CBSY bit in SD_INFO2 is set to 1. */ + } SD_SECCNT_b; + }; + + union + { + __IM uint32_t SD_RSP10; /*!< (@ 0x00000018) SD Card Response Register 10 */ + + struct + { + __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP10_b; + }; + + union + { + __IM uint32_t SD_RSP1; /*!< (@ 0x0000001C) SD Card Response Register 1 */ + + struct + { + __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP1_b; + }; + + union + { + __IM uint32_t SD_RSP32; /*!< (@ 0x00000020) SD Card Response Register 32 */ + + struct + { + __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP32_b; + }; + + union + { + __IM uint32_t SD_RSP3; /*!< (@ 0x00000024) SD Card Response Register 3 */ + + struct + { + __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP3_b; + }; + + union + { + __IM uint32_t SD_RSP54; /*!< (@ 0x00000028) SD Card Response Register 54 */ + + struct + { + __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC */ + } SD_RSP54_b; + }; + + union + { + __IM uint32_t SD_RSP5; /*!< (@ 0x0000002C) SD Card Response Register 5 */ + + struct + { + __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC */ + uint32_t : 16; + } SD_RSP5_b; + }; + + union + { + __IM uint32_t SD_RSP76; /*!< (@ 0x00000030) SD Card Response Register 76 */ + + struct + { + __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC */ + uint32_t : 8; + } SD_RSP76_b; + }; + + union + { + __IM uint32_t SD_RSP7; /*!< (@ 0x00000034) SD Card Response Register 7 */ + + struct + { + __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC */ + uint32_t : 24; + } SD_RSP7_b; + }; + + union + { + __IOM uint32_t SD_INFO1; /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t RSPEND : 1; /*!< [0..0] Response End Detection */ + uint32_t : 1; + __IOM uint32_t ACEND : 1; /*!< [2..2] Access End */ + __IOM uint32_t SDCDRM : 1; /*!< [3..3] SDnCD Card Removal */ + __IOM uint32_t SDCDIN : 1; /*!< [4..4] SDnCD Card Insertion */ + __IM uint32_t SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state */ + uint32_t : 1; + __IM uint32_t SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state */ + __IOM uint32_t SDD3RM : 1; /*!< [8..8] SDnDAT3 Card Removal */ + __IOM uint32_t SDD3IN : 1; /*!< [9..9] SDnDAT3 Card Insertion */ + __IM uint32_t SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State */ + uint32_t : 21; + } SD_INFO1_b; + }; + + union + { + __IOM uint32_t SD_INFO2; /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2 */ + + struct + { + __IOM uint32_t CMDE : 1; /*!< [0..0] Command Error */ + __IOM uint32_t CRCE : 1; /*!< [1..1] CRC Error */ + __IOM uint32_t ENDE : 1; /*!< [2..2] END Error */ + __IOM uint32_t DTO : 1; /*!< [3..3] Data Timeout */ + __IOM uint32_t ILW : 1; /*!< [4..4] SD_BUF Illegal Write Access */ + __IOM uint32_t ILR : 1; /*!< [5..5] SD_BUF Illegal Read Access */ + __IOM uint32_t RSPTO : 1; /*!< [6..6] Response Timeout */ + __IM uint32_t SDD0MON : 1; /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified + * by SD_PORTSEL. */ + __IOM uint32_t BRE : 1; /*!< [8..8] SD_BUF Read Enable */ + __IOM uint32_t BWE : 1; /*!< [9..9] SD_BUF Write Enable */ + uint32_t : 3; + __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD, + * the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN + * bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 + * cycles of SDCLK have elapsed after setting of the CBSY + * bit to 0 due to completion of the command sequence. */ + __IM uint32_t CBSY : 1; /*!< [14..14] Command Type Register Busy */ + __IOM uint32_t ILA : 1; /*!< [15..15] Illegal Access Error */ + uint32_t : 16; + } SD_INFO2_b; + }; + + union + { + __IOM uint32_t SD_INFO1_MASK; /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t ACENDM : 1; /*!< [2..2] Access End Interrupt Request Mask */ + __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask */ + __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask */ + uint32_t : 3; + __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask */ + __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask */ + uint32_t : 22; + } SD_INFO1_MASK_b; + }; + + union + { + __IOM uint32_t SD_INFO2_MASK; /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register */ + + struct + { + __IOM uint32_t CMDEM : 1; /*!< [0..0] Command Error Interrupt Request Mask */ + __IOM uint32_t CRCEM : 1; /*!< [1..1] CRC Error Interrupt Request Mask */ + __IOM uint32_t ENDEM : 1; /*!< [2..2] End Bit Error Interrupt Request Mask */ + __IOM uint32_t DTOM : 1; /*!< [3..3] Data Timeout Interrupt Request Mask */ + __IOM uint32_t ILWM : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask */ + __IOM uint32_t ILRM : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask */ + __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask */ + uint32_t : 1; + __IOM uint32_t BREM : 1; /*!< [8..8] BRE Interrupt Request Mask */ + __IOM uint32_t BWEM : 1; /*!< [9..9] BWE Interrupt Request Mask */ + uint32_t : 5; + __IOM uint32_t ILAM : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask */ + uint32_t : 16; + } SD_INFO2_MASK_b; + }; + + union + { + __IOM uint32_t SD_CLK_CTRL; /*!< (@ 0x00000048) SD Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 8; /*!< [7..0] SDHI Clock Frequency Select */ + __IOM uint32_t CLKEN : 1; /*!< [8..8] SD/MMC Clock Output Control Enable */ + __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable */ + uint32_t : 22; + } SD_CLK_CTRL_b; + }; + + union + { + __IOM uint32_t SD_SIZE; /*!< (@ 0x0000004C) Transfer Data Length Register */ + + struct + { + __IOM uint32_t LEN : 10; /*!< [9..0] Transfer Data SizeThese bits specify a size between 1 + * and 512 bytes for the transfer of single blocks.In cases + * of multiple block transfer with automatic issuing of CMD12 + * (CMD18 and CMD25), the only specifiable transfer data size + * is 512 bytes. Furthermore, in cases of multiple block transfer + * without automatic issuing of CMD12, as well as 512 bytes, + * 32, 64, 128, and 256 bytes are specifiable. However, in + * the reading of 32, 64, 128, and 256 bytes for the transfer + * of multiple blocks, this is restricted to mu */ + uint32_t : 22; + } SD_SIZE_b; + }; + + union + { + __IOM uint32_t SD_OPTION; /*!< (@ 0x00000050) SD Card Access Control Option Register */ + + struct + { + __IOM uint32_t CTOP : 4; /*!< [3..0] Card Detect Time Counter */ + __IOM uint32_t TOP : 4; /*!< [7..4] Timeout Counter */ + __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating + * timeout, software reset should be executed to terminate + * command sequence. */ + uint32_t : 4; + __IOM uint32_t WIDTH8 : 1; /*!< [13..13] Bus Widthsee b15, WIDTH bit */ + uint32_t : 1; + __IOM uint32_t WIDTH : 1; /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset + * and when the SOFT_RST.SDRST flag is 0. */ + uint32_t : 16; + } SD_OPTION_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t SD_ERR_STS1; /*!< (@ 0x00000058) SD Error Status Register 1 */ + + struct + { + __IM uint32_t CMDE0 : 1; /*!< [0..0] Command Error 0NOTE: other than a response to a command + * issued within a command sequence */ + __IM uint32_t CMDE1 : 1; /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by + * setting a command index in SD_CMD, this is Indicated in + * CMDE0. */ + __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to + * a command issued within a command sequence */ + __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is + * issued by setting a command index in SD_CMD, this is indicated + * in RSPLENE0. */ + __IM uint32_t RDLENE : 1; /*!< [4..4] Read Data Length Error */ + __IM uint32_t CRCLENE : 1; /*!< [5..5] CRC Status Token Length Error */ + uint32_t : 2; + __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a + * command issued within a command sequence */ + __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued + * by setting a command index in SD_CMD, this is indicated + * in RSPCRCE0. */ + __IM uint32_t RDCRCE : 1; /*!< [10..10] Read Data CRC Error */ + __IM uint32_t CRCTKE : 1; /*!< [11..11] CRC Status Token Error */ + __IM uint32_t CRCTK : 3; /*!< [14..12] CRC Status TokenStore the CRC status token value (normal + * value is 010b) */ + uint32_t : 17; + } SD_ERR_STS1_b; + }; + + union + { + __IM uint32_t SD_ERR_STS2; /*!< (@ 0x0000005C) SD Error Status Register 2 */ + + struct + { + __IM uint32_t RSPTO0 : 1; /*!< [0..0] Response Timeout 0 */ + __IM uint32_t RSPTO1 : 1; /*!< [1..1] Response Timeout 1 */ + __IM uint32_t BSYTO0 : 1; /*!< [2..2] Busy Timeout 0 */ + __IM uint32_t BSYTO1 : 1; /*!< [3..3] Busy Timeout 1 */ + __IM uint32_t RDTO : 1; /*!< [4..4] Read Data Timeout */ + __IM uint32_t CRCTO : 1; /*!< [5..5] CRC Status Token Timeout */ + __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout */ + uint32_t : 25; + } SD_ERR_STS2_b; + }; + + union + { + __IOM uint32_t SD_BUF0; /*!< (@ 0x00000060) SD Buffer Register */ + + struct + { + __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write + * data is written to this register. When reading from the + * SD card, the read data is read from this register. This + * register is internally connected to two 512-byte buffers.If + * both buffers are not empty when executing multiple block + * read, SD/MMC clock is stopped to suspend receiving data. + * When one of buffers is empty, SD/MMC clock is supplied + * to resume receiving data. */ + } SD_BUF0_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t SDIO_MODE; /*!< (@ 0x00000068) SDIO Mode Control Register */ + + struct + { + __IOM uint32_t INTEN : 1; /*!< [0..0] SDIO Mode */ + uint32_t : 1; + __IOM uint32_t RWREQ : 1; /*!< [2..2] Read Wait Request */ + uint32_t : 5; + __IOM uint32_t IOABT : 1; /*!< [8..8] SDIO AbortNOTE: See manual */ + __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual */ + uint32_t : 22; + } SDIO_MODE_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1; /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1 */ + + struct + { + __IOM uint32_t IOIRQ : 1; /*!< [0..0] SDIO Interrupt Status */ + uint32_t : 13; + __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual */ + __IOM uint32_t EXWT : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual */ + uint32_t : 16; + } SDIO_INFO1_b; + }; + + union + { + __IOM uint32_t SDIO_INFO1_MASK; /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register */ + + struct + { + __IOM uint32_t IOIRQM : 1; /*!< [0..0] IOIRQ Interrupt Mask Control */ + uint32_t : 13; + __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control */ + __IOM uint32_t EXWTM : 1; /*!< [15..15] EXWT Interrupt Request Mask Control */ + uint32_t : 16; + } SDIO_INFO1_MASK_b; + }; + __IM uint32_t RESERVED3[79]; + + union + { + __IOM uint32_t SD_DMAEN; /*!< (@ 0x000001B0) DMA Mode Enable Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t DMAEN : 1; /*!< [1..1] SD_BUF Read/Write DMA Transfer */ + uint32_t : 30; + } SD_DMAEN_b; + }; + __IM uint32_t RESERVED4[3]; + + union + { + __IOM uint32_t SOFT_RST; /*!< (@ 0x000001C0) Software Reset Register */ + + struct + { + __IOM uint32_t SDRST : 1; /*!< [0..0] Software Reset of SD I/F Unit */ + uint32_t : 31; + } SOFT_RST_b; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t SDIF_MODE; /*!< (@ 0x000001CC) SD Interface Mode Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands) */ + uint32_t : 23; + } SDIF_MODE_b; + }; + __IM uint32_t RESERVED6[4]; + + union + { + __IOM uint32_t EXT_SWAP; /*!< (@ 0x000001E0) Swap Control Register */ + + struct + { + uint32_t : 6; + __IOM uint32_t BWSWP : 1; /*!< [6..6] SD_BUF0 Swap Write */ + __IOM uint32_t BRSWP : 1; /*!< [7..7] SD_BUF0 Swap Read */ + uint32_t : 24; + } EXT_SWAP_b; + }; +} R_SDHI0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0) + */ + +typedef struct /*!< (@ 0x4009D000) R_SSI0 Structure */ +{ + union + { + __IOM uint32_t SSICR; /*!< (@ 0x00000000) Control Register */ + + struct + { + __IOM uint32_t REN : 1; /*!< [0..0] Receive Enable */ + __IOM uint32_t TEN : 1; /*!< [1..1] Transmit Enable */ + uint32_t : 1; + __IOM uint32_t MUEN : 1; /*!< [3..3] Mute EnableNOTE: When this module is muted, the value + * of outputting serial data is rewritten to 0 but data transmission + * is not stopped. Write dummy data to the SSIFTDR not to + * generate a transmit underflow because the number of data + * in the transmit FIFO is decreasing. */ + __IOM uint32_t CKDV : 4; /*!< [7..4] Serial Oversampling Clock Division Ratio */ + __IOM uint32_t DEL : 1; /*!< [8..8] Serial Data Delay */ + __IOM uint32_t PDTA : 1; /*!< [9..9] Parallel Data Alignment */ + __IOM uint32_t SDTA : 1; /*!< [10..10] Serial Data Alignment */ + __IOM uint32_t SPDP : 1; /*!< [11..11] Serial Padding Polarity */ + __IOM uint32_t LRCKP : 1; /*!< [12..12] Serial WS Polarity */ + __IOM uint32_t BCKP : 1; /*!< [13..13] Serial Bit Clock Polarity */ + __IOM uint32_t MST : 1; /*!< [14..14] Serial WS Direction NOTE: Only the following settings + * are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings + * are prohibited. */ + uint32_t : 1; + __IOM uint32_t SWL : 3; /*!< [18..16] System Word LengthSet the system word length to the + * bit clock frequency/2 fs. */ + __IOM uint32_t DWL : 3; /*!< [21..19] Data Word Length */ + __IOM uint32_t FRM : 2; /*!< [23..22] Channels */ + uint32_t : 1; + __IOM uint32_t IIEN : 1; /*!< [25..25] Idle Mode Interrupt Enable */ + __IOM uint32_t ROIEN : 1; /*!< [26..26] Receive Overflow Interrupt Enable */ + __IOM uint32_t RUIEN : 1; /*!< [27..27] Receive Underflow Interrupt Enable */ + __IOM uint32_t TOIEN : 1; /*!< [28..28] Transmit Overflow Interrupt Enable */ + __IOM uint32_t TUIEN : 1; /*!< [29..29] Transmit Underflow Interrupt Enable */ + __IOM uint32_t CKS : 1; /*!< [30..30] Oversampling Clock Select */ + uint32_t : 1; + } SSICR_b; + }; + + union + { + __IOM uint32_t SSISR; /*!< (@ 0x00000004) Status Register */ + + struct + { + __IM uint32_t IDST : 1; /*!< [0..0] Idle Mode Status Flag */ + __IM uint32_t RSWNO : 1; /*!< [1..1] Receive Serial Word Number */ + __IM uint32_t RCHNO : 2; /*!< [3..2] Receive Channel Number.These bits are read as 00b. */ + __IM uint32_t TSWNO : 1; /*!< [4..4] Transmit Serial Word Number */ + __IM uint32_t TCHNO : 2; /*!< [6..5] Transmit Channel Number */ + uint32_t : 18; + __IM uint32_t IIRQ : 1; /*!< [25..25] Idle Mode Interrupt Status Flag */ + __IOM uint32_t ROIRQ : 1; /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t RUIRQ : 1; /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TOIRQ : 1; /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + __IOM uint32_t TUIRQ : 1; /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE: + * Writable only to clear the flag. Confirm the value is 1 + * and then write 0. */ + uint32_t : 2; + } SSISR_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t SSIFCR; /*!< (@ 0x00000010) FIFO Control Register */ + + struct + { + __IOM uint32_t RFRST : 1; /*!< [0..0] Receive FIFO Data Register Reset */ + __IOM uint32_t TFRST : 1; /*!< [1..1] Transmit FIFO Data Register Reset */ + __IOM uint32_t RIE : 1; /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by + * clearing either the RDF flag (see the description of the + * RDF bit for details) or RIE bit. */ + __IOM uint32_t TIE : 1; /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by + * clearing either the TDE flag (see the description of the + * TDE bit for details) or TIE bit. */ + __IOM uint32_t RTRG : 2; /*!< [5..4] Receive Data Trigger Number */ + __IOM uint32_t TTRG : 2; /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis + * are the number of empty stages in SSIFTDR at which the + * TDE flag is set. */ + uint32_t : 3; + __IOM uint32_t BSW : 1; /*!< [11..11] Byte Swap Enable */ + uint32_t : 4; + __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset */ + uint32_t : 14; + __IOM uint32_t AUCKE : 1; /*!< [31..31] Oversampling Clock Enable */ + } SSIFCR_b; + }; + + union + { + __IOM uint32_t SSIFSR; /*!< (@ 0x00000014) FIFO Status Register */ + + struct + { + __IOM uint32_t RDF : 1; /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register + * is a 32-byte FIFO register, the maximum number of data + * bytes that can be read from it while the RDF flag is 1 + * is indicated in the RDC[3:0] flags. If reading data from + * the SSIFRDR register is continued after all the data is + * read, undefined values will be read. */ + uint32_t : 7; + __IM uint32_t RDC : 6; /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data + * units stored in SSIFRDR) */ + uint32_t : 2; + __IOM uint32_t TDE : 1; /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register + * is a 32-byte FIFO register, the maximum number of bytes + * that can be written to it while the TDE flag is 1 is 8 + * - TDC[3:0]. If writing data to the SSIFTDR register is + * continued after all the data is written, writing will be + * invalid and an overflow occurs. */ + uint32_t : 7; + __IM uint32_t TDC : 6; /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of + * data units stored in SSIFTDR) */ + uint32_t : 2; + } SSIFSR_b; + }; + + union + { + union + { + __OM uint32_t SSIFTDR; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + + struct + { + __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of + * eight stages of 32-bit registers for storing data to be + * serially transmitted. NOTE: that when the SSIFTDR register + * is full of data (32 bytes), the next data cannot be written + * to it. If writing is attempted, it will be ignored and + * an overflow occurs. */ + } SSIFTDR_b; + }; + __OM uint16_t SSIFTDR16; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + __OM uint8_t SSIFTDR8; /*!< (@ 0x00000018) Transmit FIFO Data Register */ + }; + + union + { + union + { + __IM uint32_t SSIFRDR; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + + struct + { + __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight + * stages of 32-bit registers for storing serially received + * data. */ + } SSIFRDR_b; + }; + __IM uint16_t SSIFRDR16; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + __IM uint8_t SSIFRDR8; /*!< (@ 0x0000001C) Receive FIFO Data Register */ + }; + + union + { + __IOM uint32_t SSIOFR; /*!< (@ 0x00000020) Audio Format Register */ + + struct + { + __IOM uint32_t OMOD : 2; /*!< [1..0] Audio Format Select */ + uint32_t : 6; + __IOM uint32_t LRCONT : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation */ + __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in + * Idle Status */ + uint32_t : 22; + } SSIOFR_b; + }; + + union + { + __IOM uint32_t SSISCR; /*!< (@ 0x00000024) Status Control Register */ + + struct + { + __IOM uint32_t RDFS : 5; /*!< [4..0] RDF Setting Condition Select */ + uint32_t : 3; + __IOM uint32_t TDES : 5; /*!< [12..8] TDE Setting Condition Select */ + uint32_t : 19; + } SSISCR_b; + }; +} R_SSI0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x400F3228) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Module (R_USB_FS0) + */ + +typedef struct /*!< (@ 0x40090000) R_USB_FS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 2; + __IOM uint16_t DMRPU : 1; /*!< [3..3] D- Line Resistor Control */ + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + uint16_t : 1; + __IOM uint16_t CNEN : 1; /*!< [8..8] CNEN Single End Receiver Enable */ + uint16_t : 1; + __IOM uint16_t SCKE : 1; /*!< [10..10] USB Clock Enable */ + uint16_t : 5; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register 0 */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] External ID0 Input Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] USB Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Enable */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Output */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Wakeup Detection Enable */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USB_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USB_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is + * used when switching from device B to device A while in + * OTG mode. If the HNPBTOA bit is 1, the internal function + * control keeps the suspended state until the HNP processing + * ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is + * set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] CFIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read. */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA/DTC Transfer Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data LengthIndicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read. */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 4; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE */ + __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Output Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Edge Interrupt Output Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] ATTCH Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE */ + __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE */ + __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame NumberLatest frame number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] Receive Data Error */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address In device controller mode, these flags indicate + * the USB address assigned by the host when the USBHS processed + * the SET_ADDRESS request successfully. */ + uint16_t : 1; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType + * value. */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] RequestThese bits store the USB request bRequest value. */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value. */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value. */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value. */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount + * of data (maximum packet size) in payloads for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQ : 1; /*!< [14..14] Setup Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint NumberThese bits specify the endpoint number + * for the selected pipe.Setting 0000b means unused pipe. */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + uint16_t : 1; + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 9; /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to + * 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes + * (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and + * [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to + * 64 bytes (040h) (Bits [8:7] are not provided.) */ + uint16_t : 3; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalSpecifies the interval + * error detection timing for the selected pipe in terms of + * frames, which is expressed as nth power of 2. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) Pipe [0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Confirmation */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Sequence Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Sequence Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED15[3]; + + union + { + __IOM uint16_t USBBCCTRL0; /*!< (@ 0x000000B0) BC Control Register 0 */ + + struct + { + __IOM uint16_t RPDME0 : 1; /*!< [0..0] D- Pin Pull-Down Control */ + __IOM uint16_t IDPSRCE0 : 1; /*!< [1..1] D+ Pin IDPSRC Output Control */ + __IOM uint16_t IDMSINKE0 : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDPSRCE0 : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control */ + __IOM uint16_t IDPSINKE0 : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */ + __IOM uint16_t VDMSRCE0 : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control */ + uint16_t : 1; + __IOM uint16_t BATCHGE0 : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control */ + __IM uint16_t CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status */ + __IM uint16_t PDDETSTS0 : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status */ + uint16_t : 6; + } USBBCCTRL0_b; + }; + __IM uint16_t RESERVED16; + __IM uint32_t RESERVED17[4]; + + union + { + __IOM uint16_t UCKSEL; /*!< (@ 0x000000C4) USB Clock Selection Register */ + + struct + { + __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection */ + uint16_t : 15; + } UCKSEL_b; + }; + __IM uint16_t RESERVED18; + __IM uint32_t RESERVED19; + + union + { + __IOM uint16_t USBMC; /*!< (@ 0x000000CC) USB Module Control Register */ + + struct + { + __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control */ + uint16_t : 6; + __IOM uint16_t VDCEN : 1; /*!< [7..7] USB Regulator On/Off Control */ + uint16_t : 8; + } USBMC_b; + }; + __IM uint16_t RESERVED20; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED21[3]; + + union + { + __IOM uint32_t PHYSLEW; /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register */ + + struct + { + __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01 */ + __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00 */ + __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01 */ + uint32_t : 28; + } PHYSLEW_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED23[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED25[5]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; + __IM uint32_t RESERVED26[165]; + + union + { + __IOM uint32_t DPUSR0R_FS; /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin + * Monitor Register */ + + struct + { + __IOM uint32_t SRPC0 : 1; /*!< [0..0] USB Single End Receiver Control */ + __IOM uint32_t RPUE0 : 1; /*!< [1..1] DP Pull-Up Resistor Control */ + uint32_t : 1; + __IOM uint32_t DRPD0 : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control */ + __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix */ + uint32_t : 11; + __IM uint32_t DP0 : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */ + __IM uint32_t DM0 : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB. */ + uint32_t : 2; + __IM uint32_t DOVCA0 : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal + * of the USB. */ + __IM uint32_t DOVCB0 : 1; /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal + * of the USB. */ + uint32_t : 1; + __IM uint32_t DVBSTS0 : 1; /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the + * USB. */ + uint32_t : 8; + } DPUSR0R_FS_b; + }; + + union + { + __IOM uint32_t DPUSR1R_FS; /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt + * Register */ + + struct + { + __IOM uint32_t DPINTE0 : 1; /*!< [0..0] USB DP Interrupt Enable/Clear */ + __IOM uint32_t DMINTE0 : 1; /*!< [1..1] USB DM Interrupt Enable/Clear */ + uint32_t : 2; + __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear */ + __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear */ + uint32_t : 1; + __IOM uint32_t DVBSE0 : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear */ + uint32_t : 8; + __IM uint32_t DPINT0 : 1; /*!< [16..16] USB DP Interrupt Source Recovery */ + __IM uint32_t DMINT0 : 1; /*!< [17..17] USB DM Interrupt Source Recovery */ + uint32_t : 2; + __IM uint32_t DOVRCRA0 : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery */ + __IM uint32_t DOVRCRB0 : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery */ + uint32_t : 1; + __IM uint32_t DVBINT0 : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery */ + uint32_t : 8; + } DPUSR1R_FS_b; + }; +} R_USB_FS0_Type; /*!< Size = 1032 (0x408) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/* =========================================================================================================================== */ +/* ================ R_CEC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Consumer Electronics Control (R_CEC) + */ + +typedef struct /*!< (@ 0x400AC000) R_CEC Structure */ +{ + union + { + __IOM uint16_t CADR; /*!< (@ 0x00000000) CEC Local Address Setting Register */ + + struct + { + __IOM uint16_t ADR00 : 1; /*!< [0..0] Local Address at Address 0 (TV) */ + __IOM uint16_t ADR01 : 1; /*!< [1..1] Local Address Setting at Address 1 (recording device + * 1) */ + __IOM uint16_t ADR02 : 1; /*!< [2..2] Local Address Setting at Address 2 (recording device + * 2) */ + __IOM uint16_t ADR03 : 1; /*!< [3..3] Local Address Setting at Address 3 (tuner 1) */ + __IOM uint16_t ADR04 : 1; /*!< [4..4] Local Address Setting at Address 4 (playback device 1) */ + __IOM uint16_t ADR05 : 1; /*!< [5..5] Local Address Setting at Address 5 (audio system) */ + __IOM uint16_t ADR06 : 1; /*!< [6..6] Local Address Setting at Address 6 (tuner 2) */ + __IOM uint16_t ADR07 : 1; /*!< [7..7] Local Address Setting at Address 7 (tuner 3) */ + __IOM uint16_t ADR08 : 1; /*!< [8..8] Local Address Setting at Address 8 (playback device 2) */ + __IOM uint16_t ADR09 : 1; /*!< [9..9] Local Address Setting at Address 9 (recording device + * 3) */ + __IOM uint16_t ADR10 : 1; /*!< [10..10] Local Address Setting at Address 10 (tuner 4) */ + __IOM uint16_t ADR11 : 1; /*!< [11..11] Local Address Setting at Address 11 (playback device + * 3) */ + __IOM uint16_t ADR12 : 1; /*!< [12..12] Local Address Setting at Address 12 (reserved) */ + __IOM uint16_t ADR13 : 1; /*!< [13..13] Local Address Setting at Address 13 (reserved) */ + __IOM uint16_t ADR14 : 1; /*!< [14..14] Local Address Setting at Address 14 (specific use) */ + uint16_t : 1; + } CADR_b; + }; + + union + { + __IOM uint8_t CECCTL1; /*!< (@ 0x00000002) CEC Control Register 1 */ + + struct + { + __IOM uint8_t SFT : 2; /*!< [1..0] Signal-Free Time Data Bit Width Select */ + __IOM uint8_t CESEL : 2; /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing + * Select */ + __IOM uint8_t STERRD : 1; /*!< [4..4] Start Bit Error Detection Select */ + __IOM uint8_t BLERRD : 1; /*!< [5..5] Bus Lock Detection Select */ + __IOM uint8_t CINTMK : 1; /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select */ + __IOM uint8_t CDFC : 1; /*!< [7..7] Digital Filter Select */ + } CECCTL1_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t STATB; /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register */ + + struct + { + __IOM uint16_t STATB : 9; /*!< [8..0] CEC Transmission Start Bit Width Setting */ + uint16_t : 7; + } STATB_b; + }; + + union + { + __IOM uint16_t STATL; /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATL : 9; /*!< [8..0] CEC Transmission Start Bit Low Width Setting */ + uint16_t : 7; + } STATL_b; + }; + + union + { + __IOM uint16_t LGC0L; /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0L : 9; /*!< [8..0] CEC Transmission Logical 0 Low Width Setting */ + uint16_t : 7; + } LGC0L_b; + }; + + union + { + __IOM uint16_t LGC1L; /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1L : 9; /*!< [8..0] CEC Transmission Logical 1 Low Width Setting */ + uint16_t : 7; + } LGC1L_b; + }; + + union + { + __IOM uint16_t DATB; /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register */ + + struct + { + __IOM uint16_t DATB : 9; /*!< [8..0] CEC Transmission Data Bit Width Setting */ + uint16_t : 7; + } DATB_b; + }; + + union + { + __IOM uint16_t NOMT; /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register */ + + struct + { + __IOM uint16_t NOMT : 9; /*!< [8..0] CEC Reception Data Sampling Time Setting, */ + uint16_t : 7; + } NOMT_b; + }; + + union + { + __IOM uint16_t STATLL; /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting */ + uint16_t : 7; + } STATLL_b; + }; + + union + { + __IOM uint16_t STATLH; /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ + uint16_t : 7; + } STATLH_b; + }; + + union + { + __IOM uint16_t STATBL; /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting */ + uint16_t : 7; + } STATBL_b; + }; + + union + { + __IOM uint16_t STATBH; /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting */ + uint16_t : 7; + } STATBH_b; + }; + + union + { + __IOM uint16_t LGC0LL; /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ + uint16_t : 7; + } LGC0LL_b; + }; + + union + { + __IOM uint16_t LGC0LH; /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting */ + uint16_t : 7; + } LGC0LH_b; + }; + + union + { + __IOM uint16_t LGC1LL; /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting */ + uint16_t : 7; + } LGC1LL_b; + }; + + union + { + __IOM uint16_t LGC1LH; /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting + * Register */ + + struct + { + __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting */ + uint16_t : 7; + } LGC1LH_b; + }; + + union + { + __IOM uint16_t DATBL; /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t DATBL : 9; /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting */ + uint16_t : 7; + } DATBL_b; + }; + + union + { + __IOM uint16_t DATBH; /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting + * Register */ + + struct + { + __IOM uint16_t DATBH : 9; /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting */ + uint16_t : 7; + } DATBH_b; + }; + + union + { + __IOM uint16_t NOMP; /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register */ + + struct + { + __IOM uint16_t NOMP : 9; /*!< [8..0] CEC Data Bit Reference Width Setting */ + uint16_t : 7; + } NOMP_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t CECEXMD; /*!< (@ 0x00000028) CEC Extension Mode Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t LERPLEN : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error */ + __IOM uint8_t RERCVEN : 1; /*!< [5..5] Start Detection Reception Restart Enable */ + uint8_t : 1; + __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change */ + } CECEXMD_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t CECEXMON; /*!< (@ 0x0000002A) CEC Extension Monitor Register */ + + struct + { + __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor */ + __IM uint8_t ACKF : 1; /*!< [1..1] ACK Flag */ + uint8_t : 6; + } CECEXMON_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[10]; + __IOM uint8_t CTXD; /*!< (@ 0x00000040) CEC Transmission Buffer Register */ + __IOM uint8_t CRXD; /*!< (@ 0x00000041) CEC Reception Buffer Register */ + + union + { + __IOM uint8_t CECES; /*!< (@ 0x00000042) CEC Communication Error Status Register */ + + struct + { + __IM uint8_t OERR : 1; /*!< [0..0] Overrun Error Detection Flag */ + __IM uint8_t UERR : 1; /*!< [1..1] Underrun Error Detection Flag */ + __IM uint8_t ACKERR : 1; /*!< [2..2] ACK Error Detection Flag */ + __IM uint8_t TERR : 1; /*!< [3..3] Timing Error Detection Flag */ + __IM uint8_t TXERR : 1; /*!< [4..4] Transmission Error Detection Flag */ + __IM uint8_t AERR : 1; /*!< [5..5] Arbitration Loss Detection Flag */ + __IM uint8_t BLERR : 1; /*!< [6..6] Bus Lock Error Detection Flag */ + uint8_t : 1; + } CECES_b; + }; + + union + { + __IOM uint8_t CECS; /*!< (@ 0x00000043) CEC Communication Status Register */ + + struct + { + __IM uint8_t ADRF : 1; /*!< [0..0] Address Match Detection Flag */ + __IM uint8_t BUSST : 1; /*!< [1..1] Bus Busy Detection Flag */ + __IM uint8_t TXST : 1; /*!< [2..2] Transmission Status Flag */ + __IM uint8_t EOMF : 1; /*!< [3..3] EOM Flag */ + __IM uint8_t ITCEF : 1; /*!< [4..4] INTCE Generation Source Flag */ + uint8_t : 2; + __IM uint8_t SFTST : 1; /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag */ + } CECS_b; + }; + + union + { + __IOM uint8_t CECFC; /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register */ + + struct + { + __OM uint8_t OCTRG : 1; /*!< [0..0] Overrun Error Detection Flag Clear Trigger */ + __OM uint8_t UCTRG : 1; /*!< [1..1] Underrun Error Detection Flag Clear Trigger */ + __OM uint8_t ACKCTRG : 1; /*!< [2..2] ACK Error Detection Flag Clear Trigger */ + __OM uint8_t TCTRG : 1; /*!< [3..3] Timing Error Detection Flag Clear Trigger */ + __OM uint8_t TXCTRG : 1; /*!< [4..4] Transmission Error Detection Flag Clear Trigger */ + __OM uint8_t ACTRG : 1; /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger */ + __OM uint8_t BLCTRG : 1; /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger */ + uint8_t : 1; + } CECFC_b; + }; + + union + { + __IOM uint8_t CECCTL0; /*!< (@ 0x00000045) CEC Control Register 0 */ + + struct + { + __IOM uint8_t EOM : 1; /*!< [0..0] EOM Setting */ + __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control */ + __OM uint8_t TXTRG : 1; /*!< [2..2] Transmission Start Trigger */ + __IOM uint8_t CCL : 3; /*!< [5..3] CEC Clock (CECCLK) Select */ + __IOM uint8_t ACKTEN : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable */ + __IOM uint8_t CECE : 1; /*!< [7..7] CEC Operation Enable Flag */ + } CECCTL0_b; + }; +} R_CEC_Type; /*!< Size = 70 (0x46) */ + +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Octa Serial Peripheral Interface (R_OSPI) + */ + +typedef struct /*!< (@ 0x400A6000) R_OSPI Structure */ +{ + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000000) Device Command Register */ + + struct + { + __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data */ + __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data */ + uint32_t : 16; + } DCR_b; + }; + + union + { + __IOM uint32_t DAR; /*!< (@ 0x00000004) Device Address Register */ + + struct + { + __IOM uint32_t DVAD0 : 8; /*!< [7..0] Device Address data 0 */ + __IOM uint32_t DVAD1 : 8; /*!< [15..8] Device Address data 1 */ + __IOM uint32_t DVAD2 : 8; /*!< [23..16] Device Address data 2 */ + __IOM uint32_t DVAD3 : 8; /*!< [31..24] Device Address data 3 */ + } DAR_b; + }; + + union + { + __IOM uint32_t DCSR; /*!< (@ 0x00000008) Device Command Setting Register */ + + struct + { + __IOM uint32_t DALEN : 8; /*!< [7..0] Transfer data length setting */ + __IOM uint32_t DMLEN : 8; /*!< [15..8] Dummy cycle setting */ + uint32_t : 3; + __IOM uint32_t ACDV : 1; /*!< [19..19] Access Device setting */ + __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting */ + __IOM uint32_t DAOR : 1; /*!< [23..23] Data order setting */ + __IOM uint32_t ADLEN : 3; /*!< [26..24] Transfer address length setting */ + __IOM uint32_t DOPI : 1; /*!< [27..27] DOPI single byte setting */ + __IOM uint32_t ACDA : 1; /*!< [28..28] Data Access Control */ + __IOM uint32_t PREN : 1; /*!< [29..29] Preamble bit enable for OctaRAM */ + uint32_t : 2; + } DCSR_b; + }; + + union + { + __IOM uint32_t DSR[2]; /*!< (@ 0x0000000C) Device Size Register 0 */ + + struct + { + __IOM uint32_t DVSZ : 30; /*!< [29..0] Device size setting */ + __IOM uint32_t DVTYP : 2; /*!< [31..30] Device type setting */ + } DSR_b[2]; + }; + + union + { + __IOM uint32_t MDTR; /*!< (@ 0x00000014) Memory Delay Trim Register */ + + struct + { + __IOM uint32_t DV0DEL : 8; /*!< [7..0] Device 0 delay setting */ + __IOM uint32_t DQSERAM : 4; /*!< [11..8] OM_DQS enable counter */ + __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter */ + __IOM uint32_t DV1DEL : 8; /*!< [23..16] Device 1 delay setting */ + __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter */ + uint32_t : 4; + } MDTR_b; + }; + + union + { + __IOM uint32_t ACTR; /*!< (@ 0x00000018) Auto-Calibration Timer Register */ + + struct + { + __IOM uint32_t CTP : 32; /*!< [31..0] Automatic calibration cycle time setting */ + } ACTR_b; + }; + + union + { + __IOM uint32_t ACAR[2]; /*!< (@ 0x0000001C) Auto-Calibration Address Register */ + + struct + { + __IOM uint32_t CAD : 32; /*!< [31..0] Automatic calibration address */ + } ACAR_b[2]; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t DRCSTR; /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting + * Register */ + + struct + { + __IOM uint32_t CTRW0 : 7; /*!< [6..0] Device 0 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR0 : 1; /*!< [7..7] Device 0 single continuous read mode setting */ + __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVRDHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVRDLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTRW1 : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTR1 : 1; /*!< [23..23] Device 1 single continuous read mode setting */ + __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval */ + __IOM uint32_t DVRDHI1 : 3; /*!< [29..27] Device 1 select signal High timing setting */ + __IOM uint32_t DVRDLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DRCSTR_b; + }; + + union + { + __IOM uint32_t DWCSTR; /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting + * Register */ + + struct + { + __IOM uint32_t CTWW0 : 7; /*!< [6..0] Device 0 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW0 : 1; /*!< [7..7] Device 0 single continuous write mode setting */ + __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting */ + __IOM uint32_t DVWHI0 : 3; /*!< [13..11] Device 0 select signal pull-up timing setting */ + __IOM uint32_t DVWLO0 : 2; /*!< [15..14] Device 0 select signal pull-down timing setting */ + __IOM uint32_t CTWW1 : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting + * in PCLKH units */ + __IOM uint32_t CTW1 : 1; /*!< [23..23] Device 1 single continuous write mode setting */ + __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting */ + __IOM uint32_t DVWHI1 : 3; /*!< [29..27] Device 1 select signal pull-up timing setting */ + __IOM uint32_t DVWLO1 : 2; /*!< [31..30] Device 1 select signal pull-down timing setting */ + } DWCSTR_b; + }; + + union + { + __IOM uint32_t DCSTR; /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting */ + __IOM uint32_t DVSELHI : 3; /*!< [13..11] Device select signal pull-up timing setting */ + __IOM uint32_t DVSELLO : 2; /*!< [15..14] Device select signal pull-down timing setting */ + uint32_t : 16; + } DCSTR_b; + }; + + union + { + __IOM uint32_t CDSR; /*!< (@ 0x00000040) Controller and Device Setting Register */ + + struct + { + __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting */ + __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting */ + __IOM uint32_t DV0PC : 1; /*!< [4..4] Device0_memory precycle setting */ + __IOM uint32_t DV1PC : 1; /*!< [5..5] Device1_memory precycle setting */ + uint32_t : 4; + __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device + * 0 */ + __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device + * 1 */ + __IOM uint32_t ACMODE : 2; /*!< [13..12] Automatic calibration mode */ + uint32_t : 17; + __IOM uint32_t DLFT : 1; /*!< [31..31] Deadlock Free Timer Enable */ + } CDSR_b; + }; + + union + { + __IOM uint32_t MDLR; /*!< (@ 0x00000044) Memory Map Dummy Length Register */ + + struct + { + __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting */ + __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting */ + __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting */ + __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting */ + } MDLR_b; + }; + + union + { + __IOM uint32_t MRWCR[2]; /*!< (@ 0x00000048) Memory Map Read/Write Command Register */ + + struct + { + __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting */ + __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting */ + __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting */ + __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting */ + } MRWCR_b[2]; + }; + + union + { + __IOM uint32_t MRWCSR; /*!< (@ 0x00000050) Memory Map Read/Write Setting Register */ + + struct + { + __IOM uint32_t MRAL0 : 3; /*!< [2..0] Device 0 read address length setting */ + __IOM uint32_t MRCL0 : 3; /*!< [5..3] Device 0 read command length setting */ + __IOM uint32_t MRO0 : 1; /*!< [6..6] Device 0 read order setting */ + __IOM uint32_t PREN0 : 1; /*!< [7..7] Preamble bit enable for mem0 memory-map read */ + __IOM uint32_t MWAL0 : 3; /*!< [10..8] Device 0 write address length setting */ + __IOM uint32_t MWCL0 : 3; /*!< [13..11] Device 0 write command length setting */ + __IOM uint32_t MWO0 : 1; /*!< [14..14] Device 0 write order setting */ + uint32_t : 1; + __IOM uint32_t MRAL1 : 3; /*!< [18..16] Device 1 read address length setting */ + __IOM uint32_t MRCL1 : 3; /*!< [21..19] Device 1 read command length setting */ + __IOM uint32_t MRO1 : 1; /*!< [22..22] Device 1 read order setting */ + __IOM uint32_t PREN1 : 1; /*!< [23..23] Preamble bit enable for mem1 memory-map read */ + __IOM uint32_t MWAL1 : 3; /*!< [26..24] Device 1 write address length setting */ + __IOM uint32_t MWCL1 : 3; /*!< [29..27] Device 1 write command length setting */ + __IOM uint32_t MWO1 : 1; /*!< [30..30] Device 1 write order setting */ + uint32_t : 1; + } MRWCSR_b; + }; + + union + { + __IM uint32_t ESR; /*!< (@ 0x00000054) Error Status Register */ + + struct + { + __IM uint32_t MRESR : 8; /*!< [7..0] Memory map read error status */ + __IM uint32_t MWESR : 8; /*!< [15..8] Memory map write error status */ + uint32_t : 16; + } ESR_b; + }; + + union + { + __OM uint32_t CWNDR; /*!< (@ 0x00000058) Configure Write without Data Register */ + + struct + { + __OM uint32_t WND : 32; /*!< [31..0] The write value should be 0. */ + } CWNDR_b; + }; + + union + { + __OM uint32_t CWDR; /*!< (@ 0x0000005C) Configure Write Data Register */ + + struct + { + __OM uint32_t WD0 : 8; /*!< [7..0] Write data 0 */ + __OM uint32_t WD1 : 8; /*!< [15..8] Write data 1 */ + __OM uint32_t WD2 : 8; /*!< [23..16] Write data 2 */ + __OM uint32_t WD3 : 8; /*!< [31..24] Write data 3 */ + } CWDR_b; + }; + + union + { + __IM uint32_t CRR; /*!< (@ 0x00000060) Configure Read Register */ + + struct + { + __IM uint32_t RD0 : 8; /*!< [7..0] Read data 0 */ + __IM uint32_t RD1 : 8; /*!< [15..8] Read data 1 */ + __IM uint32_t RD2 : 8; /*!< [23..16] Read data 2 */ + __IM uint32_t RD3 : 8; /*!< [31..24] Read data 3 */ + } CRR_b; + }; + + union + { + __IOM uint32_t ACSR; /*!< (@ 0x00000064) Auto-Calibration Status Register */ + + struct + { + __IOM uint32_t ACSR0 : 3; /*!< [2..0] Auto-calibration status of device 0 */ + __IOM uint32_t ACSR1 : 3; /*!< [5..3] Auto-calibration status of device 1 */ + uint32_t : 26; + } ACSR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t DCSMXR; /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register */ + + struct + { + __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are + * Low in single continuous write of OctaRAM. */ + uint32_t : 7; + __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1 + * are Low in single continuous read of OctaRAM. */ + uint32_t : 7; + } DCSMXR_b; + }; + + union + { + __IOM uint32_t DWSCTSR; /*!< (@ 0x00000080) Device Memory Map Write single continuous translating + * size Register */ + + struct + { + __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single + * continuous write of device 0. */ + uint32_t : 5; + __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single + * continuous write of device 1. */ + uint32_t : 5; + } DWSCTSR_b; + }; +} R_OSPI_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 High-Speed Module (R_USB_HS0) + */ + +typedef struct /*!< (@ 0x40111000) R_USB_HS0 Structure */ +{ + union + { + __IOM uint16_t SYSCFG; /*!< (@ 0x00000000) System Configuration Control Register */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + __IOM uint16_t DCFM : 1; /*!< [6..6] Controller Function Select */ + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single End Receiver Enable */ + uint16_t : 7; + } SYSCFG_b; + }; + + union + { + __IOM uint16_t BUSWAIT; /*!< (@ 0x00000002) CPU Bus Wait Register */ + + struct + { + __IOM uint16_t BWAIT : 4; /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 + * access cycles) */ + uint16_t : 12; + } BUSWAIT_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + __IM uint16_t IDMON : 1; /*!< [2..2] ID0 Pin Monitor */ + uint16_t : 2; + __IM uint16_t SOFEA : 1; /*!< [5..5] SOF Active Monitor While Host Controller Function is + * Selected. */ + __IM uint16_t HTACT : 1; /*!< [6..6] Host Sequencer Status Monitor */ + uint16_t : 7; + __IM uint16_t OVCMON : 2; /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe + * OCVMON[1] bit indicates the status of the USBHS_OVRCURA + * pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB + * pin. */ + } SYSSTS0_b; + }; + + union + { + __IM uint16_t PLLSTA; /*!< (@ 0x00000006) PLL Status Register */ + + struct + { + __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag */ + uint16_t : 15; + } PLLSTA_b; + }; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] USB Bus Reset Status */ + uint16_t : 1; + __IOM uint16_t UACT : 1; /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation */ + __IOM uint16_t RESUME : 1; /*!< [5..5] Resume Signal Output for the Host Controller Operation */ + __IOM uint16_t USBRST : 1; /*!< [6..6] USB Bus Reset Output for the Host Controller Operation */ + __IOM uint16_t RWUPE : 1; /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller + * Operation */ + __IOM uint16_t WKUP : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation */ + __IOM uint16_t VBUSEN : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control */ + __IOM uint16_t EXICEN : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control */ + __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit + * when switching from device B to device A in OTGmode. If + * the HNPBTOA bit is 1, the internal function controlremains + * in the Suspend state until the HNP processing endseven + * if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set. */ + uint16_t : 4; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) CFIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) CFIFO Port Register L */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL */ + }; + + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED3; + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) D0FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or + * write transmit data to the FIFO buffer by accessing these + * bits. */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) D0FIFO Port Register L */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED4; + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) D1FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write + * transmit data to the FIFO buffer by accessing these bits. */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) D1FIFO Port Register L */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL */ + }; + + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H */ + + struct + { + __IM uint8_t RESERVED5; + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH */ + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) CFIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) D0FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified + * Pipe Data is Read */ + __OM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) D1FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length.Indicates the length of the receive + * data. */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can + * be accessed. */ + __OM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable */ + uint16_t : 3; + __IOM uint16_t SACKE : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable */ + __IOM uint16_t SIGNE : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable */ + __IOM uint16_t EOFERRE : 1; /*!< [6..6] EOF Error Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t LPMENDE : 1; /*!< [8..8] LPM Transaction End Interrupt Enable */ + __IOM uint16_t L1RSMENDE : 1; /*!< [9..9] L1 Resume End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t ATTCHE : 1; /*!< [11..11] Connection Detection Interrupt Enable */ + __IOM uint16_t DTCHE : 1; /*!< [12..12] Disconnection Detection Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t BCHGE : 1; /*!< [14..14] USB Bus Change Interrupt Enable */ + __IOM uint16_t OVRCRE : 1; /*!< [15..15] OVRCRE Interrupt Enable */ + } INTENB1_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status Monitor */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be + * set only in the initial setting (before communications).The + * setting cannot be changed once communication starts. */ + uint16_t : 1; + __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency + * can be improved by setting this bit to 1 if no low-speed + * device is connected directly or via FS-HUB to the USB port. */ + uint16_t : 7; + } SOFCFG_b; + }; + + union + { + __IOM uint16_t PHYSET; /*!< (@ 0x0000003E) PHY Setting Register */ + + struct + { + __IOM uint16_t DIRPD : 1; /*!< [0..0] Power-Down Control */ + __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control */ + uint16_t : 1; + __IOM uint16_t CDPEN : 1; /*!< [3..3] Charging Downstream Port Enable */ + __IOM uint16_t CLKSEL : 2; /*!< [5..4] Input System Clock Frequency */ + uint16_t : 2; + __IOM uint16_t REPSEL : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle */ + uint16_t : 1; + __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment */ + uint16_t : 3; + __IOM uint16_t HSEB : 1; /*!< [15..15] CL-Only Mode */ + } PHYSET_b; + }; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] Buffer Ready Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] Buffer Not Ready Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] Buffer Empty Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Refresh Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 3; + __IOM uint16_t SACK : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status */ + __IOM uint16_t SIGN : 1; /*!< [5..5] Setup Transaction Error Interrupt Status */ + __IOM uint16_t EOFERR : 1; /*!< [6..6] EOF Error Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t LPMEND : 1; /*!< [8..8] LPM Transaction End Interrupt Status */ + __IOM uint16_t L1RSMEND : 1; /*!< [9..9] L1 Resume End Interrupt Status */ + uint16_t : 1; + __IOM uint16_t ATTCH : 1; /*!< [11..11] USB Connection Detection Interrupt Status */ + __IOM uint16_t DTCH : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status */ + uint16_t : 1; + __IOM uint16_t BCHG : 1; /*!< [14..14] USB Bus Change Interrupt Status */ + __IOM uint16_t OVRCR : 1; /*!< [15..15] Overcurrent Interrupt Status */ + } INTSTS1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number.Indicate the latest frame number. */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IOM uint16_t UFRMNUM; /*!< (@ 0x0000004E) uFrame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] MicroframeIndicate the microframe number. */ + uint16_t : 12; + __IOM uint16_t DVCHG : 1; /*!< [15..15] Device State Change */ + } UFRMNUM_b; + }; + + union + { + __IOM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery */ + uint16_t : 5; + } USBADDR_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected + * : read-only Host controller selected : read-write */ + __IOM uint16_t BREQUEST : 8; /*!< [15..8] USB request bRequest value Finction controller selected + * : read-only Host controller selected : read-write */ + } USBREQ_b; + }; + + union + { + __IOM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected + * : read-only Host controller selected : read-write */ + } USBVAL_b; + }; + + union + { + __IOM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected + * : read-only Host controller selected : read-write */ + } USBINDX_b; + }; + + union + { + __IOM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected + * : read-only Host controller selected : read-write */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the DCP. */ + uint16_t : 5; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * destination function device for control transfer when the + * host controller function is selected. */ + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 1; + __IOM uint16_t PINGE : 1; /*!< [4..4] PING Token Issue Enable */ + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 2; + __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear */ + __IM uint16_t CSSTS : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear */ + __IOM uint16_t SUREQ : 1; /*!< [14..14] SETUP Token Transmission */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED10; + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number + * of the selected pipe (04h to 87h). */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data + * payload (maximum packet size) for the selected pipe.A size + * of 1h to 40h bytes can be set for PIPE6 to PIPE9. */ + uint16_t : 1; + __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the + * peripheral device when the host controller function is + * selected. */ + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Cycle Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection IntervalThese bits specify the + * transfer interval timing for the selected pipe as n-th + * power of 2 of the frame timing. */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PIDThese bits specify the response type for + * the next transaction of the relevant pipe. */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe + * is being used for the USB bus */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is set for DATA1 */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected + * value of the sequence toggle bit for the next transaction + * of the relevant pipe is cleared to DATA0 */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto + * buffer clear mode for the relevant pipe */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto + * response mode for the relevant pipe. */ + uint16_t : 1; + __IM uint16_t CSSTS : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of + * Split Transaction of the relevant pipe */ + __IOM uint16_t CSCLR : 1; /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing + * the CSSTS bit of the relevant pipe */ + __IM uint16_t INBUFM : 1; /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO + * buffer status for the relevant pipe in the transmitting + * direction. */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status + * for the relevant pipe. */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[3]; + __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers */ + __IM uint32_t RESERVED14[11]; + + union + { + __IOM uint16_t DEVADD[10]; /*!< (@ 0x000000D0) Device Address Configuration Register */ + + struct + { + uint16_t : 6; + __IOM uint16_t USBSPD : 2; /*!< [7..6] Transfer Speed of Communication Target Device */ + __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port */ + __IOM uint16_t UPPHUB : 4; /*!< [14..11] Communication Target Connecting Hub Register */ + uint16_t : 1; + } DEVADD_b[10]; + }; + __IM uint32_t RESERVED15[7]; + + union + { + __IOM uint16_t LPCTRL; /*!< (@ 0x00000100) Low Power Control Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t HWUPM : 1; /*!< [7..7] Resume Return Mode Setting */ + uint16_t : 8; + } LPCTRL_b; + }; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED16[15]; + + union + { + __IOM uint16_t BCCTRL; /*!< (@ 0x00000140) Battery Charging Control Register */ + + struct + { + __IOM uint16_t IDPSRCE : 1; /*!< [0..0] IDPSRC Control */ + __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control */ + __IOM uint16_t VDPSRCE : 1; /*!< [2..2] VDPSRC Control */ + __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control */ + __IOM uint16_t VDMSRCE : 1; /*!< [4..4] VDMSRC Control */ + __IOM uint16_t DCPMODE : 1; /*!< [5..5] DCP Mode Control */ + uint16_t : 2; + __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status */ + __IM uint16_t PDDETSTS : 1; /*!< [9..9] PDDET Status */ + uint16_t : 6; + } BCCTRL_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t PL1CTRL1; /*!< (@ 0x00000144) Function L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable */ + __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode */ + __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid + * only when the L1RESPMD[1:0] value is 2'b11. */ + __IM uint16_t DVSQ : 4; /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates + * the L1 state together with the device state bits DVSQ[2:0]. */ + __IOM uint16_t HIRDTHR : 4; /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold + * value used for L1NEGOMD.The format is the same as the HIRD + * field in HL1CTRL. */ + uint16_t : 2; + __IOM uint16_t L1EXTMD : 1; /*!< [14..14] PHY Control Mode at L1 Return */ + uint16_t : 1; + } PL1CTRL1_b; + }; + + union + { + __IOM uint16_t PL1CTRL2; /*!< (@ 0x00000146) Function L1 Control Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor */ + __IOM uint16_t RWEMON : 1; /*!< [12..12] RWE Value Monitor */ + uint16_t : 3; + } PL1CTRL2_b; + }; + + union + { + __IOM uint16_t HL1CTRL1; /*!< (@ 0x00000148) Host L1 Control Register 1 */ + + struct + { + __IOM uint16_t L1REQ : 1; /*!< [0..0] L1 Transition Request */ + __IM uint16_t L1STATUS : 2; /*!< [2..1] L1 Request Completion Status */ + uint16_t : 13; + } HL1CTRL1_b; + }; + + union + { + __IOM uint16_t HL1CTRL2; /*!< (@ 0x0000014A) Host L1 Control Register 2 */ + + struct + { + __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to + * be set in the ADDR field of LPM token. */ + uint16_t : 4; + __IOM uint16_t HIRD : 4; /*!< [11..8] LPM Token HIRD */ + __IOM uint16_t L1RWE : 1; /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the + * value to be set in the RWE field of LPM token. */ + uint16_t : 2; + __IOM uint16_t BESL : 1; /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive + * period at the time of L1 Resume. */ + } HL1CTRL2_b; + }; + __IM uint32_t RESERVED18; + + union + { + __IOM uint16_t PHYTRIM1; /*!< (@ 0x00000150) PHY Timing Register 1 */ + + struct + { + __IOM uint16_t DRISE : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function */ + __IOM uint16_t DFALL : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function */ + uint16_t : 3; + __IOM uint16_t PCOMPENB : 1; /*!< [7..7] PVDD Start-up Detection */ + __IOM uint16_t HSIUP : 4; /*!< [11..8] HS Output Level Setting */ + __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset + * value for adjusting the terminating resistance. */ + uint16_t : 1; + } PHYTRIM1_b; + }; + + union + { + __IOM uint16_t PHYTRIM2; /*!< (@ 0x00000152) PHY Timing Register 2 */ + + struct + { + __IOM uint16_t SQU : 4; /*!< [3..0] Squelch Detection Level */ + uint16_t : 3; + __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode */ + __IOM uint16_t PDR : 2; /*!< [9..8] HS Output Adjustment Function */ + uint16_t : 2; + __IOM uint16_t DIS : 3; /*!< [14..12] Disconnect Detection Level */ + uint16_t : 1; + } PHYTRIM2_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IM uint32_t DPUSR0R; /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor + * Register */ + + struct + { + uint32_t : 20; + __IM uint32_t DOVCAHM : 1; /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the + * HS side of USB port. */ + __IM uint32_t DOVCBHM : 1; /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the + * HS side of USB port. */ + uint32_t : 1; + __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side + * of USB port. */ + uint32_t : 8; + } DPUSR0R_b; + }; + + union + { + __IOM uint32_t DPUSR1R; /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t DOVCAHE : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear */ + __IOM uint32_t DOVCBHE : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear */ + uint32_t : 1; + __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear */ + uint32_t : 12; + __IM uint32_t DOVCAH : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source */ + __IM uint32_t DOVCBH : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source */ + uint32_t : 1; + __IM uint32_t DVBSTSH : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source */ + uint32_t : 8; + } DPUSR1R_b; + }; + + union + { + __IOM uint16_t DPUSR2R; /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */ + + struct + { + __IM uint16_t DPINT : 1; /*!< [0..0] Indication of Return from DP Interrupt Source */ + __IM uint16_t DMINT : 1; /*!< [1..1] Indication of Return from DM Interrupt Source */ + uint16_t : 2; + __IM uint16_t DPVAL : 1; /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB + * port. */ + __IM uint16_t DMVAL : 1; /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB + * port. */ + uint16_t : 2; + __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear */ + __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear */ + uint16_t : 6; + } DPUSR2R_b; + }; + + union + { + __IOM uint16_t DPUSRCR; /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */ + + struct + { + __IOM uint16_t FIXPHY : 1; /*!< [0..0] USB Transceiver Control Fix */ + __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL */ + uint16_t : 14; + } DPUSRCR_b; + }; +} R_USB_HS0_Type; /*!< Size = 364 (0x16c) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGT0_BASE 0x400E8000UL + #define R_AGT1_BASE 0x400E8100UL + #define R_AGT2_BASE 0x400E8200UL + #define R_AGT3_BASE 0x400E8300UL + #define R_AGT4_BASE 0x400E8400UL + #define R_AGT5_BASE 0x400E8500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CANFD_BASE 0x400B0000UL + #define R_CRC_BASE 0x40108000UL + #define R_CTSU_BASE 0x400D0000UL + #define R_DAC_BASE 0x40171000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40109000UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_ETHERC0_BASE 0x40114100UL + #define R_ETHERC_EDMAC_BASE 0x40114000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IWDT_BASE 0x40083200UL + #define R_I3C0_BASE 0x4011F000UL + #define R_I3C1_BASE 0x4011F400UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x40080000UL + #define R_PORT1_BASE 0x40080020UL + #define R_PORT2_BASE 0x40080040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x40080140UL + #define R_PORT11_BASE 0x40080160UL + #define R_PORT12_BASE 0x40080180UL + #define R_PORT13_BASE 0x400801A0UL + #define R_PORT14_BASE 0x400801C0UL + #define R_PFS_BASE 0x40080800UL + #define R_PMISC_BASE 0x40080D00UL + #define R_QSPI_BASE 0x64000000UL + #define R_RTC_BASE 0x40083000UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SDHI0_BASE 0x40092000UL + #define R_SDHI1_BASE 0x40092400UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SSI0_BASE 0x4009D000UL + #define R_SSI1_BASE 0x4009D100UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x400F3228UL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_USB_FS0_BASE 0x40090000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + #define R_CEC_BASE 0x400AC000UL + #define R_OSPI_BASE 0x400A6000UL + #define R_USB_HS0_BASE 0x40111000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_ETHERC0 ((R_ETHERC0_Type *) R_ETHERC0_BASE) + #define R_ETHERC_EDMAC ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_QSPI ((R_QSPI_Type *) R_QSPI_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SDHI0 ((R_SDHI0_Type *) R_SDHI0_BASE) + #define R_SDHI1 ((R_SDHI0_Type *) R_SDHI1_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) + #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_CEC ((R_CEC_Type *) R_CEC_BASE) + #define R_OSPI ((R_OSPI_Type *) R_OSPI_BASE) + #define R_USB_HS0 ((R_USB_HS0_Type *) R_USB_HS0_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ + #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ + #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ + #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ RTCCR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RTCCR ========================================================= */ + #define R_RTC_RTCCR_RTCCR_TCNF_Pos (4UL) /*!< TCNF (Bit 4) */ + #define R_RTC_RTCCR_RTCCR_TCNF_Msk (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03) */ + #define R_RTC_RTCCR_RTCCR_TCST_Pos (2UL) /*!< TCST (Bit 2) */ + #define R_RTC_RTCCR_RTCCR_TCST_Msk (0x4UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Pos (0UL) /*!< TCCT (Bit 0) */ + #define R_RTC_RTCCR_RTCCR_TCCT_Msk (0x3UL) /*!< TCCT (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSEC ========================================================== */ + #define R_RTC_CP_RSEC_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_CP_RSEC_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RSEC_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_CP_RSEC_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_CP_BCNT0_BCNT0CP_Pos (0UL) /*!< BCNT0CP (Bit 0) */ + #define R_RTC_CP_BCNT0_BCNT0CP_Msk (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMIN ========================================================== */ + #define R_RTC_CP_RMIN_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_CP_RMIN_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_CP_RMIN_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_CP_RMIN_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_CP_BCNT1_BCNT1CP_Pos (0UL) /*!< BCNT1CP (Bit 0) */ + #define R_RTC_CP_BCNT1_BCNT1CP_Msk (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff) */ +/* ========================================================== RHR ========================================================== */ + #define R_RTC_CP_RHR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_CP_RHR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RHR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_CP_RHR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RHR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_CP_RHR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_CP_BCNT2_BCNT2CP_Pos (0UL) /*!< BCNT2CP (Bit 0) */ + #define R_RTC_CP_BCNT2_BCNT2CP_Msk (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RDAY ========================================================== */ + #define R_RTC_CP_RDAY_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_CP_RDAY_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_CP_RDAY_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_CP_RDAY_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_CP_BCNT3_BCNT3CP_Pos (0UL) /*!< BCNT3CP (Bit 0) */ + #define R_RTC_CP_BCNT3_BCNT3CP_Msk (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff) */ +/* ========================================================= RMON ========================================================== */ + #define R_RTC_CP_RMON_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_CP_RMON_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_FS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USB_HS0_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ + #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDGCRCCFG ======================================================= */ + #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */ + #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDGLOTB ======================================================== */ + #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ + #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ + #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_CTSU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTSUCR0 ======================================================== */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos (7UL) /*!< CTSUTXVSEL (Bit 7) */ + #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk (0x80UL) /*!< CTSUTXVSEL (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Pos (4UL) /*!< CTSUINIT (Bit 4) */ + #define R_CTSU_CTSUCR0_CTSUINIT_Msk (0x10UL) /*!< CTSUINIT (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Pos (3UL) /*!< CTSUIOC (Bit 3) */ + #define R_CTSU_CTSUCR0_CTSUIOC_Msk (0x8UL) /*!< CTSUIOC (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Pos (2UL) /*!< CTSUSNZ (Bit 2) */ + #define R_CTSU_CTSUCR0_CTSUSNZ_Msk (0x4UL) /*!< CTSUSNZ (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Pos (1UL) /*!< CTSUCAP (Bit 1) */ + #define R_CTSU_CTSUCR0_CTSUCAP_Msk (0x2UL) /*!< CTSUCAP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Pos (0UL) /*!< CTSUSTRT (Bit 0) */ + #define R_CTSU_CTSUCR0_CTSUSTRT_Msk (0x1UL) /*!< CTSUSTRT (Bitfield-Mask: 0x01) */ +/* ======================================================== CTSUCR1 ======================================================== */ + #define R_CTSU_CTSUCR1_CTSUMD_Pos (6UL) /*!< CTSUMD (Bit 6) */ + #define R_CTSU_CTSUCR1_CTSUMD_Msk (0xc0UL) /*!< CTSUMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Pos (4UL) /*!< CTSUCLK (Bit 4) */ + #define R_CTSU_CTSUCR1_CTSUCLK_Msk (0x30UL) /*!< CTSUCLK (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos (3UL) /*!< CTSUATUNE1 (Bit 3) */ + #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk (0x8UL) /*!< CTSUATUNE1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos (2UL) /*!< CTSUATUNE0 (Bit 2) */ + #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk (0x4UL) /*!< CTSUATUNE0 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Pos (1UL) /*!< CTSUCSW (Bit 1) */ + #define R_CTSU_CTSUCR1_CTSUCSW_Msk (0x2UL) /*!< CTSUCSW (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUCR1_CTSUPON_Pos (0UL) /*!< CTSUPON (Bit 0) */ + #define R_CTSU_CTSUCR1_CTSUPON_Msk (0x1UL) /*!< CTSUPON (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUSDPRS ======================================================= */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos (6UL) /*!< CTSUSOFF (Bit 6) */ + #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk (0x40UL) /*!< CTSUSOFF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos (4UL) /*!< CTSUPRMODE (Bit 4) */ + #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk (0x30UL) /*!< CTSUPRMODE (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos (0UL) /*!< CTSUPRRATIO (Bit 0) */ + #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk (0xfUL) /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSST ======================================================== */ + #define R_CTSU_CTSUSST_CTSUSST_Pos (0UL) /*!< CTSUSST (Bit 0) */ + #define R_CTSU_CTSUSST_CTSUSST_Msk (0xffUL) /*!< CTSUSST (Bitfield-Mask: 0xff) */ +/* ======================================================= CTSUMCH0 ======================================================== */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos (0UL) /*!< CTSUMCH0 (Bit 0) */ + #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk (0x3fUL) /*!< CTSUMCH0 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUMCH1 ======================================================== */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos (0UL) /*!< CTSUMCH1 (Bit 0) */ + #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk (0x3fUL) /*!< CTSUMCH1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= CTSUCHAC ======================================================== */ + #define R_CTSU_CTSUCHAC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHAC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUCHTRC ======================================================= */ + #define R_CTSU_CTSUCHTRC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CTSU_CTSUCHTRC_TS_Msk (0x1UL) /*!< TS (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUDCLKC ======================================================= */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos (4UL) /*!< CTSUSSCNT (Bit 4) */ + #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk (0x30UL) /*!< CTSUSSCNT (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos (0UL) /*!< CTSUSSMOD (Bit 0) */ + #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk (0x3UL) /*!< CTSUSSMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== CTSUST ========================================================= */ + #define R_CTSU_CTSUST_CTSUPS_Pos (7UL) /*!< CTSUPS (Bit 7) */ + #define R_CTSU_CTSUST_CTSUPS_Msk (0x80UL) /*!< CTSUPS (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUROVF_Pos (6UL) /*!< CTSUROVF (Bit 6) */ + #define R_CTSU_CTSUST_CTSUROVF_Msk (0x40UL) /*!< CTSUROVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSOVF_Pos (5UL) /*!< CTSUSOVF (Bit 5) */ + #define R_CTSU_CTSUST_CTSUSOVF_Msk (0x20UL) /*!< CTSUSOVF (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUDTSR_Pos (4UL) /*!< CTSUDTSR (Bit 4) */ + #define R_CTSU_CTSUST_CTSUDTSR_Msk (0x10UL) /*!< CTSUDTSR (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUST_CTSUSTC_Pos (0UL) /*!< CTSUSTC (Bit 0) */ + #define R_CTSU_CTSUST_CTSUSTC_Msk (0x7UL) /*!< CTSUSTC (Bitfield-Mask: 0x07) */ +/* ======================================================== CTSUSSC ======================================================== */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos (8UL) /*!< CTSUSSDIV (Bit 8) */ + #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk (0xf00UL) /*!< CTSUSSDIV (Bitfield-Mask: 0x0f) */ +/* ======================================================== CTSUSO0 ======================================================== */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Pos (10UL) /*!< CTSUSNUM (Bit 10) */ + #define R_CTSU_CTSUSO0_CTSUSNUM_Msk (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f) */ + #define R_CTSU_CTSUSO0_CTSUSO_Pos (0UL) /*!< CTSUSO (Bit 0) */ + #define R_CTSU_CTSUSO0_CTSUSO_Msk (0x3ffUL) /*!< CTSUSO (Bitfield-Mask: 0x3ff) */ +/* ======================================================== CTSUSO1 ======================================================== */ + #define R_CTSU_CTSUSO1_CTSUICOG_Pos (13UL) /*!< CTSUICOG (Bit 13) */ + #define R_CTSU_CTSUSO1_CTSUICOG_Msk (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Pos (8UL) /*!< CTSUSDPA (Bit 8) */ + #define R_CTSU_CTSUSO1_CTSUSDPA_Msk (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Pos (0UL) /*!< CTSURICOA (Bit 0) */ + #define R_CTSU_CTSUSO1_CTSURICOA_Msk (0xffUL) /*!< CTSURICOA (Bitfield-Mask: 0xff) */ +/* ======================================================== CTSUSC ========================================================= */ + #define R_CTSU_CTSUSC_CTSUSC_Pos (0UL) /*!< CTSUSC (Bit 0) */ + #define R_CTSU_CTSUSC_CTSUSC_Msk (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff) */ +/* ======================================================== CTSURC ========================================================= */ + #define R_CTSU_CTSURC_CTSURC_Pos (0UL) /*!< CTSURC (Bit 0) */ + #define R_CTSU_CTSURC_CTSURC_Msk (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff) */ +/* ======================================================= CTSUERRS ======================================================== */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Pos (15UL) /*!< CTSUICOMP (Bit 15) */ + #define R_CTSU_CTSUERRS_CTSUICOMP_Msk (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Pos (0UL) /*!< CTSUSPMD (Bit 0) */ + #define R_CTSU_CTSUERRS_CTSUSPMD_Msk (0x3UL) /*!< CTSUSPMD (Bitfield-Mask: 0x03) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Pos (2UL) /*!< CTSUTSOD (Bit 2) */ + #define R_CTSU_CTSUERRS_CTSUTSOD_Msk (0x4UL) /*!< CTSUTSOD (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Pos (3UL) /*!< CTSUDRV (Bit 3) */ + #define R_CTSU_CTSUERRS_CTSUDRV_Msk (0x8UL) /*!< CTSUDRV (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos (6UL) /*!< CTSUCLKSEL1 (Bit 6) */ + #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk (0x40UL) /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Pos (7UL) /*!< CTSUTSOC (Bit 7) */ + #define R_CTSU_CTSUERRS_CTSUTSOC_Msk (0x80UL) /*!< CTSUTSOC (Bitfield-Mask: 0x01) */ +/* ======================================================= CTSUTRMR ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ECMR ========================================================== */ + #define R_ETHERC0_ECMR_TPC_Pos (20UL) /*!< TPC (Bit 20) */ + #define R_ETHERC0_ECMR_TPC_Msk (0x100000UL) /*!< TPC (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ZPF_Pos (19UL) /*!< ZPF (Bit 19) */ + #define R_ETHERC0_ECMR_ZPF_Msk (0x80000UL) /*!< ZPF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PFR_Pos (18UL) /*!< PFR (Bit 18) */ + #define R_ETHERC0_ECMR_PFR_Msk (0x40000UL) /*!< PFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RXF_Pos (17UL) /*!< RXF (Bit 17) */ + #define R_ETHERC0_ECMR_RXF_Msk (0x20000UL) /*!< RXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TXF_Pos (16UL) /*!< TXF (Bit 16) */ + #define R_ETHERC0_ECMR_TXF_Msk (0x10000UL) /*!< TXF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRCEF_Pos (12UL) /*!< PRCEF (Bit 12) */ + #define R_ETHERC0_ECMR_PRCEF_Msk (0x1000UL) /*!< PRCEF (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_MPDE_Pos (9UL) /*!< MPDE (Bit 9) */ + #define R_ETHERC0_ECMR_MPDE_Msk (0x200UL) /*!< MPDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RE_Pos (6UL) /*!< RE (Bit 6) */ + #define R_ETHERC0_ECMR_RE_Msk (0x40UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_ETHERC0_ECMR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_ILB_Pos (3UL) /*!< ILB (Bit 3) */ + #define R_ETHERC0_ECMR_ILB_Msk (0x8UL) /*!< ILB (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_RTM_Pos (2UL) /*!< RTM (Bit 2) */ + #define R_ETHERC0_ECMR_RTM_Msk (0x4UL) /*!< RTM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_DM_Pos (1UL) /*!< DM (Bit 1) */ + #define R_ETHERC0_ECMR_DM_Msk (0x2UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECMR_PRM_Pos (0UL) /*!< PRM (Bit 0) */ + #define R_ETHERC0_ECMR_PRM_Msk (0x1UL) /*!< PRM (Bitfield-Mask: 0x01) */ +/* ========================================================= RFLR ========================================================== */ + #define R_ETHERC0_RFLR_RFL_Pos (0UL) /*!< RFL (Bit 0) */ + #define R_ETHERC0_RFLR_RFL_Msk (0xfffUL) /*!< RFL (Bitfield-Mask: 0xfff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_ETHERC0_ECSR_BFR_Pos (5UL) /*!< BFR (Bit 5) */ + #define R_ETHERC0_ECSR_BFR_Msk (0x20UL) /*!< BFR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_PSRTO_Pos (4UL) /*!< PSRTO (Bit 4) */ + #define R_ETHERC0_ECSR_PSRTO_Msk (0x10UL) /*!< PSRTO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_LCHNG_Pos (2UL) /*!< LCHNG (Bit 2) */ + #define R_ETHERC0_ECSR_LCHNG_Msk (0x4UL) /*!< LCHNG (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_MPD_Pos (1UL) /*!< MPD (Bit 1) */ + #define R_ETHERC0_ECSR_MPD_Msk (0x2UL) /*!< MPD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSR_ICD_Pos (0UL) /*!< ICD (Bit 0) */ + #define R_ETHERC0_ECSR_ICD_Msk (0x1UL) /*!< ICD (Bitfield-Mask: 0x01) */ +/* ======================================================== ECSIPR ========================================================= */ + #define R_ETHERC0_ECSIPR_BFSIPR_Pos (5UL) /*!< BFSIPR (Bit 5) */ + #define R_ETHERC0_ECSIPR_BFSIPR_Msk (0x20UL) /*!< BFSIPR (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Pos (4UL) /*!< PSRTOIP (Bit 4) */ + #define R_ETHERC0_ECSIPR_PSRTOIP_Msk (0x10UL) /*!< PSRTOIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Pos (2UL) /*!< LCHNGIP (Bit 2) */ + #define R_ETHERC0_ECSIPR_LCHNGIP_Msk (0x4UL) /*!< LCHNGIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_MPDIP_Pos (1UL) /*!< MPDIP (Bit 1) */ + #define R_ETHERC0_ECSIPR_MPDIP_Msk (0x2UL) /*!< MPDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_ECSIPR_ICDIP_Pos (0UL) /*!< ICDIP (Bit 0) */ + #define R_ETHERC0_ECSIPR_ICDIP_Msk (0x1UL) /*!< ICDIP (Bitfield-Mask: 0x01) */ +/* ========================================================== PIR ========================================================== */ + #define R_ETHERC0_PIR_MDI_Pos (3UL) /*!< MDI (Bit 3) */ + #define R_ETHERC0_PIR_MDI_Msk (0x8UL) /*!< MDI (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDO_Pos (2UL) /*!< MDO (Bit 2) */ + #define R_ETHERC0_PIR_MDO_Msk (0x4UL) /*!< MDO (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MMD_Pos (1UL) /*!< MMD (Bit 1) */ + #define R_ETHERC0_PIR_MMD_Msk (0x2UL) /*!< MMD (Bitfield-Mask: 0x01) */ + #define R_ETHERC0_PIR_MDC_Pos (0UL) /*!< MDC (Bit 0) */ + #define R_ETHERC0_PIR_MDC_Msk (0x1UL) /*!< MDC (Bitfield-Mask: 0x01) */ +/* ========================================================== PSR ========================================================== */ + #define R_ETHERC0_PSR_LMON_Pos (0UL) /*!< LMON (Bit 0) */ + #define R_ETHERC0_PSR_LMON_Msk (0x1UL) /*!< LMON (Bitfield-Mask: 0x01) */ +/* ========================================================= RDMLR ========================================================= */ + #define R_ETHERC0_RDMLR_RMD_Pos (0UL) /*!< RMD (Bit 0) */ + #define R_ETHERC0_RDMLR_RMD_Msk (0xfffffUL) /*!< RMD (Bitfield-Mask: 0xfffff) */ +/* ========================================================= IPGR ========================================================== */ + #define R_ETHERC0_IPGR_IPG_Pos (0UL) /*!< IPG (Bit 0) */ + #define R_ETHERC0_IPGR_IPG_Msk (0x1fUL) /*!< IPG (Bitfield-Mask: 0x1f) */ +/* ========================================================== APR ========================================================== */ + #define R_ETHERC0_APR_AP_Pos (0UL) /*!< AP (Bit 0) */ + #define R_ETHERC0_APR_AP_Msk (0xffffUL) /*!< AP (Bitfield-Mask: 0xffff) */ +/* ========================================================== MPR ========================================================== */ + #define R_ETHERC0_MPR_MP_Pos (0UL) /*!< MP (Bit 0) */ + #define R_ETHERC0_MPR_MP_Msk (0xffffUL) /*!< MP (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFCF ========================================================== */ + #define R_ETHERC0_RFCF_RPAUSE_Pos (0UL) /*!< RPAUSE (Bit 0) */ + #define R_ETHERC0_RFCF_RPAUSE_Msk (0xffUL) /*!< RPAUSE (Bitfield-Mask: 0xff) */ +/* ======================================================== TPAUSER ======================================================== */ + #define R_ETHERC0_TPAUSER_TPAUSE_Pos (0UL) /*!< TPAUSE (Bit 0) */ + #define R_ETHERC0_TPAUSER_TPAUSE_Msk (0xffffUL) /*!< TPAUSE (Bitfield-Mask: 0xffff) */ +/* ======================================================= TPAUSECR ======================================================== */ +/* ========================================================= BCFRR ========================================================= */ + #define R_ETHERC0_BCFRR_BCF_Pos (0UL) /*!< BCF (Bit 0) */ + #define R_ETHERC0_BCFRR_BCF_Msk (0xffffUL) /*!< BCF (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAHR ========================================================== */ + #define R_ETHERC0_MAHR_MAHR_Pos (0UL) /*!< MAHR (Bit 0) */ + #define R_ETHERC0_MAHR_MAHR_Msk (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MALR ========================================================== */ + #define R_ETHERC0_MALR_MALR_Pos (0UL) /*!< MALR (Bit 0) */ + #define R_ETHERC0_MALR_MALR_Msk (0xffffUL) /*!< MALR (Bitfield-Mask: 0xffff) */ +/* ========================================================= TROCR ========================================================= */ + #define R_ETHERC0_TROCR_TROCR_Pos (0UL) /*!< TROCR (Bit 0) */ + #define R_ETHERC0_TROCR_TROCR_Msk (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDCR ========================================================== */ +/* ========================================================= LCCR ========================================================== */ + #define R_ETHERC0_LCCR_LCCR_Pos (0UL) /*!< LCCR (Bit 0) */ + #define R_ETHERC0_LCCR_LCCR_Msk (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CNDCR ========================================================= */ + #define R_ETHERC0_CNDCR_CNDCR_Pos (0UL) /*!< CNDCR (Bit 0) */ + #define R_ETHERC0_CNDCR_CNDCR_Msk (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CEFCR ========================================================= */ + #define R_ETHERC0_CEFCR_CEFCR_Pos (0UL) /*!< CEFCR (Bit 0) */ + #define R_ETHERC0_CEFCR_CEFCR_Msk (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FRECR ========================================================= */ + #define R_ETHERC0_FRECR_FRECR_Pos (0UL) /*!< FRECR (Bit 0) */ + #define R_ETHERC0_FRECR_FRECR_Msk (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TSFRCR ========================================================= */ + #define R_ETHERC0_TSFRCR_TSFRCR_Pos (0UL) /*!< TSFRCR (Bit 0) */ + #define R_ETHERC0_TSFRCR_TSFRCR_Msk (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== TLFRCR ========================================================= */ + #define R_ETHERC0_TLFRCR_TLFRCR_Pos (0UL) /*!< TLFRCR (Bit 0) */ + #define R_ETHERC0_TLFRCR_TLFRCR_Msk (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RFCR ========================================================== */ + #define R_ETHERC0_RFCR_RFCR_Pos (0UL) /*!< RFCR (Bit 0) */ + #define R_ETHERC0_RFCR_RFCR_Msk (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= MAFCR ========================================================= */ + #define R_ETHERC0_MAFCR_MAFCR_Pos (0UL) /*!< MAFCR (Bit 0) */ + #define R_ETHERC0_MAFCR_MAFCR_Msk (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHERC_EDMAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= EDMR ========================================================== */ + #define R_ETHERC_EDMAC_EDMR_DE_Pos (6UL) /*!< DE (Bit 6) */ + #define R_ETHERC_EDMAC_EDMR_DE_Msk (0x40UL) /*!< DE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EDMR_DL_Pos (4UL) /*!< DL (Bit 4) */ + #define R_ETHERC_EDMAC_EDMR_DL_Msk (0x30UL) /*!< DL (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_ETHERC_EDMAC_EDMR_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDTRR ========================================================= */ + #define R_ETHERC_EDMAC_EDTRR_TR_Pos (0UL) /*!< TR (Bit 0) */ + #define R_ETHERC_EDMAC_EDTRR_TR_Msk (0x1UL) /*!< TR (Bitfield-Mask: 0x01) */ +/* ========================================================= EDRRR ========================================================= */ + #define R_ETHERC_EDMAC_EDRRR_RR_Pos (0UL) /*!< RR (Bit 0) */ + #define R_ETHERC_EDMAC_EDRRR_RR_Msk (0x1UL) /*!< RR (Bitfield-Mask: 0x01) */ +/* ========================================================= TDLAR ========================================================= */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos (0UL) /*!< TDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDLAR ========================================================= */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos (0UL) /*!< RDLAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= EESR ========================================================== */ + #define R_ETHERC_EDMAC_EESR_TWB_Pos (30UL) /*!< TWB (Bit 30) */ + #define R_ETHERC_EDMAC_EESR_TWB_Msk (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TABT_Pos (26UL) /*!< TABT (Bit 26) */ + #define R_ETHERC_EDMAC_EESR_TABT_Msk (0x4000000UL) /*!< TABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RABT_Pos (25UL) /*!< RABT (Bit 25) */ + #define R_ETHERC_EDMAC_EESR_RABT_Msk (0x2000000UL) /*!< RABT (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Pos (24UL) /*!< RFCOF (Bit 24) */ + #define R_ETHERC_EDMAC_EESR_RFCOF_Msk (0x1000000UL) /*!< RFCOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ADE_Pos (23UL) /*!< ADE (Bit 23) */ + #define R_ETHERC_EDMAC_EESR_ADE_Msk (0x800000UL) /*!< ADE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_ECI_Pos (22UL) /*!< ECI (Bit 22) */ + #define R_ETHERC_EDMAC_EESR_ECI_Msk (0x400000UL) /*!< ECI (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TC_Pos (21UL) /*!< TC (Bit 21) */ + #define R_ETHERC_EDMAC_EESR_TC_Msk (0x200000UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TDE_Pos (20UL) /*!< TDE (Bit 20) */ + #define R_ETHERC_EDMAC_EESR_TDE_Msk (0x100000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Pos (19UL) /*!< TFUF (Bit 19) */ + #define R_ETHERC_EDMAC_EESR_TFUF_Msk (0x80000UL) /*!< TFUF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_FR_Pos (18UL) /*!< FR (Bit 18) */ + #define R_ETHERC_EDMAC_EESR_FR_Msk (0x40000UL) /*!< FR (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RDE_Pos (17UL) /*!< RDE (Bit 17) */ + #define R_ETHERC_EDMAC_EESR_RDE_Msk (0x20000UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Pos (16UL) /*!< RFOF (Bit 16) */ + #define R_ETHERC_EDMAC_EESR_RFOF_Msk (0x10000UL) /*!< RFOF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CND_Pos (11UL) /*!< CND (Bit 11) */ + #define R_ETHERC_EDMAC_EESR_CND_Msk (0x800UL) /*!< CND (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_DLC_Pos (10UL) /*!< DLC (Bit 10) */ + #define R_ETHERC_EDMAC_EESR_DLC_Msk (0x400UL) /*!< DLC (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CD_Pos (9UL) /*!< CD (Bit 9) */ + #define R_ETHERC_EDMAC_EESR_CD_Msk (0x200UL) /*!< CD (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_TRO_Pos (8UL) /*!< TRO (Bit 8) */ + #define R_ETHERC_EDMAC_EESR_TRO_Msk (0x100UL) /*!< TRO (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Pos (7UL) /*!< RMAF (Bit 7) */ + #define R_ETHERC_EDMAC_EESR_RMAF_Msk (0x80UL) /*!< RMAF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RRF_Pos (4UL) /*!< RRF (Bit 4) */ + #define R_ETHERC_EDMAC_EESR_RRF_Msk (0x10UL) /*!< RRF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Pos (3UL) /*!< RTLF (Bit 3) */ + #define R_ETHERC_EDMAC_EESR_RTLF_Msk (0x8UL) /*!< RTLF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Pos (2UL) /*!< RTSF (Bit 2) */ + #define R_ETHERC_EDMAC_EESR_RTSF_Msk (0x4UL) /*!< RTSF (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_PRE_Pos (1UL) /*!< PRE (Bit 1) */ + #define R_ETHERC_EDMAC_EESR_PRE_Msk (0x2UL) /*!< PRE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESR_CERF_Pos (0UL) /*!< CERF (Bit 0) */ + #define R_ETHERC_EDMAC_EESR_CERF_Msk (0x1UL) /*!< CERF (Bitfield-Mask: 0x01) */ +/* ======================================================== EESIPR ========================================================= */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos (30UL) /*!< TWBIP (Bit 30) */ + #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos (26UL) /*!< TABTIP (Bit 26) */ + #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk (0x4000000UL) /*!< TABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos (25UL) /*!< RABTIP (Bit 25) */ + #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk (0x2000000UL) /*!< RABTIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos (24UL) /*!< RFCOFIP (Bit 24) */ + #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk (0x1000000UL) /*!< RFCOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos (23UL) /*!< ADEIP (Bit 23) */ + #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk (0x800000UL) /*!< ADEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos (22UL) /*!< ECIIP (Bit 22) */ + #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk (0x400000UL) /*!< ECIIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos (21UL) /*!< TCIP (Bit 21) */ + #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk (0x200000UL) /*!< TCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos (20UL) /*!< TDEIP (Bit 20) */ + #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk (0x100000UL) /*!< TDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos (19UL) /*!< TFUFIP (Bit 19) */ + #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk (0x80000UL) /*!< TFUFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos (18UL) /*!< FRIP (Bit 18) */ + #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk (0x40000UL) /*!< FRIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos (17UL) /*!< RDEIP (Bit 17) */ + #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk (0x20000UL) /*!< RDEIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos (16UL) /*!< RFOFIP (Bit 16) */ + #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk (0x10000UL) /*!< RFOFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos (11UL) /*!< CNDIP (Bit 11) */ + #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk (0x800UL) /*!< CNDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos (10UL) /*!< DLCIP (Bit 10) */ + #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk (0x400UL) /*!< DLCIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos (9UL) /*!< CDIP (Bit 9) */ + #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk (0x200UL) /*!< CDIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos (8UL) /*!< TROIP (Bit 8) */ + #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk (0x100UL) /*!< TROIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos (7UL) /*!< RMAFIP (Bit 7) */ + #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk (0x80UL) /*!< RMAFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos (4UL) /*!< RRFIP (Bit 4) */ + #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk (0x10UL) /*!< RRFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos (3UL) /*!< RTLFIP (Bit 3) */ + #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk (0x8UL) /*!< RTLFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos (2UL) /*!< RTSFIP (Bit 2) */ + #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk (0x4UL) /*!< RTSFIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos (1UL) /*!< PREIP (Bit 1) */ + #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk (0x2UL) /*!< PREIP (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos (0UL) /*!< CERFIP (Bit 0) */ + #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk (0x1UL) /*!< CERFIP (Bitfield-Mask: 0x01) */ +/* ======================================================== TRSCER ========================================================= */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos (7UL) /*!< RMAFCE (Bit 7) */ + #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk (0x80UL) /*!< RMAFCE (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos (4UL) /*!< RRFCE (Bit 4) */ + #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk (0x10UL) /*!< RRFCE (Bitfield-Mask: 0x01) */ +/* ========================================================= RMFCR ========================================================= */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Pos (0UL) /*!< MFC (Bit 0) */ + #define R_ETHERC_EDMAC_RMFCR_MFC_Msk (0xffffUL) /*!< MFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TFTR ========================================================== */ + #define R_ETHERC_EDMAC_TFTR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_ETHERC_EDMAC_TFTR_TFT_Msk (0x7ffUL) /*!< TFT (Bitfield-Mask: 0x7ff) */ +/* ========================================================== FDR ========================================================== */ + #define R_ETHERC_EDMAC_FDR_TFD_Pos (8UL) /*!< TFD (Bit 8) */ + #define R_ETHERC_EDMAC_FDR_TFD_Msk (0x1f00UL) /*!< TFD (Bitfield-Mask: 0x1f) */ + #define R_ETHERC_EDMAC_FDR_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHERC_EDMAC_FDR_RFD_Msk (0x1fUL) /*!< RFD (Bitfield-Mask: 0x1f) */ +/* ========================================================= RMCR ========================================================== */ + #define R_ETHERC_EDMAC_RMCR_RNR_Pos (0UL) /*!< RNR (Bit 0) */ + #define R_ETHERC_EDMAC_RMCR_RNR_Msk (0x1UL) /*!< RNR (Bitfield-Mask: 0x01) */ +/* ========================================================= TFUCR ========================================================= */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos (0UL) /*!< UNDER (Bit 0) */ + #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk (0xffffUL) /*!< UNDER (Bitfield-Mask: 0xffff) */ +/* ========================================================= RFOCR ========================================================= */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Pos (0UL) /*!< OVER (Bit 0) */ + #define R_ETHERC_EDMAC_RFOCR_OVER_Msk (0xffffUL) /*!< OVER (Bitfield-Mask: 0xffff) */ +/* ========================================================= IOSR ========================================================== */ + #define R_ETHERC_EDMAC_IOSR_ELB_Pos (0UL) /*!< ELB (Bit 0) */ + #define R_ETHERC_EDMAC_IOSR_ELB_Msk (0x1UL) /*!< ELB (Bitfield-Mask: 0x01) */ +/* ========================================================= FCFTR ========================================================= */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos (16UL) /*!< RFFO (Bit 16) */ + #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk (0x70000UL) /*!< RFFO (Bitfield-Mask: 0x07) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos (0UL) /*!< RFDO (Bit 0) */ + #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk (0x7UL) /*!< RFDO (Bitfield-Mask: 0x07) */ +/* ======================================================== RPADIR ========================================================= */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Pos (16UL) /*!< PADS (Bit 16) */ + #define R_ETHERC_EDMAC_RPADIR_PADS_Msk (0x30000UL) /*!< PADS (Bitfield-Mask: 0x03) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Pos (0UL) /*!< PADR (Bit 0) */ + #define R_ETHERC_EDMAC_RPADIR_PADR_Msk (0x3fUL) /*!< PADR (Bitfield-Mask: 0x3f) */ +/* ========================================================= TRIMD ========================================================= */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Pos (4UL) /*!< TIM (Bit 4) */ + #define R_ETHERC_EDMAC_TRIMD_TIM_Msk (0x10UL) /*!< TIM (Bitfield-Mask: 0x01) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Pos (0UL) /*!< TIS (Bit 0) */ + #define R_ETHERC_EDMAC_TRIMD_TIS_Msk (0x1UL) /*!< TIS (Bitfield-Mask: 0x01) */ +/* ========================================================= RBWAR ========================================================= */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos (0UL) /*!< RBWAR (Bit 0) */ + #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= RDFAR ========================================================= */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos (0UL) /*!< RDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TBRAR ========================================================= */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos (0UL) /*!< TBRAR (Bit 0) */ + #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= TDFAR ========================================================= */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos (0UL) /*!< TDFAR (Bit 0) */ + #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_QSPI ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SFMSMD ========================================================= */ + #define R_QSPI_SFMSMD_SFMCCE_Pos (15UL) /*!< SFMCCE (Bit 15) */ + #define R_QSPI_SFMSMD_SFMCCE_Msk (0x8000UL) /*!< SFMCCE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOSW_Pos (11UL) /*!< SFMOSW (Bit 11) */ + #define R_QSPI_SFMSMD_SFMOSW_Msk (0x800UL) /*!< SFMOSW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOHW_Pos (10UL) /*!< SFMOHW (Bit 10) */ + #define R_QSPI_SFMSMD_SFMOHW_Msk (0x400UL) /*!< SFMOHW (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMOEX_Pos (9UL) /*!< SFMOEX (Bit 9) */ + #define R_QSPI_SFMSMD_SFMOEX_Msk (0x200UL) /*!< SFMOEX (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMMD3_Pos (8UL) /*!< SFMMD3 (Bit 8) */ + #define R_QSPI_SFMSMD_SFMMD3_Msk (0x100UL) /*!< SFMMD3 (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPAE_Pos (7UL) /*!< SFMPAE (Bit 7) */ + #define R_QSPI_SFMSMD_SFMPAE_Msk (0x80UL) /*!< SFMPAE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMPFE_Pos (6UL) /*!< SFMPFE (Bit 6) */ + #define R_QSPI_SFMSMD_SFMPFE_Msk (0x40UL) /*!< SFMPFE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSMD_SFMSE_Pos (4UL) /*!< SFMSE (Bit 4) */ + #define R_QSPI_SFMSMD_SFMSE_Msk (0x30UL) /*!< SFMSE (Bitfield-Mask: 0x03) */ + #define R_QSPI_SFMSMD_SFMRM_Pos (0UL) /*!< SFMRM (Bit 0) */ + #define R_QSPI_SFMSMD_SFMRM_Msk (0x7UL) /*!< SFMRM (Bitfield-Mask: 0x07) */ +/* ======================================================== SFMSSC ========================================================= */ + #define R_QSPI_SFMSSC_SFMSLD_Pos (5UL) /*!< SFMSLD (Bit 5) */ + #define R_QSPI_SFMSSC_SFMSLD_Msk (0x20UL) /*!< SFMSLD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSHD_Pos (4UL) /*!< SFMSHD (Bit 4) */ + #define R_QSPI_SFMSSC_SFMSHD_Msk (0x10UL) /*!< SFMSHD (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSSC_SFMSW_Pos (0UL) /*!< SFMSW (Bit 0) */ + #define R_QSPI_SFMSSC_SFMSW_Msk (0xfUL) /*!< SFMSW (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSKC ========================================================= */ + #define R_QSPI_SFMSKC_SFMDTY_Pos (5UL) /*!< SFMDTY (Bit 5) */ + #define R_QSPI_SFMSKC_SFMDTY_Msk (0x20UL) /*!< SFMDTY (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSKC_SFMDV_Pos (0UL) /*!< SFMDV (Bit 0) */ + #define R_QSPI_SFMSKC_SFMDV_Msk (0x1fUL) /*!< SFMDV (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMSST ========================================================= */ + #define R_QSPI_SFMSST_PFOFF_Pos (7UL) /*!< PFOFF (Bit 7) */ + #define R_QSPI_SFMSST_PFOFF_Msk (0x80UL) /*!< PFOFF (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFFUL_Pos (6UL) /*!< PFFUL (Bit 6) */ + #define R_QSPI_SFMSST_PFFUL_Msk (0x40UL) /*!< PFFUL (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSST_PFCNT_Pos (0UL) /*!< PFCNT (Bit 0) */ + #define R_QSPI_SFMSST_PFCNT_Msk (0x1fUL) /*!< PFCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================== SFMCOM ========================================================= */ + #define R_QSPI_SFMCOM_SFMD_Pos (0UL) /*!< SFMD (Bit 0) */ + #define R_QSPI_SFMCOM_SFMD_Msk (0xffUL) /*!< SFMD (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMCMD ========================================================= */ + #define R_QSPI_SFMCMD_DCOM_Pos (0UL) /*!< DCOM (Bit 0) */ + #define R_QSPI_SFMCMD_DCOM_Msk (0x1UL) /*!< DCOM (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCST ========================================================= */ + #define R_QSPI_SFMCST_EROMR_Pos (7UL) /*!< EROMR (Bit 7) */ + #define R_QSPI_SFMCST_EROMR_Msk (0x80UL) /*!< EROMR (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMCST_COMBSY_Pos (0UL) /*!< COMBSY (Bit 0) */ + #define R_QSPI_SFMCST_COMBSY_Msk (0x1UL) /*!< COMBSY (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMSIC ========================================================= */ + #define R_QSPI_SFMSIC_SFMCIC_Pos (0UL) /*!< SFMCIC (Bit 0) */ + #define R_QSPI_SFMSIC_SFMCIC_Msk (0xffUL) /*!< SFMCIC (Bitfield-Mask: 0xff) */ +/* ======================================================== SFMSAC ========================================================= */ + #define R_QSPI_SFMSAC_SFM4BC_Pos (4UL) /*!< SFM4BC (Bit 4) */ + #define R_QSPI_SFMSAC_SFM4BC_Msk (0x10UL) /*!< SFM4BC (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSAC_SFMAS_Pos (0UL) /*!< SFMAS (Bit 0) */ + #define R_QSPI_SFMSAC_SFMAS_Msk (0x3UL) /*!< SFMAS (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMSDC ========================================================= */ + #define R_QSPI_SFMSDC_SFMXD_Pos (8UL) /*!< SFMXD (Bit 8) */ + #define R_QSPI_SFMSDC_SFMXD_Msk (0xff00UL) /*!< SFMXD (Bitfield-Mask: 0xff) */ + #define R_QSPI_SFMSDC_SFMXEN_Pos (7UL) /*!< SFMXEN (Bit 7) */ + #define R_QSPI_SFMSDC_SFMXEN_Msk (0x80UL) /*!< SFMXEN (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMXST_Pos (6UL) /*!< SFMXST (Bit 6) */ + #define R_QSPI_SFMSDC_SFMXST_Msk (0x40UL) /*!< SFMXST (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSDC_SFMDN_Pos (0UL) /*!< SFMDN (Bit 0) */ + #define R_QSPI_SFMSDC_SFMDN_Msk (0xfUL) /*!< SFMDN (Bitfield-Mask: 0x0f) */ +/* ======================================================== SFMSPC ========================================================= */ + #define R_QSPI_SFMSPC_SFMSDE_Pos (4UL) /*!< SFMSDE (Bit 4) */ + #define R_QSPI_SFMSPC_SFMSDE_Msk (0x10UL) /*!< SFMSDE (Bitfield-Mask: 0x01) */ + #define R_QSPI_SFMSPC_SFMSPI_Pos (0UL) /*!< SFMSPI (Bit 0) */ + #define R_QSPI_SFMSPC_SFMSPI_Msk (0x3UL) /*!< SFMSPI (Bitfield-Mask: 0x03) */ +/* ======================================================== SFMPMD ========================================================= */ + #define R_QSPI_SFMPMD_SFMWPL_Pos (2UL) /*!< SFMWPL (Bit 2) */ + #define R_QSPI_SFMPMD_SFMWPL_Msk (0x4UL) /*!< SFMWPL (Bitfield-Mask: 0x01) */ +/* ======================================================== SFMCNT1 ======================================================== */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Pos (26UL) /*!< QSPI_EXT (Bit 26) */ + #define R_QSPI_SFMCNT1_QSPI_EXT_Msk (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== R64CNT ========================================================= */ + #define R_RTC_R64CNT_F1HZ_Pos (6UL) /*!< F1HZ (Bit 6) */ + #define R_RTC_R64CNT_F1HZ_Msk (0x40UL) /*!< F1HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F2HZ_Pos (5UL) /*!< F2HZ (Bit 5) */ + #define R_RTC_R64CNT_F2HZ_Msk (0x20UL) /*!< F2HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F4HZ_Pos (4UL) /*!< F4HZ (Bit 4) */ + #define R_RTC_R64CNT_F4HZ_Msk (0x10UL) /*!< F4HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F8HZ_Pos (3UL) /*!< F8HZ (Bit 3) */ + #define R_RTC_R64CNT_F8HZ_Msk (0x8UL) /*!< F8HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F16HZ_Pos (2UL) /*!< F16HZ (Bit 2) */ + #define R_RTC_R64CNT_F16HZ_Msk (0x4UL) /*!< F16HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F32HZ_Pos (1UL) /*!< F32HZ (Bit 1) */ + #define R_RTC_R64CNT_F32HZ_Msk (0x2UL) /*!< F32HZ (Bitfield-Mask: 0x01) */ + #define R_RTC_R64CNT_F64HZ_Pos (0UL) /*!< F64HZ (Bit 0) */ + #define R_RTC_R64CNT_F64HZ_Msk (0x1UL) /*!< F64HZ (Bitfield-Mask: 0x01) */ +/* ======================================================== RSECCNT ======================================================== */ + #define R_RTC_RSECCNT_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECCNT_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECCNT_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECCNT_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT0 ========================================================= */ + #define R_RTC_BCNT0_BCNT0_Pos (0UL) /*!< BCNT0 (Bit 0) */ + #define R_RTC_BCNT0_BCNT0_Msk (0xffUL) /*!< BCNT0 (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINCNT ======================================================== */ + #define R_RTC_RMINCNT_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINCNT_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINCNT_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINCNT_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT1 ========================================================= */ + #define R_RTC_BCNT1_BCNT1_Pos (0UL) /*!< BCNT1 (Bit 0) */ + #define R_RTC_BCNT1_BCNT1_Msk (0xffUL) /*!< BCNT1 (Bitfield-Mask: 0xff) */ +/* ======================================================== RHRCNT ========================================================= */ + #define R_RTC_RHRCNT_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRCNT_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRCNT_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRCNT_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRCNT_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRCNT_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ========================================================= BCNT2 ========================================================= */ + #define R_RTC_BCNT2_BCNT2_Pos (0UL) /*!< BCNT2 (Bit 0) */ + #define R_RTC_BCNT2_BCNT2_Msk (0xffUL) /*!< BCNT2 (Bitfield-Mask: 0xff) */ +/* ======================================================== RWKCNT ========================================================= */ + #define R_RTC_RWKCNT_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKCNT_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ========================================================= BCNT3 ========================================================= */ + #define R_RTC_BCNT3_BCNT3_Pos (0UL) /*!< BCNT3 (Bit 0) */ + #define R_RTC_BCNT3_BCNT3_Msk (0xffUL) /*!< BCNT3 (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYCNT ======================================================== */ + #define R_RTC_RDAYCNT_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYCNT_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYCNT_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYCNT_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RMONCNT ======================================================== */ + #define R_RTC_RMONCNT_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONCNT_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONCNT_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONCNT_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RYRCNT ========================================================= */ + #define R_RTC_RYRCNT_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRCNT_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRCNT_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRCNT_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== RSECAR ========================================================= */ + #define R_RTC_RSECAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RSECAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RSECAR_SEC10_Pos (4UL) /*!< SEC10 (Bit 4) */ + #define R_RTC_RSECAR_SEC10_Msk (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RSECAR_SEC1_Pos (0UL) /*!< SEC1 (Bit 0) */ + #define R_RTC_RSECAR_SEC1_Msk (0xfUL) /*!< SEC1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT0AR ======================================================== */ + #define R_RTC_BCNT0AR_BCNT0AR_Pos (0UL) /*!< BCNT0AR (Bit 0) */ + #define R_RTC_BCNT0AR_BCNT0AR_Msk (0xffUL) /*!< BCNT0AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RMINAR ========================================================= */ + #define R_RTC_RMINAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMINAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMINAR_MIN10_Pos (4UL) /*!< MIN10 (Bit 4) */ + #define R_RTC_RMINAR_MIN10_Msk (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07) */ + #define R_RTC_RMINAR_MIN1_Pos (0UL) /*!< MIN1 (Bit 0) */ + #define R_RTC_RMINAR_MIN1_Msk (0xfUL) /*!< MIN1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT1AR ======================================================== */ + #define R_RTC_BCNT1AR_BCNT1AR_Pos (0UL) /*!< BCNT1AR (Bit 0) */ + #define R_RTC_BCNT1AR_BCNT1AR_Msk (0xffUL) /*!< BCNT1AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RHRAR ========================================================= */ + #define R_RTC_RHRAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RHRAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_PM_Pos (6UL) /*!< PM (Bit 6) */ + #define R_RTC_RHRAR_PM_Msk (0x40UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_RTC_RHRAR_HR10_Pos (4UL) /*!< HR10 (Bit 4) */ + #define R_RTC_RHRAR_HR10_Msk (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RHRAR_HR1_Pos (0UL) /*!< HR1 (Bit 0) */ + #define R_RTC_RHRAR_HR1_Msk (0xfUL) /*!< HR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== BCNT2AR ======================================================== */ + #define R_RTC_BCNT2AR_BCNT2AR_Pos (0UL) /*!< BCNT2AR (Bit 0) */ + #define R_RTC_BCNT2AR_BCNT2AR_Msk (0xffUL) /*!< BCNT2AR (Bitfield-Mask: 0xff) */ +/* ========================================================= RWKAR ========================================================= */ + #define R_RTC_RWKAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RWKAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RWKAR_DAYW_Pos (0UL) /*!< DAYW (Bit 0) */ + #define R_RTC_RWKAR_DAYW_Msk (0x7UL) /*!< DAYW (Bitfield-Mask: 0x07) */ +/* ======================================================== BCNT3AR ======================================================== */ + #define R_RTC_BCNT3AR_BCNT3AR_Pos (0UL) /*!< BCNT3AR (Bit 0) */ + #define R_RTC_BCNT3AR_BCNT3AR_Msk (0xffUL) /*!< BCNT3AR (Bitfield-Mask: 0xff) */ +/* ======================================================== RDAYAR ========================================================= */ + #define R_RTC_RDAYAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RDAYAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RDAYAR_DATE10_Pos (4UL) /*!< DATE10 (Bit 4) */ + #define R_RTC_RDAYAR_DATE10_Msk (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03) */ + #define R_RTC_RDAYAR_DATE1_Pos (0UL) /*!< DATE1 (Bit 0) */ + #define R_RTC_RDAYAR_DATE1_Msk (0xfUL) /*!< DATE1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT0AER ======================================================== */ + #define R_RTC_BCNT0AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT0AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RMONAR ========================================================= */ + #define R_RTC_RMONAR_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RMONAR_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON10_Pos (4UL) /*!< MON10 (Bit 4) */ + #define R_RTC_RMONAR_MON10_Msk (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01) */ + #define R_RTC_RMONAR_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ + #define R_RTC_RMONAR_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT1AER ======================================================== */ + #define R_RTC_BCNT1AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT1AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RYRAR ========================================================= */ + #define R_RTC_RYRAR_YR10_Pos (4UL) /*!< YR10 (Bit 4) */ + #define R_RTC_RYRAR_YR10_Msk (0xf0UL) /*!< YR10 (Bitfield-Mask: 0x0f) */ + #define R_RTC_RYRAR_YR1_Pos (0UL) /*!< YR1 (Bit 0) */ + #define R_RTC_RYRAR_YR1_Msk (0xfUL) /*!< YR1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= BCNT2AER ======================================================== */ + #define R_RTC_BCNT2AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT2AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ======================================================== RYRAREN ======================================================== */ + #define R_RTC_RYRAREN_ENB_Pos (7UL) /*!< ENB (Bit 7) */ + #define R_RTC_RYRAREN_ENB_Msk (0x80UL) /*!< ENB (Bitfield-Mask: 0x01) */ +/* ======================================================= BCNT3AER ======================================================== */ + #define R_RTC_BCNT3AER_ENB_Pos (0UL) /*!< ENB (Bit 0) */ + #define R_RTC_BCNT3AER_ENB_Msk (0xffUL) /*!< ENB (Bitfield-Mask: 0xff) */ +/* ========================================================= RCR1 ========================================================== */ + #define R_RTC_RCR1_PES_Pos (4UL) /*!< PES (Bit 4) */ + #define R_RTC_RCR1_PES_Msk (0xf0UL) /*!< PES (Bitfield-Mask: 0x0f) */ + #define R_RTC_RCR1_RTCOS_Pos (3UL) /*!< RTCOS (Bit 3) */ + #define R_RTC_RCR1_RTCOS_Msk (0x8UL) /*!< RTCOS (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_PIE_Pos (2UL) /*!< PIE (Bit 2) */ + #define R_RTC_RCR1_PIE_Msk (0x4UL) /*!< PIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_CIE_Pos (1UL) /*!< CIE (Bit 1) */ + #define R_RTC_RCR1_CIE_Msk (0x2UL) /*!< CIE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR1_AIE_Pos (0UL) /*!< AIE (Bit 0) */ + #define R_RTC_RCR1_AIE_Msk (0x1UL) /*!< AIE (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_CNTMD_Pos (7UL) /*!< CNTMD (Bit 7) */ + #define R_RTC_RCR2_CNTMD_Msk (0x80UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_HR24_Pos (6UL) /*!< HR24 (Bit 6) */ + #define R_RTC_RCR2_HR24_Msk (0x40UL) /*!< HR24 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJP_Pos (5UL) /*!< AADJP (Bit 5) */ + #define R_RTC_RCR2_AADJP_Msk (0x20UL) /*!< AADJP (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_AADJE_Pos (4UL) /*!< AADJE (Bit 4) */ + #define R_RTC_RCR2_AADJE_Msk (0x10UL) /*!< AADJE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RTCOE_Pos (3UL) /*!< RTCOE (Bit 3) */ + #define R_RTC_RCR2_RTCOE_Msk (0x8UL) /*!< RTCOE (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_ADJ30_Pos (2UL) /*!< ADJ30 (Bit 2) */ + #define R_RTC_RCR2_ADJ30_Msk (0x4UL) /*!< ADJ30 (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR2_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_RTC_RCR2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + #define R_RTC_RCR4_ROPSEL_Pos (7UL) /*!< ROPSEL (Bit 7) */ + #define R_RTC_RCR4_ROPSEL_Msk (0x80UL) /*!< ROPSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRH ========================================================== */ + #define R_RTC_RFRH_RFC16_Pos (0UL) /*!< RFC16 (Bit 0) */ + #define R_RTC_RFRH_RFC16_Msk (0x1UL) /*!< RFC16 (Bitfield-Mask: 0x01) */ +/* ========================================================= RFRL ========================================================== */ + #define R_RTC_RFRL_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_RTC_RFRL_RFC_Msk (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff) */ +/* ========================================================= RADJ ========================================================== */ + #define R_RTC_RADJ_PMADJ_Pos (6UL) /*!< PMADJ (Bit 6) */ + #define R_RTC_RADJ_PMADJ_Msk (0xc0UL) /*!< PMADJ (Bitfield-Mask: 0x03) */ + #define R_RTC_RADJ_ADJ_Pos (0UL) /*!< ADJ (Bit 0) */ + #define R_RTC_RADJ_ADJ_Msk (0x3fUL) /*!< ADJ (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SDHI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SD_CMD ========================================================= */ + #define R_SDHI0_SD_CMD_CMD12AT_Pos (14UL) /*!< CMD12AT (Bit 14) */ + #define R_SDHI0_SD_CMD_CMD12AT_Msk (0xc000UL) /*!< CMD12AT (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_TRSTP_Pos (13UL) /*!< TRSTP (Bit 13) */ + #define R_SDHI0_SD_CMD_TRSTP_Msk (0x2000UL) /*!< TRSTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDRW_Pos (12UL) /*!< CMDRW (Bit 12) */ + #define R_SDHI0_SD_CMD_CMDRW_Msk (0x1000UL) /*!< CMDRW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_CMDTP_Pos (11UL) /*!< CMDTP (Bit 11) */ + #define R_SDHI0_SD_CMD_CMDTP_Msk (0x800UL) /*!< CMDTP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CMD_RSPTP_Pos (8UL) /*!< RSPTP (Bit 8) */ + #define R_SDHI0_SD_CMD_RSPTP_Msk (0x700UL) /*!< RSPTP (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_CMD_ACMD_Pos (6UL) /*!< ACMD (Bit 6) */ + #define R_SDHI0_SD_CMD_ACMD_Msk (0xc0UL) /*!< ACMD (Bitfield-Mask: 0x03) */ + #define R_SDHI0_SD_CMD_CMDIDX_Pos (0UL) /*!< CMDIDX (Bit 0) */ + #define R_SDHI0_SD_CMD_CMDIDX_Msk (0x3fUL) /*!< CMDIDX (Bitfield-Mask: 0x3f) */ +/* ======================================================== SD_ARG ========================================================= */ + #define R_SDHI0_SD_ARG_SD_ARG_Pos (0UL) /*!< SD_ARG (Bit 0) */ + #define R_SDHI0_SD_ARG_SD_ARG_Msk (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_ARG1 ======================================================== */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Pos (0UL) /*!< SD_ARG1 (Bit 0) */ + #define R_SDHI0_SD_ARG1_SD_ARG1_Msk (0xffffUL) /*!< SD_ARG1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== SD_STOP ======================================================== */ + #define R_SDHI0_SD_STOP_SEC_Pos (8UL) /*!< SEC (Bit 8) */ + #define R_SDHI0_SD_STOP_SEC_Msk (0x100UL) /*!< SEC (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_STOP_STP_Pos (0UL) /*!< STP (Bit 0) */ + #define R_SDHI0_SD_STOP_STP_Msk (0x1UL) /*!< STP (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_SECCNT ======================================================= */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos (0UL) /*!< SD_SECCNT (Bit 0) */ + #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SD_RSP10 ======================================================== */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Pos (0UL) /*!< SD_RSP10 (Bit 0) */ + #define R_SDHI0_SD_RSP10_SD_RSP10_Msk (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP1 ======================================================== */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Pos (0UL) /*!< SD_RSP1 (Bit 0) */ + #define R_SDHI0_SD_RSP1_SD_RSP1_Msk (0xffffUL) /*!< SD_RSP1 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP32 ======================================================== */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Pos (0UL) /*!< SD_RSP32 (Bit 0) */ + #define R_SDHI0_SD_RSP32_SD_RSP32_Msk (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP3 ======================================================== */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Pos (0UL) /*!< SD_RSP3 (Bit 0) */ + #define R_SDHI0_SD_RSP3_SD_RSP3_Msk (0xffffUL) /*!< SD_RSP3 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP54 ======================================================== */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Pos (0UL) /*!< SD_RSP54 (Bit 0) */ + #define R_SDHI0_SD_RSP54_SD_RSP54_Msk (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SD_RSP5 ======================================================== */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Pos (0UL) /*!< SD_RSP5 (Bit 0) */ + #define R_SDHI0_SD_RSP5_SD_RSP5_Msk (0xffffUL) /*!< SD_RSP5 (Bitfield-Mask: 0xffff) */ +/* ======================================================= SD_RSP76 ======================================================== */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Pos (0UL) /*!< SD_RSP76 (Bit 0) */ + #define R_SDHI0_SD_RSP76_SD_RSP76_Msk (0xffffffUL) /*!< SD_RSP76 (Bitfield-Mask: 0xffffff) */ +/* ======================================================== SD_RSP7 ======================================================== */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Pos (0UL) /*!< SD_RSP7 (Bit 0) */ + #define R_SDHI0_SD_RSP7_SD_RSP7_Msk (0xffUL) /*!< SD_RSP7 (Bitfield-Mask: 0xff) */ +/* ======================================================= SD_INFO1 ======================================================== */ + #define R_SDHI0_SD_INFO1_SDD3MON_Pos (10UL) /*!< SDD3MON (Bit 10) */ + #define R_SDHI0_SD_INFO1_SDD3MON_Msk (0x400UL) /*!< SDD3MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Pos (9UL) /*!< SDD3IN (Bit 9) */ + #define R_SDHI0_SD_INFO1_SDD3IN_Msk (0x200UL) /*!< SDD3IN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Pos (8UL) /*!< SDD3RM (Bit 8) */ + #define R_SDHI0_SD_INFO1_SDD3RM_Msk (0x100UL) /*!< SDD3RM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Pos (7UL) /*!< SDWPMON (Bit 7) */ + #define R_SDHI0_SD_INFO1_SDWPMON_Msk (0x80UL) /*!< SDWPMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Pos (5UL) /*!< SDCDMON (Bit 5) */ + #define R_SDHI0_SD_INFO1_SDCDMON_Msk (0x20UL) /*!< SDCDMON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Pos (4UL) /*!< SDCDIN (Bit 4) */ + #define R_SDHI0_SD_INFO1_SDCDIN_Msk (0x10UL) /*!< SDCDIN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Pos (3UL) /*!< SDCDRM (Bit 3) */ + #define R_SDHI0_SD_INFO1_SDCDRM_Msk (0x8UL) /*!< SDCDRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_ACEND_Pos (2UL) /*!< ACEND (Bit 2) */ + #define R_SDHI0_SD_INFO1_ACEND_Msk (0x4UL) /*!< ACEND (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_RSPEND_Pos (0UL) /*!< RSPEND (Bit 0) */ + #define R_SDHI0_SD_INFO1_RSPEND_Msk (0x1UL) /*!< RSPEND (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_INFO2 ======================================================== */ + #define R_SDHI0_SD_INFO2_ILA_Pos (15UL) /*!< ILA (Bit 15) */ + #define R_SDHI0_SD_INFO2_ILA_Msk (0x8000UL) /*!< ILA (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CBSY_Pos (14UL) /*!< CBSY (Bit 14) */ + #define R_SDHI0_SD_INFO2_CBSY_Msk (0x4000UL) /*!< CBSY (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos (13UL) /*!< SD_CLK_CTRLEN (Bit 13) */ + #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk (0x2000UL) /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BWE_Pos (9UL) /*!< BWE (Bit 9) */ + #define R_SDHI0_SD_INFO2_BWE_Msk (0x200UL) /*!< BWE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_BRE_Pos (8UL) /*!< BRE (Bit 8) */ + #define R_SDHI0_SD_INFO2_BRE_Msk (0x100UL) /*!< BRE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Pos (7UL) /*!< SDD0MON (Bit 7) */ + #define R_SDHI0_SD_INFO2_SDD0MON_Msk (0x80UL) /*!< SDD0MON (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_RSPTO_Pos (6UL) /*!< RSPTO (Bit 6) */ + #define R_SDHI0_SD_INFO2_RSPTO_Msk (0x40UL) /*!< RSPTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILR_Pos (5UL) /*!< ILR (Bit 5) */ + #define R_SDHI0_SD_INFO2_ILR_Msk (0x20UL) /*!< ILR (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ILW_Pos (4UL) /*!< ILW (Bit 4) */ + #define R_SDHI0_SD_INFO2_ILW_Msk (0x10UL) /*!< ILW (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_DTO_Pos (3UL) /*!< DTO (Bit 3) */ + #define R_SDHI0_SD_INFO2_DTO_Msk (0x8UL) /*!< DTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_ENDE_Pos (2UL) /*!< ENDE (Bit 2) */ + #define R_SDHI0_SD_INFO2_ENDE_Msk (0x4UL) /*!< ENDE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CRCE_Pos (1UL) /*!< CRCE (Bit 1) */ + #define R_SDHI0_SD_INFO2_CRCE_Msk (0x2UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_CMDE_Pos (0UL) /*!< CMDE (Bit 0) */ + #define R_SDHI0_SD_INFO2_CMDE_Msk (0x1UL) /*!< CMDE (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO1_MASK ===================================================== */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos (9UL) /*!< SDD3INM (Bit 9) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk (0x200UL) /*!< SDD3INM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos (8UL) /*!< SDD3RMM (Bit 8) */ + #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk (0x100UL) /*!< SDD3RMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos (4UL) /*!< SDCDINM (Bit 4) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk (0x10UL) /*!< SDCDINM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos (3UL) /*!< SDCDRMM (Bit 3) */ + #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk (0x8UL) /*!< SDCDRMM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos (2UL) /*!< ACENDM (Bit 2) */ + #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk (0x4UL) /*!< ACENDM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos (0UL) /*!< RSPENDM (Bit 0) */ + #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk (0x1UL) /*!< RSPENDM (Bitfield-Mask: 0x01) */ +/* ===================================================== SD_INFO2_MASK ===================================================== */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos (15UL) /*!< ILAM (Bit 15) */ + #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk (0x8000UL) /*!< ILAM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos (9UL) /*!< BWEM (Bit 9) */ + #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk (0x200UL) /*!< BWEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Pos (8UL) /*!< BREM (Bit 8) */ + #define R_SDHI0_SD_INFO2_MASK_BREM_Msk (0x100UL) /*!< BREM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos (6UL) /*!< RSPTOM (Bit 6) */ + #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk (0x40UL) /*!< RSPTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos (5UL) /*!< ILRM (Bit 5) */ + #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk (0x20UL) /*!< ILRM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos (4UL) /*!< ILWM (Bit 4) */ + #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk (0x10UL) /*!< ILWM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos (3UL) /*!< DTOM (Bit 3) */ + #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk (0x8UL) /*!< DTOM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos (2UL) /*!< ENDEM (Bit 2) */ + #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk (0x4UL) /*!< ENDEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos (1UL) /*!< CRCEM (Bit 1) */ + #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk (0x2UL) /*!< CRCEM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos (0UL) /*!< CMDEM (Bit 0) */ + #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk (0x1UL) /*!< CMDEM (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_CLK_CTRL ====================================================== */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos (9UL) /*!< CLKCTRLEN (Bit 9) */ + #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk (0x200UL) /*!< CLKCTRLEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos (8UL) /*!< CLKEN (Bit 8) */ + #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk (0x100UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk (0xffUL) /*!< CLKSEL (Bitfield-Mask: 0xff) */ +/* ======================================================== SD_SIZE ======================================================== */ + #define R_SDHI0_SD_SIZE_LEN_Pos (0UL) /*!< LEN (Bit 0) */ + #define R_SDHI0_SD_SIZE_LEN_Msk (0x3ffUL) /*!< LEN (Bitfield-Mask: 0x3ff) */ +/* ======================================================= SD_OPTION ======================================================= */ + #define R_SDHI0_SD_OPTION_WIDTH_Pos (15UL) /*!< WIDTH (Bit 15) */ + #define R_SDHI0_SD_OPTION_WIDTH_Msk (0x8000UL) /*!< WIDTH (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Pos (13UL) /*!< WIDTH8 (Bit 13) */ + #define R_SDHI0_SD_OPTION_WIDTH8_Msk (0x2000UL) /*!< WIDTH8 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Pos (8UL) /*!< TOUTMASK (Bit 8) */ + #define R_SDHI0_SD_OPTION_TOUTMASK_Msk (0x100UL) /*!< TOUTMASK (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_OPTION_TOP_Pos (4UL) /*!< TOP (Bit 4) */ + #define R_SDHI0_SD_OPTION_TOP_Msk (0xf0UL) /*!< TOP (Bitfield-Mask: 0x0f) */ + #define R_SDHI0_SD_OPTION_CTOP_Pos (0UL) /*!< CTOP (Bit 0) */ + #define R_SDHI0_SD_OPTION_CTOP_Msk (0xfUL) /*!< CTOP (Bitfield-Mask: 0x0f) */ +/* ====================================================== SD_ERR_STS1 ====================================================== */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos (12UL) /*!< CRCTK (Bit 12) */ + #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk (0x7000UL) /*!< CRCTK (Bitfield-Mask: 0x07) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos (11UL) /*!< CRCTKE (Bit 11) */ + #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk (0x800UL) /*!< CRCTKE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos (10UL) /*!< RDCRCE (Bit 10) */ + #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk (0x400UL) /*!< RDCRCE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos (9UL) /*!< RSPCRCE1 (Bit 9) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk (0x200UL) /*!< RSPCRCE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos (8UL) /*!< RSPCRCE0 (Bit 8) */ + #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk (0x100UL) /*!< RSPCRCE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos (5UL) /*!< CRCLENE (Bit 5) */ + #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk (0x20UL) /*!< CRCLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos (4UL) /*!< RDLENE (Bit 4) */ + #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk (0x10UL) /*!< RDLENE (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos (3UL) /*!< RSPLENE1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk (0x8UL) /*!< RSPLENE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos (2UL) /*!< RSPLENE0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk (0x4UL) /*!< RSPLENE0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos (1UL) /*!< CMDE1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk (0x2UL) /*!< CMDE1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos (0UL) /*!< CMDE0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk (0x1UL) /*!< CMDE0 (Bitfield-Mask: 0x01) */ +/* ====================================================== SD_ERR_STS2 ====================================================== */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos (6UL) /*!< CRCBSYTO (Bit 6) */ + #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk (0x40UL) /*!< CRCBSYTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos (5UL) /*!< CRCTO (Bit 5) */ + #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk (0x20UL) /*!< CRCTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Pos (4UL) /*!< RDTO (Bit 4) */ + #define R_SDHI0_SD_ERR_STS2_RDTO_Msk (0x10UL) /*!< RDTO (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos (3UL) /*!< BSYTO1 (Bit 3) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk (0x8UL) /*!< BSYTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos (2UL) /*!< BSYTO0 (Bit 2) */ + #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk (0x4UL) /*!< BSYTO0 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos (1UL) /*!< RSPTO1 (Bit 1) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk (0x2UL) /*!< RSPTO1 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos (0UL) /*!< RSPTO0 (Bit 0) */ + #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk (0x1UL) /*!< RSPTO0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SD_BUF0 ======================================================== */ + #define R_SDHI0_SD_BUF0_SD_BUF_Pos (0UL) /*!< SD_BUF (Bit 0) */ + #define R_SDHI0_SD_BUF0_SD_BUF_Msk (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SDIO_MODE ======================================================= */ + #define R_SDHI0_SDIO_MODE_C52PUB_Pos (9UL) /*!< C52PUB (Bit 9) */ + #define R_SDHI0_SDIO_MODE_C52PUB_Msk (0x200UL) /*!< C52PUB (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_IOABT_Pos (8UL) /*!< IOABT (Bit 8) */ + #define R_SDHI0_SDIO_MODE_IOABT_Msk (0x100UL) /*!< IOABT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Pos (2UL) /*!< RWREQ (Bit 2) */ + #define R_SDHI0_SDIO_MODE_RWREQ_Msk (0x4UL) /*!< RWREQ (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_MODE_INTEN_Pos (0UL) /*!< INTEN (Bit 0) */ + #define R_SDHI0_SDIO_MODE_INTEN_Msk (0x1UL) /*!< INTEN (Bitfield-Mask: 0x01) */ +/* ====================================================== SDIO_INFO1 ======================================================= */ + #define R_SDHI0_SDIO_INFO1_EXWT_Pos (15UL) /*!< EXWT (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_EXWT_Msk (0x8000UL) /*!< EXWT (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos (14UL) /*!< EXPUB52 (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk (0x4000UL) /*!< EXPUB52 (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos (0UL) /*!< IOIRQ (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk (0x1UL) /*!< IOIRQ (Bitfield-Mask: 0x01) */ +/* ==================================================== SDIO_INFO1_MASK ==================================================== */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos (15UL) /*!< EXWTM (Bit 15) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk (0x8000UL) /*!< EXWTM (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos (14UL) /*!< EXPUB52M (Bit 14) */ + #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk (0x4000UL) /*!< EXPUB52M (Bitfield-Mask: 0x01) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos (0UL) /*!< IOIRQM (Bit 0) */ + #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk (0x1UL) /*!< IOIRQM (Bitfield-Mask: 0x01) */ +/* ======================================================= SD_DMAEN ======================================================== */ + #define R_SDHI0_SD_DMAEN_DMAEN_Pos (1UL) /*!< DMAEN (Bit 1) */ + #define R_SDHI0_SD_DMAEN_DMAEN_Msk (0x2UL) /*!< DMAEN (Bitfield-Mask: 0x01) */ +/* ======================================================= SOFT_RST ======================================================== */ + #define R_SDHI0_SOFT_RST_SDRST_Pos (0UL) /*!< SDRST (Bit 0) */ + #define R_SDHI0_SOFT_RST_SDRST_Msk (0x1UL) /*!< SDRST (Bitfield-Mask: 0x01) */ +/* ======================================================= SDIF_MODE ======================================================= */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos (8UL) /*!< NOCHKCR (Bit 8) */ + #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk (0x100UL) /*!< NOCHKCR (Bitfield-Mask: 0x01) */ +/* ======================================================= EXT_SWAP ======================================================== */ + #define R_SDHI0_EXT_SWAP_BRSWP_Pos (7UL) /*!< BRSWP (Bit 7) */ + #define R_SDHI0_EXT_SWAP_BRSWP_Msk (0x80UL) /*!< BRSWP (Bitfield-Mask: 0x01) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Pos (6UL) /*!< BWSWP (Bit 6) */ + #define R_SDHI0_EXT_SWAP_BWSWP_Msk (0x40UL) /*!< BWSWP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SSI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SSICR ========================================================= */ + #define R_SSI0_SSICR_CKS_Pos (30UL) /*!< CKS (Bit 30) */ + #define R_SSI0_SSICR_CKS_Msk (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TUIEN_Pos (29UL) /*!< TUIEN (Bit 29) */ + #define R_SSI0_SSICR_TUIEN_Msk (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TOIEN_Pos (28UL) /*!< TOIEN (Bit 28) */ + #define R_SSI0_SSICR_TOIEN_Msk (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_RUIEN_Pos (27UL) /*!< RUIEN (Bit 27) */ + #define R_SSI0_SSICR_RUIEN_Msk (0x8000000UL) /*!< RUIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_ROIEN_Pos (26UL) /*!< ROIEN (Bit 26) */ + #define R_SSI0_SSICR_ROIEN_Msk (0x4000000UL) /*!< ROIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_IIEN_Pos (25UL) /*!< IIEN (Bit 25) */ + #define R_SSI0_SSICR_IIEN_Msk (0x2000000UL) /*!< IIEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_FRM_Pos (22UL) /*!< FRM (Bit 22) */ + #define R_SSI0_SSICR_FRM_Msk (0xc00000UL) /*!< FRM (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSICR_DWL_Pos (19UL) /*!< DWL (Bit 19) */ + #define R_SSI0_SSICR_DWL_Msk (0x380000UL) /*!< DWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_SWL_Pos (16UL) /*!< SWL (Bit 16) */ + #define R_SSI0_SSICR_SWL_Msk (0x70000UL) /*!< SWL (Bitfield-Mask: 0x07) */ + #define R_SSI0_SSICR_MST_Pos (14UL) /*!< MST (Bit 14) */ + #define R_SSI0_SSICR_MST_Msk (0x4000UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_BCKP_Pos (13UL) /*!< BCKP (Bit 13) */ + #define R_SSI0_SSICR_BCKP_Msk (0x2000UL) /*!< BCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_LRCKP_Pos (12UL) /*!< LRCKP (Bit 12) */ + #define R_SSI0_SSICR_LRCKP_Msk (0x1000UL) /*!< LRCKP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SPDP_Pos (11UL) /*!< SPDP (Bit 11) */ + #define R_SSI0_SSICR_SPDP_Msk (0x800UL) /*!< SPDP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_SDTA_Pos (10UL) /*!< SDTA (Bit 10) */ + #define R_SSI0_SSICR_SDTA_Msk (0x400UL) /*!< SDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_PDTA_Pos (9UL) /*!< PDTA (Bit 9) */ + #define R_SSI0_SSICR_PDTA_Msk (0x200UL) /*!< PDTA (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_DEL_Pos (8UL) /*!< DEL (Bit 8) */ + #define R_SSI0_SSICR_DEL_Msk (0x100UL) /*!< DEL (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_CKDV_Pos (4UL) /*!< CKDV (Bit 4) */ + #define R_SSI0_SSICR_CKDV_Msk (0xf0UL) /*!< CKDV (Bitfield-Mask: 0x0f) */ + #define R_SSI0_SSICR_MUEN_Pos (3UL) /*!< MUEN (Bit 3) */ + #define R_SSI0_SSICR_MUEN_Msk (0x8UL) /*!< MUEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_TEN_Pos (1UL) /*!< TEN (Bit 1) */ + #define R_SSI0_SSICR_TEN_Msk (0x2UL) /*!< TEN (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSICR_REN_Pos (0UL) /*!< REN (Bit 0) */ + #define R_SSI0_SSICR_REN_Msk (0x1UL) /*!< REN (Bitfield-Mask: 0x01) */ +/* ========================================================= SSISR ========================================================= */ + #define R_SSI0_SSISR_TUIRQ_Pos (29UL) /*!< TUIRQ (Bit 29) */ + #define R_SSI0_SSISR_TUIRQ_Msk (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TOIRQ_Pos (28UL) /*!< TOIRQ (Bit 28) */ + #define R_SSI0_SSISR_TOIRQ_Msk (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RUIRQ_Pos (27UL) /*!< RUIRQ (Bit 27) */ + #define R_SSI0_SSISR_RUIRQ_Msk (0x8000000UL) /*!< RUIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_ROIRQ_Pos (26UL) /*!< ROIRQ (Bit 26) */ + #define R_SSI0_SSISR_ROIRQ_Msk (0x4000000UL) /*!< ROIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IIRQ_Pos (25UL) /*!< IIRQ (Bit 25) */ + #define R_SSI0_SSISR_IIRQ_Msk (0x2000000UL) /*!< IIRQ (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_TCHNO_Pos (5UL) /*!< TCHNO (Bit 5) */ + #define R_SSI0_SSISR_TCHNO_Msk (0x60UL) /*!< TCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_TSWNO_Pos (4UL) /*!< TSWNO (Bit 4) */ + #define R_SSI0_SSISR_TSWNO_Msk (0x10UL) /*!< TSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_RCHNO_Pos (2UL) /*!< RCHNO (Bit 2) */ + #define R_SSI0_SSISR_RCHNO_Msk (0xcUL) /*!< RCHNO (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSISR_RSWNO_Pos (1UL) /*!< RSWNO (Bit 1) */ + #define R_SSI0_SSISR_RSWNO_Msk (0x2UL) /*!< RSWNO (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSISR_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_SSI0_SSISR_IDST_Msk (0x1UL) /*!< IDST (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFCR ========================================================= */ + #define R_SSI0_SSIFCR_AUCKE_Pos (31UL) /*!< AUCKE (Bit 31) */ + #define R_SSI0_SSIFCR_AUCKE_Msk (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_SSIRST_Pos (16UL) /*!< SSIRST (Bit 16) */ + #define R_SSI0_SSIFCR_SSIRST_Msk (0x10000UL) /*!< SSIRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TTRG_Pos (6UL) /*!< TTRG (Bit 6) */ + #define R_SSI0_SSIFCR_TTRG_Msk (0xc0UL) /*!< TTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_RTRG_Pos (4UL) /*!< RTRG (Bit 4) */ + #define R_SSI0_SSIFCR_RTRG_Msk (0x30UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SSI0_SSIFCR_TIE_Pos (3UL) /*!< TIE (Bit 3) */ + #define R_SSI0_SSIFCR_TIE_Msk (0x8UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RIE_Pos (2UL) /*!< RIE (Bit 2) */ + #define R_SSI0_SSIFCR_RIE_Msk (0x4UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_TFRST_Pos (1UL) /*!< TFRST (Bit 1) */ + #define R_SSI0_SSIFCR_TFRST_Msk (0x2UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_RFRST_Pos (0UL) /*!< RFRST (Bit 0) */ + #define R_SSI0_SSIFCR_RFRST_Msk (0x1UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFCR_BSW_Pos (11UL) /*!< BSW (Bit 11) */ + #define R_SSI0_SSIFCR_BSW_Msk (0x800UL) /*!< BSW (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFSR ========================================================= */ + #define R_SSI0_SSIFSR_TDC_Pos (24UL) /*!< TDC (Bit 24) */ + #define R_SSI0_SSIFSR_TDC_Msk (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_TDE_Pos (16UL) /*!< TDE (Bit 16) */ + #define R_SSI0_SSIFSR_TDE_Msk (0x10000UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIFSR_RDC_Pos (8UL) /*!< RDC (Bit 8) */ + #define R_SSI0_SSIFSR_RDC_Msk (0x3f00UL) /*!< RDC (Bitfield-Mask: 0x3f) */ + #define R_SSI0_SSIFSR_RDF_Pos (0UL) /*!< RDF (Bit 0) */ + #define R_SSI0_SSIFSR_RDF_Msk (0x1UL) /*!< RDF (Bitfield-Mask: 0x01) */ +/* ======================================================== SSIFTDR ======================================================== */ + #define R_SSI0_SSIFTDR_SSIFTDR_Pos (0UL) /*!< SSIFTDR (Bit 0) */ + #define R_SSI0_SSIFTDR_SSIFTDR_Msk (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFTDR16 ======================================================= */ +/* ======================================================= SSIFTDR8 ======================================================== */ +/* ======================================================== SSIFRDR ======================================================== */ + #define R_SSI0_SSIFRDR_SSIFRDR_Pos (0UL) /*!< SSIFRDR (Bit 0) */ + #define R_SSI0_SSIFRDR_SSIFRDR_Msk (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SSIFRDR16 ======================================================= */ +/* ======================================================= SSIFRDR8 ======================================================== */ +/* ======================================================== SSIOFR ========================================================= */ + #define R_SSI0_SSIOFR_BCKASTP_Pos (9UL) /*!< BCKASTP (Bit 9) */ + #define R_SSI0_SSIOFR_BCKASTP_Msk (0x200UL) /*!< BCKASTP (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_LRCONT_Pos (8UL) /*!< LRCONT (Bit 8) */ + #define R_SSI0_SSIOFR_LRCONT_Msk (0x100UL) /*!< LRCONT (Bitfield-Mask: 0x01) */ + #define R_SSI0_SSIOFR_OMOD_Pos (0UL) /*!< OMOD (Bit 0) */ + #define R_SSI0_SSIOFR_OMOD_Msk (0x3UL) /*!< OMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== SSISCR ========================================================= */ + #define R_SSI0_SSISCR_TDES_Pos (8UL) /*!< TDES (Bit 8) */ + #define R_SSI0_SSISCR_TDES_Msk (0x1f00UL) /*!< TDES (Bitfield-Mask: 0x1f) */ + #define R_SSI0_SSISCR_RDFS_Pos (0UL) /*!< RDFS (Bit 0) */ + #define R_SSI0_SSISCR_RDFS_Msk (0x1fUL) /*!< RDFS (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_FS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_FS0_SYSCFG_SCKE_Pos (10UL) /*!< SCKE (Bit 10) */ + #define R_USB_FS0_SYSCFG_SCKE_Msk (0x400UL) /*!< SCKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_FS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_FS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_FS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_FS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_DMRPU_Pos (3UL) /*!< DMRPU (Bit 3) */ + #define R_USB_FS0_SYSCFG_DMRPU_Msk (0x8UL) /*!< DMRPU (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_FS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_FS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_FS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_FS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_FS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_FS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_FS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_FS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_FS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_FS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_FS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_FS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_FS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_FS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_FS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_FS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_FS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_FS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_FS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ========================================================= CFIFO ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_FS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_FS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_FS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_FS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_FS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_FS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_FS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_FS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_FS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_FS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_FS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_FS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_FS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_FS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_FS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_FS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_FS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_FS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_FS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_FS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_FS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_FS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_FS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_FS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_FS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_FS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_FS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_FS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_FS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk (0x1UL) /*!< PIPEBRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk (0x1UL) /*!< PIPENRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk (0x1UL) /*!< PIPEBEMPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_FS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_FS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_FS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_FS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_FS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_FS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_FS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_FS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_FS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_FS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_FS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_FS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_FS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_FS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_FS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_FS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_FS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_FS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_FS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_FS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_FS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_FS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_FS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_FS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_FS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_FS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_FS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_FS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_FS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_FS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_FS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_FS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_FS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_FS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_FS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk (0x1UL) /*!< PIPEBRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk (0x1UL) /*!< PIPENRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk (0x1UL) /*!< PIPEBEMP (Bitfield-Mask: 0x01) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_FS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_FS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_FS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_FS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_FS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_FS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_FS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_FS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_FS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USB_FS0_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_FS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_FS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_FS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_FS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_FS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_FS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_FS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_FS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_FS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_FS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_FS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_FS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_FS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_FS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USB_FS0_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USB_FS0_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_FS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_FS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_FS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_FS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_FS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_FS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_FS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_FS0_PIPEMAXP_MXPS_Msk (0x1ffUL) /*!< MXPS (Bitfield-Mask: 0x1ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_FS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_FS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_FS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_FS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_FS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_FS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_FS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_FS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_FS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_FS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_FS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_FS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_FS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_FS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_FS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_FS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_FS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_FS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_FS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_FS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ====================================================== USBBCCTRL0 ======================================================= */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos (9UL) /*!< PDDETSTS0 (Bit 9) */ + #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /*!< PDDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /*!< CHGDETSTS0 (Bit 8) */ + #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /*!< CHGDETSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos (7UL) /*!< BATCHGE0 (Bit 7) */ + #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk (0x80UL) /*!< BATCHGE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos (5UL) /*!< VDMSRCE0 (Bit 5) */ + #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk (0x20UL) /*!< VDMSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos (4UL) /*!< IDPSINKE0 (Bit 4) */ + #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk (0x10UL) /*!< IDPSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos (3UL) /*!< VDPSRCE0 (Bit 3) */ + #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk (0x8UL) /*!< VDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos (2UL) /*!< IDMSINKE0 (Bit 2) */ + #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk (0x4UL) /*!< IDMSINKE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos (1UL) /*!< IDPSRCE0 (Bit 1) */ + #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /*!< IDPSRCE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos (0UL) /*!< RPDME0 (Bit 0) */ + #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk (0x1UL) /*!< RPDME0 (Bitfield-Mask: 0x01) */ +/* ======================================================== UCKSEL ========================================================= */ + #define R_USB_FS0_UCKSEL_UCKSELC_Pos (0UL) /*!< UCKSELC (Bit 0) */ + #define R_USB_FS0_UCKSEL_UCKSELC_Msk (0x1UL) /*!< UCKSELC (Bitfield-Mask: 0x01) */ +/* ========================================================= USBMC ========================================================= */ + #define R_USB_FS0_USBMC_VDCEN_Pos (7UL) /*!< VDCEN (Bit 7) */ + #define R_USB_FS0_USBMC_VDCEN_Msk (0x80UL) /*!< VDCEN (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_USBMC_VDDUSBE_Pos (0UL) /*!< VDDUSBE (Bit 0) */ + #define R_USB_FS0_USBMC_VDDUSBE_Msk (0x1UL) /*!< VDDUSBE (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSLEW ======================================================== */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Pos (3UL) /*!< SLEWF01 (Bit 3) */ + #define R_USB_FS0_PHYSLEW_SLEWF01_Msk (0x8UL) /*!< SLEWF01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Pos (2UL) /*!< SLEWF00 (Bit 2) */ + #define R_USB_FS0_PHYSLEW_SLEWF00_Msk (0x4UL) /*!< SLEWF00 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Pos (1UL) /*!< SLEWR01 (Bit 1) */ + #define R_USB_FS0_PHYSLEW_SLEWR01_Msk (0x2UL) /*!< SLEWR01 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Pos (0UL) /*!< SLEWR00 (Bit 0) */ + #define R_USB_FS0_PHYSLEW_SLEWR00_Msk (0x1UL) /*!< SLEWR00 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_FS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_FS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_FS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_FS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_FS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_FS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_FS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_FS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_FS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_FS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_FS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_FS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_FS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_FS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_FS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_FS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_FS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_FS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_FS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_FS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_FS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_FS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_FS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_FS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_FS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_FS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_FS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_FS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR0R_FS ======================================================= */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos (23UL) /*!< DVBSTS0 (Bit 23) */ + #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos (21UL) /*!< DOVCB0 (Bit 21) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos (20UL) /*!< DOVCA0 (Bit 20) */ + #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Pos (17UL) /*!< DM0 (Bit 17) */ + #define R_USB_FS0_DPUSR0R_FS_DM0_Msk (0x20000UL) /*!< DM0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Pos (16UL) /*!< DP0 (Bit 16) */ + #define R_USB_FS0_DPUSR0R_FS_DP0_Msk (0x10000UL) /*!< DP0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos (4UL) /*!< FIXPHY0 (Bit 4) */ + #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk (0x10UL) /*!< FIXPHY0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos (3UL) /*!< DRPD0 (Bit 3) */ + #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk (0x8UL) /*!< DRPD0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos (1UL) /*!< RPUE0 (Bit 1) */ + #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk (0x2UL) /*!< RPUE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos (0UL) /*!< SRPC0 (Bit 0) */ + #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk (0x1UL) /*!< SRPC0 (Bitfield-Mask: 0x01) */ +/* ====================================================== DPUSR1R_FS ======================================================= */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos (23UL) /*!< DVBINT0 (Bit 23) */ + #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /*!< DOVRCRB0 (Bit 21) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos (20UL) /*!< DOVRCRA0 (Bit 20) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos (17UL) /*!< DMINT0 (Bit 17) */ + #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk (0x20000UL) /*!< DMINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos (16UL) /*!< DPINT0 (Bit 16) */ + #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk (0x10000UL) /*!< DPINT0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos (7UL) /*!< DVBSE0 (Bit 7) */ + #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk (0x80UL) /*!< DVBSE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos (5UL) /*!< DOVRCRBE0 (Bit 5) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL) /*!< DOVRCRBE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos (4UL) /*!< DOVRCRAE0 (Bit 4) */ + #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL) /*!< DOVRCRAE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos (1UL) /*!< DMINTE0 (Bit 1) */ + #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk (0x2UL) /*!< DMINTE0 (Bitfield-Mask: 0x01) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos (0UL) /*!< DPINTE0 (Bit 0) */ + #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk (0x1UL) /*!< DPINTE0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CEC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CADR ========================================================== */ + #define R_CEC_CADR_ADR00_Pos (0UL) /*!< ADR00 (Bit 0) */ + #define R_CEC_CADR_ADR00_Msk (0x1UL) /*!< ADR00 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR01_Pos (1UL) /*!< ADR01 (Bit 1) */ + #define R_CEC_CADR_ADR01_Msk (0x2UL) /*!< ADR01 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR02_Pos (2UL) /*!< ADR02 (Bit 2) */ + #define R_CEC_CADR_ADR02_Msk (0x4UL) /*!< ADR02 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR03_Pos (3UL) /*!< ADR03 (Bit 3) */ + #define R_CEC_CADR_ADR03_Msk (0x8UL) /*!< ADR03 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR04_Pos (4UL) /*!< ADR04 (Bit 4) */ + #define R_CEC_CADR_ADR04_Msk (0x10UL) /*!< ADR04 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR05_Pos (5UL) /*!< ADR05 (Bit 5) */ + #define R_CEC_CADR_ADR05_Msk (0x20UL) /*!< ADR05 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR06_Pos (6UL) /*!< ADR06 (Bit 6) */ + #define R_CEC_CADR_ADR06_Msk (0x40UL) /*!< ADR06 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR07_Pos (7UL) /*!< ADR07 (Bit 7) */ + #define R_CEC_CADR_ADR07_Msk (0x80UL) /*!< ADR07 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR08_Pos (8UL) /*!< ADR08 (Bit 8) */ + #define R_CEC_CADR_ADR08_Msk (0x100UL) /*!< ADR08 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR09_Pos (9UL) /*!< ADR09 (Bit 9) */ + #define R_CEC_CADR_ADR09_Msk (0x200UL) /*!< ADR09 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR10_Pos (10UL) /*!< ADR10 (Bit 10) */ + #define R_CEC_CADR_ADR10_Msk (0x400UL) /*!< ADR10 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR11_Pos (11UL) /*!< ADR11 (Bit 11) */ + #define R_CEC_CADR_ADR11_Msk (0x800UL) /*!< ADR11 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR12_Pos (12UL) /*!< ADR12 (Bit 12) */ + #define R_CEC_CADR_ADR12_Msk (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR13_Pos (13UL) /*!< ADR13 (Bit 13) */ + #define R_CEC_CADR_ADR13_Msk (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01) */ + #define R_CEC_CADR_ADR14_Pos (14UL) /*!< ADR14 (Bit 14) */ + #define R_CEC_CADR_ADR14_Msk (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCTL1 ======================================================== */ + #define R_CEC_CECCTL1_SFT_Pos (0UL) /*!< SFT (Bit 0) */ + #define R_CEC_CECCTL1_SFT_Msk (0x3UL) /*!< SFT (Bitfield-Mask: 0x03) */ + #define R_CEC_CECCTL1_CESEL_Pos (2UL) /*!< CESEL (Bit 2) */ + #define R_CEC_CECCTL1_CESEL_Msk (0xcUL) /*!< CESEL (Bitfield-Mask: 0x03) */ + #define R_CEC_CECCTL1_STERRD_Pos (4UL) /*!< STERRD (Bit 4) */ + #define R_CEC_CECCTL1_STERRD_Msk (0x10UL) /*!< STERRD (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_BLERRD_Pos (5UL) /*!< BLERRD (Bit 5) */ + #define R_CEC_CECCTL1_BLERRD_Msk (0x20UL) /*!< BLERRD (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_CINTMK_Pos (6UL) /*!< CINTMK (Bit 6) */ + #define R_CEC_CECCTL1_CINTMK_Msk (0x40UL) /*!< CINTMK (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL1_CDFC_Pos (7UL) /*!< CDFC (Bit 7) */ + #define R_CEC_CECCTL1_CDFC_Msk (0x80UL) /*!< CDFC (Bitfield-Mask: 0x01) */ +/* ========================================================= STATB ========================================================= */ + #define R_CEC_STATB_STATB_Pos (0UL) /*!< STATB (Bit 0) */ + #define R_CEC_STATB_STATB_Msk (0x1ffUL) /*!< STATB (Bitfield-Mask: 0x1ff) */ +/* ========================================================= STATL ========================================================= */ + #define R_CEC_STATL_STATL_Pos (0UL) /*!< STATL (Bit 0) */ + #define R_CEC_STATL_STATL_Msk (0x1ffUL) /*!< STATL (Bitfield-Mask: 0x1ff) */ +/* ========================================================= LGC0L ========================================================= */ + #define R_CEC_LGC0L_LGC0L_Pos (0UL) /*!< LGC0L (Bit 0) */ + #define R_CEC_LGC0L_LGC0L_Msk (0x1ffUL) /*!< LGC0L (Bitfield-Mask: 0x1ff) */ +/* ========================================================= LGC1L ========================================================= */ + #define R_CEC_LGC1L_LGC1L_Pos (0UL) /*!< LGC1L (Bit 0) */ + #define R_CEC_LGC1L_LGC1L_Msk (0x1ffUL) /*!< LGC1L (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATB ========================================================== */ + #define R_CEC_DATB_DATB_Pos (0UL) /*!< DATB (Bit 0) */ + #define R_CEC_DATB_DATB_Msk (0x1ffUL) /*!< DATB (Bitfield-Mask: 0x1ff) */ +/* ========================================================= NOMT ========================================================== */ + #define R_CEC_NOMT_NOMT_Pos (0UL) /*!< NOMT (Bit 0) */ + #define R_CEC_NOMT_NOMT_Msk (0x1ffUL) /*!< NOMT (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATLL ========================================================= */ + #define R_CEC_STATLL_STATLL_Pos (0UL) /*!< STATLL (Bit 0) */ + #define R_CEC_STATLL_STATLL_Msk (0x1ffUL) /*!< STATLL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATLH ========================================================= */ + #define R_CEC_STATLH_STATLH_Pos (0UL) /*!< STATLH (Bit 0) */ + #define R_CEC_STATLH_STATLH_Msk (0x1ffUL) /*!< STATLH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATBL ========================================================= */ + #define R_CEC_STATBL_STATBL_Pos (0UL) /*!< STATBL (Bit 0) */ + #define R_CEC_STATBL_STATBL_Msk (0x1ffUL) /*!< STATBL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== STATBH ========================================================= */ + #define R_CEC_STATBH_STATBH_Pos (0UL) /*!< STATBH (Bit 0) */ + #define R_CEC_STATBH_STATBH_Msk (0x1ffUL) /*!< STATBH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC0LL ========================================================= */ + #define R_CEC_LGC0LL_LGC0LL_Pos (0UL) /*!< LGC0LL (Bit 0) */ + #define R_CEC_LGC0LL_LGC0LL_Msk (0x1ffUL) /*!< LGC0LL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC0LH ========================================================= */ + #define R_CEC_LGC0LH_LGC0LH_Pos (0UL) /*!< LGC0LH (Bit 0) */ + #define R_CEC_LGC0LH_LGC0LH_Msk (0x1ffUL) /*!< LGC0LH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC1LL ========================================================= */ + #define R_CEC_LGC1LL_LGC1LL_Pos (0UL) /*!< LGC1LL (Bit 0) */ + #define R_CEC_LGC1LL_LGC1LL_Msk (0x1ffUL) /*!< LGC1LL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== LGC1LH ========================================================= */ + #define R_CEC_LGC1LH_LGC1LH_Pos (0UL) /*!< LGC1LH (Bit 0) */ + #define R_CEC_LGC1LH_LGC1LH_Msk (0x1ffUL) /*!< LGC1LH (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATBL ========================================================= */ + #define R_CEC_DATBL_DATBL_Pos (0UL) /*!< DATBL (Bit 0) */ + #define R_CEC_DATBL_DATBL_Msk (0x1ffUL) /*!< DATBL (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DATBH ========================================================= */ + #define R_CEC_DATBH_DATBH_Pos (0UL) /*!< DATBH (Bit 0) */ + #define R_CEC_DATBH_DATBH_Msk (0x1ffUL) /*!< DATBH (Bitfield-Mask: 0x1ff) */ +/* ========================================================= NOMP ========================================================== */ + #define R_CEC_NOMP_NOMP_Pos (0UL) /*!< NOMP (Bit 0) */ + #define R_CEC_NOMP_NOMP_Msk (0x1ffUL) /*!< NOMP (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CECEXMD ======================================================== */ + #define R_CEC_CECEXMD_LERPLEN_Pos (4UL) /*!< LERPLEN (Bit 4) */ + #define R_CEC_CECEXMD_LERPLEN_Msk (0x10UL) /*!< LERPLEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMD_RERCVEN_Pos (5UL) /*!< RERCVEN (Bit 5) */ + #define R_CEC_CECEXMD_RERCVEN_Msk (0x20UL) /*!< RERCVEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMD_RCVINTDSEL_Pos (7UL) /*!< RCVINTDSEL (Bit 7) */ + #define R_CEC_CECEXMD_RCVINTDSEL_Msk (0x80UL) /*!< RCVINTDSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= CECEXMON ======================================================== */ + #define R_CEC_CECEXMON_CECLNMON_Pos (0UL) /*!< CECLNMON (Bit 0) */ + #define R_CEC_CECEXMON_CECLNMON_Msk (0x1UL) /*!< CECLNMON (Bitfield-Mask: 0x01) */ + #define R_CEC_CECEXMON_ACKF_Pos (1UL) /*!< ACKF (Bit 1) */ + #define R_CEC_CECEXMON_ACKF_Msk (0x2UL) /*!< ACKF (Bitfield-Mask: 0x01) */ +/* ========================================================= CTXD ========================================================== */ +/* ========================================================= CRXD ========================================================== */ +/* ========================================================= CECES ========================================================= */ + #define R_CEC_CECES_OERR_Pos (0UL) /*!< OERR (Bit 0) */ + #define R_CEC_CECES_OERR_Msk (0x1UL) /*!< OERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_UERR_Pos (1UL) /*!< UERR (Bit 1) */ + #define R_CEC_CECES_UERR_Msk (0x2UL) /*!< UERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_ACKERR_Pos (2UL) /*!< ACKERR (Bit 2) */ + #define R_CEC_CECES_ACKERR_Msk (0x4UL) /*!< ACKERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_TERR_Pos (3UL) /*!< TERR (Bit 3) */ + #define R_CEC_CECES_TERR_Msk (0x8UL) /*!< TERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_TXERR_Pos (4UL) /*!< TXERR (Bit 4) */ + #define R_CEC_CECES_TXERR_Msk (0x10UL) /*!< TXERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_AERR_Pos (5UL) /*!< AERR (Bit 5) */ + #define R_CEC_CECES_AERR_Msk (0x20UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CEC_CECES_BLERR_Pos (6UL) /*!< BLERR (Bit 6) */ + #define R_CEC_CECES_BLERR_Msk (0x40UL) /*!< BLERR (Bitfield-Mask: 0x01) */ +/* ========================================================= CECS ========================================================== */ + #define R_CEC_CECS_ADRF_Pos (0UL) /*!< ADRF (Bit 0) */ + #define R_CEC_CECS_ADRF_Msk (0x1UL) /*!< ADRF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_BUSST_Pos (1UL) /*!< BUSST (Bit 1) */ + #define R_CEC_CECS_BUSST_Msk (0x2UL) /*!< BUSST (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_TXST_Pos (2UL) /*!< TXST (Bit 2) */ + #define R_CEC_CECS_TXST_Msk (0x4UL) /*!< TXST (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_EOMF_Pos (3UL) /*!< EOMF (Bit 3) */ + #define R_CEC_CECS_EOMF_Msk (0x8UL) /*!< EOMF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_ITCEF_Pos (4UL) /*!< ITCEF (Bit 4) */ + #define R_CEC_CECS_ITCEF_Msk (0x10UL) /*!< ITCEF (Bitfield-Mask: 0x01) */ + #define R_CEC_CECS_SFTST_Pos (7UL) /*!< SFTST (Bit 7) */ + #define R_CEC_CECS_SFTST_Msk (0x80UL) /*!< SFTST (Bitfield-Mask: 0x01) */ +/* ========================================================= CECFC ========================================================= */ + #define R_CEC_CECFC_OCTRG_Pos (0UL) /*!< OCTRG (Bit 0) */ + #define R_CEC_CECFC_OCTRG_Msk (0x1UL) /*!< OCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_UCTRG_Pos (1UL) /*!< UCTRG (Bit 1) */ + #define R_CEC_CECFC_UCTRG_Msk (0x2UL) /*!< UCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_ACKCTRG_Pos (2UL) /*!< ACKCTRG (Bit 2) */ + #define R_CEC_CECFC_ACKCTRG_Msk (0x4UL) /*!< ACKCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_TCTRG_Pos (3UL) /*!< TCTRG (Bit 3) */ + #define R_CEC_CECFC_TCTRG_Msk (0x8UL) /*!< TCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_TXCTRG_Pos (4UL) /*!< TXCTRG (Bit 4) */ + #define R_CEC_CECFC_TXCTRG_Msk (0x10UL) /*!< TXCTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_ACTRG_Pos (5UL) /*!< ACTRG (Bit 5) */ + #define R_CEC_CECFC_ACTRG_Msk (0x20UL) /*!< ACTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECFC_BLCTRG_Pos (6UL) /*!< BLCTRG (Bit 6) */ + #define R_CEC_CECFC_BLCTRG_Msk (0x40UL) /*!< BLCTRG (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCTL0 ======================================================== */ + #define R_CEC_CECCTL0_EOM_Pos (0UL) /*!< EOM (Bit 0) */ + #define R_CEC_CECCTL0_EOM_Msk (0x1UL) /*!< EOM (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CECRXEN_Pos (1UL) /*!< CECRXEN (Bit 1) */ + #define R_CEC_CECCTL0_CECRXEN_Msk (0x2UL) /*!< CECRXEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_TXTRG_Pos (2UL) /*!< TXTRG (Bit 2) */ + #define R_CEC_CECCTL0_TXTRG_Msk (0x4UL) /*!< TXTRG (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CCL_Pos (3UL) /*!< CCL (Bit 3) */ + #define R_CEC_CECCTL0_CCL_Msk (0x38UL) /*!< CCL (Bitfield-Mask: 0x07) */ + #define R_CEC_CECCTL0_ACKTEN_Pos (6UL) /*!< ACKTEN (Bit 6) */ + #define R_CEC_CECCTL0_ACKTEN_Msk (0x40UL) /*!< ACKTEN (Bitfield-Mask: 0x01) */ + #define R_CEC_CECCTL0_CECE_Pos (7UL) /*!< CECE (Bit 7) */ + #define R_CEC_CECCTL0_CECE_Msk (0x80UL) /*!< CECE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_OSPI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== DCR ========================================================== */ + #define R_OSPI_DCR_DVCMD0_Pos (0UL) /*!< DVCMD0 (Bit 0) */ + #define R_OSPI_DCR_DVCMD0_Msk (0xffUL) /*!< DVCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCR_DVCMD1_Pos (8UL) /*!< DVCMD1 (Bit 8) */ + #define R_OSPI_DCR_DVCMD1_Msk (0xff00UL) /*!< DVCMD1 (Bitfield-Mask: 0xff) */ +/* ========================================================== DAR ========================================================== */ + #define R_OSPI_DAR_DVAD0_Pos (0UL) /*!< DVAD0 (Bit 0) */ + #define R_OSPI_DAR_DVAD0_Msk (0xffUL) /*!< DVAD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD1_Pos (8UL) /*!< DVAD1 (Bit 8) */ + #define R_OSPI_DAR_DVAD1_Msk (0xff00UL) /*!< DVAD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD2_Pos (16UL) /*!< DVAD2 (Bit 16) */ + #define R_OSPI_DAR_DVAD2_Msk (0xff0000UL) /*!< DVAD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_DAR_DVAD3_Pos (24UL) /*!< DVAD3 (Bit 24) */ + #define R_OSPI_DAR_DVAD3_Msk (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= DCSR ========================================================== */ + #define R_OSPI_DCSR_DALEN_Pos (0UL) /*!< DALEN (Bit 0) */ + #define R_OSPI_DCSR_DALEN_Msk (0xffUL) /*!< DALEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_DMLEN_Pos (8UL) /*!< DMLEN (Bit 8) */ + #define R_OSPI_DCSR_DMLEN_Msk (0xff00UL) /*!< DMLEN (Bitfield-Mask: 0xff) */ + #define R_OSPI_DCSR_ACDV_Pos (19UL) /*!< ACDV (Bit 19) */ + #define R_OSPI_DCSR_ACDV_Msk (0x80000UL) /*!< ACDV (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_CMDLEN_Pos (20UL) /*!< CMDLEN (Bit 20) */ + #define R_OSPI_DCSR_CMDLEN_Msk (0x700000UL) /*!< CMDLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DAOR_Pos (23UL) /*!< DAOR (Bit 23) */ + #define R_OSPI_DCSR_DAOR_Msk (0x800000UL) /*!< DAOR (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ADLEN_Pos (24UL) /*!< ADLEN (Bit 24) */ + #define R_OSPI_DCSR_ADLEN_Msk (0x7000000UL) /*!< ADLEN (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSR_DOPI_Pos (27UL) /*!< DOPI (Bit 27) */ + #define R_OSPI_DCSR_DOPI_Msk (0x8000000UL) /*!< DOPI (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_ACDA_Pos (28UL) /*!< ACDA (Bit 28) */ + #define R_OSPI_DCSR_ACDA_Msk (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01) */ + #define R_OSPI_DCSR_PREN_Pos (29UL) /*!< PREN (Bit 29) */ + #define R_OSPI_DCSR_PREN_Msk (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DSR ========================================================== */ + #define R_OSPI_DSR_DVSZ_Pos (0UL) /*!< DVSZ (Bit 0) */ + #define R_OSPI_DSR_DVSZ_Msk (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff) */ + #define R_OSPI_DSR_DVTYP_Pos (30UL) /*!< DVTYP (Bit 30) */ + #define R_OSPI_DSR_DVTYP_Msk (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03) */ +/* ========================================================= MDTR ========================================================== */ + #define R_OSPI_MDTR_DV0DEL_Pos (0UL) /*!< DV0DEL (Bit 0) */ + #define R_OSPI_MDTR_DV0DEL_Msk (0xffUL) /*!< DV0DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSERAM_Pos (8UL) /*!< DQSERAM (Bit 8) */ + #define R_OSPI_MDTR_DQSERAM_Msk (0xf00UL) /*!< DQSERAM (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DQSESOPI_Pos (12UL) /*!< DQSESOPI (Bit 12) */ + #define R_OSPI_MDTR_DQSESOPI_Msk (0xf000UL) /*!< DQSESOPI (Bitfield-Mask: 0x0f) */ + #define R_OSPI_MDTR_DV1DEL_Pos (16UL) /*!< DV1DEL (Bit 16) */ + #define R_OSPI_MDTR_DV1DEL_Msk (0xff0000UL) /*!< DV1DEL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDTR_DQSEDOPI_Pos (24UL) /*!< DQSEDOPI (Bit 24) */ + #define R_OSPI_MDTR_DQSEDOPI_Msk (0xf000000UL) /*!< DQSEDOPI (Bitfield-Mask: 0x0f) */ +/* ========================================================= ACTR ========================================================== */ + #define R_OSPI_ACTR_CTP_Pos (0UL) /*!< CTP (Bit 0) */ + #define R_OSPI_ACTR_CTP_Msk (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ACAR ========================================================== */ + #define R_OSPI_ACAR_CAD_Pos (0UL) /*!< CAD (Bit 0) */ + #define R_OSPI_ACAR_CAD_Msk (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== DRCSTR ========================================================= */ + #define R_OSPI_DRCSTR_CTRW0_Pos (0UL) /*!< CTRW0 (Bit 0) */ + #define R_OSPI_DRCSTR_CTRW0_Msk (0x7fUL) /*!< CTRW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR0_Pos (7UL) /*!< CTR0 (Bit 7) */ + #define R_OSPI_DRCSTR_CTR0_Msk (0x80UL) /*!< CTR0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Pos (8UL) /*!< DVRDCMD0 (Bit 8) */ + #define R_OSPI_DRCSTR_DVRDCMD0_Msk (0x700UL) /*!< DVRDCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI0_Pos (11UL) /*!< DVRDHI0 (Bit 11) */ + #define R_OSPI_DRCSTR_DVRDHI0_Msk (0x3800UL) /*!< DVRDHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO0_Pos (14UL) /*!< DVRDLO0 (Bit 14) */ + #define R_OSPI_DRCSTR_DVRDLO0_Msk (0xc000UL) /*!< DVRDLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DRCSTR_CTRW1_Pos (16UL) /*!< CTRW1 (Bit 16) */ + #define R_OSPI_DRCSTR_CTRW1_Msk (0x7f0000UL) /*!< CTRW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DRCSTR_CTR1_Pos (23UL) /*!< CTR1 (Bit 23) */ + #define R_OSPI_DRCSTR_CTR1_Msk (0x800000UL) /*!< CTR1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Pos (24UL) /*!< DVRDCMD1 (Bit 24) */ + #define R_OSPI_DRCSTR_DVRDCMD1_Msk (0x7000000UL) /*!< DVRDCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDHI1_Pos (27UL) /*!< DVRDHI1 (Bit 27) */ + #define R_OSPI_DRCSTR_DVRDHI1_Msk (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DRCSTR_DVRDLO1_Pos (30UL) /*!< DVRDLO1 (Bit 30) */ + #define R_OSPI_DRCSTR_DVRDLO1_Msk (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03) */ +/* ======================================================== DWCSTR ========================================================= */ + #define R_OSPI_DWCSTR_CTWW0_Pos (0UL) /*!< CTWW0 (Bit 0) */ + #define R_OSPI_DWCSTR_CTWW0_Msk (0x7fUL) /*!< CTWW0 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW0_Pos (7UL) /*!< CTW0 (Bit 7) */ + #define R_OSPI_DWCSTR_CTW0_Msk (0x80UL) /*!< CTW0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD0_Pos (8UL) /*!< DVWCMD0 (Bit 8) */ + #define R_OSPI_DWCSTR_DVWCMD0_Msk (0x700UL) /*!< DVWCMD0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI0_Pos (11UL) /*!< DVWHI0 (Bit 11) */ + #define R_OSPI_DWCSTR_DVWHI0_Msk (0x3800UL) /*!< DVWHI0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO0_Pos (14UL) /*!< DVWLO0 (Bit 14) */ + #define R_OSPI_DWCSTR_DVWLO0_Msk (0xc000UL) /*!< DVWLO0 (Bitfield-Mask: 0x03) */ + #define R_OSPI_DWCSTR_CTWW1_Pos (16UL) /*!< CTWW1 (Bit 16) */ + #define R_OSPI_DWCSTR_CTWW1_Msk (0x7f0000UL) /*!< CTWW1 (Bitfield-Mask: 0x7f) */ + #define R_OSPI_DWCSTR_CTW1_Pos (23UL) /*!< CTW1 (Bit 23) */ + #define R_OSPI_DWCSTR_CTW1_Msk (0x800000UL) /*!< CTW1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_DWCSTR_DVWCMD1_Pos (24UL) /*!< DVWCMD1 (Bit 24) */ + #define R_OSPI_DWCSTR_DVWCMD1_Msk (0x7000000UL) /*!< DVWCMD1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWHI1_Pos (27UL) /*!< DVWHI1 (Bit 27) */ + #define R_OSPI_DWCSTR_DVWHI1_Msk (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_DWCSTR_DVWLO1_Pos (30UL) /*!< DVWLO1 (Bit 30) */ + #define R_OSPI_DWCSTR_DVWLO1_Msk (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03) */ +/* ========================================================= DCSTR ========================================================= */ + #define R_OSPI_DCSTR_DVSELCMD_Pos (8UL) /*!< DVSELCMD (Bit 8) */ + #define R_OSPI_DCSTR_DVSELCMD_Msk (0x700UL) /*!< DVSELCMD (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELHI_Pos (11UL) /*!< DVSELHI (Bit 11) */ + #define R_OSPI_DCSTR_DVSELHI_Msk (0x3800UL) /*!< DVSELHI (Bitfield-Mask: 0x07) */ + #define R_OSPI_DCSTR_DVSELLO_Pos (14UL) /*!< DVSELLO (Bit 14) */ + #define R_OSPI_DCSTR_DVSELLO_Msk (0xc000UL) /*!< DVSELLO (Bitfield-Mask: 0x03) */ +/* ========================================================= CDSR ========================================================== */ + #define R_OSPI_CDSR_DV0TTYP_Pos (0UL) /*!< DV0TTYP (Bit 0) */ + #define R_OSPI_CDSR_DV0TTYP_Msk (0x3UL) /*!< DV0TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV1TTYP_Pos (2UL) /*!< DV1TTYP (Bit 2) */ + #define R_OSPI_CDSR_DV1TTYP_Msk (0xcUL) /*!< DV1TTYP (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DV0PC_Pos (4UL) /*!< DV0PC (Bit 4) */ + #define R_OSPI_CDSR_DV0PC_Msk (0x10UL) /*!< DV0PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_DV1PC_Pos (5UL) /*!< DV1PC (Bit 5) */ + #define R_OSPI_CDSR_DV1PC_Msk (0x20UL) /*!< DV1PC (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME0_Pos (10UL) /*!< ACMEME0 (Bit 10) */ + #define R_OSPI_CDSR_ACMEME0_Msk (0x400UL) /*!< ACMEME0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMEME1_Pos (11UL) /*!< ACMEME1 (Bit 11) */ + #define R_OSPI_CDSR_ACMEME1_Msk (0x800UL) /*!< ACMEME1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_CDSR_ACMODE_Pos (12UL) /*!< ACMODE (Bit 12) */ + #define R_OSPI_CDSR_ACMODE_Msk (0x3000UL) /*!< ACMODE (Bitfield-Mask: 0x03) */ + #define R_OSPI_CDSR_DLFT_Pos (31UL) /*!< DLFT (Bit 31) */ + #define R_OSPI_CDSR_DLFT_Msk (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01) */ +/* ========================================================= MDLR ========================================================== */ + #define R_OSPI_MDLR_DV0RDL_Pos (0UL) /*!< DV0RDL (Bit 0) */ + #define R_OSPI_MDLR_DV0RDL_Msk (0xffUL) /*!< DV0RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV0WDL_Pos (8UL) /*!< DV0WDL (Bit 8) */ + #define R_OSPI_MDLR_DV0WDL_Msk (0xff00UL) /*!< DV0WDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1RDL_Pos (16UL) /*!< DV1RDL (Bit 16) */ + #define R_OSPI_MDLR_DV1RDL_Msk (0xff0000UL) /*!< DV1RDL (Bitfield-Mask: 0xff) */ + #define R_OSPI_MDLR_DV1WDL_Pos (24UL) /*!< DV1WDL (Bit 24) */ + #define R_OSPI_MDLR_DV1WDL_Msk (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff) */ +/* ========================================================= MRWCR ========================================================= */ + #define R_OSPI_MRWCR_DMRCMD0_Pos (0UL) /*!< DMRCMD0 (Bit 0) */ + #define R_OSPI_MRWCR_DMRCMD0_Msk (0xffUL) /*!< DMRCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMRCMD1_Pos (8UL) /*!< DMRCMD1 (Bit 8) */ + #define R_OSPI_MRWCR_DMRCMD1_Msk (0xff00UL) /*!< DMRCMD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD0_Pos (16UL) /*!< DMWCMD0 (Bit 16) */ + #define R_OSPI_MRWCR_DMWCMD0_Msk (0xff0000UL) /*!< DMWCMD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_MRWCR_DMWCMD1_Pos (24UL) /*!< DMWCMD1 (Bit 24) */ + #define R_OSPI_MRWCR_DMWCMD1_Msk (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff) */ +/* ======================================================== MRWCSR ========================================================= */ + #define R_OSPI_MRWCSR_MRAL0_Pos (0UL) /*!< MRAL0 (Bit 0) */ + #define R_OSPI_MRWCSR_MRAL0_Msk (0x7UL) /*!< MRAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL0_Pos (3UL) /*!< MRCL0 (Bit 3) */ + #define R_OSPI_MRWCSR_MRCL0_Msk (0x38UL) /*!< MRCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO0_Pos (6UL) /*!< MRO0 (Bit 6) */ + #define R_OSPI_MRWCSR_MRO0_Msk (0x40UL) /*!< MRO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN0_Pos (7UL) /*!< PREN0 (Bit 7) */ + #define R_OSPI_MRWCSR_PREN0_Msk (0x80UL) /*!< PREN0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL0_Pos (8UL) /*!< MWAL0 (Bit 8) */ + #define R_OSPI_MRWCSR_MWAL0_Msk (0x700UL) /*!< MWAL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL0_Pos (11UL) /*!< MWCL0 (Bit 11) */ + #define R_OSPI_MRWCSR_MWCL0_Msk (0x3800UL) /*!< MWCL0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO0_Pos (14UL) /*!< MWO0 (Bit 14) */ + #define R_OSPI_MRWCSR_MWO0_Msk (0x4000UL) /*!< MWO0 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MRAL1_Pos (16UL) /*!< MRAL1 (Bit 16) */ + #define R_OSPI_MRWCSR_MRAL1_Msk (0x70000UL) /*!< MRAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRCL1_Pos (19UL) /*!< MRCL1 (Bit 19) */ + #define R_OSPI_MRWCSR_MRCL1_Msk (0x380000UL) /*!< MRCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MRO1_Pos (22UL) /*!< MRO1 (Bit 22) */ + #define R_OSPI_MRWCSR_MRO1_Msk (0x400000UL) /*!< MRO1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_PREN1_Pos (23UL) /*!< PREN1 (Bit 23) */ + #define R_OSPI_MRWCSR_PREN1_Msk (0x800000UL) /*!< PREN1 (Bitfield-Mask: 0x01) */ + #define R_OSPI_MRWCSR_MWAL1_Pos (24UL) /*!< MWAL1 (Bit 24) */ + #define R_OSPI_MRWCSR_MWAL1_Msk (0x7000000UL) /*!< MWAL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWCL1_Pos (27UL) /*!< MWCL1 (Bit 27) */ + #define R_OSPI_MRWCSR_MWCL1_Msk (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07) */ + #define R_OSPI_MRWCSR_MWO1_Pos (30UL) /*!< MWO1 (Bit 30) */ + #define R_OSPI_MRWCSR_MWO1_Msk (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01) */ +/* ========================================================== ESR ========================================================== */ + #define R_OSPI_ESR_MRESR_Pos (0UL) /*!< MRESR (Bit 0) */ + #define R_OSPI_ESR_MRESR_Msk (0xffUL) /*!< MRESR (Bitfield-Mask: 0xff) */ + #define R_OSPI_ESR_MWESR_Pos (8UL) /*!< MWESR (Bit 8) */ + #define R_OSPI_ESR_MWESR_Msk (0xff00UL) /*!< MWESR (Bitfield-Mask: 0xff) */ +/* ========================================================= CWNDR ========================================================= */ + #define R_OSPI_CWNDR_WND_Pos (0UL) /*!< WND (Bit 0) */ + #define R_OSPI_CWNDR_WND_Msk (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CWDR ========================================================== */ + #define R_OSPI_CWDR_WD0_Pos (0UL) /*!< WD0 (Bit 0) */ + #define R_OSPI_CWDR_WD0_Msk (0xffUL) /*!< WD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD1_Pos (8UL) /*!< WD1 (Bit 8) */ + #define R_OSPI_CWDR_WD1_Msk (0xff00UL) /*!< WD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD2_Pos (16UL) /*!< WD2 (Bit 16) */ + #define R_OSPI_CWDR_WD2_Msk (0xff0000UL) /*!< WD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CWDR_WD3_Pos (24UL) /*!< WD3 (Bit 24) */ + #define R_OSPI_CWDR_WD3_Msk (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff) */ +/* ========================================================== CRR ========================================================== */ + #define R_OSPI_CRR_RD0_Pos (0UL) /*!< RD0 (Bit 0) */ + #define R_OSPI_CRR_RD0_Msk (0xffUL) /*!< RD0 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD1_Pos (8UL) /*!< RD1 (Bit 8) */ + #define R_OSPI_CRR_RD1_Msk (0xff00UL) /*!< RD1 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD2_Pos (16UL) /*!< RD2 (Bit 16) */ + #define R_OSPI_CRR_RD2_Msk (0xff0000UL) /*!< RD2 (Bitfield-Mask: 0xff) */ + #define R_OSPI_CRR_RD3_Pos (24UL) /*!< RD3 (Bit 24) */ + #define R_OSPI_CRR_RD3_Msk (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff) */ +/* ========================================================= ACSR ========================================================== */ + #define R_OSPI_ACSR_ACSR0_Pos (0UL) /*!< ACSR0 (Bit 0) */ + #define R_OSPI_ACSR_ACSR0_Msk (0x7UL) /*!< ACSR0 (Bitfield-Mask: 0x07) */ + #define R_OSPI_ACSR_ACSR1_Pos (3UL) /*!< ACSR1 (Bit 3) */ + #define R_OSPI_ACSR_ACSR1_Msk (0x38UL) /*!< ACSR1 (Bitfield-Mask: 0x07) */ +/* ======================================================== DCSMXR ========================================================= */ + #define R_OSPI_DCSMXR_CTWMX0_Pos (0UL) /*!< CTWMX0 (Bit 0) */ + #define R_OSPI_DCSMXR_CTWMX0_Msk (0x1ffUL) /*!< CTWMX0 (Bitfield-Mask: 0x1ff) */ + #define R_OSPI_DCSMXR_CTWMX1_Pos (16UL) /*!< CTWMX1 (Bit 16) */ + #define R_OSPI_DCSMXR_CTWMX1_Msk (0x1ff0000UL) /*!< CTWMX1 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== DWSCTSR ======================================================== */ + #define R_OSPI_DWSCTSR_CTSN0_Pos (0UL) /*!< CTSN0 (Bit 0) */ + #define R_OSPI_DWSCTSR_CTSN0_Msk (0x7ffUL) /*!< CTSN0 (Bitfield-Mask: 0x7ff) */ + #define R_OSPI_DWSCTSR_CTSN1_Pos (16UL) /*!< CTSN1 (Bit 16) */ + #define R_OSPI_DWSCTSR_CTSN1_Msk (0x7ff0000UL) /*!< CTSN1 (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_USB_HS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG ========================================================= */ + #define R_USB_HS0_SYSCFG_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USB_HS0_SYSCFG_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USB_HS0_SYSCFG_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DCFM_Pos (6UL) /*!< DCFM (Bit 6) */ + #define R_USB_HS0_SYSCFG_DCFM_Msk (0x40UL) /*!< DCFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USB_HS0_SYSCFG_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USB_HS0_SYSCFG_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSCFG_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USB_HS0_SYSCFG_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSWAIT ======================================================== */ + #define R_USB_HS0_BUSWAIT_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USB_HS0_BUSWAIT_BWAIT_Msk (0xfUL) /*!< BWAIT (Bitfield-Mask: 0x0f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USB_HS0_SYSSTS0_HTACT_Pos (6UL) /*!< HTACT (Bit 6) */ + #define R_USB_HS0_SYSSTS0_HTACT_Msk (0x40UL) /*!< HTACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Pos (5UL) /*!< SOFEA (Bit 5) */ + #define R_USB_HS0_SYSSTS0_SOFEA_Msk (0x20UL) /*!< SOFEA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_IDMON_Pos (2UL) /*!< IDMON (Bit 2) */ + #define R_USB_HS0_SYSSTS0_IDMON_Msk (0x4UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USB_HS0_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Pos (14UL) /*!< OVCMON (Bit 14) */ + #define R_USB_HS0_SYSSTS0_OVCMON_Msk (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03) */ +/* ======================================================== PLLSTA ========================================================= */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Pos (0UL) /*!< PLLLOCK (Bit 0) */ + #define R_USB_HS0_PLLSTA_PLLLOCK_Msk (0x1UL) /*!< PLLLOCK (Bitfield-Mask: 0x01) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos (11UL) /*!< HNPBTOA (Bit 11) */ + #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk (0x800UL) /*!< HNPBTOA (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Pos (10UL) /*!< EXICEN (Bit 10) */ + #define R_USB_HS0_DVSTCTR0_EXICEN_Msk (0x400UL) /*!< EXICEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos (9UL) /*!< VBUSEN (Bit 9) */ + #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk (0x200UL) /*!< VBUSEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USB_HS0_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Pos (7UL) /*!< RWUPE (Bit 7) */ + #define R_USB_HS0_DVSTCTR0_RWUPE_Msk (0x80UL) /*!< RWUPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Pos (6UL) /*!< USBRST (Bit 6) */ + #define R_USB_HS0_DVSTCTR0_USBRST_Msk (0x40UL) /*!< USBRST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Pos (5UL) /*!< RESUME (Bit 5) */ + #define R_USB_HS0_DVSTCTR0_RESUME_Msk (0x20UL) /*!< RESUME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_UACT_Pos (4UL) /*!< UACT (Bit 4) */ + #define R_USB_HS0_DVSTCTR0_UACT_Msk (0x10UL) /*!< UACT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USB_HS0_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USB_HS0_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USB_HS0_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USB_HS0_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOH ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOHH ======================================================== */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================= D0FIFOHH ======================================================== */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USB_HS0_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================= D1FIFOHH ======================================================== */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USB_HS0_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USB_HS0_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USB_HS0_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USB_HS0_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USB_HS0_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USB_HS0_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USB_HS0_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USB_HS0_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USB_HS0_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USB_HS0_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USB_HS0_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USB_HS0_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USB_HS0_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USB_HS0_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USB_HS0_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USB_HS0_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USB_HS0_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USB_HS0_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USB_HS0_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USB_HS0_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USB_HS0_INTENB1_OVRCRE_Pos (15UL) /*!< OVRCRE (Bit 15) */ + #define R_USB_HS0_INTENB1_OVRCRE_Msk (0x8000UL) /*!< OVRCRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_BCHGE_Pos (14UL) /*!< BCHGE (Bit 14) */ + #define R_USB_HS0_INTENB1_BCHGE_Msk (0x4000UL) /*!< BCHGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_DTCHE_Pos (12UL) /*!< DTCHE (Bit 12) */ + #define R_USB_HS0_INTENB1_DTCHE_Msk (0x1000UL) /*!< DTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_ATTCHE_Pos (11UL) /*!< ATTCHE (Bit 11) */ + #define R_USB_HS0_INTENB1_ATTCHE_Msk (0x800UL) /*!< ATTCHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Pos (9UL) /*!< L1RSMENDE (Bit 9) */ + #define R_USB_HS0_INTENB1_L1RSMENDE_Msk (0x200UL) /*!< L1RSMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_LPMENDE_Pos (8UL) /*!< LPMENDE (Bit 8) */ + #define R_USB_HS0_INTENB1_LPMENDE_Msk (0x100UL) /*!< LPMENDE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_EOFERRE_Pos (6UL) /*!< EOFERRE (Bit 6) */ + #define R_USB_HS0_INTENB1_EOFERRE_Msk (0x40UL) /*!< EOFERRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SIGNE_Pos (5UL) /*!< SIGNE (Bit 5) */ + #define R_USB_HS0_INTENB1_SIGNE_Msk (0x20UL) /*!< SIGNE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_SACKE_Pos (4UL) /*!< SACKE (Bit 4) */ + #define R_USB_HS0_INTENB1_SACKE_Msk (0x10UL) /*!< SACKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Pos (0UL) /*!< PDDETINTE0 (Bit 0) */ + #define R_USB_HS0_INTENB1_PDDETINTE0_Msk (0x1UL) /*!< PDDETINTE0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Pos (8UL) /*!< TRNENSEL (Bit 8) */ + #define R_USB_HS0_SOFCFG_TRNENSEL_Msk (0x100UL) /*!< TRNENSEL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USB_HS0_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USB_HS0_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USB_HS0_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYSET ========================================================= */ + #define R_USB_HS0_PHYSET_HSEB_Pos (15UL) /*!< HSEB (Bit 15) */ + #define R_USB_HS0_PHYSET_HSEB_Msk (0x8000UL) /*!< HSEB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSTART_Pos (11UL) /*!< REPSTART (Bit 11) */ + #define R_USB_HS0_PHYSET_REPSTART_Msk (0x800UL) /*!< REPSTART (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_REPSEL_Pos (8UL) /*!< REPSEL (Bit 8) */ + #define R_USB_HS0_PHYSET_REPSEL_Msk (0x300UL) /*!< REPSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CLKSEL_Pos (4UL) /*!< CLKSEL (Bit 4) */ + #define R_USB_HS0_PHYSET_CLKSEL_Msk (0x30UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYSET_CDPEN_Pos (3UL) /*!< CDPEN (Bit 3) */ + #define R_USB_HS0_PHYSET_CDPEN_Msk (0x8UL) /*!< CDPEN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_PLLRESET_Pos (1UL) /*!< PLLRESET (Bit 1) */ + #define R_USB_HS0_PHYSET_PLLRESET_Msk (0x2UL) /*!< PLLRESET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYSET_DIRPD_Pos (0UL) /*!< DIRPD (Bit 0) */ + #define R_USB_HS0_PHYSET_DIRPD_Msk (0x1UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USB_HS0_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USB_HS0_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USB_HS0_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USB_HS0_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USB_HS0_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USB_HS0_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USB_HS0_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USB_HS0_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USB_HS0_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USB_HS0_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USB_HS0_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USB_HS0_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USB_HS0_INTSTS1_OVRCR_Pos (15UL) /*!< OVRCR (Bit 15) */ + #define R_USB_HS0_INTSTS1_OVRCR_Msk (0x8000UL) /*!< OVRCR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_BCHG_Pos (14UL) /*!< BCHG (Bit 14) */ + #define R_USB_HS0_INTSTS1_BCHG_Msk (0x4000UL) /*!< BCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_DTCH_Pos (12UL) /*!< DTCH (Bit 12) */ + #define R_USB_HS0_INTSTS1_DTCH_Msk (0x1000UL) /*!< DTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_ATTCH_Pos (11UL) /*!< ATTCH (Bit 11) */ + #define R_USB_HS0_INTSTS1_ATTCH_Msk (0x800UL) /*!< ATTCH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Pos (9UL) /*!< L1RSMEND (Bit 9) */ + #define R_USB_HS0_INTSTS1_L1RSMEND_Msk (0x200UL) /*!< L1RSMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_LPMEND_Pos (8UL) /*!< LPMEND (Bit 8) */ + #define R_USB_HS0_INTSTS1_LPMEND_Msk (0x100UL) /*!< LPMEND (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_EOFERR_Pos (6UL) /*!< EOFERR (Bit 6) */ + #define R_USB_HS0_INTSTS1_EOFERR_Msk (0x40UL) /*!< EOFERR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SIGN_Pos (5UL) /*!< SIGN (Bit 5) */ + #define R_USB_HS0_INTSTS1_SIGN_Msk (0x20UL) /*!< SIGN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_SACK_Pos (4UL) /*!< SACK (Bit 4) */ + #define R_USB_HS0_INTSTS1_SACK_Msk (0x10UL) /*!< SACK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Pos (0UL) /*!< PDDETINT0 (Bit 0) */ + #define R_USB_HS0_INTSTS1_PDDETINT0_Msk (0x1UL) /*!< PDDETINT0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USB_HS0_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USB_HS0_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USB_HS0_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USB_HS0_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USB_HS0_UFRMNUM_DVCHG_Pos (15UL) /*!< DVCHG (Bit 15) */ + #define R_USB_HS0_UFRMNUM_DVCHG_Msk (0x8000UL) /*!< DVCHG (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USB_HS0_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USB_HS0_USBADDR_STSRECOV0_Pos (8UL) /*!< STSRECOV0 (Bit 8) */ + #define R_USB_HS0_USBADDR_STSRECOV0_Msk (0x700UL) /*!< STSRECOV0 (Bitfield-Mask: 0x07) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USB_HS0_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USB_HS0_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USB_HS0_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USB_HS0_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USB_HS0_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USB_HS0_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USB_HS0_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USB_HS0_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USB_HS0_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_DCPCFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_DCPMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USB_HS0_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQ_Pos (14UL) /*!< SUREQ (Bit 14) */ + #define R_USB_HS0_DCPCTR_SUREQ_Msk (0x4000UL) /*!< SUREQ (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_DCPCTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_DCPCTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Pos (11UL) /*!< SUREQCLR (Bit 11) */ + #define R_USB_HS0_DCPCTR_SUREQCLR_Msk (0x800UL) /*!< SUREQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PINGE_Pos (4UL) /*!< PINGE (Bit 4) */ + #define R_USB_HS0_DCPCTR_PINGE_Msk (0x10UL) /*!< PINGE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USB_HS0_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPESEL ======================================================== */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USB_HS0_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USB_HS0_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USB_HS0_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USB_HS0_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USB_HS0_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USB_HS0_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USB_HS0_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USB_HS0_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USB_HS0_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos (12UL) /*!< DEVSEL (Bit 12) */ + #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk (0xf000UL) /*!< DEVSEL (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USB_HS0_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USB_HS0_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USB_HS0_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USB_HS0_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USB_HS0_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USB_HS0_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USB_HS0_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Pos (13UL) /*!< CSCLR (Bit 13) */ + #define R_USB_HS0_PIPE_CTR_CSCLR_Msk (0x2000UL) /*!< CSCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Pos (12UL) /*!< CSSTS (Bit 12) */ + #define R_USB_HS0_PIPE_CTR_CSSTS_Msk (0x1000UL) /*!< CSSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USB_HS0_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USB_HS0_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USB_HS0_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USB_HS0_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USB_HS0_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USB_HS0_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USB_HS0_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ +/* ======================================================== DEVADD ========================================================= */ + #define R_USB_HS0_DEVADD_UPPHUB_Pos (11UL) /*!< UPPHUB (Bit 11) */ + #define R_USB_HS0_DEVADD_UPPHUB_Msk (0x7800UL) /*!< UPPHUB (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_DEVADD_HUBPORT_Pos (8UL) /*!< HUBPORT (Bit 8) */ + #define R_USB_HS0_DEVADD_HUBPORT_Msk (0x700UL) /*!< HUBPORT (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_DEVADD_USBSPD_Pos (6UL) /*!< USBSPD (Bit 6) */ + #define R_USB_HS0_DEVADD_USBSPD_Msk (0xc0UL) /*!< USBSPD (Bitfield-Mask: 0x03) */ +/* ======================================================== LPCTRL ========================================================= */ + #define R_USB_HS0_LPCTRL_HWUPM_Pos (7UL) /*!< HWUPM (Bit 7) */ + #define R_USB_HS0_LPCTRL_HWUPM_Msk (0x80UL) /*!< HWUPM (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USB_HS0_LPSTS_SUSPENDM_Pos (14UL) /*!< SUSPENDM (Bit 14) */ + #define R_USB_HS0_LPSTS_SUSPENDM_Msk (0x4000UL) /*!< SUSPENDM (Bitfield-Mask: 0x01) */ +/* ======================================================== BCCTRL ========================================================= */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Pos (9UL) /*!< PDDETSTS (Bit 9) */ + #define R_USB_HS0_BCCTRL_PDDETSTS_Msk (0x200UL) /*!< PDDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos (8UL) /*!< CHGDETSTS (Bit 8) */ + #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk (0x100UL) /*!< CHGDETSTS (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Pos (5UL) /*!< DCPMODE (Bit 5) */ + #define R_USB_HS0_BCCTRL_DCPMODE_Msk (0x20UL) /*!< DCPMODE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Pos (4UL) /*!< VDMSRCE (Bit 4) */ + #define R_USB_HS0_BCCTRL_VDMSRCE_Msk (0x10UL) /*!< VDMSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Pos (3UL) /*!< IDPSINKE (Bit 3) */ + #define R_USB_HS0_BCCTRL_IDPSINKE_Msk (0x8UL) /*!< IDPSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Pos (2UL) /*!< VDPSRCE (Bit 2) */ + #define R_USB_HS0_BCCTRL_VDPSRCE_Msk (0x4UL) /*!< VDPSRCE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Pos (1UL) /*!< IDMSINKE (Bit 1) */ + #define R_USB_HS0_BCCTRL_IDMSINKE_Msk (0x2UL) /*!< IDMSINKE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Pos (0UL) /*!< IDPSRCE (Bit 0) */ + #define R_USB_HS0_BCCTRL_IDPSRCE_Msk (0x1UL) /*!< IDPSRCE (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL1 ======================================================== */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos (14UL) /*!< L1EXTMD (Bit 14) */ + #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /*!< L1EXTMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos (8UL) /*!< HIRDTHR (Bit 8) */ + #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk (0xf00UL) /*!< HIRDTHR (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USB_HS0_PL1CTRL1_DVSQ_Msk (0xf0UL) /*!< DVSQ (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos (3UL) /*!< L1NEGOMD (Bit 3) */ + #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk (0x8UL) /*!< L1NEGOMD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos (1UL) /*!< L1RESPMD (Bit 1) */ + #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk (0x6UL) /*!< L1RESPMD (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos (0UL) /*!< L1RESPEN (Bit 0) */ + #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk (0x1UL) /*!< L1RESPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= PL1CTRL2 ======================================================== */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Pos (12UL) /*!< RWEMON (Bit 12) */ + #define R_USB_HS0_PL1CTRL2_RWEMON_Msk (0x1000UL) /*!< RWEMON (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos (8UL) /*!< HIRDMON (Bit 8) */ + #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk (0xf00UL) /*!< HIRDMON (Bitfield-Mask: 0x0f) */ +/* ======================================================= HL1CTRL1 ======================================================== */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos (1UL) /*!< L1STATUS (Bit 1) */ + #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk (0x6UL) /*!< L1STATUS (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Pos (0UL) /*!< L1REQ (Bit 0) */ + #define R_USB_HS0_HL1CTRL1_L1REQ_Msk (0x1UL) /*!< L1REQ (Bitfield-Mask: 0x01) */ +/* ======================================================= HL1CTRL2 ======================================================== */ + #define R_USB_HS0_HL1CTRL2_BESL_Pos (15UL) /*!< BESL (Bit 15) */ + #define R_USB_HS0_HL1CTRL2_BESL_Msk (0x8000UL) /*!< BESL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Pos (12UL) /*!< L1RWE (Bit 12) */ + #define R_USB_HS0_HL1CTRL2_L1RWE_Msk (0x1000UL) /*!< L1RWE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Pos (8UL) /*!< HIRD (Bit 8) */ + #define R_USB_HS0_HL1CTRL2_HIRD_Msk (0xf00UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos (0UL) /*!< L1ADDR (Bit 0) */ + #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk (0xfUL) /*!< L1ADDR (Bitfield-Mask: 0x0f) */ +/* ======================================================= PHYTRIM1 ======================================================== */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos (12UL) /*!< IMPOFFSET (Bit 12) */ + #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk (0x7000UL) /*!< IMPOFFSET (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Pos (8UL) /*!< HSIUP (Bit 8) */ + #define R_USB_HS0_PHYTRIM1_HSIUP_Msk (0xf00UL) /*!< HSIUP (Bitfield-Mask: 0x0f) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos (7UL) /*!< PCOMPENB (Bit 7) */ + #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk (0x80UL) /*!< PCOMPENB (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Pos (2UL) /*!< DFALL (Bit 2) */ + #define R_USB_HS0_PHYTRIM1_DFALL_Msk (0xcUL) /*!< DFALL (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Pos (0UL) /*!< DRISE (Bit 0) */ + #define R_USB_HS0_PHYTRIM1_DRISE_Msk (0x3UL) /*!< DRISE (Bitfield-Mask: 0x03) */ +/* ======================================================= PHYTRIM2 ======================================================== */ + #define R_USB_HS0_PHYTRIM2_DIS_Pos (12UL) /*!< DIS (Bit 12) */ + #define R_USB_HS0_PHYTRIM2_DIS_Msk (0x7000UL) /*!< DIS (Bitfield-Mask: 0x07) */ + #define R_USB_HS0_PHYTRIM2_PDR_Pos (8UL) /*!< PDR (Bit 8) */ + #define R_USB_HS0_PHYTRIM2_PDR_Msk (0x300UL) /*!< PDR (Bitfield-Mask: 0x03) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos (7UL) /*!< HSRXENMO (Bit 7) */ + #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk (0x80UL) /*!< HSRXENMO (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_PHYTRIM2_SQU_Pos (0UL) /*!< SQU (Bit 0) */ + #define R_USB_HS0_PHYTRIM2_SQU_Msk (0xfUL) /*!< SQU (Bitfield-Mask: 0x0f) */ +/* ======================================================== DPUSR0R ======================================================== */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos (23UL) /*!< DVBSTSHM (Bit 23) */ + #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos (21UL) /*!< DOVCBHM (Bit 21) */ + #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos (20UL) /*!< DOVCAHM (Bit 20) */ + #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR1R ======================================================== */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos (23UL) /*!< DVBSTSH (Bit 23) */ + #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Pos (21UL) /*!< DOVCBH (Bit 21) */ + #define R_USB_HS0_DPUSR1R_DOVCBH_Msk (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Pos (20UL) /*!< DOVCAH (Bit 20) */ + #define R_USB_HS0_DPUSR1R_DOVCAH_Msk (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos (7UL) /*!< DVBSTSHE (Bit 7) */ + #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk (0x80UL) /*!< DVBSTSHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos (5UL) /*!< DOVCBHE (Bit 5) */ + #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk (0x20UL) /*!< DOVCBHE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos (4UL) /*!< DOVCAHE (Bit 4) */ + #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk (0x10UL) /*!< DOVCAHE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSR2R ======================================================== */ + #define R_USB_HS0_DPUSR2R_DMINTE_Pos (9UL) /*!< DMINTE (Bit 9) */ + #define R_USB_HS0_DPUSR2R_DMINTE_Msk (0x200UL) /*!< DMINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Pos (8UL) /*!< DPINTE (Bit 8) */ + #define R_USB_HS0_DPUSR2R_DPINTE_Msk (0x100UL) /*!< DPINTE (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Pos (5UL) /*!< DMVAL (Bit 5) */ + #define R_USB_HS0_DPUSR2R_DMVAL_Msk (0x20UL) /*!< DMVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Pos (4UL) /*!< DPVAL (Bit 4) */ + #define R_USB_HS0_DPUSR2R_DPVAL_Msk (0x10UL) /*!< DPVAL (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DMINT_Pos (1UL) /*!< DMINT (Bit 1) */ + #define R_USB_HS0_DPUSR2R_DMINT_Msk (0x2UL) /*!< DMINT (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSR2R_DPINT_Pos (0UL) /*!< DPINT (Bit 0) */ + #define R_USB_HS0_DPUSR2R_DPINT_Msk (0x1UL) /*!< DPINT (Bitfield-Mask: 0x01) */ +/* ======================================================== DPUSRCR ======================================================== */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos (1UL) /*!< FIXPHYPD (Bit 1) */ + #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk (0x2UL) /*!< FIXPHYPD (Bitfield-Mask: 0x01) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Pos (0UL) /*!< FIXPHY (Bit 0) */ + #define R_USB_HS0_DPUSRCR_FIXPHY_Msk (0x1UL) /*!< FIXPHY (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6M5BH_H */ + +/** @} */ /* End of group R7FA6M5BH */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h new file mode 100644 index 00000000..8ad5235a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h @@ -0,0 +1,14557 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file ./out/R7FA6T1AD.h + * @brief CMSIS HeaderFile + * @version 1.0 + * @date 03. August 2022 + * @note Generated by SVDConv V3.3.42 on Wednesday, 03.08.2022 17:09:32 + * from File './out/R7FA6T1AD.svd', + */ + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup R7FA6T1AD + * @{ + */ + +#ifndef R7FA6T1AD_H + #define R7FA6T1AD_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ + #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + #include "system.h" /*!< R7FA6T1AD System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ +} R_PMISC_PMSAR_Type; /*!< Size = 2 (0x2) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x40085000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x4005C000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGT0) + */ + +typedef struct /*!< (@ 0x40084000) R_AGT0 Structure */ +{ + union + { + __IOM uint16_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint16_t AGT : 16; /*!< [15..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint16_t AGTCMA; /*!< (@ 0x00000002) AGT Compare Match A Register */ + + struct + { + __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint16_t AGTCMB; /*!< (@ 0x00000004) AGT Compare Match B Register */ + + struct + { + __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x00000008) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x00000009) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000A) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x0000000C) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x0000000D) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x0000000E) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x0000000F) AGT Pin Select Register */ + + struct + { + __IOM uint8_t SEL : 2; /*!< [1..0] AGTIO pin select */ + uint8_t : 2; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40044600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x40050000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40074000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x4005E000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x40054100) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 2; + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + + struct + { + __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for + * use in the operations are stored. */ + } DODIR_b; + }; + + union + { + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ + + struct + { + __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference + * in data comparison mode. This register also stores the + * results of operations in data addition and data subtraction + * modes. */ + } DODSR_b; + }; +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40041000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register */ + __IM uint16_t RESERVED1[5]; + __IOM R_ELC_ELSR_Type ELSR[23]; /*!< (@ 0x00000010) Event Link Setting Register [0..22] */ + __IM uint16_t RESERVED2[4]; + + union + { + __IOM uint16_t ELCSARA; /*!< (@ 0x00000074) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint16_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint16_t : 13; + } ELCSARA_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t ELCSARB; /*!< (@ 0x00000078) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint16_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint16_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint16_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint16_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint16_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint16_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint16_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint16_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint16_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint16_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + } ELCSARB_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ELCSARC; /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register + * C */ + + struct + { + __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution */ + __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution */ + __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution */ + uint16_t : 13; + } ELCSARC_b; + }; +} R_ELC_Type; /*!< Size = 126 (0x7e) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40078000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4007B000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40078FF0) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x40042000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x40053000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IrDA Interface (R_IRDA) + */ + +typedef struct /*!< (@ 0x40070F00) R_IRDA Structure */ +{ + union + { + __IOM uint8_t IRCR; /*!< (@ 0x00000000) IrDA Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching */ + __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching */ + uint8_t : 3; + __IOM uint8_t IRE : 1; /*!< [7..7] IrDA Enable */ + } IRCR_b; + }; +} R_IRDA_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40044400) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40080000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Memory Mirror Function (R_MMF) + */ + +typedef struct /*!< (@ 0x40001000) R_MMF Structure */ +{ + union + { + __IOM uint32_t MMSFR; /*!< (@ 0x00000000) MemMirror Special Function Register */ + + struct + { + uint32_t : 7; + __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot + * be set in the low-order 7 bits. These bits are fixed to + * 0. */ + uint32_t : 1; + __OM uint32_t KEY : 8; /*!< [31..24] MMSFR Key Code */ + } MMSFR_b; + }; + + union + { + __IOM uint32_t MMEN; /*!< (@ 0x00000004) MemMirror Enable Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Memory Mirror Function Enable */ + uint32_t : 23; + __OM uint32_t KEY : 8; /*!< [31..24] MMEN Key Code */ + } MMEN_b; + }; +} R_MMF_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40047000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x40040000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PODR; /*!< (@ 0x00000000) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } PODR_b; + }; + + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000002) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000004) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000006) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t PORR; /*!< (@ 0x00000008) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + + union + { + __OM uint16_t POSR; /*!< (@ 0x0000000A) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000C) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000E) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x40040D00) R_PMISC Structure */ +{ + union + { + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0 */ + __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1 */ + uint8_t : 2; + } PFENET_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x00000003) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000005) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint16_t RESERVED2[5]; + __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Realtime Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x40044000) R_RTC Structure */ +{ + __IM uint8_t RESERVED[34]; + __IM uint8_t RCR1; /*!< (@ 0x00000022) Reset Control Register 1 */ + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t RCR2; /*!< (@ 0x00000024) Reset Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t RESET : 1; /*!< [1..1] Software Reset */ + uint8_t : 6; + } RCR2_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t RCR4; /*!< (@ 0x00000028) RTC Control Register 4 */ + + struct + { + __IOM uint8_t RCKSEL : 1; /*!< [0..0] Count Source Select */ + uint8_t : 7; + } RCR4_b; + }; +} R_RTC_Type; /*!< Size = 41 (0x29) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40070000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x40072000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Sampling Rate Converter (R_SRC) + */ + +typedef struct /*!< (@ 0x40048000) R_SRC Structure */ +{ + union + { + __IOM uint32_t SRCFCTR[5552]; /*!< (@ 0x00000000) Filter Coefficient Table [0..5551] */ + + struct + { + __IOM uint32_t SRCFCOE : 22; /*!< [21..0] Stores a filter coefficient value. */ + uint32_t : 10; + } SRCFCTR_b[5552]; + }; + __IM uint32_t RESERVED[588]; + + union + { + __OM uint32_t SRCID; /*!< (@ 0x00005FF0) Input Data Register */ + + struct + { + __OM uint32_t SRCID : 32; /*!< [31..0] SRCID is a 32-bit writ-only register that is used to + * input the data before sampling rate conversion. All the + * bits are read as 0. */ + } SRCID_b; + }; + + union + { + __IM uint32_t SRCOD; /*!< (@ 0x00005FF4) Output Data Register */ + + struct + { + __IM uint32_t SRCOD : 32; /*!< [31..0] SRCOD is a 32-bit read-only register used to output + * the data after sampling rate conversion. The data in the + * 16-stage output data FIFO is read through SRCOD. When the + * number of data in the output data FIFO is zero after the + * start of conversion, the value previously read is read + * again. */ + } SRCOD_b; + }; + + union + { + __IOM uint16_t SRCIDCTRL; /*!< (@ 0x00005FF8) Input Data Control Register */ + + struct + { + __IOM uint16_t IFTRG : 2; /*!< [1..0] Input FIFO Data Triggering Number */ + uint16_t : 6; + __IOM uint16_t IEN : 1; /*!< [8..8] Input FIFO Empty Interrupt Enable */ + __IOM uint16_t IED : 1; /*!< [9..9] Input Data Endian */ + uint16_t : 6; + } SRCIDCTRL_b; + }; + + union + { + __IOM uint16_t SRCODCTRL; /*!< (@ 0x00005FFA) Output Data Control Register */ + + struct + { + __IOM uint16_t OFTRG : 2; /*!< [1..0] Output FIFO Data Trigger Number */ + uint16_t : 6; + __IOM uint16_t OEN : 1; /*!< [8..8] Output Data FIFO Full Interrupt Enable */ + __IOM uint16_t OED : 1; /*!< [9..9] Output Data Endian */ + __IOM uint16_t OCH : 1; /*!< [10..10] Output Data Channel Exchange */ + uint16_t : 5; + } SRCODCTRL_b; + }; + + union + { + __IOM uint16_t SRCCTRL; /*!< (@ 0x00005FFC) Control Register */ + + struct + { + __IOM uint16_t OFS : 3; /*!< [2..0] Output Sampling Rate */ + uint16_t : 1; + __IOM uint16_t IFS : 4; /*!< [7..4] Input Sampling Rate */ + __IOM uint16_t CL : 1; /*!< [8..8] Internal Work Memory Clear */ + __IOM uint16_t FL : 1; /*!< [9..9] Internal Work Memory Flush */ + __IOM uint16_t OVEN : 1; /*!< [10..10] Output Data FIFO Overwrite Interrupt Enable */ + __IOM uint16_t UDEN : 1; /*!< [11..11] Output Data FIFO Underflow Interrupt Enable */ + __IOM uint16_t SRCEN : 1; /*!< [12..12] Module Enable */ + __IOM uint16_t CEEN : 1; /*!< [13..13] Conversion End Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t FICRAE : 1; /*!< [15..15] Filter Coefficient Table Access Enable */ + } SRCCTRL_b; + }; + + union + { + __IOM uint16_t SRCSTAT; /*!< (@ 0x00005FFE) Status Register */ + + struct + { + __IOM uint16_t OINT : 1; /*!< [0..0] Output Data FIFO Full Interrupt Request Flag */ + __IOM uint16_t IINT : 1; /*!< [1..1] Input Data FIFO Empty Interrupt Request Flag */ + __IOM uint16_t OVF : 1; /*!< [2..2] Output Data FIFO Overwrite Interrupt Request Flag */ + __IOM uint16_t UDF : 1; /*!< [3..3] Output FIFO Underflow Interrupt Request Flag */ + __IM uint16_t FLF : 1; /*!< [4..4] Flush Processing Status Flag */ + __IOM uint16_t CEF : 1; /*!< [5..5] Conversion End Flag */ + uint16_t : 1; + __IOM uint16_t IFDN : 4; /*!< [10..7] Input FIFO Data CountIndicates the number of data units + * in the input FIFO. */ + __IOM uint16_t OFDN : 5; /*!< [15..11] Output FIFO Data CountIndicates the number of data + * units in the output FIFO. */ + } SRCSTAT_b; + }; +} R_SRC_Type; /*!< Size = 24576 (0x6000) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x4005D000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40044200) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x40085000UL + #define R_ACMPHS1_BASE 0x40085100UL + #define R_ACMPHS2_BASE 0x40085200UL + #define R_ACMPHS3_BASE 0x40085300UL + #define R_ACMPHS4_BASE 0x40085400UL + #define R_ACMPHS5_BASE 0x40085500UL + #define R_ADC0_BASE 0x4005C000UL + #define R_ADC1_BASE 0x4005C200UL + #define R_AGT0_BASE 0x40084000UL + #define R_AGT1_BASE 0x40084100UL + #define R_AGT2_BASE 0x40084200UL + #define R_AGT3_BASE 0x40084300UL + #define R_AGT4_BASE 0x40084400UL + #define R_AGT5_BASE 0x40084500UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40044600UL + #define R_CAN0_BASE 0x40050000UL + #define R_CAN1_BASE 0x40051000UL + #define R_CRC_BASE 0x40074000UL + #define R_DAC_BASE 0x4005E000UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DOC_BASE 0x40054100UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40041000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40078000UL + #define R_GPT1_BASE 0x40078100UL + #define R_GPT2_BASE 0x40078200UL + #define R_GPT3_BASE 0x40078300UL + #define R_GPT4_BASE 0x40078400UL + #define R_GPT5_BASE 0x40078500UL + #define R_GPT6_BASE 0x40078600UL + #define R_GPT7_BASE 0x40078700UL + #define R_GPT8_BASE 0x40078800UL + #define R_GPT9_BASE 0x40078900UL + #define R_GPT10_BASE 0x40078A00UL + #define R_GPT11_BASE 0x40078B00UL + #define R_GPT12_BASE 0x40078C00UL + #define R_GPT13_BASE 0x40078D00UL + #define R_GPT_ODC_BASE 0x4007B000UL + #define R_GPT_OPS_BASE 0x40078FF0UL + #define R_GPT_POEG0_BASE 0x40042000UL + #define R_GPT_POEG1_BASE 0x40042100UL + #define R_GPT_POEG2_BASE 0x40042200UL + #define R_GPT_POEG3_BASE 0x40042300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x40053000UL + #define R_IIC1_BASE 0x40053100UL + #define R_IIC2_BASE 0x40053200UL + #define R_IRDA_BASE 0x40070F00UL + #define R_IWDT_BASE 0x40044400UL + #define R_KINT_BASE 0x40080000UL + #define R_MMF_BASE 0x40001000UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */ + #define R_PORT0_BASE 0x40040000UL + #define R_PORT1_BASE 0x40040020UL + #define R_PORT2_BASE 0x40040040UL + #define R_PORT3_BASE 0x40040060UL + #define R_PORT4_BASE 0x40040080UL + #define R_PORT5_BASE 0x400400A0UL + #define R_PORT6_BASE 0x400400C0UL + #define R_PORT7_BASE 0x400400E0UL + #define R_PORT8_BASE 0x40040100UL + #define R_PORT9_BASE 0x40040120UL + #define R_PORT10_BASE 0x40040140UL + #define R_PORT11_BASE 0x40040160UL + #define R_PORT12_BASE 0x40040180UL + #define R_PORT13_BASE 0x400401A0UL + #define R_PORT14_BASE 0x400401C0UL + #define R_PFS_BASE 0x40040800UL + #define R_PMISC_BASE 0x40040D00UL + #define R_RTC_BASE 0x40044000UL + #define R_SCI0_BASE 0x40070000UL + #define R_SCI1_BASE 0x40070020UL + #define R_SCI2_BASE 0x40070040UL + #define R_SCI3_BASE 0x40070060UL + #define R_SCI4_BASE 0x40070080UL + #define R_SCI5_BASE 0x400700A0UL + #define R_SCI6_BASE 0x400700C0UL + #define R_SCI7_BASE 0x400700E0UL + #define R_SCI8_BASE 0x40070100UL + #define R_SCI9_BASE 0x40070120UL + #define R_SPI0_BASE 0x40072000UL + #define R_SPI1_BASE 0x40072100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SRC_BASE 0x40048000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x4005D000UL + #define R_WDT_BASE 0x40044200UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_AGT0 ((R_AGT0_Type *) R_AGT0_BASE) + #define R_AGT1 ((R_AGT0_Type *) R_AGT1_BASE) + #define R_AGT2 ((R_AGT0_Type *) R_AGT2_BASE) + #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) + #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) + #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC ((R_DAC_Type *) R_DAC_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IRDA ((R_IRDA_Type *) R_IRDA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_MMF ((R_MMF_Type *) R_MMF_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SRC ((R_SRC_Type *) R_SRC_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGT0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGT0_AGT_AGT_Msk (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGT0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGT0_AGTCMA_AGTCMA_Msk (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGT0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGT0_AGTCMB_AGTCMB_Msk (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGT0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGT0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGT0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGT0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGT0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGT0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGT0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGT0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGT0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGT0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGT0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGT0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGT0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGT0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGT0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGT0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGT0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGT0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGT0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGT0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGT0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGT0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGT0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGT0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGT0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGT0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGT0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGT0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGT0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGT0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGT0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGT0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGT0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + #define R_AGT0_AGTIOSEL_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_AGT0_AGTIOSEL_SEL_Msk (0x3UL) /*!< SEL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ +/* ========================================================= DODIR ========================================================= */ + #define R_DOC_DODIR_DODIR_Pos (0UL) /*!< DODIR (Bit 0) */ + #define R_DOC_DODIR_DODIR_Msk (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DODSR ========================================================= */ + #define R_DOC_DODSR_DODSR_Pos (0UL) /*!< DODSR (Bit 0) */ + #define R_DOC_DODSR_DODSR_Msk (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARC ======================================================== */ + #define R_ELC_ELCSARC_ELSR16_Pos (0UL) /*!< ELSR16 (Bit 0) */ + #define R_ELC_ELCSARC_ELSR16_Msk (0x1UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR17_Pos (1UL) /*!< ELSR17 (Bit 1) */ + #define R_ELC_ELCSARC_ELSR17_Msk (0x2UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARC_ELSR18_Pos (2UL) /*!< ELSR18 (Bit 2) */ + #define R_ELC_ELCSARC_ELSR18_Msk (0x4UL) /*!< ELSR18 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IRDA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRCR ========================================================== */ + #define R_IRDA_IRCR_IRE_Pos (7UL) /*!< IRE (Bit 7) */ + #define R_IRDA_IRCR_IRE_Msk (0x80UL) /*!< IRE (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRTXINV_Pos (3UL) /*!< IRTXINV (Bit 3) */ + #define R_IRDA_IRCR_IRTXINV_Msk (0x8UL) /*!< IRTXINV (Bitfield-Mask: 0x01) */ + #define R_IRDA_IRCR_IRRXINV_Pos (2UL) /*!< IRRXINV (Bit 2) */ + #define R_IRDA_IRCR_IRRXINV_Msk (0x4UL) /*!< IRRXINV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MMF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= MMSFR ========================================================= */ + #define R_MMF_MMSFR_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMSFR_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMSFR_MEMMIRADDR_Pos (7UL) /*!< MEMMIRADDR (Bit 7) */ + #define R_MMF_MMSFR_MEMMIRADDR_Msk (0x7fff80UL) /*!< MEMMIRADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= MMEN ========================================================== */ + #define R_MMF_MMEN_KEY_Pos (24UL) /*!< KEY (Bit 24) */ + #define R_MMF_MMEN_KEY_Msk (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MMF_MMEN_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_MMF_MMEN_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PODR ========================================================== */ + #define R_PORT0_PODR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_PODR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ + #define R_PMISC_PFENET_PHYMODE1_Pos (5UL) /*!< PHYMODE1 (Bit 5) */ + #define R_PMISC_PFENET_PHYMODE1_Msk (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01) */ + #define R_PMISC_PFENET_PHYMODE0_Pos (4UL) /*!< PHYMODE0 (Bit 4) */ + #define R_PMISC_PFENET_PHYMODE0_Msk (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RCR1 ========================================================== */ +/* ========================================================= RCR2 ========================================================== */ + #define R_RTC_RCR2_RESET_Pos (1UL) /*!< RESET (Bit 1) */ + #define R_RTC_RCR2_RESET_Msk (0x2UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ========================================================= RCR4 ========================================================== */ + #define R_RTC_RCR4_RCKSEL_Pos (0UL) /*!< RCKSEL (Bit 0) */ + #define R_RTC_RCR4_RCKSEL_Msk (0x1UL) /*!< RCKSEL (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SRCFCTR ======================================================== */ + #define R_SRC_SRCFCTR_SRCFCOE_Pos (0UL) /*!< SRCFCOE (Bit 0) */ + #define R_SRC_SRCFCTR_SRCFCOE_Msk (0x3fffffUL) /*!< SRCFCOE (Bitfield-Mask: 0x3fffff) */ +/* ========================================================= SRCID ========================================================= */ + #define R_SRC_SRCID_SRCID_Pos (0UL) /*!< SRCID (Bit 0) */ + #define R_SRC_SRCID_SRCID_Msk (0xffffffffUL) /*!< SRCID (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SRCOD ========================================================= */ + #define R_SRC_SRCOD_SRCOD_Pos (0UL) /*!< SRCOD (Bit 0) */ + #define R_SRC_SRCOD_SRCOD_Msk (0xffffffffUL) /*!< SRCOD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= SRCIDCTRL ======================================================= */ + #define R_SRC_SRCIDCTRL_IED_Pos (9UL) /*!< IED (Bit 9) */ + #define R_SRC_SRCIDCTRL_IED_Msk (0x200UL) /*!< IED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IEN_Pos (8UL) /*!< IEN (Bit 8) */ + #define R_SRC_SRCIDCTRL_IEN_Msk (0x100UL) /*!< IEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCIDCTRL_IFTRG_Pos (0UL) /*!< IFTRG (Bit 0) */ + #define R_SRC_SRCIDCTRL_IFTRG_Msk (0x3UL) /*!< IFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCCTRL ======================================================== */ + #define R_SRC_SRCCTRL_FICRAE_Pos (15UL) /*!< FICRAE (Bit 15) */ + #define R_SRC_SRCCTRL_FICRAE_Msk (0x8000UL) /*!< FICRAE (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CEEN_Pos (13UL) /*!< CEEN (Bit 13) */ + #define R_SRC_SRCCTRL_CEEN_Msk (0x2000UL) /*!< CEEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_SRCEN_Pos (12UL) /*!< SRCEN (Bit 12) */ + #define R_SRC_SRCCTRL_SRCEN_Msk (0x1000UL) /*!< SRCEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_UDEN_Pos (11UL) /*!< UDEN (Bit 11) */ + #define R_SRC_SRCCTRL_UDEN_Msk (0x800UL) /*!< UDEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_OVEN_Pos (10UL) /*!< OVEN (Bit 10) */ + #define R_SRC_SRCCTRL_OVEN_Msk (0x400UL) /*!< OVEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_FL_Pos (9UL) /*!< FL (Bit 9) */ + #define R_SRC_SRCCTRL_FL_Msk (0x200UL) /*!< FL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_CL_Pos (8UL) /*!< CL (Bit 8) */ + #define R_SRC_SRCCTRL_CL_Msk (0x100UL) /*!< CL (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCCTRL_IFS_Pos (4UL) /*!< IFS (Bit 4) */ + #define R_SRC_SRCCTRL_IFS_Msk (0xf0UL) /*!< IFS (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCCTRL_OFS_Pos (0UL) /*!< OFS (Bit 0) */ + #define R_SRC_SRCCTRL_OFS_Msk (0x7UL) /*!< OFS (Bitfield-Mask: 0x07) */ +/* ======================================================= SRCODCTRL ======================================================= */ + #define R_SRC_SRCODCTRL_OCH_Pos (10UL) /*!< OCH (Bit 10) */ + #define R_SRC_SRCODCTRL_OCH_Msk (0x400UL) /*!< OCH (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OED_Pos (9UL) /*!< OED (Bit 9) */ + #define R_SRC_SRCODCTRL_OED_Msk (0x200UL) /*!< OED (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OEN_Pos (8UL) /*!< OEN (Bit 8) */ + #define R_SRC_SRCODCTRL_OEN_Msk (0x100UL) /*!< OEN (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCODCTRL_OFTRG_Pos (0UL) /*!< OFTRG (Bit 0) */ + #define R_SRC_SRCODCTRL_OFTRG_Msk (0x3UL) /*!< OFTRG (Bitfield-Mask: 0x03) */ +/* ======================================================== SRCSTAT ======================================================== */ + #define R_SRC_SRCSTAT_OFDN_Pos (11UL) /*!< OFDN (Bit 11) */ + #define R_SRC_SRCSTAT_OFDN_Msk (0xf800UL) /*!< OFDN (Bitfield-Mask: 0x1f) */ + #define R_SRC_SRCSTAT_IFDN_Pos (7UL) /*!< IFDN (Bit 7) */ + #define R_SRC_SRCSTAT_IFDN_Msk (0x780UL) /*!< IFDN (Bitfield-Mask: 0x0f) */ + #define R_SRC_SRCSTAT_CEF_Pos (5UL) /*!< CEF (Bit 5) */ + #define R_SRC_SRCSTAT_CEF_Msk (0x20UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_FLF_Pos (4UL) /*!< FLF (Bit 4) */ + #define R_SRC_SRCSTAT_FLF_Msk (0x10UL) /*!< FLF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_UDF_Pos (3UL) /*!< UDF (Bit 3) */ + #define R_SRC_SRCSTAT_UDF_Msk (0x8UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OVF_Pos (2UL) /*!< OVF (Bit 2) */ + #define R_SRC_SRCSTAT_OVF_Msk (0x4UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_IINT_Pos (1UL) /*!< IINT (Bit 1) */ + #define R_SRC_SRCSTAT_IINT_Msk (0x2UL) /*!< IINT (Bitfield-Mask: 0x01) */ + #define R_SRC_SRCSTAT_OINT_Pos (0UL) /*!< OINT (Bit 0) */ + #define R_SRC_SRCSTAT_OINT_Msk (0x1UL) /*!< OINT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6T1AD_H */ + +/** @} */ /* End of group R7FA6T1AD */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h new file mode 100644 index 00000000..291e667b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h @@ -0,0 +1,30200 @@ +/* + * This software is supplied by Renesas Electronics Corporation and is only intended for + * use with Renesas products. No other uses are authorized. This software is owned by + * Renesas Electronics Corporation and is protected under all applicable laws, including + * copyright laws. + * + * THIS SOFTWARE IS PROVIDED 'AS IS' AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO + * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM EXTENT PERMITTED NOT + * PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED + * COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL + * DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * + * Renesas reserves the right, without notice, to make changes to this software and to + * discontinue the availability of this software. By using this software, you agree to + * the additional terms and conditions found by accessing the following link: + * http://www.renesas.com/disclaimer + * + * + * @file ./out/R7FA6T2BD.h + * @brief CMSIS HeaderFile + * @version 1.10.01 + * @date 11. August 2022 + * @note Generated by SVDConv V3.3.42 on Thursday, 11.08.2022 23:19:22 + * from File './out/R7FA6T2BD.svd', + */ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R7FA6T2BD + * @{ + */ + +#ifndef R7FA6T2BD_H + #define R7FA6T2BD_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ + #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ + #define __MPU_PRESENT 1 /*!< MPU present */ + #define __FPU_PRESENT 1 /*!< FPU present */ + #define __FPU_DP 0 /*!< Double Precision FPU */ + #define __DSP_PRESENT 1 /*!< DSP extension present */ + #define __SAUREGION_PRESENT 0 /*!< SAU region present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system.h" /*!< R7FA6T2BD System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_BUS_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t SDCCR; /*!< (@ 0x00000000) SDC Control Register */ + + struct + { + __IOM uint8_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint8_t : 3; + __IOM uint8_t BSIZE : 2; /*!< [5..4] SDRAM Bus Width Select */ + uint8_t : 2; + } SDCCR_b; + }; + + union + { + __IOM uint8_t SDCMOD; /*!< (@ 0x00000001) SDC Mode Register */ + + struct + { + __IOM uint8_t EMODE : 1; /*!< [0..0] Endian Mode */ + uint8_t : 7; + } SDCMOD_b; + }; + + union + { + __IOM uint8_t SDAMOD; /*!< (@ 0x00000002) SDRAM Access Mode Register */ + + struct + { + __IOM uint8_t BE : 1; /*!< [0..0] Continuous Access Enable */ + uint8_t : 7; + } SDAMOD_b; + }; + __IM uint8_t RESERVED; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint8_t SDSELF; /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register */ + + struct + { + __IOM uint8_t SFEN : 1; /*!< [0..0] SDRAM Self-Refresh Enable */ + uint8_t : 7; + } SDSELF_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t SDRFCR; /*!< (@ 0x00000014) SDRAM Refresh Control Register */ + + struct + { + __IOM uint16_t RFC : 12; /*!< [11..0] Auto-Refresh Request Interval Setting */ + __IOM uint16_t REFW : 4; /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count + * Setting. ( REFW+1 Cycles ) */ + } SDRFCR_b; + }; + + union + { + __IOM uint8_t SDRFEN; /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register */ + + struct + { + __IOM uint8_t RFEN : 1; /*!< [0..0] Auto-Refresh Operation Enable */ + uint8_t : 7; + } SDRFEN_b; + }; + __IM uint8_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint8_t SDICR; /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register */ + + struct + { + __IOM uint8_t INIRQ : 1; /*!< [0..0] Initialization Sequence Start */ + uint8_t : 7; + } SDICR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint16_t SDIR; /*!< (@ 0x00000024) SDRAM Initialization Register */ + + struct + { + __IOM uint16_t ARFI : 4; /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles ) */ + __IOM uint16_t ARFC : 4; /*!< [7..4] Initialization Auto-Refresh Count */ + __IOM uint16_t PRC : 3; /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles + * ) */ + uint16_t : 5; + } SDIR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[6]; + + union + { + __IOM uint8_t SDADR; /*!< (@ 0x00000040) SDRAM Address Register */ + + struct + { + __IOM uint8_t MXC : 2; /*!< [1..0] Address Multiplex Select */ + uint8_t : 6; + } SDADR_b; + }; + __IM uint8_t RESERVED10; + __IM uint16_t RESERVED11; + + union + { + __IOM uint32_t SDTR; /*!< (@ 0x00000044) SDRAM Timing Register */ + + struct + { + __IOM uint32_t CL : 3; /*!< [2..0] SDRAMC Column Latency */ + uint32_t : 5; + __IOM uint32_t WR : 1; /*!< [8..8] Write Recovery Interval */ + __IOM uint32_t RP : 3; /*!< [11..9] Row Precharge Interval ( RP+1 cycles ) */ + __IOM uint32_t RCD : 2; /*!< [13..12] Row Column Latency ( RCD+1 cycles ) */ + uint32_t : 2; + __IOM uint32_t RAS : 3; /*!< [18..16] Row Active Interval */ + uint32_t : 13; + } SDTR_b; + }; + + union + { + __IOM uint16_t SDMOD; /*!< (@ 0x00000048) SDRAM Mode Register */ + + struct + { + __IOM uint16_t MR : 15; /*!< [14..0] Mode Register SettingWriting to these bits: Mode register + * set command is issued. */ + uint16_t : 1; + } SDMOD_b; + }; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13; + + union + { + __IM uint8_t SDSR; /*!< (@ 0x00000050) SDRAM Status Register */ + + struct + { + __IM uint8_t MRSST : 1; /*!< [0..0] Mode Register Setting Status */ + uint8_t : 2; + __IM uint8_t INIST : 1; /*!< [3..3] Initialization Status */ + __IM uint8_t SRFST : 1; /*!< [4..4] Self-Refresh Transition/Recovery Status */ + uint8_t : 3; + } SDSR_b; + }; + __IM uint8_t RESERVED14; + __IM uint16_t RESERVED15; +} R_BUS_SDRAM_Type; /*!< Size = 84 (0x54) */ + +/** + * @brief R_BUS_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t STAT; /*!< (@ 0x00000004) Bus Error Status Register */ + + struct + { + __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 6; + __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error StatusWhen bus error assert, error flag occurs. */ + } STAT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_BUSM [BUSM] (Master Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Master Bus Control Register */ + + struct + { + uint16_t : 15; + __IOM uint16_t IERES : 1; /*!< [15..15] Ignore Error Responses */ + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSM_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array) + */ +typedef struct +{ + union + { + __IOM uint16_t CNT; /*!< (@ 0x00000000) Slave Bus Control Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration MethodSpecify the priority between groups */ + uint16_t : 10; + } CNT_b; + }; + __IM uint16_t RESERVED; +} R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_CAN0_MB [MB] (Mailbox) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } ID_b; + }; + + union + { + __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ + + struct + { + __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ + uint16_t : 12; + } DL_b; + }; + + union + { + __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ + + struct + { + __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN + * message data. Transmission or reception starts from DATA0. + * The bit order on the CAN bus is MSB-first, and transmission + * or reception starts from bit 7 */ + } D_b[8]; + }; + + union + { + __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ + + struct + { + __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter + * value of the time stamp when received messages are stored + * in the mailbox. */ + } TS_b; + }; +} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ + __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ + __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFDL_CFDC [CFDC] (Channel Control/Status) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ + __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFDL_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFDL_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + uint32_t : 4; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ + uint32_t : 1; + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ + } FDSTS_b; + }; + + union + { + __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ + uint32_t : 3; + __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ + uint32_t : 4; + } FDCRC_b; + }; + __IM uint32_t RESERVED[3]; +} R_CANFDL_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFDL_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + uint32_t : 3; + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + + struct + { + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; + } P1_b; + }; +} R_CANFDL_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFDL_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ + uint32_t : 6; + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFDL_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFDL_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFDL_CFDRF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFDL_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFDL_CFDCF_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFDL_CFDTM [CFDTM] (TX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + uint32_t : 1; + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFDL_CFDTM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFDL_CFDRMC_RM [RM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; +} R_CANFDL_CFDRMC_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFDL_CFDRMC [CFDRMC] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFDL_CFDRMC_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFDL_CFDRMC_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + + struct + { + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; + }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..29]) + */ +typedef struct +{ + union + { + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + + struct + { + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; + }; + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + */ +typedef struct +{ + union + { + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; + }; + + union + { + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + + struct + { + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; + }; +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + + struct + { + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers) + */ +typedef struct +{ + __OM uint32_t INP; /*!< (@ 0x00000000) Channel Input Register */ + __IM uint32_t OUT; /*!< (@ 0x00000004) Channel Output Register */ + + union + { + __IOM uint32_t CNT; /*!< (@ 0x00000008) Channel Control Register */ + + struct + { + __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit */ + } CNT_b; + }; + + union + { + __IOM uint8_t INT; /*!< (@ 0x0000000C) Channel Interrupt Enable Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit */ + __IOM uint8_t ORDYIE : 1; /*!< [2..2] Output data preparation completion interrupt enable bit */ + __IOM uint8_t CERRIE : 1; /*!< [3..3] Operation error interrupt enable bit */ + uint8_t : 4; + } INT_b; + }; + + union + { + __IM uint8_t STS; /*!< (@ 0x0000000D) Channel Status Register */ + + struct + { + __IM uint8_t CPRCS : 1; /*!< [0..0] Channel processing status flag */ + __IM uint8_t CPRCFF : 1; /*!< [1..1] Channel processing completion flag */ + __IM uint8_t ORDYF : 1; /*!< [2..2] Output data preparation completion flag */ + __IM uint8_t CERRF : 1; /*!< [3..3] Operation error flag */ + uint8_t : 4; + } STS_b; + }; + + union + { + __OM uint8_t FCLR; /*!< (@ 0x0000000E) Channel Flag Clear Register */ + + struct + { + uint8_t : 1; + __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit */ + uint8_t : 1; + __OM uint8_t CERRFCLR : 1; /*!< [3..3] Operation error flag clear bit */ + uint8_t : 4; + } FCLR_b; + }; + __IM uint8_t RESERVED; +} R_IIRFA_IIRCH_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers) + */ +typedef struct +{ + __IOM uint32_t B0; /*!< (@ 0x00000000) Stage Coefficient b0 Register */ + __IOM uint32_t B1; /*!< (@ 0x00000004) Stage Coefficient b1 Register */ + __IOM uint32_t B2; /*!< (@ 0x00000008) Stage Coefficient b2 Register */ + __IOM uint32_t A1; /*!< (@ 0x0000000C) Stage Coefficient a1 Register */ + __IOM uint32_t A2; /*!< (@ 0x00000010) Stage Coefficient a2 Register */ + __IOM uint32_t D0; /*!< (@ 0x00000014) Stage Delay Data D0 Register */ + __IOM uint32_t D1; /*!< (@ 0x00000018) Stage Delay Data D1 Register */ + __IM uint32_t RESERVED; +} R_IIRFA_IIRSTG_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) + */ +typedef struct +{ + union + { + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ + + struct + { + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; + }; + + union + { + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; + }; + + union + { + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ + + struct + { + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; + }; + + union + { + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ + + struct + { + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; + }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ + union + { + union + { + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ + + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; + + struct + { + union + { + struct + { + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ + + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; + }; +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief High-Speed Analog Comparator (R_ACMPHS0) + */ + +typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ +{ + union + { + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ + + struct + { + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ + + struct + { + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; + }; + __IM uint8_t RESERVED2[3]; + + union + { + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ + + struct + { + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; + }; + __IM uint8_t RESERVED3[3]; + + union + { + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ + + struct + { + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; + }; +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief A/D Converter (R_ADC0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; + }; + + union + { + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ + + struct + { + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; + }; + + union + { + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ + + struct + { + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; + }; + + union + { + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ + + struct + { + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; + }; + + union + { + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ + + struct + { + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; + }; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan + * mode. */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; + }; + + union + { + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ + + struct + { + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; + }; + + union + { + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ + + struct + { + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; + }; + + union + { + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ + + struct + { + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; + }; + + union + { + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ + + struct + { + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; + }; + + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ + + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; + + union + { + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ + + struct + { + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; + }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ + + struct + { + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; + }; + + union + { + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ + + struct + { + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; + }; + + union + { + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ + + struct + { + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; + }; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; + }; + + union + { + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ + + struct + { + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; + }; + + union + { + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ + + struct + { + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; + }; + + union + { + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ + + struct + { + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; + }; + + union + { + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ + + struct + { + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; + }; + + union + { + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ + + struct + { + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; + }; + + union + { + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ + + struct + { + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; + }; + + union + { + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ + + struct + { + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; + }; + + union + { + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ + + struct + { + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ + + struct + { + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; + }; + + union + { + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ + + struct + { + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; + }; + + union + { + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ + + struct + { + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; + }; + + union + { + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ + + struct + { + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; + }; + + union + { + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; + }; + + union + { + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ + + struct + { + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; + }; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ + + struct + { + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ + + struct + { + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; + }; + + union + { + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ + + struct + { + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; + }; + + union + { + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ + + struct + { + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; + }; + + union + { + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ + + struct + { + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; + }; + + union + { + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ + + struct + { + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ + + struct + { + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; + }; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; + }; + + union + { + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED10; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; + }; + + union + { + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; + }; + + union + { + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; + }; + + union + { + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; + }; + + union + { + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; + }; + + union + { + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; + }; + + union + { + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; + }; + + union + { + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; + }; + + union + { + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; + }; + + union + { + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; + }; + + union + { + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; + }; + + union + { + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; + }; + + union + { + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; + }; + + union + { + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; + }; + + union + { + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; + }; + + union + { + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ + + struct + { + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; + }; + + union + { + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ + + struct + { + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; + }; + __IM uint8_t RESERVED13; + + union + { + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ + + struct + { + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; + }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; + + union + { + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; + }; + + union + { + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; + }; + + union + { + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; + }; + + union + { + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; + }; + + union + { + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ + + struct + { + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; + }; + + union + { + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ + + struct + { + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; + }; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ + + struct + { + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ + + struct + { + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; + }; + + union + { + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ + + struct + { + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; + }; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; + + union + { + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ + + struct + { + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; + }; + + union + { + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ + + struct + { + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; + }; + __IM uint32_t RESERVED22[3]; + + union + { + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ + + struct + { + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; + }; + __IM uint16_t RESERVED23; + + union + { + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ + + struct + { + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; + }; + + union + { + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ + + struct + { + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; + }; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; + + union + { + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; + }; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; + }; + + union + { + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ + + struct + { + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; + }; + + union + { + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ + + struct + { + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; + }; + + union + { + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ + + struct + { + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; + }; + + union + { + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ + + struct + { + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; + }; + + union + { + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ + + struct + { + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; + }; + + union + { + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ + + struct + { + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; + }; + + union + { + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ + + struct + { + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; + }; + + union + { + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + + struct + { + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; + }; + + union + { + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + + struct + { + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; + }; + + union + { + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + + struct + { + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; + }; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTW0) + */ + +typedef struct /*!< (@ 0x400E8000) R_AGTW0 Structure */ +{ + union + { + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + + struct + { + __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; + }; + + union + { + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + + struct + { + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; + }; + + union + { + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + + struct + { + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; + }; + + union + { + __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */ + + struct + { + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; + }; + + union + { + __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */ + + struct + { + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; + }; + + union + { + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */ + + struct + { + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */ + + struct + { + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; + }; + + union + { + __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; + }; + + union + { + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */ + + struct + { + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; + }; + + union + { + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000013) AGT Pin Select Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; + }; +} R_AGTW0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ + union + { + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + + struct + { + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; + }; + + union + { + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + + struct + { + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; + }; + + union + { + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + + struct + { + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; + }; + + union + { + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + + struct + { + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; + }; + + union + { + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + + struct + { + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; + }; + + union + { + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; + }; + + union + { + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + + struct + { + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; + }; +} R_CAC_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network (CAN) Module (R_CAN0) + */ + +typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +{ + __IM uint32_t RESERVED[128]; + __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + + union + { + __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 3; + } MKR_b[8]; + }; + + union + { + __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + + struct + { + __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ + __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ + uint32_t : 1; + __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ + __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ + } FIDCR_b[2]; + }; + + union + { + __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ + } MKIVLR_b; + }; + + union + { + union + { + __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ + __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ + __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ + __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ + __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ + __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ + } MIER_b; + }; + + union + { + __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox + * Mode */ + + struct + { + __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ + __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ + __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ + __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ + __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ + __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ + __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ + __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ + __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ + __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ + __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ + __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ + __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ + __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ + __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ + __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ + __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ + __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ + __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ + __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ + __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ + __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ + __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ + __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ + __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ + __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ + __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ + uint32_t : 2; + } MIER_FIFO_b; + }; + }; + __IM uint32_t RESERVED1[252]; + + union + { + union + { + __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ + + struct + { + __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ + __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox + * setting enabled) */ + __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting + * enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_TX_b[32]; + }; + + union + { + __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ + + struct + { + __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ + __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting + * enabled) */ + __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ + uint8_t : 1; + __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ + uint8_t : 1; + __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ + __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ + } MCTL_RX_b[32]; + }; + }; + + union + { + __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + + struct + { + __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ + __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ + __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ + __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ + __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ + __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ + __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ + __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ + __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ + __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ + uint16_t : 2; + } CTLR_b; + }; + + union + { + __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + + struct + { + __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ + __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ + __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ + __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ + __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ + __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ + __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ + __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ + __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ + __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ + __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ + __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ + __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ + __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ + __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ + uint16_t : 1; + } STR_b; + }; + + union + { + __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + + struct + { + __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ + uint32_t : 7; + __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ + uint32_t : 1; + __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ + uint32_t : 2; + __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the + * frequency of the CAN communication clock (fCANCLK). */ + uint32_t : 2; + __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ + } BCR_b; + }; + + union + { + __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + + struct + { + __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ + __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ + __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ + __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ + __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ + __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ + } RFCR_b; + }; + + union + { + __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + + struct + { + __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented + * by writing FFh to RFPCR. */ + } RFPCR_b; + }; + + union + { + __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + + struct + { + __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ + __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ + uint8_t : 2; + __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ + __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ + } TFCR_b; + }; + + union + { + __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + + struct + { + __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented + * by writing FFh to TFPCR. */ + } TFPCR_b; + }; + + union + { + __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + + struct + { + __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ + __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ + __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ + __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ + __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ + __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ + __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ + __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ + } EIER_b; + }; + + union + { + __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + + struct + { + __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ + __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ + __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ + __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ + __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ + __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ + __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ + __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ + } EIFR_b; + }; + + union + { + __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + + struct + { + __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements + * the counter value according to the error status of the + * CAN module during reception. */ + } RECR_b; + }; + + union + { + __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + + struct + { + __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements + * the counter value according to the error status of the + * CAN module during transmission. */ + } TECR_b; + }; + + union + { + __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + + struct + { + __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ + __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ + __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ + __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ + __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ + __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ + __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ + __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ + } ECSR_b; + }; + + union + { + __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + + struct + { + __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel + * number is output to MSSR. */ + } CSSR_b; + }; + + union + { + __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + + struct + { + __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output + * the smallest mailbox number that is searched in each mode + * of MSMR. */ + uint8_t : 2; + __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ + } MSSR_b; + }; + + union + { + __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + + struct + { + __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ + uint8_t : 6; + } MSMR_b; + }; + + union + { + __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + + struct + { + __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ + } TSR_b; + }; + + union + { + __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + + struct + { + __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, + * the value converted for data table search can be read. */ + } AFSR_b; + }; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + + struct + { + __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ + __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ + uint8_t : 5; + } TCR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED[25]; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 2; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ + uint32_t : 14; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ + __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + uint32_t : 1; + __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ + __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ + uint32_t : 6; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement + * Registers */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; + + union + { + __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint32_t RESERVED6[18]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint32_t RESERVED8[288]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint32_t RESERVED9[288]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ + uint32_t : 24; + } CFDTMTRSTS_b[4]; + }; + __IM uint32_t RESERVED10[36]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 24; + } CFDTMTARSTS_b[4]; + }; + __IM uint32_t RESERVED11[36]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 24; + } CFDTMTCSTS_b[4]; + }; + __IM uint32_t RESERVED12[36]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ + uint32_t : 24; + } CFDTMTASTS_b[4]; + }; + __IM uint32_t RESERVED13[36]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ + uint32_t : 24; + } CFDTMIEC_b[4]; + }; + __IM uint32_t RESERVED14[40]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS0_b[2]; + }; + __IM uint32_t RESERVED16[6]; + + union + { + __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS1_b[2]; + }; + __IM uint32_t RESERVED19[6]; + + union + { + __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint32_t RESERVED20[6]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + uint32_t : 3; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + uint32_t : 12; + } CFDTXQSTS2_b[2]; + }; + __IM uint32_t RESERVED22[6]; + + union + { + __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint32_t RESERVED24[6]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 13; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; + + union + { + __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint32_t RESERVED26[6]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint32_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint32_t RESERVED29[6]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint32_t RESERVED30[6]; + + union + { + __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint32_t RESERVED31[46]; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + + union + { + __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */ + + struct + { + __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */ + uint32_t : 31; + } CFDGCRCCFG_b; + }; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + + union + { + __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ + + struct + { + __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ + uint32_t : 7; + __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ + __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ + __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ + __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ + uint32_t : 16; + } CFDGLOTB_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ + uint32_t : 7; + __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ + uint32_t : 13; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + __IM uint32_t RESERVED34; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint32_t RESERVED37[10]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED38[31]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED39[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED40[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED41[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED42[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED43[252]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED44[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFDL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFDL) + */ + +typedef struct /*!< (@ 0x400B0000) R_CANFDL Structure */ +{ + __IOM R_CANFDL_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000014) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + uint32_t : 3; + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000018) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 4; + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000001C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000020) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ + uint32_t : 12; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + uint32_t : 15; + } CFDGERFL_b; + }; + + union + { + __IOM uint32_t CFDGTSC; /*!< (@ 0x00000024) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x00000030) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x00000034) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + + union + { + __IOM uint32_t CFDRMIEC; /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t RMIE : 32; /*!< [31..0] RX Message Buffer Interrupt Enable */ + } CFDRMIEC_b; + }; + + union + { + __IOM uint32_t CFDRFCC[2]; /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + uint32_t : 16; + } CFDRFCC_b[2]; + }; + + union + { + __IOM uint32_t CFDRFSTS[2]; /*!< (@ 0x00000044) RX FIFO Status Registers */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + uint32_t : 16; + } CFDRFSTS_b[2]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[2]; /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[2]; + }; + + union + { + __IOM uint32_t CFDCFCC[1]; /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[1]; + }; + + union + { + __IOM uint32_t CFDCFSTS[1]; /*!< (@ 0x00000058) Common FIFO Status Registers */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + uint32_t : 16; + } CFDCFSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDCFPCTR[1]; /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[1]; + }; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x00000060) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 2; /*!< [1..0] RX FIF0 Empty Status */ + uint32_t : 6; + __IM uint32_t CFXEMP : 1; /*!< [8..8] Common FIF0 Empty Status */ + uint32_t : 23; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x00000064) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 2; /*!< [1..0] RX FIF0 Full Status */ + uint32_t : 6; + __IM uint32_t CFXFLL : 1; /*!< [8..8] Common FIF0 Full Status */ + uint32_t : 23; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x00000068) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 2; /*!< [1..0] RX FIFO Msg Lost Status */ + uint32_t : 6; + __IM uint32_t CFXMLT : 1; /*!< [8..8] Common FIFO Msg Lost Status */ + uint32_t : 23; + } CFDFMSTS_b; + }; + + union + { + __IOM uint32_t CFDRFISTS; /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 1; /*!< [0..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 31; + } CFDRFISTS_b; + }; + + union + { + __IOM uint8_t CFDTMC[4]; /*!< (@ 0x00000070) TX Message Buffer Control Registers */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[4]; + }; + + union + { + __IOM uint8_t CFDTMSTS[4]; /*!< (@ 0x00000074) TX Message Buffer Status Registers */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[4]; + }; + + union + { + __IM uint32_t CFDTMTRSTS[1]; /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status + * Register */ + + struct + { + __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status */ + uint32_t : 28; + } CFDTMTRSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTARSTS[1]; /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request + * Status Register */ + + struct + { + __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status */ + uint32_t : 28; + } CFDTMTARSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTCSTS[1]; /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status + * Register */ + + struct + { + __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 28; + } CFDTMTCSTS_b[1]; + }; + + union + { + __IM uint32_t CFDTMTASTS[1]; /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register */ + + struct + { + __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status */ + uint32_t : 28; + } CFDTMTASTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTMIEC[1]; /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration + * Register */ + + struct + { + __IOM uint32_t TMIEg : 4; /*!< [3..0] TX Message Buffer Interrupt Enable */ + uint32_t : 28; + } CFDTMIEC_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQCC0[1]; /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0 */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 4; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 2; /*!< [9..8] TX Queue Depth Configuration */ + uint32_t : 22; + } CFDTXQCC0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQSTS0[1]; /*!< (@ 0x00000090) TX Queue Status Registers 0 */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 18; + } CFDTXQSTS0_b[1]; + }; + + union + { + __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0 */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLCC[1]; /*!< (@ 0x00000098) TX History List Configuration / Control Register */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + uint32_t : 21; + } CFDTHLCC_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLSTS[1]; /*!< (@ 0x0000009C) TX History List Status Register */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[1]; + }; + + union + { + __IOM uint32_t CFDTHLPCTR[1]; /*!< (@ 0x000000A0) TX History List Pointer Control Registers */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[1]; + }; + + union + { + __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + uint32_t : 27; + } CFDGTINTSTS0_b; + }; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x000000A8) Global Test Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x000000AC) Global Test Control Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x000000B0) Global FD Configuration register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t CFDGLOCKK; /*!< (@ 0x000000B8) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x000000C0) Global AFL Ignore Entry Register */ + + struct + { + __IOM uint32_t IRN : 5; /*!< [4..0] Ignore Rule Number */ + uint32_t : 27; + } CFDGAFLIGNENT_b; + }; + + union + { + __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x000000C4) Global AFL Ignore Control Register */ + + struct + { + __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGAFLIGNCTR_b; + }; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x000000C8) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ + uint32_t : 23; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x000000CC) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel + * 0 */ + uint32_t : 23; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x000000D8) Global SW reset Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFDL_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFDL_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED6[104]; + __IOM R_CANFDL_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFDL_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFDL_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFDL_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFDL_CFDRMC_Type CFDRMC[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFDL_Type; /*!< Size = 6432 (0x1920) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC) + */ + +typedef struct /*!< (@ 0x40108000) R_CRC Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + + union + { + __IOM uint8_t CRCCR1; /*!< (@ 0x00000001) CRC Control Register1 */ + + struct + { + uint8_t : 6; + __IOM uint8_t CRCSWR : 1; /*!< [6..6] Snoop-on-write/read switch bit */ + __IOM uint8_t CRCSEN : 1; /*!< [7..7] Snoop enable bit */ + } CRCCR1_b; + }; + __IM uint16_t RESERVED; + + union + { + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + + struct + { + __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C ) */ + } CRCDIR_b; + }; + + union + { + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register (byte access) */ + + struct + { + __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT + * ) */ + } CRCDIR_BY_b; + }; + }; + + union + { + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + + struct + { + __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C ) */ + } CRCDOR_b; + }; + + union + { + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register (halfword access) */ + + struct + { + __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT + * ) */ + } CRCDOR_HA_b; + }; + + union + { + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register(byte access) */ + + struct + { + __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 ) */ + } CRCDOR_BY_b; + }; + }; + + union + { + __IOM uint16_t CRCSAR; /*!< (@ 0x0000000C) Snoop Address Register */ + + struct + { + __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop */ + uint16_t : 2; + } CRCSAR_b; + }; + __IM uint16_t RESERVED1; +} R_CRC_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief D/A Converter (R_DAC) + */ + +typedef struct /*!< (@ 0x40172000) R_DAC Structure */ +{ + union + { + __IOM uint16_t DADR[2]; /*!< (@ 0x00000000) D/A Data Register */ + + struct + { + __IOM uint16_t DADR : 16; /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order + * 4 bits are fixed to 0: right justified format. When DADPR.DPSEL + * = 1, the low-order 4 bits are fixed to 0: left justified + * format. */ + } DADR_b[2]; + }; + + union + { + __IOM uint8_t DACR; /*!< (@ 0x00000004) D/A Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t DAE : 1; /*!< [5..5] D/A Enable */ + __IOM uint8_t DAOE0 : 1; /*!< [6..6] D/A Output Enable 0 */ + __IOM uint8_t DAOE1 : 1; /*!< [7..7] D/A Output Enable 0 */ + } DACR_b; + }; + + union + { + __IOM uint8_t DADPR; /*!< (@ 0x00000005) DADR0 Format Select Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DPSEL : 1; /*!< [7..7] DADRm Format Select */ + } DADPR_b; + }; + + union + { + __IOM uint8_t DAADSCR; /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t DAADST : 1; /*!< [7..7] D/A-A/D Synchronous Conversion */ + } DAADSCR_b; + }; + + union + { + __IOM uint8_t DAVREFCR; /*!< (@ 0x00000007) D/A VREF Control Register */ + + struct + { + __IOM uint8_t REF : 3; /*!< [2..0] D/A Reference Voltage Select */ + uint8_t : 5; + } DAVREFCR_b; + }; + + union + { + __IOM uint8_t DAAMPCR; /*!< (@ 0x00000008) D/A Output Amplifier Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAAMP0 : 1; /*!< [6..6] Amplifier Control */ + __IOM uint8_t DAAMP1 : 1; /*!< [7..7] Amplifier Control */ + } DAAMPCR_b; + }; + + union + { + __IOM uint8_t DAPC; /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register */ + + struct + { + __IOM uint8_t PUMPEN : 1; /*!< [0..0] Charge Pump Enable */ + uint8_t : 7; + } DAPC_b; + }; + __IM uint16_t RESERVED[9]; + + union + { + __IOM uint8_t DAASWCR; /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t DAASW0 : 1; /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 0. When DAASW0 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 0. When the DAASW0 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 0 is output + * through the output amplifier. */ + __IOM uint8_t DAASW1 : 1; /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure + * to wait for stabilization of the output amplifier of D/A + * channel 1. When DAASW1 is set to 1, D/A conversion operates, + * but the conversion result D/A is not output from channel + * 1. When the DAASW1 bit is 0, the stabilization wait time + * stops, and the D/A conversion result of channel 1 is output + * through the output amplifier. */ + } DAASWCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[2129]; + + union + { + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [1] to 1 to + * select unit 1 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + uint8_t : 1; + } DAADUSR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DAC_Type; /*!< Size = 4292 (0x10c4) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Debug Function (R_DEBUG) + */ + +typedef struct /*!< (@ 0x4001B000) R_DEBUG Structure */ +{ + union + { + __IM uint32_t DBGSTR; /*!< (@ 0x00000000) Debug Status Register */ + + struct + { + uint32_t : 28; + __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request */ + __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge */ + uint32_t : 2; + } DBGSTR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DBGSTOPCR; /*!< (@ 0x00000010) Debug Stop Control Register */ + + struct + { + __IOM uint32_t DBGSTOP_IWDT : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt */ + __IOM uint32_t DBGSTOP_WDT : 1; /*!< [1..1] Mask bit for WDT reset/interrupt */ + uint32_t : 14; + __IOM uint32_t DBGSTOP_LVD0 : 1; /*!< [16..16] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD1 : 1; /*!< [17..17] Mask bit for LVD reset/interupt */ + __IOM uint32_t DBGSTOP_LVD2 : 1; /*!< [18..18] Mask bit for LVD reset/interupt */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_RPER : 1; /*!< [24..24] Mask bit for SRAM parity error */ + __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error */ + uint32_t : 5; + __IOM uint32_t DBGSTOP_CPER : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt */ + } DBGSTOPCR_b; + }; +} R_DEBUG_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller Common (R_DMA) + */ + +typedef struct /*!< (@ 0x40005200) R_DMA Structure */ +{ + union + { + __IOM uint8_t DMAST; /*!< (@ 0x00000000) DMAC Module Activation Register */ + + struct + { + __IOM uint8_t DMST : 1; /*!< [0..0] DMAC Operation Enable */ + uint8_t : 7; + } DMAST_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[15]; + + union + { + __IOM uint32_t DMECHR; /*!< (@ 0x00000040) DMAC Error Channel Register */ + + struct + { + __IM uint32_t DMECH : 3; /*!< [2..0] DMAC Error channel */ + uint32_t : 5; + __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor */ + uint32_t : 7; + __IOM uint32_t DMESTA : 1; /*!< [16..16] DMAC Error Status */ + uint32_t : 15; + } DMECHR_b; + }; +} R_DMA_Type; /*!< Size = 68 (0x44) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller (R_DMAC0) + */ + +typedef struct /*!< (@ 0x40005000) R_DMAC0 Structure */ +{ + union + { + __IOM uint32_t DMSAR; /*!< (@ 0x00000000) DMA Source Address Register */ + + struct + { + __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address. */ + } DMSAR_b; + }; + + union + { + __IOM uint32_t DMDAR; /*!< (@ 0x00000004) DMA Destination Address Register */ + + struct + { + __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address. */ + } DMDAR_b; + }; + + union + { + __IOM uint32_t DMCRA; /*!< (@ 0x00000008) DMA Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count */ + __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count */ + uint32_t : 6; + } DMCRA_b; + }; + + union + { + __IOM uint32_t DMCRB; /*!< (@ 0x0000000C) DMA Block Transfer Count Register */ + + struct + { + __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block + * transfer counter. */ + __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or + * repeat transfer operations. */ + } DMCRB_b; + }; + + union + { + __IOM uint16_t DMTMD; /*!< (@ 0x00000010) DMA Transfer Mode Register */ + + struct + { + __IOM uint16_t DCTG : 2; /*!< [1..0] Transfer Request Source Select */ + uint16_t : 6; + __IOM uint16_t SZ : 2; /*!< [9..8] Transfer Data Size Select */ + __IOM uint16_t TKP : 1; /*!< [10..10] Transfer Keeping */ + uint16_t : 1; + __IOM uint16_t DTS : 2; /*!< [13..12] Repeat Area Select */ + __IOM uint16_t MD : 2; /*!< [15..14] Transfer Mode Select */ + } DMTMD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t DMINT; /*!< (@ 0x00000013) DMA Interrupt Setting Register */ + + struct + { + __IOM uint8_t DARIE : 1; /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t SARIE : 1; /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt + * Enable */ + __IOM uint8_t RPTIE : 1; /*!< [2..2] Repeat Size End Interrupt Enable */ + __IOM uint8_t ESIE : 1; /*!< [3..3] Transfer Escape End Interrupt Enable */ + __IOM uint8_t DTIE : 1; /*!< [4..4] Transfer End Interrupt Enable */ + uint8_t : 3; + } DMINT_b; + }; + + union + { + __IOM uint16_t DMAMD; /*!< (@ 0x00000014) DMA Address Mode Register */ + + struct + { + __IOM uint16_t DARA : 5; /*!< [4..0] Destination Address Extended Repeat Area Specifies the + * extended repeat area on the destination address. For details + * on the settings. */ + __IOM uint16_t DADR : 1; /*!< [5..5] Destination Address Update Select After Reload */ + __IOM uint16_t DM : 2; /*!< [7..6] Destination Address Update Mode */ + __IOM uint16_t SARA : 5; /*!< [12..8] Source Address Extended Repeat Area Specifies the extended + * repeat area on the source address. For details on the settings. */ + __IOM uint16_t SADR : 1; /*!< [13..13] Source Address Update Select After Reload */ + __IOM uint16_t SM : 2; /*!< [15..14] Source Address Update Mode */ + } DMAMD_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DMOFR; /*!< (@ 0x00000018) DMA Offset Register */ + + struct + { + __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected + * as the address update mode for transfer source or destination. */ + } DMOFR_b; + }; + + union + { + __IOM uint8_t DMCNT; /*!< (@ 0x0000001C) DMA Transfer Enable Register */ + + struct + { + __IOM uint8_t DTE : 1; /*!< [0..0] DMA Transfer Enable */ + uint8_t : 7; + } DMCNT_b; + }; + + union + { + __IOM uint8_t DMREQ; /*!< (@ 0x0000001D) DMA Software Start Register */ + + struct + { + __IOM uint8_t SWREQ : 1; /*!< [0..0] DMA Software Start */ + uint8_t : 3; + __IOM uint8_t CLRS : 1; /*!< [4..4] DMA Software Start Bit Auto Clear Select */ + uint8_t : 3; + } DMREQ_b; + }; + + union + { + __IOM uint8_t DMSTS; /*!< (@ 0x0000001E) DMA Status Register */ + + struct + { + __IOM uint8_t ESIF : 1; /*!< [0..0] Transfer Escape End Interrupt Flag */ + uint8_t : 3; + __IOM uint8_t DTIF : 1; /*!< [4..4] Transfer End Interrupt Flag */ + uint8_t : 2; + __IM uint8_t ACT : 1; /*!< [7..7] DMA Active Flag */ + } DMSTS_b; + }; + __IM uint8_t RESERVED2; + __IOM uint32_t DMSRR; /*!< (@ 0x00000020) DMA Source Reload Address Register */ + __IOM uint32_t DMDRR; /*!< (@ 0x00000024) DMA Destination Reload Address Register */ + + union + { + __IOM uint32_t DMSBS; /*!< (@ 0x00000028) DMA Source Buffer Size Register */ + + struct + { + __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMSBS_b; + }; + + union + { + __IOM uint32_t DMDBS; /*!< (@ 0x0000002C) DMA Destination Buffer Size Register */ + + struct + { + __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer + * mode */ + __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer + * mode */ + } DMDBS_b; + }; + + union + { + __IOM uint8_t DMBWR; /*!< (@ 0x00000030) DMA Bufferable Write Enable Register */ + + struct + { + __IOM uint8_t BWE : 1; /*!< [0..0] Bufferable Write Enable */ + uint8_t : 7; + } DMBWR_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; +} R_DMAC0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Transfer Controller (R_DTC) + */ + +typedef struct /*!< (@ 0x40005400) R_DTC Structure */ +{ + union + { + __IOM uint8_t DTCCR; /*!< (@ 0x00000000) DTC Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable. */ + uint8_t : 3; + } DTCCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t DTCVBR; /*!< (@ 0x00000004) DTC Vector Base Register */ + + struct + { + __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set + * in the lower-order 10 bits. These bits are fixed to 0. */ + } DTCVBR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint8_t DTCST; /*!< (@ 0x0000000C) DTC Module Start Register */ + + struct + { + __IOM uint8_t DTCST : 1; /*!< [0..0] DTC Module Start */ + uint8_t : 7; + } DTCST_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IM uint16_t DTCSTS; /*!< (@ 0x0000000E) DTC Status Register */ + + struct + { + __IM uint16_t VECN : 8; /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate + * the vector number for the activating source when DTC transfer + * is in progress.The value is only valid if DTC transfer + * is in progress (the value of the ACT flag is 1) */ + uint16_t : 7; + __IM uint16_t ACT : 1; /*!< [15..15] DTC Active Flag */ + } DTCSTS_b; + }; + + union + { + __IOM uint8_t DTCCR_SEC; /*!< (@ 0x00000010) DTC Control Register for secure Region */ + + struct + { + uint8_t : 4; + __IOM uint8_t RRSS : 1; /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure */ + uint8_t : 3; + } DTCCR_SEC_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DTCVBR_SEC; /*!< (@ 0x00000014) DTC Vector Base Register for secure Region */ + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t DTEVR; /*!< (@ 0x00000020) DTC Error Vector Register */ + + struct + { + __IM uint32_t DTEV : 8; /*!< [7..0] DTC Error Vector Number */ + __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor */ + uint32_t : 7; + __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag */ + uint32_t : 15; + } DTEVR_b; + }; +} R_DTC_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Event Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x40082000) R_ELC Structure */ +{ + union + { + __IOM uint8_t ELCR; /*!< (@ 0x00000000) Event Link Controller Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t ELCON : 1; /*!< [7..7] All Event Link Enable */ + } ELCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register */ + __IM uint32_t RESERVED2[6]; + __IOM R_ELC_ELSR_Type ELSR[30]; /*!< (@ 0x00000020) Event Link Setting Register [0..29] */ + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t ELCSARA; /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register + * A */ + + struct + { + __IOM uint32_t ELCR : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution */ + __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security + * Attribution */ + __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security + * Attribution */ + uint32_t : 29; + } ELCSARA_b; + }; + + union + { + __IOM uint32_t ELCSARB; /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register + * B */ + + struct + { + __IOM uint32_t ELSR0 : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution */ + __IOM uint32_t ELSR1 : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution */ + __IOM uint32_t ELSR2 : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution */ + __IOM uint32_t ELSR3 : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution */ + __IOM uint32_t ELSR4 : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution */ + __IOM uint32_t ELSR5 : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution */ + __IOM uint32_t ELSR6 : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution */ + __IOM uint32_t ELSR7 : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution */ + __IOM uint32_t ELSR8 : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution */ + __IOM uint32_t ELSR9 : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution */ + __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution */ + __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution */ + __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution */ + __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution */ + __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution */ + __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 15Security Attribution */ + uint32_t : 1; + __IOM uint32_t ELSR19 : 1; /*!< [19..19] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR20 : 1; /*!< [20..20] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR21 : 1; /*!< [21..21] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR22 : 1; /*!< [22..22] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR23 : 1; /*!< [23..23] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR24 : 1; /*!< [24..24] Event Link Setting Register 15Security Attribution */ + uint32_t : 3; + __IOM uint32_t ELSR28 : 1; /*!< [28..28] Event Link Setting Register 15Security Attribution */ + __IOM uint32_t ELSR29 : 1; /*!< [29..29] Event Link Setting Register 15Security Attribution */ + uint32_t : 2; + } ELCSARB_b; + }; +} R_ELC_Type; /*!< Size = 232 (0xe8) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD) + */ + +typedef struct /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure */ +{ + union + { + __IOM uint16_t FACI_CMD16; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + __IOM uint8_t FACI_CMD8; /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access) */ + }; +} R_FACI_HP_CMD_Type; /*!< Size = 2 (0x2) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Application Command Interface (R_FACI_HP) + */ + +typedef struct /*!< (@ 0x407FE000) R_FACI_HP Structure */ +{ + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint8_t FASTAT; /*!< (@ 0x00000010) Flash Access Status */ + + struct + { + __IM uint8_t ECRCT : 1; /*!< [0..0] ECRCT */ + uint8_t : 2; + __IOM uint8_t DFAE : 1; /*!< [3..3] Data Flash Access Error */ + __IM uint8_t CMDLK : 1; /*!< [4..4] Command Lock */ + uint8_t : 2; + __IOM uint8_t CFAE : 1; /*!< [7..7] Code Flash Access Error */ + } FASTAT_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t FAEINT; /*!< (@ 0x00000014) Flash Access Error Interrupt Enable */ + + struct + { + __IOM uint8_t ECRCTIE : 1; /*!< [0..0] Error Correct Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t DFAEIE : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable */ + __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t CFAEIE : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable */ + } FAEINT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + + union + { + __IOM uint8_t FRDYIE; /*!< (@ 0x00000018) Flash Ready Interrupt Enable */ + + struct + { + __IOM uint8_t FRDYIE : 1; /*!< [0..0] FRDY Interrupt Enable */ + uint8_t : 7; + } FRDYIE_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[5]; + + union + { + __IOM uint32_t FSADDR; /*!< (@ 0x00000030) Flash Start Address */ + + struct + { + __IOM uint32_t FSA : 32; /*!< [31..0] Start Address of Flash Sequencer Command Target Area + * These bits can be written when FRDY bit of FSTATR register + * is '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FSADDR_b; + }; + + union + { + __IOM uint32_t FEADDR; /*!< (@ 0x00000034) Flash End Address */ + + struct + { + __IOM uint32_t FEA : 32; /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies + * end address of target area in 'Blank Check' command. These + * bits can be written when FRDY bit of FSTATR register is + * '1'. Writing to these bits in FRDY = '0' is ignored. */ + } FEADDR_b; + }; + __IM uint32_t RESERVED8[3]; + + union + { + __IOM uint16_t FMEPROT; /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register */ + + struct + { + __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY bits is D9h.Written values + * are not retained by these bits (always read as 0x00).Only + * secure access can write to this register. Both secure access + * and non-secure read access are allowed. Non-secure writeaccess + * is denied, but Trust */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FMEPROT_b; + }; + __IM uint16_t RESERVED9; + __IM uint32_t RESERVED10[12]; + + union + { + __IOM uint16_t FBPROT0; /*!< (@ 0x00000078) Flash Block Protection Register */ + + struct + { + __IOM uint16_t BPCN0 : 1; /*!< [0..0] Block Protection for Non-secure CancelThis bit can be + * written when the FRDY bit in the FSTATR register is 1. + * Writing to this bit is ignored when the FRDY bit is 0.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0x78.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT0_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IOM uint16_t FBPROT1; /*!< (@ 0x0000007C) Flash Block Protection for Secure Register */ + + struct + { + __IOM uint16_t BPCN1 : 1; /*!< [0..0] Block Protection for Secure CancelWriting to this bit + * is only possible when the FRDY bit in the FSTATR register + * is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing + * to this bit is only possible when 16 bits are written and + * the value written to the KEY[7:0] bits is 0xB1.Written + * values are not retained by these bits (always read as 0x00). */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FBPROT1_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IM uint32_t FSTATR; /*!< (@ 0x00000080) Flash Status */ + + struct + { + uint32_t : 6; + __IM uint32_t FLWEERR : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag */ + uint32_t : 1; + __IM uint32_t PRGSPD : 1; /*!< [8..8] Programming-Suspended Status */ + __IM uint32_t ERSSPD : 1; /*!< [9..9] Erasure-Suspended Status */ + __IM uint32_t DBFULL : 1; /*!< [10..10] Data Buffer Full */ + __IM uint32_t SUSRDY : 1; /*!< [11..11] Suspend Ready */ + __IM uint32_t PRGERR : 1; /*!< [12..12] Programming Error */ + __IM uint32_t ERSERR : 1; /*!< [13..13] Erasure Error */ + __IM uint32_t ILGLERR : 1; /*!< [14..14] Illegal Command Error */ + __IM uint32_t FRDY : 1; /*!< [15..15] Flash Ready */ + uint32_t : 4; + __IM uint32_t OTERR : 1; /*!< [20..20] Other Error */ + __IOM uint32_t SECERR : 1; /*!< [21..21] Security Error */ + __IM uint32_t FESETERR : 1; /*!< [22..22] FENTRY Setting Error */ + __IM uint32_t ILGCOMERR : 1; /*!< [23..23] Illegal Command Error */ + uint32_t : 8; + } FSTATR_b; + }; + + union + { + __IOM uint16_t FENTRYR; /*!< (@ 0x00000084) Program/Erase Mode Entry */ + + struct + { + __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits */ + uint16_t : 6; + __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when + * FRDY bit in FSTATR register is '1'. Writing to this bit + * in FRDY = '0' is ignored. Writing to these bits is enabled + * only when this register is accessed in 16-bit size and + * H'AA is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FENTRYR_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14; + + union + { + __IOM uint16_t FSUINITR; /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize */ + + struct + { + __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY + * bit of FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'2D + * is written to KEY bits. */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUINITR_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[4]; + + union + { + __IM uint16_t FCMDR; /*!< (@ 0x000000A0) Flash Sequencer Command */ + + struct + { + __IM uint16_t PCMDR : 8; /*!< [7..0] Previous Command Register */ + __IM uint16_t CMDR : 8; /*!< [15..8] Command Register */ + } FCMDR_b; + }; + __IM uint16_t RESERVED17; + __IM uint32_t RESERVED18[7]; + + union + { + __IM uint16_t FPESTAT; /*!< (@ 0x000000C0) Program/Erase Error Status */ + + struct + { + __IM uint16_t PEERRST : 8; /*!< [7..0] P/E Error Status */ + uint16_t : 8; + } FPESTAT_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20[3]; + + union + { + __IOM uint8_t FBCCNT; /*!< (@ 0x000000D0) Blank Check Control */ + + struct + { + __IOM uint8_t BCDIR : 1; /*!< [0..0] Blank Check Direction */ + uint8_t : 7; + } FBCCNT_b; + }; + __IM uint8_t RESERVED21; + __IM uint16_t RESERVED22; + + union + { + __IM uint8_t FBCSTAT; /*!< (@ 0x000000D4) Blank Check Status */ + + struct + { + __IM uint8_t BCST : 1; /*!< [0..0] Blank Check Status Bit */ + uint8_t : 7; + } FBCSTAT_b; + }; + __IM uint8_t RESERVED23; + __IM uint16_t RESERVED24; + + union + { + __IM uint32_t FPSADDR; /*!< (@ 0x000000D8) Programmed Area Start Address */ + + struct + { + __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address + * of the first programmed data which is found in 'Blank Check' + * command execution. */ + uint32_t : 13; + } FPSADDR_b; + }; + + union + { + __IM uint32_t FAWMON; /*!< (@ 0x000000DC) Flash Access Window Monitor */ + + struct + { + __IM uint32_t FAWS : 11; /*!< [10..0] Start Sector Address for Access Window NOTE: These bits + * indicate the start sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t FSPR : 1; /*!< [15..15] Protection Flag of programming the Access Window, Boot + * Flag and Temporary Boot Swap Control and 'Config Clear' + * command execution */ + __IM uint32_t FAWE : 11; /*!< [26..16] End Sector Address for Access Window NOTE: These bits + * indicate the end sector address for setting the access + * window that is located in the configuration area. */ + uint32_t : 4; + __IM uint32_t BTFLG : 1; /*!< [31..31] Flag of Start-Up area select for Boot Swap */ + } FAWMON_b; + }; + + union + { + __IOM uint16_t FCPSR; /*!< (@ 0x000000E0) FCU Process Switch */ + + struct + { + __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode */ + uint16_t : 15; + } FCPSR_b; + }; + __IM uint16_t RESERVED25; + + union + { + __IOM uint16_t FPCKAR; /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification */ + + struct + { + __IOM uint16_t PCKA : 8; /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits + * can be written when FRDY bit in FSTATR register is '1'. + * Writing to this bit in FRDY = '0' is ignored. Writing to + * these bits is enabled only when this register is accessed + * in 16-bit size and H'1E is written to KEY bits. */ + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FPCKAR_b; + }; + __IM uint16_t RESERVED26; + + union + { + __IOM uint16_t FSUACR; /*!< (@ 0x000000E8) Flash Start-Up Area Control Register */ + + struct + { + __IOM uint16_t SAS : 2; /*!< [1..0] Start Up Area Select These bits can be written when FRDY + * bit in FSTATR register is '1'. Writing to this bit in FRDY + * = '0' is ignored. Writing to these bits is enabled only + * when this register is accessed in 16-bit size and H'66 + * is written to KEY bits. */ + uint16_t : 6; + __OM uint16_t KEY : 8; /*!< [15..8] KEY Code */ + } FSUACR_b; + }; + __IM uint16_t RESERVED27; +} R_FACI_HP_Type; /*!< Size = 236 (0xec) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Flash Memory Cache (R_FCACHE) + */ + +typedef struct /*!< (@ 0x4001C000) R_FCACHE Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint16_t FCACHEE; /*!< (@ 0x00000100) Flash Cache Enable Register */ + + struct + { + __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable */ + uint16_t : 15; + } FCACHEE_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t FCACHEIV; /*!< (@ 0x00000104) Flash Cache Invalidate Register */ + + struct + { + __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register */ + uint16_t : 15; + } FCACHEIV_b; + }; + __IM uint16_t RESERVED2[11]; + + union + { + __IOM uint8_t FLWT; /*!< (@ 0x0000011C) Flash Wait Cycle Register */ + + struct + { + __IOM uint8_t FLWT : 3; /*!< [2..0] Flash Wait Cycle */ + uint8_t : 5; + } FLWT_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[17]; + + union + { + __IOM uint16_t FSAR; /*!< (@ 0x00000140) Flash Security Attribution Register */ + + struct + { + __IOM uint16_t FLWTSA : 1; /*!< [0..0] FLWT Security Attribution */ + uint16_t : 7; + __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution */ + uint16_t : 7; + } FSAR_b; + }; +} R_FCACHE_Type; /*!< Size = 322 (0x142) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer (R_GPT0) + */ + +typedef struct /*!< (@ 0x40169000) R_GPT0 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disable */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disable */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disable */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disable */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT7 : 1; /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT8 : 1; /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT9 : 1; /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter stop. 1 + * means counter running. */ + uint32_t : 18; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP7 : 1; /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP8 : 1; /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP9 : 1; /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's + * counter status (GTCR.CST bit). 0 means counter runnning. + * 1 means counter stop. */ + uint32_t : 18; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel GTCNT Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel GTCNT Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel GTCNT Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel GTCNT Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel GTCNT Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel GTCNT Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel GTCNT Count Clear */ + __OM uint32_t CCLR7 : 1; /*!< [7..7] Channel GTCNT Count Clear */ + __OM uint32_t CCLR8 : 1; /*!< [8..8] Channel GTCNT Count Clear */ + __OM uint32_t CCLR9 : 1; /*!< [9..9] Channel GTCNT Count Clear */ + __OM uint32_t CCLR10 : 1; /*!< [10..10] Channel GTCNT Count Clear */ + __OM uint32_t CCLR11 : 1; /*!< [11..11] Channel GTCNT Count Clear */ + __OM uint32_t CCLR12 : 1; /*!< [12..12] Channel GTCNT Count Clear */ + __OM uint32_t CCLR13 : 1; /*!< [13..13] Channel GTCNT Count Clear */ + uint32_t : 18; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable */ + __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable */ + __IOM uint32_t SSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Start Enable */ + __IOM uint32_t SSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Start Enable */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Start Enable */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Start Enable */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Counter Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable */ + __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable */ + __IOM uint32_t PSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Stop Enable */ + __IOM uint32_t PSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Stop Enable */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] Software Source Counter Stop Enable */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable */ + __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable */ + __IOM uint32_t CSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Clear Enable */ + __IOM uint32_t CSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Clear Enable */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable */ + __IOM uint32_t CSCMSC : 3; /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing + * Source Counter Clear Enable. */ + __IOM uint32_t CP1CCE : 1; /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear + * Enable (This bit is only available in GPT324 to GPT329. + * In GPT320 to GPT323, this bit is read as 0. The write value + * should be 0.) */ + uint32_t : 3; + __IOM uint32_t CCLR : 1; /*!< [31..31] Software Source Counter Clear Enable */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable */ + __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable */ + __IOM uint32_t USCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Up Enable */ + __IOM uint32_t USCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Up Enable */ + __IOM uint32_t USELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable */ + __IOM uint32_t USILVL : 4; /*!< [27..24] External Input Level Source Count-Up Enable */ + uint32_t : 4; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable */ + __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable */ + __IOM uint32_t DSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * Counter Count Down Enable */ + __IOM uint32_t DSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * Counter Count Down Enable */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable */ + __IOM uint32_t DSILVL : 4; /*!< [27..24] External Input Level Source Count-Down Enable */ + uint32_t : 4; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture + * Enable */ + __IOM uint32_t ASCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture + * Enable */ + __IOM uint32_t BSCARBL : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCARBH : 1; /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBL : 1; /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCAFBH : 1; /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAL : 1; /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBRAH : 1; /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAL : 1; /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSCBFAH : 1; /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source + * GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 15; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 5; + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100 + * percent Duty Setting */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCA Pin Function Select */ + __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous + * Clear Disable.(This bit is only available in GPT324 to + * GPT329. In GPT320 to GPT323, this bit is read as 0. The + * write value should be 0.) */ + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting */ + __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + __IOM uint32_t PSYE : 1; /*!< [12..12] PWM Synchronous output Enable */ + __IOM uint32_t NFAEN : 1; /*!< [13..13] Noise Filter A Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] Noise Filter A Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting */ + __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This + * bit is only available in GPT324 to GPT329. In GPT320 to + * GPT323, this bit is read as 0. The write value should be + * 0.) */ + uint32_t : 1; + __IOM uint32_t NFBEN : 1; /*!< [29..29] Noise Filter B Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] Noise Filter B Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + uint32_t : 24; + __IOM uint32_t GRP : 2; /*!< [25..24] Output Disable Source Select */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] Dead Time Error Output Disable Request Enable */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t GTINTPC : 1; /*!< [31..31] Period Count Function Finish Interrupt Enable */ + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + __IOM uint32_t TCFA : 1; /*!< [0..0] Input Capture/Compare Match Flag A */ + __IOM uint32_t TCFB : 1; /*!< [1..1] Input Capture/Compare Match Flag B */ + __IOM uint32_t TCFC : 1; /*!< [2..2] Input Compare Match Flag C */ + __IOM uint32_t TCFD : 1; /*!< [3..3] Input Compare Match Flag D */ + __IOM uint32_t TCFE : 1; /*!< [4..4] Input Compare Match Flag E */ + __IOM uint32_t TCFF : 1; /*!< [5..5] Input Compare Match Flag F */ + __IOM uint32_t TCFPO : 1; /*!< [6..6] Overflow Flag */ + __IOM uint32_t TCFPU : 1; /*!< [7..7] Underflow Flag */ + __IM uint32_t ITCNT : 3; /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter + * for counting the number of times a timer interrupt has + * been skipped.) */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start + * Request Interrupt Enable */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start + * Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor + * Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Disable Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Same Time Output Level High Disable Request Enable */ + __IM uint32_t OABLF : 1; /*!< [30..30] Same Time Output Level Low Disable Request Enable */ + __IOM uint32_t PCF : 1; /*!< [31..31] Period Count Function Finish Flag */ + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD */ + __IOM uint32_t BD3 : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2] */ + uint32_t : 12; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Buffer Operation */ + __OM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit + * is read as 0. */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle + * wavesNOTE: In the Saw waves, values other than 0 0: Transfer + * at an underflow (in down-counting) or overflow (in up-counting) + * is performed. */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLB : 1; /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link */ + __IOM uint32_t ITLC : 1; /*!< [2..2] GTCCRC Compare Match Interrupt Link */ + __IOM uint32_t ITLD : 1; /*!< [3..3] GTCCRD Compare Match Interrupt Link */ + __IOM uint32_t ITLE : 1; /*!< [4..4] GTCCRE Compare Match Interrupt Link */ + __IOM uint32_t ITLF : 1; /*!< [5..5] GTCCRF Compare Match Interrupt Link */ + __IOM uint32_t IVTC : 2; /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select */ + __IOM uint32_t IVTT : 3; /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] GTADTRA A/D Converter Start Request Link */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] GTADTRB A/D Converter Start Request Link */ + uint32_t : 17; + } GTITC_b; + }; + + union + { + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + + struct + { + __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter */ + } GTCNT_b; + }; + + union + { + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register */ + + struct + { + __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A */ + } GTCCR_b[6]; + }; + + union + { + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + + struct + { + __IOM uint32_t GTPR : 32; /*!< [31..0] Cycle Setting Register */ + } GTPR_b; + }; + + union + { + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + + struct + { + __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register */ + } GTPBR_b; + }; + + union + { + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + + struct + { + __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register */ + } GTPDBR_b; + }; + + union + { + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A */ + + struct + { + __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A */ + } GTADTRA_b; + }; + + union + { + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A */ + + struct + { + __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A */ + } GTADTBRA_b; + }; + + union + { + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + + struct + { + __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * A */ + } GTADTDBRA_b; + }; + + union + { + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B */ + + struct + { + __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B */ + } GTADTRB_b; + }; + + union + { + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B */ + + struct + { + __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B */ + } GTADTBRB_b; + }; + + union + { + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + struct + { + __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register + * B */ + } GTADTDBRB_b; + }; + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + + union + { + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U */ + } GTDVU_b; + }; + + union + { + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D */ + + struct + { + __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D */ + } GTDVD_b; + }; + + union + { + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U */ + + struct + { + __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U */ + } GTDBU_b; + }; + + union + { + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D */ + + struct + { + __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D */ + } GTDBD_b; + }; + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + __IM uint32_t RESERVED[5]; + + union + { + __IOM uint32_t GTICLF; /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation + * Function Setting Register */ + + struct + { + __IOM uint32_t ICLFA : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select */ + uint32_t : 6; + __IOM uint32_t ICLFB : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select */ + uint32_t : 1; + __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select */ + uint32_t : 6; + } GTICLF_b; + }; + + union + { + __IOM uint32_t GTPC; /*!< (@ 0x000000BC) General PWM Timer Period Count Register */ + + struct + { + __IOM uint32_t PCEN : 1; /*!< [0..0] Period Count Function Enable */ + uint32_t : 7; + __IOM uint32_t ASTP : 1; /*!< [8..8] Automatic Stop Function Enable */ + uint32_t : 7; + __IOM uint32_t PCNT : 12; /*!< [27..16] Period Counter */ + uint32_t : 4; + } GTPC_b; + }; + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 22; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + uint32_t : 6; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + uint32_t : 6; + __IOM uint32_t SPCE : 1; /*!< [16..16] Period Count Function Simultaneous Enable */ + uint32_t : 7; + __IOM uint32_t SPCD : 1; /*!< [24..24] Period Count Function Simultaneous Disable */ + uint32_t : 7; + } GTSECR_b; + }; +} R_GPT0_Type; /*!< Size = 216 (0xd8) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GTCLK (R_GPT_GTCLK) + */ + +typedef struct /*!< (@ 0x40169B00) R_GPT_GTCLK Structure */ +{ + union + { + __IOM uint32_t GTCLKCR; /*!< (@ 0x00000000) General PWM Timer Clock Control Register */ + + struct + { + __IOM uint32_t BPEN : 1; /*!< [0..0] Synchronization Circuit Bypass Enable */ + uint32_t : 31; + } GTCLKCR_b; + }; +} R_GPT_GTCLK_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief PWM Delay Generation Circuit (R_GPT_ODC) + */ + +typedef struct /*!< (@ 0x4016A000) R_GPT_ODC Structure */ +{ + union + { + __IOM uint16_t GTDLYCR1; /*!< (@ 0x00000000) PWM Output Delay Control Register1 */ + + struct + { + __IOM uint16_t DLLEN : 1; /*!< [0..0] DLL Operation Enable */ + __IOM uint16_t DLYRST : 1; /*!< [1..1] PWM Delay Generation Circuit Reset */ + uint16_t : 6; + __IOM uint16_t FRANGE : 1; /*!< [8..8] GPT core clock Frequency Range */ + uint16_t : 7; + } GTDLYCR1_b; + }; + + union + { + __IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 */ + + struct + { + __IOM uint16_t DLYBS0 : 1; /*!< [0..0] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS1 : 1; /*!< [1..1] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS2 : 1; /*!< [2..2] PWM Delay Generation Circuit bypass */ + __IOM uint16_t DLYBS3 : 1; /*!< [3..3] PWM Delay Generation Circuit bypass */ + uint16_t : 4; + __IOM uint16_t DLYEN0 : 1; /*!< [8..8] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN1 : 1; /*!< [9..9] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN2 : 1; /*!< [10..10] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYEN3 : 1; /*!< [11..11] PWM Delay Generation Circuit enable */ + __IOM uint16_t DLYDENB0 : 1; /*!< [12..12] PWM Delay Generation Circuit Disenable for GTIOCB */ + uint16_t : 3; + } GTDLYCR2_b; + }; + __IM uint16_t RESERVED[10]; + __IOM R_GPT_ODC_GTDLYR_Type GTDLYR[4]; /*!< (@ 0x00000018) PWM DELAY RISING */ + __IOM R_GPT_ODC_GTDLYR_Type GTDLYF[4]; /*!< (@ 0x00000028) PWM DELAY FALLING */ +} R_GPT_ODC_Type; /*!< Size = 56 (0x38) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Output Phase Switching for GPT (R_GPT_OPS) + */ + +typedef struct /*!< (@ 0x40169A00) R_GPT_OPS Structure */ +{ + union + { + __IOM uint32_t OPSCR; /*!< (@ 0x00000000) Output Phase Switching Control Register */ + + struct + { + __IOM uint32_t UF : 1; /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t VF : 1; /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + __IOM uint32_t WF : 1; /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase + * by the software settings.This bit setting is valid when + * the OPSCR.FB bit = 1. */ + uint32_t : 1; + __IM uint32_t U : 1; /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t V : 1; /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + __IM uint32_t W : 1; /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the + * input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa + * e settings (UF/VF/WF) */ + uint32_t : 1; + __IOM uint32_t EN : 1; /*!< [8..8] Enable-Phase Output Control */ + uint32_t : 7; + __IOM uint32_t FB : 1; /*!< [16..16] External Feedback Signal EnableThis bit selects the + * input phase from the software settings and external input. */ + __IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control */ + __IOM uint32_t N : 1; /*!< [18..18] Negative-Phase Output (N) Control */ + __IOM uint32_t INV : 1; /*!< [19..19] Invert-Phase Output Control */ + __IOM uint32_t RV : 1; /*!< [20..20] Output phase rotation direction reversal */ + __IOM uint32_t ALIGN : 1; /*!< [21..21] Input phase alignment */ + uint32_t : 2; + __IOM uint32_t GRP : 2; /*!< [25..24] Output disabled source selection */ + __IOM uint32_t GODF : 1; /*!< [26..26] Group output disable function */ + uint32_t : 2; + __IOM uint32_t NFEN : 1; /*!< [29..29] External Input Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] External Input Noise Filter Clock selectionNoise filter + * sampling clock setting of the external input. */ + } OPSCR_b; + }; +} R_GPT_OPS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable for GPT (R_GPT_POEG0) + */ + +typedef struct /*!< (@ 0x4008A000) R_GPT_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEGG; /*!< (@ 0x00000000) POEG Group Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] Real Time Overcurrent Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection EnableNote: Can be modified only + * once after a reset. */ + __IOM uint32_t IOCE : 1; /*!< [5..5] Enable for GPT Output-Disable RequestNote: Can be modified + * only once after a reset. */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Oscillation Stop Detection EnableNote: Can be modified + * only once after a reset. */ + uint32_t : 1; + __IOM uint32_t CDRE0 : 1; /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE1 : 1; /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE2 : 1; /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE3 : 1; /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE4 : 1; /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + __IOM uint32_t CDRE5 : 1; /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified + * only once after a reset. */ + uint32_t : 2; + __IM uint32_t ST : 1; /*!< [16..16] GTETRG Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRG Input Reverse */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise Filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise Filter Clock Select */ + } POEGG_b; + }; +} R_GPT_POEG0_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller Unit (R_ICU) + */ + +typedef struct /*!< (@ 0x40006000) R_ICU Structure */ +{ + union + { + __IOM uint8_t IRQCR[16]; /*!< (@ 0x00000000) IRQ Control Register [0..15] */ + + struct + { + __IOM uint8_t IRQMD : 2; /*!< [1..0] IRQ Detection Sense Select */ + uint8_t : 2; + __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t FLTEN : 1; /*!< [7..7] IRQ Digital Filter Enable */ + } IRQCR_b[16]; + }; + __IM uint32_t RESERVED[60]; + + union + { + __IOM uint8_t NMICR; /*!< (@ 0x00000100) NMI Pin Interrupt Control Register */ + + struct + { + __IOM uint8_t NMIMD : 1; /*!< [0..0] NMI Detection Set */ + uint8_t : 3; + __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select */ + uint8_t : 1; + __IOM uint8_t NFLTEN : 1; /*!< [7..7] NMI Digital Filter Enable */ + } NMICR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3[7]; + + union + { + __IOM uint16_t NMIER; /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register */ + + struct + { + __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t WDTEN : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable */ + __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable */ + __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable */ + __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t OSTEN : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable */ + __IOM uint16_t NMIEN : 1; /*!< [7..7] NMI Pin Interrupt Enable */ + __IOM uint16_t RPEEN : 1; /*!< [8..8] RAM Parity Error Interrupt Enable */ + __IOM uint16_t RECCEN : 1; /*!< [9..9] RAM ECC Error Interrupt Enable */ + __IOM uint16_t BUSSEN : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable */ + __IOM uint16_t BUSMEN : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable */ + __IOM uint16_t SPEEN : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable */ + __IOM uint16_t TZFEN : 1; /*!< [13..13] TZFEN */ + uint16_t : 1; + __IOM uint16_t CPEEN : 1; /*!< [15..15] CPEEN */ + } NMIER_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint16_t NMICLR; /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register */ + + struct + { + __OM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear */ + __OM uint16_t WDTCLR : 1; /*!< [1..1] WDT Clear */ + __OM uint16_t LVD1CLR : 1; /*!< [2..2] LVD1 Clear */ + __OM uint16_t LVD2CLR : 1; /*!< [3..3] LVD2 Clear */ + __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear */ + uint16_t : 1; + __OM uint16_t OSTCLR : 1; /*!< [6..6] OST Clear */ + __OM uint16_t NMICLR : 1; /*!< [7..7] NMI Clear */ + __OM uint16_t RPECLR : 1; /*!< [8..8] SRAM Parity Error Clear */ + __OM uint16_t RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear */ + __OM uint16_t BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear */ + __OM uint16_t BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear */ + __OM uint16_t SPECLR : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear */ + __IOM uint16_t TZFCLR : 1; /*!< [13..13] TZFCLR */ + uint16_t : 1; + __IOM uint16_t CPECLR : 1; /*!< [15..15] CPECLR */ + } NMICLR_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IM uint16_t NMISR; /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register */ + + struct + { + __IM uint16_t IWDTST : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag */ + __IM uint16_t WDTST : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag */ + __IM uint16_t LVD1ST : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag */ + __IM uint16_t LVD2ST : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag */ + __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag */ + uint16_t : 1; + __IM uint16_t OSTST : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag */ + __IM uint16_t NMIST : 1; /*!< [7..7] NMI Status Flag */ + __IM uint16_t RPEST : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag */ + __IM uint16_t RECCST : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag */ + __IM uint16_t BUSSST : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag */ + __IM uint16_t BUSMST : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag */ + __IM uint16_t SPEST : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag */ + __IM uint16_t TZFST : 1; /*!< [13..13] TZFST */ + uint16_t : 1; + __IM uint16_t CPEST : 1; /*!< [15..15] CPEST */ + } NMISR_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[23]; + + union + { + __IOM uint32_t WUPEN; /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register */ + + struct + { + __IOM uint32_t IRQWUPEN0 : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN1 : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN2 : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN3 : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN4 : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN5 : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN6 : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN7 : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN8 : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN9 : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN10 : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN11 : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN12 : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN13 : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN14 : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IRQWUPEN15 : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable */ + __IOM uint32_t IWDTWUPEN : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable */ + __IOM uint32_t KEYWUPEN : 1; /*!< [17..17] Key interrupt S/W standby returns enable */ + __IOM uint32_t LVD1WUPEN : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable */ + __IOM uint32_t LVD2WUPEN : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable */ + __IOM uint32_t VBATTWUPEN : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable */ + uint32_t : 1; + __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit */ + __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable */ + __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable */ + __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable */ + __IOM uint32_t USBHSWUPEN : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit */ + __IOM uint32_t USBFSWUPEN : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable */ + __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable */ + __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns + * enable */ + __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 compare match B interrupt S/W standby returns + * enable */ + __IOM uint32_t IIC0WUPEN : 1; /*!< [31..31] IIC0 address match interrupt S/W standby returns enable */ + } WUPEN_b; + }; + + union + { + __IOM uint32_t WUPEN1; /*!< (@ 0x000001A4) Wake Up interrupt enable register 1 */ + + struct + { + __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit */ + __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable + * bit */ + __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable + * bit */ + uint32_t : 29; + } WUPEN1_b; + }; + __IM uint32_t RESERVED10[6]; + + union + { + __IOM uint8_t IELEN; /*!< (@ 0x000001C0) ICU event Enable Register */ + + struct + { + __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit + * = 1) */ + __IOM uint8_t IELEN : 1; /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when + * LPOPTEN bit = 1) */ + uint8_t : 6; + } IELEN_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; + __IM uint32_t RESERVED13[15]; + + union + { + __IOM uint16_t SELSR0; /*!< (@ 0x00000200) Snooze Event Link Setting Register */ + + struct + { + __IOM uint16_t SELS : 9; /*!< [8..0] SYS Event Link Select */ + uint16_t : 7; + } SELSR0_b; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[31]; + + union + { + __IOM uint32_t DELSR[8]; /*!< (@ 0x00000280) DMAC Event Link Setting Register */ + + struct + { + __IOM uint32_t DELS : 9; /*!< [8..0] Event selection to DMAC Start request */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the + * IR flag is prohibited. */ + uint32_t : 15; + } DELSR_b[8]; + }; + __IM uint32_t RESERVED16[24]; + + union + { + __IOM uint32_t IELSR[96]; /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95] */ + + struct + { + __IOM uint32_t IELS : 9; /*!< [8..0] ICU Event selection to NVICSet the number for the event + * signal to be linked . */ + uint32_t : 7; + __IOM uint32_t IR : 1; /*!< [16..16] Interrupt Status Flag */ + uint32_t : 7; + __IOM uint32_t DTCE : 1; /*!< [24..24] DTC Activation Enable */ + uint32_t : 7; + } IELSR_b[96]; + }; +} R_ICU_Type; /*!< Size = 1152 (0x480) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface (R_IIC0) + */ + +typedef struct /*!< (@ 0x4009F000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __IOM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset + * is initiated using the IICRST bit for a bus hang-up occurred + * during communication with the master device in slave mode, + * the states may become different between the slave device + * and the master device (due to the difference in the bit + * counter information). */ + __IOM uint8_t ICE : 1; /*!< [7..7] I2C Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start + * condition issuance request) when the BBSY flag is set to + * 0 (bus free state). */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the + * RS bit to 1 while issuing a stop condition. */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP + * bit is not possible while the setting of the BBSY flag + * is 0 (bus free state).Note: Do not set the SP bit to 1 + * while a restart condition is being issued. */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect(This bit is read as 1.) */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB + * / 2^CKS ) */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Selection */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Selection */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read, + * be sure to read the ICDRR beforehand. */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/I2C Bus Selection */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + __IOM uint8_t FMPE : 1; /*!< [7..7] Fast-mode Plus Enable */ + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device-ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device-ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock) */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock) */ + uint8_t : 3; + } ICBRH_b; + }; + + union + { + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + + struct + { + __IOM uint8_t ICDRT : 8; /*!< [7..0] 8-bit read-write register that stores transmit data. */ + } ICDRT_b; + }; + + union + { + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ + + struct + { + __IM uint8_t ICDRR : 8; /*!< [7..0] 8-bit register that stores the received data */ + } ICDRR_b; + }; + __IM uint8_t RESERVED[2]; + + union + { + __IOM uint8_t ICWUR; /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register */ + + struct + { + __IOM uint8_t WUAFA : 1; /*!< [0..0] Wakeup Analog Filter Additional Selection */ + uint8_t : 3; + __IOM uint8_t WUACK : 1; /*!< [4..4] ACK bit for Wakeup Mode */ + __IOM uint8_t WUF : 1; /*!< [5..5] Wakeup Event Occurrence Flag */ + __IOM uint8_t WUIE : 1; /*!< [6..6] Wakeup Interrupt Request Enable */ + __IOM uint8_t WUE : 1; /*!< [7..7] Wakeup Function Enable */ + } ICWUR_b; + }; + + union + { + __IOM uint8_t ICWUR2; /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2 */ + + struct + { + __IM uint8_t WUSEN : 1; /*!< [0..0] Wake-up Function Synchronous Enable */ + __IM uint8_t WUASYF : 1; /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag */ + __IM uint8_t WUSYF : 1; /*!< [2..2] Wake-up Function Synchronous Operation Status Flag */ + uint8_t : 5; + } ICWUR2_b; + }; +} R_IIC0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_IIRFA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief IIR Filter Accelerator (R_IIRFA) + */ + +typedef struct /*!< (@ 0x40020000) R_IIRFA Structure */ +{ + union + { + __IM uint32_t IIRCPRCS; /*!< (@ 0x00000000) Channel Processing Status Register */ + + struct + { + __IM uint32_t CPRCS : 16; /*!< [15..0] Channel processing status bit */ + uint32_t : 16; + } IIRCPRCS_b; + }; + + union + { + __IM uint32_t IIRCPRCFF; /*!< (@ 0x00000004) Channel Processing Completion Flag Register */ + + struct + { + __IM uint32_t CPRCFF : 16; /*!< [15..0] Channel processing completion flag */ + uint32_t : 16; + } IIRCPRCFF_b; + }; + + union + { + __IM uint32_t IIRORDYF; /*!< (@ 0x00000008) Output Data Preparation Completion Flag Register */ + + struct + { + __IM uint32_t ORDYF : 16; /*!< [15..0] Output data preparation completion flag */ + uint32_t : 16; + } IIRORDYF_b; + }; + + union + { + __IM uint32_t IIRCERRF; /*!< (@ 0x0000000C) Operation Error Flag Register */ + + struct + { + __IM uint32_t CERRF : 16; /*!< [15..0] Operation error flag */ + uint32_t : 16; + } IIRCERRF_b; + }; + + union + { + __IOM uint32_t IIROPCNT; /*!< (@ 0x00000010) Operation Control Register */ + + struct + { + __IOM uint32_t RND : 3; /*!< [2..0] Setting for the rounding mode for addition and multiplication */ + uint32_t : 29; + } IIROPCNT_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t IIRECCCNT; /*!< (@ 0x00000020) ECC Control Register */ + + struct + { + __IOM uint32_t ECCMD : 1; /*!< [0..0] ECC setting bit */ + __IOM uint32_t ECCWBDIS : 1; /*!< [1..1] ECC-corrected data write-back disable bit */ + uint32_t : 30; + } IIRECCCNT_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t IIRECCINT; /*!< (@ 0x00000028) ECC Interrupt Enable Register */ + + struct + { + __IOM uint32_t ESEIE : 1; /*!< [0..0] ECC 1-bit error interrupt enable bit */ + __IOM uint32_t EDEIE : 1; /*!< [1..1] ECC 2-bit error interrupt enable bit */ + uint32_t : 30; + } IIRECCINT_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t IIRECCEF; /*!< (@ 0x00000030) ECC Error Flag Register */ + + struct + { + __IM uint32_t ESEF : 1; /*!< [0..0] ECC 1-bit error flag */ + __IM uint32_t EDEF : 1; /*!< [1..1] ECC 2-bit error flag */ + uint32_t : 30; + } IIRECCEF_b; + }; + + union + { + __OM uint32_t IIRECCEFCLR; /*!< (@ 0x00000034) ECC Error Flag Clear Register */ + + struct + { + __OM uint32_t ESEFCLR : 1; /*!< [0..0] ECC 1-bit error flag clear bit */ + __OM uint32_t EDEFCLR : 1; /*!< [1..1] ECC 2-bit error status flag clear bit */ + uint32_t : 30; + } IIRECCEFCLR_b; + }; + + union + { + __IM uint32_t IIRESEADR; /*!< (@ 0x00000038) ECC 1-bit Error Address Register */ + + struct + { + __IM uint32_t SEADR : 11; /*!< [10..0] Error address */ + uint32_t : 21; + } IIRESEADR_b; + }; + + union + { + __IM uint32_t IIREDEADR; /*!< (@ 0x0000003C) ECC 2-bit Error Address Register */ + + struct + { + __IM uint32_t DEADR : 11; /*!< [10..0] Error address */ + uint32_t : 21; + } IIREDEADR_b; + }; + __IM uint32_t RESERVED3[48]; + __IOM R_IIRFA_IIRCH_Type IIRCH[16]; /*!< (@ 0x00000100) Channel Registers */ + __IM uint32_t RESERVED4[128]; + __IOM R_IIRFA_IIRSTG_Type IIRSTG[32]; /*!< (@ 0x00000400) Stage Registers */ +} R_IIRFA_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Independent Watchdog Timer (R_IWDT) + */ + +typedef struct /*!< (@ 0x40083200) R_IWDT Structure */ +{ + union + { + __IOM uint8_t IWDTRR; /*!< (@ 0x00000000) IWDT Refresh Register */ + + struct + { + __IOM uint8_t IWDTRR : 8; /*!< [7..0] The counter is refreshed by writing 0x00 and then writing + * 0xFF to this register. */ + } IWDTRR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t IWDTSR; /*!< (@ 0x00000004) IWDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Counter ValueValue counted by the counter */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } IWDTSR_b; + }; +} R_IWDT_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Key Interrupt Function (R_KINT) + */ + +typedef struct /*!< (@ 0x40085000) R_KINT Structure */ +{ + union + { + __IOM uint8_t KRCTL; /*!< (@ 0x00000000) KEY Return Control Register */ + + struct + { + __IOM uint8_t KREG : 1; /*!< [0..0] Detection Edge Selection (KRF0 to KRF7) */ + uint8_t : 6; + __IOM uint8_t KRMD : 1; /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7) */ + } KRCTL_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t KRF; /*!< (@ 0x00000004) KEY Return Flag Register */ + + struct + { + __IOM uint8_t KRF0 : 1; /*!< [0..0] Key interrupt flag 0 */ + __IOM uint8_t KRF1 : 1; /*!< [1..1] Key interrupt flag 1 */ + __IOM uint8_t KRF2 : 1; /*!< [2..2] Key interrupt flag 2 */ + __IOM uint8_t KRF3 : 1; /*!< [3..3] Key interrupt flag 3 */ + __IOM uint8_t KRF4 : 1; /*!< [4..4] Key interrupt flag 4 */ + __IOM uint8_t KRF5 : 1; /*!< [5..5] Key interrupt flag 5 */ + __IOM uint8_t KRF6 : 1; /*!< [6..6] Key interrupt flag 6 */ + __IOM uint8_t KRF7 : 1; /*!< [7..7] Key interrupt flag 7 */ + } KRF_b; + }; + __IM uint8_t RESERVED1[3]; + + union + { + __IOM uint8_t KRM; /*!< (@ 0x00000008) KEY Return Mode Register */ + + struct + { + __IOM uint8_t KRM0 : 1; /*!< [0..0] Key interrupt mode control 0 */ + __IOM uint8_t KRM1 : 1; /*!< [1..1] Key interrupt mode control 1 */ + __IOM uint8_t KRM2 : 1; /*!< [2..2] Key interrupt mode control 2 */ + __IOM uint8_t KRM3 : 1; /*!< [3..3] Key interrupt mode control 3 */ + __IOM uint8_t KRM4 : 1; /*!< [4..4] Key interrupt mode control 4 */ + __IOM uint8_t KRM5 : 1; /*!< [5..5] Key interrupt mode control 5 */ + __IOM uint8_t KRM6 : 1; /*!< [6..6] Key interrupt mode control 6 */ + __IOM uint8_t KRM7 : 1; /*!< [7..7] Key interrupt mode control 7 */ + } KRM_b; + }; +} R_KINT_Type; /*!< Size = 9 (0x9) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I3C Bus Interface (R_I3C0) + */ + +typedef struct /*!< (@ 0x4011F000) R_I3C0 Structure */ +{ + union + { + __IOM uint32_t PRTS; /*!< (@ 0x00000000) Protocol Selection Register */ + + struct + { + __IOM uint32_t PRTMD : 1; /*!< [0..0] Protocol Mode */ + uint32_t : 31; + } PRTS_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t CECTL; /*!< (@ 0x00000010) Clock Enable Control Resisters */ + + struct + { + __IOM uint32_t CLKE : 1; /*!< [0..0] Clock Enable */ + uint32_t : 31; + } CECTL_b; + }; + + union + { + __IOM uint32_t BCTL; /*!< (@ 0x00000014) Bus Control Register */ + + struct + { + __IOM uint32_t INCBA : 1; /*!< [0..0] Include I3C Broadcast Address */ + uint32_t : 6; + __IOM uint32_t BMDS : 1; /*!< [7..7] Bus Mode Selection */ + __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control */ + uint32_t : 20; + __IOM uint32_t ABT : 1; /*!< [29..29] Abort */ + __IOM uint32_t RSM : 1; /*!< [30..30] Resume */ + __IOM uint32_t BUSE : 1; /*!< [31..31] Bus Enable */ + } BCTL_b; + }; + + union + { + __IOM uint32_t MSDVAD; /*!< (@ 0x00000018) Master Device Address Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MDYAD : 7; /*!< [22..16] Master Dynamic Address */ + uint32_t : 8; + __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid */ + } MSDVAD_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t RSTCTL; /*!< (@ 0x00000020) Reset Control Register */ + + struct + { + __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset */ + __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset */ + __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset */ + __IOM uint32_t TDBRST : 1; /*!< [3..3] Transmit Data Buffer Software Reset */ + __IOM uint32_t RDBRST : 1; /*!< [4..4] Receive Data Buffer Software Reset */ + __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset */ + __IOM uint32_t RSQRST : 1; /*!< [6..6] Receive Status Queue Software Reset */ + uint32_t : 9; + __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset */ + uint32_t : 15; + } RSTCTL_b; + }; + + union + { + __IOM uint32_t PRSST; /*!< (@ 0x00000024) Present State Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t CRMS : 1; /*!< [2..2] Current Master */ + uint32_t : 1; + __IM uint32_t TRMD : 1; /*!< [4..4] Transmit/Receive Mode */ + uint32_t : 2; + __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect */ + uint32_t : 24; + } PRSST_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t INST; /*!< (@ 0x00000030) Internal Status Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEF : 1; /*!< [10..10] Internal Error Flag */ + uint32_t : 21; + } INST_b; + }; + + union + { + __IOM uint32_t INSTE; /*!< (@ 0x00000034) Internal Status Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEE : 1; /*!< [10..10] Internal Error Enable */ + uint32_t : 21; + } INSTE_b; + }; + + union + { + __IOM uint32_t INIE; /*!< (@ 0x00000038) Internal Interrupt Enable Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t INEIE : 1; /*!< [10..10] Internal Error Interrupt Enable */ + uint32_t : 21; + } INIE_b; + }; + + union + { + __IOM uint32_t INSTFC; /*!< (@ 0x0000003C) Internal Status Force Register */ + + struct + { + uint32_t : 10; + __OM uint32_t INEFC : 1; /*!< [10..10] Internal Error Force */ + uint32_t : 21; + } INSTFC_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t DVCT; /*!< (@ 0x00000044) Device Characteristic Table Register */ + + struct + { + uint32_t : 19; + __IM uint32_t IDX : 5; /*!< [23..19] DCT Table Index */ + uint32_t : 8; + } DVCT_b; + }; + __IM uint32_t RESERVED4[4]; + + union + { + __IOM uint32_t IBINCTL; /*!< (@ 0x00000058) IBI Notify Control Register */ + + struct + { + __IOM uint32_t NRHJCTL : 1; /*!< [0..0] Notify Rejected Hot-Join Control */ + __IOM uint32_t NRMRCTL : 1; /*!< [1..1] Notify Rejected Master Request Control */ + uint32_t : 1; + __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control */ + uint32_t : 28; + } IBINCTL_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t BFCTL; /*!< (@ 0x00000060) Bus Function Control Register */ + + struct + { + __IOM uint32_t MALE : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable */ + __IOM uint32_t NALE : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint32_t SALE : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable */ + uint32_t : 5; + __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable */ + uint32_t : 3; + __IOM uint32_t SMBS : 1; /*!< [12..12] SMBus/I2C Bus Selection */ + uint32_t : 1; + __IOM uint32_t FMPE : 1; /*!< [14..14] Fast-mode Plus Enable */ + __IOM uint32_t HSME : 1; /*!< [15..15] High Speed Mode Enable */ + uint32_t : 16; + } BFCTL_b; + }; + + union + { + __IOM uint32_t SVCTL; /*!< (@ 0x00000064) Slave Control Register */ + + struct + { + __IOM uint32_t GCAE : 1; /*!< [0..0] General Call Address Enable */ + uint32_t : 4; + __IOM uint32_t HSMCE : 1; /*!< [5..5] Hs-mode Master Code Enable */ + __IOM uint32_t DVIDE : 1; /*!< [6..6] Device-ID Address Enable */ + uint32_t : 8; + __IOM uint32_t HOAE : 1; /*!< [15..15] Host Address Enable */ + __IOM uint32_t SVAEn : 1; /*!< [16..16] Slave Address Enable n (n = 0) */ + uint32_t : 15; + } SVCTL_b; + }; + __IM uint32_t RESERVED6[2]; + + union + { + __IOM uint32_t REFCKCTL; /*!< (@ 0x00000070) Reference Clock Control Register */ + + struct + { + __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection */ + uint32_t : 29; + } REFCKCTL_b; + }; + + union + { + __IOM uint32_t STDBR; /*!< (@ 0x00000074) Standard Bit Rate Register */ + + struct + { + __IOM uint32_t SBRLO : 8; /*!< [7..0] Count value of the Low-level period of SCL clock */ + __IOM uint32_t SBRHO : 8; /*!< [15..8] Count value of the High-level period of SCL clock */ + __IOM uint32_t SBRLP : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t SBRHP : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull */ + uint32_t : 1; + __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain */ + } STDBR_b; + }; + + union + { + __IOM uint32_t EXTBR; /*!< (@ 0x00000078) Extended Bit Rate Register */ + + struct + { + __IOM uint32_t EBRLO : 8; /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain */ + __IOM uint32_t EBRHO : 8; /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain */ + __IOM uint32_t EBRLP : 6; /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + __IOM uint32_t EBRHP : 6; /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull */ + uint32_t : 2; + } EXTBR_b; + }; + + union + { + __IOM uint32_t BFRECDT; /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register */ + + struct + { + __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle */ + uint32_t : 23; + } BFRECDT_b; + }; + + union + { + __IOM uint32_t BAVLCDT; /*!< (@ 0x00000080) Bus Available Condition Detection Time Register */ + + struct + { + __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle */ + uint32_t : 23; + } BAVLCDT_b; + }; + + union + { + __IOM uint32_t BIDLCDT; /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register */ + + struct + { + __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle */ + uint32_t : 14; + } BIDLCDT_b; + }; + + union + { + __IOM uint32_t OUTCTL; /*!< (@ 0x00000088) Output Control Register */ + + struct + { + __IOM uint32_t SDOC : 1; /*!< [0..0] SDA Output Control */ + __IOM uint32_t SCOC : 1; /*!< [1..1] SCL Output Control */ + __OM uint32_t SOCWP : 1; /*!< [2..2] SCL/SDA Output Control Write Protect */ + uint32_t : 1; + __IOM uint32_t EXCYC : 1; /*!< [4..4] Extra SCL Clock Cycle Output */ + uint32_t : 3; + __IOM uint32_t SDOD : 3; /*!< [10..8] SDA Output Delay */ + uint32_t : 4; + __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection */ + uint32_t : 16; + } OUTCTL_b; + }; + + union + { + __IOM uint32_t INCTL; /*!< (@ 0x0000008C) Input Control Register */ + + struct + { + __IOM uint32_t DNFS : 4; /*!< [3..0] Digital Noise Filter Stage Selection */ + __IOM uint32_t DNFE : 1; /*!< [4..4] Digital Noise Filter Circuit Enable */ + uint32_t : 27; + } INCTL_b; + }; + + union + { + __IOM uint32_t TMOCTL; /*!< (@ 0x00000090) Timeout Control Register */ + + struct + { + __IOM uint32_t TODTS : 2; /*!< [1..0] Timeout Detection Time Selection */ + uint32_t : 2; + __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control */ + __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control */ + __IOM uint32_t TOMDS : 2; /*!< [7..6] Timeout Operation Mode Selection */ + uint32_t : 24; + } TMOCTL_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t WUCTL; /*!< (@ 0x00000098) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUACKS : 1; /*!< [0..0] Wake-Up Acknowledge Selection */ + uint32_t : 3; + __IOM uint32_t WUANFS : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection */ + uint32_t : 1; + __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable */ + __IOM uint32_t WUFE : 1; /*!< [7..7] Wake-Up function Enable. */ + uint32_t : 24; + } WUCTL_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ACKCTL; /*!< (@ 0x000000A0) Acknowledge Control Register */ + + struct + { + __IM uint32_t ACKR : 1; /*!< [0..0] Acknowledge Reception */ + __IOM uint32_t ACKT : 1; /*!< [1..1] Acknowledge Transmission */ + __OM uint32_t ACKTWP : 1; /*!< [2..2] ACKT Write Protect */ + uint32_t : 29; + } ACKCTL_b; + }; + + union + { + __IOM uint32_t SCSTRCTL; /*!< (@ 0x000000A4) SCL Stretch Control Register */ + + struct + { + __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable */ + __IOM uint32_t RWE : 1; /*!< [1..1] Receive Wait Enable */ + uint32_t : 30; + } SCSTRCTL_b; + }; + __IM uint32_t RESERVED9[2]; + + union + { + __IOM uint32_t SCSTLCTL; /*!< (@ 0x000000B0) SCL Stalling Control Register */ + + struct + { + __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle */ + uint32_t : 12; + __IOM uint32_t AAPE : 1; /*!< [28..28] Assigend Address Phase Enable */ + __IOM uint32_t TRAPE : 1; /*!< [29..29] Transition Phase Enable */ + __IOM uint32_t PARPE : 1; /*!< [30..30] Parity Phase Enable */ + __IOM uint32_t ACKPE : 1; /*!< [31..31] ACK phase Enable */ + } SCSTLCTL_b; + }; + __IM uint32_t RESERVED10[3]; + + union + { + __IOM uint32_t SVTDLG0; /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0 */ + + struct + { + uint32_t : 16; + __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length */ + } SVTDLG0_b; + }; + __IM uint32_t RESERVED11[31]; + + union + { + __IOM uint32_t CNDCTL; /*!< (@ 0x00000140) Condition Control Register */ + + struct + { + __IOM uint32_t STCND : 1; /*!< [0..0] START (S) Condition Issuance */ + __IOM uint32_t SRCND : 1; /*!< [1..1] Repeated START (Sr) Condition Issuance */ + __IOM uint32_t SPCND : 1; /*!< [2..2] STOP (P) Condition Issuance */ + uint32_t : 29; + } CNDCTL_b; + }; + __IM uint32_t RESERVED12[3]; + __OM uint32_t NCMDQP; /*!< (@ 0x00000150) Normal Command Queue Port Register */ + __IM uint32_t NRSPQP; /*!< (@ 0x00000154) Normal Response Queue Port Register */ + __IOM uint32_t NTDTBP0; /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0 */ + __IM uint32_t RESERVED13[8]; + __IOM uint32_t NIBIQP; /*!< (@ 0x0000017C) Normal IBI Queue Port Register */ + __IM uint32_t NRSQP; /*!< (@ 0x00000180) Normal Receive Status Queue Port Register */ + __IM uint32_t RESERVED14[3]; + + union + { + __IOM uint32_t NQTHCTL; /*!< (@ 0x00000190) Normal Queue Threshold Control Register */ + + struct + { + __IOM uint32_t CMDQTH : 8; /*!< [7..0] Normal Command Ready Queue Threshold */ + __IOM uint32_t RSPQTH : 8; /*!< [15..8] Normal Response Queue Threshold */ + __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size */ + __IOM uint32_t IBIQTH : 8; /*!< [31..24] Normal IBI Queue Threshold */ + } NQTHCTL_b; + }; + + union + { + __IOM uint32_t NTBTHCTL0; /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control + * Register 0 */ + + struct + { + __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold */ + uint32_t : 5; + __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold */ + uint32_t : 5; + __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold */ + uint32_t : 5; + } NTBTHCTL0_b; + }; + __IM uint32_t RESERVED15[10]; + + union + { + __IOM uint32_t NRQTHCTL; /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control + * Register */ + + struct + { + __IOM uint32_t RSQTH : 8; /*!< [7..0] Normal Receive Status Queue Threshold */ + uint32_t : 24; + } NRQTHCTL_b; + }; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint32_t BST; /*!< (@ 0x000001D0) Bus Status Register */ + + struct + { + __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag */ + __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag */ + __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag */ + uint32_t : 1; + __IOM uint32_t NACKDF : 1; /*!< [4..4] NACK Detection Flag */ + uint32_t : 3; + __IOM uint32_t TENDF : 1; /*!< [8..8] Transmit End Flag */ + uint32_t : 7; + __IOM uint32_t ALF : 1; /*!< [16..16] Arbitration Lost Flag */ + uint32_t : 3; + __IOM uint32_t TODF : 1; /*!< [20..20] Timeout Detection Flag */ + uint32_t : 11; + } BST_b; + }; + + union + { + __IOM uint32_t BSTE; /*!< (@ 0x000001D4) Bus Status Enable Register */ + + struct + { + __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable */ + __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable */ + __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable */ + uint32_t : 1; + __IOM uint32_t NACKDE : 1; /*!< [4..4] NACK Detection Enable */ + uint32_t : 3; + __IOM uint32_t TENDE : 1; /*!< [8..8] Transmit End Enable */ + uint32_t : 7; + __IOM uint32_t ALE : 1; /*!< [16..16] Arbitration Lost Enable */ + uint32_t : 3; + __IOM uint32_t TODE : 1; /*!< [20..20] Timeout Detection Enable */ + uint32_t : 11; + } BSTE_b; + }; + + union + { + __IOM uint32_t BIE; /*!< (@ 0x000001D8) Bus Interrupt Enable Register */ + + struct + { + __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable */ + __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable */ + __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t NACKDIE : 1; /*!< [4..4] NACK Detection Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TENDIE : 1; /*!< [8..8] Transmit End Interrupt Enable */ + uint32_t : 7; + __IOM uint32_t ALIE : 1; /*!< [16..16] Arbitration Lost Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TODIE : 1; /*!< [20..20] Timeout Detection Interrupt Enable */ + uint32_t : 11; + } BIE_b; + }; + + union + { + __IOM uint32_t BSTFC; /*!< (@ 0x000001DC) Bus Status Force Register */ + + struct + { + __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force */ + __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force */ + __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force */ + uint32_t : 1; + __OM uint32_t NACKDFC : 1; /*!< [4..4] NACK Detection Force */ + uint32_t : 3; + __OM uint32_t TENDFC : 1; /*!< [8..8] Transmit End Force */ + uint32_t : 7; + __OM uint32_t ALFC : 1; /*!< [16..16] Arbitration Lost Force */ + uint32_t : 3; + __OM uint32_t TODFC : 1; /*!< [20..20] Timeout Detection Force */ + uint32_t : 11; + } BSTFC_b; + }; + + union + { + __IOM uint32_t NTST; /*!< (@ 0x000001E0) Normal Transfer Status Register */ + + struct + { + __IOM uint32_t TDBEF0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0 */ + __IOM uint32_t RDBFF0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0 */ + __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag */ + __IOM uint32_t CMDQEF : 1; /*!< [3..3] Normal Command Queue Empty Flag */ + __IOM uint32_t RSPQFF : 1; /*!< [4..4] Normal Response Queue Full Flag */ + __IOM uint32_t TABTF : 1; /*!< [5..5] Normal Transfer Abort Flag */ + uint32_t : 3; + __IOM uint32_t TEF : 1; /*!< [9..9] Normal Transfer Error Flag */ + uint32_t : 10; + __IOM uint32_t RSQFF : 1; /*!< [20..20] Normal Receive Status Queue Full Flag */ + uint32_t : 11; + } NTST_b; + }; + + union + { + __IOM uint32_t NTSTE; /*!< (@ 0x000001E4) Normal Transfer Status Enable Register */ + + struct + { + __IOM uint32_t TDBEE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0 */ + __IOM uint32_t RDBFE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0 */ + __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable */ + __IOM uint32_t CMDQEE : 1; /*!< [3..3] Normal Command Queue Empty Enable */ + __IOM uint32_t RSPQFE : 1; /*!< [4..4] Normal Response Queue Full Enable */ + __IOM uint32_t TABTE : 1; /*!< [5..5] Normal Transfer Abort Enable */ + uint32_t : 3; + __IOM uint32_t TEE : 1; /*!< [9..9] Normal Transfer Error Enable */ + uint32_t : 10; + __IOM uint32_t RSQFE : 1; /*!< [20..20] Normal Receive Status Queue Full Enable */ + uint32_t : 11; + } NTSTE_b; + }; + + union + { + __IOM uint32_t NTIE; /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register */ + + struct + { + __IOM uint32_t TDBEIE0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0 */ + __IOM uint32_t RDBFIE0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0 */ + __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable */ + __IOM uint32_t CMDQEIE : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable */ + __IOM uint32_t RSPQFIE : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable */ + __IOM uint32_t TABTIE : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TEIE : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable */ + uint32_t : 10; + __IOM uint32_t RSQFIE : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable */ + uint32_t : 11; + } NTIE_b; + }; + + union + { + __IOM uint32_t NTSTFC; /*!< (@ 0x000001EC) Normal Transfer Status Force Register */ + + struct + { + __OM uint32_t TDBEFC0 : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0 */ + __OM uint32_t RDBFFC0 : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0 */ + __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force */ + __OM uint32_t CMDQEFC : 1; /*!< [3..3] Normal Command Queue Empty Force */ + __OM uint32_t RSPQFFC : 1; /*!< [4..4] Normal Response Queue Full Force */ + __OM uint32_t TABTFC : 1; /*!< [5..5] Normal Transfer Abort Force */ + uint32_t : 3; + __OM uint32_t TEFC : 1; /*!< [9..9] Normal Transfer Error Force */ + uint32_t : 10; + __OM uint32_t RSQFFC : 1; /*!< [20..20] Normal Receive Status Queue Full Force */ + uint32_t : 11; + } NTSTFC_b; + }; + __IM uint32_t RESERVED17[8]; + + union + { + __IM uint32_t BCST; /*!< (@ 0x00000210) Bus Condition Status Register */ + + struct + { + __IM uint32_t BFREF : 1; /*!< [0..0] Bus Free Detection Flag */ + __IM uint32_t BAVLF : 1; /*!< [1..1] Bus Available Detection Flag */ + __IM uint32_t BIDLF : 1; /*!< [2..2] Bus Idle Detection Flag */ + uint32_t : 29; + } BCST_b; + }; + + union + { + __IOM uint32_t SVST; /*!< (@ 0x00000214) Slave Status Register */ + + struct + { + __IOM uint32_t GCAF : 1; /*!< [0..0] General Call Address Detection Flag */ + uint32_t : 4; + __IOM uint32_t HSMCF : 1; /*!< [5..5] Hs-mode Master Code Detection Flag */ + __IOM uint32_t DVIDF : 1; /*!< [6..6] Device-ID Address Detection Flag */ + uint32_t : 8; + __IOM uint32_t HOAF : 1; /*!< [15..15] Host Address Detection Flag */ + __IOM uint32_t SVAFn : 1; /*!< [16..16] Slave Address Detection Flag n (n = 0) */ + uint32_t : 15; + } SVST_b; + }; + + union + { + __IOM uint32_t WUST; /*!< (@ 0x00000218) Wake Up Unit Control Register */ + + struct + { + __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag. */ + uint32_t : 31; + } WUST_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t DATBAS0; /*!< (@ 0x00000224) Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS0_b; + }; + __IM uint32_t RESERVED19; + + union + { + __IOM uint32_t DATBAS1; /*!< (@ 0x0000022C) Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS1_b; + }; + __IM uint32_t RESERVED20; + + union + { + __IOM uint32_t DATBAS2; /*!< (@ 0x00000234) Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS2_b; + }; + __IM uint32_t RESERVED21; + + union + { + __IOM uint32_t DATBAS3; /*!< (@ 0x0000023C) Device Address Table Basic Register 3 */ + + struct + { + __IOM uint32_t DVSTAD : 7; /*!< [6..0] Device Static Address */ + uint32_t : 5; + __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload */ + __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject */ + __IOM uint32_t DVMRRJ : 1; /*!< [14..14] Device In-Band Master Request Reject */ + __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp */ + __IOM uint32_t DVDYAD : 8; /*!< [23..16] Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t DVNACK : 2; /*!< [30..29] Device NACK Retry Count */ + __IOM uint32_t DVTYP : 1; /*!< [31..31] Device Type */ + } DATBAS3_b; + }; + __IM uint32_t RESERVED22[24]; + + union + { + __IOM uint32_t EXDATBAS; /*!< (@ 0x000002A0) Extended Device Address Table Basic Register */ + + struct + { + __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address */ + uint32_t : 9; + __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address */ + uint32_t : 5; + __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count */ + __IOM uint32_t EDTYP : 1; /*!< [31..31] Extended Device Type */ + } EXDATBAS_b; + }; + __IM uint32_t RESERVED23[3]; + + union + { + __IOM uint32_t SDATBAS0; /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS0_b; + }; + + union + { + __IOM uint32_t SDATBAS1; /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS1_b; + }; + + union + { + __IOM uint32_t SDATBAS2; /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2 */ + + struct + { + __IOM uint32_t SDSTAD : 10; /*!< [9..0] Slave Device Static Address */ + __IOM uint32_t SDADLS : 1; /*!< [10..10] Slave Device Address Length Selection */ + uint32_t : 1; + __IOM uint32_t SDIBIPL : 1; /*!< [12..12] Slave Device IBI Payload */ + uint32_t : 3; + __IOM uint32_t SDDYAD : 7; /*!< [22..16] Slave Device I3C Dynamic Address */ + uint32_t : 9; + } SDATBAS2_b; + }; + __IM uint32_t RESERVED24[5]; + + union + { + __IOM uint32_t MSDCT0; /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT0_b; + }; + + union + { + __IOM uint32_t MSDCT1; /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT1_b; + }; + + union + { + __IOM uint32_t MSDCT2; /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT2_b; + }; + + union + { + __IOM uint32_t MSDCT3; /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3 */ + + struct + { + uint32_t : 8; + __IOM uint32_t RBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t RBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t RBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t RBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } MSDCT3_b; + }; + __IM uint32_t RESERVED25[16]; + + union + { + __IOM uint32_t SVDCT; /*!< (@ 0x00000320) Slave Device Characteristic Table Register */ + + struct + { + __IOM uint32_t TDCR : 8; /*!< [7..0] Transfar Device Characteristic Register */ + __IOM uint32_t TBCR0 : 1; /*!< [8..8] Max Data Speed Limitation */ + __IOM uint32_t TBCR1 : 1; /*!< [9..9] IBI Request Capable */ + __IOM uint32_t TBCR2 : 1; /*!< [10..10] IBI Payload */ + __IOM uint32_t TBCR3 : 1; /*!< [11..11] Offline Capable */ + uint32_t : 2; + __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role */ + uint32_t : 16; + } SVDCT_b; + }; + __IOM uint32_t SDCTPIDL; /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional + * ID Low Register */ + __IOM uint32_t SDCTPIDH; /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional + * ID High Register */ + __IM uint32_t RESERVED26; + + union + { + __IM uint32_t SVDVAD0; /*!< (@ 0x00000330) Slave Device Address Register 0 */ + + struct + { + uint32_t : 16; + __IM uint32_t SVAD : 10; /*!< [25..16] Slave Address */ + uint32_t : 1; + __IM uint32_t SADLG : 1; /*!< [27..27] Slave Address Length */ + uint32_t : 2; + __IM uint32_t SSTADV : 1; /*!< [30..30] Slave Static Address Valid */ + __IM uint32_t SDYADV : 1; /*!< [31..31] Slave Dynamic Address Valid */ + } SVDVAD0_b; + }; + __IM uint32_t RESERVED27[7]; + + union + { + __IOM uint32_t CSECMD; /*!< (@ 0x00000350) CCC Slave Events Command Register */ + + struct + { + __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable */ + __IOM uint32_t MSRQE : 1; /*!< [1..1] Mastership Requests Enable */ + uint32_t : 1; + __IOM uint32_t HJEVE : 1; /*!< [3..3] Hot-Join Event Enable */ + uint32_t : 28; + } CSECMD_b; + }; + + union + { + __IOM uint32_t CEACTST; /*!< (@ 0x00000354) CCC Enter Activity State Register */ + + struct + { + __IOM uint32_t ACTST : 4; /*!< [3..0] Activity State */ + uint32_t : 28; + } CEACTST_b; + }; + + union + { + __IOM uint32_t CMWLG; /*!< (@ 0x00000358) CCC Max Write Length Register */ + + struct + { + __IOM uint32_t MWLG : 16; /*!< [15..0] Max Write Length */ + uint32_t : 16; + } CMWLG_b; + }; + + union + { + __IOM uint32_t CMRLG; /*!< (@ 0x0000035C) CCC Max Read Length Register */ + + struct + { + __IOM uint32_t MRLG : 16; /*!< [15..0] Max Read Length */ + __IOM uint32_t IBIPSZ : 8; /*!< [23..16] IBI Payload Size */ + uint32_t : 8; + } CMRLG_b; + }; + + union + { + __IM uint32_t CETSTMD; /*!< (@ 0x00000360) CCC Enter Test Mode Register */ + + struct + { + __IM uint32_t TSTMD : 8; /*!< [7..0] Test Mode */ + uint32_t : 24; + } CETSTMD_b; + }; + + union + { + __IOM uint32_t CGDVST; /*!< (@ 0x00000364) CCC Get Device Status Register */ + + struct + { + __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt */ + uint32_t : 1; + __IOM uint32_t PRTE : 1; /*!< [5..5] Protocol Error */ + __IOM uint32_t ACTMD : 2; /*!< [7..6] Slave Device's current Activity Mode */ + __IOM uint32_t VDRSV : 8; /*!< [15..8] Vendor Reserved */ + uint32_t : 16; + } CGDVST_b; + }; + + union + { + __IOM uint32_t CMDSPW; /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register */ + + struct + { + __IOM uint32_t MSWDR : 3; /*!< [2..0] Maximum Sustained Write Data Rate */ + uint32_t : 29; + } CMDSPW_b; + }; + + union + { + __IOM uint32_t CMDSPR; /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register */ + + struct + { + __IOM uint32_t MSRDR : 3; /*!< [2..0] Maximum Sustained Read Data Rate */ + __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO) */ + uint32_t : 26; + } CMDSPR_b; + }; + + union + { + __IOM uint32_t CMDSPT; /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register */ + + struct + { + __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time */ + uint32_t : 7; + __IOM uint32_t MRTE : 1; /*!< [31..31] Maximum Read Turnaround Time Enable */ + } CMDSPT_b; + }; + + union + { + __IOM uint32_t CETSM; /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode) + * Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t FREQ : 8; /*!< [15..8] Frequency Byte */ + __IOM uint32_t INAC : 8; /*!< [23..16] Inaccuracy Byte */ + uint32_t : 8; + } CETSM_b; + }; + __IM uint32_t RESERVED28[2]; + + union + { + __IOM uint32_t BITCNT; /*!< (@ 0x00000380) Bit Count Register */ + + struct + { + __IOM uint32_t BCNT : 5; /*!< [4..0] Bit Counter */ + uint32_t : 2; + __OM uint32_t BCNTWP : 1; /*!< [7..7] BCNT Write Protect */ + uint32_t : 24; + } BITCNT_b; + }; + __IM uint32_t RESERVED29[4]; + + union + { + __IM uint32_t NQSTLV; /*!< (@ 0x00000394) Normal Queue Status Level Register */ + + struct + { + __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level */ + __IM uint32_t RSPQLV : 8; /*!< [15..8] Normal Response Queue Level */ + __IM uint32_t IBIQLV : 8; /*!< [23..16] Normal IBI Queue Level */ + __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count */ + uint32_t : 3; + } NQSTLV_b; + }; + + union + { + __IM uint32_t NDBSTLV0; /*!< (@ 0x00000398) Normal Data Buffer Status Level Register */ + + struct + { + __IM uint32_t TDBFLV : 8; /*!< [7..0] Normal Transmit Data Buffer Free Level */ + __IM uint32_t RDBLV : 8; /*!< [15..8] Normal Receive Data Buffer Level */ + uint32_t : 16; + } NDBSTLV0_b; + }; + __IM uint32_t RESERVED30[9]; + + union + { + __IM uint32_t NRSQSTLV; /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register */ + + struct + { + __IM uint32_t RSQLV : 8; /*!< [7..0] Normal Receive Status Queue Level */ + uint32_t : 24; + } NRSQSTLV_b; + }; + __IM uint32_t RESERVED31[2]; + + union + { + __IM uint32_t PRSTDBG; /*!< (@ 0x000003CC) Present State Debug Register */ + + struct + { + __IM uint32_t SCILV : 1; /*!< [0..0] SCL Line Signal Level */ + __IM uint32_t SDILV : 1; /*!< [1..1] SDA Line Signal Level */ + __IM uint32_t SCOLV : 1; /*!< [2..2] SCL Output Level */ + __IM uint32_t SDOLV : 1; /*!< [3..3] SDA Output Level */ + uint32_t : 28; + } PRSTDBG_b; + }; + + union + { + __IM uint32_t MSERRCNT; /*!< (@ 0x000003D0) Master Error Counters Register */ + + struct + { + __IM uint32_t M2ECNT : 8; /*!< [7..0] M2 Error Counter */ + uint32_t : 24; + } MSERRCNT_b; + }; +} R_I3C0_Type; /*!< Size = 980 (0x3d4) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU Stack Pointer Monitor (R_MPU_SPMON) + */ + +typedef struct /*!< (@ 0x40000D00) R_MPU_SPMON Structure */ +{ + __IOM R_MPU_SPMON_SP_Type SP[2]; /*!< (@ 0x00000000) Stack Pointer Monitor */ +} R_MPU_SPMON_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System-Module Stop (R_MSTP) + */ + +typedef struct /*!< (@ 0x40084000) R_MSTP Structure */ +{ + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000000) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + uint32_t : 6; + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000004) Module Stop Control Register B */ + + struct + { + uint32_t : 1; + __IOM uint32_t MSTPB1 : 1; /*!< [1..1] RCAN1 Module Stop */ + __IOM uint32_t MSTPB2 : 1; /*!< [2..2] RCAN0 Module Stop */ + __IOM uint32_t MSTPB3 : 1; /*!< [3..3] RCEC Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB5 : 1; /*!< [5..5] IrDA Module Stop */ + __IOM uint32_t MSTPB6 : 1; /*!< [6..6] Queued Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB7 : 1; /*!< [7..7] I2C Bus Interface 2 Module Stop */ + __IOM uint32_t MSTPB8 : 1; /*!< [8..8] I2C Bus Interface 1 Module Stop */ + __IOM uint32_t MSTPB9 : 1; /*!< [9..9] IIC/I3C Bus Interface 0 Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface Module Stop */ + __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface Module Stop */ + __IOM uint32_t MSTPB13 : 1; /*!< [13..13] EPTPC and PTPEDMAC Module Stop */ + __IOM uint32_t MSTPB14 : 1; /*!< [14..14] ETHERC1 and EDMAC1 Module Stop */ + __IOM uint32_t MSTPB15 : 1; /*!< [15..15] ETHERC0 and EDMAC0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Serial Peripheral Interface Module Stop */ + __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Serial Communication Interface 9 Module Stop */ + __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Serial Communication Interface 8 Module Stop */ + __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Serial Communication Interface 7 Module Stop */ + __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Serial Communication Interface 6 Module Stop */ + __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Serial Communication Interface 5 Module Stop */ + __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Serial Communication Interface 4 Module Stop */ + __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Serial Communication Interface 3 Module Stop */ + __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Serial Communication Interface 2 Module Stop */ + __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Serial Communication Interface 1 Module Stop */ + __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Serial Communication Interface 0 Module Stop */ + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000008) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPC0 : 1; /*!< [0..0] CAC Module Stop */ + __IOM uint32_t MSTPC1 : 1; /*!< [1..1] CRC Calculator Module Stop */ + __IOM uint32_t MSTPC2 : 1; /*!< [2..2] Parallel Data Capture Module Stop */ + __IOM uint32_t MSTPC3 : 1; /*!< [3..3] Capacitive Touch Sensing Unit Module Stop */ + __IOM uint32_t MSTPC4 : 1; /*!< [4..4] Segment LCD Controller Module Stop */ + __IOM uint32_t MSTPC5 : 1; /*!< [5..5] JPEG codec engine Module Stop */ + __IOM uint32_t MSTPC6 : 1; /*!< [6..6] 2DG engine Module Stop */ + __IOM uint32_t MSTPC7 : 1; /*!< [7..7] Synchronous Serial Interface 1 Module Stop */ + __IOM uint32_t MSTPC8 : 1; /*!< [8..8] Synchronous Serial Interface 0 Module Stop */ + __IOM uint32_t MSTPC9 : 1; /*!< [9..9] Sampling Rate Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Secure Digital Host IF/ Multi Media Card 1 Module Stop */ + __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ + __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ + __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ + __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ + uint32_t : 5; + __IOM uint32_t MSTPC27 : 1; /*!< [27..27] CANFD Module Stop */ + __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Random Number Generator Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPC31 : 1; /*!< [31..31] AES Module Stop */ + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000000C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPD0 : 1; /*!< [0..0] Low Power Asynchronous General Purpose Timer 3 Module + * Stop */ + __IOM uint32_t MSTPD1 : 1; /*!< [1..1] Low Power Asynchronous General Purpose Timer 2 Module + * Stop */ + __IOM uint32_t MSTPD2 : 1; /*!< [2..2] AGT1 Module StopNote: AGT1 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT1. */ + __IOM uint32_t MSTPD3 : 1; /*!< [3..3] AGT0 Module StopNote: AGT0 is in the module stop state + * when the count source is either of PCLKB, PCLKB/2 or PCLKB/8. + * In case the count source is sub-clock or LOCO, this bit + * should be set to 1 except when accessing the registers + * of AGT0. */ + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ + __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ + __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ + __IOM uint32_t MSTPD14 : 1; /*!< [14..14] POEG Module Stop */ + __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ + __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ + __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ + __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Temperature Sensor Module Stop */ + __IOM uint32_t MSTPD23 : 1; /*!< [23..23] ACMPHS5 Module Stop */ + __IOM uint32_t MSTPD24 : 1; /*!< [24..24] ACMPHS4 Module Stop */ + __IOM uint32_t MSTPD25 : 1; /*!< [25..25] ACMPHS3 Module Stop */ + __IOM uint32_t MSTPD26 : 1; /*!< [26..26] ACMPHS2 Module Stop */ + __IOM uint32_t MSTPD27 : 1; /*!< [27..27] ACMPHS1 Module Stop */ + __IOM uint32_t MSTPD28 : 1; /*!< [28..28] ACMPHS0 Module Stop */ + __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Comparator-LP Module Stop */ + uint32_t : 1; + __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Operational Amplifier Module Stop */ + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000010) Module Stop Control Register E */ + + struct + { + uint32_t : 4; + __IOM uint32_t MSTPE4 : 1; /*!< [4..4] KINT Module Stop */ + uint32_t : 9; + __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Low Power Asynchronous General Purpose Timer 5 Module + * Stop */ + __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Low Power Asynchronous General Purpose Timer 4 Module + * Stop */ + uint32_t : 6; + __IOM uint32_t MSTPE22 : 1; /*!< [22..22] GPT9 Module Stop */ + __IOM uint32_t MSTPE23 : 1; /*!< [23..23] GPT8 Module Stop */ + __IOM uint32_t MSTPE24 : 1; /*!< [24..24] GPT7 Module Stop */ + __IOM uint32_t MSTPE25 : 1; /*!< [25..25] GPT6 Module Stop */ + __IOM uint32_t MSTPE26 : 1; /*!< [26..26] GPT5 Module Stop */ + __IOM uint32_t MSTPE27 : 1; /*!< [27..27] GPT4 Module Stop */ + __IOM uint32_t MSTPE28 : 1; /*!< [28..28] GPT3 Module Stop */ + __IOM uint32_t MSTPE29 : 1; /*!< [29..29] GPT2 Module Stop */ + __IOM uint32_t MSTPE30 : 1; /*!< [30..30] GPT1 Module Stop */ + __IOM uint32_t MSTPE31 : 1; /*!< [31..31] GPT0 Module Stop */ + } MSTPCRE_b; + }; +} R_MSTP_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (R_PORT0) + */ + +typedef struct /*!< (@ 0x4001F000) R_PORT0 Structure */ +{ + union + { + union + { + __IOM uint32_t PCNTR1; /*!< (@ 0x00000000) Port Control Register 1 */ + + struct + { + __IOM uint32_t PDR : 16; /*!< [15..0] Pmn Direction */ + __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data */ + } PCNTR1_b; + }; + + struct + { + union + { + __IOM uint16_t PDR; /*!< (@ 0x00000000) Data direction register */ + + struct + { + __IOM uint16_t PDR0 : 1; /*!< [0..0] Pmn Direction */ + __IOM uint16_t PDR1 : 1; /*!< [1..1] Pmn Direction */ + __IOM uint16_t PDR2 : 1; /*!< [2..2] Pmn Direction */ + __IOM uint16_t PDR3 : 1; /*!< [3..3] Pmn Direction */ + __IOM uint16_t PDR4 : 1; /*!< [4..4] Pmn Direction */ + __IOM uint16_t PDR5 : 1; /*!< [5..5] Pmn Direction */ + __IOM uint16_t PDR6 : 1; /*!< [6..6] Pmn Direction */ + __IOM uint16_t PDR7 : 1; /*!< [7..7] Pmn Direction */ + __IOM uint16_t PDR8 : 1; /*!< [8..8] Pmn Direction */ + __IOM uint16_t PDR9 : 1; /*!< [9..9] Pmn Direction */ + __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction */ + __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction */ + __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction */ + __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction */ + __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction */ + __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction */ + } PDR_b; + }; + + union + { + __IOM uint16_t P0DR; /*!< (@ 0x00000002) Output data register */ + + struct + { + __IOM uint16_t PODR0 : 1; /*!< [0..0] Pmn Output Data */ + __IOM uint16_t PODR1 : 1; /*!< [1..1] Pmn Output Data */ + __IOM uint16_t PODR2 : 1; /*!< [2..2] Pmn Output Data */ + __IOM uint16_t PODR3 : 1; /*!< [3..3] Pmn Output Data */ + __IOM uint16_t PODR4 : 1; /*!< [4..4] Pmn Output Data */ + __IOM uint16_t PODR5 : 1; /*!< [5..5] Pmn Output Data */ + __IOM uint16_t PODR6 : 1; /*!< [6..6] Pmn Output Data */ + __IOM uint16_t PODR7 : 1; /*!< [7..7] Pmn Output Data */ + __IOM uint16_t PODR8 : 1; /*!< [8..8] Pmn Output Data */ + __IOM uint16_t PODR9 : 1; /*!< [9..9] Pmn Output Data */ + __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data */ + __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data */ + __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data */ + __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data */ + __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data */ + __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data */ + } P0DR_b; + }; + }; + }; + + union + { + union + { + __IM uint32_t PCNTR2; /*!< (@ 0x00000004) Port Control Register 2 */ + + struct + { + __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data */ + __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data */ + } PCNTR2_b; + }; + + struct + { + union + { + __IM uint16_t PIDR; /*!< (@ 0x00000004) Input data register */ + + struct + { + __IM uint16_t PIDR0 : 1; /*!< [0..0] Pmn Input Data */ + __IM uint16_t PIDR1 : 1; /*!< [1..1] Pmn Input Data */ + __IM uint16_t PIDR2 : 1; /*!< [2..2] Pmn Input Data */ + __IM uint16_t PIDR3 : 1; /*!< [3..3] Pmn Input Data */ + __IM uint16_t PIDR4 : 1; /*!< [4..4] Pmn Input Data */ + __IM uint16_t PIDR5 : 1; /*!< [5..5] Pmn Input Data */ + __IM uint16_t PIDR6 : 1; /*!< [6..6] Pmn Input Data */ + __IM uint16_t PIDR7 : 1; /*!< [7..7] Pmn Input Data */ + __IM uint16_t PIDR8 : 1; /*!< [8..8] Pmn Input Data */ + __IM uint16_t PIDR9 : 1; /*!< [9..9] Pmn Input Data */ + __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data */ + __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data */ + __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data */ + __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data */ + __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data */ + __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data */ + } PIDR_b; + }; + + union + { + __IM uint16_t EIDR; /*!< (@ 0x00000006) Event input data register */ + + struct + { + __IM uint16_t EIDR0 : 1; /*!< [0..0] Pmn Event Input Data */ + __IM uint16_t EIDR1 : 1; /*!< [1..1] Pmn Event Input Data */ + __IM uint16_t EIDR2 : 1; /*!< [2..2] Pmn Event Input Data */ + __IM uint16_t EIDR3 : 1; /*!< [3..3] Pmn Event Input Data */ + __IM uint16_t EIDR4 : 1; /*!< [4..4] Pmn Event Input Data */ + __IM uint16_t EIDR5 : 1; /*!< [5..5] Pmn Event Input Data */ + __IM uint16_t EIDR6 : 1; /*!< [6..6] Pmn Event Input Data */ + __IM uint16_t EIDR7 : 1; /*!< [7..7] Pmn Event Input Data */ + __IM uint16_t EIDR8 : 1; /*!< [8..8] Pmn Event Input Data */ + __IM uint16_t EIDR9 : 1; /*!< [9..9] Pmn Event Input Data */ + __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data */ + __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data */ + __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data */ + __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data */ + __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data */ + __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data */ + } EIDR_b; + }; + }; + }; + + union + { + union + { + __OM uint32_t PCNTR3; /*!< (@ 0x00000008) Port Control Register 3 */ + + struct + { + __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set */ + __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset */ + } PCNTR3_b; + }; + + struct + { + union + { + __OM uint16_t POSR; /*!< (@ 0x00000008) Output reset register */ + + struct + { + __OM uint16_t POSR0 : 1; /*!< [0..0] Pmn Output Set */ + __OM uint16_t POSR1 : 1; /*!< [1..1] Pmn Output Set */ + __OM uint16_t POSR2 : 1; /*!< [2..2] Pmn Output Set */ + __OM uint16_t POSR3 : 1; /*!< [3..3] Pmn Output Set */ + __OM uint16_t POSR4 : 1; /*!< [4..4] Pmn Output Set */ + __OM uint16_t POSR5 : 1; /*!< [5..5] Pmn Output Set */ + __OM uint16_t POSR6 : 1; /*!< [6..6] Pmn Output Set */ + __OM uint16_t POSR7 : 1; /*!< [7..7] Pmn Output Set */ + __OM uint16_t POSR8 : 1; /*!< [8..8] Pmn Output Set */ + __OM uint16_t POSR9 : 1; /*!< [9..9] Pmn Output Set */ + __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set */ + __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set */ + __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set */ + __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set */ + __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set */ + __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set */ + } POSR_b; + }; + + union + { + __OM uint16_t PORR; /*!< (@ 0x0000000A) Output set register */ + + struct + { + __OM uint16_t PORR0 : 1; /*!< [0..0] Pmn Output Reset */ + __OM uint16_t PORR1 : 1; /*!< [1..1] Pmn Output Reset */ + __OM uint16_t PORR2 : 1; /*!< [2..2] Pmn Output Reset */ + __OM uint16_t PORR3 : 1; /*!< [3..3] Pmn Output Reset */ + __OM uint16_t PORR4 : 1; /*!< [4..4] Pmn Output Reset */ + __OM uint16_t PORR5 : 1; /*!< [5..5] Pmn Output Reset */ + __OM uint16_t PORR6 : 1; /*!< [6..6] Pmn Output Reset */ + __OM uint16_t PORR7 : 1; /*!< [7..7] Pmn Output Reset */ + __OM uint16_t PORR8 : 1; /*!< [8..8] Pmn Output Reset */ + __OM uint16_t PORR9 : 1; /*!< [9..9] Pmn Output Reset */ + __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset */ + __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset */ + __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset */ + __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset */ + __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset */ + __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset */ + } PORR_b; + }; + }; + }; + + union + { + union + { + __IOM uint32_t PCNTR4; /*!< (@ 0x0000000C) Port Control Register 4 */ + + struct + { + __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set */ + __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset */ + } PCNTR4_b; + }; + + struct + { + union + { + __IOM uint16_t EOSR; /*!< (@ 0x0000000C) Event output reset register */ + + struct + { + __IOM uint16_t EOSR0 : 1; /*!< [0..0] Pmn Event Output Set */ + __IOM uint16_t EOSR1 : 1; /*!< [1..1] Pmn Event Output Set */ + __IOM uint16_t EOSR2 : 1; /*!< [2..2] Pmn Event Output Set */ + __IOM uint16_t EOSR3 : 1; /*!< [3..3] Pmn Event Output Set */ + __IOM uint16_t EOSR4 : 1; /*!< [4..4] Pmn Event Output Set */ + __IOM uint16_t EOSR5 : 1; /*!< [5..5] Pmn Event Output Set */ + __IOM uint16_t EOSR6 : 1; /*!< [6..6] Pmn Event Output Set */ + __IOM uint16_t EOSR7 : 1; /*!< [7..7] Pmn Event Output Set */ + __IOM uint16_t EOSR8 : 1; /*!< [8..8] Pmn Event Output Set */ + __IOM uint16_t EOSR9 : 1; /*!< [9..9] Pmn Event Output Set */ + __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set */ + __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set */ + __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set */ + __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set */ + __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set */ + __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set */ + } EOSR_b; + }; + + union + { + __IOM uint16_t EORR; /*!< (@ 0x0000000E) Event output set register */ + + struct + { + __IOM uint16_t EORR0 : 1; /*!< [0..0] Pmn Event Output Reset */ + __IOM uint16_t EORR1 : 1; /*!< [1..1] Pmn Event Output Reset */ + __IOM uint16_t EORR2 : 1; /*!< [2..2] Pmn Event Output Reset */ + __IOM uint16_t EORR3 : 1; /*!< [3..3] Pmn Event Output Reset */ + __IOM uint16_t EORR4 : 1; /*!< [4..4] Pmn Event Output Reset */ + __IOM uint16_t EORR5 : 1; /*!< [5..5] Pmn Event Output Reset */ + __IOM uint16_t EORR6 : 1; /*!< [6..6] Pmn Event Output Reset */ + __IOM uint16_t EORR7 : 1; /*!< [7..7] Pmn Event Output Reset */ + __IOM uint16_t EORR8 : 1; /*!< [8..8] Pmn Event Output Reset */ + __IOM uint16_t EORR9 : 1; /*!< [9..9] Pmn Event Output Reset */ + __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset */ + __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset */ + __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset */ + __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset */ + __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset */ + __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset */ + } EORR_b; + }; + }; + }; +} R_PORT0_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-PFS (R_PFS) + */ + +typedef struct /*!< (@ 0x4001F800) R_PFS Structure */ +{ + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports-MISC (R_PMISC) + */ + +typedef struct /*!< (@ 0x4001FD00) R_PMISC Structure */ +{ + __IOM uint8_t PFENET; /*!< (@ 0x00000000) Ethernet Control Register */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[5]; + + union + { + __IOM uint8_t PWPR; /*!< (@ 0x0000000C) Write-Protect Register */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3[3]; + + union + { + __IOM uint8_t PWPRS; /*!< (@ 0x00000014) Write-Protect Register for Secure */ + + struct + { + uint8_t : 6; + __IOM uint8_t PFSWE : 1; /*!< [6..6] PmnPFS Register Write */ + __IOM uint8_t B0WI : 1; /*!< [7..7] PFSWE Bit Write Disable */ + } PWPRS_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[13]; + __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register */ +} R_PMISC_Type; /*!< Size = 108 (0x6c) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communications Interface (R_SCI0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI0 Structure */ +{ + union + { + union + { + __IOM uint8_t SMR; /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t MP : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode) */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t CHR : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode) */ + __IOM uint8_t CM : 1; /*!< [7..7] Communication Mode */ + } SMR_b; + }; + + union + { + __IOM uint8_t SMR_SMCI; /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select */ + __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode) */ + __IOM uint8_t PM : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1) */ + __IOM uint8_t PE : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode) */ + __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode */ + __IOM uint8_t GM : 1; /*!< [7..7] GSM Mode */ + } SMR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t BRR; /*!< (@ 0x00000001) Bit Rate Register */ + + struct + { + __IOM uint8_t BRR : 8; /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate. */ + } BRR_b; + }; + + union + { + union + { + __IOM uint8_t SCR; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous + * mode when SMR.MP = 1) */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_b; + }; + + union + { + __IOM uint8_t SCR_SMCI; /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1) */ + + struct + { + __IOM uint8_t CKE : 2; /*!< [1..0] Clock Enable */ + __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable */ + __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable */ + __IOM uint8_t RE : 1; /*!< [4..4] Receive Enable */ + __IOM uint8_t TE : 1; /*!< [5..5] Transmit Enable */ + __IOM uint8_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Interrupt Enable */ + } SCR_SMCI_b; + }; + }; + + union + { + __IOM uint8_t TDR; /*!< (@ 0x00000003) Transmit Data Register */ + + struct + { + __IOM uint8_t TDR : 8; /*!< [7..0] TDR is an 8-bit register that stores transmit data. */ + } TDR_b; + }; + + union + { + union + { + __IOM uint8_t SSR; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-Processor */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_b; + }; + + union + { + __IOM uint8_t SSR_FIFO; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1) */ + + struct + { + __IOM uint8_t DR : 1; /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including + * multi-processor) and FIFO selected) */ + uint8_t : 1; + __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t FER : 1; /*!< [4..4] Framing Error Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag */ + __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag */ + } SSR_FIFO_b; + }; + + union + { + __IOM uint8_t SSR_SMCI; /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1) */ + + struct + { + __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart + * card interface mode. */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface + * mode. */ + __IM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag */ + __IOM uint8_t PER : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag */ + __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag */ + __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } SSR_SMCI_b; + }; + }; + + union + { + __IM uint8_t RDR; /*!< (@ 0x00000005) Receive Data Register */ + + struct + { + __IM uint8_t RDR : 8; /*!< [7..0] RDR is an 8-bit register that stores receive data. */ + } RDR_b; + }; + + union + { + __IOM uint8_t SCMR; /*!< (@ 0x00000006) Smart Card Mode Register */ + + struct + { + __IOM uint8_t SMIF : 1; /*!< [0..0] Smart Card Interface Mode Select */ + uint8_t : 1; + __IOM uint8_t SINV : 1; /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if + * operation is to be in simple I2C mode. */ + __IOM uint8_t SDIR : 1; /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The + * setting is invalid and a fixed data length of 8 bits is + * used in modes other than asynchronous mode.Set this bit + * to 1 if operation is to be in simple I2C mode. */ + __IOM uint8_t CHR1 : 1; /*!< [4..4] Character Length 1(Only valid in asynchronous mode) */ + uint8_t : 2; + __IOM uint8_t BCP2 : 1; /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles + * in combination with the SMR.BCP[1:0] bits */ + } SCMR_b; + }; + + union + { + __IOM uint8_t SEMR; /*!< (@ 0x00000007) Serial Extended Mode Register */ + + struct + { + __IOM uint8_t ACS0 : 1; /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in + * asynchronous mode). */ + __IOM uint8_t PADIS : 1; /*!< [1..1] Preamble function Disable (Valid only in asynchronous + * mode). */ + __IOM uint8_t BRME : 1; /*!< [2..2] Bit Rate Modulation Enable */ + __IOM uint8_t ABCSE : 1; /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid + * only in asynchronous mode and SCR.CKE[1]=0) */ + __IOM uint8_t ABCS : 1; /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous + * mode) */ + __IOM uint8_t NFEN : 1; /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should + * be 0 without simple I2C mode and asynchronous mode.)In + * asynchronous mode, for RXDn input only. In simple I2C mode, + * for RXDn/TxDn input. */ + __IOM uint8_t BGDM : 1; /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid + * the CKE[1] bit in SCR is 0 in asynchronous mode). */ + __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only + * in asynchronous mode) */ + } SEMR_b; + }; + + union + { + __IOM uint8_t SNFR; /*!< (@ 0x00000008) Noise Filter Setting Register */ + + struct + { + __IOM uint8_t NFCS : 3; /*!< [2..0] Noise Filter Clock Select */ + uint8_t : 5; + } SNFR_b; + }; + + union + { + __IOM uint8_t SIMR1; /*!< (@ 0x00000009) I2C Mode Register 1 */ + + struct + { + __IOM uint8_t IICM : 1; /*!< [0..0] Simple I2C Mode Select */ + uint8_t : 2; + __IOM uint8_t IICDL : 5; /*!< [7..3] SDA Delay Output SelectCycles below are of the clock + * signal from the on-chip baud rate generator. */ + } SIMR1_b; + }; + + union + { + __IOM uint8_t SIMR2; /*!< (@ 0x0000000A) I2C Mode Register 2 */ + + struct + { + __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select */ + __IOM uint8_t IICCSC : 1; /*!< [1..1] Clock Synchronization */ + uint8_t : 3; + __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data */ + uint8_t : 2; + } SIMR2_b; + }; + + union + { + __IOM uint8_t SIMR3; /*!< (@ 0x0000000B) I2C Mode Register 3 */ + + struct + { + __IOM uint8_t IICSTAREQ : 1; /*!< [0..0] Start Condition Generation */ + __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation */ + __IOM uint8_t IICSTPREQ : 1; /*!< [2..2] Stop Condition Generation */ + __IOM uint8_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag(When 0 is written to IICSTIF, it is cleared to 0.) */ + __IOM uint8_t IICSDAS : 2; /*!< [5..4] SDA Output Select */ + __IOM uint8_t IICSCLS : 2; /*!< [7..6] SCL Output Select */ + } SIMR3_b; + }; + + union + { + __IM uint8_t SISR; /*!< (@ 0x0000000C) I2C Status Register */ + + struct + { + __IM uint8_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint8_t : 7; + } SISR_b; + }; + + union + { + __IOM uint8_t SPMR; /*!< (@ 0x0000000D) SPI Mode Register */ + + struct + { + __IOM uint8_t SSE : 1; /*!< [0..0] SSn Pin Function Enable */ + __IOM uint8_t CTSE : 1; /*!< [1..1] CTS Enable */ + __IOM uint8_t MSS : 1; /*!< [2..2] Master Slave Select */ + __IOM uint8_t CSTPEN : 1; /*!< [3..3] CTS external pin Enable */ + __IOM uint8_t MFF : 1; /*!< [4..4] Mode Fault Flag */ + uint8_t : 1; + __IOM uint8_t CKPOL : 1; /*!< [6..6] Clock Polarity Select */ + __IOM uint8_t CKPH : 1; /*!< [7..7] Clock Phase Select */ + } SPMR_b; + }; + + union + { + union + { + __IOM uint16_t TDRHL; /*!< (@ 0x0000000E) Transmit 9-bit Data Register */ + + struct + { + __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data. */ + } TDRHL_b; + }; + + union + { + __OM uint16_t FTDRHL; /*!< (@ 0x0000000E) Transmit FIFO Data Register HL */ + + struct + { + __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint16_t : 6; + } FTDRHL_b; + }; + + struct + { + union + { + __OM uint8_t FTDRH; /*!< (@ 0x0000000E) Transmit FIFO Data Register H */ + + struct + { + __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + __OM uint8_t MPBT : 1; /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous + * mode and SMR.MP=1 and FIFO selected) */ + uint8_t : 6; + } FTDRH_b; + }; + + union + { + __OM uint8_t FTDRL; /*!< (@ 0x0000000F) Transmit FIFO Data Register L */ + + struct + { + __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * and FIFO selected) */ + } FTDRL_b; + }; + }; + }; + + union + { + union + { + __IM uint16_t RDRHL; /*!< (@ 0x00000010) Receive 9-bit Data Register */ + + struct + { + __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data. */ + } RDRHL_b; + }; + + union + { + __IM uint16_t FRDRHL; /*!< (@ 0x00000010) Receive FIFO Data Register HL */ + + struct + { + __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint16_t MPB : 1; /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint16_t DR : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR) */ + __IM uint16_t PER : 1; /*!< [11..11] Parity error flag */ + __IM uint16_t FER : 1; /*!< [12..12] Framing error flag */ + __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER) */ + __IM uint16_t RDF : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint16_t : 1; + } FRDRHL_b; + }; + + struct + { + union + { + __IM uint8_t FRDRH; /*!< (@ 0x00000010) Receive FIFO Data Register H */ + + struct + { + __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + __IM uint8_t MPB : 1; /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode + * with SMR.MP=1 and FIFO selected) It can read multi-processor + * bit corresponded to serial receive data(RDATA[8:0]) */ + __IM uint8_t DR : 1; /*!< [2..2] Receive data ready flag(It is same as SSR.DR) */ + __IM uint8_t PER : 1; /*!< [3..3] Parity error flag */ + __IM uint8_t FER : 1; /*!< [4..4] Framing error flag */ + __IM uint8_t ORER : 1; /*!< [5..5] Overrun error flag(It is same as SSR.ORER) */ + __IM uint8_t RDF : 1; /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF) */ + uint8_t : 1; + } FRDRH_b; + }; + + union + { + __IM uint8_t FRDRL; /*!< (@ 0x00000011) Receive FIFO Data Register L */ + + struct + { + __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected)NOTE: + * When reading both of FRDRH register and FRDRL register, + * please read by an order of the FRDRH register and the FRDRL + * register. */ + } FRDRL_b; + }; + }; + }; + + union + { + __IOM uint8_t MDDR; /*!< (@ 0x00000012) Modulation Duty Register */ + + struct + { + __IOM uint8_t MDDR : 8; /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register. */ + } MDDR_b; + }; + + union + { + __IOM uint8_t DCCR; /*!< (@ 0x00000013) Data Compare Match Control Register */ + + struct + { + __IOM uint8_t DCMF : 1; /*!< [0..0] Data Compare Match Flag */ + uint8_t : 2; + __IOM uint8_t DPER : 1; /*!< [3..3] Data Compare Match Parity Error Flag */ + __IOM uint8_t DFER : 1; /*!< [4..4] Data Compare Match Framing Error Flag */ + uint8_t : 1; + __IOM uint8_t IDSEL : 1; /*!< [6..6] ID frame select(Valid only in asynchronous mode(including + * multi-processor) */ + __IOM uint8_t DCME : 1; /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous + * mode(including multi-processor) */ + } DCCR_b; + }; + + union + { + __IOM uint16_t FCR; /*!< (@ 0x00000014) FIFO Control Register */ + + struct + { + __IOM uint16_t FM : 1; /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode) */ + __IOM uint16_t RFRST : 1; /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t TFRST : 1; /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) */ + __IOM uint16_t DRES : 1; /*!< [3..3] Receive data ready error select bit(When detecting a + * reception data ready, the interrupt request is selected.) */ + __IOM uint16_t TTRG : 4; /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RTRG : 4; /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode) */ + __IOM uint16_t RSTRG : 4; /*!< [15..12] RTS Output Active Trigger Number Select(Valid only + * in asynchronous mode(including multi-processor) or clock + * synchronous mode) */ + } FCR_b; + }; + + union + { + __IM uint16_t FDR; /*!< (@ 0x00000016) FIFO Data Count Register */ + + struct + { + __IM uint16_t R : 5; /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive + * data stored in FRDRH and FRDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + __IM uint16_t T : 5; /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit + * data stored in FTDRH and FTDRL(Valid only in asynchronous + * mode(including multi-processor) or clock synchronous mode, + * while FCR.FM=1) */ + uint16_t : 3; + } FDR_b; + }; + + union + { + __IM uint16_t LSR; /*!< (@ 0x00000018) Line Status Register */ + + struct + { + __IM uint16_t ORER : 1; /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including + * multi-processor) or clock synchronous mode, and FIFO selected) */ + uint16_t : 1; + __IM uint16_t FNUM : 5; /*!< [6..2] Framing Error CountIndicates the quantity of data with + * a framing error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 1; + __IM uint16_t PNUM : 5; /*!< [12..8] Parity Error CountIndicates the quantity of data with + * a parity error among the receive data stored in the receive + * FIFO data register (FRDRH and FRDRL). */ + uint16_t : 3; + } LSR_b; + }; + + union + { + __IOM uint16_t CDR; /*!< (@ 0x0000001A) Compare Match Data Register */ + + struct + { + __IOM uint16_t CMPD : 9; /*!< [8..0] Compare Match DataCompare data pattern for address match + * wake-up function */ + uint16_t : 7; + } CDR_b; + }; + + union + { + __IOM uint8_t SPTR; /*!< (@ 0x0000001C) Serial Port Register */ + + struct + { + __IM uint8_t RXDMON : 1; /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal + * is shown.) */ + __IOM uint8_t SPB2DT : 1; /*!< [1..1] Serial port break data select bit(The output level of + * TxD terminal is selected when SCR.TE = 0.) */ + __IOM uint8_t SPB2IO : 1; /*!< [2..2] Serial port break I/O bit(It's selected whether the value + * of SPB2DT is output to TxD terminal.) */ + uint8_t : 1; + __IOM uint8_t RINV : 1; /*!< [4..4] RXD invert bit */ + __IOM uint8_t TINV : 1; /*!< [5..5] TXD invert bit */ + __IOM uint8_t ASEN : 1; /*!< [6..6] Adjust receive sampling timing enable */ + __IOM uint8_t ATEN : 1; /*!< [7..7] Adjust transmit timing enable */ + } SPTR_b; + }; + + union + { + __IOM uint8_t ACTR; /*!< (@ 0x0000001D) Adjustment Communication Timing Register */ + + struct + { + __IOM uint8_t AST : 3; /*!< [2..0] Adjustment value for receive Sampling Timing */ + __IOM uint8_t AJD : 1; /*!< [3..3] Adjustment Direction for receive sampling timing */ + __IOM uint8_t ATT : 3; /*!< [6..4] Adjustment value for Transmit timing */ + __IOM uint8_t AET : 1; /*!< [7..7] Adjustment edge for transmit timing */ + } ACTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint8_t ESMER; /*!< (@ 0x00000020) Extended Serial Module Enable Register */ + + struct + { + __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable */ + uint8_t : 7; + } ESMER_b; + }; + + union + { + __IOM uint8_t CR0; /*!< (@ 0x00000021) Control Register 0 */ + + struct + { + uint8_t : 1; + __IM uint8_t SFSF : 1; /*!< [1..1] Start Frame Status Flag */ + __IM uint8_t RXDSF : 1; /*!< [2..2] RXDXn Input Status Flag */ + __IOM uint8_t BRME : 1; /*!< [3..3] Bit Rate Measurement Enable */ + uint8_t : 4; + } CR0_b; + }; + + union + { + __IOM uint8_t CR1; /*!< (@ 0x00000022) Control Register 1 */ + + struct + { + __IOM uint8_t BFE : 1; /*!< [0..0] Break Field Enable */ + __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable */ + __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select */ + __IOM uint8_t PIBE : 1; /*!< [4..4] Priority Interrupt Bit Enable */ + __IOM uint8_t PIBS : 3; /*!< [7..5] Priority Interrupt Bit Select */ + } CR1_b; + }; + + union + { + __IOM uint8_t CR2; /*!< (@ 0x00000023) Control Register 2 */ + + struct + { + __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select */ + uint8_t : 1; + __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select */ + __IOM uint8_t RTS : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select */ + } CR2_b; + }; + + union + { + __IOM uint8_t CR3; /*!< (@ 0x00000024) Control Register 3 */ + + struct + { + __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start */ + uint8_t : 7; + } CR3_b; + }; + + union + { + __IOM uint8_t PCR; /*!< (@ 0x00000025) Port Control Register */ + + struct + { + __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select */ + __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select */ + uint8_t : 2; + __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select */ + uint8_t : 3; + } PCR_b; + }; + + union + { + __IOM uint8_t ICR; /*!< (@ 0x00000026) Interrupt Control Register */ + + struct + { + __IOM uint8_t BFDIE : 1; /*!< [0..0] Break Field Low Width Detected Interrupt Enable */ + __IOM uint8_t CF0MIE : 1; /*!< [1..1] Control Field 0 Match Detected Interrupt Enable */ + __IOM uint8_t CF1MIE : 1; /*!< [2..2] Control Field 1 Match Detected Interrupt Enable */ + __IOM uint8_t PIBDIE : 1; /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable */ + __IOM uint8_t BCDIE : 1; /*!< [4..4] Bus Collision Detected Interrupt Enable */ + __IOM uint8_t AEDIE : 1; /*!< [5..5] Valid Edge Detected Interrupt Enable */ + uint8_t : 2; + } ICR_b; + }; + + union + { + __IM uint8_t STR; /*!< (@ 0x00000027) Status Register */ + + struct + { + __IM uint8_t BFDF : 1; /*!< [0..0] Break Field Low Width Detection Flag */ + __IM uint8_t CF0MF : 1; /*!< [1..1] Control Field 0 Match Flag */ + __IM uint8_t CF1MF : 1; /*!< [2..2] Control Field 1 Match Flag */ + __IM uint8_t PIBDF : 1; /*!< [3..3] Priority Interrupt Bit Detection Flag */ + __IM uint8_t BCDF : 1; /*!< [4..4] Bus Collision Detected Flag */ + __IM uint8_t AEDF : 1; /*!< [5..5] Valid Edge Detection Flag */ + uint8_t : 2; + } STR_b; + }; + + union + { + __IOM uint8_t STCR; /*!< (@ 0x00000028) Status Clear Register */ + + struct + { + __IOM uint8_t BFDCL : 1; /*!< [0..0] BFDF Clear */ + __IOM uint8_t CF0MCL : 1; /*!< [1..1] CF0MF Clear */ + __IOM uint8_t CF1MCL : 1; /*!< [2..2] CF1MF Clear */ + __IOM uint8_t PIBDCL : 1; /*!< [3..3] PIBDF Clear */ + __IOM uint8_t BCDCL : 1; /*!< [4..4] BCDF Clear */ + __IOM uint8_t AEDCL : 1; /*!< [5..5] AEDF Clear */ + uint8_t : 2; + } STCR_b; + }; + __IOM uint8_t CF0DR; /*!< (@ 0x00000029) Control Field 0 Data Register */ + + union + { + __IOM uint8_t CF0CR; /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register */ + + struct + { + __IOM uint8_t CF0CE0 : 1; /*!< [0..0] Control Field 0 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE1 : 1; /*!< [1..1] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE2 : 1; /*!< [2..2] Control Field 2 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE3 : 1; /*!< [3..3] Control Field 3 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE4 : 1; /*!< [4..4] Control Field 4 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE5 : 1; /*!< [5..5] Control Field 5 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE6 : 1; /*!< [6..6] Control Field 6 Bit 0 Compare Enable */ + __IOM uint8_t CF0CE7 : 1; /*!< [7..7] Control Field 7 Bit 0 Compare Enable */ + } CF0CR_b; + }; + __IOM uint8_t CF0RR; /*!< (@ 0x0000002B) Control Field 0 Receive Data Register */ + __IOM uint8_t PCF1DR; /*!< (@ 0x0000002C) Primary Control Field 1 Data Register */ + __IOM uint8_t SCF1DR; /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register */ + + union + { + __IOM uint8_t CF1CR; /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register */ + + struct + { + __IOM uint8_t CF1CE0 : 1; /*!< [0..0] Control Field 1 Bit 0 Compare Enable */ + __IOM uint8_t CF1CE1 : 1; /*!< [1..1] Control Field 1 Bit 1 Compare Enable */ + __IOM uint8_t CF1CE2 : 1; /*!< [2..2] Control Field 1 Bit 2 Compare Enable */ + __IOM uint8_t CF1CE3 : 1; /*!< [3..3] Control Field 1 Bit 3 Compare Enable */ + __IOM uint8_t CF1CE4 : 1; /*!< [4..4] Control Field 1 Bit 4 Compare Enable */ + __IOM uint8_t CF1CE5 : 1; /*!< [5..5] Control Field 1 Bit 5 Compare Enable */ + __IOM uint8_t CF1CE6 : 1; /*!< [6..6] Control Field 1 Bit 6 Compare Enable */ + __IOM uint8_t CF1CE7 : 1; /*!< [7..7] Control Field 1 Bit 7 Compare Enable */ + } CF1CR_b; + }; + __IOM uint8_t CF1RR; /*!< (@ 0x0000002F) Control Field 1 Receive Data Register */ + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000030) Timer Control Register */ + + struct + { + __IOM uint8_t TCST : 1; /*!< [0..0] Timer Count Start */ + uint8_t : 7; + } TCR_b; + }; + + union + { + __IOM uint8_t TMR; /*!< (@ 0x00000031) Timer Mode Register */ + + struct + { + __IOM uint8_t TOMS : 2; /*!< [1..0] Timer Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t TWRC : 1; /*!< [3..3] Counter Write Control */ + __IOM uint8_t TCSS : 3; /*!< [6..4] Timer Count Clock Source Select */ + uint8_t : 1; + } TMR_b; + }; + __IOM uint8_t TPRE; /*!< (@ 0x00000032) Timer Prescaler Register */ + __IOM uint8_t TCNT; /*!< (@ 0x00000033) Timer Count Register */ +} R_SCI0_Type; /*!< Size = 52 (0x34) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface (R_SPI0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure */ +{ + union + { + __IOM uint8_t SPCR; /*!< (@ 0x00000000) SPI Control Register */ + + struct + { + __IOM uint8_t SPMS : 1; /*!< [0..0] SPI Mode Select */ + __IOM uint8_t TXMD : 1; /*!< [1..1] Communications Operating Mode Select */ + __IOM uint8_t MODFEN : 1; /*!< [2..2] Mode Fault Error Detection Enable */ + __IOM uint8_t MSTR : 1; /*!< [3..3] SPI Master/Slave Mode Select */ + __IOM uint8_t SPEIE : 1; /*!< [4..4] SPI Error Interrupt Enable */ + __IOM uint8_t SPTIE : 1; /*!< [5..5] Transmit Buffer Empty Interrupt Enable */ + __IOM uint8_t SPE : 1; /*!< [6..6] SPI Function Enable */ + __IOM uint8_t SPRIE : 1; /*!< [7..7] SPI Receive Buffer Full Interrupt Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000001) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + __IOM uint8_t SSL4P : 1; /*!< [4..4] SSL4 Signal Polarity Setting */ + __IOM uint8_t SSL5P : 1; /*!< [5..5] SSL5 Signal Polarity Setting */ + __IOM uint8_t SSL6P : 1; /*!< [6..6] SSL6 Signal Polarity Setting */ + __IOM uint8_t SSL7P : 1; /*!< [7..7] SSL7 Signal Polarity Setting */ + } SSLP_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x00000002) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + uint8_t : 2; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPSR; /*!< (@ 0x00000003) SPI Status Register */ + + struct + { + __IOM uint8_t OVRF : 1; /*!< [0..0] Overrun Error Flag */ + __IM uint8_t IDLNF : 1; /*!< [1..1] SPI Idle Flag */ + __IOM uint8_t MODF : 1; /*!< [2..2] Mode Fault Error Flag */ + __IOM uint8_t PERF : 1; /*!< [3..3] Parity Error Flag */ + __IOM uint8_t UDRF : 1; /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.) */ + __IOM uint8_t SPTEF : 1; /*!< [5..5] SPI Transmit Buffer Empty Flag */ + __IOM uint8_t CENDF : 1; /*!< [6..6] Communication End Flag */ + __IOM uint8_t SPRF : 1; /*!< [7..7] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000004) SPI Data Register */ + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000004) SPI Data Register ( halfword access ) */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000004) SPI Data Register ( byte access ) */ + }; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000008) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] RSPI Sequence Length SpecificationThe order in which + * the SPCMD0 to SPCMD07 registers are to be referenced is + * changed in accordance with the sequence length that is + * set in these bits. The relationship among the setting of + * these bits, sequence length, and SPCMD0 to SPCMD7 registers + * referenced by the RSPI is shown above. However, the RSPI + * in slave mode always references SPCMD0. */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000009) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] RSPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] RSPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x0000000A) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] SPBR sets the bit rate in master mode. */ + } SPBR_b; + }; + + union + { + __IOM uint8_t SPDCR; /*!< (@ 0x0000000B) SPI Data Control Register */ + + struct + { + __IOM uint8_t SPFC : 2; /*!< [1..0] Number of Frames Specification */ + __IOM uint8_t SLSEL : 2; /*!< [3..2] SSL Pin Output Select */ + __IOM uint8_t SPRDTD : 1; /*!< [4..4] SPI Receive/Transmit Data Selection */ + __IOM uint8_t SPLW : 1; /*!< [5..5] SPI Word Access/Halfword Access Specification */ + __IOM uint8_t SPBYT : 1; /*!< [6..6] SPI Byte Access Specification */ + uint8_t : 1; + } SPDCR_b; + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x0000000C) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Setting */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x0000000E) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Setting */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPPE : 1; /*!< [0..0] Parity Enable */ + __IOM uint8_t SPOE : 1; /*!< [1..1] Parity Mode */ + __IOM uint8_t SPIIE : 1; /*!< [2..2] SPI Idle Interrupt Enable */ + __IOM uint8_t PTE : 1; /*!< [3..3] Parity Self-Testing */ + __IOM uint8_t SCKASE : 1; /*!< [4..4] RSPCK Auto-Stop Function Enable */ + __IOM uint8_t SPTDDL : 3; /*!< [7..5] RSPI Transmit Data Delay */ + } SPCR2_b; + }; + + union + { + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Pins (R_SYSTEM) + */ + +typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint16_t SBYCR; /*!< (@ 0x0000000C) Standby Control Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t OPE : 1; /*!< [14..14] Output Port Enable */ + __IOM uint16_t SSBY : 1; /*!< [15..15] Software Standby */ + } SBYCR_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x0000001C) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPA0 : 1; /*!< [0..0] RAM0 Module Stop */ + __IOM uint32_t MSTPA1 : 1; /*!< [1..1] RAM1 Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPA5 : 1; /*!< [5..5] High-Speed RAM Module Stop */ + __IOM uint32_t MSTPA6 : 1; /*!< [6..6] ECCRAM Module Stop */ + __IOM uint32_t MSTPA7 : 1; /*!< [7..7] Standby RAM Module Stop */ + uint32_t : 14; + __IOM uint32_t MSTPA22 : 1; /*!< [22..22] DMA Controller/Data Transfer Controller Module Stop */ + uint32_t : 9; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t SCKDIVCR; /*!< (@ 0x00000020) System Clock Division Control Register */ + + struct + { + __IOM uint32_t PCKD : 3; /*!< [2..0] Peripheral Module Clock D (PCLKD) Select */ + uint32_t : 1; + __IOM uint32_t PCKC : 3; /*!< [6..4] Peripheral Module Clock C (PCLKC) Select */ + uint32_t : 1; + __IOM uint32_t PCKB : 3; /*!< [10..8] Peripheral Module Clock B (PCLKB) Select */ + uint32_t : 1; + __IOM uint32_t PCKA : 3; /*!< [14..12] Peripheral Module Clock A (PCLKA) Select */ + uint32_t : 1; + __IOM uint32_t BCK : 3; /*!< [18..16] External Bus Clock (BCLK) Select */ + uint32_t : 5; + __IOM uint32_t ICK : 3; /*!< [26..24] System Clock (ICLK) Select */ + uint32_t : 1; + __IOM uint32_t FCK : 3; /*!< [30..28] Flash IF Clock (FCLK) Select */ + uint32_t : 1; + } SCKDIVCR_b; + }; + + union + { + __IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t UCK : 3; /*!< [6..4] USB Clock (UCLK) Select */ + uint8_t : 1; + } SCKDIVCR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t SCKSCR; /*!< (@ 0x00000026) System Clock Source Control Register */ + + struct + { + __IOM uint8_t CKSEL : 3; /*!< [2..0] Clock Source Select */ + uint8_t : 5; + } SCKSCR_b; + }; + __IM uint8_t RESERVED4; + + union + { + __IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register */ + + struct + { + __IOM uint16_t PLIDIV : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLLMUL : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency + * Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 - + * 0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0 + * : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5 + * 111011: x30.0 */ + uint16_t : 2; + } PLLCCR_b; + }; + + union + { + __IOM uint8_t PLLCR; /*!< (@ 0x0000002A) PLL Control Register */ + + struct + { + __IOM uint8_t PLLSTP : 1; /*!< [0..0] PLL Stop Control */ + uint8_t : 7; + } PLLCR_b; + }; + + union + { + __IOM uint8_t PLLCCR2; /*!< (@ 0x0000002B) PLL Clock Control Register2 */ + + struct + { + __IOM uint8_t PLLMUL : 5; /*!< [4..0] PLL Frequency Multiplication Factor Select */ + uint8_t : 1; + __IOM uint8_t PLODIV : 2; /*!< [7..6] PLL Output Frequency Division Ratio Select */ + } PLLCCR2_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint8_t BCKCR; /*!< (@ 0x00000030) External Bus Clock Control Register */ + + struct + { + __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select */ + uint8_t : 7; + } BCKCR_b; + }; + + union + { + __IOM uint8_t MEMWAIT; /*!< (@ 0x00000031) Memory Wait Cycle Control Register */ + + struct + { + __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT + * is prohibited when SCKDIVCR.ICK selects division by 1 and + * SCKSCR.CKSEL[2:0] bits select thesystem clock source that + * is faster than 32 MHz (ICLK > 32 MHz). */ + uint8_t : 7; + } MEMWAIT_b; + }; + + union + { + __IOM uint8_t MOSCCR; /*!< (@ 0x00000032) Main Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t MOSTP : 1; /*!< [0..0] Main Clock Oscillator Stop */ + uint8_t : 7; + } MOSCCR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; + + union + { + __IOM uint8_t HOCOCR; /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t HCSTP : 1; /*!< [0..0] HOCO Stop */ + uint8_t : 7; + } HOCOCR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t MOCOCR; /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t MCSTP : 1; /*!< [0..0] MOCO Stop */ + uint8_t : 7; + } MOCOCR_b; + }; + + union + { + __IOM uint8_t FLLCR1; /*!< (@ 0x00000039) FLL Control Register 1 */ + + struct + { + __IOM uint8_t FLLEN : 1; /*!< [0..0] FLL Enable */ + uint8_t : 7; + } FLLCR1_b; + }; + + union + { + __IOM uint16_t FLLCR2; /*!< (@ 0x0000003A) FLL Control Register 2 */ + + struct + { + __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the + * FLL reference clock select */ + uint16_t : 5; + } FLLCR2_b; + }; + + union + { + __IM uint8_t OSCSF; /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register */ + + struct + { + __IM uint8_t HOCOSF : 1; /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF + * bit value after a reset is 1 when the OFS1.HOCOEN bit is + * 0. It is 0 when the OFS1.HOCOEN bit is 1. */ + uint8_t : 2; + __IM uint8_t MOSCSF : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag */ + uint8_t : 1; + __IM uint8_t PLLSF : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag */ + __IM uint8_t PLL2SF : 1; /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag */ + uint8_t : 1; + } OSCSF_b; + }; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t CKOCR; /*!< (@ 0x0000003E) Clock Out Control Register */ + + struct + { + __IOM uint8_t CKOSEL : 3; /*!< [2..0] Clock out source select */ + uint8_t : 1; + __IOM uint8_t CKODIV : 3; /*!< [6..4] Clock out input frequency Division Select */ + __IOM uint8_t CKOEN : 1; /*!< [7..7] Clock out enable */ + } CKOCR_b; + }; + + union + { + __IOM uint8_t TRCKCR; /*!< (@ 0x0000003F) Trace Clock Control Register */ + + struct + { + __IOM uint8_t TRCK : 4; /*!< [3..0] Trace Clock operating frequency select */ + uint8_t : 3; + __IOM uint8_t TRCKEN : 1; /*!< [7..7] Trace Clock operating Enable */ + } TRCKCR_b; + }; + + union + { + __IOM uint8_t OSTDCR; /*!< (@ 0x00000040) Oscillation Stop Detection Control Register */ + + struct + { + __IOM uint8_t OSTDIE : 1; /*!< [0..0] Oscillation Stop Detection Interrupt Enable */ + uint8_t : 6; + __IOM uint8_t OSTDE : 1; /*!< [7..7] Oscillation Stop Detection Function Enable */ + } OSTDCR_b; + }; + + union + { + __IOM uint8_t OSTDSR; /*!< (@ 0x00000041) Oscillation Stop Detection Status Register */ + + struct + { + __IOM uint8_t OSTDF : 1; /*!< [0..0] Oscillation Stop Detection Flag */ + uint8_t : 7; + } OSTDSR_b; + }; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11; + + union + { + __IOM uint16_t PLL2CCR; /*!< (@ 0x00000048) PLL2 Clock Control Register */ + + struct + { + __IOM uint16_t PL2IDIV : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select */ + uint16_t : 2; + __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select */ + uint16_t : 3; + __IOM uint16_t PLL2MUL : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select */ + uint16_t : 2; + } PLL2CCR_b; + }; + + union + { + __IOM uint8_t PLL2CR; /*!< (@ 0x0000004A) PLL2 Control Register */ + + struct + { + __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control */ + uint8_t : 7; + } PLL2CR_b; + }; + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t LPOPT; /*!< (@ 0x0000004C) Lower Power Operation Control Register */ + + struct + { + __IOM uint8_t MPUDIS : 1; /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock + * (valid only when LPOPTEN = 1) */ + __IOM uint8_t DCLKDIS : 2; /*!< [2..1] Debug Clock Disable Control */ + __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W + * clock (valid only when LPOPT.LPOPTEN = 1) */ + uint8_t : 3; + __IOM uint8_t LPOPTEN : 1; /*!< [7..7] Lower Power Operation Enable */ + } LPOPT_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t SLCDSCKCR; /*!< (@ 0x00000050) Segment LCD Source Clock Control Register */ + + struct + { + __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select */ + uint8_t : 4; + __IOM uint8_t LCDSCKEN : 1; /*!< [7..7] LCD Source Clock Out Enable */ + } SLCDSCKCR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t EBCKOCR; /*!< (@ 0x00000052) External Bus Clock Output Control Register */ + + struct + { + __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control */ + uint8_t : 7; + } EBCKOCR_b; + }; + + union + { + __IOM uint8_t SDCKOCR; /*!< (@ 0x00000053) SDRAM Clock Output Control Register */ + + struct + { + __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control */ + uint8_t : 7; + } SDCKOCR_b; + }; + __IM uint32_t RESERVED16[3]; + __IM uint8_t RESERVED17; + + union + { + __IOM uint8_t MOCOUTCR; /*!< (@ 0x00000061) MOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original MOCO + * trimming bits */ + } MOCOUTCR_b; + }; + + union + { + __IOM uint8_t HOCOUTCR; /*!< (@ 0x00000062) HOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original HOCO + * trimming bits */ + } HOCOUTCR_b; + }; + __IM uint8_t RESERVED18; + __IM uint32_t RESERVED19[2]; + + union + { + __IOM uint8_t USBCKDIVCR; /*!< (@ 0x0000006C) USB Clock Division Control Register */ + + struct + { + __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select */ + uint8_t : 5; + } USBCKDIVCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKDIVCR; /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select */ + uint8_t : 5; + } OCTACKDIVCR_b; + }; + + union + { + __IOM uint8_t SCISPICKDIVCR; /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register */ + + struct + { + __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select */ + uint8_t : 5; + } SCISPICKDIVCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKDIVCR; /*!< (@ 0x0000006E) CANFD Clock Division Control Register */ + + struct + { + __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select */ + uint8_t : 5; + } CANFDCKDIVCR_b; + }; + + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union + { + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21; + + union + { + __IOM uint8_t USBCKCR; /*!< (@ 0x00000074) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCKSEL : 3; /*!< [2..0] USB Clock (USBCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request */ + __IM uint8_t USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag */ + } USBCKCR_b; + }; + + union + { + union + { + __IOM uint8_t OCTACKCR; /*!< (@ 0x00000075) Octal-SPI Clock Control Register */ + + struct + { + __IOM uint8_t OCTACKSEL : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select */ + uint8_t : 3; + __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request */ + __IM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag */ + } OCTACKCR_b; + }; + + union + { + __IOM uint8_t SCISPICKCR; /*!< (@ 0x00000075) SCI SPI Clock Control Register */ + + struct + { + __IOM uint8_t SCISPICKSEL : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select */ + uint8_t : 3; + __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request */ + __IM uint8_t SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag */ + } SCISPICKCR_b; + }; + }; + + union + { + __IOM uint8_t CANFDCKCR; /*!< (@ 0x00000076) CANFD Clock Control Register */ + + struct + { + __IOM uint8_t CANFDCKSEL : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request */ + __IM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag */ + } CANFDCKCR_b; + }; + + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24[3]; + + union + { + __IOM uint32_t SNZREQCR1; /*!< (@ 0x00000088) Snooze Request Control Register 1 */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request */ + uint32_t : 29; + } SNZREQCR1_b; + }; + __IM uint32_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t SNZCR; /*!< (@ 0x00000092) Snooze Control Register */ + + struct + { + __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other + * than in asynchronous mode. */ + __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode */ + uint8_t : 5; + __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ + } SNZCR_b; + }; + __IM uint8_t RESERVED27; + + union + { + __IOM uint8_t SNZEDCR; /*!< (@ 0x00000094) Snooze End Control Register */ + + struct + { + __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable */ + __IOM uint8_t DTCZRED : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t DTCNZRED : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable */ + __IOM uint8_t AD0MATED : 1; /*!< [3..3] AD compare match 0 Snooze End Enable */ + __IOM uint8_t AD0UMTED : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable */ + __IOM uint8_t AD1MATED : 1; /*!< [5..5] AD compare match 1 Snooze End Enable */ + __IOM uint8_t AD1UMTED : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable */ + __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set + * to 1 other than in asynchronous mode. */ + } SNZEDCR_b; + }; + + union + { + __IOM uint8_t SNZEDCR1; /*!< (@ 0x00000095) Snooze End Control Register 1 */ + + struct + { + __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable */ + uint8_t : 7; + } SNZEDCR1_b; + }; + __IM uint16_t RESERVED28; + + union + { + __IOM uint32_t SNZREQCR; /*!< (@ 0x00000098) Snooze Request Control Register */ + + struct + { + __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request */ + __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request */ + __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request */ + __IOM uint32_t SNZREQEN3 : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request */ + __IOM uint32_t SNZREQEN4 : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request */ + __IOM uint32_t SNZREQEN5 : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request */ + __IOM uint32_t SNZREQEN6 : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request */ + __IOM uint32_t SNZREQEN7 : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request */ + __IOM uint32_t SNZREQEN8 : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request */ + __IOM uint32_t SNZREQEN9 : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request */ + __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request */ + __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request */ + __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request */ + __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request */ + __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request */ + __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request */ + uint32_t : 1; + __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request */ + uint32_t : 4; + __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze + * request */ + __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze + * request */ + __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request */ + __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request */ + uint32_t : 2; + __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze + * request */ + __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A + * snooze request */ + __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B + * snooze request */ + uint32_t : 1; + } SNZREQCR_b; + }; + __IM uint16_t RESERVED29; + + union + { + __IOM uint8_t FLSTOP; /*!< (@ 0x0000009E) Flash Operation Control Register */ + + struct + { + __IOM uint8_t FLSTOP : 1; /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation */ + uint8_t : 3; + __IOM uint8_t FLSTPF : 1; /*!< [4..4] Flash Memory Operation Status Flag */ + uint8_t : 3; + } FLSTOP_b; + }; + + union + { + __IOM uint8_t PSMCR; /*!< (@ 0x0000009F) Power Save Memory Control Register */ + + struct + { + __IOM uint8_t PSMC : 2; /*!< [1..0] Power save memory control. */ + uint8_t : 6; + } PSMCR_b; + }; + + union + { + __IOM uint8_t OPCCR; /*!< (@ 0x000000A0) Operating Power Control Register */ + + struct + { + __IOM uint8_t OPCM : 2; /*!< [1..0] Operating Power Control Mode Select */ + uint8_t : 2; + __IM uint8_t OPCMTSF : 1; /*!< [4..4] Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } OPCCR_b; + }; + __IM uint8_t RESERVED30; + + union + { + __IOM uint8_t MOSCWTCR; /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register */ + + struct + { + __IOM uint8_t MSTS : 4; /*!< [3..0] Main clock oscillator wait time setting */ + uint8_t : 4; + } MOSCWTCR_b; + }; + __IM uint8_t RESERVED31[2]; + + union + { + __IOM uint8_t HOCOWTCR; /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register */ + + struct + { + __IOM uint8_t HSTS : 3; /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of + * the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed) */ + uint8_t : 5; + } HOCOWTCR_b; + }; + __IM uint16_t RESERVED32[2]; + + union + { + __IOM uint8_t SOPCCR; /*!< (@ 0x000000AA) Sub Operating Power Control Register */ + + struct + { + __IOM uint8_t SOPCM : 1; /*!< [0..0] Sub Operating Power Control Mode Select */ + uint8_t : 3; + __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag */ + uint8_t : 3; + } SOPCCR_b; + }; + __IM uint8_t RESERVED33; + __IM uint32_t RESERVED34[5]; + + union + { + __IOM uint16_t RSTSR1; /*!< (@ 0x000000C0) Reset Status Register 1 */ + + struct + { + __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable + * only to clear the flag. Confirm the value is 1 and then + * write 0. */ + __IOM uint16_t WDTRF : 1; /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t SWRF : 1; /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + uint16_t : 5; + __IOM uint16_t RPERF : 1; /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t REERF : 1; /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint16_t SPERF : 1; /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint16_t TZERF : 1; /*!< [13..13] Trust Zone Error Reset Detect Flag */ + uint16_t : 1; + __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ + } RSTSR1_b; + }; + __IM uint16_t RESERVED35; + __IM uint32_t RESERVED36[3]; + + union + { + __IOM uint8_t USBCKCR_ALT; /*!< (@ 0x000000D0) USB Clock Control Register */ + + struct + { + __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock + * (UCLK). */ + uint8_t : 7; + } USBCKCR_ALT_b; + }; + + union + { + __IOM uint8_t SDADCCKCR; /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control + * Register */ + + struct + { + __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select */ + uint8_t : 6; + __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ + } SDADCCKCR_b; + }; + __IM uint16_t RESERVED37; + __IM uint32_t RESERVED38[3]; + + union + { + __IOM uint8_t LVD1CR1; /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD1CR1_b; + }; + + union + { + __IOM uint8_t LVD1SR; /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD1SR_b; + }; + + union + { + __IOM uint8_t LVD2CR1; /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1 */ + + struct + { + __IOM uint8_t IDTSEL : 2; /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select */ + __IOM uint8_t IRQSEL : 1; /*!< [2..2] Voltage Monitor Interrupt Type Select */ + uint8_t : 5; + } LVD2CR1_b; + }; + + union + { + __IOM uint8_t LVD2SR; /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register */ + + struct + { + __IOM uint8_t DET : 1; /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only + * 0 can be written to this bit. After writing 0 to this bit, + * it takes 2 system clock cycles for the bit to be read as + * 0. */ + __IM uint8_t MON : 1; /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag */ + uint8_t : 6; + } LVD2SR_b; + }; + __IM uint32_t RESERVED39[183]; + + union + { + __IOM uint32_t CGFSAR; /*!< (@ 0x000003C0) Clock Generation Function Security Attribute + * Register */ + + struct + { + __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00 */ + uint32_t : 1; + __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02 */ + __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03 */ + __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04 */ + __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05 */ + __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06 */ + __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07 */ + __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08 */ + __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09 */ + uint32_t : 1; + __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11 */ + __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12 */ + uint32_t : 3; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + uint32_t : 14; + } CGFSAR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t LPMSAR; /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + uint32_t : 1; + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 1; + __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4 */ + uint32_t : 3; + __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8 */ + __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9 */ + uint32_t : 22; + } LPMSAR_b; + }; + + union + { + union + { + __IOM uint32_t LVDSAR; /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + uint32_t : 30; + } LVDSAR_b; + }; + + union + { + __IOM uint32_t RSTSAR; /*!< (@ 0x000003CC) Reset Security Attribution Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 29; + } RSTSAR_b; + }; + }; + + union + { + __IOM uint32_t BBFSAR; /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register */ + + struct + { + __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0 */ + __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1 */ + __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2 */ + uint32_t : 13; + __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16 */ + __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17 */ + __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18 */ + __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19 */ + __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20 */ + __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21 */ + __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22 */ + __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23 */ + uint32_t : 8; + } BBFSAR_b; + }; + __IM uint32_t RESERVED41[3]; + + union + { + __IOM uint32_t DPFSAR; /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution + * Register */ + + struct + { + __IOM uint32_t DPFSA0 : 1; /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit + * 0 */ + __IOM uint32_t DPFSA1 : 1; /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit + * 1 */ + __IOM uint32_t DPFSA2 : 1; /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit + * 2 */ + __IOM uint32_t DPFSA3 : 1; /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit + * 3 */ + __IOM uint32_t DPFSA4 : 1; /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit + * 4 */ + __IOM uint32_t DPFSA5 : 1; /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit + * 5 */ + __IOM uint32_t DPFSA6 : 1; /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit + * 6 */ + __IOM uint32_t DPFSA7 : 1; /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit + * 7 */ + __IOM uint32_t DPFSA8 : 1; /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit + * 8 */ + __IOM uint32_t DPFSA9 : 1; /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit + * 9 */ + __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit + * 10 */ + __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit + * 11 */ + __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit + * 12 */ + __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit + * 13 */ + __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit + * 14 */ + __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit + * 15 */ + __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit + * 16 */ + __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit + * 17 */ + __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit + * 18 */ + __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit + * 19 */ + __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit + * 20 */ + uint32_t : 3; + __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit + * 24 */ + uint32_t : 1; + __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit + * 26 */ + __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit + * 27 */ + uint32_t : 4; + } DPFSAR_b; + }; + __IM uint32_t RESERVED42[6]; + __IM uint16_t RESERVED43; + + union + { + __IOM uint16_t PRCR; /*!< (@ 0x000003FE) Protect Register */ + + struct + { + __IOM uint16_t PRC0 : 1; /*!< [0..0] Enables writing to the registers related to the clock + * generation circuit. */ + __IOM uint16_t PRC1 : 1; /*!< [1..1] Enables writing to the registers related to the operating + * modes, the low power consumption modes and the battery + * backup function. */ + uint16_t : 1; + __IOM uint16_t PRC3 : 1; /*!< [3..3] Enables writing to the registers related to the LVD. */ + __IOM uint16_t PRC4 : 1; /*!< [4..4] PRC4 */ + uint16_t : 3; + __OM uint16_t PRKEY : 8; /*!< [15..8] PRKEY Key Code */ + } PRCR_b; + }; + + union + { + __IOM uint8_t DPSBYCR; /*!< (@ 0x00000400) Deep Standby Control Register */ + + struct + { + __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control */ + uint8_t : 4; + __IOM uint8_t IOKEEP : 1; /*!< [6..6] I/O Port Retention */ + __IOM uint8_t DPSBY : 1; /*!< [7..7] Deep Software Standby */ + } DPSBYCR_b; + }; + + union + { + __IOM uint8_t DPSWCR; /*!< (@ 0x00000401) Deep Standby Wait Control Register */ + + struct + { + __IOM uint8_t WTSTS : 6; /*!< [5..0] Deep Software Wait Standby Time Setting Bit */ + uint8_t : 2; + } DPSWCR_b; + }; + + union + { + __IOM uint8_t DPSIER0; /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0 */ + + struct + { + __IOM uint8_t DIRQ0E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ1E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ2E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ3E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ4E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ5E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ6E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ7E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER0_b; + }; + + union + { + __IOM uint8_t DPSIER1; /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1 */ + + struct + { + __IOM uint8_t DIRQ8E : 1; /*!< [0..0] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ9E : 1; /*!< [1..1] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable */ + __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable */ + } DPSIER1_b; + }; + + union + { + __IOM uint8_t DPSIER2; /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t DLVD1IE : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DLVD2IE : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable */ + __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DRTCAIE : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable */ + __IOM uint8_t DNMIE : 1; /*!< [4..4] NMI Pin Enable */ + uint8_t : 3; + } DPSIER2_b; + }; + + union + { + __IOM uint8_t DPSIER3; /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT1IE : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable */ + __IOM uint8_t DAGT3IE : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable */ + uint8_t : 4; + } DPSIER3_b; + }; + + union + { + __IOM uint8_t DPSIFR0; /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0 */ + + struct + { + __IOM uint8_t DIRQ0F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ1F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ2F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ3F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ4F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ5F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ6F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ7F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR0_b; + }; + + union + { + __IOM uint8_t DPSIFR1; /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1 */ + + struct + { + __IOM uint8_t DIRQ8F : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ9F : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag */ + __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag */ + } DPSIFR1_b; + }; + + union + { + __IOM uint8_t DPSIFR2; /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2 */ + + struct + { + __IOM uint8_t DLVD1IF : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag */ + __IOM uint8_t DLVD2IF : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag */ + __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DRTCAIF : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag */ + __IOM uint8_t DNMIF : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag */ + uint8_t : 3; + } DPSIFR2_b; + }; + + union + { + __IOM uint8_t DPSIFR3; /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3 */ + + struct + { + __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag */ + __IOM uint8_t DAGT1IF : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag */ + __IOM uint8_t DAGT3IF : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag */ + uint8_t : 4; + } DPSIFR3_b; + }; + + union + { + __IOM uint8_t DPSIEGR0; /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR0_b; + }; + + union + { + __IOM uint8_t DPSIEGR1; /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1 */ + + struct + { + __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select */ + __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select */ + } DPSIEGR1_b; + }; + + union + { + __IOM uint8_t DPSIEGR2; /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2 */ + + struct + { + __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select */ + __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select */ + uint8_t : 2; + __IOM uint8_t DNMIEG : 1; /*!< [4..4] NMI Pin Edge Select */ + uint8_t : 3; + } DPSIEGR2_b; + }; + __IM uint8_t RESERVED44; + + union + { + __IOM uint8_t SYOCDCR; /*!< (@ 0x0000040E) System Control OCD Control Register */ + + struct + { + __IOM uint8_t DOCDF : 1; /*!< [0..0] Deep Standby OCD flag */ + uint8_t : 6; + __IOM uint8_t DBGEN : 1; /*!< [7..7] Debugger Enable bit */ + } SYOCDCR_b; + }; + + union + { + __IOM uint8_t STCONR; /*!< (@ 0x0000040F) Standby Condition Register */ + + struct + { + __IOM uint8_t STCON : 2; /*!< [1..0] SSTBY condition bit */ + uint8_t : 6; + } STCONR_b; + }; + + union + { + __IOM uint8_t RSTSR0; /*!< (@ 0x00000410) Reset Status Register 0 */ + + struct + { + __IOM uint8_t PORF : 1; /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear + * the flag. Confirm the value is 1 and then write 0. */ + __IOM uint8_t LVD0RF : 1; /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD1RF : 1; /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + __IOM uint8_t LVD2RF : 1; /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only + * to clear the flag. Confirm the value is 1 and then write + * 0. */ + uint8_t : 3; + __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to + * clear the flag. Confirm the value is 1 and then write 0. */ + } RSTSR0_b; + }; + + union + { + __IOM uint8_t RSTSR2; /*!< (@ 0x00000411) Reset Status Register 2 */ + + struct + { + __IOM uint8_t CWSF : 1; /*!< [0..0] Cold/Warm Start Determination Flag */ + uint8_t : 7; + } RSTSR2_b; + }; + __IM uint8_t RESERVED45; + + union + { + __IOM uint8_t MOMCR; /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control + * Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t MODRV1 : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching */ + __IOM uint8_t MODRV0 : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching */ + __IOM uint8_t MOSEL : 1; /*!< [6..6] Main Clock Oscillator Switching */ + __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching + * Enable */ + } MOMCR_b; + }; + __IM uint16_t RESERVED46; + + union + { + __IOM uint8_t FWEPROR; /*!< (@ 0x00000416) Flash P/E Protect Register */ + + struct + { + __IOM uint8_t FLWE : 2; /*!< [1..0] Flash Programming and Erasure */ + uint8_t : 6; + } FWEPROR_b; + }; + + union + { + union + { + __IOM uint8_t LVCMPCR; /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register */ + + struct + { + uint8_t : 5; + __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable */ + __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable */ + uint8_t : 1; + } LVCMPCR_b; + }; + + union + { + __IOM uint8_t LVD1CMPCR; /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 2; + __IOM uint8_t LVD1E : 1; /*!< [7..7] Voltage Detection 1 Enable */ + } LVD1CMPCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t LVDLVLR; /*!< (@ 0x00000418) Voltage Detection Level Select Register */ + + struct + { + __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during + * fall in voltage) */ + __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during + * fall in voltage) */ + } LVDLVLR_b; + }; + + union + { + __IOM uint8_t LVD2CMPCR; /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register */ + + struct + { + __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during + * drop in voltage) */ + uint8_t : 4; + __IOM uint8_t LVD2E : 1; /*!< [7..7] Voltage Detection 2 Enable */ + } LVD2CMPCR_b; + }; + }; + __IM uint8_t RESERVED47; + + union + { + __IOM uint8_t LVD1CR0; /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD1CR0_b; + }; + + union + { + __IOM uint8_t LVD2CR0; /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0 */ + + struct + { + __IOM uint8_t RIE : 1; /*!< [0..0] Voltage Monitor Interrupt/Reset Enable */ + __IOM uint8_t DFDIS : 1; /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select */ + __IOM uint8_t CMPE : 1; /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable */ + uint8_t : 1; + __IOM uint8_t FSAMP : 2; /*!< [5..4] Sampling Clock Select */ + __IOM uint8_t RI : 1; /*!< [6..6] Voltage Monitor Circuit Mode Select */ + __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ + } LVD2CR0_b; + }; + __IM uint8_t RESERVED48; + + union + { + __IOM uint8_t VBATTMNSELR; /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select + * Register */ + + struct + { + __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit */ + uint8_t : 7; + } VBATTMNSELR_b; + }; + + union + { + __IM uint8_t VBATTMONR; /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register */ + + struct + { + __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit */ + uint8_t : 7; + } VBATTMONR_b; + }; + + union + { + __IOM uint8_t VBTCR1; /*!< (@ 0x0000041F) VBATT Control Register1 */ + + struct + { + __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop */ + uint8_t : 7; + } VBTCR1_b; + }; + __IM uint32_t RESERVED49[8]; + + union + { + union + { + __IOM uint8_t DCDCCTL; /*!< (@ 0x00000440) DCDC/LDO Control Register */ + + struct + { + __IOM uint8_t DCDCON : 1; /*!< [0..0] LDO/DCDC on/off Control bit */ + __IOM uint8_t OCPEN : 1; /*!< [1..1] DCDC OCP Function Enable bit */ + uint8_t : 2; + __IOM uint8_t STOPZA : 1; /*!< [4..4] DCDC IO Buffer Power Control bit */ + __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit */ + __IOM uint8_t FST : 1; /*!< [6..6] DCDC Fast Startup */ + __IOM uint8_t PD : 1; /*!< [7..7] DCDC VREF Generate Disable bit */ + } DCDCCTL_b; + }; + + union + { + __IOM uint8_t LDOSCR; /*!< (@ 0x00000440) LDO Stop Control Register */ + + struct + { + __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop */ + __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop */ + uint8_t : 6; + } LDOSCR_b; + }; + }; + + union + { + __IOM uint8_t VCCSEL; /*!< (@ 0x00000441) Voltage Level Selection Control Register */ + + struct + { + __IOM uint8_t VCCSEL : 2; /*!< [1..0] DCDC Working Voltage Level Selection */ + uint8_t : 6; + } VCCSEL_b; + }; + __IM uint16_t RESERVED50; + + union + { + __IOM uint8_t PL2LDOSCR; /*!< (@ 0x00000444) PLL2-LDO Stop Control Register */ + + struct + { + __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop */ + uint8_t : 7; + } PL2LDOSCR_b; + }; + __IM uint8_t RESERVED51; + __IM uint16_t RESERVED52; + __IM uint32_t RESERVED53[14]; + + union + { + __IOM uint8_t SOSCCR; /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register */ + + struct + { + __IOM uint8_t SOSTP : 1; /*!< [0..0] Sub-Clock Oscillator Stop */ + uint8_t : 7; + } SOSCCR_b; + }; + + union + { + __IOM uint8_t SOMCR; /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register */ + + struct + { + __IOM uint8_t SODRV : 2; /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching */ + uint8_t : 6; + } SOMCR_b; + }; + __IM uint16_t RESERVED54; + __IM uint32_t RESERVED55[3]; + + union + { + __IOM uint8_t LOCOCR; /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint8_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint8_t : 7; + } LOCOCR_b; + }; + __IM uint8_t RESERVED56; + + union + { + __IOM uint8_t LOCOUTCR; /*!< (@ 0x00000492) LOCO User Trimming Control Register */ + + struct + { + __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 + * 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center + * Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : + +126 0111_1111 : +127These bits are added to original LOCO + * trimming bits */ + } LOCOUTCR_b; + }; + __IM uint8_t RESERVED57; + __IM uint32_t RESERVED58[7]; + + union + { + __IOM uint8_t VBTCR2; /*!< (@ 0x000004B0) VBATT Control Register2 */ + + struct + { + uint8_t : 4; + __IOM uint8_t VBTLVDEN : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit */ + uint8_t : 1; + __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit */ + } VBTCR2_b; + }; + + union + { + __IOM uint8_t VBTSR; /*!< (@ 0x000004B1) VBATT Status Register */ + + struct + { + __IOM uint8_t VBTRDF : 1; /*!< [0..0] VBAT_R Reset Detect Flag */ + __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag */ + uint8_t : 2; + __IM uint8_t VBTRVLD : 1; /*!< [4..4] VBATT_R Valid */ + uint8_t : 3; + } VBTSR_b; + }; + + union + { + __IOM uint8_t VBTCMPCR; /*!< (@ 0x000004B2) VBATT Comparator Control Register */ + + struct + { + __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable */ + uint8_t : 7; + } VBTCMPCR_b; + }; + __IM uint8_t RESERVED59; + + union + { + __IOM uint8_t VBTLVDICR; /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control + * Register */ + + struct + { + __IOM uint8_t VBTLVDIE : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit */ + __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit */ + uint8_t : 6; + } VBTLVDICR_b; + }; + __IM uint8_t RESERVED60; + + union + { + __IOM uint8_t VBTWCTLR; /*!< (@ 0x000004B6) VBATT Wakeup function Control Register */ + + struct + { + __IOM uint8_t VWEN : 1; /*!< [0..0] VBATT wakeup enable */ + uint8_t : 7; + } VBTWCTLR_b; + }; + __IM uint8_t RESERVED61; + + union + { + __IOM uint8_t VBTWCH0OTSR; /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register */ + + struct + { + uint8_t : 1; + __IOM uint8_t CH0VCH1TE : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable */ + __IOM uint8_t CH0VCH2TE : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH0VRTCTE : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH0OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH1OTSR; /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH1VCH0TE : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH1VCH2TE : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable */ + __IOM uint8_t CH1VRTCTE : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH1OTSR_b; + }; + + union + { + __IOM uint8_t VBTWCH2OTSR; /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register */ + + struct + { + __IOM uint8_t CH2VCH0TE : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable */ + __IOM uint8_t CH2VCH1TE : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable */ + uint8_t : 1; + __IOM uint8_t CH2VRTCTE : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable */ + __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable */ + __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable */ + uint8_t : 2; + } VBTWCH2OTSR_b; + }; + + union + { + __IOM uint8_t VBTICTLR; /*!< (@ 0x000004BB) VBATT Input Control Register */ + + struct + { + __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable */ + __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable */ + __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable */ + uint8_t : 5; + } VBTICTLR_b; + }; + + union + { + __IOM uint8_t VBTOCTLR; /*!< (@ 0x000004BC) VBATT Output Control Register */ + + struct + { + __IOM uint8_t VCH0OEN : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable */ + __IOM uint8_t VCH1OEN : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable */ + __IOM uint8_t VCH2OEN : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable */ + __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection */ + __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection */ + __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection */ + uint8_t : 2; + } VBTOCTLR_b; + }; + + union + { + __IOM uint8_t VBTWTER; /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register */ + + struct + { + __IOM uint8_t VCH0E : 1; /*!< [0..0] VBATWIO0 Pin Enable */ + __IOM uint8_t VCH1E : 1; /*!< [1..1] VBATWIO1 Pin Enable */ + __IOM uint8_t VCH2E : 1; /*!< [2..2] VBATWIO2 Pin Enable */ + __IOM uint8_t VRTCIE : 1; /*!< [3..3] RTC Periodic Signal Enable */ + __IOM uint8_t VRTCAE : 1; /*!< [4..4] RTC Alarm Signal Enable */ + __IOM uint8_t VAGTUE : 1; /*!< [5..5] AGT(ch1) underflow Signal Enable */ + uint8_t : 2; + } VBTWTER_b; + }; + + union + { + __IOM uint8_t VBTWEGR; /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register */ + + struct + { + __IOM uint8_t VCH0EG : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH1EG : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select */ + __IOM uint8_t VCH2EG : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select */ + uint8_t : 5; + } VBTWEGR_b; + }; + + union + { + __IOM uint8_t VBTWFR; /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register */ + + struct + { + __IOM uint8_t VCH0F : 1; /*!< [0..0] VBATWIO0 Wakeup Trigger Flag */ + __IOM uint8_t VCH1F : 1; /*!< [1..1] VBATWIO1 Wakeup Trigger Flag */ + __IOM uint8_t VCH2F : 1; /*!< [2..2] VBATWIO2 Wakeup Trigger Flag */ + __IOM uint8_t VRTCIF : 1; /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag */ + __IOM uint8_t VRTCAF : 1; /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag */ + __IOM uint8_t VAGTUF : 1; /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag */ + uint8_t : 2; + } VBTWFR_b; + }; + + union + { + __IOM uint8_t VBTBER; /*!< (@ 0x000004C0) VBATT Backup Enable Register */ + + struct + { + uint8_t : 3; + __IOM uint8_t VBAE : 1; /*!< [3..3] VBATT backup register access enable bit */ + uint8_t : 4; + } VBTBER_b; + }; + __IM uint8_t RESERVED62; + __IM uint16_t RESERVED63; + __IM uint32_t RESERVED64[15]; + + union + { + __IOM uint8_t VBTBKR[512]; /*!< (@ 0x00000500) VBATT Backup Register [0..511] */ + + struct + { + __IOM uint8_t VBTBKR : 8; /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store + * data powered by VBATT.The value of this register is retained + * even when VCC is not powered but VBATT is powered.VBTBKR + * is initialized by VBATT selected voltage power-on-reset. */ + } VBTBKR_b[512]; + }; +} R_SYSTEM_Type; /*!< Size = 1792 (0x700) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CAL) + */ + +typedef struct /*!< (@ 0x407FB17C) R_TSN_CAL Structure */ +{ + union + { + __IM uint32_t TSCDR; /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register */ + + struct + { + __IM uint32_t TSCDR : 32; /*!< [31..0] The 32 bit TSCDR register stores temperature sensor + * calibration converted value. */ + } TSCDR_b; + }; +} R_TSN_CAL_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor (R_TSN_CTRL) + */ + +typedef struct /*!< (@ 0x400F3000) R_TSN_CTRL Structure */ +{ + union + { + __IOM uint8_t TSCR; /*!< (@ 0x00000000) Temperature Sensor Control Register */ + + struct + { + uint8_t : 4; + __IOM uint8_t TSOE : 1; /*!< [4..4] Temperature Sensor Enable */ + uint8_t : 2; + __IOM uint8_t TSEN : 1; /*!< [7..7] Temperature Sensor Output Enable */ + } TSCR_b; + }; +} R_TSN_CTRL_Type; /*!< Size = 1 (0x1) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer (R_WDT) + */ + +typedef struct /*!< (@ 0x40083400) R_WDT Structure */ +{ + union + { + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + + struct + { + __IOM uint8_t WDTRR : 8; /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter + * of the WDT. */ + } WDTRR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t WDTCSTPR; /*!< (@ 0x00000008) WDT Count Stop Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t SLCSTP : 1; /*!< [7..7] Sleep-Mode Count Stop Control */ + } WDTCSTPR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; +} R_WDT_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief TrustZone Filter (R_TZF) + */ + +typedef struct /*!< (@ 0x40000E00) R_TZF Structure */ +{ + union + { + __IOM uint16_t TZFOAD; /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register */ + + struct + { + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFOAD_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t TZFPT; /*!< (@ 0x00000004) TrustZone Filter Protect Register */ + + struct + { + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] KeyCode */ + } TZFPT_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[94]; + + union + { + __IOM uint32_t TZFSAR; /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register */ + + struct + { + __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter */ + uint32_t : 31; + } TZFSAR_b; + }; +} R_TZF_Type; /*!< Size = 388 (0x184) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/** + * @brief R_CACHE (R_CACHE) + */ + +typedef struct /*!< (@ 0x40007000) R_CACHE Structure */ +{ + union + { + __IOM uint32_t CCACTL; /*!< (@ 0x00000000) C-Cache Control Register */ + + struct + { + __IOM uint32_t ENC : 1; /*!< [0..0] C-Cache Enable */ + uint32_t : 31; + } CCACTL_b; + }; + + union + { + __IOM uint32_t CCAFCT; /*!< (@ 0x00000004) C-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FC : 1; /*!< [0..0] C-Cache Flush */ + uint32_t : 31; + } CCAFCT_b; + }; + + union + { + __IOM uint32_t CCALCF; /*!< (@ 0x00000008) C-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CC : 2; /*!< [1..0] C-Cache Line Size */ + uint32_t : 30; + } CCALCF_b; + }; + __IM uint32_t RESERVED[13]; + + union + { + __IOM uint32_t SCACTL; /*!< (@ 0x00000040) S-Cache Control Register */ + + struct + { + __IOM uint32_t ENS : 1; /*!< [0..0] S-Cache Enable */ + uint32_t : 31; + } SCACTL_b; + }; + + union + { + __IOM uint32_t SCAFCT; /*!< (@ 0x00000044) S-Cache Flush Control Register */ + + struct + { + __IOM uint32_t FS : 1; /*!< [0..0] S-Cache Flush */ + uint32_t : 31; + } SCAFCT_b; + }; + + union + { + __IOM uint32_t SCALCF; /*!< (@ 0x00000048) S-Cache Line Configuration Register */ + + struct + { + __IOM uint32_t CS : 2; /*!< [1..0] S-Cache Line Size */ + uint32_t : 30; + } SCALCF_b; + }; + __IM uint32_t RESERVED1[109]; + + union + { + __IOM uint32_t CAPOAD; /*!< (@ 0x00000200) Cache Parity Error Operation After Detection + * Register */ + + struct + { + __IOM uint32_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint32_t : 31; + } CAPOAD_b; + }; + + union + { + __IOM uint32_t CAPRCR; /*!< (@ 0x00000204) Cache Protection Register */ + + struct + { + __IOM uint32_t PRCR : 1; /*!< [0..0] Register Write Control */ + __IOM uint32_t KW : 7; /*!< [7..1] Write key code */ + uint32_t : 24; + } CAPRCR_b; + }; +} R_CACHE_Type; /*!< Size = 520 (0x208) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CPU System Security Control Unit (R_CPSCU) + */ + +typedef struct /*!< (@ 0x40008000) R_CPSCU Structure */ +{ + union + { + __IOM uint32_t CSAR; /*!< (@ 0x00000000) Cache Security Attribution Register */ + + struct + { + __IOM uint32_t CACHESA : 1; /*!< [0..0] Security Attributes of Registers for Cache Control */ + __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration */ + __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error */ + uint32_t : 29; + } CSAR_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SRAMSAR; /*!< (@ 0x00000010) SRAM Security Attribution Register */ + + struct + { + __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection */ + __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection + * 2 */ + __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation */ + uint32_t : 29; + } SRAMSAR_b; + }; + + union + { + __IOM uint32_t STBRAMSAR; /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register */ + + struct + { + __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM */ + uint32_t : 28; + } STBRAMSAR_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IOM uint32_t DTCSAR; /*!< (@ 0x00000030) DTC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution */ + uint32_t : 31; + } DTCSAR_b; + }; + + union + { + __IOM uint32_t DMACSAR; /*!< (@ 0x00000034) DMAC Controller Security Attribution Register */ + + struct + { + __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution */ + uint32_t : 31; + } DMACSAR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t ICUSARA; /*!< (@ 0x00000040) ICU Security Attribution Register A */ + + struct + { + __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers */ + uint32_t : 16; + } ICUSARA_b; + }; + + union + { + __IOM uint32_t ICUSARB; /*!< (@ 0x00000044) ICU Security Attribution Register B */ + + struct + { + __IOM uint32_t SANMI : 1; /*!< [0..0] Security Attributes of nonmaskable interrupt */ + uint32_t : 31; + } ICUSARB_b; + }; + + union + { + __IOM uint32_t ICUSARC; /*!< (@ 0x00000048) ICU Security Attribution Register C */ + + struct + { + __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel */ + uint32_t : 24; + } ICUSARC_b; + }; + + union + { + __IOM uint32_t ICUSARD; /*!< (@ 0x0000004C) ICU Security Attribution Register D */ + + struct + { + __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0 */ + uint32_t : 31; + } ICUSARD_b; + }; + + union + { + __IOM uint32_t ICUSARE; /*!< (@ 0x00000050) ICU Security Attribution Register E */ + + struct + { + uint32_t : 16; + __IOM uint32_t SAIWDTWUP : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16 */ + uint32_t : 1; + __IOM uint32_t SALVD1WUP : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18 */ + __IOM uint32_t SALVD2WUP : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19 */ + uint32_t : 4; + __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24 */ + __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25 */ + uint32_t : 1; + __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27 */ + __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28 */ + __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29 */ + __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30 */ + __IOM uint32_t SAIIC0WUP : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31 */ + } ICUSARE_b; + }; + + union + { + __IOM uint32_t ICUSARF; /*!< (@ 0x00000054) ICU Security Attribution Register F */ + + struct + { + __IOM uint32_t SAAGT3UDWUP : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0 */ + __IOM uint32_t SAAGT3CAWUP : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1 */ + __IOM uint32_t SAAGT3CBWUP : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2 */ + uint32_t : 29; + } ICUSARF_b; + }; + __IM uint32_t RESERVED3[6]; + + union + { + __IOM uint32_t ICUSARG; /*!< (@ 0x00000070) ICU Security Attribution Register G */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0 */ + } ICUSARG_b; + }; + + union + { + __IOM uint32_t ICUSARH; /*!< (@ 0x00000074) ICU Security Attribution Register H */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32 */ + } ICUSARH_b; + }; + + union + { + __IOM uint32_t ICUSARI; /*!< (@ 0x00000078) ICU Security Attribution Register I */ + + struct + { + __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64 */ + } ICUSARI_b; + }; + __IM uint32_t RESERVED4[33]; + + union + { + __IOM uint32_t BUSSARA; /*!< (@ 0x00000100) Bus Security Attribution Register A */ + + struct + { + __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0 */ + uint32_t : 31; + } BUSSARA_b; + }; + + union + { + __IOM uint32_t BUSSARB; /*!< (@ 0x00000104) Bus Security Attribution Register B */ + + struct + { + __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0 */ + uint32_t : 31; + } BUSSARB_b; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t MMPUSARA; /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution + * Register A */ + + struct + { + __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7) */ + uint32_t : 24; + } MMPUSARA_b; + }; + + union + { + __IOM uint32_t MMPUSARB; /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution + * Register B */ + + struct + { + __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution */ + uint32_t : 31; + } MMPUSARB_b; + }; + __IM uint32_t RESERVED6[30]; + + union + { + __IOM uint32_t CPUDSAR; /*!< (@ 0x000001B0) CPU Debug Security Attribution Register */ + + struct + { + __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0 */ + uint32_t : 31; + } CPUDSAR_b; + }; +} R_CPSCU_Type; /*!< Size = 436 (0x1b4) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-bit A/D Converter (R_ADC_B0) + */ + +typedef struct /*!< (@ 0x40170000) R_ADC_B0 Structure */ +{ + union + { + __IOM uint32_t ADCLKENR; /*!< (@ 0x00000000) A/D Conversion Clock Enable Register */ + + struct + { + __IOM uint32_t CLKEN : 1; /*!< [0..0] ADCLK Operating Enable bit */ + uint32_t : 31; + } ADCLKENR_b; + }; + + union + { + __IM uint32_t ADCLKSR; /*!< (@ 0x00000004) A/D Conversion Clock Status Register */ + + struct + { + __IM uint32_t CLKSR : 1; /*!< [0..0] ADCLK status bit */ + uint32_t : 31; + } ADCLKSR_b; + }; + + union + { + __IOM uint32_t ADCLKCR; /*!< (@ 0x00000008) A/D Conversion Clock Control Register */ + + struct + { + __IOM uint32_t CLKSEL : 2; /*!< [1..0] ADCLK Clock Source Select */ + uint32_t : 14; + __IOM uint32_t DIVR : 3; /*!< [18..16] Clock Division Ratio Select */ + uint32_t : 13; + } ADCLKCR_b; + }; + + union + { + __IOM uint32_t ADSYCR; /*!< (@ 0x0000000C) A/D Converter Synchronous Operation Control Register */ + + struct + { + __IOM uint32_t ADSYCYC : 11; /*!< [10..0] A/D Converter Synchronous Operation Period Cycle */ + uint32_t : 5; + __IOM uint32_t ADSYDIS0 : 1; /*!< [16..16] ADC0 Synchronous Operation Select */ + __IOM uint32_t ADSYDIS1 : 1; /*!< [17..17] ADC1 Synchronous Operation Select */ + uint32_t : 14; + } ADSYCR_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t ADERINTCR; /*!< (@ 0x00000020) A/D Conversion Error Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADEIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Error Interrupt Enable */ + __IOM uint32_t ADEIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Error Interrupt Enable */ + uint32_t : 30; + } ADERINTCR_b; + }; + + union + { + __IOM uint32_t ADOVFINTCR; /*!< (@ 0x00000024) A/D Conversion Overflow Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADOVFIE0 : 1; /*!< [0..0] ADC0 A/D Conversion Overflow Interrupt Enable */ + __IOM uint32_t ADOVFIE1 : 1; /*!< [1..1] ADC1 A/D Conversion Overflow Interrupt Enable */ + uint32_t : 30; + } ADOVFINTCR_b; + }; + + union + { + __IOM uint32_t ADCALINTCR; /*!< (@ 0x00000028) Calibration interrupt Enable Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t CALENDIE0 : 1; /*!< [16..16] ADC0 Calibration End Interrupt Enable */ + __IOM uint32_t CALENDIE1 : 1; /*!< [17..17] ADC1 Calibration End Interrupt Enable */ + uint32_t : 14; + } ADCALINTCR_b; + }; + __IM uint32_t RESERVED1[5]; + + union + { + __IOM uint32_t ADMDR; /*!< (@ 0x00000040) A/D Converter Mode Selection Register */ + + struct + { + __IOM uint32_t ADMD0 : 4; /*!< [3..0] ADC0 Mode Selection */ + uint32_t : 4; + __IOM uint32_t ADMD1 : 4; /*!< [11..8] ADC1 Mode Selection */ + uint32_t : 20; + } ADMDR_b; + }; + + union + { + __IOM uint32_t ADGSPCR; /*!< (@ 0x00000044) A/D Group scan Priority Control Register */ + + struct + { + __IOM uint32_t PGS0 : 1; /*!< [0..0] ADC0 Group Priority Control Setting */ + __IOM uint32_t RSCN0 : 1; /*!< [1..1] ADC0 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS0 : 1; /*!< [2..2] ADC0 Group Priority Control Setting 3 */ + __IOM uint32_t GRP0 : 1; /*!< [3..3] ADC0 Group Priority Control Setting 4 */ + uint32_t : 4; + __IOM uint32_t PGS1 : 1; /*!< [8..8] ADC1 Group Priority Control Setting */ + __IOM uint32_t RSCN1 : 1; /*!< [9..9] ADC1 Group Priority Control Setting 2 */ + __IOM uint32_t LGRRS1 : 1; /*!< [10..10] ADC1 Group Priority Control Setting 3 */ + __IOM uint32_t GRP1 : 1; /*!< [11..11] ADC1 Group Priority Control Setting 4 */ + uint32_t : 20; + } ADGSPCR_b; + }; + + union + { + __IOM uint32_t ADSGER; /*!< (@ 0x00000048) Scan Group Enable Register */ + + struct + { + __IOM uint32_t SGREn : 9; /*!< [8..0] Scan Group n Enable */ + uint32_t : 23; + } ADSGER_b; + }; + + union + { + __IOM uint32_t ADSGCR0; /*!< (@ 0x0000004C) Scan Group Control Register 0 */ + + struct + { + __IOM uint32_t SGADS0 : 2; /*!< [1..0] Scan Group 0 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS1 : 2; /*!< [9..8] Scan Group 1 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS2 : 2; /*!< [17..16] Scan Group 2 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS3 : 2; /*!< [25..24] Scan Group 3 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR0_b; + }; + + union + { + __IOM uint32_t ADSGCR1; /*!< (@ 0x00000050) Scan Group Control Register 1 */ + + struct + { + __IOM uint32_t SGADS4 : 2; /*!< [1..0] Scan Group 4 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS5 : 2; /*!< [9..8] Scan Group 5 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS6 : 2; /*!< [17..16] Scan Group 6 A/D Converter Selection */ + uint32_t : 6; + __IOM uint32_t SGADS7 : 2; /*!< [25..24] Scan Group 7 A/D Converter Selection */ + uint32_t : 6; + } ADSGCR1_b; + }; + + union + { + __IOM uint32_t ADSGCR2; /*!< (@ 0x00000054) Scan Group Control Register 2 */ + + struct + { + __IOM uint32_t SGADS8 : 2; /*!< [1..0] Scan Group 8 A/D Converter Selection */ + uint32_t : 30; + } ADSGCR2_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t ADINTCR; /*!< (@ 0x0000005C) Scan End Interrupt Enable Register */ + + struct + { + __IOM uint32_t ADIEn : 10; /*!< [9..0] Scan Group n Scan End Interrupt Enable */ + uint32_t : 22; + } ADINTCR_b; + }; + __IM uint32_t RESERVED3[24]; + + union + { + __IOM uint32_t ADTRGEXT0; /*!< (@ 0x000000C0) External Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT0_b; + }; + + union + { + __IOM uint32_t ADTRGELC0; /*!< (@ 0x000000C4) ELC Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC0_b; + }; + + union + { + __IOM uint32_t ADTRGGPT0; /*!< (@ 0x000000C8) GPT Trigger Enable Register 0 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT0_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t ADTRGEXT1; /*!< (@ 0x000000D0) External Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT1_b; + }; + + union + { + __IOM uint32_t ADTRGELC1; /*!< (@ 0x000000D4) ELC Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC1_b; + }; + + union + { + __IOM uint32_t ADTRGGPT1; /*!< (@ 0x000000D8) GPT Trigger Enable Register 1 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT1_b; + }; + __IM uint32_t RESERVED5; + + union + { + __IOM uint32_t ADTRGEXT2; /*!< (@ 0x000000E0) External Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT2_b; + }; + + union + { + __IOM uint32_t ADTRGELC2; /*!< (@ 0x000000E4) ELC Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC2_b; + }; + + union + { + __IOM uint32_t ADTRGGPT2; /*!< (@ 0x000000E8) GPT Trigger Enable Register 2 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT2_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t ADTRGEXT3; /*!< (@ 0x000000F0) External Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT3_b; + }; + + union + { + __IOM uint32_t ADTRGELC3; /*!< (@ 0x000000F4) ELC Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC3_b; + }; + + union + { + __IOM uint32_t ADTRGGPT3; /*!< (@ 0x000000F8) GPT Trigger Enable Register 3 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT3_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint32_t ADTRGEXT4; /*!< (@ 0x00000100) External Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT4_b; + }; + + union + { + __IOM uint32_t ADTRGELC4; /*!< (@ 0x00000104) ELC Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC4_b; + }; + + union + { + __IOM uint32_t ADTRGGPT4; /*!< (@ 0x00000108) GPT Trigger Enable Register 4 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT4_b; + }; + __IM uint32_t RESERVED8; + + union + { + __IOM uint32_t ADTRGEXT5; /*!< (@ 0x00000110) External Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT5_b; + }; + + union + { + __IOM uint32_t ADTRGELC5; /*!< (@ 0x00000114) ELC Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC5_b; + }; + + union + { + __IOM uint32_t ADTRGGPT5; /*!< (@ 0x00000118) GPT Trigger Enable Register 5 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT5_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IOM uint32_t ADTRGEXT6; /*!< (@ 0x00000120) External Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT6_b; + }; + + union + { + __IOM uint32_t ADTRGELC6; /*!< (@ 0x00000124) ELC Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC6_b; + }; + + union + { + __IOM uint32_t ADTRGGPT6; /*!< (@ 0x00000128) GPT Trigger Enable Register 6 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT6_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t ADTRGEXT7; /*!< (@ 0x00000130) External Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT7_b; + }; + + union + { + __IOM uint32_t ADTRGELC7; /*!< (@ 0x00000134) ELC Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC7_b; + }; + + union + { + __IOM uint32_t ADTRGGPT7; /*!< (@ 0x00000138) GPT Trigger Enable Register 7 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT7_b; + }; + __IM uint32_t RESERVED11; + + union + { + __IOM uint32_t ADTRGEXT8; /*!< (@ 0x00000140) External Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGEXT0 : 1; /*!< [0..0] External Trigger Input 0 (ADTRG0) Enable */ + __IOM uint32_t TRGEXT1 : 1; /*!< [1..1] External Trigger Input 1 (ADTRG1) Enable */ + uint32_t : 30; + } ADTRGEXT8_b; + }; + + union + { + __IOM uint32_t ADTRGELC8; /*!< (@ 0x00000144) ELC Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGELCm : 6; /*!< [5..0] ELC Trigger m Enable */ + uint32_t : 26; + } ADTRGELC8_b; + }; + + union + { + __IOM uint32_t ADTRGGPT8; /*!< (@ 0x00000148) GPT Trigger Enable Register 8 */ + + struct + { + __IOM uint32_t TRGGPTAm : 10; /*!< [9..0] GPT channel m A/D Conversion Starting Request A Enable */ + uint32_t : 6; + __IOM uint32_t TRGGPTBm : 10; /*!< [25..16] GPT channel m A/D Conversion Starting Request B Enable */ + uint32_t : 6; + } ADTRGGPT8_b; + }; + __IM uint32_t RESERVED12[29]; + + union + { + __IOM uint32_t ADTRGDLR0; /*!< (@ 0x000001C0) A/D Conversion Start Trigger Delay Register 0 */ + + struct + { + __IOM uint32_t TRGDLY0 : 8; /*!< [7..0] Scan Group 0 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY1 : 8; /*!< [23..16] Scan Group 1 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR0_b; + }; + + union + { + __IOM uint32_t ADTRGDLR1; /*!< (@ 0x000001C4) A/D Conversion Start Trigger Delay Register 1 */ + + struct + { + __IOM uint32_t TRGDLY2 : 8; /*!< [7..0] Scan Group 2 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY3 : 8; /*!< [23..16] Scan Group 3 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR1_b; + }; + + union + { + __IOM uint32_t ADTRGDLR2; /*!< (@ 0x000001C8) A/D Conversion Start Trigger Delay Register 2 */ + + struct + { + __IOM uint32_t TRGDLY4 : 8; /*!< [7..0] Scan Group 4 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY5 : 8; /*!< [23..16] Scan Group 5 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR2_b; + }; + + union + { + __IOM uint32_t ADTRGDLR3; /*!< (@ 0x000001CC) A/D Conversion Start Trigger Delay Register 3 */ + + struct + { + __IOM uint32_t TRGDLY6 : 8; /*!< [7..0] Scan Group 6 Trigger Input Delay Configuration */ + uint32_t : 8; + __IOM uint32_t TRGDLY7 : 8; /*!< [23..16] Scan Group 7 Trigger Input Delay Configuration */ + uint32_t : 8; + } ADTRGDLR3_b; + }; + + union + { + __IOM uint32_t ADTRGDLR4; /*!< (@ 0x000001D0) A/D Conversion Start Trigger Delay Register 4 */ + + struct + { + __IOM uint32_t TRGDLY8 : 8; /*!< [7..0] Scan Group 8 Trigger Input Delay Configuration */ + uint32_t : 24; + } ADTRGDLR4_b; + }; + __IM uint32_t RESERVED13[11]; + + union + { + __IOM uint32_t ADSGDCR0; /*!< (@ 0x00000200) Scan Group Diagnosis Function Control Register + * 0 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR0_b; + }; + + union + { + __IOM uint32_t ADSGDCR1; /*!< (@ 0x00000204) Scan Group Diagnosis Function Control Register + * 1 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR1_b; + }; + + union + { + __IOM uint32_t ADSGDCR2; /*!< (@ 0x00000208) Scan Group Diagnosis Function Control Register + * 2 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR2_b; + }; + + union + { + __IOM uint32_t ADSGDCR3; /*!< (@ 0x0000020C) Scan Group Diagnosis Function Control Register + * 3 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR3_b; + }; + + union + { + __IOM uint32_t ADSGDCR4; /*!< (@ 0x00000210) Scan Group Diagnosis Function Control Register + * 4 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR4_b; + }; + + union + { + __IOM uint32_t ADSGDCR5; /*!< (@ 0x00000214) Scan Group Diagnosis Function Control Register + * 5 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR5_b; + }; + + union + { + __IOM uint32_t ADSGDCR6; /*!< (@ 0x00000218) Scan Group Diagnosis Function Control Register + * 6 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR6_b; + }; + + union + { + __IOM uint32_t ADSGDCR7; /*!< (@ 0x0000021C) Scan Group Diagnosis Function Control Register + * 7 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR7_b; + }; + + union + { + __IOM uint32_t ADSGDCR8; /*!< (@ 0x00000220) Scan Group Diagnosis Function Control Register + * 8 */ + + struct + { + __IOM uint32_t DIAGVAL : 3; /*!< [2..0] Self-diagnosis Voltage Selection */ + uint32_t : 13; + __IOM uint32_t ADDISEN : 1; /*!< [16..16] Disconnection Detection Assist Enable */ + uint32_t : 3; + __IOM uint32_t ADDISP : 1; /*!< [20..20] Disconnection Detection Assist Mode Selection */ + __IOM uint32_t ADDISN : 1; /*!< [21..21] Disconnection Detection Assist Mode Selection */ + uint32_t : 2; + __IOM uint32_t ADNDIS : 4; /*!< [27..24] Disconnection Detection Assist Period */ + uint32_t : 4; + } ADSGDCR8_b; + }; + __IM uint32_t RESERVED14[7]; + + union + { + __IOM uint32_t ADSSTR0; /*!< (@ 0x00000240) Sampling State Table Register 0 */ + + struct + { + __IOM uint32_t SST0 : 10; /*!< [9..0] Sampling State Table 0 */ + uint32_t : 6; + __IOM uint32_t SST1 : 10; /*!< [25..16] Sampling State Table 1 */ + uint32_t : 6; + } ADSSTR0_b; + }; + + union + { + __IOM uint32_t ADSSTR1; /*!< (@ 0x00000244) Sampling State Table Register 1 */ + + struct + { + __IOM uint32_t SST2 : 10; /*!< [9..0] Sampling State Table 2 */ + uint32_t : 6; + __IOM uint32_t SST3 : 10; /*!< [25..16] Sampling State Table 3 */ + uint32_t : 6; + } ADSSTR1_b; + }; + + union + { + __IOM uint32_t ADSSTR2; /*!< (@ 0x00000248) Sampling State Table Register 2 */ + + struct + { + __IOM uint32_t SST4 : 10; /*!< [9..0] Sampling State Table 4 */ + uint32_t : 6; + __IOM uint32_t SST5 : 10; /*!< [25..16] Sampling State Table 5 */ + uint32_t : 6; + } ADSSTR2_b; + }; + + union + { + __IOM uint32_t ADSSTR3; /*!< (@ 0x0000024C) Sampling State Table Register 3 */ + + struct + { + __IOM uint32_t SST6 : 10; /*!< [9..0] Sampling State Table 6 */ + uint32_t : 6; + __IOM uint32_t SST7 : 10; /*!< [25..16] Sampling State Table 7 */ + uint32_t : 6; + } ADSSTR3_b; + }; + + union + { + __IOM uint32_t ADSSTR4; /*!< (@ 0x00000250) Sampling State Table Register 4 */ + + struct + { + __IOM uint32_t SST8 : 10; /*!< [9..0] Sampling State Table 8 */ + uint32_t : 6; + __IOM uint32_t SST9 : 10; /*!< [25..16] Sampling State Table 9 */ + uint32_t : 6; + } ADSSTR4_b; + }; + + union + { + __IOM uint32_t ADSSTR5; /*!< (@ 0x00000254) Sampling State Table Register 5 */ + + struct + { + __IOM uint32_t SST10 : 10; /*!< [9..0] Sampling State Table 10 */ + uint32_t : 6; + __IOM uint32_t SST11 : 10; /*!< [25..16] Sampling State Table 11 */ + uint32_t : 6; + } ADSSTR5_b; + }; + + union + { + __IOM uint32_t ADSSTR6; /*!< (@ 0x00000258) Sampling State Table Register 6 */ + + struct + { + __IOM uint32_t SST12 : 10; /*!< [9..0] Sampling State Table 12 */ + uint32_t : 6; + __IOM uint32_t SST13 : 10; /*!< [25..16] Sampling State Table 13 */ + uint32_t : 6; + } ADSSTR6_b; + }; + + union + { + __IOM uint32_t ADSSTR7; /*!< (@ 0x0000025C) Sampling State Table Register 7 */ + + struct + { + __IOM uint32_t SST14 : 10; /*!< [9..0] Sampling State Table 14 */ + uint32_t : 6; + __IOM uint32_t SST15 : 10; /*!< [25..16] Sampling State Table 15 */ + uint32_t : 6; + } ADSSTR7_b; + }; + + union + { + __IOM uint32_t ADCNVSTR; /*!< (@ 0x00000260) A/D Conversion State Register */ + + struct + { + __IOM uint32_t CST0 : 6; /*!< [5..0] A/D Converter Unit 0 (ADC0) */ + uint32_t : 2; + __IOM uint32_t CST1 : 6; /*!< [13..8] A/D Converter Unit 1 (ADC1) */ + uint32_t : 18; + } ADCNVSTR_b; + }; + + union + { + __IOM uint32_t ADCALSTCR; /*!< (@ 0x00000264) A/D Converter Calibration State Register */ + + struct + { + __IOM uint32_t CALADSST : 10; /*!< [9..0] A/D Converter Calibration Sampling Time Configuration */ + uint32_t : 6; + __IOM uint32_t CALADCST : 6; /*!< [21..16] A/D Converter Calibration Conversion Time Configuration. */ + uint32_t : 10; + } ADCALSTCR_b; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t ADSHCR0; /*!< (@ 0x00000280) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 0 */ + + struct + { + __IOM uint32_t SHEN0 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 Select */ + __IOM uint32_t SHEN1 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 1 Select */ + __IOM uint32_t SHEN2 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 2 Select */ + uint32_t : 29; + } ADSHCR0_b; + }; + __IM uint32_t RESERVED16; + + union + { + __IOM uint32_t ADSHSTR0; /*!< (@ 0x00000288) Channel-Dedicated Sample & Hold Circuit State + * Register 0 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to 2 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 0 to + * 2 */ + uint32_t : 13; + } ADSHSTR0_b; + }; + + union + { + __IOM uint32_t ADSHCR1; /*!< (@ 0x0000028C) Channel-Dedicated Sample-and-Hold Circuit Control + * Register 1 */ + + struct + { + __IOM uint32_t SHEN4 : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 Select */ + __IOM uint32_t SHEN5 : 1; /*!< [1..1] Channel-Dedicated Sample-and-Hold Circuit Unit 5 Select */ + __IOM uint32_t SHEN6 : 1; /*!< [2..2] Channel-Dedicated Sample-and-Hold Circuit Unit 6 Select */ + uint32_t : 29; + } ADSHCR1_b; + }; + __IM uint32_t RESERVED17; + + union + { + __IOM uint32_t ADSHSTR1; /*!< (@ 0x00000294) Channel-Dedicated Sample & Hold Circuit State + * Register 1 */ + + struct + { + __IOM uint32_t SHSST : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to 6 */ + uint32_t : 8; + __IOM uint32_t SHHST : 3; /*!< [18..16] Channel-Dedicated Sample-and-Hold Circuit Unit 4 to + * 6 */ + uint32_t : 13; + } ADSHSTR1_b; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t ADCALSHCR; /*!< (@ 0x000002B0) Channel-Dedicated Sample & Hold Circuit Calibration + * State Register */ + + struct + { + __IOM uint32_t CALSHSST : 8; /*!< [7..0] Channel-Dedicated Sample & Hold Circuit Calibration Sampling + * Time Configuration */ + uint32_t : 8; + __IOM uint32_t CALSHHST : 3; /*!< [18..16] Channel-Dedicated Sample & Hold Circuit Calibration + * Holding Time Configuration */ + uint32_t : 13; + } ADCALSHCR_b; + }; + __IM uint32_t RESERVED19[3]; + + union + { + __IOM uint32_t ADPGACR[4]; /*!< (@ 0x000002C0) Programmable Gain Amplifier Control Register + * [0..3] */ + + struct + { + uint32_t : 1; + __IOM uint32_t PGADEN : 1; /*!< [1..1] PGA Unit n Input Mode Select */ + __IOM uint32_t PGASEL1 : 1; /*!< [2..2] PGA Unit n Transit Enable */ + __IOM uint32_t PGAENAMP : 1; /*!< [3..3] PGA Unit n Enable */ + uint32_t : 12; + __IOM uint32_t PGAGEN : 1; /*!< [16..16] PGA Unit n Gain Setting Enable */ + uint32_t : 3; + __IOM uint32_t PGADG : 2; /*!< [21..20] PGA Unit n Differential Input Gain Setting */ + uint32_t : 2; + __IOM uint32_t PGAGAIN : 4; /*!< [27..24] PGA Unit n Gain Setting */ + uint32_t : 4; + } ADPGACR_b[4]; + }; + __IM uint32_t RESERVED20[12]; + + union + { + __IOM uint32_t ADPGAMONCR; /*!< (@ 0x00000300) Programable Gain Amp Monitor Output Control Register */ + + struct + { + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Signal Selection */ + uint32_t : 13; + __IOM uint32_t MONSEL0 : 1; /*!< [16..16] PGA Unit 0 Monitor Output Enable */ + __IOM uint32_t MONSEL1 : 1; /*!< [17..17] PGA Unit 1 Monitor Output Enable */ + __IOM uint32_t MONSEL2 : 1; /*!< [18..18] PGA Unit 2 Monitor Output Enable */ + __IOM uint32_t MONSEL3 : 1; /*!< [19..19] PGA Unit 3 Monitor Output Enable */ + uint32_t : 12; + } ADPGAMONCR_b; + }; + __IM uint32_t RESERVED21[7]; + + union + { + __IOM uint32_t ADREFCR; /*!< (@ 0x00000320) Internal Reference Voltage Monitor Enable Register */ + + struct + { + __IOM uint32_t VDE : 1; /*!< [0..0] Internal Reference Voltage A/D Conversion Select */ + uint32_t : 31; + } ADREFCR_b; + }; + __IM uint32_t RESERVED22[7]; + + union + { + __IOM uint32_t ADDFSR0; /*!< (@ 0x00000340) A/D Converter Digital Filter Selection Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR0_b; + }; + + union + { + __IOM uint32_t ADDFSR1; /*!< (@ 0x00000344) A/D Converter Digital Filter Selection Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL0 : 2; /*!< [1..0] A/D Converter unit the 1st digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL1 : 2; /*!< [9..8] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL2 : 2; /*!< [17..16] A/D Converter unit the 2nd digital filter characteristic + * selection. */ + uint32_t : 6; + __IOM uint32_t DFSEL3 : 2; /*!< [25..24] A/D Converter unit the 4th digital filter characteristic + * selection. */ + uint32_t : 6; + } ADDFSR1_b; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t ADUOFTR0; /*!< (@ 0x00000360) User Offset Table Register 0 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR0_b; + }; + + union + { + __IOM uint32_t ADUOFTR1; /*!< (@ 0x00000364) User Offset Table Register 1 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR1_b; + }; + + union + { + __IOM uint32_t ADUOFTR2; /*!< (@ 0x00000368) User Offset Table Register 2 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR2_b; + }; + + union + { + __IOM uint32_t ADUOFTR3; /*!< (@ 0x0000036C) User Offset Table Register 3 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR3_b; + }; + + union + { + __IOM uint32_t ADUOFTR4; /*!< (@ 0x00000370) User Offset Table Register 4 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR4_b; + }; + + union + { + __IOM uint32_t ADUOFTR5; /*!< (@ 0x00000374) User Offset Table Register 5 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR5_b; + }; + + union + { + __IOM uint32_t ADUOFTR6; /*!< (@ 0x00000378) User Offset Table Register 6 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR6_b; + }; + + union + { + __IOM uint32_t ADUOFTR7; /*!< (@ 0x0000037C) User Offset Table Register 7 */ + + struct + { + __IOM uint32_t UOFSET : 16; /*!< [15..0] User Offset Table n */ + uint32_t : 16; + } ADUOFTR7_b; + }; + + union + { + __IOM uint32_t ADUGTR0; /*!< (@ 0x00000380) User Gain Table Register 0 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR0_b; + }; + + union + { + __IOM uint32_t ADUGTR1; /*!< (@ 0x00000384) User Gain Table Register 1 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR1_b; + }; + + union + { + __IOM uint32_t ADUGTR2; /*!< (@ 0x00000388) User Gain Table Register 2 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR2_b; + }; + + union + { + __IOM uint32_t ADUGTR3; /*!< (@ 0x0000038C) User Gain Table Register 3 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR3_b; + }; + + union + { + __IOM uint32_t ADUGTR4; /*!< (@ 0x00000390) User Gain Table Register 4 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR4_b; + }; + + union + { + __IOM uint32_t ADUGTR5; /*!< (@ 0x00000394) User Gain Table Register 5 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR5_b; + }; + + union + { + __IOM uint32_t ADUGTR6; /*!< (@ 0x00000398) User Gain Table Register 6 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR6_b; + }; + + union + { + __IOM uint32_t ADUGTR7; /*!< (@ 0x0000039C) User Gain Table Register 7 */ + + struct + { + __IOM uint32_t UGAIN : 24; /*!< [23..0] User Gain Table n */ + uint32_t : 8; + } ADUGTR7_b; + }; + + union + { + __IOM uint32_t ADLIMINTCR; /*!< (@ 0x000003A0) Limiter Clip Interrupt Enable Register */ + + struct + { + __IOM uint32_t LIMIEn : 9; /*!< [8..0] Limiter Clip Interrupt n Enable bit */ + uint32_t : 23; + } ADLIMINTCR_b; + }; + + union + { + __IOM uint32_t ADLIMTR0; /*!< (@ 0x000003A4) Limiter Clip Table Register 0 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR0_b; + }; + + union + { + __IOM uint32_t ADLIMTR1; /*!< (@ 0x000003A8) Limiter Clip Table Register 1 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR1_b; + }; + + union + { + __IOM uint32_t ADLIMTR2; /*!< (@ 0x000003AC) Limiter Clip Table Register 2 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR2_b; + }; + + union + { + __IOM uint32_t ADLIMTR3; /*!< (@ 0x000003B0) Limiter Clip Table Register 3 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR3_b; + }; + + union + { + __IOM uint32_t ADLIMTR4; /*!< (@ 0x000003B4) Limiter Clip Table Register 4 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR4_b; + }; + + union + { + __IOM uint32_t ADLIMTR5; /*!< (@ 0x000003B8) Limiter Clip Table Register 5 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR5_b; + }; + + union + { + __IOM uint32_t ADLIMTR6; /*!< (@ 0x000003BC) Limiter Clip Table Register 6 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR6_b; + }; + + union + { + __IOM uint32_t ADLIMTR7; /*!< (@ 0x000003C0) Limiter Clip Table Register 7 */ + + struct + { + __IOM uint32_t LIML : 16; /*!< [15..0] Limiter clip table n : Lower-side limit value */ + __IOM uint32_t LIMU : 16; /*!< [31..16] Limiter clip table n : Upper-side limit value */ + } ADLIMTR7_b; + }; + __IM uint32_t RESERVED24[15]; + + union + { + __IOM uint32_t ADCMPENR; /*!< (@ 0x00000400) Compare Match Enable Register */ + + struct + { + __IOM uint32_t CMPENn : 8; /*!< [7..0] Compare Match n Enable */ + uint32_t : 24; + } ADCMPENR_b; + }; + + union + { + __IOM uint32_t ADCMPINTCR; /*!< (@ 0x00000404) Compare Match Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMPIEn : 4; /*!< [3..0] Compare Match Interrupt n Enable */ + uint32_t : 28; + } ADCMPINTCR_b; + }; + + union + { + __IOM uint32_t ADCCMPCR0; /*!< (@ 0x00000408) Composite Compare Match Configuration Register + * 0 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR0_b; + }; + + union + { + __IOM uint32_t ADCCMPCR1; /*!< (@ 0x0000040C) Composite Compare Match Configuration Register + * 1 */ + + struct + { + __IOM uint32_t CCMPCND : 2; /*!< [1..0] Composite Compare Match Condition Selection */ + uint32_t : 14; + __IOM uint32_t CCMPTBLm : 8; /*!< [23..16] Composite Compare Match Condition Table Selection */ + uint32_t : 8; + } ADCCMPCR1_b; + }; + __IM uint32_t RESERVED25[14]; + + union + { + __IOM uint32_t ADCMPMDR0; /*!< (@ 0x00000448) Compare Match Mode Selection Register 0 */ + + struct + { + __IOM uint32_t CMPMD0 : 2; /*!< [1..0] Compare Match 0 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD1 : 2; /*!< [9..8] Compare Match 1 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD2 : 2; /*!< [17..16] Compare Match 2 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD3 : 2; /*!< [25..24] Compare Match 3 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR0_b; + }; + + union + { + __IOM uint32_t ADCMPMDR1; /*!< (@ 0x0000044C) Compare Match Mode Selection Register 1 */ + + struct + { + __IOM uint32_t CMPMD4 : 2; /*!< [1..0] Compare Match 4 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD5 : 2; /*!< [9..8] Compare Match 5 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD6 : 2; /*!< [17..16] Compare Match 6 : Match Mode Selection */ + uint32_t : 6; + __IOM uint32_t CMPMD7 : 2; /*!< [25..24] Compare Match 7 : Match Mode Selection */ + uint32_t : 6; + } ADCMPMDR1_b; + }; + __IM uint32_t RESERVED26[2]; + + union + { + __IOM uint32_t ADCMPTBR0; /*!< (@ 0x00000458) Compare Match Table Register 0 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR0_b; + }; + + union + { + __IOM uint32_t ADCMPTBR1; /*!< (@ 0x0000045C) Compare Match Table Register 1 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR1_b; + }; + + union + { + __IOM uint32_t ADCMPTBR2; /*!< (@ 0x00000460) Compare Match Table Register 2 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR2_b; + }; + + union + { + __IOM uint32_t ADCMPTBR3; /*!< (@ 0x00000464) Compare Match Table Register 3 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR3_b; + }; + + union + { + __IOM uint32_t ADCMPTBR4; /*!< (@ 0x00000468) Compare Match Table Register 4 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR4_b; + }; + + union + { + __IOM uint32_t ADCMPTBR5; /*!< (@ 0x0000046C) Compare Match Table Register 5 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR5_b; + }; + + union + { + __IOM uint32_t ADCMPTBR6; /*!< (@ 0x00000470) Compare Match Table Register 6 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR6_b; + }; + + union + { + __IOM uint32_t ADCMPTBR7; /*!< (@ 0x00000474) Compare Match Table Register 7 */ + + struct + { + __IOM uint32_t CMPTBL : 16; /*!< [15..0] Compare Match Table n : Low-side level */ + __IOM uint32_t CMPTBH : 16; /*!< [31..16] Compare Match Table n : High-side level */ + } ADCMPTBR7_b; + }; + __IM uint32_t RESERVED27[18]; + + union + { + __IOM uint32_t ADFIFOCR; /*!< (@ 0x000004C0) FIFO Control Register */ + + struct + { + __IOM uint32_t FIFOEN0 : 1; /*!< [0..0] Scan Group 0 FIFO Enable */ + __IOM uint32_t FIFOEN1 : 1; /*!< [1..1] Scan Group 1 FIFO Enable */ + __IOM uint32_t FIFOEN2 : 1; /*!< [2..2] Scan Group 2 FIFO Enable */ + __IOM uint32_t FIFOEN3 : 1; /*!< [3..3] Scan Group 3 FIFO Enable */ + __IOM uint32_t FIFOEN4 : 1; /*!< [4..4] Scan Group 4 FIFO Enable */ + __IOM uint32_t FIFOEN5 : 1; /*!< [5..5] Scan Group 5 FIFO Enable */ + __IOM uint32_t FIFOEN6 : 1; /*!< [6..6] Scan Group 6 FIFO Enable */ + __IOM uint32_t FIFOEN7 : 1; /*!< [7..7] Scan Group 7 FIFO Enable */ + __IOM uint32_t FIFOEN8 : 1; /*!< [8..8] Scan Group 8 FIFO Enable */ + uint32_t : 23; + } ADFIFOCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTCR; /*!< (@ 0x000004C4) FIFO Interrupt Control Register */ + + struct + { + __IOM uint32_t FIFOIE0 : 1; /*!< [0..0] Scan Group 0 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE1 : 1; /*!< [1..1] Scan Group 1 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE2 : 1; /*!< [2..2] Scan Group 2 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE3 : 1; /*!< [3..3] Scan Group 3 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE4 : 1; /*!< [4..4] Scan Group 4 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE5 : 1; /*!< [5..5] Scan Group 5 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE6 : 1; /*!< [6..6] Scan Group 6 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE7 : 1; /*!< [7..7] Scan Group 7 FIFO Interrupt Enable */ + __IOM uint32_t FIFOIE8 : 1; /*!< [8..8] Scan Group 8 FIFO Interrupt Enable */ + uint32_t : 23; + } ADFIFOINTCR_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR0; /*!< (@ 0x000004C8) FIFO Interrupt Generation Level Register 0 */ + + struct + { + __IOM uint32_t FIFOILV0 : 4; /*!< [3..0] Scan Group 0 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV1 : 4; /*!< [19..16] Scan Group 1 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR0_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR1; /*!< (@ 0x000004CC) FIFO Interrupt Generation Level Register 1 */ + + struct + { + __IOM uint32_t FIFOILV2 : 4; /*!< [3..0] Scan Group 2 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV3 : 4; /*!< [19..16] Scan Group 3 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR1_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR2; /*!< (@ 0x000004D0) FIFO Interrupt Generation Level Register 2 */ + + struct + { + __IOM uint32_t FIFOILV4 : 4; /*!< [3..0] Scan Group 4 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV5 : 4; /*!< [19..16] Scan Group 5 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR2_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR3; /*!< (@ 0x000004D4) FIFO Interrupt Generation Level Register 3 */ + + struct + { + __IOM uint32_t FIFOILV6 : 4; /*!< [3..0] Scan Group 6 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + __IOM uint32_t FIFOILV7 : 4; /*!< [19..16] Scan Group 7 FIFO Interrupt Output Timing Setting */ + uint32_t : 12; + } ADFIFOINTLR3_b; + }; + + union + { + __IOM uint32_t ADFIFOINTLR4; /*!< (@ 0x000004D8) FIFO Interrupt Generation Level Register 4 */ + + struct + { + __IOM uint32_t FIFOILV8 : 4; /*!< [3..0] Scan Group 8 FIFO Interrupt Output Timing Setting */ + uint32_t : 28; + } ADFIFOINTLR4_b; + }; + __IM uint32_t RESERVED28[73]; + + union + { + __IOM uint32_t ADCHCR0; /*!< (@ 0x00000600) A/D Conversion Channel Configuration Register + * 0 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR0_b; + }; + + union + { + __IOM uint32_t ADDOPCRA0; /*!< (@ 0x00000604) A/D Conversion Data Operation Control A Register + * 0 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA0_b; + }; + + union + { + __IOM uint32_t ADDOPCRB0; /*!< (@ 0x00000608) A/D Conversion Data Operation Control B Register + * 0 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB0_b; + }; + + union + { + __IOM uint32_t ADDOPCRC0; /*!< (@ 0x0000060C) A/D Conversion Data Operation Control C Register + * 0 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC0_b; + }; + + union + { + __IOM uint32_t ADCHCR1; /*!< (@ 0x00000610) A/D Conversion Channel Configuration Register + * 1 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR1_b; + }; + + union + { + __IOM uint32_t ADDOPCRA1; /*!< (@ 0x00000614) A/D Conversion Data Operation Control A Register + * 1 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA1_b; + }; + + union + { + __IOM uint32_t ADDOPCRB1; /*!< (@ 0x00000618) A/D Conversion Data Operation Control B Register + * 1 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB1_b; + }; + + union + { + __IOM uint32_t ADDOPCRC1; /*!< (@ 0x0000061C) A/D Conversion Data Operation Control C Register + * 1 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC1_b; + }; + + union + { + __IOM uint32_t ADCHCR2; /*!< (@ 0x00000620) A/D Conversion Channel Configuration Register + * 2 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR2_b; + }; + + union + { + __IOM uint32_t ADDOPCRA2; /*!< (@ 0x00000624) A/D Conversion Data Operation Control A Register + * 2 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA2_b; + }; + + union + { + __IOM uint32_t ADDOPCRB2; /*!< (@ 0x00000628) A/D Conversion Data Operation Control B Register + * 2 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB2_b; + }; + + union + { + __IOM uint32_t ADDOPCRC2; /*!< (@ 0x0000062C) A/D Conversion Data Operation Control C Register + * 2 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC2_b; + }; + + union + { + __IOM uint32_t ADCHCR3; /*!< (@ 0x00000630) A/D Conversion Channel Configuration Register + * 3 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR3_b; + }; + + union + { + __IOM uint32_t ADDOPCRA3; /*!< (@ 0x00000634) A/D Conversion Data Operation Control A Register + * 3 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA3_b; + }; + + union + { + __IOM uint32_t ADDOPCRB3; /*!< (@ 0x00000638) A/D Conversion Data Operation Control B Register + * 3 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB3_b; + }; + + union + { + __IOM uint32_t ADDOPCRC3; /*!< (@ 0x0000063C) A/D Conversion Data Operation Control C Register + * 3 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC3_b; + }; + + union + { + __IOM uint32_t ADCHCR4; /*!< (@ 0x00000640) A/D Conversion Channel Configuration Register + * 4 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR4_b; + }; + + union + { + __IOM uint32_t ADDOPCRA4; /*!< (@ 0x00000644) A/D Conversion Data Operation Control A Register + * 4 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA4_b; + }; + + union + { + __IOM uint32_t ADDOPCRB4; /*!< (@ 0x00000648) A/D Conversion Data Operation Control B Register + * 4 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB4_b; + }; + + union + { + __IOM uint32_t ADDOPCRC4; /*!< (@ 0x0000064C) A/D Conversion Data Operation Control C Register + * 4 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC4_b; + }; + + union + { + __IOM uint32_t ADCHCR5; /*!< (@ 0x00000650) A/D Conversion Channel Configuration Register + * 5 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR5_b; + }; + + union + { + __IOM uint32_t ADDOPCRA5; /*!< (@ 0x00000654) A/D Conversion Data Operation Control A Register + * 5 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA5_b; + }; + + union + { + __IOM uint32_t ADDOPCRB5; /*!< (@ 0x00000658) A/D Conversion Data Operation Control B Register + * 5 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB5_b; + }; + + union + { + __IOM uint32_t ADDOPCRC5; /*!< (@ 0x0000065C) A/D Conversion Data Operation Control C Register + * 5 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC5_b; + }; + + union + { + __IOM uint32_t ADCHCR6; /*!< (@ 0x00000660) A/D Conversion Channel Configuration Register + * 6 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR6_b; + }; + + union + { + __IOM uint32_t ADDOPCRA6; /*!< (@ 0x00000664) A/D Conversion Data Operation Control A Register + * 6 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA6_b; + }; + + union + { + __IOM uint32_t ADDOPCRB6; /*!< (@ 0x00000668) A/D Conversion Data Operation Control B Register + * 6 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB6_b; + }; + + union + { + __IOM uint32_t ADDOPCRC6; /*!< (@ 0x0000066C) A/D Conversion Data Operation Control C Register + * 6 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC6_b; + }; + + union + { + __IOM uint32_t ADCHCR7; /*!< (@ 0x00000670) A/D Conversion Channel Configuration Register + * 7 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR7_b; + }; + + union + { + __IOM uint32_t ADDOPCRA7; /*!< (@ 0x00000674) A/D Conversion Data Operation Control A Register + * 7 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA7_b; + }; + + union + { + __IOM uint32_t ADDOPCRB7; /*!< (@ 0x00000678) A/D Conversion Data Operation Control B Register + * 7 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB7_b; + }; + + union + { + __IOM uint32_t ADDOPCRC7; /*!< (@ 0x0000067C) A/D Conversion Data Operation Control C Register + * 7 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC7_b; + }; + + union + { + __IOM uint32_t ADCHCR8; /*!< (@ 0x00000680) A/D Conversion Channel Configuration Register + * 8 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR8_b; + }; + + union + { + __IOM uint32_t ADDOPCRA8; /*!< (@ 0x00000684) A/D Conversion Data Operation Control A Register + * 8 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA8_b; + }; + + union + { + __IOM uint32_t ADDOPCRB8; /*!< (@ 0x00000688) A/D Conversion Data Operation Control B Register + * 8 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB8_b; + }; + + union + { + __IOM uint32_t ADDOPCRC8; /*!< (@ 0x0000068C) A/D Conversion Data Operation Control C Register + * 8 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC8_b; + }; + + union + { + __IOM uint32_t ADCHCR9; /*!< (@ 0x00000690) A/D Conversion Channel Configuration Register + * 9 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR9_b; + }; + + union + { + __IOM uint32_t ADDOPCRA9; /*!< (@ 0x00000694) A/D Conversion Data Operation Control A Register + * 9 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA9_b; + }; + + union + { + __IOM uint32_t ADDOPCRB9; /*!< (@ 0x00000698) A/D Conversion Data Operation Control B Register + * 9 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB9_b; + }; + + union + { + __IOM uint32_t ADDOPCRC9; /*!< (@ 0x0000069C) A/D Conversion Data Operation Control C Register + * 9 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC9_b; + }; + + union + { + __IOM uint32_t ADCHCR10; /*!< (@ 0x000006A0) A/D Conversion Channel Configuration Register + * 10 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR10_b; + }; + + union + { + __IOM uint32_t ADDOPCRA10; /*!< (@ 0x000006A4) A/D Conversion Data Operation Control A Register + * 10 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA10_b; + }; + + union + { + __IOM uint32_t ADDOPCRB10; /*!< (@ 0x000006A8) A/D Conversion Data Operation Control B Register + * 10 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB10_b; + }; + + union + { + __IOM uint32_t ADDOPCRC10; /*!< (@ 0x000006AC) A/D Conversion Data Operation Control C Register + * 10 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC10_b; + }; + + union + { + __IOM uint32_t ADCHCR11; /*!< (@ 0x000006B0) A/D Conversion Channel Configuration Register + * 11 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR11_b; + }; + + union + { + __IOM uint32_t ADDOPCRA11; /*!< (@ 0x000006B4) A/D Conversion Data Operation Control A Register + * 11 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA11_b; + }; + + union + { + __IOM uint32_t ADDOPCRB11; /*!< (@ 0x000006B8) A/D Conversion Data Operation Control B Register + * 11 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB11_b; + }; + + union + { + __IOM uint32_t ADDOPCRC11; /*!< (@ 0x000006BC) A/D Conversion Data Operation Control C Register + * 11 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC11_b; + }; + + union + { + __IOM uint32_t ADCHCR12; /*!< (@ 0x000006C0) A/D Conversion Channel Configuration Register + * 12 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR12_b; + }; + + union + { + __IOM uint32_t ADDOPCRA12; /*!< (@ 0x000006C4) A/D Conversion Data Operation Control A Register + * 12 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA12_b; + }; + + union + { + __IOM uint32_t ADDOPCRB12; /*!< (@ 0x000006C8) A/D Conversion Data Operation Control B Register + * 12 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB12_b; + }; + + union + { + __IOM uint32_t ADDOPCRC12; /*!< (@ 0x000006CC) A/D Conversion Data Operation Control C Register + * 12 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC12_b; + }; + + union + { + __IOM uint32_t ADCHCR13; /*!< (@ 0x000006D0) A/D Conversion Channel Configuration Register + * 13 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR13_b; + }; + + union + { + __IOM uint32_t ADDOPCRA13; /*!< (@ 0x000006D4) A/D Conversion Data Operation Control A Register + * 13 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA13_b; + }; + + union + { + __IOM uint32_t ADDOPCRB13; /*!< (@ 0x000006D8) A/D Conversion Data Operation Control B Register + * 13 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB13_b; + }; + + union + { + __IOM uint32_t ADDOPCRC13; /*!< (@ 0x000006DC) A/D Conversion Data Operation Control C Register + * 13 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC13_b; + }; + + union + { + __IOM uint32_t ADCHCR14; /*!< (@ 0x000006E0) A/D Conversion Channel Configuration Register + * 14 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR14_b; + }; + + union + { + __IOM uint32_t ADDOPCRA14; /*!< (@ 0x000006E4) A/D Conversion Data Operation Control A Register + * 14 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA14_b; + }; + + union + { + __IOM uint32_t ADDOPCRB14; /*!< (@ 0x000006E8) A/D Conversion Data Operation Control B Register + * 14 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB14_b; + }; + + union + { + __IOM uint32_t ADDOPCRC14; /*!< (@ 0x000006EC) A/D Conversion Data Operation Control C Register + * 14 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC14_b; + }; + + union + { + __IOM uint32_t ADCHCR15; /*!< (@ 0x000006F0) A/D Conversion Channel Configuration Register + * 15 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR15_b; + }; + + union + { + __IOM uint32_t ADDOPCRA15; /*!< (@ 0x000006F4) A/D Conversion Data Operation Control A Register + * 15 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA15_b; + }; + + union + { + __IOM uint32_t ADDOPCRB15; /*!< (@ 0x000006F8) A/D Conversion Data Operation Control B Register + * 15 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB15_b; + }; + + union + { + __IOM uint32_t ADDOPCRC15; /*!< (@ 0x000006FC) A/D Conversion Data Operation Control C Register + * 15 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC15_b; + }; + + union + { + __IOM uint32_t ADCHCR16; /*!< (@ 0x00000700) A/D Conversion Channel Configuration Register + * 16 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR16_b; + }; + + union + { + __IOM uint32_t ADDOPCRA16; /*!< (@ 0x00000704) A/D Conversion Data Operation Control A Register + * 16 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA16_b; + }; + + union + { + __IOM uint32_t ADDOPCRB16; /*!< (@ 0x00000708) A/D Conversion Data Operation Control B Register + * 16 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB16_b; + }; + + union + { + __IOM uint32_t ADDOPCRC16; /*!< (@ 0x0000070C) A/D Conversion Data Operation Control C Register + * 16 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC16_b; + }; + + union + { + __IOM uint32_t ADCHCR17; /*!< (@ 0x00000710) A/D Conversion Channel Configuration Register + * 17 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR17_b; + }; + + union + { + __IOM uint32_t ADDOPCRA17; /*!< (@ 0x00000714) A/D Conversion Data Operation Control A Register + * 17 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA17_b; + }; + + union + { + __IOM uint32_t ADDOPCRB17; /*!< (@ 0x00000718) A/D Conversion Data Operation Control B Register + * 17 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB17_b; + }; + + union + { + __IOM uint32_t ADDOPCRC17; /*!< (@ 0x0000071C) A/D Conversion Data Operation Control C Register + * 17 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC17_b; + }; + + union + { + __IOM uint32_t ADCHCR18; /*!< (@ 0x00000720) A/D Conversion Channel Configuration Register + * 18 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR18_b; + }; + + union + { + __IOM uint32_t ADDOPCRA18; /*!< (@ 0x00000724) A/D Conversion Data Operation Control A Register + * 18 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA18_b; + }; + + union + { + __IOM uint32_t ADDOPCRB18; /*!< (@ 0x00000728) A/D Conversion Data Operation Control B Register + * 18 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB18_b; + }; + + union + { + __IOM uint32_t ADDOPCRC18; /*!< (@ 0x0000072C) A/D Conversion Data Operation Control C Register + * 18 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC18_b; + }; + + union + { + __IOM uint32_t ADCHCR19; /*!< (@ 0x00000730) A/D Conversion Channel Configuration Register + * 19 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR19_b; + }; + + union + { + __IOM uint32_t ADDOPCRA19; /*!< (@ 0x00000734) A/D Conversion Data Operation Control A Register + * 19 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA19_b; + }; + + union + { + __IOM uint32_t ADDOPCRB19; /*!< (@ 0x00000738) A/D Conversion Data Operation Control B Register + * 19 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB19_b; + }; + + union + { + __IOM uint32_t ADDOPCRC19; /*!< (@ 0x0000073C) A/D Conversion Data Operation Control C Register + * 19 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC19_b; + }; + + union + { + __IOM uint32_t ADCHCR20; /*!< (@ 0x00000740) A/D Conversion Channel Configuration Register + * 20 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR20_b; + }; + + union + { + __IOM uint32_t ADDOPCRA20; /*!< (@ 0x00000744) A/D Conversion Data Operation Control A Register + * 20 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA20_b; + }; + + union + { + __IOM uint32_t ADDOPCRB20; /*!< (@ 0x00000748) A/D Conversion Data Operation Control B Register + * 20 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB20_b; + }; + + union + { + __IOM uint32_t ADDOPCRC20; /*!< (@ 0x0000074C) A/D Conversion Data Operation Control C Register + * 20 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC20_b; + }; + + union + { + __IOM uint32_t ADCHCR21; /*!< (@ 0x00000750) A/D Conversion Channel Configuration Register + * 21 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR21_b; + }; + + union + { + __IOM uint32_t ADDOPCRA21; /*!< (@ 0x00000754) A/D Conversion Data Operation Control A Register + * 21 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA21_b; + }; + + union + { + __IOM uint32_t ADDOPCRB21; /*!< (@ 0x00000758) A/D Conversion Data Operation Control B Register + * 21 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB21_b; + }; + + union + { + __IOM uint32_t ADDOPCRC21; /*!< (@ 0x0000075C) A/D Conversion Data Operation Control C Register + * 21 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC21_b; + }; + + union + { + __IOM uint32_t ADCHCR22; /*!< (@ 0x00000760) A/D Conversion Channel Configuration Register + * 22 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR22_b; + }; + + union + { + __IOM uint32_t ADDOPCRA22; /*!< (@ 0x00000764) A/D Conversion Data Operation Control A Register + * 22 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA22_b; + }; + + union + { + __IOM uint32_t ADDOPCRB22; /*!< (@ 0x00000768) A/D Conversion Data Operation Control B Register + * 22 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB22_b; + }; + + union + { + __IOM uint32_t ADDOPCRC22; /*!< (@ 0x0000076C) A/D Conversion Data Operation Control C Register + * 22 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC22_b; + }; + + union + { + __IOM uint32_t ADCHCR23; /*!< (@ 0x00000770) A/D Conversion Channel Configuration Register + * 23 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR23_b; + }; + + union + { + __IOM uint32_t ADDOPCRA23; /*!< (@ 0x00000774) A/D Conversion Data Operation Control A Register + * 23 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA23_b; + }; + + union + { + __IOM uint32_t ADDOPCRB23; /*!< (@ 0x00000778) A/D Conversion Data Operation Control B Register + * 23 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB23_b; + }; + + union + { + __IOM uint32_t ADDOPCRC23; /*!< (@ 0x0000077C) A/D Conversion Data Operation Control C Register + * 23 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC23_b; + }; + + union + { + __IOM uint32_t ADCHCR24; /*!< (@ 0x00000780) A/D Conversion Channel Configuration Register + * 24 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR24_b; + }; + + union + { + __IOM uint32_t ADDOPCRA24; /*!< (@ 0x00000784) A/D Conversion Data Operation Control A Register + * 24 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA24_b; + }; + + union + { + __IOM uint32_t ADDOPCRB24; /*!< (@ 0x00000788) A/D Conversion Data Operation Control B Register + * 24 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB24_b; + }; + + union + { + __IOM uint32_t ADDOPCRC24; /*!< (@ 0x0000078C) A/D Conversion Data Operation Control C Register + * 24 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC24_b; + }; + + union + { + __IOM uint32_t ADCHCR25; /*!< (@ 0x00000790) A/D Conversion Channel Configuration Register + * 25 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR25_b; + }; + + union + { + __IOM uint32_t ADDOPCRA25; /*!< (@ 0x00000794) A/D Conversion Data Operation Control A Register + * 25 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA25_b; + }; + + union + { + __IOM uint32_t ADDOPCRB25; /*!< (@ 0x00000798) A/D Conversion Data Operation Control B Register + * 25 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB25_b; + }; + + union + { + __IOM uint32_t ADDOPCRC25; /*!< (@ 0x0000079C) A/D Conversion Data Operation Control C Register + * 25 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC25_b; + }; + + union + { + __IOM uint32_t ADCHCR26; /*!< (@ 0x000007A0) A/D Conversion Channel Configuration Register + * 26 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR26_b; + }; + + union + { + __IOM uint32_t ADDOPCRA26; /*!< (@ 0x000007A4) A/D Conversion Data Operation Control A Register + * 26 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA26_b; + }; + + union + { + __IOM uint32_t ADDOPCRB26; /*!< (@ 0x000007A8) A/D Conversion Data Operation Control B Register + * 26 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB26_b; + }; + + union + { + __IOM uint32_t ADDOPCRC26; /*!< (@ 0x000007AC) A/D Conversion Data Operation Control C Register + * 26 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC26_b; + }; + + union + { + __IOM uint32_t ADCHCR27; /*!< (@ 0x000007B0) A/D Conversion Channel Configuration Register + * 27 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR27_b; + }; + + union + { + __IOM uint32_t ADDOPCRA27; /*!< (@ 0x000007B4) A/D Conversion Data Operation Control A Register + * 27 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA27_b; + }; + + union + { + __IOM uint32_t ADDOPCRB27; /*!< (@ 0x000007B8) A/D Conversion Data Operation Control B Register + * 27 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB27_b; + }; + + union + { + __IOM uint32_t ADDOPCRC27; /*!< (@ 0x000007BC) A/D Conversion Data Operation Control C Register + * 27 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC27_b; + }; + + union + { + __IOM uint32_t ADCHCR28; /*!< (@ 0x000007C0) A/D Conversion Channel Configuration Register + * 28 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR28_b; + }; + + union + { + __IOM uint32_t ADDOPCRA28; /*!< (@ 0x000007C4) A/D Conversion Data Operation Control A Register + * 28 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA28_b; + }; + + union + { + __IOM uint32_t ADDOPCRB28; /*!< (@ 0x000007C8) A/D Conversion Data Operation Control B Register + * 28 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB28_b; + }; + + union + { + __IOM uint32_t ADDOPCRC28; /*!< (@ 0x000007CC) A/D Conversion Data Operation Control C Register + * 28 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC28_b; + }; + + union + { + __IOM uint32_t ADCHCR29; /*!< (@ 0x000007D0) A/D Conversion Channel Configuration Register + * 29 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR29_b; + }; + + union + { + __IOM uint32_t ADDOPCRA29; /*!< (@ 0x000007D4) A/D Conversion Data Operation Control A Register + * 29 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA29_b; + }; + + union + { + __IOM uint32_t ADDOPCRB29; /*!< (@ 0x000007D8) A/D Conversion Data Operation Control B Register + * 29 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB29_b; + }; + + union + { + __IOM uint32_t ADDOPCRC29; /*!< (@ 0x000007DC) A/D Conversion Data Operation Control C Register + * 29 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC29_b; + }; + + union + { + __IOM uint32_t ADCHCR30; /*!< (@ 0x000007E0) A/D Conversion Channel Configuration Register + * 30 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR30_b; + }; + + union + { + __IOM uint32_t ADDOPCRA30; /*!< (@ 0x000007E4) A/D Conversion Data Operation Control A Register + * 30 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA30_b; + }; + + union + { + __IOM uint32_t ADDOPCRB30; /*!< (@ 0x000007E8) A/D Conversion Data Operation Control B Register + * 30 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB30_b; + }; + + union + { + __IOM uint32_t ADDOPCRC30; /*!< (@ 0x000007EC) A/D Conversion Data Operation Control C Register + * 30 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC30_b; + }; + + union + { + __IOM uint32_t ADCHCR31; /*!< (@ 0x000007F0) A/D Conversion Channel Configuration Register + * 31 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR31_b; + }; + + union + { + __IOM uint32_t ADDOPCRA31; /*!< (@ 0x000007F4) A/D Conversion Data Operation Control A Register + * 31 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA31_b; + }; + + union + { + __IOM uint32_t ADDOPCRB31; /*!< (@ 0x000007F8) A/D Conversion Data Operation Control B Register + * 31 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB31_b; + }; + + union + { + __IOM uint32_t ADDOPCRC31; /*!< (@ 0x000007FC) A/D Conversion Data Operation Control C Register + * 31 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC31_b; + }; + + union + { + __IOM uint32_t ADCHCR32; /*!< (@ 0x00000800) A/D Conversion Channel Configuration Register + * 32 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR32_b; + }; + + union + { + __IOM uint32_t ADDOPCRA32; /*!< (@ 0x00000804) A/D Conversion Data Operation Control A Register + * 32 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA32_b; + }; + + union + { + __IOM uint32_t ADDOPCRB32; /*!< (@ 0x00000808) A/D Conversion Data Operation Control B Register + * 32 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB32_b; + }; + + union + { + __IOM uint32_t ADDOPCRC32; /*!< (@ 0x0000080C) A/D Conversion Data Operation Control C Register + * 32 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC32_b; + }; + + union + { + __IOM uint32_t ADCHCR33; /*!< (@ 0x00000810) A/D Conversion Channel Configuration Register + * 33 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR33_b; + }; + + union + { + __IOM uint32_t ADDOPCRA33; /*!< (@ 0x00000814) A/D Conversion Data Operation Control A Register + * 33 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA33_b; + }; + + union + { + __IOM uint32_t ADDOPCRB33; /*!< (@ 0x00000818) A/D Conversion Data Operation Control B Register + * 33 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB33_b; + }; + + union + { + __IOM uint32_t ADDOPCRC33; /*!< (@ 0x0000081C) A/D Conversion Data Operation Control C Register + * 33 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC33_b; + }; + + union + { + __IOM uint32_t ADCHCR34; /*!< (@ 0x00000820) A/D Conversion Channel Configuration Register + * 34 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR34_b; + }; + + union + { + __IOM uint32_t ADDOPCRA34; /*!< (@ 0x00000824) A/D Conversion Data Operation Control A Register + * 34 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA34_b; + }; + + union + { + __IOM uint32_t ADDOPCRB34; /*!< (@ 0x00000828) A/D Conversion Data Operation Control B Register + * 34 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB34_b; + }; + + union + { + __IOM uint32_t ADDOPCRC34; /*!< (@ 0x0000082C) A/D Conversion Data Operation Control C Register + * 34 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC34_b; + }; + + union + { + __IOM uint32_t ADCHCR35; /*!< (@ 0x00000830) A/D Conversion Channel Configuration Register + * 35 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR35_b; + }; + + union + { + __IOM uint32_t ADDOPCRA35; /*!< (@ 0x00000834) A/D Conversion Data Operation Control A Register + * 35 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA35_b; + }; + + union + { + __IOM uint32_t ADDOPCRB35; /*!< (@ 0x00000838) A/D Conversion Data Operation Control B Register + * 35 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB35_b; + }; + + union + { + __IOM uint32_t ADDOPCRC35; /*!< (@ 0x0000083C) A/D Conversion Data Operation Control C Register + * 35 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC35_b; + }; + + union + { + __IOM uint32_t ADCHCR36; /*!< (@ 0x00000840) A/D Conversion Channel Configuration Register + * 36 */ + + struct + { + __IOM uint32_t SGSEL : 5; /*!< [4..0] Scan Group Selection */ + uint32_t : 3; + __IOM uint32_t CNVCS : 7; /*!< [14..8] A/D Conversion Channel Selection */ + __IOM uint32_t AINMD : 1; /*!< [15..15] Analog Input mode selection */ + __IOM uint32_t SSTSEL : 4; /*!< [19..16] Sampling State Table Selection */ + uint32_t : 12; + } ADCHCR36_b; + }; + + union + { + __IOM uint32_t ADDOPCRA36; /*!< (@ 0x00000844) A/D Conversion Data Operation Control A Register + * 36 */ + + struct + { + __IOM uint32_t DFSEL : 3; /*!< [2..0] Digital Filter Table Selection */ + uint32_t : 13; + __IOM uint32_t GAINSEL : 4; /*!< [19..16] User Gain Table Selection */ + uint32_t : 4; + __IOM uint32_t OFSETSEL : 4; /*!< [27..24] User Offset Table Selection */ + uint32_t : 4; + } ADDOPCRA36_b; + }; + + union + { + __IOM uint32_t ADDOPCRB36; /*!< (@ 0x00000848) A/D Conversion Data Operation Control B Register + * 36 */ + + struct + { + __IOM uint32_t AVEMD : 2; /*!< [1..0] Addition/Averaging Mode Selection */ + uint32_t : 6; + __IOM uint32_t ADC : 4; /*!< [11..8] Addition/Averaging Times Selection */ + uint32_t : 4; + __IOM uint32_t CMPTBLEm : 8; /*!< [23..16] Compare Match Enable */ + uint32_t : 8; + } ADDOPCRB36_b; + }; + + union + { + __IOM uint32_t ADDOPCRC36; /*!< (@ 0x0000084C) A/D Conversion Data Operation Control C Register + * 36 */ + + struct + { + __IOM uint32_t LIMTBLS : 4; /*!< [3..0] Limiter Clip Table Selection */ + uint32_t : 12; + __IOM uint32_t ADPRC : 2; /*!< [17..16] A/D Conversion Data Format Selection */ + uint32_t : 2; + __IOM uint32_t SIGNSEL : 1; /*!< [20..20] A/D Conversion Data Sign Selection */ + uint32_t : 11; + } ADDOPCRC36_b; + }; + __IM uint32_t RESERVED29[236]; + + union + { + __OM uint32_t ADCALSTR; /*!< (@ 0x00000C00) A/D Converter Calibration Start Register */ + + struct + { + __OM uint32_t ADCALST0 : 3; /*!< [2..0] A/D Converter Unit 0 (ADC0) Calibration Start Control + * bits */ + uint32_t : 5; + __OM uint32_t ADCALST1 : 3; /*!< [10..8] A/D Converter Unit 1 (ADC1) Calibration Start Control + * bits */ + uint32_t : 21; + } ADCALSTR_b; + }; + __IM uint32_t RESERVED30; + + union + { + __IOM uint32_t ADTRGENR; /*!< (@ 0x00000C08) A/D Conversion Start Trigger Enable Register */ + + struct + { + __IOM uint32_t STTRGENn : 9; /*!< [8..0] Scan Group n A/D Conversion Start Trigger Enable */ + uint32_t : 23; + } ADTRGENR_b; + }; + __IM uint32_t RESERVED31; + + union + { + __OM uint32_t ADSYSTR; /*!< (@ 0x00000C10) A/D Conversion Synchronous Software Start Register */ + + struct + { + __OM uint32_t ADSYSTn : 9; /*!< [8..0] Scan Group n : A/D Conversion start */ + uint32_t : 23; + } ADSYSTR_b; + }; + __IM uint32_t RESERVED32[3]; + + union + { + __OM uint32_t ADSTR[9]; /*!< (@ 0x00000C20) A/D Conversion Software Start Register [0..8] */ + + struct + { + __OM uint32_t ADST : 1; /*!< [0..0] Scan Group n A/D Conversion Start */ + uint32_t : 31; + } ADSTR_b[9]; + }; + __IM uint32_t RESERVED33[7]; + + union + { + __OM uint32_t ADSTOPR; /*!< (@ 0x00000C60) A/D Conversion Stop Register */ + + struct + { + __OM uint32_t ADSTOP0 : 1; /*!< [0..0] A/D Converter Unit 0 Force Stop bit */ + uint32_t : 7; + __OM uint32_t ADSTOP1 : 1; /*!< [8..8] A/D Converter Unit 1 Force Stop bit */ + uint32_t : 23; + } ADSTOPR_b; + }; + __IM uint32_t RESERVED34[7]; + + union + { + __IM uint32_t ADSR; /*!< (@ 0x00000C80) A/D Conversion Status Register */ + + struct + { + __IM uint32_t ADACT0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) A/D Conversion Status */ + __IM uint32_t ADACT1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) A/D Conversion Status */ + uint32_t : 14; + __IM uint32_t CALACT0 : 1; /*!< [16..16] A/D Converter Unit 0 (ADC0) : Calibration Status */ + __IM uint32_t CALACT1 : 1; /*!< [17..17] A/D Converter Unit 1 (ADC1) : Calibration Status */ + uint32_t : 14; + } ADSR_b; + }; + + union + { + __IM uint32_t ADGRSR; /*!< (@ 0x00000C84) Scan Group Status Register */ + + struct + { + __IM uint32_t ACTGRn : 9; /*!< [8..0] Scan Group n Status */ + uint32_t : 23; + } ADGRSR_b; + }; + + union + { + __IM uint32_t ADERSR; /*!< (@ 0x00000C88) A/D Conversion Error Status Register */ + + struct + { + __IM uint32_t ADERF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Error Flag */ + __IM uint32_t ADERF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Error Flag */ + uint32_t : 30; + } ADERSR_b; + }; + + union + { + __OM uint32_t ADERSCR; /*!< (@ 0x00000C8C) A/D Conversion Error Status Clear Register */ + + struct + { + __OM uint32_t ADERCLR0 : 1; /*!< [0..0] A/D Converter Unit 0 Error Flag Clear */ + __OM uint32_t ADERCLR1 : 1; /*!< [1..1] A/D Converter Unit 1 Error Flag Clear */ + uint32_t : 30; + } ADERSCR_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IM uint32_t ADCALENDSR; /*!< (@ 0x00000C98) A/D Converter Calibration End Status Register */ + + struct + { + __IM uint32_t CALENDF0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End flag */ + __IM uint32_t CALENDF1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End flag */ + uint32_t : 30; + } ADCALENDSR_b; + }; + + union + { + __OM uint32_t ADCALENDSCR; /*!< (@ 0x00000C9C) A/D Converter Calibration End Status Clear Register */ + + struct + { + __OM uint32_t CALENDC0 : 1; /*!< [0..0] A/D Converter Unit 0 Calibration End Flag Clear */ + __OM uint32_t CALENDC1 : 1; /*!< [1..1] A/D Converter Unit 1 Calibration End Flag Clear */ + uint32_t : 30; + } ADCALENDSCR_b; + }; + + union + { + __IM uint32_t ADOVFERSR; /*!< (@ 0x00000CA0) A/D Conversion Overflow Error Status Register */ + + struct + { + __IM uint32_t ADOVFEF0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag */ + __IM uint32_t ADOVFEF1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag */ + uint32_t : 30; + } ADOVFERSR_b; + }; + + union + { + __IM uint32_t ADOVFCHSR0; /*!< (@ 0x00000CA4) A/D Conversion Overflow Channel Status Register + * 0 */ + + struct + { + __IM uint32_t OVFCHFn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag */ + uint32_t : 3; + } ADOVFCHSR0_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IM uint32_t ADOVFEXSR; /*!< (@ 0x00000CB0) Extended Analog A/D Conversion Overflow Status + * Register */ + + struct + { + __IM uint32_t OVFEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag bit */ + __IM uint32_t OVFEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag bit */ + __IM uint32_t OVFEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag bit */ + uint32_t : 2; + __IM uint32_t OVFEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag bit */ + __IM uint32_t OVFEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag bit */ + __IM uint32_t OVFEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag bit */ + __IM uint32_t OVFEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag bit */ + uint32_t : 23; + } ADOVFEXSR_b; + }; + + union + { + __OM uint32_t ADOVFERSCR; /*!< (@ 0x00000CB4) A/D Conversion Overflow Error Status Clear Register */ + + struct + { + __OM uint32_t ADOVFEC0 : 1; /*!< [0..0] A/D Converter Unit 0 (ADC0) Overflow Error Flag Clear */ + __OM uint32_t ADOVFEC1 : 1; /*!< [1..1] A/D Converter Unit 1 (ADC1) Overflow Error Flag Clear */ + uint32_t : 30; + } ADOVFERSCR_b; + }; + + union + { + __OM uint32_t ADOVFCHSCR0; /*!< (@ 0x00000CB8) A/D Conversion Overflow Channel Status Clear + * Register 0 */ + + struct + { + __OM uint32_t OVFCHCn : 29; /*!< [28..0] Analog Input Channel No. n : Overflow Flag Clear */ + uint32_t : 3; + } ADOVFCHSCR0_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __OM uint32_t ADOVFEXSCR; /*!< (@ 0x00000CC4) Extended Analog A/D Conversion Overflow Status + * Clear Register */ + + struct + { + __OM uint32_t OVFEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Overflow Flag Clear */ + __OM uint32_t OVFEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Overflow Flag Clear */ + __OM uint32_t OVFEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Overflow Flag Clear */ + uint32_t : 2; + __OM uint32_t OVFEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Overflow Flag Clear */ + __OM uint32_t OVFEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Overflow Flag Clear */ + __OM uint32_t OVFEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Overflow Flag Clear */ + __OM uint32_t OVFEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Overflow Flag Clear */ + uint32_t : 23; + } ADOVFEXSCR_b; + }; + __IM uint32_t RESERVED38[2]; + + union + { + __IM uint32_t ADFIFOSR0; /*!< (@ 0x00000CD0) FIFO Status Register 0 */ + + struct + { + __IM uint32_t FIFOST0 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 0 */ + uint32_t : 12; + __IM uint32_t FIFOST1 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 1 */ + uint32_t : 12; + } ADFIFOSR0_b; + }; + + union + { + __IM uint32_t ADFIFOSR1; /*!< (@ 0x00000CD4) FIFO Status Register 1 */ + + struct + { + __IM uint32_t FIFOST2 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 2 */ + uint32_t : 12; + __IM uint32_t FIFOST3 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 3 */ + uint32_t : 12; + } ADFIFOSR1_b; + }; + + union + { + __IM uint32_t ADFIFOSR2; /*!< (@ 0x00000CD8) FIFO Status Register 2 */ + + struct + { + __IM uint32_t FIFOST4 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 4 */ + uint32_t : 12; + __IM uint32_t FIFOST5 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 5 */ + uint32_t : 12; + } ADFIFOSR2_b; + }; + + union + { + __IM uint32_t ADFIFOSR3; /*!< (@ 0x00000CDC) FIFO Status Register 3 */ + + struct + { + __IM uint32_t FIFOST6 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 6 */ + uint32_t : 12; + __IM uint32_t FIFOST7 : 4; /*!< [19..16] Number of Available Stages in FIFO for Scan Group 7 */ + uint32_t : 12; + } ADFIFOSR3_b; + }; + + union + { + __IM uint32_t ADFIFOSR4; /*!< (@ 0x00000CE0) FIFO Status Register 4 */ + + struct + { + __IM uint32_t FIFOST8 : 4; /*!< [3..0] Number of Available Stages in FIFO for Scan Group 8 */ + uint32_t : 28; + } ADFIFOSR4_b; + }; + __IM uint32_t RESERVED39[3]; + + union + { + __OM uint32_t ADFIFODCR; /*!< (@ 0x00000CF0) FIFO Data Clear Register */ + + struct + { + __OM uint32_t FIFODCn : 9; /*!< [8..0] Scan Group n FIFO Data Clear */ + uint32_t : 23; + } ADFIFODCR_b; + }; + + union + { + __IM uint32_t ADFIFOERSR; /*!< (@ 0x00000CF4) FIFO Error Status Register */ + + struct + { + __IM uint32_t FIFOOVFn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag */ + uint32_t : 7; + __IM uint32_t FIFOFLFn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag */ + uint32_t : 7; + } ADFIFOERSR_b; + }; + + union + { + __OM uint32_t ADFIFOERSCR; /*!< (@ 0x00000CF8) FIFO Error Status Clear Register */ + + struct + { + __OM uint32_t FIFOOVFCn : 9; /*!< [8..0] Scan Group n FIFO Overflow Flag Clear */ + uint32_t : 7; + __OM uint32_t FIFOFLCn : 9; /*!< [24..16] Scan Group n FIFO Data Full Flag Clear */ + uint32_t : 7; + } ADFIFOERSCR_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IM uint32_t ADCMPTBSR; /*!< (@ 0x00000D00) Compare Match Table Status Register */ + + struct + { + __IM uint32_t CMPTBFn : 8; /*!< [7..0] Compare Match Table n Match Flag */ + uint32_t : 24; + } ADCMPTBSR_b; + }; + + union + { + __OM uint32_t ADCMPTBSCR; /*!< (@ 0x00000D04) Compare Match Table Status Clear Register */ + + struct + { + __OM uint32_t CMPTBCn : 8; /*!< [7..0] Compare Match Table n : Match Flag Clear */ + uint32_t : 24; + } ADCMPTBSCR_b; + }; + + union + { + __IM uint32_t ADCMPCHSR0; /*!< (@ 0x00000D08) Compare Match Channel Status Register 0 */ + + struct + { + __IM uint32_t CMPCHFn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag */ + uint32_t : 3; + } ADCMPCHSR0_b; + }; + __IM uint32_t RESERVED41[2]; + + union + { + __IM uint32_t ADCMPEXSR; /*!< (@ 0x00000D14) Extended Analog Compare Match Status Register */ + + struct + { + __IM uint32_t CMPEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag */ + __IM uint32_t CMPEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag */ + __IM uint32_t CMPEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag */ + uint32_t : 2; + __IM uint32_t CMPEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag */ + __IM uint32_t CMPEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag */ + uint32_t : 23; + } ADCMPEXSR_b; + }; + + union + { + __OM uint32_t ADCMPCHSCR0; /*!< (@ 0x00000D18) Compare Match Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t CMPCHCn : 29; /*!< [28..0] Analog Channel No. n : Compare Match Flag Clear bit */ + uint32_t : 3; + } ADCMPCHSCR0_b; + }; + __IM uint32_t RESERVED42[2]; + + union + { + __OM uint32_t ADCMPEXSCR; /*!< (@ 0x00000D24) Extended Analog Compare Match Status Clear Register */ + + struct + { + __OM uint32_t CMPEXC0 : 1; /*!< [0..0] Self-Diagnosis Channel : Compare Match Flag Clear bit */ + __OM uint32_t CMPEXC1 : 1; /*!< [1..1] Temperature Sensor Channel : Compare Match Flag Clear + * bit */ + __OM uint32_t CMPEXC2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Compare Match Flag + * Clear bit */ + uint32_t : 2; + __OM uint32_t CMPEXC5 : 1; /*!< [5..5] D/A Converter 0 Channel : Compare Match Flag Clear bit */ + __OM uint32_t CMPEXC6 : 1; /*!< [6..6] D/A Converter 1 Channel : Compare Match Flag Clear bit */ + __OM uint32_t CMPEXC7 : 1; /*!< [7..7] D/A Converter 2 Channel : Compare Match Flag Clear bit */ + __OM uint32_t CMPEXC8 : 1; /*!< [8..8] D/A Converter 3 Channel : Compare Match Flag Clear bit */ + uint32_t : 23; + } ADCMPEXSCR_b; + }; + + union + { + __IM uint32_t ADLIMGRSR; /*!< (@ 0x00000D28) Limiter Clip Scan Group Status Register */ + + struct + { + __IM uint32_t LIMGRFn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag */ + uint32_t : 23; + } ADLIMGRSR_b; + }; + + union + { + __IM uint32_t ADLIMCHSR0; /*!< (@ 0x00000D2C) Limiter Clip Channel Status Register 0 */ + + struct + { + __IM uint32_t LIMCHFn : 29; /*!< [28..0] Analog Channel No. n : Limiter Clip Flag bit */ + uint32_t : 3; + } ADLIMCHSR0_b; + }; + __IM uint32_t RESERVED43[2]; + + union + { + __IM uint32_t ADLIMEXSR; /*!< (@ 0x00000D38) Extended Analog Limiter Clip Status Register */ + + struct + { + __IM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag bit */ + __IM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag bit */ + __IM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag + * bit */ + uint32_t : 2; + __IM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag bit */ + __IM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag bit */ + __IM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag bit */ + __IM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag bit */ + uint32_t : 23; + } ADLIMEXSR_b; + }; + + union + { + __OM uint32_t ADLIMGRSCR; /*!< (@ 0x00000D3C) Limiter Clip Scan Group Status Clear Register */ + + struct + { + __OM uint32_t LIMGRCn : 9; /*!< [8..0] Scan Group n Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMGRSCR_b; + }; + + union + { + __OM uint32_t ADLIMCHSCR0; /*!< (@ 0x00000D40) Limiter Clip Channel Status Clear Register 0 */ + + struct + { + __OM uint32_t LIMCHCn : 29; /*!< [28..0] Analog Channel No. n Limiter Clip Flag Clear bit */ + uint32_t : 3; + } ADLIMCHSCR0_b; + }; + __IM uint32_t RESERVED44[2]; + + union + { + __OM uint32_t ADLIMEXSCR; /*!< (@ 0x00000D4C) Extended Analog Limiter Clip Status Clear Register */ + + struct + { + __OM uint32_t LIMEXF0 : 1; /*!< [0..0] Self-Diagnosis Channel : Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF1 : 1; /*!< [1..1] Temperature Sensor Channel : Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF2 : 1; /*!< [2..2] Internal Reference Voltage Channel : Limiter Clip Flag + * Clear */ + uint32_t : 2; + __OM uint32_t LIMEXF5 : 1; /*!< [5..5] D/A Converter 0 Channel : Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF6 : 1; /*!< [6..6] D/A Converter 1 Channel : Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF7 : 1; /*!< [7..7] D/A Converter 2 Channel : Limiter Clip Flag Clear */ + __OM uint32_t LIMEXF8 : 1; /*!< [8..8] D/A Converter 3 Channel : Limiter Clip Flag Clear */ + uint32_t : 23; + } ADLIMEXSCR_b; + }; + + union + { + __IM uint32_t ADSCANENDSR; /*!< (@ 0x00000D50) Scan End Status Register */ + + struct + { + __IM uint32_t SCENDFn : 9; /*!< [8..0] Scan Group n Scan End Flag */ + uint32_t : 23; + } ADSCANENDSR_b; + }; + + union + { + __OM uint32_t ADSCANENDSCR; /*!< (@ 0x00000D54) Scan End Status Clear Register */ + + struct + { + __OM uint32_t SCENDCn : 9; /*!< [8..0] Scan Group n Scan End Flag Clear */ + uint32_t : 23; + } ADSCANENDSCR_b; + }; + __IM uint32_t RESERVED45[170]; + + union + { + __IM uint32_t ADDR[29]; /*!< (@ 0x00001000) A/D Data Register [0..28] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 15; + __IM uint32_t ERR : 1; /*!< [31..31] A/D conversion data error status */ + } ADDR_b[29]; + }; + __IM uint32_t RESERVED46[67]; + + union + { + __IM uint32_t ADEXDR[9]; /*!< (@ 0x00001180) A/D Extended Analog Data Register [0..8] */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D conversion data */ + uint32_t : 8; + __IM uint32_t DIAGSR : 3; /*!< [26..24] Self-Diagnosis Status */ + uint32_t : 4; + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Error Status */ + } ADEXDR_b[9]; + }; + __IM uint32_t RESERVED47[23]; + + union + { + __IM uint32_t ADFIFODR0; /*!< (@ 0x00001200) FIFO Data Register 0 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR0_b; + }; + + union + { + __IM uint32_t ADFIFODR1; /*!< (@ 0x00001204) FIFO Data Register 1 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR1_b; + }; + + union + { + __IM uint32_t ADFIFODR2; /*!< (@ 0x00001208) FIFO Data Register 2 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR2_b; + }; + + union + { + __IM uint32_t ADFIFODR3; /*!< (@ 0x0000120C) FIFO Data Register 3 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR3_b; + }; + + union + { + __IM uint32_t ADFIFODR4; /*!< (@ 0x00001210) FIFO Data Register 4 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR4_b; + }; + + union + { + __IM uint32_t ADFIFODR5; /*!< (@ 0x00001214) FIFO Data Register 5 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR5_b; + }; + + union + { + __IM uint32_t ADFIFODR6; /*!< (@ 0x00001218) FIFO Data Register 6 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR6_b; + }; + + union + { + __IM uint32_t ADFIFODR7; /*!< (@ 0x0000121C) FIFO Data Register 7 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR7_b; + }; + + union + { + __IM uint32_t ADFIFODR8; /*!< (@ 0x00001220) FIFO Data Register 8 */ + + struct + { + __IM uint32_t DATA : 16; /*!< [15..0] A/D Conversion Data */ + uint32_t : 8; + __IM uint32_t CH : 7; /*!< [30..24] A/D Conversion Channel Number */ + __IM uint32_t ERR : 1; /*!< [31..31] A/D Conversion Data Error Status */ + } ADFIFODR8_b; + }; +} R_ADC_B0_Type; /*!< Size = 4644 (0x1224) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC_B) + */ + +typedef struct /*!< (@ 0x40109000) R_DOC_B Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + uint8_t : 1; + __IOM uint8_t DOBW : 1; /*!< [3..3] Data Operation Bit Width Select */ + __IOM uint8_t DCSEL : 3; /*!< [6..4] Detection Condition Select */ + __IOM uint8_t DOPCIE : 1; /*!< [7..7] Data Operation Circuit Interrupt Enable */ + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint8_t DOSR; /*!< (@ 0x00000004) DOC Flag Status Register */ + + struct + { + __IM uint8_t DOPCF : 1; /*!< [0..0] Data Operation Circuit Flag */ + uint8_t : 7; + } DOSR_b; + }; + __IM uint8_t RESERVED2; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t DOSCR; /*!< (@ 0x00000008) DOC Flag Status Clear Register */ + + struct + { + __OM uint8_t DOPCFCL : 1; /*!< [0..0] DOPCF Clear */ + uint8_t : 7; + } DOSCR_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + __IOM uint32_t DODIR; /*!< (@ 0x0000000C) DOC Data Input Register */ + __IOM uint32_t DODSR0; /*!< (@ 0x00000010) DOC Data Setting Register 0 */ + __IOM uint32_t DODSR1; /*!< (@ 0x00000014) DOC Data Setting Register 1 */ +} R_DOC_B_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI_B0) + */ + +typedef struct /*!< (@ 0x40118000) R_SCI_B0 Structure */ +{ + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 2; + __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data */ + uint32_t : 19; + } TDR_b; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] Bit Modulation Enable */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty Setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 6; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + + union + { + __IM uint8_t CESR; /*!< (@ 0x0000001C) Communication Enable Status Register */ + + struct + { + __IM uint8_t RIST : 1; /*!< [0..0] RE Internal status */ + uint8_t : 3; + __IM uint8_t TIST : 1; /*!< [4..4] TE Internal status */ + uint8_t : 3; + } CESR_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IIC Interrupt Mode Select */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] Clock Synchronization */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] ACK Transmission Data */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] Start Condition Generation */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] Stop Condition Generation */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] SDA Output Select */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] SCL Output Select */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select bit */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t MCR; /*!< (@ 0x0000002C) Manchester Control Register */ + + struct + { + __IOM uint32_t RMPOL : 1; /*!< [0..0] Polarity of Received Manchester Code */ + __IOM uint32_t TMPOL : 1; /*!< [1..1] Polarity of Transmit Manchester Code */ + __IOM uint32_t ERTEN : 1; /*!< [2..2] Manchester Edge Retiming Enable */ + uint32_t : 1; + __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting */ + __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select */ + __IOM uint32_t SBSEL : 1; /*!< [6..6] Start Bit Select */ + uint32_t : 1; + __IOM uint32_t TPLEN : 4; /*!< [11..8] Transmit preface length */ + __IOM uint32_t TPPAT : 2; /*!< [13..12] Transmit preface pattern */ + uint32_t : 2; + __IOM uint32_t RPLEN : 4; /*!< [19..16] Receive Preface Length */ + __IOM uint32_t RPPAT : 2; /*!< [21..20] Receive Preface Pattern */ + uint32_t : 2; + __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable */ + __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable */ + __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable */ + uint32_t : 5; + } MCR_b; + }; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + + union + { + __IOM uint32_t XCR0; /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0 */ + + struct + { + __IOM uint32_t TCSS : 2; /*!< [1..0] Timer count clock source selection */ + uint32_t : 6; + __IOM uint32_t BFE : 1; /*!< [8..8] Break Field enable */ + __IOM uint32_t CF0RE : 1; /*!< [9..9] Control Field 0 enable */ + __IOM uint32_t CF1DS : 2; /*!< [11..10] Control Field1 compare data select */ + __IOM uint32_t PIBE : 1; /*!< [12..12] Priority interrupt bit enable */ + __IOM uint32_t PIBS : 3; /*!< [15..13] Priority interrupt bit select */ + __IOM uint32_t BFOIE : 1; /*!< [16..16] Break Field output completion interrupt enable */ + __IOM uint32_t BCDIE : 1; /*!< [17..17] Bus conflict detection interrupt enable */ + uint32_t : 2; + __IOM uint32_t BFDIE : 1; /*!< [20..20] Break Field detection interrupt enable */ + __IOM uint32_t COFIE : 1; /*!< [21..21] Counter overflow interrupt enable */ + __IOM uint32_t AEDIE : 1; /*!< [22..22] Active edge detection interrupt enable */ + uint32_t : 1; + __IOM uint32_t BCCS : 2; /*!< [25..24] Bus conflict detection clock selection */ + uint32_t : 6; + } XCR0_b; + }; + + union + { + __IOM uint32_t XCR1; /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1 */ + + struct + { + __IOM uint32_t TCST : 1; /*!< [0..0] Break Field output timer count start trigger */ + uint32_t : 3; + __IOM uint32_t SDST : 1; /*!< [4..4] Start Frame detection enable */ + __IOM uint32_t BMEN : 1; /*!< [5..5] Bit rate measurement enable */ + uint32_t : 2; + __IOM uint32_t PCF1D : 8; /*!< [15..8] Priority compare data for Control Field 1 */ + __IOM uint32_t SCF1D : 8; /*!< [23..16] Secondary compare data for Control Field 1 */ + __IOM uint32_t CF1CE : 8; /*!< [31..24] Control Field 1 compare bit enable */ + } XCR1_b; + }; + + union + { + __IOM uint32_t XCR2; /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2 */ + + struct + { + __IOM uint32_t CF0D : 8; /*!< [7..0] Control Field 0compare data */ + __IOM uint32_t CF0CE : 8; /*!< [15..8] Control Field 0 compare bit enable */ + __IOM uint32_t BFLW : 16; /*!< [31..16] Break Field length setting */ + } XCR2_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor bit */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error Flag */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Flag */ + __IM uint32_t PER : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing Error Flag */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] Transmit End Flag */ + __IM uint32_t RDRF : 1; /*!< [31..31] Receive Data Full Flag */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] Receive Data Ready flag */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive-FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit-FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + + union + { + __IM uint32_t MSR; /*!< (@ 0x00000058) Manchester Status Register */ + + struct + { + __IM uint32_t PFER : 1; /*!< [0..0] Preface Error flag */ + __IM uint32_t SYER : 1; /*!< [1..1] SYNC Error flag */ + __IM uint32_t SBER : 1; /*!< [2..2] Start Bit Error flag */ + uint32_t : 1; + __IM uint32_t MER : 1; /*!< [4..4] Manchester Error Flag */ + uint32_t : 1; + __IM uint32_t RSYNC : 1; /*!< [6..6] Receive SYNC data bit */ + uint32_t : 25; + } MSR_b; + }; + + union + { + __IM uint32_t XSR0; /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0 */ + + struct + { + __IM uint32_t SFSF : 1; /*!< [0..0] Start Frame Status flag */ + __IM uint32_t RXDSF : 1; /*!< [1..1] RXDn input status flag */ + uint32_t : 6; + __IM uint32_t BFOF : 1; /*!< [8..8] Break Field Output completion flag */ + __IM uint32_t BCDF : 1; /*!< [9..9] Bus Conflict detection flag */ + __IM uint32_t BFDF : 1; /*!< [10..10] Break Field detection flag */ + __IM uint32_t CF0MF : 1; /*!< [11..11] Control Field 0 compare match flag */ + __IM uint32_t CF1MF : 1; /*!< [12..12] Control Field 1 compare match flag */ + __IM uint32_t PIBDF : 1; /*!< [13..13] Priority interrupt bit detection flag */ + __IM uint32_t COF : 1; /*!< [14..14] Counter Overflow flag */ + __IM uint32_t AEDF : 1; /*!< [15..15] Active Edge detection flag */ + __IM uint32_t CF0RD : 8; /*!< [23..16] Control Field 0 received data */ + __IM uint32_t CF1RD : 8; /*!< [31..24] Control Field 1 received data */ + } XSR0_b; + }; + + union + { + __IM uint32_t XSR1; /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1 */ + + struct + { + __IM uint32_t TCNT : 16; /*!< [15..0] Timer Count Capture value */ + uint32_t : 16; + } XSR1_b; + }; + __IM uint32_t RESERVED4; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERS clear bit */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMF clear bit */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPER clear bit */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFER clear bit */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORER clear bit */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFF clear bit */ + __OM uint32_t PERC : 1; /*!< [27..27] PER clear bit */ + __OM uint32_t FERC : 1; /*!< [28..28] FER clear bit */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDRE clear bit */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRF clear bit */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DR clear bit */ + uint32_t : 31; + } FFCLR_b; + }; + + union + { + __OM uint32_t MFCLR; /*!< (@ 0x00000074) Manchester Flag Clear Register */ + + struct + { + __OM uint32_t PFERC : 1; /*!< [0..0] PFER clear bit */ + __OM uint32_t SYERC : 1; /*!< [1..1] SYER clear bit */ + __OM uint32_t SBERC : 1; /*!< [2..2] SBER clear bit */ + uint32_t : 1; + __OM uint32_t MERC : 1; /*!< [4..4] MER clear bit */ + uint32_t : 27; + } MFCLR_b; + }; + + union + { + __OM uint32_t XFCLR; /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register */ + + struct + { + uint32_t : 8; + __OM uint32_t BFOC : 1; /*!< [8..8] BFOF clear bit */ + __OM uint32_t BCDC : 1; /*!< [9..9] BCDF clear bit */ + __OM uint32_t BFDC : 1; /*!< [10..10] BFDF clear bit */ + __OM uint32_t CF0MC : 1; /*!< [11..11] CF0MF clear bit */ + __OM uint32_t CF1MC : 1; /*!< [12..12] CF1MF clear bit */ + __OM uint32_t PIBDC : 1; /*!< [13..13] PIBDF clear bit */ + __OM uint32_t COFC : 1; /*!< [14..14] COFF clear bit */ + __OM uint32_t AEDC : 1; /*!< [15..15] AEDF clear bit */ + uint32_t : 16; + } XFCLR_b; + }; +} R_SCI_B0_Type; /*!< Size = 124 (0x7c) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI_B0) + */ + +typedef struct /*!< (@ 0x4011A000) R_SPI_B0 Structure */ +{ + __IOM uint32_t SPDR; /*!< (@ 0x00000000) RSPI Data Register */ + + union + { + __IOM uint32_t SPDECR; /*!< (@ 0x00000004) RSPI Delay Control Register */ + + struct + { + __IOM uint32_t SCKDL : 3; /*!< [2..0] RSPCK Delay */ + uint32_t : 5; + __IOM uint32_t SLNDL : 3; /*!< [10..8] SSL Negation Delay */ + uint32_t : 5; + __IOM uint32_t SPNDL : 3; /*!< [18..16] RSPI Next-Access Delay */ + uint32_t : 5; + __IOM uint32_t ARST : 3; /*!< [26..24] Receive Sampling Timing Adjustment bits */ + uint32_t : 5; + } SPDECR_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) RSPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] RSPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] RSPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] RSPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] RSPI receive data ready error select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] RSPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] RSPI Mode Select */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] RSPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] RSPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint32_t SPCR2; /*!< (@ 0x0000000C) RSPI Control Register 2 */ + + struct + { + __IOM uint32_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint32_t : 1; + __OM uint32_t RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only */ + __OM uint32_t RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only */ + __IOM uint32_t SPDRC : 8; /*!< [15..8] RSPI received data ready detect adjustment */ + __IOM uint32_t SPLP : 1; /*!< [16..16] RSPI Loopback */ + __IOM uint32_t SPLP2 : 1; /*!< [17..17] RSPI Loopback 2 */ + uint32_t : 2; + __IOM uint32_t MOIFV : 1; /*!< [20..20] MOSI Idle Fixed Value */ + __IOM uint32_t MOIFE : 1; /*!< [21..21] MOSI Idle Fixed Value Enable */ + uint32_t : 10; + } SPCR2_b; + }; + + union + { + __IOM uint32_t SPCR3; /*!< (@ 0x00000010) RSPI Control Register 3 */ + + struct + { + __IOM uint32_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity */ + __IOM uint32_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity */ + __IOM uint32_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity */ + __IOM uint32_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity */ + uint32_t : 4; + __IOM uint32_t SPBR : 8; /*!< [15..8] SPI Bit Rate */ + uint32_t : 8; + __IOM uint32_t SPSLN : 3; /*!< [26..24] RSPI Sequence Length */ + uint32_t : 5; + } SPCR3_b; + }; + + union + { + __IOM uint32_t SPCMD0; /*!< (@ 0x00000014) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD0_b; + }; + + union + { + __IOM uint32_t SPCMD1; /*!< (@ 0x00000018) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD1_b; + }; + + union + { + __IOM uint32_t SPCMD2; /*!< (@ 0x0000001C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD2_b; + }; + + union + { + __IOM uint32_t SPCMD3; /*!< (@ 0x00000020) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD3_b; + }; + + union + { + __IOM uint32_t SPCMD4; /*!< (@ 0x00000024) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD4_b; + }; + + union + { + __IOM uint32_t SPCMD5; /*!< (@ 0x00000028) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD5_b; + }; + + union + { + __IOM uint32_t SPCMD6; /*!< (@ 0x0000002C) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD6_b; + }; + + union + { + __IOM uint32_t SPCMD7; /*!< (@ 0x00000030) RSPI Command Register */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] RSPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] RSPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 3; /*!< [26..24] SSL Signal Assertion */ + uint32_t : 5; + } SPCMD7_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SPDCR; /*!< (@ 0x00000040) RSPI Data Control Register */ + + struct + { + __IOM uint32_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + uint32_t : 2; + __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select */ + __IOM uint32_t SINV : 1; /*!< [4..4] Serial data invert bit */ + uint32_t : 3; + __IOM uint32_t SPFC : 2; /*!< [9..8] Frame Count */ + uint32_t : 22; + } SPDCR_b; + }; + + union + { + __IOM uint32_t SPDCR2; /*!< (@ 0x00000044) RSPI Data Control Register 2 */ + + struct + { + __IOM uint32_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint32_t : 6; + __IOM uint32_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint32_t : 22; + } SPDCR2_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t SPSR; /*!< (@ 0x00000050) SPI Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t SPCP : 3; /*!< [10..8] RSPI Command Pointer */ + uint32_t : 1; + __IM uint32_t SPECM : 3; /*!< [14..12] RSPI Error Command */ + uint32_t : 8; + __IM uint32_t SPDRF : 1; /*!< [23..23] RSPI Receive Data Ready Flag */ + __IM uint32_t OVRF : 1; /*!< [24..24] Overrun Error Flag */ + __IM uint32_t IDLNF : 1; /*!< [25..25] RSPI Idle Flag */ + __IM uint32_t MODF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PERF : 1; /*!< [27..27] Parity Error Flag */ + __IM uint32_t UDRF : 1; /*!< [28..28] Underrun Error Flag */ + __IM uint32_t SPTEF : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag */ + __IM uint32_t CENDF : 1; /*!< [30..30] Communication End Flag */ + __IM uint32_t SPRF : 1; /*!< [31..31] RSPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t SPTFSR; /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register */ + + struct + { + __IM uint32_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint32_t : 29; + } SPTFSR_b; + }; + + union + { + __IM uint32_t SPRFSR; /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register */ + + struct + { + __IM uint32_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint32_t : 29; + } SPRFSR_b; + }; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) RSPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] RSPI Poling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t SPSRC; /*!< (@ 0x00000068) RSPI Status Clear Register */ + + struct + { + uint32_t : 23; + __OM uint32_t SPDRFC : 1; /*!< [23..23] RSPI Receive Data Ready Flag Clear */ + __OM uint32_t OVRFC : 1; /*!< [24..24] Overrun Error Flag Clear */ + uint32_t : 1; + __OM uint32_t MODFC : 1; /*!< [26..26] Mode Fault Error Flag Clear */ + __OM uint32_t PERFC : 1; /*!< [27..27] Parity Error Flag Clear */ + __OM uint32_t UDRFC : 1; /*!< [28..28] Underrun Error Flag Clear */ + __OM uint32_t SPTEFC : 1; /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear */ + __OM uint32_t CENDFC : 1; /*!< [30..30] Communication End Flag Clear */ + __OM uint32_t SPRFC : 1; /*!< [31..31] RSPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __IOM uint32_t SPFCR; /*!< (@ 0x0000006C) RSPI FIFO Clear Register */ + + struct + { + __OM uint32_t SPFRST : 1; /*!< [0..0] RSPI FIFO clear */ + uint32_t : 31; + } SPFCR_b; + }; +} R_SPI_B0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Trigonometric Function Unit (TFU) (R_TFU) + */ + +typedef struct /*!< (@ 0x40021000) R_TFU Structure */ +{ + __IM uint32_t RESERVED[2]; + + union + { + __IM uint8_t TRGSTS; /*!< (@ 0x00000008) Trigonometric Status Register */ + + struct + { + __IM uint8_t BSYF : 1; /*!< [0..0] Calculation in progress flag */ + __IM uint8_t ERRF : 1; /*!< [1..1] Input error flag */ + uint8_t : 6; + } TRGSTS_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + __IOM float SCDT0; /*!< (@ 0x00000010) TBD */ + + struct + { + __IOM uint32_t SCDT0 : 32; /*!< [31..0] TBD */ + } SCDT0_b; + }; + + union + { + __IOM float SCDT1; /*!< (@ 0x00000014) TBD */ + + struct + { + __IOM uint32_t SCDT1 : 32; /*!< [31..0] TBD */ + } SCDT1_b; + }; + + union + { + __IOM float ATDT0; /*!< (@ 0x00000018) TBD */ + + struct + { + __IOM uint32_t ATDT0 : 32; /*!< [31..0] TBD */ + } ATDT0_b; + }; + + union + { + __IOM float ATDT1; /*!< (@ 0x0000001C) TBD */ + + struct + { + __IOM uint32_t ATDT1 : 32; /*!< [31..0] TBD */ + } ATDT1_b; + }; +} R_TFU_Type; /*!< Size = 32 (0x20) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_ACMPHS0_BASE 0x400F4000UL + #define R_ACMPHS1_BASE 0x400F4100UL + #define R_ACMPHS2_BASE 0x400F4200UL + #define R_ACMPHS3_BASE 0x400F4300UL + #define R_ACMPHS4_BASE 0x400F4400UL + #define R_ACMPHS5_BASE 0x400F4500UL + #define R_ADC0_BASE 0x40170000UL + #define R_ADC1_BASE 0x40170200UL + #define R_PSCU_BASE 0x400E0000UL + #define R_AGTW0_BASE 0x400E8000UL + #define R_AGTW1_BASE 0x400E8100UL + #define R_BUS_BASE 0x40003000UL + #define R_CAC_BASE 0x40083600UL + #define R_CAN0_BASE 0x400A8000UL + #define R_CAN1_BASE 0x400A9000UL + #define R_CANFD_BASE 0x400B0000UL + #define R_CANFDL_BASE 0x400B0000UL + #define R_CRC_BASE 0x40108000UL + #define R_DAC_BASE 0x40172000UL + #define R_DAC1_BASE 0x40172100UL + #define R_DEBUG_BASE 0x4001B000UL + #define R_DMA_BASE 0x40005200UL + #define R_DMAC0_BASE 0x40005000UL + #define R_DMAC1_BASE 0x40005040UL + #define R_DMAC2_BASE 0x40005080UL + #define R_DMAC3_BASE 0x400050C0UL + #define R_DMAC4_BASE 0x40005100UL + #define R_DMAC5_BASE 0x40005140UL + #define R_DMAC6_BASE 0x40005180UL + #define R_DMAC7_BASE 0x400051C0UL + #define R_DTC_BASE 0x40005400UL + #define R_ELC_BASE 0x40082000UL + #define R_FACI_HP_CMD_BASE 0x407E0000UL + #define R_FACI_HP_BASE 0x407FE000UL + #define R_FCACHE_BASE 0x4001C000UL + #define R_GPT0_BASE 0x40169000UL + #define R_GPT1_BASE 0x40169100UL + #define R_GPT2_BASE 0x40169200UL + #define R_GPT3_BASE 0x40169300UL + #define R_GPT4_BASE 0x40169400UL + #define R_GPT5_BASE 0x40169500UL + #define R_GPT6_BASE 0x40169600UL + #define R_GPT7_BASE 0x40169700UL + #define R_GPT8_BASE 0x40169800UL + #define R_GPT9_BASE 0x40169900UL + #define R_GPT10_BASE 0x40169A00UL + #define R_GPT11_BASE 0x40169B00UL + #define R_GPT12_BASE 0x40169C00UL + #define R_GPT13_BASE 0x40169D00UL + #define R_GPT_GTCLK_BASE 0x40169B00UL + #define R_GPT_ODC_BASE 0x4016A000UL + #define R_GPT_OPS_BASE 0x40169A00UL + #define R_GPT_POEG0_BASE 0x4008A000UL + #define R_GPT_POEG1_BASE 0x4008A100UL + #define R_GPT_POEG2_BASE 0x4008A200UL + #define R_GPT_POEG3_BASE 0x4008A300UL + #define R_ICU_BASE 0x40006000UL + #define R_IIC0_BASE 0x4009F000UL + #define R_IIC1_BASE 0x4009F100UL + #define R_IIC2_BASE 0x4009F200UL + #define R_IIRFA_BASE 0x40020000UL + #define R_IWDT_BASE 0x40083200UL + #define R_KINT_BASE 0x40085000UL + #define R_I3C0_BASE 0x4011F000UL + #define R_I3C1_BASE 0x4011F400UL + #define R_MPU_SPMON_BASE 0x40000D00UL + #define R_MSTP_BASE 0x40084000UL + #define R_PORT0_BASE 0x4001F000UL + #define R_PORT1_BASE 0x4001F020UL + #define R_PORT2_BASE 0x4001F040UL + #define R_PORT3_BASE 0x40080060UL + #define R_PORT4_BASE 0x40080080UL + #define R_PORT5_BASE 0x400800A0UL + #define R_PORT6_BASE 0x400800C0UL + #define R_PORT7_BASE 0x400800E0UL + #define R_PORT8_BASE 0x40080100UL + #define R_PORT9_BASE 0x40080120UL + #define R_PORT10_BASE 0x4001F140UL + #define R_PORT11_BASE 0x4001F160UL + #define R_PORT12_BASE 0x4001F180UL + #define R_PORT13_BASE 0x4001F1A0UL + #define R_PORT14_BASE 0x4001F1C0UL + #define R_PFS_BASE 0x4001F800UL + #define R_PMISC_BASE 0x4001FD00UL + #define R_SCI0_BASE 0x40118000UL + #define R_SCI1_BASE 0x40118100UL + #define R_SCI2_BASE 0x40118200UL + #define R_SCI3_BASE 0x40118300UL + #define R_SCI4_BASE 0x40118400UL + #define R_SCI5_BASE 0x40118500UL + #define R_SCI6_BASE 0x40118600UL + #define R_SCI7_BASE 0x40118700UL + #define R_SCI8_BASE 0x40118800UL + #define R_SCI9_BASE 0x40118900UL + #define R_SPI0_BASE 0x4011A000UL + #define R_SPI1_BASE 0x4011A100UL + #define R_SRAM_BASE 0x40002000UL + #define R_SYSTEM_BASE 0x4001E000UL + #define R_TSN_CAL_BASE 0x407FB17CUL + #define R_TSN_CTRL_BASE 0x400F3000UL + #define R_WDT_BASE 0x40083400UL + #define R_TZF_BASE 0x40000E00UL + #define R_CACHE_BASE 0x40007000UL + #define R_CPSCU_BASE 0x40008000UL + #define R_ADC_B0_BASE 0x40170000UL + #define R_DOC_B_BASE 0x40109000UL + #define R_SCI_B0_BASE 0x40118000UL + #define R_SCI_B1_BASE 0x40118100UL + #define R_SCI_B2_BASE 0x40118200UL + #define R_SCI_B3_BASE 0x40118300UL + #define R_SCI_B4_BASE 0x40118400UL + #define R_SCI_B9_BASE 0x40118900UL + #define R_SPI_B0_BASE 0x4011A000UL + #define R_SPI_B1_BASE 0x4011A100UL + #define R_TFU_BASE 0x40021000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_ACMPHS0 ((R_ACMPHS0_Type *) R_ACMPHS0_BASE) + #define R_ACMPHS1 ((R_ACMPHS0_Type *) R_ACMPHS1_BASE) + #define R_ACMPHS2 ((R_ACMPHS0_Type *) R_ACMPHS2_BASE) + #define R_ACMPHS3 ((R_ACMPHS0_Type *) R_ACMPHS3_BASE) + #define R_ACMPHS4 ((R_ACMPHS0_Type *) R_ACMPHS4_BASE) + #define R_ACMPHS5 ((R_ACMPHS0_Type *) R_ACMPHS5_BASE) + #define R_ADC0 ((R_ADC0_Type *) R_ADC0_BASE) + #define R_ADC1 ((R_ADC0_Type *) R_ADC1_BASE) + #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) + #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE) + #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE) + #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + #define R_CAC ((R_CAC_Type *) R_CAC_BASE) + #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) + #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) + #define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE) + #define R_CANFDL ((R_CANFDL_Type *) R_CANFDL_BASE) + #define R_CRC ((R_CRC_Type *) R_CRC_BASE) + #define R_DAC0 ((R_DAC_Type *) R_DAC_BASE) + #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) + #define R_DEBUG ((R_DEBUG_Type *) R_DEBUG_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_DMAC2 ((R_DMAC0_Type *) R_DMAC2_BASE) + #define R_DMAC3 ((R_DMAC0_Type *) R_DMAC3_BASE) + #define R_DMAC4 ((R_DMAC0_Type *) R_DMAC4_BASE) + #define R_DMAC5 ((R_DMAC0_Type *) R_DMAC5_BASE) + #define R_DMAC6 ((R_DMAC0_Type *) R_DMAC6_BASE) + #define R_DMAC7 ((R_DMAC0_Type *) R_DMAC7_BASE) + #define R_DTC ((R_DTC_Type *) R_DTC_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_FACI_HP_CMD ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE) + #define R_FACI_HP ((R_FACI_HP_Type *) R_FACI_HP_BASE) + #define R_FCACHE ((R_FCACHE_Type *) R_FCACHE_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_GPT_GTCLK ((R_GPT_GTCLK_Type *) R_GPT_GTCLK_BASE) + #define R_GPT_ODC ((R_GPT_ODC_Type *) R_GPT_ODC_BASE) + #define R_GPT_OPS ((R_GPT_OPS_Type *) R_GPT_OPS_BASE) + #define R_GPT_POEG0 ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE) + #define R_GPT_POEG1 ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE) + #define R_GPT_POEG2 ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE) + #define R_GPT_POEG3 ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_IIRFA ((R_IIRFA_Type *) R_IIRFA_BASE) + #define R_IWDT ((R_IWDT_Type *) R_IWDT_BASE) + #define R_KINT ((R_KINT_Type *) R_KINT_BASE) + #define R_I3C0 ((R_I3C0_Type *) R_I3C0_BASE) + #define R_I3C1 ((R_I3C0_Type *) R_I3C1_BASE) + #define R_MPU_SPMON ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE) + #define R_MSTP ((R_MSTP_Type *) R_MSTP_BASE) + #define R_PORT0 ((R_PORT0_Type *) R_PORT0_BASE) + #define R_PORT1 ((R_PORT0_Type *) R_PORT1_BASE) + #define R_PORT2 ((R_PORT0_Type *) R_PORT2_BASE) + #define R_PORT3 ((R_PORT0_Type *) R_PORT3_BASE) + #define R_PORT4 ((R_PORT0_Type *) R_PORT4_BASE) + #define R_PORT5 ((R_PORT0_Type *) R_PORT5_BASE) + #define R_PORT6 ((R_PORT0_Type *) R_PORT6_BASE) + #define R_PORT7 ((R_PORT0_Type *) R_PORT7_BASE) + #define R_PORT8 ((R_PORT0_Type *) R_PORT8_BASE) + #define R_PORT9 ((R_PORT0_Type *) R_PORT9_BASE) + #define R_PORT10 ((R_PORT0_Type *) R_PORT10_BASE) + #define R_PORT11 ((R_PORT0_Type *) R_PORT11_BASE) + #define R_PORT12 ((R_PORT0_Type *) R_PORT12_BASE) + #define R_PORT13 ((R_PORT0_Type *) R_PORT13_BASE) + #define R_PORT14 ((R_PORT0_Type *) R_PORT14_BASE) + #define R_PFS ((R_PFS_Type *) R_PFS_BASE) + #define R_PMISC ((R_PMISC_Type *) R_PMISC_BASE) + #define R_SCI0 ((R_SCI_B0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI_B0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI_B0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI_B0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI_B0_Type *) R_SCI4_BASE) + #define R_SCI5 ((R_SCI_B0_Type *) R_SCI5_BASE) + #define R_SCI6 ((R_SCI_B0_Type *) R_SCI6_BASE) + #define R_SCI7 ((R_SCI_B0_Type *) R_SCI7_BASE) + #define R_SCI8 ((R_SCI_B0_Type *) R_SCI8_BASE) + #define R_SCI9 ((R_SCI_B0_Type *) R_SCI9_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) + #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) + #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) + #define R_WDT ((R_WDT_Type *) R_WDT_BASE) + #define R_TZF ((R_TZF_Type *) R_TZF_BASE) + #define R_CACHE ((R_CACHE_Type *) R_CACHE_BASE) + #define R_CPSCU ((R_CPSCU_Type *) R_CPSCU_BASE) + #define R_ADC_B ((R_ADC_B0_Type *) R_ADC_B0_BASE) + #define R_DOC_B ((R_DOC_B_Type *) R_DOC_B_BASE) + #define R_SCI_B0 ((R_SCI_B0_Type *) R_SCI_B0_BASE) + #define R_SCI_B1 ((R_SCI_B0_Type *) R_SCI_B1_BASE) + #define R_SCI_B2 ((R_SCI_B0_Type *) R_SCI_B2_BASE) + #define R_SCI_B3 ((R_SCI_B0_Type *) R_SCI_B3_BASE) + #define R_SCI_B4 ((R_SCI_B0_Type *) R_SCI_B4_BASE) + #define R_SCI_B9 ((R_SCI_B0_Type *) R_SCI_B9_BASE) + #define R_SPI_B0 ((R_SPI_B0_Type *) R_SPI_B0_BASE) + #define R_SPI_B1 ((R_SPI_B0_Type *) R_SPI_B1_BASE) + #define R_TFU ((R_TFU_Type *) R_TFU_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ SDRAM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SDCCR ========================================================= */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_SDRAM_SDCCR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_SDRAM_SDCCR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCMOD ========================================================= */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Pos (0UL) /*!< EMODE (Bit 0) */ + #define R_BUS_SDRAM_SDCMOD_EMODE_Msk (0x1UL) /*!< EMODE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDAMOD ========================================================= */ + #define R_BUS_SDRAM_SDAMOD_BE_Pos (0UL) /*!< BE (Bit 0) */ + #define R_BUS_SDRAM_SDAMOD_BE_Msk (0x1UL) /*!< BE (Bitfield-Mask: 0x01) */ +/* ======================================================== SDSELF ========================================================= */ + #define R_BUS_SDRAM_SDSELF_SFEN_Pos (0UL) /*!< SFEN (Bit 0) */ + #define R_BUS_SDRAM_SDSELF_SFEN_Msk (0x1UL) /*!< SFEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDRFCR ========================================================= */ + #define R_BUS_SDRAM_SDRFCR_REFW_Pos (12UL) /*!< REFW (Bit 12) */ + #define R_BUS_SDRAM_SDRFCR_REFW_Msk (0xf000UL) /*!< REFW (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Pos (0UL) /*!< RFC (Bit 0) */ + #define R_BUS_SDRAM_SDRFCR_RFC_Msk (0xfffUL) /*!< RFC (Bitfield-Mask: 0xfff) */ +/* ======================================================== SDRFEN ========================================================= */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Pos (0UL) /*!< RFEN (Bit 0) */ + #define R_BUS_SDRAM_SDRFEN_RFEN_Msk (0x1UL) /*!< RFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SDICR ========================================================= */ + #define R_BUS_SDRAM_SDICR_INIRQ_Pos (0UL) /*!< INIRQ (Bit 0) */ + #define R_BUS_SDRAM_SDICR_INIRQ_Msk (0x1UL) /*!< INIRQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SDIR ========================================================== */ + #define R_BUS_SDRAM_SDIR_PRC_Pos (8UL) /*!< PRC (Bit 8) */ + #define R_BUS_SDRAM_SDIR_PRC_Msk (0x700UL) /*!< PRC (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDIR_ARFC_Pos (4UL) /*!< ARFC (Bit 4) */ + #define R_BUS_SDRAM_SDIR_ARFC_Msk (0xf0UL) /*!< ARFC (Bitfield-Mask: 0x0f) */ + #define R_BUS_SDRAM_SDIR_ARFI_Pos (0UL) /*!< ARFI (Bit 0) */ + #define R_BUS_SDRAM_SDIR_ARFI_Msk (0xfUL) /*!< ARFI (Bitfield-Mask: 0x0f) */ +/* ========================================================= SDADR ========================================================= */ + #define R_BUS_SDRAM_SDADR_MXC_Pos (0UL) /*!< MXC (Bit 0) */ + #define R_BUS_SDRAM_SDADR_MXC_Msk (0x3UL) /*!< MXC (Bitfield-Mask: 0x03) */ +/* ========================================================= SDTR ========================================================== */ + #define R_BUS_SDRAM_SDTR_RAS_Pos (16UL) /*!< RAS (Bit 16) */ + #define R_BUS_SDRAM_SDTR_RAS_Msk (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_RCD_Pos (12UL) /*!< RCD (Bit 12) */ + #define R_BUS_SDRAM_SDTR_RCD_Msk (0x3000UL) /*!< RCD (Bitfield-Mask: 0x03) */ + #define R_BUS_SDRAM_SDTR_RP_Pos (9UL) /*!< RP (Bit 9) */ + #define R_BUS_SDRAM_SDTR_RP_Msk (0xe00UL) /*!< RP (Bitfield-Mask: 0x07) */ + #define R_BUS_SDRAM_SDTR_WR_Pos (8UL) /*!< WR (Bit 8) */ + #define R_BUS_SDRAM_SDTR_WR_Msk (0x100UL) /*!< WR (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDTR_CL_Pos (0UL) /*!< CL (Bit 0) */ + #define R_BUS_SDRAM_SDTR_CL_Msk (0x7UL) /*!< CL (Bitfield-Mask: 0x07) */ +/* ========================================================= SDMOD ========================================================= */ + #define R_BUS_SDRAM_SDMOD_MR_Pos (0UL) /*!< MR (Bit 0) */ + #define R_BUS_SDRAM_SDMOD_MR_Msk (0x7fffUL) /*!< MR (Bitfield-Mask: 0x7fff) */ +/* ========================================================= SDSR ========================================================== */ + #define R_BUS_SDRAM_SDSR_SRFST_Pos (4UL) /*!< SRFST (Bit 4) */ + #define R_BUS_SDRAM_SDSR_SRFST_Msk (0x10UL) /*!< SRFST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_INIST_Pos (3UL) /*!< INIST (Bit 3) */ + #define R_BUS_SDRAM_SDSR_INIST_Msk (0x8UL) /*!< INIST (Bitfield-Mask: 0x01) */ + #define R_BUS_SDRAM_SDSR_MRSST_Pos (0UL) /*!< MRSST (Bit 0) */ + #define R_BUS_SDRAM_SDSR_MRSST_Msk (0x1UL) /*!< MRSST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT ========================================================== */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Pos (7UL) /*!< ERRSTAT (Bit 7) */ + #define R_BUS_BUSERR_STAT_ERRSTAT_Msk (0x80UL) /*!< ERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Pos (0UL) /*!< ACCSTAT (Bit 0) */ + #define R_BUS_BUSERR_STAT_ACCSTAT_Msk (0x1UL) /*!< ACCSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSM_CNT_IERES_Pos (15UL) /*!< IERES (Bit 15) */ + #define R_BUS_BUSM_CNT_IERES_Msk (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CNT ========================================================== */ + #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ + #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ MB ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================== DL =========================================================== */ + #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ + #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ +/* =========================================================== D =========================================================== */ + #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ +/* ========================================================== TS =========================================================== */ + #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ + #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ + #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ + #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ + #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ + #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ + #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFD_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFDL_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFDL_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFDL_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFDL_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFDL_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFDL_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFDL_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFDL_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFDL_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFDL_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFDL_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFDL_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFDL_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFDL_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFDL_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFDL_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFDL_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFDL_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFDL_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFDL_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFDL_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFDL_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFDL_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFDL_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFDL_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFDL_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFDL_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFDL_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFDL_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFDL_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFDL_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFDL_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFDL_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFDL_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFDL_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFDL_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFDL_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFDL_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFDL_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFDL_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFDL_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFDL_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFDL_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFDL_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFDL_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFDL_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFDL_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFDL_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFDL_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFDL_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFDL_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFDL_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFDL_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFDL_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFDL_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFDL_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFDL_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFDL_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFDL_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFDL_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFDL_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFDL_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFDL_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFDL_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFDL_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFDL_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFDL_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFDL_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFDL_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFDL_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFDL_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFDL_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFDL_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFDL_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFDL_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFDL_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFDL_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFDL_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFDL_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFDL_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFDL_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFDL_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ + #define R_CANFDL_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFDL_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFDL_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFDL_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFDL_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFDL_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFDL_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFDL_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFDL_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFDL_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFDL_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFDL_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFDL_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFDL_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFDL_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFDL_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFDL_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFDL_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFDL_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFDL_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFDL_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFDL_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFDL_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFDL_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFDL_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFDL_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFDL_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFDL_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ + #define R_CANFDL_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFDL_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFDL_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFDL_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFDL_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFDL_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFDL_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFDL_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFDL_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFDL_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFDL_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFDL_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFDL_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFDL_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFDL_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFDL_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFDL_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFDL_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFDL_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFDL_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFDL_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFDL_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFDL_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFDL_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ + #define R_CANFDL_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFDL_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFDL_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFDL_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFDL_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFDL_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFDL_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFDL_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFDL_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFDL_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFDL_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ RM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFDL_CFDRMC_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFDL_CFDRMC_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFDL_CFDRMC_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFDL_CFDRMC_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRMC ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ ELSEGR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_ELC_ELSEGR_BY_WI_Pos (7UL) /*!< WI (Bit 7) */ + #define R_ELC_ELSEGR_BY_WI_Msk (0x80UL) /*!< WI (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_WE_Pos (6UL) /*!< WE (Bit 6) */ + #define R_ELC_ELSEGR_BY_WE_Msk (0x40UL) /*!< WE (Bitfield-Mask: 0x01) */ + #define R_ELC_ELSEGR_BY_SEG_Pos (0UL) /*!< SEG (Bit 0) */ + #define R_ELC_ELSEGR_BY_SEG_Msk (0x1UL) /*!< SEG (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELSR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== HA =========================================================== */ + #define R_ELC_ELSR_HA_ELS_Pos (0UL) /*!< ELS (Bit 0) */ + #define R_ELC_ELSR_HA_ELS_Msk (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ GTDLYR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== A =========================================================== */ + #define R_GPT_ODC_GTDLYR_A_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_A_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ +/* =========================================================== B =========================================================== */ + #define R_GPT_ODC_GTDLYR_B_DLY_Pos (0UL) /*!< DLY (Bit 0) */ + #define R_GPT_ODC_GTDLYR_B_DLY_Msk (0x1fUL) /*!< DLY (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA_Pos (0UL) /*!< SVA (Bit 0) */ + #define R_IIC0_SAR_L_SVA_Msk (0xffUL) /*!< SVA (Bitfield-Mask: 0xff) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_SVA9_Pos (2UL) /*!< SVA9 (Bit 2) */ + #define R_IIC0_SAR_U_SVA9_Msk (0x4UL) /*!< SVA9 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA8_Pos (1UL) /*!< SVA8 (Bit 1) */ + #define R_IIC0_SAR_U_SVA8_Msk (0x2UL) /*!< SVA8 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IIRCH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== INP ========================================================== */ +/* ========================================================== OUT ========================================================== */ +/* ========================================================== CNT ========================================================== */ + #define R_IIRFA_IIRCH_CNT_STGSEL_Pos (0UL) /*!< STGSEL (Bit 0) */ + #define R_IIRFA_IIRCH_CNT_STGSEL_Msk (0xffffffffUL) /*!< STGSEL (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== INT ========================================================== */ + #define R_IIRFA_IIRCH_INT_CPRCFIE_Pos (1UL) /*!< CPRCFIE (Bit 1) */ + #define R_IIRFA_IIRCH_INT_CPRCFIE_Msk (0x2UL) /*!< CPRCFIE (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_INT_ORDYIE_Pos (2UL) /*!< ORDYIE (Bit 2) */ + #define R_IIRFA_IIRCH_INT_ORDYIE_Msk (0x4UL) /*!< ORDYIE (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_INT_CERRIE_Pos (3UL) /*!< CERRIE (Bit 3) */ + #define R_IIRFA_IIRCH_INT_CERRIE_Msk (0x8UL) /*!< CERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_IIRFA_IIRCH_STS_CPRCS_Pos (0UL) /*!< CPRCS (Bit 0) */ + #define R_IIRFA_IIRCH_STS_CPRCS_Msk (0x1UL) /*!< CPRCS (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_STS_CPRCFF_Pos (1UL) /*!< CPRCFF (Bit 1) */ + #define R_IIRFA_IIRCH_STS_CPRCFF_Msk (0x2UL) /*!< CPRCFF (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_STS_ORDYF_Pos (2UL) /*!< ORDYF (Bit 2) */ + #define R_IIRFA_IIRCH_STS_ORDYF_Msk (0x4UL) /*!< ORDYF (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_STS_CERRF_Pos (3UL) /*!< CERRF (Bit 3) */ + #define R_IIRFA_IIRCH_STS_CERRF_Msk (0x8UL) /*!< CERRF (Bitfield-Mask: 0x01) */ +/* ========================================================= FCLR ========================================================== */ + #define R_IIRFA_IIRCH_FCLR_CPRCFFCLR_Pos (1UL) /*!< CPRCFFCLR (Bit 1) */ + #define R_IIRFA_IIRCH_FCLR_CPRCFFCLR_Msk (0x2UL) /*!< CPRCFFCLR (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRCH_FCLR_CERRFCLR_Pos (3UL) /*!< CERRFCLR (Bit 3) */ + #define R_IIRFA_IIRCH_FCLR_CERRFCLR_Msk (0x8UL) /*!< CERRFCLR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ IIRSTG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== B0 =========================================================== */ +/* ========================================================== B1 =========================================================== */ +/* ========================================================== B2 =========================================================== */ +/* ========================================================== A1 =========================================================== */ +/* ========================================================== A2 =========================================================== */ +/* ========================================================== D0 =========================================================== */ +/* ========================================================== D1 =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ SP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== OAD ========================================================== */ + #define R_MPU_SPMON_SP_OAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_OAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_OAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_MPU_SPMON_SP_OAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ + #define R_MPU_SPMON_SP_CTL_ERROR_Pos (8UL) /*!< ERROR (Bit 8) */ + #define R_MPU_SPMON_SP_CTL_ERROR_Msk (0x100UL) /*!< ERROR (Bitfield-Mask: 0x01) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_MPU_SPMON_SP_CTL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ========================================================== PT =========================================================== */ + #define R_MPU_SPMON_SP_PT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_MPU_SPMON_SP_PT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_MPU_SPMON_SP_PT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ========================================================== SA =========================================================== */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos (0UL) /*!< MSPMPUSA (Bit 0) */ + #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== EA =========================================================== */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos (0UL) /*!< MSPMPUEA (Bit 0) */ + #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ PIN ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PmnPFS_BY ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ======================================================= PmnPFS_HA ======================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ +/* ======================================================== PmnPFS ========================================================= */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos (6UL) /*!< NCODR (Bit 6) */ + #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk (0x40UL) /*!< NCODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos (5UL) /*!< PIM (Bit 5) */ + #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk (0x20UL) /*!< PIM (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos (4UL) /*!< PCR (Bit 4) */ + #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk (0x10UL) /*!< PCR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos (2UL) /*!< PDR (Bit 2) */ + #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk (0x4UL) /*!< PDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos (1UL) /*!< PIDR (Bit 1) */ + #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk (0x2UL) /*!< PIDR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos (15UL) /*!< ASEL (Bit 15) */ + #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk (0x8000UL) /*!< ASEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos (14UL) /*!< ISEL (Bit 14) */ + #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk (0x4000UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos (12UL) /*!< EOFR (Bit 12) */ + #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk (0x3000UL) /*!< EOFR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos (10UL) /*!< DSCR (Bit 10) */ + #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk (0xc00UL) /*!< DSCR (Bitfield-Mask: 0x03) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos (24UL) /*!< PSEL (Bit 24) */ + #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos (16UL) /*!< PMR (Bit 16) */ + #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk (0x10000UL) /*!< PMR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PORT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ PMSAR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PMSAR ========================================================= */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_ACMPHS0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMPCTL ========================================================= */ + #define R_ACMPHS0_CMPCTL_HCMPON_Pos (7UL) /*!< HCMPON (Bit 7) */ + #define R_ACMPHS0_CMPCTL_HCMPON_Msk (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CDFS_Pos (5UL) /*!< CDFS (Bit 5) */ + #define R_ACMPHS0_CMPCTL_CDFS_Msk (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CEG_Pos (3UL) /*!< CEG (Bit 3) */ + #define R_ACMPHS0_CMPCTL_CEG_Msk (0x18UL) /*!< CEG (Bitfield-Mask: 0x03) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Pos (2UL) /*!< CSTEN (Bit 2) */ + #define R_ACMPHS0_CMPCTL_CSTEN_Msk (0x4UL) /*!< CSTEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_COE_Pos (1UL) /*!< COE (Bit 1) */ + #define R_ACMPHS0_CMPCTL_COE_Msk (0x2UL) /*!< COE (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CMPCTL_CINV_Pos (0UL) /*!< CINV (Bit 0) */ + #define R_ACMPHS0_CMPCTL_CINV_Msk (0x1UL) /*!< CINV (Bitfield-Mask: 0x01) */ +/* ======================================================== CMPSEL0 ======================================================== */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos (0UL) /*!< CMPSEL (Bit 0) */ + #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk (0xfUL) /*!< CMPSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== CMPSEL1 ======================================================== */ + #define R_ACMPHS0_CMPSEL1_CRVS_Pos (0UL) /*!< CRVS (Bit 0) */ + #define R_ACMPHS0_CMPSEL1_CRVS_Msk (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f) */ +/* ======================================================== CMPMON ========================================================= */ + #define R_ACMPHS0_CMPMON_CMPMON_Pos (0UL) /*!< CMPMON (Bit 0) */ + #define R_ACMPHS0_CMPMON_CMPMON_Msk (0x1UL) /*!< CMPMON (Bitfield-Mask: 0x01) */ +/* ========================================================= CPIOC ========================================================= */ + #define R_ACMPHS0_CPIOC_VREFEN_Pos (7UL) /*!< VREFEN (Bit 7) */ + #define R_ACMPHS0_CPIOC_VREFEN_Msk (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01) */ + #define R_ACMPHS0_CPIOC_CPOE_Pos (0UL) /*!< CPOE (Bit 0) */ + #define R_ACMPHS0_CPIOC_CPOE_Msk (0x1UL) /*!< CPOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC0_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC0_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC0_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCSR_ADHSC_Pos (10UL) /*!< ADHSC (Bit 10) */ + #define R_ADC0_ADCSR_ADHSC_Msk (0x400UL) /*!< ADHSC (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC0_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC0_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC0_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC0_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC0_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC0_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA ========================================================= */ + #define R_ADC0_ADANSA_ANSA_Pos (0UL) /*!< ANSA (Bit 0) */ + #define R_ADC0_ADANSA_ANSA_Msk (0x1UL) /*!< ANSA (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADS ========================================================= */ + #define R_ADC0_ADADS_ADS_Pos (0UL) /*!< ADS (Bit 0) */ + #define R_ADC0_ADADS_ADS_Msk (0x1UL) /*!< ADS (Bitfield-Mask: 0x01) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC0_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC0_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC0_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC0_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC0_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADINV_Pos (14UL) /*!< ADINV (Bit 14) */ + #define R_ADC0_ADCER_ADINV_Msk (0x4000UL) /*!< ADINV (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGM_Pos (11UL) /*!< DIAGM (Bit 11) */ + #define R_ADC0_ADCER_DIAGM_Msk (0x800UL) /*!< DIAGM (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGLD_Pos (10UL) /*!< DIAGLD (Bit 10) */ + #define R_ADC0_ADCER_DIAGLD_Msk (0x400UL) /*!< DIAGLD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_DIAGVAL_Pos (8UL) /*!< DIAGVAL (Bit 8) */ + #define R_ADC0_ADCER_DIAGVAL_Msk (0x300UL) /*!< DIAGVAL (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC0_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC0_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADCER_DCE_Pos (4UL) /*!< DCE (Bit 4) */ + #define R_ADC0_ADCER_DCE_Msk (0x10UL) /*!< DCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC0_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC0_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ + #define R_ADC0_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC0_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADEXICR ======================================================== */ + #define R_ADC0_ADEXICR_OCSB_Pos (11UL) /*!< OCSB (Bit 11) */ + #define R_ADC0_ADEXICR_OCSB_Msk (0x800UL) /*!< OCSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSB_Pos (10UL) /*!< TSSB (Bit 10) */ + #define R_ADC0_ADEXICR_TSSB_Msk (0x400UL) /*!< TSSB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSA_Pos (9UL) /*!< OCSA (Bit 9) */ + #define R_ADC0_ADEXICR_OCSA_Msk (0x200UL) /*!< OCSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSA_Pos (8UL) /*!< TSSA (Bit 8) */ + #define R_ADC0_ADEXICR_TSSA_Msk (0x100UL) /*!< TSSA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_OCSAD_Pos (1UL) /*!< OCSAD (Bit 1) */ + #define R_ADC0_ADEXICR_OCSAD_Msk (0x2UL) /*!< OCSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_TSSAD_Pos (0UL) /*!< TSSAD (Bit 0) */ + #define R_ADC0_ADEXICR_TSSAD_Msk (0x1UL) /*!< TSSAD (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXSEL_Pos (14UL) /*!< EXSEL (Bit 14) */ + #define R_ADC0_ADEXICR_EXSEL_Msk (0x4000UL) /*!< EXSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXICR_EXOEN_Pos (15UL) /*!< EXOEN (Bit 15) */ + #define R_ADC0_ADEXICR_EXOEN_Msk (0x8000UL) /*!< EXOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSB ========================================================= */ + #define R_ADC0_ADANSB_ANSB_Pos (0UL) /*!< ANSB (Bit 0) */ + #define R_ADC0_ADANSB_ANSB_Msk (0x1UL) /*!< ANSB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC0_ADDBLDR_ADDBLDR_Pos (0UL) /*!< ADDBLDR (Bit 0) */ + #define R_ADC0_ADDBLDR_ADDBLDR_Msk (0xffffUL) /*!< ADDBLDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADTSDR ========================================================= */ + #define R_ADC0_ADTSDR_ADTSDR_Pos (0UL) /*!< ADTSDR (Bit 0) */ + #define R_ADC0_ADTSDR_ADTSDR_Msk (0xffffUL) /*!< ADTSDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADOCDR ========================================================= */ + #define R_ADC0_ADOCDR_ADOCDR_Pos (0UL) /*!< ADOCDR (Bit 0) */ + #define R_ADC0_ADOCDR_ADOCDR_Msk (0xffffUL) /*!< ADOCDR (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADRD_RIGHT ======================================================= */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Pos (14UL) /*!< DIAGST (Bit 14) */ + #define R_ADC0_ADRD_RIGHT_DIAGST_Msk (0xc000UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADRD_RIGHT_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_RIGHT_AD_Msk (0x3fffUL) /*!< AD (Bitfield-Mask: 0x3fff) */ +/* ======================================================= ADRD_LEFT ======================================================= */ + #define R_ADC0_ADRD_LEFT_AD_Pos (2UL) /*!< AD (Bit 2) */ + #define R_ADC0_ADRD_LEFT_AD_Msk (0xfffcUL) /*!< AD (Bitfield-Mask: 0x3fff) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRD_LEFT_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC0_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ADC0_ADDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC0_ADSHCR_SHANS2_Pos (10UL) /*!< SHANS2 (Bit 10) */ + #define R_ADC0_ADSHCR_SHANS2_Msk (0x400UL) /*!< SHANS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS1_Pos (9UL) /*!< SHANS1 (Bit 9) */ + #define R_ADC0_ADSHCR_SHANS1_Msk (0x200UL) /*!< SHANS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SHANS0_Pos (8UL) /*!< SHANS0 (Bit 8) */ + #define R_ADC0_ADSHCR_SHANS0_Msk (0x100UL) /*!< SHANS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC0_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDISCR ======================================================== */ + #define R_ADC0_ADDISCR_CHARGE_Pos (4UL) /*!< CHARGE (Bit 4) */ + #define R_ADC0_ADDISCR_CHARGE_Msk (0x10UL) /*!< CHARGE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADDISCR_ADNDIS_Pos (0UL) /*!< ADNDIS (Bit 0) */ + #define R_ADC0_ADDISCR_ADNDIS_Msk (0xfUL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSHMSR ======================================================== */ + #define R_ADC0_ADSHMSR_SHMD_Pos (0UL) /*!< SHMD (Bit 0) */ + #define R_ADC0_ADSHMSR_SHMD_Msk (0x1UL) /*!< SHMD (Bitfield-Mask: 0x01) */ +/* ======================================================== ADACSR ========================================================= */ + #define R_ADC0_ADACSR_ADSAC_Pos (1UL) /*!< ADSAC (Bit 1) */ + #define R_ADC0_ADACSR_ADSAC_Msk (0x2UL) /*!< ADSAC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC0_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC0_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC0_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC0_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Pos (8UL) /*!< GBEXTRG (Bit 8) */ + #define R_ADC0_ADGSPCR_GBEXTRG_Msk (0x100UL) /*!< GBEXTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADICR ========================================================= */ + #define R_ADC0_ADICR_ADIC_Pos (0UL) /*!< ADIC (Bit 0) */ + #define R_ADC0_ADICR_ADIC_Msk (0x3UL) /*!< ADIC (Bitfield-Mask: 0x03) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos (0UL) /*!< ADDBLDRA (Bit 0) */ + #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk (0xffffUL) /*!< ADDBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos (0UL) /*!< ADDBLDRB (Bit 0) */ + #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk (0xffffUL) /*!< ADDBLDRB (Bitfield-Mask: 0xffff) */ +/* ====================================================== ADHVREFCNT ======================================================= */ + #define R_ADC0_ADHVREFCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_ADHVREFCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Pos (4UL) /*!< LVSEL (Bit 4) */ + #define R_ADC0_ADHVREFCNT_LVSEL_Msk (0x10UL) /*!< LVSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Pos (0UL) /*!< HVSEL (Bit 0) */ + #define R_ADC0_ADHVREFCNT_HVSEL_Msk (0x3UL) /*!< HVSEL (Bitfield-Mask: 0x03) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC0_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC0_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC0_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC0_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC0_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC0_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC0_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC0_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC0_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC0_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC0_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ +/* ====================================================== ADCMPANSER ======================================================= */ + #define R_ADC0_ADCMPANSER_CMPOCA_Pos (1UL) /*!< CMPOCA (Bit 1) */ + #define R_ADC0_ADCMPANSER_CMPOCA_Msk (0x2UL) /*!< CMPOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Pos (0UL) /*!< CMPTSA (Bit 0) */ + #define R_ADC0_ADCMPANSER_CMPTSA_Msk (0x1UL) /*!< CMPTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPLER ======================================================== */ + #define R_ADC0_ADCMPLER_CMPLOCA_Pos (1UL) /*!< CMPLOCA (Bit 1) */ + #define R_ADC0_ADCMPLER_CMPLOCA_Msk (0x2UL) /*!< CMPLOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Pos (0UL) /*!< CMPLTSA (Bit 0) */ + #define R_ADC0_ADCMPLER_CMPLTSA_Msk (0x1UL) /*!< CMPLTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPANSR ======================================================= */ + #define R_ADC0_ADCMPANSR_CMPCHA_Pos (0UL) /*!< CMPCHA (Bit 0) */ + #define R_ADC0_ADCMPANSR_CMPCHA_Msk (0x1UL) /*!< CMPCHA (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPLR ======================================================== */ + #define R_ADC0_ADCMPLR_CMPLCHA_Pos (0UL) /*!< CMPLCHA (Bit 0) */ + #define R_ADC0_ADCMPLR_CMPLCHA_Msk (0x1UL) /*!< CMPLCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos (0UL) /*!< ADCMPDR0 (Bit 0) */ + #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk (0xffffUL) /*!< ADCMPDR0 (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos (0UL) /*!< ADCMPDR1 (Bit 0) */ + #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk (0xffffUL) /*!< ADCMPDR1 (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADCMPSR ======================================================== */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Pos (0UL) /*!< CMPSTCHA (Bit 0) */ + #define R_ADC0_ADCMPSR_CMPSTCHA_Msk (0x1UL) /*!< CMPSTCHA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPSER ======================================================== */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Pos (1UL) /*!< CMPSTOCA (Bit 1) */ + #define R_ADC0_ADCMPSER_CMPSTOCA_Msk (0x2UL) /*!< CMPSTOCA (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Pos (0UL) /*!< CMPSTTSA (Bit 0) */ + #define R_ADC0_ADCMPSER_CMPSTTSA_Msk (0x1UL) /*!< CMPSTTSA (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC0_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC0_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC0_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC0_ADWINLLB_ADWINLLB_Pos (0UL) /*!< ADWINLLB (Bit 0) */ + #define R_ADC0_ADWINLLB_ADWINLLB_Msk (0xffffUL) /*!< ADWINLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC0_ADWINULB_ADWINULB_Pos (0UL) /*!< ADWINULB (Bit 0) */ + #define R_ADC0_ADWINULB_ADWINULB_Msk (0xffffUL) /*!< ADWINULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC0_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC0_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTRL ======================================================== */ + #define R_ADC0_ADSSTRL_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRL_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRT ======================================================== */ + #define R_ADC0_ADSSTRT_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRT_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTRO ======================================================== */ + #define R_ADC0_ADSSTRO_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTRO_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC0_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC0_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC0_ADPGACR_P002GEN_Pos (11UL) /*!< P002GEN (Bit 11) */ + #define R_ADC0_ADPGACR_P002GEN_Msk (0x800UL) /*!< P002GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002ENAMP_Pos (10UL) /*!< P002ENAMP (Bit 10) */ + #define R_ADC0_ADPGACR_P002ENAMP_Msk (0x400UL) /*!< P002ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL1_Pos (9UL) /*!< P002SEL1 (Bit 9) */ + #define R_ADC0_ADPGACR_P002SEL1_Msk (0x200UL) /*!< P002SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P002SEL0_Pos (8UL) /*!< P002SEL0 (Bit 8) */ + #define R_ADC0_ADPGACR_P002SEL0_Msk (0x100UL) /*!< P002SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001GEN_Pos (7UL) /*!< P001GEN (Bit 7) */ + #define R_ADC0_ADPGACR_P001GEN_Msk (0x80UL) /*!< P001GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001ENAMP_Pos (6UL) /*!< P001ENAMP (Bit 6) */ + #define R_ADC0_ADPGACR_P001ENAMP_Msk (0x40UL) /*!< P001ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL1_Pos (5UL) /*!< P001SEL1 (Bit 5) */ + #define R_ADC0_ADPGACR_P001SEL1_Msk (0x20UL) /*!< P001SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P001SEL0_Pos (4UL) /*!< P001SEL0 (Bit 4) */ + #define R_ADC0_ADPGACR_P001SEL0_Msk (0x10UL) /*!< P001SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000GEN_Pos (3UL) /*!< P000GEN (Bit 3) */ + #define R_ADC0_ADPGACR_P000GEN_Msk (0x8UL) /*!< P000GEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000ENAMP_Pos (2UL) /*!< P000ENAMP (Bit 2) */ + #define R_ADC0_ADPGACR_P000ENAMP_Msk (0x4UL) /*!< P000ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL1_Pos (1UL) /*!< P000SEL1 (Bit 1) */ + #define R_ADC0_ADPGACR_P000SEL1_Msk (0x2UL) /*!< P000SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P000SEL0_Pos (0UL) /*!< P000SEL0 (Bit 0) */ + #define R_ADC0_ADPGACR_P000SEL0_Msk (0x1UL) /*!< P000SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL0_Pos (12UL) /*!< P003SEL0 (Bit 12) */ + #define R_ADC0_ADPGACR_P003SEL0_Msk (0x1000UL) /*!< P003SEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003SEL1_Pos (13UL) /*!< P003SEL1 (Bit 13) */ + #define R_ADC0_ADPGACR_P003SEL1_Msk (0x2000UL) /*!< P003SEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003ENAMP_Pos (14UL) /*!< P003ENAMP (Bit 14) */ + #define R_ADC0_ADPGACR_P003ENAMP_Msk (0x4000UL) /*!< P003ENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGACR_P003GEN_Pos (15UL) /*!< P003GEN (Bit 15) */ + #define R_ADC0_ADPGACR_P003GEN_Msk (0x8000UL) /*!< P003GEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADRD ========================================================== */ + #define R_ADC0_ADRD_AD_Pos (0UL) /*!< AD (Bit 0) */ + #define R_ADC0_ADRD_AD_Msk (0xffffUL) /*!< AD (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADRST ========================================================= */ + #define R_ADC0_ADRST_DIAGST_Pos (0UL) /*!< DIAGST (Bit 0) */ + #define R_ADC0_ADRST_DIAGST_Msk (0x3UL) /*!< DIAGST (Bitfield-Mask: 0x03) */ +/* ====================================================== VREFAMPCNT ======================================================= */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Pos (1UL) /*!< VREFADCG (Bit 1) */ + #define R_ADC0_VREFAMPCNT_VREFADCG_Msk (0x6UL) /*!< VREFADCG (Bitfield-Mask: 0x03) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos (3UL) /*!< VREFADCEN (Bit 3) */ + #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk (0x8UL) /*!< VREFADCEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Pos (7UL) /*!< ADSLP (Bit 7) */ + #define R_ADC0_VREFAMPCNT_ADSLP_Msk (0x80UL) /*!< ADSLP (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Pos (0UL) /*!< OLDETEN (Bit 0) */ + #define R_ADC0_VREFAMPCNT_OLDETEN_Msk (0x1UL) /*!< OLDETEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_VREFAMPCNT_BGREN_Pos (4UL) /*!< BGREN (Bit 4) */ + #define R_ADC0_VREFAMPCNT_BGREN_Msk (0x10UL) /*!< BGREN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALEXE ======================================================== */ + #define R_ADC0_ADCALEXE_CALEXE_Pos (7UL) /*!< CALEXE (Bit 7) */ + #define R_ADC0_ADCALEXE_CALEXE_Msk (0x80UL) /*!< CALEXE (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADCALEXE_CALMON_Pos (6UL) /*!< CALMON (Bit 6) */ + #define R_ADC0_ADCALEXE_CALMON_Msk (0x40UL) /*!< CALMON (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANIM ========================================================= */ + #define R_ADC0_ADANIM_ANIM_Pos (0UL) /*!< ANIM (Bit 0) */ + #define R_ADC0_ADANIM_ANIM_Msk (0x1UL) /*!< ANIM (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGAGS0 ======================================================== */ + #define R_ADC0_ADPGAGS0_P002GAIN_Pos (8UL) /*!< P002GAIN (Bit 8) */ + #define R_ADC0_ADPGAGS0_P002GAIN_Msk (0xf00UL) /*!< P002GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Pos (4UL) /*!< P001GAIN (Bit 4) */ + #define R_ADC0_ADPGAGS0_P001GAIN_Msk (0xf0UL) /*!< P001GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Pos (0UL) /*!< P000GAIN (Bit 0) */ + #define R_ADC0_ADPGAGS0_P000GAIN_Msk (0xfUL) /*!< P000GAIN (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Pos (12UL) /*!< P003GAIN (Bit 12) */ + #define R_ADC0_ADPGAGS0_P003GAIN_Msk (0xf000UL) /*!< P003GAIN (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADPGADCR0 ======================================================= */ + #define R_ADC0_ADPGADCR0_P003DG_Pos (12UL) /*!< P003DG (Bit 12) */ + #define R_ADC0_ADPGADCR0_P003DG_Msk (0x3000UL) /*!< P003DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P002DEN_Pos (11UL) /*!< P002DEN (Bit 11) */ + #define R_ADC0_ADPGADCR0_P002DEN_Msk (0x800UL) /*!< P002DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P002DG_Pos (8UL) /*!< P002DG (Bit 8) */ + #define R_ADC0_ADPGADCR0_P002DG_Msk (0x300UL) /*!< P002DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P001DEN_Pos (7UL) /*!< P001DEN (Bit 7) */ + #define R_ADC0_ADPGADCR0_P001DEN_Msk (0x80UL) /*!< P001DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P001DG_Pos (4UL) /*!< P001DG (Bit 4) */ + #define R_ADC0_ADPGADCR0_P001DG_Msk (0x30UL) /*!< P001DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P000DEN_Pos (3UL) /*!< P000DEN (Bit 3) */ + #define R_ADC0_ADPGADCR0_P000DEN_Msk (0x8UL) /*!< P000DEN (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADPGADCR0_P000DG_Pos (0UL) /*!< P000DG (Bit 0) */ + #define R_ADC0_ADPGADCR0_P000DG_Msk (0x3UL) /*!< P000DG (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADPGADCR0_P003DEN_Pos (15UL) /*!< P003DEN (Bit 15) */ + #define R_ADC0_ADPGADCR0_P003DEN_Msk (0x8000UL) /*!< P003DEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ADREF ========================================================= */ + #define R_ADC0_ADREF_ADF_Pos (0UL) /*!< ADF (Bit 0) */ + #define R_ADC0_ADREF_ADF_Msk (0x1UL) /*!< ADF (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADREF_ADSCACT_Pos (7UL) /*!< ADSCACT (Bit 7) */ + #define R_ADC0_ADREF_ADSCACT_Msk (0x80UL) /*!< ADSCACT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXREF ======================================================== */ + #define R_ADC0_ADEXREF_GBADF_Pos (0UL) /*!< GBADF (Bit 0) */ + #define R_ADC0_ADEXREF_GBADF_Msk (0x1UL) /*!< GBADF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADAMPOFF ======================================================== */ + #define R_ADC0_ADAMPOFF_OPOFF_Pos (0UL) /*!< OPOFF (Bit 0) */ + #define R_ADC0_ADAMPOFF_OPOFF_Msk (0xffUL) /*!< OPOFF (Bitfield-Mask: 0xff) */ +/* ======================================================== ADTSTPR ======================================================== */ + #define R_ADC0_ADTSTPR_PRO_Pos (0UL) /*!< PRO (Bit 0) */ + #define R_ADC0_ADTSTPR_PRO_Msk (0x1UL) /*!< PRO (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTPR_B0WI_Pos (1UL) /*!< B0WI (Bit 1) */ + #define R_ADC0_ADTSTPR_B0WI_Msk (0x2UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDDACER ======================================================== */ + #define R_ADC0_ADDDACER_WRION_Pos (0UL) /*!< WRION (Bit 0) */ + #define R_ADC0_ADDDACER_WRION_Msk (0x1fUL) /*!< WRION (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_WRIOFF_Pos (8UL) /*!< WRIOFF (Bit 8) */ + #define R_ADC0_ADDDACER_WRIOFF_Msk (0x1f00UL) /*!< WRIOFF (Bitfield-Mask: 0x1f) */ + #define R_ADC0_ADDDACER_ADHS_Pos (15UL) /*!< ADHS (Bit 15) */ + #define R_ADC0_ADDDACER_ADHS_Msk (0x8000UL) /*!< ADHS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADEXTSTR ======================================================== */ + #define R_ADC0_ADEXTSTR_SHTEST_Pos (0UL) /*!< SHTEST (Bit 0) */ + #define R_ADC0_ADEXTSTR_SHTEST_Msk (0x7UL) /*!< SHTEST (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADEXTSTR_SWTST_Pos (4UL) /*!< SWTST (Bit 4) */ + #define R_ADC0_ADEXTSTR_SWTST_Msk (0x30UL) /*!< SWTST (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_SHTRM_Pos (8UL) /*!< SHTRM (Bit 8) */ + #define R_ADC0_ADEXTSTR_SHTRM_Msk (0x300UL) /*!< SHTRM (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Pos (11UL) /*!< ADTRM3 (Bit 11) */ + #define R_ADC0_ADEXTSTR_ADTRM3_Msk (0x800UL) /*!< ADTRM3 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Pos (12UL) /*!< ADTRM2 (Bit 12) */ + #define R_ADC0_ADEXTSTR_ADTRM2_Msk (0x3000UL) /*!< ADTRM2 (Bitfield-Mask: 0x03) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Pos (14UL) /*!< ADTRM1 (Bit 14) */ + #define R_ADC0_ADEXTSTR_ADTRM1_Msk (0xc000UL) /*!< ADTRM1 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADTSTRA ======================================================== */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Pos (0UL) /*!< ATBUSSEL (Bit 0) */ + #define R_ADC0_ADTSTRA_ATBUSSEL_Msk (0x1UL) /*!< ATBUSSEL (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Pos (1UL) /*!< TSTSWREF (Bit 1) */ + #define R_ADC0_ADTSTRA_TSTSWREF_Msk (0xeUL) /*!< TSTSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADTSTRA_OCSW_Pos (5UL) /*!< OCSW (Bit 5) */ + #define R_ADC0_ADTSTRA_OCSW_Msk (0x20UL) /*!< OCSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_TSSW_Pos (6UL) /*!< TSSW (Bit 6) */ + #define R_ADC0_ADTSTRA_TSSW_Msk (0x40UL) /*!< TSSW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Pos (8UL) /*!< ADTEST_AD (Bit 8) */ + #define R_ADC0_ADTSTRA_ADTEST_AD_Msk (0xf00UL) /*!< ADTEST_AD (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Pos (12UL) /*!< ADTEST_IO (Bit 12) */ + #define R_ADC0_ADTSTRA_ADTEST_IO_Msk (0xf000UL) /*!< ADTEST_IO (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADTSTRB ======================================================== */ + #define R_ADC0_ADTSTRB_ADVAL_Pos (0UL) /*!< ADVAL (Bit 0) */ + #define R_ADC0_ADTSTRB_ADVAL_Msk (0x7fffUL) /*!< ADVAL (Bitfield-Mask: 0x7fff) */ +/* ======================================================== ADTSTRC ======================================================== */ + #define R_ADC0_ADTSTRC_ADMD_Pos (0UL) /*!< ADMD (Bit 0) */ + #define R_ADC0_ADTSTRC_ADMD_Msk (0xffUL) /*!< ADMD (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADTSTRC_SYNCERR_Pos (12UL) /*!< SYNCERR (Bit 12) */ + #define R_ADC0_ADTSTRC_SYNCERR_Msk (0x1000UL) /*!< SYNCERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADTSTRD ======================================================== */ + #define R_ADC0_ADTSTRD_ADVAL16_Pos (0UL) /*!< ADVAL16 (Bit 0) */ + #define R_ADC0_ADTSTRD_ADVAL16_Msk (0x1UL) /*!< ADVAL16 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR0 ======================================================= */ + #define R_ADC0_ADSWTSTR0_CHSW00_Pos (0UL) /*!< CHSW00 (Bit 0) */ + #define R_ADC0_ADSWTSTR0_CHSW00_Msk (0x1UL) /*!< CHSW00 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Pos (1UL) /*!< CHSW01 (Bit 1) */ + #define R_ADC0_ADSWTSTR0_CHSW01_Msk (0x2UL) /*!< CHSW01 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Pos (2UL) /*!< CHSW02 (Bit 2) */ + #define R_ADC0_ADSWTSTR0_CHSW02_Msk (0x4UL) /*!< CHSW02 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Pos (3UL) /*!< CHSW03 (Bit 3) */ + #define R_ADC0_ADSWTSTR0_CHSW03_Msk (0x8UL) /*!< CHSW03 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Pos (4UL) /*!< CHSW04 (Bit 4) */ + #define R_ADC0_ADSWTSTR0_CHSW04_Msk (0x10UL) /*!< CHSW04 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Pos (5UL) /*!< CHSW05 (Bit 5) */ + #define R_ADC0_ADSWTSTR0_CHSW05_Msk (0x20UL) /*!< CHSW05 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR1 ======================================================= */ + #define R_ADC0_ADSWTSTR1_CHSW16_Pos (0UL) /*!< CHSW16 (Bit 0) */ + #define R_ADC0_ADSWTSTR1_CHSW16_Msk (0x1UL) /*!< CHSW16 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Pos (1UL) /*!< CHSW17 (Bit 1) */ + #define R_ADC0_ADSWTSTR1_CHSW17_Msk (0x2UL) /*!< CHSW17 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Pos (2UL) /*!< CHSW18 (Bit 2) */ + #define R_ADC0_ADSWTSTR1_CHSW18_Msk (0x4UL) /*!< CHSW18 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Pos (3UL) /*!< CHSW19 (Bit 3) */ + #define R_ADC0_ADSWTSTR1_CHSW19_Msk (0x8UL) /*!< CHSW19 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Pos (4UL) /*!< CHSW20 (Bit 4) */ + #define R_ADC0_ADSWTSTR1_CHSW20_Msk (0x10UL) /*!< CHSW20 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Pos (5UL) /*!< CHSW21 (Bit 5) */ + #define R_ADC0_ADSWTSTR1_CHSW21_Msk (0x20UL) /*!< CHSW21 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSWTSTR2 ======================================================= */ + #define R_ADC0_ADSWTSTR2_EX0SW_Pos (0UL) /*!< EX0SW (Bit 0) */ + #define R_ADC0_ADSWTSTR2_EX0SW_Msk (0x1UL) /*!< EX0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Pos (1UL) /*!< EX1SW (Bit 1) */ + #define R_ADC0_ADSWTSTR2_EX1SW_Msk (0x2UL) /*!< EX1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos (4UL) /*!< SHBYPS0 (Bit 4) */ + #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk (0x10UL) /*!< SHBYPS0 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos (5UL) /*!< SHBYPS1 (Bit 5) */ + #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk (0x20UL) /*!< SHBYPS1 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos (6UL) /*!< SHBYPS2 (Bit 6) */ + #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk (0x40UL) /*!< SHBYPS2 (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Pos (8UL) /*!< GRP0SW (Bit 8) */ + #define R_ADC0_ADSWTSTR2_GRP0SW_Msk (0x100UL) /*!< GRP0SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Pos (9UL) /*!< GRP1SW (Bit 9) */ + #define R_ADC0_ADSWTSTR2_GRP1SW_Msk (0x200UL) /*!< GRP1SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Pos (10UL) /*!< GRP2SW (Bit 10) */ + #define R_ADC0_ADSWTSTR2_GRP2SW_Msk (0x400UL) /*!< GRP2SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Pos (11UL) /*!< GRP3SW (Bit 11) */ + #define R_ADC0_ADSWTSTR2_GRP3SW_Msk (0x800UL) /*!< GRP3SW (Bitfield-Mask: 0x01) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos (12UL) /*!< GRPEX1SW (Bit 12) */ + #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk (0x1000UL) /*!< GRPEX1SW (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSWCR ========================================================= */ + #define R_ADC0_ADSWCR_ADSWREF_Pos (0UL) /*!< ADSWREF (Bit 0) */ + #define R_ADC0_ADSWCR_ADSWREF_Msk (0x7UL) /*!< ADSWREF (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADSWCR_SHSWREF_Pos (4UL) /*!< SHSWREF (Bit 4) */ + #define R_ADC0_ADSWCR_SHSWREF_Msk (0x70UL) /*!< SHSWREF (Bitfield-Mask: 0x07) */ +/* ======================================================== ADGSCS ========================================================= */ + #define R_ADC0_ADGSCS_CHSELGB_Pos (0UL) /*!< CHSELGB (Bit 0) */ + #define R_ADC0_ADGSCS_CHSELGB_Msk (0xffUL) /*!< CHSELGB (Bitfield-Mask: 0xff) */ + #define R_ADC0_ADGSCS_CHSELGA_Pos (8UL) /*!< CHSELGA (Bit 8) */ + #define R_ADC0_ADGSCS_CHSELGA_Msk (0xff00UL) /*!< CHSELGA (Bitfield-Mask: 0xff) */ +/* ========================================================= ADSER ========================================================= */ + #define R_ADC0_ADSER_SMPEX_Pos (7UL) /*!< SMPEX (Bit 7) */ + #define R_ADC0_ADSER_SMPEX_Msk (0x80UL) /*!< SMPEX (Bitfield-Mask: 0x01) */ +/* ======================================================== ADBUF0 ========================================================= */ + #define R_ADC0_ADBUF0_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF0_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF1 ========================================================= */ + #define R_ADC0_ADBUF1_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF1_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF2 ========================================================= */ + #define R_ADC0_ADBUF2_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF2_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF3 ========================================================= */ + #define R_ADC0_ADBUF3_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF3_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF4 ========================================================= */ + #define R_ADC0_ADBUF4_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF4_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF5 ========================================================= */ + #define R_ADC0_ADBUF5_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF5_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF6 ========================================================= */ + #define R_ADC0_ADBUF6_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF6_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF7 ========================================================= */ + #define R_ADC0_ADBUF7_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF7_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF8 ========================================================= */ + #define R_ADC0_ADBUF8_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF8_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF9 ========================================================= */ + #define R_ADC0_ADBUF9_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF9_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF10 ======================================================== */ + #define R_ADC0_ADBUF10_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF10_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF11 ======================================================== */ + #define R_ADC0_ADBUF11_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF11_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF12 ======================================================== */ + #define R_ADC0_ADBUF12_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF12_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF13 ======================================================== */ + #define R_ADC0_ADBUF13_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF13_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF14 ======================================================== */ + #define R_ADC0_ADBUF14_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF14_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUF15 ======================================================== */ + #define R_ADC0_ADBUF15_ADBUF_Pos (0UL) /*!< ADBUF (Bit 0) */ + #define R_ADC0_ADBUF15_ADBUF_Msk (0xffffUL) /*!< ADBUF (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADBUFEN ======================================================== */ + #define R_ADC0_ADBUFEN_BUFEN_Pos (0UL) /*!< BUFEN (Bit 0) */ + #define R_ADC0_ADBUFEN_BUFEN_Msk (0x1UL) /*!< BUFEN (Bitfield-Mask: 0x01) */ +/* ======================================================= ADBUFPTR ======================================================== */ + #define R_ADC0_ADBUFPTR_BUFPTR_Pos (0UL) /*!< BUFPTR (Bit 0) */ + #define R_ADC0_ADBUFPTR_BUFPTR_Msk (0xfUL) /*!< BUFPTR (Bitfield-Mask: 0x0f) */ + #define R_ADC0_ADBUFPTR_PTROVF_Pos (4UL) /*!< PTROVF (Bit 4) */ + #define R_ADC0_ADBUFPTR_PTROVF_Msk (0x10UL) /*!< PTROVF (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS0 ======================================================= */ + #define R_ADC0_ADPGADBS0_P0BIAS_Pos (0UL) /*!< P0BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS0_P0BIAS_Msk (0x1UL) /*!< P0BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADPGADBS1 ======================================================= */ + #define R_ADC0_ADPGADBS1_P3BIAS_Pos (0UL) /*!< P3BIAS (Bit 0) */ + #define R_ADC0_ADPGADBS1_P3BIAS_Msk (0x1UL) /*!< P3BIAS (Bitfield-Mask: 0x01) */ +/* ======================================================= ADREFMON ======================================================== */ + #define R_ADC0_ADREFMON_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC0_ADREFMON_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC0_ADREFMON_MONSEL_Pos (16UL) /*!< MONSEL (Bit 16) */ + #define R_ADC0_ADREFMON_MONSEL_Msk (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PSARB ========================================================= */ + #define R_PSCU_PSARB_PSARB1_Pos (1UL) /*!< PSARB1 (Bit 1) */ + #define R_PSCU_PSARB_PSARB1_Msk (0x2UL) /*!< PSARB1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB2_Pos (2UL) /*!< PSARB2 (Bit 2) */ + #define R_PSCU_PSARB_PSARB2_Msk (0x4UL) /*!< PSARB2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB3_Pos (3UL) /*!< PSARB3 (Bit 3) */ + #define R_PSCU_PSARB_PSARB3_Msk (0x8UL) /*!< PSARB3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB6_Pos (6UL) /*!< PSARB6 (Bit 6) */ + #define R_PSCU_PSARB_PSARB6_Msk (0x40UL) /*!< PSARB6 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB7_Pos (7UL) /*!< PSARB7 (Bit 7) */ + #define R_PSCU_PSARB_PSARB7_Msk (0x80UL) /*!< PSARB7 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB8_Pos (8UL) /*!< PSARB8 (Bit 8) */ + #define R_PSCU_PSARB_PSARB8_Msk (0x100UL) /*!< PSARB8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB9_Pos (9UL) /*!< PSARB9 (Bit 9) */ + #define R_PSCU_PSARB_PSARB9_Msk (0x200UL) /*!< PSARB9 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB11_Pos (11UL) /*!< PSARB11 (Bit 11) */ + #define R_PSCU_PSARB_PSARB11_Msk (0x800UL) /*!< PSARB11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB12_Pos (12UL) /*!< PSARB12 (Bit 12) */ + #define R_PSCU_PSARB_PSARB12_Msk (0x1000UL) /*!< PSARB12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB15_Pos (15UL) /*!< PSARB15 (Bit 15) */ + #define R_PSCU_PSARB_PSARB15_Msk (0x8000UL) /*!< PSARB15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB16_Pos (16UL) /*!< PSARB16 (Bit 16) */ + #define R_PSCU_PSARB_PSARB16_Msk (0x10000UL) /*!< PSARB16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB18_Pos (18UL) /*!< PSARB18 (Bit 18) */ + #define R_PSCU_PSARB_PSARB18_Msk (0x40000UL) /*!< PSARB18 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB19_Pos (19UL) /*!< PSARB19 (Bit 19) */ + #define R_PSCU_PSARB_PSARB19_Msk (0x80000UL) /*!< PSARB19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB22_Pos (22UL) /*!< PSARB22 (Bit 22) */ + #define R_PSCU_PSARB_PSARB22_Msk (0x400000UL) /*!< PSARB22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB23_Pos (23UL) /*!< PSARB23 (Bit 23) */ + #define R_PSCU_PSARB_PSARB23_Msk (0x800000UL) /*!< PSARB23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB24_Pos (24UL) /*!< PSARB24 (Bit 24) */ + #define R_PSCU_PSARB_PSARB24_Msk (0x1000000UL) /*!< PSARB24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB25_Pos (25UL) /*!< PSARB25 (Bit 25) */ + #define R_PSCU_PSARB_PSARB25_Msk (0x2000000UL) /*!< PSARB25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB26_Pos (26UL) /*!< PSARB26 (Bit 26) */ + #define R_PSCU_PSARB_PSARB26_Msk (0x4000000UL) /*!< PSARB26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB27_Pos (27UL) /*!< PSARB27 (Bit 27) */ + #define R_PSCU_PSARB_PSARB27_Msk (0x8000000UL) /*!< PSARB27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB28_Pos (28UL) /*!< PSARB28 (Bit 28) */ + #define R_PSCU_PSARB_PSARB28_Msk (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB29_Pos (29UL) /*!< PSARB29 (Bit 29) */ + #define R_PSCU_PSARB_PSARB29_Msk (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB30_Pos (30UL) /*!< PSARB30 (Bit 30) */ + #define R_PSCU_PSARB_PSARB30_Msk (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARB_PSARB31_Pos (31UL) /*!< PSARB31 (Bit 31) */ + #define R_PSCU_PSARB_PSARB31_Msk (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARC ========================================================= */ + #define R_PSCU_PSARC_PSARC0_Pos (0UL) /*!< PSARC0 (Bit 0) */ + #define R_PSCU_PSARC_PSARC0_Msk (0x1UL) /*!< PSARC0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC1_Pos (1UL) /*!< PSARC1 (Bit 1) */ + #define R_PSCU_PSARC_PSARC1_Msk (0x2UL) /*!< PSARC1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC3_Pos (3UL) /*!< PSARC3 (Bit 3) */ + #define R_PSCU_PSARC_PSARC3_Msk (0x8UL) /*!< PSARC3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC8_Pos (8UL) /*!< PSARC8 (Bit 8) */ + #define R_PSCU_PSARC_PSARC8_Msk (0x100UL) /*!< PSARC8 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC12_Pos (12UL) /*!< PSARC12 (Bit 12) */ + #define R_PSCU_PSARC_PSARC12_Msk (0x1000UL) /*!< PSARC12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC13_Pos (13UL) /*!< PSARC13 (Bit 13) */ + #define R_PSCU_PSARC_PSARC13_Msk (0x2000UL) /*!< PSARC13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC20_Pos (20UL) /*!< PSARC20 (Bit 20) */ + #define R_PSCU_PSARC_PSARC20_Msk (0x100000UL) /*!< PSARC20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC27_Pos (27UL) /*!< PSARC27 (Bit 27) */ + #define R_PSCU_PSARC_PSARC27_Msk (0x8000000UL) /*!< PSARC27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARC_PSARC31_Pos (31UL) /*!< PSARC31 (Bit 31) */ + #define R_PSCU_PSARC_PSARC31_Msk (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARD ========================================================= */ + #define R_PSCU_PSARD_PSARD0_Pos (0UL) /*!< PSARD0 (Bit 0) */ + #define R_PSCU_PSARD_PSARD0_Msk (0x1UL) /*!< PSARD0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD1_Pos (1UL) /*!< PSARD1 (Bit 1) */ + #define R_PSCU_PSARD_PSARD1_Msk (0x2UL) /*!< PSARD1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD2_Pos (2UL) /*!< PSARD2 (Bit 2) */ + #define R_PSCU_PSARD_PSARD2_Msk (0x4UL) /*!< PSARD2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD3_Pos (3UL) /*!< PSARD3 (Bit 3) */ + #define R_PSCU_PSARD_PSARD3_Msk (0x8UL) /*!< PSARD3 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD11_Pos (11UL) /*!< PSARD11 (Bit 11) */ + #define R_PSCU_PSARD_PSARD11_Msk (0x800UL) /*!< PSARD11 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD12_Pos (12UL) /*!< PSARD12 (Bit 12) */ + #define R_PSCU_PSARD_PSARD12_Msk (0x1000UL) /*!< PSARD12 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD13_Pos (13UL) /*!< PSARD13 (Bit 13) */ + #define R_PSCU_PSARD_PSARD13_Msk (0x2000UL) /*!< PSARD13 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD14_Pos (14UL) /*!< PSARD14 (Bit 14) */ + #define R_PSCU_PSARD_PSARD14_Msk (0x4000UL) /*!< PSARD14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD15_Pos (15UL) /*!< PSARD15 (Bit 15) */ + #define R_PSCU_PSARD_PSARD15_Msk (0x8000UL) /*!< PSARD15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD16_Pos (16UL) /*!< PSARD16 (Bit 16) */ + #define R_PSCU_PSARD_PSARD16_Msk (0x10000UL) /*!< PSARD16 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD19_Pos (19UL) /*!< PSARD19 (Bit 19) */ + #define R_PSCU_PSARD_PSARD19_Msk (0x80000UL) /*!< PSARD19 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD20_Pos (20UL) /*!< PSARD20 (Bit 20) */ + #define R_PSCU_PSARD_PSARD20_Msk (0x100000UL) /*!< PSARD20 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD22_Pos (22UL) /*!< PSARD22 (Bit 22) */ + #define R_PSCU_PSARD_PSARD22_Msk (0x400000UL) /*!< PSARD22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD25_Pos (25UL) /*!< PSARD25 (Bit 25) */ + #define R_PSCU_PSARD_PSARD25_Msk (0x2000000UL) /*!< PSARD25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD26_Pos (26UL) /*!< PSARD26 (Bit 26) */ + #define R_PSCU_PSARD_PSARD26_Msk (0x4000000UL) /*!< PSARD26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD27_Pos (27UL) /*!< PSARD27 (Bit 27) */ + #define R_PSCU_PSARD_PSARD27_Msk (0x8000000UL) /*!< PSARD27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARD_PSARD28_Pos (28UL) /*!< PSARD28 (Bit 28) */ + #define R_PSCU_PSARD_PSARD28_Msk (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01) */ +/* ========================================================= PSARE ========================================================= */ + #define R_PSCU_PSARE_PSARE0_Pos (0UL) /*!< PSARE0 (Bit 0) */ + #define R_PSCU_PSARE_PSARE0_Msk (0x1UL) /*!< PSARE0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE1_Pos (1UL) /*!< PSARE1 (Bit 1) */ + #define R_PSCU_PSARE_PSARE1_Msk (0x2UL) /*!< PSARE1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE2_Pos (2UL) /*!< PSARE2 (Bit 2) */ + #define R_PSCU_PSARE_PSARE2_Msk (0x4UL) /*!< PSARE2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE14_Pos (14UL) /*!< PSARE14 (Bit 14) */ + #define R_PSCU_PSARE_PSARE14_Msk (0x4000UL) /*!< PSARE14 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE15_Pos (15UL) /*!< PSARE15 (Bit 15) */ + #define R_PSCU_PSARE_PSARE15_Msk (0x8000UL) /*!< PSARE15 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE22_Pos (22UL) /*!< PSARE22 (Bit 22) */ + #define R_PSCU_PSARE_PSARE22_Msk (0x400000UL) /*!< PSARE22 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE23_Pos (23UL) /*!< PSARE23 (Bit 23) */ + #define R_PSCU_PSARE_PSARE23_Msk (0x800000UL) /*!< PSARE23 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE24_Pos (24UL) /*!< PSARE24 (Bit 24) */ + #define R_PSCU_PSARE_PSARE24_Msk (0x1000000UL) /*!< PSARE24 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE25_Pos (25UL) /*!< PSARE25 (Bit 25) */ + #define R_PSCU_PSARE_PSARE25_Msk (0x2000000UL) /*!< PSARE25 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE26_Pos (26UL) /*!< PSARE26 (Bit 26) */ + #define R_PSCU_PSARE_PSARE26_Msk (0x4000000UL) /*!< PSARE26 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE27_Pos (27UL) /*!< PSARE27 (Bit 27) */ + #define R_PSCU_PSARE_PSARE27_Msk (0x8000000UL) /*!< PSARE27 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE28_Pos (28UL) /*!< PSARE28 (Bit 28) */ + #define R_PSCU_PSARE_PSARE28_Msk (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE29_Pos (29UL) /*!< PSARE29 (Bit 29) */ + #define R_PSCU_PSARE_PSARE29_Msk (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE30_Pos (30UL) /*!< PSARE30 (Bit 30) */ + #define R_PSCU_PSARE_PSARE30_Msk (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01) */ + #define R_PSCU_PSARE_PSARE31_Pos (31UL) /*!< PSARE31 (Bit 31) */ + #define R_PSCU_PSARE_PSARE31_Msk (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01) */ +/* ========================================================= MSSAR ========================================================= */ + #define R_PSCU_MSSAR_MSSAR0_Pos (0UL) /*!< MSSAR0 (Bit 0) */ + #define R_PSCU_MSSAR_MSSAR0_Msk (0x1UL) /*!< MSSAR0 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR1_Pos (1UL) /*!< MSSAR1 (Bit 1) */ + #define R_PSCU_MSSAR_MSSAR1_Msk (0x2UL) /*!< MSSAR1 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR2_Pos (2UL) /*!< MSSAR2 (Bit 2) */ + #define R_PSCU_MSSAR_MSSAR2_Msk (0x4UL) /*!< MSSAR2 (Bitfield-Mask: 0x01) */ + #define R_PSCU_MSSAR_MSSAR3_Pos (3UL) /*!< MSSAR3 (Bit 3) */ + #define R_PSCU_MSSAR_MSSAR3_Msk (0x8UL) /*!< MSSAR3 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFSAMONA ======================================================== */ + #define R_PSCU_CFSAMONA_CFS2_Pos (15UL) /*!< CFS2 (Bit 15) */ + #define R_PSCU_CFSAMONA_CFS2_Msk (0xff8000UL) /*!< CFS2 (Bitfield-Mask: 0x1ff) */ +/* ======================================================= CFSAMONB ======================================================== */ + #define R_PSCU_CFSAMONB_CFS1_Pos (10UL) /*!< CFS1 (Bit 10) */ + #define R_PSCU_CFSAMONB_CFS1_Msk (0xfffc00UL) /*!< CFS1 (Bitfield-Mask: 0x3fff) */ +/* ======================================================== DFSAMON ======================================================== */ + #define R_PSCU_DFSAMON_DFS_Pos (10UL) /*!< DFS (Bit 10) */ + #define R_PSCU_DFSAMON_DFS_Msk (0xfc00UL) /*!< DFS (Bitfield-Mask: 0x3f) */ +/* ======================================================== SSAMONA ======================================================== */ + #define R_PSCU_SSAMONA_SS2_Pos (13UL) /*!< SS2 (Bit 13) */ + #define R_PSCU_SSAMONA_SS2_Msk (0x1fe000UL) /*!< SS2 (Bitfield-Mask: 0xff) */ +/* ======================================================== SSAMONB ======================================================== */ + #define R_PSCU_SSAMONB_SS1_Pos (10UL) /*!< SS1 (Bit 10) */ + #define R_PSCU_SSAMONB_SS1_Msk (0x1ffc00UL) /*!< SS1 (Bitfield-Mask: 0x7ff) */ +/* ======================================================== DLMMON ========================================================= */ + #define R_PSCU_DLMMON_DLMMON_Pos (0UL) /*!< DLMMON (Bit 0) */ + #define R_PSCU_DLMMON_DLMMON_Msk (0xfUL) /*!< DLMMON (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTW0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== AGT ========================================================== */ + #define R_AGTW0_AGT_AGT_Pos (0UL) /*!< AGT (Bit 0) */ + #define R_AGTW0_AGT_AGT_Msk (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMA ========================================================= */ + #define R_AGTW0_AGTCMA_AGTCMA_Pos (0UL) /*!< AGTCMA (Bit 0) */ + #define R_AGTW0_AGTCMA_AGTCMA_Msk (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== AGTCMB ========================================================= */ + #define R_AGTW0_AGTCMB_AGTCMB_Pos (0UL) /*!< AGTCMB (Bit 0) */ + #define R_AGTW0_AGTCMB_AGTCMB_Msk (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= AGTCR ========================================================= */ + #define R_AGTW0_AGTCR_TCMBF_Pos (7UL) /*!< TCMBF (Bit 7) */ + #define R_AGTW0_AGTCR_TCMBF_Msk (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TCMAF_Pos (6UL) /*!< TCMAF (Bit 6) */ + #define R_AGTW0_AGTCR_TCMAF_Msk (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TUNDF_Pos (5UL) /*!< TUNDF (Bit 5) */ + #define R_AGTW0_AGTCR_TUNDF_Msk (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TEDGF_Pos (4UL) /*!< TEDGF (Bit 4) */ + #define R_AGTW0_AGTCR_TEDGF_Msk (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TSTOP_Pos (2UL) /*!< TSTOP (Bit 2) */ + #define R_AGTW0_AGTCR_TSTOP_Msk (0x4UL) /*!< TSTOP (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TCSTF_Pos (1UL) /*!< TCSTF (Bit 1) */ + #define R_AGTW0_AGTCR_TCSTF_Msk (0x2UL) /*!< TCSTF (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCR_TSTART_Pos (0UL) /*!< TSTART (Bit 0) */ + #define R_AGTW0_AGTCR_TSTART_Msk (0x1UL) /*!< TSTART (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTMR1 ========================================================= */ + #define R_AGTW0_AGTMR1_TCK_Pos (4UL) /*!< TCK (Bit 4) */ + #define R_AGTW0_AGTMR1_TCK_Msk (0x70UL) /*!< TCK (Bitfield-Mask: 0x07) */ + #define R_AGTW0_AGTMR1_TEDGPL_Pos (3UL) /*!< TEDGPL (Bit 3) */ + #define R_AGTW0_AGTMR1_TEDGPL_Msk (0x8UL) /*!< TEDGPL (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTMR1_TMOD_Pos (0UL) /*!< TMOD (Bit 0) */ + #define R_AGTW0_AGTMR1_TMOD_Msk (0x7UL) /*!< TMOD (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTMR2 ========================================================= */ + #define R_AGTW0_AGTMR2_LPM_Pos (7UL) /*!< LPM (Bit 7) */ + #define R_AGTW0_AGTMR2_LPM_Msk (0x80UL) /*!< LPM (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTMR2_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_AGTW0_AGTMR2_CKS_Msk (0x7UL) /*!< CKS (Bitfield-Mask: 0x07) */ +/* ======================================================== AGTIOC ========================================================= */ + #define R_AGTW0_AGTIOC_TIOGT_Pos (6UL) /*!< TIOGT (Bit 6) */ + #define R_AGTW0_AGTIOC_TIOGT_Msk (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03) */ + #define R_AGTW0_AGTIOC_TIPF_Pos (4UL) /*!< TIPF (Bit 4) */ + #define R_AGTW0_AGTIOC_TIPF_Msk (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03) */ + #define R_AGTW0_AGTIOC_TOE_Pos (2UL) /*!< TOE (Bit 2) */ + #define R_AGTW0_AGTIOC_TOE_Msk (0x4UL) /*!< TOE (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTIOC_TEDGSEL_Pos (0UL) /*!< TEDGSEL (Bit 0) */ + #define R_AGTW0_AGTIOC_TEDGSEL_Msk (0x1UL) /*!< TEDGSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTISR ========================================================= */ + #define R_AGTW0_AGTISR_EEPS_Pos (2UL) /*!< EEPS (Bit 2) */ + #define R_AGTW0_AGTISR_EEPS_Msk (0x4UL) /*!< EEPS (Bitfield-Mask: 0x01) */ +/* ======================================================== AGTCMSR ======================================================== */ + #define R_AGTW0_AGTCMSR_TOPOLB_Pos (6UL) /*!< TOPOLB (Bit 6) */ + #define R_AGTW0_AGTCMSR_TOPOLB_Msk (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOEB_Pos (5UL) /*!< TOEB (Bit 5) */ + #define R_AGTW0_AGTCMSR_TOEB_Msk (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TCMEB_Pos (4UL) /*!< TCMEB (Bit 4) */ + #define R_AGTW0_AGTCMSR_TCMEB_Msk (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOPOLA_Pos (2UL) /*!< TOPOLA (Bit 2) */ + #define R_AGTW0_AGTCMSR_TOPOLA_Msk (0x4UL) /*!< TOPOLA (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TOEA_Pos (1UL) /*!< TOEA (Bit 1) */ + #define R_AGTW0_AGTCMSR_TOEA_Msk (0x2UL) /*!< TOEA (Bitfield-Mask: 0x01) */ + #define R_AGTW0_AGTCMSR_TCMEA_Pos (0UL) /*!< TCMEA (Bit 0) */ + #define R_AGTW0_AGTCMSR_TCMEA_Msk (0x1UL) /*!< TCMEA (Bitfield-Mask: 0x01) */ +/* ======================================================= AGTIOSEL ======================================================== */ + #define R_AGTW0_AGTIOSEL_TIES_Pos (4UL) /*!< TIES (Bit 4) */ + #define R_AGTW0_AGTIOSEL_TIES_Msk (0x10UL) /*!< TIES (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CACR0 ========================================================= */ + #define R_CAC_CACR0_CFME_Pos (0UL) /*!< CFME (Bit 0) */ + #define R_CAC_CACR0_CFME_Msk (0x1UL) /*!< CFME (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR1 ========================================================= */ + #define R_CAC_CACR1_EDGES_Pos (6UL) /*!< EDGES (Bit 6) */ + #define R_CAC_CACR1_EDGES_Msk (0xc0UL) /*!< EDGES (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_CAC_CACR1_TCSS_Msk (0x30UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR1_FMCS_Pos (1UL) /*!< FMCS (Bit 1) */ + #define R_CAC_CACR1_FMCS_Msk (0xeUL) /*!< FMCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR1_CACREFE_Pos (0UL) /*!< CACREFE (Bit 0) */ + #define R_CAC_CACR1_CACREFE_Msk (0x1UL) /*!< CACREFE (Bitfield-Mask: 0x01) */ +/* ========================================================= CACR2 ========================================================= */ + #define R_CAC_CACR2_DFS_Pos (6UL) /*!< DFS (Bit 6) */ + #define R_CAC_CACR2_DFS_Msk (0xc0UL) /*!< DFS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RCDS_Pos (4UL) /*!< RCDS (Bit 4) */ + #define R_CAC_CACR2_RCDS_Msk (0x30UL) /*!< RCDS (Bitfield-Mask: 0x03) */ + #define R_CAC_CACR2_RSCS_Pos (1UL) /*!< RSCS (Bit 1) */ + #define R_CAC_CACR2_RSCS_Msk (0xeUL) /*!< RSCS (Bitfield-Mask: 0x07) */ + #define R_CAC_CACR2_RPS_Pos (0UL) /*!< RPS (Bit 0) */ + #define R_CAC_CACR2_RPS_Msk (0x1UL) /*!< RPS (Bitfield-Mask: 0x01) */ +/* ========================================================= CAICR ========================================================= */ + #define R_CAC_CAICR_OVFFCL_Pos (6UL) /*!< OVFFCL (Bit 6) */ + #define R_CAC_CAICR_OVFFCL_Msk (0x40UL) /*!< OVFFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDFCL_Pos (5UL) /*!< MENDFCL (Bit 5) */ + #define R_CAC_CAICR_MENDFCL_Msk (0x20UL) /*!< MENDFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRFCL_Pos (4UL) /*!< FERRFCL (Bit 4) */ + #define R_CAC_CAICR_FERRFCL_Msk (0x10UL) /*!< FERRFCL (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_OVFIE_Pos (2UL) /*!< OVFIE (Bit 2) */ + #define R_CAC_CAICR_OVFIE_Msk (0x4UL) /*!< OVFIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_MENDIE_Pos (1UL) /*!< MENDIE (Bit 1) */ + #define R_CAC_CAICR_MENDIE_Msk (0x2UL) /*!< MENDIE (Bitfield-Mask: 0x01) */ + #define R_CAC_CAICR_FERRIE_Pos (0UL) /*!< FERRIE (Bit 0) */ + #define R_CAC_CAICR_FERRIE_Msk (0x1UL) /*!< FERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================= CASTR ========================================================= */ + #define R_CAC_CASTR_OVFF_Pos (2UL) /*!< OVFF (Bit 2) */ + #define R_CAC_CASTR_OVFF_Msk (0x4UL) /*!< OVFF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_MENDF_Pos (1UL) /*!< MENDF (Bit 1) */ + #define R_CAC_CASTR_MENDF_Msk (0x2UL) /*!< MENDF (Bitfield-Mask: 0x01) */ + #define R_CAC_CASTR_FERRF_Pos (0UL) /*!< FERRF (Bit 0) */ + #define R_CAC_CASTR_FERRF_Msk (0x1UL) /*!< FERRF (Bitfield-Mask: 0x01) */ +/* ======================================================== CAULVR ========================================================= */ + #define R_CAC_CAULVR_CAULVR_Pos (0UL) /*!< CAULVR (Bit 0) */ + #define R_CAC_CAULVR_CAULVR_Msk (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CALLVR ========================================================= */ + #define R_CAC_CALLVR_CALLVR_Pos (0UL) /*!< CALLVR (Bit 0) */ + #define R_CAC_CALLVR_CALLVR_Msk (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff) */ +/* ======================================================== CACNTBR ======================================================== */ + #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ + #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MKR ========================================================== */ + #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ========================================================= FIDCR ========================================================= */ + #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ + #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ + #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ + #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ + #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ + #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ + #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== MKIVLR ========================================================= */ + #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ========================================================= MIER ========================================================== */ + #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ + #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ + #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ + #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ + #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MIER_FIFO ======================================================= */ + #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ + #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ + #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ + #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ + #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ + #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ + #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ + #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ + #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ + #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ + #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ + #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ + #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ + #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ + #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ + #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ + #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ + #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ + #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ + #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ + #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ + #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ + #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ + #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ + #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ + #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ + #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ + #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ + #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ + #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_TX ======================================================== */ + #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ + #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ + #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ + #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ +/* ======================================================== MCTL_RX ======================================================== */ + #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ + #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ + #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ + #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ + #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ + #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ + #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ + #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ +/* ========================================================= CTLR ========================================================== */ + #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ + #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ + #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ + #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ + #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ + #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ + #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ + #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ + #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ + #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ + #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ + #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ + #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ + #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ + #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ + #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ + #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ + #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ + #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ + #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ + #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ + #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ + #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ + #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ + #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ + #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ + #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ + #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ +/* ========================================================== BCR ========================================================== */ + #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ + #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ + #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ + #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ + #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ + #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ + #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ + #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ + #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ + #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ +/* ========================================================= RFCR ========================================================== */ + #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ + #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ + #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ + #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ + #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ + #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ + #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ +/* ========================================================= RFPCR ========================================================= */ + #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ + #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= TFCR ========================================================== */ + #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ + #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ + #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ + #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ + #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ + #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ + #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TFPCR ========================================================= */ + #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ + #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ +/* ========================================================= EIER ========================================================== */ + #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ + #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ + #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ + #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ + #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ + #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ + #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ + #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ + #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ +/* ========================================================= EIFR ========================================================== */ + #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ + #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ + #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ + #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ + #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ + #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ + #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ + #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ + #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ +/* ========================================================= RECR ========================================================== */ + #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ + #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ +/* ========================================================= TECR ========================================================== */ + #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ + #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ +/* ========================================================= ECSR ========================================================== */ + #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ + #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ + #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ + #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ + #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ + #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ + #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ + #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ + #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ +/* ========================================================= CSSR ========================================================== */ + #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ + #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ +/* ========================================================= MSSR ========================================================== */ + #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ + #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ + #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ + #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ +/* ========================================================= MSMR ========================================================== */ + #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ + #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ +/* ========================================================== TSR ========================================================== */ + #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ + #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= AFSR ========================================================== */ + #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ + #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ +/* ========================================================== TCR ========================================================== */ + #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ + #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ + #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ + #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ + #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ + #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ + #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ + #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDGCRCCFG ======================================================= */ + #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */ + #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDGLOTB ======================================================== */ + #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ + #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ + #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ + #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ + #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ + #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ + #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFDL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFDL_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFDL_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFDL_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFDL_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFDL_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFDL_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFDL_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFDL_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFDL_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFDL_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFDL_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFDL_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFDL_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFDL_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFDL_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFDL_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFDL_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFDL_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFDL_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFDL_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFDL_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFDL_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFDL_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFDL_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFDL_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFDL_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFDL_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFDL_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFDL_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFDL_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFDL_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFDL_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFDL_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFDL_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFDL_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFDL_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFDL_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFDL_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFDL_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFDL_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFDL_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFDL_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFDL_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFDL_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFDL_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ + #define R_CANFDL_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFDL_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFDL_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFDL_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFDL_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFDL_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFDL_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFDL_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFDL_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFDL_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFDL_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFDL_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFDL_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFDL_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFDL_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFDL_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFDL_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFDL_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFDL_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFDL_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFDL_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFDL_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFDL_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFDL_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFDL_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFDL_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFDL_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFDL_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFDL_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFDL_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFDL_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFDL_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFDL_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFDL_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFDL_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFDL_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFDL_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFDL_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFDL_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFDL_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFDL_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFDL_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFDL_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFDL_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFDL_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFDL_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFDL_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFDL_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFDL_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFDL_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFDL_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFDL_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFDL_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFDL_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFDL_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFDL_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFDL_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFDL_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFDL_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFDL_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFDL_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFDL_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFDL_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ + #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ + #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ + #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ + #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFDL_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ + #define R_CANFDL_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFDL_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFDL_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFDL_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFDL_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFDL_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFDL_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFDL_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFDL_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFDL_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFDL_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFDL_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFDL_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFDL_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFDL_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFDL_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFDL_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFDL_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFDL_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFDL_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFDL_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFDL_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFDL_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFDL_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFDL_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFDL_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFDL_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFDL_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFDL_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFDL_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFDL_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFDL_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFDL_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFDL_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFDL_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFDL_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFDL_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFDL_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFDL_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ===================================================== CFDGAFLIGNENT ===================================================== */ + #define R_CANFDL_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ + #define R_CANFDL_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ +/* ===================================================== CFDGAFLIGNCTR ===================================================== */ + #define R_CANFDL_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ + #define R_CANFDL_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFDL_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFDL_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFDL_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFDL_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFDL_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFDL_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFDL_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFDL_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFDL_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFDL_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFDL_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ +/* ======================================================== CRCCR1 ========================================================= */ + #define R_CRC_CRCCR1_CRCSEN_Pos (7UL) /*!< CRCSEN (Bit 7) */ + #define R_CRC_CRCCR1_CRCSEN_Msk (0x80UL) /*!< CRCSEN (Bitfield-Mask: 0x01) */ + #define R_CRC_CRCCR1_CRCSWR_Pos (6UL) /*!< CRCSWR (Bit 6) */ + #define R_CRC_CRCCR1_CRCSWR_Msk (0x40UL) /*!< CRCSWR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ + #define R_CRC_CRCDIR_CRCDIR_Pos (0UL) /*!< CRCDIR (Bit 0) */ + #define R_CRC_CRCDIR_CRCDIR_Msk (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDIR_BY ======================================================= */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos (0UL) /*!< CRCDIR_BY (Bit 0) */ + #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk (0xffUL) /*!< CRCDIR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCDOR ========================================================= */ + #define R_CRC_CRCDOR_CRCDOR_Pos (0UL) /*!< CRCDOR (Bit 0) */ + #define R_CRC_CRCDOR_CRCDOR_Msk (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CRCDOR_HA ======================================================= */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos (0UL) /*!< CRCDOR_HA (Bit 0) */ + #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk (0xffffUL) /*!< CRCDOR_HA (Bitfield-Mask: 0xffff) */ +/* ======================================================= CRCDOR_BY ======================================================= */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos (0UL) /*!< CRCDOR_BY (Bit 0) */ + #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk (0xffUL) /*!< CRCDOR_BY (Bitfield-Mask: 0xff) */ +/* ======================================================== CRCSAR ========================================================= */ + #define R_CRC_CRCSAR_CRCSA_Pos (0UL) /*!< CRCSA (Bit 0) */ + #define R_CRC_CRCSAR_CRCSA_Msk (0x3fffUL) /*!< CRCSA (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DACR ========================================================== */ + #define R_DAC_DACR_DAE_Pos (5UL) /*!< DAE (Bit 5) */ + #define R_DAC_DACR_DAE_Msk (0x20UL) /*!< DAE (Bitfield-Mask: 0x01) */ + #define R_DAC_DACR_DAOE_Pos (6UL) /*!< DAOE (Bit 6) */ + #define R_DAC_DACR_DAOE_Msk (0x40UL) /*!< DAOE (Bitfield-Mask: 0x01) */ +/* ========================================================= DADR ========================================================== */ + #define R_DAC_DADR_DADR_Pos (0UL) /*!< DADR (Bit 0) */ + #define R_DAC_DADR_DADR_Msk (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DADPR ========================================================= */ + #define R_DAC_DADPR_DPSEL_Pos (7UL) /*!< DPSEL (Bit 7) */ + #define R_DAC_DADPR_DPSEL_Msk (0x80UL) /*!< DPSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADSCR ======================================================== */ + #define R_DAC_DAADSCR_DAADST_Pos (7UL) /*!< DAADST (Bit 7) */ + #define R_DAC_DAADSCR_DAADST_Msk (0x80UL) /*!< DAADST (Bitfield-Mask: 0x01) */ +/* ======================================================= DAVREFCR ======================================================== */ + #define R_DAC_DAVREFCR_REF_Pos (0UL) /*!< REF (Bit 0) */ + #define R_DAC_DAVREFCR_REF_Msk (0x7UL) /*!< REF (Bitfield-Mask: 0x07) */ +/* ========================================================= DAPC ========================================================== */ + #define R_DAC_DAPC_PUMPEN_Pos (0UL) /*!< PUMPEN (Bit 0) */ + #define R_DAC_DAPC_PUMPEN_Msk (0x1UL) /*!< PUMPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAAMPCR ======================================================== */ + #define R_DAC_DAAMPCR_DAAMP_Pos (6UL) /*!< DAAMP (Bit 6) */ + #define R_DAC_DAAMPCR_DAAMP_Msk (0x40UL) /*!< DAAMP (Bitfield-Mask: 0x01) */ +/* ======================================================== DAASWCR ======================================================== */ + #define R_DAC_DAASWCR_DAASW1_Pos (7UL) /*!< DAASW1 (Bit 7) */ + #define R_DAC_DAASWCR_DAASW1_Msk (0x80UL) /*!< DAASW1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ + #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ +/* ======================================================== DAADUSR ======================================================== */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DEBUG ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DBGSTR ========================================================= */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos (28UL) /*!< CDBGPWRUPREQ (Bit 28) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos (29UL) /*!< CDBGPWRUPACK (Bit 29) */ + #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01) */ +/* ======================================================= DBGSTOPCR ======================================================= */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos (24UL) /*!< DBGSTOP_RPER (Bit 24) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk (0x1000000UL) /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos (16UL) /*!< DBGSTOP_LVD (Bit 16) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk (0x10000UL) /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos (25UL) /*!< DBGSTOP_RECCR (Bit 25) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk (0x2000000UL) /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos (0UL) /*!< DBGSTOP_IWDT (Bit 0) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk (0x1UL) /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos (1UL) /*!< DBGSTOP_WDT (Bit 1) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk (0x2UL) /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos (31UL) /*!< DBGSTOP_CPER (Bit 31) */ + #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMAST ========================================================= */ + #define R_DMA_DMAST_DMST_Pos (0UL) /*!< DMST (Bit 0) */ + #define R_DMA_DMAST_DMST_Msk (0x1UL) /*!< DMST (Bitfield-Mask: 0x01) */ +/* ======================================================== DMECHR ========================================================= */ + #define R_DMA_DMECHR_DMECH_Pos (0UL) /*!< DMECH (Bit 0) */ + #define R_DMA_DMECHR_DMECH_Msk (0x7UL) /*!< DMECH (Bitfield-Mask: 0x07) */ + #define R_DMA_DMECHR_DMECHSAM_Pos (8UL) /*!< DMECHSAM (Bit 8) */ + #define R_DMA_DMECHR_DMECHSAM_Msk (0x100UL) /*!< DMECHSAM (Bitfield-Mask: 0x01) */ + #define R_DMA_DMECHR_DMESTA_Pos (16UL) /*!< DMESTA (Bit 16) */ + #define R_DMA_DMECHR_DMESTA_Msk (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DMSAR ========================================================= */ + #define R_DMAC0_DMSAR_DMSAR_Pos (0UL) /*!< DMSAR (Bit 0) */ + #define R_DMAC0_DMSAR_DMSAR_Msk (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMDAR ========================================================= */ + #define R_DMAC0_DMDAR_DMDAR_Pos (0UL) /*!< DMDAR (Bit 0) */ + #define R_DMAC0_DMDAR_DMDAR_Msk (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCRA ========================================================= */ + #define R_DMAC0_DMCRA_DMCRAH_Pos (16UL) /*!< DMCRAH (Bit 16) */ + #define R_DMAC0_DMCRA_DMCRAH_Msk (0x3ff0000UL) /*!< DMCRAH (Bitfield-Mask: 0x3ff) */ + #define R_DMAC0_DMCRA_DMCRAL_Pos (0UL) /*!< DMCRAL (Bit 0) */ + #define R_DMAC0_DMCRA_DMCRAL_Msk (0xffffUL) /*!< DMCRAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMCRB ========================================================= */ + #define R_DMAC0_DMCRB_DMCRBL_Pos (0UL) /*!< DMCRBL (Bit 0) */ + #define R_DMAC0_DMCRB_DMCRBL_Msk (0xffffUL) /*!< DMCRBL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMCRB_DMCRBH_Pos (16UL) /*!< DMCRBH (Bit 16) */ + #define R_DMAC0_DMCRB_DMCRBH_Msk (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMTMD ========================================================= */ + #define R_DMAC0_DMTMD_MD_Pos (14UL) /*!< MD (Bit 14) */ + #define R_DMAC0_DMTMD_MD_Msk (0xc000UL) /*!< MD (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DTS_Pos (12UL) /*!< DTS (Bit 12) */ + #define R_DMAC0_DMTMD_DTS_Msk (0x3000UL) /*!< DTS (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_SZ_Pos (8UL) /*!< SZ (Bit 8) */ + #define R_DMAC0_DMTMD_SZ_Msk (0x300UL) /*!< SZ (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_DCTG_Pos (0UL) /*!< DCTG (Bit 0) */ + #define R_DMAC0_DMTMD_DCTG_Msk (0x3UL) /*!< DCTG (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMTMD_TKP_Pos (10UL) /*!< TKP (Bit 10) */ + #define R_DMAC0_DMTMD_TKP_Msk (0x400UL) /*!< TKP (Bitfield-Mask: 0x01) */ +/* ========================================================= DMINT ========================================================= */ + #define R_DMAC0_DMINT_DTIE_Pos (4UL) /*!< DTIE (Bit 4) */ + #define R_DMAC0_DMINT_DTIE_Msk (0x10UL) /*!< DTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_ESIE_Pos (3UL) /*!< ESIE (Bit 3) */ + #define R_DMAC0_DMINT_ESIE_Msk (0x8UL) /*!< ESIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_RPTIE_Pos (2UL) /*!< RPTIE (Bit 2) */ + #define R_DMAC0_DMINT_RPTIE_Msk (0x4UL) /*!< RPTIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_SARIE_Pos (1UL) /*!< SARIE (Bit 1) */ + #define R_DMAC0_DMINT_SARIE_Msk (0x2UL) /*!< SARIE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMINT_DARIE_Pos (0UL) /*!< DARIE (Bit 0) */ + #define R_DMAC0_DMINT_DARIE_Msk (0x1UL) /*!< DARIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMAMD ========================================================= */ + #define R_DMAC0_DMAMD_SM_Pos (14UL) /*!< SM (Bit 14) */ + #define R_DMAC0_DMAMD_SM_Msk (0xc000UL) /*!< SM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_SARA_Pos (8UL) /*!< SARA (Bit 8) */ + #define R_DMAC0_DMAMD_SARA_Msk (0x1f00UL) /*!< SARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DM_Pos (6UL) /*!< DM (Bit 6) */ + #define R_DMAC0_DMAMD_DM_Msk (0xc0UL) /*!< DM (Bitfield-Mask: 0x03) */ + #define R_DMAC0_DMAMD_DARA_Pos (0UL) /*!< DARA (Bit 0) */ + #define R_DMAC0_DMAMD_DARA_Msk (0x1fUL) /*!< DARA (Bitfield-Mask: 0x1f) */ + #define R_DMAC0_DMAMD_DADR_Pos (5UL) /*!< DADR (Bit 5) */ + #define R_DMAC0_DMAMD_DADR_Msk (0x20UL) /*!< DADR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMAMD_SADR_Pos (13UL) /*!< SADR (Bit 13) */ + #define R_DMAC0_DMAMD_SADR_Msk (0x2000UL) /*!< SADR (Bitfield-Mask: 0x01) */ +/* ========================================================= DMOFR ========================================================= */ + #define R_DMAC0_DMOFR_DMOFR_Pos (0UL) /*!< DMOFR (Bit 0) */ + #define R_DMAC0_DMOFR_DMOFR_Msk (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DMCNT ========================================================= */ + #define R_DMAC0_DMCNT_DTE_Pos (0UL) /*!< DTE (Bit 0) */ + #define R_DMAC0_DMCNT_DTE_Msk (0x1UL) /*!< DTE (Bitfield-Mask: 0x01) */ +/* ========================================================= DMREQ ========================================================= */ + #define R_DMAC0_DMREQ_CLRS_Pos (4UL) /*!< CLRS (Bit 4) */ + #define R_DMAC0_DMREQ_CLRS_Msk (0x10UL) /*!< CLRS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMREQ_SWREQ_Pos (0UL) /*!< SWREQ (Bit 0) */ + #define R_DMAC0_DMREQ_SWREQ_Msk (0x1UL) /*!< SWREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSTS ========================================================= */ + #define R_DMAC0_DMSTS_ACT_Pos (7UL) /*!< ACT (Bit 7) */ + #define R_DMAC0_DMSTS_ACT_Msk (0x80UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_DTIF_Pos (4UL) /*!< DTIF (Bit 4) */ + #define R_DMAC0_DMSTS_DTIF_Msk (0x10UL) /*!< DTIF (Bitfield-Mask: 0x01) */ + #define R_DMAC0_DMSTS_ESIF_Pos (0UL) /*!< ESIF (Bit 0) */ + #define R_DMAC0_DMSTS_ESIF_Msk (0x1UL) /*!< ESIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DMSRR ========================================================= */ +/* ========================================================= DMDRR ========================================================= */ +/* ========================================================= DMSBS ========================================================= */ + #define R_DMAC0_DMSBS_DMSBSL_Pos (0UL) /*!< DMSBSL (Bit 0) */ + #define R_DMAC0_DMSBS_DMSBSL_Msk (0xffffUL) /*!< DMSBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMSBS_DMSBSH_Pos (16UL) /*!< DMSBSH (Bit 16) */ + #define R_DMAC0_DMSBS_DMSBSH_Msk (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMDBS ========================================================= */ + #define R_DMAC0_DMDBS_DMDBSL_Pos (0UL) /*!< DMDBSL (Bit 0) */ + #define R_DMAC0_DMDBS_DMDBSL_Msk (0xffffUL) /*!< DMDBSL (Bitfield-Mask: 0xffff) */ + #define R_DMAC0_DMDBS_DMDBSH_Pos (16UL) /*!< DMDBSH (Bit 16) */ + #define R_DMAC0_DMDBS_DMDBSH_Msk (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff) */ +/* ========================================================= DMBWR ========================================================= */ + #define R_DMAC0_DMBWR_BWE_Pos (0UL) /*!< BWE (Bit 0) */ + #define R_DMAC0_DMBWR_BWE_Msk (0x1UL) /*!< BWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DTCCR ========================================================= */ + #define R_DTC_DTCCR_RRS_Pos (4UL) /*!< RRS (Bit 4) */ + #define R_DTC_DTCCR_RRS_Msk (0x10UL) /*!< RRS (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCVBR ========================================================= */ + #define R_DTC_DTCVBR_DTCVBR_Pos (0UL) /*!< DTCVBR (Bit 0) */ + #define R_DTC_DTCVBR_DTCVBR_Msk (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DTCST ========================================================= */ + #define R_DTC_DTCST_DTCST_Pos (0UL) /*!< DTCST (Bit 0) */ + #define R_DTC_DTCST_DTCST_Msk (0x1UL) /*!< DTCST (Bitfield-Mask: 0x01) */ +/* ======================================================== DTCSTS ========================================================= */ + #define R_DTC_DTCSTS_ACT_Pos (15UL) /*!< ACT (Bit 15) */ + #define R_DTC_DTCSTS_ACT_Msk (0x8000UL) /*!< ACT (Bitfield-Mask: 0x01) */ + #define R_DTC_DTCSTS_VECN_Pos (0UL) /*!< VECN (Bit 0) */ + #define R_DTC_DTCSTS_VECN_Msk (0xffUL) /*!< VECN (Bitfield-Mask: 0xff) */ +/* ======================================================= DTCCR_SEC ======================================================= */ + #define R_DTC_DTCCR_SEC_RRSS_Pos (4UL) /*!< RRSS (Bit 4) */ + #define R_DTC_DTCCR_SEC_RRSS_Msk (0x10UL) /*!< RRSS (Bitfield-Mask: 0x01) */ +/* ====================================================== DTCVBR_SEC ======================================================= */ +/* ========================================================= DTEVR ========================================================= */ + #define R_DTC_DTEVR_DTEV_Pos (0UL) /*!< DTEV (Bit 0) */ + #define R_DTC_DTEVR_DTEV_Msk (0xffUL) /*!< DTEV (Bitfield-Mask: 0xff) */ + #define R_DTC_DTEVR_DTEVSAM_Pos (8UL) /*!< DTEVSAM (Bit 8) */ + #define R_DTC_DTEVR_DTEVSAM_Msk (0x100UL) /*!< DTEVSAM (Bitfield-Mask: 0x01) */ + #define R_DTC_DTEVR_DTESTA_Pos (16UL) /*!< DTESTA (Bit 16) */ + #define R_DTC_DTEVR_DTESTA_Msk (0x10000UL) /*!< DTESTA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELCR ========================================================== */ + #define R_ELC_ELCR_ELCON_Pos (7UL) /*!< ELCON (Bit 7) */ + #define R_ELC_ELCR_ELCON_Msk (0x80UL) /*!< ELCON (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARA ======================================================== */ + #define R_ELC_ELCSARA_ELCR_Pos (0UL) /*!< ELCR (Bit 0) */ + #define R_ELC_ELCSARA_ELCR_Msk (0x1UL) /*!< ELCR (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR0_Pos (1UL) /*!< ELSEGR0 (Bit 1) */ + #define R_ELC_ELCSARA_ELSEGR0_Msk (0x2UL) /*!< ELSEGR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARA_ELSEGR1_Pos (2UL) /*!< ELSEGR1 (Bit 2) */ + #define R_ELC_ELCSARA_ELSEGR1_Msk (0x4UL) /*!< ELSEGR1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELCSARB ======================================================== */ + #define R_ELC_ELCSARB_ELSR0_Pos (0UL) /*!< ELSR0 (Bit 0) */ + #define R_ELC_ELCSARB_ELSR0_Msk (0x1UL) /*!< ELSR0 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR1_Pos (1UL) /*!< ELSR1 (Bit 1) */ + #define R_ELC_ELCSARB_ELSR1_Msk (0x2UL) /*!< ELSR1 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR2_Pos (2UL) /*!< ELSR2 (Bit 2) */ + #define R_ELC_ELCSARB_ELSR2_Msk (0x4UL) /*!< ELSR2 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR3_Pos (3UL) /*!< ELSR3 (Bit 3) */ + #define R_ELC_ELCSARB_ELSR3_Msk (0x8UL) /*!< ELSR3 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR4_Pos (4UL) /*!< ELSR4 (Bit 4) */ + #define R_ELC_ELCSARB_ELSR4_Msk (0x10UL) /*!< ELSR4 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR5_Pos (5UL) /*!< ELSR5 (Bit 5) */ + #define R_ELC_ELCSARB_ELSR5_Msk (0x20UL) /*!< ELSR5 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR6_Pos (6UL) /*!< ELSR6 (Bit 6) */ + #define R_ELC_ELCSARB_ELSR6_Msk (0x40UL) /*!< ELSR6 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR7_Pos (7UL) /*!< ELSR7 (Bit 7) */ + #define R_ELC_ELCSARB_ELSR7_Msk (0x80UL) /*!< ELSR7 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR8_Pos (8UL) /*!< ELSR8 (Bit 8) */ + #define R_ELC_ELCSARB_ELSR8_Msk (0x100UL) /*!< ELSR8 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR9_Pos (9UL) /*!< ELSR9 (Bit 9) */ + #define R_ELC_ELCSARB_ELSR9_Msk (0x200UL) /*!< ELSR9 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR10_Pos (10UL) /*!< ELSR10 (Bit 10) */ + #define R_ELC_ELCSARB_ELSR10_Msk (0x400UL) /*!< ELSR10 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR11_Pos (11UL) /*!< ELSR11 (Bit 11) */ + #define R_ELC_ELCSARB_ELSR11_Msk (0x800UL) /*!< ELSR11 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR12_Pos (12UL) /*!< ELSR12 (Bit 12) */ + #define R_ELC_ELCSARB_ELSR12_Msk (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR13_Pos (13UL) /*!< ELSR13 (Bit 13) */ + #define R_ELC_ELCSARB_ELSR13_Msk (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR14_Pos (14UL) /*!< ELSR14 (Bit 14) */ + #define R_ELC_ELCSARB_ELSR14_Msk (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR15_Pos (15UL) /*!< ELSR15 (Bit 15) */ + #define R_ELC_ELCSARB_ELSR15_Msk (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR16_Pos (16UL) /*!< ELSR16 (Bit 16) */ + #define R_ELC_ELCSARB_ELSR16_Msk (0x10000UL) /*!< ELSR16 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR17_Pos (17UL) /*!< ELSR17 (Bit 17) */ + #define R_ELC_ELCSARB_ELSR17_Msk (0x20000UL) /*!< ELSR17 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR19_Pos (19UL) /*!< ELSR19 (Bit 19) */ + #define R_ELC_ELCSARB_ELSR19_Msk (0x80000UL) /*!< ELSR19 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR20_Pos (20UL) /*!< ELSR20 (Bit 20) */ + #define R_ELC_ELCSARB_ELSR20_Msk (0x100000UL) /*!< ELSR20 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR21_Pos (21UL) /*!< ELSR21 (Bit 21) */ + #define R_ELC_ELCSARB_ELSR21_Msk (0x200000UL) /*!< ELSR21 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR22_Pos (22UL) /*!< ELSR22 (Bit 22) */ + #define R_ELC_ELCSARB_ELSR22_Msk (0x400000UL) /*!< ELSR22 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR23_Pos (23UL) /*!< ELSR23 (Bit 23) */ + #define R_ELC_ELCSARB_ELSR23_Msk (0x800000UL) /*!< ELSR23 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR24_Pos (24UL) /*!< ELSR24 (Bit 24) */ + #define R_ELC_ELCSARB_ELSR24_Msk (0x1000000UL) /*!< ELSR24 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR28_Pos (28UL) /*!< ELSR28 (Bit 28) */ + #define R_ELC_ELCSARB_ELSR28_Msk (0x10000000UL) /*!< ELSR28 (Bitfield-Mask: 0x01) */ + #define R_ELC_ELCSARB_ELSR29_Pos (29UL) /*!< ELSR29 (Bit 29) */ + #define R_ELC_ELCSARB_ELSR29_Msk (0x20000000UL) /*!< ELSR29 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP_CMD ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== FACI_CMD16 ======================================================= */ +/* ======================================================= FACI_CMD8 ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_FACI_HP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FASTAT ========================================================= */ + #define R_FACI_HP_FASTAT_CFAE_Pos (7UL) /*!< CFAE (Bit 7) */ + #define R_FACI_HP_FASTAT_CFAE_Msk (0x80UL) /*!< CFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_CMDLK_Pos (4UL) /*!< CMDLK (Bit 4) */ + #define R_FACI_HP_FASTAT_CMDLK_Msk (0x10UL) /*!< CMDLK (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_DFAE_Pos (3UL) /*!< DFAE (Bit 3) */ + #define R_FACI_HP_FASTAT_DFAE_Msk (0x8UL) /*!< DFAE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FASTAT_ECRCT_Pos (0UL) /*!< ECRCT (Bit 0) */ + #define R_FACI_HP_FASTAT_ECRCT_Msk (0x1UL) /*!< ECRCT (Bitfield-Mask: 0x01) */ +/* ======================================================== FAEINT ========================================================= */ + #define R_FACI_HP_FAEINT_CFAEIE_Pos (7UL) /*!< CFAEIE (Bit 7) */ + #define R_FACI_HP_FAEINT_CFAEIE_Msk (0x80UL) /*!< CFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Pos (4UL) /*!< CMDLKIE (Bit 4) */ + #define R_FACI_HP_FAEINT_CMDLKIE_Msk (0x10UL) /*!< CMDLKIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_DFAEIE_Pos (3UL) /*!< DFAEIE (Bit 3) */ + #define R_FACI_HP_FAEINT_DFAEIE_Msk (0x8UL) /*!< DFAEIE (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Pos (0UL) /*!< ECRCTIE (Bit 0) */ + #define R_FACI_HP_FAEINT_ECRCTIE_Msk (0x1UL) /*!< ECRCTIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FRDYIE ========================================================= */ + #define R_FACI_HP_FRDYIE_FRDYIE_Pos (0UL) /*!< FRDYIE (Bit 0) */ + #define R_FACI_HP_FRDYIE_FRDYIE_Msk (0x1UL) /*!< FRDYIE (Bitfield-Mask: 0x01) */ +/* ======================================================== FSADDR ========================================================= */ + #define R_FACI_HP_FSADDR_FSA_Pos (0UL) /*!< FSA (Bit 0) */ + #define R_FACI_HP_FSADDR_FSA_Msk (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FEADDR ========================================================= */ + #define R_FACI_HP_FEADDR_FEA_Pos (0UL) /*!< FEA (Bit 0) */ + #define R_FACI_HP_FEADDR_FEA_Msk (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== FMEPROT ======================================================== */ + #define R_FACI_HP_FMEPROT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FMEPROT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FMEPROT_CEPROT_Pos (0UL) /*!< CEPROT (Bit 0) */ + #define R_FACI_HP_FMEPROT_CEPROT_Msk (0x1UL) /*!< CEPROT (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT0 ======================================================== */ + #define R_FACI_HP_FBPROT0_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT0_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT0_BPCN0_Pos (0UL) /*!< BPCN0 (Bit 0) */ + #define R_FACI_HP_FBPROT0_BPCN0_Msk (0x1UL) /*!< BPCN0 (Bitfield-Mask: 0x01) */ +/* ======================================================== FBPROT1 ======================================================== */ + #define R_FACI_HP_FBPROT1_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FBPROT1_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FBPROT1_BPCN1_Pos (0UL) /*!< BPCN1 (Bit 0) */ + #define R_FACI_HP_FBPROT1_BPCN1_Msk (0x1UL) /*!< BPCN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== FSTATR ========================================================= */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Pos (23UL) /*!< ILGCOMERR (Bit 23) */ + #define R_FACI_HP_FSTATR_ILGCOMERR_Msk (0x800000UL) /*!< ILGCOMERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FESETERR_Pos (22UL) /*!< FESETERR (Bit 22) */ + #define R_FACI_HP_FSTATR_FESETERR_Msk (0x400000UL) /*!< FESETERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SECERR_Pos (21UL) /*!< SECERR (Bit 21) */ + #define R_FACI_HP_FSTATR_SECERR_Msk (0x200000UL) /*!< SECERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_OTERR_Pos (20UL) /*!< OTERR (Bit 20) */ + #define R_FACI_HP_FSTATR_OTERR_Msk (0x100000UL) /*!< OTERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FRDY_Pos (15UL) /*!< FRDY (Bit 15) */ + #define R_FACI_HP_FSTATR_FRDY_Msk (0x8000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ILGLERR_Pos (14UL) /*!< ILGLERR (Bit 14) */ + #define R_FACI_HP_FSTATR_ILGLERR_Msk (0x4000UL) /*!< ILGLERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSERR_Pos (13UL) /*!< ERSERR (Bit 13) */ + #define R_FACI_HP_FSTATR_ERSERR_Msk (0x2000UL) /*!< ERSERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGERR_Pos (12UL) /*!< PRGERR (Bit 12) */ + #define R_FACI_HP_FSTATR_PRGERR_Msk (0x1000UL) /*!< PRGERR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_SUSRDY_Pos (11UL) /*!< SUSRDY (Bit 11) */ + #define R_FACI_HP_FSTATR_SUSRDY_Msk (0x800UL) /*!< SUSRDY (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_DBFULL_Pos (10UL) /*!< DBFULL (Bit 10) */ + #define R_FACI_HP_FSTATR_DBFULL_Msk (0x400UL) /*!< DBFULL (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_ERSSPD_Pos (9UL) /*!< ERSSPD (Bit 9) */ + #define R_FACI_HP_FSTATR_ERSSPD_Msk (0x200UL) /*!< ERSSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_PRGSPD_Pos (8UL) /*!< PRGSPD (Bit 8) */ + #define R_FACI_HP_FSTATR_PRGSPD_Msk (0x100UL) /*!< PRGSPD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FSTATR_FLWEERR_Pos (6UL) /*!< FLWEERR (Bit 6) */ + #define R_FACI_HP_FSTATR_FLWEERR_Msk (0x40UL) /*!< FLWEERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FENTRYR ======================================================== */ + #define R_FACI_HP_FENTRYR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FENTRYR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Pos (7UL) /*!< FENTRYD (Bit 7) */ + #define R_FACI_HP_FENTRYR_FENTRYD_Msk (0x80UL) /*!< FENTRYD (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Pos (0UL) /*!< FENTRYC (Bit 0) */ + #define R_FACI_HP_FENTRYR_FENTRYC_Msk (0x1UL) /*!< FENTRYC (Bitfield-Mask: 0x01) */ +/* ======================================================= FSUINITR ======================================================== */ + #define R_FACI_HP_FSUINITR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUINITR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUINITR_SUINIT_Pos (0UL) /*!< SUINIT (Bit 0) */ + #define R_FACI_HP_FSUINITR_SUINIT_Msk (0x1UL) /*!< SUINIT (Bitfield-Mask: 0x01) */ +/* ========================================================= FCMDR ========================================================= */ + #define R_FACI_HP_FCMDR_CMDR_Pos (8UL) /*!< CMDR (Bit 8) */ + #define R_FACI_HP_FCMDR_CMDR_Msk (0xff00UL) /*!< CMDR (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FCMDR_PCMDR_Pos (0UL) /*!< PCMDR (Bit 0) */ + #define R_FACI_HP_FCMDR_PCMDR_Msk (0xffUL) /*!< PCMDR (Bitfield-Mask: 0xff) */ +/* ======================================================== FPESTAT ======================================================== */ + #define R_FACI_HP_FPESTAT_PEERRST_Pos (0UL) /*!< PEERRST (Bit 0) */ + #define R_FACI_HP_FPESTAT_PEERRST_Msk (0xffUL) /*!< PEERRST (Bitfield-Mask: 0xff) */ +/* ======================================================== FBCCNT ========================================================= */ + #define R_FACI_HP_FBCCNT_BCDIR_Pos (0UL) /*!< BCDIR (Bit 0) */ + #define R_FACI_HP_FBCCNT_BCDIR_Msk (0x1UL) /*!< BCDIR (Bitfield-Mask: 0x01) */ +/* ======================================================== FBCSTAT ======================================================== */ + #define R_FACI_HP_FBCSTAT_BCST_Pos (0UL) /*!< BCST (Bit 0) */ + #define R_FACI_HP_FBCSTAT_BCST_Msk (0x1UL) /*!< BCST (Bitfield-Mask: 0x01) */ +/* ======================================================== FPSADDR ======================================================== */ + #define R_FACI_HP_FPSADDR_PSADR_Pos (0UL) /*!< PSADR (Bit 0) */ + #define R_FACI_HP_FPSADDR_PSADR_Msk (0x7ffffUL) /*!< PSADR (Bitfield-Mask: 0x7ffff) */ +/* ======================================================== FAWMON ========================================================= */ + #define R_FACI_HP_FAWMON_BTFLG_Pos (31UL) /*!< BTFLG (Bit 31) */ + #define R_FACI_HP_FAWMON_BTFLG_Msk (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWE_Pos (16UL) /*!< FAWE (Bit 16) */ + #define R_FACI_HP_FAWMON_FAWE_Msk (0x7ff0000UL) /*!< FAWE (Bitfield-Mask: 0x7ff) */ + #define R_FACI_HP_FAWMON_FSPR_Pos (15UL) /*!< FSPR (Bit 15) */ + #define R_FACI_HP_FAWMON_FSPR_Msk (0x8000UL) /*!< FSPR (Bitfield-Mask: 0x01) */ + #define R_FACI_HP_FAWMON_FAWS_Pos (0UL) /*!< FAWS (Bit 0) */ + #define R_FACI_HP_FAWMON_FAWS_Msk (0x7ffUL) /*!< FAWS (Bitfield-Mask: 0x7ff) */ +/* ========================================================= FCPSR ========================================================= */ + #define R_FACI_HP_FCPSR_ESUSPMD_Pos (0UL) /*!< ESUSPMD (Bit 0) */ + #define R_FACI_HP_FCPSR_ESUSPMD_Msk (0x1UL) /*!< ESUSPMD (Bitfield-Mask: 0x01) */ +/* ======================================================== FPCKAR ========================================================= */ + #define R_FACI_HP_FPCKAR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FPCKAR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FPCKAR_PCKA_Pos (0UL) /*!< PCKA (Bit 0) */ + #define R_FACI_HP_FPCKAR_PCKA_Msk (0xffUL) /*!< PCKA (Bitfield-Mask: 0xff) */ +/* ======================================================== FSUACR ========================================================= */ + #define R_FACI_HP_FSUACR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_FACI_HP_FSUACR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ + #define R_FACI_HP_FSUACR_SAS_Pos (0UL) /*!< SAS (Bit 0) */ + #define R_FACI_HP_FSUACR_SAS_Msk (0x3UL) /*!< SAS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_FCACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== FCACHEE ======================================================== */ + #define R_FCACHE_FCACHEE_FCACHEEN_Pos (0UL) /*!< FCACHEEN (Bit 0) */ + #define R_FCACHE_FCACHEE_FCACHEEN_Msk (0x1UL) /*!< FCACHEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= FCACHEIV ======================================================== */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Pos (0UL) /*!< FCACHEIV (Bit 0) */ + #define R_FCACHE_FCACHEIV_FCACHEIV_Msk (0x1UL) /*!< FCACHEIV (Bitfield-Mask: 0x01) */ +/* ========================================================= FLWT ========================================================== */ + #define R_FCACHE_FLWT_FLWT_Pos (0UL) /*!< FLWT (Bit 0) */ + #define R_FCACHE_FLWT_FLWT_Msk (0x7UL) /*!< FLWT (Bitfield-Mask: 0x07) */ +/* ========================================================= FSAR ========================================================== */ + #define R_FCACHE_FSAR_FLWTSA_Pos (0UL) /*!< FLWTSA (Bit 0) */ + #define R_FCACHE_FSAR_FLWTSA_Msk (0x1UL) /*!< FLWTSA (Bitfield-Mask: 0x01) */ + #define R_FCACHE_FSAR_FCKMHZSA_Pos (8UL) /*!< FCKMHZSA (Bit 8) */ + #define R_FCACHE_FSAR_FCKMHZSA_Msk (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT0_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT0_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_GPT0_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT0_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT0_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT0_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT0_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT0_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT0_GTSTR_CSTRT_Pos (0UL) /*!< CSTRT (Bit 0) */ + #define R_GPT0_GTSTR_CSTRT_Msk (0x1UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT0_GTSTP_CSTOP_Pos (0UL) /*!< CSTOP (Bit 0) */ + #define R_GPT0_GTSTP_CSTOP_Msk (0x1UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT0_GTCLR_CCLR_Pos (0UL) /*!< CCLR (Bit 0) */ + #define R_GPT0_GTCLR_CCLR_Msk (0x1UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT0_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT0_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSELC_Pos (16UL) /*!< SSELC (Bit 16) */ + #define R_GPT0_GTSSR_SSELC_Msk (0x10000UL) /*!< SSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAH_Pos (15UL) /*!< SSCBFAH (Bit 15) */ + #define R_GPT0_GTSSR_SSCBFAH_Msk (0x8000UL) /*!< SSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBFAL_Pos (14UL) /*!< SSCBFAL (Bit 14) */ + #define R_GPT0_GTSSR_SSCBFAL_Msk (0x4000UL) /*!< SSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAH_Pos (13UL) /*!< SSCBRAH (Bit 13) */ + #define R_GPT0_GTSSR_SSCBRAH_Msk (0x2000UL) /*!< SSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCBRAL_Pos (12UL) /*!< SSCBRAL (Bit 12) */ + #define R_GPT0_GTSSR_SSCBRAL_Msk (0x1000UL) /*!< SSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBH_Pos (11UL) /*!< SSCAFBH (Bit 11) */ + #define R_GPT0_GTSSR_SSCAFBH_Msk (0x800UL) /*!< SSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCAFBL_Pos (10UL) /*!< SSCAFBL (Bit 10) */ + #define R_GPT0_GTSSR_SSCAFBL_Msk (0x400UL) /*!< SSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBH_Pos (9UL) /*!< SSCARBH (Bit 9) */ + #define R_GPT0_GTSSR_SSCARBH_Msk (0x200UL) /*!< SSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSCARBL_Pos (8UL) /*!< SSCARBL (Bit 8) */ + #define R_GPT0_GTSSR_SSCARBL_Msk (0x100UL) /*!< SSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGF_Pos (1UL) /*!< SSGTRGF (Bit 1) */ + #define R_GPT0_GTSSR_SSGTRGF_Msk (0x2UL) /*!< SSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSSR_SSGTRGR_Pos (0UL) /*!< SSGTRGR (Bit 0) */ + #define R_GPT0_GTSSR_SSGTRGR_Msk (0x1UL) /*!< SSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT0_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT0_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSELC_Pos (16UL) /*!< PSELC (Bit 16) */ + #define R_GPT0_GTPSR_PSELC_Msk (0x10000UL) /*!< PSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAH_Pos (15UL) /*!< PSCBFAH (Bit 15) */ + #define R_GPT0_GTPSR_PSCBFAH_Msk (0x8000UL) /*!< PSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBFAL_Pos (14UL) /*!< PSCBFAL (Bit 14) */ + #define R_GPT0_GTPSR_PSCBFAL_Msk (0x4000UL) /*!< PSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAH_Pos (13UL) /*!< PSCBRAH (Bit 13) */ + #define R_GPT0_GTPSR_PSCBRAH_Msk (0x2000UL) /*!< PSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCBRAL_Pos (12UL) /*!< PSCBRAL (Bit 12) */ + #define R_GPT0_GTPSR_PSCBRAL_Msk (0x1000UL) /*!< PSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBH_Pos (11UL) /*!< PSCAFBH (Bit 11) */ + #define R_GPT0_GTPSR_PSCAFBH_Msk (0x800UL) /*!< PSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCAFBL_Pos (10UL) /*!< PSCAFBL (Bit 10) */ + #define R_GPT0_GTPSR_PSCAFBL_Msk (0x400UL) /*!< PSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBH_Pos (9UL) /*!< PSCARBH (Bit 9) */ + #define R_GPT0_GTPSR_PSCARBH_Msk (0x200UL) /*!< PSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSCARBL_Pos (8UL) /*!< PSCARBL (Bit 8) */ + #define R_GPT0_GTPSR_PSCARBL_Msk (0x100UL) /*!< PSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGF_Pos (1UL) /*!< PSGTRGF (Bit 1) */ + #define R_GPT0_GTPSR_PSGTRGF_Msk (0x2UL) /*!< PSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPSR_PSGTRGR_Pos (0UL) /*!< PSGTRGR (Bit 0) */ + #define R_GPT0_GTPSR_PSGTRGR_Msk (0x1UL) /*!< PSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT0_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT0_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CP1CCE_Pos (27UL) /*!< CP1CCE (Bit 27) */ + #define R_GPT0_GTCSR_CP1CCE_Msk (0x8000000UL) /*!< CP1CCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCMSC_Pos (24UL) /*!< CSCMSC (Bit 24) */ + #define R_GPT0_GTCSR_CSCMSC_Msk (0x7000000UL) /*!< CSCMSC (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCSR_CSELC_Pos (16UL) /*!< CSELC (Bit 16) */ + #define R_GPT0_GTCSR_CSELC_Msk (0x10000UL) /*!< CSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAH_Pos (15UL) /*!< CSCBFAH (Bit 15) */ + #define R_GPT0_GTCSR_CSCBFAH_Msk (0x8000UL) /*!< CSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBFAL_Pos (14UL) /*!< CSCBFAL (Bit 14) */ + #define R_GPT0_GTCSR_CSCBFAL_Msk (0x4000UL) /*!< CSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAH_Pos (13UL) /*!< CSCBRAH (Bit 13) */ + #define R_GPT0_GTCSR_CSCBRAH_Msk (0x2000UL) /*!< CSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCBRAL_Pos (12UL) /*!< CSCBRAL (Bit 12) */ + #define R_GPT0_GTCSR_CSCBRAL_Msk (0x1000UL) /*!< CSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBH_Pos (11UL) /*!< CSCAFBH (Bit 11) */ + #define R_GPT0_GTCSR_CSCAFBH_Msk (0x800UL) /*!< CSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCAFBL_Pos (10UL) /*!< CSCAFBL (Bit 10) */ + #define R_GPT0_GTCSR_CSCAFBL_Msk (0x400UL) /*!< CSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBH_Pos (9UL) /*!< CSCARBH (Bit 9) */ + #define R_GPT0_GTCSR_CSCARBH_Msk (0x200UL) /*!< CSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSCARBL_Pos (8UL) /*!< CSCARBL (Bit 8) */ + #define R_GPT0_GTCSR_CSCARBL_Msk (0x100UL) /*!< CSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGF_Pos (1UL) /*!< CSGTRGF (Bit 1) */ + #define R_GPT0_GTCSR_CSGTRGF_Msk (0x2UL) /*!< CSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTCSR_CSGTRGR_Pos (0UL) /*!< CSGTRGR (Bit 0) */ + #define R_GPT0_GTCSR_CSGTRGR_Msk (0x1UL) /*!< CSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT0_GTUPSR_USILVL_Pos (24UL) /*!< USILVL (Bit 24) */ + #define R_GPT0_GTUPSR_USILVL_Msk (0xf000000UL) /*!< USILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTUPSR_USELC_Pos (16UL) /*!< USELC (Bit 16) */ + #define R_GPT0_GTUPSR_USELC_Msk (0x10000UL) /*!< USELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAH_Pos (15UL) /*!< USCBFAH (Bit 15) */ + #define R_GPT0_GTUPSR_USCBFAH_Msk (0x8000UL) /*!< USCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBFAL_Pos (14UL) /*!< USCBFAL (Bit 14) */ + #define R_GPT0_GTUPSR_USCBFAL_Msk (0x4000UL) /*!< USCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAH_Pos (13UL) /*!< USCBRAH (Bit 13) */ + #define R_GPT0_GTUPSR_USCBRAH_Msk (0x2000UL) /*!< USCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCBRAL_Pos (12UL) /*!< USCBRAL (Bit 12) */ + #define R_GPT0_GTUPSR_USCBRAL_Msk (0x1000UL) /*!< USCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBH_Pos (11UL) /*!< USCAFBH (Bit 11) */ + #define R_GPT0_GTUPSR_USCAFBH_Msk (0x800UL) /*!< USCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCAFBL_Pos (10UL) /*!< USCAFBL (Bit 10) */ + #define R_GPT0_GTUPSR_USCAFBL_Msk (0x400UL) /*!< USCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBH_Pos (9UL) /*!< USCARBH (Bit 9) */ + #define R_GPT0_GTUPSR_USCARBH_Msk (0x200UL) /*!< USCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USCARBL_Pos (8UL) /*!< USCARBL (Bit 8) */ + #define R_GPT0_GTUPSR_USCARBL_Msk (0x100UL) /*!< USCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGF_Pos (1UL) /*!< USGTRGF (Bit 1) */ + #define R_GPT0_GTUPSR_USGTRGF_Msk (0x2UL) /*!< USGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUPSR_USGTRGR_Pos (0UL) /*!< USGTRGR (Bit 0) */ + #define R_GPT0_GTUPSR_USGTRGR_Msk (0x1UL) /*!< USGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT0_GTDNSR_DSILVL_Pos (24UL) /*!< DSILVL (Bit 24) */ + #define R_GPT0_GTDNSR_DSILVL_Msk (0xf000000UL) /*!< DSILVL (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTDNSR_DSELC_Pos (16UL) /*!< DSELC (Bit 16) */ + #define R_GPT0_GTDNSR_DSELC_Msk (0x10000UL) /*!< DSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAH_Pos (15UL) /*!< DSCBFAH (Bit 15) */ + #define R_GPT0_GTDNSR_DSCBFAH_Msk (0x8000UL) /*!< DSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBFAL_Pos (14UL) /*!< DSCBFAL (Bit 14) */ + #define R_GPT0_GTDNSR_DSCBFAL_Msk (0x4000UL) /*!< DSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAH_Pos (13UL) /*!< DSCBRAH (Bit 13) */ + #define R_GPT0_GTDNSR_DSCBRAH_Msk (0x2000UL) /*!< DSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCBRAL_Pos (12UL) /*!< DSCBRAL (Bit 12) */ + #define R_GPT0_GTDNSR_DSCBRAL_Msk (0x1000UL) /*!< DSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBH_Pos (11UL) /*!< DSCAFBH (Bit 11) */ + #define R_GPT0_GTDNSR_DSCAFBH_Msk (0x800UL) /*!< DSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCAFBL_Pos (10UL) /*!< DSCAFBL (Bit 10) */ + #define R_GPT0_GTDNSR_DSCAFBL_Msk (0x400UL) /*!< DSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBH_Pos (9UL) /*!< DSCARBH (Bit 9) */ + #define R_GPT0_GTDNSR_DSCARBH_Msk (0x200UL) /*!< DSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSCARBL_Pos (8UL) /*!< DSCARBL (Bit 8) */ + #define R_GPT0_GTDNSR_DSCARBL_Msk (0x100UL) /*!< DSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGF_Pos (1UL) /*!< DSGTRGF (Bit 1) */ + #define R_GPT0_GTDNSR_DSGTRGF_Msk (0x2UL) /*!< DSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDNSR_DSGTRGR_Pos (0UL) /*!< DSGTRGR (Bit 0) */ + #define R_GPT0_GTDNSR_DSGTRGR_Msk (0x1UL) /*!< DSGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT0_GTICASR_ASELC_Pos (16UL) /*!< ASELC (Bit 16) */ + #define R_GPT0_GTICASR_ASELC_Msk (0x10000UL) /*!< ASELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAH_Pos (15UL) /*!< ASCBFAH (Bit 15) */ + #define R_GPT0_GTICASR_ASCBFAH_Msk (0x8000UL) /*!< ASCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBFAL_Pos (14UL) /*!< ASCBFAL (Bit 14) */ + #define R_GPT0_GTICASR_ASCBFAL_Msk (0x4000UL) /*!< ASCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAH_Pos (13UL) /*!< ASCBRAH (Bit 13) */ + #define R_GPT0_GTICASR_ASCBRAH_Msk (0x2000UL) /*!< ASCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCBRAL_Pos (12UL) /*!< ASCBRAL (Bit 12) */ + #define R_GPT0_GTICASR_ASCBRAL_Msk (0x1000UL) /*!< ASCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBH_Pos (11UL) /*!< ASCAFBH (Bit 11) */ + #define R_GPT0_GTICASR_ASCAFBH_Msk (0x800UL) /*!< ASCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCAFBL_Pos (10UL) /*!< ASCAFBL (Bit 10) */ + #define R_GPT0_GTICASR_ASCAFBL_Msk (0x400UL) /*!< ASCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBH_Pos (9UL) /*!< ASCARBH (Bit 9) */ + #define R_GPT0_GTICASR_ASCARBH_Msk (0x200UL) /*!< ASCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASCARBL_Pos (8UL) /*!< ASCARBL (Bit 8) */ + #define R_GPT0_GTICASR_ASCARBL_Msk (0x100UL) /*!< ASCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGF_Pos (1UL) /*!< ASGTRGF (Bit 1) */ + #define R_GPT0_GTICASR_ASGTRGF_Msk (0x2UL) /*!< ASGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICASR_ASGTRGR_Pos (0UL) /*!< ASGTRGR (Bit 0) */ + #define R_GPT0_GTICASR_ASGTRGR_Msk (0x1UL) /*!< ASGTRGR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT0_GTICBSR_BSELC_Pos (16UL) /*!< BSELC (Bit 16) */ + #define R_GPT0_GTICBSR_BSELC_Msk (0x10000UL) /*!< BSELC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAH_Pos (15UL) /*!< BSCBFAH (Bit 15) */ + #define R_GPT0_GTICBSR_BSCBFAH_Msk (0x8000UL) /*!< BSCBFAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBFAL_Pos (14UL) /*!< BSCBFAL (Bit 14) */ + #define R_GPT0_GTICBSR_BSCBFAL_Msk (0x4000UL) /*!< BSCBFAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAH_Pos (13UL) /*!< BSCBRAH (Bit 13) */ + #define R_GPT0_GTICBSR_BSCBRAH_Msk (0x2000UL) /*!< BSCBRAH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCBRAL_Pos (12UL) /*!< BSCBRAL (Bit 12) */ + #define R_GPT0_GTICBSR_BSCBRAL_Msk (0x1000UL) /*!< BSCBRAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBH_Pos (11UL) /*!< BSCAFBH (Bit 11) */ + #define R_GPT0_GTICBSR_BSCAFBH_Msk (0x800UL) /*!< BSCAFBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCAFBL_Pos (10UL) /*!< BSCAFBL (Bit 10) */ + #define R_GPT0_GTICBSR_BSCAFBL_Msk (0x400UL) /*!< BSCAFBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBH_Pos (9UL) /*!< BSCARBH (Bit 9) */ + #define R_GPT0_GTICBSR_BSCARBH_Msk (0x200UL) /*!< BSCARBH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSCARBL_Pos (8UL) /*!< BSCARBL (Bit 8) */ + #define R_GPT0_GTICBSR_BSCARBL_Msk (0x100UL) /*!< BSCARBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGF_Pos (1UL) /*!< BSGTRGF (Bit 1) */ + #define R_GPT0_GTICBSR_BSGTRGF_Msk (0x2UL) /*!< BSGTRGF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTICBSR_BSGTRGR_Pos (0UL) /*!< BSGTRGR (Bit 0) */ + #define R_GPT0_GTICBSR_BSGTRGR_Msk (0x1UL) /*!< BSGTRGR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT0_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT0_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT0_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT0_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT0_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT0_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT0_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT0_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT0_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT0_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT0_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT0_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT0_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT0_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT0_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT0_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT0_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBEOCD_Pos (27UL) /*!< OBEOCD (Bit 27) */ + #define R_GPT0_GTIOR_OBEOCD_Msk (0x8000000UL) /*!< OBEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT0_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT0_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT0_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT0_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT0_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT0_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT0_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT0_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_PSYE_Pos (12UL) /*!< PSYE (Bit 12) */ + #define R_GPT0_GTIOR_PSYE_Msk (0x1000UL) /*!< PSYE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAEOCD_Pos (11UL) /*!< OAEOCD (Bit 11) */ + #define R_GPT0_GTIOR_OAEOCD_Msk (0x800UL) /*!< OAEOCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT0_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT0_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT0_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT0_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_CPSCIR_Pos (5UL) /*!< CPSCIR (Bit 5) */ + #define R_GPT0_GTIOR_CPSCIR_Msk (0x20UL) /*!< CPSCIR (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT0_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT0_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT0_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT0_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT0_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT0_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTINTAD_GTINTPC_Pos (31UL) /*!< GTINTPC (Bit 31) */ + #define R_GPT0_GTINTAD_GTINTPC_Msk (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT0_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT0_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT0_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT0_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT0_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT0_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT0_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT0_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT0_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT0_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT0_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTST_TCFPU_Pos (7UL) /*!< TCFPU (Bit 7) */ + #define R_GPT0_GTST_TCFPU_Msk (0x80UL) /*!< TCFPU (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFPO_Pos (6UL) /*!< TCFPO (Bit 6) */ + #define R_GPT0_GTST_TCFPO_Msk (0x40UL) /*!< TCFPO (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFF_Pos (5UL) /*!< TCFF (Bit 5) */ + #define R_GPT0_GTST_TCFF_Msk (0x20UL) /*!< TCFF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFE_Pos (4UL) /*!< TCFE (Bit 4) */ + #define R_GPT0_GTST_TCFE_Msk (0x10UL) /*!< TCFE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFD_Pos (3UL) /*!< TCFD (Bit 3) */ + #define R_GPT0_GTST_TCFD_Msk (0x8UL) /*!< TCFD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFC_Pos (2UL) /*!< TCFC (Bit 2) */ + #define R_GPT0_GTST_TCFC_Msk (0x4UL) /*!< TCFC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFB_Pos (1UL) /*!< TCFB (Bit 1) */ + #define R_GPT0_GTST_TCFB_Msk (0x2UL) /*!< TCFB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_TCFA_Pos (0UL) /*!< TCFA (Bit 0) */ + #define R_GPT0_GTST_TCFA_Msk (0x1UL) /*!< TCFA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTST_PCF_Pos (31UL) /*!< PCF (Bit 31) */ + #define R_GPT0_GTST_PCF_Msk (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT0_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT0_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT0_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT0_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT0_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT0_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT0_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT0_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT0_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT0_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT0_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT0_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT0_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT0_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT0_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT0_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT0_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT0_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT0_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT0_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT0_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT0_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT0_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT0_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT0_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ + #define R_GPT0_GTCNT_GTCNT_Pos (0UL) /*!< GTCNT (Bit 0) */ + #define R_GPT0_GTCNT_GTCNT_Msk (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTCCR ========================================================= */ + #define R_GPT0_GTCCR_GTCCR_Pos (0UL) /*!< GTCCR (Bit 0) */ + #define R_GPT0_GTCCR_GTCCR_Msk (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPR ========================================================== */ + #define R_GPT0_GTPR_GTPR_Pos (0UL) /*!< GTPR (Bit 0) */ + #define R_GPT0_GTPR_GTPR_Msk (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTPBR ========================================================= */ + #define R_GPT0_GTPBR_GTPBR_Pos (0UL) /*!< GTPBR (Bit 0) */ + #define R_GPT0_GTPBR_GTPBR_Msk (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTPDBR ========================================================= */ + #define R_GPT0_GTPDBR_GTPDBR_Pos (0UL) /*!< GTPDBR (Bit 0) */ + #define R_GPT0_GTPDBR_GTPDBR_Msk (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRA ======================================================== */ + #define R_GPT0_GTADTRA_GTADTRA_Pos (0UL) /*!< GTADTRA (Bit 0) */ + #define R_GPT0_GTADTRA_GTADTRA_Msk (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTADTRB ======================================================== */ + #define R_GPT0_GTADTRB_GTADTRB_Pos (0UL) /*!< GTADTRB (Bit 0) */ + #define R_GPT0_GTADTRB_GTADTRB_Msk (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRA ======================================================== */ + #define R_GPT0_GTADTBRA_GTADTBRA_Pos (0UL) /*!< GTADTBRA (Bit 0) */ + #define R_GPT0_GTADTBRA_GTADTBRA_Msk (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTBRB ======================================================== */ + #define R_GPT0_GTADTBRB_GTADTBRB_Pos (0UL) /*!< GTADTBRB (Bit 0) */ + #define R_GPT0_GTADTBRB_GTADTBRB_Msk (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRA ======================================================= */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos (0UL) /*!< GTADTDBRA (Bit 0) */ + #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= GTADTDBRB ======================================================= */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos (0UL) /*!< GTADTDBRB (Bit 0) */ + #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT0_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT0_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT0_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT0_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT0_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ + #define R_GPT0_GTDVU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDVU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDVD ========================================================= */ + #define R_GPT0_GTDVD_GTDVD_Pos (0UL) /*!< GTDVD (Bit 0) */ + #define R_GPT0_GTDVD_GTDVD_Msk (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBU ========================================================= */ + #define R_GPT0_GTDBU_GTDVU_Pos (0UL) /*!< GTDVU (Bit 0) */ + #define R_GPT0_GTDBU_GTDVU_Msk (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTDBD ========================================================= */ + #define R_GPT0_GTDBD_GTDBD_Pos (0UL) /*!< GTDBD (Bit 0) */ + #define R_GPT0_GTDBD_GTDBD_Msk (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT0_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT0_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT0_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT0_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICLF ========================================================= */ + #define R_GPT0_GTICLF_ICLFA_Pos (0UL) /*!< ICLFA (Bit 0) */ + #define R_GPT0_GTICLF_ICLFA_Msk (0x7UL) /*!< ICLFA (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELC_Pos (4UL) /*!< ICLFSELC (Bit 4) */ + #define R_GPT0_GTICLF_ICLFSELC_Msk (0x3f0UL) /*!< ICLFSELC (Bitfield-Mask: 0x3f) */ + #define R_GPT0_GTICLF_ICLFB_Pos (16UL) /*!< ICLFB (Bit 16) */ + #define R_GPT0_GTICLF_ICLFB_Msk (0x70000UL) /*!< ICLFB (Bitfield-Mask: 0x07) */ + #define R_GPT0_GTICLF_ICLFSELD_Pos (20UL) /*!< ICLFSELD (Bit 20) */ + #define R_GPT0_GTICLF_ICLFSELD_Msk (0x3f00000UL) /*!< ICLFSELD (Bitfield-Mask: 0x3f) */ +/* ========================================================= GTPC ========================================================== */ + #define R_GPT0_GTPC_PCEN_Pos (0UL) /*!< PCEN (Bit 0) */ + #define R_GPT0_GTPC_PCEN_Msk (0x1UL) /*!< PCEN (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_ASTP_Pos (8UL) /*!< ASTP (Bit 8) */ + #define R_GPT0_GTPC_ASTP_Msk (0x100UL) /*!< ASTP (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTPC_PCNT_Pos (16UL) /*!< PCNT (Bit 16) */ + #define R_GPT0_GTPC_PCNT_Msk (0xfff0000UL) /*!< PCNT (Bitfield-Mask: 0xfff) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT0_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT0_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT0_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT0_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT0_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT0_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT0_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT0_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL7_Pos (7UL) /*!< SECSEL7 (Bit 7) */ + #define R_GPT0_GTSECSR_SECSEL7_Msk (0x80UL) /*!< SECSEL7 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL8_Pos (8UL) /*!< SECSEL8 (Bit 8) */ + #define R_GPT0_GTSECSR_SECSEL8_Msk (0x100UL) /*!< SECSEL8 (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECSR_SECSEL9_Pos (9UL) /*!< SECSEL9 (Bit 9) */ + #define R_GPT0_GTSECSR_SECSEL9_Msk (0x200UL) /*!< SECSEL9 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT0_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT0_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT0_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT0_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT0_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCE_Pos (16UL) /*!< SPCE (Bit 16) */ + #define R_GPT0_GTSECR_SPCE_Msk (0x10000UL) /*!< SPCE (Bitfield-Mask: 0x01) */ + #define R_GPT0_GTSECR_SPCD_Pos (24UL) /*!< SPCD (Bit 24) */ + #define R_GPT0_GTSECR_SPCD_Msk (0x1000000UL) /*!< SPCD (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_GTCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GTCLKCR ======================================================== */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Pos (0UL) /*!< BPEN (Bit 0) */ + #define R_GPT_GTCLK_GTCLKCR_BPEN_Msk (0x1UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_ODC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= GTDLYCR1 ======================================================== */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Pos (8UL) /*!< FRANGE (Bit 8) */ + #define R_GPT_ODC_GTDLYCR1_FRANGE_Msk (0x100UL) /*!< FRANGE (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Pos (1UL) /*!< DLYRST (Bit 1) */ + #define R_GPT_ODC_GTDLYCR1_DLYRST_Msk (0x2UL) /*!< DLYRST (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Pos (0UL) /*!< DLLEN (Bit 0) */ + #define R_GPT_ODC_GTDLYCR1_DLLEN_Msk (0x1UL) /*!< DLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================= GTDLYCR2 ======================================================== */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Pos (12UL) /*!< DLYDENB (Bit 12) */ + #define R_GPT_ODC_GTDLYCR2_DLYDENB_Msk (0x1000UL) /*!< DLYDENB (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Pos (8UL) /*!< DLYEN (Bit 8) */ + #define R_GPT_ODC_GTDLYCR2_DLYEN_Msk (0x100UL) /*!< DLYEN (Bitfield-Mask: 0x01) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Pos (0UL) /*!< DLYBS (Bit 0) */ + #define R_GPT_ODC_GTDLYCR2_DLYBS_Msk (0x1UL) /*!< DLYBS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_OPS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= OPSCR ========================================================= */ + #define R_GPT_OPS_OPSCR_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_OPS_OPSCR_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_OPS_OPSCR_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GODF_Pos (26UL) /*!< GODF (Bit 26) */ + #define R_GPT_OPS_OPSCR_GODF_Msk (0x4000000UL) /*!< GODF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT_OPS_OPSCR_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT_OPS_OPSCR_ALIGN_Pos (21UL) /*!< ALIGN (Bit 21) */ + #define R_GPT_OPS_OPSCR_ALIGN_Msk (0x200000UL) /*!< ALIGN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_RV_Pos (20UL) /*!< RV (Bit 20) */ + #define R_GPT_OPS_OPSCR_RV_Msk (0x100000UL) /*!< RV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_INV_Pos (19UL) /*!< INV (Bit 19) */ + #define R_GPT_OPS_OPSCR_INV_Msk (0x80000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_N_Pos (18UL) /*!< N (Bit 18) */ + #define R_GPT_OPS_OPSCR_N_Msk (0x40000UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_P_Pos (17UL) /*!< P (Bit 17) */ + #define R_GPT_OPS_OPSCR_P_Msk (0x20000UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GPT_OPS_OPSCR_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_EN_Pos (8UL) /*!< EN (Bit 8) */ + #define R_GPT_OPS_OPSCR_EN_Msk (0x100UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_W_Pos (6UL) /*!< W (Bit 6) */ + #define R_GPT_OPS_OPSCR_W_Msk (0x40UL) /*!< W (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_V_Pos (5UL) /*!< V (Bit 5) */ + #define R_GPT_OPS_OPSCR_V_Msk (0x20UL) /*!< V (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_U_Pos (4UL) /*!< U (Bit 4) */ + #define R_GPT_OPS_OPSCR_U_Msk (0x10UL) /*!< U (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_GPT_OPS_OPSCR_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_GPT_OPS_OPSCR_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_GPT_OPS_OPSCR_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_GPT_OPS_OPSCR_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GPT_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= POEGG ========================================================= */ + #define R_GPT_POEG0_POEGG_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_GPT_POEG0_POEGG_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + #define R_GPT_POEG0_POEGG_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_GPT_POEG0_POEGG_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_GPT_POEG0_POEGG_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_GPT_POEG0_POEGG_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_CDRE_Pos (8UL) /*!< CDRE (Bit 8) */ + #define R_GPT_POEG0_POEGG_CDRE_Msk (0x100UL) /*!< CDRE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_GPT_POEG0_POEGG_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_GPT_POEG0_POEGG_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_GPT_POEG0_POEGG_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_GPT_POEG0_POEGG_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_GPT_POEG0_POEGG_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_GPT_POEG0_POEGG_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_GPT_POEG0_POEGG_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_GPT_POEG0_POEGG_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= IRQCR ========================================================= */ + #define R_ICU_IRQCR_FLTEN_Pos (7UL) /*!< FLTEN (Bit 7) */ + #define R_ICU_IRQCR_FLTEN_Msk (0x80UL) /*!< FLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IRQCR_FCLKSEL_Pos (4UL) /*!< FCLKSEL (Bit 4) */ + #define R_ICU_IRQCR_FCLKSEL_Msk (0x30UL) /*!< FCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_IRQCR_IRQMD_Pos (0UL) /*!< IRQMD (Bit 0) */ + #define R_ICU_IRQCR_IRQMD_Msk (0x3UL) /*!< IRQMD (Bitfield-Mask: 0x03) */ +/* ========================================================= NMISR ========================================================= */ + #define R_ICU_NMISR_SPEST_Pos (12UL) /*!< SPEST (Bit 12) */ + #define R_ICU_NMISR_SPEST_Msk (0x1000UL) /*!< SPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSMST_Pos (11UL) /*!< BUSMST (Bit 11) */ + #define R_ICU_NMISR_BUSMST_Msk (0x800UL) /*!< BUSMST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_BUSSST_Pos (10UL) /*!< BUSSST (Bit 10) */ + #define R_ICU_NMISR_BUSSST_Msk (0x400UL) /*!< BUSSST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RECCST_Pos (9UL) /*!< RECCST (Bit 9) */ + #define R_ICU_NMISR_RECCST_Msk (0x200UL) /*!< RECCST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_RPEST_Pos (8UL) /*!< RPEST (Bit 8) */ + #define R_ICU_NMISR_RPEST_Msk (0x100UL) /*!< RPEST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_NMIST_Pos (7UL) /*!< NMIST (Bit 7) */ + #define R_ICU_NMISR_NMIST_Msk (0x80UL) /*!< NMIST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_OSTST_Pos (6UL) /*!< OSTST (Bit 6) */ + #define R_ICU_NMISR_OSTST_Msk (0x40UL) /*!< OSTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_VBATTST_Pos (4UL) /*!< VBATTST (Bit 4) */ + #define R_ICU_NMISR_VBATTST_Msk (0x10UL) /*!< VBATTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD2ST_Pos (3UL) /*!< LVD2ST (Bit 3) */ + #define R_ICU_NMISR_LVD2ST_Msk (0x8UL) /*!< LVD2ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_LVD1ST_Pos (2UL) /*!< LVD1ST (Bit 2) */ + #define R_ICU_NMISR_LVD1ST_Msk (0x4UL) /*!< LVD1ST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_WDTST_Pos (1UL) /*!< WDTST (Bit 1) */ + #define R_ICU_NMISR_WDTST_Msk (0x2UL) /*!< WDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_IWDTST_Pos (0UL) /*!< IWDTST (Bit 0) */ + #define R_ICU_NMISR_IWDTST_Msk (0x1UL) /*!< IWDTST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_TZFST_Pos (13UL) /*!< TZFST (Bit 13) */ + #define R_ICU_NMISR_TZFST_Msk (0x2000UL) /*!< TZFST (Bitfield-Mask: 0x01) */ + #define R_ICU_NMISR_CPEST_Pos (15UL) /*!< CPEST (Bit 15) */ + #define R_ICU_NMISR_CPEST_Msk (0x8000UL) /*!< CPEST (Bitfield-Mask: 0x01) */ +/* ========================================================= NMIER ========================================================= */ + #define R_ICU_NMIER_SPEEN_Pos (12UL) /*!< SPEEN (Bit 12) */ + #define R_ICU_NMIER_SPEEN_Msk (0x1000UL) /*!< SPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSMEN_Pos (11UL) /*!< BUSMEN (Bit 11) */ + #define R_ICU_NMIER_BUSMEN_Msk (0x800UL) /*!< BUSMEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_BUSSEN_Pos (10UL) /*!< BUSSEN (Bit 10) */ + #define R_ICU_NMIER_BUSSEN_Msk (0x400UL) /*!< BUSSEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RECCEN_Pos (9UL) /*!< RECCEN (Bit 9) */ + #define R_ICU_NMIER_RECCEN_Msk (0x200UL) /*!< RECCEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_RPEEN_Pos (8UL) /*!< RPEEN (Bit 8) */ + #define R_ICU_NMIER_RPEEN_Msk (0x100UL) /*!< RPEEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_NMIEN_Pos (7UL) /*!< NMIEN (Bit 7) */ + #define R_ICU_NMIER_NMIEN_Msk (0x80UL) /*!< NMIEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_OSTEN_Pos (6UL) /*!< OSTEN (Bit 6) */ + #define R_ICU_NMIER_OSTEN_Msk (0x40UL) /*!< OSTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_VBATTEN_Pos (4UL) /*!< VBATTEN (Bit 4) */ + #define R_ICU_NMIER_VBATTEN_Msk (0x10UL) /*!< VBATTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD2EN_Pos (3UL) /*!< LVD2EN (Bit 3) */ + #define R_ICU_NMIER_LVD2EN_Msk (0x8UL) /*!< LVD2EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_LVD1EN_Pos (2UL) /*!< LVD1EN (Bit 2) */ + #define R_ICU_NMIER_LVD1EN_Msk (0x4UL) /*!< LVD1EN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_WDTEN_Pos (1UL) /*!< WDTEN (Bit 1) */ + #define R_ICU_NMIER_WDTEN_Msk (0x2UL) /*!< WDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_IWDTEN_Pos (0UL) /*!< IWDTEN (Bit 0) */ + #define R_ICU_NMIER_IWDTEN_Msk (0x1UL) /*!< IWDTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_TZFEN_Pos (13UL) /*!< TZFEN (Bit 13) */ + #define R_ICU_NMIER_TZFEN_Msk (0x2000UL) /*!< TZFEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMIER_CPEEN_Pos (15UL) /*!< CPEEN (Bit 15) */ + #define R_ICU_NMIER_CPEEN_Msk (0x8000UL) /*!< CPEEN (Bitfield-Mask: 0x01) */ +/* ======================================================== NMICLR ========================================================= */ + #define R_ICU_NMICLR_SPECLR_Pos (12UL) /*!< SPECLR (Bit 12) */ + #define R_ICU_NMICLR_SPECLR_Msk (0x1000UL) /*!< SPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSMCLR_Pos (11UL) /*!< BUSMCLR (Bit 11) */ + #define R_ICU_NMICLR_BUSMCLR_Msk (0x800UL) /*!< BUSMCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_BUSSCLR_Pos (10UL) /*!< BUSSCLR (Bit 10) */ + #define R_ICU_NMICLR_BUSSCLR_Msk (0x400UL) /*!< BUSSCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RECCCLR_Pos (9UL) /*!< RECCCLR (Bit 9) */ + #define R_ICU_NMICLR_RECCCLR_Msk (0x200UL) /*!< RECCCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_RPECLR_Pos (8UL) /*!< RPECLR (Bit 8) */ + #define R_ICU_NMICLR_RPECLR_Msk (0x100UL) /*!< RPECLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_NMICLR_Pos (7UL) /*!< NMICLR (Bit 7) */ + #define R_ICU_NMICLR_NMICLR_Msk (0x80UL) /*!< NMICLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_OSTCLR_Pos (6UL) /*!< OSTCLR (Bit 6) */ + #define R_ICU_NMICLR_OSTCLR_Msk (0x40UL) /*!< OSTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_VBATTCLR_Pos (4UL) /*!< VBATTCLR (Bit 4) */ + #define R_ICU_NMICLR_VBATTCLR_Msk (0x10UL) /*!< VBATTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD2CLR_Pos (3UL) /*!< LVD2CLR (Bit 3) */ + #define R_ICU_NMICLR_LVD2CLR_Msk (0x8UL) /*!< LVD2CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_LVD1CLR_Pos (2UL) /*!< LVD1CLR (Bit 2) */ + #define R_ICU_NMICLR_LVD1CLR_Msk (0x4UL) /*!< LVD1CLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_WDTCLR_Pos (1UL) /*!< WDTCLR (Bit 1) */ + #define R_ICU_NMICLR_WDTCLR_Msk (0x2UL) /*!< WDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_IWDTCLR_Pos (0UL) /*!< IWDTCLR (Bit 0) */ + #define R_ICU_NMICLR_IWDTCLR_Msk (0x1UL) /*!< IWDTCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_TZFCLR_Pos (13UL) /*!< TZFCLR (Bit 13) */ + #define R_ICU_NMICLR_TZFCLR_Msk (0x2000UL) /*!< TZFCLR (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICLR_CPECLR_Pos (15UL) /*!< CPECLR (Bit 15) */ + #define R_ICU_NMICLR_CPECLR_Msk (0x8000UL) /*!< CPECLR (Bitfield-Mask: 0x01) */ +/* ========================================================= NMICR ========================================================= */ + #define R_ICU_NMICR_NFLTEN_Pos (7UL) /*!< NFLTEN (Bit 7) */ + #define R_ICU_NMICR_NFLTEN_Msk (0x80UL) /*!< NFLTEN (Bitfield-Mask: 0x01) */ + #define R_ICU_NMICR_NFCLKSEL_Pos (4UL) /*!< NFCLKSEL (Bit 4) */ + #define R_ICU_NMICR_NFCLKSEL_Msk (0x30UL) /*!< NFCLKSEL (Bitfield-Mask: 0x03) */ + #define R_ICU_NMICR_NMIMD_Pos (0UL) /*!< NMIMD (Bit 0) */ + #define R_ICU_NMICR_NMIMD_Msk (0x1UL) /*!< NMIMD (Bitfield-Mask: 0x01) */ +/* ========================================================= IELSR ========================================================= */ + #define R_ICU_IELSR_DTCE_Pos (24UL) /*!< DTCE (Bit 24) */ + #define R_ICU_IELSR_DTCE_Msk (0x1000000UL) /*!< DTCE (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_IELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_IELSR_IELS_Pos (0UL) /*!< IELS (Bit 0) */ + #define R_ICU_IELSR_IELS_Msk (0x1ffUL) /*!< IELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= DELSR ========================================================= */ + #define R_ICU_DELSR_IR_Pos (16UL) /*!< IR (Bit 16) */ + #define R_ICU_DELSR_IR_Msk (0x10000UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_ICU_DELSR_DELS_Pos (0UL) /*!< DELS (Bit 0) */ + #define R_ICU_DELSR_DELS_Msk (0x1ffUL) /*!< DELS (Bitfield-Mask: 0x1ff) */ +/* ======================================================== SELSR0 ========================================================= */ + #define R_ICU_SELSR0_SELS_Pos (0UL) /*!< SELS (Bit 0) */ + #define R_ICU_SELSR0_SELS_Msk (0x1ffUL) /*!< SELS (Bitfield-Mask: 0x1ff) */ +/* ========================================================= WUPEN ========================================================= */ + #define R_ICU_WUPEN_IIC0WUPEN_Pos (31UL) /*!< IIC0WUPEN (Bit 31) */ + #define R_ICU_WUPEN_IIC0WUPEN_Msk (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Pos (30UL) /*!< AGT1CBWUPEN (Bit 30) */ + #define R_ICU_WUPEN_AGT1CBWUPEN_Msk (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Pos (29UL) /*!< AGT1CAWUPEN (Bit 29) */ + #define R_ICU_WUPEN_AGT1CAWUPEN_Msk (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Pos (28UL) /*!< AGT1UDWUPEN (Bit 28) */ + #define R_ICU_WUPEN_AGT1UDWUPEN_Msk (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBFSWUPEN_Pos (27UL) /*!< USBFSWUPEN (Bit 27) */ + #define R_ICU_WUPEN_USBFSWUPEN_Msk (0x8000000UL) /*!< USBFSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_USBHSWUPEN_Pos (26UL) /*!< USBHSWUPEN (Bit 26) */ + #define R_ICU_WUPEN_USBHSWUPEN_Msk (0x4000000UL) /*!< USBHSWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Pos (25UL) /*!< RTCPRDWUPEN (Bit 25) */ + #define R_ICU_WUPEN_RTCPRDWUPEN_Msk (0x2000000UL) /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Pos (24UL) /*!< RTCALMWUPEN (Bit 24) */ + #define R_ICU_WUPEN_RTCALMWUPEN_Msk (0x1000000UL) /*!< RTCALMWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos (23UL) /*!< ACMPLP0WUPEN (Bit 23) */ + #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk (0x800000UL) /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos (22UL) /*!< ACMPHS0WUPEN (Bit 22) */ + #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk (0x400000UL) /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_VBATTWUPEN_Pos (20UL) /*!< VBATTWUPEN (Bit 20) */ + #define R_ICU_WUPEN_VBATTWUPEN_Msk (0x100000UL) /*!< VBATTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD2WUPEN_Pos (19UL) /*!< LVD2WUPEN (Bit 19) */ + #define R_ICU_WUPEN_LVD2WUPEN_Msk (0x80000UL) /*!< LVD2WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_LVD1WUPEN_Pos (18UL) /*!< LVD1WUPEN (Bit 18) */ + #define R_ICU_WUPEN_LVD1WUPEN_Msk (0x40000UL) /*!< LVD1WUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_KEYWUPEN_Pos (17UL) /*!< KEYWUPEN (Bit 17) */ + #define R_ICU_WUPEN_KEYWUPEN_Msk (0x20000UL) /*!< KEYWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IWDTWUPEN_Pos (16UL) /*!< IWDTWUPEN (Bit 16) */ + #define R_ICU_WUPEN_IWDTWUPEN_Msk (0x10000UL) /*!< IWDTWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN_IRQWUPEN_Pos (0UL) /*!< IRQWUPEN (Bit 0) */ + #define R_ICU_WUPEN_IRQWUPEN_Msk (0x1UL) /*!< IRQWUPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== WUPEN1 ========================================================= */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos (0UL) /*!< AGT3UDWUPEN (Bit 0) */ + #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk (0x1UL) /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos (1UL) /*!< AGT3CAWUPEN (Bit 1) */ + #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk (0x2UL) /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos (2UL) /*!< AGT3CBWUPEN (Bit 2) */ + #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk (0x4UL) /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= IELEN ========================================================= */ + #define R_ICU_IELEN_IELEN_Pos (1UL) /*!< IELEN (Bit 1) */ + #define R_ICU_IELEN_IELEN_Msk (0x2UL) /*!< IELEN (Bitfield-Mask: 0x01) */ + #define R_ICU_IELEN_RTCINTEN_Pos (0UL) /*!< RTCINTEN (Bit 0) */ + #define R_ICU_IELEN_RTCINTEN_Msk (0x1UL) /*!< RTCINTEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_FMPE_Pos (7UL) /*!< FMPE (Bit 7) */ + #define R_IIC0_ICFER_FMPE_Msk (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ + #define R_IIC0_ICDRT_ICDRT_Pos (0UL) /*!< ICDRT (Bit 0) */ + #define R_IIC0_ICDRT_ICDRT_Msk (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff) */ +/* ========================================================= ICDRR ========================================================= */ + #define R_IIC0_ICDRR_ICDRR_Pos (0UL) /*!< ICDRR (Bit 0) */ + #define R_IIC0_ICDRR_ICDRR_Msk (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff) */ +/* ========================================================= ICWUR ========================================================= */ + #define R_IIC0_ICWUR_WUE_Pos (7UL) /*!< WUE (Bit 7) */ + #define R_IIC0_ICWUR_WUE_Msk (0x80UL) /*!< WUE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUIE_Pos (6UL) /*!< WUIE (Bit 6) */ + #define R_IIC0_ICWUR_WUIE_Msk (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUF_Pos (5UL) /*!< WUF (Bit 5) */ + #define R_IIC0_ICWUR_WUF_Msk (0x20UL) /*!< WUF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUACK_Pos (4UL) /*!< WUACK (Bit 4) */ + #define R_IIC0_ICWUR_WUACK_Msk (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR_WUAFA_Pos (0UL) /*!< WUAFA (Bit 0) */ + #define R_IIC0_ICWUR_WUAFA_Msk (0x1UL) /*!< WUAFA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICWUR2 ========================================================= */ + #define R_IIC0_ICWUR2_WUSYF_Pos (2UL) /*!< WUSYF (Bit 2) */ + #define R_IIC0_ICWUR2_WUSYF_Msk (0x4UL) /*!< WUSYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUASYF_Pos (1UL) /*!< WUASYF (Bit 1) */ + #define R_IIC0_ICWUR2_WUASYF_Msk (0x2UL) /*!< WUASYF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICWUR2_WUSEN_Pos (0UL) /*!< WUSEN (Bit 0) */ + #define R_IIC0_ICWUR2_WUSEN_Msk (0x1UL) /*!< WUSEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIRFA ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= IIRCPRCS ======================================================== */ + #define R_IIRFA_IIRCPRCS_CPRCS_Pos (0UL) /*!< CPRCS (Bit 0) */ + #define R_IIRFA_IIRCPRCS_CPRCS_Msk (0xffffUL) /*!< CPRCS (Bitfield-Mask: 0xffff) */ +/* ======================================================= IIRCPRCFF ======================================================= */ + #define R_IIRFA_IIRCPRCFF_CPRCFF_Pos (0UL) /*!< CPRCFF (Bit 0) */ + #define R_IIRFA_IIRCPRCFF_CPRCFF_Msk (0xffffUL) /*!< CPRCFF (Bitfield-Mask: 0xffff) */ +/* ======================================================= IIRORDYF ======================================================== */ + #define R_IIRFA_IIRORDYF_ORDYF_Pos (0UL) /*!< ORDYF (Bit 0) */ + #define R_IIRFA_IIRORDYF_ORDYF_Msk (0xffffUL) /*!< ORDYF (Bitfield-Mask: 0xffff) */ +/* ======================================================= IIRCERRF ======================================================== */ + #define R_IIRFA_IIRCERRF_CERRF_Pos (0UL) /*!< CERRF (Bit 0) */ + #define R_IIRFA_IIRCERRF_CERRF_Msk (0xffffUL) /*!< CERRF (Bitfield-Mask: 0xffff) */ +/* ======================================================= IIROPCNT ======================================================== */ + #define R_IIRFA_IIROPCNT_RND_Pos (0UL) /*!< RND (Bit 0) */ + #define R_IIRFA_IIROPCNT_RND_Msk (0x7UL) /*!< RND (Bitfield-Mask: 0x07) */ +/* ======================================================= IIRECCCNT ======================================================= */ + #define R_IIRFA_IIRECCCNT_ECCMD_Pos (0UL) /*!< ECCMD (Bit 0) */ + #define R_IIRFA_IIRECCCNT_ECCMD_Msk (0x1UL) /*!< ECCMD (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRECCCNT_ECCWBDIS_Pos (1UL) /*!< ECCWBDIS (Bit 1) */ + #define R_IIRFA_IIRECCCNT_ECCWBDIS_Msk (0x2UL) /*!< ECCWBDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= IIRECCINT ======================================================= */ + #define R_IIRFA_IIRECCINT_ESEIE_Pos (0UL) /*!< ESEIE (Bit 0) */ + #define R_IIRFA_IIRECCINT_ESEIE_Msk (0x1UL) /*!< ESEIE (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRECCINT_EDEIE_Pos (1UL) /*!< EDEIE (Bit 1) */ + #define R_IIRFA_IIRECCINT_EDEIE_Msk (0x2UL) /*!< EDEIE (Bitfield-Mask: 0x01) */ +/* ======================================================= IIRECCEF ======================================================== */ + #define R_IIRFA_IIRECCEF_ESEF_Pos (0UL) /*!< ESEF (Bit 0) */ + #define R_IIRFA_IIRECCEF_ESEF_Msk (0x1UL) /*!< ESEF (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRECCEF_EDEF_Pos (1UL) /*!< EDEF (Bit 1) */ + #define R_IIRFA_IIRECCEF_EDEF_Msk (0x2UL) /*!< EDEF (Bitfield-Mask: 0x01) */ +/* ====================================================== IIRECCEFCLR ====================================================== */ + #define R_IIRFA_IIRECCEFCLR_ESEFCLR_Pos (0UL) /*!< ESEFCLR (Bit 0) */ + #define R_IIRFA_IIRECCEFCLR_ESEFCLR_Msk (0x1UL) /*!< ESEFCLR (Bitfield-Mask: 0x01) */ + #define R_IIRFA_IIRECCEFCLR_EDEFCLR_Pos (1UL) /*!< EDEFCLR (Bit 1) */ + #define R_IIRFA_IIRECCEFCLR_EDEFCLR_Msk (0x2UL) /*!< EDEFCLR (Bitfield-Mask: 0x01) */ +/* ======================================================= IIRESEADR ======================================================= */ + #define R_IIRFA_IIRESEADR_SEADR_Pos (0UL) /*!< SEADR (Bit 0) */ + #define R_IIRFA_IIRESEADR_SEADR_Msk (0x7ffUL) /*!< SEADR (Bitfield-Mask: 0x7ff) */ +/* ======================================================= IIREDEADR ======================================================= */ + #define R_IIRFA_IIREDEADR_DEADR_Pos (0UL) /*!< DEADR (Bit 0) */ + #define R_IIRFA_IIREDEADR_DEADR_Msk (0x7ffUL) /*!< DEADR (Bitfield-Mask: 0x7ff) */ + +/* =========================================================================================================================== */ +/* ================ R_IWDT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== IWDTRR ========================================================= */ + #define R_IWDT_IWDTRR_IWDTRR_Pos (0UL) /*!< IWDTRR (Bit 0) */ + #define R_IWDT_IWDTRR_IWDTRR_Msk (0xffUL) /*!< IWDTRR (Bitfield-Mask: 0xff) */ +/* ======================================================== IWDTSR ========================================================= */ + #define R_IWDT_IWDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_IWDT_IWDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_IWDT_IWDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_IWDT_IWDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_IWDT_IWDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ R_KINT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= KRCTL ========================================================= */ + #define R_KINT_KRCTL_KRMD_Pos (7UL) /*!< KRMD (Bit 7) */ + #define R_KINT_KRCTL_KRMD_Msk (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01) */ + #define R_KINT_KRCTL_KREG_Pos (0UL) /*!< KREG (Bit 0) */ + #define R_KINT_KRCTL_KREG_Msk (0x1UL) /*!< KREG (Bitfield-Mask: 0x01) */ +/* ========================================================== KRF ========================================================== */ + #define R_KINT_KRF_KRF7_Pos (7UL) /*!< KRF7 (Bit 7) */ + #define R_KINT_KRF_KRF7_Msk (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF6_Pos (6UL) /*!< KRF6 (Bit 6) */ + #define R_KINT_KRF_KRF6_Msk (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF5_Pos (5UL) /*!< KRF5 (Bit 5) */ + #define R_KINT_KRF_KRF5_Msk (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF4_Pos (4UL) /*!< KRF4 (Bit 4) */ + #define R_KINT_KRF_KRF4_Msk (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF3_Pos (3UL) /*!< KRF3 (Bit 3) */ + #define R_KINT_KRF_KRF3_Msk (0x8UL) /*!< KRF3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF2_Pos (2UL) /*!< KRF2 (Bit 2) */ + #define R_KINT_KRF_KRF2_Msk (0x4UL) /*!< KRF2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF1_Pos (1UL) /*!< KRF1 (Bit 1) */ + #define R_KINT_KRF_KRF1_Msk (0x2UL) /*!< KRF1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRF_KRF0_Pos (0UL) /*!< KRF0 (Bit 0) */ + #define R_KINT_KRF_KRF0_Msk (0x1UL) /*!< KRF0 (Bitfield-Mask: 0x01) */ +/* ========================================================== KRM ========================================================== */ + #define R_KINT_KRM_KRM7_Pos (7UL) /*!< KRM7 (Bit 7) */ + #define R_KINT_KRM_KRM7_Msk (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM6_Pos (6UL) /*!< KRM6 (Bit 6) */ + #define R_KINT_KRM_KRM6_Msk (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM5_Pos (5UL) /*!< KRM5 (Bit 5) */ + #define R_KINT_KRM_KRM5_Msk (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM4_Pos (4UL) /*!< KRM4 (Bit 4) */ + #define R_KINT_KRM_KRM4_Msk (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM3_Pos (3UL) /*!< KRM3 (Bit 3) */ + #define R_KINT_KRM_KRM3_Msk (0x8UL) /*!< KRM3 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM2_Pos (2UL) /*!< KRM2 (Bit 2) */ + #define R_KINT_KRM_KRM2_Msk (0x4UL) /*!< KRM2 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM1_Pos (1UL) /*!< KRM1 (Bit 1) */ + #define R_KINT_KRM_KRM1_Msk (0x2UL) /*!< KRM1 (Bitfield-Mask: 0x01) */ + #define R_KINT_KRM_KRM0_Pos (0UL) /*!< KRM0 (Bit 0) */ + #define R_KINT_KRM_KRM0_Msk (0x1UL) /*!< KRM0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_I3C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRTS ========================================================== */ + #define R_I3C0_PRTS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_I3C0_PRTS_PRTMD_Msk (0x1UL) /*!< PRTMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CECTL ========================================================= */ + #define R_I3C0_CECTL_CLKE_Pos (0UL) /*!< CLKE (Bit 0) */ + #define R_I3C0_CECTL_CLKE_Msk (0x1UL) /*!< CLKE (Bitfield-Mask: 0x01) */ +/* ========================================================= BCTL ========================================================== */ + #define R_I3C0_BCTL_INCBA_Pos (0UL) /*!< INCBA (Bit 0) */ + #define R_I3C0_BCTL_INCBA_Msk (0x1UL) /*!< INCBA (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BMDS_Pos (7UL) /*!< BMDS (Bit 7) */ + #define R_I3C0_BCTL_BMDS_Msk (0x80UL) /*!< BMDS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_HJACKCTL_Pos (8UL) /*!< HJACKCTL (Bit 8) */ + #define R_I3C0_BCTL_HJACKCTL_Msk (0x100UL) /*!< HJACKCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_ABT_Pos (29UL) /*!< ABT (Bit 29) */ + #define R_I3C0_BCTL_ABT_Msk (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_RSM_Pos (30UL) /*!< RSM (Bit 30) */ + #define R_I3C0_BCTL_RSM_Msk (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCTL_BUSE_Pos (31UL) /*!< BUSE (Bit 31) */ + #define R_I3C0_BCTL_BUSE_Msk (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSDVAD ========================================================= */ + #define R_I3C0_MSDVAD_MDYAD_Pos (16UL) /*!< MDYAD (Bit 16) */ + #define R_I3C0_MSDVAD_MDYAD_Msk (0x7f0000UL) /*!< MDYAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_MSDVAD_MDYADV_Pos (31UL) /*!< MDYADV (Bit 31) */ + #define R_I3C0_MSDVAD_MDYADV_Msk (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTCTL ========================================================= */ + #define R_I3C0_RSTCTL_RI3CRST_Pos (0UL) /*!< RI3CRST (Bit 0) */ + #define R_I3C0_RSTCTL_RI3CRST_Msk (0x1UL) /*!< RI3CRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_CMDQRST_Pos (1UL) /*!< CMDQRST (Bit 1) */ + #define R_I3C0_RSTCTL_CMDQRST_Msk (0x2UL) /*!< CMDQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSPQRST_Pos (2UL) /*!< RSPQRST (Bit 2) */ + #define R_I3C0_RSTCTL_RSPQRST_Msk (0x4UL) /*!< RSPQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_TDBRST_Pos (3UL) /*!< TDBRST (Bit 3) */ + #define R_I3C0_RSTCTL_TDBRST_Msk (0x8UL) /*!< TDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RDBRST_Pos (4UL) /*!< RDBRST (Bit 4) */ + #define R_I3C0_RSTCTL_RDBRST_Msk (0x10UL) /*!< RDBRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_IBIQRST_Pos (5UL) /*!< IBIQRST (Bit 5) */ + #define R_I3C0_RSTCTL_IBIQRST_Msk (0x20UL) /*!< IBIQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_RSQRST_Pos (6UL) /*!< RSQRST (Bit 6) */ + #define R_I3C0_RSTCTL_RSQRST_Msk (0x40UL) /*!< RSQRST (Bitfield-Mask: 0x01) */ + #define R_I3C0_RSTCTL_INTLRST_Pos (16UL) /*!< INTLRST (Bit 16) */ + #define R_I3C0_RSTCTL_INTLRST_Msk (0x10000UL) /*!< INTLRST (Bitfield-Mask: 0x01) */ +/* ========================================================= PRSST ========================================================= */ + #define R_I3C0_PRSST_CRMS_Pos (2UL) /*!< CRMS (Bit 2) */ + #define R_I3C0_PRSST_CRMS_Msk (0x4UL) /*!< CRMS (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_TRMD_Pos (4UL) /*!< TRMD (Bit 4) */ + #define R_I3C0_PRSST_TRMD_Msk (0x10UL) /*!< TRMD (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSST_PRSSTWP_Pos (7UL) /*!< PRSSTWP (Bit 7) */ + #define R_I3C0_PRSST_PRSSTWP_Msk (0x80UL) /*!< PRSSTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= INST ========================================================== */ + #define R_I3C0_INST_INEF_Pos (10UL) /*!< INEF (Bit 10) */ + #define R_I3C0_INST_INEF_Msk (0x400UL) /*!< INEF (Bitfield-Mask: 0x01) */ +/* ========================================================= INSTE ========================================================= */ + #define R_I3C0_INSTE_INEE_Pos (10UL) /*!< INEE (Bit 10) */ + #define R_I3C0_INSTE_INEE_Msk (0x400UL) /*!< INEE (Bitfield-Mask: 0x01) */ +/* ========================================================= INIE ========================================================== */ + #define R_I3C0_INIE_INEIE_Pos (10UL) /*!< INEIE (Bit 10) */ + #define R_I3C0_INIE_INEIE_Msk (0x400UL) /*!< INEIE (Bitfield-Mask: 0x01) */ +/* ======================================================== INSTFC ========================================================= */ + #define R_I3C0_INSTFC_INEFC_Pos (10UL) /*!< INEFC (Bit 10) */ + #define R_I3C0_INSTFC_INEFC_Msk (0x400UL) /*!< INEFC (Bitfield-Mask: 0x01) */ +/* ========================================================= DVCT ========================================================== */ + #define R_I3C0_DVCT_IDX_Pos (19UL) /*!< IDX (Bit 19) */ + #define R_I3C0_DVCT_IDX_Msk (0xf80000UL) /*!< IDX (Bitfield-Mask: 0x1f) */ +/* ======================================================== IBINCTL ======================================================== */ + #define R_I3C0_IBINCTL_NRHJCTL_Pos (0UL) /*!< NRHJCTL (Bit 0) */ + #define R_I3C0_IBINCTL_NRHJCTL_Msk (0x1UL) /*!< NRHJCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRMRCTL_Pos (1UL) /*!< NRMRCTL (Bit 1) */ + #define R_I3C0_IBINCTL_NRMRCTL_Msk (0x2UL) /*!< NRMRCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Pos (3UL) /*!< NRSIRCTL (Bit 3) */ + #define R_I3C0_IBINCTL_NRSIRCTL_Msk (0x8UL) /*!< NRSIRCTL (Bitfield-Mask: 0x01) */ +/* ========================================================= BFCTL ========================================================= */ + #define R_I3C0_BFCTL_MALE_Pos (0UL) /*!< MALE (Bit 0) */ + #define R_I3C0_BFCTL_MALE_Msk (0x1UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_NALE_Pos (1UL) /*!< NALE (Bit 1) */ + #define R_I3C0_BFCTL_NALE_Msk (0x2UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SALE_Pos (2UL) /*!< SALE (Bit 2) */ + #define R_I3C0_BFCTL_SALE_Msk (0x4UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SCSYNE_Pos (8UL) /*!< SCSYNE (Bit 8) */ + #define R_I3C0_BFCTL_SCSYNE_Msk (0x100UL) /*!< SCSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_SMBS_Pos (12UL) /*!< SMBS (Bit 12) */ + #define R_I3C0_BFCTL_SMBS_Msk (0x1000UL) /*!< SMBS (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_FMPE_Pos (14UL) /*!< FMPE (Bit 14) */ + #define R_I3C0_BFCTL_FMPE_Msk (0x4000UL) /*!< FMPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BFCTL_HSME_Pos (15UL) /*!< HSME (Bit 15) */ + #define R_I3C0_BFCTL_HSME_Msk (0x8000UL) /*!< HSME (Bitfield-Mask: 0x01) */ +/* ========================================================= SVCTL ========================================================= */ + #define R_I3C0_SVCTL_GCAE_Pos (0UL) /*!< GCAE (Bit 0) */ + #define R_I3C0_SVCTL_GCAE_Msk (0x1UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HSMCE_Pos (5UL) /*!< HSMCE (Bit 5) */ + #define R_I3C0_SVCTL_HSMCE_Msk (0x20UL) /*!< HSMCE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_DVIDE_Pos (6UL) /*!< DVIDE (Bit 6) */ + #define R_I3C0_SVCTL_DVIDE_Msk (0x40UL) /*!< DVIDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_HOAE_Pos (15UL) /*!< HOAE (Bit 15) */ + #define R_I3C0_SVCTL_HOAE_Msk (0x8000UL) /*!< HOAE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVCTL_SVAEn_Pos (16UL) /*!< SVAEn (Bit 16) */ + #define R_I3C0_SVCTL_SVAEn_Msk (0x10000UL) /*!< SVAEn (Bitfield-Mask: 0x01) */ +/* ======================================================= REFCKCTL ======================================================== */ + #define R_I3C0_REFCKCTL_IREFCKS_Pos (0UL) /*!< IREFCKS (Bit 0) */ + #define R_I3C0_REFCKCTL_IREFCKS_Msk (0x7UL) /*!< IREFCKS (Bitfield-Mask: 0x07) */ +/* ========================================================= STDBR ========================================================= */ + #define R_I3C0_STDBR_SBRLO_Pos (0UL) /*!< SBRLO (Bit 0) */ + #define R_I3C0_STDBR_SBRLO_Msk (0xffUL) /*!< SBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRHO_Pos (8UL) /*!< SBRHO (Bit 8) */ + #define R_I3C0_STDBR_SBRHO_Msk (0xff00UL) /*!< SBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_STDBR_SBRLP_Pos (16UL) /*!< SBRLP (Bit 16) */ + #define R_I3C0_STDBR_SBRLP_Msk (0x3f0000UL) /*!< SBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_SBRHP_Pos (24UL) /*!< SBRHP (Bit 24) */ + #define R_I3C0_STDBR_SBRHP_Msk (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_STDBR_DSBRPO_Pos (31UL) /*!< DSBRPO (Bit 31) */ + #define R_I3C0_STDBR_DSBRPO_Msk (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01) */ +/* ========================================================= EXTBR ========================================================= */ + #define R_I3C0_EXTBR_EBRLO_Pos (0UL) /*!< EBRLO (Bit 0) */ + #define R_I3C0_EXTBR_EBRLO_Msk (0xffUL) /*!< EBRLO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRHO_Pos (8UL) /*!< EBRHO (Bit 8) */ + #define R_I3C0_EXTBR_EBRHO_Msk (0xff00UL) /*!< EBRHO (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXTBR_EBRLP_Pos (16UL) /*!< EBRLP (Bit 16) */ + #define R_I3C0_EXTBR_EBRLP_Msk (0x3f0000UL) /*!< EBRLP (Bitfield-Mask: 0x3f) */ + #define R_I3C0_EXTBR_EBRHP_Pos (24UL) /*!< EBRHP (Bit 24) */ + #define R_I3C0_EXTBR_EBRHP_Msk (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f) */ +/* ======================================================== BFRECDT ======================================================== */ + #define R_I3C0_BFRECDT_FRECYC_Pos (0UL) /*!< FRECYC (Bit 0) */ + #define R_I3C0_BFRECDT_FRECYC_Msk (0x1ffUL) /*!< FRECYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BAVLCDT ======================================================== */ + #define R_I3C0_BAVLCDT_AVLCYC_Pos (0UL) /*!< AVLCYC (Bit 0) */ + #define R_I3C0_BAVLCDT_AVLCYC_Msk (0x1ffUL) /*!< AVLCYC (Bitfield-Mask: 0x1ff) */ +/* ======================================================== BIDLCDT ======================================================== */ + #define R_I3C0_BIDLCDT_IDLCYC_Pos (0UL) /*!< IDLCYC (Bit 0) */ + #define R_I3C0_BIDLCDT_IDLCYC_Msk (0x3ffffUL) /*!< IDLCYC (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== OUTCTL ========================================================= */ + #define R_I3C0_OUTCTL_SDOC_Pos (0UL) /*!< SDOC (Bit 0) */ + #define R_I3C0_OUTCTL_SDOC_Msk (0x1UL) /*!< SDOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SCOC_Pos (1UL) /*!< SCOC (Bit 1) */ + #define R_I3C0_OUTCTL_SCOC_Msk (0x2UL) /*!< SCOC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SOCWP_Pos (2UL) /*!< SOCWP (Bit 2) */ + #define R_I3C0_OUTCTL_SOCWP_Msk (0x4UL) /*!< SOCWP (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_EXCYC_Pos (4UL) /*!< EXCYC (Bit 4) */ + #define R_I3C0_OUTCTL_EXCYC_Msk (0x10UL) /*!< EXCYC (Bitfield-Mask: 0x01) */ + #define R_I3C0_OUTCTL_SDOD_Pos (8UL) /*!< SDOD (Bit 8) */ + #define R_I3C0_OUTCTL_SDOD_Msk (0x700UL) /*!< SDOD (Bitfield-Mask: 0x07) */ + #define R_I3C0_OUTCTL_SDODCS_Pos (15UL) /*!< SDODCS (Bit 15) */ + #define R_I3C0_OUTCTL_SDODCS_Msk (0x8000UL) /*!< SDODCS (Bitfield-Mask: 0x01) */ +/* ========================================================= INCTL ========================================================= */ + #define R_I3C0_INCTL_DNFS_Pos (0UL) /*!< DNFS (Bit 0) */ + #define R_I3C0_INCTL_DNFS_Msk (0xfUL) /*!< DNFS (Bitfield-Mask: 0x0f) */ + #define R_I3C0_INCTL_DNFE_Pos (4UL) /*!< DNFE (Bit 4) */ + #define R_I3C0_INCTL_DNFE_Msk (0x10UL) /*!< DNFE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMOCTL ========================================================= */ + #define R_I3C0_TMOCTL_TODTS_Pos (0UL) /*!< TODTS (Bit 0) */ + #define R_I3C0_TMOCTL_TODTS_Msk (0x3UL) /*!< TODTS (Bitfield-Mask: 0x03) */ + #define R_I3C0_TMOCTL_TOLCTL_Pos (4UL) /*!< TOLCTL (Bit 4) */ + #define R_I3C0_TMOCTL_TOLCTL_Msk (0x10UL) /*!< TOLCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOHCTL_Pos (5UL) /*!< TOHCTL (Bit 5) */ + #define R_I3C0_TMOCTL_TOHCTL_Msk (0x20UL) /*!< TOHCTL (Bitfield-Mask: 0x01) */ + #define R_I3C0_TMOCTL_TOMDS_Pos (6UL) /*!< TOMDS (Bit 6) */ + #define R_I3C0_TMOCTL_TOMDS_Msk (0xc0UL) /*!< TOMDS (Bitfield-Mask: 0x03) */ +/* ========================================================= WUCTL ========================================================= */ + #define R_I3C0_WUCTL_WUACKS_Pos (0UL) /*!< WUACKS (Bit 0) */ + #define R_I3C0_WUCTL_WUACKS_Msk (0x1UL) /*!< WUACKS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUANFS_Pos (4UL) /*!< WUANFS (Bit 4) */ + #define R_I3C0_WUCTL_WUANFS_Msk (0x10UL) /*!< WUANFS (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFSYNE_Pos (6UL) /*!< WUFSYNE (Bit 6) */ + #define R_I3C0_WUCTL_WUFSYNE_Msk (0x40UL) /*!< WUFSYNE (Bitfield-Mask: 0x01) */ + #define R_I3C0_WUCTL_WUFE_Pos (7UL) /*!< WUFE (Bit 7) */ + #define R_I3C0_WUCTL_WUFE_Msk (0x80UL) /*!< WUFE (Bitfield-Mask: 0x01) */ +/* ======================================================== ACKCTL ========================================================= */ + #define R_I3C0_ACKCTL_ACKR_Pos (0UL) /*!< ACKR (Bit 0) */ + #define R_I3C0_ACKCTL_ACKR_Msk (0x1UL) /*!< ACKR (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKT_Pos (1UL) /*!< ACKT (Bit 1) */ + #define R_I3C0_ACKCTL_ACKT_Msk (0x2UL) /*!< ACKT (Bitfield-Mask: 0x01) */ + #define R_I3C0_ACKCTL_ACKTWP_Pos (2UL) /*!< ACKTWP (Bit 2) */ + #define R_I3C0_ACKCTL_ACKTWP_Msk (0x4UL) /*!< ACKTWP (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTRCTL ======================================================== */ + #define R_I3C0_SCSTRCTL_ACKTWE_Pos (0UL) /*!< ACKTWE (Bit 0) */ + #define R_I3C0_SCSTRCTL_ACKTWE_Msk (0x1UL) /*!< ACKTWE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTRCTL_RWE_Pos (1UL) /*!< RWE (Bit 1) */ + #define R_I3C0_SCSTRCTL_RWE_Msk (0x2UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ======================================================= SCSTLCTL ======================================================== */ + #define R_I3C0_SCSTLCTL_STLCYC_Pos (0UL) /*!< STLCYC (Bit 0) */ + #define R_I3C0_SCSTLCTL_STLCYC_Msk (0xffffUL) /*!< STLCYC (Bitfield-Mask: 0xffff) */ + #define R_I3C0_SCSTLCTL_AAPE_Pos (28UL) /*!< AAPE (Bit 28) */ + #define R_I3C0_SCSTLCTL_AAPE_Msk (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_TRAPE_Pos (29UL) /*!< TRAPE (Bit 29) */ + #define R_I3C0_SCSTLCTL_TRAPE_Msk (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_PARPE_Pos (30UL) /*!< PARPE (Bit 30) */ + #define R_I3C0_SCSTLCTL_PARPE_Msk (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01) */ + #define R_I3C0_SCSTLCTL_ACKPE_Pos (31UL) /*!< ACKPE (Bit 31) */ + #define R_I3C0_SCSTLCTL_ACKPE_Msk (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01) */ +/* ======================================================== SVTDLG0 ======================================================== */ + #define R_I3C0_SVTDLG0_STDLG_Pos (16UL) /*!< STDLG (Bit 16) */ + #define R_I3C0_SVTDLG0_STDLG_Msk (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff) */ +/* ======================================================== CNDCTL ========================================================= */ + #define R_I3C0_CNDCTL_STCND_Pos (0UL) /*!< STCND (Bit 0) */ + #define R_I3C0_CNDCTL_STCND_Msk (0x1UL) /*!< STCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SRCND_Pos (1UL) /*!< SRCND (Bit 1) */ + #define R_I3C0_CNDCTL_SRCND_Msk (0x2UL) /*!< SRCND (Bitfield-Mask: 0x01) */ + #define R_I3C0_CNDCTL_SPCND_Pos (2UL) /*!< SPCND (Bit 2) */ + #define R_I3C0_CNDCTL_SPCND_Msk (0x4UL) /*!< SPCND (Bitfield-Mask: 0x01) */ +/* ======================================================== NCMDQP ========================================================= */ +/* ======================================================== NRSPQP ========================================================= */ +/* ======================================================== NTDTBP0 ======================================================== */ +/* ======================================================== NIBIQP ========================================================= */ +/* ========================================================= NRSQP ========================================================= */ +/* ======================================================== NQTHCTL ======================================================== */ + #define R_I3C0_NQTHCTL_CMDQTH_Pos (0UL) /*!< CMDQTH (Bit 0) */ + #define R_I3C0_NQTHCTL_CMDQTH_Msk (0xffUL) /*!< CMDQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_RSPQTH_Pos (8UL) /*!< RSPQTH (Bit 8) */ + #define R_I3C0_NQTHCTL_RSPQTH_Msk (0xff00UL) /*!< RSPQTH (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Pos (16UL) /*!< IBIDSSZ (Bit 16) */ + #define R_I3C0_NQTHCTL_IBIDSSZ_Msk (0xff0000UL) /*!< IBIDSSZ (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQTHCTL_IBIQTH_Pos (24UL) /*!< IBIQTH (Bit 24) */ + #define R_I3C0_NQTHCTL_IBIQTH_Msk (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff) */ +/* ======================================================= NTBTHCTL0 ======================================================= */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Pos (0UL) /*!< TXDBTH (Bit 0) */ + #define R_I3C0_NTBTHCTL0_TXDBTH_Msk (0x7UL) /*!< TXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Pos (8UL) /*!< RXDBTH (Bit 8) */ + #define R_I3C0_NTBTHCTL0_RXDBTH_Msk (0x700UL) /*!< RXDBTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Pos (16UL) /*!< TXSTTH (Bit 16) */ + #define R_I3C0_NTBTHCTL0_TXSTTH_Msk (0x70000UL) /*!< TXSTTH (Bitfield-Mask: 0x07) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Pos (24UL) /*!< RXSTTH (Bit 24) */ + #define R_I3C0_NTBTHCTL0_RXSTTH_Msk (0x7000000UL) /*!< RXSTTH (Bitfield-Mask: 0x07) */ +/* ======================================================= NRQTHCTL ======================================================== */ + #define R_I3C0_NRQTHCTL_RSQTH_Pos (0UL) /*!< RSQTH (Bit 0) */ + #define R_I3C0_NRQTHCTL_RSQTH_Msk (0xffUL) /*!< RSQTH (Bitfield-Mask: 0xff) */ +/* ========================================================== BST ========================================================== */ + #define R_I3C0_BST_STCNDDF_Pos (0UL) /*!< STCNDDF (Bit 0) */ + #define R_I3C0_BST_STCNDDF_Msk (0x1UL) /*!< STCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_SPCNDDF_Pos (1UL) /*!< SPCNDDF (Bit 1) */ + #define R_I3C0_BST_SPCNDDF_Msk (0x2UL) /*!< SPCNDDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_HDREXDF_Pos (2UL) /*!< HDREXDF (Bit 2) */ + #define R_I3C0_BST_HDREXDF_Msk (0x4UL) /*!< HDREXDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_NACKDF_Pos (4UL) /*!< NACKDF (Bit 4) */ + #define R_I3C0_BST_NACKDF_Msk (0x10UL) /*!< NACKDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TENDF_Pos (8UL) /*!< TENDF (Bit 8) */ + #define R_I3C0_BST_TENDF_Msk (0x100UL) /*!< TENDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_ALF_Pos (16UL) /*!< ALF (Bit 16) */ + #define R_I3C0_BST_ALF_Msk (0x10000UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BST_TODF_Pos (20UL) /*!< TODF (Bit 20) */ + #define R_I3C0_BST_TODF_Msk (0x100000UL) /*!< TODF (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTE ========================================================== */ + #define R_I3C0_BSTE_STCNDDE_Pos (0UL) /*!< STCNDDE (Bit 0) */ + #define R_I3C0_BSTE_STCNDDE_Msk (0x1UL) /*!< STCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_SPCNDDE_Pos (1UL) /*!< SPCNDDE (Bit 1) */ + #define R_I3C0_BSTE_SPCNDDE_Msk (0x2UL) /*!< SPCNDDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_HDREXDE_Pos (2UL) /*!< HDREXDE (Bit 2) */ + #define R_I3C0_BSTE_HDREXDE_Msk (0x4UL) /*!< HDREXDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_NACKDE_Pos (4UL) /*!< NACKDE (Bit 4) */ + #define R_I3C0_BSTE_NACKDE_Msk (0x10UL) /*!< NACKDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TENDE_Pos (8UL) /*!< TENDE (Bit 8) */ + #define R_I3C0_BSTE_TENDE_Msk (0x100UL) /*!< TENDE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_ALE_Pos (16UL) /*!< ALE (Bit 16) */ + #define R_I3C0_BSTE_ALE_Msk (0x10000UL) /*!< ALE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTE_TODE_Pos (20UL) /*!< TODE (Bit 20) */ + #define R_I3C0_BSTE_TODE_Msk (0x100000UL) /*!< TODE (Bitfield-Mask: 0x01) */ +/* ========================================================== BIE ========================================================== */ + #define R_I3C0_BIE_STCNDDIE_Pos (0UL) /*!< STCNDDIE (Bit 0) */ + #define R_I3C0_BIE_STCNDDIE_Msk (0x1UL) /*!< STCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_SPCNDDIE_Pos (1UL) /*!< SPCNDDIE (Bit 1) */ + #define R_I3C0_BIE_SPCNDDIE_Msk (0x2UL) /*!< SPCNDDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_HDREXDIE_Pos (2UL) /*!< HDREXDIE (Bit 2) */ + #define R_I3C0_BIE_HDREXDIE_Msk (0x4UL) /*!< HDREXDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_NACKDIE_Pos (4UL) /*!< NACKDIE (Bit 4) */ + #define R_I3C0_BIE_NACKDIE_Msk (0x10UL) /*!< NACKDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TENDIE_Pos (8UL) /*!< TENDIE (Bit 8) */ + #define R_I3C0_BIE_TENDIE_Msk (0x100UL) /*!< TENDIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_ALIE_Pos (16UL) /*!< ALIE (Bit 16) */ + #define R_I3C0_BIE_ALIE_Msk (0x10000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_BIE_TODIE_Pos (20UL) /*!< TODIE (Bit 20) */ + #define R_I3C0_BIE_TODIE_Msk (0x100000UL) /*!< TODIE (Bitfield-Mask: 0x01) */ +/* ========================================================= BSTFC ========================================================= */ + #define R_I3C0_BSTFC_STCNDDFC_Pos (0UL) /*!< STCNDDFC (Bit 0) */ + #define R_I3C0_BSTFC_STCNDDFC_Msk (0x1UL) /*!< STCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_SPCNDDFC_Pos (1UL) /*!< SPCNDDFC (Bit 1) */ + #define R_I3C0_BSTFC_SPCNDDFC_Msk (0x2UL) /*!< SPCNDDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_HDREXDFC_Pos (2UL) /*!< HDREXDFC (Bit 2) */ + #define R_I3C0_BSTFC_HDREXDFC_Msk (0x4UL) /*!< HDREXDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_NACKDFC_Pos (4UL) /*!< NACKDFC (Bit 4) */ + #define R_I3C0_BSTFC_NACKDFC_Msk (0x10UL) /*!< NACKDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TENDFC_Pos (8UL) /*!< TENDFC (Bit 8) */ + #define R_I3C0_BSTFC_TENDFC_Msk (0x100UL) /*!< TENDFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_ALFC_Pos (16UL) /*!< ALFC (Bit 16) */ + #define R_I3C0_BSTFC_ALFC_Msk (0x10000UL) /*!< ALFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_BSTFC_TODFC_Pos (20UL) /*!< TODFC (Bit 20) */ + #define R_I3C0_BSTFC_TODFC_Msk (0x100000UL) /*!< TODFC (Bitfield-Mask: 0x01) */ +/* ========================================================= NTST ========================================================== */ + #define R_I3C0_NTST_TDBEF0_Pos (0UL) /*!< TDBEF0 (Bit 0) */ + #define R_I3C0_NTST_TDBEF0_Msk (0x1UL) /*!< TDBEF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RDBFF0_Pos (1UL) /*!< RDBFF0 (Bit 1) */ + #define R_I3C0_NTST_RDBFF0_Msk (0x2UL) /*!< RDBFF0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_IBIQEFF_Pos (2UL) /*!< IBIQEFF (Bit 2) */ + #define R_I3C0_NTST_IBIQEFF_Msk (0x4UL) /*!< IBIQEFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_CMDQEF_Pos (3UL) /*!< CMDQEF (Bit 3) */ + #define R_I3C0_NTST_CMDQEF_Msk (0x8UL) /*!< CMDQEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSPQFF_Pos (4UL) /*!< RSPQFF (Bit 4) */ + #define R_I3C0_NTST_RSPQFF_Msk (0x10UL) /*!< RSPQFF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TABTF_Pos (5UL) /*!< TABTF (Bit 5) */ + #define R_I3C0_NTST_TABTF_Msk (0x20UL) /*!< TABTF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_TEF_Pos (9UL) /*!< TEF (Bit 9) */ + #define R_I3C0_NTST_TEF_Msk (0x200UL) /*!< TEF (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTST_RSQFF_Pos (20UL) /*!< RSQFF (Bit 20) */ + #define R_I3C0_NTST_RSQFF_Msk (0x100000UL) /*!< RSQFF (Bitfield-Mask: 0x01) */ +/* ========================================================= NTSTE ========================================================= */ + #define R_I3C0_NTSTE_TDBEE0_Pos (0UL) /*!< TDBEE0 (Bit 0) */ + #define R_I3C0_NTSTE_TDBEE0_Msk (0x1UL) /*!< TDBEE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RDBFE0_Pos (1UL) /*!< RDBFE0 (Bit 1) */ + #define R_I3C0_NTSTE_RDBFE0_Msk (0x2UL) /*!< RDBFE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_IBIQEFE_Pos (2UL) /*!< IBIQEFE (Bit 2) */ + #define R_I3C0_NTSTE_IBIQEFE_Msk (0x4UL) /*!< IBIQEFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_CMDQEE_Pos (3UL) /*!< CMDQEE (Bit 3) */ + #define R_I3C0_NTSTE_CMDQEE_Msk (0x8UL) /*!< CMDQEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSPQFE_Pos (4UL) /*!< RSPQFE (Bit 4) */ + #define R_I3C0_NTSTE_RSPQFE_Msk (0x10UL) /*!< RSPQFE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TABTE_Pos (5UL) /*!< TABTE (Bit 5) */ + #define R_I3C0_NTSTE_TABTE_Msk (0x20UL) /*!< TABTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_TEE_Pos (9UL) /*!< TEE (Bit 9) */ + #define R_I3C0_NTSTE_TEE_Msk (0x200UL) /*!< TEE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTE_RSQFE_Pos (20UL) /*!< RSQFE (Bit 20) */ + #define R_I3C0_NTSTE_RSQFE_Msk (0x100000UL) /*!< RSQFE (Bitfield-Mask: 0x01) */ +/* ========================================================= NTIE ========================================================== */ + #define R_I3C0_NTIE_TDBEIE0_Pos (0UL) /*!< TDBEIE0 (Bit 0) */ + #define R_I3C0_NTIE_TDBEIE0_Msk (0x1UL) /*!< TDBEIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RDBFIE0_Pos (1UL) /*!< RDBFIE0 (Bit 1) */ + #define R_I3C0_NTIE_RDBFIE0_Msk (0x2UL) /*!< RDBFIE0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_IBIQEFIE_Pos (2UL) /*!< IBIQEFIE (Bit 2) */ + #define R_I3C0_NTIE_IBIQEFIE_Msk (0x4UL) /*!< IBIQEFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_CMDQEIE_Pos (3UL) /*!< CMDQEIE (Bit 3) */ + #define R_I3C0_NTIE_CMDQEIE_Msk (0x8UL) /*!< CMDQEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSPQFIE_Pos (4UL) /*!< RSPQFIE (Bit 4) */ + #define R_I3C0_NTIE_RSPQFIE_Msk (0x10UL) /*!< RSPQFIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TABTIE_Pos (5UL) /*!< TABTIE (Bit 5) */ + #define R_I3C0_NTIE_TABTIE_Msk (0x20UL) /*!< TABTIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_TEIE_Pos (9UL) /*!< TEIE (Bit 9) */ + #define R_I3C0_NTIE_TEIE_Msk (0x200UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTIE_RSQFIE_Pos (20UL) /*!< RSQFIE (Bit 20) */ + #define R_I3C0_NTIE_RSQFIE_Msk (0x100000UL) /*!< RSQFIE (Bitfield-Mask: 0x01) */ +/* ======================================================== NTSTFC ========================================================= */ + #define R_I3C0_NTSTFC_TDBEFC0_Pos (0UL) /*!< TDBEFC0 (Bit 0) */ + #define R_I3C0_NTSTFC_TDBEFC0_Msk (0x1UL) /*!< TDBEFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RDBFFC0_Pos (1UL) /*!< RDBFFC0 (Bit 1) */ + #define R_I3C0_NTSTFC_RDBFFC0_Msk (0x2UL) /*!< RDBFFC0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Pos (2UL) /*!< IBIQEFFC (Bit 2) */ + #define R_I3C0_NTSTFC_IBIQEFFC_Msk (0x4UL) /*!< IBIQEFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_CMDQEFC_Pos (3UL) /*!< CMDQEFC (Bit 3) */ + #define R_I3C0_NTSTFC_CMDQEFC_Msk (0x8UL) /*!< CMDQEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSPQFFC_Pos (4UL) /*!< RSPQFFC (Bit 4) */ + #define R_I3C0_NTSTFC_RSPQFFC_Msk (0x10UL) /*!< RSPQFFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TABTFC_Pos (5UL) /*!< TABTFC (Bit 5) */ + #define R_I3C0_NTSTFC_TABTFC_Msk (0x20UL) /*!< TABTFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_TEFC_Pos (9UL) /*!< TEFC (Bit 9) */ + #define R_I3C0_NTSTFC_TEFC_Msk (0x200UL) /*!< TEFC (Bitfield-Mask: 0x01) */ + #define R_I3C0_NTSTFC_RSQFFC_Pos (20UL) /*!< RSQFFC (Bit 20) */ + #define R_I3C0_NTSTFC_RSQFFC_Msk (0x100000UL) /*!< RSQFFC (Bitfield-Mask: 0x01) */ +/* ========================================================= BCST ========================================================== */ + #define R_I3C0_BCST_BFREF_Pos (0UL) /*!< BFREF (Bit 0) */ + #define R_I3C0_BCST_BFREF_Msk (0x1UL) /*!< BFREF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BAVLF_Pos (1UL) /*!< BAVLF (Bit 1) */ + #define R_I3C0_BCST_BAVLF_Msk (0x2UL) /*!< BAVLF (Bitfield-Mask: 0x01) */ + #define R_I3C0_BCST_BIDLF_Pos (2UL) /*!< BIDLF (Bit 2) */ + #define R_I3C0_BCST_BIDLF_Msk (0x4UL) /*!< BIDLF (Bitfield-Mask: 0x01) */ +/* ========================================================= SVST ========================================================== */ + #define R_I3C0_SVST_GCAF_Pos (0UL) /*!< GCAF (Bit 0) */ + #define R_I3C0_SVST_GCAF_Msk (0x1UL) /*!< GCAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HSMCF_Pos (5UL) /*!< HSMCF (Bit 5) */ + #define R_I3C0_SVST_HSMCF_Msk (0x20UL) /*!< HSMCF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_DVIDF_Pos (6UL) /*!< DVIDF (Bit 6) */ + #define R_I3C0_SVST_DVIDF_Msk (0x40UL) /*!< DVIDF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_HOAF_Pos (15UL) /*!< HOAF (Bit 15) */ + #define R_I3C0_SVST_HOAF_Msk (0x8000UL) /*!< HOAF (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVST_SVAFn_Pos (16UL) /*!< SVAFn (Bit 16) */ + #define R_I3C0_SVST_SVAFn_Msk (0x10000UL) /*!< SVAFn (Bitfield-Mask: 0x01) */ +/* ========================================================= WUST ========================================================== */ + #define R_I3C0_WUST_WUASYNF_Pos (0UL) /*!< WUASYNF (Bit 0) */ + #define R_I3C0_WUST_WUASYNF_Msk (0x1UL) /*!< WUASYNF (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS0 ======================================================== */ + #define R_I3C0_DATBAS0_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS0_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS0_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS0_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS0_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS0_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS0_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS0_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS0_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS0_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS0_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS0_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS0_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS1 ======================================================== */ + #define R_I3C0_DATBAS1_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS1_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS1_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS1_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS1_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS1_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS1_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS1_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS1_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS1_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS1_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS1_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS1_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS2 ======================================================== */ + #define R_I3C0_DATBAS2_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS2_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS2_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS2_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS2_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS2_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS2_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS2_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS2_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS2_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS2_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS2_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS2_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================== DATBAS3 ======================================================== */ + #define R_I3C0_DATBAS3_DVSTAD_Pos (0UL) /*!< DVSTAD (Bit 0) */ + #define R_I3C0_DATBAS3_DVSTAD_Msk (0x7fUL) /*!< DVSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_DATBAS3_DVIBIPL_Pos (12UL) /*!< DVIBIPL (Bit 12) */ + #define R_I3C0_DATBAS3_DVIBIPL_Msk (0x1000UL) /*!< DVIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Pos (13UL) /*!< DVSIRRJ (Bit 13) */ + #define R_I3C0_DATBAS3_DVSIRRJ_Msk (0x2000UL) /*!< DVSIRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVMRRJ_Pos (14UL) /*!< DVMRRJ (Bit 14) */ + #define R_I3C0_DATBAS3_DVMRRJ_Msk (0x4000UL) /*!< DVMRRJ (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVIBITS_Pos (15UL) /*!< DVIBITS (Bit 15) */ + #define R_I3C0_DATBAS3_DVIBITS_Msk (0x8000UL) /*!< DVIBITS (Bitfield-Mask: 0x01) */ + #define R_I3C0_DATBAS3_DVDYAD_Pos (16UL) /*!< DVDYAD (Bit 16) */ + #define R_I3C0_DATBAS3_DVDYAD_Msk (0xff0000UL) /*!< DVDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_DATBAS3_DVNACK_Pos (29UL) /*!< DVNACK (Bit 29) */ + #define R_I3C0_DATBAS3_DVNACK_Msk (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_DATBAS3_DVTYP_Pos (31UL) /*!< DVTYP (Bit 31) */ + #define R_I3C0_DATBAS3_DVTYP_Msk (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= EXDATBAS ======================================================== */ + #define R_I3C0_EXDATBAS_EDSTAD_Pos (0UL) /*!< EDSTAD (Bit 0) */ + #define R_I3C0_EXDATBAS_EDSTAD_Msk (0x7fUL) /*!< EDSTAD (Bitfield-Mask: 0x7f) */ + #define R_I3C0_EXDATBAS_EDDYAD_Pos (16UL) /*!< EDDYAD (Bit 16) */ + #define R_I3C0_EXDATBAS_EDDYAD_Msk (0xff0000UL) /*!< EDDYAD (Bitfield-Mask: 0xff) */ + #define R_I3C0_EXDATBAS_EDNACK_Pos (29UL) /*!< EDNACK (Bit 29) */ + #define R_I3C0_EXDATBAS_EDNACK_Msk (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03) */ + #define R_I3C0_EXDATBAS_EDTYP_Pos (31UL) /*!< EDTYP (Bit 31) */ + #define R_I3C0_EXDATBAS_EDTYP_Msk (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01) */ +/* ======================================================= SDATBAS0 ======================================================== */ + #define R_I3C0_SDATBAS0_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS0_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS0_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS0_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS0_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS0_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS0_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS1 ======================================================== */ + #define R_I3C0_SDATBAS1_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS1_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS1_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS1_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS1_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS1_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS1_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================= SDATBAS2 ======================================================== */ + #define R_I3C0_SDATBAS2_SDSTAD_Pos (0UL) /*!< SDSTAD (Bit 0) */ + #define R_I3C0_SDATBAS2_SDSTAD_Msk (0x3ffUL) /*!< SDSTAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SDATBAS2_SDADLS_Pos (10UL) /*!< SDADLS (Bit 10) */ + #define R_I3C0_SDATBAS2_SDADLS_Msk (0x400UL) /*!< SDADLS (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Pos (12UL) /*!< SDIBIPL (Bit 12) */ + #define R_I3C0_SDATBAS2_SDIBIPL_Msk (0x1000UL) /*!< SDIBIPL (Bitfield-Mask: 0x01) */ + #define R_I3C0_SDATBAS2_SDDYAD_Pos (16UL) /*!< SDDYAD (Bit 16) */ + #define R_I3C0_SDATBAS2_SDDYAD_Msk (0x7f0000UL) /*!< SDDYAD (Bitfield-Mask: 0x7f) */ +/* ======================================================== MSDCT0 ========================================================= */ + #define R_I3C0_MSDCT0_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT0_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT0_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT0_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT0_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT0_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT0_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT1 ========================================================= */ + #define R_I3C0_MSDCT1_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT1_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT1_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT1_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT1_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT1_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT1_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT2 ========================================================= */ + #define R_I3C0_MSDCT2_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT2_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT2_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT2_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT2_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT2_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT2_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================== MSDCT3 ========================================================= */ + #define R_I3C0_MSDCT3_RBCR0_Pos (8UL) /*!< RBCR0 (Bit 8) */ + #define R_I3C0_MSDCT3_RBCR0_Msk (0x100UL) /*!< RBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR1_Pos (9UL) /*!< RBCR1 (Bit 9) */ + #define R_I3C0_MSDCT3_RBCR1_Msk (0x200UL) /*!< RBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR2_Pos (10UL) /*!< RBCR2 (Bit 10) */ + #define R_I3C0_MSDCT3_RBCR2_Msk (0x400UL) /*!< RBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR3_Pos (11UL) /*!< RBCR3 (Bit 11) */ + #define R_I3C0_MSDCT3_RBCR3_Msk (0x800UL) /*!< RBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_MSDCT3_RBCR76_Pos (14UL) /*!< RBCR76 (Bit 14) */ + #define R_I3C0_MSDCT3_RBCR76_Msk (0xc000UL) /*!< RBCR76 (Bitfield-Mask: 0x03) */ +/* ========================================================= SVDCT ========================================================= */ + #define R_I3C0_SVDCT_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_I3C0_SVDCT_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_I3C0_SVDCT_TBCR0_Pos (8UL) /*!< TBCR0 (Bit 8) */ + #define R_I3C0_SVDCT_TBCR0_Msk (0x100UL) /*!< TBCR0 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR1_Pos (9UL) /*!< TBCR1 (Bit 9) */ + #define R_I3C0_SVDCT_TBCR1_Msk (0x200UL) /*!< TBCR1 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR2_Pos (10UL) /*!< TBCR2 (Bit 10) */ + #define R_I3C0_SVDCT_TBCR2_Msk (0x400UL) /*!< TBCR2 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR3_Pos (11UL) /*!< TBCR3 (Bit 11) */ + #define R_I3C0_SVDCT_TBCR3_Msk (0x800UL) /*!< TBCR3 (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDCT_TBCR76_Pos (14UL) /*!< TBCR76 (Bit 14) */ + #define R_I3C0_SVDCT_TBCR76_Msk (0xc000UL) /*!< TBCR76 (Bitfield-Mask: 0x03) */ +/* ======================================================= SDCTPIDL ======================================================== */ +/* ======================================================= SDCTPIDH ======================================================== */ +/* ======================================================== SVDVAD0 ======================================================== */ + #define R_I3C0_SVDVAD0_SVAD_Pos (16UL) /*!< SVAD (Bit 16) */ + #define R_I3C0_SVDVAD0_SVAD_Msk (0x3ff0000UL) /*!< SVAD (Bitfield-Mask: 0x3ff) */ + #define R_I3C0_SVDVAD0_SADLG_Pos (27UL) /*!< SADLG (Bit 27) */ + #define R_I3C0_SVDVAD0_SADLG_Msk (0x8000000UL) /*!< SADLG (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SSTADV_Pos (30UL) /*!< SSTADV (Bit 30) */ + #define R_I3C0_SVDVAD0_SSTADV_Msk (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01) */ + #define R_I3C0_SVDVAD0_SDYADV_Pos (31UL) /*!< SDYADV (Bit 31) */ + #define R_I3C0_SVDVAD0_SDYADV_Msk (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01) */ +/* ======================================================== CSECMD ========================================================= */ + #define R_I3C0_CSECMD_SVIRQE_Pos (0UL) /*!< SVIRQE (Bit 0) */ + #define R_I3C0_CSECMD_SVIRQE_Msk (0x1UL) /*!< SVIRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_MSRQE_Pos (1UL) /*!< MSRQE (Bit 1) */ + #define R_I3C0_CSECMD_MSRQE_Msk (0x2UL) /*!< MSRQE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CSECMD_HJEVE_Pos (3UL) /*!< HJEVE (Bit 3) */ + #define R_I3C0_CSECMD_HJEVE_Msk (0x8UL) /*!< HJEVE (Bitfield-Mask: 0x01) */ +/* ======================================================== CEACTST ======================================================== */ + #define R_I3C0_CEACTST_ACTST_Pos (0UL) /*!< ACTST (Bit 0) */ + #define R_I3C0_CEACTST_ACTST_Msk (0xfUL) /*!< ACTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CMWLG ========================================================= */ + #define R_I3C0_CMWLG_MWLG_Pos (0UL) /*!< MWLG (Bit 0) */ + #define R_I3C0_CMWLG_MWLG_Msk (0xffffUL) /*!< MWLG (Bitfield-Mask: 0xffff) */ +/* ========================================================= CMRLG ========================================================= */ + #define R_I3C0_CMRLG_MRLG_Pos (0UL) /*!< MRLG (Bit 0) */ + #define R_I3C0_CMRLG_MRLG_Msk (0xffffUL) /*!< MRLG (Bitfield-Mask: 0xffff) */ + #define R_I3C0_CMRLG_IBIPSZ_Pos (16UL) /*!< IBIPSZ (Bit 16) */ + #define R_I3C0_CMRLG_IBIPSZ_Msk (0xff0000UL) /*!< IBIPSZ (Bitfield-Mask: 0xff) */ +/* ======================================================== CETSTMD ======================================================== */ + #define R_I3C0_CETSTMD_TSTMD_Pos (0UL) /*!< TSTMD (Bit 0) */ + #define R_I3C0_CETSTMD_TSTMD_Msk (0xffUL) /*!< TSTMD (Bitfield-Mask: 0xff) */ +/* ======================================================== CGDVST ========================================================= */ + #define R_I3C0_CGDVST_PNDINT_Pos (0UL) /*!< PNDINT (Bit 0) */ + #define R_I3C0_CGDVST_PNDINT_Msk (0xfUL) /*!< PNDINT (Bitfield-Mask: 0x0f) */ + #define R_I3C0_CGDVST_PRTE_Pos (5UL) /*!< PRTE (Bit 5) */ + #define R_I3C0_CGDVST_PRTE_Msk (0x20UL) /*!< PRTE (Bitfield-Mask: 0x01) */ + #define R_I3C0_CGDVST_ACTMD_Pos (6UL) /*!< ACTMD (Bit 6) */ + #define R_I3C0_CGDVST_ACTMD_Msk (0xc0UL) /*!< ACTMD (Bitfield-Mask: 0x03) */ + #define R_I3C0_CGDVST_VDRSV_Pos (8UL) /*!< VDRSV (Bit 8) */ + #define R_I3C0_CGDVST_VDRSV_Msk (0xff00UL) /*!< VDRSV (Bitfield-Mask: 0xff) */ +/* ======================================================== CMDSPW ========================================================= */ + #define R_I3C0_CMDSPW_MSWDR_Pos (0UL) /*!< MSWDR (Bit 0) */ + #define R_I3C0_CMDSPW_MSWDR_Msk (0x7UL) /*!< MSWDR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPR ========================================================= */ + #define R_I3C0_CMDSPR_MSRDR_Pos (0UL) /*!< MSRDR (Bit 0) */ + #define R_I3C0_CMDSPR_MSRDR_Msk (0x7UL) /*!< MSRDR (Bitfield-Mask: 0x07) */ + #define R_I3C0_CMDSPR_CDTTIM_Pos (3UL) /*!< CDTTIM (Bit 3) */ + #define R_I3C0_CMDSPR_CDTTIM_Msk (0x38UL) /*!< CDTTIM (Bitfield-Mask: 0x07) */ +/* ======================================================== CMDSPT ========================================================= */ + #define R_I3C0_CMDSPT_MRTTIM_Pos (0UL) /*!< MRTTIM (Bit 0) */ + #define R_I3C0_CMDSPT_MRTTIM_Msk (0xffffffUL) /*!< MRTTIM (Bitfield-Mask: 0xffffff) */ + #define R_I3C0_CMDSPT_MRTE_Pos (31UL) /*!< MRTE (Bit 31) */ + #define R_I3C0_CMDSPT_MRTE_Msk (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01) */ +/* ========================================================= CETSM ========================================================= */ + #define R_I3C0_CETSM_FREQ_Pos (8UL) /*!< FREQ (Bit 8) */ + #define R_I3C0_CETSM_FREQ_Msk (0xff00UL) /*!< FREQ (Bitfield-Mask: 0xff) */ + #define R_I3C0_CETSM_INAC_Pos (16UL) /*!< INAC (Bit 16) */ + #define R_I3C0_CETSM_INAC_Msk (0xff0000UL) /*!< INAC (Bitfield-Mask: 0xff) */ +/* ======================================================== BITCNT ========================================================= */ + #define R_I3C0_BITCNT_BCNT_Pos (0UL) /*!< BCNT (Bit 0) */ + #define R_I3C0_BITCNT_BCNT_Msk (0x1fUL) /*!< BCNT (Bitfield-Mask: 0x1f) */ + #define R_I3C0_BITCNT_BCNTWP_Pos (7UL) /*!< BCNTWP (Bit 7) */ + #define R_I3C0_BITCNT_BCNTWP_Msk (0x80UL) /*!< BCNTWP (Bitfield-Mask: 0x01) */ +/* ======================================================== NQSTLV ========================================================= */ + #define R_I3C0_NQSTLV_CMDQFLV_Pos (0UL) /*!< CMDQFLV (Bit 0) */ + #define R_I3C0_NQSTLV_CMDQFLV_Msk (0xffUL) /*!< CMDQFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_RSPQLV_Pos (8UL) /*!< RSPQLV (Bit 8) */ + #define R_I3C0_NQSTLV_RSPQLV_Msk (0xff00UL) /*!< RSPQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBIQLV_Pos (16UL) /*!< IBIQLV (Bit 16) */ + #define R_I3C0_NQSTLV_IBIQLV_Msk (0xff0000UL) /*!< IBIQLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NQSTLV_IBISCNT_Pos (24UL) /*!< IBISCNT (Bit 24) */ + #define R_I3C0_NQSTLV_IBISCNT_Msk (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f) */ +/* ======================================================= NDBSTLV0 ======================================================== */ + #define R_I3C0_NDBSTLV0_TDBFLV_Pos (0UL) /*!< TDBFLV (Bit 0) */ + #define R_I3C0_NDBSTLV0_TDBFLV_Msk (0xffUL) /*!< TDBFLV (Bitfield-Mask: 0xff) */ + #define R_I3C0_NDBSTLV0_RDBLV_Pos (8UL) /*!< RDBLV (Bit 8) */ + #define R_I3C0_NDBSTLV0_RDBLV_Msk (0xff00UL) /*!< RDBLV (Bitfield-Mask: 0xff) */ +/* ======================================================= NRSQSTLV ======================================================== */ + #define R_I3C0_NRSQSTLV_RSQLV_Pos (0UL) /*!< RSQLV (Bit 0) */ + #define R_I3C0_NRSQSTLV_RSQLV_Msk (0xffUL) /*!< RSQLV (Bitfield-Mask: 0xff) */ +/* ======================================================== PRSTDBG ======================================================== */ + #define R_I3C0_PRSTDBG_SCILV_Pos (0UL) /*!< SCILV (Bit 0) */ + #define R_I3C0_PRSTDBG_SCILV_Msk (0x1UL) /*!< SCILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDILV_Pos (1UL) /*!< SDILV (Bit 1) */ + #define R_I3C0_PRSTDBG_SDILV_Msk (0x2UL) /*!< SDILV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SCOLV_Pos (2UL) /*!< SCOLV (Bit 2) */ + #define R_I3C0_PRSTDBG_SCOLV_Msk (0x4UL) /*!< SCOLV (Bitfield-Mask: 0x01) */ + #define R_I3C0_PRSTDBG_SDOLV_Pos (3UL) /*!< SDOLV (Bit 3) */ + #define R_I3C0_PRSTDBG_SDOLV_Msk (0x8UL) /*!< SDOLV (Bitfield-Mask: 0x01) */ +/* ======================================================= MSERRCNT ======================================================== */ + #define R_I3C0_MSERRCNT_M2ECNT_Pos (0UL) /*!< M2ECNT (Bit 0) */ + #define R_I3C0_MSERRCNT_M2ECNT_Msk (0xffUL) /*!< M2ECNT (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU_SPMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MSTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== MSTPCRA ======================================================== */ + #define R_MSTP_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_MSTP_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_MSTP_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_MSTP_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_MSTP_MSTPCRB_MSTPB31_Pos (31UL) /*!< MSTPB31 (Bit 31) */ + #define R_MSTP_MSTPCRB_MSTPB31_Msk (0x80000000UL) /*!< MSTPB31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB30_Pos (30UL) /*!< MSTPB30 (Bit 30) */ + #define R_MSTP_MSTPCRB_MSTPB30_Msk (0x40000000UL) /*!< MSTPB30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB29_Pos (29UL) /*!< MSTPB29 (Bit 29) */ + #define R_MSTP_MSTPCRB_MSTPB29_Msk (0x20000000UL) /*!< MSTPB29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB28_Pos (28UL) /*!< MSTPB28 (Bit 28) */ + #define R_MSTP_MSTPCRB_MSTPB28_Msk (0x10000000UL) /*!< MSTPB28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB27_Pos (27UL) /*!< MSTPB27 (Bit 27) */ + #define R_MSTP_MSTPCRB_MSTPB27_Msk (0x8000000UL) /*!< MSTPB27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB26_Pos (26UL) /*!< MSTPB26 (Bit 26) */ + #define R_MSTP_MSTPCRB_MSTPB26_Msk (0x4000000UL) /*!< MSTPB26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB25_Pos (25UL) /*!< MSTPB25 (Bit 25) */ + #define R_MSTP_MSTPCRB_MSTPB25_Msk (0x2000000UL) /*!< MSTPB25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB24_Pos (24UL) /*!< MSTPB24 (Bit 24) */ + #define R_MSTP_MSTPCRB_MSTPB24_Msk (0x1000000UL) /*!< MSTPB24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB23_Pos (23UL) /*!< MSTPB23 (Bit 23) */ + #define R_MSTP_MSTPCRB_MSTPB23_Msk (0x800000UL) /*!< MSTPB23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB22_Pos (22UL) /*!< MSTPB22 (Bit 22) */ + #define R_MSTP_MSTPCRB_MSTPB22_Msk (0x400000UL) /*!< MSTPB22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB19_Pos (19UL) /*!< MSTPB19 (Bit 19) */ + #define R_MSTP_MSTPCRB_MSTPB19_Msk (0x80000UL) /*!< MSTPB19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB18_Pos (18UL) /*!< MSTPB18 (Bit 18) */ + #define R_MSTP_MSTPCRB_MSTPB18_Msk (0x40000UL) /*!< MSTPB18 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB15_Pos (15UL) /*!< MSTPB15 (Bit 15) */ + #define R_MSTP_MSTPCRB_MSTPB15_Msk (0x8000UL) /*!< MSTPB15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB14_Pos (14UL) /*!< MSTPB14 (Bit 14) */ + #define R_MSTP_MSTPCRB_MSTPB14_Msk (0x4000UL) /*!< MSTPB14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB13_Pos (13UL) /*!< MSTPB13 (Bit 13) */ + #define R_MSTP_MSTPCRB_MSTPB13_Msk (0x2000UL) /*!< MSTPB13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB12_Pos (12UL) /*!< MSTPB12 (Bit 12) */ + #define R_MSTP_MSTPCRB_MSTPB12_Msk (0x1000UL) /*!< MSTPB12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB11_Pos (11UL) /*!< MSTPB11 (Bit 11) */ + #define R_MSTP_MSTPCRB_MSTPB11_Msk (0x800UL) /*!< MSTPB11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB9_Pos (9UL) /*!< MSTPB9 (Bit 9) */ + #define R_MSTP_MSTPCRB_MSTPB9_Msk (0x200UL) /*!< MSTPB9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB8_Pos (8UL) /*!< MSTPB8 (Bit 8) */ + #define R_MSTP_MSTPCRB_MSTPB8_Msk (0x100UL) /*!< MSTPB8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB7_Pos (7UL) /*!< MSTPB7 (Bit 7) */ + #define R_MSTP_MSTPCRB_MSTPB7_Msk (0x80UL) /*!< MSTPB7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB6_Pos (6UL) /*!< MSTPB6 (Bit 6) */ + #define R_MSTP_MSTPCRB_MSTPB6_Msk (0x40UL) /*!< MSTPB6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB5_Pos (5UL) /*!< MSTPB5 (Bit 5) */ + #define R_MSTP_MSTPCRB_MSTPB5_Msk (0x20UL) /*!< MSTPB5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB3_Pos (3UL) /*!< MSTPB3 (Bit 3) */ + #define R_MSTP_MSTPCRB_MSTPB3_Msk (0x8UL) /*!< MSTPB3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB2_Pos (2UL) /*!< MSTPB2 (Bit 2) */ + #define R_MSTP_MSTPCRB_MSTPB2_Msk (0x4UL) /*!< MSTPB2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRB_MSTPB1_Pos (1UL) /*!< MSTPB1 (Bit 1) */ + #define R_MSTP_MSTPCRB_MSTPB1_Msk (0x2UL) /*!< MSTPB1 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_MSTP_MSTPCRC_MSTPC31_Pos (31UL) /*!< MSTPC31 (Bit 31) */ + #define R_MSTP_MSTPCRC_MSTPC31_Msk (0x80000000UL) /*!< MSTPC31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC28_Pos (28UL) /*!< MSTPC28 (Bit 28) */ + #define R_MSTP_MSTPCRC_MSTPC28_Msk (0x10000000UL) /*!< MSTPC28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC27_Pos (27UL) /*!< MSTPC27 (Bit 27) */ + #define R_MSTP_MSTPCRC_MSTPC27_Msk (0x8000000UL) /*!< MSTPC27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC21_Pos (21UL) /*!< MSTPC21 (Bit 21) */ + #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ + #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ + #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ + #define R_MSTP_MSTPCRC_MSTPC13_Msk (0x2000UL) /*!< MSTPC13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC12_Pos (12UL) /*!< MSTPC12 (Bit 12) */ + #define R_MSTP_MSTPCRC_MSTPC12_Msk (0x1000UL) /*!< MSTPC12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC11_Pos (11UL) /*!< MSTPC11 (Bit 11) */ + #define R_MSTP_MSTPCRC_MSTPC11_Msk (0x800UL) /*!< MSTPC11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC9_Pos (9UL) /*!< MSTPC9 (Bit 9) */ + #define R_MSTP_MSTPCRC_MSTPC9_Msk (0x200UL) /*!< MSTPC9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC8_Pos (8UL) /*!< MSTPC8 (Bit 8) */ + #define R_MSTP_MSTPCRC_MSTPC8_Msk (0x100UL) /*!< MSTPC8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC7_Pos (7UL) /*!< MSTPC7 (Bit 7) */ + #define R_MSTP_MSTPCRC_MSTPC7_Msk (0x80UL) /*!< MSTPC7 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC6_Pos (6UL) /*!< MSTPC6 (Bit 6) */ + #define R_MSTP_MSTPCRC_MSTPC6_Msk (0x40UL) /*!< MSTPC6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC5_Pos (5UL) /*!< MSTPC5 (Bit 5) */ + #define R_MSTP_MSTPCRC_MSTPC5_Msk (0x20UL) /*!< MSTPC5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC4_Pos (4UL) /*!< MSTPC4 (Bit 4) */ + #define R_MSTP_MSTPCRC_MSTPC4_Msk (0x10UL) /*!< MSTPC4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC3_Pos (3UL) /*!< MSTPC3 (Bit 3) */ + #define R_MSTP_MSTPCRC_MSTPC3_Msk (0x8UL) /*!< MSTPC3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC2_Pos (2UL) /*!< MSTPC2 (Bit 2) */ + #define R_MSTP_MSTPCRC_MSTPC2_Msk (0x4UL) /*!< MSTPC2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC1_Pos (1UL) /*!< MSTPC1 (Bit 1) */ + #define R_MSTP_MSTPCRC_MSTPC1_Msk (0x2UL) /*!< MSTPC1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC0_Pos (0UL) /*!< MSTPC0 (Bit 0) */ + #define R_MSTP_MSTPCRC_MSTPC0_Msk (0x1UL) /*!< MSTPC0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_MSTP_MSTPCRD_MSTPD31_Pos (31UL) /*!< MSTPD31 (Bit 31) */ + #define R_MSTP_MSTPCRD_MSTPD31_Msk (0x80000000UL) /*!< MSTPD31 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD29_Pos (29UL) /*!< MSTPD29 (Bit 29) */ + #define R_MSTP_MSTPCRD_MSTPD29_Msk (0x20000000UL) /*!< MSTPD29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD28_Pos (28UL) /*!< MSTPD28 (Bit 28) */ + #define R_MSTP_MSTPCRD_MSTPD28_Msk (0x10000000UL) /*!< MSTPD28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD27_Pos (27UL) /*!< MSTPD27 (Bit 27) */ + #define R_MSTP_MSTPCRD_MSTPD27_Msk (0x8000000UL) /*!< MSTPD27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD26_Pos (26UL) /*!< MSTPD26 (Bit 26) */ + #define R_MSTP_MSTPCRD_MSTPD26_Msk (0x4000000UL) /*!< MSTPD26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD25_Pos (25UL) /*!< MSTPD25 (Bit 25) */ + #define R_MSTP_MSTPCRD_MSTPD25_Msk (0x2000000UL) /*!< MSTPD25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD24_Pos (24UL) /*!< MSTPD24 (Bit 24) */ + #define R_MSTP_MSTPCRD_MSTPD24_Msk (0x1000000UL) /*!< MSTPD24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD23_Pos (23UL) /*!< MSTPD23 (Bit 23) */ + #define R_MSTP_MSTPCRD_MSTPD23_Msk (0x800000UL) /*!< MSTPD23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD22_Pos (22UL) /*!< MSTPD22 (Bit 22) */ + #define R_MSTP_MSTPCRD_MSTPD22_Msk (0x400000UL) /*!< MSTPD22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD20_Pos (20UL) /*!< MSTPD20 (Bit 20) */ + #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ + #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ + #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ + #define R_MSTP_MSTPCRD_MSTPD16_Msk (0x10000UL) /*!< MSTPD16 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD15_Pos (15UL) /*!< MSTPD15 (Bit 15) */ + #define R_MSTP_MSTPCRD_MSTPD15_Msk (0x8000UL) /*!< MSTPD15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD14_Pos (14UL) /*!< MSTPD14 (Bit 14) */ + #define R_MSTP_MSTPCRD_MSTPD14_Msk (0x4000UL) /*!< MSTPD14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD13_Pos (13UL) /*!< MSTPD13 (Bit 13) */ + #define R_MSTP_MSTPCRD_MSTPD13_Msk (0x2000UL) /*!< MSTPD13 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD12_Pos (12UL) /*!< MSTPD12 (Bit 12) */ + #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ + #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ + #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ + #define R_MSTP_MSTPCRD_MSTPD5_Msk (0x20UL) /*!< MSTPD5 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD3_Pos (3UL) /*!< MSTPD3 (Bit 3) */ + #define R_MSTP_MSTPCRD_MSTPD3_Msk (0x8UL) /*!< MSTPD3 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD2_Pos (2UL) /*!< MSTPD2 (Bit 2) */ + #define R_MSTP_MSTPCRD_MSTPD2_Msk (0x4UL) /*!< MSTPD2 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD1_Pos (1UL) /*!< MSTPD1 (Bit 1) */ + #define R_MSTP_MSTPCRD_MSTPD1_Msk (0x2UL) /*!< MSTPD1 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD0_Pos (0UL) /*!< MSTPD0 (Bit 0) */ + #define R_MSTP_MSTPCRD_MSTPD0_Msk (0x1UL) /*!< MSTPD0 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_MSTP_MSTPCRE_MSTPE4_Pos (4UL) /*!< MSTPE4 (Bit 4) */ + #define R_MSTP_MSTPCRE_MSTPE4_Msk (0x10UL) /*!< MSTPE4 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE14_Pos (14UL) /*!< MSTPE14 (Bit 14) */ + #define R_MSTP_MSTPCRE_MSTPE14_Msk (0x4000UL) /*!< MSTPE14 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE15_Pos (15UL) /*!< MSTPE15 (Bit 15) */ + #define R_MSTP_MSTPCRE_MSTPE15_Msk (0x8000UL) /*!< MSTPE15 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE22_Pos (22UL) /*!< MSTPE22 (Bit 22) */ + #define R_MSTP_MSTPCRE_MSTPE22_Msk (0x400000UL) /*!< MSTPE22 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE23_Pos (23UL) /*!< MSTPE23 (Bit 23) */ + #define R_MSTP_MSTPCRE_MSTPE23_Msk (0x800000UL) /*!< MSTPE23 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE24_Pos (24UL) /*!< MSTPE24 (Bit 24) */ + #define R_MSTP_MSTPCRE_MSTPE24_Msk (0x1000000UL) /*!< MSTPE24 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE25_Pos (25UL) /*!< MSTPE25 (Bit 25) */ + #define R_MSTP_MSTPCRE_MSTPE25_Msk (0x2000000UL) /*!< MSTPE25 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE26_Pos (26UL) /*!< MSTPE26 (Bit 26) */ + #define R_MSTP_MSTPCRE_MSTPE26_Msk (0x4000000UL) /*!< MSTPE26 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE27_Pos (27UL) /*!< MSTPE27 (Bit 27) */ + #define R_MSTP_MSTPCRE_MSTPE27_Msk (0x8000000UL) /*!< MSTPE27 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE28_Pos (28UL) /*!< MSTPE28 (Bit 28) */ + #define R_MSTP_MSTPCRE_MSTPE28_Msk (0x10000000UL) /*!< MSTPE28 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE29_Pos (29UL) /*!< MSTPE29 (Bit 29) */ + #define R_MSTP_MSTPCRE_MSTPE29_Msk (0x20000000UL) /*!< MSTPE29 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE30_Pos (30UL) /*!< MSTPE30 (Bit 30) */ + #define R_MSTP_MSTPCRE_MSTPE30_Msk (0x40000000UL) /*!< MSTPE30 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRE_MSTPE31_Pos (31UL) /*!< MSTPE31 (Bit 31) */ + #define R_MSTP_MSTPCRE_MSTPE31_Msk (0x80000000UL) /*!< MSTPE31 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PCNTR1 ========================================================= */ + #define R_PORT0_PCNTR1_PODR_Pos (16UL) /*!< PODR (Bit 16) */ + #define R_PORT0_PCNTR1_PODR_Msk (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR1_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PCNTR1_PDR_Msk (0xffffUL) /*!< PDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= P0DR ========================================================== */ + #define R_PORT0_P0DR_PODR_Pos (0UL) /*!< PODR (Bit 0) */ + #define R_PORT0_P0DR_PODR_Msk (0x1UL) /*!< PODR (Bitfield-Mask: 0x01) */ +/* ========================================================== PDR ========================================================== */ + #define R_PORT0_PDR_PDR_Pos (0UL) /*!< PDR (Bit 0) */ + #define R_PORT0_PDR_PDR_Msk (0x1UL) /*!< PDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR2 ========================================================= */ + #define R_PORT0_PCNTR2_EIDR_Pos (16UL) /*!< EIDR (Bit 16) */ + #define R_PORT0_PCNTR2_EIDR_Msk (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR2_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PCNTR2_PIDR_Msk (0xffffUL) /*!< PIDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EIDR ========================================================== */ + #define R_PORT0_EIDR_EIDR_Pos (0UL) /*!< EIDR (Bit 0) */ + #define R_PORT0_EIDR_EIDR_Msk (0x1UL) /*!< EIDR (Bitfield-Mask: 0x01) */ +/* ========================================================= PIDR ========================================================== */ + #define R_PORT0_PIDR_PIDR_Pos (0UL) /*!< PIDR (Bit 0) */ + #define R_PORT0_PIDR_PIDR_Msk (0x1UL) /*!< PIDR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR3 ========================================================= */ + #define R_PORT0_PCNTR3_PORR_Pos (16UL) /*!< PORR (Bit 16) */ + #define R_PORT0_PCNTR3_PORR_Msk (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR3_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_PCNTR3_POSR_Msk (0xffffUL) /*!< POSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= PORR ========================================================== */ + #define R_PORT0_PORR_PORR_Pos (0UL) /*!< PORR (Bit 0) */ + #define R_PORT0_PORR_PORR_Msk (0x1UL) /*!< PORR (Bitfield-Mask: 0x01) */ +/* ========================================================= POSR ========================================================== */ + #define R_PORT0_POSR_POSR_Pos (0UL) /*!< POSR (Bit 0) */ + #define R_PORT0_POSR_POSR_Msk (0x1UL) /*!< POSR (Bitfield-Mask: 0x01) */ +/* ======================================================== PCNTR4 ========================================================= */ + #define R_PORT0_PCNTR4_EORR_Pos (16UL) /*!< EORR (Bit 16) */ + #define R_PORT0_PCNTR4_EORR_Msk (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff) */ + #define R_PORT0_PCNTR4_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_PCNTR4_EOSR_Msk (0xffffUL) /*!< EOSR (Bitfield-Mask: 0xffff) */ +/* ========================================================= EORR ========================================================== */ + #define R_PORT0_EORR_EORR_Pos (0UL) /*!< EORR (Bit 0) */ + #define R_PORT0_EORR_EORR_Msk (0x1UL) /*!< EORR (Bitfield-Mask: 0x01) */ +/* ========================================================= EOSR ========================================================== */ + #define R_PORT0_EOSR_EOSR_Pos (0UL) /*!< EOSR (Bit 0) */ + #define R_PORT0_EOSR_EOSR_Msk (0x1UL) /*!< EOSR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PFS ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_PMISC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PFENET ========================================================= */ +/* ========================================================= PWPR ========================================================== */ + #define R_PMISC_PWPR_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPR_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPR_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPR_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ +/* ========================================================= PWPRS ========================================================= */ + #define R_PMISC_PWPRS_PFSWE_Pos (6UL) /*!< PFSWE (Bit 6) */ + #define R_PMISC_PWPRS_PFSWE_Msk (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01) */ + #define R_PMISC_PWPRS_B0WI_Pos (7UL) /*!< B0WI (Bit 7) */ + #define R_PMISC_PWPRS_B0WI_Msk (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SMR ========================================================== */ + #define R_SCI0_SMR_CM_Pos (7UL) /*!< CM (Bit 7) */ + #define R_SCI0_SMR_CM_Msk (0x80UL) /*!< CM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CHR_Pos (6UL) /*!< CHR (Bit 6) */ + #define R_SCI0_SMR_CHR_Msk (0x40UL) /*!< CHR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_SCI0_SMR_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_MP_Pos (2UL) /*!< MP (Bit 2) */ + #define R_SCI0_SMR_MP_Msk (0x4UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ======================================================= SMR_SMCI ======================================================== */ + #define R_SCI0_SMR_SMCI_GM_Pos (7UL) /*!< GM (Bit 7) */ + #define R_SCI0_SMR_SMCI_GM_Msk (0x80UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BLK_Pos (6UL) /*!< BLK (Bit 6) */ + #define R_SCI0_SMR_SMCI_BLK_Msk (0x40UL) /*!< BLK (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PE_Pos (5UL) /*!< PE (Bit 5) */ + #define R_SCI0_SMR_SMCI_PE_Msk (0x20UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_SCI0_SMR_SMCI_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SMR_SMCI_BCP_Pos (2UL) /*!< BCP (Bit 2) */ + #define R_SCI0_SMR_SMCI_BCP_Msk (0xcUL) /*!< BCP (Bitfield-Mask: 0x03) */ + #define R_SCI0_SMR_SMCI_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_SCI0_SMR_SMCI_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ +/* ========================================================== BRR ========================================================== */ + #define R_SCI0_BRR_BRR_Pos (0UL) /*!< BRR (Bit 0) */ + #define R_SCI0_BRR_BRR_Msk (0xffUL) /*!< BRR (Bitfield-Mask: 0xff) */ +/* ========================================================== SCR ========================================================== */ + #define R_SCI0_SCR_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ======================================================= SCR_SMCI ======================================================== */ + #define R_SCI0_SCR_SMCI_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_SCI0_SCR_SMCI_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_SCI0_SCR_SMCI_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TE_Pos (5UL) /*!< TE (Bit 5) */ + #define R_SCI0_SCR_SMCI_TE_Msk (0x20UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_RE_Pos (4UL) /*!< RE (Bit 4) */ + #define R_SCI0_SCR_SMCI_RE_Msk (0x10UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_MPIE_Pos (3UL) /*!< MPIE (Bit 3) */ + #define R_SCI0_SCR_SMCI_MPIE_Msk (0x8UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_TEIE_Pos (2UL) /*!< TEIE (Bit 2) */ + #define R_SCI0_SCR_SMCI_TEIE_Msk (0x4UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCR_SMCI_CKE_Pos (0UL) /*!< CKE (Bit 0) */ + #define R_SCI0_SCR_SMCI_CKE_Msk (0x3UL) /*!< CKE (Bitfield-Mask: 0x03) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDR_Pos (0UL) /*!< TDR (Bit 0) */ + #define R_SCI0_TDR_TDR_Msk (0xffUL) /*!< TDR (Bitfield-Mask: 0xff) */ +/* ========================================================== SSR ========================================================== */ + #define R_SCI0_SSR_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_FIFO ======================================================== */ + #define R_SCI0_SSR_FIFO_TDFE_Pos (7UL) /*!< TDFE (Bit 7) */ + #define R_SCI0_SSR_FIFO_TDFE_Msk (0x80UL) /*!< TDFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_SSR_FIFO_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_FIFO_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_SSR_FIFO_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_FIFO_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_FIFO_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_FIFO_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_SSR_FIFO_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ +/* ======================================================= SSR_SMCI ======================================================== */ + #define R_SCI0_SSR_SMCI_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_SCI0_SSR_SMCI_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_RDRF_Pos (6UL) /*!< RDRF (Bit 6) */ + #define R_SCI0_SSR_SMCI_RDRF_Msk (0x40UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_SSR_SMCI_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_SSR_SMCI_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_SSR_SMCI_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_TEND_Pos (2UL) /*!< TEND (Bit 2) */ + #define R_SCI0_SSR_SMCI_TEND_Msk (0x4UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_SSR_SMCI_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_SSR_SMCI_MPBT_Pos (0UL) /*!< MPBT (Bit 0) */ + #define R_SCI0_SSR_SMCI_MPBT_Msk (0x1UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDR_Pos (0UL) /*!< RDR (Bit 0) */ + #define R_SCI0_RDR_RDR_Msk (0xffUL) /*!< RDR (Bitfield-Mask: 0xff) */ +/* ========================================================= SCMR ========================================================== */ + #define R_SCI0_SCMR_BCP2_Pos (7UL) /*!< BCP2 (Bit 7) */ + #define R_SCI0_SCMR_BCP2_Msk (0x80UL) /*!< BCP2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_CHR1_Pos (4UL) /*!< CHR1 (Bit 4) */ + #define R_SCI0_SCMR_CHR1_Msk (0x10UL) /*!< CHR1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SDIR_Pos (3UL) /*!< SDIR (Bit 3) */ + #define R_SCI0_SCMR_SDIR_Msk (0x8UL) /*!< SDIR (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SINV_Pos (2UL) /*!< SINV (Bit 2) */ + #define R_SCI0_SCMR_SINV_Msk (0x4UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SCMR_SMIF_Pos (0UL) /*!< SMIF (Bit 0) */ + #define R_SCI0_SCMR_SMIF_Msk (0x1UL) /*!< SMIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SEMR ========================================================== */ + #define R_SCI0_SEMR_RXDESEL_Pos (7UL) /*!< RXDESEL (Bit 7) */ + #define R_SCI0_SEMR_RXDESEL_Msk (0x80UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BGDM_Pos (6UL) /*!< BGDM (Bit 6) */ + #define R_SCI0_SEMR_BGDM_Msk (0x40UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_NFEN_Pos (5UL) /*!< NFEN (Bit 5) */ + #define R_SCI0_SEMR_NFEN_Msk (0x20UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCS_Pos (4UL) /*!< ABCS (Bit 4) */ + #define R_SCI0_SEMR_ABCS_Msk (0x10UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ABCSE_Pos (3UL) /*!< ABCSE (Bit 3) */ + #define R_SCI0_SEMR_ABCSE_Msk (0x8UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_BRME_Pos (2UL) /*!< BRME (Bit 2) */ + #define R_SCI0_SEMR_BRME_Msk (0x4UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_PADIS_Pos (1UL) /*!< PADIS (Bit 1) */ + #define R_SCI0_SEMR_PADIS_Msk (0x2UL) /*!< PADIS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SEMR_ACS0_Pos (0UL) /*!< ACS0 (Bit 0) */ + #define R_SCI0_SEMR_ACS0_Msk (0x1UL) /*!< ACS0 (Bitfield-Mask: 0x01) */ +/* ========================================================= SNFR ========================================================== */ + #define R_SCI0_SNFR_NFCS_Pos (0UL) /*!< NFCS (Bit 0) */ + #define R_SCI0_SNFR_NFCS_Msk (0x7UL) /*!< NFCS (Bitfield-Mask: 0x07) */ +/* ========================================================= SIMR1 ========================================================= */ + #define R_SCI0_SIMR1_IICDL_Pos (3UL) /*!< IICDL (Bit 3) */ + #define R_SCI0_SIMR1_IICDL_Msk (0xf8UL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_SIMR1_IICM_Pos (0UL) /*!< IICM (Bit 0) */ + #define R_SCI0_SIMR1_IICM_Msk (0x1UL) /*!< IICM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR2 ========================================================= */ + #define R_SCI0_SIMR2_IICACKT_Pos (5UL) /*!< IICACKT (Bit 5) */ + #define R_SCI0_SIMR2_IICACKT_Msk (0x20UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICCSC_Pos (1UL) /*!< IICCSC (Bit 1) */ + #define R_SCI0_SIMR2_IICCSC_Msk (0x2UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR2_IICINTM_Pos (0UL) /*!< IICINTM (Bit 0) */ + #define R_SCI0_SIMR2_IICINTM_Msk (0x1UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= SIMR3 ========================================================= */ + #define R_SCI0_SIMR3_IICSCLS_Pos (6UL) /*!< IICSCLS (Bit 6) */ + #define R_SCI0_SIMR3_IICSCLS_Msk (0xc0UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSDAS_Pos (4UL) /*!< IICSDAS (Bit 4) */ + #define R_SCI0_SIMR3_IICSDAS_Msk (0x30UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_SIMR3_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_SIMR3_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTPREQ_Pos (2UL) /*!< IICSTPREQ (Bit 2) */ + #define R_SCI0_SIMR3_IICSTPREQ_Msk (0x4UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Pos (1UL) /*!< IICRSTAREQ (Bit 1) */ + #define R_SCI0_SIMR3_IICRSTAREQ_Msk (0x2UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_SIMR3_IICSTAREQ_Pos (0UL) /*!< IICSTAREQ (Bit 0) */ + #define R_SCI0_SIMR3_IICSTAREQ_Msk (0x1UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ +/* ========================================================= SISR ========================================================== */ + #define R_SCI0_SISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_SISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ +/* ========================================================= SPMR ========================================================== */ + #define R_SCI0_SPMR_CKPH_Pos (7UL) /*!< CKPH (Bit 7) */ + #define R_SCI0_SPMR_CKPH_Msk (0x80UL) /*!< CKPH (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CKPOL_Pos (6UL) /*!< CKPOL (Bit 6) */ + #define R_SCI0_SPMR_CKPOL_Msk (0x40UL) /*!< CKPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MFF_Pos (4UL) /*!< MFF (Bit 4) */ + #define R_SCI0_SPMR_MFF_Msk (0x10UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CSTPEN_Pos (3UL) /*!< CSTPEN (Bit 3) */ + #define R_SCI0_SPMR_CSTPEN_Msk (0x8UL) /*!< CSTPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_MSS_Pos (2UL) /*!< MSS (Bit 2) */ + #define R_SCI0_SPMR_MSS_Msk (0x4UL) /*!< MSS (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_CTSE_Pos (1UL) /*!< CTSE (Bit 1) */ + #define R_SCI0_SPMR_CTSE_Msk (0x2UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPMR_SSE_Pos (0UL) /*!< SSE (Bit 0) */ + #define R_SCI0_SPMR_SSE_Msk (0x1UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TDRHL ========================================================= */ + #define R_SCI0_TDRHL_TDRHL_Pos (0UL) /*!< TDRHL (Bit 0) */ + #define R_SCI0_TDRHL_TDRHL_Msk (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FTDRHL ========================================================= */ + #define R_SCI0_FTDRHL_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_FTDRHL_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRHL_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_FTDRHL_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FTDRH ========================================================= */ + #define R_SCI0_FTDRH_MPBT_Pos (1UL) /*!< MPBT (Bit 1) */ + #define R_SCI0_FTDRH_MPBT_Msk (0x2UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI0_FTDRH_TDATH_Pos (0UL) /*!< TDATH (Bit 0) */ + #define R_SCI0_FTDRH_TDATH_Msk (0x1UL) /*!< TDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FTDRL ========================================================= */ + #define R_SCI0_FTDRL_TDATL_Pos (0UL) /*!< TDATL (Bit 0) */ + #define R_SCI0_FTDRL_TDATL_Msk (0xffUL) /*!< TDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= RDRHL ========================================================= */ + #define R_SCI0_RDRHL_RDRHL_Pos (0UL) /*!< RDRHL (Bit 0) */ + #define R_SCI0_RDRHL_RDRHL_Msk (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRDRHL ========================================================= */ + #define R_SCI0_FRDRHL_RDF_Pos (14UL) /*!< RDF (Bit 14) */ + #define R_SCI0_FRDRHL_RDF_Msk (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_ORER_Pos (13UL) /*!< ORER (Bit 13) */ + #define R_SCI0_FRDRHL_ORER_Msk (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_FER_Pos (12UL) /*!< FER (Bit 12) */ + #define R_SCI0_FRDRHL_FER_Msk (0x1000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_PER_Pos (11UL) /*!< PER (Bit 11) */ + #define R_SCI0_FRDRHL_PER_Msk (0x800UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_FRDRHL_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_FRDRHL_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRHL_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_FRDRHL_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ +/* ========================================================= FRDRH ========================================================= */ + #define R_SCI0_FRDRH_RDF_Pos (6UL) /*!< RDF (Bit 6) */ + #define R_SCI0_FRDRH_RDF_Msk (0x40UL) /*!< RDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_ORER_Pos (5UL) /*!< ORER (Bit 5) */ + #define R_SCI0_FRDRH_ORER_Msk (0x20UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_FER_Pos (4UL) /*!< FER (Bit 4) */ + #define R_SCI0_FRDRH_FER_Msk (0x10UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_PER_Pos (3UL) /*!< PER (Bit 3) */ + #define R_SCI0_FRDRH_PER_Msk (0x8UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_DR_Pos (2UL) /*!< DR (Bit 2) */ + #define R_SCI0_FRDRH_DR_Msk (0x4UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_MPB_Pos (1UL) /*!< MPB (Bit 1) */ + #define R_SCI0_FRDRH_MPB_Msk (0x2UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRDRH_RDATH_Pos (0UL) /*!< RDATH (Bit 0) */ + #define R_SCI0_FRDRH_RDATH_Msk (0x1UL) /*!< RDATH (Bitfield-Mask: 0x01) */ +/* ========================================================= FRDRL ========================================================= */ + #define R_SCI0_FRDRL_RDATL_Pos (0UL) /*!< RDATL (Bit 0) */ + #define R_SCI0_FRDRL_RDATL_Msk (0xffUL) /*!< RDATL (Bitfield-Mask: 0xff) */ +/* ========================================================= MDDR ========================================================== */ + #define R_SCI0_MDDR_MDDR_Pos (0UL) /*!< MDDR (Bit 0) */ + #define R_SCI0_MDDR_MDDR_Msk (0xffUL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= DCCR ========================================================== */ + #define R_SCI0_DCCR_DCME_Pos (7UL) /*!< DCME (Bit 7) */ + #define R_SCI0_DCCR_DCME_Msk (0x80UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_IDSEL_Pos (6UL) /*!< IDSEL (Bit 6) */ + #define R_SCI0_DCCR_IDSEL_Msk (0x40UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DFER_Pos (4UL) /*!< DFER (Bit 4) */ + #define R_SCI0_DCCR_DFER_Msk (0x10UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DPER_Pos (3UL) /*!< DPER (Bit 3) */ + #define R_SCI0_DCCR_DPER_Msk (0x8UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCCR_DCMF_Pos (0UL) /*!< DCMF (Bit 0) */ + #define R_SCI0_DCCR_DCMF_Msk (0x1UL) /*!< DCMF (Bitfield-Mask: 0x01) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_RSTRG_Pos (12UL) /*!< RSTRG (Bit 12) */ + #define R_SCI0_FCR_RSTRG_Msk (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_RTRG_Pos (8UL) /*!< RTRG (Bit 8) */ + #define R_SCI0_FCR_RTRG_Msk (0xf00UL) /*!< RTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_TTRG_Pos (4UL) /*!< TTRG (Bit 4) */ + #define R_SCI0_FCR_TTRG_Msk (0xf0UL) /*!< TTRG (Bitfield-Mask: 0x0f) */ + #define R_SCI0_FCR_DRES_Pos (3UL) /*!< DRES (Bit 3) */ + #define R_SCI0_FCR_DRES_Msk (0x8UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TFRST_Pos (2UL) /*!< TFRST (Bit 2) */ + #define R_SCI0_FCR_TFRST_Msk (0x4UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RFRST_Pos (1UL) /*!< RFRST (Bit 1) */ + #define R_SCI0_FCR_RFRST_Msk (0x2UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_FM_Pos (0UL) /*!< FM (Bit 0) */ + #define R_SCI0_FCR_FM_Msk (0x1UL) /*!< FM (Bitfield-Mask: 0x01) */ +/* ========================================================== FDR ========================================================== */ + #define R_SCI0_FDR_T_Pos (8UL) /*!< T (Bit 8) */ + #define R_SCI0_FDR_T_Msk (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FDR_R_Pos (0UL) /*!< R (Bit 0) */ + #define R_SCI0_FDR_R_Msk (0x1fUL) /*!< R (Bitfield-Mask: 0x1f) */ +/* ========================================================== LSR ========================================================== */ + #define R_SCI0_LSR_PNUM_Pos (8UL) /*!< PNUM (Bit 8) */ + #define R_SCI0_LSR_PNUM_Msk (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_FNUM_Pos (2UL) /*!< FNUM (Bit 2) */ + #define R_SCI0_LSR_FNUM_Msk (0x7cUL) /*!< FNUM (Bitfield-Mask: 0x1f) */ + #define R_SCI0_LSR_ORER_Pos (0UL) /*!< ORER (Bit 0) */ + #define R_SCI0_LSR_ORER_Msk (0x1UL) /*!< ORER (Bitfield-Mask: 0x01) */ +/* ========================================================== CDR ========================================================== */ + #define R_SCI0_CDR_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CDR_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ +/* ========================================================= SPTR ========================================================== */ + #define R_SCI0_SPTR_SPB2IO_Pos (2UL) /*!< SPB2IO (Bit 2) */ + #define R_SCI0_SPTR_SPB2IO_Msk (0x4UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_SPB2DT_Pos (1UL) /*!< SPB2DT (Bit 1) */ + #define R_SCI0_SPTR_SPB2DT_Msk (0x2UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RXDMON_Pos (0UL) /*!< RXDMON (Bit 0) */ + #define R_SCI0_SPTR_RXDMON_Msk (0x1UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_RINV_Pos (4UL) /*!< RINV (Bit 4) */ + #define R_SCI0_SPTR_RINV_Msk (0x10UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_TINV_Pos (5UL) /*!< TINV (Bit 5) */ + #define R_SCI0_SPTR_TINV_Msk (0x20UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ASEN_Pos (6UL) /*!< ASEN (Bit 6) */ + #define R_SCI0_SPTR_ASEN_Msk (0x40UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_SPTR_ATEN_Pos (7UL) /*!< ATEN (Bit 7) */ + #define R_SCI0_SPTR_ATEN_Msk (0x80UL) /*!< ATEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ACTR ========================================================== */ + #define R_SCI0_ACTR_AST_Pos (0UL) /*!< AST (Bit 0) */ + #define R_SCI0_ACTR_AST_Msk (0x7UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AJD_Pos (3UL) /*!< AJD (Bit 3) */ + #define R_SCI0_ACTR_AJD_Msk (0x8UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_ACTR_ATT_Pos (4UL) /*!< ATT (Bit 4) */ + #define R_SCI0_ACTR_ATT_Msk (0x70UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_ACTR_AET_Pos (7UL) /*!< AET (Bit 7) */ + #define R_SCI0_ACTR_AET_Msk (0x80UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= ESMER ========================================================= */ + #define R_SCI0_ESMER_ESME_Pos (0UL) /*!< ESME (Bit 0) */ + #define R_SCI0_ESMER_ESME_Msk (0x1UL) /*!< ESME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR0 ========================================================== */ + #define R_SCI0_CR0_SFSF_Pos (1UL) /*!< SFSF (Bit 1) */ + #define R_SCI0_CR0_SFSF_Msk (0x2UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_RXDSF_Pos (2UL) /*!< RXDSF (Bit 2) */ + #define R_SCI0_CR0_RXDSF_Msk (0x4UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR0_BRME_Pos (3UL) /*!< BRME (Bit 3) */ + #define R_SCI0_CR0_BRME_Msk (0x8UL) /*!< BRME (Bitfield-Mask: 0x01) */ +/* ========================================================== CR1 ========================================================== */ + #define R_SCI0_CR1_BFE_Pos (0UL) /*!< BFE (Bit 0) */ + #define R_SCI0_CR1_BFE_Msk (0x1UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF0RE_Pos (1UL) /*!< CF0RE (Bit 1) */ + #define R_SCI0_CR1_CF0RE_Msk (0x2UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_CF1DS_Pos (2UL) /*!< CF1DS (Bit 2) */ + #define R_SCI0_CR1_CF1DS_Msk (0xcUL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR1_PIBE_Pos (4UL) /*!< PIBE (Bit 4) */ + #define R_SCI0_CR1_PIBE_Msk (0x10UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CR1_PIBS_Pos (5UL) /*!< PIBS (Bit 5) */ + #define R_SCI0_CR1_PIBS_Msk (0xe0UL) /*!< PIBS (Bitfield-Mask: 0x07) */ +/* ========================================================== CR2 ========================================================== */ + #define R_SCI0_CR2_DFCS_Pos (0UL) /*!< DFCS (Bit 0) */ + #define R_SCI0_CR2_DFCS_Msk (0x7UL) /*!< DFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CR2_BCCS_Pos (4UL) /*!< BCCS (Bit 4) */ + #define R_SCI0_CR2_BCCS_Msk (0x30UL) /*!< BCCS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CR2_RTS_Pos (6UL) /*!< RTS (Bit 6) */ + #define R_SCI0_CR2_RTS_Msk (0xc0UL) /*!< RTS (Bitfield-Mask: 0x03) */ +/* ========================================================== CR3 ========================================================== */ + #define R_SCI0_CR3_SDST_Pos (0UL) /*!< SDST (Bit 0) */ + #define R_SCI0_CR3_SDST_Msk (0x1UL) /*!< SDST (Bitfield-Mask: 0x01) */ +/* ========================================================== PCR ========================================================== */ + #define R_SCI0_PCR_TXDXPS_Pos (0UL) /*!< TXDXPS (Bit 0) */ + #define R_SCI0_PCR_TXDXPS_Msk (0x1UL) /*!< TXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_RXDXPS_Pos (1UL) /*!< RXDXPS (Bit 1) */ + #define R_SCI0_PCR_RXDXPS_Msk (0x2UL) /*!< RXDXPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_PCR_SHARPS_Pos (4UL) /*!< SHARPS (Bit 4) */ + #define R_SCI0_PCR_SHARPS_Msk (0x10UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_BFDIE_Pos (0UL) /*!< BFDIE (Bit 0) */ + #define R_SCI0_ICR_BFDIE_Msk (0x1UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF0MIE_Pos (1UL) /*!< CF0MIE (Bit 1) */ + #define R_SCI0_ICR_CF0MIE_Msk (0x2UL) /*!< CF0MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_CF1MIE_Pos (2UL) /*!< CF1MIE (Bit 2) */ + #define R_SCI0_ICR_CF1MIE_Msk (0x4UL) /*!< CF1MIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_PIBDIE_Pos (3UL) /*!< PIBDIE (Bit 3) */ + #define R_SCI0_ICR_PIBDIE_Msk (0x8UL) /*!< PIBDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_BCDIE_Pos (4UL) /*!< BCDIE (Bit 4) */ + #define R_SCI0_ICR_BCDIE_Msk (0x10UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_AEDIE_Pos (5UL) /*!< AEDIE (Bit 5) */ + #define R_SCI0_ICR_AEDIE_Msk (0x20UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ +/* ========================================================== STR ========================================================== */ + #define R_SCI0_STR_BFDF_Pos (0UL) /*!< BFDF (Bit 0) */ + #define R_SCI0_STR_BFDF_Msk (0x1UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF0MF_Pos (1UL) /*!< CF0MF (Bit 1) */ + #define R_SCI0_STR_CF0MF_Msk (0x2UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_CF1MF_Pos (2UL) /*!< CF1MF (Bit 2) */ + #define R_SCI0_STR_CF1MF_Msk (0x4UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_PIBDF_Pos (3UL) /*!< PIBDF (Bit 3) */ + #define R_SCI0_STR_PIBDF_Msk (0x8UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_BCDF_Pos (4UL) /*!< BCDF (Bit 4) */ + #define R_SCI0_STR_BCDF_Msk (0x10UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI0_STR_AEDF_Pos (5UL) /*!< AEDF (Bit 5) */ + #define R_SCI0_STR_AEDF_Msk (0x20UL) /*!< AEDF (Bitfield-Mask: 0x01) */ +/* ========================================================= STCR ========================================================== */ + #define R_SCI0_STCR_BFDCL_Pos (0UL) /*!< BFDCL (Bit 0) */ + #define R_SCI0_STCR_BFDCL_Msk (0x1UL) /*!< BFDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF0MCL_Pos (1UL) /*!< CF0MCL (Bit 1) */ + #define R_SCI0_STCR_CF0MCL_Msk (0x2UL) /*!< CF0MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_CF1MCL_Pos (2UL) /*!< CF1MCL (Bit 2) */ + #define R_SCI0_STCR_CF1MCL_Msk (0x4UL) /*!< CF1MCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_PIBDCL_Pos (3UL) /*!< PIBDCL (Bit 3) */ + #define R_SCI0_STCR_PIBDCL_Msk (0x8UL) /*!< PIBDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_BCDCL_Pos (4UL) /*!< BCDCL (Bit 4) */ + #define R_SCI0_STCR_BCDCL_Msk (0x10UL) /*!< BCDCL (Bitfield-Mask: 0x01) */ + #define R_SCI0_STCR_AEDCL_Pos (5UL) /*!< AEDCL (Bit 5) */ + #define R_SCI0_STCR_AEDCL_Msk (0x20UL) /*!< AEDCL (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0DR ========================================================= */ +/* ========================================================= CF0CR ========================================================= */ + #define R_SCI0_CF0CR_CF0CE0_Pos (0UL) /*!< CF0CE0 (Bit 0) */ + #define R_SCI0_CF0CR_CF0CE0_Msk (0x1UL) /*!< CF0CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE1_Pos (1UL) /*!< CF0CE1 (Bit 1) */ + #define R_SCI0_CF0CR_CF0CE1_Msk (0x2UL) /*!< CF0CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE2_Pos (2UL) /*!< CF0CE2 (Bit 2) */ + #define R_SCI0_CF0CR_CF0CE2_Msk (0x4UL) /*!< CF0CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE3_Pos (3UL) /*!< CF0CE3 (Bit 3) */ + #define R_SCI0_CF0CR_CF0CE3_Msk (0x8UL) /*!< CF0CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE4_Pos (4UL) /*!< CF0CE4 (Bit 4) */ + #define R_SCI0_CF0CR_CF0CE4_Msk (0x10UL) /*!< CF0CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE5_Pos (5UL) /*!< CF0CE5 (Bit 5) */ + #define R_SCI0_CF0CR_CF0CE5_Msk (0x20UL) /*!< CF0CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE6_Pos (6UL) /*!< CF0CE6 (Bit 6) */ + #define R_SCI0_CF0CR_CF0CE6_Msk (0x40UL) /*!< CF0CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF0CR_CF0CE7_Pos (7UL) /*!< CF0CE7 (Bit 7) */ + #define R_SCI0_CF0CR_CF0CE7_Msk (0x80UL) /*!< CF0CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF0RR ========================================================= */ +/* ======================================================== PCF1DR ========================================================= */ +/* ======================================================== SCF1DR ========================================================= */ +/* ========================================================= CF1CR ========================================================= */ + #define R_SCI0_CF1CR_CF1CE0_Pos (0UL) /*!< CF1CE0 (Bit 0) */ + #define R_SCI0_CF1CR_CF1CE0_Msk (0x1UL) /*!< CF1CE0 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE1_Pos (1UL) /*!< CF1CE1 (Bit 1) */ + #define R_SCI0_CF1CR_CF1CE1_Msk (0x2UL) /*!< CF1CE1 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE2_Pos (2UL) /*!< CF1CE2 (Bit 2) */ + #define R_SCI0_CF1CR_CF1CE2_Msk (0x4UL) /*!< CF1CE2 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE3_Pos (3UL) /*!< CF1CE3 (Bit 3) */ + #define R_SCI0_CF1CR_CF1CE3_Msk (0x8UL) /*!< CF1CE3 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE4_Pos (4UL) /*!< CF1CE4 (Bit 4) */ + #define R_SCI0_CF1CR_CF1CE4_Msk (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE5_Pos (5UL) /*!< CF1CE5 (Bit 5) */ + #define R_SCI0_CF1CR_CF1CE5_Msk (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE6_Pos (6UL) /*!< CF1CE6 (Bit 6) */ + #define R_SCI0_CF1CR_CF1CE6_Msk (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01) */ + #define R_SCI0_CF1CR_CF1CE7_Pos (7UL) /*!< CF1CE7 (Bit 7) */ + #define R_SCI0_CF1CR_CF1CE7_Msk (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01) */ +/* ========================================================= CF1RR ========================================================= */ +/* ========================================================== TCR ========================================================== */ + #define R_SCI0_TCR_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI0_TCR_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ +/* ========================================================== TMR ========================================================== */ + #define R_SCI0_TMR_TOMS_Pos (0UL) /*!< TOMS (Bit 0) */ + #define R_SCI0_TMR_TOMS_Msk (0x3UL) /*!< TOMS (Bitfield-Mask: 0x03) */ + #define R_SCI0_TMR_TWRC_Pos (3UL) /*!< TWRC (Bit 3) */ + #define R_SCI0_TMR_TWRC_Msk (0x8UL) /*!< TWRC (Bitfield-Mask: 0x01) */ + #define R_SCI0_TMR_TCSS_Pos (4UL) /*!< TCSS (Bit 4) */ + #define R_SCI0_TMR_TCSS_Msk (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07) */ +/* ========================================================= TPRE ========================================================== */ +/* ========================================================= TCNT ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPRIE_Pos (7UL) /*!< SPRIE (Bit 7) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPE_Pos (6UL) /*!< SPE (Bit 6) */ + #define R_SPI0_SPCR_SPE_Msk (0x40UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (5UL) /*!< SPTIE (Bit 5) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (4UL) /*!< SPEIE (Bit 4) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MSTR_Pos (3UL) /*!< MSTR (Bit 3) */ + #define R_SPI0_SPCR_MSTR_Msk (0x8UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (2UL) /*!< MODFEN (Bit 2) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (1UL) /*!< TXMD (Bit 1) */ + #define R_SPI0_SPCR_TXMD_Msk (0x2UL) /*!< TXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (0UL) /*!< SPMS (Bit 0) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1UL) /*!< SPMS (Bitfield-Mask: 0x01) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL4P_Pos (4UL) /*!< SSL4P (Bit 4) */ + #define R_SPI0_SSLP_SSL4P_Msk (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL5P_Pos (5UL) /*!< SSL5P (Bit 5) */ + #define R_SPI0_SSLP_SSL5P_Msk (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL6P_Pos (6UL) /*!< SSL6P (Bit 6) */ + #define R_SPI0_SSLP_SSL6P_Msk (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL7P_Pos (7UL) /*!< SSL7P (Bit 7) */ + #define R_SPI0_SSLP_SSL7P_Msk (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPRF_Pos (7UL) /*!< SPRF (Bit 7) */ + #define R_SPI0_SPSR_SPRF_Msk (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (5UL) /*!< SPTEF (Bit 5) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (4UL) /*!< UDRF (Bit 4) */ + #define R_SPI0_SPSR_UDRF_Msk (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (3UL) /*!< PERF (Bit 3) */ + #define R_SPI0_SPSR_PERF_Msk (0x8UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (2UL) /*!< MODF (Bit 2) */ + #define R_SPI0_SPSR_MODF_Msk (0x4UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (1UL) /*!< IDLNF (Bit 1) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x2UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (0UL) /*!< OVRF (Bit 0) */ + #define R_SPI0_SPSR_OVRF_Msk (0x1UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (6UL) /*!< CENDF (Bit 6) */ + #define R_SPI0_SPSR_CENDF_Msk (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01) */ +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_SPBYT_Pos (6UL) /*!< SPBYT (Bit 6) */ + #define R_SPI0_SPDCR_SPBYT_Msk (0x40UL) /*!< SPBYT (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPLW_Pos (5UL) /*!< SPLW (Bit 5) */ + #define R_SPI0_SPDCR_SPLW_Msk (0x20UL) /*!< SPLW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (4UL) /*!< SPRDTD (Bit 4) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x10UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (0UL) /*!< SPFC (Bit 0) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x3UL) /*!< SPFC (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SLSEL_Pos (2UL) /*!< SLSEL (Bit 2) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0xcUL) /*!< SLSEL (Bitfield-Mask: 0x03) */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SCKASE_Pos (4UL) /*!< SCKASE (Bit 4) */ + #define R_SPI0_SPCR2_SCKASE_Msk (0x10UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_PTE_Pos (3UL) /*!< PTE (Bit 3) */ + #define R_SPI0_SPCR2_PTE_Msk (0x8UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPIIE_Pos (2UL) /*!< SPIIE (Bit 2) */ + #define R_SPI0_SPCR2_SPIIE_Msk (0x4UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPOE_Pos (1UL) /*!< SPOE (Bit 1) */ + #define R_SPI0_SPCR2_SPOE_Msk (0x2UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPPE_Pos (0UL) /*!< SPPE (Bit 0) */ + #define R_SPI0_SPCR2_SPPE_Msk (0x1UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR2_SPTDDL_Pos (5UL) /*!< SPTDDL (Bit 5) */ + #define R_SPI0_SPCR2_SPTDDL_Msk (0xe0UL) /*!< SPTDDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (8UL) /*!< SPB (Bit 8) */ + #define R_SPI0_SPCMD_SPB_Msk (0xf00UL) /*!< SPB (Bitfield-Mask: 0x0f) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SSLA_Pos (4UL) /*!< SSLA (Bit 4) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x70UL) /*!< SSLA (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR2_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR2_SINV_Pos (1UL) /*!< SINV (Bit 1) */ + #define R_SPI0_SPDCR2_SINV_Msk (0x2UL) /*!< SINV (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI0_SPCR3_ETXMD_Pos (0UL) /*!< ETXMD (Bit 0) */ + #define R_SPI0_SPCR3_ETXMD_Msk (0x1UL) /*!< ETXMD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_BFDS_Pos (1UL) /*!< BFDS (Bit 1) */ + #define R_SPI0_SPCR3_BFDS_Msk (0x2UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR3_CENDIE_Pos (4UL) /*!< CENDIE (Bit 4) */ + #define R_SPI0_SPCR3_CENDIE_Msk (0x10UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPPR ========================================================== */ + #define R_SPI0_SPPR_BUFWID_Pos (4UL) /*!< BUFWID (Bit 4) */ + #define R_SPI0_SPPR_BUFWID_Msk (0x10UL) /*!< BUFWID (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPR_BUFNUM_Pos (8UL) /*!< BUFNUM (Bit 8) */ + #define R_SPI0_SPPR_BUFNUM_Msk (0x700UL) /*!< BUFNUM (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPPR_CMDNUM_Pos (12UL) /*!< CMDNUM (Bit 12) */ + #define R_SPI0_SPPR_CMDNUM_Msk (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== PARIOAD ======================================================== */ + #define R_SRAM_PARIOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_PARIOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR ======================================================== */ + #define R_SRAM_SRAMPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos (0UL) /*!< SRAMPRCR (Bit 0) */ + #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk (0x1UL) /*!< SRAMPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMWTSC ======================================================== */ +/* ======================================================== ECCMODE ======================================================== */ + #define R_SRAM_ECCMODE_ECCMOD_Pos (0UL) /*!< ECCMOD (Bit 0) */ + #define R_SRAM_ECCMODE_ECCMOD_Msk (0x3UL) /*!< ECCMOD (Bitfield-Mask: 0x03) */ +/* ======================================================== ECC2STS ======================================================== */ + #define R_SRAM_ECC2STS_ECC2ERR_Pos (0UL) /*!< ECC2ERR (Bit 0) */ + #define R_SRAM_ECC2STS_ECC2ERR_Msk (0x1UL) /*!< ECC2ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECC1STSEN ======================================================= */ + #define R_SRAM_ECC1STSEN_E1STSEN_Pos (0UL) /*!< E1STSEN (Bit 0) */ + #define R_SRAM_ECC1STSEN_E1STSEN_Msk (0x1UL) /*!< E1STSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ECC1STS ======================================================== */ + #define R_SRAM_ECC1STS_ECC1ERR_Pos (0UL) /*!< ECC1ERR (Bit 0) */ + #define R_SRAM_ECC1STS_ECC1ERR_Msk (0x1UL) /*!< ECC1ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCPRCR ======================================================== */ + #define R_SRAM_ECCPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_ECCPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Pos (0UL) /*!< ECCPRCR (Bit 0) */ + #define R_SRAM_ECCPRCR_ECCPRCR_Msk (0x1UL) /*!< ECCPRCR (Bitfield-Mask: 0x01) */ +/* ======================================================= ECCPRCR2 ======================================================== */ + #define R_SRAM_ECCPRCR2_KW2_Pos (1UL) /*!< KW2 (Bit 1) */ + #define R_SRAM_ECCPRCR2_KW2_Msk (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos (0UL) /*!< ECCPRCR2 (Bit 0) */ + #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk (0x1UL) /*!< ECCPRCR2 (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCETST ======================================================== */ + #define R_SRAM_ECCETST_TSTBYP_Pos (0UL) /*!< TSTBYP (Bit 0) */ + #define R_SRAM_ECCETST_TSTBYP_Msk (0x1UL) /*!< TSTBYP (Bitfield-Mask: 0x01) */ +/* ======================================================== ECCOAD ========================================================= */ + #define R_SRAM_ECCOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_SRAM_ECCOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================= SRAMPRCR2 ======================================================= */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos (0UL) /*!< SRAMPRCR2 (Bit 0) */ + #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk (0x1UL) /*!< SRAMPRCR2 (Bitfield-Mask: 0x01) */ + #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSTEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SBYCR ========================================================= */ + #define R_SYSTEM_SBYCR_SSBY_Pos (15UL) /*!< SSBY (Bit 15) */ + #define R_SYSTEM_SBYCR_SSBY_Msk (0x8000UL) /*!< SSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SBYCR_OPE_Pos (14UL) /*!< OPE (Bit 14) */ + #define R_SYSTEM_SBYCR_OPE_Msk (0x4000UL) /*!< OPE (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Pos (22UL) /*!< MSTPA22 (Bit 22) */ + #define R_SYSTEM_MSTPCRA_MSTPA22_Msk (0x400000UL) /*!< MSTPA22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Pos (7UL) /*!< MSTPA7 (Bit 7) */ + #define R_SYSTEM_MSTPCRA_MSTPA7_Msk (0x80UL) /*!< MSTPA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Pos (6UL) /*!< MSTPA6 (Bit 6) */ + #define R_SYSTEM_MSTPCRA_MSTPA6_Msk (0x40UL) /*!< MSTPA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Pos (5UL) /*!< MSTPA5 (Bit 5) */ + #define R_SYSTEM_MSTPCRA_MSTPA5_Msk (0x20UL) /*!< MSTPA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Pos (1UL) /*!< MSTPA1 (Bit 1) */ + #define R_SYSTEM_MSTPCRA_MSTPA1_Msk (0x2UL) /*!< MSTPA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Pos (0UL) /*!< MSTPA0 (Bit 0) */ + #define R_SYSTEM_MSTPCRA_MSTPA0_Msk (0x1UL) /*!< MSTPA0 (Bitfield-Mask: 0x01) */ +/* ======================================================= SCKDIVCR ======================================================== */ + #define R_SYSTEM_SCKDIVCR_FCK_Pos (28UL) /*!< FCK (Bit 28) */ + #define R_SYSTEM_SCKDIVCR_FCK_Msk (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_ICK_Pos (24UL) /*!< ICK (Bit 24) */ + #define R_SYSTEM_SCKDIVCR_ICK_Msk (0x7000000UL) /*!< ICK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_BCK_Pos (16UL) /*!< BCK (Bit 16) */ + #define R_SYSTEM_SCKDIVCR_BCK_Msk (0x70000UL) /*!< BCK (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Pos (12UL) /*!< PCKA (Bit 12) */ + #define R_SYSTEM_SCKDIVCR_PCKA_Msk (0x7000UL) /*!< PCKA (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Pos (8UL) /*!< PCKB (Bit 8) */ + #define R_SYSTEM_SCKDIVCR_PCKB_Msk (0x700UL) /*!< PCKB (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Pos (4UL) /*!< PCKC (Bit 4) */ + #define R_SYSTEM_SCKDIVCR_PCKC_Msk (0x70UL) /*!< PCKC (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Pos (0UL) /*!< PCKD (Bit 0) */ + #define R_SYSTEM_SCKDIVCR_PCKD_Msk (0x7UL) /*!< PCKD (Bitfield-Mask: 0x07) */ +/* ======================================================= SCKDIVCR2 ======================================================= */ + #define R_SYSTEM_SCKDIVCR2_UCK_Pos (4UL) /*!< UCK (Bit 4) */ + #define R_SYSTEM_SCKDIVCR2_UCK_Msk (0x70UL) /*!< UCK (Bitfield-Mask: 0x07) */ +/* ======================================================== SCKSCR ========================================================= */ + #define R_SYSTEM_SCKSCR_CKSEL_Pos (0UL) /*!< CKSEL (Bit 0) */ + #define R_SYSTEM_SCKSCR_CKSEL_Msk (0x7UL) /*!< CKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== PLLCCR ========================================================= */ + #define R_SYSTEM_PLLCCR_PLLMUL_Pos (8UL) /*!< PLLMUL (Bit 8) */ + #define R_SYSTEM_PLLCCR_PLLMUL_Msk (0x3f00UL) /*!< PLLMUL (Bitfield-Mask: 0x3f) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos (4UL) /*!< PLSRCSEL (Bit 4) */ + #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk (0x10UL) /*!< PLSRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Pos (0UL) /*!< PLIDIV (Bit 0) */ + #define R_SYSTEM_PLLCCR_PLIDIV_Msk (0x3UL) /*!< PLIDIV (Bitfield-Mask: 0x03) */ +/* ========================================================= PLLCR ========================================================= */ + #define R_SYSTEM_PLLCR_PLLSTP_Pos (0UL) /*!< PLLSTP (Bit 0) */ + #define R_SYSTEM_PLLCR_PLLSTP_Msk (0x1UL) /*!< PLLSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== PLLCCR2 ======================================================== */ + #define R_SYSTEM_PLLCCR2_PLODIV_Pos (6UL) /*!< PLODIV (Bit 6) */ + #define R_SYSTEM_PLLCCR2_PLODIV_Msk (0xc0UL) /*!< PLODIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Pos (0UL) /*!< PLLMUL (Bit 0) */ + #define R_SYSTEM_PLLCCR2_PLLMUL_Msk (0x1fUL) /*!< PLLMUL (Bitfield-Mask: 0x1f) */ +/* ========================================================= BCKCR ========================================================= */ + #define R_SYSTEM_BCKCR_BCLKDIV_Pos (0UL) /*!< BCLKDIV (Bit 0) */ + #define R_SYSTEM_BCKCR_BCLKDIV_Msk (0x1UL) /*!< BCLKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== MEMWAIT ======================================================== */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos (0UL) /*!< MEMWAIT (Bit 0) */ + #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk (0x1UL) /*!< MEMWAIT (Bitfield-Mask: 0x01) */ +/* ======================================================== MOSCCR ========================================================= */ + #define R_SYSTEM_MOSCCR_MOSTP_Pos (0UL) /*!< MOSTP (Bit 0) */ + #define R_SYSTEM_MOSCCR_MOSTP_Msk (0x1UL) /*!< MOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== HOCOCR ========================================================= */ + #define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */ + #define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== MOCOCR ========================================================= */ + #define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */ + #define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR1 ========================================================= */ + #define R_SYSTEM_FLLCR1_FLLEN_Pos (0UL) /*!< FLLEN (Bit 0) */ + #define R_SYSTEM_FLLCR1_FLLEN_Msk (0x1UL) /*!< FLLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLLCR2 ========================================================= */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Pos (0UL) /*!< FLLCNTL (Bit 0) */ + #define R_SYSTEM_FLLCR2_FLLCNTL_Msk (0x7ffUL) /*!< FLLCNTL (Bitfield-Mask: 0x7ff) */ +/* ========================================================= OSCSF ========================================================= */ + #define R_SYSTEM_OSCSF_PLLSF_Pos (5UL) /*!< PLLSF (Bit 5) */ + #define R_SYSTEM_OSCSF_PLLSF_Msk (0x20UL) /*!< PLLSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_MOSCSF_Pos (3UL) /*!< MOSCSF (Bit 3) */ + #define R_SYSTEM_OSCSF_MOSCSF_Msk (0x8UL) /*!< MOSCSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_HOCOSF_Pos (0UL) /*!< HOCOSF (Bit 0) */ + #define R_SYSTEM_OSCSF_HOCOSF_Msk (0x1UL) /*!< HOCOSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSCSF_PLL2SF_Pos (6UL) /*!< PLL2SF (Bit 6) */ + #define R_SYSTEM_OSCSF_PLL2SF_Msk (0x40UL) /*!< PLL2SF (Bitfield-Mask: 0x01) */ +/* ========================================================= CKOCR ========================================================= */ + #define R_SYSTEM_CKOCR_CKOEN_Pos (7UL) /*!< CKOEN (Bit 7) */ + #define R_SYSTEM_CKOCR_CKOEN_Msk (0x80UL) /*!< CKOEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CKOCR_CKODIV_Pos (4UL) /*!< CKODIV (Bit 4) */ + #define R_SYSTEM_CKOCR_CKODIV_Msk (0x70UL) /*!< CKODIV (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CKOCR_CKOSEL_Pos (0UL) /*!< CKOSEL (Bit 0) */ + #define R_SYSTEM_CKOCR_CKOSEL_Msk (0x7UL) /*!< CKOSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== TRCKCR ========================================================= */ + #define R_SYSTEM_TRCKCR_TRCKEN_Pos (7UL) /*!< TRCKEN (Bit 7) */ + #define R_SYSTEM_TRCKCR_TRCKEN_Msk (0x80UL) /*!< TRCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_TRCKCR_TRCK_Pos (0UL) /*!< TRCK (Bit 0) */ + #define R_SYSTEM_TRCKCR_TRCK_Msk (0xfUL) /*!< TRCK (Bitfield-Mask: 0x0f) */ +/* ======================================================== OSTDCR ========================================================= */ + #define R_SYSTEM_OSTDCR_OSTDE_Pos (7UL) /*!< OSTDE (Bit 7) */ + #define R_SYSTEM_OSTDCR_OSTDE_Msk (0x80UL) /*!< OSTDE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Pos (0UL) /*!< OSTDIE (Bit 0) */ + #define R_SYSTEM_OSTDCR_OSTDIE_Msk (0x1UL) /*!< OSTDIE (Bitfield-Mask: 0x01) */ +/* ======================================================== OSTDSR ========================================================= */ + #define R_SYSTEM_OSTDSR_OSTDF_Pos (0UL) /*!< OSTDF (Bit 0) */ + #define R_SYSTEM_OSTDSR_OSTDF_Msk (0x1UL) /*!< OSTDF (Bitfield-Mask: 0x01) */ +/* ========================================================= LPOPT ========================================================= */ + #define R_SYSTEM_LPOPT_LPOPTEN_Pos (7UL) /*!< LPOPTEN (Bit 7) */ + #define R_SYSTEM_LPOPT_LPOPTEN_Msk (0x80UL) /*!< LPOPTEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos (3UL) /*!< BPFCLKDIS (Bit 3) */ + #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk (0x8UL) /*!< BPFCLKDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Pos (1UL) /*!< DCLKDIS (Bit 1) */ + #define R_SYSTEM_LPOPT_DCLKDIS_Msk (0x6UL) /*!< DCLKDIS (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LPOPT_MPUDIS_Pos (0UL) /*!< MPUDIS (Bit 0) */ + #define R_SYSTEM_LPOPT_MPUDIS_Msk (0x1UL) /*!< MPUDIS (Bitfield-Mask: 0x01) */ +/* ======================================================= SLCDSCKCR ======================================================= */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos (7UL) /*!< LCDSCKEN (Bit 7) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk (0x80UL) /*!< LCDSCKEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos (0UL) /*!< LCDSCKSEL (Bit 0) */ + #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk (0x7UL) /*!< LCDSCKSEL (Bitfield-Mask: 0x07) */ +/* ======================================================== EBCKOCR ======================================================== */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos (0UL) /*!< EBCKOEN (Bit 0) */ + #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk (0x1UL) /*!< EBCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SDCKOCR ======================================================== */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos (0UL) /*!< SDCKOEN (Bit 0) */ + #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk (0x1UL) /*!< SDCKOEN (Bitfield-Mask: 0x01) */ +/* ======================================================= MOCOUTCR ======================================================== */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos (0UL) /*!< MOCOUTRM (Bit 0) */ + #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk (0xffUL) /*!< MOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================= HOCOUTCR ======================================================== */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos (0UL) /*!< HOCOUTRM (Bit 0) */ + #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk (0xffUL) /*!< HOCOUTRM (Bitfield-Mask: 0xff) */ +/* ========================================================= SNZCR ========================================================= */ + #define R_SYSTEM_SNZCR_SNZE_Pos (7UL) /*!< SNZE (Bit 7) */ + #define R_SYSTEM_SNZCR_SNZE_Msk (0x80UL) /*!< SNZE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Pos (1UL) /*!< SNZDTCEN (Bit 1) */ + #define R_SYSTEM_SNZCR_SNZDTCEN_Msk (0x2UL) /*!< SNZDTCEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Pos (0UL) /*!< RXDREQEN (Bit 0) */ + #define R_SYSTEM_SNZCR_RXDREQEN_Msk (0x1UL) /*!< RXDREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNZEDCR ======================================================== */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos (7UL) /*!< SCI0UMTED (Bit 7) */ + #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk (0x80UL) /*!< SCI0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos (6UL) /*!< AD1UMTED (Bit 6) */ + #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk (0x40UL) /*!< AD1UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Pos (5UL) /*!< AD1MATED (Bit 5) */ + #define R_SYSTEM_SNZEDCR_AD1MATED_Msk (0x20UL) /*!< AD1MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos (4UL) /*!< AD0UMTED (Bit 4) */ + #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk (0x10UL) /*!< AD0UMTED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Pos (3UL) /*!< AD0MATED (Bit 3) */ + #define R_SYSTEM_SNZEDCR_AD0MATED_Msk (0x8UL) /*!< AD0MATED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos (2UL) /*!< DTCNZRED (Bit 2) */ + #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk (0x4UL) /*!< DTCNZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Pos (1UL) /*!< DTCZRED (Bit 1) */ + #define R_SYSTEM_SNZEDCR_DTCZRED_Msk (0x2UL) /*!< DTCZRED (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos (0UL) /*!< AGT1UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk (0x1UL) /*!< AGT1UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR ======================================================== */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos (30UL) /*!< SNZREQEN30 (Bit 30) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos (29UL) /*!< SNZREQEN29 (Bit 29) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos (28UL) /*!< SNZREQEN28 (Bit 28) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos (25UL) /*!< SNZREQEN25 (Bit 25) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk (0x2000000UL) /*!< SNZREQEN25 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos (24UL) /*!< SNZREQEN24 (Bit 24) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk (0x1000000UL) /*!< SNZREQEN24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos (23UL) /*!< SNZREQEN23 (Bit 23) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk (0x800000UL) /*!< SNZREQEN23 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos (22UL) /*!< SNZREQEN22 (Bit 22) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk (0x400000UL) /*!< SNZREQEN22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos (17UL) /*!< SNZREQEN17 (Bit 17) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk (0x20000UL) /*!< SNZREQEN17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos (0UL) /*!< SNZREQEN (Bit 0) */ + #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk (0x1UL) /*!< SNZREQEN (Bitfield-Mask: 0x01) */ +/* ======================================================== FLSTOP ========================================================= */ + #define R_SYSTEM_FLSTOP_FLSTPF_Pos (4UL) /*!< FLSTPF (Bit 4) */ + #define R_SYSTEM_FLSTOP_FLSTPF_Msk (0x10UL) /*!< FLSTPF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Pos (0UL) /*!< FLSTOP (Bit 0) */ + #define R_SYSTEM_FLSTOP_FLSTOP_Msk (0x1UL) /*!< FLSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= PSMCR ========================================================= */ + #define R_SYSTEM_PSMCR_PSMC_Pos (0UL) /*!< PSMC (Bit 0) */ + #define R_SYSTEM_PSMCR_PSMC_Msk (0x3UL) /*!< PSMC (Bitfield-Mask: 0x03) */ +/* ========================================================= OPCCR ========================================================= */ + #define R_SYSTEM_OPCCR_OPCMTSF_Pos (4UL) /*!< OPCMTSF (Bit 4) */ + #define R_SYSTEM_OPCCR_OPCMTSF_Msk (0x10UL) /*!< OPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OPCCR_OPCM_Pos (0UL) /*!< OPCM (Bit 0) */ + #define R_SYSTEM_OPCCR_OPCM_Msk (0x3UL) /*!< OPCM (Bitfield-Mask: 0x03) */ +/* ======================================================== SOPCCR ========================================================= */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos (4UL) /*!< SOPCMTSF (Bit 4) */ + #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk (0x10UL) /*!< SOPCMTSF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SOPCCR_SOPCM_Pos (0UL) /*!< SOPCM (Bit 0) */ + #define R_SYSTEM_SOPCCR_SOPCM_Msk (0x1UL) /*!< SOPCM (Bitfield-Mask: 0x01) */ +/* ======================================================= MOSCWTCR ======================================================== */ + #define R_SYSTEM_MOSCWTCR_MSTS_Pos (0UL) /*!< MSTS (Bit 0) */ + #define R_SYSTEM_MOSCWTCR_MSTS_Msk (0xfUL) /*!< MSTS (Bitfield-Mask: 0x0f) */ +/* ======================================================= HOCOWTCR ======================================================== */ + #define R_SYSTEM_HOCOWTCR_HSTS_Pos (0UL) /*!< HSTS (Bit 0) */ + #define R_SYSTEM_HOCOWTCR_HSTS_Msk (0x7UL) /*!< HSTS (Bitfield-Mask: 0x07) */ +/* ======================================================== RSTSR1 ========================================================= */ + #define R_SYSTEM_RSTSR1_SPERF_Pos (12UL) /*!< SPERF (Bit 12) */ + #define R_SYSTEM_RSTSR1_SPERF_Msk (0x1000UL) /*!< SPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Pos (11UL) /*!< BUSMRF (Bit 11) */ + #define R_SYSTEM_RSTSR1_BUSMRF_Msk (0x800UL) /*!< BUSMRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Pos (10UL) /*!< BUSSRF (Bit 10) */ + #define R_SYSTEM_RSTSR1_BUSSRF_Msk (0x400UL) /*!< BUSSRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_REERF_Pos (9UL) /*!< REERF (Bit 9) */ + #define R_SYSTEM_RSTSR1_REERF_Msk (0x200UL) /*!< REERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_RPERF_Pos (8UL) /*!< RPERF (Bit 8) */ + #define R_SYSTEM_RSTSR1_RPERF_Msk (0x100UL) /*!< RPERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_SWRF_Pos (2UL) /*!< SWRF (Bit 2) */ + #define R_SYSTEM_RSTSR1_SWRF_Msk (0x4UL) /*!< SWRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_WDTRF_Pos (1UL) /*!< WDTRF (Bit 1) */ + #define R_SYSTEM_RSTSR1_WDTRF_Msk (0x2UL) /*!< WDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Pos (0UL) /*!< IWDTRF (Bit 0) */ + #define R_SYSTEM_RSTSR1_IWDTRF_Msk (0x1UL) /*!< IWDTRF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_TZERF_Pos (13UL) /*!< TZERF (Bit 13) */ + #define R_SYSTEM_RSTSR1_TZERF_Msk (0x2000UL) /*!< TZERF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR1_CPERF_Pos (15UL) /*!< CPERF (Bit 15) */ + #define R_SYSTEM_RSTSR1_CPERF_Msk (0x8000UL) /*!< CPERF (Bitfield-Mask: 0x01) */ +/* ======================================================== STCONR ========================================================= */ + #define R_SYSTEM_STCONR_STCON_Pos (0UL) /*!< STCON (Bit 0) */ + #define R_SYSTEM_STCONR_STCON_Msk (0x3UL) /*!< STCON (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD1CR1 ======================================================== */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD1CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD1CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LVD2CR1 ======================================================== */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Pos (2UL) /*!< IRQSEL (Bit 2) */ + #define R_SYSTEM_LVD2CR1_IRQSEL_Msk (0x4UL) /*!< IRQSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Pos (0UL) /*!< IDTSEL (Bit 0) */ + #define R_SYSTEM_LVD2CR1_IDTSEL_Msk (0x3UL) /*!< IDTSEL (Bitfield-Mask: 0x03) */ +/* ====================================================== USBCKCR_ALT ====================================================== */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos (0UL) /*!< USBCLKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk (0x1UL) /*!< USBCLKSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= SDADCCKCR ======================================================= */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos (0UL) /*!< SDADCCKSEL (Bit 0) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk (0x1UL) /*!< SDADCCKSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos (7UL) /*!< SDADCCKEN (Bit 7) */ + #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk (0x80UL) /*!< SDADCCKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1SR ========================================================= */ + #define R_SYSTEM_LVD1SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD1SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD1SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2SR ========================================================= */ + #define R_SYSTEM_LVD2SR_MON_Pos (1UL) /*!< MON (Bit 1) */ + #define R_SYSTEM_LVD2SR_MON_Msk (0x2UL) /*!< MON (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2SR_DET_Pos (0UL) /*!< DET (Bit 0) */ + #define R_SYSTEM_LVD2SR_DET_Msk (0x1UL) /*!< DET (Bitfield-Mask: 0x01) */ +/* ========================================================= PRCR ========================================================== */ + #define R_SYSTEM_PRCR_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_SYSTEM_PRCR_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + #define R_SYSTEM_PRCR_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_SYSTEM_PRCR_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_SYSTEM_PRCR_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_SYSTEM_PRCR_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PRCR_PRC4_Pos (4UL) /*!< PRC4 (Bit 4) */ + #define R_SYSTEM_PRCR_PRC4_Msk (0x10UL) /*!< PRC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER0 ======================================================== */ + #define R_SYSTEM_DPSIER0_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER0_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER1 ======================================================== */ + #define R_SYSTEM_DPSIER1_DIRQE_Pos (0UL) /*!< DIRQE (Bit 0) */ + #define R_SYSTEM_DPSIER1_DIRQE_Msk (0x1UL) /*!< DIRQE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER2 ======================================================== */ + #define R_SYSTEM_DPSIER2_DNMIE_Pos (4UL) /*!< DNMIE (Bit 4) */ + #define R_SYSTEM_DPSIER2_DNMIE_Msk (0x10UL) /*!< DNMIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Pos (3UL) /*!< DRTCAIE (Bit 3) */ + #define R_SYSTEM_DPSIER2_DRTCAIE_Msk (0x8UL) /*!< DRTCAIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos (2UL) /*!< DTRTCIIE (Bit 2) */ + #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk (0x4UL) /*!< DTRTCIIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Pos (1UL) /*!< DLVD2IE (Bit 1) */ + #define R_SYSTEM_DPSIER2_DLVD2IE_Msk (0x2UL) /*!< DLVD2IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Pos (0UL) /*!< DLVD1IE (Bit 0) */ + #define R_SYSTEM_DPSIER2_DLVD1IE_Msk (0x1UL) /*!< DLVD1IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIER3 ======================================================== */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Pos (2UL) /*!< DAGT1IE (Bit 2) */ + #define R_SYSTEM_DPSIER3_DAGT1IE_Msk (0x4UL) /*!< DAGT1IE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos (1UL) /*!< DUSBHSIE (Bit 1) */ + #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk (0x2UL) /*!< DUSBHSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos (0UL) /*!< DUSBFSIE (Bit 0) */ + #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk (0x1UL) /*!< DUSBFSIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Pos (3UL) /*!< DAGT3IE (Bit 3) */ + #define R_SYSTEM_DPSIER3_DAGT3IE_Msk (0x8UL) /*!< DAGT3IE (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR0 ======================================================== */ + #define R_SYSTEM_DPSIFR0_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR0_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR1 ======================================================== */ + #define R_SYSTEM_DPSIFR1_DIRQF_Pos (0UL) /*!< DIRQF (Bit 0) */ + #define R_SYSTEM_DPSIFR1_DIRQF_Msk (0x1UL) /*!< DIRQF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR2 ======================================================== */ + #define R_SYSTEM_DPSIFR2_DNMIF_Pos (4UL) /*!< DNMIF (Bit 4) */ + #define R_SYSTEM_DPSIFR2_DNMIF_Msk (0x10UL) /*!< DNMIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos (3UL) /*!< DRTCAIF (Bit 3) */ + #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk (0x8UL) /*!< DRTCAIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos (2UL) /*!< DTRTCIIF (Bit 2) */ + #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk (0x4UL) /*!< DTRTCIIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos (1UL) /*!< DLVD2IF (Bit 1) */ + #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk (0x2UL) /*!< DLVD2IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos (0UL) /*!< DLVD1IF (Bit 0) */ + #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk (0x1UL) /*!< DLVD1IF (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSIFR3 ======================================================== */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos (2UL) /*!< DAGT1IF (Bit 2) */ + #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk (0x4UL) /*!< DAGT1IF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos (1UL) /*!< DUSBHSIF (Bit 1) */ + #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk (0x2UL) /*!< DUSBHSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos (0UL) /*!< DUSBFSIF (Bit 0) */ + #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk (0x1UL) /*!< DUSBFSIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos (3UL) /*!< DAGT3IF (Bit 3) */ + #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk (0x8UL) /*!< DAGT3IF (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR0 ======================================================== */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR1 ======================================================== */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos (0UL) /*!< DIRQEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk (0x1UL) /*!< DIRQEG (Bitfield-Mask: 0x01) */ +/* ======================================================= DPSIEGR2 ======================================================== */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos (4UL) /*!< DNMIEG (Bit 4) */ + #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk (0x10UL) /*!< DNMIEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos (1UL) /*!< DLVD2IEG (Bit 1) */ + #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk (0x2UL) /*!< DLVD2IEG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos (0UL) /*!< DLVD1IEG (Bit 0) */ + #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk (0x1UL) /*!< DLVD1IEG (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSBYCR ======================================================== */ + #define R_SYSTEM_DPSBYCR_DPSBY_Pos (7UL) /*!< DPSBY (Bit 7) */ + #define R_SYSTEM_DPSBYCR_DPSBY_Msk (0x80UL) /*!< DPSBY (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Pos (6UL) /*!< IOKEEP (Bit 6) */ + #define R_SYSTEM_DPSBYCR_IOKEEP_Msk (0x40UL) /*!< IOKEEP (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos (0UL) /*!< DEEPCUT (Bit 0) */ + #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk (0x3UL) /*!< DEEPCUT (Bitfield-Mask: 0x03) */ +/* ======================================================== SYOCDCR ======================================================== */ + #define R_SYSTEM_SYOCDCR_DBGEN_Pos (7UL) /*!< DBGEN (Bit 7) */ + #define R_SYSTEM_SYOCDCR_DBGEN_Msk (0x80UL) /*!< DBGEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Pos (0UL) /*!< DOCDF (Bit 0) */ + #define R_SYSTEM_SYOCDCR_DOCDF_Msk (0x1UL) /*!< DOCDF (Bitfield-Mask: 0x01) */ +/* ========================================================= MOMCR ========================================================= */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Pos (7UL) /*!< AUTODRVEN (Bit 7) */ + #define R_SYSTEM_MOMCR_AUTODRVEN_Msk (0x80UL) /*!< AUTODRVEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MOSEL_Pos (6UL) /*!< MOSEL (Bit 6) */ + #define R_SYSTEM_MOMCR_MOSEL_Msk (0x40UL) /*!< MOSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_MOMCR_MODRV0_Pos (4UL) /*!< MODRV0 (Bit 4) */ + #define R_SYSTEM_MOMCR_MODRV0_Msk (0x30UL) /*!< MODRV0 (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_MOMCR_MODRV1_Pos (3UL) /*!< MODRV1 (Bit 3) */ + #define R_SYSTEM_MOMCR_MODRV1_Msk (0x8UL) /*!< MODRV1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Pos (7UL) /*!< DPSRSTF (Bit 7) */ + #define R_SYSTEM_RSTSR0_DPSRSTF_Msk (0x80UL) /*!< DPSRSTF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Pos (3UL) /*!< LVD2RF (Bit 3) */ + #define R_SYSTEM_RSTSR0_LVD2RF_Msk (0x8UL) /*!< LVD2RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Pos (2UL) /*!< LVD1RF (Bit 2) */ + #define R_SYSTEM_RSTSR0_LVD1RF_Msk (0x4UL) /*!< LVD1RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Pos (1UL) /*!< LVD0RF (Bit 1) */ + #define R_SYSTEM_RSTSR0_LVD0RF_Msk (0x2UL) /*!< LVD0RF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSR0_PORF_Pos (0UL) /*!< PORF (Bit 0) */ + #define R_SYSTEM_RSTSR0_PORF_Msk (0x1UL) /*!< PORF (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR2 ========================================================= */ + #define R_SYSTEM_RSTSR2_CWSF_Pos (0UL) /*!< CWSF (Bit 0) */ + #define R_SYSTEM_RSTSR2_CWSF_Msk (0x1UL) /*!< CWSF (Bitfield-Mask: 0x01) */ +/* ======================================================== LVCMPCR ======================================================== */ + #define R_SYSTEM_LVCMPCR_LVD2E_Pos (6UL) /*!< LVD2E (Bit 6) */ + #define R_SYSTEM_LVCMPCR_LVD2E_Msk (0x40UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Pos (5UL) /*!< LVD1E (Bit 5) */ + #define R_SYSTEM_LVCMPCR_LVD1E_Msk (0x20UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================= LVD1CMPCR ======================================================= */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos (7UL) /*!< LVD1E (Bit 7) */ + #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk (0x80UL) /*!< LVD1E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDLVLR ======================================================== */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos (5UL) /*!< LVD2LVL (Bit 5) */ + #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk (0xe0UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos (0UL) /*!< LVD1LVL (Bit 0) */ + #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk (0x1fUL) /*!< LVD1LVL (Bitfield-Mask: 0x1f) */ +/* ======================================================= LVD2CMPCR ======================================================= */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos (0UL) /*!< LVD2LVL (Bit 0) */ + #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk (0x7UL) /*!< LVD2LVL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos (7UL) /*!< LVD2E (Bit 7) */ + #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk (0x80UL) /*!< LVD2E (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD1CR0 ======================================================== */ + #define R_SYSTEM_LVD1CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD1CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD1CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD1CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD1CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD1CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD1CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD1CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD1CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== LVD2CR0 ======================================================== */ + #define R_SYSTEM_LVD2CR0_RN_Pos (7UL) /*!< RN (Bit 7) */ + #define R_SYSTEM_LVD2CR0_RN_Msk (0x80UL) /*!< RN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_SYSTEM_LVD2CR0_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Pos (4UL) /*!< FSAMP (Bit 4) */ + #define R_SYSTEM_LVD2CR0_FSAMP_Msk (0x30UL) /*!< FSAMP (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_LVD2CR0_CMPE_Pos (2UL) /*!< CMPE (Bit 2) */ + #define R_SYSTEM_LVD2CR0_CMPE_Msk (0x4UL) /*!< CMPE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Pos (1UL) /*!< DFDIS (Bit 1) */ + #define R_SYSTEM_LVD2CR0_DFDIS_Msk (0x2UL) /*!< DFDIS (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVD2CR0_RIE_Pos (0UL) /*!< RIE (Bit 0) */ + #define R_SYSTEM_LVD2CR0_RIE_Msk (0x1UL) /*!< RIE (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTCR1 ========================================================= */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos (0UL) /*!< BPWSWSTP (Bit 0) */ + #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk (0x1UL) /*!< BPWSWSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== DCDCCTL ======================================================== */ + #define R_SYSTEM_DCDCCTL_PD_Pos (7UL) /*!< PD (Bit 7) */ + #define R_SYSTEM_DCDCCTL_PD_Msk (0x80UL) /*!< PD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_FST_Pos (6UL) /*!< FST (Bit 6) */ + #define R_SYSTEM_DCDCCTL_FST_Msk (0x40UL) /*!< FST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Pos (5UL) /*!< LCBOOST (Bit 5) */ + #define R_SYSTEM_DCDCCTL_LCBOOST_Msk (0x20UL) /*!< LCBOOST (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Pos (4UL) /*!< STOPZA (Bit 4) */ + #define R_SYSTEM_DCDCCTL_STOPZA_Msk (0x10UL) /*!< STOPZA (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Pos (1UL) /*!< OCPEN (Bit 1) */ + #define R_SYSTEM_DCDCCTL_OCPEN_Msk (0x2UL) /*!< OCPEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Pos (0UL) /*!< DCDCON (Bit 0) */ + #define R_SYSTEM_DCDCCTL_DCDCON_Msk (0x1UL) /*!< DCDCON (Bitfield-Mask: 0x01) */ +/* ======================================================== VCCSEL ========================================================= */ + #define R_SYSTEM_VCCSEL_VCCSEL_Pos (0UL) /*!< VCCSEL (Bit 0) */ + #define R_SYSTEM_VCCSEL_VCCSEL_Msk (0x3UL) /*!< VCCSEL (Bitfield-Mask: 0x03) */ +/* ======================================================== LDOSCR ========================================================= */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Pos (0UL) /*!< LDOSTP0 (Bit 0) */ + #define R_SYSTEM_LDOSCR_LDOSTP0_Msk (0x1UL) /*!< LDOSTP0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Pos (1UL) /*!< LDOSTP1 (Bit 1) */ + #define R_SYSTEM_LDOSCR_LDOSTP1_Msk (0x2UL) /*!< LDOSTP1 (Bitfield-Mask: 0x01) */ +/* ======================================================= PL2LDOSCR ======================================================= */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos (0UL) /*!< PL2LDOSTP (Bit 0) */ + #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk (0x1UL) /*!< PL2LDOSTP (Bitfield-Mask: 0x01) */ +/* ======================================================== SOSCCR ========================================================= */ + #define R_SYSTEM_SOSCCR_SOSTP_Pos (0UL) /*!< SOSTP (Bit 0) */ + #define R_SYSTEM_SOSCCR_SOSTP_Msk (0x1UL) /*!< SOSTP (Bitfield-Mask: 0x01) */ +/* ========================================================= SOMCR ========================================================= */ + #define R_SYSTEM_SOMCR_SODRV_Pos (0UL) /*!< SODRV (Bit 0) */ + #define R_SYSTEM_SOMCR_SODRV_Msk (0x3UL) /*!< SODRV (Bitfield-Mask: 0x03) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSTEM_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSTEM_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= LOCOUTCR ======================================================== */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos (0UL) /*!< LOCOUTRM (Bit 0) */ + #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk (0xffUL) /*!< LOCOUTRM (Bitfield-Mask: 0xff) */ +/* ======================================================== VBTCR2 ========================================================= */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos (6UL) /*!< VBTLVDLVL (Bit 6) */ + #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk (0xc0UL) /*!< VBTLVDLVL (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos (4UL) /*!< VBTLVDEN (Bit 4) */ + #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk (0x10UL) /*!< VBTLVDEN (Bitfield-Mask: 0x01) */ +/* ========================================================= VBTSR ========================================================= */ + #define R_SYSTEM_VBTSR_VBTRVLD_Pos (4UL) /*!< VBTRVLD (Bit 4) */ + #define R_SYSTEM_VBTSR_VBTRVLD_Msk (0x10UL) /*!< VBTRVLD (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Pos (1UL) /*!< VBTBLDF (Bit 1) */ + #define R_SYSTEM_VBTSR_VBTBLDF_Msk (0x2UL) /*!< VBTBLDF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTSR_VBTRDF_Pos (0UL) /*!< VBTRDF (Bit 0) */ + #define R_SYSTEM_VBTSR_VBTRDF_Msk (0x1UL) /*!< VBTRDF (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTCMPCR ======================================================== */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos (0UL) /*!< VBTCMPE (Bit 0) */ + #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk (0x1UL) /*!< VBTCMPE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTLVDICR ======================================================= */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos (1UL) /*!< VBTLVDISEL (Bit 1) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk (0x2UL) /*!< VBTLVDISEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos (0UL) /*!< VBTLVDIE (Bit 0) */ + #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk (0x1UL) /*!< VBTLVDIE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTWCTLR ======================================================== */ + #define R_SYSTEM_VBTWCTLR_VWEN_Pos (0UL) /*!< VWEN (Bit 0) */ + #define R_SYSTEM_VBTWCTLR_VWEN_Msk (0x1UL) /*!< VWEN (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH0OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos (5UL) /*!< CH0VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk (0x20UL) /*!< CH0VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos (4UL) /*!< CH0VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk (0x10UL) /*!< CH0VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos (3UL) /*!< CH0VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk (0x8UL) /*!< CH0VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos (2UL) /*!< CH0VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk (0x4UL) /*!< CH0VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos (1UL) /*!< CH0VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk (0x2UL) /*!< CH0VCH1TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH1OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos (5UL) /*!< CH1VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk (0x20UL) /*!< CH1VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos (4UL) /*!< CH1VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk (0x10UL) /*!< CH1VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos (3UL) /*!< CH1VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk (0x8UL) /*!< CH1VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos (2UL) /*!< CH1VCH2TE (Bit 2) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk (0x4UL) /*!< CH1VCH2TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos (0UL) /*!< CH1VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk (0x1UL) /*!< CH1VCH0TE (Bitfield-Mask: 0x01) */ +/* ====================================================== VBTWCH2OTSR ====================================================== */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos (5UL) /*!< CH2VAGTUTE (Bit 5) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk (0x20UL) /*!< CH2VAGTUTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos (4UL) /*!< CH2VRTCATE (Bit 4) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk (0x10UL) /*!< CH2VRTCATE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos (3UL) /*!< CH2VRTCTE (Bit 3) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk (0x8UL) /*!< CH2VRTCTE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos (1UL) /*!< CH2VCH1TE (Bit 1) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk (0x2UL) /*!< CH2VCH1TE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos (0UL) /*!< CH2VCH0TE (Bit 0) */ + #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk (0x1UL) /*!< CH2VCH0TE (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTICTLR ======================================================== */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos (2UL) /*!< VCH2INEN (Bit 2) */ + #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk (0x4UL) /*!< VCH2INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos (1UL) /*!< VCH1INEN (Bit 1) */ + #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk (0x2UL) /*!< VCH1INEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos (0UL) /*!< VCH0INEN (Bit 0) */ + #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk (0x1UL) /*!< VCH0INEN (Bitfield-Mask: 0x01) */ +/* ======================================================= VBTOCTLR ======================================================== */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos (5UL) /*!< VOUT2LSEL (Bit 5) */ + #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk (0x20UL) /*!< VOUT2LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos (4UL) /*!< VCOU1LSEL (Bit 4) */ + #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk (0x10UL) /*!< VCOU1LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos (3UL) /*!< VOUT0LSEL (Bit 3) */ + #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk (0x8UL) /*!< VOUT0LSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos (2UL) /*!< VCH2OEN (Bit 2) */ + #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk (0x4UL) /*!< VCH2OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos (1UL) /*!< VCH1OEN (Bit 1) */ + #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk (0x2UL) /*!< VCH1OEN (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos (0UL) /*!< VCH0OEN (Bit 0) */ + #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk (0x1UL) /*!< VCH0OEN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWTER ======================================================== */ + #define R_SYSTEM_VBTWTER_VAGTUE_Pos (5UL) /*!< VAGTUE (Bit 5) */ + #define R_SYSTEM_VBTWTER_VAGTUE_Msk (0x20UL) /*!< VAGTUE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Pos (4UL) /*!< VRTCAE (Bit 4) */ + #define R_SYSTEM_VBTWTER_VRTCAE_Msk (0x10UL) /*!< VRTCAE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Pos (3UL) /*!< VRTCIE (Bit 3) */ + #define R_SYSTEM_VBTWTER_VRTCIE_Msk (0x8UL) /*!< VRTCIE (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH2E_Pos (2UL) /*!< VCH2E (Bit 2) */ + #define R_SYSTEM_VBTWTER_VCH2E_Msk (0x4UL) /*!< VCH2E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH1E_Pos (1UL) /*!< VCH1E (Bit 1) */ + #define R_SYSTEM_VBTWTER_VCH1E_Msk (0x2UL) /*!< VCH1E (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWTER_VCH0E_Pos (0UL) /*!< VCH0E (Bit 0) */ + #define R_SYSTEM_VBTWTER_VCH0E_Msk (0x1UL) /*!< VCH0E (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWEGR ======================================================== */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Pos (2UL) /*!< VCH2EG (Bit 2) */ + #define R_SYSTEM_VBTWEGR_VCH2EG_Msk (0x4UL) /*!< VCH2EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Pos (1UL) /*!< VCH1EG (Bit 1) */ + #define R_SYSTEM_VBTWEGR_VCH1EG_Msk (0x2UL) /*!< VCH1EG (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Pos (0UL) /*!< VCH0EG (Bit 0) */ + #define R_SYSTEM_VBTWEGR_VCH0EG_Msk (0x1UL) /*!< VCH0EG (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTWFR ========================================================= */ + #define R_SYSTEM_VBTWFR_VAGTUF_Pos (5UL) /*!< VAGTUF (Bit 5) */ + #define R_SYSTEM_VBTWFR_VAGTUF_Msk (0x20UL) /*!< VAGTUF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Pos (4UL) /*!< VRTCAF (Bit 4) */ + #define R_SYSTEM_VBTWFR_VRTCAF_Msk (0x10UL) /*!< VRTCAF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Pos (3UL) /*!< VRTCIF (Bit 3) */ + #define R_SYSTEM_VBTWFR_VRTCIF_Msk (0x8UL) /*!< VRTCIF (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH2F_Pos (2UL) /*!< VCH2F (Bit 2) */ + #define R_SYSTEM_VBTWFR_VCH2F_Msk (0x4UL) /*!< VCH2F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH1F_Pos (1UL) /*!< VCH1F (Bit 1) */ + #define R_SYSTEM_VBTWFR_VCH1F_Msk (0x2UL) /*!< VCH1F (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_VBTWFR_VCH0F_Pos (0UL) /*!< VCH0F (Bit 0) */ + #define R_SYSTEM_VBTWFR_VCH0F_Msk (0x1UL) /*!< VCH0F (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBKR ========================================================= */ + #define R_SYSTEM_VBTBKR_VBTBKR_Pos (0UL) /*!< VBTBKR (Bit 0) */ + #define R_SYSTEM_VBTBKR_VBTBKR_Msk (0xffUL) /*!< VBTBKR (Bitfield-Mask: 0xff) */ +/* ======================================================== FWEPROR ======================================================== */ + #define R_SYSTEM_FWEPROR_FLWE_Pos (0UL) /*!< FLWE (Bit 0) */ + #define R_SYSTEM_FWEPROR_FLWE_Msk (0x3UL) /*!< FLWE (Bitfield-Mask: 0x03) */ +/* ======================================================== PLL2CCR ======================================================== */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos (0UL) /*!< PL2IDIV (Bit 0) */ + #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk (0x3UL) /*!< PL2IDIV (Bitfield-Mask: 0x03) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos (4UL) /*!< PL2SRCSEL (Bit 4) */ + #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk (0x10UL) /*!< PL2SRCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos (8UL) /*!< PLL2MUL (Bit 8) */ + #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk (0x3f00UL) /*!< PLL2MUL (Bitfield-Mask: 0x3f) */ +/* ======================================================== PLL2CR ========================================================= */ + #define R_SYSTEM_PLL2CR_PLL2STP_Pos (0UL) /*!< PLL2STP (Bit 0) */ + #define R_SYSTEM_PLL2CR_PLL2STP_Msk (0x1UL) /*!< PLL2STP (Bitfield-Mask: 0x01) */ +/* ====================================================== USBCKDIVCR ======================================================= */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos (0UL) /*!< USBCKDIV (Bit 0) */ + #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk (0x7UL) /*!< USBCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== OCTACKDIVCR ====================================================== */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos (0UL) /*!< OCTACKDIV (Bit 0) */ + #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk (0x7UL) /*!< OCTACKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== SCISPICKDIVCR ===================================================== */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos (0UL) /*!< SCISPICKDIV (Bit 0) */ + #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk (0x7UL) /*!< SCISPICKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== CANFDCKDIVCR ====================================================== */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos (0UL) /*!< CANFDCKDIV (Bit 0) */ + #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk (0x7UL) /*!< CANFDCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== GPTCKDIVCR ======================================================= */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ + #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== IICCKDIVCR ======================================================= */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ + #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ +/* ======================================================== USBCKCR ======================================================== */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Pos (0UL) /*!< USBCKSEL (Bit 0) */ + #define R_SYSTEM_USBCKCR_USBCKSEL_Msk (0x7UL) /*!< USBCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos (6UL) /*!< USBCKSREQ (Bit 6) */ + #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk (0x40UL) /*!< USBCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos (7UL) /*!< USBCKSRDY (Bit 7) */ + #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk (0x80UL) /*!< USBCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= OCTACKCR ======================================================== */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos (0UL) /*!< OCTACKSEL (Bit 0) */ + #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk (0x7UL) /*!< OCTACKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos (6UL) /*!< OCTACKSREQ (Bit 6) */ + #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk (0x40UL) /*!< OCTACKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos (7UL) /*!< OCTACKSRDY (Bit 7) */ + #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk (0x80UL) /*!< OCTACKSRDY (Bitfield-Mask: 0x01) */ +/* ====================================================== SCISPICKCR ======================================================= */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos (0UL) /*!< SCISPICKSEL (Bit 0) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk (0x7UL) /*!< SCISPICKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos (6UL) /*!< SCISPICKSREQ (Bit 6) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk (0x40UL) /*!< SCISPICKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos (7UL) /*!< SCISPICKSRDY (Bit 7) */ + #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk (0x80UL) /*!< SCISPICKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= CANFDCKCR ======================================================= */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos (0UL) /*!< CANFDCKSEL (Bit 0) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk (0x7UL) /*!< CANFDCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos (6UL) /*!< CANFDCKSREQ (Bit 6) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk (0x40UL) /*!< CANFDCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos (7UL) /*!< CANFDCKSRDY (Bit 7) */ + #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk (0x80UL) /*!< CANFDCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== GPTCKCR ======================================================== */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos (0UL) /*!< GPTCKSEL (Bit 0) */ + #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk (0x7UL) /*!< GPTCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos (6UL) /*!< GPTCKSREQ (Bit 6) */ + #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ + #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== IICCKCR ======================================================== */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ + #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos (6UL) /*!< IICCKSREQ (Bit 6) */ + #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ + #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZREQCR1 ======================================================= */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos (1UL) /*!< SNZREQEN1 (Bit 1) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk (0x2UL) /*!< SNZREQEN1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos (2UL) /*!< SNZREQEN2 (Bit 2) */ + #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk (0x4UL) /*!< SNZREQEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= SNZEDCR1 ======================================================== */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos (0UL) /*!< AGT3UNFED (Bit 0) */ + #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk (0x1UL) /*!< AGT3UNFED (Bitfield-Mask: 0x01) */ +/* ======================================================== CGFSAR ========================================================= */ + #define R_SYSTEM_CGFSAR_NONSEC00_Pos (0UL) /*!< NONSEC00 (Bit 0) */ + #define R_SYSTEM_CGFSAR_NONSEC00_Msk (0x1UL) /*!< NONSEC00 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Pos (2UL) /*!< NONSEC02 (Bit 2) */ + #define R_SYSTEM_CGFSAR_NONSEC02_Msk (0x4UL) /*!< NONSEC02 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Pos (3UL) /*!< NONSEC03 (Bit 3) */ + #define R_SYSTEM_CGFSAR_NONSEC03_Msk (0x8UL) /*!< NONSEC03 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Pos (4UL) /*!< NONSEC04 (Bit 4) */ + #define R_SYSTEM_CGFSAR_NONSEC04_Msk (0x10UL) /*!< NONSEC04 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Pos (5UL) /*!< NONSEC05 (Bit 5) */ + #define R_SYSTEM_CGFSAR_NONSEC05_Msk (0x20UL) /*!< NONSEC05 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Pos (6UL) /*!< NONSEC06 (Bit 6) */ + #define R_SYSTEM_CGFSAR_NONSEC06_Msk (0x40UL) /*!< NONSEC06 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Pos (7UL) /*!< NONSEC07 (Bit 7) */ + #define R_SYSTEM_CGFSAR_NONSEC07_Msk (0x80UL) /*!< NONSEC07 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Pos (8UL) /*!< NONSEC08 (Bit 8) */ + #define R_SYSTEM_CGFSAR_NONSEC08_Msk (0x100UL) /*!< NONSEC08 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Pos (9UL) /*!< NONSEC09 (Bit 9) */ + #define R_SYSTEM_CGFSAR_NONSEC09_Msk (0x200UL) /*!< NONSEC09 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Pos (11UL) /*!< NONSEC11 (Bit 11) */ + #define R_SYSTEM_CGFSAR_NONSEC11_Msk (0x800UL) /*!< NONSEC11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Pos (12UL) /*!< NONSEC12 (Bit 12) */ + #define R_SYSTEM_CGFSAR_NONSEC12_Msk (0x1000UL) /*!< NONSEC12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_CGFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_CGFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ +/* ======================================================== LPMSAR ========================================================= */ + #define R_SYSTEM_LPMSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LPMSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_LPMSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Pos (4UL) /*!< NONSEC4 (Bit 4) */ + #define R_SYSTEM_LPMSAR_NONSEC4_Msk (0x10UL) /*!< NONSEC4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Pos (8UL) /*!< NONSEC8 (Bit 8) */ + #define R_SYSTEM_LPMSAR_NONSEC8_Msk (0x100UL) /*!< NONSEC8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Pos (9UL) /*!< NONSEC9 (Bit 9) */ + #define R_SYSTEM_LPMSAR_NONSEC9_Msk (0x200UL) /*!< NONSEC9 (Bitfield-Mask: 0x01) */ +/* ======================================================== LVDSAR ========================================================= */ + #define R_SYSTEM_LVDSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_LVDSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_LVDSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSAR ========================================================= */ + #define R_SYSTEM_RSTSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_RSTSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_RSTSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_RSTSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ +/* ======================================================== BBFSAR ========================================================= */ + #define R_SYSTEM_BBFSAR_NONSEC0_Pos (0UL) /*!< NONSEC0 (Bit 0) */ + #define R_SYSTEM_BBFSAR_NONSEC0_Msk (0x1UL) /*!< NONSEC0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Pos (1UL) /*!< NONSEC1 (Bit 1) */ + #define R_SYSTEM_BBFSAR_NONSEC1_Msk (0x2UL) /*!< NONSEC1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Pos (2UL) /*!< NONSEC2 (Bit 2) */ + #define R_SYSTEM_BBFSAR_NONSEC2_Msk (0x4UL) /*!< NONSEC2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Pos (16UL) /*!< NONSEC16 (Bit 16) */ + #define R_SYSTEM_BBFSAR_NONSEC16_Msk (0x10000UL) /*!< NONSEC16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Pos (17UL) /*!< NONSEC17 (Bit 17) */ + #define R_SYSTEM_BBFSAR_NONSEC17_Msk (0x20000UL) /*!< NONSEC17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Pos (18UL) /*!< NONSEC18 (Bit 18) */ + #define R_SYSTEM_BBFSAR_NONSEC18_Msk (0x40000UL) /*!< NONSEC18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Pos (19UL) /*!< NONSEC19 (Bit 19) */ + #define R_SYSTEM_BBFSAR_NONSEC19_Msk (0x80000UL) /*!< NONSEC19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Pos (20UL) /*!< NONSEC20 (Bit 20) */ + #define R_SYSTEM_BBFSAR_NONSEC20_Msk (0x100000UL) /*!< NONSEC20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Pos (21UL) /*!< NONSEC21 (Bit 21) */ + #define R_SYSTEM_BBFSAR_NONSEC21_Msk (0x200000UL) /*!< NONSEC21 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Pos (22UL) /*!< NONSEC22 (Bit 22) */ + #define R_SYSTEM_BBFSAR_NONSEC22_Msk (0x400000UL) /*!< NONSEC22 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Pos (23UL) /*!< NONSEC23 (Bit 23) */ + #define R_SYSTEM_BBFSAR_NONSEC23_Msk (0x800000UL) /*!< NONSEC23 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPFSAR ========================================================= */ + #define R_SYSTEM_DPFSAR_DPFSA0_Pos (0UL) /*!< DPFSA0 (Bit 0) */ + #define R_SYSTEM_DPFSAR_DPFSA0_Msk (0x1UL) /*!< DPFSA0 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Pos (1UL) /*!< DPFSA1 (Bit 1) */ + #define R_SYSTEM_DPFSAR_DPFSA1_Msk (0x2UL) /*!< DPFSA1 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Pos (2UL) /*!< DPFSA2 (Bit 2) */ + #define R_SYSTEM_DPFSAR_DPFSA2_Msk (0x4UL) /*!< DPFSA2 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Pos (3UL) /*!< DPFSA3 (Bit 3) */ + #define R_SYSTEM_DPFSAR_DPFSA3_Msk (0x8UL) /*!< DPFSA3 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Pos (4UL) /*!< DPFSA4 (Bit 4) */ + #define R_SYSTEM_DPFSAR_DPFSA4_Msk (0x10UL) /*!< DPFSA4 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Pos (5UL) /*!< DPFSA5 (Bit 5) */ + #define R_SYSTEM_DPFSAR_DPFSA5_Msk (0x20UL) /*!< DPFSA5 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Pos (6UL) /*!< DPFSA6 (Bit 6) */ + #define R_SYSTEM_DPFSAR_DPFSA6_Msk (0x40UL) /*!< DPFSA6 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Pos (7UL) /*!< DPFSA7 (Bit 7) */ + #define R_SYSTEM_DPFSAR_DPFSA7_Msk (0x80UL) /*!< DPFSA7 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Pos (8UL) /*!< DPFSA8 (Bit 8) */ + #define R_SYSTEM_DPFSAR_DPFSA8_Msk (0x100UL) /*!< DPFSA8 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Pos (9UL) /*!< DPFSA9 (Bit 9) */ + #define R_SYSTEM_DPFSAR_DPFSA9_Msk (0x200UL) /*!< DPFSA9 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Pos (10UL) /*!< DPFSA10 (Bit 10) */ + #define R_SYSTEM_DPFSAR_DPFSA10_Msk (0x400UL) /*!< DPFSA10 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Pos (11UL) /*!< DPFSA11 (Bit 11) */ + #define R_SYSTEM_DPFSAR_DPFSA11_Msk (0x800UL) /*!< DPFSA11 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Pos (12UL) /*!< DPFSA12 (Bit 12) */ + #define R_SYSTEM_DPFSAR_DPFSA12_Msk (0x1000UL) /*!< DPFSA12 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Pos (13UL) /*!< DPFSA13 (Bit 13) */ + #define R_SYSTEM_DPFSAR_DPFSA13_Msk (0x2000UL) /*!< DPFSA13 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Pos (14UL) /*!< DPFSA14 (Bit 14) */ + #define R_SYSTEM_DPFSAR_DPFSA14_Msk (0x4000UL) /*!< DPFSA14 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Pos (15UL) /*!< DPFSA15 (Bit 15) */ + #define R_SYSTEM_DPFSAR_DPFSA15_Msk (0x8000UL) /*!< DPFSA15 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Pos (16UL) /*!< DPFSA16 (Bit 16) */ + #define R_SYSTEM_DPFSAR_DPFSA16_Msk (0x10000UL) /*!< DPFSA16 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Pos (17UL) /*!< DPFSA17 (Bit 17) */ + #define R_SYSTEM_DPFSAR_DPFSA17_Msk (0x20000UL) /*!< DPFSA17 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Pos (18UL) /*!< DPFSA18 (Bit 18) */ + #define R_SYSTEM_DPFSAR_DPFSA18_Msk (0x40000UL) /*!< DPFSA18 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Pos (19UL) /*!< DPFSA19 (Bit 19) */ + #define R_SYSTEM_DPFSAR_DPFSA19_Msk (0x80000UL) /*!< DPFSA19 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Pos (20UL) /*!< DPFSA20 (Bit 20) */ + #define R_SYSTEM_DPFSAR_DPFSA20_Msk (0x100000UL) /*!< DPFSA20 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Pos (24UL) /*!< DPFSA24 (Bit 24) */ + #define R_SYSTEM_DPFSAR_DPFSA24_Msk (0x1000000UL) /*!< DPFSA24 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Pos (26UL) /*!< DPFSA26 (Bit 26) */ + #define R_SYSTEM_DPFSAR_DPFSA26_Msk (0x4000000UL) /*!< DPFSA26 (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Pos (27UL) /*!< DPFSA27 (Bit 27) */ + #define R_SYSTEM_DPFSAR_DPFSA27_Msk (0x8000000UL) /*!< DPFSA27 (Bitfield-Mask: 0x01) */ +/* ======================================================== DPSWCR ========================================================= */ + #define R_SYSTEM_DPSWCR_WTSTS_Pos (0UL) /*!< WTSTS (Bit 0) */ + #define R_SYSTEM_DPSWCR_WTSTS_Msk (0x3fUL) /*!< WTSTS (Bitfield-Mask: 0x3f) */ +/* ====================================================== VBATTMNSELR ====================================================== */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos (0UL) /*!< VBATTMNSEL (Bit 0) */ + #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk (0x1UL) /*!< VBATTMNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= VBATTMONR ======================================================= */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Pos (0UL) /*!< VBATTMON (Bit 0) */ + #define R_SYSTEM_VBATTMONR_VBATTMON_Msk (0x1UL) /*!< VBATTMON (Bitfield-Mask: 0x01) */ +/* ======================================================== VBTBER ========================================================= */ + #define R_SYSTEM_VBTBER_VBAE_Pos (3UL) /*!< VBAE (Bit 3) */ + #define R_SYSTEM_VBTBER_VBAE_Msk (0x8UL) /*!< VBAE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CAL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCDR ========================================================= */ + #define R_TSN_CAL_TSCDR_TSCDR_Pos (0UL) /*!< TSCDR (Bit 0) */ + #define R_TSN_CAL_TSCDR_TSCDR_Msk (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSN_CTRL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSCR ========================================================== */ + #define R_TSN_CTRL_TSCR_TSEN_Pos (7UL) /*!< TSEN (Bit 7) */ + #define R_TSN_CTRL_TSCR_TSEN_Msk (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSN_CTRL_TSCR_TSOE_Pos (4UL) /*!< TSOE (Bit 4) */ + #define R_TSN_CTRL_TSCR_TSOE_Msk (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ + #define R_WDT_WDTRR_WDTRR_Pos (0UL) /*!< WDTRR (Bit 0) */ + #define R_WDT_WDTRR_WDTRR_Msk (0xffUL) /*!< WDTRR (Bitfield-Mask: 0xff) */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ +/* ======================================================= WDTCSTPR ======================================================== */ + #define R_WDT_WDTCSTPR_SLCSTP_Pos (7UL) /*!< SLCSTP (Bit 7) */ + #define R_WDT_WDTCSTPR_SLCSTP_Msk (0x80UL) /*!< SLCSTP (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TZF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFOAD ========================================================= */ + #define R_TZF_TZFOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_TZF_TZFOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFOAD_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFOAD_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ========================================================= TZFPT ========================================================= */ + #define R_TZF_TZFPT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_TZF_TZFPT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ + #define R_TZF_TZFPT_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_TZF_TZFPT_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================== TZFSAR ========================================================= */ + #define R_TZF_TZFSAR_TZFSA0_Pos (0UL) /*!< TZFSA0 (Bit 0) */ + #define R_TZF_TZFSAR_TZFSA0_Msk (0x1UL) /*!< TZFSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CACHE ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCACTL ========================================================= */ + #define R_CACHE_CCACTL_ENC_Pos (0UL) /*!< ENC (Bit 0) */ + #define R_CACHE_CCACTL_ENC_Msk (0x1UL) /*!< ENC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCAFCT ========================================================= */ + #define R_CACHE_CCAFCT_FC_Pos (0UL) /*!< FC (Bit 0) */ + #define R_CACHE_CCAFCT_FC_Msk (0x1UL) /*!< FC (Bitfield-Mask: 0x01) */ +/* ======================================================== CCALCF ========================================================= */ + #define R_CACHE_CCALCF_CC_Pos (0UL) /*!< CC (Bit 0) */ + #define R_CACHE_CCALCF_CC_Msk (0x3UL) /*!< CC (Bitfield-Mask: 0x03) */ +/* ======================================================== SCACTL ========================================================= */ + #define R_CACHE_SCACTL_ENS_Pos (0UL) /*!< ENS (Bit 0) */ + #define R_CACHE_SCACTL_ENS_Msk (0x1UL) /*!< ENS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCAFCT ========================================================= */ + #define R_CACHE_SCAFCT_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_CACHE_SCAFCT_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ +/* ======================================================== SCALCF ========================================================= */ + #define R_CACHE_SCALCF_CS_Pos (0UL) /*!< CS (Bit 0) */ + #define R_CACHE_SCALCF_CS_Msk (0x3UL) /*!< CS (Bitfield-Mask: 0x03) */ +/* ======================================================== CAPOAD ========================================================= */ + #define R_CACHE_CAPOAD_OAD_Pos (0UL) /*!< OAD (Bit 0) */ + #define R_CACHE_CAPOAD_OAD_Msk (0x1UL) /*!< OAD (Bitfield-Mask: 0x01) */ +/* ======================================================== CAPRCR ========================================================= */ + #define R_CACHE_CAPRCR_PRCR_Pos (0UL) /*!< PRCR (Bit 0) */ + #define R_CACHE_CAPRCR_PRCR_Msk (0x1UL) /*!< PRCR (Bitfield-Mask: 0x01) */ + #define R_CACHE_CAPRCR_KW_Pos (1UL) /*!< KW (Bit 1) */ + #define R_CACHE_CAPRCR_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ + +/* =========================================================================================================================== */ +/* ================ R_CPSCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CSAR ========================================================== */ + #define R_CPSCU_CSAR_CACHESA_Pos (0UL) /*!< CACHESA (Bit 0) */ + #define R_CPSCU_CSAR_CACHESA_Msk (0x1UL) /*!< CACHESA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHELSA_Pos (1UL) /*!< CACHELSA (Bit 1) */ + #define R_CPSCU_CSAR_CACHELSA_Msk (0x2UL) /*!< CACHELSA (Bitfield-Mask: 0x01) */ + #define R_CPSCU_CSAR_CACHEESA_Pos (2UL) /*!< CACHEESA (Bit 2) */ + #define R_CPSCU_CSAR_CACHEESA_Msk (0x4UL) /*!< CACHEESA (Bitfield-Mask: 0x01) */ +/* ======================================================== SRAMSAR ======================================================== */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Pos (0UL) /*!< SRAMSA0 (Bit 0) */ + #define R_CPSCU_SRAMSAR_SRAMSA0_Msk (0x1UL) /*!< SRAMSA0 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Pos (1UL) /*!< SRAMSA1 (Bit 1) */ + #define R_CPSCU_SRAMSAR_SRAMSA1_Msk (0x2UL) /*!< SRAMSA1 (Bitfield-Mask: 0x01) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Pos (2UL) /*!< SRAMSA2 (Bit 2) */ + #define R_CPSCU_SRAMSAR_SRAMSA2_Msk (0x4UL) /*!< SRAMSA2 (Bitfield-Mask: 0x01) */ +/* ======================================================= STBRAMSAR ======================================================= */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos (0UL) /*!< NSBSTBR (Bit 0) */ + #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk (0xfUL) /*!< NSBSTBR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DTCSAR ========================================================= */ + #define R_CPSCU_DTCSAR_DTCSTSA_Pos (0UL) /*!< DTCSTSA (Bit 0) */ + #define R_CPSCU_DTCSAR_DTCSTSA_Msk (0x1UL) /*!< DTCSTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== DMACSAR ======================================================== */ + #define R_CPSCU_DMACSAR_DMASTSA_Pos (0UL) /*!< DMASTSA (Bit 0) */ + #define R_CPSCU_DMACSAR_DMASTSA_Msk (0x1UL) /*!< DMASTSA (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARA ======================================================== */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Pos (0UL) /*!< SAIRQCRn (Bit 0) */ + #define R_CPSCU_ICUSARA_SAIRQCRn_Msk (0xffffUL) /*!< SAIRQCRn (Bitfield-Mask: 0xffff) */ +/* ======================================================== ICUSARB ======================================================== */ + #define R_CPSCU_ICUSARB_SANMI_Pos (0UL) /*!< SANMI (Bit 0) */ + #define R_CPSCU_ICUSARB_SANMI_Msk (0x1UL) /*!< SANMI (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARC ======================================================== */ + #define R_CPSCU_ICUSARC_SADMACn_Pos (0UL) /*!< SADMACn (Bit 0) */ + #define R_CPSCU_ICUSARC_SADMACn_Msk (0xffUL) /*!< SADMACn (Bitfield-Mask: 0xff) */ +/* ======================================================== ICUSARD ======================================================== */ + #define R_CPSCU_ICUSARD_SASELSR0_Pos (0UL) /*!< SASELSR0 (Bit 0) */ + #define R_CPSCU_ICUSARD_SASELSR0_Msk (0x1UL) /*!< SASELSR0 (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARE ======================================================== */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos (16UL) /*!< SAIWDTWUP (Bit 16) */ + #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk (0x10000UL) /*!< SAIWDTWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Pos (18UL) /*!< SALVD1WUP (Bit 18) */ + #define R_CPSCU_ICUSARE_SALVD1WUP_Msk (0x40000UL) /*!< SALVD1WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Pos (19UL) /*!< SALVD2WUP (Bit 19) */ + #define R_CPSCU_ICUSARE_SALVD2WUP_Msk (0x80000UL) /*!< SALVD2WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos (24UL) /*!< SARTCALMWUP (Bit 24) */ + #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk (0x1000000UL) /*!< SARTCALMWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos (25UL) /*!< SARTCPRDWUP (Bit 25) */ + #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk (0x2000000UL) /*!< SARTCPRDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos (27UL) /*!< SAUSBFS0WUP (Bit 27) */ + #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk (0x8000000UL) /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos (28UL) /*!< SAAGT1UDWUP (Bit 28) */ + #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos (29UL) /*!< SAAGT1CAWUP (Bit 29) */ + #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos (30UL) /*!< SAAGT1CBWUP (Bit 30) */ + #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos (31UL) /*!< SAIIC0WUP (Bit 31) */ + #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARF ======================================================== */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos (0UL) /*!< SAAGT3UDWUP (Bit 0) */ + #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk (0x1UL) /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos (1UL) /*!< SAAGT3CAWUP (Bit 1) */ + #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk (0x2UL) /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos (2UL) /*!< SAAGT3CBWUP (Bit 2) */ + #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk (0x4UL) /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01) */ +/* ======================================================== ICUSARG ======================================================== */ + #define R_CPSCU_ICUSARG_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARG_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARH ======================================================== */ + #define R_CPSCU_ICUSARH_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARH_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ICUSARI ======================================================== */ + #define R_CPSCU_ICUSARI_SAIELSRn_Pos (0UL) /*!< SAIELSRn (Bit 0) */ + #define R_CPSCU_ICUSARI_SAIELSRn_Msk (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== BUSSARA ======================================================== */ + #define R_CPSCU_BUSSARA_BUSSA0_Pos (0UL) /*!< BUSSA0 (Bit 0) */ + #define R_CPSCU_BUSSARA_BUSSA0_Msk (0x1UL) /*!< BUSSA0 (Bitfield-Mask: 0x01) */ +/* ======================================================== BUSSARB ======================================================== */ + #define R_CPSCU_BUSSARB_BUSSB0_Pos (0UL) /*!< BUSSB0 (Bit 0) */ + #define R_CPSCU_BUSSARB_BUSSB0_Msk (0x1UL) /*!< BUSSB0 (Bitfield-Mask: 0x01) */ +/* ======================================================= MMPUSARA ======================================================== */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos (0UL) /*!< MMPUAnSA (Bit 0) */ + #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk (0xffUL) /*!< MMPUAnSA (Bitfield-Mask: 0xff) */ +/* ======================================================= MMPUSARB ======================================================== */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos (0UL) /*!< MMPUB0SA (Bit 0) */ + #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk (0x1UL) /*!< MMPUB0SA (Bitfield-Mask: 0x01) */ +/* ======================================================== CPUDSAR ======================================================== */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Pos (0UL) /*!< CPUDSA0 (Bit 0) */ + #define R_CPSCU_CPUDSAR_CPUDSA0_Msk (0x1UL) /*!< CPUDSA0 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC_B0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ADCLKENR ======================================================== */ + #define R_ADC_B0_ADCLKENR_CLKEN_Pos (0UL) /*!< CLKEN (Bit 0) */ + #define R_ADC_B0_ADCLKENR_CLKEN_Msk (0x1UL) /*!< CLKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKSR ======================================================== */ + #define R_ADC_B0_ADCLKSR_CLKSR_Pos (0UL) /*!< CLKSR (Bit 0) */ + #define R_ADC_B0_ADCLKSR_CLKSR_Msk (0x1UL) /*!< CLKSR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCLKCR ======================================================== */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ + #define R_ADC_B0_ADCLKCR_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCLKCR_DIVR_Pos (16UL) /*!< DIVR (Bit 16) */ + #define R_ADC_B0_ADCLKCR_DIVR_Msk (0x70000UL) /*!< DIVR (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSYCR ========================================================= */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Pos (0UL) /*!< ADSYCYC (Bit 0) */ + #define R_ADC_B0_ADSYCR_ADSYCYC_Msk (0x7ffUL) /*!< ADSYCYC (Bitfield-Mask: 0x7ff) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Pos (16UL) /*!< ADSYDIS0 (Bit 16) */ + #define R_ADC_B0_ADSYCR_ADSYDIS0_Msk (0x10000UL) /*!< ADSYDIS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Pos (17UL) /*!< ADSYDIS1 (Bit 17) */ + #define R_ADC_B0_ADSYCR_ADSYDIS1_Msk (0x20000UL) /*!< ADSYDIS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADERINTCR ======================================================= */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Pos (0UL) /*!< ADEIE0 (Bit 0) */ + #define R_ADC_B0_ADERINTCR_ADEIE0_Msk (0x1UL) /*!< ADEIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Pos (1UL) /*!< ADEIE1 (Bit 1) */ + #define R_ADC_B0_ADERINTCR_ADEIE1_Msk (0x2UL) /*!< ADEIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFINTCR ======================================================= */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Pos (0UL) /*!< ADOVFIE0 (Bit 0) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE0_Msk (0x1UL) /*!< ADOVFIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Pos (1UL) /*!< ADOVFIE1 (Bit 1) */ + #define R_ADC_B0_ADOVFINTCR_ADOVFIE1_Msk (0x2UL) /*!< ADOVFIE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALINTCR ======================================================= */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Pos (16UL) /*!< CALENDIE0 (Bit 16) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE0_Msk (0x10000UL) /*!< CALENDIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Pos (17UL) /*!< CALENDIE1 (Bit 17) */ + #define R_ADC_B0_ADCALINTCR_CALENDIE1_Msk (0x20000UL) /*!< CALENDIE1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADMDR ========================================================= */ + #define R_ADC_B0_ADMDR_ADMD0_Pos (0UL) /*!< ADMD0 (Bit 0) */ + #define R_ADC_B0_ADMDR_ADMD0_Msk (0xfUL) /*!< ADMD0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADMDR_ADMD1_Pos (8UL) /*!< ADMD1 (Bit 8) */ + #define R_ADC_B0_ADMDR_ADMD1_Msk (0xf00UL) /*!< ADMD1 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC_B0_ADGSPCR_PGS0_Pos (0UL) /*!< PGS0 (Bit 0) */ + #define R_ADC_B0_ADGSPCR_PGS0_Msk (0x1UL) /*!< PGS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Pos (1UL) /*!< RSCN0 (Bit 1) */ + #define R_ADC_B0_ADGSPCR_RSCN0_Msk (0x2UL) /*!< RSCN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Pos (2UL) /*!< LGRRS0 (Bit 2) */ + #define R_ADC_B0_ADGSPCR_LGRRS0_Msk (0x4UL) /*!< LGRRS0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP0_Pos (3UL) /*!< GRP0 (Bit 3) */ + #define R_ADC_B0_ADGSPCR_GRP0_Msk (0x8UL) /*!< GRP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_PGS1_Pos (8UL) /*!< PGS1 (Bit 8) */ + #define R_ADC_B0_ADGSPCR_PGS1_Msk (0x100UL) /*!< PGS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Pos (9UL) /*!< RSCN1 (Bit 9) */ + #define R_ADC_B0_ADGSPCR_RSCN1_Msk (0x200UL) /*!< RSCN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Pos (10UL) /*!< LGRRS1 (Bit 10) */ + #define R_ADC_B0_ADGSPCR_LGRRS1_Msk (0x400UL) /*!< LGRRS1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADGSPCR_GRP1_Pos (11UL) /*!< GRP1 (Bit 11) */ + #define R_ADC_B0_ADGSPCR_GRP1_Msk (0x800UL) /*!< GRP1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSGER ========================================================= */ + #define R_ADC_B0_ADSGER_SGREn_Pos (0UL) /*!< SGREn (Bit 0) */ + #define R_ADC_B0_ADSGER_SGREn_Msk (0x1ffUL) /*!< SGREn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSGCR0 ======================================================== */ + #define R_ADC_B0_ADSGCR0_SGADS0_Pos (0UL) /*!< SGADS0 (Bit 0) */ + #define R_ADC_B0_ADSGCR0_SGADS0_Msk (0x3UL) /*!< SGADS0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Pos (8UL) /*!< SGADS1 (Bit 8) */ + #define R_ADC_B0_ADSGCR0_SGADS1_Msk (0x300UL) /*!< SGADS1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Pos (16UL) /*!< SGADS2 (Bit 16) */ + #define R_ADC_B0_ADSGCR0_SGADS2_Msk (0x30000UL) /*!< SGADS2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Pos (24UL) /*!< SGADS3 (Bit 24) */ + #define R_ADC_B0_ADSGCR0_SGADS3_Msk (0x3000000UL) /*!< SGADS3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR1 ======================================================== */ + #define R_ADC_B0_ADSGCR1_SGADS4_Pos (0UL) /*!< SGADS4 (Bit 0) */ + #define R_ADC_B0_ADSGCR1_SGADS4_Msk (0x3UL) /*!< SGADS4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Pos (8UL) /*!< SGADS5 (Bit 8) */ + #define R_ADC_B0_ADSGCR1_SGADS5_Msk (0x300UL) /*!< SGADS5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Pos (16UL) /*!< SGADS6 (Bit 16) */ + #define R_ADC_B0_ADSGCR1_SGADS6_Msk (0x30000UL) /*!< SGADS6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Pos (24UL) /*!< SGADS7 (Bit 24) */ + #define R_ADC_B0_ADSGCR1_SGADS7_Msk (0x3000000UL) /*!< SGADS7 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADSGCR2 ======================================================== */ + #define R_ADC_B0_ADSGCR2_SGADS8_Pos (0UL) /*!< SGADS8 (Bit 0) */ + #define R_ADC_B0_ADSGCR2_SGADS8_Msk (0x3UL) /*!< SGADS8 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADINTCR ======================================================== */ + #define R_ADC_B0_ADINTCR_ADIEn_Pos (0UL) /*!< ADIEn (Bit 0) */ + #define R_ADC_B0_ADINTCR_ADIEn_Msk (0x3ffUL) /*!< ADIEn (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGEXT0 ======================================================= */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT0_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT1 ======================================================= */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT1_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT2 ======================================================= */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT2_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT3 ======================================================= */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT3_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT4 ======================================================= */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT4_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT5 ======================================================= */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT5_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT6 ======================================================= */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT6_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT7 ======================================================= */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT7_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGEXT8 ======================================================= */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Pos (0UL) /*!< TRGEXT0 (Bit 0) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT0_Msk (0x1UL) /*!< TRGEXT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Pos (1UL) /*!< TRGEXT1 (Bit 1) */ + #define R_ADC_B0_ADTRGEXT8_TRGEXT1_Msk (0x2UL) /*!< TRGEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADTRGELC0 ======================================================= */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC0_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC1 ======================================================= */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC1_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC2 ======================================================= */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC2_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC3 ======================================================= */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC3_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC4 ======================================================= */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC4_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC5 ======================================================= */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC5_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC6 ======================================================= */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC6_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC7 ======================================================= */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC7_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGELC8 ======================================================= */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Pos (0UL) /*!< TRGELCm (Bit 0) */ + #define R_ADC_B0_ADTRGELC8_TRGELCm_Msk (0x3fUL) /*!< TRGELCm (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADTRGGPT0 ======================================================= */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT0_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT1 ======================================================= */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT1_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT2 ======================================================= */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT2_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT3 ======================================================= */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT3_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT4 ======================================================= */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT4_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT5 ======================================================= */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT5_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT6 ======================================================= */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT6_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT7 ======================================================= */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT7_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGGPT8 ======================================================= */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Pos (0UL) /*!< TRGGPTAm (Bit 0) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTAm_Msk (0x3ffUL) /*!< TRGGPTAm (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Pos (16UL) /*!< TRGGPTBm (Bit 16) */ + #define R_ADC_B0_ADTRGGPT8_TRGGPTBm_Msk (0x3ff0000UL) /*!< TRGGPTBm (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADTRGDLR0 ======================================================= */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Pos (0UL) /*!< TRGDLY0 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY0_Msk (0xffUL) /*!< TRGDLY0 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Pos (16UL) /*!< TRGDLY1 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR0_TRGDLY1_Msk (0xff0000UL) /*!< TRGDLY1 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR1 ======================================================= */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Pos (0UL) /*!< TRGDLY2 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY2_Msk (0xffUL) /*!< TRGDLY2 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Pos (16UL) /*!< TRGDLY3 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR1_TRGDLY3_Msk (0xff0000UL) /*!< TRGDLY3 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR2 ======================================================= */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Pos (0UL) /*!< TRGDLY4 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY4_Msk (0xffUL) /*!< TRGDLY4 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Pos (16UL) /*!< TRGDLY5 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR2_TRGDLY5_Msk (0xff0000UL) /*!< TRGDLY5 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR3 ======================================================= */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Pos (0UL) /*!< TRGDLY6 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY6_Msk (0xffUL) /*!< TRGDLY6 (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Pos (16UL) /*!< TRGDLY7 (Bit 16) */ + #define R_ADC_B0_ADTRGDLR3_TRGDLY7_Msk (0xff0000UL) /*!< TRGDLY7 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADTRGDLR4 ======================================================= */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Pos (0UL) /*!< TRGDLY8 (Bit 0) */ + #define R_ADC_B0_ADTRGDLR4_TRGDLY8_Msk (0xffUL) /*!< TRGDLY8 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADSGDCR0 ======================================================== */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR0_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR0_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR0_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR0_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR0_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR1 ======================================================== */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR1_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR1_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR1_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR1_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR1_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR2 ======================================================== */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR2_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR2_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR2_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR2_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR2_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR3 ======================================================== */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR3_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR3_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR3_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR3_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR3_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR4 ======================================================== */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR4_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR4_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR4_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR4_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR4_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR5 ======================================================== */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR5_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR5_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR5_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR5_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR5_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR6 ======================================================== */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR6_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR6_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR6_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR6_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR6_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR7 ======================================================== */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR7_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR7_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR7_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR7_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR7_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADSGDCR8 ======================================================== */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Pos (0UL) /*!< DIAGVAL (Bit 0) */ + #define R_ADC_B0_ADSGDCR8_DIAGVAL_Msk (0x7UL) /*!< DIAGVAL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Pos (16UL) /*!< ADDISEN (Bit 16) */ + #define R_ADC_B0_ADSGDCR8_ADDISEN_Msk (0x10000UL) /*!< ADDISEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Pos (20UL) /*!< ADDISP (Bit 20) */ + #define R_ADC_B0_ADSGDCR8_ADDISP_Msk (0x100000UL) /*!< ADDISP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Pos (21UL) /*!< ADDISN (Bit 21) */ + #define R_ADC_B0_ADSGDCR8_ADDISN_Msk (0x200000UL) /*!< ADDISN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Pos (24UL) /*!< ADNDIS (Bit 24) */ + #define R_ADC_B0_ADSGDCR8_ADNDIS_Msk (0xf000000UL) /*!< ADNDIS (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADSSTR0 ======================================================== */ + #define R_ADC_B0_ADSSTR0_SST0_Pos (0UL) /*!< SST0 (Bit 0) */ + #define R_ADC_B0_ADSSTR0_SST0_Msk (0x3ffUL) /*!< SST0 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR0_SST1_Pos (16UL) /*!< SST1 (Bit 16) */ + #define R_ADC_B0_ADSSTR0_SST1_Msk (0x3ff0000UL) /*!< SST1 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR1 ======================================================== */ + #define R_ADC_B0_ADSSTR1_SST2_Pos (0UL) /*!< SST2 (Bit 0) */ + #define R_ADC_B0_ADSSTR1_SST2_Msk (0x3ffUL) /*!< SST2 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR1_SST3_Pos (16UL) /*!< SST3 (Bit 16) */ + #define R_ADC_B0_ADSSTR1_SST3_Msk (0x3ff0000UL) /*!< SST3 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR2 ======================================================== */ + #define R_ADC_B0_ADSSTR2_SST4_Pos (0UL) /*!< SST4 (Bit 0) */ + #define R_ADC_B0_ADSSTR2_SST4_Msk (0x3ffUL) /*!< SST4 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR2_SST5_Pos (16UL) /*!< SST5 (Bit 16) */ + #define R_ADC_B0_ADSSTR2_SST5_Msk (0x3ff0000UL) /*!< SST5 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR3 ======================================================== */ + #define R_ADC_B0_ADSSTR3_SST6_Pos (0UL) /*!< SST6 (Bit 0) */ + #define R_ADC_B0_ADSSTR3_SST6_Msk (0x3ffUL) /*!< SST6 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR3_SST7_Pos (16UL) /*!< SST7 (Bit 16) */ + #define R_ADC_B0_ADSSTR3_SST7_Msk (0x3ff0000UL) /*!< SST7 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR4 ======================================================== */ + #define R_ADC_B0_ADSSTR4_SST8_Pos (0UL) /*!< SST8 (Bit 0) */ + #define R_ADC_B0_ADSSTR4_SST8_Msk (0x3ffUL) /*!< SST8 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR4_SST9_Pos (16UL) /*!< SST9 (Bit 16) */ + #define R_ADC_B0_ADSSTR4_SST9_Msk (0x3ff0000UL) /*!< SST9 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR5 ======================================================== */ + #define R_ADC_B0_ADSSTR5_SST10_Pos (0UL) /*!< SST10 (Bit 0) */ + #define R_ADC_B0_ADSSTR5_SST10_Msk (0x3ffUL) /*!< SST10 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR5_SST11_Pos (16UL) /*!< SST11 (Bit 16) */ + #define R_ADC_B0_ADSSTR5_SST11_Msk (0x3ff0000UL) /*!< SST11 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR6 ======================================================== */ + #define R_ADC_B0_ADSSTR6_SST12_Pos (0UL) /*!< SST12 (Bit 0) */ + #define R_ADC_B0_ADSSTR6_SST12_Msk (0x3ffUL) /*!< SST12 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR6_SST13_Pos (16UL) /*!< SST13 (Bit 16) */ + #define R_ADC_B0_ADSSTR6_SST13_Msk (0x3ff0000UL) /*!< SST13 (Bitfield-Mask: 0x3ff) */ +/* ======================================================== ADSSTR7 ======================================================== */ + #define R_ADC_B0_ADSSTR7_SST14_Pos (0UL) /*!< SST14 (Bit 0) */ + #define R_ADC_B0_ADSSTR7_SST14_Msk (0x3ffUL) /*!< SST14 (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADSSTR7_SST15_Pos (16UL) /*!< SST15 (Bit 16) */ + #define R_ADC_B0_ADSSTR7_SST15_Msk (0x3ff0000UL) /*!< SST15 (Bitfield-Mask: 0x3ff) */ +/* ======================================================= ADCNVSTR ======================================================== */ + #define R_ADC_B0_ADCNVSTR_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_ADC_B0_ADCNVSTR_CST0_Msk (0x3fUL) /*!< CST0 (Bitfield-Mask: 0x3f) */ + #define R_ADC_B0_ADCNVSTR_CST1_Pos (8UL) /*!< CST1 (Bit 8) */ + #define R_ADC_B0_ADCNVSTR_CST1_Msk (0x3f00UL) /*!< CST1 (Bitfield-Mask: 0x3f) */ +/* ======================================================= ADCALSTCR ======================================================= */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Pos (0UL) /*!< CALADSST (Bit 0) */ + #define R_ADC_B0_ADCALSTCR_CALADSST_Msk (0x3ffUL) /*!< CALADSST (Bitfield-Mask: 0x3ff) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Pos (16UL) /*!< CALADCST (Bit 16) */ + #define R_ADC_B0_ADCALSTCR_CALADCST_Msk (0x3f0000UL) /*!< CALADCST (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADSHCR0 ======================================================== */ + #define R_ADC_B0_ADSHCR0_SHEN0_Pos (0UL) /*!< SHEN0 (Bit 0) */ + #define R_ADC_B0_ADSHCR0_SHEN0_Msk (0x1UL) /*!< SHEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHEN1_Pos (1UL) /*!< SHEN1 (Bit 1) */ + #define R_ADC_B0_ADSHCR0_SHEN1_Msk (0x2UL) /*!< SHEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR0_SHEN2_Pos (2UL) /*!< SHEN2 (Bit 2) */ + #define R_ADC_B0_ADSHCR0_SHEN2_Msk (0x4UL) /*!< SHEN2 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR0 ======================================================== */ + #define R_ADC_B0_ADSHSTR0_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR0_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR0_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADSHCR1 ======================================================== */ + #define R_ADC_B0_ADSHCR1_SHEN4_Pos (0UL) /*!< SHEN4 (Bit 0) */ + #define R_ADC_B0_ADSHCR1_SHEN4_Msk (0x1UL) /*!< SHEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHEN5_Pos (1UL) /*!< SHEN5 (Bit 1) */ + #define R_ADC_B0_ADSHCR1_SHEN5_Msk (0x2UL) /*!< SHEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSHCR1_SHEN6_Pos (2UL) /*!< SHEN6 (Bit 2) */ + #define R_ADC_B0_ADSHCR1_SHEN6_Msk (0x4UL) /*!< SHEN6 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADSHSTR1 ======================================================== */ + #define R_ADC_B0_ADSHSTR1_SHSST_Pos (0UL) /*!< SHSST (Bit 0) */ + #define R_ADC_B0_ADSHSTR1_SHSST_Msk (0xffUL) /*!< SHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Pos (16UL) /*!< SHHST (Bit 16) */ + #define R_ADC_B0_ADSHSTR1_SHHST_Msk (0x70000UL) /*!< SHHST (Bitfield-Mask: 0x07) */ +/* ======================================================= ADCALSHCR ======================================================= */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Pos (0UL) /*!< CALSHSST (Bit 0) */ + #define R_ADC_B0_ADCALSHCR_CALSHSST_Msk (0xffUL) /*!< CALSHSST (Bitfield-Mask: 0xff) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Pos (16UL) /*!< CALSHHST (Bit 16) */ + #define R_ADC_B0_ADCALSHCR_CALSHHST_Msk (0x70000UL) /*!< CALSHHST (Bitfield-Mask: 0x07) */ +/* ======================================================== ADPGACR ======================================================== */ + #define R_ADC_B0_ADPGACR_PGADEN_Pos (1UL) /*!< PGADEN (Bit 1) */ + #define R_ADC_B0_ADPGACR_PGADEN_Msk (0x2UL) /*!< PGADEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGACR_PGASEL1_Pos (2UL) /*!< PGASEL1 (Bit 2) */ + #define R_ADC_B0_ADPGACR_PGASEL1_Msk (0x4UL) /*!< PGASEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGACR_PGAENAMP_Pos (3UL) /*!< PGAENAMP (Bit 3) */ + #define R_ADC_B0_ADPGACR_PGAENAMP_Msk (0x8UL) /*!< PGAENAMP (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGACR_PGAGEN_Pos (16UL) /*!< PGAGEN (Bit 16) */ + #define R_ADC_B0_ADPGACR_PGAGEN_Msk (0x10000UL) /*!< PGAGEN (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGACR_PGADG_Pos (20UL) /*!< PGADG (Bit 20) */ + #define R_ADC_B0_ADPGACR_PGADG_Msk (0x300000UL) /*!< PGADG (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADPGACR_PGAGAIN_Pos (24UL) /*!< PGAGAIN (Bit 24) */ + #define R_ADC_B0_ADPGACR_PGAGAIN_Msk (0xf000000UL) /*!< PGAGAIN (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADPGAMONCR ======================================================= */ + #define R_ADC_B0_ADPGAMONCR_PGAMON_Pos (0UL) /*!< PGAMON (Bit 0) */ + #define R_ADC_B0_ADPGAMONCR_PGAMON_Msk (0x7UL) /*!< PGAMON (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL0_Pos (16UL) /*!< MONSEL0 (Bit 16) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL0_Msk (0x10000UL) /*!< MONSEL0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL1_Pos (17UL) /*!< MONSEL1 (Bit 17) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL1_Msk (0x20000UL) /*!< MONSEL1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL2_Pos (18UL) /*!< MONSEL2 (Bit 18) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL2_Msk (0x40000UL) /*!< MONSEL2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL3_Pos (19UL) /*!< MONSEL3 (Bit 19) */ + #define R_ADC_B0_ADPGAMONCR_MONSEL3_Msk (0x80000UL) /*!< MONSEL3 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADREFCR ======================================================== */ + #define R_ADC_B0_ADREFCR_VDE_Pos (0UL) /*!< VDE (Bit 0) */ + #define R_ADC_B0_ADREFCR_VDE_Msk (0x1UL) /*!< VDE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADDFSR0 ======================================================== */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR0_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR0_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR0_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR0_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================== ADDFSR1 ======================================================== */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Pos (0UL) /*!< DFSEL0 (Bit 0) */ + #define R_ADC_B0_ADDFSR1_DFSEL0_Msk (0x3UL) /*!< DFSEL0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Pos (8UL) /*!< DFSEL1 (Bit 8) */ + #define R_ADC_B0_ADDFSR1_DFSEL1_Msk (0x300UL) /*!< DFSEL1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Pos (16UL) /*!< DFSEL2 (Bit 16) */ + #define R_ADC_B0_ADDFSR1_DFSEL2_Msk (0x30000UL) /*!< DFSEL2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Pos (24UL) /*!< DFSEL3 (Bit 24) */ + #define R_ADC_B0_ADDFSR1_DFSEL3_Msk (0x3000000UL) /*!< DFSEL3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADUOFTR0 ======================================================== */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR0_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR1 ======================================================== */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR1_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR2 ======================================================== */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR2_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR3 ======================================================== */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR3_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR4 ======================================================== */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR4_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR5 ======================================================== */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR5_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR6 ======================================================== */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR6_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADUOFTR7 ======================================================== */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Pos (0UL) /*!< UOFSET (Bit 0) */ + #define R_ADC_B0_ADUOFTR7_UOFSET_Msk (0xffffUL) /*!< UOFSET (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADUGTR0 ======================================================== */ + #define R_ADC_B0_ADUGTR0_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR0_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR1 ======================================================== */ + #define R_ADC_B0_ADUGTR1_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR1_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR2 ======================================================== */ + #define R_ADC_B0_ADUGTR2_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR2_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR3 ======================================================== */ + #define R_ADC_B0_ADUGTR3_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR3_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR4 ======================================================== */ + #define R_ADC_B0_ADUGTR4_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR4_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR5 ======================================================== */ + #define R_ADC_B0_ADUGTR5_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR5_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR6 ======================================================== */ + #define R_ADC_B0_ADUGTR6_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR6_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ======================================================== ADUGTR7 ======================================================== */ + #define R_ADC_B0_ADUGTR7_UGAIN_Pos (0UL) /*!< UGAIN (Bit 0) */ + #define R_ADC_B0_ADUGTR7_UGAIN_Msk (0xffffffUL) /*!< UGAIN (Bitfield-Mask: 0xffffff) */ +/* ====================================================== ADLIMINTCR ======================================================= */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Pos (0UL) /*!< LIMIEn (Bit 0) */ + #define R_ADC_B0_ADLIMINTCR_LIMIEn_Msk (0x1ffUL) /*!< LIMIEn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADLIMTR0 ======================================================== */ + #define R_ADC_B0_ADLIMTR0_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR0_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR0_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR1 ======================================================== */ + #define R_ADC_B0_ADLIMTR1_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR1_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR1_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR2 ======================================================== */ + #define R_ADC_B0_ADLIMTR2_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR2_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR2_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR3 ======================================================== */ + #define R_ADC_B0_ADLIMTR3_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR3_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR3_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR4 ======================================================== */ + #define R_ADC_B0_ADLIMTR4_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR4_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR4_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR5 ======================================================== */ + #define R_ADC_B0_ADLIMTR5_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR5_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR5_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR6 ======================================================== */ + #define R_ADC_B0_ADLIMTR6_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR6_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR6_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADLIMTR7 ======================================================== */ + #define R_ADC_B0_ADLIMTR7_LIML_Pos (0UL) /*!< LIML (Bit 0) */ + #define R_ADC_B0_ADLIMTR7_LIML_Msk (0xffffUL) /*!< LIML (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Pos (16UL) /*!< LIMU (Bit 16) */ + #define R_ADC_B0_ADLIMTR7_LIMU_Msk (0xffff0000UL) /*!< LIMU (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPENR ======================================================== */ + #define R_ADC_B0_ADCMPENR_CMPENn_Pos (0UL) /*!< CMPENn (Bit 0) */ + #define R_ADC_B0_ADCMPENR_CMPENn_Msk (0xffUL) /*!< CMPENn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPINTCR ======================================================= */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Pos (0UL) /*!< CMPIEn (Bit 0) */ + #define R_ADC_B0_ADCMPINTCR_CMPIEn_Msk (0xfUL) /*!< CMPIEn (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCCMPCR0 ======================================================= */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR0_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR0_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCCMPCR1 ======================================================= */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Pos (0UL) /*!< CCMPCND (Bit 0) */ + #define R_ADC_B0_ADCCMPCR1_CCMPCND_Msk (0x3UL) /*!< CCMPCND (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Pos (16UL) /*!< CCMPTBLm (Bit 16) */ + #define R_ADC_B0_ADCCMPCR1_CCMPTBLm_Msk (0xff0000UL) /*!< CCMPTBLm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPMDR0 ======================================================= */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Pos (0UL) /*!< CMPMD0 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD0_Msk (0x3UL) /*!< CMPMD0 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Pos (8UL) /*!< CMPMD1 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD1_Msk (0x300UL) /*!< CMPMD1 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Pos (16UL) /*!< CMPMD2 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD2_Msk (0x30000UL) /*!< CMPMD2 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Pos (24UL) /*!< CMPMD3 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR0_CMPMD3_Msk (0x3000000UL) /*!< CMPMD3 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPMDR1 ======================================================= */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Pos (0UL) /*!< CMPMD4 (Bit 0) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD4_Msk (0x3UL) /*!< CMPMD4 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Pos (8UL) /*!< CMPMD5 (Bit 8) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD5_Msk (0x300UL) /*!< CMPMD5 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Pos (16UL) /*!< CMPMD6 (Bit 16) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD6_Msk (0x30000UL) /*!< CMPMD6 (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Pos (24UL) /*!< CMPMD7 (Bit 24) */ + #define R_ADC_B0_ADCMPMDR1_CMPMD7_Msk (0x3000000UL) /*!< CMPMD7 (Bitfield-Mask: 0x03) */ +/* ======================================================= ADCMPTBR0 ======================================================= */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR0_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR1 ======================================================= */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR1_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR2 ======================================================= */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR2_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR3 ======================================================= */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR3_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR4 ======================================================= */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR4_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR5 ======================================================= */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR5_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR6 ======================================================= */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR6_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPTBR7 ======================================================= */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Pos (0UL) /*!< CMPTBL (Bit 0) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBL_Msk (0xffffUL) /*!< CMPTBL (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Pos (16UL) /*!< CMPTBH (Bit 16) */ + #define R_ADC_B0_ADCMPTBR7_CMPTBH_Msk (0xffff0000UL) /*!< CMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADFIFOCR ======================================================== */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Pos (0UL) /*!< FIFOEN0 (Bit 0) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN0_Msk (0x1UL) /*!< FIFOEN0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Pos (1UL) /*!< FIFOEN1 (Bit 1) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN1_Msk (0x2UL) /*!< FIFOEN1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Pos (2UL) /*!< FIFOEN2 (Bit 2) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN2_Msk (0x4UL) /*!< FIFOEN2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Pos (3UL) /*!< FIFOEN3 (Bit 3) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN3_Msk (0x8UL) /*!< FIFOEN3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Pos (4UL) /*!< FIFOEN4 (Bit 4) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN4_Msk (0x10UL) /*!< FIFOEN4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Pos (5UL) /*!< FIFOEN5 (Bit 5) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN5_Msk (0x20UL) /*!< FIFOEN5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Pos (6UL) /*!< FIFOEN6 (Bit 6) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN6_Msk (0x40UL) /*!< FIFOEN6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Pos (7UL) /*!< FIFOEN7 (Bit 7) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN7_Msk (0x80UL) /*!< FIFOEN7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Pos (8UL) /*!< FIFOEN8 (Bit 8) */ + #define R_ADC_B0_ADFIFOCR_FIFOEN8_Msk (0x100UL) /*!< FIFOEN8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADFIFOINTCR ====================================================== */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Pos (0UL) /*!< FIFOIE0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE0_Msk (0x1UL) /*!< FIFOIE0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Pos (1UL) /*!< FIFOIE1 (Bit 1) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE1_Msk (0x2UL) /*!< FIFOIE1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Pos (2UL) /*!< FIFOIE2 (Bit 2) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE2_Msk (0x4UL) /*!< FIFOIE2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Pos (3UL) /*!< FIFOIE3 (Bit 3) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE3_Msk (0x8UL) /*!< FIFOIE3 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Pos (4UL) /*!< FIFOIE4 (Bit 4) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE4_Msk (0x10UL) /*!< FIFOIE4 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Pos (5UL) /*!< FIFOIE5 (Bit 5) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE5_Msk (0x20UL) /*!< FIFOIE5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Pos (6UL) /*!< FIFOIE6 (Bit 6) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE6_Msk (0x40UL) /*!< FIFOIE6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Pos (7UL) /*!< FIFOIE7 (Bit 7) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE7_Msk (0x80UL) /*!< FIFOIE7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Pos (8UL) /*!< FIFOIE8 (Bit 8) */ + #define R_ADC_B0_ADFIFOINTCR_FIFOIE8_Msk (0x100UL) /*!< FIFOIE8 (Bitfield-Mask: 0x01) */ +/* ===================================================== ADFIFOINTLR0 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Pos (0UL) /*!< FIFOILV0 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV0_Msk (0xfUL) /*!< FIFOILV0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Pos (16UL) /*!< FIFOILV1 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR0_FIFOILV1_Msk (0xf0000UL) /*!< FIFOILV1 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR1 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Pos (0UL) /*!< FIFOILV2 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV2_Msk (0xfUL) /*!< FIFOILV2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Pos (16UL) /*!< FIFOILV3 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR1_FIFOILV3_Msk (0xf0000UL) /*!< FIFOILV3 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR2 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Pos (0UL) /*!< FIFOILV4 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV4_Msk (0xfUL) /*!< FIFOILV4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Pos (16UL) /*!< FIFOILV5 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR2_FIFOILV5_Msk (0xf0000UL) /*!< FIFOILV5 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR3 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Pos (0UL) /*!< FIFOILV6 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV6_Msk (0xfUL) /*!< FIFOILV6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Pos (16UL) /*!< FIFOILV7 (Bit 16) */ + #define R_ADC_B0_ADFIFOINTLR3_FIFOILV7_Msk (0xf0000UL) /*!< FIFOILV7 (Bitfield-Mask: 0x0f) */ +/* ===================================================== ADFIFOINTLR4 ====================================================== */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Pos (0UL) /*!< FIFOILV8 (Bit 0) */ + #define R_ADC_B0_ADFIFOINTLR4_FIFOILV8_Msk (0xfUL) /*!< FIFOILV8 (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR0 ======================================================== */ + #define R_ADC_B0_ADCHCR0_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR0_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR0_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR0_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR0_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR0_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR1 ======================================================== */ + #define R_ADC_B0_ADCHCR1_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR1_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR1_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR1_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR1_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR1_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR2 ======================================================== */ + #define R_ADC_B0_ADCHCR2_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR2_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR2_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR2_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR2_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR2_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR3 ======================================================== */ + #define R_ADC_B0_ADCHCR3_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR3_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR3_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR3_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR3_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR3_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR4 ======================================================== */ + #define R_ADC_B0_ADCHCR4_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR4_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR4_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR4_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR4_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR4_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR5 ======================================================== */ + #define R_ADC_B0_ADCHCR5_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR5_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR5_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR5_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR5_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR5_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR6 ======================================================== */ + #define R_ADC_B0_ADCHCR6_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR6_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR6_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR6_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR6_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR6_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR7 ======================================================== */ + #define R_ADC_B0_ADCHCR7_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR7_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR7_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR7_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR7_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR7_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR8 ======================================================== */ + #define R_ADC_B0_ADCHCR8_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR8_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR8_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR8_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR8_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR8_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== ADCHCR9 ======================================================== */ + #define R_ADC_B0_ADCHCR9_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR9_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR9_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR9_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR9_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR9_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR10 ======================================================== */ + #define R_ADC_B0_ADCHCR10_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR10_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR10_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR10_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR10_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR10_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR11 ======================================================== */ + #define R_ADC_B0_ADCHCR11_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR11_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR11_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR11_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR11_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR11_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR12 ======================================================== */ + #define R_ADC_B0_ADCHCR12_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR12_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR12_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR12_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR12_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR12_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR13 ======================================================== */ + #define R_ADC_B0_ADCHCR13_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR13_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR13_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR13_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR13_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR13_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR14 ======================================================== */ + #define R_ADC_B0_ADCHCR14_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR14_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR14_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR14_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR14_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR14_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR15 ======================================================== */ + #define R_ADC_B0_ADCHCR15_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR15_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR15_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR15_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR15_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR15_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR16 ======================================================== */ + #define R_ADC_B0_ADCHCR16_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR16_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR16_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR16_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR16_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR16_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR17 ======================================================== */ + #define R_ADC_B0_ADCHCR17_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR17_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR17_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR17_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR17_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR17_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR18 ======================================================== */ + #define R_ADC_B0_ADCHCR18_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR18_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR18_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR18_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR18_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR18_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR19 ======================================================== */ + #define R_ADC_B0_ADCHCR19_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR19_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR19_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR19_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR19_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR19_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR20 ======================================================== */ + #define R_ADC_B0_ADCHCR20_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR20_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR20_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR20_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR20_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR20_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR21 ======================================================== */ + #define R_ADC_B0_ADCHCR21_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR21_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR21_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR21_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR21_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR21_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR22 ======================================================== */ + #define R_ADC_B0_ADCHCR22_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR22_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR22_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR22_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR22_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR22_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR23 ======================================================== */ + #define R_ADC_B0_ADCHCR23_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR23_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR23_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR23_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR23_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR23_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR24 ======================================================== */ + #define R_ADC_B0_ADCHCR24_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR24_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR24_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR24_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR24_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR24_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR25 ======================================================== */ + #define R_ADC_B0_ADCHCR25_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR25_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR25_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR25_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR25_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR25_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR26 ======================================================== */ + #define R_ADC_B0_ADCHCR26_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR26_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR26_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR26_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR26_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR26_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR27 ======================================================== */ + #define R_ADC_B0_ADCHCR27_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR27_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR27_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR27_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR27_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR27_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR28 ======================================================== */ + #define R_ADC_B0_ADCHCR28_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR28_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR28_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR28_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR28_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR28_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR29 ======================================================== */ + #define R_ADC_B0_ADCHCR29_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR29_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR29_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR29_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR29_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR29_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR30 ======================================================== */ + #define R_ADC_B0_ADCHCR30_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR30_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR30_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR30_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR30_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR30_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR31 ======================================================== */ + #define R_ADC_B0_ADCHCR31_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR31_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR31_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR31_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR31_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR31_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR32 ======================================================== */ + #define R_ADC_B0_ADCHCR32_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR32_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR32_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR32_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR32_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR32_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR33 ======================================================== */ + #define R_ADC_B0_ADCHCR33_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR33_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR33_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR33_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR33_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR33_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR33_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR33_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR34 ======================================================== */ + #define R_ADC_B0_ADCHCR34_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR34_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR34_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR34_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR34_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR34_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR34_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR34_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR35 ======================================================== */ + #define R_ADC_B0_ADCHCR35_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR35_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR35_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR35_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR35_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR35_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR35_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR35_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADCHCR36 ======================================================== */ + #define R_ADC_B0_ADCHCR36_SGSEL_Pos (0UL) /*!< SGSEL (Bit 0) */ + #define R_ADC_B0_ADCHCR36_SGSEL_Msk (0x1fUL) /*!< SGSEL (Bitfield-Mask: 0x1f) */ + #define R_ADC_B0_ADCHCR36_CNVCS_Pos (8UL) /*!< CNVCS (Bit 8) */ + #define R_ADC_B0_ADCHCR36_CNVCS_Msk (0x7f00UL) /*!< CNVCS (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADCHCR36_AINMD_Pos (15UL) /*!< AINMD (Bit 15) */ + #define R_ADC_B0_ADCHCR36_AINMD_Msk (0x8000UL) /*!< AINMD (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCHCR36_SSTSEL_Pos (16UL) /*!< SSTSEL (Bit 16) */ + #define R_ADC_B0_ADCHCR36_SSTSEL_Msk (0xf0000UL) /*!< SSTSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA0 ======================================================= */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA0_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA0_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA0_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA1 ======================================================= */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA1_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA1_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA1_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA2 ======================================================= */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA2_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA2_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA2_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA3 ======================================================= */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA3_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA3_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA3_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA4 ======================================================= */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA4_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA4_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA4_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA5 ======================================================= */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA5_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA5_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA5_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA6 ======================================================= */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA6_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA6_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA6_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA7 ======================================================= */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA7_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA7_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA7_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA8 ======================================================= */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA8_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA8_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA8_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRA9 ======================================================= */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA9_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA9_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA9_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA10 ======================================================= */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA10_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA10_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA10_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA11 ======================================================= */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA11_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA11_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA11_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA12 ======================================================= */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA12_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA12_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA12_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA13 ======================================================= */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA13_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA13_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA13_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA14 ======================================================= */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA14_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA14_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA14_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA15 ======================================================= */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA15_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA15_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA15_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA16 ======================================================= */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA16_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA16_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA16_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA17 ======================================================= */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA17_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA17_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA17_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA18 ======================================================= */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA18_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA18_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA18_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA19 ======================================================= */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA19_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA19_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA19_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA20 ======================================================= */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA20_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA20_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA20_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA21 ======================================================= */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA21_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA21_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA21_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA22 ======================================================= */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA22_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA22_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA22_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA23 ======================================================= */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA23_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA23_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA23_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA24 ======================================================= */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA24_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA24_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA24_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA25 ======================================================= */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA25_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA25_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA25_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA26 ======================================================= */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA26_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA26_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA26_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA27 ======================================================= */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA27_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA27_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA27_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA28 ======================================================= */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA28_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA28_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA28_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA29 ======================================================= */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA29_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA29_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA29_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA30 ======================================================= */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA30_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA30_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA30_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA31 ======================================================= */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA31_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA31_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA31_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA32 ======================================================= */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA32_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA32_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA32_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA33 ======================================================= */ + #define R_ADC_B0_ADDOPCRA33_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA33_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA33_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA33_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA33_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA34 ======================================================= */ + #define R_ADC_B0_ADDOPCRA34_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA34_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA34_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA34_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA34_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA35 ======================================================= */ + #define R_ADC_B0_ADDOPCRA35_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA35_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA35_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA35_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA35_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== ADDOPCRA36 ======================================================= */ + #define R_ADC_B0_ADDOPCRA36_DFSEL_Pos (0UL) /*!< DFSEL (Bit 0) */ + #define R_ADC_B0_ADDOPCRA36_DFSEL_Msk (0x7UL) /*!< DFSEL (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADDOPCRA36_GAINSEL_Pos (16UL) /*!< GAINSEL (Bit 16) */ + #define R_ADC_B0_ADDOPCRA36_GAINSEL_Msk (0xf0000UL) /*!< GAINSEL (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Pos (24UL) /*!< OFSETSEL (Bit 24) */ + #define R_ADC_B0_ADDOPCRA36_OFSETSEL_Msk (0xf000000UL) /*!< OFSETSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADDOPCRB0 ======================================================= */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB0_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB0_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB0_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB1 ======================================================= */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB1_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB1_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB1_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB2 ======================================================= */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB2_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB2_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB2_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB3 ======================================================= */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB3_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB3_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB3_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB4 ======================================================= */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB4_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB4_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB4_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB5 ======================================================= */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB5_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB5_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB5_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB6 ======================================================= */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB6_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB6_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB6_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB7 ======================================================= */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB7_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB7_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB7_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB8 ======================================================= */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB8_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB8_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB8_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRB9 ======================================================= */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB9_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB9_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB9_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB10 ======================================================= */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB10_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB10_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB10_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB11 ======================================================= */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB11_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB11_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB11_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB12 ======================================================= */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB12_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB12_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB12_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB13 ======================================================= */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB13_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB13_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB13_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB14 ======================================================= */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB14_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB14_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB14_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB15 ======================================================= */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB15_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB15_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB15_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB16 ======================================================= */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB16_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB16_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB16_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB17 ======================================================= */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB17_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB17_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB17_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB18 ======================================================= */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB18_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB18_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB18_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB19 ======================================================= */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB19_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB19_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB19_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB20 ======================================================= */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB20_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB20_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB20_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB21 ======================================================= */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB21_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB21_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB21_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB22 ======================================================= */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB22_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB22_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB22_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB23 ======================================================= */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB23_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB23_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB23_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB24 ======================================================= */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB24_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB24_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB24_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB25 ======================================================= */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB25_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB25_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB25_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB26 ======================================================= */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB26_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB26_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB26_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB27 ======================================================= */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB27_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB27_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB27_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB28 ======================================================= */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB28_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB28_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB28_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB29 ======================================================= */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB29_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB29_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB29_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB30 ======================================================= */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB30_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB30_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB30_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB31 ======================================================= */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB31_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB31_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB31_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB32 ======================================================= */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB32_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB32_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB32_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB33 ======================================================= */ + #define R_ADC_B0_ADDOPCRB33_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB33_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB33_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB33_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB33_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB34 ======================================================= */ + #define R_ADC_B0_ADDOPCRB34_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB34_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB34_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB34_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB34_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB35 ======================================================= */ + #define R_ADC_B0_ADDOPCRB35_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB35_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB35_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB35_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB35_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ====================================================== ADDOPCRB36 ======================================================= */ + #define R_ADC_B0_ADDOPCRB36_AVEMD_Pos (0UL) /*!< AVEMD (Bit 0) */ + #define R_ADC_B0_ADDOPCRB36_AVEMD_Msk (0x3UL) /*!< AVEMD (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRB36_ADC_Pos (8UL) /*!< ADC (Bit 8) */ + #define R_ADC_B0_ADDOPCRB36_ADC_Msk (0xf00UL) /*!< ADC (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Pos (16UL) /*!< CMPTBLEm (Bit 16) */ + #define R_ADC_B0_ADDOPCRB36_CMPTBLEm_Msk (0xff0000UL) /*!< CMPTBLEm (Bitfield-Mask: 0xff) */ +/* ======================================================= ADDOPCRC0 ======================================================= */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC0_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC0_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC0_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC1 ======================================================= */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC1_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC1_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC1_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC2 ======================================================= */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC2_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC2_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC2_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC3 ======================================================= */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC3_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC3_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC3_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC4 ======================================================= */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC4_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC4_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC4_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC5 ======================================================= */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC5_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC5_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC5_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC6 ======================================================= */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC6_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC6_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC6_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC7 ======================================================= */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC7_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC7_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC7_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC8 ======================================================= */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC8_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC8_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC8_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDOPCRC9 ======================================================= */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC9_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC9_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC9_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC10 ======================================================= */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC10_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC10_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC10_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC11 ======================================================= */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC11_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC11_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC11_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC12 ======================================================= */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC12_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC12_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC12_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC13 ======================================================= */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC13_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC13_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC13_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC14 ======================================================= */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC14_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC14_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC14_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC15 ======================================================= */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC15_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC15_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC15_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC16 ======================================================= */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC16_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC16_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC16_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC17 ======================================================= */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC17_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC17_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC17_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC18 ======================================================= */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC18_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC18_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC18_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC19 ======================================================= */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC19_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC19_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC19_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC20 ======================================================= */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC20_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC20_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC20_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC21 ======================================================= */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC21_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC21_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC21_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC22 ======================================================= */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC22_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC22_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC22_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC23 ======================================================= */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC23_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC23_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC23_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC24 ======================================================= */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC24_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC24_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC24_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC25 ======================================================= */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC25_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC25_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC25_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC26 ======================================================= */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC26_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC26_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC26_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC27 ======================================================= */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC27_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC27_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC27_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC28 ======================================================= */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC28_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC28_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC28_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC29 ======================================================= */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC29_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC29_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC29_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC30 ======================================================= */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC30_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC30_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC30_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC31 ======================================================= */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC31_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC31_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC31_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC32 ======================================================= */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC32_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC32_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC32_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC33 ======================================================= */ + #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC33_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC33_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC33_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC33_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC34 ======================================================= */ + #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC34_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC34_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC34_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC34_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC35 ======================================================= */ + #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC35_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC35_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC35_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC35_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ====================================================== ADDOPCRC36 ======================================================= */ + #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Pos (0UL) /*!< LIMTBLS (Bit 0) */ + #define R_ADC_B0_ADDOPCRC36_LIMTBLS_Msk (0xfUL) /*!< LIMTBLS (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADDOPCRC36_ADPRC_Pos (16UL) /*!< ADPRC (Bit 16) */ + #define R_ADC_B0_ADDOPCRC36_ADPRC_Msk (0x30000UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Pos (20UL) /*!< SIGNSEL (Bit 20) */ + #define R_ADC_B0_ADDOPCRC36_SIGNSEL_Msk (0x100000UL) /*!< SIGNSEL (Bitfield-Mask: 0x01) */ +/* ======================================================= ADCALSTR ======================================================== */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Pos (0UL) /*!< ADCALST0 (Bit 0) */ + #define R_ADC_B0_ADCALSTR_ADCALST0_Msk (0x7UL) /*!< ADCALST0 (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Pos (8UL) /*!< ADCALST1 (Bit 8) */ + #define R_ADC_B0_ADCALSTR_ADCALST1_Msk (0x700UL) /*!< ADCALST1 (Bitfield-Mask: 0x07) */ +/* ======================================================= ADTRGENR ======================================================== */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Pos (0UL) /*!< STTRGENn (Bit 0) */ + #define R_ADC_B0_ADTRGENR_STTRGENn_Msk (0x1ffUL) /*!< STTRGENn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADSYSTR ======================================================== */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Pos (0UL) /*!< ADSYSTn (Bit 0) */ + #define R_ADC_B0_ADSYSTR_ADSYSTn_Msk (0x1ffUL) /*!< ADSYSTn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADSTR ========================================================= */ + #define R_ADC_B0_ADSTR_ADST_Pos (0UL) /*!< ADST (Bit 0) */ + #define R_ADC_B0_ADSTR_ADST_Msk (0x1UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTOPR ======================================================== */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Pos (0UL) /*!< ADSTOP0 (Bit 0) */ + #define R_ADC_B0_ADSTOPR_ADSTOP0_Msk (0x1UL) /*!< ADSTOP0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Pos (8UL) /*!< ADSTOP1 (Bit 8) */ + #define R_ADC_B0_ADSTOPR_ADSTOP1_Msk (0x100UL) /*!< ADSTOP1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ADSR ========================================================== */ + #define R_ADC_B0_ADSR_ADACT0_Pos (0UL) /*!< ADACT0 (Bit 0) */ + #define R_ADC_B0_ADSR_ADACT0_Msk (0x1UL) /*!< ADACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_ADACT1_Pos (1UL) /*!< ADACT1 (Bit 1) */ + #define R_ADC_B0_ADSR_ADACT1_Msk (0x2UL) /*!< ADACT1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT0_Pos (16UL) /*!< CALACT0 (Bit 16) */ + #define R_ADC_B0_ADSR_CALACT0_Msk (0x10000UL) /*!< CALACT0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADSR_CALACT1_Pos (17UL) /*!< CALACT1 (Bit 17) */ + #define R_ADC_B0_ADSR_CALACT1_Msk (0x20000UL) /*!< CALACT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGRSR ========================================================= */ + #define R_ADC_B0_ADGRSR_ACTGRn_Pos (0UL) /*!< ACTGRn (Bit 0) */ + #define R_ADC_B0_ADGRSR_ACTGRn_Msk (0x1ffUL) /*!< ACTGRn (Bitfield-Mask: 0x1ff) */ +/* ======================================================== ADERSR ========================================================= */ + #define R_ADC_B0_ADERSR_ADERF0_Pos (0UL) /*!< ADERF0 (Bit 0) */ + #define R_ADC_B0_ADERSR_ADERF0_Msk (0x1UL) /*!< ADERF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSR_ADERF1_Pos (1UL) /*!< ADERF1 (Bit 1) */ + #define R_ADC_B0_ADERSR_ADERF1_Msk (0x2UL) /*!< ADERF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== ADERSCR ======================================================== */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Pos (0UL) /*!< ADERCLR0 (Bit 0) */ + #define R_ADC_B0_ADERSCR_ADERCLR0_Msk (0x1UL) /*!< ADERCLR0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Pos (1UL) /*!< ADERCLR1 (Bit 1) */ + #define R_ADC_B0_ADERSCR_ADERCLR1_Msk (0x2UL) /*!< ADERCLR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSR ======================================================= */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Pos (0UL) /*!< CALENDF0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSR_CALENDF0_Msk (0x1UL) /*!< CALENDF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Pos (1UL) /*!< CALENDF1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSR_CALENDF1_Msk (0x2UL) /*!< CALENDF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCALENDSCR ====================================================== */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Pos (0UL) /*!< CALENDC0 (Bit 0) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC0_Msk (0x1UL) /*!< CALENDC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Pos (1UL) /*!< CALENDC1 (Bit 1) */ + #define R_ADC_B0_ADCALENDSCR_CALENDC1_Msk (0x2UL) /*!< CALENDC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADOVFERSR ======================================================= */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Pos (0UL) /*!< ADOVFEF0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF0_Msk (0x1UL) /*!< ADOVFEF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Pos (1UL) /*!< ADOVFEF1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSR_ADOVFEF1_Msk (0x2UL) /*!< ADOVFEF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSR0 ======================================================= */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Pos (0UL) /*!< OVFCHFn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSR0_OVFCHFn_Msk (0x1fffffffUL) /*!< OVFCHFn (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================= ADOVFEXSR ======================================================= */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Pos (0UL) /*!< OVFEXF0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF0_Msk (0x1UL) /*!< OVFEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Pos (1UL) /*!< OVFEXF1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF1_Msk (0x2UL) /*!< OVFEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Pos (2UL) /*!< OVFEXF2 (Bit 2) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF2_Msk (0x4UL) /*!< OVFEXF2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Pos (5UL) /*!< OVFEXF5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF5_Msk (0x20UL) /*!< OVFEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Pos (6UL) /*!< OVFEXF6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF6_Msk (0x40UL) /*!< OVFEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Pos (7UL) /*!< OVFEXF7 (Bit 7) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF7_Msk (0x80UL) /*!< OVFEXF7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Pos (8UL) /*!< OVFEXF8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSR_OVFEXF8_Msk (0x100UL) /*!< OVFEXF8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFERSCR ======================================================= */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Pos (0UL) /*!< ADOVFEC0 (Bit 0) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC0_Msk (0x1UL) /*!< ADOVFEC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Pos (1UL) /*!< ADOVFEC1 (Bit 1) */ + #define R_ADC_B0_ADOVFERSCR_ADOVFEC1_Msk (0x2UL) /*!< ADOVFEC1 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADOVFCHSCR0 ====================================================== */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Pos (0UL) /*!< OVFCHCn (Bit 0) */ + #define R_ADC_B0_ADOVFCHSCR0_OVFCHCn_Msk (0x1fffffffUL) /*!< OVFCHCn (Bitfield-Mask: 0x1fffffff) */ +/* ====================================================== ADOVFEXSCR ======================================================= */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Pos (0UL) /*!< OVFEXC0 (Bit 0) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC0_Msk (0x1UL) /*!< OVFEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Pos (1UL) /*!< OVFEXC1 (Bit 1) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC1_Msk (0x2UL) /*!< OVFEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Pos (2UL) /*!< OVFEXC2 (Bit 2) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC2_Msk (0x4UL) /*!< OVFEXC2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Pos (5UL) /*!< OVFEXC5 (Bit 5) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC5_Msk (0x20UL) /*!< OVFEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Pos (6UL) /*!< OVFEXC6 (Bit 6) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC6_Msk (0x40UL) /*!< OVFEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Pos (7UL) /*!< OVFEXC7 (Bit 7) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC7_Msk (0x80UL) /*!< OVFEXC7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Pos (8UL) /*!< OVFEXC8 (Bit 8) */ + #define R_ADC_B0_ADOVFEXSCR_OVFEXC8_Msk (0x100UL) /*!< OVFEXC8 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFOSR0 ======================================================= */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Pos (0UL) /*!< FIFOST0 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST0_Msk (0xfUL) /*!< FIFOST0 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Pos (16UL) /*!< FIFOST1 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR0_FIFOST1_Msk (0xf0000UL) /*!< FIFOST1 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR1 ======================================================= */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Pos (0UL) /*!< FIFOST2 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST2_Msk (0xfUL) /*!< FIFOST2 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Pos (16UL) /*!< FIFOST3 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR1_FIFOST3_Msk (0xf0000UL) /*!< FIFOST3 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR2 ======================================================= */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Pos (0UL) /*!< FIFOST4 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST4_Msk (0xfUL) /*!< FIFOST4 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Pos (16UL) /*!< FIFOST5 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR2_FIFOST5_Msk (0xf0000UL) /*!< FIFOST5 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR3 ======================================================= */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Pos (0UL) /*!< FIFOST6 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST6_Msk (0xfUL) /*!< FIFOST6 (Bitfield-Mask: 0x0f) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Pos (16UL) /*!< FIFOST7 (Bit 16) */ + #define R_ADC_B0_ADFIFOSR3_FIFOST7_Msk (0xf0000UL) /*!< FIFOST7 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFOSR4 ======================================================= */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Pos (0UL) /*!< FIFOST8 (Bit 0) */ + #define R_ADC_B0_ADFIFOSR4_FIFOST8_Msk (0xfUL) /*!< FIFOST8 (Bitfield-Mask: 0x0f) */ +/* ======================================================= ADFIFODCR ======================================================= */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Pos (0UL) /*!< FIFODCn (Bit 0) */ + #define R_ADC_B0_ADFIFODCR_FIFODCn_Msk (0x1ffUL) /*!< FIFODCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSR ======================================================= */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Pos (0UL) /*!< FIFOOVFn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSR_FIFOOVFn_Msk (0x1ffUL) /*!< FIFOOVFn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Pos (16UL) /*!< FIFOFLFn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSR_FIFOFLFn_Msk (0x1ff0000UL) /*!< FIFOFLFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADFIFOERSCR ====================================================== */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Pos (0UL) /*!< FIFOOVFCn (Bit 0) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOOVFCn_Msk (0x1ffUL) /*!< FIFOOVFCn (Bitfield-Mask: 0x1ff) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Pos (16UL) /*!< FIFOFLCn (Bit 16) */ + #define R_ADC_B0_ADFIFOERSCR_FIFOFLCn_Msk (0x1ff0000UL) /*!< FIFOFLCn (Bitfield-Mask: 0x1ff) */ +/* ======================================================= ADCMPTBSR ======================================================= */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Pos (0UL) /*!< CMPTBFn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSR_CMPTBFn_Msk (0xffUL) /*!< CMPTBFn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPTBSCR ======================================================= */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Pos (0UL) /*!< CMPTBCn (Bit 0) */ + #define R_ADC_B0_ADCMPTBSCR_CMPTBCn_Msk (0xffUL) /*!< CMPTBCn (Bitfield-Mask: 0xff) */ +/* ====================================================== ADCMPCHSR0 ======================================================= */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Pos (0UL) /*!< CMPCHFn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSR0_CMPCHFn_Msk (0x1fffffffUL) /*!< CMPCHFn (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================= ADCMPEXSR ======================================================= */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Pos (0UL) /*!< CMPEXF0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF0_Msk (0x1UL) /*!< CMPEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Pos (1UL) /*!< CMPEXF1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF1_Msk (0x2UL) /*!< CMPEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Pos (2UL) /*!< CMPEXF2 (Bit 2) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF2_Msk (0x4UL) /*!< CMPEXF2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Pos (5UL) /*!< CMPEXF5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF5_Msk (0x20UL) /*!< CMPEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Pos (6UL) /*!< CMPEXF6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF6_Msk (0x40UL) /*!< CMPEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Pos (7UL) /*!< CMPEXF7 (Bit 7) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF7_Msk (0x80UL) /*!< CMPEXF7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Pos (8UL) /*!< CMPEXF8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSR_CMPEXF8_Msk (0x100UL) /*!< CMPEXF8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPCHSCR0 ====================================================== */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Pos (0UL) /*!< CMPCHCn (Bit 0) */ + #define R_ADC_B0_ADCMPCHSCR0_CMPCHCn_Msk (0x1fffffffUL) /*!< CMPCHCn (Bitfield-Mask: 0x1fffffff) */ +/* ====================================================== ADCMPEXSCR ======================================================= */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Pos (0UL) /*!< CMPEXC0 (Bit 0) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC0_Msk (0x1UL) /*!< CMPEXC0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Pos (1UL) /*!< CMPEXC1 (Bit 1) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC1_Msk (0x2UL) /*!< CMPEXC1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Pos (2UL) /*!< CMPEXC2 (Bit 2) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC2_Msk (0x4UL) /*!< CMPEXC2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Pos (5UL) /*!< CMPEXC5 (Bit 5) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC5_Msk (0x20UL) /*!< CMPEXC5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Pos (6UL) /*!< CMPEXC6 (Bit 6) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC6_Msk (0x40UL) /*!< CMPEXC6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Pos (7UL) /*!< CMPEXC7 (Bit 7) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC7_Msk (0x80UL) /*!< CMPEXC7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Pos (8UL) /*!< CMPEXC8 (Bit 8) */ + #define R_ADC_B0_ADCMPEXSCR_CMPEXC8_Msk (0x100UL) /*!< CMPEXC8 (Bitfield-Mask: 0x01) */ +/* ======================================================= ADLIMGRSR ======================================================= */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Pos (0UL) /*!< LIMGRFn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSR_LIMGRFn_Msk (0x1ffUL) /*!< LIMGRFn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSR0 ======================================================= */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Pos (0UL) /*!< LIMCHFn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSR0_LIMCHFn_Msk (0x1fffffffUL) /*!< LIMCHFn (Bitfield-Mask: 0x1fffffff) */ +/* ======================================================= ADLIMEXSR ======================================================= */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADLIMGRSCR ======================================================= */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Pos (0UL) /*!< LIMGRCn (Bit 0) */ + #define R_ADC_B0_ADLIMGRSCR_LIMGRCn_Msk (0x1ffUL) /*!< LIMGRCn (Bitfield-Mask: 0x1ff) */ +/* ====================================================== ADLIMCHSCR0 ====================================================== */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Pos (0UL) /*!< LIMCHCn (Bit 0) */ + #define R_ADC_B0_ADLIMCHSCR0_LIMCHCn_Msk (0x1fffffffUL) /*!< LIMCHCn (Bitfield-Mask: 0x1fffffff) */ +/* ====================================================== ADLIMEXSCR ======================================================= */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Pos (0UL) /*!< LIMEXF0 (Bit 0) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF0_Msk (0x1UL) /*!< LIMEXF0 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Pos (1UL) /*!< LIMEXF1 (Bit 1) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF1_Msk (0x2UL) /*!< LIMEXF1 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Pos (2UL) /*!< LIMEXF2 (Bit 2) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF2_Msk (0x4UL) /*!< LIMEXF2 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Pos (5UL) /*!< LIMEXF5 (Bit 5) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF5_Msk (0x20UL) /*!< LIMEXF5 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Pos (6UL) /*!< LIMEXF6 (Bit 6) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF6_Msk (0x40UL) /*!< LIMEXF6 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Pos (7UL) /*!< LIMEXF7 (Bit 7) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF7_Msk (0x80UL) /*!< LIMEXF7 (Bitfield-Mask: 0x01) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Pos (8UL) /*!< LIMEXF8 (Bit 8) */ + #define R_ADC_B0_ADLIMEXSCR_LIMEXF8_Msk (0x100UL) /*!< LIMEXF8 (Bitfield-Mask: 0x01) */ +/* ====================================================== ADSCANENDSR ====================================================== */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Pos (0UL) /*!< SCENDFn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSR_SCENDFn_Msk (0x1ffUL) /*!< SCENDFn (Bitfield-Mask: 0x1ff) */ +/* ===================================================== ADSCANENDSCR ====================================================== */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Pos (0UL) /*!< SCENDCn (Bit 0) */ + #define R_ADC_B0_ADSCANENDSCR_SCENDCn_Msk (0x1ffUL) /*!< SCENDCn (Bitfield-Mask: 0x1ff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC_B0_ADDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================== ADEXDR ========================================================= */ + #define R_ADC_B0_ADEXDR_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADEXDR_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Pos (24UL) /*!< DIAGSR (Bit 24) */ + #define R_ADC_B0_ADEXDR_DIAGSR_Msk (0x7000000UL) /*!< DIAGSR (Bitfield-Mask: 0x07) */ + #define R_ADC_B0_ADEXDR_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADEXDR_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR0 ======================================================= */ + #define R_ADC_B0_ADFIFODR0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR0_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR0_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR0_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR0_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR1 ======================================================= */ + #define R_ADC_B0_ADFIFODR1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR1_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR1_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR1_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR1_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR2 ======================================================= */ + #define R_ADC_B0_ADFIFODR2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR2_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR2_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR2_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR2_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR3 ======================================================= */ + #define R_ADC_B0_ADFIFODR3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR3_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR3_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR3_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR3_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR4 ======================================================= */ + #define R_ADC_B0_ADFIFODR4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR4_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR4_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR4_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR4_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR5 ======================================================= */ + #define R_ADC_B0_ADFIFODR5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR5_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR5_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR5_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR5_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR6 ======================================================= */ + #define R_ADC_B0_ADFIFODR6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR6_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR6_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR6_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR6_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR7 ======================================================= */ + #define R_ADC_B0_ADFIFODR7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR7_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR7_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR7_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR7_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ +/* ======================================================= ADFIFODR8 ======================================================= */ + #define R_ADC_B0_ADFIFODR8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_ADC_B0_ADFIFODR8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ + #define R_ADC_B0_ADFIFODR8_CH_Pos (24UL) /*!< CH (Bit 24) */ + #define R_ADC_B0_ADFIFODR8_CH_Msk (0x7f000000UL) /*!< CH (Bitfield-Mask: 0x7f) */ + #define R_ADC_B0_ADFIFODR8_ERR_Pos (31UL) /*!< ERR (Bit 31) */ + #define R_ADC_B0_ADFIFODR8_ERR_Msk (0x80000000UL) /*!< ERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC_B ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_B_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_B_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_B_DOCR_DOBW_Pos (3UL) /*!< DOBW (Bit 3) */ + #define R_DOC_B_DOCR_DOBW_Msk (0x8UL) /*!< DOBW (Bitfield-Mask: 0x01) */ + #define R_DOC_B_DOCR_DCSEL_Pos (4UL) /*!< DCSEL (Bit 4) */ + #define R_DOC_B_DOCR_DCSEL_Msk (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07) */ + #define R_DOC_B_DOCR_DOPCIE_Pos (7UL) /*!< DOPCIE (Bit 7) */ + #define R_DOC_B_DOCR_DOPCIE_Msk (0x80UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSR ========================================================== */ + #define R_DOC_B_DOSR_DOPCF_Pos (0UL) /*!< DOPCF (Bit 0) */ + #define R_DOC_B_DOSR_DOPCF_Msk (0x1UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ +/* ========================================================= DOSCR ========================================================= */ + #define R_DOC_B_DOSCR_DOPCFCL_Pos (0UL) /*!< DOPCFCL (Bit 0) */ + #define R_DOC_B_DOSCR_DOPCFCL_Msk (0x1UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ======================================================== DODSR0 ========================================================= */ +/* ======================================================== DODSR1 ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI_B0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI_B0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI_B0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI_B0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI_B0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI_B0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI_B0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI_B0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI_B0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_TDR_TSYNC_Pos (12UL) /*!< TSYNC (Bit 12) */ + #define R_SCI_B0_TDR_TSYNC_Msk (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI_B0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI_B0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI_B0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI_B0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI_B0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI_B0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI_B0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI_B0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI_B0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI_B0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI_B0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI_B0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI_B0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI_B0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI_B0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI_B0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI_B0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI_B0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI_B0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI_B0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI_B0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI_B0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI_B0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI_B0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI_B0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI_B0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI_B0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI_B0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI_B0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI_B0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI_B0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI_B0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI_B0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI_B0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI_B0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI_B0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI_B0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI_B0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI_B0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI_B0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI_B0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI_B0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI_B0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI_B0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI_B0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI_B0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI_B0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI_B0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI_B0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI_B0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI_B0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI_B0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI_B0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI_B0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI_B0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI_B0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI_B0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================= CESR ========================================================== */ + #define R_SCI_B0_CESR_RIST_Pos (0UL) /*!< RIST (Bit 0) */ + #define R_SCI_B0_CESR_RIST_Msk (0x1UL) /*!< RIST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CESR_TIST_Pos (4UL) /*!< TIST (Bit 4) */ + #define R_SCI_B0_CESR_TIST_Msk (0x10UL) /*!< TIST (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI_B0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI_B0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI_B0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI_B0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI_B0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI_B0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI_B0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI_B0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI_B0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI_B0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI_B0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI_B0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI_B0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI_B0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI_B0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI_B0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI_B0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== MCR ========================================================== */ + #define R_SCI_B0_MCR_RMPOL_Pos (0UL) /*!< RMPOL (Bit 0) */ + #define R_SCI_B0_MCR_RMPOL_Msk (0x1UL) /*!< RMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TMPOL_Pos (1UL) /*!< TMPOL (Bit 1) */ + #define R_SCI_B0_MCR_TMPOL_Msk (0x2UL) /*!< TMPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_ERTEN_Pos (2UL) /*!< ERTEN (Bit 2) */ + #define R_SCI_B0_MCR_ERTEN_Msk (0x4UL) /*!< ERTEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNVAL_Pos (4UL) /*!< SYNVAL (Bit 4) */ + #define R_SCI_B0_MCR_SYNVAL_Msk (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYNSEL_Pos (5UL) /*!< SYNSEL (Bit 5) */ + #define R_SCI_B0_MCR_SYNSEL_Msk (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBSEL_Pos (6UL) /*!< SBSEL (Bit 6) */ + #define R_SCI_B0_MCR_SBSEL_Msk (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_TPLEN_Pos (8UL) /*!< TPLEN (Bit 8) */ + #define R_SCI_B0_MCR_TPLEN_Msk (0xf00UL) /*!< TPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_TPPAT_Pos (12UL) /*!< TPPAT (Bit 12) */ + #define R_SCI_B0_MCR_TPPAT_Msk (0x3000UL) /*!< TPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_RPLEN_Pos (16UL) /*!< RPLEN (Bit 16) */ + #define R_SCI_B0_MCR_RPLEN_Msk (0xf0000UL) /*!< RPLEN (Bitfield-Mask: 0x0f) */ + #define R_SCI_B0_MCR_RPPAT_Pos (20UL) /*!< RPPAT (Bit 20) */ + #define R_SCI_B0_MCR_RPPAT_Msk (0x300000UL) /*!< RPPAT (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_MCR_PFEREN_Pos (24UL) /*!< PFEREN (Bit 24) */ + #define R_SCI_B0_MCR_PFEREN_Msk (0x1000000UL) /*!< PFEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SYEREN_Pos (25UL) /*!< SYEREN (Bit 25) */ + #define R_SCI_B0_MCR_SYEREN_Msk (0x2000000UL) /*!< SYEREN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MCR_SBEREN_Pos (26UL) /*!< SBEREN (Bit 26) */ + #define R_SCI_B0_MCR_SBEREN_Msk (0x4000000UL) /*!< SBEREN (Bitfield-Mask: 0x01) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI_B0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI_B0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI_B0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI_B0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI_B0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================= XCR0 ========================================================== */ + #define R_SCI_B0_XCR0_TCSS_Pos (0UL) /*!< TCSS (Bit 0) */ + #define R_SCI_B0_XCR0_TCSS_Msk (0x3UL) /*!< TCSS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_BFE_Pos (8UL) /*!< BFE (Bit 8) */ + #define R_SCI_B0_XCR0_BFE_Msk (0x100UL) /*!< BFE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF0RE_Pos (9UL) /*!< CF0RE (Bit 9) */ + #define R_SCI_B0_XCR0_CF0RE_Msk (0x200UL) /*!< CF0RE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_CF1DS_Pos (10UL) /*!< CF1DS (Bit 10) */ + #define R_SCI_B0_XCR0_CF1DS_Msk (0xc00UL) /*!< CF1DS (Bitfield-Mask: 0x03) */ + #define R_SCI_B0_XCR0_PIBE_Pos (12UL) /*!< PIBE (Bit 12) */ + #define R_SCI_B0_XCR0_PIBE_Msk (0x1000UL) /*!< PIBE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_PIBS_Pos (13UL) /*!< PIBS (Bit 13) */ + #define R_SCI_B0_XCR0_PIBS_Msk (0xe000UL) /*!< PIBS (Bitfield-Mask: 0x07) */ + #define R_SCI_B0_XCR0_BFOIE_Pos (16UL) /*!< BFOIE (Bit 16) */ + #define R_SCI_B0_XCR0_BFOIE_Msk (0x10000UL) /*!< BFOIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCDIE_Pos (17UL) /*!< BCDIE (Bit 17) */ + #define R_SCI_B0_XCR0_BCDIE_Msk (0x20000UL) /*!< BCDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BFDIE_Pos (20UL) /*!< BFDIE (Bit 20) */ + #define R_SCI_B0_XCR0_BFDIE_Msk (0x100000UL) /*!< BFDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_COFIE_Pos (21UL) /*!< COFIE (Bit 21) */ + #define R_SCI_B0_XCR0_COFIE_Msk (0x200000UL) /*!< COFIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_AEDIE_Pos (22UL) /*!< AEDIE (Bit 22) */ + #define R_SCI_B0_XCR0_AEDIE_Msk (0x400000UL) /*!< AEDIE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR0_BCCS_Pos (24UL) /*!< BCCS (Bit 24) */ + #define R_SCI_B0_XCR0_BCCS_Msk (0x3000000UL) /*!< BCCS (Bitfield-Mask: 0x03) */ +/* ========================================================= XCR1 ========================================================== */ + #define R_SCI_B0_XCR1_TCST_Pos (0UL) /*!< TCST (Bit 0) */ + #define R_SCI_B0_XCR1_TCST_Msk (0x1UL) /*!< TCST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_SDST_Pos (4UL) /*!< SDST (Bit 4) */ + #define R_SCI_B0_XCR1_SDST_Msk (0x10UL) /*!< SDST (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_BMEN_Pos (5UL) /*!< BMEN (Bit 5) */ + #define R_SCI_B0_XCR1_BMEN_Msk (0x20UL) /*!< BMEN (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XCR1_PCF1D_Pos (8UL) /*!< PCF1D (Bit 8) */ + #define R_SCI_B0_XCR1_PCF1D_Msk (0xff00UL) /*!< PCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_SCF1D_Pos (16UL) /*!< SCF1D (Bit 16) */ + #define R_SCI_B0_XCR1_SCF1D_Msk (0xff0000UL) /*!< SCF1D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR1_CF1CE_Pos (24UL) /*!< CF1CE (Bit 24) */ + #define R_SCI_B0_XCR1_CF1CE_Msk (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff) */ +/* ========================================================= XCR2 ========================================================== */ + #define R_SCI_B0_XCR2_CF0D_Pos (0UL) /*!< CF0D (Bit 0) */ + #define R_SCI_B0_XCR2_CF0D_Msk (0xffUL) /*!< CF0D (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_CF0CE_Pos (8UL) /*!< CF0CE (Bit 8) */ + #define R_SCI_B0_XCR2_CF0CE_Msk (0xff00UL) /*!< CF0CE (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XCR2_BFLW_Pos (16UL) /*!< BFLW (Bit 16) */ + #define R_SCI_B0_XCR2_BFLW_Msk (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI_B0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI_B0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI_B0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI_B0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI_B0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI_B0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI_B0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI_B0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI_B0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI_B0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI_B0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI_B0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI_B0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI_B0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI_B0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI_B0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI_B0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI_B0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI_B0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI_B0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI_B0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI_B0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI_B0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI_B0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================== MSR ========================================================== */ + #define R_SCI_B0_MSR_PFER_Pos (0UL) /*!< PFER (Bit 0) */ + #define R_SCI_B0_MSR_PFER_Msk (0x1UL) /*!< PFER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SYER_Pos (1UL) /*!< SYER (Bit 1) */ + #define R_SCI_B0_MSR_SYER_Msk (0x2UL) /*!< SYER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_SBER_Pos (2UL) /*!< SBER (Bit 2) */ + #define R_SCI_B0_MSR_SBER_Msk (0x4UL) /*!< SBER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_MER_Pos (4UL) /*!< MER (Bit 4) */ + #define R_SCI_B0_MSR_MER_Msk (0x10UL) /*!< MER (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MSR_RSYNC_Pos (6UL) /*!< RSYNC (Bit 6) */ + #define R_SCI_B0_MSR_RSYNC_Msk (0x40UL) /*!< RSYNC (Bitfield-Mask: 0x01) */ +/* ========================================================= XSR0 ========================================================== */ + #define R_SCI_B0_XSR0_SFSF_Pos (0UL) /*!< SFSF (Bit 0) */ + #define R_SCI_B0_XSR0_SFSF_Msk (0x1UL) /*!< SFSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_RXDSF_Pos (1UL) /*!< RXDSF (Bit 1) */ + #define R_SCI_B0_XSR0_RXDSF_Msk (0x2UL) /*!< RXDSF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFOF_Pos (8UL) /*!< BFOF (Bit 8) */ + #define R_SCI_B0_XSR0_BFOF_Msk (0x100UL) /*!< BFOF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BCDF_Pos (9UL) /*!< BCDF (Bit 9) */ + #define R_SCI_B0_XSR0_BCDF_Msk (0x200UL) /*!< BCDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_BFDF_Pos (10UL) /*!< BFDF (Bit 10) */ + #define R_SCI_B0_XSR0_BFDF_Msk (0x400UL) /*!< BFDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0MF_Pos (11UL) /*!< CF0MF (Bit 11) */ + #define R_SCI_B0_XSR0_CF0MF_Msk (0x800UL) /*!< CF0MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF1MF_Pos (12UL) /*!< CF1MF (Bit 12) */ + #define R_SCI_B0_XSR0_CF1MF_Msk (0x1000UL) /*!< CF1MF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_PIBDF_Pos (13UL) /*!< PIBDF (Bit 13) */ + #define R_SCI_B0_XSR0_PIBDF_Msk (0x2000UL) /*!< PIBDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_COF_Pos (14UL) /*!< COF (Bit 14) */ + #define R_SCI_B0_XSR0_COF_Msk (0x4000UL) /*!< COF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_AEDF_Pos (15UL) /*!< AEDF (Bit 15) */ + #define R_SCI_B0_XSR0_AEDF_Msk (0x8000UL) /*!< AEDF (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XSR0_CF0RD_Pos (16UL) /*!< CF0RD (Bit 16) */ + #define R_SCI_B0_XSR0_CF0RD_Msk (0xff0000UL) /*!< CF0RD (Bitfield-Mask: 0xff) */ + #define R_SCI_B0_XSR0_CF1RD_Pos (24UL) /*!< CF1RD (Bit 24) */ + #define R_SCI_B0_XSR0_CF1RD_Msk (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff) */ +/* ========================================================= XSR1 ========================================================== */ + #define R_SCI_B0_XSR1_TCNT_Pos (0UL) /*!< TCNT (Bit 0) */ + #define R_SCI_B0_XSR1_TCNT_Msk (0xffffUL) /*!< TCNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI_B0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI_B0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI_B0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI_B0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI_B0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI_B0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI_B0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI_B0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI_B0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI_B0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI_B0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI_B0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI_B0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI_B0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ +/* ========================================================= MFCLR ========================================================= */ + #define R_SCI_B0_MFCLR_PFERC_Pos (0UL) /*!< PFERC (Bit 0) */ + #define R_SCI_B0_MFCLR_PFERC_Msk (0x1UL) /*!< PFERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SYERC_Pos (1UL) /*!< SYERC (Bit 1) */ + #define R_SCI_B0_MFCLR_SYERC_Msk (0x2UL) /*!< SYERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_SBERC_Pos (2UL) /*!< SBERC (Bit 2) */ + #define R_SCI_B0_MFCLR_SBERC_Msk (0x4UL) /*!< SBERC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_MFCLR_MERC_Pos (4UL) /*!< MERC (Bit 4) */ + #define R_SCI_B0_MFCLR_MERC_Msk (0x10UL) /*!< MERC (Bitfield-Mask: 0x01) */ +/* ========================================================= XFCLR ========================================================= */ + #define R_SCI_B0_XFCLR_BFOC_Pos (8UL) /*!< BFOC (Bit 8) */ + #define R_SCI_B0_XFCLR_BFOC_Msk (0x100UL) /*!< BFOC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BCDC_Pos (9UL) /*!< BCDC (Bit 9) */ + #define R_SCI_B0_XFCLR_BCDC_Msk (0x200UL) /*!< BCDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_BFDC_Pos (10UL) /*!< BFDC (Bit 10) */ + #define R_SCI_B0_XFCLR_BFDC_Msk (0x400UL) /*!< BFDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF0MC_Pos (11UL) /*!< CF0MC (Bit 11) */ + #define R_SCI_B0_XFCLR_CF0MC_Msk (0x800UL) /*!< CF0MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_CF1MC_Pos (12UL) /*!< CF1MC (Bit 12) */ + #define R_SCI_B0_XFCLR_CF1MC_Msk (0x1000UL) /*!< CF1MC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_PIBDC_Pos (13UL) /*!< PIBDC (Bit 13) */ + #define R_SCI_B0_XFCLR_PIBDC_Msk (0x2000UL) /*!< PIBDC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_COFC_Pos (14UL) /*!< COFC (Bit 14) */ + #define R_SCI_B0_XFCLR_COFC_Msk (0x4000UL) /*!< COFC (Bitfield-Mask: 0x01) */ + #define R_SCI_B0_XFCLR_AEDC_Pos (15UL) /*!< AEDC (Bit 15) */ + #define R_SCI_B0_XFCLR_AEDC_Msk (0x8000UL) /*!< AEDC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI_B0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ +/* ======================================================== SPDECR ========================================================= */ + #define R_SPI_B0_SPDECR_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI_B0_SPDECR_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SLNDL_Pos (8UL) /*!< SLNDL (Bit 8) */ + #define R_SPI_B0_SPDECR_SLNDL_Msk (0x700UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_SPNDL_Pos (16UL) /*!< SPNDL (Bit 16) */ + #define R_SPI_B0_SPDECR_SPNDL_Msk (0x70000UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPDECR_ARST_Pos (24UL) /*!< ARST (Bit 24) */ + #define R_SPI_B0_SPDECR_ARST_Msk (0x7000000UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI_B0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI_B0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI_B0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI_B0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI_B0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI_B0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI_B0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI_B0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI_B0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI_B0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI_B0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI_B0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI_B0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI_B0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI_B0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI_B0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI_B0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI_B0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI_B0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI_B0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI_B0_SPCR2_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI_B0_SPCR2_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCR2_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI_B0_SPCR2_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI_B0_SPCR2_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPDRC_Pos (8UL) /*!< SPDRC (Bit 8) */ + #define R_SPI_B0_SPCR2_SPDRC_Msk (0xff00UL) /*!< SPDRC (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR2_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SPI_B0_SPCR2_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_SPLP2_Pos (17UL) /*!< SPLP2 (Bit 17) */ + #define R_SPI_B0_SPCR2_SPLP2_Msk (0x20000UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFV_Pos (20UL) /*!< MOIFV (Bit 20) */ + #define R_SPI_B0_SPCR2_MOIFV_Msk (0x100000UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR2_MOIFE_Pos (21UL) /*!< MOIFE (Bit 21) */ + #define R_SPI_B0_SPCR2_MOIFE_Msk (0x200000UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR3 ========================================================= */ + #define R_SPI_B0_SPCR3_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI_B0_SPCR3_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI_B0_SPCR3_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI_B0_SPCR3_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI_B0_SPCR3_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCR3_SPBR_Pos (8UL) /*!< SPBR (Bit 8) */ + #define R_SPI_B0_SPCR3_SPBR_Msk (0xff00UL) /*!< SPBR (Bitfield-Mask: 0xff) */ + #define R_SPI_B0_SPCR3_SPSLN_Pos (24UL) /*!< SPSLN (Bit 24) */ + #define R_SPI_B0_SPCR3_SPSLN_Msk (0x7000000UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD0 ========================================================= */ + #define R_SPI_B0_SPCMD0_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD0_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD0_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD0_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD0_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD0_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD0_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD0_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD0_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD0_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD0_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD0_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD0_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD0_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD1 ========================================================= */ + #define R_SPI_B0_SPCMD1_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD1_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD1_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD1_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD1_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD1_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD1_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD1_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD1_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD1_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD1_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD1_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD1_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD1_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD2 ========================================================= */ + #define R_SPI_B0_SPCMD2_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD2_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD2_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD2_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD2_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD2_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD2_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD2_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD2_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD2_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD2_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD2_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD2_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD2_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD3 ========================================================= */ + #define R_SPI_B0_SPCMD3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD3_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD3_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD3_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD3_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD3_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD3_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD3_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD3_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD3_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD3_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD4 ========================================================= */ + #define R_SPI_B0_SPCMD4_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD4_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD4_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD4_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD4_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD4_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD4_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD4_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD4_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD4_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD4_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD4_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD4_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD4_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD5 ========================================================= */ + #define R_SPI_B0_SPCMD5_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD5_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD5_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD5_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD5_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD5_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD5_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD5_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD5_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD5_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD5_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD5_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD5_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD5_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD6 ========================================================= */ + #define R_SPI_B0_SPCMD6_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD6_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD6_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD6_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD6_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD6_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD6_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD6_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD6_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD6_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD6_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD6_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD6_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD6_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ======================================================== SPCMD7 ========================================================= */ + #define R_SPI_B0_SPCMD7_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI_B0_SPCMD7_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI_B0_SPCMD7_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI_B0_SPCMD7_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPCMD7_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI_B0_SPCMD7_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI_B0_SPCMD7_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI_B0_SPCMD7_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI_B0_SPCMD7_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI_B0_SPCMD7_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPCMD7_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI_B0_SPCMD7_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI_B0_SPCMD7_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI_B0_SPCMD7_SSLA_Msk (0x7000000UL) /*!< SSLA (Bitfield-Mask: 0x07) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI_B0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI_B0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI_B0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI_B0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI_B0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI_B0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI_B0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI_B0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI_B0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI_B0_SPSR_SPCP_Pos (8UL) /*!< SPCP (Bit 8) */ + #define R_SPI_B0_SPSR_SPCP_Msk (0x700UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPECM_Pos (12UL) /*!< SPECM (Bit 12) */ + #define R_SPI_B0_SPSR_SPECM_Msk (0x7000UL) /*!< SPECM (Bitfield-Mask: 0x07) */ + #define R_SPI_B0_SPSR_SPDRF_Pos (23UL) /*!< SPDRF (Bit 23) */ + #define R_SPI_B0_SPSR_SPDRF_Msk (0x800000UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_OVRF_Pos (24UL) /*!< OVRF (Bit 24) */ + #define R_SPI_B0_SPSR_OVRF_Msk (0x1000000UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_IDLNF_Pos (25UL) /*!< IDLNF (Bit 25) */ + #define R_SPI_B0_SPSR_IDLNF_Msk (0x2000000UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_MODF_Pos (26UL) /*!< MODF (Bit 26) */ + #define R_SPI_B0_SPSR_MODF_Msk (0x4000000UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_PERF_Pos (27UL) /*!< PERF (Bit 27) */ + #define R_SPI_B0_SPSR_PERF_Msk (0x8000000UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_UDRF_Pos (28UL) /*!< UDRF (Bit 28) */ + #define R_SPI_B0_SPSR_UDRF_Msk (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPTEF_Pos (29UL) /*!< SPTEF (Bit 29) */ + #define R_SPI_B0_SPSR_SPTEF_Msk (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_CENDF_Pos (30UL) /*!< CENDF (Bit 30) */ + #define R_SPI_B0_SPSR_CENDF_Msk (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSR_SPRF_Pos (31UL) /*!< SPRF (Bit 31) */ + #define R_SPI_B0_SPSR_SPRF_Msk (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI_B0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI_B0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI_B0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI_B0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI_B0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI_B0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI_B0_SPSRC_SPDRFC_Pos (23UL) /*!< SPDRFC (Bit 23) */ + #define R_SPI_B0_SPSRC_SPDRFC_Msk (0x800000UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_OVRFC_Pos (24UL) /*!< OVRFC (Bit 24) */ + #define R_SPI_B0_SPSRC_OVRFC_Msk (0x1000000UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_MODFC_Pos (26UL) /*!< MODFC (Bit 26) */ + #define R_SPI_B0_SPSRC_MODFC_Msk (0x4000000UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_PERFC_Pos (27UL) /*!< PERFC (Bit 27) */ + #define R_SPI_B0_SPSRC_PERFC_Msk (0x8000000UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_UDRFC_Pos (28UL) /*!< UDRFC (Bit 28) */ + #define R_SPI_B0_SPSRC_UDRFC_Msk (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPTEFC_Pos (29UL) /*!< SPTEFC (Bit 29) */ + #define R_SPI_B0_SPSRC_SPTEFC_Msk (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_CENDFC_Pos (30UL) /*!< CENDFC (Bit 30) */ + #define R_SPI_B0_SPSRC_CENDFC_Msk (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI_B0_SPSRC_SPRFC_Pos (31UL) /*!< SPRFC (Bit 31) */ + #define R_SPI_B0_SPSRC_SPRFC_Msk (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI_B0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI_B0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TRGSTS ========================================================= */ + #define R_TFU_TRGSTS_BSYF_Pos (0UL) /*!< BSYF (Bit 0) */ + #define R_TFU_TRGSTS_BSYF_Msk (0x1UL) /*!< BSYF (Bitfield-Mask: 0x01) */ + #define R_TFU_TRGSTS_ERRF_Pos (1UL) /*!< ERRF (Bit 1) */ + #define R_TFU_TRGSTS_ERRF_Msk (0x2UL) /*!< ERRF (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDT0 ========================================================= */ + #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */ + #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SCDT1 ========================================================= */ + #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */ + #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT0 ========================================================= */ + #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */ + #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT1 ========================================================= */ + #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */ + #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R7FA6T2BD_H */ + +/** @} */ /* End of group R7FA6T2BD */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 00000000..8676f738 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,117 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas + * @{ + */ + +/** @addtogroup RA + * @{ + */ + +#ifndef RA_H + #define RA_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include "cmsis_compiler.h" + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is provided in bsp_arm_exceptions.h. Vectors generated by the FSP Configuration tool are in vector_data.h */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if __ARM_ARCH_7EM__ + #define RENESAS_CORTEX_M4 + #elif __ARM_ARCH_6M__ + #define RENESAS_CORTEX_M0PLUS + #elif __ARM_ARCH_8M_BASE__ + #define RENESAS_CORTEX_M23 + #elif __ARM_ARCH_8M_MAIN__ + #define RENESAS_CORTEX_M33 + #else + #warning Unsupported Architecture + #endif + + #if BSP_MCU_GROUP_RA2A1 + #include "R7FA2A1AB.h" + #elif BSP_MCU_GROUP_RA2E1 + #include "R7FA2E1A9.h" + #elif BSP_MCU_GROUP_RA2E2 + #include "R7FA2E2A7.h" + #elif BSP_MCU_GROUP_RA2L1 + #include "R7FA2L1AB.h" + #elif BSP_MCU_GROUP_RA4E1 + #include "R7FA4E10D.h" + #elif BSP_MCU_GROUP_RA4M1 + #include "R7FA4M1AB.h" + #elif BSP_MCU_GROUP_RA4M2 + #include "R7FA4M2AD.h" + #elif BSP_MCU_GROUP_RA4M3 + #include "R7FA4M3AF.h" + #elif BSP_MCU_GROUP_RA4W1 + #include "R7FA4W1AD.h" + #elif BSP_MCU_GROUP_RA6E1 + #include "R7FA6E10F.h" + #elif BSP_MCU_GROUP_RA6M1 + #include "R7FA6M1AD.h" + #elif BSP_MCU_GROUP_RA6M2 + #include "R7FA6M2AF.h" + #elif BSP_MCU_GROUP_RA6M3 + #include "R7FA6M3AH.h" + #elif BSP_MCU_GROUP_RA6M4 + #include "R7FA6M4AF.h" + #elif BSP_MCU_GROUP_RA6M5 + #include "R7FA6M5BH.h" + #elif BSP_MCU_GROUP_RA6T1 + #include "R7FA6T1AD.h" + #elif BSP_MCU_GROUP_RA6T2 + #include "R7FA6T2BD.h" + #else + #warning Unsupported MCU + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RA_H */ + +/** @} */ /* End of group RA */ + +/** @} */ /* End of group Renesas */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 00000000..af1e2842 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h new file mode 100644 index 00000000..faece4f0 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_ARM_EXCEPTIONS_H + #define BSP_ARM_EXCEPTIONS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* This list includes only Arm standard exceptions. Renesas interrupts are defined in vector_data.h. */ +typedef enum IRQn +{ + Reset_IRQn = -15, /* 1 Reset Vector invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* 2 Non maskable Interrupt cannot be stopped or preempted */ + HardFault_IRQn = -13, /* 3 Hard Fault all classes of Fault */ + MemoryManagement_IRQn = -12, /* 4 Memory Management MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /* 5 Bus Fault Pre-Fetch-, Memory Access, other address/memory Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */ + SVCall_IRQn = -5, /* 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSV_IRQn = -2, /* 14 Pendable request for system service */ + SysTick_IRQn = -1, /* 15 System Tick Timer */ +} IRQn_Type; + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 00000000..14ac005a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,354 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The following definitions are macros instead of enums because the values are used in preprocessor conditionals. */ +/* Must match SCKCR.CKSEL values. */ +#define BSP_CLOCKS_SOURCE_CLOCK_HOCO (0) // The high speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MOCO (1) // The middle speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_LOCO (2) // The low speed on chip oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC (3) // The main oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK (4) // The subclock oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_PLL (5) // The PLL oscillator. +#define BSP_CLOCKS_SOURCE_CLOCK_PLL2 (6) // The PLL2 oscillator. + +/* PLLs are not supported in the following scenarios: + * - When using low voltage mode + * - When using an MCU that does not have a PLL + * - When the PLL only accepts the main oscillator as a source and XTAL is not used + */ +#if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ + !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) + #define BSP_PRV_PLL_SUPPORTED (1) + #if BSP_FEATURE_CGC_HAS_PLL2 + #define BSP_PRV_PLL2_SUPPORTED (1) + #else + #define BSP_PRV_PLL2_SUPPORTED (0) + #endif +#else + #define BSP_PRV_PLL_SUPPORTED (0) + #define BSP_PRV_PLL2_SUPPORTED (0) +#endif + +/* The ICLK frequency at startup is used to determine the ideal operating mode to set after startup. The PLL frequency + * calculated here is also used to initialize the g_clock_freq array. */ +#if BSP_PRV_PLL_SUPPORTED + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) && (BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif +#if BSP_PRV_PLL2_SUPPORTED + #if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL2_SOURCE + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #else + #define BSP_PRV_PLL2_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #endif +#endif + +/* Frequencies of clocks with fixed freqencies. */ +#define BSP_LOCO_FREQ_HZ (32768U) // LOCO frequency is fixed at 32768 Hz +#define BSP_SUBCLOCK_FREQ_HZ (32768U) // Subclock frequency is 32768 Hz +#define BSP_MOCO_FREQ_HZ (8000000U) // MOCO frequency is fixed at 8 MHz + +#if BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_HOCO_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_MOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_LOCO == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_LOCO_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_SUBCLOCK_FREQ_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_CLOCK_SOURCE + #define BSP_STARTUP_SOURCE_CLOCK_HZ (BSP_CFG_XTAL_HZ) +#elif BSP_CLOCKS_SOURCE_CLOCK_PLL == BSP_CFG_CLOCK_SOURCE + #if (1U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #elif BSP_CLOCKS_SOURCE_CLOCK_HOCO == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_HOCO_HZ) + #endif + #define BSP_STARTUP_SOURCE_CLOCK_HZ (((BSP_PRV_PLL_SOURCE_FREQ_HZ * (BSP_CFG_PLL_MUL + 1U)) >> 1) / \ + (BSP_CFG_PLL_DIV + 1U)) + #elif (2U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #define BSP_PRV_PLL_SOURCE_FREQ_HZ (BSP_CFG_XTAL_HZ) + #define BSP_STARTUP_SOURCE_CLOCK_HZ ((BSP_PRV_PLL_SOURCE_FREQ_HZ * ((BSP_CFG_PLL_MUL + 1U) >> 1)) >> \ + (BSP_CFG_PLL_DIV)) + #endif +#endif + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ +#define BSP_STARTUP_ICLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_ICLK_DIV) +#define BSP_STARTUP_PCLKA_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKA_DIV) +#define BSP_STARTUP_PCLKB_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKB_DIV) +#define BSP_STARTUP_PCLKC_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKC_DIV) +#define BSP_STARTUP_PCLKD_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_PCLKD_DIV) +#define BSP_STARTUP_BCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_BCLK_DIV) +#define BSP_STARTUP_FCLK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ >> BSP_CFG_FCLK_DIV) + +/* System clock divider options. */ +#define BSP_CLOCKS_SYS_CLOCK_DIV_1 (0) // System clock divided by 1. +#define BSP_CLOCKS_SYS_CLOCK_DIV_2 (1) // System clock divided by 2. +#define BSP_CLOCKS_SYS_CLOCK_DIV_4 (2) // System clock divided by 4. +#define BSP_CLOCKS_SYS_CLOCK_DIV_8 (3) // System clock divided by 8. +#define BSP_CLOCKS_SYS_CLOCK_DIV_16 (4) // System clock divided by 16. +#define BSP_CLOCKS_SYS_CLOCK_DIV_32 (5) // System clock divided by 32. +#define BSP_CLOCKS_SYS_CLOCK_DIV_64 (6) // System clock divided by 64. +#define BSP_CLOCKS_SYS_CLOCK_DIV_128 (7) // System clock divided by 128 (available for CLKOUT only). + +/* USB clock divider options. */ +#define BSP_CLOCKS_USB_CLOCK_DIV_3 (2) // Divide USB source clock by 3 +#define BSP_CLOCKS_USB_CLOCK_DIV_4 (3) // Divide USB source clock by 4 +#define BSP_CLOCKS_USB_CLOCK_DIV_5 (4) // Divide USB source clock by 5 + +/* OCTA clock divider options. */ +#define BSP_CLOCKS_OCTA_CLOCK_DIV_1 (0) // Divide OCTA source clock by 1 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_2 (1) // Divide OCTA source clock by 2 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_4 (2) // Divide OCTA source clock by 4 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_6 (3) // Divide OCTA source clock by 6 +#define BSP_CLOCKS_OCTA_CLOCK_DIV_8 (4) // Divide OCTA source clock by 8 + +/* CANFD clock divider options. */ +#define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 + +/* SCISPI clock divider options. */ +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_1 (0) // Divide SCISPI source clock by 1 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_2 (1) // Divide SCISPI source clock by 2 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_4 (2) // Divide SCISPI source clock by 4 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_6 (3) // Divide SCISPI source clock by 6 +#define BSP_CLOCKS_SCISPI_CLOCK_DIV_8 (4) // Divide SCISPI source clock by 8 + +/* GPT clock divider options. */ +#define BSP_CLOCKS_GPT_CLOCK_DIV_1 (0) // Divide GPT source clock by 1 +#define BSP_CLOCKS_GPT_CLOCK_DIV_2 (1) // Divide GPT source clock by 2 +#define BSP_CLOCKS_GPT_CLOCK_DIV_4 (2) // Divide GPT source clock by 4 +#define BSP_CLOCKS_GPT_CLOCK_DIV_6 (3) // Divide GPT source clock by 6 +#define BSP_CLOCKS_GPT_CLOCK_DIV_8 (4) // Divide GPT source clock by 8 + +/* IIC clock divider options. */ +#define BSP_CLOCKS_IIC_CLOCK_DIV_1 (0) // Divide IIC source clock by 1 +#define BSP_CLOCKS_IIC_CLOCK_DIV_2 (1) // Divide IIC source clock by 2 +#define BSP_CLOCKS_IIC_CLOCK_DIV_4 (2) // Divide IIC source clock by 4 +#define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 +#define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 + +/* PLL divider options. */ +#define BSP_CLOCKS_PLL_DIV_1 (0) +#define BSP_CLOCKS_PLL_DIV_2 (1) +#define BSP_CLOCKS_PLL_DIV_3 (2) +#define BSP_CLOCKS_PLL_DIV_4 (2) + +/* PLL multiplier options. */ +#define BSP_CLOCKS_PLL_MUL_8_0 (0xF) +#define BSP_CLOCKS_PLL_MUL_9_0 (0x11) +#define BSP_CLOCKS_PLL_MUL_10_0 (0x13) +#define BSP_CLOCKS_PLL_MUL_10_5 (0x14) +#define BSP_CLOCKS_PLL_MUL_11_0 (0x15) +#define BSP_CLOCKS_PLL_MUL_11_5 (0x16) +#define BSP_CLOCKS_PLL_MUL_12_0 (0x17) +#define BSP_CLOCKS_PLL_MUL_12_5 (0x18) +#define BSP_CLOCKS_PLL_MUL_13_0 (0x19) +#define BSP_CLOCKS_PLL_MUL_13_5 (0x1A) +#define BSP_CLOCKS_PLL_MUL_14_0 (0x1B) +#define BSP_CLOCKS_PLL_MUL_14_5 (0x1c) +#define BSP_CLOCKS_PLL_MUL_15_0 (0x1d) +#define BSP_CLOCKS_PLL_MUL_15_5 (0x1e) +#define BSP_CLOCKS_PLL_MUL_16_0 (0x1f) +#define BSP_CLOCKS_PLL_MUL_16_5 (0x20) +#define BSP_CLOCKS_PLL_MUL_17_0 (0x21) +#define BSP_CLOCKS_PLL_MUL_17_5 (0x22) +#define BSP_CLOCKS_PLL_MUL_18_0 (0x23) +#define BSP_CLOCKS_PLL_MUL_18_5 (0x24) +#define BSP_CLOCKS_PLL_MUL_19_0 (0x25) +#define BSP_CLOCKS_PLL_MUL_19_5 (0x26) +#define BSP_CLOCKS_PLL_MUL_20_0 (0x27) +#define BSP_CLOCKS_PLL_MUL_20_5 (0x28) +#define BSP_CLOCKS_PLL_MUL_21_0 (0x29) +#define BSP_CLOCKS_PLL_MUL_21_5 (0x2A) +#define BSP_CLOCKS_PLL_MUL_22_0 (0x2B) +#define BSP_CLOCKS_PLL_MUL_22_5 (0x2c) +#define BSP_CLOCKS_PLL_MUL_23_0 (0x2d) +#define BSP_CLOCKS_PLL_MUL_23_5 (0x2e) +#define BSP_CLOCKS_PLL_MUL_24_0 (0x2f) +#define BSP_CLOCKS_PLL_MUL_24_5 (0x30) +#define BSP_CLOCKS_PLL_MUL_25_0 (0x31) +#define BSP_CLOCKS_PLL_MUL_25_5 (0x32) +#define BSP_CLOCKS_PLL_MUL_26_0 (0x33) +#define BSP_CLOCKS_PLL_MUL_26_5 (0x34) +#define BSP_CLOCKS_PLL_MUL_27_0 (0x35) +#define BSP_CLOCKS_PLL_MUL_27_5 (0x36) +#define BSP_CLOCKS_PLL_MUL_28_0 (0x37) +#define BSP_CLOCKS_PLL_MUL_28_5 (0x38) +#define BSP_CLOCKS_PLL_MUL_29_0 (0x39) +#define BSP_CLOCKS_PLL_MUL_29_5 (0x3A) +#define BSP_CLOCKS_PLL_MUL_30_0 (0x3B) +#define BSP_CLOCKS_PLL_MUL_31_0 (0x3D) + +/* Configuration option used to disable clock output. */ +#define BSP_CLOCKS_CLOCK_DISABLED (0xFFU) + +/* HOCO cycles per microsecond. */ +#define BSP_PRV_HOCO_CYCLES_PER_US (BSP_HOCO_HZ / 1000000U) + +/* Maximum number of delay cycles required to ensure 1 us passes between setting PLLCCR and clearing PLLCR. */ +#if BSP_HOCO_HZ < 48000000U + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (BSP_PRV_HOCO_CYCLES_PER_US) +#else + #define BSP_PRV_MAX_HOCO_CYCLES_PER_US (48U) +#endif + +/* Create a mask of valid bits in SCKDIVCR. */ +#define BSP_PRV_SCKDIVCR_ICLK_MASK (7U << 24) +#if BSP_FEATURE_CGC_HAS_PCLKD + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (7U << 0) +#else + #define BSP_PRV_SCKDIVCR_PCLKD_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKC + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (7U << 4) +#else + #define BSP_PRV_SCKDIVCR_PCLKC_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKB + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (7U << 8) +#else + #define BSP_PRV_SCKDIVCR_PCLKB_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_PCLKA + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (7U << 12) +#else + #define BSP_PRV_SCKDIVCR_PCLKA_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_BCLK || BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB + #define BSP_PRV_SCKDIVCR_BCLK_MASK (7U << 16) +#else + #define BSP_PRV_SCKDIVCR_BCLK_MASK (0U) +#endif +#if BSP_FEATURE_CGC_HAS_FCLK + #define BSP_PRV_SCKDIVCR_FCLK_MASK (7U << 28) +#else + #define BSP_PRV_SCKDIVCR_FCLK_MASK (0U) +#endif +#define BSP_PRV_SCKDIVCR_MASK ((((((BSP_PRV_SCKDIVCR_ICLK_MASK | BSP_PRV_SCKDIVCR_PCLKD_MASK) | \ + BSP_PRV_SCKDIVCR_PCLKC_MASK) | BSP_PRV_SCKDIVCR_PCLKB_MASK) | \ + BSP_PRV_SCKDIVCR_PCLKA_MASK) | \ + BSP_PRV_SCKDIVCR_BCLK_MASK) | BSP_PRV_SCKDIVCR_FCLK_MASK) + +/* FLL is only used when enabled, present and the subclock is populated. */ +#if BSP_FEATURE_CGC_HAS_FLL && BSP_CFG_FLL_ENABLE && BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_PRV_HOCO_USE_FLL (1) + #ifndef BSP_PRV_FLL_STABILIZATION_TIME_US + #define BSP_PRV_FLL_STABILIZATION_TIME_US (1800) + #endif +#else + #define BSP_PRV_HOCO_USE_FLL (0) + #define BSP_PRV_FLL_STABILIZATION_TIME_US (0) +#endif + +/* Operating power control modes. */ +#define BSP_PRV_OPERATING_MODE_HIGH_SPEED (0U) // Should match OPCCR OPCM high speed +#define BSP_PRV_OPERATING_MODE_MIDDLE_SPEED (1U) // Should match OPCCR OPCM middle speed +#define BSP_PRV_OPERATING_MODE_LOW_VOLTAGE (2U) // Should match OPCCR OPCM low voltage +#define BSP_PRV_OPERATING_MODE_LOW_SPEED (3U) // Should match OPCCR OPCM low speed +#define BSP_PRV_OPERATING_MODE_SUBOSC_SPEED (4U) // Can be any value not otherwise used + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +typedef struct +{ + uint32_t pll_freq; +} bsp_clock_update_callback_args_t; + + #if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_clock_update_callback_t)(bsp_clock_update_callback_args_t * + p_callback_args); + #endif + +#endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +#if BSP_TZ_NONSECURE_BUILD +void bsp_clock_freq_var_init(void); // Used internally by BSP + +#endif + +#if BSP_TZ_SECURE_BUILD +void r_bsp_clock_update_callback_set(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/* Used internally by CGC */ + +#if !BSP_CFG_USE_LOW_VOLTAGE_MODE +void bsp_prv_operating_mode_set(uint8_t operating_mode); + +#endif + +#if BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED +uint32_t bsp_prv_power_change_mstp_set(void); +void bsp_prv_power_change_mstp_clear(uint32_t mstp_clear_bitmask); + +#endif + +void bsp_prv_prepare_pll(uint32_t pll_freq_hz); +void bsp_prv_clock_set(uint32_t clock, uint32_t sckdivcr); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_common.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 00000000..e836a255 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,415 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Version of this module's code and API. */ + +#if 1 == BSP_CFG_RTOS /* ThreadX */ + #include "tx_user.h" + #if defined(TX_ENABLE_EVENT_TRACE) || defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) + #define FSP_CONTEXT_SAVE tx_isr_start((uint32_t) R_FSP_CurrentIrqGet()); + #define FSP_CONTEXT_RESTORE tx_isr_end((uint32_t) R_FSP_CurrentIrqGet()); + #else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE + #endif +#else + #define FSP_CONTEXT_SAVE + #define FSP_CONTEXT_RESTORE +#endif + +/** Macro that can be defined in order to enable logging in FSP modules. */ +#ifndef FSP_LOG_PRINT + #define FSP_LOG_PRINT(X) +#endif + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +/**************************************************************** + * + * This check is performed to select suitable ASM API with respect to core + * + * The macros __CORE__ , __ARM7EM__ and __ARM_ARCH_8M_BASE__ are undefined for GCC, but defined(__IAR_SYSTEMS_ICC__) is false for GCC, so + * the left half of the || expression evaluates to false for GCC regardless of the values of these macros. */ + +#if (defined(__IAR_SYSTEMS_ICC__) && ((__CORE__ == __ARM7EM__) || (__CORE__ == __ARM_ARCH_8M_BASE__))) || \ + defined(__ARM_ARCH_7EM__) // CM4 + #ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) + #endif +#else // CM23 + #ifdef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #undef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #endif + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uint32_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state for different architectures. */ +#if (0 == BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION) + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_PRIMASK + #define FSP_CRITICAL_SECTION_SET_STATE __set_PRIMASK + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET (1U) +#else + #define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_BASEPRI + #define FSP_CRITICAL_SECTION_SET_STATE __set_BASEPRI + #define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + (8U - __NVIC_PRIO_BITS))) +#endif + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions, used as an offset from XPSR value for the IRQn_Type macro. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (16U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* Private definition used in R_FSP_SystemClockHzGet. Each bitfield in SCKDIVCR is 3 bits wide. */ +#define FSP_PRIV_SCKDIVCR_DIV_MASK (7) + +/* Use the secure registers for secure projects and flat projects. */ +#if !BSP_TZ_NONSECURE_BUILD && BSP_FEATURE_TZ_HAS_TRUSTZONE + #define FSP_PRIV_TZ_USE_SECURE_REGS (1) +#else + #define FSP_PRIV_TZ_USE_SECURE_REGS (0) +#endif + +/* Put certain BSP variables in uninitialized RAM when initializing BSP early. */ +#if BSP_CFG_EARLY_INIT + #define BSP_SECTION_EARLY_INIT BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT) +#else + #define BSP_SECTION_EARLY_INIT +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/* Private enum used in R_FSP_SystemClockHzGet. Maps clock name to base bit in SCKDIVCR. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_PCLKD = 0, + FSP_PRIV_CLOCK_PCLKC = 4, + FSP_PRIV_CLOCK_PCLKB = 8, + FSP_PRIV_CLOCK_PCLKA = 12, + FSP_PRIV_CLOCK_BCLK = 16, + FSP_PRIV_CLOCK_ICLK = 24, + FSP_PRIV_CLOCK_FCLK = 28, +} fsp_priv_clock_t; + +/* Private enum used in R_FSP_SciSpiClockHzGe. Maps clock name to base bit in SCISPICKCR. */ +typedef enum e_fsp_priv_source_clock +{ + FSP_PRIV_CLOCK_HOCO = 0, ///< The high speed on chip oscillator + FSP_PRIV_CLOCK_MOCO = 1, ///< The middle speed on chip oscillator + FSP_PRIV_CLOCK_LOCO = 2, ///< The low speed on chip oscillator + FSP_PRIV_CLOCK_MAIN_OSC = 3, ///< The main oscillator + FSP_PRIV_CLOCK_SUBCLOCK = 4, ///< The subclock oscillator + FSP_PRIV_CLOCK_PLL = 5, ///< The PLL oscillator + FSP_PRIV_CLOCK_PLL2 = 6, ///< The PLL2 oscillator +} fsp_priv_source_clock_t; + +typedef struct st_bsp_unique_id +{ + union + { + uint32_t unique_id_words[4]; + uint8_t unique_id_bytes[16]; + }; +} bsp_unique_id_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +uint32_t R_BSP_SourceClockHzGet(fsp_priv_source_clock_t clock); + +/*********************************************************************************************************************** + * Global variables (defined in other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + xPSR_Type xpsr_value; + xpsr_value.w = __get_xPSR(); + + return (IRQn_Type) (xpsr_value.b.ISR - FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS); +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + uint32_t sckdivcr = R_SYSTEM->SCKDIVCR; + uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRIV_SCKDIVCR_DIV_MASK; + uint32_t clock_div = (sckdivcr >> clock) & FSP_PRIV_SCKDIVCR_DIV_MASK; + + return (SystemCoreClock << iclk_div) >> clock_div; +} + +#if BSP_FEATURE_BSP_HAS_SCISPI_CLOCK + +/*******************************************************************************************************************//** + * Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR). + * + * @return Clock Divider + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr) +{ + if (2U >= ckdivcr) + { + /* clock_div: + * - Clock Divided by 1: 0 + * - Clock Divided by 2: 1 + * - Clock Divided by 4: 2 + */ + return 1 << ckdivcr; + } + else if (3U == ckdivcr) + { + /* Clock Divided by 6 */ + return 6U; + } + else if (4U == ckdivcr) + { + /* Clock Divided by 8 */ + return 8U; + } + else if (5U == ckdivcr) + { + /* Clock Divided by 3 */ + return 3U; + } + + /* Clock Divided by 5 */ + return 5U; +} + +/*******************************************************************************************************************//** + * Gets the frequency of a SCI/SPI clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SciSpiClockHzGet (void) +{ + uint32_t scispidivcr = R_SYSTEM->SCISPICKDIVCR; + uint32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRIV_SCKDIVCR_DIV_MASK); + fsp_priv_source_clock_t scispicksel = (fsp_priv_source_clock_t) R_SYSTEM->SCISPICKCR_b.SCISPICKSEL; + + return R_BSP_SourceClockHzGet(scispicksel) / clock_div; +} + +#endif + +/*******************************************************************************************************************//** + * Get unique ID for this device. + * + * @return A pointer to the unique identifier structure + **********************************************************************************************************************/ +__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void) +{ + return (bsp_unique_id_t *) BSP_FEATURE_BSP_UNIQUE_ID_POINTER; +} + +/*******************************************************************************************************************//** + * Disables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheDisable (void) +{ +#if BSP_FEATURE_BSP_FLASH_CACHE + R_FCACHE->FCACHEE = 0U; +#endif + +#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE + + /* Disable the C-Cache. */ + R_CACHE->CCACTL = 0U; +#endif +} + +/*******************************************************************************************************************//** + * Enables the flash cache. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_FlashCacheEnable (void) +{ +#if BSP_FEATURE_BSP_FLASH_CACHE + + /* Invalidate the flash cache and wait until it is invalidated. (See section 55.3.2.2 "Operation" of the Flash Cache + * in the RA6M3 manual R01UH0878EJ0100). */ + R_FCACHE->FCACHEIV = 1U; + FSP_HARDWARE_REGISTER_WAIT(R_FCACHE->FCACHEIV, 0U); + + /* Enable flash cache. */ + R_FCACHE->FCACHEE = 1U; +#endif + +#if BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE + + /* Configure the C-Cache line size. */ + R_CACHE->CCALCF = BSP_CFG_C_CACHE_LINE_SIZE; + + /* Enable the C-Cache. */ + R_CACHE->CCACTL = 1U; +#endif +} + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 00000000..2cadeb19 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,112 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H + #define BSP_COMPILER_SUPPORT_H + + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include "arm_cmse.h" + #endif + + #ifdef __cplusplus +extern "C" { + #endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP "HEAP" + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #endif + + #define BSP_SECTION_STACK BSP_UNINIT_SECTION_PREFIX ".stack" + #define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" + #define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" + #define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" + #define BSP_SECTION_ROM_REGISTERS ".rom_registers" + #define BSP_SECTION_ID_CODE ".id_code" + +/* Compiler neutral macros. */ + #define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + + #define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + + #define BSP_PACKED __attribute__((aligned(1))) // DEPRECATED + + #define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ + #define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * TrustZone definitions + **********************************************************************************************************************/ + #if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) && !defined(__clang_analyzer__) + #if defined(__ICCARM__) /* IAR compiler */ + #define BSP_CMSE_NONSECURE_CALL __cmse_nonsecure_call + #define BSP_CMSE_NONSECURE_ENTRY __cmse_nonsecure_entry + #else + #define BSP_CMSE_NONSECURE_CALL __attribute__((cmse_nonsecure_call)) + #define BSP_CMSE_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) + #endif + #else + #define BSP_CMSE_NONSECURE_CALL + #define BSP_CMSE_NONSECURE_ENTRY + #endif + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_delay.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 00000000..fd5d85ac --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,75 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "bsp_compiler_support.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #define BSP_DELAY_LOOP_CYCLES (4) +#endif + +/* Calculates the number of delay loops to pass to bsp_prv_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since bsp_prv_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h new file mode 100644 index 00000000..83ec718d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_group_irq.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_GROUP_IRQ_H +#define BSP_GROUP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Which interrupts can have callbacks registered. */ +typedef enum e_bsp_grp_irq +{ + BSP_GRP_IRQ_IWDT_ERROR = 0, ///< IWDT underflow/refresh error has occurred + BSP_GRP_IRQ_WDT_ERROR = 1, ///< WDT underflow/refresh error has occurred + BSP_GRP_IRQ_LVD1 = 2, ///< Voltage monitoring 1 interrupt + BSP_GRP_IRQ_LVD2 = 3, ///< Voltage monitoring 2 interrupt + BSP_GRP_IRQ_VBATT = 4, ///< VBATT monitor interrupt + BSP_GRP_IRQ_OSC_STOP_DETECT = 6, ///< Oscillation stop is detected + BSP_GRP_IRQ_NMI_PIN = 7, ///< NMI Pin interrupt + BSP_GRP_IRQ_RAM_PARITY = 8, ///< RAM Parity Error + BSP_GRP_IRQ_RAM_ECC = 9, ///< RAM ECC Error + BSP_GRP_IRQ_MPU_BUS_SLAVE = 10, ///< MPU Bus Slave Error + BSP_GRP_IRQ_MPU_BUS_MASTER = 11, ///< MPU Bus Master Error + BSP_GRP_IRQ_MPU_STACK = 12, ///< MPU Stack Error + BSP_GRP_IRQ_TRUSTZONE = 13, ///< MPU Stack Error + BSP_GRP_IRQ_CACHE_PARITY = 15, ///< MPU Stack Error +} bsp_grp_irq_t; + +/* Callback type. */ +typedef void (* bsp_grp_irq_cb_t)(bsp_grp_irq_t irq); + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_group_interrupt_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_guard.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_guard.h new file mode 100644 index 00000000..74d32482 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_guard.h @@ -0,0 +1,46 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_GUARD_H +#define BSP_GUARD_H + +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#if BSP_TZ_SECURE_BUILD || BSP_TZ_NONSECURE_BUILD +BSP_CMSE_NONSECURE_ENTRY fsp_err_t R_BSP_ClockUpdateCallbackSet(bsp_clock_update_callback_t p_callback, + bsp_clock_update_callback_args_t * p_callback_memory); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_io.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 00000000..98d8dff6 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,470 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write access to port pins. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_PFS_PSEL_OFFSET (24) +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PWPR_B0WI_OFFSET (7U) +#define BSP_IO_PWPR_PFSWE_OFFSET (6U) +#define BSP_IO_PFS_PDR_OUTPUT (4U) +#define BSP_IO_PRV_PIN_WRITE_MASK (0xFFFE3FFE) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin_t +{ + BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7 + BSP_IO_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8 + BSP_IO_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9 + BSP_IO_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10 + BSP_IO_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11 + BSP_IO_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12 + BSP_IO_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13 + BSP_IO_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14 + BSP_IO_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15 + + BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7 + BSP_IO_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8 + BSP_IO_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9 + BSP_IO_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10 + BSP_IO_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11 + BSP_IO_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12 + BSP_IO_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13 + BSP_IO_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14 + BSP_IO_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15 + + BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7 + BSP_IO_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8 + BSP_IO_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9 + BSP_IO_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10 + BSP_IO_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11 + BSP_IO_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12 + BSP_IO_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13 + BSP_IO_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14 + BSP_IO_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15 + + BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7 + BSP_IO_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8 + BSP_IO_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9 + BSP_IO_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10 + BSP_IO_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11 + BSP_IO_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12 + BSP_IO_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13 + BSP_IO_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14 + BSP_IO_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15 + + BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7 + BSP_IO_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8 + BSP_IO_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9 + BSP_IO_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10 + BSP_IO_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11 + BSP_IO_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12 + BSP_IO_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13 + BSP_IO_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14 + BSP_IO_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15 + + BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7 + BSP_IO_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8 + BSP_IO_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9 + BSP_IO_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10 + BSP_IO_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11 + BSP_IO_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12 + BSP_IO_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13 + BSP_IO_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14 + BSP_IO_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15 + + BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7 + BSP_IO_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8 + BSP_IO_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9 + BSP_IO_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10 + BSP_IO_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11 + BSP_IO_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12 + BSP_IO_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13 + BSP_IO_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14 + BSP_IO_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15 + + BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7 + BSP_IO_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8 + BSP_IO_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9 + BSP_IO_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10 + BSP_IO_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11 + BSP_IO_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12 + BSP_IO_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13 + BSP_IO_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14 + BSP_IO_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15 + + BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7 + BSP_IO_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8 + BSP_IO_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9 + BSP_IO_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10 + BSP_IO_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11 + BSP_IO_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12 + BSP_IO_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13 + BSP_IO_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14 + BSP_IO_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15 + + BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7 + BSP_IO_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8 + BSP_IO_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9 + BSP_IO_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10 + BSP_IO_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11 + BSP_IO_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12 + BSP_IO_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13 + BSP_IO_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14 + BSP_IO_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15 + + BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7 + BSP_IO_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8 + BSP_IO_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9 + BSP_IO_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10 + BSP_IO_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11 + BSP_IO_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12 + BSP_IO_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13 + BSP_IO_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14 + BSP_IO_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15 + + BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7 + BSP_IO_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8 + BSP_IO_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9 + BSP_IO_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10 + BSP_IO_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11 + BSP_IO_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12 + BSP_IO_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13 + BSP_IO_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14 + BSP_IO_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15 + + BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1 + BSP_IO_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2 + BSP_IO_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3 + BSP_IO_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4 + BSP_IO_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5 + BSP_IO_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6 + BSP_IO_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7 + BSP_IO_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8 + BSP_IO_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9 + BSP_IO_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10 + BSP_IO_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11 + BSP_IO_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12 + BSP_IO_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13 + BSP_IO_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14 + BSP_IO_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15 + + BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2 + BSP_IO_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3 + BSP_IO_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4 + BSP_IO_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5 + BSP_IO_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6 + BSP_IO_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7 + BSP_IO_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8 + BSP_IO_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9 + BSP_IO_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10 + BSP_IO_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11 + BSP_IO_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12 + BSP_IO_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13 + BSP_IO_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14 + BSP_IO_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15 + + BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1 + BSP_IO_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2 + BSP_IO_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3 + BSP_IO_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4 + BSP_IO_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5 + BSP_IO_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6 + BSP_IO_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7 + BSP_IO_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8 + BSP_IO_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9 + BSP_IO_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10 + BSP_IO_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11 + BSP_IO_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12 + BSP_IO_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13 + BSP_IO_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14 + BSP_IO_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15 +} bsp_io_port_pin_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_pfswe_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Read the current input level of the pin. + * + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin) +{ + /* Read pin level. */ + return R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS_b.PIDR; +} + +/*******************************************************************************************************************//** + * Set a pin to output and set the output level to the level provided. If PFS protection is enabled, disable PFS + * protection using R_BSP_PinAccessEnable() before calling this function. + * + * @param[in] pin The pin + * @param[in] level The level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level) +{ + /* Clear PMR, ASEL, ISEL and PODR bits. */ + uint32_t pfs_bits = R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS; + pfs_bits &= BSP_IO_PRV_PIN_WRITE_MASK; + + /* Set output level and pin direction to output. */ + uint32_t lvl = ((uint32_t) level | pfs_bits); + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = (BSP_IO_PFS_PDR_OUTPUT | lvl); +} + +/*******************************************************************************************************************//** + * Configure a pin. If PFS protection is enabled, disable PFS protection using R_BSP_PinAccessEnable() before calling + * this function. + * + * @param[in] pin The pin + * @param[in] cfg Configuration for the pin (PmnPFS register setting) + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinCfg (bsp_io_port_pin_t pin, uint32_t cfg) +{ + /* Configure a pin. */ + R_PFS->PORT[pin >> 8].PIN[pin & BSP_IO_PRV_8BIT_MASK].PmnPFS = cfg; +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD + R_PMISC->PWPRS = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled + #endif + } + + /** Increment the protect counter */ + g_protect_pfswe_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PFS_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_pfswe_counter) + { + /* Decrement the protect counter */ + g_protect_pfswe_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_pfswe_counter) + { + #if BSP_TZ_SECURE_BUILD + R_PMISC->PWPRS = 0; ///< Clear PFSWE bit - writing to PFSWE bit enabled + R_PMISC->PWPRS = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFS register enabled + #else + R_PMISC->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled + R_PMISC->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled + #endif + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_irq.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 00000000..8b06295b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,219 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit + * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_ICU->IELSR_b[irq].IR = 0U; +} + +/*******************************************************************************************************************//** + * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + /* Clear the IR bit in the selected IELSR register. */ + R_BSP_IrqStatusClear(irq); + + /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ to configure. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + /* The following statement is used in place of NVIC_SetPriority to avoid including a branch for system exceptions + * every time a priority is configured in the NVIC. */ +#if (4U == __CORTEX_M) + NVIC->IP[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (33 == __CORTEX_M) + NVIC->IPR[((uint32_t) irq)] = (uint8_t) ((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX); +#elif (23 == __CORTEX_M) + NVIC->IPR[_IP_IDX(irq)] = ((uint32_t) (NVIC->IPR[_IP_IDX(irq)] & ~((uint32_t) UINT8_MAX << _BIT_SHIFT(irq))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) UINT8_MAX) << _BIT_SHIFT(irq))); +#else + NVIC_SetPriority(irq, priority); +#endif + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the NVIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex + * Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions + * every time an interrupt is enabled in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); +} + +/*******************************************************************************************************************//** + * Clears pending interrupts in both ICU and NVIC, then enables the interrupt. + * + * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed + * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the ICU and NVIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the IRQ in the NVIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the NVIC. + * + * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system + * exceptions every time an interrupt is cleared in the NVIC. */ + uint32_t _irq = (uint32_t) irq; + NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL)); + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority NVIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + * + * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq]; +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 00000000..b878e3ca --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; + +typedef enum e_bsp_clocks_octaclk_div +{ + BSP_CLOCKS_OCTACLK_DIV_1 = 0, ///< Divide OCTA source clock by 1 + BSP_CLOCKS_OCTACLK_DIV_2, ///< Divide OCTA source clock by 2 + BSP_CLOCKS_OCTACLK_DIV_4, ///< Divide OCTA source clock by 4 + BSP_CLOCKS_OCTACLK_DIV_6, ///< Divide OCTA source clock by 6 + BSP_CLOCKS_OCTACLK_DIV_8 ///< Divide OCTA source clock by 8 +} bsp_clocks_octaclk_div_t; + +typedef enum e_bsp_clocks_source +{ + BSP_CLOCKS_CLOCK_HOCO = 0, ///< The high speed on chip oscillator. + BSP_CLOCKS_CLOCK_MOCO, ///< The middle speed on chip oscillator. + BSP_CLOCKS_CLOCK_LOCO, ///< The low speed on chip oscillator. + BSP_CLOCKS_CLOCK_MAIN_OSC, ///< The main oscillator. + BSP_CLOCKS_CLOCK_SUBCLOCK, ///< The subclock oscillator. + BSP_CLOCKS_CLOCK_PLL, ///< The PLL oscillator. + BSP_CLOCKS_CLOCK_PLL2, ///< The PLL2 oscillator. +} bsp_clocks_source_t; + +typedef struct st_bsp_octaclk_settings +{ + bsp_clocks_source_t source_clock; ///< OCTACLK source clock + bsp_clocks_octaclk_div_t divider; ///< OCTACLK divider +} bsp_octaclk_settings_t; + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +fsp_err_t R_BSP_GroupIrqWrite(bsp_grp_irq_t irq, void (* p_callback)(bsp_grp_irq_t irq)); +void R_BSP_OctaclkUpdate(bsp_octaclk_settings_t * p_octaclk_setting); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 00000000..e275e9d8 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,190 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#if BSP_FEATURE_TZ_HAS_TRUSTZONE + +/* MSTPCRA is located in R_MSTP for Star devices. */ + #define R_BSP_MSTPCRA (R_MSTP->MSTPCRA) +#else + +/* MSTPCRA is located in R_SYSTEM for W1D and Peaks devices. */ + #define R_BSP_MSTPCRA (R_SYSTEM->MSTPCRA) +#endif + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ + +#if 0U == BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH >= \ + channel) ? (1U << 5U) : (1U << 6U)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U)); +#else + #if (2U == BSP_FEATURE_ELC_VERSION) + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << 31); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) (1U << (3U - channel)); + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #else + #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); + #define BSP_MSTP_REG_FSP_IP_AGT(channel) *((3U >= channel) ? &R_MSTP->MSTPCRD : &R_MSTP->MSTPCRE) + #define BSP_MSTP_BIT_FSP_IP_AGT(channel) ((3U >= \ + channel) ? (1U << (3U - channel)) : (1U << (15U - (channel - 4U)))); + #define BSP_MSTP_REG_FSP_IP_KEY(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << (4U - channel)); + #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #endif +#endif + +#define BSP_MSTP_REG_FSP_IP_DMAC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DMAC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_DTC(channel) R_BSP_MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_DTC(channel) (1U << (22U)); +#define BSP_MSTP_REG_FSP_IP_CAN(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CAN(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CEC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_CEC(channel) (1U << (3U)); +#define BSP_MSTP_REG_FSP_IP_IRDA(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IRDA(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_QSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_QSPI(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBFS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBFS(channel) (1U << (11U - channel)); +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_EPTPC(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_EPTPC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ETHER(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_ETHER(channel) (1U << (15U - channel)); +#define BSP_MSTP_REG_FSP_IP_OSPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_OSPI(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SPI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) (1U << (19U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCI(channel) R_MSTP->MSTPCRB +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_CAC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CAC(channel) (1U << (0U - channel)); +#define BSP_MSTP_REG_FSP_IP_CRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) (1U << (1U - channel)); +#define BSP_MSTP_REG_FSP_IP_PDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_PDC(channel) (1U << (2U - channel)); +#define BSP_MSTP_REG_FSP_IP_CTSU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CTSU(channel) (1U << (3U - channel)); +#define BSP_MSTP_REG_FSP_IP_SLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_GLCDC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_GLCDC(channel) (1U << (4U - channel)); +#define BSP_MSTP_REG_FSP_IP_JPEG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_JPEG(channel) (1U << (5U - channel)); +#define BSP_MSTP_REG_FSP_IP_DRW(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DRW(channel) (1U << (6U - channel)); +#define BSP_MSTP_REG_FSP_IP_SSI(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SSI(channel) (1U << (8U - channel)); +#define BSP_MSTP_REG_FSP_IP_SRC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SRC(channel) (1U << (9U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDHIMMC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SDHIMMC(channel) (1U << (12U - channel)); +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (13U - channel)); +#define BSP_MSTP_REG_FSP_IP_ELC(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ELC(channel) (1U << (14U - channel)); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (20U - channel)); +#define BSP_MSTP_REG_FSP_IP_IIRFA(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_IIRFA(channel) (1U << (21U - channel)); +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (27U)); +#define BSP_MSTP_REG_FSP_IP_TRNG(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TRNG(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_SCE(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_SCE(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_AES(channel) R_MSTP->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_AES(channel) (1U << (31U - channel)); +#define BSP_MSTP_REG_FSP_IP_ADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ADC(channel) (1U << (16U - channel)); +#define BSP_MSTP_REG_FSP_IP_SDADC(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_SDADC(channel) (1U << (17U - channel)); +#if (BSP_FEATURE_DAC_MAX_CHANNELS > 2U) + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U - channel)); +#else + #define BSP_MSTP_REG_FSP_IP_DAC8(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC8(channel) (1U << (19U)); + #define BSP_MSTP_REG_FSP_IP_DAC(channel) R_MSTP->MSTPCRD + #define BSP_MSTP_BIT_FSP_IP_DAC(channel) (1U << (20U)); +#endif +#define BSP_MSTP_REG_FSP_IP_TSN(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSN(channel) (1U << (22U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPHS(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPHS(channel) (1U << (28U - channel)); +#define BSP_MSTP_REG_FSP_IP_ACMPLP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_ACMPLP(channel) (1U << 29U); +#define BSP_MSTP_REG_FSP_IP_OPAMP(channel) R_MSTP->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_OPAMP(channel) (1U << (31U - channel)); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 00000000..66943f7d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,74 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to operating modes, low power consumption, and battery backup + * function. */ + BSP_REG_PROTECT_OM_LPC_BATT, + + /** Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, + * LVD2CR1, LVD2SR. */ + BSP_REG_PROTECT_LVD, + + /** Enables writing to the registers related to the security function. */ + BSP_REG_PROTECT_SAR, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_security.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_security.h new file mode 100644 index 00000000..294f1c6d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_security.h @@ -0,0 +1,47 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_SECURITY_H +#define BSP_SECURITY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void R_BSP_NonSecureEnter(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_tfu.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_tfu.h new file mode 100644 index 00000000..3ead89c3 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -0,0 +1,228 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RENESAS_TFU +#define RENESAS_TFU + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Mathematical Functions includes. */ +#ifdef __cplusplus + #include +#else + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935f + +#ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + +/* No form of inline is available, it happens only when -std=c89, gnu89 and + * above are OK */ + #warning \ + "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" + #else + #ifdef __GNUC_GNU_INLINE__ + +/* gnu89 semantics of inline and extern inline are essentially the exact + * opposite of those in C99 */ + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif + #endif +#elif __ICCARM__ + #define BSP_TFU_INLINE +#else + #error "Compiler not supported!" +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calculates sine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Sine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __sinf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + return R_TFU->SCDT1; +} + +/*******************************************************************************************************************//** + * Calculates cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __cosf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read cos from R_TFU->SCDT1 */ + return R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates sine and cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * @param[out] sin Sine value of an angle. + * @param[out] cos Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + *sin = R_TFU->SCDT1; + + /* Read sin from R_TFU->SCDT1 */ + *cos = R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-Axis cordinate value. + * @param[in] x_cord X-Axis cordinate value. + * + * @retval Arc tangent for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) +{ + /* Set X-cordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-cordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + return R_TFU->ATDT1; +} + +/*******************************************************************************************************************//** + * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * + * @retval Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * @param[out] atan2 Arc tangent for given values. + * @param[out] hypot Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + *atan2 = R_TFU->ATDT1; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +#if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* RENESAS_TFU */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h new file mode 100644 index 00000000..1c4f1d54 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_elc.h @@ -0,0 +1,348 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/******************************************************************************************************************* + * @addtogroup BSP_MCU_RA6M5 + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_ra6m5 +{ + ELC_EVENT_NONE = (0), // Link disabled + ELC_EVENT_ICU_IRQ0 = (0x001), // External pin interrupt 0 + ELC_EVENT_ICU_IRQ1 = (0x002), // External pin interrupt 1 + ELC_EVENT_ICU_IRQ2 = (0x003), // External pin interrupt 2 + ELC_EVENT_ICU_IRQ3 = (0x004), // External pin interrupt 3 + ELC_EVENT_ICU_IRQ4 = (0x005), // External pin interrupt 4 + ELC_EVENT_ICU_IRQ5 = (0x006), // External pin interrupt 5 + ELC_EVENT_ICU_IRQ6 = (0x007), // External pin interrupt 6 + ELC_EVENT_ICU_IRQ7 = (0x008), // External pin interrupt 7 + ELC_EVENT_ICU_IRQ8 = (0x009), // External pin interrupt 8 + ELC_EVENT_ICU_IRQ9 = (0x00A), // External pin interrupt 9 + ELC_EVENT_ICU_IRQ10 = (0x00B), // External pin interrupt 10 + ELC_EVENT_ICU_IRQ11 = (0x00C), // External pin interrupt 11 + ELC_EVENT_ICU_IRQ12 = (0x00D), // External pin interrupt 12 + ELC_EVENT_ICU_IRQ13 = (0x00E), // External pin interrupt 13 + ELC_EVENT_ICU_IRQ14 = (0x00F), // External pin interrupt 14 + ELC_EVENT_ICU_IRQ15 = (0x010), // External pin interrupt 15 + ELC_EVENT_DMAC0_INT = (0x020), // DMAC transfer end 0 + ELC_EVENT_DMAC1_INT = (0x021), // DMAC transfer end 1 + ELC_EVENT_DMAC2_INT = (0x022), // DMAC transfer end 2 + ELC_EVENT_DMAC3_INT = (0x023), // DMAC transfer end 3 + ELC_EVENT_DMAC4_INT = (0x024), // DMAC transfer end 4 + ELC_EVENT_DMAC5_INT = (0x025), // DMAC transfer end 5 + ELC_EVENT_DMAC6_INT = (0x026), // DMAC transfer end 6 + ELC_EVENT_DMAC7_INT = (0x027), // DMAC transfer end 7 + ELC_EVENT_DTC_COMPLETE = (0x029), // DTC transfer complete + ELC_EVENT_DTC_END = (0x02A), // DTC transfer end + ELC_EVENT_DMA_TRANSERR = (0x02B), // DTC transfer error + ELC_EVENT_ICU_SNOOZE_CANCEL = (0x02D), // Canceling from Snooze mode + ELC_EVENT_FCU_FIFERR = (0x030), // Flash access error interrupt + ELC_EVENT_FCU_FRDYI = (0x031), // Flash ready interrupt + ELC_EVENT_LVD_LVD1 = (0x038), // Voltage monitor 1 interrupt + ELC_EVENT_LVD_LVD2 = (0x039), // Voltage monitor 2 interrupt + ELC_EVENT_CGC_MOSC_STOP = (0x03B), // Main Clock oscillation stop + ELC_EVENT_LPM_SNOOZE_REQUEST = (0x03C), // Snooze entry + ELC_EVENT_AGT0_INT = (0x040), // AGT interrupt + ELC_EVENT_AGT0_COMPARE_A = (0x041), // Compare match A + ELC_EVENT_AGT0_COMPARE_B = (0x042), // Compare match B + ELC_EVENT_AGT1_INT = (0x043), // AGT interrupt + ELC_EVENT_AGT1_COMPARE_A = (0x044), // Compare match A + ELC_EVENT_AGT1_COMPARE_B = (0x045), // Compare match B + ELC_EVENT_AGT2_INT = (0x046), // AGT interrupt + ELC_EVENT_AGT2_COMPARE_A = (0x047), // Compare match A + ELC_EVENT_AGT2_COMPARE_B = (0x048), // Compare match B + ELC_EVENT_AGT3_INT = (0x049), // AGT interrupt + ELC_EVENT_AGT3_COMPARE_A = (0x04A), // Compare match A + ELC_EVENT_AGT3_COMPARE_B = (0x04B), // Compare match B + ELC_EVENT_AGT4_INT = (0x04C), // AGT interrupt + ELC_EVENT_AGT4_COMPARE_A = (0x04D), // Compare match A + ELC_EVENT_AGT4_COMPARE_B = (0x04E), // Compare match B + ELC_EVENT_AGT5_INT = (0x04F), // AGT interrupt + ELC_EVENT_AGT5_COMPARE_A = (0x050), // Compare match A + ELC_EVENT_AGT5_COMPARE_B = (0x051), // Compare match B + ELC_EVENT_IWDT_UNDERFLOW = (0x052), // IWDT underflow + ELC_EVENT_WDT_UNDERFLOW = (0x053), // WDT underflow + ELC_EVENT_RTC_ALARM = (0x054), // Alarm interrupt + ELC_EVENT_RTC_PERIOD = (0x055), // Periodic interrupt + ELC_EVENT_RTC_CARRY = (0x056), // Carry interrupt + ELC_EVENT_CAN_RXF = (0x059), // Global recieve FIFO interrupt + ELC_EVENT_CAN_GLERR = (0x05A), // Global error + ELC_EVENT_CAN_DMAREQ0 = (0x05B), // DMA 0 request + ELC_EVENT_CAN_DMAREQ1 = (0x05C), // DMA 1 request + ELC_EVENT_CAN_DMAREQ2 = (0x05D), // DMA 2 request + ELC_EVENT_CAN_DMAREQ3 = (0x05E), // DMA 3 request + ELC_EVENT_CAN_DMAREQ4 = (0x05F), // DMA 4 request + ELC_EVENT_CAN_DMAREQ5 = (0x060), // DMA 5 request + ELC_EVENT_CAN_DMAREQ6 = (0x061), // DMA 6 request + ELC_EVENT_CAN_DMAREQ7 = (0x062), // DMA 7 request + ELC_EVENT_CAN0_TX = (0x063), // Transmit interrupt + ELC_EVENT_CAN0_CHERR = (0x064), // Channel error + ELC_EVENT_CAN0_COMFRX = (0x065), // Common FIFO recieve interrupt + ELC_EVENT_CAN0_CF_DMAREQ = (0x066), // Channel DMA request + ELC_EVENT_CAN1_TX = (0x067), // Transmit interrupt + ELC_EVENT_CAN1_CHERR = (0x068), // Channel error + ELC_EVENT_CAN1_COMFRX = (0x069), // Common FIFO recieve + ELC_EVENT_CAN1_CF_DMAREQ = (0x06A), // Channel DMA request + ELC_EVENT_USBFS_FIFO_0 = (0x06B), // DMA transfer request 0 + ELC_EVENT_USBFS_FIFO_1 = (0x06C), // DMA transfer request 1 + ELC_EVENT_USBFS_INT = (0x06D), // USBFS interrupt + ELC_EVENT_USBFS_RESUME = (0x06E), // USBFS resume interrupt + ELC_EVENT_IIC0_RXI = (0x073), // Receive data full + ELC_EVENT_IIC0_TXI = (0x074), // Transmit data empty + ELC_EVENT_IIC0_TEI = (0x075), // Transmit end + ELC_EVENT_IIC0_ERI = (0x076), // Transfer error + ELC_EVENT_IIC0_WUI = (0x077), // Slave address match + ELC_EVENT_IIC1_RXI = (0x078), // Receive data full + ELC_EVENT_IIC1_TXI = (0x079), // Transmit data empty + ELC_EVENT_IIC1_TEI = (0x07A), // Transmit end + ELC_EVENT_IIC1_ERI = (0x07B), // Transfer error + ELC_EVENT_IIC2_RXI = (0x07D), // Receive data full + ELC_EVENT_IIC2_TXI = (0x07E), // Transmit data empty + ELC_EVENT_IIC2_TEI = (0x07F), // Transmit end + ELC_EVENT_IIC2_ERI = (0x080), // Transfer error + ELC_EVENT_SDHIMMC0_ACCS = (0x082), // Card access + ELC_EVENT_SDHIMMC0_SDIO = (0x083), // SDIO access + ELC_EVENT_SDHIMMC0_CARD = (0x084), // Card detect + ELC_EVENT_SDHIMMC0_DMA_REQ = (0x085), // DMA transfer request + ELC_EVENT_SSI0_TXI = (0x08A), // Transmit data empty + ELC_EVENT_SSI0_RXI = (0x08B), // Receive data full + ELC_EVENT_SSI0_INT = (0x08D), // Error interrupt + ELC_EVENT_CTSU_WRITE = (0x09A), // Write request interrupt + ELC_EVENT_CTSU_READ = (0x09B), // Measurement data transfer request interrupt + ELC_EVENT_CTSU_END = (0x09C), // Measurement end interrupt + ELC_EVENT_CAC_FREQUENCY_ERROR = (0x09E), // Frequency error interrupt + ELC_EVENT_CAC_MEASUREMENT_END = (0x09F), // Measurement end interrupt + ELC_EVENT_CAC_OVERFLOW = (0x0A0), // Overflow interrupt + ELC_EVENT_CEC_INTDA = (0x0AB), // Data interrupt + ELC_EVENT_CEC_INTCE = (0x0AC), // Communication complete interrupt + ELC_EVENT_CEC_INTERR = (0x0AD), // Error interrupt + ELC_EVENT_IOPORT_EVENT_1 = (0x0B1), // Port 1 event + ELC_EVENT_IOPORT_EVENT_2 = (0x0B2), // Port 2 event + ELC_EVENT_IOPORT_EVENT_3 = (0x0B3), // Port 3 event + ELC_EVENT_IOPORT_EVENT_4 = (0x0B4), // Port 4 event + ELC_EVENT_ELC_SOFTWARE_EVENT_0 = (0x0B5), // Software event 0 + ELC_EVENT_ELC_SOFTWARE_EVENT_1 = (0x0B6), // Software event 1 + ELC_EVENT_POEG0_EVENT = (0x0B7), // Port Output disable interrupt A + ELC_EVENT_POEG1_EVENT = (0x0B8), // Port Output disable interrupt B + ELC_EVENT_POEG2_EVENT = (0x0B9), // Port Output disable interrupt C + ELC_EVENT_POEG3_EVENT = (0x0BA), // Port Output disable interrupt D + ELC_EVENT_GPT0_CAPTURE_COMPARE_A = (0x0C0), // Compare match A + ELC_EVENT_GPT0_CAPTURE_COMPARE_B = (0x0C1), // Compare match B + ELC_EVENT_GPT0_COMPARE_C = (0x0C2), // Compare match C + ELC_EVENT_GPT0_COMPARE_D = (0x0C3), // Compare match D + ELC_EVENT_GPT0_COMPARE_E = (0x0C4), // Compare match E + ELC_EVENT_GPT0_COMPARE_F = (0x0C5), // Compare match F + ELC_EVENT_GPT0_COUNTER_OVERFLOW = (0x0C6), // Overflow + ELC_EVENT_GPT0_COUNTER_UNDERFLOW = (0x0C7), // Underflow + ELC_EVENT_GPT0_PC = (0x0C8), // Period count function finish + ELC_EVENT_GPT1_CAPTURE_COMPARE_A = (0x0C9), // Compare match A + ELC_EVENT_GPT1_CAPTURE_COMPARE_B = (0x0CA), // Compare match B + ELC_EVENT_GPT1_COMPARE_C = (0x0CB), // Compare match C + ELC_EVENT_GPT1_COMPARE_D = (0x0CC), // Compare match D + ELC_EVENT_GPT1_COMPARE_E = (0x0CD), // Compare match E + ELC_EVENT_GPT1_COMPARE_F = (0x0CE), // Compare match F + ELC_EVENT_GPT1_COUNTER_OVERFLOW = (0x0CF), // Overflow + ELC_EVENT_GPT1_COUNTER_UNDERFLOW = (0x0D0), // Underflow + ELC_EVENT_GPT1_PC = (0x0D1), // Period count function finish + ELC_EVENT_GPT2_CAPTURE_COMPARE_A = (0x0D2), // Compare match A + ELC_EVENT_GPT2_CAPTURE_COMPARE_B = (0x0D3), // Compare match B + ELC_EVENT_GPT2_COMPARE_C = (0x0D4), // Compare match C + ELC_EVENT_GPT2_COMPARE_D = (0x0D5), // Compare match D + ELC_EVENT_GPT2_COMPARE_E = (0x0D6), // Compare match E + ELC_EVENT_GPT2_COMPARE_F = (0x0D7), // Compare match F + ELC_EVENT_GPT2_COUNTER_OVERFLOW = (0x0D8), // Overflow + ELC_EVENT_GPT2_COUNTER_UNDERFLOW = (0x0D9), // Underflow + ELC_EVENT_GPT3_CAPTURE_COMPARE_A = (0x0DB), // Compare match A + ELC_EVENT_GPT3_CAPTURE_COMPARE_B = (0x0DC), // Compare match B + ELC_EVENT_GPT3_COMPARE_C = (0x0DD), // Compare match C + ELC_EVENT_GPT3_COMPARE_D = (0x0DE), // Compare match D + ELC_EVENT_GPT3_COMPARE_E = (0x0DF), // Compare match E + ELC_EVENT_GPT3_COMPARE_F = (0x0E0), // Compare match F + ELC_EVENT_GPT3_COUNTER_OVERFLOW = (0x0E1), // Overflow + ELC_EVENT_GPT3_COUNTER_UNDERFLOW = (0x0E2), // Underflow + ELC_EVENT_GPT4_CAPTURE_COMPARE_A = (0x0E4), // Compare match A + ELC_EVENT_GPT4_CAPTURE_COMPARE_B = (0x0E5), // Compare match B + ELC_EVENT_GPT4_COMPARE_C = (0x0E6), // Compare match C + ELC_EVENT_GPT4_COMPARE_D = (0x0E7), // Compare match D + ELC_EVENT_GPT4_COMPARE_E = (0x0E8), // Compare match E + ELC_EVENT_GPT4_COMPARE_F = (0x0E9), // Compare match F + ELC_EVENT_GPT4_COUNTER_OVERFLOW = (0x0EA), // Overflow + ELC_EVENT_GPT4_COUNTER_UNDERFLOW = (0x0EB), // Underflow + ELC_EVENT_GPT4_PC = (0x0EC), // Period count function finish + ELC_EVENT_GPT5_CAPTURE_COMPARE_A = (0x0ED), // Compare match A + ELC_EVENT_GPT5_CAPTURE_COMPARE_B = (0x0EE), // Compare match B + ELC_EVENT_GPT5_COMPARE_C = (0x0EF), // Compare match C + ELC_EVENT_GPT5_COMPARE_D = (0x0F0), // Compare match D + ELC_EVENT_GPT5_COMPARE_E = (0x0F1), // Compare match E + ELC_EVENT_GPT5_COMPARE_F = (0x0F2), // Compare match F + ELC_EVENT_GPT5_COUNTER_OVERFLOW = (0x0F3), // Overflow + ELC_EVENT_GPT5_COUNTER_UNDERFLOW = (0x0F4), // Underflow + ELC_EVENT_GPT5_PC = (0x0F5), // Period count function finish + ELC_EVENT_GPT6_CAPTURE_COMPARE_A = (0x0F6), // Compare match A + ELC_EVENT_GPT6_CAPTURE_COMPARE_B = (0x0F7), // Compare match B + ELC_EVENT_GPT6_COMPARE_C = (0x0F8), // Compare match C + ELC_EVENT_GPT6_COMPARE_D = (0x0F9), // Compare match D + ELC_EVENT_GPT6_COMPARE_E = (0x0FA), // Compare match E + ELC_EVENT_GPT6_COMPARE_F = (0x0FB), // Compare match F + ELC_EVENT_GPT6_COUNTER_OVERFLOW = (0x0FC), // Overflow + ELC_EVENT_GPT6_COUNTER_UNDERFLOW = (0x0FD), // Underflow + ELC_EVENT_GPT6_PC = (0x0FE), // Period count function finish + ELC_EVENT_GPT7_CAPTURE_COMPARE_A = (0x0FF), // Compare match A + ELC_EVENT_GPT7_CAPTURE_COMPARE_B = (0x100), // Compare match B + ELC_EVENT_GPT7_COMPARE_C = (0x101), // Compare match C + ELC_EVENT_GPT7_COMPARE_D = (0x102), // Compare match D + ELC_EVENT_GPT7_COMPARE_E = (0x103), // Compare match E + ELC_EVENT_GPT7_COMPARE_F = (0x104), // Compare match F + ELC_EVENT_GPT7_COUNTER_OVERFLOW = (0x105), // Overflow + ELC_EVENT_GPT7_COUNTER_UNDERFLOW = (0x106), // Underflow + ELC_EVENT_GPT8_CAPTURE_COMPARE_A = (0x108), // Compare match A + ELC_EVENT_GPT8_CAPTURE_COMPARE_B = (0x109), // Compare match B + ELC_EVENT_GPT8_COMPARE_C = (0x10A), // Compare match C + ELC_EVENT_GPT8_COMPARE_D = (0x10B), // Compare match D + ELC_EVENT_GPT8_COMPARE_E = (0x10C), // Compare match E + ELC_EVENT_GPT8_COMPARE_F = (0x10D), // Compare match F + ELC_EVENT_GPT8_COUNTER_OVERFLOW = (0x10E), // Overflow + ELC_EVENT_GPT8_COUNTER_UNDERFLOW = (0x10F), // Underflow + ELC_EVENT_GPT9_CAPTURE_COMPARE_A = (0x111), // Compare match A + ELC_EVENT_GPT9_CAPTURE_COMPARE_B = (0x112), // Compare match B + ELC_EVENT_GPT9_COMPARE_C = (0x113), // Compare match C + ELC_EVENT_GPT9_COMPARE_D = (0x114), // Compare match D + ELC_EVENT_GPT9_COMPARE_E = (0x115), // Compare match E + ELC_EVENT_GPT9_COMPARE_F = (0x116), // Compare match F + ELC_EVENT_GPT9_COUNTER_OVERFLOW = (0x117), // Overflow + ELC_EVENT_GPT9_COUNTER_UNDERFLOW = (0x118), // Underflow + ELC_EVENT_OPS_UVW_EDGE = (0x150), // UVW edge event + ELC_EVENT_ADC0_SCAN_END = (0x160), // A/D scan end interrupt + ELC_EVENT_ADC0_SCAN_END_B = (0x161), // A/D scan end interrupt for group B + ELC_EVENT_ADC0_WINDOW_A = (0x162), // Window A Compare match + ELC_EVENT_ADC0_WINDOW_B = (0x163), // Window B Compare match + ELC_EVENT_ADC0_COMPARE_MATCH = (0x164), // Compare match + ELC_EVENT_ADC0_COMPARE_MISMATCH = (0x165), // Compare mismatch + ELC_EVENT_ADC1_SCAN_END = (0x166), // A/D scan end interrupt + ELC_EVENT_ADC1_SCAN_END_B = (0x167), // A/D scan end interrupt for group B + ELC_EVENT_ADC1_WINDOW_A = (0x168), // Window A Compare match + ELC_EVENT_ADC1_WINDOW_B = (0x169), // Window B Compare match + ELC_EVENT_ADC1_COMPARE_MATCH = (0x16A), // Compare match + ELC_EVENT_ADC1_COMPARE_MISMATCH = (0x16B), // Compare mismatch + ELC_EVENT_EDMAC0_EINT = (0x16F), // EDMAC 0 interrupt + ELC_EVENT_USBHS_FIFO_0 = (0x17D), // DMA transfer request 0 + ELC_EVENT_USBHS_FIFO_1 = (0x17E), // DMA transfer request 1 + ELC_EVENT_USBHS_USB_INT_RESUME = (0x17F), // USBHS interrupt + ELC_EVENT_SCI0_RXI = (0x180), // Receive data full + ELC_EVENT_SCI0_TXI = (0x181), // Transmit data empty + ELC_EVENT_SCI0_TEI = (0x182), // Transmit end + ELC_EVENT_SCI0_ERI = (0x183), // Receive error + ELC_EVENT_SCI0_AM = (0x184), // Address match event + ELC_EVENT_SCI0_RXI_OR_ERI = (0x185), // Receive data full/Receive + ELC_EVENT_SCI1_RXI = (0x186), // Received data full + ELC_EVENT_SCI1_TXI = (0x187), // Transmit data empty + ELC_EVENT_SCI1_TEI = (0x188), // Transmit end + ELC_EVENT_SCI1_ERI = (0x189), // Receive error + ELC_EVENT_SCI2_RXI = (0x18C), // Received data full + ELC_EVENT_SCI2_TXI = (0x18D), // Transmit data empty + ELC_EVENT_SCI2_TEI = (0x18E), // Transmit end + ELC_EVENT_SCI2_ERI = (0x18F), // Receive error + ELC_EVENT_SCI3_RXI = (0x192), // Received data full + ELC_EVENT_SCI3_TXI = (0x193), // Transmit data empty + ELC_EVENT_SCI3_TEI = (0x194), // Transmit end + ELC_EVENT_SCI3_ERI = (0x195), // Receive error + ELC_EVENT_SCI3_AM = (0x196), // Address match event + ELC_EVENT_SCI4_RXI = (0x198), // Received data full + ELC_EVENT_SCI4_TXI = (0x199), // Transmit data empty + ELC_EVENT_SCI4_TEI = (0x19A), // Transmit end + ELC_EVENT_SCI4_ERI = (0x19B), // Receive error + ELC_EVENT_SCI4_AM = (0x19C), // Address match event + ELC_EVENT_SCI5_RXI = (0x19E), // Received data full + ELC_EVENT_SCI5_TXI = (0x19F), // Transmit data empty + ELC_EVENT_SCI5_TEI = (0x1A0), // Transmit end + ELC_EVENT_SCI5_ERI = (0x1A1), // Receive error + ELC_EVENT_SCI5_AM = (0x1A2), // Address match event + ELC_EVENT_SCI6_RXI = (0x1A4), // Received data full + ELC_EVENT_SCI6_TXI = (0x1A5), // Transmit data empty + ELC_EVENT_SCI6_TEI = (0x1A6), // Transmit end + ELC_EVENT_SCI6_ERI = (0x1A7), // Receive error + ELC_EVENT_SCI6_AM = (0x1A8), // Address match event + ELC_EVENT_SCI7_RXI = (0x1AA), // Received data full + ELC_EVENT_SCI7_TXI = (0x1AB), // Transmit data empty + ELC_EVENT_SCI7_TEI = (0x1AC), // Transmit end + ELC_EVENT_SCI7_ERI = (0x1AD), // Receive error + ELC_EVENT_SCI7_AM = (0x1AE), // Address match event + ELC_EVENT_SCI8_RXI = (0x1B0), // Received data full + ELC_EVENT_SCI8_TXI = (0x1B1), // Transmit data empty + ELC_EVENT_SCI8_TEI = (0x1B2), // Transmit end + ELC_EVENT_SCI8_ERI = (0x1B3), // Receive error + ELC_EVENT_SCI8_AM = (0x1B4), // Address match event + ELC_EVENT_SCI9_RXI = (0x1B6), // Received data full + ELC_EVENT_SCI9_TXI = (0x1B7), // Transmit data empty + ELC_EVENT_SCI9_TEI = (0x1B8), // Transmit end + ELC_EVENT_SCI9_ERI = (0x1B9), // Receive error + ELC_EVENT_SCI9_AM = (0x1BA), // Address match event + ELC_EVENT_SCIX0_SCIX0 = (0x1BC), // SCI1 extended serial mode event 0 + ELC_EVENT_SCIX0_SCIX1 = (0x1BD), // SCI1 extended serial mode event 1 + ELC_EVENT_SCIX0_SCIX2 = (0x1BE), // SCI1 extended serial mode event 2 + ELC_EVENT_SCIX0_SCIX3 = (0x1BF), // SCI1 extended serial mode event 3 + ELC_EVENT_SCIX1_SCIX0 = (0x1C0), // SCI2 extended serial mode event 0 + ELC_EVENT_SCIX1_SCIX1 = (0x1C1), // SCI2 extended serial mode event 1 + ELC_EVENT_SCIX1_SCIX2 = (0x1C2), // SCI2 extended serial mode event 2 + ELC_EVENT_SCIX1_SCIX3 = (0x1C3), // SCI2 extended serial mode event 3 + ELC_EVENT_SPI0_RXI = (0x1C4), // Receive buffer full + ELC_EVENT_SPI0_TXI = (0x1C5), // Transmit buffer empty + ELC_EVENT_SPI0_IDLE = (0x1C6), // Idle + ELC_EVENT_SPI0_ERI = (0x1C7), // Error + ELC_EVENT_SPI0_TEI = (0x1C8), // Transmission complete event + ELC_EVENT_SPI1_RXI = (0x1C9), // Receive buffer full + ELC_EVENT_SPI1_TXI = (0x1CA), // Transmit buffer empty + ELC_EVENT_SPI1_IDLE = (0x1CB), // Idle + ELC_EVENT_SPI1_ERI = (0x1CC), // Error + ELC_EVENT_SPI1_TEI = (0x1CD), // Transmission complete event + ELC_CAN_AFLRAM0_ERI = (0x1CE), // ECC error + ELC_CAN_AFLRAM1_ERI = (0x1CF), // ECC error + ELC_CAN_MRAM_ERI = (0x1D0), // ECC error + ELC_EVENT_OSPI_INT = (0x1D9), // OSPI interrupt + ELC_EVENT_QSPI_INT = (0x1DA), // QSPI interrupt + ELC_EVENT_DOC_INT = (0x1DB), // Data operation circuit interrupt +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RA6M5) */ + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h new file mode 100644 index 00000000..17af584e --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -0,0 +1,353 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */ +#if (BSP_CFG_XTAL_HZ > (19999999)) + #define CGC_MAINCLOCK_DRIVE (0x00U) +#elif (BSP_CFG_XTAL_HZ > (15999999)) && (BSP_CFG_XTAL_HZ < (20000000)) + #define CGC_MAINCLOCK_DRIVE (0x01U) +#elif (BSP_CFG_XTAL_HZ > (7999999)) && (BSP_CFG_XTAL_HZ < (16000000)) + #define CGC_MAINCLOCK_DRIVE (0x02U) +#else + #define CGC_MAINCLOCK_DRIVE (0x03U) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPHS_VREF (0) // Feature not available on this MCU + +#define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0) // Feature not available on this MCU +#define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (0) // Feature not available on this MCU + +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_ADHVREFCNT (0U) +#define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) +#define BSP_FEATURE_ADC_HAS_PGA (0U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x0000FFFFU) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1U) // TSCDR is a 32-bit register on this MCU +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x37FF) // 0 to 10, 12, 13 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x1FFF0007) // 0 to 2, 16 to 28 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) +#define BSP_FEATURE_ADC_HAS_ADBUF (1U) + +#define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0U) +#define BSP_FEATURE_ADC_B_TSN_SLOPE (0U) +#define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0U) +#define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0U) + +#define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x3F) +#define BSP_FEATURE_AGT_MAX_CHANNEL_NUM (5) +#define BSP_FEATURE_AGT_HAS_AGTW (0U) + +#define BSP_FEATURE_BSP_FLASH_CACHE (1) +#define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0U) +#define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) +#define BSP_FEATURE_BSP_HAS_SCE5 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) +#define BSP_FEATURE_BSP_HAS_SP_MON (0U) +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock. +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) +#define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) +#define BSP_FEATURE_BSP_MPU_REGION0_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0U) // If MSTPRE is present than the setting is not valid. +#define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1U) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) +#define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_OSIS_PADDING (0U) +#define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) +#define BSP_FEATURE_BSP_RESET_TRNG (0U) +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (100000000U) // The maximum frequency allowed without having RAM wait state enabled in SRAMWTSC. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (50000000U) // The maximum frequency allowed without having one ROM wait cycle. +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (150000000U) // The maximum frequency allowed without having three ROM wait cycles (Set to zero if this is not an option). +#define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (100000000U) // The maximum frequency allowed without having two ROM wait cycles. +#define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0U) +#define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190U) +#define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (0U) // RA6M5 has CAN-FD + +#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_LITE (0U) +#define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_FLL (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (0U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (1U) // On the RA6M5 there is another PLL that can be used as a clock source for USB and OCTASPI. +#define BSP_FEATURE_CGC_HAS_SOSC (1U) +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC. +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (200000000U) +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x01U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0) + +#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) +#define BSP_FEATURE_CRYPTO_HAS_AES (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) +#define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC (1) +#define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_HASH (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA (1) +#define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (1) +#define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) +#define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) + +#define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) +#define BSP_FEATURE_CTSU_HAS_TXVSEL (1) +#define BSP_FEATURE_CTSU_VERSION (1) + +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU + +#define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) +#define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) +#define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) +#define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (1U) +#define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0U) +#define BSP_FEATURE_DAC_MAX_CHANNELS (2U) + +#define BSP_FEATURE_DOC_VERSION (1U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1U) + +#define BSP_FEATURE_DWT_CYCCNT (1U) // RA6M5 has Data Watchpoint Cycle Count Register + +#define BSP_FEATURE_ELC_PERIPHERAL_MASK (0x0007FFFFU) // Positions of event link set registers (ELSRs) available on this MCU +#define BSP_FEATURE_ELC_VERSION (1U) + +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_MAX_CHANNELS (1U) + +#define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x2000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x10000U) +#define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x8000U) +#define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (128U) +#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U) +#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U) +#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1) +#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1) +#define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000U) +#define BSP_FEATURE_FLASH_HP_VERSION (40U) +#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_LP_VERSION (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0) // Feature not available on this MCU +#define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0) // Feature not available on this MCU + +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x0FU) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFU) +#define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (BSP_FEATURE_GPT_VALID_CHANNEL_MASK) +#define BSP_FEATURE_GPT_HAS_GTCLKCR (0U) +#define BSP_FEATURE_GPT_ODC_VALID_CHANNEL_MASK (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MAX (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_ODC_FREQ_MIN (0U) // Feature not available on this MCU +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2U) +#define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0U) + +#define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0U) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (1U << 0U) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) +#define BSP_FEATURE_IIC_VERSION (1U) +#define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) +#define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) + +#define BSP_FEATURE_I3C_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_MAX_DEV_COUNT (0U) // Feature not available on this MCU +#define BSP_FEATURE_I3C_NTDTBP0_DEPTH (0U) // Feature not available on this MCU + +#define BSP_FEATURE_IOPORT_ELC_PORTS (0x001EU) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_KINT_HAS_MSTP (0U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY (0U) +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) +#define BSP_FEATURE_LPM_HAS_STCONR (0U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register + +#define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) +#define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) +#define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_99V) // 2.99V +#define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_2_85V) // 2.85V +#define BSP_FEATURE_LVD_STABILIZATION_TIME_US (10U) // Time in microseconds required for LVD to stabalize + +#define BSP_FEATURE_IOPORT_VERSION (1U) + +#define BSP_FEATURE_OPAMP_BASE_ADDRESS (0U) +#define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_HAS_SWITCHES (0U) +#define BSP_FEATURE_OPAMP_HAS_THIRD_CHANNEL (0U) +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0) // Feature not available on this MCU +#define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) +#define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) + +#define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000U) + +#define BSP_FEATURE_RTC_HAS_ROPSEL (0U) + +#define BSP_FEATURE_SCI_VERSION (1U) +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3F9U) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03F9U) // Channel 0, channel 3 to channel 9 have CSTPEN feature + +#define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (1U) +#define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (1U) +#define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x01U) +#define BSP_FEATURE_SDHI_CLOCK (FSP_PRIV_CLOCK_PCLKB) +#define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0U) // 1 (2^0) is minimum division supported + +#define BSP_FEATURE_SDRAM_START_ADDRESS (0x0U) + +#define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU + +#define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) +#define BSP_FEATURE_SPI_HAS_SPCR3 (1U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x3U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (2U) + +#define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x01U) + +#define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32U) +#define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1U) + +#define BSP_FEATURE_TFU_SPPORTED (0U) // Trigonometric Function Unit (TFU) not available on this MCU + +#define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0U) + +#define BSP_FEATURE_TZ_HAS_TRUSTZONE (1U) + +#define BSP_FEATURE_BSP_NUM_PMSAR (12U) + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h new file mode 100644 index 00000000..b724182b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RA6M5 RA6M5 + * @includedoc config_bsp_ra6m5_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RA6M5) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h new file mode 100644 index 00000000..1dcc4ed1 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/api/r_sce_api.h @@ -0,0 +1,2223 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup SCE_PROTECTED_API SCE Interface + * @brief Interface for Secure Crypto Engine (SCE) functions. + * + * @section SCE_PROTECTED_API_Summary Summary + * The SCE interface provides SCE functionality. + * + * The SCE interface can be implemented by: + * - @ref SCE_PROTECTED + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCE_API_H +#define R_SCE_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* For AES operation. */ +#define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (9U) +#define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (13U) +#define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES256_KEY_WORD_SIZE (8U) +#define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES256_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_BLOCK_BIT_SIZE (128U) +#define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) +#define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) + +/* For HMAC operation. */ +#define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (52U) +#define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (13U) +#define HW_SCE_HMAC_SHA256_KEY_BYTE_SIZE (32U) + +/* For RSA operation. */ +#define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +#define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) +#define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) +#define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) +#define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) +#define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) +#define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) +#define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) +#define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) +#define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (105U) +#define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (261U) +#define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (197U) + +#define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) +#define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ +#define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ +#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) +#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (1U) +#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (17U) +#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (13U) + +/* Key update. */ +#define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) + +/* For TLS. */ +#define SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (137U) +#define SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +#define SCE_INSTALL_KEY_RING_INDEX (0) /* 0-15 */ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Data lifecycle */ +typedef enum +{ + SCE_CM = 1, + SCE_SSD, + SCE_NSECSD, + SCE_DPL, + SCE_LCK_DBG, + SCE_LCK_BOOT, + SCE_RMA_REQ, + SCE_RMA_ACK, +} lifecycle_t; + +/** Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t * pdata; ///< pointer + uint32_t data_length; ///< data_length + uint32_t data_type; ///< data type +} sce_byte_data_t; + +/** RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; ///< byte data + +/** ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; ///< byte data + +/** AES wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_aes_wrapped_key +{ + uint32_t type; ///< key type + + /* AES128, AES256 are supported */ + uint32_t value[SCE_TLS_AES256_KEY_INDEX_WORD_SIZE]; ///< wrapped key value
@note The size of the "value" array and the definition name depends on the used SCE. See the header file for detail. +} sce_aes_wrapped_key_t; + +/** HMAC-SHA wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_hmac_sha_wrapped_key +{ + uint32_t type; ///< key type + + /* HMAC-SHA256 is supported */ + uint32_t value[SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; ///< wrapped key value +} sce_hmac_sha_wrapped_key_t; + +/** RSA 1024bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_public_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa1024_public_wrapped_key_t; + +/** RSA 1024bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 1024-bit private key n (plaintext) + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa1024_private_wrapped_key_t; + +/** RSA 2048bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa2048_public_wrapped_key_t; + +/** RSA 2048bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 2048-bit private key n (plaintext) + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa2048_private_wrapped_key_t; + +/** RSA 3072bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa3072_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 3072-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 3072-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa3072_public_wrapped_key_t; + +/** RSA 4096bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa4096_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; ///< key management information + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; ///< RSA 4096-bit public key n (plaintext) + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; ///< RSA 4096-bit public key e (plaintext) + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; ///< dummy + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; ///< key management information + } value; +} sce_rsa4096_public_wrapped_key_t; + +/** RSA 1024bit wrapped key pair structure. DO NOT MODIFY. */ +typedef struct sce_rsa1024_wrapped_pair_key +{ + sce_rsa1024_private_wrapped_key_t priv_key; ///< RSA 1024-bit private wrapped key + sce_rsa1024_public_wrapped_key_t pub_key; ///< RSA 1024-bit public wrapped key +} sce_rsa1024_wrapped_pair_key_t; + +/** RSA 2048bit wrapped key pair structure. DO NOT MODIFY. */ +typedef struct sce_rsa2048_wrapped_pair_key +{ + sce_rsa2048_private_wrapped_key_t priv_key; ///< RSA 2048-bit private wrapped key + sce_rsa2048_public_wrapped_key_t pub_key; ///< RSA 2048-bit public wrapped key +} sce_rsa2048_wrapped_pair_key_t; + +/** ECC P-192/224/256 public wrapped key data structure */ +typedef struct sce_ecc_public_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE]; ///< key management information + uint8_t key_q[HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE]; ///< ECC public key Q (plaintext) + } value; +} sce_ecc_public_wrapped_key_t; + +/** ECC P-192/224/256 private wrapped key data structure */ +typedef struct sce_ecc_private_wrapped_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; ///< wrapped key value +} sce_ecc_private_wrapped_key_t; + +/** ECC P-192/224/256 wrapped key pair structure */ +typedef struct sce_ecc_wrapped_pair_key +{ + sce_ecc_private_wrapped_key_t priv_key; ///< ECC private wrapped key + sce_ecc_public_wrapped_key_t pub_key; ///< ECC public wrapped key +} sce_ecc_wrapped_pair_key_t; + +/** ECDH wrapped key data structure */ +typedef struct sce_ecdh_wrapped_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; ///< wrapped key value +} sce_ecdh_wrapped_key_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_wrapped_key +{ + uint32_t type; + uint32_t value[SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_wrapped_key_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_wrapped_key +{ + uint32_t type; + uint32_t value[SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_wrapped_key_t; + +/** Update key ring index data structure. DO NOT MODIFY. */ +typedef struct sce_key_update_key +{ + uint32_t type; ///< key type + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; ///< wrapped key value
@note The size of the "value" array and the definition name depends on the used SCE. See the header file for detail. +} sce_key_update_key_t; + +/** The work area for AES. DO NOT MODIFY. */ +typedef struct sce_aes_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint32_t current_input_data_size; ///< text size under encryption / decryption + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; ///< reserved + uint8_t current_initial_vector[HW_SCE_AES_CBC_IV_BYTE_SIZE]; ///< current initialization vector used in CBC mode + uint8_t flag_call_init; ///< control flag of calling function +} sce_aes_handle_t; + +/** The work area for GCM. DO NOT MODIFY. */ +typedef struct sce_gcm_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; ///< AAD array less than the block long + uint32_t all_received_length; ///< entire length of text + uint32_t all_received_aad_length; ///< entire length of text + uint32_t buffering_length; ///< text array length less than the block long + uint32_t buffering_aad_length; ///< AAD array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function + uint8_t flag_update_input_data; ///< control flag of next input data +} sce_gcm_handle_t; + +/** The work area for CCM. DO NOT MODIFY. */ +typedef struct sce_ccm_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; ///< formatted data area + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; ///< counter of CTR mode + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< text array less than the block long + uint32_t all_received_length; ///< entire length of text + uint32_t buffering_length; ///< text array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_ccm_handle_t; + +/** The work area for CMAC. DO NOT MODIFY. */ +typedef struct sce_cmac_handle +{ + uint32_t id; ///< serial number of this handle + sce_aes_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; ///< message array less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_cmac_handle_t; + +/** The work area for SHA. DO NOT MODIFY. */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; ///< serial number of this handle + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; ///< message array length less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; ///< last hash value + uint8_t flag_call_init; ///< control flag of calling function +} sce_sha_md5_handle_t; + +/** The work area for HMAC-SHA. DO NOT MODIFY. */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; ///< serial number of this handle + sce_hmac_sha_wrapped_key_t wrapped_key; ///< wrapped key + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; ///< message array length less than the block long + uint32_t all_received_length; ///< entire length of message + uint32_t buffering_length; ///< message array length less than the block long + uint8_t flag_call_init; ///< control flag of calling function +} sce_hmac_sha_handle_t; + +/** The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; ///< serial number of this handle + uint32_t flag_use_key_id; ///< control frag that the key_id has already used or not + uint32_t key_id; ///< serial number of the wrapped key + uint32_t key_type; ///< key type + uint8_t flag_call_init; ///< control flag of calling function + uint8_t flag_call_make_public; ///< control flag of calling function + uint8_t flag_call_read_public; ///< control flag of calling function + uint8_t flag_call_shared_secret; ///< control flag of calling function +} sce_ecdh_handle_t; + +/** SCE Control block. Allocate an instance specific control block to pass into the API calls. + * @par Implemented as + * - sce_instance_ctrl_t + */ +typedef void sce_ctrl_t; + +/** User configuration structure, used in open function */ +typedef struct st_sce_cfg +{ + lifecycle_t lifecycle; ///< Data lifecycle +} sce_cfg_t; + +/** Functions implemented at the HAL layer will follow this API. */ +typedef struct st_sce_api +{ + /** Enables use of SCE functionality. + * @par Implemented as + * - @ref R_SCE_Open() + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration structure. + */ + + /***** TODO: Replace "struct st_sce_ctrl" to "void" *****/ + fsp_err_t (* open)(sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg); + + /** Stops supply of power to the SCE. + * @par Implemented as + * - @ref R_SCE_Close() + * + * @param[in] p_ctrl Pointer to control structure. + */ + fsp_err_t (* close)(sce_ctrl_t * const p_ctrl); + + /** Software reset to SCE. + * @par Implemented as + * - @ref R_SCE_SoftwareReset() + * + */ + fsp_err_t (* softwareReset)(void); + + /** Generates 4 words random number. + * @par Implemented as + * - @ref R_SCE_RandomNumberGenerate() + * + * @param[in,out] random Stores 4words (16 bytes) random data. + */ + fsp_err_t (* randomNumberGenerate)(uint32_t * random); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_WrappedKeyGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128_WrappedKeyGenerate)(sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_WrappedKeyGenerate() + * + * @param[in,out] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256_WrappedKeyGenerate)(sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, sce_aes_wrapped_key_t * wrapped_key); + + /** This API outputs 128-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_RFC3394KeyWrap() + * + * @param[in] master_key AES-128 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + */ + fsp_err_t (* AES128_RFC3394KeyWrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, uint32_t * rfc3394_wrapped_key); + + /** This API outputs 256-bit AES wrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_RFC3394KeyWrap() + * + * @param[in] master_key AES-256 key used for wrapping. + * @param[in] target_key_type Selects key to be wrapped. + * @param[in] target_key Key to be wrapped. + * @param[out] rfc3394_wrapped_key Wrapped key. + */ + fsp_err_t (* AES256_RFC3394KeyWrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, uint32_t * rfc3394_wrapped_key); + + /** This API outputs 128-bit AES unwrapped key. + * @par Implemented as + * - @ref R_SCE_AES128_RFC3394KeyUnwrap() + * + * @param[in] master_key AES-128 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + */ + fsp_err_t (* AES128_RFC3394KeyUnwrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, sce_aes_wrapped_key_t * target_key); + + /** This API outputs 256-bit AES unwrapped key. + * @par Implemented as + * - @ref R_SCE_AES256_RFC3394KeyUnwrap() + * + * @param[in] master_key AES-256 key used for unwrapping. + * @param[in] target_key_type Selects key to be unwrapped. + * @param[in] rfc3394_wrapped_key Wrapped key. + * @param[out] target_key Key to be unwrapped. + */ + fsp_err_t (* AES256_RFC3394KeyUnwrap)(sce_aes_wrapped_key_t * master_key, uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, sce_aes_wrapped_key_t * target_key); + + /** Initialize AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128ECB_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128ECB_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES128ECB_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128ECB_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128ECB_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES128ECB_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES128ECB_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256ECB_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256ECB_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256ECB encryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES256ECB_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256ECB_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256ECB_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256ECB decryption. + * @par Implemented as + * - @ref R_SCE_AES256ECB_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES256ECB_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES128CBC_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128CBC_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES128CBC_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES128CBC_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES128CBC_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES128CBC_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES128CBC_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES256CBC_EncryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in,out] plain_length plaintext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256CBC_EncryptUpdate)(sce_aes_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256CBC encryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_EncryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] cipher ciphertext data area (nothing ever written here) + * @param[in,out] cipher_length ciphertext data length (0 always written here) + */ + fsp_err_t (* AES256CBC_EncryptFinal)(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); + + /** Initialize AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptInit() + * + * @param[in,out] handle AES handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initial vector area (16byte) + */ + fsp_err_t (* AES256CBC_DecryptInit)(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); + + /** Update AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptUpdate() + * + * @param[in,out] handle AES handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in,out] cipher_length ciphertext data length (must be a multiple of 16) + */ + fsp_err_t (* AES256CBC_DecryptUpdate)(sce_aes_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256CBC decryption. + * @par Implemented as + * - @ref R_SCE_AES256CBC_DecryptFinal() + * + * @param[in,out] handle AES handler (work area) + * @param[in,out] plain plaintext data area (nothing ever written here) + * @param[in,out] plain_length plaintext data length (0 always written here) + */ + fsp_err_t (* AES256CBC_DecryptFinal)(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + + /** Initialize AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES128GCM_EncryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES128GCM_EncryptUpdate)(sce_gcm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES128GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_EncryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + */ + fsp_err_t (* AES128GCM_EncryptFinal)(sce_gcm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_data_length, + uint8_t * atag); + + /** Initialize AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES128GCM_DecryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES128GCM_DecryptUpdate)(sce_gcm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES128GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128GCM_DecryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + */ + fsp_err_t (* AES128GCM_DecryptFinal)(sce_gcm_handle_t * handle, uint8_t * plain, uint32_t * plain_data_length, + uint8_t * atag, uint32_t atag_length); + + /** Initialize AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES256GCM_EncryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_data_length plaintext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES256GCM_EncryptUpdate)(sce_gcm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES256GCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_EncryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area (cipher_data_length byte) + * @param[in,out] cipher_data_length ciphertext data length (0 always written here) + * @param[in,out] atag authentication tag area + */ + fsp_err_t (* AES256GCM_EncryptFinal)(sce_gcm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_data_length, + uint8_t * atag); + + /** Initialize AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptInit() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] initial_vector initialization vector area (initial_vector_length byte) + * @param[in] initial_vector_length initialization vector length (1 ore more bytes) + */ + fsp_err_t (* AES256GCM_DecryptInit)(sce_gcm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, uint32_t initial_vector_length); + + /** Update AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptUpdate() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in] plain plaintext data area + * @param[in] cipher_data_length ciphertext data length (0 or more bytes) + * @param[in] aad additional authentication data (aad_length byte) + * @param[in] aad_length additional authentication data length (0 or more bytes) + */ + fsp_err_t (* AES256GCM_DecryptUpdate)(sce_gcm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_data_length, uint8_t * aad, uint32_t aad_length); + + /** Finalize AES256GCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256GCM_DecryptFinal() + * + * @param[in,out] handle AES-GCM handler (work area) + * @param[in,out] plain plaintext data area (cipher_data_length byte) + * @param[in,out] plain_data_length plaintext data length (0 always written here) + * @param[in,out] atag authentication tag area (atag_length byte) + * @param[in] atag_length authentication tag length (4,8,12,13,14,15,16 bytes) + */ + fsp_err_t (* AES256GCM_DecryptFinal)(sce_gcm_handle_t * handle, uint8_t * plain, uint32_t * plain_data_length, + uint8_t * atag, uint32_t atag_length); + + /** Initialize AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_EncryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + */ + fsp_err_t (* AES128CCM_EncryptUpdate)(sce_ccm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES128CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_EncryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_EncryptFinal)(sce_ccm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_DecryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + */ + fsp_err_t (* AES128CCM_DecryptUpdate)(sce_ccm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES128CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES128CCM_DecryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES128CCM_DecryptFinal)(sce_ccm_handle_t * handle, uint8_t * plain, uint32_t * plain_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_EncryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] plain plaintext data area + * @param[in,out] cipher ciphertext data area + * @param[in] plain_length plaintext data length + */ + fsp_err_t (* AES256CCM_EncryptUpdate)(sce_ccm_handle_t * handle, uint8_t * plain, uint8_t * cipher, + uint32_t plain_length); + + /** Finalize AES256CCM encryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_EncryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] cipher ciphertext data area + * @param[in,out] cipher_length ciphertext data length + * @param[in,out] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_EncryptFinal)(sce_ccm_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptInit() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + * @param[in] nonce Nonce + * @param[in] nonce_length Nonce data length (7 to 13 bytes) + * @param[in] adata additional authentication data + * @param[in] a_length additional authentication data length (0 to 110 bytes) + * @param[in] payload_length Payload length (any number of bytes) + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_DecryptInit)(sce_ccm_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key, uint8_t * nonce, + uint32_t nonce_length, uint8_t * adata, uint8_t a_length, + uint32_t payload_length, uint32_t mac_length); + + /** Update AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptUpdate() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in] cipher ciphertext data area + * @param[in,out] plain plaintext data area + * @param[in] cipher_length ciphertext data length + */ + fsp_err_t (* AES256CCM_DecryptUpdate)(sce_ccm_handle_t * handle, uint8_t * cipher, uint8_t * plain, + uint32_t cipher_length); + + /** Finalize AES256CCM decryption. + * @par Implemented as + * - @ref R_SCE_AES256CCM_DecryptFinal() + * + * @param[in,out] handle AES-CCM handler (work area) + * @param[in,out] plain plaintext data area + * @param[in,out] plain_length plaintext data length + * @param[in] mac MAC area + * @param[in] mac_length MAC length (4, 6, 8, 10, 12, 14, or 16 bytes) + */ + fsp_err_t (* AES256CCM_DecryptFinal)(sce_ccm_handle_t * handle, uint8_t * plain, uint32_t * plain_length, + uint8_t * mac, uint32_t mac_length); + + /** Initialize AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128CMAC_GenerateInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES128CMAC_GenerateUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES128CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_GenerateFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + */ + fsp_err_t (* AES128CMAC_GenerateFinal)(sce_cmac_handle_t * handle, uint8_t * mac); + + /** Initialize AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* AES128CMAC_VerifyInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES128CMAC_VerifyUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES128CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES128CMAC_VerifyFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + */ + fsp_err_t (* AES128CMAC_VerifyFinal)(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** Initialize AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256CMAC_GenerateInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES256CMAC_GenerateUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES256CMAC generation. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_GenerateFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (16byte) + */ + fsp_err_t (* AES256CMAC_GenerateFinal)(sce_cmac_handle_t * handle, uint8_t * mac); + + /** Initialize AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyInit() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] wrapped_key 256-bit AES wrapped key + */ + fsp_err_t (* AES256CMAC_VerifyInit)(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); + + /** Update AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyUpdate() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in] message message data area (message_length byte) + * @param[in] message_length message data length (0 or more bytes) + */ + fsp_err_t (* AES256CMAC_VerifyUpdate)(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize AES256CMAC verification. + * @par Implemented as + * - @ref R_SCE_AES256CMAC_VerifyFinal() + * + * @param[in,out] handle AES-CMAC handler (work area) + * @param[in,out] mac MAC data area (mac_length byte) + * @param[in,out] mac_length MAC data length (2 to 16 bytes) + */ + fsp_err_t (* AES256CMAC_VerifyFinal)(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** Initialize SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Init() + * + * @param[in,out] handle SHA handler (work area) + */ + fsp_err_t (* SHA256_Init)(sce_sha_md5_handle_t * handle); + + /** Update SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Update() + * + * @param[in,out] handle SHA handler (work area) + * @param[in] message message data area + * @param[in] message_length message data length + */ + fsp_err_t (* SHA256_Update)(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize SHA-256 Calculation. + * @par Implemented as + * - @ref R_SCE_SHA256_Final() + * + * @param[in,out] handle SHA handler (work area) + * @param[in,out] digest hasha data area + * @param[in,out] digest_length hash data length (32bytes) + */ + fsp_err_t (* SHA256_Final)(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + + /** This API outputs 1024-bit RSA wrapped pair key. + * @par Implemented as + * - @ref R_SCE_RSA1024_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* RSA1024_WrappedKeyPairGenerate)(sce_rsa1024_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs 2048-bit RSA wrapped pair key. + * @par Implemented as + * - @ref R_SCE_RSA2048_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_key 128-bit AES wrapped key + */ + fsp_err_t (* RSA2048_WrappedKeyPairGenerate)(sce_rsa2048_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs 1024-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA1024_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA public wrapped key + */ + fsp_err_t (* RSA1024_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_public_wrapped_key_t * wrapped_key); + + /** This API outputs 1024-bit RSA private wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA1024_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 1024-bit RSA private wrapped key + */ + fsp_err_t (* RSA1024_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_private_wrapped_key_t * wrapped_key); + + /** This API outputs 2048-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA2048_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 2048-bit RSA public wrapped key + */ + fsp_err_t (* RSA2048_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_public_wrapped_key_t * wrapped_key); + + /** This API outputs 2048-bit RSA private wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA2048_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 2048-bit RSA private wrapped key + */ + fsp_err_t (* RSA2048_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_private_wrapped_key_t * wrapped_key); + + /** This API outputs 3072-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA3072_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 3072-bit RSA public wrapped key + */ + fsp_err_t (* RSA3072_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa3072_public_wrapped_key_t * wrapped_key); + + /** This API outputs 4096-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA4096_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 4096-bit RSA public wrapped key + */ + fsp_err_t (* RSA4096_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + + /** RSASSA-PKCS1-V1_5 signature generation. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS1024_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS1024_SignatureGenerate)(sce_rsa_byte_data_t * message_hash, sce_rsa_byte_data_t * signature, + sce_rsa1024_private_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature generation. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS2048_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Inputs the 2048-bit RSA private wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS2048_SignatureGenerate)(sce_rsa_byte_data_t * message_hash, sce_rsa_byte_data_t * signature, + sce_rsa2048_private_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS1024_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS1024_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS2048_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 2048-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS2048_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS3072_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS3072_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSASSA-PKCS1-V1_5 signature verification. + * @par Implemented as + * - @ref R_SCE_RSASSA_PKCS4096_SignatureVerify() + * + * @param[in] signature Signature text information to verify + * @param[in] message_hash Message text or hash value to verify + * @param[in] wrapped_key Inputs the 4096-bit RSA public wrapped key. + * @param[in] hash_type Only HW_SCE_RSA_HASH_SHA256 is supported + */ + fsp_err_t (* RSASSA_PKCS4096_SignatureVerify)(sce_rsa_byte_data_t * signature, sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_wrapped_key_t * wrapped_key, uint8_t hash_type); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS1024_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 1024-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS1024_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS2048_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 2048-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS2048_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS3072_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 3072-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS3072_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 encryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS4096_Encrypt() + * + * @param[in] plain plaintext + * @param[in,out] cipher ciphertext + * @param[in] wrapped_key Inputs the 4096-bit RSA public wrapped key. + */ + fsp_err_t (* RSAES_PKCS4096_Encrypt)(sce_rsa_byte_data_t * plain, sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 decryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS1024_Decrypt() + * + * @param[in] cipher ciphertext + * @param[in,out] plain plaintext + * @param[in] wrapped_key Inputs the 1024-bit RSA private wrapped key. + */ + fsp_err_t (* RSAES_PKCS1024_Decrypt)(sce_rsa_byte_data_t * cipher, sce_rsa_byte_data_t * plain, + sce_rsa1024_private_wrapped_key_t * wrapped_key); + + /** RSAES-PKCS1-V1_5 decryption. + * @par Implemented as + * - @ref R_SCE_RSAES_PKCS2048_Decrypt() + * + * @param[in] cipher ciphertext + * @param[in,out] plain plaintext + * @param[in] wrapped_key Inputs the 2048-bit RSA private wrapped key. + */ + fsp_err_t (* RSAES_PKCS2048_Decrypt)(sce_rsa_byte_data_t * cipher, sce_rsa_byte_data_t * plain, + sce_rsa2048_private_wrapped_key_t * wrapped_key); + + /** This API outputs HMAC-SHA256 wrapped key. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_EncryptedKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key HMAC-SHA256 wrapped key + */ + fsp_err_t (* SHA256HMAC_EncryptedKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Initialize HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateInit() + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + */ + fsp_err_t (* SHA256HMAC_GenerateInit)(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Update HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateUpdate() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + */ + fsp_err_t (* SHA256HMAC_GenerateUpdate)(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize HMAC-SHA256 generation. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_GenerateFinal() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in,out] mac HMAC area (32 bytes) + */ + fsp_err_t (* SHA256HMAC_GenerateFinal)(sce_hmac_sha_handle_t * handle, uint8_t * mac); + + /** Initialize HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyInit() + * + * @param[in,out] handle SHA-HMAC handler (work area) + * @param[in] wrapped_key MAC wrapped key + */ + fsp_err_t (* SHA256HMAC_VerifyInit)(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); + + /** Update HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyUpdate() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] message Message area + * @param[in] message_length Message length + */ + fsp_err_t (* SHA256HMAC_VerifyUpdate)(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); + + /** Finalize HMAC-SHA256 verification. + * @par Implemented as + * - @ref R_SCE_SHA256HMAC_VerifyFinal() + * + * @param[in,out] handle SHA-HMAC handle (work area) + * @param[in] mac HMAC area + * @param[in] mac_length HMAC length + */ + fsp_err_t (* SHA256HMAC_VerifyFinal)(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + + /** This API outputs secp192r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp192r1 public key and private key pair + */ + fsp_err_t (* ECC_secp192r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp224r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp224r1 public key and private key pair + */ + fsp_err_t (* ECC_secp224r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp256r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp256r1 public key and private key pair + */ + fsp_err_t (* ECC_secp256r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp384r1 wrapped pair key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_WrappedKeyPairGenerate() + * + * @param[in,out] wrapped_pair_key Wrapped pair key for secp384r1 public key and private key pair + */ + fsp_err_t (* ECC_secp384r1_WrappedKeyPairGenerate)(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); + + /** This API outputs secp192r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 public wrapped key + */ + fsp_err_t (* ECC_secp192r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp224r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 public wrapped key + */ + fsp_err_t (* ECC_secp224r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp256r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 public wrapped key + */ + fsp_err_t (* ECC_secp256r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp384r1 public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 public wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPublicKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** This API outputs secp192r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp192r1 private wrapped key + */ + fsp_err_t (* ECC_secp192r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp224r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp224r1 private wrapped key + */ + fsp_err_t (* ECC_secp224r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp256r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp256r1 private wrapped key + */ + fsp_err_t (* ECC_secp256r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** This API outputs secp384r1 private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap() + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key secp384r1 private wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPrivateKeyWrap)(uint8_t * initial_vector, uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp192r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp192r1 private key. + */ + fsp_err_t (* ECDSA_secp192r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp224r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp224r1 private key. + */ + fsp_err_t (* ECDSA_secp224r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp256r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp256r1 private key. + */ + fsp_err_t (* ECDSA_secp256r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature generation. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp384r1_SignatureGenerate() + * + * @param[in] message_hash Message or hash value to which to attach signature + * @param[in,out] signature Signature text storage destination information + * @param[in] wrapped_key Input wrapped key of secp384r1 private key. + */ + fsp_err_t (* ECDSA_secp384r1_SignatureGenerate)(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp192r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp192r1 public key. + */ + fsp_err_t (* ECDSA_secp192r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp224r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp224r1 public key. + */ + fsp_err_t (* ECDSA_secp224r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp256r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp256r1 public key. + */ + fsp_err_t (* ECDSA_secp256r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** ECDSA signature verification. + * @par Implemented as + * - @ref R_SCE_ECDSA_secp384r1_SignatureVerify() + * + * @param[in] signature Signature text information to be verified + * @param[in,out] message_hash Message or hash value to be verified + * @param[in] wrapped_key Input wrapped key of secp384r1 public key. + */ + fsp_err_t (* ECDSA_secp384r1_SignatureVerify)(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH Initialization. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_Init() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] key_type Key exchange type + * @param[in] use_key_id use key_id or not + */ + fsp_err_t (* ECDH_secp256r1_Init)(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); + + /** secp256r1 ECDH public key Signature. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeySign() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key For ECDHE, input a null pointer. For ECDH, input the wrapped key of a secp256r1 public key. + * @param[in] ecc_private_wrapped_key secp256r1 private key for signature generation + * @param[in,out] public_key User secp256r1 public key (512-bit) for key exchange. + * @param[in,out] signature Signature text storage destination information + * @param[in,out] wrapped_key For ECDHE, a private wrapped key generated from a random number. Not output for ECDH. + */ + fsp_err_t (* ECDH_secp256r1_PublicKeySign)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + uint8_t * public_key, sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH public key verification. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeyVerify() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key area for signature verification + * @param[in] public_key_data secp256r1 public key (512-bit) + * @param[in] signature ECDSA secp256r1 signature of ecc_public_wrapped_key + * @param[in,out] wrapped_key wrapped key of ecc_public_wrapped_key + */ + fsp_err_t (* ECDH_secp256r1_PublicKeyVerify)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + uint8_t * public_key_data, sce_ecdsa_byte_data_t * signature, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** Output the key index of QeU without signature verification. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] public_key_data secp256r1 public key (512-bit). When key_id is used: + * key_id (8-bit) || public key (512-bit) + * @param[in,out] wrapped_key wrapped key of ecc_public_wrapped_key + */ + fsp_err_t (* ECDH_secp256r1_PublicKeyReadWithoutSignature)(sce_ecdh_handle_t * handle, + uint8_t * public_key_data, + sce_ecc_public_wrapped_key_t * wrapped_key); + + /** secp256r1 ECDH shared secret calculation. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_SharedSecretCalculate() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] ecc_public_wrapped_key Public wrapped key + * @param[in] ecc_private_wrapped_key Private wrapped key + * @param[in,out] shared_secret_wrapped_key Wrapped key of shared secret Z calculated by ECDH key exchange + */ + fsp_err_t (* ECDH_secp256r1_SharedSecretCalculate)(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key); + + /** secp256r1 ECDH key derivation. + * @par Implemented as + * - @ref R_SCE_ECDH_secp256r1_KeyDerivation() + * + * @param[in,out] handle ECDH handler (work area) + * @param[in] shared_secret_wrapped_key Z wrapped key calculated by R_SCE_ECDH_secp256r1_SharedSecretCalculate + * @param[in] key_type Derived key type + * @param[in] kdf_type Algorithm used for key derivation calculation + * @param[in] other_info Additional data used for key derivation calculation + * @param[in] other_info_length Data length of other_info + * @param[in] salt_wrapped_key Salt wrapped key + * @param[in,out] wrapped_key Wrapped key corresponding to key_type. + */ + fsp_err_t (* ECDH_secp256r1_KeyDerivation)(sce_ecdh_handle_t * handle, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key, uint32_t key_type, + uint32_t kdf_type, uint8_t * other_info, + uint32_t other_info_length, + sce_hmac_sha_wrapped_key_t * salt_wrapped_key, + sce_aes_wrapped_key_t * wrapped_key); + + /** Generate TLS RSA Public key index data + * @par Implemented as + * - @ref R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall() + * + * @param[in] encrypted_provisioning_key the provisioning key includes encrypted CBC/CBC-MAC key for user key + * @param[in] initial_vector the initial_vector for user key CBC encrypt + * @param[in] encrypted_key the user key encrypted with AES128-ECB mode + * @param[out] wrapped_key the user Key Generation Information (141 words) of RSA2048 bit + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_RootCertificateRSA2048PublicKeyInstall)(uint8_t * encrypted_provisioning_key, + uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_wrapped_key_t * wrapped_key); + + /** Generate TLS ECC key pair + * @par Implemented as + * - @ref R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate() + * + * @param[in] tls_p256_ecc_wrapped_key P256 ECC key index for TLS + * @param[in] ephemeral_ecdh_public_key ephemeral ECDH public key + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate)(sce_tls_p256_ecc_wrapped_key_t * tls_p256_ecc_wrapped_key, + uint8_t * ephemeral_ecdh_public_key); + + /** Verify root CA certificate. + * @par Implemented as + * - @ref R_SCE_TLS_RootCertificateVerify() + * + * @param[in] public_key_type key type + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[in] signature signature for certificates. + * @param[out] encrypted_root_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + * + */ + fsp_err_t (* TLS_RootCertificateVerify)(uint32_t public_key_type, + uint8_t *certificate, + uint32_t certificate_length, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint8_t *signature, + uint32_t *encrypted_root_public_key); + + /** Verify server certificate and intermediate certificate. + * @par Implemented as + * - @ref R_SCE_TLS_CertificateVerify() + * + * @param[in] public_key_type key type + * @param[in] input_public_key public key. + * @param[in] certificate certificates. + * @param[in] certificate_length byte size of certificates. + * @param[in] signature signature for certificates. + * @param[in] public_key_n_start_position start position of public key n. + * @param[in] public_key_n_end_position end position of public key n. + * @param[in] public_key_e_start_position start position of public key e. + * @param[in] public_key_e_end_position end position of public key e. + * @param[out] encrypted_output_public_key public key for RSA 2048bit. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_CertificateVerify)(uint32_t public_key_type, + uint32_t *encrypted_input_public_key, + uint8_t *certificate, + uint32_t certificate_length, + uint8_t *signature, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); + + /** Generate encrypted pre-master secret. + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretGenerateForRSA2048() + * + * @param[out] sce_pre_master_secret pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + */ + fsp_err_t (* TLS_PreMasterSecretGenerateForRSA2048)(uint32_t *sce_pre_master_secret); + + /** Generate encrypted master secret. + * @par Implemented as + * - @ref R_SCE_TLS_MasterSecretGenerate() + * + * @param[in] select_cipher_suite cipher suite type + * @param[in] sce_pre_master_secret pre-master secret value for SCE. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[out] sce_master_secret master secret value with SCE-specific conversion. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_MasterSecretGenerate)(uint32_t select_cipher_suite, + uint32_t *sce_pre_master_secret, + uint8_t *client_random, + uint8_t *server_random, + uint32_t *sce_master_secret); + + /** Output the result encrypted pre-master secret with RSA 2048bit + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretEncryptWithRSA2048() + * + * @param[in] encrypted_public_key public key data. + * @param[in] sce_pre_master_secret pre-master secret value. + * @param[out] encrypted_pre_master_secret the value encrypted pre-master secret. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_PreMasterSecretEncryptWithRSA2048)(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, + uint8_t *encrypted_pre_master_secret); + + /** Output various key information. + * @par Implemented as + * - @ref R_SCE_TLS_SessionKeyGenerate() + * + * @param[in] select_cipher_suite Key suite information number. + * @param[in] sce_master_secret master secret value. + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] nonce_explicit nonce value + * @param[out] client_mac_wrapped_key the mac key during communication from client to server. + * @param[out] server_mac_wrapped_key the mac key during communication from server to client. + * @param[out] client_crypto_wrapped_key the crypto key during communication from client to server. + * @param[out] server_crypto_wrapped_key the crypto key during communication from server to client. + * @param[in] client_initial_vector not use. + * @param[in] server_initial_vector not use. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_SessionKeyGenerate)(uint32_t select_cipher_suite, + uint32_t *sce_master_secret, + uint8_t *client_random, + uint8_t *server_random, + uint8_t* nonce_explicit, + sce_hmac_sha_wrapped_key_t *client_mac_wrapped_key, + sce_hmac_sha_wrapped_key_t *server_mac_wrapped_key, + sce_aes_wrapped_key_t *client_crypto_wrapped_key, + sce_aes_wrapped_key_t *server_crypto_wrapped_key, + uint8_t *client_initial_vector, + uint8_t *server_initial_vector); + + /** Generate verify data. + * @par Implemented as + * - @ref R_SCE_TLS_VerifyDataGenerate() + * + * @param[in] select_verify_data Select Client/Server data. + * @param[in] sce_master_secret master secret data. + * @param[in] hand_shake_hash TLS hand shake message SHA256 HASH value. + * @param[out] verify_data verify data. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_VerifyDataGenerate)(uint32_t select_verify_data, + uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, + uint8_t *verify_data); + + /** Retrives ECDH public key. + * @par Implemented as + * - @ref R_SCE_TLS_ServerKeyExchangeVerify() + * + * @param[in] public_key_type key type + * @param[in] client_random random value reported ClientHello. + * @param[in] server_random random value reported ServerHello. + * @param[in] server_ephemeral_ecdh_public_key Ephemeral ECDH public key from Server. + * @param[in] server_key_exchange_sigunature Server Key Exchange sigunature. + * @param[in] encrypted_public_key encrypted public key. + * @param[out] encrypted_ephemeral_ecdh_public_key encrypted Ephemeral ECDH public key. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_ServerKeyExchangeVerify)(uint32_t public_key_type, + uint8_t *client_random, + uint8_t *server_random, + uint8_t *server_ephemeral_ecdh_public_key, + uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, + uint32_t *encrypted_ephemeral_ecdh_public_key); + + /** Generate encrypted pre-master secret. + * @par Implemented as + * - @ref R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1() + * + * @param[in] encrypted_public_key encrypted public key + * @param[in] tls_p256_ecc_wrapped_key P-256 ECC key index. + * @param[out] sce_pre_master_secret encrypted pre-master secret value for SCE. + * + * @retval FSP_SUCCESS Normal termination + * @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed + * by the processing routine was in use by another processing routine. + * @retval FSP_ERR_CRYPTO_SCE_FAIL An internal error occurred. + */ + fsp_err_t (* TLS_PreMasterSecretGenerateForECC_secp256r1)(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, + uint32_t *sce_pre_master_secret); + +} sce_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_sce_instance +{ + sce_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + sce_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + sce_api_t const * p_api; ///< Pointer to the API structure for this instance +} sce_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_SCE_API_H */ + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED_API) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h new file mode 100644 index 00000000..2573996d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/inc/instances/r_sce.h @@ -0,0 +1,607 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup SCE_PROTECTED + * @{ + **********************************************************************************************************************/ + +#ifndef R_SCE_H +#define R_SCE_H + +#include "bsp_api.h" +#include "r_sce_cfg.h" +#include "r_sce_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +/* ECC curve types. */ +#define SCE_ECC_CURVE_TYPE_NIST (0) +#define SCE_ECC_CURVE_TYPE_BRAINPOOL (1) +#define SCE_ECC_CURVE_TYPE_KOBLITZ (2) + +/* ECC curve size */ +#define SCE_ECC_KEY_LENGTH_256 (0) +#define SCE_ECC_KEY_LENGTH_224 (1) +#define SCE_ECC_KEY_LENGTH_192 (2) + +/* For AES operation. */ +#define SCE_KEYWRAP_AES128 (0U) +#define SCE_KEYWRAP_AES256 (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_FOR_ECDH, + SCE_KEY_INDEX_TYPE_AES256_FOR_ECDH, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_ECDH, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES256_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_GCM_WITH_IV, +} SCE_KEY_INDEX_TYPE; + +/* OEM Command */ +typedef enum e_sce_oem_cmd +{ + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES256 = 7, + SCE_OEM_CMD_RSA1024_PUBLIC = 10, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA256 = 27, + SCE_OEM_CMD_NUM +} sce_oem_cmd_t; + +/** SCE private control block. DO NOT MODIFY. Initialization occurs when R_SCE_Open() is called. */ +typedef struct st_sce_instance_ctrl +{ + uint32_t open; // Indicates whether the open() API has been successfully +} sce_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const sce_api_t g_sce_protected_on_sce; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_SCE_Open(sce_ctrl_t * const p_ctrl, sce_cfg_t const * const p_cfg); +fsp_err_t R_SCE_Close(sce_ctrl_t * const p_ctrl); +fsp_err_t R_SCE_SoftwareReset(void); + +fsp_err_t R_SCE_AES128_WrappedKeyGenerate(sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256_WrappedKeyGenerate(sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA1024_WrappedKeyPairGenerate(sce_rsa1024_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_RSA2048_WrappedKeyPairGenerate(sce_rsa2048_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp192r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp224r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp256r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_ECC_secp384r1_WrappedKeyPairGenerate(sce_ecc_wrapped_pair_key_t * wrapped_pair_key); +fsp_err_t R_SCE_RandomNumberGenerate(uint32_t * random); + +fsp_err_t R_SCE_AES128_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128_RFC3394KeyWrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key); +fsp_err_t R_SCE_AES256_RFC3394KeyWrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + sce_aes_wrapped_key_t * target_key, + uint32_t * rfc3394_wrapped_key); +fsp_err_t R_SCE_AES128_RFC3394KeyUnwrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key); +fsp_err_t R_SCE_AES256_RFC3394KeyUnwrap(sce_aes_wrapped_key_t * master_key, + uint32_t target_key_type, + uint32_t * rfc3394_wrapped_key, + sce_aes_wrapped_key_t * target_key); +fsp_err_t R_SCE_SHA256HMAC_EncryptedKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_hmac_sha_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_RSA1024_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA1024_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa1024_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA2048_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA2048_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa2048_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA3072_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa3072_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSA4096_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp192r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp224r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap(uint8_t * initial_vector, + uint8_t * encrypted_key, + sce_key_update_key_t * key_update_key, + sce_ecc_private_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_AES128ECB_EncryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128ECB_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128ECB_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES128ECB_DecryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128ECB_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128ECB_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t R_SCE_AES256ECB_EncryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256ECB_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256ECB_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES256ECB_DecryptInit(sce_aes_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256ECB_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256ECB_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t R_SCE_AES128CBC_EncryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES128CBC_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128CBC_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES128CBC_DecryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES128CBC_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128CBC_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t R_SCE_AES256CBC_EncryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES256CBC_EncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256CBC_EncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t R_SCE_AES256CBC_DecryptInit(sce_aes_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector); +fsp_err_t R_SCE_AES256CBC_DecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256CBC_DecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t R_SCE_AES128GCM_EncryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES128GCM_EncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES128GCM_EncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag); +fsp_err_t R_SCE_AES128GCM_DecryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES128GCM_DecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES128GCM_DecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length); + +fsp_err_t R_SCE_AES256GCM_EncryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES256GCM_EncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES256GCM_EncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_length, + uint8_t * atag); +fsp_err_t R_SCE_AES256GCM_DecryptInit(sce_gcm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * initial_vector, + uint32_t initial_vector_length); +fsp_err_t R_SCE_AES256GCM_DecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_length, + uint8_t * aad, + uint32_t aad_length); +fsp_err_t R_SCE_AES256GCM_DecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_length, + uint8_t * atag, + uint32_t atag_length); + +fsp_err_t R_SCE_AES128CCM_EncryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_EncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES128CCM_EncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_DecryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES128CCM_DecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES128CCM_DecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t R_SCE_AES256CCM_EncryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_EncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t R_SCE_AES256CCM_EncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_DecryptInit(sce_ccm_handle_t * handle, + sce_aes_wrapped_key_t * wrapped_key, + uint8_t * nonce, + uint32_t nonce_length, + uint8_t * adata, + uint8_t adata_length, + uint32_t payload_length, + uint32_t mac_length); +fsp_err_t R_SCE_AES256CCM_DecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t R_SCE_AES256CCM_DecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t R_SCE_AES128CMAC_GenerateInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128CMAC_GenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES128CMAC_GenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_AES128CMAC_VerifyInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES128CMAC_VerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES128CMAC_VerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t R_SCE_AES256CMAC_GenerateInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256CMAC_GenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES256CMAC_GenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_AES256CMAC_VerifyInit(sce_cmac_handle_t * handle, sce_aes_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_AES256CMAC_VerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_AES256CMAC_VerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t R_SCE_SHA256_Init(sce_sha_md5_handle_t * handle); +fsp_err_t R_SCE_SHA256_Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256_Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t R_SCE_SHA256HMAC_GenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_SHA256HMAC_GenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256HMAC_GenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t R_SCE_SHA256HMAC_VerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_SHA256HMAC_VerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t R_SCE_SHA256HMAC_VerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa1024_private_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS1024_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa2048_private_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS2048_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS3072_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); +fsp_err_t R_SCE_RSASSA_PKCS4096_SignatureVerify(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_wrapped_key_t * wrapped_key, + uint8_t hash_type); + +fsp_err_t R_SCE_RSAES_PKCS1024_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS1024_Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa1024_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS2048_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS2048_Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa2048_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS3072_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_RSAES_PKCS4096_Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp192r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp224r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp256r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDSA_secp384r1_SignatureVerify(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_ECDH_secp256r1_Init(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeySign(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + uint8_t * public_key, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyVerify(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + uint8_t * public_key_data, + sce_ecdsa_byte_data_t * signature, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_PublicKeyReadWithoutSignature(sce_ecdh_handle_t * handle, + uint8_t * public_key_data, + sce_ecc_public_wrapped_key_t * wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_SharedSecretCalculate(sce_ecdh_handle_t * handle, + sce_ecc_public_wrapped_key_t * ecc_public_wrapped_key, + sce_ecc_private_wrapped_key_t * ecc_private_wrapped_key, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key); +fsp_err_t R_SCE_ECDH_secp256r1_KeyDerivation(sce_ecdh_handle_t * handle, + sce_ecdh_wrapped_key_t * shared_secret_wrapped_key, + uint32_t key_type, + uint32_t kdf_type, + uint8_t * other_info, + uint32_t other_info_length, + sce_hmac_sha_wrapped_key_t * salt_wrapped_key, + sce_aes_wrapped_key_t * wrapped_key); + +fsp_err_t R_SCE_TLS_RootCertificateRSA2048PublicKeyInstall(uint8_t *encrypted_provisioning_key, uint8_t *initial_vector, + uint8_t *encrypted_key, sce_tls_ca_certification_public_wrapped_key_t *wrapped_key); +fsp_err_t R_SCE_TLS_ECC_secp256r1_EphemeralWrappedKeyPairGenerate(sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, + uint8_t *ephemeral_ecdh_public_key); +fsp_err_t R_SCE_TLS_RootCertificateVerify(uint32_t public_key_type, uint8_t *certificate, + uint32_t certificate_length, uint32_t public_key_n_start_position, uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, uint8_t *signature, + uint32_t *encrypted_root_public_key); +fsp_err_t R_SCE_TLS_CertificateVerify(uint32_t public_key_type, uint32_t *encrypted_input_public_key, + uint8_t *certificate, uint32_t certificate_length, uint8_t *signature, uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, uint32_t public_key_e_start_position, uint32_t public_key_e_end_position, + uint32_t *encrypted_output_public_key); +fsp_err_t R_SCE_TLS_PreMasterSecretEncryptWithRSA2048(uint32_t *encrypted_public_key, + uint32_t *sce_pre_master_secret, uint8_t *encrypted_pre_master_secret); +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForRSA2048(uint32_t *sce_pre_master_secret); +fsp_err_t R_SCE_TLS_MasterSecretGenerate (uint32_t select_cipher_suite, uint32_t *sce_pre_master_secret, + uint8_t *client_random, uint8_t *server_random, uint32_t *sce_master_secret); +fsp_err_t R_SCE_TLS_SessionKeyGenerate(uint32_t select_cipher_suite, uint32_t *sce_master_secret, + uint8_t *client_random, uint8_t *server_random, uint8_t* nonce_explicit, + sce_hmac_sha_wrapped_key_t *client_mac_wrapped_key, sce_hmac_sha_wrapped_key_t *server_mac_wrapped_key, + sce_aes_wrapped_key_t *client_crypto_wrapped_key, sce_aes_wrapped_key_t *server_crypto_wrapped_key, + uint8_t *client_initial_vector, uint8_t *server_initial_vector); +fsp_err_t R_SCE_TLS_VerifyDataGenerate(uint32_t select_verify_data, uint32_t *sce_master_secret, + uint8_t *hand_shake_hash, uint8_t *verify_data); +fsp_err_t R_SCE_TLS_ServerKeyExchangeVerify(uint32_t public_key_type, uint8_t *client_random, + uint8_t *server_random, uint8_t *server_ephemeral_ecdh_public_key, uint8_t *server_key_exchange_signature, + uint32_t *encrypted_public_key, uint32_t *encrypted_ephemeral_ecdh_public_key); +fsp_err_t R_SCE_TLS_PreMasterSecretGenerateForECC_secp256r1(uint32_t *encrypted_public_key, + sce_tls_p256_ecc_wrapped_key_t *tls_p256_ecc_wrapped_key, uint32_t *sce_pre_master_secret); + +uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t * message, uint8_t * digest, uint32_t message_length); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_SCE_H + +/*******************************************************************************************************************//** + * @} (end addtogroup SCE_PROTECTED) + **********************************************************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h new file mode 100644 index 00000000..3924fbb6 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_ProcCommon.h @@ -0,0 +1,4776 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : SCE_ProcCommon.h +* Description : IO definition for FSP SCE +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 05.10.2018 1.00 First Release. +***********************************************************************************************************************/ +#ifndef HW_SCE_E017_H +#define HW_SCE_E017_H + +#include "bsp_api.h" +#include "SCE_module.h" + +#define SCE ((SCE_Type*) SCE_BASE) + +typedef struct { + union { + __IOM uint32_t REG_00H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_00H_b; + }; + union { + __IOM uint32_t REG_04H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_04H_b; + }; + union { + __IOM uint32_t REG_08H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_08H_b; + }; + union { + __IOM uint32_t REG_0CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_0CH_b; + }; + union { + __IOM uint32_t REG_10H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_10H_b; + }; + union { + __IOM uint32_t REG_14H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_14H_b; + }; + union { + __IOM uint32_t REG_18H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_18H_b; + }; + union { + __IOM uint32_t REG_1CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1CH_b; + }; + union { + __IOM uint32_t REG_20H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_20H_b; + }; + union { + __IOM uint32_t REG_24H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_24H_b; + }; + union { + __IOM uint32_t REG_28H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_28H_b; + }; + union { + __IOM uint32_t REG_2CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_2CH_b; + }; + union { + __IOM uint32_t REG_30H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_30H_b; + }; + union { + __IOM uint32_t REG_34H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_34H_b; + }; + union { + __IOM uint32_t REG_38H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_38H_b; + }; + union { + __IOM uint32_t REG_3CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_3CH_b; + }; + union { + __IOM uint32_t REG_40H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_40H_b; + }; + union { + __IOM uint32_t REG_44H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_44H_b; + }; + union { + __IOM uint32_t REG_48H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_48H_b; + }; + union { + __IOM uint32_t REG_4CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_4CH_b; + }; + union { + __IOM uint32_t REG_50H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_50H_b; + }; + union { + __IOM uint32_t REG_54H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_54H_b; + }; + union { + __IOM uint32_t REG_58H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_58H_b; + }; + union { + __IOM uint32_t REG_5CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_5CH_b; + }; + union { + __IOM uint32_t REG_60H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_60H_b; + }; + union { + __IOM uint32_t REG_64H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_64H_b; + }; + union { + __IOM uint32_t REG_68H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_68H_b; + }; + union { + __IOM uint32_t REG_6CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_6CH_b; + }; + union { + __IOM uint32_t REG_70H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_70H_b; + }; + union { + __IOM uint32_t REG_74H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_74H_b; + }; + union { + __IOM uint32_t REG_78H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_78H_b; + }; + union { + __IOM uint32_t REG_7CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_7CH_b; + }; + union { + __IOM uint32_t REG_80H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_80H_b; + }; + union { + __IOM uint32_t REG_84H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_84H_b; + }; + union { + __IOM uint32_t REG_88H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_88H_b; + }; + union { + __IOM uint32_t REG_8CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_8CH_b; + }; + union { + __IOM uint32_t REG_90H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_90H_b; + }; + union { + __IOM uint32_t REG_94H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_94H_b; + }; + union { + __IOM uint32_t REG_98H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_98H_b; + }; + union { + __IOM uint32_t REG_9CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_9CH_b; + }; + union { + __IOM uint32_t REG_A0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A0H_b; + }; + union { + __IOM uint32_t REG_A4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A4H_b; + }; + union { + __IOM uint32_t REG_A8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_A8H_b; + }; + union { + __IOM uint32_t REG_ACH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_ACH_b; + }; + union { + __IOM uint32_t REG_B0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B0H_b; + }; + union { + __IOM uint32_t REG_B4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B4H_b; + }; + union { + __IOM uint32_t REG_B8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_B8H_b; + }; + union { + __IOM uint32_t REG_BCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_BCH_b; + }; + union { + __IOM uint32_t REG_C0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C0H_b; + }; + union { + __IOM uint32_t REG_C4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C4H_b; + }; + union { + __IOM uint32_t REG_C8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_C8H_b; + }; + union { + __IOM uint32_t REG_CCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_CCH_b; + }; + union { + __IOM uint32_t REG_D0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D0H_b; + }; + union { + __IOM uint32_t REG_D4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D4H_b; + }; + union { + __IOM uint32_t REG_D8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_D8H_b; + }; + union { + __IOM uint32_t REG_DCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_DCH_b; + }; + union { + __IOM uint32_t REG_E0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E0H_b; + }; + union { + __IOM uint32_t REG_E4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E4H_b; + }; + union { + __IOM uint32_t REG_E8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_E8H_b; + }; + union { + __IOM uint32_t REG_ECH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_ECH_b; + }; + union { + __IOM uint32_t REG_F0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F0H_b; + }; + union { + __IOM uint32_t REG_F4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F4H_b; + }; + union { + __IOM uint32_t REG_F8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_F8H_b; + }; + union { + __IOM uint32_t REG_FCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_FCH_b; + }; + union { + __IOM uint32_t REG_100H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_100H_b; + }; + union { + __IOM uint32_t REG_104H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_104H_b; + }; + union { + __IOM uint32_t REG_108H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_108H_b; + }; + union { + __IOM uint32_t REG_10CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_10CH_b; + }; + union { + __IOM uint32_t REG_110H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_110H_b; + }; + union { + __IOM uint32_t REG_114H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_114H_b; + }; + union { + __IOM uint32_t REG_118H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_118H_b; + }; + union { + __IOM uint32_t REG_11CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_11CH_b; + }; + union { + __IOM uint32_t REG_120H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_120H_b; + }; + union { + __IOM uint32_t REG_124H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_124H_b; + }; + union { + __IOM uint32_t REG_128H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_128H_b; + }; + union { + __IOM uint32_t REG_12CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_12CH_b; + }; + union { + __IOM uint32_t REG_130H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_130H_b; + }; + union { + __IOM uint32_t REG_134H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_134H_b; + }; + union { + __IOM uint32_t REG_138H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_138H_b; + }; + union { + __IOM uint32_t REG_13CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_13CH_b; + }; + union { + __IOM uint32_t REG_140H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_140H_b; + }; + union { + __IOM uint32_t REG_144H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_144H_b; + }; + union { + __IOM uint32_t REG_148H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_148H_b; + }; + union { + __IOM uint32_t REG_14CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_14CH_b; + }; + union { + __IOM uint32_t REG_150H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_150H_b; + }; + union { + __IOM uint32_t REG_154H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_154H_b; + }; + union { + __IOM uint32_t REG_158H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_158H_b; + }; + union { + __IOM uint32_t REG_15CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_15CH_b; + }; + union { + __IOM uint32_t REG_160H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_160H_b; + }; + union { + __IOM uint32_t REG_164H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_164H_b; + }; + union { + __IOM uint32_t REG_168H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_168H_b; + }; + union { + __IOM uint32_t REG_16CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_16CH_b; + }; + union { + __IOM uint32_t REG_170H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_170H_b; + }; + union { + __IOM uint32_t REG_174H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_174H_b; + }; + union { + __IOM uint32_t REG_178H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_178H_b; + }; + union { + __IOM uint32_t REG_17CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_17CH_b; + }; + union { + __IOM uint32_t REG_180H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_180H_b; + }; + union { + __IOM uint32_t REG_184H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_184H_b; + }; + union { + __IOM uint32_t REG_188H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_188H_b; + }; + union { + __IOM uint32_t REG_18CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_18CH_b; + }; + union { + __IOM uint32_t REG_190H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_190H_b; + }; + union { + __IOM uint32_t REG_194H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_194H_b; + }; + union { + __IOM uint32_t REG_198H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_198H_b; + }; + union { + __IOM uint32_t REG_19CH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_19CH_b; + }; + union { + __IOM uint32_t REG_1A0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A0H_b; + }; + union { + __IOM uint32_t REG_1A4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A4H_b; + }; + union { + __IOM uint32_t REG_1A8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1A8H_b; + }; + union { + __IOM uint32_t REG_1ACH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1ACH_b; + }; + union { + __IOM uint32_t REG_1B0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B0H_b; + }; + union { + __IOM uint32_t REG_1B4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B4H_b; + }; + union { + __IOM uint32_t REG_1B8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1B8H_b; + }; + union { + __IOM uint32_t REG_1BCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1BCH_b; + }; + union { + __IOM uint32_t REG_1C0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C0H_b; + }; + union { + __IOM uint32_t REG_1C4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C4H_b; + }; + union { + __IOM uint32_t REG_1C8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1C8H_b; + }; + union { + __IOM uint32_t REG_1CCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1CCH_b; + }; + union { + __IOM uint32_t REG_1D0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D0H_b; + }; + union { + __IOM uint32_t REG_1D4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D4H_b; + }; + union { + __IOM uint32_t REG_1D8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1D8H_b; + }; + union { + __IOM uint32_t REG_1DCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1DCH_b; + }; + union { + __IOM uint32_t REG_1E0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E0H_b; + }; + union { + __IOM uint32_t REG_1E4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E4H_b; + }; + union { + __IOM uint32_t REG_1E8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1E8H_b; + }; + union { + __IOM uint32_t REG_1ECH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1ECH_b; + }; + union { + __IOM uint32_t REG_1F0H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F0H_b; + }; + union { + __IOM uint32_t REG_1F4H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F4H_b; + }; + union { + __IOM uint32_t REG_1F8H; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1F8H_b; + }; + union { + __IOM uint32_t REG_1FCH; + struct { + __IOM uint32_t B0:1; + __IOM uint32_t B1:1; + __IOM uint32_t B2:1; + __IOM uint32_t B3:1; + __IOM uint32_t B4:1; + __IOM uint32_t B5:1; + __IOM uint32_t B6:1; + __IOM uint32_t B7:1; + __IOM uint32_t B8:1; + __IOM uint32_t B9:1; + __IOM uint32_t B10:1; + __IOM uint32_t B11:1; + __IOM uint32_t B12:1; + __IOM uint32_t B13:1; + __IOM uint32_t B14:1; + __IOM uint32_t B15:1; + __IOM uint32_t B16:1; + __IOM uint32_t B17:1; + __IOM uint32_t B18:1; + __IOM uint32_t B19:1; + __IOM uint32_t B20:1; + __IOM uint32_t B21:1; + __IOM uint32_t B22:1; + __IOM uint32_t B23:1; + __IOM uint32_t B24:1; + __IOM uint32_t B25:1; + __IOM uint32_t B26:1; + __IOM uint32_t B27:1; + __IOM uint32_t B28:1; + __IOM uint32_t B29:1; + __IOM uint32_t B30:1; + __IOM uint32_t B31:1; + } REG_1FCH_b; + }; +} SCE_Type; + +#define MSTP_SECURITY R_MSTP->MSTPCRC_b.MSTPC31 + +#endif /* HW_SCE_E017_H */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h new file mode 100644 index 00000000..26bb94be --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x40161000UL + +#endif // HW_SCE_MODULE_H diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h new file mode 100644 index 00000000..ba254bc0 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/private/inc/r_sce_private.h @@ -0,0 +1,807 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SCE_PRIVATE_HEADER_FILE +#define R_SCE_PRIVATE_HEADER_FILE + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_sce.h" +#include "SCE_ProcCommon.h" +#include "r_sce_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ +extern uint32_t const S_FLASH2[]; + +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +extern uint32_t INST_DATA_SIZE; +extern const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM]; + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/* --------------------- SCE driver wrapper layer ---------------------- */ + +fsp_err_t R_SCE_SelfCheck1Private(void); +fsp_err_t R_SCE_SelfCheck2Private(void); +fsp_err_t R_SCE_SelfCheck3Private(void); +fsp_err_t R_SCE_LoadHukPrivate(lifecycle_t lifecycle); +fsp_err_t R_SCE_FwIntegrityCheckPrivate(void); + +fsp_err_t R_SCE_UpdateOemKeyIndexPrivate(lifecycle_t lifecycle, + sce_oem_cmd_t key_type, + uint8_t * iv, + uint8_t * encrypted_oem_key, + uint32_t * key_index); + +fsp_err_t R_SCE_Aes128EcbEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128EcbEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128EcbEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128EcbDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128EcbDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128EcbDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128CbcEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128CbcEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CbcEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes128CbcDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128CbcDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CbcDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); + +fsp_err_t R_SCE_Aes256EcbEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256EcbEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256EcbEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256EcbDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256EcbDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256EcbDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256CbcEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256CbcEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CbcEncryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); +fsp_err_t R_SCE_Aes256CbcDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256CbcDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CbcDecryptFinalPrivate(uint32_t * OutData_Text, uint32_t * OutData_length); + +fsp_err_t R_SCE_Aes128GcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128GcmEncryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128GcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128GcmEncryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes128GcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes128GcmDecryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128GcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128GcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes256GcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256GcmEncryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256GcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256GcmEncryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes256GcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, uint32_t * InData_IV); +fsp_err_t R_SCE_Aes256GcmDecryptUpdateAadPrivate(uint32_t * InData_DataA, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256GcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT, uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256GcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +void R_SCE_Aes128GcmEncryptUpdateTransitionPrivate(void); +void R_SCE_Aes128GcmDecryptUpdateTransitionPrivate(void); +void R_SCE_Aes256GcmEncryptUpdateTransitionPrivate(void); +void R_SCE_Aes256GcmDecryptUpdateTransitionPrivate(void); + +fsp_err_t R_SCE_Aes128CcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes128CcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CcmEncryptFinalPrivate(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +fsp_err_t R_SCE_Aes128CcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes128CcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes256CcmEncryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes256CcmEncryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CcmEncryptFinalPrivate(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); +fsp_err_t R_SCE_Aes256CcmDecryptInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +fsp_err_t R_SCE_Aes256CcmDecryptUpdatePrivate(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CcmDecryptFinalPrivate(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_Aes128CmacGenerateInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128CmacGenerateUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes128CmacVerifyInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes128CmacVerifyUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes128CmacVerifyFinalPrivate(uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen); + +fsp_err_t R_SCE_Aes256CmacGenerateInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256CmacGenerateUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CmacGenerateFinalPrivate(uint32_t All_Msg_Len, uint32_t * InData_Text, uint32_t * OutData_DataT); +fsp_err_t R_SCE_Aes256CmacVerifyInitPrivate(sce_aes_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Aes256CmacVerifyUpdatePrivate(uint32_t * InData_Text, uint32_t MAX_CNT); +fsp_err_t R_SCE_Aes256CmacVerifyFinalPrivate(uint32_t All_Msg_Len, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen); + +fsp_err_t R_SCE_Sha256InitPrivate(sce_sha_md5_handle_t * handle); +fsp_err_t R_SCE_Sha256UpdatePrivate(sce_sha_md5_handle_t * handle, uint32_t * InData_PaddedMsg, uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256FinalPrivate(sce_sha_md5_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest, + uint32_t * OutData_Length); + +fsp_err_t R_SCE_Sha256HmacGenerateInitPrivate(sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Sha256HmacGenerateUpdatePrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256HmacGenerateFinalPrivate(sce_hmac_sha_handle_t * handle, uint32_t * OutData_Mac); +fsp_err_t R_SCE_Sha256HmacVerifyInitPrivate(sce_hmac_sha_handle_t * handle, + sce_hmac_sha_wrapped_key_t * InData_KeyIndex); +fsp_err_t R_SCE_Sha256HmacVerifyUpdatePrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT); +fsp_err_t R_SCE_Sha256HmacVerifyFinalPrivate(sce_hmac_sha_handle_t * handle, + uint32_t * InData_Mac, + uint32_t * InData_length); + +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +fsp_err_t R_SCE_EcdhReadPublicKeyPrivate(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_data, + uint32_t * InData_Signature, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhReadPublicKeyWithoutSignaturePrivate(uint32_t * InData_Cmd, + uint32_t * InData_data, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhMakePublicKeyPrivate(uint32_t * InData_Cmd, + uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * InData_key_id, + uint32_t * OutData_data, + uint32_t * OutData_Signature, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhCalculateSharedSecretIndexPrivate(uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_EcdhKeyDerivationPrivate(uint32_t * InData_KeyIndexType, + uint32_t * InData_KeyIndex, + uint32_t * InData_KDFType, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * InData_SaltKeyIndex, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_Aes128KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes256KeyWrapPrivate(uint32_t * InData_KeyIndex, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t * OutData_Text); +fsp_err_t R_SCE_Aes128KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex); +fsp_err_t R_SCE_Aes256KeyUnWrapPrivate(sce_aes_wrapped_key_t * InData_MasterKey, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t * OutData_KeyIndex); +/* --------------------- SCE control procedure related ---------------------- */ + +void R_SCE_SoftwareResetSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_SelfCheck1Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_RETRY **/ +fsp_err_t R_SCE_SelfCheck2Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_RETRY **/ +fsp_err_t R_SCE_SelfCheck3Sub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_LoadHukSub(uint32_t * InData_LC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_FwIntegrityCheckSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_UpdateOemKeyIndexSub(uint32_t * InData_LC, + uint32_t * InData_Cmd, + uint32_t * InData_IV, + uint32_t * InData_InstData, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateAes128RandomKeyIndexSub(uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateAes256RandomKeyIndexSub(uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateRsa1024RandomKeyIndexSub(uint32_t MAX_CNT, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateTlsRsaInstallDataSub(uint32_t *InData_SharedKeyIndex, + uint32_t *InData_SessionKey, + uint32_t *InData_IV, + uint32_t *InData_InstData, + uint32_t *OutData_InstData); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateTlsP256EccKeyIndexSub(uint32_t *OutData_KeyIndex, uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateEccRandomKeyIndexSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_GenerateEccP384RandomKeyIndexSub(uint32_t * InData_CurveType, + uint32_t * OutData_PubKeyIndex, + uint32_t * OutData_PrivKeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_GenerateRandomNumberSub(uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void R_SCE_Aes128EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128EncryptDecryptFinalSub(void); + + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256EncryptDecryptInitSub(const uint32_t * InData_KeyType, + const uint32_t * InData_Cmd, + const uint32_t * InData_KeyIndex, + const uint32_t * InData_IV); +void R_SCE_Aes256EncryptDecryptUpdateSub(const uint32_t * InData_Text, + uint32_t * OutData_Text, + const uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256EncryptDecryptFinalSub(void); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Ghash(uint32_t * InData_HV, + uint32_t * InData_IV, + uint32_t * InData_Text, + uint32_t * OutData_DataT, + uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes128GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes128GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes128GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmEncryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes256GcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmEncryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * OutData_Text, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256GcmDecryptInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t * InData_IV); +void R_SCE_Aes256GcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes256GcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataALen, + uint32_t * InData_TextLen, + uint32_t * InData_DataTLen, + uint32_t * OutData_Text); + +void R_SCE_Aes128GcmDecryptUpdateTransitionSub(void); +void R_SCE_Aes128GcmEncryptUpdateTransitionSub(void); +void R_SCE_Aes256GcmDecryptUpdateTransitionSub(void); +void R_SCE_Aes256GcmEncryptUpdateTransitionSub(void); +void R_SCE_Aes128GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes128GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes256GcmEncryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); +void R_SCE_Aes256GcmDecryptUpdateAADSub(uint32_t * InData_DataA, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128CcmEncryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes128CcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CcmEncryptFinalSub(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes128CcmDecryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes128CcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes256CcmEncryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes256CcmEncryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CcmEncryptFinalSub(uint32_t * InData_TextLen, + uint32_t * InData_Text, + uint32_t * OutData_Text, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Aes256CcmDecryptInitSub(uint32_t * InData_KeyType, + uint32_t * InData_KeyIndex, + uint32_t * InData_IV, + uint32_t * InData_Header, + uint32_t Header_Len); +void R_SCE_Aes256CcmDecryptUpdateSub(uint32_t * InData_Text, uint32_t * OutData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CcmDecryptFinalSub(uint32_t * InData_Text, + uint32_t * InData_TextLen, + uint32_t * InData_MAC, + uint32_t * InData_MACLength, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes128CmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex); +void R_SCE_Aes128CmacUpdateSub(uint32_t * InData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes128CmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Aes256CmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex); +void R_SCE_Aes256CmacUpdateSub(uint32_t * InData_Text, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_AUTHENTICATION **/ +fsp_err_t R_SCE_Aes256CmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_Text, + uint32_t * InData_DataT, + uint32_t * InData_DataTLen, + uint32_t * OutData_DataT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Sha224256GenerateMessageDigestSub(const uint32_t * InData_InitVal, + const uint32_t * InData_PaddedMsg, + const uint32_t MAX_CNT, + uint32_t * OutData_MsgDigest); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_Sha256HmacInitSub(uint32_t * InData_KeyType, uint32_t * InData_KeyIndex, uint32_t LEN); +void R_SCE_Sha256HmacUpdateSub(uint32_t * InData_PaddedMsg, uint32_t MAX_CNT); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_Sha256HmacFinalSub(uint32_t * InData_Cmd, + uint32_t * InData_MAC, + uint32_t * InData_length, + uint32_t * OutData_MAC); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsRootCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_Certificates, + uint32_t *InData_CertificatesLength, + uint32_t *InData_Signature, + uint32_t *InData_CertificatesInfo, + uint32_t length, + uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsCertificateVerificationSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_PubKey, + uint32_t *InData_TBSCertificate, + uint32_t *InData_TBSCertificateLength, + uint32_t *InData_Signature, + uint32_t *InData_TBSCertificateInfo, + uint32_t length, + uint32_t *OutData_PubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsEncryptPreMasterSecretSub(uint32_t *InData_PubKey, + uint32_t *InData_PreMasterSecret, + uint32_t *OutData_PreMasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_TlsGeneratePreMasterSecretSub(uint32_t *OutData_PreMasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateMasterSecretSub(uint32_t *InData_Sel_CipherSuite, + uint32_t *InData_PreMasterSecret, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *OutData_MasterSecret); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateSessionKeySub(uint32_t *InData_Sel_CipherSuite, + uint32_t *InData_MasterSecret, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *InData_NonceExplicit, + uint32_t *OutData_ClientMACKeyOperationCode, + uint32_t *OutData_ServerMACKeyOperationCode, + uint32_t *OutData_ClientEncKeyOperationCode, + uint32_t *OutData_ServerEncKeyOperationCode, + uint32_t OutLen); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGenerateVerifyDataSub(uint32_t *InData_Sel_VerifyData, + uint32_t *InData_MasterSecret, + uint32_t *InData_HandShakeHash, + uint32_t *OutData_VerifyData); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsServersEphemeralEcdhPublicKeyRetrievesSub(uint32_t *InData_Sel_PubKeyType, + uint32_t *InData_ClientRandom, + uint32_t *InData_ServerRandom, + uint32_t *InData_Sel_CompressType, + uint32_t *InData_SKE_Message, + uint32_t *InData_SKE_Signature, + uint32_t *InData_PubKey, + uint32_t *OutData_EphemeralPubKey); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_TlsGeneratePreMasterSecretWithEccP256KeySub(uint32_t *InData_PubKey, + uint32_t *InData_KeyIndex, + uint32_t *OutData_PreMasterSecretIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa1024ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa1024ModularExponentDecryptSub(uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa2048ModularExponentDecryptSub(uint32_t * InData_KeyIndex, + const uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa3072ModularExponentEncryptSub(uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t * InData_KeyIndex, + uint32_t * InData_Text, + uint32_t * OutData_Text); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaSignatureGenerateSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * OutData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaP384SignatureGenerateSub(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * OutData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaSignatureVerificationSub(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaNistP256SignatureVerificationSub(uint32_t *InData_KeyIndex, + uint32_t *InData_MsgDgst, + uint32_t *InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_EcdsaP384SignatureVerificationSub(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_MsgDgst, + uint32_t * InData_Signature); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_data, + uint32_t * InData_Signature, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT **/ +fsp_err_t R_SCE_EcdhP256QeuOutputSub(uint32_t *InData_Cmd, + uint32_t *InData_data, + uint32_t *OutData_KeyIndex); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemQevSignatureGenerationSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * InData_key_id, + uint32_t * OutData_data, + uint32_t * OutData_Signature, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_FAIL @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemCalculateZSub(uint32_t * InData_KeyType, + uint32_t * InData_PubKeyIndex, + uint32_t * InData_PrivKeyIndex, + uint32_t * OutData_KeyIndex); + +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL **/ +fsp_err_t R_SCE_DlmsCosemCalculateKekSub(uint32_t *InData_KeyIndexType, + uint32_t * InData_KeyIndex, + uint32_t * InData_KDFType, + uint32_t * InData_PaddedMsg, + uint32_t MAX_CNT, + uint32_t * InData_SaltKeyIndex, + uint32_t * OutData_KeyIndex); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_AesKeyWrapSub(uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + int32_t KEY_INDEX_SIZE, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_WrappedKeyIndex, + uint32_t WRAPPED_KEY_SIZE, + uint32_t * OutData_Text); +/** @retval FSP_SUCCESS @retval FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT @retval FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL @retval FSP_ERR_CRYPTO_SCE_FAIL **/ +fsp_err_t R_SCE_AesKeyUnwrapSub(uint32_t * InData_KeyType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t KEY_INDEX_SIZE, + uint32_t * InData_WrappedKeyType, + uint32_t * InData_Text, + uint32_t WRAPPED_KEY_SIZE, + uint32_t * OutData_KeyIndex); + +void R_SCE_SelfCheck1SubSub(void); +void R_SCE_TlsRootCertificateVerificationSubSub(void); +void R_SCE_TlsGenerateSubSub(void); + +void R_SCE_func000(uint32_t * InData_PaddedMsg, int32_t MAX_CNT); +void R_SCE_func001(void); +void R_SCE_func002(void); +void R_SCE_func003_r1(uint32_t* ARG1); +void R_SCE_func004_r1(uint32_t ARG1); +void R_SCE_func005_r1(uint32_t ARG1); +void R_SCE_func006(void); +void R_SCE_func007(void); +void R_SCE_func008(void); +void R_SCE_func009(void); +void R_SCE_func010_r1(uint32_t ARG1); +void R_SCE_func011(uint32_t * ARG1); +void R_SCE_func022(void); +void R_SCE_func023(void); +void R_SCE_func025_r1(uint32_t ARG1); +void R_SCE_func027_r2(uint32_t ARG1); +void R_SCE_func028_r2(uint32_t ARG1); +void R_SCE_func030(void); +void R_SCE_func040(void); +void R_SCE_func043(void); +void R_SCE_func044(void); +void R_SCE_func048(uint32_t * ARG1); +void R_SCE_func049(uint32_t * ARG1); +void R_SCE_func050(uint32_t ARG1); +void R_SCE_func051(void); +void R_SCE_func052(uint32_t ARG1); +void R_SCE_func053(uint32_t ARG1); +void R_SCE_func054(uint32_t ARG1, uint32_t ARG2); +void R_SCE_func057_r3(uint32_t * ARG1, uint32_t * ARG2, uint32_t * ARG3); +void R_SCE_func059(void); +void R_SCE_func060(void); +void R_SCE_func061(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func062(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func063(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func064(uint32_t ARG1, uint32_t * ARG2); +void R_SCE_func068(void); +void R_SCE_func069(uint32_t* ARG1, uint32_t ARG2); +void R_SCE_func070_r2(uint32_t ARG1); +void R_SCE_func071_r2(uint32_t ARG1); +void R_SCE_func073_r2(uint32_t ARG1); +void R_SCE_func074_r1(void); +void R_SCE_func075_r1(void); +void R_SCE_func076(void); +void R_SCE_func077(void); +void R_SCE_func080(void); +void R_SCE_func081(void); +void R_SCE_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void R_SCE_func103(void); +void R_SCE_func200(void); +void R_SCE_func202(void); +void R_SCE_func205(void); +void R_SCE_func206(void); +void R_SCE_func207(void); +void R_SCE_func300(void); +void R_SCE_func301(void); +void R_SCE_func302(void); +void R_SCE_func303(void); +void R_SCE_func304(void); +void R_SCE_func305(void); +void R_SCE_func307(void); +void R_SCE_func308(void); +void R_SCE_func309(void); +void R_SCE_func310(void); +void R_SCE_func311(void); +void R_SCE_func312(uint32_t ARG1); +void R_SCE_func313(uint32_t ARG1); +void R_SCE_func314(uint32_t ARG1); +void R_SCE_func315(uint32_t ARG1); +void R_SCE_func316(void); +void R_SCE_func317(void); +void R_SCE_func318(void); +void R_SCE_func319(uint32_t ARG1); +void R_SCE_func320(uint32_t ARG1); +void R_SCE_func321(uint32_t ARG1); +void R_SCE_func322(uint32_t ARG1); +void R_SCE_func323(void); +void R_SCE_func324(void); +void R_SCE_func325(void); + +uint32_t change_endian_long(uint32_t data); + +#endif /* R_SCE_PRIVATE_HEADER_FILE */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sdhi/r_sdhi_private.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sdhi/r_sdhi_private.h new file mode 100644 index 00000000..61740cd1 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_sdhi/r_sdhi_private.h @@ -0,0 +1,306 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef SDHI_PRV_R_SDHI_PRIVATE_H +#define SDHI_PRV_R_SDHI_PRIVATE_H + +/********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define SDHI_PRV_CSD_VERSION_1_0 (0U) +#define SDHI_PRV_CSD_VERSION_2_0 (1U) /* value of 1 is CSD 2.0 according to SD spec. */ + +#define SDHI_PRV_CMD_GO_IDLE_STATE (0U) +#define SDHI_PRV_CMD_SEND_OP_COND (1U) +#define SDHI_PRV_CMD_ALL_SEND_CID (2U) +#define SDHI_PRV_CMD_SEND_RELATIVE_ADDR (3U) +#define SDHI_PRV_CMD_SDIO (5U) +#define SDHI_PRV_CMD_SET_BUS_WIDTH (6U) +#define SDHI_PRV_CMD_SWITCH (6U) +#define SDHI_PRV_CMD_SEL_DES_CARD (7U) +#define SDHI_PRV_CMD_IF_COND (8U) +#define SDHI_PRV_CMD_SEND_CSD (9U) +#define SDHI_PRV_CMD_SET_BLOCKLEN (16U) +#define SDHI_PRV_CMD_READ_SINGLE_BLOCK (17U) +#define SDHI_PRV_CMD_READ_MULTIPLE_BLOCK (18U) +#define SDHI_PRV_CMD_WRITE_SINGLE_BLOCK (24U) +#define SDHI_PRV_CMD_WRITE_MULTIPLE_BLOCK (25U) +#define SDHI_PRV_CMD_ERASE_WR_BLK_START (32U) +#define SDHI_PRV_CMD_ERASE_WR_BLK_END (33U) +#define SDHI_PRV_CMD_TAG_ERASE_GROUP_START (0x423U) +#define SDHI_PRV_CMD_TAG_ERASE_GROUP_END (0x424U) +#define SDHI_PRV_CMD_ERASE (38U) +#define SDHI_PRV_CMD_SD_SEND_OP_COND (41U) +#define SDHI_PRV_CMD_IO_RW_DIRECT (52U) +#define SDHI_PRV_CMD_IO_READ_EXT_SINGLE_BLOCK (0x1c35U) +#define SDHI_PRV_CMD_IO_EXT_MULTI_BLOCK (0x6000U) +#define SDHI_PRV_CMD_IO_WRITE_EXT_SINGLE_BLOCK (0x0c35U) + +#define SDHI_PRV_CMD_APP_CMD (55U) +#define SDHI_PRV_CMD_C_ACMD (1U << 6) /* APP Command */ + +#define SDHI_PRV_IF_COND_VOLTAGE (1U) +#define SDHI_PRV_IF_COND_CHECK_PATTERN (0xAAU) + +#define SDHI_PRV_OCR_CAPACITY_HC (1U << 30) + +#define SDHI_PRV_OCR_VDD_2_7_V (1U << 15) +#define SDHI_PRV_OCR_VDD_2_8_V (1U << 16) +#define SDHI_PRV_OCR_VDD_2_9_V (1U << 17) +#define SDHI_PRV_OCR_VDD_3_0_V (1U << 18) +#define SDHI_PRV_OCR_VDD_3_1_V (1U << 19) +#define SDHI_PRV_OCR_VDD_3_2_V (1U << 20) +#define SDHI_PRV_OCR_VDD_3_3_V (1U << 21) +#define SDHI_PRV_OCR_VDD_3_4_V (1U << 22) +#define SDHI_PRV_OCR_VDD_3_5_V (1U << 23) +#define SDHI_PRV_OCR_VDD_SUPPORTED \ + (SDHI_PRV_OCR_VDD_2_7_V | SDHI_PRV_OCR_VDD_2_8_V | SDHI_PRV_OCR_VDD_2_9_V | SDHI_PRV_OCR_VDD_3_0_V | \ + SDHI_PRV_OCR_VDD_3_1_V | \ + SDHI_PRV_OCR_VDD_3_2_V | SDHI_PRV_OCR_VDD_3_3_V | SDHI_PRV_OCR_VDD_3_4_V | SDHI_PRV_OCR_VDD_3_5_V) + +/* CMD52 Arguments */ +#define SDHI_PRV_SDIO_CMD52_READ (0U) +#define SDHI_PRV_SDIO_CMD52_WRITE (1U) + +/* SWITCH command argument's bit postion */ +#define SDHI_PRV_SWITCH_ACCESS_SHIFT (24U) +#define SDHI_PRV_SWITCH_INDEX_SHIFT (16U) +#define SDHI_PRV_SWITCH_VALUE_SHIFT (8U) + +#define SDHI_PRV_EMMC_EXT_CSD_SIZE (512U) + +/* Offsets */ +#define SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET (185U) +#define SDHI_PRV_EMMC_EXT_CSD_DEVICE_TYPE_OFFSET (196U) +#define SDHI_PRV_EMMC_EXT_CSD_SEC_COUNT_OFFSET (212U) + +/* Commands */ +#define SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE (3U) +#define SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT (2U) +#define SDHI_PRV_EMMC_HIGH_SPEED_MODE (((SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE << 24U) | \ + (SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET << 16U)) | \ + (SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT << 8U)) + +#define SDHI_PRV_SD_SWITCH_STATUS_SIZE (64U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_RESPONSE (13U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR_RESPONSE (16U) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR (0x0fU) +#define SDHI_PRV_SD_SWITCH_HIGH_SPEED_OK (0x02U) + +#define SDHI_PRV_EMMC_SEND_OP_COND (0x701U) +#define SDHI_PRV_EMMC_CMD_SWITCH_WBUSY (0x506U) /* eMMC CMD6 switch command "with response busy" */ +#define SDHI_PRV_EMMC_CMD_SEND_EXT_CSD (0x1C08U) /* CMD 8, read data */ +#define SDHI_PRV_EMMC_DEFAULT_CLOCK_RATE (26000000U) /* 26 MHz */ +#define SDHI_PRV_EMMC_HIGH_SPEED_CLOCK_RATE (52000000U) /* 52 MHz */ +#define SDHI_PRV_SD_HIGH_SPEED_MODE_SWITCH (0x80FFFFF1U) /* set SD high speed */ +#define SDHI_PRV_SD_DEFAULT_CLOCK_RATE (25000000U) /* 25 MHz */ +#define SDHI_PRV_SD_HIGH_SPEED_CLOCK_RATE (50000000U) /* 50 MHz */ +#define SDHI_PRV_SDIO_HIGH_SPEED_CLOCK_RATE (50000000U) /* 50 MHz */ + +#define SDHI_PRV_EMMC_ERASE_ARGUMENT_TRIM (1U) + +#define SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS (32) +#define SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS (40) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef enum e_sdmmc_priv_sd_state +{ + SDMMC_PRIV_SD_STATE_IDLE, + SDMMC_PRIV_SD_STATE_READY, + SDMMC_PRIV_SD_STATE_IDENT, + SDMMC_PRIV_SD_STATE_STBY, + SDMMC_PRIV_SD_STATE_TRANSFER, + SDMMC_PRIV_SD_STATE_DATA, + SDMMC_PRIV_SD_STATE_RCV, + SDMMC_PRIV_SD_STATE_PROG, + SDMMC_PRIV_SD_STATE_DIS, + SDMMC_PRIV_SD_STATE_RSVD9, + SDMMC_PRIV_SD_STATE_RSVD10, + SDMMC_PRIV_SD_STATE_RSVD11, + SDMMC_PRIV_SD_STATE_RSVD12, + SDMMC_PRIV_SD_STATE_RSVD13, + SDMMC_PRIV_SD_STATE_RSVD14, + SDMMC_PRIV_SD_STATE_RSVD15 +} sdmmc_priv_sd_state_t; + +/** SDMMC card specific data */ +typedef struct st_sdmmc_priv_csd_reg +{ + union + { + uint8_t array[16]; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + volatile uint32_t sdrsp10; + volatile uint32_t sdrsp32; + volatile uint32_t sdrsp54; + volatile uint32_t sdrsp76; + } reg; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_8 : 2; ///< [9:8] + uint32_t file_format : 2; ///< [11:10] file format + uint32_t tmp_write_protect : 1; ///< [12] temporary write protection + uint32_t perm_write_protect : 1; ///< [13] permanent write protection + uint32_t copy : 1; ///< [14] copy flag + uint32_t file_format_grp : 1; ///< [15] file format group + uint32_t reserved_20 : 5; ///< [16-20] + uint32_t write_bl_partial : 1; ///< [21] partial blocks for write allowed + uint32_t write_bl_len : 4; ///< [25:22] max. write data block length + uint32_t r2w_factor : 3; ///< [28:26] write speed factor + uint32_t reserved_29 : 2; ///< [30:29] + uint32_t wp_grp_enable : 1; ///< [31] write protect group enable + uint32_t wp_grp_size : 7; ///< [38:32] write protect group size + uint32_t sector_size : 7; ///< [45:39] erase sector size + uint32_t erase_blk_en : 1; ///< [46] erase single block enable + uint32_t c_size_mult : 3; ///< [49:47] device size multiplier*/ + uint32_t vdd_w_curr_max : 3; ///< [52:50] max. write current for vdd max + uint32_t vdd_w_curr_min : 3; ///< [55:53] max. write current for vdd min + uint32_t vdd_r_curr_max : 3; ///< [58:56] max. read current for vdd max + uint32_t vdd_r_curr_min : 3; ///< [61:59] max. read current for vdd min + uint32_t c_size : 12; ///< [73:62] device size + uint32_t reserved_74 : 2; ///< [75:74] + uint32_t dsr_imp : 1; ///< [76] dsr implemented + uint32_t read_blk_misalign : 1; ///< [77] read block misalignment + uint32_t write_blk_misalign : 1; ///< [78] write block misalignment + uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed + uint32_t read_bl_len : 4; ///< [83:80] max read data block length + uint32_t ccc : 12; ///< [95:84] card command classes + uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate + uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles + uint32_t taac : 8; ///< [119:112] data read access-time-1 + uint32_t reserved_120 : 6; ///< [125:120] + uint32_t csd_structure : 2; ///< [127:126] csd structure + uint32_t reserved_128 : 8; ///< [135:128] + } csd_v1_b; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_8 : 2; ///< [9:8] + uint32_t file_format : 2; ///< [11:10] file format + uint32_t tmp_write_protect : 1; ///< [12] temporary write protection + uint32_t perm_write_protect : 1; ///< [13] permanent write protection + uint32_t copy : 1; ///< [14] copy flag + uint32_t file_format_grp : 1; ///< [15] file format group + uint32_t reserved_20 : 5; ///< [20:16] + uint32_t write_bl_partial : 1; ///< [21] partial blocks for write allowed + uint32_t write_bl_len : 4; ///< [25:22] max. write data block length + uint32_t r2w_factor : 3; ///< [28:26] write speed factor + uint32_t reserved_29 : 2; ///< [30:29] + uint32_t wp_grp_enable : 1; ///< [31] write protect group enable + uint32_t wp_grp_size : 7; ///< [38:32] write protect group size + uint32_t sector_size : 7; ///< [45:39] erase sector size + uint32_t erase_blk_en : 1; ///< [46] erase single block enable + uint32_t reserved_47 : 1; ///< [47] + uint32_t c_size : 22; ///< [69:48] device size + uint32_t reserved_70 : 6; ///< [75:70] + uint32_t dsr_imp : 1; ///< [76] dsr implemented + uint32_t read_blk_misalign : 1; ///< [77] read block misalignment + uint32_t write_blk_misalign : 1; ///< [78] write block misalignment + uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed + uint32_t read_bl_len : 4; ///< [83:80] max read data block length + uint32_t ccc : 12; ///< [95:84] card command classes + uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate + uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles + uint32_t taac : 8; ///< [119:112] data read access-time-1 + uint32_t reserved_120 : 6; ///< [125:120] + uint32_t csd_structure : 2; ///< [127:126] csd structure + uint32_t reserved_128 : 8; ///< [135:128] + } csd_v2_b; + + /* All structures in this union must be packed since some bitfields span more than one 32-bit word. */ +#if defined(__ICCARM__) + __packed struct +#elif defined(__GNUC__) + struct __attribute__((__packed__)) +#endif + { + uint32_t reserved_0 : 1; + + uint32_t crc : 7; + uint32_t mfg_date : 12; + uint32_t reserved_23 : 4; + uint32_t serial_number : SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS; + uint32_t product_revision : 8; + uint64_t product_name : SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS; + uint32_t oem_id : 16; + uint32_t mfg_id : 8; + uint32_t reserved_128 : 8; + } cid; + }; +} sdmmc_priv_csd_reg_t; + +typedef union u_sdmmc_priv_sdio_arg_t +{ + uint32_t arg; + + struct + { + uint32_t data : 8; /* read/write data */ + uint32_t stuff_8 : 1; /* Stuff bit */ + uint32_t register_address : 17; /* Register Address */ + uint32_t stuff_26 : 1; /* Stuff bit should be set to 1 */ + uint32_t raw : 1; /* 1= Read after write. */ + uint32_t function_number : 3; /* function0~function7 */ + uint32_t rw_flag : 1; /* 0:read, 1:write */ + } cmd_52_arg; + + struct + { + uint32_t count : 9; /* Byte/Block Count */ + uint32_t register_address : 17; /* Register Address */ + uint32_t op_code : 1; /* 0:fixed address, 1:incrementing address */ + uint32_t block_mode : 1; /* 0: Byte, 1:Block */ + uint32_t function_number : 3; /* function0~function7 */ + uint32_t rw_flag : 1; /* 0:read, 1:write */ + } cmd_53_arg; +} sdmmc_priv_sdio_arg_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h new file mode 100644 index 00000000..575f13d5 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h @@ -0,0 +1,912 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef R_USB_BASIC_DEFINE_H + #define R_USB_BASIC_DEFINE_H + + #include "r_usb_basic_cfg.h" + + #define USB_CFG_LITTLE (0U) + #define USB_CFG_BIG (1U) + + #define USB_CFG_ENDIAN (USB_CFG_LITTLE) + + #if defined(USB_DEBUG_ON) + #include /* @@@MISRA del */ + #include /* @@@MISRA del */ + #endif /* defined(USB_DEBUG_ON) */ + + #ifdef __cplusplus +extern "C" { + #endif + + #define R_USB_HmscTask usb_hmsc_task + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Version Number of API. */ + #define USB_VERSION_MAJOR (1) + #define USB_VERSION_MINOR (0) + + #define CLSDATASIZE (512U) /* Transfer data size for Standard Request */ + #if (BSP_CFG_RTOS != 0) + +/* The buffer size of interrupt info is increased to avoid overlapping interrupt events. */ + #define USB_INT_BUFSIZE (32U) /* Size of Interrupt info buffer */ + #else /* #if (BSP_CFG_RTOS != 0) */ + #define USB_INT_BUFSIZE (10U) /* Size of Interrupt info buffer */ + #endif /* #if (BSP_CFG_RTOS != 0) */ + #define USB_EVENT_MAX (10) + +/* Scheduler use define */ + #define USB_TBLCLR (0U) /* Table clear */ + #define USB_CNTCLR (0U) /* Counter clear */ + #define USB_FLGCLR (0U) /* Flag clear */ + #define USB_FLGSET (1U) /* Flag set */ + #define USB_IDCLR (0xFFU) /* Priority clear */ + +/* Task ID define */ + #define USB_TID_0 (0U) /* Task ID 0 */ + #define USB_TID_1 (1U) /* Task ID 1 */ + #define USB_TID_2 (2U) /* Task ID 2 */ + #define USB_TID_3 (3U) /* Task ID 3 */ + #define USB_TID_4 (4U) /* Task ID 4 */ + #define USB_TID_5 (5U) /* Task ID 5 */ + #define USB_TID_6 (6U) /* Task ID 6 */ + #define USB_TID_7 (7U) /* Task ID 7 */ + #define USB_TID_8 (8U) /* Task ID 8 */ + #define USB_TID_9 (9U) /* Task ID 9 */ + #define USB_TID_10 (10U) /* Task ID 9 */ + +/* Task priority define */ + #define USB_PRI_0 (0U) /* Priority 0 */ + #define USB_PRI_1 (1U) /* Priority 1 */ + #define USB_PRI_2 (2U) /* Priority 2 */ + #define USB_PRI_3 (3U) /* Priority 3 */ + #define USB_PRI_4 (4U) /* Priority 4 */ + #define USB_PRI_5 (5U) /* Priority 5 */ + #define USB_PRI_6 (6U) /* Priority 6 */ + +/* Host Control Driver Task */ + #define USB_HCD_TSK (USB_TID_1) /* Task ID */ + #define USB_HCD_MBX (USB_HCD_TSK) /* Mailbox ID */ + #define USB_HCD_MPL (USB_HCD_TSK) /* Memory pool ID */ + +/* Host Manager Task */ + #define USB_MGR_TSK (USB_TID_2) /* Task ID */ + #define USB_MGR_MBX (USB_MGR_TSK) /* Mailbox ID */ + #define USB_MGR_MPL (USB_MGR_TSK) /* Memory pool ID */ + +/* Hub Task */ + #define USB_HUB_TSK (USB_TID_3) /* Task ID */ + #define USB_HUB_MBX (USB_HUB_TSK) /* Mailbox ID */ + #define USB_HUB_MPL (USB_HUB_TSK) /* Memory pool ID */ + + #if (BSP_CFG_RTOS != 0) + +/* Class Request for Internal Communication */ + #define USB_CLS_TSK (USB_TID_4) /* Task ID */ + #define USB_CLS_MBX (USB_CLS_TSK) /* Mailbox ID */ + #define USB_CLS_MPL (USB_CLS_TSK) /* Memory pool ID */ + +/* Peripheral Control Driver Task */ + #define USB_PCD_TSK (USB_TID_5) /* Task ID */ + #define USB_PCD_MBX (USB_PCD_TSK) /* Mailbox ID */ + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* Error discrimination */ + #define USB_DEBUG_HOOK_HWR (0x0100) + #define USB_DEBUG_HOOK_HOST (0x0200) + #define USB_DEBUG_HOOK_PERI (0x0400) + #define USB_DEBUG_HOOK_STD (0x0800) + #define USB_DEBUG_HOOK_CLASS (0x1000) + #define USB_DEBUG_HOOK_APL (0x2000) + +/* Error Code */ + #define USB_DEBUG_HOOK_CODE1 (0x0001) + #define USB_DEBUG_HOOK_CODE2 (0x0002) + #define USB_DEBUG_HOOK_CODE3 (0x0003) + #define USB_DEBUG_HOOK_CODE4 (0x0004) + #define USB_DEBUG_HOOK_CODE5 (0x0005) + #define USB_DEBUG_HOOK_CODE6 (0x0006) + #define USB_DEBUG_HOOK_CODE7 (0x0007) + #define USB_DEBUG_HOOK_CODE8 (0x0008) + #define USB_DEBUG_HOOK_CODE9 (0x0009) + #define USB_DEBUG_HOOK_CODE10 (0x000A) + #define USB_DEBUG_HOOK_CODE11 (0x000B) + #define USB_DEBUG_HOOK_CODE12 (0x000C) + #define USB_DEBUG_HOOK_CODE13 (0x000D) + #define USB_DEBUG_HOOK_CODE14 (0x000E) + #define USB_DEBUG_HOOK_CODE15 (0x000F) + + #ifdef USB_DEBUG_HOOK_USE + #define USB_DEBUG_HOOK(x) (usb_cstd_debug_hook(x)) + #else + #define USB_DEBUG_HOOK(x) + #endif + +/* H/W function type */ + #define USB_BIT0 ((uint16_t) 0x0001) + #define USB_BIT1 ((uint16_t) 0x0002) + #define USB_BIT2 ((uint16_t) 0x0004) + #define USB_BIT3 ((uint16_t) 0x0008) + #define USB_BIT4 ((uint16_t) 0x0010) + #define USB_BIT5 ((uint16_t) 0x0020) + #define USB_BIT6 ((uint16_t) 0x0040) + #define USB_BIT7 ((uint16_t) 0x0080) + #define USB_BIT8 ((uint16_t) 0x0100) + #define USB_BIT9 ((uint16_t) 0x0200) + #define USB_BIT10 ((uint16_t) 0x0400) + #define USB_BIT11 ((uint16_t) 0x0800) + #define USB_BIT12 ((uint16_t) 0x1000) + #define USB_BIT13 ((uint16_t) 0x2000) + #define USB_BIT14 ((uint16_t) 0x4000) + #define USB_BIT15 ((uint16_t) 0x8000) + #define USB_BITSET(x) ((uint16_t) ((uint16_t) 1 << (x))) + +/* nonOS Use */ + #define USB_SEQ_0 ((uint16_t) 0x0000) + #define USB_SEQ_1 ((uint16_t) 0x0001) + #define USB_SEQ_2 ((uint16_t) 0x0002) + #define USB_SEQ_3 ((uint16_t) 0x0003) + #define USB_SEQ_4 ((uint16_t) 0x0004) + #define USB_SEQ_5 ((uint16_t) 0x0005) + #define USB_SEQ_6 ((uint16_t) 0x0006) + #define USB_SEQ_7 ((uint16_t) 0x0007) + #define USB_SEQ_8 ((uint16_t) 0x0008) + #define USB_SEQ_9 ((uint16_t) 0x0009) + #define USB_SEQ_10 ((uint16_t) 0x000a) + +/* USB HUB PIPE No. */ + #define USB_HUB_PIPE (9U) + + #define USB_HUB_P1 ((uint16_t) 0x0001) + #define USB_HUB_P2 ((uint16_t) 0x0002) + #define USB_HUB_P3 ((uint16_t) 0x0003) + #define USB_HUB_P4 ((uint16_t) 0x0004) + + #define USB_HUB (USB_CLASS_REQUEST + 1) + +/* Interrupt message num */ + #define USB_INTMSGMAX ((uint16_t) 15U) + +/* USB Device Connect */ + #define USB_DEV_NO_CONNECT ((uint16_t) 0U) + #define USB_DEV_CONNECTED ((uint16_t) 1U) + + #define USB_OK (0U) + #define USB_ERROR (0xff) + #define USB_ERR_TMOUT (0xfe) + #define USB_ERR_FIFO_ACCESS (0xfd) + #define USB_QOVR (0xd5) /* Submit overlap error */ + #define USB_PAR (0xef) /* parameter error */ + + #define USB_TRUE (1U) + #define USB_FALSE (0U) + + #define USB_YES (1U) + #define USB_NO (0U) + + #define USB_CFG_HIGH (0U) + #define USB_CFG_LOW (1U) + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/* The number of USBIP */ + #define USB_NUM_USBIP (2U) + +/* USB module definition */ + #define USB_M0 (R_USB_FS0) + + #ifdef R_USB_HS0 + #define USB_M1 (R_USB_HS0) + #else /* R_USB_HS0 */ + #ifndef R_USB_HS0_BASE + #if defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) + #define R_USB_HS0_BASE (0x40111000) + #else /* defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) */ + #define R_USB_HS0_BASE (0x40060000) + #endif /* defined(BSP_MCU_GROUP_RA4M3) || defined(BSP_MCU_GROUP_RA6M4) */ + #endif /* R_USB_HS0_BASE */ + + #define USB_M1 (((R_USB_FS0_Type *) R_USB_HS0_BASE)) + #endif /* R_USB_HS0 */ + +/* FIFO port register default access size */ + #define USB0_CFIFO_MBW (USB_MBW_16) + #define USB0_D0FIFO_MBW (USB_MBW_16) + #define USB0_D1FIFO_MBW (USB_MBW_16) + + #define USB1_CFIFO_MBW (USB_MBW_32) + #define USB1_D0FIFO_MBW (USB_MBW_32) + #define USB1_D1FIFO_MBW (USB_MBW_32) + +/* Start Pipe No */ + #if defined(BSP_MCU_GROUP_RA2A1) + #define USB_MIN_PIPE_NO (4U) + #define USB_MAXPIPE_BULK (5U) + #define USB_BULK_PIPE_START (4U) + #define USB_INT_PIPE_END (7U) + #define USB_MAX_PIPE_NO (7U) /* PIPE4 ... PIPE7 */ + #else + #define USB_MIN_PIPE_NO (1U) + #define USB_MAXPIPE_BULK (5U) + #define USB_BULK_PIPE_START (1U) + #define USB_INT_PIPE_END (9U) + #define USB_MAX_PIPE_NO (9U) /* PIPE0 ... PIPE9 */ + #endif + + #define USB_MAXPIPE_NUM (9U) + #define USB_INT_PIPE_START (6U) + #define USB_BULK_PIPE_END (5U) + + #define USB_ISO_PIPE_START (1U) + #define USB_ISO_PIPE_END (2U) + #define USB_MAXPIPE_ISO (2U) + +/* SPEED mode */ + #define USB_HS_DISABLE ((uint16_t) 0U) + #define USB_HS_ENABLE ((uint16_t) 1U) + + #define USBA_ADDRESS_OFFSET (0x0010) + #define USB_ADDRESS_MASK (0x000f) + #define USB_IP_MASK (0x00f0) + +/* USB Device address define */ + #define USB_DEVICEADDR (1U) /* PORT0 USB Address (1 to 10) */ + +/* HUB Address */ + #define USB_HUBDPADDR ((uint16_t) (USB_DEVICEADDR + 1U)) + + #define USB_PIPE_DIR_IN (0U) + #define USB_PIPE_DIR_OUT (1U) + #define USB_PIPE_DIR_MAX (2U) + + #define USB_CFG_ENABLE (1U) + #define USB_CFG_DISABLE (0U) + + #define USB_CFG_IP0 (0) + #define USB_CFG_IP1 (1) + #define USB_CFG_MULTI (2) + + #define USB_CFG_HOST (1) + #define USB_CFG_PERI (2) + + #define USB_CFG_CDC (0) + #define USB_CFG_VEN (1) + + #define USB_CFG_24MHZ (0) + #define USB_CFG_20MHZ (1) + #define USB_CFG_OTHER (2) + #define USB_CFG_12MHZ (3) + +/* Channel Number */ + #define USB_CFG_CH0 (0U) + #define USB_CFG_CH1 (1U) + #define USB_CFG_CH2 (2U) + #define USB_CFG_CH3 (3U) + #define USB_CFG_CH4 (4U) + #define USB_CFG_CH5 (5U) + #define USB_CFG_CH6 (6U) + #define USB_CFG_CH7 (7U) + +/* Bus Wait */ + #define USB_CFG_BUSWAIT_0 (USB_BWAIT_0) + #define USB_CFG_BUSWAIT_1 (USB_BWAIT_1) + #define USB_CFG_BUSWAIT_2 (USB_BWAIT_2) + #define USB_CFG_BUSWAIT_3 (USB_BWAIT_3) + #define USB_CFG_BUSWAIT_4 (USB_BWAIT_4) + #define USB_CFG_BUSWAIT_5 (USB_BWAIT_5) + #define USB_CFG_BUSWAIT_6 (USB_BWAIT_6) + #define USB_CFG_BUSWAIT_7 (USB_BWAIT_7) + #define USB_CFG_BUSWAIT_8 (USB_BWAIT_8) + #define USB_CFG_BUSWAIT_9 (USB_BWAIT_9) + #define USB_CFG_BUSWAIT_10 (USB_BWAIT_10) + #define USB_CFG_BUSWAIT_11 (USB_BWAIT_11) + #define USB_CFG_BUSWAIT_12 (USB_BWAIT_12) + #define USB_CFG_BUSWAIT_13 (USB_BWAIT_13) + #define USB_CFG_BUSWAIT_14 (USB_BWAIT_14) + #define USB_CFG_BUSWAIT_15 (USB_BWAIT_15) + + #define USB_CFG_USE (0U) + #define USB_CFG_NOUSE (0xFFFFU) + + #define USB_CFG_ON (1U) + #define USB_CFG_OFF (0U) + + #define USB_CFG_FS (1) + #define USB_CFG_HS (2) + +/****************************************************************************** + * USB specification define + ******************************************************************************/ + +/* Standard Device Descriptor Define */ + #define USB_DEV_B_LENGTH (0U) /* Size of descriptor */ + #define USB_DEV_B_DESCRIPTOR_TYPE (1U) /* Descriptor type */ + #define USB_DEV_BCD_USB_L (2U) /* USB Specification Release Number */ + #define USB_DEV_BCD_USB_H (3U) /* USB Specification Release Number */ + #define USB_DEV_B_DEVICE_CLASS (4U) /* Class code */ + #define USB_DEV_B_DEVICE_SUBCLASS (5U) /* Subclass code */ + #define USB_DEV_B_DEVICE_PROTOCOL (6U) /* Protocol code */ + #define USB_DEV_B_MAX_PACKET_SIZE_0 (7U) /* Max packet size for EP0(only 8,16,32,64 are valid) */ + #define USB_DEV_ID_VENDOR_L (8U) /* Vendor ID */ + #define USB_DEV_ID_VENDOR_H (9U) /* Vendor ID */ + #define USB_DEV_ID_PRODUCT_L (10U) /* Product ID */ + #define USB_DEV_ID_PRODUCT_H (11U) /* Product ID */ + #define USB_DEV_BCD_DEVICE_L (12U) /* Device release number */ + #define USB_DEV_BCD_DEVICE_H (13U) /* Device release number */ + #define USB_DEV_I_MANUFACTURER (14U) /* Index of string descriptor describing manufacturer */ + #define USB_DEV_I_PRODUCT (15U) /* Index of string descriptor describing product */ + #define USB_DEV_I_SERIAL_NUMBER (16U) /* Device serial number */ + #define USB_DEV_B_NUM_CONFIGURATION (17U) /* Number of possible configuration */ + +/* Standard Configuration Descriptor Define */ + #define USB_DEV_W_TOTAL_LENGTH_L (2U) /* Total length of data returned for this configuration */ + #define USB_DEV_W_TOTAL_LENGTH_H (3U) /* Total length of data returned for this configuration */ + #define USB_DEV_B_NUM_INTERFACES (4U) /* Number of interfaces supported by this configuration */ + #define USB_DEV_B_CONFIGURATION_VALUE (5U) /* Configuration value */ + #define USB_DEV_I_CONFIGURATION (6U) /* Index of string descriptor describing this configuration */ + #define USB_DEV_BM_ATTRIBUTES (7U) /* Configuration characteristics */ + #define USB_DEV_B_MAX_POWER (8U) /* Max power consumption of the USB device from the bus */ + +/* Endpoint Descriptor Define */ + #define USB_EP_DIRMASK (0x80U) /* Endpoint direction mask [2] */ + #define USB_EP_NUMMASK (0x0FU) /* Endpoint number mask [2] */ + #define USB_EP_USGMASK (0x30U) /* Usage type mask [2] */ + #define USB_EP_SYNCMASK (0x0CU) /* Synchronization type mask [2] */ + #define USB_EP_TRNSMASK (0x03U) /* Transfer type mask [2] */ + #define USB_EP_CNTRL (0x00U) /* Control Transfer */ + + #define USB_EP_B_LENGTH (0U) /* Size of descriptor */ + #define USB_EP_B_DESCRIPTORTYPE (1U) /* Descriptor type */ + #define USB_EP_B_ENDPOINTADDRESS (2U) /* Endpoint No. , Dir */ + #define USB_EP_B_ATTRIBUTES (3U) /* Transfer Type */ + #define USB_EP_B_MAXPACKETSIZE_L (4U) /* Max packet size */ + #define USB_EP_B_MAXPACKETSIZE_H (5U) /* Max packet size */ + #define USB_EP_B_INTERVAL (6U) /* Interval */ + +/* Standard Interface Descriptor Offset Define */ + #define USB_IF_B_INTERFACENUMBER (2U) /* bInterfaceNumber */ + #define USB_IF_B_ALTERNATESETTING (3U) /* bAlternateSetting */ + #define USB_IF_B_NUMENDPOINTS (4U) /* bNumEndpoints */ + #define USB_IF_B_INTERFACECLASS (5U) /* bInterfaceClass */ + #define USB_IF_B_INTERFACESUBCLASS (6U) /* bInterfaceSubClass @@*/ + #define USB_IF_B_INTERFACEPROTOCOL (7U) /* bInterfacePtorocol */ + #define USB_IF_I_INTERFACE (8U) /* iInterface */ + +/* GET_STATUS request information */ +/* Standard Device status */ + #define USB_GS_BUSPOWERD (0x0000U) + #define USB_GS_SELFPOWERD (0x0001U) + #define USB_GS_REMOTEWAKEUP (0x0002U) + +/* Endpoint status */ + #define USB_GS_NOTHALT (0x0000U) + #define USB_GS_HALT (0x0001U) + +/* CLEAR_FEATURE/GET_FEATURE/SET_FEATURE request information */ +/* Standard Feature Selector */ + #define USB_ENDPOINT_HALT (0x0000U) + #define USB_DEV_REMOTE_WAKEUP (0x0001U) + #define USB_TEST_MODE (0x0002U) + +/* GET_DESCRIPTOR/SET_DESCRIPTOR request information */ +/* Standard Descriptor type */ + #define USB_HUB_DESCRIPTOR (0x0000U) + #define USB_DEV_DESCRIPTOR (0x0100U) + #define USB_CONF_DESCRIPTOR (0x0200U) + #define USB_STRING_DESCRIPTOR (0x0300U) + #define USB_INTERFACE_DESCRIPTOR (0x0400U) + #define USB_ENDPOINT_DESCRIPTOR (0x0500U) + #define USB_DEV_QUALIFIER_DESCRIPTOR (0x0600U) + #define USB_OTHER_SPEED_CONF_DESCRIPTOR (0x0700U) + #define USB_INTERFACE_POWER_DESCRIPTOR (0x0800U) + + #define USB_OTG_SELECTOR (0xF000U) + #define B_HNP_ENABLE (0x3U) + #define A_HNP_SUPPORT (0x4U) + +/* HUB CLASS REQUEST */ + #define USB_HUB_CLEAR_TT_BUFFER (0x0800U) + #define USB_HUB_RESET_TT (0x0900U) + #define USB_HUB_GET_TT_STATE (0x0A00U) + #define USB_HUB_STOP_TT (0x0B00U) + +/* HUB CLASS FEATURE SELECTER */ + #define USB_HUB_C_HUB_LOCAL_POWER (0x0000U) + #define USB_HUB_C_HUB_OVER_CURRENT (0x0001U) + #define USB_HUB_PORT_CONNECTION (0x0000U) + #define USB_HUB_PORT_ENABLE (0x0001U) + #define USB_HUB_PORT_SUSPEND (0x0002U) + #define USB_HUB_PORT_OVER_CURRENT (0x0003U) + #define USB_HUB_PORT_RESET (0x0004U) + #define USB_HUB_PORT_POWER (0x0008U) + #define USB_HUB_PORT_LOW_SPEED (0x0009U) + #define USB_HUB_PORT_HIGH_SPEED (0x000AU) + #define USB_HUB_C_PORT_CONNECTION (0x0010U) + #define USB_HUB_C_PORT_ENABLE (0x0011U) + #define USB_HUB_C_PORT_SUSPEND (0x0012U) + #define USB_HUB_C_PORT_OVER_CURRENT (0x0013U) + #define USB_HUB_C_PORT_RESET (0x0014U) + #define USB_HUB_PORT_TEST (0x0015U) + #define USB_HUB_PORT_INDICATOR (0x0016U) + +/* HUB PORT STAUS */ + #define USB_HUB_STS_PORT_CONNECT (0x0001U) + #define USB_HUB_STS_PORT_ENABLE (0x0002U) + #define USB_HUB_STS_PORT_SUSPEND (0x0004U) + #define USB_HUB_STS_PORT_OVRCURRNET (0x0008U) + #define USB_HUB_STS_PORT_RESET (0x0010U) + #define USB_HUB_STS_PORT_POWER (0x0100U) + #define USB_HUB_STS_PORT_LOWSPEED (0x0200U) + #define USB_HUB_STS_PORT_FULLSPEED (0x0000U) + #define USB_HUB_STS_PORT_HIGHSPEED (0x0400U) + #define USB_HUB_STS_PORT_TEST (0x0800U) + #define USB_HUB_STS_PORT_INDICATOR (0x1000U) + +/* HUB PORT CHANGE */ + #define USB_HUB_CHG_PORT_CONNECT (0x0001U) + #define USB_HUB_CHG_PORT_ENABLE (0x0002U) + #define USB_HUB_CHG_PORT_SUSPEND (0x0004U) + #define USB_HUB_CHG_PORT_OVRCURRNET (0x0008U) + #define USB_HUB_CHG_PORT_RESET (0x0010U) + +/* Device connect information */ + #define USB_ATTACH (0x0040U) + #define USB_ATTACHL (0x0041U) + #define USB_ATTACHF (0x0042U) + #define USB_DETACH (0x0043U) + +/* Reset Handshake result */ + #define USB_NOCONNECT (0x0000U) /* Speed undecidedness */ + #define USB_HSCONNECT (0x00C0U) /* Hi-Speed connect */ + #define USB_FSCONNECT (0x0080U) /* Full-Speed connect */ + #define USB_LSCONNECT (0x0040U) /* Low-Speed connect */ + +/* Pipe define */ + #define USB_USEPIPE (0x00FEU) + #define USB_PERIPIPE (0x00FDU) + #define USB_CLRPIPE (0x00FCU) /* Clear Pipe registration */ + +/* Pipe configuration table define */ + #define USB_EPL (6U) /* Pipe configuration table length */ + #define USB_TYPFIELD (0xC000U) /* Transfer type */ + #define USB_PERIODIC (0x8000U) /* Periodic pipe */ + #define USB_TYPFIELD_ISO (0xC000U) /* Isochronous */ + #define USB_TYPFIELD_INT (0x8000U) /* Interrupt */ + #define USB_TYPFIELD_BULK (0x4000U) /* Bulk */ + #define USB_TYPFIELD_NOUSE (0x2000U) /* Not Used Pipe */ + #define USB_NOUSE (0x0000U) /* Not configuration */ + #define USB_BFREFIELD (0x0400U) /* Buffer ready interrupt mode select */ + #define USB_BFREON (0x0400U) + #define USB_BFREOFF (0x0000U) + #define USB_DBLBFIELD (0x0200U) /* Double buffer mode select */ + #define USB_CFG_DBLBON (0x0200U) + #define USB_CFG_DBLBOFF (0x0000U) + #define USB_CNTMDFIELD (0x0100U) /* Continuous transfer mode select */ + #define USB_CFG_CNTMDON (0x0100U) + #define USB_CFG_CNTMDOFF (0x0000U) + #define USB_SHTNAKFIELD (0x0080U) /* Transfer end NAK */ + #define USB_DIRFIELD (0x0010U) /* Transfer direction select */ + #define USB_DIR_H_OUT (0x0010U) /* HOST OUT */ + #define USB_DIR_P_IN (0x0010U) /* PERI IN */ + #define USB_DIR_H_IN (0x0000U) /* HOST IN */ + #define USB_DIR_P_OUT (0x0000U) /* PERI OUT */ + #define USB_BUF2FIFO (0x0010U) /* Buffer --> FIFO */ + #define USB_FIFO2BUF (0x0000U) /* FIFO --> buffer */ + #define USB_EPNUMFIELD (0x000FU) /* Endpoint number select */ + #define USB_MAX_EP_NO (15U) /* EP0 EP1 ... EP15 */ + #define USB_ENDPOINT_DIRECTION (0x0080U) /* EndPoint Address direction */ + + #define USB_BUF_SIZE(x) ((uint16_t) (((x) / 64U) - 1U) << 10U) + #define USB_BUF_NUMB(x) (x) + + #define USB_IFISFIELD (0x1000U) /* Isochronous in-buf flash mode */ + #define USB_IFISON (0x1000U) + #define USB_IFISOFF (0x0000U) + #define USB_IITVFIELD (0x0007U) /* Isochronous interval */ + #define USB_IITV_TIME(x) (x) + +/* FIFO port & access define */ + #define USB_CUSE (0U) /* CFIFO trans */ + #define USB_D0USE (1U) /* D0FIFO trans */ + #define USB_D1USE (2U) /* D1FIFO trans */ + #define USB_FIFO_ACCESS_NUM_MAX (3U) /* MAX number for FIFO port define */ + +/****************************************************************************** + * Another define + ******************************************************************************/ + +/* FIFO read / write result */ + #define USB_FIFOERROR (USB_ERROR) /* FIFO not ready */ + #define USB_WRITEEND (0x0000U) /* End of write (but packet may not be outputting) */ + #define USB_WRITESHRT (0x0001U) /* End of write (send short packet) */ + #define USB_WRITING (0x0002U) /* Write continues */ + #define USB_READEND (0x0000U) /* End of read */ + #define USB_READSHRT (0x0001U) /* Insufficient (receive short packet) */ + #define USB_READING (0x0002U) /* Read continues */ + #define USB_READOVER (0x0003U) /* Buffer size over */ + +/* Pipe define table end code */ + #define USB_PDTBLEND (0xFFFFU) /* End of table */ + +/* Transfer status Type */ + #define USB_CTRL_END (0U) + #define USB_DATA_NONE (1U) + #define USB_DATA_WAIT (2U) + #define USB_DATA_OK (3U) + #define USB_DATA_SHT (4U) + #define USB_DATA_OVR (5U) + #define USB_DATA_STALL (6U) + #define USB_DATA_ERR (7U) + #define USB_DATA_STOP (8U) + #define USB_DATA_TMO (9U) + #define USB_CTRL_READING (17U) + #define USB_CTRL_WRITING (18U) + #define USB_DATA_READING (19U) + #define USB_DATA_WRITING (20U) + #define USB_DATA_FIFO_ERR (21U) + +/* Utr member (segment) */ + #define USB_TRAN_CONT (0x00U) + #define USB_TRAN_END (0x80U) + +/* Callback argument */ + #define USB_NO_ARG (0U) + +/* USB interrupt type (common)*/ + #define USB_INT_UNKNOWN (0x0000U) + #define USB_INT_BRDY (0x0001U) + #define USB_INT_BEMP (0x0002U) + #define USB_INT_NRDY (0x0003U) + #define USB_INT_DXFIFO (0x0004U) /* BSP_CFG_RTOS == 2 */ + +/* USB interrupt type (PERI)*/ + #define USB_INT_VBINT (0x0011U) + #define USB_INT_RESM (0x0012U) + #define USB_INT_SOFR (0x0013U) + #define USB_INT_DVST (0x0014U) + #define USB_INT_CTRT (0x0015U) + #define USB_INT_ATTACH (0x0016U) + #define USB_INT_DETACH (0x0017U) + +/* USB interrupt type (HOST)*/ + #define USB_INT_OVRCR0 (0x0041U) + #define USB_INT_BCHG0 (0x0042U) + #define USB_INT_DTCH0 (0x0043U) + #define USB_INT_ATTCH0 (0x0044U) + #define USB_INT_EOFERR0 (0x0045U) + #define USB_INT_PDDETINT0 (0x0046U) + #define USB_INT_OVRCR1 (0x0051U) + #define USB_INT_BCHG1 (0x0052U) + #define USB_INT_ATTCH1 (0x0053U) + #define USB_INT_DTCH1 (0x0054U) + #define USB_INT_EOFERR1 (0x0055U) + #define USB_INT_SACK (0x0061U) + #define USB_INT_SIGN (0x0062U) + +/* USB interrupt type (OTG)*/ + #define USB_INT_OTG_HOST_INIT (0x0071U) + + #define USB_UACTON (1U) + #define USB_UACTOFF (0U) + #define USB_VBON (1U) + #define USB_VBOFF (0U) + + #define USB_NOVENDOR (0xFFFFU) /* Vendor ID no check */ + #define USB_NOPRODUCT (0xFFFFU) /* Product ID no check */ + + #define USB_INTFCLSHET (0xAAU) /* Host electrical test class */ + +/* Root port */ + #define USB_NOPORT (0xFFFFU) /* Not connect */ + +/* Condition compilation by the difference of IP */ + #define USB_MAXDEVADDR (5U) + + #define USB_DEVICE_0 (0x0000U) /* Device address 0 */ + #define USB_DEVICE_1 (0x1000U) /* Device address 1 */ + #define USB_DEVICE_2 (0x2000U) /* Device address 2 */ + #define USB_DEVICE_3 (0x3000U) /* Device address 3 */ + #define USB_DEVICE_4 (0x4000U) /* Device address 4 */ + #define USB_DEVICE_5 (0x5000U) /* Device address 5 */ + #define USB_DEVICE_6 (0x6000U) /* Device address 6 */ + #define USB_DEVICE_7 (0x7000U) /* Device address 7 */ + #define USB_DEVICE_8 (0x8000U) /* Device address 8 */ + #define USB_DEVICE_9 (0x9000U) /* Device address 9 */ + #define USB_DEVICE_A (0xA000U) /* Device address A */ + #define USB_NODEVICE (0xF000U) /* No device */ + #define USB_DEVADDRBIT (12U) + +/* DCP Max packet size */ + #define USB_MAXPFIELD (0x007FU) /* Max packet size of DCP */ + +/****************************************************************************** + * Another define + ******************************************************************************/ + +/* ControlPipe Max Packet size */ + #define USB_DEFPACKET (0x0040U) /* Default DCP Max packet size */ + +/* Device state define */ + #define USB_NONDEVICE (0U) + #define USB_NOTTPL (1U) + #define USB_DEVICEENUMERATION (3U) + #define USB_COMPLETEPIPESET (10U) + +/* Control Transfer Stage */ + #define USB_IDLEST (0U) /* Idle */ + #define USB_SETUPNDC (1U) /* Setup Stage No Data Control */ + #define USB_SETUPWR (2U) /* Setup Stage Control Write */ + #define USB_SETUPRD (3U) /* Setup Stage Control Read */ + #define USB_DATAWR (4U) /* Data Stage Control Write */ + #define USB_DATARD (5U) /* Data Stage Control Read */ + #define USB_STATUSRD (6U) /* Status stage */ + #define USB_STATUSWR (7U) /* Status stage */ + #define USB_SETUPWRCNT (17U) /* Setup Stage Control Write */ + #define USB_SETUPRDCNT (18U) /* Setup Stage Control Read */ + #define USB_DATAWRCNT (19U) /* Data Stage Control Write */ + #define USB_DATARDCNT (20U) /* Data Stage Control Read */ + +/****************************************************************************** + * HUB define + ******************************************************************************/ + +/* HUB spec */ + #define USB_FSHUB (1U) + #define USB_HSHUBS (2U) + #define USB_HSHUBM (3U) + +/* Interface number */ + #define USB_HUB_INTNUMFS (1U) + #define USB_HUB_INTNUMHSS (1U) + #define USB_HUB_INTNUMHSM (1U) + +/* USB Manager mode */ + #define USB_PORTOFF (0U) /* Disconnect(VBUSoff) */ + #define USB_DETACHED (10U) /* Disconnect(VBUSon) */ + #define USB_ATTACHED (20U) /* Disconnect(HUBdiconfigured) */ + #define USB_POWERED (30U) /* Start reset handshake */ + #define USB_DEFAULT (40U) /* Set device address */ + #define USB_ADDRESS (50U) /* Enumeration start */ + #define USB_ENUMERATION (60U) /* Wait device enumeration */ + #define USB_CONFIGURED (70U) /* Detach detected */ + #define USB_SUSPENDED (80U) /* Device suspended */ + #define USB_DETACH_PROCESS (101U) /* Wait device detach */ + #define USB_SUSPENDED_PROCESS (102U) /* Wait device suspend */ + #define USB_RESUME_PROCESS (103U) /* Wait device resume */ + +/* HCD common task message command */ + #define USB_MSG_HCD_ATTACH (0x0101U) + #define USB_MSG_HCD_DETACH (0x0102U) + #define USB_MSG_HCD_USBRESET (0x0103U) + #define USB_MSG_HCD_SUSPEND (0x0104U) + #define USB_MSG_HCD_RESUME (0x0105U) + #define USB_MSG_HCD_REMOTE (0x0106U) + #define USB_MSG_HCD_VBON (0x0107U) + #define USB_MSG_HCD_VBOFF (0x0108U) + #define USB_MSG_HCD_CLR_STALL (0x0109U) + #define USB_MSG_HCD_DETACH_MGR (0x010AU) + #define USB_MSG_HCD_ATTACH_MGR (0x010BU) + + #define USB_MSG_HCD_CLR_STALL_RESULT (0x010CU) + #define USB_MSG_HCD_CLR_STALLBIT (0x010DU) + #define USB_MSG_HCD_SQTGLBIT (0x010FU) + +/* HCD task message command */ + #define USB_MSG_HCD_SETDEVICEINFO (0x0111U) + #define USB_MSG_HCD_SUBMITUTR (0x0112U) + #define USB_MSG_HCD_TRANSEND1 (0x0113U) + #define USB_MSG_HCD_TRANSEND2 (0x0114U) + #define USB_MSG_HCD_CLRSEQBIT (0x0115U) + #define USB_MSG_HCD_SETSEQBIT (0x0116U) + #define USB_MSG_HCD_INT (0x0117U) + #define USB_MSG_HCD_DMAINT (0x0119U) + + #define USB_MSG_HCD_OTG_SUSPEND (0x0120U) + + #define USB_MSG_HCD_D0FIFO_INT (0x0141U) + #define USB_MSG_HCD_D1FIFO_INT (0x0142U) + #define USB_MSG_HCD_RESM_INT (0x0143U) + #define USB_MSG_PCD_D0FIFO_INT (0x0144U) + #define USB_MSG_PCD_D1FIFO_INT (0x0145U) + #define USB_MSG_PCD_RESM_INT (0x0146U) + +/* USB Manager task message command */ + #define USB_MSG_MGR_AORDETACH (0x0121U) + #define USB_MSG_MGR_OVERCURRENT (0x0122U) + #define USB_MSG_MGR_STATUSRESULT (0x0123U) + #define USB_MSG_MGR_SUBMITRESULT (0x0124U) + #define USB_MSG_MGR_TRANSENDRESULT (0x0125U) + + #define USB_MSG_MGR_SETCONFIGURATION (0x0300) + #define USB_MSG_MGR_SETCONFIGURATION_RESULT (0x0301) + + #define USB_MSG_MGR_GETDESCRIPTOR (0x0400) + #define USB_MSG_MGR_GETDESCRIPTOR_RESULT (0x0401) + +/* USB HUB task message command */ + #define USB_MSG_HUB_HUB2HUBSTART (0x0131U) + #define USB_MSG_HUB_START (0x0132U) + #define USB_MSG_HUB_STOP (0x0133U) + #define USB_MSG_HUB_SUBMITRESULT (0x0134U) + #define USB_MSG_HUB_EVENT (0x0135U) /* nonOS */ + #define USB_MSG_HUB_ATTACH (0x0136U) /* nonOS */ + #define USB_MSG_HUB_RESET (0x0137U) /* nonOS */ + +/* CLS task message command */ + #define USB_MSG_CLS_CHECKREQUEST (0x0201U) /* nonOS */ + #define USB_MSG_CLS_INIT (0x0202U) /* nonOS */ + #define USB_MSG_CLS_TASK (0x0203U) /* nonOS */ + #define USB_MSG_CLS_WAIT (0x0204U) /* nonOS */ + #define USB_MSG_CLS_PROCESSRESULT (0x0205U) /* nonOS */ + +/* HET task message command */ + #define USB_MSG_HET_UACTOFF (0x0171U) + #define USB_MSG_HET_UACTON (0x0172U) + #define USB_MSG_HET_VBUSOFF (0x0173U) + #define USB_MSG_HET_VBUSON (0x0174U) + #define USB_MSG_HET_RESET (0x0175U) + #define USB_MSG_HET_SUSPEND (0x0176U) + #define USB_MSG_HET_RESUME (0x0177U) + #define USB_MSG_HET_ENUMERATION (0x0178U) + #define USB_MSG_HET_TESTNONE (0x0181U) + #define USB_MSG_HET_TESTPACKET (0x0182U) + #define USB_MSG_HET_TESTJ (0x0183U) + #define USB_MSG_HET_TESTK (0x0184U) + #define USB_MSG_HET_TESTSE0 (0x0185U) + #define USB_MSG_HET_TESTSIGSTOP (0x0186U) + #define USB_MSG_HET_SINGLESETUP (0x0187U) + #define USB_MSG_HET_SINGLEDATA (0x0188U) + +/* Descriptor index */ + #define USB_DEV_MAX_PKT_SIZE (7U) /* Index of bMAXPacketSize */ + #define USB_DEV_NUM_CONFIG (17U) /* Index of bNumConfigurations */ + #define USB_ALT_NO (255U) + #define USB_SOFT_CHANGE (0U) + +/* USB Peripheral task message command */ + #define USB_MSG_PCD_INT (0x0151U) + #define USB_MSG_PCD_SUBMITUTR (0x0152U) + #define USB_MSG_PCD_TRANSEND1 (0x0153U) + #define USB_MSG_PCD_TRANSEND2 (0x0154U) + #define USB_MSG_PCD_REMOTEWAKEUP (0x0155U) + #define USB_MSG_PCD_DETACH (0x0161U) + #define USB_MSG_PCD_ATTACH (0x0162U) + #define USB_MSG_PCD_CLRSEQBIT (0x0163U) + #define USB_MSG_PCD_SETSTALL (0x0164U) + #define USB_MSG_PCD_PCUTINT (0x0156U) + + #define USB_MSG_PCD_DP_ENABLE (0x0157U) + #define USB_MSG_PCD_DP_DISABLE (0x0158U) + #define USB_MSG_PCD_DM_ENABLE (0x0159U) + #define USB_MSG_PCD_DM_DISABLE (0x015AU) + + #define USB_MSG_PCD_DMAINT (0x015bU) + + #define USB_DO_REMOTEWAKEUP (USB_MSG_PCD_REMOTEWAKEUP) + #define USB_DP_ENABLE (USB_MSG_PCD_DP_ENABLE) + #define USB_DP_DISABLE (USB_MSG_PCD_DP_DISABLE) + #define USB_DM_ENABLE (USB_MSG_PCD_DM_ENABLE) + #define USB_DM_DISABLE (USB_MSG_PCD_DM_DISABLE) + + #define USB_DO_STALL (USB_MSG_PCD_SETSTALL) + + #define USB_DO_RESET_AND_ENUMERATION (0x0202U) /* USB_MSG_HCD_ATTACH */ + #define USB_PORT_ENABLE (0x0203U) /* USB_MSG_HCD_VBON */ + #define USB_PORT_DISABLE (0x0204U) /* USB_MSG_HCD_VBOFF */ + #define USB_DO_GLOBAL_SUSPEND (0x0205U) /* USB_MSG_HCD_SUSPEND */ + #define USB_DO_SELECTIVE_SUSPEND (0x0206U) /* USB_MSG_HCD_SUSPEND */ + #define USB_DO_GLOBAL_RESUME (0x0207U) /* USB_MSG_HCD_RESUME */ + #define USB_DO_SELECTIVE_RESUME (0x0208U) /* USB_MSG_HCD_RESUME */ + #define USB_DO_CLR_STALL (0x0209U) /* USB_MSG_HCD_CLR_STALL */ + #define USB_DO_SET_SQTGL (0x020AU) /* USB_MSG_HCD_SQTGLBIT */ + #define USB_DO_CLR_SQTGL (0x020BU) /* USB_MSG_HCD_CLRSEQBIT */ + +/* BC State Define */ + #define USB_BC_STATE_INIT (0x00U) + #define USB_BC_STATE_DET (0x01U) + #define USB_BC_STATE_CDP (0x02U) + #define USB_BC_STATE_SDP (0x03U) + #define USB_BC_STATE_DCP (0x04U) + #define USB_BC_STATE_MAX (0x05U) + +/* BC State Change Event Define */ + #define USB_BC_EVENT_VB (0x00U) + #define USB_BC_EVENT_AT (0x01U) + #define USB_BC_EVENT_DT (0x02U) + #define USB_BC_EVENT_MAX (0x03U) + +/* DCP Mode Setting Define */ + #define USB_BC_DCPMODE (0x01U) + +/*#define USB_BC_DCPMODE (0x00U)*/ + + #define USB_NOT_BC (0xFFFEU) + + #define USB_ODD (0x1U) + +/************************************************************************* + * old basic_cfg.h #define + *************************************************************************/ + #define USB_SND_MSG(ID, MESS) (usb_cstd_snd_msg((uint8_t) (ID), (usb_msg_t *) (MESS))) + #define USB_ISND_MSG(ID, MESS) (usb_cstd_isnd_msg((uint8_t) (ID), (usb_msg_t *) (MESS))) + #define USB_WAI_MSG(ID, MESS, TM) (usb_cstd_wai_msg((uint8_t) (ID), (usb_msg_t *) (MESS), (usb_tm_t) (TM))) + #define USB_RCV_MSG(ID, MESS) (usb_cstd_rec_msg((uint8_t) (ID), (usb_msg_t **) (MESS), (usb_tm_t) (0U))) + #define USB_TRCV_MSG(ID, MESS, TM) (usb_cstd_rec_msg((uint8_t) (ID), (usb_msg_t **) (MESS), (usb_tm_t) (TM))) + + #define USB_PGET_BLK(ID, BLK) (usb_cstd_pget_blk((uint8_t) (ID), (usb_utr_t **) (BLK))) + #define USB_REL_BLK(ID, BLK) (usb_cstd_rel_blk((uint8_t) (ID), (usb_utr_t *) (BLK))) + +/* Descriptor size */ + #define USB_DEVICESIZE (20U) /* Device Descriptor size */ + #define USB_CONFIGSIZE (256U) /* Configuration Descriptor size */ + +/* Number of software retries when a no-response condition occurs during a transfer */ + #define USB_PIPEERROR (1U) + +/** [Output debugging message in a console of IDE.] + * not defined(USB_DEBUG_ON) : No output the debugging message + * defined(USB_DEBUG_ON) : Output the debugging message + */ + #if defined(USB_DEBUG_ON) + #define USB_PRINTF0(FORM) (printf(FORM)) + #define USB_PRINTF1(FORM, x1) (printf((FORM), (x1))) + #define USB_PRINTF2(FORM, x1, x2) (printf((FORM), (x1), (x2))) + #define USB_PRINTF3(FORM, x1, x2, x3) (printf((FORM), (x1), (x2), (x3))) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) (printf((FORM), (x1), (x2), (x3), (x4))) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) (printf((FORM), (x1), (x2), (x3), (x4), (x5))) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6))) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, x7) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), (x7))) + #define USB_PRINTF8(FORM, \ + x1, \ + x2, \ + x3, \ + x4, \ + x5, \ + x6, \ + x7, \ + x8) (printf((FORM), (x1), (x2), (x3), (x4), (x5), (x6), (x7), \ + (x8))) + #else /* defined(USB_DEBUG_ON) */ + #define USB_PRINTF0(FORM) + #define USB_PRINTF1(FORM, x1) + #define USB_PRINTF2(FORM, x1, x2) + #define USB_PRINTF3(FORM, x1, x2, x3) + #define USB_PRINTF4(FORM, x1, x2, x3, x4) + #define USB_PRINTF5(FORM, x1, x2, x3, x4, x5) + #define USB_PRINTF6(FORM, x1, x2, x3, x4, x5, x6) + #define USB_PRINTF7(FORM, x1, x2, x3, x4, x5, x6, x7) + #define USB_PRINTF8(FORM, x1, x2, x3, x4, x5, x6, x7, x8) + #endif /* defined(USB_DEBUG_ON) */ + + #ifdef __cplusplus +} + #endif + +#endif /* R_USB_BASIC_DEFINE_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h new file mode 100644 index 00000000..4f1d2ddf --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_cstd_rtos.h @@ -0,0 +1,145 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#include "r_usb_basic.h" +#include "r_usb_typedef.h" + +#if (BSP_CFG_RTOS != 0) + + #if (BSP_CFG_RTOS == 2) + #include "FreeRTOS.h" + #include "task.h" + #include "queue.h" + #elif (BSP_CFG_RTOS == 1) + #include "tx_api.h" + #endif + + #ifndef R_USB_CSTD_RTOS_H + #define R_USB_CSTD_RTOS_H + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + + #if (BSP_CFG_RTOS == 2) +typedef TaskHandle_t rtos_task_id_t; +typedef QueueHandle_t rtos_mbx_id_t; +typedef QueueHandle_t rtos_mem_id_t; +typedef SemaphoreHandle_t rtos_sem_id_t; +typedef TickType_t rtos_time_t; + +/** USB task's priority **/ + #define HCD_TSK_PRI (configMAX_PRIORITIES - 1) + #define HUB_TSK_PRI (configMAX_PRIORITIES - 3) + #define MGR_TSK_PRI (configMAX_PRIORITIES - 2) + #define PCD_TSK_PRI (configMAX_PRIORITIES - 1) + #define PMSC_TSK_PRI (configMAX_PRIORITIES - 2) + + #elif (BSP_CFG_RTOS == 1) +typedef TX_THREAD rtos_task_id_t; +typedef TX_QUEUE rtos_mbx_id_t; +typedef TX_BYTE_POOL rtos_mem_id_t; +typedef TX_SEMAPHORE rtos_sem_id_t; +typedef uint32_t rtos_time_t; + + #define USB_TASK_PRI_BASE (10) + #define HCD_TSK_PRI (USB_TASK_PRI_BASE) + #define HUB_TSK_PRI (HCD_TSK_PRI + 2) + #define MGR_TSK_PRI (HCD_TSK_PRI + 1) + #define PCD_TSK_PRI (USB_TASK_PRI_BASE) + #define PMSC_TSK_PRI (PCD_TSK_PRI + 1) + + #endif /* (BSP_CFG_RTOS == 2) */ + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + +/** Size of a queue **/ + #define QUEUE_SIZE (10) + +/** USB task stack size in words **/ + #if (BSP_CFG_RTOS == 1) + #if defined(USB_CFG_HMSC_USE) + #define HCD_STACK_SIZE (2048) + #define MGR_STACK_SIZE (2048) + #else + +// #define HCD_STACK_SIZE (1536) +// #define MGR_STACK_SIZE (1536) + #define HCD_STACK_SIZE (1536 + 1024) + #define MGR_STACK_SIZE (1536 + 1024) + #endif + #define HUB_STACK_SIZE (512) + #define PCD_STACK_SIZE (1024 * 2) + #define PMSC_STACK_SIZE (512) + #define HCDC_STACK_SIZE (512) + #define HHID_STACK_SIZE (512) + #elif (BSP_CFG_RTOS == 2) /* #if (BSP_CFG_RTOS == 1) */ + #define HCD_STACK_SIZE (512) + #define HUB_STACK_SIZE (512) + #define MGR_STACK_SIZE (512) + #define PCD_STACK_SIZE (512) + #define PMSC_STACK_SIZE (512) + #define HCDC_STACK_SIZE (512) + #define HHID_STACK_SIZE (512) + #endif /* #if (BSP_CFG_RTOS == 1) */ +/* Number of Memory Block */ + #define NUM_OF_BLOCK (64) + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ +typedef enum e_usb_rtos_err +{ + UsbRtos_Success = 0, // Successful + UsbRtos_Err_Init_Mbx, // Failure of Mailbox Creation + UsbRtos_Err_Init_Mpl, // Failure of Memory Pool Creation + UsbRtos_Err_Init_Tsk, // Failure of Task Creation + UsbRtos_Err_Init_Sem, // Failure of Semaphore Creation + UsbRtos_Err_Delete_Mbx, // Failure of Mailbox Delete + UsbRtos_Err_Delete_Mpl, // Failure of Memory Pool Delete + UsbRtos_Err_Delete_Tsk, // Failure of Task Delete + #if defined(USB_CFG_OTG_USE) + UsbRtos_Err_Init_OTG_Detach_Tmr, // Failure of OTG Detach Timer Creation + UsbRtos_Err_Delete_OTG_Detach_Tmr, // Failure of OTG Detach Timer Delete + UsbRtos_Err_Init_OTG_Chattering_Tmr, // Failure of OTG Chattering Timer Creation + UsbRtos_Err_Delete_OTG_Chattering_Tmr, // Failure of OTG Chattering Timer Creation + UsbRtos_Err_Init_OTG_HNP_Tmr, // Failure of OTG HNP Timer Creation + UsbRtos_Err_Delete_OTG_HNP_Tmr, // Failure of OTG HNP Timer Delete + #endif /* defined(USB_CFG_OTG_USE) */ +} usb_rtos_err_t; + +/****************************************************************************** + * Exported global variables + ******************************************************************************/ +extern rtos_mbx_id_t * g_mbx_table[]; +extern rtos_mem_id_t * g_mpl_table[]; + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +usb_rtos_err_t usb_rtos_configuration(usb_mode_t usb_mode); +usb_rtos_err_t usb_rtos_delete(uint8_t module_number); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_CSTD_RTOS_H */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h new file mode 100644 index 00000000..7defb6ce --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_extern.h @@ -0,0 +1,811 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef R_USB_EXTERN_H +#define R_USB_EXTERN_H + +#include "r_usb_basic_api.h" +#if defined(USB_CFG_OTG_USE) + #include "r_external_irq_api.h" +#endif /* defined(USB_CFG_OTG_USE) */ + +#if (BSP_CFG_RTOS != 0) + #include "r_usb_cstd_rtos.h" +#endif /* #if (BSP_CFG_RTOS != 0) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/***************************************************************************** + * Public Variables + ******************************************************************************/ + +/* r_usbif_api.c */ +#if (BSP_CFG_RTOS == 0) +extern uint16_t g_usb_change_device_state[USB_NUM_USBIP]; +#endif + +/* r_usb_cdataio.c */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +extern usb_utr_t * g_p_usb_pstd_pipe[USB_MAX_PIPE_NO + 1U]; +extern uint32_t g_usb_pstd_data_cnt[USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer counter */ +extern uint8_t * gp_usb_pstd_data[USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer pointer(8bit) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern usb_utr_t * g_p_usb_hstd_pipe[][USB_MAX_PIPE_NO + 1U]; /* Message pipe */ +extern uint8_t * gp_usb_hstd_data_ptr[][USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer pointer(8bit) */ +extern uint32_t g_usb_hstd_data_cnt[][USB_MAX_PIPE_NO + 1U]; /* PIPEn Buffer counter */ +extern uint32_t g_usb_hstd_data_cnt_pipe0[]; /* PIPE0 Control transfer data stage receive size */ +extern uint16_t g_usb_hstd_hs_enable[]; /* Hi-speed enable */ + +/* r_usb_cinthandler_usbip0.c */ +extern usb_utr_t g_usb_cstd_int_msg[][USB_INTMSGMAX]; /* Interrupt message */ +extern uint16_t g_usb_cstd_int_msg_cnt[]; /* Interrupt message count */ + +/* r_usb_hdriver.c */ +extern uint16_t g_usb_hstd_ignore_cnt[][USB_MAX_PIPE_NO + 1U]; /* Ignore count */ +extern usb_hcdreg_t g_usb_hstd_device_drv[][USB_MAXDEVADDR + 1U]; /* Device driver (registration) */ +extern volatile uint16_t g_usb_hstd_device_info[][USB_MAXDEVADDR + 1U][8U]; +extern usb_ctrl_trans_t g_usb_ctrl_request[USB_NUM_USBIP][USB_MAXDEVADDR + 1]; + #if (BSP_CFG_RTOS != 0) +extern usb_hdl_t g_usb_hstd_sus_res_task_id[]; + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* port status, config num, interface class, speed, */ +extern uint16_t g_usb_hstd_remort_port[]; +extern uint16_t g_usb_hstd_ctsq[]; /* Control transfer stage management */ +extern uint16_t g_usb_hstd_mgr_mode[]; /* Manager mode */ +extern uint16_t g_usb_hstd_dcp_register[][USB_MAXDEVADDR + 1U]; /* DEVSEL & DCPMAXP (Multiple device) */ +extern uint16_t g_usb_hstd_device_addr[]; /* Device address */ +extern uint16_t g_usb_hstd_device_speed[]; /* Reset handshake result */ +extern uint16_t g_usb_hstd_device_num[]; /* Device driver number */ + +/* r_usb_hmanager.c */ +extern uint16_t g_usb_hstd_enum_seq[]; /* Enumeration request */ +extern uint16_t g_usb_hstd_device_descriptor[][USB_DEVICESIZE / 2U]; +extern uint16_t g_usb_hstd_config_descriptor[][USB_CONFIGSIZE / 2U]; +extern uint16_t g_usb_hstd_suspend_pipe[][USB_MAX_PIPE_NO + 1U]; +extern uint16_t g_usb_hstd_check_enu_result[]; /* Enumeration result check */ +extern uint8_t g_usb_hstd_class_data[USB_NUM_USBIP][CLSDATASIZE]; + +/* r_usb_hcontrolrw.c */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE +extern uint16_t g_usb_hstd_response_counter[]; + #endif /* USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ + + #if USB_CFG_BC == USB_CFG_ENABLE +extern usb_bc_status_t g_usb_hstd_bc[2U]; +extern void (* usb_hstd_bc_func[USB_BC_STATE_MAX][USB_BC_EVENT_MAX])(usb_utr_t * ptr); + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* r_usb_pdriver.c */ +extern usb_cb_t g_usb_pstd_stall_cb; /* Stall Callback function */ +extern uint16_t g_usb_pstd_config_num; /* Configuration Number */ +extern uint16_t g_usb_pstd_stall_pipe[USB_MAX_PIPE_NO + 1U]; /* Stall Pipe info */ +extern uint16_t g_usb_pstd_alt_num[]; /* Alternate */ +extern uint16_t g_usb_pstd_test_mode_select; /* Test Mode Selectors */ +extern uint16_t g_usb_pstd_test_mode_flag; /* Test Mode Flag */ +extern uint16_t g_usb_pstd_eptbl_index[2][USB_MAX_EP_NO + 1U]; /* Index of Endpoint Information table */ +extern uint16_t g_usb_pstd_req_type; /* Request type */ +extern uint16_t g_usb_pstd_req_value; /* Value */ +extern uint16_t g_usb_pstd_req_index; /* Index */ +extern uint16_t g_usb_pstd_req_length; /* Length */ +extern usb_pcdreg_t g_usb_pstd_driver; /* Driver registration */ +extern usb_setup_t g_usb_pstd_req_reg; /* Request variable */ +extern usb_int_t g_usb_pstd_usb_int; +extern uint16_t g_usb_pstd_pipe0_request; +extern uint16_t g_usb_pstd_std_request; +extern uint16_t g_usb_peri_connected; /* Peri CDC application enable */ + + #if defined(USB_CFG_PMSC_USE) +extern uint8_t g_usb_pmsc_usbip; + #endif /* defined(USB_CFG_PMSC_USE) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +extern uint16_t g_usb_pstd_remote_wakeup; /* Remote Wake up Enable Flag */ +extern uint16_t g_usb_pstd_remote_wakeup_state; /* Result for Remote wake up */ + +/* r_usb.c */ + +extern volatile uint16_t g_usb_usbmode[USB_NUM_USBIP]; /* USB mode HOST/PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern usb_utr_t g_usb_hdata[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +extern usb_utr_t g_usb_pdata[USB_MAXPIPE_NUM + 1]; + +#endif /* ( (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI ) */ + +#if (BSP_CFG_RTOS != 0) +extern usb_instance_ctrl_t g_usb_cstd_event[]; +extern rtos_task_id_t g_usb_cur_task_hdl[]; +#else /* #if (BSP_CFG_RTOS != 0) */ +extern usb_event_t g_usb_cstd_event; +#endif /* #if (BSP_CFG_RTOS != 0) */ + +extern usb_pipe_table_t g_usb_pipe_table[USB_NUM_USBIP][USB_MAXPIPE_NUM + 1]; +extern uint16_t g_usb_cstd_bemp_skip[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1U]; + +/* r_usb_creg_abs.c */ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +extern uint16_t g_usb_hstd_use_pipe[]; + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if (BSP_CFG_RTOS != 0) +extern rtos_sem_id_t g_usb_semaphore_hdl[]; +extern usb_utr_t * get_usb_int_buf(void); + +extern usb_callback_t * g_usb_apl_callback[USB_NUM_USBIP]; + #if (BSP_CFG_RTOS == 1) +extern TX_SEMAPHORE g_usb_host_usbx_sem[USB_NUM_USBIP][USB_MAX_PIPE_NO + 1]; // usbx + #endif /* #if (BSP_CFG_RTOS == 1) */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + +/* r_usb_pbc.c */ +#if USB_CFG_BC == USB_CFG_ENABLE + #if (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI +extern uint16_t g_usb_bc_detect; + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ +#endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#if defined(USB_CFG_HMSC_USE) +extern uint8_t g_drive_search_lock; +extern uint8_t g_drive_search_que[]; +extern uint8_t g_drive_search_que_cnt; + +#endif /* defined(USB_CFG_HMSC_USE) */ + +#if defined(USB_CFG_OTG_USE) +extern uint8_t g_usb_otg_hnp_process[USB_NUM_USBIP]; +extern uint8_t g_is_A_device[USB_NUM_USBIP]; +extern uint8_t g_is_A_cable_detach[USB_NUM_USBIP]; +extern void (* g_p_otg_callback[USB_NUM_USBIP])(ULONG mode); +extern volatile uint8_t g_usb_is_otg_attach_interrupt[USB_NUM_USBIP]; + +extern TX_TIMER g_usb_otg_detach_timer; + #if USB_NUM_USBIP == 2 +extern TX_TIMER g_usb2_otg_detach_timer; + #endif /* USB_NUM_USBIP == 2 */ +extern volatile uint8_t g_usb_otg_hnp_counter; +extern TX_TIMER g_usb_otg_hnp_timer; +#endif /* defined(USB_CFG_OTG_USE) */ + +/***************************************************************************** + * Public Functions + ******************************************************************************/ + +/* r_usb.c */ +void Test_USB_Change_device_state(uint16_t state); +void Test_USB_Change_remote_wakeup(uint16_t data1, uint16_t data2); +void Test_USB_Change_usbmode(uint16_t data1); +void Test_USB_Change_read_write_pointer(uint16_t write_val, + uint16_t read_val, + usb_status_t code_val, + uint16_t request_val); +void Test_USB_Change_Info(usb_instance_ctrl_t * p_ctrl, uint16_t ifcls, uint16_t speed, uint16_t port, uint16_t state); +void Test_USB_Change_Pipe_flag(uint16_t data1, uint16_t data2, uint16_t pipe_no); + +fsp_err_t usb_module_start(uint8_t ip_type); +fsp_err_t usb_module_register_clear(uint8_t usb_ip); +fsp_err_t usb_module_stop(uint8_t ip_type); +void usb_cpu_delay_xms(uint16_t time); +void usb_cpu_delay_1us(uint16_t time); +void usb_cpu_usbint_init(uint8_t ip_type, usb_cfg_t const * const cfg); +uint16_t usb_chattaring(uint16_t * syssts); + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_cpu_int_enable(void); +void usb_cpu_int_disable(void); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ +bool usb_check_use_usba_module(usb_utr_t * ptr); + +/* r_usb_cdataio.c */ +uint8_t usb_get_usepipe(usb_instance_ctrl_t * p_ctrl, usb_transfer_t dir); +usb_er_t usb_data_read(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_ctrl_read(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_data_write(usb_instance_ctrl_t * p_ctrl, uint8_t const * const buf, uint32_t size); +usb_er_t usb_ctrl_write(usb_instance_ctrl_t * p_ctrl, uint8_t * buf, uint32_t size); +usb_er_t usb_data_stop(usb_instance_ctrl_t * p_ctrl, usb_transfer_t type); +usb_er_t usb_ctrl_stop(usb_instance_ctrl_t * p_ctrl); +void usb_cstd_debug_hook(uint16_t error_code); + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +usb_er_t usb_pstd_transfer_start(usb_utr_t * ptr); +usb_er_t usb_pstd_transfer_end(usb_utr_t * p_utr, uint16_t pipe); +void usb_pstd_change_device_state(uint16_t state, uint16_t keyword, usb_cb_t complete, usb_utr_t * p_utr); +void usb_pstd_driver_registration(usb_pcdreg_t * registinfo); +void usb_pstd_driver_release(void); + + #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) +uint16_t usb_pstd_get_pipe_buf_value(uint16_t pipe_no); + + #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_hstd_send_start(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_buf_to_fifo(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +uint16_t usb_hstd_write_data(usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode); +void usb_hstd_receive_start(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_fifo_to_buf(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +uint16_t usb_hstd_read_data(usb_utr_t * ptr, uint16_t pipe, uint16_t pipemode); +void usb_hstd_data_end(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_er_t usb_hstd_transfer_end(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_er_t usb_hstd_change_device_state(usb_utr_t * ptr, usb_cb_t complete, uint16_t msginfo, uint16_t member); +usb_er_t usb_hstd_mgr_open(usb_utr_t * ptr); +void usb_hstd_driver_registration(usb_utr_t * ptr, usb_hcdreg_t * callback); +void usb_hstd_driver_release(usb_utr_t * ptr, uint8_t devclass); +void usb_hstd_set_pipe_info(uint16_t ip_no, uint16_t pipe_no, usb_pipe_table_reg_t * src_ep_tbl); +void usb_hstd_return_enu_mgr(usb_utr_t * ptr, uint16_t cls_result); +fsp_err_t usb_hstd_hcd_open(usb_utr_t * ptr); + +uint8_t usb_hstd_make_pipe_reg_info(uint16_t ip_no, + uint16_t address, + uint16_t usb_class, + uint16_t speed, + uint8_t * descriptor, + usb_pipe_table_reg_t * pipe_table_work); + + #if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) +uint16_t usb_hstd_get_pipe_buf_value(uint16_t pipe_no); + + #endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void usb_pstd_send_start(uint16_t pipe); +void usb_pstd_buf_to_fifo(uint16_t pipe, uint16_t useport, usb_utr_t * p_utr); +uint16_t usb_pstd_write_data(uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr); +void usb_pstd_receive_start(uint16_t pipe); +void usb_pstd_fifo_to_buf(uint16_t pipe, uint16_t useport, usb_utr_t * p_utr); +uint16_t usb_pstd_read_data(uint16_t pipe, uint16_t pipemode, usb_utr_t * p_utr); +void usb_pstd_data_end(uint16_t pipe, uint16_t status, usb_utr_t * p_utr); + +uint8_t usb_pstd_set_pipe_table(uint8_t * descriptor, usb_utr_t * p_utr, uint8_t class_info); +void usb_pstd_clr_pipe_table(uint8_t usb_ip); +void usb_pstd_set_pipe_reg(usb_utr_t * p_utr); +void usb_pstd_clr_pipe_reg(usb_utr_t * p_utr); +uint8_t usb_pstd_get_pipe_no(uint8_t type, uint8_t dir, usb_utr_t * p_utr, uint8_t class_info); + +/* r_usb_cintfifo.c */ +void usb_pstd_nrdy_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_bemp_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_brdy_pipe_process(usb_utr_t * p_utr, uint16_t bitsts); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_hstd_nrdy_pipe_process(usb_utr_t * ptr, uint16_t bitsts); +void usb_hstd_bemp_pipe_process(usb_utr_t * ptr, uint16_t bitsts); +void usb_hstd_brdy_pipe_process(usb_utr_t * ptr, uint16_t bitsts); + +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + +/* r_usb_clibusbip.c */ +void usb_cstd_nrdy_enable(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pid(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_port_speed(usb_utr_t * ptr); +uint16_t usb_cstd_get_maxpacket_size(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pipe_dir(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_pipe_type(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_do_aclrm(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_set_buf(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_clr_stall(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_usb_task(void); +void usb_class_task(void); +void usb_set_event(usb_status_t event, usb_instance_ctrl_t * ctrl); +uint16_t usb_cstd_remote_wakeup(usb_utr_t * p_utr); + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +uint8_t usb_hstd_pipe_to_epadr(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_hstd_pipe2fport(usb_utr_t * ptr, uint16_t pipe); +void usb_hstd_dummy_function(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_suspend_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_resume_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_berne_enable(usb_utr_t * ptr); +void usb_hstd_sw_reset(usb_utr_t * ptr); +void usb_hstd_set_hse(usb_utr_t * ptr, uint16_t speed); +void usb_hstd_do_sqtgl(usb_utr_t * ptr, uint16_t pipe, uint16_t toggle); +uint16_t usb_hstd_get_devsel(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_hstd_get_device_address(usb_utr_t * ptr, uint16_t pipe); + +#endif /* ( (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST ) */ + +#if (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI +uint16_t usb_pstd_epadr2pipe(uint16_t Dir_Ep, usb_utr_t * p_utr); +uint16_t usb_pstd_pipe2fport(usb_utr_t * p_utr, uint16_t pipe); +uint16_t usb_pstd_hi_speed_enable(usb_utr_t * p_utr); +void usb_pstd_dummy_function(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_pstd_dummy_trn(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +/* r_usb_creg_abs.c */ +uint16_t usb_cstd_is_set_frdy(usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel); +void usb_cstd_chg_curpipe(usb_utr_t * ptr, uint16_t pipe, uint16_t fifosel, uint16_t isel); +void usb_cstd_set_transaction_counter(usb_utr_t * ptr, uint16_t trnreg, uint16_t trncnt); +void usb_cstd_clr_transaction_counter(usb_utr_t * ptr, uint16_t trnreg); +void usb_cstd_pipe_init(usb_utr_t * ptr, uint16_t pipe); +void usb_cstd_clr_pipe_cnfg(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_set_nak(usb_utr_t * ptr, uint16_t pipe); +uint16_t usb_cstd_get_buf_size(usb_utr_t * ptr, uint16_t pipe); + +#if ((USB_CFG_MODE &USB_CFG_HOST) == USB_CFG_HOST) +uint8_t * usb_hstd_write_fifo(usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * write_p); +uint8_t * usb_hstd_read_fifo(usb_utr_t * ptr, uint16_t count, uint16_t pipemode, uint8_t * read_p); +void usb_hstd_forced_termination(usb_utr_t * ptr, uint16_t pipe, uint16_t status); +usb_regadr_t usb_hstd_get_usb_ip_adr(uint16_t ipnum); +void usb_hstd_nrdy_endprocess(usb_utr_t * ptr, uint16_t pipe); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +#if ((USB_CFG_MODE &USB_CFG_PERI) == USB_CFG_PERI) +uint8_t * usb_pstd_write_fifo(uint16_t count, uint16_t pipemode, uint8_t * write_p, usb_utr_t * p_utr); +uint8_t * usb_pstd_read_fifo(uint16_t count, uint16_t pipemode, uint8_t * read_p, usb_utr_t * p_utr); +void usb_pstd_forced_termination(uint16_t pipe, uint16_t status, usb_utr_t * p_utr); +void usb_pstd_interrupt_clock(uint8_t usb_ip); +void usb_pstd_self_clock(uint8_t usb_ip); +void usb_pstd_stop_clock(uint8_t usb_ip); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/* r_usb_cinthandler_usbip0.c */ +void usb_hstd_usb_handler(void); +void usb_hstd_dma_handler(void); +void usb_hstd_init_usb_message(usb_utr_t * ptr); + +/* r_usb_cinthandler_usbip1.c */ +void usb2_hstd_usb_handler(void); +void usb2_hstd_dma_handler(void); + +/* r_usb_hdriver.c */ +uint8_t * usb_hstd_dev_descriptor(usb_utr_t * ptr); +uint8_t * usb_hstd_con_descriptor(usb_utr_t * ptr); +void usb_hstd_device_resume(usb_utr_t * ptr, uint16_t devaddr); +usb_er_t usb_hstd_hcd_snd_mbx(usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t * adr, usb_cb_t callback); +void usb_hstd_mgr_snd_mbx(usb_utr_t * ptr, uint16_t msginfo, uint16_t dat, uint16_t res); + + #if (BSP_CFG_RTOS == 1) +void usb_hstd_hcd_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_hcd_task(void * stacd); + + #endif /* #if (BSP_CFG_RTOS == 1) */ +usb_er_t usb_hstd_transfer_start(usb_utr_t * ptr); +usb_er_t usb_hstd_transfer_start_req(usb_utr_t * ptr); +void usb_hstd_hcd_rel_mpl(usb_utr_t * ptr, uint16_t n); +usb_er_t usb_hstd_clr_stall(usb_utr_t * ptr, uint16_t pipe, usb_cb_t complete); +usb_er_t usb_hstd_clr_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete); +void usb_hstd_suspend(usb_utr_t * ptr); +void usb_hstd_bus_int_disable(usb_utr_t * ptr); +void usb_class_request_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +void usb_host_registration(usb_utr_t * ptr); +void usb_hstd_connect_err_event_set(uint16_t ip_no); + +/* r_usb_hcontrolrw.c */ +uint16_t usb_hstd_ctrl_write_start(usb_utr_t * ptr, uint32_t bsize, uint8_t * table); +void usb_hstd_ctrl_read_start(usb_utr_t * ptr, uint32_t bsize, uint8_t * table); +void usb_hstd_status_start(usb_utr_t * ptr); +void usb_hstd_ctrl_end(usb_utr_t * ptr, uint16_t status); +void usb_hstd_setup_start(usb_utr_t * ptr); + +/* r_usb_hintfifo.c */ +void usb_hstd_brdy_pipe(usb_utr_t * ptr); +void usb_hstd_nrdy_pipe(usb_utr_t * ptr); +void usb_hstd_bemp_pipe(usb_utr_t * ptr); + +/* r_usb_hstdfunction.c */ +void usb_hstd_bchg0function(usb_utr_t * ptr); +void usb_hstd_ls_connect_function(usb_utr_t * ptr); +void usb_hstd_attach_function(void); +void usb_hstd_ovrcr0function(usb_utr_t * ptr); + +void usb_hdriver_init(usb_utr_t * ptr); +void usb_class_driver_start(usb_utr_t * ptr); + + #if (BSP_CFG_RTOS != 0) +void class_trans_result(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +uint16_t class_trans_wait_tmo(usb_utr_t * ptr, uint16_t tmo); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +/* r_usb_hreg_abs */ +void usb_hstd_set_hub_port(usb_utr_t * ptr, uint16_t addr, uint16_t upphub, uint16_t hubport); +void usb_hstd_interrupt_handler(usb_utr_t * ptr); +uint16_t usb_hstd_chk_attach(usb_utr_t * ptr); +void usb_hstd_chk_clk(usb_utr_t * ptr, uint16_t event); +void usb_hstd_detach_process(usb_utr_t * ptr); +void usb_hstd_read_lnst(usb_utr_t * ptr, uint16_t * buf); +void usb_hstd_attach_process(usb_utr_t * ptr); +void usb_hstd_chk_sof(usb_utr_t * ptr); +void usb_hstd_bus_reset(usb_utr_t * ptr); +void usb_hstd_resume_process(usb_utr_t * ptr); +uint16_t usb_hstd_support_speed_check(usb_utr_t * ptr); + +/* r_usb_hlibusbip.c */ +void usb_hstd_set_dev_addr(usb_utr_t * ptr, uint16_t addr, uint16_t speed); +void usb_hstd_bchg_enable(usb_utr_t * ptr); +void usb_hstd_set_uact(usb_utr_t * ptr); +void usb_hstd_ovrcr_enable(usb_utr_t * ptr); +void usb_hstd_ovrcr_disable(usb_utr_t * ptr); +void usb_hstd_attch_enable(usb_utr_t * ptr); +void usb_hstd_attch_disable(usb_utr_t * ptr); +void usb_hstd_dtch_enable(usb_utr_t * ptr); +void usb_hstd_dtch_disable(usb_utr_t * ptr); +usb_er_t usb_hstd_set_pipe_reg_for_devadr(usb_utr_t * ptr, uint16_t device_address); +uint8_t usb_hstd_get_pipe_no(uint16_t ip_no, uint16_t address, uint16_t usb_class, uint8_t type, uint8_t dir); +uint16_t usb_hstd_get_pipe_peri_value(uint16_t speed, uint8_t binterval); +void usb_hstd_clr_pipe_table(uint16_t ip_no, uint16_t device_address); +void usb_hstd_set_pipe_reg(usb_utr_t * ptr, uint16_t pipe_no); + +uint16_t usb_hstd_chk_dev_addr(usb_utr_t * ptr, uint16_t addr); +uint16_t usb_hstd_get_dev_speed(usb_utr_t * ptr, uint16_t addr); +void usb_hstd_bchg_disable(usb_utr_t * ptr); + +/* r_usb_hsignal.c */ +void usb_hstd_vbus_control(usb_utr_t * ptr, uint16_t command); +void usb_hstd_suspend_process(usb_utr_t * ptr); +void usb_hstd_attach(usb_utr_t * ptr, uint16_t result); +void usb_hstd_detach(usb_utr_t * ptr); + +/* r_usb_hmanager.c */ +void usb_hstd_notif_ator_detach(usb_utr_t * ptr, uint16_t result); +void usb_hstd_ovcr_notifiation(usb_utr_t * ptr); +void usb_hstd_status_result(usb_utr_t * ptr, uint16_t data1, uint16_t result); +void usb_hstd_enum_get_descriptor(usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value); +void usb_hstd_enum_set_address(usb_utr_t * ptr, uint16_t addr, uint16_t setaddr); +void usb_hstd_enum_set_configuration(usb_utr_t * ptr, uint16_t addr, uint16_t confnum); +void usb_hstd_enum_dummy_request(usb_utr_t * ptr, uint16_t addr, uint16_t cnt_value); +void usb_hstd_electrical_test_mode(usb_utr_t * ptr, uint16_t product_id); + + #if (BSP_CFG_RTOS == 1) +void usb_hstd_mgr_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_hstd_mgr_task(void * stacd); + + #endif /* #if (BSP_CFG_RTOS == 1) */ + +extern void (* g_usb_hstd_enumaration_process[])(usb_utr_t *, uint16_t, uint16_t); + + #if (BSP_CFG_RTOS != 0) +uint16_t usb_hstd_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string); +uint16_t usb_hstd_set_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum); +uint16_t usb_hstd_get_config_desc(usb_utr_t * ptr, uint16_t addr, uint16_t length); + + #if ((BSP_CFG_RTOS == 1) && defined(USB_CFG_HHID_USE)) +void usb_hid_set_protocol(usb_utr_t * ptr, uint16_t addr, uint16_t setaddr); +void usb_hid_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string); + + #endif + + #else /* #if (BSP_CFG_RTOS != 0) */ +uint16_t usb_hstd_get_string_desc(usb_utr_t * ptr, uint16_t addr, uint16_t string, usb_cb_t complete); +uint16_t usb_hstd_set_feature(usb_utr_t * ptr, uint16_t addr, uint16_t epnum, usb_cb_t complete); +uint16_t usb_hstd_get_config_desc(usb_utr_t * ptr, uint16_t addr, uint16_t length, usb_cb_t complete); + + #endif /* #if (BSP_CFG_RTOS != 0) */ + +void usb_hstd_submit_result(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_hstd_mgr_suspend(usb_utr_t * ptr, uint16_t info); +void usb_hstd_device_state_ctrl(usb_utr_t * ptr, uint16_t devaddr, uint16_t msginfo); +void usb_hstd_device_state_ctrl2(usb_utr_t * ptr, + usb_cb_t complete, + uint16_t devaddr, + uint16_t msginfo, + uint16_t mgr_msginfo); +void usb_hstd_mgr_reset(usb_utr_t * ptr, uint16_t addr); +void usb_hstd_mgr_resume(usb_utr_t * ptr, uint16_t info); + +uint16_t usb_hstd_std_req_check(uint16_t errcheck); + +/* r_usb_hhubsys.c */ +uint16_t usb_hhub_check_descriptor(uint8_t * table, uint16_t spec); +void usb_hhub_open(usb_utr_t * ptr, uint16_t devaddr, uint16_t data2); +void usb_hhub_close(usb_utr_t * ptr, uint16_t hubaddr, uint16_t data2); +void usb_hhub_registration(usb_utr_t * ptr, usb_hcdreg_t * callback); +uint16_t usb_hhub_get_hub_information(usb_utr_t * ptr, uint16_t hubaddr, usb_cb_t complete); +uint16_t usb_hhub_get_port_information(usb_utr_t * ptr, uint16_t hubaddr, uint16_t port, usb_cb_t complete); +void usb_hhub_task(void * stacd); +uint16_t usb_hhub_get_string_descriptor1(usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete); +uint16_t usb_hhub_get_string_descriptor1check(uint16_t errcheck); +uint16_t usb_hhub_get_string_descriptor2(usb_utr_t * ptr, uint16_t devaddr, uint16_t index, usb_cb_t complete); +uint16_t usb_hhub_get_string_descriptor_to_check(uint16_t errcheck); + +/* r_usb_hbc.c */ + #if USB_CFG_BC == USB_CFG_ENABLE +void usb_hstd_pddetint_process(usb_utr_t * ptr); + + #endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +/* r_usb_hostelectrical.c */ +void usb_hstd_test_stop(usb_utr_t * ptr); +void usb_hstd_test_signal(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_uact_ctrl(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_vbus_ctrl(usb_utr_t * ptr, uint16_t command); +void usb_hstd_test_bus_reset(usb_utr_t * ptr); +void usb_hstd_test_suspend(usb_utr_t * ptr); +void usb_hstd_test_resume(usb_utr_t * ptr); + +/* r_usb_hscheduler.c */ +fsp_err_t usb_cstd_wai_msg(uint8_t id, usb_msg_t * mess, usb_tm_t times); +void usb_cstd_wait_scheduler(void); +void usb_cstd_sche_init(void); +fsp_err_t usb_cstd_check(usb_er_t err); +uint8_t usb_cstd_check_schedule(void); +void usb_cstd_scheduler(void); +void usb_cstd_set_task_pri(uint8_t tasknum, uint8_t pri); + +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +usb_er_t usb_cstd_pget_blk(uint8_t id, usb_utr_t ** blk); +usb_er_t usb_cstd_rel_blk(uint8_t id, usb_utr_t * blk); + +/* r_usb_hscheduler.c */ +usb_er_t usb_cstd_snd_msg(uint8_t id, usb_msg_t * mess); +usb_er_t usb_cstd_rec_msg(uint8_t id, usb_msg_t ** mess, usb_tm_t tm); +usb_er_t usb_cstd_isnd_msg(uint8_t id, usb_msg_t * mess); + +#if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/* r_usb_pinthandler_usbip0.c */ +void usb_pstd_usb_handler(void); + +/* r_usb_pdriver.c */ + #if (BSP_CFG_RTOS == 1) +void usb_pstd_pcd_task(ULONG entry_input); + + #else /* #if (BSP_CFG_RTOS == 1) */ +void usb_pstd_pcd_task(void); + + #endif /* #if (BSP_CFG_RTOS == 1) */ +usb_er_t usb_pstd_set_submitutr(usb_utr_t * utrmsg); +void usb_pstd_clr_alt(void); +void usb_pstd_clr_mem(void); +void usb_pstd_set_config_num(uint16_t Value); +void usb_pstd_clr_eptbl_index(void); +uint16_t usb_pstd_get_interface_num(void); +uint16_t usb_pstd_get_alternate_num(uint16_t int_num); +void usb_pstd_set_eptbl_index(uint16_t int_num, uint16_t alt_num); +uint16_t usb_pstd_chk_remote(void); +uint8_t usb_pstd_get_current_power(void); + +/* r_usb_pcontrolrw.c */ +uint16_t usb_pstd_ctrl_read(uint32_t bsize, uint8_t * table, usb_utr_t * p_utr); +void usb_pstd_ctrl_write(uint32_t bsize, uint8_t * table, usb_utr_t * p_utr); +void usb_pstd_ctrl_end(uint16_t status, usb_utr_t * p_utr); + +/* r_usb_pintfifo.c */ +void usb_pstd_brdy_pipe(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_nrdy_pipe(usb_utr_t * p_utr, uint16_t bitsts); +void usb_pstd_bemp_pipe(usb_utr_t * p_utr, uint16_t bitsts); + +/* r_usb_pstdfunction.c */ +void usb_pstd_busreset_function(void); +void usb_pstd_suspend_function(void); +void usb_p_registration(usb_instance_ctrl_t * ctrl, usb_cfg_t * cfg); +void usb_pdriver_init(usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg); + +/* r_usb_preg_abs.c */ +void usb_pstd_interrupt_handler(uint16_t * type, uint16_t * status, uint8_t usb_ip); +void usb_pstd_save_request(uint8_t usb_ip); +uint16_t usb_pstd_chk_configured(usb_utr_t * p_utr); +void usb_pstd_bus_reset(usb_utr_t * p_utr); +void usb_pstd_remote_wakeup(uint8_t usb_ip); +void usb_pstd_test_mode(usb_utr_t * p_utr); +void usb_pstd_attach_process(usb_utr_t * p_utr); +void usb_pstd_detach_process(usb_utr_t * p_utr); +void usb_pstd_suspend_process(usb_utr_t * p_utr); +void usb_pstd_resume_process(usb_utr_t * p_utr); +uint16_t usb_pstd_chk_vbsts(uint8_t usb_ip); +void usb_pstd_set_stall(uint16_t pipe, usb_utr_t * p_utr); +void usb_pstd_set_stall_pipe0(usb_utr_t * p_utr); + +/* r_usb_pstdrequest.c */ +void usb_pstd_stand_req0(usb_utr_t * p_utr); +void usb_pstd_stand_req1(usb_utr_t * p_utr); +void usb_pstd_stand_req2(usb_utr_t * p_utr); +void usb_pstd_stand_req3(usb_utr_t * p_utr); +void usb_pstd_stand_req4(usb_utr_t * p_utr); +void usb_pstd_stand_req5(usb_utr_t * p_utr); +void usb_pstd_set_feature_function(usb_utr_t * p_utr); + +/* peri_processing.c */ +void usb_peri_registration(usb_instance_ctrl_t * ctrl, usb_cfg_t const * const cfg); +void usb_peri_devdefault(usb_utr_t * ptr, uint16_t mode, uint16_t data2); +uint16_t usb_peri_pipe_info(uint8_t * table, uint16_t speed, uint16_t length, usb_utr_t * p_utr); +void usb_peri_configured(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_detach(usb_utr_t * ptr, uint16_t usb_state, uint16_t data2); +void usb_peri_suspended(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_resume(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_interface(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +void usb_peri_class_request(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); +void usb_peri_class_request_ioss(usb_setup_t * req); +void usb_peri_class_request_rwds(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wds(usb_utr_t * p_utr); +void usb_peri_other_request(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wnss(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_rss(usb_setup_t * req, usb_utr_t * p_utr); +void usb_peri_class_request_wss(usb_setup_t * req, usb_utr_t * p_utr); + +#endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ + +#if defined(USB_CFG_PVND_USE) +extern void usb_pvnd_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_pvnd_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PVND_USE) */ + +#if defined(USB_CFG_PCDC_USE) +extern void usb_pcdc_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_pcdc_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PCDC_USE) */ + +#if defined(USB_CFG_PHID_USE) +extern void usb_phid_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_phid_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_PHID_USE) */ + +#if defined(USB_CFG_PMSC_USE) + #if (BSP_CFG_RTOS != 1) +extern void usb_pmsc_task(void); + + #endif /* #if (BSP_CFG_RTOS != 1) */ +#endif /* defined(USB_CFG_PMSC_USE) */ + +#if defined(USB_CFG_HCDC_USE) +extern void usb_hcdc_read_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hcdc_write_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hcdc_registration(usb_utr_t * ptr); +extern void usb_hcdc_task(usb_vp_int_t stacd); +extern void usb_hcdc_driver_start(usb_utr_t * ptr); + +#endif /* defined(USB_CFG_HCDC_USE) */ + +#if defined(USB_CFG_HHID_USE) +extern void usb_hhid_read_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_hhid_write_complete(usb_utr_t * mess, uint16_t data1, uint16_t data2); +extern void usb_hhid_registration(usb_utr_t * ptr); +extern void usb_hhid_task(usb_vp_int_t stacd); +extern void usb_hhid_driver_start(usb_utr_t * ptr); + +#endif /* defined(USB_CFG_HHID_USE) */ + +#if defined(USB_CFG_HMSC_USE) +extern void usb_hmsc_strg_cmd_complete(usb_utr_t * mess, uint16_t devadr, uint16_t data2); +extern void usb_hmsc_drive_complete(usb_utr_t * ptr, uint16_t addr, uint16_t data2); +extern void usb_hmsc_registration(usb_utr_t * ptr); +extern void usb_hmsc_driver_start(uint16_t ip_no); +extern void usb_hmsc_storage_driver_start(uint16_t ip_no); +extern void usb_hmsc_task(void); +extern void usb_hmsc_strg_drive_task(void); +extern uint16_t usb_hmsc_strg_drive_search(usb_utr_t * ptr, uint16_t addr, usb_cb_t complete); + +#endif /* defined(USB_CFG_HMSC_USE) */ + +#if defined(USB_CFG_HVND_USE) +extern void usb_hvnd_registration(usb_utr_t * ptr); +extern void usb_hvnd_read_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); +extern void usb_hvnd_write_complete(usb_utr_t * ptr, uint16_t data1, uint16_t data2); + +#endif /* defined(USB_CFG_HVND_USE) */ + +extern uint16_t g_usb_pstd_eptbl[]; + +#if defined(USB_CFG_PMSC_USE) +extern void usb_pmsc_receive_cbw(usb_utr_t * p_utr); +extern void usb_pmsc_get_max_lun(uint16_t value, uint16_t index, uint16_t length, usb_utr_t * p_utr); +extern void usb_pmsc_mass_strage_reset(uint16_t value, uint16_t index, uint16_t length, usb_utr_t * p_utr); + +#endif + +void usb_hstd_device_information(usb_utr_t * ptr, uint16_t devaddr, uint16_t * tbl); +void usb_pstd_device_information(usb_utr_t * ptr, uint16_t * tbl); +usb_er_t usb_pstd_set_stall_clr_feature(usb_utr_t * ptr, usb_cb_t complete, uint16_t pipe); + +#if USB_CFG_BC == USB_CFG_ENABLE + +/* BC State change function */ +void usb_hstd_bc_err(usb_utr_t * ptr); +void usb_hstd_bc_init_vb(usb_utr_t * ptr); +void usb_hstd_bc_det_at(usb_utr_t * ptr); +void usb_hstd_bc_cdp_dt(usb_utr_t * ptr); +void usb_hstd_bc_sdp_dt(usb_utr_t * ptr); + +/* BC State entry/exit function */ +void usb_hstd_bc_det_entry(usb_utr_t * ptr); +void usb_hstd_bc_det_exit(usb_utr_t * ptr); +void usb_hstd_bc_cdp_entry(usb_utr_t * ptr); +void usb_hstd_bc_cdp_exit(usb_utr_t * ptr); +void usb_hstd_bc_sdp_entry(usb_utr_t * ptr); +void usb_hstd_bc_sdp_exit(usb_utr_t * ptr); +void usb_hstd_bc_dcp_entry(usb_utr_t * ptr); + +void usb_hstd_pddetint_process(usb_utr_t * ptr); +void usb_pstd_bc_detect_process(usb_utr_t * p_utr); + +#endif /* USB_CFG_BC == USB_CFG_ENABLE */ + +#if (BSP_CFG_RTOS != 0) + +/* r_usb_cstd_rtos.c */ +void usb_cstd_pipe_msg_clear(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_pipe0_msg_clear(usb_utr_t * ptr, uint16_t dev_addr); +void usb_cstd_pipe_msg_re_forward(uint16_t ip_no, uint16_t pipe_no); +void usb_cstd_pipe0_msg_re_forward(uint16_t ip_no); +void usb_cstd_pipe_msg_forward(usb_utr_t * ptr, uint16_t pipe_no); +void usb_cstd_pipe0_msg_forward(usb_utr_t * ptr, uint16_t dev_addr); + +#endif /* #if (BSP_CFG_RTOS != 0) */ + +#if (BSP_CFG_RTOS == 1) +void usb_cstd_usbx_callback(usb_event_info_t * p_api_event, usb_hdl_t cur_task, usb_onoff_t usb_state); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void usb_host_usbx_registration(usb_utr_t * p_utr); +void usb_host_usbx_attach_init(uint8_t module_number); + + #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint32_t usb_peri_usbx_initialize_complete(void); + + #endif /* #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) */ + + #if defined(USB_CFG_OTG_USE) +void usb_otg_irq_callback(external_irq_callback_args_t * p_args); +void usb2_otg_irq_callback(external_irq_callback_args_t * p_args); +VOID usb_otg_detach_timer(ULONG args); +VOID usb2_otg_detach_timer(ULONG args); +VOID usb_otg_chattering_timer(ULONG args); +VOID usb_otg_hnp_timer(ULONG args); + + #endif /* defined(USB_CFG_OTG_USE) */ + +#endif /* #if (BSP_CFG_RTOS == 1) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_EXTERN_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h new file mode 100644 index 00000000..8d2f73a8 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h @@ -0,0 +1,263 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef R_USB_TYPEDEF_H +#define R_USB_TYPEDEF_H + +/****************************************************************************** + * Includes + ******************************************************************************/ +#include +#include "r_usb_basic_api.h" +#include "r_usb_cstd_rtos.h" +#include "r_usb_basic.h" +#include "r_usb_basic_define.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/****************************************************************************** + * Typedef definitions + ******************************************************************************/ +typedef void * VP; /* Pointer to variable */ +typedef long ER; /* Error code */ +typedef short ID; /* Object ID (xxxid) */ +typedef long TMO; /* Time out */ +typedef long VP_INT; /* Integer data */ + +/*----------- msghead -----------*/ +typedef struct +{ + VP msghead; /* Message header */ +} t_msg_t; + +typedef t_msg_t usb_msg_t; +typedef ER usb_er_t; +typedef ID usb_id_t; +typedef TMO usb_tm_t; +typedef VP usb_mh_t; +typedef VP_INT usb_vp_int_t; + +#if defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) +typedef volatile R_USB_HS0_Type * usb_regadr1_t; // @@ +#else /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ +typedef volatile R_USB_FS0_Type * usb_regadr1_t; +#endif /* defined(BSP_MCU_GROUP_RA6M3) || defined(BSP_MCU_GROUP_RA6M5) */ + +typedef volatile R_USB_FS0_Type * usb_regadr_t; + +typedef struct usb_utr usb_utr_t; +typedef void (* usb_cb_t)(struct usb_utr *, uint16_t, uint16_t); + +typedef struct usb_utr +{ + usb_mh_t msghead; /* Message header (for SH-solution) */ + usb_cb_t complete; /* Call Back Function Info */ + void const * p_tranadr; /* Transfer data Start address */ + uint32_t read_req_len; /* Read Request Length */ + uint32_t tranlen; /* Transfer data length */ + uint16_t * p_setup; /* Setup packet(for control only) */ + void * p_usr_data; +#if (BSP_CFG_RTOS != 0) + usb_hdl_t cur_task_hdl; /* Task Handle */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + uint16_t msginfo; /* Message Info for F/W */ + uint16_t keyword; /* Root port / Device address / Pipe number */ + uint8_t ip; /* USB module number(0 or 1) */ + uint16_t result; /* Result */ + uint16_t status; /* Status */ + uint16_t pipectr; /* Pipe control register */ +#if (BSP_CFG_RTOS != 0) + uint16_t setup_data[5]; /* Save setup for Request */ +#endif /* #if (BSP_CFG_RTOS != 0) */ + uint8_t errcnt; /* Error count */ + uint8_t segment; /* Last flag */ + const transfer_instance_t * p_transfer_tx; ///< Send context + const transfer_instance_t * p_transfer_rx; ///< Receive context + union + { + usb_regadr_t ipp; /* USB module startAddress(USB0/USB1)*/ +#if USB_NUM_USBIP == 2 + usb_regadr1_t ipp1; /* USB module start address(USBA) */ +#endif /* USB_NUM_USBIP == 2 */ + }; +#if (BSP_CFG_RTOS == 1) /* Azure RTOS */ + #if defined(USB_CFG_PPRN_USE) + uint32_t timeout; + uint8_t is_timeout; + #endif /* define(USB_CFG_PPRN_USE) */ +#endif /* (BSP_CFG_RTOS == 1) */ +} usb_message_t; + +typedef struct st_usb usb_stnbyint_t; + +typedef void (* usb_cb_check_t)(struct usb_utr *, uint16_t **); + +/* Class request processing function type. */ +typedef void (* usb_cb_trn_t)(usb_setup_t * preq, uint16_t ctsq, usb_utr_t * p_utr); + +typedef struct +{ + uint16_t rootport; /* Root port */ + uint16_t devaddr; /* Device address */ + uint16_t devstate; /* Device state */ + uint16_t ifclass; /* Interface Class */ + uint16_t * p_tpl; /* Target peripheral list(Vendor ID, Product ID) */ + usb_cb_t classinit; /* Driver init */ + usb_cb_check_t classcheck; /* Driver check */ + usb_cb_t devconfig; /* Device configured */ + usb_cb_t devdetach; /* Device detach */ + usb_cb_t devsuspend; /* Device suspend */ + usb_cb_t devresume; /* Device resume */ +} usb_hcdreg_t; + +typedef struct +{ + uint8_t * p_devicetbl; /* Device descriptor Table address */ + uint8_t * p_qualitbl; /* Qualifier descriptor Table address */ + uint8_t * p_configtbl; /* Configuration descriptor Table address */ + uint8_t * p_othertbl; /* Other configuration descriptor Table address */ + uint8_t ** p_stringtbl; /* String descriptor Table address */ + usb_cb_t devdefault; /* Device default */ + usb_cb_t devconfig; /* Device configured */ + usb_cb_t devdetach; /* Device detach */ + usb_cb_t devsuspend; /* Device suspend */ + usb_cb_t devresume; /* Device resume */ + usb_cb_t interface; /* Interface changed */ + usb_cb_trn_t ctrltrans; /* Control Transfer */ + uint8_t num_string; /* Num entry String Descriptor */ +} usb_pcdreg_t; + +typedef struct usb_utr usb_hcdinfo_t; +typedef struct usb_utr usb_mgrinfo_t; +typedef struct usb_utr usb_pcdinfo_t; +typedef struct usb_utr usb_clsinfo_t; + +typedef struct +{ + uint8_t state; /* BC State */ + uint8_t pd_detect; /* PD Detect Flag */ +} usb_bc_status_t; + +typedef struct usb_ctrl_trans +{ + usb_setup_t setup; /* Request command */ + uint16_t address; /* Device address setting */ +} usb_ctrl_trans_t; + +#if (BSP_CFG_RTOS == 0) +typedef struct +{ + uint16_t type; + uint16_t status; + usb_cfg_t * p_cfg; +} usb_int_info_t; +#endif /*(BSP_CFG_RTOS == 0)*/ + +typedef struct +{ +#if (BSP_CFG_RTOS != 0) + uint16_t type; + uint16_t status; + uint16_t ip; + uint16_t fifo_type; +#else /* #if (BSP_CFG_RTOS != 0) */ + usb_int_info_t buf[USB_INT_BUFSIZE]; /* Interrupt Info */ + uint8_t wp; /* Write pointer */ + uint8_t rp; /* Read pointer */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_int_t; + +typedef struct +{ + uint16_t ip; /* USB IP(USB_IP0/USB_IP1) */ + uint16_t fifo_type; /* Use FIFO type(USB_CUSE/USB_D0USE/USB_D1USE) */ + usb_cfg_t * p_cfg; +} usb_fifo_type_t; + +typedef struct +{ +#if (BSP_CFG_RTOS != 0) + uint16_t type; + uint16_t status; + uint16_t ip; + uint16_t fifo_type; +#else /* #if (BSP_CFG_RTOS != 0) */ + usb_fifo_type_t buf[USB_INT_BUFSIZE]; /* Complete DMA Info */ + uint8_t wp; /* Write pointer */ + uint8_t rp; /* Read pointer */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_dma_int_t; + +typedef struct usb_event +{ +#if (BSP_CFG_RTOS != 0) + usb_instance_ctrl_t ctrl; /* Control Information */ + uint8_t code; +#else /* #if (BSP_CFG_RTOS != 0) */ + uint8_t write_pointer; /* Write pointer */ + uint8_t read_pointer; /* Read pointer */ + usb_status_t code[USB_EVENT_MAX]; /* Event code */ + usb_instance_ctrl_t ctrl[USB_EVENT_MAX]; /* Control Information */ +#endif /* #if (BSP_CFG_RTOS != 0) */ +} usb_event_t; + +typedef struct usb_pipe_table +{ + uint16_t use_flag; + uint16_t pipe_cfg; + uint16_t pipe_buf; + uint16_t pipe_maxp; + uint16_t pipe_peri; +} usb_pipe_table_t; + +typedef struct usb_pipe_reg +{ + uint16_t pipe_cfg; + uint16_t pipe_buf; + uint16_t pipe_maxp; + uint16_t pipe_peri; +} usb_pipe_table_reg_t; + +typedef enum e_usb_class_internal +{ + USB_CLASS_INTERNAL_PCDC = 0, ///< PCDC Class 0 + USB_CLASS_INTERNAL_PCDCC, ///< PCDCC Class 1 + USB_CLASS_INTERNAL_PCDC2, ///< PCDC2 Class 2 + USB_CLASS_INTERNAL_PCDCC2, ///< PCDCC2 Class 3 + USB_CLASS_INTERNAL_PHID, ///< PHID Class 4 + USB_CLASS_INTERNAL_PHID2, ///< PHID2 Class 5 + USB_CLASS_INTERNAL_PAUD, ///< PAUD Class 6 + USB_CLASS_INTERNAL_PPRN, ///< PPRN Class 7 + USB_CLASS_INTERNAL_PVND, ///< PVND Class 8 + USB_CLASS_INTERNAL_HCDC, ///< HCDC Class 9 + USB_CLASS_INTERNAL_HCDCC, ///< HCDCC Class 10 + USB_CLASS_INTERNAL_HHID, ///< HHID Class 11 + USB_CLASS_INTERNAL_HVND, ///< HVND Class 12 + USB_CLASS_INTERNAL_HMSC, ///< HMSC Class 13 + USB_CLASS_INTERNAL_PMSC, ///< PMSC Class 14 + USB_CLASS_INTERNAL_HPRN, ///< HPRN Class 15 + USB_CLASS_INTERNAL_REQUEST, ///< USB Class Request 16 + USB_CLASS_INTERNAL_END ///< USB Class 17 +} usb_class_internal_t; + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_TYPEDEF_H */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h new file mode 100644 index 00000000..863294d2 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h @@ -0,0 +1,497 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef R_USB_BITDEFINE_H + #define R_USB_BITDEFINE_H + + #ifdef __cplusplus +extern "C" { + #endif + +/***************************************************************************** + * Structure Types + ******************************************************************************/ + +/* USB0 & USBHS Register definition */ + +/* System Configuration Control Register */ + #define USB_SCKE (0x0400U) /* b10: USB clock enable */ + #define USB_CNEN (0x0100U) /* b8: Single end receiver */ + #define USB_HSE (0x0080U) /* b7: Hi-speed enable */ + #define USB_DCFM (0x0040U) /* b6: Function select */ + #define USB_DRPD (0x0020U) /* b5: D+/D- pull down control */ + #define USB_DPRPU (0x0010U) /* b4: D+ pull up control */ + #define USB_DMRPU (0x0008U) /* b3: D- pull up control *//* For low speed */ + #define USB_USBE (0x0001U) /* b0: USB module enable */ + +/* CPU Bus Wait Register */ + #define USB_BWAIT (0x0F0FU) /* b3-0: Bus wait bit */ + #define USB_BWAIT_15 (0x0F0FU) /* 15 wait (access cycle 17) */ + #define USB_BWAIT_14 (0x0F0EU) /* 14 wait (access cycle 16) */ + #define USB_BWAIT_13 (0x0F0DU) /* 13 wait (access cycle 15) */ + #define USB_BWAIT_12 (0x0F0CU) /* 12 wait (access cycle 14) */ + #define USB_BWAIT_11 (0x0F0BU) /* 11 wait (access cycle 13) */ + #define USB_BWAIT_10 (0x0F0AU) /* 10 wait (access cycle 12) */ + #define USB_BWAIT_9 (0x0F09U) /* 9 wait (access cycle 11) */ + #define USB_BWAIT_8 (0x0F08U) /* 8 wait (access cycle 10) */ + #define USB_BWAIT_7 (0x0F07U) /* 7 wait (access cycle 9) */ + #define USB_BWAIT_6 (0x0F06U) /* 6 wait (access cycle 8) */ + #define USB_BWAIT_5 (0x0F05U) /* 5 wait (access cycle 7) */ + #define USB_BWAIT_4 (0x0F04U) /* 4 wait (access cycle 6) */ + #define USB_BWAIT_3 (0x0F03U) /* 3 wait (access cycle 5) */ + #define USB_BWAIT_2 (0x0F02U) /* 2 wait (access cycle 4) */ + #define USB_BWAIT_1 (0x0F01U) /* 1 wait (access cycle 3) */ + #define USB_BWAIT_0 (0x0F00U) /* 0 wait (access cycle 2) */ + #define USB_BWAIT_B11_B8_WRITE (0x0F00U) /* b11-b8: Reserved bit write */ + +/* System Configuration Status Register */ + #define USB_OVCMON (0xC000U) /* b15-14: Over-current monitor */ + #define USB_OVCBIT (0x8000U) /* b15-14: Over-current bit */ + #define USB_HTACT (0x0040U) /* b6: USB Host Sequencer Status Monitor */ + #define USB_SOFEA (0x0020U) /* b5: SOF monitor */ + #define USB_IDMON (0x0004U) /* b2: ID-pin monitor */ + #define USB_LNST (0x0003U) /* b1-0: D+, D- line status */ + #define USB_SE1 (0x0003U) /* SE1 */ + #define USB_FS_KSTS (0x0002U) /* Full-Speed K State */ + #define USB_FS_JSTS (0x0001U) /* Full-Speed J State */ + #define USB_LS_JSTS (0x0002U) /* Low-Speed J State */ + #define USB_LS_KSTS (0x0001U) /* Low-Speed K State */ + #define USB_SE0 (0x0000U) /* SE0 */ + +/* PLL Status Register */ + #define USB_PLLLOCK (0x0001U) + +/* Device State Control Register */ + #define USB_HNPBTOA (0x0800U) /* b11: Host negotiation protocol (BtoA) */ + #define USB_EXICEN (0x0400U) /* b10: EXICEN output terminal control */ + #define USB_VBUSEN (0x0200U) /* b9: VBUS output terminal control */ + #define USB_WKUP (0x0100U) /* b8: Remote wakeup */ + #define USB_RWUPE (0x0080U) /* b7: Remote wakeup sense */ + #define USB_USBRST (0x0040U) /* b6: USB reset enable */ + #define USB_RESUME (0x0020U) /* b5: Resume enable */ + #define USB_UACT (0x0010U) /* b4: USB bus enable */ + #define USB_RHST (0x0007U) /* b2-0: Reset handshake status */ + #define USB_HSPROC (0x0004U) /* HS handshake processing */ + #define USB_HSMODE (0x0003U) /* Hi-Speed mode */ + #define USB_FSMODE (0x0002U) /* Full-Speed mode */ + #define USB_LSMODE (0x0001U) /* Low-Speed mode */ + #define USB_UNDECID (0x0000U) /* Undecided */ + +/* Test Mode Register */ + #define USB_UTST (0x000FU) /* b3-0: Test mode */ + #define USB_H_TST_F_EN (0x000DU) /* HOST TEST FORCE ENABLE */ + #define USB_H_TST_PACKET (0x000CU) /* HOST TEST Packet */ + #define USB_H_TST_SE0_NAK (0x000BU) /* HOST TEST SE0 NAK */ + #define USB_H_TST_K (0x000AU) /* HOST TEST K */ + #define USB_H_TST_J (0x0009U) /* HOST TEST J */ + #define USB_H_TST_NORMAL (0x0000U) /* HOST Normal Mode */ + #define USB_P_TST_PACKET (0x0004U) /* PERI TEST Packet */ + #define USB_P_TST_SE0_NAK (0x0003U) /* PERI TEST SE0 NAK */ + #define USB_P_TST_K (0x0002U) /* PERI TEST K */ + #define USB_P_TST_J (0x0001U) /* PERI TEST J */ + #define USB_P_TST_NORMAL (0x0000U) /* PERI Normal Mode */ + +/* CFIFO/DxFIFO Port Select Register */ + #define USB_RCNT (0x8000U) /* b15: Read count mode */ + #define USB_REW (0x4000U) /* b14: Buffer rewind */ + #define USB_DCLRM (0x2000U) /* b13: Automatic buffer clear mode */ + #define USB_DREQE (0x1000U) /* b12: DREQ output enable */ + #define USB_MBW (0x0C00U) /* b10: Maximum bit width for FIFO access */ + #define USB_MBW_32 (0x0800U) /* FIFO access : 32bit */ + #define USB_MBW_16 (0x0400U) /* FIFO access : 16bit */ + #define USB_MBW_8 (0x0000U) /* FIFO access : 8bit */ + #define USB_BIGEND (0x0100U) /* b8: Big endian mode */ + #define USB_FIFO_BIG (0x0100U) /* Big endian */ + #define USB_FIFO_LITTLE (0x0000U) /* Little endian */ + #define USB_ISEL (0x0020U) /* b5: DCP FIFO port direction select */ + #define USB_CURPIPE (0x000FU) /* b2-0: PIPE select */ + +/* CFIFO/DxFIFO Port Control Register */ + #define USB_BVAL (0x8000U) /* b15: Buffer valid flag */ + #define USB_BCLR (0x4000U) /* b14: Buffer clear */ + #define USB_FRDY (0x2000U) /* b13: FIFO ready */ + #define USB_DTLN (0x0FFFU) /* b11-0: FIFO data length */ + +/* Interrupt Enable Register 0 */ + #define USB_VBSE (0x8000U) /* b15: VBUS interrupt */ + #define USB_RSME (0x4000U) /* b14: Resume interrupt */ + #define USB_SOFE (0x2000U) /* b13: Frame update interrupt */ + #define USB_DVSE (0x1000U) /* b12: Device state transition interrupt */ + #define USB_CTRE (0x0800U) /* b11: Control transfer stage transition interrupt */ + #define USB_BEMPE (0x0400U) /* b10: Buffer empty interrupt */ + #define USB_NRDYE (0x0200U) /* b9: Buffer notready interrupt */ + #define USB_BRDYE (0x0100U) /* b8: Buffer ready interrupt */ + +/* Interrupt Enable Register 1 */ + #define USB_OVRCRE (0x8000U) /* b15: Over-current interrupt */ + #define USB_BCHGE (0x4000U) /* b14: USB bus change interrupt */ + #define USB_DTCHE (0x1000U) /* b12: Detach sense interrupt */ + #define USB_ATTCHE (0x0800U) /* b11: Attach sense interrupt */ + #define USB_L1RSMENDE (0x0200U) /* b9: L1 resume completion interrupt */ + #define USB_LPMENDE (0x0100U) /* b8: LPM transaction completion interrupt */ + #define USB_EOFERRE (0x0040U) /* b6: EOF error interrupt */ + #define USB_SIGNE (0x0020U) /* b5: SETUP IGNORE interrupt */ + #define USB_SACKE (0x0010U) /* b4: SETUP ACK interrupt */ + #define USB_PDDETINTE (0x0001U) /* b0: PDDET detection interrupt */ + +/* BRDY Interrupt Enable/Status Register */ + #define USB_BRDY9 (0x0200U) /* b9: PIPE9 */ + #define USB_BRDY8 (0x0100U) /* b8: PIPE8 */ + #define USB_BRDY7 (0x0080U) /* b7: PIPE7 */ + #define USB_BRDY6 (0x0040U) /* b6: PIPE6 */ + #define USB_BRDY5 (0x0020U) /* b5: PIPE5 */ + #define USB_BRDY4 (0x0010U) /* b4: PIPE4 */ + #define USB_BRDY3 (0x0008U) /* b3: PIPE3 */ + #define USB_BRDY2 (0x0004U) /* b2: PIPE2 */ + #define USB_BRDY1 (0x0002U) /* b1: PIPE1 */ + #define USB_BRDY0 (0x0001U) /* b1: PIPE0 */ + +/* NRDY Interrupt Enable/Status Register */ + #define USB_NRDY9 (0x0200U) /* b9: PIPE9 */ + #define USB_NRDY8 (0x0100U) /* b8: PIPE8 */ + #define USB_NRDY7 (0x0080U) /* b7: PIPE7 */ + #define USB_NRDY6 (0x0040U) /* b6: PIPE6 */ + #define USB_NRDY5 (0x0020U) /* b5: PIPE5 */ + #define USB_NRDY4 (0x0010U) /* b4: PIPE4 */ + #define USB_NRDY3 (0x0008U) /* b3: PIPE3 */ + #define USB_NRDY2 (0x0004U) /* b2: PIPE2 */ + #define USB_NRDY1 (0x0002U) /* b1: PIPE1 */ + #define USB_NRDY0 (0x0001U) /* b1: PIPE0 */ + +/* BEMP Interrupt Enable/Status Register */ + #define USB_BEMP9 (0x0200U) /* b9: PIPE9 */ + #define USB_BEMP8 (0x0100U) /* b8: PIPE8 */ + #define USB_BEMP7 (0x0080U) /* b7: PIPE7 */ + #define USB_BEMP6 (0x0040U) /* b6: PIPE6 */ + #define USB_BEMP5 (0x0020U) /* b5: PIPE5 */ + #define USB_BEMP4 (0x0010U) /* b4: PIPE4 */ + #define USB_BEMP3 (0x0008U) /* b3: PIPE3 */ + #define USB_BEMP2 (0x0004U) /* b2: PIPE2 */ + #define USB_BEMP1 (0x0002U) /* b1: PIPE1 */ + #define USB_BEMP0 (0x0001U) /* b0: PIPE0 */ + +/* SOF Pin Configuration Register */ + #define USB_TRNENSEL (0x0100U) /* b8: Select transaction enable period */ + #define USB_BRDYM (0x0040U) /* b6: BRDY clear timing */ + #define USB_INTL (0x0020U) /* b5: Interrupt sense select */ + #define USB_EDGESTS (0x0010U) /* b4: */ + #define USB_SOFMODE (0x000CU) /* b3-2: SOF pin select */ + #define USB_SOF_125US (0x0008U) /* SOF 125us Frame Signal */ + #define USB_SOF_1MS (0x0004U) /* SOF 1ms Frame Signal */ + #define USB_SOF_DISABLE (0x0000U) /* SOF Disable */ + + #define USB_HSEB (0x8000U) /* b15: CL only mode bit */ + + #define USB_REPSTART (0x0800U) /* b11: Terminator adjustment forcible starting bit */ + #define USB_REPSEL (0x0300U) /* b9-8: Terminator adjustment cycle setting */ + #define USB_REPSEL_128 (0x0300U) /* 128 sec */ + #define USB_REPSEL_64 (0x0200U) /* 64 sec */ + #define USB_REPSEL_16 (0x0100U) /* 16 sec */ + #define USB_REPSEL_NONE (0x0000U) /* - */ + #define USB_CLKSEL (0x0030U) /* b5-4: System clock setting */ + #define USB_CLKSEL_24 (0x0030U) /* 24MHz */ + #define USB_CLKSEL_20 (0x0020U) /* 20MHz */ + #define USB_CLKSEL_48 (0x0010U) /* 48MHz */ + #define USB_CLKSEL_12 (0x0000U) /* 12MHz */ + #define USB_CDPEN (0x0008U) /* b3: Charging downstream port enable */ + #define USB_PLLRESET (0x0002U) /* b1: PLL reset control */ + #define USB_DIRPD (0x0001U) /* b0: Power down control */ + +/* Interrupt Status Register 0 */ + #define USB_VBINT (0x8000U) /* b15: VBUS interrupt */ + #define USB_RESM (0x4000U) /* b14: Resume interrupt */ + #define USB_SOFR (0x2000U) /* b13: SOF update interrupt */ + #define USB_DVST (0x1000U) /* b12: Device state transition interrupt */ + #define USB_CTRT (0x0800U) /* b11: Control transfer stage transition interrupt */ + #define USB_BEMP (0x0400U) /* b10: Buffer empty interrupt */ + #define USB_NRDY (0x0200U) /* b9: Buffer notready interrupt */ + #define USB_BRDY (0x0100U) /* b8: Buffer ready interrupt */ + #define USB_VBSTS (0x0080U) /* b7: VBUS input port */ + #define USB_DVSQ (0x0070U) /* b6-4: Device state */ + #define USB_DS_SPD_CNFG (0x0070U) /* Suspend Configured */ + #define USB_DS_SPD_ADDR (0x0060U) /* Suspend Address */ + #define USB_DS_SPD_DFLT (0x0050U) /* Suspend Default */ + #define USB_DS_SPD_POWR (0x0040U) /* Suspend Powered */ + #define USB_DS_SUSP (0x0040U) /* Suspend */ + #define USB_DS_CNFG (0x0030U) /* Configured */ + #define USB_DS_ADDS (0x0020U) /* Address */ + #define USB_DS_DFLT (0x0010U) /* Default */ + #define USB_DS_POWR (0x0000U) /* Powered */ + #define USB_DVSQS (0x0030U) /* b5-4: Device state */ + #define USB_VALID (0x0008U) /* b3: Setup packet detect flag */ + #define USB_CTSQ (0x0007U) /* b2-0: Control transfer stage */ + #define USB_CS_SQER (0x0006U) /* Sequence error */ + #define USB_CS_WRND (0x0005U) /* Ctrl write nodata status stage */ + #define USB_CS_WRSS (0x0004U) /* Ctrl write status stage */ + #define USB_CS_WRDS (0x0003U) /* Ctrl write data stage */ + #define USB_CS_RDSS (0x0002U) /* Ctrl read status stage */ + #define USB_CS_RDDS (0x0001U) /* Ctrl read data stage */ + #define USB_CS_IDST (0x0000U) /* Idle or setup stage */ + +/* Interrupt Status Register 1 */ + #define USB_OVRCR (0x8000U) /* b15: Over-current interrupt */ + #define USB_BCHG (0x4000U) /* b14: USB bus change interrupt */ + #define USB_DTCH (0x1000U) /* b12: Detach sense interrupt */ + #define USB_ATTCH (0x0800U) /* b11: Attach sense interrupt */ + #define USB_L1RSMEND (0x0200U) /* b9: L1 resume completion interrupt */ + #define USB_LPMEND (0x0100U) /* b8: LPM transaction completion interrupt */ + #define USB_EOFERR (0x0040U) /* b6: EOF-error interrupt */ + #define USB_SIGN (0x0020U) /* b5: Setup ignore interrupt */ + #define USB_SACK (0x0010U) /* b4: Setup ack interrupt */ + #define USB_PDDETINT (0x0001U) /* b0: PDDET detection interrupt */ + +/* Frame Number Register */ + #define USB_OVRN (0x8000U) /* b15: Overrun error */ + #define USB_CRCE (0x4000U) /* b14: Received data error */ + #define USB_FRNM (0x07FFU) /* b10-0: Frame number */ + +/* Device State Change Register */ /* For USB0 */ + #define USB_DVCHG (0x8000U) /* b15: Device state change */ + +/* Micro Frame Number Register */ /* For USBHS */ + #define USB_UFRNM (0x0007U) /* b2-0: Micro frame number */ + +/* USB Address / Low Power Status Recovery Register */ + #define USB_STSRECOV (0x0F00U) /* b11-8: Status Recovery */ + #define USB_USBADDR_MASK (0x007FU) /* b6-0: USB address */ + +/* USB Request Type Register */ + #define USB_BMREQUESTTYPE (0x00FFU) /* b7-0: USB_BMREQUESTTYPE */ + #define USB_BMREQUESTTYPEDIR (0x0080U) /* b7 : Data transfer direction */ + #define USB_BMREQUESTTYPETYPE (0x0060U) /* b6-5: Type */ + #define USB_BMREQUESTTYPERECIP (0x001FU) /* b4-0: Recipient */ + +/* USB Request Value Register */ + #define USB_WVALUE (0xFFFFU) /* b15-0: wValue */ + #define USB_DT_TYPE (0xFF00U) + #define USB_GET_DT_TYPE(v) (((v) & USB_DT_TYPE) >> 8) + #define USB_DT_INDEX (0x00FFU) + #define USB_CONF_NUM (0x00FFU) + #define USB_ALT_SET (0x00FFU) + +/* USB Request Index Register */ + #define USB_WINDEX (0xFFFFU) /* b15-0: wIndex */ + #define USB_TEST_SELECT (0xFF00U) /* b15-b8: Test Mode Selectors */ + #define USB_TEST_J (0x0100U) /* Test_J */ + #define USB_TEST_K (0x0200U) /* Test_K */ + #define USB_TEST_SE0_NAK (0x0300U) /* Test_SE0_NAK */ + #define USB_TEST_PACKET (0x0400U) /* Test_Packet */ + #define USB_TEST_FORCE_ENABLE (0x0500U) /* Test_Force_Enable */ + #define USB_TEST_STSelectors (0x0600U) /* Standard test selectors */ + #define USB_TEST_RESERVED (0x4000U) /* Reserved */ + #define USB_TEST_VSTMODES (0xC000U) /* VendorSpecific test modes */ + +/* USB Request Length Register */ + #define USB_WLENGTH (0xFFFFU) /* b15-0: wLength */ + +/* Refer to r_usb_cdefusbip.h */ + #define USB_TYPE (0xC000U) /* b15-14: Transfer type */ + #define USB_BFRE (0x0400U) /* b10: Buffer ready interrupt mode select */ + + #define USB_DEVSEL (0xF000U) /* b15-14: Device address select */ + #define USB_MAXP (0x007FU) /* b6-0: Maxpacket size of default control pipe */ + #define USB_MXPS (0x07FFU) /* b10-0: Maxpacket size */ + + #define USB_BSTS (0x8000U) /* b15: Buffer status */ + #define USB_SUREQ (0x4000U) /* b14: Send USB request */ + #define USB_INBUFM (0x4000U) /* b14: IN buffer monitor (Only for PIPE1 to 5) */ + #define USB_CSCLR (0x2000U) /* b13: c-split status clear */ + #define USB_CSSTS (0x1000U) /* b12: c-split status */ + #define USB_SUREQCLR (0x0800U) /* b11: stop setup request */ + #define USB_ATREPM (0x0400U) /* b10: Auto repeat mode */ + #define USB_ACLRM (0x0200U) /* b9: buffer auto clear mode */ + #define USB_SQCLR (0x0100U) /* b8: Sequence bit clear */ + #define USB_SQSET (0x0080U) /* b7: Sequence bit set */ + #define USB_SQMON (0x0040U) /* b6: Sequence bit monitor */ + #define USB_PBUSY (0x0020U) /* b5: pipe busy */ + #define USB_PINGE (0x0010U) /* b4: ping enable */ + #define USB_CCPL (0x0004U) /* b2: Enable control transfer complete */ + #define USB_PID (0x0003U) /* b1-0: Response PID */ + #define USB_PID_STALL (0x0002U) /* STALL */ + #define USB_PID_BUF (0x0001U) /* BUF */ + #define USB_PID_NAK (0x0000U) /* NAK */ + + #define USB_PIPENM (0x0007U) /* b2-0: Pipe select */ + +/* Refer to r_usb_cdefusbip.h */ + #define USB_BUFSIZE (0x7C00U) /* b14-10: Pipe buffer size */ + #define USB_BUFNMB (0x007FU) /* b6-0: Pipe buffer number */ + #define USB_PIPE0BUF (256U) + #define USB_PIPEXBUF (64U) + + #define USB_TRENB (0x0200U) /* b9: Transaction count enable */ + #define USB_TRCLR (0x0100U) /* b8: Transaction count clear */ + #define USB_TRNCNT (0xFFFFU) /* b15-0: Transaction counter */ + + #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ + + #define USB_UPPHUB (0x7800U) /* b14-11: HUB register */ + #define USB_HUBPORT (0x0700U) /* b10-8: HUB port */ + #define USB_USBSPD (0x00C0U) /* b7-6: Device speed */ + + #define USB_BYTE_MASK (0x00FFU) /* b0-b7: Byte data Mask */ + + #define USB_CPU_DELAY_US (100U) /* USB CPU delay time microsecond */ + + #define USB_DEVICE_ADDRESS_MAX (127) /* Device Address Max */ + +/********* USB0 Only ******************************************************************************/ + +/* PHY Crosspoint Adjustment Register */ +/* PHYSLEW */ + #define USB_SLEWF01 (0x0008U) /* b3: Cross point adjustment bit 01 */ + #define USB_SLEWF00 (0x0004U) /* b2: Cross point adjustment bit 00 */ + #define USB_SLEWR01 (0x0002U) /* b1: Cross point adjustment bit 01 */ + #define USB_SLEWR00 (0x0001U) /* b0: Cross point adjustment bit 00 */ + +/* Deep Standby USB Transceiver Control/Terminal Monitor Register */ +/* DPUSR0R */ + #define USB_DVBSTS0 (0x00800000U) /* b23: USB0 VBUS input */ + #define USB_DOVCB0 (0x00200000U) /* b21: USB0 OVRCURB input */ + #define USB_DOVCA0 (0x00100000U) /* b20: USB0 OVRCURA input */ + #define USB_DM0 (0x00200000U) /* b17: USB0 D- input */ + #define USB_DP0 (0x00100000U) /* b16: USB0 D+ input */ + #define USB_FIXPHY0 (0x00000010U) /* b4: USB0 transceiver output fixed bit */ + #define USB_DRPD0 (0x00000008U) /* b3: D+/D- pull down resistor control bit */ + #define USB_RPUE0 (0x00000002U) /* b1: DP pull up resistor control bit */ + #define USB_SRPC0 (0x00000001U) /* b0: USB0 single end receiver control bit */ + +/* Deep Standby USB Suspend/Resume Interrupt Register */ +/* DPUSR1R */ + #define USB_DVBINT0 (0x00800000U) /* b23: USB0 VBUS monitor bit */ + #define USB_DOVRCRB0 (0x00200000U) /* b21: USB0 OVRCURB DM monitor bit */ + #define USB_DOVRCRA0 (0x00100000U) /* b20: USB0 OVRCURA DM monitor bit */ + #define USB_DMINT0 (0x00020000U) /* b17: USB0 DM monitor bit */ + #define USB_DPINT0 (0x00010000U) /* b16: USB0 DP monitor bit */ + #define USB_DVBSE0 (0x00000080U) /* b7: USB0 VBUS interrupt enable */ + #define USB_DOVRCRBE0 (0x00000020U) /* b5: USB0 OVRCURB interrupt enable */ + #define USB_DOVRCRAE0 (0x00000010U) /* b4: USB0 OVRCURA interrupt enable */ + #define USB_DMINTE0 (0x00000002U) /* b1: USB0 DM interrupt enable */ + #define USB_DPINTE0 (0x00000001U) /* b0: USB0 DP interrupt enable */ + +/**************************************************************************************************/ + +/********* USBHS Only *****************************************************************************/ + +/* Low Power Control Register */ +/* LPCTRL */ + #define USB_HWUPM (0x0080U) /* b7: */ + +/* Low Power Status Register */ +/* LPSTS */ + #define USB_SUSPENDM (0x4000U) /* b14: UTMI SuspendM control */ + +/* PHY Single Access Read Data Register */ +/* SPRDAT */ + #define USB_PHYRDAT (0x00FFU) /* PHY read data bit */ + +/* Battery Charging Control Register */ +/* BCCTRL */ + #define USB_PDDETSTS (0x0200U) /* b9: PDDET status */ + #define USB_CHGDETSTS (0x0100U) /* b8: CHGDET status */ + #define USB_DCPMODE (0x0020U) /* b5: DCP mode control */ + #define USB_VDMSRCE (0x0010U) /* b4: VDMSRC control */ + #define USB_IDPSINKE (0x0008U) /* b3: IDPSINK control */ + #define USB_VDPSRCE (0x0004U) /* b2: VDPSRC control */ + #define USB_IDMSINKE (0x0002U) /* b1: IDMSINK control */ + #define USB_IDPSRCE (0x0001U) /* b0: IDPSRC control */ + +/* Function L1 Control Register 1 */ +/* PL1CTRL1 */ + #define USB_L1EXTMD (0x4000U) /* b14: PHY control mode */ + #define USB_DVSQEX (0x0080U) /* b7: DVSQ extension bit */ + #define USB_DVSQ (0x0070U) /* b6-4: Mirror of DVSQ */ + #define USB_L1NEGOMD (0x0008U) /* b3: L1 response negotiation control */ + #define USB_L1RESPMD (0x0006U) /* b2-1: L1 response mode */ + #define USB_L1RESPEN (0x0001U) /* b0: L1 response enable */ + +/* Function L1 Control Register 2 */ +/* PL1CTRL2 */ + #define USB_HSRDMON (0x0F00U) /* b12: RWE monitor bit */ + #define USB_RWEMON (0x1000U) /* b11-8: HIRD monitor bit */ + +/* Host L1 Control Register 1 */ +/* HL1CTRL1 */ + #define USB_L1STATUS (0x0006U) /* b2-1: L1 request completion state */ + #define USB_L1REQ (0x0001U) /* b0: L1 changes request bit + */ + +/* Host L1 Control Register 2 */ +/* HL1CTRL2 */ + #define USB_BESL (0x8000U) /* b15: BESL & Alternate HIRD bit */ + #define USB_L1RWE (0x1000U) /* b12: L1 RemoteWake enable for LPM tokens */ + #define USB_HSRD (0x0F00U) /* b11-8: HIRD bit for LPM tokens */ + #define USB_L1ADDR (0x000FU) /* b3-0: DeviceAddress for LPM tokens */ + +/* PHY Timing Register 1 */ +/* PHYTRIM1 */ + #define USB_IMPOFFSET (0x7000U) /* b14-12: Terminator adjustment */ + #define USB_HSIUP (0x0F00U) /* b11-8: Output level setup of HS */ + #define USB_PCOMPENB (0x0080U) /* b7: PVDD starting detection setup */ + #define USB_DFALL (0x000CU) /* b3-2: FS/LS falling output waveform compensation function setting */ + #define USB_DRISE (0x0003U) /* b1-0: FS/LS standup output waveform compensation function setting */ + +/* PHY Timing Register 2 */ +/* PHYTRIM2 */ + #define USB_DIS (0x7000U) /* b14-12: Disconnect disregard level setup */ + #define USB_PDR (0x0300U) /* b9-8: HS output compensation function setting */ + #define USB_HSRXENMODE (0x0080U) /* b7: HS reception permission control mode setup */ + #define USB_SQU (0x000FU) /* b3-0: Squelch disregard level setup */ + +/* Deep Standby USB Register */ +/* DPUSR0R */ + #define USB_DVBSTSHM (0x00800000U) /* b23: VBUS input */ + #define USB_DOVCBHM (0x00200000U) /* b21: OVRCURB input */ + #define USB_DOVCAHM (0x00100000U) /* b20: OVRCURA input */ + +/* DPUSR1R */ + #define USB_DVBSTSH (0x00800000U) /* b23: Interruption factor return display of VBUS */ + #define USB_DOVCBH (0x00200000U) /* b21: Interruption factor return display of OVRCURB */ + #define USB_DOVCAH (0x00100000U) /* b20: Interruption factor return display of OVRCURA */ + #define USB_DVBSTSHE (0x00000080U) /* b7 : VBUS interrupt enable */ + #define USB_DOVCBHE (0x00000020U) /* b5 : OVRCURB interrupt enable */ + #define USB_DOVCAHE (0x00000010U) /* b4 : OVRCURA interrupt enable */ + +/**************************************************************************************************/ + +/* DMAx Pin Configuration Register */ + #define USB_DREQA (0x4000U) /* b14: Dreq active select */ + #define USB_BURST (0x2000U) /* b13: Burst mode */ + #define USB_DACKA (0x0400U) /* b10: Dack active select */ + #define USB_DFORM (0x0380U) /* b9-7: DMA mode select */ + #define USB_CPU_ADR_RD_WR (0x0000U) /* Address + RD/WR mode (CPU bus) */ + #define USB_CPU_DACK_RD_WR (0x0100U) /* DACK + RD/WR (CPU bus) */ + #define USB_CPU_DACK_ONLY (0x0180U) /* DACK only (CPU bus) */ + #define USB_SPLIT_DACK_ONLY (0x0200U) /* DACK only (SPLIT bus) */ + #define USB_DENDA (0x0040U) /* b6: Dend active select */ + #define USB_PKTM (0x0020U) /* b5: Packet mode */ + #define USB_DENDE (0x0010U) /* b4: Dend enable */ + #define USB_OBUS (0x0004U) /* b2: OUTbus mode */ + +/* USB IO Register Reserved bit mask */ + #define INTSTS1_MASK (0xD870U) /* INTSTS1 Reserved bit mask */ + #define BRDYSTS_MASK (0x03FFU) /* BRDYSTS Reserved bit mask */ + #define NRDYSTS_MASK (0x03FFU) /* NRDYSTS Reserved bit mask */ + #define BEMPSTS_MASK (0x03FFU) /* BEMPSTS Reserved bit mask */ + + #ifdef __cplusplus +} + #endif + +#endif /* R_USB_BITDEFINE_H */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h new file mode 100644 index 00000000..720213f6 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_dmac.h @@ -0,0 +1,92 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef R_USB_DMAC_H +#define R_USB_DMAC_H + +#if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) + + #include "r_dmac.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/******************************************************************************* + * Macro definitions + *******************************************************************************/ + #define USB_DMA_USE_CH_MAX (4) /* MAX USE DMAC CH for USB */ + #define USB_DMA_CH_PRI (3) /* DMACmI interrupt priority level for USB Pipe : DxFIFO->buff */ + #define USB_DMA_CH2_PRI (3) /* DMACmI interrupt priority level for USB Pipe : buff->DxFIFO */ + + #define USB_FIFO_ACCESS_TYPE_32BIT (0) /* FIFO port 32bit access */ + #define USB_FIFO_ACCESS_TYPE_16BIT (1) /* FIFO port 16bit access */ + #define USB_FIFO_ACCESS_TYPE_8BIT (2) /* FIFO port 8bit access */ + + #define USB_FIFO_ACCSESS_TYPE_NUM (USB_FIFO_ACCESS_TYPE_8BIT + 1) /* */ + + #define USB_BIT_MBW32 (3UL) /* Mod 4(4Byte=32Bit) */ + #define USB_BIT_MBW16 (1UL) /* Mod 2(2Byte=16Bit) */ + + #define USB_BIT_32_WIDTH (4) + #define USB_BIT_16_WIDTH (2) + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + #define USB_DMAC_PRV_REG(ch) ((R_DMAC0_Type *) ((R_DMAC1_BASE - R_DMAC0_BASE) * ch + R_DMAC0_BASE)) + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ + +/****************************************************************************** + * Exported global functions (to be accessed by other files) + ******************************************************************************/ +extern uint32_t g_usb_cstd_dma_size[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 buffer size */ +extern uint16_t g_usb_cstd_dma_fifo[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 FIFO buffer size */ +extern uint16_t g_usb_cstd_dma_pipe[USB_NUM_USBIP][USB_DMA_USE_CH_MAX]; /* DMA0 and DMA1 pipe number */ + +void usb_cstd_dma_driver(void); +uint16_t usb_cstd_dma_get_crtb(usb_utr_t * p_utr); +uint16_t usb_cstd_dma_get_ir_vect(usb_utr_t * ptr, uint16_t use_port); +void usb_cstd_dma_clear_ir(usb_utr_t * ptr, uint16_t use_port); +void usb_cstd_dma_rcv_setting(usb_utr_t * ptr, uint32_t des_addr, uint16_t useport, uint32_t transfer_size); +void usb_cstd_dma_send_setting(usb_utr_t * ptr, uint32_t src_adr, uint16_t useport, uint32_t transfer_size); +void usb_cstd_dma_stop(usb_utr_t * p_utr, uint16_t use_port); +void usb_cstd_dfifo_end(usb_utr_t * ptr, uint16_t useport); +uint32_t hw_usb_get_dxfifo_adr(usb_utr_t * ptr, uint16_t use_port, uint16_t bit_width); + +uint8_t usb_cstd_dma_ref_ch_no(usb_utr_t * p_utr, uint16_t use_port); +void usb_cstd_dma_send_continue(usb_utr_t * ptr, uint16_t useport); + +void usb_cstd_dma_rcv_start(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +void usb_cstd_dma_send_start(usb_utr_t * ptr, uint16_t pipe, uint16_t useport); +void usb_cstd_dma_send_restart(usb_utr_t * ptr, uint32_t src, uint32_t data_size, uint8_t pipe); +void usb_cstd_dma_send_complete(uint8_t ip_no, uint16_t use_port); + +void usb_ip0_d0fifo_callback(dmac_callback_args_t * cb_data); +void usb_ip0_d1fifo_callback(dmac_callback_args_t * cb_data); +void usb_ip1_d0fifo_callback(dmac_callback_args_t * cb_data); +void usb_ip1_d1fifo_callback(dmac_callback_args_t * cb_data); + +#endif /* ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* R_USB_DMAC_H */ + +/****************************************************************************** + * End Of File + ******************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h new file mode 100644 index 00000000..54dab35a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h @@ -0,0 +1,452 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ +#ifndef HW_USB_REG_ACCESS_H + #define HW_USB_REG_ACCESS_H + + #ifdef __cplusplus +extern "C" { + #endif + +/****************************************************************************** + * Macro definitions + ******************************************************************************/ + #define USB_BUFSIZE_BIT (10U) + #define USB_SUSPEND_MODE (1U) + #define USB_NORMAL_MODE (0) + + #define USB0_CFIFO8 (USB_M0->CFIFOLL) + #define USB0_D0FIFO8 (USB_M0->D0FIFOLL) + #define USB0_D1FIFO8 (USB_M0->D1FIFOLL) + #define USB0_CFIFO16 (USB_M0->CFIFOL) + #define USB0_D0FIFO16 (USB_M0->D0FIFOL) + #define USB0_D1FIFO16 (USB_M0->D1FIFOL) + + #if USB_CFG_ENDIAN == USB_CFG_LITTLE + + #define USB1_CFIFO8 (USB_M1->CFIFOHH) + #define USB1_D0FIFO8 (USB_M1->D0FIFOHH) + #define USB1_D1FIFO8 (USB_M1->D1FIFOHH) + #define USB1_CFIFO16 (USB_M1->CFIFOH) + #define USB1_D0FIFO16 (USB_M1->D0FIFOH) + #define USB1_D1FIFO16 (USB_M1->D1FIFOH) + + #endif /* USB_CFG_ENDIAN == USB_CFG_LITTLE */ + + #if USB_CFG_ENDIAN == USB_CFG_BIG + #define USB1_CFIFO8 (USB_M1->CFIFOLL) + #define USB1_D0FIFO8 (USB_M1->D0FIFOLL) + #define USB1_D1FIFO8 (USB_M1->D1FIFOLL) + #define USB1_CFIFO16 (USB_M1->CFIFOL) + #define USB1_D0FIFO16 (USB_M1->D0FIFOL) + #define USB1_D1FIFO16 (USB_M1->D1FIFOL) + + #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + + #define USB1_CFIFO32 (USB_M1->CFIFO) + #define USB1_D0FIFO32 (USB_M1->D0FIFO) + #define USB1_D1FIFO32 (USB_M1->D1FIFO) + + #if (defined(BSP_MCU_GROUP_RA2A1) || defined(BSP_MCU_GROUP_RA4M1)) + #define USB_LDO_REGULATOR_MODULE + #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + +/****************/ +/* INITIARIZE */ +/****************/ +void hw_usb_hmodule_init(uint8_t usb_ip); +void hw_usb_pmodule_init(uint8_t usb_ip); + +/************/ +/* SYSCFG */ +/************/ +uint16_t hw_usb_read_syscfg(usb_utr_t * ptr); +void hw_usb_write_syscfg(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_cnen(usb_utr_t * ptr); +void hw_usb_set_hse(usb_utr_t * ptr); +void hw_usb_clear_hse(usb_utr_t * ptr); +void hw_usb_set_dcfm(usb_utr_t * p_utr); +void hw_usb_clear_dcfm(usb_utr_t * ptr); +void hw_usb_set_drpd(usb_utr_t * ptr); +void hw_usb_clear_drpd(usb_utr_t * ptr); +void hw_usb_set_usbe(usb_utr_t * ptr); +void hw_usb_clear_usbe(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_set_cnen(uint8_t usb_ip); +void hw_usb_pset_dprpu(uint8_t usb_ip); +void hw_usb_pclear_dprpu(uint8_t usb_ip); +void hw_usb_pcontrol_dprpu(uint8_t usb_ip, uint8_t state); +void hw_usb_pcontrol_dcpctr_pid(uint8_t usb_ip, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* BUSWAIT */ +/************/ +void hw_usb_set_buswait(usb_utr_t * ptr); + +/************/ +/* SYSSTS0 */ +/************/ +uint16_t hw_usb_read_syssts(usb_utr_t * ptr); + +/**************/ +/* DVSTCTR0 */ +/**************/ +uint16_t hw_usb_read_dvstctr(usb_utr_t * ptr); +void hw_usb_write_dvstctr(usb_utr_t * ptr, uint16_t data); +void hw_usb_rmw_dvstctr(usb_utr_t * ptr, uint16_t data, uint16_t bitptn); +void hw_usb_clear_dvstctr(usb_utr_t * ptr, uint16_t bitptn); +void hw_usb_set_vbout(usb_utr_t * ptr); +void hw_usb_clear_vbout(usb_utr_t * ptr); +void hw_usb_set_hnpbtoa(usb_utr_t * p_utr); +void hw_usb_clear_hnpbtoa(usb_utr_t * p_utr); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_rwupe(usb_utr_t * ptr); +void hw_usb_hclear_rwupe(usb_utr_t * ptr); +void hw_usb_hset_resume(usb_utr_t * ptr); +void hw_usb_hclear_resume(usb_utr_t * ptr); +void hw_usb_hset_uact(usb_utr_t * ptr); +void hw_usb_hclear_uact(usb_utr_t * ptr); +void hw_usb_hmodule_otg_init(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_pset_wkup(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/**************/ +/* TESTMODE */ +/**************/ +void hw_usb_set_utst(usb_utr_t * ptr, uint16_t data); + +/***************************/ +/* CFIFO, D0FIFO, D1FIFO */ +/***************************/ +uint32_t hw_usb_read_fifo32(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_write_fifo32(usb_utr_t * ptr, uint16_t pipemode, uint32_t data); +uint16_t hw_usb_read_fifo16(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_write_fifo16(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); +void hw_usb_write_fifo8(usb_utr_t * ptr, uint16_t pipemode, uint8_t data); + +/************************************/ +/* CFIFOSEL, D0FIFOSEL, D1FIFOSEL */ +/************************************/ +uint16_t hw_usb_read_fifosel(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_rmw_fifosel(usb_utr_t * ptr, uint16_t pipemode, uint16_t data, uint16_t bitptn); +void hw_usb_set_dclrm(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_clear_dclrm(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_dreqe(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_clear_dreqe(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_mbw(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); +void hw_usb_set_curpipe(usb_utr_t * ptr, uint16_t pipemode, uint16_t pipeno); + +/**********************************/ +/* CFIFOCTR, D0FIFOCTR, D1FIFOCTR */ +/**********************************/ +uint16_t hw_usb_read_fifoctr(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_bval(usb_utr_t * ptr, uint16_t pipemode); +void hw_usb_set_bclr(usb_utr_t * ptr, uint16_t pipemode); + +/*************/ +/* INTENB0 */ +/*************/ +uint16_t hw_usb_ReadIntenb(usb_utr_t * ptr); +void hw_usb_write_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_enb_vbse(usb_utr_t * ptr); +void hw_usb_clear_enb_sofe(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +void hw_usb_pset_enb_rsme(uint8_t usb_ip); +void hw_usb_pclear_enb_rsme(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/*************/ +/* BRDYENB */ +/*************/ +void hw_usb_write_brdyenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_brdyenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_brdyenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* NRDYENB */ +/*************/ +void hw_usb_write_nrdyenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_nrdyenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_nrdyenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* BEMPENB */ +/*************/ +void hw_usb_write_bempenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_set_bempenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_bempenb(usb_utr_t * ptr, uint16_t pipeno); + +/*************/ +/* SOFCFG */ +/*************/ +void hw_usb_set_sofcfg(usb_utr_t * ptr, uint16_t data); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_trnensel(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/*************/ +/* INTSTS0 */ +/*************/ +void hw_usb_write_intsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_sts_sofr(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint16_t hw_usb_read_intsts(uint8_t usb_ip); +void hw_usb_pclear_sts_resm(uint8_t usb_ip); +void hw_usb_pclear_sts_valid(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* BRDYSTS */ +/************/ +uint16_t hw_usb_read_brdysts(usb_utr_t * ptr); +void hw_usb_write_brdysts(usb_utr_t * pt, uint16_t data); +void hw_usb_clear_sts_brdy(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* NRDYSTS */ +/************/ +void hw_usb_write_nrdy_sts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_status_nrdy(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* BEMPSTS */ +/************/ +void hw_usb_write_bempsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_status_bemp(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* FRMNUM */ +/************/ +uint16_t hw_usb_read_frmnum(usb_utr_t * ptr); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/************/ +/* USBREQ */ +/************/ +void hw_usb_hwrite_usbreq(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBVAL */ +/************/ +void hw_usb_hset_usbval(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBINDX */ +/************/ +void hw_usb_hset_usbindx(usb_utr_t * ptr, uint16_t data); + +/************/ +/* USBLENG */ +/************/ +void hw_usb_hset_usbleng(usb_utr_t * ptr, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) + +/************/ +/* USBREQ */ +/************/ +uint16_t hw_usb_read_usbreq(uint8_t usb_ip); + +/************/ +/* USBVAL */ +/************/ +uint16_t hw_usb_read_usbval(uint8_t usb_ip); + +/************/ +/* USBINDX */ +/************/ +uint16_t hw_usb_read_usbindx(uint8_t usb_ip); + +/************/ +/* USBLENG */ +/************/ +uint16_t hw_usb_read_usbleng(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* DCPCFG */ +/************/ +uint16_t hw_usb_read_dcpcfg(usb_utr_t * ptr); +void hw_usb_write_dcpcfg(usb_utr_t * ptr, uint16_t data); + +/************/ +/* DCPMAXP */ +/************/ +uint16_t hw_usb_read_dcpmaxp(usb_utr_t * ptr); +void hw_usb_write_dcpmxps(usb_utr_t * ptr, uint16_t data); + +/************/ +/* DCPCTR */ +/************/ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hwrite_dcpctr(usb_utr_t * ptr, uint16_t data); +void hw_usb_hset_sureq(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) +uint16_t hw_usb_read_dcpctr(uint8_t usb_ip); +void hw_usb_pset_ccpl(uint8_t usb_ip); + + #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ + +/************/ +/* PIPESEL */ +/************/ +void hw_usb_write_pipesel(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPECFG */ +/************/ +uint16_t hw_usb_read_pipecfg(usb_utr_t * ptr); +void hw_usb_write_pipecfg(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPEBUF */ +/************/ +void hw_usb_write_pipebuf(usb_utr_t * ptr, uint16_t data); +uint16_t hw_usb_read_pipebuf(usb_utr_t * ptr); + +/************/ +/* PIPEMAXP */ +/************/ +uint16_t hw_usb_read_pipemaxp(usb_utr_t * ptr); +void hw_usb_write_pipemaxp(usb_utr_t * ptr, uint16_t data); + +/************/ +/* PIPEPERI */ +/************/ +void hw_usb_write_pipeperi(usb_utr_t * ptr, uint16_t data); + +/********************/ +/* DCPCTR, PIPEnCTR */ +/********************/ +uint16_t hw_usb_read_pipectr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_write_pipectr(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); +void hw_usb_set_csclr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_aclrm(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_aclrm(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_sqclr(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_sqset(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_pid(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); +void hw_usb_clear_pid(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); + +/************/ +/* PIPEnTRE */ +/************/ +void hw_usb_set_trenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_clear_trenb(usb_utr_t * ptr, uint16_t pipeno); +void hw_usb_set_trclr(usb_utr_t * ptr, uint16_t pipeno); + +/************/ +/* PIPEnTRN */ +/************/ +void hw_usb_write_pipetrn(usb_utr_t * ptr, uint16_t pipeno, uint16_t data); + +/************/ +/* BCCTRL */ +/************/ +void hw_usb_set_bcctrl(usb_utr_t * ptr, uint16_t data); +void hw_usb_clear_bcctrl(usb_utr_t * ptr, uint16_t data); +uint16_t hw_usb_read_bcctrl(usb_utr_t * ptr); +void hw_usb_set_vdmsrce(usb_utr_t * ptr); +void hw_usb_clear_vdmsrce(usb_utr_t * ptr); +void hw_usb_set_idpsinke(usb_utr_t * ptr); +void hw_usb_set_suspendm(uint8_t usb_ip); +void hw_usb_clear_suspm(uint8_t usb_ip); +void hw_usb_clear_idpsinke(usb_utr_t * ptr); +void hw_usb_set_vdcen(void); +void hw_usb_clear_vdcen(void); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +void hw_usb_hset_dcpmode(usb_utr_t * ptr); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + +/**********************************/ +/* DMA0CFG, DMA1CFG for 597ASSP */ +/**********************************/ +void hw_usb_write_dmacfg(usb_utr_t * ptr, uint16_t pipemode, uint16_t data); + + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) + +/*************/ +/* INTENB1 */ +/*************/ +void hw_usb_hwrite_intenb(usb_utr_t * ptr, uint16_t data); +void hw_usb_hset_enb_ovrcre(usb_utr_t * ptr); +void hw_usb_hclear_enb_ovrcre(usb_utr_t * ptr); +void hw_usb_hset_enb_bchge(usb_utr_t * ptr); +void hw_usb_hclear_enb_bchge(usb_utr_t * ptr); +void hw_usb_hset_enb_dtche(usb_utr_t * ptr); +void hw_usb_hclear_enb_dtche(usb_utr_t * ptr); +void hw_usb_hset_enb_attche(usb_utr_t * ptr); +void hw_usb_hclear_enb_attche(usb_utr_t * ptr); +void hw_usb_hset_enb_signe(usb_utr_t * ptr); +void hw_usb_hset_enb_sacke(usb_utr_t * ptr); +void hw_usb_hset_enb_pddetinte(usb_utr_t * ptr); + +/*************/ +/* INTSTS1 */ +/*************/ +void hw_usb_hwrite_intsts(usb_utr_t * ptr, uint16_t data); +void hw_usb_hclear_sts_ovrcr(usb_utr_t * ptr); +void hw_usb_hclear_sts_bchg(usb_utr_t * ptr); +void hw_usb_hclear_sts_dtch(usb_utr_t * ptr); +void hw_usb_hclear_sts_attch(usb_utr_t * ptr); +void hw_usb_hclear_sts_sign(usb_utr_t * ptr); +void hw_usb_hclear_sts_sack(usb_utr_t * ptr); +void hw_usb_hclear_sts_pddetint(usb_utr_t * ptr); + +/************/ +/* DEVADDn */ +/************/ +uint16_t hw_usb_hread_devadd(usb_utr_t * ptr, uint16_t devsel); +void hw_usb_hrmw_devadd(usb_utr_t * ptr, uint16_t devsel, uint16_t data, uint16_t width); +void hw_usb_hset_usbspd(usb_utr_t * ptr, uint16_t devsel, uint16_t data); + + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + + #ifdef __cplusplus +} + #endif + +#endif /* HW_USB_REG_ACCESS_H */ + +/****************************************************************************** + * End of file + ******************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h new file mode 100644 index 00000000..6a84d85a --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra/fsp/src/r_usb_pcdc/src/inc/r_usb_pcdc.h @@ -0,0 +1,44 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_USB_PCDC_LOCAL_H +#define R_USB_PCDC_LOCAL_H + +/****************************************************************************** + Includes , "Project Includes" + ******************************************************************************/ + +/***************************************************************************** + Macro definitions + ******************************************************************************/ + +/****************************************************************************** + Exported global variables + ******************************************************************************/ + +/****************************************************************************** + Exported global functions (to be accessed by other files) +******************************************************************************/ + + +#endif /* R_USB_PCDC_LOCAL_H */ +/****************************************************************************** + End Of File + ******************************************************************************/ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/driver/r_qspi_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/driver/r_qspi_cfg.h new file mode 100644 index 00000000..5bcdd123 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/driver/r_qspi_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_QSPI_CFG_H_ +#define R_QSPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define QSPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define QSPI_CFG_SUPPORT_EXTENDED_SPI_MULTI_LINE_PROGRAM (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_QSPI_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/board_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 00000000..2e11f5ac --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +void bsp_init(void *p_args); + +#ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 00000000..d4aebc83 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,59 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 00000000..bd6a901c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 00000000..2f0e4c29 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5AH3CFP +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 00000000..a0429fff --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,370 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((2 > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((2 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((1 > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((1 > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((1 > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((1 > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((1 > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((1 > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((1 > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((1 > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((10 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((1 > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((1 > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if 9 == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else +#define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 00000000..f27fd05d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5AH3CFP.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* BSP_PIN_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_adc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 00000000..be8a4272 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ADC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_agt_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 00000000..c100353d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (1) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_AGT_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ble_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ble_cfg.h new file mode 100644 index 00000000..533482e8 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ble_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef R_BLE_CFG_H_ +#define R_BLE_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define BLE_CFG_LIBRARY_TYPE 0 +#define BLE_CFG_RF_DEBUG_PUBLIC_ADDRESS {0xFF,0xFF,0xFF,0x50,0x90,0x74} +#define BLE_CFG_RF_DEBUG_RANDOM_ADDRESS {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} +#define BLE_CFG_RF_CONNECTION_MAXIMUM (7) +#define BLE_CFG_RF_CONNECTION_DATA_MAXIMUM (251) +#define BLE_CFG_RF_ADVERTISING_DATA_MAXIMUM (1650) +#define BLE_CFG_RF_ADVERTISING_SET_MAXIMUM (4) +#define BLE_CFG_RF_SYNC_SET_MAXIMUM (2) +#define BLE_CFG_ENABLE_SECURE_DATA (0) +#define BLE_CFG_SECURE_DATA_DATAFLASH_BLOCK (0) +#define BLE_CFG_NUMBER_BONDING (7) +#define BLE_CFG_EVENT_NOTIFY_CONNECTION_START (0) +#define BLE_CFG_EVENT_NOTIFY_CONNECTION_CLOSE (0) +#define BLE_CFG_EVENT_NOTIFY_ADVERTISING_START (0) +#define BLE_CFG_EVENT_NOTIFY_ADVERTISING_CLOSE (0) +#define BLE_CFG_EVENT_NOTIFY_SCANNING_START (0) +#define BLE_CFG_EVENT_NOTIFY_SCANNING_CLOSE (0) +#define BLE_CFG_EVENT_NOTIFY_INITIATING_START (0) +#define BLE_CFG_EVENT_NOTIFY_INITIATING_CLOSE (0) +#define BLE_CFG_EVENT_NOTIFY_DEEP_SLEEP_START (0) +#define BLE_CFG_EVENT_NOTIFY_DEEP_SLEEP_WAKEUP (0) +#define BLE_CFG_RF_CLVAL (6) +#define BLE_CFG_RF_DCDC_CONVERTER_ENABLE (0) +#define BLE_CFG_RF_EXT32K_EN (0) +#define BLE_CFG_RF_MCU_CLKOUT_PORT (0) +#define BLE_CFG_RF_MCU_CLKOUT_FREQ (0) +#define BLE_CFG_RF_SCA (250) +#define BLE_CFG_RF_MAX_TX_POW (1) +#define BLE_CFG_RF_DEF_TX_POW (0) +#define BLE_CFG_RF_CLKOUT_EN (0) +#define BLE_CFG_RF_DEEP_SLEEP_EN (1) +#define BLE_CFG_MCU_MAIN_CLK_KHZ (8000) +#define BLE_CFG_DEV_DATA_CF_BLOCK (255) +#define BLE_CFG_DEV_DATA_DF_BLOCK (-1) +#define BLE_CFG_GATT_MTU_SIZE (247) +#define BLE_CFG_TIMER_NUMBER_OF_SLOT (10) +#define BLE_CFG_EVENT_NOTIFY_ENABLE_VAL (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_BLE_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_cgc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_cgc_cfg.h new file mode 100644 index 00000000..0501e2be --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_cgc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_CGC_CFG_H_ +#define R_CGC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CGC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define CGC_CFG_USE_LOW_VOLTAGE_MODE RA_NOT_DEFINED + +#ifdef __cplusplus +} +#endif +#endif /* R_CGC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_crc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_crc_cfg.h new file mode 100644 index 00000000..ec619e7e --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_crc_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_CRC_CFG_H_ +#define R_CRC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CRC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_CRC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dac_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dac_cfg.h new file mode 100644 index 00000000..5924bc46 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dac_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DAC_CFG_H_ +#define R_DAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DAC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dmac_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dmac_cfg.h new file mode 100644 index 00000000..4ece7d37 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dmac_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DMAC_CFG_H_ +#define R_DMAC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DMAC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_DMAC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dtc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 00000000..fea5e9c9 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" + +#ifdef __cplusplus +} +#endif +#endif /* R_DTC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_elc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_elc_cfg.h new file mode 100644 index 00000000..84f408f9 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_elc_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ELC_CFG_H_ +#define R_ELC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ELC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ELC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_flash_hp_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_flash_hp_cfg.h new file mode 100644 index 00000000..0c23b89e --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_flash_hp_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (1) + +#ifdef __cplusplus + } + #endif +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_gpt_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_gpt_cfg.h new file mode 100644 index 00000000..9a7e0697 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_gpt_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_GPT_CFG_H_ +#define R_GPT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define GPT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define GPT_CFG_OUTPUT_SUPPORT_ENABLE (2) +#define GPT_CFG_WRITE_PROTECT_ENABLE (0) +#define GPT_CFG_GPTCLK_BYPASS 1 + +#ifdef __cplusplus +} +#endif +#endif /* R_GPT_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_icu_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 00000000..85fb06ed --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_ICU_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_master_cfg.h new file mode 100644 index 00000000..d3e9396b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_master_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (1) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_slave_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_slave_cfg.h new file mode 100644 index 00000000..004a988d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_iic_slave_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_SLAVE_CFG_H_ +#define R_IIC_SLAVE_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IIC_SLAVE_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IIC_SLAVE_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ioport_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 00000000..d2688bf5 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_lpm_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 00000000..586222f5 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define LPM_CFG_STANDBY_LIMIT (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_LPM_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_rtc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 00000000..7e95d5ea --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (1) + +#ifdef __cplusplus +} +#endif +#endif /* R_RTC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sce_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sce_cfg.h new file mode 100644 index 00000000..305fcc9d --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sce_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCE_CFG_H_ +#define R_SCE_CFG_H_ +#define SCE_RSA_RETRY_COUNT_FOR_RSA_KEY_GENERATION 10240 +#define SCE_USER_SHA_384_ENABLED (0) +#define SCE_USER_SHA_384_FUNCTION crypto_sha384_user_function +#endif /* R_SCE_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_i2c_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_i2c_cfg.h new file mode 100644 index 00000000..c7e30f61 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_i2c_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_I2C_CFG_H_ +#define R_SCI_I2C_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SIIC_CFG_PREREQUISITE_CHECKING_ENABLE 1 +#define SCI_I2C_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_I2C_CFG_DTC_ENABLE (1) +#define SCI_I2C_CFG_ADDR_MODE_10_BIT_ENABLE (0) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_I2C_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_spi_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_spi_cfg.h new file mode 100644 index 00000000..5d23557c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_spi_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_SPI_CFG_H_ +#define R_SCI_SPI_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define SCI_SPI_DTC_SUPPORT_ENABLE (1) +#define SCI_SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_SCI_SPI_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 00000000..a6f61400 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (1) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#define SCI_UART_CFG_RS485_SUPPORT (0) + +#ifdef __cplusplus + } + #endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sdhi_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sdhi_cfg.h new file mode 100644 index 00000000..ae9b39cd --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_sdhi_cfg.h @@ -0,0 +1,20 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SDHI_CFG_H_ +#define R_SDHI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SDHI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SDMMC_CFG_UNALIGNED_ACCESS_ENABLE (1) +#ifndef SDHI_CFG_SD_SUPPORT_ENABLE +#define SDHI_CFG_SD_SUPPORT_ENABLE ((1)) +#endif +#ifndef SDHI_CFG_EMMC_SUPPORT_ENABLE +#define SDHI_CFG_EMMC_SUPPORT_ENABLE ((0)) +#endif + +#ifdef __cplusplus + } + #endif +#endif /* R_SDHI_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_spi_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 00000000..e9fd1386 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,18 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DMA_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) + +/* DEPRECATED: Use SPI_DMA_SUPPORT_ENABLE instead. */ +#define SPI_DTC_SUPPORT_ENABLE (SPI_DMA_SUPPORT_ENABLE) + +#ifdef __cplusplus + } + #endif +#endif /* R_SPI_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ssi_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ssi_cfg.h new file mode 100644 index 00000000..6e840862 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_ssi_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SSI_CFG_H_ +#define R_SSI_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define SSI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SSI_CFG_DTC_ENABLE (1) + +#ifdef __cplusplus + } + #endif +#endif /* R_SSI_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_basic_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_basic_cfg.h new file mode 100644 index 00000000..390ca297 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_basic_cfg.h @@ -0,0 +1,104 @@ +/* generated configuration header file - do not edit */ +#ifndef R_USB_BASIC_CFG_H_ +#define R_USB_BASIC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#ifndef NULL +extern const uint16_t NULL[]; +#endif + +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HVND_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif +#if (1 != RA_NOT_DEFINED) +#define USB_CFG_PCDC_USE +#endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PVND_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HCDC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HMSC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HHID_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_HPRN_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PCDC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PPRN_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PHID_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PMSC_USE + #endif +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #define USB_CFG_PAUD_USE + #endif +#if ((RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED) || (RA_NOT_DEFINED != RA_NOT_DEFINED)) + #define USB_CFG_OTG_USE + #endif +#if (defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HPRN_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HVND_USE)) + #define USB_CFG_HOST_MODE 1 + #else +#define USB_CFG_HOST_MODE 0 +#endif + +#if (defined(USB_CFG_PCDC_USE) || defined(USB_CFG_PPRN_USE) || defined(USB_CFG_PMSC_USE) || defined(USB_CFG_PHID_USE) || defined(USB_CFG_PVND_USE) || defined(USB_CFG_PAUD_USE)) +#define USB_CFG_PERI_MODE 2 +#else + #define USB_CFG_PERI_MODE 0 + #endif + +#define USB_CFG_MODE (USB_CFG_PERI_MODE | USB_CFG_HOST_MODE) + +#define USB_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define USB_CFG_CLKSEL (USB_CFG_24MHZ) +#define USB_CFG_BUSWAIT (USB_CFG_BUSWAIT_7) +#define USB_CFG_BC (USB_CFG_ENABLE) +#define USB_CFG_VBUS (USB_CFG_HIGH) +#define USB_CFG_DCP (USB_CFG_DISABLE) +#define USB_CFG_CLASS_REQUEST (USB_CFG_ENABLE) +#define USB_CFG_DBLB (USB_CFG_DBLBON) +#define USB_CFG_CNTMD (USB_CFG_CNTMDOFF) +#define USB_CFG_LDO_REGULATOR (USB_CFG_DISABLE) +#define USB_CFG_DMA (USB_CFG_DISABLE) +#define USB_SRC_ADDRESS (NULL) +#define USB_DEST_ADDRESS (NULL) +#define USB_CFG_TPLCNT (1) +#define USB_CFG_TPL USB_NOVENDOR, USB_NOPRODUCT +#define USB_CFG_TPL_TABLE NULL +#define USB_CFG_COMPLIANCE (USB_CFG_DISABLE) + +#ifdef __cplusplus + } + #endif +#endif /* R_USB_BASIC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_class_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_class_cfg.h new file mode 100644 index 00000000..7f78a4cb --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_class_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_USB_CLASS_CFG_H_ +#define R_USB_CLASS_CFG_H_ + +#endif /* R_USB_CLASS_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_pcdc_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_pcdc_cfg.h new file mode 100644 index 00000000..af17755c --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_usb_pcdc_cfg.h @@ -0,0 +1,23 @@ +/* generated configuration header file - do not edit */ +#ifndef R_USB_PCDC_CFG_H_ +#define R_USB_PCDC_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#if (RA_NOT_DEFINED != RA_NOT_DEFINED) + #include "r_usb_pcdc_2ch_cfg.h" + #else +#define USB_CFG_PCDC_BULK_IN2 (USB_NULL) +#define USB_CFG_PCDC_BULK_OUT2 (USB_NULL) +#define USB_CFG_PCDC_INT_IN2 (USB_NULL) +#endif + +#define USB_CFG_PCDC_BULK_IN (USB_PIPE1) +#define USB_CFG_PCDC_BULK_OUT (USB_PIPE2) +#define USB_CFG_PCDC_INT_IN (USB_PIPE6) + +#ifdef __cplusplus + } + #endif +#endif /* R_USB_PCDC_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_wdt_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_wdt_cfg.h new file mode 100644 index 00000000..41bf58b1 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_cfg/fsp_cfg/r_wdt_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef R_WDT_CFG_H_ +#define R_WDT_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#define WDT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define WDT_CFG_REGISTER_START_NMI_SUPPORTED ((0)) + +#ifdef __cplusplus + } + #endif +#endif /* R_WDT_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_gen/bsp_clock_cfg.h b/variants/THINGPLUS_RA6M5/includes/ra_gen/bsp_clock_cfg.h new file mode 100644 index 00000000..c857a47b --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,31 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* BCLK/2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_gen/common_data.h b/variants/THINGPLUS_RA6M5/includes/ra_gen/common_data.h new file mode 100644 index 00000000..80ca4682 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_gen/common_data.h @@ -0,0 +1,51 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_elc.h" +#include "r_elc_api.h" +#include "r_cgc.h" +#include "r_cgc_api.h" +#include "r_sce.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/** ELC Instance */ +extern const elc_instance_t g_elc; + +/** Access the ELC instance using these structures when calling API functions directly (::p_api is not used). */ +extern elc_instance_ctrl_t g_elc_ctrl; +extern const elc_cfg_t g_elc_cfg; +/** CGC Instance */ +extern const cgc_instance_t g_cgc0; + +/** Access the CGC instance using these structures when calling API functions directly (::p_api is not used). */ +extern cgc_instance_ctrl_t g_cgc0_ctrl; +extern const cgc_cfg_t g_cgc0_cfg; + +#ifndef NULL +void NULL(cgc_callback_args_t *p_args); +#endif +extern sce_instance_ctrl_t sce_ctrl; +extern const sce_cfg_t sce_cfg; +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef NULL +void NULL(external_irq_callback_args_t *p_args); +#endif +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_gen/hal_data.h b/variants/THINGPLUS_RA6M5/includes/ra_gen/hal_data.h new file mode 100644 index 00000000..121dd759 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_gen/hal_data.h @@ -0,0 +1,323 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_sci_i2c.h" +#include "r_i2c_master_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_gpt.h" +#include "r_timer_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_dmac.h" +#include "r_transfer_api.h" +#include "r_sci_spi.h" +#include "r_spi_api.h" +#include "r_spi.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +#include "r_wdt.h" +#include "r_wdt_api.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sdhi.h" +#include "r_sdmmc_api.h" +#include "r_qspi.h" +#include "r_spi_flash_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_crc.h" +#include "r_crc_api.h" +#include "r_usb_basic.h" +#include "r_usb_basic_api.h" +#include "r_usb_pcdc_api.h" +#include "r_i2s_api.h" +#include "r_ssi.h" +#include "r_iic_slave.h" +#include "r_i2c_slave_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_dac.h" +#include "r_dac_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +FSP_HEADER +extern const i2c_master_cfg_t g_i2c0_cfg; +/* I2C on SCI Instance. */ +extern const i2c_master_instance_t g_i2c0; +#ifndef sci_i2c_master_callback +void sci_i2c_master_callback(i2c_master_callback_args_t *p_args); +#endif + +extern const sci_i2c_extended_cfg_t g_i2c0_cfg_extend; +extern sci_i2c_instance_ctrl_t g_i2c0_ctrl; +/** AGT Timer Instance */ +extern const timer_instance_t g_timer1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t *p_args); +#endif +/** Timer on GPT Instance. */ +extern const timer_instance_t g_timer0; + +/** Access the GPT instance using these structures when calling API functions directly (::p_api is not used). */ +extern gpt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef NULL +void NULL(timer_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer7; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer7_ctrl; +extern const transfer_cfg_t g_transfer7_cfg; +/* Transfer on DMAC Instance. */ +extern const transfer_instance_t g_transfer12; + +/** Access the DMAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dmac_instance_ctrl_t g_transfer12_ctrl; +extern const transfer_cfg_t g_transfer12_cfg; + +#ifndef NULL +void NULL(dmac_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer11; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer11_ctrl; +extern const transfer_cfg_t g_transfer11_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer4; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer4_ctrl; +extern const transfer_cfg_t g_transfer4_cfg; +/** SPI on SCI Instance. */ +extern const spi_instance_t g_spi1; + +/** Access the SCI_SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_spi_instance_ctrl_t g_spi1_ctrl; +extern const spi_cfg_t g_spi1_cfg; + +/** Called by the driver when a transfer has completed or an error has occurred (Must be implemented by the user). */ +#ifndef sci_spi_callback +void sci_spi_callback(spi_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer2; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer2_ctrl; +extern const transfer_cfg_t g_transfer2_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer1) +#endif +#if (RA_NOT_DEFINED == g_transfer2) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer2) +#endif +#undef RA_NOT_DEFINED +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer6; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer6_ctrl; +extern const transfer_cfg_t g_transfer6_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer5; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer5_ctrl; +extern const transfer_cfg_t g_transfer5_cfg; +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart1; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart1_ctrl; +extern const uart_cfg_t g_uart1_cfg; +extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; + +#ifndef NULL +void NULL(uart_callback_args_t *p_args); +#endif +/** WDT on WDT Instance. */ +extern const wdt_instance_t g_wdt0; + +/** Access the WDT instance using these structures when calling API functions directly (::p_api is not used). */ +extern wdt_instance_ctrl_t g_wdt0_ctrl; +extern const wdt_cfg_t g_wdt0_cfg; + +#ifndef NULL +void NULL(wdt_callback_args_t *p_args); +#endif +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer3; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer3_ctrl; +extern const transfer_cfg_t g_transfer3_cfg; +/** SDMMC on SDMMC Instance. */ +extern const sdmmc_instance_t g_sdmmc0; + +/** Access the SDMMC instance using these structures when calling API functions directly (::p_api is not used). */ +extern sdhi_instance_ctrl_t g_sdmmc0_ctrl; +extern sdmmc_cfg_t g_sdmmc0_cfg; + +#ifndef NULL +void NULL(sdmmc_callback_args_t *p_args); +#endif +extern const spi_flash_instance_t g_qspi0; +extern qspi_instance_ctrl_t g_qspi0_ctrl; +extern const spi_flash_cfg_t g_qspi0_cfg; +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +extern const crc_instance_t g_crc0; +extern crc_instance_ctrl_t g_crc0_ctrl; +extern const crc_cfg_t g_crc0_cfg; +/* Basic on USB Instance. */ +extern const usb_instance_t g_basic0; + +/** Access the USB instance using these structures when calling API functions directly (::p_api is not used). */ +extern usb_instance_ctrl_t g_basic0_ctrl; +extern const usb_cfg_t g_basic0_cfg; + +#ifndef NULL +void NULL(void*); +#endif + +#if 2 == BSP_CFG_RTOS +#ifndef NULL +void NULL(usb_event_info_t *, usb_hdl_t, usb_onoff_t); +#endif +#endif +/** CDC Driver on USB Instance. */ +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart0; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart0_ctrl; +extern const uart_cfg_t g_uart0_cfg; +extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + +#ifndef NULL +void NULL(uart_callback_args_t *p_args); +#endif +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SSI Instance. */ +extern const i2s_instance_t g_i2s0; + +/** Access the SSI instance using these structures when calling API functions directly (::p_api is not used). */ +extern ssi_instance_ctrl_t g_i2s0_ctrl; +extern const i2s_cfg_t g_i2s0_cfg; + +#ifndef NULL +void NULL(i2s_callback_args_t *p_args); +#endif +/** I2C Slave on IIC Instance. */ +extern const i2c_slave_instance_t g_i2c_slave0; + +/** Access the I2C Slave instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_slave_instance_ctrl_t g_i2c_slave0_ctrl; +extern const i2c_slave_cfg_t g_i2c_slave0_cfg; + +#ifndef NULL +void NULL(i2c_slave_callback_args_t *p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef NULL +void NULL(i2c_master_callback_args_t *p_args); +#endif +/** DAC on DAC Instance. */ +extern const dac_instance_t g_dac0; + +/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dac_instance_ctrl_t g_dac0_ctrl; +extern const dac_cfg_t g_dac0_cfg; +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif + +#ifndef NULL +#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL 0 +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/variants/THINGPLUS_RA6M5/includes/ra_gen/vector_data.h b/variants/THINGPLUS_RA6M5/includes/ra_gen/vector_data.h new file mode 100644 index 00000000..141afc75 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/includes/ra_gen/vector_data.h @@ -0,0 +1,112 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +#ifdef __cplusplus + extern "C" { + #endif +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (33) +#endif +/* ISR prototypes */ +void iic_slave_rxi_isr(void); +void iic_slave_txi_isr(void); +void iic_slave_tei_isr(void); +void iic_slave_eri_isr(void); +void ssi_txi_isr(void); +void ssi_int_isr(void); +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void usbfs_interrupt_handler(void); +void usbfs_resume_handler(void); +void usbfs_d0fifo_handler(void); +void usbfs_d1fifo_handler(void); +void usbhs_interrupt_handler(void); +void usbhs_d0fifo_handler(void); +void usbhs_d1fifo_handler(void); +void r_icu_isr(void); +void sdhimmc_accs_isr(void); +void sdhimmc_dma_req_isr(void); +void rtc_carry_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void sci_i2c_rxi_isr(void); +void sci_i2c_txi_isr(void); +void sci_i2c_tei_isr(void); +void sci_spi_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type) 0) /* IIC0 RXI (Receive data full) */ +#define IIC0_RXI_IRQn ((IRQn_Type) 0) /* IIC0 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type) 1) /* IIC0 TXI (Transmit data empty) */ +#define IIC0_TXI_IRQn ((IRQn_Type) 1) /* IIC0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type) 2) /* IIC0 TEI (Transmit end) */ +#define IIC0_TEI_IRQn ((IRQn_Type) 2) /* IIC0 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type) 3) /* IIC0 ERI (Transfer error) */ +#define IIC0_ERI_IRQn ((IRQn_Type) 3) /* IIC0 ERI (Transfer error) */ +#define VECTOR_NUMBER_SSI0_TXI ((IRQn_Type) 4) /* SSI0 TXI (Transmit data empty) */ +#define SSI0_TXI_IRQn ((IRQn_Type) 4) /* SSI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SSI0_INT ((IRQn_Type) 5) /* SSI0 INT (Error interrupt) */ +#define SSI0_INT_IRQn ((IRQn_Type) 5) /* SSI0 INT (Error interrupt) */ +#define VECTOR_NUMBER_SCI3_RXI ((IRQn_Type) 6) /* SCI3 RXI (Received data full) */ +#define SCI3_RXI_IRQn ((IRQn_Type) 6) /* SCI3 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI3_TXI ((IRQn_Type) 7) /* SCI3 TXI (Transmit data empty) */ +#define SCI3_TXI_IRQn ((IRQn_Type) 7) /* SCI3 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI3_TEI ((IRQn_Type) 8) /* SCI3 TEI (Transmit end) */ +#define SCI3_TEI_IRQn ((IRQn_Type) 8) /* SCI3 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI3_ERI ((IRQn_Type) 9) /* SCI3 ERI (Receive error) */ +#define SCI3_ERI_IRQn ((IRQn_Type) 9) /* SCI3 ERI (Receive error) */ +#define VECTOR_NUMBER_USBFS_INT ((IRQn_Type) 10) /* USBFS INT (USBFS interrupt) */ +#define USBFS_INT_IRQn ((IRQn_Type) 10) /* USBFS INT (USBFS interrupt) */ +#define VECTOR_NUMBER_USBFS_RESUME ((IRQn_Type) 11) /* USBFS RESUME (USBFS resume interrupt) */ +#define USBFS_RESUME_IRQn ((IRQn_Type) 11) /* USBFS RESUME (USBFS resume interrupt) */ +#define VECTOR_NUMBER_USBFS_FIFO_0 ((IRQn_Type) 12) /* USBFS FIFO 0 (DMA transfer request 0) */ +#define USBFS_FIFO_0_IRQn ((IRQn_Type) 12) /* USBFS FIFO 0 (DMA transfer request 0) */ +#define VECTOR_NUMBER_USBFS_FIFO_1 ((IRQn_Type) 13) /* USBFS FIFO 1 (DMA transfer request 1) */ +#define USBFS_FIFO_1_IRQn ((IRQn_Type) 13) /* USBFS FIFO 1 (DMA transfer request 1) */ +#define VECTOR_NUMBER_USBHS_USB_INT_RESUME ((IRQn_Type) 14) /* USBHS USB INT RESUME (USBHS interrupt) */ +#define USBHS_USB_INT_RESUME_IRQn ((IRQn_Type) 14) /* USBHS USB INT RESUME (USBHS interrupt) */ +#define VECTOR_NUMBER_USBHS_FIFO_0 ((IRQn_Type) 15) /* USBHS FIFO 0 (DMA transfer request 0) */ +#define USBHS_FIFO_0_IRQn ((IRQn_Type) 15) /* USBHS FIFO 0 (DMA transfer request 0) */ +#define VECTOR_NUMBER_USBHS_FIFO_1 ((IRQn_Type) 16) /* USBHS FIFO 1 (DMA transfer request 1) */ +#define USBHS_FIFO_1_IRQn ((IRQn_Type) 16) /* USBHS FIFO 1 (DMA transfer request 1) */ +#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 17) /* ICU IRQ0 (External pin interrupt 0) */ +#define ICU_IRQ0_IRQn ((IRQn_Type) 17) /* ICU IRQ0 (External pin interrupt 0) */ +#define VECTOR_NUMBER_SDHIMMC0_ACCS ((IRQn_Type) 18) /* SDHIMMC0 ACCS (Card access) */ +#define SDHIMMC0_ACCS_IRQn ((IRQn_Type) 18) /* SDHIMMC0 ACCS (Card access) */ +#define VECTOR_NUMBER_SDHIMMC0_DMA_REQ ((IRQn_Type) 19) /* SDHIMMC0 DMA REQ (DMA transfer request) */ +#define SDHIMMC0_DMA_REQ_IRQn ((IRQn_Type) 19) /* SDHIMMC0 DMA REQ (DMA transfer request) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type) 20) /* RTC CARRY (Carry interrupt) */ +#define RTC_CARRY_IRQn ((IRQn_Type) 20) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type) 21) /* SCI9 RXI (Received data full) */ +#define SCI9_RXI_IRQn ((IRQn_Type) 21) /* SCI9 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type) 22) /* SCI9 TXI (Transmit data empty) */ +#define SCI9_TXI_IRQn ((IRQn_Type) 22) /* SCI9 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type) 23) /* SCI9 TEI (Transmit end) */ +#define SCI9_TEI_IRQn ((IRQn_Type) 23) /* SCI9 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type) 24) /* SCI9 ERI (Receive error) */ +#define SCI9_ERI_IRQn ((IRQn_Type) 24) /* SCI9 ERI (Receive error) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 25) /* SPI0 RXI (Receive buffer full) */ +#define SPI0_RXI_IRQn ((IRQn_Type) 25) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type) 26) /* SPI0 TXI (Transmit buffer empty) */ +#define SPI0_TXI_IRQn ((IRQn_Type) 26) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 27) /* SPI0 TEI (Transmission complete event) */ +#define SPI0_TEI_IRQn ((IRQn_Type) 27) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 28) /* SPI0 ERI (Error) */ +#define SPI0_ERI_IRQn ((IRQn_Type) 28) /* SPI0 ERI (Error) */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 29) /* SCI0 RXI (Receive data full) */ +#define SCI0_RXI_IRQn ((IRQn_Type) 29) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 30) /* SCI0 TXI (Transmit data empty) */ +#define SCI0_TXI_IRQn ((IRQn_Type) 30) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 31) /* SCI0 TEI (Transmit end) */ +#define SCI0_TEI_IRQn ((IRQn_Type) 31) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 32) /* SCI0 ERI (Receive error) */ +#define SCI0_ERI_IRQn ((IRQn_Type) 32) /* SCI0 ERI (Receive error) */ +#ifdef __cplusplus + } + #endif +#endif /* VECTOR_DATA_H */ diff --git a/variants/THINGPLUS_RA6M5/libs/libfsp.a b/variants/THINGPLUS_RA6M5/libs/libfsp.a new file mode 100644 index 0000000000000000000000000000000000000000..4260a1e90eaa30ce132ae61891b901b93bec0437 GIT binary patch literal 20421610 zcmeFa349yX)joX3(#V=9aiS=Tmn1j|2_cZ!mSoum67ZTh@rLarkOIPy701LIlAVQ8 z_PwPoTcJQ%Th_wMzVA?4C_9wB6lkH4Qc9sLr3Jp{xieRqk!3^qzwfvG-uyDw+~=PA zoO91TcbU=5)!ey$OKz!SyaP}qQKRJr7|3v(! z$E-Jx5dU94cDnyz@xRBn_rbi}h2mQuPtOqZ{)1!w6`za$wO~3-1v-|L^gC zs}B|~xlHV`eV$nK@cUwM;5D(^Sv6w!9W7#M%^Xp3@lQnQKY}7yeTNAB_!v>{|6D}6 zj}aBW%oCL#oh$Zex=if(^Owb5|F}Uc-|KU+_lb9ieO_29YUa-qwS9|4-OWK!|K%L9 zqCQWo{NbCT@x?pD>UoEWrt?}v^V?HJ>yq`NZR_)5-v=V1W8w{>bDc-5!TMqCho6Z3 zRvsbtzvv0^oq09lfJ4@c18+!(gZ}x1IJkPT=sNjavEhY>MfdzIB0jiKY`o(tu}RMn zy-hcWL(X_YY<^{q=%2Sr4D?@TGTbEuYw%u@$IBeQR zarpej;(H?-#1a3VCyrV%AdWumC*qh_SBc{mo*<4tbGovGsFg$Z%W(7EFKcfKu7 z_2h{k?z>+6==_((X{!zsr@!^4ICJ;6#aWj>D$d^d5OK~=J`v|mI!v5*_z~j#U*91v zsM{efd~%hzIDetIWYb~d=OYh`%TE4@xcs?i#FhIUA+Fl-L-EVdA>x{2?-AEN@wvFJ zX_dJCsi3&AAWz)XyHVVH(?=%$Q@ zYqhd(aRgs@UiElX|7O{?sWtV6b zZL743@0{?T9f=FH3iD`>uB+>ewhqMygn8Q8+aDhs8D0?|wt)8d#zZ{1$x3w$cMXpu z)4684wlCh5uq0{+M+S!DiL^*R``r^a!G`uy@I~;f7vE*=fv?o3s-7vB-n(RHyl$PjF?@&D2JJ4(LN+{Nsh)Os% zu(3z-N;rw~16`ZbKyNZiY-6H(dm4;w>WRii5-gtvDK?zw8c24(sm|5Ah099ra z*t9ju>dKlXw2=KJ5zgxS2k?vN*Tyv z8xSvw#&k(9I?uocg;8cSvH^i=6EY(v17yj8Y;qZ(v?AV*0U)K+;&XzOOAcdw@R8E zHh}rViBZw%fJ_;imb9OT6RCk!`q??2v0!o}iQw zrb5bYOv=$9kr)}ml+ZQM-4{<-IOgb){&)u1UCJ>i6D-RFH;q9Hd^7{WQ4G-`PRtys zM%iX&CA+r7G5Z}l634WFnwV&8(`HPe0~>pLMiTMvG@gj}4`S-y+O;`8V!BfD52G-> zVXYCU(yI1QVlWm@n%6*v-24m*Z!m^`pBO=6!4G#`kSPxqm-3m3a;?S(0HH{3>=I)`y(1_|ELuLnY zVwBpt8J@BiLzjsrlKrW9%qlqs%<&n%O!WdwnlOgabpMnV#bQILS!~Ga4szwC^rKCO z6N7!3rYlsAiL%$HYTu3Vt0%f?aL`(oVId+HOVY&{h5DkhmD0&1oG4S>UBg{zQJG4M z%4ABE3rF-Sj)7Q-rgU?bi6%Gq4p|`cqr+Vr`jnJhq$V*wcJ*NxKw#Q4W7hH(g@+`k zYeJE11p6N zZ?`XHy9ce&J4MYf;w+K^FrsqYvpSKv${tKW>rmY4tt=AX61P`_rH8wcRy+1}C6l(K z*=4hK?hP@^Cx{ZPt}#ds$78m!g834Pj_T~l8cOu`cO|x4B96X^++-XP+3n0X10cmJ zYb~2jMjQKo29%Dfv=}Civ{d&twyg=KCsXINXOW_pmXx11e+8*?&_?F(7TnDIYRN0La zy<0$JE(Q`AvqHDZ#3dcB-%<{=sCox5rSxZ%p*LiolMS>njs?}mhFtc$G#I!V$8laV>a)`4D+QZZarxp^? zjeT8?x}|flLg)BnE9F>~u#pf5V`bYj%;q#_g!BwyHSz|#BzlPK8#dN#9gr7NW;3Qj zN=_b9MGBJBniFE4S~l8r5JtaE2WWh#t2+^NmSrlqaR}poT5c0YEzSk@Y0DZq2C$+@ zEtw@|F0iwtA_RJQ@e%DERM!ck^AcOTty(j0aCnm(+HDstql;`E7>91`tgT~a;Wp}; zj+&^tYicDs%(k>rYtbMb@(wLU+YqzuT(6iVne5=|*i1Id>(`c%{tfD;tfZ$;Ip*X`uf(WD!0qa$93k_qvg&%+z7N(+kCZ-x0o&1=Cd`) zcsF&}-GHXAH7{UTdz&rJjC6I|(it>Av&HPHR}LnJE%Hv@UB=oZWh*c1tvLcWoY5s! z0v^K}0nKOu$dcE_*1#@@PxCz63dYLe#Az2=?|WoMw=C7y4G@`Jh$D` zHw#+cW2W_O0#8*Xc`n_KHCM7XI=n5~H;8-wa#?0ViEYu5fi!56%Hpz|S*jNcn1tYY zVq5wgQHH$@%a%jpV zm7`q9jQRvuz-a1jtQk`4?6k)K_xHzeMH<7sD7LW$#JUn(wWa|$l2eESOLq4TDxYsw z_IJtq%C<(UPY+wQ_0f*Ojl)~J5}5Ooa`Nr~){bS=V85ED2jX&YVm#JItLr<;f|W48 zYiKCmy*j>qMLaV>jhC?V=8n)Lgi%@-SEpPt}l~n~3W#jWH(O@wAjYZ2N-&8bI`L(Q_O&!tp z!NK9$cmme%(E z;--1^1F^*RAza9};noGzk7{kUXi8{QE@NSg+>Vvi$X(f7T|1V9YV#C9s?xTA8!eR0 zP!$BS8HwLa)NKA#`;Ehz z+0^5RX4;y~Lt_~`u55<2*<_orLR>kr*@{GK!0CwhZLH(e8<@u0VgJ>@wWRVZRVDOJe z2jl(G&GGH#efq|hj?QRZb!T<7qj7z`=!g;sTA%n>Szq0TkM`>3^yrHIR$p7AqED^6 zQlq*p&$M~0k`4IEs&70aF|2jw zX3)a7wKb{X$Z4%JFVk9QZg$$N)>;L}u-2KIL5r%4X{|Fa(^_Y4cG|4gS_Q|j)|s0@ zi>j=sZ5}gjZF!m2I!k7!&1$Vxa13jmxf!&mip?TtBslXjt##&Rr_E}uRd5Vzow*sb zs7mcPzP06LTI(#Coi?krR>3i>b>?Q!qAE6vM)}s3muaoDWOmxD)>;L}u-2KILCdOe zjiQ#CPJ1(RGcC@{AA@`?u4Xo3DQ8|prv`JW*vuP?*v!qKWrfDJIWsqtIx~L^@@zJ% zqSCtDfl ziN`jKp$9qH%7AT*GGVejxB`s$ziob!JTw{K{ zoVgtSdO33~oRTwx{_Ct8OUh~67*ZLQWlF7-ZbM7q64W-Bz*F{|)TIb5Pn(-nWIPQi z9^Us@*E_rkPl>0Tk)5|=6Yf&r?pZ7mA5Pr~$}Wn9b{$4Vj0SvmqbC}Vb#Fq=?7hZ} z7hKwPAYj^7*LKJ|1Su0T;$=)ZM;#$m-;pM(H!q(o6EiZc=_H-0?2uQH-@p#1T&5k0 zO~wLPG|LG4)Mz!!w*rs%Uuqm9Tk z()^Chal4L2bi@-|;t3S2-)4R(^&eCzb)SI)o~5ulp2XZzAKPHr%LZ20>ek)Q3<P zw8R)Sa67 zh{g_#G}UbfXBfwB0z;SzPwD(vEtM zBMnPxzc%jE5@R%&gJnzyfo8l0Gf5nVXLDSdCA%VcD{b#sk(!nmqec#v@f3|$Ba>wO z8aZULE23ktpd|tEO+r%4?`^B5Jy3<+wpIT4rn~+nKUBJWVxLkYq}XuWHQTugCR0 zZzQDdDma^HRCeYKhtcBAc-(Isw$%LxR3LRzqLJ?}jHYtjjBsX~7aS1ax3#0P5cgwc zVcvvdE=12t{b_GNBqQOiXf)!EhjAE-X9z1XYA%_dX&Xj{Z z9JUjsu8L(1!j2l0J6Osc=9fFnDR*cncW5Yw?apk6l88e|#GxeOP!e&lL>x*Yj)sUh zG*qA=97GjmnE;}~DUlf!6`3tk;fRU~M^scgs#IyOQkf%E%SxSjb{on{?bQuB$^}d9 zlEKn)TZ;xu?Un^g?UsccEFp*Xkb^Vi&>kwaJ3Hjihhg5PJydFMh)}7$Awp$#zl0p! zAyj6sQK-yb_fVNbdzrnqA?$>Z?iQgkhb?6eTgn`^1Rb^n?d=c>I&5)t%}~%`OHkS3 zcnYlpJ3X03sWqB8P@0dWVc?S^ZB{9anO`Smf4I%Yv8hXLOTuT|G9TwiOPO}0FQ&}- zs=B&vY!Nvxj-Abw&DgmnfBJgk>m<|p%5&CA=4+jj?Bdd7EU{F*9gFYm^|nODs<)Lr zM!g;UD6v2eAQ#49sl%i1*nToPshFFTz&5>Qq@_<7u%jHKlwk%?!*y{TFleKsarhnh~ zi1Vu>K5B})G-<_Lf48BskZc_p9>O<$sR7=`vL(f0ja?3olwfM*|Dsy#wb2{5} ztL*{2bQUi_f??RE#>-}W8`0Ghuj}o>>s?McJa9TX;?q|!&gMZX|vo0nwG4oOBG@4=zr7^3+r|xWJ@Aj!|rzAU+{zwTBv6CjuQCE+MXLB<+3GQQ|@s8dFL6B+yWiCIa~-x6lc zHg64#sb*daPU#pJNW2sDy6=kSRxsJ*MQtTQRNTyw&4l%!PsD*X|oin9vL2l;k_HISAQg^nnET_W7KO* z60*D@&-d#cs^S+#h&P)>IE#k#f9Ay%cp8(CEI!jEDtLH zFXN3yRDG0CFYd*eZ~rO;#Y`V@9V1_@vgODZmKz7K7RsRR9T+nUgfh=uLuIP73TDl; zJgD^d4kT-_Wn{_&s4~-dUu=*&GSEZj8ATfL{##S^TD%lyz7(DYQWm5{5HYr{mzGSq zI3+19>P6%y`EFh6m9{jZUTU);)@yBPB>fs6Uvx8>XnQYv47E2`cXZa{PQs}7_iUM? zZC0ghZ}HjWZEmmx?S8NzYYLxlj#*!$9hLkz1U}i>~656)a#ixDW@YWxwI#0 z*F^E!E_ci6!|0@JbE2vDcpIH~U2jtEAq9szGcx>^ktql5M6@?HVvS~T%YbNa;!qi2 zu@N-VindO?87_AhFi*KHo(Ze>5s9aaVDOpiTGm3aM~i$dd>9j5f(-%< z@VuOQqbu7S@9U?)#_n1Suco;vusX)g^44Knox!c+WSK*-O+&gJQdDZ3NCS=mB?X&n z>jusjC=%P;fOoj<##=3zl2@^m0&4m&3CdTs?8Q_^PK$A>+$!HsO<`(sO#zr-6T@qU zsuS@pEQh$u&qhQ&HY339h0@6~iA{FYoA`2`qsz^cP24FCZ-{kSXA_F#&osF_gICR@6_nWt*PbE~;{YM19SRL55n(t6F|A_Fvy zG2acf#x5ygGk}>X3z$$Q@Z4?#OebWki7Ao9gf4esNN*Q0oG|y=V9PR#PO>rMRK*uz zYt-Xu$`A>&N{k2D7We>7ZF|Z;4yCP=*{OH_&5{@a%{>6R*K(69bFG^y zYc&{lr%p(X_@KrWX^lAT*p7F|`=K|s*(wguIkK`u$}pBr##qHVxyfECDl93i#?3)r z>ak1Os*)x#m#}I8VHul2=8$6}He(_Ms9v4|j$~o5%vaimWb~;re))Zt(%lVP# z>1bxkJ`FN0N1;jh)b#{2TQ_b*H!|CgXV>R8MxN@FX^Sjdk|K)jzc*vCWo{uC9o&e$HwLib1J_XIXe3L{nilb|0 zXfcrtu^4V~V5_U%p|k?IGi_pc&}QH!Yhp-jO^a zhm_g=Mj{Bw^3rhFjLd^499iGgplO;=|1_~kq*FrF-79nSu>4pg7Kok2aSguh(^kEr zy>dh8&1W3CdfREA<-A^`weHAUp7)P^4tnK=+8ueWNzJEyCSIS^H2t%@w$nayy{>=Y z(jl=F5=St9x7v=QR&N)@WCM1wh_*u?<(^o(Ck!#xY zRTDpOO?3U;lb8E?;4{tV4jx?ZzPJ4|_r#S4C+k0cI&W3p>ZykmZF=CNoP#Itj=%F< zpNo&?f1dNv#Cvn+c~`Z5AVmJXQxAN0AK$@Kq#oAMO=YiZ`|v~lEBEEWEsD=O>A{aCxqJsB=U(O=*C2`?dsmzL*k=<MQY;mg5>&Wtk@2+Edenm^dBI_ZJCK2{H9ANAvt*ju5U6RK&Gg zKC^N(?|BpPk)xj)0XWr%KUD?o%*n|;0m3kG=Xn5sw-|p~3;LMj&V6WSe0cSb%J`A% zTMFfF9i4%B@0LR{Iu%fUV0Vb?Kf)i+dHlmO*L5yr?L4i4SyvIgg=mWov~=3RMDN2N z&tv>^AO7V2WfA_kPr|9bI7k{gBBoEyuY0xM1l8aRKL(W8;&gUb}kWO zmiK+I&GEj1hTF+2Th9A28epz>;#?u-dG`dveD7K`?atoc6brGyyBhr6-aBA_+`A_v zf8#Adi$3E0BW!-udnB~{)|-HTAM@S`y2rgYqM4sCUI)IrW}KEU#1hT87}hP-jAj^L zq8XP@7ot=%k|7~}tQki@<7t|)6ot>wj3W5vOwIVod?C)#j6vx8iDtZrXggaoKEcO1 z$OH9HHRD3~>0Hg&4Q@YAGaiM<|DhRw1NFz6QH2orL^HkvcYmrGufmI;X~t$$YQG%g zB$T@=$M~{9h<98@UqFa=UB)A5j2$lHbJ+eDml5Api1%E^Tp00JmvIjo{C$^k7Fhn~ zGG-!PK5!YIp+4T6i&jqoDAdN)QvbKpUO2hqtZ|38uyn9@l3AqJX+=1Tw_-h ze=gTJ8{Yk0u5lnfp3gPr!-Fs68h=4+zL;y=36Ym_jn81&Z9d~Ac!$%htI%M zW8zMqaWvd>(PX0%{rKX^#znC6lF7!K@ZhDBja+>Ee6sO(RPz^;jXChdWs{8-*m6?9 zSdLIWIbcjfOHbLwSPr%RU5r`a9GYny2|Ev+X}pexOUyJLM>8g88V#t?@J!!G^V1q+h-aNLhWHQjXxkXzB|)610sjdG*0vg@x7VGsc`EN zGmY=T1xL;_y5Z}i0HTW>J<}LQ-ah9WccZDQ&o{0|U#>adSO*u>oo~F0kNWeCYhY)? z`9=(qE6z7AgRk2jG%kc?`#xwaf+r5%VT5K2(Y3=^0cUO4VLXqH5ZhsV7n0pOj3>*` z?{*lc;A7(sV;)+rXUBxcVA+sg6BCX^kwbZME@C^ulU?BIBu_4c4~8WIe~s{@8{KCM zPZr?hs7jnnhEYfJqcOp+F!0ywc zI9Y~1aXL?~M+Be2lP}@PGkJ0fbe+YMi(uIH7*75H6^HTU6L=IurkL;&RA@Zegp(Ye zltR0UC)42!H&6ZmQJp9I6=ERe$##TaE>B*9+r2zl2qzdkxf@+|0#9B=y?i{`JP|`H zPu_#)C-I~L0g%U&O0@lCp1goooWhgK5L14hJb+f7%9Bm#gaMvhjqWs!CvB+dbe_~; zgrn6H{tRJ_C!cVh;>o}BSPPu&1bf^(IT69G^W+2szlSH&QHoL%dhns~K7{%i)}q?2%>3D0+Mt`m?s$EzG&ct)5*An%M~cxI0OK9rbv zC;nWmq)`4mN)eFdf2DGAgy&}F5cmdvCSC;E9JH}A>qC|!AZcf*oIK&d6en~7GAE*P z+`_YvIRs=*o67MB&pyl{Aaf2;Il02Ko;d_2=Xfp(8W-biN^4ua@LU?4bqj66%Fypc zYk7XI0H9NIJm&}XhanuuVcrG7dF}{MQq>NdX1Ie;a|D6_79d3lMppTNMB`Q{A4cg8BhC z3#>)tdVU$qr^3KFQ<1nm=%c-~>b{`y8m(Gd4EzC$z%^U=cO~$U0-$qe0uL)-y72Er z;5Q2Jizzj=tA*!L1xylC8VNk609{OJAn=3&&;elPT|wQ2o)ox5fbJg4%(mT-cq-^) z1;k{{^Fq+r2|`oWkl^KD(RqM17YQ`avq8O%1V2NNdwv(3$-KZ0bZO74K_96}@TZ`0 zFi!nb@W=DEB0y7s;Ps$>JPGp9fjn$6)C`CZg2sa+*m*JV53TmcZ_)a% zN7wZHLj{CS_(uqQVgViuT8NPMg8DmDu{%umyl+LwrMn>U@1T#$X`?G-xG_5T&&6ow z(L-h>H3UCw{3@vL%8_F-Mlp{TGAr4_L~h7OY7*pyjI|_?7EG}SbeHfiXU(Qs04yTo zgpmGSGX550uxFyh_yLE+K*&d3WGo69XOr<0x^uSEq?sZ8E)raiKb``MU=$v^Ig_>=XVu!J3;(B!0i2)!45{bt2H-^H7nDYH9ud;< z3SW|%&wB+yj9 z#R|#uf&xGXzx+0&&%n?Y@FV^`k6SvgWa7n;kJeD<8zG|>LjD#GS%0($7+Pm_%M6@+aVuyk@5YIaU2<^WA*0wKoOWtwIifoNrD4*M&5fC!5)Z1 z&xau&sY&q9knt-Le91Wdmy_V*kiLTi9c-je6#?7yi;$1hB=Cd{j~@h&Vma*bhRqp( zGc}x&6V`V_ULb%*^SHz24DiwP3RkgYt`BDjEp zMPVPQNw9O+IEfb2v*8w61n?>?C=Tn_kl^>Y4Dige2pZXbi^4uqlb|d-=@AlqPz*d2 z-pQP)O@bw1<9!mm%qoslbQs3g(ppbTm1iw0AKDTs0c5-{;`gpC<5M$?<2<0=P!yLd7!_F1iQ>k(OTR3G0VY zMKjg+S}N`>L*me|kIJdyu<)cSs3M;(Jv{Au|1|Uh&k+_t70;nXJx7Ljva8qczp^T(;-$yCk&7!K?85SqrSOrtXDJu7S+i&Os^_RX_x-gDs^%kxv4_YPs_JJ;#G z)57`{C>>~F1D#=c?|P0%=Y@S#MirNYjkl?yhGWFfZ7SBF1wEJ9RNRWt^jz*#aY0!3 zVdM%N%whc^OT{y^_KL8N%BkYN!bT&6{AG;7>uoBIVyPQ#D*nkq>?Ws*tHb&LRh-EY z;2KNCERNYXhkaDeD}sB&#xJSjZZ^>U;q-ONuL(S$09>a$P2fQVz-w5|-x=1Qriu@^ zG`Kr#UUW=j%>63tqjJ{biLfylTK%`NzdWUk#w`0w&a%%az$5%0V_fq*rvQ{j^FA8Z z!zdl-=UD!jRSO?u?ss7yl~cv6pX~K`!mW9VqKtTAb2~1GHRN-$T;8TEK z_}3AbsDLS0(Gkc~0GCe;geeLzgujl!R0VjkWFs(50f?RT1g0whu@fgSQvryKAp!*o zKxAwR0Vq-c`W^bnr(ykLG*KX*ZTwHGkJNCqn^W#%3o{TFmK*bM`^Nt%!*fx2>SEA; z1_c)@0J(^adFA>F2nVF_&gJIXpqFvHd%2Ig$QUX&Vr2X-qRCTk5#*o?f}o^aKZykG z9Q(>Ff)-AJ73DrslVEwdaWe_dChGvE#=moqsh1^p^e)WfCxO5D!!|LNy0xDOFhpK z3V;!7xV$@B0SLG+c%^Wx0x(z&aA-Y20T`@~;&gVh0uYixcG2%E03rDSB~DcUjK)>u z5ZWI`2R>zNB+AXJ$cbSjepv2fo$0Hy%Z;D2W;d~BKTZ3Jt#wAZ{s;-ya=<>za?L>` zI3LZ891{E-%}s(+*eNbc6ZrR|L$6Q(P0~CUqW!VZ47@=9UTiVG$1ZbaxsSTYctg3d z5<>n2o9`xz05R=f)@iquf}HeE-iGU+<~m3bV$|1m0HwCW(6p{7nIvBz{fc0|j7`;Pm79y86|CW(I#_*em$BxWK8J)bH7b3!qJ&lG?;Aw=MF1)#s} zMc`iwK!joFeXCp_LOlaNK)pSGE;pAak8`>FMY)e|qBHb}@f4jAqY=50^a?0Rz)%33 z@m&Hw1)%Q#V%M0Y0951}O5`a3b2N<5BKpTP;1z6`>D$Zg@-Yqhj$|)3x==b7u8ZDnjWz-vr7{?c@ znv^S7D7_H{D7_U5fPZD1Rw+QW=^hHe7+TLp-ctb>LvLoS_fo(_;XedJg=d)paGNAa zV7US&2>;;(_ErE^0>=~BM*$d=QMHnYeidpF_=GFFGON*sIiJ-;e5^F9x;kPsW4QHi z;3(Lv2vF5t0<8)_Rfh=ds{mAWD}fFLpkEz9V2uJ0TgMYvrvUV;9}w7I0q9p}5crM) z(67!VaG(MZju#V%Dggbef=lo&1z_>DH-VS}(9u>9h${dct(8EJ0~2oSH@yfOc#quuTD+EeU*A0hk;Q zB=9{2a9QE@G(_|Snkb<8k+;%n$J=-{dsM{77Ump&a>RIs?YO2C`1d2}IlK@8o>LV7 zySpiIngU>EFM-n)05ca7I5Sdo3#j=e7N^_eBl@Q_Vh8h1jF{8yr&!Z?&WiYG9!L4} zBS!gr7_k&d&jk^41<1MW0kC*3vH)I;?@pSF6+ji5=bVVX9;E}9g3WVo#9R{I%~|D= zh>yyt;>w7zg({xO0e-bbAnzRFftrYZ9tmEg`pYeXE%e$o5g(~Za8txsiay|fmIKc% z$^x{-u^gptRRD~Bm$kc10cac-JK60Dz{=&{nB6>gC;%&$w>U`OsQ|28ev6UJbC&{8 z@rlI%?p6RyLdCC(=p8UAFo7NQ2Fvc+U68mZ;$w|y_pc(x+qC-*68u^b!0yhu0DhwY z*gc29BMN}s?-F=a0kC@uJ^Wh*!0tPt#PgT}V0SlEc^+2)>~2{A;0XnocHbY-eSibU za*6YxW%mr;+ITYJV~uF{^ATe+g#4dz>UdER!0yB8-j@^ryFX{mURD6?euj3xq5#A9?p_F;g)IF?OXuIXEPF5Fqczm|QN%bKLjIR&^v8+-I!|Gs zeWC#9{D7YLQ~}UAfr0j!0#I>$y@~5C1)#y+Bk;Kb&|uFn(Eg#N5(4dS z5&bUO-Okn7-z~eZVORVj;$w|yx4XhN=3-@^@DZsQ_ROrJnDX^Y)=Tw*@Lzj+3UWJb} zqTSOgjOS=Ko>jn#LJ`2<$I-p{3V_`%npvO#*!?nrLIuF?o7rYX3NQoBU!nh#Mr@!F z0n3Qnxe%LO;iGvpV&@8DB^FfvPDaf_MF1lXW2o$+02r~7fwo8iFk&|r*;N5%pcPl> z{h$jRLY?z0ooBJT?N;HVHPjizm-M(k@c(QH@US9)&I`EKDOUh=uGRoV6abwi9sm^z zK*bFXx0MP&gWWg)LCIy&w?_Ht)o_60w zyQ?j`Z}lP3T;XGlXm@9YQG{Cr{(8D*ts;QkFK`4{rvTV}9H+hg6<~%@TZO(4N(X*L z744RaD@gU73LlkIMXbW;r;1|s&A1|fit~~0=}~}bbhJW0os2iKZ*^IW+qlZyRNK5YK8t&59HCBZR^DP=)a! z8P{>Zeb{0=8BX^+Q8AgiD0Fj$&c_$0(a>q+rkWQkCWQf-YF@Ufd6~igss*55km0!s zV}A$--UuS^c}qUYi|DwW2>u8g^(%{1o zrcIv8^t>!>%2j}}$*TZm(*z4pHu;o*Wz$5JHf<7>`a87g*ArnzPNg~L23WaCl|EWa zn`TrRZrt$mFM*Aod_{oJfMflY`mV?ed_{tQMes7+RaogGH3{Zc8ucVNhXFdjvhX6n zbTkQOSL%n5U_BkNQ{@ci1*$N4cotOpNKJy>D~%IKZ~()7sndc*mHO2rSj!+S=5A+3!$X00@9QfW`Bx)-s(_9+0s&Z04je4E6YElF+su%*E zW(AmINJFJ@IvM}W`E{km_y!P9Yvp9>qS|n!emPF3v98m|O*QKfQaJS=z$V(?a-KCQ zbfEo_7m#^tEa&~X7=qua^pT1LF|F;Cp-{V3WWc>%Vsr^_N(!nvUb?Qanr ziuNbL#SE;Zlb|2%PlAisj+ zLbK;6w7*4ga;5QW5}d~Q?)y#)j<3|;Bf;6sJJBN84Wa8fwbDmwT5wjS;l+^U|1%fu zXIliAE9mvpD)lAE3%o%GpJ5SPun>v!D}AIU!7nNeeof;)lH=>lJP)>>!lWB7(=M%>PjDVk@1E~<8Cq{g?r435#ck5?!Q?9i0K#&yH)i&(7@yG* zAE`<3c%{(>A^&HbR-a50__q^yN&#kw|E5wOA>*!G)jVo3UQCmosq|478DFk6P9x(I zj_|K40@I}DEA?AQa0os1qD3%=&H7rUkJKc1yV96}x!dohZ{Jk}@X{X{!aEdz0d)^{ z-oGdS%ZCa!)q4s++g(}=;I9hEk&b<{Qr{E&fhXv*KUqec$ua+Ll|GtBBR;7#_;8^A zR>tXPiU4gli{AWP0WiYr1Mn{ez=$7k4fAgWz=#bTR=!YxX~c(>`h7H_hW9T1VHvTN zo0$?+u zcxsh?1yvl!($g#z)vV{NDj$_o#r!Ix0FeLBlYlQ!1W<7-TVeq~>y{de)msZtQ8B^hSKVOma)GGp5#pjJY4GMr&GuatdD8Ouvy{mNWi7f)}(&B1M z#j70I8>@U&P8Drc#uZdi!HTyl0;ovR=ne%y#nGhcQ~)Y|0oTTB6o88F&Wf*904knK zj&%w!E8bM4KTfM&qi~C5)lKt|*uTn0dui3dRmQutYQ_ZMF-3shh$uUtO3$kV!P9is zK^8%0F%t1AAE`+&SY<4RkpEiZhgt-jA*PEQ&*mzHI0+|TX?Pa^iHX#^)rQU#xt?=^#y^(h{kQrBD1UA+@K^AN0=^b7G2g!nu*-vi zI|1e87cq53Fz^l}rWD`~f|ymn$Lfm<_|*E&`3so;T5#$`kX}&02hkVimk`@wV!IUZ zk*!4qeEfTH0iWUCEr0jjkv}~Ycp7DPFW^(yr3EkIZ&?AKhYsdPn7>CTK+aJ9K1}Ty zlJIm~&)WLsUpheDh3FD3S} zX=!slzfJbMVluT9@Da|o{M(7WW0u;tfDd7|7w}2Sj{Jw1^HnJDM|id~|4F7qSl0RA z0zN9)RUqGW%72+Tv(21X{##7V2?vHys=I&>H1-wn!NL9lJ_I;Wz$f_z3-~zRQ2tc* zz;3hTq4_Nw$m3z@$3y|2w;L|t6K5j@e0pq40Uz+%TEJ(pw&m|n*;~z$+w;4by3H(k zSpGt?-X0FT1`7@^-~&}B`ISNreYi$cC8YF67OqJa-}QAWe1`@;=ZMccHu! z<1X?dRy}8%qEp?4yuA`|7d4aMiVA7*Go0pnX7q zk7{?(L7ZX_tdthifS?R7Cc2AyiS|~?D5-ZB4KsO&Db(ODI+DrFm4W$tV|;)%lsO98 z@Nu-e=oDriW6B=mE}8_To?|NmkD`f=a~JX=;>Yfy3n=s>)9lmSg}gF2-CcAg(F;ti zXSj=QV)DYuz#34T=`Q5z|2lUem+aTO3%RVm!Ck~JXgv>`L^rw%xmLc(UGzG-x92$% zz1dyJ_3kb1q8@~j=XDdk)m_L%>}~EsE+cPu7jhwYhr5tVsXN_;T<+ZEF68>+Zg=6- z3L)-s7jn|Q*Ime2?ml->f^0oi(na^Xi@wL?rYh;j2i!#`G1*%c;FCWOxeGb5;jKRT zW}16%>kYVDu(Djvzylz2=BS)WxMh!Xoq(?aE$!J_<>D-cY4Xiw#=e04br`Tbe_CcP zI-!O0>}$*PEyxSVyw{hR3&wL1j-I!d`O1;Q??B&QX8ei-Z!ZG=!7}qZP`r0ArFL}( z?yFdU8_&s2L=W(Mq$Idxfg?R1D}alG9M6tr`VQ*69u4eyZ<+a(=Oxtn=`tU!q0TRt z8H@IT&V$f>JYxAQ&aOFmxHoqiE2k~DzKF&B!;fiIjshSC6`wEDn^8J&D@I$-zbzGK zb0Bst_fa|hGGV#V3nBj%vf$* zg;PH-I6VbUf~m{(CrMC_@bFBt2rgk|3YYsxEhbO&yt>RNt;Rxv&0{St-dQGlrdB|Y z=M>Nf?gE-p?_x2=80?>-O%Lh*R%FIG^Z!2cz&5?@!U`^S$4jiFJ%{g)njC zyymJyvD~ZBU?x%So_UXwsDCbr*dH|Sg_9xaot1|%(|aoh6}R_qAkw{m)L@cu-44rg z>s+UjXsVtfT9LP)1{5nW@Cxq%_^Wv}gGA3yAkp{HN!{M68StHVSuyEehY=p{15?4^ z{gQ=*>-%0LI$Y0_`e#%lE1SDE?*LLii-A&jXCP!W?*a@6Io{c zB|^+97R@_@#rA~p!u#k>ELIHf7$cf-4H7tM5N^YIB(Xi zZrlUQJ!8uJI*2bp+vlED$jA`0I}r}KKPhDEYO`}0f@c@9J#uCrhyfz^oI-lpHM3W0h2gBtD! z+dMp<8$r_k2r z`0oR;He&@uk0QgmoW0qDc8y}t(e}?V{kJ%d;XwPN=A#n+gHEBHe=V2x;dZmMY(* zEn)eq0AGefERLhzS|D9uSQfaeQ5hUCEBqwj-{RQ)_Fbg>8ulP<-zBoaW@&}@A@4&R zAK+NR>n?4!2~I*J=s1>e)YRsf;6VV^6XfWr?WD=!^GE>SBbZzOaK4sDPQJx+I>9>h z5v|+={|mr1IF>G5g+GwOxy;?^B-mZD7tn_QJ%EF=n<#4p@-k8{;wW2-#NTl8S0-Xe zOaQeP2W~jLi(r7SL=NXHEuu{-`4-xtEoILc+ucy<*#hPH1+2I22y3?`8~h@%2KZwl@CA{q1%>5IQhSDb;& z({PB&f1}ZJrkSpEE&33B2B}&ud3Mc*>vLw9ZrU~KLt>_tI2hrdlW!)V+pjIi3;0}l zMR{vx`n4&To^o~;KHqXc802OMSKc1JJ$+TaMy^b(9B}L9f{16K{K$1{F02}TkTRt; zf^QHG*Z zCSkc`CL04j-z48eUnL6q0n=j1oQ9{)bQBKQr7)RIlC_u)Aw8{OhBO9d&xB?ho^LNq zodqn;lR|ld5=9OX0J8#ckTf5zr1|KtY0t9koXPMyUAogkG;ML(@j}d^ksQU+m_@qHX$T&R!)l$yOSQcV?1lW= zRL?&7XV*xZcC(kwnRzRp%HG|9LF*Dbqb0O-wpJEs*KVuvt(m!>Z-0HAG^IorWdTc~ z)TgZh8#a4NLBUala6d3*AAHM7IqVBtw#X2+h|3)q?2FjFW(idQV}Qwm^kikG>(EZ> zpBpC{cCEq(x(!Y_s9XQCf@Yqr7$+FF_(*HJP?b}k?CRj=2j%~Jgg75$XTlvZs^bUe z0H=^9)>^nG+HofT(J~Ah*x(0UK%SLe$WJUcv9C}P7ZLb3>p~_MD+psQASQzf!Y3g9 z1%pg6P@^L{ln-aP01C9iwR$SRhXhQhxGlBt%(jLt;vaF zC6YO!(k2=PvJVbhJvE`gT#*nf7gVIFa~xTfjx3Gjber8ujerTJ{0Kz;lh-|>jUU}O z95tqyxXmo#Y!Zf#d1n3^oXLMonvKK&GXIg8|L9ZxV?gkql2D)1Ojw4sbt*l!2NHYX zVCB?5JJte_HDev^|Nc+(c4F#qi9d1z)Bcr*?WoM{D-lcD(xoMdu9A((p^{`GRwB2> z6eXJm`{O0}6`O4(J)26Z6Wt@d1B12Lm3WD@cWw#x%uRG9OX9)g@JM&>AU4cB1bf3K zOFFQX@#cn+foLbTHtlKa8%ajnt0T?jN=NTNtfXtGw**@8pBk|}XGwo-1ls!SdY59a zx{!e zy%g*&zcyo<-Yxa)FaNHQfA_`TX#stvN7JV-Ww|NE`c6pbo>JHo$iYT>TH4Sva*$IH zz`q%K5u`NNp~ZTUYce&K=+ivK`hgy>1mx-7JT1^s6Jwe_%d^)~ePXdb$um!npyV!l z=?1=%$??q5tN1xZpTQ5%OBCB@8B5(cdZ8;y1NA%irmL0)_fik2ZHF2$k?m3Flx#LYwSgDeIb|1*U^(T5%3G zFtp{K)VaZo%|`J{O^&?X1t8rRU9sp5?MFu-~DL>21o&pmFUiTl}zMeUWFH zv~H2K&TK*IUt81JUe_R+TWecu+oKx<_m8h{$B!k|*LJqzchl;d>Z?2OTgcUoP4#u6 zuD-slc1>qWYE4H?w4-r-eYACLeY;p!hhH-2tnOUX5na<#SKr>y)Vhvjt?j7-9rZ08 zplxiSU`=CFe5yX-C#%)vqe;6wRNCugREp{V{<)BiIzq1Gkz&6=&(k3t`R<84;$Ek z^dEkJqP3;7y|u|qrQ~bto0`@%RpW<2T3Z?#S13h8vCSKz8|4n*1F`L*qpo%}f=M*3 zt?PhnI;Pe&HZ(@7+hjX|p~b8?-PydRDW#;QsUEG^Af@VCs*y}NCn|q2At_o~TM(c4 zC2|bb_^kkQ^p3`c6Mb;{x=uJO#g=lk+050oosDbjQ@OQGtLc^c{c7v$>!7EjwXL?f zv!fv;pyIKix~?95qO+3?jp(R#v!)?msFy|mn5+W|otY4@=E%B=#46U*Vs!16uW{_%+vh6xCGYR}i z6{82dh#%{RlcN3c{=vj{f#23?S>KL|HZ(E%%%(ygLsON>5bvmM#7_*u^!B>_MeWM6 zwTS*so4?F%)Uu|jDcaWB*uu!`AmhGLAsy4)W()J0H4P2;<+b|ew$A-W`Lq^4bkknn z5S1+>YT6pm8g-3mI@s2hZUPxKo$b{v9nEPETTWvCNSj>0FUmI6wwE#Hx$36&`s%v~pNRJXOYx9->2Y|eRY9nG}@BZC=Xsfc0lT3VI5 z+9nKA)wQ+t9UUAjP?43jG*ro1*2&?#xviZqd{9_JZH@fa#AT{ z&1+V3sKAfl#J35K{q1Y(>+rR9GPW6}#qh(OsA@)MRA$LZx}y`GPN}L3)|oRtdN!8; z94>q0D5fgPpOo1=GGs-5BRfwWemDj(#YlE`JH&Fj4)xLMnhp%J<^mzr0-~{XHC83E zr?+%AiRv|-t#znG+9tXM&D8;qNEI9Li(*QBy`1whmH=fD4$ZVoX|L~GiD9h0zP28- zN7NeCGUgJwEa_-%D2>+bi=TX2X|6|7^Se3X!qts+opx$j3?Z=s^9xr}=6Z?qkU1L( zgk&9B91}bHG-6V9N_E2CC%dV+Zo&A(^$LfeVAEREfg@oMip|lv-Wtow5ct(~rHDoN zrMbR&T{T8m&Pgd@S~z!eNu>Og?!M?s=1{Y?wW$-8lYX`q zhZyt`X)CR&ayqolxLm-DUe+|%WAKWi(OXmmo8v0$WqF1Z)(UG-kzq^?9qZLBqi1KK=l^<3Rj$2rpGE<^zwZnZdPI_p=9xNuZTq)D}{&26nM zP+*!;Hf}CPZj9_<^ungL*0%J-plUAb*P-GhMa9Nq_hQ4OK)EbvsYVpl)|$c8*}k?Z zJsepsXm8;Hva`C$aut^vt)Sr=Os*zI29mu!1M%)++$Ktxb}>NBwUv~B7i#vGXAJh* z_EH)2SO8#QgWm;{oQ%5;y!MK{ zUwg0D-bKaUz4n3y3o7>SefM5_W|DjF?|Z&Ke$O`#^=9M%>!9#idfNg}DP z2JyybR9jOK^!y-^#FSWF^;~}Q)(lzMD!{mG05On+PG|%16;9YhfBGrHFO%tyh;c5c zW-atcGjS*@nJ~r7QDhkd3xx|-;lqBN?f53qq64s6m@FJq0LYT<7aj=2*R)jYi$OYP zP-ev6(x$sLJ%DZQz%-(3nfO3Lr?!TcwkCe18BJAFT}!iaE92~{;i?YntELA-ZP&fH z9vP?^l|D?Qn37;G4vA)6HCddtCPuZ%M2Qg;KGv9|_Gn7fc%pkJX5mA8mpH1cBOX5o5#c3Q;VRq1Vanfl3LX2gaoy<&GG8?SR~S3 z8m>)NTr-kWH4_s7nmth|z}Q$X*GAqb3<5$_TOCG58>wYm z*V0s-I$A{4N=zLnv>M*B9Aa!LN-(m~1L;H!pD;0bSdKJm5T9Z%Q@t?!L;pFgwN#g^ zk%e_Rbtc%gZ21yBSCcV1zec!@+F*4eg{>O0rrxL#>us)N_y_7lz>l` zqCB|ziSPE|TYMrN#wundBsmpLJ^FgpSfw=W;Gzbhi#pAe*|@A=Jh4K9q|%q*2t$*UL0~`$pBN7}wyek7H_9jCdnvz^uOzRB6ujKn@va zN3doA3ZzS!2ZZ5{STs|MSL#x;r3NNQ$mT4Lu2`cUoW`43 zGNo)n(a27GMQ}k^$Ec#Qs}`+YU$qEdxbN6FcGdXtAgo)qe$_%CKBv84-B|23Rbj-j zm;|I;vUbD7v0ZD&E-sw}%7V^C%c`*Xv|-BFRmH2YeKlrr*V-{l))tLjS~Rw?tY|ED z1gaK6fU!$f;d|Kldf(WU9jlkFTUJ#9k{-~E<$wlf=1Y2G@o7nZysry1egQghuKLby zMaFg3=C%eJ5kvegd_LDKCg`%$^$}f5nd(|}kAmKUZRVtuHZxKmZRe1cof3yoRttc| z9j@bQa8nx>Vq_hXg@X1Sr7u%tmC1kb*3zr=VliaBphE&8VRcv}OO-_WLUHAN4$ zjVm_K>DK!iGRIDsWwyal&60$3Xbj1V{ zpKR_qk~isF8ynl}s~hIZEU<;PVT09eWhYV9BUral^@~lfS!U&oC$SowG9={!m@+kr z)?`NusCi*a4MsS6s;vGd=j1XSm8E+0#wcqnQ7J%s8VNU|2}v+i63uR|ZB+#$i_a){ zsKMDHM{CHQ!wk3!3t25w!_sO!7;d4P>Y5UkAX^wCsf?m9?Z6u}6SD$1m|m?dF{`$M zWrFDaA#bUcw=}607Z*^7Tm%yahC{g_7#1bt4P}Bkm}m|rnS;sZV2U{?x6pjHz^##0 z^Q;mL$!St@E{p2agrU8e$#S1>ZRhe0vRJXstk{}GM(kxT?E;abY~5uV6E(nf8nK9{ zOHB1WWf&TB_*7OKH*?Tbqso3sJvL$5n$^0FZmr=?Ej6&MS+8b8jm210Ro3Ai`vIz# zpq0zCmCI0*n^h$?g6aMfyDhS;B_=8@H3w>G0bCCXse>@^DJ>uw0E$ z^>PRnKicX!qo8HRYs-v}|8HzHtFQlx*)Xfr_A4{CEi-P6Z{6vo5NRG${XmTmW$n%s zTDNg88?0niOw3i-wa>*HZuKk}{iRv0Px`qTjbIOGS_4-O6Kwv&Ku5{Z!ci`l7wXXe z>oG!2sakU~=7(~L!(;(MK{Ey9>{E)hELnh9GEGpE1&CfHK~1g{C&X@^*49nxCcRsU z>Y}G1$+h8>rZ&u`mIXgS7yN`|!^4in?4TjRWHf`Sse`6$@sbH?1=UKm%&u*X)R>#N ztgBbwRMVoHdiXh#t4$&9tQdX9Cw+c=sVrY5FDCtceA3^?C(SiJX)eT2>uEcOL}J+S z<*IDrSS^Ac6Sblf;}}sI0rd_=LNJWi&Ak(nf=x)4<%DEePDlzjVS*Ymqt{5>ofK?B zvK+C1U|bgqX=e1HmY2JhVK`QlSn%O@Sn<8})ym>%7*p4Q42x)NRxJh>s%=BVBpt{k zt>vVYQqptSwuTuEjk7WI=(e0Kt<#K{>dsZu8f$25n^uGFTvj45RYW_*g*MI_b(3Xe zNQ}4>b4+m@ZU z{2#`EWe`<&L9keSb_|2R)J7g}_%}LDN@_nTsXb>rDinsnYHCpm-D1fs%(UBdTZ8=y z3)`i-_D<2#PDvKGQBbvqx)0{GKrcl?q{ONa_CiseYuWwkgCvjSe25jNRK`-JC3=>K z%54l=+k{<}YHVcJDc4EF9^kHWEm^tl)kS>T%PgpIupC7fh;pW-WUI!^F*(YtYsBV> zxuAC-)QlIy&uO(0ERtjR-l{jC5=%#56=f?$wG^uDe{}YGlx2ol7-#7Pw?@`7vm?rW zo1S3SJXCK4jw{!!URuODIcqki60Q5BZV08yRae_ELyhf4-Rfwm-d>R1>12e1va5Jp zDTX6P%jTA9Oe$5aWGsfB;A7&brzlbtrB#Dqx-*M4lq8O@il(-sV-01Aqw$F&_?BFq zm^hl0IGUU|nvyvB_x?t&tLi0KPR{jO^?#@drT?jVOh~AjXgiu?(`sALfN*AH`VeCe zu-D^n%(N3TAQ?L85|x2VDMl__e8bR2O$4!!qPkkM|IZ;QDy-ofL1!Q45|+s@bq86u zy2*h(__kxs6>W#?c%go)Nol?6Nc3V4T&JVG`^ea=kZVDuqb)^G8xG4hO+uW+cm>PB zbu-$hRo6C94eoIwGd=E1sU-*>YHNvc@T*!c<)7U;55w5B2K6n|WYDc9Q%O7MmXWiY z+J?3mYQl`vZQ?|itmQdf2K8S;xZsUuW6az)s!z7NcOOjE$zcb{a-XK`m~m6;w`n^-QEG){-d8WJi_k zr;^>&1h{9JY(#KjE2d&3j4=^H!#&Je1ih%*k@RiKWc?Zm|G8*Edo!gqx~h3bk%h2bW9uXQD9@p{@gK74ZDv@H=n&ugaaTV4zV{@b#LB5fORx}+6vlua_RoB;7C)Rzr ze9pZ&WkvSEXb)z~EII6~ERfn?}IilPH;%G}DCRY-zid&5#O{udI z#G>uS-_58?DaU2p^%!9_Vt#_Xy*fNg3lVXs_YxDqmF>$8k&#=3={q{jwtvdpmOI#>q!BEsgBUcef>d z4wFk#R_$dA?7#HG$x#Dqm8qf$NmErz%vYriR-0LB81?UCDIJ0UY1tVov9S}M9NMTw zYXln1ZE20w>j+fcL#5OJGpo@HO5LMD#ej*bhi#~Mk~_v0Ep1_p$!Zx>qc^G6b`SYg zvsfALc5kyW;5F?VgfTU<498slVg2tGV2iEUgt2Hr6$hY00#n*iEc&Q%OzOsEVqZjg zCgxVL)G3lGwUiKs_NLl7m@&!}!Z=H6@jz=e)=Y?;kjsRBvRN`S$q6OplM)HI{NBP< z5j9p*jhSxR%h0r&$c~hvq20~aidq<=r6i)4?Oznjv|J0o$ca06*d#Ks6sh%$P2=Q= zx(7pNg4N{`sVt2R>U2D56S&}B58shaDn$(CyOd=b`hTT6?UK?w)uP1A)*|lHp~;NL zHTE-=ZFXbx4Do6;merA;xP?pJN@im>9qG@xDwg&L3`ilXkwjQZIr9OIx0VpAE2#(w|irOBAY)RNXMD$3d@i)Jx#m^1+*RT9*c zw8@Ee85SqG$E5xy>${SI@sm9^`HhsOlx5k40qr`TUFIUmHZT(53d(Hy8V4t;Kg3`# zp>Jw^<3N=a2V)`$#%pd$387F-x#+EiOh%MsV1@ECGX_>Iq~52tk})3%YhcCKFwn!2 z#H?DPb2tEGldGPbQ0pWq9f0X=xyJa?89KHS*k;N!JgrTQ6YSRceN|=?Uw*lBH z=^la|5Z9D2XOq=t>Z1BKSsOIAGL|q8rRXhH)EwP^msngXLCw;I%*eVFVO5K))>PDN z-H0!%vubERUWWMNxf`K&cGZjtORO-huCA&;t*fm3kS^Ql_5b z@mu{|zaip%ZRSv+8_(q8^>QgckCL4)LC`;HoBX-)fNuBnUX?!iItx6&oAPtxvEAyA~?&-Uqxvh*I*E3S?=F|WF9@qUUKlAniyjrG5`ph2blaeu^+sab+ zCvVEK@G2tpqhu~zPyM;^9)#{3So+DI8}Cu*em&P3CYJ{Q@nMH#VjS_U+TGLlvc^ja zJR6Plc&Sgy&us-#&Uk;Shw~h-luP-!ExbS_<>$8WCY_X@+rn#WQ+{p>FQZNQxvhaI zXXMYfcqD&rYmgPeDZP?)F93hzn;&@2`WApcwFAwM+ONTXUgvQD{&Sd|(-Q+Itu5Wo zGc3N8gXyVh0OfnLoYV3FSnm-af3$BezNf-Gzdm%GHFWWRdGeo^!qNm;oNLQ2P=g_DIo^@5W$6vKSzN2Hz8pzKOwG2ZG- zlwwZXQ@_C@4UG_MURsH6tI|rfz0>fv71}XvEZ^D(gtM_mrwx&GBWXjN1L;XbdQ94I z3ndN2Tfab3bg)p!cc3v{SP-wpQs;dA260!GK_aAU_tsbVCJ43zi5@5)2831#1Kw1X~690yFZPFUU`D^L(XX zr{G4x!v&8PJW=pe!LtSVhA{Hshp33x2;L}oyWqWo4+%aYxJ~dS!8Zio6Z}|khv2t@ zKMDRWh_C*r{2jqu!F<6z1o?I}%DJcDctO4+jr3~48o@@vS%UisE*3mMuv740!Oeol z37#T&mf%*w%LV@-c#GiOf)5HlA^4o&D}rweekk~b;J1Q53;rp{HzHEcOu?XFKfytQ zBL&9^P7?2qxI8<1f5adUf zncwk(rwN`fc)8&9f_Df$Ao!%lm~W0?f#4v)(SqXzLxTJ! zH1BH^Jk_92)2|o2N046~Wcm*Ue-QLwU`u*$!Qp~o!A8NQf*S=-5IkS-3&EcRM`Nf? zzLNzT1rHG1D0r&irGmE#J}>yT;17a17}Aq3-@!+mAQ%%|Ah=raSi#E#ZxVb`@FT%* z1$`KRlkZT$Qo&lm4#7@Ae$R*LuM)gX@L9pn1a}EyimK9&6r3nnFSx(p8o|wiTLrHb zd|2=$!H)$063oQVSLq?hSM&0Grr`d98w8INyj<{R!KVa27UWkf$j8CNh}chXjNmju zzQdK*R|+04$dAsFeuLlxf-eZZFZjElldIDY5-byJ5ZqU=OYrZ4TLo_y+%EX8;E#g6 z_?}eA!!KJBCkZwS@>RB^A0&8&;3a~03%(-wf#5HKy)i}O{euM?1rHG1D0r&i^@8^Z zz9{&$;ID##pyoS7aDrfy;C_PZ1&1A>hk`!{dN6Tgy554r1^FR4(rX0g3a$`5RPbcM3k7c!d{FRh!OsOb0VLmE zf@1|M1e*m{3mz(XhTs)~4+%ae_=%tk?+PXVY{B7zVZlbhrGorEG1H$Zc&Q-2t3>)U zf^Q3cCHRM6HkLe?ZlGX^V6|Yg;A+7`14OFUlII7@F&4^EbWkgf#4{?3c*=| z{Jaj+9V&RT;Dv%W3O*?Kw&3T2TvFowy#&V!RtPo=E)wL2c9{ND!3zcXtqRiL7W_)^ z55epreSM%{iD0#0v*04Zb%Lh~UMP5n;1hzc3w|#6i(tkeonL>!Jq4=-8wA@0*9smX zc)H-_g0~AkF8G?@XM(#0oxwWaeu85JLxOVz`G$Ae>oCDn1TPl6S@2=OcLjF{a*c@h z2L*=;P8F;d><~Oc@D#zT1n&}jO7Km=9fH3JW)9W)6$+LM#s&8mTqC$y@HD~81aA|3 zOz>5~?*#u8>@!T~H$rfVV6EUjf*S;n61+h0dcl7RJ}2;?;jvIL9j`1Kf(2a zrwLvpc&Ff#f^P_ZAvnB5^G9@p@}C)k^8_~v9wT_G;PZlS3;rOOQ!4Tb;u$o>w@Gk6 z!S#Zt30@?4r{GJ1{}TLJFj%Jf6$wretQG7K>=Zmv@B+c>1)mapRq$&;XT0X$N3d9M zZ^3;9mkDkb+$wmj;KPD134SEFOVFO6^BE*qEEpG@Ex1hZV8IgwuM)gX@L9ok1iu#i zQ!rw@`4jU|6t4aIxTe!D9u_5xh(~lC23$746PVhp(>jm!=JA1Um&E5`01MJ;70X>-(n) z&J$cNc!c2Pg0~B97kpRnM?vpY%`abYyx>&9IfCm1j}Sah@D9O81m735sx{v{!NG#1 zf>Q-!g0ltp6I>*?TyTxxdci{lj}$yb@DjnR1g{soRq$@X2LvAzd{*#v!7l`N3jQeg zo1iPK^-CAb5)2CV6&xryT(C?qDmY!RNpP0neuB#d4;4H@@HoLOf@ca|B6zFd-GUDa zJ}daH;75Wx1b-6rMYMj|f_Z}d1P2M03GOX8SFl5{Q*e{u7QyobFBQB|@IJw(1YZ^W zP;jTx90)oG%nyA-GzQ-xZ{sM+x$if;>N0kY5wz`E7!a2|gwGmY|BCK{|drkm-LAI9pJkgrv64iSDkPjEgF?X&V@;4+>=?v;YyyK#>ERNMyS zIRnS!{~!^3Rr~??{l;_LKLQ5h{dv59l-LW`lzniHE=uX4avRQ#=c?_i*=Ns zdR0YFVr%l95~*oTNMb528JPI*R2`m}N>2$=>_$!rRV?mYLure3$YRg;n=47XrI4V; z?zfreNV`!}-czaAEbdsiekq=MTe8L~*2fDLF6`{splzfnczoq zbj&Y?|Ec`W#rZn?H$TI#8iZ7SH-ldhXynIs%J5?yO68Y{6I7wZ&+uE@Bi#U`GuN2d z93R^wUD1C@cTtaYLy<0zjO1td-GOslN|f6aoct&Go|AN@92qN0{mswt+X({snRJXH z9bggxO}Z~}oNB-Au-_EWXg@SL3Hy0)e=5JV|Ak+_9_dcTc{=!*pUIc8ulSevoq>~1 z4kYAfu9e{+RX*R@*q7pL|cFeS_CeY2#g)Tbjz_1y7{Vpw zy9en|>}w5+y3_FOWOD*!p8OHh)RF#kJkmAcMz|KYEfl|8AoEOdBkK(a$8o6n8GgM$ zNKLm9@;z-X;+i=eS5nmNS30?5(v*_2DP^GJ)x4!Ce#wExXfmdu_MJ6l`~o32dMG{W~o;?DmzMy1S^vb*)phWw)o~ zub=>9(I`fb1N zmLrBBpOPa^CV$r`--Ff=Snw4Z;rS>eaR``s4f6CT$b z7(MgWK?wMw2c-PcTwcbOyFZ1ar;RC~AE&u|b|xUrp1udJjL5-pd0$ipkkZvgkH>xj zj_%%t+LPAUcO|cQ(!W4mPxIM@{Rrv%z&ku1n~%)l+69G3{z3-+6a?uq_TTZxdjbBq zw;-W=XkMJuD@nbDe|Y3xgrx40y!kk`AHpB+HvCEd3vF$>hXXjzjOaydCuoY?$0|zaJ;9>>4I2eUCvxDMz}7=MuClUIZr^c5|{HWZavlItU%eE=5juO z`Oa`T2SCO%UCu5rKg;D@i?g#q%*2ew<(vvG=enGCi!JLsms5yq=ewM(5a|M!vl|)h zayi4G+>b8jG_*xOxg74o{_JvYgSB?MoXHSuPMUKAGP*y_8Bu`UT(|RKhGl)>b}D*V z)(*FGGpjj^NZsIZHly?#JvD2V7=)oHpdw>~XpPEgpya;;kNMCT?i+IBVcVvph}% zh_gM;T=1OZarPKuS#v#(4JX>i zjkfc+-?9$2omcu;)*-f24&pnu^Bx8=@7fN-V&Ai!BjITOvYmHES=Rfu^9}O*z;^C} z(jVH+XOLxkx-$$(UQBmZ;`W!)o$1K-<#cBX#C;{*c?tTxn(kbSn)X_{^F0jmdb$(G z?Qf(zi=p(J>CTl9_in%Q2~2m7-^qfJ@AW$mpy2NFJ7Ku(B{|N|@X1SaocVCU%W|A2 zkl*Dw&e>4=}~7XuFZVZ*$8>(?{J2| zBNyy&{>sF+Rd+Z~z{rbsIAhUZEZ*T<3a{(f;WR;qB|Dr=kb3EkjG-{kS}c`he29`i zkO!CH-cBC;21*wX>R`}yJa`!;vYrPIz>FJsurFL{Ge)f$9dLjncqV#5VaQ%(%>Bd9{de94Dw(b{49?Lm!gn+^WYQcPN_47z>)Fzv6XQO zgiqr^09o*1+>BpQT|GP)noccn@G%VK9O!>?dsd2PEzlv+Sqr0w(PhYhP&D+im~lpktZKe%*F*pi@pC zn8SWkZif%?_LptD4A*)!SoW)OdjoHO%l4D4mF=+~vz=Nb2~Z|0Ku&3v|0ei_{f_PC z%{DJ1pU-UPcpPcDcNj5^++P`jmir^yz7B~g_a~`x@3j5ViK9D3cW+C&+!kaLD_Y?dHukFRLONf&*1}*_JnmW19r^ zM_uM47wWRd@|N)m3F^u`bH!_U>v)9(h<-=8^Er-ken5S+?<$uf%&~G_hW7S7hLCCH zj6kDe-)jhdD`z*F9{WB+$gpyLWj(v!5F9IKAle%H0YiX&pMf*m4;ca~7z*~5a+_^@ z@CGV;TewxZIu0_Ft{IX zZ$Dq|Cu=fzwcNRp3_2+E>*f9L1UU_>csZvq+c$*Z!qeJ6;fnp1AwVq`8Vma!Lx5Tj zqLsDZGdz$SLcCaRzf2)cLB+FQF3%_b;6Suw_J`$uibo;7D0g;Jh-cAc+Fu%usIy@3 zNx7Ye#xZywoY($L7;HwfVt-xkCu=g;Rqou4L^&r==%0jv8$x%X1+aG;!=iA$L*2K3 zF$8FF1ZDZv5THdNE7@;`;Inda(e~KC8v;t}Dr9Q^VF+F;=Z_H}{AmcbmGc-{X!|ci zK$cMC+j9F|DsnQKJNtVnj^mlTx57^qsYrH(^9vPeqa|`HwA)E}W>naFpk#y7ptPM? zp&jBb$`YvXlQnZGtjLNm(Y|bH238cYJqbSR#Ys^`(FHhRE+Z;>tw5r@ApY2+Du!G_ zdR|c}&PG=ZVJbX7pJorK$U2U^rjXY#&8s)LvvT&Ya4y1OfFfA|vP-jaJ$8PDeIJg4 zf6$-$RupW*)!yVnhLb9?-si;-O*}<}JBVdjo)m6sMXz+2FRu_O?XVHqjSuD=>469dXg`aX#s)H+> zwhfZ{pZz`;J%q;Oj~o?;MA zGlVoT%^8MZOmn6oXfcneu&;syK`%{noQS!T-RW5sekwpQw^lemQcPu2xvCH7+YJM> zRFNdT-KyFD*V)la{sHs*^DkM=V}fzJ}?Y045?#3_K_i=V>^hA z^v8yPhTsJfJ~0GzY@67pd}atxi^ zb$VCi9>_bts_;`I%Dtx$m2IdfT|5+K=|Ddpz2H((I19@KAg{r*?$@W$~}()|78e}0X@LC74{|w z9lU}9BdpacI0f3|=@y0h)Q)Ee$dR zX!a6|Xs{tbv)5RvLkt0$T|v7JH3Vq(2a9N!AwaVL4LaNqpxFszI>HdNW(Ae@cnBTb zyBOE{iDt8@*{DiCb*5$|mCljW>{yn#aCzvLT>e z!%z0Cw6A8K`?H!COP*J7OjBOzr!>rSYNay@jZF^U4q%5316Xqp*2{4}0mKYd+6|B(IE?J}5;33SNqwcC z3Q)|}N@p01kmIKKv&1wUIoEJTG23v2RIBI~b4&`Drkrju*H{w;)|mmqK8An-y946{ zdtXC<+%M2s=NSST*N>>kekKHJ0APp4ZPU>Kl?_~fv?$`IfueC39{+7M78 zS+w^WLx3@|nBqV~U<1PxorVD2tLO;p3<0X{8Un(4Lx8G}(%}y>1ZY-4!8RI#)~ut_ z9tzgM^XNuPMY9`=aB^^^pE^^sBPyLYktiq1hVdxF0Gdr^%{|%>;C#=Qf^du>pxnP> zxgTo?DEAo@^Eg9*F-j=a@rD3n?8h$i1Vex^zGIo4XbA9(``C<~WC*a%eq%v6*${M9 zKCIIIlbU&%;U>{+e^$s-D*e=%nw?eY+y>2a-Xi@R!vLB!GtYAk0h;mgTKhahfMz*t zBF;AiXx4W)2p1RvG%I2wwbc-ySs`8gLPLONg)E|r3;~*5N(*0X2+(XZUHlS5(3+iA zX}S*4#kQ?qL;oh@+w96qjMUuPIVv**|ZU2h1`Y(Bf58w>%O z^)}Hi-!$IIQ%>o z;v4cFe=R^9{Hpzm`*cAHa^W8Z< zQE4wF$5txzlyJNOjO-UG{mhFTU#oP^B*z`}i8q8}It=wVvwlZ7x>2bi<4cwHJ>;ko zzakvJW~=>PrJs3`@rsH-i81xT|^oC7y>#0D47|uOL2E_D&0F< zvaslj1tC8(XBGoP&i+W0Gm0Ds2?Lho-mKk2g#hm4*gs?+MULmuhYN+{COXluke_*x z4DB*QfDj*XKsVmp0zH2u zVS*u`-tj#%_9R0<$H5l^*i#Gv)h2^2Te)GX6&V?_>mXzB$lR*gNBgvCmB3P$7)J4(B;`|WHja3 zY6#GC31yjO2F>8_3R8emyu%=%VM1{VEZzj zWwB8RE(i=6SBLB;$?*n`H`WTrvsv(mg#65l9FGV&TZ)Vi9VHCtL&{~2F@h5$X6QK}OR0k)maLDPwb0NZ+of^c$3x5bb@-7QaRltcLiVlDB6t-gy*|C2beGH<~jlGXaV4}A=dGijgKlSJ6# z!jN+)JU?eVr!N;9Ine#xM3=k75MZF*^tDS30cCIo+sMld0o~tc*&tkQ2ynjRdCL`s z0GsBq5x>e1V8Ve+akVirO!zhH%{7LAmI4KPUdX-#G6rvU;o1dKu(vbeKSF-0!-Bmn z5RQAZ_@4;*nHM=eA94;P$GNb&{h}~HL`BXuXb0?!?CKUT$p#j@)ug5je%DIz-_YGkWbcyUwJ}`tr49U|#_|Ong`LWjgX2>1~ zcEK)Gd;9H>T5AsSEiv}TAwP4b?q7u*j$m`fj0AmWcjJ8?ve%NqJdXEwi1GepRrxOD zCu=g;9db@41HO*L{>?C;X|T)@vTq@S8k*)OVekrV_(#Z3)?{E;IZ@QM96pz9r&lFc z4DMkK^BDp>dpFy0#}MGzZ_u+d3;~{fC7sG|2=MIBSnipI0MBk?F4JJUwur-FZV#miXi<`*L#JOrw+w$2XX8YL%aPk>j)~=X-MG8;9&#BO~nc8s(@n z1eoD&HU#x1Pc*}0DMXVYfF1ITRN47xWP;1-9x=&tD{bCf<)<{gTZ!YmF#+1qof@_Bdgks_Qdsq!;(X0fWu z`I1>oMV9v3DyhExF#~572O2^@E9Xo0&RvF3fVD?Twcg|jskm!tZ!iQ%^#ZHcMnlk2 zEw8dUlL_(-A@%`Px`Mw=sSc^~Q(hYTh$`m@B+5Ax=k`&?&ry6&vRyse5Kz51(6o;= z1PH-5PT9vB0)+T07lf0H^-+0lWfeWy5WK254y&@SqEu@*p4?QWD^Eu{PEM)vQ(j7S zR+aNI4s#;R^BltfQjKBHbFLwvqe20nR%P!d$Df(~8N$&=rO&VOGcQ{I@+xO5+OV7v ztfp5Q+oJJ2kY#q2A)xWRlvU#zLl}TogU))bA@s*+yQu_oOk?aE5b8m=-Vk7`5|+=6 zh5%dbU{i6kA;4DsSzxyrf-bO&s_cg$WAHi-b}o?u+e(e^tnyPuD)K;;vjGz3l){|$ zLq;knvJd_HVMBl-cQVDJhCoN_1;S&707q+J89ZSKaI}kQ!l#T>uy-4BwVyTwXvWt7 z+RqvSG*c%v=V^@EY9mqT8*YH32@f2EN?SCW}c?42yo25GQe^A z>cEyFgmdMM<~?VI2Gi0<=1t_;S)sufr6Ue2?-3UJ*`dLw?1_-cys5l)PH6CXxOPQ= zBhj1lW{`Hh=6-A5ES}vE3LbzIw+A@Hdo1rFl(T)0PVq$EN~X9sq)P3n0LO6K^3J8d zJf%}SAK)l#dmfu?`}I)pOmO-*z!A~6c{h^wX(;%2&~_DY#A3M$IPOSu^}UDJ{t5+0 zA~%n#fP;ytuD*|v8mv+_3cCu}RYzR~>>J~*0(NLMt^)Q#(_MXEVA9sA;50C(a}}_k znC~iJTfW#;z{Yc#tAMT53RmB^m~?AZ@ETZUrK^A~j^!y}eMPUGISV$Uy(E^#rn9Rs zn#&FG3d_s)*VrWZ>3a4{Rc_WC`vy?ZFfI%`C1X+hRbb8HaB?)H;%Jr_0_vrTqgiSQ zsFx~^W|<*4c+j^6!AHvtfunf(!wN%yDbcv@AGX_&p^l@OAJ)yailbQ>_CE-rC{91BHQ#quChtlQkJ^3OhfMfr_I!BCLmBi8z`gg^-A& zIoc4QmWrb})(|kiQ*kuM8y?^fEe;La{h^$Wqd6>`5=V1#*iZ2H~{G7{-HnzIZ? zv;|=B_pm*W3{)J=X~ICo(VP?ZlQkJ!gt(}2V4&h?E)fQt=BhZF%Zy=BI4X|jazlU? zDvss~Lx2`4j^;{3K;fu3nyU=~o$FP|)V{_LFiTZ&G}jserX!DKA;muo!J`y8KWq~Hs}zTdqq#Zkr;1eM?yyr$MN}Nky~04s^Y*a4gbY+1&7H#FF3NI$*iY8%q@E0C z9Z3ccqmtN9hl{p>>?y(@43-`ZJ6Dr|ig9^7tj0mXyCI#uEu2HvwD*hQtZhuB0&!jr zrv&1>5>5o-ydCcK0}|;#oOi=RF2TJLi1S`J8Hn?GI4idVyi_30o0?Z|a;Ky(gq;z% z7@$a2fb3K_$-`kg1afa`(VKTO?T&EP92{z`zUr>kr(x$XT+_iZpNm%Cpnljp!#QL{ zt#*a8E@L7U!Sj=7r6PEKPHOdMxYyH2q$7B&h-jrEcwCXBR=Gxsh4;%(4k`*93rPaq_J5UORs6}ty&9qsOtYQ$gRymPwW#vSi7F^R&HU5Y$s|R2c zyH_NKtf*C=NY+LsQlUQu5nWa)^rvqmQC3BfUKb;g4*eNyv{IozLsGOF5Xriqyj1AV z9-3Ega;Kzu5$9zb1}KshAUma1dc^)5$GxdVZ{AH89vgAymO(2O@-r@?8%joVsF0sh zAtXY6#v6hO@0cirM99x%lLBiwD&%L1A!sX%ir9xELml!nCZZck74lOa@l!rZH8tWq zN2yd?OE{w2xkSiMObCgPpJ^rwRHg3fb(#Lk+4JXOfgLdjEw{H%)j zDGl>n7jgcMMA}I<2!n)aHX4q`G=~TwVVXlt3S*kT8G$^%B@0v&Jwv*$j@aFKQ*G<*G8PPCP8i$@^hVGfSHU6 z`MJRm&T1HMtfe!e?{ry_O;*K~->Gr~ZHxNML3$(jsa zk2rJ4fUmf=-|Wud<%oS48K_8-SA~I!BzZgHCu=hJFyd?@0~JZ~Nu)<4$*0CBC<_%y z@|hu^EL0@PmxiFnrtd}U@0h2GBza%*RFNb*BYsN5Jb#KfT~m;!iX_=>7{DP^B*`y^ zfT^vDB>Bw{&_Jq4lHY}ph$Q*b5K#UqlEjM2FdXHtB1zH=0TQ5p{61oz3kh^2$u1F7 zMUuFqekwpQGosF#a)_xSNiw6_G#opsNRlkW5mKqu!EBQPrcse3IYMw@sHh@Iat#4~ zt0GBy83N>1kt6{_K%G^QBter46j6~Rd4>Q-R*@vV4Z%c`^f3f@wu&UlHw3M_H)@{= zwR9wjFRFV*6-iPM_0uZUePGn7t$^+-l4Ou!fFe?nBtr}Vbyh`^3^fG!iHal{W(Y8b ziX<6f2+&dSeI zYf#bd4EBm5<_-*0T*Opi@Cfd+<553ZlRZFChQAHc969y7( zuqtYgz%?ChutpfDXoC$=KUq_x!=p|s8K`K3&B7oNZE&O^ATg9YBx)Z_jw;&VZ^BVU z8yp?=GcR&HDe9a>j?;@E>K0*;s~H>@#li;|sAz)|gn^1S_f~2}fr>V`ygP#nqjm__bhN?6!azkETp9I~ zH5ptVbq+xyy*quAFi1oj++ql5fmF1?t%jgm>uaL+#mquQ8~j7EP|*grNBzv4S=<+O zw&76kJ^xb}B%%!-5&|ZRwEJCA`#W+}(FXSjM-^@GXw=WV$nlw|^VD8ur+Aw%NJJYv zXJkZ68-<+q3xz{N`)|F#r({R z9P?sM2RW(`hCad|5yH?<2ol1O8?#R&M-{>l5RNK@VL;5!yvT7#%xS7NjyX&iBtjTQ z#$*rDxZP+&Fm5;2N1ieqpjAq-HxF6KN6g5FVYlq?fF>PpRCDX zUChaffPvb`-e4GDl%qDX4>AM{MAb(2Mngc$^ahp>?1K#fV?ec$eTX5T{;G}aLk$5w zqc*Y+Gi3#jP#f8Y8-kuTtc}@a5J_)jcZ%F`PKOs*UVR4M(>spYvjNzbH7WjqD4AquR*6JmzO!QUrGSoZxxpCcJsvZ1+aX;myRKw%WS(Hlc;Eyy6 zAeGv|A7u#HisRt8eJ?qx9sHrfQSIQ5iTjzCmA}$u&kH-H)3NZ&4KORf4X3mKca1y& zZrgYR981df@U3CBv6m6xHim2uKcH!{J^Wx;wuia;pBLb2c|m}y%L4*jH!ccromRGo zXGB!mp#iR=jtp>_a&&+ThkFLNE>|4jN?A#O>rS#gd|yQ6KOw*sn@IsKyG#ji?W7{W z1&~mHOA>npIOCrh;M`ZXhfAaCzG#56#(02JznTE&Z_@*ugw+K&PihEoZX?^n8}%K{ z0Zvz11Ds;a3UHn{PvV z9FGm&7iU)l*!6GMTgGj%-~#Nbeq6x58C$mOVXrv1O~akdKTh z3t`Kaof5We*$ZIHmQ6RdY}wvo%U10yKN?fThAmsRh)u2nwn@#dzG|cSlUVQ=NZRTu zV5@=sT-I#t=dvncKbO9Xr^hn0ApvzTTefsSwPicY5Hl=q9LF{ZekQla#@+O0dp;=r zJT_lUhj&U1hO76lD1xI-%TDL6aXP;=V0ou!--ZOfgV3H@zNrPUf^S-1+~NBHmD6px z2c{v>BKPq~lzyx`aoe)&k9pfBG^m#Ercu1@pLw{=a_@)xysO*~@`mI3C2m-o-G2s> z{x*m=JdMWF;RmR~-W$|O zrsc-u)bifwz7Y)e@ObZcHq_xAQ)}}75?^^+-&w#6NA=i6%?)yj;ppaJK2XH0tyZt}KiKlQO z8@TuSuLDb8;nYl=e3Z`$n^|})GyhzjWLrZ#Un03pE<@e-(+|FIGvfh^Fj?|>zs@bH z2j|}?-*@>uwhGUs@qP&K77y4LaHL9q60NBC!_V2XK=IuL8^B!$ zKt;_x2Aq(EyuE+seuI;|zrhK-jw?{mfYf;_nJmv0D8rd2uVy69hPVQ= zaOTU~3`g}Ay8;K`EHiHx_WxQ~B=_yY|$!-if`hj_{$qc=+(Qe2gu!s+zNK0`cvfS|5W zP<@5Q8qR7x{64S*qbVj0#aC%SoM(uXTi;02;mU#L%EgH*SKZkhj>oHU;n@? zoG)^@7gExjK^gHaT8K>V5?AhTILrHu##rVWKz*#dD$Jj~%UuJgk|%E=OL2v302BJa z@Si~cER>}80GIm_oOoT0DAtpTP1&YDpM5MSzSEF}<$HTH%GL)SsKzg#blkq1P+}h6 zh4^dxM!Imn?_%_t>Atg2u09{XN9p(?_?zLoA9TNOE`-bU#o)(TzH5CL75F|MixGk4 zUc+YWeRq)Azl3U_T`T>g>|RaaG!E_2X5W3Nq(}HFau9jsYsbE$d|815jp*j~^X8#kU-s|L(hU z47w!WbD*DQx%r0H^q<|QLzEG3;s#%O)Rns!V&u&Plk~VN`$}YJ9C>C^OCT3#n@ zR-?~6d3;lNdaXY5TK>PG1xugqauuWF6iyV19Nb}D!c-jInx5X z;3+(xCpD^}@)aHizjSI<&PPExGXj-hkXP8B+0+FnVnJaT`8Z9g zJO>ocq>wY!$sVJYueF@!Y!*sUVHJwqX;Bvj7t-!dt2!B4cnDA0)XDI|KZoIDZWiwu zS-6c?_E9IJ3TanoUuD)k3u#too;oQB+yXr&Snj82t8l@oI2+N=)^cTK_nGSYS`+H}%Z;QwO$ANL$8pzFB4 z)yOIBwAPZTpuG&9rLHDdMX75hXvj7M2X;+Wyw@RtYb%rJY^RQ9wp&3x8~=5-Q_Gpf zHvE5zG?netTGGD5|F7|1XB$pr+W?x$w%lY}<{Jo)#Q%&M1ar80xrSv2{qF4k*=_l~ zT)AjO(uP`o|6U-$?fO{m>ldk9#}nz($Vh01EqsudVrJx?HtE-jX#4?8f1i?4Zl<2P-5XJts@cq0;;PS^iA_ z6r{?{@0O|;Qu*{vlr4}2W=s}Ly&GPhddlm)nGloj)Z3Gp)d zpX~>?{z;pmt_EQkr3p+(O$y~MWl?6nhiEF-(SIc^o)n@;WK*{#$%DiIa`WKSo8jpc zh?)%@4o4W)+cl!EHZ$HiN%Dw5S<28x!?l_shLvN(PTj_#-v_BWkMxQxXIpq zLuhNp7Q6QDYltKI_HqThQwz=stGkQsl;mmocZK0}<5F3qp@l9v;Yb&pvlO|No_Hi) z%2#k&804~Iiy5rWR=goMG)w*_;Lv3?5#spo!8aV5F6NP{*4^F|4I+Po@!w_5B$zv9 zrrf~>qsOlV=Ps+6VD4y6xdYX<=a0!C6@gc^R6J6({@6)@K-Xq`7{}#=92vdyvs>yNZj)buJjU zq-*WCuFgf{I@{NGEo@)AXz?PRTH}_jS=BLa!OD(}=csTt2q6qyWGbuSi5{2iW&b{#0yc>i&k|l?;02F*sy$2$GGNLL#(B`Wn8Vc`v1N# z|I0bR2iGlFy@=nF_#b>*ETSEL;exK^%Hzi^?p(g1qmv$pm$xP=L%SvyFG3Zy+81{$ zS+IWPy7qMkukGk6UdEbbP?ofw*Fp_nzq0117!CgI~F9i6K+1#cX(Y}H`6AF^Dw9n1^n z*#WQ1_7&NVx8CmO4cadEh9W!P-K!{s!!;X7*%IpE7!M4nHc}sA?y{ypQyEwXf`0y>#6&i`~GYl?%GM+SjF; zBN}V1j?`G;SbdY^8?UabOK>xmtZ$jt9&U@rk$Fq)J~6AQwkbA=!X`!hH>GRqtEa_u z@@S-~zIskm3fp$rfO3Q*G;4`sI3)~*i8PVsxlOH&?G0^pb?r@!wGFMYW-Ah}jW^;3 z+NV^Gt*+%uS9dHfLTA;PxY@`ZuZCG$Vy&$#(?ktjwPtaLm_f=o5{(GQ78DeUq`A7G zh1$|x+Ew91W0B?G&MI^Ep@Tk@sd&t1v|UCwlyh5^UU@zd=fiA)#17n z2Z^=TfOk{PT)Jyxb9-HF!;HjTvuoqE?bS`nwIYoT4Y3HbR2FA3sdO!Ekw~f+*W-lN zp4k>_i?zpLGpnu%!s`3VY1o)W8#aVfUAU>bxwbWF^47-2_WJ6Exl+{0N}|fPrLjfH z1eehw(WTHbuR{m8PRTb}$p_P#rm$=IAstpYQZucGo4{pD+flf{czc3h|qw;I5-v$(C< zwGGkO97|cEA&eq66-G4x(c0>1@RNp?NZpL~Y1OqT)9T2Kq}1Y!)pbgS_QobuV8g)p zTDZA(T1_ju-j;;NnIv(rwIU6z^(p0u@`yIIG)H13+N~iH%UJuL8ML(@)VX|J2Rom& zD?8S8q&Qv^9S@Zq4V)E?&4QnT!K$vM%Q_Y;7KcQwiozPG*H-iF7){GwCMkDqbG*7e z7KyZ%hT*i;t*vMX@Yq?F4SuL99pp9v7oE2-1*EP=WnS1m9VeLJ@qpG&B;WJ6jFegJ2m;?w)By?0t z5{i&aluQW;Bq1b(qFj+GC}5 z-tYUL|M~MgC+|6H@3Zz=Yp=a_otdWbsmKn;t!YeWXqXhAh_sscl=`U|mB!HC3O6zl zJr%Nynf=(6Xl9!zLrA8PU`ANqB$v~Zlg`2OR~>%HvU#b3So>-D5L{VL^AE$1R{6h= zl@S-FqV3u0N9|8)gI7+ECzA=ZWxlm+{(-aSEh~p<5|gI3#9L}021Ts!+p39lXvK-f zmgY7`B`u%7Vr9ECYZiv8E5_hW%RgmY1fUsCqKuJ|nzXdSIWlBIPnLSeMhv$3hDnHy z%jPe~7zi>np|#dbX-PIWruq=$H)yQ!+VM`JxvjOOf+5%zZ=yqTQhmqhU^JibkM21arUkCO=$SFHT8^~ez>Q@r>h;EV&kNiq@oo99=j6A6{{c5 z$QMUrZgJXYnICntLa>b^;Mz8us6nALd%5X*(za@@X-hcu^;4#1*snRWPSqQ>BpZ@7 ztr?+RO{F!SoK@3?FyAz#K3+4W9*xhhUE^0QN8^#ENli(owGF*JrDYxjJ^4heEM*YW zDbSZ^*^x>rNx`{xR!uzK)>0E!r{c7rkB!Z$Yb~2KC9~Pr!L-wAV74jsjY+s=rh;^k z4zf+bu)_>uoOxz$F^esIK7Jq1+7tCQ3qfq>#%C>zf!O#aGYCW7C0nK@6Xj!4Z)XN= zzfZAz?d!E@)00|e%&Ns$tPYjQNi0Vb7%oxL#(0XC438cYoqbz63M48L>SZx6N+er2 z5l9N>rmr(zW7yO+`s^^4YO6J4q^XHG zdI{F(s8qkr(J4d0q*^e9^QQaWbT<@_PnuPSuEep;Tw~9Qj3#HzgF1vhss1Jvd)t>C z(msFLibeC;HCvm;lMM}R4K*!jd*ka{5j5zQwt?A9Y@4QgLv#22v7E8eL6Ay!dB#UD z4xH6mhXF2nc(%NBjHmju%4fx9Oi4Ni`g5-N%NC&*Te=i8==te*+L%Pgt8wv;g48!- z2(6yKnZAQ@d|hkH^kh@xB)inR?vI zS-Nt`tT|W~Ie2-BI5x9+V3ZiIa1ybGSjwg;500BYNIj5g>V6jkGopirW0_H_wX$i> zsliQ$7{{28UdfreV%g$UF&R+>y<>eX8U*5^(-xoTj~5d0+H_oGl*o*ol!k#g-E%$hK%ekvW4(k|OD3H>4r46mwbiYM7$WfqoF1B2jM%`LU2 zqp)K%<6X9LDxA8e=Gc@;>7KwwDQmfm5w58!c-2aDze{Exk*c%NYIJ7M+n$zW*%6MJ zB+wov-b2u3SlY6Kmz0=)I?PiQV6ry_Go)D)lYSkrZ!#S&I%~fZLo;OwWBnn7l{>>& ziAiP*F>C6ihA9}dXSACsH7!&8u~93Ub%Q_88tF6gdqCDB$BmdUV8D=}+=?Td`LnoC zF@M=IjB=B(lLFNk|9#4|moc_KfG8i$vB%UHe64H;C$Dg7+2m8hih9gr*rOu+nh}Vd zS{^og@yhggQeA5!`a^VQ4Ed&>YvGEmb${MNqS`05VF-*)t*N%5KF&~5H{O`fL>;so zW7|~C_3amFSpT!X=3Po-+ImJ|%BeFOK4Q4dU*odbX+`}IM)Y=h%@k&1``O?E> zG1_lLPAh`#R~l+&aH=oC$2YZ=#>bAu5AqEgF|53lYrJJ+Dn^zL#*gIApS^tk?xjPQ z%xzy;J@=4h_{rR%OGbLzlM?omV~@ zl-bMXF096i@nK_zE*Z82YtDPlTi(9sg7(s(2bK<+U?4Fi^snmg^jJ-7*urtQlHbYcSO}L7Af%(^WZjSj?K@U}L%b&tpIWF%i>5 zGaQd4Td_z|j!20p$f#pEr)z*S(OIenBf@Ai)<|X43Y8r(X_X6Y)3nHPEYxu&FO{9s zQM1tCj};KbSilUk_?FoVaP&0NA3e=CqbIX&m*T@PVJ3R1`t1-J{IL-##1EYqcZkyH zEI(wyio>zp)4Jl2cCH4YHp^%NOcOCOP8DDbK-V9Sr4&<*X1wRGpHk#ZlZ^5Mia!#G zr&j1-)7B{{8)GyhD=X0Nho&YPx$2P?FT+Hpy|w(W`BXYKEkY{nk{^tRAHJ(IU+l%VD^O&LYj8T>{uIpMRkFF>EU_hQnAo!D?WG=~eBBIMvme zHA?k&CN!Wc<%F_s23IF3P`NKgs+#MjVd9TPE`LqREWW0Fz&1im5_Trq<=A;#U*386 z)S-2AEkX;D03;4+lhe6e1}|-J>ULgy_lJRPO*K;yJ-FCs+NW87 zOk$dlj5$dRyjxmQ?(MJ>m}M3utx5f6h_!;GKNU*Hj0|I@;&H@eJWw%sI4Nz~e0 z&(Q?ecd?k$6yxZWu^io1OLH8>a?QcPT63%4XzM6IV;r8+(WiW8^4Fu#%rJLwYT#Lo z%nlC7&lOqjH_V=gRjot0;gI%b^pS98Kh~tJl`)-ZZkbe9kM&3RNE4RtuukI7Cc)RQ z!L<9CMInX=c9`{8SlAc#^aryeDo_dp!Xoc6lKr(g)mrf2X6s7w}|5cqCSKO-$glT^=?fJ?1yJ5R^-t>49FVj%#9O zi^}N7V*;o`)MMs?GuMJ)(^RYRdp$02wIrvY`&u@?eg1630laA9U^-{2!!sSJ4Y8~o z(~q{cwL;=VX1_Fh*$Tg+SVz9hSR2F(vpUY7F$=?PRDHbO43L^@(4U}FV#ZYI{#ee; z%GrluBdL*lXZ}E8?&3q1&o_)m8BxrTIqmqcx}AvmAvMJ{HCgC5RnUw}6= zEXu~kCDZoN8f#mc8s(>Eo~pegx_x3ihAHWhU8>01X|vj}B?fKKdz$)0FF$Y5a^rNG z`oS@cmtqLQUPaj&(QsETU*<1`VmoBz;`y_%*fD4RGBeGfw(LPMp7q;BT3vWoD@PkC z2XjynX(M-7^)K-67)_VryHv;ZQacQV^|)(gwnkCQ zQ@GyLR@>AVGcLPw1$N$3jM#o_Vy$Sy{`?CqLZO{Y?#P?U$v(bg|RIXO6=whi|E9BO~ z{w@M^$v6Y_|JMPW#QZrc;lervkRD)gMKyCn$+`*6=wfuoK~}OlJ3t^ z8}?{u8Qmqjpboo=c6mp2LiIS)oSI0$+tU%wtkh~{h-Rr^&zjOOV<2M|WUWyd3e5@v zi*;g+T8}f^*5tzOEMs}bkg!19VWTFql^ON84=!oV4!_@I5tC?BFf|k8q@Aa;(b_`_ zT)0ljY&u44r=YpUF(KWlZ!}|M@-vGgP8+6)8H1+|vo81%Dp5}B?;s}~f3?BvUYIpT zYm-cUYU>-Y#$_7OPOY`I6`xqcV3l2WO6XK4n6iZGgo_W1!c$u68+o)L&Q2$_Xi=VC zzbG#^Ml$o&bb5MUpgg@XP(CW1VRZU-FT-GjKYHg-+U#bHO%EGPhtkATJ{h~7oX*$J3G>>y!|BRyHSW-^sA)J$);`xO$;+@h7AvKL7;1T%*) zM() zjaXAnDPy(3)EMKt1ZElRuy;6BW;XZIo2%rFEnC0s`Wrn?OC8!weS$|W%%Us?SB$~f z@OM%pYu~)ANu7a$^K!CmMn-n?oHP}02kQQKD1EjgJ(9?5VCF=T--!PtUbQt%Y??H! z$sbd3Fsd>zp{tpw138$q!CkPc$=#@QAsG>`!!`-_8<%E!v^jK>ipm+MK9a05Xw9jb z&zvV=8qJPIN)VM|>%*Ab3aK<62dPEyvICgp^m^{M+FT~eVX#p)D=`_XSatqpMCz3XR znIVd%LTTsDG#IA;uotIcDeX+JlsQwiYAXQ};`}4yQOdSBW>h!cKMn-v;X(!%1?+p) z(&iQOwqt70rl*HWmXeCdnPSAu`8O@`WjIYk4T|#zs%7TjBAZ6aJ4{bm;jef?Q<@jk zpk~b2G|qeDqa9B)k6^}o8-`nF~aq*y5w zyUfgqd1n^9(}N+yBz>+^QwQ}**frcSQku?ye7MjFRd_qb#9=$oMNh&S^{0&*B^lx8 z&dCryJ(S16M|(ogmS#P|wjr~n$?5DNOR*cZLpx?L*x{T^YIKaX+-2BF_78`ejyhEY z50048BhO@*#inKR!GFP`16MAapVFH{X)~V6T$iMHsdjI6Wz%cQmOon;n~`1AO0^97 zhd)o%1i{)G#`K4Of8tdB=ABL()8yQnL_ST(Gu|*OYW_Mm+KY~LrtFb1C{Z734w9zS z^-phb)yeuSbZtS;XV?BSN}^+P=il}jcK6>}Al6XRG!ZM@No-%K0oWuO$7aWD9Lpvd zCdER-EP8TkSv_IaCe3+1sy@Q^ww8LVLBuhGPYG`VWyeJvjdL7-^50>gYdS#;b#a;u zYu>5J40;OxkoBUa^X8`yAe2|2Co~fxb2>IvW@ZPCiloquIOC%8VOHPt#LjekjBDdF zx+5x&XwwFRTB}U;50dKq60Gj;#yHa^qFJZdCa0o<^mmT@?ca9vVl`zNmbA=?Zb+Xo zs7*IXC!XMX3+gdFwob)vvobcmg@?U&aGnkeg>0MY7=*o<=4LEKr3AHV$7|x~qHCcG zXCSFwGnEfZBK0wDjM&0-kk_ytYaGt%?zb(;l;O5E($PiDLUpE3$FO$B!^dW(X~yCi z4N2pg9S&RC@^%`rXdIfgN>Khn_&nE5omr2TT ze)uCZJ)0k9%J|FHM+_|qUx{LG4QAtWO!z{BjK3TQpWt-bQHaQe?Pqn1C}LD9mP z7GwYPI3%-}H+MMgk23K&ec3vYv?M+b&?n zK759PgGI;JR+#iEVN5t)NWJ+!^(M|19wIzUc#QB2;n~9Lg-;6K6n-WAPWZEMyD$J_ zv%F41eiH?s3xz#}y@dmWdkV{idkL$Babdl1lCVvf@ZZAUggN-|Ao+)d5n)eZ zsc?{Rm~fOZDvS&H6-(qdSvXxdOSnL|M7TnDl<)-MX~MIG7YQ#HUMIX&c(?E&;giA_ zgf9!<5WX+`O!&3%N8x{j2o6S{PQrX)H(@VfKj9w2a^V=^KEhgIqi~9FKj9qVB4NAm zaN)7SHNv&R^Mvb!R|#(v-XXkC_^9w1;opU?2;UZdBs3o>N4u*_^Z%GheW;eg*}9&!rg@x z!YW}x*eIMToF!Z+JXCn3@I>KS;RV9Wg*OQA6h0_?O89r-Yr^-1{}g^F+$Id*6Wi1; zS6C?QB^)3eCfrLnPB=k$yYO)#znhnQCt%1#Tp&DLc%Lu}->}5=Lxm>@&l6rNyjS>~ z@J-=QLJq~qr&u^rSRJ}ulN{8EUo05|1y749zNPaCrQCgDusO5shy=Y+2czZU*Si0`T~d}@Vrh3&#q zg%=9%5Pm9j@MS%eqpOhLoyg}l;i1A~g%=8M5I!J$QTVy=M`13;c;vUMuv*w8Y!|K- zULxEed`kGL@H3%_TOq%m)yR!9h=YaWgp-AH zgv*5|2`>;{FT7v)s_-M>HlY{s%h^S^r!XpP6z(rPM0keqV&R>_Cxx#FKNW5jx|pI+ zukOM@!ZAXA%@5P(3zrE`7hWp7RrsjzCE?hnu*dUxITq!(Rc#-f% z;e*1z3Evg|OZc0xCng*$cc5@@;UwV!!b63B6|NKBC45@=n(%YsFTzfk3$dJH;YeYP zaE9<8;ZZ{V@Dbm;OnAHSap5N6$HE_l*_dPTy&_?muv*wATp&DLc&hLc;mtyR2_X4x z6uvL~R+x(kIMaIwhYR^Ns-#aA&Jivbo+P|Lc)jp`;S0jggg*#9Oc2R;7vY{lenk}N zjl%tfhX_{-&kCH2MdoDUM##$_^9wD;fKQQ z!Vo6>EU#2pE^HL;D_kZ#QFw*$R^cWC?G~sd~za5_W zFBU!|{JZcy;Wt7L-(zR^3x^5!5$-2kC|oT(M|hj?A>pUOtwOg{{Dp&rV}$j>eT4@L zj}~4myiWLu@F!tTAD@3W;XvVD!aCs$;X%Tah35%x5k4<`P53Y2Z^E8^{qhD1_ZChP z9w0ngc$)Az;hVxQh5r$D>*w?BE36bw70wkNCA>&@t?&`yKZG9$zY{wBeg0jAeT5^0 zlY}#cD}-x=7Yc6>J|KKi__>f@&P;#G9pK}x!o7qE;Y{HY;c3DPg|`bI7j6=MEc{KF zJ5Y8Lju0k<2MCu4*9b2Z-XMHH_@eL~;V;7MLDEM!L|854FPBj7S;BVVTHz(a4Z^2{ z9|*q|W)JrH6bT0iM++ATj})FEyg_)6aHH^j;kUv+gk5&`%jqMm5XOa5g!6^R3(pij zD|}n{g|KiBpKnrljPMTO7sBnrf<68G!-dttiNYDeCBmbGX9+J8ZV)~zd|UXlFg(OB zhhH4cdYUb~UHCWQyTX47e-ri|>c3YdtP>s}JX&~~@G9Y5!l#9=2|pJGhWUK+g#(2# z;UwXK!Xt#I3D*g45k4aPhwua8cf#;+zr12$nXo}PLwKn0uflc0yM&Jm-xPi>{9QP{ z%r9rIuw8hn@B-m&!iRg|)){g$D~y6rLlzS@@GMr^4scO;{(KCp=Vm znsA-)7U3hpw}hVye-q}9@cEYsYlL%!#|hU8uNB@ad`|eL@F$@&(&t+&++8?PI8%76 zaGmf5;p4(h!jFYN3iC(#{C5?O5GI6e!Ue*^g{KNH5#B6(PWYDh3&#qg_j6#7CtO|Q}~(iS7F{5 z=_4F294DMCoFhC|c!uyA;XT4MMI5N;ECWBu}W5$-9B3LAy{3y&0@BD_L)r|?PP zE5c8OTZL|=UtV|NAmJF{6ya>)D&YmftA!5<-w=K(+%D`<<(Jc67!@`O_ZJ>1JVkhg z@J``I;oHI=gn3cfO;{m}3ug%z3r`YWDZEYitng#ux58kx&%dv5xNy2~k#LRhT;a{a zhlOtnKNIHd?epDDI9xbRI9WJHxLkOW@B-oW!uy4<3O^EV6YjE)U*4X=sIXDEzwk)m zDZ(p+cM3NO-xmHL%o-W3FA3ijX2*QKy@f-B3E=_4CBikr3xzib9}vDMd`I}T@K<4R+%Io{uv*w8 zoF!}*9xpssc)Rdn;j6;WgigZepC=q394*9=Mt?jjJY0CH@Dkz8!smpq3cnWqD$Gmz z{B{!#7vdO=DQCLyc;Vy1jl$1_KMRAk{(F6e!-eC8(}jzKM+(mnt`|Nad{+3r@LS;@ z!Yy zCoB+l6ZR4g7FG(!3C9ath4Y063l9|@Av{TVp>VzM8sQznM}#j5-w=K({6QFO@a69= z94)LBP8BW?t`@EpULw3z_@MAP;j6-Lg#Qr+8~t(%g@c4+gcF1~L~s0ansBbLU3jc; zt#F<2M&W(JXN0c^KN4C}YlAo_gI8Zo5SRouE+*_CsP7pQ=rwV5Z z=Li=HmkL)1j})#Jo+3O?c%AST;RfOT!bgQq3ttqzEPP$~uJB{w7s79ZKMDUM{6pwA z`}PS7Bf{N;Lxh#WIw5`$#nkV7;WFWB;hDnq!kdK;2%i(aCj3PBz3_Ko=gEFKy9kF1 zW5OB2`NG46rwK0*UM;*s_=xaD;TytFh2IN*6Xv$~a`Y3H39E$@gwurcgog^(2%i_e zBmAfE8)C?De${iQRy^n7T#m2{u`BlR^xRw6U-aR69w8hf`gkJv{zcF8h_2%-*YmMN zlyidc6w%Ms^M%4oMZaFpHw*6&{V^i=zNY85gh9tIKUWA9j6B_hy@maRn0ADBLLABz#l&uJ8xp&%$4Y zJRHb!jQ(N#;)&?RMAQfWn4TjfiS*9GU$Xu5i;;o!BGMz+-%@@|r_HmqmosenswFFC z&jGGj=Ho(pXFlyPjGv8lhRwlOlnukza}6VLSn7ab$1ivIlMFkYKr}h#@nhBg=WB-f z_p|5BSvLPLzW|?tZ%xd6oQ+Sr9mp^2rwD$Iohgg?QxHmp4$d%s$3DJGH}kCp%VsY@ zrka+857lA*cFe~#{td##I{d%o zD?^?g%UuDQ{i8qdZwM|A*En4K`|Mobhgkp2!;9syJ!JB`5zjMm*+0t<-DU@VTQm64 zM=d|v(CS1U{2}U((U$F>O*;gHO!;!o!%ve9^!<}^S$@ai-o8T~pHFd|XRL8E($2}a zXTF=JVXr#lMSJ^Kq-B=7mJJn&vAtpfPU&E^C)(ac|$jt+O5cx+5OgKb!U>2$}qz z0YAnP^6QGr^4pAizC-`wU)TM?v)sSuf2Q$zPiXUXKHEP_46^yN`M$yv@9p1oMG`vv!C8|?t|cO&>!+6SO5i8g8%a@e3-x|8>$Bw~>6$70v_vX}=KlsPLfB)lY zx5w*~wytjP@+hB5Yx%#+*44+A)&@86esyl3Y;|DuU4Hr#Kjk`I9`$oM-yes2=kcLm zZHu=}JbPPddrs|$Z9U5JYA?MjYtI(*_U^TQ-v5R3`gYo$_2Y-zN{@HHUXz{mbv!$s zm~rauPVfJo@*n@r2Y(0@EZnrb=e&WPwg-O+ejN|iCQ566IMtW7{4^h(KE(f3%Ae66 z{c>9z?>z4G9W*h%txqZ6UtP{0@Bf~<&E7u%2`TS~+orGX^_H(u zrZ%OuHCtEDp0S!dsm-Jjd>sN&AFsVD*VNxL8>~Dh=6v&d`=d2mvU9rDQu72frU7XBK#uz%I_~Um5UsK%^<2!9oKEJ* zQphzYTSA>q?}x&3Tz-WR(x#Lk`vMG(vx^Ja<-2F$U+_}=%f7BN{`D`aCG|Q|H}D_t zvTtJ{Wkm$Gmjt|fk#k+ZWAA%uz?%YJ*c$MbLAjp;9*>p( z67cRr>HiLRpTb((0^R`-Yfk` zsguWF{M+2g`#WBLrIW{x=e*jb1fwvYST~**E;euBecz*-yYYMzg zQ2N>eZ#3k*uE47W&+7|3ehB5%LXT&-Pb>76!RxyW@*V}3u7kY)zy$3*yf(;kXb%tW z=`8Ev6+^M*J-l9MsVjPT6H&!0dwAcYpu>82-=c)Wdw4t`ctj5`4^~>$!#e~%{a12*4K>EUSBX7ele*dw8oM(zx~B5h%81y*Ch* z8e8vef-5H0dz0Zk$@SjDaN64S-XK_TJOGu`{Iqu#(k4IcJq4ZzZ1H|T3z)sdI~K*x z+2Z{KOU&JZ-*`o{+u|*N*UjJJy#fm^*y7EB)CX?K9RowQcMTwL><+bgGZ61C<4qq> zmhqOq^$B)4F%8V&0y5l1-yA4O0JrVo8B

xjl{JNQwI~fYPyx~ckAaA0m3H<7qlRFKR z5O3aqjXmDP;S~7kRwwsK+=O}44Nau8$pdTP_Zpqt4FeEhdBcyg6!7MKh}wlWJk-~f zH{W0=9N|qjyj94X`#~w<%{o+aH{QGe-6?hMABZdX$f}cj4TQ(9x;weGD1sjX&Bb>g zK?~gAC1`=0n^3Jm-n;@2Vy@iIFdcsR+{yg}UYo_62*lufPIwbLlBI#{H}KqfGyW~W zTY0DA2A>I?ihGv?lR}R)DOpaiohc;z&wu$@?%!N*6S5S%jq=@pxV<)jYZg9cQIG>+ z-Ipu@Ufd}%LgubX$9=&qX4bC!*)(^P8@>i~2mIc2y#iRP;76FleOs?1wD9#; zUAF>hU7H;Db-mui*WYo&Wb5STxX-v=J+ee7lM^AQEGN7iO~QT8&F0H4lTpqWu6HW# ze7Uz+F|FMHvIJl5PhIyGWTxDoXUhGZ8{Q9e^83a0o+m#e_qL95|LD3~_&Vg?nkn~h zZkTK-Hv(t?{v4r9PK2Bw_frEQ?;mb9Uv`D7MR3+&=NX3 z1yd1e+=nb7>=b;$s(aWHa-D)zYvpBIC( z(H7j7#)iq73|=4WJxvCy5Lw+f$L@L`$XQwWPQeE(_ALOMqI>p%J?8 zSpw90ntt|yKtjS>OSnnTX@HU11MGUeb^jlp)*k%oj%6W=! z{>Kua#Z8puzm@2AV( z;TN=G&&uMBNbN>0WH`Dq?`I|!V=Up0k#K*|R%6q`jjQb13#6heDO}77Hx0NtbTft9&kA=xTBAENL%6oeyf?_JlCCpN!jU_LYpnFX!EJ=1 zI1#cl!qr#0xp2M8FTO7d*??7h6In zr+Z^;n&U1N0l#(Hy(I}kyUh`B3g)w}4z&c|8gnY$D=7^>0qD+?v+Xhn56ddUl#^1e zs`S32R6LgI9#!cFkIp$xL0_8Z*veiengp_(f*-nraGWgyWu7+#gw>Ydm$|aiEkex{ z9?uqXxXRqluycH6n9{J!(<;3Sk;%8j8DfAI;w%1F%h4)+mIzS1;NRfjo^5mB`x%Od zfpCr`WXUw=S%Njq`Ig{|xu(*6m||{bt2#wu7PG-#P#LBI6mxy0mkZzVO>_BrLO5q98TS^^Z|$MW4RmH@fmGaa%e_;SBn={`ic&!kT8 zOKyI#fcvk?Fg2pwTPwXoz`bA%&8^(^lIo0bTY5Eb~8>fQEe@ zY~lXb5}@i8tYGe>*{v!}ovB%`Dz6{PFUX?tcC!pnXZx^&RoEB|tNN`q&+03BG2Ud9x+O^UEZt(H zNlSq7exRS!ijW1Vsu9K9I!i#1`jv`Iu&nmy?jGpsdHVID@~?!K0Q z3QMq|?q>;*J6I0FOiMs;UC$u$7h4JxS;12Fw*(eK;Lqg(X1MVGMLDEdiDk0GfSEv5{fy3`>A@)(iz< zttI$P`IsuV5K0x^&8B>uG%I2sb!JtVI#aU?syudV1y_)Mk!1kQzM`L8YzfeepCNWH zu>@$=k9^lz0yJwM2*Rb70L`YbM%G&bG%KKsUuFr=>^g>^%Pj$#ZKs8=umos!6XWrf zmf&l4PL<2emcr{ePdrbWeFKHutE?4krHdq2Qn@n-;vIJ=MC4=bQmH^H8AzJqy zOYk+juF8ELg%>`{7F!xHc|!q|gV?jCr%@U&8-J**-cX{4vC!YrIc{H@BH#v&rD;ywSMq|Gxj@f9`knxo&_a$;P znO_sfzc6ZlP!(obV8TF|EAaHMEyYr z&Fgy6FjMcj6f)8n>K4QR{BA-BIE79$AR1;_ z@?$-tzI6N4|QU~M!^)@0BW^$IcYDd$AnmXzO!| zB|y(D>?EdI0y@ZhNSI~`2oG#r?hFwSuUJ15qV5k$piJ%(aKkA-Nj$e|=0pi%3ZhCMu%(AHGvZ!}IIc{VBxk3yWUwX4H zju0V$K>%c28g<_z$Fn)!Xcx!tS@B0k!z_y&kB@p+ms%e>Q4Huq#%0#n%Cs(XvL#rT zImMP~UFK9vfS$ux@@bX;+wzN_+|w-qwv90et&RGz7;+bEWR5d!4ve$T7zD!EHiz}H zb1Z??5pj=+y3a$4!UD28E?WF1AD*D`&W(oO!-KzOPqJBM4`C%5_nm2W0XEHJ z5Wn6MV8SGG++d9i6Y`_$?v0k<_jZ>=-FqQp;gbvwm#SiOnDORlnCh@%?~Zz#smLle z{d;W@a4vYp9Z~leGT4P7YJ(WGv+>;@4U;t)JQ4N!q0tt!v*kXOW>7GIz2h^MfT#eD zk3`)%kAA8XBTN8JS275)Xy z-hDS})|v}{q3eGZ4YOqG{;#Na0L!dmFZ5kU<9!)*xzJwtWLKnZk?|g3L--*YCTlX- z7WJ+ogNx|Z+bsi{2Fn~#_c<~+nuCO2#2`#}{4E+LYcg=Fy&3(%;40d-Q+0a9;1_yM z$P(b$9^JyT1bFsd9G&M{0zCT~I#t*b;Mq%A@0~3Ho_#D!$*)$!h9idYX+ zWGdLg23wxNu`BhgupF~Z{p?ZgE+EI(De(|-T*_uNvO3JN$g!&0T(33U3SGD^9IUYo#j1|YfG2^)EFv}vx@zq`@G?s$nNw2pu!Y*Uj2{c#& z%5CDk5J zkQb~#k#2jnn(waQNXs2+3A;E2kF$v7mQW0rp;RkvnULyJdfs7{0I42e^E$#3e5n>y zyF9Q}xR?bVTb9;M8?&VECJ2y6H0ZmB|wNv z7%NV-1PE~mJD)SG_0f2~V-sC#2|-gG$5guyQ>pt9ptZ9t|1&KKS5 ztZflI8J*ngEdjyvGd7JIEuoiFa2B2QCQH~AqwVH01ZivR0uUNOxYZJ1t2-H2Znp&3 zY9TA^PD_BTey1XLTY_IHQ&SZ|KEdh>p7!CA{CBV^gSO?Ep0vxS?IbN_*!QSV>eC~^u0L{LkTm0P; zpxJ?t-Q8#j(Ci@&A6~KqU$Y0RUGA|LUe8*2SehM2zu#0Hrp`DxnB(3t*5k%jghvOQ z2zTbQBHUijiEw{A7~v*$s3=UKLzRX1AyaOI`@Nluj-`2vd|G}HH!t08m4$4ET_W6P zEsBs<9O2GkuL$=7OC#KS>sxdI^PcGE?H}RZ*x(4ap7w}vGiXSJdo9Bv@8f@2gnJ1U zMGvy9Z~d}HMz~HtI>I&WF%ho+Rz|p18jb9Y#<6#Vi-Y4LTqcVZoekdZQB_9nM1%`W zwGl4H)J1rfZ9;^T{DuhU;Y|_FotukZVo4wQZ?r@>`<)WujCE>+)6VG;&K>uSZ~{0p z!a3Uh5zea)DB2sr-i=00Npm8cqRcC*C#}w>Er@W|v9Rbyddy6pc2I<4{>2fF)0alB zF2xzIqW$^K`O&_#^a(|a_;f+E@8z9vIICzDtNp@g-)m4|XBY7so!pC}eYyL3ZG9%O$!N_q>ghRY%iUzQiJm}|muINhUcqnRW?S%-(a2t!V8I@k} zbG#JcC~Q+vK51`83(p6q&mtTVeP7g*w0}km&jM|0F-I&;pqMQ?E6}q))BcDSBK#tx z7jrN%F3@v0sfE?XMzKIKyXr)sn0;eypqL$6U7(n~(1bwGN@kr>T{sgA8Un@aCk_Y{ zGnUT_6f<}(3=}h39Te!9WY+c7g^$82ivz`sI8IJ6+beqQ&YX(UUS^z^gII<8&UDfT zEb&?=cq8sz62hz57+QYv#q$qakySW`QN3U7B+=2U-H! zr8!5l&=NeSJANtKaTi$vh8gBy%|Vs`QzE$TA9D{vf&Mv~17d!-Hs@#-$HK2cC`z?F z=ABHbjHD~YKoj9ZV(u+uV9wDTDhB2p%@MIMS(CwWF)s{f^v}^8AM=M_oX(kZG$)9V zI!AMoB|t56j^<=b!2HgfqdC>`0Dow4RLm^{fBziKF|mwuG;3pFibo;Ni+K$c!knYI zz;Z;Z1%tC2R z0a}=IG}l@Jv@qvruCoMGjyXqjgC(GIrQ^6aS^{RN<{ZsUmVoJqIY)D|CFB@I*2P>N ztMJd!tXFlIb2N9x!c>upJP`AyQW0~G<{>dqeclsuk0Jwej^;iw_=K`N5(|?xJE`Ym zc^8pES2PRv#aQV^kaJ4$4}+zrW8NcVV9vNa8#Cje!jB-GyD?Tk*0lHLSl-9XWDerI z8p}9{^I9x*5a-=k*H9UPyE%ySeyrb>cvlB;K8U3c;=CEl8-Q&7L7caJUfsx@lD-`C zqDYKTB%E!>tvOEeWXzq6`)<^t8{cN$EwQ{Mxb?OAS4XY>8S~CXntwRvOKH^yp5=ZQ zD>AisOD=oz(@Idd5?ART}Sl4>I{jfBIUj%+a5I8Cvy< z=WQl0I+DAa&#N1`Q_`Zi_a$y46v>H@ozbdO-2Dyr-Ka%3zD*Y%8uylBBIKXu7#{Zn zC0y7)@>4EC>d4OsOR&c~Mv0I*^0SxCfwdfSvJpDDLF@^gXYHb;K0j)$oc<-RHI z-8>p{nD3@YuQgc1H%U#@%ztz?>v`T@1`gl6T`_vL=I1;@-z( zU`~>J9^c_4$v>@8P#5MT$rqM@x-ch6zP1E^Z2Cdm4UR#X<|N5SD$|@K`7R!&G%WL% zxOXZt`6o%XSq5+jbCTpgmVmLQIZ3kJ5)dHGNs?bhNS!44-4am$<|K)e&@deJZ%&eA zSpp0$}+TXT}6t0h2gbCM)t323wCBuSwy1&WxHBt@10M>Z!(x>p8QDl#WY z`dI?ntT{>2-xA;_<|N4gOMo%VNs>X90Nu?=lEIb$-OWjoJuCsLnv*1ZS^`uxCrO4{ z0yHxxNrqX1ui35%EE_;GbCRS)n!Qj8&4wq!)R~&?mGG{hW@lpV?v51$wb>B~_Zc!U z2R25DfjO{Il?anH8N?FaM`Un2*Ps#|8SI^K-6}9J=OV_5!8dr%txbf2ORkFvkz}P548W)bWFv)+n%&IezdL zOTgRk{VAw_7I9iBil3??%<+T$6JZw4BIYN&H&}!@esG|QNF6^|)RE)tgu9&_&GCb| z;`kOAxd*}S;&^Dn>k$PgVHaK4l%xQyli7;7{!Bq)w z2r~Jn4X)|P;If1}nGDQngDb?qoHn>F5hiOgxHaLOgWA>6a*(ix-bHZ1A)~XP(}5Hwg{+d&Wn6y z3AP5eSOOF=2M)fr1jJEu;NV}DfIh?=IQUkCEMLrz(Ecf=IdJfa#54yEzDtCu0LAVBK!0Ez`PPnI)jM z%n^nWmVnwaM;Jy~0xV(taExVY{jk#JfFGJ83{jiI`r$s704;EYp?A_f9a{KD82TiO z-z>$0Il@qr3^T>)OjE4GosKX-^@gPP76|^1`Xm*Z+EH&7A+@7ESp@B<*CpNGSftre zpODPhQEyF#nc{Rd#l=!P>L_x*q_;Z={zmrxR!a9- z*@s&K2BKyo`v^<08`-NY0b@Y3k$t2kp#7SS?4v9JK4UhrkFj+Hk1!kA$6A6vZD>!r z;~|p2k-bcEn~m(%$uKpd+@~hJ2Pn7M$UfZ`0lCda_8B6iHnP{+9CoOBrpiohWS^}Z zsg3OO?JK@DPfEJ)Q!2BOeX^ul0%6<>lVQqBsV+-;xd}*RHnOkG;Al3oud*DoP5oSw z#Gniu%|`a6;%GLquStek7CGLW^k$Ny*~q@tGT)UM4trXTD03Ef zv_43e*}XY|gNq-EkQHRl)QY1k9m{+p>3+*H`TG*?TPm|V*H%AGhA9mf2mh7yhSWlF zvxEO#a@Wlur+4swumm&>vxC3Y5*Pw<+%J;uWW4R~;D43O*unpIGR(qR#P3P(DHdUN z@B_6w?BHivg5AN-u>`w=AFNGFWp?m8SpuXoJNTX@_)`5h>3%_}%ntsq$&4NRaBZ0K z(%6w&Z~AyhWp?n3YSnGPZ_N&VH%ovEm>v8cmVl^XcJO;z0)#L-_`Pa1pGDL#JNPA* z5Hx<6U+W%&0{tEQF13DtX?E~?*M=!Cr5af4-At*>4*p=v08*J9{M{`9`ylY_zP0Yl zgn_z@{FWMfyE2iyX zZewVB_%WZR?cv8`+8*ZWe^G?1<;4-MF87LX-MBQuby{r?PmG(q{UcmQ9US2@#IiUJ}qG$u2v`zehpSB>v!Q;XR$7TmbIG$P@ z;TULXgyWWWfBQI|)b_C1EKVf*p57_7J)BJTor(%O+uu5_P4;ca)3p(H{hRzP0VsoIFF{vfc(`+<o3;!%ly|6C-e!jq;wRA$w0}byA$P~OT`(h;YIumbq z3EtSnZNP7~tbzT4H|IZryiUoH$Q-=IJmi!-ijoruw=S9c_I2|m!}XQV_Zq*JmGo)>(7*X?-7DOtk+_rb3G!t_wd z(_uV(+Jgd2W z_fAP2DmM62gsz`?%emg1WH6wc3Y?9(r2giWEKehQ5> zkj;AF!(a(UjW!R(H+euj)DkJT{~}F?l#^}BJ*kw3aEBCndXUt9IalI;`1a0to*T$M zoRU5Z%AofUAvy;a1iEyY1Z(`0##k8WMSbvPTqSr~6zD~ja*CQ*iw6aIF=Ge}Um?Sf zf*>9o$bJ(K!R|;I{1&{)uiH+=f&4mVE@8EX%8@k-@AU(zU(R(XV0U~WcxYf3YMwoP zPh=e3bqW%*S0iVrvftq*;|WYXaSu@T>35o;yo`F!eiX8WYKkufrPo)u9}`M+Iind4 zxE-x4R2!Lv1gB&x+I47rgb6t%Tli3CTr*U17_=iMJE4~Rvyf0)vXu#~CZTW1zGyU| zDdwSn$!tEfnTLTTizv;EJiaryqFBGDcP2bhneP~EW$5BAL(Rw zfdN9X;*0RqFXuA+-}5f~8)*JfxPknKBpRnrPUtW0J4ha~s2xJi>V6D}eK(?&hGzFT z8289`7NA$_Fn)L6`(5~D=_Mh=^U#MzQl})^8xJ3uhpdt*Ec;{gkW(@h?h^XMJOoQ_ zN3#ljY92yPc6}+HKFj_HC3j}=6Tw#J(TC1JK=XzdRe?10V6gB`-i2Qy)R{%EviSlw z_m2aRP!%u-uE6@1 z7L2CM8(aK0LQKQo2=nHafO!*R0Ea6yBkB=%z@U}v7UG(RYa}Yhxo0L~KX{D_G-s{A z|H)Y^k%Ho!Cy_F4hm=u)mYj1IpP%K7rW7wB2j0v6DFBIw)u3w%+zMr`#!J33w+03q zWoE#ZNE*%3%hsZ1@Q^eQxA-qjvB$~oj1?ovG2(T%GXbN2w*pI}?Ak^a;YYIQgFZ?VJ z&cIc<$O#x0rT(qNM^FA`Z%QsoT&$#)459GNE20Ptx8J_## zrV7_MvYUmQzu+2~0H=3RM;;_(%^rsTEx{G|`nA=4Mg>~4!^2lQH4Vu0g}9z8%4`c%u!=4Q;e1?`b5<^J0@M8Zco>8SNnGj#ru(GV z@c0t0kzMdoKa{^+Vp4DVHMGZfVb##N%Osvn!W83E=pFdQG_kjgbfcy_PTVxHU-qDI zIEcb?icTVm@D})G3}qXS=Qyq;s}R!%C%}Jb)=psefIDWYYVIIpS%}NjY3hO1n0laV ztVWh&aizV2+;UPZtyf%tJm--ez2X+!+{6d6OFfX?lb}A1%Xq~bxOolN$R@C)SM-5! zsTvBD!8qArXLZUikoqTnkz9jFbuHE7KN>nv9dIwBo>wB}YZUMmuIPDqa9qdv9Sry=ABYTBV{g9zTPQ?<~sx_ z?z9~W8aWRsM7m@P%PAS(S5VEc#Fa3?_^6R=A}jE` z7*{QSk34XUiSGB{`F7Ik`hj+=p?!+y4{?p`g_l^z_e!F4x6~ggtmBt=N@2)h9e=e` z%1ETpm$GO0ny0x%kwV*-?3A)UQds-tsT61Ak)W}5lNq!VKx4hm$e^7ruFFz1Kcp5NgbnTwZ-V5AtBtN8k2(C9uRcf(B|B+g1F zj@$#ZVW2Hf)9S~7Rs~v30ylNIv5HJ!=fOXEabW#^GZ8=;zd1om;xdt)pA0yV4;)>b zjhnT6UyK^xf_FxH%at}tzen{Zu#qqE& zUgnj%5VE{F9A)Cl-ICk%-y+B1mHU0L>0IRImHSJuaRY3?%VQyrLM2|gWq6nmKj4)+ z2@kW%;oi7%r{ZBU#O0N{A093Ol~?X)Y{dq;1_tC8hO_f`&2Q_`HP8iC$?ETf!+V2- z2;AMt&aVvP>sG?`cs)lcFseJsAtgA_K&PBQcK+VsFmn0114s)E#>>6Jkks6upU5>g zXq{p4b$z~_1A+QNzLM7m?1tl&{K7yu3|7cMdO@Bqhshrf=Y>0m#~@di9vyOZMXr$l z5@n0zff=(EX1yNDqkOrbWSW5V%5_o*meLuuB2#hABkaW|-6# z!Z1b?n2?&3=q+PW7QUM_ReJBt^t2GAlFhu9Cijs6^m5S% zn|YvX6dsfkPG%n5p&CWp9s1C!rfBRFWJ*E>_9S1bHY76zu8(zsl<(}*Gujj3by#4Z zo`wkCgL;-4i{SKHX04Usk*}GmMt|P%m9BwEa9r_4F;ieg=9^hP?vKHFM`XS(+Q`#R z2*A(Fjf;&s{RDiibn!VcgwWA`!UeIO<&b|b39ORGbS$~PutV8nGc&84O3+gNCt6hr z%54ce5DT~Um>!tG2k*eXUxsZmrg8ZL7tlxE7Vx=kq!Db7m$9_Sfh6KhNtw zFUb4e?>+Z>zUQ3pS?`%U^pUQiw(#*(sE-IX!->;BLvRvs_%%p}{aV0jCD3A1O3>>w z9V~TRgM&UF|JM104K)870>#q<#RmkUS~Q1@k|;HYZA8?U5*QI70A|huKmNV*?Y%U2 z{x!UvLyv&NAI3Jf`xge@Z)17oyTMHoNog=%K@BMXeqO=b)4U>J@`b_-r#LN_ z{rpNR3L9;DQTTzxwT^!fN9=Gzc`JvPJq z_LqNWQa2th1@LBRXyJb*n?%EmGVgT?ui+8LwLIIqPnJMvK7Pe-A)dv5WGC@kbJ#+> zivP4^U>i_q0?j9Epj2iB%*qf3xP1yEB~2?gcaK3c{|9NB0z8jJJd7(X+XH6F<}M>l z=5)GnkF5!UJL7ys#J%RQm3Y9H62HcOKTCM@w10sx3j|Ipjs|>urSl1U`}}KCx6ik? z_bYS^M*YtsfaS|uw&|FBAO8amuO>g)m@^)X{{d%lE#Mo4iSajoJX}K75o~JE5fJE8 zDJ9s(LrP5XrNm5MO3d=5gqf1=ITQSN=G%Duw5Fn(&!~8N-%NnOeDd&@fngJ?p&xq- z>-8bNv=;DVZ^6-kPYxv1f&2FY*pT9IDsZ5GI2-Vri56;{>r1NuYDQT6?eoEijAFu9 zF~Fw=n-Ki55EEk03G)*bC#Z&j2DYigjHU!(1EsfLBPH)sEm*4=cn_vSir*$Nmk2*! zS_!Oo@dkoQY0bd8pH`AKP^#{?;AQucenGGRhM@3tX^i$R~_q2U$t&+=k$&>og1eY;YU$B)=ckN)zRHKy}Prkv!|nH zdS_{SPw$51tJh8MUAJz{vQ-_cyLzUtT(+#eqkHZ2lH&Fm?WM(~CG91}6i$P1TGzU+ z&S{+;OIJ@TDK45ZjhBmXxzDBPtGkx1*|5BG`r3|VtN633|3912b6iil2`g7kuk2pF zVRhHK=(_ICY013U*xPNg#LtnI?sZ3YF6-@?o>^uJ%@>Wo65n4L$Ag%7YsZ zvRRMB{=d~ey<`3A=_qRaV=*s9aW7ljv$|(`Rp&9Qmvv5$$C_e^%Ea_KKiB`?8-t0U zP5hqyj;1c}UVThwH(lX>4$eT1@4m~rJ6E=MEbS>;hGxKNU*5T*W5b%>_TJ;xclH#m zV#S8XF2@hq;RICzzTeIt>Rs2>j$DEawKP7fn&lIz#VO|X-R&sXuAUX0-3o#Vn^sl& z3mFq)#l5I^emMMSac6f|y2Kc{Y*}XyZOTTC$9Dl-)93`t0cgaG*v23Hi$(De#)ePppacrSMd?iz{EL$XTT!mL1{n^(x& zh9+-21|p-i#2pH{Su>5oAz8ui6!OkOb1Q@3w!O`5g=jibc7Ej;LvhzIcVwwMZZ8BZ zrq%AqNp4^&|7Ii3;FO}0#>U2A!8~_p@a~iErMmr#MvlNIm>U@NZ8zIQQTcNOYHVt3 zgof#^JB=y3>Et4JA7f*^J25Lz1Z86jd0}OdTfn=5W1!nD433zG@s;GV4Dh-7qbaaMtweIRs9z#%kTv4#=u8XCo2GP|##kazSrcn-ZEkLF zXl|-WUWm3P+HhO6xv`}o)`|daO?9~3Qr8lj6^S*rIPAWcp>=CtzOKDv*_!UPPD?{c zv^CyPf}aJm>Z6tMs`jSlR%lAZ;;peNXVtN$<6pL>v!ff0V@EG~sHL52*C%h8*AlB~ zZ)-}lwX`(zj`o(iMX`qV>gIT3WvjCw(w2xdIc?SP#-_GL#MBx~v^F+Z@u$q1;#G?i ztqB}e#bfhhNsUd-?TNNXA{wuY#NtrY)>P%x*2Sw@YvWF$xjI&v3>l9lTAE>LQb5yV z@yY}YXQHLOy0W1m8N_C7W1^-#(pFuKC=zvt#!OBfOp{XD1|+Snk$G=|S4CSID;Kq- zsclC}owh_I5@oIy8-=qYP?!u8jW2F#ZEkOBYiMY1X|8K(jm4d+lIptZX5>MX#GT9z zBg3)NvwCG$=kh{~ow}1+Yyzq)k&B5~Yb(n+*$b^*x4g5xS1J-H2xNJ@vMIrIR#sKT z+fC+I#iH>T9Sa$iXoxMWE-n^J9F*9?N^A+SK2aB+-yVTq;=2l!kp|pgFT`4Fp|quT zFAV`bA~m2OJCDb7T5!q`-WN@7fkque6x z)rn#_ZVT#7yuB5jw1Z5v9edB}<2#*5w6><7XTTRrP!Zd~>h`3*<^|El=B8wt{7mvQ z$P`3lU90swlR}%D(aI)7j*?;k`f)r~3ExT7VUK1s+LChM=0vnT(b|jxiNV>M{4z14 z>vk5tv#_qIDz?Zmxz!Xw`6pvw6H!%HSp%iN3wL z1+~{Iu$~u**VWXvVqBO=`kxI_4Yf|RskJe!tWjoFEs1zER_r@DOk!61&RG>(0Jnr_ zZO_V8ogK@a*2OKTj8#Y+YOfPt7)#I1y1ICEWqT|dZ7+$yMJrodqqPoR2i{WUENqB1 z)wI?ojkT4HjTzfSd3&-{JC-l+HW`N6k`$)05z=J6iPj>YRB`%Og7_jdBJIr!V)5#R z=7s%Zk2lpM+j6*RWn(HpLvyqq*D9l}bqmt6pJkMQFC<%U(g4UCY>1b$9k)5RNFCP{Ar&syD7O^n0_ zOEpcYn&g{OTWhl$NlE87GmRVe{B4@^I5Z$<&M zqm39?BW!4lhiaP4SO|p>i!X>(mCR0RPHz+aX5H$ww^yU0HOCjXS2t89YMu4%m|HsR z!!Z$jX(BwcbTm7wbwR^=$NZbmMy4?qETiX2PL~w4jNgLo2wBE zyfW1tnt`Ed^`p_|_FA;uj;*p90G6iJFPmK`LZmO*yeAvT_1){%cXs!#?(9jc^3hmB zLt8^-99>pTT>=dNozm7En|-W^rZ+*|_C2wLIpm;?X+n7QuuYsg=~j6RW?OqP7fAo>~IW`C6k5mXnRY%+Vlo?C}g|}b!b^vZ?XhRo!X|BNNaPd zg|}^#&C9egrzt%w{A}pzZC~55F{$KW)j2Z^HA8Y{jA_7OVK>$_?T{jA-yVli$z~9V zL#tOG^9zH$jOi`Wx%%A^>Lp{C)3=#T%cZJj)1|jBXl`i5%p|SGv{uGj{eeLO^|-;G z-puqB`F$A+l;biC+R?$MRlweja91vUb#`~79f~1m)LhN>@25?(OfLJqzww2t1rhjL zF*6G@)|4fjJ+L=Ki`&_|AvJAOf7pmF4!slGbyJAd@Vi7Uvci^2n&U!sa~p<{=%bpd z8|tFyU@#~*S!9|L)DV+@$$NdLi^rld46*E>JFRk|sYVtj2P_zQ#41}c=Z;lkOwX8- zMW5wcqs7pYYdIHZ~%5&Faip zuegu*ukKp0E}1}%{>-ovlbJY-ZDFA%D+)5a7mLb0?HmXqQiL`$K$yaDRTSd@GnQm) zh_eXXAT=2>lOW$@_#+0`jkugltd=JlDi?G5ENg3;+6tp{<`i=6zNn;-tM|pTOJ^2N z?(W3uK~LwD!f9)lt=~|wY+ZM6=f-JkXUu@0ch!cqOTiUu)^+qw!_t2R=DN!%K*$yA zk2z>s&-!W0OAdylqkGw^3OoxqX7;qTMQiai;eh2m>knA5zHr*g!fDN=h10OQQLzjL zOk1%Qi>DncJEyJb>{{8os-hSozd@hIdW*9a8@iVDu3pzQtq05SU=L)=J9;~k=O!C* zyK%3X{?OMZ-wcWTQJU$R%&J3Ea~rx=e-PNG#5lZcgV!Z<59=A4EoiWYfp7z^TIIFEu=~Hk+;mjTe^HyO!I*RdP6t z_B_=Fv7bwJpN;4bBh8Bjo!X~elL)0Hcb_nsnMC%FWE4e`QM%! zBY*sb!t)z!u5>9M`m8f{buT|oK^vW(bt`(0#pA_9@4EF|1cFNxGovuAM14vvZ_*Ll zS9h((jMT0<8j&e^7T`htkZPqFlEHt?sLUS-MU$&=$oxbr?7|q)q{Eav6YeaiYUEl* z%Jj6XO6#mr&GMRcT`LQd14_)6(HAc3?Ov12;Iz9q7GQ5-24}Va(n`LqwFTa2yZcJi zsYax{(^NZ?%C2>(>c@2}49ons%U`;67zmLkWN%!8DxNRYqm=8qc8%0g8m8l{wK z_CiqI)46hOClX{W#h4pwC0OihFrB#_b|+oMtW>C*HEj!ea866nMPd<>@s^;CYi&z4 zIkgM1%#HOae>ur4rw*+0m~adf+6C6-ofte09GUg0`(_E&UvDg77nw{@D(kB%(`JZv zzSFniYAA^<;=&iQvB9ZLEv~bTG%N2|b>|ZLnpDyIqt3Rb$^~eBxRPh;vsti@VYU*B zI5CX;@qGg8=qbz0OaTiGSnf6r$(}Mf8QSz%oZ2@xu?H~CRLOt5T52rueTRh;*9vjG zxWrsB6O&Y}^SdxS3GFc5sXuzgT!HmwreERG$MAOfCuu^WrH&&RuH#|_2rrSs2$(%U ztCNVgM6o!{B@72^$_c-U*7}onxJ=)4`(EX*QK6ot&lRxr!D@QhAkDSzF@GwRKpA#7cD&R`IY7<4;_n*Dtk{Q>HyvscWsn zQpTb1Xn*uPqZF~gAgtOh!kx*6Cgwyc(ZSWAD>N;L`NP(ux^59F3|2hRM5SV2KiYrJ zW~R2OAjX+FR;fV?#cSF<+sDvXdyYnBOx>F75KZ4|+gFx_=~@$Q37B1#-U)SJpkrEGEQhR? z<+aAZc61vs%hdYy8?eb>O~-NVB^%O5R|!0Ks*Bc{!B|TrIun})e`IN@HVX)kiW>P0 z%pX>;Q#CDUtzADl$XI7a@2Pr#7SzuD{H8Xk-8S}Wqy1HOIJmzM!iB5qcvGWX(9Cl6 zEC|VoRn=hBl4_V!^Pq+8ZFs5$bI~W70z|*Qe07iUCru;a;TW$lJ2AvyN1}j@sG=Ks zy4yMOHq#fH&h8OoAm7cCw$p_Y98)B{$U#1*a<0$HNn&xrI1)#askIzdp4zquA5*5( z`h%su>#24mimc(ICi9>&#^^BPY^!c+j95=fjoNxT*O(ID(2E@*N$sqZm61ep)fdjM z)|%ddu*r~Sd617q6ASB5>#YTNC}JjjJ*zOVE@T4qBo)PtmYmbQKD~=+y!ti498A)E zZ8z)0@q8xPKbg`tD-20nDieJ6%l6DKgH(mI4g`g54gM0Q84a^!&2tB%4SAGSE!p7M zi3=)z6`$3Z_8A$9)(7dJIq`*Ua1L7yRF!KnpY~l}3nR$@)(}od*c2q7)YL}fIU0nf z4_xu!wl0bu215ydT?EgE6RGC~2`n08bzV#EHuwFf5J*ef7PJ3b`@5<-mu`TQ%hc33 zgNw9$kThUkz;Daj;MT90xBm0-RIi1RB|MN`VKStb^$-H-W81f^C%x^nS=rXYD$KQe zE^PZ_XAN@G9;zi9%4l`ee|(s<$$ysaFZ-$2MAqTi8y=6cBe&hi()4GmeEX1{b)=f| z)Ks=A_6?I+CVerqCKC=#O1D4OTD7u$*@kZB0V3d|Dr+dKnq3pJlRi4IS<*^dxk^1P z$F_>()AELrrdUlgMtQ4Q<*m-N{SUTgaaG+s#$+p!szPkUX}iA^KA#z*qA{ZoOvLHJ z7}K|}SktjmYre@{6HdZB$4PaJ$tU`#s;FJoo&nDz?edhrYGHN)a6-GFstN|}G0`eD ztI@1AYt74FC91_EbF)gs%qul>BO5raD>gHk^c1dGy<%OTtV4#FDI{%nB8^&b^dAF5 zGrLpyA(}g8DuiYd9;Pa6Fdlqg$%%)Q$&6SC%*UKP)MQ1hdB0zRN)H4pfy)~xe5 zZJ1l8jk)?v-QY+lOu4fE{5j_M>m1e^Q;y4*t^cN`sJgBJt97Q54XFKzL=+2}4GkOt zB+XBDwWip)JwWBa1rWCCt?{}>Ziui;CMBuWlM;WlZsxqH>!}ABC8;MFB?qMf9Gp6w zWiot*KNCpCFef$MFhi0iZud#Gr)Ce1H4`4jKHm&eV(FDXeSl`mie3033q8BvnTKIKnojoW)|qz;y!ozVD;lImLB8I-6Ndcl>3DR8yVI_|jA%mX@TX zrK!VIDVC;6u{2eRr3a@9$t=THa#9Cs$Xobev3{O&6x) znDbU)4wJUU#a?7B)(SG)2I@|3r-|31PSsU$FNaxl#vqR^H#QnL*kQYVO=oYXa+;;A zEmUx6&dkk#%|7C%Ox4ED3jARj2C>>Sg1r&kJm)8FPwi4$Q+-qO!X|%Qhq{|o;s?LMvsXSwOEuqVEnA;wJ9sMEmG0VRQ7PF>r)?mKu@I0%PWOD}+#b_t9>Z8) zNewIeE?4?K#yus~Xv6H-D7L7M&x30*f=Vr`rZ&oya-$6PSaha_rKUYZRW=g^=3X2b zwx@P6?WtSp!LQx7_doBv9#}t{>pBhb-8HiELPHmm0TQdp`~O^;Ds$teW3i*XXewql0AOr+YJR?n?ktItNq zQLuVKZV$!tfClU|}(-fm5wI@__6~<+Tpex}47`3;X;f0OZCdSV>D&_hrQp>~HrYW`qWppn_ z*U~h*QxgSjp0qpotZupm9aqa0*dm6^^yfwCvj<~#)qL|*BYj6tawv^8%5FUR_IHw+ zzPnE+#$|bSV%$bzRT*9 zR#!9t;E39v2=2i-{6~@6b*%Y+S}?N!w-D=#+%M3qt)IyRrwv5t^e73l*)*9Lf1e45 z?AGCs)p7J_vbTHfvF-iGwe(JIO|adB-JW0zE7DNeRFCEI7#^m{i|r-miVcqWK9*#v z%u2u6@ki@SRl!uc4$B)+tOFzsHO*q*RcX3V+VDc77{^~x=rgu8T^&ZZ>#=6l)9cs- z*(V{$O)YAt#vmo7_VHXYE4Y@*ThpI1q~>#GjKJ2XCapiB-=a-uLyp;GFYtGaYC{#G z_8-tV3+queZ9ZWvgRaki(Bwa=PMfLvoh3KR)yBEe(r>W*y|GpSTW>7T_=}5HXsQRM z{>AOABUQEj#)RblUK>m!0Y0(e0Mjos^9-0-%%LO}UKS?XBKu$qyXV;{qzz$HwatlE zah(RGni@$bo7`%yv(?18>ARo1V6T2^J&|>egFM@+nkEG+-YqRy`by@U&5meg6m#L~ zcC&hx>Nu0(u)b0k;o}t>r*`uCb;Pt*Hb4BzCDZz}7fdkQi)Cvt@k{lQXqSD*T-Jpd zFE;F;*Krcui)_YhW;mW!gH zId*2(XH$-`3PFA~HZrvEwCvLdoso5> zdsgP=;MoY1aahjtPe1kK6OTXk=ujtucX$-0-NUcZRt_C@dgd9yGa0t?d4$6YB}S)( z;a6oMO2C0B-4*qoTTdYoCIu700(;ADg(A4B)4Ik9#1#`0VG7ADD0;7VX17iYX1LFeY z1AApm2oxcY`hU_zna)RFr(X~9JB(?cpuU)FMR*grJv0pB>x=vnbn27(3NvLveA&3~ z^(^y+>BE!J;Jb}!pCG=Q*f)H(3BN5FhTmOGeS&yVY2WZUsf#!Y!n68bAKdTy(0~}uV_%pMg^(qhLSCkflsjKXFzM$Xvk^Rn3>UVxozw?`M&iGhg^WYDB zJB0l(KE5@>et7;Ddjj(Oi+<;WsZ1YU->2XCtbXT>{mzf*cfP*g`6>O*FYR}JN5Au@ z`-#LHm*?wqmdX?gNp8wr{6NKk{Eii9kTa}0UP}c8yW54r`e&@aY&dz@%Ph((=?GpwAr1j;1+;)B@^&2?3Xm)5CFS%azvtGIs6# zWv1Uw7a|fPOHSF$K-p{_QZOysX#~?pXs1Dagm!^1sga``f6s@)rRFwiW~YSdHm0Oz z8YBf=SnwZTCnHIIr86yv|CFbXaoFPLk3RcJ&6hgOW~)72FyHnxvxt8C{1iB4CG))R zwyJ^4E(6v(lZog%9+dL*nUxjU8Ah5b_{HQu0Z=ezQ)=>WCgc=xNmn6KOF!wFjYHwd zY|^guwVd>TdQ{U-#BG%3);^E^(*xPbQ8I#MX^*OsLf`y>8)~E}mFfJph=l$KN zAegCUn%nQ8FzP3J^PCC(duMVc`Y%(;!9a+0JqNEy<4b6Aa59(N-ye77OmUn-o=^4L zsGI}v?rolP7Ve_XX^TSByPHd#H%K+CQI?UTyh3pBupam zC&+{GmTMC6zD^=u_Bo7qCy97>lZbaR8ZO2gA@Q~zj$1Nd)DjY7vgKr%|Kg*)4)Wg% z$NQnu=!XeLKY|$j^GLiiCr(yC4~ckIk%(tKiFh`WNarRJ>D){r+yx}kc^QdxUP~g9 zpOAP7&mH8q9p_gh()|#LbZ-M`H`7hKp9N{}U|z3Oc}4tptMTW6*w*I6{I`_nRI6NS zRBo`pme*mw35WB&be=;Z{sIz-g)2CF)ypqnUmnkKJqyej?Z=;iAeUbS}{WpmZi?4`(7yluCCVnLb z0{;E{?EvZ-BIb)@#J$CR#RJ3=kz*I$Um-?C{`>&t%_4t_j^~Go9pXxHt=Jx zA@UatsOLhFV;!FVNW4M3MZ8_STf9$vSbS1^PW+w7-#nn+KZ$=8-xEI)|0(`U%*^ob z3yB;nQO_8$P~2ZE5)Tr?VpN-;94d|wIrgHSiQ-g|V=&5Ri~Mm2o>z;F zVyk$VxKvy%t{0CLPZG}%&k-*YuMn>jegra<>K|?ts;LUfcHNjJ|X^Ad{ul)+#!AWtQ^ZoS zT&xls#RX!!xJu-k@sHx)M81)p@$C}%+r>Q3 z5%b0I;=W>$I7^%>&J%AF9~A#>uV?%ESBS@o_lOyI0UqN&Q@m9CiMUmKMtn_tU(Ck9 zg7=RQr-^mq0+GK+%Wx-)7l_x1cZ$!8uZf?Cxgr04z9^V_W{NR!fw)rKD4s1|A>Jz9 zFTN`NRs5GY1_Ln0v!8f~ST8OUj~2ft{#txZd{=aa`1?KqPZF;c?-!pI-x5C-gBYkX-wMQHu|jMUSBS@oo5jn;pNjX1&x-Gg zpNT^-U}k)KiPOco;(T$b*dv}UUMv1wd|Z54d`H|RdU!K7;~Og;Acn<8@d)vF@htHg z@ec7}@dfd1@l(;oM1k>*6!#Zri+r&vuXl*YiQf~i6n`c@AU-etN!%$0Fu|a{Jh4bD z7Zc)gaf5iKc)fVL_@wx%_;>M35x+ZN;u|kc6YInUVwZTb$e+EZo!5zXijRsfihmV9 z7YE^$u)J@yI7N(!aq&p;1o0g4N8)YbgW@*vE%9S9h&deN+gm(PtPhtX7O_I zr{aC$v*I7cFT^ZN3>n{E;&gGYIA2^U_K2s87mGKEzZ8EbzA5e!y|I3LW5ol+u-GUb zA+8hotFg56LhVe=a^PzASz%4ufv$KTw<_&KH-8CyCz|?-CyuUl!jHcZnVr8mND) zcz{?Vwu)=S&Em!4&&A)0Z;Bs@8F-vR{depE(Rv}@#Kj` zV!42Bf%r3VtGHeKv-pXKAC@uYJVM-0 zoF&$Z%f+L`v&AdKTgCgu=fpR}FU3Lo`tj{87K;tyV)1B^zk^6Wyjr|fd{lf<{Hyr6 zn75ze5od|D;$m@wc&d1Xc&m87_?-BL_zy9(zaP(Nu~@7WDZc&!abNLZu|`}Zt`?6MFA;AL{~&%S z?iMFc_2W5I{DJtGxLX`{fFEv>SS7~AC1RI&s(68Tqj;zIg!l*XLy>FL%-2G(UOYy8 zRQ!{;Qw&V=@5>WsiY?-I#0}zw;??3k;*;X5;@`zD#gRpRJQGE{?bO)2P+Ts4S3Fm| zTD)C+NZc;|S^PxIoUVKjr-?DKL+ldI6t5R=7oQYg6yF!W6!VMycn%jgif4#F5`QW_ zB5o7^E@Icd$%iKKFtJD6Bwi-oBt9r+m-_dQ5vPjZ5swqk6t5O<7atP0iyw$zig`19 z{S(EQxIo+}{!qM5+$ugJz9zmeX3zBXju5Ab_z@$MA4|le#f!w-#rwq<#lMQ5i-Qi5 z-D0s=D=rp~6i*P(5q~7!CO#;>CcY~=2mA317bl1_#452(Tp=DSZWb>W?-m~s{~&%Y z250&4jT2{yRpQ~|M)3^sN8)YbgW@*veenx%_-sF(3E~W~N^BEXh{uW-iPwt15}y|T zAigK=7KhC7zGF5_`o{#LLCI z#YePnc zpZKi!uK1Zasd~vDRBc3l_CEg`IF1{sxC}z#|^^X!~h;zk7;%e~>@dx64 z;&2B~ zuXv95Bk?xzLGd;5UD1gtJ>mp$hFB#o5!Z^Bh%bt7iC>6(M$dd2C(aV9#KXn4;z{E9 z;TjJ#*e2!+*dqUtPz)q>&4CD<>KAqBjOk0kXoff#M{qIx{edKh;NJI z>ip|d#987p@o4d6@m%pb@d5F7;=jdl^L)L>h!={Nh*yhui1i;sv;i!X`qh#!cb zh+m3X^?tmgMedzoxlR(NiX~!&*ete*hl{JkIa47V%f&W8!x44e>p3 zmzdSy+dED?K&%%J6OR&45HA+56K@kA7M~Yi6W_Cjkr-f zL%c}5PP|=wK>UsPd+{CdGx3Qg->z51zlooU8O{FnQQ{OaEJnm7;u`TJ@dEKG@fPtO z@lkP`_(ySv_)jsj#kXU)I8~e_R*Cb)BgCV`jp8}t^Wt0LhvHXa_Iy9S5#j`~SZoj% ziN}j)ir0y^i@zlE9p?pd41TLxd`;Ki(fNDgPRV!coEx!tpG!i|-eRSgAW{Fi#1q8L z;>F?(;_YOv<2*w`@AKmCbp1~{e_MQ4@=tZXOZ=DQUc%QiM9d>$&t5v8AeM*+iHDG| zBT9~Q9DH-g*t1CN5Ie;#v0FSrJXt)Qgq|Oe(0i%)6J7tAc(=G!d_;Ug{H^#q@pbV{ z@vkKG=d}8qARa8v6Tc(&lE{zml0#q@iG06OyjItLrt>?*hsDRm7sXe_Ka$Y5Tg-3s z;~7il;JGk~cxH=HMN*NgXyFN-_HoJGFAN#emI{G);#t3I&Emu2YvN~O&Y{vP&KBe18u3i=TJbLN zaT58njdUGn2RX)ZJ`_LE^?&O;<1qjFAQJcG>3pO(PV)V9K2@AfLVr|j5SNI(;)&u9 z$l;FjV-oh}xID{OB=g&GHEACC=zAAAEIl^&z zbp2RylX$v#Hi>XIh){6;uGR;#ovjqi*JhWitme`in~PTJHGx*aj-Z{94(F) zCyA5A67eAM5HTXwi_PL9@o;guxJq0v_KM#XH;HG9=ZcqzSBN)=H;Z?OcZm;(4~x%; z&x@~!uZe#V-xYU?pNhLh=LkO^v&F&U2yu)!LEKNAF3u3c;#{##Y!tH{#FMXm&mjJp z^HJhn;skMuI8DSf)r7}%$q>UyLkt%TSBY!H9`RW5LK6M!#o|@swc^dT^HJ>qlX zcJWp5b@6ZF4)G)LGch;d$8YvU!;Y~!-%I3vd)jxPI72l1q9LEJbF=>$=Vm`XX!hfS zN9uZ)xIr}gpK<+sonItgAzm$R5zYQ)gg5(|!N(e~bKyMW)9S z`Q0v_oBhh5*{=+iN^bTm<9x2pYs7l7Q(P^s7tKCp+;@`B%|2zEn|;dQxsvm{UX1@% z@lNp`@d457PewSiKN);haZ;S7UABrD~!?TcH9FGvki)P<1U@9k0I^g&Sga#4j%pNJ#YN&#;yUpd@p$n9@rUA-;x*#k;#Tn? z@iFmL@pbV7@gp%C9WuvjgT;Jtl(?5TL7XB^6Qg2{*d)e9WUG^b&V3k(d>c(7?m`mv zZZe7XrI9u|u;C&S@f%{T=7DceuPYuY=+7sWB- zdzC~y)9HUm-ymG0UgI~=XZ!;97f>GtM<$)P=RlpCbm5*QIydn{@98?fs^om82(#*c~F+F zkKa(9apl<=@u=ZoG&FQCaFeZw-kTJBc0ROE% zet*^8LmgR5{V^+#`LWmdeO7x+`Q0nfr?3F@vDX&jAUz$K$f%v@2N*Bs(l%bs2kkvn zF=n0PEaHJa_S%Ym`aa#^_r27I<)@^+6Z`2q8u~U`WuVo^`DVI(;rATpAzY_Ewkg&= z&PVM%5IcW|zVnd|`?1&fJ>7JDyP$+B+QQ@-%_fhc3QPxcgz>HhU4*?BVno za|+WxC9{eTo?TozyR^6vZ?7sYN&9>7!837IGNW|nY~HaX=j2#Jbs%6hQRn2OUK+UT z8gtF{`-aKRE%?^{@cJ3Mh816VXT|}U+XGYbw`EMp**1KOGjVkF`kK(Z!S#X3qaVz# z=2_0XoV2s-d0yI?^C0yXI^NvEVZ-Mh2p$Md1}B4F{RO)U3uo-gGw}qrIfd(M#%^`% zM{nMA=lYsV(bs_-o$KJ9z+`uOa9;lAEANbcx~V6B6Q1KgNO@mf&bIY6fvLNRq>3igQRP&(PcIJXH1iyo`Jf{ zwiv5-&P{60nD;rGWn(w*3k|TnG#OjK#6}Isp`HGjx%YpJFYt}=4YbkE+dFs7ExGc} zG12RH%^hyaK{o#9@Dq0g0=i?5;ZuHanf$@=o z&d`Iw`po)QzjxX9XtlM0Wt`tfx4SJcr2us>ciZAE@a)O|M4imT`H*eSl+U+&^?x{Z zeT`Rt1^y1Izv8s@HCgpz@i$oihtuA92e#n&|AX!g)IAn|2i1=~*62RQ=suRZ|A6BG zx|4N!yzCsbeP~^7ePHV72Se3zkY+dZM#v3d?`d3 z+4f`D-D4V10&mXTwU@K$&Wy?XA-3_zl|kDJ>I!Oq{ZSxy@Pp@6pI$xa&8N2xuggo5 z+`r2i7Tl5HeDBT)JA%Pr^k=)A;$aWu)P>T*y#J0YFl`vyE!x5OX$RXc+F{Bmnci_~ zE8S#z$5gv-p0agF-4K(uG1Vc{ayf|*S}sp19#j3v|3O^LTlz%bxX$hq*Theq1luP+ zHnhyh-!au6+t`@5-;l1^ce~Z}?yvv(@2@kfCs&gb*_I|&ZJD?;*R&NAH%;6;ZqV-S z6aCgWF>%xE2N>JLO`pBfH(&lcTQ~h5+B)p6ar6UcW?GN6A97}|ZCkfE`&enlw(so9 ztVi#KRLouG=ZZ7+(`}*6lwW!0*l3O|6ZCCks{i~>cAejsjj4Y9ok4Zkre7OV{qj5X zN$UqT|Exdkyn9gfX?M_?ktWZAn;ZAK^3K4t%<7--$|@fB`v>sX<{u?Izw%C-lm1zB zM^*-|720dTJ9a)W+h}tpzp>qDKshi4)bP?fBm1;#`@kxu z@UzYN!Ou=fq}MjG$h)M5F6=B%)W|+1K|!vfgOw8RKDm6Ks4S;~do|zDbC04C2e)o>!k==cl9j(@l}F zD8VgzOr^c*)#vmJkCblm+nHqCN+aVnZG5tRvyIQ&8mu34CR;%Mr7y6(X5W$1$3}*o zx;1NF{(0;pha)V;0LkP3d|zN<*_Nz%+s+Gq8Tcp=J^Rk>jE|!LlShn;aSj{@%-a%} zFsSy?^D=NByb3+-!?-grAz1rqzk3JT>c=_kd>iNRv;KGD44$8gGk`ny6ldQyf%!A+ z?nAc*CJt@Lt(~-McwxlEJsjz+JZsnk%{wtEoH(e~n-};fXK>-J@o&6o+{t?6Y>GZEJNM84k`d?p^yzU?MzkX=)x_^|q z{>^qDZtkJo{t@p<`Pes=`{B$hlslOo{+r`DA{mc=^xwsEgyJF73% zk2KcEh5>DGx<9T-+U+0xcXqFl-DJAm-;|$S3QwkoM{73NZ~soc1HJY`cGjD@4gEPR z%eZ5G&C)HWYzfr|->VF8l&H~xu1(pJWv+bmj$8K+{Qp4hc^A^$g*vkYT(ZYLA+lvq zQfCz7LH53xM)Fxd9YY4RQIW0QywY96F+#zeJri(*@&5n`(@7g>%bwa`8$U*)W+qMx zg2n>$O1xKT=-bD$jhwgj_gnMl-MMRtv0zir^*CBzQ@J&FfGm`>YLl_^&3Cf(C~8fj=spvc)x5 z|M5;HNT;k@L%)(^PG5;S-Fe(=rr_KnwH_t|s2X0F{Q4+@cY zXFH)Pjtw)-(HBbZd9d|7*xI))`)x*G>Q~!MzaKC&^W?ZIFnQ4SOn6@gRz9!-g|&~2 z5|px8g9=Q})-}wNq8y*=D&o0dwZGPgzkwIA=r{N|td720h(+JD)x?ZI)-ap~FT)d! zi~~l`M%~B=WKS9lWVk2qjVl-85n;xhF=kg)#-OvYnwpX6J~kd#{xlZH&12T^p3Ff3 ztTkt3yV+RM&Bz|~8df_qGhP0oCa&Fw$A`gB@lYZ-I{!cfchAS4tSj*+cm$qE1}7C% zQ_3e0SzGvrN5Q*_@Ta(7369-|@F(k8{29~$dj@50#$jgtP(B;Y#;h8DUxBfK?CQ~s z9_LOldoj|RnVok4ZqNSP1l*t95yHLMw_@!vJNr?X<7F2hd`|W`&=AUAJCP5+Gx5lC zNcOpSLNPRZ5{%8w{ysDe%Pv94;n|ns$wXfE5adFBb^*c^Wb-vYBeEYu$dTE51z(02cy)&Tmy`c9wmb2dvdXsVA2SM*nWX6X0Jw}n=-u{9mi?T^xn+Iv%X9(g4~^->9rxgc&5jf;3P7=`;mrL2ysJO zrpFx`3o<>v{B~iccO7&t%Ji;*2QSX_zCuPGn(6UnQHN!Ed}rw4nch=K${m>=-xOHj zdLK-I2e_VxoY?4k+mWK%BR`asKFfFQbg#aJ?~5{U_HOHqmk3 zbiGM1@GaLn5LxhN*Lw-JY#Zc#gle>XkT(T7Ul`=IBHG^#^1?9p#X;WZNZ(6?yyFq% zWt<^HUK!;55_$IOAn)5q^zU&4+~`*!uNq#zHRMfztKS>)-iO!T7xKP01bYB-y`RCP z>vFwIQ0~{~det!LhFou-eI4h-`upY|i(-1Iy0N_a+TRZP?#C z23m&i@4X2pT0hD=a-`!NJ<3D2INhVXc0}7V%6khTdq;V{N9-F$d6g)}V@7%3MhwS} z@~(x)ZXD&6A(xID<(+{{K7N$9H%vNVly^H+e|MC36w+|wDDOaI@=2q-LCB?(M|me9 z$fi-=pP=lNQQjReY3^0t(TKM4DsKe}HFA~r2wbu1Dz6#d6T8a09!^_*l~;%ythvg& z8->&IsCO=|&41K;8akKk@D{-%J9ccyKCml0Scu z(~N@2G?$P-mj~a1vuE+(aFoO#9=w3&D4PerMIL)R;7++59{dCcAs%eOU4waW2x|Bc z9^~!MH!R~|8Ok@82iMcFc(4t1W;hSV!aMSKun>8e&x60f&kA^O4hne$53WVpX?4!x zLZ$)-Z^QTu9{dXJ9DlSUXAPQ%Odg=}BNaHf8^xN%18#O=sGI|lbpamy2Dy>JgKn6? z`<&2jxLIabAow!Q2XDup6%Y*Bj060p#{wL?6qqZU?3D~BYdx<}@Qr_lX1LF|-Zliu z{VU>kpL54=fz}MXqB8eg80$W71@Piw8SWFV`w0RMk2&sB?q~)b9&2CfxZB*&4Ujv~ z_loP~B2Bpsg}D9qx*a~m+kfY}rMNb{$#GxO?M=M>4{nHRouTO1U9S#7@@SKjM@<<{ zs0UTTeccW6W|x-{&pWQS8Ara|JFJ=3?)R<0xBG3^y%m9J_g~ZP{)Zbn407uG-1VNM zK4bT;zIK1?x;uC~?EW;}?ti%sQ4{Q*IT`kT?FM*R79qr24#20OXmM@!@0YXu=EH(Ut8eO8d;fkcJH?W&&iFT0djwB z1<3R;JluWA3Q+4%+FRzhZ20rnF&BO@$GA)Wr>GO|BXdG0z&4us^c?RH1j_v`nj-f% zQjm$t4h4_TahFlS>1epzC#B#<465Ac=Y*)53SOGyaU_*{1=<()l{w??fjA>$sFT~m zXkV2eFvQ8_{&x2dR)A!^fJ*4TZUsozqx7>ktPUuG5!>gu@6w3dP#fLf%^5}g`Ftgf z`{y|!nnxr4KF7;MtC+h0?Wp^n)rg7=1%I96PQkVOTj0^|J5s=Rak?MO2~jl_d^*Q_ zjtck=CHHeF2*T*E(eJyvY{sH+ZiH6%3oAe>ennfpv;w3eQ3%0TR*>!F&M$#rw-unY zo*NlmeP3Gv+8`uk=N$KACghiB1Kp2R9JkUFvdThCA`>#S z%o~c*%YAtgS?d?%rjE ztTFlDqt6zW6<&!G#89LbQf)K3C@bk#QbPKip;&pe_FwE7W!?KwJJe#>MUnR)Dtr zT+?$|0o-VB3|ZY5tpIs-7aN0@tN`B5uPC@LTLJ98hdN%d0^jbZ%iIj~PWd;pQvF7D z-+LfVUM&kTMYQ`*W!}XIl8S5+4ypABAh>$FYtBuvI}}jwgRN=xNHattpF)|nEAbr6(D7N8M-^c z3XrnZjBKJ6AZ7eH2zQbdAZ3G?8T(oRQr1o#`&j`}_A<+Te=G1)HoDxch0*z^6yw@h zrR-mfY)W~EX=cib%e_mPvfJp5Gs@L1!79F!*_~-M!m6Ff3-=%^fK?Z=Z=7WX=nUZ} z2bR0{GtLq08;ca@p9*m@r#wV!80Xw_?+}z`?s$ym-H26y-29N~j9LM5^V=-Jm=z%N zenLN~mLLOGMbH|!wN`*eY8LC>JbMeOavqg7SOF}6nc;GG87#=Jp}Iq4=BxD5#_|vo zKr>s*%_2^24b5Mmtl`M{5xUAks}WY!u#6Yk5XhQ5lz_X~<|Yd4QhMH@R=~y;qZjuu zD}ddVGaxwJ3edO)nZ4h!u^=H0jO7R`K%3Ofp+vhCpmF8Y)?H!+Xr#hL5Oi39pZ1n= zw;fG={vuYWxYB+m8~>%{A?6CxzPjAw`f={5bc>^`0u<5y^n$fk06+OVTZ=9$K#7cE zey_6vWX5oYINA!3cD~lz?Y07>eIy;B*9wr-liAR1umU7?AC}FrR)CbvrePbcz)x9c zxjP3&=bz46x>702Wvg&pd5CFd%1$ZwK4i+4vtc~VDnQC6v*w;|1#rG+CPHwA6`omU=WnwheT%e|)%DEC&%FSQDgvSaBdmstT)b}I|u zaw|Z}N~!k>D?rM2?hnD0R)CcKm?d(R6(D7wv&?>E1xVSEY?H3G0;G&@dv&j|0{T2_ z^R-ssr|iOV_XDPE(NtW!NGbap669WA9%7oAvRlf%>rtk;Ptav=wF;23;e`Syr0ctN_emI??=salD`izI?R&~YOfysVK)L6_!rULyaULx9rwJj{{^^Y3 zVXF}ie+mon5i7vmXvVgdyHjy@{+FqjoX?2-1U%iTgO-sacM z#I?Uj<6_qN_sTU}-+dMADtE7^f}^;&@ud{(paox-hp3tgvclf4sbB&tN_N;E4atIxu=_R@ zoKLUM4EuwQnUJ_%I7HP{Ff8ot1GgAiRTsyoMG6A&*r}}GBdh?qbTw@pX$9y6kV}KZ zZZ+=CZ=!n-RTPyaI2j!dF>*$+ci8JepxpP^s_!EOEXlLzw38%&c4{0Kb}yqw{#u;- zEotnf6YU!gF)nI6FzkiV1CMN}tHJ<43b<&-@7TN3t&MQMhv=szVU0LY?~Y)5QECM+ zVqaF~8TJ;Wvx$P4R)BhU8QbiGtpFWI0d>r_0#uu6^!hngsh^O^VYdS|<{v_JQTrmvsh}zB<)aqmK1s)F zNh$ElGj46P<=JWlNavZfWq}o-gKVK-p%tKc*ulsaOMv!@CNAcE3lBA5h5>X`DhgJt`bxTuf(o*!v|l zma!~)rGV|ra8`(o5(H5Eu(2!bzD|voalEl!8sA`{9Ul%cE^0g_>|I}IedshPpbr_B zIl~sFb(u4*z`D#?Hcsm@o2>xpJd81)Z3W0%emUO#o)sW(FP{X#IbpvohTXYYOxbxh z1jbpptoIk#5Z22sv;r1Ko_k{0eG;k2ub{e%~xy}ku1`F9nUT+2H{${d4 zy}=6Le0;aOd!rQ~Prqid-DCyG!hcig%{G&fg}1W{{fQMI`%ti#huynjWB$Et9IjNs z9>ah?4TqQ<7VIy=-gYMBCRY8sZ4|Hw3T_X(pHsm+Hc?xoU@$A+FT)|Krh$Zs4(se5}+^3y_`+r?VYAkpAHYD-{YyB+n3?wX!`>3c`3l|nAAK|L-LQKG z6}+2=Yde&A@1tvRKMIGanhJJ>z3ZrezZc_vWfd@Mu*?y5pP+&d_rtZ%rJ$OVoPUKw zR80kLg|`^hBlk1r?VyU(iop+PQnnSqv**w)JS%`_-$KvMu>yGZHabHL;YUFdQP2(lND+zL6L0-GxvLRrmnJezCI5XjB{8F#Gk3wXk4||Elw6DFz&&?4P zZUIK%`DZiLqh!@#Fvi`#B1C&>RZ)dki9os6(TI{Xjk}o6QmZj&%4ceYyMh|eIS|(l zl*ZkxDl;oWjEfq}E4+)SF`vDBg;jubhG^p<6@KTi#X%IA60kUBTORLewiDvlzLI_%{0O}BDw8A|Q>heEf zvldgFUoy|*6(L%~rwWHvctk9At$kyB(WT*R(wF(Kjio@84tpEwxzz~mG0UYgIX3%3+ z07o0fGI+uY;AjO5@szcS`OOl1+6s`eo7mm{#tM+K`(eBLtQ8<-SFxTwZv}qJwpO@z zKvVu8l!kksQg#hnjBOPmrWqRtGu_+gco(6m$>Y`mCy#lUk;ljDnR$G^ot4Lj)Y%22 zXmoa2{yhkklgH=1gA2yeSqpsG&;pDDG5IOW-;NN&^7x#!Ade3;N9Xa$;rKj03oOjz zv$qKahcfJGe%MKQd^R>YkB^?F=J8?Bfq8t^Qk3^c{4LJovxL%uHpca#AJ@!0uG1f! z$2INQd0hW3%i~&UIPVZt>O=Cl!)tCHm&qapr*edRLbd3&DEev{9Mg9ZGl{JCUY;l~-(X6lNwFfUio-x17I4=`z6^_j|nqOJr zjZT(XzNR2_DJ$a(6+zY<_Yp|YFfNUlU8erVn&pwyXvplNSz!gJm*GO(wbBYuFU>xh zRaW3RBWn}bk+j+hFw8I;YmT&nL8fs%BH|v2=E&bivn1j-*JdBhnn>tH7)7gkBHoz@ ztgeKZ>*A*!Z=lOtZJ2nx(Tno}bF@GH5G=2Qui`)E$L z0wl}qqdC(GFuybVXf|6N(2p+Sgos-V{r*0h6C-K+XwHd*XdaEYDB?BH2(ypoVyn@g zdYm6|kEViKkSp$mQegJcTp9^cH5FVP@kUIC0<(|iS}EW(*X*OY-exQc$LyoI!3vNH zvybLRD?lm|g^1|KR)E4W`)F>q0(7p=AX4`yR)ATm*++AW6<|7I_R;**3NlSjToG~0 zV57f}<|-A3*++9nB*Y{#A-{@v3z!hIkLF$}PE~ z{cXex<6<67!rpcqn(ZVHN8I^19>G+M;N1+nBQj(y4*gWU-#1l%i+Df4HGgx=yGqsG zxZC|lB$uj~s!tD7G<09m zw3N~%OBcFOAj!;RX|qm}E>K9@By9t28j_S2WD^0|K@=2Z5ph8fQGS3M3ZjT83MeX~ zY@)Kh;4Yx(@B2OX+-GYF=Q^2NUr`&N}0Nnt3Q)dZe5k6#@zuT zbM>dxmP)Sv%=VRPTB_ht@{+4RGYqeT$eofFr}AIGYmy>4NwSktjY`Gd!uvri#X(F> z6JC_c@5k!E+~z1xnU0dTIpoSur3ScHewNq(d%a_s2Dn##mRkz!<;azv6*juK1x-U%Ks&$k}E$oDbvrnSAH@Y;9mKuvsoZdx$;wQ15BQ) zQ!#$r!d&?|QuCB6KMkn_rD2|Jsr>UnWHiyP45$gY>(psE+Jdjw0QX+Y21|kUm0bDR zXanrMmSb#yRm~Q$EFf20LAP{<-bKSMK#;Ps_6@><^-FC zRn1NtVDj9Yij^)!o^s`9tL7v)x(%?ZIl~4RF$Yqy2Pvjp`59C(<;u^QsRRo^G2frcpR~-X=KQc~E()vW z5}Sop&80TLxvZ0A0zIpX+Uaz4G%h8vwcG%Fhipz{vfoTWpO2>!ED`1YOe+88!ytEz!_zI60ah|{<>yu#fH7FE{Cv&^U<{TkKeyQcjKP<2 zf%^p;fUWO6C!OE$oi?31b3!w}kB z3i`B`OfCg|IhA0US+Z}W@?U1jKEM_1HrD2|bPUW8mB6E}Eb;|$-Ava0humM=w%1x5L+5mKrG8O-u z2Dmp#{%!+M|8kSWN$WHm^)EL`a%=!3K;`^C6}y#U%1x3#s+e+@OKn$8vx6enrOl`)H%TU? z6VwXJJ~N$v+$xk^Zj#Kh3{XXKlVr9HK%14DBy(&4>_l#o9Bc!i47o{ihz&s5ey~onkn0D>r4!7YS@fp!f5I%} z`oVV1!o7ab7v#7l9s4Ue%JqY8<@hKV#g2#GmE(!&{E4f6D26Efrd}ScF4K7V5$eIkUOy|E$26EfrBS8k2r(;D& zfPvgL_>eM?+Xh#s6J$*WH>C3yf@rMVHn=g!;M#PojSS?r!S%{OZX0|uogiy6_-s1= zQoNee>D!cnd)wd(HUK@4+%~w~2AJOZrgZEMW+Ar?Zq_X1w!t0g1T$wAUrpyfi&t~@ z{556Z-Zr>b1F%@6aeXlziysM&a@*j`%293`d^4S3UgY@QbpDedGPeyLQU>mAgYR1z zu}c3F$Hj+j0D2oaOMb-mlIU&Z`oW_%0KLt@oMrsbCPBgF`oWKE0J@>xGVtJsqk)z|ES_*WmazWv78-Ru-7ZiSGlbEu9I~~h83T2lI3g6MP%LRoeFsPuw zEc>s}c0pwB7yL#!Vt#9C@OhgBiYoU-UbF$W24AuPD2QA*c-aP^AC(ISuh;;LA#&m1 zRSn27Vm^cRPch}f!7o)zxp44WI>7=^%s-?3Q_Q@XP|fSgfQ{`Ic3OYcfEbpY98J;w z$+2-f;{K={rwz zutT}Ru-Z~sJ3Pt;pcJ^mFf$Xo0HrWj7-nTA{j>xgxx!GLNifD4LseXjH@(7uqBmyp zA4h;WQE$;K-4pdz4RBA?+cZE=)ax^`x0t1zsISTRPSo2o3C1{MB)b~-L>*ZklgU36 z0p=k4I9p0=$ik%7XJXBWGY8olwYuaWdvhjHfEZTS_DufqWFQCG$6E#wVbGn4T}lRW zklm{cL-0?DyCJ*o+)xpJwX{79j`Or`rH@btw2iCRPWL%t7{`$}I=kXJ!&C5#>HFlm8{k zEeF{b*eoEo9Asap0q#NeMV7)&RWH#z-Gl7Ql)^p8{*X;#w0U+W_9Uf}gY0uvs$(Eb z?8;1n@=~g6Gx?*_kV+1+Kj!23I$Cw?2Fo!j<-95rD+jST$o{Bul!NRWGYRHJjyGrW zH<6PXL1HcZob$cfEC*~;!*>`B3a*+LvOoGxd&j&O4of+iG zP0iT%lmUB{W+*rIkPUzk`8?ZVtYZ$zNEDg3Ag1YniE>5_%{2zq0{o8ghdF zM;pK{AUF1WCf0`3<^=!6jPC^hFPQ{0XBL0Ytl3Ki3A>6a09s zCzYJwkFo)fN>1?eZGe&L%}nfhN+l=wf6Mqz@DsHO%1dP@Yx6hMK`J@HFRs;L19mGX z_y^eln1Gz%PqYE(HRJ?;vJHR`a)LjtR@bxWHRJ?;x($en9TwKcPD6&~1iz@(jF)nP zKeIMLc`4Q0+Wea-m7L(uvkV}WoZug70}6#>X>IIba+DMNIm%H^@E6o3n3pqgXC$_% zCckzKHh%dvD^8LJPB}@Q8s#Q=Y!grN>_v}v(`Q=`YjY$(M^ z?v_tVa(8)JlKaLbN$%6?@$lM|(9TJ6A9Y@m+m!Q@+&EmA4k~?J;N$xx8@$gqu zlK;{qcWe$za@%D^l6xnslH34Uo#d9pkx8!jtCC#%>hW-8TGFMHTs77vx%8_~a{aa@ z$wgRWlIx`AB-b{2JiO1O$R@d5=}2;ku`bDV!iFR#`$s1^W8akIr24odC&GF>{EKw) zT~OoJV!5FDWV-kZ@aZw}QzmX(l9R_BNzToVPjWuBGs!tnf0FZ-0dstu%INX192TcD zr5B8HkB2jv(sih?%goVnZKiYpzE31M^gm*bj5{;qPr_!>uO@M9#*r;YSRC2P(Q$uf zd=27oWXoX_N49c=d{)LD*>X_Aku6679NDt##*r=iTO8TS$?`WdQf)Z0WsleznZ!OR z8<{Kz&A-l!KL?U_L?*G`?j46Z!EQ39=r2)#3?Flw;v=cuD z?=c1>9-ED~MYT~{b8HVnrsT%n55N~q?S`pOyLwT{tXK=u4oK+aU4y@oyf2}D&&lgV2FRx&hGeHjV;~w;GuKUa zR^c&B_GB@WZNqvMUlXzujVgYAbTvso;*nllco9kY%U(`i7A4Hd+dE%)A4lFFj&5gy zMaWc(es$p&nc$YOOmO!h!uzI~ApKEB@q9tc=D#-j%FFZRXk&y=-dQ+pNoDI+-Bs)@6NvvoMs+334!;OQXP?; z+?<&^ron&z9F{W@iRP5_4W8)4ADl+nB9WY&nf!^j_(QWP@XK0qFwS-$}OpH64Bf|b}Mo&J!TwY9#4$p`|nU&@h6f}o@rANQ564D z(Vq~Lq>#?^Kg06kPfq0)H?f1;Ry)I%auAiayp9WM7Og0{cE%l5z`(mK;H4c7e$-VtsVg* zi04O=i{NpJzecj+NU{#T+~QnRZhUqmc>;WS#ceRucv&QQCVXRx?+4%bD&s3EzKivf zi6pN^TygQ*3GlU=xJkuP7V_vw@*c!ZD?SW8b9}3bD{&5P7=?iY5p$>W&piA=39o<- z;|!ghTL*#TrSeK~g`UD0deP79+$A=Kf|?jAYc8Ah+^>Qq7&TcMiZ3(>JkbVHZj+Fz zL(I80<_09^=MOiWKf(da;I;ir(R4qZ~6|DHm^aN)0pYE)7;mHr)c`!W8qnw><5G5 z=?kHvyv8I&oHTte^K31o=+mZGQph&(%$VOdfF7*yQbd$Yf0YsK5>YyRFBG2FA)YzY zPp79-JaebNi2f^YV*%65oBkEX94($hryofHj+sT(Eu4OC0-jCcsYpJKax8VCf2Xc$ zCVdgU*|}fC-vvL!pSkjf!p-F$L{T}ja`TRjy@}|BeFG4(Yr?e%EPWiUIB(0u3-J!R z+W?C`f_9RB?i8K~jbZxIHXX$xdd+;%FQE7Qt0#{^MA>2(TI4TUSRF~|z!r4kzaoSvvbr+5nxsenZf#X*}S~-AU=R(wc7J+8Q zXYrft`+EyTlMv>t(eSP|xxfgKbXL|TU0pbjNox^Y1GnT9bTObkj9Kl5+YVPg4gCND z>lhfxF1?HPdSu~ba`^&+J_83e@wIFUbRQ`;d12Osy!L@=nTT0jIEQ&fT1_s+g^S7X zHMr;D4BH8YZ6#Jmhr&5!=VCO7yiy>VGz=ef8NO05*U#{kf~6uh(rt$`3|}oUaw6a} z!f*nHx5)i|hEv+Dg!dN&B)q@CNQiXLy9^&N3@b6r9}4G`Eyws2Io~iu@lfP*!O+yq z`G(;MAlwdT3Vyy}dkq3EVxXw^{DKsPFT|8256%dGp~)+afK_l#*(b}uKV$ORAbI`X z%_~z-N^Njbb1t08D^pNGw)}b4TNo&LWeTbp$lp*s1kU7DXY%4VsBMIE%8rELMn;*u zh9$2fI;^5bSw)qL!HhB`inJM4`G(bJz~+;}YM87Z93z!zSe@sxdT@;D+^~9ZjOg65 z`ra6+K7PRC$HMBOBCxu_url`WGnds3V*>VY!x*uLf*8hdI3wGQhT&QS)WJDrO>C3Y}R-BC{9rLmzW=W#K;;^Qutbw)W4gZO(cmkox?>j?NQxs)BlI$LH+Fh}GlTyM+0 zEFqm^q}7yrSwgx+mizB4!8m`p({8G9!BpeiR25es$H>d0-Rd;uz5pprxnCYF)yX~a zGB{K2{}?Uhz6t>s!#QPRG0aB3%TrHVQ}?=ge|L01;_r^O5?6c%X(P9Kd6yt{My| zw<-5oNNLL5W6He_S*(FGd2cg$--&?FNZxO8F_-e^{UtZ=)aXO}7MdEpOf9sc@L;5x z9?tvkZr;;J%h*|nF%nl2H1C-v?_CJk0_Rlpb6CsqxRf9;a!q=p)n3l%L#Vy`K>QV# zORnL<%l6zHbt-;*2vWU}@7BNJa)Ha`g?!;sg9NMKj2>Rfm-;^&0jI(_6>s5h?UwAHG6TsX!qM7{))@xQp4q7bi9+{oU#k?C$ckNEV`cW*L(yVj8*N- zm%hMG8g}NdV$Gg{bc2$1$^_6a^QV2xO}i|Zc9}_gH`3i9X~!={+PCt2`4$~x^L;B% z`#jUBzLh6^-rte#&yx1yMM!&-No)GcS~u-Yc>!y@DbKaWPftXuOY=e&uoo#!E4(yM z>aMB~Gj=$qtd`ZZ(_~X5s=3w8W@p~Pexu)+x5ReKOKE6pOe!--zJ^q$O4j5_7jYKY zp8{u!wmIXo~*WOxOHzi~M{ zFiK>Y0Yy!svdU($C9-p^qVI2hv|KT2!R%*)1)k{Xg9B$>6@Vpl`CT#zmaNy+^+elE7ko$sqT-9RQ%rQS~w%s14gPZA>ej6Ppa==Y94veFV*vi ze-2Kh8jqnm2Dj=N(1}!g;X4ryPsQUENc{P@+aQNUGM3o1me0p!Nd7#?KMrTK_W8KX zu%=13z9$*olxYxC$*)_oBIBG=?@u@XKVlf}#fVE;`xBjM9A zSktC78YhCUy2gq-RmBY zA^rill~2O+54^kvx2lzu@e)E##H`~4I6P%_=1!uPD!0S z5EEtIjFi{F8L1vLQWZ{tFmNK3X;_r%dw!{oKs-OJAyW0>x z9EooK8Us$OL;j$! zslz=yRzaw(L-?IC{>FXe62D4rMFOLeOM)u7#HeHd+_$>fUS_g=3<3Ne8BZnOVM#9c zt0X!N^#dAFNjW^T;8r~YI;p4+!gnzop0f8Iio_@TrAl>MsZKU3u@!Z)QN}|^$S44g=HAzn^{TXhrYM5@=|dl3##**&bN%|@!T z5fHg%1`N#fGnZnHYc(*HkpC5XJRP@XNuNsidKh!YB;ZDY@kHF{-W(e{2-hZ?M}RW8gA79=%i?q zORzkH!&4EPgT(bQw;MIBgRRaKuRbQ-XcpvYI8(g(m~^9GN5JRdjC^a1eDh~v;|$JI zy@Myx=$G$8#J>+tqei> z^>w4q=4v-Ow-PD$f>632F(fN;2->o?^ z)4-Cx;@QQZd@B-C)gjxhs@{r-2@itfHaN2&`bR``^C$xDXI2##VcHRSJj`X6%jNNi z6lngzI6;FmT%Iso&PTv$a8B8&hk(nS5h(#`5GD8wIG7UL8PR#4=??CUh;E-ix}Qke zlVK{6%l&D8?WVmv5}0pZ9+COxKalRPlC~`uX^%B&jj4>;Ve>uKrgh3*WtX$skgXQ+ zmbhfABdTC0Gn5aqH>41T*#=P6%KYUGmBY!*9R;Fa3X!S&(?C@B3=8o~m(z*pK_mD2 z)bVkb)4jTT=w!Z2;Xmf%^ngqBF_}zY$31ffiQebq^omRLK3Aqg7Jz8C5W&=;{c#uw z>tvf`_e^Qctxo*{n0I7J$XqyLHb@DVNIfr{iz5%XHD8_w>Sbaq7s7uAoU@kwBOgNK z8jh=toPzL?R92nWSJA*p(wm;rK`*0ahSj_}Bs?htMYy1&J|<6`(4b z7@!&lsyvg3vLy?^jAY~esd3`u_c9)z!Y2I$e{wIAi4Y~`i84vJqA=KY5Z#DOD-bYc zEcAv81)k2(gN}z{q$E%wOEO(kiAI_E3@xd~&-BN8LX@a%lFSR9r3%o*rT)Yiv?&lv zHiwpS@IjG7CL1-+jY)wIafMSg&kIze1|Ev?P^*$P<}!XsSbzoO%c3px$KYfDr)aM2 z95s10X0T;tk)tMCr5!SPTqGH zbCepP;VlX9G(=1NM4E6}fEn^W3`8Dx1T3E(sT`k;e5oeUIdMZ`V{ARRqs}W)?3Dy% zv?>wlgdm46^@3KH!2*o=Q2ixh1xNTZ#1hOeC+2B>5iyNE|Evg_X{EG~>I=?_fcXb% zAXJTwz@Ww8oJkU#4hU~bopF_kY7A+`;nf@i>Vv66Re@V7o`I+$)@Tt7 zPb0(HGL#`uiH)KwmZp5OG=w#c;XKA0n;S^9>VLMi4jz zm-mNug%JeHq3wEj)r~AjF^T}GMGr=5KJH|1_J_*PdytD@lUCTe2vNQZ513cBdm5K_;#d;AXLGb6nv|J zLkfb;dnEPHxS$1s%`tmD-2Z~2MSTPYy8ObWF9tzwHm*<@5RL&W6O0TC9 zhXWz-xX(XJZxc?z3&bGU>Ti?kHwAAacp9~-h&BmQTOz#rDX{Eu*yOx2FpG2`1fKmK zpG?6P`!DqvWC6hlOixAIE+-_fC&&y*BO?GChA~XOtuhgWDmW9tw;ga84)FJYk58jj zAo5JH9zKXdSmQ?UtW5M;mxeN}>^l#c3vj zPy%Pl&NrjsR>BH50x$C9*cU~zXB`lW;h;1EHO^pS2^@k6^WYdvB<~Sa95=xP)~gW< zFY@?vKS0hUAY>LqG8iEXgv#?jO*Irc4-Q2ljDa)i;hV28C2j;>+-Ef2NQl&|p%U|o zzau_AcBD4>@a_Lmv$2KvpD6dgR;T{9z`CW;`|6lg&H7^SJJk38=Krs>sehmTX}kXu z?bbK2&qEQ|N0`aRLijKw5$fFtyzKYnA_@;1tJHTYZF0e(nHbvX@UWyT?P5*x_m$4aHjh3kP+GL(Yt3!Yr65+pAvJ;Ye&JYGtS6G8 zMydeDnp*MZe{#elwC_fI@_QHJo4kTG;>u&iH?oQNr1y*Om(aXZjVOrKCS@?AMU{yl zq~S~i-&j(lAauA9d>b|q_sv{cI!8nKM<%EX2b)np&qgmGcJC`HVO>Y$t^ zBBTyVY9hS6Ty?ywmTD!p>R?tQsDl})I+&AR9q`IC8h=q}!mzxqm*CK!5{YUfY=ASu z^X*tTR5F3dO$1&7&sg}dBSx@9S+55TkkZU3Cb0w#q7j%?#OWX$Ew9p_8i6|y5P0(7 zLps7maFl7JxssP=h9r=YosG^Ef^SBDZG>R4jSy{w9ybNww!uLk1e^Crn}_v6mL=F6 zv)A*DiTs;~uv+s_Mk-@2W*l(eFmLt3ht6 zk#9a5uXiK(_O4n8Il#mS@6bX>Lbm_L7V@^@o4np#3$e0|)I!D>nF(jZQE_iKtV|Pf zSt89>^0w>wR%Rjyt!@P0%)Gjdu-T2^8?*CuQSj-L24b`zSXNm%4l*goX}`y)L)JJp zO}nJo3Q|lK2u#lMwY#G<*)SWES_Uqr20df=MBSlk6?{}6(GYDSkf~p<=rS-N&qJtB zvrJ<&%Osm!A71+gq{1wTi;bthtrIPQj$$8(Y=>O$LGXnSvKcPq2CIw})o)Y73t<+PqA6 zWb$&G%)6eUFGb!|2$5OAJP0%#1{0YPf^CWX>N~&;oy<^h%LuPbZ1~Vf>_eL{Eg_yL710Y5M%EQA|bNXAk? zBB@4@1flXAFrz7mMmoX_IFk|I-nE)QE6N^0RqQeuOe9ZaM3|$&!~&SzolPog5C6%&Z4EWI7jI%A2v%qHlE!TAB#JUSLPCYwSJ3L8gKm< zsed?x1M1(WxKMFL2yJ<6xb<&VI_ob|e~F?kZ@v1%X!%+C1EHm}{K9^l?m+Qj{f5)q zbURc|Tb^{tAJ*Rnjc*On+4L4|JzD)vQ+kW)m0pc?PkKAh+mYAO5ZQy%u|2;NJ#Cx3 zDC1^0`!GCD-AM7Iqh45sdU|}1&Hq603_lW%vil!@x{>1lm2@lzyX{6eYv;_BDwx=`310i{bW09rLmAn~e8=`!m%;xIZeNd|1EXc$;pA z^0DElXixy-xX#-Mf0rx9sfQS6;SrclVZ^UEDP^yr-vcclq${-8;K?Z0YMCD&OAS-L++KS9xVc*OIQq6^kpo zDk~Vc2!V_GclY-$>fN%nZ&77M*^)(!E<-tt{rx_9*T_x^t^#?Z+_ zei63sD6byu+0)m*JGFbTcaf`$eZzyI5~GpU!QIFAb`KAgw-0O?JfU_^e^&>}vb}ZZ zo}sR6^+C^&a_vzmp2%# z|JMtHkHpx*k8F1owP&#Jq~1ZA0zOMCmf4N3Uh3M?-Q7DhRMt)V?ds{>wq?)G;jZD6 z2YQFfc5tYHJ@)kV55oh4hh=wl@7}d*cYhajfUsP2<;!cS{hE4s@%g2}F4S88(6-(| zB|(?&YY5>$=7e047N5Q|biMnAdk6bX2!5g4i9rgqxTo?Xu~>0&Y(hK|%Ucu6k5|Sb z@#v48ZLx9j=xt||#iqt5#Ujz~IU5+T*80oE`!zTIhz)sYvG~aWWxE7i#~ZFwN@5er zVtK1$g$rY`c(k~r7&(kbPSO67*cfD65HDr+WhHo&UALm^{%AkL3h#3lhF zJ92UZH19)#*mx<2n`0z8wu~7K+l(q=6-YayEH-ToWyvq0DA@P#XZEoX86}0$i5{bA zU<4Lpwh4<^fW^JCM$B})$UR`?o;#8Pp!eut z31dQfzdL6norYMJ#;A${h@~pYH!2wwP|1_;hSfhO-Q`hA7c#O)bflWvAXQa1LT%sq zE}2MOt%*%5^KlAR`r{*UdOMphc5PnXLb`wJ!0Zn4n$Rv=v8A!MXLoDtT~y`L*bHOU z`9@X20{%!?g!Emwummma;Mlmu6d-mGn&%XhE7YbwPPY3s&cnqv>r1@ErLnn2fXdY) zG^?_1#)v8$b6=LaYEEN<>gF|9{XSCH;^uuRFR>#K13%$W(HFQ-O z8y78E!!e_TwX$#xYyw?=g#A4Fw^^}#Bt-3?GAzw^oc)NPna_aAQmopK0Id5;e5`|` z#WNx$I)(_un-D$gjFNz)7>j7Keo^zIM-PXD+9vE5iR7_FMQjWQuURr)#p30$1Wi%> zk#g4M#eRv0eW^==(!Js7@HeNwlMW#m2ipC$bw5VLLdX!=$h=>N#k<{0U@E!zwC?6|P~eLWJk`7eUE_#lKM{h{VTYyq{eb8+RlWNt1}g4y}k4 zm&EcGqIRS^izPWBneF7{Mh?P^1u!-?kpNopijj>jvzo|{Pm@k4S%xzae{*`kEA~hJ z^8Bng|)5sP8waWJ@cES4oQlOP!Gfhsh5X(jwjst2N-Yn7sV+{vfkg-kw<%hU_sj zz-Df&5~5X=#V~!Di4j&hA+wS|EGN>4&&dyz`O>lPLeROf8ZfRzN{`>NOS@Zul)!7Fo{M$5hr?B$(qB@1P8;YDhpidZs^$9xGSfG>ti6kDe zwNCZ65w_c{m8D!%tO<3uXHPV3;NPU0n}yvwnlqQ>G#Vm%yphcLp?@E%-wLbovB}78 z0ycIqV$P3EE=AU6)d8JDiiOw|q1v$y#!S9rwRkWTV}Xb63bV<%v5CL}jOa42mpRQi zFA+%Bt@e|y#>Q+(bcp@qAvt3LRrlzm5!4=u9waLycRzWqWRxF2GL}TfRMZBV0r*9+ z6AB?#hdSKXM`nv%Ae6|r$7aegOX{g0ey*0w_>s-%VX?O0XnMose@-Q8#!93jqN6Vhgp7-S2unj&)huq3QDaFd3Kt*PMe@akRvho2 zGGgKW+w#AEboP5WOZ~jOmeWKBqtHD z$MdI-SpNBv|3)|ef&eqfc9dDmm&LGK4Q)d{wa;S$l&cRZiS9wB!A5ZZ$eE7R2q;JC zfm%UXNvIjT^3O7UTU!PDps{{v+K9^f&&z%HKg*cLFhc9vPa)44#-X8NOtcvDb!=v0 z-@;b0Y)Y3Sefd`Hdc0Rb+VcEOm(=9qJ5@0LLv zV{RG7N%7X+T?1~CHLaPtuFmH6&eqlzrs!&I*pO-Ls%^iY_F+FQNb0$a77Imx-_Zm#@3FOuIA3h#;(?uhUSh; z)=5{^Hq^F22Pq;_;?Xbab$u-DBfj zyL)=OhLuG->I0h3RyVh^xMbcXb&$@avKbl{^wr*&SzlXGp;+ml;?`F;cqZ47ZR@Im zUE(K*t7{sOz}jM_qaI9K>o?M5Te4k^4b5xa$n_1i4PDi(VpFM>=H^U_dC?pX6LTb! z_Rdra_Uxvy#@*JL>CAN1LR(H_E2K2(R#K%IhuUkdp&45_TC1}S9iFn;G@7cLH)us0hr4zR z^*ZUyI#?elb`5Rc(YvL`>Dbtcrk6%x(N>-8`ix&`4Gr1a>aI*G)m2#oORVnbNYy*( zhAcjayuLBhT-Qj?IUdK*$wD2 zx?0v{vbBvZ>%+Nco9o;z8`fCevv$~q+eu3gB>FR5QM#3e zUV(m;`k{$R!)?uE8-%KottjK1(0lUU-Ge=Deyq$9#B5yK(g~~DkjiAzXokF5h3hL@ zdIl@mSG26lrn1$@jMcZ;G&AXy&;Zj-+15^{s|y#5hF5^tHab^p=q@%|!x==)c5NHn z)xT$#ldfRD24irt?M)d^_qdZayrsXJoz!6O5bnz$*Jd=W>W*xtwaIeomSLx-d*|RT zcKxZ^Iw#%Q*`8g@ZqjF4J>A=OxiU!u&$KiI8@QB&a#+#5ev6}qX^%dZTL*hi?(N6e zBn7Cix7kVI2KokiySHt}XxiA`;f+Tr4xbIpXyUci4eTRL7tWE^vjq%qO)c4s_Dks6 zI9#AOH4Sy_<9I!&cMvy#oD^Dd))kkn8ojIS_S4nKmlahhLkukg{g2bo(6P=n3Sr*D=vPTvb_@nHH9J_`m=yedb$U? zL1WCQroxp%h5#CQmz|ZkQQ8&Pc2%cRo!RP?4k5zc7`7F;9-3WW4Xt%FG-Y7Kwga>h zu!HH|Gst>zxoa`4#$?#G{7`XS=(D^gsl~Mh=QAgp9y77JW|@WgtYm1<&_Hj0&n|Z| zRk^~=-`|y+LB{58S=ORIXvuEus%@;sXAK9saPiFH!~*jpw)Liz%S+3GAr#|$r`Lm| z7pHaD#f7;vdId}ZPy?yz3bj2LE;zE`u+CNnCpfGWJK8q3;2R-GBjd6baqnQ?aBmm2 zIy~4fIycwB@WDQGYwrY2KZ zt6*vT?!+h1D{@f5;O6Gw>y-O31cq1L zoXR*uxDIOPk;u#~GbYkqt=U=`sqAD=4A9o+VyC{jwWg!R8)Iw-Xf^DcB}<*+Zt0%> z;jUd<_SuqapElTgVy|1@hiOxlxwNb+Sd}uCK-xjvm9`TmSJuE3(dO>A|Sb1Rj;%m3V`(W2PqN4lCKv~+$tuW~+({jcDrTf3`i#3SkYx6e`~1iqtSCZ=Qcys(lD;R z4|Q?k3^9;i7RC^cGt3m$-!k`Rw+vqm49i<1%G%Hr0v3)1NfV;o;_I$WWA#REE~xx< z&7CEwl`Bj534^lA5`M;@V#VU6CG!S*G07e3J+x%euI_<7M|AHV9PZt>XxEY@2pHb6 zXV+HXww=4T3@^e56pp|aKo0{zxozO2Ws8Oe7WGsfhLA0T-8+uJCl*dxv1nJ>E_~); zLC?^@f^7pOi?)|6YFS*e2zStr=!O7`w(Y`Y^)1_b7wzor-#)zKhzbOmv1Ac@0{FJ= z>F*xy+ugrt2p<*z4k4^(%kUQ0Z>@sUuC3@)MXg{bHo4R+9jrQJl4qu(GG@viO>;{p z#(XpP4b&-T)txX^SDV=V(bbl(BOk`+8@9^Y)}?dj$5=jB*EBRX9PLeMk-JOh&6qfT zxWQgegqbMjQXRG>_=jVB=3;1g$W3FXaWxzgy$uG84=HqpHCTDud5>##M&;5wcVsz} zZrae=E)y$nY~!H7mflcjrw{0J+G&5fVJGxvZ>zn&qq%ymT@*QKtdPAv$I2(86;>7a zOhA8+tvYvNkC9@)EfU97cerjsv#x2`;6_@0sYXodFlFba4Li_^KnI#_ug2zu3=Euc z$(ZTXcd$ZQEUWn3q^Lvn8ER;o6F4RX)$kgVo0hih_%c5fTr zi%&~v?8V)&WeqPgbG+>`N5ni)rio@|mU4G4 zQ9JD&5E2^*QYbMEYQb5TZsG=!R}P=veA7O!``)>`e|w2L!$sGPVHJzZou0hj=*T$- zM-`bZ+S>4$MrTJW%+*dSs?q40e4_w1^)U4_J(kg@Ba3^iWK~;`)oeeSiHB^xq?<5A zS)EHuf{g4MhI+T}>V>#g4ovv5pM-tSMj7tyoZqzy+0D`MSGo}l?Ob1Dpu~PGv#vyU z*3s$pF7@lNUHRLxbG34yQfansV2Fru*Zj3VJ{6qPLrNR&O>2 zU>U(e8sjnBb!aU9MFzHN*fucjWLk8iNX(7r40hhIQHOOw7l&@Q4?>1$62|&H#rWH4 zwxzxSJF?iDZ^niu_KnQq7<^3?dA27zV(eEq*fwAbouS(_-0b7$xen&h51-n7MXC>S~sf8C6IRhZ3mU?3ap9q8SHz5sR* zOvNdk?ZSLrDMwk`ky6hx$hLR3qtI#pP_t!l*wh`XjgyxSY;Q3^7lsE&Xj$Ww5hrjB zsRo&EwN_(@uu*2#D0>YYj&Nw!#M3}Co8Y)9J!ie$v|1*j$V}a980b0e%F%SOE_d5c zYTs-NZ-!MKRLGG8nt<61=k{4`wz)}-R2I#8K8Dg{(sh`EwGu;+9i+%}@<6xan*~ zfVO#}C&$7W=89!*XKiy+jV*{bAsp)6DTfz(hPh8}WoNspu4zYaVAhXli#i@qP|&)R zvhT@5==Svu=xVG4IFynl<v zaYE*faAGsE?cru$-Oj^x_M4_ceC=OF2mj7SvmGmQYubVw^$0hp#n*_~yV@lWx}G$T z$7CFU4$=QXbc&N*-wAWFs?v(6$0FUdDBZ1b39JsekYU%-4yHD-f2NBA@rD$JGfYU# z9u3aj+r2ZEcI%tb^Xuu}t$SeTI>Gk(F77k)$SyFQ;Y^Re zt!&Ay1yQBu-hnqLV)ltDUJuj4_PeiXbr1PFORKleR_+_|w1PYGW-hJMU*DmnJAF#k zrp$4zD~Y+8U^XFjD2Bptwuw_7&K2yawbg$_4Ks8XCtfe>t$5R!1FU&j;EmwwE7#U; znQ*6DdGKe&V#Bf9N_KTf+mtOd-)5M1#Q=9v+$#o+mCc#D7EA%rXZc#A@A8OkHQfET zU9fLwg&h_}HCy&=)PqVaJtCIp?B#ggfu)kYY2viYk(D=gy4N4j`p{r(+1yiI|2FDi zFSk;#PlPp08rhFnMy(RdNcOz7U!`*7C{;I)>T$t9HjhjM7e_XkZ**qjK*_jvWv6Fp zsR&t6QfQ~9Nq08QX*#mxIO`Jo+pB1ScMx=jAya(Q_|d&l>qsr@dDqCzplEhnQtatn z#xh3Z=n5@Ag>}Gw!?fI(AVb*^ayqg2^iAmk%R3ku>RFB2ob+cLvsn^QgwBVp9{feC zZD_>KpES4qT7P?c3j3vvjhs)o;=3nAu2Sr*jQ0%CnRjFxn*0}~D!nb3N;C79b+NlI zQ|X<)RC>oRmCHPW!@Sq!qUt4PRl)f`uVPiM^ky$I!D;3-Dz874yG^zmg%NOa5a`jM zpI!R~hWwp^f0AeQMzhIw`p)aH*wXS^e$t|}6F^RE(SEMp-3e1`DgV4qO_}4A+p1(` zBsW&1mMgKp%5zHWZZz_q7H1J=TUw^genRZCcy(sh{kEIs+8A>M?k%VqjJ5KH8g~e3 ze6rJTqd6(&ehDM3(ieNxy13F3Dj(Acx|Ci8;}>q-P_Kd)ALiAc90*kN#)@2ev5f89 zt*^fahZBQ?-I!)b8}R9z<(P&$9}d2RWMF6SaIdPK!@S;ILqEU`0GYeldlL-Pc4b!|X2ymovfkgR zz=8tD@VurZGcZ#w*#WXi)iOGp*EYATZ#Hv1EP-t_R;Sf#^%9lr!^lQcLo+N1C(b-B z^yW&w{xWbhg|py(zoiNbxA*tm?#ZxnP-red4fBlT*}vP?6|KcwK7j`1bjikebJ5`T zsWDGp1gb@MXlGZM4GlaUug4tBox_v29PZk(d$*ky^R^Ri#rT$P($&J?WJN>0XQAPd zx?JBuqjxOsZ0#E!81A<>E^Q&ULj;a280fJdH0YVGUr9L9f{wVfbZbclIRBd47C|GV z@@0WW%hOXi&cVBP^mdC3*W*al+oay4&W5-HfWIs?a_dodEPdA2SPeqq0f4W+j91Vzavo zb+K}=Fl@!DRaXm`_1J6?ZwBx7djI0cKbE00=53iKTo&-%%#pzY4LES_Ro&W}ZP|dE zsnRu2%jQa#u17FMvibUoYih{!o;KR5mYdhO#%uQ;?0pQEjf_jR)m)$8HXs*8>~NNt zoiFVYe4T}5Yx$Wyso003W^U6yXEqd|S)r4=J#I}Q)k*mgT8O*&NEH+_}Q!g%3Mo*-IZ*7d4I5&1-RFkipquXlsUQvgFv8z;0Ap&NAd?D8-c~i1mL1 zwqa7(uW;p%>zKjQFX^d+`}5`k(C+@-+qTK&d3L*ICnPXamr)pV^#Od**${X4%$X0= z>{G|Ct$W?+QRQNLUTG<$rRl)qs@Gek%5;W(T%B(Kq?x1V>4g5Q5(0KYb}O(*lbgtT z+@mhKE?3E}Kf0!*R}=I5Ea<(|WfTGSgCYL0!C`>YwI# z4cSShxj6+h@D>hk-!HdX>azUMK*+uVo3U)HoVeQVT{lp+FfWekEppTHq))UuGEG*+m7Pvauak70&v);{ z8rf;*eRr92%DTeW{Iy0x_kwLES`oHL?&hJH$H**rgiFBw-6NTnHG3;E*UWKZ7AP>* zX#O*In`KQF_aHm)wTJEQr4cI}juG7(urv{Sj_Ag#U9NA*uGN*jv?6v$I5ubF!H}n| z!<*D#L(J~yn_^miwYa>_m9+h|kd@!g7}2H4jL}}Y^4gYOaPam`oVrwMRmnVFf2kha zRg&4YwYR4SA7<&W-_0pEV(fQr9(v&WG5i9wFD6LE4*EgVxIeuneufn&UV_%)<{ z|D=$gUxVt8Ul{VgQ+${|zXsLMFB~7{7xstg!+w6PtDk>ZUVe?PKR%p(Qz$;{---BQ zIQyK9m+Hd2vvV$q1o)E9pAY@it$nKSQe9Z|zTC5;=ZuuL#1aB8658CeBb}qaRp?YF z))LYQ`Idc4HY_y7XUERTJvaJ(aI7gT*)h7XxH=J(gLHnm215RQA^*aVf5kia!}S}c zXS`p3o8ezGg8ssMibDC8g#2MU;a5NV%lS_Ju$*E3|ExdEFD&0X#fS6zXVbq^J9wx3 zncp-x`|xX!YYX$%j-~-N$=`r}!}XO0yL(Rs<-;>bafiP1@s$&o3MsgY@s89Akq zGV@CbNZ~#Hpj_v7|L|h?70>=y`sI6QU6Lrj5ZCua@nyIN`TYFZg-P&}OAlNQ{QOlQ z+Pryk?TcU(Uwj`-9~b(0E)~8>*Y`y6CHF!4JfZj6ah{Kw^5=)>^F#deL-dIdeM0DI z!{$LJ=6j+}L5RK}#J|8tO?k$K=*Ncm^YjuNC#3O(D9 zdH53_-V;R+7^E)_@%J>#R8eO_h<-wdeuBqb=qH8fCxz%~E#4D#riAFHgy^Su#CVIM zX9&taEkw`O<2_OQxImD8hR}Od{BZ&Ai8>`A`Vyh{?4iUX##5jW1FB_(hQZNTJ{CQt`(zyeH~Zh3KnRFB>r!<`94W zD2ew(@k1`b`f3&WF)oRh6N92oHbkEldaoDdkBoRv6hCDcK`tJ+TA0MJWKE(g{5dF>&{mzj5 zJ45vSA^QFh|NapDK!|=o=)L)Y*Yh)B)ENxX4~F;;hWHPM=!Zk{4~OVa3elew;(tzGem!8 zi2s=(`m;jxX9@jgm+CC{jW1FB$Xc*JJUc{xc8LDm5dFDApLVIvb>H|Bbi2g$%`VR@c*FStHM1Mty{)!O&6(Ra7L;jD1{8xqi9}W4h4f)+)7L@R)b3-Wp z#*qKxA^#^GF5T@@gqJ!vu8)_(C9(eHPlC};9VD^7WsgTcZ6JyDD_a!(90QV0!nsiW zCcePACJ;Z?`K>Zc7R@$UzL_+sZ7^&5T@oZkohlbkp*Xa0uY6lZe4Kh0UB ze%5&s>#HNwZ{#g;TGdY*N@9J~6G%VD*{l9d55;5?|xo81Sc^yVP&$tJe8mAimytDiFWM`Gfj53%^Du z?%Sea`KH3pA{&0qPKEjzm&E+DM*St?&pMszuMmH`)2DvUq?4E*o)Pe`cRmvEZ*;z( zep9|-Px*s zlYgJHClG(Ub3q{ePUpHne82O5)IUecKj3^v{iZ$#onNTm$T#f#PW?u{lblibfhg+V z`1d)})xSgdo#Irg-_*~kPL2B05`VhW9*92^zx`zR8GAg-*&Fbm?VP9n4U+y`=fmo6 z75{n8P3kxKUEq8<;J?UuDB!=uc~bqR{a@z%Uj3&0mpd_R(Xo8fg#U+}$pJt5=aD`y zF=zMyM^t5fLxWq&Dx5hzPVm!<{u4R9IIKau(Xju0B7X=e_$iUVF{Cem@$!{K0Rn#r zDde(KfWjX_3cY?Apb3V_8KZtIS;-{G9;#}XWXF$%`e}G%?j22<`z^sR_XHE4o7I#a z*+^mT*9EvKdHKO+>bno&lgnJN(*Sd#8we6*%JmAl81r^l$TYPO`*PrI1fSP_Pml(= zqVf>hM<$o^{C-|HQonl{h!>T7Gtr|lY3KWyjD>-j>jY=~K zUfyA1d>GjG!5}F(B<6)CmBcNVFU)XruN(vlGQua2ExGqik($Ej*?cRQKM1wT&oPC9 zcnLNXBsXS5VRBi^AEpEIj?jBieogMb9}~c z((n$&&59+898;N(#fk&?Z9c+hW<=%|Ovn6)wtO7p=?|mjZ_(0+{RavU>+wM8Y&mT? zR;WDIzghhj)9SbKTDmaWdbaXm%Hia^rse;m9ScvQXM!HNqMD;1Y3a!p41lwyNoi(;qZF^XFhw=3>a98x@4@eIXt6uEX|J|9s0 zu;R6fH!6Nc@ixUf6~C(Z4aEl(zpwZs#h)oYt@vxjmlc1f_!q^u6mzjwqI?O(q~c`7 z5=E{7Nmr)0OmVehN^y;1o8kt=F2!w%ToaPtu;P0Z&r&>J@iN5^D_*DgNyX19{vXA! zD1JlnJBkl0{zUOf#a}7DtoVDyHx#jfC322ZEL1#5ahl?6#rcYriYpY4Qmj>MQtVJX zMscem*O=7LfZ|@o(-qHAyh!nbidQS%pm>wwZHjj(eoc{UQReeK#UCpEOz|1T=M`U7 z{FCC}6r;I@&uGPQijx#)D$Z40q_|Y^aK#$M2E|sz^@_(S_A2gF98x?*@x6-YDPF30 zrQ)@UpHRF-@pi>8E8eU4fZ`7nf2_#0F7@}E;!BEL^D_K(#eXQqu~uYwfnu@ZRK-%o zLlr9&mn$Brm{Dw0FaiW3z}6c1Hgta!L$TCquSonn{b4#g7{Pf>iI;zf#AC|;-dX~oYg zep&H8#qTLTrud}dZxmlsd|feuIS5D~igzjE2izq7T*VJ7-lX_t#qTQqT=5mfywN88L5hnM8x+?m_A8#Dc$wl2inlBN zK=J2_e^4BY>q0EYG{vQg8O3#q+ZFdIp09Yd;w_4ID?YCHYsI$|Cyz1t%~d>7ajjyv z;)#kED1Ke>=ZY^V;(C+FU#NJ9;xUT*6wgt-R`C|aZz;a6cu=9rr?_14c*S!SKd5+% z;@yhhSA0tGO~p~THbp(pRIE_UDt0TLqj-bj=M=xK_*2Cf6yH!hsL1dyRa~XGR&kf& z>53myyj$@>#b*_NuNcKdm2wv=Rwy2!*r~Wpaj)WeidQM#toT*MhZJ8>{F7oq(&RTo zv0SlAu}yKS;*jFmiXT(FRq=kspC~@B__|{Lc$420#RZD16`K@~Q#?iS{fgHseqQk# zia%6*PVtY5v0{_o1jR!XS15KUZc#j0@dCw@fpR}74xT< z{H7=_P+YCpqo;k+^V=+@%@S)QM^O( z8;Uipfor>ovUZHra;)9AmQT&Hu(R9Oqq2fx#HpQ)qrz>8l zc!%Qsia$|&Uh#Fs{25vwiVGC$6gw1mDxRl!h2pJ>4=X;S_&dd%nTG!i#RZBf#SX;* z#nTk8Q2dnQeTok&zOI;GqVg*)P+YCpqC~}Vx!_l#S<0JQoK&_7R7HWKBo9<#Xl=1=W0HR%N6StH!AK?JWKIv z#ak5bR{Xx=Q;M%CCJr(AOj4{+tX9k_b}J4mo}+k!;^!2*Kc;xM;)9CMD*j$EdZ^)Ftaz~EVTyH%8x;E#Pf@&5@kYfb6kk>Ro8r9r zCZD4fFIW7Q;@=dD78trYifP5H;%3Eu#j_MIQ~ZSD?TX)4d_wV6#nB5*J|&846;D$9 zrsC6zzg3JZGU<|vOBGuck5$~G_yNW16z@`eK=EDc+#?WyS9*{#@}D#k{44??H--6pvKgtazg0 z2NiEqyj$@x#a}D_S#i`dm0Phwv0ibb;_-^_QM^d;TE)*P-lO<)#TOKL8IJR>af+pi zOBBEO_bQ&Jc$MOviuWl#q4;OT=yH?aRK?|rX~j*7`xMVnyjJmZiuWi!qWFs9 z8;avrn0!hVmnfzcI~BJn?p6Gt;>Q%fr1+rX6N)b@{!Ou9rO9uGV!2|KVw>Vt#UaH@ z6|YgeL-BsapC~@B__|{LDwE$7#RZD16`K_M6i-sTMDb?DFDgE)__E^bibaQ;d=@IM zRBTh+syL*0sp2(?cPQSk_^jfqit*K2Pm1M=b&4AlhZWzec$MOviuWl#q4;OT=n;nh zRK?|rX~kWNrz>8q_-Vy^6dzH1Mez;A(jyK3C5maqPQ`7Cdlk=9yh`zA#jh$pr1*m3 zpA-v@GWnD%Rw=eAZdDvoyj1ZT#XA)5SA16SRmFIf;XhGviDH%F2E{(ba}+OE{Ho$Z zicc!Os`wAZqH2@REXBo&DMfqXu2Na)E{H@}o8k2shVzuH%#XX8= zDPFC3i{jmi-&cG}@ij#!W%!R%T%@>4F{{|EIIMV%;+2Y@R{W;oBZ@C5zM*(f+T>TN zxJq%Y;&#Ph#fucLRs5XdJ&He9d_mF4Xn7P%6_+Tc6*nvHQoK^}F~w&U-%uP~Yxqu8 zT&|c_+@!cm@pQ#Y6+fo<1;y_xKB4$~#b}+$r&#e|#lsZq6uT7%6wgzx%J4BmY#z1&V7Gk5N29@jZ%HDBhs> zImK@%{^0+zcP7wHRqNY7X&cB%N>gZ|q!b8)fXGk~5ZcsRTSgf~Kt)BRP$p$4v>+lg z2&gD<0YyOtK}1Ex0h|y)a0X>kLBRo05m8alTSvaZwVps7Raez2f94p==&KH-7kBcvgZ;5-wFU23l zSG&1>?Ge8akBe~^x$$Y@*PkawfL>*x!BF8j@VQ@kNg_n6QS^>;??9K%NnNe1o39_bIV#m z9<{7h;-iXRFK!_ZSk}ji|4clj_~QzfioZ)w?1B5RPp?YCeumgUdM5d?g)e+`(_NwX ztHu7(M<`q@-XMJnxzDohQ}_|ZKQ2BkeWSu##5bkyB==g@QH6g~JU%|^`0FM4JVW8i zVm0Y?$oDMkeCc^&2gT!uha5YXiG8FGR(Pm5Qu+jir-(D9&mnhN*2B^t6Q3gC-%AQ_ z7GIaXTj4$8e(7H+{Ec`_`mf}6oEz)q+HD}VAkluU#q*`NC%54{FBC2oCy_`$O}tt9 zJn~J;dR*Zb6#tUAMf!GycZ(lLKR~`_IS15O?%*W|gVjjnS5rJodSh~nWp!5gGR0ph z_LV+V;UaO2^r_?~%eqJUGI6EipHz6A_=5D;6n;zmRQgxs2AprZ6olVtVomY|%gRx> zt9Uv2EY44nDBoCdg5qyh_%?CA^!v!Qmi4^!4dQ0SzoYOjaj*1G$tUsMRSE|$LzsS& zk6Ttth1-c2ldCOjC<*_H#LNE|JFio!RE zw@Sa0oM%}p6@F6j>%wi;!&;&B+6A$Op{)RycP4M z^gOYH;(IE5nRu1-0pu*qCkoF|{Cx2)>C4EQFdr)Xmg3(L-<7_foN8IWDqQ|bgyC;M ztVp69A###sou_aIu_rm+vid1JoW%X3#Ie#RlQ&q_y$U}jt|P}-)(#T)y(@m8_%9Sb zEFP6!N*3dN$3E_TX<`Nme;X*=NNg@Wi!8#lDgAQsYQqeC5_8rG>G9VfjB@!%#HT7;Rje-kY=s+(tw`9(CXruP=@*Mvh*yjKNu(R9aFIBc zM80>5E5s+o=Si$t?~?FyulSMT4=enwcue{Uh2#6W_xVVcPvNR!V-oiB#a<-R^&zom zx}HS7H;R)LKU?9s;zH@m6n;Q_So%7JpBFciu>U%Vdig;5N8*>_*WytU>3&xDchQSJ zPk$?r-7V`Jh0i15cea=-y^F%##mh(#P3PiDc{d!RTB2YWM`~13SUT~oZZBp(($dUj^1A!O5(ne zB>bNyeWo~9Tp->>BHjH8uM{66;m0}>ud(b__!Gq+6u*-GqryLnasA!<%9F4kBH@2^ zv7XpaY)T?sYlS0XTM~YBA@Lg5AnDhMMT#G<@MQ5O>GKp`DBdl7rNR%3FNiORTS(-) zUE$s0eiD8hAmQ(E>7}9vb2!WC75yaAr6`;x)+Ay795N5jccot_UZnUd6~0C+lwPE8 zi8z6Tov9@9TOfUrxJ-ONe3(SKrxbohe2Ii#ABkU!KZ~9Li2oa&2a_mgSUiiweJ#Xp z(tC)#rS~Nxm}jI<5~nMEzWAv0C&Xu@ZzkKoKj{a=FBSij7&p-Mubh}j!oO6qm1Q-R zey-SB@g2m=#Qx;DmNk(?d8djq6@Q0#zx0*jYUxjtnOK(AMOMjBAi+->0KE;0` zej)u^vKIUv48q^aWDT^x!r5ds%eq|QzGPL)8lmt+@g}k|=2L|qCM#jRQ1~4(Xj$JV ze4I?g_q7ZGk#8ljI%#8{OQKxaVlIhvofW=Fyqxq})(r|z5NDA{KU?%!2!F26r-3O7 zr-`TnC;lw4k%%UD^!DTd?2AOatmK68G}_?^u~-}@P84T}v&H!$o`N~|KOy3&vJ-w$ z+$6p(ZWVWnd&KX^k1gw%_>1_5=<~SoiDHVFCOV&2!~HE4&JiyVJBnSzUSe-?1i8<$ zip6o_L~)ilTbwUCpHIVmPblns4h`WK72YJiE^ZZfi+jZH$h|1P_>1_5=!8DQpEHA<9EC3sJBnSzUZV4PGo-(c;rB2u#4+MHaf!H8d{BHuTq`~&ZWOnOZ;Ly{ zy`uBEGUWTE!p`T)5OzLS2L2@7`5YO-mEv7LLt=HYzIcwK zg7}iSm&EIv`^B%t??mVGU3fjSBIZKAu31&g5bKEz#b#nlv9oxQc&X@oz6Bia&CTpu@1S(vg(UX zMCbEe&?5@xiXFtx;w9qc;#hIK=zP8lc4jI(Pjo)#1$~LaOT~x9$HcXw^SLji->mR! z;@jd*@v!)<_@nr?=+br;4|T zw~GtKyToPU1LA6Njrgp%UVMkd;SE76@L>Gu%I)&PYjAFVl}a*m_@F}^DwcU z*h%auUM5~G_7jJSMWXY0IM};U;k(3p#0SKO#5Lm6;(BqT_?q~ZxJ!Ir{FYpad0qTj z{9P<>yYT_Bl2}D-BxZ`|iP_?%>HiNH<+r%BB^SMUEf2{Bq;$bl%;NI^Olf_iA znpjh;FP$cvajc z?hro|KNi0b4~q$j?)^S7SxgnHi8aOg;yGd-iT4xQi(SQw#Vf^Y#DU_q;&gGAI9FUC zE*9?-9~2)EUnOs~tT)9S;=AI<;%DMv@msM}{7sCn;MyxMo+X|wHWOQl5iwWnD0UHh zikFGki2cQJF(fK?u>>gow7|utC{}6u_y~%F8E!Gg7&kN(e zvlVVEo+oCDJ;-Y<>r(M5u|T{|93hSo$BBOz?-1`1mx+&vkBeK#L3n*cd`H|R?iW85 ze-eKYJr&*iy<$*I5gU?)`2G~JrPxNy7dwdE#2(@(@@mT(BTf*fh_{M!#5=^h#TDWz z@p17f@kMcy_>p)(JS=`II-j40KR+w%!D~zO&nqU1$zoM8L#!j#7yl;aix-OB#7o4> z#lB*pI7PfkoGs23?-uVB9}piBpAw%DH;6BbTgC0-H{$o=&*JZ5LW)}-J~3HL6|0Fg z#rmT2d2rNYbA?-py-2)|*IT?s>@N-zM~Y*`@!|~e7IB`qP`poEEfL z#4p9K#UI3<#FSLm|1`0NSX*o)W{T&D*#_Fs5nL(C*CP87MF_;ijRrT_XMCmo>zE-_=@<3 zxI=tb+$Vk_9w#rw_XCM1#CW^_PCZ?$A)X~V-#38xa}_>MJYUQcdy9R<{^B5UnmALO zBhDA^7Vi}w5FZlPh);{Jkv;J}QsPeWJ+V~$O?1B30O`wDb?>VvRu(hFu-H&+BDNIU zi1}g%v76XKyjC18juvkar-?JgCE`+XmAG1bN_<9qOMFM%D>~n=fO4KtI6mZ-*DofC zRmBXkj#yu8CbkqKqVv5Buz#V#-NZ}8%f*r6XmNr#MVuwh79S?NTh?RZTJbq?v-q0$ zwzyN=CpzEv06SkQ{I&R___LUl?&eoXbiNM)_tjANEb(kHN4!AnD0UHth{MDZajZC1 zoFU#OI^QROd>1QxpSV(dSbSQ1R@^4;5ci7v#e?D@@i(#?-VDNfdCoZnF(B3uYl~-# zjm3PigLskHQ!FAo<9w)iqc};tS-eeLAUfZ3f&1=Pc%}HL_=Na^_>#C=+#`M>9u&V8 zzZ2s#T>r|8Nn$0jsd%oKC7v&K6uXE$#mmG3ae(N2-v-K6r0_U#qBvi?Q@l@HEHCB7rR zFMcR~CVnaYN=C3x6wB3d!+x=@*g(t_TZj=cSL`Tu5evySI6o|o5R1hL;uLX~I9psP zJ}f>dt`lDrH;HeE+r&@ERyaQ_el30{+I10sF3vrPsbW>Jw&;A15YjbPxS7~N>@4;a zFB3z#3SNyu~a-E#-HW- z84!bFL$V>}1F@ypM$8vGh~2~Ek0+BbI*Y_OnoD9_ zE+R2MEG01yts*hsts(O)>shiL-VY*?`RgS1)7wcrkJ&?Z$LF5No|bip#OoAC$=-OK zgS-;|dBCf2PJk>x`N=|*pB#j9uOwdgZ$RRGf=sdq z%1=&3`N^A5esUJdPu`01leeS%>~Ci(XaZ5eMNK$M@Q2;ED^_wgV7B*t4r%oW>;-9_hoDAM&-xR2OZEEJ1KG)jp$Rva%*7N?7|#M$B^af!H8 zTp_L!SBq=Jr^RQ*_2TO!=8di5c5%1(iFi;vBpwluipNEZ;{fwdg6NDxgq?G!pfesp z{stb?IpY${P}mul2scvL8J`HZP}mu#2uBol#w)^Y6?Vog!p^x>&>6R0^nb>K&iKW; zR>&~ujN?Rn?ulX08P8Z3N*D&6agFt1Jj38*66?ftaTZw>=dQ)MWHpQraS>Sq=jFtu zWG(D>#8qTn%UUh2A?xFP67g9Q>&tp^BZ+lpi}*U3iS`q>ljq`dFXA2&>(4&%6B6st zLGch7!TZhPQ4;IYaj}%lv#j4lD;{CYCkdjD#C(t_CX*P?sbWsN*tCNVziiVaAN zn?_9z`-_vwVzj?Fi^O_4TbxT`-CQ6pA~BgR5tou!M^}ie$f;<5aSeGB z+FyK@oQ3umH+uosD2a9XxL8Uq zMf;0f*tkw7h&~eQb)uL|V%<&^tCFkH{$iNKI$l?7Kw>>_BxaIW*IS6rxnwLF&beeT zm--86f3YLE0qrk#CpV$}#opu=w7=Mw#6F-<986+AFjOoeu`ehQ$CBI8{^DeE7usK( zMPk1&TbxT`->^VjMD9cTi%UuDBUXs3$OCA9aSi!7+FyK@#GF@Lo4gYED;9%M($>KgztPaGgI zKU@Z%IWO!bF&{YRsxS{!PeK^ue+!B6{x_6~%{Zk=-s7_SFVCmg30Qb3H)Y!c(rc^@C+@d(2=Syqo!a2EEbv<=6D z^L^uM@x3DqKZ|o9B>Q~`M1P+{qMz4F2e)9IB45L}C*Q=mezYz7vGabyc7!t!-i0vv z9=`v8uM6+BtV!fPn?xI+>74rqlc>8Ag~yV}WV*t$NR(-T!iz}wv_j!kB>L~u z3O`HMMZGKhI$0m}qwpTGA^MTRhe-7A;|iCOnc7F9ygm=Y=c4>1%TKmK`4w(Jwn6z7 zZcRo|euX=d7!SP^?oDD`6e>KJ#Q1Rbfw1rF13O|~QT$vIP^dVcatDR{|fge3*o=Q zgGr3P5{1W-7>Cmpo<(9jE>L(8iE+6?;Z$SU&HWnlwa{1Nz4;l72Zx_zSyVmCnV;L zBMKiSF@OA~u$6!?=8;5_7*SLsH3fyE%r6U{ zlFs>^O8unppA7KVDxIGZKIInomp4xz$GiC3!e_Y2iHdfU>7Ab%KEn;CkK>suKK+F8DUt4Pik>O9 z>{k4&@jtospU1X7_0}@G{K42$43CQXN#s)^-G&@GYS^jwx&6icndH;o=lllpDN(xb z^pVVuKb3sSU5qe4ntV!RSpm=3R?ZJ8pK>3K_Tx{!o)Y6WlzvM2lvv*P&*IDvE}wFv zTlO9w)1HtoL_i8ZH)6f&!-f`aY4WC zd`hHSM`wyPw>rP2eCB(d--ABYBU(M()a2%AejoZ2vreYwm!eOJJ$W;KGy0!I^Vg$K zi7vDK&tv~tdCPuV`V`|QU2}eA`jq&x%uib@?Beb(PoHulqud{yJ|)WSf@g?yMve2k z)Ti9%M&bWc>xfbOY3ft%aq~KD6z_3=tojUhogvb_@1IO?tZn|f^(khZ$~5a{?8;vD zYuA73lp3z1i;J{a6b|S&dJyKxfg`Y`ajpyc;b+#zxVgE?&=LKkg9W1sh7TH`)!0pO zsxoxQaO_0fSZtiECjCbY8#Z9L>e|%@jw%?2L>Khv+N7YQWYmy;qf21+FF)`!(8ALi z3olJLj~1cx8gp#*;+a$9CRg8vZeir(b`vw+P{AAC0|U(4*~@MA>5<7<(gQ>}^H3D*nvF*u&GD zKjnK6VV2E2OuCs6qVpXel`nOZ?}NCGZVx_3W*wM^v9}yTw7uz3_5z4A_BP@=+FmXK zr}J-pjJ?@W_9{f#dq2ir(HZ>vJ|-QXYoD$?zKO|qK~%oUQTbND{rFebPq!n0mjucl zre195(e<(<${t=KDXW+IG4>MC(NE`Jofvy7qU@zc*~^cymkWERtLMMP*jpWCuS%4? zYhvsboxvV|^EMGJLX5qoXDBa!8$8-Ad-ar#^C@4WiuNxV8J*4^U(<^A?|76w){pUTK#aYih!~1^^I$qY z3S#X27G)1FF_zhz7GrM@3`}<{xc?b@lVa>8oON>jV1HmbmY3rpy1aex8pi4TTM}b0 zG0I+(D0?r&*n9m9_MVBcml|b{^M~-^JK#6y+cLtFf1i{uW(-pTOR1#G8llFA?dY{c90ruN4v-duPYk8(Q9d zJv-LkSuyq^QRQtNWskpQ|0n;>U@tGmUY98UvZCx2#@OqHPE=%^Q#uCw#@Oo>WsmEZ zDeuG>ds|>{EDh*k>Tg_(y*^R)&PQ5fZ&8fB2r8ZZ-8_uF1u^ytqwM7(v9Y%<#@=Aq zWBrN~%3j+jd*8*_<9C3te$B)9_jQcD@lp2L zBeC%>2^Z1*CDniW^7@euSy{QtXnK^rj#2i`iLuuO_D<(t{TO?*qwHN6W$(fmd;IQ@ zzVd-UwDaJ1PeuE;0QSs$&_(Gu{|$<<8fEYDD0_d4vDXLoPB+f8W9;pYvWK_6%F5e2#vZ@ZB#e0TV7>6c?*@x5 z$J1v>cS}sV-DgO*A|~DOGo*VtCS59??3}K={O+;n`r8*(-U9e<+V|rad;AWR)Ahd( zW9%J_ve!S#-tRH?#-G8zpJVJDiLy5!%3d|B%YUlpGx(Q=bkXHK9%XM(l)Y9l_71{c z81d#|+P7y+x`d?D*ULpQ`TiD_@3k;$>X~OMqRY_&_Dl|ZmI_wQbym^@V<9FIc`xl9_Hx7wS{SAq+$M2Xq-FiMC z#$MYfd*h?*O^>nHAlW_d5$oUN7<*l!>`jcacVCRXp|E#4{}#vC>lI~ha+E!O*Isn{ zu7W+bzj>JY<9G8#*I%C~dsC6v)ZhCt_A)A--X6cxFWO#Vl)dRu_I`-5Hy8GL8|Rdc z!Ea;i4UMulL+Lo)0{AbwyoX?~I}PYz%3B`kqWvq0vNsE9O?m6Z*lUd!qfXZzwPWm! zkFs}5l)VdL?3J9sUQUd?=~4D(N7>_d7DktM%^B=n5o2$5l)c-d?A;J!?+EOj?)8n) zG4>Wj*_#_>Z&8fBaLVcDzXdV&mPFb6dz8H=V(fK+y$r;ghiPAar($%y3_e4;LrQ1v zpN@13hM16RgQ0^l{;hz2OYy{aCF1VDpXo2hW9(I(fbYjPP9YtA;-efopSfoEg(;Tx zLp@%(4-?1pWYPV!?Nx}W@8)|KlA3%g$Jl#x6+VB0*8t4J*sB<8Z@R}h-_3F?#-Fj* zAjV$HN8Ix$vG(f5*jqotWAXbkX%9zz%Isyu*z>NzdC8i_+R3_T6=Sc_9N0rSXz#u# zd+lW}Qzq)XgL5-c9hK$f-^DTMzKi!b-{-B{oHR^#b&P+J1dr7bdo%MeO~~)c#J{rV zjZ5ZvtWOY0|CZy=)ZcYTgr}@U=Kkq;ft#;Gn1^W(GOC%ZjYu~+)v_LhUWz~3OU57b zguSvyZVivss9agFtS@1@`%}8{cp>*j-mHhocNEXDTvIr#pvj1)VLY0hm)WXyX7kp~ z+Tc1fvsu*tty;A}s7>okrVEGr`X{yP(%$1SmRQdX%JOG6JWqs&*KLjl@IPn`g5cI+ zf^%yk+rA5v;SuL4_p$@u=R};|Ap`uZ($aIy$P zVFQYb3kD5n%tH?)gL5(=xrJ*?PZ1h8dU*emAtQ!2E=H|^#n50W6@^AwNGW z+<-;AVAQa1yJ7tX6c(bbdyN<|6efoZcS_xuWp2_e^XxO%fptL}^q7JHD5>RXic4?n z#$B6qy`WP!t6atMUF~?kuTny)r?Mw4zN#nWN%vIqWO!=C)%G-DPy6#DT1l|JKM@@p z|EE#MZW}$5FdRK&Fzk*%VN4$j>L82bIUCLSiECPAk;5$x<1wsoeX)tyQskbC_vMQhiWiI5hyz6@U(Q4S zw`UpMcjy24nSioG0B+(lzuo^oeRtoo{@w5Iqvo6k=kV)vO_=`J2-oZ#x%lIw5xN$i zw{enYFXJDlS+<+G2bazoUXK@gn7D2Tn`=hBg1@S~(8I*B-J|nefsB|B^JVWf`Cf%< za}O@9{rIcS3q4HS5QKSc_7T6}dcTQO9D|r1{*>;03^n><9!$f(3HZaPD_i$#A@En$ z{XR&y5%*%1a>feFak_Os0}(8%c^Fq?*ZtKLdA8N^f8 z{qii{zi-|DPg~0W;yz{Yh~g3~>o~18q<_IsY+3%h1^9Pt0m{ZM`Z(sd|Cl|%Dc#3e zlkwkw_X7VnC;k5O_5!(Bd;T4J0e(*Oe|s-*h%1X8&LV^B*uB7kzql9RS*E|T7a05( z_W})2-qY=oV)p_Y&$Jh4jVJa|53?8eC$9mtc9Z|>*8tl7i@iWORObJDFR&YTpJ^}P zahmDh_8P$dt9yY_0|s4F(69KvyMTYs3jyrZ=JB7j2RPYn{`*?M|Lmmyf8P4v;@`CX z^EvPT_WFMyYT!8w3kG5A`oHfluK)G^;`-nBFRuS#loxN$l|78BvFks-N8_}w1vJZS z9<}`c%hv*$wQ1Apude@H{>A!#0A44qfye)&*8=z=!kN~8zS8sG*8=|X%lb}2=fD3) zU*!L*FLpR9Rsa5YR{?vR|GpRSzxQ6i;6K;wfA<0Zzw84d|E7Ha*Sr7ieZc2tapmHo zzu0}i$A57jz|TnhmDd6IS%rtDSmP#5Lp`)TH3T#elatUtp(zR`QO<@$212H86%*N$|qI%Roj-|+I% zB5Qf+DEyV+Zw&s%;%^-O#^Y}y{w7;{W>lToduG)cy=SD)s(my$u2Mp!#PrF$4o6*k zqONmwy}YzNEOf*l-u;0eR_)2PYIL^3>C8JBd54iV{z~vS27hDmHx7T}@i!5Flfxg( zNS}Gd%=8&o%m~e@bu`&yC)kOh$-E9nU3;Rgb9IfpVWA`bE@aLx;hnHtE4gBB^4f&< zC;suriPg_lL(Nw5HrRc|;8gF+$2NxR?T)VDyr>#Ze$mq?eMb=KcO)bu{maL!%$*5I zPWtIid*mHIS>wqs=Kip+d-97H9bey<*9UOz*8S17nNN8dSlf@jIPd4=@LLn&zVF+% zn&-nO6MigcJH6C8w^^6wo!geyPLBJ2qo-$St=tjElH2BkJ?+I-+|inG@!$8&pPL*1 zV?qAr(#f8xeUH9)(NRxgz0UQz?kctF*6!B#SVE=Exbjb!_j85JN}d{BzN@vwgHRF+cUfhobd5OQoAM1N8xkFpTyj(iDSxVox#?SjX zFf zm#mjAIzDbBujZD9t)<_4tTn$(KALM6b@=XB{Iuk3--TB`x$)c{@UmP-l>CA`T*c2? z{G{g`Ye!KB$AV)M@AW->@(z^D)1$PORjv!}$<4!6uhKf1SCuAoUNkoP9`_D!Sso?_ zr*FXSUyDDTkNKzd@vqrCvp?Tr!o(DWM}mjH36;nnN_rCS%JK^u%>(ZV?hNBCzCoBb zyysMH4L#1|yA^XF&INsrX*0e*-aqiR3H4x1T>0mb81EH!sf(EGCWyHxG?Xz3<#*Qu zeBP^ZgaFSKZfk~Y%gzgxr=b^9u@|YD!nd-$bMRj|9)OGIC#%ZUO>Iy00jf{%KVHQj zI15*qseN(n-H89nZN-1(zd8s1CCuVw=cG<}6WVtz-?{aj(-=#IFEg9jUyP?Y@xBZk z7)#3 zyASPF*T)|wILkK&B`WmY4gUxDE9_k3etau@_gv_bYnrx`=P$vA3O#Z!h%Nm!KbHdhD~$!*^z3u7fzwW4{aM=6md# zsG9{IdoHSep~s$v{O<7BpJAoF(_?$kREs?JP?)~UV_yg7@AlX^sP@Gk`&!iOagY5n zO#kSyJE8V|^4PDSgZ#r||AJa9_1K$HsNQjQFWk32&R&p#Z`6*r<58Bc;_XdnjKlHv z9q|3@c)JVw$dP#a;ii`LO}zaU8vNUMy9l-VUA$cvP8^N5uS1ExkGEe%1$IfWQ=3^< z*97~9fMs<{u=k=JFG{eRVv+8iV9x|DPOy{FOg$3pCP2>wdpa7qSAty=b$CgFeGe-A z(gfR^jxU8wus0yCcY?hS;^hhUX7uzc66}AVb*@aXXP`OzB-riH$=4*<{H4uQuU!|# ztn9UKKn;%d+C9)}H+b#AxM7^vK8PCJ=e4JywEMmG-N@l1+yJjX_S)Ofmp<{@4N>+_ zy*7V#`GD7sL(1*t?WrjAj`DV+7M8WMy!{1QWmkE-C2rqc-adxXzFXdY33#u(&7bjm zzr1}It+}VX{RWck#SQT6*?`Tjl6)>;ue9;&b^&`G#={E%yBxah(x5#MUMvgRo8jmE zLAwyfmIv)A=;SMc_9&!$AZYhRO{@&s1K`W76uTPAeshY=pVLmRZ}V3HE7rFcA!SjT z?Sr2q)9m-qaHG=f!Dz6^$E4Zk!OHb%b~!jWHqHJN{qu%2 zyB%^Lmu7!~-g9G`{V@9!}jAS-@wE6Kon)rVgK#$tf->L z^8b!oM)IN#CWKME7>}wh<^_Mo%o#Y)(jhi^de^B150&Wo8L3}RmF#~@q4i*|5q zAuo2qu^am1;vQr%ju(|shumHJXCMm?FFr>-#_=Kvx%0T2|93P~0x!Nny?c4F7X7mv zFFr(@mFGphTHOER;zkT`n-{w<;QhRK3Pld^q9PWQL|)WQfqYkr%lbf|Ypj16nqP7q4MBrShU0N?Ms0dFVm(+CKn^J-oOO{>1TOZ!$}P z3orah;DsNx;pN45==|k)5pgO3N9}q$b%BenC}14!^Y=TKmQkiaDw@6ga8LYu2$w$> zb>sD*4J=>%q({&b61$<=MkY2yV~$F^3f-nS@v1NyKk+Hd+@llEgS|0{YtRd>Puu`U zZcH4BLX1zm6kTd!;^mk-CRy>xi1xLJzZB-m(Po7Nd%P#U1j&;+_3UBU6Fo^Akz<0L zW(6BIKs8U2P(Im8>d?-zCo7B}X%Dt!f+ zZ1x^EZgR>!SOM(4ZrsMyd~_fC1KsCI?ZF#A)Qz50FYnx^J3Xm=7`tD$dQ$6S{M#St z-ni5;Xh-{F-5Zy>2or(*iSCU{oyL1V)xB|*J9S619Pm`yM1SK`C-dIVJe6KW@MuEn zxh%~=Po=FabCOksWXaNI;UZ{xS>!4kalPiGSY^dPRi6r7kO%+*eoUaQ<6jG^GfG%zu7*puPfOW`m4S0T>- zrq`Z|#K8|S^8DMp8Bf54IP|OF*=Iv|+X$F}lH>fZdc6-Iam99)|8;LwCau`+ntqml zyEkwNbPM+0_u89iZ!ddWK-{Q4@#bt;- zSs_|N9le0*%D>MW&zrrBMm}G9?JUguuHT1^o5t@WMsWT9%;Ctjh*o^sfT=uRI{WFI?W#PXK+JBsWdsfoHh%_@ia!SYgYVw#wk8dkX) zjG^GfbTlzZR=L)Up>Xm)C(TfkCc!Gl4?uek2XTG(5PyVLm%9{x}`jn$C8`5Xjl zhXahUsw~9+J}ikEY{;@<*lrIYc%l)~H8KX#^w(j2@HdIdGJ@&EpJ`GsOOL-^*n1uB zPS3=m;cpO5qr>Sfu+8%~3kR4HdqZ~EF2o`id<~1TKPRkF5wwE*sF44BBP3bDE^yEP zHzQQAg8ZR-f36WQf&YrVmHz@G1gzj3tQG!zBiL4O2j&-lTO;_a;Lq5}`r8=+B^%9b z+ZzG3yC2^9I~c)h1*c)1^mjBuf)$(Am`f3pR8UeL)j5S z-dH;$!}e0tL-1F2y3cg zIhYFJ1|y($_F`Y-A7=#APFr?_8;yY4=}Q~qjey$82&kQ1tc*!U zK<(7Ua_OIJ1k_Gn4%n$iaBF8+*!v0!p1zCrM}*T@@bqakH7y)qy>X(P9kxG4lLvQj ztll2Z*a|tpQxnaMeWHJk5o%b$157d32-VSFDa43U?bJ1(P9# z#YU)P1^-TAi4iJV!Fwp&V+4H2%gbJVuMyB&iYVM?1oRgE8iRkS5zt#EHh{3q2R z4s`$hMnG>_%sFm_5zt$%<&^n=5zt$n#J0n~(g^4+6FImZGy-}{avKP%jDX%!9ER|a z5zt$vQ+U`2=q)3#&GtWH1oW1E%^^H$1dkQ0&B67!5zqya6a2Hn-UJNO^rdE5;Q%wYu)Mq$wihsqzMQ+>FpCGOW&#(3w~T;pg4JYm*!vtUI&rUPHK~DB z%>Q;cz`Qsk>)OyMKT8 za7ttBCF^=JxR_;noL#^FS~pR1PwE}a=elr8b0liv$>5xx>q%Wo^(Hq_o+owX*$B=E zrwoRNZ9N&B+Ln4U*hN=(Qk$aJ`8S1AQea_~Cxg9eqbD_s>UP)vO`g}*5#goB)W5uOjN%bQ)QCwW=Kn6b!r<}_|#$~W?OpZ$(N%h-sN(k!GxC}NZ zp7}akxK41-srqcI9A886QgCAWo0uwAxt@%n5cq{7_(V9Kt%L6IbUpi7$U%OAi+^3c zlauyGEg(E=1Wc#Jr~v=-MnD(Ds9RIdyB~L_&*#eYWIcCaALm$DUoS8YG0b9fJ$oM3 z$KXdCny(rI9LE%1GXj?Z3a=Xh%fK-TZyEu!{x1~XG6H6OPb&ypjQ}@&6t)=wvwo1m z+eW~wKan=J8v&F23<^7pfJy##3OkK}N&XHByNrNI{$2{Zjetr1Q3~%F0aN%|3hx^M zQ}{vpvDXNgv5!#rzzCSJk5l;22$+_Bqp;5in6VSMlI}MGX6!@?9~l8Nb}EIBjer?D zgTg09z>M9VJJ3&!fEl|Rg#$)Fo1tM}s^?vYHcMa3hTWuw?Zk2aS-k+8oDF-po}GYw zPOuNNIARQ7#_mty8zZ2luch#<5zx{jDST%HwDedCM~#35e-ef7jew?~LE#4@py_X; zaLfp3`UMn@8v#wfn8J@nK-1^KasNMzfTr(Aq0|Uy`tB5dHUgUdTdozq7y(VsgVg@t zjDV$>-_h#--3Wdwcs_*_MnI#qr(o6B;6kIMaygGP070Y;VCfh907(kWZP9ez%sPcsrl8t~WUqYd>5m4oiQK)7F)bLsg z8Ad=2Z{nm-!w9IZHz?FJ0;+4yxe&reKy{s!2BDS_P+d!zqP7t*QdUu@V+3r6o~KaP z2-psFr;U0>z|gss8@KvKK$Xv@aJCUJmKIZJXatO<%=*naJPB2pCIGQD|%g zjHMSSG%*62Z8L?YMnJQ@MIqA&7)zgFne;a|g4>Se>U+OO6Qw`GcJ$SE=fw4_+H>m% z*urebtors|yucRR$}L!qF@SE*7Zm(|GXm;w1%(TYfcm>1YkJcYYMw z8v$j1o^HUCnKQjA5gf^2q^n_-qP6!C_BFz%iqNam`9FK=xPMF zGFsL5{(*9)KgG&ut;%?gd)IFD1FR;iLaP6{EGXyaW*Cnj;!?P}vbw+nH< zcc4vx?$L>_+So7BiTAiG_}W-RCBeYwZM+9)AjqczU&_ERz9jTbn*dGI!0|Tr3~aK4 zEBUPCCmD!`(@X0?C^Z#}#_@z9{A>i2;&ImKFGfHqE@2J*Y6NunczX4l5ztyk>p=M3 z2?6SLe7F{m*Dm9hdf&0MNyRj7y}rYAC&npt7K#FG9c{R?M> z7bC!2>StAKjYKJYA>4mjI<0e# zsg`9A#bt;tSs|K><2sX;<-Hl#>CM@nLRrrIRGn66uvJ!t#~3+@gQ~Th={iNR-0Y;r)5WxeZ+8@}r!KWL5ZqwyvkG^W_|^)43K|wv9O z3Ug>HfwnG_bF@z9x@OrcaT%g3R*2>t=Q?G1H{&|J4hKhPIY%pOv4L4OUuq1tr$2*F z_KV>AZ0Bnwc+j77(3AW_jez%gy5?PG`G-r0!#g`Y+CeBXDKNF3#ZEZV2ySik%ko~1 z4AXySD-^1;{gQ>isH_0}q*pg&*{kT)vzSi(H)gq$MfNn0ya^6#StLEO=s#z9WHTRn=Ow}wmf}7`}Ebk%aITSVTzgu~BW4Bw86`(iF z^N}q3S`1aUY95t=vZ{I9STt4hgoLuHdD5gXRr8b)Ox3J4f~lHyMsVGHFv~j!9;C0~ zTJezF?8tr1Gg$!^fNpNcvOl7mPOsS*TQ!?wt7ePI!c@&GMsV|dKFb@AL6ANiHSb@q zJcHcXzM2)FH_UTemVE~j1^07HwcQxNT;8t*gdIk}Tz)0I^zSqR=JFTWvb&6cZWPD4 zdAAWzSGk!1Xe!ob+-;&?y@Yla5E5H)b?~k+W zZdk&C+p9tU)EL0FcISBzJ~ILqwvV`fIcNk-1nrwZ_}mCs*rw8nFO7hL%uj`I$OtG% ze=gvMjR3ztt_b04Be;HlnB^^oOX<&GKjq&qzc+K5IFc1$iRkz7EV}`o+615BO#72D z0Ka>4Z2!Xu*k|<4givY(EZIR$tv?$91A80`@{18r)B!B&uSP&ocXJ&7W&{+q9);hH zfHk}uZTw*bwEMGc<`YIhdtn7Qn&s^Zr_-l#T>YSueax=x$qum0ESWFcj%$FD`S99| z-=BSQV|a-TAz%cQtRb^VGy+OCmMvYu2q@WMj^-pIpkyy&it-1IfRc6N4nElkDB1GX z5Goo0B^$&grjij*ve()5Q;gu2EFs%lA5Nz~%xWl??QR`PS|U(6JHRrtWEt7cX{X@J zEO8BE0Bts$6J1Rspk!h04Z}u2$wDa*Y8e3~+sP`dZ3LDKnfU7%0VR6`_35u`1eDC8 zaF!8JGX5%qzn&3LvJi#(MsQ13HQVb!-%Ibx+D})>hH#ZUJ3GKKvt*gsc6THSUd}Ae z&DOF6uWsiEXkjeEtFOyLXlVp^bxs(~65`-hdCoW;jetq28|S18%`F(p zXWJ0E7y%x@%}BO41N-Fk>^Q`oFE{71Q+CY`umE(kSGIi&iGuuUcK@ZS8t$B1LiJx} zEW)ciI?>ytK-FBy=D6I{CK`-iOX$DC2xzce&SqB{0e+8SXYFGIOs@PDY5!Fw7Zjue zbGh0Gn3D!_a=pd~m|SmQZ|rLXOj5l$YZVy5EqnKDZ&mE0(l;@#hswU2^G3hy0BeP1 zAChfvL!w}1c8lwb0W?ulRE~d`5ztRA4nr7j1hmM0cAODLKxObWt$(BuQ1;fW&{0M} z*>B_6E-?a%`ZPz;Xd|GgJ6QJXjewGEVs9L41h-@Zvb{gBWN)x!gH*C0$KMUv0hXC1 zo04rm2xGx}IO?Vu11MRLcTG0}I^U0U;wB@Y-CMEEW*7nO9$@XvGy*E4CCBzGBcL+M zv8&u{1XM;V&LFoK0X?IIAHuChK<(VaQ8C*H?oghP?cEBe)7P^0C#ht2bH=(oJHRrt zWDB$HDcBJP=T(D#r!jz%d7=6j8385Z2U7fZ8G${TOV8a#K*!KV}4!ES+oU<3>QqcEJ(< z8Y7@&<2i#oVFZ+{H9OyvMnK7?utz^-1eEMS4&JAY;Fj!xZ0}?^oqjWW&4Vi073?7E zvI8tLOZH;6y@4gG%RS3W+3wSX07id=Mcrg9qQeI{RlRHk+>L4Mxoq!e%wioAzo0DI zv6eSy2bejtcr)8hMwx>X@am0!tFquU){T|-_Ma`jn(b|g#OW`fPx)V$#b=rDo$LVf zqQ&>J?S8a)FbVn|SuBr=n#ZEmFm?w~AI;{^M4c7S=&;t$#OkF;1FKKqZ$0BVLV zeVgq~M-NM%!FD|=12=H^|Ck-1X&U$~+irzK!J6EN{PAZ4rP(v@us69($A;;hAPMqR%%uxz#_6Bc@eu65(Qsm2Wl&edb#QR zi1$hwaN=@h;8JGYJ`$j58t4|Wx6;5q1pVDl8gSdQhw;(0XD=h5oXgmiE;Rxc$ODNG zE;9nAhfkQ|atW9j*gh9Vyx-HS=YojqBCmRIVz~mHN?!Gg*fr2w+!imC0laVSw)nLY z)Z$l1y!l9+{w9ZOUs=41tI2hd0P|uwM@8%+S{&92dWj5he#v1!87qMwjew8CBi@Cy z*rF2Rie&LJSn`jH1eg~sPKnr8wlIBYnhdZHIbG%^)0n2q%rJuKGBZt{rpwGS0?N6S zUHxVwpl(kv_gjpBx}9GU!t96+8DaCWi%%PFHz}~sdW;=su1R5f**qh#IV$-lM7)zx ziu8;4WN=cX>RbjMawDMgZDX^oFaqjyLNbJvMnDyQ$KBb3 zrjk*GPp}89GJ?C>-4*c;hmYy!@b1NG*bMYc|HF|0i^GO}Dq`Qlf>fguYfTpDuIL$$ zN4$^Izz~k{CuCqc-G3$$plKS|7_s-!0A@ifh9?aKXI6l)#R#YtSX>|R@=faWcH9$e zkj0nS8m~qI%!?M^j@W-gqTmUR-W@W4FMth(xE}13fVC|6AxphW0=|vgN>25^8Sxe} zi+4~!|JF#=5(Y|{-@B2(4G6exOxbB;+j7!Zp6#_{RZ!}jews0J6C_d z5zw<6r$Go90X=&(H#~_(K+o>NR!Yjzz(z-YlYV2KS_g0NIX}m5PmcFIxRhR!Li(8wObG+LeulVF3O@G+Ye2o@!i~*E$Dck4#9Cz_XIoaap z<#uv;?L!S9L-p`rm4CdL+l!CKHkDLI#u`sr-%(3fW4hu$Du~+9*+W|R&8>z?8kNtg( zfF81%y{x|xIE^IuFU|3G#NFwSaU}H4N#ot=rCdb@<^-5Ivly0RKgTR8GK-=d4PU&i z{3hlZ|41X?z5cPxqSy#HJaIm!i_s=ec-4oK+ZZFjt9^8HtPxzVhU9oZqF0ZylV6wP z4)7n@eB*Kg^p}-ACC9!9^&IqbQl4h|IhyYQZttcW0mExD>vo0_;KYj@>a&ahC+=d4 z-)d?fgJ(Q#%r=5McqZg{OORoDI-hk-%5ewJ9~?=y=LG04y;_)KFQZq-Iacm82H+JJ zMgJlrpoY=F^K!he(qbLXzVl_#8$#gjoB;D;?Jv)S!D#A#TdiI{vjh&!*08KCZ1!O$__&43SqSoP*-7Y7#=eM>Z&3eY>g36R|Obi z{-=!KHrTy6-Z}6w{S6L?rE0MI*csO41Xx5CWJ8YKHU|Z1f!(x!qwxv_S;i7?G6D*6 zDW7_5HUc^t55)Pm7y%vaI@*5K2LVT0j=bldVWjQAg{UN^Jo0#GpPE2*Rq!fOB$zM4ug~Kp8G&GD)Z-n@U zX4MeiIm`(0y})pY@4eMd;b)Hg)7-RmLws+nL5LscY#8F3L5)Iuucb+d?|x*4_+CQu z6z72Aw{Bi7LVTURRfw-?w+`{su2~_zRvHQM)ywlkd~q;0#FxqPQk)}`G3=km^0RGOPlve0+mbSq+H-D-S5yAZ(DM_~#CcMGXWWTM zN)LF9qp93X;6SO5%W_JNQ%8B83@+6;NXoUby(fbUT1QU?SD_0%sVPj_D<@?n40Q2i zaGmJu$>3aG=*i&ZIoOlI+3H$PDt{ivza%GR3~FVlCxbJNm5{;lidDOc50gM2#5nuB z1k20L?wkf4X~Y#)xdL2!DFhzkVBDD#&ynN35eg>8etGsExN;BH6y}}W4UM&sc%Tt5 zE}e5UgN%T2>71h(Yy{g%>ev$>%o<_@Y%`pLHP;%Uyfe98o#(A{0Y6~+pW~zj;b2QV9fMPl4Xl57z&+nXbG_#Bi*vAraW1jabI^mq7nUEKCj%IdV zfbP+W`FXZC4^BAeXciiaLC3(HJa0q9x#wu+$$)c?=FYqTP1C@=dG^~h;GCmbDg%6) z>zt#x-&8Cb#}h_tEjI#6;hdvcVFZ-IIY;w=5zsi!IhqHJfW_50N3+TZc$Vs%qj|^( zcsk;oqj}f}SPf7UcjtMJu^`Slnk8xu=N!$Nya0>Hf;^jN2lG)7=N!%RGNAT+I?vkz zaqc;qbu!?bqgkI9plL2rujN(fP6KyhHu1la7v2gv0cGZ9X>*=Eng*ORF0bS{`=Io> zi1csG3(_>*+>uw|ZYFXL;_S+cI*7A7uk0Yshj|q@A(49!XMbLurMOoIaX!jBc@XFQ zyb2%DmU9qiuWPG1t<%$Y^6VdR8KO)0b#q259d{=2hlCn zkw2H}i#)qC;@rbAhg7O}tD;oj-6-8Jo_zNhUk(NqB*Bj2lKq2;JP|XQJr@) zZH4>_zv0p?RWScgZDr@%wb~&Q=TuD~-)*bb+>}+!57HD%RVBYddnR&@{#4C(+sZlm z6Ur}Zt8jkBVMyd2{i$tA5xaV5V zGb!*|j&tOvwGrG}I6L3l1sS?We$L5vCranYPn-Mz{i9d8`SxOZ0q)zp3aeQR@XI8WoonfBQsDWObL8i8Bbak7R~o@oO&=q;Zg$Q04uS{nk)Mm?rgP-ys{8;8 zKsO8X?R9k1shWYYRWl^EYOXU`n5r3S1UJvV`Q8tir*q_|pYn8${0z$v&>QAil5bzt z(NxVC87QlovBsjQnsE}!s^&(M!c@(8Bbch0XarL=lZ@cHS(NXc3J=^PKcnQPbL3}o zet-p_n=|w69dy&Fnww**W_E1V+-|ZkRWrv3Zl2Tfy+1Ke=g7}Z%F{XWGdDj#Z^Mh$mKXucj&tPa9wXpsx^v{`UL&BcoFhN?8NnR+ zS!x9M?Hu`8W(3#o`T5?*;F5dfXQBLdj{Mx8A7F{-_e1%1{|n)_bL8g{V*t-&oFhMv z8UbstbL8hSBVY}7j{H1s1gyb*k};B=FapZni_fy3Gy=-*9142c2q>y^C}^z_P*mqo z&@)Cr$(%z$&l8E`%g>1!P*1fiz|knq>?jK$L`#1jWX(t_{oDSo^BD*0sB?i;64u-uv3? zV%b&Kvglgg?|q-|d1fZ)?q0w5{r&%Q@$h-hea^X0?`I~GvW+nIzK;szo0jN;?+W=I z5e0hp=58v`yEhMn{GwVEJRZtU-NTD0n4Z!E+(s0#TqhNnW4=y-D(F$S3J?Pn&ObuF zm5714N%AG5sW(ZyVZS6mqS-r~Gp7d8)SD!^VUsm7chs9CeXK^rN_PkItP5m~-X!Tu zfd^AXy-Cu~3Q%wLCP{xQK)m%P$p9-ro7I~n`8E_Jq;euMW1tnFBI`|(K~`XIk_@&2 z)NH*;GQt$pkAvQuQXu-d2F5>P?bKR)Cc0 zO_CBTFew`r_RU75%}tU$nKHdeGCAy*G)u~6gmaci%1$gsyk}7X+w7FE?-)^_7dEC* zfnM0yH|!VHq97Q~IbRffGzbd9=?dnCeSa1OdM{!g73jT)im+c)i-MYP&R;~q3x!Zn zm#!ch_WdXd^!mX9D$wf(3&Vab#UP~a>-B@ybd616->sriuOBp1qh3Ea z1o;jd(YP+0^R#Hx+XmfK;Pq*g+QPoCM1kHmSW5+Z+u*RUUsQ{Njp3Y;^-!R<4K`7M zd)wexD=>*XGVH5_V{_Z!Xlm5k2FHc{5|(H@C7jbN8uu(gL7YYf{fvSW!@iS5f!;RQ zOa*$|;PkLxREvUh!a0|V0=;c;Ub=#_!oEjDf!;RQLIrx;;DWGUREvVG;hgtHf!;Rw zUAltbhJC#kLV?~kxP%Jyw!sx)zo-@k*M)Pc;K-a#-$(`SZG)Sw06mc2Hn_zKOmBU4 z*w-dO=xu}FGYGwHaBJ8vflCl~hI1~!t2ukViwfM^20JLogkw~$KZSjFi$=X|a62{r z5q7=r3;QK3(fDXM=bV^5DSn&^+}j3E*f^rLO_WXBr>p?Ijh-bxZF@=dHhTTw87n|< zGqVg{p0!?(aJ_!;oE4z^xugg#Ua$h0A@qmfMXLk7jUFApWL=mPLA$sB9V=F*EsuvDEu>y=Cdg0*j6l9oazJ>OW7?=wO?=YHr;o#G-UlJfi^flVQ zM04V3L}C{eNMpNq1O)%0z~?ceDcZkid_&gOUsB`YGFp9)_75A;m>J1=TQusWm8^&v zpQY2%ODnx8U^Q|gzN`jl)GG`b5i>^V6^1?$zl0?k2S#$Hz>&GaFqjIYkJ2j)dr;s( zHlkwoi};p^M!mu?fEx7*Lt(@(VTs1#NX}l3wqlN^0{05TxQOX#WreEMZh{rqYB$M- zX{%kS6`-{A3d0mDKxyd}hG|xSoX~nW(<-&~a3AZ!USXJRUD$fKpA{e#xWX_z;tL@a z<_g1zNXiw4K*TRL&S1%kINo@L0ZFfp};knV|kJq75m&58O#3V5Pk74h9B zLF$S6{7A})dOYG68)vWt_aGjgs3XYzBRTItU=FemvZ>70;#wT>^;!gldXT-8#ia+? z2S@y(Mv7}yB&QgT%t7`cR)MLL%@JRfDA0rK7Anw#>@^X;s1^m?k(^gWfgWTZW))zT zGfyT5hg$(AqI!_M!3t2v^dS2PE5IC353-N60<>Q}$Ue#nP-pZY`xskRs1bUQz0nHH zvY`XNY`7Tl)`RR$##;}vH%0uCB8m4&k(_mKWDc@Vwm~4?%cZ%VLVehZ znC?OL8Fb+uWN)!vOl}?*@tvcwk^_Mg7%M%yeHz9*hrX#qI*AS zgFq)Tcsc}6Q6PnLxr}a4Q{Xj)^FYKm1^V}RPo^;sF%suvX4U(-h+m>7k@!m_=U6z( zi!W@%WlyUSVQv`bC-@&mQcm#y z8SzWt62uRYoTK2#oZx#ZdYs^ASb;sk&$I%2f}d59jFq0?_p$=SN>A`}tiZ(T+lcQ{ ziItw0| z$}Es$o2&vkd*Si$EkPa+%P|IzhyQG3JRZI~$m3zz{U2B$yX8X*wnpT5SoV#J3S^&_ z$HNOk>ULCt?4yn=kZsBd1+sBCu|W3aN(yABth7M(op?NaXGp`JS|B?%(+gzVWoCiw zo$ON}8z8d_WJ_XhfvouF70B9`$HQe|^%pLXRbxegEd8nqWc@b3Ko()u1+q@6Es(Vh zkB2uHAF%>it~3w{$&@qh2*PXYdX`>M&xh6A2vIN(Iy-+fi27+sPV;cb^FS z2V+Xvds2m0YO}8dlD#s0^8nl&J9r#?%KJfhR9(UuzH}CTD`unMbb%R_F7v$Y6 z9vVl9hk8s$p!=&4aC(LJELe;z$wBwxzq;R#FceoKJN&=T+X1&uaWm58zg7*I#Vbo- zxK0h(#a_%h{MV}?*YQ^Nh3N+GT~IJ8)4x6E_=E9t@_)>S@ZOP<9iEKLjL}(RVSZqg zq|@W^W{hd=T<7>7DU`T*JQ*3IFU*Gh|1w~QgU`tQhDb`c_4^by1rkZ8 z`0Pore|^|jFk}|b5yx)~3qoaf@x7A$?+%d`pIht|l{?jt=Zw$%7S4U5WrDW=h3Nm# zD*=z(7p0!<|69MwP0$<}1&hyz$h%WK2bIwO#Q^b=3IG2By$4N)>`QMiILMlY|9YJ_ z(Jixo=CweQUF?D9?13mtl-awY<6qtiSd6Sf$&B*<(C>Q~@}DSzMUH2{*yV7Y{|2gr zf1qbT0H)0R(PCHZ8PEb#c7AVEMSqEBz>zTJ<{vLrcpqcxmp^zQOcBq3EwCGyf91X~ z)f>B^`DaPlFY^qz9d?EJol+9Zja`wmcNA?3zrpNG93uaX#D7SkG|w!Nj?WArj#-8J zD$!N<5;@~u^JjeKBnZ?-B5G_TvnEPkF!4^PgrZ98Mxw87AUxCxCEmuPWF2faS(_VN zn_KY)8>#78A|0Q30si+7L-Y1Gd%Wu;rguX!={U^Qa{Vhk{dzYeOGoYnd-Qjb9w&dB z2c}j}p(IIvm(TGZ;wcn|*--enDEvqi9_sNv14C9n*z|gO z){}iciW7CX107xN{oaw{VP3B5;oZDv#X}UuwJG~v$bXqFzaV#P_S9+k4fpJWP*IP| z&O#|1pM52Co{)X@Q2cIt_6QW=N!fRMaYH(LG~Aq=9YEthCHqTAPR*X)4}Uu_`*ZmE zb#~rJ$2mQFd{aLu&UCyVPC-=u>5U`cl3Nf*)4k;m_2m5^ak&yYJlXwGBk@zh zqtG~V3q9U9VB_D4E-ZJZr|-}e_zMul_)m+_nY03(=g{1JJpE39EdT0Ja5dW)ocv~V zI=OR32F(JrH>>9G@ux z_!psF=LS7qiNW~HJtb!MBK5glCT5e?ps$>md%UM#|CNZ&Dae4_6Fnm&ZBG6l%V0Xm zGeU~VlYcN0nY-CDLX>CZKP8bn*)u{)#G8M(7p7A@BScAN{sc+-sh$x-V9G9){w?=3 z&xmW0#ku)cqUGiO+L-#}e^?CD>Bf|oe=T~x+%t@+Z~hAs-kHYKFaPBkFr8&g{qx@z z)7i!}ptQAPjgz~@#4JDma+Ff;Z;WYR{_HH6&M~Gz`HPBRI@g#6=TAk)lY5>q4avV4 z^)UB*V;Y(-H??vvFs6e1A>&}W&@*CBq^L0eeDn~x7kNfV!^H0%q5|dq)-&P~V(1&6S&IL&rs?Yy$lS6;^-iBL{iMZv zPn(SS@$~)`u=G}=qwlj%ajQDqS8S`0?S1wuK1wAg&4VO>0_+nQdKx4n|AneMvro9+ zF{{w=%8w@ZsTi;j7EbZoXqJ5{2Z%*x@i3H2pDOK=vy0D1^!r2y?0~D>;{C)hUk&|= zZyp81f&ufOU|{iLsP0oeK%zLb_^vT9)aOam3ybHWWcn;r!(QdB9ZsKEo>Z8k;?3wg z`oz^@WbvINU}#XosNx({r9O>n7*qU~BzS2b@iVUYeM!wSHHu%> zsG+pr_ejT7$J>I|-X}P8GfZd#_d|G`Q!XKZGl1AULfdP-{tBAFPx z7Q%54NO(;{4#Yd${Sp|D@g9FRrZ2jgyc712Uj?6fKjPsj&CL1{zNbm$_LOJ#mCEf* zeG}#38I_r}$7*XehE~%bK%MdIk(nh?D8=Ks=m|KQq5cbvqfD{GXXYba<|Sj3=qt<| zbSj+A62m^P!fM~q-NxQ05MPwY)c=($o z22J){H`zNOk|fWP7ftsGP<9+1`DnsXUNVqC&v#zmHPE98zYx;%)y>vU%(n67EfP1L z%wbQ6n_D2g3DO(H&D>89F>ZRz6gT)2Ou_FV*>583UeO$y-e(9b{%(?L3iUF$FiHK) zB=sSi7DLC-6>X+q*;uCwvl)u#ZuC*dwYwEg%DKY z!2%`Yw_wHBC9pij+s7mIsPc1^HcXSH?K)Ks#$?Z-u&eqMh2g2i+w{@B@OGzsF9rhx z9?wMw!eexAbS)5%yaJ+Ip!Wtm^TqysWb*>gLWGVIn7)26oLy^tiwe(0=exeIHNIbh z&*#Lq*weQMquBJ3Q{cYZ_}!&`?^uhF&qC#gxLBh61N`m66K-C)N`&EkS0clag%j}1 zyc<;meGVJ%7EjLTHe~#JkX{GtEAh;E8HV@p@`e~5hhaEkJq%BE85*5<&Zx(K-aCAo z*1*Lg2!pVlhiA@w802JLE^^M93&R$?oQ0?6cQ6#en+L7X@ow6`Nd1TVnu89dd^a4fc&=ZWn(zAq#i9T0vC+pqD=5{ubK zLoyuQ$}l`N(u;_nENK_s#XhZTLDpK_i~oqhOF< zn{G2cG%MT1@56XJhkJ55VA8BS5iX9$qgi<|UM>)WWaUG6k-uhDEh#(}{xXK5sF1?m z;#X4n32b+Y3rVH8$gCF^=lEWcf|6AB_n~*kGfONql~Z9V$D^qfKUo{Z4^vqSoB4R~ z(NtcEmkj+6FE*9y;9xBtP3301oTxr(q{tOiAQUsc+8Lrj_3_WYtSfegY9kNTx#S~c#&Vq)F^(9moM?uN{!qGzaIGy zIqpW&kLI0&N26JUm%Z??R&K{j#!v~2wNiEm;L*~09xu_8{^>%MS|zxK8Rg8Xdk0pVHb zL+2%~yz-x9lem})=d*{vW-6SN<8c;#h-4Pw#Vh|If7RUqa5v|lu!+Kr{7pP(UvXC| z*7Bd#r*0CkmyI7ps~Z2In{J63Oh>;q3+S8qY0({aLPaiIV3c8N(a22S01HI3JE89D+x_a-y@E z0yt>YvN>Oi=0I33#ZxCmBaXcCpT_z8oF@^umdr-DkiRMB)Jcx#i8J|6OXmEXui#8m zcQ%}yDb8xenam|T@*kb4lWSmol{j&*p0!cgs!`bi@pe2Km2t52%6}S_tvO2(Z;i^^ zaPg)n(5OrlXY!whu{CECoM|{;!^xN8tVW_T8!sNInx3sWYMqNz_Lh`lv-g^T(DA@f zU0X=!u~;Uc-UsIVNvi#liZQU=HrOkjtg+d)kJv12!++jwRXgBlsjPmy+m?z7XUV+? z)_e9~uZ#l5$JsNCu92vQ-d_#&N=ImHel=HYmJJqNC+3MRXUXN0U|2oaE1iIGwR&nY z#MMD@WkOsXHzB?QiML^}ceCrGVTR1Ujo$sKH-N14Rt)w^UuE=GOxHR3lD}cC?43T? z`-p2ZeP0bx(>1+PL)pJC;+5IUGfez=C07Hv#gOE9`fBT_7y?tqvzf!ZQk5!ygS5g_ zF0pm?UxK-H#;uvd#pE3g`+%%{GH%Pv6^XO|Ls%kZ45xj>wI4zI17yA}pCUY-i)1oB z`)i1bQG~yxuK654i zo{%kDC};r-GO`ZZ6Eb=FzSaAn0(5Bd^xF@AXs*9!bY8ySn>Q@4aY%npKTL=-Mmc`} zT!@hR!Du`C`1keC@<;QLeYAm6-!w-gSz{EvGCkhBxqd%f8P^`zWsigBLO+HSeZlb8 zTVGK7{nYC-dUI9Y2cvtw$M1&*$VEe5AIF<*jM02Q{)$wteaQRR1#}80_&x^CenCMj+9X;b*A6z^b4RB%)=HR4tf+ zAxbHM7OFG2-&0=D>GVZTqf%h)>*n%)1+%eiE6Vir%+3+XvcS|n9~rJ$g`$x-6*FKh zDT&D_W+m-Mr`jj;Yzz~r-jd?6%u0G5m+Bb5y&wd5ALKv0PkfUzJ!RjI1 zMSstLta(Gv4Ql8!Qk`ZD`BM-rVCJ5lviz85ThQM)WQl*NZ?R@EGP)6#`%HDp5bJ$i zH=@qCLPHlzYMJ9pzRz`CTa8$VZa&uI^!NNGSRnf5rN^;IgAA}{Xx3o0AsR8)Np~8} zPfJkPmy&iyC6cO#vWgN^A=4nn7MS2F;ni(eSOS)~Msb0;OsYNA%ttEFi7*ulPDYwC zhMpP3_*I>rX1~eBn%$%rfn6E%5^gbO{)ANOOT8cA4akz$g*~0HsA48kl38&#vrwI+ zqNZh515>0`jVWqmW~Is&F|(+{WY=Qmv^vCCnCiy3SemLHLtLt63?!)~5Y0DU4k$t0 zON--yC606o?RmCraHyCjLijQw;3FM>E*=kNT!5LlcJ0`B2@K}rktvE!Q=GV!VGiEY zr|cn*fgh_tA zpr0DQ@YK6Gl!2=->7NXzRBc7x%jqcE;wc+1e{EWKK(d_D6dQjqrhPCyL0;7hL_wxFb>m`PV#E+f0?FH-c7*L5<4h29oyprl#sdHU%x5Cx z9%rGT6i+Xw(= zP8Q;S{YcX=Yl#0ru&Ej)@ATu*IQ9r8Rp`2uu*KaxJU<(2sfRrr)k2isEJc$PggXM`_Wxhr(TduuDl(G2g9QP?2!*5w4Wee;7}08V=_$Ms*Hs|;<|fI%B&<0kL09q z6rPk6IUW(plOn_)0*7EAp7dnOq^E~}$;ojLPgKXHmk1?ZDcT&52<1r;dR0&kVR{g= zA?fKKq8@XrB8YlS^8U-|;n3ZDu7O0FlW4Rb$x8j8P~;5n<@t*p;2eUjM;IW@n zf8y4D-mGy&g0G>UpC73E33G*mCr78CIH3KhJ zcdiwtQ0yfv`$=^xU5reArDL(5R9UKA-sKsC$F?u)Cp9fUB^zpm)3nB3LbJh?NmzH516c~e(w zvzk{Q?o3|2wykAy)0&nIlUJ>t9OzuJzO{XAXl-Z9q|TQ1mae9*$t@eYI|b!k-RoDh zuC4D}dq_)jch}^2M^opa73|XZF|e4mZs&clgdg< zrc4s+5?H5MNu(s%liQk_kyUBQ|NkQzT}O1K=EVQQVrL2b?`r>v@@;PGYVDdFZaJ*A zxn*)JQX7c};{V@OHs?PzGO3CyI$IBG>6EJQpPh>%$Fx<{+>&N#$(qCjs$I!ynUkPa zCvZvz0}e{W(7d*-ZEd?TCswqqY+ApjJJEeaM@tuE=owJ4SG2Zw!+;$ZloLH9&{!Zt zuO~`SZ4)gUnp--$Ti3RWM<{Pb!%Z}|O_>5C0*=k7kVYP?f)R7|&ICG#_O6vJoz#Rr zJf)ZEDU=8ya`1~II^z!AOG~Fj+?8~;tV%RBH@9?23@|Q9%#aV%#q_RdS<`d`>|u29 zwOXHyC64zjkH_cB_vK^_^kq*3MwSfnWM=q=doRrP_`CxLPR8Xh59Hpr4j1__@9iqj znr);H9PXL#DN3>Md9o(s*g||fa=6DTJG+Onom6&nnzAR7%8Ui{98{8#iHFva>YwAtk;&v+{={B9rkVqW{+%LA^iEGK4$4$hYTw zgg(Oe-E))Dq-wev#yD3$$i=Mhr(j48yCKC5WH$_{zX3Dh^$hdDdv&$^Ovx~p3p13!hW^ERM^W^ZY%6xHn*cDDm~q@^%#Y`enY^r3 zL17l=Kl8=e08hSeBs^D?l=vn=_1+-FbHwu@qB`HVcNSW{w8XOzal~)F#BWlTch@n} zWsLEjlu-h~2=6Hy#n~9|S8y)o7mtxV8{_?bhF0bL`H&V{Z#nR$>CE!pvwK2|keFpi zu6GO)?54NGCSd6(WE=6jcaON1&`(7e1@zw)i*KYizeI~e;^>ua?;w>wO$lve%9ePIJM3_^)& zEgS1SDNCwTp?B92Me|XA;PQF|*T?(vMs+t9?tIzOysku!N{ifB)T0miCKNnZgf#nn>D@` zEq%P3rJ)YY@_ywY{8FC}f|A)idWI7)O#1RQUw;$@|D$~Uo)NvvjcCzINwfEXUbq#V zR*n}W!~6Ju9Nw8)!h^lnB*Q~+W4%|f9A9G!m-H0h*J}9s1KEuk>%tR z*H1iB8;8bdZ6e+f2u7=;%K{D2x>_e(AFFS4>ZA3MU@W{e;)LrK#X_+_sp~OXyC_f{ z4JT^q!VyP84pj%@@kD)~G3YtRTG8)_@7nfme>^gNTP2qq&`5ewA7sgp=xJ=;Aq(d~p=makt`v$nmpdu?YT z8e7=zrnoL1LJ)QJiEyL=<$#P&1hM>cqTzZ3w;)ogaZ7|6Vn{e9&bWykF0F`G)Kyiv zIzq9f^$m52cqoFLLfFt0b1fwodlYGHT?5J{+7LxvFGGkZg<6xEDP@xD!4QJ0E=7RJ zB0#w}BKMs7s-^KrgR6aUv?7`a)F(t`sIIowBq3BUPLa;VjrEb*veM*hS@N|!`8p-} zIyLz^%~=!-G&HCVH$bK}R$GZAn98DQ7H^@LQy;3UL6AY$y_>(G>blT^L?F}l8fpUz9NEyof}v>zRw7PJ zB8n)-8{$q_Q7U!TlpOwVK=ILohBH&babl5pB(?}aOI0bGE_#eWOTyH*FZDMs(`-(L!ohe0GwFqw3w6w44 zUhRY$;tP{?UD^ivf%-_GLDSZ@c0~(f6tsn3T^5UL2yXL=cQT^F61Muaf@^0`gDhr4ir3*Mb*+nFHJV+lLYqLOHUMMTiH49IxQaQo6{utAQM7$U z%BPdFoGz@8?dlafJ>5<1%`MWp8e-9!GQ`xh^6F|g9BE=!zw}>WcEI7XWJ@wV8ahg7iQ-hE}u#HEUg~X zv_;v7*m4O}$0C97QaA5x&zjOA>Z_vRa!2+w&_<+6=<(IB2?s1d1?VQ)a^t)Yr%AmPBjJAm202HPPzosEv3y zhF8o3&~s}BcVK5odqvw#>Aq(|Ivyuhg>DaJl2}pZ#2P|@>KfC9#21CIpK69t=3#Q| z<@lgOTups-1l^Sks-Yf3X0SR?yC4y&ieOA&qh1_th}5!LqCQK;IrxeHU|LJ<=v>>; z(%IeG(&bby3YUkfW5`T1;z$QwCLL4+oq8yQxF<(X>6Jx@0BojdY1>TKNr?;&Ncj3S zE!Zzx+u^zlmxpC~qf@lna3m%JklO)A+MAZIX>r|3r4Iz-?%3#-rh{q}kC_n_QNuip zQ;Sj)Wiu5ELb&>HEs&08nK>aQT^QoJ+Bp75rod?^P$j9W2}vQYR2S>pTHLY5rZLh` zh5j1}k6_SEusiQD1ncY#U1ez^ys#k=u4>SZ)SV4kRhWG=Vs47z!cD9CM6E-&trJwu zBQs85yR zxvd~&giHi=s9BD^{6n#!xxT$S(blxVsH&2w+S>M&t*a6%ldr4OqmD$EVZcFas;Ed# z|D@qY%1p->DVyecN%k+*;X0j+Cl=LJHz4(nY;0<5r<>T?Jd^sj`-HG2f?g_ticxE8 z{wghSl%zI0Gy6-1o8CQ0PCG5?p?OVHmo|ekRBLUT%(O&9jB{U|(AenM%3iftrix+A zKd~f8wvl?wWy+n%5{#W@HX7k@5aDnTDQB*fPwU|=q}^SF!$JhZLa-thF^wJ-#?(># z-v3K2+YAnG&MP$TVD&QW{HC#2rkb zF!Pj2dpufMYX*SG6f+@+U?7lsg|!y!p#tw_64a93eWc8;D*_FHYLf*{&64_fGCexG z!u-*}v{X7kGgC41TxocS215CXNJnc!G20<)#$cYlzP+n;ReQ^dB6R$nPA5tO-Oaj$ zsF$uErKNKWtac=yVv;^HMC-PH=LRRBZB{aSs`kV(9me`oYKUZ)gSCica;!dt_AMok z?7~cWQMk;ECfYATVl!XX19cUNnn+DuEIG}TYARz&yfKc3gYg6vBst4WjtWu*nmSih z=m`iWSILE5C{XM6gf&=V2kVwN&;>PX*Q`L#(RC;ieOSvHHzKB;R>&;FtqGFMP(^Zf zYAY0G2(nb=>O^{US%p;9)(0Ev0?4qg?oL_%%Hpj$vRI39md>Ta^{6+=grF~6gCs~W z)_s*4Nj?WSq7#UC;!AMi_3uED8Tr+4*rfLPc|yMNV1TBFB1XJ;sQmJ*9U3CQ&kg zVWgLO>pFI4Zs7ou#a$7qusLkzR#*+$IeS`*l}Wx6tl>JTVJQ}ZnBOCcm_2qiceZw5 z-S1RHm!JSjlPyC>t@1>0DQ0bDJBcFgdSG&L5;xaWyf4vTG2FG@!1BWA))=Rlp7rYeJchrjmV_8b;Y5(XC>h zD?%)GQJy_gRc2D9b*MIo;*u^WfDV0;ne>)&qXjnXGNnwT4YhGMeo<75ii&6`s&nc3 z0O~-aTj$(TLaWlAMpkFiKy|Ki827Sg1<3Q_^kQ`87e*J=CgDW>9M z77&-7!iHok0w%{1RC3eFnNC&GXPrqiPwl&9CjfQ5dCl6c7H$hvC5y&Pkj&(+B3g|_ zuuSf3H&r41sM$)Ws&P=0x)V(+u-BkfudDUQ7Mq*eV5e(?cH?1(ZB$$=u@^*^+R?Kr0Y#q8oO8V6H{U%G8-nL z5Wf2?Dzsk6>O<^zpQeE9x z9YEWVr{;-#HpYfm@E zYC>ol*p9*uLhYhx$V_Hz?A+kpo}tGED0UtK3pnMLcwq&zdp(l29mYg_QMg8z>5|GR znwRNYH!Ihg#dew5geWspK1r3VB;sZkD!F6EQN%mGR66@or?R%OC^TzUk=))XDJzou zJEb$rrxuOtY{A;At7UxAq_*ac^>c6w0&QXvu0cT1y?TAya&YCEwN2fVaQSBrCQd6v z0GBH}4x2Wqt7FoNvgwdCbvCb_gKHIs&79O$(uVs)d#~u~*n4G1(WF&Hlj_QgCSmbC zrx_8Lw6YBs9-3CQOfuVob4npH^Rh`YFN102`u1kIm@%mf3nsas0ojVC?k3mlmYbXt z#2RZ&c`rvp{f{?PQg54JY(}#+EhS~ffgOfgt<0tAGwM)H82feD_s98wZi^#(rJykK zyAevRoFr;?d&cy#A?f1H6w^##-8z)Aryi@Tiej+E>a!Nx$DGw5k%`!nv>Aq}Nk20s zkr^abkByky+g&^xmeln0eV;HIV*`c_GrmY&w{EdHlRTr5l7Xnlfjw-HI8RUM4$baiD<<`_inU%Pw{&_GufiNqr|VKJ8meot zWsRjBX3mmc>zrE)Ji-b~#lafBG9}+ME{kK)2HC8w<55es?9NvwCke^TCsbRvPnY2q zW}ZJeIPpl1cbr6F&4}5qrd4KOsEt_EW1@}-a2_ZJH!%}w>}AzsGgOX7APU!@oF!9q zBgRdUZZuQ`WDAwk0aLGKv&oT3d_`#~iQ}s<_Df8SX^5rfOG?#mY^cY|#%>wdjH^Xi z)?ruHWFWVd;+zPCW#`k`fL%({zcxx2k+QT2S72)4#+ZkGH8@0UG|N2Aj|voiyh_?9 z&hPYCuOe1kEF#U;%lgii$DIKIPlDLG&PlxDQz8n>tM>5#)ja8#z{{|h%|^-NOEtFTtXLe&(p*0u7OOvJDhbW2I+ ziX23PQ524u+~`!tgMy& zTPNPqjKWN*dA71>yy7zFmR*}_9DKSti8BRTLO9@cUz3G}T_snVEG+CTxzg#$1lS2p zdN(Z-5ZMoK-PzexAXeF^F}D%L1WB?F4a00NI_>M*?5fjA1$HLTZ3_FG#z@h8e!JvU_-v$N!>)U`GMVD>?QW-U6R9k zpb@*%wGGjbIkwQ6U#44Wi*X7WNghM8!)dHtP+PaS7EMD|V$zwXtS{(BmRT|-kfMy# z)-_gEC3nYcM}{R0k}7LYg;TB=qiKmVk zQ_T{@bs_s|-7-Y#c4F!we^qjpB^@bGF2gl)YooR%s*|OV99hX+etox`dZX#4mQ=J} zPpUKn>ZO*V^}5q5jg3yBBce{1*P=<+v$Fe;+!L}5NxKn5H70qj8%|sWl%l$In2Q^7 zD?}y)aDqxT#a61WmQ_;yWVUTa;*@1ta-erMbaZtl4r^Moz6E>M$UICBaHbGn;KXDm zC4-8dI?FZ(wmTbi2NHW*dO5>wqRBOi**wr~wUpG<C>2p))=+ z;_DnMrM8+Smh7_1)dlP{cDJ^*n6fvervsC&f^Y}C9c!O8Yui^9Njr2q2#hAE{K>t% z)F@WtPKzosby9LmYA+rvQ0o?zVmr5{9v25pPa#cBuGPy9W=r?_4%-S4z4Ww5@9+~- zR&(m-x{bvHSoCRA#VnrFT6I&cQ>hrIRI$=B^nTsgi@+%)@~O5ah!{q()2(~a2wi3^ z=4w(Ej*fdIU8WaiWWegy#?xJs#v+x`IPyvs61I!Bj@-*Cn9jMY1gfTo49&Gq7u_I zrxD>9pBhzNE}#KM7D)neXrmR+W*Vk-sNJR>rVR{92j-qoO}vuxTwPkAh&x)Eu%(7W zhh%ij_<&&^^XbNjode3=U~Dmt1d@%2)7`X=YOyRj8mi>9S{o8KIbH46ai|(oacuU; z&KdUi;IvuXFjl4B&gHW}S;kppcXfw=jVvZzHKG1I2VM8G&=*(K=!FDnTj3g67MPA&>ZQ%Eczsk(d!x83r3VmJo>E9s zdCY#4G$g4*dSaaHzjQd5YWD6^`Z%1-h8%4~&hEE6LNVL`k^^0=im`*8cBCtvBYF{x zW+@TvxdD+9L1d9$n$hi$>L_{vw?tC12L&V3XFYlEa?>yImCCGBXgBe8;?8!HyqPAc z$I$_oJ$j`93v078hsc_)-fUvYVM1#Q?q?;MVWCcIl6jVTF(!=O54~mDCXpHbPz}t0 zlh7g1#t(O6B9&+vW;9ON?R4$lHCVY8hG3CoJ&>?RAhKlB>6ojCmmwSLQPuU9m7FBB zB;?yx*dRwQ5n0lJ@krJTm?&Xbkfl<+)B~#`r5vha3*0LtW-=^G#N@ak{uk=l;`+92 zxH3>vgBwCTij?8Jx}L+iWH}Ow+-;ONpunUi+hsPyDKj+8b31XNLPlUWer{RHu5x8e zE@awuk(@xe?qo>8SuVEm)4c!ai8=as13RxOE%J!?pfz7I_rtx@C`GZ&SuSEUUE(y zUCjm$8o#|-DKo;f3atI9^aeOdt!fOqo6eB9*^*rPU>h`AVGe{e*2rda>qriM7Nbxw z@>y@m1IKbXa5Q(Cb!uS_S};bUSZA7T+4vD%4Xv1wXl-$uF1J|Zc8s{y=>`t-WQz|6 z;97E&zwu}P^ zXVc772oa4_Oae^&WbuQA4eDs^+IBgVkULgUyOg#4cyfawWq-l#wWqi_=uZ7o z&jqcLX{G>HqqoULdMzrsw`OC6Wuki_RQhbY zR7}>1s<@WDsSC39tWG_QWmlE9|7UfJJ`6bewF8XKR%~;y0&`2;>_}8#Zcv3Y8JQ5( zqNJ@moj1gLPCIm!fC-swyO>Meu7_lk*5ieqJFKazA6+8JNj1BBz0Rf!DE%*O_8P@4 zBy-6pS_|hjT2Ioq^wSRlQE4&s+hj0@b{h~eZ;CetU;OW;KXrnOfwsr`?fQx4vmj>&jMKF_+?(D*|w)SH6R0mM3DpL!g^;DI=%$ zjpi1ejkaW=-qx@J+0@d>Tk6@ZyVTSj3{`{66)AT_0{P*MqW(LWnwDd zvWYJ;eZN`WOYj_9a7C`Q3rF<{y;hpi`QwBXNAGpb)E|cKIDT`4JB=;_eXsZ|&3pKsMu2%2Vo` z+f?mcE$N#0Z6uivmnSn1`_w_X6=EkN$p$UkBG4_Dne0f0LXk2I^74KVm-mg?TzL;- zoo39_%#})WaW7bAZn_6?$ZYnroT>(0Bx5!j#74SoeA%y982?5MwNtsNQ9*NyK4`wd z6r|=^Sb;`U>Vz$CZd{pCNhaDIBtjwi#>8S-hU#}ia2?fNkuqNxh(;S0x&BhynoNo1 z;0)6zj$2rZL%GlXpzC0`hzwD`<2#HL{*YWvpWInSS0N4e|zQ5WD=E zOZ+}YkT*wz{6aynd=_>aQ%n`96vJ{Rp!UX?7V!FRmIYc9SR8uM4NlSoPwYoD@mSoU)?UIKa9$7TH5{8*xu?^5}|<9x?wp5Q%EY}57NH(=8A%CB*y zh9kdnm1-`9IrZ1G|&+nvsypFGjd!M?O@-ZLzP2}Xq zi(ltS*Po^CH@HruC5e5pITC4pVz}) zi{A~vi$4XQuD`FwXPoPzulpu1UZ;N#_x;uVMAub+_szJ^@8LdQ-50v9^4&M%eqayx z1ADknZA}uNK|S0L>JfkZ1=y62*BR2o{g58|@q_y*A1_)_dj1UU;XbvMNqq3P6jDB3 z2Y)Ry<>S?#NKFd7X}_T-{)>{9c=PISK_*3B{XM@_^O&ST-H+~J9_L67ORJH-X#m>8 zD4In$0QG$?&C)jwKz**IS?c@%)Ys*p{YXD^1Rl{RHG2T+=P985h`s!VtJq6T9)S9J zGtFW*0QK=PnoHH(*LfGTA90gxYv$Jsv!G1$Ngp-<^>3IM_!0Nzv@gQ@0Hjv_;G8%y z=7G)uG@I}SIo)aYL!8ZNW|U{@ealhZ&Zrf-D&(Y1=S!)A9xFGQ%eYQ4Fo_wLRCP6F zSIYlp8YE85H)`buu-W8Hzi(z0Cck&9lArum1Z;lt?ymUQ?W?8fUvo2FI{E3kXbHgci# zMHvC}%a?o2GrxW*?xauKE3~`4)Z>gvW{k@y$6tLDGblZWP+D{bD$fWZ<`SYu*OG^k$B@#FMDH2omE=9-OXP>-r{q`UzexFgNzv1b>_g_01>|sY zG`TlfM$RDTkRdWk){%|m{$vxmifkjh$Ro&KkjIm!kY|$TlJbWmB|X0*uOV+F|480R z-a|e_K0(T#c@#abkZ+RjlOL0xlm8^YCo?hC5dVI109im5kz>gcavC|C43YE6h2#=4 zL9Qg*$Zql|@>p^+c?Nkdc`@;&ln@*m_kBnB%}@5nrI z5LrkTlM~1?QvPVF z8+jLbKlvE>Ecpug7Wr55@8nnHccd2`n8dF)*`FLr%3snH`!VDsaw@qm86=~m{CyGe zCx1p$co5k_t|7a~BgtQqCy}R<=a9c8FDI`hZy|3dcaRT}Pm(W?uaWPPACaGvyT~8O zEKIc}9r71Ag#*c9&k6!}Z?MDjH9Y*PLVsKn4&5qALFK z$&q9kIghL(+erD-lH%`W@?b0h#k`KZiTsWn>Nob|$<^eo~m_Qldv;#EYJkwG#}t|gBqw~$wmw~-H# zFOwgV-;#bTZ6&-yauPY0tRoL5*O8}@7m&A*_mR(&?~`AXy|7r3@P?A($$iKLInmmF$nY@s^j=YO}lKhDLC)pPZU9CT){4q8$*O1G|PV!geCFFJF{p4HZ z-$);}9zzh8 zB6F}LmvHwW_a``YC+{R*BHtswBl{GZaQ7l7lk>=h?D6hZXvHA?;)QgKOi&kXDuZE`jTVGnPik)MjlF@NNypoBOfMTApb`G zK=vJO!Yd-n$RHUfSCH$;Gs%m|+sJ3hH_3mJnMEd?LUIBbA`d6GkXy;y$%n|d$bln_ zzA|zyxrkgr9z)(tK1sewenu9LH2U@s zvYR}f+)Ca+K1jYq?j*k<4kyakmY2EY#>|6!^jiK^T=z+JIKe#zmi{) zx#LZEdy*yOe&qh-YH|~KCV3h82l9UM1@Z$jV}c2%FFBT+Nk++KMdT`S1G$;JfV`I6PQFaOPkvA4O*G*RCrily86%s?Zt{5Y z9P$?OZt^8^C;1K8dy)xn7&(!gL)MZBvV%O8JfFOoyqA2Ae2@H!%qlVA4I#&ov&i}6 zO0tVQg}jKoo_vISk^DRPBROoc32z)Zk6cK$kw=nek-sDFCLbr?BjwLi$vE1F98Ctu zT5=_MEO|P)jeLZBpZo{eyNu;R&LG2N8@Z7@oxGI1nY@>Lj(m@F5O<9~IhqWRwd6|j zB=UUn_vD@AOXPdxcVwR_CY}kC3mE z-;@6RjK2bMEV(ZkB@ZMIC4WJlOOkPM{N8UxgLViI0K<*JT z;f*EtBljm)lbguX$ScS{kdKpt!bV>iIhR~SHj_t@o5{<_kI7yUqh}yFk(@;?BopKY z@*eV8@?COph0#||?nf>rSCdDOCzDr_e;^+tUn74Y`&KgDWDU8D>?D6hZXvHA?;)Qg zKOp}}7E~Gi6Ub_EHMyQVjl7t=k=#MPMt(?oqDJokvY4DoM#x3vDslt4h1^QsPCiP$ zN`69qPv*@x;SMKD$p9H6+sUKIv&kFD?d0?1XXN+fpam=!axS@uTt#jmH+%T$gjw(TBC0yIhn*y&S*HzWCwW?c{zDA`3U(w`46&pozXLl zoJdxYjbt0Sk-UJsioBbAmE1|n#WdZABqx#kkTJ5IJc>MYhbHXOLCoQt}Y;1oCY1T5>!2 z1o;N}De3HQ!YL%jlL0bDwv$JZw~!B#&y&spMqfF32ze3tJoyg!8CiIs@i&2-Nmh`{ z$iv7}$v=_LlamiJdghY}@(A)+ax-}bc^>(D@+R^&ayxk+`4ss!`B(C9wAF!32c z4kh;@N0EDzGsq}eM=m0llilQz=p1^3UXB0~9jluVE-$xiYY>!UNe@$LUUQPayyqA26e2x5&{F?NxGT|1IVUkc&xc=Alj&k@4kRg_;#{*m@~(EdJ}pA?om z&WEJ0)tLJT_rN`KA;OtRmeD>)`${3gYasF6EA_XEX8hoU+8-f=o@2<9h0uRG?JuSL za`Fb+|AF@RQ~ogdEbU*S{rfb3CPaF635VdG+aV_0A!Lyd^3g)XyPTXyd4yafM0}T# zD=9xz2!BUYzKJ}U_NUYSJeq$eM0{=(4sx7Fh0yyX`5f)vr1@R)W6D1xe;{)YHTnjV zMdUbPzT?cGIV40lm1H&T52F1_VSmS2PxCK@aDO~`GVL#*{bj;D+}ES|E+O3CLq1Es zNWLkA`}c&%udgWohRj%F{AZDU$$YX<2>&C5@LxvxG;%H(Bo~l%uiY@-SILE+m(c2a&6U@V`a~|3_24iQG*4U(^0#$}c0YqWmVB zZzb;%Lhrq_f0FWN$v0^KF8KxJ|0JDu_%FftXUM+7Jlq=;BA!K*k0K|LW#m5OT(VM_ z=Q!0u_+LW#0VIBoR>Ny0*9-F;=SU&kpGf&BnVd!WTry7iVzPeRF zMfvw+-a3=M0c3#?>6;)#_|t^hjuWQ2PKf-7lS?UIA@n&;7tI@Ke=K<-?YGeW63Tx^ zUPt?z$pW@*l~*ohF|77n3W_?6fV%|1^EF-6p3&}?E zKvKVd2!HJ~caodP$A>=QKxxeGQO1?vWK>i@i!;@i{L-rwu zki*ECq<$|D{`7l+U?t@Zq<$|D^5rz^_X1(o?*)SEDBnox_W~i;?*oEcDA(`*!F&_V zeSc95S)^C{%T_2Hj{^uN0P^qCy?io z7n0YJH<9;}50bA7@w`p$BtId)Cch;;ImW$@94WI0(u&L z>2Q9NNoJEeZ$tcs(p*Ruk)z0QI+(aHnoPVy7-GxAGPehN$Kbtaij=92x$f#guKkksF=fd5f6k0U3NJ?E?QC=ZkMWY2l) z0hAw1t{^*vXz$(R2J&d~B=S`93{vN_@OK`~7m-(!*O51ox02h)?c~Ek^fQl>Pm|A+ zFO#p4JIPPT&&V%HN9K{xmq})mxnw_bAX!9?BFB*v$(iJAavm8b>xJka^>;DAB{UyE zt|r%z`uiAg*G=;#VX@;JN1jCL?_@x(^K9@U$}c4^C$A>2Be#*;$sOeVmH0j_MEtJjJm?I(OT2uDtHfsyA>uJv_t9|%h zt!A}XD{19j*^-NF*>b~0%>_$Z8Ecy*Tg@xU1qiZi%LQy%NU||q)IdTgp(Ws80)ZqX z^cH#xgd{*r2%#haQeI39ArK5Wq5Yp{%H5Sr-n`%Y`~KgzKi$1^&&-@QXU?1{x(oVA z-a+?$-a+T49Na-?TrTdwUqJslPmh*qzh14om7ZsQ$vx9aCU-a-Eq z{XE1w__#nnU(7rB*{z?i|)a_><#EiGJ@Ap5I|U_?P1Z zp5-_(9qSYHM|jTR{V)_N8#r;>VD~!Q2m951vq{O{GA@&^gf3e*FkqDtP=>cbrQV^% zckUko9`VwxGW;U!A!P;zxA$4Yb4I?1>(JcPySM&b-mY!wY<~H#kq@i;rElOGSz^SC zwp?NO3a#Pq)f$#H{O8?=A^p<#Y`K;BVy%CJ_t1B4NxU0+*6rA&e$%Q+jjA zRIDIdx35os?8cjpH}ybWY#vqOP{`ITy*-xBg;`i-_;GUi!(?f-HuiVpXST}flg(w_ zgM2oE!#BAUu0?*L_)af(HlcyZ^{oQ;_x%B`b?6;QajJ2;Te%T$V1C}HIXW&Yw zYe5n0&*o$BoeDrYzRhX)h{xdL+F&}qgTTjp^D+3imY9yOFAX226E407kWR-(g?|~o zdq?2gm4+`T4c`kR@cDo*A29PV{Cx~SI^80at1yLdH|0J+I$e$-&?P?Vnd`GgFMQ`( zI=%+rOSdh9Z!`*}2e0nG5H^Z=1K9+r^it) zoxj__-w!ZwvOUJ)B0k#BuSejUcp}aRVC*#?WXlg@Z<8kAt+iEXV#KJiV&W$<~?zf2u~t=|IQB4+B3 z$>W-|1K1J`Up?8jhTsT@uLPIDS2O}&-i4NR7vdE2G588b;Cp$7E$8dRHwBl$$GHUS zn7;EkIzIoO%6yo|t9(ScOJB0AWu}lW!*XF=&SbrTas|xLA0zrAluMVlVy11qfimO| zA&SdiBg(-v-6lAIV5bK8=3`Lvj-u|T;uWl~gV-!U7UCjZ_IuIBgU``7oP_N<&ob}c_~d1m6ygG=7H^I&4_ zod+9+?mW1x@6Ll2kG_0i@kK{nH0fXG{PR0^Sf!Kxb>Zg|51igwI&{`;_uMh*U*{cs z1m72YI&_DBC~t4x{v1!}z))+>UVGN^kG|;7d1T%4^~F-eQcG`@(_8qMpLHqJnvsmn6mw5t5O}N=pkjow>Yd zDE}d8J!xOQyDvUiVo5&U>$9$XzrwohUqkOLaeNP1k9;vDu)Oc?@#p0=+p}j4S$q2) zN~f8BU?|~zKI;A8Ma4teP~Sr@mX;)D4?Xl&-x6Sa#E@BZcc3{lG5b8vfzzXRez@fH z?7iNX@BDD+bno6fKeSHw>|OK_p0X^072xN+GtTuD0n54Gj)R$QDTO5?Fka%y zdA{|4g*u9Ysx>C@?!GaJpYKaiVTzPU@l6RQB|b4{A$Vl^xBDo^#56g+eqY=-4;;ir zb)rJ@HT7VI|HoR6na|IZT%O~bfHLQ}Wnu?2Wf|Xl9^X%3VQ)iTRr?1qanSb1CD8q#8}D0Z}u5m%fH*(RC=E0zWj$+e?tksE%Y8(zP6+PKHr{_v0V0}M^yQ@ zj#A?UzU>Pz0OaIkVe_`ckW=>z+dGqE(%l%GGiDbdbg?pQ-&Dk~85v?fhJMdch$}Oy z$0nJRk=0#}Tc(I2$nac<$$LiY*saXT%(`w2Za#4@fxfJYsUVvv_;U})TR=pAL>%KO z3UP`eF2a`=W3%Ns1qD4*3lfChKEWpHHkt(}A+#}_Ihc|2Pl-ygwbrf)_es{6K1L498fmNT+^Tmbd?ZUZ}x?~lmM z_I(d3@cZ6CnH(Qq|CZ|;#6m}&Z~Sb8)xHxk>gM}CN6Aq>XC_|y?R&or$4z~CC{y68 z3t`LC_W(+c@m(^5+fz?fVsXWH)-;5GK2Hf2UVMXqkM}La_XOV)P{2eVe~4g`Zy9n+ ze6K^!$-Y`pnd0jJwo>2b$yk>0y@m8NUq_W?ZSV~tqUrHv&ckwvZyR{{xoH=9S?b*^;LuVbIy;)Vmfqb{+y}6}Iyps$Oh6 zIcS?pZ08oJ?^4@Yjfmnh+u>T&<+gJ>p02Q+p&ZM)(ss53%eQQY@6q_S?R)_(Uu8RQ zgT1S5XEdZbU^@}qKD3>iQ2is@*#PPv+YVpwanN=Kz}V^x=Ohq%FvIy6EWhP(4xknO z>T!BUS=N4!b3Ew1?QtGOX!DN8nTC3Q^Ef3?#=9P;v;aruJkESH)q5Ui7s$TvaVkNt zDbw-csX5c(4tz_d^If!lE1tk$Tc#6-c2{IN(;#~?(~08Np6Of;b#`PrL#WW1>9oR% zR%SXY53}$xTW2?LuFiB0lv>uBOy>e9^~g+TTaX*=4%g(5&UCJZD7R%g)1kov;Z&pE zXyIH9CUyzuVLx73FPvR4my?9^3oK~;UN{4oto%VZ&!dfB6V4ex{km}8!qXeVnE?j> zD4dTV^q++DGw`xE%lQV{@A)i;@96k-mcv(CzmVl@0=vJ-az223FJ?K1p~!Eu9KQDW zr7UM7s=u7&%z)6ZWH|z+^Ao>w7gTqj-w8m;_xqhE(Qps=owIW->)L=b8&>q)fHM^) zcwNA`1uR`3aLz$*{9eG>gOWD{oPVLK-578lg38YeIXl7G`5|W_tUiB+vl>`N&2X|{ z6McowUm)M{g$}s2`U{sVboKWa&L-X${bbbe? zabls92_>I|JT&pig$`fjc}k%(0WzFg=yb!DPAhcywwu!norxecROmE=!Wo6mbzo`9 zZf6(B*6((XK%+)>JIBKV#dbSQu%7sC=MgZN*zFWUgG+Zi*P(IRo^ZZ~ycJJ4eB;g9 z{mv8U0p0tZ0LZS}?|cD$uHWwz!WnGX?|8vd&wi&FGHl%M)PU1%i|k|$7VE|_^u@_1?lZm-7m$R4{ z0}DHwi59f$IZW`iMdvcX_pE-Ei5CF5q>Bki{7okKYROBPxCa7W#>DR+)a6Wk8$zDA z9*Nh`;3qNhu>-XsLeG8}&1^H#37#{UI0~BNPoHGJ3LDF0;!hAzFmW-=#>+$}x=9uj zEr9r#;0BSy#0vC_Y$o_BVm}ifp-c`FB_Nv1#Nc!|SSHRz`v#aeALf$J#4@ltiirnc z9YH3JfDS`U@LiGxOw>Z;(M+_0Lvo${C;ERT9t86lOgJFHA8g5<4!g``0-YaHAkm0s z^)hh)7Q|B7Pry8FCa!=sGMM-S+Jf~gKi}M!*=u`#i|3r@@wE}Pa?e8ozsIr?X+eO@ z88SH;mbZ^N1pM2tybSRR;p|0`0N)NOo)r^r2i6Qb%L@Di%!=m>09KrzA)XTA0~8(= zx5U$;h($-myVhA^ukc?FxCMMK2`2z;1zv3rg5TXisqgpKSqORV;>aPkv z(OP+#;-|vlxrrcovVz2vVfn8?mk_@f9#$622AzGvIS(nt_kP2s;rkr}P<;Pch##Ra z`TnnTzW*-#M*&WJAHnqzpXB@CaK8T`#C}!>-v`q9{!I9ZmVCp3+Ayskd9s4U1io*a z0e-&_9#$62mQBR-6|(X2EHB@UEC`TaGCN|jGc9iwa|n<*N1Gh4^YUeGa z0)F%eac{M5!hjXH71E3Q3?K(3;8eu@2H>{>PqLLBFo0|;kd6K-9y9>Q3QUKu5f2*x z^!pJ!gLu>c(818Kw^xf?c&N}HDe#@u(lSCTVgBOrYX3&?MmB$5?Hqfq2ybAQs;x&T`-z$e4pcioL7~7yWcnkG zzyqeg4-X&?8pWblAGXwBi zfzgKn@VNm9E8r!6Ul;(~4Fq|wTKs{6@Kw6vAG$eyMC#reKSiVIDadSUBELqN zoo>(U8Zi+q8~Os9#zb$DP<{}xJqksze-#$6W26_Yc#R5bB?cZu0b+LmaHJr zWmx%{qOe9hfOO~=)Z*BhqGymhnplW%VNLEE%>0Czi!^gTqOPh_%q^)Im4yyd5JpK6 zG0c6F%^yu;E?kp46~#hvL=9rGW{%j&-257+7MVe^Vg-p#GFMR}7~+IJpb=DQ=7@#N zwbtaG%FN%8?h4J^F{AL1Ofk2nX4Lmks35^YM;YdL+DROp#$0Dj?qkG-pO3S|D$N|R zley*^=Vc^=WW@>+on)@DMtq2L=mAQ)Tr)>3Y_W|s&PM1da2&hu=9FCoM$vN|s{uCb zc^|89HGnK@Omk$FC3-a=Bhwm_j04bTO4wGQfz5He0Vr*(s}WxZ!O%9M+n|l@^BH*P zukn*la&=;j^D4RW&H?=78s$8&{2urYtWlg+GeLS2JHrb6oD;Uw4GGXZc`g7$2B2u} zs1aX~<~a6{6Ew{ndapBT{N#o-&#!ULK=Ub0d|e|z4^e`D!(cRmU!(yLJn%PQ5Eq*g z_}MalIRKX!K!#S$r3PSBbD04sHqWUMH-dxEiyR5Qs@Z%AVV1bO#!msr=I$EjL$WDV zbInNAe0QX3t}`TzYOXf`Me|!VVjKqi(DewF#Z{W-iPY2gYW(DeG=Eg%>_#D_nwvEO zS2ed9j7BxLYk;eoJ4^|qnmY}^sOD}1Fsix702G_wuMv-t%~9Y;{7|#m%@(}3#!msr z=EF5kKDw1s&7&h#^TbHi{M3*zs(I1?6wUio3Y zX$EPBdkq5k@)I~NJ#PT;xMf6#olu;x28eo92X57an(Rem6!{^}!x0DK>X{vkd#0K^%4sH=kp zfFXM|Y5vmy(6QHX4F8t_K-A^L@reOI)Jy1pJ~aS{`Zi_%%m6Tkf53MC+yKz-Q8N66 z0e}aL0Pod^)4_D82*H*3hn9>d@`YXNr_7YhSL@72;1l>WJA8I+DlmMDHt#n8NXFq& zlD z2B0L%tQBj(bcnAR7T#JFI!v36htaiu%1p^7)H-=E{=oHA-b8}{ZI)mYO)>yT*3HGlKloVXfe$IAX$PqrW*hxdx-5m z!vK_IMYUocm=3KeN8UIsSr;WctkzGNDOp9Wb0#I5Mr)i`tA{0UbrWgMHyFXyx2eqq z1^}*dIW`_{02mBmCv$4W_epax$Hp>Eb8`tEs%!n^hBTMdI)|Y(15rftB4Q9gn-8It zqFb!lypE2sxzIi^|b~7 zCv^lviEaZ>vbWWWWe_X$Yltb5TJ|uVz`9yLwL;mq)H+{K_J7jDA7>D-iRf{*8362L zB8|1z0MH`)XgJ#q0LnOw{^WQAfb8$GM85$*_BtBEpaDSC_vw#!7yv~5GY$R(1At@? zkg;6`pd{<56;pvaG>?kfq$N9*LGX#Se#%VA&Zu=>L7~6^9phOB0VK<3&pq1!V0;ti z0dS51pxyb)Wa3-{K)X*Sn_o2mDC2f=b)Er08831oc)kHZ8K1GuzGeWh4E}qY___f= zJ40mvTwnmIE1y~`KBr_?vMZmiCHpx$q zdypo6tpO;>E~yoqLxsM>dDx{|vOhy0ab2ySGE=f2);ixnn+B>l2K>k%fMi#(YyQ{( zAlY&bJvSQwBs-bz_Z9$an*l&F9;yT~H0PZvZ zNVbxE++_etvKwl}9bh{2S_SgHuO;I@QHpzN{gj!KJyh$wN6Gy3T94GKX@VcU{}PgT z%wUAU_p%WmHvrUz8@sPojD~!n#kBDUGztDbjd-HgPvRu;i&`gwLIJ@xenyj^8~YCJ zVzpZsHBgQ|{CSKMUv!JLrpyKx$qX(TDJpQ^? z+((SE@NYE6IrQ4E)%r<`7~iaQ-Xz8=*?ezl1U_iGjz+cL08khh|5Pjd=x3qdRUz*$ z8lw-=innY1q(zMXsC8zbP{2pk9MA|D@dClSwW5g#zD54u(+F;-Q~$8mPt-*4X|1!F z2-@i1J|B+YV6FHD5xhoQ`j4;2~Ol zW>^Isd%?PJ!hWJAg8ZvM-+hZdd!Yef;CPmvZIJ<>+l->sR~w{CkeOl81Rg`T6WuH=$Sn*>Yr=kt zNI@cDXEO=~YB*5GG)BGLv^XrjK?E{yiAKQRSrmz|pQwqTCG7C0Wdirpu-Z}xRC^{3 zkET643;=STOkP$R00zikP6c3<0l+=v(5TjE0Q?o(XIWU3qT7Z%kU%tPt|r3b#E~#6 z&DFZF(}qH-#W!dK4pb>y{8$apEq+W`@K2YB{X;IGpuyY+Tj$>O4 zY6SEzFR(3kX#oG589ere#m|V5KV~KRG{#rh@F#`+q(zKpgq?4c7#liEBcKgQlR3vU zrZJgw4ZxVpR}D>LGUpiph+wn!PT%Pw~j6phw z`gth@gg(9#c20&H3v8m-+++B_@b@%L?pgzYf_Pv~eAfWb27jWDyv_hH{EeqWz1{#| ze0{9)Jp+JFZ=oN%(Ey;rY?k=GQ8H9Gnd1Mz0Muyr?Xb8OJcjt+`{HWdux~MnxGC(X zIBeKE!_I>gB*-?n+mHZ9u#8*7;*Ug7N*8szMu5e2tdE5KL`?*bhMhcg+JK-=A5S3& zT$>HRPYnQ;2#gPg1*e3e_c>>MSYv#hM)_3OPg=zIT-Z6D7>mH7cwQsGiHbl39Y*|G z12C2awpIf0f(B&TAWEC^?n|{X!Lp4VOP0?eUk{{! zSo!=z*vW=a0sh*Vcs)Gf8Pv_RCm~KH;0*(qXaz3F0N{@XP>iljz@H2N28OlfSHhwk z=t4_iOyYN8xz-$dj-Bo=VLvHT_IJV#&EAKUSg!jXK zq9%faVdnxOm_w`n#2}z*u*?w_w-dn;3}imi2>4qb;$KgER}r0AShE=K+vy0I=*ZjmmETu%O#HuC0ZjDKY}nqTK9En=*#b50}1D;X-* z83d5?Wt!6BIyHDhPPX{rb>ezrY^GAGHO5;h%#u1kX%XYnI_Dq6$hUQfM#CfYVsj8^ zG61OIO}2Qmp$RwqO)}AD06+(t(K=BG0}GwSVLq;D4pHaHIzPGLuEJ4uPA3Wl1}WV! zb>p80IFo_YLkwQl8UQThL=K(n4S;SWQ>?5LCy_)mRlmBfkhMdXOvb~;IzNe%#I`!; zZIU<~U!t#0ci-_=;A)aM-T=l~fn_8yU;sr{;1qJT!_Wj*gE;`~GyrhLh*In_0L9go zI*|{j6DlXc~_H9)S;H2^TN ziVb|80f33cqX782(LOrQo9v<&7=Twc$EkIKo6wzv)-Ch#-* z${UPs;XIeJ&2BURIM4IhHGW_K6Rbc#jrE5HFdor%TLtErM%e)XngRH+0YF!?*s-Tm!-c_{b2f0qaFvvCSMM19r)&#j$8V+*xa&eH0gG+*3CW{orsN0ikCEu|i z7nl-3F2*zjxp1*8$Vq-vkn`}CAm`3)1>6=EZ>So{AZNcFLC#oL2086q9pv2c$RHHC*j#V{E#_ziJ2uFee`}C&dT;O> zB{ur%F6ku%0FE56f12I>;FAnS#4%FHfry z&jlHU?Janeu$RK2%Yf-GK}JOH75tL0H^ZTe06S2`h{dvt76lkNqQ|p*pFfh+V{?I%XG9#)MtO0js7y`!S2|t_%GDTG?tB(c@T|MeMH_wR2WNXVjOB^D?o;i?lpObG-q6 z&+=Z1v>?FW%I^B>IuCn}xET;Q#&r>=VlH~WJXo_Kl8T1pIhu_IfPN{@(QGmR^h{LbG$|%&(Z9P_=%bbPLDVr5rI5Mb4EmkU+y`YGc~|HM{~9T z(A{vzKi2>-zmw-^&NDcGA5xqg5#!6iggi%cY9#F(%>@xZ*&`E|Mx4V@NS&j(++c(+ z0D_Am;%Fj}=V&g`2;@1MDrouj!{Bj7Ywo};D()&(U0O0FXkS zqxqfzKni(|<^}^mstC3Vvy)#^@HzUre$Ww=7-qKP{fIh|FBLSkK zR0krt*Rha1!Sj)pN}k~PI3?BRkx~2|MRkJ5ifXCk2_8F|lImZPT!z2u1ka~hDq<(6 z|A;uBAsHk~R*>kVRDX$xU?l{i6r)+2WpkssWdJIv0?}b@^QjLk`?qVT%^rtAQ+Dab%85?!msw6sU4+^QHKU0iU^5{=#np6{_xepSTJo+$x^0UYQlok$)iqk+)9r>9ZRgO{~`KgZj$sf5|5_O&> zSMpp-B&z(Jd*mms0q&8XrG^A($|FAw2B2t$qv9W=DUbXt)->gjpT?-4+>qvqs53av zXrf&speE#5r%r>>2);@K+;c6fO$p4e24K#$9AyATHAfqOVzW6az6}o4k)Kx0 zrabcVm8hQrkj)KI=Pj}+RkLxVYPO72&2ff=QO#BZP&C&@Mecmilt+HnX`1rL&$g(a z+>qvA)VTq$!X5TxAeo*pWwmt~LM+JMzfSZUexuBai%i#{e)*mq&iCF#zaF9{Jg0 z0OrWgwFUsb<&mH78i3;a(x`ZYe9I$0mutS|k)P|Leo92Xe;9QxUkJYCk)IzK1enRl zBR@AA0LEZ>2)7=sg>;NETkkp0!s0Nh~!kX;@My2}6{syq~Qw*f#@ zc_`>!1At`mP|!~dKuLB(RNN1y)uEv8YsuuHp!=eJ%1p@~i#orhWZj&>KA{n0d!-A0 zC@MZ70(ti45sg5ey?HX~Cu$;iCh8O(4g@n$M?5zi!P8L@MxHw2@(YbX9&y@RrCrL64032X^{6|!L3mmAE zBnLE`@+65T=BEH;Gdt#NuLhg)BuP$8sfMwmJV}ykFoG+&I+$llKsE9tNk9W^go^Sc zNxlKVZskdmQ3e3Mf+E>Dt7HVD{6L9}J50ie&ylO$6O0Cplz zl1wuIC_|nknPC8sU7jSFX#kL2o+O!N01#E4B$;gh5LKQenQH)$Or9huGXN#o_!y1_ zLo#`iq*zNPPm+|!{FIrJ9UgPOM#)OKJXfs|=sr6yCT=AHd0=CKMj#Jt)W-ZoO$3pc z^GhPQglkZ-;RqJTaOMsO`)jAwOV@y;cPaQv4 zt`W%N2P z924`CI7#%xoX1E)9zWQmNznG?@q;bHF?Ppr6aX0I@q_gm<8weHj)mSe#^Ym7Mi?07 zX@fzHK%X|)785g&r%oGe*9hckgPk!yQIn<9VonDU$kPTx8i9M-;7kKhLY@>8ClaGP zZE%XlC{G)l9rKeGF@8PfTuzMgw81wtf_#PGt1&Em0D(MhaK1($Pa9km^Aj}@ToH4A zO9b+?!MBDZ_+|`yD?lJm8(gLl$kPT_#r#A~1mBH0g>^t6Pa9l69Km;DB8)tB+F*}H zAWs|I5c3l?5&SsjoP)(~Hec z@iQ8Md)nYx!y~Ni3yzDwG5~lRxtF}xcu9C0dHmpc1Aw=Y#}9sOszC6^xUcYn0l@vp z;|DJq0KARdI{vM}0dFI>j$bk*;8^7Wg_jKg9ZMcic*RsvvOg6Qe}h=+fWp&Sc6mVI zRSYUx_P?O-9szC2^965ejEHYl3+^){AgVks@>c^eEx6wRAc#D0@U{WKkIDlF?-&5a z5P9I>T@A=kY`%g14-V9UgFk6D<$;60$NUt4P4p4^KiNDJtCHfNM!?Q?7M<278o-y- zb2LT&C&te>HXP6xzc&dFpP~OFhZr;CPH2fSBX3-d&vaVy2t&38Xfv|nVi5|fBMcdF zHAcxJ47qVXX%S;V-02}kd4yq%MnE4Wk1&kW0DXiZKQ6vTjPeLWP-B!w7$(I1q(zLS zai^``80IvMz&*k+Gp_d_joHmI0AqG@4NYTq6$XITl1CWk830;K9${Eu0MLZA!$k(E zvBMfu0(K~mFoaDBV~0l=0HnYXhDmX;15&6X43pz&M;Pkke&$#?RK+<+=_3pfy(#WI z0f5?3Z`CB-9rZR1aCg*KXn@{PZ-|SxNK)>oFN>$`sJF-c%&~Gv?jSC`qYjcs#hro( zNXm`uV~mstWMNXP@D2{-sg3M4y1C>=_S(3gXxLnv;!YsNBfjWdN`-xsiRM0U!pH8`&or z0Q#@o$UfNsU^8+f`&83bun4)4eVPHNX+vLJRDmV6k=?KPmK)haaX%#@-{-}h>&ds= z$o`rk0lwu%_SZGQ-N?SclrW*{g_@?jk$tf);cjGKW~wM{o*frYlPkHAeXize8<-JS z#Qo%#Tzx0*d`Pb3M)tL780ALxcMV35Y@ct(#kd$S%8l%+HAcCSeSO?dTEuu$+*yi3 zY9sr{1_9)h8`(FxNKX13;Aa^C zxRN{gjsYmH{uLL$CRcI?|I>Kd4!%F(C%;s7FyTa(f-AX$Uy#tl2JBYu;Ey%{n1I~D zFEjvn4Y`9q)&RhS+`*ra(DPY%4Y`9~Yye(qhj|IH83ff1ettrYmvRSxQo>Ju$<_3P zb2+(^JNPpV0&pdF@DDS9Jc)5iLflV`atD8^#wd62XD9rmWfg9<#nBO`av2tWxdCPc zx#5%%klQxiAopJM_V67My*L1wpQs7X`VxJR!(+ zZ*|%29awUXVloUbSW184q=1SM@JN9GkIa%Mlh^wsPyZHy)acJZ#x=*u<8t z+(JGxZnkVWC}GQ%qX4#S>AJCHOMif;ZVz)+XwW!*g!Zwj%w{NY`ecP9$?dZ*#Rmp>L-@a@BQhVPa_ zzD&cjA_Ilid(K0lth+sKwas~dVYTz%P%Yo?S*#Yv>Lgy%!52zb7s>9C6%$W26l;nMKD&@3oPe#d>{^Kq0 z&nJ*K+s??C6wgHdGo=&`J2M%RczneBys7V*G+`>9e^bo%KylBcg=h`$OT}zfl=oPZ zGrjkVZ-MfZ&?w}*?Ee&)rkst|^1d3B@=W+IC^p~wll(VODo7@+;y=Ukynh(~CLS`2 zPk|frzBYakD1F6UIe7SUAv_s|-oJWCc*2#KEcv{D z%P(mL=7QPCc)yTotN1f2?}H$#WTO5%xO=9K1MGn3AkyCHD3$dgQ0X@NIBz8&zPF(R z%lFg-h-i6w=Az&yp2Lwb;g`9f?fpFeT|5-rHWL|+9V}`=>4JM$tiTRd;VHAA4UOw9 zwSz11w{P_Yzu~`E`8z8*}lz z-uA2`r?&wz<6`)R9PdUu{}VhF+%*R9&GrP!V--9^wQaE{P^8QPzDVACtUZAReL(mS z?*6}E2=^XmdmhJw*KQ@DizMYdnZ5z(nJe3@tm*lb&ogrl8h+uZX~^_^6;-opN*iRs zZOpBNA!Qv=dZdIfIP+YD8GKfK(N;hvJb?6~tXTfhZ7{P;cz~=#umTxY@yqDFSxbY= z$Si)24-L`)eZ_^~Ijd22ik#vjVYFGx{&ro_|tTk)q9bD$VT0_pGz+`SK8fhfZp+w#?-dz?$bo%Y7bEAWLvn!J+KrqYhvdvc&JU1t(IGii z$hiwSKRhI-204!*=kfF$yTV#PX`V&K@6$6RYb%lSDsnzLB&QcS`;e0leGL=m@FC<( zmCzM-#X>s?3X84)>;Ou;C3Vh1yB*n9bp_hqJ}$!_f_?IH87_NwPX{!76f6x{GpY7F zaNUTjd}yu&E+P=`dc*4g0K5tIiIPo3G6cW|0%Zdom$8-&G$#W+5ZC;+9F*Lq8Yl_C zG6J&*?9GtF{8a#4fvaZwh7FcIph`Xtz{9v|C;3ovPyy`)Q^13L6v8raOZj%nhCKld zn?O!3a^@eBvsUM{jLcc|HH~c;Cad~`0uXuMb`|tAi|w9+_E8FY-#(1Gcn9pgflDdq zeY={#l9o{K_A%Cf^P)i8eB>jA1dIx z0PM%5bn%e_+6$(G+*n9Fy)&(?GpLIi#g+nct{Tcs{V(;4M_A zsREwIX%4?qcwn}`^9=Dwzx6A-l&#J!$!c5*`LFB+M7{xlV{q|JPHD(juoZ}RD=p+f zg%=Sm@cLI76c5_7iQ)=WzZh2?QLF@i6)d<839IZ)4Bqx7s(MUTU*}f8#GcOTd>#Me zxE53(zZbRIP=Z<-#5W|g!i#kVfRr0(KZCckH!8FZ6764!R=W9(_VkMY;;%}wK+U=x z8!daYvd5(WL~$)J9Nz2FviPoC>m<Jq4>+0vN@#s((rUlCb4qg=cFV zE_-+LYNMcpT}}zNfMSo!N`qqM0sy{7U{8O)Wj89|cLCUgt1cUu$P0cYWejjuri=P2 z@k>!F?P(PCDb#oz*8&>IH&N>wD4{fHEyx4x8o<7r1|y$80_^TI*mS^t0@%+}uthKc z>q)>gE^F~u^TEslkU|%LFSU1vkAx?gjMlRk%w^Q{HuCo2Izo<(3lj=s7 zf)=vOgNA%}>3H< zs|1U2Ex8UZ$gY*JB%b-Yz$KGP01Hdl8F)UKu%D9sIthCK&-W2lFb}ZB62{+Je2%cm zrGOnFVf?*C&X<<_lSaKn!f>?D`i!tgX_563Rtnf8TuW{ue-R0b3?^ruK_B;3(Ue3eb*!dVIc{xvdV^^R6FXtI=bj&2Iq~h{zLWOM* znwN7`c9dN4@p}h5<%l_PIhSU~dSFDnoJ+D} zuY+k`&SlxLZvrPT=i2Pp7bwfixjZ|z293|l`DS+X8ZgQW@8QjkU0H~iA>(r1$c{}p z41p{z=WcK8=Fu=4T+RjF*jJFx%XvLJb^sQ`%Q?pzdj(d(%lTt=^h|^gyqs}hdp|;K zUd|*ujGuwU6I{+zJe)cQZ^6ao9EOLlqltMr=YWwe%oKU~@IF6#lszpk zRGvWIWCDFGTPD1iU}?NU;mxt_#t^IIP6j&u99dq-_WOYf1qjC*b|oLOyx*Ve&+#up zsr_A=TAz{Pcc!Vd6U&r;K^D6y7H9t%9tFHAxbtC zeZ-nJ+MY31sTr@ICU}O+oL2KpuucU^Dwrpv6D6;+h=NkgPR~IUig}%DCP$17WAZ(B zI4A=hqO8n5VytP#8DmG;LGO~HDiPViz}bK0+r)Xz^rgXv|B})v96jWk5BIr--mBLpnEF zX0b(j^Ni-P96SsJ^so-|fsepiRU2;@DiMq#UfE+Z%^iN6g?PIb*OwQfqqnUUyqQ8P z4#6}^7E1EQLbipt)O>1?Sd0sl3~1zioXX~HAuh!TQ@S2+gKh>>XW{}v-Y#=9koeM% zLcby%{fa#)^efWQuh^49zaky|2%&9Tky7{cZxwx6Ns?oSwXF``czLYB)Aley;((`k zNRo$T3d$QVls;t-6YCV5w~aE{$=g<39&5+xdzc{8(0YpZBzeD3LOXb)mWDM8p7F`X zWn1mMsS+y*<%cf>=O>7Zq6n+cs+{JkjgM8+q_R%axp-ufgmq!0+z+|$!-ZD+8g3Wk z$^sz!i!a6vGp8gnR?Bj$cj88j|1-;BC1p8GtyT4SqxdR=sVi^+A#YE+8AyETC(UvU z`W1Up=vS;oErWi=o)r2O>F5u!oOIh!N+v`@6-jA56M-F8!rL(Gp^5-cX=-JPrQ}*< zA`D{z-jtQVkeHxC0q5;JnOvD-IZ2j(prE|{7?;P|dHNnEZc%XFo|4H9-l#v@T8Zyr zpER3NC0u9lZ*0nNuWgDveG`{{WRkp%uqmpG_H>@i+GWifw}+)jQCRX3sbL?4`Czw= zHy^GqcX!M|A>MNSZ6O3qvKZH2ExKKFA>K@l5iO1!MN%U!z$2Q0w<26$&ImHBS-4P# zw?#79!CRez@)pDO@2lslg1iOYf=pplCSKke+zce#4^2)JuR?MmE|hn(bwVkjjW=5D zNJeM}dAQPQ;(h%Z7(nCs`o=Ap+E73BFy9CtfHH6nvLC8Cf zvlS2wW4!g_BCjjxX9pbf)*;dhp8%+ z!CS)3V5&o9@V3#-U}{ih@OG}7!IV;Bk~gEc zfC8>DB|TDJ0=@8aCjzI*;XQ^+vAc@weu~SsR^eNI$YV;NPL@D6{#+NG2}lzz;_zB0 zSUa=~L}Z?k9QMh@6FNC>CAiqgsbKRIK$L2TT7AeoKWtil#;Ke8OdnZQv+Ow;?3_oq$y|sK`b9aAFd4ErD&p`J;c~4c> zz~GJzTeg=EZr{Fj{pRj1y#wW&*01mC?%!5kSLr%_ixy-rFVOD zdwc= zf6LCEewxC6F3v)hGT%P@FnU+_x`DFw@BmiVhMtYxJGKsX4W8K7Gf=jf9Um6E0lxx= z2XqP8eiwgkdwXvev;-J@Lh|qg+b7b1M?t)3*WQ7RJ^i`}!V5) zzc(Es`B}fdXMp7CFR%e8r2p|Ou!RVveMSr0>p9*QK2M-bINm8@l-I`H<1dpb+q0oW zjPgt4V1n_KoZnn!rw%7C0X<>;B z$$XV!k^fK|LT(EGr$V;pJBq|XO~UVqg-P;RtAr%W@DEHGnKp&~Z`oB^HTv*uEc@>W zrx(uk1jEAb`Tprr&{wQ7DX1c9C{Oth$R zVF?8yXAV$JagD3_zE z@J_>71RI8DdeiM0u;2o8q5Kjdrhq2Rbo??=JXwsN1Y@480O9`#K>sPvz|V%I;eLv^ z*)?ov)IYTh=qf#a^i;2B2W>y6Yy>lJ$_fQyDtHK%qQprh!Z%$^Ef&5~exs|&o@INA zXs@2*N>n#;ymiuma=jiWEb>u%l(*7bg6>^`v^^Et@*H0x=HLN+e@-!;f!*uLVb32N z$;Ble$u@N&a;FG;q7Y5sWx_Q=(3b#LUKq&hhyh(a*E3KS#&1`qOa35HxLPfP{n%he z%*F3%rx*K`TMW7{D=8b6`MS*XE*l1XU-DKE@{EUEUQai=ug?Q3wLRT36^2?$MHw9+ zWJCAzc$?*SnM#XV-aRMTLIO}u!hyQgdHfq1l_>XRtD9UkO)}!v`Y)kDO1F}EuxS_z4O_m zi|i3L_O76E#~=@eEanMN6w^w)Rn5&!%_0vKg?Bl79J{Wkq)bc)9^p9&2HlJ_dNQ43 zsW<}3Ia9=}iDFI#zcGG>#4PV9F=w)vT_GyV6i|72y1Qwp;DEQuxZ57TRC&BC0~=sz zE&m)cMF_l&5|bwjA6k4qDorS_Q`IUmGKUraNEN6565cv*ne38@_O`BgGTGJGva-IZ zG1gU|T-wS%54YHDp+>Sjbc+B;D#+S=UK6z@QR&Xz`Gw>7rK z50Au~+bo9t>k$=oZP?z`y?$%|Hmj|vGTM=Bs_a^q!cw1%b+xp108@KB*%6Ofn@^Av zhJl{Ju5Ig1a0@PLi!bf!Y-#UoYinh>uC~V2@usdsYqGh%!&({XY>&5Corz>~OJ_6i zcf{K}npvwS&F%tFAb9=m_gYEA|wcECD=;<2NDB96fXq04qOFN|{@-Eptv3N8Y zr@=v$?M?AjiHZt+ue8vntLht5rr4NV(G`Kc;=hUNBTcAaY&71{0HkdVYiP=?$*!ix zmgR2ds>VcPSACl_vS@2dOFT+iG}DFBOo^nuGa7}RyLF7wujq_-#=8!Zt4)~>CxzDbhrYHdTGUI**$ z=}jR@psp2d>1a-CL})(N)}D;UE0hs~u684R>$moF_hWK4(6zIB>y{0&wUjl+;wxc? zD7tN6(`K}$)v=}xT8u$5bXqI9Dozb?Hs%V^*qBVzcg3U8uF41uv%aGv+F;=|{cSO8 zRa3lWX-9)w)O0YqHhM^H<8H%sZ`jZ;Rfay|0#k|v)a@`r>N|#jWFdPCQ|I{|1*3Tk=czYg*pg2?JUkjmKl!i(*RKy`jI7KBIMIGMcPM zYtrniRNv|$)mU?~t<&o2!ZOL=B9t`N}Pq)ugU}(Qg`lWY3GYHV*I3(!r7~Q!M4U zIHIUNruJkYgqYxgF%iXN?!@us*O{fr>m+S{Y? zuKG@RFVp>&IJt9Ri#Jm+tP>St$wS$6Js@*)s9cw zM5MxHMf!D`YL^K?tP}dT3<9lN#Q49i`e?K>Ss&HogT$$<)$rc{<*urS;yN0e0B$`rViz3Kp*_uDLe#aiMMhj{fzQB>fxe#J z4cpkb@#M;Qta1@776VR7wsc3V1`Aic>o*^V)u-N#TQ=?J@7ZAWbzwQoVz7XCh*3dv z)MZbLg>eyscW25E#HwO?EX6WjES}`Zj$Rq9uh3=(`vgWBKO3lec+kQ|F+*rmYkP;Q zaH&>>sG(WkG0Z1Msu5-qVsI%9_&U8yR9!} zde)BK^ytr+e<=T>pmWC_3qf#wGK=C#|^l^YQ+%jC(;yg4be5{s2rH| zuq2&_vMomB(&S`(Y7{Mm6w+K2M$5*;8mUC9GrC-d1JOjvkJ5tE zeXUlW4kpk$F`0o)(wF1BGZt}EgA5jY)67LhkZ^wp0+qjzQzG5LRm^0BQKNwhVd2Q7 zKh{HG%I&30yr~rWTZOMcjicG{Nt^M z_|D~V)lMAmxiLC)O(Cj;@uhO&ypsrFF56`ecWSr`pl+n^fpL zUm;SXDjSv|B_l7!P(QsUbi|!fR(Pts5L6nnfY&}9ZW3a_|$WcPJVgjbw-T;-1P#T9{kZA2h zB#cq9CDGIv#ZZRXf#gv7Aao+BN4KuBx@0^WM<8gXqiOvQJ|3!e11v;J@%j#|6U6H= zr648O1QxkCT_>q~q~Wu%sVTm+9wTCE-rWTAZBNajp#f-iN8e!A=I-7NThXyFt;5_B zEVz?V-STqo>tfdH7fb7#o57f#jK&b(LG9^1V@oflY^D}xS28ZfgewU-+Su-HCqkPH zVsCArivcZ&qO_d2f)xgQQOu8t9~zbMY6O;&ny|@+HdSYD z80ee5v9DzArjog>RV8z=j8V5949wlQ4RKlbrk=T5dwMqwZmz2UNR0t=*|qVsaYyfZ zu5rvAK(vGV0AL(D+-IpqRF{@FUxn~Sd>NOiP*M(eayg}?wG+d&idcuW*!qo|tWFrD zt352#=;;n;k1p5^XE8yok2E$l9;qTwLp9|Z7#wi6#J&nPTnwqGhrZthr&a7sA|C26 zhHo&N=8SOcO3mrv!=vzF5in^271y?uVx9Z3vM6mwBIVTi=r zvD#7z*9x~u*JUuLnt{{ZE=2Tfi4LW(keWGwlq2TNa=j!bk#MAVGc)! zNyc9zN;DxH1>J#xLYHW^2DWb;JOKwN+6TAyaSaM~P(c-9@{6wG5|j#LUt0=)Dhu{qr8Nx!)Z(Cu zBiayLBJ{*^x@j*Na;u@;8tB=ytp_r=2-~`_yn|KACONX3;9c8o+UgbN%-d3(N3Naf zp;&qyjPjf;W30p?Dmkiz6YS_rIirSEaCum3Q>$ijF*s!zMl8%`4h5R!;SHSQ9va0B z^BG)sQR}6L^t^dhuF$ET9IH>8i<+6$a7Wiv8DGuCK4`niYB+QULB*z>E%htW=v0tx_u(WiJWaED*xNu zDmBK)pqMR_)XUq+ib|PNC4DEm)O^+ZhKDL@xyq%`-qy&D!3AZkShYkL33CAGu-cPt zQ7oKu(Zs@fcf0Dn4QjRza~Lj`vKYA<)r8)}$pV}a>Y^l*+>MhFg;UEmbn* zC^^6yH%Yz8!L+@z9YVy?$D8i{LDd#)1|WRNd3Fwh2w8DpYHRn2U6t^thAr&( zVdtwc+9>0xwt9>sCQF5fvS)IX!X{NScj#0oLF5Z0J2L3DKqq|wPEGBUcXW{&7pJ|g zTIYu;t2JgWWF?X<&Dz*xf7RPhwB6WJ1SlzAnws9M>gvQc8n~oQu@Mn!ZP+p(ZA#9O zV)Gk?bh4I@RIQBoB|THT&KadwOUl^ma`nS z?tw`u<5PA9GvZoF>`1wzle8kaFyS&+-_GrAdPLP+X`NjQ285kWYAL}T6y%nUylqhZcj=ttUtbR9Qc z42JaeDeOWwMll#6qEJgIZmD*xMq^h&ZxNVQP&*|MA??uZ|63TE_YTG`=g9QBG$YJ3F@txFoLPXC2F??ftoq zG@6L2eNLl8?b6kPpdLw~6>Je=dzK@)8FbdA@AC5HWoBZM^6aVUYApV5Cae^A4Y0c6 z0u!W7+4ts6UF&!BGt316?yWVnH+HtUVzW<~r6DsPq!W`XTxotcwV{s_A?}8LQ)Nqh zX)9tkI5h0(7#*aY;xJu?%kpyPl@6jJ-8(S|+0whAXP4E!Lh1**4wwp=^BsUP@J$Vg z?#Tl5Gjt6@)7>GZ=yIwufXR|Jla;X;>^;?0Z#|s_JVIl^>j1{a%0+E10 z*EKDU2mr9q1 zF;dH;mDMRTm9vW$o?S}KQ{{mo<1b+jj1pvw6Hj*q>Cu}JmL`+zOxq^I97sz@N6yZf zjv{r+K($!(OXlDlZ`?j3rzY|=hjv18<)I$2P7}{JrQ8YqW^ea#j26_gv5a)nYhqm` z)kbRKZd@xTtT0ioDCmx&wp-R=H;M;9Xo+%>-PLnds?Dk@Q_!kZGSz5RsYa_xHCole zRGY}f_H2f?bJx)h@`pBVcSI5k?l>lWqIhx_5NumW#Vi}NX<#4 zLe4`%&2mS_WkgfqF_{G1pNWj(s~frN+<^GWjnDN`3=FZWe_&gWiz0O-sES8|uuRjF z3SOm$g@=)|5^6MwPW@$`Hf`%Jwd-t7E~ZR0T|R6ZK|D_OTwdh3l|JP)3fCDRjw7CO z?MhAlxyhwef`d~HOV!CIv^m!}xW2Hdi&GIjV9FptqOhda4f0e_WgxEeP3I*d&+_Rt z!?cEOss}9!_1Th@-gPhUm)BOp{xwTDdfnZTdSq z4GyrHX}vj_;G&U(L!zFu0i1Q?e1tu0o?0N%{W7h`8ngzVA;+Ls4|=Yk?l~2yIEFSn z@rpfyCLEq+2-MU9mtru$)er$zm86T`wmEHHCQTc|j$1g|95XA7roQf8uD;t>ux%+! zMf&Qz@vsaFWUgGhPmSf0RO;NTSqM-gT$Rg!(SuStsc5$t8i|bg=%o;xfXl`5a>OYI<*B6 zE05tCyJC*H?bb34C*$FMOjVRSGd5}YI(vP`+$*vr;dMG$*lI+vUevfR(u_qRovzKL zs#(CN^e7d1n&Ya~uadTwC-23jtSR6aXk(iNPYnh+S(5BIDO*8SRkRMydJTADxIXC) zkyKMVC+VKay0v>`$>VBJ(r zi zUP^qvd7wPI?Rvy=QssOT0purAo}U&!mYuuazajG^96RvEZBIVIcblZf;adyJvvW`M zug~0I;yn4pn3kDn?UYzK-V}@1_!ws<-C#!v% z>Of|&Z3lmzuamD!W>;S~Uw2;*Ur%4JjK02MsIT--s>ttr_h;&HJSCYL#IxkyJ0+|T zKj~n<8fN0j@(!&eey0<{JCkbg`6EC-D9Y4#&ACrv3x7@URGVyGA>-em#mQN;L zbkq8H(C8bVjKUY;w0tsA^R45zON*ac@_fTYc3OP4w3bgMUi;QsU+Z^bWa4P+-vRA^b=vWh)4~^}g>Ov@ zKb97LBQ5+@S~#^!)4t9yhW4b7n?jfW+n8WQO^9Wy>%zL^dP3Y}2r3vk3h0T51(=|#z{q~?0 zC-<1Gpyhc)B)DcyF_X`CE7%fc%zuh-y^z$Nyoj*Tl7bf9Nm1&F zfAM@am3oh3AamTekTKeKXnhmL6WVKo)-kn1k<|C!+y-=3(mrkgCQnK}Ca+j5U~dyT z^)%~|m^^Jk$`)=)l_$MA{_`F#Pc;{)Egjk0E>B4~`2?Ctrz%AlBYobp=cC5^}N>FJ~qr-s>VW@P;p2 zBqulrzlKN7_1;4ooaZ=Pw`R=u?8;bxV?5sIy<9oC$h%I<81&!eTqE!}%e~i9j~OUT zBQN6og5w~sQOIs2E~xsDh4^t8$+_y|aa6S-^UpA<$dK>xW0>VZ!gRxx;$h-3;%VZU z;p3hxnEFz4)_;3o&D78!=n#B=!{hiG#%=ag4}cA!2?j z#A>lY6bSaE~6NjzJ;NW4P4Uc61bTYOM_LVQkqReW3gQ2bo{TKrM` zP0Yl^LHmPZd$Ft7TO1$`6}d*{d8J}htP*R*>Edj$QCucAi)+Q>#f{<_;(6kw;??3! z;udkM_=xzF_@el__^$Yg$X|wHe!dg;h<}P%cmpAiheiJ05yL&izTzOUP#i6e6BFVj zv0gktTp%tJ*NDf8CyQr_7m8PkH;H$O4~pBwm&CWkkHjy2wuGi2O|-%4doPi${r@#7o7k;x_Sp@fWcT-eOCAy~RSYT&xoph^xg7;(6kA zBHxNjeJ_h&h<+@9C~q$g5=V(O;w*8Ec!Ri2+%A44{w(6hV~qX^ae>$*ZWPZGZxcTe z`2urepV(KNDjq5xE1oA_C*CVQBYrA=F9vfw{XN7ou|{kXH;EUDo5jb(?cxp*x1)^R zVR3J9lsH3NDxM}@C*CPOFTN*!E&eI?Xz!&nP#iB#5$B7|;(GC1@mld7al81TxJL}& zW-sfZyST3y5v#@7;!5!}@dEL7@lo+r@e^^E=;B9Rm|kabA90Mx-`(NyMsbyRs(7(@ zv-qI+qWFRMt?0vr6ZLfv`-%IBlf;GM8u29YeDQj5tN5(=j<{3&UF?Pn4yHRm94Af| z=Zc4le-kefw}_96uZf?EyTvx0y>z;YBgArXrg*S;l(JuSbSOhNc>*R#BUog zUwLAoSSC&t7m0_98^sI78^!y@=f(HLuf-s43NyVfVu3hboFdK_o5l6wx#G3rJ>t{i z4)HrNfD1&X*InFKpc-iMUI2^QB+hM;s$oi3f;>h)0VT zh}Vc8i$93|KA!$g;s9~9SSijF4;D`n&lYbIpAugacZ$D@-THdz4G_nPlf}8>(c&rM zHt|jI3-M>MQ$J5{U$I1-CN2<<63-W}79S8_5Z@QS5%~)$Y)9?IzT$9kvN%gzEp8Cc z6R#8R6`v756~7mQdwc2i5J!t~ahAATJViWDyj6Tyd|CWR{9OzVP`Qc2#ke?ETrO@9 z`7@L(kL$#H#b?BSio3%=?7=f(HLuf;#b+(BMCeZ*ohCN_wT;_>3?;*;Xr;^$(=!JgiPc#L?P___G2 zn6s}Jzd$S#CyF!0<>FD|8RDhlX7Ne!ZShAjG{j41lsHekReV-_N8Bm?F7_VkonInawClf;?gq2k}fi^MJB!{VFbr{W*tghDT!1!9x9Q9M_?MZ8~pP23A*$Z{MjR*193 zL&Ousv&0+4A4Gq#r>B!xDJ~Qb6;BZ_5^oY85Z@9%6@M4AhkN=9#d2|hc$~ONyjr|V z+$O#${vbLdJiT4TLE=PlmUygqk$9c>u=uk0k@&rsJ<`+PLmV!~#i`;V@o;gYc%gWs zxJ}$HekJ}UhDUkn^%4uj@!}M5zSu0T7cUoY5uX%462BI+MtkY>6$``(;sUWr+$dfs z-YDKLzA5eye-p!FlpnD`94}50=ZnXRr-@gIcZyGnZ-}3Zd&Iz4FTL*KzG6hI7H5lV z#goO$#M{M3#aG2o#9g9W;-%MF+(#TEHi+}YBgJ#YE5-Z7H^fiGU&St^UON57h*&Mo z7T1a=iK{94Q^^Yr%>3&a`XQgMU$ zckxE?e(_ClhZr8`>Fp&Jh~q{6mMO=_`C_xUUOZR4R=h{tE`BKP5xei_>DyO~h}Gh3 zajkf=c$s*+_`LYG_??(BUilIC6=Pz9*d!h!UMt=sJ}tg2ekuMcwk!A2*-IQI?k657 zE)mZZuMoG0FN*JonNd$~Z*hni7w3x0#SP+l;&tM^;xpnu#jnKQ#I7+fy}iXUu|}LD zHi^fJe;02R?-#d=J49~yv;Bm{y~R-?o{2KY=ZJ@k8^sI78^vwncJV9mH!+;>^wGC~ z=@y7^!#Cj>;_>3c;`8DT@kcSM!aJ|8SRhUiXNXJ1wc=^wCE~r}lj3{g*W#aI?gTHr zK4P&5Z+Tc)WOuc(Hhec%68Qc&GS?_^SAp_`dk5_??(J(Mvxd=7^odp5j2U zL>wb%R zLh)vCtGG?vF8*8mS;UX_n0o6d?jw#7_ZRW}u8B8YTp%`y$BLW8i^S{2yTvEOSH%y- z%{89>$HiB~55#|q8I!$uMPivaS)3;>7uSj>i|2?}h_{OOi%*NMiyw=>ifwDX^gD@t z#R4%RR*46Rmx+&w?~7lGyTyztp8jmHyEs5B7RQMb$%7rIR^b`s0LNLZa5Fj7aSj)c z*71{c{A}?G@iy^6@kw$o$9YZR4@v0TA^uD99~J&t{6lj3Y%zYe*pV#4KB2<>#DOHz ziHftt!^AVi8^y=P_r#yX_Vu2gy~PBH^rnzK9A~b=%ShPOB(9PCc!f8Jr%HaF!WW5` zNq&>Uw~2R3{)oa)h|fs=y25XZUy5IgKajB3*WlUPLmVki78j9-w~FlMIL9meHxl_e zOFU2VD;2(0yh-wV6uw`4MDphqep!57@{bh$RNO88BK}FjuJBaPu6@J`ajtm0c(M3^ z_>TCa*m;_#XDA81BgroCGgP>iM1JuT3x+dwe2tDDLw0hUO$uK?BK{@f6_Veg@MiID z66d|3)wPg1y6oGSTTg%^rTC10)Z5#lkDZ&Y}bc$VasD15nijpVm0e5bfo z@+TC2T6{tBw-kO?{7CYh3V$p9D7kZhS6+TGK%(686z(eSMWVcii{)fK`jd{&5D$`k zk$5->eMgDw#f{=w;<@6b;uYcz;w|D`;#To7ahv#}_^SAh_<{I^xKsR5{8`L6(6cv7 z%oaO{-Njzw0CBKbERGV#iBWNXu|}LO9w;sl7mF*!X7MQTIPqlhH1TZleDN~zD)DCV zc5$otptwzZR@^SWDSjyK5dG+KTt}d58|H`@0!?@jiTRpclN=$A5wTn|a!kvHXqJWt ziOu5S;<4fh;@RT);uf-p_jBsxg9<+?J}15;z9Ifo+#!A;ek1-Mw)c7ZJBj?gd!~~w z4i@=L8Ra9zv7+%ihJ1p;HDaB(PFyb@fQYfko+-moA`qGinx>P<~ZMqKZ$&XjdC~BV?gAy zY?SATy~MuaAaSTTQJgGJ6Ausqh;};xQthd82%zX#9Z@en{cR#An18#Mi{P zL_X_AJ)ep@#c#!*#9ze>ba=+k62qeL`-Qx_!o9@3#X(}BX#9T>-}wK6`$=9Q?l0Dh z#t#_rj2|#KU-G5ma&euwUOY`Se!w{IT7_>E?-GsQFOEN<@YCXU@lEk-@q6)i(TBN_ z<|9pYEwH)0?Q=ZCRw7xTofVqbB9I8-bWCx{cpI??#|Lhn+BvF=Dt*j?-;4itxo!^P2JxtI_qiM8SZ;%u=|Tq-t;#?Kjc9jovO;wJG-@qF=OakF@r z_<;C`xLtfxd|&)n{89W_#LrQi@(GCj#C^nJVzD?@EEDU*Y2rcRJaLJ*OgvuPAf6?j zD_$X9Bi=7QEWRwhCVndZOY{X*-(ov4SL`S5BMuXb#e`TTP8E%RIO^+AhVyY3Qhq)xy zmrKZe+^-=A;17v(FiaaFDU)715lNVI^F(70((lPIm`@^7f6>?ndxkI!7Lu^btZPAI zFYLp1ow0K~2|MGWu^;OZ+*UPq*OIUsw?hm~e)9F49XOYAIVVb|YD*t4GP0d{=EdO`ZfLI=z3782>1@+emQAU$J0 z!j-fGI%bgw&n0orYK4y=VaEjuUqZs32NZsUgk5hb{4NRmzEF542|M>F{2R%6mFrBT zXV=?f6poOve}=-d$b6KC!mG)CSSKmW=Uz>_7}k8`^40U^JHwh+ukyIWe#37)t#*d- zd0uDOeEeMIF#H_UFbanypSo>%kk|fd)?Y+w^}zjK98Y_&{V!s)eof+EL`Xho{#Qn( zJ!<|JrzamN|EtrJ2lc%9U!33a5cyvzNIrG_R|o&%>F~cuprxF>2d4ibO3Fjge|5Cw z@o3iNu>bZzv^jMl-)ru@i*lIvecpV$8sRX{eoum56iN-w!|PucH>!*l46lUDeyqMJ5Txo`2z`u4eHa>zPU>5O|EcdS+&RDBWXWBJ;T)t8G%srvF#^mRaFtB=ohr|OGC-_ur^;xRZpOJ!JE70Em+pvc_3=4#{7a4-bN`FJd(!mzA8ygd z{$%yNou+Rc^s)Z!$J)pHO{w+U6Z&lX>xIZx-w%k#_JL|OAM@O*z7yy!=97mnh?@K` z-p&J)!Q`=A#7j+g2-0oB;KXw7ga0;NKL4Jo@9253!y1ox_E>RRy!DM(W3hwlW8?Ap z`P6hT`3mC!;xXO+_;1rKPt(`A$#K?67h(04rRjVAM{mtbeOSIF^);mFI}iHsFZr?h zYSZ*ZcH@~!#G<}|_;2mwbNu!kD#<$3ah}5Z&wlK&`DyyvVIWz8NYpnN|E<1N(pM-2 zFC6VSRl^kksE_}TNsHI{cJJL9Hl~etYMOm>5s!VrewZ#lC#Bi98uon%Iqe&U|JFXf ze*kT-2_o~^wb^?&i49xTB%&rigWsvH>dVD{wgKCg@zwe8UfkQWMj>qV zwNH!Jum|^eQxdT83W`P)<)?g#Mi-76Q&>EvxG*1Yye!1AC?8iPT^n2_0|#toqkSVr*LbV{X1^FcuVZt+{}*ankM*Lg&g#z zz<4LO{rE9kT^#9$SUvnb+A(Iv{<}YKId1fv0zJFdHFrGT=t&8s#XH@^i*-E7#7haa z#53ug-f!2sm`M*YTc6& z=9T!?G{OB3NsGQcTZc{TzVYu{qPy13@4l}4#ya=6*WJF8cdeT@dDmX!AK&wBe)o-i zzs=9+;P23m#}V^eUq<(J-PU*8aN&lous`>%UXy(JfBy8xpP!uJ%kTHC&y?gRCwr29 z-)1P>52c)MzV}<#&(w@Bv){Tq_hb}#rFJ#GeX{YLHov_-es`PZ$-A8SPCjfXU$E|z zGraQud#Y(`d!%F1YH>l&rz{{!i=o;CNudpP%Helm#+}h5R zNWX70jXf+Sugr?J#$dl!YX1FqejbDMUdW!?yTa=u`0Ja2e$#F{dP`PnPeDt}@MZPD zwPj`*{$%Xib&L_UosRWNMuyALC374vgU5EOG=IFE;e|KOPS2|IFi}5BW4E2Jp+HTE~az{6lV6%gRPEx4W$?j zoXoc9LYakmb1A)_(x>pJ&GY#45&pN`h(CA@=qrFrfjRQ4J(A&MeZ?ab{MSE$4F9uk zU?S29uE1d7f5Gj^lr!-5fgtYy`CqgG6kRC8zs+^IplFwH{7<`G8MR#k?;Q5O?1p+l z?m*w0Zs1hv+lWcX|F%x&2!+$PyY4MKy~gpsuG4FH`aj(e)j9#c{|Pt1t)wt*a>CS< z;bfnl16}XBnLOF$VWji98{poMXZM%ZOl$W}EAZ_8#B~QCGVT5})$VWH&>Kt$`gXg4 zDD@e;_q4YAd)MVY5$)cUYWMGMh-zu~M{eL~d=1kkCrnMS`%Nqs{C~QcJlW-8Q$^fD zGL@I@WS!0<6qrBe@PqcS-^sd#M<_5y-n2)uoUEsKgaVj;*Vw=Uw6x%fu5i39r zQL&rHy4*0zc>$flf5%wUGICfn{>R3KJ_2dxGh+i+)6Ct}_?#5@p$!V29P4sNDTlXR z{ZC23%e3Xiu_3Cag4f3exZM-HhRxy4u|4jFI3pw53BJvIz9oS#>;zY}hv1)9fNb%# zME-ZJ0NLXGYybOJ2Nc1GSH`+E(4X@rk8K~@h5B>uWeI&eHbnDi#J|P{4yF;SS(IN{ zjj#v`J{{|FKPcxL=J0bVSViOhJvKzuRIqDoU^q%Gcm!?SEd`k{x|-SAV+$6Q(*qYI z{-3P?x!_Bh{J&TMa`8Mn*{@d6)(KwBeEwzysI6^0<##K{a)R8@@&923t`mHRI{vf* z7>SI0JJy|ncsb{=uD@4xbfc=Qk`S}VjAWMtRx=~VA?VL7@tU3LGg#vC4KO)}P(iyA zuR-vhzrRCCh^m>&UM1m&7^w|gP4AL?jwd;bX-gq>b<76DQ)3^~OfxGcFOjDdN)fwXoOWf`Fp7R~^T`c3Mg~m-T3Gd;-lbG8nGLEkR z^4GN(H?yRDZ?xpxZZz&dYuq?!@XtyyZfZ$5f@nFNFi88S%Q$MMan&UO?lgsIiW8BxOF+R7K%LQS!Q&h8rwlQ=3iA3qMfwr$dbTR zL<;gnT>hgV6M(Hf?CN=e{1rfEvzG$}w2@iP85tI=ls3<;3&;O#7$Gi?mKoqGxeXIVjp ziso!9utjr@6?kTDC~^DX#GJkyN=}xUg{vnk#J* zwrH-h0x!)AN?h(LsXutjsX6?kS|SK>xsLC$d2;0-eK1DNN(rzFG-(9DNQ0;kbT(`p_` zFPg{Gi{=TNge{sUt-wq3z7qF#ruh=P#sf-o16$;_k`S$7nlF?DVko-c>1@s~TLl=) zXK*NZ#R@Q%_hJdZY6Td}eXQo~R)A*oDq6q)H7h__9mG>!w*s{G8dl63Rsg$?=a}-Q z6?k?(Q{pbci8;4$0DDe$-%Q z$?j~}>)%-tVvcC{u9Cp(h!o6a;qA5xVD~tl^^+A~opCwM++zipvVUVe{%i&4*b(OJ z7b`$kUuB*BY6ZyZCrte}D?nCnq}{(;0p{?>ILZ8B1*rF@SkQl30h%kuyl+d~UzoES zSuWozXa7Qm{Jzo<^UR#JEe-JfP{AJ57%XjB7|x}cAuB-6KBJlKtN=Otm1c&m06Dvo zwVG`O$k`LjdyW+#XW!7wTq{7%o@V*Aw*utMY?yYi0_1EOm3FiOFK7Nz_cf@_sbIs* zD)p8QJ!xO3(h&2^ob@aXoPtaRA7n;)Sp}%G%UB-0tpGVYn?~eY0dlr4n^qqyK+c|` z?!H!loY5D+-_Ht=v#)tde=9)FeuNqRy{!N_zlfE6HTd(rxRtia1z*HZUZ7@aea z$GR(LXR~ewm4=vS=B%(Z@H=yMB#U==siq}ZbpvP55mqCtDqw3IX$7$A99F<+D?kA4 zWJsyo7Y!_DI7@n%(tMniJGL}LYnbNv(!kY-6y(bq{ZXp`rCG(oi&+6mlb0R-gcYFh z`f~KFkRXFr(e6qsz#!F*x!vEMg07rJrIV}x7QoC%srwAge1`=)PG-Kxx~wh@F#|NS zp)_zglm+Qi>7S;e;mY}Ami~0B5mt4gV1|u>qB(#$o@q-H6;?yL53mAM7+)ajKhO$b zcOMF7Spf!Dr0Vz&vZ){=doz{UR)8_-Itu1k0S4CvER4BUfI*6GKK^-D0ENhVZK?Yt zvX#@wmQbg>)6d60zcj>BVcwUP2G*jT2G5|zL#zT+(PM0z%dG(Iq$llOVFjp>JnCI( z1t^RYSj~r80rLJD3wo6mAn#vs8eDA!$SU2@{A;WLSuJ8=9Bu{3*=7okumUeFueSm;KE9LHzrhMn?{u>B zpJWB7_cK_{CtCpuV<-h1tpJ5V|3v>OR)E5og#z}UY6WN+M=|fGSpiCi*Wdn4R^WBz zV@lm4VRR1fYx<8<&aPt-oL(AYo|&_AO9R6?B4;@?^L(oSIg7AMTwn#rSs7d7g;s!^ z&7qkWSpjnPH|oCF3Xrp}+14(x0_2Pyvi?i006F6;b^ZUa0_3a%3-mH8K+fjS`pd1r z%h_3_Zas|7p+mC&Y~}0-HlZs^L(DUCc0*~PEq1qpZCRH$Sp~@12sYcBtpGW@ly=`@ z1<2VH_V8P+06DvX^?sWbAZJ-@Ew@_%a&|lijLlYnob}-;TdV*%8^E01VFkz;Ul-}W z(+a$tT~q1~h0!_tvO2C)&dy>X-CY`Do|&@;O9O{6XLnM;!=>J3LI}N|j;{VktwuEX zOPP_!tN>@DD{n1z&twt}H1K{U@g9wPyfnnbnZ&cDfd`ocUE=)DD+vx`^Jv(Mtu<~d zbw8#?zAw`Mv^2J*#+OP%Op6-dC=KLvg2wNdnYW~|4GQXJMtoNqGhq~Le6`dafyg-~ z@@vv~E^GV!(h$?4#?MLv^QiFy_Kq*4pe;)J8`i~_R^a9O<5Kq|YP^(1v_l$~vk1N_ z4KXch{Ju1BB{j}t_u3@|90Fj{*QM@LR6yr6|F=@`8B_YPG(^=@@LOr%6Dqi$ivMV> zU{9&rwlfr5#v=Vi3g{l>|Fbki)l`rb3G_##puz@qFU1+2-{tf2l9z%FX+5pn;Z#+z8}dr2c-eCyvk5@K4^ zI3yCdvI~r^t%_p-AO*Z>_9!(LSR2v&R8X1tN`8SJr?R%tJKTLz=-=4Y|QD$Mm|^>`GC4hA|Ymx8Hq*$ zpCD53V@8Tgqi#2ii@0sE3!P(*jhBKFrc@CLQ8g9RL;^=5Qt&Z0tlAa@UVYYC8*P0y zSON3NY)!KQOpw2FK%8y`7#?n=(wP#VK3G5dN8EqVs(sktCdn!~=K2pnqrwqdH9rz~ zj#il(Unm6u6s4*0gC$Un&yKj?QsWU!ZLT!_!d`PoB*e6+aaAO+7d+d7^=t{NrGVqh zVXVF*B=DhPVB?C28%5-tqu45&r147@@!Cj;X;I_xkw9B)?t5+ML@8h!GEHWKtxVfw zPO<{qWKOne+9tEn3Xsn}Y-Oid0m}Ak3Qn~GlnSPZ*^SF!X@w=uBJ8pRSm z)5fr^>?|u_b#(9_6LE(k7ddBhhlSkzO7^8w_*9z zwFprjmqr4+AqdW;rpv4ynEoE(czd}Opnxufk1xa-|hu`n#D!)>T%3#&Y2q0HdLs@OQ2%8ii_v%`wL zBN7;mNWs(Cp6;?qKpR@dZ4q}C74VJF{>@U5MFsanLR3u!k3<5eP{AE+T936T2wuu6 zdcq2z0vaEPxVKW{I4XHa8vmgBZIKYuqQ(~^ft}Py2X+4|QUK4;;L|wne^mm^WkKGU z^lz8IkI^iY=YKZhwujqD&Po>Z^O3H77&wlB*CU|;bSN=(OtGosfMepfp#qg5W<`G#^BIKE>pHy`A8-6ntm}y`11nEd7tHU@u$@Qt+`AKndV#xalfL1>1-Zfs_+J|l)sCFsG17) zL;`L0f`XB>@mH&WMT6TM5qAiV<@`bAyQQFzRq=ZyMAcN_mIWTB0zU5HZ&TKC$KW&; zc3Uez%N{^MzzWc^*Rz0vR)CiMFvs7J6`*A|@|1Q~fR;UpF|y0lvC)uUWliN+f!C0I zW$q5zy%$Z*Ec2%3XE|K8FAFh8w7XkbU@F{uf=5$h51RxpB3N8KC4d8Q@D%oky=)Aa zX|5G}D@{Kd+VxDRk7D>Shn>X!wzoaSE6q-2?ph?6b0!n)BCGndX!j`#(Oz0LtSoRH zt-68LRFtA|IZLA0YV=0p!Da6A)W|0v{6nO%Hw$${S%_&-V`*97XKHLTGTk9EU+Arf>_)+{wixD%4J^`!z3#} zG2BC2s%@GWhVN#KS}VX&q!}x7|IRcs*v=D5Gs+H8R~Di*+*LTREbubZe2NNYm-Tp_ znz@kL#fWpQ04-!9OGiVAYdsLq}MFXVua&_cSD! zGnP}pA!S|%e~GEDEep|J7WVOFf!}D=Xjb2eww#d+C?h&%|Z?J+MSZ&u9;u_Nyb`Av95Zr79D69TV|S$#}%ZnpxI z)lv%XumZ2b{!!*eU}MgQ%;e>&uyWSk-DM$Wkr{cYEbtvOaugfMBi1TpDboqzin*b=e@D1N7n%-%)Pmc zFt^wJVeW5dg}F)HHWz;|?w54D8w`fI-`g&C4`-J=PnMm_Cyo4_N;Kj1?Gpj_trOeHqAfLi`zfUy|IB|ZaobSb2Dg2n0qb5!rc8R40A7`ICn7f z@U@rLh%oQdj|%gi_Lwm5|CWS#uQU?o-OF)d-W(hs=54ZQ?g*ZDRH?B$9_9_EiZE}+ zREBxuV*fBN@+XCP9bOaWwR3ImIG*vLcSc>9SHBHmUa?LK^RjbBnAeU6gn0otE6i)O z*?zfc9@?-~xx#nLM<~n^vm}~2% zT>c`A|C~r)mh=huaZZHJjr8TF`}*9c*)YzF^bHKa6NqMHxI|I4s#`Xdv0gS zZuYcq$?e0?Es>6&LD!vOF7cko9YWbwFUGdq(G1-eF}3z|m}|J_a}VI8`m`70#V}W4 zFXuK=_GYAG4$|5Y=8EXs+$PFCi*yV^wkwY-7RQ&zbw`G;(*bPLe?~f9#qQwC<6>gG zuhV*-(Xq^wQPh{msXFe<C59Rw7;*@8I0Oc*6}eYnB>djJTcdowdWKcxx|;p(duAdr*%y0lCqBdP%6uOc^q-jF41Bmi zJ6YNI?oyCl$?AEvER#J4W8(a1;97`1pPGfymW9yAtfoa)fG%lVXck)my5xg2V~G_6 zoDP-s@H<*+1z2GipPGZM0J*@pIy>qPLnPXgNmPJD&afDViM+2YJD&s=4 zMhbKdyfW&x+Xo7a3(cWY@G@;VA{wG4Wo5wEa><@_caKi}t%5=gJ4?{b-91&YRKjNz`S0aNhQGwWoGk`cgD-DZYkj zk`tyn<4N*p)ZK#b?U{@AJezU9jD}ytS1(sPTj%PtXy6AN^Za7IP_FiHUil`PLsiVx zu4uUHU_>&`JG+%D^SHDEVv#85B@BF4*Q9CXD zJ{oAo*Dy_T!c=E+wIk|o#P{~hMSGsjxZzm%YJBx_l@n`KSAkgI865K*YCtbM0_kt^f%)7R!|95nd*rR1t-EL@Ce zp4U$=Pgi?tr=@wZKot&#X_6DBI+Lq5F?Tk;w`VTe^K3TZp|QYA`06=w6vVuN5>43i z_9>De>FqPz3an?xND1KC;d%RvwlQ!U=Z+A}9%BVa5T!6E=I%m*p104wF>jze2*>m-Qt-wn&5_6Y8o#*W{PH7r% zpQ>1h)-cT}vA~y1(|G&TO94y5xH(O=8g0g>OOSMFnPFq#(#m-I%(MdQ(sG~`*rJ(b z1)iDJF*j!@%rxFUlVzsy_BkjPVg_jD!dPH7B6&r#D7|QwrWeg2HVIoa%dEglb8gH% zk!c!lpZQADc>64mg=h`aTpbIz!)(zUCI!i&Il^kRMYC3dWYHXDW7wiO+6rvZ9BT!( zXpXZ2&&;NnI~W#t-ae~jrt$V!7Yi{1H1p(G;7FQjTFoixMYAcrXim3D*rGYZ3cNH= zjJf|{nlFXXqBbZ^x6j2^fN95g`&?oLn0Ab} z&!tv?D|F-S^A9UPSs8Di%dEh9`&@1Xu-kb1Tww*C-Dk(#X)ww2_BmH}8*iU0V$1G_ygT*1zygsiMfR^+VcmxPB}CFKwD!W=9xKr zG!~e|oPB_x|8Xe@W|_g~!I*m}6&Sahho#_OjQC_MMAcOAd@S%cDtHh}8vl!}6+9ht zw@`ucZh2M;jCae+u@F^L!JDzbi&QY36TsW86>N{WKTv^jB6(d3j1$Q_u@F^L!N;*c zv_^>JuB`8ha>OCiKK1Zn-z@{N!NIYrNX@Tjt3q_B+rSY zk5zywGEOA@tN`uAIFanS)n?iS*h z=V)+>6c|T?GvXntrh@b0fk{+g91SjLt>Eu*_fRS@jt1vQfpIjrC?29}D!3vZ_!|`% zM}wXmFVn7)OI^;vuT0f}7)kZ}HXJn7&O4l8y$OtpFp?V>rRT#R|O9 z`ue!rX*7~Bjs`a>3FByRXFSBjnZ*6^KopU@ZRZE2An9oEhy=KlW#hUh?k=WA<7lu| z8jYjD;{~3NYH3UE?>b4vaQt*Z55v0|Tq^O?b-+(6Nkf z!rS%~FYnvp?gC`X^G$eKc{jcZ|HP!CyzfBYMI_I);4^8&`qrz#&utROs&N(hmlfC= z{L%`Lk+saoS5|;=)c6|gv;xc_#@FC$2{7ESiatdD9}6>$uffMM)A$;E6Av*1tfJlM z|A-Vkj_a*GQozo}r`-L&O5kE3=WL4pPmQZ+&n{`)&f)QQ^nVr33N;$?}dznH%A%og>WLow5TyJ5qO6hjrT%lDM)%RbeBNh3%Lo` zDS<}gz0g4#jrT&&M2KloW4}aT8zOn$3wuie8>VS?0~6YQw9Rg?71(As)TU{hU7;1A zwv6|}a4SG<8SjOWR)CT)?Qo1$YTIFnjbXhPA~uF?hx=Ipasls!-U;_BX4QBv^hu<6 zFO(-jJmR!rQSkR@%pK3R%=)B6U~DN0(`=?sR+7oh^jZm$o9R;|&}MpN!sXA_c$?|_ zCsH=k>k}a!aoRAs75JvjbR>CTB5*2`G<(>yZ7y+p3QcNy!o7_O%^vnlRhQYro|_0! z4Q*bW2s}pxW)J&dtH5iM3li?PRABb78>PVPVJ}OBsG15^Cjuu%pup^5A7&L`m1Fj> z54Qp|0JDdEgcV?9S`Q8WBdq{yK(mLv)(X&n%^vnqR)98R_OOq!b%hpT_OOq&0`Ib+ zDdAoZle|6bRkGXcVXsSsm?PS~F%jri2D{B3_Ng`r*lqT(Pm>_IhrP+huuIj`m1c4e z`%J}1?qQ!}Pw`4~eZn1w1id}%lVp|I!#*z&qP?{0(nR18T4naIFHg~E_OP$88nJzZ z3cfJmo=J^n5Bp+i#2tKixFkYMiyCiC1RkVDvxj}NRe*e&J?vW&t@g05O}HOZquIm0 zUK-6F_HBs})1t<^6M-V!;qvyd@3l6fT+AN!{Z@cU;U3!ZfK3yf(d=PAYy~)qTx?0W z)1c1V!@g5#nmz1C6Cql|G@nTX?q-_jQ{!_|z)|H3-im$R3Sh)xSoHf}v`JtP`HG|M zOA@ehj^R4(WeGC9%6T&3zC$Bip8b@J;4Yefdm=>hXv9Agfx-J>Xse$x6@H#pBhs9} zb@2NwX?CcM!)NgW2{N)cGu6XurFEKbB;3hRmvbQJhqsjGM$XosBto=?HwSkn0)Im! zZ}a|}MB3*4cUFL|VK(n~SpkOtzyI@uyM;-Z&HH~PQa0~@N`#m=llUVM=r z(OwpIhl;>fT4grx^C~oLpxvIp66$0HXaZ*QzKa!L)G(X(-K+pcn9cj16}q0qs9`qm z_p$y!p~>-uJEu(Oz0Lpdt_|hgD|texOwVtIX#8AS-~0XxV)$ z+(Jb5Ht+jOquIRQw<5%}oQ}(U{#nt$burxdK&BQ&t$}eJAY<-ybvSj|lUQ&8RSMyNn6*-bqQAH$Wm`-jWy><`w_= zFt2^JGh7rm=f%UkYODzJ(yubi>$m;Gya<~V=5b-d0W`wju{JwW=QJ9OzC1I}3 z4i0lYwJgjv(26kEElu9eaV(*oVY5#hPxR$7O*_MhMBjT*VP|@~#ubUauOM`Fm{b4D z-fr>KM8|hA>g>ql+>G5?&al|6HM_~1X^pxLc`-U@?G)&uzNQjom`D*Zz%GTEB(_KxdtHPHD5sA%Kk zQrCSdI}pcjn_r0{ce>n~$!Em7K9rk0oZ-tJ#N&5k+;zI3MdEljz9HPV%!jUrc0$??rhiS$S^(#)jcn{W@*7fng-(`2Nm zDJoyB(}Qol_YF?b#3J*GU~nHL*XKeQ&i`5Oh5C%d3H+b+ZpiVq_wAkCF_f9zBYSF> z_P*RMXj1*1P-q-Pc*9C(Co{VwR2mu^s_KYFrz5B!cceo})&PSxK3`QwAHr?>AY6d! zq(DbsD1TGH$Y%iI>r@=PKweuSl!8VEZ3eVN(gLLpe}6#+BSWgs%r6Nz+f zbyV5xHq5tQH&bE|?9;8iuS3@OuIER)@yzaSN)cpqb(|i_$SB^l$avFvOTlM!xhINx z+3S=Oe5kG>Q_#ImJ;CQ>bUiByMZN6-RC}xQaIDWTXTNTdZY#2_IyAe~PcH;~PAw6| zf4}pCul6#2tMm>K?4{lTd@-M8_=^z(A2fA+*wp#SH-9mOrP0dM$!^OJQ{l&kISi$K ztiF5+ZP?Pv(`ohnPx`x{_hdTHB1;**U$eswUf_lPfr4>-!-f^Cnpd!>xv8Le)q;Xm zbNIH}`SY5WE->LGhdTvJRxWQWn76F)h=O5wkLkQ+1XEkS zk=cTIO-l<<8TiMFn2!osu)KL`b3wfEu%!zc3+fUziTd*Tf-0|E{_h*({BJFTrY>By z^svTNtSraz+D_A|#>I2yEm+Wq_vS8O3!AgBanZar%T~`>ePmN(^ROlCSZFZ|@!~85 zFn!mJu3%Y2D-lF@OKF00P$m#!tn!3-n{wl-6_9W;z!J$deKd2h&viSxZL@rCAgiz2 z)$j;I-x6F6`Ft%=A9Gs89g^ki?{?33yYBD$`r_r=W*J^3H%ziAz} zo8prH5qAUZN-=vVP3e*Ec1xN9Nt!7ad#7~E%5&QeF`4yJsBujS_j1 z%JCep9M`9*e($g1E_E{ezD{lqk>mCwkZ}{thqWV&l|2Ty-9}}u8U{g;>S~GW73xg4 zhbgc=X~Y>up4oAj>&wcl_qjtd3!t%AepVqX%nkH$yZ2@#2D17T8Hrb?Yz{o$67n*2 zfZN3=JhGL+1OAJ_#csFE;IKZKhtg)-z79yU(b_yvwib9*vJc*hfTBt^)omHAD!nIa zvRyB?XJ7seXJxj}cYDGz-+@Re^Kb@Q9q-Gd8G%+Bced7u3}&`tX`kqwTmrS`G>E2} z@(yQ>^b)Byw#6Fi8l1XBeWGq!BJM0X+)MyXe2w?vhpcIGY9|#T#-!po^PQ>n(K(ZA zoM^0af)lTuT3=UO=fsODswyT|R(gV>x;Yi~h*>|iE-@uGsm_VDV)h41-E1YlHuZLqPo_JLRjBG z<&&q?#p;|%MRn5?PCQmo?Zj#ts^d=O)M)KwWFZf>#;oOALkf@2` zz?v1!OBb(bTxhJ3Vh3aS>fyz6Ry#}{Dd9%|>l={uLY$yND8koxL##64aFSfmv<5@l zvUx|&IbwNptAbnDw5n;1Q(qoaj>eiCRZgFZ-#Lv=E1%@V6Vp&ANFiEP(@^NdtAPY) zvKGZR6m@w#UdN+CSGKEQr={QnRH3Na#mNv9t<%-p-RxX>fa6!|8)vNG6_=Toyy(*znFTdr? zxoJiyZKi-jUQJJ*IJMTqE@rB%?b_<{87U%ja4Zixv3M==-)LGd8t&RMuBPp~@CDIjP1;Os+`O)g}IK%%*X^x!qVe+>{h*8`&~-8;!9~6?**ybztgh zQc+D}!eq2$R{0#SELfk3DGs{ABnNF|lIeq}(W$j_>Kn=%rq&aaOiP09N+(tqLorp= zp%$oRlqnh%b1aH7W|xhzgsW%N);r5qu2`IJ{} z&C452Z#MeJFw3yjv_lkVlxEgXK~bB-qfIAZ*$nskqF0$13HSvKxPom^!fJ%7Yo>a= zq|j@f8YR8@gke<`xI-JS^|EXS-37}U=dD7!ZJvW4VOZ`YW>m#cHXIz8L#95$*fA|0 zhoXcty{aajm|+GQr@X-oOz0wBKW!N#c-|cJEHhXzFv`n* z0vIrK(Q>Rs=Phm=x~y@<;?+ya3L)|)fT6frS%uJ|H7gdZUb=F{&}OXG!Dh(#OCHIv zGfkCXMr@O9GblTA=5XF98ijcSb;#8dGR3M(deq zUTkD`>Mb6Hny&Vy!G^k;M2#(9uRdw1ZT?K6K3b1Xu4xzo)`S@e*(5P@V!);~OxYVs zFbJ5W*#Oko+58I4T(-0ceUUScGqs|wrkX0II1P#VhH6;N8pm9SE?hC$OtE%NpeAX0 zPRnp&rufR44Rux3?1D6`$V)I)qpTBoLQW)!U)jeK%N zU2>g(K{RICBu^;xPT*HGb8j;BMu;)q5wvBz9wA=AfzqVlHCW7T397G-u{@1Fe2G>~ z;Kb=o$ruJWP;)4Xl@~gdRdsQ1#ze&Wy4si-%&TM6q9Gjz;;2=x?|aElNBUD+2B>0= zei*e8lg5lO;{z11$F&{^yk&$*8v_j!Z>U86Fd<+qkf@)8!4!ibOy%(AMMKSTl*c*@ zLrk3Yo$RZSm@z^UCC~YkUsYdfVYc2l3pwQ`KlM{=>lx`yDy+gZgOkH5$Mq>#lW_FK zTvUxJH!DHTREcS5XHIQwGL|&7-h^QS+B_C=rc6ed6k4ybiZGR{6LPdg8)fN@Wf5yW zf{r>Yu`p0_GGWq{HMP-($>k=dnF}Zo61CNI=v5(y=^AV~ zB>Q^(R8CuQ&xj(Li)1HFVqb1Z4x=y#t=3K|YVBrtwexdwHDiWkHNu#&%dC3Qjj^_> zgX^isBBx;{GFZogQU^yOiCR0^m?fDvQ(y^)Lo6fH+Pww_3D*--(Xo@`PLZZ&q`~#7 z9gapMzm3!wk`#qQAV)dLTIRJ7DGJTh)nN_LAbTf>aS#n!z&6E> zK7ja4-puXh!j8i^uRG0nVY-TUQ=zz}{EJ)4zZerCPG^Tq7IAS)9TbmjX~4;4@nQ3p z;UdzjcyupV;9c;oT(NS|B2Cs1{;xMK|LRVq1`XxPTo2e>S(%w^PEZH<`0hURjy8z)7LpsjEblR#n$duBhOoVW)oHcv-NZX<1UReC5J5%Np_f zVoO&$XfAb$*yL$uteAr{?ZtsElDyf9#cC$$gf2v6zgeiGc1#5dID~@q8j@Lg89U8I zi|HCuS)I1VwZtvL4^hWrCHVun#4lg9JU_8~e&fQ0xS!HsHvr74-`?0C^xv-ma2uDq zxPRh<-JYYfu|dYL{c!6eHJqOoPCuR=PLKb;g}IfIhyV7&EtUD%ZP#aS5L8RW(jl`!>~q%wXFN{ybkNUzg0TzHYwmz8=1wzFrx9 zeZ#mBllDm!`JM0nOg)^*d+I5lOl?$IQ6_Jxr+hMTPrXx0m|I%dH*@lnGTd`d`DEgD zd+YeFiO+Mq4{pb&eDEU`Y4Nkt^qZaA<4Fjk8$c ze6R!B%dxG(0q5LS;h=Mi!tBQ#P@fMe%>Ld1_4O)fKe_m_!v;WxcjG_p_0G?B+9AL& z$AJ#0kH6ds>%ZFRzc4whbDZ}s@a)L%-Ti4TV=QwU-bSJzd6{K}-kJYJoV=aXIyS}L zbZX`QK}y4CQHO4 z#V5s&#P7u-ZoDJ@G2%|~cQG47Hjnof`Fn{Bmy31c3h^lMZ1Fbn0r55QQ*pQ0217md zb`?j6<>E|njd+51k$98%fcS#=zW9yE9b2Z;UhFH56X`q3;|s**MW;%4y~kw3Y^ z^S%}Pqros-F7mz43@;K_i+>Xz72g-l@46#?CZ-&o*Ipbf&K8dnH;H`og7IG#cZxrY z?J*_scwdno(+tPOx#DthgLs~JulS7km54`pjGjDkh-iK{9Qtb%o+I*Y$4qylNS9lN zH;dcF9by)yI%Bt3AWjfxh)cz_;(6j#;{76Dzd?QPiF|y5;XlP(OqC4x5sSqd@j$Uz zTrZw0@@;)Q{~nR=q-XeT@k=qQohR=o?kh&bYH_x>Qd}pVCDP@P`tJ~*5I+?EExPa< zWW3HIpW9)0j94WeARZzfE&fgXhsXyadHz%42jaJ)4@&|b?;!RQM~De=nz&fxV~#xU z9PtW~FVmp>S@9ilr`Q%#9FKPrhl=CG$>Ln`Q1JxuZ1Fbn0r55QQ*pQ029qw+>naWs zOT>xdEOEJbtayfalX$QAviOnsy_kuKhw0^sdyAvQ2_m23XS}822J!FWjpF^{^CBPJ zMk3URi$Qd}pV zC0;4sAwD6#E`BEdBzDBb71PTX$B0$p0peleiQ>iL&EnJI>*Bw~Kg8}>Ffg5c#Qnrt zahZ6ec$RpJc%S&H__g?}*s-&xzd($LjpAYA-^I(sd&H;39pZOlcY3G7?tR6GSS`*L zSBmSzv&37(`@~npuf<=*j<}d(IwQpjak{ufTrZv_-XPv5z9D`h{wlV^LXG+diX+9@ z;!1Iyc$Rpjc!&6e_`3L+_>4<~G z5^H zD-If<{D@P;`C_wpuDDrzNPI*5Ui?$+vX7^Cpg30CUp!DeTwE_+BHk-LDZVFuE&eIy z4)oILBNmG>u|aGUj~7oDuN5B?UlKnTGY5J4bH#z;NU>TxP+ToOD84OzCjKFY277w@ ziACc6;@RSD;sfGq;z#1oVw-(Eefi>2ajkfo_>lNd@pJJ{F&ASU$Gbjau~;J>C^n1h z#cRcT#J9yC#f+hz-tOYQVnnPKmx_mpr;C?~kBYB~yTsgKp8mbWkz$27U0for7ta!J z5bqP86aPQr-UB+W>UtNycSdJ4S0icU8QGGtg~tWk7^}Lffi*>zY&DN07a)vfNiN_b zB-t23LJhr`&`V-!AOu41HG$9}5PBf=&)bI!mw`q8ZhBs>XfQHX$_?d>^YdCtA;yYEt zc^WopxI)7NHTQsc!`C(ZPDB4ZMK_{hrG~8~n`hEWaMHC&_NRt?Y6@DdI0(C{%0 z-_`I-4ae6g`lTA~tzo-{D>Xb=!=p7kQ^U(OyhX!jG<;1%U#+5Fq~UZ8;~Fl}@K6oU z*6>md@6_-G4d2%AI}LN|6#Wtn%QW0a!wwC5G#u3MGz~A*@Foo()bM!?-_`IN4gK|s z-xLiiHEh;!Uk$ftc#MV@YIu!?k7)S3hM#EogNDJq6`zQPbs9En*rVZ~hR0}lmWEeo z_y-N2((oG%=j@~CM>X76!-F(DT*LD;yh6i!G<-_K*ERf1LwkXu8`7{$!&(hHHSE)H zvxdiMc&>(5Y51Uq&uI98hTm#9ra|$Wtl_>IZq)E_4X@JhuNsD;>bbavhiiC}hUaPc zpoV|Z@C^jEn&p64$=3=X?Tu?zalKLtZVfBZG@PM-lgIFy8KxU-zLNy>qElbEbCwT z-k(tTAYl>y*;?P1YB-y)(6W$qEuTk%goMcQvpl2lukHH&5DkA$m~UC9>idf{yo@kl zSvTtYKWO*}q2IDz)c5ad_z9t~tbgnKKqKxUe^A3B4aaE+64D;I8iqB5N)kU&!#y+v zDT&9lMnWIqRCT6FzQw!;(Fh^rhH0fe2@p>PRg}_ z5OSf}C2S&$SXPUMQf|oE#e2Y)J%E(g3kdn<5kkIRLdbJEA>{cZA^3kz2)+?0NIUTB zg2?Y!(C~oI3xt!kewd3({eYAD;9lwjK2m<%OZmZ1%8Pp`FZfFNaKD^#f`1<&?$;7R zj$wVjl@RhAtM5-Bgj{Fo`|}9dfAszJgb~ZSTi@SL2zjltp+h$e_aKvMXn0V;wdM-R z`omV4Oi3(TH8fQsi*`Eh-c_M{=>6Xc)zSCJ zQuhG74F94qvM4hNYh;OgtSt|_|4Ui=$Xk-`<9`Mrqigjh7*byMtXehLzs1TZ#eZ67 z-u4XkY+Tb1Yg07!%zt9m^Z%rEDVobF>)o_rLqGoGF5{`ygFX1am$HUrYgy0m@Zh>t zn}e_fScJMV@0rwMKNWK_*SkJ3&|Dztu_`+5NGB*Cd>#@)8%y&9)=9Q%{ z*mpAP?T`D2E+a7Y4#0J0y~A<8D|(xEs(1N+skd#XdQad!g131YzSjbg$@gR2M@%I^ zQ|~ccXVznm$*$_Xzf--LsK>ZyUWOjOc?y4SyX}vg2TdhFQ}0JyJ9sa^o3EAwRh*9C zIu~!&V|$hCL@$Dd-xc5Lo$7U<9^P^NtXI?0luYGZmDc}B(uL4dP zL1_WrMm~J+jMP^?gpcc*@OvhP2=2}0;XBp4Y>~0(EBy&nP-5ux)-Z@yynZ4U4V;B`DPx6 zUyea}1aAxpF1_nf&pZRPbqnZ?Go2atrtBJAWYT*T^f>-R@E(h|k?(HQ<1?o1pI(BP z5CTHKSjP9mJJrkT!*>jsO1ci~J*VrLq7Kx1#M}UqFJDiiUZ#Ark5B81AfS{x~-Q_P43@%7TRWW+HRc@78KfGt%SFm{74(t9|JH}UBc%x@8`)MmOurPP= zxD)KX3ZAxZY5&a5KmB@VaY5sOji>I2+<(~)>y013`Qb+^61@H=JF>oe9<{CeBxU_k zaZ6-zR-?7`{Of1!D5yAfN0UXm9?%_oeZ@U_jR)T_R#Kn#v^}M0@t%zZjX773KT^?T z4Qs|fp1JIVoU0zcLE`qpEvH}a-D*u-OHC?RQ|Vyc$2ui172MMPVJtVl zCH3toUl#80zLD4R)JIQwvp#yj``4A$*4=t?79F!AVkLLXj9j*3_cw|g?|Hvq!TBrq zT?tC}N%|w~@YyZfK;z!e{lVIo+COZ|&uYy7-1d%ddgaD~9p3xLEq>yoC#<_a_XWKl z-EW1S$(eQrEIX#Hzwx*o{x_PpKCokX&%uKa>{xm5S)fuei4?>eo}Qytwtx79XTrCq z{PWU}a&sqb^?vk(7g9x>MWCLa+))5Yyr!-NFFA|sk7D+t zH!j(K$qmXbJ6q*PT1?j$FJd-Jk!y;t#kiSo-79*-MqhS(244kJJ5PJCXkEzfJ}7EWv+)LfMrORKEmsd2exeCaR0m@!`9WAH4GB zO~c2O!bTQdP3*1w;Fb3lgd1-~;YwVKKN0&3KC)LpsO+p0aGA9@zYVhcWq9##hs3sj zD?&0?EO^qtbOP%5Pc6pdex8K+{P`HTv;B7=`uP0=kje2kqJED5QrIEjKOS{*{g;7j zp8xP5zKzOXRE9OD|0Jw13jDpOIm&nq&O$?TInQ zzuO$FaQwN`F+TWvC*cdB{Eq=Y&VNh}R&@Rc%CXM&KaQbjf}iJy5x=(*(beAqE|dIM zfZAmLs40l2{w1*V9{$@wtUZg=IbN_hN1Hg#UND zTh^2Q0R*|HoYxTgXWGsQ5UbR7Hv6!Yv7N=39+cZoBP6S^ov-oeHrv?}v8*#}=M$Lk zOxqa)8PBqv5Tg9qw!{3kb8Ke`yysloxeZj#vz;hJIp21+V*t1SG$GQ3wlf7kA*}JK*BOtd`poN`0uG;hon_$HlI5(2jasvuJ7JQx zEa!BzetVX~pWN%na#o-{mt;Ac!7rKRoC(mG<$S&u7L!@dL3p4$%XuDNv^2}9g?}!~ zaxMbRA%K2~2JF18KO<{#nkaQ04k8XC^FIh_7G4bEAdx6@=I- zoa5nRhvE)ycbIS<1@cwl+&>1%f5MrCve$(3PdM7^!kG>5hH&t2S=O7v>4ws838xj# z`*gN*9?G7{b_!wLzhpaoVEb&g!}QnZvYj`f-}Bi{2b%bWY$q4U7qgu=FwVY|?feCg zzntwXg&W--a8|>Q?g%(f!mM`&oXKdoy8_PIe9O8x=v+F(vMvcam%{}w4LUW@_OhTe z2EFm}pu_W!D}v52X#OVX+y#@L5O)3zE1ej2ii7A4)0{3)88ywxgHH?;In{9IgNqy( z!Wt}cjsV-CBIh;K94>N>LlbW zI)8_kulmq=2lnj!(D^-d==;$5`DpaJ51mQSVfBa3c1XSE!<;^tX8^yGkn?9Kd@wIg zz_WwAcpsP{UfhQU9OgwM+;B55UV<67@M0d~(vkCV!LR;2iWi+Q%F(>I8b!zOq7@!? zEH55G8~lP74d_hA@!|u>ay&1*Xx1}QxVQ@%|B@GeNP8wP-h_f@@!|>C@@!rRD0yfv zE|`087%y(YjiNcZbzf<^@b_nm` z#V^5v{}q&T5;|cPFOqNu!HYk@P(EH91c zE5tmMjcT*R^ZM~NKK@q`AXzIvOFSr?HdF~QBw8U-!jGbTgy+Sp!pnyRi^1nT;hc&q zCHIF$Oe6Ql2BGABTZrpXnR5RTEh?F4rzxRZ^KMF4&7A(%C$)@8%HXgo=s+dT&C^N?;GT-u*;u=2@ zu0Le){-!v~^0lyp2wAell=v*)YL*ZIeQv3C@Ebo?a12Hhaa*-+*Ps>r7A6sQ7(}iW zyb6&<+-VR2E0_gO7Izs$jum`^o$qdgaI9bo0Z80y5HR|_@NjXzL7>;6wQr~v{Dq0| za`aDeQ?+!L@Ke)q^T+DIk&u#NK3eU>DCSQQip1lZ0DjYf1pZVl){?*l2wdV}P2fEA z1@RQV#}XwZ@O-uN2nigF_#$4c9(Nbe9_$eZr_KQ4C5^yuZ3gk>UvM>pfLgDi6N*<2 z0&4vYp;x?SXn+uec&1u>B87;c?Ahuf(hsjjcoT0`2Phte_@LTx5EX-qrvd+wp~!gR z5r3~1Whe_zq!YZS2{6%Gd{P}CX%hIV+W89!Or+3XYXV*f?PIsxVGN7L`33<&{L3Jq z#X}gk#kU3lE$Y~O-x-A83T{R~68|;`wAL+PD!w-epB4NNQBnM05CU8fw#API0hUnY zvug1T75Oz{p!h;J#|yNCuO>hhsYrf}!{q+p^HYH@s8MdG+cT#|%tu)`g)lF2Ym`Gg zL|H;L0g@({lA64qu+q&8KND&q>@ndl=(CX;_4AA1GOcFRv8Yt|4}6F{YbIZeN><_Z zbix@m`bQ-}YjREAC8Tu*Y3-qCjV5*W*l{(^?YIn4Br8O69;+Zr6xE35aUFJO#j!QT z&!BWPsZhANHF@8%a6cB#*TUVzwyaJIx1eU!M0A+K9jGayMz~@&e=I||x|+PbQ7!xr zjE7=xEgY#+xY;#MHwr@(#R`#}6t1F14Dy)`7$ZcL7LHUXTzgI4xh%W_A7Y6X?jCwa zGA-PSno;+nypTU$FZMISeFHZX`)3H(U6c0;X`M#bS*C>}bqd#7<9vb35Jj;E$O`v)6@vc{?!aRsIMlH*XHcDBvzUV}9O%1NmXt#Q7hRHGOq ze_Er0M{brCT+O!odChnkP4EMj!7|Le#1V!Cc%F{An>f-S6wl2yVl12?d^UT?A)4oR z3_C~F1Sk!8o>=2th)T*5Cu;)eAxiO64Mn5)=^6pWgRg*s*k)?rA5P!hV|O0?qS2-dtW2pfu$9yBgsnC1qJa7}ZgsbNfW zlR+5M++q;MG`AXr67$L$@e0M9hY#^vE#`8LKeyEcr~t*hx5k-)4ya6X|IVg)U}w`j zXjmB2{K+5`&pT^GJIIB7WOKLXnZthjP)&f+kmr*%&RgWUmAeT~8v=;sA4Gt7#vl;O z&mRNCUkn1Vyoe*_vjzb-x)pO*@ti@xR)?XJisuai-o7_I;{}6&+?SHeiw2?OezZnp zL(1?rcB;p<+}D=j=B1hdHKN?F*EkoTQgBbk{5K5&OhXRjIQF(dU|{30OzYPMaK1 zHEW=u?b-l!re^+Hrwx;e;3ir#r#3w?T!khR0fT^Mo9Gs~1_8}3rFruV0-Ei`Hp@2% zXg16q9W)4Nb}XY`fk8mCU(sBn3<8>c!5L1-AfQonjEstOQ#-Vh@9WX6s2~szE@rm)I`T3_@vETq{~3bohcQl!8K|lhCSywC8LV|D&$?dJh3g|Q|YEKbkc*C5bf@8<)tpFu$G z)Epr8HwXmRPpQaH3>PTkkjnuEftWObQ;C#8Ahv0>;RuR3{h&jIj^wDNZy97=!;;EKV{Ac*gS#V<#H~taEuK5T_V~>dHT>6~*X} z;ls%A2(4Ka{8XG)8=%hA?Ce_SNmL5nM*O*k05qFIp63|^G<%Q{;e3ODX6-~=U=Yyk z>OFzD&>*1M#cYv_3<8=>ri=f|AfOq3y~Yy1HVA0;4lTUhAfQ7u|E8#OiCV7kB83NGkWrm<@3<8=x%gMmC1_8}(XQ%nS zK|r&+80W7u2xzvNUGsW_fM#EFwseC*K(lk`z&9EMG|Q)TZZZgHb~fd>*&vi=SJa9p zAar;%W7w5iv+GIf*4hAdre^olIyne>!4v2>_tmOpLIAzrA&Wm4ig5TcHsT)*0#751 z-BByb@pSk-2H3kai+pPQKy84`$>OnEXMeJ&U>iT7Sul+4M&EpDB*lkn#ZjcVk_tVd zDc%i2;?K1K@*>3-YMtMc;(;7XUeXlt#Rb9jWc{k9=tZZ7jDM*W&yu37{G6tEGDGca zwE^-X#dm8RW&{QU^zZjI0Y5C=OQ-tKAW#_;->MaRpmKON`{z5F;_IL!KB^6n7b$*G z>+oMLg9VINUugm$Mgsq+6{|^LBIW-~6S#*#{hze~k|u$F*E&a&Kn>&D4|0IXC}6~owE>bQ0biZ-0131+xcTeUY)DJssT1#$z{B+VtU5L6@Nfa^)CEYI z1Pbb$sW9jmeAzQ*Et-H0kF8?|A8in@62GiNj4=o`66e;5#dtc*FJKV)nnnLC+!WUZ z$eb)D)Hz#GDfm6DG*J^^OP)lhouUz-PP2`x6a25y@J)E476K|5@lNhtafTs8|8~(7m0C|z(QFYFh5#vM0Xae*h=`z1CjcHuwID;@Q zbG+ecT;>FWfSxZ?suK+Ywmphd)sqYYw&lNKic{)TEQZ`c{@9;5&D6j=i~n>ewwW5n z%g!(eHb+SOtWG=uEy80N(~hVsew8;DqZ!06>jH1$M(x=XEw|_Wh|ajqrF}k6BVmtU z)j1qsf}f(-itR=Y41fG`9&xcjz(Af-ATBWov_X_H@=}Aq@YleAdYM7M`Htcvmm36Z zdJeh##vowAT-LbK7#Su!kLq7#5NfnLzfRl<8N-h;I9#Y3HpPlp*9E8!8}_C;=LITq zD!cwIhDA_%#&vb#I}+H)5Osql@M0crZmSEBGzr{a=S;_JJa`*>?jO?xf-4#29yAEF z7kusRI?;;C;p=ixcCV&*9-IH6x&V2R;!|}F{}np86(8amO#o>Y!J8qo_=`qhEDPSn zkoc@dWZ7U*C?2a5*OSEw9Ic!<^mTl}f~N?corrd;+?txIaBwK>zsb_EaoWm=}6QTDYVzzN*VtTGh6vVCUMi-Sn<2rg=7YKp&QH=11^ATLs^t(WN|uU_0kil@*h)tcfCR$NdYATLr}SnuQ_AO`OxzS+nKyZnoCv={`; zP{RJ!YIq_HKL)oI9R>k%;2EnIl^_>>io<+D^V}W0M6y0WX?UuzU%kUEsbDj;JD`5t z3qWUaA{C;`tTYIC$iEPKMXy0HjAV(W_2MkD_y!+hd3_O|4%e_*SJwx~oGdofI|9Q- z@P2yxK)vq1<8b^>76%)|ZusF`vKTUmVr)iIs?CNcr22qfrlRs>A97l$XXns@}PfQq5!>KF0Vtn(tc1)ng3;-RnzAb(}#!2!8L2 zIKdzw#IHC9IN4Yqoo73{=qU!_lg;t7dT~FcigAW|M7`=fH)rGKwE6($rBr9vJD*Uh z1rgxSH3TRXd)avgfq54i_>6iHf{I~&|B*OTQ#^r6Ur-+)FIxYydgoT4f*TmzuQ0Yn z@cf)@_8Wsh@VtOs<0^v~Zv}6lv;Ni~#$mSIQGqq4F?JA$Rv@l12-xZ~w$JYk0=Bw_ zq2hXjfUREO6zL{|@Jl!Pb-j3niu{9ppG} z&`hQZJYf*f>`qP}o-zof*&X%b76=`F6H17?v}Ok}Vmw_Rpw37f%o5jCJLh4X2{CoR z3h`v#6XNlDR*2`@z7P+o{e^o{Xn#%kE>y}1@w_*;@CBN;P~q|mKcS4HYr^b?1tFfZ z7KV7BSsdcY;rI~G0wW=wy-g~t#neI^qv}ox@oa2*h(}K|LOcwb8RA(>S%{|}6(OD_ zR2AZPH!blG#cOtm`}A`|+|!;P;{I<GL!l~r+hI%3y;_A06#1-q(5SN|HLtH!V8{z_R z{}9(`2ZXq;T3L7!d|uSmNlvRmT%z<9o=sen!mSQ*)v>maKbb7{SGWU1ob#^_ah|?0 zbY%oNUWHflnX~F9(b7j3-om@H>n2^6jpVGtIb2qqQ#a`t5hYCMtjXUdPt349p9PWw2JvnK5 zMAdjI#97$Wg|mr!u`YZ*D7_QnjOeq%eTaLvE_@bnUlnu4V%f!DSc+9+xlbEuBn#T*+O?PBI1Hrd4-g%;UkSF&nXeYgh%TI^zu6D#dv z#_~S9n89M7D(WmMMemo1HGR?aY)IzOtTqVrOPNQr#vsry zWgg91gK(@d__Yg5tTPBqGh|}Tfd&CnBDfw96`R0N<mG(aC({4^@~Z71OiBH;V8Xht5*DbWDMqY!6Coh1}P=FyyO zD5|B$=~1zT1Y{n~8Jd91qd7MkAZZf#b=27npXE;WWl&D92xB`tA5RO|y8 zRUXYnx;bPX&Gpd$Riq-fN1gqsh|Ht8Qxnkbd2>`8NdhvD=2lJMABB|0jv0>ND-;`}W-`C>e)6LDUPrW0{qjONWiHI<0-vZ6Jb)G6toqfP?~ zLlgc;Q1!4)eq58Z=;gR;IU#_E1AJ#$I@DT8_lyoUS;t7TWdw? zl=O?JQ-s10MY2L9C$)MfDrN#bnp%wJ)2y2p%WJ}=(kd7m(N<2(*?=;YRTGG*wwlaY z_o!Hqq^Q-HSl%yLNv8f3$5dO%)St02x2+vPDu-6&L_AGQ6wuwa#E}8nDAgE8%-@n^J%(pY0Mb{Qe|_L$5fz%3#*i$N{w(+ zer6ejN$;4W5lHV)DL?Z}4eaH}l%M$qp{%fHOq>UXD&=Rdmw>coQ)wx zv}-YC%FjkUHjTp1J7Ku)FntkOJX%Fl*a zfYOlXaLoBFdCHWZEt-I9nyrSSG0kBb;hN^BriL-i;Raz$^K*kRra8hOl$ZlC@f5|B zDL;c+Oqud?WGp}hDCY4or(}*X&51jk=9HaHbDCjcOmn(HD4xf}1W(CS%Fiz}Pnq(w zEf%0O0Sr4IM9_#A8U%)&^Er*b$RIH6$dsR783f!&ru_WcAYdz* z^0VC_Ov=y21_8M*C6`MKLdkt*Oz^9hRLalUT5g&0b7?Fs2LB6lZ1H=8z!)r3ey%eJjKSA%fqR2NK=*R4)NeEh=q{6jZZ-(0DwBe4 zF$kzClY(wD2xvAPb3$>uK`70xh>7PQbok8(%C6L!$)un=Vgc$*&HfN`KBHz2a<}gR zO(4f7L-0K@F?t>d$lROzGy$1=^QTyVq)Fh3n8UA<3YOv-@zh8HkHo}M5|Ak_k7)uj z#pUT(fTT&_#h5cl0{ntm@$yIl&&I^LBp@?Mp4S9qCdn(Y07;X;TQTQd5|EiBe~;;N z9khkaBze~u1#KZSN!~LEw1vzh`N$yD-1N1W;CEQ5Op-S=Pnk*bX)Hi#$n)!%b1EvS zOp+aj031SQlKjgcu(Xw#B;OeX0;J3&`L{;6nIu0L1loUG1eUPkdK!-Qmzg9UgMb7W zAHRqRepQyrB>75lmN=3qk3lx!=B!vb6N0yl+qYc7jl8iA3 zc(%+WDKZG9yDu(&54BV#i9fDJMVU!b91qYc)O|wS>8*k8GLvMYA%G^5nIw}90)8Sh zNv0SC{6uDw>|qcvhRh_HW)RR_W|B-d2|NoE)XRF#<|dl>{&m6;@^1_8}vCP|q= zD9y&j#R(8vWs;O=&15D?c|1U!soA`^!*3T0Zshh{wI-nZ?5wzWlmukL#vDyRCT!Hk z10+oX(YW(>5_p<>Q1Ouj_KqWi4g_Rg!~#v=89XN%;{lQ;f!4S)6_tXu*gFyJBMCIe z#bOeW=?9B70hxZVBpx7X5?Bt$BmtRzuy0&VS={u4{f$vzC7FKk6NA9h@ck~dKUv81 zgQc2XDS232 zoJoqa5opEXnxf1$I5r+2FH$@??p#NTGTY!(O`t##I6f|(BLSIhaH1w4vkgv<2S}O( z&WSspk$}uLIBz6@U&h7gdJvG=24`skGTY#Scz~oy;F7q*uXDaz%_B_EL^J7>FYEBH{0L_gFpn5*#NGyyl;;C_w3Vv){uTU-S821S`|aEGQSvke}I2gr*QAB#J0 zp_0lrctR6!vkjg!GQ!&iIX(TeK_J@5v*f2ulti>S3adf!j6opU$n=B1m`9+vOh0(m zAP|0J`oZ%CfoLO-j$be|5N+hq@r$Mg0;^0=c*!8pv1Ee6%jOZK`$KV&y$^Jk2?~#B z-DQHpUoogaVe0-4`YtM|{DOBiMa*wi3%+MqKvkJ9@_|8^7W~j4pomO3_{bm-M`gmn z#|D8hL?#^kLnAy&%s0^gDW*&~cuR{Z6AnI&2dDtW{2KkAVty5Yd3R_6>}<;!w7$~_ z{s$FDQ}q7@pvWy(@s+0dHpAoh=>M8xR>CPoCFMrGgc_e2v}6iHjz(xVvJxUmiZX@4 zlTc%nOkv1N1jvgr7ABk{NKvLRjL`%bqht!hZW^Ie7zz^Na#EBj3?WTXrZ9|81jvgN zCnuZ(8;oP_p$WJt4AT?(4AQvW41+LkS88|~x2rG+wARbxV31h`f!2~K408+umXLlp z-w-u^SYv9K6oxue!}#Go1_3RQ!Z0BrPKOpMg<)bMBZZ+M5nzdxOH*vemE899Q}vdF z^EV*WiF&(c>7J-}XoP#BzC zlmVd*vJWs?VnY@#wJaezNl+eSuh7jU53*M#0whBMYZA^T5|9Vk2O0vlB+#1>XOX}o zoZI&s0+_dp^@#vUlfZDonHB>9d62!u5Wp-)9%LV45SWO{gY2ya0UwhG*@qeg=791b z`!IuGsNz=oPYnV-BM-8FX4(oKArG>DZV+nOFpv-}5J??m4{EvPLH3b}05ziACnTJE zD7QSwKFP3v-0~p%WQ}kSvQIHJ%vAL>&C@-|-ll7~2ia$tN0c>>O<b?} zr-u~fLH0F<0Q8gx+1Do2lw2QV|0W@hBSm?TeU+vt53;XI1jvgNZ%sJQlcGGxzTLazyZ^=_0WZ$fL%7g4bBm$I%JReOs`zFA1 z1$KYL;qUTzp+4JU)(0ok(37 z$@7JT_>w&Dq<}AJo^!C#C*Dp3C=E9UKTbH6jZj>k;D4GJ_X5!A6a3E&0$oF%;D2Qh z3;|i^JqBS;@UslUoZ$N!(^AP3 z{A`1ORPqGhF$g8qw+ZnvrIIK3|4w9_;0GE5l$XX1H99|82&v==eqo~?HsH7N1b?(a zzy;(9evv^SYRD7(u?7JlE|A|Sjs`<@f?v?6#><;Id797| zpuCi7YNK-;&V;f(HXD|AA_{OL{9_BHIJ|4bT;q>wFebF#Iq#(rI|H2S= z%Zo$YT^=9ezHubPeOi4yyf`N7P6=@zb$W=~lruuyIGh>czFb*|J7pCi?mOw@;k#mz z|LhQVZ03fz?J_^ay_1>{H$dt_+>+Qk#1;R75ZAu?c(^hypNogMYHSQ~>DLtE`fX8& zi?Egu*GX+5u5I-3@K*IiGQ{OdSBOiDr6H~pmWMdm-#5e=`~D$Lst*WpBCL;xUyT>u z1^rhQ$^_NF#S3r6ojxXhO_i+lQ!e-@(_pqr`3^hcOuMRr+cTEV>6CyIl|(|RvsO1 zOoSJr3`e#cHgRMtkC2Z}m?K*bN;tCRD1akdhHf0$GT!3IR-P^ zt;Dq;BCrkBMQNj#-YgCSX16SH3IM)s>VP1=1?j5EaMXqQ*&Fx5*N52L{_rize-ah^ z-%P`ef8}nlg8$-ic)}kZ%Wv55R(nvX*Lx`{Wnb)dA6uLM10P$0fNJ@#LSL}`^7o}I zFMqblx54`|AK1ObePAGe&SF&ExCb8?2S>O4FH9kyJ}>~EEdr1I%$tKs+2!bZTD+t4 zSMsqBM)R>tN8vHcdn%sxo#<^~)xmVtQ}fSY)k{Fg^8b7<(!LG{#GrjLX`ky|&j&t% zi8SpC^6%yYf8i?FzhzHJ`+UgcyTbb`6pTLzPZ#*ED#&TU7ftR3`}wZU{}bw3B{!q8 z?|1ShtK@#H1bo-X8-K|*bU5F&@+Q~vJ{!Q@@4b(J+U{AtyPa*IG+`SI>-*y*n#1;F zc_!?!JMRB9g?iey*ArPcc(CPrbUbCVZI5R{c^1l_m`vqxGUJ)Bk&--Pp7&08Xe#cX zD`9(}x_81tw1)4+5;iO9d##CCzB|Q@;5=zCgp!v6V|e|+7+n7~B=s2|M?rz__JVIw z5~7e+$t5``|JyjL6Nq@<>Jlwop#15NV;)CD#-j_G|)@1y9JRFZy zrg&eaAAH~?WecySPpkVxX6io5`P~dMvSlwqY6gYOM3O82a zy{uMfhgxu#RXArR?k3xz0o?fui{PlfGCTAO+~pQN4Z6M>byrY$B-EXDV(Y=?K3%RzA2%gs)WXx%5FXNevkyAq^U#kWgQ^57$oIZ57KlfIoXul;g;No zE0oaFeZ)@Ax&ohpL_Y3&ZSUcf^f6$j%|&d;^{uuGMz_Nn|3+u>t+mHfAFHq?g1dG0 zc&e0Dco%B=4z$O!q8|ib1U7IN?RAjteHAypaVW|DWRhvy?1%GPSoZ?iw)4u_w%PoV z5Y_bAPvzgo;u{d7EI)tb#rC5op_gw#<9YoTp+U3!C*f20=h-0dFUPQ$?SBu=?)Tpe zZ*=@^_{{OQ03Yyoq9Jqr4?}}I|140*_a6aKf|mD0M!7e3DLQ1xfwcal4>k37Yp}++{b~`B$R|2kD5#*$dU3r|?Az*QD;U z3dd9IW_9PY0zV+8W-qe6kAls#lfht0_A0yJInvCFps3HDNOo4?YZS3x-Pwhe5GZ@K zy7LrHLk!PeV^3rwcng1yhRj}TPoykag`c3`Wv{a*(m#BK^{{F7f%Zg(HhVOFJxQY602onMhjBw1O3^u@xqCW{nCaaotvq z>$#({c>QM>#i^ORH?AjV9gl~+rSNZOpUE8(^BkPo`&|T>hT>JgjGs0U6FMheknBVV z&4y*1#?Vw0SS58caI-MPf~=A%-ZaVJ>M!{bZs0V_fS+4(M;JGY- z@d3D-oYjZVy$;34RQW+pQ~7}+8fRjb^Am9iif67HfRL#%SmIfe-hmr9Jw;VC(&VhA z0OR?4MLEvj3cg0&lJ-4N{<@UZD!CAWz>_t&l&y-OtRi$Z%NP`1$S8Xs zvgA~T9s;WLo?KiXGMZK|y%(D0Y*p7sz&ts}?Zz+p%B79Rbf@_~2KjSN3;BS`rOD@; zGTTU23_hCH5w-jdryyQvT?DZBtrqYJe$CRU0#9?jw&(3Wq(+|_D zvzEHrR$d3Mu`6xoE4NA&6}Ic`kb0tu+Sz-X+gbRkKFglumEWIf9}Y^hIk*B-!J9dK z>jrtVka2x3BcnaVD|^qpb$wecdk=L3p?9Dc&kxT)g>O7LyV2e8Lie%ki+Yw>R<)%1 zji;PcIehR{&ESgqjilZPL=^8D$>m?3AXQt3_Zqxw`v)P%x1Jy=9}UFec-L*l*ZkYx zd4gc;5{H-!CP7O1kWhy9Fw}9=ouxgSo2HPKglzSzEIi-PT=e3dU^S`g@wod1-cr>|aB(5tF#fUl7=W(U{I4UKmGI8%|Vh_&%O{18=3|L{9_z?R5D5B)pZ96Fu!za(^JY@Ky~wSt)rQ z5NF}7l%1lLohy~yLn)h95=1O}h9`F-gpf+|CrIwcTPpbyE?&Sp!D>>;PjUAV-cm_^ zt8G5sP%?@SrQ{=(p!mJ*I_e~p*cYASD*3%F9W{#Qc0NJaM_Ix}<23GUYD7j3!$=oXNTA5Z0(!zqD;tAy@ zE0qPy(Pj932uiJ$wseydfH)d&rPfMYy2;%@+>E!<;&|Ki>IHK_`Fikl6-dh7xag0V zJll(GJc8aYxsOM!>KaDCMfMa%@_(Z6OIBEHIt<&$zKFeA`c44`5kKD2t2%J82yf{_ z$Kv8}-Y_O`thp0!t7S?A^9#IlzRGENb&h56o%3Z*YXXsv@0=b_PU{(H2flNDhMPk8 z7T-Bdc24Wn!1A3F$Iag{Xz-o03Q0EhD0`3maKM{CF2B2IlwE)k%`?TqktR@R%`uiY zza~%{s17uT5%F~i0;!l|5#yUGL3Wny&EGo^KrL0$ zO7v6GqGZ0i)>M~I$Sh9_5z(^A$I|GD+5r0DNtq9$15hApHf1V&XphnMw6V&}Q-xG` znk$?(^YjtTsF8a@A6iwi##U^mBvfE8(xqxMGfOa2!bH~foqfjEjm3N=6Xn6+P(IsQ zs6B?a_-V?_M~JG_DB1G+j3uf{KLiwSXO-FejFpc8K@B6)(6dE`%V0)<+YH~Bn@JYG zIfdJd()l}+9A$@m3yRN;NFZ1E%5c)YJsKd7 z<$)DqnG}C-VO56pL;K85UoSZEXd8XD683I5>1cchaq$^Zkcnohryq-D@?t-XyS%!K z(wq_jyBiubg0MBpK07*=v=@%h2Mn4FU$%6!s>_OtMw)7bp%#}x&JmcFGK-$DG2b*Z zCJiG{XhOJZ=4&_H*j5L@biA{yFYS))yh7At0Re_OU4V-bFHGD~Np9PkN=vqz8n&FQ zO;lA3663diA$Vdt(f{LiUXUZW5s;9?1IicrJ|gKc#y6<2m@kyev4+I`){s>>lcHXg~BQfAJ$<+$jj2D^?BsvI=l$Tuu z$KtIl$*be=Mje9l+yY$e;1uyR^p8U0z-Vsc3zQUhB~+#@oK}JZE;7> zC79e!g8Qoif|YoCtbqbTLp+&59McZ-nu&{J@P;}Dr3{ZH1ZY&cRx)jtVINkpr4;f} zj=KoYc(Y~X4L)RZ*~a|Y*3Z!(lWo~>B;{BG-m`3p;w_(ctYL$~-G98M00U_WqIj!T z;ZeuPA>UvjNy$sq146hK(%-l9lC`q6 zxp!d~wcG@2OmY*Jc{uf6pP(=h(Qi*HS#WU2EzWU$v zV90{F1m^iAvLErG3_U1XrU(?&0>KWWnURjZv zm8zBdbP`%C+KR;??otSFmR%HlEf%x3PEq=Dz;&4L!YU`Gc1K zkHr`|bSP7VHEYWo2KzRz+qfyVX|TW4wZ+!qL1_|Yk&eMl2ln?450!Tg^b8)(qF%KqP_UfwgXt{lycKQ{F$G;#$@%}CAdi%?hiMB*% zLuYxjvikphVg4_3fDaD$Z0zMvrT%aDIGqi@V3XQBv?|rBe}b78m9ifKMultsj}GJO4@$o1yo+VOceM?@hCa(UArY@c_DEh65E zh_JmKW$MbA7!i@(QC==0s7jdYs}lA^QRv-Lhl)87B=lx7y~InV)9i2|DK53eH1AAO z?23p9-Wj}F3PFe~nkj^@LdxckK&q)_qzk$BD+7~=$n$x}Mno~#7VxG)O!3*cfJ9SD zaX%52X7Py$)SVCIfm#8okD4S3b{C_3Q$=1S#4emvGNGJLEDrm2gIZfzbE4EIPwSQE zn+5) zKFh$e%7>EAP~v#Y(Dak>kmFlReI|=q=rvw)jrd0I#fxxQ1byB@u-*f@_m@o~`N9a0 zV9KWSg?Dbk<3w7vGmUKE`Nq#}(crxpjo>dMm4do3>BTBl6k?wiabi6ZdF&bQQ z7l_d_P`?T$wqg2dqSQB9RF#O*G7Ok6oHS z-)Bz{6Uw0+Xu$P+-WXa3Okui~-8vjz( zp&N~C@H9u5!@Hh*y~WbK@UO_W-PqZYN+gr1=C-8`EzR*%LvmqvYoe{o>h6rDI=dRW zx;s-1@pv-P*=d=&v98W;JP>Pd?Py7KB~o48ZOv^96Y{jNl3S8IEmKk3w#jIZeI>ckaxYg90jCVC9tRTC8`li4wPc82-!n9n8qTy% zJkiwS%9n>q25ftg*SV z9S_h{mHOHmTDN9ne_sT1u|fA?BX?s1EZmvs>SAk~#!TUt&HJ@QbnD0BF-@@(ZHCrK zHneq8TRKuowo^P2OD5=NXmfg+da|hldncVOiDiuyl@{7~SwnMIT8iY7R21HdEboSB zONOr`x|%?{qiF>lxjmU`X>MEWKDDg5u{qVyA-yct-qx0gk)^bFG|{Sz*x4P6W%_q3 zZfNZ#-HGl*su4D`S~?)Cdajy=O<1&HTa?aixf=Sjsm~$_LY$DZtRW!}={Em3teunp|UL3JnZTZcMo}+n2^# z+uK|LV-0O7*%qzMU6Oe+(EuOmY+l%Ab*<<~Sg}|~+FRQ@V+a84FnFRXm1t8omveO4 zN>C9TmG&9H+E5Ao)Ph47WO&REOh)WU{lv};3baoWMPLpHQX8B*;X=+8zY z<8RSq^TMVs%q}}!uQOE|LDq`3b+u-+CE6t3(V2`TDwJzOB(}5i!L*Zg(8*q*s|)=fU!&X+ zx0bae+7@;-xm8WSV~k_8)GqI~X-{9@py@#_GHqnIg4=mwO|YWwJv(=S1Xk1a-7L#(TLX-4BPz<0u3WL$T{lQgG_Q}GV^e+42j zjYQw&+&6W|;JV>{*`Z}G??@z@M%} zS8r0?Kru|WU(-@_MB@i=gZ6H?=ki!05l6=+fx-SYJ$-|f48QG5ld)t2^ET0ac$NhUg4GlSsF&#iT7OSA3bZlzEDBgl;fLk}l zA-lN^0i>~^nNe5`9qdqPx58N4+MZ14$cNy`VF}_!n-?;Q#t;;e)_`;wmoQ@mg171W z@dhwut5wQzEN$bChHf=vAktaQ%}7egD9dyWJ;EjvEs2KCjNw9e$q zVYjA<+Np+EtUK8d(}S0l#8@6pHFZ{`x-vsf6U@G>0VeHgZcV`BGnJ;(@gY51V;kyu zlhr4e=qW~-{-GgE!(2(2sE+mL@Zfq^Bn+yiQH^Jy@l%MX{}~}nGhxoSuuaYv;Q)!` z(nP#+zMk#%%Bhl>47pq~hZQyQ8D@rNBcf4zaz&~UbIB$MiCqVaa~{m^sAp@;rKOt^ z<2t4!-RbxhuZrur05&J$2tw$6hy}4I!Zbibh4xywHv`6+eny`Dfpv)SV8kxQ7OoyS zC1b0aKHbvZ*(K}9FpOE6VT8dBi%M07~C|_KRCRupHm9+P%P2X(%sUKL_c5H z+=;+O*WbC_=|gfzM#NF>UP)tEh^OgcTKXL3uc^)^%+W11`Am;jR6kXjimvEF!(`4y zTN9WZ=&Ah9jGH?!>({fB4!RVAa8qY;d7`bgT{WSK<@2P?Gr}Jmufh$0t}|MjH)hUg z4Sp8mm2}tH?$sPC+L%nZxAUxxn>VCZVcYVcAs1P#eVcRM%r1yX9jmh9(Uz!dXV=eT za*Wj@tPC;Auej)t?j~p8rg>xpaVKdbVl0O&3=YCE*ZLx$I@Ot}tQ$ziO>w4C6%8anqvub^Me#Su7k!+Nso|(8x z_ce`Pg`BO9XjglKMYl;Y#n9N_#8-2lu?CR70EIVWda|KstLqeVb@!Ibf`N319o%Zk zWfTo2N3n#3P$q-1nn4>LyPO2;hQ-Rb3v0;K;)H5hj<|CAffB1r>qrY}FB)io7vJ>H?1=3>k(kwpEvQo|2Y9^;feYyeX+*oj7 zj+LSM@K$sbZg4UUGm25O8w+&#{CxHNe~~yQ>&%mlCBsXitGmMtY*;_&8CvCBcv*aD z6xvo~D9;H~Ra&8DEEqZ6zz8B|cWP*D#L&tX!T7C)STn=g(zAYZ+K2RXq!n`qjQSkm zq&qdD`*b$#dNu*?YVXGK17m+%V@q?4A+bpfB{F)Vx677uTSfJSWFnTpHbR^T^3{!TBytH@xf6VSKE)r6sWtlgf-ekQQ{RP7CX1Ea}0= z-2=ci4Ybo9gW4Wi*wESv?s^YEt^z7X_=%ji8>VbRx!}MeHwj@o=rFEJp;d-)q%oA@ znm~E6+#rA`oZ!YVzmlsA#(msH;bQ3~l(QoxGI|0SCE;L(uNfFy8dh+RMN7M|tveE{ zu8#2JsH`%=v!janRkI`02m9Ce_YC##87bY+JFvOFchlf-|JKqCvt|J?yms@3Re-D4 zZ|WH?#lcfOc1HS$K+V+yTjrDw4V3m(&IP7tuy<`ePNKHVFWpeK0cTlz^$iW|wR#{@ zx+YTEUKJ_DY_h%=0+g=afZ15jn*LI?vs7OJlp3Z=88L9Tdh^EK;dPrfmJZ<%2yh5E zuCUyDX+}J*JEe?0MtwQARMTHM2y-+~w6%9*Hle2CBU-F?^%|=iUMCmm)-tqn#!Skc zm9rB@n_HUqRa50%^k1_-0>*Abq$gq=c3gBi9AWN@DH#H4@PHax#A6fNs%!*?hAUy{)D##H|1)%ktHm-?aLX3#SW0;NUg)j$ZchGOe03K~$ z?pn)GinUOe+WA!gr zKZsR&&!eRh5gYN9(aVreHyL*sQo7xw9CPJd%&n+*8qEw+?^ZIvuvb@N@0FXgZgp-o z$ju@(PeL>#gB5b4D|2+>Y;v}mO{(2wxxR4eu+8P-d>4%`cYIt&84-5WoD$8ZLNnH> z8q;bGZCX8i2u`azhc^vyw-0SzVZk(5@?%ZmGM0v64_k;RDjS;;=(QMCF{YAJ4a^$` zq|xRm4^%T)EJDw2b7{PlJ6&n9GfXPGd-A`ndDHP& zx}!TkreC^^qS}y4WX?M{KFC?6TkbX*mN6ahN;8?rP<p z7~JrbvoOqRUH-=7<&saE9tx^WSheAz4J>z%Tqd-S+;fVzB8;VZa!>-#q5d@+u(ypziZQ@)P}4(_g?OL#*&magQ8nXcuwOS~br)5ItSX%ox2VG4t`SWW4} z8Plq2s@vVxuoMA^+r83JFtjhnfv`T8F8^5D{St6-zt^A4YlB}qZ+qg-bA?zv`nEfMtn1x{K;~>GsH2YIY>so0_rr4KHlN)-m?Z)aoCMl#iqxTy7XLByk4N zjQyg0(PC<&bygL)Kz6nUK1*4MO3F*Ai`=N}>tD5b zO=|6?O$R|4?#rha)UFpbMCEa+v^6LAFgw)Yp#`qoPMi+^$wU{%;=%rb{vL!SSWCw0 zbWJzl$XP+=FtF2lls>6ecXGDS+1&}1;+dmt&mbm7T#jSUYMs^q+t1K5r4A{LcvuqS z@U%JBEGLc~4HyP7#L*$eMm7%( zs=atjLN>4OPhsP06|(oZUZdjD!{ix*JBQ-j6}!h+IjAm~wg-H+lM^x5ZOxVqx6);o z>&+N}N9>KUU6j{!FerDf=#)Op>34b?kJFTR(|1^#=d>~}0FKhd zoyzXUw$`Xr3;+EJyO`!;Bx#6tBATdXL$}kz7y}0XQ`Xd!o54&t=v>x}P-U3m7*Q^O zht^^ZDX026M*(phLmZdCE!fcE2#O>FZVaorgq7rJlNpnxAIQdY`5~(U2@(vn%HZj) zZDa+(?iRJjBG(0U0D0^tsX^t84$g3lrj_eCgq1i?F6E#C`ydojSK9#G3k(5g~Qtbp+wz&?3X!BI8HJ+X_%3vUUOy{U%?j0f> zqB(|P7LzTtX@vztXZlF16Gsa;P11)yrg_xDK`zGhSvyld)HX{-lIZ`b49z$LvQ*KH zznrhS21&1}xZ9t3aBCcq4W&|5+^)ynU$`vWNE%3PeP;Nuv2u3@0|U>Cc>19RHoaWP zIG%RncdRj{j_HkutNnwN+P&3N0k{xOv2pOm$&6giVc6T{_G1$drObjaJ+h?t1LBGQ zvLis1SAe{$FixtVUc7^+wMIC0KeKOUmdpAuKu&I4d#5u_kgw!soU~N7B^I`0Dy%(y zGqx^W+8J3#rbqJ7MP>vrn54TNotNUOlaeJg3XYLdtJn9e(Hr}2Vv^M<4-R)B7y5I? z(9dCX#1X#Px6{o*eYpN#8jpi}dcc#%271enJ->>f-&HAN<~Cv-Cwm_k)?{l%TlGe* z%mpD84!pbU|C#69nY~i#$LtabKZ;>$jC>iwC96@a(k31Zf<2jB4 z(bZ$vF8GfjU9Le$d$t_IyRlf$m^zMFvrj5XCsqxf@KC>Aj}PN@*~; zSCB4GA6`|aPp>NHq$|u#U(S;RX31Gb8e6^7vZ9S?b?M-VL9f$23Wkqxx*(@TiOdt^ z%t@iK7yT&NopIiYHKf*)?JO6o8FT7%qKj&f7^8`yrJa@|m)k4k>PsdY>DVH7YZ@@` zX<=3r=L{;E%b8DRMeI85OxZ+Ajz5?ga65%ABu^;JtcCMYb-2V89M89_(#=y<>6)|( zqoJvgZXf(}uZvB$Pu1MC`Q;e}(+5>15)ailKVn=m>q>b@kN70rTMq4+2T_Cl+-b%( zx~rX03wsfml*X~>;;dn(G*5Xpoz68NZTCQg%;ijNh&x}&CiJD|IFq2{c0A^N49&=} zv5>t!u)ZG&KXNeQ1Wyi5a!sXLf{m_|64|oYw~!MzlYx@a+Gb&*rfZlV>jbQHw9V{` zGR05z_g%!f?zY8k?aSKKl#g?3tvn8*8W!v9IIM2rSvaoek!qSrMx-2ZD#u8<^NNO( zR2;Bx)V_j$Z&|;pr}vg^!t70V{6WdzlA)Bj; zmeaJgY)+%5E@ReLBO;}ljwO~iGZn$qk|7ndpNdp`2{ta9)cKa1I@pA{U3yo%+0A&X zV#XViN&3?RrlbTvmy0B+G6Ke~f^^1lVmdX!B8T)yF*}b&*BHHCOn012gQ-0m zE@EBn(`a=Tl~4^0Dbf*v|dgb?lGKz+p1SQ(W{j*Y8$s4%nK?mW%1! z_BzJSYDuawH|BNKyp_S+KHe~~nGf?HyRj@L*OaGp8&<8=r;EVkV+4-C`j3Ik4Xo*( z{7H(O`<+_DY7>5{war+@5gCP(0iR6r`JMFveI(D|cvj;dm^wHOZ*f<{3|h80hZd2(^M8Ooh&!kF5EIBDs2~cMoHTQaNS<%#5y#o+UA9y@zld- z;m9m*nh`I1*~61zTV1f76OErYH^umr>zirGX}mTwcswh*ZJA~?o(~09VEX&|4!r}r zm<|)&lGpbb18BvB3V#;4xz;d-@HWRUsbq?r%4IH&IVZ|IJZxQntEddL5=jsp7p|lo@Jy& zGml06F%q;e%>hs5Ny@dA&irQ9dD2IJ3Kj1=?5%Aw&&)~NjvJ*U$XiNIim|6PJ2A$3 zUo)|K@&t^BBrvwB>r}go8Dpd4c?KR-B~$aCpPEO_W+pJJnrWPOhePOP#df5=GB~T*-ws5ISsOkq4%1Ge72c2 z-Jg%HNrfm3e_EC^V*(m}Qf*>7PR#z`r9Yt|<^H_wN$j{rPSp0hR)6MwvbH3z6x&)I zPc3+qD2*Km(0Y^q+Y*~%KZQA zN7QxmGBjmp4W3`}bq8}BZthJ|nxZbfI!wz>n&y|ebtm}@()2(Y9%`#0_VOfYE{%|} z$*fG)6jN-;sF-Y-oL9`!w*#Qo5^KVYDUB0!LvLz6l0YYF+{LL&mAvf&1`o3AfUs|~ z)mMjC4|xAegi?2|S~oKOe6uHQQIm z&BPx2O8CJ4KFxJmGxP<+123&^PlUc*iSEP)KO1$?wD~{O)qsHR{^Na z4V?rHvtD>2x1D~j3{ah0aFTm+`YFLv5#!jb7oL9VNyMrNr`lPLc;lsitn8$p_QSZ< zT(V*gU!ZpaW!Q8_4xUtsCuozMj82)8ykJ%+l3oz#94HJH1-bv5-ZM_hu&{e_n;SvA{oJXYq-_NSf4|#dziXDps7)S& z*QHZFLA(UrUSFn(e^N4zzaowe2CcQWzY>QsAeK__bVw<*DLS1F$$_HqS` zwom&|5Wo4{UedWODz<`Hm!kdt_Ulvxox%?Lu}W9UCy3V2{`fXe7%k}R*p8?~Nt9 zX{X=+M9>~86=wev!Eylgp#9LNgKPj~_|OjFwz}@`zYP1S|6F_{XdgFri2qQB@arAI zA9V=-fH3v3UyGpq@K=89hxT+qn4)HUBWOSUJM7=DLwJJXv%ia={p_!Bxe4dtr!{4r=t`bXWHaLQHQcd;=B*0;k-PKtibxHBpUw+?ytf*ox~zdt>k_V zR%rvr_^Ze9xYH2kac7b^jy-2qjr5`0G5Qkz8c%8Hrl88{jzrCI*l&)*e)bD#=!7mH z5$`y~W6wx^gD6LQ>L>Y0Yv3YH;8g#bie%fMoc%e&Y_B9&FiIP&cyPWG!ywNjWEZmB zF+FYC5Pz{N%5jL<&;F2Mm|{3qoF*P9&JkCL>%^nQGsJVno5ZKYcg3&8o#HPdJ2l#o zA#$N>h9hE;*j?-+?j@FsBgB|kBaRa%i_IeYL#8uZTqrITTSfMZjCYK9lDI)USG-W% zBwi)nApTXnQ@mf?Dn2D{6JHkJ6yFm+5v8^ulH)#8of?c%-SBjQuy-^5qN zcf=3G&%_<#PvUPP*Py38*0d5hC*C67DLx=_L2|}_R(w%>LwryCm-walz4(h5K!-#<{7qRhPuxQ+ z7W;^Mi$ldx;uvwPI9Z$~9w^Qe4-r?1>&0WmQ^d2x3&hLBtHi&Ew~66=#Yq;$m@? zc!YSOc&4~f+$>%%-X`8BJ|;ddzAFAh{8;=(+$C}aTKdD^QYWKgH?gl+D()+e5$nZ9 z@c?nY$lqF_-gV-!B3Epu{5IUxYVjm-qj;TokNAqXUEC!W;MSe#^c1;jGsEM>1H`4`(c;GDPqvAir&&9NC zUvGDDZ!s=5h>OK_;yL2u;&$;X(Z!<#+KZLp4Y72&;cW3}af5i3c$@gFxLe#4Yvohl z-eOE#A)X;#EZ!zQD!wd!DDp>ms4p9jFvvdQKH>~^A++Z-hLUEWlMw}@w5swhh z5U&^S6t{{05Wg0G7xVGxi|O?ghl-QM1H{$hN#aKFI`JOy8SyRgbMaR(8xOjeUa?pz zju&T$E5zf(^TeyfE#ed6YvRY^Phto+fK0ECI7F-$_ZJTpj}p%kH;cE5Tg8{e55(WZ zFm4Q)UT<-@m=LFni^TQf>Efm0P2z*%o8rI3-C`~tEi%0xV!2o?a%pJppC_&nPZlo} z?+_mm-w;0)e-=A;_4V}J@Ffng9Nmh`3Eb&tD z4)Im-U*eBqCLZ-te{Zo|94F2a*NP{Imx?!uPm8aLyT#lR*)Nuh)ncPKPh2COEM6$y zAwDAhTg30o82h`6W#SldsyJ6%EuJJ^A>JZBDgIOZTFmI>r&A~n6UT@%#U%>#VtHs;IXT-O}&&6NG!hT9ejER%PgT*7nQ^m{0 z+r&r3m&Fgoonn4}Kb>N6AF)oHAubjV7dMF4iCe_y#dpPBqB}t8h^69wBA35sdp%LS zK)hCbRD41FSo}#04fK!iBJL$tiW9|y#O30#;$`9u;``$FVqh;{|6s92yhwaj4D9X4 z>nsiw>%|%30&%r?s<=`7i+GRty!gKOy_h%1Pp_}oARZ|`BYq_QAZ85qkK<2PGT%pu z)5N*r5#oj7)#3xwFp zy0}POFJ2&CDc&bOCw?q`FNR|(CvmtqQ9MXITs%eGEZ#3ZExs@QDu$|j{Uu^dtQT9w z6UEELo5d%@*Tiqd-^Bi-ef=ZFdU1d8Q1K}7EOE1VtGHEsN&HIuMU3p{r!!nkh||SI z;(GA{@k;SN@j3Bh@p~~m#@F9X94RKmgT&?H2Js?stN4=mf%v_cUhV7eEcO%k6~~FQ z#I@oH;*H`1;x_S9@dvTE#!qLI$e)De`Q>2o2=P>rKfuNPw~3F6FN+_FJ4H9{$KOL7 zD()xF5EqMwiyOqt#GA!u#Mi{H#NWg{YyI^4i~EUqJ=xg3R6JZfPrORpB0eE*7rzqS zg!~cvizCH)ae>$>UM9XJek}eb=GFOnOT?I1FU}EL#S_H~#B0U7#h1nR#h=8`SU;UE z;$C8qXfPJB#! zQw)w*`r?t|h2mx6)#6>^1LC9N)8Y%_+v1nvcj7MbcQHJ{Prq2~Ee;gR#1UeR*evcZ z&JmZ1$BHM5XNZ3iH;cE4cZ&~+&x)^$ABsD~-C}s6@=q)mv6j4PKeNS^;&I}o;&tK{ z@hR~Yal81Hm^sPU8x>2$!6Mc-H|g?M*x2vP7Y`9viAReY#EZr2#5={u#23Z)#4p8P z#OEjb>HS0eLi}0GoZ|2ACYFk0#5xfx-5R@F#0BD^;wtel@o4cx@pSPVaie&dc%^u~ zc#F72yieRJZWG@VKN3F|cZffV{}wq1i1{B9bHxI2Pq9SoCk_&aiX+9*Vy!qqoFN_} zt`rXwH;Cto7m3%1_lOUP&xvn}AB#Ih&Sj!soy6|qAhALmCr%gVi>=~u;@RRR@ka4p z@hR~g@n^AXqi;ulahQl#`Hg)u#ChUM@n~^_c#(LGc)R$p_`LY0_^tSx7;f^@D-!#P zL&g0>EL&jg+9=*2-X%UJ{#|@m{7n2w3^x0EI*VP!o??G-usBQ{CGIC;xdvm;1aYc3 zLp(^FCoU0Jh-<|o#S=vS;w$UN1L7OvhvGNluVUdeKmI830P!gCbaJ5MTtuR6T}z@* z*+Qc4`H)0as6LANLbbcVqF&}WIpH7w-6$`~~B;xf|c%V2` z93fVb&^wldT}@;j{8M;234dC}6U9@-Gf5nGvBI0gD+r|E_3Y&Sm2oF@)%-2PDw8CbdF2YR;FA~lC zT*%G*TyUM_W?nABXDEE7c&&Jcc(?eZ_^kLTiGJxz@q5wCw}m_q^!J8M1Nc-P7OWiGFyCc)w`ozd~;2zk<(7Zsxxt{D#8si64kxiaW%g#9u`-4;IIV(C0GU zf#P6sxHwX*5$nWBqM7%K!1XAU-KR zE50b2`LKxpj>7MYpNU_IJ4G`;7V*icR7SagMk^ zTq>><%{*D?KU3lJ#f!u%#cRa}#jT>5FN@=!SNLV|b#c4+k@y3NJos76$FV%W7KmNN z9^yc8usB>CDK?1B;sIidxI|ngo+O?oo-1A;UM5~HUN7DxJ}f>az9_yb!YwBaC)0cq ze!?|VekCNzdjN@cY0k4~?;{yTzdDA*`5KSiOnv~SzeKY!H0N`~H|KNE=*4l}xF0ML z`-nzA(jU$+Xwrd=7)CJmj3Hr9t!UDPT@x7w8%U&s+a|-AB+@xhoK3>s`Ql;{MlBW1 zdjm)}4-T;Yn*Imr&4G;iZz7?8Eb9UE?#=vzz8jQ}1=KT4ej={%3*iBjBaX2fVPiM+ znsgCf$^FoOnvOq{L^{_fd;^K}wkiA~iFChIcn8VMEnR*1GAu?0u4(nT*lw96S4z#h zbER|fOJAiFl=4lvj!OfV;@2)x_9kCC`~$iF^4%ZoFz@=cm$$v&_XqMnQq=Z7U;6`6 z-|V9+rT_Udp2SJ-+J2!eWlzegBB|1LFYNg{QdV^GGmtsNEhKHyu&)KC3e9_d|M?R{ zrL8Mcjx;uymp+Y;{sPTreWg-=d(PastqayUDSPpIQ>no@SiWKre~R4LWL_BkPsvjL z$h|b8LO7-TS#d6OpK{c~);Y@%sk(7e>6|rdT9?dSy9R3i$DgiJ!! zI+;&T{AWB|N|;Z_c-+TNe|$su{=dZ=gg713Me|L5?DqH$@z}Spzpx)0uMPqa-!a;8 z)E2*=VmfHj4&%|Tx%j50%eH$izV>7F9SlLLzD>}_w5bnWLQ>z6*iO~QcLe)DWaasrvX1A^S!9vHH$|AXVSHDgK7B&+5Ag+o}5aj^M>snc^{c zJ-(^>{tbNtAftWg;*$EFz;>#>0jMD5klBy5Zz}|;`ug1IpQoq~U1U<U(5BstDJS6%*iP!rN;yq)PfmYwBKZy57 z>GEFif0FJ}#KT`ZKaTr@bQdF1YQDsfFDwt{a}mBaUykpfZzu8vr?TY7`f-ioVYmN5 zM&{dX(8k-Ucy<@>ogT*X0Q(srD^}eKd~tv7D`ayf?MS@W2<)05{si5VrgH z?y22oym|BRJc|udAG_~uY_v;vyW^}!Jf_xr+`$9rdc3{_kQee1cQkKM<2V^i%L^r_=)MI7qujjz=g>7cLsQal&_1AlW7 zFIC@{&^Jc<`ljgPySB8!w%NcM$GLF?1p06vzr2@Ejd#Ep#er&uEif84!5O0?a zfVK#SB3`O}gFbVds)kBwJ0WW>;tl+TcT%SVhXA3Abqc?lLK zDj$;af5eF4B_;ce96oAvAXUy*~KG3)bap`xS6gXQx}XU|l=;*i zK*$|RVJP$2K1e*><1W(*c+$! z&|>`050xNhr_jv+KerfHvJdbRlx9N9cL%EeV~06nlpDLMpvNEzs6G)VUWfyFz>+ zt#2qX47ZA*xkDUhL1;I&p9$@Twr4|pE&jO>AFezfdIh#^3pw!jZ=oPkf5DrC0vZ(X z_JLW01Kxos-O_;fLl?YdAMj3uW#s|ydmMUhz~k#D=LNieFy;J!cOh)NAmH)db7R2U zj?jex?}BWMY6Lt!;J7&8J%cK6Nx&P2eU}Ejk6_Ye0q=Gsv@_uC0DcH~H{U@-uM3nl zqE1rb)cw=FYa)(wK)QD-s?LGw-eRP8Te`<5a0RZ%iNl>;?*d@G>wOK64tKrVFrIF7UDw-$`{aMP-lf?0p6h*!iuS(i4F|Tn-hD{#pRP9;S@41D{RUfJ%=FI2zLzq+ zJ8}5Sncjg&_LWSp3Ff|<>3szMUd!}eK}&l*)60SIjZE)eWF zdY>WYnnLd@q`tP$I|0SGuFz{j3Wp(t8oR#G`yI{T@Ivoe)Yc;ky=8kk&XI-QgHU}` zq1PWi99`&*OUDu+h2AFQ(y@hJF%mki(EA0-jxY4yf=OdGdFzpE^(HR|ZKP(C_a(H{ zZt}8F>k^y1?_prwCNCE`IChiwG76yKac>;=baau0V}h#f|5);W#($gJd-~ z9zX%E;l^($k+s}-3)#4i8)u+O9XApivAy91H;zK4oWPCWu(Yb$fyWI}0X@N|fcHp7=f)$_^=cl<(x$gIf+$rI> z&$va5+9`nrJKY!E@YRqz(D#Px<-w=C14?lCTRI$dh=;%8y7afxWXF9?hfn6=Z@Xct zb#l|)CtR-{Q6jX-iBMCT6Yh@A!F|^a@?e*{k!F@zp~2ek%w&c~vD4JYWS`PF`=cSNB0H@X#{Q z*SHT`0rK|~oO|4@R)7YEg1vo|%T*|%C(+?8qfE_+4(^Y@W23?gVH?eSc9b^|k@9At zBXOUXf^@WND0p&|%jGJfm!XexpOyl?;Of3GDooW>@Y*QvuT*d&x)S$|QC;tbI4v#L z$y>l=-;^MbgSv~Jz&&n4tDVX-tHR~-9nop%(cSC{zd}4qTOt)M@0$y zljsYqvn3TJyf|kn{VO^hf=C51{Bs9Z^uB`ff-3Z=?p_tW87n|ty(@A~rLFGE>@A#2hpP6;ne4jmT}ZhVRK`&Yjhj-D!_`WnpEBL4GHzoh1RC3nn^n>28bm7KdMWM!*0|-U zhVFqW#!aipd6c?(vg*u`anw%ZCRKQEVlzThoCwt!bmc+38N+-%uOfV=B6t z-XxIbBf^R2*U%>`EAn|X4D%jIFB z9<%0DnRzf9?8b^P9iW+;D!dr|HHjh zX>MRXT~iUJHB9rS3U3o4`B`&|6eP3eR;$rw&FvB-v*r#P!)DDEE3jE}mlfEox!VeS zGq103AElW?VUhb6nK_H+pL;68bbw|)T;b)TS@~JBwPV&i-Z5*Quu0ggdD05}H1Dr) zxhhUHlgT`&G(SLE?o$>5-A_@+8&=@k{cMHH)pw!~vQa%RyZ2{H zdb1)-k7)P%72a_;h2;%opZ`y*0GA<)cpm%E3UFduM7uw-0(1l)QSdJ-z=^Fp&#s?X z0UY^&m#3dv0UWtK2*Kx80J|6TgWwA*@a=x5!sRMIQI|RQ57}M8BfqQ&(<9owv%=dS z+VlR&{_01o0CpdR_Tm0y1-Q<5oad%pR)AA>7SsIM3ed1G;W_*lD}bv9Q^&7X09U&V zhTz{;09O~Xh;~~6&f%SLljr_s1t@neOz8e@1+W2UfE^Vs*B6SuN~6D%XQP?Xfyyv_ zre~o_Z#XV|@(y8x&#G*@FyzutZrBRo*&VDF*;WA0rm%2xtN@<9h6fjJt`)$uQnu(k zD}ZN5vG>cj0(kZ$uQoeb0X!=n3PHpQ;Mp-e8AYwY_bk2Aodu(#Kd`Q4RQi_=UofLP zSBB{`J?mEK<)VAZ>(0#UZWW-+xageQ!wTTpT|CE>SOGlavMz2l z6YFgS@az%hYac6sXJ4_1`dR@zTSp!JtN@<9$8zs)1-@rRl`hv*ik6gP-=6YpM1KSZ zR)*;_Ju9#DPM~K$vS5c*>a+x_ZeyCmtwvaN37f<|RsgH6WG&y<3ec`mPX<-GT$d?2 zht0fHX?|9Mz^KYFtznvDD!qXy%{* zFIia+v;uUlQD*N!HWfIsiK!fH1?ZDb;iW{26`*tdnYljO3eZWt#MVE@3Vh!iDqVK< z(J$bp+bG{#*!j<`3^P~g`;toUcl!PqtHq&K0gC8D_BhL|0QH1V4BX{bfD+lw{9a)N z$P7-%bXQpcd{1ZFZnXmVK86)xjTOMvKeInxYXxw%7t7`_D}ZN*(6IGZ;Cr^9(≥ z(Z8}9Es|$@u~#^}GEAT8+3}U$TZojG$E-QgDu8E`*>X>^0#v>|hC^_&6`77QiJ|0MB+X z%}cESp8dpb;xa3MXV0=kHdz5YD`6G?vlYNIUV6HltpJ`aWe#6%1@P?8tm0Q#f$!OQ zl`a?jiZ<GemXyr-BoJEZ`f2o-!?>2i^^C|6)|cSylyY}`LohRtucK*7H&y~R|p zFZ;LO+AG*q>2fu;D3>5|f02R$r0o7)8K!DlkP-9#LIo4qxrJi>)sQSmi@993EqXC) zeR|Bl=-@(ct``eaH5KH?ylhm9J!Yb}3c9kPg6bmzPCeb729gIkM7f@qQDPT#~pboozB!G5m>>6{qR$TNZ*5P7l zjPfkfHx_1E)Ho>S^~V`_j|TkEv|B0#d}x+M8_TSXsD4enpc@j?6$jd#$Npld6~KtQ z*qDdeL*VDZ6b!clw7ZYkXOFM~oH&YE4Mti4n#~ui^`op(-;n_^cOq3;Pt&O%ko2>wTa%ow2x)tCAxjzLntN`7E%fx0$fc}c*Gd|{Wt-RUzy4GtIEMv)L@dm-sPXuicUFn5LnlfB>yW83 zC)>ibRpt~cuvO+%o2IQYr&$5~oJp%rw*uttB(xWIgB2ieZ{ex#%$VO7!|uGk^z3XK z1J_v*w)=B!3|q_2vjP@J#63FZ-T^P7o%5@71bDi%?_p^yWAQ%~3o|Whd?DtoqQ=cI(S1n@ zFry;xO*9zyWeIRD%Nxauk5?o}4UdZ0~+C!ha_d7QJ6x0#n_@5j1r!?Eds9!}nM6l}MG?oM7d&nN%1f@0i1 zra|z56`+FQS@T;lm+Lh~??q*D--(%L&CwlfbRWgSOqsra8S^GE&2LzpziFR&pT=A+ z>==ET*ZZF<^E$I3d>ac>H5KfNd1q3=-&m`EwF;Ouc+3%VZ>NGim^D92!MDuA-LWuL zQ-NFM)uMUiZKOQ2s_luv(KIP!1*q9Oc;@n~05!X0I0RW%fSNszl`3onsM+0F?%7s= zntd=+$*oeuMnx`QR_0lOUy%b_qjciTbB*5DRdEX$f-C`R9W}17&9!fJE6%7LlIQJ?>I?iD?;HuZ{YY*{rvvZZp z^(&)Xe9bMCRm)(E+rKJIdudf^mB;BtdB@O*At@S*>E}?ZF=)zXuPT=-UPcEE!oES$ zm`|sNSB04tHC9%6$57)Pyi}~R3gG82tV*M+{F67|qCko7TjgF&jZZRDMoHscbY@Id zm}ybt*edTkYCMwidTS%{PupiQFX7xxY z&F&~Ax3MZrYdETKK$SNQk@9Y1g*dpX>q`))^Fr!%UcAh<0@RQiHu`y1z-}bnonGZ~ ziO%S5e@tILxE^GVBDmCA(=qs7TDl6C%PoSB^YAYzh zWjL)`Ytw{Pvng0-1+eNXHm~(o;9Iq%%H_hJ(I1eiduWy4z-Q2^BdWr*mzjNhm3KTM zxs#B~0Mx4(AKFtbX#M({}oMCexjb|O3=$TfKVT$AE zDwoTNM&IW35;=F=h^UQds3d^;n;LF!P!RvI0u zh~AAzSrLx+W*78f_7?cE+=4tlIO|*yeF-u0Bb%|WAi@F7q6kM0yG1w_SQ6pbTd#s< z#y!!G+b6;Y6ayk0dfF?(!Jt7Aj`9)u~A1)p)>MX_F&VBa+nUWwjTu#>WzeeHJ?{LauVvFM?Q zac6{=cuy3(hH`fA^J6?!(3vgv{+KDXXCl0Y+g7lF_2n5q#tRW%g}qp?k+L^pQNCpP zQG{1SI|{C#?BiJU9LRPS@ruO>6!E$vEzspA?)yC!9e~u*14X=;7!&AnH>J@klSegy zBA%*i14TSH)&+`qLK_z-;#p{Xpv$9-+FTVK3k4GcMLbW;4ivF3pC2e<=eamg#NO(V zK$mTdx~VF919D|)pol$=lU~I3inDh1bmSTH%UtKBV~7{qW*W`aR(Oq*aXz+P3c{zb zF}_?CWXo}Hfdn1n+#0VOy@NloW`0fE)sUG-v(O6AE~`+4?jkEdyX?)DyVwdmXOD4B zn0&Ov3V4~p`f!L9WSY+P;2M{!1^e@8X4m-LwV6k=v?lxrjG|SmYrIvo%FLr#D+Rg{ zUQy$6Sz&)3%_=D{^Jv!BgsGYej;-;2qyjUK=J*=_@+&!y<^&0n^Jq@80=Q-7(VSuh zxW6;=Xil>_pdY7*BWql)QS8s7Il3lg9?h9GVVXxH&ad(IMI?V7%|@%yzx6n$#^qwh z{yduVq`=Ihxu_;g)l{$<^PWzE@wi_v+&skE=xclVd)WSI;0n-EV60sES_g ztjW2Gk&Z8c{6~3ZX7K#f=GAXCot{M`e+G{emse&6Paxjr)h{(UA5)i^!SioZ2MrG6W9Mi_ScnadYB1r4agF<;B~Tl^6H8cC|mNCLH(6>TXEf zPVqddqE~ywbJjDGnfg-{_seQyCq(KJPnK0lywl}~Xv%1?bfOlz3t z)VQ~1n9YeMDPT^RxlYrpM(g+t36k?#X4)9IzcN#PW?6xq*K&Xr*sM9w3Vbss#a*r- z?oaudA~VgDpM&CIIzTh$$GuN!rpcOx9kXUh$E-QjCSkK?sTKHX&W^jh5%#D2%vG9Z z%FnWRnAR}OHF578MDi=iIw?qI&3dcRX3Y^2B(vs78^dPJQC48H<`^rmS#zuv_-3w* zyIl0#pYqcxGtHErH`d%=Bd)|}okYtHPLHD}u-Y}TA(1%8?*#@zu>=TG@L zS!tRnKj+57w1#P36!#urnr6z+rB(q>J7&tyWmbUGj+yea$qI1VF;jm2Yz4SYH&cE# zTLJRQO!>Lo3hb1hE35!^n<+n6T7hr(`Ei#EwEI(jHp*@@<>#t+m>$vYzr?+bBVf0g z@^h0_fIAs8<>wYFz&Y4V`T46A;2dnG{M>2h;fexXU%<{kb=fNP(Gq^JF|s)l{%8?iKC}1$*Hb_l5Qfo{76$Y~G*Z z@|+a#64!k(9;Rw4cq8u3q=H#{K>k*H1+T+J^|OZ8j%FrFj@1aO z%+tYK8v|KmW|HJd5WuCPnMsmw1*o@XCP^nNfZb*$NyG}!X3b2Js7(cqn3*I6R)C6Z zW|DNa0y~pr4=X^;HZw^It-$v^qt?9uZuv7wLbd)`(aa<%stq$&=zEV^uf77lo0%j% ztpXI0nMu;y3Q$kXOp-oUfO=wPlJvC#WQLhZ(%%Z;yO~KczzX2InMtyj6~I+9lVooz zfU9OE$zUshXJ#fzsTKI1b*;s;V0dO`k`&7`Gn1sOHcX%C*}k>j272}c?$q5;QlK_F ztk%7i3e1F!eWbul*r==xQ#BRT)OycTfmZ?rwe1y*uEm@?C@}LP#z?`dIL@uB4O2B0 zOse&=E1}>jK9QQzUO|1W%U>?=ryop^0yF(!YHgURsbD55CKZ_J2m9Chmn_NY2M5|r zK`xo;2M1XJjz-;YM)@-dGyPz?k}%T`4z3L|aVD{#)_asmnCS(zvSDON&9HnQgE}3N+hbS*_b2`~2AkE2O~8Hdt31rfQmW zOs&^U1!lIvaZ-?+ZE%7W_)Z>C>+%;E{MiOaNu!x|{3e0SSOKZba zO$ArhdWBU`U}hU!-Cn_;YhC{MgFoBgaw#yg4X&*XQ#BRbTvn?+Wx zdum<&;)Flj;67{JHlntTg`Mu-tpL4^8B2cA z_LAsr%=CkotN^`@nSSuHJp_)M=?AY^0lFVE{opk#KyPD)j$gMr(A$`y<2P&!bgX8A z!kborhGixwyk!sZeSfOf{R(dR6BM42?`DF++c>Gn_m9wa_d{-)`2`kQ$hHi;4)1t=S39q5rR?NOqketFWAfYixTkZC;0$c3{ z+ca&pE4KoamYKpZ%nDFiW(vbTR)Cx^^>CzBYU^Qzje&Y-rZB{83|kNPvjTX5DGWUl zE`N>0pTf{Hkurs$IuYg`C!1MuGPX2@0j^I>c#lKikEl;klF1SE1__cQ>Qg1qi2AsM z%O5uJN7TnBQbyF95@GIfvYFg2d^MtuBo9b<1vN<03}hc{y$qRtWJbarg?;`&_AC{b z8OWZU2vZGW*{8^=WiZCQFcGG`wCc|Z?+03C2C}b6(P##; zue2J2rhG0*xcsRYe<1rZX*2`bS0}^qgF8OVM#5vDav^Vx(qCV@16!GlZpc`0D8!nKLrZB_sye%uR!7i<#f zM1pt@?*3f@7S8Zq5WFZs&@Y@P6E1)4Cc2sThEL0gt9TpyN+L}2XvEtI?@mP8qiO0i zO!l-Ik!BXp8Sk~Fxkp1SCN91&L0SgSOih@&(mu`C6E1&ACt5=T-&C3p@!9H!i7>6< z!@(~TUSS;^HzWApB)Yx?aoY&~w^o3rVMg$GS^>L&boY~l%OBzKNAN#Oq>SMIln66% zCh=RsyM;-Z5&S@1hY|cVE3hN@=~iGz@H6V#tTH3`nN|R+%m}_`1-@0kBwYTqk3WL{ z??lQ7ez-17dzsmhIxjvJR+$m}f;ycxP;bo$erGE{6)+?Cg;s!G!;Ii}u>u&ewi7b7 zTb=G_(QB9y{9-G}F!eCE&gBmV`6KxGb^iI%jNtdE3)5a&)vwOmNUO{U{s5~0R+$m} zfmV=fH1?`<`4dC_2!0=FG$Z(X*M*suQ@AwX9$4cI8IK3Q8~}479B@jDaMUP0!eN_? z2*+MDJbXuuhKD(fq2b|&eVK-bAF0vsFrWSxMEJD4D8i@9-6DK$ToU1PS`80Rh?}^5 zB7BZIAi~F#dqw!*a8QKLseyNrzR*-1r&4?toO zK9U$6;T`{&2=9G0JUpb<99J9RU1ME@w|?Uyynh=X;Z4}Y2=9|7M|f|e;o4==#~HHdqE|Hv>|B57 zxGvG_0EDiI@YMgJKV&>D5uM{<7`KS$W(?W#42vOKGjzN>5gm+u7_#MQ6GOIU2>FDB z9kS&~2}8C#3t-5WT{nho+23Nw){HDao-oCRAzSu{4S^!|NsWOnW}x|BiRj6&v^h}3 zUIXK~Y}pvkWmCdVV09ohi#XF@F+xg2iFBzo88%v z?3wPi0$5Y(FjV!fclSg^9h;k(7>JcZ0(|_DF+O(-B7{o%ArLC>f?NpgyC;qay;#V_ zG=f}fJ!4+*G(^h0GMGGUaqdSvj8h_<&?%U*5(piMr;}KwqXNfeEDJuu18(n{JYZ#R z*9nL^zc&xK8Vx28dJ+A5T4(_hKsu{k9CmbY2M=2cV`Sb5xph43%mN;^2=}X45u`sF zRmSPT{@9UuYg^Q_at~wF%~0foroqFs&~bYi-KSCaMZrcMFb;`I_oca4@qoYP@qjn_ z8{HRRcgD5B6S1RP3`gf@+>plyA^Sr;=lj|ZZd)N;v;Y;ka4pKgo+2E zS!Uc~0@=umFhYL~{uK(kr)NCqt(%B7rY03Z_*gGyM<6Xdt;Yr35Pq@`{R{+xX(dZq zS2-EacB5^9Kw4UlLFw4Ptv8*+$V^&~Q)$Ud_V{3ryZRvfYB9?L(Stqu?v3yp#Vl6D z4`LPejQib-k#eu`=w3744F4ONdfkH3%6L0s{OQ&WJMuH`&EJk#5gO?f7iD4pKe~R5 zKzcFe7daX4bzK9Mq2eXk2z*$`2Af^nw=V*pnn148JN*kpcd4aM@DkR8&w@<2+Y1pK znDJG9$s}lgi1vM3$Ze-Mh=R@dKEgxNar~EH@DkL&jGe(<*v{yOSecIuNtW49xziyD zWt%cvSqvAQU;wo#!h@6al1qJUh-x~aVMFm@#G5ZH1 zH)3D6g8gAn#$112iPM)$p`~F*zYzaL@edvzhdj)nw0HVY*qD)HHfgSjPviXfCVzUT zcZb02p`rdBW>!Bo>wXVFB@~UcacI7Y1L1*INW1+5nRVE+%I>*5x#wDJVGnD12Bp2z z&%poi>>PyW1%h*F>1~ko-;N$4J7ZxW|5t=th^)3mRF9 zhXlGYVh9Q!0>hJ0k{O2vf{!7P5txEvU56a>+hgVnxu-x9IvzS#b~6*hc@S7=27UFY%Bp4;)&v< z5HiR)IW!aMP6_=B4fE8{Qf!|VIt-4T9y%ILaYLvG<$gx!qzo)XANngiI4g83a^~#N zNzi;w==i}nC50Y>{5&UE3O_P`3jPVE^nVuzgfeRb`SW2$K{J$O)&+8}MS@Pj(=a4+ ztRG4%IEZ;R&JU#*^q`J&T9|#shOaE5r?2|b+kUwB5v`mK?neziZ&oMer zg+rMO{7|6a3e@tN6P~}X;`;{CAkQ# z@Ixi2EV{aw$iS6F$%eeP#bU5CAy-zTb`w=xbyay!JMHfKQZ8o+?dbRl{HKIG>FFJU2k(t=x z6dySNfw2+pNH1Q+z&O)Ug^JHa-S+BD=b2r6UIc;hCXiqJ2;A}}L@J@6pm+ju%9|LW ziABYyGR+24p52O@Y2;KB=ss}CO2=!=JqJma6pul%drf9XuVUuA*K7iPif1q|%>?=t z@92-ftQ;OQp!hG`v%d)pEM~rX2bgRfRLpGk4m5%C2!EYzxDz}d#o*Nxor_TK^b7HS zubc3%pZUi;?#F-F#mwoM?j7X5g57&BSqURs_E-mDuT#-ydvgl;t8|EW8ZfA`9BZou zychGkH6i2vu@@q|-i6jV#UEmq_l5}sitBOu_ulNnSZT#SqFs4!bs2;}wv)~3#7#Xj z$*zXpSX(%FE2^vaPVg;QGuZ8mW`2ApS~~bpH1n(z{O#TSuzg_x4=bIImL0evEz7ur zh%mzmY`P!2%FbH-1i_j3B6FDurQ_jMU`!zCNeOlZHeH37`>e#G?bx+9J$W4BNAMjnckMza zP~&$9pF;2vzWe@$ULp|ph1uB7!nd5J^^(uV&tY59?*)4MHp5P&Qve(Nbb1H+F`fQ6 zl6_7Yy9~q~&K#Z#!NK^B%txRUDtE&?WM$e~{GXb(#&JebU1eKhLjsL~p~$5H_!kKK zDWXCk#RbU}!+}0b@l+^2F_~gGFqA3Y48aZfj^aV%jNV4RnNx89mFzUR&N2;b`aASh znw;9%m+D@_QGBO4W*pc#jN0;1sM+`$`=>$MLpZ3t{Zux$&3?zJ+TI81UrUyYpW688 zHnrDG1seseL-6%edo9M)xM=uFd`FK%e-?PdH0p~G-iWWUUETbl>Px|gkCjAw{pW*8#eXmJ6A1B0Ie3MDv`F~3K zYn*Qb=O&Xzzlc1ZGsAj)?l30J6*_w3>nD9~HIqIa;bZX~%`4WxpG?v(Bm4qoCMV7} zvYiO;z;`5iFNZl1hjQh_NcioX4%v)0*?z297eeM#{V))k*ClOZ0A z$5k%AzHRG9(6*TfH{(0TG@kXwjw2C19N+zD$JNwdaRN?Bf!U^RvEvAAVvph1t=UHR zpAi3Se0|-sjqZC8=1&q0=OMRIPxZsFjNhyuvTAzcs*&HU#t91K;qfteS4< z28fRh-%;pGUFq6qj6FGFAo>JY!-B?z2__Q!9S$MnD{hu`q{Kt>IJ?1kU( z6zs`H+WdwOKw!x*$Kf|T0)ZDpxI4x-yfBbeeHc>bH~a(^nCukjn;Q)WbGznFE9?}= zFGNS!#|ei=LxfZ69!@Z~B3v0B6|Rrse5pN9DH?C?m$ z$}emes}o{{{DWv)BnQeEEt+~X@;f!i{hb*R4;E7oZ%d>QrnqgU6dA2>rb|0D5bT+U ze8cT{Tb`kyqsSQJ39^u$6zeFHqfETJJk|alsr%cED3NXEur_f|Wq=Oum3lC$9}S{s zefptx_U#<#-^I`7ey(x2f6_Q*^8lF63^b`=f%VixY3p88K`-`B-GdXnQN&D=A%k&6 zlB_rTb&26>va~d?Ul$`pVl<>vAd)er=%N~Ny1I4cTx4 zmK-fQucinm?NTRIQBn;~I_;B4?xDrQq0H$N*jUqr`u0I`$(o|%M!@EdvVG-;sdtJu z(warJqx^u>RwNBTKJ@R>&VWiKY4TR8V)8mwR@GidhkP2Hnz7QdpYIy|8Y3T46;?C9 zVqKQ!+7iKY!FD1zhw9P(V@}x)SJZRZO{P1zj<}p#JY@x(1_GTXHk*iYeEm4s=e6yXkSok{h`<`o^UcLFq(W%Av|9tS&5=7w{Dd-%t@^WtQ7zAct4z~NC9Wphd z1m6yN0|AGl_|G+5DC9RH;#{;wrW({XmDU4(C9Gm%mc`XK1%EVugM zi|7Qa@E>P6cHrY{o@zBS>eS2IluuPRRpm`(vk4+_8~T>k<2v2)=)iHtr57CfHK{SiK)~nA*$Vk#Ch=2Z{`XA4EG=8TcuwnrvepI57p$JMx@^JFmep(4&R?>kY|V-lOXn?~vt;?| zvPJXewajT^XJR{FPpLY@YSg%ELvPv-8z5mlI1JnD_R!}PUgk>HLWH~{2Xa$ zU2({Qd23deHLaY}dT8C+NqRg|12W3 zEk4Xdcl_ouZz+B$Z}r?ID@*60UvgUJFIYHd?b0m2;gQH zjje^hzPDm|3yK6Xw9CeQ>sT3T#vzF7l-3qhqUEa>E@)L0G~krB`G-OriF-aj7L$e< z5aERDi||{I3tE?_N?I2zYMC<+8AK!5QDWYkYr3o8b|>JvQ8$zka0C0eZbpxcQgj+^ z`+qe13rvLkayQT)af;nQM)0tJ8xDFU2$s9qJi06mziyCn_E0KP@49S@r9*PsWa@DZ`w=(!Xe*9|h z9&TmX;GS;pGPknFU>uE2ltX2Y((!I+qFdP=qOzzvAfv$Ty*ED1m2 zW0ma^{T5FK`UEL*XHo>*VoQr$Rq+N8wfW@lPcO-oaAb@Q~Qmg?Ht#za$-W8=n~o2KD__>@Tv z6BEsemgZ@b>nD#jN5m&qH#N01jH|C5>Lhpw8>4=8XBf>M@vKf%*4c&x+#s5s+*nZHPf0BlbvaG zjgux%n*@c;iKgaBQ)>Bp5|bNiXEil9VGDLoO(Zo=p3>4Zt)?m7SYMN9graGaYn^fR zjkV3=8l9#ob&2X^Ot{-H1qL~-3s$XNuzF3)(gn*Gty%25v~tHl0P<(v zisj2&@Jp#q?GOo_)k_vFUogJ}S0JrPE!Kg$YUFQIqPdyHo$Owht(d<+`Jv*E*T$u> z2_=TIX{?^yM7LR!T1+X`CgP0=Ry342tD1l0xQ52bPSeE1jJon64oY}Nb$xT26^&C{ zYEWG<>#VwFVoFU(G>?PshHIPHC;!`G1PQ;m{$$FNT ziPtnO9#5^{lMrCGPo0*SmT0L%<~b7^V61=KDCTg&VP;OQNv+Eb)s6MdZF%23WlGDW z>dCWI=56iA6mrv)CSw!oj&Bm13r@Fda8Mo!O_`j`hj{hm7E=zB>YGi%jfrYhl&1Qzlbz;S4GAY6Z)mHsQ<~yv z{Zo+HiRPBXWIw;nRcQ;0+nG^6xi&G=F*z~021T4~&+Hp&>#N72o=k3vPn^&)wz?i= zS{czpZNRyefxKptKm84J#*f9XXc%E z-kEvNInv6iS|dZ#w0iVp$H3`YyrE{&(h62j1w-$Kjq{SJnb1chT(W$@!j?JBQap5{Bub5r>^00vu?p!5q~)t= zsIF>CB@#`e<5143>C@5k@k+<~q&KTJHFeVT$zf90`Doo}Dy8mWd(LTYZZp-11`mnp zN(MFTIEl%qMfIG{>fbOMMx|-m%v3{l?X+2)b8nbBDKzd-(5kw0g4$_`DY#aZm|in8 zqjA`RjZhb3)I%F(s?!>)WIc7i1U8tJgla@Bo6DoAu_2Mwb)=#+`-NnWykMq@)MZLZ7SSb@~EnvPb$ zlz>vWWNG8ZQPOr=E9>OR-oiaiUA94coA?#%dGi-wkgdhI9p0bd09!K^oxZxNhE~&> zdUk@eDqv)+o7Rw$rGl~Jcmi4DHIr!d66nYcUTc&2ZnqPR{Ts&C_19z-GG$YYHUm() z{_3k{B)yuN=`%Cxv_7+)H6%8qYExB>8D?GGr!kRgs+s{4KXrOdqH1~#I;3rJqif7Z zZpzeYQ&T^z5$yRk&VU=h67W74LFrDsB&;MeNKogSoKq8ClCiFCs!AkgG*l%t$aoDH zeB(`%8%vs|XPSq}sP0)+sLJUzbt$NCW}&G_9ps%3f5dn5qq>5{9q)kc8+Fccrb100num-+{LEG$?$_Q{?P3 z`{`(iOxLe2g%ZkL?woN=Jv?jq0rk`tIQ)|v8)m1b)=jfbX3gqWrp`lk@>VR(bPpYU z42_9VxUu2UmR`KNAr+o(TJS{R2rvD z=eIh8YQr!NRWi=3t5wsPLszGR)#J#3vCEs+-nKZ*Cd1BP46Ug~7l5VoW+bLq?;)9} zPFqTR~-gSTOjD?9*i^qOIxqBI@eCaNQ=gR##K#Cq&Na*3J?|YI;?} zbn9(3qRZFXsoGe}$c~?Eb9$VZYQP1_C|vtqnX|+>%Xjlynz&rm($)rdIfZJIO&f37 zQN*oG-CGZ3^f)wsa%LQATGFY1l%^%D!CZ(VGt9K{ZrnU|k2#B1qu_P%^%BZ1J$R7F6W&md%PsEScB3qH^A{w)U32 zMl2aK288y7E0)X!&R@K2PWuS#B2;3+-%J8h&Trjg%Mr_4M>LNf2g;nbc?&DCt+2=V z5lcoc!N$b!=H;!!=eHJ*SWrA-T50hJtjt!|J$&x|D2cEC1aVS8z_>we*E0=B$0UGmKJgE|b5@oBTei;ioe z7XB6-WiF=Bu$36Y=IW-Qu?p)6#(vWoGNYO|8B1r=Jw(ioUb~SQCMHB^}nCdN8!Xk%-c;S7mV=Ph40zkN?^Gd8v_YvqC! z6r_X|h#4*%^e_XX)hz!cSWKfC#_6=HzbvVg-BjL|*7vgRQ6gMTM2j>|N8WH8jjU{b zJHpLO)^TCRTVRT2nyW)asJTMvGpf?`@P;3o6{bz_;$=%06o<|!=J^;Hf6T|D!@!Zj zIC-wk()}7UhI%Nm^9eF4Vis2S*bD8dcZR*kvK+>2Ypd)Eo@XZGn0l(tQ6#&7XcrbV zVKwU_AwO1FJ^W9&s2G#d>^bs){qmLtOR!=Rwi#S_EDB*gv(}91&WjI~%B-?#v^B;E z139O_7#6Xyk?K`KzGF}OS$YrARY z48Tn?LWvsdYv{*t(HbjPQ{!};IiO(7Y^YBlTP~bFs7f+kjp>`WP%+h)$lKE3BuGrb1OCOe?gt@k~q6nQ~vEN{=oovg?bn{~Vj z&~-8GnY=8Q7OIliQGaBUfR~YcT>yKIdd1c zkQ>K1OclZnE?vpk4@mbkGY*w>8i(8}O6FV>1ArO4?9@VfXB`W)b$Xps6$@R)0=O|S zT&Iw3j!Dm4%pnBjN^sgw4Yi{xZno}BJ<{(+m7;RFOpc?lkJ&vcuJbjdrejoXYiVtn z149CRForapG8~7E-Z&f0Rx%@cfX&Ut(6YBhD%2s9X^+-v&6FgcDDi@!>-tHRn6EA^ycb@sdZ9eGX>X%8hb=?65Oh^ zdm3h0J*#O3HVjc3xD%#T;a4;-T5gn5(^%-NQDAsK9H^A64jq5R@;19hj6I?ii(8to z<}(+IBAg(xv>cS-l-n+oE-rMek^W7nW*(X*-IqEn{y=+V0PAT08@F#Xibr2Ky*S0D zo;)MYZR2z?XpBs*Ukwa2YIvvG`epU!2r8P!wk;?5=BvuzRlHV*2`TNWFISkaCE zlaM?6dsVzKTntBN(Rjh$jkIA(v%JY|>c&|$Fepv}Y(beB=JJJ@q!qIO+S!J}U@YPM zvK9*-9ICK2&81E|j(ZK*2MfnT)7WOcBg_xm@z_?UIkeTD?xaqSz;H&bU1kjj53`YD zxS<|0x+?uKG^Lq0!5AdD>t)P7Dh&pUg@tQs_jV{bg=?5K1D(ieuMEp%OxbNW(V|V5 zz=_4_5{*S8vT!$Nde+z%uSsC^g2Q5$YQj{FSl`CRg!U6$4cmPflqDks?w5)`OSa5i zv0&XopMDtcdv&yLKk2rk9jkwmkE zj9tpms3xitcDL4vWarvVc9~LRFKQ5*nb>Kjo8ZQsxme^1W#S|GZeoI$sf z(Qsw-(2S51*Ri-8U^azmDAGNM#)vYTCH#5Z7Po8BVJwQ*Xttfw!(kZyfX4} zu@i_U_`%R>Ty*j?3q;-w%xg2;vJUgW(7Os30nDx}GztwV_5IPAsomXAd3J@y>=Bve zSy%I!<*%-(#bTi8X9}rGcj(4Oyr~4fH9ZA4W}!wLn{f0E>rk!9r5jrM=?yh?3^Yk_ zv*;-&(dmtu(Oaeyj7uMGWf+XH(+Lnow7+8JJ5w2a zm9aO?skt+-VNJJU2y0s2+S1a@2BwQ(T%S~?jmUKITs2S;8)jte;$gz3vXhaSEM}OQ zbfAQ7$3*7ly0o67SJ=7CgvbP|$U3Rr&C-lK8g5g<?==T{iUaQj=9&JCNQG~KMFqtn#V^kKSPOVjOI znr_$9ap`6=8wCtbv(YXdwjt)hyD*){4ELFvH&~Xz@-Eh{!?L(SU~K^2XcE&UdJ>&t z25Ckz_QS~=^L=Y78YZJ})+8B5V^+OkY-!#R#DUH@jOm20Q__^&4r_Un?T$|v6gC;oSY2ANtx;^oj0>9Bkq2ymnW3zm!Y- zA!}DmTc_m1WnI(*562s$>-=Vn8tf%@NlzY_Ee;A2GR$x!W`q%yt{!+lRnm1RvvbUu z_A)5_UTG#qc-n+caZI7Jjm1-p+f;RAZHDbI3kLHT|5QDL!xsAmgJ#T%Sz8OTo4;tm zinf-t)Ns^|>z26!OKD{RRNVA}y33BGVNY@^b7AM8-q>AvO+Q@Kqi(IIxfW%!d!>pR z4}BCGK5lQ#nYSB`IxhKgb{-$$A#SrEo#Dn!&2L*8_o!vN~6dP7z5q* zNQQ{idq!cn0mVgPxQd9^R!yCPRsIw<4b?x~CDxHkj+Fwe^JLU4Rz{kr-{ICm(k#ZB zXiZ9NIw&UZHCQxBV09rB-q_NPt4{KCJi9RQ1J_z^6UR#U(})nn4nR0-!mwha=NBz) zZb^rQj4s81$(GPwi7Qj4H;tC1_;rXFgPZL@pA-u~v#>O0!u272hCiI{zg{BAB_cF$ z+EouNzFFa$)WAsoPCC_L36woIZLl(IEc-rR`+>kktg(fXyLw1eB``g&M&UTu35VP; z9hP-!;@m`Xxo3v3Ht(^#9V;3pu*UhzCOj~_-S$ffo}u#2c2d2~f_-Lxh-0CU;pfIB zG_HL{CzQj~DGaw$gSgU#>w4DHFup0G8C`1QD^1OqAW=dI+o7EET088m*Mu?UrHm;L z+0{3N;iOarx5pP=m+sA))-Xl0Zqp}_E9wKQ1qz6F>9MBd_BE~i?m{)f!Z~ww&*zwi zHzC!gDd+{H7iAQ#ke(}elM;!t;$aL!scKtNoWh!Kb2A^B=^GycnUpC%8((yXJpp46d!z6sOMf!&) z;?4CmWq^m5(wHAxCSqROAOaveeAeI6vODw~Uf(30*rXrS>3m41bG&aU~#JJ&Urs|AO5EPJBJZ+J*YD7E+Oin5V^yc?FX=jaehm8hQK##84X-I5 zElCXe%9qVCNr^e{=MBv;F)UxQ)A?^Yov-M0u7|lZA2}b~?hS6n>gp`4x8fZN=?P`# zmVCzChh#3iOlf4mmg^5w znpN5!Zbw{Ru31KSQaWvm`6k@4T1 zYe-Ja*G@caNLj`LZkQ1d!leKca~AI2n>6+zUT)@xw{!?fGvpr)E&Q=iw)9=iE0!$T zyUB&S{^$;aV&6E*Z3G3U4eEjy+8G>c`*W8q?fYiBjI-l^7tlGXbb+B_pZ>vlxqbW0 zMiqEh9QkgobQ3L~jjHUMTe>8y&B+>w7hEA-Rto>%x6veff0u2o-Oqvnq;1Qp#T&_p zb@ok9S({qESun9ZNeA{4atz3VDc*#*x$ejH5xNc$P5QVHS(Nj z6V4FsD5MQ0-vz=Y!sWufg$D|0lbQY);R(W1g=Y&d5dKkkweSYvt-`y74+{ChPx4Gu^LB0O4nypXRGWx78IFA`oM{FCs{!n=hJ3I8g5M);EOP2qdOPlaCz;h>m& z^Mrh_DCOuS>@VcYK}p|SI9fPfxQ(z{SSOq=+)+4JxJcM4+*5df@NnTu;fcaCg#5Mv z<+)UNweUva?ZW$nj|%w$Q{MNy@Kxd4!ViUC2)_|#!&%^cU4%V_eT5qfHx-T$^8LcR zuUr@x)(Go`vxGYfTZD^+%Z2+04;CIJ{GIR=;n~6qg_jGj6Y`ULl9_=#|h@Oxn{UVKBo-Guy(6wmt!2MRY6mI${JZY@j+YlV%%9fb3Qi-jwM2MCW8 z9xpsyc)sv*;q}7Xg%1e-Dtu1(n($rWXTooUJ_b;hv%9d5uvoa6uvAzsObY9SGlfmU zg~Hv1`v?yet`wdu{Dbfk;Wffrg!c#^74ofOl=~&&--RCu*9aqdHeDBCp|HPjh;XEE zD@=L4|ZZF(bxUX=f@ND5N!Uu#e3;!j|i(0-L3rmDm!Uo|yVY~2f;VHsPg!c*` z7rrCJ=NXOsJ%yVI#|ftjcM`4;{!#dVaJBF~;a5VuYuE6v7S0p43Xc+=BD`AohLCR= zW&QRP4iwH1?k+q)c#7~6;myK_g>MNz6?VakD9OK{uu?cx*eYBpJY9IL@E+l6;hREE zl*zZ7aENf6aJF!f@EGAG!s~^rgf9s{6n-!42gjB93=>WiZYP{8TrNCJc(U+f;Z4HT z!dHcBgaI6O=Ch%2xUfQ4C)`=MOn8j&G~qSEyM<2*`R!%$|6J%}5r^l!g+qnog?xK4 zueS)>gufM@DZD~>yYMmLE5eV35iE|7UrabixQ(z@*eqNjJVJP?@KWI|!bgOBfjjxX zFZ@=x0VW)zZz|kcI8C^VaChOc!ZU=|3GWp?C45Wxr7#bRV9cklaICOO$d9b^`mVx# zg)4<;3$GI1DSTY`n($L$Hs2Qxenr9(VWn_}aK3O);ZZ_l!mow-SSDqD#lq3T zI^hn&HsPVdbA(q2?-M>P{6zSjus0SBnNO*38{sVBa^XS3(}dRx?-sr*{94!tZ^9+t z!NLk*op6zG58*k&YlL?TpA^0!{9Nc`vC*`LuvEy86OcYj$PW_o{2<|J!aoZi6}~9^ zKp1Q+{=$*MZG<}t7YYv&o*=wZ_-El8!q0_%vG@yz3daj;ggXd#6YeKGO?Z*;b>U~i zoJ}nMUcyauIG~q77{e(vg9}qq( zd`I||u-72Vcc8FLI8!)JxUcY3;f2E6gntpfEc{5wjS1>UPvJn}7~wSGPQrHK;lfjd zmk4hbJ}i7o_^GhV5Sw2=;a0+=a3|ps;nBiVgjWgg6h1C|P57;_%ciO~;TU03xQlR! z@NnTN!b^lV3m+D~ApBC8JyhipZXv7`P8Bu@TZJoyrwgwY-XnZj_?|F(n9Zk1I7B#3 zxJbB<@EGAG!s~^rgf9s{6n-!4v6;x~;Tgiq zg|`X+B79l+kuW;S^6e`u5!MQ~7w#@RR(OW+I^mtdXN7MGzY|U>vH8pswhE6Do-Djl zc&qR!;egTh{t3cr;m*R{gog@G5MCzyOqf$@`ScP_7B&la7alDAyv;TmBu!REK2aJaBSSSQ?BxR3Bi;W@%TxZe#NqF02sN33nFmBRo=gj_?}c zD&h0OPlQ<$RUYARVL~`v*ecv#c(L#%;X}gbh3^W#7Iv+&`3w+_6mBEjQMgceyzo5X zb;8Gle-mcME#HlWTL_cFU4%=7hYL>;ULw3%_^|K=;d{bwgnbh>zahd(;Z$LhuvK`l z@b|*2gtrP;3*Qv-14h)VZo(nLaY8&?V6Ha__Y@u_JY9I1@B!g!;d{bwgxyk>-$uew zLc~j&d}a#|7TzgbC45u(g)q0;-ZxM}{vCzOg@*~x6<#TPQ@BQ$JK5e}Dr^>>C45YnTVvA|2?q+N3U?CjD%?xB zQh2HG4>9x!YR4bAmhcl{_7t0cAS@8} z680Ak6P5`l3MUC0g)PF}gu4s(5*{WzMR=C*0^!xd+k_7bpAo(x{6v^rYvu1P94D+6 z&J@lU9wb~TJY9H&@D||%!qvhLgkK4B>ukP-!lALd{ubuRLlQf;S<7FgdYgArrC5w!cB!+2up?IgD7;8`x$s)yO~TuS_X-~t{#E$2@NdG`gl`K!5Pl~7O8C9duebFR z6~=@c3AYfI2`3BjwQAG8Ey6b8LBivNX9+J8-Yk4T_>}N<;m5-7gk86@`D`d0C5#KV z7q$rZ6do-+S$MwiYT<3dhlS4w-w=K*{8red!OAg6SR$+xZY!K6Y!>b=JY4vo@CD&J z!Y_nbjW(YGVWki+crx`pLpVpcM7TF`V|=<@=O+<|dfsWmvvvJeUB8z&03WN>`7^|R zp7)mUBhmj!?2CA^>A>OGKO%x}Z(%>thw6N|a4XUA=0Gp27e1ye`ds01;hw_%h~R&e z&Q}UgAmaWDbp3K-q31oI>yHTks_TE#`76RViAevQu-6Qm&j4aie3X}n@>B?`biGdJ z+X-h9k$%3eFCiA-Th6+EjPQ6}KU3%D2rnce{T;%`i74;ih}}Hz3nJwBO8A|w2Qw|b zn=nSieFJp9iEvXQ_>>8!5Rq;sF^U*yBKWrp_ty2pbbgfZSkX_@`B}pAh~RUB@Bt$D zKS2yU?>!>;e2tVU-Y3mA1*8*f`3vtTR4{pK1+ysXa^$l zKSp@GuAiy%bA(q5|0KMbi2Ls$g5SeL-}Bzk^|yuZ>-s-+{qcql9CG6~c+a8eyGqrf>)0JmCUitFT?Tzwlt;Z-vJRPZgdiyijd{Fq9@JZo2!uN%r3I8eV8nO5H5Dq26j+l5-V5!c>2~9jH=v6wOEUXpI70wr$ z_)(XDmPIR|u~W-Xt{fp}5YEz|+2%I8flLI)77W;y^)XEI-qI zDg2j^G5n+#3Hu2*7V@+2v@exH#`N=ivamroQ}`R<9HEKxMEbpSexUGBp^5Lr^)q$O zZ@tsr+$g+VXyQ6Se^lott`p}bt`qoz==?4`@Bc)&M)-}8--ze+A|XHUPCGM3SSH+B zm=e|q>xCwM6Zh?`a}&Rba}&P_Tp~I@7Ek`i3QrQACOltwvG7XawZdD4cM46MCip$0 z^OuCL2|pLE5q>W;ahkY~AC0Ho+ekP>xS4Q_a4X@~LKB~f`}l!*-oKM@o^XMXADid( z1BJgQ!mgV5OQ4Cr1fD1QO~PA+_Xr;l=CWT7vGMlg)0gMqUra=Kh7r-8B}C}acp~(9 zA`$%q(^=Dh;Z_>E0JCQ7&n`sxJqwBOhgylSbNn$MWN$E^i2S+=dk~Rtk5{fksZqHJ0ZOG| ziOB!AMC5l45&4<=Kp~ODpc6KhE2E9r7Hd`&SYn z*A+UyhDiBzeispPzN+&#iI8`V&c7i-s3O`s@b626{DXBqjEHiK)%kcL^lEBW7-C=8OOAOISwQ<2iHZwzceG8_QDg&6CX2Ie7cg0)A1I&1qBokg}NH z>eW@~gEx{NJLTJ-Gwzz-HfISERW;O&oYUUkh7YK=gYCNipq?Jo5KlDPA8keE4?~&x zZGwN94kq6GI;Z0`{)XZ&AAdiUj<%_DzFk3cKbQ>jLpL&?RGnx~y_J_*{`CErhJVa& z8vZi*O~g6vg!?&uQ$T=8Ft&l$PRiiNI&l1U#c?LT={O&TKlgL|=7W&Q?=0}6U7~!H z%keuN$C>>0!+C%Fxu4^=5`;{C*MnaV(8!PevExVEl*#WjoUe`F6`*JGyDx(u>)Y{r zq7%RCe}vy(I`MldgJ1Uyejjw=_c+d(pZmG;{sV+e`Q8M-e9%~4mfOjfkHTh__eESQ z#-IB+emO{#$?yFP`C>@y`0?4TOn%?sTCroMbUfXp6TfdV_))(cKR)A?$*(_7l4PKt zlW&_&{JQ=zUEbbE>-h1RuuOit;KcDDOLsi06ThMie$+$9kI#^0@@xJPek(hrTZr=# zW~iUb_bAXa>$yMjEk+u)8*Pfqm(QHxf6v*G({RG}bw9`NPNj47b8&wAY>_nr9N0e-EPh56U<`??dq{lJfX zj{Jt;&++SthH&?g!N_Km*BO7DyKCK$F0;I~&s+bM{AlAHzX9UsbR>5-ymwpb68m8kje@+HoJ_+e2XAqb#f1^9ecRl2DjeD5-2LY zk1o#mjozwc-1w5x@ueljctuJHu7&@O8#fkb6DEwa$#>~;V5+t{5^*`Q-iCFkJ3hCC zpKqIE800VT7Jy*uFeehltzC}+fj%gIS&`gT2J$~5Wcl|P$lHsM<9}-)4<56ZmG7HX zfc!k@nU|g8^JUdpIe9oCms|=J=@}W)y)c^HyH>&1$N zQ}f#Z|7M%lP-I2E?%oX_sWv4AWBlLY4OBn;?8pDw%bnNq{wsXNzHQDZycB&DzFsye z#ecAGn^YkVy)>`Jb^wM7y=upD&gx^m}zsTO4{bzmmDO~}q znqTgnLcipza60s{U*cUj(s%=W_f6(6+cSMCBxM^56rQ4s&?`*;vb|{f1V?<=jeFOH z`S_4kKa)!qvZ7DMIWp}P5z|?N?0)z(yjQGq+I(K8{U>fItPm!IwCTLQov=wrKbdrv zj%x%zd(OKqldN!7r8(D+&Y%9r(H+K&XJq)wnraaKkU7Lz? zcg#!oskBpcP^Q8v6e1C&ucMlG|m+*%rk?`lPEdqtdEH{7u!r$BO zB93{;KNyJ)>0Uzvtj(|3AL&rXp&u|DC+p$|EJV7ya4$wJ(^puIwfO5dIkS=o7N2abhv=Z#!8isSoF`vK$O4ef4~WF5!;UDk2zFGhLk=eVB}we#42&5w-zqe@FK+fV;~dhGw@ z)&QP@&|S}m#2I7%$)I8EznPHbbAcc$%dG(zzaSj@U%-u7`FZCd$q&ZK*vIda; zUf24eJYy*TIbIT9RNuC2aoe77mVN~;fU!SRaQ=QxK0szYulED~M_Z=9IzQk)X$^q; zCho^W{&n^PUSCH)V2gG11AfjLK#>zpvhlRDAMg`v0Cvq7>j3NE2b5Z`;iuOCCjZ15 zK!A$u$|3uI9p?YxNykO~pEGDmQ|5W=cLLV=>jJ;vP5>3# z{eDe8K&Unle!UOy-{Av{|2M4#aL)TnuLbbE!|rDW7o2qV0bW^0A7Ha}^Z}aJaV=ml z%FFTI{hX+seSn*PWGz7Z01H>lUB377e}@miS^p1xfDb_Z!CJuAB!+7N>wN(8#qOWA z7VvWhd#S{{bnrt*$6>t>u-*q)=U9M+p*EopulE7g`v7j7f;#--u>k9R0M_ac*8zUa z2N+e#=)d&u|K&PB7brsKSb#?%JN5%UBxLz_8_2tgkmECMI_(2Ihr6*3@GOWw*biWo z!GGd9z|R@OvF|^B(fnoW0|J^y&|N7WG2eX~XTQ}cH@Sn5}@b`?4X9gE^!p`deudd@d0KciTF7bdrXB~jg8@Zno zbzRp1MwN~kpY{NLIv%jJWb``k1?=<_djWiYwd>l~0oI^AKUfD~w13(Mc%5fI5))9s zYWVMXF5rJ{9ROB);hd$-i(AZ6(W2H8coRRem#}_G;NP(%@T-jtSes_8UmN)ESR3Fw z8}@>6W*i$1&ENlv=LGIUX210Qz{ebA^fLnvjywAW@2;a?Fm@gN0)9j9F68r5&j~Ol zv%h2`I8i(M1*?#5ZO;jeDjlci|EzcLQ)>gixL?5Fz>NKYr*Vq4fpzx_Uc(JPSR44S z^b3CG!a;{Ye>9g67A;uX(p;S01z6`8gY|yFdcR=ZpBr4**)O2-t@jJo`vq?7f<^zu z_YBti1+3K{?iu{JUob(>1FoB2@Jqf&;3>%YKYxZm?-4i;On%@Otbc}J+0q5Y|IOq2 z&vB9#^<6H4zJ{G6e0 z$(*Hg7PPc=82Q3Y0nFbzEEa?p(n|+SvVK+I->@o>Ifwc+`2cB!TOT{HK6W6zj!j?o z9Qd17d;q6<=&tL1fd393;6Ld(g8$_A35*)E<gwYo+IdvNzMQKokB0-?jL)OfNv{W{~WKcc1PMt&FFk)kikIH`PqRt*YVkbk?Z*E zz|VQVAiojjeooZR&ko%6BhL=lcMG+y^EU>z95ZGs`>?@J`vM1X-#+78L&cc*kH5jM zK7LKH_x(S=`+it;WD}xa>-KnLY^3qx);i{1ym zv)bM56_3B&9Y=8N-C1%&PW3U@FlFv0#nr^k4L^JAS37ENL+$nXK`S-F?j3mSnw;XIJF^Bx2KrN?#gRX5co4ZquPM1bGG)L)L>9OQ^3OFT%gi^sy12T( z=r-s3KJ$uuKwhTr`y=Ts{l3p8BIO;k>@zs{H}ZQlaM#6X)Oc~nk8j{hOZ=vC_Aq>5 zBWrly@sJ1WD--Zd7d)eR2R?_Ey`TWc6E1-17^FA1aY{PFl6_8P36#w)s#QnU+>{k!mw`La~rHjpPT=O~=#OzB<&vGdKBPx6OhnFw#3?!)YH(aX;N5JKkU z|7|neoDQ*Z-e~jA=QTY?_e*pU%rnV`{yr51#FZbptd&7?^o=3#rfAD$4&C1$Yo%D6}Sz` zAGrxW`I`R-j)&y;FZI0U{GIU?la~BH;`pKb*O1G@`3abYNAmv#2l~Cla!0C~o3D?eu1jj?9Gb6!u z$msJ(@Cx7y+=tu01Q(qBGZI{a+FBC{hND_$X9aO&bX!(%2}FJ;JJ>YpdH=``+M%EC zW(N;|=X(Hr9_9V);7ioY2id{jQAr+joD=MZ8)oDL*XDWN z%$(p$5NG8CwP>K(AP(}p?Q?>?QK>uR1j}Qdw_{H5JE+c1IYA@xyCx@Ch{`YWgXeKy zFF%-wn%K(^zCwxi_JhGtmwo(T1c)#C!N^|tPK_U2gljMRK`*d=#SeZ1eS6gpUPFGb z`N20R^y_}G8I7#hq4m!3m| z8t6o8pWt^W-|l?^l*DW66P$=_m-h*tLdy0&!5ZYgqEB!pnsJXl!6f9cXP>}FJM7gb zXhS#HyHD^nin33i;21RVzDNny`}GOFL>czS4QS~D`ULlZ_kn$aH<09@K0zUJIJi%c zgVIhsE7%>`R-F|DC9rR21+!p*l4k`2pmnLUf>KCbeO8c%8k}@i@DduJ{@!3mT-)y6 zU{9#VF7F1X!aB`)HyDF#=e`@fiu#=QZg4+xXnr^N5Ph)a-QXmYVg9?pD`?aO?{?{n z>S^s6@w)tWGZdQ#&vZq>d2j(J%X#n$8nB%Qy`Y9Gc<>ymaStB+6)JTQzTDhp0J{9a zJeZG4IfMssbjCw@@FL1`7!Q`A4G!nQM@W1G4|YTuj^x4q!_jk_aBvGs{Cgf83~5i~ z!I3E7Nj!KSg*urBOHjzY=i%T6w8K6;*a~H0G)0$J3J5s(7BXk?UeGD zf{)LG94LD(53WZ`f6pdB$D+<|s3ig>UIirk9_Es&5>cexpg9O1zs z5I)OLVCS-V@FBWu4iDx-8GIg$hVZ#O_zgHSRhOHfZ4n+^i`vNI!5wG|-seSIag?(( zlKl+MyFP(`$fw&;IKa17W|Aif=E_0tN|u+~$}1%N=s(@F{73xYaU>~dMbr6z@%vv3 zu33>hui!KoYyUAvKt=Y*@*nX1&ycuh%JU!c`!Z?IRMT9~f838=0J;Z$&-y_D%2aSU zs>6R?w?l_``)c1W#kHPOJ^yLlK9#q>;77^U>z?D^=La=N5~ECBjGVH(XdK4Df6>q8 z%|0(9pSS(sC>&Y2-*sX-x!-pLEB70|e>oCU?zb}K{>YE+2s-(F=?4#zpOJe_N4Y=s z{dajg}R(*Lf{n?!q)hAI0EYT4k)vKmm{F3p<%C`;CDlB zE}X#v|7n8JjKa^M{{B4^qVpje#e8@|uo)5+l);erkBUJK3>O&OKf#|$24}!V`45Ug z3Dn+yY(kW*$>8Y;!Bu4N9{Q*M?1X+df}EAr-76T!Y@ZV$(#)qqBcQd|NBwUdA=fLoXc!3JIf9Q{DBt&v z0CR(ad_2MDNLBbEhE@MlHOGF;J+~~%BC;Ue%Z#s4@D6)tk20%vYR@iZ{zhoo!UJK^ z{jOzJA?~3pv9c&xGnWBn-4aanH(HvF%Ze#$VK>%Yaar-1IAJbB%X;pLL`9SEkH1;j zpmRwtDk{a<=4FGJDned^%DNp%UN@815X-9uN$;xQS&w`3vHGrx!OTv*mg{vzIp2J~` zqIfZ~Gs4xB`Cs6;Z~zV46bVNzY_a)e!F<$H!R~M~{Do<~D0r4R>?%S8`b<;qFLs1H zuXkO1mgg@OAuGr0-H-yI)uo7d1wGgtyE}rdjk#t1G03p+udMfGDO(%6S6f+>a#E_j z%Yqju)uqEh-?z*fkFGgh!E?|?|A4ao#+pR3yn>~0vit*G7RYm(5g;7o2sY0ZW&Zcf zb2WR&p30M7u=Wowi&7fqd30HDFf4#3+$`Mdk578Jr?Fi8J25QDL zjsUs4n9$$DrcB z;RqPm{z)VKrX#=*Orw}@IRXZ@7)RH)9RUTokM8L^j(~z(!vXwVM}XYrbT{5}1S|L7 z%KVEUQeh3t^pfPBz&qbBi?T$N`}4A32XHSK!pi&7F@W3)&_DctIs*KREY{T;N5GK% zImP_S5zw(0at!~MBcP}?MXm>8c`rkW( z^=LmX^ACj3g?%aXrz%+`D>_mhWtmyB{PJKd9G`;Y*x|dBryaw9Di?JGll$x6zDLs+shHtd*k4NH(}4D%f8I6|s@ z*(J7g1W5HdwR|f_fUd$**rMFOgn6Dz)g7rkClupkLV1+ZFwcqQ!DcWv1&8~f#~lOI z<{#MT2}eL}K2ZWf$`Lq{QBSHx$bwWc^eTU{Bfv;q%7Sd`Zb4UG$b!^50wjQ#73Ka^ zNKp9B=D4=C#JrSRT2~%r0VwA5@?Z%1M!{+H0cNUd=sA15YnI~(sXm}u%yubIHTzO6 zws*CO2D_1(w}T^~!RROWJ30d7zL(0nlOw>m&SLfc#^r*7e9ByQb_Cd@6X;4bIRcF9 zU@G4(jsPR|6?^|2N3dnDFZZ`au?qJ`G5rRW{Ye`Cx#dyT3d_EzJouhv&t+}y<`|%f zuA{|S;t0@_?`bWTIs#f`3F~{ABcL*dGR5wWfU>tUMVlj_><3a2+8qH!J(7lQg(IM- zIc%Ff9RVe~ir(H{j$ljHQtl51>%t9KQ43VE1g*l}KLG8 zd$aNma|9^gJ*6NV?g(i2>)Gx{I0D-JWg5C89RZbbA*DLX5l|VIaUyuMBcL*d(DMD( z5uh1Q(~KSC2&kRyMuM=?5o}l9zufl$xbd0{)7%xFqCKLG8r%+E$a|D!ZNA|PR9RVfFrinPi5m2&+HU;5KM?lH`#1=Wr5m2%ws`%NCfRg=& zHt7$JfRdd=&_0$=9{DA`!n&Yv6sCEJK{T<-|BWEYkD*FosQ3u(hHQOTyWwQnqsvdk>m?d8G8 zELk!8*`4Kfnh-_rAH^*0b{wJb=duy+aRl5AGj>b4-wWj{%%P6osx1CV?Z3A?%FLO? zBjrIHi3*;fUae9VG-HQTPaf;Y@qu!G0Xe=v-V8?mU(2J+iyWUR4^AS-<2jZ* zCysfjs1&IFi{hA#P7N8KEcb6AN0ay|aV(|Pez`o#yvXtI<-y;{aX9t+9Wls9P1jJV z-gN{d2FKUS{V4ib;X&-5Z;IoGRO$E1qs)sOKP?Z2B2mFB#h`yK1~4LI@L{=MO9o>p z|HopmA3OIK}gYkDA8LTPyk0pbKVYv1$F*uO*{(X6rtjQp^BKRX2 z97E%lUtzr=Nsv|HKSl_Lv3hyh#jVCb+v zSOjoqwe_p;4<*MxQHKYJ<0>lAkcuetBF8N%f}zlz-t{#}H~?b6MYDi1j&d?W{odmE zGrB?^2m0L_TI5nkfDmo$%wyawDCbcmjCBO`yRT`p$2kH9jw`7K;~fFr<~wTr1jp1C zWLSk?3mFUdBD>91kiXC{msLbrL>44o5iCTaf+-xRlj5l5rmZXdW68i=nhC;@r75;Ts=svv)a|K* zL0DN~Z8797sAtKJb1C3weaSK8c$dOy*$Ixo=7{jAyAu;$RuN@!*sy=92ySCR9%a|R!DRu7pcz+J_^*+{w=_}Liop+gecZlPiZ2ku-qRfjN zAFBv;4mBfQX8M{^&6NlOkX&D;P}YW3>o;q^3ua|44;@3bVMFqxGtaz8CYP zjIHu?Mf7r<*fu8Fv~l2>^j#^}t!W}wK3}Q`xWR7lsU8P?^gsC2$(juO${>l}R7!5oT|?+DQB_o)_vBS5oPQM0=^0yO&zDpk}G zpxNC0@w++#G`ohmbgxv$h9WnzDhnLJDsrUKUj&f~Z==7JU1^8rYW9hql~I<6a&J%> zyg<1>rjqn?S)fNA!`{?ige-{J7j^9qa48_BnJaFrJh7o)@D*74n=LGmHzjX>K2x|kEGg>cMh$LQeH|mvNG5LwO!CeAx39#DGQpYjdw9n?1{&q-Q zID(_@7UI~Cg&tcOWnSc1UKt!fjt6p-uXGGh&i$!MTUXk_8|7q+Z&m4EK#skra}&gI zJPR|iGRnNjaZ+XQDLH;e1~pDb)XVXdqt+2n4Of(aQ0MZ58QzCN)H?#$A{uDhK%#496C}9sWQ7b0yN|Z4xRHHfo3Gf zpIPbe!z{X>PW;)GeRy}_ESL{}er1%IGm9ma!F$Z&@5s_`tyK5z=M~Ik7P~vbhG-mS zvD^{*V&YG!R=7MN)ovv0;Rui_!S1z}BUq^xRr)<(T?=1khPzeT4&F+s_Nk0gURL(O zmBGPCR8T=Xe5liNG~d_sCk}H2bgzRb)e(*WA#&M1M>zt7NcIHb7+3q~JUg(9u5^T4 z(;WL(`WI8G+vraoSZO=YC3!eGt};q_Db>l9!D<{9+{8RjbqpZY`wA@4FoV1zE!s_c{U;Z3-*s zK1YC}oyj(Mz!9KmZ_OgXq|tnO7;vp>*JMCmKiaEIsVlXf&)=F9|t`)_&q1iXaox}by?gbXd zxc4@&XdC?NA8OMMj&W~nSd3dwo5#2rv_*`2EhA&x{V0iXFQK%Eo3;LjHm|WUuG5c; zaZP)CjO)K;F|L(X#JGC7b&QLH6JuN^ix;)9Zuc!WawlV4V5*MM|D7D;!o{{RPV#GG zoQF@1aqe7SbRctj)!xw%sVOSPL0{g(sqr}=U*J7pT0D9Y%#*Qif-pUCshn&O&?P9 z5YJAo82E=g#9uaXn)>pPP4QTaUfAPBHKaXTQFszK zy&0oN^l{OANa+8)qVRX1ecqQIix=rjzauNM!9u40zM^m#a?6SIr86-xvcYmv3oA_> z#Up(=R3{^SIW|^D`f@;<9O=tZXxqpJ2QcaM%EC!tP#fvXablN9U)u8KNM9Pyg^|9r zR=Y+vIGRb%sw}(|wX!(Umlns%>C66#QM>C*bOzR!@$+)9#fxJTMstB9Ug+hXh-06G z=nQt(Co8krbNnkofnl5*4@yR$_nW|)=6Kp0GI2EX9RdB)#L+Bp1oTT2N3+lo0;h17>#9RXDdq?gk3yUn54J)g8%J}p;|N;-2EU8@JCT8j zqd7qgOdQRr@hDl7!5$S+#ztj;hOEqyce{=+{0CY!+%N!xc6y%J!KLj$`IGVH6943zDns}5& zWI=9@2URSHiKF?m7^pq3kNfkE3v72^p9em;2+!4=RlLNVqCqK-R49C*s{!F_8(xSsl*^#Ca+n2IBlJ-t#jg zvVk}+#Rr{>dliWDay%V~^K86Z4>*c85a)Tzs~5Rb(!a)op|}{MNM4NWOgPEialZoO zUMxi~-p#b{#=FhNp)J+>9ZU81c(6aN+2ELWRH_f4S^h`y0VoAdp?XrHiE}Xs8l9`Cz42)>R<70e!!SjtuMedaJ(|GVL4r3I_i;O;jZB?A;c@7fU(4T>>R3`LiP)4cxC%WB6UIUoNMwVAEa;Kz4iC{Gj zV~jQTVq|AZm6!0}!ErB^q8IO`3Xezx+hZbRqd7(;tf6EyhY9%^EkYRbGsY2Ic*m9^ zgdsm$xfEE-F(E(W9l_SZW(ofQWN1Tvh9|6{G$B6|5>d)WsU{|ZzfdX@*Ah=yI~Ruh zq(lfqekQprkf#axnd}HQ&x(ZqDf2WTKU*tL6Y^7&h*BEnxm_Y?ALDAGQ4ClUCe~?& z@-tU?nvkC*i72IEp6!X?cSvNF zWDhY2t7b39(N)bpB7{}5uS?;oWu9}sdtL8YDg{zw1IfBje(1bq>>}<%-;mXs5{2ZT%QX1xYY9hFm zd76-)GaLg9J0|4kOh>@5V?ut;as&)JCgkUAN5C}Qg#7%$5l~kqf6yCW4d4L2eWBbGc)HnT!efxzZ6Z2Ahzd zs~iDiunGCO+7U1YzX%`Rzt#~@_QQLDaGfKd>?SDadPhJ}O;FGcj)0sE!jm0|IZNG1_fQBl9`~OTM|*0nI*eB5j?|^4dx8?UNPvBYfSL%3IA&{FtImx zih+r}xjzvlYcg1s2>NUV28(cy|5!%`4<-BxT(coAkBET@ad|uuC2KNxHWADwgZEes z&v#_7I^pk624gT_`cI32i6r@3B1+a|@OmOxMFu94zlru@IPUmCX(b;S8c@*;G;y8(lF026T$NF$kRlUtZ@vW5GIo3D@VZ8)Fo&6Y!gY+#}RDVbCdo_D3*;R$xqr* z(L|E;O-5NOEc?dEpr#CEH<2WpI0k4U6G<}25zuE%B*|b$fS#C0k|BNls;vy!B!C!EnU!9DSH5t?;gRbRZa3xoyrgdaclk`X9nhiggA_gY>V7p|LtjS#~I52Rpe+K`oi^gWos;?uPD9NBc7i6MisLS(xyHos&^!&MaDz!QITl zgdZ$W7Ge0oqK+KrBoPV#jwbwIo;cnNM*gm-cX8Z38Dv#}qlq?X7Xw8bEJ^x9am_{> zEE5A0ZLmi&O4bzVfMhV83{14aL1GX_8yw;YwvhWI{k_T2L>ufUjwagRuw;~Zk>fGR z;AC=qr5K_fD+WC*gCmnz_y7YFZE&<0m}rCFC8K0b2B##0XUM=r8=TgW!S9pUTLA+T zZE%tpm}rADl2NiIgY%L>pGq(=(FPZEWN>!UufR1MZE%hlJlGGSUX+ZIH5puy4E8}H zyE}cg7=+OV*E#|$kcl?9&JnD&zBK8dW3r$oUZyNew88bsC^Kgkwr%k5ngE68904861SmZ3Zn0&5AnAXAV%Y$Nhg5bGpzs0)6_x!>^xbVxnC@8Ssm z*0$i=E(;XZ#EbmH5nKzt>j)^w8C_93?>PeOs0lcD-x0XnfM)SO6d}us`6~K9B(MPo zuS-l5aPUzw$^x*7zC{10m^*C*25ZECo$V2-%GVUE{=;g#>uzn z|F}YqIjNvD`m$h6T;9f6=h!JSdj9LP+#Q~bBGv(Aq>M(+Jkgzx49!Y zwHx8`bZS@P2xu)6!Z5}W&{`&hVM|9qO&C2K@0dD0EORNKhbDxf!liI}xQ!#A6bND1 zIOVTEDQpPCCaH`NhN@JQSG=yQioZL1G&}0srZRTa8&gqU@wzg*HTctxIZQ=G8@@PNU9wnjDJchN_i>O*{R?QN@X^(&&}XyHnPui z9J5XPoSyPGOoF4?$UajX%|`YGsVMUz$IDW|BqXvM*;hCQD5u%TzB1KeBm3f%znC1& zM)sxRXg0F1PDPm)Io_BGZY4*vk$tn15%pp=vTt<+3<_o=`!<&+I-}XhzS9xF4r+Q` z%72x4nvLx1m8aRrzB?7AG|cniR4_4xJiBoo_NW-ps_cx)^;bCpgm{wM3Xi!gU_?IU zbmy-kuyN`(0pW2GvTftspYmJ4zp#A>u01FrRu0C=>Qt2CQHU2(!SzVgyK%c22=;Uw zk!LRsA}^=&>|LKk;NmMHWaV;XYDDNt$2^}&`Oh=YU9sKZKc_rj=i2HUsVJr4;^6zK zpiealZg%iLO7(jJ97k|F__@_-smu<3o+Cgivx6Tvf|crDDgQ}IWp?ntNoDNd zN2{Zhmz5o>4ib|fmD#~Bs@AXpy)`@dy&M55V0Q5PI0CGO*}>ny5g>%w!S7$K`7Er4 z*})&+2)RZNyI1=Qk)hqe?@?{XOS6N&adnjPQmRd>gOe$h*})&?7(gnsgTI+0V21*l zJ+RvUGdY?a{K4XAcJPN+N12z`XK}>eDISd877M@J0P|wpaLS7Dg(x{OZrkL>xc8#% z;p^hs9_BWNwukSqG;I&x8Q1nOSO1G*TrKY#mtE@NpoK^##v)^j8nhKG0xw%jd2oI8{<4_YK(ImZ4d8d?`Vi|x-vb+DaOng z=Lxf8boO_M(PQ5!MyGn`7#(4455Jf!x)Ielx5xyjzLYGw7H8Tfe%W4|AEWcQFh<{O z*BJe&#jzIryEI0>rPXd9CsNuTHk-xC)WF~7h1g(N1R<4YM*Yj&3JO_^rHmMtw}eWWjKQbS||v(fxks_<|~Iz7^tRs;LF?Ah4QWmm#} zE_HX;h}X3{Bw!ibmMs;~Y}w9q#4cWLHI97}qV-7bkEqV3Hv7APvSE(j2EaR|=0er` z{k0g1I;nf!X2bBNkO-GQa<}dNCnU)4G6X02clAXrw;xDyr$#I-nd~&_MN;TuU~jWYxjOrko35Lyx}2q zn@IjwuFe`u8%?$4c$@|po2Hr3SnTq!r-OuL@zb)VmCv9qYe}y?f?nT*$ z;zIvTad(g0OM85blL4bpf4P@+zYA%-0Z$@v?&anrXTVN{IJv@{~<$+I`kMQh|fJAloK^x57f zIk|uKPeaZFH|U8g&qcohr-9p`wQ^sGnez014;9-Z_vRk2B2|n+dIJV^!S$E={T(Mc z17^aE<-Xjn9W3()w0FhH|3}<=fX7i?@58f_M%vL@lD(3#3^vFG3>aI*#znvgkD0gA#@Xn=`|4A_r7=DySsA8|M&Zz z=leh3KGME3XYQPP&bjBFTjuQUJ0sX(hm0OM9w+aclYD1f)(0r=lFRtaAyo69nXGu! zg;*>Fvp*VI(geCzmcZHm4ob+i<4Kb#1XF0 z)3Zq(mvu7UL+yDuUmD07`WkN4v!;tLdfuY~wtY|L#`pUp4>f;pMNVD|>Mp31# zqPI~p`+&eG77T*nJ;2c3XvypY1DSupNp_$G&3Y6p=(laolljMk5*&sbo#0s$(Y8Sz zW&~T%I+?)*=#E*zINsf0B!K&aXO!dK;F*(9Jh%m-c)>I9o*TRY^ic3BwA7H`2_B+n z@Pi;`1;M{h#*DzpJc(iK&CEhpe-AWN_3z{lYXzqU#G{SD9S{kR4sIww=27sZA@~ZY z;Ce7RHV6Yb#|4i8yW@l75mrtJo`d5PgZ)tKq~N9KioXgjK)atDyg%DyMa8VB!9UA(LSqny zbM_8ovYH7uLelX$O9Dfi=7G!kkTqvnV9cq8=S9#ur`taZ6n%|`$XV{6WfU!i{y8fG zV`#R_qWfX`oRxtwlqIWZ1G)4B#;`@Ri!OvUa}EfM`7^Esi{3z=&p9wKhAIpxVpdYl zs=ydJbWzbyuujfu|E##EoEohOjG#|AD0yc-2#@ln4eJ9rb1PK#D#x9L<8fK5dG*!ZLD_5EW<$9X zQe-a0P~g=T-vP>~Q*k`Qiw(W14KXVUy}i2d5xC%tZk&LVIbmMN8Xe(Dy@_VQ(LbPx zy#^Cuhm2l~2(@*}ZmiVeDwy-Rm$X<3~TnlTLH8%jj!i2X9dx@7Z8gA9J$X zXxi1=*O+yW(KM^KpE)TDzX(01I+=ID0A8f{7MzXCx(n~SKaICt%o}aI3*T^w#u=04 z{lfhQmnZi0Lde8+7l1gnqX-I78fb3ES0YY=e+C|zMy_Q`)-87ej~SiH4@6%NJZ{Y3Or8uO1DpN3j!oXRd1~se ztJ3be+P|yfOf+<0y}65ZFJYaVPU&!*DW=l(rc!o1zNVVWHyAd%;v8Z*d%gne1r9T` zML4I1(}v)!XMy8PhuY3M9DEOfW&~O@*5Q3#pxl{`vBCKzE)<|DTnOyxOeeSBfHcl0 zp{z38vCT^y$}Nb4(kmp)Pp;NWeZ9DgbCfW%%Qled};MyBPIO#X%P3`8k;X_7TEL>MW?9`f^a>QmR7zR2fybDt$ZI2?!mvQ zgQ6dotiw0b^r2uy(a+NbT6sIrDEhU@!oGLX$`AXr%r641GBfQ@4l;8st;`qcflcfN z#=f6JjIET5_MMmkW8>f0H-dv%_)iMCyU$Io0Q*`YXX!$^kZsAr&djl>l0rfhDd2IU4h{6rrn5<5q#3>FHdKSt)Ojr3=4#_XBVFnF(M%Y*z#{E%ouT71fD!Kou6oXrZW|7 z+DX3*IKu+v&}=#m(I?7{JI?qO=o!VQN1(w>djWe+g9RBRM%5tpxUYINn6(9NM{f3r zg`q{E1xE22*D1GB&I$!OA?#jLQ>59+o5(zMTkT{p8&qFpvO|Nf$+yZoPIM3nO^e32 zFZ5gtb9_ST&l4O(cK^k1XZ5E8y8=;W24I$dhgLk{dq{6oBN^TK4DbrB9XhaH5C_|I|>o-f9Mc?Hl89HPa30Ehesdvn>m zjmLY1Atsf|Vv*#Hl#vYhpW&2WOb+}f9bjIW=ISyW58~Ynf=^8H&Q6w0zu)KLzo#ij z(|{oXfg6Xd1df4&_4JKt#>SLtnb4juHVo?`vPcNhBZ6-~dwkjCqynHPU;m>3Lt*E^meP^+O?{*e`Qx+cWGbun(qFt z{?hJ>ME}6LWj$+42kg(U^_Q+#x-`+%x4N{vEHNcfQC3l&C@&*%5{Q%5tX`Q z&!qCQ$x|lr@?=~dbg8sw&C*rtmUWk|?pnICXHED2-(vJ1+Mh1Mij}3ceaqJMtXUgf z+t)oQX^Zs(ea0ldMOypT9?-pXpue=ex2x~Kx^-(39nfV(>#BAAiMHBlO?#I1b(Jpf z@1?T;ce$5#_4bsax$)QEx3qK#>Rh_Izo)-6)_ri#((cl>cyqkHw!O5$xBCBmVg4`I z(6gq0pli+2?tYB0*2q-c{}GKPUHv^vjUkrx^&H&YXYBvKDu_ZW4>84^)bDXDWoJq( z>t5cqZq-0y;LzUg{>dv55FB)jW%!*&oM82fc1|o^yL$E7H3>8ZXy}n`)9dI4k$Rk> zoAxE(K5P1yclW6Xri5t{|11%AVw1ox#i}6&NI^^LUO&*?w zVOdFbsXIKo5Z`9!4jt+R&`kHI^NhB8;9n#>W^P3Hc< z7)#v$!6`MpCM>$r#$xrP_=WSc_ui!$9M+_p&v(p&cQ`*jckOJ=~aGSUu>zNBsMe zR?eQa&3${N-B#D$nuxcxB^sLN*ETl9618n}I-BCn9ZqL^B+=ec+tJycsEx(i;_dB@ zEgS7<@5Bw!mZsLmct7q3m0grKc05XkB4K4@Kc|3G3@_nH+0D~)cEDCJ4SqOH!l{w0Z}tGfF8 z69egnip4u>qxDWC-qb2F>S`MslgzD+o7(3jBAs=0kfpt0pSaW7&>Ejc*;5k#hYcE< zYUjlL;t-&zc42E8+XPHPIU-RSyv#715dp(wnP}Uh){d4$b7x~?qP3-=xg*}@MC%&r zT5to+Rjy-)KL?CoI$eq(IC-;`yRH^iZjX0#u(gwsWcAu*-7{XnE!2kH z2Wm@4N|?5a#iMO;`Wf1tp61_K-`dvfv^T~V)RmPxXy*mB4IL>d+U6x9@Kz*N)J7W9 z{3YH|58kcyi|EKLZHdN)=DEqc7Bti~Bx+lYr$t+uo8wVdX)MlWGUeJkqtSH#Zo&zz zJ+Cv~8Bf%~W=>-(g!S*6NyEk++ORo7=eFIVwYIIHBW3cAmX<_QZSx{Eb*lTAwry`| zH!{Ixe39r<7*hr?bPpK$rW^TSS{t(adp2}Ck!by#ZQKMNT%JJV0_zeCttn4!X^*1wx4_u(jzqlKw>NyEXHA05 z?JQ_$j>Q)`#uCkuG#i-E5NoKN13zhQk2cOt%&Bcao7P6>#{YLiW%{sZEi3P>Z8SnB zT3Q(Z;5F)z?XmRE;K#8@Tf?0C4oo`QlOAii)j=#L+T78U<_BocSZjM*G+yR+3#ddN z@%=aDpsjRJ#0Z2)Cl;R%e@4O8{VP^>cP*3SqW8sMHS~X{Z9$w(z)>^V4h;=$b+w6j zG@2-nz`1KXIuJ1Mt!J$Mlut=vua{&ol=dCP_>+5~#_J z7p+GtsON3lecBcx7A0Ed$J^=}TNZ3vdt39IdXl#kj#kJaKN5lM-OBxSo zhr5|EAsO0?IsF(HYh~XlLnNn>U`ANkTrQ`_$DISa4?SdU-?C&yZ1j|Th{^0K-3NEC z8A$Z3S-v(se#}Q7watuHZs~;gE{w+GG4y%fg}F)Bvc7VdCe|{)E!tKKF(_h%-=|GP zL~oBZwY7FSs;R$wU|p}1NMJHPFavj5{z>B^P%Uy|WsIQIq^%v!k#d=OjD^X2Y-C|< zXly|g?d$HxoDMQHqgU5nuBe8<$RP)E zMH=QXLPpW)+nnCSvaW%yBxA+`1ZF#q#A;C~&0cQCsFbZ*Ydd33Lqo^>H2bxtx2ZQ_wmoeKP*-V>#uK%j7!H~{8ltrw4d{G+>l(jeJ(|%pw=~C{_D)O^C@sq%ILap? zWl6cs;6Yzb*tt&fl7e_$qBa`sY^#lG@NwEO7Dp2G?PZCM^lo1d(=Mom**Y4U;&97! z1?eDzWb43e#ms%2WoGr1U{A+BXI|wql6R*EcYo}$ z&SGz`L!WMGTa>87Y_1-SiIt7RSqElWl(Z?D&$Fwek_XN zf$a87j_{n}G8nYffg#*CHA<%jtZ1|)QIA2xu^nCW*NU`GXAOi_ght7cB^iBt`_}e$ z_YL%Pa}c*yjm8@rI~!};(EH{zv?FZLF>M#Kh1fgIxP}hzdt^C{;UG+<265vhm@y{W z>oF6>T!4Kq73HaZqC62<)PaUbpZzt(F(hjOy=}z}t(a?TPS8qk!Q8*Ty=`HE&P?wRm_J4< zoLHnWlC)vcXQO7+(U@a8x9>AB8-`@Kl9|t1tC|j+oc0WgYK-z2hn%GYeXEkyq{R`8 zhYfY;0*Hi8XLPPV6Np9YQjw7EnI0`E4MT6z8?X#da|3@iiAa<-NA#n!KW#-|HGxqh zQz{CjT(q$TBOy!;FRE>h#+`066q&UGsA?P$r;bGO;+L5H@8MQ zT2kYHjZxN$Y4c#yY}jU4hrxGs*ZO4pO;d+6Q{�Bz^1sABm=IOtg8Qn;&a6q=(WM*x)!0;@kw5;iO*uQnvI5hEH01`?qXoF_(%sjGxo{kIQjnVA z-%pvQ8)N&^hw^EhdCZT%@5;7u_==QB4Or-KC`H^gQxCfoJ-BPty3|BcV`>uyLX2aK z^`?pI;F0b1u+Tuy>h9DMF3qvg?k$~|>0(T4u4`y@z;bLbR%QjqzCy<+7^$- zG0(FL*R&pp=neZPr$d;-#A`dSkr1!Nl7uxSy(BdTC1axcq;0Z>#>V)ZT8wU~<$5E$ zz1_j`4l7U8lU%B*&9_+!`?LQ!wM|W^T}xFn;Vc`}L(Ig{R?4ty=C)XiwL#d{LA@A_ zFn~?f{sbqbs1&8mIu@dEQWnL$!AxiwEO8crkNA^-Iy(vQMTWCtmfwWSwq84$G}bQS zR)D0P)7)7SojKF|viRik67F7?&8V1KvTI-Ws_w4-?%hfztzO!@u4d`lzJc!blU7fe z0>Z$`b*q;Em#f4UG-^q^5mfoh+A{k1%2<$*ItaNgQS>n0fggyYdhdTKllBOJHlh ze;_savaJ^3NR(RDBYZ~@q#{`9+Brrt9{ct)0kflxGtQ=kt?g#@oEl9Sr`aPL=GYM$ zfufzxgh7RSXQsTrt<;W{ZS7pUC~#s}L#C!)Rz5SB_z?sV3fr`6QcEfhUCCjw2}4|@ zWnt1NmO-=;GbT)Lxi!K_R%RlZZN0YkTI>#(xWeg-8N-}N^BWxlhG6Gr7sYcV;CLTV+pw3gpjHqRD+dn6!&DICMv6U02e9w&Ua=ax49P~pR2ds7*h6eIL#>@HCr3Uri_q|AqJy)- zM3E&+@$hBB~6;aWk0slX`iNKbWJ%QrmyB zAv_ZM!X}1r$uAF^l3FvELkP+Z($sV@*~YaI^IXiBjMHCO4|e44F^-Zw#UC8GCDs=2 zz$n+(-P_%T*nmbiu`*RM+3U@CYr`-b#0U|M^sIGNaxQdmabac-)$K0X+$wI?3A;^ z(suFYhutLCo;2y5C9Gl6A2{l?L>T!b?k&%{iHBaezTp|h^*@AEfL@t|ehs_q0f zOO{|E$5jcncXSiu{86aDVcpFG(^hCgLX~eD+*ez3|j4r+KroWwwc=1 zVZ+vUM)<@tRg3RZgLhc%Y!%ky^Dy%a7OmXD{i)8n=B9}0hU*59dyr(rK3f}UN5A!# zYYyOCuL+rvzmnq!a$6VflSzj0THUG6egDb!wxD!;o25-rga~M zlzOb0{Vt=Ok)*&@EG|wMCfZSj?FQ-FPk6rE5XI<&*@wR$k}TDZO=9fcYt!8}f&X9v zx}@cA{eP9U6zg8H4nD5bgw%R~TeRuVsH`8+jQ&&oWUF#2ie_B^2TR+Qw#MjeW$)x> zJU6EO!9cU&wC8WhxEQUA`p+?~NdBrd;cwa^E-8_j&4ROg#0d%vp5tJj;pvRPU!$>VcWw>6QAB&;VQ~)#^!P;wLh_B#ao3dMK ztQ@pNq1^OWW)*B0554xYJuNj5uj*0h-Q}A zal6`Qm$g$&?u#d7HsdCq&!DqLvCH`%L#LTGlb_jjaXPWmOq)*)TDZZ5&{%R=|B-au z@%Jpu!w|D=X?-kRpSp%d?3kG@^dEh-y&a!G$NZHeds67+7@4$$+JsvejKLjk4Nc6c zh;mFyZhe%ec0tO^jgicfH+4Pr*r7c2+@XBWRDo%!!|8^>6n{d`*)=y;%4eo#6=o&T z%xt5y$EaKp+t7z5;h=3MBiw{f2A%XNmbDjMr>!&XffSZS($n^5GYwaV25++@OXHe) zr0=&;H2pEK;y;I#WZy6=4U?9kXk&ICYB39GWL^?Se1Ff@%sA5vV#6fWR(_|jA(OLO zjO*MspjVk4?xayGQVmp5Zq-_f?aDqIsH~wYQcYEnYO0D1Mo5e?-yO%?(cM-X^uO>R_dfsbLI@5)S3tB*B^Ih^Z&J27XPfRdp)Ew?1jwu07N()rApSJPykoFoNNEw&+yt*wx{#-x)vL^M06i7#y6 zGhJKCgg(qa$`Y}8*d43)pL`@UpXxC|O6{wr5^gG(aD(UQ-KmMF;RM$->j+xE4ITUE zf@#{rwbV0Sn{Q}hH2VkU-(be%AQ-{!)@k{a^6GShVVeL&xpYfvXNIcu6|GfU7a$?> zG#R9lwnfrX{Tx5(2+qR|4{jdV`>dtSEooDTrEAcvhMQwr)Rs@prYt2Hw$sImnCv`l zC8jx1V=b!p=dxuc%aUCs=`ChBtw?UJ(%e`|wPMw$skx>cc3a470byroplj)X-9@AC zoA`~sH|Rl5E%LKk79v&B^lHvr{DdFP?=ge=8I62<`r*x9wkBg&LjtOuRoIMxBpWkS z)YWpnk8~q0GK_5gR*!mfT0ggJEk9cw=dl_HnU0x~*n>Y){i_tUd&cQj97xtfM=;ps?HDq}jvm2DDxl7l?9oBQza+s}G66MKuZ{jEOkYA)|tv97Nh$voTxPMC?fy@fM&Gj~hhHcbm2(lxaOZf~S2?2UF$ zE!n~7TmJKGEk&%|VOW2v`7;jbKY>(+wKfFOikV$Je=i;#ObM$=gQU%RG!UB<*`!7N z>=VxYt&>B+HjJY7`9xYx>kG8f%;9Vi!J+r)=sm_7W{(iz7Q6+cs%- z#70MgeIU8@A2a)*CId0qWwHKlz#d2x`vpniP0$^@iKJPR<8M9;nn{}h6?19izhNIf zxhle_<7boitXbBbN}4FIz^H20S0?W_S!eoSkJh8mO~}zvMw`_)wQe*+CDFZr=JX* z^oQisEY+zvRA9%)-?pS=+B9dTxUE=YKc5wGHtRR1c^XWEbKZ)*n+4cXGeSZ7v?+3` zPda!^hvq{&rY7&n;mhpI&1qvA`!>!qXrq!HG8Kd{n76iKD=aCfRXbW6#c*E-UAV+a zj=;%s*l}ry@L`RuOew~OwMlhL7WMmbGY-_;QL^8*bO=lmDrFi(hvY@4Hu2#Rs zZNUmkV!f{HYg-=MJobU0FOgGbb9YEZLPg z7PWn=OXApDUA7FLcj&MmEi`Et_9KJ4{r4mceBlf}(ex8u_@L|I`9ty?eC9a$;^!u7 z^M@Xjb!_Hw8NUfQIgWumpnKlP%uQ?JZz?#{%wJEgxe zx4Aph;a88OUYUbhi2Cz;FjB9~LEgdZ__Cq2SEhrH?x(#n@!4*CDBf6|z7&Q%r=(q{ zF41kylOK=VleBYfk8rdcyv?sN>6tnr4cdSBKg@5_ zIiyvS+IUaD_djR7=~sX5A@;U80QB5keEk(|nu`ynGj8PKtDE?xGW@j|+LPzBGtX!1 zyqUNYz6n#v9>OoU%O`>lV+8M`XXTE;mroE;es|IN)c`EV?-pRW7!l-Rx? z&n`T|FVCLB^7MF?H*$in;Sc)%RF2m(hWYU_1Kk3L4sp1Uo}U5X!P?0Hk^1xcBw>{> zBAg?nzq8za!Y<)j;laWqgeMD66aG$kpYSE&KZTzNzY=~YF80^$C`Zs96nzi@-_XyJ*%Q-x;>FBD!OyheDFkl)=%{r@a{Sooyy1>xU??+CXF zKNEf<{7IONF9aapJYkV=2jN)ZZo)F*bm1&vT-Ye&_w$qQK0SF)*B0AJTY%oP?2M+tWpP8LoV z&KB-1yiRzp@JD+c6BzPeE<8kdt1tuK`M~Q334bX(LwJSo7U4s}mxNyk`PG2rQ!Jb+ ztQ9U29w0nSc#7~s;T^(i;xp( z^34DC`lQEZi)-S@?wTHQ~p?pM*PL;>vn<70wpU6D|?<3y&3^CH$T6HsN!^ zH-+B_JxsJ&&-TKJ!fIiYaDU-i;mN{tg*OQA6Fw_^NBE`C#X^(yZ6}-{oFU{F+3|X} zuuu3a;RV7!2=5U-Ddd;*^8QbS0nGJz9u|%h?j>v#E)%X39xpsc_Dy$VQ5*{EtOn8d$ zLg977dxcL6-x7W<%;Z-`;4h&x9Tph^%jW;Y1<7?T~bS0XA`e;acHF;pxK5 zgntq~E__G$rO?F!n*6pCP7uxzHVF3-9wMMI69%yt!1_vr<-#W6 zKEgiXF~W<5e-J((d_nk`@JHcxSo^b{3gKSD1;T#eM&Y?aem6evyHB`P_?>VB_5gT& zys%o>BulEZ#3eOeZDSTY`ci~4u z4|^Ggzi_f}FX6tzmBNj}(}mXx?-afx{8H$ah`(@xaE7o!xR3Ba;o-t_g;xsS7Jebj z8sqaHF5E>pU05$%Bs@TPyzmU+HNuC5&kH{k{vaGV)~|0D;VfZ`aIx@k;Yq@Wgf9u- z7k(=oKF;SmR#+*VFI*}-On8p)3gO+tzY1R$ej?3pWdI7Cs?-P580!C*jcD{CdU+D}+&Dhp=0CwD32=2ZgT)-xC(@?(>Zcj}Trj zd{6kDuwbHJzEoHvoGV-;TrE6Ic&hM1;f+H6IsyIs72#LH&>lX0ny^cFo$xW?tHKY3 zKL~f4IJYRT|@Lu6d!gqx~3g?vh^(+KpHwzyWz9@W8_>It;>DRZtaH6nU*d*LvxIuV=@M7T&!uy2J3f~caDRe9S`nD5J z5Y7;G2)l%b3eOT=CcIPlqVOHzcft`>em&!b)xsv>{=yBy6NDEFZxB8qd`0+~Ft1v6 z6IKYL!h~>@@L1s`!fS;O3f~fbEX=O)`HvNr3Kt4{gvSYgE4*5Gm+&Rw7Gd5jpYM*s zQsHdjJmC^yzwlV$S;F55ZxcQzd{g+1aQnUd`X&mig-yc!g&Tw?2rm}iAbdjjitsaG z#%$>$oG6S6JA}Q$BZR*b-X?rR_=<3=@H^p9t3QrSWD!fVfr0`W? zX2j>alW-4VOt@IMT6moBY~g0%?ZQWee-nNn{9afb_3PVNSR-r}CWO7hqlLc}UMIXu z_?&QykPpB)-sTB+7ETi)57%5z2oDjSC_GPiweTU~bHWdV-wX5NKEEA>r9xzInR*rq zj~3o5d_uTI_?0lb&cAQ0uv9olxKP+5+#ozzxJh`s@Im2g!jFYN35U+{>l-7i5F!`L z$iJ_!UwEwW65+MNEy8bv+4cVY6~bl0O~NOI*$sZVBH>tJvv5D*0mAjdQ-r@4{z>>x zVfNlW-!9?d!lQ*J2`>;{D%>o*R(P}U&%$SgFAHB6zAOApm^s(4-xC%HhYLpucNJC& zXA9>D+lAf21BC|(*9(soo-N!Yyj*y_@NVIw!WV__2tN~MH~R8#C!8j%6V4Yd7j6`u zB0Nv{2jLyUhlI}wKN5Z`%x?1QEfh`=&JgY`#AiW_e=ZO%74`~`6rLhHU-*0Bt-=R{ z&kElZ-q`H(zhC%_@D1Td!i*NbT#;}W;U2;Y;SAv{VNAHUuvIu;xSw!|aHVjKa6q_0 zxKVh5@C@OV!fS*#3U3qMBfMYusPHM_3&K~0ZwcQMekA-t_^t3Kq1)=)CnO9DcNCTh zrwOZt_&RRWzVn0$;cDSw!e0r`5nd_$qwqfAQ^MDT9|*q{=FIc!8!j9tEEn!2>=3RH z9x42laFg&l;hn;Vh0hD$5`HZFP8e*H9Kx}}QX#(E+}Nd4xJ0;Cc)0K+;n~8gg&zuk z5*D?C-_H2`B_hVn-Gvchi*T`Uz3@2UX++m?F4pB70f{e_1Je@z7cGl@BlbGgp1BSNm5gtv+Q7!l>3A{IH$8$^_Q zNBF+zpXvN7;g7XKy0vX%;RJ?kij-Tq#^l#C^vL&lg@Nd_?$n;tmhTZDHAvmDe1 z{|gEWgoVOgg?k962&W6N+%WfJnrm>8@E5{vVUMs^I3PSsc$Dx=BHH;};l;wsg;xu& z6Fwk(MEI2OIpG%J`@$cDChrmTcmcmYllO@8;W{5FG4pD&ld7W3wi%_LX)3}^9OZq@)L3XjL!LEg7l}ag(m+H=Yb5L z9uy7{779lQCkji25n-LMS=c7bru~Nc`M&gf-$L7npw>E=G% zKZ@tT64A#C4Il8^gXh39B5s~4H2H40?@y?J{5o*Va;Fecu88GEr0OyE&+3HYa<{!iuTOWW4F3^eSY>GC}fe(ZPTN4YG&%{WfySC12xvoFh!F*=>!_uy9o8u_7%CHego$K-GA+zWoT ztw2s5{{zRY*S=WpFAMBh>e|~NrPn*^BIK(T#XUcAPCekLHj+*NS=y=@_t;r0Dg&R+Tw<&L!{KQ~c zZNj)?nc$i|9JWoltj8SZP`HnpT= z&$1aaW|;DebB~HQ*7-kK2!@8|uF3j&KKn0xcU(VK?h4zCa(ZtG>|9jmj2$(1^u|$h zix-coFBunDJglyy?x%nK_>(hcTO3;#G*<$3drwK7GlutA zB&}S0ESA)jo4a|AG42RL_F=?-iK=xN?_sr#p+8Gmz z84EH3!F@u24EF;}i834VaXfQm8?R*KG+`vk$Z{`-(`EipjN_J(t9T_V=L7WPjG(*A zNJ7qIV^DdP%WsgwwQ4dNioly$T*#rwJr!@+7vL?kXe{2wqs>9RlGGdd#-q$jcE?*; z(PA9Cf5uz(6L`xR19@_?PQ+o>-24X2pMw10hZCHNz7+^|qxWYpqT`2mOED^E1rNtq z>IQc&!TrJ0Awo{@5-1!DzJb2t1*f2VZtx&*2n8=fnIXZ`&^PjeOAxK|gG~tC1;M|8 z!_Z(WN)8JizcUgngIgxzN0@`(4?*w><{%yp4}OG_+XcTHkMzCZ^^?)*f_dW*u7fW@ zs_lcXgT6!1LyedX5QhLM>y1JA&J|;2t|6?JIZ_j&}~$ zl;W3KgDsPgC>neQ$BzWJLWW0!Vf6FIg3DbjM1wy;wkLx3qEY@D45IcYyWqJI>Ommip*yyxmd3%Fd zYnE37>(0yaR-nE%6alnndCOqVjx4VdH*{us??SQpS>D~dIL?ABZxeVf%<_H%4_=hz z{SAiPC(C0p^1fN#0Ge&TEbmy>d%5cl?ww;q0U zN62gU9OurEcN-e+u8?;k-1d?J@AvScOAEX&&>WW)cuZ!yyuceh)^V;V@J>g`D+|1T z<~z>s3cO#Th7$|DAz*zH06k;q1aAObhE4EpffMzP@RmTogGP82kgRWn#|*yy5#FsR zIWWTe3bn5r;hl$OJa~jxg&GbS;oSs}T|dGb4=Wuy!dnI-Zy4dN#!~;V5#F_6efS9P zAJE~55gtEgbmRyx16Dd}g!dqdYy=TC96iFD3z24T@|L68+D%?Q8a1-XdlO+Pw#nNI z-V@*C^`dR-HhIHg!8x0}cj0cW_j^a++PwR{TflSiR__7yfUd1x9Mvw_>hWV#OSgJ2 zpoV2zy{F-I-CMoWp~Ld6-YJlJ#n#*%VV>S$0Vj9j1gOn}kI?9SJcxnP&x04yfCD@z zg&VHp!Dg88U>-aIE*mk^$-NGRkLJNXFv>4^a2P_?F+5-r&#^pUHve%vI0U|PJP%eu zhZA_M8L&x(Iwm6uE!Ua4y1nx4F2lF86Fdk&VJHkA8 zAMISogD2r@|c<=$*g7-P0t2mIX31q&A^C8dRZ8`4BI}r!?y#0I}yCj$^ z8|{@0C!1Z_CE>rmcOs5_xwl#|t=u14f-mlDmpKfBu! zJf~nJVvYMJOMrdfm<+<7Edd=24SVBEHxE&vaDOWN$C<`63O|SYyMLJ(S`OJL=A$#c z-B76D@d=UYO}!M+Vsx`lXpW+zN6A zKG9yV2djNqgg~BCz~!U+H%ow8W$172-z@=Z@k6Wb>y`%?L5OE&y3bLFQuKfKxtSx# zzi>}PGWYG7A&N&K{yEe8ghI3-WV#<%jtG)q@a{~v2!XgT2IqC(6NAeTR@{$fhRB)> zzMSdZjzR?!DD>B2kO`qrMg(xbv4%zC?1xC;erpNP;vCBIZ%cp{Otp8vvxJ~i;34+7 z-&+D&>t0mq{$L5&PQh;x3Edwp!F3A0WQ+e~2?#e(%NmBmls>Tq%)!)cXyZ}Q?( zyf{O`oyWGEnG$Yx<**!(iux#A#0po%=8vWcS6!Jm9>ogzi3E3+gd=wfH?`8M!o@H} zal&M0ge$9b7xJFB=>!!Lj$9~QOJ&{>yqJr7+<6kN0#Vj&O9{8Aa@Z9pRCG9n+t&(r zFnXiAUz%{8m3jA(*Vsw8ut36*JB4ei^j^kcn4&mgvNOUpRJvc`xNsRYoh#wUg)O$c z(pwIp3;xLNyE5e$1#eCQ;Q$c=@aNNb`zlMwakguUEO6X4B4lJa+qK0(=(QyRPQfTP z$3d3hTVqM3don64%p|*Ia<;?Rz4|Icl#@~&TIv0bQk64E9#-iGk0Du3!JFup?va(F zOf##Ksd@)fjawl2VtWn_;s$Ubbn%<=dyK{1@D4`dzvkQudVrUA_%8jLWWFph9y|joM{QZn8#JRzk>vY z$Fo>hiVNLT#OR%Q7#S*M(ZnXqo z%*~bVeH8O2IEZ_d#N>BRxVKe?r~t+MQ>8Z)Vc9p$pSLy5{o9)60b7MN&4ZTU*Li29 zyC>Kcen3aLTXh}} zea{l0$R9X8ecuwG$Wa`?w^{<^uHtm#155DbeznrQ5;qneOr2hn+(F*?VP%LKQSL7* zy?tQFg8gZ{uPp<}-9XRymnC4H!EXp~zp(@i*>6+KZ!G~GyAC|ve_H}nok;OMt5Tu!(-K1dQQv#-AT80qy<+o$@D3fD9M`KCN_*g3yJ(=G5|YX_iAn2dYBU znVJQwys7AS1xK*M=T@aAhA*M#yCF+}X3x_thFAhLdzp=!X9>{kVJ-*qEdiPx#~xi^ z3DAst$?i}~fM%a@xEp2((5#(}7`6mxc0328LQC*9%c^o0fpy{A^tJ3Nf9h}_8+UkB zh&ofVQB__(x<^5n#@o>{K%0H(g0Pb%K(kyLsKgSW89xr{j9=h&i z)j1tYaCc@^h|;jm*;U?d;9kIQ6mcV#0j$Yq({9ufV9mcx0wHb*Fy1rtlR6Rb^tj+n zMzeZLK#=0cR^7erE$GVQX}m^DfCLb;y2@>a1ckk1H%nq3Ojb=*Au2#IJF2{$ac{vD zoCD04X*hE}eF6vzEJsMSfo;6dmVjyAqgyPp))u-B?hUmHTiK!7 zqmDnnVOwd<^2&ZQsA-9b1VaBwwZo%t|dUTd)NTySpqck$oG6pfM$Oh z55fhO0L?CCi)^w4X!bZ={6b5BW_z)TF0uq@wuKhH*b<=Gm2~k-EWy|8^eXpd2wj-T zK6QpPdld?~msN$RGc~)a%KJ4eTW|wi_8Q9onyq2i{DUPxvu{g4xYiP&*-z{=*I5EI zyN_}HdP{(2FR*LgUQJkAB0h-OBb^d4x&}?_gakC}(nq67t-UOiw zuVoC|EX`)JwQsEoQDCWO%YC$WnAEJrx}jcmlfSOV@w7`vm& z9gZ6dGw9=YsfxpCr2DHvtejOmR^>%dsNfs=)f1|MVQdBcrp1lfk~b z;M%{%AV}qZstS=c8Dv*`SCPTL$RJql&xRyHMz#AS8H}UXXI1-?jy=&}u2&r*Ycd#G z?G1rnZ5L~3!>mON@VKSmLU#P&mH;dLl2vSH35a7*a!9pXj=KwwqI>77if`G^i>pJd zoK@^p?d^|31^f;ecZ?XYB|l>C9xnp8lj9E6?lI(eE`4~kI9^95+PON!y2x>lYHtEe zzFliW3=;q`;HKGg94AVxjBvlJ>8It@nsK1t9nE-AVF?hTrv!v4_7>=Q6bVx;0sU@x z5QJ%#fPtfcZZN|V&~37)@l4CqS7g^}w-GWHt|hzOrN|Zr=E~|2Riq-3YHuY975rid z=rM8BcGIkC_t#`#uFV#ME7%Bi)giJbgXU`QM>5!sj@6oC;J0U+mC?3mhb2JI8!5|t zOTYkmJP8Xd0pa0ZR<=k4#4EPX-qr3n1cJhO=mKt|q{`!@W*<0}q*_w#wW5&U;>*Oq zgDFjmA0UESeE({99XXy%CX2;!ce?3;)gjhJJ^QM?%gFI@j-LZ!!1ywpZLwa20Gb~% zuBmn(CP&UW-Cl9zC*R!-)gjhJjz?E}zb>&pbc`6#hm6Y{XB*SH%<-0BUFHN^r*)YV zEdhGQS@TJj0NdV*aP9ue5@6dC8H7%$_G2;RE;xsp{l=ESJnJWpA*b0A*2_+}1U5(5 zJ)+vZ30f5HMRrG37ypGPH`92(tqwhm6KBYccq7?t&j&Ha;CKk_^HPckdt6xU9R?-^ zRg9V!TRAZNok1_S#1dej{TWX#wFI=m^^B31SptSXj{)^^OMvq|!&|Pf1lV*mJaN9$0w`3gUInibbI$1F+fH|K?6dh`>Y5U%L+O<+>|H#Lnky)n4v6 z$Z;*FW^YuFdII-m1$J@@ZXw}KOV|-pg$xkhvV_r2K^F;cTLQ$!Uh^x}ZYkIm7E!HN ztIb|>VF@Pp?w0BhYo_iWR(o?<=Xo5)J{fGh_p9ArG8o`|f2)jl0z1NI)giJbgKw(6 zQ^?>Hdi8gf0ZoH#j%xQtGI$kl?$=`QPulQ@>JV9zfm`FnV7h_}NzbWC?HC+Dk%E>0 z&;D!=5IjqOXMai0&b0)1_MLR9kR`ygC$Zg!SOPqI18d2zQOAZOKfsnMumsWYqMwuy&U$Wrrnh@(E$2m3L=j3<|=?zv!*kun60*#gcGu*;J z&}8dG7~YRUv|0k#q0VTHI|8m!ctt+0#Z~955}dTvgeVQ4D(qY1b)rzg?R1F!Yj$`B zGBk>^}XK#QV*Pp@&mA;(-+e}*_-K&8*G39&9(|MD7d6WqAKV>i9h z+7`j{J+|5JECIoDEADWAZwaHYgGy(;$`W?KY`e7#YfNkG0uY)&_=6?DR%_W{*I5E= zwF?{U21|ggJT}-LEx~WFi)!5aAYNFt zOQ2?u-F?Cmpjij|*^`#wYj#JCdjW(lbP+V%yQJCe?5t1Mgs3xe1hd@hXL?6Mi7-D-d5e5ne$iISIJ~lu-Ee65 zBAgY4`9QNc%qNGV!h9B366UkFu|=hzxX1Wq$A|fBY}YU!J?$Rm!=OFFeAY5K%%>k^ zVLnT!C_0&SeeBmYHOzhbX<_bZ&j@q>w=&FmYjv2rm$Sm$9Go5IHd&--3T=B>m61CZ z<_1$;n42;6VQyUP9p)mxG0b&%bC_%A)}l*T)0_SsZDFo{JHlMC&JT0hxiHMN<33?7 z0QU=XjkbT7>#D^?Cu8t-tE){-OTt{DEGyz1#I5&f%fnoCtSq9j-Ti#p0b$PhSA{uG zUlaay3DUWWI6HCAtR72C|FY;-o}E=a_M#l*VHNGjW~Fy1w4(cX?VRed=i%BF zVa`NvD0+glKlt2lD&kkMxz|<~a{uw>FsFDA6m21oJNyz46@A1KcUGHLdnC*`+!ICf z=r51>C7uj(7WQ-zzckH#sk-n?aM}{)jOf#%6{P*6y6{xczAWa9#R(L1-jNX)*~e=? zRTu6GugVG(b22eIF!Bge3u}yxB7tHK)v-V^$HuxqF$c8zKru(5y#pgpWYLbA!Z~2j z7%1jAu{co7SiUS!%;32)P|Rp`Kw#tpHe~W>mRkb) zrOBgNVF~D$CXZ&NC3wzu_4olQx5pAN%`k~I2Ur43iQu|_#O*|dejd%@h##&^9?hyq z=w1j#srn<{L6pkm(X0~#Eri!b+_TBR$vm24EdgqoJeuPz0qZ-HM{}a(0she9u!y_EWC&sMXpV@a<aYn?O zjzWGO%~_TsdMy~78gZGd>*vv&E(Ru#=A1}~tjXXa%FMd{k6uCfFyM@$~g)s~QD z6gfZQ?hG0IJeo~v4wFZ7LnK5MsmSdSua=6KJeoVjK<#;R#9dAX2bZAwTgBjM%5rxk zMAjUn9**Swk_`ILgWN|WB~O5yg&R0ox@?gZwg9 zl=P{HHvt#J6v+vbok=ITFXC2%Je*n#=iMy3HIlawhrU)H4%X@)5$_0G^OIxVmsb3~ zJ@=DH0a;P2FC%%Ev5?8&`C3|;44!|bwE8hJ>`@f*GkBb+v@#hyfoMvre@F8EL0%?< z=X+^I?v(WNi1z~y!xYI0lbz9OOT-PALm_H0oOiQqUNmnqh`v?@(LrtHMZI=h^RsF~ zQNOM3LVt0GMGMG^T5T82ThBr!^`|)Mx0Ol#85vEsRY`Q%#VF*b{*1L+nbe4ECGUaEACD`(FQklG#NYsyW$&{bC2+5S6IkpPaX;OabEy1s|I_iGTI!(&YEY)dJej1`7 zO2azmMZJM3))MVvKuefhr%ub!D!xF3WM0ccTLSAVlk&635^P?}zLsE3v!5mSVm3wH z^B{qr^3x(QP0G(Nq9H0kF_%TX_bH|^&GKzc)3dE<4zyKR)2y-tzs|)`H*YHHG$}tz zRHsS#Sse{g8rC@w^-e`0-$@P@gQRKJTaMN=8$?K&<}h2rn&xmzu%ggbAcsb*fA+Tn=Aptj!F5s&=RmrHz_|C zSpsZjQhqMB1e@}6i6ua8lk#(^CHQim5q00B+$QDcEXi$BelClKs1fD9D(amz4RSY> zAb?zB8DJ%2Qhu(r1dPEZ<>xv}z!+>&ey+C!jKLd*gU5}Q0NocBfpC*0KzEZAbh9Nu zRg)BSizPr+lN5BDB|tNi6m+{K_?lfAb?=1Gep1k8X=ajw?udq{Gc~&}>b*$KF6VCF z{bG=tZ9?!pQTIDCFu6DPih;?!c`zCxYchBu>W!EV1~0f^@Z?|yk3`*ST=P?09uotT z;_`GfMAl^RQq)^W1_yB7{>oqm&qduM$RLg>q5Faum`svaqam^;gSVsJ6J%gAN#2ca zlS%RqYZSDF$s~Et63`YVljH+S@aLwlN8Qg@r^zIFQ+1k5l24)`O2az8j(YtwP^ZZx z`NlGULzqmGZ!G~!Ta!uhoh2YZnoN@KMM!3n{AdYif0Ie##54^@`9n7#}~6 zy5~XyKa=E3iD@!PGGiesKrwS;-rAWE(`1qiiTS4C+|gu`}&}zhRGzEUEzL|ONog!ZovGRMnD;Acb_~|`?o2UIpPdqOuO|bOu(78Yn1qe0 zSct62AQJN)CxdS8LB$3$m=#0L9T=Frh}mNBD(-XZVj;37gQl1_qzVkK#^Tj&8O)#| z=9c4{pMEe`3{3jLyjX~=$zUNIlMGDy!9Fp6%92b!*v}dTRx;@azpw<{4d3rT`?Cs@ zelTBEnDm4FVtfEXy-V0Fx$fNOrX!CEme*#-y4LS#*mj*NL7WMHxlHi|(q+u)a$;48Ty z<{nCpmtwKt9xje1+u+z(h;@Q)3~r zCWEtM-iu^lvJK81%;2{%JX-++lWlOO7?^B>^J5{hCWA|3-iR77Fxdu|4`y&-%&o>X zKilA9F)-N%SH?nQO$L96c^gp3e>#1=7$ma|ZnOkMAd_uylO_1k`u8#SVpd_Y4X#!d zCfnfVScsLgio0Uo6FBsrJ>Me+$!vo^i-5%lGz4-wKBrn_^Vj%QeD7C}zu+I@i21GGg74WXpsL9i`KKk=7TjtHP{br0d|(NPqbA|t zLrcIIViFEM79qnI^G)=BNZ=}(G+XniMw z8}LU{^nY@Eco?pIDURz$bA)q_IAd?n?H3f8Rge_w(*Yt7oRVr@Fejy1Kf1W>($8kRk*zBO_!MBeQc0 zLsG~Yqtq=7X(1oWBFD^--9?V-7KS0hfIdpy!Z2J2atnh$WS&Nj>K29!;izt57#Z@h zEOHzdvRf*(VeTUgVz)3%3dtU%HoGaBpv`WYE>oLbfhM4})GZ9tH36-qZef_I3DAVH z!(z=;+hM8B0XtN;FqG>Y+79>E1k?hzFpLSA>re~l7KX8*gj*OYLq4V$sZ_;DIFef! zQ1yn8{R9Zkj(W2c8QW2B5khQ7eV!0xN4+*=e!?Qvj{4kC!j5`t$j1~TmBsDBS9a7< zK*@tQdF2$fT zWFAEZY9qT#7^scxRUsc)lR;m|P78v8+Q>daGeDH1HnP`i0s>LBk-b3^U}I_{`$$bd z45&7;kJ1G6U$v2av?jo2)JFEPx~*UlY9sp(n&3@#!@9jg9G%8YGfpCvhB8`* zJz1nW5W<)jgnX2jQe7Uhzo%4cBm2q(j%p+OD$UWY+UMesIlLMi)kgNE!clExUla1N zEONX#WY-{*vypwPW`KICjqKY({Wh|%51FgTQEg=3C>+&B_8lP~%Ob~nLiU5?s5Y|i z(=tLYY9sqWO~9a_HnJbmWuh~xjqFD?0qkI=TSDf0EK_Y{-z8=4mjk^#7V=RVmib)B zo)bcue5r`}f-s<02|~H%i<$r-dMASLvMvHn2zv`6wQR_-Dwz3z>$r&TGfbo|+@d9K{{2cj9FZX{pAIi|+~{$>PY= zid$Fum-&y7`3B2;fC9cQWqP=_`eDdNX}CD}dC1NVqvC1@|Eti5?I6c@@W0jsbPctG z|D7h#1$fMzA+sD;J3IKFh7xx0{}b}Da2D}v$i9t5s2zM)c)$*Rk|yXKe2*sR9egVs zmrCv6Cu;(vQakvzCOA_47&3QIDz$_Eb0}d4-xu~#UMf2yYzJ!~mD<7249l@JNTnC!BTdZ9yV8?KxYTvA9lt|wSzw< z?4!JtYC_mPpHitE{7IStq*6QhlQkh-am)>y50InU!5=Ri)eipDu#aUK*{fXUK~;9) zTrB)@1I)$Q46c?B z&EV?t$PBI<=VWl5RyB5U5Ycfc2b(b1(5O#E=lZ{!5ROY49`gV2ZW}L}3@jFi1vJ3`~D>4|H9h$*-YE?!T{;$bk+|uoA9|uFSJ*+m1 zt3$b`CC9dhL!sPCG}u|r)^RwLdmzrP&EU|#&Dk<;4+T09<9#%gV>7mFIl^MgR&5=x z2?aQ+Vat}oCbn$V7V;lMddrrB61HqP3Si5Yt{Ypn^tafuRXfX1gjBO(%a$Io#Wj>Z zDdHNYHkv;U1x|vbZLXp88raWe&&GZ(yAt+uX}gEIjMQ{Uz&hwHTNa@K&LQNnRfW1MlhNeW5$T3!*4gs(wlO z)x4k+PQdW~WxV2j3zDtt+$SJmuEL(4Td4`c~vMMm>wn)-CG9GpZy5 zC%38-@2FqU;jP=$Nvh$lf_kjm-M53mXpi-feMAG^F?H+^5FgK_I$TMfq%jMJ+9WP?iq{oS4Xiuklj7z zLR8v%Z4{do`Q64?kM)3g5lYV83H@2G`+f$eT>d7h_0J4dpONSnSO1qd$()7;v}{+#&?e;0youQ| zT^U6<^JLz`v~jMC`8e}to(My=@?05*;Vd=tD)6;Roil&t`D~w%E8`@jWo8Dcw-zUD zXy(iN;_Lud#?43@nfXQ@&Xzc7ImSMG6L7fyTYXZCVga^SAjEZ$0im&p3c#tMiZs$U(4k?H0lq+H>*Wm~$ zv~-Kqah}uh-`53gTAeQU5=wd}C=++UL!?^ET>hVMmdPKSwN|)BvOY%UJ5<|B*GN{$ zlUdDHJk&Lk8NFcmFwn zQ&x7v;ds1@(s<3JQCBhL0Ch5X zRDc2;IJN`=>^th76r3ESP6{$^LOo^}?jNYDs-c^3HqP@W{GWOa{!LK-DBJ}8LlTuU z*5f_cd;!V(uIz@8(INbWh1^+i!rqQ-{t5%~@y8WXx8m@9Zu}Y|lKrAdmWRU7pL_ zXeaf_AD=_oEDDK;#@Gkn0ytJ5(y)HxPsnm||13s90TM1j!W9D(iji zW<9j-%1gNpsr+oh*L4{iz^Pi^#I2yTL)>P3ovP&(vuc}g{zuYO)$;0DwFhy2H@>rS z^T4J+8T=PG--)kkKvwtQ*59pek~haFU|X`jNA%BQ6o8+x6$yVHn85nJh=kjm1ZocE z0v*C~i~=Y@Y2)dEmmPovYUAC33Coc11`>WqOh`Hcyw(V>08(Sk#gy6jYSlXSN~%#@ zgpST{%8ORc^BzzP{iAC%_Eq4N8DX}(lnF>?8{`{f#pTwdoQ3YC!t zX3Q2yyc#Y)@s#OV%!n0;#LMG_WJ44)F3M2F6_pv*j|~XJ2SIO$+v7UJAQFILR862l z)?}1ir8LUIM@vm59g%BX<8dK!L^gF}~sGxh4*C)I7md z6`mLqPSiZ9Uo#33HzzBts-oet6D45^z15(OhrgA2D{F$8divc zr#soy83mbJPdM!k`uc zoD#;rZ(S`{=)~Vg^aflqk3b*hGTI39@#WR?uHex@P68pS4qFI|@pba>Xc@k^m~fan zY$0eV=KYQoL!4{`s1&oo9%BrUW8Qxg937v+5;*3%jCO*);`a(cCsi3E1m~JILQqj# z2>SBK@5q?pWFutan`HE=cYt&7`foC_E|8Icxd1Nd?sv)W3F%ZTLO4oY-A2%b43w)J zX|*a_%UnQ%b9e|~iF1hm>H}|&;`#BY|NKX${IJseuz?ak|5JK0oQ&JJ&JC`vpVILf zQ0MjF7;;^CdHFpZ`OA8{^Lu+b^LwKF`HCeSy(>G_`O==1M|AZV`7740?#l02)wLl% z4?hLbu`0iJMMqCpeoxn$uHKH`{H~&CZ{ND5E7#`ttzEmSb4AC>HNE-EJ3FHtJ*)Ez z3!>AbMFmBL(ZT`}r-3+a&Du3x)4DpAtejR@kT-oAlk zACvfhEJp8q zgqlLFm96=8j@JM03j?pNEC1hZk4Esn%Lr~O)~oD>W5(T`YuEJktXB*7Tt=yLMmH)6Va)+ADTx|T;fIy<}Y11&2shen9xGECL| z-FYt43}l)vYmhm5oaq{6nv=}YBTUmOFvnX+v+^CxHOG&}S+13nV-+?untmo8X!>!1 zHO{^7LU0J=m}!=KQI3^k?O$)2?pzm%q^-!a@~pzf1`r1+VqOy7FN`BC#m@%CK=#4r z=&`124F8+^ID+IV;l__M&2i><7B{xPMEf^2HX;iym{yLRmqfOg>InLGEyCFYHq`It)WO; zsM=VuUb)!LRb3rDFusmH_<D%xwwPMBAHM+gnR<;@Q ztJ+&bO-6e-(%97Ah?3eut!<6X)qERqQ>1!PYg;Rhsw1I!p%}-e=4fksRckO(R~3qY zQF~LhQCk)fl?F71l;35!RORdZ3@yhR}jACfyDe8fd5mm348u zs*B8vR>AnN^;lWefD5#ZgxYGsw54_t?Xo!%ZK!Lik0mas3)e*}Ta*n2o12rm93+ZK;gZwZ)Z7`){ml zS|p7cXRlhZwYgQvRE?gXM2eufs-of60@!N{I!7eh2H$5uiP~TGt~{#Cs0!BB3@`|o zU?F;26c~=i_%+WDHa0iK>J+SO0#7tRV_lmnI1;LaCA8MnG#SBQOWYirTZ7Towr1!# z1k-JDRIMVCDBILnP}fu)T4*RGG*zKlbu*~$U0qjM17m1v4K~zAYbxuSjMmB^e$P0T z$+5V~2335txdnYur)h(#iqzHAwqY!7jhU6s5(Zl%*wogT(1d7;>Xz0>FjU~!E<~aR z9h<8T&4;ytw7Pfsimr~OM%$tmbggPs4t>#xEC?kksje;(u8f9)!DwL>EU&VyEm&*d zr9Cax#)5`WQ%zfKOjzA@=$h!y#E4^!)vEvB=rOJL60iAkliI@9M*N@`n5evV+FAte@DKC`sQ|+&%$6RRE_?|pctcc$I_lc zI)&!>kzk|}rLdujoc^Tz4tiR3W2B|sh(-|?_7x+uZu*$I;1?Dd)dh4-lr7TQ7>a8c zadThCnohc&o~~ZRDk!1}9j3A^62i~^qKgE>HAZzyduybKF3$Nuw{8S63}hhV;p@73 zJ&{mDNDWuIZer-I!BDia9iFzStu9#ERtMMOG@i1G)^-e- z6o54N8EN9Gf*5<{hiQ3HJ^sg%#2<#EmBCNrf^{d?+$MR9#pcdV9EYt4~G z(Qrd$Ypu~8MM!RNP)2OQQMfS}<0VpJIKr6O9`BviMb$EdVJcA_if}+hUkO$gh(*A3 zz>yYAJ(u(k4yao_ay2x!w#D?PwB#_VZ4|`l8dlnwUmb)CCcBxj@sQyiyKi$C3}JNf zF)i-ngTdx#E&Q~h`>6zPMKH;Mnn7!!DlumsbBEnMYrDI8`c`)JqPxa^_HljB%D%3s z`ejJXC>UyJXm6;Dplj9CwZaq7{&Z*2nb`Hzc!Eyu7-At6WWd=pp*dou_H4i)%FYw_ zz|=&vFj}>!4ULf)AT@?Cph@UBu)Mk!M42*}w$Ne_1J|}j7KWM{o0XPf{nYDh)#nl% zP4~*~u7a4WiP@U5ZcSpCrRme@29!0_>~yxVX5H%O5-cnn)*B<1I5NOu zsv4?dO%gNXpc)`#c%Ya?jx|AfA!TGL0@S)yy*Cy<^z%~m*cdWmB_#L@j9PVJbO<;# zqdizJBXTetcWSiRM8`)#=vZTog=u8M7~lkC@Hh!!mg9S!$PYeJxjGqO;@&52w++o0 zub@$wQDsvwWb|S-s{Si@=N9Q*;v|$#J&>Pw+BW+GR(u#iD;7mnkIERq7L=aLdT`7M7 z>sN}5UF#TFBoquGlF~D@gpLDu3|+^<6T}&z$~H`kLzRfgSyIdf;-g8-p-ETLhE&(k z5UQ!fI2E66Ho#I_4a{yZ#X>o;IhnNYfH|KtC$Fh&Y((iYCsQF^K|f1hxn|kgSOpml zsOS+>kqCrs>DL3H`97?-^+p-?p-|*j^EZgXC@P4tUWJTwH#n<;J;bLnY6|0s48uem z-H7B^Wn~4Sp>h%DydrH)Q+rOZqy#_Gm^VGIFoz491;s@(awg%Ya=SWuyC&yMTiw~c zuA*~o4}LCq+Un`kLFiktZuJu2vQ=w4`lex3v;s5Lr6eHdvhE{hPV4QSwzO~-C>=eW zD=M%|dPMQG)p@J2&^mQ#Z}-$?-8s{i=S*uZ%9(~Zu%Z(JOk1`ZD@q;9yQZz`TC==w zMMVKfj)$Jc4ve#9>(+Gktz5fi8h$XC*b5p5uGqO=tx!>5=c*p%*uYMi+YBf0)#^}T zkQ0Te@klKlG&Q$ljCF#&el6I!Y`M`6D~xFqixM(P;EXFqjzxl))Kym1HPjst58hB% zEMGkKpg)e0!?$C$F_(L8jGFb zr*UCRtBP0RV+7{K2c+mQQO8= z!u=tIzwaZe;UFaj2iS$aEbG#Wi6^u$-C=q6<@FJE`R&;bMB&$Mn z9PF)ySia)=RxCT`gKEz1!~^hhEMSpZtV(di${=S*fFuimbQ@|e7Himku0p~O?M@MJ z38m5KUAwGrJ+?nu`_^`I9R+Pyz-nVA2P5t;9D6|xJfCW`*rFYEKhv=oC$I>{)~%qq z);5%e;7duTnn{JW^Q#-VOd$RpSrQfD=#8_SxGP+>cFppfSX9Pe1jX`pU(c$zgz>95 z5Yt1eVCT2$ML698)6rvXCCt7t9_4Ul2g9J_51chkgHa+1)B1s|&Ki_68n+;{Lf{2= zALl}+4lcc2%hj)hYatM)Vub-KUkz%I)S+r@z)}lwGHR(_{J+~R_?<0+D%F`WQeh>J z@)pA7w6({bLhS-92xB$KS-eq8k@42nT@1nfZ;5(waw#U~zY{6->$_YSkVU&fj#Tm1 ziWz%#Wx`}k&n*}a#C=RdVQ3+jnP8p`I-W>e>~liC_NL1Da1~r6Q=L(*V}~#e2vr#& zMADH+%&y~NsK^_WcB~7lUjKV75zDPc1x}fpo9KO&PbvH#Q;U=&jxDhzBC@6$DJWDa zD$rL)Gn^ij7y|3{lUNC@Ep_Y>T-d}CN>df1OFG^*qczeJ#A+>P{stCVTb&+Q>&$i0 z{QaxtSeCQMgKor7TN@}Hd`l#(tWz&I!nuGixGe8h%l&GFM$HMiVj05XPKR2piE=QF zIUo#*=m3sKi7P1~_-lzY*VbWa5BAZ7l`$-0I8#9sBvJN1XqweE2omCcG(LM+5N*c>4y44WrkVrc&eD~=%3Nd?22(}2z(NoLaJ-O= zjp&8zdV8FO76$zkodX;KOUGVgveO`1Io8K)B5~c6y)xQKE0@5a-_kH_)3)|-Q)89tD(m{NtsG;-epOl3ioWH{ zhG4|vX}QLPys?~W$&7n{tqbbVadlzXD^L@p-W8Z*|TVuOWhOEvwDl~>uyO-#BSN5k>Xqh$rd_6BF^PKB0iH?{JvxS`4kU5L&} z2leQr)!e2~4i@@>r+};!C$gX&O&@C;N6EFAV>?6$37sxMAlYQe^1 zT@WJ!hI41FAeO5Y%cEF(mW5=kQ)lHJ(kI-5@_*_Ekm{}_>tM9n{9;anYm|w*CfYEl zIA<3(K5`(eg9$Bw#Uw1qYGt&yu#0iknM<-x6slMAf3Mtd(AoRaB000VsIzb-!xL12 zjUz0>b1cfWBnF^YpizQgv!zS)u7V3VtKT4T@NEn z6u|8kEhsyLUg^+tAex|Bu}ScA@f}?3=f`$%8w#63HO&Z`;8_xSS;Aht?i^etR-16_ z*YREedyBi6)_F=ZSntNvLGRKVt!kSgKGwvxlF_5k33Nq%vty=LR-`Fd0Z!uPS68FZ zc>hofow6w7EMwGSM^-IkP!C0FBB2XO7{mI7{j7$XF;NPms!^7~oUKQ2;ZPKlG_g~u zYH@>Bq*PnaP7j6Cq0Vr%nsdSj(yzw2s4)v059o_Q%;zJ0qaVtscU2`&Nx(U)5O;T3Y{2N%?;z}@ip|q_#%4Y%y@=b z@x$3l${(C_WjV98b zuqT75h18jh)RZP6@{8{&JFOM`ooOw{jaZLRLBHC$7w4kp<&}sW8hC$7+)c2t*K{0a zUIWm`e7oNrJG@ngd!e*NwIm$Vd{Mj=iwfh^qWEFF z8H?i0SQKx@qFM1)QcK5`+`dEOydMkaz69jYuteSY0*mE>P>E@QHNC*a0_ihg|onuD&j%X*ID?hQcY0 z=$h>;ckRH;IiXdNlHPYFO}dhfwVn6~YaViEL)@n(c13k(jN=6`7R8u|A8T)_Z)#r9 zFF{s6RWJ38%r>`f-zwik$XPzLJ~Y-zg-LL@2yF+cXbCz%y}o=_z+@Kq1K#I zIm~%mN2A(chzTO4@UDk2Je&?;LJRA-hgpk2C%$SJzm=niw{qZSfUbCisJtcmwu;uN zx(K@G?|IFH&7t^arM^!rZfuDa!FC1e!P!nsZZ)VR&h)fqB>{!wMmn`otm}+>S!!#X zn^e%Kod0v~t*_Gts4h`g8%nb}Js#j_O3bGwiczKRuaaf4gvM;BL~%|)S)guoqZP+m zO^s|t&RQU9O3h)4(t=r%1jGmcbg@WxM#9!whWa!;OALMZ)AonI;B+n54nRYQ1V! z+gjJ&f(VGsL2(PzJd{Uj5jY;jC?@fH1NGF^8AXa>taYs%6_O8^6;W*-ss(u+0MOB^ z@Nr3ksPRQ<+(4&q_tKhS%c}{BGeyV!M9^xiWF=trJhhgdc*{pDV#Ok84>nMpn+Vn5 znRq{qj3NC77Os?VU|}qx7HE39aQpJImCM)lbj8YLe5-<^#DzO8GR0;0(2G4Wi)X7l z`=Ju9%XrKv)``x3$5fnMExGGdX2A*B)bi2-tgCVDt6A;=j8#7&E?^fxbEvxxWA$+E zOW^8^Hb3Y)f)PhAekYVf8|CtvcFcN-O;@|Bp|YtSOT-~;)rc+YBx*!w#}pXr6V+Z zy?r`(U@WqF$@*94s>WB-e=T^8#Lr*C0(WX^hu50^g=ZWBLmGAzM&mD z(-oiZ++8Sl-axU=j)SqF9-T49HZ&iDkh34+?05d=RzdD9)JAwyp5wTj`zSR7x?-$a zI4ftGsJaPe&IM8SmFik&n>%)kr_LthBDWwI={c>YHVzrFF{Z;x#R9DVsQYRTxO+?IRxw9Y z!UTeLH&C%H(b)ZNY*M{(6X)UB(Sqhkz04PtNz)TxNuC@rPKfo!M|UiU=xr!RHq9@L z`$suT(|6%3C90bLgAZ95u6!Jt#nT$|uq@JK zSc8)rZFh<{!;|UCa%H=Rx`w%iyGFQ1x<)7Ey7KU>%)n0~$zy!IH!Ww6~VGYP{sr=Qk{Coy7{&C|Wn*RK~D*vij z7CvMX|F{i2-<4>(^m;C#)1^J52`qbtQeEboQ^ z=l2abmxr z5p__TPzIwQIgKyJ#pL=QM_MlCBvg|PqHlOt{Urqtisz#3Q}FaIUQ%GB;QcH!h$Hcm z4=0ZoxLUAR@JPYq1Wyt?UGQwd3k5G1yhiXQ!8-)`>JygF*Psv|6MRPS zCBat&-w=FP@MFPUf?o^%NAMRxPm;smCzv5POfW}qq9A_^g!0T3EEfz4&J~;|xKJ=E zxJ+=hV4vX8f`1e|Rq!mq3kCloc%9&_f`1i!K=3iaX9fQz_z%Ii1wRtpCHRft4}uuP zReh5M(*?5xM+%M;oFZ5#SS+}|U|6tGuubql!6kw#1-k{;3;sdyB*8NT&lS8x@G3$6 z{21Ho4#9f_9~OL4@CCsgf^P`EC%9AaOF_Pcj(mR>bbFlh6v4rQLj}hOP7s_XI76^Z zuu8B_utjiz;30xtf~y331&+oMDxL)uc!6e&BKV0ySg69feD|oly(}J%F zek;f+4(q|!Q4?nfRthc>JXG*#!7~Ie7rbBaX~A~{e-upiIsC^676?`fMg%(r`vgxC zyg={7G z;01zr2!1GNVB$_a4;IW7Y!^IS@DG9)2;LxgpWt(X9}9jXn1UFP{6`2@2sR0J3!Wi( zvEXLG#|2*z{78_KL-I`%+(&Sh;6lNbf~O1KAb6MHi-K2_7nVwBQ+nmkZu5_^9AE!S@Bf5p?r4b|^1XkiYB1^9sRs!DWK$ z1vd#^EO@ivgMu##zAgBrU<%$gMgG}>`GRu<`8F!1FA?k&JW=p`!RrO@6?|6kBf+l) zZA=i!Z@A!8LB3>-^hUu$1lI~~6g*q-YQaYYUl9CI@H;^hb7k@!A~;d7Sg=m;0Kvlq zj}g2`@H)YV1z#3?SMVo6FXsF#FGsLYuu<>;!5+aA1g{XhRq#nc{`4C8eJ%K_;1Dbb zkX|IXzu*GFUcrrm7YW`a_?X~lf|0uX{{zhv0{T z-wB#ni(tMXf<=P+3oa1s72GIzk>CS@F9^OR_=O;UCsy$n%oE&S@Ib*8f*S?T7Q9W6 zZ?7bu4+XyyG;@T%;6%YEDM(`rR>jXa#{8rF2*5RKeI6-i>V6EUH!9xX4 z7Ccw*7Qtr(UlsgZ@E5^hxlVZ#1osnc7F;ZNjNqw)PYd#G_0-cRfSOLf?NnA-@$^pg3|??1^F}T%-1J)lHdh`HwfM*_?+O! zg5L=NW}oU#6Y5`0RKKVL=qPQkzw z=R72Mtl%AjI|Y9dE*IP& zc&gwfg0~1hB>0lxJAz*c`tqIfh6)x4HV7^fJY4Wh!Ak_U2tF$Kn&8KRzY5kAIOTK- zb_;G2JYVoO!3PCj6&zLQTwfv>7Cc1oFu@Z9&lbE{@LNGok;5lTuvT!X;NgO&3SJ_3 zi{L|ouM2)G_={lrbccU|V5MNE;BkUy2wp3Ax8T!)uL*uD$c+m2i=l#(1?vS568wYU zC4x5yJ}S6P@O{B=1k-0a{6`2*7pxX+7hEQ|UT~A(#ez2rJ}vl);4Z|!Lf?o<+vz>Bs1@i@K1Um)01vd#^EO@ivgMzOKekAy_ zU|O-%M=)P-j^I4OC4zqtJYDb_!Mg;X68wkYPQg8bc8OEoaKWj9<${fZhX@`ec#7Z^ zf_Dl&Cb&cJL&5I^%~GelA%YVHiv`;RI|PpuJYVo?!3PBYA^4%-PlDNHPC4TR%LN++ z4-q^{@D#x-1n(4lQSc4HuLaY}MQ?&df4&Tv&`GRu<=Ls$m>=isw@O;7R1@9GnMeserJ%Ypc zcgmY8ST5Koc!=Opf~N>xA$X_Yi-KIE+-!X#w3RVj)7F;cOlHdh`HwfM* z_?+NB1$PPlEI2gil(&yyg2;L$1kl=HI{}B98@M}SAuPpB8*Y z@C(5o1g%D=+<@Rj!D7L=f_Owl+2;bmPQh-$KM0;7c!}VRg7*kMDY!%MJ;BXQ4*w?v zw+p^2_=R9nvy(4VaH8Ne!FhrQ3$7JBUhqu8O9XEayi4#g!IuT!6#PW+d%>g@M~)GK zlLTi9RtYu>9wfL@@L0h|1wRn{RWN0q!+(fiuHa;%4?i;@=Ru<1Flq!FguXz|4-{NX z#C1mso+EgR;FE$c34S2>0}=k6HzwgHl#M||oDV0W+|h#Lgq|noMS`=1UM1&v#i6>c zo(O(x1WysXQt*DkZA6s!CebvE&*c1jBFg_k@K>SRtqwg+FoTHeN6GnE!3jbyl=GQ_ zr9_l-h~Rp`vjlG!d`9p+!5;-P+nnpC5>alx;B3J%!JuG`V6z~eg;3WWC>Rx7A-GC# zo#2sze-u1f@Xvzh3SKIBh2RZ>w+P-Pc%R^7f=>y)B)DDhpMviQdSD{7FEpvbL4pB6 zOm`F=;j}`8CkinvDuf$Q2y;_-pkP#Rnc$&BM>zY6k~yvTo~;5fmFg1pz7=|zGig6cjt(AE8Fu){^9 z0~ZS}6jWeVQqcJi0v0_yE- zBKWBEEa4A61P)A0w~#$kljRCa|x^!4>)l@8#<=^3>aU@|N`W8hLni zUml5hvHMix_XhvBMCaz(|CY*oYE{}&zWc#>m@v;d?pU&*-jHOqG$wypF!Uo|Q}1^?~jG{xbqu(d_D; zR9;10Cw^c8>N6JqnGa2;J_GYHjh~75vi<-6^093Pmb(cw{h=-KvoF3jzH{*9=erBg ze}KdBWgdQ69(_(CKl*?ceDz23Lx|gtU)zNaZ}Ov^Ykr5}IFVl}PWnL8AI)z$2#NBY z2Y$7nkssyK{7%6!`RUI_ocxOhEgzkB0?rfpy#;<(PH_08AWic-7svVc`xwW(M%Qsv2ln~(iKH=o_kese&c?4xgQh>s!|yMG zn!XYFe$VcIK!!y5zS|nFZ#L4je0)X&&EBo~dCzg~N7v^plOJM2vm4dO_Z|rB|MchN z=f{_2CYX^i{(Qsun`VMEeMp`6%l8=CRwpLplUMXPzd@C^HotIo!K~tfqT-^$96Wzj zkobSrtQk2uCDUgY0PtCya$Kk(?EJ_T7%HBVV&(IE#UZLd)A2=>Z8~$$BqMXmh}Yl!Bx!f=>gB@|KZ|_B8zvcD z^#>kmOf`0&xzWf?x^ZyWb=E~Su8UX}c}M5EroXx6>Yv;hJG@D|{+M*lt}6G5ptG#O zyOYgD+ZWW2*yO_XXKkF1qrmRPgWS6pCmFlX*w|XzI=8JZW0QNMZ&TIA6E;TX&aKbb z^yZIHc6zuVY{osGp!Vw zGI!^W^rs9_rBcFU!1IU%zI_SDYZ8uEBpfeEI6g?#<9VSRwsUa(;JTz6hi^<#Ey@z= zcP8f~-K6VQy_0st&r2`9$T0JN{1o3ksQ#(bJ>lSf5aWj0v#V>dFztc7*g52Lh?IySBaIx+02 zcdm8UUW5J+yB-<#=6dSgU+1{S?Mcc%y=wT0KW^`?`IXN=)?d0}=#j8+e(ny`U%cY% zJ;r-y?@8L4zRQ*L+=hnFT>Jhjl(}QfkAM2MdAE^1Z-ZyDXZzV3j<51Qdd?pAdxJOl zsxRHr8A_@C`jzf5`yF#RM`Ste)7_QhQO4UF&fSyr-pCECLo$1{F*&6v0+ zYwNXJMs1iql<=c8;I@o^tb(B-D+h;)7p1eWSak z_-;=)OSPPPQu6D;(MeNtVWsZfsd${H_~E^iGPh4b3qSlx@tiES`J?*G)9=jecc!c( zmeZ}$;D1zk-6$^|CAz|XRqB**p;%DTq`)@&^|4{cdWa8y(mjV|?w#ZpDY`|9-^=Al z);-55-FWn|(;wTMR`0*Nb%A9o8y0&wezcT{*JS~ zIa+7-=AHOcQW1sjmscPG&=J+Q*_24`i=N8UwoO?6Q+EbA8*r6xj{}Z34RIjdhcAj z_K8o;+$TOw#@EKz7z}QMUtcn;BbLu8)+oN)3}f6dQXPv4yLaz)kK5?9m^s&~AH3<( z73SQlHZI;c;>e6mA8yP&zW8CeRDnGu{q^Fz(^TtcDjqKMWV6nICa4csTui6DVD5^7 zyLNnP%zJgk_RVLlNUw)%ZII2MwKBCKwKlCT<5<)e6wBpn@YSWF9^Oh{oz&D-@KATn z*(0{ro-VSx(y5ug`%k?LK90c%E3XF=^U;XjVJAL=bp30 zbq+0J9Bj#TiKBI-6_kWs7{yanw2*e^?uTFbG-;pbHz$vs2TsP+H^K9OZe!Z(+g{&k zoy_;t_GflZ4gV{qtE1OAu@?Tjb`QZbfVUN5J#G|&z=Yr_ z$z`3CgSg~i(2}MO#da@#^V9n};_##-^Hc0Hx_4u`oK!Ll3uPcBuSVu1j~N_~ls^~X zxOvzrrg)OCp9t`pFU=+-pNdGy<1zU*Nu+&JhV0%<{2LnJG|T)m{#lpepPNr0xyNUQ zN#zW}+RT4Ea`S;mcR}W29GhG5&*E^G{K_=`3^W5-4?1Bo<~}zt%J+8VBV_dM&kank ze+;hl)}S^X@AXJDy}W_l^45T!?7a|@dcEtg%wT&D%)!GN-ilI$?%v~PLP=gf=00iO z-H1@rz5fLJLEa}UbXf0#421vQd#57M_nwY0Kj00{!a{=gxl}w(>E#XCL%h5_DcgJ7 zBm}zNPZ8@5^WK7*5BL5A9ggsRG#v{&-dyk;?fnjU#&{VH=XggTI3DZeEqS@#$G~Bn z_cp}Hk3@MFxa=<>;Ds(b6-{-K%RUoDUhJ~JhYl`r+3TV9OI`M4X!bjo zy$7tnciG24d;bQ&;Qr&Xo4s84vA3gA3zO`3aNR>m_J^1beB!p3V$tPOw>=2e`^;_6 z9&H%A+;&@@VSMhkPbxBuFWmO^Xz(xHb~iNkmD|pT5WC&>gQ(HhZu?azu)$*wfweVy z>`%~iO&jdnHOHSO$uF)=dj(_x73n|3d3 zR5;6>JD+g-?cM7BKz8eE@k^8t|!*>*W;rML(aiq<;%x;4T zS6*hHjlNuUnaz96t1q*sKog~Y8$zRbQEIcqMncR|-JPuQnIvUyL~=RgySKeL}l zu^pe;eW?4A&+H$dy3Wt+r;u~$XZ96vXI-D!>jBF?v+Gfn<)5Xz3CX$#yNr}Z==X3Q z%z#n%@Zevt^!D=XD9S>Ha7ahTaPe9pNjDt!DbvzGT=+S@V0q>hVfd{Fm z=ZQSn7e;at54J)pC-dN5^vzRva1{F7*-;$)1fxEO2REW7=klNm5}wC{t5E3qJSaf3 z9odP4C(&?6@!%t9l(X!VZEy=N9)xg^#DgK|fP76yN+pzmpFuTJ@?hg84~C9}Bjv$s zXfyootC7-x9_i)5iRj=q4<NE5D%t8 znSLJd=ApqnD4onF;c;*sS~kFgf1o>M@_-LIWbxoEG&7}6S%=Jcg^H2#9Wp2JfU69A zxk$=IaJe2Hc+pHI4+cYr77t2b9?X@p8sOr=WiZJk9vsGQit7yD_fWlOjm!NHoF|t- zH>L~M8|K9HTfjMW4b1QG)c?TQ^`s6)C+SU{kb}lgy%C;!UFyl;cSPzzX!G@{0Vw9^ z)a9teF{uSGsXwH?2E86#I|161Q^WVBT)9xle54xH4hFlI!^YT|r^ITqzSH}EZE^p%H|1^DMYYg&OPn!14 zI1ErGBS20`hVL6#yY-go=EWwHQO-`&{uD=!+@EPNwcMX;f+P2brkM%@r`#VW%Keq; zdk9R(@870930WMu_w<+h8`G@k<&gWkM7e)4ePm0y;h~q{FhH4%069VKYIII(uj%H+ zCX-bYornX~c`V6w9z~V+sin{q7RG4nvzi9bMPD zw?vw7km28gvBtVz6H*QTnGnu;Kofk1|A4_DJg5oi5}&ixAJPQd@LvN*XFZ|`(C^3O zu~ie$W6-dhOUyNpAk$Nfw7-@p%gF4_#mVC(zGomM#eA;BK8<3Y4!gHr5C$IjCNOxa z#JqzH-h|a#&j!u87_P;7tz^VKASYov$bZ!!5MCF8E6wl+ z$mXA#fNJ?D*jt)_YIRbGcQg+$f)LwF%o*UHxdZOjdZi?r{4|f01Q4ZG1rlS4+Dp_QyAPn6(?Vm_{f?JzALeZq0;_jSc>&;Vc>?)=dl)h zv|`aXJK(^rA2b2A_=08rs0pYApZB+Z(gd&JAIls+YXVy95sVntFPdN({xD1VRTE6~ za}xGy0{j^&vb)6G4>D%*c?9blX^w~3o>r-kRb)ldOYH+#k#pejEPttEcG8|HrRH&D zuoS-9N-cE^;;MX{WR&{Inx%{?O}mzv>gjFAl;+T%WHy6h<&@@JiW8PHv2^eYAZ5+Q zU}#M)9d{+^Sv6GNl+tm`m#7oY5~_HlR(A$NAp5vBHC90n+o5g@xHW3b1{ zE;UDD;K`gpdm2_c^hKl&Ar~^7Rhm}G#Gf;fSS-RF4Rg0j;=;`-9lQdWvbIbCy-Ewm zw{BR$1mVg{(@r9<@5pOE5sus`+>BEDG8_gdiV+|?C0s$Nc|VRbU(3cdMIs!zP`KvO zw0D@ekPPREaO>HZBXQvtl@2!1d9x0o<_^@trLjLBlptJtX&N6V&Kxlb2@6Cxa;I>O zrFIDt0~Eywkew2)uGE~*Yc}qSYwATfa$$=tE481&p?@RgSrNAj|6E$rp+a!MoNt;7kKun2CU5IU^bn`wXKIeR;(rzbD(?R)uCvb4 zIoyVyPS84A6Ou$V=W2ph&3T&Oh8*Ev5D^EK{lGHenD` z%^jMfR?TK1#8k6I=g_M8t0rjG+^q>(HTP(OBjydIW-cr=^R8Kt>?RTO=J7bWx75c9 zP|Qb4?Zc7DQO(wYs(E6dYM#_ZXw^KW2~L?0l$sZ?OdqZIAt^J2Sk-#E)JJJp=1Zma zWXv`E#faRjZJGgmc{!c?c1?gU|B-BVXaan>8_}-yiYCB}Qu07}RTH4AdGug^*92Jm z8zlTg6Cn33wD#9D!IAs9QnLvnWwx`x7ewx#IJCT8>SK*4_q(O``;T2Xg@bOcNlt4`Num zG{KSk%~I3Cg_-X#GJ0F&9!EFvd8v;zqTJt=s^tRz7xc9M)(jx`vFzLb(FDX9#h8m& zdo%$<_6LO^{GbWw*uSzOKWYN1`Ur*->nBY>Rhuz-T0d(7s>*j`Sifij#_&hU<5x{U zyPr%&@6`nOHH-keOU?IKvu#x6H&Qb`ZeqF0e5^BT<}I_&#|Yt%A_B8g%Ho0HOB_CZ znt+;J$c9bT1k@~xgfvY+&AQl|(=`D#+k(liHAoXsvl{vszb2q&Ycbie25SOp_7R7x z3{61I{3HZ4!Ks<2%zOak%slGWDsw`I4{7>YWj@xKH5*xGuSJ{sA7PD0YX)eugDJ!q zO+d}o(vjw90&3QPX1B&_0%|q|-rCC51k~(tj)dbh0W~{zA_(I(0X6#*N3wl10X2J- zf!G91K+VRJFi{hnnhh;8&x6pJTd4ivQnPDlwv)?ztTSs?P-cI~n(bl{)5~O7f>dYH z8fR#ZkSa+3FjEsC6`yLhW@`dcVJG{RnO&OCO`s+ zSzcz|K{30MkhY(Q8K&Jgmibr#irH3XpNu~0=i8vH`Jx&|&Ns40FVGwz)m#d(Q0IVZ zj%9N!(%M9W^-_ofGyx5kLt{Nq6Cn3jw9SJw0nYVO@;F$Rf{O6zN9zzxfKQrFUmDc} zIM)@l#>JWdC$)fHt3wlx1d^?_b@FYb!T*FEh+O+E3Es!WvCLi;Q4J)@lNjv4<5oToX|DB~)mSCZO&;?Av{sfU53hFIuMw zsA_&b2rT)N zP_t}ab)qJ~`1Zx1Y@MVDX!mT6)+cKM+Wlf`=M+tVGESu$H)#TtaU@OUR84>~N@js@ znkK+9USZ8n*92&1#wZZZ&;+L|A6sTdA#`RM*&Qb}8%>Y(r!pVw%$l8FW@nr_wrB!sb~7#dubP0GdEnWsyEMV6*>z;3FX^t@X>2y_(YXYu@8@s>EJc30uarAspikQc?e4@<9!db-g zW%e~J;zj(kUX&u}#x`*%c)35vr_0P|$?-4KkoK%_{E8X>R_0?_Mbw3#aNtHSX(Hsm{HK9)s}|0=Up&3D28+$qwRW#(;Ua2wlo zw`RcZ|9zQ{tjXZ#GW$6)*pUPJul*V9DKoz$gX<{WkHX+cdd9tFKC&hQtK8;0Tm6?% zOmDdp4T%IvEyBPBi|wTOWoZJm z^c=gv5KVAK;?#2U92Vhco1{w-xf~#dmit&Zix^XGKZ-;Di8RZx!a%hoJM(xUpq5nI zh;oxN=*$x+=P2R$JkqRv%6%-09QQ4^HzAnLZmFwA03ZywXm%xam9J%l`Tal#Qdlk# z2m0MxlR+rb1enux9N(tvOHfa~*TI^h3Fvo`91vz{0tSxP*^i1f0o~?I_M;Nb)Tzj% za`QIGm{~dlX;Y*k=TNDopF<{pAN@tOaKwy}n%J-0{E`e*+8kl9Pbo5n z%Y9@`22JI56ovag!>QF0XW+DFM9Zk#vrQ9F&$nqx^ECkjPQI0~@N`#1=nP2-4z*l$-w`$0hVH zi-qIc98C@@_pvP2v!~p4=YZpF#h~{I1NxWKX(tnUi#5YLhux6ST>kqRZ4Kvq=+B&+&9xr)mOp`z1?1 zO%tHokLWVaD0h4@rkS8?(Y5~WG%FXl0k^3FiBf{|qw#L)t zK9)s}FPGap$njs)+;(ArXEXd`D?r#G1dL^Vn`ZHf5Im^C;7sfJa`Qhd;w;V=Uo0QW zZT8Gu3itPNUn)+VHYQoMv2CdQX_RYZoQRdrx6AFrK=4OsAn%rsd=b}rTw}0hLc)8R zFdB<47&EQ+HDMH1B1rf^6EJvSt@({|^DMB-Y-Dr1S+3TaGjF6@`Ka8-l3Dl9%k5iP zW;#vatNzOSq}<$22J>lipNaBLAcL>VePm4rd&=!E$Y2`U*ZN5_plYzpQEp~n=*i@} zcC3F3gH;U1e<}BoH5r%{_I1eQe}!XYaz%W_;29{$@@fJsdl*LxTN7Z}OL$3&Ccv@} zVBF)=1XwoTf@Y;^0xWw1TPeLlIyMYBM7alPf@8?83iEl&eZLQB?h0pUzK6UASNK>X z$~~;YE zG4|R=U*c#ptHN9i)|q?*o0Tn6`Kj886+X&Ksq!l9Gbz4ngQy`H*s0}RXBq;>d6+LU154AfaA%G zMoNU^U)eF|RQOmHIo4Fzt;po>W%sJnGD0t#sNx1qfEr$6?HYBNaKncqu(4V+0qjs_ zu)^HHGXKmnLsI5*^cs;0AEn{0!hsd`JuGuL{#l1qjMxschk;ZHhpfe#01Nq<_SvZk zbR!;Xeueoai};#7VPQo!ug(l|6j@f`W8o}fb%ou40o1={U(mZNr2CG*<{^tXToZ<4 z@qk72YQj*g70^Ac(`7=c&)FT1&;&@8Nx}wAaHLvUVIGbGGk>O$A6DUX@E$hbQ58PQ zOJyHlVShlWt}sDALEAZ+Z#}5iiJE}!_3va5PSyknk;Q>ylO{ljX14h0TKnicmE>`T zCRnODj;%10(QKIyAc(S#t8hBc0-C^|DtwfeQk`F6&p;;s!%3iDs2M=2gV;YW(gbK2 z4SaTmxriJO=9qJ?a4h41d`X3mWl{UrRM@|eV+C8~I;~qc&qdVj^_l?ZSx&!lqb7_r z{5K&Yw{Fse5s0>13NXji${qv)rV!SxngCrz$ns~+*9FW63qscv2H!XnmCGX-$Bk8EnC4wN%jeFEA79IZZ&#E{7D>3z~qM&7k9WQ4>(JGa#t- zvL-k+yT8KxnKgSR2WbyV&2s2kw^jI9XWV}1vF<3b-$myL@YVq%z@7P|0JqmY0q$>G z0d7)zv-pIh78bGuHV5PCFL{ICnfCzzN_%0nX7532+*6{(vkqDC`+@plUD1{mIXNLSdsM>X$Lv9Lj#QYR|VWTcvd~|CH{A3?PU6S<+;@K zAG5yU+4<$Ud*KI8%;I~htqaO?ze0nZmGukLE-cUe5oy;37>VAQ<%LAntq%7sSplBi zRvvf}IqnKD#CtMpG->xcIiAj%%(Dl|RjWN4U<~(S)}@f$de+JDa)43Twyf((d#yb1 zJve<7U_`V#Ycpy8Di7@b|EPNt=(vh2fA~E;y;ir{l4Z4ITiBLc-i@uzJI2QDO;+35 z+%0(lOe0IOEs!N4$zYR(gg{tALRgYOVgex{A!Hje1hSEkKsNpi*%PvnWF~v^pO8!@ znanWo{eHKq-h17KnVj#OneTk>=;>A6s=9US)~#E&s_uIY*q<6`u~>Ek?T#}0tWPuT z#ci=0B2?)OG$wZ1XMKs#*mmJj(r(~Xowge|H+I+!oX|S$2F^me?X$kYto_?#_X9zf z-N1R`V!MI5eAsTF@;qiYP+MJMpYn%t@&=Aq%-U6tU@(whV&|1x zE`?p(Xv&dYfbYRZ1b{99(JMfI=o{M|jvTid5GcmO$;d4TDaV@Oq;Czq5jBO57y!nl z_|Y6S0E|oVqd8^(5o=y2eiSe?Y5*`Z#IfcQ0{|R)`sx41kLb&V27P08FmpM{~acV3jI9$G@sN6bbmgSbiYId;z#qaMj(DP zpH4=Jnv>L*l2!ji1b5Kp`bskX6u{+i{DZOdcrp^kI!XDsd?6`zP~C1MhMr2!CTf!T z^<-5uGl?V4HIO6;$x%3{C)s8sNCVfYo?^gH1qx@S@j77RjYni+^SzBBhMmDImi4; zw<^jh`S;1$M8#J9DOu&TBa?XW{8_h3Jb3=%x9WxDoU@ThdGJ^%-74|mu~UAl{ykZ> zi@3yt=Xu>KVkf14Oh)+O#~4YnVnipc`dQMQMtCk;F_)#8w<=Y2GlHsBvr|QV6-h-N zLYnfbiKbLvO+Y(_=A>p56w_+j+Z7~4Fh1Dtd$EZ-b{H#eS zMJX;n=cJ;fk5uhUMOt9DDd&x3O6fVzqHDn~IVe*10zo`8Mkmzm~j4Ku(CS(}2Nf8oplx&~WAQbHL=l`bu1W4jO>*Yq`Jx z3~Mel07YhZ%KdkeDK0;~noM!|Ih2aB0VH!c70F`HOtI!jDQiYcS#znW!mwt{092h9 zr`&O%Q!YP;b)Dk!b37F#HLP$?*D5+tcZ%aiMLU}8fpSK$Xn0CbF=N$%sX-8asP8$HG z9dY@&%K#uo;_~xO0|2kY<>zh#FfKp$7y#%Nm!EeTfTH`hl$!ua%H`)Rnr?CVxi=MM zi%9qTQ;|QDZgKhffI)zjjJW)K$N(@0i_6c44FGenxcq#?05AvhH$_4Z8UWgU)fNCg zY5-`vI0Zdq0BEW>1%1o_&{S~>dc*+GGI0v}xB;k^-IsC~V0u?hLGRNo6Q`h0q@rvy zTlTqBWHU0=+=giAagCrdBr5pPl*^T|^1b=2Mj*a7Ur0rXnh2gsMNSgIp8R?-e8XX3Bk*2*i`*+Zus*lKdbQC2Au0 z$5f;lEL5H(KTnl-lKjFj1$`l&B)>EO^o4km{MG=JZTf7=%>kYAB>9Q1Q#?t2pNf(i z*7@gD!KC&^z80Ji3~IGXhz1^@*qo+Qs}fagi_f&rla#goKJYcm}E ze~Pm}Alc$cGS2{1+e2yhU(qb(NfJ)0Sy4Pm=BK0N3fsOo9eH3Y+Af|XO$GtF zNIXfF8UV)ZS#h*|nE^mf#FJ#X0e~6eNwU%a(DuWydqb-X0BsjflCuo}O%+d)H3opD ziYH040ib2#Nz!5fs$~n(?pHyy@+4WLTPB_)t?4M+%$99VM}EteZRb+%9F0Ja+4X6+ z=3F2UhmDOIfjDfOn~oAS5hT-*wa8R6P!9y@Vg%=<-MvI0ei1u00`ZIJNJoj92)fge z<3zB9EA-xC1lhEED-nqM!5)L43K{pNqeM*v2OyY4Anpg}r=YB9+jBzmS?m}keelVml ziu=JO;Je0nSvoRAjN)xDqY-FtgX3xUdLj^Sg9(j5ybUf-M~Rvwy*eHF7!ll1gEqZJ zBk;Tpt~LPG$Sc$C_lZ%w4PL1+UP4W9O*+cDi17{S$e)Q(yba!{5db^6bY0qAupJ1* z+u#O+0Fcnl=_pYX!CTXj%>XHHgFA{5+?sYTBm(g^xLqRGP@+u%V1fCdt8gO3`3($@E< zUF$qlA>IZL=qkk9;GuMsm9vUZr6bMAq|Tln)d)OqgU2)gLz--RB<<#iQM?U4p)o#* zw9w<}DC;7|C)1JDJIqP(QyPKiZSW6M$`rKti<6@QUm8-VG--xvTI zA`S!sMQ$7g<)YP%DRYgX(sYu!U*PajlgqZSe4OdkVfpzHUJ}b&8AKxc5McL-Vzsv z^#*|65*LPz1^`Zo9Bwg4jT~+@IgAU#Hj~51;SK{pE8xPgIOBc?txzruO__iTLn0Gp zid98c`~o4_;S96sU75(TB$z2D>b<&3??k;%1H2RUy&9lT)H^e77NymR`tD5NL_MF0 zGR3N5bq5iWDkH4&f=uKDtCWN6i%ct_qajlJGw$1oP!6&W>h6+*?29u|q9KB#naIOL zAP3o(7zDN;7|OUmAObna9?=NoAbTtmC2As=$wbCeKp+R%mm37Ia^xWU3Il*4DhJso z4Zs{^pE3a0fO3$1r2%04%0c!k3;;4C2idPOeFce-gX~uufLb<8X58CAk~+wq(sVyO z7h~x)nJ8OCy06bf%G01*4zh1FRe)|e$bN$ccn8@xnHs&fy(o-)@R1 zZeEjdSEE98ko|g1l^kThH4`Phr0T9rWFM)LgY0_(808@QT?V5g{c~r=eFZVfLH0W| zMmflScP7fZi1C3;yp#|@3(iyUNs$^bAa$U*j}O`RBwa*+L50{}XR=|?ke0_fC1_CvZ(ImrH8 zCQ52p=T|b3cd<^MgoOT&MnJ9d)&&4OWdI=J=VbsqZK{A0Nx&QreN_Y4Irm`yA@ns3 za8&1fA>)3LM7#r=ZJ{q|A|_o#zL|-VJQDH!Or*X8sx7~F0M4EUBkH_;6*4~S*Ez2* z4adbFYd~3uGgBU}E5&twC*y7fy1MtU&S!L;|H{SrKV_n%hMR-G%S28hlRClweP+Se z0rpSu|6l+Z8ghdFCj+1gC=dNI=$qcR?pG$_f55jZseU z*K|Z#mog3U`gr)GNjcc7jPV#l9}j;< z!SwO)XOsGPn7jXVG47Vnk8yW-VT}96@fi1M_3`kYl;m9&<38%D7`G|Uj&b8~ZH)VJ zEivwtwZ*vaq>qO`m6G~5#JFR#DaLJ=Eivw$Y>jaPWLu0|66eLZ;@=tL+E*VBx2L6C zI>uFFM~q9q&KTEkyJK90b;Y<&>WOh}qmPGAsuH;vmn;1-E;07SxK20_qp^Q}j28Qa zF&fnu#b^lYmCLh57*CdQ2i)f_aI{WnD|+hb|gmQ@mOrhPMmGVX7GP3_C@?3 zkI`;!Lj?9uzBleycr~a?0BjbTg?DG*E z<2G<^#*r;&SRC2P(eZdD_9mp^$d=P4j%?)!`Ra^t2uHS@lyGFrSpY}2RNXkTrM|_H zt(+`Bo{?_Dku5c1pWQ&6l(Wy0gXW)SV!r^T{dNPj2F`OivT>fvp@j2X%I+n$RW$($ z*ak5qaAZpXlq1_m46qWXatONwL{F51nav#zrP=))APdUfZ{mTER-L~ZvQ>c6s@PRs zu@DQt3L7$DRqU>=+XK117Gui_pM&yt_&9{BEd16=%W^Dd`YdD`a()dg6>mfD>SD*L zGc5L|IV|=d(AnYFtwAx%c@ctAaomX`x#9;9WnEyh`jss35#YAMF)Z@!@PqhY7Cs52 zsONi&k@Z#1UKab}*{Hxx~x*#_DGzD-c=X z(S^kQb%py7+weB$?^)ofI{ekRGycT^@@!du2R^)fACFK>Lboo0JOMj2v)v6}iLYrq9_o=k`^>f=1JKwI2_F{C^-&>2=VU-rQR%Fp}LnyRz zl>cV%4=wyDco-sdS@~@sI5aLnk}LU1oXRi!Syq0PNg<&sh0I#XVZHKGKnX;5nmi<5 z@&Nd#0g`T2kgP+>H%y8Js#Qt|A*4{!Lxe6X{~a<#3lyax+j*Rn&H;SY1uhs=am22< z5V88tFGBh;dm-Cn)jwtz?eJ&~ z$Nf#H#tDBi3_8MphGuiaXQN9);T4!7E5a>NWDnaIMv?GlNPcBF0sPVMhX9!sz6BFj zRrv4Fmg?{yAj7jQXDPIB_$SVNtp0~6tm*xy>UXpHZ9x5+@YY$D_1f@!{J%Q0|v*<;d~k9u<$cz%q^Bv0o38YILlD+>W^1?q?Fm!UnMQyLj$ewHRvSU zTAinGD%Q@otAEe*FQN`R{46NI$9Q@$cEby8hb5yoHY2jdo*mf>>!J?-M8d39Z>xc2 z65eXpTme}9ix>;xZ7PCKxM3vY6MK?WUjHP>37@B8;reqqz zso#dN7f#qUH-p$Zhz6g_%2`45&8^DI>N(t6DhFj z8_9za6|?KVGaIoZDppp%n?iHcZeo`^^_$Q$;bV3aX(_LF=O8v}H&Gfx^&e_O>=L`_ zF{Fj-pCDH*wVT+4S@jDkNn>^sM{iyI@5#;MDmK4<3;H=cZa0yzh4pi*5t~r4IJh&> z3+~J#3np#nXFwL^Pw0lHRgbOuB$~W7e63w`RzDijj9D>!o!!Jf2dg$9cD>!i(PgV9 z-%!-78%?wBfp~=9U^fv-dHr>35xdE5iX#?Y!)Yn}M!QMA;8kBi^4_FkRrQZ7MeJr3 ztFE5~Q4POY#b(!ko-Dpa#cJyBgXo2CRk1nsA7<<}6{}q{Iyq*AZ&#GX>Q}WR?JX)+ zSN{!&boi|*R$sq3j@a8&Y;Ju4^F{a$6`NN-!Vz+(ip{SdXYB1N)=*yoBPje1yJ-bl zv{14CwB1B~8dvPUOEG+zV*fi;Y!%r5I&geh`SalCvhok3gQAa-pu277Q;3At0^hRo zbMQZOo&+fu%gWj3P9OR#(sI_jkZmUnv)V>Z0R^$9yM0V9Op}g@G&`6b?GUbLFf5E!5wT~g!tj60I*)5Tp#wRhjEBDl9 zfuOE2kC9l}RZGg}H{QGwkv1;yv?_De98B@Xwnil6C1FV;$4h0u zM3yxcDiIlw$cn~KvB3wcSY}n@rI6do^Chynk>jEA0vQf#8#x>*FO*1I?1yN_2FrPR z9$?A&pF(U|`RDNe?C;>;O8LhQSjm4#B6F6MR~~X-Kyu6IB#11`eHVaB53#<%dHfL{ z%h^aKT{fq3AIsF>|Jlp&Z)GnM1=C7Kk@WWfEZ$Igb>vyZ8|i#kc}*>qm({qJZN63_ z<&E#fFsOXJM8b_9gSb>)Cy`l=A161iuN7t3_&!V@l{ZM=)HN=JO0K+7BJ&&H0X13q z28k?e{26pbl$U zE<|GU;S)!!%8%7CY&Bm2=004<8vB~35Pn3$d#$P_B#+_NTcXYf$dFGs%>Y%AvDf=) zt*aor(bl??0JT03VT+E=q3E_2Fnptz)RWjM{`+*G%)8N$=%w`^BtE8n6M;6X^$;f5 z=ve)iiR!nT5I!!&Tkl2BN5_3sRR=U_wh%bmY8^#eqZ9RiVaf7^2v4e#@2f}nG8OIy zx1&=k%q4tuT7^FgQHsvgQ$SiTfy$4bsHZMyO|tCe_2fhA7oanvSE&3k+8-xXxEdl5 zJ*C3?pgW_ll@4h=0(Bp~TEgx30D--)(uF$E&Ha+0{{?Fun{Mx~d;}nsqy2V5&e!?d z$u|1}6T1c3>ViWrWkkw%ku3y#7b%K>I{3;hIqt z%jZnC3Twl|P;vI*aO5XmmW}se$kVDTI>A$=MJ zCvdB}pASnD?f~F+0;TTf!_t&T0r&)NRrd?wm#lk(sr$Tcs0jP>;gCIzDiyarAC~5B zz7_34k~C9s>+|6Zo3}%n^@KugZ8`UBECV^D=iQ#@@0k z@jq8~3h*rhFm~+*#oPNy(dnLxjA%3{-hLHGzJz;g?HtJ~yp2MwIJgyW8*c$HiKS3x`(RWpxW}b7LfK_g|zq>a@ePzLB_2j|IbydXXFM@^;+EL3>`VjynE9a z(q97LaomYy9EJW^QOjxMcL4kfch?UuhA{(d;W(LC9d^^d0c4?zucqV95Ze70KsF(^ z0XME?&s0=ife0_CFwpcs!HC2&6`Lrp2T-U7_f{H>$e-ra`)&a4B9MzB z0QcXA!nDbs!rkQ#f*xWElct|mxaqBcl%wS@AUWNP$Oc5(aHr#l>_Z^ONDPrv2wZ_X z!@}LW0J#mZn{jUg0oGMox@Rce&cE2Oz|kY!P_y=D6mNF|V4rTi*tFv_6|HQ?CxPK1 z+~>?39%J4ev}At=z%Ov83P)hypUxyVFw%V)k``7#v~WWlAnw*pAYvOe z`yHB^69{klb|s2_KoL;}fPH%AV(_jO8wdceqTy)w^_&MZh;F`*IrjE+@$rF*EJ?I; z)_K2a!t;)bko^G4Djj-9#Turn8Rw3Qb68U8&^s!!j96Q4U4~MxQdO&d{0@qr>rmvb zs;FZmgdv3ABSi00e$H!Ij--oF4?Al!e~uop^~|_KN?oiaG zEDqRb0ZaO@zIA|IdsOl$YPN*RKuu!^GKZ53-1h0~hfFIQL(9p^J5j@1aBuzoT*)i* z^Jf6y29{z{V@L$%uK@fQcjCwAB4=C?`5qXUr*ZE=Y3nHv^gT_Gnh*@B&miTm9;wt) zqRF7utUVAL>*q+1fiz#!q2yi|pw=IdvPz|(Q8|mdgu?iw0QcG%#r&MLrynUVAp3=9 zAi7v1x-5XGj|?$AxY;1Fw%kEJJmUspi^L`>6D9g$_bs~wN`jQZ0Hdiwu#Db?Oe4CO?c3a&}QXDLhaMvK=I_v z@kz^m#Fb_85E?OvI}u-k^p7jxRRFvSx3%-TR0wZ&JrjpI%s%am0Lvha+gnwE`;eIn zC~M1Yb;z(vvHl*({6l2!`2xloz^f^)&}px$m*}|?-J29c_iR^8g3kfXXK^P-EqjeC z2Ent4ev6<>EPJg2EuV$`3fu`XpPCi$VgSx3@So#A-=cuG0q{lwpL79iRlvsqcocVX z1e|D7uzx}P{}MJliiWi-;KnM;YR7Hue2$cVyWHahCDlI7X<(}~?%U<9Y|R8RAH_}b zzgsTk|2?Ab$DNQ?Kcj$lHAId1r0w4;m$oklunD(n)%R7-3;=u=-^!&Sh4y2L1p6w~ zyyFcHAfGQ+nsN)z3+(rE+SGQ<=?9RBlzc#Cxfo~;5Y?8`od51rSyi9bL+fm9YY^}% zw&WAY_%YmFmm)=^=gWZFr_0?81Nl<`TYczmYuRy;eYHrU7`9OiD_^jYW^Gwds;^g7 ztpdP4O@xA#3djCC{<{fS8PHg%ng2_y=UrEUQd8w2o7%D;O`OqO*m+|aQd-Kr`65mH zr?(wL^ByEAE#)noFMfiieIK{d*KMkFHLR0axMf&VH$MyPMqf7q5tYq{K7_b2-h?}yMr01UiGC$~8OG{92FR}g`6=$~3?j}gAHQngLL@z= z2r0kip{qiszw9<^_hF>%15pD{AnYtOStA40|#R2~8D{uO|e0PcPc zfmb51=id>y0fFVC!V*-0M3qZQlWK2Y|>$so5)8!J&O`pfg?M^xg0z}HT;&@+*GvAr~Swa@&f^S0QfGr`eFq8 zF1VSGy%(J3BWIn@H4v}0xb4&FOCdm90JUQk*Nj`Ofe^?s!WGsl5a2tJvV`hlagKbs zUSj$5PUJjoiaw0ML%1`{t(Q;z{7Qwl=8@$ScO%dQDhFN=T2S^XP^NXlECBusop3%? zF)!w`Prnld#S;G-YJLj0bv_MOUX!@()9qtu8P^Z^!4vCwWRR6bJ0d(|lr_gk5V(sG zu0}Rs|8xazSz+*Jes0Arh7VU5vvB)^{&E;Foxt3M-oB8{I)K1#j=W()FlemH5U|eY zVvH9v+o!pjyx=z%BiNVy3m(P-KlHsgj56HOPP_8ZXIn5q;*PGeBZs~QHu8?HM&xic z9Aa=sUs+apQIm_7;GXs4%0n+e+whL=K>3@_#(D&I^pqVvv|=e*g*%!=O5*}ZEbizu z%HOaBV;A?V&x8*BOO<8ujxMn)FS^af3JdqF{}Vd&i&-$GaYwf!p&Gi2_pC=lhb~x) zrr?e)2i}pD*kr&RU13)izJgQD%PU|oS%>a|amYKGK&B{A%DohkZ4fTr(KsRn(8oJ^ zWm)B+522@cM`u9e$FVfvJ?p~IA$~f7ck~s=bwwMb6?gO`BA>-H!#jGkEOe*^WqC)B zA@W5C8Sm&3M9#;+;~hPPGSPJi@V)|(U!x(sqt_zahY;W$y&93vA;3HOIz+yW0PpBE zh}?+)@91k0S&bDP@8}e;{Q{$%cl2^Zn!y&{(bpi`$uNGR33qe|ZL0>4c+a{hbkVml zE%TmrD0Jvi^ds-+E6{ztm>PITPn1*O@veiw%+lsQYV|FwOoXAOdO_d@@3Pz(<(OJZ~F(04$gd24XqyGY@uW3>=b{ zfR}7Zqb?<^W#x-?OLclYnC=tNq-m34K6r^{fG)f=SQr|R1hHky(e2iXdV6JqV)IH@ z8obIQPP2J+QGaUS*(^uW*Jv7~6G-}6w3Pf7q9B_=8kyb_1i;|IF`6e;I~uk@NZXn~ zSo;QRmzJNh`Irm+Xf{T``r>i~ZO|YgWk&-+8(Zuh4T2v)MKHFdg7UB#QPwYoU_})d zm}A$5cFuoWQkr^Buw>c1N0JyHTZ6?l?A#z7q+;6*SKAm{?O@mT8(~Y7&A%lH@Oi~` z#YGf$1Pf!;P@E?lE21b7%&coq0_MrPhNTvv@|^wgWOQKOf#^YZzf_fWt@fDCk%`&^ zXimolfUv{qz!iRcgN`MvLnK%~2ga zs8Q+Y`7PjMQ4hcyNipL>)B;x?HeC zE>I#@k{wZ1B5z9A*7<$~`Qq%DGi60*Tm7pLOyWk6t5ii#KSFXjCLq`yEBxZ!#D6hv z+d5$I3*5_T9YByt;FbYm8q*hxmsxFsMrAr^&=7301)qV=ekI_bl#d%F*vH5H3X1<{ zT&nC|K3GUGo}sI8gYkT@xJp2v=n5kS(dWZtI#W2TWSRKb_7qW z4EV1u8>Xh5Ucf>`$vhwD;dZTQYs<2`86+ad!XXWw-o>6{W5_EugSboiX7Zq0R(Y8u zg3N)-CZRe+(y3O1X(Wx_22i?I0MQVL8#rC<8^Na9wbgP{)GsFsgoUIGF|m*W0j zK1`vsaV6|k zm%H09kpo;VN|lAT0AG&QI8us9LJ7$qAc&bj5dO<$as+6IBY|lA!C(s#1+N^oJqDH| zC&>vECfUV>0nit-g2Q}lkl+9xJ8>6N4S>F2=97_ps1lgF{Sv;sl)G-|Y^3m}xSDV^ zY#o3?OUrM!!!MrY5e`_%h2iD3h!U*T1T|xO+hg*@x&?ZUf=VOZm z`}o+2`%LmlkU}qq4$OpJ!T+L*nhON*F^>C8G|XLt8)f-0nfz{KhL^trrivndfRA%< zqgFn);%2S6yBShiXn>DBxY470bm3Nc7`jjrWXrN3!9G4N#;x)&bPP8J3?IiOnB&6` z?++3H<%;7!{8U#Q&lTTdOR`hpFI9yG~`=8_e{#vQSl~5ajq! zI%$B9jkv)iKFC+a0EVbk!2mu|63p?D#;x)&#O5InACwE=;UkAz>FY*q74ytg5DT-mlcbr8CV{AvIHC=YQ ztzd}CMH)?sN|ZoXH3!Sgk}?LW3l%+*h(Ut*pems__ub7Ww^mO zKB#2T`IJi{L6DE#61<2H;=+qrVLU>`la}dUqTy7)g3MhyErbB05{8=PgIO>h@n0@m z(iD)QC6}NUt5u08QIdjLxT7#yoflqw@x_Jh%kL(Dk|97mEdq_GR57OpF7>ShLU^$( zILQZv;N=*mw3Fz-ol>Hok2LPm5^N~bAg%cS-(D+_gTe^D@PQKsYqmA>bxXLse%Xw* zWNF#e0N$$dJc-ATRPbkb{89x`8ow1TNM_-IAAcvl`FJc+!DV>R%@0sMHsX$eFB<|OBrok8@ssH>v8jR|5n^Q(0?cH z_u_s4HxK5Y!p*bz@8dT7Wp$*N{GpOrh1*>0J+^~shTlwU#2v?N+H*F-YjL;WHvBB-jVsiD@X!inj_ zg~Nl>qeBuOo*KP;WXftiHgSBUb#QFtWNXXV#L(ba>-4d~sgc&Hk@1n~!RgkKb%p7f z6T_nutuqr7V?)OVN5`jIj}8qL2B(gjTOB6@?rY0^K8Jd}H%})+aUD|PCywH!f9PJxBF_=n&XR)^qPL8&s zyYa`aK8!9uK6C=TI`+R_@6hq-(dpLo$mOF$BdxhiPbQzpw`Nsu|IZWiKU@Q3e`aue zXk^;@TgDcJ{BO$$Y{#yU?3Nm)lWKIf3~?YAhDVMJo*0`c%$%AWnQl2oy@o+KJUTvu z2n;t2@xsu=@#7QY1qcFQ&<2nJ4$;EM$)SoJDrMTMJ^s@wnS~9?0GocSE798*$dyq58PHaIxFC z){TUg#6rMRSLPN~{^JT%J`eb-+zrcJdjbE4k`SkTNH^J7Z}$$j-FfR(SL^!k#jmHj4I$?bSGGuX zZvu)2=Z{x{fJ+ns?-t0909he9PD}h}Ui>W*|81be0|NOD$fzfl5OAH0hol;G!#c9L zVTrpAY;OoP#iTPIlp%(D@Y)IE^H@?EHS_ENQikO2@ zfw&u5hgu=IEflp?5VZ@D7-M9pMI>R?Zt!D?>pExQw5BE=s&ULRti?jS&G!Lj6t1=uALIII(RUC4_{WBgk3jp@|fsxl^IBLv!2( zDD4!`u?w6gl)%^yIs1x=7VCxgOHskQB2@22tg><^wA)=FPmB+Fwz{r7s}+2iyIi6R z@yQEh2X={q;uR%YmrrPdoXG#>p9LTG)oTJ&ffFmz4->shw;hpU+YIj#Ti|`Al&_f)3 z;KqRMu6Ncj+JuqPFPK73JBSO#;y}4mw95{vw^+P{-1{q$9n{KIj~vbk4!0Gn?4Voowb~mTBi_uTm_F zfC+Pu6Y3j$(iNuM?EozxXos+Qo{#4^@qjUkU1JK1?R){4bLe*4NpY0!a2G+jmdrVC zjv_a7aumohoZQfgdUqo_1+!KdT8xvH?NqgtlzNb*=Edq`4tjZG$e9AMDA0tw)$x*v z;u&27-adBib5H|5XO18w2U^i~*3Mv9_Q%}~A*TsSjPoy=PX8#w75G% zDV?E~ka1+FW(LUG*%zE_8|X@KRBqvv#;m&I=f0vz)78BvtG1 z^`SVFkxY8^Zl&{Qa=5OZhEt8hw0{#*l0mVh?55ID{S52Is1|{zs@nwFdHB^tGaou{ zE`@))^bcx&6xP>T=kZs^RbPp8I-lnJh{o1XD`L(lo{^qY`0LfI$SkYXoUmF-D;bCG zbVDo2L+7Wjwwv1A)y`>~Y-}Rv=K#T+TkYJ5np_x}a@B#(uL+%XFsi{4%!HkWOqk93$sTxD!z*;b3{x)K$+UA}O zjI&`!M?)M3kv8afj8^9g%xyFU&qD@k^ZBeT652>5IGZ-C%I`YR(&QaveQKLK56G%Q z2Qf#~?M4qDmT?T51v%m^MQZ9!MP^-n0}`oIYn`tHtL=Q`)wIl=`w?LWisg>3RY}m> zfou{M74jI^$o{Wc;)Wa9uv&~}#3P|)A~jV|f3Um}Z)qLWU}E3{zPSOAy8=j9sww7*04#AMG>N)eN7ZVl)tzrfS{o_p!8i!b2jzssM(17jwr%79>;knq;o>BMwNc|Dlv~2#*G4Vod<%_c@6C#D6Oo;s zkp<<*({d40KyuJx^kNUN|~3Qy3iMYItyFq%eNsxSupNGBkqy zH!R}^r)GqljXj{p8c6NQXS!0FtfWs?M=sHg7Ag!QQ=`}vn8DteRVZMaYGzAe#!8PI zK5?{rVtjOFVyckM?H%`s?9HdZh2FkGI@1qcgSp49kS>`9frm$qPmYWqwzBCyuy9YN zO&SfR^$+9=J-s~{@SGo9$nDQ`lYea;*^b`MP7ir1cd)O&w~$X|z#|ZeDso;T`KSBS z;|jijRG67492tcm7!l~{?MGK-`?FyE`JfM-(t~=vy@{EVq$-(8_2;_Uz<$49a+$pY znS8(1*Lg6X>Gu%s&vs-Bi9R%-zmV$f=~2!0Xkf#qPaHlzIzw?XR3y95hFpgf%Jd`< zg&1ZJ0JWDzw>Hn{r&8IL#n1@pl44{@BSVu-`U@j*dxM$&6dGoZ0n%I z27ql}GT)!K((-7tAcKX`Ba~xs5`4t}evTB*tS0KTi`L;qo zwx~+^)-%x6Rp{%@_E1<;slF~!ne9m*@G>R`I;dd4i~fVs+I2EMJ2*&9Czu{eB~s8{ z9nci$Y0DE@2-ytwgQp8uOiT?2bVhe3pHJ+{6#9F63theFR6QD}Mh1tWA7`d#roAde zjz!&dgQt2Z<$F6a7XIZds8+8!vpLD3(4Wh8x1&lmTDzoq1&m%pIfsRj@N^&8VCDC6 z_)ri)0eCxEn3y>>GR4n<5C{zbAjIeJ$keojZx0rR!DBGpLur@+$r`HCK%ln zkhQ+fYrQl8`@1qdyZQsVtUo_cNM{qf3aNn{Hm~~&`QCwC%5Nm* z0u0f#D9a#Rx(RxwBfHCV62(tzQL+S_l9|S|e{yJSWN@l5JUKOa;tU?LTn6IJ2?_@c zmq{=%u?&q(6|k#&cnqC2JR-W$OjF%?48csk3loFvvW|`yj*lD%x1}3pT4HHTOJ1#7 zmzWOh?aSn3u2fT?H`l81S3qATO4*X=>&x{X$ad=~HkZv~V(o)^wB*33!0~G3I-xi4 zUChF8yOrOU!r_FPrPz7kr9ahadSp)M?(526WOL3E$p}n5$*x4to6Ca^&|5r9F|%dlQYCmFlJU}LNboK7H(wTjUbQ=A( zFP#RZnLyV;Rw2JWfHoC0)X3D4!69W+O^!}t5}6XFz+g(Jx^mqz;c4D%R^v$Ke$F~m zBhx32kCZ3`E!;`b;IIjfPam~LWTu)JpEz>F!T>rk>B&gpm`~8~iQ~slK@0olmf>7G zG(1L1M~82B8LnY^(~71m-7A)DVP9`oKUfx&IX%6>fZ;HJM&N0SFmh9%P3-OI6Vou_ zh6|8q9J!aqp1P5Y>kx8an%HHyjmFNlft>)3t*dQvUAQt*_ z+9VaD!L-+mhtB=9#?mnKFd30JZCt}}SO?2MSt6pOgn;54P;4E!jM4)Tw{+h?KDUlm z3_9x==1z}L=>Ref)+=5bSovIE3WHiRsr8;~Q-i(Q^#6hlP zwSiAXPK&*>r!U#xn}Euho|%FbX=M&%DP~;fbY=ESU!Ef-sb>JvegeU)XPw7Hy=Dpw zwoaM|1JL%`K+nLM;mVHEogYZ0V4YfNs2&&~iT+gQuE5MZ(32nN>+8*NI+g)yMub@W ziKI$Nqm(g1*Fl_2CM}wnZbajW=7$+?&Y#6dP{ecg_DXrGGM(^euu@$l1`~T#n_QF~ zHpF1*z=F$4c598=e-JApy)7|3GCedkI*CQIUhB2_@-NfZx(>c6N z;4u(;D!Th&!DaPGgQA2jOSWQ8L~oWfu3a@w#HA;R&hncHTLe=j3`eymfi$fZgMFHX zM09jyQ&};V`x3B~2Rd@y*aiu9JjRT-hT*Ui>)nFO!sOV<%!uCtvxGr2NXO7&&Z~$h z1!%PKdL`V3e`XxPXw5*Rl?pS79Iipd8xRp?t`FoO%R^%m(<6G3+?jzYyX?dW#N+b8 zu@fUfjiY_0402^gDU+@v+l93xO**5iI;cw3!n?B@D_kHP9LCCAI)8ff$`MQ)V)@F5 z-6Uh#VD`it;*6E*p3FfrbC?|3%=D*}>4_sVSHN>CFFQ&m8#(QdHUl**D;*`iD5f(a zjHLyVx$G`%HDF|U3X7vX!v(yyL6ng+11}J~s4$Q}NE27Qfn+Oz8&woWQC-+D!%7yL zXQmouOb+xU_Cd39|HT)_X__}s?bt1wo;fPJh-xb73P`lS8yMIu5OcyCBnpKm<(x2r zD=9;XvEi_9gW;1%VXaBa9rligiJ$oIYVXPH>g`s`f-TAjr*xWaGP3|zZI%>BpuZ$A zTLCX&MJtfne+Zaoq#X9IAQX|o-UrsshHlfdSZzZVy-vb%uXz7aOz5c-lL}D*7C=zW zIgKmf@66`B$pIWFm^BGUaYrvKc#chMd$s#LHA6`kAxBfYQ$anD>FOHjO5}WHP_oyH zZGglcZ7l~4;r+R6f5tb1Jq5Eb-OZ(=Fk`)N16BJS#I0ruTf4HB*%p%9WlbCzo*wck z=2j%PB>8Q2S!I$PYT^X-o~(#rCyGCRFi(RFNh6aJkVvC2lr^%eXCR(B=bSj*A6wev zbbxHzvTj3s)zk>q{L>?=8OG7} zArR1fR2VZa~|) zP|RAi1BL}Q0brki-))NDMkZ6;Y3y@he;ga=vU?1sG8+s554*o0Vm)U2Md{KMZG1J@ zm8I$-4s1Q=dONe2e6bSk!A@&nt1EY)$lx$#IT2uWJ^;hqY=oI4%6Rc!P8x%$KVS!O zR*^l){QfM|U#V`!{)vB%k;=ogg^ub;VV6yt?2{wd^EB1@*0#2v)W|c*qKRP3h;Abp zIqa(x(y;9dm}Qe-meNcnKX(YxYOMC=e8e{ffnCpfUUx`Uf89`8gRIuhLb)E0mea%gaD*1}}(Xlv8YcDw|N zjT9wQo_ZNNcB$TiIxz+D=+9AZyq@u_U@U0*u%ZaJ78IO`1NsFH%{PS5pl;&7}5bj$aiw!f`Q!2f^pZ=?UiCz%N%d0 zP-h*xz(uu%s94c{#^fR!8D1fO7#Eq$q9Zt&;;>A%=D-)fValk$TzF(+>i8gamv0E9 zIukhflOD+=uo&^gLCFs6TB=R1syyyfj#Vwv&3$?Uz|w(r-ib&%_TBX1NPD{<3}jgE zLpS)rjec;GAKdH*xA?(xM0C!f8nu$#MkS;5RtfgC|0leh<@AuJMOY5v>`y2d7Z(@S#89bRqrzbxd(zK_1c}-3kGpBeGp`pe-WG|oBu-q;j51?I!c5I`Otr&=MV5c_#Oe(o0 zOUe{YAFolKjB}$~X)q5VXEf7M++67E!T}0*n=pvK+`2nmSHT0nt*a zG&!c-;gxX)y-XdoH>e)5uc$4I>0_{};@;L2XtuD$KW+uLsthNw?TkH@5)BqmMg!O; z@9EE`^sxr_pxR|aZa!EpeNQ#)j%Rb~wKoyT<4>>n?R!q}h|AYKmcxXHn->@o&V%{zTl zjS6-WuL;ahZm>(jPD^*wNy2PBnKM9aivyi$S+=h*z#UCCsgKeG0rrGZZHgP?QdWNJ z*Kr<}-9I*(%3Vx$oN%3(!W%X-lM`2rObH6LLPq6yfI3S@N5z&8C+%8msCUCrQu^_p)WSUK8aEF_1znc&jLTfG#Hj13;e`aRzda=G`4 zT{3Zy@LS1)G_D6Q!3H;b$q}_SQX3U=!0I1wfpHiMa7pMogLkrj%o7fU)$I1mJfIvL zK!>2iPDi`i>hj4^2OHiQfI0#1Fel(_uFNRDAr{=fz;R7Bg|h;f>B^x-9o4mAN*F-j z23bVn+AxR8CW$8xp4RKwUl@Q#2y{KB5?LIQd**lzAFieM0ro*f0;Fk^GK>2SAqTWj z6qHnqO^hFnb1ZwtGPDCml7H+LY)cpXSOmSlAm_-zjU%t#eM+8WTR?5-pe?d6)8eTN zT)pNVJb^R$=?S$FhY=y?K%TOcev-`yGc3ehmxFoq{ zA$dU$v>hGA44^C=LC_^;WKNrtxwdvHiJtDHmCkZMP>nILoDAm59zoxJ=%oE1<4ML> zF+XW5sc8yZ8m2{F$L2D-vUwEX^2$snCX?sw0=w2*P?0;dnPo+w9ExN=%A1kZ;iNj) z#;b>8hX;o)4XBtDru-zg^-OIzSMKt~1XkPx4i~N%ymSO-bAdgQq6BUlQIY6@EL_>F z1|}J_K@Bc#j~6*VaV4t#06b=3<}6^#0eg!2xD@Z(1-A7v>0MZmK8}XEM<&vONLm{ylMK@*eTulU3z&T=en5bCqXpcG8-B6X)|jo z%$q#}MVeK&6>{kxt|?jd9WXp`ELv4~zI@8zN~}n42#N`FgzFl;QSH%U=uUNEy@Y){ zIoQ|-Hy`vzXFhiz)6?B6{E__%c)$cL3bp#wMiT`^JW;52;Rxqd;de! z6!51_Inmmn4t)ZX0?yx4mW(d04PaOVC^5%+`n19~WCEmsVd5wy`(|BPoGp628ekSW zmkx-B@t*mm#XbrgCbFjSnrYThdIb9Jd@`$HQWLj6uRG=RS&o_2oPsSEwMUDFC?z9Z zFGo(JBY1@uhfBUNc)B*QjqSmdZ-AH!9&G(fl-=+Wu#G&+V{i!- z^xRPP3`A0y1qHEb40p0!U71}N(OOrSW1PSg7(CMeN8sX|#I62nZq zk5M+R*J@9`X)W){(Z|=U(0NMh<>S5|oG-KoP@x}dE_4T*B3@`}@tE>A3gN2`Js8{o zhl7>bEtD-WX^?;Fjo$2sILc<3uYLj(8yD7ed7wGO(>z!_QvViZIe`-G6K|HN*h>-T zTP{6{Mk{;=ItP;85eqxQKe10|)aI$za(^L?inAT+1k~D(-ho|Va`{K^>v;4|4bU$C z1EW^$aCqw?vQTWiv zA*!}!)j5K!lLLbu#v;9M=s!)q2S=G1CsZS--)Icz7jYH#+%^8T?-i7Oq=2=pXG0XX z#D&M|nHcZJ#xs}3S!fPnlQ(9xrZE0$X2K2Zy?K-Bdatv+l}PYJ-xS>_a((<5NL_O)<&@M!1jW-2j=JY_UviEdX~Cc zzbj?zzY_zpgJ+j~KZaagr?_g)K4jlq>0-`B)ZxnMN9I)M_7mW=zq@Vd#+HNUhaKFn z@ddIoFMVf(-CB$aTmztbn!^lnn_KHkaUn$8UVd)V_a0@^d5_Fl@Q=~Yk$`a?ybxszJg39?W z+k@I@SG)^dIznNQ`iJfu?_Ldv+(dww(Xw+7SWg zgCf9}ZuCy~kx}f7Q5?ieL=7_f_@D%#?P@s-sqOad4N>UIpVd%Gu8G%`0dRXYEIk%*1%r}5fXysDmJ+bs`}`xKV5fj1vUW4o8(|S(Ko@H-Eoqy0 z?|KqoULxRH3eNM;_GB3cgxZ)fm@!{==h63kgGpPK#--EqVuHI@M=zb(d`m#Pu%P3W z&1j71HpO7<8fsS$;kf8?NRD#U7w@TnGWItTr?I; zVb;fjOEwR%6Pw?s6sFq2^2cdc-cph|H8O*9V(qeqU7usq`lSpV@cmuouo`P$`eS$T z-5up^O+#P2ojsmG7`$O)TpL-l@1qMRU4IO5I}RMC>z|plAde`JLmfeV#92^n$XcEK z^gE=9o`lnosaXVyUgjmvHY#5?7VB9s$mBLsqc>4i%e_=zN2F4Gy=FgG?DBF@#vEv< zH!tYM$CppMg^GH`C7Z>^X-!o@;iV}~v4R1n4+Kmusgg%cVwxGK?@J{sZ0)Lood>*@ zrTo+Tp&0}G<;ziOvrlc$1P@x(g4x@2x^(0e-zky-qV~Cs38!Rv2x|$xuVZL2ioEDR z!`Pc#PlGqp@@ht#3Hb7378?O&)`fjQ?5FY+Mp__BLOC5u*LoFe<*tUIx1Z1n&z8WE zootIyk72k$f?(C07!%iiyldoP;(l)u9;)8iQDCSQ?e{6Ip~j7AzmTD30$Bi4Dd=Mu z>W<=Vcm5)#DX3TA!W@hKL;amOUt)X{AG}6S<}nVJi2yn+5q^aS2>^2S)u zM<8H+$yR~*+R__+Se=y=Z650NA!zgl7_I7{PV%F(Fyc(=+KCjKDPt0qJ zvXcqZ3Le_Q)+L*2`f0Lc8Zrf8`UX;cUJ0_WysBX*tH);P} z9lJE1-N3Vq73+&1i%e9{y2iP-j5PG^s;r)sh@O!DK|0gOpQx^RUAf9x)JA?>Gnkhj z-~`>**qu-CdzVFd*`^?^EEkM3%#V(ms~>>`X~)xi=#pvo;7(T0zb168`}*?hoa;e- z5uVa|NMk2%bB!aA_S@56`Scf_c)Z$5MbrOvNM%!B*)73!P5HIX>p{o<%BR2h1++XF z?a-lAw9|v7Rbt!}#&aj`banU|l+9N@EhUrH))P+$dAb&PQq|$tAx}@W_4v~p5I5H( z0_Yo4|Da!&7wS~C7WWhR0p4C?7tZV_egrjG|4vnh*Z*WXi7z}|++W9# zC&@NmYhP4J?j)jC+#tYnOw!}mgs-i5eds#(`tlo`8`-BpS-l^564iCrxYw4y-nkB` z9o3zqmDP1XWhMA46@&avCw?dzL3c}YcMHtE9xF7bqC4VLhHJ~~?0S2iGv98o&$1WT z3+=|TC3Xu1tKC z3?T;}f-lB5Tk@~-a;f-*9$QuXhk>}4Rq)Lz!8b?n?esDg*XH2YRf-`o$?vx+=9Of? zvFc0m*Gqn1_wct;{L8WCmE@l%`F$OR-}Vb!4t@itn4X4`{QPko|8lGaCHWUfe!o{2 z_?Z!MtVJdH7fJp;FV`Y3#DHThF3G=G^55a*TI_{X{-%=rO(paPql7Fe>_xZoH zB>(b~{L3XjKiI6UXP);f^VCbYqb|*z_HepB z{$|O~k36eOr7tm2OQjzR#JwN_j@4R%uT}7I{#6&Xn}0d@8KPo&YM1=J-fZ_XBji}? zOY*Om{Qi8hz9j#~lKdMbzt0c;s*Qg+*5;D@nDK)MebjYb#6)e zxq|N=FUz@JhylmiF6lmSyC0PF^Gec#pY3M(9VO{IO3LpnN#9wLo+wFAl%yw1(vv0W zsgm?mNqV{@-IokzbnsK%zV0C;!++l8SREzl9bOs(4t~0zxIBM4z`q<=QN`(g&oY-| zWlPeteql-9U6Q`LBz;dwI)7Tqza0EHOmY2Pej-AS)m@U_U6S5YlHOC2-dmF1Taw;a zlJ09(W^_t^yvr&1H6q9RyuU*0$S)@ORXFlHD#7^qegq*0Kdi;}`@N#(SHBn3{5cqy zKRLb*2jVR6YiXr#ef?CbUoS##|8lHDegq-Mx)?JcKF^MumQXG19cm~)?&{y^Qfr-B z*faZ(Zmt>xhH*1L=h#}z162GY=eosmKp^`X%_`qDm z@7qSIJ>F@HlzytyR4qa>a~oG7VTYN35cOVVFk62Ge?{`V#ECrjebmc*Y! zob{2`TG(rLz=S3&j5yOd=hVVJYtV5eFY~N+9p`$b7WUO{9jA>^3;StA$NMF|$a;;A z-y`wG)}1=8@HJT<(s4!4QtQh)&NXALwcPp<;^tzW=St%EuBFhc@~^b!A#N__Ut1F2 zSrX5e#E+H4Ux7IJu@iT#wHiOxiGaR{{{fw@#>X1#F&&>oS}p94AC=^Pt|VR_Sb`AW z+>-daD|BUeF#T+#lOF1zT8#c(I^HJncB`P{J0-r}dPNDoHgi5n1lKAYdTJ`n1lKDXFC1@I(ZJH?k`2<6Xr|#{#X8& z%~;EZ)!se#|4QBGu}7`kmA!Ax$U(aPhMIAV)5l;1^{D|bhkvN$f%G}77sr;R`k;;? zfp~+jg~;xud5=sA5u%WIZWSKPa`TkZXu%J^}aAVi2**hxqIpkFma8{S2 ze!is9xqnW$dl@Zrj5isz~39Z_Aa^bH0M zUjk%yVO`*a#zWyX;!H37Gkgc7kW!xBQIZE!NB`zf#{>IskQ7zT$@i}Q(&+|D2qG7<5y&60Id|sl?xhg-ZeoU_N@70g!RX(JCbguGa>IZBqA69mK z*&`}{*4Ke~3Hp_$rF_?e9sl$yrXw2`7OBArg8| zr~=6eLXtxhq$3Clp`-LBf(1npJ3N3`5K%#~g4jh=6crQ|#DWTn4G~dMQLyq}*X%VR z#Qc8m^UwQv&xi2cxo7sC`<}LCW_KALCc;G{H}(9Q+QIAo7n3V(^Yg9rhX2*z)3^KA z3#I!bZ1#sf+Ffaf_D6X|5oUShQ2%4TzbwB-k~d-cclm=u z^qqeGr|GEb@L6?R`$%B5o7k5kC<3iC>A|i9d_Ki@3RI z^d^ZZVpXxGSXXQ!@_rQUX)m5Bb`g7t1H_@?NO6KVRlG>NOuSmWL0l@{F5WG!6W5DR ziJQf(;+x{T;z#0s@f-06@mKLLF+Rcfw~|;z%oJ;h4aDYR8!=xj6uXOk#B;>+#WCVU zafUcoyh2y8?o&}; zWief>A=VKai!H=*m7w-|D6Wh^K}8{2Gd9ibKWm;(T$5c#rtFxK(^#JRlwugUNnA^~9E9cX5n3UA#_QA+8rU ziyw%UuvCWarlHtI>?xir&Jgbxw~D*OZ^dI`Do#kLw^%F@r;7{3r^I)~&%|S5FzoB8 zE;bRni2cP2#Y@Ch;(BqH_`Udt7{Q4??W`-d5o2PBI9XgMt`MIU-w+RrL7ebXZ&k6m z*iq~)ju0;quNChWH;S)_?}=ZFzllk>;9-85VjHouI7GZaoG0EO-YGsRz9{Y#4~xHx zRnq+Y>WHnyVsW52R=h}DB;F=ID844{7QYk!5-a1vkp7)6=8B!fzT!x6hIo~@T6{!& zRs2BwMm#QhxKLq!r-@C)sMt$9Uz{smBi7A9kI1oEDjXMiWiAX#ns|7;(Oxf;_qS&EKOuNH4_WOv&9R{76*!B#f!v6;%(xC;wEv2xKI3DOswtaQzQ-$$B47VYs6c{2gK*ZH^pzn zqhfL$UwQw z7yl3=jr{!Tif4*F#nIv{aiO?Ed_(+1JS+wq`+BR2&BcylZ*hb;O}tWEDy|Wq6kij+ z5PuXKH1YGx6T68s#rwoh#nh&L`flPdajLjjTqQm%J}15{?iG)S|A>)hzWxSco;XOH zD6SA+7Q@Z`{hEqVv6pzhIA2^TJ|J!p_lbwZxEx<^npjV4D|Qh_ic`dE#CydJ;x_Rk z@sRkZn4Ih9mnG(iXNrBqiQ>iL67do7Iq_Zb2k}oat%aXYw%A_mA`TbViCe{8;>{2o zP7#-g_lR4?{o?nc+s4;hO>8K(7YB$X;>F^1;=|%*@iXyHG1%7EpDnf&3&sB86!8*q znYdPbN_<`1BYrFXA%@QI^J^%!5qpZ~iIc_4#l_;?;zscm@jdZtG0@J>Cq--^7K**a zapD4TvA9m$D((`$75@-J?fraeitWXic%C>}yj)x?-YsqvUlBhO4~q#M{Cuj44a9b0 zH*tt~fjCdRLA+CZRD4nVL_8=ud47IX#5!VYu~-}^jukHw7m2rtPl_*#AB(?<@%es! zHNuso2JueuQSn9b6Y-$vbW%Nt&BZ*ipEydqT)aVCBR(na5t-w#qHuxVqBr0Pnwu3M#a(MeDOwct++*eTRb2h6N5#*{_0{AF<-<7 zpiO%|PrO)MD6SIMi!X`0#4p5O#Bi~%ucp{WjEN=UWO1RmLVR3&N!%lTEB+ydVtzgi z#Wo^7wnB6<-zq7IVA%`;QZ6i3`N_;%4zp z@gwnj(d*&ssU`Lh$B8eC`@}EAL*idz+*!V!pqL_76>E#F#SY?`Vi&QWI9j|woGQ*1 zFBPv9?-1`6*NIPvuZcUvcg2syuf=2H-(o^f->+0LOKc*x6N^QBhs3n+apFbd3h{pN zY4LUObMbre53zDDU*BnBL$QsBPjHz0&K1XrGsQ*XZQ?`XW8yR7R&kg3nfSfYuMuw)mx{NG_leJlFNj;kH^iOd2jX7w3-O@% zgLqW@L*zm)o<}5#$znvTF4h;@i3MVj*j?-`;_XF7?@+Ns94Af^XNVVzmy1`6*NaQU z72=)Z8gYa8inv|eDSjz_D;^R57OVF4?X4@e6wefUi9^K+;#J}j@h@n&(QxIz3`JR!Cn>;6l zulTv*zgPGt@i)oihWhCf#SjTUYmm^_QsJKB5OJ(HQ@n)q9A^cI{O=G~EB;}HH;7M4 zzD40z#Wy7Xn1sF~3jal-4Tgq+urGr|J~hN_$(t$MLToE}XN6;856K59e6BcL@(UH7 zBF>b2zQR|D*Gj%z;oHPjl0T^MqvGQv{Mf1ZJtW%DFN!}V{-yZfdA^^?VigkpXDM7; zY#@0nh0hSXif4&^NbEnFM7|TqMUFF9@t29$h}VnD#9PHXN$mF!2|XLcHx>VmxJTS8 zeokV)A4u$%biU72v4hx~gq`P*7{kXZJe@?n&lax{uNN1S*l(r6tHlRM=y{Yx{+lF! zQQRu|TMF+IKO>>L_Y1wB)pqI;X&dUahAAPyi&dm;%>=5BU?GnACmtgCXDg*CX=}s z2NZ51#z^GTT^uY96E75}h%-spIbY$c#A_vAuJCQ*D#;&I_)+l%@nvzh_@TIuL_Xh= z&G6ik!UJ}ep~VHik~QcKZ$YcTk)vmfpL(dO;;nK?{qR7=QrXRB=$Q~>>>F%B=(y~ zV!wsrf5_8dufmUz3mxY%@hQn)R`@mXO%nTkCjKL4j`!uw!~zoe#mK67PDnhDT;w=- zA->6Pj(CN5wRj!5$Z?h`yh2<{Lf;ng4e>*ArsEt^_=Fgo;HR%5HW2g0KH?a0uDC$F zReVHzS^Q8uEdDB1y1>t`me`(TIf#A5^TY|_Leh1d^<)I?ghYM3CcY!?7Waz##UDuQ z_Y1iQ$M*~U{ZqsYv4)sUB3*M5`*kO?9Or!TLK5xfO0u!zEGJ>lZQ{LTk>fn2@N?oT z;_Kp0@jY>$__=sU{6YMMgx<;%eO41|iH*cF$Zn3)kNnbchLG3ccq5J#FA!&l7m4%5 ztHc|{CE{)3o#K7sgW}`j)8b3wR`D%ym-vymPdp$V5`Pwd6HkcolYGBIVpz-+Yl`*7 z#$pSxjaVRd7JGJXb5!Z>2iBF0zh%bw8 zitmVf#J%Fz;Rk#J=JX@jMal)-dHX zL7Xnm784xAr|5ZBFsyKzh%RU1n~QBkoH7{s*8E%5Zj6Q;y@DDnM1@8 z;%MNkTBD_!G&&A)wKg2+s zzn?26i>YFLv9Z`fY$N82e2*3LA0V3N4-qa=c#JqvoGLC5uMt;@tHpKV!=icK5PF|h z*gRi|Mzot@@MG~)@oVv0@rZa-48{BVg~e*(X<|LGk(evC7Q2h)xkBV`o+|_gOFmtk zEnX^KAubZl^Mu&XJWmL&ko;kBgZQ+#NqkLwL;OtqQv6Q*Q8dpBLVprEGRrGfOc$Gq zx#AgOp4eH8iG##*#Yy5c@mdns|2K-u#9PIC#QVfY#K%PQ{2%szQ{i{T55&VF-=oER z{uTo`CtU;@KSyHle?fdz+%E1E&2xW9cUa*gBHz=+{r?nsuY=)4 z(LC>maJIsY#Aae^67@QW>;%8W5^;<;QJgBy6)zL77Oxe}bAQmcLg7{7JtE)l#r$3n zUlq5DyTuR1L*ftOZ{i%BdE%Ag zLh&{d_b=`g*NE%H7sQvv?c!VF@8aKL0*<}Z7Zk%{ns}Ocy4Xl;Cbkyai5xd1+=3+~+y%-gX#IEAmVn1;diThaN#K|PamCF@g zAYLc=TC$bnJRok6d<%*DRRD4BzU3^E}Eq*M1D*hrK6XPrU zekX}l#p+^Pv4hxM>?KYin>mhoz89RU@MYp6@dk0JxI%nfd|G@#d|BKsz9qgV?h!u| zzZ4IVXh(q*-!50IELIWgi;cw=VjD3gb{9vG4KVK{P86q#7n9%N{=33gi#JJri^8{y z_e%aOS=Vtki}Q}YUh#hMQE{WVMSNAWp#I|Aw zu~6(H_7?k#BgE0-BypNJSG-KTM!a5JCf+Kp6(0~cicg6zim!+}#GT@|;`icl@h>r{ zitm3&tR|i&wj^vyR*Z_B#2(_=;y}?nw+_9d6dor|7N?7si1Wp3#OuZN;^X3T z;tS%d;&ySj_@Vfz_=RYmhlgE96h0>YDZ023#PaaOR54v_BeoaM6pO?j;@RS0ahNzt z94Af_XNi}H^Tm6_`@~1Y$HYzIi=ufRANIeY@O$DO@iXyD@q6(n@wjN7--jMtu9)jg zG<$QOJd?z^d^U-5x<(|9X)Q>Mg*cTm?YPrE2C@_8F-J(;PvDRJ7MJ0MK@l#Ra3%@AYKqxnJ+YAp7fiYqVjB^r8+lah zBo>R^#GYaw5vH2`28+YQ5#nfZyf{&uD$W$=h?j`-#jC_c;tk?rahZ6lxKdm#t`Rqo z*_bC4pAnxIw~?s#9pX;$J#jyYdiqK{C>|D%h)2ca;$LEr_XSbE$zrOQE@qPh@V*AI zk!bFVLT>Jhf^8)4M50|3i`~SYVjppUI9MDeju6fLQ|Oth@Jw-zc!{`(#66K4#Kk1~ z+cNQ168&zaxSCAH`}@RoB>LgQ;sz4!`3dnE67BbS@g)-dbE~+GL_ggj?j*Bu91-`B zsK349eiHrnEAb$SetcLwLN?QTF2UmrqhJ3eI=qjG{%zhT2l6`%?C0h_E@Rm1PNIGW z20_*fiTe1QL_L`M1t|Yf(7|%wLZZCCAW^L>lw)n=#qwK2qWo&} zd>!Rx-V22CGVlLE`AmW>ET8vDl#6+P56WXX&->v2uO$3llM2G`v#NmbH{Ai3=>4Ja zp`OBxNci1GVVGe2@1rnOnR1w@@Kh3cFH-mh5_#RKuo-tyPERQO42kmEtMGmj<#t?Q zGcKU~f^2WFFPY3%|3|nH!zj--if>P%T#FU%MxuNNC_I>KhWb@_Dv9#GLE*(D%H8x& z=r{cn<^QnaH;^a<(+?1D`T^?0v`d6dyF|U1_Jy!%U!5Fh4%-vLmyoEZ4GKR&qP})0 zypu$|?NxX`iTXRP@LyzK^q+VT`m#w>LR8^SBNWFI1zS6&f*psjGuOLz{ z_AjUK$_*hMe;FBfylEB`BqGq1&-HFDB~nf!ot1qtk%-v5UvzU;k%D5@>-uI9}=DVQuqoI(VYKFW@TO!Ux5Oea_TGND@auK=mW>_gmR3NLBHR*UKgR*DKg7h(Gy;^$H@( zeDs&SILCiQ_y6<)^)gAOp7P%HvJt1gIlXKQJC%JGczJo*R)5kE|EnLgp zO2aI-%c*Z;FTdw0Z#@5(-cw@rKJLXeCK>ca`T4wiX!~? z!IzIIeam{q5p@4w*_3^8efizWy*d7Wj@IkrO-mX*X5_4KD2B09a2zn(B_l^pA2ZwU zW4;96i!K{1nO-t^+!!1zIO_W;{wjq9lj##i&Vma#VEuQ$8c2pivboOX9z0Je`@`YV{A%NWro-XT{K}_e9Dfb*7sTKH zEgeoF{*^CI4NHG^yGOZnICU`BrZ%BXH?CZ|D8kIc{%pEY5a3kN>7f?D|S$(S&2biC=?|p>Irdxw>Mdh*!^0N7M!d|vqaH?FI?~mp5?L?T@EcR#f{SJb% z`uafMLC9DxIE60N$8|bo?b`!g#fY~*tB>n?%Ia$$2$*{=)K>+6OvmzWR!$$!^XP~D zS$#b3Evs)l^jUv#3#e3I*K+!rL0==QOz9XbDyMG_^kqX{f)0{O&KOkLz2Ktum!!@ZNIz zo++b`V~W+cqny5F(1+9Q(x0_&TRD9%mC=XGmr{LvA3Oe)j#mevZ*{3QKOKYLm(#Zm z`fUByLcFz)*VSe9@x9j-)kiAQm2EG3%IK?IMqjIP`uLvgirOFF2VYj-!7~2VEu-(8 za{8WtzNv_}Kl;I6|8n|{Kwk^UOYm18e@w^vo?T8~JzT3+q;GmTec5pVrxW(4K92EL z-|}+$mO&rW*`Kv&VKM-+bs}Ia6O# z{8@b;meWVY75U5cXJz#*hCUu^sIPe$egBlxHx>H2A>RJ1zkig|w+;Gif5YW+seSd) ze#`p%4D_+y?9b|}jdW%0+X;PkJZOo;*59t>^c{r0PF9)HF<4Yi-$CeW1Uda}jX$ez zQaOEGms62_eD8i)`%>di+K0>kQhm3S(>ECU#v|VTtiS&$r>_z8bwVQA*A9QyzNgCR zdkOj`BHsS2zK!MdjfXy4A03d`>f2pTUo#|HXO$@(gYT5nHx>F=F0>D~GfMS+k95oj zFu(T@K+`DwS^Kz-uY5X&?a!ubTtT|B`s{X51?m1_L(|Xd8(Kj+tAk1H_UsDMl|2Wv z`nXQ8ydRyECt=e)P(eDI7t`5ot{*I~&&HKa_w|37&ck@}-{`CRU#8=C1OHkgvbZcChbX>PsK3zrjee_?Z<9*!!Mqd`jr!vjb zVgI;%@<{`2Ty>-?JHD(&f7_1%n*FV>{9u0k9)jJ6TKZpvXGvg-{n{x=h^YLfxTa9$seJc0iZyB7(^Eb`^HZQVlJKu?Pop6CNlKbF~`cm=7 zJj@cK0XE0DRCXD_hU?4(p5M+ zj7xAcF-H=AO(wQ`SLgXcTtd?8&>k0bH&7T%s#zPEC%F8gD&p?MHBI~;G=lidG@g#S zH{-v=JMdq8ZzPPbm)?cawUj=_|F{+ZWn=u;B7Fq5-IwrR;tu?mbO6`WNePRvnQ&H0 zcbu;TpJEFPE{CzOyc)Ad*ohC`1tSxJk2b*W!Ao$}k{BF7?d zF|^sL!Dfx{kY}(yVl#qY;fyyk*sTsO4TBv~-lqkFkk<(Af?YL(0q8$HSQ$3d3eHDt zcCcy_OsEClhMjeS+n}v(kgp@J7wn4xrhagG4yFf#^HFSLf+w)OEm*U@<7^M|Q&DdO zd%1WxAb2ml-VtmAf8PprK<;mQ3vpH2Ea3eO)0+ppACM|1;9ZYP-`s$=43@PBcvnNX zIN;4g-7E=sU!wSy2E2=5)w*Re3kCMELVeT^_?=uwLvmvhr3i-K^cM$ckDde?F#x;M~`xtHV z?yz?*n&3TQ?{?&OZ`d1L8*{T^?`5Q18}``xZyIt~l;-V4DP5c9?ZWP<4ZXTR zm4@C*G@_{)UI3kcT87sOmQBy_jw9O{8Q#3gcwjig+l<_2;X^(U&d%`oM)`{}yg{h` zIS`_hF3#{if-7?~ykwNpybNy`R9}+eErt)5LK&RCEW_)BQo20D8;vCMGrT!ac14C4 zgtwhmdSj7o=at@>&G3SYmEHvyfr?jpSEBXAR(j{a>Mkq2zmTNsO79U=PM=r2mk`(Y z74JB7jyUA;BL^jiJgzYwdC21>)~G{XLsZV_L*5j$x-o~mA@E`BA+H6j9(Slx35sWG zm4H*}yasTa8!NHzbZ*RsWCk}Hp+IMHgP$;;#f_U#jI+5h5nASBrnu66B))8<=pra-TdNF*fl)w$9b-A$-1(nDRJ_y59mHMK!1-Q`}r4h%Cp)iB{Iic#T4P;@me}j~~4cA4C4`TW-zApfxU#f zeYflK!I&y%JMR11{cP_3u^XaVCndq%>U!OgBtn~@wO^QC)19%1dz)`CN@lf%(rw7ux6q zC$SY{C@?X@Y)qn)$Oma$3Sjz^9lV3s3YRp3?CB1w!mtzW3h&)#tsvP6*T$gYK4%3X zC;SJ79(R)!RC2;UvY$O~1)dY;8~xoEtN`Vkj>hc1WCiG8sMyCkxRo&~q%Eeyk9ROF zBdsQSnEP^v5TE6tncF*fjgct)H%1-zO({sg_y7g3c5u(80s(dZ95)OZTwIIOk_4`Q}^BnVV?!oMNL{n!fN);s8L?p`Z^TQ{>weQI?e zIgHrV!R2!=X^YX_+}#~As6TB^69m5K5TbcB;@b}1k2K;&44LkCRwE96Q1EpJHy!1d zhVJ9I-$=nY3@h&U9YR!11xGu0&md8_FOB|93h+EdxGQ_$aa*vcoZ1)(+~2JLUVKbj z{;&dgk-<*(rxgU9Fu#xB{$&NIt^1Iv`?nP&I^nGt3Eh9Jz;(jUq6XX(R*+yEInu%1 zM@PD1xO0D2b$rg;6Z1lJk&dL~dB4+<43$Vb394olaOw9UiKXbFqejTRW3lH^bG9eHqNWNn)37u*a(~C z)nzK&IgWGd=2gCix?Z5J`o6BJ)XvUXBhOof%?M3$B2*WLCvV-1Ja-ee(@wBGRnN=Z zf!M0lLWO7KRo>6YGg!p!W!(9!%MK@v>y%f8Pr#(trg4SVxZ`x8sEl#Zyvp^EENvvf3jVKt2Bq;0txUWUAPx_pJ)Y1PPJZz=Q!?U z3E~o*YW-pmOtmQjPWV#R)if*cOJii7dp$Bt+s$$xt;Y5UyVvx*5bdN@7w35&)2d+{ zB0Xvs(~Ks8I4Arf&I#SiZ5GILM`H-)TY;bFtUUJw^X$kTa*^_U z9VZ~}6?q|A!#uCe^R7Up_$6_@6rhLrj^AiCTE}me0FH-uK!dy3rigdKotr|i#0uh6 zG)t|(7R@p%@XfqB&%F;8q)lScTq84I$wpv#UWg9R%$0c_*G2k8v#Na2++DtC?y*_e zqPf=!{5)^Xb5FwoKW!&Y(A?XV=XjRWn!FILVV)1=c`K2~FPcZBptNY#TaC789+RN7 zXg1muwrC!=0$VgsT7fN^r>wv?^Zq<{3(ee$2I4*-Gpq9W^K@Q_4$#aO^1M_G%YMKx@BN+jhUR0^jaW^4zu9 zG3`V8v`=>b$T~ip7otbB`)HnbE($XIHcvNxvkG8$3R}i8E5LaMpW1hiTLBK)SWL#Sc}@T@-%01+#IXJ_+Zlx79K zX9@Z45U5T|=ZQ*UzJKcQ7Yn*-euzHPvzqx{3W_Pbl7)A=Re(DC1Sh0!Eh~U$FY*|Z zZ3Xab0xrVb+ExJ1o@F)Hu>yFuhMCp10(drs4Y-~az_ZQOAgFHz@a%W$XkZ2KY$^o} zt-$vzGv93uqthq3 z=5~~st*EM3euxgx%mMjceHavWY5pJ;4bPlkX#l}FRwJzXk|AeWiIDi0mh^Ycq%d63NW~Gy4@XN z1sJ4e@l>M33Vh%DU4f*L2!*6}3x;`|VOre{~=dmkY_ypb(wfmHy{X0!0F zvH~=|%v=brwgS}qJhqmFR)Bi1Of#>s0u;tfTD8auP#8^F$k$o{3gcJS*>zTcmT@rSlZ8dv34-zbjvw@BTy2_#HdBg0G{zxHtwBP0M8OwMXRg;p4DOF zyUPmT*~je7tF6HIY)QVm2S%s0WuICq&t8T@?mhV-`b^Ir$oFnU$%Y5<81Rr)0MFjx z5cIGWz_YWmA$Y_J;Mq(LzmHl0Jo}{{1naE;p54i=xxotH*~4tFk68gc>q~PsS^+$p z#?pD*3gFrGwBrdY@I70b?{0+AX`k{!=YDyX&Dwq{KSZDD+2(xj2tC`*hVx>+f0+~oGY_S^A;4fw+zH9~98^hSM`EFH=5@{3I#y2U8IxM7D@u2pcE}2l7#hFGcSA5Q z?E{XOUrFN+Y|`K5hnN>N{+#bMM4~XigzFxa0-o_g!4LUnsxNH{?LQ&~J=wW`%@0vE z75tU&ji-WdIKKUJs)FPB?v1qI#`=i+Lkj+b#_FEP4{;We3KFB<161%S2e)9^YWWuC)=(uMgX4%c#yc*zY(Z zx3U5lv56;it?e%Ga~B0|tN{J)4UXAoSOE?kkFy!Hw*qvVu59%ktWw{RMp3sXY)soi zbxq{R(hvf9(GXpvBZX0KJQ9VId7v(qM%`}e7vMn=z|Rr1Wsnu%0NIv;bF2Wv17D!#4v_%k73-%*)U6AT(zb9c z=_#wWb5uSTjY?LHjCy^L$glCyQsAK|O^sh5folBxs5^@qyRy5EkjA^%OfQUvm>2z= z9`){_Msw$XrW9~|d6soCM}h#VA2v>oy023sKPc}`mBtJnDCR~(%!?YYh+cva7 z3fP8BleyYfrfo6{t-v;!Yiypj$t7+1lTCs1td{Kei){+q%9dCGyhx3>mqy)<(3G}>>MoCFzRW;l*3EySq1O>`k{`o= z6r0=gK^$YSoy_w2@T3ssac9(9R)8|SpX1nlR)8YBol5Vwg^VKHSr3ABR)FF|#oiWmSHs3M zzRA+PLlwJ%2_KAx=ngCP@u>Ga9XW$t|4Ew#yn=%DQTKByXw4z&F)28}cK>uVMAcOA zQq)VqpdHSJLigp93c@Qm%5AlRpwakz)NPH#X?)q3`+_vS%0~HGG{n59@$INLjT-x- z+q=7@04plO58^=LzAFKaW#K72d)X~PLI7E$yKh9@TbRYibrH8Cnt2}s%ULV$M?()G z;MXz5rj9+wq)(<@n@$RG=W}1ws{|$CzO?VNXw4niHz82V2@j!QzZIPBggeDS@VOOa zIblA8?S5ee7};^J`J zx>Kp31&<7eRCvYg2tP$bR80lPquvcv5MZnR(<)%m;5J9peT)jK;Xn5`DL9?Y@$YDe zs;R&&@QTq!!tb(dlL}7WF<42Hf>wZ*U5CxWvjVj2I=K*3vI4a15o}Z;D?rQsmGz!% z1!&ppnM+E6IyM^eL#(N=75EJ~P~c90NohCmd@H`dKQs?vpQut0qDQp5dVyI_5T3~5 ztzol3j~vS0R8xXDm^lf(+0C*kV5YfNtff2?(9nK>O1HLBB;Xi!Jui>y+g<$9tXkln zpjBadogu4+a?geZA=*o;atgd=D7SDfjc8d$BOe2BTUm|qrhb|fxP6g0?I;sBlg9n* zMr{g0%!?ZH3%tvy5wp>bTVNHy&$ro>Iu`f`Z}`a?Z&%>nOO02uP&!ECt#qbSL5O)# zW7h)jXKL(Cd3S3g%H0i7u47VaRN`IKBikEtN<;fB|H5nE8sAa;0`Kq=Q4{9 z7%|+z1sU8s?Rgwd-LVBBX3i`o6?oqzqi0!iRKf2gk$AeTecWHTeHsYvjPmBl{n0=vx1s9+Oe@dUKAE3kBY6#D`yVA%DqQ1xHq}eQ&V>IMRfL`id2xp}o%n+G+)8XmwZz zuUP>a+GM8KX01Ybw`UD*w*q+9KN*5ItpJ{Vk_5pHD}ZO!Q7i7-R^WT~Y=L_Rj85ZG z!QCX!&SAUXSrDSnSR*GVDYB=vXu1ow6SVl8oOa?WEDc`5l(1kMmTd=Gs3yR>ZBiK+68{v zdJ)czHHvWRsY!&BLCqqZYsral_M=6Fa|x}|^Vl(d@bhXD;eGluBD|;FKEnIIc@f?# zjYfF)vSWld2RlW0o2)RMFS>K*!pqLV5nel<8{q}uun4cw&X4fAYDD^LY|_!F$!TPSmnfst zcTv{OmyM0^s$+cm`lgT#^JN!Ac+NjD!t?aWksGtIoGbkR_gNOL!;-!-{U?T&N9*u~ zwpXR|HMQ<7(K)`^NMLLytt$E<}naB0R<0 zn*J~vhx@Fb;S2FHIG>tEMNeE=}WTI1``u&uq6__$A3}kZYUvVIl z$Hp#!Odim>1u}UQ>Jg~Ekx2&>n9JmzflMAJMg%fBmX8i(a_}4<$mD2sL7@6(CS6&O zwhpB-F_6g-$4SU!f5lNdnXlAkd71OP1WfT_+bpBG*9zA-iA%BVQV{x#o$=j*c=jCk z5lApFjx6+A;1tDQSTnltEz6&@at8nsHWuereXxjJE>Msn)GO79UNp0-R=; zg*6vg0g4iX>-mN5KxF8zqZv`?57%ZL&BVgci!h2-%_#Jy(JHf!W|kD_LU>A{dkYnq zbu`nYz^tR0Qy8LZD!9DR`;7|BI+`mA{nM|~bu?E>P`ZxhDl33nW*yB!E5P-gSx2+T z>VSTDF|W|AkwY(dJh`;6%sQGI3PUuHMl3D#+98p@j%K;lh)RHhn+x4xRAAQ8ERh1U zj%Gz+h^nbz71l-NLV;OFvswyD*U{W#3l^1Q*3sN+1@OYGqgi7G@WQO4S!)HT9J7w* zek;Ji^*&_kuCoGMrJ8j#4_E;%N6b2!2dyB%IC6WTTOT(1>u6T0I?Otn4TT}PNJpM2 z^g7cKvySFDDNubrQRt4P0<(_hDJgiGwme@LqG}$bUN5YCB^9jUS;h9k>>Us%WaB@a zEWJ|b-A@H(jmxWr<~%5E0jzU(6o#pq<-M!0@(w043vqTAmRX4NUSa7%oKFg?{DMUO zLY#etbys6wEyVe>@Z>_A4+|@&wtz0P5a%ObS5<1KrSBAa4G|fkNlt|7%yN<~g>Dq$ zs`R2N_h#Bdg_Q?m)A#D|sa_o@^e#o5zc}Wgyz18kUj0}YrYd@Mw6O9$Ok`H@{3fr= z3Z7#pz51uH%6263SMWGR^2)5>2^5|5>W{+82dK-e;Q32lQ9CXDxzPI?n-QAiM5xYq z^;Mx8X$gnuMOE(2w3Ul0=RoLt6)rlZuDl|zKjQpVHK8KEt`4KuyH$$9R7J0<6;+R7ML(x19zysBAL`FZLxOMg!HbycNyTAE(u z?Z#$=COHwRGhQVXxd*Xbm0nck-fY6ni@YJN;FVeOlUw8ulw8eWmi)AopmfPkYb&tJ zJK9Q6y5y&wO@VtkX30-`EAUI9aglo&GW3`HG%fN6O0(prLs5wK(W*{G-dnV47!C|> zVUa)1l`i>-Nl?1vr>o5Zd733Z-K@aRGg{>S%skDKpN`7YEcxkP6rwfEvu}|%v$ZXW z{!+k_Fl(I#T8-B6b0jET*D~0q!1a|`@-xH=?7EhrR$z-}m=*YD_9}93g9ZMQpWZU_ zm24Ejc|{>QKr=@dc?W5xDVnk6i)KRkqPfs!VT)#>75I6MC~_;eL7ryG&q(EImi$aA z3eg(oIkU*S8HxNxGFu8ti)N11Xp3g91f@kY&!(_NbBPt$qPffpY|&h91-_Y6i`*w@ zrdjecU1pjkKl6)1bbw}FQ{=_BwMBDn`J%a@e9_!wv#>>TvlaMxE+}#vL7l(k=W69? zmi#O(3eg(oxuVG1#5~QCpWCeh9Cpl-pF6AohaI!zXQdV3uw$0|+-U{4OgBq@R#^ec z$}IW0%L?q0pVd|XyUmiHyRE>tdufropLUxiKg(seS@LsFQHUPV?gxsz zML|zm0bDhUf}XYlcxDy_J!1vFXKRbx=U}wIDCmB9W)=lKTNI+t^lVF!_W?cY$}8Ac zq@Yrw8G<(#xqniDS$p%M6#Nj6gs&EbsG16P6nPo#px}8I^0!Y_u&v0ABFpbp zBrHJyr;27JNvai~-I|poRjdGZo0TLHD?pz$D@oF9E^x%GBuTddG-R`qq^cFzl_b@y z04>|BB+0M>-}l5~cNyIBSCRya{iC8;Ns?I{VyV#gTE$-XJos)_lGL^eP(@}XNnI;I zpEWB<>RAEWiCIZf-wIF|W+h2OD}e82B}pSIfbV7{NfRr8t7auhQ!C)`l!Er%+zQ~C zSxJ&(1-@rBim@yho|%;-S@O)RB*`rf(Pw(ruGqVdo*l<^zS}_x)Mr~4yX&dIEZAr( z1+5}Tm|q;CYAPr!_THp|*LV-A_*4ZQi?QYo3e38QPEznP_H(-whp3tgdKG)g`A{$& zSHEuWQx$YCc3UFOUw&|w6l4dGuy1jQs;OWw8YUH(0W%MXUxLP05+8kpi>YV0Lkcs%g??#ohoaSdb0H z^QEA4wZWBEfW&ZeZn1kYHJa51mq?>oZE#g_hGGnc&6j*=K{%<_X> zR)EpQEI)YH?gGcn@`K%0fZ@k1KX~5?Fxq^aja)vkIxyOpspAiA3Jk1ffx;duK*ur* z6h5-M_`bhZ?0yfo`~?czJw z*cv=!1#rYHIQY&AFpio92ZyZy#}KpN;0Fofd^7i>|HA@*!NC_Y(=0gnu{cBrSVg~~ z|I^GvHBdCirGTC7W)50^O5kE(;?WfSpBkrCLEKSk{HP`Zf202+h8h!MURo#Hj1pu1 z@tK2`S;A0B0yQHi=C(&-e+ffe%s)n%B@C5gA?8Jm=`n8%HJT+1)ufMU8c1UZ2jkVb+&|(j^RyVw!`r&8~?R*k;$<=4qQ<3oAfv znI#OZtpK%UmN2xn0+fVlhwZIW+Ya+=3baGBgdu8E*miiP6~GHDVW<^zXTb}92}A8z znI#OJVfScoxBGP665Kh3Bk%b_tZy%1TNiR|;OmpG9{lR78nc0imzkv&A!WhSym#6ncV z>KYgG22z2U$iBcT2p9#UV(wfjFcaBhq`*vMPmG1AnhIvdyvjvTU?#F>TLn1FF%#Jr zSpiN&%|!MbE3gyU7h3_&0nJ4ATq{8TH51wMtN?AsOk`hb>k2KxOk`hX1^#8j)R@}} zCixTD(`C1r$etey(IeWuDCXTuyUj%Qbv6swZ6>m>m!Nba`v#lBo~quYJWD6C7b`{S zMD{Yfi(i^o#oTSQ%1mT0lvP7vjC)HgM0;t~oiXoMT4g4(SC`RfCbI9g8skm<+!k|B zD~3ihk$s0Wnu+XtVbz)v%g{YdPTiR}Ag?nG)d6WQye(M)8o zkA;{QH9i&dHc_LQ$bQD!h;lI#*_*5Y2L&^c{k+W+ozYBWzi0(ehi1Al=I&>nW+M9u z_Ak4AhP^PWJWYW@2T#9~jY5qW;idAd(e z=2@*zF%~Xxk4*isbmi1MKZv;>G0)>PaF6or%6qF{#zM4)HwO>Lyo@ez+|1zr z7^|@h;*&G@KUo2~hMB=XY6Tnu65MZMZWMd_Gx*=e%FN&&i-njuv-l_GJ;E%^41SQ(?F%nW|bF1nt@s9|RCv#cP| zw8NAx?s#PA&)}za@sF2g2ESI95bdQ^4Z3*CX_cA5Z)6p~Dl>!M*a~o^g_d2Xi~Afk zni>3h(r9Mzn|28?FDGMSz#UfTwd{c#znlPbBAjrFi*VK`A;M{!#0ckJG(EhrP}9Sl z#?bWe3%*R#!!H(UdYE_r(<8iFo*CiY<(d)RH_ndmKCPyQ&nhx$>qU4UwNZq(DVs!i zhmK!5!UqZ-s1G9P>dtf%>vbZ#p#bBq-o+${kX9ao;;3^@Z9Wz z2+yY`M#kX($q}BnO!cRai(;A{Hj~B0u{zf!l}-=GVs$#B!WR2e$6aD|h9a~k!bAT~ zf691ZEUg6Rcwc4m*o-M#9$_(MYo?AT$I_Z34pX)~Y+}mROd($xvs1P_C}GN$M*&RP za_GjCEyr6-*_xThAV^Y6Bbu-cYbu5i9h8YmZFA^27X_6V-Q-N$$*-i2BjwzT$36D{;4W4Y}L(xI2m0bTq_%iId`A_cU~Oc;d|d2yY5WoHb}5X}Zdays;cg$}zJwFpjqZv!g4~6@6R(YLh=`<@PA0uE z zWAD_&b*V=X$oeW75f7%kgtSi9&q$p3kO?GYeOU#8hfN@u)f62*@evb9cH%2lLg>-> zN1@>Kgv95)**)=&soE&y#Fy)^I0A7Aakbt;Atkw1SO^mCYv2HR)-bpWc*D-GtL2FflaLk6~do zV7G3t2`Ztey-h>&O&SP?St0HAcVy8aW}1z;t2AaUwh+UXo=9okgzNEtC>^DlI4Tf7 zl9q0Oq~UCg4atdP1F3%^l>SjV5r3sHj8aSpe9{H0V8GN1%aAO7=*&jVCa%W z2rmr8zl=a)pf@v0G5@cHf<}Y-I7tms=~?{6jZo!hRH=o?_?p-$DX(s!NjQnI_n-+S zomqE)kvxai5&skNPU@UF7LuA-HF3C0Do%wuCu>y#BDzGHAi~L-SPy}&5k@3rjbxyk zX?nq|R5XC3?xs5=XZ?|iKo1j0&FYYXz*&*%P>`OL$835=XkunoG4e_3lS0#LW*u-5 z=xYL}H=Z!nN$Qt!Ga|CH7SsCvCZbMO0Xjv}028Q}Rm{LZ6KIh2Ifj&^A(gpLqpV9A zbFK+A&f=o6q@lIbU_i61%PJu-%mi9Q7Ql}-PJBBw?4-iXkqFgI7?1y(T#El1nEz;8 z1OA677EbMir1RXhh;BMzDvTUnts8`O-bXJ?D#W!AxGo-)8*faJXLB4@$99ZlF(~MQ)%k|LYew6Q?RD zcxNeMYx}YBzXbZ2c&9}h#N36LeC^i`az;BXd9ZpIF|BCLv)F*zlRG-i{zh{P@X>v~ z=!*8kW-A9 z-yt37$DklpW~d9Z%M|U>)|OeTVTk#6QMJy7xBLs%2~=t`4DF78-j2l9=iy+=zu>62 zO06G5tKwgD`OR_uhQDBOpi=8us6YM%a}o18oZ?@wK9v2AB>eMUNNl|f<);oHF4zb=*TnJ3GaD}2g4sZIhNRc^^(F@b-P5=W z9+2&xmWy3d(gL9nR3QQ7;mW=pCVePWIg}jYr@2!zPDxb-se=Aav@KE@%9t#z?A{nS z$_5!8Y!v8g=-r-e~&IIlZdW*CanP%y?56d^sy z(q5)SnfdARRPnXS#-B7ITeg|qPKs-*0JL+RvO8n&ph5JkUIVnf`c(rBtNX>=z%>px zEHzHW+z6(#08K7<+i}@UX=@XzpchTc#-N|(1kS8(8%o3KRRWR3PMIqTP15FWnI;sM z@pK_tSkARq2GH`QRS^wV&wor&l}aK!W@xYY@N$bg8M%|1jI{P}6H@vk38!GP13u(|ZT>trr{nTyrX z_pb80duH!G1c%p(v+)!4Et}}yn#yZFHC%ClVi=>p1V(fgD8UifH-uYF{Rn~suphy# zGfcz)BHwKGB{(+wX}HzHL<}H!*hD!I9E|-m+!|ye1`tEdW*>sXvY&=q<|uQ@Cqy9h ze`U(w8s7J=lZN-D;oP0dPL>)Sh%*Wj%>Vq4srX|>@W)y!`}^PG*FjCZb5lID2L4RJ zt0MhZHRBK%$jQl_UXnX@#?;&y(?{h_AI?t%jx3omVU!8`UsZE*$4{9wCbwkbm^ryQ z_-0he#M~Lojzvrm>DHAa>um7m$+t)o-ieM=9DQD@x`_YlV{|P8#QWp$@EFN zEn5t4J-k(mRxO9OY(Zgj2%AryGI>n%F(o4>G;i4=r*(5i=OFr&sN4yYM@^hHdQ9%5 zl2PON)v5o_X3V&FMp+ZajnC~oee|pelcy9-nLeg@X<5v{H}6;^eu?y%KIMWjqh`*? z?LW0-`h{I)O&&e~zKrWLan_9C{W_n~tF0}5IQ#!rdv3|p3Aw0l{9{#*M3s-4G-JYy z++y>^yWD=Uvt#``_s{L_m-_#EW1Rn{?XeO3cL||w{6!|Y<2U1}cu_XLUYIiqUE3Kx zdd%38Srcat=f~V;V;?Z?GFkjL*q-tHk%qL1cWhXkz?XId1#J`1(jt zm9b&QPRnsSCdN;VLe`7I|HIy!heuJRegDzK@RkxQ(KY`@SnW;I1={``~~JxMsxV_q|VjPgNyk z=9%kypXd6$f4qG`K2@hqo#j6JsjB-PERIViX81b}l+%6X^w5c>&%ZBrntVPt1>YM; zLVuM6pC6H08N)LscJr|b-v4bPgDQ$bi6Vsn{Kp(9=^NZLeMo&D@mV4nTY}s=sXP$z z#gYxFXd;n{*Ub&r#4A(bL{(F5w64+67iy!)WVkAtYOJqM)zsHjITs?0$tK(usjqFQ zi8jJRQ(YXF8{!So11h4m4MsyvX{0exQ<_@n-V;t#rt0b&abGf;XpB}mR}N{2R;8Ni zl1&W_^>QKA5T75dNyX|Dwc$o%ZbefvT4yxH618Jv}QNmZbZ;W1ITqQ+C;(Z*^7+EBefs$YE~RTHn9?WA&E zJQh!d8&p+^)YsKTBNCTXt*NSNN##s7MIxx1&ON%K&S{D^MN=_I$EayQD((BGiwL8J zNUN^GTO}L9iFl(cT&d=@;kpGZR5y54iplze2&yh>66#Z{4tB}-6W8_)(4sYY~7 z280Mxjvb3z+fyCOj&C(8BGpwrDg>%vDH>G@jHR6L>gPsk>+766MZ$Fm69rHkZ&VQ{ zqG8m8WW1`*h(sFP>R6wQq>_#GkaHAOx6T%|ni-^|OpST*y2|K$LkXd-0>!GEw`#?e z@o*I?LtQdbGdookj@KE? zq^_~nQ-mmr%7$bj5-qXoE|Me?wCh}DbS`QeoK|!!S=!pX$Y@-E$#+8~GKaQkB<4lE zLW;)|v2ZFHiKI#^Q1il#jge{t3RW5_jd?ZEx~j%%C$YNeNDn047Avt+Sj~$TwJU+4 z5jc*n7~$$Phe$Q##P-m$ZYSoWOGwqvjV59>_49hho~WyGx?9w~aINd1ram$o*TRv; z_*{?prKe4zE;t>m>S2_??5?J=K`M3$`bm)w#0NR5%cas>qQ+6J#~r(>eUTH9lw&XH ztC?Njgz7Ut5{*`(y~*ShgJ|=j_EPB->gOgRi7;Z3f-1Aylj?WS(kg2c4NXQWh51?M zGM{r z%7&(7qD;Ct9lC0h(fWAzHmTAik!WvjS0f#}-GuCtu74U7?PIbmq2txrVRN1&ULt{Um8h*wE}6G1ylII&B+LjR`QNo5$Zi3Cekryh@E zv7-~pfg};FiK@XzyR+IRBhgg23H@eWV>}XWjH9Eli$axgvI)bVL@aLTHCSL3B~I|F zSCx8{(u1~hiM?Aa6^=xj65$AYWfhiPg>+h~A)t9-WWF(88%1@|eTowl6RY#9hB?O) z`oh)~Z7F4uSBD4rr_c}VUF&rKn3h!4sVND{AexvPt;E)*zT4aH**&tpqHm9(G1Vs) zq+&JUWVO+j!erc#Q5Ta38D?uEPFPGh#v2TZO>Xn6EUV-gg*kg=G$A7<8bc&p!pebK zgb<~Qis+|zAN@t#dT6StPc}LtRf4kvs;(t5e8!Z(=2k|~$4YSfI|H6f)1-aY#}FXu zpF3!|op>ZtpQ=VjZ0Lr_Nm!Yu)o96}0Ff1^w|4rww)RzRt?ix5T077losv7YeOYH~ zN}0IVB926BYMN@o2{fsycoI!rs-$i=+LJUnHDI6>+jX;41Z1E$sY7u%v9_7j0PccJwP=- zr%D;CS9+&Q+I_M#d{ybDI7j;%6|qFrIX%Ewxq3xvAr|UKbvTaG?Wj;ODrzd68s^m2 zi0bIs%}Z*^>`DU}MO9r=GdV3n)oz_>K(~HLdR}z>P7I!&0;5knhI)@~%xH?t=Exd} zx!sslO>b8x36Xx&DHE)^Jbk%6u|i+tnJ(E~t3885uc$gV4is*`<5tg_dW<`eC~8Z% zE)q35us+liB}C?A12e@`Ln5a7bv>I=wMLglnNeNWP|;ZLcHFu<(n9l016A2zvAKF> zXKF?B8mEw^vVp0Yp_(O&1XRC_q_tx|MNbEug!MWFa(X=E3ccCvs4aCFJk)@P@zEY- z&D_x&k9aEU)u^1BTVKw6_G}}GMq6VqG^W@A*+Z0+oXn{(kH#47 zX<40XFdvoWc58b(I-Mva!)|DreZQpX03}{~056@2Qm>p_fr?ck!oq^kO^HnCWspNp z+S<9g&5;a;xmt`|7>K05R;3q11xr>#6uMkIH55VDH(?5h;ixWF6OUjl!8}=sNc9nD z3QB&?y>@L&L?cm5kMy$3(~8gqL&VOU1CxhnxDiX*Xc*IMiODH?cLZ@dF}5q6&Uj5t zv?`3T$z4O%pxP!4ELpH_LOjkwi^bYwA!o0rtHQOlh@A^9HBT$)R_&F^cpa%MCe)M= z>x%>u+t95!Lg1a)%<4$VTn>@Kw_21TDKa&RV8~bVKfh=U1+N!#yg2?pgutqm=^2E{t*)=SgRyL)e2nOq0n>$*^6%?;%Xzd*flPANWbLr|83&F+9S2cGQW6N!f$cxA18y={Ip@aGW7TdegqT{`vb^Qrf0_J0wcQoo6tkbBAtU`tocbSS#ID$^70_!(DOK^HvTX?DqY)r^Zv37n# zQcXkLF+qA>X^!zKJ+Pu9NJ>rOIH>&FJ0eM}_rkOFyxge7y33t4>GY`~0eug)=T^E4 z5E*)$5v>+OR7L%KC-3^!NDXE?n2^dUU;3yL)kkRoB$8pQc2##G(+)KT8P$za5O`8w z+Iu%piLMXpD>Zknh$gW`P>K!_ot<<%I%HS&vV=>q08|pDs#$~MkvlPZio@L;=^La$ zmSWpU_N5%}vW`=0ZF~GjM_jKDV+Cke@=P^wT5y^vs-V#>4xqxF^{54 zt*?7+;6du~z$``hyr zdp;3yww)lrWFsQQ)Ji2%m6n>g&aJGKRX%%ic!50rqmAgjHkBPI+CrDbklR%*U$t^c zfir~@la1J2?rdM~X3xD##%Jll)y&8V)hQcHu^UkD^bj0IL#cJAM6#WO(b4WNuxjmG z-C@Xj29asuB8T?IlRZc`U>=598ioTm6zTL4N=NIG6|G3CP6Xzz*jB)HSB)Aw_4L&l z(A4f5M>W;%F<{Dq4ku6QOPmSXTAiaVwP($;pu0k}AWVg_d47bnj?tN~7~-j|g?N#;D$V^VpuzHPwaZ zqQ8(GF4ZE{UUL*v{Ah&{#q>Fma4NT(3^m=x+8mp@s_FM8QOCFH{bhw*Unl*p>R3wu z?bR}s61z@FNhG)-nkXq%SJdoY9Zj*@k9XdyH$R*hk_~aG*|IB%{g1i|nLJAGivcFl z5W!ZfEc6ZRkS6W+S8cCjQT*MrW!DgUhX&0-=GW*&a4&qy4r0_@+^uY1bez2`Z^w2U zHhqpx$!WdktFbt`NuKq|PkHzPs@?)b9{f`@ijA1?3 zHEOwsZfI^&dV9=&TURzOT;6S`)~)2K_b%ztd+SBKcNv7fRCVI+Oo}o=^}!aUYQ?hn zW&4}#&bQSeQX(66?%hrShAY%l5G4YcS3(+)i|l6NNOu<=`6r@{7)RP$+gh8^T2Y9u zC%0ph!Ay5+B3m_o;SZyi4#;^4_gJQ7#alZG(5 zd40*AL8)dZV+kHs)XGyBdytl(_E(Xsd8%7&(Rt}rj@`>S;pwi5-J`u1tkx$Im~6eo z5_Pq#F={=>2N6;ME2}W-yM3ZNs(7B~giaO(=0)o7vE+u^hB(FxT~t2b~<5dP_r1B4~ZHcZ&oM z{^AjI?ii8n)x6^?iQP-=5_9WUOV-}`MjkxxV*F3N2vOO(a5d^G=a=qCEnA4*rxv<; zi1_TMsP3?U85SziJk%S{eyJ8lQ-icD*(a7AQ+pc8d7$TsjMF_uViEhHguY# z1?c?;y=;*>r?yW#Q+W4bDV~r!4@+xG>!MZlnBt)C@H8vWV{hFWWWQED?~;b>R(n(} zw-ZUuQ9{7ZGiLkxfw+-W&j8$k#Cd9qCWKnAGqTsiDZSr8sY?cA-8Hwe5|O%1LG49y ztHj=1sK&!jwYea2C{vSu9f@av>NeSyY^X(!q{67E<(`!NlnSOU5Z0o4Tuve=~Ch;K?CVDbtI*E2hDktBRyeze) z7i~<$Yvp0KOb^wQ5qF(lYEM1Yg3Z0|?q`>}8``D&yB?;xhX*KWPPV7DP7KrC;aV+6 z>f{X#&$BjpZ9;cn&cg#)ilt=zkCK-`RE_&lZ?o-f>LRrx(d2myf*C*aECH#NhUZDU z`<&J;oQU^PA*-T{2u{^kb8+=FoE?T*Glww=sF8O*42;G0j-r~jc|BrX?-r6h4(nb| z7GS7+vgYNEQwuiB+Eeo6t97MaL)E^kBj_@>(8@|(*E09eEwwVY)XLmaE1T*TirSwI z%M)<*5Z%D0Zwp3bRkhU+>D>))Z?u0A(b>Sl5v#LG%+NirBj}6LcDc1EtzW`+ zUVTVZqvgaagUzjlP0XYbR1YSg=g~} z4J?9Chw!{k9=o`aczU{Sj|lK2ZKb!GtCumH&e`)0K~#zixt67m9k{$9QLA?IorEwJ zd4V8?9!$?hqVwbOw6Gd;7I!1heJi3&-ip9;^;UPvr+Py)X*J&#(IwC-d+QZF&u84n zg8G#!x6*ktf@cHBhb&c`bgMzbyCTz)pIVldA0$p&G`@ z?7cc%S2x4q3T`HM7li%2sdCkJs)q0sm3RrsQnfO zW+SrIgE@*0(UU7%hIa3xFKaPLwZ|)UdQ8{Pgq>hiM;;5yOd7B1$b4O;&EBhE%ks22 z9jp#dM<+8y4p1T|YzWujojvdD0sVw{zy^lu16C~cEJIYCM2GLBDpFgiH?OLb@umh$ zZAA2vv=X&?lq0nv>)FXr`xo7wQmb&?SMKy0)E-F6oY-`xYza!xvT=u8%i%QDbL#mf zI)5pYmW7_wyYpwfm!{vM(t?qKSE~bh@ua#~^7>*j8AOf|e&yJkE+h4{P9!WdIqW>l!v>CeGZs1UOd8#`Wkf1v zZvqA9&SstdH6~j{RS9`%wnvTVwh1OJ$?Y)gZmC5^5cSk?^&P8i>-wA+ZPjap82<6`=|Pfjtw$>g+U`Kpdq zBPs8Gs)d}I2YXr$3#7*jcRGBQgU*z*k7SSRYVw9xrL=D~?WprC9i;B{6mCPxdEZQm zRX-7N!?5epy!ym!E(uk&mbQ;Qa#me;WXHaS-T}1}r2~rLHB4EU>37zZ^wc|!&N~(E z#sHtAx|3(4DiSF#D3a&p;r0~;(G?3@7cIh@*Nyt~9Q6oYe|9tOUq4Wnj}x-+{}=r5 z!QBbjS$))3Y2q$F`RXW|9ax`swy);pr?T~NG$<#LP!$;=Raojq{E;u2(!pNx2ZetwUoouKYQA1eCswMf5iF7B6G;_Npv zdR)h+Bc7ih--C3&U%n4{rT0Gimr=aj4gS7egogD zdwzZcUtD^Aeq*5LOu`?m?hq+S9q5Pr%V%x+hYy9-cX!@%`J7JwxNF(=k|u~)UMaQ z%bghM*}BtfI+vV%h@LNlsQH|?qjqj_AC2wpw08u~q|8mW=f%nH>E?!j6RdNu6RaU$ zY6ejiW(lD`U^F-!RYl5vIKIV|?^K6F8%hm1UpN$>d<*x%C)!|egkcoOIsTLg;a@&U z9bO16Mnd{eL&t-EhS;B%4{U`}ONF?_NJACJEk+s&PvRGMe66lHgOu>Zy^3ri<+Dw3 zZzflf$B;_ALN(hx8xqu=d;7hB>RwgI@{k^<)!y7}-oNAy<$cq#*KE$P3De1LqMe2)Ax`35OUs^z|q$(`g^s8hJ1oBWuY<@-T8Cxr}Thk0nncH;`wM=aZL_zb9`Z|49Cce3*QSe35*Ge4Biq z6qUy!FVSc({FeNY^kcXd_aNDq%qK^X`;x`v6mkYxLB`1javpgE*-9=aJ4i9MD(P59 zo=%=aUPN9=UPp>6kbfrMB0nH^kYAHOk|qW) z$#*t6h%6w-k!9ozvXZPN=aMOMDS0$`Jb5a47I`80JMu>I4)T8T3GzkqHS%5Z@8p-H z7zL7i`S97YFi7T+!^kn@MDhS~7I_GHJNYR2v%Ze$tb{K*iG;_Je025vV;ti z39^OkBsY*3kvEc0l3U47NvPUZ>FP_4Bd3yezTG_?DmOO%7MV?7sLf%0>PQF5ZM1Dh>SUyU)1Ie-E zG*T1@$@NyUojilQoV=BMn0%RhkK9H2`rG04BS(=3lQrZbay9uI@?!EP@_zCK@-O6P zBxU5%~>i zVl6E34J5~s)5th^D0vil0(l8}J^3*CGWj04hZF4>B5x(1 zB3~y(38RGbGdXaWeO^W$OwJ=a$hG7p~fP9hsEBQHTVGl#nKaiYA9!wraE+yBJ=aRRP z50D>`-;ibj!zag*)5th^D0vil0(l8}J^3N|HJM&$hd+Sampp(JrLdB}1>~>D-;n2% zw~)`0uaTdTKaqn++Tra>9z@oYN0KLy8_8$LH_1=Qf06@6+2M{P%gMQ93n^xRB|jIF z*O3pAFOh#Eza(XYOYZASjwC0O^`xjy7k{1P2J#~EM)E%LdGZtTD>6974reHN09i>M zPOcy~k{6M;laG>H$q&e%$l$(qJR`};WF>hdxq{q4UPRtV-baeYV#)tIa4{Y7>>{mC)pRB{=4Jb5O0BY8Kug?yL%g8YTd9cRZ= zNS2WivXN{h*O6zFPm^zx+sVBB>~N#xiR2&2?c^RZXT0ry5;>EcO)el;kiRC+A+IFw zB%dbVCch;^6YO}VlFj7pTm#iS`$tC0(awB;ec?Z^_HZ&E%ux zo8%|t&tz4J9Zw6{MxIVyNZv+1NWMnyQ)=Hoos5x3kVlcHlIM~)lV6kRWp+3N$ZB#C zc{I6^yo|hse29FD{Dl08%${tAUqXh-7V>2BEb=t>g#fS7i47cKAcd$z&zjL@p+eB~K?WC2uC5AzvkTl0TAtrrPlhCnu4! z$T{RfvV&YtUQOOcK23f=enDm&V8=6(oJ3ZUEo2*cI(aF1Gx;F-CiyY>BiUyf^FvM| zXOVNrh2%-(ndG(P-Q?5c8{~Gfi?pWO@eLuzlLwNuQ zZpSx}97|3k8_8z!IPyaB8u9`14e}#$4>@Rt9nWa;K(dxRf;^r)jl7DygWN*CP3|W9 z97ws5Wn_d*k;}>Tw;E?c{^xtK`R|QE7+Y zha5vrCGnD}8h=vcvE=FGrR2@zGvuq}PVz^xPt*=?I5~;L`%o&L`Q$qCQF06UG5IZ- z5wq_bNlqfG$ob?l@_6!0@(S`k@@ev2@(c18GPlZ(uaGPw@n(}s|6ybYxt_e5yp8;r z>>@L&?fc8fMdTIa%Vb8}_Sc^rN!F2vlfNR@kY|xMk&lr7ATtiJ!)+!{AlH!_$;-*# zlQ)vLk$01ik*|<%k$)pUA$ODh*>?OEnL`dBhml2OIXR20B9mk*c@%jxxrSU%UPN9& zUQ7Owe29FWe1rUm+)ZZG*y$fgP9xkoayv)z5ik3)x1VM4m-nM&3mJiF}HDg?yj9v(66xNpc(c9{D+$R&Vc5y;XF^iO!v2W{x12U5ce4gn?uM^@>KFP@?7#l@(S{5@<#F&@@evUax3{7`8V=I z@*m{qq~C{ppuS|1*C8e|UX-y@Z9^5q?g=&|VFi%k9Le)VLWE~b>^N>k zXERg`b#%7dT&ju8H<>^TLJgt;g8m+AdHS={;@6N0LignJnAK-Y(0cod177M z-n;^y!in06&7Ga?%NDNgM6mz)Zz#N?nyE6DyQat=&kt2W{R;6{{GsU7uctq`Ccm-x zFXjK=`IA1aXS_$kP5-1W$!`MwOHt3lfBAii&IsEN%Dk5Nk^d53E&hAMy8!1>|MX9X z7l(s4yn^%W`=t+-dalEhKGGZB)i}qr*ZJx27Q@9GUJ=48f}4aV>C)kyhGQ)w92%eE ze@0S{?4Q0SeXlpX286e1j2&JO*K~O2<5=G#A$)i5PIzzQSl@#~<97(}R$W-0Yp>(j8{SrgC;gg) zmxup4eV^c1!jrhj0O|6Qc^cg}BZ6F6{IKke@)oXN5N{T2Ss(kGx! z>OXPpP2Z=U{0^c&sb4_^hPKv*L-kvFHmum{6Hvz`^c1^s9sJ37A?<$v{!6^M_%Ctl zwu?jKsZEA4N(X{-eJC>b`pbV1veOqm{w7T+EiLf;N)ITRI<2H^T3JZ}K8z{BHRtct zsZ$CH%1WnCnWp?789X^!6SIx!AV3vnkrTh1-#SPB8m8SB6`||~8`JLj@@xO8{SL{U zaoFZW*Qkcvnw!@A^8L@hT+r1}@|Kal^GW}I9l37U&1>>wg_YVpaENd6Up8N}$KUUj zK-$hz(yrZE;a?B`(;hY+RWabtOIx;VnSim#E}wK?KL{@C6_mt2$aI7D1*Z8jjwyg_ zz8;K}jn9|9D$N&Iz7LRQ${Qj6PL!KDU5wnpDf2;iPD{sVhbtT5%d8)~T&|>N9x)6E zn14sJPYYyrpm$17H$~qLt{sG;^G`)X%E-@?F48aW#AJ-_AH%VEIsRnGAOC^4DWjzS zkvPsgNB*RrE`Midmtfcp_z|5EI0AS20!vZwX@NNY`UCe3L{tHJ8^8=ik&TSN*h1VD z_&6Kh1JMzvC4pDbDFg!*NLwgS0J&rZ)?tRwC-6FQk{x&!Da#2wjo5Pog=kKF1CRB` zcO!vgaaUg85Hzy>fx&PY5O@s<85p<&_YMj?jlcPUa|`eVLI76Aj3I$^+&eTN?{y3d zY(-qd19#wfMBqM%rXX+^q*)kP2yu=KT!7F<1?D35(Sc4B(wKlB)9FQlzvH+yuo2>V zE-(!Z{P{pOj$a5ogsi_9_yppVbcytjlM8gmyVU z&62l5A4;=MLtvl!t*yxKKm69o$ovk!brtU0>9>~Q+Gl>N4n9BkTXW&~h2Q!D!{C>G zYXq{g%WpM9qPzW87Q|bVZtVhU)2*X$LtVNRKuxGmw`L&^4e3@1n)sY_Yd(rTk#1d# z+mq>5EyUTFZheh9(3EbSfE(tfTc6?fdFhr9H_T7BhM<-#NVnD_qC?ZI8&H1^OSk@v z8xBvm#60I6>DK*7Qh(FxL;?qxmb}is#;uy}68O-xqDbJ@OzTo4cUz`44R{4-5c#W_mdrd~%d{>) zjeb4Tx;@P>-pI5*M3`@8T3176Z)IA`5cJ!b*5L@{zK|tvp5Gs`)+6x`gscMO@4=9@ z88=*=V?B-p{yxXL3E8|R#}d2n*XCG1K@!*HSZk58>vOCGs_+dt) z86G>xS_mnv8Dza6!Wv{PMqN67ko6jZ{`DX$j@VBaWc?Rv>xqM`r%-K98e|ng@+S|n zu0;aZ4ziZP=Q;$2`(|BXEgXf(_Z8NWDDa9athLBW-J{a*QcO%Hk9`_z1V3DhG$5hOL)_Hxb1KIoJtl{zeX_BM+y^!IjA9xhWhx50~@g zAQLX<%YnSocYz#aL2MVw!4#zVxE35-07)D#2eqgNG7tvk{V1OtY(#p}3u zZE#7KgO71w%0Yh=V}=}zgM2gPphCJ+IT(wAw&Y+BF2Mk(5qt*+Avus&EwkjH6_LWW zoDp1tyRzk=6cr*z4*Eh+xpMF;B&)9+Jc`QIPY%9@=R7$`Az}UH;66xWfE)}!&689I zX9D>86orDafB|hISd4lk-(&{mMXPi<*Z^Ugab^1A;#~>t*DuJu4sS>d2}=d3I*K zkDRT}dclWc&-x>RKQ`-oNcz`V2jTAtSyNHeCuPYybSE4B%@AE+ihm}8%aAbppi}bs z4?{57@npiVPV!~nDT%QL896UQ7}m*j$jmjep>o|?%k%UsBj;`LuueM!jO<3kI)$g` zlCz;$#X6PeSO;g%F|76aa=MW{*RVF|Q@@cNF|6O{(=;RdP{TS+pZbjKI>S0$pCW;| z>DKW+>jb2`??S`c=rgZHX8Im$SZDaMBm+k11vpq|+Ij1jZf=BEOf`;ztn=jfM*Q!8 zIy|O~0S`bz>Em)PhSR_WXz)Rpw3m0#ZM*KlL$alh4g3yeY6Ol#S^ENOA;z@8Y&2GU zdwU7GgJ6sQL3ql%2Th!}EzKSz!oC&GM&O15x$RQifFj=t1XuXKk{ilV^>{;DcAeai zgHkgBoe0zycn??80%xGy5ziR(KEV_Hqu?p?3e-K`c1refa@*O+uMr5L`Ji_FggO%3 z=s#4veu3ISufNT{S-hT%n~lJos4r3sF}^!=FkI5} zeQ2%0zYRSTK?d@_Ln91+H0Vb7%F2IHs>i45B-!`r2TB17=>+;37E8R#aVjc z)zTDT(tab(0)+(-UJxeje}}WI!Zi>_5GL*AEVpo@ND3zH@55RD!ZRfG4feJC!i5Mp z2$S~j;@YsnRU#Rfw3qt|jFB>}-XDjfX2_oy{vd~UL53OPIwHMQGB`^eN^+HdNu2Fp z$!A3R9DPL+YF`myjgn?Q>Q)4afTY=~yCq`f2ae}xM@hGRqlgYyuG3duajv|DBV3W1 zo*}Ly(jUR!&{Po;Oxj;4Dg6j8ql@7qE4bK~I}u$-;mZZM4wLqhAER&vnr9Fu?Ila; zg>&H{2$S~WF@OMfNr3XvTo5Mhzr{($6zPRzJJv4S(4*PXfdz^oZzHe{b=4Pm8ch&& zcrIK*Px)21^$s%58$QbZPHwmoE^7nnDC~8ClTe>d30#aIP7MUnFxLl4P$(M$_v83C zfw9QXX@TPr=;?vm5a!0f+bH-m0*@nCX9m7P(Vi7J96|mza3tC?+M}mn|RU1kQxJFVHwjk{znY?V(|4)3_2E3+aTW`Em}# z$-Y(iql(ZN9foZ4L*>5Qo8eaYB&uHMK>Nffya{;<&9u+b3!g{oLkHPsfx_1daCWeL zmQ{#s7@=9d+&d6RZecpY426BU=fJf;WG@_%E)j(OfZifh;qyxhMx=+4+|V${FVtbD zZ1fg%Z4*Kpe7XChRTZv73k#j*E0nw$h5d0Ybh@ulipf{_C7N1jqpwf`Pb*vkp@z=z z6-tTt3%AOEf2OZc0!c62CUKtSE1ZF|z*yA5qYu^X#*}g`Y^}I^RC)H+EUuawBwsowB^b_a!YC+GqU> zzeK@?F0#)C6w1d}p^NRaframg&r9sHL4`j_{w}r8@(VMN_RwYa+2F$ckmu0lzQQnE zhZUYJ#dL+QP#R`I;l<+fN?+lVklEkDOPA7bhM$XeEv6Z zGB}WRy|n@N=ZiSAZtN@Tb|ZfQQj&F(I!ViyR+jaLzT!)I%qq}-4H{9_&HhFl4{pr5 z&3Xn0MGK*GChMO5a%>bG+h%0_slOCeLs2`9?^VZhj6C_=>J9u?(*+BID=Jym{eH>B zfEysyKF17@%i})8AK$2ui7Jg}3RC248rq9(pxJkYd^I&*O4fI9Uny8*O8q8Ca(%N@ zav>$PyHxx-Jj)N_#>I+0>u^3%jwfx$QOUQwoLK;;w4ks5L^&wU#JDyA2O@j<6-%5* zp^+w|xi2#GI-Hk1hd*JQAB_LTWOO3N0NgjZ1P3E!IxuAyDo*;-`O<&-B_aDus?(pI z`8%0nOuZC;(lUKRB@cc{$N}p4kLAme>6kI~Y=r2?ICUpZ{1Wm3Pm0gNbbDep?HrV% z{O@zTFEs5Sl$-qTb95Re@_l_{vhzaz?4j9BgZlb%A&s=rFaUoLoDhO*m0mvRO6L{C zY3{F#!DsBNkeTlDXCD+2yYaRmcro`LD1r_5VW@nTI*{3pIzah^7%nWxOSoCe9hJTh z&DztlJS{88EXwOYmbSj&u3e+?_Y?NPlC&UDIQbv zVjCVaQa9Teyd8V@FbyyH!XAmXS|8671NVcOYF;1Wz3!%ZDANO9@jTag7*oxg_wnA0 zX-^-dQsNjP$ro7_?29rkq%S1_xjb@!Z|q<@W1~z}B%_^VQyycwl@T5HmHQ-9W0^W9 z#3FBUB?`PrTgB2%Lv`D4qVM3rS`K3e_x1J5n3aEVg$isuL>jOwLOd^R(7hF?RTI2o zrd#nozS6ve@4kvq)1djG1)+ILz7s<}`TA_q6r&UgE9vgXoQI^8$|Z(TX1d3dH)2b! zFTzBFnur={CqV>LphDi?^rQ>ThJKJ|*Ute=rxFC7<4iQ9POQvUp}`T-x7)Y$8$Khc z&eb1uK1Q8#Y;qiZ(izErkIyvKJ&13QBl;uuPOAICncat}1J57n!6ZCs_R`Dr{ORl3 z-RoDP^!^U_oIHhSp;HKd|Bo%i|4*p{r&)T~|L(y74zYX>I|wT#m6oI? zr^Iqq3ij^dSPaMFm8({^7K>J^Vli!{^>Rr%+)HBGeEI4{t&>(Xx4?vat2gieeZfgRR5XbAF)91(G9hY`aAZn>&`F0xHAyj-zX}9{q{!&#_uBJ&fttr=JGX@A-NC)6>kM{-?zbeE+<3 zzd6ExAuQJW`}a?WA^8mdMQeO;^!s;Y7GzAy@WHd0;s5kFAD#(~%Ugz-n978Oy28dS;phwzK5!yo~uvp7j2!Sk5p#d*n*xYiIqX>{{ z16}J1;QJOitQE{Q(E1QPNFm3ezfSg6#aq`sDMwVsw0)I zHKKoEtl6>OW@{K!njN*az<;YWRq03+J+}XAHXB-PLv|t|M~GVKqOw4-rVW-!j%i-L z+E%rVCxq%<6o|9e;!&!n#k^ju8Mc>G&>-GTXSGK~rWU}z*8@r8MN*8m;UImRsBnaS zU1beV^ebzVtMUlbNtsec+|9_9zTKk`SUYJI@%miradbjc`k8y!QtQot-Cyk)o^b*K5wgxm|2{IQGdMS6A(;R~ck*;Z;} z^d6CTlqb8Qv5Th{rMWs`-Ac`on`>nOlG9#Q``FtskiM*oDkl1Kp}!m^7^{@245gM@ z`|4p;T|2w=L>X>TLyr2>t^05r0IVG9TUAXG-SHkvZe`x4r>uTx-xwQ|+V>vX*u`GF zYcs-aTGex*>0aNfbJ#=Ey1wk@L8+(J&iXEB;uqcPJ)OHL%+?om>nKe%*25-fEJniw z=ue&Mz}{0CzV%wX)M2P9%9;to0O<6MH4VvxZN^1=(uwP-F3x_^%K-m0RF z|MhGlwXG{wwI5dtQxQvA<()=*9MY+gp~JR5IYS6R|{^`h^ex;jzF&W&um$RL9(HO35TcuR?UD?T8$(<~@ zo~1yfX}DJC|2qrN|JLZCm@R?XESN`4ifKo;W&H;#xc5?ltwrF7M=KV09F&z5v|mp? ztK)8@TF$mH0JqDLiHbKHV(m?=zjN}d<8^C-NJ)%JIagQ%;H(Bi1SahSO5R)Am$h}S za*JA0rfRCPk)-eEkU%qGZi1T}ZU5S5uj=&mMJIn^$VEGLQxC2kIW-WIBl;#~b=A3x z9wei%%vGZ-e|w5gve9D<LdZ1&`Nv%y*iEezDM^%-|xxTmA1bwG# zIaa&uZGTl?>BYjKzNAKre`9w``(vfhCU`vN>)Y2jsih~KDZ6#L6B1YFGKv^>k5;#J zrl8T@v()s~lf7;6!OTiWYx^;+i%JaV&|B)MCKz?-kzkoKcVCS5^dZ9OZVFTka!kXJ zD3wvwN;kRO?La4^EDP(%q;Oqh$J$kOGg1c}lg-|~Nj6-xPhFpB?9*KjbYGu!H$3CC zIMrFoA`!K7_43vfdc1|L?e-Ko1!1YVvbTY-oJ2NzTYPYGEeATk&h*kw-=#FJf{TR)QKf!uMMvi&1+OmQgaoL(8S7#nDvwjV$Ym(a+z>Js%e zT?$p<+S;(Ql+ai0nU2TKv%a8>8z!47l95DQOwrcFz2*T`wz0OwTA?N?Mk^s8tWhdf zcl5p|;^}mpIB3`8-&#&nrnVbk2`@Ra% z7eijs*4#-3YRQr|ba5+NJDNLE%dlAl!$9i$DDkJvv@L60*@CT3*U(z`c^Iwc>f|-n z*QaX3b;|w<#u(Q)o-QwyuB2zW)qv@iYkbMsY;(4UY};3EduUK&pfXRQBV{ks(;Aw- zjOC4WD)w$_>tP=`+1dizN1hVZe)arNpX+4Xwo4sR%XR?zJDKsR76{YtwtXIb zpDF{7IZv3zn-9B`w0UH&DZ15XN2-Zv6)L1{cem$+$u)!9n*}EoXSBYDO_se3QMwJ= zZY9cYbreF86@k;uNT=bokft+c&lBu?^h}<2P~F?arN^4N4or3nRPQYtB+@j-BI zkUd{dN9IX+QvwFjv4>dSB=!|OwF8TkG8Bevr^CvmHzIFtIFobj!RT_v{z+Y($L^1a zp*IUr_O^1oqdj7`m+srjYO{^joMe)zjQ{DhILk3?^Ei_>eNmMm7W1ia1lFd*5w69Y zjKG$oV_wM__uNf68sUQVX*Od=lv3FsN_7R6zfy~xAVuz8+g>zaI&tD8J_+n-Z<*wI zm@!Gt7qu@trnQ~UZOG$ZPiLH%W#Q`1v!$riYQ{Ewr}N#-vZ8imyT&MueWIqlW?Z_= z)J}>DSM907C|fGEq_s08I~nc-r`v|7$C8n^(xRtOn}~I*R@OFm93|$z<12gYKj__G zdlIbd&N^B3Y_EB;?D6TTsIr;s+=wZf=LS!|;d)UPOI$g6+Coor$?hH#+6ZjF$@tZa z)kk|3pvpq3K(tO7%5o~mQm2BrQOW3?LcNr>2O)c>uc!i^97wb2eRAa$x6|~wAW_29 zg^wOLiYbJX3SHW$*^6%?;% zX9aqPZfJ<#dgb{Spuhy zWlL7JE-IF_B+eGEUfCiKH;X%36+7T2-$y&=PARB~Nw`6E)+pdQ7%PY9lE-y4E^9f; zp2#@el6Uiw9kn~FXtrk+s57W>*gVl? zcGb#d*!SUVuy=c_^5EEgTBddaJY9?elAt*PTV}X z#p*?kx2kE^#3PMHa&810yWKZv9dm9{*y`!6BYfwHm2TYL<%?@Y%_+lhqO#XXNRJ+A zZhcK-7+-AY`*asAlhK-b^nQ-C)xJm%L)DyXyN_tN71wL6?9qL6o4{x@@H!cK?qK(> zJvKAlrOn<}LS^NIDFElHIye@D?gx7q)e~W>38j-)x9U|!UCZ+cG5_16p?cQMcAIr1 zxz{w-UD*u-Pq7nf{#&#lmx{+c;nk7?`9+(O&h|6}ixsGL zAm%Ys?h{lkwW!w&xg#4j>d{zlFGe@fCBaTPdZwdSH!okdcp3IMba+zYIx#&9T-79b z{3#|k)$-A(M)%#zGDE6Fw`ZWbRD0Sl)X}PfkWf7jusl7IQ=4ik>(ySWHg4#oTQ7V$ z)b@Oq<7wrvxmq2^9w>^T4xJafKAup6gziuMdA8BNIO`#))PQr>O! z+MJYEru9$WTMTFCo|?YizX5h9|F5}xVk1(nyFYn*)BXAJ zO{Vwf#}}F2AHHk!p33{2JI)Bs}0Xe?!Vd zY(O61xk27Hb@PfZKyZFkkL#!Kybdq`3m_K`8V=oQrR;^IA8JnpQOAr zD)DBLq5(qAmHsSH>CXa3(Ov1!!g(prr;!JfF|w9adbHsGFrF(tS~ypFw7@pHA4{G@ zZXnMh&nGV`7rqu`6BrW`8N4Jxt;ui{FeNY^y6(>kxP*5OXia!$bCuq zY)|}8A!m>kWSndu=aEN{t>kjDgFK#GN1jfeLtaEGJz|LeI-cJ`ZYJ+1A0wY7UnXBC z|4M#D?jU!QUF0uhhP=s-c>9p@X}_EgB}bCu$P)4Z@*pxw){sf^P_mg^O0FW0Ax|XN zlV_6Wk(ZKJlQ)vLllPDhkx!B@klV<&$oELmsUrFPocx9qWgX%!I^u*DnM)2Lhm&K- z3FKt5oD7qPkV*1zvXxv(9!stzHD$A0?k7w~_CVACaGt-;zI*nHZ=f z-?`*qawIvPoI=hdV`M!!pKK<7MT!a_3I7Cg19>(nI$GrV)#M+@&E$jRQ{+qJ8{~WB zr{r$(2hxuzl7yc{4j_kBJU<2B3~w7Bjr0|x$k{)JNY#!3R&cOi0n(|lcUM0NH{>Pc@5t-OTgZFK=gB{lZ;&67Uy?tP7N)e4pMm6Payl6&myySj8_7$_yU0h$ zE#!OTXXHQ049w*u-U4z0DIb7|dyG7kJc>M#Je53yRQ4Wm-?coylYEqXiTn%s5Au7` z#KcnK%_Bc1za!J}^`u-^_8h?ip6^dqkqgKa*-9=a*N|tBn@DB<5#e6J^J~bP$lJ-g z$p^^C$Y;ncs@g*=)(nfxvJ2l8I>X;Rs(L_8nxTt07?c;z#2 zVF>?)gUPXEHF*Si6uE{xi+qz51zr+Pmk^8XpLm{*g^Y}q!-c48BgwHs_$lN0RPtaU z{8tJgE74LQJc8~mJYP<(79!l^$lnNY|CzjgIo+=!ujh5q#3laj6CxdNke`y@k)mux zt`8)YeN3E>;`vw-(@PZ|h7m>ix>Lf33LnJ@WCI8;IV;26)?^9I9 z0#NF#_>un--)vIHy9wt~KlD$Bw*(G44RTHVm7rbdpT5=t2XDNA3d4~8UE;;G#)-EB z$NC-|8jm3?S%2xDzP14l`dF@ggUu3e`t-GRxaN)bxq3VA5-*yZ6Ym8$*7xAhsK!1` zfgJFsuSx#A;RPD(b}QjY`_%Hg5y$!-92!dz-jQ;^pT2f2&b{H~BfPb6lkm{>IpN)p zV|@<}jpq>FbGi^b*Y3fwH@r&_o|LDAmy7>8eNW?9!Yjdl`E5dHb;2n7SpLd2`M;Ia z{<5Hj;t;s$pZ51I9OPL4=EI-VHT}~`eH#wm^j+QH%CA4J>GbWuF^auS-@hK=mFp8w z$0d~hSN|S^KiQv=K1+v}i(`os;W@vCF!bL!XKr}t?z;KA1L>1}EB({)PMR`#x<~D6 zfur}e)T8m$K2~~P512ZA3e>;i_uuP%y=jz+#nJmZ9U7sF|FJ8a9vcwLjpf7&W1`u$ zFjmx!?{(Fz?ddkZYxI#f+!>l(7)y4IE-8vlZoYTD+-r>V#c<7tEZx1nZ|td4FR3y{ zRl~=_pYB@c>V!SFt01?2$JVUeLwq~e`Q(4ruG}nR7qs$?O53?Et!9Uj<$pgoK5cg} zEwpvc#!EK)#`$+c71FkIH~Mys@SPRiwXLn{mx8t`hKZxVJre(8Uq6-`co@1p-fpXE zyC*%?ceW2HENCc-On}s&IMes}F8A;9`+eg}x6X?B z?|_8QiQIM7=6m<->N57^w~hE=ZP$Ifjhy|q8507JN_@|3uiy1cK>IaDl_Ew7Ph#<> zzxtY-%kj(G3r6+j@g>_w#OinX0yk|hV(rlPi|du!UD?<&A3D439?1L1^q4PJ65C(N z+!!_RkUN)Fbd7Epa7alE%q@%!VGS!$tiAJ|J-fa#_VjDI@cu&Fciv`6haB~!E)!qb z4o}=tE>;mrrfSMt17qp2U~Ho*5BvUKipFg%tAFh4kf}qQhg{zryQQM|)dRPhcOmYt zjXik{Yd0H3Rog^TMX|B9lku>%iDeLl{NUSA|{bHYb&V7N+o;=&~ zhI~*zi~rFT@r_=Knm879sbN#v`@Si`2}8DK{*eCl@QUjMAJl?>yC?zBA&V)|FS{8=t>*4kdj`=G52paU^~EYvQ*drhS*ie1%0_d2Nyx z-;|6ATT#N$r`UDmrhv-9jhnMo9EaUGo#Ex~O3Nuj3(VY_p;9V&`4oBC1?656%6Hov zVr8+6LR(@P6K>r0`gVz5pI^1@B~Lj;)|lgi+e+?va*edswDIG&`p27FjZyirl85DQ zTh*q2rj=~!N_)&0|Mfd*`|aMgXe9c_hRN}?J!ZcP&M^>o)~+0XGd-|)V z`9@t?aZOi+aZOj{tn*K+-C{1>nk>$a^JQgv8wN?D@BL5Z)Zi?HC;<*-M&4z-z|{U zqAaAQBsZS5$3N_$uHYnkdD<)*DY{noCm0^i8N%iQKGTCncYb%94mb!F!cK4rlv!O1Pr-P``FD}9gM=g7F_8@*_(85><^ z*Z1*TFYJN_hn?&FnS0W{N<&Tg`cU8a-P@#gOSz#wb;%gBHk!W`bwat>=fk(Abvw`5 z8kXLeE#g%v`*p^sBJ^5=)m`sx$0LuCMLhcyXFlglx0kMa?9_#ry1xG+b-&;2#`O8N zu7^cTLDZ16@xE>TqMWS;#8_X+%ng-3Sa z@%==JdlCNT27Z9gzJb|eu?ZF!3n}CUWYemD;1T#A5NL*M2L>M67t`p#gfdJn1AiVZ zs_kkZ?;(M!;65~P3TBwY0?%U3J3O#2(l8=$F|HN_{1fruHt_m5Y<~n^M`)u0&lNz6 zUZ5R{rp5%eA+$w-%_XA5{e;P)#Qh$m;rW2*S$rXIlPOBv|A1U?2|SAl`b&W|rJ}?= z564jAUWQ~riF*S|7fRe8#FQ6G+^sQ~)cdUWaVwO#7o%*T#Qg(^4@%tkLmHvPeE=re zP~t8s@u9?hGL|h+;=UN6K#BWwBn3*`KZlf|#9b`vLWz4H1h7$LCkQOL$KNen~#C-z7gcA2wL<=SE^3)JY z+;<{>P~v_Cv}QtyyC^4w68FF7C?)RuBhyggo`os`CGKaV0HDNu3&aW~?n97iC~?n1 zwS^M*4tRkQ_oGn-p~U@hlo6D;Z$+k|#QhAU6H45VN0?CJem6u8CGK;OGAMDs0k=bm zdsh~k!&vKkhyY65%aIl+aYtrFiTe;_3`*P^&{CnqeI<$*O56vb7@@@d3&a2=?uVoJ zp~PL3szZtUQ4lhexbKg?14`UW5d)OCpVv<*aj!#3Ly3C^qy#1IYamD{alZ|LL5ce& zBne8~7b99IaX%XQgA(`K5ek&JpMu&0CGPj5(n5**07wu@+>b%wK#BWfxCSNe?;=bn zanD4JgcA2BkRvE@{|xek68A;O1C+RLLal=m_aO2BCGJy^YAA7UhOm?p_c`OJ#Qj&e zS1ED-668Cn5qLjFcb#|r1eb{I!aX%GZmQv#0gvO$j zxW9}tu$8!@Oq3G$PmmU+#9hoaC?)Q>I8aL5$04;!iTh{Bpi<)A0$D00?(d?RD<$rw z5S>!uem81`tZIXztx+j)e-UX`O5A@7Nh&4oVHAu~;(j4AsFb*WfNGBMx;uK`(tBd_X4+fpnPp5?x-$GiTlY& zs#4LKD``eXn_LlxfB7dn&3pmI9N;A;u{Zhs~Hk)=?21k)3kCRt(@Tyhxs;d&&4&| z{;Fw~;acB1!+f2$*U9bgm>~()$WAw(GOakg^pi9}sU;4f()U6%3G=U}Uv4(#GUC~8 zTBqa4PWKL-Or7q}w1b`Qk4*Cxc$Rd3;!XFLW=Is(OL*Uz*0U0xN_SWHbbn=r))%1kfVPd#AGqbBr8$`fT2>9iU!+ zJ~|ci0qqbna=OsxX_I6=KiwJ!PdVx6NX!=*0F?eq08dXh>m&eq|Hgcl z0UV8LZ@xS|Btc66uTQsbmjIqaCu+VqedwRyoQ9__IiHK1-=c%B51v|~Cotd94#?In zsoj6o4#?IgQl0BwP9G%U=k-I^Xnr_7B*~LR{A0THr6j@> z_nkUKv{?l3$#k^t&*00PeeQg&@GxH$_u1F$@{(3*@E(d%W)#H zj4kgggIoVkaFaQ%eALzA-v4>2g!`3`5??+EYgBok(rGp&ihFk!Qk@zEx0;BLXiNcmiKvIE>?<&r!jGpr9`H?iJMj4 zHxuIP|D`0ZLMKjjxe-s|4lM688s74*FMzj$m^cYt5;vvXnt_Y`Bq>He2~H)hq}-e@ z_jI6YnPp6zgd&NnFYj}rT$IF`bC|d%(aV|%H*pKf`(6i6{iTr1!*t^04FvOWPvV-& z`#dgTZIG%nkBO7eC2_UomOR4lCrL5-NpLE0@pAK99OwN(D*9|DPC}6qTU>4}hMaO9 zm*%_Ftrs~BrEvHa9ek+IugmSrwL_*cu(o2JVXmY@TDmbX5rspW_Te*fel2Bnw05wi zv9R1c6A|WBOK^)=*=CK!Nqc!n(kZDruH1S@Qstij_g|OWokv!>k#n?&=cMvssyBh{ zhMcDd!r^2c1>(HC7!GT-gB|DUa`P97vq@UWv5eD{-fLZXNKzwlZY;Ofq4;b`oXG&t zLhOwHR)?rFehwXw@tjW(g1Jfi@EbW{>4(qN4rvt4`PxB?<^t_tCv!u&c>_|A_o1|^ z)0oWB(qJzv4@m|jnOBrs-%2u-XnxmIG{5gDnrn0vS~S;c2RqJ7%FQ9Dig_Pns%&1y zI8PQiT~{8G)JUASlv`K8lP#Lt7=R<1Kk5**XzrwgBbv?HhZfCU+Chuv9_^q-^C#_K zC-cT~^KnV$rI3R82PSjAl;FMPA<2Lw^O15Zx33n>V?9OlWKYpNrK8ZId0IQzaXwIP z?vLQ|awVFF7-ufxGM_0ANopj{m&z^Cr=C+J^>C{W0Dbwbn3tN{v;+F`OGU!3Xb1G= zgQUs5svS^`LYSSJuW1L!>Tu~XUe^w&?Vm}_ctblN-K`SKo7%xn_w(iE=aTNjq*1-d zbk7@)lefx4k|Rm?d*#+z3}HFDWs>oM4gk}T6&O^^kF)~@wn@_Af2yf0q>m*O_GTl+R^Rx1h z(7qWV$+P4vFvFUHDw0zo(hSaUCx%PW3eAvqK+eSAiJ7Gxkh2;o+&ve_KT!GPdnH-OP^sbK%(<* zle(5M!=5@EEpy2MGeVMQ$=R?ORyN|#d0#5da2){3OkU_TM`#D+Y?aKt3$z1r_L0aN zW>fA&NNGOgOx}?)M`{P;Y_LQ&N;@EDPm5efYX{`)NvxpFG1>t+6T?>KzS;pfi;BZo z?O^9De}*|3iO#!t60Qwl&Tf&&#?1&xo+W1`Gpti2XTO%(IC%z#C8X+7iF1k$5vdv_ zO=5rTfK<(rvGD-yfWZ*;WWo&dMu~GUPR)so^B$SgOrH^w)JUAOX8eE5y?K0`RrNpq zJefSxOeR|=X`8l5n{Kpp$<{4xCZ(ArP1HX_O3;{^F$f6b8|<@74Fa0+0?pWE1_9|jSPjJG2BC)X*^SOW*|L9fD4(la zmgIoEqA|!evt?H`2EL4z7k`iVYYYLjjK4SGTx$?$*(gdlpEU@YU(&tKAkeaNj|1X! z27#6hutyFX1X@-`6~Epf&@%p(o^yjipk;4R!bc1OEt^XfztJF6%dTv6ehQ{bgB(+z z)-C%v8syy67-XB-vO5|BABXZ6@1@Fq(GWn(en=B^mqDOqk8=Zfw?Uv~Z*$PxV-RTB z<+Stn8U$L#owoBOgFwsvz}3=y27#7sCOh{V1X}hN8qqHs1X^|p`FOw}RLgE{bnZvx zr6sgsU(hYFQKaU=WqX&Gno{hY;<;!VgnoW zl&1J32suA$46-g#e4#P$8B$zE9)GGS;x|`|zeZvILR0i%P=m)GH#!fIqGbMwrg$Yy z?JpaHtcw(1Zw$OniiI3dZ)gH}kn|H&sy7V+nL+W@Mu$HVSlZ6<`I@FUg=7A$#vtn= z#rGNm{4uWLwX|1%(gaW|3B29tw3EPV)aiFLfs;76|GP0r(j@Tr#=ve8Xrg`lXC{I7 z8=a4nz&0Lk{7n;hfgJp+F-X!R;137xAb~ZIgOe9l3jobQPS|;d1lCjQbHi%Uu^Oy9 zfpCzdNuVSgD8L*rHP)8Esznp9p|Kz00H0zIkkU8F<5YuCGjT!KsYB_~_qpaN(p8*X zi%5Am$jVv8>~P=|WGbFTigPpp_T(y#?)e%4>J;0|uyZ~s@}KvdN=>n!O0*yxWL>1V zG#pq6-I>~rx2-zWng9>YO2}i4;SuV$i+WlY)+-K-yCK?(dV>HHlR21|n<8i@eq{)2 z5`)0FyMi`*l|f+Q_!%u*gF#@}Y@pV!F+^2E7KNR5@L0N>^cS0ka7ns09Ap#OkVrVN z8<~oKMtn?D)W=Qh!p_G@K+@K00>5ShTf#w-CV|dy;GZNgNX6<-6Hxt`Fg%+6>@f(m zvzm4G83ZOs9}!y&0_NfGtZbV`z+SO`Hin&fSgMq6L+3i}nyVX%5jhb`rMcP>4s;`v z>hVEMAOKNHkDsa$y2nomJNrqog2Q#Yrnr=9dRjQhy4cRKaNs6VT)@7V&;)2-USVGx z&g!F;J5)SC?g%9l^|yu~0O z)3<2HZZimo@D>vNf)O%AILzkXZV+m=`)t^`5j>XufX3l-x?>kJd7VsOI;_s=HPlki6ixi&;2Tmu&en{PUP7{DfMe&)i1I~{%0&`jM zS2>SAuMxR6swi{5A9lz}>FLKI?dfp&ZH&CdUipu3@QaA3J|&(8tk*9K8(6<HiFIDXY3vV~!h0j^jFJF=ROj+jEjUnYXWC;1^AC}kfce#X$r*VgTM^pCpCFa z49HTRK|r&6s1^Z(fMy?|X6G9OH2X{{RnQ=y*|)LZ3k(99{TKFNQIj6nP-L4^bFo1v zMYfxqVX#!%%k`G8Nlneyb4*Nb3bIAydwNsgXXN`-ig%`|0weNNj;0EY$N`&oLeHE^ zlLKtZUU9arGZ%_B3G#C0=p4D2!>;7^Xn`rBq&cO@`4_pmoUNXwxjG5VI18JC9fA(wl} zN4r5l4CU;t4pS%0a0Qv@HVBYIozW&|8pdAfo1Et3y3W@r^F&jS-0)W6q^3YGG8Nac zb*D7Vd=BVbE~MTj#q913%2~zU zrodaQ;(S!;j5g`vI}>vUt2o^tW?02HvWjtoD98GcTwrNh zu7;bO5?I&L53|D4n$!T#XTuLR1<5ak{n4htN0F)ckBB?x8$Cz&@pprr3k(9o>wDzt zB7*=Ed)dJk8w8lRnQMT{jPx;h`Z+`|HweFU$JtHJZRBdO6lv!+slii4t8qnBko=OX ztC|9wK#TvvIthT#rvBxyRE(W3lh`S5|vf|~p zbB{qlR$ry5_>w_DRzY^ymkmO7*bPn2g<ooww1V6h1(h8u48xEAE_}XE8M9e zuKD+bxK1AleY^_pTxEM%<}=~Bl=OLJ2N=65Joko4@WU#*hTVR3cxeCF5*bD8a!%DTyPR`li(SqMt<^5)EVR*{-o~swO{E(^ zpxrL#Jh9y_r!60}%V|7!+vT)Yr`pqdnDuZ|>Ftop9=n_t$I30|c*U$;&^6viHMJFQqj!c40?Q0>tU1*nAW9h5QzA|;DpYCH0;iKJ@uS(V3FwXRzKC-*35Xxf>6(D}(Hy|9&?1Ed&W!~AOakIZ^U;V}ez|@$ z=V^rNM{|KepjqNabCE${e@fD6XHj6cEsaHb9p34_Q=GiBZ1Y( zr2J^EG88dtLEsY+=VTHPKbk8w0r8``CK4oR61V|=Q5aInkLE^AfZJU0qq)fl7M&x0 zG&dUrS|NTkw-^LkA$~Ns8U#8={Aj*l5SU!QiAtT@4FbDV@uRuJAg~<~KbkuYB3Bx6 zUBp=c9+e->Vci|#NAsmfkWFMmz7`4aa$ot;Jgf=m{(K?8s4qj^vhc$U088VQm# zC#mm73eO{f)fg7e_aaqK1D#uiFD#b69SMAa1jNVXiHNL&N?!tZ&eM@%lBT?$ixfW1 zOyY?1e8l63^OK0{i1YKvWSTJLi1Tt}-i;`$9dUjcNju`a7%42N1ub#Jc}dZlLh9u7 zN0GonB!h(zAY@{jYm^XB*)!fvS z6%zigTSe;R^u0*n9|(rXk`*F3Y1L~HCsc<9u@zHTnt2POh1Ec+RuxAx`U>vnNu(*S znqXA*)!%K@I5}EOQf$@KXyE~764#&dsOqb4mmt&hsM}Xn(aA@UNxA;aHLViYpLw2E zRYVIPB`tCNnWbn=A$4+E77aX)V2CVPA(E3;O^P~iAUuVwn8MOj;bqalHtZOcH%CoW z8A_RcAQryvI7lEAOS361KOc$)*#NRR7!ABZHbpc$vqdwUEt=Cz6-G3B3_{hpJ?a#$K%L_9 zvqRS@Ey}-6b-TgWbqJZlhGi#VV&1R1COvyarwE<5Wut}EmA>ZQibCu>>Tz+nf2H7I=eMdBK)hh5U zE00&}pq{M=&@n1jXT=U#)r9DFj?@Xmb(fwl*y0CB%TpzY!m^ngL2 zsp1s$6@x%i#VP2k27#7|Q_$B8LbdGHsPizGR!%`*&@B_EpogMCwwWz^JQ{d`E$iS8 z_S>33zF$o6*Q3q{Bp|*w-_!)e_vVRckfcfA>1bfuY7m%(GR`xZ1fGgIVWcS+m+xx= z;^OjbG)U4U@M1Kul>~mnwf{?*1fGvNXOn<o+bhDB>8PL z%ai1FBNX(7c#{0iAkY`$N%EFKsI}=Yqt3gmQ#?st(RGR^$seLYa>F|R91V;&pic25 zdEXF#LWn2HUkw6VTk$0Mz#w2C#gpXk8sU19{L>)N|Kdqv#q=^9{V$#*IR*g^Fh9N* zb*=>m%9G?znoaQ}@x_8{0NKos1@^50o8n1Q5L2RYJxK};MQ|mjgGD9>L?fOg#TsE_ zsVJT#B?bY#6;G1M1_8dslO$vi7_;I@Qfg{JL&TG$%pjo1;z=^aAdDx;RD*zKizmr6 zgHUbv$DGfgS;~_nFQ#Ti@gyma1t}G_eReF+wiay{Pm(!?0J=y#N#+>@#;kaf%r^+= ziFlGMFbD`kJV_QB1llg1B#R6JZ5L0H#Rh?#{!qKWtZ}_XN@MH$L#W$b1w;q!^TQYKpZw2V?mN8 zfk-Uy0}}WS&!A$N1lGmia|Z(A7qMOw_&LfsEwLa;lR!r-P|yeh^KgRVbY&7~i#c^j zQ|NkADkFdOBUDt;AA5dNJ-oeK4cIm4c+fS|Feo4s!)BO zu0q@oPKgCsIjb0o1s-P=;(oA8SK+!J3};g8kHHlH6vh2uKvR4Ygq%|$cTMs1SRf}1 zisEfBp$TYjgS|0lA<~q$!9GnuybaEX1xcDLof8Z6kbrm_9MS|_Z-es;0-4dsgE8kU zQWS54k7$bGZE!&>$ht`JvRL3MQWS54k81*0B$L3$VmSB!0r57tL=zBigHObQBuxTW z#{w^qfOs2Rn@QkPG2E?yfOs2xMiUTkgX>~Jk|u%A#{$!uKtQ|=Zq6ideas0XO?ev} z(FDZX;MQ1>q)FheSl}QssoUv$H38S#;68(Z1rl$A`wc=_>)T__5mq7I26yTz#M|J3 zSdf*oibrCBrx8?l&tKOBTyKNNGy>3oBw^CN?RwUN8zXN{GFwHd;Bhx434z}krW!H-Q5G+f*do;L`X zA8|kU4}*ZUk*nhu3=LQtxjKH)QVt4FnYI^z zzn@`J(QSVXWA_9|Q~V2F*A%h7RXzASQw5qT{v!Wr5T*y;Gzc_A91h+x2-s0^IQYFm zU=9(7gSRyT7mn>%uTYBeV-cN!+=V6vc%hq$!FELq$Bux=3+e zJizxUDL0q}ntfXnrZ`4ucN%25g z1XapK_9>>7Sja-9w#1z^NK+Tt+jMuyMfUc1kYw0hyW)Xf5|E4RQw;%I2n@uXgCrmq z*+ZIuTx9Qw2T7U)CgOp@C_hP&TSUGujt6cg z-*S5q z8RzPFko=OX>*Im{CRcKieWQn>Tx5UVQ1nUvd^YaPh=HP9WPeUml#A?}<3ZL%ig(5X z8<0s|WZz{7pq+A&eRn+LBKx+uvxgMrBKvktQ7*FYjR#p5DLxnvJVJ_ck^MEpBjh3% z*^d|mCWUgG4>^yTIx!gKBKw;L0di2&`{OXDs8cSoAJBEmMfT(IAh}_k--`#<$5Ce= z4lbP^XackjIsU1xb0yDKe-jUq8y*h+J|39Xf`-ct{vYBqp94C5ga58UU}(q<{+|qj zCLq`OUEB$yw7S9n&$#CX|1a?%D`yq|j0f&!6>@`bw`ASm=NN>!!Ot}abA#`1NpmGP z_>&9*T*(c7z#tS?e~UXmCRcKU|M$4(20z#mB)=4Ps3j2H0IuW)zpO=18_-+1!JlFf zPyxBYpJouS8ghd_-5|ik%{;ZOXwmywSPi+suQUk1=wVTdvl|tv8~lAaq$oG|^EE}e!C%r6WL?&@J+^alBv7{z z2fw@kvqHRZ$_eq-C^y7w8-Iv*FZz1;{)oOF=7FWY9{z^H>FeQdM)dVCPyfq8JS{H| z@pQQ&#B<}S5YK7#_3);sbNC7_aww_332LwR$UqQ#!LGHxW+B#+>9$*&ak+$m8;{CcBf~U?JcfsoGBV^n3=?YQ{e2pw zkoTu@l*qetDqp7Ii{>EHfbU{tnsk@XEw;PpH5NM=2Gz=ISgZhgKeMEbY9@VDNMD22la(+3uj&*}ivJ>^(4}**mYOg~dK7WwG0f zQOxok;c&aew-5=FRxWU}e!S>RX1xrAti1JTAzn5Jiw)ZQN&6aKf(1UPatmBnbQ25w z14h8gOC2Y)SAZw~t-kY-Q1K_wDDmH3@(v=E4?%wZJBuDeUaRsFWcGhiBDs~h;LU%R zMDi+c$KdqeEs+At_eefs_xSDsfmyl!M+0ZH;~i5AA!Prz=29GZ#bwUy6K5j+#C*2X zwtYEO_|Zqp|Gf(GX4^SAv+Hw_{`5RH4mUG7v)?8s&zbVR*~9Y?|4AkL1KEAEpGBkn zFIKW!k>6*{$@M?%T#K6L9)NlE|1|h_P@4M$ddvT_khG^_BN9sdUn_Y9xk6;ps=N`J z=YM(T>xkr5J`6MF|K-dHkj$$L6(I7PX&kTxm5;IVHzZPI&C7iY*&R}u?;EEc{HKo< zR}^8hl;{7ilBy0+et0nw-krv1NSH2`w07wL#|0HU>CJM z{H3T5n7nc6vx*8d(ejiQ0twuscvJiFq|5@@jB4vfpBY(gSm3N}5vgeqs%nsEf zmRt6XMTpI_Lw$(lm5oDD{nd8pG{g$Z=-A?4t70W(huJ@IJ9Ht^%F6ysxpk|w^0GSE zZU2dO=uV_nl=Z=8`**0cDr-R-26zqPx!6(OWh)BVKG z%e@TW!T&5ke8BeYAg5mfX5nqH4F&$4cF6~bl|76L3IA@pg6*-&-lf=v?Fu$2x2%}G zc&c5&jCmmVb-*Bhy~BT+?fVuYe!I)E7F`C_Qhhrq$1Yk9R9{6$Q_MCI+GNla zR6aKuk&O~5sVpi+WK-w_5GbqsDFl(%9wLk7mB-<1Ag{ZKtXEXFlF7{ynYDO$)XGZ~ zeF6zpl@4?zFDVIgE2}Yd@_HmPzj7rby%IUD@&LKnR>(4oD$i%ii4r-!^6nx;PMWg@ z3@okO5Jco;iPVPfKs#1gzJE|wk@AZXo0oe9zL(sLujAy4%pJ!sBvCkXa`Qgq`~b;I zheyF=YU&7(bN`I7n%6(=WQ39L5J1I8YTyKy_i{_iRL7kw{Ku z^D;z!Es@;H1}IJ5s}k{7-ig7L_Zx}iS-z915PQw{9BM9L^6;g7ND!CR27$|Eczh>>g!qD!{*-zvZ5Uu@Eu9UhF2>bBYl7`|-xk8coPRFAt z{ybNBxgLm5<5|69|4z$(IaeC}TOfXgr-9WhK{bBRQdO<8H`}#VLyJzBosm#yHT3C( zhKz)It6?`1R)bW+n~-w=m3#y#F{JGGrr5Qs>;%7(tnN~s<=UgO)T=Bjuhm&RY?4Bq zO1A1BK>ynhDFL-3uYLGWAhssL-hC)n`qJ)JqIpD#ro_fJ1dp}03S-e;mMbcNxWymN zvk(8g7Xn@kLx-fLRM`fg=i^cRxGXoue*7U2Unf%3VOegH>d=;hs_`^R=hozk1+kMW zIO6PD)d~C+wy)q>!NF$NDI|XytrE`)(b44!c@Gd=*M+Id)gUj+LVJ5|#ou}?t7$P* z>j@-3j;E;-kv9=|oskkm_+w+d6KnDzG7o_{c-A$5$_cB1S%VmVUkuA>YKzl1m-jrK@ z2qYsf0I`mk6Mlox&yndRX0)Q@;$h|-M&?`XLhi~0tdh=CZHGA_6WIYwn@=0N19?SlRZ~7e=Hcd%j`Es)_ z;Av_>qq>@h|;H$!y zU6DH_2aS`-&^x#>?GOCjM5mJ?G=4geMNAR_I2WAe?<7hiW zsy>JmtO%@Akh1Ei6f(jx-5DuoqRdT5ISncMbPAiW**#1>R$x%EE2?dh28g3IJ(fVK1f!no;+d*Wp z4^u%Dw`&!*^I>MH@F;HADsEeVh~Qa~htX(<6>Fyfu?r8mZBi&YT3?2T|CV4~51w9d zd7{$nM+zsFJCO3uQ7KpeSq~zm7%Y+R{cNFFXEML?WF&tZ$wwzy@#YZNxoEsGKDIgvr@;5Brs*v#Ou=v|&D?Y`JY*WY+fLwy7VFp-v782?^(W|Bt zkXRz;EPTrZhh|zYBhzSBCaZx0eiJE|O3G$cghRaH0;K!}DYqO|=95Ut9e@GJNI45- zuG3|HnvpVrlxKCyd)X-~U(qQ>Yd7a0zg7QX_U;ol?1*I@!ebw<1Fx!Ep0K4`9z**d z#j_eKQ2V>~WOl&s5dSrv72I~(PuY_nL)j1}*b+QS*59)yv;U3q>?9_ z{W&N>21^YqP>2hOZ)T-%9bi@xVdSBpU&_j3H6)Ny0-^o!s1!)Vszgd5+Lu`)2w97f zvM@Vk!w6DVA;ntz92#qHv|SZ0ht;Zd{38(mMdX%pRJ2(k=N7{9<7t=+{;1d0A5u~g!vNJ#mRsvJS0hn~p*1U$)nGbe z$5AQl2+kEBIVy$XX4hYRRLUq)x>3)AIz?s?nVFJe-!4TuE#I?8m3#pyA417DGg3Id zUPa0q9EiQM+3+`5L2X}?2!rmgo zFi?ckFFcClEn$+ZMtm`zjhIrm39&7Rb>Z1G!1?Ax!F>{OzIAKk#9s8+NrJl-asDs7 zwV5+IKkR(_@ce$g;QAI4zkx@VV!uOxKMWv?G&zkZh8}RKhogUdQT4Cfo~24MzkD3x z`QlM2XuS1Vq&#s{N;Oh$Mar*^N?C=J`;hY2qf$DN!o^)Fc+XJgB(l01f!&(5nO)8g z7UXDbf{ncjD83SVEuNmwBVun(+%4H$(ZEh3_vegg=t7smBciz&feRSnBKd9v?!Y4p z)D0}gUbHrIYrv0ML%l;nT=f4ES)XB9Zbte_&_j4+qwp03?qGylq_W94xWFUZg1rdr z!eedb&V(PBKyWt;0%+pioK131cvSWzTcn&_~c)g-#Z2S z1wMh@c7AVk4y+;`yn;Tz_ik7MK7nT!6&dDk%c}?Y|pPe3!r;=0;i(N$I(_k`L}~(2!>C99N$)lciZC$ z#E@$*s^F9Vb$@Tq40Jo5KofG^w-h>tCvX}f9bl19;7l~qUyHK_Jo&ff_gxQ}@X7x| ze%~z6jMKgvLm9j|T9FVI)k)l#N7z8O~ zAilUz@gezx!NOockZ;#2nU;}jGIHgqLgXz}2x81u>Maeu_C}dLg&DDf_ZClAG7YRa zX;#XGDjG9AgA5QeiXk^#NTp?lg+VCtHz}4z z&(Q+Vg|QUzcGo;I#FouJ4nttU6no)xCFbKCY4AdqIW6Wz8QrLn_^(@$s#FcT@8yII zSVFpN+EQ-{h8oUiUEMihdU!hKjcWUZ>4F4pGE*fosc}5Li$#PkD4mT1MWlLqwLX)^ zWIN*oZf1SS~^l>x)^g~1`6C`7^Oe5nzOnI8t~XwF9DbFxfYgXM-Y$? zW(*sXmVB5w$ErI*sLJ;cz|`VWbHY9nLIBeZi1pw*`6LGM&Is0uK@hPIVI)`lL!Ac-T!~=v9?Kz*FhWt^o3= z&s1P+YcqjiYV#3>)~W;oQ}^a03|*iS2u$6Zk1+I5C5Pr5xdNEG z1bdFc<{yg8Ir0-==p9;M8Egr##P|j4rGTvRp*kp)P>}Vp@A9nC+|Ssk?}+J1bSkT5 z|D_WdyA}@;32w)eV~x!qB!BtXEaVN&I^CK(Zw9$zAEyhO9!Fu|~a_D`!{*j4T7gvDV3vnIRNYhc%Y~R zCX<&JW+C1?5N)}iP}q78FX_B#zAc+F=93{TN{_;}r6UnwP${2B-9=d-K`%q5WTtS^ zST93qtcM|~Ed5m`Rd*8{mS7*j=OvgRP`vjM+^4VvuSl>D-x(i8Z8O0ucqsBT^Z3CX z;39Z7;(#1a87(TU!Wj5j>^@2G}H@b*6oU0WyG01dmDZ#3uosRY82q$CmpPRjJ$dG%{03 zcB6>OdZI4wj$+GV(~m80#cj5{6?<--GzTQX%&gV4z{`O*4_aojAc#U4pAy8-9Ryn? z$nT7g%CXtx$n4h~xh-lz0gsh%dr#=FAbBeXtd@*e1z=H%NBWF`28o24lBSNxCph1SV5@D49%zMR;IG z2*xDXNAM9mB%C@e zRrb-Tc+eFDdnMRC0&qxz9(|{Bs3GN%yjln=F?os|)eR_X(LACX2wuaZ*kR~Rl|aBt zf@ATCBz!9HKm!R3h0RA8dP5};7z)Q$%@WC&Ab3=Qy#y4lQcZ^Bq9S{YtU$s>JTO*= z0d7=5O8z|+#JBz^U1o#@m|GW8H6~dHnFf~S-CF z6kynsU4kBsJQ;|idpZQHV!4-~15ZY?sDvurqnW_r12f6I1O<4qY5Rf8S6T2aA6uq> zA`30JiXED_T}Lyn8%!{P=h%!FAqAs~z+_4@ z4y67}282~7I8}nZ1g1oKO%0@cXco~l0?Oprb>sG!nFz?_|CDL7H`CD!DoP1&rlWa6 z74AnhTQ=GyK&q-4qNu?W!BRJYp_ob_VE?ER3{jU+f?&{1K;W34a$q5D0z-cD5r)|B zNHE<`@|%y4{6>{PV8|ccek97L0^jH+0z*C_gbm$aks)0z>}aOHLW_B!MBH z6!Hy1B}rh&CxyJy+9ZJ?pL9o<%$-Ov=NYwfp21##JPBCDyBI>${djsX1f=Q@hG->F zo`7Oj2?)r?RLN9QHn~th=a5CY%9d+TqUem6OeUp3=V0gaL&MF_A^BF8nL(;IKWq>` zTNRL934`3t^V6&Dw9~uIF{{JMOZrpzPtXr_}$gw{t!Y{?*0~Ybv z)zvj){WUwsM{CB%25QDq`^R^rcJz-A4@i7)Z1{|!F{@_xzP&>={dL1%%Q&*c>o~o~{ zuS?a{61fb>Wh47WhL#QW?-*WIS6jV&8I!A#oRL&BJTkCn|KL!~-u{8z!y`lgU$ZfO z*0`62UAt?V#|HNgkL-)?8yi~Y%HqJpn21D4qi_qd!TpG7{J+;dD#8CQBdF~@Q?gr1jYszk?|?cFk5&&*)l-8*JNx(VnMh5XH99n2 zy&Fc)g4zxak4zwfv4KI58rZjY@4k@~Lq) zxnm|9$(m3r%HkSS?h4Te$7_#>{a1!@TvmL+R zH*8lkT@YEiEmb>V*B(PT_>pUhUMZaDu*rVR*RLJF}5&;h&`ZRnA)fMn((#_!aSDNaEp0`uye*~nHg z&za3=ol`-U=Q$M;JE6n(iE|nrDmnNVHjl;D}_tE?h69EQZY5RGlj!B3rg#Px(vi%a#A15uEk?b}!76!<1nBsI|K z0yYO-ROt8N-2}6Jr&ne5RH3f`DBlDN)cFpdjlOynJyBTR!DgY{CXv)+(5gnfY@;(} z5nI}f;e^htW@jdOj>_Ax7=AF~+F1 z9h3^ns(r0nf%VrqH7FiB-ocyA0{*$^Nearh zteR{~ZQH68D+{TaRn8oOjZVJr)M|9wj4D*HehLV00BVO+x3YSQ<8-pFv+S%+y`RRc z)K>&eCDXpQtm<%vNFN3ogV-0ar_xHG15QUnD}9s0PW1vfV90Ubqc6zY8)5(=e0YN!HMs#gZ4CMvhPZeo>GR+hI-r1@xJd`8=dL?gj4S4P@KLB zIq!syPKVU0oRxkNA?=nh`U^;M`Y}}C-bupm6vZq$up;VI&x1@5f+_RxGugiYb(c8D zucMAlRxOzlR&DYPLU)hRB%6a7ss~wf@J{zPPj{yH_S;|@vHI$jSvKa?W3W>*&*^8s zcsL4+Zo$ry4couYIay$d(@$9KtRUFv%xH(T?sBHUtWQQ?%6M6{l7gt6PO+V7JIibF zhHxM*fX;m7Y{;Svor|h!Kmk2<8~W&2?W*uCsCKGp^T}07rkv)BoMx=kl}`idt6kDI zrU>7UL6(DeN}W@-#F;YBR5uP*SaFtO*qAb_F&L-#dZ56LZyYl96;?s>8Pt6|-8Tc% zfNv+7N3BL0f+{UbiSN#nJ})hss)u$&=_yJVZ*)pppx5t1g-U!E%OFIUgT!~&xxj(x z*ZH%w<_vZ0LjM*i%ZKC79np z1co5E)oJjT&UOkGI1QCGG`@28*IG?^+)xAm8sS+EXxa!AEST5kYj^ z&F4;_?ic?}-DOUaHCH=Hsd*!t`0Hafd6_hM*0QC@Qe&Dt)prGIuJoOMPPiJ;=(FQW-QvYQx~EcA9+o%z8$Z(;|Z->MS^hu5$jQMQ(x>+ewa`QsIKL zl=SCv4+2yR{YN2IQ2M)&&j zxaGtKh4}P2nEyp2wW8LO(Ltg%Ra$LOXtc`jTZ5s9Y?DFBJCL9tbHkLuP<5uB6Q8x* zys3clDC0~Ps@{s>JyPxW{S`9-Sdk@VOR_r^Pb5-poqf&iZLw5yVnc67ytBtL2_5ld zvUx*1)zj6LYVYdY;3hUdg3u__nETq7}zt^KZb2g{{%LaJBHwTZ0g_G9p8}Z?M(J|cXzQw zs=IA#ygk*@mFQ^hvHBvt$#|#L+mh($?Cn5JJ@I5uM^`M4U}qw>E!mSqD3*wCj=K~) zyHd&CNHUsei^LNk)Y}=eTH6w_p4Nnw>}rWOyEzl_WOo-hbrEDeo@h>jaqgBzvF}Rl z+&4BbG?>DEXz%by|HSaV5sS^&HMcakx4XrSkUNqaQjy-47F3^XJ25UYTSa!$H67LL zwhs1!WRFF=JDRt4d&s6B1*RQ@bx*(q@AxctIfz2x3~gF~qaYwv;4 zaZM+Qo-pi1)ODXm{&2YH(K~)!x>*$xYnS*3y=0?iOu}c6D~fqpXYCxk|K?M3TMH zDAe06V|0CUZ@f32YJse*_HJFu$hesuZp&V52^4P_j+D9+A^SJAth6Ky?d>2vUO zG7-hpb4nbwifM zK!58nR8xR0DVJVXU$mpE(`{z7xf3+eCmn4)QgI^Q3{^?C;eQ~a(eAXqb|s^!WKS1F zABWy|D(TC)Sc-jZZE5R_#kX1_gw6DZY zD%spF)u+0;F^~-bqiB&t+lJO2oaiK7bu(F7K-P+O_H=l96oBo0fE{(zH2wS(dyaOjj8*Pb}=2ScyP1Qx9kgtOpTH3p|WY?bP+~8Vrs9 zI93M%#Jc(t(L^(9VW-uru_d+%12NW-=BTjr1zHd%?umNrhDG}H*wlim2xL~6&_;8{Z>u(!fpYb$2U_GC|b>WOluZ0p1T zZE0?!(Nl)m!jzQmRLo=@U5U81DzH_w{$MrIwt+?~ijkK{PgM9vrPRbeWxNcR9G`PAvdJap(+v74P8mf9MB%|?Eb1#f^ zXHQ$Sxu*@IOLeShj24D;)#&gjPM625WG`lFGR=IjQCcM;wXRsjtW#lAX5rx`X{^h(^0ot+4Ty8P|H%SnnBeMl$Fv zG{v0=Tq`;{wr_N3Y+`t59AnvCmz_B_JTa6S?4RgQ3oPE=-rL@sz;N8qmW1V?PMQH` z`hmk$<|0@C&*CT=#)^ZE*069kzw6vaQ`!)vRk*ziQyoMMjcV?U#;tMO&6sr>Dsx+d zwQH(7(IWGPSxkurneM5#T06TVJzeQpz}P1vJI}&Yx(F9N`$r~Hd;1T#eYHvtLRpx~ z;+=vJdk)sdaG7ZqA}(XcT!FbJ5Uqm6+Z0#A=S(D17N%r1WnrMQhBcWc)+3%+mn;NQ zeO>K6*u!{+MNf00N3C;`7})J62c|d7Otk6J zdo9qjWGh5r`o*KDAl=oA6)5JX&X)GJC?*#y(}gp!7Z?#DKew#XwnRJ{$HL5P3q6Ag zW*Q=PmpNFR#G8AtPmecamCu^ou20W0QDf-z@G^Y1wYSGNG-Lis?|<8&wn+<{C~W6Y zkGucV-I}%0REGo`aI=8g_5M$mhP4@LKRkjBlBtxd2w99`dy@dO-Rx9%gh1dExJe#Q zaruZ!kz2NjV1-MsDAoY7^rQ(wECMx1Z;xbKq*zw^$f1 z&6+A+*;m(9@zTDwp?*cxqOl>ILW~a`U$t!S!07&_fqi2WLkE`aUA`QMiQW76?f~4m zXJ7xsGTit#VP8B*1aj^iJ!9pv@zG_2b*q5s9~;=+1Q&oa8kX&?-U}y!C4=LmOLmS{ zE!$PKtgF6i8BPtF2Ef3woqKUz+P`aP*`A@1T@$;TYJpOAdl^SAVmtSb4Dd){**Mlm zfaAb%N^|38#Vc#dfj!F3ft)DZ3blkb9U%)OwPuqUNlr65yLvJEs-=ixy*W zd8Wlxa0H9j@qIfd&V=hva$?^oPjAp&wQMOih*0u$J7vK)JTg3C?HHaIpBTsLO`kJL z3g%t4TVAOaJZfPQbabK*1#}s-lKo+k^)KMLGPieEcXWz)K zDtA?fJuv1f?3nhX1(`0zxti8o7E4D98cXtS=#80pFzVw*jNfTyH zWl7Wlt;I~-t{K`!A7ziC#fb)~vokfTcVqpA)g5d`nly(nNRJQg+B<{>xzxH-I03v2w~7rE-|64h`!#g}Dt%>v*i$vwJghbfz_FuZwTxnHI#@ZnYkLgszr= zy`9Z{FbX`8lkq1f?s4o7;t?y3Wp^Uss&kqR8DKaWzzMdD?_){S%`KA!_t;&Xw7p_I z>i);ndf`MVir&=^%AsyTAMPe<>m-Y857L8-Q!NkIZ%}6;j7c7*t%b!?2(%a_$oP;ytv7ysboQGZ8g!vT8u0}^%ke-!eccQDc4abZ) zc<#h09ZpNsJ`#MWF7;HLzDH^6X~TiTiO_Ae&Rt%QTF?L-&2B|W*W|>lNHgZ24VbCK zmdF?FNK4yR3>}D9v7ynSei#jCgBZ+oPM*2S z;kamxvBT^snMISmNiZJs&Qe?#iDkw)$1tSGLs%RcqC_fl?!dho?v>i2ZL(hKZpIX2 z7*wl2u>tHQTm^OT{!1+jNNT0jE~{({RK1gLdZVW7u1nNder>STX*zUV9Zm3rsU^|b zp|w!9r22M;N*&vP#YWmnr#CHIQoXpW0+*N|Ra@iM;PANUk?eTI$q_q0s5%B6naApa zbBoU2fq}e#d`zAG3{LDBk!=TC!D$lK`-gaFjzxtzlHs6h?Tzp{GtGd~p3KuyqnMBEvjp=$Sd2=M`9`j;g=qW(wb#uz$AFof7TiReP3c=A;&c5Tu4%}%|vY_aCzg-aH1k|hT!tjoa7xb?V#$d^vE*LZ(LB9)^&T?eYPT(lISfk_bspl9O5%(d=kxl6 z-E@b#n?U0{9_{~c`EkdFcI?Oa&|IcxI3Cn`Z=8%yQLgF^Jw4N5T?*}!5#gSgdeqU# zr?;C!oQLo{p_c62TnvrkKB%4o)5~phNpdW%TB7P|(J-vGw<&d?rzcwo3RiNt$l%$4 znPGN#uT%L$2WES+!%E5(grS%g0h_uFB;1Cgm~N-i{N1}!1N+B>^H?{pt6Gz7z1?ZH zv8OZVJZ4Krm6c;EkGV}>lf%8jy(Vw3>x^&c!phJU)b8Qb_~;OP5A=)*o99`SdweF$ zDC42J+;`HVq=yq!G;Q~in<*vltCnX#Ux)#*jMa-hr)MFSF*&%V)SXJ?QW^?{PSg6U?xN$CI($dzBlQ)hr zlbY7)WD>vgf`eSH3oKltj9AHSY*#JX>gF~(73p6(4VV=Zufwr;>`AnB(EGt0f#A0& z+@MiDn!O zwbN%vMz>fKZi`0xPh)?mBVbv=dQ0LYCEZ7A0bxulH^9(P9x-V3R~}Y$t>U#a6;Te# z%{s@m)2`s_)16pfm&VqogXvzZPxoSdx)?mGws4o9^2&@Ha%Px=t;^XavzVAl(7%eC=Mvp#hfyS-_clf6s6++Xc03tHsI{dgl6>q|L5( zh>GiyvJRNKTu!tp>+Rgs*|nupEda5>HH>1H+Pq1-`N#@GymHz)p>VjMLXYeCmT3fy5NqL|J&moJyMx#@;y!~arQIB#Vx2}gMK+3a*5;euKA(I zN(+poSxd#Yw(%ml6)Ua|qq=gojg@qIY$(Gxh&>k4T#{mfVIgFbemUN1#D!n!{7@+WBp=yLAsiIldayZ zkat+X^3u?{W)vlQTRH(4?-tyFH6{8Dy9u zU0$OdF>|_V*wZd#@Hd9F`o?1C$U`TEZJl98ZXqMrvAvLAlUiD@xV{ybSwk)hn z%|^u4Ue{~U(5Ak!N&0*SyL$Ap+St)Tm~6s! zY_nXhm|9u1=-FFLpq{%kCUjb8PUu_!%F!P#)Ao(*9Nx8m zEIpxdS1&74@3C?E08meRY#Wu$oF}@2nkuWV>Gd8;FNnCEP} z{(;kASu(m#Jl?k87?)lWUD^}Y6`E(M#u1I)6yIA{>dKRb+U8mHB{1ikD;N)p+`7^c z!_0%m8N>8oq`kRw6Ye15xHi-)U6Vu^nd~?M!O>Psu1~}(l3dC7$LT^FPJE&`8gUsE zv!8j?FMXe0cn!&k)4q{?J9nzvFPM3C;F7UBka-;&fl>S?@OXOi^O{ZRIj+<7wn{D~ z^j$)F{Z?0Rt}4w$D`Swep7(MmZHr`mMWegHGwE_vz!dgErbaM*$_H2bm_hLBUd-CE z$+H>8IuJ9xy1!F5_(%ED@&>FmL9bP1rBj#>KhnRk;Y~BAd%_oK|hgT07(ZPuw=WYoPR4wxTf}ZlT}PyAXG#Y2k_H zh6KIlvlJ@hz?Nea$K!A?=RVstS)L0?u>&wR_-_atA-c+CBou9q;)J0kB?px0d4kTS zYB^z+akvQ3ZqKerupWu<4$N?j`Fb?;@l)|zT{rr!gt-f>*?O@ z7VS>C9->qYa|7w7Ykl0(mDr?5m<$cnz$+(Kgy~L?g7gX;r)TEURk3X7wZKuEyL0mo zGa_GEKF-I$~&Lsstgj4uUd%}m0XZ}q3ZDm_!^c-(fkVn7v^0w z>0|zjol9~r^<9SCk)qn1*8HORkzkK}pCaG#(jQa&5CZWu{n30?L4@xGuEJwJ?;sE@ zs=6TW!bunTKjvJVdx`JT>^AbXFIA=h;2@qzQPuf*7fia)f06UC+>3peWVes6boqbE z^NPxIRNeD|Hy^%ICRS8%f$u`pu(8Pc&J)i>O|;Bp0&K_AT$Bqbt5>X@PD z7G8tx`Q+-?2q`_z!CNuN?;bY?wKe_Wt3)%)`z1eRt3G&ThUeqMD=#wh^A#BBkIxEZ zrSr{J>5tC}W~B$EKJ)q=ynH{M86h9uah6$Mq2%X}{i#o(2?+FA#aa1_CBJ#i4_?-v zm49+p{>hU64L28G9G3q0kUNu~%$U!bl9fJ1=xujNOmRaD_^fGJ`KL+#9yb@>x9<7) ztm#?#r%V2yx_R&-d(X#b&CJR_Q}Xj&ed;sQ1O)o5%B=jAlE2l>Rq2Kp@L997^3Rt1 zhuvJW-H^&ZCoBIP$)C1?bF%W!%gR4b@^5!@&2vKx_^bt4`4?oRAD0zhlodZdE50Nv zj-RaXe0;)98sW3*(h-Dw*7B@)eO7#>yg{;>XtPUn0V!g%h> zO5c|izc4F)T~_>yS@A~^CyH}r2=?LGtn}Yz#Xrc3PxF{m^1CQ29?pu(y8w}oALieV zbdo%TCj@(PW>)^ov*LGW#UIOx{|Dlv_m0q;Y`u|{{y|neh$(>iIY)<}?fijJ#yM|= zV1F7AHy`rbnH3+<`KebS*q?K<(yz*j-<}o!jxPU-l%H<>Dl7fHtoS4-4*BD}9)dlZ zt>c_yLa;ady;7#%DDm0yv!n>hhy3>=-Fz6I(D^x!hpai)rCI5p*Xe_jKF@kk$IB%S zdvNs8(0tGT(-{BW>QQ*3RM%Sb2h$6DZcBJqam>v?2GX2YWFXD0gnLZD4TEg`vs}V- zDcPs;tc3g2V>xOZeLCu%vv_Wob;&eAg)s{AL_ zKe%Tl=)I*|9gnumf9nzH-U;!n=_tQ6x0vU@p4?L2b6gk6BXsxpECZW$K9i9)I;?tK zJmNfFzFuLN0|bqeEvq@bmvWi@-Y)$C&-J;BWam87pT-=$mv(t|uWRWQ?bhPGMR1WvU#uKWMJ|0a1grj`)g^L_HxIaJ zM;|A8yF;HO9`g*^B|&M(fuuTJcJc0RJ`3;W=bc3c-}=&>6hw`Ms<>4jO_YV*jBZtO zaNuTk1+BfEq=Q`~wOaXIsn?L^N7O4s^P}pe)%h{?+U5MXdP!@3i+U$({sy%l$ibp+ z6gDxZO~3Se6T*n+yC~@`CG5uU6cKJ#KWChuP-_L2<2sdeIG5xgvJr4rQrD07 zd@g1=yeGeb5Sc*Q%ExcQ@h!}xzlZQd%esgV_57F+zv%f(LM$NOBm|wm6M`<+{j9Hy z5cL^8YncwB8TF*_8#%h1)VE#liNN;(;7R8rgrIXO;H-X44}}&XPJZ!c2@!uXNU(p4Ct0WL-hmW+clnY$iW`EfN-58m`u`NyDgyZ5noI*sI}5 z8un|rOT)byj%#?9hUaR?H8$mRnTA(tc#VeFYk0GUcW8L8hF{U}5e*;L@VgrRP{Zdn zd`ZJ!X~;D>>winbcQyQrhX2qoH%H|QY8cXRx`tI6F4VAE!<8Cx?aq3l8gA5ZvxZwW zOli1N!@U|#X!v0b&(rV{4L_;jH5%Ta;jJ3prQw$~d|1QBHGE3LA8Gi4hA(UQnuc#_ z_@0J;)esv>Y2PFbi!_{~VTFeCG+eApJx`qceJYU1h zHM~m08#MfahF{X~Aq~H!;SV(YiH0w0__~IF(C~c?ZLA5X-&`9ImTFj`;Q|e-HC(OX zdJQ*fc#nqP)bO7sJx|fyso|L#KBysHzbf^fuHktaep4X@Vl z3mSe~!)G;oL&IDwfY_eN8Xm9VDh)d|JXyp28s4GdlNvs+;aeL1RYUx$tk7@Ka6rRR z4KLR4Y7Otz@HZOrN05X+4d-gutKsPyo}=N_8h$~;uW9%_4S%cQdm85B_?`4;YS^S< zr-q{%UasM1HM~#5Z)y0vhOcSJgE`VI)Np}@t2ErI;jo66Y4`;VAJFh=4PVyqZ4LjW z;Y=)CST)s_L7n;X(}?H01B}vfV=(j%j$QhM&{$E)Bn~;WHZk zO2cD4F~@Zaqk@-RkgnT@5y9`*%^|+BtQ@Xp(8>HAcPbpnVCQ! zjT8h#Lkj}ZOhCon1;uv6&Qa{W_uf6I9FHCKC}LNziyqIhz4yKLy(WR<_x*kUd9PnC zhRJc$#>Tc!T($_=5OP@k{YHu{Ulw=*LiTKe0}nBOWH6C0;7t zB|a^_E`B2ZBzEcPr;{y?70bn$;u7&_alQCg@iy^s@n!J?@q00dWg_~OB^HQfB7e4* z=NF1ch-<}5#GAy2#Vz7{;@4towy&?3m@iHg`8zR8Z=TpLo+4f#UMJo!ZWcclzY{&& zAX496;yxmOx0&)9@nCUlE$%NKAhwGqh!>0Z zh);?;#9zc-SQe!HgT+#@MqDf&E?yztAwDU-Dt;vH65W0(4{@}(zj%PyE}kG>EIuT@ zD84IxC3;wVKyi_Hf_R>ItN4)kk+@5AbERJ#CKicR;w%=+YG2%M$IdQA_ zx%h9f#~@$tK(SbyF3uN^7B3R75g!r%E^ZUQ5&3|P<=kByD2@^9#M$C1@l^3b@p|zA z@pfBMZQ|qN%i;&(Z({0D<(oK0jEQr^W#Xygh2r(% z1LE`IJK|4baG3lNM~Y=)t=J;26xWNFhCCO_tVQ33&d)1rg)fm zmUyXnm-x82Rs2N!U7S?lr!!w%DXtYS5N{P97GD>03jOORh?U~O;-TWn;(6jt;tyi- zXkSkcak98TJWO0CUMk)!J|ey)ej@%RrjPOU7l`HJeDQd3y?BjyulSs}Rs2EZ!V~-J zY;kXKsyJIbPP|mSUVL19S^Pl!UQFND*WX7RBgVvLaiMsGxK_MGyh(gcd`;Xb{wk)8 z^V91m=8F@>Y2rMwT|7nHB;G1MD}Eq;EvAh3(-|n{i<89p;!1I?c!_wE_^`ND{8;=| zOe>Ni_j}y-nuNLnSpB3K}KNEizy$ODLdx`sqrDBbEuy~Ysx_E_nhxnxU zs`!z(OLU9<^m>ZJ#3HdtoGY#oFA%R19}?dbKN5ctdzJX<3>Hhp8u4K9DDiah3h@qc zi}<$qotRdtd=p2DQL#l_DxM;45^ois6+aNa7E{W6{R72(afY~9JXQRQc$4_BxK;dE zOheme`|l^_ixb6Z;ykfkJVm@fyiUAdd`;Xg{w(gbzn|VdVyRdo9xNUuo-SS?-XU%g z-xj|UlP1a^aUU@%Hi;|6W5w&l`^C-T+u{!K7qM%(pH7aLC+;sEC@vDu6|WTU5?>Pk zDF!Qiz5T_JVoaPPE)!1`FBGpA9}u4x-w}6;zlzyWKfNJhnOG~fh%3bt#lMKRi4Tjf zi64tj%-5eL4iU$R4PuLUgt%6`M7&9SPJB(=DgG*^#r^d9iTNVFDPrpR4Dm$qadC_I zvG}8yQt4keP|O!6i8I8-;!)z6;zscS@mcXb@oVu9vD+j+y#eBA5#Q=C_8%y=i>HX2 z#9PIW#h=BL$^P}D#RcL<@g*^(%8!>N4isy}+2RuMNO8S*gZP;Eg_ttM*E?4{Mm$km zCtfCADPAw$D&8YLA-*cUC2kWx5x*0IQ~mTkF+=Pj_7#VV#o|P9lGrG=iie7aiARd3 zh!=_*#jC~J#Ye>F#W%%|#P7tEYTy2z;yAHVoGvaDPY~COmx#BB4~ox;uZdrY{}xkf z{B$$LVPcUuMZ}lvP5nGToG-2vj}zC6mx?!t_leJluZr8nJ8OOYPm8aJ?~7lFNp*g_ zEOD4PN}MJhB(4xo6weYb6|WcX5uX%a68|ZFF8(Mc)%$kz5r>QWiWOp=I9psS9xFaB zzAC;iekuN2Oqu4VmnjYq%fy-DYVjiRLGf8}tN5|_y_nqK>+dJ-BNmBx!@Vj0TC%`# z4pMkAi8-;8i6!tMF{4fbUkBiSp{<6Zai=T*Jh+mV?)1}d8 zt~f!&JA%yl!^KO)2T9CXo+L*&&dUnFFYY8^&o|;v3>N z@k8-55_-N>c$fGGiFA^iefB1i4>{scafCQV94}53V`7asO+1i9y354FB|l0$l|=ey z==?>JUnX87-XPv7-YY&PJ|+H*M0zhP{JQuqiE{p!9PBthDEx=c2d6_0ze6PAWhtC3 z=19J`!lT4eaiUm7LVqm@J6a^4FD?~VifhDU#gj-}x1NNa+r+yie};seo5feeH^gn? zhvH`>^nFJ{U+@5*IpTP6nz&LtN4$ zf2;VN*lngSA4$TFVsVm)chDO7TyceXG}#;VTHy;x*n6pXh2%FYe7ks$xJ~jM3V$vBAo(8(2WR=|he-I5rEs>GBl+G6j}k|dy&dNO@i6gB@mle5@on)3 zk$ae#UWDw4eXRo9*dqC%3a=1XNq!QEbT*1li0_EI#Pr#I zyy4<#66x(nW?~&x;h7}tJV=};`ErHZ#3Lj>S>e;g^^#w#@J8`U$!}HoPVqj;pHlca z@kPnED*R7zyX0Rg{H^$-mc34Kq9?})p^%ohKA4!Ixpqmb#2GhX2e z66sfp)5Tfh5^=fMPU8AgN$9&!yh^-Hd{}&r^c?36g}0MP?_==`$#*IIvzRi+kC!TD zkVtPYh5Lzl;%Kpybdk>rH;S{xIpSh*nRq0L>;59%B0eW>7ylz>&GqB&O?Jh1#Yy-z zQ9OX`i|-34yj(m&JX$h?~V%#5crk;)mi+@f-1H@mJBE@B8D4-NhbaKXIVAkC-ox7fZyL zI9Z$~Hj4*~^TZ|Ma`ABSDDfomH1TZlFXE-*<>GbXP2yeRePW6Oe{o-vDs~rph^VsW ze6EP9Wx}XJhIlMwh{qU)xE(XZ^wRKP5!q|Pt4ZANtPxKTPZ9qrUMb!v-YVWBJ|I3R zJ}Yh!UluHfci+>R}ikrmi#hXR*y$huKio$P+?~0#_J4Exn3&j6X;XlM+lJ94#m@a0E zeZ@iIFtJLk5u3yr;ylrO&jRV1?^%F{Np8Mpf$;GPpC+CmZV)dPuMn>m9~GYzUlX^A zUx;6ce~7`L@9!wld_MwqnD0e^QOT!>{0=qi!EAAkc!+qY*e;syM&2PkLE-|@d@lj|&G!<()si14o+Pdl&k{F? z7mGKFw~CL6=6edzYrdZVz9sp0;*a95qSM9qyNehWBVtc6M;suI6^lgkeFdZ!Q+S3r zTbwT*A|6E!aGc}BQ^j@SMsbsPy?C=|z6XKppH}!?al81r_@(%R_%G23`RON%X<~PA zFxe0FK+G4%h?U|LahljH9xAR7&G#~(?`VZD5-$_47Oxj?6Ymlq79STki(ACk#I52E z68Ftti$9A07Bg_q!1I~nUSdD7NGuhj;v}(FY!GLQbHpRWqeb(*6Qp;V!e@!+i5H6- z#aqQY#m(Xt@iozWPX&6nDg2@Mh4_`2gozdXO%cEbML zp14q4F1Cql#AC%%#dYGj;s$Y}xJkT0yhVJ1#B+vc#23YXh@Xi&#qY(R#NWg~*w+&g zdy0FDqr|adkyuCKKE6?$B_1p;5|@hY;t}F`;sxSHag%tHc$;{y_@MZjxK-RHekgt+ zekJ}({6*}BdrI1$CH4{fi$lc`VqB~e>%}JVK(R$!C@v8X6V3OCknS-GpCDc!ULtN1 zuMuw+Zx^2tH;exe&G(U@{~d+5i9d+{5`Pzy()@hz#58fBI8@9NM~lVceqsaJ4bRKO zgT%Sw5#rI}N#beZMdD@RZ6uz9+$BCJJ}SN9Sag%w7xLj-#*NW!*V2F3V!WW6Rist)aIRAjckBHmIF^==0 z_=WhD_%HDnk#&jjQ^am!me@z^FYYal632=~;&gGAI9F^HSBUN6QQ~ppT5-L2zIc&% zulS(&g!qj3lK86lwrIZJ20uSjc>i_>-802LjBGY_Y#MNE{^=ibZ0nSSd~s&G+P> zuUX+`;$h+%@mSG(e-822D!hrrbFOQ|o5kD32gOIlXT;6oHt|DohxoOK>8X=cO z?IfFFwC7wB^>{dmwopJKj}X=L=Mzbci<3!==k+A&;|vn>uQ?>js8F<0qWi$S}BxL_S|5-ax|1Tf{ra zOvkxLe1Js$KO#Osq8y$PH z#Ggr&->;$*K)3+qCGvfXEKj}zjWo}hP_E`V6L>f8-;pmfl0oFh<0SIIe4iirV7{l{ z4dXZB(C?dh9|eDFyMXZXgb)b7t|Z~tH0Yo|+e!El=llcq{|cS7dojl=*xQf&I_x}~ zgk5>;2Wc1m*kAP@X^vI6h=k6V!jnnpY*Kgz30+GSUP;34a~0k|!u~A^zf8i9T?(6g zgg@ELC#2t(gkQrI9!bK#YK7~`0ccMOuOi{^28Ays;rAm7KS9F(*A+I;%a9Md6#khk zfd70>ME^||fJW#2LPCs8`Rzip3;JH52+Pp;eZ^=*F=rPEv6{^V?@H>>^0+1=l1_NNi-`^Wy| zr1ksH^5nl?IQAzB{`-Ame-i1x-wF07krHq5^55?DCovK)<@z6EBy{j)UjH`@|HJvj ztGt%4aP}zV#Ho(Ae3=9m@Mr7%Uj)hXkLS*t*VcNtpS&+wx?+Ck;9UIv&mpaY(eyJ}V2;(4oALGAzguMc9Pd6{=& z@gnvqo&V6Z%-;a~&v@t(&EKB!c#eN))_k1u{}~U>`M=U#1)2RrS8M)8;(v5)&O{T! zyU(`z$87G5!w=JI#HX_#Hy~V(kNvay>LBQ>Zz=Tgdg|jm!|Gdx_L|cn>74GWPU%u^)4dJHozvwQH9MiLBi)a z(6@jF>CgH*aSwf4pl>+h&|j|GF&_0V-a{Xs?azSR{#kvkd+6H*eYuE4eZBCp`nWcQ ze~I>c4^C`H*#234XY8Rb>+O#6z|fx1clRFpHejB?`H}sz`uGmA&gHQH`fUEOPqFsB zv4_4*Xk^t^nc^|XwX)9omUhyYqj=QMcaz~?!rw2UZxh1y&)WCH9{N^6-$X=W{`JSl z+Q;_}ch#_yqTGxRMmn*9H)zA<~~d#01W zgF5MJ*hAk)WJ30z=sQyJ?5P;yJwD%td>d(ge%O2@2K*R5bc+9`O@v-Uhoo)6Sswh0!acUR|W!B6Vo1^NS_A&{2c#x zTz{@J9Q{T=r|90~%C0qk{Ok8W_{pv0|A#IfbZ2Nvpfa*HxANjixs}cUO7~fmTlw~y zM?Wu`h|uFk6aMRl>r-<(uHEo+uJh>U-AtTOUwm8c8jTk~$~exT>?wi4nI~jVSuiZS zHuHqQ_SBKRU&h&j3RzCXq%8AZEZ*BIZm5(}!^uET16u;<`19zcvbbW1z z;|yf)-03eVkiz{B!Q0W%C+(A6gi}d@&=TG{C%JcFXb7(0ZSsWP*t8E(m(S5!lak%0 zkvMZ*ZyeY4M%M*Vmvb==CxzU9P#Eg6W*`zzcKLJSIQKJdXM+`~_%AyXS32%F_%G!$ z{1w*c zh|@LH4XLJu_|mZS&^_ooGeYI~zgy@t#Oxkgj9xqvT7g{14DrEzR%meqQ;<;82)sxo zbUkvoSBPJL&kj8{2(Nez-2toi3Y`IYpU~cDoqa>a=s){~_|m2RpJMWp$jo* z*%E4pzkd&HM$DJIXZFHmKHv?3S)&3Tm(KG7-WeF$@&n#pgVAXPymxTvxdHD@l+Aeo z??9Mxe!zPLdAA|p^+mTy&nVK4Y>TLfcG0*`d7efLT>#W@OHtl8A;wSB=ks<_cBcWJm@u}6ut<0 z8&E%Y1U)XL?hJZwX5gt)(7PJ>@>S4#8CCY{pcg}Kd=vC~qNu(NdM=XvF6iBj^s19R zzEYqj*?SCGQk(3ZfYPr^_FAE=KG}N%`8_S!`yJ^uBzt|41&ztxVA#@>>~ZT#bF$Y5 zwP<>>_vtWfeopo>alwpaZ#*jI%w+FuWa_MB@BHqLb6~Q!4pnD1v>?4ZlD%%o!7SH% z9@q77z2PwFNY@*I%v$4m(@x(S-(DlxTEiZTR_!6a8x_FbJ^VKfi!ASPCF5WDd`+67eRrvQt7q1*q-t6LK zLAbSxcOLTWtuEe9T>f?!uOF(>17U9g>d}K?uN}qsP}rM=f_pgZUECFOx(x43)S@dh zyf;uBS7mt3!|@{;8Qx29`kD-HEMi`p;SGY$>oUBjk>zVMy$Yyam+5g?s@pK{6lm!_ z%=->mu(Fr81O6S>%Nq^L+Io4%BH8v{-n)pos+TtmMZCI~cQlIe@Lt}RNa2WHUKNVt z$X?#_Xa;L~dA*RyNA>b{qKJ>~Y+c6eu^o144CYeus3c6gs7Kj-i8Zh;RAc6fX#Tng`pFjfeA~1zJuh!a)yIhZA`a z9)zDX;lT(r#*=w)Eh^|KJXnJ=IF$$65cxD7oPqp2od-)%`Oj;?!A^Mm7alx;EIXeE zV`1S29()6*F5tmjIJss%4lY2}9mRtK;S)#YR4#x8c<=^nPU69P$VvVzQ|kAqW63-i z4m~apzD2c3;XxKkq6-ghgCxX*w^2(y9+aR`r1IcF9E5pr+AwsjJh&IRk;a23&ymh|5J~XIq*CujBTVK2E`k?0Sb}0r;lUHAL5!8kRgwS?9!G8@@!&p`1+R0$^Kg{B zJP>>n;jXXXzlFFeZ7mM)TT;_;>{4LPoM6u+IVmf7hJyd`zw{*c1=o8SQ8I2v(Yb$j z``!tyNqCiM#$VA>xi47(YH_zD_c_<)?wam#$KC8^GivuZwj;YQyWy)Lcc5>p>t!If zGEPEvxNqxnbS=F6HP;=DbKPql_YGZM%gf(!!&K{}C%ezMUKOH5Xp9z!&s=XUj(od!STn8NUs{20_eZXKGa}ROPdeNEjT=4?a_alZ_5MbE#_peY zxBGk7<;Xz0cXhV=H#bbRv>P300QEUSo16$W!R|+fz}`RHATM@#+7!_s9GJpOcT%_~ z$ECphXHHkx)5%WCXr7_KoZ-eBb76{;Qq40I!1Q}3c%S1a<9xJ7_x=eg!VD*4BfNJX zw1Tcq#&x+6JY)r7C!>v}^sp7AIvL#T;67pno|AD6TC)3?6(E04MrC%NumUtN6zrW7 zT<)^TEJssx@19_4M&?zh{_ax~!V6&=&3t}>w>KhXjNTja7o{K>=|RD>6Wm%VxC(ug z`!^}bMzwcenh>UHDtKdpcN-PFkM`+qozUk#h?B7Lk&(t^-;yAZ=4AYYGwwT90JmIT z@~#!Ytq)kGwpksB4kKQf;J!v9b~4@9CiJ5I%qK=7@Zp3o&7%=tOz^&;5kYjB?oO)_ zog@@|GQrJ4N1S;GDzE#Q6l_Mf;(j$DOx0AdYl8OxB4vbV^iNU{gwcOT58(c6GZuw& z5_$sn-&O!G2C^*vV+HVH9gFW5D+oCmx1i&6f3*UX)^$kK{mlweoQ!LSLGZg3xK74i zwC@iqKz9R2zMbH{M@Pn>yK}!+aqP|1Q;NfMk&dJnd;g{*nata6#eTI@d8QV-{ZO)* z^U$NaU5ot+aX)Q|6o;vrspJ%=MH%U9_B8#AbJ?F{a`&T~Tbz3t0!(FCad&R4$vP4j zxqBB6+C+KQ+pL5miU%+;NYlyF_2eq?t_9^x*$6hiqp39EsMb&ag%Q$MGadpLM z$MWP}xW=6(<4!>@>o#;4H?z3=HHeh8p2i($jk^J@(VgANxaQ)tC#mZVR-FT69JSN9 znqu!Q97br06QMd|Tvf6ABaSmqr>9e89JR2-78ZL8QFAkvvKcMvs23TVFfh7HBnY5B z-_6UHT0s}5XHCTcj=NlfB>b#mLmYyYHb%h7_>q6rhFpj-O>UTF1|k0FGyDfd=K3!8BrZr6S=3;LnBKcW! zs}v-%=60*mX3d=vB(ml%8^dPJ-Bw_;=3XnXS#zHi_-0;T>^?~|haeZ+8)fDp9DnXF z4$}de`B<^X$C!TBJh5liJiTYuJY$ovS@WzF_-Q^=?CuM7nP^2AWtHZW$P)Lt;xMgY zntw0$xOFCjKeXe%Y!#p{kF)N-Vg=~SmotZ7wF30zub7d`3Q&zc#f;N^-3pLb->|m7 zVFjq|Z?k5+X$7$R2kO{r1-{+S7rS54?lo*wFUsyIY)Nkwhv^aRe!tk`(}RqW?DIdc z3NQ^>g+ayr$O6T9skKHfZZ$5b-4es0?aeG zQ{VmB3NU1!&q=_)tpE+1d#2p~SOHvZp^jgy0Ir7if#6pwfU7~=K)AnI0mkrmS?<4E z0m^+G4gSLlU;{>gZ;RdIVRYuLoLYV_&!#e?10`YlOwU3k-dI$TjG@fU)RK;gVRu%! zuob|wk6A6cS^+%UpM{%d1@LSM2i9~efM>nfqBE=jo*l>DubUOXv(32>bhiR{_F+B* z5i5Xa4{$Kbv;yC=LK2-?P~?F>P^=2@m7Gr5cOnaiF-ZM>@6;0(iEBj}k7k0(jQI64_`4 z@T?1~_+PC6p0%=1y4(uj*@3KlS6Bf&D`OSkWCgxw=asl`!RX9UY*XjUv!~#YdsRu8 zKGU-sOT4pC`7>ry!Od0yJe$O(d5aamvllrTxYY{a+4*cVw^;!^yJjc^w_5=#FmvY) zD}ZOeCqZzh6~MD;H0LfWfM*}F6TRCC;8~D%++zj4XV;dvcOmi2W$eSQmuIys?fXi? z^qHPLTH<|6&qD0A9xw546Y$N*jQ5ztlU5@t{5v%BDJ#I$=*Au_aeJV~Wq!>L_F*NF zjPA>Qx+KiRnZyevUIij$oXj%bq9oXjy~=v>((W3cD{&8@#+TUnY?j7b>Hj}U!c2=A z-z@PqP~(2I@hxfWf{Z$dnfua>wEQlp9dx->Sh*WOkVW?IzvX^HnKH3r$B zK9_Z+2(hagqapKeqZ7ZL!^wY?5}o70aB%c zuS?u&D)@|b`dcYj#m4<(Ntmjs;MWpw5f#MPzx}?uf}cy=v#4PCFr5336x>M*{wN7k zH5H_kdN)$R7V5}9O-4$@QHO>k!a9m6sMOJ`j za}I0$1gq3{WO%7tjRu=}Ak~eKBfHo!7ng?VA|0tH^%fyg#eeq6aP_cp0bB9#^AUs^Ji;^5c%=fQtxO~)r_;)YhGdP z!0`7RYr!TfKn6X_{^Uw4KpCuIA9Gd{~k%cGH{Tr+R*@uF?q}1I68#A8?;M`>@*vX7|Q)!s)uwd^l^&X)k16c<5+9Xi9 zpy2jW_X8@pmR;1Hw)V2|-Cr7}YASf5)JsQpX55aj`&5U53_RX*+-Ix+y#h2oQtFOD z zyq}HktdQ+L^EgZ(a**)_J=gb3aMJSp^9ERvM;iDsaoZ7|v(xOL>>Fjwc4k(xi|Tpk{Ai zweYL}HTyBv>{Kg2&8}vp3R?kcb`8tDs}-PTN0>@_nHn}KG8RYiOu-8LiX13&7sI5? zuUMmkW&Y57B-=#yvM@cO-M!1acWC#=%-%jW3AD(Q*_!%FkOVWo&xIhz#(^R;Y4Y8N_x!I%4{exEBOs{*%ssnlDu(B}irB!)l-bhr$j00#y zVJD3q{TyvI22J^lD08PFa%NwSm?Nce3Y{KX7G_%1SW@O4M~z!JRV=d#;OCR9O8b@h zgE#zSiH|RHucpTTFjFQ-+P2$J7N#{^RXDKBYeuAu9jp)sm-TrC;$%*w zp629bjuoJW9L3Rcz7?<=Np`1~xkoVxHgtDJSub9lS)Pl)!m=)q&f+#(tB~Jcuv$EC1@P=1R*M&{ z0G^e@c6W;vuz{dd+?TAt_w2zk_c9orc`r-lVR<%=_5S6uFnz`z!DRRL3Epudv8czb z15Si1^GOjduO~;izMT@`B6TS10~#GF&b$wiQX^dN?V2@**_-9d(zCjuvvGSAXR;Y~ zi(C$ivm#v3%#Lv7uy2HGfw>W`y$#H2X55qgxPv2H8ygZLQrKJ%*z1%Othl3L%d`wo6wSswjbcwM$ z7U2V?$_O9EOpfru#gqtd@~b1f53h~z-nl;O4yLr-zoH?+yWge=?^vftc-uK6!h6SA z5#9jKj_@As;0SjT&dDmp5agDYnv~{6c#EZJ`4akFRwl7-};hcYI zg!A;}k+X8KohxfLuh~#KkU4!))*%dCP&)APF4%{aHG#!`Vd=oLQDEn0wej3Vr2{X) zxoaYviQbWQEM>R&+V9F*%h0W*nTI0AJrPdvp2y-L0jW8=&dq2xmm!W@S?LX=&y;knPImjKv9LbKa2@=-rR! z{wU2Hj?|I^*_=#F4D{Zc(#$fGM-_o=4%M+hHpj-wKsE=o$$@N+LQ?|0$1-YDStj2; zQys|WI58)X&Axm=Ae)`%qChr#t0jTn`!njsvdkNhD@y~}>~WmrY_?a7+Fhq3&zN6k zo|lXzUL2ckG~Cu{gx5GJ=i}I=AiSE*_0_TiXb!Ogv`e#(W|0+mPS44W*nG6u3NXzu8*7$W0kRUK=fM?jGZOUo(afpv zyKA$LW@$zEaTrCb+AF-nXqDMVvswytBfO%*y^spbKAOX%!0e+rvLZ~?RB(KS_Y)PE zeKaRl_|q@m&Y68QCrOalM{|l5z%8?n<}@q7{hirIv)1Z>et2=A{U*U~MB!3^x1y&&+Y7SC=t4KSE3fNZM=PPozK%AV5|1ep4y287j3d|mtXDiG+ zDDxk%&fQXxLDkIfS1QuBFp}Ab^IAoxjX1AYBsSvwv!eSCh~#g?d9Py7CS0qHINK^Z zHsWlpNb6PrU1lTB+rF+I)J{wPQQ-~4$p}qyB2;I#lRR1BmO|WvUi9GAjJu;EZ3Yf~ zufE*ft4}MuV{y*k9P_!nx)klh{iY&=s_50OinOa3$?V|yNnV*9JpbzO>i3H7&m)q* zgU5-=E3<rd}! zqO5YG-LF6-f9uac>y_F1GpLhSeWPiQP?y>I)6dt{gW73nR@8e9hY_0OM5xYq)g|hF zj^iHmq6e>L6&@A!W{!qeX3I~0)bA*{n`0BLFO(p$_`?G3x!DR+)V*6;Z#ROKkaxOOV*|Gsz}_ zG|iTu$yVT}SsHb}XPRcq&wfhNZ275*hG`AcoEG&~jj=h=C_g7}i&rB<@`&tgP0-H6nt-v?4ChA@S3;ZoVbu!az`8g;WrUNu{LDc)4W}2*7 zxM$WZ-ZN_swMp2lS!xA-nscIV+E}D%w*1Ufnr6$-vS^srFwIp_?;J$(E6L$fkjR=N ztwx(QM@f*#nxkzDn>EK+fz6uZtiWc?@mAoQxiaeBLo>~mpEj9kw)~tB4buUdd3w|f z?rXDV-JV&qe$T8q+a_VN<{T^V(>yuq4u?8_%g?Dw(`@-UHyWljO!K0s_b}5mTYfIJ z3NY-LEkBo80frs3O+ois0bDhkg6_8hcy<+s{s*kU z_w3rJ`w)!wHw9fU&&;Nv2cu#7OwXQ-dT-LRV&1_%Ed{A5rVD;F>i$9nX7A18QegJp zJR1#DH5F`$dcDR&L3do^zO=i7%~7`$=lm@$FGzve;_`AdOx0AdHR{cvf{Gqc@b>Ns zUW>ZNQi0h?@`esKD$b`6Rl>PLfY;rl2g$PLj{80A*ozlI*ks ze{Q-h>VC&G%}$c-O4IBl`6e2sHB9rTsMlVEG|f(upREE^2(y#q-&TORrrAmIixr@Q zG&@Otl_0T`?GO83gD{QNixa`;F;M;l4k|JXMJMW77WkKPLdpXHYyh_ zBR>|V&-843%sYdgjl;dWJ3$K6X2-&sZwCJA54pd zshSFApkh*i*?ur9=1*A?+Ye^jOhGQ0?FR>00j@^fZ$kMq3A6oRx{@&44-SrnnK+YZ zjd@Qp3A6p+5GBF7Z?+#S-d*F|7`6gHquG8iUm9O1!lLw2~v>QZE%tm_)Z=bbJtL#*==x)G@9K8 zr^LcciyF_2c^6Ql*==x^6m;_yoF2o24=6CZ4c1A4*==x6EKJo@aAC}QlM2jkgNt`p z@Ru0YR-nM_HrOBqX1Bqmu`pFr!Id$uR~ZzT-3C|huHdgRw-o36-3C`kf!S?vZ7fXH zRB%hoI|`Bf)#=-%AhFxvPAfnUWOf_eWd(k3eM8K>f=QU&1~(}Qv)kaFSeS`3iHBp} z799F(&yPw$Vz5w-1Gj*I`W0`xX!E%{~JOQN?i+Yer`0`xX!`@yUB5;$(QAG~G-=zh%hgEy=I zy^UEqe$(neZ)28@x7rx!Sj`57x2ymS%WP11+g{@P{#?xc3U2uu6gJCuvq9k<3@Y;d zW3=7Lc+ z1WCS`+tL1EfxqG4Lz!td9DEZC(*YLIPiX%%vpxp}@Us-KvHhE!)-Mvc{xaA1X#dps zdv~1MC5_YAJ^qIFk2BPm9QQIO+G>;%_s3^;T4oDFssyS=PTVa*WPb}oQrsV-%oc{U zc$jHXV^-X2rAD)bp{EqEk1|^r_L4wb7`nyXGpNyQVTeeh*}~8_9%fq9I4JJbm)nXt zL<(3jO|=^y*BYd)b|b97R=ZI)OtN^8DwlIvb0+g27!mzIuASX;cEV4>%JuJ2{ zP!G)(hEf~D*2Dd+0A64VL;twD8eaHY7zV^UZDA;nhk3^7%B(mQN7}*w*Q?{+(-8P8 z>UByov7%ltL1IOHngm)=pB#5TXOd<`eM-F3ih5%_%rj0`CigQwT2V)m2gbdu3M6S3 zvJbXi;(;vskptrH1f261vS+He%tH2@c$jKfT!+NHW-2fX*-NZ~fKf0%?jA)2W+A&( z3d}G9XUxK6*j!cc%y0UwkZ^qrX znP%ZWxcV)nc@CegeiRSW8a^ESGVb-NgyUuf|C@N9S0L_K!T-(*&@{{n{w^zE7m)0J z7I#Z=wZDS@MZD7r{=ed3Ce9>&k9)T=3A2J9sN7=(KgkO03VyN`*cJSg$_}f{3Vs(W zfK_G%-?IYWs{h2@S80`5!T&YhX$3!A8K%9=>`0{-odm1Q3Vv3lh7HtPvx48l3Qz^i z3VtsuK(Ap|@OxVUj4&(seJgc8i(bR5;OAIDim8X`mF^-W=&#^+tMtc9vx48hGE94E z)zC`s0$OEO@P}Iku*$69?`;Km7=oHTu+n{q8fRlZ><*Sjvx2`*WteF>y_N>t*%e;l z6g>Fl0+Tn2t47HYF59F;xb~vu;kzodJj`VbEe}8D%d|ZFc!idS`Sd?4!l&ig z5k6h+8{u=~+z6l3YI%5S)WjVe;d9jC5k96I5#fWwkr6(Z%Zu1-f148F zO;~k=_er%8-rHz-_(=bXh6rz0nj*Z#m>%JM!i)$f`?DgPvCochQhjiQ6Jae6zZ=WC z57{^`%WP16FP3#DLRu!?=AT;_;pA~qgmbec5zeQUMq2Uz@(AZGEB)o;Xk5#~X0bRH zA9zNW#PV=FKCm1GcCNp4Tp1sDAVSwfIP|~lFBvz-Gv{KC_i;AIW-QrqgvFArSvp=G z&m4twShD4?i6vXJgnUxmF4=NW!jdgV0W8_F>&B8T`&%s8nw90JEgS2(Y)V+qW!+s8aJr_$0{UQ=Y*_)#lI?UWOm$K! zaqLnMJ{9fO9aR}*ZFc8CvRAU(2H>4iOVaSdqucwVqE1Th!WYeV3Gnep%9QlG5g~LV zx=<(dMK9z+=$&j_5jwpmU#1b{d;3!62iGD}mm7kK%NC`7%*%GA^0Jn_dD$vFoy2Q8 zzQxnIlx4xkc|rfZ5*MsY?=uxq4;#P>R-^L_gkH;KI_*dR>F~FbQjQIN%gci3+-2TL z>6N_fx=dcy2($4+%DUh%oaj>75%sL}BN&xGs^o;4hf(*w7-OJ&1$AE(Y~Te` zk*IWEntl~8Scgu)2~8PdbYFziDc1&1#)-Z?ado$p8@hdqKu#R_mvU436Nu~NtU~0J zn@u1&=duU_x0paE=Wl4jDYu$HS0}g%*^_cx@HQyumz?s5cX&14F_nc(PI+n|vm=m{ zoYX(u2jOQ2)6YO4n3TJ??Jy_h`M$I*5J*bu&tJ<**)oXEVPz(%|53E$6?=WKf6G9G zU(aEAAbPO>@52$^n!{p6{Gc-+IprbuVx&B90{XX2qfnO*}-k=vkEFhIoE~}_^1~fY}cH}nE2-=kdEK^+KK2c zwG0m4$!op{GU2|DcE^P&UvPEopo3qLbC#qn{cjg)@kM8aAe+nM0au;?p=kzR90K$^9TOXK1K@hM6^#&3fp=PzgmvHV(}B@|pNQ%pYt?nI8zwqosF1GHf;ahOQ|K1KoZ>DC;V= z^+kcc^vB8KexQ`afxdJpIqOHnOj#1>%ZMQ;d=w0qGuICd1fN16B~ZtN&M_%x;&|9q z7~n%)Vu5Z85z6`vp)Qqy^lK5p$+|Ngp-FxyDJwG%p~-$IIV%lw!!A{RD8&i?l8fM! zK(N2jpKkuAl0nJTJA8V*6B^o$`4_xt1QHzA{Zxp9{86${@t_+_^kqEz0xD`~|3MEK z$wR0;!2|GwAXJ{c1(Lq}7DiDh*6opcRO27eMnjd6b8*7SDH@8vqzF$W=j1Uk*;MdQ z&amDHRGCKCHRl92iYX@0E$33W7n&Mb0|i+*CnF<6)e)MQopTe@tT(yPH>ZR~PBVdi zdoNz;gc{P%L6W&SU+_euIWaIN1zmTj$pi-Hq%qKJ0z-4=qvHzAOyf1fbE^g z!{2}j9XOyJ28_&kKNW%5CQuOh0)C8jf-BL=LKWGY5gL^I68<0Y5&j!${$uVAHRUuY znVB;nIdqU4o`yG*E?x;ETYBCG;lL}=)_;2X( zIB7HuWe}&HfS}*l&`I7-gmW%uft?azZE+U@voWTGPB($B zIR~R6hSo-UY=I{q5keri-rWN|o1X6OQqYDasWC9^4_&7%K(8s}lF;)IF zfw!aw^M2$x=(4?4J(y7=FGt>ZCw8a2E0bN1kC{XS^h{#pml!#{OL`xU6C`jVkdC9G3-Z# zzQJcS3e1@ay;sYO)krG>Su13tQMsMNaPXo|9*LBv1&WYv65@@Xfz!v~^e2gHaXRTp zOt+Wd%paYlfm+|#v4`Uf9dbtDZovtxHC8h(0vi`3tX^xZ9)fc1kB_nOOk7im2yi`6 z?C|^K&P5Q-@$u6OC$Sy^&4O;lwBPo|K|-sCN9MzMon&9XY~J>eAGrm5}k1x;?e%E{qubq~4n{;j#gEvn4*> zF@f-e)8QvS-qNI$q6^Vp`AMCYT67WSKm4Q~oHAiFeB#GjgDaMzzVPEM4x|=6f^L-` z@7?f(uV6nv-hZI#Y-A-rsRyM@7>b1X@eWN&nZV8A{CEc>rA~Ma^JRX#{R62J?n2kW zPii3oUqi}I>Uiw#33Lw(NzV)i)BB`1_v#+#hN)lDU?&{j4tN#PVYYa4s|)7xxXr1asgbMRS0X4@>+Ko{RAurK zymGZFGar|vX9mJys6qtFGtzuJO#E;-E!;I+gjn5r?G~#$Vuk#RXj>!=$`~!P^VJx> zItO{a2P5KXOy|ox66pm~+zwN+jaE3*dp9)@?3IChL$}e9XXrmNkuk;-WFbAt(N!i# znRq{Ws`LFjpYJdtSGJkUI>ZB%0lIi#=Zi5m(I9#@7}ePs(jzdex1Y^JUE}bugmKE| z;V_*UXi~vjz&j^OTSrg@z1XMo8FbGWeG}DW|K6o&wxjX_`}elOVZFNtA}JHIFRCzC z<5y|znX1gBUib6yUw&s5k`+LfFh{b&bteU!?twxWF&c-czJ;ddj5!1Hr0nx5P|L^q zaW1In&1n1j(GWsg_K)ep_=K2|it-%Vy*%9-<~S2}6CsC?hky2m#(+6~J;BZ-;4~4X z_#`_R2Cm@IbpHf#pgF83X5-_>;nBh7L=&+naRLXO{@|O^XztM3+;K7bG5gmS2N*wT znH6;q!!S<}ZRW6wB{_vxkiOa(cvND3Cn2!guO&dpKeTbC zK+tGp3PGcGPXU6&Uni@^LWpaK@#e6en267wm!lJQa`EZpC$GX30e{KnfBrX7N3?){ z^p$_i>CS%>75Kl!8;`agbgl{_mB26Qcr&U0#&Tv>US59N-28>@EA!ji=I8rwLZ3Ic zeerw~UeLDq@YXgbf6YfGPiA6eqlk&n3mB6qYGOK3n&}~;i%;+mbZ>-ojY&w zsKSE0F{5}o52trKmA`oT{H3cGwB|3HJAV;>#peHKGuqd*cQ)aWMfv4z3sx^)z9PD! zt#wo)FOFQ*X0pW3k@~h3OIqizYR_+6Ik)Z5%GJwTn&8VJ^-EW`w=|TGtJ&9PKb-x4 zt37}2%EkF8Zv10W&qI;VU)H|3JwMiZ_~QAk`3>>fcw>2EewCl=|L=`){x@}xmEeCD z5!x0VVWK;`ztDd^nwrzHpmpKg)k{~ktXi|OwLNbU+Z!tF0=&B&0kjM>ffoKW(u(CR z$SBCr6dT4@vWO}sBZwx{)`Fs4-oCK4O;ONUbZRks3Yij8#kE~*Jp5KzYuob968wNv z%iQ_%Tia<<2yGc_;;!inf=@XC*UjwV22#><-J!u@xvm>LC^w}r-_1%1K+wO`byITP z5CUGxAU8E7Fa?5OIJd^#4>C8`4dlD-s66a#4Fo#Wu0_Djgx2m*I3PErU_Tr)Vp7s> z@iv-xCiy(q9h_2F4nu6b@+%D|a!aoojqZb~2}n33lW#mP_};tixT5Z74C@OtG=9=v2M zGdYt6ABNmj__J$(AuNA&_VOgVtd8JSr@3y^$%w6?sz&-4TfEo8qS9 zFc3`3bJK(Ec|0o3O~R|71C@>SE%Anima5w6<<(WOmhy&4%{B4bCdZzri8nTuPl~rR z)z!6B*VRr+oQO6xHsi8rT}^#;ya^GSYpZa&zN$Vxz9L>z@6=ZpMw=R{3-NMdt1MdH z5NoNeYr=Jn@rI^&EOBN^eSA_&b8TaDeSIBIwA5G4h*!5%)-}|WH#yTQnj7P_PIF~L zO>J`x6gI^hn`-J}d~b4XLu_VaQzMRI4e@F5gvQ#smd56a#%M!TMZ5uunrmau+C_K~7uiVXIr)SG6o{U4F=_Mb05DiQm1Ozhe2q#fP*kU%kvp z$QG_>o8P*i1vP%z;^lK!EnczQq2IElvb?%Fk%GM2|)5YszQTcT(Ged~uo^D=MPQ>H?#%r~(QTaiR?~>znFYYMZO8Tk7ko zYMbH>PPDSBvJMw8&kA+y@aI8V7vy4eYfD^g?XE0GRyW3*npnb#PGZ@L1+6WsIx?hv zb^FTJ@n}Pw)ebeH zu{wT0WkG>h=%DBiD6i_MkW~%SS}IU$vFuu2QQfHu#hWHWY5nAxtk880E!9=EQxl#X zP*qvgQeJN=U$m~aHXdbKtgPcqWn~R*Y>q}z+Y{H=sz0qc-W+eKL=HOD^{~>vZUVD8 z?l4DdD>_&5`tpXVrj7z&!>K8+ovDKFP;W}Qv98hB6hjj-CN-c)D_SZW3(x}U(W)9+ zn$XWW$Y|R)w=X`b)v1V1p0r1$L8UH4Gi?DYTN3)}rblb)Y7;(1%WI(%1yEDfWD;(O zm!q~cR!ypP7PKC&B6OnB`i|OL*BEVSY^p<+$D3N>wSKOfSx^hBfO9}qZ7e>+G5Jwj zff7zMcXko6s`5#wJGG6`>ZvW0%ByOf#`5UY4%<~h%d3qgEp_#1=!=dpO>h3v*12sh z^Ov_SPpGVf7AIQURMV;OPzbU5#)fFTz^~b`fO+TFHq-}HT-NmXbW}JTENeexQS00V zPSebKw7?jgLX&kG4v2Tor>d%k%JP!%s|i4Qa3%`P+47fz@Di$ z)J{tD;i!P+H60PE>!MR}t~}aQHN8`|vuqks9TL5^>4;3u`8`sso^`tboiFnT*@p}@ zrwiF);?AM1YmQjawjhxZ%kNL@tDaidjA}C@8jr`&;QZRQxTOmA;)lF}RHk2b3 zme^>&Ntx~mjV)HwP~YsJKjt;~$;#C$ot73%NLLl%N?XSgd53;trV}e*cSb`S8f)UL z(V7>bZ*Rx+2+7o<-IO;q#OrGk{XJ(g9226Ilbl$6b7RA3c8xX#(@x`cRlB!SV)>|N$i87XiyD_)Y-t$=h+TBR*uw|rG;iNsH$q3o`|Xes3Be*FK_JBf2tlgM&m8z z&FD*Oo2sJaO;zYT{IW5H-q?&mmI+gaoBQIJq?dRkVj7CSXaoKlZh*-{>jHaC<< z)l)lupEntOp6Tmsj!wpG;ec}FKvPvs9F@rSFbRFK*g9>-NP97Iyaj#2e^-1P8`GUh zwPvb=T#q+QkH-p&5}G@Ad49ia_1eoT(VprWX0}vTmp4wvP=|XChvPFQB^;1zq6uBH z5~B`=&*qL67#khaNQGOISiFH_Yo{rP?oH7`qU8muAgD=5gVmJTKVkQo1GC%?S=Duo zO(u>R+)N!XiYC{vz@p`oF|1aa{F)w%qQj-SeG>yACxmRYb(K(vI@mFonMt4N(WBA2 zmdRC08fmZ9+#X@F=g9#e$dfIRY>Y!(-MY$w;+_obzXtD`)bhpfamco{bnN28_ z&XcB^IDFLPbI+u!>M>8%;91YAgURyb#)cX3+L}6(xo8W_&haMK6Lrg3y}a`b%gV>F z&70acHgUACQ&HIvPXxysujb*w#G&m8;RHV^)Q5`dibPdQRNJWO^ws6ln$dn;L3YJW z6*7}Qo13P|CT0b@bxG`nF$^S9=+sGIB&w=J13(YvG)JfU!)+{D+0lcsMt1JyXb8K^ zM48}Dv{T9Z^DJ~Ton}vduj)_e&>@4j!EoOSplF zV@rKQrRmb`jK)+TTNE9ZWTyrR!*-hn*`yNv9K1reHZ|_&I>!w&-eIit2N<+HrZB-Dpc9uT zreW2wIx|AIOs}hM!fi#TrqER0(B#iN8qrp({d<$Kz9N5gV##r$g=sa$>rO3e)sdK< z^7%q*TO0c5IC4h4PmzB;Z5nT~*B`$N$8qSNUV(~Lz|6uOXNM)6-*bFJmuiN5Ged|w z81~y&wHGAD?8E0SUEP|C_SuEFU<7U-Eob@|NyL)?4EM^$a_!)G#cPUd8iFk~`> zP(tV+kU|qufJ_M>gc3S(4IzZ0l#m3)jtUBjU98x}-g~`b!-m+!UanX!_Hymz_dI*A zJu`{k-~0XJ{l4#fAkW$B?6dY-d#}BATXTjBW|4mUlv#z*(WCLpl|{pfN(;HQS~6B|TYF0~N=-_>`%$Fy`vHU>olSYp`a)8rAB`nuB&vnQA0vhgio|MJ7(3I6pbD zLkYo6(6Cyb&ciRiQgiG*Hs-VmgOO%uHkEvVLpEGOG^T%ILU>XUv=+!VxOD z7=~|;!nZ}RG&FOLgyYuLt32z>TFyOd=1!ZTCWFbLh7O$_dE$68UcwtbH1jE2dyA-=>+;)R!Zfsss z-;ngi$rAKD1U{2R%~ShhDXw0b^>CSg$wnldjatejn!k;Mk!g={&X~^$rN(Mmy`=Rp z9NWxjUERcO88mhY>jVoyOs^BIq=chRtcy$v-3GX*8<9y9o9Fhn!dSE1+BBu5YKB4PN@E~llnzI81&?4UmiGnEJN z^?sM03{1m(53@md7PCL2`nMjKt(L~6D;puMkpt6Y>}Fu2ZL%7P%}iN5LzCXxfn%U? zu1p%Z+76U~Q@IFP5-n=L2}diW!zj(wCw6tPPe=(%;nHT#N_vtBbFfd14JN%oq&7p7 zjct; z!{z$aDfHsXCzbwR?+#UxXzO81)XI)+ZAq!Rqt+Xo!>Pp>r$y{1!*!QxJJW#itx9no zGp0@CY=c{<*rk~g;nbE+93xxpv}lR3y~CQ9w>H)-ZfN4bht1s?x`R&8i*Fc4Vj8AQ zO52j&S%O$tc<9X`4tEJfv7^Dhgc&5cz?p&#cSd(q2f zyPRaTrS#NkwNocd#6BV{W(v09u%)7xqTsI^Flme_M1PB=sKz=&P7MTmL*(PvIGv5?N?=Lu?o*Mdj)qQ$Es>I_NM5a+|FEL0n}ZEtv?H z(n*b##+NFe&kchavt~g4SnA+Y-wdD4fdpF{%S8oj0K)p~+71ag1H)0!#OOpdahg_z zk;BNQr+%snbA-a_O$`sR^jv|gMyP>WEsc_f4o7I#aN2_=_!+k+9$D{ttJN2oaX+cL zc1n#{lv=IIsS6D>HXaj=q<>8=SmxBt!qE~0)NToEkX^SKCRB@;wpZd$8W8&r$KAUe9X=!9OhqZynoBuvRd9VhFt z%{Iu4c{7wXabB3*jbT5TFq0GK39}+Rd$eX@=8!BwAD^||5H(Xw)F97()DdKyC1VXa zt9nXJL`}cew&FlN!HB)CDl#LnLkqhX&&;VB@+NYseLS9R&X_Y1-P#m}V+-YGT9#p9 zQ%JG-AXYjU7+2IEUbk*#i#Z^LNx+YDl{R?_bm6>^W@<)Fs}=_+iQz`Iy4o>FNKiF{ zr?YfZy1r9-pe)J2aMonK!>A^=Y*%$GptzwDQaT!^K4#g0o*v^FigLuLF}NGZN^xrE z%z|l{4j`R#0v5p9=w+iLks)ExJZ44bo&lz+*C{KJxn%0*5l&GjMlrBpW}x>u60Bxm zgBM%pvL9}$TOS8Njg+XI|F=S7VvUQ|!j?tKSxw8_D}Ahb9-6ObY+5?a)Ooca?$FjKBF_jiL2F{ax%i9QgG0PQ$`NT zW-wTkx}U)BBbhZq(&Hvqk+JxHSw~XSdElDR6P%z`Y#L93j7;nxW*f$=!DxVLiz#J! zp|&B^=#Mak#QE~%(kb!rQ!(jc-NDhU#ZDG|P)ZL>i9;~mgxlKctdM;^*&kqeN!K%D zIxA#t3pT@6)Gw87)AQx1^-Ika;uUyyElG<VRz3;wL3KA$hQ^TQQot3KoOp_>eGjwIons1L85%g1!nfh{=qlu`q1wnT47i zre?(UL$cBIIBnb>*MzWDuEuG7Y9HEIQ^H*)Dt&0O0f&|*sY8>O$rc=%Y{8+)792V< z*+6OoyNclgD&oMxu6P4RYt;+XV3~Sc0JFvxBhRah?HU!Zj>TdzhDAV1_=dU3-kWl4 zO5TZ3k^fQHVfzrm+6kB_OpGxELT%T!nTj>8!kK-`%0~2GI%b^RW9755X$2PK(mb>T zi9tfg;Nn{5#`Rpn+{U1EPO zIa00C3t5aN2_K&l&k?6Zpq99J)50)prAD2mBm@_!7|c-(Uuq^l@wpRuNIL;jq?$y- z=pB?q(-_^8fh$89xYBm(Pq}M26}3=c3)I3Z{GHoQIW|ik(wb1azt;~(Hc*d?tb{tL zEtznpGNVx8R7PkujHRwg+inx-r9ivPkR0)f^oEIgMEuW$@j9LdhQ<91?jM-vOy5zD zsHZJ;?qTjHXIX}l7zt8Ei>PQc+3QO&sL53*PET)3RG=aIQo<6{a643Qb)uSB?O0k( z!@^Fc=a`U~VsT#&&od@)Jwo$W;{m!~n{%0}Y1mhoi}*n0B51ifum%>${V~i%4965j zbhT;!Xl|RDVQ)j|rCC>-6a54mHS|CF>J+8MwBNfI4aHr3S+MY!P}fLP`{PSpqpW%j2UB7f)K5VnXSJGGbYZOh8Y*z zfHIb-^>U(fCw3DPCmqbBcE6KzE5$zU|aL=j$D$f0)!=+$T_1rEkrG=^!5Wnv{3tc{ljllnrupg*mQLmks5E4 z@LBL!m?B6VrFP&-e}je6H>ZF6Iy1Wv`(tS@zsGP(aGKA)np3z_Y# zM6XEB&}B6tGYihP^@{Ir%t;>yN@TDs>Ql0*4YWDfKjaDjREergXq+;`VK+e&sW{Gr zLOSw;n^ML^QP;H?8_lkNN=dY11`(J6!~_zUI*d%NnlcHy;BlO3iM^X!tPztPQO($U ziK*>*6>3MRhH1m8ort}PC>HYx0hOz4yNj$$DLJb#Cf2+P8p@=}(z^z2rrK&m#AKVD ztOc7Odi!}Oh727Ay?oW;#$+r*=}>cmmJlV?y`$k6?^T1)7zr9PswP)`YSKavHa_Jv zilz*|G7EKSDrB~f=9Ew;RJcBZvF1!dpH8$S8KrmwOtvsc>Z2olpq#S4)ssU;woRyI zETndVI&4+dUc+L3Q6cGD=;N_nqqh-_CaODOU!bIpeJVCV#~36cZA~^A#CbZyiLP#H zb!^MV;FJ~{GIOvErcUmmUdrq_*&(fHj9WHn|Kv13;l``E^)|kiQQ7SbtIeh&duGxN zVN-kBG;DGu+RxNOv?_}AbakEDElUoeiF`PiofzSXi78CNZFToihH7-z{Z3?}9hayD zDHg9SjoSBd7R9-h-mF=LJ-r!>23FbBgg>Q&NrktIyfkG=JsT|&8)|w^pr)RPmovH5 zY-dW!nu&(@m&((I5vfIB+f002XhtIHAi-u@T_P-zEo;uT68FWn=1i@fBr_dl_Vgk+ zoW*d48QEG)rNzjT69{bln6o;qfniyVXkIQ~&G#u(wX0CsL^w{eSIAj;a#>-Gk4DQ1 z2QX@)s(EE$eC49X#fuT=Khu1ZO$AbzZ>SCY?_m{qD*(Q}^Cv#|TIW&OnOW*ve)8=+ z^>x0g?BEH$4c?7ur+Mb>e&X@R_dBo?ARk_%k@)cIfhcE#Z=?4_NAvHzVD4Jq99n))EZ-zg|m+J|8^1Pir`JOJGuAXk5g0x= zv%dK=^}d&1yh{0aPH*J>=h2J;7QZhyOXKPrgRLeE5=sxJdw+<`;a;hv|b& z0?70+?b2trOK)$Nz6)uVPg~AG`#jg~{(J4xzqCtd;$c2dd(T1p^+h0az>YLc55MpZJNGeHU#muAaf<)Sq6Fiez z$@k9^do!?4ddv*G3WuI81D%#On}K(D^dlB%-6@mQB&|Mh|*Iygb92OdN=}@)6;T=zG&JU>!xoJABp?i|~FyVxj(af59NUiUaA4 z5|O7=^UoNH7dMbTO#8PC1^F@^%J(0^ zUj;oLO-~o(d%Bn}B$zMA7u}G~m);Nu36=`(FIXuU6`UwIRdANzfr9mdO9fX7wg?_B zc&y+?!BYh3e<{y-f)@*3DR`aWErNFmJ|Osr;FE&S3BD}&hTwaG9|?XY_>JI?g1-y; z;D;$!K#+c%>3qRL!Ty3pf+Ga!*O{NMdLkYmI9+hAV4dI+!Igrof=3D-FSuFo48ijR zFA>}>c%$GQg7*tPBKVZx^MbDlz9YC-@H4@01%DRAy4i_vJj0jE?oF+I&@F2lP!4-lnf=37* zC%8%QbV0t^iS==@;8lV*2;MGupWqI`Ck1y4zAE^(;D>_zIdt;>M(`)WKLs7UPl5Nd z1ak$u3ic8lC|DxMSDEm+F@kZy$$~Qk`R-HZYYu zmEb(Vg9VQi+#-0f;C+HS1>Y6?MKB#NX<|7&1WN>~1ZxEw1X~3+3i2mA`2013j|sjY z_^BX%B1GluC^%4Xq~H|61%iA{DfwO}xKr?D!OsML7R0N|RQ_tg2Eiu5O@ikN-Xi#+ zASaA0ucKfu!C8W91dkCsSMVCadj+2s{7CRy!3-?L$-k>$rQj67Cc!O&7YN=a_^9B^ zf_nuyVJ6=!!M=hc1?LJb7d%Dq8o@gScL}~D_@&^Vf?Y9jWjO-`#|cgsTqM{cxIu8M z;MIcn2)-=%zTi)SF5VZ&a=Hi(608uc5j;q6wcsg&=L_B{_=w<3f*%U<*J)UejV%yj zC&B)LqXhXfINom*Y!*CO@FKw*1s@XJE%=_`*Mc6*^~oD}o;h{veo+GFVP$ z!Qp~cg7X9q7CcgLi{QnAHw!*2_=4aEg5L^yu|>u5_y%rbiD0GREWss$hY4;Hyg=}J zLH^nv`Ro#WNAOF*jL!Ogo?x-yIKk*aJAri!7~M~5d5d$vw|NAelKX_t=Z(;NwB}*D8Y$>^92tPJWB9+% z3GNnrPw-bkKi2*%uTZd5utspcV6)%}f|m;3DEPSGtAgJM{vp^2dkZXw@2Mq@6`Uj3 zBDh}ge8D>f9}(Oq_^V(Z_A1D)k6?vhjo@;@Lj^AtyjAcK!IuO-6#QP$#vTaycM=>b zI970uV2j{-!Se<07kpOmZNV=DUF@YO{(?n$UvjrOjj}$yl@G8Lv1)mdq zSMV!A9_Fx}I|}v^940tbkUx>ae64~T19EvErJ&a-X{2{;JbpK33>vSAVUW&WELbTx zNpPOvO2H!qPZzvc@HW9G1m6(k4@uC@_*>`1k%IMtHw!)^_?F=3g1-y)7^0sq7n~rt zQ1B>0{+v0>xm@se!N&w&5&TFHuLo55vjzJJMg*q{E)`rSxLNQ*!5ai06nswbUBRye z1I4<$&VnU^lLhAqt`R&{@It}c1s@jNBlwZvAA;jcbU6)zO@jQHVAju8!J7mh5PU_j zd#TPhTCiI1Ai+ZfPY^s)@Or`T1bss_pRnKr!Nr1W1UCy_D0qY5gMzOMekAz2VD>Q0 zzeKP~utD%x!7YMU3Em~RQ*e*qcY-|VU_Esf94I(RaDm`4f)@&2Blxi33xXdAek+(g zLi6t`I7~1mI7@Je;9-KB1TPT0UT~-2%YvT?{wA0;QkPdCSS&bBaJt|k!4|;{f|m*2 zB>05j2ZCP;I{WK#dI=T_ju&hYY!cigc!A*cf)5Dp5!@^In_$)`(MPaYaGc_W3*u#} z%KkbD_7@x_I8(4*@NmJcf>#LMFZi0^hl0Nf=9TMm`UqAC)(9RXc!c0df|m;3D!5DV z4Z&{&vnr(C1cwSn1?vP?2yPI(Oztb{8G@V)cku177NZ5TrRj#@GQaW1s@RH zBe+*EYmDYwAXqFoPH?*5BEc5H4T4(*uNJ&V@MXdG1%DFkGFF#2NU%b%M(`lPBLq(p zyj1X3!CiuH2!11&Hcs>r93&VOoGI8Oc(mZvg7*kMCHRKmKEYoFGplqt-35yT#|j=O zxJ>X2!OI127u+rQmY_GH`SuVTEEp49D7aE^qu{xM*9hJ#__W}gf}aWgCfGTu%j+vx zDL6&2POwSvIKi_7Zx(z&@MXchf;_n9_>v{qS8$|YtzeztVS<|kFA%(5aHrtQf}aWg zCYTl1(IKhVncM0wl{Ewhht)J^9SS&bRaIWBT!6O7u5!@ztuiz7c z?+AV=_@`iSye_Y&;7~!t{VDkm6l@XPAb6SJO@ey`e-d;i=;wzDE*9J-xLeSfsPp9t z_7a>TxIpk=!F7UL1g{nRr{KQ@odY!AdcmUvj}zQ1c#+`cg4YP%BzULb4#AfMUl)8= z@FT%*1ih1V`L19G!LVRA!2yD0g5w0o3(gR16g)(5jo>=L4T9$iZWFvx@D{-b1)mmt zP4Gj(Zv>smTK-OgBL%AkXA3S7Trapq@B+ab1@9BwDfqJB7lJjWPX{8KPL-1n3>jm!-d|dEF!FL5e7yL=kuGQt|2=)*h zEI3+lyxAE(PZhjCaJ%4*#4O8tK+-#jIXH(9d|v2pO8Q;FF9p99{E-Mg)(nlV zV0XcOg2jTP1giuQt*`wrF$3|Vl3q*9!7rEzo+NmR;2A{Zze?~X!CitM3o>ww`7($Y zFFO+b*sqrKAR@{s791}3#|s`P*hs|lD~Psb9VzJ(iFp2G!PA9)p`f!G8)qD)_A6^MbDnzAgBX;J*cfFhSa3u3%Te9)kS@ z_Y)j0h~=4j4%1wPm|iJ7KoIUvrRNGR5Nr@!DtN5m34$jJo+h|e@B+c>1#cF7jF@3r zPYUi9d`a*P!FL4zBlxqRitEGkwny_}95nd_1^W_V_X7n>1cwWj3yu|>M})opLvXR+ zGQrh?DsB(?j*#>*f@cYyE9g*8G?Hp3*& z_~5y2ybrw1tDpCS0r{5@k?$Fzv5!1?4&|u!M;gmPl^@;DN<&(;H=a96((8$ouc+nl zm3SElu(es^GINF3VYXUD>P0(6i}3plMR;Ro5s5{K5ZYw;_21lV7ybM|4oke zQNk+AV!jVWf48+rU)L{M)ZBQemQYjh`isIsQsn!CzGpj;I8yh(CbC zm(-<{x}>=t-^MAbs;w!4e$C4lt!)L{|M7?Y7$&6RaQP7XZR#gY5V_^D+Dm0U=es;6;`-0W|WXT!!D7xK8EQ8Hr_} znUCRjDhR3k=BDsNcS-QO6W8QtKI@VA7QWhi%)MJdNac4K_+5)eqI~T0M!p@mHqYSF zYMz6xXc{r)9{pu%zRTuY*7g*FxukzhEqB6WmUS6!vfK{%Z_53k9l!Vj-M%2JkKsqZ zoXYRh$8{_?`E|s9!|!`sn`dxo9Swd1cp)Ei?`xz}`30ZQHb#CS{5Sj@JYb$7i|yc7 z4!>qT=3W{uQu$2-zd~dpzcBtAemTg;XK4TYykBowAC&5A{^dRX?~Xr2lkbtUE$aZJ z&Bx^1Px2Xh<~jNoXib{s^3xCbQsrw((KjFWjeLwdN3%Dnhw$f4@WWPQ;=^+JAsXMn z^w-F@5D#|8br<|6zaajz%oH=Srk#&7&6EcXKel0NzFQ&Rcykl?%w_TL5u*xIKBfDY zj2u-mbkxw&LVWeFB=zsek;4lMM~o~PF;eAUm~m`;a<%?tJup-}2PF71UHBURTJ~@S z1FRlaf%WH)e>~iDms4F*jjKQH>Wo67PWjrTHtzFzW8=C-dpn=L68?I9hunw96-Eo2 z9tw{|gr^1a%=fM5=pM7pmuZRiLh>ew|&>eG=2%kaOF@w--@3#J-Prt4L?O~<XU-d8S@-s8n=#Gf{E9~QehM#~HmI|jH+cN`nN}+;&7Rp4caDTTrH#(7#dB$C z>AwyI`0RxRxU(6(ENyE33f}RhpO5K9n%};iM1T4w%uIbgo9~;$y$cJG{j31~bPjQ7 zu}{Yz2R_mAzJrY3KDpJTZYT9N{^6DP8}veNN$x^i+dJ^b*@ZvpGayg8Zxb$kld}24 z_x>MPJN}CytjB)@dKD)~c+x)_vt*xt1;!cM|70IL@Bb4br2DUi!hU}}u3i5GqN<-Z8tGTR?3g4^^zHw2x^--w(Y{qy!ikeq)yY9Zuj@MNyPITx`9BzFS$Y2ONDOX%9--&^$DzKv_#X$otG^N>NjHBs_!sz>p|*PX&&1tA|5!Mp zp8gY2N-zI($lTk1Z*PR|__N```ugtxx5fTT&^sFabN0utBl};23{U$@9*-ThDLeLKNhXL+g*-4gFWtD5Nn9XJrJ#1|cK1Mtb+&tcCYJZM`x(sc2-|%e#J6qt)J~T5j_nS|y?1SQe@OP8?G~VV z-nZSOAm9hKI|oYt3%|z)<9#9BodjEaG2Q(UkH3`e@@q#gr@Ip%?knl;9_aUKx?2mU z|60162I8J{_W`)_*VEl=@c0|)ZW)a7-hkT|s@xZFPeL=^A8=nl!#xmi*Joo+(7`~k-N)Jyke zJPdgcgDyy&xQcySMUNHZ_GfzrZ@b!fm=ML}b)<;8APB;EoLPs9-O%_fUOa&+JDV4s zAmKT@*aM}u^1=%x4{yN5SXA8+yjTsLIKpSRC;~qZY-QX5nel6v_+@m|B)_Jf@gr;u zzmsWYd;$gW!;ehNMVI5SrUBcDCI z*d65KxQG<;7NiTj&w*r>$NL)6=^vo}Y!7P6vioPVPh>7d>#fOL2+f)^UqrjLWOjop zt(k|xC$7z8Nd2LicR`lJGGBwRM`pf{oJVDTfUIgnW zagn_V7x*&&J-D_>P9Taq)v%B2}u4(u_N^k+h zb9Ng7x=F`0XQyq?MCP2hvL&&s(mGD~5{e}>*f@y4} z2Mi&@3i2By&Vz>FTEY9_Dx7~B0_t}bdW*Be5YU6su(yr2S3!c@QuKA_j?v08av99$ zJUTk?B&4L6Pmgv_rkHoZtvSyM10Ost7(6lBzJ(0j)zNN; z02r)>uX6T`?s_-KX=&MLGZy>05Ik8{@K@Y%-ZTWLbxk1%ZyN&CdLC}vdDrkjb_ns} zXnQ#L=bp;UFOSY6|J*A|k@(l>0L7ya{~qm5qY&NugZ`P}h)xU!AC0!xlEDk;bIvEi zfZu^}z8D=KYclwLw3`p5gIN^%2Vvla(0=y7pG?J~asGgFaeg)gXu+^B=NChO7Wr(x zUk$-;1woZk!qt#vgDb$&Ml#|nNs2!uZj!G;M?zCR5CMM9CUN84i{V{SS8sq?Kg zM}Va}WdW*4MY7A>`BdbtLePU{+U%q~Gs^5^$smV4H?vF|#66THrz}9$ETwx{)>X`O zKRr#4vO@Zk+~;Vsg=K{oA;D7mmvwv=nZn&M!Z-uVdS6C*_y!u`er3Ix%R^qh%d$Qt zuk*;OujbW>+}Sz1mbri8GDMNA5ZR?!9eqw-ncWRsbJJOi`DLAV;ch2#A;XbnSyj9_ ziZ@4zaQCsUMkj?ESJrVEGKKq7xQG#s&e(~j2v<>-wUNBGVr+26h;Zai;f9yF+i)48 zC{~E6~V3#|TJ>)Pc^JC0#oa4#@l!j$)E_46I zGF45SA`H+&wBn~4jz;m*g#g8aFM@+}hRNZzf|s)QooNVZQZ;8Af~lHw3_**zvCK|~ zez|^D%}FAruOAXy%K}t@Vs0yQXCsrYnoHVO&E@T@<_c4UshTSdL6>=cnaxds+=n`$ zm<1H;b^MnHX$Uc=5~|ARLvcRV5;UWLoiiy zw;^aTuPL*8p>O4uLJa3RV>KLq?kNjU0gCz0GItF!>8jb$zG@z8Up0@LB23jhVF`u1ln15E&p>f@mIWvc%Y3fP9f+KwVu&XYi^az}jguH0_GX~dbjhFAz;Y9gJu3~2H9Lkve=C|zU`2b%1Js$C z`ODp{xzMaPYcr!fIWa7!$ps7nnq5M($TS3K_BfkRfQzeC782$d|jDw&s-Usl#T@CBx+b>P*eL zmAk895y4AXc?E_6+H3-wsD~jyv-NC%LPLONw_uUw^fUx$){hRLmmxs20W7SyAwaXI zS+9Kz0h*1#Hj&fU5TMx-^5|y>(Ck?j+usnhW}VCJb0Bo?cSCWni)i*L3maG-pw85+ zq+IQD1TSO54l9>o2~q`E=5WIiQa#Mt9AOBMY6-{2{S5*A8g??c-1fsu-# zMfWXq{)@^3tQG3Myxd*L4UiQyi$e?pG*K3jartw{B2+%A*6Ti$5v}R|P+oK_L?&X7V z?`+ZRNhsu8Q68Yq)a<%)_e*M4Nd`9<2GDE|UC@n&0L`xB6#phefM)lz)7)$b(CjAq z`CAMDn$2O?ywwn(+2@>;-DU{TYzqzec0+(>`K+Bg3;~+)3$o6ghM+auUT(9VbN3F% zy=z3Xv25+T%LCMznmttRPDiHTiR@<&m+NIh0KGq*MLc3S!r+V9h>scqo`xH{uiQSA zMVv+(e?W>Tq{fex2Us|Zc&6OFl0~dw8}E`L=*Hfmo$PMQac8;x6geJ5g`N_QH-VA! ze0hLnk>hLS?tjR!f@8_+!Z95cwTeZ*EgZe*)R6I|a=Q!qW3I~lif}xYUi;nh0LvoB zkIUWh$P|2y&G)G=@S~>xL8IDd2*?bM|0=h+sh*q1{<&8;?gJ<1v+@ATBFAsb-A&}U zoK^F^FaR?$__Ex-i44A@O@A#69Cq&iln2O~41OzjIhzeuaWMX)ErXxR?JvpTRBmqk zA`H#}#rd;5K-Og7RJeRcUvM^^o4-QOhD3t23cDEha=)b2`zrLL;|tcFTM-~@G6+_< zD?!SOO{~SNMHqNsu|KophYbO>^cZFAWC-a>$;=A-EEchgbDnG|Vi0Yyb47rKvxpuQ z?!&kYayH=f6b5X`Rt|A}gaGcWwyqWSUUIyIHr!n}_MwC8TM=Mcn#LF?v^{P!hrrINRPEn2p;%Q z$hfM)9)Qfbk8r-xBpmy2pg5u;z_Q5kxC-}6WYRWtf-s;BDU;b~8q=7}iH2ZI<|I?5 zF_}$<06q88LN*%$>UIM9i*vFepl)Z=Eo`aKz8G=`M^LlVOb*PmKI0g2hRI>9>`X&| z79De(qbuwXylC!TTG_D`oqIE}2F>7{RS_6~gq3w0{*bJ;=lyui4z9CUKckXF)W^jY z?%N;)pQ6{i)X0J1?-g3XWrlzX8p&>ZxgnqpM$kuIVF(!h%IQ$AGz1vm1AOEvLqMHg zM?ZG8A)pGUFvm5fl2L^xQ~hfVL63G9RM;NOlXLkhNarGH*ip=QeMNxkuwn10aJwT@ za6fkayG#)slx5sfVMoYdI9=3j!oXqYyQd;R)?~1w!d*=U2eVEeO)>~h=OF&LA)vir zYY$e~=aA!adcc1Q$4l7!J1YV#iyU`XxG$08Ec|g^6b1;{2;PKda9$Du#{=>+7Uk-eBx2|DoeK95 z5P~0LV&J@2(QOx=^?7<&K~8*}_YI-I3U(s<4-BC@&SBC(_?ID|^|06cMumL_*ySFL zns?r+Pi&6!dn3y%91QwbZ7c873j0Me_=YMST)$@sIYVTfWgiIxc7rFsN)3g_lf{nlYw37Zbzn|m-O_?)Gy^h5*ZcpDmbODIFVzT)?XAU6XI;gRQLIuBHg|$S|FKHz6RDIY{-K?j{Gs zRBOc^QYKC@gWrLr(^GQzFot>A;(g5{x;Dd=_CgexyOdhz8L9YW|H=U6rBp?g?x~dO zLw4BG6psC==TO7ZtJ-J3O8a(lypa+Q7LFIP8x5}vuq<*cuXNud$32`XRvHG-b2Lq9 zOr;*Yp(k5>|4N%%y}2i|Qbr5MAe9+c8DLrDIKI-IflR?2WH8alh`-R3(q6|hj~s@3aVhgH)_HAZfYR_(;lN7wZkCxt?GCE!`Xb0a zPNbgX6$!wbqmgsqUiP9%=}XYB{^tIz!M>Ew8lK zpupTB4$X&D>JI)Zr8=TAKzUi&$5p!jqEwyfhfgqej^=wCE#_=61az;jDba7kIu7|U37~fII200uC&up1G$WLb&jpnou?rkiPI_rl$TO%t#pSY zQ?R@c^z#e@NVS8#?0iFj>qi5hS!vHB$MabH*@h!1&V`i$mc`n?veNyX91o#$-)`y_ z&ht{X+0}*s=lKr1#oN_P)31^c5qogGFh zDAJks{fHqzk$airF++f%UCj!5+z?=B?{QAQ(-2^210JW=|@S3X9+{Y z<5-SYEM1~v2WMyKKm<1?W}vy8CYLxp69b{8oLUk@gch+ zUWJVa5N#3yx3V+7ROw~Uv9m#eV_Xz*&%~7utXUjM&W2PR%@RXEzf^HFOAP`2l852W zGDC2!yb1WpEoZqQV49%vSh6k>AZs!>Hsa1H0s|FCb6iAEzqp)JaWuyZArVKj z!4RONqx2o;MFM0^2A4$K`eHCpaWt0+gG3z76{cd*I4X|jN<)Aa zDvstVLx2`4j%K?dpmEAM*SW?JFt}cgLY-?30jpFMM{}JaU^$XT`K~tvpHk$)h7)X2G8L^)v0~JSew=lSevOE|GkTnOXCnH%O z;xfp$mpM;I3U`6*E5sj6mL7|^ehhFr#^s5Kng`{+1L>Sykq%_d`hGEzHH4W|AkNE? zlt7$UB8fnpw;~AqWq4Ksao&w219A35veuB73dDIs^Xf$Il=S(C%U5ZI zD3TQ-I~7jyNW{Jv*PWibBR7bG3Q^Mh!mB6xmGYV}8?<9^7bBY3Q+Xr&@}Jkg|9zeKXelb4F%`AxJUcS`zg z#N`XVLKMjgk)6_NZ^UlFbth`kiBB_cRy6B$TxzX4MBB8L8+Gr*JsnjOi0ZcDtFN4n z(GFxqtvW@s-e4vb`qMe8+e(H02RT%AP4TV-J^rx56N`?OPPSL7cG^;zZ>Cm47 z&8ri+Q_|e1I~+Gd6baF_xKvuDN9~EY?nEs*@oAdykf=*{rlUEEquNozgmuVIsSpw& zKf?^cgm;V(LL%g6f0F}yIV$95lp*L^7#OwRLxDQvXHZl-N)_@mIvSvSlxkemEyAFy zgEt~k?dK99KXD->LVm`ZB2cCZ`I%q{y3C5GJp=4?$j=xlQ-%CYj0PwT%bXr{UuBus zafvWP7_cT(tkW#R(I`Gg2#L6sxh4nJS1ROZo*|gHmIDpJRLufI&|=m^?O!OS3i+8T zVycjze?$XRfMPC=x)Whox@wlRubSoUtL6|>gsGYphM>z_7`0b{oeud~BxS0QpOw)7 zrD2(^QTJ<>sjB8sVUVbrb%vvMlkmT{WBASIw68Rdbpt!c@)ahM>zlA!=`CnJVOGqm-#a ze$I#nC=JUzFY0z1i858l&xM8ohMi9eA>2iVfMG|4{A@D>3_B|1=VC*^GF^rITw(~Q zD;4r{sUeteO=W3fpV*mpBoGV ztYlQk&rODaF<6EC+-wLKgH_1SErx(G_*^bRK|yyJ z0#sE&LH8H}G*dxA_ZouMYQTtsoP?03B3Ii2M@>VoJ)@1Ons5@j77^p~+kD~1&Nj^4} zg0@hRB%c@p+CoK=d}auGZu)N2t_3?CN%FpwsUk_fiUueR%lskgzQQt9B*{;P0SrP# zlKgB4m}{y?l3xu04pK#u{3e7%B*`C!fc76;h?=lsG7U%jt4NYGLx2PrAHR*-KT}K< zN%FmjsUk_du>cjIm>Dtmh0zdGMUrI3bk!sxNwN$_NTqfMvrP_Ejfy1cAOysB=tz>F zA;4}`BuPg@fZQsQB*zfYXTP8#AyWzzQIRCMh5$oWktAV5Fp(sk3;~v{B1!TLLF?|s z?EgS59ZBMk=}}Qdl5~y*SS!@MN6fvx47#gGlAeYEnn*>G^fm=6d8intZU4E9zyF# zlJ26JiX>Vu(q|XkE*}-x$=!bhFgn!V1cO=)RGE6_=h3jY1sZuv_Feb;Rmy&2o-*CP%Oa0 zSwv&Z?NxyyRQSPCDIyVmu)HnD`j|Z)nRWOZQe3?$lM zWz6101}fTMwJ=c828YH1WKEHdiMe-?fr>U*FANgV2FDwMR`Q6L{U$l8XoI7Kqlz}z z5DTy@ay%vG{y>f@+Tc`S5Y!A#irHN&!9YbDY!(J8+Tiq9fUL>j+?cyRGU;f8^V>2w zD`qbs0~Kv>jxbQs1{cNxWK9N_$J}*fprQ?~Y|G%{n0+xBsAz*rg@KAT*d7azH5uF( zbKkuSiD-l8jEp#k ziEwTIydl8bsI%l3jF*JBQQ-$K8UnnH3O{(sJOag4_`%DD0QaN94_-9{cpG(e{F>nb zZ=;Tm_m~`TtZTYLj@JzV9ZLl$ykQ>Ey6=qHQ=pa(PEr0e(~k9DHsF7(-OR!Iwh76qZf&KKeh! zJhTUN`j?2Q0uH{41*ia<=m+%waS-#{LS*_$7_hVP3rfzfLf{*fIGUpWBXjQ1T-^I! zIDSC)_&fT)aP-C9R&rD!3{G5+&vaTUgdsx+Vn$ZnzJMH62t!(2k5MXwAuAqWS(Gt1 z?(QT<6~fR-7$ia%x(Go+7=m&8GjdcR3^~G4g)nrB2Ur$4_Kv%^RT;zVD-04L3N4QGdWBMLxss<>~O3h zKnsL0^oZN9K?@zi&@-MA!cY|t@Q#(ms`waJ62bu0C&%4B5mcr+QJ*SBCQj6+2_bQ! zK3xcMqCO#RPsG#uME!tx%8B}ncz}1TEEYEpS8}3`A`gtaYgwc^$Uewui49qp)SS3| zAsMQJ?0M2$>L7bzJU}*VuBCDJZZeoy08=~IFz_e_4RQM|GEfKEjl!S~^LA%NJV4fD z&>DAFMZrKFWFKl6V3wl}vJW!^OhnZ|_Bul_2ib=k0_K3~Ao~bIK>t+-*+&`zY(^bq zA8pzS7NHKZk1+(jY-ozxXG0`?klieDtAp(I@c=cV+?(RAF9x~QLH5a}2*|AtvQH60 z;vjpA$zi6dr%9QKgX}XTN8%v+9P@~-%?)vTAPUq6*(VyQAdGWvJV1FV)x~jlHlzA4`3 zAp7dL{Tw-}gY0XCqdLgGB_3c|=Y_z=+0z?@7lh!|jq^m@-bo>b;b_BoQiPb)ABmUa0g6W<-i*89 zYPhx;c&nlFw&92}@61HTcavr2O^YFL@jW4=IUJd0Aatc|nXkp|GO)|Fv2E$RE@iI4 zZlCjEJV0r1pj+OpbPLhpTzBpS%f;l|93p) z1pmi)fQ7S&KjLoocod;d@IBRPH`M1bC-`ZGU{3IThG0(co$91i>I6UC5FpiZ`W4p@ zv{b*u?O`ZTpWy!%PdUL4R0k+8D?6v!y^2z)6a3t288%?I>I6S*2rvP4f}dvy@EYm_ zKi?1_ggU|RRxRsUcnx)e-`x-#Wrx|-_S2L~o!|$n^?0dH@OxATC@-bzSMB~lsmcqX z)&Ro*QmGUCfrgN+IQFWxyG{T{b%Ni=aHNF|st&L$tMdwvvmoN0bpSSgc>rdGc;J*4 z;;E4@#A6#L#IqMU9=<&y$HRQxiX0FBQ`6*l_~D2g4|DfFH^klY&LQqDcMEafxG=iho>)YhO7YE{&<@Vj->?t3zD+O$c%Qc0h=Wu*o5=lct2YwvprE zb^3|g5SJ@6LtJ9a4so3@H^j;Q{19jC3qqV!9~9z5SdNF^j^*BsYFrdn0jlrBa&JRQ zj)~vZ_m+e>d0ZCiH4bN+p;r7|5!#8rt3sT&H0k5xXk3nm)nRcg-s`jU#PM)E-s=i9 z*ctlhxH{hJL8Pt$j%+z>;>cDV zAs-(%N46Z4aAeC-07tfT-8izPzr~TQI$3@!u9^);w)BY8Jo)rVwVp2Op!uVC=wnDa z)00oHf%9DUY@Fw^E8#qswtKM0%32KxsDnAOr2(oV+j|T#1E+Ghwn+%AM0RILwU^dx zKLScupZzibFRkJaQ+AsNkD5L{JAGsh(8KMI^aHYUC&6x??vI3jT^H1X|LU%I!k>|E zSzgQACk>ezy#EH5^m8$s$z#j1<9w_Z4%PC1gTCPLujquwEN^CKWLoJh#O?Hw?uiGQ zvX9~eJ^S*3IWTvR|KL6>XFdu*IY-;bdbD>sAM>E=Njb-7U&F_43-hs~JK{0R`!t?T z-|XGQtToB3r)Iy-tk;5(EC-meW-yw4)<^SpQPfoD)f!u!H(?_^}ugumbfbh7lD zR3g*zJ{~~oW^V^D=;2F$(A|TJ!n07Z>5ukeb$HTzX@x;}-t;H>P*0D?o7QuA^BODt z>28$G<4H>^9O=XTUA?IsPG-^y(^#o5n&-WRtNJ1RN_VygvU>}ULu;h(>CR?Fey`Qb zmwvy^_l@^%WwXB?_y?~qL2ISInWOaSUX2^U^m~IWp9urGfQZn&PD!;!GUzc5>_C+BRWeBqgck?QTq zxd$nKcp&Sv$dj`Rsm$=}J&-EXsbIL4?GyLpe2ja!;pbUz)AYU0VgAfd`g~7LU@Cf7 zcrSA<()S9jetg$j10L$XoPS#J2O55WI&?_w<2#!Qu2Pp2SLLU0I=`x)KE7kk9SW-N zu(JBITlaqeEWzjklZWD~JRm+~h?HAD$g0Dgm&_dtQtLYou5gEz?vUEY_c<~J{*euZ z8a&>|C}~H~2MmXA$V^}22`)e?%wO9~U*_pXeXQ_^LZp^^x=|%x_z~nxKiJca8U0{b z01QlKiyY$d_C~^4gg@!|#rUJz*8gz!1)%s>p-wG-Ci|oR2ecAwcylf&k9%ABz{RX` z{lM<*&eL$?X?QKmKOc-de)KK$`*mneum3ST?DJoTzqWq}r=R})M&en2Z}<d7_I@5m@97LA?TR)tx|Ae8KOjzDy;rIOSd$+Ur%Ooou2;C#A22D?4OZ=*WTw7fl`hyO=!9~3m6_bjlw-F^JSyoyrV< z3_bnhJi(*EBpB|KiBy#*cshj5g=rA`_*g)o89MnR9xo*r@D}9s`(vKq9+o{7-N|3= z$=;6KR(J>bkJqWR@CF!#e}Yc=!hCtDf1*w~R^Vn-um1p#_YCsn51aS#FY*L0ss)#f zLfl&H=}8H!@B?Tuf1^%$!rf3;{v|q<7B0dV;$Q0N$tL%PM^V>ho}QG&7v2Yd;a~3Q zNo#b%v(SS6gFQWW;GRF+8xGEYh^Hr2$PAaWmRERsviIhOFDyZ7rA~DY$EndOPfrTg zExf1$Qmb{U5Vf;8ak}75-ghE8<|htU`PXX;cid=`10rBfZlw=#9MPUQ?*-n7E&E{T`oty!Lz4X8U2E6eD4LQq>Par>yh1iJ!~?g ztoH`>=x*MfUj)k7-sdVxSJbul=R#1bI$sM)_r5(bpU;Q|`Evb&Y#3%nbq;@!z$zH9 z9}?qpc*9pvz{CVKw)zV)U^*ESb9NwCW&xu{GY(LRV8Okpl#EF^6Tu+2;7^!x#^fA| z*tuXb%E_3fI$XDc85DB5N)!xP-ehIeW}gmbg$3m>nv5ChMy~>PjEtEo(Wjs*nj&MC zO7tt(jC#nJm&IoW6nw~R^HpMC0S!OnKxOxX3uyNl3sj;c^aS)6Zh2>yfEMX|6;geC z*W>Sg593dN^@laxpMP+RmD9_Y@elhG+%8()1R?7>oeW~{8^hpGpSKRzmiJ@WQpTE& z-yu^U-_Q8FU-oP;nTnf=Q-3CLYa0kXhG!h_K8bVze?c*0Lk_)^Rd6&l+o%%0f;AnH zI8i111yT6yjFVI%v!FYiXU3)+<@E~kSWlZ(+vFDHu{lmwiOvO2GTSLC(XHSY3^o~C zRHCq;FFHZSsVdQ@pd3R_#%U@spr8ZAIX#D(4lbZW%{U{6bz5S2&m4}_nciGTU7QWa z*y_o6A=qgS#2yDr%6KiG`K*FY%(h1*JOxf)Bwo*FuC#)GWg+oKem^8Ktt@&qUdm=> z)+|)Z$Yk34ExcyNTi%yZTo!AtHhHgP5ef_x=i((sR@M#_x+>+~KMHZLB9TNT4+52#`t!VbKy;-jOz4G9D9>z`YI&4$9jp?kKXR-Nf5F_HDPWVzT~ZOi^%{Ns4Y@Sy>$6dB zffjvzWd^QW!?c!?F3i6+Ob<}98?6&KOy^k%BM7Y1*Gox1TwmV=g9;qik#d)8gUt6L*eZ>9N% zTO$|CooQ|EtV2Po-K1U&Aw4`Z=LR++y^%K(5HO*6| zYns^_Q?eCGwsnbYW6}1C8+0ZoYuq&STF)fa=su)9+nzw?iu=(#o=K(bV;Pv?IQTz` zw|xgDs>`yfZa|gt13!cZBd2t*tPfx!SypsqG2Us8|AEbE8L<~&1^l1+UPkOF%yjra z@J=9l_6WQY75@WABjUu<(bG3O6!2zu&7PIl(G$!A+dftxFa{(z(oU8)yDWfL1q3Ey zK=H{P6lRaGNOAfpNcVZX*<%6$)3OL{8F!Sy~|VU?7kc$PA1^u8w(aa^)bGUq3`4Ls?+PY`LjV zW7?FO$CHJ0hA4JYlzhb%T6Jl|286C1P=T0!Br6XidI&Y7G(lZblLC24 zRV@qeA)3nl!qodoA$p2z>airbmsEf}+&lGQ^ehTQ&HB;~`-MII^K~`jD1+ny3E`xg z2exTXA@0ZLDEc6gK{WzJ9}G=d-%2RFT{~4q-Y-feV8~L%u_{H}63hS+W;QmzA|GxY z6BBD_k!Nhax`U$n=XdnvIO95>7g0hCvr{Y~E$^NPEO$6)iFOy-2=H!C8@c&-4-CIl zncDs*ACGtBc0MzLt};sB*c!<%g`T5}EGZsx_J>eqZ3%@?tvn&3$}=(4M#u^gQdNuy zRGF%*(8i?F;MR?Na1?F%x8Yt@WR)h%!xk^atH@uKtt->AqHPGML+od^Awe!wbLuA- z36C|6aFx28MYu*&2|wY#&w}5+6c>N_aHR5B(+T?V*~!PJr#?PC@iDFNU_gENR%!mD;4FAE*kPKpSMlylr zv@K&eD0I8}p1M%Ectwf$(f4&tX^Q?!Zv6b;@~wk&^jiN!)-=zr*?23o{*?&Skf*4q zxVgS~NlR04OLIeUa~*$aXiW0+~Eg4!` zS6V{i5Dx~#aWdGXrit5!!>H#ZJR)Wy2iW>qD+My55dKDe==wWWAQQ+@Lx)oWMP&4eyX zr>$7qQde6wvSx&-ekl9D%e}b1X?Zc48~@nUi_qjN8`h##SNwloZo|r!e`9O)sybK$ zXmANI1oqRq#&r#iP2|M~G2f`&znbSZqA(YBie$e}@<+1Ht zgc^E0N#Z+}#{t<&^Ld?O{tdPL)5&&8$hCtii$^CXsYD_F7XJ_KWU1`<#dl{@x@n$&avO=HnL@Ee zN+?P*fPxL|Su3`+yV!LtVDBrgu3Z=GuH9WlQCHSQMc49so|$Lvy@|Wu-}jH-FMi~C z-}BCU=FFKhXU@!=d++GZ0{$)(D#*YO0Hn$Mcm^cS@9Xygty}NW{@#20gED&*`9+yI zMSduA7Ad3sf#bn(p+AVtKkh-o4sj~mZo@}*OF+gt!t?T z!{&HXb8UT$-^o9F<-9RoU1Mx!Q*#q;A?iW#B-^_B)~1$7Q?#)<5^n^zmb#c%RoxhC zu4?p}>J#zGWJ$EJp&n9s?QKV|Y+Jsfby3@r`70K9971yz&04;^bw#>PV)5q6Xq6X< z*EXo$L}g7)lABX!ZPS$2NJ}Dt%A2YWj(ZK&4e|XbY)Zu6w7j~ua!TA5k3}15D`zyM zv2BGSC`Tkp-4+{$6C+@lEE8><+0b0yTGvuj)7ns9UDq6M^rDICL_J=heoA!hEnhf) zN!#2a!~^Zgmz~^+O6ayJ-rUTNO?sBaOXs#p4eID4wV2>gJU8o9pXaYb)z!s@GG4#&mO2 zeUp(1)?-DYbzweQfpBAmk#B;L4_bEKeEGuT+Pp}#YDyQ2f%TTOqMw0@)+E3BY0+97 zIy&t|E9+WKKh#z?n~EFbl`xg2>M3>J+_q!%Ym#2`%!arZjW(q0x4tQg(O(a}$D3Q@ zbyoFeD9oD=NlgsdN^|h0SJ%bjGd!c7x(NC`SvS2zth#av?5M6OS~InEN@X=Vx-yC% zl}{G3##&ip1Z%Btz$kamoGnHgtEW^oBMNCsTBIwI09!9w*Ib*{x#*-=LsMfkUTn=C zBC+GGQKqb}fmVk>4{zti;?rQHD7bj}`~_{Z=E@o|x?*TQ#y2)U$&`H6jfu+E zcr@Bt5`o25HaEi|;4AYQV&3$cc-@rds$@|&Ch7U;G&Kg2ojhyq+;*c*=r&1ADH+t{ zXo^-riyBT{$3)`{_?p)GY4OHHP5tz)wKvvHNxFGhEsjT=8jVA5g0UDsp7c>hZ`N7G z8ff{&aKzL`BwEvG2Cx~`4e`cmQ?!J(8~2WCTYc=(_PI&!?Anx2@T|0>wqx)^qV_jS zQ+-l34Wlh7RL#`-78u`*XgnUn=;d1oKxWNtFM&Q{_0t-ojg=6I;*PPS)3`Z|+gNR5 zLyM=Hmba}~xy);A#Zq9!M7-(vCp8L}Gt-L|(=EbCyv8P21O|tKwPbncA2`Bm>fsjK z+m<7kL;ZCao0ZLtar~IOn>>u6U}#1YQ@mJ1OH<<*`ri4b=?n}R_MtUqrb*UdTtvLS zy0eQgjiO*q@RaA{Oln886~C$qlWq-W?PS>~C*0~fjQ&JrHQlFm|M1yTCx<}F5HMZV z);GrGyx{*h$v|*3^05?|J!{TUP+=6qxe+|fZ{eC}OBXL&w2)zS>zvtXI_AiSZ+0U& zRteGAUnOS7N_BigWs98=;LN=0>gH)_(?dhLQD`o0jMu~~o6=?j4X~zYytT3gGecc- zb+od%8bh|V)dZ;vm$WW!TMSz;oE6yA)z`(nrWQmDY!3y4x0Go`ijzt-vk8Yss|$IO zkJtoG?8d&6RQdWuYh^Ur(pVYQ9OX4)_KvhxH5Iour#q4=bkg)nsJ*$mHV&IlZ#*KY z&Js5xpfNELZ4?W%R{9P^;5rB);FLNO z{=qEbjnm?>l8H%9>2rdey<8pc^#rP@Z=BhhKonR7`@llhV+eyljg6>{CV8p9FgGK@ zXi3cnu`w~t=U8{f;8-xu(ngIoJTUm95%^j_WwA^ewvVbf-q??mI>%V-J2!r7>YJLq zrq#=v7s8eiUMw*$m}%EorQuptn_evjDqWAQ5J6u{!US_^g0aLgvlgvv^QOh3n8PT; z_++TT0Gqz7J^?8(z*6CY@w{e|j7IBQt1!`d&QB?P9)sc6RnM>!C?+`@CTEOg?Ms&- z5L?*BXu`b|jn~w))KoUYQ%tFDg4g4)aPGhrq9-wvF9N3~M#gqHlu(V{l9h|$uiCLM z;=${tCg`N`H&r2K$E-kak(#N@xF~6j%xsQ3Wwy01!~%E85^TA&r6!2lI5eP8zpG%? z4OkT@cxj+fVrf#<)HowvS6grT1LKs+o?!Yetw)wET-H|n8y9PRr;QjB)isEXX<KeI1V#b*|IU#l+h;$RAAvIig*2HTvIZ_>*V7(4Pw&v=B#L6l&mJrPa;aF zPGGEJUhrC?Q*C^drodU)s6fx7&O~a0;6O^BPADMfrnL9azw;K(H?JlQ6T2B{7HK1F z#0qI~b9%>M7BVx1=J=E&PK}nDdc+jy9vF0GT{OrG8P$cc#-?4@ zj`6DM8Y0d0sVUPrVW;A>^?>PK81PDjE{kWa@>-V9n%|Z%TRO&(IHvn){F^1ivXo@) zs~9=Ao2O<9v~n_MSacx-OKakaRj_&P zW3{!nV^I)?_TX+Q+C=+4FDIBTupwE=ez1&Xtw*n%wP@kIh1kvRJWj@V3A&(Uu*UTu z*JPMnOkC#zF6(?RvHKe)2#{t6SakfrgVDsp!HL zm{pdya=ielP}*!3V3&e1a}=?dS$DXQ45ns7sDullY@09&u_l(Rv06RFg%L3|B+=^?I>s z*f&bblYKCPAHd49MiuH6``@C6mQad848f+8; z56G%!nr+f}N_1nB<7{MTBP6rKnv|4Y!>r1ahS14V*tiefW!)|!B2j9+iyw@fFqO05bha=LQHTYIxHQZ%`j3hg#Eqi)2X zMpiQ}%m&D`SS|OTQsO~bPPb+xHvX@*YsytFTDoL@Q8F6k&&Olp_#ctn)c8!gI2+2j zic)=nl}7`t&`tblEuD_7OO6=3kDnTL+;hY*tZiGow0(8$tR-+%i@9B6f*k8o;Q?yp%3%PH#p3?F!_9e>n~`_ZoJwc#W;oZHL%%FN(xQ2n;ocF zEoLxp!Li!em^Bwu)r#dSmV3+F=2QAq^$o4qM8l?VjR^|esv^ z_o}o-UBVeNJ^n_|ELzmcu%?=)q19d3>d1h=X5YS%dQ5-j)C8Sq&QTVfj7;RY1a*rO3ctxFqa$8X#SyB zOjOUnn8cPlym6`q1_E7|sb+^Defx`nDr&O4$9PS*u%1RxVG9 zg?R*rrq$7E6E`+gVlu^y%vX~|Y=~<%OE`h!yt9@^yf%hHL+$#tikp3N7A;-gW-1-v)wC6`^DBTJ`2=hHQ%BwxcOMif(F1jk)&)6bkHVF=kBD{fU9 z?*t!_XsoN1v70>uoq}@g#HJv&OC2L7rAbV0ZNWJ&+HUi7`DU2bf$%^8kY_g=;PG$(h&Kf!W7N z)`y%5WJ}PeTAlxPoePF7HFlrHtS~rK%yFFIh9;+td3s*-qgm3yrNnq(X(kis2hI<& zQk=%=Eoq}oexeH740eRs&^vV~<&;L7r=Mv8Q#VA?_x6z6P#whti4e(dF&R&&eNoQE z?xiLiG2rM(Cp}KZ_DBtlNlP~T|0>fj);4=3tXc^%srZ>Y^E^&X8xl6gnv?RQ&UUC< zn`M$*x-e>ol}(3Hr5$uQeYG@j1oPyF8_{;Q(ZV6^_&6EAMH5kbjPAs=i~Lr*nX2g- z>cJ^9j?x%)m^r{rP_vUO;S$Uk++)FF&ddug9O8MC7>6l8xdPC471V&smej zu^@JPUT!^1J2bm}X|6Vv4}u(`WIjlmc2_V0=Drg4_!eRJ0|TZmKBXQZDhHxjj-zr! zF&L7Fy<6v|0+O^0A~&FTfZ{wa!iTha=-3u6ncIe4S!OcW&Glqzk=JBS1(TsyN^A_m zw7HtoVW;DEw;!jj;d@;EPm9GcE^yv>5WB@G&1~RnsT8S3fE?>8q1^*9-o zs`wchK&e4%CS@G{VQ5E@{PCN4*{lgzx7n{k7n*HfhS#a6uG69y_Jux^`F7UK;-xFv zT92J|R2xqB%^Hk*<|YXv?n!4nO4I(b&aa%>Q>NY26zz1xh$PF|i)0oE-5Fq{H13Yl zlKVdDIqn|On>ROB*D^UM%6Tj`*02H92D44YV`fVs^*nXHRFXPiDjATfp7{Ek9@$`T;J@#{oqIEa6q#bA?+E6>m$Sgjk z{gQNEspJ*gdr|rs$5fWfX(>5+jDeX1A`Wu1t89nr9PWiFc;SIB_I;Y#=B#W_KX|EO z5+1_`8wHsF+3<2cE|C^N*?7S@U{&^_7TUFq^M(3 zm#Kanlj_GYseT-@U#gqnms{gZA+*Uy9?nY`9+^l;DavNU2cFIh7&EP>A3(LYafg|Q zvQDk8N!WuxtQy1GiV;JX1W$8vok~RL)VnCWCT-Z4Pw@sV-^4~YzqwiRts zGIgaCMD{DTBTQiCa#hm$x-w$&Ig@gv{HY$;5DhW0a;;LqO?up5()+CEz+9K)CQE9m zn_5>tz0QVtjHlITtavM@DmxDQ8!)(9dn%f$B+ZLidgkq1bsAT5{6m;#i_g|8Knd2F@j zfGyb^$?E#qbfs&mo-xTQ0l%A!(-_p$F2$kE(st{A;xnq5q2S&#E*oK0ack@#?1fg@ zld@z&VHLu_)CRi^+LNgyjz@Je6K)JM;fz{3SAZGNEU?(wjqpDIZEi?A!c8SIxXfNV zIBh;MgI#9rO@p?um@>oGKG7mHHOkU8jHwkxxd67Wn2}zUatvlFPTw_f&C>(BDlnUt zu4jt9W7`*E8d|m#GYwWv*rBiqgD_|AUvd9uerwu(i&;`*#B(iR_<6?DxtdbpqoX9( zd+CBjOp2_wnR)zbQ-P8y$JC6vZD?O?@|`)P8MC#gRAV;b$JkAH=!Knv z)KOO~&i+udP=$`{4U`y-r<-LgZiO_ygE=tJ%R)pXvv{zFqo*3Awlg$z9m#-*Wfw1i z>Rjb!pkgvk5~8&+x7S?NRNc~m$dcVm6%?C&4qlm)oi4j3sRVN^<}{<@ti9`GVJ1iN z;TAjE$xCzo=3+8Vm9!2U4Jzt1!goppOpCW#lBvM1HfLRK^qO%EWnk+O$FN;AKrhuL ztuEsIZv!?IlM@z6K=I&WUm9^03oK1GL~-KOcZ+@Nd)HEg6r>lsZF!#^k#i*HW}?ns5gBo zd`{Brw43gjVva+YVNY>wl1AEghK<0PtXtJMHM!qrKS*E{IA<-1}CVs@j(9Oau z&7mmT?2_W{jHXL`o7{jk4pe7iDKj#$WL>(GhhcQ>mxk74b~P=+9rn5!oernhH%`?s zHsb}2MI%kKFr^~ALQK1Iahut0YR6WNK49Y5V0+M=uUlE&g9JWi!HqrlSvaF)^J#@- z`dn%VDcdEru=A!wqoqZ|n6^~ezPKoko%y+Q@sX`&_c3mh$>ctsJ^X*?HR1byJnvWh z;Y$xr=-soIxi_Cn$3OgtIzNZ+{`g_e%HFxBWu2aRM#g!ePG$M=PV#bpydUOnfc&C> zNbkbax}ENyk#%Nf2j0(Uc=_39p8m^I{G7g5ISK#F;wQ_!5Wcd+^Cym~9gWSxI(!dd z_u3${M|NITL8x!2UuI#be`wdxfY5HCJu>zTjkaGGKo-frbW)c0uV0f7aN)jRz|k_3 zAJDfHd^4$gWH1w2*rgN2eQ@8E@7CoxK69J)mx)i(c7C7VhLHNp#K&qoKgY*x)BZB? zaoWz$dwBTn3GbF<8GbcQ>MyfXFR;Bvy~zTZ_ zzF8yfFVjeqB4l>57}h_)<99BwPpG*({L8OeaDVtJFs}*!^EvG+51(0{2XudYzS`XY zd4D$kXL;IK9`t)tr~AO$qGWrTkZzP`+s)1=Py6FKRz$)azC!ieN~tH z!@Arr?Q(xwm-|b)+~3ya{;4ka?{vA}-sL{ieAe2wfb#e2azCugeR-Gr#xD1ByWAhw zzSF2CbVz;XM9q|2>c2)??-yxvqXFm z&5J~QY2IeyXnf@w5fdPNR7SD=cCw5T&-;+~_#VT55XXAnXT)*%8ZjcizH2*iKl~as zaf1E6ojnHI_GiGw_aq$?3B5g$UY*FfB%{Fd1`$Do$c7G)43-Ha!YRTQ;i1A=!llAv zgeMB=vsvFd;Z4FPgl`Hz7k(}LR`?%bC}jC`7xoh73;PQP3ilF@6qX1l2rGn9A%C`l za@Gr5gog-c3FiwJ3zrL53)cuw7oIJ=KzOO}YT@<5TZJ2h_X!^nJ|TQY_>%Bd;oHIw zgr5k%5b{Sj*}m_EKMS)mEIlmD6ZRJt35N$GI8In5j0mfR{FX2Boi03F z*d|;gTrNCLc(SlVc)sxW!mEWh2yYYKEqqA0N%)NLW#Q|>cZGi!ZWI1XxKsG6up7Rq zhwbSlED#P5?kOBDEEY}>?k|iBYlKb0gN1X1i-aqMCkf9Kt`lA^yiRzV@Lu6#!l#9Q z6}~0>NVrY-Z{bfu9}_a$-CNjCSR@=S93w0f#)P%PX~I_F0wKTdoBWRx@=Mlve~$1H z;WfgWg&Tzr3I8m7LHL^RJ>jRquZ25>A$+|O>+2!R7w#t9OE_9MK{#1>pm4fyp>U~i zrSN#+$-*;*=L#WGUYLu(mwaQwS;BVVslxk(uLwU7elN_%wgLI{7mg4ngiXSugeM5E5pED} z5q>57QJ9x&`41M36UK$JgiD0{xdF;^sqi7;^TIEM*$8-9uCH*EaDQRF@Ce}v!ruw6 z72Yj;Quvzi6XAEl?)X+<)>kMTC#)3C6dox&UU-i1YT=#2$Az1PUkZN^_Q7@y>)TT} zRu~hu2_*eALDI__MCW@xp{~x^RJT zweS+*b;5^*F9_ciekJ@xn1k&!)>9-b5%LRcNpBL)6|NLsAiPF+zwjC1Tf)zUKMKQz zmhW!DQNsO&^}?fstAy)>*9z|zJ}G=n_=)g4VRtMr*^WZtaA927C_GYlyzm_1)xtZ4 zj|(>oKN5Z;%-q%1H&D2bFec=Wbx@vp!efOU!pnt!6h0z+QTU$l2VpntF_0hk8i@M} zCkqc1E)C& zKL`g5wDs*HtPs`-j}#s&JYTq8_^9wX;YY%6guRO_{{h07uthjec&xBPc)9S8!bgNJ z3f~j{AnZ2C))N&r3)_Up2+tH=CcIVnuwVZ!mkTH)css-QCY&yuE9B2B^8Is#*9bQVHwm{0zY_i^ z%o}FkA1pjTSR&Vkk1)U3)>9;$C`<@j zg|`Tw5^fQGF8of|yTtO_O*me7lJE-Q&BDipFAD!5{6-iaWBD};`FmOHhhv1d3jZQ} zMYv7)A7Rh2_PyPOlY|N3;licD3xwARpAvp3{7UGLvwZoZLzHW%aH6nTI7_%%c$V;X z;bX!Ng#2kp^2;7?u}FvyMHqTS*d$ykJVAJ|@J8YN!e@kU2|pM9C=BnXb_mA_YlMdh zmk8Gg*9or`-YtAm_?qw&VQ7M_r?+r#VMJIjoG;|>k5V7>rKv5^fQGF8om#o@n3O zO*l~)7ak^DB3vU}C%jg8x9~~f2f{CfS(9u%eT91qCkU&AGlfSAj~AXJyjpmt@NwZg z!q0?EE}%a82=^3@6~=@u!g<1Dg&o4nh4%^nEc~1BJ7H#-t#5#Ef-ojLRJclby6|e@ zox;b3?+8B=dgW@5aFnoA*eF~gJYIN_@CM-~;Y-3#grN${zqfF2VMJIjoG(08xK8+x z@Oj~Rd}dy zvG63}`NH+WM}^M`|0T?b*n0AX`wGj2bA@Y#=L&BWJ|TQr_^I%FVRqE=?=Ku7EECoU z4->8yo*}$OxIwr{xJCG}@ZZ9mn5}O&;W%MjI7_%hc!uy&;XT4l!ncH<3x5=b4~x5!-PwOYlQ2Bw+kNXx8!m9}+$!!NVq}xsPHx6C&Eyb<=ZHS(sI0+mkEYT{uEG zK^PO_ds|KW=L?S&UMjp<_<-;k;YY%+gg**<)mnbL3Wo~E3GsCoroMxP^Mxyf9m30n zw+ZhOJ}7)jxJCGZ@GIeegh8FHub*%);aFj%Ft6U08zLMdoGh#p&JnH@o+&(6c#-f5 z;Z4E^g?|!0C464ES@?$VUE#;V&xHRJ?hyVc;TqxT!n1`J2rm_0ExbXvQTU|rIpJpE--VwGw+nw3_C3hT zJ6KpEJV010JVdxqc$)A6;U9!|2pOt{B1ThB=0L}6UmC~Orj60R1WA-qVqUU-M_Vd1mF*MuJnzZU)^ z45nLoCJ38^OND0(FBM)dd|dd3@MB@t49hQ9xSMd8aGY?mutqpTI9Iq#c!ID)c(L#* zVlU6TP4^EF^E~en;fun}!ViRh7k);>`x!GW?k=1lJVDa1VX=6y^*2 z3HK20DI6{wB}7wS;7UvMZ!~rX9&*|UMReY2z~xhc$e@#;d8>5 zgzpPK7XDlKy^uf9OMUki_7$3ZRM5MzT(14R0m~KYy&@v?Ka2={@sH25ghr2$)94Wh z7N&fG(D1=~yYU|Q5?PB-a{vt_dpxM_i%6ONBPORj}h@6rcLu4 zZqv&Md)^VcpG%~?qnEE#`1PY{Z_R6;h0l_Wu57FwJ!=KNVRH6Ld~g6t z{=fShfMPH^V{3e49RErC%h2^8Aj@UyzH2!?^5b}O{Eo(Tx_qnj3}F5o zKl+CBawp*4J!3(4eSep7YjM95|GPg|?rsp$w*7Sj_uuo|DDcp>8-*| z9{i~LbI)D^A)Vi$x1j6@%a8uS@p})~?j7rgy%LZv?$15rX8_Xq^?c3R3+3ay^1-8GyY%NrQDeH$d3oz{kd{eRL;>)Snqiq?gq$u`Nz*H zq|3Jm^3hLIzW(^%$=8f>7`w|rGJjdu+MhXg_jqjnh|V{VFd606;>F!@y(|7Fzg+y! zI-M`TrMKw@{B(TUi;f@rFumNPkZ-Pgh-dC{-*FR*i_-o|CKT^Cv3ShHF(pO##AF*k41YB;<)7t+bcs-=clY9gm^#H_RLBjqyf(zP-}h ztKZaq2M*}yyEb#jn&>^><}U5M`JQi!m-gS1KlREZ@3|}Q!2IfhjuDBHodvm%eYU-_ za7u1nZhcmwxZ{DH-r8Tk|K-=Q9npBk=I&FkTo`@`B~BiZC`wG~uw}i+O?Cg{pYx_> zB>H!ROugRHgEtr7ck0G|Z+Rn2Ai<`kpQ6KlPZ-u7$OdV_5F!YM~o9X562PH)qI4#?m|xAhE#qQAR) z&_gqg4Bqxr*5)Qy-yt+#9kGrXc@8AY|#H*B4PQiG$nZ>g@1P7M|mc7#`*8oB(f!o;Op?R%kNp)0Q5QejG6 zzQxq{>;6+G*1Y<8M*gN@g^%}74C#1w)!C~;S7d(S4ZiH|^^rB-9k-zuYKCui0_fhTTn??`aewSf09#rTC*eA&?hmhgFJs77D|M! zIADjj!RpM)@Yt5LhGP-xiyL|K4VXy1T8)SKJ-nwqEH}u?{ImH+6EGj;; z`rMs8i_e%EbPVVi(Q(Jl-HK11ddJRPa|d)}-kM!>$Ie3hzellu=^Zky96-PlJvO$RCdG z8olstZ^X%4=HiVtBmemJ30q(7wr0n18)i>!t-oSHSx4jQDC4O_FL_lA9^QszC37K5#Oo3e*( z&KNmzGkJJhLkU~&ufw_}4%qSCoguX_G>q@fG^JdtU9S$9I(FwSMWGREc6@ZFw`XB> zQ6gu-U{Lxb9-Q*#r{uc{b#K12Cu+O?+qIECS!=$1?#|HOIn_A_hGBKypk0hSPkj16 z2g3j1K`*s({hh3dt-SKi0Ie*PJ^$WF;AD2VJ~1g??2UFV@s@VmoR85` zv^0Yjzcg=4QLSs~NNBcCa%6;Ih2F@ojo<%r^Decv2UzB-E!NJv8$0gx zB-{nkyC>iL|18(CDc|T_S@P=HlvnbbFfcEDev>@xY%qP1Sg>KEf z7%iPlnR;x@eJmr9dtd$bbv}u4NjXnzu`Tektn{eXTsZy@14Ezpaq`cO`j6F zwR;iYpvE&VK|Kvtqr=Q-3d4ukhVt4gQ z@nbed_&@O4vuE{V=+*26;F&vMS85=eZNG?`adQ2JtNJ?kzRZNzan43>`w?Ezu+Zko z!@6zphqoe*2yNfDe?$N2gu=7Mgw!KZ#m?PlHzpSsDv5I(brE$;~p zdqb!vmctuGEZeilmi5sSxs&nkrexW{yH*dtsLWsc(bi7yeb^1XmkI5LF2wsEc78K- zMNy)U(eTq-`@neX+C^4vXE<%j8JwHwl6X={Bs83$u5XlGbZ(K7C8gxSZ^t!67&MIh5>^y=o*DpxKO_^RpK~p9R^uSoieJE-A(a zW%gHCa`wxffrUG><_sY&gpUlnvWxVILWj}-KXS10A`CK+X9{YUuYrf~b zkbNQ6A}?ldMW?)!{qTOC_j1q^*ZYJ5eolT=C^)YhcB4YUbJzyiHx%?4j)hq$=n3Mw zP;hM#wnRh0V2E;2D9G>Oc^Bgj3!6(q!3^B}J`}tLbGS4V{1q=;77AuVl*>cGpRne+ zA{5*Sk**8{OuF9@3i_jQ--d!sc>TLj@HeRM`%tiLEH(i`fe*FJ$OyhhKRuceyaACv z%M9K{FMOUERKh;DWd{48zArL^i}LX4{mft>-uo&u2tgVD%nW{lHondbGSF4qGXs7& z^s5w{opPb+6R7c z6x8#fAAE=UKJtU-(CCl-pb^HqxqC1iMYePg7UT6-x(5fM+E=>=heF)fx(BbIeXn;9 zF2qQCqkFImh;Mce>hSto-Gevr`rF-uKSSIH!@(&~&qLwhPf+W_;UJ2Rdn6pp195#$ za0RUB+MM83^!s%=K>@7q`kdeqH2Q{|V0V%2kLTT#6YvA%9r?j$(9-YngH^El z+@Zlsy)hhy2Ia7cW&Hwv#^&gL0Tk%9_X{3Gk1g*P@B?Wp`UTgbi&ypw&KZmp%znY! zsNvXtK_$9>RlnfELMW?WuoBjKT)*Hl?6M!UFUr>P7PQEIbhiWUY3N}LO$W_56m}2az;0Rbx{HkDINS(MU_z6X(Tot^J z4rq8XxCYM-dNNoK(>P*Vzz-12+7@)6MYFdB+n~=m+k&mAVeYoz16W<#wxBQCFmGGn zL+bh4dK`k`zYJS2Ju0BJqj^z?ciVX}4V2})Xg~+9;KfXs;Ywb73^g9Zi#C|l+KIT> zgu*BDVkeYx3NPNmqf>ctDMs;Wyx0%@dO9y2fwi2$i}7f~nY^e*M_$m13w|=?LSD2( z+KYJcJQ{d0FUCWcm++ztja)qk7Z0N!j^o8munO)D^tb`t9OA|0kU4`FFG7?2I;b9{ z=$I^CRH1=BFMfsDbmPTq=&bI%cnp+mUi<}C8t`HP#zhZae1VHFFD`*)^yI~AT=e3_ zCvZZ&dBKmN=kQ_#%q5o>-xR^Lc+n2)$m7M==;wT1L_sOw#aZa&zPxyuTQQKj$MG;^ zd{q~;0o7&j;xJUfFR|+J4-D5VUbMm(d|r%(@ZETE1~{`+k1JqpAzqk|Ir5^th>sv$ zI2Tu0OG24%;J)V;{4)=HdUfC;)9W^kJV`K5*19JdUbkg@Lc;(2r+0?`ydP{vk(_Dh zI{zhqx4XbKBh=l?c^96_f7uZ*%yKjQr+xq5DBLIR`Oo@=EZQfIZ;JCb`{C zKi~(KbCy6I{@Z#Tn&s=S`u-R^>r?0Xuj}|{9_(R+~X{-+Za9}!8|$CJ?Z9ktKkz8Ao_iig3oZ3^907D|G*@5VUCxR z2POIsIYLh_=OZ{3|6xZ6dpV`-rAHj0hnK?-9s7?uLIC~3*Z6;O1n8IBsQxBLzyL$X z-ZjbZh0&bfzy{wl$yi4IGsAK7=Skstkd0zKHz^p7LOJij>-aB-K^B||82n|DUq=RK z!$BauuDh4eue*ddUVX`KJ9g~6wQ7ETBh5k+qG9mOjcmRK= zQ!F|s8_M;6a0ImCLCW%@BcK&4*?s?UglsS8HaJfICr3bU-Goa0pB@uk*z^vv>d-iF@&lS+3p-XxUaF;6e`Z-NB*ajND_iTUl`xVfY>%mz@* zt4f1!DW*})HC7SuID%8neU9K%bH5{4F>fyQpP-lz;2-~1iCNA0 z=Yi5N8$dDtR2t-B09w^->Z+P2yQ=0XSA|o}UmU^K`EaQ}9_;eJq@g^jI!{7`?LS=_ zrZlYcrPAP8*7w@Slo5#|1%G+2wKSK5+z0Y_|;sVXGscA@?yn{mc>2kcT;eZ*v65 z{qJEQeBlUI?srQ48zEADKWgqh$sOgJUzUd1BFep^G&mTpGv^U1?>ol;a{mNd^}lxn z#2LRLn)G)%0;cRUSmzIpfPp=gbNG*rfTq4r9{+I!G!;K=hZ))t(9}|P(a(;6Is8xb zKfgEv`kh};=KtylkO4Em_ELWhgwDT{LVu%{HB!-`vM}4smSvX(;~-E@h}!H?mI@4C zM$`SUBcNqR>|zWtlXDK8}Ev z9m-D3a|E=k2O)SyOjmK!7S$+8qOY$ z0d0+4G|&;yvOb7D{US#|%f6<*2RQ;-c00zMzo#RhWrJARU`Ig9UZq}#I09OBJJ#X; zUXFm4@jGq&y&VB9JDh}}j$m6>Smuv~(D~=nmG7#SZDwV|%ff6kTUJ~aoWhoEX2*^# z)3gMsma@)qjw7U6L~V|D1W0uat$czbU|hpa_9^pkW}W=9DSx!;95EO-lgh%BhILLZ z3x@B4I{D3He#9|=Ha}*kM;!s$JcmzO<8s2pN#-1A4P6M}U($v>v)*LmUBe-%Vv4>IiVIdr`fIxmwVWLs-k< zjsTx@6hnztM}Tv!Wq@;pBfv@Z9s|NGN3d;gDDw|Qv+{4?fNE6Rv*`q8mxZYnwtZn) z@GIMX70u!(#{gY)3GBvS>a5AkI{$Std=nW z%)h@Z%r>)SkCg@6*|Pg-IFFavWkMLEpWhJdKjApS;7?~K{@D@mHr&`lWqx0DW&T*& z_#>*~2)6jivM?)W70;Ii5fsYl&pv)pRnU!HNZWk5GsmaP{Q2bgdp77O(OnwF(~HX{X zf#UyK7A9*l=vE%wN(M*Jxn-BzXh;%dl>0A}K~K&kS>-n9DCV|fP#z|0GRQ3tdP1SQ z#Ht$+wTM9o7JCy1eqTp`mYC}8@8Sq{Chl48m*DOEOqzFZRdMBb+!U6FSvjj1SRNdX zLOJuvagZ3WCs)9R{UIWNJJmLz+&`5ZFQ*OfE{0w%~c zBusY%xQG6%Y^DfUM6!PlEcXY)jpW}%Us5BfzU9rqFe*tkyF6$B$@chMF$kba)8j{q zpdLTG++RtKXK}b5A&z^2lYdlsn02w8?d8FB`53??EJh?nLx5(MhsbWAIGA47n>r7`dXE=g0nKNCT&SW|q0qv}Y z>HEKP1nBm3hN@>d0(3i^ZsDAA>x&_G&T6*oJXZp7*1tH1taBxtm0jQn?2bJD#B%>` zv?Bj?`m{CWg@5MFyHwtV<>6;=T{h127$q}H! z<5=Qmr(~#*-(2M1;t22*=-A84{q>MBewzl>Xue-g(`w(jZjFzX`6m&=2r$?-1y<8KiIWK`sQ0-60+M8I5@^UHo9yedLg z2vrpL&zJkZXBEphTfbOdcoT1O=Qr4@^}# z^EhZeDBtZxyqgsoh@}JxA3DMwUQQ9&f8+?e;|wJOgpVBo?ZaO4+vWbgV3&U%n(4n& zZuXkecJIl>6 zch1$c>i;+fR1LN{%Kf{@fM2uaeJYv;v?5G-Db?tTU>{VM zlTRT^(m0l|onsuwOw&IjD*S^`IR6J0-bWmdrL^NJ!mNuN%PNAC$nhM`@)eE&+Ic-q zY5xj4dGpg>=92AGE7igZ zKNkY!pUMi4s;~q650vV-iZJD+vQMrEPDY`eA@swiIy*=ARnV`V<_H*GMQr#PjsPLb z*})x-03rDG!v5J#`xrb6IYiHKgl?ugPOR{6qEvS}cm(-EMn zfsD>JIs$Z+#SXj25p0KDQ{g`W8T0?ZU}wELjNhT^-(L}C6WNeIRRqVNZ8`IxPJfe= z3Jv)q?fVHwKtsM|i6>{6v~$=8Pdfq(?Jh=f&pN4~@0~P@=Ntho`;lhx zf+L`14FL!*Is#fYs1FD)JA!T5Llyp&5IX;F?3G8 z40H3YftN1GP3|ENxyMR~-uq{PCb2YH3I2 zG3H;C$2fgS-nm6c=PIb@I~SMlNll+pa4_#KDc|#&?#RO`7|(A1efgf}p~Kb{wDH-c z<$H2Z_l7)1q8kgAk#@V~es{s~yt|`3|0tBWH;*CSQw6mgB@fvWPZwOk5)YS~UVAo= zG2Dvi#;)M#CUY8N- zKZehKEzchYiL*k53??Rr`d5&eUtx3<2^Dgxj)e+2Hzq=boY1O5g`9;B4E5)?c>2v1 z`BT84CRE6I;)qZoefiu_A)V)fP$9k5k)i%gEP7Q%{w>hTqEI0{j+a%)@rqfy=d^5m zY!XjQoR@_oUR;|rn(H0$2Cv&ixb{g1^IO{eS1K|&a{N0$fn%H<35rKy^qa(*xsg;f zWb$a{IReI|$)lO?2pE?pk7j`*;D-dO@bkC+LPtQDVG?VObOfjp&h_w!-+~Hl9?cOE z>#j{6&7w&7aR^1JmPdl4DV52iSt$lu2rrHJzb6BeM{~3om^_+QkuX`4!J0_$9T}KB znv)|o{4!et^gpMFkj$ew%@NS74~kIY3`gMl4#A7x;dp>QT5){DA21q1{Dp;2jHKn! zoD&ICJPL79B$$9gHjm~K#}U2&49<`EhmwKGqq#r~OdidpkuX`4!8OQ>+7}E=9?g0& z;4;_b(Ol;gi_S55G}k)lSgy2BVcm936=V{I09CwCXeP; zN5FE#+!A&)^vXr# zXcKYXw!He1J0<;VB;cuW9!2u<$j+pbJQ4BBLGH^|^yS+uyDidd1}<%@zU66y0C3fT-EFRE6V44zOl z)v6yOy*?!`lfmB-wMbSPCYi#Pz zo~~6U^=EKet9Fa_dX&6O>dzjQS6_0cqy^F7Rb1v#BrlKbOsl#_{m*dSm#yf_w`szo zqQT5DXq8F%**9t(C9^q9%1?<1$&{b5j^NTe#*2_l`I+EKU@ym{{7iHNtA*iF|0Gms zQ+`H9t)nz4Ka-+i%15atM}wCrmC0*~M6I7oru@W3NT&QuaaEvBlk!vL2)54hsQ(S? zG$}v(t4@>hQymRc8rFGGG*|&Uw3=uV18TzLI<+{CuHn-~NanT7a3!$5GATbZ9l_t7;Z@Rn1YZ3a6Sy zj$rFNBI@@-Kx|WfW~)w<^0PP^rZlW`MKs{aw^hwCVvtnLD#y{O<~R|OsyW`3aH=`M z5u9pHas;QEHI87#To(23rI;q=r(I&2l%KWHFdINI&x{6{2-U1=e%Dns=X6!gd9Dhl zn)4mO)_H2w9|m?d<>z$OX;OaHMZ=VabzT|`9$}p(<>v~=0Mm|1`MJ^&FzuL>pQ{`J z(~e2`x!Mu1OgAY%*Ej-nWm10r;0P||XT2jp?w5*S9oIU7mHVQo{~_fzDLVPl`d0ZpH;a7WMx_1}69BaWOEtH-CwS$(jsaj0XKCfWe`7$A7sq zgJ+|DIiA@Rm*>U6q_}L3hRK=?-i!wPAXiQvx6$72%;43iejI~@ZUgvliN!4a^uHJK#;aRfL>lS%TE2+2&6UmOAbe`paj;l&h& zqyJ4NNrodp0?d!!ME%Pkfz2e@Au&xRNoFj}22ji%v0&*Wh-orOdd9437&~5%n9T3x zI6^A3JJ{QmfND%8Nsb61go-AUB-asOw_lO*5Of`*t(k^)D7 zA)8E+zK-BBNp^7rShmR|>E{Tx?cHMj#b}nzB*~81SpSjFy>9lHJuZlS#5~EX+2uWfNk-S!~(GSa182#6V+q zY|P(41}0%+ycn2-jj~vntjQn}3tk|DZdm&IvCa(kk0Iv{3}$2f;!hTXKjS?=5et(w z8Pvvto@HP#8v7)EeP;&MF~0=QZ2G}eF)--|2gSlejf|oAOn+aa9L*t7shb50tP1A;9@Z_*#=j{!emVb*T#Z= z6<}bp4X*FZ;OdxPj%PO8;15m$TJ4RoFjNfTnrwrI z#L;9MJQ)kKE^>T67CgJZJ1Krq49wO7mz*y-8DVW}AgBLVM}W66XUUtLmxQ-5=?7aJ z0p7->AH3pTLBmb@!K;n{_hZrzUUvj|8*_C0hT{QmV~&pBbR~FnJOFaM

y9CPCqC z_lj-%(=q=mG|MI^Jgc^w1ckq0Qc>Igfw6l4v}y7SJ{3pAx3&kjx+>6AlP~hQBe)*i z<_KtrNjUhz5#UEn!oio0fH}k@9Q;#+3@he`82^yKCLDY$F-^k3*Re1gz%Kd@?x-@sB6um=zE5Cp$Ch7Ps>=oz@D* zK0QQ`8F_JkA`06ShK#tKqf81zuXvbskz+wTXd_3H!mx`N&_|gRhFwKa3PWz(KZ_hq z3PYYaniPiJ;$hZBj)UVtL!~p!y~KcqY0Pd|TxXEZ>_#|(GrLi)PG@$-j)2}WDGXyB z0lj5X7{)sSG-2#;qGRgpu+){H9dh%g+?8;4cz`3I6-Z$i824AA6*h%oP&_S#p)wxk z6R#&#aXPM)!hojN#Dgb6uqW#Esxo<^-XKEqMExKUbfR7r_djEm=0yF#c-o12Q#{Nk zUQbrH6aVW(9aSC@4+MnDTeMCG=HteqX@t}na z%t7{%jzP#Um=pJpBLj1g-6jU+AbU|fOx9$uA|CXLf`K{6KE^RXlw%IEk97nXfH}xs zL3X?3 zHV4^j<6*Xla(Bdo>nXQ6$Ue(e0lCdV_SqsN53<6+86sjiL(-%=`bki9;QqdCaF)^W@<{d0NT-!%q~<{A?zsOU>of=1_o_~Fko`nF zOler>bMatu9CbEe9q+#&2J|X1DA#|{5g^3rTv)v9s(=&O2b)y>UqxW&oG=80%_3yl z&iPB+Zv+4QeRwGGjD*-@7;avThbbO~_**=<7ln3d!WUxu?>dgCbC+Hy_LI`EK$NzggOli0|_+>okmq5eK3I5md0b4*$ zo#6k=5im6NF2b8T9Dyz%%ikLJ%kj27!T&s-c7p$XJj}{j#V_&T4pw1K@I#3%C-@nT z;7;(f9KoI7cT1$CGAH=m9RX6A6a2sttW-b7{a1`sRQ6Btv=jVrB20Oy?7Tz}okA<4 zyDms*+JN1f6a2o8023%;!}~b`yoNc!@9zi@!kpmmme6_@Uc;Q=@9qfQj2-q)_zV6Y z;@$*2s`BppKa0@;`(ED8)E2@=^t5*Bx~xLXyqZpEd2 z+_h@0RqIl%Rjbxot5&T~wOX~cwY6IHQS0{qe((Ex&YVPi-agm=eXe(|oP5r`|L*N~ zZ)eURL3@Hfw91Z`<^+Fi)ga1CsU}rre1}qPVwzLj2q2X?!9UEk$TBgGs|wxA7|jX( z1jT4h@TXM`Vp`6~&4JMBij2}F*!blEn3K%|r<81-8l`6Q*e0CKvlkr?-%+9CVIE`X zc=)H*PRGL!R_J(`8%R0X+%3<|=I-+7Z0;N9XLFxc$HPmb#_xn|?xRl0<~HTjY;JT+ z&*r{dQ8stVO0v1{q~qcHq9*+r+1#<2mCbFJ+1cDXnVZcGkono%l319{760OFu6=bp zTv}EHI;kO>Ya1O8@3tZ0*<7x)WOIqJJe%u;mD!x^ zACb)&`|4~?s@G<7BCO-#-&f|`g<@QvV;)d_r84J-FzJ~1RqM7Po0G?l*_@jlojrUp zkB2+)e`_}9E#3C`I2zOOusJNQjEy@h%{v~B#l}TYVdvYUFzldt}Q&2}iaZ1#o0b)r})t z>RTMynv><9$4s^1$d($hDUeH@6c3Ct2hDHAhI2~P63C_2z8(fr>6{)yuoHssG1$ML&n4a|S^ROD^bH3y*wAbQbAl(J1BA~EPKHC;g2Ozo-_F`a zuXiINC%pzaOiBL`-4k)|XWW+r`SUhu=VMS&+?Qv4p8@6!V}P|&P2A7IIecyKTW}a% zjL<{FHw=9bhP<;;e&L(49)e#d?_PKg-)s!2c@-mIxWyRK^FBbKhJRoTgPq_^EE2-E z25&_KV^YKSXY8!QJEr~%1si^N9E&56lA1EMc?`^tPGCL*fnZ90SI>4Q{KRO=76_!I zj9r`x_ov1)b2ynv8JmVxd-ykQ_~6*O$uK{k$NGTx;Mg0fjb6-SwZebUDM$_98@d!J zkNXqKFZ|M=&k@tO4XCZ~%h@JBqwj&k(C|G&UxTk~3hCsXl?nG(4*e4hsd;xm*@Ry` zv=33H=bbwQhBrpC!w$}?qPMq=Ao&;ZMJE6r?XCG%RhfVrE?p&lV8H+4B z!G&e;_*w99IE^=I;R-& zgx6cQd}ktGg_Z(`N$LDI9RHBRJt)I4ZO5mULB{Y9b4ziJe+p;)oAMc-ItCWTg@Rfa z7S<$o>q++^N<=i<^+WNEA6Tw-Eh)DR$fASGcGu-9&*fU&!G$e7Oxy9PXXF2%pJu__ z9tf_dq_@Ln@|}mGfWjLBLqCHlXE1AjV_-D%(V zNM~;3qL<%;$_u972~Ciiesm!kVEPnH7Q^XVFw~``KY(gaPd@}+Gtz$q-ISSr7VHP5 zKZA-KocM&q}`$D(39; zhcKBrCw(U}^X>Gz^6_9!dLLpwFa4%cj9BTX!hW9<9F2UWeH{EDM47S^(n*w*K-Ox? zav$P$(l3I_37~+_g8|hJhsn8UdFg4DfuXm-lyeSDX;p!&YvIAk*$Sc4s;wy{=VQiN zV@;_!d^veqtu=+6LHxbwv?YPyM#gy!1fGz#J}|U*8Dg2652ubm0TXp{zCh;FI;|;? zlR$?_+h9#8IkTaB(~b%hu=IjCpP~lRHUJ9|&M`YtunfUlrMjYHf6=@Y6atwkVw!F#7m^73r1piWk<}z#8m9P%}85z%* zJN{?5AD_B~u6$S{W6}8MjLp4h(!tUK*hF&q14^UU;C^;S<DlS-dc2)jM{AGd~jZ24h&0-VQAixVK6MsJ`EA%+ zbMy8x%_dW;qw`Lqkjso=%+#)KCnKJ99wN)n+l|W4Xf_Vx@>u#AEyge*kFQ_PXf=jO zdAm>!8LNgc%#^%1U5+q@!}3_V8AqDJou0?S%~)*=CD|#>{Mm-!Go`Sr$bB8T8lU=S z{GawY{!KFfSkjaD4^Awcg4B#Pp$P~#y{j8SCJz1uEXTEBbkArT`D5HW!Bfy8Gqw*a zfv54Qv+#e~Qv92A4jfHPlW2s~?_e=zM#d=_sVykl$5>%|v)THcydx*WaH=t+=A~xC zaGEis=Pg7Z%Q)Q_2IpOYPL^>-_IiXFn%BZ|I@8omPTnR~$63aZn>U??vyEYNUKToa z#yQ52pZ8t#yo_%f!-TvbR7J+Q#xNysHN`nE+vGIw*ugNIpUtu@af0tdqh;(1E<-K` zKLo3Mh_8L3!f)q8Kb2$;g;n8oP>h*f!`N5~Z^**^(IZ%pgZZz;7iJoIP3EQ%m9R2y zn{ZR)6m~Pn<`L@{RpCV3Z!y6O=a=JttG%yba^3cR!yw#mxA*-0cf7fdDHV21!hNs3 ze>oHPeIr=lg_ZQbV+1=LK&wVT@-mb3dq6Sq(VFmmLPJ z^-&s{E!GOS0{gFnYe`S%c3PLPx{Vv0N>712u#B+gQRH|#KCUP-82BV@)CKUFvahZj z#o$zQ;)Q;QW=5bXr4Rp?rR=~9Ru{vi5iaLhm%wZ~?5lHT*1=&l9O!+A@!kiU;y!4z zz};3fdI{{0EO$k_+lqEHtUGX7(eAdQ?T5w1xU6U|eqFR-h^D`2v*4YgO|>pb(JJ8Z zb)lZMCnD4sgnGjZHO8OT7=K!|Zm91cj!?r8>MJkQFdND#eidyg@I=_u z>wCyxVE-$q`qE1oA>nZIe=*q|8n#-aX z$JqF93UAWVGOl0YIP)%mOA|)(I$ZNkg@JDu-HvPiRWPLNYnizO-dX;rmB8VqS)gst zWid4{BK|Wm{xLl4Q^v?&F1s8NT+A5ngW*Bk+{YMys~C44Fh&;PUdG6O5ZVd65FS>5 z%+GrtE`LM>uiSnwq5+39Yw0fHX{notBl+*$Av+}K?o`?}jg){){f zg=RuHi@0wQSQZ`<_!MDmb6gfKW>qhRDcR7KpLuT|^+_j;Wbo(gy%TvQ7lH0Vphf?LLJpjdyGy*_=Lb!3SM;sl>;x_d=6r^R z9%7qA?TljW^uYULp7)-hDP`-uufO-#sd?9=3<(^3q?@-jDW-H5Z|>ac1QIEx@E3P= z>~;d{tYOZT7&`)ODW)do?7)y3SZ`gNMf@&M;DNx9z$P!g2Lh(y*yJA!_@rIT5_>3+ zW2*OT3^0M8$zaO$VQX-TUt`NTJAiiXIG5rI>>s(>)gWgFCbPblp!aZbZT0oH0~$&y z%}~;Xo^&7NvHIF6ry5|Rf8N>!N~kR`T$Dq%nsMjP#$j2Y#3|niEA~VODY7Tp0jJWL zxrcUeV5Gb7-^Ab)KSfy=Sy}Idm%#ofJXsf6Sucj1=XkP4lCn;Re-3+_ZCZBNqY!hI z)~OQ06Br}5!`xlwg>cF*fE^{iL!Lc}_bZnE5=ZZ$#2=W#EkPp+?Ei8dcEijN^noec z)R5!61bJg-B>KoL+A8V>RJRj&jsJ!RhMckn`Ya7yDHXAOiBRQJ;j$C5%z=wazxqyS z|8K#r`f1#pkDKzp;)eN7_7o>;d<+~Z=&-e}7)i(KT#N<3fn)hp+|btyzpoTDr1C1byb6~Z<6_&~a@f5CyY*l5 zy&f(U<@m3;91WLG;BxWTTzcTbv~Tmfpb0HK7Y=BrPxZH-5s1UFns2!dZGeDdaKniI z;rB+-XHJ5P$&@!8W6yA^{)*~eha3Dd4*mrKLtbDld;;5#QN&zt)zW222nD|i^T`#s zmSn@Q6*rr4m7j&sER;0}=yt@5V3!Snw)^bZd?~?M#!iz$NKkxSY8h-xkv!|8>*f zkid{1uY3~%7(bs9Qg_!n;e3s>EC7|Qz)6Z5wTvDh}w z(m*L!p9L4w7tX~EyH5Fj+^|!eZ~PiX#Yxp1Wd0g2xHI!s*!jCmIrRmV*3;HgQuDnG z2P%y}%fV9`Zz{w9rEv|F#>-(iVy_Rk``5I&O56#wVA`2<(PV+hEf zenT}-2`@omR-u5yNP(j6+Z=Yv*TRxb?ohww9kML(SxcP*JH86}Gg4l62ax7)RFL+lsuS;OoLUlF-UWa6>vr-&q3vSBC;fC5g9jUt6 zs4jw~X_Hhvbe-gLEk6a8?A-H=Tt z#kgu|xsU?^i-9UP2n+Lx9$yIm+ru>M!4=p)y~AxO+f7U17Wav`YB*gTLoc|Tz`h}` zLZoHmVHuwV3(8_9%~Xg^6X&S&=`WZ6&K@%F+pzcw(R_@nb~Y@RTn?MLm_E(IRb2&} zV>^ zE17l5U~CzMahVm&eB8{&rA13!IkUj1ruCByYjYNtJ5@@q&0GII3%@{tE3-0?*}85V zS{ts+8W9W6hD7hjVt`lX8h9H!0b>fT%p>9QHp-h< z=0X@c(1v&o+62SjP<*^HkA~sygQ0D4Wgd?Reli1U1y|;2DdE#FIkg zOEwcMXlzQc$RiPCol6fJg)D><14BjK<1vcgHRE)Ax zE%ceu0gKQuY^$0)%8IfWiTRpuq{z!RePD9ucV`MwFGHxC0VP?fjF?(esl}8VYljG` zy!^C|Oy;HmgGmp(Eh9Ly3^*->8)Df3LL4}aI)wT+(x|d&5N?PA zr2*#yexO>JKf;XSPBYPf%cjk{wYUOKGjXivz`NtE196(?z`KjB1989Sz`G}`1M#Hi zz`GZ%1M!mQz`M7s1M!~cfSZ5o!wCZFf^f66j3?BlI^e)sakI4SD&C!l3l4;vrDa#~ z?tJS&xLI0u74Lp(9SAo|%dXy}0`1x(o8MaQ;7h4ud;nBwEZZ&kmhE=C+A=+uXJgBT(}2OXQo|7NXnQ5?qWxUSg!V zZ6c;yTVkHIC3w`zya5%~mRM_Ti8gCXoNsLj{_r1UAl|dK#240<$i_Mj@e(7k72=4f?-tE2n|G))u;H>{oGWp*Nju94ljN9zGqF~Am z3Da?<)kU~coRX`^OK}C9<*t{c2VczmmGvt47%m%_caIx~CgShrHcq^Y%lhFReh81nK}=&*T%XX#d+!K3uDCp=kb{O89?V zlD-1-a)qv9KkSCSu6QhrA?#1jo^Ta!u`XaH3DzkFWNsw0BEwKd>0c#vksEUfZfw!C zFx%@*s1^pk)84YWS+~9p?}o){3=WmXaoJYDrn&4=+%io}>>dUf18)Ba*oc-TBfua7 zYh{Srs@AiotzctD+pl*zHx4v~uYG)7@EbbI|5i(+C|^Qow&^ryht>aX>-8-B0(0|~ ztsd3JZBsUF+$MdT1`D3;_$*=4=igBm-`FwTNDf4tjWb1J7B1V9dAHCy5OH(cLQv6L zKfGIq3(bXSGq+8|9$eNBZu))Z!=%Xmr@SN4nD7;^9*`5~s6+c?3-e_)Za zji+UV>*+vi2J5YfC^RABL>aCFN1J6lEhAh{|A%O?4G6*G1dHjw(GE49mJ#&i>#E1Y zXqyX1P5ap+vZ?Xox^P;?&z%-#^Wzr#d)8?FkHLS2n}KVV zv9bSnAIHT?Ta9ZSu06Qi58W9*um8?pKHRCksMddq>k(Y+6x3yG`0j@?_Tl1E?L^m7 z_veBa;bI(|NHQ$-gIhkZGI7$4aZ*3KpGmmkRF%^fub^bN7-X1yxp890$tS0BoLIW$ z4KF7DSAqlm(9Qkq(TywD|7N}Y=RurJ@v)_pz-L+b$yrX;*s`2JQBiSETk(e8?&98_ z_Trwzj^6c&^=-Xf?Z({E)3vj+$0^>pZA)iy+vd*Q#YLO9wYP09?%mkd(^=fpxwW&m zt+%+dEYaJyqoZqEao@IWo7*?Gb#3h}KB~Pv(blu2xU?iuo+v9RD@~M^(6SJggtdOCJ= zZQT~#*3((&mBsG99#bT?M4EcG9o^a9*IV4&-PW_IYRA?@3-WSQ)8-w$iFjmI{YFw$*uI${|)!tbgk2S=aBhAINw$%Ukh527j0d26a zZEJgHuk-J;aW=Mp&m&^nxXXBVY193G76=-kk@V{>1k@0jk+ z-lC0ECFmd>U0eHLfUZDyOSEs>vSr)W1S$n~=$Y}utJoYWYG4fE)GUE!w6%9bXOFyu zY3KFM16m>^9#62om^8$IRk~}{xx25kXRF_)r}L;pTRVz~LS{fC;7to52n%iTz7q(A zhKB;-VWH8*p>g9vqsN3oVLW^n9DPdg=}b80geHXpq4c6qMtFQE6SsljT{|{}GJ{WM z7UhSAgoD@bfUj`ygN#6EXkHO)vJfaIJOU=zmzIRm5hw$3P6Y=eOdxpa&HzKclTj4P zGBJK<=loC>&G{+#U2LS`%6A8?viztG>4$UtL2hTe;5ZssIr8^jY)AK{qib50fL&L(sJpqUq4xWAj zOuVADfRdIxjTel=^={hrYnrm>-;^FxJKg(l}O35^H`KSG`}f@|gv4-G}# zW-Ja39gR3AgoYg*8i{C;xe?*|&=}l~D-Dg#gK2yy7p74VFgH9jls^tu4dMCB(LPkd zcsJ0(P#$iJ3qp{51cWSxX?A`nHy=TRR|kra>8v7CmO1nBj{H!R-WG)>z}txMf>1#? zCsZ69oF6I(?#>StuY={G2uVled=74M$A?Byo<)*pQP>pg=O^Zero-7t9xPmG#TXaL z8w0<^5Ci3AC1N%p^^GUZH!+w1b)Epl;b2xksZRm>SP}_H{ZA*~6?@5&P?Xkn-;~$+ zD9hk`=sVd+YiNEb+q9r?5!&`|&{B~4Ln%cgLI;Nrg1qAqQwfW@2saCqtNKvB6%)U& zQh*%h(6KI50?VQzmgd3X;NVpdSnumUFWdf;F#@gkbo5XpQq<4G2gXAVTI@lgapOaQJpB(XLemS5z89Smp$>sK zMhVO++Q8g>d|Y4wEYR(*HrX{j047v%8pH@#Op8#~e{?ns z4^4&*D(B#NEb0lSTn-7(2#v}y*&KzUvKgGUD7=#8{r%l+hPh+L6$g(knsnIM0^E%$ zK`YP94~-A@QbQFFA8uNzxf`B~`{1rXK`3JuDjTtxucj#YThoOGiZ}hh z(v1q&Qxt^!^q4^K?sVoXl#zoTh7OS*I*c9j0;4X6q7%Z~6T6@(Sbq3I71EF*%*jEs z85){6E>x0Foq^6UbAIT^`Jtf&_^BO)+Z8Sf7w4GrLEDPW4^3wes4F%-cNjEP9-A1u z49YT$zA_$(PLpjox(MApoF5MU3hk4+dwdbpE`J%Qk^Uw(x(iK^O6{6JO6inKqGTsTD;^)*-oF!; zU|=4FUL4%XP8iH6`dT*}DD^(*W-}idkrL>aoh#`OoEjJbJ#jG9Y$J4Hu#^h75$ZBn zoIj>`EQBpKY9th1fRu4NtsoRC2?a`1Qu;;qdqy^r)fqenZFy$tSj4jn@k}Ww422el zat~uvh=OsTS7N#mC>apP2NH;rr(i2$2^P*DhiH~joN4)JyPh;$0W528@v za)fK@uZ!_{Mmd2QT%8{p8Z0QXF)l>}BT#QBOt?d4n@Y}f+!VkKF@%eA z%Z=&`VLC^9h!rj=N(uHWgO8XPR8au)wcJ@q29-Uu%$G>0c1&nOerN{L85^2`f;Huf zc99$0&19L{a1_@8lbczDcj)??;}b)e98w!PKa{>O6mwEi(epFHWx>Py&|7|s-Wl|gZc4=B@kDLI z@t%}z-wALfSmRNI3ePd+|w+->iRn0BUxPz3- zVqT05jfv*gisop%wjvfsM6C^#PEBpRvZW^OG&feoBA!oVuBj0MIa-M&@O_x0`ZhXT zF|}`Q>+MbS`HQ16))I-)Y7b!*3_q$eU4TsGWGEp_v(H%So7es*FYBF*YpJIh&S^q^2p};5668R#cUg zI;i6nk=mA|K=EaX3N%l=+$mB~=W8pmmKwy}RI`dLw=tfmt8G|nDvPUW)L2iVvl}8M zy0&(7?)IWvQCn4;h%}kz7j0~4h(#%jsTEeG@z>lMjrv=9Jq)aoWv#K+SfUE$>eMwM z7dG4+7JkfOIX6`Jn|V_tUfYtamX^lGM17=Tm6}7cBboYdZfrI(p;=jx*zBq-BG@?RcEs0oztrN3hmtgB~ zR@63B##TC}P#P-G4BUW5UsTpcs?n?(nxl0~6V;Jg)O#elG?@Xl-AJ7gC(+o1{_aNL zHqDB7ZFNlxwwju~2I_jLLbOh_p{3qerKp<9rsjAwR$_YrL}GQ@HkxdNO>BhF0nmF+ zWo$XxEIe-MJ!)fTTZbAaI$I@jjqdKmSHxJF+#^ZKR~xU2Bx2EMqO<}HIMUJr{eWLr zZK`xu)WsUATWUP7ZWpBvr215s@T#`0qoc4j!j{=?Y!oFr zcx8ROsnt=M$nuVECy~HbZQpE!bmRBRA4+SLQ&~dA$~?uJ(TLECw2SBYcNGa$L0uyh zYfon{cKMKg13Gb}B_3<4_l6(Sw$O*8Rn<;qQ)_d)jN1DsQwT=IQO#+r@=`FmB-U8l zUzeCnQ7~8Vr0(P}Y`eY{zorHwb{&R%&u^5Yb!`LGL{+4g3fSuS{tcp|v$wsctGjPo zPZ>K=vK3+ct#6FSr1YRSIcgyv6}8n=piwA-I0lf8w!StmMd}AAbhp1(Mj#EVsMHK| zzAhVSwZjM$ol{%evfS4Wn*8lR18_W67mGCeh7fhb=4dPtX~l5T&{7+XwA7+w+ZJJ3 zCDYRssG+eT<}|lrfKyFjqB4+!&7KTs4GCz^q#|(JkXt>NFjhC1$)YAqsQ*}e zd91Q@wik(i&`1t%cA(z42|L+aH*_7fqo=b2spDwD;j{YW#)c9S?FVD+vXje&hpAA#yBQB)5Pf(FBMl~ z6%t1GNlqe?gJ?9`n5e-(=(tLW%FXHpC}=3E&Ylfz?VZUc=++k+2MWd;I@>oKwQW=X z&g=y)Pud@aNZo2`>+9OKwbZNJXsoWTwJs8e9;vQvhE8M;a+QUf9qJh~nnR=6u2X6> z_tqU-FwN<~ftCYxoE+>;ufv2n(OiR-0H!(A8{gDtc5Oww^^`HoI#HUaSk;22;hz}S z$1wfSVq&0twM|%eXe!ji7L3JDO>=x@tf9Wq)FV1GE9r1k=f0Zk?&|I=@$|6Q_MIJD z{nKmLzMR_8^o|+c-At#VDjxHUhdV5j^*ANn)azN!@%LrSxuazRs%A$Ijt~11-P?BI zw6(ILuEMJxukS_8fIe_IXT^FIUTW4vrZ1Saf?In=eVGF0bg|z!z@ZYuy3{8>0#8&5&>u<{O>ubR9Yz zlW?zdFuTdYs#Ka9ionfkvWL|*V)}vVLYs~>L}Q!`_*3#iU{#W6idUH-*PRfXw(VAR znN!oyRMFCy98+Bd?I!A5S(u7PSKEQw+|suD-#bw}&@rN$`Yb6Ivr2&~b(ar4yB)Lg zW7(RK6*=s|fxA2P^zwJW$+&75EBF>HdlO4zwu(7DFw-DRq3k?D)9pESiidOT?Ow#b zqONQ-6TQUp#<~_PwS1kqB@%D3GuvjUtvb7co?&D2R-0yukM$qsa=sk)?RGj7JSpw$ z>A`{|hEkUHo^8XM4(&}KvD$5Ia))}XN;KgsoyEE0@(MKak^#N2EGcI#mZ_Z3VEi(Z zMX$key4+83mUuHfI{>(CK(n5DOi?hy;DBmcR2BL`bIpM#EvVwgR;+9=sc5LGtBq1m z*4Q!3XjiOcOl5c_Zs&dRSTu$yy}K_VjlctC4#Ql=d%6@e(paPg`$4e?){{)jQ%T9u z-5UU;7~CAy*44$TBbYuUH(=_}nVNk|nhi&>aNQjVwUq%o9(GHrI#OQ`8MGr|mJ%iX zx};eWxJh&PFv}S%r{fU0iQ2sfE9gTxrsz^Ijpjp`| zSCu>EvLd6AV|7;#XE$AUkgbcX;*O7`t!`+|kItEs&nH!iO7r=wO3Cc98TnIsIyZN= z^>!YXU$~{cd&h$IZ9RRRy9>9Jm&2lO0HEUcq{60(Q`f+Pc~!k`r}A z?fFa20Xcqn)=5=^i8N-1nEl$;+^?T!r}cWkhzi9+jDKuNe0G_Nph z!5Y=w5_gvgv+azseq~d$*%?WWbR0a`duyw`VHL|`HaN`_jDNes*o<9|$WnJP=u~2V zAvyVVMK!A>tAn8U@W2Lkaop^1SoKEndaULu8drLbZUoUf%sjE+;0{>7(%I07-Kd_< zWMhvvN3aWIMgq?G%r@KsgOodXV_@llwMr#)GBz2^s;eT_jIFg&Xlf{2YBEo7?lqge zBkp4)REPc3!e-g#&1S5dW#(vJSZ#;86HslbqT8F!UW#2|ZX0`ZpaUdoXHHO?OnsHv zd+`rZoNvys^UY4P6g1n#UOd!AW`n?MBmMM`on4|Pt**vAS2p!d@3swnyYQG?bKkaZ zZZM)5l(2lTy@2(Nmw;*9>{Qj*k~8&hX3uupo+7*D#qn;YZHjg(7WFoUQQ*xjNE@?U zBP+eyL2`LzJ$KKN;-RqIvNb(9{!MG@qypZ&ZR=6_-i#PU?Zx1mDRK@0jcKQfZVJhc ziv>{=TBbWg@MUoY_F37B>_J3QFL8qu!;9C5xhL#3VymL;4y(hC&vm=X7&){Xyk-UJ zP6^C*l$Qz%s0njhOn)&zB@^W^ghYEgkJ^F>xtC9@FR)36{pLC|s=G@JZ=f~X;~H&^ zw!u)&J%*Z9+!&`orFQA=#aOcfdq~(jwOgI$2q4)c+|G=}*w-!HLjlZ#`wlSQ>!&5S zrKK(JQjU@SDY)rz36`BFRI<7%Bhdk~r6}?cTgkmy6my+ZlROw=4Yj+w_O>6p^>1g! ztqqaoP*>b+)+)?w&EQw4E1VckapG~WTR0r75@v7Qjl*_d>^H^i+BB(%e5LMX!Hia{ zW^DFgoG@A~x!66BYnjQYtsb1Xtcb-`DYlJi`=ZS3BF9Tg#8O}J)YLcoON$dpwy!cX zH^r3FERZ=dqwNgagZ;}9_en)B6U|Mvod59r0lSI~6`YK7M8T*UZ;C<$Zelq&3u(3* zpoYTKN72suw@BL*?WQQ^wpd`x*#}g|Nk_A~}6IE^5hc8+(J-p%O^*7uOUP#%vr1{GEU7=dMHPp zXyDG3(^p^dSPKTpp3ZK}7x4UcXPZ&4?lvjcL%rLfijzV65ALplXAPNwyt%a*VpsZy z!?vD2-;A6-F|Vq3lLpFk>BQd(X-8YQ(+rvUD)CqDE^=I>{X48NtQDmPp7x_nbzn9vs)e}N*upe*G4feV%B8$lssR}IF-PWlTL`-DzUS9 zvzXFZJoiU!pYeU8<^R_AI4V2W??4C9vpC7A6u0_$bnEL~cIwrh)W2@?WA)glT)fo= zcV^L0y|VI6gUg*2Xsx~@6t|FDo2VjqkiX@1yE=N^Ue5^3qX|@4 zCH{6oEo>ivX@q?7?<5R%*0P8RsX-8nbGeC$)^uv*!?C_LL~0Q&F!?Uh~+B zJMe!)399MZ0}1*yj}pY({T8Yix2f^K#Y@u64Df&(G)NSi5?`Afn575fGrM4@*zG&o zHg|FIo}6FyTMDCPqSDm(o%K65;43@*>u}39D79T}n>z6nf_bb2;~NGDvor0sX}_MU zs;$GeCws2zn(QFW&G?xrtOhu>Njkenc%~)z&v^I@3kI5&cx^qOZHjV;_4cMpliO6K zw${w{^e`)Vd$_6ga=T{YTE(0p&l#{FY2c%P$@<3_+iaTzTC3OR zjK<@}7j4YKvKwQn?T4&aPG-!UE#}uW{u!%VZfsWZR^Rz7rcEjhMr2mRK4q1BM90== z)IaOg2*=^n>rY1En8&1~nj&O1%hw|hLAA#(;~2PZSP_eYC8 zu4HA~zT~QUt{*VD;T8{DtvMR;YNae$!}tMXw^qu`LmsAr%92%#cf5HXl2u$bD_Mi) zkc3Z7+6Sy0oXhwpcdkTLn62T^J5hyRhVyOIp}W2{k0wB!o9<<%D*ofLo=)z4^C;P^ zJ~u|}m0+@6i8Uc-K?5FkHD~k5M=BV%x0;C8V8&Hj$!ERHkpQ|gM;45NSiWxQ-rU*O zIiT5bv8#$;73ncebRF)bnE9vsG!E?~io3+J6Hd(Z^_*F9s^;(B=1E7ZVGf`pTN{=( zG_Gi{lUA-0lm?dMk)?Vb5IZnvhV}O7HkpWT5!dg~58L}&{XNAz=$9N}w?c1k#SagW83zbE^T2h5jVDwU z*Y;ka_*1=w?IV?F^xSmgUX>fpZ4D-f z3GJAc=ej57x~`44&h?8?VV)<}HnuHWGbXT>wzh5ZlEcHuNZ&4LO3Xvz?DpQ=$V@ZJ z>^48jh%EyP?Ivst_=?x7c=KR_U8?C}RI{0voEjmDw@Y3+NC>*763gx*a&+jT@tVCrKN%EhPTa&N}fJp?Q>zb1fDxiYIxXkK(|(ktMigBTCN|)Tj-N@%`&i&%%{^-lFxD?rwWc zb8Rc$l`eHmhRzQY%YYqZQ@OC^&hanJiMPt{#-j_|^{IAt}^x7>0w<)^Q2=lB1N)sv!$I%1IirRI+ zs)oi%-@e(aU-TFZV*d2%iw03*C zuWzOJ)-}oH;D*g@N4XnPz6i|zv^}muzt)rfUh(-RpzPnMe)HV|FZcHOHSXcMeG6HS zV}jzI-T6{t2joLZ?l|r~nB*2nMO~y}DUPIKIKoy(b)8sNu6JxfVUN*Q!q{j_urqk) zV3lUa-#pPxiObEbtTJAUJ-8^gtvun)=+J-1({8V9+q!MT2Cv2TY(>^JeRb?sSii-R zdDslgCHD1R-=+qYxz6?y?jsDg^>OKJzMsM)2)<&$TQy_!Hx^nUyOY<_GR$?TDA1ho z^$RZtezk>G!Xl{0GlP0!*e$)J0yC2sYV&H}6oW+x9ovfPamzS40YDz4dGL_D{nCP- zOGVAv6I*A+QfMD9vDk7(l!KM#Em?S&$2k@{vwaTL9S>LFAlW?bgBwfqXl&um~2I67Tn-laZ~z% zW$%6QrHo&EaTCIkxA#Ok+lhPT?YXN(u4s%e)qK))8Ki)6F(rW^7DGC}C9#E1O6zMp zZUop9bsqy(W#C`=jKo0LtBxaE%`B= zY;<(sdvY!An~BVGT<#l(4*TY(x}3py56V~g;N|AWXAK@=-h9P(qwuo_S4CFt-teiR z(^5|lo{@5HU}fghkN@JaM<2;@B7<7pTlXzm46`3^R;kSzyf=6%d`Gf!w`XPzu6UXO zDhAd1?ps{zRwQ6Nr<|1KJo4z%RjxS#-;qI-&;9W2QPW)m$hT2NvU2u@PE9>6cskOn z%&O_g%*u%jNb^EvSu&O8r&~@o!>p0HG9nfch-j& z9`5Vmz8H4yhi^NJSo!FhnU#*pH2+b0=@n0#%8L4KWf_@+fNgxC6@G;dx1rgE^+nj6 zZg9fG((3UhiuCN%oWO{{$Y5?@RN#=np@GqXF)8B$MSKs}fREoQ)p`Fbzcaq7?Kk3O zLgsZno*jO2-Mi;a5U&;*(a$E;$%VPYvt!Fieu8+lWPkr*@#~_af3I*4v3#EAo&S8nFHK2P5SqH@mY7inb>};`xGzRnXZFj5WTp6eg>QPuJ(NS zTPx+u8sI<6_}}aK=iC00pP(~zfd8RMN8AOSVFTQU4R9Ymz#Z@2_kDtJ?Js|SQ_vYX zztG!zvBH-Tw*VH-Ol_lAke7feh9^-$|JK;4OCp{Eu}e%h~!LoAivkpp!qq zoXiOwg3kB>?h^-?-Po;l(7g3J=_Tm!&6LSc(7ajFZ}w|#rdOfu2bk9kFmE4V-aEj|m)^P`#((z!^REV&UmIZlbby&}b9FzAZw$=zLQR+r{ZuA1 z$Ixu(BmNAa`=S4p1I(KSn2#S|K5KyaiUH=k2AF?6!2H$#^JfFh{5e4PL;0o-FxLz) zuNq+9Ho*L?0p_a)n13?B{3OgQKh7btp>JQ6`BG!fa{ehZ#m+{H;tzS#e~B>v|MhZz5BJ&7EuBw!v|A0_mZ1j0#V0-NA zvvj{{<+Gwc`z;iorEhyCxrTE0rhWU+=9JAGcO<8Jo*n`y+nNvLeS30>z*lio=_5Y zL;paHz_(G~@3_*)&fN@Cj&@&!^-e1;RvA0*?V~ha;(Vwh8Nx(DEB`Anl5#P)@7)-l z14DQZ?s&FL?d!J8ZT}~3yZ{3>BE1}aZGT49YI18H3G@|wvKjfS!`kAx7oX4MuA3gh zIG~%^k)w$H_WnJY5wWeS10R+cf8VhD{sy-mKA_>b_1}T=tnG_s(C)Y~l`!99{RTIF zFZ>&vcpB`>v-i;4fxY{^vRad0UUe#syGtETxL^~@Fa zEzo0@+P6NB!65NhmyFuwC?#t&|C+{#?-I4_X+ zUE$YA_~S2ZX0F8#&yjHFd+y28$OL}#kwiK0h54E5@YAkj8-DqfTyNhhP4_2hZg-qN zkqG}+65%N?!~Khd{~YEIl{txozu9Cb)~_Vw%r6u>fvgbnU8Bo ztK-eJb^^G5)$$EkcjVi+3y7z-x(z0JBLJkY!8g@A`_rjH~|IK~yw}P6Gx0_7FXBJMkHpVJzO$TirHMnt;o>N9tT<7e zCYFkaiwnf4SSvP)t>Teln|PGCMeG%i5l<3N70(v;iI<31i2otpDBdRiSiDdCnfMEl z>mHWJbK>vBKZtLM?}+bQ#5)X;iEG1XOtMg zniC@R6wO=2KJhs56!A=vdW`-r5w8@l6>kxLB=YCP>HlY<(QhzwT}AsB#8*V4$6)`C z%>NWW6&>m)xTlF(B7gjf_M^q|BG+HEFBNBti^M9iUThJM6xWMgVz;GOTqem}D9#Y) zi4|h4*d(qH*NUCuX0ca1Ry@5ML7zl!gR zpNLwo#F%H zW8$yHm&Dh_zltA-pNk<3NbDC`;z%)HJWMPT=ZTeKy|`RVh#N)ztT^L8R{WNDj`$t% zO7VK}cJU|T!{RT+=fzjVKZ*YkKM@0IYX9PJakMy5ED{eF7mG{8Tg3;(FJ1R^8~+Az zmw1GyFBGp4e=I&Gz9@bmV#~|KlPk^;BjPIYXz@7l9PtYAC*ot`tKz@J zv_UqVv0{nH!ztEdTx=Kn#8btK#p}hNi_eH}i>a6ZF}`8qVd5;YL0m2F5N{M86Q2{` z5kD32!`CMMDzRPc7S9kb7H<>Z5OL&SSj^MDb$rdhs6d36Vb<&;0&V%sj}N z4;2@P4Pv)=j(C~)L-AqpIq^-Ao5M_Jh&WN4C9V{^#Iwcg#XH5P#8z%& zQ^dvMGI71wEAAD)BVH%oEj}l{CVnDjWZQHO5vPgs#d>kAxJ^7;yi~kh{F(Ty_=fnQ z7#eQVJ6N17&KCJo;>>ra*dv}LepkFjd_a6!{Db(O7|5~lWsBp*MPi-UA?^@Q6E6{O z5Pu>*DgLMUH}MN`6c!xJ$0Tu~*eI?Ow~OBvFBk6+e=a^Rz9s&bn1%%w)5#TQh!Js> zc(iz&c#e35c&qrJ_>B0v_)js2qcx_NBbJB@ME+{+QJy@J9&K7IMBg9SO@#3Z8wc-Qf)8Ze*&&2dYZF>1)saP)_A@+#h z60Z_(5g!qME50v&DIPr9rc)*^5?6@5;vVr*@lNq);$Owj#F2S6-U;G-v0m&FcZyeu zw~Id$pB3K_KNLe_R3BoQxJXJe zH;cazpBMioej$z;XVaS`E)*NZb>i{jnc`#Oi{jhjr{ak5Hr{dKTyeSBE*>XdB3>ij zFaAn=Rs4s@4LH{GFmaq%E;fp*#Xj*=@nZ3M@gDIB@h$P6V&+7f-l5{*Vx_oR+#;SS zUM$`!J}5pTzAkMMiREIYxK7+6o+@4}UN7DwJ|Vs={+Ae>to(@6#RX!6m=L?g zbHvNUABqo)uZr)8!6`PK9C4yJOY9Pl70(v07w;6G5?>MD6~7XP9%j=i5X;1<*dlg{ zCyVEbkBYw&|11ulYU7QGCy2L+e-=Lz51MBE7mEwTrQ#}ai+G%Po_K}$L-A4Zcj8Cl zpy@W9Sz?=btN5h&pW@%dFT}BhHvBxXMqDQzFP7drqeEV zi)V=65q}`wCq6IcmD=!g#42&ExJmq$xKF%E{6I`Cv+;}&Ys3z5yLhH}xp=d9zxa~) zmiUF3Rc_-i5hG%|c#?RIc#ZgD@iFm5@dMGBVdKpe4-=P)tHl$=%f;)(2gPT^*TsK| zSu<_?hl=H5rPwNN5O;}Zh?j{siI0iTiSLM?i$iAF^u~zA;$m@`xL)iP_lj4GKM)@k zUl-pM!-v~+#)-vZwb(9pi)V4|#bd?O#jC{I#h;1Kif@P?ilMnSy@SQc;%u=+Y!ig+n)r!$$ReBGG;zLIFRm4j6;Bth5^oou5`QPYFQzP3e#B{FRBREu#S_Hq z#Jk1E#ovj46+aUPM{GKIVv)E=JW|{!o-ck+yhD6i{7*4hVdEVuP8Tc1b>bHBRPkc* zdhs6d3Grp|9r1H9H)_+HC@v5i#Dv%_o-AG<-YVWFJ}15@I+Zs5A>u@FmWVHkns%KK zcZp|+mx(utkBQHT?}(p^Lt-|*F=DZZ@8y_uR*EN!4~kETZ;Bs@;VK($oLDSYiz~%0 z@mTR}ald$v_^9}b_^$YsIJDZPS0I*&_==2?|46Y{+$&x!{y=vhfu|Zrd9xd(`&k=7Be=7b(3@@?qwu#4!CyQr_-xa?nUN8PYyin5+4zt6<-s7*kI%Tx%eCL58~g<$|>N1P;17t6(%xKvywt`OIV z?P8a>P23?KC!Q>xE`D3QP`pgMO1w_ILwrPhQhY{yLHxb=NAYd(UGYQlUm_ng;(Q@2 z4i>Y;TycyzL7Xa0Z{UPEZ;$(4#7!e!9BgH=PWbs__yW$PvkHv?@ z7sT9VoBl-cNO7aMLp()1PuwrwDBdOhTzp1+Mf|Jyu^4Kx=@y8E;v5k_QDoZFW^uQ; zS3F#fa?dWnLy8K_b3{*eCnl;>qHv;sqr9-y;4{d`#|7 ziqDBJif@t#_oWzIY0bGL*%JTqdq15$`VXJn?4n7vifV>f>+X zzr^%a*8X5|f>%^atrH=CpnSU#OE@m8Q(;X>J6c>{-@cf?4YsJlCADQbo-;((}a*pF% zC|)Z28%X%OU;M53wisA#-E&FQPd+&U{afaFB;s8pR?5DGgugA~Y2xMLkHjZQ#QPg^ zD4tuE`5hAR{zLpw_GxRZzro}@$H^n%uRxq6_qk$JtP|IXU1E=Tx_AzWc=wZt_iFK4 z+21Pj9pZiBgW@A3^6`@Rk(j;K+8-*;6l=wH@dWV_@pkc7;tS$?;^2ghcNht|$B~eG zk~mHFGi07EM#Px7goNB{#UAl&@gngG@h)WIl;ReBTn!k^4Rp_4Ym4Un|}u`ya`CxA>6wi1;hvc1qv8|dv*HWlAH+ArzlraO zpNe0I;SDyw{B8{MJzN|q=8F@=La|hwD=rkP#ie44xKeBrJH@SHk9eGTk{EU%*Cc!g zMI0t#2sZYk#e8wLIA4s4*mg4hu`D;l^2YFJay-7bB<>K85%-9D#r@*d;`QRq;vM2$ z;-5&&6aOl{FMcF`E;<40FH_7CM~I`u@#18$NGucQi;Kl-aj9s&R|0uf$-GYN5Vwjw z;xXb0;_0IKUJ2s4K<10ZN5sd)UyJ5@BJlr;%&&`Yi+>aUOXT;^SZ;w7%aC}GI9xnL z93xH=e61^F0vA^(AG6N|-J;#{#wG~WwBc=Npw zFd_RL;xXbLaj$5;{{jD3%6zSOqxhisbCKWQr<_lVe-!^Dn(ueO-AT3n(!@cc`CbRy z$IHy`^E198aS4faK!eySt`gUY9pWZ&o48Xn-|Ij;=KC8^K9|!T{GNENc#C+uc(-_; z_^|kxm>NPnnD3>F2Z_VQL&P!SMA3Xd1L4f~Gr$?LpC>L7tHdSZGO<-$Ev^%f5;uuG z;!g1d@nrD~@f`6&@e=V$(R{B1a^5KO4@C3*4%pu#^Mm5g#V5t5#ovm*6JHbG6yFj5 zA*NygG36^BBn}r35yyxTF(%fDP2vjiNO8TmLEIvm?}H#;yJbFJ{FZpSc&>PXc$s*G zc#U|2Xuc;)CMP#b1fP5nmF2FaAmVtN6b7k@&gjWY}~w#Vm1z zI7-YHCx}I2nK(yWAjZU6u}N$Zj}#MPm$*gj6L*Vy#J%F#;(6l5;^pG^#B0SLh(8qX z5$_it5g!+SEj}l{BEBxZE&fe3-!np)ek}8sVhSdhtk+C2OB^AN5(~tM;&ib@Tqkyj zo5XG6PVrdrWbst-Jn=&Da`8&>TJc8lN8;V$PsNADC&j15--^EzUlZRH-x2>Iek^__ zrVO&>6c)3@Y;l@cEY1?=iZQWPY!X|rj}ga-=KEf-FO<1SY!QzX6XFK(Xt77!DV`vn zES@2rBVHt4Dqbc2hj_Din|POaulTh1toR4<4e@i)8KV4)gT&EdzBor*AXbVsVx!nB zt`XbBjpAnUToPmZ1>$Am72@^c&Eg&6UE%}c&%|GfzZPE*Ulv~%-x9wPgBU|7N2Zu1 zju1zQ`Qij|uDDQ)iM8Td68jzN#V&D+*eC85&lN8aFB7j2e@tRO&WqX56vXKf95b)(jMtx`fZ4= zX^3WRXwrwf*;fGbWj{eQ^1yz&%tjuV&3*&8SoW2okq`EDG8;Kz#_^&_ZygCCI>e3Q zX0coB6L*Wpi)V=Ei06wJiC2r)h&PD0h_{P(iuZ{3i;s&>iO-17i?5MG@je#uZSim7 zC*tR#+2?@&)PN0_E)Ev?K0n5nBj$>u#VO)+u|%99&KAu+2;!-sndL7wk?AOZaV3d% zwpuj%AqZ#oL%@x+N4wiBc9Xf-{}y+XXots(dq}j$z2X@p+T}Uo`D6j!>mpuCqMhy+ zuO`u6uMuw`|3CKL13HRhYZvXFo^EwdD~vQVNPrL{BtRrdWHcIKp=7c|5W&VKW55Iv zEk}YAPS`jHoWpT8&e=E|XO0cd**Ic@1LoM6WBZu*eN|nf5l-iS>z#M+y6euO)m6K8 zeLK{y&|Sq0;`UbWE}m;)&r5#LVF$mYmim|Q4t*OrKS5tR6?f?Q81K;UP2QnbA;&N1 zBgWNyO?#Mm$S-35hTMyIhrBS`Yp~ZJA#bRcAIUppiFiW!jm)Eth#%xd{6G&856FMP za_AGJ{>X=UhhCz6kgsH(?}NQ^(LT^q_#5TI-^zc;EB^_9Ais(Ap#K)H{#M>$$5&o{ zH}CBC#mkOfxEyc&i}8!N@;+Ck#4i;T^SiIK;u-ittm37!7Zj6NEWQRye1)3&j<3=` zE$#iMrG5UiwC|sm_WRS){#ug0fAC#n2Uzu6F7d5nzr)q~`^SEV;dj1?>@T_aon(K> z#BV42D<;uo#qzro*?J<0c2G&r>9hC)iSh?hie-BGj2TO3uax+bvS9JdC5qZ%rjQtd*=|6|LF(a zLqiyg?^I%)e*Ba4!K*;=$;V&v88Z7DK9=#*6&JejU-FfL=RmouK~o-izxkAg-#%i|;70$j;>e0QlZP?Si| zMLHSJzg_A>JmM(*PDeT!kMBTBl`}m)+_Y10CF7-T*R-opk$8AaO5ojybTZyaP@Xoc zkJ9xz5R&n3{Yb87h=*Z2f%gp3$#{eCuH$0R)JNex2|_a7FG+Y9suOtIkxs_j3Ot2@ zqD0yPQ!?Lc;G=Hpqw4s;lq`4T$1Q&5z76^4@16(X`9VyMX@ysG0N(f{yigL}r~~i@ z0gvl3^-*~Ij;&<idCHv(U+R;ba5e2)l z!-dkxc;_@>9io&6pDOEc0N?Tz_`XRzkEoC0<9CoH%dNp?+;;HMe+9UdT<$fgI>dPC zBu!h*g!fTp+?z_qE9|U`@5LluXIu*JpabwmpNw^t0s)^&mLGt3KJXp~jd&d66&}9} zP1ONevrg5t4}ZtrQ3v3SM+ck>e&Th*rSJ~(@JQ$9vkUP(EZ9?5AIjo2_W-^V&ex?Oh)sC#wb%jLPMG5&3 zuN6%cWu_cYi!kSo(kl17*U)sZw)wB_MqT@6E$TLr*Qk3pDSc>C`m*HoT<}jLf1pnL zF4Ztz3{D#}O^Y@iTy&?_jq>cxI&!>({Bc@Qcymsj%%>ML-5VO^Hl^43>-PWn>;5B~ zyEk82)qd-Bb;hoz{N}Ec{HguST}FDwmRrBb(B$7M_W8CK%-yn2D?MeOw*AOvz3;ns zIX%{G)(Vbng4{>xgWdO@(Of>-XnLXf>`lJit9(y31?I1vzGsTwef-uyb84O5-K;aV z`tth@@3b!z?A^SyIkUQQtCp{KDjix{9|djC_>!UZ-={7;cwa$~niVwbJ&bKym(se7 zO}ig0Y9`I9(~9$PH)-7t+6qdP*yr7)_wa4gqUoF9!!BlBm!`SG zuGK}ow?1AJ*z7Bq(=@Y5%F}i?8POg+wr0Lv+N1Nwy))S3n{7JMyLM>1r)iZ%d$y*I(4yr399F*9z*>62%%+!j7~pzq zhYx>W-(lhJD?5^HYBxe_?z=BodKq-pp=;B@!FyAMmQtg6|B~x!ADDb zWJ5pSTN?6vcTh7wH2V>n6|DZo(`NU!A0ew?_2-aVu=*3|P_TNtl#BR0XVY2xtkTY- zjpnsY1K_K)x~gXVrnB}HmCBgC9HmB&f^D6e2kgrdnswYdE2{nM+jDhu&Io z($}tL+&bTl#_kN?yVlUnGZ2&Ao7jGve$eW3wr={NvOWucSJ(Tu!XM*u>Vj+qMD*3o zz8lG>70g{NsXkEuxkJa_-3i~=_ogIy#@H%qMD0gK|9e!%hEb>8d-kUGNs-iWXXT!c z#!}wvMfT=UT@GUVuzmiYjYO*HUb9XUQT_OXJ(|;pr;pw`o<8u`oqLzwJ!PBL$sHE0 z8-hsg0&3HvEfLwHdH0U`?;n{Jt%Dt{VsrPs{<=1GS@pi=6E_Xqm!+lEt-i}wU3z@cVA|ye$!=l`Fi*_%Mqoj*^fSHJ^ou=OCN2~^hap=Poe1^)khIiYeh_DBc@VC zG{L8(rm#&~oh#zEJ0mK1+Fh4aWo}Iy>f5!}$4lF_R;xNKP^xz~w&kz8v@%fLX|>)r zfZnD>eTW+Ri+9y;cHevAru4e(I{l`qW+@}*K`BMV+W2T4z3Z=w)%Es9ve%3JTlW|3 z-YQGrzn)-|oWc1?S0`2kTQ!C(DZJXEA!8^!`9Pkzy~Qpl%UXXaz=u@ZB?uSd=x z(0#i7Ghglb%#jr+`IfH*%i4}*i7#b2n07_{5x8<|6&!2K~5pK5mKHkXt z?38k>BK&?6KZU@u0eGe|K81KAC)5+{=GpjTUB*958Mk2VV-$w#SadU~JOgJjWz6l0 zKc(SmNSjZSx($C)vWoG?zYaN z+I_%d*|R}UvFAcv+unqSTE`v@qXPCuEc9G^WPfSH?TU5h z(H?l^t2;MCY^m<7#NzuL-FXBOH|Wl3Q0_e4+0>P9nVtPzH0=W2;W@nvb>~|sc#-a; zp{Xv`oueW05@1?5&!jtZAmK9IIT)V(UUxnP^bfkj?>*eBJN3P>Wv)BZZJhYk9Uf+y zBnN`v2-h$tB2caA|b zjrBX+;T-38UdQTuyx*yV4;%eXBU~`S@8rT~6a7vJP$v1E^Ff^KcMN#q5Wn*{I1lwZ zkCfx3zuy@SFKzNWr@+jx=?q6_h?q`3lxQ}c?gg55wCS9L<~+u9_)XRCna-oI_I=ZN z0unwj9ki?Vq3IMum+hwW3Vq)^0Db00?w@|&YduNTZ;2MjD97>xd;*aYKp_J zk$Wx0d8nVJy`JKng4-J@&OVs=W{UG~wB}nW&QD-@JH>eenmyn;li{TYU5Cd$9&(** zusrNK{L+!DGMuZ>kFU;f!nj?N;bZ~q+6<>TgqQRg&b#p0^%)M2Q{0f@oDW^rg`7pO z{j`vi3-<)OIw3S%W>-fCW>dD4g|5FO+i8PfSeotN7p=5q*-kzzTAuA3i!QJt+qo8) zE3+L3?l~&kc>(dhM4UA|<(vb}#ysU522V`e>D&jg(|0<(VEc@n&b?WhHgl(AgLBqS=MES)d#7_M zZgX}zkHeHBb_V#hxJ{Y57WfHOmM}3I1Hw`!K1HlAW8w~U!{tnLMz2}H1P_C*Wa1aN zXZ0W?K0yCi!^FR#+AaNoS@1hHw#DovdKbeVa$UcP$e%aQkOdO9sw_z$0++IJI ziSuE}c}y&Y@6Km}Pm&ifF&J%m^h_k4g@|LAcnTinqhR3bp1dLPI>rYd6Qz*O-|Y*0 zjX3f%5kiccOzcIASxj7mh)H2$JKSzF!Edv6n25m%0VeK+beD+}()dymiOukQ8WYT^b=+mrSNSh@5;hzkj^@8b)fG)wlY|Vd|x%UCYr>AJakKje?B}G6K zW%{gVOmh*KvuZW#IWvc>S+!GVXx3KK%>!Kn-kYX#I`MX+S**9c>To}+ziOI1_m+hp zmVDi-KAP3vFApchz}ss&Rm2l|?`y619@Cu7>d^c9WWE1wx`d_P7`Bf? zGDMxU5RssFJM>sKD+>sq8u62u=-{E8~}Yu1x2 zAwiVzV46U);3Afg0DJB&bDB9me}PHCy1&e8*9jcsmAt z>&Y^AFSMkZ&zCv;s_meT9%8-d0r)YB0pRH}^8*6xMgOp#^#I<(AZoo-<`S9!ua`N4 zF_HwI!r)=OS=RnxkbT%u4rU|hthYRZo~8x=IRJ!r6ai-SrDE?X0?hgc7FgB?3Ijk; zVq2NX@9+*^pN+Ct%d&|dE@Q)fT;@_eD)D8R!vki)zfsd&3K8=L06r@-uOq-47$vP8 z9zYWYTI=gFm(T?GzRVd4ql0Y`jn-Zdz<|=#MIh``jz!}<7X{&8iU2DjwBjd4fE7p3 zLq98mtp(Gl)h~*G)*6j5%lfw>SeV2i+xk@zOf7g4bhq{^0!BUBA(N{z{YIEQ^ZE9MfKQaZ%a z_+91UksOyh#-i*o;c1{)(OC2{WGJO;Eb}LjBClbjwYtR$t|C1$na=ATD5cFY{XI-fJ1+QxD?(zYQA0SCm=_{Heq zH`u8LdCFafaJR}@l&g$oUIeB{MGw%clyW)5t4>lb9!tB2ST7N4u%{f+sa(I9!;@ur ze?a93CzLCVnO`6sekuob`gqC_h04{(($df`!#xN%##63RzZb!c&eYY_T~p zXD^b$p44YeF#(KN z0icIS!_QKP%J8#20t^q11cG&r;=s@MUX1a_+MozN&o$>Mf^yCIiXhcIIcD-}?!)hM zL^{<|^IE##f|yGKsOH9)b28NwuDRks*Ia#|Ypziulxwb41S#|4n0Yg0MmhUj>d9o} zTGz!~YD1Z~#GIa)$~Cun014OJp%9g8?(_%=*W9Hzlxyx*1m&806+yY?K1Gmf{w-$m zoB6}naIUz?Q}bI6m-ok98bCE4i#bNTGZ&L(}jUiura><^W~{7QW5eNXS(IZS*Nb7>Lv{yygHq~33H zq}{6kp!d=2+dnD-))}Al0b!paV9H+I8-#x;0y_3y8uF7Oz|@y9*;qd-0!*Ea+0*(( z5nw8h>0AF+1kB;r6XRD!K)XA1^nOLaxP}>Ecg)OyOTz!8EBAPoy~a@1%U#+`%j|OJ z?_dg^j1`y_C~sL9zR2m*RRmb(XC$R60xX-tmQGUySavjfbGjnHvRpPmh9bbSto|Sb z6#>=iU7-=G(hO02(YY@gszGpEz2o4`P&fTP4s>{&$2_PPPcNGHq)}wawiMX z8hn!?`j&gs60|yv(b!KRLaXH*ANnf-wE8v*!azkpDdMDOxj7JU;gu{a_GI4C9+|Ro zm)cNfWx4YpWiIOidX)lzH#f3YwIaZq1M!S&)hYs<_c_C&&LiM|#ss@@#2Kmx7^IeQ zOd77Lpeyr9&l;%+&;V-2%gqm{<_sUo2779L#Go8i?$Q9NIlkPv7fuLv;EX-Na}8I{ zqkDodQ6WOBSyW<@;(%)wvNnx+UCr0!y;nXU-Z_J(rv9hepF$>*Z6p6yla*E7mp zdWE*nD|gPu_!K;wVR57aKojll4#Gl3K%7L_M2i#wE%GBf*Eln(c!Wk-0HeaC=5 zy4Oha3p)(i3$Lgt)Z_@QUnCw<5c2gML@gH;lOx`BB0$*rgu(N1UTaw zx^bN%z!@DGDyJy|oY7+d2&XFoB7^_k%sN96;2nz-;+cvdyYlhn=6Wa{zL-I>%CoGH zBi8zImp0R~3(B2p1b^@acDIWZ04(dzb>hW}0L%Dafvrmv0hS#O=UA620xbKGmR+U@ zu&kb~x=|5e8Gla4x?B-p*=|<3LJ?ruUF9HLsR*#_9*&JyDT1_YL%BH@N{5eQ*?FF2 zqx&LrO}R^(Y1vKXP6rqje3HHY76kyy9;G*LRRmZzinH5oiU7;_>l)VWiU7;bpx5qD z1Xwl~iddTz0hV3D5#&xqfMtg;`0i2!SavZZ`ff#lWglQ7c*mA*R4l|DdVwd58u^C+PS}xj78XVZr>GhjJE-;|s05#V~Z>uwL=HFp0W%3VSe;Foe|9|7Lx`1WgSfPLj=hYkQZo7(;40Yuq1 z_m{hbCV&-p%D@!l?>bm^T&{*Z4SaF)Z~`3E2W9@aTy$i?8I}`w2~B`t+}Vg^cFnM{ zShaWnIwE!)!!M!;@Y4P425l4pBO{DVjhp->oA6Y&NxCQE>wd`O#9a!fh>mgR8zh7L zKWbLK2f&t`Tm(X)M}U@IzM-iaJvxp$8uc`t&C(xDs6aoFNmW?w&5ioJ& z#XuOO2tdX8p7jR%X1VM!oYBeM7Y^PSD#bXVBxD(TmwO(;xowb79=p4nNqHKdAz>3T) z>-e}?1uMeq82GE=Ib)gOm;PJl#@&g?$anT6i?{5yCiv6npCej`@WQxTH)rx>Nm_k zGVX|*O9+s|K7OYMu#oECA9o2&fXCy`6$DtyY5vI;fZ%uRAb(c`xCMxh#LcIOcneop zk9mk+vNfKGyOc%5m*S3&=ng*18GM@ufd57oJcCxh;t?>H1;3%yuX+SOEXWL7FT~9* zs2#p)Aj-DHa|SRokIKCscgvBHZA`LgV@DJGY1C^(3lVQV-;X<&f)E_n1(iRH=Wat? zzupmDpM>p-kcU^2jDn98p@SAo!GvRdtO&^9UGv*)%^STq@ySPhe0_=-BxnK$ofjQRC3V^P` zYmT@%gaDVbJ@0g?R-YdVU6$Uc{| ze?Sos*%P?#aTNiPeFy!LstAbefmAcS!t2-^^GL{01R2PBh50Y){eX)yqe4#28;PA+ z;nE`N-L}G+k9jrNISP7vB?3Ki8(S;aBlw`^@r&^W~9PA8v?^iFwI)oo>uR2lI~jJQeSFST;V)It@sO#R_`Rl&&k+FAsV86 zx>uMV5%Cxz_Vf@RqUe4VE@ct1yuwL`MZx|=tWW^3^E-&N23N?*8+NkA2UeJU!5lty z0Lscd#J{s+R#v!_MZ|+EoV7&!lHF^V(h+_+i7pI##;7ZyH;GHX4VD>-V6t#GLgcNGq;a6Y5VDO}VZUeW#yko{ap9mOeYnj#=VZeo

60T4zK1cGN;0&aEe%1;T#L5U~h_Os_?pRdptK$#1chl zrv;}|#4<(5(Sp};cv_)kLaTQzM4kR+Z6%6+Q0_eqzLfUGITNPZbh&~ z7+q0ej)9Khfm~`|!=7c`IkaxAaA`9RD*CNE%A9m`ju4LyXd&**`$F7a_lLN@ zZH2f=ZAY%5=j>SMVK4Z6@|F<)IG$_pq?S_wG@ZA`%xO=UP7NpIvxLwl+`c9_w)lo ze5XAq#P`3k5Z{%?LwtKVIK-EOl_9<+tBT~X-m&FE@0t)_Fx7?lGG=IqFD{0M_>ey` z#OLtQAwD}dMELW0)^=HAY=}?4<3oI6oe<(<=cEvy9S;fd0dPu)&uE8-_*^wDaw5`J zJT4^72=NhRR%AVCLnUoah)*4JBbSgiMbhSnxaMCF>J!D+Nrt$#Zi-yT^7G@J=;^hQ zJD9s5-ifCKPKxYci(DA*l!pd8C-M->E{b;wqwKm6SE8FDPm^}5M87MtmATvEp=~Mn zZ=@kE@%|opm$U~Z$1{=7nR_TMTJ5=+j7OC>2100@agSNXOG_>5An;G{CZn1CMxxI@3KayLingkZ_BB= zMsLfxu}*Kx32ms}mb1`sz1`(OmZQ~tz1??Y z-B=MC1g|X6+j7Lw{B7A^F>9ysYqaPuvCi{rCWBoZqv@-N*WoQc(k2P+PteqQrNUs( zF)Kj9z&NAIc^oNuux3_O%WCK>NV4WA0{W#mM{|TCpkIn}G;^_aMBu%H+=@ z%5yYJJOFWyrn$-`GyzssIj0anoTFJ&C6`}`b2Mu`LgF0FNs0io#5tN%6oGG;D&UEA z3Iq7C;@B#azqKgO(HviubdKiCDwpa}iSw$QXQ_lZM{|Kf#3%uPv#ZRn2q4bUZ14cY zIhu>ATtXAziYkW(O5{13t2}_jIht#fW6?OzMWN%hiU2FbIhyMf0al1}G}kKv8b_R? z`I{nOauw%jZd3$3rHXSjHz@)hN5narn-#$?47s$*ycaskb2J;h<`Cy-HdVPak%l}_ zKNQS7A z79yOmDy75prQa@@{S?wGKCV6lqrt<4EALHfG%VWt9GdkWsa$K{CF89Ju%J$peMvx zr$&XS44>!`V7NT;Gf8pa`AQu5nXCxvT+5+~pjgd!YM0tj=JIN% zBVO%E*R1pa60T`hh{`p`c!Y#&j#V7WHODD}a?J^fpj@*`5u}<;)h2(uRUY|S>ZvJ? z{H(5aX#mwcwc0t4Y6{n!cA#s{JkT}kl?dgUvlT(gJh9q*fHK9ApOZbA;>gcA)h@N6 z%!{g>5g5GXk)KNy0Hz&rG1uIP!Cw zB47>{M}BTs1kAzW$j=>$fH_zXq9@&{2(bN8KB?cO2(Voo3c5!TV5&G2bgv@7RBC4LqQK#yR?~>JyGql^wb~^#0p6^3 zz97I4ct)|_ZVm8iwaH)Cl_yDF_W;C6l6R|JLKEQQYG(?VijyR%HPSVSlO$;h5n742gXxL`t`R3mGCTs_&B~J`K}A5^ zijyRniU7UENs=r@K%W&SNkU2r3=tw`#ECdb(peGU z3~`dAt0KU5agwA+5n#JGNzz>rV5&Gt(nAqosyIo~OA%n1I7w2h2-33lHRi9hOq?X? z;8`Y4l9bfAw3(I-tZ~|v!?Kt7C|BkIczw2Sjd>8tpRVg$0}QJ%pCEuZelWrV5XTS3 z)VPEuz$64F0mSixLu%xbC2{;e6F{6cSnL6a(*`SRTtXAzgc|2l0*KQFt380kX@j+jAdNhx#&qz|DNh?5=OK#I z1}D|HltsidYMjnslBW&M@&GWw&`YP*n8OJmP8*!&0f^HEXV7xWfZToHn>q5ikOY(*}1bf*h@HtTFj}*z&Z&&7KHx+TflVm%=IH;TmTO znB?B`qaHxww87&Z0gtkD+x<1>8X}6*1`m3OFQCkNs>Y=(BEC@LOgc#I6mRhW5~mIR zp>)JP%nmHKtd|u5qm9^0-l|4Pj5gx)+`AC?TT1*1495;s}FPE9YkpTH**pz$18Jq}7_w5m6jr@YTvW zN*rNGt92=hh~Zl22O^3i3~fAs#1V#e9>F`p5Ue%Z4FRG!!jR=5iX#lUwJv25v7px3 z4kmeop|b~&IKog=D@R&Bp^C8Ut_UjZdMTMI>`D~@ttE~y^i>43mN>%DUlHI55r=~m zsEWgw;!sBz;)+AX;X#T3D{zFNW36dc!BlaCA-^{12*Z$CmnB*nT@gV_y!Nzd`p8;m z90+npz1|a<*imor2#Fo_F&@F&Q6E}sHdCb7Q6FBLw4*+*)@6y7Mse$K36Ty(9$M>M z2ZG$lKHLNJHnJzyn$M$5Ze&mPnoDeCPpfqaLx3Y{ozDm`q!U7Iz5>uiOwOz|1JwW! z8`-lx0I`w1pw=Zc0hZS~mxD=eWUo{JSmlU~?4uL`3sJF=-K+>|Bl~DYz#33&WFMml z=)Ynk`&dOl%!rNb<5gQBBE&}a35p;e8=7j(C#kpC$X@E{EjF@O*SfTbdatW>`qn`2 z&QTbCx)K4s#YXlS9wD)jeWv12OV#zB%*00aIUYx1Bl~<+MSAn3T5}Qv%8l$(Jgvk= z_Jy@B^`%yq*E%OtE3uJ%RT84u$i7-38lrtJsWthN_i`iqG7nK~WM5nBQWg_?PLbVjj}y;%_ehmr5DTC)joawGd5Po~(&exlZ;HkA2%t+SOf(VMVO z=K*k3S(6LG7Da#(Z}>oXNr}K9vI>tP*2^A&jWd=L;#QAf$i{iP*8G7=EW*n+>se2U zOH5>5t#zp$m3XJtsj0)zHf~HK4tpv@$gIYOi1k5>%j${qY)YLj;G-8z^0(%D&c&a2c)?BIv%ylDe*D|YZBihvLh zJNVg(fKfy2;I~x-C?R(6bL+h4S&SND2fu?NSRxM7>&$)BO6=eV>*RbXcJMpaxzv|h zb*XbY4~14@2fs)GKr69>-%SzH1!AW<98&19uca8iZZrfNPZbEq5!*^AA+r!+(@V18^lQeI8cypDvJ2Mc*DixXe0LHH@dZdc#8(o7Lww?|4Ds35+aB&+BkI+J_|#Yz;-lZt5TDZffvH)G3|Gc2}j#n$nn z+R&pY!EhUE#$SeYRi_B61HqP3t-EZLpQc;Io@K+R_rW4RV$heTech#8}zmu zlg45{w*#W(v)T~9=5@T@mZJvtbJ?@8pUbX<{anWGd|gXB4I0n}wPniy6kE2RD`G&i z-ay(U!JXv?bgw#t(QNJprM=(uji61I(;cz(SO&hiCG}FidQ%WjY)T=f(eL1VuX0h6lnXJ~WC#q@2Gz3D* zLZhA)xbNUqXiC3@6^`M1Qag+{FuMH${`%~%!4EmFMZtQ!v6|J!^hi`&oBjr?&0?Rk zpH4wF&3FcaQcg4OC+n953D&dHQ$~VmAAmHw2b}D)`$1t~A4(f8GCpR7MUg~>OVj(X z!s^bfu(^xC-p~of*Bc=ebT}Ig6im4>xEh(fTzD(x=Jcn*tL6F7Ia6*C8Gqi#=)ozs zij18%5pq**6PZ-a_ypri%I(Hr0Ce=HJmOfR(6#Rhf%s%6xYmU||U3TDvIcd~>%9p+}!(g%V~;0jSmE$vHW`|A9YeUE{L?&G;^dAd$lPH~yZ3wuOFAWOruopv?o$_^X z6Eb;C@OR30*-UGBTd2lAvslHC`p4mJJWE%9Z>&Swx(|O+p2qmU>J`P9#J*Rl6zTg4zD@CNO7Rs)pKc&7I|7nZl0b?ll&1>)l%l`xn#5fIEsMp6Yxmg z7>kUx0e@0{#B;Q4TYGc*bL5?jc}lZ&cviQEprav%Z$Jy%e>bjWg`Oz(DmJ-CpvyH+4qr>EZx zZY?q&;b9*vbH2!J2myPj%=sf_?U5TMbC%{_gsI3Lt{Yu|QdEyJzdce9-c8I0(K_~M zJ)Ih8k)w)`tCu-Fau_VP8$1b``!&WidyH-zLzM5@5M`VmOc{rI=cDcIMm%Wg$CRHy$S@RVcJ)=)o6>xgL#W&(iZH=E-cG*)pd` zreXNRcP)xCUt}7)!V!8t1KEfSr$ux1e0s?rxr;W;)AQNKtjKw#$j#UDIk(u6ui0Kl z>iKkTYNR{+#{xZ{!&f-+BHMYP%;iM>nStCQJ)er@M#>Sg_F|cfqTQ~jN4wqA2gD}b z2!q8fM<=wG$yjnnFx*z@VnTDP(a-F)dWJb3Q5M9XuDeh{D|!H}($hX!4=!$m?Q7X! zr|S8PT`h84KjhZw`5c3E>6g=5*?zjReLce5K10tZh(9u%K08y-UxA$6lasf7mYy%a z5v?a}STA#Fkr*aE`)rv@kMKLg>~mx;BeI9>utDa6kzMHb_PH{b8Tp>M^JFfo=e(u` znti_1EEFm3jj{`5E*$xS-S|S8i$vP7{VtNZHj&HGZS9L?E<3V<(Q}E+>-mjUF675l-g}ZQr72oq&uc=1==>J?lK={1N^tvi+Ezbw6@;B$ti- zJmzcUQX?-%k$Y9oGAFU4f5j$vSJn$h&SBXnGM5vn#xQGtrDt^nXRes9?Y(+d4RX=Q zcnqnw?h_IUBTWqORGBM^aNop^__7WMXV1t<4EK({tP_zdjoeBJ-F#U$BG)f+E5?7j zk1y*vwIv|jZC4QH~X^gL2f~0U^#Mk`?6j_t|?N?dXM_zm4|pz7JntrWK4L1F=X!8jEHCsws@NG05|UG#Lip{Tj=ksm>3GOx>r72l^mZa5h<^jLJIw}6w@^cCXw=(I6uIDis{J&6H_SR zkcw5HDrZ=AWyb{ZB}LTHPEs+E67KZiIqDYrKT({FHOZOqIf~Oj6>ea-$zm?7P|{PC zFxXluqNGlhEKig$g%VB>h5l)(oZ%*G(l;nstx9fBlrV)7HgBQ-QdQ1ilr?DUTZ39oQA)S%#pQ9gw_a+k>v_O|2 zXQJZTvH0f9Ah8Ud*AMi~>;?|QM9si}%si&~W1oRo!6c+%<8V+8!2lIFs9?UJa2hb8 zm{9^la*hL~gEn4vyzwxrzH3mA4i8|(6bQT@JR0SBhtRwa zg-f)&59sXeBIC=8VU!MhBr^WIH!*|;J{B1(?*jVg6Opks;|=nCYIFx$$^~$YTuukR zN%tRy=-lIng?77Ku9jbG&!>#_WSMl6cWtjQ^?Vn(K74{pnuT5sW)D3YH4(P7*d57bgkDf2C8<; zq$0g;#+2ut(vDxsnbrjF#1)^T_4*g=cGqY1B;V~2?OqtB^U~;{`HD~XeB0|vtWDiZ z+Kwmphd!k5$fV#tLqX6_PBS4CIqIRGqH>g`U*&pbQReOr$z0!mB1HAgA%4xPq=+zl z4?Lb7{VofGG_KpHw6Bbh~1-4d6l={6jey?ge2FE(v{t zgwBDM{E0}d|JOahIOjsqasz!pr{v;dxvbvrxi8 zNiR*yV%Y2h^&4C>9f?nw28m#G!WOI6%~Si7$-Vq z(+(+k8p@~O()zcdO|KjXx-tR!O6mZDo($$S1myz~_(vv#z9vC$M)?f_^e}Wnee;2! zFD5`Yr}iP}%V2(ypnR?a|47cCO4BDK==Uh!EkGT_uYT)+pwa2d{99A|6SOTlS_Ic1 zKG=bOM6#y0OVGh6kKxk#Ul;<@xE9cUAnF@$PJoV+n$86CR9xjVscBAXOUj3kEX1XR3Hy)()Bi zbM#%V2v~i=428MN9V9Suw1LH=>7h!#L`CNCr=g4#@U<&~v}*QJ*z>I$><4?KwB2r! zwC`L`T6%XN+~Y}mCn4>gWNG&#OS>mo+I`8=9!QqVy2i9s=46HAsonOQy$AN0Mk`niVup5^Qomwfm3&vpXJj5_+YDclR_ve3o)9(r- z#+n;J)HmKYOUbw^AOhjx3qhDiq8I`03LHYg8$dV%mlS+YK(y_X zAUuYvTExwL0nw7ihI>{Gyuk+E1Az>N!{^}G&Z;8R9t?=+?`mpVJ}w#V4+Sz9?#6}( zR`K^Mw9p*9jhiLIdpUx93_-OT1ci1Y?7L1DkzK1e9mI2FR}cj4pnQh(WNEyfJzKTy zvB4~2IZ zK$2`hHy~!7iLh@RE;*FCfhr1715}z6a~#T>acQ+LvO7(6M3Zfvt(2bXl(clVsZMQ6 zXPfFYK8<>nqLrpPGg~Z}?ugdW4tfA9A^kR6c3}Ec4hpx~LOmJRx7jr0B3uK-;J7BGJx8K3AdDhWj8$t>gz!}$EWssX=EM{+M6%80+;>Wf*f#nY9Pi+& zsRa1t2#jrW660iSJZNG*>|clFf*xzJ12xcwrAH_`V$zO2P^K8yATb-qQmSqypSL85 zOT8wdd>k&V_F1g?^tUbHocbe_zu&e*ht>|dneDMe7VC=>G>vCHkKna5Jo=0XJyL0arLPWO>o?J}3B_Oc@=M z<|=J(GJCW{+)d^vzBrJ>`%UIyB05Ct-DDowBKj6HN%XB|lIYvaB++-6p6DOpEq$;j z`qhN!!KO4+47h{M%9g+!Y&Nur9&8@oBDykJ^pIrHRmq}jl;{ULL-Zwvv^s5`vicH3 zSUp4pVYOcbp&Z_8{9fcw>Wi8u=!wWrWovCbbiRt16Lg{dDX^^>*8pzkfPXY!@o*jf z0j@eR8?M&H7}y1aWIJ3k$j{b=oHZaU!*%dh1QgfYw?N105g7CJkl{uArd1X1q2y*c z>WKva&f#d(9gbI@Yzk=VofPa;8C{RLM-7Q`&qwb-X9-A}fiNVq^9BiZzr7TXO{ zHpTZJf)1xoZ}Fz=f0u!EfLQ%c*L(6c&HHf0+qi}b$IXPi5V#-LA_=eESupH6rY7FhG9Z0pvJ@5 zq4|-T7DLjA=^%XruAR8F;T*O3kqk@7unnY80MC@TMt*>dK4#=D-o}pH$J@A3<{S(z zDD8(!8_vGK&v;z=Mq>dWJ_Bhg3Mbx{mAS@;!|9sSrbFErbqb)0sb$_ zXXSP-{$C}ovPzT)gcx#zaMcqb)(_-TSQv{T5vQqI42aq=CWmui;AcE8eWSh*pz}c* zi|V6sjW`OKdxf--7#?2k_@TbJWwgy^q4T zagC*%K@`M4xfF)+VJ93gjyMAO-{AWhmyns2if43OLL2_q>CU+7DP|O9#F2}ULRs~c zR8a-cM%ctPvshG!xF73V33^2l{&0qDDcpcX#&8b8{7CEf)B0~g8b@SYBYr_<1rke` zaUkU)B+g@|4KfcRaWAfh0%T}?Dehw`@CVip$L#|YzJqHl<+QdQ1M?RUH;y<0`B(7$ zf=kE@VJgVPCA29*q6@BiiWx;2708v7LRs~cB&?tQKeV1x6hG)PX#4jULEajW#sj$l z*NFAVtVCidGnXNA84~=xfrcBA@oiX8e=qK1p2Qy*{4#F*-zksa8cXOnvH3?dH|D)( zAYmMF1oC$9eSk~I`~eC6@3?v*k0NXUgQJbBp78Yquc!gm!UJpsxhKd6wCw`4Emy<* zG~v=WUcDHSo&%`>m>qD9cpaHW3Sj1AWKKq64X#n&B6BMeH{fdc1sR&^pg)f#W*36; z4;BMr9eO&U3Gfd1-@+xJ_aL#G8469wz?h4xp3wD#97VibklNwWD)4e8VS^m5H_!$? zmGM)DOW$}QOc`+kNPSVK1lNc&kZD9>3^Nxaa}*NGaE-binM;u1d$;j-A+vwfX8hfZ z?ESbJwjhI$9Zd;E6oDWT&u6PBgi!mywilNWl7?~8#U;ddLL!Q*jCJZMX%r=tfz%&Y zJq6WMKt&%g9PPE3G;1Zg;8@>Lpv$LR)o`BC@XT;N-tr@jK4S@_1_5>`peN!Q(E*v` zkvN)}?#Nt;#AUcf4MgS%Bp$^zo{tmzM~%VX9msx&tKo2DXf!1VqgO)=AAy%s2%(~w zM)Gh8A^hJ(eVL*7;YbX{RmM8?lr)MGrh~*S>Us*QrvPE}$^TQM`BH%&5mXy%mqO|z zAe{*4Rk%hxkIeN*T#akg8_2wX#52r%g3N9tzQEP68yQ6FSi%(&kAE<#Xnc84OjH7O z%fkC+TtdWPB;vU0iCRyzdZJX6qSgjs#uzz@M}VG<3TNOF;_gP`HfE^R$4I<~tBkelDRUHM@mu0uT=f)LPf;~h zU|=f_Se86%AaG-Nk`+M>AGJYJMX;Q6Hq2stH-p|-Zeo3EmO%l#(M_;epl33cdd&zwH}w1d6C^5tN*Xf1)He#s;f z`WNd5wN;Hxb2IfUt1{=JDxvfMGbs>!+4ol=><4-f!Vr%(s1+Yz(RPjCjh%+gg-pFS z?8h(cDlx-CxoG`32#MgMDivTxHzV`l(^1ctv!M#)gAUX%D&nFtStMWfCc)!~d@?v5 zX_HGSt47IU)6^a)fyBCG1kcQaUFer(v3O{5G0hp4EP}mxcri?A<;@W$n#_Y5Dbmnn zRKFJD=nkkdR)3(%ZOoqJPBteBOY6yjIY%&}#uz3ja%_T~Vp=NTH6SaD7ktnJzy8Sh zT9mHh4afdlk;s z;WF8P+jyBg1UD&-#8#ibwCq1N|Nm^Hq@L3c4*dNv`Aa5t87zRXYC=T73LE z`%DzqdR#uO_m#Yp-KUjasj86)uVT)7`d3n z?RP%up#7I^q6u?wC0ceVGRGwo)*^FmGU0Y)sCS|Y(ycy!+G@%Rf6CMfPGrP$xW=RJ z+5@qQZ7VL>u1tw71noENiW2eq0c~4^q(mCe8!Lg@Qa91! z$_y}w&m{b1Lr%kej+f@W2^VzXjZW0H3Do-qT;y&6o&d`4d@RuZo2LJdS^+PgXbW$6 zVC3jl9tVf8;N@mWm4I2Hr|Vay)N+MY4gn!IH{bm89|} zfdkvk1Kdh&|6^4!=5vOUE#FAFQdmpR(pkpq_Xf8h=rEZ#s*|)#Lr#1O@fZD$H_6e0 zEE&Xd5+f}a1(M@89Vk~|jN?rj{ZD;d!f0jgpQ$qF_pn=tNh-AvDarfL+oN&8Qbkht zKa(nX{ttIR59t@)*w23_0@%S30lbleec`tw0f!$10dI<_W%a{_35WAPlNI-BVmd*} z`?L^~TC)a)Y{%beO}w&^1-#7_$wuCqaQ#sq4hyz1yvZ8llWY9eQm#2*DQ^n4#ZnOQ zVUPSz716~j+i9pl1(T7wfJS<&CTSrixrrV*L~xG7-&UVY7qc1rkxB$%?D9Ftl&IPxcbT6hjLSOOkka0~l^-k0nx zZ44PzxTO3Bj(n0M(W`#}$%l(hQyXzPbbM1HAlv@6H=_QjN<|wGS>;A4$=cpYd_Xjp3@qrSw8lO!mJ=r#!Zr3K{aMkL4x)>i$>lqRRhwZl9;2oS|KV z;PmM~r>EiDI>gHxM2ucsT(Wd}$(&_PCCir1ELl2r#j+VwXG~uCl1mELgE@>ewLzM)g-dhq3=%^pfdK^GeXh_{a90fp%Uv za|K#;!T;}aXD(beZ&^vr?3MFo&Mp~SJGyqdeIp7cO2j6^#!Xx;@&R-E!*e=9#mbmd{(fh!weuHn5K2STz(`41`Ok zB8(R;n=^Z>R-E0ueD=~s$&{tDkC-}rCR{}wFnY#k zteCf8d9Qhkz~HPi#5*~1|-otovE zzon1}bu3aI6xui?~;qsko=1X?oyp zT1Eg`F{D}x{#6JzG9cA5nsl?1(Kc$fH+E@J*12F6GNO9EIS6;%m=iSz8SOwV7TU=| z<4djBv@PApr>llD2~CW&s99|30w@o^bLy!v-0WqA&B8o$Kxea82XjDyS=bG=I#~vy zyO*(?5WNjY?=N72#zm{>&XWw9Zv1*e+{_T@%D#iFVypKkGYDduWjJvoGj4W7CKxAw zda>sQBTVy+xNi10YNB9WVfF`?Zj{e~JmZDqi!J;*bw4v`+`6h*$SaPTnU-<-s^X9c z^~`)Tw<9PeR@^e$>VqrnRObUyZuAl%nA3W&+YX0Z`Pbif0K6Sa&(qLGl%Mvs_X zA=$M0hCSahwv35zsL?HI6^BtAHdA|oqf~IB(Nm4jb!e4OlWvB7?0anTOuE-8E=Hmd zR_7SUFqxk%Jb;AhK%N&E6-M`S;EZ-=JENJttc28TFpOdqqvIqY3-(dQG+{d;hMIb` z713hL=w58HtECnxls+`Yxby@XybC%4>R~9z7C=2Z!hdnBz-BZytq&FYI;C7 z;eXV&84kvF#212>s*Qt#;I4yVmQhv=N(llEQUk+H_G&he2=_cjG-?=WkW*)f`rnL#SyLhH}_yD-b${TWn?& znEwxR?*SfFmH+>r$s}PW2}yt;K~RS#9g@%$G?OVwAdQ)XqO6mU1SU!eNf5AsfQoHJ z0lTif?y9&pRuL9mbazp)?5@2R#D-!CuCBlL=bZPwb2GBv@Bevz&;R-V=YhQLDfg7m zX`fT>y;;)t7V5^Fh8)6ims;yfJHlNe&HV(QFG=FpbVGRVyIn46WA1;RWBQeiDL!fX z(#I6&{-V#ov|+xqk@$Nw{!UHHOm}~JHX4h2ONuK`cZFHHBY6QbD}=0F?!mZlL*9^o zAGBCgdoqQ%0bNR&Z)_SGZ?CCiP`J{Er%yl%^2Q`p-6u0#`qpU}U)>l;S%qEhg;F2T zsp4vkxzfG(pfofg$Y>l&#Fci$R0ziBlgd7p{a$!FZg~#LL>BHxlk&QEDi=GyleFx! z(~D4`uC%;@F-gL@JM;fXiMa&*dVcy5X|55-K86lGh+t?#Lx8xYgVHwIElY}Hs1yf; zG;WZQ%K*8j1Z{G#6tf5y?Eun4XCY%8t544bBB}czsWg#P9!%m^p~aa2QFVto7ozG~ zPhZnY4-(i1k)R^ykC#-UB1oj@2c-o|38MRg*)-w2ygVekPu|$HO!w^R@G=~odNz}i zXwj%Vy*H*!&qWQ*OY`NH0~T&013PDrgrJ0KGR*BL^D;Q(E@E1ffn}a<<4{+HX?-I(t+>?Kv$BsIwWmi z{{d+^fP1ARajaD9fx0f>ZMUE|{aE&Lh0dxt2GTxNs=iMKG52ZH>4|DjfmDGk*L0+} zy+bchG@stQq$Ad{WWiE}c};7J3P)>Vp-3ba4FzheBe6)RBIJ*TVqt%IMJQ;y)VBc6?HOpU79@K#dKl>Rf$??mfspN$M3-Uk$tBv+(1QjU`EUzs4btBsGos~ z8P#>QvCy1AC=_&5cb)cVz+Z)wSJqTOc)GGqDG4Dq6>o2j$r~`DWwllQ8Cq1BnKv|H z4M0U^*TKiEl4xyI1vLt!!a{10SzB{Mlfq>!3Q`1&yL7mdC0rE=MMIHUB70Ps!ifk> zWUQN2S+&R)%|-hRIfP#p2nJM1U39j;ycRK3)KrG5f=>5YFdE@topH&+W(Y`@k+AO3 zfM&6%dC9_#IMNiInP|^C%1Edt)MOj53 z@CVROg;D)bq{?1*X>ac6z*1p*Y{k;HrY<#9M_J`Z>>@2I%F0kQ>Msq&YOAYbI!B2r zowz~77hl2BYG^{w+0ow7Zik^Oitbk`A%C{1XmvQG@F$|BXQ!`2p%1oA*0Ps0o7zZu zWg$`=EC`o}t1Bw(;HB+YO(Ix>RH^7pX=74(TFrtOQqM9cLw#*+1&h|$jm-5OGT89)BN}h#l^_5CG2UO^e*y#<6 zR6x>=z7ctlS~@}3XG_jj`}S8vLjK@fJ45Bc8VnccuoH5xDJu^ap>c?m(4I`TT9>2F zE^1g6Te-MBsghPzM=Jdl3KewuqUNgQi|04DNw;amjA~sM3zqv!V}ZH|)=g_;(dxQL zz}f!&XwX3=NpafiVnwGFE-$qTRT7CoOuAwb7^JJmEITesn&Kyfwj#rt{H=6muQH0p z8j4n6T+mB*ElXmHn-`cF2;D6kgsDNO93l{fZ-SR}X$q}vOEK(rv|tI?jAhb!=&lwW zyF>2Lx+wbkpsr$t(mgnqL6tit5=a7@Fk|22t3vfD) z#ug~FsO7B*i+I=UKv0F~_0e#`;e^s<2_eyGR0ONFz8jlWT~P}OIO`(E!i0Vx3;0?t z6HWT1CY$700ZY~RwJuf}LI)K?J*u)=iy5ua#p~v2G%h;>N&SPAiGnsF+S;Oq_I90u zSZ#!gr`95@_^k#}He2+uAap%w;)(hyV`GsD%_$Frs_f{*Sq33VpE`a1@^+~%UGG7U z7LJ5WHz37YQx}aCiMF%2ePLYs9V>oal|-L{CX23E*QCP#(X~i7LZe$1q7{}^6pH#O zL!}vJbRS@aZ{<%{k|?U5WJJr*@*%BPlw3>Fb{#{7jTlV}Rl*uzv6Tb0U9wXUiG`yI z4H{aV=)TeNQYhmIG1yJLOw@(uC8CS7R7?+I=aR)Iifq`AW?-bCD(BQh6Is$K4Ky?A z14eh0)`sX2`(aXDUKNN~{c%%E8x&w{RGC2tUFh;9?JWzJG&lLs>$hpmJ~)Erx|2(KA2_0ZCAL_Q){6^+yc z(9S8y`L>>0H12RBw3JM%%tSx04#z4(mDQ2Ngutqo){qcDl}c!Wi2+3_O+#B#Sa17v znRSVBZ*{7bnCzBRCzMgsCc~m!*mXrR90-@%C27^R3jbW00*7jAW$ci2+2vC^w?^t) zt&$#JCIn?wH6^vxeh9R^qYbL68SbP@W~tOHU$m&MRnMdc})}dXB zjQ9~HXJrm?mWig}D7TK4oEn6bo)5=bmqL?mZiD7iiC#d29jyxlpb@JQe{Gz&1p!1AFdAN~^KWogGkl(-5a6ic@)LapsuIrJ8+9Rphh#x~vG z>R|*k4r@bIw_%Zgksc+jSQ8y}(4QDClRHSQj!Cgld6OzB*%T`?f3;h0jR?&OJ&d`b zDyd|3l%f=!MLOE1=Jv+6mR8K;IZZ84iyKz9VgaGKqrK&f=0pS4BW6*oWG*zqKvZgg z6?%DjBECQ?3PV-_BB5He zpJ1dWm}ngY<*5P$`mfR%mjjt6^0M%6OJhqoD=q zl@i#n$Ce7fSrmrm7$(qm63bD$!r}5jxmM3>{Ls$p!jVcW;ou%Cd(v2S?q!xGgS?4T}! zM$x!vDKcbc`(+_aik2;JMqRFF2)uM!TnN8F^gPl~f-~(}rb`_funrn@6mJe#hiQ%t(>4J_GIF|%P zuq~kkif9wf(7M?Ylhu4gkQ2HjAW;Q_p)Qrsy0s)yUWyeHG(Nk#luja~TH4Jd_P?M1 zaGa#TQ4X!>b>Mh}s=>;~T$s(8hF&<4wKhqd?l-X*h`Bfx25}1)`RqDnl-;^2|19+W zvg%|Fcvd@b)b_*zCznMmu~>>X7M9Rx`~l2vWj2A{&hEYBYY`QNRiV=AN;7qtY%1X4 zIv_p$HFYAoyuGz~Ns~1&K%3N)INTLQ6E-UaW!8#;$+1*%>DNrdHB%`&yVh#QVRU?B zWtLt7ftm^(nl4+c@nGg}W!5T4EDWIT+J$(SjObM<>o&XF(uE~u6N5@)hZ+b~RMb`Y zp<>OB)nUytC=HP-ROUj7~q&fpBw}% zm|Qg8H>|CBQFB9k^Kjqj#f`1Yr!_8ZLkk(bc-%Nxbi}bV0xnpzw4q}(P7zLnBG@Dr z@VTJ%^a-QeTSqq)PJ~TETVs40&O4nxdGz8ji*Yb5gm=-Kwq7~86?M5MOhn+0R+h!^SdgdZ4YdG$N z#U!h+WUC=kSEaMxIA6vfy*%a^xv|nwrR7^--g1KxRDz3Gp zXE{k_?z-9(L<_5R=wLDs>4|W3b~*aYIKuyz`xU?%FW%apHKMx?gTD(XVlWlNExR;;3BP&lDyRyb#|I@Pk& zt2JPhUShG2ODEjn(u?F3A@pNTH3R80O&x1!+>Eh?b1s!v$Xb4d)w@V1o6tTIt7@pN zb}t~Kx71#dcvXN*2FS$Vsb5Nswyc*(HpHwEBJOr=`yR34$O8*^!uVZ%*AGkzgBCZ zrcGNer$*K`}6PkUQs2oK_j^gRk*s*43`%l!BqC{OOnwZGDrD}B@Y$P>C z%MyK0*4XVk?2JZAvE_k$TG@gUC#8b6tClQZY^`TluJ)3l>Bj84WT0bVifk8SnO|nb zH5J$zl4Uo&$5o)0MXb@qF>P#Ig0(4ll+72tif=bQdzOTL76GH^F#O@{L8v03#5)=@ zJ^*gEnPnl*?3fj*%I3vO+g4R#<7r{@VmTzCmx}^H5r@{)&>2f#HPhKCVl9=5h8_t_ z9g_N^cjw#V(87H7@*6Z9g`JKi%DEh8i44o;Sb0tA-5kAE9kv0gYRdy=TSqsVLcJ_G z8~doC#M%`{l)9=JRn@br^xUXDF}b6w%nn6Kk#Y)ERo9hTGYQc~6JaCAnDt|zkV4{8 zTO~vkn}4^|2jjm!2ftBrb5S+Bx6PZpGkeuqhr z?xu7=1zJ&P#cBKwnH-sUpC5B%=%UhMv1lWO9;}q}C1w&K66fN0z`4hl=m?_GK&fuz z*wjZ#tP&}&iPgzsu?VR~>L;qd%*k7pH0b43TS3$*)7rmvsH7%wiX^eiBF)Uqo{6Z4fsk`j=6_2HO> z(A?~Gv6x=Ha7Y%d5l2EQx(K(+ttML8R7o_d#15|>w`DU?dy{B*`~>;Yoe0))3eDV& z_lK=h3HA_}&`g3av{< zs8dD?3eod+U<(ctTXYRol_e@zE~|~EnLtE|a>RLh@DHCm^tN272 zGh-FjRIF^-llw@hv^*{dmffJBF5>yUIVj_{^)wimEdAT;7&BU#iSnd^ohyuuF)T4)8IpUx zco@yGDi{iuV!mcJk904Kz7HLR*=nAoS0s$wan4Pa&Oti-lpWH$DRWYm+IWZz&PLo{({eQ>tS{c5q?jhl z4TJ+mvU=Uw_Mk^)nb8N45vhC)IMZWy&dCy+T^*TWrd&p1mOF=fS^Jma9_p2@r*ibe z+5~hAQ*zkR*$wgTGJA{C3f2;k9{Vjz-J^u6%XN2dA3LyIF)>72sVG68YVG4iXIk4% zvSOld#{o}txB(p4`PF)Z6;PKmd`-8;kG)P)*+X*5Rk9P6NsoPdV)+3l?eun* z=!!AE;wODNbAolCsVN*XMwKq}~e3dV)7IRV5bjxDB` zEKk{;i}VK4fPu3bX4VwN;;7Nc6ONk!8Hu<4JTIva}mex*_S*>Q!kY^?;l}kduER zdGuSzGBS|3)$Vb$UT38}c@fHy7l=`x*V2n)73JuC>_T^l9DS`!LFVI0>(elg(x-aM zmbQ2B7;i1N5fjzGngy|;@($<+A_UAZIWLt1J=mS#nk;f+Mlz$}$j(zsGag%wHNruA ztxSl{c|0qK{u!OOULxe#OPQ`fVYO3a#(Y#aGrq?3xNpg)yrLphie|_*Zf(HmK}n}V z9-c)iAO>!nsdnxi*g^2jY+Vi7mOj`gdr#Q4$Fr^S&60}3(41O~q!_ZG!D7`8{ke6o zqd3YUGcXL9KGaM)^b|>?rpGtAf2JPy?7J=RrT)rFoK)lV*P3D2tFlr}Fv*a*BCWu2 zL=_VacJF2r*{%SXg|tDz6m`Q+s$H~|h|)O|8eQSh{H ztQML-L?l_$C(X>HD3DkU!)bJMA+qeNl^CnmTT$R3l(jyl*N=3iNo*XWtZGp$bV3}< zkM;_i>FBhI7s9SB6u7oVofsZ`x8_{dky}x2yHs9m*q7Cn*gFhthU|lap`^?wrkPMc z%EM;oP$wDk#mP!p?!pe?Y?KX#TPu%=J?tXc!!}3Vwd!Ln-tumJLRGo}#$QuCJ0$z2 zGHoyu1G7tK4q5A?aG2oRo0B-M7hTm}+tPTN-BTy;+-nult{Pm5!>mBdOemro$C{8m%#5?k#MXhGyVlldG{F>U z9JSA~N-Q2uw!^Tqq))b(Q!pYuQJ8E`2mt4}&|RSaXvFl!suX&O-x;}MI%==dBz)U7 zUQ{$&(KItSGr2JvUs6Iyw(j)gsRUhY&aF0ilts!$9}%%mE}+`#zESSzPAgnlXp zjlr_Eq#uT|jT29?F!Z7_>=0rlz5;vuwm+>iMUz!7Jj4ok3}rI3$mQnr1eR(s5Q1*+OZJEnD8OsAWM5jy_3s(Pt=3 zi&e|M6wNfPF)Q6QU3)!aA>Z|iufjxEA>sw~o|CY-hB>MOV}9w&~#J z0Z_$61o{-NUD>Qh0c1MTW{yX5U&^d3m;qasy0q?RMI_r=QB);)dWnT;9pSW32H^}< zxLQt^C6+970`y8Bj!jjGVqzBxn_Gm7$8!EtpFGlfvlOt-x9Fj0@K}5f`MGY>D!sjS zl_z&*�@hGpEOXNnk0aNLnV`G?hgY?(}F?7mqxs8Z0|TXPJS>ENUkDg^H+RE!R&k zVeKQ{&c`u$kvQ(EH*_(%l!Mh3@^p_mHZ5wiKI3eQ(0TI7I;SX6@_{(f#*542zzcA)pB2cJ_=iYMQk~RaPq#eu>Pk!sbY0wA!5BhIVYFQ&(6y ze4ca=#+=Qr#G(IkhsdoO$W=fiCp#?11UVp&=FFA}w0_pev7TU_b}28%8_29QINO0J z(^CDQ$8pKr@})zUXS=k9XW1rBFX@Rb4l&A;5Y|(HJmyiL%J6uXIjvrcURi2gVolOf zDsl|C%f_Wq=;c_enJ&>gt+WE3ZkuF;RmS(GUX?;K$x5{)^ zo=?+{a}-z?iCSmPB^>=|1(wQWabFJlNDg%Wq>lr}|A#pgM<3I$?Fql7_u0=IHMXM7 zU@fLe512Z;=%kTQYKEA%;gKCXqp~!L<4t&Ehx;?SCo;{e zA!{)xIdfB67D>z;6B7r~gY;}Ms2_=QY$I4p;sxeO0?`efKJAV!QRIoat)3rSNlDD? zB%QLXI9GQquSSK$gBiA;MB}Nb#z8)eVJKjK zmE)l&yYV^q;~k2lnczv9phsCp$7Kmy`V}+`dnpQOd(!}&$nk7-`IBhLO#t!qmN>fX_K6S4*a}yKs#E>hC*wztw zhfb>ZB}CHtFk|BIre3bJyFJI=q3GgfUr$70Z;u&eRd0N>V$&~X1_HC3V=B2sqR)XT z%*^zFXJyGM5bN2<`Hd0;_83s9w9s`h`Uzhsf;gLvL%{)AKZC4LSZGeBa+=3YDhegj zc73oarYezB+D?H>jpWI0RkFO@v3HGo&?ywiDim0V54{Eg$N7fI*)xCJVqXZ2wy6ov z6VzI7uhYlTthdq)|L=#>@ZvyuVc{?M;X^%VWoLEQX6K6q#ohX)`I?eK8$$b2`e)2-dlI+~|spq-RPx-A&zr4|Mlb25Vv-8%cotJvP`vSOz zvTIs0vh)0zr|G{l^j~}c%DMsEga7_Sc$L{@@RjS&JVpOKN&n4r_;1Da^lZ<1iCbO( zY5nBImX37!vun=O_fFS;@gXnEBPcJG^k;k4Nfp*tadiQxqX)rr~Rz`M~AD<&~ zh9&aolJERQI>&+R+%ED7!(W%O@n`#xN0d#4{_B+G|K`^jzq|m{ArF6cezlIj4Dmbb zk<@!<9H;7Z=dVvcFYWx)3)~x!L!@XyMs|KlW?6RrukQ6v!3_=ax=7_3i_5ghqbtWi zd8|_DJ-Sum?L3~Isd=v6u0D8mOkdZLu70lmuA@^1y2hYRCjXpPsp{)robGs=k<*A* z=$Ti!T9$5ksh;EK#tZf2wZw^^)R@H2jTh^6b;pbL96vYSwAa;LB$fEN@p+A|?syBI z%qIa_s}n=l{RR8^78G(&#ihT z`R}Fue`|Y@PXQ%?^r&s{u*= z2WbB_wyy#9mGM6)$^W1v|ME?v#LumUB>5kr{U^$ENWwF&+-hi&|DoD{-1arpzLE>K z8lL2Tc#`|bBzO6)K;q|Cqm$f6CmeC*R%4Ug$0oTKB)JzPxfdn5%j=aBKQ})8A!B&r zC*J@`{M>lub65BA2}fMH)r2JX2}$k~liaOWKpSsvH7Ut`QqujCliVlk7odwL>1kc& zd))RtZZ##zzYGM4pIhP6rH-FlO>>weKh9T6i@7+-y(GyTOft)8nE1I>qUMXOTa_jp zwRt+fzF@wi(i7vuDA>!WB0YOgj0f^^>V!F6hnO&TQ}Sx^gxRCNBP3?&nR}u?Ka1|h zoS`o3V$M`|bTMbCKXoy8=Xa6J8}56e|9yk*QZIU^q<4Uz@NAmB$@q5=17uxL6Z55B=e<7=IfKpzfUqhnPlDzvsmrH z|DLFQZzs8blVmn;pfwqi{Pade6)&y&{yu61&39>YUo{nG>nHxBN#>VhdDDjd%(K&l!#xjg%<6fjDz$`y$S3S_*l+f(a<_RiFv!Dn1w+5OEAlDxF2E^hn z?&H)2G z<64>Y5Ilo-9%C?8zgi$lgq~RcqgThF3uA+g5Oc)O7;zBG%7AQ<*p_lS%NXp_D|#Wf z%ZtY7TXvgxP+t6SHBGNK8vl>*X8v* zR=C&};A1-`#ny>GJ4cR165b$Qm_}_jHMLmuR>pl=*^;u z93ZtL73-uUslPgR$WYDWBUX0o1x@_|CF3RHTvE5A=z6Ng_%vrX#fx1~)~nm3aFb4M zia%2fT@T+{v0}ekyd-w7je}YIv0coOM&qPwyzSC1tB%H@%fk-FDrpl>RzBrU{VF)U z>3UdiQju+M&Zr&1Nx7N#hx|&aiDhDjjxsg*G3LXa<}ohZ2;xa^b2gWT#IbK-7N&sOSP;Wl^w5DOE6_e@uzsGbut0 zJ{}>`F%?c3Yt47IGS(@zllMI>g#TxSNX!wSxG$o+Pt4~kb&Bu;^Xbxz4NBbvv&4Iw z@Is@rWL&J2kM^SHWL#?WvkWLx1!CT4zV4H8Ilgc${*e9(`bQFVItGhB#3veN#wL?q ziKmPGmW2H<`Y#q4L+sAlw-<5rHaKLDos#$6Xkgg<#`?Da|7jZiCOnbfe_}2 z|HVqx3zsO>BwT8~l$LTH<lD56S)H0rGqDClYV` z*Z#d^F4>1XnjAuoBFB-(k$$p_tR`oXzag8*)5tb*6)E!oN&f}pZ^

^`y)P#NR#S zR`M}&2f3S+`GNR8l6R61klV;z>$q|*O2FvmylPGSCcoAw~_adTgl-bliuUVRpejD_sDO^La*_EHtEVR=APsray%I# zXORoZb>v3!F7j#eMeCF{wRni42nS$i?J2-BY)|1P~wd5x9HgYHV9QhIX zJ=qNtSdnKwIh;I>oI%bb7nA3Z*OGUVJIKA{d*nBy8xu+09>^i&M6#5eLw1nolGl*; zkdKpl$hXKZ$zRA^EF4I@1IQw>iaeQYC)bl($UDeK$!E#e$o=HM$*g`RzG379vXVT7 zTuNR{UQIqg{+WD>+)t+TH{tgp$C6XYTC$lum;5bx2f2%Uf&7GYA7#SNC5Mqgawd5O zc``4G8>e2Y9prXOv>A4?XKGs*d6JGq|RLf%2{B3~dsA>G(&m-5afhmq6ClgUNo z+2l3k9psbb3*={HCzi9CzEl)RgKgnXWShde-L4Km^PC1;Tf$(7`V z@@KO5P{u<}BFo6R z&Uyvo#dP3r=+XE#B&rm zg2W4XbiJ-77m~}#-;)0#50a|T+?P)dA*YcuNPLw;hyMriujD_;FUfzCy^4(g0pxMy zI&w34JNYX4E$JF(?(a*EAde?2$T+#2yp+6=+)2Jj9wc+doACRS8N+NhZELvVfdM){)D|bI2>n2gx1ezsQ56Y(z=_oKFrXk0WQ03&{@h z67mM}K5_@Smwb=>hRmK~;_F9_BZFiexqw_jZXmBA?;#&2_mFRqUy>QenfUsUW65H2 zCOMyMC)bl($UDeK$!EzA$*)Q8@g}|@WDz-?TtK#y7n66A50QJwx5zKajH%2IIhHIY z=aDVsx#SJxJ>)L(W%4WXCo*rEiKl>^M%Izb$aBam$p^_D>zI-?<04Rd&&36Z%FrvCj2~d2sx1~B^$|Baszn}`8c_Ue2e^&%qV6#kYmYWavs@2 zo=aXq-bX%8zD#~dD!&Q8J2{aoCFhVWuEIElRBj=K*l4p{akav*}lh2WFlV6dtaW4H>4{{)R0y%?h zBs<8B=8EMRFm__ z4)Q$mO7cN+2l+2@A9;w(C^g~sBS(>VPl`@=9l4l1hrEouiQG!=BHt!IBi&^tygagi zoJMw#8^|lkUF5gqsB#m|Ddd&pZRCUG+vMlukECb1xxYU-nXDpLkynymlUXy&eLcv& zEe3pEje3$%$JV>f4la6e%KRJS&Ooqu?az5Eg`m0Sict&2!tASifo=sjs-bOw` zK0)px|4ROY{Dl01{FYQTCcd6zK6x}bm>fYCkQ2$NWC>YDR*|*jNn|~_fLuhjldH+g z$*ag4$Xm&~$@|HN$;Zh*lh2UPkuQ_4k?)Wnk)M%YlRuFEAv0zgc^yR#B1e#u$mwJa zIg9)a*-D;Ho=sjvZX)j`w~^0~{~$jgzb1bnkBpdf4kag$co&tfUo*)Vxr98EypX(# zyq$cA{4@Ci`4;&Zd5H8xO?qChR7({K&~Y> zledr$kWZ3($k)kzhqF8RYro)#Q!j zZR9=V1LPy*6XY)PS@L=E74miRUGih{bMhOqll%|a`!^Mff03+LdRwD1#|n6ZXUTS(;nv-a)RS{RVO~?XMh7?>V}^ChV=$KAOK3;(sUkGwrkLVUK*~3t`uv97y{y z!d^;Eqq&^!m1KnW4di0lFC$mbex0y~QdiJ?qY&}kLf%RHN61~Y-%akJ{j0(pr9Pqg zAl-i;f1-URWF`6PBSbv?$N{t;EiA;jaGJ~LUO~>JeLcB|_O0Z3w7;C@E#$RAgnKXD zx08P(|3!XCeog*D_Ly(deKa|eoJ>YYyp=@fZ!x)=yo9`lyo20HK1aSmenI|7c7x1B zZh7PY@_4e0oJGzTj!|kE&1VZC?{mrXX@3RHSCZG!{!W_jB_9wXyg$)>w{WCV|DgFj zA;SNN+)w-OY5tM?h4z_E#(xf(Cxn}iW<33-!y8Wf>7x#>ijPb4GcJR#B(7p5t-g64HXOIlJC*}EArp8|AkCF&4k-i*iES+Lc~9u94E|FDopcqGEOccPZy3;>Oz_? zC9fo}C2u9~Bp(pszK4YvlXlboZ{!QKf0gDp$&ZD&?-IC+SQlbI4v~ zf6_-z6e67C$r{?%lD{Dv$WuwY^k2twE_oh#u@K?iAuPdsg7(|V-Q?fMm&t#T?~)&q z2gx5uPpb*HyAbW^Xd&`DkQ_;lB`1?pNxu;HRnr_L=L?bEHRN@|pi=kI{Xz0^atHY= zxrh7*`5L*8{G9w*h;UPu;Xl&RONjLMA${avax_^;P88z4AkAguY$3v3PHq&2mAaMg zcajf~50Tr+Ka+nWpC{iDBAgG&L$v>yOmBlb(w{*dErkEE_rYIN0Z}89QV-oMTA&a!E&J{mTNRoMKm!SYoc4yJe@p) z+)Q3g{*Jtr`~$g_e2jd8d`XD)n17OQk?)b;lRuI!m+_xQ=9B%&LF79M$@(J<<;TYtPe4W(K*~0#Nn)P$FFze@P!89~f zxlcb=3-+S?7m>duuO_c2^>eZCe<#iNkq?sF$nE4aOFl?G zLT)GjO#YpGf&7@aw2&GSwfbRm1HeBhpZ=?$aBf_ z$VV^zD)Kt=7V-}A59C(zG4cuW zDe@WedGaN4Klvs39eIevt8{gGQ^_OAqsbxUaPm0v1TrF=2z`_M4cS0;kSod6=p{@^B=(c>`5L$4kbsDQ^{gdKUa=*mDyqjPa)@% z%gI&b8ge~(6?q+b3wZ~rpGQZy+i8B9e3sPDr^Eeynm;AKApb+k7%S=PMfM?wk)z0I zq@S!6Vtr-~86)-c?yx_d<}=81$@9qT$lsB7koS-~$*0M`lP{3(k{^=ak%!2PY?Hoh za**&urG}DY$RctIIgP9%=aThg6L}iBlsu2TkkrrTBfiZv|DJq+e3X2g+(qstUnk!t zzahUTyFvGr{A7~-Ngp{*Sb}*xc>-BN){*-8fB37Xxrtmso=L7H&nK@TZy;|Y?;>}Q zPm%il0f^^CnqMW~BtIZOAv?*R$nLo&KRw8S*{U6Y?|iJ5s;r0O^t!dP(|H$xJeb^pS(f3FH)VI$1?F zkj>;GvXxvX3}at{{4IF}c{_PG`2hJ4`8V=;@*m`D`vAs7TA2`W)d;bkF-M5?oO)qj?9&Oc-qk9^y4gx0 z^w~ASfl6%=a@=eO8EZaIX;k^s7Sj zfA0#>&i4sX-wz0pZ}~|)sicR*Fs0d;)k{#q4Ap&1dZXhoqwfvCJ>%|P-MBYX|AjCZ5AyUf|<^6=1!JR^s z`_tsJLX`g=a<35e;1yEK8};E$F@x_4Q7=9u_X$xyJ|_f=1JUWj_xM8<_v`Tj#tuXCcFc8EQ=Qi$?Ci(DfNqI}5> zLe$?&$c;jj>t=FmD$FR)=Y=T0&xI(zOxQ`ejTWN3DugJXGleLhdxR*L*Muk!PdbQl z(Ca0Tzg`!Cye}4e$onoK@?)BENZ3KbkOZ36bW(G$U%A@9{KG79vdu zLi;ZhA`P`P&k-VS1f|{MLd4ZU^GYG)v!3P+Lda<|%~uN{uiI$8O9;6=MDt@p$nR;I zpA|xmuh9Ie5c2$x=6yoQRY`d^vEDnG%_>l4hnJ`H1ifmzp=ktiSD|9c_i zzmw*tg(!y)Y2GJ9d8icpllX)v7rmYhvwmMC%BP0zwL;X}4w_dAQE&BoCE@=jF_)kp zru!aY5bc|0z3z;1>@VxI@b43rAs(6wgec!RG|v-OAbn%nS1rc3zQB$)!?<ZJ7fb8a=uVH;3(}o-_G{9UE%mFTotBkJuS|Ekb@~3g z)8SXIPj@;>+=-W{J6(c~SE)Pg?H8&$Et6iWp5!DiS0B^XyvS*7zh*tzL4V9Q+0uH) zc(Q%cOUaX+ov$bVm796Vc(Qeu7mFu5nsq1nw*jk<{Une7M(tJMZL6z@+P^zns{Tl z!`6H_)?s12M_gN3A12VbZCff$lSx==UPi7RnwsY?Ux;_xFIbA!tFIg8&u?o!-3ZCp zELz&=G&Z!!JIT?+rKF6HU)wBdS<-BUh(1D%X7o^eLH!#~T0nQFe*^GW{Gl7uzhr;nCcmNh@4^57&EF{aNsd?U zvwo?(@Pkf&=(2VA$^Pn+{GqEptiP5df6^r%F5YvJ{MG&!f18s0&4U@Lfc>-baX)OF z`G~`OIDgM3`Rn*E{ys|bx8}e2`z6WWCI7`=A0*D1KG6rDqS!wxAEIwM{oMs0dA2W% zyS$eDai_m0V1KyqPD%2&2ma<9CcKm259*I9rrR8BZ8j#tWYMN)W!Va~#T z>u05}Jt@36!rK5(5+2kdJ3P@(<#wxm6re#!8m*rdp6IjA^c_HW!{AB6gIZ;WcUw|; zKOwwUD=_*K<4sB7<^Ma8U#MkvcuysTw+IbS%EbCv>D!SM-Y|q`r4MSI9o{=h;pHKK z!B$}OC&o9D!mDwlPx=&z*MtA^o^kxMebH82Vqsm+J&Zq@yIViY-_pbQ zJ6ycy9mb#ZmDbM+@5;mYv)sh5b$$0?{5gWN{rw64B-xgmN#Xq#iTl>d zB;2j=zE1MD_FSxS{bvasL+laadTFKP81X ztiq+&6eYZ3{I|lBb4J!ZuvYh9X~rnImY?M&=aQUq$*)BEP&g7^3I1E*4M_^G`f5C@ zBpm{OR(J!F!rNEv(rcd*UJ(DS@Cq58v>Ey3-;K2|5eR=0p8TJhulz!|aOQU}7SawN07+jN{)<1U2XfvDx3}U_|586w`rC(=S>lwR z(5lN~E{4A~Sc9s-^+NoY@I*`!rz1IP=XY3R7DxW9@I*K2;xFP-3l8J2E!N)NGG^&m zAAg0D3MNi2D4JYU=)?EE3!Hx^P8{#^O`1Gq;$-c&K4W#LBJ6TmF-jhW+4Vt^vqqFg z99iLp6hiVIL4jzqx+z*Fw{AqV8_Ag%XS=GdRZX8>5$K-Mr6Ga^`;y+ zCMD~~ly7|FLY;$rP9Mj>NA?@80Y{V>U%qiJ_$zk!YK*@gAGmc>JU8C&)T>Jy&(Lo2??!W=no*Ld8&#cdE8FV1ao!Q{q zx-PEb{aUUrogd#6A7tXyCN=1#RX4|9>Xy;)^r!A|Pk)*=E_b`<;a`6E&o9d7*{*i9 zKD;izzGZGp+Uh?aOdD`>$*>&*!YQLC>~)RKda?r{_l?JO!@4g z(4iM|-hFGExJ}qwo3Gwo7w@+^rPFo%EhUF=N80N3E$ia0AJe{TI&wsC=cj3dtG``S zG`HoXhSY7rhSu#REyk^PaD79lK@C5+_sdVh2sXnk~mU{Pu@U8KSx2E{!#^33D_0JjcU7entFXR8-bMxbGcB+E# z0Z+xQPPOyu()Z(Qw}ua>K+3T*uWRomnS&XLgQy_X;KTJ>~2A zl62Jhl!;>R2_<*D`E=eal}y_4-h!FK`W9i@F;}-P`%KN3AVB zu55jL@cxvPwe@S`7r^D7c&~c@w`<1rYUt6>tL0)yxcGb5vcefN=PTb4^GDWqZg&ls zzuNtEeQ{6MOAo5=8j9B-A4AKSlk}5xn{^@mSE!oKV{;`p%!$7kW|NbfKN+|>KPVx{ z-Mm+sdnNBzsF|IM7ldRK9Md`?ve9jtc$ zA+83h_+6zb;reavFxp?yP4PhdI+gm$_I;C!QwE?F?&v-+H#~WJrmmx%I*i`ofj_E) z^W)j!m*U55J=x70vJpyWu}goly@ zY4Ggr8b>kWNTf>nBwZ3;=fg*YOX3?l`|rFWo*F(XJm|-)1N*mLrDNTJRH}iGmENRd z9T6@J`@$d8OJ6i+o8;+QmGR2SE|E@Wv0LX$@{k$c_epo1mje%fbf z+!g5@P&}awwK`bSIY^bjv^##^AJ@jyTB0qftDicU*7(%dKKH%o(?*6(j zovCL^Ojk7=dhv@R(?471Ml2Kl{)xmnKKR9v5~muud+#pvaPH<^C<9%;P|b3g-;*EA znr`Jcqf34RErYg-{MNO&x8`n78L)j{Zn4y=q%hX20XZ{rr#3wp?HsJu#ZQXQt-k{G zC(x3q@0JieGj@)Ls}IsF34poVWsIFW|43av=s~S|uP^@RKbJy*F{(nUtLIp(qZ}BH z4b7v`ZZK)Iekrc>S1`Q0+`?X5t3-DcFWeo6KR$Wzns#ZYnE*&p6lLJvyM?==eE z(=NlG^y~1){XRUV56%mV?d@W_RsP78yBlV1=>>W9xK7)NKk0kq&rba5HUf$2mbyVM zXJl6)F&=sHKzUk@g#O~W=?F;!%*yRq*AEHt{0?!ac_t3P{hm%-ck|qUTzfon{?hAN z0RI`DxdDdkYexB)nLEz)p| z=dbYT^Grcz2Y9YQECW3oF(Vk{8RNs+jb{j!vxaz97D0dYTm<#F*(2}zeb$pP6dJeZ zU8MPMo)ZQu^>@!|EG+Hu9F6=w=lKCXpZDH|bdGX)Uq-SzuP+(@qOm@-Ug9=?)IJrxqRXFeuT7q>GrOJG`@0s z--X}~0B)tec6)C`d=;tQevnaRs`o@#R;7BMMCn(jdS68XYf`=UK;AP`z4DojNUHZU zAe!o3i}-3&z28BGb*Wxi3YeAZEgq)S>{RbBh-gl#SKg;TH`V(E0y`(6`dO zCqf`^r+IfFW$&bUC!jdqP4jL*0^dvXUIi(=pXNOqHF|G1@3j#5i`~30Bg~h&c^4wn zFL(1!LXuwT=7r9o{?W~QJSzM@yLtbDJp8MhcO_)@YB#T(Vt=ihx40(`reu0IBHC@4 z-bw`ar%dm=WAWCWOm8np>82d-^T#T6bB_0Ml>03?-j`5!Zq4z2h8S+k@vekeZ_n}m zfQoiUj<*dlZ0O}Z8bM#!%R30QK6j}1L$vuGL%p5w+1khZGbX&t`goCA)z-&*H==Ft z<9!A`JNkHkgCbtu$J-m(JiU+Ci(0p$kGB`fVPzlhosi(FKHgW5l{5NyKY~Ec?BjjB zJ5~bvcxNLIXZP{mi~4d-A8%jyT;0bz0THdi?TF#rKHf^S$>Qt1w;@{p_1@{Im?hVH zPed67VH$ur-u2#FPypfUy_jsP((An!Wui_z<$WJDYvxnl{y_bH?_$Kzu;2SUq%?oO zcRs|^xZnE{Vrbg$l~YyC`@J8dVlLS4m2bl=+@EnSf^O~MQW@TH$hKU(hth77i~r!F zT`n4Me}`OLgu-4f7nebdr_04~sb#ieB61rY4>QS!e z$;H{IJLk*A%aG>4i>pvDsdABtaMI*r4C+L>TpWdx=q48jQIR}y z@q5VFD;M{md1T1N@n{Q~a&a5(%94u>xacky17ZKRx$;FW<&m|YXL*i59V&7oN1ukZwUZ%xsMmy2gmsl`{ue#p=z7x$qEQsm-vBtz~~nYHM?yDf3K-+;NB4`NGm!A5z8WaA<)+SWv^y6O%4sc1Qo?a?7XOvdg0p}8VZ-PPf`Uh%<_g}7_x5HH2%O@Fn)wr$c^&vcXUo&ny z^GZ=}-q(4bE6)pQd*9%VuDmf4+nc=8mG^@L`xbA7XEDCbdsFh{#J~3)-kXv)Q(WKW zy(xK_;`$!%P3c`;gJOB#)pNI`*PSO{ne%?&>M2i=97xT(7=`Qo(A9Gf98t}W5K7Ma zY`{g1N|P)fu@l!1CoGS+4rU21Up#%~QfcC-eZ6Vf22xaJ46W4rkt_91Nco5t;Z>eU z(E+ib_99T*N~E(aET=oRL;}a7AaJ!Lsb8 z(q@XKM1Hzu*+-=>z;&8fXcze~ppN`#l`g}4npkL;dn}i1m42+2)A>-&uaHPDwSF6sz*3dWBs9eIvKIl||aM^ADVqO;E!Wd+zx<@AAc zGsZZg3`?*DmJf;2m2s>u?KX+B0@X8Pn6Hl{xbG13C>e#mOo>Q!Psupm=e+^<=6rxg zk}=KKe=Dq0TsbP|fW&!%Ws$9NUO|VFaiV3>UFFpJU{P#YpwYjKT9M(mEHYKjt7)(Z zSQcKDa{)T+jG$%VL7?cLGD4OGa`qg$r;M;=0qM>|@0U?(S){3){t`=>Ws$0K+K0oU z+_G@19Qj;Z#&pX91@gu)SX5XR$YE|u#w1_bE@Zs#A0EDK0yU(wQS!YO*XK zopubP8O@djq;s!S*M*jakxs;yCJ(vv)k&(QblwoT#(kM0H<8XVpZ7KNbvauxoM*KA z`aJ?`U3XpJizCt0#K&gK zqA#Y5BCai#MZU`UNqk&sSzr)PmoTofERIk)Q=x}vTy0tORyn0&agAk>r*a}h-A6HfOkKa3Y?lj3HX_};K z(st6OX=!PeX`3#zrIX2IX|r`^(uHkE+q4aK2}xSYVkwA#2)F?X_NAbpEQ;WYh)`A+ z6a*0!MFCO41yFEdQGVa=InTLsCoTHE{@?fWzwNo-bDr~@?K#hR&T?<=7y>NKHz~M7 zh5&6@4VzhTogqM5?qg41ZwSzqZ&iTsDMNs^e1+jJ%p6tRLo%CeM`a5hjf7biEy7PC`NbG>V{fL>d0I?LK3WEY`((sj zfVjzXz+3Q?n3NLQfuBdh%$lwKbtFH-3=VQ+{Z`t96=!jK(kgh#v=PhWl1RaG5%&US zIH3W&zlu!a+Ff?eGF^%g1?R`;EiknV^>id z-ZBI95YEa%@pM<$IyE|d4L=l&517jhe*Rw*Q_A~TlapTIisk8Oll zdLURZK9WC#x>j&aVU@iOhJxxy87Ih+N>2KgUH(fz!GcKHbqwisWx>KonKrX(Az82} zQuZA*J7`yO7LV9!0a?(knP%8(#aPf2DT{)s+OFibw%%4N#e&l`Q`9b>j-&M)kN)TkRL=%fH6p6OpnnAkBkzCH2M%l;2P4FEmpiQ2u=ee;Fye z5=_BBC3WLKp!_GKz8on#8`SFpmF!ULmelI)d{j?K`8X>?`MM;in1d!}f)%=yF(iZ^ zo`bC3i8$;XsK=LU^8W<#*oUaVU#-a+?eCFrry;d12VC1hS;YmY)k>?v21y30QOgKMfQt)F#fC=Bnwarfr0T%lJ2~QgWEcV4D z{LBzwmOf0v&kX?<`x7KQV+gR=*OBlGLx9D;iG*Jo0xULvioW1kLx9ERZ?YFWX9%#^ z&yn!FA)wFDvG>-vub|H+yU>z?`=n!=xWfBYO_*KIj{RLt{tC<(V;eZ1{lR1ai@k(| zKNeSzZn9${=Fpp-4M|A{LA8kHw*z?e;EmH8Unh$umps+4FOYeISKzT zgaWKUNqEN)&?yhI9@cCbT<8@3U1veS5VXjDQ{!%eG$$8P*ij!EVj0>;uyBpho97)yU5VZI??EFC)+ zgjz#DxAE7K3+fC3-Nw&o6x166#?mG(%c6#$`!O`zor^A-Jf8iSH(T4p$0^zcv%~CR z_T#eI`K3rZ_S?sRzQSYxwJ)G0J>C!?znQedF++g-R?h^X*$~k7Bnb&aK-(|nOx|J$ zX!|a5v>F21zL$hHLqOa2lhAGmX#0gEtTqI+{c;l47y{aU0^8nU2(TlQW`WRY2wE78 zv)#qun>>}mSR%r>25|*lv%?gVRa9PZTTT9{V5;CmWL0pk2v*Rr-2sX%zxaWXCqJVlSIK(3R(NSifQj=*k6D zsaFjFUHN`i{ZEE~uKXGG`p<@d^Tqg@6fCJBVEv65;0F!vpCI1JKcX@{(V*3M9gX2% z8p1o#1?+>j8}dJc_^~gussC)igJ#+CU0e&oJBENhSi@RbQO$v$>mIv}`PxFTq4{sH zRsq8S>+=^%I2f(enWCvhG^1`*dKyi2xe>@S1T^(cu2I58v^QxE}9T^`KWX9 zE$EGcNm1QJ=TQx7qhU6Y4OtY;{}q^ulg%ww!D5rabQ0n??-F^3pq}Yw)H`N4#*zSz zHp8KX*AR8{aQZR%AqsYZlv&9MZ%s7J+OW)Yw5S?PV+T0S)WaF<@J?kelPfsKoD!XQ2RYATTQgC0w#TBjM~glLrm?fg zbXs(}QkIC$WlJ>w%gjKSW&g~ljis8GR8U9CE7&uWDk!wd3br*;!Rl07 z;rm#j%cBkpoECIn0)%+O`wWAy2@~k&kFv{tZ~A74Byh~ww?U2s=O7|92{)Iwsu>?a z{^8c*G5j^{G4>J*q1DAFAu2C~UbOQ5j)}z1y9;J3kT(a?!y9e?u)(z1X#mrhI>$@4 zz4$UFI|({(&|XP)e(@_zb{hn5M{Q(L%oIdvf>D4?7Vy! z7b|Z7Eezy+XpYL8f0P~mxbqeh>_MTD;F{t!OmI3%v-0+`>6Y^VqQf^j$0B0pAX1lv zZz{POf$ByGJA6y=Venejw}Ux+s|p0GzleoH_;V_dSG{Hd0-slbLd&UaKXXr#;nzy3l0hgb z3w44RX5rVJE8!14fZLcy>b-vYTk&h4FfpvCj-jyTy%fRi8^{u=e`I)AeZ>Rf z8-~bw>x2{?Vv0dfg)R4Dn&3kWwL3&A%mwaYe#t7l*>>JxO*=t3wlxR=g}2%zpFpVW zJdW?}b|u?mm7Pkl4cL`zQn2h%SdQ>%b|o3}kl_i;@J`s|@Ox}0gFxt7+{T;+>FP09 zxUBe(K;U|Mw#d-c<$d>dhU^+6~|;SDMf zsm`!%H>yAtRQgubKE&$GKM%Kgyn#x2hUkw3_u}rn96_SbIG2(9Q4nUX#Y(ig@aB@) z=(lRxsKPIo@~uOwdOmuu@SCMu5eQb_!N9|%2N1}seuYwbqVx~~h1I7s=9$ua5GbjB zoWlEk>GKGbS3f~{{iSpaba7HO%~9b$RBn}J7o)C)1$OB?M2T%W4oT+4cr&Gz_G`*|KTJa2nE0kjI4QyoL3MuIOICN@}SMD>`b>T(f$;3+~>_%#f=!b02m zG+W#N%9yJ`(Zj8%ws;dLdB;I`R$d$I2FB1*Sf-+=6DR8rp?Jc&sQ59mUZGg8$9T5$ z?!-Ni_aof%@*FhM$*V&l`FY=i0tE98Vm>O!`&%8&&~MRI;k-6KU6s?}f{(|1X>=dn;NUprRG-r3m$A4`bGkXUwGPMwYo@JQop_YG@UmsD@Ug+J*#* zPO6}CSF3SWbaDk}qd5@f&ykUHJw{m3DbCMW-4kH714Vr$Uu1Q^Z6jjyL`oBNM+=L# zOr*RZ&%=PCe&-UfP48f(c1&6c(wKF;sfDS%q4*WH=1!MVT?l$0@2@BpOT{mMZlCOY z7f^c-{nw0hF{1FcXAm7>|0Wn>pa;%A7=pm-xuUXvAFSZ$Za6&*`X7Q7j6tK-)$kVx z(|#?e#8eFutbrAs)TCnrRtYQd`{4ZRVKEmluy8Ko7L5plYt@4mEU?QL(9?J!=&O)+ zrA}`}zl%^Y0s*UyIsGA+xCc2c{u#*DlApvVOpw(b$^|Ryy1yjDuMuS}Wrc2svb+Y; zGP@@*h|eiA!Ho;yX@O^cJ#LZUe#j!kX4Tz|uC?#ga%e`JeQ-L2yj;oQK`n>%AgAE8 zJRZ{WI17Y*Bz~Q<(szReOh(gr8JtfZ*FkXhgTeWCps)oDjF!ippecFKqvUZTa`-eH zFC~uxcmmcBnA1bS#8b#=1?6!U$alh7QOX7O8ceT}>Dxi~EizFikAeJsGA)H(DA|lf zMMX9%mw`r+EVI|z7`FjCz^`xCUB>C~IxUn}!D1gIlNQR2S|}tx52uCl87-6zHr}3v z^R@rmP&fNVv>&A|U|@9nUj$9HpB~lzeaK-i94}wfsDk#*LH8--q?&dacs@uzC8R=l z0$9O==`+E^TV$e;J_UyB6w}jaAZ@U1wUOzzVE$AzYQ>8ne*+9(fm^_s#=n5_GD0uF zE#w!78pqi5TNMW6^R;P>a%wUUX9HXt(g8Wv^t&LA`b#lzVLuYkmw zxU2&R(`3`J|$Q-%fw|&983Z;i3BZ4hO!s?s_a!`TO^#;cW(-f$LDNOn)_2SBsmc8U*!qe02+9UXWE0{#(P!|5}?F-BYMN*LBs zxJB$us+Vm=cn<~L6<+}90OHPqTk$Cb__h3-;f|;DVfroTgf)or8hQNuEMk5Fx8`L8 z+7Q$D3OtiAt4x4HD)z||c$EG#)jvRpBJNnYRRs_YO%N;57)BriD!=E39Pb9>sifZr z&)J~yZR9nNB0#g-_!vB20_6_HjqXaqzCQd zz+Qw=rSoyKo25#eD7EmKb*mFR-LMnRaa6ltaJVeJmSjcPS1r7v=pQd0a;0{%cjgX)JeT`pfF zaz_74Nahmn8FZe-b71iNlO9nk&V)_MR+ZU0_^R`W8p z?504GeG`jU4Z10iP+hNzzbUXwZ8mzAq7wFCKrK?O;m%^@uqogk2H}s0 zeF<(!x(Rkaf=ge4yt#0) z)tzYrx4P+TLB&V~m3Kw`90v9hma$yXd7nhznn3;9y)+0UzXZ7?}BeGz0rr+^0 zEeOnIrssfpAKdE3nTkKo9ka=_P-l8Q;{OZI>KQCYd)-z#|9cRA3&&qpQCkBnhhcyq?yl!JpzqPy+Lt4@gc>aO*s9&y7~X5wDPyRN z^z+cEt!iLDpbOI$?{QmOkDbRL|DV~#hrwobeT$8_R7!i^EA3KUcRd?i zY9F61;8J^Cwt&n11$bj66@2JR32)>K2@6tI?}laH8FkHRmVVCuQ?I*`McW zlIObp&=C7BPu9Tzf(IX5g};hZ(z#2Cx*T1=Bf|B{lHIkMhAfS68{7sZk-L@jZ$|if zxQ#QXAe&!kQQ+^iH!5rVLK%%Q|E7C`vcbPq8|`0%{~5Rw)P(jICCdmJS_!AEeNfA^ z1%y>3s(HcH#Qh))lE_cS+NGNK1_-Z_IFZZQDov~@#Qqzufj{zN&(cKxki#+(A7kg$ zXkrqC9=PPgw%)z&ISw2=ueZnB(s1&cC@4Yo3hA42p8;gnG% zSHR+(#j z_8_rsEn#A*>4S*kvo}@KpThHFIB>J`)`2^qzXSXYS9RR0i2MVb>NrLRtwCmXm3us! z!Hye`Mcp{K1&mn8j#C{*=8*MaGE0Xo15+a$F4bZC!4a_Z9X{!>lfiK!IoV-6FC5lM z7Ew3PS4nP1ruH3}ttrLJ5dA?oCB@Ic!?(4S6rY3V8MqTEMWzg@JDUqhPDgf1lEG4h z;glq&!ZVQpN^%`MX}D9^=a(Y`Tis~`j5Oba=mGMx-w(jUA3;D0O7o*g5m5JInL;G` zaWH%g?nDj+vINzA4q2{pKeP&YQL1-?0>&bGr~+Qe0I;LeTA!s?q3+Z4EAf|jYrJ;COGUh9rM1G+4L7ldXDM9_6ZK9sJXT;%+_mr6HC$c z+Md$&+K&}UAU(mMHPI>3i+MV$>vf{!TMc;zS|&K`a?RD!NG_}I1qdt9IKkl&t&V9t zPL-%y-`J{3>9~3#dUTAf&V3y&s9V2{={A^ekLBNNTFnJeNau-Qg~R20A|J9xD9YMe z9gXz}eK|OtA!meXzlVv*`D(C`6szMma}k;@@mx^r_$rCt@)Tr(eS3woo!F zCZ5*`aQ4BnIBeWsmy$&9}j1Tfd=6O<7IdO+=fYdjBu^WZrbuA6gj z;E0X(A~wAiQTXCQ09C}QaWPw~T6q=HT>+3gWw%1Os#46sp38KRu z9zW>3os!l|X-JmqXI@D-`{1JqWOf}$KSf6TgZUMoN1zglR|2= z=T-)uMBq7io`H+kJUiglJd3~_@;?X9XF=gN9@e~!z$#K-f#;8){2s2m z4J|zKXvJDY31D>K;#cFj)L+a-tHuVWfDET(atu7P;1-Z?A)CLA&9-~g5&gRfm}eHFKtV4Z*X60V>|7;JFq~sn;X$Jiq|es}M&a{QAFAuan_f52w_N z(x$a;qLp~Odff}pH{sCL>=s^_=TVbCuqG7zQ;2;6PIbwf@Vw3dJ8LdfvIb7| zMh`rE`9SpsAOBy(0DI#Fc%Fq@#oj1K<{V3^M+&j^48f@$88ki83JSkyfNOx8L0%`o z*#}od5!{5R6W~@HkHGctT+KiS0>6TXUm#hr5rG=m+$nI4TM;-L9{#;t<1hkWh3AWK z3lAU=rTn!rUd--&+#dh8R%QemC7bA24PIbh0 z;W^9z$NBgO7K?DIBQRvL9nk`66P)UZ)8W|-*IjKHJ@g-_Sy75&3F0tTSy60ohoQ2I zDFxN~OC$KI1e|L9Bk(-H03}vXg&g4)FyTVVV;kjQ_cT%h3B<(UR(4tMW(Im25k>Xj zGp7+{C-&l=ggL@xkF#eLmxZ0;isIgh<7`@j0AA$_uLKDre1hc^FAE4gG+PUh|8OU#M~g}D-Skw1wm`vUxDm@*Dyx zJKmpu2?!HxySF#@|Pe@!LZ z70g!rD|H@MHcck?@nIxlA(Y1|6TpzIMIUNqG?KVVOQOm3>80cu&k+ae)9g1*ydGnr*Yqj2WnTW!ZECSDUGm4T zTdOWn!$AbULB!{$VXn^dRl=5?00PC}XF73o4N({N$4MStDY2^I$w$!0d5TB%w%F+!VO-;ZSZ~73q1#F*FJzxJ{{3cm0E^uQlvJ3s1HWWmAkQAc)jeaL@trEYw~C z3kX>J#*M!42Mfwmj5{6MLoA1bp(1Qo-nD~(+qD;Wb@BUWY%4?vWY_0gr(1ipnhznk zHCtrD)fG_8Y~HABn2~)U=vTl&(1dH0H%XvFp648*N6R4zpSl8;Nq0n^h{tq?{CWtw zE@_pBH&mThNF20?URu`>Y*zl;Q}`pr>d6bDD&d_07eN2{FVbt^z(SY@2NovGxq=9x z8U*ScY)Urzs6-RJNpbfOZc^Sf;XybKjvmi&f`DrZ+w&rITQhr zyoH+g3R_V@P#1e{Ib0JQ)Q&)Vt22(kr!H)|J+3hrNh%A&t22%qk?|==v>guFs!VWm z)Z9j*my3xq$TmPm1or)reG>rn-!g&c-!uKUbHZMgbs`kN<<^P0@cNfbnnmBI0gxNv z9*EzzdI@}h3o1c9*tUB8Y5e{O0}KIr?VNa&1Re(x5$B49^C)5 zQq%}uOiPmxu%d^EXTjOldcwtuyrb^BZv0g9|MtEK~`G zN=yR38RsX_zz7apOh*SzwpLajqIZVMCPk>$*(j;=t#=q5!Vlnz@RPG@s##b)Y*ig1 z>3O&kYh+Srray*M-BsQ?GlWufvA+YdF+}|YbDgQOzm2wK82lz6;G-VzlbPWS;?Kdy zdUO_PDh~}}g;}itD$FQev`~Kqz6rx;rKJ~hOw=LIVx8_(Z|UiJ6{b2uXD5lF=7>5o;5O6 zcL+l*aOf~XPfjH2tS%7M&^%Q!rU=YFXzlg&mZMnsl7O$-TJ`?JV*NS#TE{w$Dh4LT zBYK<^Ir;u&t*JhvnD!%0ZqukHqnOS*f=R#laNr1fP`wawBt4*H$jQbhFVVzZ_JIDFU;{3m(31(yvVL)dOF#l)`^ptUpIj`1-|) zQN{R)9w%!}zJF8eBbfMFL~hgAO`~%9>Jd!(eTut}pa<1^7Dv)47#4&xS~$pTHK0d( zxrW@Jy|^E7<$CNO7-flpmFdfl8)waVDZYXfmfGp>Y7^< zBvKb^;%j0AK{BpAMBfZJmSnQAakT-!!!Hj#(tFlLPU&k%Igdi_;P`l>c+#xC(v{QJhR zL*~G-x>Qb9i&D-R5@2GU%un%=}>8pkdVSO`bRlbXe zz@V-`PWkC<`CgZp0YUcv{qngTLklS?mHPxB7N7*SFa%3HXw5oAKO4pUAyJDf#p-e- z7&iLxS_9X(W~%lpJ7Uz+7UqWDXX+;HB`~2LT^x2f7puczNv4LM8i&k) z+Ad>o8oXw3(a-0UIfLt15SSqcCUH3&(&Fx2rSNGXB?-*psKboK<_t1+GV&rY(Z3j3 zR0Y=LDE$DcJb36ShnHgzeL?7gqeOa?VLm}e;C{q46BG;=LUvZ6Z=H@HF!|9t4G}UZ zlhg@afpz{0Bz+ZNUPrxjud0)Aokg!diB!o#!AF_xsE0neQwOwo>6-(`vVDC3in?^! zOzmr%E;*fLr&!cwCb$2zILQX3vbYEw#7SV?IdIOwofnEQe=;Za@tB2bbw= zt(l~h@P_L_4Qj@qm*w%|l*H?H4a(BdOA+wm87eQ9&dc-)XGvZ(v%C!dt2(G2UDIpI zp`W$OgDZuj226pA!kLS4tPkU8x(4Bf;4Xl>7S3EW(=*`az%?2o@ZIZXq1w%thY0aL0->bk?H~j^#6+X<1iuvChqKZE!ts>)yvL2_a2zdgc5Q9lP+#5F;laA$q0Mzenc?99 zt8V-5o&9xvJNoz4ZQEWK8``pGVAt;W?xFtqL;bt@hx>->`uB|t5u(E*d$tVh?it#B zTL0#e;kwjd-_Uzn_Uy`}w-4;v*0W>Ja3&dR>|A8Z7}&MBu5WOl4yEEhOWcH#cW&N; z(sukGmD@M8vo7A5YENYrX{=*Y>e_d0-mzy(zrWDh9lJO8?Wh~x-iLUvsnLvXWZlT_ z-8(jK?;F@PT(@oW<_z;~sLw3OMC+psnTC22=Yu$Z*X~{Y^ZWZY4a{$-uU#;o(Y1)q ziK>GnSbW{izReKT|L@fpK6BVFiU0j>|G&-sC`z??=kUOAU3355fzADO_~Lvb6-ynh z)BpFI%F6s7Hy1iM(zk1K|1j2P9I~~WIhZk)GWfgC+U+!Gs{I-0B!Z5P+q`?{&fU9o zbY@Hc*1kPEMlvI34)za&2IBxl--6$xMgT`IBVG-SNwj zX2wy{d_9|{VshH{MWg)iu9Bsg=$%R$ayGW zyOWS|dc@7Eb@M~@D$k$(M|mR0Ng?OE0Tv%|rz2NimQPBS^Ff{$ac4wWS=4mCy1OX& zU)C3SM?%gMlJ{)p9YJ+xxXa-!iMWyDRiQ^lxS^Phtf%A8WGRaBx{$3~e)HL+S2(XK zdT6<(UVgS6S{>S8NBnV=RXpS%&UMS#l@YvX<+F%4y9F}KJ$3|#~x>kOe4)JpB^ z)qu+nRk;w(G`0uBV!m4xI^IS1xf5&Qt#hMeC5|I(ve)o3B>;cY*&X1IxV4Cw5XnvI zb~?A5Tk9^L=GIiXlWJItGb3dX?l`xm&fQq$&Q`T`^UK{ikjwP>s7n>RtZ%hfBxP@- zq0WK`*`05mYnL&T63L`yx;wiH5i=!)vvT>nweUpU!qL@4rsGimkaH`tM%UP^o6Z(@ zH&ivgqRgGGdahxVZTe##DqA)Iy;0;=%pxzl?<_mwmN@y4_*67$4%LY|*WgZ6ZL8Ag zKr<#fI~W7+3`JDqZl=;Vy90TgR2$JHmKtmL$uTIg+$}}>i)W|;wX)WYm-es1;76~P zEq8kX6Trznu5ufIb7+OMi1S0$7-VafyZPhYvBE-iFM=Rxk&8krM2t~2430);SDF0m zYUJ&lgg&yJYBaZSx@%X}juO{hC{iqcjRWIkJ1NztGixV}FH`k*Lwc0Cp>y0)=SdEU ziDeVY#=8?xmRO}kXo5Sn(nUj2<|10Ex^lNMRPH9`yA@S#=@K_lPhy!{5kgP6p-B_` z$xG3biKsiZ!Y!?GtLMANM;L6J;Vz_QK{`~Wf;`hzy|P(S~|dYXXe< z{E+kfeww`5&b4-A#x#^whq@LyH?!iLLS}}X2Vn~la_$aBX#YdbW#=Hna?CEboeTP8 zw<=^iYaqCp&LZ2binx`|3AG5+L>Pc_K#?Xm_mFo2c~x!BLoFsa8(4~oq-VDxR6~uFAsdMw{+_CsMk{FEb>8vtDSVrArrnEoB97fLA$b_;<7~kbeP8{e} zAUEh4ADUeV1A^2|OvG!j}aGl;}-25AmCh@&*9ylS4PM)%lM5spf2 z!KKNzTSq;>_iPY-=KSE)_T3X+H~Xuw-UmFDnOY3gU-g3uRD49wUqY1>SPSO zQpk{_*ZFwRR?Cu$M%8mBn#Br2G5^1+;eS%I@y_=xS}Uiv)}4l`z|NGx5S6>-Gu+b3 z>F$CmcWkX&9(BjIAZ|up&K&tO{2Gc)MXbUnH{7uEG>0Q}u^t%}lU@UR4iY9hs%L&^ zX1O~Tp2?Bbv;bA^xKKUWCc3kf*+;sN^TBhVHMK}J5jnmG1IZb0)5b#QYz&C-Tqx66 z*PdNFYQnzMQI)B8e&Zm40jfn`&F{w%U$8T>MNukV`>^_ zy4edMs(q@|eM-vJBJmi zyoOail}pdV3$?}bsZ=exM(dPM0%7NG$YYjsvBL#c6^s@vhUu{JvN**e)!B}c zoJmIUW}-I^WzM0kP0|z>d&}AoiLujG5#d zVxG!=9l(4w!#QBD2LAypOX;tbebKXudxG;{T<4C5wX-GSc`TV%eHKbxNO%gn$J9|vMpjA#zCMV=W}cpwTEqDQ4P*xRyKwWUSIFdn$D#<8_Zg} zp~YMdbH~yU2;~^qd$Vfvz`Lo@f7x1%ezpHdHF67$=6qc==fDw~v*9S3^NwiFKe1)Y z(VX-0ZPo7_YBL+uiq&?CIDu3^aI+w|+ELre-(;I`@ZFm5pfus`QB8o-V`2BAs>}@M zM`v(2%yk}sQhM#uIzGwyDRq1T4-iDhZ-I^<1L- zQ8hQ;FDli^&;ZwR4cC{lqos4y*S`x`jDjiFvGo9VdiA*xl zlZd6Q_Gl{86YtEdZ*NYwWfnv;P3`HFKDNq??91%f-M1yPbztjmi)U9BesQrUo=jvm zWlM}Dn=@VAX_T5uB-4pzFJ^U5qBYaomFn&3>1ITxr+q`BBh%8I>_oXqaIZ@=H{`N6 zb#%wqWSV2?Sf;DDvk5hZ9J-SpQ&)E;)!UScC)*j<(%swDYz>d7)2hu|w|Q*IM5?D7 z^|3nEH8-s9?ZFRN8qu+;iDWG0tEdrkXR0;R)Z3!u)P6$3inXQ}^fv3{sZ@JQvN_q% z=w;O2mFYzZCf|5+V^6vpweIN1^mMm(r4vc3kEidM%{aGyk2O57ZCC%62u`SnyfmiZ zmKgdYl}M-ASKevd&fQ!3Gb7pXaR0~%j_rrhEmn6b9q&kH`!&|woYdXgoIw9jS)miS?-7 zj(2x;CE_gPjA0x^?n2G>^efI(Z#)k5^immJUE7=JO=MaiA1|sWmTXUNw9XhB7}05| z^h#|~-6>T}Gn81BVrs4{sFVT>N>eOI$(&#g51e&GPAv@>Cz(`tOH1a6?BcPmj2axB z?P*nDG7)RusMNfvp+PVzxIl2B;3B~#f=jL4gZ;apkA1%8h+f1xRL+@hzb=~oZ%Vee zwxw|fp7ON7w6`VRvBpXzI#S7c|DfYAZ*GsZVl;pu(;92&|b#P z+t5N$aHF&8XgxEuFSBP?)=HVGirAA~t)3Nyw#7QVO1JmGHc6-Vz+TY2(z-Q8rMsij z-S{qdvZFtP4*_Qe26u4OLiDhzs;gu? zTf@7zj+}vKTB(uUgUlk8HFwmRO!vA(vZbSYy)tH$ir2=DH4u0vu_2yFG-D*9BX@7j zS{D%k>~cB=qqHWmG1C%j_mB48RMTjZBud3OL8Q8Slki}yw{*0}(^e*fM~x#(pd+RV z-oyg6+L-NNqix_E>L12)3~POJ8j7R@xu9OK!D@=Hi9zO6NQ%JipbEzQzGYq$)SW(<~CytAh*RiB%V8kWLbs+8Chh?w}6 zOe`MnO~&Ff+j#M9SW~QzLH6nP&ID8(GRMPctBb}Ew$Q@#1v9&S_s~dW&n}r**)>$J zW{g9lojp+dR5FhC#^UMrb=k?<7+$QdTD#QBDl3Gc{=O|<4&A9ZWY&$Da`Z%GvS>lp z-AN3sj##SAtVK8l>>2iQkzT|&!VKRFyGT{b#zLxQlI(zquu^9Zrw2B_C!?B4Lw&~X zp)Hvm{kyh}Y{!UVE91!+RF!dqn|Ef;7}%m>(k)3QSKaEH3Sslsvnx5>ENvUN+rfFk30sZnU7AHlDuqEy{2Av7aZ?be9U0bh7E$cJAJ*`PD z=48m}sdT+s-*ArMinrb}z6Q(FUbQSV^aUQrLeICz^EGk>pyFCSiSw23{#<26n}a9Z&Q10&?^K>gY(c#yZS$nafZA znoljTjSx(Zv>xr8a!1WV(qnDNPA~SM_b^MzUZ7VUpCQC_*xsV&GPD)5DQ$z<1o$ft!*!33m7J;%PP->;qCetOfLy0a3LTR5eE3)Q|H|RxByg@I5;`quS zq@3{Hl#OW$nu*n-Z&g3k zKiJ_o zwP~VhH0HD;wh?lBun8D%%vjzsK1@B8JTm7jk;$h%WYO zoV8rJ>%w*!-M+1M2h=wO;o}V~W#YX&O!2L;&Q260n^?b+5A4F}LBAS_YAeibMs}ci zyIM8LZSwaohEpbkcnpj7&RA+q?qEaj>wS?|6^Jwy z0bSj_nEWuoZ0V=P=-WBC10$PbUmcX7Xl~}Uq4A>qE#%RI>Zb(_YBx2s4@PHrNM^1r z(B55J`Y|fE3=QnXEfKjwYijRkKS8hZm}>%qPiqZE6;?Ugtb6*N zQfrO)j(!|0aC7HdM`ukw#o`GeJ07w6!eo#(`oSja{aSiMCehi0y?H9#o|PV!#8?`3 zG{ta6BddwH-l%zFQdTLnKUgS3o=d!9**)A!w6~fWpa*hEt<&oqW0lPEMzBdRF4!!1 z>l!UTdX#ntMD}rL53=9P}w= z)w83q{F0H$!As@qU3K)6OvJf^#GytnHXK=l%T@V8z5LP36t(|UTHlL30+s?8I!J+2 zum&?r>QU@J)@qhr6M2&stwYvC=xmc*PkZ{2Gu*lV>#^FKp|UiJdd~IQ#~GBZYfZrN za?fOzfM(;|wR=}5W*aX5+A+G+BFCQJrnC~Zim@YLqVO&cEzxPkv2`#CT##XrL7~O>4B_?T5o|wN`_&qvyCrKQbxEywqgC&1ygI7U%-wT$7fr4j z%%e`fN5w|1!Jz?axU%b9p6c@3hlk?3VdD0UuzWSy;Bd)wC%4?5QQ-X1EQ`8kEb0tX zs;8X;fTypTWuc%x)54M)1F~p{~WQZ=31&5Lo`<-wJPGJR4j9GqKE8I zxt3I}l(RibGnJ7kDLV!*x$2b~_qL|~zU@Fyvb(Jv$B|H_F6{DsTbOwE(L{T?9ee!~ z)GCa-Ts-H{t9!o|h!XHHio#YWKHjlU8WtVPk#;QMOeIv0`X6v)ZMBvgmTh{<_BQEO zy4RDc94t0RMdmnIOvl^0x+U!rt6%SIeGB32h}zUQ+^?47IPF!&Q;t(j-OPc4-@GK% z@c^C^Kq+!+8q$o0Am%s+ATys6lz z?lwoodQQ!qKe7j-eM5S!jwdkL^#l$!@vx>n4uN6?(-Xr2cl5Y!#01C3Sug|`quA-N z=?OW2Y{qI$udA}%BO3yLA^IEv2he!np)H59wyBO74wT4`<>g>zsDGQR3$mva>S!)k z+5L|%)L7wj2RZyxk4D&n?BlowQAu4*o+|ZQTLy;Jfd_3do5Xd91$#R%)W3y`?9D@{ z%&rWUI7f)XJl%tN#fmk%lR^jj&b(lSI#Z~WegdP;VRZRB_xPV{D2pn`0xE{GKnI~p zIdiF5T<}DU_G)w=MWv4h@O&||bw^+JDW2$A?!l*7J3>P{o7JIXM~@sjVmYSI-I~+T z1*33WcE*}g-u4O&63d)Ut;c9He4Lwf&#rIBI5g!bjloc*8q+E$bBiaTYB`zJldM{E zDepa#fxT-Jdk69OHX>%~#Im=y15aUj~EFC#7-? z^;vI2)*H=w7i7H)vtArDd53Gc*d_Sw(>#b0JL_ix&hZGd;MgB3A<#${W?AJeXl+AiS2UV|_V}^G!2+($9zA@mQ|)%I+td6YsL4q|7!Z z(pkmisK%aE-e}+;!$?ZtFg|0pT3q_;N#0vMWFKeaU50mgoQ z`^v@QcRkiSJY(yYXUedkFd=&8F%RW(pG7PAL}H1!7C0~Me?59sa%z& z>#>Oe<2%#m!!dLXyPQuCvG>LUL{DPb9Sb{3Jt_mUGD{7M)YPxm7(OBMt&q-G*G8FG zQhIQrPg8oc-n99b5s8@^dUEpG5k10yz$XU#{vk)fV2^8m)TPRgkTAfduSf6!G#r3guc9M+N>q%bqimaI+ zOLa)5t+zhROyD6E&v&q&(I)_yFU`qKLKa~OdAggxDVa{IpYA5`RLPuBz_KR$c`T(D zNph@@#kI$fJ;2A&jYrKM;rreqF&h(^NY!RrMxCc#YF6svYcm~c!GRM?v_1-KZjF4lf7Nad~t5`nE;>+S|XS zKI>J-qd8l?#0IDmw|sI=e3WHB^iVAlJ$a*FGl^KdO&w?Oc~(kq^L*yJK^=>jmxKH# z??e4N@i(YPn=!G^hAC;rR>ZeQG1Dmzc(MjX^|-vCmFz}+cy6E+8XINqJx49{D44jM z5$m3c%K^Te-|OvNTz6PpcUW9^SX_5lJp0%*nTp|gr|J|woXb6SiZ!X1xxBvfq-G*; zLZW94RVf&0)64!LuHGx6DOGD)pY0M==H2 zNy@XGoTn0M|EXSf@hdp@OId;Y-Y-!-523?YjmkNvuSUi3MUxg7N%IU#tvNb(?;04{ zJ){izE`zFcvnYG!x&%7(-KsAntc z@B>SYquFxbBdNh5yu>s#GJq3sa}w@#v0qBQha`BFMz%-l;K962gC`o8In+F(Q~@*a zCQj8p!K(RHWzT)ksON$z(#V`6LRl1_-It9+J6`1A(?aB{Z5(&7X4odxj#|Gfz>___ zlkrc!Ff=eR=pCe2N

sz0?Nf#4*fnJi|THQ;6)!&{G3*0_8tpW3v-@a)uH%!-|E8 zP2Dmugk_U@CSxiT>%p360}d~8ER*+e$aH}^d$f4q>y==lIGpin%Hteka#qV7zHOsk-o<+hcs`#Ssou8ZdmDT&%p^0tp*sr4 z&agK;b_Qs9siO(K!rjIr3-z@K&amnYPV|^81j)kl1CucoNo_oPF-$P<`KRaV{L$l3 zvfv}qQE&8k8ztS}NcThLfkMc%6G2>1` ztxEmpvnE4UmIKio`gs;CyRpFQpg70(s$gWNAHK>v%BYK)%6waCHO};+js1y(0mGEt zPA|;vetaimP!GeJ-TdkIN_fU%G~4jt>AaNAH#+3uq_Tke30-nS?z^-c9DIGiOnqi& zyG?2S?p+-GUTd2=VqI%sv=excH_GZ#bS7<59gyICFwPy>>5%G>eR{&_qK_{otKOCI zh1XBGKE=?+fhT%YAI$LhM~^?RaoO_--}1OY8HBXQwAgCx>W##gE{*V$9kmS+ezc>0 zNpxXk&QL!NDTe!xiOk=*d2r7PeChz_;`8yX0}w{G@7cKtxD~I5j?BjwKUU!7>n$XJ zbL-&VMe~OT=Wl6f1f_3i^Y#_^cEa8z^LN&A0XJ{U@Zh|ygOT~$BJ;bWk@@)c!ivqP z!2GQ{apH>SJM;BUW<@VMcq=;ijY7Ir(XOYMzzjMKWKS<^=Y9e3ua?0VW^cdZ{hB z#ycNt$6(xG>3yolyFP~b*{twJWxz*bT)Jz`QP0w8lJz3cx24FM0IP@33Y0b4I@FJO zNxgyS6_#_btDgL|<9J%lJia${vI`ZT;WfiJ9*g6gp+&FQtu}PK@972B0qTz#ymsKx zKog&JnX!x3Jtxy$G_Yd_ zkCsPulJ_on)c-Cx)`H&Ko0NuG44QhI3gEfR8d=#Y-5+)CEn6~^N|u60t`RZ)nRkhF zOH7Iuyz9+#G_Nb=#f0qk%xaCtmqq5#vc!gVMiM(W^>5jNztBjV?+7VlW4;e`%)6T& zehh`5<9Y`d{&4u5;=-bw&wcTeQ;atk!;?$^_#j-Yxa57o3!L`{@H+y2UVfH}pU*NE zKTp+MoOc2F{B(Yb*W9olX?q^3uE|6 z%Q=Pt$j@CN-wOiow>K9&^kA_S3&#yISn1>CC$VD1linA)zhG^pv*J~Kbi$*Mk-wkVe@dQ^O^iRj*~c$YS#}+~?vnYPwKx>*vO?p= zbmlt+d8NT}d%Qgne>XbWo?=(nmG-p247-*e2OD+yNkQvR@A#t~etgJxIr1?~L*h?L z`Y#6`8{(IKvR5$ch0nqFhjQc9FDiLF4!%W{8_(bR(LZLWnL-{fJr2G?l*^B=68SC% zAJNN=&%>91E!8T@GoU`QmrdY+JC{E<py-}{P@~gv~J4!L$&XF)Rr4-}o zatU)@pf+4BVcO_Y=-Ukln~P<91CIIAMwg=0Z%LT8xD@}MkTC6SDfH*p5~htUg}%Hg zVd{4&K3rLV%$VP+Dm)3l2d~4ljiu=C84~VM;Y!Qcv}%OMv47Nt6~`adBUbem*}i&j z-1&C1>Y0TO=e|6kX==?`iydxXEl%y#AGWCz@X-&Y<={xIzm9T_wgM5EM}&gVItCJ2mjf+&JriixYoNgK`fK%pRXYDbOn(wJut?G^qdp)# zkXDE|nYhHVs)(3F=Lnsnit)z@vVIJ=3ib+~B-kgoTX3)7dj&rz_+i1%2;L|7bHSGd zUl)8+kOP3_hXe}+O9dwhP7|yaoGVx_*eJ-)^)kOE!8XAz!L%Sh)l0rp1^L-thIa@K z3GNf*Cx02wU$i1#BKTp!s{{`UeoF8r!P^ACEXbdMVm^lj9~S(c;1hyB5&VT9=R2nR zo#3m2e-(UN5Z`4{eEEVUf)fR&3CD0#w+OyRa7ge>!2^O9 z30^LErQkuqPYd26c!%Jfg7*qOEckuFCk1~d_`Kjtg0BkxP4J(BE|ztaXQ5!3;1t0s z!8w9;f{lVJ1e*od2qpzL3Z5#sO>mds9>H@2-zRv9;70^MA$UmeGlHKN{IcLT1n(F8 zj^Gaje=PV5!CwphLGU%fHwA4ND#|BMaID}2!Ks4Pg7XBUf=dNg3APG$3HAz}B)D1d zG{Msa_X(aWc%k5Bf>#KBQt(rPHw)e__%*?M1RoOop5PA!pB8*h@I}E_1pg}d55XXo z_mopuuvBoeU_@}XV6EUH!R3N+!PSCm1vdz01h)&GE_jyU`vfl)yi)L5!OsfbF8Fo9 z`vo5nd{Xck!QTkJBKUVf8`~7NyFjo^uu^cAV6EU{!Bv9og8b1B=5wOp7Qvl@dj-!G zyjbufg4YOsTJUp%UlF`V@LPgE5d5j&^Mbz@d|mJ#f+1|TSiiA?lLV^-=L#+mTrQXp z>=rypaF^hS;8}tP1TPf4RPdvMpAfuO@CLzK1n&@hM)044pTt6g_5YIKeS(h(J|p;h z!8Zl-v58>1NrJNl8wC@BX~7}E^8}v}{3#aM%;$H4ZwXGsHj?ye!4AQb1$PNvBKUE^ zF9;qMd|dE(!Pf+XSXeRt@q#siiv`;RHwvC6c(&lBf;S0%MezHAzYu&yklR+4H%@Sd z-~z#B!Ct|wf@cU`EO@oxErJgV{!sAuf^Q2JVN=6$rwP^xt`b};xJhtW@B+ar1wSMB zHNkHSz99G~!F(Jpu)HaP^8}X*b_$*%xLfdm;70^MCHN)52L*p5_#45$3Fcu<&2lFT z&J{dPutV@90 zy9IwD_-ny`2u{W^1k0%rTq$^(;2DC41P=>7BltVP+A^I_TrervCwPY7g@OkKZxy^x z@CSl_6m)P5!upj8RtYW^Y!N(3@Uw#V2tFqGtl-;%`PjHH-zveVU|cXQ*e|$O@FKxa z2;MAsm*69UKNtL?;6DY&;#h{|Mg$uKn*{k2dyL;AxJU3p!H)~xB=~i~9|=A$_@-cZ zqRy{UaK7M5!EV7*1y2_|U+`msHwb=3@L|Cp3%)4$h9LK#Y)6IQv4U-ay@ERh_X~bV z@H)Xe1n(F8q2LRGe-R8}1IqFy3eFK+D!5wkM8O?`?-jgU@Q~o`g7*nNA^0o7*9A+a z=yInDE)r}JTrap?@Jzu=1V1VGIl*rVJ}UT2!B+)soE5O0Qw8S=_6c4ic&p&|1%Dy< ziXac=na?=Et%7F=UMzUE;4Okb7JNbQZNVb^A|LacCRiu9N|3*5$oNfy!-5wGUMYBo z;5~v*3I0}a3XY+e&pg3S!BYg!61+(8Wx=-u%ckq}b%M(UHwtbQ+%I^I;AaIN6ntFp zCBZiZ!x5eTY{7+s9fBtdo+)^t;4OmB2>xBLs7mKIS1>BrEVx>*M{u3s$$|rdXA7Pu zc#+`cg4YOsPVkF@cM9Gk_>kb^g1-`cN$^#{w*`x5==zrnP7$mUoG*C1U_!7%aD!mK z;E>?Cf|m+jBlrcudj)?f_=?~=f@5dudL1LUNU%w;S8$WyZozW|FA=;-@Y8~~3qC0L zBf;Ma{!#FCK|YM5J{JjA2p%K2STG@&66_P)E%;u+|3}$>z(-O2Vc+m~$n?-=Ft+o_t`xbFOpdcYdeLIcH{PX8SaZ*((sQ7jG43iBE`Y#COGy#m~gA z#69AE@u2vdct%Wa6wAM|SY50wHV~VM8Dh40iP&8nDh?ONh}Vl##o6LK@ey%__^SA( z_@4Nccu@RRJSp-gF4;bn#p+@mvALKlb`b}N!^AP-Wbsb%0dcXoQd}>-BYr0C6%UJl zi1AHgex{1G#AafS*jcEZkWfEM6s! z6eoz&#Cyd1#rfhR;uGQu@p*BL_^SA(_^$Y|xLw>U9v1%)vHuH-e^=p;#eL#Q@gK2rOY8@~gCw*p5_a2) z?G@ic;XdL3>BAHrDUK&$XA+5W+#%jCeZIm=#1$m+dscjf#Qqx<|B3X^#XXAOulVEA z{}BIHd}^zhoq8n7*H~;#;+W_`BHupZ0L2eec%(Rwoh{Bh}ji1@nG+rI*d{Hu|$UsDWAZ>n%h@nZ2(u^S0L`jD_QRQfQn zP#iDbNFx2+3eOVfOJAz+a`7eUn-zXf{6zY0g})OIOaDXRGh%#3EZl)L%dJ=gW^KzPl>C=cf=pWf5jGUV*Xqtb``G_ zr-%#1HR5X|&aFRE_#5#jv6Mu4PKu|c+nF)l5i66hQ=LS+Hk95}#ErzBoow+^66yOX zJW#xv#QxVPe64sRiS&0XJWHG}eW}9B#g|Cf*`V-7@qOu^D*T1Ghs5!DSo}kbkHqv; zv9_2Y_7E=@M~RcfY2tiwsraJ!y7-~EL;OMfhs0VcJsR_)kr)y4#NOf%ag2DQ_#lZj z=F;UC0<(oZP-r}&TbKvvApkl0kr7V&hGSI_;#5#mI# zM0`M8EIuo)CzEkMp2FKn_`O5iCH;{2r&s}Lym^tt|Egk0dK1#ItQ>{$_?4HgtJq8W z6$)P^4kxkS^@^V={dVyl#osSJDg9}2we(lStv zA0+JkEheLE3|AJzB#ze>WFpF;a90v`dy4&}4->~ppCH~SeHv+7)*OYGD1NE9Li##! zv-J1GEz-XxD_Pb7g^wxzlz2vZg|;z2T`@pnzq%yK6%q5q-r^8(j5tkvP+TUi65kL% z5`Pp=iOh@t17b+b5j&E&rgNFXSCOdS0&%qTB84Z5Q>5Re@J#W3>5qvoiW?NaQQRhO z7r!F$f4{;9#3R!GQ22~^R=WSQ8@0Ev1jQ2co5 zMdD40pRV`^rOy|aDE>+DRq1bt?@Qk*?vwtL_?z^TqTMc5PDe~9;a^Z}B|THTSiDs1 zCiW5siC2mv#B0O};tk@hWXQ7aS9q?tSo%xidJ@OL+lqf*{8aox+(U-Y-Xzi=m;Q%% zR*b&{@#v4qVyak!3|Uqk68pE79ueCqzN6y%OCKx_l|D-0LUAGqyEiL-y7YU*`HFu; zd{+94;w$3o;`=1*Z6)F7H`4crKZ%FLW8x|CUlRK#w2$qdN}@i}#ad!ru_cN05fb@z zmflUgOdKTsPaGkRBeDNP68le+K0|y!oF^_8pAc7)*nbs?{a=^Fvd? z(tC@;rH>YGkUoV(d1pw!S6ra@N5$u)uM%Gs-w?Nw7>5swaUEje6tSil6+4JS#mV9{ z@lo+STSE?S+iKkC^bVW*;4ovefJI}~m$=8EmaE@F4Fzc^SNCXN)xldwBUyhr+d;sSAz zxJ+Cjt`c7s-w-#6ABo$%UpM7=a8Q7^5LjL zR{Rn1g!rduOrh1RuY3^ZLzV~T#Smj zVh6E{IDl+ySyz(q<67z0i#Ln6h9HV?5FTR@k$c*CyNQFa$bK<5(8qI*g$L| z=7~5Qz5OmHaou;QI6}NeoGRWfJ}Ax?SBTGwuZwSqpNU_JrDRiFUlacl&x(#O7GF`U zCe{@Bj0X2_BzpIwBOFz@z3APK4*d#+uM$U!V?^(MbELaf;rqq8qIX|8;-6Od4RMp` z-A9i2Eed}wekJ}U9v4rG|A>6{h2=>S17eyO6l;rFVq4L>PaOOAQuuOlsCcb-y?D1c zOPniu_l3ibcV9TTRQfaG^Wr_Jw=_Y0zTe>cKcDqJ9r z5~ql_iFb)J#d+dG;`8E5;w$3o;@hHkUpMmomSGG&-hJHQVTFGcPl{#YSux&@?H3Zg z`?s-wYlS0XM=@W#TpTK1BVH?(h=tibCJUB#r`C&e-9R~7Ke+I#GAzX zNXN1s6dw{F6_<%C#5cva#gD{o;+Nt#;;-T{@wE7ln1YGeyKXDi7aNOh#Y@C~;y`hz zI83}roGRWU-X}gQz9_B}H;CT-=BSS^72YTQB=VtE`kNqD5o?H2De;5A{&xq+R_Q!RA>S7(S zzSvA`C1#0j#ew1#;xKWfc&&K7SS;QuP8aVH9}wq>&x$XK>%Ch=Wyi}55z6vKJh2n330W!PJCbdSllCiFP4fYMYm$CJSk#bv7y*P%n&<>UBt`9q2fgGMzKV^ zOMF;dEWRbaBW@RWh*cm@9S{dy56)C~=%PL7Xkl z5g!&8i)+O7;zn_^__erO+%FywPmBMEX*l6x`KpPv#d>14c#+sg>@Qv;UMt=vP7`N} zv&Cn`=f#cUX7O{;d!7S+dCzlzN2H$><5OdPR}!m;Au%joB(@j3h}}i+xewSMuJBFb zRB@&_TbwUGEWRYJ72gv-5_gH;ilyR7@h|bLSOs$h+oOgU78{5ciS5NMVt4UsakzM+ zI7Pf)oGU&pJ|}Jvz2{Eg$GZxDDDD@%=TH!TRN+!Fp>oXsB(auQS8Odt#EV4lxfR$O ztnd(VoH#)&5$_To78i?8icgChMen&6*#A)Bt>S+1fOu3a6%(-5WP2ouAu%lGlDK}{ zPV}CiLAa~JeMIkh8tB(4JW(tbZxyGD_lOUO^Tfx*W#UTl1<`vB2l>3O@YmvQu~a-M z`qSY*uD1rns$x*|p4UNqLxo$55wV-tOB^6xE)Ew*i^bxt;&kyIahbS6d_i0-zAC;U zzAt_(?iRljPl{#YSuws!tlSmFN@8=dwU{klBz6|NiTyCyT}69pZHH zQSotch3Gw(1bb^0epTEgzANq)zY`CLhsD3dvtk9DIVtQPR=Ba)T+9@+ z#XPaI*i-bLtAd@u3J(z{i^bv{;&gGA_<*=bTq3R!z2~rCf1|>i#Vz8e;(qaf_^WtK zw5!L;?TD#jy4YHbh!=_N#V%rZae#QaI8q!VUN24(XNdQTbHoMWOX6Dbb@46neeq-Q zOYs}=NAaNen|NHTh_R0SrIJ`(42j-zWQcE}a8%3{FBLn9eZ>LdB=IKEd)^H8rYSsA zoGm^hJ}<5lH;9|Wcf~E@r{b^TF)<++D_@cr5Yxn_VoNb9=8ApD`uJW=yi&YcoFv{P z-X=~H?-L&spA?@KUliAfTgA`Buf^TsPvRl*ckzUnTr=ixs#r~|DYg{bh`C}rv9s7s zyjt|0uR}c)Dm-4iS-eGjK%6H&CN2{Y2~nBEan#dNWm z*haJ6JXtIj=ZXu(CE`-?1#z|bw)npIiTJtbJx7TA4k`S* zctT9B6)SJ5SVOEOHV~VLUB#ZF_q<_a++WNvc%3*=EEaDS?-pl?%fuDp3*u_=bdZh~J9)#Y5sz@r3xN_^-${2HUHKSW9dmHW4$$Y_YxA zQM_CnDvl7n=RDaT6rL!~6laU`#fQaZ;tKIaagDe|{8ao(+$A0mz2`=ef2qPJ#lJ-> z94mhnv4$8H8;GsNh?p<-5C@4@iW9{f#o6K<@nLbXxI%nZTrI8>w~C*MUyHlNpTtAr z@8Sv3#azgCP7$k!HN^U2W3iR!JqL^Zx+vUT>?aNsaXH?Ki|RdRw%%`+i1i(HTqA8l z;#yM%iEA3UB+fTVtyzlF`ku>@NXvB6!#gE zEi7vh*%}`t^2gUd9+O14;)PSibTLfAp9W$R5hgu7Lqt)%uvZSGZ>MlKv6t9S94Hou zqr^gSyy%q+_HI?UM7&G%%7^+{z%b~Q6I`P3N)q+YF|SX~T>VX=YOL~J2?-_xV~-uLuiuJm?d zH?f!4PaG&-A$s5AWB&q$M~Q{vc(GXYzSl?k5{2&)XNt4MMdA{1skmHRDZU`C7T1ZJ z#rMRI#BJhsafi51{7F0{9u>>PzeS7Ro1+}w{Q{tOzW|sly}B3@!(s!miP%ES72An< zVrQ|RI8eMoyhH;5a>&Ek9Fc5#Qe zQ`{>aA~Aj)6-&jFq7{$$x~Ok4NlX?~MelwEr1S1q07KHf_tzoZLg5TCD&~pad+d?ZaS`-ua^D@5--dGM=1VedW)go_lOEEbEmiY20Ve+ANe_g8?krOy!;h)c;9mbF}5 zDZU_X5I2gO#rMSR;tp}AxL4dK{v?))C&e=HZ_&b9f&L_jsU+s@bg{bV-LC=NyI%ur zAU#8jin*fq-aVx2rf@H@pEyt~An|{c=)Hdr>z45hgGHo+{x24j$(WzT5)$i~yTq9! z)-~RH`oK91V?JLXE+VncSt2eaF@G-?SCSZSUl3Q57(dpD8%P|N8^z6JeLS}(end9J z@gi;~aeVF&carEId&PYu>i;M45Q%y_D!$Bi!nSvx4eFx`b=1dx-hY95NQ1`me@vph zr6kIG8`7|x-uLAw-wXPFI6VLzjI>o!!XM4&HD&@^FHcfr_%2w zQ6CAMHxTd5%cz&I!VO5&kJajiDc4ONJ_4LPDaJyx#UD+#TJhIdtX3oN%h|0cw2HlR z*?Tc`d0~L}Yr^~imhx)s2d2(b%KhG0OgAr|o`7Eoz7dY#S8B@d;Jrz@e9Cjb8C_l- z$zS5;2Y<{=J{ZgRH6`;}>kF-WFQ>jxjJ=QgLe+c2bongLdp~vghzs6QeW4-Ge9YQ^ zWi9{a>T~JKzr*@`)x6ExQzuPeBegp3&DLJTDE^pl?DxxB#kPl!7%^$|O|eRjDdQ)M zEFT;`Y54VH@OyUU_WwVX@nf$ajh^9IM{luOjht}Zb@-*l@_St~Y4~+W)S-XxR>LPx zo-}p@eoXTQbh!U_e>IT|UD)DzBL8@tmj6Td_5SMOlj-7P!T%#25-_{VZGZ%kwV`FH09_A+pQmLlH#nSA-4 z^z!A+D`&4d5;Gm^Z_x$z!kCjg8)Hhx;DQV6^@Bayp?~;_;XiwPzdHW?H*SoAy?zLr zKjYtX7uYL=y)Y8d9;W60?7b&@rpv8^y#|Okf5zVC3+&B=y>3WEd$@G^pS^Eo&+NYw z_U1C7{t)f`?Yh9;cGz3gDrPT?6wH_PclZK(V^P>aX3#{uvG>;n>E0S_StIKrf&NUo zKe181-3nnLi~_J6SbqGMuZs#X`_M#PER0riLw_c&0@9VYH?y|Sy9Pyj4e{TUqt*rX zK8C$A^i}g`?A5ryUKj^p9x|Z4#`tgSwZ6dK+qdJpM0RBT8GFqyuvdTqbq>iqj+fn|-3#J2fKd;Fh&LAsoeV!s{1H2gE^23+9ZT}a2V()=-B{`G}czWz$# zUl>N{M@#%S{uLk{=C&g4!@mt%aL;mV)B9w;{3FX{W1U30eK67ndVBn*y;S^Xo@TDZ zrnTcUyxYMTLD+0ox*%O@GoMvdE(4PeOR=J{ttPY%>#t2tMs{vSW^QJiFn%m7qx@%f zc9dFHZZwyP3*0-p^vd`7j3wsXx+~ubZ#(Q}ZYyh$TGZ9r zWYz0bn7Tf$V93~n{CaEV7p4~0ymnF7k%hsryrwW6`6HeS+Iasv2cxO@Sn<&G6YhT9t>DSI!osd5}-}mD4 zYvvzHv}WM{h{Edmm5QgAC2aoT+8PCq7K}vMp1QW?nuUm)j{o-Rj5nL-|8mgURJQ)^ z!dm%};>XIWZ%!-Ci_a^)vt;w(_{xF&4uvIU;mry8n-ANO_lI{ITe@cBu|QzO@T+&l zHR@DYqi}2SH7D$}twnK-?!(sf`1^{Ue|hV)Sp`$guYvGJvT!UeGN zbfJH2{90NVJv@I`TzE)frNS-61t;vvTZ-bsTZ&(Nx!}a~xKE~SDe7BbwH~-Vv-q*X z2`9Q#u3k8Xk@1&$t~)fnf>?iNl%xhZjKapDlLeQ6qUWX@mOLYxU)l{Q}}7|$P;$ePm3Nu zNUieDm`4*lkJcYd3dhne*whjB<4T{1`{JOl(VYi<;bjN!D<0vMH=*Z!1@|8O;^i^$ z9Hr>dqu{B7UYEm1>iPxw59EjP?_6!wos>T^-&%0?&wtOxt!BG1&WovcfxhmsvV=U} zf~(6CdLs3vmWNCGCgdj-2gX{bO5)>B-9MmaT*dqutK*L)Bw4Mk(%`hdrTEd=!rVfC zVX)xcvZRtX3TvX)E96^E@=6n@jT?KznlBIgD)&8UHL8v@l?!VlRYJ)erD#8`N%1+$ zR-@;}jxHE6;>g&i3Vs;z^oR*lt=4&^XG=EJO={G)G&N=1Eep&1o10x*GycV?osRU1 zZ{Dd&vDGrK^i+wjp?$_GElJEPtu<|4nQ!w~#eI+Ts+xbKSB1JqwpD7=X-;v~DJ%2p zmlnmh^!eu2UK7_UeN(tmMx%LU_U4VptU!hB8;|({>6`kL`cnFo#;43HOWK@V8lT+d z$ZWfLr-f7E7SfY9OXg0USLT#_Gquynf==;se?O5r%hzzmiPV|H3%@VhH+OECwRu-r z!s>0u(vs~n$$vLLlAQc8jsR$zXCW2pDjDT)>YSPW7wS3nsls7rO3v&oE-0K{7QeYh z(eyIk(#MOwm@@3l1OGlcDgM#vWyvK&ZisvIi5sSu1@=8vmb!X+SvWkstnQpSr{gk4 zcDZHu;O=uy`!cNNb@%uhcAOG_tRTO#?~9i!oEn~gcbQecU!M+T_4DG7ZB88G9q~4f z_j%Ufvc~=5jumu_J2kxHgcGS<@)3TgtfWm^fv-{g)H$aU!kv28^x40}CFk|s^YZL6 zE7GB?US8a>&B?LxrvgTw%gb66EVi(BephT+jgWJv_*26>y<1jN7yV$$oYV2)n!Y_R zSLr+h`)Bl|h57{<`S$8J50yUHW31Ke(vwLqp;v@2L$9dr^$BkTRNuMu z1y&x%xbFOw>%64AaF4n@D_>i)@SPKJ1z_&wfdBGM_qiDOsL202@5wR)l03{w=@pzAD`UGOMm=Ck7D1&<4^c7Ui2vP z7Zr7_5XQVvzejQP{0UHFS{(MWk`EkA0DZ~(F zEx_N@b-$m8pPqVg-5x_zv#tB=iHJHITP z7ii(%^+;j&!o0G2sk_GdGG}#sba?W1jsrzq6I)c@`ADHNW!gX!bNq8(y`hE4UhYhD zz6Xm6^9sK`xTJ9T%y3!dyq)x!^~gW?*0C_{+O#!8i+#8>3Rv$?F~GP_{?!SdxdZIfB9Z8FNYjdf?? z7sc}uD}2?lu>VwFvpBVauU?a0le>G z9hZt3Jk4razbJiAB{Y$7A^T*A17#K}Fd*7a3bg!8%hidd7{&8uIE z1aZEkAF*tWi?b*9L=2y3u-n$Sk}+|KBbosTb{kw8jc?u#F@0Ak70pt^=1+=_3|30oQIV;HrW z>Nb9C#z*3_x%fyxS**mKDSc3$q+8MvNaB06d`Y|Ea9q;sjbS5+Z*WLR`WBIP((6c5 zA?Zf=o0v2NekLWQreO`A)B~k)lNNNtb1q43I-sVKB3LR{OzMg=p_HVhF76LcT8}iT zNxbi~Qc^+=-t3li2hyY^#dXBh^Q5P7GEgPyh8nmEkTeSm>}pA~QO@c~OTxGZC@HT8 z&c2iQ3`otS-l*G9(n6d#)K0oF8COP<5NU;z-bBsUO?n3>EA^7zhlTn{%WRxOC&fc) znDiK$ZdB4Y@PBmDDdhW6Qc*2@JCJl1K5t3NKrUO8mZN^RC2hr>v7aPOY-CxVIvb$3 z@HrpU!%2|O=?3pw`J8&$cr4fFRK!*E44>1pD=(5eNm)3*_Bp)0c)riMwGFQ%IDg>m zX`#>IIo(4(=bd=Vdf4ae0~Yz5t}y+G&pC>!f7IvH!lm=YKIco+_(`906-=M-2G#wi&*774Wj^N>6zYmN=PT^DG0y4G0JqM?J5$j04#zuRpfQfbJ6qxVFY(T{ zw)nav-kA<3evNmoMuYzr?-Za`e~)*3=rpDA&T}Zyv3TdKWm&xvoMO~$?*u1+>sWmf zoQKekeG{B)Tp{h3;Oqr1OK=9DnffO<6M+E<&bz4ofeFs-=q-a1oM%w!gA<(3QLxJs z9A8EFnc(b$cx8g~EShczcEFW|p@{2(i$e*{Zglb02~Ha7EZufeP|PZ}^C`{_i)|+r zZ8XJpj-m0U+RnYG!M(Oq8KwQ!cAl+kS>M@C5xoB1c0PkI`)sEX%D&%ro`ds0*v^CX z@s&uT^AGyj=ZQ{9C!9zpI_uD5zf5%e*nLN$GYhr*RiZN(_&U+4jT-zW(cx<=b|yNz zkz`k*^9VfK;CJprExqP<4xj;E_dAcF{oe39?{=`Pr2*$!9Kg#0&IAi=3IkspNgwF15ny2)to1h z`_yXAbxD?WOEsq&cDS{g6U2dXTQz4lYVh`IP90Ri9o3w1=x!y|oG;KBrokrM&0FGh zM;Gp}#NivaJ1%hw;Zo-%P7=C)mnF{E@H2mj6GqCeOPrTb*Ztmg_{`X4?>aqD69q?{ zo0?eG@FUI(IKW37ael^8H1dcu9w|p1arpL}(MO!lz%@slZ{XROBkmn$-B5Q6qP@N8-tMd-Q4&*!?Nz-MpO7bcNjJrCs@`zZj3+=p3jZhsL2J~m=DJm zawCGaoH7y{%`tjR<;LHrQC=!=(~*Ub8{R8Jxp6xVK>p6N`!)Je0ylm~z1!SajGkP9 z8Yu;hbFX=8mFwrV3s@*j!#T(fySJad^Nhw4asYpqVbcz>xGt2eg*b!N-jfpxH*}> z<#kJPQxxLXD~xZVQ!cZdyG(R~ zl``0JW|$y;OuCch+--t!R>}~|xyJ;3R!SesnQ4M>Fg3xM>T@22-<3vK&b>bSZ4{=` z&6YFEm&^iK{uj`Do%>>CtDKPH?C?2raG<9ZVd8PV_ElbrfR)CV=sMr{D)Zs;ytFy! zpw7-%TuB;#u+Z5Ri`$$&1qZgXTl@La-{g*aw4*QmQyi(zUhU~i{~68Ze5+l3>A&P5 z_?`BROE2ZV-)rBvbpB9~vrqfRrT>QZb@prDxGLTIp;>T>( z6VjLA2ylM#Ro;e3bn~htOI8g%3BBEBk*jXT_WE;T)x`+YTy-Y;-Dla1^iu6LYA5`f zcmWPz=YTKa8Psys&yn=BvEj2S9LBay!HY>lfAg}mtqSqjwke$ZsIda|;jdk3GmKPy z1s|PEdRU4uDFx5c)g~s+s?eJ;6#hSbR9%V;mK!t3U;!;q@CyExi9zkGqR1-y(ulY~ z_bx>i_mB~*Srv9-+os^f#G%%`;?}k*9A^v#FD7JSQmhJmfZnFyeR$Cqo9G0qLUYDY z@M8G1yl1k4RiO)GD0m+geQwRL^CW_S(KRvN)e6^S1N!1BSb=1Wx^5jK#94td^h39< z1Rs*6rn=R__J`OzSQTTVTO(YJH4q$x#g1Dq>}QNsbre3o!GCodWZ5k2@CW(=zhi!I zTNs0hRv?W&v?`Y+?>BcdObTY{a~p;2i?DZ)?6mcc$wol!Y^D=88UeMF+YG`@MnLThMUA^R8v(U5A7?r46eFN^?qg?~Y6R3y9k}7% zVg%IA)2#Aajey!YKtFCX0&3?Kw&U$aK<$iUSGmIosGV9E_}vmCpmw^my6!YWtah#o z+Y3&@GC|dP@n`IPNkdpttnk(DS4b&|4O>rI#B4 zz2z7dZte;rptt;p0oQ%n2RNiO#pBcQjGa4cGB1oW1Vn?iWj2ZKyR7I z4)DAY&|8vllHtB+1fLbSsS|{kjKJ=b;LZ%&U!rFO?_j}ag{!k?1TRL1a#x4_>{#qR zuZEpU7`6gAtghFL0d${Fx0IYk4VSTzS#Cai-~ zy7#x-!={X=qSUavKWqmv^alqeBkhmj>Rdkr|HaqTwb+f{0Ltr4mSBtZF*yk;4-M+Cz^?cqs*6kNg8-coM;H$;SEW_umU)^hC zi86iZaadKmOpM_+m+Cb~PEmIDtv`)YA$Tk5ODF1p;8 zp3WZhb~vpbEUfg^Vz1ilORqz9d(8j0ed)~@{5)px9bbADgI|Qx>cao`e6`qbthn?% zs^7&D#l@xfWbpfNS|SS>SBrh4Brbh0)!)KtzaqP(akbc>IEV9=aMj_SSM?X;3Lv&^ z3SJCF(2QP1qxR)En4*3?Gyf-%Tk3jTa1AD;1q?eM!LR^Nqgl*G9nLzKFs% zM!?|iEN?^Mdm~^h zZ%bjH5ipjIVAt4h1dQd^Qux6LXfrhIrbhM?XtUrjHtgGK*iJalcYkc;XOpvGk2G?A z#UK$F&n%7_0~pJ1pzx~^(9%;W{AL8S^fU^;8v!lNH{`mdM!-_wK?=u=fTrg=bKT=c zK+``);e-*;^vfxnGyXJfF+-Nw#(tRMqh*=EVc0IK{83MocFmG7dEY6MjIJ_=QgfGR&op{5Z~ z!@p4o838pMr0rhu?E2_>$K-o(vbTIoz=*1pGh!DmaA`2`567&_jDXT6b0yW^2q-Oo zR>B=%1eBKVJ#hyb0j2%qVhDqbfJ=r0`gOsjS0kXb53ofqHv&uRb9-diU%{o|T$Z+1 zM(onWX}WzyhQAhK==ZP;rw|=H@BmLKh8qL$dp?_fgc0C(ZyUl$Bf#%Z*=(bX0KY%u z@i^KD@VhfRE4_lXggeFv@cRaiMTJI)`8_nlz8@|HGr2apT7JLBIvJbcXNl-{ zQHHaZeg_&tpJWWcZ<|NO4Mu?9+u0&F8UbEiMd2nR#Cdf!KEw9aMxKwL(cSBn=i_vs zIKxkGnCBfC&H^L~Y`{M5G-CjHwq%punNf2o()oPIb2nB}?sSs^b@dcSmAj09x+-R) z%rFAH`h~;v-9|uNJ<|@tJw`xXJ%^&ZGmU_((8jl9*ssy=qj1r^O@6=L9f5l@{45d2 z^4S^oFHCd>hr9bgMr;hYv;_hWX2dSZG|WR_PDb^`*nuT|IKxTANloC=T>Zh^SqFRYz~%Ccuu1eRs^nGX%D%y6!x0j^cu=Q4szA^Tt;a5?+m3r0Ze!{YJ` zn?JD~JdlUDr!%TDagZ;Kb5~{fnHMdt&v5wr+vxf@NqJQ+p{;3PO@_UR2Ht1eua!&u z^(uEmhM%TsU{i)uCk&T{v*zEH0bW|1lLg@&BcN?+@nCvaf)8!;C(nf6GXmPCE02Zu zjSwrv8yR+I*bn~1PXDHySlu3h4>SC9k4}7=;S|t`MArUx8BoP;$*^b8K#;v@n+)J< zB`p3j{4`AiyE2?**bF?wQtUb3z*iae2Z#$+X@+=zg2wr)e7aDZ}}J27aSw zKc8=4UxuAn7Y5$Opy&P|1N)fMp$tDw)4=Z;PB9V%T#Sb9F;fRP3KH18jvE0LJB7ZV zFao|7={FF=)=49vrcbb_r;LD_9@+-N9}+Mmv2}mRupgsW?b!;y%Bw$^@XriC{pCsV zzZp*ddhlvSW9U|!bC+1(dj|CD zXt}n81o-_GM}P_@1^nhup1FxeKo4ox1VWM#aP%hQtjcwaz>=l9XEN-Y;dF3EPsIJ5 zQT-kUo@T&p6GQb)5k_Bv)UhW)Tbo7h0cpSX3i+xVHeRWZ-)mf`emfN7j_vlZe@=L>P( zhzoHfj}LM1ObBtTOA2woazY$r+)$k`PFq6-_)HEh!)L|N5BN+8c|AYGo|YP7g@;3| zq`I+73ys=%mksKrdDj#gw@Iso(XT-ozd&=F#Nyh8csD|O%fE_!EVoTOi-4+Fn(5pN zKU4a0Vt*=A-51?vIY;2-MzFk+FUho5A#w0ty83u#tmJPn;fhTERfyr5ZdInkO9Qb} z>D8I%PNlEzjD%~9fVKH}3TuskmG=!4))@gSZ}04Ty%EgW_p3(0fQMP;xlFq=GK`&l zzmQq(?EAG$KmDawn=_pc=+)pB$l@Ith{yTBWfa~s0`lxd;R7S!I%!u59~q&NmC~_O zPn?b$p&~9{QP^e#j5qldJ~e{Rb8};+{R`cEE)nM5lAGH&*KW`BvjFV;-()(8jnEu} zXkd3{>~M;w0iXM2rriQ@!Jj)|pRY1wN6$l-BCt2pPt)Ego9T2zqCf)I%Rd_fwr5~p zrhOd^q;q8cK?YWJLf}xQpQhO%N;943X`m_(zvF6uJPaK8l!wAe(;;xMOs4RM1U~wL zW8-M1y`5Qn4VT^D)I;`ih4FW$pPAFg_=t0qS-hPG-H!Y>X0VWFGwn(kNrTln$@?O) zLe}QAkQnjPG!3Lgoc2f*^B`3QY>b9ivSgJdz$038BlbvIY{LO5Sr!+gy4jreJr20BEXjx@lF zX>Oy^;p{u-H9i0Mjnc zFd}}MrhzLW&U-X4sT=em=NlLpu@BS0h6;!qECVkwa8<-l)9iaABaV&rTwr7}^wE*n zVB}}#jdO=Z>}H4yZsI<}BeAi^<>I_B;-_hPFd^bhp@FCKpihhhmqPaOWN1DQhZ~K6 ziS&K0w{JEA=FRTx9>qq89dY9#_T$VmAN|g~E)rWG*5kZBHR7i?%=6BOvzK|!rPFt* z)SNro@z}oG2pCf9BAI)SsTb^x-g$e(_F)+i{E&xRiRxt{n|5Zz&&-*{gAu0{5(P>* z63vwXE(dOA6V5;1;(ZZ&04*M4Gu|(Yz4H)Q5b-lFT3j4)N@(#q9>b3r1E{FmxjK8o z2r(ZYj@T<`u^YSWBeM7heOwyxGcQ_vCgQwJixW9IJ!=dkdWC!{V*gA74KZ=KD`X&n zlgRTCKTWgo*F~HL&0*jRbSw82H9iNP1Quk21Rn;TzVQ%Vm!N@Xb;RzDy@MCCp0XO0V{z9*HcbF7tD*nc&`;8G`4voJxV*krLmvYefM0p;oguu>-pWZOf z{Sl`*+C4D00rVebfc>i{oj7p5#cv~aKO_$R!tVXOEH2GJ;OB^+dC}r;5obItJ`sgp zY7E4h>PW<%O9TJ%a5yRh719tm9`VyO4V;cRFVa8-7V@w24V;SDU(i61jr6As>}H$( z6Y2C88Ka4X9IUuEdljQVMs1{y@2A{tnh1HF+9=zJ&~wHMOB&lp+V zdNS}sJ_1dmewwC%HqnY}Xy9plxRGcbp26}&lSOD5b-tznemmi|ju{WW*bRZKXn>|^ zpk1`$aT?egfZqOm1G!PB8Wxnnzc|=kBm@8UKp-y~plRmPJZiTFi%?F)tpl{S(MFXQ8#9bx> zlX@X=dDKtSH1NNuvxNrUW|I}1Z(vB&{+$LIuwt%~fd<_X7!mc;G!2Z4IxR8A1{$!* zt~+NSaCt=t6C~gf$-v1J2u0DFOR=N($RuiIOw{g=y@Lms{a9sje`f?HM*Ym3Sxk*q zoWm?;)Q5iSxw;SRV##ioz$`|fSGspZ>y*#prl_-?S^Uhih2oe$!QFWXltcr}oLSrx zt$2c2v|{z#TP};c*{1iE%iooz=ZDMH-j1da9w}FQFJjVkA3eYJ=0@!~%(p{V#LZXj;l@qe z1`zc#GiLE*)cKTIZ08uUyj&LDc}Dbfxh($2(#Y0&T)}5cl^HF;+_6`o>2=Jn^c!$H~`lz3o^Ne6q z)LFnR(h+vwj-ESDsZHS>Bj7xx359o!fGGhd9dAVK*OSyLG z#ivo{PiDd2<#D$gr!mVGwTJM95pXJNb0M?C2-q9VyCrIeGLZ$}mhNs-DfkKp_p7L% znKO%Tqs~i66llP)>U(1VSv2K%wa*C1;%Dx;-w2pLj`48%!3db5Ry2h0qY<#2UWq>C z{$vC!lGb99a1R&(hsQYf&!3GD^Ltm+-a)_jbVA%7`P~9@k9#QUXNlb7B zeCzfj>m$(!II;YVLXr{iz0zq4juG&^QbK14t`YFPQh4zkNFmt>_+F$Tg%l%T z`81;ogj6HoD$`odBbAMSFG}8`kZuI@ou%BRiV@Ivo~KaF2Qj5 z^|I{NNF4MMH^_>u4UQxuVT&w3^PyIRk;y^&xc33NA%DAFj{R;ze2ZJG9u4tNnJeI2N7M?VROj zUbNUN%lVELYx217Ba2wT(?GW@J062ta7JCk^^k!l>0iGrKTXrX6z8Q^yaX*}-M8;dx$U~yHJ&3li7&vSjUS{9e|MBr6)2*l9hTUpMX*i7l% zWuWD5HU{uWLGQkOa6!y;h}dECdY1hREk4OUx=|KWcqD(2UN#bt`rAELcVY81O zGXf@w6bi?UfJveng%d`=BoU@?(g>I&no>Ar1WXb`8bJ8d2$&N_QYbS5=7gIloG}7! z9JqtRUq--^7(?%YEc*(SGx!}+QPD`OE$mY98R1+32a8p*oz_SkY|egIEtXrbUOWP|vjfbF78_<)yzW1X zjg0}cv1hS~5wJ4w%GuNiv4vgTY-b*`*uVp;zOtCbwR7|A05hi_Y1#HO*sM*@Ycn(E z8_9OA!z2(ZNtUS!lW(>WOujirK>d1c+SUlBO)oM6#?YB;<0#nM7(h`wQRr&~6m=s<_REZbq82d403+bI8be`_5zx23=Ps8U0ms!{ zOmU?Va9rI-VW<&sTvhG};c6qGJ3hk{!;FCAY70u|4mSc8UtdrdX#^Z-yD5w|0uHnv zD2y=z7GFmwj5PulU&kqoGXfT0XDD1}1hgaHvguAR0@~4~FwqET$I29LFap|>;a}K{Z+j*Vs z_$w3Lmwj#y=UYYH`;7p<|7ME0Mu3~XP7vl90dB5hiUrxRrznsQr`s9X_V;w+Sthyk`W&~#8a~EaXoMwY( zIQ>7G9a|EnaaMUU+t19I#k1MY|Cj||oa{a?1KyQGpSvR4o=yWTe29BS298!o;Kgh| zP1C@-Y^Q1-3>@dc^NR5RZLy&qgjbCKr(3Xe8;pR)dA%Wo*NlLbOQj|dUN-{2wczOT zh7quGd8QeJjYdGhf9J{1n?{Hge08>cF zey^tAyNv+9U!dQ6i~zqsWSi|Z0(t;?%@^5rG3*EX(}^8&;&b-W@3Q@Lk4_xOc0QyN zn>ZC5GzQ>=-2=iQBfyCl>Hc9Oz=`|0%Ml~+h{T25Z2Ktl9Kt+*RGvX5JeuvNH_Y=y zwsQx1dEj(i=%r(pGH8QZ?mJ7836^a&W?842xzc^rV!2;0S&f_ z9qlh8puzrNNBi3da0!0@o^3COOTpz_OC6Kn<5^e#Wcyhn`kj#DL-^Gqr(FifWtsMI* zxD@2C<+yPOOJN;&p^I89Qw;oJb0cmDbQcWu`!n$A?EZWIX0Iz z!7Z%%#me*UZU{V`Ye!cGKcRiAel`EdK5y@M%tfc`@7dIri_^tW8I2 z(>Al&nNu-@DKeJL?sC~Y!Q*SM1RNK%up`ImfW*PU?1f(|o1QpLalgw6&^9d|$f`tb%brh(Mle1l8NvAEN-#e8 zO#=CpY{D_0tXz9LeX7OdATBpH=O(gn6?6UcmOfR@b&g^)P?J+nbz=bi1QlB;*RF&< z7@ST6X)^F6C+A?UpQdS`Zm!c3i30rHOSgV*a4BR~G!4|swfob+aSnoYa;q{fxG)ES zhPi&4rhyi@&h<2qf)BUV`5rXMwdd2o)$Byg*YHCW}ki zd-~=Em>08+=GqTpvo_0Go3@$F<>*q_478|(#8;~FG${-~`y(#s#SK#B@f&Y(Kr*kjpDn z6J+2Oeiw5i+8;6W;8wIh4XnnZ!oB_cA{3+jY2dD=h?^<{`5X*N(Ec)TZ?5wa4IJYV z>%Q|nn2~Gmpn-ciX53?nz#-uNTt7|IgN31pQ$dNJ1QHeQvH@r4I~@<}ol| z26FLDfV(8uPt!E8BG>7NM1c=DzOFPLpnu)V;r%&NrkKTLx%L=Z9K}BUlq}X}!sm1S z%!?LZ&UIGM;*qw{*BOiGJ`-5|>y3au-H9##syXg362s|Lx%L)j@irTEwX#^n8Sb@Q zKQm_*n{%C?nZ?eE(BCl@V+ZcWT-)Cl2JW&E_m&LsSzGtLTt7|Iz$dv*E)oT1CPV-1 zoPmIk!geFXy7))A_SLjFz5(L4$YLM1OkJG>~ z*3?cJ7{n(3F4s@fH1Kn-^DhmY;xK&J7(gwx;|O%b2pCXTq5HbO7y-+NP8<_ti{eE!bHrClsa-u0p=>DGTr+akbk6dRu5(T=`i85mVZ8w0mdBzBE zVq^fqUq*lvAJm8Nw-Mk(qgD|9F+$9Vu91bNzIWPE=^?BwYq4 zQrRVw+Mb(h4$^hU2&kGyVF-RBz=>Ww43doiCwNbTThRzHC*s=LEnz>nm}6{0+t}pt zB2P5}ZT)nQPE>8{jH45LLAG1n7(h*2#M-Z61USK84|jt`Ks})sS8i+1VHO`p5SOkj zM&l}y8*1xk=FFmgTgTTQS@8FE+=j*gviO%rP9q~Ai{~prXlw-3ei>bFVgwYtIqRya z5m4|BJlL8UAy)7@ZS6+LF!*S5#MPBowKyQOXzQoH^eWQUd6-@WX)((ffLA=VbhC{B zuinP_f}3Lmcy(hN2)RapS3R3RXln#`^(rTZi;NKSs&!j?BfT2O7HA`{d_30Lwe{0q zdey0|bB12MP#Jm`V*p<9H=x~oBfzV6^&oULLaaG1ZEM#VfGqx(kGKxX;uenV-P`(^ zIkV{3)|rDufiMf+-xxp^*(~?~BOr?pS@3~IK*6UrgD}VlD0qJse6SHv@V8j-%Z(5# zc(1nhdV1BEGejSG<&`ORoyrI-k=kHwF4gV*mpQdf8QN?LTP1&&v9r3|zxw ze{@?vP1C@Hwoc`NFtC~WL>b@=QPYZZ$F;R{5gGI%uWMTk?*X%dll(||V_Sb81Y&Pu zqU^nb>MUMC#T}|L-(ls{%2uMgDAUn|~<8+v>w1-nHH!jW6YLzssz=6b2fGcq4kFG`@<X8AJZ$^R07;x2JXs@ea}+Y2ND&K8{)I8RAW$z0$mQ9_)^J z+B?mA*TJ5cr9PqNsF{9g-U|;7#rC=^#G5ethj=IDfHd!=2WKN`Gf=Yw(}tr?T`TI9 zxgf+_C5MN2zvGCs@rK=s+nn1seKsrT6A{W5$5|*Ed87i?}wU~Hj62~iFz$I zKg1iD7KC^^(89EZj5!rc{ZNQ^_$*3WN-dn_`MM;;yG0%k@eYqCLcC35Y1(W5KjPj5 zPOhTbAHTP6-%ckp(+M+^$vUBDvJeQFeM?9}db)cio%GCfx@WQpbe5Scl1#$P1j4?m zh=_oQh?# z<dwVjPwQ!y(%w6t7cK6r;`mR?w^x1$?Ye6|?@qkG>cwir72B)UA@1(^ zybkfg*d5>s`FU9Q_I7+ z=bh@gvk`k$N7Zb^{?w^n%;41>LbpFTwLIzhi&M+97AsuK^AI~+TeBALB!z3g4&a1q zX>$*UYiad%!?iR-N5ZwV>rM&R(o7l+*K#$P8m^`7a9X&Qrns_jEiGH+;p%y(A@b}_ z8HkE-EsasJaIIL7!nL#m%?Q`h5_3|xx{Galr$Vg^*V4RF6|P>+0zTL&Ev^pN(g0Eu zuB9DeR=AeC^4a0)By;{+<(w0)<$oBR8?NOhcV4*qOcpS`OIk2LT+3}{ZMc@3#RcJ7 zZuw3QR}Zm(maeLEFhuciEq6g{Q2;<9T)hV~dD_`s(t>UjfY?;HdW^CAx`a#8;p$5n ze7!>I30Ge`7r}G8s>)sm`GDH`@NY~|8^D#}>bDX1DusJhxcVby2wvS)#Y4So!nNE) z+!(IDi%4%%&AusI%bmf^;p+Ps`yN&6+r!n5v6^FDRYeqWOSqQW|NY@ws_Y*N*HW#1 zAYA=r;ykGe`gpjOy7GhJ>Zw#&pHZ=&2-i~IeJEUg;pvEdUd4VgTuUYP;czY0$WMi9 zsmMJNuB9sVXtg~?BuXpi#Yt>>r@+Y!$PltliG{coL__WLZ?ojKvaB5H45mBP2vBa zQI(aik9`3t(SL?)v!dsr0y|oZDHMu+q=Nst#yK6TP5Cb8HXuz&ZSb<~jlIllH_u|W zXHlFT{S<@}{$uI2;M?*8&Ob84dQ4kg&!O0|vw(U5%C@3^n!yZDoWy!&p-|M*0I5)Z zsl#txO?ex7tFv7d+r(_2g_yFU6JR|2bJP_Gl)u^OBTNp0?^wc+^ zq(#5O94`NSJ;`B*!l6aH6DgCK?qLw{Or_;aeWv>nMmcUXJfAJ!sw`LAZQ1E>Bp5WW0gXVGufZ(WDL zZ!4K4j6!TgI#Y=7vQq(n5HiBprQu#QI8rZOHdpZ3IE63tSsHFNDQu`pA+eTmt}lBOMWUcSgTv+v z4kFJpk!-ihNYWwYjV9$mFXa*VkV1BkFm`G94*ZryFvrVx+0F%Q=@$`m`U~X1^4<1~ z8QVe9Jv9jJwdb=xR@K?qXO!===d(-UDhLm&{Pp&HB1Tc*w^(2^DRi#wdjYZ!Lp)@`E9N2J1Gy^$%QnVcdQW?DmB~(QhMKPMuFM_*gM*ji4 zP!rv{6vGu=1csawy%XiniT0xWxzYDvlFo~cqWt;MpMn=^qhCRd3!)LU@MO!mI)*B@ zIZM&>2-`p92*imJVHIb`=IlUo=g+h7drwBV^($=R4(E?Vjjr}khhr(C4oxHKPbnlV z=Q$R=*IA5&DbJ&gy3})H2Z`DS?zf`vfLsUam(b0MgHDd9k78nK)QQ;bME$gsx)^c{ zsNaT&tvKRbOw{?{dyRT=?2APG(a9|JF8l)Z6H9=4xpOyB{}pSGM!hOly%R|DF*tVg z7iUu3K1y*Ly#=!`96b*NbE9j~w@CDoIC4dwM@-amKwzuldgq%cuI}k>j910mW(=XE z`b)tq6*nn~RR0*UZmwh%;rbeMvf}L`A5g#py$Idn#F11t4x%oqxMRldU8aCLE8d2z zR{fRef5rRi?#F1`^-0jJ;{6f`)vv^$SKKWDr~W|)fe%O^T>nq3^n-OQz^z|jhrov< z5UKwaBxl8kB`~EvZ6k1x1fun~Ve(hpTgM@uTL0Dg2z;cDgE+1Jvnvp|ua3i1R{vvg zOT|a)I1uIaZ?_S+zmBA?s4rsdDn3@n9?Ym;&S7~#0@d~JVz)nDaTQW#D;hi~G?*^} zv*HsHh+|eQ+>XyHTmZCX{6Pfi8KHk^ct3ufx3m8bIXf7AEh6Fvry}C9SlwQ*^6ZMw z&3F}&^^}wqU#&cK7-iINBmKT#*@r;5z6$fR;>F7I5Qx@aj44?0m&)4_D6e`hfx(BKs=l*p=T#s9MRgDtMR4&m#EHpm(9F2qTt;Z=rXAc-a7veXMZV9R7%Kdlq?? z{cgMDY(%W!upJ6Vq+k%IU~t&H0M2oRU0@K|a)n4jFZ&Njzh#%ghxXlJaK3GD5cvfB zWwRkxD(2eGd)b43M$DAYfDhEnh&9Bfjet;n7)vYqVTd72qI)pPu@>i-M133Pl}2rk zwG%axBUw|Zyt#uMaU5_EvsL9wn zi5eH#a687%juzk#MIVA6y4Dk{A>-_4w$o6l&X$cm#cWBaR95s2GOyo~K{m_z96)TN za~CsQ;J1D-_V3IviXyD&?`v7lD5MoK+yWknZFQbOa)U1YY&*UiXl=l?q8|rs(EcB? z-0hBwgelLUg&K8N>>yEpgeG8pmxeg#a40$xzfSZN{Dz||@asl-A2<>{8^2R5=c%`gQ5y=WU}ZS2jn9!EQ^dak~)>t=CIh3on6O=EAFMXYH3B6i{W zS)4HC^}oj$#@;%MlVV2wizLtuQb2Y6t5Xqpn*?Upe`*;5H%efByH^_i&SuaxG6k)f6E8=^duP9ZW;V`7 zgnj8rIE%;Av^b5>{|QGJ_&%I{H1m4c)2I{MzX;ExIB%iCVgE8bk16P{JT2Fvt@dBS zGPIl`m^fBz>SC4ZSWlru6tL)N)Yis8`zEAy+@TR7*3S@!Yv0vv^mIOe_#Wg8-c6g zxg73{$591F7@7DB5?Y~q+%uj=EY?ZH@>gQ-b*&YPk#oI7^A}uV*?+{hVOT>8k{(3F z18}R}sqq}aJ`GW!TiwTq_CBP14dJiAwcn4x>d$Cg*P4wkg*Lk@pGM3JNdGAuOpIqD zH~~*c|HAh!w=0X-_AU59$63S;@YwPTeZ{ipxUP+H>0(*dnGfUVsY9R+qSo5E(E0e? zXt!BsKA{s@Cna=QiLdJf9~(-|(lFVk=}L6S{malwIa;%x$tx{$E%3` zGn`_QClr&^V7;w`3-H5QjI#Z?@XY5>e;Wg({IDHy!VmNaKXjmkHaI@5?78BHBP{9j zVfR&(Boy2L9Dem#G0g&aLe_0WdLq1P(YZh((`*OAIYbiXp`f$n^V`BaPlczxk%(lT z!$2B`6Xv-No@?QRd9sp;zd`27Ni2Uo<{^7RcSjBUg;=ueuZJssW@`8V3cSnI@HKe8 zY-$*lO#BVjFeb75^=cq{UMJD~J&nHagexw`;0SyE1qJ>IPS}$ej$ki^5A1n1(a4^B z>3t@g&z{6}t@}Yd!=6n@Z-CS6Nv018>ocx|J(E--$$dAY2J&6AmHL*BQbDWfb7g4j z4T`0{i!}S_-RQ4kskbYZ+JK^a;S@`~Q?b-2BKQ@U7Vcf`cZKIN+f9hL5-z}JH$wE; zZx7GxJ^V@pCHm|M0W#W6V|?nU|vAy};rZojNHJz68$~m@Q3?cn>ql?@B=Xu5g8L!yke03Y>5QaYBMa zt^qfUgO0)tCxg4@!F5ttb;Gk3PJ|ZogspghE4Cx)EI7>-Pq8RV{R&q|ORok3cLmbY zcf<28$pPWQ1;42eQ_nu4IDwpLAB`WxA|Q*+k?@)&2z&||J^`l&{bDufKS9KEaA^{X z>Zgy)_{31l!n0iJt_C2b44 z-$O~lb3X#k4~Q4wxfuxCXN6bso7Tc}FC*gL1ZfLcsUFxNYblY=3A-&s+KuQ64Br&E zHm3BBBZh|B4iXWw70+Jg*slrL1A!>)|b+mQAaxHiU01rH!H=p?s5`T6Tgp$XBbKApS{9KP+eRUr6mQC zH2m2soy4;!mH+qYLyWXp-5E~eciUkhK|^N3DQ;cuh`Lrp#1I^nV{6kG7<^=G%(CC? zRI!D3A?3Yr16*b~fiky(#8=?jnB3WenBODxE4a=A0(`+K4cECH zf$QP977kIQ=nL?K_;4TWi6sV28@pi*7|Dj2TZ&bHd~>_*LGHL*sS%J%|qI^ zLlyR@m-g+@88W25<4pLcQ0#HwW&ebYr2VW82)%!y0@nJM5=iII=TDL&VXq_{3|7VE0hfg*U_uGfK%RR~~PC9Oz8DYF;pznQ}f3(ZVsae`m>~Kg@to$C*{)2XznF-gUBKv6eFu3+I zm2~>!h65WAcnoM<#w>6eUJLYSO}B%55Vc(XW3t{Wyi4@QGIaPqipE+ z6khtz5N3Q3hlfmwBI;I7zZgp_SDy%uWPs& z1>R_C_y9cbH#O{)O#BVjuwP>NYiej^4V9@N<_oMm4}#M6wF^`PEvc@`!977@Q;q{yd*cFXU!gFxtBHC&2ya^1oX z&-tyLgC-8Jajl&P$gi~v00lI48Eh2xG{31e($w#GO`T>pu&E6w@-#Tr)H1t)O)Vf| zfRWOwa=U@8x(E>yjFeVY*bQtIKX-aJTmr)4#I3TMRGac^Lzh~i37`!PpM<9U&J!gV z2N3Z9m}Qg9!QU-s!~PMaeg$rmkn5G@q}D44zr;9c*YB6JSxYe_^>CY{S$|m0R&7Ce z5H3*zgvqpGb4V!=jFj?QwRr<(pna#b%BHzui!|oWMYOeU5dnJVI?B(jB0t|J;&YoQ z8F!0#uwJ(xJqdkrHe2d^4JDk#optDotNG%Yb@n-{k@|3r!&#wH9$v|mEoWeL3_ZN= zaUg9WQ-&Vi$|9_@uj@eIeKig@11iV+x|n0z2O5y@!5DK`XBW`X(A#Sqs(uRV?VYN| zk3w*SuC8%Lyp*fg`1#+Y^FMM1u=dtCw0)@jd)xeW?d@hQs$F{vs$G3h5kiAC4ma^C z$6zOo2dZ7K)8#J4QW)x~alYeW^>h%+I(t(iQaWlJ%6FB&;|!@$df(A2wQP)5W3pG< zb6LMbOVoz<&5@WSkN2|=Lp+CT)Jl>4I%p7{r31Mz0<%@X+ISJD8=hi|>B|{LG1*I& zBW9{S{q`tIUjHV9oNtBaIajcXg|!lDVWrl_FRw@F!SKlpId?GceM{hbC|u4MYvc2a z5IR|>KklX1>GX4ISz3iX&pGEN2z@66Uy*#yX9lI$(Uq4Wcqv+cA>7LA5cnuO?}qEV z6@fNP_6E4lI}sR$XFDBrkO+#fMY`JGE<1b)GG`EbJ(912Yoplh+=Q6#A@miv&Rqzk zF!9#Fbsj=s9G(LVT#CS*@EnE17Lg4cmC_&Q@114RtmlyURXAzz8qD@CxVAVrp`8tF zX9KrWak>ndLSkjHf8_r9QslS|u?K*?hdF3|>3lz8K8(<;?^3IV5M{+L+*5v4|Y8 z9wxFjvK|J~d2o2d%KDTx$nOM zO&}$o0?LzcLdhS&^F0Pg$>>(_tEb|dpM*3+aJ_RQu{bP83zyL=&Iv4fBt>H-XpCjPIuF`&F)}vjELE-0 z!l#+z3}Ep4?!p`ecs8mmlFvTLUL30`b7J#iL$gk@XJ8(O7FlIwYY+t~QG**nE6dI( zTTzy&LQ{1L7EHI@VoYR-fGJ_yiLEIs1D3+JkrrKw%=584PZbZ;fNA1^h%D3Px~klA ziHD|JQDv8vp#;RUgjfZRDOE62RaRC}R$kVH@}?u2t&-e+^o&`PGM^O8455UgUBBq6 zU>Pj5dQt=$J2RNS3lTN8ovC88X4Rq7jmR@wJV?Sfx_vsGIcF8-6E-t`BQa&rxIp#u zD^LWhtrZW7SU?ZN_jC~7vf@7BA=axvU7-ucfeonFWy`Rzl!cmZI(<)vGxq z1cBPrV4pe1Q0bI8C)t&ewX@&ZExDUPQg7_B1J@LmF%Ql9WH%VKwbpK~%G(cjyF;_K zlx=l43vt@Y>>(t!w^_|-M8|PBmNHLn%@wOk zb0U_#U+u+9;{_!VDtz{S_D$U&Pr@X?MiQikZhBHBzoUDO z%9;vBJlm)_42Bh3cNK!-}mhg=yJt&Nkjs9N%qS;my4nFg=A`E6i32TzQy zD<1Mv!TaQE)hu1uCS90J7fq|pr8!iqwggeJHPoXeIkDPlQt068biZ_+s)Vyp0@+>T zoE^kb80R#2eLH1N9AjB*0MB@Y#ERmLxZya`bVr%S5^;|mfVvN0ZIZC}Lv>wQbcSeM zc@WOFhMolYzVhN%JvPQiskvgBl1Pk}oY^k|w5~SgJj&Db~2P zZqd3W#|&<{!o9_oSd#_1GQ5Z2jw|am65Q9yp$?k6Q50He$|tOc`wX0Iec>c|;2BRw*}FAphs4%{#tiXq@8%(V`cQqo{~ zMHt+2g?k(&IlT9ssI1pWaD^dGkOO5%|8-XhxHg2XvBxhv#zgfn{=0AiYUmUXFk6S9 zj5v(e!?5zTx%Q@h|_x`oNeU^Zh>Qt+X3&^e!?fzz>qawy&Z6`_A|q6+7IA8?CiC0U`2xK;Z!d;b>v|) z4AvA(44Ewkw_IrCl#D#{y$9}oINV(z;IM?P^8>@ha!Zh&Isp>t%J?WVPnxOha7h6~ zF0F-`pFS==EQK=u_<|8B&usjHE(A;A!WN940d5l<#Igt(2?E#^K>M*cAv3CJ6gOo= zS;j)L71F$i$n)XAVgzwG4{_2s7{n>om>LIzKHZdiqM;~9dG&B$76LVM&I=3$A_ZZ$ zLb?p#sPf`hJ^vf5%*uP<(2jn9?aF(i+TH3)4Gy{ZiQUnMk(!=oz55v+u>twDk{;?3c=-!M zM?QyvgL3N;gr9^1xe2}n7lFu%#_NtT-x4?^5ztA}t8ZAI zlv*J8K3o(_Q`e$#tL_*>&%@c)S$@+3>XT~F)4+&Wms}o2bzg^{xsU_D@~B$?zlJ~9 zEuDxRvn1pQR>3*en0<^Mu9|APz*F)Nc?%rKOG*OH zd*OgQ2EcNI!(!t>lv<7&07F*OF~T;4#aa$y=rBO|mB;oXW#L)e>5ollQqrnmlF2&RAsk={B9zdUMKIS_&FIl{t>JPuzSRbL_a0cJXa2u6C#1N`1|8+`A9 zgYY2WRC28etoc+G2Plz$B*o)3D}m5RS8(t<*bW%I#F4_ivW<@v-dRY)6yNXNGn z);}pLPoQ#~70hvbv&nfFH3Cz2X|vV+bTkkLJF>MraRb$M1#2M7A}ZA2V2%^DRt;UA zK;<|qnB(}?av;%Kg1K;P$nmWunbBGTIrj@lYeb#sS&B$BoZxox4iVf5!Gr7MVZu$| zU)Hwq7=6QVz$ds)yh8*uS`(k}hj0p?zF)&(qffvV5eenXgDCxs0#dlKf@|RDH<{@- zc!U&IuiZ^0Fb!UybF2dGDCq(#L#(L_US{PZ;!=6#m(^0nusMWl;XrAEZE%bx+zE$h zRx<&|XhKy_j`jQm4j2TAHk*(o@Q{5~V>cUe*w$vhg(b?>d=Gt#kG{o6-x4Sq-fp-Y z95{(!D_qDrT)hRY8JC86VihSw(+^wp8vN0Zd}_Se%m0)qPQ(eS9@fFaAhlT%`v9-O zSF&81g9JR6!QF-iYIGjDoESY^Q4xzxpN>@jVP-lGknuZK^on5M4hh@<)OI zf&=$I3&0l@;3Z%yAl$O1|AJ0Js5Wi%yRZ=%<#9u*6AZ9^mdLgc?v|2srZh&gu$!fW zIRci;Xj3r#$S6-lD-EjL?;?(=gwMmFY4KyhlK->faFN0*P!&mnut>sRz(Lj#ybR}} zFU@tw{s8Yq(us3|RrwS-$245M>Hu`iX|3&$8dT|61tHJKaVlj|hhu4ft?#&k0c_Pw z=3^OzbW!W3!CUOVrIcyMmGPg|TgHC?z=|!0U))iR0Ayc+#gA}>H3nM&dfz7M zGrPDQ4mnOdLIsY{AK-w2lI7vz=0EHkiy@5(xm1A0IiJQHZ>AdN^;3gP$MNK{;inqr zU|v%n5ahW7zvoNC^8}oEO52M2+?6*41eCrIn3!Bp565x|hv96I-l}Yyk#vDbM^+W@{)C`-)vERFzgcatM2|geX=6z>!AK92lp@|=Z8hgn z3DS$lb&acX3DVDwLkd~UcsyOguMw}VG<2w8G?XUfO@}|iVNMY6<^skms>Z7nv0C!y z30PFvx+E|ph>(jLe-()om_=^uyV7?_7~CyHmj(mbW*mZra0Qm(1%Da1bm#|6|pEbHIk3@@CB zA4=)MWyUjd;C!2_}H$- zvEulleOBY%g9k<$ckCZI(zs`DV`6Oh@V?Q5$%A7f%g07WN5*%IH;x>c7$ayIpEx|c z?_h51;Oj?rO^i1d4(%8_x99L^ad7Xx(LK5ShsTTgL`Pq{sbk;huErgQ_BEnb{ISNJ zsQJLI!>Dcl->KdmV+R_OeT7V+*sfqByV95$-L?Pl@JO)IhW!V3?bzQqzIO-Gy{@(t zRVN!K4j$aUYwwPIqvMTxcI_&%+~%fYYq6!NrMcML#K`4{Tt0embY%I+j-C6KH#ar3 zE@yHBk|!lKf)cF0@xYE)?R{2S-(Mad>3+j>G#WiW3(e8W~3%gaa6Tc;Dy*0=Pg8k)Sga(I3P?=&=y6adG6x zu8~6%`wosWBkRJ1D(*Va+KM3R%6Il~(s!>z5C&E7*2KsG>vGm%ggvLV>~9KTdK zDkF2;Sqoj;IUIK@m%0nI*NrTl=|&^AJ2g`8o=zB#yR({6SlnHJU^E^`ai=FFp@s1TP0=Hqbv|%c>@XJMzVjM0;ZI=V%+9poXVUF<1WU*jpW=al;lS0 z5Kmao0gmHTKRCi~k0Pn621ym}yv2fTgE8#5JHwgU;6`gPQcK-fM5xg0E@4SdP264L zydGm+*XS-;z)V%{EUCk(jz{9Ci6I&Oh3+DF?JSCWT|>Nty&jF&QXaU`cFty->zsOE zM2FPx1hpmlvjn+Mhx~6cUJ96@v9o^W?~$?%F4mcbC;pb3*BL?l}lejcjwz1YAx2taDdORJ~-F8tHIXAv}jkXQH}hci9qmx-+jK?zTjnv(T9T zT774uurr(7vlqClsv1?!aLema1!+v0uBs;?=QO!XPDgCLJ4f2I&}~@{mT)T^ zVdZLfF``eebEEa{V$Rt*nROglH47KIbrGi$Q^FZ#ZyPaGF}up0S}k={HMsFMTq>#(`p%r(hMV$Ad;;A!{Z8}=H-Hk`^CMpPA5pmv# z!ZBbC^e^$f!|26MsVM6vBK9gKFGSo99k(`Oho(&8>p!3%CF|Vst#Ql;do|8m*mNTe z-|9(2w|v8i5bh$vY;q%~LwTEP*SY1(8zvQUr&Lo7r0Jwh(<-;pc`x%-&qTMX+`5y6 zq;a&~s$Qka!CU-i6jlu;pF}5fd zV{RnwLh$;UW$yH5W<>TioU3)!kW(|<=}qtpORtAy`NpO8ZnrGr^q>Hz#daG2XHxVp zP|Z78mrPi_&^@_U>QS-v7$@hm(xoc>%$!{_(_I1F4H(T;{LL;zj^>#&F=6alcdk>` z;I=wP;#^?Lmmq1)>}uWYK6eH(mP67-oRe0$lyxiH-Bahg-OJr+r#HG4OWe*SZlmN} z=r%UG)133krHiX(V%}&rC&!W&IpKdjgZj6Y$k2pWNnDO(RM}KyU_oPF08a8_2 z7R1LFxeHE{Oba4a95Fw6L1d;HES29R7})I2)06qZOE{VT$w9lTmB1tyCXClC$A7q3 zAvpJ44$mB}c?WEFp;Hxi>*DT0Oi}>!d@9-MG2+y?SR|+0Zk=;pT*Stem=ZM(#Wp0R z!lCD&M9fEb>K#ZTwZP4H4y<|)%d5m>#u_RGtY-e#vuKHnD_TDq<|>KyybDcagBa~R z6V?my?=D7O^vpDzlLgBPT07s_)_@F4yrwspX4P;?{dd~jFrnLwHb9oD1$>$F%4Jw& z(3ul=;4{*Jg%Rh&;3c;GS=08r*!DT@!U)8SChsb*jXNI*Fe z&LNNw%hT;4Na#{Q;Ypat*4m403+J zf4GB2{keoe&}g4CoDB_5yW)=kk^kQO0m)hkeT>VH^D+b#hrWUW-TCKBWg+<$$UHq1 z@zu_lB4vE0TaDtm%v0>maB}Qhvkc2n+?`FCFk_)Ro8o^pf=VA3F^g%kJ~VYwm%mJf zuSQL!M~)~?d~ynB(K6?eBP65is4&#qPe5vM8up-2=%dhZmkIyb&X=axC7R?jD0pTy zXb5u7bMCv4PeOTh7mbdl~{E%+=3a7Dr^c^94ID zZHYKvmy{ak#S2j4Oh_9_kSm~z%y+K1JieX{jyOa9PpQwQ=OmcF*zz@V#3^Vs4-F0 z{P`62yGJ4?4-ir~Z=Xl=u_(KHX@$aeTz=5g z3K0tziO6-X(7eH|kCNsA_P8>N4`56x|AwhS_IR1&bRzb65pst7am(d@GlN_!G^lYN z_-hREbo*vuvQ$0)^dxS0^0m0(b~KCJ@WN$(GdDb>x#60> z#tr|Wx#7xEZum2}VJ7IZIL_^Bj$@9F8vdWViUY8Bl@R;;tl+iD!G z&ub}Yt9%8m;crpU(2;M0x$MYdcj~DT2V6w%n(9oAyNjF)xL(ER8>0X@b9SVmWViNz zCb7dmycRorL9+uEiAk#mdQ=~AK65$Olhd3pSXe>L>hU9ChuN4K9Ie2@a5tJOh69eN zqWj1HXCsO!2J!qd2EdK3+bFtN_z}{;i zf8EGJwbOAUZCWt3amNk)fvszkc6{V~kVF>LtI%}Foo{0lD0i@2ZHZ&Qh@A&lfMKE&jCcy!;c9W-wiC#=4K)~DV?|a3WK?1bF+pm8n$}ag>-)bWoG(|g~3F3 zCY#xo7|aaxThbzF+xYnY;`qpZ9LAu5V@LKC_Z`~rWzY0)N@O#sV&6b2ZKb+<)BRQ< zoh{^>JdE|ZbT3=)MPzctq5jNZv43E&n9HZpfI%yjD{M~sC`0|JbiOA$u-O_JQ}yMG z-5^3{?7ZauksV{Xkx^Kc_kdi<4JiAF-)oC2Fw5}yD3#j zklv=Y&6%D|5sc4TlLP(zs?W(>8XsRLh5PVza}a3rP%hoy+~j+keQ%5JZS}ovWR0er z)j!aWNz}Z;t1;D*B6DH}aLOol!@mODJP68qNZv3cvjfQu#YA#2v&m;L^cw?OOm9i1 z(0;RK?vLr%t&LSr^cYqc1g>-&X zI@Qd9Xh~bWxk2(4N*LjpZSlat;gO=8=-~b1ZCYaCG*gDNcwpqf!LbXi)L^oITOQrs zKQg*!Vy`t&7)%LjPnMjk#u`!qRW!@oLT3)?acF4)kLY<_nAkCKcwA<;RY+#QIp}*n zwH31&0+B6m$yv#D&6_Yw2Lr@c4BtPL%@%V5nSPN1Y|ut&1gYGY1FNw==7g)bYhr9a zx^K9yd#HzVJ>8cZ-0DS|K}#l*5V$=>8G6e*X&N7yn1BQtFJ1t70*XzHC^;o_$m-64 z&o@APTckn`tbia#Qk_fTpluAoRG(UD+0&$DPp;6Hv~Y}F+%Y^nCS%~WNv4O$ras6| zJ(ay#w(Icz9TOwn`%v!02t}PhpO)#3UP0uwT)s!5N!EoPDb%4pw^3YO9uy_ zHD_&34Pq<}4{%D4`yKHJ> zxy_l>;JRY-ieh&L6OkO9YWAnLlG_Pi0{BV(q;K=4KmHMx78)JGhl(XkTo;;)v0_UT zspg?Ridl%nOpj1QO&%_5g>0KI-wk_U{Tj;pYwx;5KD9ZKPZtL>eQ8Jq^e3BZL2*4w z&`C$Y_6oL^bQfp-(p_ODOk9Q4p<$i29kpbJxdHP`y!dEe=#|f$2qm%J~Qx% zY(AYxZS@vL_BY*|Z=&?T49>~A)rxfsvkwatn-6)bAigajVco6fRvm8BuwBCr4Ldc& zVk!B2;p;b6x3gFn7|JKp)}gU|2gmkJTu7p~=d?KT^$;t+C50J|K@pLq#!fUXHL>$W zk|TL|3>PjYpfmJ>PqQhANq;Rg$s}s4r$@_L_P{UxNDLbCh1X4Z=V!ofl0^t5zf(^c7iAvC!t$Q3Fh; zdZFf}$gfOp^A(qTI+soi7Qu=MLsW&MN2R6H69$P~EoSc6Z6d^cV`p* z8;Z$wX)Lo^zD*vRE;TgW`P3#ZN+Rc>X;2RmC9Zn|*RKn}JR^Col3dxSa`2J?WDuDI z_ldw-kpG3jOy0_;lV~7-S_|9Tt?^ywVv*f7Cdd=icgM%9Jcgr3kim5rydLC+hT=8c z*CR0BpuFlO9@S?k)|dksQ~iCIW*9^W9BYp(ve*%zQC23E?e{eXPSZqp0s4T_u03Xe zvJd4ND@I}v8j8s1{=ux37#bW%VJY|9BU*1BJd)DOKQvs)|rdheyWujg1V;27sF( zGf><)9=~nqOGCvkf(84{loV0B|J>rCy*tK7P^?-lxew8U1GO#LtCu{ekhtOliGF@j zG+3{;5`icBH?>5xTO6|Q`K&krg%!kB5j zrl(t4b+}E#z~K3NGtAd@5PX@WlDS-1(vZjss`WkHvcdwRgJU&^i)y9~0n*asKwoa4 zAH}E^HhY9UQ7RT|=sRr?K57C?U;^X@a=vC@C?owZ$R^(62EZ`0S2~%5(uE8mT*rN1 zU^x=T^ES|lR4T6+5}b~`4>d9LNo_Fv?f51LVTwr-qE%^kX{@xEYWYps6!?HC#X;OF zLzQW0j3bHx6oZJQH$$x1D&OA=b{$M)_4pZWyXY@pU=ghAoNwGz46r-UMrGen$Q33V z0{nht`XPn%vUPZLeBYkYk>NNB9a97a*HX@K?yC))Dh~o5St&k69N3ZsFdoO_6H@bV@9-%3jN@=47xv`k!TC(mUDx}H26a5U_qs6|+*RSl!kvNUI)*Z{|1GIQIFB_0b0Z6qXhVJMkQ7Yf2*Kv%3SBPo^ zFbqPO4=|nx6s0~ZrCrQf%Ig);<yTD1F?Da_XAq_)B9dk@RDg%rygM zw0$Z9iQd81q5d9pZL)^h+@@4aF?o=nSTH@lhY8Cw4bsHgBGy`~kWHqb`)Fa^lWzs% zD-kEw4vLoyB(>M9OeWuxC_?irHei`@*|Le; z?HkDSaLw;4fDgzy(uv^u@99uRlu#l;bOuP~>#Vf!NeNg}`e2+@>r&A(H4OA;w?cWy z^lb8)qsNAp#(a7(Fp;@77*jHc>j@p0x-oBIhDtS42L@q{AZ%8wExH5Z64+16Ud3!U zO9!Y`4UpjI&1YK)PK(}z369?Kbe4=AHrueYtEyI*RhCK&*O~+tbSijOX0YEk1ZFTH zdU`U+3|HMkE&=W~!$ZmA(Tg;Y4L0{Ez+qomGCJQR+X%JUXoLMr?>pLBDbf2lJYH10 z@9nhIuEmd8fx^U&fnuTH%4%iWV%QxUNHB?*|kITSWHg#g3Mq9AC{b) zWW~DRS!G(anZjQQNIlr^feF5LU*1eLP{b;Q&?vWpRYgIDX+MXpZdyga8+E-hdySz{@T&5?s1;RN4|fvVX^g+QyOG3@Pc0M*q}A?WCX@^}zsU^&2}V zxlndmeTf21ww!Xwd;%0TLuIx}u(rcElt{u>C3<*ZHQ_gVu=@9c1L(X7Cu5w#lo zn;*R>vtnUt5;mY7p=K?bH1s#)YJ;3xw^h_$HLWMLl6&HkR+_UN6st8oGK)5A%S16H z^nuH`Ggc$e13R`y0u`mq(&X@oBgJ97+vAU(Y!fLkl1cVnx)WSwwDkbCNSGr$Rt~DH z1u<+DU<(EdX-mA?TlF7Qws`E~`f@mX(7Qdaao%7z+n1`!i`49TUs(n%HXWM}`>z z%-x61Z(lxsX!&q+2V!=N?b^E8;yAOp7C9AA>J<>V9qND-HDe7Wx=14p6b*1jcNTUz zrFUr~pD3KN=Q5%T?<;v{@gjn`t_|d2vMb_jv)Ge?u5b0_hIn|R4_h%#)LOt|+7>LW zGYhH8+vnvy1mjYXRPY<=Z~S3tU6)~vJwyFCMa1ex^N})Pm_FsVOj3AFG&e{PnL{uQ zdPg?e9KdMh)<>kl?R>~8YOg!Q1RW~>=Q0z4>!^`hCAs=krd6ktkNVIo?Lr`34cjHlgrI*g~&c)E;dg>19r&>9AJ z+BY!cP;Gt_3_=9Hh0EXUK}6(WPcT-{$)-jcc+?RYB&-?bez4#GPUzI&$!g!i0j5OH z^jJd_c>&9UHZgJtObPnROdl@c3@KBPkiQ3fS6GJuFz5eVtDxLq%qW{mE@H^C$wf`> zf{ojrdw!avd&rD6K7>NUno&@;<|aJaDpdif=* z^C(;f>g}fu)JqAduZ59a;G4h{GP$M26x&#=c=m@W1tUzeGQud?&y9(%-*N(B{>dSZ z;RaC2^ZM)pv%44Tvr9`mOdjhJev;29xVq(KSfLjl;oSrKeEXN#4<_=xLz8-&Q=f?C=8ytmG7Ys!sZZ`S_3aqN8gPI& zGEvhghq$Mp)=rO1*o>>;mYvbT{c@)4b*{~)TwAkZa=rLM5Mftih|tzXEu#ez)QgcD zDlM4JUW{)K#i^B6cA~ojz9fHOlr(oB+qG&z!fj4Ntt6Kl z>U(BX^94u9fyv|0LC0{?75jwVFogis!WYzCEZo5F9N8IZ|44O3Yw6a^fXb8dDi zDs=fgU??Svkyw7cMs`^gT>5YW)<$KQH?sw^6dHV{i0cvQBGw)lsd_S7Xw5M8?SMVV zKiRX692y@}W^|}2kQtQ4Fg0y}6^@4(x~^a!DvG5x4tYJ&S5r~efP*zOQ)o5N#P z3hEU&HZVVo-H2PN>_A`}q|8-fEW=)_7d8^usW+t6EoN&JmdE0bUHCU2E2X@e$p@9)BJw!Ap5(?AD^& zpc?#(5!zPv9~|8irx4q;8S8?#{RG)iSqiF%T)`=^bn*_OX=bqN*-ZZio)JNkQpdp{ zQHRo$PM`(r3QdaZaOqE9+YlpU8V!)xLJmhr5_MuG9134x^4U zHd?WK7{ZwOrw%OD*`|MJg?3Sk*T?G^6p>Vu=}(25~4vaI!G0IW!MjbA{fUB}#+A2tgVnQY|7TE4E`pg*5k@ zGGc7HZ}d?%NVV{&sWn+qn5+Qldv$)vO408t^qMPSaz7_{b6|3HLJN6sgXTR`j%TF6 zWtaXToIYXyiHSj>K`YrLYqrUwx7UVeWzEofm(sIy*#Vxy7<_}6%)$@=J3J43geSC) z*bF7n;41TrR0e9}HQ_(VhG~H zNJ%);ZbK;`UTxkmGJn znF=PoJYiHYkjNVVE&^CS)Rt6fOSsfE?6ojp;KNksrGz~91Cw8w(d57$7CUk)JO1YP{~IN$@zf+=~QQ^rWk)W)Io!>zBa)Vg|u9- zW`XK3+)#$)>FFv$1~bGY$)0(##$}RpPk92*9-5wEXF?|A)kaa3aj(of+DYvjmwR(1 z9q7=9z)FMk<(sVa*k1COJOcxwUP(bRC92^`_0Uibd7S1>Os+sElYZZ%Yrmx?u8_Hqg$!iDt=J94+=SLq|(Q9bXJOM30 zQNenv4Q1Nu1Z6_sQX}P{-ArZ|%`J??C9lL*4BQY78lcFO#6Y1biGgBM5(5RNBnFC3 zNemR8k{BpHB{66-^m*R9Ar}V3T7c8mMmoLyR zZV|AIU=r#B91T+#IZt@1cZx*o;EyQMQ#MMn{Z4HAB zcx2!CBVN~K(Zl6OZMrKC;+_z;9cupseuZX+EiX?j&|b9FaA*Se6!S7+aD8tSl0&Xg zm{c&KG2YAclY#XqqitJgC*&DvA@(aktRHN!fEKT=z`{&J39kb3z;P?LQDeKTwCu`* zx&%t1IL4+3ZID-o4%N#mpcpauh7^i1HJGVDahFaNjbu|t zxiBVR3pfBv5Z)w~>p6iN1li4L+La+#q;b7a`TGx!@*)5ir;IVXagO-vtT{NATgxal zI7a$5xF8 zLJW;yGK>9-H-4wpw3&1ar7yb%Ppk~r^%+w!D4y#`Pqhzh3fv74y|hrO(9#@7 zPHqXXvM)B|r8#q$Xu2HijPMw(k$ORw3p+klJr*(T`RwjYB1bN0mp%vsg$Wt+YC%e^7#7qHS$CSCM zUbHdIJx2qibbO^3|OppwNm=kw^kKvTSIxzxR0 z?%i-As+Q3fz2v8G8p@?0g$<@TG6wBcRJ(>9iqHu~XqAS;-@XjShrfeZWiq&Pr3^*N z>@J4-6wYpW=8Ub9vRtX&V^sOS2K0!^F37z4Ez2NoE&M^ss>~;L<-E#>K+&J zq0w3cGt@UCWAi|MgPygr0akB>A`99Hbz3YG2#Jjl)^C~$K^Eu*g-vR`RZA%a2WZHX z3(x3=<7{Jp!{B*dD8Sk(hXM4wpoxj~je0nzr{1KliS}^7EH9OC zd=u)wdZciIEJ4Ky3H82kqEjsCX5#5_LfeHi@Tw?vds-@>aHtoX3cO>%dl$g)IG+`J zGS9qG;kPQA>EV@iVJx#hfO(fl?FRpW|DD`$#H*N=*QGlt$^ZIsFynclNfeo0y(CzWIKr%45x^>mM zST#Sp)d+N}5$IMgbam?*{nwriL+V2Uz9k|5LBY_=UyhPV8uvHr`*8!*pS3D1Dh#%G zr9{&=kWEoR!NnV_lV)N`-j=||&ey;-z4iJq>0c;#8)#*HyyWm46cRQHd})o6KN7;BxOq+U}ezqx1l-ZW%|l^NK8f5+qHGTZ;avYUk{ro|+m z8a(cJRc{1EJD|!g{~$=c-+_P81M8aH4Z)=r*{?{?y7lXF-FRIN?-}?aneS0>y3=+| zkp+?ItC(o8T=(@3%DrPSLFTPFh&Od>+sF(>Ui`NZ5;UdAo6-xDqH9Xi75DJ`eS$V@ zd7Bk~qYCPpB}Qt+T{Se{za=eF9X2x!`F{s!Lu=8H??rJF$j&7*`Wg>+Eb5;XkvrGv zV|&Vw*RX=fUSFm2zq4c$_|Go9&5KgG=6SCzOnNCt_Gx&v)?DF0cn|J+)=cjFAXi}LBX5!DcV7HL0+&8`MyPH?9Jlzuq&C^C zt@I3G9sK_hvTN`RQv{>G^%NCV-cLsYu)RSrg53P$8MVJLR|g{`tgUPX1j9 zH#3TlX{^FaeEPDmVSA=i6Ocm#zC>wt_oNEe3BIYKzN~`JG(d4vN}m{y4Z&5EJ~)2K3kzrU^;)CXkCvwBxe97e0*S_yAU(b0Jk8Oo6iIrDO z`kD^EfWt2(nTKD(Nyehrgl@2{xQPVhmvIuY@@t$oAf-DN-#RT;o+$IbR7X^PH7609 zeRbp-_YL7UI&Web^O>L@eoZH#%1*^*^v3vQpI|z_;H1-&u^By*&acLqhhOzc#KPCu z=_lmFJ^bR4dH4mr?%1MhroJKi#wl-#TBD_FIvYru0p9rbR2m)%Hw# zmNVO)W6!nc+4JoMp?bRkV^jJBqr%p|z8Xx&M;(Ged_hD$`QgPm{H93Yaqz7YejLPq z!oC+i2cIvQobC$!p75~nd6U57;L|3P@gvrBq_b7z#gKd(%Fp27qb8H_r&tR$KKU|) zbdGV(>lQwO5_lZso}7Pj$g#>w(!up2RVDaUg75QERSAA|34XQU-{@flr2@;ZDZ#H1e4nQ$f78veW|iR2 z68x`v<68t%W|BQ!)&t(N3$C_7yKTq(#;o;2leDpY0t)%;rwbmIrKu)!h z9(){pOD-rA_-(nKN%#wb=qUf>68w`(((6jXKYE9p*?^Vm`c4hbfmU!T-0K zFhoNo`2D>In};|L!?C{W;VQx3{|IOvrvC_z>6D|D;OCchnDV!hs}vHMPFY(Cew?Yp zl(m)Mw>lkuUcz&%U z^dI+1q>2n6==-mXH+F_e|9DBs)KH^k4T8R*7SbADafCP{UlDR1EdZpf3-wyowFrkY z>I;PobIuZS90?yGJ~Dk>!v_JUA^f<8PituMA!vm#IXRC*N%h6RP)gMsO5^Lgj87;% zC)BOJDj4e0>8r^LNC%v$Atg-+!l90EmEt$1ql<#qrXh-wFuEeJU&FIB#G8geo)9MP~`!%7WjYq&teMH-%_A;0L${2dyu z(vV;HW&An~`!$sDMf^4$-mW3PWJ~=08jfjrM8nH8yhg+8G`vy6TQxkY;hh?OP{aE) zd{DzjG<;mcCpG-4hTqcgyBhvb!=GyS3k~^YR<@g8lqLL=hWM_Jgr{maL&I4bF3@nX zhNo-Ts^Llv6B_c1t}K5*!%Z5Vt>LhS=V~~n;e{Grq2Ze}yg|cvXn0h^yEOc;h9A@L zVGTd4;gcGEO~Yq2{GNtC(eURQzNF#rHT;W)F62D>Rjy%`hI2Kn({QPVjT&}nxLU)M zh8r}@Yq(Xz?HcaUa8$#?8eXE|)f!%>;Y}Lerr|LS@7C}m8a}AuqZ)o*!!K+24Gq7e z;SV+ZKN`NM;cqqkqlPvF66q7waJq&y8rEvKNW*0swrIFQ!?harYS^#gkcMYzxJ$#= zYj~c9M>M=#!#8U9Rt;~_@ZB2Tso{q-ykEmlYWSFjU)1oc8h%^D=QRAWhCkErHyXa8 z;h!}OL-i+}$~3IhaE^v?4NuXqLBn6`>(C`Hff1}|aG_)hC-_ta#(r~_pi#2S}uv5de8fG-i zYxp`1hc!H);rSX~uHm&B-lXB}8s4Shy&8T(!^brIl7`>V@SipOiH5(_@MR7EtYKt| z>gRL~XKPre;b|JSYPd?nw1xv3o~7Zah7%fIq~R4BzEQ*LHN08F+cbQShVRqx!y0}} z!yjn)7Y*MXRqg+{hM&{$A2s}ehQHMCj~Y(JhLC(cTfVjl zO_g&HTTYgDg@!k2_z?{s(eNi4{#L^QM2+^6A{8s4noT^c^9;TJW0R>S|R;U6@d3Z0hq&DC(3hO0E})9@S(FVgT$ z8XnW|ehojT;kPvW7Y$$5(1jw)`f4;hMZ+!){~u>}0#`-#|Brv}2FzTRtB9b8UeHin z0J#_U6ajHV#U(Sd1i?hymr~0Vx6+SRZk4H(m7mnK)YQt-)YP)nMAO_;TimijC8fpu zz1}mglj!gJd;EXDKacWx&wFOx=ggTi%bg2zJJP;%2%Siuqp#7mbUQsrzo*x!6Bo!* zZv>5}O=$=E5G|rl(K+;0x|x1XzoWlVc>^K!)u0KqE$u;v)2HYHx|VLChbi7tnt4NL zD(y|j&|s^Q^cA|2en|JzQ}i0WA8$;gp5b&dolDoy z&GaDso?fR;ym2?TBaNp`X$SfcEuv4+IrLTf9^FPu=s9|gI&iB;>a9ZWqfKag+J_FN zGw6K!4*i7gqo?Vw^fvY2jlR?yOH*hD?L`ODC+M?u5nV+;rhDlrT25Vf<0$pT&_vpX z=FmJknogq&>3``5^b2~7UZQ_eH*U~Ky)|ef+M0HwxpWkrN*B=ObUWQof1)>NAa1Qm zeNi-lwxFG9KRS#~qA$>8bUocqPtZy=ta|Fv=Cl)im=2{+)7R-IbPqjCuTp!Al|P); zp{X>BK1j#VV!DW~q94<}^a3rT!MJ5;jt`nh+t3`EM@Q3X^mV$1?xF|jck~9Wj9Xk% zUoF~{cAy1x6#XxKpMFJ8(kt{94fR_2>(i#R8y!N&)46mF-AoVCU+AB-a;%lVHuclq zbP%0J=hBsQGyRI5q*rKY9Q%hR)3)>xT0~dSkLY1~j{ZT7+E(6Z+LUI}esma}L>JQ) zv{oG}Pb1or=FstUA$@~xreD#M^a{O2L+`Wl*QZTsH=0XF(W&$x{f<_SXFt-Wv?tA_ zs$v=<#opQbO;x9Nv;5B-r|rFuiFp6av-&7cp{adbLeN1p~0 z4QOQLuSr|b_Ow5Jiq53V=ob1VJx6a*Bhkv=l=h^#bUa;1-=Lf65&Av-le&|vyftVu z+KxU#httV)30+CI(}VPT`VVy{TlF-f9cf?s1f52g&^2@`JxbL5tMU!b;+JolPv2+G~iLRhKX$ieZ|DX}6R()}_ z1?^4q=~HwLT}e05{qz#OK|`BZ`RmiBv>VN(6X`7a27RCIq=)HG^ac%VYSj}(6KD(C zo95G}=*x6D-9q=%OY{Z}ZN}|GThb2nIl7p>Pj}KY^a{nV+?wO6HSJ9Y(eZQ^T})Tg zEp$Kqj{Ziq7FPaBG>*2WooPNDOJ~rR=nA@%me7mz4;svSF6K@ZU%Xc={-S@p!yM4Ck(q=j?>{SRG2*U+u>I6Y7Qp3`_UbS>RZ57O`Hb?VHp>WiT9G@W*%gXnlV zi!P?C=@;}cy+Uu%&`hhoTC^qYKy&FRI+ZS<%jqWiIXz0RQ>~pry|>rjO7G^clK~ z9--%HTqi4E6753=((kJLNx`eKwTj|&I3@xR>J*;}F(Z)2L;_nj8@l`+{r_azg z>00^)Jw`84S5GTXWm=!Mr1%wjvz|xja5|YTp)2WjdWv46wq91AnzR8OLMPMb=(}_W zJx6U1Sb4%|ZQ7BJpik46>1w)}?xz>%?=-Bpl|P2!Pjb!me~?b2^XThz1KmN7(BG)z zK`T#f+LU&t{pm0|g}y*n(GTfqdW}}?W94s1ThcZ3DE)<2ddQkTk>W8A=6a5xGw4G4 z7Trz{(4XjE)ac8+G?VtFE9r;yb6V+PYq`3#A#F`FX(yUPd((b&03A$c(0TL~x|*)1 zAJVOK7cHUR(~I<1`a8Atv)Ug{tI=BYKH88rqn&6DeURqU$LUja3Y|$8(zodvx`A$^ z`{;3co?fT6N38Z&rSUY2_NI@~C+J+dl&+#%=$G_c`UAB;YSkA?qiH?biguy>=|DP^ zj;Ax|0{RABOSjU!^f=BSfxbwW&^PD``Yzo-H`8r&H{DAQ(xdb={efPlf6b(zSF8{gQr5f1p?C zi2|$sEA$`g9B9SeG?FIJB-(_g(_XYM&7;HUWIBV+rt|0`x}1JMx6se%m-Gm|K!2gv z>7TU9W7hgqr?IpVZA079&a^vykUm25>0mmN&Y<(@TXZemLcgTn(jRCky+w^dR=Xo< z9om?-rrER)9Y{yh$#f2Vg}zNU(Cu_TJwY$fG8$B9wW}IU6mf0sW4Wc+P}3e{IbUq9 zX@lrc#>cZfkrY)jxGror9P4rU{c|W5EL@a-V)3306jRp?3=6BO7G>XQG zSiUZ8O7Ev#X)iihME%3)6O2!!a~WSq-(-BHi1pjZ_(yanr+-O*qCZo6k=4Fv>Zdv4 z{rLM$F+tPDh-lY1I+4?7vOI^rC}RF4BHFW(e!%z^mUq*yMdUq1&xlz5Cr-b?_@C4{ z#F}o1$R90Y`C2rA)01c>;~i*s`T%`YM12KxEPayBrt|3ABIuNC`?G&*-U(o}c zev;)g^hd@^SuUfuMC5S{gJ_S3))W!1!*V0qL_~cpXnPU!b>Z|!86QB0a{6dapT_vJ zbRMU_%;_r`Uqjb3{xQp+(l15Sdw~AP_(gh^{!VX;nBO(rvZ{#ns7`A$o-1d_+jWyzThn&2T*B#x>2bz?V)+uiCStjA zs*gY!>lZ?+((1IKi2D4Z7k|gXcu(4g(+gNGq@zU4KTgDYPp9)4U&Qho^c@lHc#nP} zV)-4Meu(jJ=~+%c&*?WA|BJdtTFbjd)L%nHelNX`@uni`xu4}uoZgl8WV|2CxwKG3 zzl;=PG;K1=vpM|*x`@+X6VZ;mGN6F+eTaU1c+F#$}Cr<(IWacnPoq1E~35ZB9_Y$lW=_@V*a5b+CP#$E@J*k zBIchXrfAyBjK3;kxeX$g`;cy7d^gKq(nIuHdWQZ$e-%+*8Fh`Z^6Jzhq8&A9L)wD2 zr@d$%9YLR_v*|1JZMuPOr~By%dV!Wv+gPhTp){H%&}Os~Euf?5BszyK602+43YIsB z(yw$2<9q2*#!u4A^jCUaM1MISxAGb^T14Jjv>t6pQ)zRWPP1rF5qbNIf%tuFmY?MG zNpu?HFR;9TE)}udoAg7*KcTzm9(qv3{72~p`V0MsI-juSt0rRoVrV?APkkctHK!eE zH=0Wy6EVKWiOBa9EoOWc%g@o5MC4sc*U z5!<1G=)&~{%UL4wcB0)Ff0PcR6X{G5^UtC48GlWT!10Xb&78iKe#ZFMEFYpr8UKOh z3-k)(`N(>sdcxISmOK*aoobQt3kSbmyLW&C-T=hK%N ze~aZ6bd895j&b@AVkJ$x#_}x@_1Y#_28d{XC6*&-b;j>wIe{iJ-kjz8X}XAdhI9I4 zI-9;l*U_)(1$v#z0}7-))o46TqYu%?=wv#ZE~4w{r}P-TO8=prr>y#7Xnoq0wxbWy zfpiR=LKo0C=mxrj?xn}YNKLyaHrKQ(^mqCPwNJFB2hcDYPHTwB6DPLRv=qjh(3Xs6 zvfP1orw`Ca=>R%}j-XG9sHa#&J#!eJOJAX{(lqThmOB^p6%(m2|HCedcJ6>Ud5(jK%o?Jr_IhO#`8PGEd8UC8(%`X=Km z=~l*f(7lWwq~9}so?d7C4-x(8nq;lFPAiLOSCok935++QO=t_6LEF2o5MUm#-n*BO6{uA%GbCnDzGA!7dhj31;YIQ=ZAmoi>P|6n|DvXv)9 zM4oCQ#zPEE;PfQghVcxVO><~J5$zfvBHtLs$I)UsojynB(ZwQ`UnXMtb&PMMTRD9v zr+>rvQF@B;%OdiWvivuvYsH9T{eneIuT0|@kEco0M_Y@SKT|}zav1MLAE9})hz_UY zL@fU_eU9;YbTNI6z9VA(bt3B9!T4_aH9bU6(lhj;h~x{oe*U)wJ6A|<8 z5HbIL#t+gHoPL(mOBpYte=r_6)yfkhB2P6D{SreHI6aBBVLXFo(;RBouzW*4PX$J^ zT#MqChdI4IZA?>X7VShIp?MUyUCrfj+sSkqeU>hyi|9uB5#3J@()08(y)EMYo5N;V zl~$+nJRzBWA8kTg(9X0Q&7}qOaXNvT&pkoD=UHAsSJU_D2XsF@NX_S%VEOM^{)d{+ zD?!|RJ_(G*hLLtBQ$Ou2VxySPA%W&|NMK*ahg0+UBZ$vq`9*3zX9V$OEU%<%=tgQj zZv^x0WcdsFH9bU6(C_GZdYRs)4u{q5Dm02F&_*wcO)~5AoB2A}RG?y08A#?nv{;Yirt8x{L0i-_!H-7kZWcLCxoQAWsn9i%Gs<8c*xf#?*Xn2j=U>a!;B| z3+N2dt7)_7T)L3HL*JvDsQFwDEcX@5U(+-62UpdZmK^Z@;ao}k~+oAfU#V_wEx0If``(ij>`8_~wJ3++z( z(0;Ut4yTXP33LvfOPA7RbUocfzY?qCxp(vkJx;%;=c(Oo%^yHRXeAm&YtSU>qb+D_ z`XGIn=F>sceEtmDH-_b>=w$jVolRe*Z_o|&L%N6Vqd(9K)EZ46*Yno2`(0(+Z4x&$sc%L_g&ZKkbTDpOLOh2W&>6i2%JwngWALwQJ zEB&4RL2VwZJ?3+V(5^6+!)bL|llrOoJR;1W#&Rajra82L7Sa)P44p&g(wFHH`X+sw zzDw8BkLVV9lAfU#=+E>Ty+Qw>GG=7E=rn|y&qG4I8p~cZok>he1PWRa%|a zq4j8Mnoc{?F0>czLx<5(bUd9%r_pEWJM=yJ0sWZnq+ieydYGQ3=jcUxg22!3 zF;2!uF!j(#8cmzf7Brn^(Jr(*eTY6n3uqx7NypOX>3q7FzD8Hj)pP^>kZz+p={fon z{e@no<@9eFSjFlGH?2&o(wa1mCeTJSlXjpvv=_~#1#~DKNoUeIbRk_t-=^=-_vr_8 zA1$HBsQElDY~LSQzDPYdXUcZ3LTgYjO{6Kb6YWZe(vfr=eTq({&(QhwCAx~fOE=Pw z=ytk`?xhFl6EG0-YOP-=txBuYdbA<+(`Gb_cA^95V{{lDMJLi?`YfGIU!!l* zcc}RsGHeI)Ib?7r=ndYS%8ZJ1ZKpNj@l4~?bw(H68d&89i@LHaO#oKB#{bUIx` zm(ulg6WvL_pkLEN^fEP{dxqEMbI+h7isO<-(FQb$HlZzO4mF>PhCC0m+@C&9C(vR# zotn=}!*WYmUPm|5J#-&ELw}%`>8~`XnzbImG@M4#Mzk?)MqAMyv^RZ(n$KTDJIAs7 z6rD<+p^NEj^nGeRmkrB*#q!tm9Q}!2p`|nk@14x^1dXAwG=(;y?P+KFC>=lt(_wT5 zokbVZ*XUZhf$pMv=xKV6{zk9UKj}ZzeEu8yp$2aJ%X-zOb!ki5hW4U;=wq~qj-rp# z=jc58CViWJNI#)p(?j$)Jx#CEoAe)QuVJ-6iq@dDX#@B96HoMD$~hh(7Kk;(lPR=;d?dao=>Ll;d%q zO-#V&>taLvBjSA}Zp)hDc8@9EcAA>)LH%g1*$ywQLsk1E)xYh;{C<|r_M+U1WwX5~ zXR~a!8|7Xso9#!rAIrJ4fELoB)Lb9TKau5PI-Sm>bLb)w{k4=Xqs!?^x`wW!8|iks zi|(QOXbC+`kI_@~Ed7yQq*rJuEu-c1Z>q`XH)y|;22t}l{)l^6u0p-E4y{KU(q!tV z&1fr{Ml)##noV=@1((!a6ok{1=xpX02M3>TKbU9r| zH`0&j7P_78qI>8*T0#%gWAqd~OMj#n=@nW^%V;_Mn`-iTm26KMM1!gMJp!0sg=H_T zL+jCo)cpJo^P8XF!8FD*X$P83b7(J`OU>^W!19GG52fSjL|ROz)0uP*T|~{#0g-PR z%ggCXx`vvc17f}{EN`c~=pMR{9;2t|S^6WrNUzXRT1Lz1-&AvOd(a>nOwG>`(Y_ii zdubhNes2M$H)J`P`e`%Til$NX`wXyL4$Hl$`S~N_=I4(vm+=BxNQct#bRsRL)9Fk) zhc2Q^=`y;UuB2<|M|2C_PIu8gbRRuNPtmjVM_NkDXgU3x%8AL`Kd6URp;5F3tw$Tu zWa_8QXe-)*X44$ni<+O8qTkKWOJO17L#g>a35ZW*xtLC;GwB?FSD{g~2CYXM(q!tV z&8Yc(3&@woawhFSvuO_PMf=cxw2%&^Bk5Q=o=&92bUK|Y;yP#{T|}4CWpp`RM>o=s z=oY$%?xQ92Fg-?3(Tns7Ev02tlh0w%J|_*L!PG;mP%o`R>(PcZnfhs(i0i*h+JR=% z9NLTK(gIpYhtlzMA}yxV=}bC@E}~26GP<0uqZ_IDc{bW>ex42YNW7t@?V~01Fg-?3 z(Tns7Ev02t!?myEbJ8FhOwI3|!1Nj{dubh-EMnXFsrh+0UYnnX!!(KGv$sszL6qxX znj_-6z8CEy;`+WH%@uK-UqA~*9B+owks_}9&Ck)H`8hg{FB2sWi$&~r)9FmHHh!;` z&K2XaKhQ-Y`gti`CSv`UQ}cUVu)gMT1hGTXk61tR`!=v%@8~FFefEi1k6%Qzzmk0Z zh<2CA=LBfyP7g%;YRLUzwC|+c7e%{T%6&n!r=#3YLOaaoyQBUp8p^Ht{s{HgVY!}& zcC=zSO+;O}EEkAqS24@eMbx>B<>eyk+|KeY5p|o_>!|Onl+o@exn4uLhKTmpW4WP- z^=QU&E76PX$Fh0-i}f1H@<S~|630v!Ha2en96Q>wP`xt0 z<2bP(Z)~2HIAF{eEl~oA|9->U&;fb*LwXJzdv|>3h%o~hvA&@0?k}xN96fNTmFNHT z^>ugVsPLt9_Xe%6r~4nH<`>o7JH`CUx_g5ec|-61mO86p*4NPWFBq1W-(MOptEt^t z)|za63EiCq{@(Ip#Fo0KQ=;3v|i^87%+O^6V_r@WaxC~ z`4axGSg*VXs)3mLQTgU0P%+;rl|C=ua$tvcPYnK0Mdo;XfKDlODsw!nZDatva zV!h7zJKIgpUuwIxz9*ktE7X$&{88)i$UXDPHGtetQa@_GhwiC2xI(=+b^TlKn0xZI z!XP@Ul5svMj<_dZ737m~CF2jbrT@)0>z;fyu<~-=R6nYHGw#XP5c#~AN%F}tMfJ-P z%qQbo4Uux>Q#la+_qF`)^Z(6!+b|#g(=hDJAIbMW?H`|Dri$Aw8|_QR64E~Ty>!*S zW6WnJ!#^HeXY`w@N>*J`l6yrJ^G!s)4(+Ubv6!y%$vq?d_wUb84CY@jrqz#{cH^G; z9>M`)aD{=Y=DUU$73n?BEG-rtt?)yMxTUlZn&Z7M%?O7Q#C+16|MSMtgK^4*)FnlCQKrgcJD{iyl6 z-qXIJm~Wp<-Fd`O~bHO&+WL?~h6?V%C3u z#$rAX#!Ct!ZSlY4^WcB!W3>d9!9RZ>}-9U3QkurZP$0_5Q72+P1us zS)t3imZ*p8_?B9LcVzo}|Ia9lo@8qfQeum96rCJWJlRn;C8M}y)HYk~pppL>sd+n( z9NFGcw0Ov8*V8KhdO_PZJxlZMyEHdtUwNy_Bin1+s&|U+?AchQsCwb9>-PM`X_#Ic zuj+iC7Wb#4Y)*RMahuO*P=2uEjkL5!%AK7@w*O@FZEv@-;vT2Uy~(z-wiZ`Qjt`mT z{PW1-q4qLuv^^ueta!BMU0krQJeW(^;ufdP4f^qdcGi|A>(;H*9$dO9B&%(qv#4v~ zprNA*+n1${(+dX`WL&lfZVTL1zHUd2l5VA1u&u6kwN>bj@}RTZFNJ)z{gOM?=v-W0 zZ=^fdk+PvM*Z=POpIv{!o}HUq_}r9-3%6b@P5Wv}RQuVv_RhaxU2*nUh9lduUDQ4x%dTjtGQ{CMf*K3tr(f^>%jH|TDfdyuAK6^9+hjv zbx+$glvS=68!5L*~V^$Zullxol?sBbo zOp$GYZAmqImBZ=RJYx-H4f{8%H7(j6aM-rwMBvpUn%BM#BYH~58|~AqS81KIHEE+3 z=dEL_>nNH!E;LKV%I1#vchocMmKH32Y-jnp*q!D3@c-FZm)TlpR@8cLR)Co+``TH1 zgQ8|x)dzMfdvcVF&$z7EENi4Xv$T4b4|Xd%GCC;sPUPId21QE-Z}|PlWUcgr;s#IN zZlIOwQ?xjHg?SDf98&0rtu?-0mc3~kXA9P<)!TWneo=!b=MQ$Tj|`T$USXL{$h&y3 zZGQD4`~1a4j``6;oC{tpubjL@Pb*znZ1cWa9_-y(Zg}ja4*Pt2`sI0*x0VNac3l6g z(wrKvmWOz3rD3+2Y29n28E>R%f7z}kBOWpx05_#__P0arscV z&DSC;5OuH4lQow0oLu(ATE~(;cJ1oh#X~yYS=-5FMQeu?dN6O_!FT4(MXW_uQ$+iZ zzY~36Z5AS5TyJZ?6YIP-C`l{bS8PkFvQ3M1#%5kS>!@Fpak;H8eBhA6hbASgpN}K) z_R3RBZT6zk4-X!am$=?_H7GFbK-lLk3w^n^+TN_y6%Js)J7+v>5{U_^x^8cq#({9`z z^`CTSiPoS^SglSQLrfgSbpJv>O;HTxH>itJ&<1Nv{x^{{*&I}+HI|G!Q!Fm zWoe@q7c9*^mRl`%NRhTc!@kny_r$f1?1;14w&LmmTH5%hZOfj)d9(O-nypovGVfZo zS6cH&WB#gZwIzK6e>?JGd3Lg+G|Ul()(5Y(cQh{8VpDMpFE0JlK5~;*2j`#Mc{p;~ zv))SgoU~!Y)N-v%dq_{{;%(fnJXYIwz1s`hu8(*jzC-uIwDQ_%^Kg{Z8dSoZvDpvF zG1291yfQ7b!kk*2=zr&xqoK@O_5V1phx2N6&%_xM*qqsr+8(r#pT0 zNQJ&Rm0KfsW_xee$gLHQTipVSBC`G*GHso`Y)X1@{m};(Wlfumk&eA}T5-mcT7%&S zan^O0lslI_HS`2N+&EEQ#fxLp#EinwtZ&M-xot1o9ZLegD9_yfMftk*!%CdkhEZ9z z`LZ2twZFs?)646vlO=77^Yg1_W)$wa)^4tG%{l5R07F)Y0D!y9Y0gTX0&VjY@bStfw(J||d3sK(hF5t>`W%;IB zSq}8!i6K@GCLXl<>gzgOb)d4*fA|GzNk`c zO5Sm^rR7_-ZOt~xHJx>)Nnv}MmdMs@e9$pD|C5Zu=b|1SEK56Z1hn06WO=i^v9iTV zHrLOJjrE#sUbb0AS3LSb_P^Z!!?;>x?sLt|b~W4jK+TZMqi9FFG>K&5UpeoTTnZle zUb-`D`npObbIa=`+ZrU6*c)6ZI$YkYxLJuUwSDHM^nv*o2G~oS=GkVUIZydP?Y{g% zjGml_3kT*eF2ohnV2qsy{+qw3y|;E;k?qBI%bm%%_Db<)eOA7%yKU9}OZJ|!7AG%E z9fEOa+g>E4!>C;{UMR9RkQzTf*gPve3)3~3x()kv>82U$e!K3NuEn+M>}gf-e$Vnc zx%)5K;(R#2R2$sk+T`Q`*EL(Uyv0LK53!fJ><2SkX|Lp8$|wm;zwByvJipSBpjfoU zQ*H2t)-j)%gzdC=u|#t$Q-Y zuvsPQ^K6n@g8r>VTI9NC2~UOjrFF7IWwk_(R=Yl~o(>Mj=KCvUCCwXa`!=XZc57Ipu4E16oy?iPu55+92v|DAPKJP6)*N>d)nFn*MoPyp7c(9>AM%J*p8J zqwnjAMfI04(WSd_hbcgBfLnxtx)yAfC==mMdsk(fne2Bgo zH#S1`^SBQirayukN*;Z4G(IlVE91kU%6ea10fg&mxC>E5KVBJMr>!5yji0J|d`tZ4 zz8;1ZkJ5M7!EHG`4O^kQJ_5ZQt@mz^8=3lLWUHyChvFud{(UVC?*`c=A3&SG(np|{y?QY^e4qYvbv#f) z{}m(RYr}?Z)X--9x2~o&vKjNxxmcXAWd6rGk!<6FR>Yo z(c@({V>eR&ZZoE1Ox&;;FJ@}mO`EX_H!!Gc6r14`{O?x8J_zYRb zMH-)@55`9tiCEhSk;XM_zb7M&!MdhB6=_6bfr*iZ4;4KfY23gVoD^w%i-9>A3#8-P z8*^e8n}S);+_a^}6>O@uON~LvcrfHr<9YN_=2D{wJ<)Ed@haMxwbZDLIomHaHlnX{ zb{fagvhF*Li5MukmyNv`yLp$5-!RSwTs8tg{$-;(<}A2uJc%tm@Un3M+u^axMmbtG z=(2kXS~jwhO>?)yel<#7d=r2bmlsc=tH;QTFR&Yql@~M68IQ{gd6vZ!@?uX4)}a|* z$hTBYkr!1PYuZ$Ku^X+OCNFNeaDz}@yo*6OLtZ?9x}T93v#?t{D=(Iy-Shh6MF9rc ze0lLk9qh#NVkUZWp}ZI!h8fSGRGV$VU zAda8%A{a*nTytygMi}ERd9fQKIY3^F$F3eIFWyJD2g!?bXtORa3W9M^l^2Jw%5HhF zG#rOkd69s{L*#{g<9evPNW!)clNXh6bn?iHhjTErt-i7uqn;H zz>A9*l6EZTehmAGET;uu!s#k-xXlq@!AkV#L-r%z6CqK*u~4(ikf-F=RkC#&yU6^y_5Jxd5Xj$nSUt z=>jEZs8gS4b1V-+*L1{p1L>1&p=YEqdZgyrj$Y9xGZ5&}!rHgf^kSBs!J22U%rHd- zg0!$+nm(09TOcx`JdI`il1x~4O`onNJ2iY|jy^*b9a>n1raz;Kb}g*0ra!BSHZ82H zrq5JGG_aCWf6}J!M!PEy(DYe0*A=Wx<#C$+A6u}jfEK(2E3D79)-Bu_svoxLpJ1?7 zsfPVq|JGJ{FA7?fB6O*K)K<9!rL-znun*|RtZBtn>dG)XZcW=Bu^2nHeuB%{A}(Ox z(ob?hTf{uKQI;k2sI9ub<_z_J||czWO;X zYp>cd2b<-4Tji_LUPr_knfimR@(mPAoe?dtx9LCHD*r6&9I8c%vSv{j1{m!DvdWRt zA!qLdBR8Qe>8i<0zuB|^nP|?1qr4Tx2|2g}c3}M{oAVHQIkFV9*1=RWu}urCg4Y2O zF#jNF04AQT!PZ0F)A3S1;`T<%=Vz00#-s$btm*A?& zvkB)7qmMWG-`?4VlacX|3ZQouORM^-0D31%R^(w7K<|w9Aka?*&^!O&ENVQeT7}+8 ze*l60DuCX(zb*o~DuCW;Ej^s40_dHAG7tu+0D5N_u6K-l6+rKJaYi)?Q~YH&v;_;>-KE@j@M;3GJ z6v}8Es{-hq^Y~9l0x_DWg#_lQKn=~4DS`Pa5UqK-N??HsRM$LxB(P8gs%f5$X$ZWi0#TZ0 zsLb(_3gF74SlaQj3RKlR6J=EwsX&D0c~%0is6Z9XGhYIWRUjNkCJ8K2fy$ak{*=L3 zssfcX&jty+ssbL2P&sV8rUE$9tdn8?x(Z;lyd%5oG8MpRsey|@;|&$SXpslH8E>ip zMoX|9)|RUPM$1dG`u|k{jFuL1JbPOOFj_KY=USlx7%lSG?8ZtJz-W0u2I(plz-U=6 zfp=5@qvfg$u+=Jn(URT~fp=8^zd3MQhR9kKz!0c}H?Lk-Ol1t8gRpHJn29^w;554-sn91`fu1$^2DglO1aaROBRsjs31R2y@Q~>W0QN;$Yt5~X7T^rLj zv5Gug5gFUOZmC?u>E#Qr{;pK9yFTJys*?x0W`LY;_No9*Z#bLm^tuj7MswP3o=paz zvBuY4x6~y^gkxU)SIJn4e~c46r09X>0r#-i6^pF_1qyH->?rYwt z3sP7w>u}5KzJh{vB_m<8%Kln_%pWOjkcTla7+&l&BD{JJv^7SqDYPnmW!%*9h7Ur> zQ&Ud*nk{02bb`+tF4s~v>tfjOd&7^QXt%C@jZ|;=awKrtYRXyMYcsEUjc(RVaW?ZZ z*U0gPufRoC9a~K~nI+rI%Uh$!nkmH=aS2zu#t?7#8qDOk)s$m;nl0kGL}yqtrQ0HI zN%0wPxSUHfZ8hc4w#-&jhUjuzL>C!BJJ5V&SZS*%qiVY?qK`yNtoHA)MdVBIpq215 zTf}fF9`c3{LHl>vYRb65FNIH#=y%pkc6-EhDW36$cbAp4*OakQY>#+BqQ82>na2_YS-$yEd18qrl1U^;)T=ZjqTo>>1;4&q;X=6-# zKi=Bq@b9R90H;E)R7 z@Ly8`->3i%|M3zytO7XvXGq{%6~Mv0vjmQ+01ob}x*>2}1#m21FM$&(fMfY)37k{` z9I$ps;FJpBSpKC1POAWpmSa&}6+oB&B^xC{1+XuL;&^1#R{`uxRVC0s1+XvGlt4ojz`i8kW^Oc6 z0qjeOGDo5cV6%;uIg(TWo2`?~k*osPmpnL98!0MaZO4GRt~%IJqA$sI4617#6IV;u z`s%u63(IzFQCAPHf$iA5C*t?31Q_<`M#w*<0O0PEf!=Xs;O3SiykFRqLZDu8uwh|`qOQ3bH>ehG9^0jzr~33OHgtovY` zT8wNJz;R@h1iGkz)fr9dx*B6WqZ7g~tr$;_zw9qQXd+~Z-%oHOhA}vPF z70wtrumr`(SPzaddrAwQBKdRbIwT>w@UcYwl62v*RtOg+T02(&hB4lZ;JnX(9mj={ zvOf-Gz=1aaPxL@w1OqmV>)gHk z4J$~rw)9KcD2z*V4?^3dnUfRs`k2YHS;o#3Ch%e!5Lv-yX-_l3xt^GDYNA_G zOM+R6`VdKwBfH6LCh%A-n33q3D+$bL&oaSm>5%6V-I7`oEKJn5;$>LRUO9NDq}Hhx z0_`&JhC~I>?P${6MA!F{@pt@V%x6ZI?Dp>@x}`43xIR(;2QNMQU5IbEd!61*bk#=Z zMVr&sGC@~40B%ZjOKM55B~fpKnLM*PBmQY(bSc74FaALbK1y^INCI=($BE|EOY{az zG`1zWCAB2@Jkk6((X%Zb@jXnyPWdd+^NWBrvBPV1iF&6%Hr5CAB0tnW)<_&^+Hr3r^qNf}@G9x|kMiPCL#73H34K znMAjwmIUV$^$bbyrW_hB-ra)l6J3Rpz?}9Y6O@Hw#!HEANi7LV6ZPqm;H0$R+TAU< zlIU6`3CwA~GQpd2)GSMMOKM5*SE9aK5?q%f$}J{{!nVd%xS8m>ED6kMe=xyV>BQTK zZb>Z(0+RFquOyHb1SMIUF$gmufj!C90Mnw)Y0e~TGoFz#Y$UlQwIryNq#uw3Ps>G0 zc+#D#&z5q(B0>dl_R=3fpsEVs>{Zwnfk+j=k@IGA1fr5^m}AL?#2-5FT3Sfm!JYTFW)Z*=lUuTqlIPm>V`9w3e>=R!t4ierc!}u3E*8~ zBNf1!72S^57)h$#QCe7fk9N2ps^-8O&GZKmNKpZ-YAOz}hM(Kah9lfE z>EY%oMz&2}wN{nn3!0gyWZIWCsORHW< z#k96;)rTP{bWL(gd!ZQz+Lo%f(hfL47edv+fcz$VI*v%y0ufM&jm!}W7=R=F{up-qmtZGxl}PeNiW6Au)$ z&6)J!s@QVaisQ`w+N79HjDu5vnDd)0xRRBYv8&=&|s{&Y&J`z~30@&j6g%!p| z6~Kjw+%GaVsQ@laCbmT20|p#8bYQeEO>)h^T14-V!}e=Dvi^{W!saBmbb_qv_9Q(J zx5zzf<<$L|%7|6{)QiAQ6~L-~C5NnCDu7iz-4=n}Du7jeARU3vRRF8{x9p`~r~p>= zJ!#4w6~K`N&D@gYYKRs@%eQM7pR$>=nxODil3P|lnt3ou?;y=QDjC1wCPfP+!Tu!I zFi8+D7pn)jNn;!+oJ?{{YDw@zlDSu-j+Hq zs{jh9^GuTKoYeV(939WG&IS!pxRT_S)<~V#lk{43QD+O;DSuZ9Q0J)(1a7JTF5V*= zAW*IX)=2#=$tCw_qqAjSyvi!N$@{23liX6dRAEcjr%Dygu{jM#@|_do5KK2*Du61^ z%H9#60#+5bl3XjKiXUXd-DVYg<-`+|?3T)<3Qw}WQ>u7fcJ*+T06QPLAvoD}Q4%bc zYnISt>zp@CE>t3t-I7`o#3buZ?DC$?a&)Yv65z~^1l5vV378grK(0ljnc$fu6k?Oz zl3EfZBYw%*|B- z9BdCYMxccXAU&FtlI+?d8DEzs`I#{Q%{5vjyQMBI{70LSo2dVkfOjGC)`IshCnScK zqTq~?>-eA;xflVQR$75E5kZ5a(P!TMy}Bs#>j$*$GJ%baPBehaek-*x;bv%NpY1)tIT_xYf`Lz!Mw-0ImIpQl~!#}(VxJ+?)j%H zs`!iv960JUkS(-J1yE*9P?u(utx=O-Ibov8OKN!2*HJz1oo)_eitT70$-~D z&P*8ITT)z0(1PeEf{^Z0Hgjwy3MDCSSpoTIX99 zPDz5KPFUthiuJkrq4p@8N^whSN$_KeUXGWZIylf6=T!oinc!@SD+Wi(=ta#j?RzG` zpJUeGLf1ZE37OyI&jkha)mjmiw5MUv6*xxyPE<0UzQ2Q%Z>=x-z3=a#x8 zW3*3C!c3l+j)=$H-K0pLtCu9GDd&S~Oi)Amx0cT>sU<{;Z66y}J{{`CKnb z0&`j&Ca5J_zLC!@sU?Bmr>~a;8!)JiCU+-D_PM^51l{BSpTYzsP86E?+>%-nwDsxN zB*CM>h-ciL;C`Pg64xKmRsEROh6x6wq0r9fmei76;`$ zawy^heb&LqErZu?^!K?=NP-5kOrFm=_Pi$-+J!#1q?Q(p@aYLShj}i^$QtFV{xQNf zj4aO<*<6pS0B)bjBY=%@DuBCXw`6#XR{?8}8{%_yMY`y>v2Pf|d{re~^enk>e$wZb z)<~UGefk`!bC5K8I@j8PTXs7#5O_ufa7dkoC5&fPzhG&M&PhJkdZ}WTTnQAjUyjSB zo#}H+BC<8Soohb2K@oU)A%xbfw{^S+!TKVra! z1J76o0v|KL1J632>kp~oDG#Q-&*3p#s@URlOXbqWojyGR7apE5vZ;38-NtP`R|`yw zPV!>f4z{tT4EHa5Zb>Z(4*2w0lAv)9#1Gy{;At!U_zeU2ZAi~c0SFvcb6``|meco9 z6+k*{{JlQcds62o$|1H|G)$?z81^c{d9N6(>|9x zF(6u=U~QaX#ta$S=Y4LeOEUiI(`#TRPfL04QmPVIo9eR9)m9R0l!M(BCb%ru(bw=T zL6{;5{_yFKNP>CTHI2XSPVl?WHB}O%%0{}$1OsH7-txI6wIm4e>#s?I5wb@F`K>bm z&WqA1cE4+hxP@fPHe#3-P-pwIrzG*Uw0T&bT@=s@|Qz<99jn-XdC_TwzpZ zf&`f{+V7UslAw-X_hKebR2#(OnE<^iE%5qX?Ib}a4va<|6O8PJLOs7*QcHry{*XLL zuowRrK7XxE2-}#TkzapC67-OLB*{u1-L^Xlss1oYEeTrrL*A4Grz;`e`tAhH{Q4J? zptmg3f(aVRd$=@zn533wHt@Sn;bkppMlDGtSv&aka=i3(ZGo9P-MwC!ewX|`LG&kb z{?Foi4U+>;w%;wOBtcKV-W)S|qUFuk19vCr=65|R37#-8tveHJegK6B{ccGu2_E(9 zPfCK!&WPvUouIGZ^|~Z@R63>~6O_qH4)D7rwImqg*H24=)oF+iyOY4vSdKp<7{FsE zJhx3ffS zLzXd#0jc6qIUP^-*Q!{>6MlW5RPlUUOdD^tC;FxwVT=7?Qn^&|tUu%}sbb0lh|j7} z#b`Og&aP0!NjbaBxx0#KetnNrQMCuA&0rOwvbQ|v50lDeRmb{Wr}46utV%7ZOzM5n zuSetB&GR2QhrC>&_nyR|-*}}$@7X2Y;=6lqp5K**rK3B_&bNTQx26gTOZ;xBOsaU( zuTPRHhRHEvd4($4%6q}LD^#%pZ_rF>38FRb+ZmC?> z;%mRYLaG=h`%8&xG|sZ~WDFcq0es$fA3kX_4yyo`#^(LX@7gC-`-P(@!^@|+6b{1GmD&-W^TQ`9lJDE>hOa5Pj;3DZE>HVKn0K3Of8K37>z-sq#ziT?06g@s0(@wJ8!HrS4=y%H+NxOgZ>&v9w zZ_6HdRVA>_K|lLlyCuQvQvEMXV3P#b{ccGuo9{2bUWj9ywfSzTje~nU=H~lH1=Qxd ztpa$GK{5gsK28pPF?=z@q~AIC`&id1V#A$I;(Ppo$7$?DUjHB2)ll=TQknssKjDU2lo-LTo~0%b;}l(fe@dne=OVaKQcV)rT+V7 z(6dZttgiyNn!qj*m+Cqr8O@pNq*~VopNC?`hN*6;OEUUWb@}xJPqkpgQ<(t2FfR#` zQe9qL^+aEmQ+s13h>}xa(^R*lmISR+^)8snBVY4oq}@s2@yI1udMe*mSWRk?>KZK> zCuCq+D`rfRGi+w6Tk4XG*{S;Tk}**B`>xE03wUW#hg8=FNwE4pOzXr1H>G_!scuOv z3Hqe!2PA=CE@S#K0k1ZCrMk)_K|MLz^=5+oxSeG@lIoV!l3-w}9*ZNT$B=az#02ur zC{@lAgYRCayi`{fW{y4|iD~)F7$RqZA*pVuORm?)qMIe-@z#hxk;*$q_;ryUa?w0N z1uz2Z_Cnx)G4~$eQB_;t_&IaVnM_YeCZU802}$TAw9HIG2mwMBFpVOhln{#2q}ve7 zYr%>NHYBL1*ig9^M64I=ylzevYxRyhL6_-pgTkZi%0LrmZe6@s@)r?SAeJFKxCJ zy>(%UGn)eDc0$=EWtw#EV79>BD4~Gua5n`UG8*)2n+2pb(4adsfhw84CitHcLtN^v zR1#m}oPT|ZpKVd%t`hG%l*nH!^xdum@Si}IO#bU?^qv!}$FLWz$uM)xX-mvY2DT;gY2 z)bXhj@2SX29iM5f(H zr6ypJc%6i=Gy#jm2PAy030NdPC*d1Sz#{Pj3Eyf07KuMe_)ZhBNO&0M-)jOEiBmbn z{HO_76V4&wCr!Ybu#JRYGy&u7dJ=xs1Oy1C-VaM0PbG}ezX)X?m&onOyNs~kOZ+qw zjp0PS3&4~%lUk)jn|DAW@`dA zU!RfCpa~dg-;vO$2^eUHGxf-zDuIcH*Df!?$9rb$}Qn;t}0hW{cM~~Tp#s@Mxu$IIcRQF z0>qs|eB2`H3`AM>A8h_QB_O3Ukej1^il%_uquz%ppuQXEcWMpbi;Fo+-K7aodNO;r zTNB`%PQ5|6TNAKzS;@WK9!pknf3#2d-)#G0-$&OAP^qa1n9km%jRR60KJbQ$K#p+ zy(iPcPiO-4{s*scp40^By%&3W-&2|Zz5nDs_-Rd$dOsL-u7*n4J*oHKmEJ+v+4oG; z&mK|lm!n>5H1s}~OUJ8P0QA0>3+6vG0eZhQ5QNt>0ebTWjPG?#fZpF1g7AhWAOa9I z&qtjeke?l=5-%zxmM}`+iu$P@mH05~T|*`ExfFb?1waXhbK?O`fD&`5{y#N=Ba+*) zPc*?6ZN3|Iwy@1rRPcS(<{C177WGpbw)t(;TRaABPG_KfuLYpZt=&QRK@-sC;S97N zH34nrG0=X}1a$m32HMY>0EgYpK>I}#;IK;>XuoO#9QG(3_M0Y1hkY4!>Y-Bhi+L#f zTIu}(hvM&1KYK*I?U?st>is(d%^hpLjGN9dO3?)9{U;sf(FExIcM`ms0KJc3p!qZb zdcVs+^J@b1-p4=-Xae+3;j|jm1gWi7m}0cdkTCI}^(fHpZ#`l6bEHXrbU5Yq&7d|x^U zaZP~3Ugh#zstIt|)m)&(0Y&41g-ZWnxOR_uL)A`p)qF_RLZWR-oupM z{Hts%(FEw7$tXBX6J!`w$DCK$!~`}`tD4wP zQPX37HqIs*VqOPRSXyu3zD6woP27ZX-+WDwO3#cry}+FP9LLsdCGl5^Ul8-NElOM( z^K$7<+r$g@qm=-4E9Iz|a}))f&q-ym5>VO|$cmVsqAB3mnD+?^I1$6mcf8gBDhavN z4=QP|;v&L#p%#!LCgpQtPJfhTKT84UDFJ6uxlJ)YMN`1mn0Gw|bmyFKr4|5{a!I&K z5nPCu?HoK;YYxOqJOsjaO^`}o8gs5;o4j%ByIi%I%j=?RV}5GGHh0Fn53B zO}K^9H^iKeC}0k*<$X6P0kb*t?uz*-ngZ^L1v4-?q@B$<{=S%eK!vZqr}c9{xL*@Y zA@Q!5m-h*?&#gz<-LkdpCYs^FSSs71#7ASnMoJvZW*=7q_}YbN;wddrc5+|LyMYqt zc)&+zLIzX z=lV}$sccK^A7ai_Fm<7#T_~H)d>8XRf^2H-SiDR1gRCjuK6si2`%x1R?2{rO{GmR!=RpcMf&(c-30O=4o#K9qrhvS-_e}~ogS+(nc;Yn= zdL|NgTo_8(i)e^0arw?hU?`BnxSygapikVJ1E#bw4ELgz8uW-eBPbx3LDWlW&`=Ac zU))d86i^lq{*3}29RYfITn#SFYyaeM9ij;^>sH49P))#KnZuo3r6$1Dqv~)6ZkQ&( zuGLkz*w#4OL$9K7@2gabuVwk-QsL~|xwRS*Po=t4YFs?%K+m*pTr$UN0Z?is)_mUt zO^|cQsJOQmn6sbtp=^wjcp{ZOG@i<~*zBOVGZai+*w-$U&1R+`q}a@y3@{(2jHecb zI{2SbMcE`}ygl4GO^^F2iUJzoe+qE>L2qnn{h9DT1zbv%XDb1Hxi-v)|CNBF;eQHP zoD2GjmI4;T|JXHUpG}u9RRU_c#;$_@m4M^ne=wyrVrKKLYuSah@IM8-S%k7E z#p~gJl&}kD#=SEspflIIvs!BKKXK<&3h2tR)0Kd|oC3~?`ze|NHpRVsDK@QZAJ8vW z0$_bwePi6&PXU!20~aa*@8Y(*Z%f=y(G+k^-1`j$+)0=1&>A4V98T{y=srn_SH>Ow zS7LT|#`M)n;&dCxjd4HQqQqTs?<6p#omUC^?OGzj=R0oR?$89p^f4JA+@;5z+@b7@ zJIAsKe5noVm1<%NSGc?5em2e~9*BE4vx#q0L4Qa~lp}v{+_{GWqQxk?PYJl3%ksXs zpQ0(?skrw51xyNo{!Fugv`2y-yKwnd4r#l1bj zly+AM=x=BNQl*#U&O{2}?{)fKRRW^iRlgPYQ#1v96!-3=fW4fC|EUGQN|$5j=letx zFroSpi3wr4LGVZ5(RN{xY zcOayvy;2GKPg($c_X?xo7fpZ?we3LoRTH4Zn>|4IO%tHRnS((1T@$1d-^87%ke@w~ z!}2??!B_h;Ns^{9lq)VrHX@aJKCp3>&EW*#PfpH~xLnnn(2za~J5y}dyQXabbz z5CtKq2~r7Hsq-e4IC&(>>{7Y7@H6VZ)KWjyqY_!A-s~y#C$9)QXaTUqIndJAQ4^rV zrMx2QqzSMShF*H9Q;FKy_-vi9|fdysh^FriTqOUZES)+9q2360?@?Ow0<{D zKod?FgzlOE>+|1>eLXY*9eZu9n`1u@cy);2~yi2L`GPPRQA7yz;tNS@2^eOdI zUure5)H`}Aw0ehE1tnSlw0Z%%SYK2Vpw&ujT6{50fK~+@rg2SxR(JLVp;Qx~RXt^t zX@bL0l z(j7xfooCpDp8+&XHSsBD_OYdYHqIuhOTCqcp^0Z{%33V|P5gsO*J%QpIF=o+*93ID zz8?saGyxsImmQz13F!EA%9x@Fvg6}Rokld6eI{3kiAt-#F<=iX^;2JJHLKKn615ta z26}@QfQbZAHlx(JmIAucSVt%Uw^spaEcH_~1uQM~K12ccawBuJ62KLrGkyc}s8Z(u zC5XbsrR{$v@=*Yst4jTUP=Xj8B#Z9={)z7ZvO;^di?1&xs2N6z?~(!DvuEjlrnqcC z#*5ez7!m$kKtTS3!*v71$6rG7-x+oc$an@EX%W8W-#Nn9>T@G}YrR1JJHuN8()U0> zVT3QDcMJ1-h`vuGt$T#;miLJ8_3vI0zQf%+EdH+{bD;Paiars(h21a0SE>6)_&)T2 zFu#fDD;p@jMl&!hz8N!kpwMSfgfBct!{3r)^gz*SEW&q~;}O1yTpHoq#AOk_5?me@ zACfs_mEDR6->MxN;hV6P5x%`TEG)h#bF-8`JS@H>vs3C;72)ftVKw=}}n@s@>efVF*dWzD0*cMxkFB<#36!uRb~M)=0rstDg6TOHvGUTY$J z2WxHk0rK7@YaSDRg4k|Z^Vsmq#O@xHu^$>7AK?pCXN2D+?U6ykqi2UdBlf7|KR?3v zp)LsjNZKodgvTz7@H+US2ww-<6n4R*zV9XX<_O>Lxg;DUEw@DIx+TK5MYcxxhDTF` zuW4)xXLB5mDiPAIjPON^tHRw#t1U_Y7J6MB;ky&pg#XE9d}c|;IiOt|;p-4LgyZB} zTp}!eV|WCyB_$af{DyH;gs(R|5S~cd`Lgwg!iN#tSd#GoWbBLZHGyX%eAfS5crHtB zlzh*J7j^)4Q%S}>;CnH`XZP3{&$l;Ue2dvDE z2uk0dCBl6Btegdv_*%D>!-tYjS~+~e_^g#VAR9bY(TqDO-pb*_xOc3~DpF65X3PQg z11s}Z3OXe!?Dm_L!zVp|SUG&wV%Rx+9%9-#e5&EHbNG>S>T^V>PRvlXy2?_q<7$Alw-b`Ebwh3p*OK}xlA z#C;$;hj(Jy*_o@T>cx^Z-Ol0dl?*%cDGJyT6B>u@9NqxQvU7MJp}n2MtMU$Z=6crr zLe}hP=kSWVlbyqh+-y7ZZ3;+@3k^EkIlRn_*g3pd%&~KL$=Aisyodq@#4~naNy@cz zcokF$0Z4|~nWHgIeTT<|2E!o$)G9l(mehrD5hWw-%)^NuDVavunG1*>7066Fq2Wo5zBmYfp z3#=yoP3=x2RcJSU_$W_#y-2>I$vYvv}_Sd6UH`EuJq#Ern z2Oibp7t#$oc>T8Q!mZQZ@q+vJarSz{OT6 zD^zz$RJbg3CM)bMVTCnV10ehF2=Bl(){!Xa`egv#3G7IF1xWt;Fh}49@u_Mf{~`1% zaHBx%{0}hC1#S|ECx2isAU6vnVAus&z;;@jAfUhw?DZbrfGtQGZV&|?>PmB%F56YO zvK09K0`}81EmyaN%a1k!k9DSQrs;AO_JSILC-d1k+$nVx?so%!PS>{z-NkW`Cniv41Al;DmH|?%5(-9zOz0+J|!JooHPh`zaEJLnr-87U zo&(Gd-^8HHH`9j$^Mub~m=u}mQ-B4+T@X8gGKr;ykD!r9n(0TQEF3PuL=>o&WgWup ztAI^2(>J56b9fjPpCik1jo$njk1wD{pYM436DRbLV>E@-o^}q-DL;!W)fN0yPVx); z^t62-h!QF)OK7YQL+&^lrY>=NbPB_ z!8uTlF&=0zt%=lh3n+b;qfddrJTvWMVBx1R`U4Bh&g_p7KHUXuq1l;Tvco@PY6~1` zb|#|-0cvGx3p&QA%2$eC3V`@O4U4(kUN!Hn9ZEzB-Q$sJ4^}(XSL68M6 zQg|n$a0vEi!A%P9XcXQ7S;5T;?_d-*_5pse!rL2#y+;DSyc4xGZObft3>pWwbb1?l z*!WIOp&OP8UZL=IM&Zsh;9C`*W)z;z{x>N+)hPTO{Rm#E@`P;k4#y++|>SWko3DBNQdUX58Oc&)-yjKYF4;MXbKZ4`c834Djb9mqF< zU$1c6D6FF^Z&0{p6waCi{6>Ylj6#R~xk=%sQ8u-phfB1`ZAtHR4E=`o4pHTFV>G5NTv z2_Kw{)jarwDu?8YY2znVxs?2jGwUeW_(hC};B&GBpVX1wctLR@TB{gcFDg9C=(c>` zDkJ!k!ZTI$y{z!Citbk=?m{$+XnR$a!$+GL4gXL$d=#c;a&fm281(*|PNzlM`)^B5 zd}%Z$qDjH@rD=CtY8m}!GwOWcNyex>)mkvOOJqRvnRM9 z;^k2z_-P8gTD&}F1iww884dfc0g&;XMa{aVV79k{Kc;;HB)=Ob#^CQh=8gP+aMt=m zAZGsM0U&=01luyx#UH*7bifLNAC0l@1%KcBFl~l|mYKG2F)~MDehxZjd#;B@csz%R z+iXw4X82(`JjE2hpkarnrUUax%oFbC2j-PnAUuGf;FDOI5tzc!<;U;6poPAV4~7Q8 zkePN1+iOHK`1#i?u1iL^WCE~uW)`hyha;Tc(#`yJ+iG8Gn_T53U4`bB zRm3FH)AoQMIvh=ulp}{`e#YQTA+@L7RWs2evU;*XM(bkXBH;-Rt3Jll-2X=4`_q(k2bX5~5p8eR9%AIGZf9PdUy!VTp-|29+=`F{Mh#mV|qj9e- zYTbt7uI1S9*r6eT$`zQ)`QJIAp>nRqhgS%lnITNxEt%`HRFJfQRUdv z%*V_V8mn;ZX}%r;e4N6AMz^^uml~l%6do|TEnKw52#r^`pZIbkG(q9m(+t5}5}K%R z>}gKy0Q^vedyH;#mNy!qYK5l&$Awp@M&Z~U{*C(AO5DNDqY)E+s7{r`cirt!sdo-6 z+v7T{OQFGHohzQRaHSEdPk9gK$HfpXE<%$mn%_;%0qsJ#G3W|SO`Ee4D;4LK(6nsM z-$p*K;X>21IVSD=3*r0FjBE}-Pk#GUActo&FguIYEp&uHB4XVO%@jyZ{&L*J3eC!< z3-Uh=1DTV}i0P4EkBK_ekjE?63_pw9?1Oc1rS|6kSj!Jp;#cwT?5Bpoe3Qo;nZ5`8ptIpbX0^ZR+S5Z{AW+x zQDgtsqN=!~h94*UoT3+5E1+AaUy6`l+36;zR*;su-TO57@}JAZHOzHgJ{5KuU;^18 z5Ig@|mRv6oPkt|KPEv0WNPx9(^Zv9Nan8MT>g`!<6(8(33cFFj9STPr9|~`!-YIbt zaojx!{4RxKw>7#1_-=(`uYL>EO}$&;h;tX#htxe1cQTB^%39#}sB-MKE`tqH_e$JG z9RIT&@Ove0VekD2;wtq%iMtS&r(nRQ-mmIoM_lU#{(!_&Ok)sV!AyNn;l~<<_hbNn zNbz^H3ojfB{O=OCvh2bX>a$Pb8Ft}!wAp@zr`d&tni>+I0&JV`iR2uosC2L z0)JHEfpvCaKE`S4V-k0D_7uL|ANb=EH?uv3w_v49eL~@#JcYv$V5v_kyrZWO*W*U& zQws0kDZCAP$keALZihYH8X6jm)Mq3f@OTQpa-;lNiF*uBVcI0%&ndh^pfIls@aGkt z7AWL*I8tAbxZ4*fJQ@Qj^+k!hJb}U}%U@FbhKQ6myzi~mk@B|U)RFRz!gZv)EAd36 zyr*y-Deo&>N6H5Z*OBs}#1oP7kt)}b^0CAdk#a!diAedU#1oP7iK?$7qz-r@gq{kkAx+@PQe+8{~f=j8wh?y$Th6AKHWhG zC<5+%r9IE7B4}p)f{^$0=-^4qV=RUgN17*)*4+XjHBlvyCZZD;0AjlGbVxJ0w@cmP zyakWl-aMBlSlA`IsJiT*3kVvY%6Bk6~%Z|L*6+m)@{&u94c#^fR`N zt}`(WwoAP%?Hh=S&<5C2Jj1CFmk<;u1zWI zQZy5-nBVw>4f;{cmd`;RE^P3lFO@dHWM^Q)HAVhMW#{faf;T%h~|FTwPhffTi!b!FGdLGJ?7KSlkR@fm*noJWEby1oxcI3d!O;8 zb3gMu2#*3p|EV?JbEno%`U)?E^ua_#|3}lkWU$p)+CX%_JA$$hfJ5{?3mKQugL0no zRon_W(z&A7wJ00s&FF|X!>dxz|FA2eZZVX^Gw&B>kIDLYvX z9=^mR&2p?T0P-+_FE z%mG08vp~kaiPJO)rTN_uSMe4I{V{xtIfTo;1!=2j^HH`r+iBOEZJH+{a=?IX97ZRZ zenG}E-XYT@$1517qwp{?;HQxplP4o%inH*}UZ1lR6_s~#pphPatL5;Uffs1rE=Qdu zK5W8(u>KY{c8C~WOMGP8b; z>TU2&=sOBXSA{%Jt@3@Nc;96NpRt*RKJk!kMD8#ky?tUT98v8DGF~FF#^uWmv)Y%+ z#*9M;u*tW)qG{lU9H67tYdgH<9Z4PXF;nxa%7+MD-u8~9E>l1_ltiJ^JCe8=gmXz0 zy1nZic{w=$0m3tYxX|%^uh22i=8F*=*VOf&UZLxuAPgl@=9ceMlHT_Qw<9nxUw;x0EcwhK5xEs*$fegWH60>jIoEj z!P~(m;*3AhTL>^JF;ypmXk{XZYEA}u|F!rPbkyL)j$d!9+@@%p?pKzRx&~#nF0PIf zn?|FF25E6~=1Dpj8l<6Xc}En*lWE`)yj^BCO3RGc)(^-$g}jO}Wu7CEI%$`aycxo$ z#>ACuqEa>Sw?q?_UJ-8-)=+Atx0W~VVxqk&Zz|i9az=VZY>eP7L36BE+!8b<{)7qL zEKo92&}$jP1zs7WMR_PL^vW20IRd1cLhh{s(p@65fnKr!W8!NCD7w`n<9trl>n(RA zDQsvWKYeVTq?+EFX!<0N2zS}Qsj7jEH0N2KR9?6m6H6+9)vKD;DcTVA9$|=DUWKE0 zicp$60w9gTnT@DzPW6Z@V`JiP#lSvDk$s<%5c5Hb6eHa7VT!b;==(=0qni7EAVv25 zw|q$XBt`VynAj@~*nTDR)P&6aDWhr65lc)IKdP9=KSYP_N(q|V5{$c2s>oOKxj5!M+Y{5vuwDP~3~eMHP0k|JWJF1FAxC#Q&u@VXeEzL+yo#BLK!jQ^}Z zn%M0Qnso{ByWOJs3B12;-tDduCge4!xkn))%I;B!&|CU{_5gz{-gttkYYk_#HBz6Zw9$-=~s@?ZLC_UVT(%YR3%9)CiYQSJjCPrLD#6ym7 z$|g|H0Zisnh}baVui|7r;pDL1izs;(fMZD43q*<~nFreKR5b{sUr_uLU@)l_!$3(( z!G;-7F%d{1GWkTN1F2*NfTP|!9zr%Xn`JwQ=9WWF*Jjz|RM0Fl!G0Lv5D^5MoI|PB zMi9;-Q3Sup{2jN~o8HW`nbR6%{K$keq-%i84z7XVZQT`=hFiR>{gVGV4?EsZM z!2j&EVzX}c$K=hgz8NE_&md%6;#`EBdAZ|QpjNHGX&P!y22{-haso2P5jhOV1<0Ha zs8|o=I%N3o-^LWqIUXBQwmN~T13(@Ec@JRd>p+G+jniP3PyHS_TrN~%YjUt!#`x)z zA!E4{G`WM5bMkU$7!5W-7;3pwOPfp(23qdSB{JeCv|}D8!kEiGO94rU#>#o?{?7io`FeS zT+#e)_vRIiG5%0C{T0fFCd$6Dd$DXny-yUyuBZ0Ay9d58mjf{-?%`tdf-OhgOw^S9 ze!(6mr>}3Z(wjG{@@o_2H``-bK4C*Hig(&$zo%p|+1w%#IbQF#<#;{pj#1znZu{k` zidSF3Z*JLp7Q*csc6hj5#5?O2t{3=G6M2nVWsB>w5)g|4WwdDs6ZmH=ukrU(fHH325tBb+22_SmK zADz7cAbNEy*iD1yQl*W}O^D?d1@fi`sM8=;8S|o6lQf zAe#Ho(gZR7p0~vKljHe$D``AGZ_VT2mUl{Cw8V&%gZpJmZk#^j0Di?1`+*VV^*~-# z$SO`Q|4_)?y@0%?5HW?mE)iq;+3iqtl~f9C8ASkdOUHAx9j>wl&<-a+_ceeSn==Lf zBtFYCYh+KiOVw^cIp3%@rtiu};p%3gbh^3au!PXn)*uRf8_cg$DBocO|48wgK#eiI z1FsSCTi5?MQ9s{`vA!LET)>QdW58cv#rU)o&Y6Q1&MdTIG#;Guc_ET+3ay)QMSq~( zCF2Jg3WHza3}qokO+5i4-J z&^*O-xT7+RBM!klXYcR89g6i0gwEtn$KF5W;}lS4m7-01cb3JaT$b!EW65l8bL`z? zC}cM0Mtk>RVv{rL`BWg=v#fE68r$QnG3R#-QhSHI_hYk5#c@INd@GzNiW$v1#TJk$B7L2{Xl6OB76BgW*du8D$(Xum+At0p=FdnY#(1+9Q12Ap{Jd$`2%hOh+PrqQWR- zh65ToMs7kqm(hXId5`lOI#x9W)T2;5pDYY;ve?ELvTSx9C(C1?o{!?Q0fSjk@e(M1 z19lr=9%G!9+~OveW_D*G^k&J;|oB=2|zp;%x(Z= zay+u9cpgPX_Bd6yfRc;C96;68Kw`)YByus3BaoQ^n8%^C0~JmD5*I42b;K5Z1&WR) zuNQVc1DVqRILdgn^_s}O3U>1f)A@EY*!qKf1z0X;odO`ckhzsedmxV^^Dtlt{qYuR zo5oM9{hjRU|b?B`Tu zCKF*lS0b|qWo8YaykP|h8uViPVd?dt^^3D zmmw1e@DT3ca|pa6$Mt2a>8!m3t07v=4w)JNxakHy$HJv9xs?l!MBzMu7=bLdjYnC$*{PxdX#Vq1 zd=_9Z3z~gEX18&G%xdJ_4yIcHIK;@~V=0$-I0dGJ6J7zwO90`7FOm6NR*_CP5_K>j zEts*%bbh}SI?xFz8TfBNfN(-*WI7R{69ysE4nWF8>G@$eQhZvcc7PDN$YSis843E!gV zYw~g|c*3w0KskXA=v>Bnaw{ivL18vPIDy5sv5m!>oyVvNolu41O2A+iG&_OJZv0Cy zn3WS2QVsxzaKbLpnmmI`O@I6ep$!1xgzd;&C94>f{ZR3ZYsLLF^)Q^z1_K)iDC3RyS*V4f$y!6) zsjp!3Q?(1^l_+1vS}Zy8eo$^OE1pEM6~qew<^KRO_9L9WfcZy3%H612@i7S~J^(oC z8z5(})o+pMiw#vzK#dJ6^PcnN;7|0><%z)sWbZFEYIW6=wk%j!Y$y zOMuKqW+tHg8X%QBAf;tT2eKDyKtAehH2x@5nR*T~u8s9&d>pn1C64hG$mYfF)Y(^{ zy@4RFg+%@$`p|AbsygDd71(8f!Q`!|1m$61djS;_fVArfIe_wMKo-r%DGgicD#)u? z0Av-4js_T&`wr5uRBLFI@wwDElh)+t<;*5LuV{i2T|urY#_4*9xCT&_3FH}Mo&XFc zZ$&vM-vav_P%#!rK__fY03%OE`&(U{T6l(e4b$hzoe#lP7oq4d@Js`e=6k?MKBC$Mxt2J`DYwY${JIsDMxrQ?jd2L5iUa9}OaYPJK+2IRBa#E84w)Jv z?SL#qW{0S&(@*rcrx?$*(JzqCc@iiJCV5wFqr(}_St@54+3y3 z=6(N9AZ|F7?C%X!(R{rB|2Y^w1T^3OSGWGFD?3>S-}8mu%g!GsT^k3 zxmMxUj8Qqwl#`hpt)P_swjQ^XLA8uojEn2ssd?MbWHyXh6~d{gGp16&U=~;O0Hqq( zctAx7kmHeAOJq2ZUC7)7IO+c#S!!eI+&O)FwYp3m#C5?>L{r0 zUSsqx7*Gf`jhf+#r4rgD*i6n*9D&@frDG4uJmOgyZxx8uqD#auIs(Kx zawswr0E5qm%H>=?%DHZgJ{6(Px&d+Kj=_A%bgC`@c`n%b^Km@p@)iz{D)5?HoU4(m z1L<^>uK`re0>YpC{e;M3AZO#Mp1=EBbu5sNka+`8aXOHA7u<{oR9pn437N|QoVfBcn@Qv>oN;JhDT452>VsE~L*$D2Z;Au|`-RWJw@1_9{> z5Xzm7%rQi$_UFia2pG(Vd*xJ0D8t{_%mY+V8U9RtH4!Rx5i;ik%J?1&M;i9kRBo8d zKl3UG9Ru=Sls)GPx z8kmO6WFnjf)**8&5l#a;kl9Xz)4=1%JPZ)iz|%q|pIw@I8u$cd2guB6;7??JC&FnU zT!3d7fWhKfCm;Ux1lAoOkA=K##{>H}1k&T%QSWJx#(|?8Q1v>Hoyc58O8+ zz6UY~$TUEO3&DFGGM5rb1>)@nO@NelW^DJwDJhVqQu#kk|E8-Uhk;ZF?n3}Z8TIKw zg^cxN!Y#g=wktKx1;Yk_Xn8j>yNFPy&ye|m2vzUZ9ia#qOabLotegr}P!T?#9|NeM zLT4j$20(af5Lz^iOHy!duROIAWj6qXr=CUTNh0*rcgTE2gr3TUx}5;RQ`N|f2aM+P zj^RQk&wZHF-dcw8C9FVi{SPvy5TUm&L*^2In6Ga^=4JqoN^~wU&&v0H_%ctO^{rWh zRf5kwcrY=yFea;pA^$vTKLn_n2xM?iyz>gEnhs=$nYCY zgITBI5>PtyMsxy(aDL$tG`^y|`|V5-62nmz2jCdO{$V!fQ1al6hcKcS{9TVz0iu8W zaNeCn*z+%tIRF?;{&IFwbgoMu{5uAqf}J}YnMp+0$;*)0OoW}?gUoIs?DTWUJVS(? zKY+|f0P!Gx3^c;E6wc_FVcNEHHZ9Kw@qd8lH-K<)xG%;aK)AR!GCcvp#g)tejG8i> zxRzWC30!KVk3G3YM9t$0v za%bYPO)FI4_k%-nnjm_6pkin6`b5UTMZCzk5lTv?BV`5!J&1?V8K&P437}I#YS6Ge z5*?f2_Xqs}f1KKbOpQeCW^%jsEh?ucSH?~oqMc^Z;ba*Un%RN?WwVm&$3bXsnqxDl zR);)vx)^mjiVTW64N9`n(2nKUo@OV@L!3gnq~;?*h+wlhA_Ea!n8CDRo2~7b*X#h? zF2Q^1Az>rYb?8Ozy61s4DkJu8at!@2O?4ZV0m8 znP&Hn(jt8vp?u$ja>{{4?OSPEoZKvC1&UxV`Zosz7GfcW)>3K=Ojd)g7?ey9+T-)d zn8*ehqZxo`oj<=EEi#98)REG?V>|r2YGsFuhl>Vd@K_?WFr_F5ijZ=(ziT*#13nI? zE04{fyt0VdKcm*%J=~epeyaa4XNqvZV86)=K>VL!e{^KXK|C1CEK)*;I)bh8%#%%w zK-L(x;bhZrb=b%YzTwGQsTw1a)xdN?0jg+ZqA~WZS*1~sj_)W^`sg-Tu-LU_na$EN zWBsT|dGyP;A~;Z5R2xvS9pWTgM_O!rGIy@9&V*z(ydIOxF*ZZ;9NLm7{lwO*{jiZ# zq(&Qz^jZi_a$cR^#D=XcA?d#4b{J2o5-`rD4VjLsWK9ea263 zs{l~;_D@07O>eu7YI{bq0T@Mxw`P|{I6~=Q(#V}L zdXHj+am*}|8L}^?7$sK?tR+PTr_v=M*&}QlS`tdp9~`_InguY8NjQtcG;kFomtO-L zA$6Eo*Tf}@Y1C^P(*OW|fq;4@oZ4(-uDn5P`sX) zBo2Gx*5bsQH`EJv%ymr{FxJLe0-*Y~(XZ)3o4E>rWz=10GsAtO*I0pX_gbA$PP9sw zGefy0N=?Q8e~71Fin9$PQ7`VZ)&eYJZ;Ajpd&nG4U; zG>?3=rkO;_ebF)i{$qt)H_7bdNS>5glnD9qUs^zGKCpWd_JFr(4ffbJjz({pn+I@= z73J>SCM`mvD3QkuB;+%jBf}K`>G7x_PL^Ek+b_&QlQw$566xb=CUgQU%VZS5Hoi5h zo0uCX3KC8RmN;bf8YcY#rZIzwu3nQ=ogPg(uq9J9>c~9?U>bEy*c$HFKG5uU5ahuK zMYJ)Q1&|stC;iZ-hCUR-N=(L!>?9_$0IXiq#GI_27+Ncx}@%kcc!r1cUAHJb{6J#>9R*R^EINmVLSt7{`RSz#U^X`Zq8tHU^0f#AX{ z++4Yil~q*g))1f|ibF(^%O#9f35sptS0$U68xFt-II)SDDgc^f!Vx9tND~K%94RTr zatLsB62qnzgk(Jhx70A66eJ$d<8V!NM z}g?Zr_z3($gCelStKuuaP+aoS@3Be4x7NS*~~sf4B`Ns&|4*>zhY(^|61 zch+7O#1>o8%Rt&9$hAy%06fOZoQq7)pUrC^h~k~My+|?8m{62$tWCNEWO&^K_?JwK z&Q?q>wjt?R&<>`%53Wqc)@rcg!RpyU;K6j4=oxiN_6X4b$TG>b6U&w<%-Bj~GBLp^ zU-9eIG8`oFGpOJ)R^}o}9Iqkw3jjV~!g{u`F3AU`cxkVdJV~THcs94CXCXmU`Il1V ztAJmLh7-XfiET?wu8`=fDc%ZfB_)}d;AA9`?_Vm#NNUBzcluh|gAvn;DSQx)FPd7EbG`=t=TS@zx*Z!D(F% zb{ebvOR1I+z<2PHq)KAjQj;qrT!D!R5?V<~CMG!PH1hpRrRcO)One8hr9J4hR!p-F zVv?^79&AioyiRy99T#Mf!H-=enL`r!rURUom+%-eWWGo+*D+zemN&digD)|(k|&9j z2dCv7>@-&Smr^YubpzOvw3NiQr6yNMxWY8Z+)7F^F~Lcvk?&tBMW?l5;@g5P?Lnut zV%m8SlgnVmgNP&s6LV79WL=*r_hf(F9_ol2A?z+WqW~`16-duld8S(d(3r^$B3r))Rim&sxi3Mw zMdeW{4vS~ARqGUwNTBp;nZ>#JFb5znd8)}X3V>FbNcMW<#NkHkl1S|!lD(%o$ZBnp zLQd2%O=}u5+^0h*lO-ZsPZ3f~^&p5KByY;m6LS_=)(LLW5?NY{=UoKHF&8B`tEm$t zu{9=q(-D_-OwuKl314som5G$fp6bK4&F>)O2S5sbGCXyS(Yc8Txj}FXg07n2(6t#R zto{oC*Tly9KP#KqdK92>&1*3N#0!gbEc!+!S`t~lBG)QT!2=>o<-yzKcOtt7K-+Pa zB``l6=|lj`z@%1W>!%@EAgN3^mB0*4)=4Up(tF{fdxfxkD?>4?E z=eAED%_T|R@`!F;2Oht%%65xsE#H;cZyF{yjg&^esRNHNMBmsa+ybv}(&iCJTU;$o zs5zR`eaIdFpb;jv>?y^Ti{4c;nJPPa8WQP?ghI`N4C5Uj?*VY*+lUr6G22aut7Afy zea6N)qMs;c6YBujbTL^ENG>KW+e*x;Cguq4UARX3jQ$%B7orN9CW4h;BTA-$O&k_@ z#{uYOVI%sj0z;{V!IHUDpphrZSulK(BnAK_5@0wjlVshnh-1-oJ(zeaXzdAR6Z40O zN;SHYF47g{Yox83#|t~qhs5MIoCMV}R+T53cEoF>tbqH0ZBTjd_v=6ZT(4Vf=Ev>J z%0vbEHY&v=*#VasFyL!|q^Okdm-6+^)}otBl2vJ@wrH@KoP6EYOifb5H2CgmTP-%1 zB)8a1O%lTX?}M0^MQ>`EyaBL`6%T0B$P~BA*i-h2) z+zDU|F_rq%=!TL*OH>34cRc)uEO?s<-%&*`naIl3x^hxDcv#tF`D=px;N8Lppv&EY zR?s8(Nl$W+eCPDZmPB16IUU3XjcO+H;-;R-ACk(1)0({R!JJ1(tY#u7sCp*7B$Y{( z$R;Ls2x#+|2`U~XFj*m+1PVxk+ZZDLOLIB^vU)}(_s@G(s@p%C12ZthuK za?k2S&!nuWS^%WCI2a!E)PK=o7_7KdkP*PBroAfw$q|krArA880-#QFuc~R2q=4uL zG-;(56~*H?We@E|n1-xuE9uU>WaqgXfL=k6GhuBywYG@@+H_8{xW8}?MgF@$)auCq zqDV#;LYGNWkWufpgN&^l>@+PGrfJr*9<1VkFdW+f(n{6M?A2^kS}C!W5DvlQwgVMt z96F2X!y-Rcn5Z+Vk3R?Ev^;-{!_z8V**-Ru0oL)I()F2$Tn# zC#Z+Y&FI8&c*abW!X0B2QDzD9*>LU-=GQ0iemj^y1AwW3$<+WCzJIFKP*OmZhsmzW z?k0SU*Uf})m5;O=ljeNQp}nqIl0B_?9zp|-vC?+uhsjm|P^eM?s>=4%FxA46#%4>7 z`eqLHUL27a*rs+rE!Fbc02d9OCp_<7uk*#O4Qc{_$1~4$I zo0vOW6x1_0Uu3J9Tp+19w|R606-qFX&DH7VWW=*Y3I~sFLl&?ZDf=&bkhJ;?5+Wus zp+t(PZDMXc0Ip_2iL#(scFS=J1|Dtz0*=WTk)6Us%dHb~rD}P!?=2g z$(5!XTH(aRl*(Z>VL~&Ktj!6sb{WYi6-V+~)Cm+-yG`%w`ruKu@!2c+Oqur)q{DQ3 z64QK06=#wub)~u_B@?EUHKg<;x9U2zqRx779pqNf_pez-0_e7|#LDx^nIpL@SC@+X--&j zutJ+b_V3%1ujI68Q8vF`G>`}mU^qGh+B9NwjfCYy1ySQ*i#4++CSx6aY@!Unt~2FG zMMp;=VP}!mm6MHw5>eOEVoZbF(2 zF9IjLrQj>11l~0zlq*<*l(0d;Zlrqv_W|^ABr=NtO8|8C$$--U7XdZ{v<^&@bzolW z@iOxI(DJr{KzkZ>OlH;(g@@1%VD&RB#<5eG|wMD1A)^%FT zZC%bssQO5jc`oRe0d^*p>#^-Y1&+}GfMYrfFbJTJImnz3&|^i@IWMqI8lV$^YegRb z=ddWC0#FUm2lJHk33T9d6FwN>^8zmJ-z817~fc1cF0DX}69l(2l50dCyD`@k6fMmbXmu=Ctk6QD`!9NW!127Aqk8)(% zqEG${I_H1RuV({RCC@{goA&~!3*~i2c`kslLAm;P7?~#lPXoxO zk7T_&fw&B?62Sg)eCVSGGD`rf0m*jMx|ON&zp@{S#evWhW0P&H1*`|03ZO4G09qg9 z&jM)v)_k2&wj6LQU_C$|j1$JhRKPUAJOJ0q)(88~IVS)}Yh4Ijm+K-uH<352iAXyD zXg}&hU1=xwZ!;h($q!qB-wAjK@F+kZ+BeUF@G9U9z&n5gfFA(A0E{F#T3vCPhb~P{c)W-m11_7dgDos==W$^fS zDaQ&Atq1+UW0_16`@J`m9k(mGo}cLh9(o*JAkjp;U#0N>WWV}i9xn!dfXXiO*ARY* zS^irRS~iP{ikHtWp0{FI@rvaQ#mi@|n7d%1QM_R3;>P0HiyGG!&tFhHZ28<(3zsY% zv2=N3-{p-<8duC-QQWw8<#HwiR;*k#cj40NDdsomMj7Z;D1P&c-2W{FIT z*_Gn4OBxofn%kJ%Xwjmj4YL;&uUIe}<%zBim?=A1ymIN%MGXsPFI=*scz#2}Ov>%w zZ|1<61Nsf^hH7J@IO>Ow0h)r(eIK)8W#eL*Up^Bv$C4HE8kZ}nn1tDd#fvebL^F!8fKB4I zmh9imWy=??p1raWH1xB4&Z>orR`y-Eq=K^`m73eQX!bEEgf2ueqbO-082B||hpAzG zVdM7@tgxApkr6hX0@E?w;anHrJZk3I=8z|yJb%sfoM4Iyrhmb9y_>RP|Bmek!4@(9 zy1lDXASlBMm`)LRJ-JTaaHnTyr-K#Db+WUa{6c3yUne{6IPRiMbgI2GpfmFM$YwZR zx3w(S>4|#fxh}g!UpILu7F_MD{9IJ9j?HztxHFv&y@B+jq>NV9xzW!WnYPR6WPPw2 z`LGj$IV76PS9=5E_X&kD1M6Fw%vnx4&xK1NK7YN z&@y=*=VU~3opx^gEPx5aEvMl!op7#`=^o(3P(Rb1=j6ECIc3Gps9dLWf2UtW(E5q8 ze&{-_-3PKvG|42_87UHRaycyw`EG_VWWGDgF?;4Zee)cDzSB42bj^3#%QG#S?{tN9 z7{=-2wtS|OZ>=r|+Akxc11Kgu)iuNE;STqAau}J$MJMUg|1mnp47?-xQpPE9uB^x!OR39$BUF5^;+Q~ zr>nInmyLvT^POxE;n*OWMz^LqW@b_A(f6@S7!ncbjIqG$%SBkNghd(YrnN#S&aV62 z8M)3FhDR~-v?>&ITSY~=K&|26v(n&n6lA)`!RHxnvuh5yGELiZx>&cNjuj3UyGcqfz-2FLT@ujA| z)-xwC);-p3u3X@G)_V%y>Y|^!I^DqUbyqr07P29yOQqntT5xr--UJt=c5$0|eVNNd zalYGn;RK<+b+eF~<+ir017q09vUZ+`_B(>dbn+12*0dsoTQ^J`RMYYnf#p832wzgT zbrNR5ENiOhmnzHzVW}W6KDt^NMUaG!jNxaAnYFXqN`>vMqjUck*8N{=e6i5@x&NKUFz){YjXAb4?ftJ+z7#5V zL>xP2zSA+n5u6uBIG7nlE?%27uf&_U*2vi>1HVa7gz^96ak-dltXpi1@+_wlRyRp2 zL^()(fj$Kmzx6k;dxz$_bDhB$SK%=js@Abs2~eX`u2V=};g;u*V^mHNG0q{|)xwMu zu~xG%PYq(77Ko*e^zIlzSh1`%98ASnrcfWLp50}d@8p8sy}-%kT0B%tjjYU}q*9>* z_7Y;{<4lhQ%8S`C3)w)f6`YD?8#8Ve=2>d*?Z&xnJ_cO7wrhaBAJ{wKSIOKKW~e}} z6Yj@(b2n-St%v>(Z}$NnM|J=Ef8=F_amNMQfQ@WyFc=rf9ZXs6t}NMV>`ImmghjSx zTgJAGBo`p2_ZlG700GlN2pvL8=q*5~A(T)hd_Y)`JVHh*_Gh;`#<-&|9ka3 z_G_oloH=v)?8ay7^WBF`oZX{Gmyo_Arc-j|fcWrO?}_n}*l$$E7%?K=dppf|MVDC= zTWjHRy=D)wH55cP^Xc`r^36RMNAT`A0H3}m| z)S}o&_QV&*&gwbWC(z1>m7r_Ov6k`0i^tX#D=B|uy&{84z_qgnZD%UEv7d#rZOIm~ zVMSVYj3Sh!HCq=KSz0uyxI{;>4K>g1=@`39qb$vtYdO&;8;jy)+IWycM0at3*3jH7 z=En7d<@&Tx|Lf$wU039ep+tUQ>@2OPOVOv7tl+2pZm$e#$f)@C+u8s9-T(38dC`%z zt{u7OsQ4Hc!AbBeHP*f_(A^kP9Q*TTKE1qIanN1OMEg0p*!hj7OX(BGwrY4Y*9SN1>q3FY|>mN2gV+9H)C*YsKRo1e1%S< zPf3Z2go|8U*A@88dUq|*4o}*sdtx`k?P<1V?H*1KjQzpFdaw$S7CnZ?hL_BakBlvI z+YM8ZMQMoEx4S(%zY9D4d2Sc+;qKxU3W@kol_=vXmF%WX6wh`miI23?afOuP*lC9- zqUj{;u`7;Up;B${*m6x;>~hga5#?1&i~Qy45wL<;O8csr9UrFxhi>Vn&LWqETQcA? zx6xMQu=rT&&eSD#9J6T9Y?VpB>orjq99ysZ(^o5L?b-S;DL!3~>fj-LHKQ&+V@SL{ z)=?DS&K_fx9LMTncCqcYcky@2lK6m$D(#NZjU5!P+b%xdrbbzgEV;~QHu}pX;wx#K z68n$h+W&Us=)09WsII#IT%VPXkM*8yrR~^K<+yeoy^4qFs zhZHHyRFc12sm{RISAh%Jfw4<;dhubz`?cZ2*Ee>OBArSyicQ<9nA?9_6+!OXSfXU- zo*owTV@Oc9SIAtUM_YHv9zA>FyP8kFl{Ne1+akeFC*RvnQ&w=WE%(W|#h!wM+wES{ z?%w|o3HV>TCE!#4zZ391x+dW6vDrRM35N`Kv8yEZ)nT2gA;pe~=|>T}B<1%_)2^x}v4#kBptu(-(T*UteM? z>MYLDY4(j>YYE{0cosUiPC;c1#pnr~%jEx~b2+!?M4jTO*gvClIoF-b@BW{kOYhi4 zoXcC$xm@7RO zXyRh_(;JJ%x<-Jm)xsM#E3zjnc1_%J^XJuQptBe}%IvGdkg;qu-7y5}S8x-VR#l%hEH zx@IV69IYH^sMV*H1{QCv6*pKddXlT_xZ3oPs5U*+=Moc(=UKfvK6Io@y2oh;qhkXn z#;3d19TwmX|%AKokZ#5!5b*K0a zqvAuR#mD$c^(59Q9Tc}ht)>1}%XWE9aqQzZMY28ZT6HwbCPwcW@2OS+-#B11^k}F6 z+Bf#5J;qA(2D?J#ma)@Ru<9TCRC$jc2c0fu&FMOo*fmP^Tr}A>_PC1?{~Jl+|6e6p z-R|eCnIU#mTs6a@*!S+W--&R!8Bi1D`{351^YTLdO z*D6J>;1x#IzeG_rik^y{7Zt=#pM9%&A-3A~G0;cb!Qrjb`RmpxZB-V*ty6m2H+HEN z77K3OQ>sk#kKL$cU2fgDpU$`b-&R2EKE%#E*dAw#k&D2ui#f(zq=bjn)dFSGkS zvs@&+)Pj5Vr0NAFv75H&a?fr%q^P9Jjd^x+h0!1drTzvh-FVuvqgcNpRTKtVDc`kj zsWA4HW$3XJdz2I}B?-|z`dOHOsNkpi(CLTSI(@>K#Hwj}nv3G&M#ZOZ=bo3Dni@J` zl0}`qCAx)*b1I3tvn-xe5++Dic2QCiPWO%d%csPn^;oLJJ>ACzwJiSMOLmK5N4SfA zzR2B*Yjkxw=lxXRRdlz)X6*GM_aHpzuKN|g+U19J3*pPHMbcNECr^&|)Lk7J@2Se6 z>XVkct7&bE;%TZ^D!CmKpI;L1v$JOGsG6TCE_Q+4xWO*b8@NM!%!v5FQYD2xM^GhXsAW`RcD67bM9MgNl-dDff7i(?KeMuL z?2W_Jh&?*K?Sy#W$;#C(vMW;Y@b$xr1{Dt(;o3fnbgr7Uzhx!;WBu&pV{28(v(qn& z_t`c+e~ev0-{LVnHt!PAeltYpx0PC)w~4*H(oS`d3J=@G&en!%{Zm;)k?gp>*7O&P zebYWs)rlgltcT(~wFg>lV2~APM#s)uS)%zn#~uh2R3$WNZE_2T#m==oZ)ML4rJHy4 zb>0>=-?k!G>{q=@6p*SzsE(i$P#m|Xs`og{xhwVro>kR))ShGd14I zNs&AIa_vx;gDK`HthJ3r6@`n!-cF@w?9aWd72xKzmiDSHtH;9rYdAxXUR}MVs zKy5U{Qo5rotYcs4+17o$SohBA-CHUP?;HEp5=^B6sxuIQtPx<6qR&#z!c&sODiawy=b{#8!-*qFl5j_PH7@2FA|RXTRg^VjpSF znAmAL_w8bz>MSP3&g!K~nnlvl@%ZR??@`+91Fd9j?v}(IuM4xArgX~J>5G&)=n|gQ z@wU_L*;!Su2|9u8t!-A8nF}n;zV21jqj#6c_>e_LH4PLM>ypZf_i)kjt{+FsE|E~N zuQ>L{!!25Ni+=YJ{l2z9E{uN1sfSCwC^|vAH={`r_i#7Po@rl^QPD%IY*D-iC6yJ{ z3$SIpWKw+a_VKt1ITr5fH5ja!N(Rc@4SjuuT|)kbZW>b5?TP!;F48}7zxeT``6upa zp12#@OS(RB|NX^&#Kk`0F4kJ@i(@wpE~<5B^+&+DkcmOu=P-PZjkJZd*#TZMLfyLdnQUlGc>lm@GHzvq5-W6CY6 zXya{Tm#wfAMa}#}Z2lN`O&3Pj)afqiZH231l~R=6#kDH1`2L(tyRyd<}1 zWln=HI$N7p1{K-*Tso7|rRXabS zW94eswZkQYshA_WkV)Wo2^J^EEF>h?%H(^YUfm^74X$b zov^zPWi#z~nQZ-(GHsO1B-1rIIqL+sj_%yzjwQMFmSwrlK&w=1@WSNqLuqtw6`4eh zcC6ob%Isa1o)hG98m7}ZQ`=P5CF>d+bf~tLRk_wBZo0{)Q!R_uE~{x<-P+mKp3`Re z0Itg>b;fn|xm3C#oovwME@@rY+M(4tmbWhL407cf{1Vt{b#%6`UEI00y(OrsN+#!N zuNo$>beS%vrY4z7&)2QVB@-E4T)IZ_E)|_`GPAJ0p)QwArgQZPox2XCyO*+Sw|kk% zHdI9GTDVu~hF2*9?W27ttSmxj8}vQ7VeC#eWE*p-s>B@Kw%Tm6dR}f$qN>&h@03#8 zq`a|WvO;&&(q$G34f|9it23IPoL8r_uAZODChU%d`)jJIsLCbkT^vi+)z2{KsiQZC$P6Tj?xC zphQE1+gWrjgjJ??j)K8IMJ~*2d!2hzgF+%&Il6br>bm5-Tq4;}H9s9KRlq1R2%71vaUW^)1Yto4zD{rKt&>zR!}xHSftVelFV4t4A;^l;OD0iU_>AI`p4`G{mQ7XF*^YH9tLIk-7X3@7>umhFX@pFt#-G_E zwAJpjwfi^~fi?VWQM1mMlu4&pyH7@!*}~A2*0$XG_SVjp+^RN>8M9Gx_N;bj>|3t2 zqdlmowui^ZEhTe0P^n7|Iy%|jo)CY-%gXZURMwrMORX%v`s61_R+i3Jg3?fM5B;N4 z+gM$ltFNo7wI?SGzht_)y0Ka@xuPl8SU)FYcaiYa^<~nEF9o;J9;`Y=+h}t=BbHjF zYw8;oMl-`GkxV4@7+2(6#0sK;I~^^Zol03da_igLmGJ}`4A;`$-qs#eCF?UmdA**q zd8sNzP=$)#h_XqG8J6fKD<_jsvXelA0CUYtmbCkj4X?^Qj4my$QL@kV*a_r1*0i)N z3D&f&*9fAuYm^+>T@KdercBLEnP#DAPrVLZoy?Tlg}V=)vT!g_bS0K^`dC&r4W|=* zmbj5)iauf7$hIhEX}DB4d?_4*rDIlB<)U<7$+5yLkx%y;Yg6e=MRi@1Zfu!u>}1_o zAB)Qyv$>|KR6}L1G*@2L5ZJ;B{a@EuT5SOq21Y^3S(%v^r3h8p@d6ibEaCP~OG+8M zJvFJ)d2-0&h zmKQ0BYp`@8m&o{>dy0}uWo#COG8P$KS9x_Ko~*Y)2ckP zqH0d~tXfGdm99=KbOpDprEPV!schgbt*TAeY#S%nwriYir;2QI^mO?M6&-o+#&o07 zG9`M^tT3v$TW2vTn^BHjW*aJ4UBp+`AKtn2-eJ(Dt(+HhXpFLzXmodTiw^G8=t%|_ zE?@78FqWKks2t@+7q+gp%s{DBKHUqSct!5;%6T-y^HS29am8i|y%tBUsHg&&ds5up zE1Q}xC1%p~=|qEKLpl-O0lyA+Q1LZ9RHD8 z9!tY)*s@PylQk-hXBv`;>Kb3>u*}LmTRK#@w;XbDvvLN7S4(@RQtNOh<<*JWdAVd|TE!I7bd?4ar^>SnEoo30Fq

P9u+q+#ZX>qG|EIv?$n8ocuM)$VDZB&qUxtJf` zeOJ-RHYlP;SDY$yC0A9flu{@ku(Fk&{;JxFy3$-tB0Eok?n^MbdDS{&_t2NC>>Mm| z1t^yk<-;$XOO$7$93YBr`o&*Wr7U|QEoOXh&gxM*fC`wpQp*c#8>)juV?$j^<*EE> zx_V9~k<}gLY%GuRr)i}zJGZLpOpPo47DkJ7L!}Zzg=AV~PRn|&Fww09>gsjbI+ev! zdpG1#mA)DmRWy9rN#UTJurSwin<=`_QK{4_v8n*nS@GR!P1B}oeccdUloe-vp*Bz= zpz1{Um=hnZ3h1g_nRKACrlsgg7s4bt{9p;IOQe0>kYY+ul~(0Thf;aa6$cA%gr)Q@ z+^8QCUS;8JwODAy(sjAAS-B|`Ny@adsHkA^MPcVsfO0Fl=SzkuAD4*)i`&+&?#!)f z-e7k}&#G?D!n&lcReK8`J6{4zq$VqY&~4O(y2ZXwPCB=~xwX@(!Wu4Z!{S|iZk?Ty zVo1KU8Q!nboK@HADk}1oLKllQxhAdpohz?~$%QXX*eP=_l{@?FbFyy(P*q>!zkMaz9w1kQ zu@t79;(|-`w7or!`S4D!wxq)qy_Ghqgr>VTBd1!ruT{HhMR-=><6ha6vph|;R6X$I z;l4y~nOV5D3r%--T~Q-f+gMYsXT- zve`=a;qzf->Zl0pa?);>nyjm-udB6I0C$P`_6ipe-Il5xqk`pBm4T}3>+~a1Y7A(Y zmyd~INW0+6y7r>LWiK`9nx=$G%wZr~^ogoA4H?%g5j|#!R4U^eVicEE!HrV<(ivd^ zAi5&883oOY^SYQ>iId8V%2kJ7P8Y z3Y9dgx$*u{P!vw(3l;Abl9gFsFo+i91F)(#sjSIo{cBfuv@ToSvZO?3 z)$Z?~;zo2WVYN*uJRxl660D)cRJv8`0Gt*TDZE>M!|+sW)^)n}^a`-*O^UKQ4I zpKI2rjYfg2n-Ny~+FRDNGlAKDbDmUj=wdULJ!UrJRm{sjQ z6&2F+0hcc^xrmiaRn^u6mCfx-D%@K@3XlBWbhDy7y+-Xl<#noOx@&D)xkUL;$AP(( zYWi6jsLr=^?drwuO`u@Os%90~4$8Hzu_A}%Q$7cpR;IRNU$)CP_WGo~qAsKCDoos6 z@z0ugtRN9RL17}Gx`firuz|`_3N`*%My*>wD}b+5WZmmVNsAPfhgec<#c$Uh8r?)I z7AY7~G*m>9lLp}qU4_q2iBvj-wOjdHXvK`GG%>xPsHh!U6V&vn`VbwdpcGfo5N)+g z%R{Xt(IQ{AF_}zfv#NcyEm7-gZgumj78m!U2U~|*-fAUk_uiK)*Xc06#G{xJCO3_> z*~a?%x{MV86pkt?S%O`!=;RWza5YOjRg(1Uxh4oJ;-slL`O2MZ-t`~DBJz~5)q2Ks z?bSE_`EUw%Ome6D=Q4lS>=8CYsR1lmX${7ilr?Dw-5LV(MTb-(8C?)N3?qTB_!T^k zED|ZbIFE`PQr(3*ox`e1MRk`U@~7ZX0mIAiIPEA z3N6dIWHMWwOsOG67voDLQxqO94|jC{OOvaV2S!&>Rh6koWxZZ~!?Wa6bHK(#c zuL4_pl<(+hUA<0agC$WmriicVmD-eCCn=pp3fpe^cDd zJVWin8gHx{!kpLI#woem#~X*0u;n+v(tCA!Gg zr3dGi&r(8RjSI;pCBXS)H{X%!>&iic(q?Nr2@+O1PA^bO(3G$i@ap;+wFw8cVUI&+ zbMs=Csw6Xsf(Iz9;HsfQt)GdcT54U}LP55o*QBkUf#jVrUI%(}PeBrm?jMcE$;M$O?(-w(nI|~zp8bxSpCi#g5 zQ$Nf1?zlR;wVh{-nuQ1oP`OYhqO4`--+*tH)^4OEsUhEZp_uL-z9aW0q2mRmb@jdcTrVPI|V z)-+}be?^`8Tr4M36+#E{t*?4Vebp+9{wkU_CDjwDCH2*HD&PdQ^Q)4+5~m`GC*hxi+dF$$>Z7zDJ)Qe0_NmpgLOi=AwZ>@%-GD0{YKnp9a=h(GT zS^)S5QRQ{Nh8pGWhE2p%1S2aD+qR9tP_~9bd_r1O6?~o4O!N?eD}$k zYDJmpN}yfMp)^dVtJ=h!_HNIf7C|dMrLH{DyvjPRkus6#u2D|V4aq}Ni00m%z`e(`*5~Z zL6wU)>Ol;L%!G^V;q2NyWJNuNvCcPK$7heEY_tow@g~jdT9js4E0t0Z`b%e8e`&r{ z7^N{`mBzQ)xtf^Y^v8`IuD#X8f9pF~+N@DRmNn{5+GQ76%~B-VNGtO>n&foPIX?IF`|RfWS>z(cfy+gEy7OL z{*4NyBIR{T_oKDlwfO>@I-?jVWOqqrpmuk79yzrkwyV)4w^|89OMAYyL2Hmzkn+Wr zjEaR-ZD|!%RGqiTW=Ve-8a!lbI8+HUYUIos-ip!abo3=Eo2Z8r*ZYf7cmkflPAvhQkf#iTNe$(C^`E;m|QU(gn1qhPv41%@cr zD5f_0W=Nmi>p{y_Dn^7On=FUd5E(tgmRc5$mGR?f!fJ&Jr0`OEz*E%1A#iVXuyPhI6_8BVAIJvR!6{w@l5=%$cbN%bE`gySoZ1?p>M%+FMkP zU)s9NM%+c|T(VL_-F%%Xok&)ymqLxExeXdc7iAt%Yn+BB`IaDSqX?gWE0`-&)$O!A z*!sxAqL!K;qmRn47I!Se6HP-kRto)e5=-Pc*oyZzpPgqS-bwI!HZZ~g=zlT#Q{%?F2lN(9N z?NkT9zprI(0HD77%m$+}Yl;#?>*!Lk(MF?bG@>6=K(<<#(zzNq8DQA^t8&s@|+NN{{DiY{>pR8fTjSefdk&*6JS^sue_V6V` z#T`p#5B8mgHXbG0qSm#-=QKRHJNvA)O;{gKwMKUai8&3WjkOheGQ((~po%``BbN<{ zBc7>eEBcs^TpFAe&CNIBs5dK`n~z>)`9Ut>bFQ&Ajn-)qC0zBs3Z+EEw{Q7YPL1cY zaX)rJ1vzxN<KPrErNE*5S1jU5+8<&m3+9R7AI#|tCpo|X-|b~ zR#xDL>s$D_oFdy))sULat^BFwKYF zw1O&rL2{;=v>$Grt+Pv3LZav02L4(*wsjCBEL~ql>9$Sd0qq+LEe~;xZIpy)-}kr2 z6ZaRMU?=NWt#PB!YnoRp0S_s`{I*v{VHt_Y6?Jh!*F=ed<(q?n<|#g>KYcnI8CPPQKovE@$cpoSUx#wCTIp zR$1ItN}&isYfzK*s`+wN$8uHIN}?V+^-}y~)NQJF(Nei_Vb@+5H&bcVlWD>71O4qilQ4kh2teMvjh=?`|2gbUbqhJ`RuY34Ge`;Bc!g*T$S(%nk zoTlXyr)l~7rhY!fBMmewXc3;4e_E!^P;-OEY!J%bn@yu`)cmtz#ih=mJd@Qu@F_*G zq@z98x=Q^-nWS15TtruXtrk>Y&i7yR7btnMVuYH)>MOI8eL+^01D6WaC+8&s{a0@P zCA$u9a;aHiObI$yt?4#Qs-h{aV!l0aVO*S^518rsfSH~TnCVjk`rq`GfUXZNuwiws zWUptTQP~1YIuh~m#7k_lksD^Rj1O~PHE)H^|`k-iYh_!gSXWG71gHHb`y=S+ptEr zO>N3+TU07jytll>HCDD3RQmn60)?wfCR9uCLl&(uN-a<-5m~|5f5_J$@=aTrCO3x3 zB{6zdNeul-x~3eZoKaY4lx1Z?uQOD;CntP+=EsfCE*EnrG|PwXtcoCPVc|T}`S|Mk zH8r}vty3=?Sy`Q%8&$V`rs#SC5*1b&Xa5?uq^Cxg9-d&>dTI6S>N@qbgbV!GGFRMF z1$>U$=+xgcFYRBd3GACJgOuf^7FN!Rpu9-~=fds%$Qw5#%~hu@{KAC8wSn3@3Thcy z+@=AtUFyzi3CI^L-2h76cDE1RG3&3&Ovz_Cx)fK$lZs+fG!Q)>N!*Rsmu^}^-O9Gr z%StTeo!_J^Gb+yNChDwGDunr@+s;1U4xd$&3$LdzJgTc|=Y?-1F3;KAtB30_gi}^$`9Y#qiK&53Wp}5j{coLaxLc_sal5EW+zA&E8 zrLFj`5VGMNVUk>`M@n7Su9KCLf>!dS&vfnN=#yUAaV64pZCUhbO7uyA%2EyT=acFg zeA1|HKBs=!b+^5gYd+FkpFHAkvm zVXZ-`X8951)Z3ac*<#_nCr@^wKjsI+D^l56AmnFTa}~RNMqJ~BI`Sv8Oh==k%DxoO47>4 z=#mdlHD8<2=!o#`F0w&Ce9Co!(QfXFi@J$Ad0+e1=WtJ|DmP{|xPbvuE_V#nA>8So z$u7mB{5HJ2n4LrWhHq0T9R3ro8#PgBxLs|dh8U=3UyuSvZ&vy}x=e|JyRUe-{JtVT zentsfxa%;|Cacv@qYfnX^eCPtQ+7vO-a%=)RK@9V8=vwL>v)Z&wL^`7iw{)7rZx`M zg8<*X{I*7QG+s))nG9Yf7zkO$mcq z)u*|K%f&8BAFNy7jgC-h#&?-a4x*3w=e3|g#EO3EuywT|Yv%LAAXBP0MrY;=l$Fr{ zJF5}+!ce$M7?iHn$3;U0L%7i873sPvmq+G@CMzwr>W3P-G+w^CT-i@fLl5gTtU?KH z!@RDWS0_{nsL{))c89x;^9&EuKQt|xEVW^>Gc~^1 zZnSFIu8tPIs~2_5MypS?P6$RK@rG+S*wV`TVMWTuo>Zk4ghgHplIR7!D8w~3)&>k$ z>8&-bu1*{KUria|>$fg(@`I|Q!1r;)x;ZQ~7DQn<{c|~21(NJ)oFNYht z=RkMc^|`wj4V7s9M1+naN4wIq}(cNVDl}YZp_b*UwITHa^8#h}+CJ8e)&Fmm!ySRN=~iNQJhk^x))ZX;hpY1FkeHrXP=SAvNX^u{<*fLIrWn*Q@5(U z|DkiV(Xvq(xLie=n>0wb8A;S=woy@+tr5^HoC|# zXcJjW(5=f=uQsjruSAu0eH+c*J2xeqV5qVX@S`R>ORa+o$A^Q_qWqx85kUC~L){AKi8L znsO9w1;q+obybDW8l%Pek(y;TQZsxCyHpQ-Ns?DX^hkAv8gCw0SB&om z(0D0z4_ddGYrC-_|Eu(J&q|G*w{UaCE!Ep};%YZ(XjOD^4O(Yb2xglJWPEBEB_< z@kXB>Eqi6%#-q8=uBdKGTc?G!k@|{HojozNZL4cEB*=O$HN3(HqkFAH+cG5BH&=Fv zybQyLBGlA^;i|3>!Jsp{u7Yj>dq*H)SEEc}EK41;R{Y5{MYlvd@uQvnvteD;{)N}@?zjZE@UR7qSy8jSdq=9q zF49Fe-L!nSluAwcM53KRkg9syFmer+&+3Z+Y;d|-`w9jusR|h0F*OaU>BWzZcdvP%593YG6G!$PS>fVlTmcwwCWa_b&f`>c&Y%0(rueB+{J@8Pw%f>ySB zg(G~r%G^WStyol8h>Fs1_ab`OgCFj^Ficz-$XdTCzPR_PU0amOQei zlKK<$(bKpv+mNpDDW882t018WTlxwIB`VWtTidR85yNv=T`SvI zuKIJ8r4xQApN&paTZbAiYz$(U(Q41pQ>(_`szkXTjh}XxU}Y;yTnpo$jp~T1S{4~C zQA?KldZK@pOYQ3^q8dwdRu;_eWd{GMc|k2z9d@q1S2+AN8f)dAfr5@MO9g%Zo*y}_ z?9C6wEeItSGYa10$kl6*b+tmmUX@YfnpMs77d|83>Rou(6^gE%Aqt=wYCt3DE_3yi zf*$4Y3l@~=S|u)MK2X_S^a@OPV|3qZvNlA*)sfwRw{TJTsOZ~z=G3~LRvXBpgi*yC zy(!>IsRac+UQ2TwrB=jCsr?{)M@IqSXSwh4P+4F`G-tZMT?v1?{8}1PVJ%PYe~po9 zZ`a5YRn6V|CB7lhcMqlXx~vW6P*vEsPx^pVy~4i4$l{4oD7tLM1w4!zoYh2MoL7B4Prn)ktrD1c_jN$H#WrXuGE`k+g5K6V? zh3{Xw-e^DW)5gn2w{o%$Y>`)|PANO=4D=&hb?-FHwfntks>{qH32-eSOE=IYt4mSM z$~9T(D6Sn}z0=lytN_!Vvh#gb>I)c_GAUrKuPth6)rE(Rt}2cxFq9ej)l|9GS0v?I zado4kHI>1syRtT=!3nh3YJiN@7j$&}@0&KQq!3<->l#h1FH%_G(Ai_>xa`ts5X*?MKgh{+;(Qw^0GoWww5Zu%d`!s)E^?Ys=g^9y}TU%5sRM~m{U?Dkb<+#nUu?WuM*NIe5C zSPLG3`e?%zNz=ZJd!$9AF)=P)$Fq=Y`JXnsM{W77JGnygDR6;^s& zK}_}IX!XLh(5m&8c&VDk%h2J$+)i!GimSkdbMr5gxCg~X>iC+Pi!n+o{0Ivdd7}ds zR4Y{Ya^I!mhP+m*=;T8=3~gTCE?3RSg+AXrRIa$@rwJm3yPwVvXz>-csO>(iOZ#9~ zB4z8Vuh`*lf|4pX<&Ty0_afANlR$+x|&rsvvqU=$=EI$!q z;VZ$`+!&1mvYbwRmHuUdv|0jc>KomgDsFaJRQ-#-II>$p$Y2?Nmy%Ts%2VR5LRfgR z{z0=x%yKuMbXtXXoxinKe#|%SXe#Jf-`cr&xqs&&+DrcF*2^|?@|9kFX^qB^E>oJ_ z5iGOPwfp%|8xyapqkp?8rKhq|ml^OOpOoZxT3x62(ezj<4kl{VQEGQ1JvBOdl;)_h zJepZhIrIHC+E&FGA7!kb(52+uwSB;U*@SwdZ8V1^aDEhA7-snsODZj^)H`X>gQ3JB zd`6T$_yUR2@lBlJ9m`*&>bte- ze`VmjBB*;mKyL&pQ1yC(Jrot;)1eO+cOM44Ny??BWS z$OOThWOCP%arUNAqJ33KS|j|IEYbHsG=#s8>s}rTfA@B$|Nd1X|4Y|D=&vZ~@$-It z`nq4fwjb)Wzs>Zo@K>JyPp9n{nG5%4zsy{sf8n3~LUXd;X2%pY_Ij{ikm$X@6O0L0 zkoN1%$$o>6i66V!ak1ljoK|#TuO}aQ_#v%d-n*n=y}A0F=-20%*s)qC*{@{(Uj6zc zdUrjZ{ql2pzmlVS9<%we#mB{u-|Pf^&;4md!MK9`T&~aM{e~S=d~E!<&5n>-P2=>-oQ!e$ltEyDslK6$^TITi!e9tL-h6 z?D_4XFR_6a=TD$8W`vyB}v2Aa0q=%N<_RICp|JmO2e=+@@d)Mvz1$%0- zZ9iB4dPKkX?zf2r{kyH--|hdw=(hIvEAoFV*s|ODTLukUW~*CT&_m1Z{4UWy|F>oM z!5Iq%b=!WBTmL^%wDHUPMA61CPZdlT?l2Y%>9)Ti{`{krhD4w2Lo68DZT+Ec{k@{= z9olXE;oa6B-fj6d-Ij0DZTX09%SUuuzFoKF+qv^8iOy%cZtIWgw*Dx$em*{o>bCy& z-PYgUt)EZBx9_(8*lz2Ob?e(b_J3o;56+mD+WpS|b)AX@JLMPYQ!E(YZMraru;rEu z=Ko@WrF{9nSWuRq(5F~1wcGUcZqw7cP0w`Cjs>r!JOlOrI+>r22gi1qE)LG=GQD~5 zn=aEmgS(ivGasn*!}2ZLpXJ{J6`HTh@Na-V{FnaOa?4)_>iPRNTqte1e$YDlv+3d8 zrYC6HW?6nZP|wpIOxtk>>Uo&QwB?Zl72g-w%KX{>axAy}Z(uMyIFRX6-1IiV2Bs~K z8yJiT&S2W|vVp;N!6v5HxaFgQo0*>Mrne6sVfp|!JvMkz)Ana~%B2pz?51zy9}~Tx z_!F-%jL~;ibQ^kMofqNEuA^>#qBt0K+*s*h3`VMQr5jI zWnGxeNEUprMfcI=tm1kAdAI7nsVVv{>#lDhvUR@WHaw#1o?^mXRQOH0%(Kf5PcQAh zUAB8@hC{jB@YhxL^Y-EE+&_B9Dx6XH&R#e#`i}AL@4Q(2=+PLsGGMQ!z{P_e3j$Y; z>a{Qk4$*Sco||4urmLBrZz@@`G|jYlXq~+ZnkN6om$`0RGYTH9=d2tk9zDAsDvW-_jQ3DIw{+}hju#HtP6r+X1y=V_Sjp; zwdsrx*B)7plk?%;LkF2`%l8dba*}EGtHOZg%sr%n&Z$cddQ=9%D6=XEtlVhJEga0< zP>bBOPQj^L>|Bg1unjljF?b@Li&x-p@gaNzEq%1(Z*Ji$Ej={1!?8FXOK}G7j!CS- zI&8#!u^E@)D(t|6@o+pAPew~G?flNgi|{hM8n4G&@h-d%EgiM}{28Cam+*Cb8$ZBL z@GJZdV~Y2-zb&vo4#9136z+%=o-uki;gR{CJ!)fWfjHaHr0!pS%T_rNq(V;1+pW?YVKxDGes zF?cebiRa@bcoklUx8fi00elRf!58s$ds#evDt?_ZW}+aO#7D zaBCce<8TsA$K5f7^Du)8@c>+gt8p#<9FNA6@GQI#ufXf@HoO=AgwNvN@E`aQeu+O| zPh~(BU$(@paeLear{Nwr2kUVmF2Vz`6F1^SWPf?9z$^)&ceC4FRsKB@NB#m@5ZO_4g3UqsA6fy z8-!zU8dhKvF2{rMB)k%D#>ep${0P6t{{8)NORyBnF^fxZEgpyG;&1RldHFzYR ziI?Fm_z?aT-^H(S3pF9y`EQNmaW>ZA{@8{`;2F3HZ^oza75p6Isu0@ow!$58CRX7- zcp&~9PsNMzdb}5(!N22YxS1-9cHAMj1D0bQF2fCYB3^*k;2-eM_!|Bf23z~%ZHc3C z3Z}3Tm*RRn0nf+Z;$8RzzKZ|CUfcNN4#i2h7w(OVumg|5v++v24Ijmq@O}IihpL0f z!gmbri|u$c{t~ai-{T|rB7TlVYJ0H#4##O&j{D#`JQ^Rx=kX)lVx-^SRyYyoViUIE z$#@>#fKT8{_zCt^6S$r4)>wwMxG#3#>3AXDf=}bC_yulR;`cuir{f%4fUS54o{Sgb zwRktajPK$PIAD}N-Y9Irb$B)2iSOd)*k`ogegsa$J+U5}aU-6DoA73Q5TD0)@GI=O zy+7V?+!=SnCR~C)$5ZiQyb~Y6Z?WeXzyA^}$1E;EVWA{04iE^~c#3 zC*U4fhX>*Y`~_Z$H{k>L7knGP#DP2b<86mCFpCG^20Rfjz-#ak{0n}F-(kNU{c(22 z8CZu0;6ZpQUVt~@llV9M4Ev8G+;A$^1pk14!Z-0d>^0Hve>Coa^Kda9j;G+|crX4L z-^MR-^GSaH!*D7la3QY1L-Aa^9RGlS#((0M*l)5w&UUyPR^kEpb373*#hdT}d>uc; z%}V|LOK<|}EpHcJ^_7;+Ww-%jZzXag+TaC+cEuM;3_BU{!{$^#^X%XTaNBHEAe1F1Fyw9@m-8f_1g`=ahSrru@#TSGx4{07e0aS;TPC< znm^7+oP_gm0j|L#@l3o9@51-+-`H!q-~SG%uV!-LF%S2{Rd^zvgV*6b_%wcq|Hdt6 z`2CJXeUqI#P95%top>ysgE!$l_yWF%|HfW3{eHK>U2u1-#TB?7PseNUc6=J{9c z%O7Vjj>YLX2Nz%~9)c(1g?KIAjZfhl_zCvd)gN~dj=^bIflb(fN8ovQH9myT;`>;< z8^^)%I2#vW3vR^o@k+cKU&eRw2OKclA7>Ywg?r;7?7(C2Y`hY0!$@N<=X!8F z&cOy;i5u~Jyb|xmr|<*(8h78rA7?Hu!VWwgFT^+TUs$}S-+m~L!&x{N_r;aC5l_Qk z;|+KpK8ydtZ*kCG{PJO+{S?{^%|!nwFFuE%5WLcA95 z#;5QD{2B+$^~V{7WthYUY{7MSJYI%3;G_5wzK`ExpLzaxBXA<_iTmPmJOaQWIPXVz$fq} z`~+=mjnywl;&@DA1Fpf1_*=XSU%-Fhf3Req3{2T{l{C-E^TwIDBcrspvx8M`_9)5v+ zvz#wZNB#PmyMHTiJ)Vx&;O+P{zKP#quLi%L(KrQDcmS@#WAReF4j;xB@G}e={r-pH zR7~JPT!Dw;DR>dyfe+(r_+J>z_s7{1N8=ti4;N!69*gJTRrmltjql;V(Z=@K^Roj^ z!FjkJuEN9cbi4%rfPca_@l%W~@W&a9V{tlWFo)~$1Uw&a#ryGP`~d%heHZ%Ujl@Yf z4;SDXJO$6k8}Ui}8*a0Y-|r;c9e;)g;Td=%-hL{r)E49NZUMaU-6KSKvMP zXZ$yAzMtRk6ii?pF2;lKSo}5KjL+e__$~JTncx2iEX6%>AuhvHaT7j_uiyu`-~N8T z$KyqKAHIe?a(=z-a2lpCi)-+3JR7gUJMlIA9D5z$_rCy_;X1qzpTsxt9sCeK#jo*u z+^pH}zcTCG#^tyMkHQo1H2fw03a`RD@E&{!pTHOKef$`|#Q$Jykw5SLI0|>f ziMT6PV+I#s4iChQcr>1b=ip^{1O5>o!x!-*{0>Jf_UAhRcgGrBh8=hWo`sj-wRk7K zgm2@g_yZ1F;*YC=@GgCwj>lTSc*xk!aAIfi?9<9!6Wfh{54*Izr)+{F?yOq`4L*o2F5Egp(T;c0jYUWvcMoA7qL8z02S@M-)jzKWk>kLBDa9F1jIju~8p z?RXTPiJR~yydR&%zvHLaqm|?1Xe`5W%-~A=Ii7+S;_vVe_yoR!AL4(o&kBG1ZE+Wz zjn%jx9*5`PmH2yn8sET=alnE8I3+k4_riKyfrsEpcme(v@5IOOWqcpM!7(fSai?Mm z8*ve?#+&eNd>miIxA6=71~*^jk23_f$5PxAYj9s&f$Q;DJPR+y8}K#!5Wm5mtNrn} z!ZBEedtoi^hbwRc9*4igO?U&|jZffr*uTvme;Dq7Q?VTDaerKihu{f#4qlEo;l21I zUUHB>?oIe0K88=@3-}g(j6u8KegKx>WZVnu@c>+dN8m5;5_|(c#*z+yoXI#B7h@+L zg{R|%cs2eWAHb*aReT@6!p%DUaks>gI38zW1vcQpcr0FkSK%#qAHIn1;n&!6tv~)S z9EUTp5*Ofd+<+(GdH5T=9UsLP@jd(+d#>a7I1XoGB`(0_xB<_@-{9@|D87jAVUP9x zcmr`XmSH(&a1plSQFtb9!kh4Zd=~$XpJI;<93Mwx8J1%P7vWKOCT_x;@P2$2Kf?Y8 z`{R{hDVAdvm*84F4ll(!@F9F1Kf_*!=r}4{^*85g9HhBt5KLiuPqRYb^MIAiUw})P zzZ?%Twf%atG6;^rGns!L)0g6JP3`|Wyvx+~_p$s%re9QFOzm$dZp-}1rq-KoYQIU`oB2&lAAqf<_Ol8PF}3{>EI*g&iZXzI9sX8IX?8DGN>O&#Yuri%{q`|WLN{+6cpGn)B3;AEChXL*wOb1=*D zg}4TfHx-Vjo7)7z#Z3R!)b(74H#7eprXRpZO}j3Zzl#54`A7IU^Lrfbk2e5E<0PDo zRX86P;~G2}&ozez!IezkWa_+sk9RTu5vCu({JG0%>RVxFYp`Y7a!sG-wXSj z_IxwF9gboCWTvO$9Ol=VQ-ffCrdP0hHFmK42$uhn=?hGS_cf-j^Lo6MwlzoC!CH+JOJDAaJ&+4!H4lVd;>qio=5rPY>iW~7Wc(gJQ~l&>+z5H6#f&x#LbTO z$Jq)e<6K;TD{ws?i)Z1bcr)IMFXLv%_~Q)3?Qj>Ig%#L4P^j`LUMzl^Ul|2?KZ#4qsQ*yA{V{l(bNRJd$yj?(*AOiyF^ zEZl?nbD6HiEc0_rFUFOo_SbIee2-@S@puaJ&u033yx7!sx8vRT9Lrz8H}D_$5q^T- z;P=?`cz+&4%nFT5$8pS`X6m@rrov+%T!x)^B%Y2J;cxLad=Q_(*YRK2>jZzCu~>$C zVFnMtc03$U!K?6QbLSwqpXnz}UFWm-0`uQu`d$3k)OKH*mCE-|^xO5u!KRjPZEE?B z%pZ?aS-vaQF+Yp@;Q`ocYJY8bI3A1V;Dx4+ceSbOxE6npcjCjQ_V9~@$8{cUhOmSQ#*+*04`!Sp{^{vLkB z{QqF@Q~Y*Y;|`|Ie`lP`{Bo?r{je2}#$Vt?_*=XUAHrwM{z32t(;u2T?#K8A^EW%y zpWgse%Ln7u%-_N68wAssPMBIRjdPj54=y!(2f9{Md{K z!4FLLKHcx9KMpo^-rHjtmSY1p<7zw>l9F5~~63)cgm^QVad8X2#1@@9BS&gBTSvgMCO;_ zZn!5_Vl_6J+J0YC+aJjMHr&AS!&rVA^UuU{nSTk>m*cgj_IoqS?_vG}_!P^Z$G4gP zPy7_W#GzYHIy9Q|lkW{A2J` zJOeMli}5N`+h1#H`#YI`H$H-o<6rPaeACqS@8Y-2{{efRqvaM4a0m{^(WbT^hclT! z8`D^Y4W`!L2UjqEHLhp=Mm&T0XX9nezuMIG-pc$t@IjV8hA%V!HGCI8z^_f6&-bSG z*Z*9p>m7vKVhQeq6L7kz?Pr_XzKZ!ZI3M@H#kdUDnA(1wsqK$r{z-Tio{N{@<#?^B z?Qb@<{XNWo0H468@o%Qqf78_ZA2I(E{D$Shd4Bl-Q{gcfhckaiQ~Q~~^emR|j#VtL z!yNM$<4RnE8%^!+XjA9)OXi=4m*N$89o~d@ncDt7Q`oAM^;Q`ocYCmnJ zuJZ`yAA=_{|4gRO!C#r$?sj}0|7L1GADTL^kMRrUf6sJ}U-{*|P3>n(Q`?PZ{th^v z`MWW_C)SwSZhxj1;en?1)5-J(+-Pe33-L~T5x>S^7y9)^n%d7KQ`a#CXEMKn>A9FS zwf}{h}wOxOv2jR9@ zf)h=xw;R)YV%pU4m*PrO>m9}N%6lzKb8@ z=lGqe?PC{v2b&6yVK@rM;zTUN-EdE=#A<9bwf}u_4f8v3BOZw-;c0j-{t7S0-{6g= z_J5nH@OqH>kK!}LV>nJ`ej1nKVR($G{as*cyNmHM z=KqfA8}JVNBR-6e;d7?;_X^W*;M=CI`v)9-iJwm3&v3D+?bnz(pHAF}N8)j&);r(S zet(TOu>2Oh&zzv=i0K#cO?(^wg`eWL_yhL5)Spiu9D>7f7gNV6Gj(1`=Fh>sS>D9* zCCp!r2jN;g43EN-@pSy9spD*7`bxYWZ^l31z4#|n=lPVW?cZSjKky^`1i!)Waq~^u zPWPoZ4luQ!;Y^Rf9dKuyiL)_b>O7X<3RC-8&+ zLrtB>Da`)`UcmB8Sbih(Z^gUuetaCC!WZ!seACo%K4;7(meQ_(?8fTl@Z@H=P$TGhP55Oh33J=0{rnWnr>7(%!Q~N!W<-cbBWq3Wy zZ)N%Y%zqf4!sqZ6d;{M$b==RG{tAODHDA}g8TQ33acdljJK}hpiZd}`>N@7&e#}1r zTX7Yx!$a_BJRVOqwZE(IVN>mUkKr@;Jidx=Vvj)U?->NeI25-@16 zGq@C2;GuXpo{6f?y8Wma<5aThyw#i)1b5)G_*Z-b|A8OjCm0m@?Ki`|xFzn0<8ih* zUF{*bH#XvOT#0M(VAM~7xb4rx^U;0pu=aZk)3@V2_y9hJPvZ0V5`K)I%FY!Apiuv>EiS`>6cAndtinKf8L@dMExED6zzPJdN;wn4{55>dr9J~N8#VhbS zyb0a+{_6bhW%?z275{&$Ro#UrleZnZMq?I11hO{A#)To?khc`R@CC zHJxR8e_VvC(S4t<);o;pqtJbiujZf0^!a!ZUV&HRt#}7Mh0oz9=F}kg0{??S+|S<} zd*eXd3U|cuSYZy*@2lY6*ogb#0k{kg#CBYV8}UfI058TX@M^pnZ^OIsetZI-#&_`p z{2af=A|=FjJ#p-V18_$ik7YO=cgF-S!2NIuF2^?Pz(epbJR8r)%kV0^0dK*(@E-gN zzKCz5`yO9i=Qm7$j|0>PX4gL$$Kp=77p5?0j?%b4T!E``Egp<#;MsT~UV>Ml`~F_- z_W`CK!6)%qdf(q{jmjGaU&jyXW}_{ z6<&k)qx)WAoyXHm{{>&gH}O4m-#e`JW9kdFe(ue&9}dLfI0C2PEZhrII1lS^F)qUm z_;WlJ&%jN1CH@ib!{_h?d=Edw@35$szpjC}74C@Ru^cOK0q%$H`;vDKf`gbo3Xj8c z@mKgeya6A<$MIEs6FzT~h zv|NZk!wyqvvHM*&5mTi5jk)5ZP#b@sv$ zI10z%E?9wcac^wI1F;R);UV}7{3ZShe~s?@xOINFG5u$J246(?J>6RGW2QgHo_aRy zzV$)(echTK!}JW?4c+&5Yk39J`{N?)!1Z_no`M(QrFawm9v{Oe@p*g+Kf+J2#{hr+ z#aM!4a6C@JB+kJFxF2@n20Rf@#fxzhy6*{Bc-+DCz4#!$jIZI__)q)+V@lKPKDh4_ zm;IO?jXU73xCdr%J}$!p@o+pEPr}o16JCk8;a&JVzJzb!Kk#e(5B44CuVYKx2`Atl zSdLk2!WFn0*W$r=I-Z3W;Kg_gy6-nvINrnb1NZ{|4gU*2!_8Hev-{8+x5W~iiZgLf zOrraKbZx&c(<^Zeo`k32*?2x)i#Ou^_%ObPf5*@8E9^PgpMM|R4!6ghaU!O$66-LF zt+)z1aRZ)$zrf4!H+Z)>R^wUmPw2kSUGv{z`hENazrg>X{qU6SXAA6$?t9-ge;cMJ zVj0fD-Ejf#hf8oduE9<`6c5Ma@FYAF&%xi}4R{;gh4e_g55l21(oCs5$#f}}V+A&23vNL7J^wnNW0^h?-S_=# z{wAic#%u9md<>t#=kXPM1K-6D@KgK}w;b-T&;4G2j$6X?7#xq2a8FF)T&%_YaS^V? zgVFuYfR1x2(^uoQ_f51 zeF=CJ)wXr@P)S#Hk`8p3noei}0+LP)=}yv25(0!-5Ks|O5(Z6>Axs(-H3}*sS3yt_ zP*G6v%2hzTf`WjcqM`yKB7%ZA0HTEH8V2QGt7;zzy!ZYopR($#b878<_8DtPWv1X9 z!4-nm-(Ns{-k0b81)mmtPVhy+C4x%@|1J2g;0D1D1-A%p75ql~930i-b0=fevJy39n;4s0Ff@1_{2+kCIMsU91OM!yjSo6!D)gs1YZzbB>1}En}Qz;ekQnGaHrs2!To{<1&;_i zLUtTzVau;8tNBLyE3d`$33!KVeE6MRwdb-_0U zR|~Ec+$6YJ@Jqq31b-JiCRi6^i_X$2IX#IT`_&H0`O9Yn+ zz9smM;HQFL2!1X2t>9t7KLpPUx|-VcOA)Luc%@*bU=Lz8{{FJyb%Hkv77Gp+yj^gt z;9Y|E3QiTACisNlY{54KR|u{aTr0RqaI@fc!JUG81@{a7CU{iP#2$k6NfN9h*g!BO z*iT5z18_4jXJf3l<>7Mw2ls^IH_D+K>7xK?n3;AX)s zf;$Cw3+@-R{*Dgp9+7mFpwY~ZN1|XI!3KgM!KQ*?!E8b6@9#jjt)#8L!-Mn4kXu&%L?-6`l@JYc1f(r##39b>`DEP79Ho>n2t-tF7f2t(?r{GyZy}4a~Loit| zMbP^DKR7>2(z$}I1^WsP5F9LM{e2*uS1RdIf)fQR1ZN1&6nsW-zTg{zD+E^yt`*!W zxI=J{;6A~Vg4Keq7IuB(1w(>O1v3P%5^OElUa+s=0KuCChX|GnP857d@KM2eg3k+D zf5!-MdP~yVi8=Uvf5E+i`vngQ9uYht_@|)bO8b0WFhMX`u%2K;!F0i9f^7vm2o?$U z5F8*lP;j*1IKc|R$$}3HP8WPl@Lz%}1y>2K6Wl2Hso)oay9D?GJ#(E9sOIR83H4;CyIyi@QV!3PB&7Mv+KM{vI23xaC| z*9(3u_?h5#!JUG81@{a7CU{ivKZ0ij9U0O;1nUb11)B=C5G)id66`H_t>8ex!GgC6 zjuadxI7x82p!IjJ5XYw^{jA_3!B+*>2(B0WSnxB!uLZvq{6p}#;Az3X1l?h~{vN?b zf=vW71g{dz6Ko^cQLu~P&4ML@qXowaRtQcOoFe#$;5@-cF*BSRqi8|i9BgW&t8qvV-8xp;E4~v+H-@78> z8CwAn&vv>I@r z67w`|39+@NEhDzW{bFJV{6mCYx1dKbK`>bmj|r@DAwg`5taJ-OgwIOD1q)%?!k8dT zTIp^?)T@_ZU%>%_#YEJ1xL~Q^D8X{UiGo%fP=2zcD+Q+tP7|CVI8$(rpcN;azd+Ip z1s4l05nL*`OmL;36-S)EM$(%Fw+L<(+#$G2aF5_V!Jh;V3LX)x50W|;1qTQY6dWvQy)TRNtoLPs z<-$)CtPq?mSSdJFaHilK!MTD91Q!Y}7F;5@RB)N#O2PGln*=utZV}uixJPiG;7@`F z1&;_;3!W3yoYEeG9>D}b>wR3r!FnGT7!tmzV76dXFecbeut2c0U|+!jf&&Ey3l<9w z7c3W?C|DslS+G)Ys^Cn)If8Qq7YHs9Tq?LsaHZfX!8L-L1-A%p72F}XOK^|iLBS(} zRe~o4s|C*qTJHlRuGag&z+{)*9w~zL1%rYu1jB;af>FVkp!MD`^tws9mtbGP0fGYs z2Md-8juI>voG4f+I8|_(;0(c;f^!5H3N990BDhp=nczyn^@5uOHw$hN+$y+3a38U; zru`&%Q1FOgmEcLiYQb}Y9=Cmdf?%>>ieQL{^{c613qk8WW$@N}%D|}bF~N3%1%jOg z`w9*a94I(guvl=oV7cH#!3x32g3|8YTqC$yaEstp z!5xCT1osH;6Z}cAO7Ns$wct5HO}FFg7EBgQ5v(s56buPA70ecl3dRK633e0gCD>PR zfMBuUaKTc+QGykMlLadUrwYy#oFh0_aDm_wBKAE?1(yk~6kIR3NpQ2^7QtPDdj$6h z{v=o>cv7%h@SLCr8$H^$-opl3?_mQ|gbxWe6>K3G7K{nD6D$zyEZA3YfS~ohHuSCc zwSlF=j}j~woG4f+I8|_(;0(c;f^!5H60v_=EVx8)so*lfm4d4T*9fi`+$6YFaEIV7 z!99Ze1b-5&5-}-q=_cu3 zf&+=!h`(U5;BdiG!BK+cf)fQR1*Zy56PzJ9SI~Oz9Cj8;da>XV!KH%B1Xl{KCt|<9 zNpQ2^7QwB8I|O$L?h)K4_>*9j;7P%1!E=I|$F}Dd^av&h))x#4h6I}mW)q{B-vwiW z?F0)1I}7$D;`(KP;6TB_g2jTv11`x3D~8z5-? ze!&%(pO^*~6IBM8OIo=8wsOl|+osse;pp=x;LwXA;rh<_OLu zqMa8AE+nFT7YpiKH}U_KM8x$PBH}rTh&Wp7I^t*jo)qF%hx0z-)s=`i-NJbX@yTWX zM_jDmS3x}9N@y zC<_7MzXMwIJB8QPJ>~uld~7P|7DV_02`fKFL_Io7x*HMo86fF_MAU1zq)UmY-$Y4Q z5K+&mlAcCH9hOMiy5E3$ZFOd~$l z^)%Af^)%wNL&{s%y@=OINn6*oh+8tRt580L7{z@nNw*^+j@I=h@~!Jj#M8QdMB2K3 zL|o@e`2|G8SIe4k*XW5QLxB^=+gPfOCXT3>sAUZ=nOLG_4V^GS%Oa80Z%F^n-MSCy zH=<;C_pz69H;gZvIO1~BF4%=qHP4r_|Ap^9w)>cgUB;9Q9W~<86Z%gqnK)@e*AbWL zbSfD&YG}!@+xs(P{D@Juk?}(&3@hdf;Vzb?-9exO1h6J ztLdm@bs9Bx0_uDD8CH<~E6tGpSGLRel1nr$uj7AH83t+e=wU-jh7FrAq-?_Y8loy| zSjqU||3lXB(Ip7nxc?z{!tk=O7qiBXWk1Tg4edgMW5-wxWZN4)V(6sXhLnxD72U}` zE*Uy>{D?bh=Asd6CQHz8w~auTWW?-q{wp)8Yz$&*=b}$*S;NpgBgRPhZT{BrC8JTO zW53>6B@-u(FB>{(B4q#Xe=r4T7@``cN9zYe@{%76GwY`@{$)8_mRmoUmt!7(n&W>D z{{KIf3!}{CcHQ9Ak2)>@QL`N9NtMU4>iD|L%3-RwkXN(ZsLRR~{14@(URJL2|4{C^ z%gS{_8q?l|ALZXlFg5GJ`8xSRsf)gDyR01N@rnOUxzE92xzGwE&y5M0amSRYdGSB( zGJOpH*R*>M>2mz9ew2R+C{(lDC?tBRLO@lH-!-UNZWR)|x2b+qIerJBrhf_WkM*U0 zShg4l+J37-C8 z*}R~4_hov#{@Q|k^`rc|<1)Ra&{OS!Uj?|JH|sLJUMR#hR{bcwe_W=wvW6a(@e6vq zKh4us{J0;Uqr{{flZ!9YTT?@?fs~`a?_Z|Z6#K3j6p$a~-@BLTZGxU^U(P8kM?HRT z0{>m`ZyEF!Bdvav-nPs1c0jK_3b8%#>gWZ%>dW*7ptFZ*Kz@`S_Z>C+-;o;rVXJmQ z&yNX?r>po?Cj9r~!-sM;_0HAMYg|Jw>oUD6=w*v<1m$1L%k&cNx){GEHS~I2rWe8< zu$V&fqx8C6rWdTChi%)1`ramb0PCj`dNt>Ar8n#{y)g7jaR%Fib3DtjeW!>X4y~V+ z&^!2wO4+ex>i*00=0I=mKwIxhmZ^qSiXm?(JsUCgga}uH|cP|!(9v6#QdCWh3nSYy6ZWTE7!+P-N6u6r43**Bw z#Sox>*#2MeFAj4y{wwD>{HYx4(AwCC*1xpLA7TwN+8UHAMt@=1Yw$nqCgXqFgx-ap zASP@+ds9E^kZVcJax;>gTHP9iDu>PKu(BbOO2$vj8hceJ6l#^9ofpf_iRHAyadvji zfAjL9;BvBah@nuid4HE)MGl8jVjWso^-#WaQwm|H!(yHIySXQTKcd5H5 zsc7W#DHXFyT~#iZqwN)ETqlxCpD4{K(i+cSv8rqGYAv+skUpY%t+uZEZFf;(k!xgS z#j_P!l`Fwfb&uoO^8IBm{g&WND${>UaHN;)FTP{>$mI#g&bLcHlW=_Y3N8Je((Kar zOVdl1buC`qWaPq%c|2Dutg3W6Tg)qWZPh|8D|VMxuWdO^3l*NcuW=gYsSPACW!&8Toz4R#JLpIxo( zOQ^ahVZ;eX(i9wjQt|A>Z|`zcEpnKhc8{Ba^U9&!r|Nvp#2yJt%v#=&Z!G9Sb=- zR;Onxgb8&2OLeNoJgM5r%LOzuPm;IyP|LD zfdW^j{>A-E9{{g~k`Z@pzqU^+@Dx(q??4V|u`J*M-WH!Ig1V^1V^EyPjZYlhTczv7W< z%~e$0xZtVNdUA`q`cNS$l%H@W>F-X}&G)JEadvz^q^+~BDa6tG6+`M@JU2dh$^ZAc zMskb0|Ic>4o!75`=ay}Z2G?(;^!hFIbFJBprJ<2#Y1h=c#lMu@P<%&4*6QT!zQtQB zMxD@;x0bUX)-IjdHLj?7bw*j_EwpR#jiqL3a`BEs@x>nppTQYX}tBsPtGt`eBE2Q1MNrmFzF+1;~r`7XSa3FKIqCSJRDzJt9rds%Su^yyz!5Xx3374KReEOkEdnQIy1eW=B#o$ z2Tdrfc%Wjtqr1aV6>@A}VRq6QHyA$?v&S39oDRp81;?ML+`eM>xWdv|71veVSl*xl zvx}oa`L>GM*6hNWN6j!=I(n9|>5wZOb7uOE>fpkII%7R8iIrX*kyciWzSmThC+X;=*H$-Q4Pmb^I<6J{~U)Q};|I9;GeK6-H^r@;$N-KJ7*_3M6KF-Ah``p;uF{@QY z+mTw+u_qpM7*Dn=ZB@SUgtKIN0sf7oV=dCsJ#+f@ikrRYtoz-DrZy*jrt?XCwlQCu zH@k4mZms!qSP@*ayZ3a>+k5keCkk92o~YE_voku)F1&tQ=bn-3dX@3>U1vSjar56g zTYY>$+WBygUCy(f)2aLP`K!;KIB|bQ;kT}{T9wvf)w=W9TJ43WHfAr3VF8`DYF$C$ zgM|fqobzA%&10M>k5qK3a=Rks1Kx79>rphY=-Q$_hYw9S|L5Q59rLu7-)zH~k%euw z44!#Y;k?4Sd$rk3daf+reRHJZgAu@PDmtodj{xnsU_ zwj)3Bs(ITy^G__-<{PM8>K-lRUAFdM)f3LywR*beeG46J=7tlRRt%-`iVY_=IEF&0 z&RCFg4U9M+gy`0&O3LH5d{CtOpK+upPyt%vK_dPl$N z##*o!W{QGB91W;$qHVP1cNgaP>^0?GU1j&I-g?N>RBJrD!c}#@i*cA;zM)tPAKjY0 zrZOEdSoa`SV3)&r<%Ux4R`0)vop6obv-_=kOuzB2*;x4!*4Z@*Rwerqs$$N#t+T6x z>w{GeYkU~Crm-vP9wd`{|AffluftGk)RnVo?5}=2E6`_!&O!?u7pDff3a4H z&0?iPb7EV|i?9ESpC9Jgdtm(QXq$oOPGhmFyeEQ-n;I8YPIvt366~WLaUaL9{f#=Y z`OK)#yX#JeXBNL?;M9|cA?Nzq$Z6f+M&>xyIMk)*D_8s(@6V2KQT3 z{2LuXjmM>#ep~$~NqO{hg9!11`oSx=UWPlGuB2wDYkfZ))AU#IPuyGlhexhM*u%#) zP3g_756FJOe|Y5j3ZBM={lz5qk|-L8qwJIkIM)9ldxrn;$n|bF9L4+(<2e4WuK35z z>*DyHNqmIvSrb6Q^KEwo*fSJWb$VXN#YrB155w(wADO!6B+A5j<|A{1s$MXtq z#TcGJh=b{QYY6VVc?{f$Oz`k)Y>A%d@H{2SvlDj!e4ZO{pCZ|FsxiLA?^#rYzl-RZ z?!cWUj~mxqDV}&(spDDEMAPbeiaX)2t#~FC;#rL6W`wPQ=bjS$9XL-3V&Bj+{HtWLOV7jJ;Rk^8^lq zzcH5OFvfMkNBbQ{8qUdf7|n0tBOv2j_&m#Dcp7QiY=`l70iOpM%>hq2jG?giw8P+) z*fTf}FxO%DApNYvD8pshJcn@(VW00XRw3di9R^>~KIJf0pm+SoVf>Cexqmv05s8{s z?Jzz^@CQ1LemHN9(^%UIHyd2W-z_xlkjr?#zNQ^^85`mIZ!Tj3n)`^$cn-bzcbCx& zVfe#kbS}hh#%1(`6ICuFqbcr>x{QMwZgskib%<i12&(EwH16>sdy(zI^@IB%8LNI;ZU zdyPrxZ0~xFkvD7FdtT!+glD187)cTHkMj}#o)-zrSB3Si|r%>Cw>KXB{em7KbljWXzMn4ppT+g^4 zse9`gE&Je0YxRusy0{Tl&&cheX_fVirRWR~)HBXqqiF>TjFirr)^UOH6~=Pm0watN zbY5V@q3d^9U<|wxAJAH0{EU)a7Z`t{WZ#X(DtLD7Mk5`OC_ZeAMXQt?HoBy1+R(#B zHU`PC!-f+*a`<86Bee90!$v#6t%r>^LpANT!{&V$!sWFbn)wD!8OMWxn1{ympglr8 zfd?jHFp&oijEqS<=;}fMcyPvvI>c~L0jD0|!NS(~>k&K{18=ABU=SiXl?PvA!g+`X zGZB@CdEhM2v`2UlfZwxl)7%{A#z$Cr&=MVFHV+mec5`^p5i{6RJXi+D?iz-Jf5F7v zJUG%3-B829>u5s<4_-#qojl0whWV2RzhmgSd2j}C*Ll!52NNj|2BQ1L^PmZw_wb-M z2Drh4BAjJf2W|L71B{~%rdA#tMdTBC&=b~^crX}U&c}n+Xq#jnEWQO@iw7EpU~L}! zik9{BU=c!>!h;Q%XzK7_B$}CCo0%xg<<;y3f1ErxiaFE81Af5I&4YyYtOX7Zq4US_ zAf=F}yEOArfP)9Qt#~>PZoZyb2(7nZ7^*tP;i}^RjzBZ&4w%^o{(2;4I7?_iL_S zB9M!^o`PH)H51*&WQXf54`S54e?QH*&yn;8oiXZZzQb_YxL=6)WG$&{7tN@YG`@l8 zJH-MID8i#94bY4SCFzKVBGOYNjrTEZBPDtE5v)8l)MI zsH8(nx<)gmsU#dsb{ls)48Gu0Yp7;C>d?=kGPUm1jOmU9RzUN9gh}0a%&uE)capKg zVSH+!b)PN(ztd5BHxiov0ff}}#!>qRqze3_vAh|(?7T|97c;W)t(~_%q$yXQg^oHjotaiCeqq#NJ2^G)$t$7#v%|d~QLcL)MI*?ygdJL36CCR# zteoB|N7v%oGlzurPlL`_RlRAo=tJGF@DE@9Q6hX%NGD;5JgIV=S{y%7s+0JC`ls$H z82DDnz{^jlK*Fl?36+Du93aVPc`(OX{={o~HA&VqRgv|yxI`T5B&?i#m6N8$HD?Y9 zE9Y93lcdFUWDW`IA1k|DWxKVwV&;&ra;B@CI4$mO=8&-dNpzSEL&i5q`qrSW%+ydr zww=Qnr}>(p$C-^3;naM$V*)oD3xNqlOHMZHh4gbcJ8)+T@*0HdF#>_lyCRVu@-j!O z`z-!Vz`P|r1}0mEj2<9-pL9pLuo8^de6KbKkyXQFE@me)Ta}f3D-0vEND+wc z_PQXtDni$M(=peX-4x;0eEcYv*#&lMVq}8ff^<|&HRx54^%NQ zoi4Qw)n~;6(LqS`4tW_jM(6sF@h}|ny+nRssNsd^%*AHLyipN|&X@FRkRliz#_uLY zAUgcEq&Zj-h|UYtxJ7w|=-iD(#~h*vL}vk}C$m@)h|cdVK$IwgeUHRYMIbuM*fWMH z0@3+23&e0mAUaoJH8V#j0@2x)2I4kF*wN`1(qBi#1C~nzBsw`*x6RU!mvLis#)XW< zK18QpH}Dfe4LPY;eP=q>T63Zz5S<6<#3V%^I^D3mn|CMz(cza=%{vu==aknB6o#n7?-lGUa$4iaLia>PYu=1GqDgx12$9B9=5r|HhUFCj7AUZ$v22rU9 zL}w(!^`Ii`=!_2OpTKya_BF^G8>+{O2XqdzDIqW8hSl7h5i$;-$$d9^z&{=eo&oK4 zG}3%m-vZ(ZMWn$5OUzV6s^*(WVwNI;n(samPb#9J=9@-hwju(Wk6-pS=P059D$)(a zQ;Mjs`Ceg(rxk%+h0a;!8Aa5^P-_EXt|IDSxU%lgDk24AkHkDh_%$DYQNWz9h}xK$ zSYm-9YH2?H=>zjQMI>v!fx|#NuL#UEf01}W5$G+$I9wMh0=?z>P9R=X1bRy*XRDVK zf!^{8d)#70ptn5F>c6ZA^p@HjkFO{Ky=Bo=AYN4jddu2k5K9z+-tsHr3eQ^IR(C{2y}sDw>d4OdoY;>5{4shdZ<2oMj*=R zby>*Ej>YctPRJ+%<=cr>+gz;#(0z8{g4BFh5$Ha5u~V;6M5<-tt&n~@O=NLhcw0=2 z#E!*W7xL1$hUMkskTI7g@+06sQHuvc^AGln&lG_s#%i)Lq_3r-mG_~nCO0Ib;1?k; zZE;4}6*9i1Vjfqy-7=*ZSRXOr?g;6BQ(!-enmc7msgsVxo{*Q)to6?!qop4Ld)X&` zl{#SyoYcJ^w(zQs2vKs#+#k~Wplo0}hy8(2eeNFubJ%x|guKkr>eAp49Lcr<22O^I z1vD_cDa!rlG6SbC8t@h3Qo=l|2vnhArNgWW=^xPKs;jb z-sqaqkpC+ro%YVw%nkXUfPmYP%2hn%uy(X&AG=Vx!`i}{eMA0du-$0tNabRd?Xb44 z=199x4hnG^yFKLRTij7cD(Cb96e9bOU8vBJvXjY&L;g|lu(KnTQ`=&XfaWzqboH zohg4X`9sLxj+Jz#vTsy6Q%;lpBjis9yU>}+2F2x@wT0^q_pH#j#r_w^IteT1HkDIX zi@Sk2B)p@CK_9Db`5fr<9r zMj+l*gn$kqg8&MPT|L#1h*Tf$4uJiLVra>3<}N9g4v8Kbyo(MPPEDPvRRzU~=D!n-k`@ ziojg{Gl|`bz+C=2iSHDF3F{PzJ&M3w{uhb8iojg1bJ6`?5tz#pN&KJ)%;j}R>{A5h z@<-S;_A3H&`4c35R0P@#4ZE(Hz5{I*_=F9+K^iuVv)X}XUN$)!_HZ*Jy#X4w8%-Qh z0+`GDkoa8@XzA-o{GkZ6^vxuWDgrG%oJ5r(uobwS#4$yn>Bo~et_U>!T_jE@0!?2@ z;-n(b^pB7@r3f_rcsOqUsR%UvV(xFN6@jLIfF({V0!{xhOPo;zn*KT5TQbin0*mx& z2Z+BEVPdspiSvp;qx{JdT5}m(Xp{!*aZW|pA^)YB-WAadG~gSm@QFqZ0*$WjEF zEkxofMWESQkjPd9#!_vpXl9Ng>~@T6uKOCI9UHS9JRxH21QF*^X_R8-JpZ z55Er*9wZvUPeLS-G>haQKSgey*o>E zRRs5h)aa%N)cr#e-4%hl-_KKeC<1kVghWq8pzg;Qj9!YsJTi{Gytg9kVB|H|gFytt z#T`{lg0cB(B(7=hWtgj#L^q2K#ow zwUJ8W&S0l**p)q?2;3X&gcBZAX;#c(-jQLPg7sScd!uYchIQK{urn8yreyf~A%`wb z&qy4Ws$85Q0(7yk6MX!KBE+S~l?8F>36+LRg}r*>T1pXcsViKXrP8)b4`&$DU@hX;wuM$|d3!ZzA2*5d~jUexfn%Xa(Y*ia^c#;f$p! zjhYWY`d=!In)mAt;tfTh<^xE)sR-N2mokhguwScxCsbguRQ(l>_+=SBx=$zH$w+iH zQckWGfeTK)s}z-!?Wd=*iOEcVYGn#z#Rqf>uqte8N1B- z3?JQRxEE&V?NKO=;Y_2u^n7!M!B6KV4d{&OeR^s8Y|7B@LtZT_?;~lSf3np-%kWZ) z0y{DiYlSe~yv!lAQ@MpZ=)LyRGvfz&IJ*FyaM@oFU6hrO&3{q7t#y3y|r z+(8tHfC~{u#S6mvXbN;0j=VwZZp5->IweA`r@->VqgzgwrxHFs!FH zg$c(E$QvXkzJ;vQorU>p^`eW!n zst8moyBA7KR|F=9-bI+Q9#aH5;VNqULlNk69dWzFd|VNBJs$|`3*kXv1$*oisb?Dp z5>JG^tN?Fu%?&5=36PJU#4zWD8+`$qehBo(@|NQv#t*C^$dtqcjCx z3McaQDc@cOYOx659+|!7yds1HqaBLRhm8md2fkxVE(}`_AObJuBk@|;M_Y{Cig2xB zDxNO@zcQR|ZSXjUSgY7OilCyyd?TFr5Ec2Sddy|vG!_o@>4L<&VLxqAaYMM)i&RYH z$lNFbGOeu*Cw@eMTPUzj1PU3AkHUURvyw~0#$Fr->6aFy7JgyMX+9a&`6=BrMlg+0 zNTU=_*cMLoH;2W>-1dAGZuAvs71qzgMhtlYEAPv&^_(H_dtDUV5%y7!0^fxbS5x5M z+2Hqz0K#go+&>6`uv%;6k1DN}!~=>@OX5$8P)p0ticm}9FN#19LEXLy8{gB*+F>~G zt$5jzqvT-NNBhHbC@;?_LV0;s5z5PR zilCPc^Y?J#R5%bg!rA9&*jjM|AvWdTVL$z+mwINch4k`E_Wk%w+e_4h0*=hY4=G?Y zK%Ohp7ARsLPssFBnvL;W*w}-^AnU3Hsbw|)XJP$6I8I|rr?IutC`F5PGL71p>3!F6 zeW{meFM}T2Vy#R)A9(>Q&!1^8VFrhM{Y)?QD9|X=c!mP}%ZFxT5#SieX#=8(A~5BR z8VaJRA`rK9cK&9Hz})b2ZxAgMVLQ<x5_lyV-8L# z!Zk-E^WwAA)m*o76@d%)Zn$x2<|zUdP!OZf?3{+K;*3VbATK>7^a24azkBz@fdl9V`NTfZUhM(-5VI%kOtd3{!+{ z;`&V8p81oF>L(8dsr^uMAVLSuQn}rwSu8^#K&2x52Z)Chf$q~{Ac%(*0S~wWX6k3*L0}CVtwOrbHeL@rlIdjy=;q^@Mi1mCb?lF} zm?;9-&Lnm0(HR%9N)cnf;{cR+QkB4ERL3qLW~&mm&FPu?SjYud*M^xHV)ISpnR7C| z^oBMUpfjM5Z$Urs&np46F`S-@_NPEk3`BFD2xRk$c44NM(iC_V?N5QTT+aTP+0dTR z5XuL*<9uBa2&J`mT&hfVthK>Le{w=<0iD3nxKgq^`V zN&sU!i3L|F0ydxFgMrmTI59|i_5|^+DuL#M)0+975a@$+VtJ-M*LI?nX1*m(?B%?% z27L%Qtmj7bAsqUqaIXAN37}d_Irn|6Y;xKifbGde1OJ;6 zKwEsrf=3hq6KNel{H_QD>M;)MKNNw+d5LTNQAMC}_-C%nDn($+1FwG0)N^rSt?u;d zSMloCL=-%p>7~E)>U5^@3cY$~82Ga_2Kf1IAkHZQUR^=2{!#?InpptiZ$-c>KZAE( z5%8)3x}m9M$*f^}bt+T;j9&F00I&Ycw6E>%=D>GmdFd~`GO~t4Mv8z}c%1=vwG{!c zey2ubMPPP(g&OIK!0cGSQ<^9OE}@OInDaw_v5T_(=0D*M8C7LjHM{# z>%a*pTM5ALA`-0>0l#~b$Wa9R9zY_Z2>5*yiKrsr_fQhKih$o`B=QsizspJFE5i1> zWtP5;em?*g&9M0W>vc%Pvb?Mj{VvEdey87a+4BmOfIX_)W$CpsWz`zM&V98A^caqU zowK}@ra;duqb~~iZt4uaw+QfdTt`Nzk5WXnUT1IbD}>A5@O917Cs`(V|FyfAnA8Ua z`(=4)TuY3a<1>seBG{?%wx|~5Elx*}x8R&X-cEA`d5gpylFDuXd0dHGhyhrIa9dB6Wk@LDUa& zkq-p9QU`-v2vhCH;!kHToBTOoROOZIcYWxa^|}t$jPZ$kds04 zAO~Lye+y1bDOrAA=v*0O*Kg^+feS}7o6GRW*tE^{Geat$Z(mLl*B>vj?=6@h11)^qH)6``JEzoQ5PUb)SG=IH#54f{Fv(wrL4 zu~+AK=`X!npJQ~%g;&3~fr$@9z=bDk2T5#F1Z*B4@sT3%#?gVnAT}$a7S{YuxS#*2 zA`JYmS!{;JErG$9NcplCGn` z?i_o1mQnLnj{Z6Yj$VgzzRs~{(!JLru_wn%X$t(5V|F_>=6{5U<81FV zkL2imaCV>ybvFNy9@2#q@VOi>jnhY0#JHU%rgsFdM=q>E^znR-K9d4RIjuV)b|t%V zevXfLDNTW-h_RLemIuiqpkvBx&zjX10v=J(jOag7@wNiwC5U1HI;-iAcxj7@4I{?i zRD5&*_|!{Xsu$6lVDSnp^&_u=2n@jNU^a?)DNTW95u*bN`3h3Nx42XwJ)#e%fR)!& z1WqTTU}nTiX$nLmMkNLIa#-hGDv%w~U#7tBA;`-S0e;`vj77YZra;Gt!RJN3w%mtw zx>TTjME`{XohZ;j1Zp)$qD#a}X$tg?7|s|3#<98jTq@8#qBlog;73keJw*VX;tplR zOKA!Wj2N9L@C>aCx>R65L@%YlYglB=>qTH86N4jOO0(|`ix^WWurCSxh=@HIdD(fL z=8%Z~8U^^dS+gW!&prGb?Ph7jOKEyAHeys$;Klyn$3-q)RL$pbn4}0SOY?bAb*Cb* zxQ;CVQK1M9S%-OhMCTqSaGJekbj03K#c`g#JL07`wE1AfxCw=PNj~sXrPjDY@=f7B z|6xU7Ng>;WzG_fY)rE&VW zF=G5g6DFnx^TSJhTo=&|gg5X@3*>DOAGfo+e;n~rngU-&jDaZRdx^r^E(-WgGT2`U zf!}8F)nhl^p-P~s%xge=qX@_$E}up8duh|bN#k>|`8>PLu85c3(B}S#@lV>UhXva_ zAOh@P#dPB5OBMGKZxSH9gz4X;-xJr{t+>Lqv9kkK2=J4*_VA>R=UP4n!f0;eMSwG_x>BmF4?v)HD8MZA=zKwQ)q zO@S259Hu9F$*nbKRDY5Jz6Qv1N9`40F5{aR^-`JwDN*AM3M6A=X4bt_AUUdkMS-i? z%C$w{NJ}IdM!l4#K+~vklmgMN;G2nnJf;an^_2Dy_zdfnnJxm)+>AtvsF%_dXcbM& zMj_vMHdiESKjIUC%&2i41-5a(TxE*~ws2O=jru4}fp*cvaTGAPtXzGmKrCuJO@Tky zi`t05xS>cCM17QI@5zYjuj4R{ZlqC)s@F!=Ao$`- z1qMa+F%;<24|#({pi?mtL!(|wQ{eWfv6KQkIk}C#DB$yQwjV15zJBD}!@*u2mHRt5 z8&SC}s&AtSy##q>V&Wk>JTB^`ahkY0n&`uz@V&`GlP|{Jm!1IPJ|Sr0IupeGQF+F0 zo46xtL~(XtMR(*?*!~21bLUVQ_0c#@JQ7VDPZOUYEasy%OgzRmeXNFwhH)TfTxw!U z)Ody_t}jO3Lt1{IeKgLhPK@eHahS%cq|q4dJ{2_%ag-s z6R$`0uW8~z&H(=s6X{I69re;UuL#yf4L>G1E1Kqp=*8=lt5Hq!14ZCEr5lNjibzH5 z-R65yJ%+ObFGrELHfmpVe0Dt&A4a`2&RTpCHSVB^+q~enDyOl^{x}T8c17T_`BAK* z<_<;RY&7quQGGs5JOzv97O6!V2gTP>FOAd0-l&m<;p_`?uKGaFP6ThEk1rJ8OtP%Y_8a2k!??P7Ym=dtppx>hU917H7+ZLTB?`+h_ zN7LKQ_m^rM{wfR4`dbmI`OYf>mwf$LLd%sF$IFz1NjMaN7x``_;Zy{!Ov_2Q6oIS6 zyGghefh*IgBy>gK{nf`w#3=&ruYPzVh2Hw@2_NKgdcFihoCm!t@6pQhaeB3Ti5=23Sjh}w$4W1Pk$QWSx{vxukEQ3U$V z8zkx}0zG3ji3W;5&zL$KL__0kpR6N4DJXZv8 zZ;Ap}BLp%%^{SbG?+N zz`$JNc?vkW-x(wVvfCJtt8b)0S10nW7l9|ZR@|KHr8EUbt)Nz7& zk0S77F@x84_bCESlwJqo0Y#w0b zgAVj*guJIDG|y3B0h(I`7NfZ-P;o8zS1tDDU&KK1W&4Q`034iRT5zMHG_QZsM|`{)``8$lVoj=CNaZ zBZ^P+0&ahAcBu*&;i^NV&F@GuoYr+pCsuh7X;T(xGioio{ zofn2@6@j6J?a9x%`ZuU&;7iUUzvkN8lV55f@mH>wVPY`!JR=`dpYKfuBR=oq4rm<- zLlFqZ$0WRpK;7dZVJ0d96*Ut1jYjt>*N`4P>~q3q@n+bltdpzpsHmgu2lr8T27+BA~3G*BypW0(6{*huz7dVaibzI zu4a(9Nf8)VDc6IzSrO=tOITuvA~3E_n;=RQfz20gBw=k+1O}QxVuT_v&}xymO%d39 zH6T%@2yDI@lek?G*nC|{VzeUAj;%^9 z%;f6&Sl-1od{P?_|4;<{ZpRX{6ahCol6X=PaP!m+Am-%R-y=X@;&S^?o_-7T1FPF2 z?~y!vx&1dMu&468bdR(Af;?jZoxm8wQ>8q62gtSU)GZ(u3c-uS9vMVOXD>0TAs0&CeCosye!~KJBonQOIW*Aia_Ix<{(?G2<%*{c&YZTBCvD0 zjkC*pionjr$DPX>MWEuhu{qW%!mjwTJpEnzT~ds^72q6qlCh9y2#1pMC44c2FhfZsP1fY_o4_}!M%#OI2D z-y_)Dzfgqj_l7)uJX{Kt(eI7o_xC-K_%hGS8qx2adB%47eSHh?yOaR@b}+o(Dgu5_ zV^i-|1pMyX9>jNwfZtEB&Gsk)JpjFCd!GI$oftp5CM%{2tsAdB?=>w>bR&%JZ^D^xK_p{2PUQ&#|M$ zzoXy7>9;fAo*52fW-^oVy{r-au9I)H?GL|iVMnW{1Q2h7;jOO-`27MqS_4JE?}79? zpa}T=6x*z!BJ7Sl|uW6H~@)d!KpZ0@@DFO}l2bbU0ia>)+41;K+2sBuX8`HLmup2BZ zU!MV&0@=yP%ND=a(^$KFFKa} z^1G)Zl;6D+Vf)=7U+)Z;0ajf$|lQQv(1RhlTIiGE_@O-kLA@1=2?7?yABpoybgCPyd%nD`3$=530wogR{} zpQd7;0_2s5Vr32zrTJdkqT<+mqYk!Kz8mP$I1!LrDYxhAZIBmOd^7S!i$Ht^5)<;h zl%~Ml`Nlj7Y~sdavhn~f#X=zNQv_?x9`b-9&{}iYL#8SMt#x}h5YrR^eauaFC` z#F+ZXs}LuqVOW{d^SyMBPRzu-xVNlzSw+y z2okU4d+7~rzL9Utq|M#fC7H{V3Hx&VpZWUR6!@L1{ZbJ)%XxK0zL(MzcrQQkM+z96 z>G=+B9=A-*_6N{adg9vCnky9^3VF z?oUOavyW*CqFNDfq~Dbw&Io~y1Pv_AssLW5?uVN)=TzGEp(iY5%vef+ ztLuPo61(u42U{jJrf;J_4g=9BX1}x10=KBlD`H+sQy?5Oey6|#?Cx2Yde9=K*T&uL zKy!AYmg2#jVkEL-UP@D-O)T+26!J~yzO`LU1{a$8NeFtb`!-_yi?OB=A$i|jmGq(!RX7|PXSK?_z{;ze+b&20v+gbi3sqed-FE5 zzX*&&`%@sDqh`XT0;AFX6nL3UK2`*_c0ghh+Ft}Fqx~uH!4=@|yR-@wXn!nefhRfs z?-qdoU9Cj>i@>8X>+8h6A6kNc>{1UNis}6+@H6us5rKA`0{#*6QkpS%DrStuq3_lx z_-8}_QzfH5E2ht(zzHAnW{ZH)8HoikFQqB)a?IF3fmE)nOOyxbUq84({8QD*R(vt0 z|3bwq_UT2USjvL0$Go&f#T7B5DXzGE&vXO7QYoVQ%wzc9Rs{O=KiTr{sBvfSP~M2? z-Enrn$w(~|6JHe|u{!3Zahg~kGe*$F$K1wzpcL(qzb2+nr@)iwpXU1_Fswcjn_^x{ zQ{eNM@eT!ahUUwQ0=@^SxK$B$7vCJy_fYX*E98ADiXB+%?J+NHQE_+7sHS4mtHJM4 z0=7##V|pr<<-j7Ivr7aHvD1AY^HQ1uzr>7tQONftr{P0N08v_w-Gg~p5tvZh4hQj@ zBCvfJ#A~`Eia^`l-xkF0ioh-ez2V20{t}(&$r}D7PDJ6Lc{JvwdvxMIF~eC5Cwz3G zS_z=-G8xS?ihvWnYJ)hd2sm*D=b7ge0Vig0`}CJ0Y$uM#^yVlR*oWP$c~YEsjkD+Z zn3wL+iMZCrBXlAK{n+%hzPQ%>Le~vNAT+3bJKoPnX?Aon$ zUkOaCeSk}i(WP6dfr6|z^l!idW#eRuljQ^bXA1i935Kg&(lOR%pYb)RdLSj z-CKKUoF@9VHhgGXUsG1RpAvwHELOa~B4A=WD?UIGsQCIAi0c%AiVtGNuU7;rek&_} zgCd+(C+XE%kHTOek1NDA;#EcmByMc&rN8v5xV6!jUKzE(4^skeOJHzoeG&!6GFZ2W zz;QP2h}K?8Q($asV-^Lbb50m10;rV|nK(blUkga^Ti^S8HOKmGha^A0 zYi%yc@vlRPkIWoz^MoZ71(a7B@(bI|TVA zY(bE3uXglXUk&`1tzYQ3z83g~?OW#{Ur+58c+wfp=kS|nC^YY<7?@FwF__ zb)cvG6PR<#F8y?nZ}`mh-$yQ#Yx%k$$hSqF5AqF<7tr}MZJ~cP`ixnWYpJ~$kaGuzmc11TmQh{mE~vU`uUeQHwF2cz}6t2^>6bV=!@p-cDe2TTpg*Ux&GHtZby*M z?)L@xynTO=&&Yoa^11c_e=5&8kn1lWscAo@^2zjiSIXZc&*xg<+vG~+BihZbR6dm4 z;!5Qc#;vXt16|teoacXq@~%`qjN9i*IS>N-V4lAp*q>Y}Ar_jFXT|NDE0s@r{&uDE zS&QaQm4-W& z_YO^WDsRPk-Ko5@mEcavpuwB-t%gW+r}Ac0k~`J9gXB)-eV}A_D(}S9a;FqEM$u>N zqP5+ryuIRgr?jWQl6=eK6n83bfYf!T@;*X6cPg*S>$_7P<(YrjXEt!B@`^j)PUS^z zLw8Ca3ix7{2SIl#FEdl!sk~TBbEoo>uaP_DV+!QN{Ily|;&P|*DyRSggE9QwDcdj? zm^a5P4+y8ACwL_h?LBzS-g^ zwmfLx1sMMA)Y=4ul@>o&OlLj3py^x!bz|cnE!86z)5!x^ zh5wBNFKjwj!*dWf7de^EZ{XFK&PN^OWjga4Xlpoa@FJ$O3tqkH6q}G=z&Q@j3^;Ft z7YI0a!?Oa;gYbd@=j-t7fb+T*H^Ldc#(jUg;yVN23HxN?K}^aXj;x<)FEIwF?bgK2@~RimU9##8~=SNgZwP# z-2hfu&L`l7E$0b%j^$j(?qNCagjZuZAA?tGIbViXXE{HB7qOhLKzY_%&Zd6k7j&+D zE%FOG7a|l0Iy3OBpmPJfV9@zncy`eFG`vvI`5L^cpz{-W;h^&pJSXU6hLB&-DZ;A> zI>)P!U(mVdBIFlzUI$<#=zImC`k>PZt!mg#KRnZR_QMO<&Ix#y?fe~@BWOGCN65CF zClCtZzb_$FWjnuw7q*=c)UabapNG1tww-V0ke}`R4|uh<^9Oi!wiASCM{H*qbaTD! zd`5=LABLkn?tU^&zJLYTBrB&W2}JIp@I(R5`=&tSaXc zc)=>?T6lJqa|gUomGcpJRaMTH;DxK4XW%(i&J*a2)m6@q;MG()zkyd<>+EJS``XB?qm*g1}n9d>Sk7YaKcf>#xGs-XYF zVdp`hI0&H!REM24@bFL9y4fGX&eUs=U)XsALXog@C%pQw^YgQipW~Qok)PwVL9YiK zCj-xNoFcrS;~a-)JI>qSg&gN@cqsdW@WPJsb$E{B+;k4|bDVqO)i}=Ep@VB3=N}QO zgNIPWasC^;ddGQT5%Q~cf{T$~wevR($gkR2g^*S4Y=IZ7c0SmM{HmRU2!*PhhY_l( zcCJGxTT42TM8o8&N=XEs-5ldYO9^y@an3aBk&^C&Kuy>S38$=A-@{uZs-ZK z#<>NdK#lV?gsd9pC-8zb&P(v@8Ygll@~d%H!KI4K3wbE3QVWgc@vaJb**z3yqa3)Bf}tB>wFcVx?1PQ@FKO&@8Q+g zIzNJf0GEFQ&jhnqBfmOlIXtV*>3|okb9TbB>zomIp*rVscvW@IP4L2X&aWW_PM!0| zTI5&fv_cqa>YP4!wRO&g@apQE8F-O8=LUH7bxs7<7@BhxJTu~KfftB4S$I~&IS3E` zZ|F*RHh^ruh;t`GRT1Z-@WK)2F?deId4T#Q;(UerCE`2_uQuZR7G7P%sfK2VMDV|x zkzd59IVX+C-KJHKA**R2q^GVoQuP=bR}F@BJ0d^16r_K)9pwry!~kf9e}_&U2;V*j zg)*$fMkE=v9t2X=gZsT?ha(MBNN_9K&lYJO$#(%*2Br>Xd ztF@b`FF}^v9Bztykf_H&$OvE1O4>hDwAUh|x;w0EnP35Ws+-_lk#94>+1r@l9hT7E zv<0XiupU6fisk5lbLu`cXZbYl?tcR8sQa+|k1Hekb}+Z@KJ^c;q94S_QFp%t!qN92 z-@1=Tpw_T{v;d)xT0a7{mBG4)oezN0s_P-6b&p2L4l@u8tom^r;V-XZJx$XJtRA1b z)TsN%r7W9i1_G;og<98rZ6zy*&qM}R?WjWd+d93q>R!@&Y8l%D=+>%p!Q8rkUdCnx zzGbWl)_vA~0y&@cD`>a6@71j1`OzAhvwAJz}#UWjp%O1|7gj4 zK!VXNn-O?+$$KvbqoSPp)cwnXZvd+{`mBw>a}tOcYlF*yZj(xgkF%}+NFe%oi@C2j zRY2;xU(6{WCOQvHulv;kz8ldKMFf5`mq~&k(gff7>{h^jYput7=zKh?&dzuZ_hRG* zK*HZOkvRPOHK?ayZMX>df3Pk=#EK`;D_7P1c~0~=W)7c&&Z=|Fx%~(j4e?fl=9zO3 zB82~zOQBn7&byAZ}j6_yL5nDsExJ za}CQ-Rtd>E#C$-<@TE9mi)Pb0)ccFW$P8o?uZXoX4*ww??7<=(bsGwl@AAziquzZ=h{@F7s&9{y@Krc{P?0~$86)9NL;pL?Pb8H{|6&fsYpf@j;HRG2iCh?2a5+#Htz&|7 z@PsfHvyrh0n;dhUQ-60O}}H#fn@pmrM;t zk3&);ua}r`^qUyMB3DbVgQ|KO!%gHG>n)^qO&!=9xo*xsoY2(X)OZi*7}1Zz4v)OK zkvuh{kE}r8Esf+?Ao}YT1m4<6URcpjGt(O+O)z>jv`*x0jr^y9cC-q-jNB+Op=fRs z0yjxaRkRxMk+(}sI2x`-;BO?xi7rJykK8OV)zNQ2Pe)EkOilEhMg-omg5|7@u3*eN zB`_zNVVb+@euS8Ls;2Lenl2P&6Zu;SEQLh&p!6G_1ll@203ZuPd|w-U0#6IeqekRz z>uG}j1%Rg4#{sw}vf_RS?W)L!=e*%07(*=+`TM!|eL<#uGW?k+y=!2<>VEy@`pbZzi|^7U?cWkE&1{1aXj{Jqr8NmVYIt{#E1K05lF)zsTP6TSk*{vE)>yPBl zLx5DR-K4u|eJt`jK*E<|1T?~zL%o<`-X92rU%x;U!QZ#TwCc3J%4FA~6RO@_zd5r0 zbx82~G?TS0WHPS3TH*U@0Kk8bM(XU-wYUkP!!8Dn96DnkAn(bq;0 zNK3$6^-czQRUi-wtlHj*aGwgBc0i=AKBE*u^i8mA>US=XWryhR7#N(-Myie80L@ju zOVH*-f82vWL1N}br;`Zmk(h;1s_y#p7gAW3MxR0n>tEZz0yar+sxL}!S{3~gs$753 zQt2YnwdzNuH?0SY`Bf(C@1R)f4_IBOXlOptSG^Yk<}&F}Bn3!#{v5I=kM3Ja8V~B$A}8mjOQ?<9*T7xYcgf+BI-*c9_sPPyNUWVGyp8QK|%c?nymh$ zbtO?3pXH%m8F`$j+r{WR!eSU!^J{>5jdc%E3#GDN7x@)YZ`nesx9t_wwb17EZ?>L9 z#7eXNW~cWmD1p~P-PhkbpABf5wy`R70O8x*aL`!wem3Jf+^}V=T7{C=-{FRl-x{<2 zMtdBT&iXwY`0Zzq(peuqAMfw1`4h4-R`8!K2J3H_a}ThVGE-yq=q1zG3$2q}10l0{ z|I`%j5J)%>?P8YikpPCSdA$g|*J2hSQdrRp@d(!6J?9q)L}~Zb|6P=PF{1CFaKAsw znw!xJ*wi10Qlv0QeI|_12d#%l;I?7tsrq~8OuimzRL9}WM`_4?qGvI zu#)AZeaXUyNWeOih5n@V9{?=c%7T4v(U+0`#_HE1-#0ftkD~nTn@l4%Q9$@D5;n{g zSD-CT^VFO_gM>7Ld8=X|j$%nOnYX#&kZMNr9d6iG3^#9A;Q&OBCuc;Cv0t_^|;5Kc07oPZ8 z#tCEts`FFVAc}#_S;TF5mx~ZG?gR{1zUFoD<=p!L$Gp(MR91eQesCvR8m|H4O6v3tL^44Gq&B#nXnn#Z-Txw?+t+*wxHn5 zyKa61b|$1%KN^x&y$#?S;Z*B>DkQD@0|34a*E0u6pFt+A(#(&Aq?rS!X3o0?vEM+u zAUg!h`0#PatNGE;{FTV6i-Af$d<8J!17Cy>G}soy@wbT$s9N{Or1Xi9-3LkuR>*viY=!F;NvI3u zUjW`A07eLu4qq2K$XUbf0Pw^7tslgIYSxDq(?AZK+S~bK&^H@GVhDT%2#><`HG|A{ zGaF#TWS*hC{@$)Ldy)N)r!lr66r)M8gJS^#dj}AMp8HAabz)`mP?+Wqk!FHvq{u(C z6D+ckd9)sJk0b65FYa-B+pUP(LE8mUMKORgx3Fjr0`cn};)C{9BJLbNc7##+&x7Dj z={XPDhkp-!XkYO*~te4xV68Yu!L6Yy7K00NX8*QzkL_Z&tm6;AH!jq~9;17qpi-Xt`dXwhQ#lcKH0;t{!>Rv`fg&{D zwYrakmHc0?C*eB7y}lp0H3p@iCTlOu;4ns76b5k1-ub}Hxc;2 z765;)fDZ%kX}BI9e>{QWbT+O*>@Tba7WhQ~e+t)iCm!)}!~B)Cfbba`M=0RBz5;k> zum>srXf-nCU4Y)gn3ou{6eE?1U2+!mDL}sg*ZBn&bcq7igbaiCa64(dnP&#iB#p}e zycllVj}dqVDw@A7FG71Z z0FZ}MYV`w_3_K?R;ON$TqNoNtAWDtZn!((TKNyn&A+#nbLA;;>LOQ(>Z0C&J+*RO8lKF+eb{5vm6*xgOzZlrgS-P25rTzz1>O)99 z24`eXlEh#s%Znw;Ki#0S91KXSz8=U|!1Z!H8u)pxL;NiO{O7N|zlSUUIL;M}M*;W( zoXT&P%I~KD@ME~Dsq+D8YTo9?e-IEe*68FM+q^y?rqFso*TQw4f`MwjQ33f6U;E*P zx1)%G%f$46CNZ+#qUt}RR0Wu5;M(86O;_QJK#W}bB+`Biu9vIm!0+dx%Xb0zHi1%w zGXkTm!ixa>22NFBo~ptk7*F%zR2Al{Dr^N{6I_lhwG^(Cy8vcXmG}r^4#N$vMNHsw zT6JPXqVV|b`dtdBPn(`BJ_Vq8SMu$;+)tar`VWBu@0Y96e9siI`#u0q!R>xO60v98 zb|WxWLCVaRO#1}@s=*bS9$T+~k|CBQ&mi82k^=s@HzH~saL$G^wqA(PhXj#N=qEv( z0Ak_@qP7ER8xi*q@li(0Q&SYA-9RW1$=LKCcS5o8&DaiS{?xQzBB{_jarO-u<8WP! zId?7~w<7d6aC<)s+G~g}Ptp$DXYYLs&~pUJr$FzAbZ=!I?SQB!YLC&zw9miE&F67Y zd=yTy_;X9F75i(F;y;c)_&Ke7l>&2@srtlN{cQmv_NQ4%YzPH2C!AaJ@kJ z6e!rVCx_5m00_vFVru@@v=bKr{7n%1Ivm9DiyZ1Vm&EaY4B+Nnv~ty`v)Pnx^fO@p z1g=+1z0Kw@jihz32v@)<89i6Y=m`Lh!720QdQ&=mr`Trqnqr%M0VRS``_T=Aa(Y{HE_R2XJP2fbdi4`*VWPMGbGyz{kI|&@###EyH2v97U zKZs}pF#|-A+I>Lc|0GwU{e2*s2A`UuAWZ_{D3Od!w25H@0_!3^uQu)TZUd>e0(?C% zc+nwoB?9lp%N=l=XejRns$qPO3I55pzj8Bhz6kK=5dRst!~+O?3oqYb-~$N!6fge* zCq0R&1GsB|)St8Mo|}Qgo>X-PbSPXGV?;!jBD5GzMC5$tX7CwgdbcORya1F>fwCvb zl!qc4z(4v%?8CNwhmNF2fAH3;pa z`!)jCAO$#u6oC_V;%9&yL(~LZ;#mZEUgbJC{De<8$m8nf~F!+?71YR9J1w8WV8Q}agoUrKyy!<UO-` z1}B_i>VUzg=F}~>0FRuy4>|C;?yq%X-)uiwLJX{k728?5VE$=|yaDtET0_i(&i7zAYGrT;=o84R8-a7LLf~@1r{Sa&ua{ErDdV7R*Oy9hCy;K3 zlTv&HFZVIPQapy2M;Kr!evTLJl}IT9jX1H*086nFffaE4ZQ_~-SBp&J5kB8%+TFLK zR6hW?`#C%keA@!-PPhai7vg0vTo)6Z`#V5RA;i_ja|59MNxXcFfqDeErt@6}mLl+< zczF?S59b>*NUWYw_~z?uN9G*K1%|O5PUakAco~JmZ_{!J+eanMkMT4=VcO5%PBeh8 z1j-4x*Pe250yxYGfx6v(kSOm3^ln7I2d;||=YANF#}IlHZXZ`1NjPXUG0`4dfG`HPnf!#+~DK|F7_KctIv8=`N4>tclP@Lq)Ofs^tv5gMF{-10q!s7K-O6CO?p zS@kRx@EKtIGo0{{rz`(mB`N;PY9M`ip&a+7xqlHC3j<%?DrO#z^#oIhZ`+6 zmP&uPomiuTm?Z`d_q>3*jdJ!KIGkrejgeJQFo8m&#Xg`?6gF|UN0sX}E?q8=2hxoe z$A5*D?j)8m^4e{P>1?#Pz@%b2&y^e{m(E_vW#HG4px``nG4r>$5wwF_fPf@;vc7*= z1c63nRrhlU4=!*6x1oK43st}v-~>2WWiDaX7AJT85h%}~W7akvw*jUTmcuwwA{0cYzz-dyeGnZHg zPGR0<1@MLoc82k*^SB>#kXo1y6LxcTq@l)&EQt&+IK!L+4H8&|Q>@znLb^u7ifpMl zw`Oxq27_AAjX~+{4ug=;8u6-vrWM&%Qv)o8Z6Yqb7KxW4Pe)#CsBL*cO5KDIU8i>m|^UbpsDK4zDrNHaG!nuvMfha6xvp+kQa-*M1OCbia zG60y+;s*rK3tL@)G&KQj?M5$U3;+h(o6YkUX<;~P(HZ94(DsFQ^ho|4Nb5-t%z-je z3m)u&sBcOmdi{&KoRdsqZAF+u7sFsahNqi0cz$YIJC z#%!?}QldCh!H8bl*I!&(eJU-qkUv?I)PIK`AKOR>`uN!I=OZ+gKYgY_Q5dW-S@@wE zsOxNb6J;988fn+;vA3%x%+-Kjb0I1D+0mFu!CzX+#IUN`t>o=)MSysFW@#YUh0DNS zkpQ>ZYW6@<_j$M?7XmxqgZVLEQ-k&-fLUCi0~qN&Y)yd(7kbbV4Z@2q6VV0Py%ZBK za``UZ6=RnlM`7%Do5IBybvfY%4>Wtte%7KU)M~8Rpl+IoD4mYkSP8&EM>gvBz&DMo zgz=y~HV5t;d5@i54_~3|!khcU$m9ZZ8f2JgHMQ8u!=L&`Qmf&7IlKaK}sddD>K z^g7{!#-)$E{`3WSyU+`9G2wnMgqMmRMsH&;oM{y3VLN~&AdO=RN^e?0XW)?*aPd?> zljAiV%He{*85XXo5=a2E^I;++ziK?)D0*b6s!R-T^N+w;8;Uc6rvZ_FQMC(@1T z6;Jgu(c5Ht2D^g!)7uVbqiXFdctPDw?bX50dk+Xh9GGXq`RWi501My)BIN$&!AGg+ z!NS7pFufiH#k1n4(07&4`5ypXbe~-5R0=(((StZqkUL#UQ4%^y5X6%lMFSFNyLzR^ z@?f^V7GA}VBv5{OSJK2ZPW98jS>CVeufR5%1br7hqOd@_P9sq9TaU15JMqzW*<{fN_=hpu~c#f!7U3F#YXt zmT~IiSM!DI2#h!af5v^M&kFk59NAgSl3Z?vV^&z)lq{n_1-*x^<_j}p1pOWzLE@~E zVClM9##Ikp4Kng0-Ezv;BTOPVBE@oY4MLrk5=`|-!rK9dg3=>pv|*pl0rl!rh|JoM zj-ta%>aWCll{QPi3oc}w%7#{&r*+<-n`Ie}!CA(%d73X%K14E&8S8|)5Fz6#A*3^= zzaNg7n8qH`Cn{e37=XyKD;5S2m818hycXywz7&{N@x>=p6cVC8Cg}T0==)0O`w-{- zN>asS?}xLEV?X}&$yD>ZNlY3fDVgNyF%uChpvcb_`DF73 zjBc;%R0*^TP@hnTJzy1dW#8&ei#>d&EUMcdrLy74O<@f^Mc3B|3a3^ucF|K9!wRmR z94TL&#+kt2aDfJ3pKDjIc)r4q_`oeCD=@WEM_GE?1))HX9fR5>dzx>m6J_ZQ!ubb5 z1ocmqb{9PoR{F1$#V%&Sk2n3kXr?(0Vg$&W<GDC8u;%C~j54;8Td$mp^fr??YvIT<`eYDz zMvq;|-;J1nQbCe+#&PVv+-8RVb8*Yk)u#zM%LUJrz<^Zzn4K#r56NqR-cxYp-KNwI ze{l+^jrW7jhu~Oh`lM?bCBxJtkj@9R1n^M+14fJ2Na`rZxyi)wkxf#;sMjx0wP}3DlEg!xlIYrk8|MgfRhBKN8kh9$}5E z2-nO)IEQ3=;Xs()emF#;-YVU6Vx*0_pr)hvXMA=zbcAWZKXI7JvIz0{9{HI_$M z<0`^V1z~k2gAF-LhalD65|yR*aY!Vv=sgUlB#3WvRKqt7WIFG+3U6qCdWyiXpTMru zB+!VGV=hFGw8}N8rou(AT20pNPL5P(F|#kA2eSf@we*fHoo2j|P(FbSmd0oB=%#{n$w7(58_ zY&oha>W@37V4BVsAp!eXq%aB^L$U9A1bzKc0Vf3LscxpAHuup|$vj#CiQ6y9ybd3n z4H%Fva9KHKKqUEPG>KJFKGV3y1A4jpfnM&){(l76W!1X@fcpjLtKM4xctn66O?7JH zeFF4o24zlB0Sp)fe5xEXAb>{%=%Yz21@vgDQx+ANexQeG$nl6j3e5`Oa{~0$=rI5k zrZ4x$0erSRc~EFp00V;c%W}+sLBPvsmVjQ7)M`FCQGw0Zx~Y%@OHFI51bJ;enzU#OQ>x zjPS2dYa9vqvAThwikBq~RXnc(Rxl{Y+kr(#(WKuGSBF&|F-|wF;!t=2Kyp^d$dS;U zIwV`xS;X63hq}R@gzt&5{p=YwB=<; z>Ilipb5O@dXnXlgpMabt;gOCq;Q0U$ScS<`MH?ppW^@@oaVsbXg#dvsBXT3Efi}di zB(^kB`MX$oGJWIg4mTWi{Xy67a{Z@VzsL3OM~3{}%+8A+^Wu+o41e3@iPE}0y>sB0 zo^~6Z{#E0p7H$sQTsY1hiQ5d9gwwweUczu1uMzLW(Z6kYp*={q-*vRt=x%V``{2`k z%5}6q=xA=x{nB+D#q~(O81FIHwZrd(+XAP5%vaZohJY@^Y~{FKCxSm)I+k1i_$=lt-RX4wAHlo+5&mH~wjty7&kuV<1L14l&Bi~PTKY%6 z{u>-ELh@Jt{4hVh=KWvFf3{B)ZY>!5RaWBZ_}Sq9hP2PY zy#V)TII3X%qw3R+%8`zGPX8FU5N-_|^`ib!WodT--Z`VC#?o5LkLQo~!wbOQ4M)|d ze+%)l6s`#_3U?0NdN}s|Znz$}B%J;cXBC|8UyR!UmxZHzY=@iiwd;1kH4TkNP)?)L}}`2fV32iFL9 zrVs9iMSbvgy!XQm!WDdQ{Tjqetq%Bn!l{q-k2uVe?bQUQe}3314TK+qW1Gyty$i1L zr|ZQ$X3Jm4>vZIS#+{>qK40T&9AA{Y>Ua%*HG2Oy$I--M+R4v={Q>h2I9Z2%5=tkW z+1$KwYGmWV>0=wGr$#qU6{knXi^oT%W{i!8Cy$P8962&}V&kF18{<<4j*m}FCMKuG zHcX98j7^VBZyY-@Gexg;dgl0n@yYDef4-_L%wM^>kinUeiP5oX447WOZ60N}Mu#fm zPZ*0qjXY zIk*Xms1#sOb0h*;E{>fT9XmENJ~_dJ%nQA$IC`|L4MF6U+mvR{@99Gjdj$}%nX#kl zU5YrVQcV@1NhYQbj!n5aK;ce_8uEv=YC;-p4|MN8K7M3o!}tUTZEPFhUwu#=8`i0y zY1{K`Gc?CO(~30NrZv^%d$U6;tr`>2)|6?7iQt5y3+=N*))l55JIg-XI@x4*HrsQX z?79v{o^Q7{+4cgvHZ0zp$s+0bC8Luc4? zo9+5e)ClOUXW8|v+({C|JJ6lbD!V4M#%@K0nr(Zby%50KwaEWOvt8RspTyRpKBip< z#M)4!9bIZSkyEv(bjUi^WUo|-Rub8?=5&`=_lq`)*8n!0VXb6^tt(IiuxH^qvS&Ub z8eoe18T3mph2WDP$advYd$ILryV*X+dILzLtv806?X}jQQL}~3E0D3%Y_GCjuo+d| zWY4oMYql4!Y_{uwP6o9!%*Xq$NPGT#dojvvhX(A`@aHp|mG*kPwl&!cngNiE--L8z zh-$^kQoe&R^C%w6@V21C4ma7$SUEe?E^Pr(v702h<#fA{n7u+EajABotlHmTOal-t z2NGdjCWVMC*0dVzXlS0jbiEyo+Dp$wt88;yC2DsfWdqP5C-u!D4^F7XwyhfiXkzQ7 zt3<#cTlLl#uZA3iq#+u0k>;T}Oj2FG9u%T3RSK>(*R(sWiDnQd?a6Lb)jER9(fG$1 z0Ic+9QPGBfS0$A}tJ_Q19IOvGV>x&YS(lskO1_@if{2+WpdesFmX`>3qPos@H^PgU z*H)Apm6_LIF9is4yc7V`NNT-NNqs9lAkk~E7t;&j^mNc{rgWIiW!!$+VgVPiG$%}Z z?pmOnXbJ}G4c3!aHKB*rSf2?r*>jhnSSwvASdHj)A?s0zx2-P(h~F5pK7SSZP9xjL zw9`%YhGu&m0HJL`3l;kbKRYoGh_>~ftD6P%w17g*)B_>wUrm!_tcS1a{x48@-lg*3 ze~HS^Tq>V_ITf}~|6f+4U!oD}tmh~J^X&y-3PcZ`gR;dwhNfPy9n{eL2$e;E10n0w z36#RJms<~`uUhlwZ48-;Q(wG-@Fmvw1s>{F(Dz?qhW3Vbm`(mT@^(weLLACqU5m!O z_I2z94S}jMDY&VYQqYK)I(zAA;SE8dXrx!+Ht+;fn^-c3Ed|9rc0Uds;%z7yxZtc$;s}7g^@mq&iH@ZiZEY!Db^n z{QyOl-Cc}>t$4uzxW=?w#Y}2M*i~F^hD%glYXvcCcR^Xq4Ot(0mE54#?B6ztY~uq+l+s%_wOt3q|Zj+hLHr zwW`TpWW5NI99!$GKLHc}xrQ1WNt*3&w@R`AI-}0s9k-XB4dWXTk)=qnalSNIwFpTa zlZLF?9m=9xh{grUMFNdB+GpTJwbKH$XXAX@FPEBjQ=9!77;DY;`m^kHF#MLubF*Cy ziw0#?$z%38OfA-TJ@haF%h<>(?RLCE_x!;?Zu3RUFJ5WSQb=+8aNiy)j=a9KK9~ z3rfRAt%h!NucNer8@i#iZ?>teRCz(ntdtPcm2I{xpo=YTRo zsIRezwA8u=NXSky_}|O!{(z~*mmkcYAKKr|BCTuE{ocQd`6hG07sAbk;Dr%$k7$-%c6^mg$AY!p~ zFU=+z6Chh}FKe+QXWHk)KqX>*0~4@@)pnoN+yvBftp7YI>! z3HUuM&LrRFHrYMaR@m$3SQ*Th2EdUaI|EkCX|gj-_C?)xrkU?`p|}`P^U1TV(EaRe z+w2ANU@ls#52AN&7Y+_|+Qnvj#SSR)IGSKB{BCKAMVKu&+cB_yf%PdU;F$F_quEX@ zN6MWbwjcy3^m=Te)nM9(06~K484H%+eCsGGz$xGSkhP%O-X5|JVhU(QnTaMI!_0aE zMw#KI_J&n_CY$WxCOg@@(cTudlj}Ev-d13c?oQxhvWbEZ!-Cw7xkw;nGIm zd}tLnTpe0}23q2bko9vExi-{qn;0-rzOm*~uE`bl@N(wrW{d_V}y93o_;`IdU4eOOHzr^|+?XY;6wG4d8HRoQO1{tl8t}*vgTU@P2{I}Lpe=M|qGXo?nCwNxf z+c1}=nuW%mZ*63+Q)9DfVg5Qezr2Dui4(V(w?&ngT-1AyfsbsDjJuqV(vzrQT+N+yd?F~y&w^msMse{Eb2L#Rlx8}j0k1z%~EQpwAA^Ay; z$+QC4K((vwB{Y&+T)wUZUpo{MSe0u&WS@oJ7u#T;)lKGYa|y~kx*Pfc=E`~29alG3 zOvdhu_}Tf-iO8?EcH{-*@`4d@S;w*3)J&*`LH)|tLlR)Ys#sRkc) zYw+Y>UW2c>HTVS!;;+G}I+F`qi_oxPtdJ#WVJ~a5&shcI7^8#(<;e9ZEHt7{^X(e0 zy0xh4QBKfD#>Agvr|Dz4kX{T}+eH)Fp>ZytS=WMyVhUE4T7@Z(!jvjw$`??5G9?72 zWHUW^Bflq?HU@?gLy25*zkyX?taGRH*o`DrXGj3)w_Vi;?Zm zBs06+V4H`WPYvdgUuKXbdoul*^W%lg(4aAP+1SL45l<9Y#HkbGMSdDt7cw)rI}UQi zfuUr|NcQxm2911XAlC}ie5ya6i+PwkvZ-Fy%L8Px#o<8|dvK^w%;r+azF;J?`8|o8 zF*c=g$rXFRjLg)fi6dhpQ`xZztfL7|9z=|J1!6%`gYh1+*-z<2@!{g#yy#IrWntPG=birs;KZG zkxk_b!sUVCej|~N4J7&v#OxW)rUua;yw}!J`vF!=#S?v{$oA4}hcP%bi0;|4S(>w_ zrBz8RKK$c}*5FVEoi-64OrVz1k&4Mop2B79DS*Kq7rfR<^baL=7SYc#yHj3lqJJma zxtQ9UNTrhCU4AH=7%1e^ls@nvBjTYMsykykPO(cB3X~!sCdyh9MUdvu{6-nm;3~SS zF^cWlONs}^FEggbMh++mFM#UeDR0tZX{DFUtaWstU)LD~(fiQMi~vaQSL%@*9=kxP=Sbg1zO zc2oo1espqTW@_?C@!0r;AxdPZm>q(mjI|WAP;s#ie-}S^Wb$&I!ec%3Q=%^pN$M|C zQHh<|AxKdnpYmy*;?c3AlT#;+WFawleh%$)WNhNl%wZ$l&yJ_07OD|dZxL;we22GMn?nBy4&PepN?1ru>q{{2krRvh^mD%m7gTwv(sBUJE z9ks0XZi;rL$SJTa?=ERpO3FYMolDCTJMIwrNJ;YBW~H{-OQ9t&5l>*?N*6_@jh=Ke zlQO(r$?36~8R+rp;^mW52hegeV@lg+68LUFPZs@rC*`WAH#uN1K*^+f?Nb8T7jsoE z)l5IqfE8a;Q=v zU^O&K8a7K>4MqNjry)lnNkWp8U*2_E+EmxwtfU_uQDG^OO15rt!(FbwS;pr?KTJk# zyij5|bQW?${YB`b90rx4L?Q0#4c!kAGmN1p-YZ66F)^IO(Tx&UO3`jiF+Vh%OO!?+ z4j0*6x)|@zrQ*qbo`u9#P4(ttXz)WEGN3=l4jvpI9jCR30Rsk2BHfaMVFDRygYhDL zrY)xUg*FzxVfa;ktLwM9e!J^;xPGVWZ!(~2M~^|(lI<9Q3u)LZ#<8jKNwM<0YWK$n zvXH^t-X!!JB+1t&4^DbQAzGr`{y;PChj12sf;}tCJ$Z6@pDQx&#PKPdbDDw8+6(FK zPh#XODO4?)unyVBd(ddGOInEqc8LVQ@W~Gih(6Yh38myKygH^rE6bfH=mzqeuR6{h z4|Kjz<~e1HD0`hOY>oLx@Z4UA)Ihc$CZ6IjJ{;y5wYgL_6)zOghvHgFq!n7-#(~u8 zjN{pCZfI|2KusaC`GJHX2fdVz_V;SHCqN)_g+#o6K&-No27-9ycPC)rE1Nc%7)Tp^ zv{VfY#C=|Vdf=m}$>I+{#?kt^I6eLG!JQb+Q?Rhyp#aUSZE#~xvH%HD=YDX~N9^J0 zQT+QBF@;-AZT0`0Cb`Hq93x%^2PNV^Hzf)a0S5vFT|q zU9vSvV@;-)9DQggiuj>J9T=GzDegZxgQHL*`$wmZPo^+6 z#e@%19WTJZmGN>AQ=<5AVJHckZP242f||peHtFhl7zeQGIj+Tf5*YY7=hNnzt0!A$ zg_b6-GP}$VrDMh9u0k={r>2$Ogl9IA9Vntqi}o9tB+R+eghhx!c6&K_!|Yi&#a2MI zXn!j!yd*EvA~34Esxh)GKiA^Ku&O6*=K6~vN-pk!y+E_b$Y8l(P;~Oh^vQ`)QDr`|dCrQ}Bv&(EYEEN^Q$DY+ z%hc8F@I9QF82e>%FgkgBVy1X>&Ri*sjVM~|@|?8_HY1H}SPz_}Jp z3$#f*8G|-Jn-8Q0_QYY5?MI_CZwQR&!k(S}`J8UhmLg}KL+NyB_9_y_F2{+po>Qk< z(4MYFERAWkp(=KE6RpEPw)J4# z+Ubgsn@X8isn*S9Ik&`AT`@Dr_OvEpDRQRibv!gc8T&Y34h_2V-=SQ~tH#34fj!g? zh1#DT!q?|CCEZHW7WtBqjdS5x_8L3jt`(ufVmY+g5xCoyzMUq%&jxgGi75; z38aor75X4e7~fJ@)F}20r@1y(xx}GXmvVz#0V>4%UEz~i4_NK>fRgF%^Tde<2aIC=+*=jB8O~<&+C0 zn1cEj!lq96?Tq;T$tg^`l5uD=3g|129s}{co}84FV}2Nu>tb&_GgxYPS>Hv&Q%GAN zr2Z1>Zc*OVG<1{EGn~gFt~)G>_R@AVrtfM7OS#DAGP~8nKrxE~^tf$_1vRMjLLt{{ zV8IS_WD4BtSw*l@_3956U%6VDjQjeDe+dVi#nRVqQK!nBM3YWTjJZpm6nT$TYSk^Z zx6snLS6MKSxfD9QT9Vg-%tg4NbP=6y2v(bh>OPkr&SRM*sn(>Z$2_5h<#lXqYG!(7-NUhr8fAE0GFS?j|YO`C4uD$M>OUduxugMo@mV5~ib2a%_J{ zF8P+1W9tbT6Ma{3j>O1**#waVZI5-MGgC(@`-rQUD^>tJb?ukdm@p^XH)B%j=_|<@IS%OIxw>l55;f zgZ3vh-fZN{E1;900$3yNr^UrJbZN)oL?V^Xi#rW!ePx{ zPq$H_t!IPIDp*+PnGLtRAvE3chR{%-ZK_5)425Et%CetcgDuO(Wqn0KHMG2-8d_dZ z4J|LIhL#spLpwMZrfrQjqo*6CG-@Q{2{9PBcsEv>Wr|Hw#wK^#Q^9B#T3&v=C|_QF z4J|LfhPE5=-a^~(U>Y(+Gc7Yz#y*W!(M{d#%cWf7Zsuw@#!*N)%zuAnTD)R=mX*v5 zTZ=vWV0F)iT3%{Rpn~fz*>b(3aVvVSi(6hHjayzJ4fQR|XL9Ly5$g=a7Hk!J&8pS+ zo}t`M*E*9KiEehi=qI}X+;`=k2lTSmQDWd=M=g9jZo1G-DH~#+{@*u01buSIwW(^yI;r%W=CG`c2D5Hj!ruDk=n2lI@=g?VHbXIRu z%TGaXb(L!$4J~ha4J~ha4Xt3RSA*GdtI!87ZbfHyq2+bcxpkGgp5Dflu@Bu2%6x!l zF|e-90f`f3-s+v0!D@|~1j=fzn($<%rxGfPvmIU*K0Yx%I>LLt#hJ3XB~@OXp7&Z#!i&1sW4aQ z>575C-JbNXo}ehMo#gtZHEbyww?-<8CJLKpWb`>Q&`|46+}PDiv(hZs)Aj9<3_$yE zgG5PS8V621HYiYPAd6!_vP7?TxL6IG={ixwc?}O&t2FG%V-LzxXZaLN%{)Y&o5-;w z2g#>;l=$UpouMCkFqCeXt>gf4NqgqnX~ks;xG=iVbQxZhwM~q zZZc9Ai^+Tsx0MI5{^AkUn_o0m(?dA8;dL_nS0q(eu#HE|Fl$xkI=Kq7CxKH`h#1_R zNhnhU`#uO`t_4$0i%;45G#cD9flG@>{>3#f8j9!O_@U!dnCR;Bf^y=57OZ|KVdBjTgbbN zJ|2UU{Yvse;p7I?ioI;iVWyJD&X;@46$cmv&}#G!4mTw>Z*JnpK$=^c_&JbRS8IFI z+9_yHsLivRHsFZB@vZoN0yOdld_Vz!nZw7A?uQSFADP*J#oVn}<~=|FFb^KPtYgFU zu?+`WIsqA(8a=!fA7r?!Ys1mzqxd|@x&zb4)*U?7wBbe5Ca-LgNd$h6@Cz2-;wHphSt#U-DKas?d9UzO^cV|%;xH>UdX^Be= zBynmOSdim9S6=g2w5GuJ^rH*|*-(D>Yh`OT=H3L0eM7xr$ci?eHk7_P7e>_ z93z(Jd7??}OlkDo-mF9K^h?9t&?LM>F(-C^PNhW*HJcBr=3c1xei}r-ACu5eJs>9y*EE{I*Fx<8^ z3eYQF>cY@aaUedp&)xrk%%?FDf~_21X50hS6{jfm8DQB&@F*p4gh@7eXdLR}v^<@5q~LTsr*`?}nfC9QLHbH&vu|L=DHNPv zh8+QJVy&9GokD?@&^&XO6WrtLIJgek!;v=eQ2RvB5Y)SeEj8PNlcPLrG~^yr_VI-0 zQgGnLP}3-+OrjQ^2IS%s3c|GkNH-RrDRZLPDb%_|?$#@|>#%X;?Uiu}5=ND8l@U`y zRU;6|;>;M23A-nLW3G>$C?|kn!;uc&?I6! z?@C&+cKxEy8DkySjoPGNy7UVs#@Kd2|MW4d;5)?QHyp~$ShRZ!+8rg#?Z#0-dZj5& zX}J&jB#XTdy?@SgnDPx9jEp$)B}W2q-gf-5@#)Da^g@5<8-&?8Sx~`*nvZkJegnWrgZNr4B%$Ou-eX(_DrK+lWBq$YZSe#cD4_YuM3Q(6r?H=LQgL|&ZZ55cMs==^y zjEqrHjC!!)T+>@e>Sk@x&Dzq1jzP8Ux3qj`hRT-Xrp8JGzcfCISVTX;e`fRa8u|8SVzi%i39S7FP03o+L(1#!u$$Y72sc{X>%3+X~FZ6l`%meQg zcPiYK9@N)+Z7aQ&7Fl3edkCGS*G;9@uF@;}Nckyo&wkvijRqJz~5*vNW;&VZ581EBM|L(v@C8dQ) z4s*Gu({OB&yW6mi*h0{-K3!S1+Q(BH9)(i3rGdH++x_au5v;0L`ZS&ID|PtVm3LVN zr^WCUEAMo83-4cm>70XbPRb+KrPU{G#N&QP?;!Wqy#o1W2l=s4n5e$~T~_TpSFpU3 zhgjKfaaZX4QE2U*OH92mShYk6Fr2IjN$r?2Q6P%)W`a|yc&3Q z%k>VIRV}NoWI_F?wP$tkD=#OWSvB9t+ryEU3Zz|$U_0i)$#kjVsc~e&LBhDqjx*otaHHln`7HV%zb8{j z^yv(ELQ^b)RtzQDq5#u{NT)v8AWLSNbvVlFz2b)?3#Q1z_727N z4&U;FPcgdJa=4yD9&o2T&Q7OpG2sOVO7P@pCF{FXk-R~~rglY>-P9P6DWdMb01y7_7W4@TezduGVB^09!5#V+tt|+C~q%P&g!>9Ie3tg z=;FYaYuxA6sDeWJhd#Yago&OUFr6)~)tEkvSyYpEI0h!PA!pGjWtlWqhf8N>w2UQF znCEib_fNb_vjm(7?SqoQ*#Ma$&KH{<+gr$0~1v*Mi+EE%AJ4#xsqtv4K*UGRDaB>v(vu?qTlFsTV>8uWJLBW9W zY+jyIE~#L*<~&5DH5N>*IM(__T_{h?mlm!i>4Q1Ehr@+St~Qj8m*nJ>DDIHqrjy*} zD)wQ)**G{gc4_hO6+){8raaCC%jm=`T4LCe(pT!R7bq(O*#u7a;E~`%4*T+KAy~U7 z1tXtty3U;?Ms=1L)mb{N8LxAf!ImZ|Ex(PHR`!j=BbSUZ_6dkP>6**(> zA3_7`2z8E7R#P#R?!_t^HaT~u3Nn-#{5q$RiVu;B&E&n4HCXO`_>9eH;*&8sL1UAF$RH*aTbOI zzB3BAab$AhP!kpH?me)%JYycBiIOK_ic#lzC)nKH>Rv7-A?Ol0YE{~K$Rn%Sc*%C) zDkKIFIhuF?-yc0JwyE1U;u!M!@-cS+liNNyxp0F^UhZ*jS%XQT4x$I#sZvWTN{B^V zA0Kl0I1b;6qQc6MUK+>b6`8xICH2CK2sD>aA+)&ffeyMyu8yjMGO0m~SaNL<*LS_Q zR`0FNdu#XJI=r_|?+u;7rGndS?i=nC@hXPql_#%qye&PHL!Aw8G)3h&l~VRSR;$$k zRCkdTk?zLsF||`%EXqe#$0vAMlsA}kCf*2>OZ8^345x1BxR#$r0(I{ax3@AT>wu8> z6xNi~bWSybJJo5yT*sXz$>KDo9k`7oMhlfUWDBcr1M-SPFIWVD4#!dS@;xeb$W%uA zlEn(DMI770SmPe%#U*!ah4DfY>OCNal-guPr|<+=?9M?l5kTmPK4vW`80rVV_;uXU z%7WZN_APU|$1+tNU0b>Z#5bo-jmZxY3}g zV8T3{PjLxBMmHJdRF^C>f=cM_7ZCEj?n;N)@+kYUu@UU9PmPUuq}>AY(q3k87*}F( zVWPMn!w9GR7*#Y)?^6tlv!n&XlZ_#NGH_EVTB@wX$w~Yd1_bA=U^@9gfi4H z9he@Qx@_z~%S{NG0vupEG5$>P} zKWOf{4dPzz(zaL0TrC-4B^#`*%mm;)Jbl;MGu}$m?M`%IuX_FtfX#!7Q=aPjjMAvO z+_3t2ofh|;WT43;^^nTX2$Xm;h+9$k%mz(yj;(SnRn68=$AYrMI1Al>{GfaU8yDvM zci(WeUVo&({e}Q7Vz1aT0*h2*9mmVGB&6gqg)^l&jM*HgFf5}=2BTf?Rwmu+My|!{ zKcWhYb$YC%8^tzhS4YmE6GloGP}TRxC-ET@thmGefTd265rI+K9o0r_<0>JzhpYCo zWrN}fI5KN4};-X(o;zEz0Gv=@P%Z zZC3Tw8p##M?XVES^2tXLxG(`bh8DE8rv26Cgam^F1{K^V#9EkGn!G4S1?3GX{wt|a z?@+61QmGqG8IIXLcPqXq29J)+^!KNFp-S9|fwo4m*nF_4zIvkub;^ef7`)XjN4YSF zz!1aS-aQ-u(@Z#qO*xEU<7JJ-B@Z!Sa9bKJg=OuuJJN9ip_T<!aB;Z5SK|;(QWyK>2lB z#c>-Zr@o-%9`GCC#aePuqwog5yR)KZGAIu_E{My59DK9~?*NHcn#%eHVlMIU`UrQ5 z_i_CVrz^aVFTyOvU9I_#FRO!E^g0qw97>+KNS^oq2;HdG_?Fwl!lfcs?*T&Lv>~(DFt278hD^V9TL65@_SZ|iG zQJI7gr~a}Mwz!z39T0bfDcd%8Z`U!g7DH_hr7>B<_0D1%v%9`oNvn$-G2am?nKtHM zK5bMVOKOE;*SYxDFw+^BS@m^HCC`*H17IeaP8JsG3bT7|43mMvI_ zaV^_!usiXMz!UfnTR4uw{Vthq(E@W<{kYa#8pLH^ZF^|C+NPF~v4)5<46{<}fNFHlH)^Ko^?K8C%EWL}A-DDL* ztqa}cnWhl8*~*KHZQA$~YXfqU!M8q*OuQ$D#SKo%c9%_p`9Vl^ri9BIa_n+bC7`Pk zuvzvm6FqAEMU74^@=+2!QdA6X>boMkVJP=<9a4P`$+tp;Eo)h3@t8gJ^vzIF;DgO?kbXVW?Qyj+Li|rM6WfyY5g#(%E`9Hi+##C3$K#pnf^P01+fxm}C z%+#_Swq0o6=@q9|nCN){Qt0aFJLxRf8hW3nKNg`*<)so8DlUm z$0fHpBe!xbV}^0RjwIwRL&~@$|Q)~@ARV zrFdKk(PUlyub!pf8*x4Z=|x<*u)qh~0*4*vz@mG>mU3m)StaEb1LF&vG0LH}ZT?>3 z-*dF2jgD_Nb=y2vq0 z_inO7>m=Kz9?In2t|I*|?@-C?#w)~}k7jygzM<`WfxpnMofjVbcQpUzlgzTYgCv_v z-eCScDcM@`qGp4UyH|zQH)_kj9VJf&>P|-HL;iOzHMlp>&9e#mFb`kEXs3_U>K4|l zw!2}<1ZWV_aB&dp^mzc?o+d3QNYwtwxL^IyT0e=_2J3)1~YkQ_SGoi|Qu zwE3=#npOy)@h}?tkT?NmFB(#GR?gY zlXl~2G2g_fRcN2b_lOE@KST@d^N1Ge7@~#tc|;5C^N1GO=MinFPkl7gw=_6!#5GGf z|3o)EUGMVWnZMVO^U*%?j7z$Hi@CddcB*F)a@{md;3D zo$Gccn*Z%e=U&haTYuig1!s$J&ZA|yx?fJotGvJkD>6=02^xo-ld6dyrPCDhDK!<{F6OekG``M!D4(WX722b9T zgLxP8oKro0d{Ua_et}RY*V81ohURA9>;^f7au-c=7L8mI$*;wl2trbr-{#S^?)}At`wb$@!XXbEge@fz%zyzrB%PNV|^mt#8>>Wwp^4u{)hE4@TuJM_yqm zuN}?57*OE4n0xnKrj?eui&(E3-0-2=eY&8)@{upg7rexs_wrrc**QX{`rFJHr&Vd%_Cu^`8OPMo%=7&l>k|Y&XsA_ycROOJZ!9+iMwi;om*O`J2UT; zRWtuXS^h^SeNM-`C9S{*IVrNh6*}j|0KD`duTSN3k9KF8Jf3CVmX&w2uE0aLdi%`z znB_hkBVFb`XR1#=UXcJOq=t4->#jUw`e;ToHFw6QR};|v(2*&^1)H= z^2w_0Jp7=qLe+ByeMONzu&Q6bbKaYx&qy`Qu;f#K+eUrE>LB+Hy<9AI9+z{j_}Asi ze_gq0V3xP@#j_6b?2O)Pk_|}KN`0liJh7zb^X_xY&eo72_a4lEJfWNSh6cIik@mo- z0*~OEwN3VadP}xPGs|k3p57=}O}}B;Y~+2x7WefZG*I3?80>0(sonX~rTGQ+>i_#I zm{w8w`RMENCqFPdA*N`wRYreLn!h??vzU_8BBuLhgwOQO3Y+J-Vf@hl7_a4-zZe-P zX%b=^`PVEaFg<*RcczwAFmFW}SGhpm4lP`Hd~4(vz0+f=O|z%_ zXB3$kIV)ne@8R%AymPd?S_SHvFTX&Z7E}4(xiVrpg)O#YDyK#Dijjf~mOaJ$EIX!1+Lw|$Evi-iU{@K`wilfD)comgh>tE1Z`M!} z&RY{L&&@LEYmm~urhGE!U_}&*Z14BlMdHGXdlEc}-jbeDp3|Su!^3VGQWlY z3Wmb1^VbWG_v%ly7x?q)FQ*sy^XgBh7x?qaPqOR!lm8c}f%{=8O^LgVH4*$e!6<@eZcoL+vPy}+N>vI~v33yjtF zM->_$WfhYgyYh1Bnx6mXm96E*`rP$gdsWxvup71}EkC+Y{%EKCwRwxd9lyCiTI*k# zw-}=HE0-a!63O-dw){V@6<;WSyp#X=ye#o~LptEK z5(?!{aPsT^!2L@w1CCxRu~7a*C;za#T#0!@I^eZRIpgz#rK}VZ+A|&*U+~Xsl`fRO zwAF|VrJelxfBv7>N-C5;DSxC4d9AXA(&Y=KgN4$%2hIQU-ms_9@~Y&Ilp(KGtx&o~ zp>*{^>5$bwZ5@wznrqYfIx~`+9|R z2Pf^f-XpEcFiy6guSn}YJWjTkqoj4894G7dIZ2zpfDA0hV9mtm80plmNi?I4SlXE2l&}CUh{Pl%gM>i z1kEoi>}ulOiD#p(+qUG>by%nCN?P|bn%2LtmX>TiVpGd1qNZBT-aAZo9vVuCkg(X{;cq`L2*7Z%&qVDxn-8+TJvAu#SJECgD^%$??>!DQX zq@@cSbz9W&x^1ida5(C^uJNfj3!lK{xEiC@h&%k!r z1-oN!9Ed|P8^@p?x19MvXSqxHa$4ua7vWM|i7(vU+Z%yJF%C;&IjoE|uom8mO)wqXU}x-(eefQ<4@cueI29kp`S>J0gD>D3 zd=od}Hr$C{;Wu~~kK<|l1FxVQ;GF)7#28G#GFS;~U~O!GO)&%8V^{2n{c#9pm5^upTzXG;EEX z@J{TFgK!v*!tpo-XX9hI7@x-H@l{-p@8VYc1i!?u@euxmr|>-H;&qIWj~Cic(O4Xl zup(B+T38=%#}?QQGqDHu!z>(*V{jr)$2qtFpTcMHRosB@5>*6kfn<=#vAF z_CpLNVi2oi9c+xvu|0OfKA43ga6C@Kx%dP=gD>G)d>22&&v8E<#$WJv%teoU40N^! zjK?x~6V}A~n2N2j3--i;cpr|z$@nlX#?|;bZoo~r6+gyZxEBxL5j>8kF;PxDbUqv4 z*Z3R$g?{;1tN9Y~Caj0)*aiDxHcrNQxCYR z5bwbLI3DNVa(oRxz_0Kqp2slxu&3>b$I5sMX5gJT3UhD?zKomjb3BB<;XfEFAELD0 zAlAk-%*28C06vb-;M@2K9>8DmDn`Y+^_9UCyd67YUmSr`aUs5en{hw>jDKRJoapNO zmBi}U2-{*WybmYgW4IF6;fJ^nkK-kbkP~ICHxa90Lu`XRaTrd-dAI`C;x^oiXYntL zk8|s-jJIHC?2Th^7Cwh-aVH+f^XQk$BRXHVU>Xj^Ik+0%!Yde4+?~EGhA<5~<6sBq~5&RwX1EjN@Fa;Z77aV}2aRx5NmvAF~ir?XByoS+onM~^~hc{y?cEE146eYn7$cVpb^0V6fe+)Wcm#h(E9g#F9XsQ6d=WpyukZx=E4b4)!S>i2 z$KxzKhF3AFqC0&VOu^f+2M)%`I3HKxdfblt@n`%K<0`rJmB;#+iG6V_K8!Emdi)H( z$1_-@vRi%vrr_<^5&Pl@oQlujtGFG1z%!U|lUq-HybFioOk9Ys;wQKt&*0x!s)}1~ z6}%lg;=MQ)=i?fD7sIN$<&?u@Ovfj22kyaN@wRI2^h5DMd<1ZpWh`>5TTUsI*L^w5K_2>a z?15u&8ZN^%xD&s|-_T#*EvE$5#5Q;*4#zpT1lQs&Jc#Epx`A7MX_TiHopyJ?o;V60 z!{xXEKf-VD1bQ2~|qTR@?ClPPPw%8rBaSATL*YQ2v zhri=BEH39tdcJfM-ij@80A}NCd0><8cSc|3g5-A@fcpks1|NLRk0qn!z_FNAH|pP zZTu2{z`w9ahFg9Rd@LrCVMlY>e$N3m?Eo z@fqBNpJ35eZh57!Hl|^3ycgHv`}j5ff|s#KYs$qM*cjX4-FQDv#`(Ak-^b7J7+%2e zHg0_hSOwFtBM!!~xCmF_yZ9M?kC!pLty@oROhb7`q`RE)0i20X;%a;sKf~|wGKRNv z%PWH^csq8)zBmG>;zE2L-@=daTRe$Z&~ES6n}i{}4Le{T%*H9W0H4DxxC@WtC5-6c z)|ZIYusL?dAvhlA;7hmxci~CAgwY+{ddlI=n2MdTKaRrbxDsE(kMJ8jfw}1K8E?VP*c->-EL?&w<0kwZ58-d<@8Z^10&8MZ zl-D#k+d)4ZiPLZqzJS~COZ){dW06d^yi!;LGf-ZM$ z;;<6dLwSk2Q%^S>iIee3T#fJIXZSsy!M`!)4!7JISRXrLUmSst;!<3X+wliHgW=uW z@`IRyEwCF7#(*Bq>tH%|#X&d*7vKtf2Y2E@yo6!>s0Wj=3AV@HI2`BT5?qVha4-IZ z7tz<>t*-*s#0vv4{-jxXaT{2UMAZ}<o5O=zGtcXpq0}jOT_%ObP z+wmY)9qN{QE4IM-_#(cF@8fp-6u-i+@q7FcPh$AJZhZl)h}Ezr*26}aiW%4ryI^*r3`=5ptb!?64;y0|w#H6)C-%lcI1ESOc$|W>@iAPCPvi6WDz3+OaVvg;U*gwz z2!Fy;cph`{I!4^@_ER(#$0V$X)v*@V$J?<5w!=*9f&DNG<@bM_^Tsha5vSuET!2sE zN_+`l$G31ZZpY7X4<5iD@E80IFXCSqHr#Ee9|M?(%_&pxOU-2AX#(&V4?eLBz+N~2hvEnvi<5CCK8lNQ89s+=aU*_)yYU-5gg@c$=o#tG ze>JSMi+sC*gFQgHPh~xE{CS zmv{(IVJ=2I;Fez;f5yw`8{>|T#|n5Ww!$9R7w^GgI13-7^En1hevQhW(F;BmZ!f1^FlZAT(j#@cv0w#Dvv501un$Ghcxj)(Cl z{1t!4KQZhfce>(O8iQB`Q?MasU?%p(Y|Oz&aVfrp8*m$biQnT%yo6yB+;*10s@M>l zVg`1>fjAUL;6!{3pTOm~8aLrq`~>&m&v+XDz{rU#SFDQlu`}L{Lvbmt#&_{!+=oZ; zEMCRPNi0vSfHko(w!%BGKR$%Ba3Ma2>+l2o5|7|@3`}<0Q4y0uu|4B689$JC7T(YJDfqZ5^Y@fm!Ll}}Qr|{=pYflP z{sQ-^GJoGQ{si&Ucutk_>}jq6Rq~g`Wa70+H^OvP>Tii%RVk+jRrAllU9)ztKP4ZFe-rsZw8gRq9W{Mwp5H za5zrHM{o(gh+pC%{1v@3+=kZU*`)0ZG=f@aTri)i)xtAwi39B(ah4BrE--c<#JCN>zcM=~!dN2-C zrN1ZQG*#-K&-g|76!B+Czld+(o46Ub;%BPN$5;5hTFkOek^WPa<$D#c6OWqh#$&O# zD&+)8SH|k9ly^JnG;FC#{yP~zi1Y|G*0OR)&sC-V`S=9!Rit0QSBSq&dJ}$*U*XrP z)cd0vZCU3?Ut_%Wuv?!`m3+l9NW3!EAbzVFWmzpqcV_$@*n{{zq=({g;t!FYjMItF zC%p)tR;8ZjR9XIOiEqI7aU1SbrTzO=zh(VI`gc|O^8)4)k9@?H`4tXe-GYE{6W$WVGi-Rr03%k#8;7i0pG?=xJ8xu-=WInEl_etW* za3$m4X8eb0yk+eneOQ%t{)oR2|AX|O_?Ifv6`AYSQ(TqlN@4|7##hBA#8a^i@lH61 z_z)aLd>lSPd>%eUe1)p(EAb8ZF7XdZe~e$L(yp)ZXFQF6qxVraUrANws|?0yk|#s`Q`Aw2^hA-^9ph|mRRVDvs z;#=`k`~tth@9-y8rvFuy>8}$12fg#%cu`g6Gk~R3nXWwEjJIG*Y_CeWy;YgMKMrI3 zNXAblJ`EqoC-50n>U&<5^41dHfbZir{6dxd`&7w)ocKvRkC*Tt40~MiOFN@fnZ6iS zAzlOPVtq_iC4UBX!(MnFj#8yP(^aWwHZEZN62`wk{AGLx-@_fM)b|;FNBjt$z|(kH zmHdCJQh&?>xBfUx!tz)RLwJiS(>KOW#Jl3%*bj%Ql0O@Ba3(&9Ppi_N*H!6{^|+bw zA2R+c;`{JN{29-xQr|@kU+9)s1dCw;R!}8>RaNS*N4x9yI@aMrtgPih>yo< zI1A^il7BJ2h->hD+^$M{_N&q#2k;oStQM*JiE68GZw_yeBAGk6KFVAvB< zuk=?07E`4i)Ic&tpk8rH^Ju$e0PTdGojcjCQp5aaJ<{6oYi z<8<1$ssTct`n))Rjlw=n)AJV^X7o+f@? zmFfQ`?pY$~`tsgCRmzXUio~nnt;CzCGJR{}?Xer_$V&J*YG|32*1L8_#Ga>FiYA~gZDa$rAU{>o3J`I!rQSUX5v7#s%2&2 zIF#E7PF!}I&UIPocE=U?9KMF@@IBmu-{TMX3!cLBcnPne<#FrNceUzu;V3MFL9C6p zp!42G$=`-_Ked8o4Z>mQyysEk<4I4#**F)UMdy8v6)fvD((CYJbl%@6} zyo6WKmIbQqi^1|(2^**-EX#Qhqv*VcQEW-P19ri|crT8`F*p&Y;9^{gtI&D>qSW&S zY3Kcml6Ky=DDEP@55L7Dcnot@xsG=YyofCl16c9DxtuT%3#FSYgfK4$S+hRv_-j68L^&mY4o%bS2d@AXg_$WS(&*N%z z-j68LZ6N&~Zo$3y4W7g^_%}N5N0f3(%C$#b{?2<5#alF8%(5Dy^FBmLHz$23I`2c2 zcz@FO;5eL!({VN~!xi`3|_#?=qcis=fk2Hz^a&x zb?{b9#pc)+JK}I0h2wD&&cKIpJ}$y#xB_3s*Kh-F#C`ZJ{(wK>Y5X1k#H*;++_irr zFdB=Y^Iphkx!$a4u@*Y-iIj93(jD*)ybDLDQI_=pPQV!HfzJShqC1v`xq<7*j z+=t)d5j=)};#G{c-S!m2l2`_7VLfcA%Cv2<3wFc7crQ*;WnG(!596b_5}(Ic@eTYC zKgKU`51zo&_y_)pe(5W%KN=IT6o#-C*2l)!4SV1{I26a=c$|VWZ~-pHH&xlUzJnj& zhxj!f#G`l|FXLYrR@5yo0!v|8tc=e4L#5u^NH@dQ*dDuLcN~Vj%9V{rmb!&&$YK8tVQoA?#(!&9n!2s?|H z@CsV8FVykj7=v+`j5p)0*a(|p3+#xQ*aLgxSe$^tb_kg?HiII2=debexULa0R}Iui$&Q1$X0qJb|b25Bw7& z`7l)$oB0qbL9bl$5g z^PNF@AZB4Uj>d;@GS0#|xBwU9)3^#Zp!0rSsdo$M?f5kw#8Y?{Jqhmo`7j3Kuo{N2 zDW+o^?0|i7AU=o>;Z&T7OK>^9hU;(#?!-O#HJ--bQLnw|dgr`HSd1oJ3@c$(Y=pOC z3v7+Ou|E#M`|v@02p`8Ma5=8TH}M_ZiaYQi9>(K%60f5-(VfpIjKzvr1yis#Hpf=j z5i@ZR4ngPr#?p^Dq-WtAT!k;-8eEGza3>zaU+_0PkG_)beEG2~R=~#C6f>|5_QipC zFAm3PI15+d3%CZ?;tt%2hwvy~#edKzeWmN4AIoDUtbsMLIkv)%n2Ce&UYv~6a1k!S zm+>{+fjjXa9>%ly2g>CDE9@42uSm|HWwxBp6G2rz2USz$T)dVl=XwoPIj2Zf9M2J9;v^K zro|viQBK;lFGSjDr{t?gI#reSHAmClcBGwl%lNLO`>N9Zf#|ef(!)qQ^C9Wcq@DSZ zw0y0=nJx#X<7}LZ^KlU_!R5FTpU2g>2G`;S+=!cTEAGIZxC;;9Av}u5@g$zXb9fPR z@fte!0c8He^?JD&z~WdEo%;eZK1jMU*1~$&0GnVdY=@n&EB3{Kn1#-L1gUQ<=?R#F z)6uz~Ao-m83F3U>i*O}AkE?MFI=>es(`_cb6?fon+>ZzF5FW+jcoNTGE?z@RuhUC? z;TXW;SQ5)%H4I@btcTA13n|aJe<7w4Z;q|79d^fF*cS(4Hjc)zI018TI?l&MxCEEu zYFvYBaRY9}9q8Qukoj=#e~7z@@5iHf98cmIJck!C7q4Lvy-y(J7R3M-#~@b5Y8b*= zSPxUNIkv)f*a^F0ckG2(I1ICKH0I!RoQ-pFJ}$x~xExpG8eEGTa3gNUowy5k<9L+AIeB!5@Z-LV&%`#8f$ zXX9ubixV&hr{ioi_k9ZA?^((C=W#Wz!L_&nH=?;Ow3GBM+>QJ303O1lcpOjS8O+6N zC_fkK^k+C0!J-(z;#d;PU=S-~H4I?`wSp`!OvUEd3Axc$EtE(Hvw~SI?l$qxCEEuN_6gf zNjc8_F44K)C2nN=X56Vt-|WKOs+>>m#{;UI#~#9?s+=Dl$CIj@*Pg+1s+`|m#9UR* zbFZN#W$XE5I2KXmytgO@R5?Br$HMp5f*P0gtTI+pWqF3MmReQLU$KEI^W6lU?NR2} zS-&Ob+;5cmo2c!R`KqM(WPV1gG9S%~h|>OJsgr0myDIG&NIFZEx^hTQSEYTV=C$9s?5)5(qq*MmbIL;b3P~Y z=bVqp^v?O1%%^j{CFygTPv+OEIcnT}qx(9N2GkKdWZ{QKPJy z8mL*|=Wv~0_Wf7X{e9nmg$w@5@4rTx-}?R62=j}-{~F=`?(e_CdB6VquQBd#0K4Il zee!;BcR;^k!}5RCxaP<~!~Qj;^JBsPIp)US1J2KqSGxHn;Qtt9eiQgVMwy=l{*O`S z2ZC#k9Igwd<_$l?oF5!GWK5p{!w21S&yWE_2Hh`9QRgdfk_Y;Y9NlO5{n`ocn1O@( zKQOq@5czdwS>DcYzyAG44jNN%?6Bbj3MTuF?05fQd25DKvOCScBg2N=Kgg6QYn4@V z!0`L-%WIE2)jcEo-6xrvb!lI--{{dJhxC77v=sY)`@Qz+kYNw@ote2*2%S4#@7{2%#N7s}UF@^$);eEJ++!S?CrMBOKvKhwU0 z5-6BYKmX~xm_L(G_j3jF>F1s1CX;CL#Y?7w`SkOOo}-&TlP^{>$?n)nWkmNoJkD}V zk+kfFo$}<+V5Jl)Pmja;S=juU@~RgqudkFBluTNl?8fuT>r|+`T2jee8E^hfdF=|7 zmm}rr^40R>FpyW?y@kr#Eaj~+g^^E_gA0{6zd-xsFp^i^%tGa5NhhUh0sNWvO)XU3 z+5+v9LuOuis|uC3TFM)33L~E;pDtA1)&k|pCDFX{Hd3A}R_9NjSJ35U{!IJ6D3mWG z`AVBiqRDr(U! z^e~ zmc;Zg=Y)KhWuQB(|7-j7-~EO1m5>d!jb`A_NU`ueeKCD+GTh=rX;PqT3-EHPxf4AoX8!l&Kd2v!zApeY2w5SYx-RcFOXmXZFp^ znj-N5Sv`hST(>YQkd-uaNy`CQNkfv>EzK&K6)!1Ex+Czu^`mvvN-dIF>#g*mGuDP@ z%+2t;_UgKY@<`td`PVaK);%HPrpZ6w+FI`?XPiD^ zZAtm{Tt};7(Tu3E4-fHP%JF(H&CT@m|8YoK|NcXg!h9K9fAyr#SUaV^tZ3(gQ#xL> zs&vls)h&{h-gjYEMBgN7;gXg)8CJE_bJ0^O4jI4h)hwB(dpc)%CC{{f>2( z`B%aM^K-+FTGj6wzkW-26{||ebJt@$)l2FUD)Q9$w6PH~6jsDnwPi-wId7P!dfK_1 zu!G~hi>-6N=Xk0Y-_r72PGrk-TO;p!$dc5t3a2WBJuZDZ*Hb}zPfE#Hm}|`+-nPnB z|CQcZRZjUMdiU*_HCM*%TYq)EXMt6*tinU>o70Z^0v#Z)X95(YfN{4x7?cZt*cSzbX~K~_f4Ij z;gL1Yy3{YV|Aj#73>mvMH>b9@?;=?vSB`T_`oAgXf0g2`b@cy-Qo^lDZoF?lm_jma0!zFsNguU`fXv6BDTZPsd&!>T^{V(~Xxo=c4koY3{# z>T9KDwocDC7Z@^sU3%6l>yxqu z_4{s0?Kki08&=`FvHdPg3;Qm+luT!3^^|pW#*)A*`DfTyt;l~mQ~?} zersEHk}<&{v)2WNtX^jYpUql0HvQZ=@51ct_lpFx-!~;yZPTOgwpSI4RbT%Gpq{zGp=9$XNwF~RP|r^w%Ko$ z%ZkphDwS(jdFYM{VfRN|jrm8cSMzH4Kjkt!bvvF)FKS&adadZ`m~c;%MSoqp=xK62 zz;Aa(=QYW?^`D4ucAdeo+=s|DW$bL73gP$Ne$Q6Udov~;=JWuv&E|T z;re^WhO+Ou;PJkaZ3XX@zI57m)RP+6@cRYtv_Rv8Ha*wN_TlN0TfvHNH(b`7G#Toe zTd7u$AqQnnBlhn5H7s@Yx}07|vpscs^m`;NZ1>%{;cc^9mX>wt%ATcJnp!y4d+s4` z`nhmjA}x<*|9V2#8?DRKQ?fukCH`kUyYuQrx@Xv4E}0?uyq+TZ zAeA@Fx3rCnd0RfY_!^e#t7F0xOiMb5D!Lh*xjIFu&CwTh3I;fOyp$3Oa?4u$_JA2lNy#7m!8MQ)Md z$Z+WmE3$3OTT_R9pnGamQQ>B`Eqg<@NX$8pVa&Z zZk6va`uj*1$NQt3$@N0NKEapZ-(O08W7}U{PH7VT^`t9G`nv|@TXFuDvS3R4w@Jq* z`TN{1*YW({NonQ$$BN3k2>h}cd~$Z|Zz?B^H~Dkg z%2h^xhO~c>f1lL5)1N6HC_eQ!l#eT)`Hz;D?-2O6NWbs$UzQJ6U-;Wqv8*rcQBr%z zW9!chr+93AdZMPs{_Pgay4ho2koBpS#~vbU$b65zO4|Im$4-!m7kX^{ea=N5`*JN= z+dQ^@3RXL;pCDIWU;VTs4SE>%9|v7=?tEfr*8FZ0+lq{lCM>?ShqlE>~QtHz%m zdy91UWsjXB=li)HTW=|J53~Q2MYcK2u3T9z(t7PSWi0DguU%6X;VG~EqO|?A*IqA+ z_>9*cEsgliYj2Qceb#GxrB{FV+IyuD=e%~5%<*}zeL_00UAR3%daZr9Jx3mP?GSFS zOtq|z;dYvQj_VX|Zx%X-+mFa%>Jo0R7Ba(aU$oxpvWLoYza!kvkS^#JZZDKRyEEKw zBICM;+v6m7SGcVYn)V2{m&nrT8E)5*RlirbeJWk9*oWIs$x2e(XCIR;NbuQT-X^!< zeRi%iX`IhKEemhF&({0Fha_0ZvJU&~L()q}e6}o6>j$6xx3uM`&z>qP;*UN%N-8?$ zvxiI0-I4Y?_2oN!k@mba%i0@h50f=^U!?uLG;n{U{krt-*OB&k;hRW1Tzc@^NV}5E z%7I9GWd->zcBK8Yv}|LPeMXl1yHWN~S=ly4*&jw))_YO*7pa!DGS+T$vwYh(*1lV2 z?AciROXwU_j_5+BqW8e!Zb(jZC!fku0MU?GI#ej83#)mQCP+M7xiaIVRCQBCG9#iS{qD zK97|w!nj2H4XJ&6qP<>LsfQBnax%e$M0<~(O+HO~n zzV5u;?kYXe_mrJl&9eHPvj3J1y#Fa%f4P3ZDSM|Zm4T=1FJws%I%VH2+;hr4DJ>g( zDyoR=1hR{Htf+C)zaw-YIYMS!2iizikJ5q4(g&k;;J6GtpacKNsxU?e-j;!!1~Twg z6PXJgxI0I`}_98lvDI2(72l~lWwhsIw^A)878)Qu? zssmZl^U*qRO_qF&4m6f!AFBiUQ@8;gI4p&mry5c&puDon> zI#9l%&PABamt^+nz&UA8m<~K8Rd{t^wCu*ib)dSe>^>b>Co6x14(xL}!7Gc>=?fWn zM>fDPnJ%hwGc8%Vw&4ATnUZwrpYfb4Z65wF0X( z!xR%JV#Ri~{8LGKBBex0Pa`e&6k|JE{^@3PxE0&Y^3O0yuN9ka`DdDBm=)W@^3O6! zj}_a&^3OI&X<)H%|9Fr8fV4ZVzvX|}fq~FDH6s zm8>sgoq|19WK|iC(10_hvl-*FBAe+L4LJXm-Yb@&X_yQm>4Uvg^tmH^Pe+%v>6?4MGn+48gRzU zGh-sG$Voaz1I~Xj9y=-M|6Y=TzNKYXS2mcW%gz%PVFj+p8fTX`fiNrZk?d6M3It>x ztYQH>G3b-sp_SBJc8hkYV50UwQYqQ7*cF3OI>t(TT1%H9))=X>M$q3u0)gXlXs|=3 zz(^}lUJlH5%>q^0vU9X+nH*ZB$F36ejnXQ+){$}5f=Tjf4JS za`qEwSWV)$1dH_ zC@WAzc6fHW3HYr*H`(Ov<|a_Y3h0lr+AT~#=InN9mz`k((z|=&B+$|Xd{&^f?Cb1S zCJ-*YBRgQbwF!8wz)IP*+HFig7D$BVXlDZ2J7ISHpzm>+@uYs*q=vzgI^#)q$U)z3 zAB@s|)86S8^gkk}G=Ys8?;cFb>zyAGByg7rNbk(jR`oCe>7Ado|9YB$^iCf+%dmTy zfb`CJT@`wpR!Q$%Y9oO@CLq1jQI2$WUlWktX{0^e&jh4*PU~XpZvxUgSz5~g6Oi6n zP(cC%O+b3*7daN$gG@kr=ST?&3^oC`ce(_9`u(#cr%7GuouYEwwzGm!+HcxBBZB_b zvQh*(>S{bHn4~)uXWc2LYvX7Wklq=pjd;KWq<3o8kiZxdklxv;%l$zUkltCZo7p%M zkluNznFPk0fb@=jG0=X<1f+LLY8ewuKzip(Ip*6FO+b3*V_lAuOh9@kLsyl_CLq0Y zMUKvPjtNNbl<`VnstLHgb6?Q+h0J);G;P7~ptCnk`czk>X~8J%H#wTybA$d9vV;Tr zeRF$Wu#6rM!ae1!fLxHZ?8i)?oE2!JIp&){Su4<01CN_P87t6R0}D(bNfxsP7Meh5 zD=<<6i%g)D6{w~Aj3-Q>q!pN{ITo9MoK^T+O5jNoC?R{ckOY>PK!O#ht@Hkr2^6;i zO*F971mdkgOARbDfjBFmZ^y8gn?Nxups&ZUpEiMjtP67PWItm9vZv|VRst(bK-QLe zy1A}20a;th>m;j8K-QLbb=UK(3CP-Vzb@(LO+eO`Z*`q~!31P&siWKDizXmzOE=xP zUNQk$TQ=*yXtfE*+Ony-1YR})SzE4Z;1v^)wPlK~ldqb9?rBmb@R|w84d3ay3w*-_ zboB|hX9s;nWv`ahUuXQ0U`bswk`~DdWv>lJ>58SR&pSbX8_5*tnIiFbO#!m{{MlRr zn@m7fpQY&%*lYrFsvuRo8T1X;D!jTSzC{&v zhjh(qU3We=fe7blvOVbArX@P#KH_MyS2ut!gHc+S?hy_I{fD(g{Z6C(9lI32ta!4+ z-5>Pn<4#FOC9C}nyOjO9yE+t%(xP>)e-8RHcJ9bI>1!eoEU`aiHNa~^M&Y578j zPUi>XbHeR}pud?^QC80>tm5TTrHsnK_-+ykl+%O0-&%MET{YHO1PdVMEr+O03X>^90Db15`Rg*J=@!8VC=ALr8Yg_3lr>p4mo`k>U zBci=67~fM$SnVmNYt>dyLJ?iBcDwE0=1GXxS^+aV0^01WLP;}H*&%fnrifHFusaJSB90-1u7rkoKv{Y(mbc@8_W5x z3`c0d8FQ~0Q^Jbusbe%ybhhpUuLr%lbewDpOtwfXQorICp#fQOHdOI{CqsdBSrzQJ ztK{#_7wYD>(F9~idq_S-*qcm1PUvNOTwBF=U8YW&lq}=cS8+G_26`5^xk{9NV^FKu zUd8{WOdAMmA@Pq*0kVbrHSmcE$N?gtft@BG2Z%%sd}ac2JSeAu&rLv%2RCV8mkCHS zLmK$P1mt*7R|8*~fE*8UbWgL}1Z4L=Ligo+Oh9)3^EAg^6Oi5iVh!vw0onaOqk;V< zAiMu{8u-QpWas{_2EH``*|}HOU_Ec#D1aLEK@(f5;v z+m}s17X1(nCL1zdXzdzm$wN@!do>;7lwAZUDbb9&L9Im zJ*XEo1xS|{)j*61NSDWJAYcO0<)t-{U;@(R6*Q1!0@B0PG*HF_q=%a}lR!BWknXCj zdx`QUAl=nXa|BI5x~sPaDwu$D*9Z+%Gy&OC#%Z9E3CM}kqZ+7e0&=1>Q;&RAOh7iB ziMlVUY68;b^@~WLx(Ud()KmjCOhC4!wK_?%3COmTs3%(?6Oe6bkWP|f0pYvyn;5mBI8@a#l9Q1mxOax=b+Dq;Q%Ze0IZBJt0$xmx?qANC zQR&LnG)pfc6{{l|UpDQOh4E+w3A|zgGUr`niZv!JbKX_bubH&Wd6(7_c-;hK&bw;h z4HIx1`E0U(mee1YnJzQ%JhMJfxA?WmvD$oX3_}v8DR{ogmKPnAK z`a=G*f1;HE-N4Qz$7=hvm6wyFM@b*Jy?ezJV0!njeYul&8MTPu&*HQXNIzBp7+L-}%2$3P*1sNCTjPr*|=(r>+Rf>)YMQM3j zKtjl$DHkFF6B|oBG2~uVmRmM~1+^tm$^>Lv)9(e^NhTmip3Qn`p}Yx54}7kH3ML@s zOVf*md}F2jq`TY7xcHE}S6UY-iAtd;ZJsuwM#vvkNg6RYMdBe-fHY!)9%O5pfUNb~ zw2E3LAg!9MXYaL5Kw9OMg6z5`Agv0M!<2oC3CMD}s58>g1Z27Rb>G+61l)F43HfSC zNl8Ow_iI<9-LL5J@U~Et&XKmedC1>R+nufJSq25@dp~8yQ$xNHTEH@$@iYo}Lg%Md zC`yag0y>8L&u9U?w6i;#7RZdZ&@~{FfE1`Dwhj5VYl%-ZlX2}S@tDs49ib?#OH1q( z@_Q;vi9g>W@!kbW)YmfEeM~^QvTJb(^fQ4lr;6?&Ulo};X_;2hgDMV4$@YLylvb`) z3=R38)GDUxDl^O!AdUW6cMA8JfK*XZm*@Q^AWLhl?q7zRfGn*VQ4$zIAWRmHzSYql zX#(zy-xKm})>f_3R%OwumAVd%3PovqwN>Lo{sY>o%d$tZC$J^RimW|1CgjsA1WA4L z1Y;~)!Z*6mCWWH3Xf0qy$Upfe*_1Lf<)|~uv{7bjZ@6TfZ324Uk|~@1!zLiJ^_up? zBPJj_hxQq=%bH^XvJ&c-gzZO7K-RflI^*+9z@5)2A>Z@Tf~1f1g7`G%^I4tpu~3xG zfL`KS5{lj`nF3!#NPKCi{I?PglT$vu#I-2o|5*!g#w`vxH&c@K>F1(lp;#?i3wSmZ z9alvP_$Dav=P5w0k-2-t7YWEAMoWAqLKU}3*rWRp=P34$322EP`}I)t!&;(WuD950L*+Dc(l@%cZVJU~U0UL{ zP_Y-Z#64Q#b_!s(_I@b(Gc6!i3)n&d2@#U`I25l%>rAc*`G1tbvf3`Itd`}`*;x?s z{UyWYwFk>vh=)|g0lYz^6B(D}jQc9&+-FESpw;gW z#cFw4!1tl(_qBiqTEJlnkZyI4+&>VIZgq~4$4uHB5`QuQb4WaH0_M>2vk90(;x8uP zaTe9LA^$OL;z0dC<=ZKrMPxnp#gyOaR+Dcza zvFEjw%VZimGR18ri{FzH{izl(P7Cm+xCO-4lSI*!cr98N#_5p%s0^0Xd9})FS3G)%eW+GTzraq2wSY1 ze94q3El&$5pW}n?9 zHX)|A5)@y{Juj215CiJqFahDQ5H~K zJ3YDWP8FvsNXEe_QChiHaes=xu4D?-ln=RfHgn8fg`p|F?pi>)ws9D9yempFj!KEr zqIKmMpW^>c3uqww3VT9|dzPjv$4LFGKFKU;Ibzn;U4M=V$f2dKUSgSM0j?TSYUF<$Eap4B(TuraO->|#WzZdOVY!#J(oIH z$T)jZN|d%n>s&4?gJcS{Ybx<)OaYNjqnF6?*8=uvr!1v_=k=UoWlEG5tp&U!%U=t) z7?k)cDM{`gO}cV6BHsodTy>yV7m`P?q+kPHUu>2c>HQ-I9YXx;aHV(Qf0ZdW-y*=Yi9 z6~B+i&uJB%bmwu9 zDq89}<*}3~tz6sqYl^?PES|szK8c?;1<10ftQpUkfK>6jF2&zW;QwLnP2i&{vbOPi z`}S>eyOR)-PFO;RBp@J5NO}(o~YOU8Dwfex;>I)ADKb!8MzSQb((=DD23cT}y zf15SIXL6JIodTfMSJdiz1wgBV8F_zD0JOTB#`{qL(CQN|=vtK>HKbNwPB(u?trAIS z_4Ralwp+%D@2K)nUutDlS#{OW>Q7uMJyn^r-4qzyovQ$7br^>uPXW+sCqrGn0-)86 zh=uOq3V>D<@&ObmKx$=HnY|ELx`XV7Rmqid4uf7{m52ILt1(s9H`MB7&g!v>0Y>oo zFaVzdpp_qMtGi4A&}tZua^n;Lt?~(!D*#%BBLFHCfau6yX>?aA0MU^zJi5m#04l-r zN~%mBhM{ytDe6Yqde29Ma!;u8ut(Ips>-?*LlHqCF$I=Z3dUqiDOkBvL=K1RTf|2Di}}4Y_}QkcHDdP ziB824-Flbzle%nxZ_mNDbF0j)LIm%>w%Q{4_61?Q%0uB=e$d@F)p`LN8y|0rYChiL z)P1}K=kW1%n&IOu5~q)MI!qsLSGatpyw#|8 zPn6hH?@b)qNwPG}d&@kOCd<-vA6>4>JKh2|Q(`lG9L{PV$E3zPw;nY~S>yNCL3ekz zECsaO(?+4Vu*%>7U>|e2-^#^eF}#!a(XaB``$PB^jqJW!0nihhukC)b2E?UhFuMCP zzud~r*7%0AwCY;4uZ@jU(LT#@eZX5m@sZaX zZXrLj$KQeT!M?=+zEBQ<=Xihi0{F@XT#WV(_s4!Sf!3w>q0jD5Y!A7XLHs+vhr+3& z5wJE;#Pi(WnSt~gL>+(ho9C0kcO|IP1G1Cz8L)>1JY-D<`2p)8G7uUR*bGdB%XIY83`9w$YA85^E%wAfO#_+oWeHC12XpfXC4Zx0v@ua z1{(s_cVzGshw;!r=1|2yIN;u-04z%jO8^|E04%PZbdN0x;FQ(fYXW8kHfyCtST5Y_ z0&++76=J%3TfjqYDD&8Wl>$-04^;YiyVp1&6_jyqpQr$YR44b=Cn>w2HAEa4FpsB* z%Q)SRw(W8+3nvFW6iyLm1*~6E#567n=hzIK=*1f7;686K$I}8PZ)29;&tW{n=6EO# za(=)=S>*V$fMq~P!RwsEmnsI>xSY5zfE@~uI$jtsCxf{3Tw42Ln`1e{!Q}xDWs&2x z0V_t1ht~nWUNJzdLnp5an5)U)Q?467w;8<2E$oc}4_R~Y?+94el0kF~@Vo56XW+RR zVZ*)C26P0TN&~<>Hed&yTLb3P6mbiu)or$Wj2wr;eE|=JQ^(%~tPd#yzczvM(qJ7Q z2$*>ou+jjR=7($@OX=>92Rvj=2EPkfOF>kyjf|hqFetc|cKi<;!2f0`;9tISzo;lM zR5LmFFDn4-V3*$p%ws6?Sq6<~Y?-xmn^yuJYD1ZC2drBtbAWr9KiLfEUsI{XdxJT? z5itLQ9FL%T|Iy}n4)z!B_X8fvBF9ex)?dkSHWnTCF2z6&)kgu-3r$Nu;BqiP&WpJ?*ksPCIeT{I+P4v=59VG zIOx`zBWPYg2K>!_w=*bLfP?B$$P0SNnhd-_>ozhNMkgv6%%C7>zDx!`a+C{g2Cs4? zOM@P=CW8q<>vJ;Lh}h+xXfv=M)079zQJ4m$7fnK4rOjYh6AF`q931Vkr|SC=?9F8q2O?`CWBeQyiH_~%fX*Lm_amXT|x%@J7eyd zHUlp=fpx**WKHjx8Z>`_>^Q11j;zSFC20K?*@7I*L6n0F6m&>1vqP*-|A*Qf{Cwc2WQpkFn4Xp;BEng8 z`d|^q1+AY^#G&lP3ATt&OHnu@IGn=S)q$XSE3)I*m2nhCxjzkBpCDT>n%jd5v#j^% z-T*Gnvfg2n0bDZJdglbqqB_X^1t;Hmw)NH*qVThzhr%f0%AmCXLQ^YTV)*TeVKVahiWtNCKwz@q_#AL1x zcMKMBW6=BqMd1Ib;e8Za#Ge=r?hJY;oF{?@g4Rg5Xo1P-_)su&P8m+%VFlovGMd0| z6acTpq2u15ISZ{z@8WLj*FkycxScNlXwXC9?8UP|Ya2ye&iV43QW~r57R(j*3ktxo zxn>lA7Zrfk7~ZFX<_?PJVl02!?!_ZC)bE2H3a5xSf|kDlB7Wo+<&TO1L@Z*wdP@Ni z@hMxrtpKba>$p_DqW~;XNA3mSPYS?x`XnAn-&FuMN!MYKaKEPjOpn{>pYJO`>ivhH zxdolsKP&Qvo=cb`vlafcIBZ1Y8Qh`>Ws49>WxXgXJ(rr5pv|4b4IVmICmGrjLMI z0eC}mG69bQ@P=W4K&}GthT&`i`3k`H=^9wcU7!Fw^LT_ouTTMajPpAJUIoB+9%7SX z1;BTnCNNR~@QjxUj8*_V<5h;aQU&N@j(i<7mw~SIPDcB`*>mJDM!T|*ha*f!m>9Co z08s&6_QU!bN*@Lb-e7c{q5wloiOP_98#xN%2_d;Rn8sycTF66LgL%D)>6N&kcX_v zV84)cB^m7Enz+PfVDC1PA@gxE$YFmM+6-RjT5&+gL)K)_8?wG2gP+h?2ipwzxarsE zhI{qkJ}nQKqnp_$4qT7T5&s7s|05&hp)Bs#2ViCp73{|y)aFp;$znTo+^PV0pos?V z!xexhi%}kxj#L1YxTFriF$#dgeOC$KI0YbBh2Spk6BU496`um&6a~N~r!ZQarU1C) zN2EAI0nh=b$c-3(_UuuH?Y@vaMK0ma?97mdeWtB03|Yeg6%6O;>f(&8I9lh0%pmGY z`4@fMKebJ>lMJ?FxNQbkW4OuSGn(d_41 z9iLMoq>fL9%p=J0boTnUHplzvIWL4fltqqz2wB%7D|LKLF;F`Gaj=fR51G%B<5&*+ z%QnY9jz!_^kcYCkYJ3#3?n1OHxQhPuu?kmMHSQqri2|@l{F=aD6@W$JF#@|3fJNeW z1U^*&7Kv8~e5L>_5^oduTme`lJ|ggi04{yyZPnP?0%Z0!TDC|E%yhJ`ab zpgsbY0$_}71Uw2r-{){@cRN0N&2{WG?{w zDgd`hz9ukR0r;;iqd8&cC;&SF_e2173dj*%n-MmP+tB}WF+T1Zd(bqlXANNwJI$`n z4_iCi(bW{AV7p>~t{z07QvvAeV|4%)C;(kOjuZ(6U|yX{pj!d(txwrxkpeKUt|i4{ z1z=v?LSTOdU|#vKt8^cr0J!5*q(~_M^Qy)Iuv`JyeAN=@Q2-`dJ%L^YV4}4WI9LJL zd@UfbS^?O6Ehex=0oZ&kC$LTd7{}EFHYfn&$iLX^K2!l1$E^hV6@YQP#0_AR0x*uh zBCtgPSS|UJ74E|ofW`4W0zXlJQ;cJC*n9&+RC;RRk^til+(j}Ch{!d$~o30wPi zU>u7YfS(r5tl`tA0XRbe(7Tcp=O_SbP9kuw0-)xj9E0=2^7jZJhs*5=VRHrem)=d{ zlfrVj_0g4o8um~vAg5h@$(lu-pN1Z7X7^xZDPK82>FrT%iDp(A^h>%||KX zO)meJgyoiS8&{Pp!yXE!i0i}F+Z1sOC(VsE199gNzb6(pU7cVsPDkCfHiM-+xZWK0 zkTn_H5w;FZ>wO=E^TG;A&Cg5EXL zfj_PoKyP;yfF~3Hy;~^aNd-Xf5u|uZ0nq!B832B(0O&o5=l`b_0KIn+ct!!xdqM!f zvkH)UKNL1ML#5K=srPSez1MK}{JXG+J)+((g{_yU_t{)JUQrC7_le^H{6PWGyOu-! zssf<*$<+Hb1wilfxQl&V0q_8L%?n}kTPkrnm3Yxs;v;(Ln_&;tqZ03ht$7Qe#LZj^ zK2QvxL~bj94;26M2Zuq!>EGXG@D98JQH!yalwnV*L( zM;tOAprd`M7(nJJbhNJ&0GTCpw67HanP<|`zEJ=={u~|cZwkPGO{Js#T>%)dtLbRp zDgXmEkzVkf0_1@GHEd3TN~I@pclN2R_cq$<`>=;SqTbGkbr1E9($QRz%rUN=9UP_r z=)E6BuRIEX-ro?&RRHv!Mn}t2fYe)yn17_+XHjoQ zL`H_4!%)bNc-SNAT^zCIB%t?2bhMF*0qlJy9c`2Xpm$dxfYAzo-e*(qF$#d*CvnV5 z6(AjLM8sSP{-qaEi6UEx`NL80MLblGN=%4Yw^NC`Xsd~e0hB1FqfJr(l=wLvZL$KO z#1=N$TLIG1$|L40l(~a4D{Yx4@NkZmNaKF+WR16^VN%k|O0Lc6c z17lbLkh!-7AffzzU zbw$h@DdN`@5w}G=FSbDu4~0`iPsDnKA|9v*QLkbE5ig+LeXs(g(y55~Jvol!R9bFx ze3mg~Rm4MCtpC4$0z`!)k_aKUI7@bvm5|UR)Flq=7{+lD&ge8dW)?D z?~l7rjd-XYl{hD2{gF!imA9wQQw$IY5R}h|n9fCDFo_J#vKcI-q@PASWK9N_MXUsf z3W^yMu22l1Qa*tzZGit(Ta?boWi(zTf{@wWN>dJ?|m}3kTL%Lh9YBspFyKCBbDZr#;n~P=%A(jiBW546S$5$BZ|1&b2vMBb2h&dHR;Zb>Hwu6v=kPwo-)#Vn1RhwJ6#-tRj^n1xcd9IP*cCA!prRMmqU~q47t9jta>PUJ zsFO2lRV`6ExuThMS?DxO0ZOMF1t^`|HlTF!C<0rjTve7jX;Cu)aizy|5phK2n)?AK zMPAfHZK+d9)Y<@|f?_T`qZ9)!SPa*IlZOUKbE8>7RiE|r=W&3gse0+U2-iUE{rs{_!k z02xD?qt^H2_#a$fTWpTE&}f~};gm(O!Khid6dumLjw5f1Sp=5?Sg?Eqh!@+&vloQ~ z#vgU1qORLE-p{6kaQ~=>tjM4T<4*>;Zs5Ixt)Ig9lfj`>dAZHtWUdVdWBhFfhhqH6 zVEtI&{eu~-!}ycI_Z;#KHiNsXQP_m>w;3FP@h5`^8-X7=xC>h_{s(|T=iaE>W-};f zFgP0HZ!izd`j$a=apH zengH*`t(&cNB*%__l;2xWs&1;QET#n;P_k=_#KKP+^3V~zf%G5=}jE@yVbk{8z_BC z)NDuVQWppHR$Ih{T;YBd^-wrPJQ%fBQ^b^f;14T~a^~L`HP0l2V@=fEZ!`E?5ekn) zJ!DM=&qS?z$>2*atG~-IC^(bAa|)0y{zTM#iyS+-t9i=i_!xWrLexW9m= zlCJx8#Xzd`Qq-(SfkA*KeZ^+r_o47+)I-)}@P5=f21ErPF%17%F@TlYxDESA0Su^| zm;b2%Y#)YK0{B<~7&{kd%3l=V5QcpxYFY;j6;;X3TS_UQR zsKhsl0miPC*8IBypu|l)dwi<^C~?zx0N*J9O4QE*@Vx@05}!rQso-B)SckeVY$e(l zJ%5aPs2-JY)mo=fiT9{nPHkqb>EUo&3V>-|8VA6m04On<(;!y?P@;#!k*5HugrnBH zl}a2n3w6#~xwxEx4UBtut%vGSiIQ6D6Do0j0Qe}y0G60R>yK6dlsLNtz!(Lj+D`=W23XmNiS8HBRtsb3aLlPSucU}$now77i>0oYiiAV$w5@Es~!0?3om#;xvAFkJUNKj zL3lLyYIqmU#RelO_nj=XNE_z9$Zw?%Q9t;1iNELxgmBHr{}zzz6~Fg)tzZ0ahkP%8 z*V=uZzvwrhDDd$$|FJ&4R$uPpTk8|N{AFwRoBqPbz+f*QUqqki1L7A4177jFfcpf5 zK0zN}cn*7ak;B}8kQ(vv9pEjEHYkhoiaGj4Y0j~G)O}-62zK*xiTf`Z- zQnozQ>*b{F4GKH<`S`xwfRAsSZSwK$vCX~(b@-)t-yQhg;`L4f?cK8FR_{2LcFLC9 zyi-{ERj`N;DUR^*g{qUiA!3gQ#fYBntz+p4Nq@GF??avIolorLpct|9e0+iFd>>y2 z`l)vzYrd4!7x?&w&qdzl#L7cL*X=&OEpnNUZ+PtR@imRhy~lALHirbaD|~#>;!5wC z#NwgCcc9l*KE6BgbMNwEV5v~iF~F|z@pXtByqA-1T}W8^M(>R*tq&D##Z0=%$JZMk z^xj46Y$^R=??Wt|6Dqm`JRb4!HG$`ReAfTG_i5JLDCu7Co=jOcg^GRwx)*(XcK?=- z&)eVj@frC$J{~Ckoj^AO!x#-|z%XBi(77|t@@b9Xw+c-Px>mhnck%UQWxTVM>nt8Yfd@pyK;${gcrz;BS;jj^!<}W~K9IAFcVb33i;t$N7fRAX zXBls=6gi8>lfiWnp|RIl#v33d&NALd80jqIseF{P_(Hb)M7A95EaQoLjI)e~+)`(8 zhzy2Dg$84tWjtp3oMk*LmO0CK`bam)ToXBoHEw>gX7CCy`!(e2JM?v?Lw7QZ+a=!+7)(^be6f6;g7XA%TB}P9%mW1QujK`xZSzWS;qavubpLF(C>GaanXIiS;kfF zL1*!0n{I&B#IK{?r48dU za${GT>J%~^4!)gt#VmU8k=Q2#kJk^}P&wm5e*5$KMuuj9b(|QXx z5pt|Ukk7U5L=Y*k4nmL_WzDPLD(c*KJc!;jE=RMG*P_+mkP(`sv@u^|emeFZ{%1ht zCwswQZhp?_5+y8mUVd~9#M}b$n#GsWb!$=`T3BD?@n>J1-#|ickC6wWoF((p%~s{F zX0tm-vf064r(36l(M)q*jJcn?&WN!=VBd6ujro_e!7<>iSyM)^K`}bzu%?441M~~|CY_RVtLf8humnUIlqIT+*6F3NV*p5v@~1p8TsFl)Q^CoSvO$y zb6Cep-mgJi?uEw7Y_O^{-Qbe^Nozqm8v7m1dJqR|@c!#mkpA4rK}E$X40S>7bp@MH zsPtm@lY4{st07wDPV_7HMp1B9)?@L@y-5^uD*ptzxi^bKuI9W7D^>0-MgR=PJ9F=| zzC~t2?`VJzSJE81!|9lCx*z37C$OKoZaDT@-FK*#`{Y>art1#JgmE6!KRuqE!%a`e z1fL7#=T&=S!T|Zb=;L^R+?cSd0Ogl`99Ga9+C*pWJ*ICR{?FzkCTd>s90Sgi!iXKY zuNHoWzH1fNik|K)=mnLJN@|ry%tZYgrE7pVE8m=g!keYnqavrW2xF1^r;#tCkX!k8 zC%!)vg?w$Ya}&s2DxENT?x!P}*DBA$qLTZ0 zA)7eCWHYZ%Rss9MI2QR~x8f^jNo{)IzRrIOh;@aI#?}`I6d1S`xOwik#zUy6I32?? zA@_%ZE$gutTtnS0z3@sDH1A~`AFp0`A4*Pd8GI#oyk7VgN;%$B=q6Qq;g=}odWXSx za%aj?f%jY*xk)b^z5z_U56nlYOV*9@ZlVJ$(F=p98|%Hd3Z)gYu3VeKzo>RP7*0Kx zUzg$wJv1>k!-!6H-p3AJD6&*n&{H`{FYGhfd7Y}EqOyj@n##F8^=*8C(Zh;{>I)ix z?<d`!J%DoyGXhorXD{+oKyFQ`4D1rrkgf%sogiH~}T^ zQ<(j^tMsw#kLI24Kxwr;mR)js;s09hA^KPn=78Z`GF;}y*BaeuLt)ryteJ!8BWH2m zKKTc3#Hdb$`x#a##@uNwj3UHZuVI(tvVP_PrL{LW=E_PS&eXF z_vnE9Guflb2t1ngINTK8x|Av|H#U&;UAT`;x-$P)B)t;d)2u=UNzJ*>aFDJtE+Ogj z(9tGclm9MB4}&h6<;Dg8q>ItbybZ>qB)uII(7X4CRcH=5D7;`4fpSKe6#PoYpbw-OcS$cR*VF{#ci zqzGr_I&?DcJP{wj;5jUkdFLBHC4<9Y)CqZ)7rfS|7+jfmCz@)N8xZUAuCCx8f6^<5 z!)|#$7X?S<0T}eWYed1Q+-jh3ttdDv*)s3C3SP`g4GUl1^`hXae1qI>5QSlt6A^dv zZWM)_%0fi7yqhY-5LaF}7KNKDIEe1bpTjlsZmHlfc`6s6+j+mJ;6UV7_LIS_6*P5T z<+E6m^L|;u9u!obUx>nOqTsFMpTy3)J@0GOjFL9EL)c)f2$*?yib6SN)kSc-=^uk^ zD!%~Gp2L`*?0g&F&UNhnUB*jkvxcV7#5Lk>Vp%nWgXaLqCpZiz{-5#SGCEzlw1ITzI zzsfovnW`0ieOi9C^uoP**7R%nHKKqY1=cH@auJmLqKvK5p%o|vjAdw6;YS29^1}u9 zqENXA(&uA{8}|G*eWib;U>LJE|eAZrcn zIWR$+$rY#$vJje#x^SOO;L>&h!>hdBATyEUfg?Dj|44k`nB(BV032Elq(V@v8Jwc$ z0$u>PlX3!Q9S`#(qif|P`r0tpkZ3#Lg8;82Q7s7;Zv|_8fgYqmHlokNsCM-sh>-f@ zvcHtBZ(nnm>hIICzefW;0!jAw8QI^f09=8T)!$XilYxo;G9&uC z6CCbB;z#rs-iZEQPEOAlu`oD^{yqcvw}OcMMOa3EcarG$hPgk9*xz>mzeS>25~%(n zP*lHK57Mh-Co$yc=(B*1Mdgts(5g3%0)B$*_9_7Sb{a+c@+q?0SA+6$B-!oLWVfFL z@F-GNxA$YWPce%B0zHB(4DI$7U}9{U5#9bXIDCM_Pgb|jCZ|&kvkmBteVTI4C?BZjz?9FAKht0c zefxM!H>vMkj!w4v0utXxn#Dtqez&8O%gkZ}K>%qM4@3G+N9VO*a5I1%1bGh9f92@p zT2zR94pKuMz8-~2en&lOUvlilMg9PQi;!x1u~6tAIEusx0l=w9jhy*(*nQuCeEoID zSO!xWEWvOYNOBKHw*jJk@*}c@cePODT5Zgv4R$5hIJ*>h`tH96n??? z@q?_1d<3K#r7EPRb5FoM61369H>x$qjb_t!pic;t-vYe})B(E9)1=X!1E^OT*5j1H zS=NqvKL67KBaX-4gG2^@?3hGT4eLh|l>z3CZw*qAHIXSmE<)*iHj{qr;%IC9um1WZ zBTq1X7KNt-1^%k-89AsqOnQfY6h=b2*lTuURxbLj#nL5TYa0u$4yPk2GG`t zAvsD8iPkEMr`bhq_8-s)hxaEGDi*@cQI3i-0oTK5sBP|RU|MvGus;#Ol`LlwZ= zb&r}7C!?9FXhibQ z!Z7G}%0Fg$2mr28{*Lhgf34@e51uCg_z6-Cw@mu|5_|!`Qv|tn(jSmu39OfoAkX}S}j|YAvk{0+K{D2>aRt_@gQ!x)pM&AZ}8whSi z3bH2h36LjHdJHM@EedZS^BM~|CxAaPUmeb0A(bJ%oyh4R`4oMMtVGo%pt%T1>jDkI@*>K0$2X;7a?MQWELR_5zQpk_?<0coDuMD_N$6xB`T)ppA>lmT6n6Rm%=ia* zh5mVN9G;Pc{>Oq`*Z7^y{X~KCTXEOs`C&0Vp7Amq2jFEhk5OJ0*Jsnq>cE+g(zkvLLh0p_D*`m^vD~eoV)<9HIGk z*f}Alkg%UvF^?E0mX^gA!1WxDj-uMe4sck)L!RT& zegDp=x_`qg)b1=XIDKTz&Y7%PcoHUzV`s}}AX-T8b?jVB7TW$x;FgZ7ON_76Ev}BT z#iHY|qB*XUJHGw5b1Ykw-WKr(OhC&pQdUKlS;~#>ZV{&oh5SZtuqQx7-<(K zI8hiS3tIC7uMUP{ph7lOKDrvtI{;SA{7>@!d@UT~HgTz2Ms0+XTSr%~hK@^RK zfL@2{%aMYth%^BC2&LDNBAqBSBc3)OrIw;l2aUY?J6_HDT9T0p}Qp6!{W`C^BKBWe#koo}fSjnJyr0NC7&*{m|0T-lCS+N^XFfK^Da3 z<4_Q7K(coq&k9n0yO2nJ5qrhm$BCdio|Izu@iD74e#1Ehp&;50f=dKDScoB`1%j{@ zqwGt~5vPFHBS3!%l3yT2ccSnVGLNuu6AI=CP$C`3InKrots0KyxW`;|GDwyJos8;< zNYO47>XF%pg%}FkklBK?oKtieWr{PbV~ZJm7|2Q=aS0aI$;b^50wTz6S)kq%@WVYO2`o7ESXZ&H)ZK;J_3>qtRXM2-bw6hbJ{a)uH%a%s1+(IQiv z6b@A;a1KY42sBS|NhUK4jU5;cM_9h|nLmI(0>^4+xM(UwqS?v_xQ^@cFGsG^@ zxH~}dGbCZxhmm;@N!XQbTw0C+dfTqAqv{nT+pI4MnerP%wpo7!!S_hQtRoSOi;?gV zW_=w^;9B6R?=T-Y4LZ=QGe9vNNtm?-nFbbU*5i=jkHiVHvav(sw{6x@WI(fC1Cp!R zhGu;L8UCSWVb*Vu`3gyx^%FGJHGVsxg)(biF&;x83A0ur!=F90&H9-T8Kn(uv(}CtZ{%#V z-VcKNkc3%ZLgq!$LR-%1KY@O#Z2?dHa#NV}6V!f;Bur|+UOJL6X$3MqBr)~b(9o`< zGWVE0r-Ov%jG?-L^fc#UWEQayLtzs#{YYZ!2Zhup*x2^aQ&Dv?X*uBY(EX0}4s0qt2R)hGRkN z78w)%Co)(Ja&4Zbzo6Unviw6Nvwj{fK6u?MbZ!Mx)qbktp8E7+FWKcCGm}R3mqi5mR zQJT#UPmQ5mmUv$tSWs-4$biK-W-u!=*2W+f!K}g{Fg_($+Dye*u=#k~V0Qh4?D~vl z_OiPonq}aLw!!Sild>C&T?NMzZ*fe7yG$w8CykcfpK1zCr=^v%M{7DssAW~QIBGc~ zsLizL%lqetk4uDVedHi)+PmFvuqJ4W8!0KfFx))nJzV*#IDQxw;C zHkjQb_wy_^7YX|WJ$g49go0WP^a$@pgE_$}n+FCpov%IRSRGS>&1Rm8oBEDX=QKdo zeX1}5(rc8W7f3~CnORO~Gu(HOqG&!lyLq`#aZYwSO{>dpf*nY9gVrKx8e3umJ4gFA zdZ1|`rcq2PeI7M!@}V=rAgqH)Jd0rY=E3}=3Ujk8%9%VJS`PIOMjFGveir2 zjfI=rLz1-Zn~il3RPzSX!0# znn|O}F+c}Y!JM)ew(Sl~8%B6GhLL7Wc|a$Jf0@i;k=TtA%R(B_u%3Na$fv zTR#6=D2WcjWk6=}Ek9XCNGQx9p5~OH2+kRhfGsWqN+>F6_ap!{?AE`fC+!1~OL18x zv-p;u|5ZKrBtQw$#70Bw;)O$wvEXI4$Yur*Mfs8B3lzCi!!4*CnHCEaow{OYB#!y$ z=VWB}MuJna0sR&zFO=rcHcr6hAAHJzqa80>L^jFGHj(Y(F0kBwg#~MR86D&X>yyUX1d>^A#x5ImXiaBJeUm4`f*35(0`ODP*peuFGq_kyDUBqe9uN&f#lXMBP;P? zc_Wfb>pIW5;5?^9Q67eSuxV-RK83N9;IH~>Xq)wPFDXH`aA>pAC{9s8#~@{OMo)vo zuxz#L6&aJJcMPhUm0d;l@*~-G@j}N2XI@@J+LOoR0{?egI51G0v1cN&)4bk|1aHH) z{OAOkvOq%s=K^$SHR;aCXP7q(CPhg+>Z3hjOI{`;$?zkMh$1tikXW6bX^J*igeu37 zX$DI1ymA(L&mwS+0 z+F?+zVh7pfq6Mllsw@I1KBlhNK+2D4U0i86TSH1FyJwMz^V%U;XBGsVAd{}8K|=s9 zidNan`o}d=5t9w3DJh$D|5R%_?+_wBDID6h z(}C@dGvE(tOv0g!*>HDz;YsHnarpr871U+f5rXi!0N_PP7(SOAK9(*Mq+Pu5$zi5a zHj>|LdcPn{@Iv-O)g;MHf+X!Va`^t6V&yYX$uT`B^10>^G1*|6lCnwnPqpUo4Iz4I z4_$i!*zP!oZ%AVj4z&v#?rtxqV7NPuht;4jgZ8@(A1mHO!UzqM!^hIQNSJ-R@Y!Uh zQVyK_W>cr&nc#)&hpI`E&ycdjf(oDirdau`RdP%ZihO=LL`*iArlf4r{Zp+ud_#!% zHDzIR(SrarrcL1=?iUQG$HniP6cCLkHpM&ji#oh$daU zu=U_OsfKt)%jcF^TqU??uGtN;R!ZqDLL@KJD5Pp6^%;ZASR`)QHX?DqcCu6$B|OMO;+~K=llsv9q~~TZ zo1PfgKqjsi*@=q)6N4-h15$Qk^kL#GR#Ti_uhLk^VxkW+aj>!zhm?t%Kec&L`ckhx zJN>_|UkrU7sy{bUOiv;0LQock#CQGMLgIBWy|BPhd8=i;h9r04EvAri+cf~-T3`jC!CIvq)U=szlD`w;W=AttU^>O=fiq}!10 zL3#@51tj%RKKIZ3jv-WiK118DkiH=g-~~tw$?8*y{J-*3MiKSNre~Dnfrq}WKE(bJ zu4vUEW@|L4nck` z(q<&KJs;@;q`xD5hlG_v+@haGTiTzSaJ>bI=aZ*xj2GtLK^hC%@+|s~fPIX_xslBm zMe$L$!r3NU4l5lM#5G@7RO3QM3hF{FEKo@9HdEWtAMt$Zj{Z zUX?k9ik7_9hwCBNz-dS`6=+}c?dyy7RgFLIIq;+WNcEHb;76_WC(B}byp+9W*?7#p z@^S{0GVtp}oC)9N=i%9fIJd)F^{T2FeamMY)W2~?e_zjxzEpqD>Qw*6)!K|z8`kyC zSiZJ*%Z!6p&8Y8NxoP$K4UHT6dZ+jGuJ7$%-an&v%RnD5{{DeYD_3vm>f3NgZ_hyg zjKs#}eQTOGtxqLatzLg{*V;|}sd#<3J*4EUUf(lg`Nq{VAQ}HCbp@oa>)8ZpYyU6F zUEa5DMq_)THIWL*>kM{fM(g^XwVPJl@h4QqQ= zEnmI9f5yQ*Jt^|7sZIq_{%U_ss-~LYbb!;>Z&=?uy?6PF)zfRLs{+$mU4`mFRWo1- zil4D=c@IqW|GOIfTl=#u@xMRp|983X!Kr%I^{?)q5$oN&x~F$Wys4upQJ>h;p#Sf8 zmCF2I?k;?AVEOu<-hS+1)U>VY;c|!hl)`_0sanN=DQu8}U!sU74y^0hux{Ok^|Cs( zviG3no7N7b2DWbO?FWV+0cT&idi?+jxSxs8U^hsiPrwjV$po&P>fO@QyK!LkhV^Vn zS(sF*o^^o$ijWnLG;`uNw4jLlp75`M-gPqHmqPGZ-+xeVpUoBF4ZYa7dQefuBDAm& z#7tc?MQk*F@6b)N$kbgUjPd2B=`yyJo8w%?=BTMCR2QS72oL3TJ=5ZNL$ny>8sl`B z(~X}US>;5n@w#4adJL-^*~0`QWJkF`>Z%6aRF`q_k>wyXjSuv403|Nt{3EMOv!uwZ z1XXjnIlao93cxkniU0U-yrb!+;RT^-TzXWMfL;=ii{hZ?8M;n3#(781`X6vP)8=yS z|A@<3HkWh$M_kUuN`j7#GcJQc46k>FOP5`JV=M7e<352a13bJH|FN@tXvIvIfeO>~ znj=A7R&M5$o0hB6oQ4ucWaJ#!uG}m`X>f(w zR29e?+c4$@hE-+e_#kAmneWm$f;Hwuk{c!E=0xKV2(6f5PAp@iBB2#V&s**)hgQ^4 z=rP`$fUMpIcKcVA5AnFaVc?~Y!Z;;W@GvlKHAcWw$D0YCIj+5;0-o@(QEn!TvyPw( zZlDWR8pCz7$W?@FHC^0Tqk};)t13pCg~mJdWN(qz%zyM6Z9F4v{cGs}!Gj^sRX8DAVh z3;A@j3fB@d&-gPZqPIv4jp-U+#7{9a^O|E|->ON**7B5*JI~zPSc5_3M9Xh5)|Q*O zd!bZZWm?41(a}b(ZsuYJ=fFxv5l7$1tMUTU&HOSm&(&a$vwyVowq0;CcpJWRT*e89 z6Euu(od>zn{&$)HON}#4Qo3eIuiUjwzsdGLyMi+_;4)CbE|t2Be0?H<0JJnbR zDO-&<$GArBEt-$9+58(?|?%0|u{=mCS4qz*umsG~jV#jdkT_vr#mUHq14i z(5evJrW-qtqL6j-;BzjcP%lCp6*J7(mrM_#Ac2X<>M}~C+HjcN)Gika|L>{EaQ$D< zY^2m|^#6OBjiP4bT}CIy6N}Q5j5S$fj$wr5%nIQb+2cFbh3J9`<4`#w|8$%yT}F{w zl9FpgoR*9IoQ_9WJP|m_!9fhgyca7yt83*;S2vlnh zCo~}QDK5~L&ojr^v6mAXQp_M+9PMES>NgTm)6J_4;FY4kSd73j*JZ5K5pBjI&~Rq9 zgMn_WU|-v49Q=v|Ot-8Y8VcLYhqgNQ5iX+^%>c<(vZBoChOk2NKwq^8#a+uMT<%}e` z#^+AXimApKhnF)T>BblMo?}d=*=o4J*xLLnRc3*HxLHn}@~EQ=Kdd&$|DJ|3nnf5! z?lj?nkey#uUS2hb=vc8w9VJLMlf*rg;vPXUx|r@axb5v?x9W6a)%oL*LT{g|M0DvA zEM892XS^@=rMiJKG|3~FZ~Xp9y3Gvi4f4?eUyYeR&74wATfj%I!vDcQ4SWw1)WVuw z;lfOC`7i^EVeSq_X){!1&V;!*7;;va^l#&^DqgBwMuD#O9pgvA;jxzju~@CKnC}e+ z80o4iQ&x6rhN+J?y_igxrLf~}ySEdD>1MGPhDP5? zjUONiI}P~XIOC@fBo}{}|4&EC#s5;hTrB=hcJ@Q;CZ}L0>Oi>vHB9A%{ePniKSAve z!cj_$`?%*UHsyMDG?}R3~PnzLy!<+e~7ci#4iBgc=wH9tct8dvL<5Z1Z@9dH(p1%yZ09 z(mX$E|F(H9HEFmKE^B0Id?+^5{c1fEu9 zjvtSK#ikOlg*9UwY=bS#65*|5r^8-*(TQlUA90}Jq#ZVBK0ZFkUibbZdtqF~Uh=ge z_JT#Q9{w7&PIHR!8x4C{ zXJb6ILc<*e+%n-EfZol$>v2CqYff~fn&RW)YwXWUV z9h#7>)i)-o5=1w)rV?GPsd(@5m0I7H)v47R*QR;2b}X!KYmKGaJ7Y~+tYL0bhn8q< zkNeRw(bSfRSEniGbv4apSJFUhSE{?CHJR$@Os2ZxP0%K(@e*Iy6!X_;v983T#<38)>Zos^ zy;iIqNNwm_+1n>=;jgx@HG)xNi@!6O5S@1SyuKsR+yo0G>*Gn$MOe3EZd()H z;%jS!a>By?D2sj=J1w(0Uf&Kvt+lnWalRPYSZjQNziFdemF&bQHl@1ip%*x0#()l^e5osew#`~|G8S)XOE;(aS}{zm80IAqoMzk9 z*4EutA5S%Qb~LxnRa}HcVEutDsg;}7t=p<4mozuF#kEANaXx%pYg-sgpixG>MXk-P zsroMA1z^=7yVuy&gg6%w$7aM`s6S zPfe{Dt%e%EbSeBU&Y~o2mF`g5#*J;Ajq_7*|JH>~>DtD&`53KK(|(OjO);1u(b?75 zo=h~;anPq$G04g`YEm@U$C@y6lS%qQbDVZX&(WfB&=+n|QPz{+iV)n@a^ZOBd z>^YwpSU#|+U(9?B;Rw+P=84A^qit(k1AB<@C$mON`g})sTU)BDv$caRFCrI49V*A0 z76`35675~^N;Pl|-OZfuP3>LD#c5EDW@CLL;%{?G_=nce9BXaT(l>DXdj|#(kor@H zA-=$71HCeAwKjIewT3Rtf%&v}!`xWA#sUX7jwsV2$F!x|jy#-wbP_xgN-bZxvM)tr zr&SS?MTDhx1WtS6BB=E(ALz|8Ow)pN3;I@9yje^y6$P6Syy7(wA~W*h*P3G-Y~dmP zu%_Z^qIW>+$4aE`RI5AgX>qaEg|Oh@pwZnCYl=6wbuPl#_%Sxs7#sVc8t#`5Ab9t# zWXOWUv9?*`Y(loPyQYnn;d0Y}9xiH)C0kN8wJaorYB9`THTh-quCGo5nW{`I$b2dx$h75p1su3Sxd6;{0Nw#*9NQXh{ks*g9NlCAAch&UQ1X21_S z#k!hh;N$?sFgfHkFvM1P0w-)G{14tPslxU(Vqc^7wU#SLqOmQJrE_|uZOuCyllAs& zQ@UfGcc)^l^>f8OBh}a)$8)7jA2QW;O)AmZ9dFD`Pvw;LZSki1*y8l^Ov^USjaSnR zJGq`VHrHUoz_l}gwNsd&rrN%8hX9knALKP)UxW5FWM9MfHDX_*_O(_^HeI|Vh9u%G7 z+e|o7V~qU+Cct2)_E*b+LJUg8vC{e37F`wth6Pla9dmhbLwho$A9vwF)$+c~1Vx;K z&uv;ikcmxd%0lV%2+9Dd6zuG3ii^FUy^o_|u{ok(#Hv(R3-_E&vANh-#<1%Y)xpgE zDBjf7RG&=2ZR^!gOB&nu{zzJIeOFh!bHCPhxznTo?i>-yFbV8AB*T;@o-oVsM<;W<}7|xPd*ofVq+%mN^3dfn>)smKJ?|{TkroF4JsU6OW@m02HXshp- zpK5Gr!m4kF)WH^y%8^`kBvY{# zc`Qh8cjZilpwAwi3q9mfKAU{<40lj4b?v$;8Q;NV_d9eJ8+Lg|6a1bYN9xgIR+Y)fK9usN%b zrO!Wd7s~j_L)c-fR}QQ~JVKan#3ovK0gofQA5z+zu-2sDb{%SdiZHx(O={z+<^8>4 zapaQhN2lyD!`85IuDxI?=Jsq;ZY-ASxIAvwh;Rar6|n_u(mT(l^~+bR?G;;0L?0MZ z9^k}YSus`|TNd#!6vJ65Yt9LiiV;p>yH}s;=x%S|7L(frZFLVi!QH*u)MAwp?$=~5 z@J;@JT@KpUEX!vOc9?Q42x_g3GOW^pn-Fy6RW9~T{#wk427fH6!K>lrwoi+FpuLX~ zx;A#UcXf7vo76FLkls@*7GEsRK}3tTuFkH^7C@OqbR2g%5GXXUleOJ%(1Q0)>YQD+I7v>}p7ID#aJJVR26p zP9^ceht?~{SPf?rY{@$2lvVBq4=7VSj6C^ z2rpa;cvj(Yh(}0q3=t=8aqiB#=aA`YYX^dny=KLl8xuH3!4+F^`q;F-fAzuZdsmiY zt?W~9Gv*y4Nh-CRuU@6r!o6U5%|28Lff)LR#Udw`C)}iw*BUHSY1R9-WF~NWxH7Xn z(aoK~-1=6W>o5v6aDj&I1a9KsSR>E5v}aemb)h^krMf`hz;KgHw&Oq!LnM>&xf)LT zXv0$gIHYg?REwKnnS&;*hePy2F-_(AFK(@HcrzOzq58Vj*ei2g!Z0+!)8&mdHMTs% zcQ&Wsg`HS#70R$fCrorF;D)jEhA%UY8~Zlk$UU&Sw;!6cEbm*{EZ!GF$1^u+VBxga zwB!C2?)Y_X>|L*6 z0TM^ov;)a8l%rsWcu3CjoPjNLbsmp#NXGJorGs~I*aLV?V^bm_{0)ud6v)i`PTWvx zO)gHgw9ai2JmmbayWZWA=Hk2hyY?;6X#jA{mT$#&O+VEF1VLk{jgo+Y*+eaW=^cWF@p}? zhs%QkRy1|m7BRDaZZgo_(TrX*fVXxEdu1JugK~c=?#0m9SWvk@irIsClfH||8^iuo z!(yIA+8Sdx@7l{ibDZZ~#-&yS{eOb3>~?YYmAj3mL_6-Y zh|_a5=XG}XGh0vIOr(~OjXrfq`hdIy(?Y~_wC_rz<7tE7{y5ir#H$+aQH8LuWQQ(@ z)gL}nj}x^xfvCgcP?H6u$pnpka10Ki@!JP2L1Q0eB15c+!#1rcNNUxJ%54Z2mwK$> z42>b^DdL;fn(WBjZ)}A(H#fI7wsNUWbk%2_j~PkQcX?WX@E5mB&^2swMQ~M) ztpXAbknk&3iu1eJLpOka@L8$`4#;~ssx`Yxk5JKWFty)4dI|l+Lx@E@SqXtGJS8>KWg=eNgtVv7+dG}UTt7Z*x1i&O-)lH-$Jj@@{@Wp2j{#Nc2 z?OW=*nK)qIS%B-c5O1KJg z+aRvUMwO42rc0fJVrc_>VjVZSsL~X<*0xG2ij;021;1>O(q0;;q7rG8-1ORd2kjsw zyHk4`KBZ+FCMlB<`9`M#lZ%pYK3G0{lA9xhO|eeMwqmUpvftB@w@k6Dn9y9iRBGj; zw0VCQoL@A6==!Glg1y zsqXiB^>B4FW`3wy*LrDmxwafwS0!SQC^YpX$w^a*-vBC`FlD@Un6$b{4!HxuDW&Tu zrc5cVEH*XUXib3yqGu*Ie|U&Yr()c*FZ}$A4(xr+S zvpld4F&O34PNqpvjq_W3W+{!2Z6B&-4Y%DUr;xD-hYM9zfzWZq=wR5G@$r&DgW~qE zM4y7VJuZg)c6YFOV>^-;7T&+v;W-hGBn_Uy{eQLb- z*ur>kop?WHh9b~=_S{(u7fw5MR_}15=9qkm!j(pETWQENd-1#(cILhJLOt$cXWu28 zIc?FjgxSsB!g0c_2TYTZEFasRt{Bg9yFg8Sl&RKKhSt4=iUwuT37V}Jy8VD~wjw7s zo(@oV<_o%HbmN$eKqQ~Wk_*dvxG%Y2wp=O#}HOqrrhgaQ3D zZ}QfO7VRg@ZU&Q#lj~5`jk`|TZJ$Z?_dn<_5~>{6D9T2Zjnzg_QF5v{ZtU18ql?B& zVim3GU#3Ao`EDJ&n}?(vC2%w3N=*pHm|oJYP!ka@(YA=|er?e7ThXRGavSHCtdy0e z4IHj;rP~`@p%KFhTE*^nptK^M!hW62B{k>Q5sY$mGg_@#w`!FjB`?tcaP&gzZ`Hwk zP5KNN(gn}?71+E74Dtf+MSfo|>E|!}etZ4^FFDd*4D=U+oT@-guc%n+3~lnL&s3-tCrC+S zC`ehYm8akaA|Y{jFkDp;j-Pzd#e61+z}IT{C?bXK{^YW^BwR z@^g%;q-q6K(v9|o%0?Ug3sn)uTgR8Ox(|CV+hV40e7SIXX0*=Zj1ToQu5ij!Lo0`? zcv21s*bx=$&(uSyHhK@N;kyyFxWvlQ>XY`|9n>jRxcMZOQ%nJAa7B85UoVAq4c^vZ{vziHgR?9Xq(==ZMPki1MTS(Mga0bnx+kB2(g~Pm%rQDVRK6RlIjU;CSkd)J}ag7sk5jweRINx zr2fHXT$7|b4Yxfs@mMfxp&ov7I)jArR4qy;ca&p327YOxV?e{km^LzDlQL(moHaxB zC8hQFyIuUPZ`XKcTX0I6v>F9yHIxwBCQ)j9nQ7^qxJ*_6y`w%MO;!LMR!B&b6+ox5 z64F75xF%9jF>HLDM3jeT>eQ0MnOUeB3N^~%dALfq`ELnI8ET4csIeN-^mW^liPu5EUT}{31`LQ$BY~^c7o}HP4yCtn@~|=xXKqE>@-2uU{GYoC5_?bc{ zR;g~vn{sLjEdttv;zY*wPnJ~w!7L-1Lp)p-*Wt(>~9Q98&hW@&SDlvG!3NUvA5O zJFMj9?BPy>9)Nbc4Z;8NUWMcv7WAmLO?x#IjMs=@^P`b&H&3bxTQU3S^wkVRJLHzI zfnkmeOjai!6*t;xY@Ddh!)eTEU_~XB`KdaflyfC#*DPEx<;-bw7SGa5M%|6|>{2p~ zl+w)h7L*}Qr7f1*e8$acN`@*sHDevBe$r4F!W7st^$XEI#DEaV(=R&mtgcIkTt~TT z?@v8j!Uly2D^S}j)_HH~CDi6rvvlRFidPcZs%q3&t&!@~hZ&3K=oDZvhXMUPq4LV9 z!?Y3`CZ&lq%_E0~r(L5i@Z`i5)d!%t$wrqH+}}O2aGj>9w7Xy273R((yh{MmW9VP|JD+T)Yun8khs#JMQnAPk*h(BOKvO4=ag?W;Vxph;h5YMQoK^C zmMd$U$=5c%K`6uqSLJyI&6g0G2ziNCOqDeyh)sCPiQ{eYELzBs8j{v zf+8#oCg=s4p)-XiRY?tm>5VjbwjDgT4?5ai>S&#o$?6QXFA|P`$;p}Sn4(=o?LV-) zufzQ(STE%CR-@f~B25iG)nQZw?!n^rhXSXObGMD z0!OaOeQ z`*I&$IgAA`M^<=-NLin`-g@ZR5pG~foSU-~Xi`FJ!4P^?tbr|&iSCwB+Eke`xN;2PZb;)ZbEu*lB=2lsWXKIDUCu(Vh$W= zE?nj|2Zp*qgq=TyF{0GzRjdvuisQnWh~}r#Jm}0n^HGZkZPj%xDUHUhk?X2^{aq>b z&2q--*-)P^nkQKmw)2LrO6%NLVt=Q!dZ9bMRxkMj*nxg z^ui5K%|2YtFPvpPlJ>lG(9|k@sZte=F80muP-&!bo}*lrY)wGwW(*~5)8~}FBBeSF zuNav)*gHaJf+yOtVIKXt0&2N6>1tb(Hd3GL`#QSD@_^e zb|30SO;0trlK_6no!CN9sC8XZxQdwT0FJbopyp8FV?Xw2Nw}6Pfu*T!I6NHh=04g` zPWFAtYGu2Z!z%1aEozt>5W+KYQcO!vXQz6T_0i7z=tv%FtSRI445Oyv;n^ZJ2&;BV zfgM;bce4@g!P^=~u~kfc4i@R8T!q^&D%aDKDI=ja2 z-m$ur3MKDHl!YC5A{xnqM1^*c$n8hDhg#fRMrJ!;-~^hiDU)MJI`4- zu3AsRxytE|nkp)ZP6X|;9hfe+dwnk3s>7X9vc27*PHA96l^toQv`rt^qq)7=#L=)| zv>h?k62R1xwkUE`Wm9n~;rJ zMQLd#F^gQsB2BYBcjnSk&p~)bt)4LX&_tsBq@JJg<7t1lb(`-?RnqIG3Dc$BDPcKS%;xtv)4 zQc@hw&Q(<>C{eCS`gW6?t+*B)J}crQV>S2a@3-cBi(qftt_ol@3J*q#;pAB$gE6|VejgI7s)PBnGoIm<$g zLOw$h_xr~lo!g|2+jhSzO+W3HH?B{2>m+S}nyQcywvf3%X+ikZM5&f{{+P4E5AWy? z2ZUK)6lQ&B7e4eU4UE0Q!2Q<-x1JHQF>8blF@-vnP@7t+{Z7-%YPn*|0UbA4=$oEb zUb{z*b<$GfOgQuOXV1{yhR=kl2U2GwHLA8JD@yX!G20P&%~{RZ*Z%c$C-B?=X=`28 za^@&Xl&=b|Sz2u!rp2hsb}3%4PwB`RQ;tDl78!uJG%L@b77Ny0tCaH|kL%x+KgadXs{8}fX3^et9LOCVfwAWLq zC=-`S&6i3tAx-MO^!!mmdSrOS(ftqAKR($ua9Ts~&3u%d)3Aar3g3xQs@+&;468&@ z_>^qXkxqT=+oW4Hxa#Ywh_)bYqHPL;N;|6HPS?s?pM4fyqTBON0VFL)jVQKrvVN-R zD~fx`g(^z2$1`QYKh4w-|Ed13pf&6cOqTLy0^rg_qOyDE7$E1MmUEq zrri`VRg4K&>m%oS#Rn>SZwNt-4Zj-LF4gWeU#$CaX>INSQi*_q4P-`87&Y zmoVRb{_{Xsu_~e~4`qHx@`}g4inae8%9Gg@>Twd-Vr z7*t6ZQb|}UC1E%vgF>}SYR{$xz0X8HQK|Esnr{U@B6=Eq>`1-QCb18gxZSU{Q%2rV z>XoG=uA>GhWToh42v+fIU^XQM$`>X%;UJRGk?9RMQh&LF7&SasY0rLZKzA8vPmWnz zuvf}x$v-C4Bd8Gdkb#15YGTocp~Se;wTXS{#L^<{M4a|qPs`aEXS-cqmxdvf`d%p% zGK7VBUP_+p6kIYW^hkaTI^ zdG@?%xTv)3w1))3Lo=$&!`T71B5+fa%27pnVG8|aB0rMT#mdT(VZo_(KFhs3-JU^6 z97->B9@=^#Ci%rex-C)btsv_NVluG5paXOt5CUUHaH!wio_Y1DO_i9UjLh6Xz;sY9cR>P&QW zIyR!Nh$G^DwOw33p>l%KnVbbC=W4bE<(~^onK`PQQkF^Xfd@a#xR*j`nBifLq^Bw8 zDNGd=o*=LxD4b`6W$$)CwQ4PMhwr3zP4ifhJ?&e9qq05kAf9 zH&WeFzAsDqzFPe!qo_sL813e80#o(F-h!j^1=c{r10}9rmPv`=FLaI~@vzAJnxJ^` z!jw}_zE-H~FpcDiML{sEq~xf0cRS);v|w(0=-lbEX6hX%@p1lD`tH=Xe?@+e|NRWO z`^3WU`bC1YrA-<&uJZ{9`b*8SrJ{Cb#cQ>8m!8^G~=@L%jN#~CIizuMPg056lafh|HDrn z`CILi4Mk0IS7fYAzu3a{pKdUFyG}Lx&r3W}iUH1)w=CZa} zSzSr1^MMunj7GzH?i)J)*SS~Io4@vj&*V>E^{(eW8sy2^{I~j&CVTtDNS8!5*t_nN zzw{ux-u?D<+T<@?wsqrQ*OVUQ)U(e?-mI(iplLn(rY=6q60VviuIwURxl=cU=Fa`p zge%Lv>@pARnL7Z=RVm!Th(*lrk?vY&b|K(N)WWE=e}() z42flVBxvj0Cmpp-Ug|1cA26%?37B^E>^sym$LpCp)-!jmXFj~1xm!JRk9uaSJ;`5s z&@*Y!ReI3defQSVW_@BawGZnr%>1S^XYz6Gu%BzD`g)1v{%2{uMSter`m1KDfA?dy zKC78>dkbdkvzn=Xy(apf-T$%v?0)ORnyG#r6#dWa8_Ck_Endx3pX_r>W?tmXhq!iO zW-G&Hst-qFZ~apm7S8n?+X>?nHDM2N-2{;cec_A{O$#*Phw zWnx;9KJRAKeKpWpNlX>W+Of&IW41Cjv;ETajU@9oO+pJN?U=9*ru`xO3{#rEQPsla z8k_9XPH7sLtd6G1Q|qOS)|(iu)u$B(K}TcXAh0pa8b#srxQF%N`)fThqrnP>Nv!xP|SI33z& z?#$ghxCq+k@l3u9UJS2**TS{%7I-JT7usj<%%6wh8i+9&YL z-&*(^%&__>c?{a8@yy&3wuAP`JCk>ZeV~1k&g4hIA#fNR1INS3a0WaLo&nE>7r=|* zm2eHb8Qu>60yn^az$f5ya65bhz7Ic!U%+qRkMLKRq3M&QHybvCZD1UBgMDCscr+}5 z$HC*_L^uV`hI8Q}crLsMUJ6&kKf+t!pW%J*LHHPa3T}h1!nffE@Kg8|{1*NMt;4bW zX$YIZLts1D8TNz)a3DMumch|*96Sk5ht;qKo(0c`E8!LJI(QSj4c-GEfDgkh@LBjW zd>y_AcfmdIYxn~^2-7ufwtR}grm!_U40eURVLvz+7Q+#+98Q3zz*%q(TnLxI3*jnw zHM{}-3El-CfRDhZ;7jlgxD$Q`zlQ&THt<+JL}4@77IuNX;Q)9n91f3%C&C$U4qOb+ zhnK+B@J4t${43l9x4`G&tMFa;G29Ekg9l+|!!VsqU@I7hJzyam3`^l?cmkXPtKb=M z30w}Zgg3$a;NRgR@Co=VdvIWw;am8~z4!v^=(O zLU=8_18#!P!MEWaSPP?4!&tb7!aR6191Tx_^Widh4ZIyb0bho@;rB38i+u~PCF}+V z!V&O9csg7PuY|Y22jEut8vF!)2Q##gbmasK;2+=#@Kks&6t00A;1<}RTj*aW zcmx~_Z?v$SOzD+DtHdO4BiDFg#Uv3;IFWW z)X>%r4}J|Dw8=enuf_K9w z;STsQjP(xh?+Z)ecsLtg4ey4Jz;9u!5B|WBa59_=Z-9S;Pr@DWWB4shKO*$E7c7P2 z;cR#oTm^50Ps8`&SMVTgoFDq%0UiNI!ilg3UI?#+cfd{XIrui*1Jet_aB^XHI0zmG zPl9vcdGIQDE8GmX!Cf#~7>3gk>Wq=Aza?-EY|%HAPlR*e61WPkgAc=J;T!N5*h+20 z+DR99G#m|2f%D-qcn!QCJ_cWhyW#gRvws-QI5-Vn4{wK$!MEXV_zP?_AoQm_90beY zDR2qA1l|fa!0qrocmOs&GW7pYs54wHf5yO*;6ivcTn9J79qgudIv zZEzPn0Mm{Q{qF$tURPaPpvDHsaEwm+m^wf#<+$;QjD1_&VGTe}|3ALVvnIJ<#s_ErSza z6+8!C25*MnZBFl$s8P8=4%Vps`h!o~1n_(ymT zd=$O}{{{EKUtyEcVYr9Ed{_ka5-?Z4XTU{pCAG7#kD%*B17I!=WCK zbm7f~=fkVvU*RKg2iymLf=$PU{&a$UVJRFBXT!7LDtIT{2w#Nn!>`~$*tk3luLC>+ z4uO+lHM|gB3-5rN;B)X}_%&>Bd>BqE*c}dn`UbR>GNZF}w!e0w0Di zz};{^%sL?qrwc5AdU!ER4?G<%g;&DAz=z>0a4-B1%$X4S7l#F~7@h)8hs)uu@ILq~ zd=j+yOs;Kfng3g#NdJec=!|5iWuk!W-ee@Ok(K z{0cUl68hf)_JYU2F>ng3fmgsA;YRp0d;@+8e}GM=hT(O91K=U&FMSp?|qBAC|(Ia0R>;-UYYAZ(%Si^zTsE2ObT} z;c4(}cr9EHx5M{ggV~|KEnp`&0G7guZ~?p+-UT0nufR{>ewcA;7)~?T3myfh!o~1L z_yBwY9#Iwgb0VyPYv4xs7W@`wRfqSrf?Z(=tbkSUe0U|?2w#97z`WB!e~*GA;2L-v zd=NegpM=lBm*H#h9rz*q88$dQ46g}{!>+IwEQEvLP&fge3}?X8;F)k0yb7*?H^JNB z{qRZn9NZ4yg?r(C_#^xkM(2d-Y70BU?yw&$f@9!GunL|DFNZh7&G2RTFZdPAoEwJU z6n20G@DFe#oCwc?%i(JHC%6$l4c~8C+;DgvdiTN40-6;338x{YL;J=Z7hxs7PJWK8r|0rx})cx&@y1zH_0yr4^BJ3-W zp8zLgKgX!}FEYlJ4(zXkYq7r*^F45*QSSd?RQS)r*O9-A`D3`(sQ7;ke=+L*$l2lj z&5W{d3FAiDcg6ll_=ih5&2{|!>DwfZfqX}7bCw6UXA_Dm~Vym80G$NMx|>r zd=dGpnBRpT8x`-*;I~HIUyFV8oY1~8Y-N;vd!zjCgS-$PjeRlpW06W`X!BRKC1{`5m~^sC@he^LOx9qtcUperVsqsPwdk?U8rI+!OYNN5Ubn z6pl2?-;<5jFTi=mhCy&1=1YwV?@D+r@>?+94(~SVzD?L~MgA=OC-!f^FOctpKO#Q} zn_duxdk8$tDE|+K1CSpDhaw+oR6b5dJ{8VFJ`eK(c&<_YUI?#&e}sR555Q-Q%8zaE zHTV|%&?x^th2O)UVfM1nzA5Z#lz%;8Uw9-OVw8Vn@B}y+&V>u%3Zwj61+RhE!&{8< z?@qW0J_ffLRUh6oW(L7-%-27 z$J`GNLOvAp2sj4$iI`7;Gmy{6ybzvkRQP|w{vKls&66-cZB%@ohc6?48}s|{BjkHA ze+|Dw{u}1B<)MEKjY@Ab%q?MCqrxA8{qgW*SPd_N>*1sDIruvK3f97AE5dN|;6Qjh zJQ;aF2Lt!PH1sB4V@H+S>_*Y|NjjKkL&(rW_ z_$quC?u4JgFX6XF`BQ6D|CM!d=wBn))F}C(m^;93Fc0=K%3TrWp>QnniI^wDDx<=k zhy4=d=fg|j<#4r8{@-ELeSg9HDE3?6)5u@O{3?7G?u4JgFX6ZFNBBETzeM3Fe;dJE z*ao(TU13ky*Qod&jd=(hVO0FbVm}$q!oC_VGRoZ&cs26t;GdA+0XHFk1U`rSWuxNp zFXSJ=FW^4-1N;f5tqQ}>GV1=;M&(00csT3<3*i8GtWohFYSjJ5BOeb>fz#n!quehv z%KZh%m%}TtzZU!3k>3UXihL91N8nRN`TGL)Zyi$V^F7h+r5_mqm1YQo;7ZV z-$lL?eun*5@OR|tm&v`=dzcH`80Ft#M){YA{0Mjy_CsJf@^SEFI1SD<%D;t1`L`VT zC2%!d1OEhXgZCPB{|5Lh@@?=n_!j&SegeNT>iz>Ta=FY(cP4BCo5A)*x$kULe2+lh z7aom$F+2hJiEsuy71kK#-Lj<^ee*qn;VrMtzaB>fxTe?Jj$s1hZq(9DCFgE5i|na3Avh@F(~y%(_zkX@1fOW&|>K<$W(=4(8^t z8_a`8!y)i^I3CW1r@>{$&OxAQgQJSU@oIPnyc<3OABX>hufb2?=kTC0u78n`4PiFy z2oHz7U_LB@L!o<*i~Ktg^XYItya>AYwaDF-n6H8E{VeVE-X1fH55NcEi}0V&y^lri z-o^YS{5N#(U6FlSTIgSM*b4T9ePDk$2#ztvf}jFUf+xe7unL|BFNCY$74Qal6Wjy_Gzc=P;o(6x1>FJ?72AjY`pnHFc?(2-%y+1`}_x=>I5V?DQip)bW zPl6}InXn4hK=J?O{jQ9rl6);8Cy$4uvPfX|M{;f$qI13h!LZ?tLgSuf}{E{4;zU zZiO#E_x=;z=iYxJzKz_y|3v0bG5-ht0y8qh^k%`f(7o?O_vK@D?>UiqH0I;sL^v7F zhYO*5pNZ}}AM;wc4*mt+4_|?=!}s6^aKBM{pzq-?@ORj%L1^C=c7k1@dvA&EFTgwu zj)WEP1b7;p2Uo&N;WhAjxDKv|55NcE>+o&(A^Ze>3I7d$fxp9+4a4*u3OmDYFdz1V z?!6^S@3ELGpnGqL5Z-%!*_udlu^DyRZa69|}ehh2jLD(uw>Cv@& zPl?zGb640K7Qhj3G#m#f!YObDJO`c!SHer-P4E`@0DKTW2VaCc;V!rbeg)H_VR{;#7x z)z(VkNH`Wwg)`wpMuZ9?QjSD9PWh&;14i6I}ASuwuFbm ze53SO{or7DEF2Ff!KrX2Tnd-LOW@`3T6hDz4{m_}fSciK@GZC#?t(uWrRVw?MjD0Y zOxPZFgx#Tge~#|!i}^@67FNO&;VEzytcDlBXeN5H<&y=O@F$6-Dm zj)$}1Y4BWl0bB#u!du}T@P4=v>P^nB{I;?1T zk#I1qfG5Bya0WaL&Vv`imGB056Z{+eJKPMPgzv)-;pcEKJOF=y5zUn>eVMQk%!M7{ z;cy^48kWOxa58l7SCYT({Yv6uIci0OKfu(RFoD6H=B6umh65b4Ng?GVw;j?fXd=Q?7u*BCg1^Ibjct~$RTb038`Vb+G^*@}7!`-%M%`3y)VgY-QTnN= z#(4NnantwJn7OO|88u(ma^6wP5Jydy92JD4f^du*6@C}!O0`p-%I1nBUhr>~@9FBuiq0=)fT&HIi=OC|vi{ROCDO?6uz}0XKTnpF1_3%!( z0d9hiz{lZM_$=H8x5IbgPPhwx3crB+;C}c$tc3?*mg#Yo{zfntwt%f+JJ=oeg88r? z90;ABTmBBgTndN7QE(!h45vb;2ef%m~jV0}IQv&eVA zH{rW*C;S5LgZtt4uofPKUa#NC^yA96T-XA}jhbh4f!$#*==A@xclv*E2=Y=m9FBr+ zKS1*pw;y2h7L$uJVHI@mJ(v7!%uC@ixB{+*YoOad(0y+IKwOXfPPhSXf{(z*;WoG( z?tpK?UBDjX>T=&5b1yg$9u0@UQdkbh z!HIA(tTJ|1{|{^6B6v1j3Rl4^pnLzi?q7r1?PJJ%C+2(LeeepAEmXf@l~MEfIk3jqTJv9cwo&b9DO_e$J$Cyp;wm$%UR(j){)?4| znZ>n6rEeX4$=bQnw>wvQDGg8d5BTrPsKdbsCcZ!yw0ewHer6m zD9@k8?B?H!-rlc4C zlS+&D1k-=p_>VFDw~hZS(|_Ce4>Vbh_euFwm2Up#0 ztH9j#wCU3q%sMkjv7Ix2Myhezf@$+kouyK>QV8$)Z^@kMd9%Easun??8T04Pou#j4 zrrb4q!L+$@R8%p#&$LC07F17Pyhz^u|L|)ox2leTnymZvgC3gFx?e~AH+SiwF{tm( z?CjS~e_8tbzq#urH}%6+lT7?FxEd~|x+|60+NJ+_cc(~@>aMj6L%bu=yIZE~RCm@U z@AHXFako_0+Kx>4(XLa(rAum+KwXXV&(e9L{!;zRP(Zy*z|V(!z09fpbxHBhzpdH*&`lImZt6#uj>m+;T}u2lbymVXwG|9Sr`PgDKtm*Stg&V+y8 z>N?fGQu*ioFhBkE*Sb#i@8}f&)ZHii%av!T{@Gk^m3hR^``1X0QvEBHe^y_tJTzP+ z{Oe!OKbu=s;g`YtS5VKtaVhcBaFg(FY(4)5s-Z0UAN(6x&%enj{z*NV@UOa_e>R7) zam)XF{AShjZ)Qq*rRGccx4fQzU&y~w?-}mQctJh?7Nz*t26t93Zj?KtZ@)HYktp%= z*Z1qfu6@%ncN!uSKc9}j$Wdy!tx&l6a%JV#PJiak!h0V7bm@LJ7ixN?HzninbUptz z$-iwwL;pI+x%cn&dj5@HqxazZPEPJ*?S7_n@z*A(x=H7~Era=ayIs0SO~=xzNU&cO z#nRDHe?HvriuQvozxLspg-i3JL!jD1-ey=Eb1D>)fGr zK>WO&ogGZ|Z>RjTj>G&rTz@`(t?T*s@uNX-O$+Z^GOQN${aY1r?a2J=mf~L*{IfE( z--1{4eCNpU+WuSo?C*$r?oK&05*%j^_<46n*NfjhayQ2;`B^&bH?Us(N-vEBJ0!RG z<>}9-cZA%jF4supel6NXf}^}a^j;g~H1R8!yBc|Ngd_v?Xa42t&+^!}4P6FXhqKGZH5b-q zZ@sRz=hpYC51qceHb1_+w%684(`$wWPs&|<($qs2*!2osZ~wAM;r7~oxuIRgasR3c z;x`}q;LppyJ1Lr7Q!}ija71O$*?i7@D5ET`I#P9A&2=>w$^X^0J%dlGSJd_jrcb}D zy7TlEwfXtGr*_(ST~%&X+tbz#>sU3iy6wiBs#;eym+71DaxaW@UjAL~sUQ#)=vg$&~gLv*14Ue}AVI9=)t8{fZl^ zvZ{KP-B!I}SfsOs+&BN(FS9CYwpiQ;KD4?vYinlN;|C%+7fxGN+b93&X~T9Xj$4Dy zE9KM5+9UK=pufKPJ*Qt^+dICpHgD_7+FtpmPj9v{A~yy3n>zNa%B!xZzOm-CjX}qX zs%BL;*2v|MgO4iC)0$50+;LN<8yDOpS$_P`N009m#NS^qa7)n1!dxj?n;nr(*Vp#Q zZFJ!Gqu;B+|9B7|xTWdTrX!A@`r)3SV@cIA#p$GAS#9_HWpew#p6+G8|L3>gudnTy ze|>GQcqFgkYmvh1YrE&>RbQ_dzW(=j_CyN(^{acV#Q#rejdWCMbN^4Njcrs~bN}C_ zwe9~Qt21KfUbq>dhM`RduS)s_I&mUURkPLZI@*yj#;Z1+*q@`HhcZr+O+j!_g>K`wm&_lc&%Sv z+hFzD+Q{lr`{RwK{Cvg1<+@&8+i>gJ+RUw^$1YbbUt62Lb>wl&Yn$mRW9!(x+Z&DA z8{js&b$M-U*QABl*EZgI{ZBdhWA`>{*Wj!4Cg#&swZSv#2exJntL;2w?B2=_6}8=0 zkKKD!ll1+Er8hY+bxiPc`gcu!m^NnGcex{qW%o+$vVvD?gZ%4%%FQ=F{{O$fN&e-< z&E5|>w=U~&oZ4*P6>5>6OkJT?ddIXCYMHzBKR-Wh!HUGlQ}JzJ z@mo72^T5=SirTK_=|4;>Q4EI`>-w46Ws%lXU*GfB>LBl<9loy#y1(~Y{+_Te(Fc`x zS(^!_21Bebt9fYU=@)ItD9bLJS9Z*U*Q;c$PJD8D-Wi>%dQLsDy4l7xYCpGayt%r$ zUBxRNopE~ivbDqRIKA!08{~4i{?azoY;j>#t6$sW>XEKGSADvtf7yEq_nYt1m*)=7 zJnp2wZ|z%A+c|gscezEyqV-c2kD7-<7c>6Lg~_KJmpk~Rzw5psovNFk`^j=1YPI#;i$?H+%>W=(Bg+}uTuiYSNk;_938YqqRW zkLUW(&7Du%ym^iC{PG7YIz~Fbw!re-?0e@wsI(U3-~8zD=gc_m_UhNh$yM%~UuJbS zpHyC*Z`){hbgK6EXsfW}xXy9)`A6iwv7ly)`r@EwOGRh99@nXJ_4`I=vbYvKI_z1?9u5gYE-&Tv{FU=)YrEbz1kr_m+3~KEAr< zGWGa3RP`vkz53?AZy468YPWjlw87VCgt}Rb^d%9b zRll)h{&&x$zp-GoYU^J&Yh1}yo;F&o9KNx*?Q7|$o%E>2tK8MK`9p#pEuKv4nBMWu z2j5s=J$qQzhyPbur)|jH^5CP99z8Tl_1GG8d~Lx+YS*h(ZjrvrAgJ)V@SsS-y?HW`k%dK_l?>gX|zjj-dJ$m+3EXVO~0<@**#a3Y0Ow{VMo>~ zrumV)Ou6m8HLcp>`{JIE&$zzT()_z6`v3BaREBdU{g3>nNnxWiH6#0jlyRnn^}n=8 zgT=ixKl(|s%)Hh%zea1WhGOMK{kzG&osFxPQ4O%x>XhG)H`q$uQ`)60_ zu`asm(xS|)?ltMd_Rp@;A5)|o&)j&`kMW-tA=N3HPm0gZ(QrS?em*(j* zWPKw|N+fHZ)<9{to(a;k4v|VQBdbyo$js`{N%v>1)pf%xTk2$GHP&@BtB>5rvi_!t zVRqKFa?>d5CI#I%YhM$6T0Uz+o*vf9`n0F2TGkM`Y?`&8n;tvQ>ZOcrp0%vERH9i= z%l440eRA0{>;0}ee3bQ4UoFM5=4sa7ChNt+^!Rhu7RlRY#ba7>Wo^)19kMP_91hDG z6c2)URv*oAJ7!%he>!DN)RLxiR(eM%GqXO@_2F4Xnmx|UI=?UoW@VYOb6ZyD?o#Py zl_}LPW!aX+%UMmeg4~|9M(eqMX4!|pUx{9%c=n1!-%zxAN1{tr&V3@$*X8VpNc1|z zEI$%$FRYG4uUDyG6NwH{M6ZiPx2dGpM51#QvFjtz28!_wk?27=`C}ydkbGGiiT+w( ztJLV3a(PoE`lX_Gv+PvB-$$YymAD@w(RVak|1lDMK%xI95`9K_SsRItQN$*uMX!|0 z$J3%cwdVOEJ!(g;zf6xdYZe51)1&+3=U3^`d`;f>rAKEeU;dpQeNJ)tIz3vV8@@@8 zHdRsWPmgX=2nW)m4He#~jOdT@dUQtAzK1*}BYKNUe{4qd1bJ4T5gnrPJU%0OjM83_ z5j{z$%!uyGkv3l@-7r2Qx=pp{gp6o$k06+k5pAyuHZdc*wzD3z&4})oXD4Pvhbw|7 zWkd^9$tGt+*DJgY8PNw+Of52_XDAB}$&9WN&d!V;r_4GhGy1SRTap>QK<#5^X7nrh z`9Ws%OQrV1%;*rs?4!)+{ff)3%xDKi@Z-$rDAlP?GNS`kd3Q979@<#PqZ>x=k)N+O zjNYW$@@ql(Mh4WoxC4evCJ{+g@j+ZskM(e3XwjJ9na1dn7# zCn|!EW=D4^N{?knx2xbbXGafH0j$r7KBpRTTTZmOa`*O}sC^pk4w=*>@63sQEGK`? ziTC)!WNh;0UZqa*`u%_Lj<5U1Ot)k1Mtv{nxRFyPX&?!K?ZY|*-?ecq^e zUDUn;Sh_CyjS67sx@eYSUA8W2j~WhJ7ww~*D1RopSvBkUXQK9fsi}LTH>#hSwl{jI zf}OrMnyK(+?2SIJG|b!^ZLBEG+8cdE4Po})=&cIx)V;BZDu7}fvCuBgQ#u#fMQauIV!QZ3*?6X1d>~(z4b;V2Ilj;?URSAIWEa;d%a+^4M@q{I zyZB7yy3#H#RGqunE*7d1U1Ap*Dy3_t=ptJ+;aa;`qb$45E*h#bt+9)aDy{47Vz}aS z&J10wR@N=Ci$5w&wq}hDQxFlmcuMI?vx^Fat_gS$YpR0Du#1_>oJ_kIr8?2TE(WV4 z8rsDVsz_OO@s{#9Y8O*gsxiChsiM!ei~Dp}BfI!SeR5;FctNRXVi&e~o?{pPRQHl= z7e}f*n%c!6)v;!FajWvDxm~17(!wq-R3RT?7Z0m|EY`6ZMRzr@i<$D-T*Yo|X1D92jdCN+F19MFc3+TviacsKFOt4X=7vS8 z7?~0Eok3Q&CJ(80HTsvb_KZgB)dUtavQK9%Y*ejiE^5?Taa`PJsY>9?Mo*~B&uY|9 zo$R@dURGu-ZM0jh@%%=6R0tOY>DjW*>X$xM-Zd~k8)rn9M$*q$q8EBWR?uWz5WNUvq@jG2c{yfn8#XyU zh_3L~89|d1g6K+bOb?or1ksDVF)e6vVi3K=8zVuJF+p^dH!6a;8PO$?s1;Y!=|S|; zNapiOOw+T1=w*>cmVhApd)4{qIWi*MtsS!vmqraG@qw-8ht0y z>|U9MG%v9Py&KvsYks^OMBfYTwzl|5H9h)1_eEL^Q*KB9#f^~`<1DnD+!<+cxq15m zw?S@9Ixw46F3`trpwuM2pXJjHYRX3*L#~L zL4%cMV*+RMfVXK7G`Q7lOwc$IYa5ULM^`zM)d9rX$J<(lMA8}rIek?DVuyJ_T9C6- zg%RtBK;2G|n;UBt&uph6Yg3^H8fz18WvOdppG1vyif5Zm(DG4JS9+-ARdRS?g%fP%(p zvBB}^D&3p2Oyw0jCf@F0iPIuELC$7#_y;d&66CB^w-Gzm3mOMGT`Va>yg*I+7nOai z$P2QAoayRgVkKS>4RY+;$+1!|$O>}G&BahJP|C)rPmh&(fpWJ=rUb*hAT!AM*djLE z3o?S7ADT)q!VA)aoNFzn$9aJY>9 zUZC8u2l8X5_*f}-PE|h}o8kq^o#pDEVpF|9xwFOU-ZU>z?p&ckBR1U&lsi9IhR*N; z<<8lbq?ulz+__%~ip}x@<<3HN2eDJVAk3YLc;?G;*TzL@9JzC=!f;1pZr1bIn-1M%SRT)|eA5sayCNP zI5f!FXfD=xL7O1w8w=%nFK8X)yk#zK@B$6hADQ5fUeHoi*1Ds$UT{c|GtUG!dO?dI z=NuE<a&9ugpS&P9$hp{R`7K_cp2j}78@tsDR9ozg z8?p6XpxW|~)rH%bA@K(%GMwUj@5foe-5b8(j!sJ67R8h5uB zsJ3KTOz-gm)t25C%3r)dwdH2(>F@Od)t1rLFZ|UDR9l|VL?L#+7es=bfmXpD@B*to z8L?IIOna!TO|~`O%i^uAX0*B7yxI`Ywu)ud=O6LtY^y$xS!O)yJy7*2vu^h>FHrTl zO%*QoxECnS3gW?d=H(W|S(bAT5k!W1wb+yKYzy2*v=`#hM=XegRw6I@!9!USv2?!d z1?t%}nmiNF{J?y4cF!@I+@Q$DUWsR0Sk@!F8;|~EK0ari&iiyJQ8hYsxNpWYJE%Rj z`9%(5Z_}lGsu^r-XFS`ywp4!>j~*vSIrm!2+C!Q&uWT}+B8YwI)0iU<@ORNI@ z;sr{=q01t%{qf9Cba$Ig3M%$(y!E$c=xG({*Lb$|HsLJA#4gAwfpg!|;?PjtEW&2X zGGd3sqbDm4ZEa2wG`EM#VqN0R7f6)b&IbJ;(&8A)-M;bW>&+C-9%KFD&BJciO&4SR zJn*ZgIRvW%?D$rg^mg%EgsXYvD4$t zJIPVMNIUD(heTRjVWF=K9Ti7fylRdvjyJzTF)WR=v#xD@q@7jKJ0mT2Xps?nD&9O@ zKHL*&XSHf;q{WBU1?>pq|5T*K=jQ0O(8H%AEe@FR^?37}bkDPqc2;k6&hDT|KMWnE zrL|~it>UA2^JQ|Bk=D-Y#h`G>i2lMm5!>%rmj(Y{w?QYtH2L;O?KMfo8S>IPanji!6#mzGE>1m*){Whm06o7tze&`U{CKQ!|txxR^(Q&d%H%v zt0&Fr+D-C(-UId6y-o0MFHlMMGr`whppqVJf^WP)C0%TS{a&B}e}oARc!7$(+yvix zfr@^D3BL0J75ynD_}&Xt^s`LxgBPgi?GgCcf4o3N|5p>#dVz}mK@0oIcgwcIuq=;ti|*GTnzP$R*+$+2W%*tcH1Psu`2iE;dV#XM)&z%mfwH`_ z^#pCbKsnsg1ns;)IsCMZ*B!h-+4YhM4)X$KSHrFn#Jxb-^_jWo=mpBIJaf^>3)E7+ zHy53~K+~avCg|b?nhs^yl)kGMsOgMvD?v9eP?n!;f*xL=wlvEGJ-t9}X|4(Kyg+Sf zu?c#4f!fk}Cg|-2YD+6k(8mi@Y*(7#2rp2vZB(xp%l87cr9HOJD)fS|92<1YJVXg- z^Qx6&R=2QE{LHepZ?|kKVJpX@x z+CUVvwXq_jt#vF}ZLO|1YHK-_8)WactSRr7ZXRkfwaLv6g^a82XN_4|T-mG9W zJ3KQl`inwuS~*&7&(3qokv2uv@R#T1Oq7j9@v^+e)v6(36tBPoi(+w!;&`PO5T&bp z2t?^>Z&s9wM~&2q$qN*vVT#f<-W*2h;=Jfp3a!nX7K>FxX?k3SYx8m}vKH?}d6{>} zQG3g}_7*vd=S_LhCoP`E6-vyy@Xkn9c*6~OnV-t8sk2*~7b;bbv?lwfylnHzJh&^b z@l55i5~{4chiI9qsI!8J{l&*qg|WfLkbAvADX-8S_j$8YK2GNQy;&)*7$L#myg(@* zXMzX3AdKYgdC^N1e$z^Q>oj&JNndWugbjH)7JZB4Kk^z!)po*2K8gp4NIvF$^pV`` z1w`_3ZzhskyxB+c2`})Ge9{ZTNIsYs?W6G9wC=5VJwzn$&X-|pUXDfI%4dCEW{DiN zx9n_h(Y2Uw%ZpC2n2#$}@?NT2KF{W5u8>_*XZJkibCor>m-DjCEA!yZyvD6GlH@!h zbL?#&Eh(Qzmltc6l6Tm8xr=E2kyFu6F5dM5siVt>D$Mu%Ey{~B6TI&Q>KTr)zU^OL zpq^o>t+RJ}fqI5+mdFphKtU;?JMyAOD@si(rBIK(PHy}|3!T`9c{!FMi}z=Fjkm~A z6HE6Vf4@337t6g~;A8of7x-B2^8z2se|v$IS!tQ(BwnCcj#oX2ed7gTEI-bRexeAp z>1->>-NbURIozL@WAV3G{wJ^T;<(SPKVgy>cu?=IE8Y%uRCC z-l|4>%jfo%3`)b2bqGyrl*(=&uqi0TIb!D+$-UCIV&;)(FK(+p4 z%b9#HP^>oE+`PaG6sxaH71-Ac6suL%k@fcimCK`j{~zYw1Te0u>>Iy#?%XuVWNDMM zO`Eixq@^u1leH_9wv(Aj8=9>%lWrhG+NKM%Nl4PtLfH`&QDha7r3wN9BDf#|vdSW$ zEQ%l~Dj=w!fPl*j!vFU>=Q($7(&Fp;zTf+O|J$DV-SeF7InO!gInO!g=3WpM83Nkn z8S-|RA!xp5*0_yeY0}GJF@Lu3{g)s-hu4HyBk~=u$?G8Bzu~}YkqjJggo-b#afg^e ze*j_4k^$eem%pMW#H^V?XHDKdX7IKR`YOW#rB4Z^gn$g0y%88Uqk0At95o>GQ*+@Mp!y?v85o3{c z{>GXR3uh6>*5rMOMKqJX-DCi!$FnVV7y^p8rxAocLqKaiG8cq?LqKai!)fPuA>di? z;$JY+K||0L-(2I~O|E*$)mGtZ2kSFb6C%Il>cpD7=gC!?op7&=1axFdZdZ-_5i|G{ zXT#kx5+0<8PpJtpYi97tn!M9tIu)f-n6^G;cto}8FyQh(Z3whmQW*N5F$7fWPt5lm zLx6HiKLLJm=MfSOIQi zU0PFkKOz;s$Q&=LnRXk<{G&i_WL;E~_Zl-$VVBgXBa=ydYfb)_Yl@jQGx%yvVc9{* zAeR|mBN<>POwT#j3V};pzLyp zb9_KD01M3E2Q`I{GlNOY;2z1~W>)5*no?%XO5RkH_cCrP$d^^Yyzpl?f&2?<+<)SJ z3MDv&QkcT5nBb|J!bvcTi|?mW`)SRzJ3%&L{c%m+5`;}sVNcYk(}YQLh z1~1eU-op%VLWL<*GJsh1%>8R2K&)zxe98FDl=!kCm?`lULoidz?+n3AiLV+0ln3he zY)#%P<1d8EYi7ao`wxqQzMgv-Ahzv1#9 zhG4k-4?{3qzHbPI%MT2JT-y16swq4N3`}~EE&gWBR5CDW7S-Q}HKpXAT)L5Q*OE)V zP%wW?L~|+4Z$}CrV+Oxu22Mn0Fu=i35GiHWY>d}y@?OGi1?y^6FfY~okJY#z;C>2Q zdJ0=>3bSH~<0Exl z22M~_k^#rSZYtvGh5(g!9C@8#2$0)Xt3a4(2+$3s%wx78Ab-fMBI4dpCVs)xQ-p~Z zsOt`igvcJN-4Mx(VZ;=*V9n7K$)1@0ssi!m83GpWALfHF-w?0~wusePUrACwEi zA|V8^R{iD}5Dqg0)ZeO*K!UH+cxY*{2k{>kO?NZ$G6 z5>Z+s`e@D#!Dhx%(|8?~TP))8aj)%1g>so>a6CQx zA|YnY46Z}_GlQStC;x^>#XgXg3BR4~f1@Ell*)Fz$rORML=jh`{b2`A*|;E=tHs1cShfSGOyJ?sw zj~Ie3;vTd=RZ}BtK&A-ZKQ2ZInHCE zFQkZaHup=B5DRA!e~9EwKo=^W!RCJ5WPrB#9&>!d5KzQ!GVv!vfS|sg2g08X0gZDK z7Xoh@0vhKA6q5gzAwbaJ>URMa@p}Bf5;yy*LQfYAYw}@Wb zeTZ?KAE*tHUviaKo7apXUYyUa6spax?M^5A1%?2w_R@SRGz4(<2eMgY2;gceds(p| zfU8p2ocUu7L38ESx?51-B)&*Ie@v~ODbI(km0waDBERHna&6v!kgKC;zg3zH(1K4O zLjDv(09UuLdrdV2aP>11rWpdb`Wo{H8v?lcka<)Y0<`1(j8Sa}(2lcEcK&oj0841& z3AOGtXwgY~*zwDS?=xZ8<dFdEgj4k4_azZ^ zusyYc6IHl^vrSb6Cxq$>YUJq^RGKp?sQC`6pmLg7L1i$jf`e~%>1AxVvf9!wqiP3N zu#zZ)2HoGni$7txvIte?{YP+e?mz91;NCg7_)U<)H$cvz z_LlKxh;^Do%=f4JCHk! z0#MGW=$oOF9cu0|>x#W(XB0ifWM@K+S-IDYMKa5I5iK72jPor<{WkcP5ZDMCQiZbTg$ zx_<0Q@KkSyY(qDwhmNi4>kv6~qkaOpnlJYa-K0FZ)phgW`G)coSk6L}7`oY6gbbz! zLwDub2%Yf-nAf5Et0@jU5Dd&X1cM^<;0)H&ww=I1+Xj!fLO-e`Z?+u>%vcjf_~X-A zIcz=#X1qvFo-*m38TWEv{A>!_1JRusyV1=<&rV^pBEDnI42JG-r=#RqeC>1SxzMMO z)2w`S-q7o2O}}`d*vyzW(Q9~beFm0@aJIX1$Kr%I4r&DxDuoe{b}qi@KkdYhTfjY zd#n1RQh44eVUi#+*$Z?A(FsHEI-kaU&TaS^^CJ{44fnUAS3${Lq8jc^>J-a41_Lwn zzVk2ws`%RX8KDoyo-!ZmU>K8ZD9BZ=+ zp<27-efSDWkHr!!bg1@?Ej^o!l(0+2FMw_-U7G`6mkuj0eG`K)wB9Z`6k(O6-(}1V zIxK7*!avBm02$7?ls{MF2Q>_#ZE{GR9lW0vyh7cQT@|0q>G(=Mvx7IA5HhMmD6Bag z>vQf!mdNN46Nl`pI3T`Zh~!%*r05W0gP;nl^Frp~4k7IBIi$`GR^T`EokIL^l^5WzW&Q?(TI+=A6(kAtUrKDtoB+Hy94RXvF67OX30tf1wr z2dQAa6JwgoP)obu6Jsx68g{~hOg`^XjvaUaGR>jS<&U!jI8^)+SiY^kJtg4M4>rxk3i7wl1<8EEG#!Ab2|h&G2mAW(8Syq_K1gI|YlGA%gK z`6kI1gAlGq0~DNARP{JyA1*j^?2JQ=*v>2Iz`a#{Cq;cl$;t2ptGn5-Hz`kU_18o2 z++K14LJF$yqR1XBxfPzV)h9wx7yP{B8FP5Q z{AtAx7`+yJ<&Zi%_!Zv9)GZlP17{F7I{t3ny?``xzJ&T9I@>FU;j@Ej6P?_t=pdeH zh~!e|p_1q7RY@~wj@@;SRW=Fh<$viP2f^QISvcL=!}namEp0FM*HR8a7yb2GVr zAB3u2^n;wj$k?riL7*kbuCT69b;|0zFg*2z*ZD#d51ep`6hRQB7T>bHf9 zr>b$Q#z^7eDx{!#3DYc@%JgGZCoWu8%uZaUI&ooCdB&?wT-dBU6RPJ_Ax)x~axbrb z5elHNrI_VZR?mdKEnKcV;p)|s;aQ1B*tqfVIJO@|5i%F@lO?eKf zo(nZo*seTts`>Wz!VcxBQN6OTtMp0;JyP929wDogr#8|%IA|3nm8Y&c$}}nEsjvQ! zl}js6Lv_T3r(1a%t6wGutCgoojkdydYP8L*?k-2j`f3iLg=**(enO45#b|3<*v{3k ztO}2IhAI9TP&YY+J!6Xwhs3YPP$}Fvl}(OlpTZC>+~m9i!A^^isqNFoFv(+}+eM4V zMww(Btf!)-N~}n7>Q1iQF}5j+`W`^IwZYxo0`w7Z4& zuR(6)gacpO@8Ci0Uqe-L7|>wBGO=qBEoX^|R_iWT(HcHO&OQtl+I3#ohd~wA^lS7E z{Bey^AZxL%d4(y!I&7d6p% zvX2T@DC@vF^fDA3DHC3+;b|`V(G6m%6!4B&4##tB^_KaW$+v70yPe}alb_=UVdd1U*}L&+Tl#2;@AZ82DtgEefpefl+EcNoB+4v z+$4T+q4P1T9nS2&W%xWCJ%;#w*ZwB)z0~vqfYOR4=%8=$NP_BgUBDj`E zk%FCjq21-2&sX4DEtlelSuV6!*$pBO78A7gG2>y!-5W(-^eA~Or#u*8jQR~SDrBO> z@e<1T4IHj$8=|enjcwg7`NY`a6vb<^zw$-eydm}$E8y6GxmD@=yd zO?RYjx&{#V3NK&N?E@S3TE{)OnXJMyy6Nr(O*I{F6t6AFAr8lD37Lfk0keF+G;``e zPKsfExKzC?OBDwtji!5xk=8r2FF~ZG^kgN&2(HCnkh79G4Y`~GhfDR78Mp~RAtIk6 zo%o%|NA;775rvzDbz>jxxUpwIx(R{T!!3CLeRwazZS}@z`wb> z0{JHhf0UUl`6GOvSCPKJOup;nwJ_4(LFRko-++rUqi?A=w=hoJ%~P3_IOxo9$c1Y2 z4He@_#<;;Lyq38f4l=)bS`WAM_Xue|0u)+j3Ah#bt8A*c^J1!NQOzyr&?NLUc#ZC} zTDp+8bjrXmOI*xHDeNV>XM{npFJBY~BiW%k0O8s#jynaQ5X# zB+R68WMDoE_$Rpg8{9mlAdd{JSpo%F6U6Qm+!4#sU+hl=!Zf%8=Wm_QPbS$t0cAMw zk@>Z7dO8{ksOjib5cr+d`Ly)y6E*QGAY1{r61h-Ms0r%OFLK_Q63}}7O7PV<$kL_+ zmeFi(oLvFW)W9;D!;Soen>{VC>;+`dco1d|I~-U>gP}<&;Oc-<4A+y_aMbAf}nB&lo%K7^j+l^fX(m4n{TgB+yP!Ia!Splecm%obwwE!Ns z52XNZLhS3|y85T8_(##&w^wO-{6x#+DTM!+xprR4u6so`(;^mr`IhA-(<|%*GyN+f z|Am=yVP{`yC%DY8S9NiTYhPt2xZtppU9>&zeRhIN4?Crc{HiW;0wh#MDRr*Fwt;<8 zwn#O$F8_sBV7R;Y!^Il;O04cw!w1- zO7DY<9R<%=G(r$=DHAt;0TllE(t5Zkb!k{-tVUc{z>O^j>28GG0=I;=EGKx|x}Lui z9ru%{aqN2_PsDP&6mBU)ntuoizYjVOF8LHZPm=mHZU#Zw4u`AdUi=vKj#+?LXJZvI z4rc}X7Krxce>nnqsi7aX=ds6p6IomhH;=oJc9lJkf-S^E{SOkAV5{wU6ztU?o(HD| zJKdf~!SWlI2f=B<9=yL`f6rp;MX-G5$(e9Uu+00r^iZ%FjG>iqO0a*z&2QnBGO-eD z3|fbuRaAnlW|sKVIQ$yHei>n(gYyaY7=}ZzFQUduun&i4F6Z* zx|NpwiBhrwsD=+gTdhXlt7`Dg1T75Lekn?y0r%IHM)5kfQoP*=T?MBUFJrmtW%ohc z*@$u-;w#0w3vq_wwBo%SH;%<$4n0PE5)qY7<)3?gh7pzGy`8}pe@%`m(pM1SDn_!_ zY=E6qkDCDgWDs#b3bnN(r_({@UkZK)E;bC$FLCp8xTTEM{CQ9cG2C3Z4z&tH4z^m| zL8O))3>H7ohLnYf$8Q(%H3u;)6Rh>P;YSQ(@1WlwkDDEE&65#wK5ovVXBIry;^rE9 z=E8F)Zn%bA8-*uu{@Uga;L{-d1a9TgD33PMF5q&qvQ@Fd-$QtpA1qdEyo1PZ!zniM zuxBv_PO&i+H;HHHhvXQ~fk#Hl}I1_|Z;Z|ONvdG5CKy+?eLU-ZD z!QWbfi5zIl0g$do)UU$DHp259Zhi*0lu?>b2IcSY{S|J>8LME|feKTIee#Wf`>PJ5 zx(;N%S11G*`!YN;a1*BIJb2o1(+aodT}d6Vb|bZOhdY;v`AW6{1ott1Aw2vWOP&|S zY~>?Pg7N@@?ql2`c%H+}&*2dJJ18oR*a7Pi7Imi^yAPB% z5%@aXnwf~r;Gp$)24CXdKu(%KErUuQ3%8U3%}YU90N*^gb#0O;$0~>Q=B#m*y}1fO z?Qpo({{&_1Ri*Mb2$J(9H}(Rk!-z2m*Zdkh=i=rZokU6WEJQ}5B2)WM0e4y#SfNC( zK@`3n>PSjdN%Btkz6Yly$yAUeS-HdA)rlySrr{*#g5Tm;s`DG4$-Xg$f`OWZfe0VTK&!QF668K5M% z7rqnWlmwY52QNxPB9Y)F2)Y0cmy+OJs#N~^CHQ^B_#T{+;8VDHLMMr`PyQK^@iu)l znf-PkPf70&2!0JND?JO_P9K1xq{kEv{!A0UceuAxeyb?}Ha070RffEUSfD{3&8xULi;2s3-gi{h^aL`)D;7i!TaF52Tn##&eux+!z$pn%C`Vt1)7McK zO+vf}%XuE^kjtHIN!Ua07H_!sknG+l;108ba5{4YJ6X~2!6)`XC=(914I$I|= z9H=_h*16ddw>D=>+?vuQ-ZTv<(i0qxQk^2bfcr)|-yR2uF8Ou6) zSp*^TCphPNA@dJYC8~POU#?0y^p1Qq*ciKlX`Gu7wP`D46U?)V`HCp3;ixH){L{e- zhwGKbQz2FO8daSREpLSHJHcu6Ioy9~QlHDYEm)w!dxCQiK25@PSe1lX_Bi{XqSBC4 zR8iDDahyFC%@~+rg+fa}LT(c*r|8hoVWCB#R;cNqgn%P=o<&N|Oa)_two|ku6hbT= z+eTRKY$WE}g!0sli^Ds0gDxJDd|jO{o}ofa*i(h2b|{1#KxYm`g?Klm_O_OWLWQA% z&_d)_3^KV=sk7v<6GtQ-=T8h{30b?@tV{iQFjIUPJ)7x5FgxC#o`eau-C9bvCRU-+ zbx4CJ)o_ELN&dvxlL9BcvMLG@jb)&UxIz3Wyukw+#gH_%+vn<{m6VrGT8zdGX9W+% zQ3~lQxgZ7^sFvbX0%km2uCp~hoQ8ZF{4h0N754cV^q*E0YeQ9svOE**y6hFa89H_@y~VO7&c93Od2 zjgBojNWYouPcY6d$yrwZ#b#C1Jb${t#P2nuU(fd^7TSW(oMB@KT-c1_7oKwl-ilX# zKJOuCY+w7cZ!Ogv9fn-IJ_)0x)?PZvusCbd2qq5qN0kDXOtBkEllJY+Zui8sp>^&W zRn4U#yBi!Xo2yK*=zejaTNxyI#N6zCJcRtZCsMo#)WsSHFKjqnE#5BoG9z!gNZ15k zy_vH0K$W;eOY(>jQiEt#>ZCB5My6^l)s>fY?IFmuB!}5|9DoJVI}eCPcxj z{NkiuN$R@eHKkrg=)>%vBREM*MylJ32)m_Le%flu-%nfPv96jcq?>E4Y7DTnZognm zlpak4jzpOF*=Bens&pygQ+FwB9c9NQW((lINMr9sDg8?VJl~PSvCn~S94*4urTQ&ddiTpSb|$DtXRmg zfB}8`dB7L-?PY);>082EZ~^Q5VSv8W-!yXW^JR}mok3vMBZxYI4)`CHiHus{bRMg| zh1+}KAP)Sh3tB;4zACXEjERcg3-}jRf@vxjle4A)tNtn?#bR4WF{@jIOw`#PbuVtU zcUP9?mZ=&QmxC?s@30avk`G0s)zo8JALsl!t{dM zA5))&upv-1VKUsPGVH0K(fPOwsDfF}2%$qskwVhjrNez=c|!AwULts2bt)e=Ve4>-rl`{*j(1Qn}Ygw1e@&YNR3 zop83H^X42)Cvdr<;`2tA+l3tUWpgCb`6R^<7>RNal`6n3G|*_lgQBkz0JEeZVG;nCXO^Lo&%A{e0{^+ zvPq=#5%mE884g$tUir3?1BaV0Dw0W3ZQv=y(St>SXMONJf}BIvE9I`s;yWKsuvi%-BB6UmZJjGKRX=|RHxOdGB$eOy)gxT^GXmAuNwRVBH)0}g|b zAY4`YxT^GXmGrtbB9FKx!-u{>2*aUjwM6F6>ZGpX-3@SvL||!*L^O3ydAakkWj$^0 zR`KeuIuUr8+_M5q!@&tq7yAs;D5oeo{l`d2XS;JhDX|Fh`+rDEAIH^X6oZaH@b@U; zYQG+3xLW0JyYl~bj{;Yoq)LPZ89n3xBjQ8=I}NA=mJjN`9z9trMoXR*`=5_VB|+q* zuQ0%u?|;fIMFbx10I*BrmN07Avj}SK?K*}T9*7Krx^&eThc*z#3W3pGOboDsO%m}U zz;~_2{Z=?6BQRN>PL?x0m}8QTngtQbyL=U9yX@aQ%tM;zUUl0=cuU>>KT&Qhp305* zfV$sVP9#hJo^qRum=Fnp)kkLkP33mC&WLcYWJDCMD*asjTgt6kXHrXK?>eAzV`)@w zL{sOFS8feH<<_7^IMa-@Aryf`@8ZDy7%BbNmD_(yO8+;N+r6mmzt^MwC(4bbVAvBz zjUERibB$7&|AR3(Qn|59`NsOctK3Z2J}~3|e^qXAR2Cc))M>MCb!p@*SfFCAB0PfH zK+zF+oT60;@BX3#2-O%PI)HaN?-5EcjEp|MbmV|540kCUEevK;5663=&aw-k>I!1D zz^IqQF$(c#aJID?zxuLCr1KH=sr6Su968c&2j#AjQBkPcqG2(pzF`QrAgGHmbR1vJ zbo6vKdRoQ84|!%q>*0=uBj3bLaA=eZ06K9O6W73j3ZlAfyAi09`IkAQege)nlc5Y1 z*~b*q`Ik9137Y7YfL%>5ucL6MFMA14$6VvlaKmYtqQ)lCQN*=yzEz5CbJk^*SWAGq z^p{}2fcpbR9l;^f()nay*&L{vm~Cc|`ruB3LtMgHaE>(;%mJ#4QYY~oI5JE;7tSX% zt!mf>q`QA?2S*fjF-10hn(^6g{z|Al5WbJyR`QXAi$OR|5xuU#5R#WE@=*jHg6CR0 z3oo*BKbq`G&_vv%BBlt;DroKY?I{IRUTGD@D*~+jdqwzDdpn7?;%8KrexetXsBJ zqWGkpC3>QhMF)2jG`l449=!r%j%#VucCweg{M8;!@&^HGz zm_i&Ci3jQcY)| z=>HXd{qmWB{Kzj|B^+h(ulT+j;r{ghQ@(4EUoBic9PI@TCR#}5;+(V??Mjy(<@Ul) zN9AM`6t#eHcj2DS*m|7Q=spm~vdr}~Zhi)rkFWx`GPntFbKw@kE%v!I?)`2r{B)_FjVppzeenBn0-+%a$iaJ%8mWn}!X z&!shFcA{7S3FL+Gax(oGEDfm#L5GR|68> zC`j4xGUfhP=Fc-QK{(cZ5Kq8Jr*Ewin0 zqgA)He@Aa!&-UKkbz8R9MF%(S+}770>mTfm4EFZ*4)qMx_3j=XBs2~U@7%PlziY7n z*xrr9Lv^Wvp26cDslxTqhw9=#tGWTy9UFI|irf9=)^6|L*t5NEXloDn@~YaH(Uq(l z?(g5eacj@EzM;A;8#iWHpN9HOQ>L-Lu_4n?PhtebNMCp1zH}LwLU14BOg`9Mr1X8Fa&p_`GXiyU9?3?i2ad_|~BHB(8WH5k0%h8#jD`$FlZ|ofy-qzp8 zgvfj&26JZPj;1DfQE+lW3kQDl3V89<>R<*6qi<+)@1W!a^*l&rliATTG(3_jY6uDQ z7-`cm>w;T+F4l69HT2m_0o!#;T{~x->*maM3!U3ZnBbPF#8NxH%2(q?`$L?!*e*SGf~C8pG-kW;3#L=gBs*F2$^9dD=l8d-T3ujuL zJJosUlrYkKSBb-u6Ka~{JaCHb;=w(YPcASor`oL{BEeEn@#!@9a>M=rH)p9G#Ge>A z-*Ro&DJ!eXv4hOP`O%4_S2#~9dd^}^z4=5tXKl_AcGw?Qi?Bm;9E7=UnUaA!LI!`! zML?-rrC6(X$y$vS2vQh?Ic^o90c=IxDT?34wGhR0w!>6+dbL|#gRpw!ToxYH@DHiJ zH331+Zrd$(-c%Ak|CCxcSKXH#;x2HmfW+9pN}R_i+lkItyVNaH+)P*8%yOQz!?mpS z!=4D2qA6}+^zrBr6YA;?LArc&4(Ehg_KiAF5tvg|imP1ZLUC*2GS%6uoCnasL(UJ- z+4X(7x_1$;(7A`4mz8-bD^c5uDQuhRZY70)LBRf7fVW@du#2dc%vr`ZteU2Rai==c zH!vo~B5H0e$TL(U+sVJ(VCIX@b-VJ zZA}Jf+gtvfww)SwD{KFo&HFgpOHUHhoEeMVWzKGltr_mZN_SeLyYLXVbg?__AhdW! zb>B(h@$N397++?FokH6=nj^BBajHnEawj%34o>K{_x9LsElM4)75=SbMk@SA zcWZ_JgrXaT|IOX_BXX_nC4kz#DaSzoxxn`3h3#b}m zUeJO5cdkDPdD(86^BR83o#V-6Mz?|WX>!XG$_H~m zVI!t1xyq$X>RnB*bp9;#3lzNxS|7^q2zPQTV$G8lq~XEbs*%(59OulF z)C}nSGgu44gdFGblfX$C+W%&>q&o?5Y`3b`onFgd$ThDPVRtiZ0vg{bhQh3Jj@N4Q zboBEH&RT?_`E?}T^eaMjj#CPK>FlU=Tb$A(YTZaJeMcO@TuU%V%@O5$I5Rnx1!x+o ziWt8OvhEX{$42p|=UE5U9LW~Bs#P5SZ*s+!ErNt{bx~j13kwI{0#2S2r&iQ8PB|FN z({P!nZptu!ih)+Aj0g7G7oEkbY7b*R@r#~St9Eu^POGBmMhU+vM^EDavU;4JAZ;V; z#b^8{!sfJ7qIxa#;yXx88)|IW9jAMlJ29*aeS41`C>k+^y})KFO&TbJDt7_&j{_SNktd45ROL6Al%>S@Ge?BZ(dLvF>P!kRRYFzj zX1cag+bG$dS~0O|bDTZq-d(T^JRMg%+PbASVfuqpS;`^K16J5AK&@2QdqR!B za_5hZZiYLVfrs6}USmWJIhG8sotOts~>Fy@L`&Xv@|<8`ak5S%{JQbafY z{9e+XpP~|l&Oc~ijYsy%Zk!XQzC~bR*j)h9Y+7pULQrSUU~Qxd-X%zd2@{F*;zAeT z7Eg0w32;*4$nZ*e3N{Fqe4tKu%k`wi6(Hv_9q&dMF&I+!fg4P2NO;ewthsYY*qy2T zs})0kLq1GU41lcAcRmf3B1WtUw4KkOZpiHsE9|^R+hW4_tVvw$9)t{vpns;jMI3cp z5tg#0p0gH{NsjS1kSpr{2y9Db7Bjngh#LByQ&=IU3)$ZeaOu(WCMq z8I^a~wIfF5zZgL;$q0IO^a#3Mji4V}Y)G|8<`8nx1B<~6hEkaW3oAe82PE6yXM0y$B8>>$ z9jypXrV`23iFkwM+e5YCBR;Fs{?CywLUC6^~O|Dwg-IeH==arO9q`Ep$A**e5yg`LoU@yDDHrO-V>qTbm z6Uk`GS9jAg?WyIN=I$1JEHaa7U7xU`%hOHWah;)Qtk#Z9H%cj|=(Xr($@l2$qy?MSg6(Re(WY41b<@dUa8`yDDCZ;7QW zR5I3@X>E*UV$yk1y*}oWt1`{#x$)Liw7JbEtVDVR^6gr&PPb&Ht+ivNpG&kQSTyok z)7sLSiFT#P$7xB1#sb>38GN);2wP*J5od}iZyXxoXs)|SksojZ2y$*8oMO+CXss^bp!_H4@Z z4_F&<1ae$vsCRf6=Ql%EtfjuaHQ}#W&!$a-8EKZ}+IS+BX!F<-4q6&8iZiLsmKMlc z*oY?Z(M}_eShORf8mGNAt+-7lqVaVc4yHA6zSP^dsdrO`gMuTtxuHR@QLssHuHZbu zg@TK${(;`UY?)Le@z&^abh3_AtZijxd9<}78?3u9UhhX%GMyM&UYO~k&B@l~E7CYf zNO>LA)Tjj+S`bAlS&z{hYsVw4sYH7c_o$TD0A|7>UdYr_MKU!$EMA)Nj2$LAXzaO<(?I4+e(N#lUN%|B;r0TAbJne zNIDADw=%IV(-Li^p76wMWimKC9bO1+kczivN3bVYbcJ=^f0rn(0(1!K4^9hzEOzaL8jNyArIg8cirgW5cLPNUK-;ZA)@F zdnqDWU9pyic+%p`G-{|PI$K97o8}l)su>em9m&~75An1b6VX_z-fF>jkC9 zQfbGh(=bsaqcB`raNpI|jX5VBi?+3ooKe*jk)mQWhK?158d;I59~rMZ)vTsv)sHFeF3 z1k3Ib$2jb2ZH{9G7|Q7-8&nrec{? zx)T$tnIDWaO_~;D+nL08YK!78fd3aBNQn1t*a>?}%u;E0OwO=Bx?%Lh@EtAH6Ja4R zQf%iS9taq29Xx)y&pu##nJK#s28os0GnC$j2^8j8pBiDYWE9;q-2y#tsg`Vj*OW@7 z(%FI>(6!fD_?~vArM0EgG77^)GcrNr!8qD)?lHkMaID<}L!;H6*Flqs<*oQWnCj0) zQJFG0MAf9%vjJVfYK=By#4FneRgP`mlIZK%usy3vJ>tBA(~Rd| ztPOjH@zjBtX%09y`BXsGUTN#ZHEs*Uj6!p^>7tOs^m-9tTFdRx?k4r*MQ>=tr_CpsV$)i0>=Vq#{- z8nopSYtWWUtYNN?!)V9KOl(C0YdR4glxZeAQb z+r4~!vWj;q{q9+Jp0z-0F|Ez86uMSh0(OFDxD56V^!5y6@!Q)21@DoEck8*E{lqt- zv*nrztYuB68|yeQnxNqyOEfB-1RGXA7l!pguYZxH;xuJPFoc^yr}r{8vr>H~zABxG zuh6!>r}D8RfYD=wC6jhL=HqU?L{nX$1${KN0v1(DSq>()uZyEKJG+yZu%WzL+FE02 zuanHRAfwe<4L53oC)TJ89#bLDcG@^RxIJ5uWTGn(O=FKD5ydiwnR_Cj{kgTLZ_{>| zU}P!P9&42n7I<~>G_G_H!?hXWz9oGd#se33%EZFMHnIryvNFnjd9=M9%*guKtXbn} z&cLuRl4v*>Ag#-n!`eu%Z5=VZw)Ji9M}s!tWgDjA{`D1xD_Sy{$c}fj{L7rsKe!3q z#@Cq!cQb1adw&*QzFwzOYp+yS0ydXk7Wr1%Yep%hCIp>M^{wgHbF?fl}V z5vA%|+KN*XhuYBS=uR!Z$q#J2ZhuHixtGr!LiOsvL4l}WD6+Igl**{Oqi z*<&oL7GT<8Qc0UGnM(WC6R?kARJJuop_Ig)h-rJ@Ym)7~eOrdNDvb!!8_jA8rpo2u zX$gMGcuLeiys?1+i%&PT+99LS zr`9HIJ_(7sfoa~3T#cmkh!KM%PsC>g8J0RfM)Ci#mlqQ##{%tC@CG8MXZBK}7AvWOh1g0de459n5y6x!i zYsZvKBexZ1gR&D?tpt|iga!?b8k#iB)i6)Pd<_e-v#d6nJNmUQ@L168$TcSR@uKZm z0wwi=*0WQ&vc+V;N$CKoxX%DRsRpZ0X=8T}HE!?S(LcDSy{8X0&kn3ubX80)Y!jK3 zVC12(xC;WHa&7bL1Z_?w+PkpLs5W$>*!M#>;qEB5{V)t@H1+kte(@9x=NWLoouh0& zQQNLE;?zDkx32MgIG#Ao){PtTeq+?IyJ8K_0%9wDTP|ksb45)NnH~Qfs@hTyFJlwi z+myyGfHrYAVSpUKWE-K8xEPZ?*xrrU?Dv_Fsn+%+S8`a^Vavj>>&^S4v}u~F5=a>z z6-Szp3wkZ+?vChc=s%jf`V0X3zHv+(%{Vg2Dr%)4xIfU@!FfQbhX$|o1BJ4`)??Zn z7~ID04TC6^RFe|zd%d!49U6@F;}m1}FjuxvhO50C*;|aVQ>s2L=5ZY6v8i;btCjtj z`_XF80G4tLmNcrXy?To;-k`Vm;th+SG@BdaX)7MXZe8=vA-`C$1g1rWIwQ1YR4>xq z2a`9J3)sv;38F8WlgJ6nZ&1{nvvu2+t=VolaxdOzId&yGSF|>B3Dn(zO$>Bt-#qPY z*?1L=Wsi+o)2-OlSdV_GxA&SF(eFp@+G3%rHqa<&wOi$FSsB4`+Vyw(bb|XVnGHKP z<0)ycRMo2fBdP5Cpam?JZCv(R9EVonfC^odz_6CkvkY?n_j$)rXsYL6UM+e?Xpf*e<(wJuas~9YwS9|*+ z=oH*N;CT|}q!=1I9dF5+9@%+I&An!0eB+*t+k1y(Cpf!X%*oL-1om%n-i56LWn6Vd zVeZ3rLjKrC9qRQNt}*5JW>7GrW>6lYSbEb^b$M8r-c0XXuxTY|?cf2*$c<^Erm)G5 z!=W|{EtxQY@O$Gg2$9P1}alR*gPpGt7?M z5=L)rj&))8To!het69}RslsT^n*3;xo=u*tXac1;t!EWOJT`J;K~Ha{PP7xOP5pA} zr1HvcZF^G(t(JcE*96(k8cu?yiDcA{+>y>g0hY1@ zs8!NvTV|6+!o2BF~y*9oUM{^{% zL1H6UMRJOuj&Y22a{`-og*2_=Nt>FS6O|Cn?mjwm!b+{?ndHa`oa)#tP@sO&G3Ow8dga=hV9}F)`r2+yunCNycCWzv8gXR_NIBVM^@fy z9A%g`^)}qF=YX9Fy_v)f?d(w`m2k9K_hx;(?)6DocMkP!9?h|-dv_Q2O1P=cZ9X3O zc|~WnQLH64@~BbH9<*(RM-#v>53Z8x^bcA`PXRu)ljHzY7OC2#i)t01x{Oy|cJUZb zsO6)|(kF{7L+nE9625akXjCYK);LcBI5)R;dfB$NCR?HzbpK2Po6!iCW)cQP0vrEm zGQDo&_O;p#@pNCd6X5X;@7TS$h1)(fpc=s*6fMjgldo@{^K=uAKQr5K;>XEGpOwax z=>?M&qu!)c=O-i0F10GjYT_(6EqJISn=*TDDavrfrVs=(^5n>8KhTg?Y{jr-`iXi70LH3sN#t3*Y8%5h?DXbB z+PArYEf{L9j@1}e%I1dgPMxLJVm|(qnSrwwjJg=k$@hO$h0hLfC&y>Zj99L);!&LH zss0Sn$5Toc(FJ>ciLc9018~7{BP~>?>-(sfTv5s*r#6s-6r`0%(?JG30b#4)^6uUyk(UL|+c{ z7wN5bl{$_+bu(;bG@+|!59TT2I0R%4CzZ%yQ?zW)S6SD;ns9EEK8wk;#dV> z%`iGp89W{vzU8lfb&*v@3#eBy8lgRPZ;Z)KwU%*A&LQL&LO(wdldViG>X;UFOp7|U z$Z8p}yBBR%kFt4udaRiMY$xa$MVU9;_JSgp9jmB14P*<%(D_YO{UcUA`Q&vJpYe{y zF!808yE|5Pbgt>JFaxysS4%_vI|nyrcLSQSmxHI})X6Z_t2qJZV{b~~jmlOX*888^ zfr?ADU>fDImD)q`EpYhc5=|NZ;?nnQi|R3>@=xN-wFL^%oVlr!J$wx2ahU+ZrS*JtZky{72Negx5a}G*||b#YUmMl z5~Mc&aRz$;jm->jvhRER2%I;u#A} z7HV3-qXb&v$FP-?wZPPxS?zRUebOnO6Y94K&-GDSw8_DUYH#d*^yAE7kJlk-0%>c{6z6T-_*dj?5!l1Am0g`#ooaYe zyAe2_#p*|Iu6nu0+M?}UurPLaVNfgSV3!EIWHMVYQIMJyxY|Z-)Z3^S7hI~0d?bOr z&lHJmmS{WKS%KcIPIXM=Xcxr077IY7l4xAVT3at+vj(7Fv*1XB zc8FhXYWv10uB@8sDsM*Zb+7InJIF%P@5gPWd)5yK$rMDAnCBE=~a zlD2pGnxaedi*rdoGirwj!>}WcjUg{je+~G2C>P9lPC=d`G9{})jA>UL$}6kcgv8q8 zX3tY?#^_lHDwz?odv%=6yd>Py=CecU!RQfG^{8Mx8uQ|s2Y~jE#je4}_i!xhtGW>p z>WK|k>={GRanBeq;-TK`#?cmTR;agx&}_#syxLpz7|8ZTJo`HODNM8BnCgZ~h5o@_ z#Hi#-a6C>P^`w(G1F3Tl^AO|5yx=7JsuR33!AJs+R?7p7eE0`lK+GXNjidJWe2;zW z#V{U6P%~|+3l9sKY`8R1=CglGS1qjPc_$YKKDJHb*j7c%9wbvwQ6ZV#Mo&*??FT$% zi?aZ7k{ywz(e#n3JiU&YN=@_iSbC`X8A5hrAiFP+-4@7Nr}|+W9zA)ZSF*%|6mpk+ zZgbnv(9T|3YdnX_V5S`66PiX!Q~`X-!#pBk7Uwvw$!b8>-ULK(J`4GcIBjEZQ7TcL zpk%c{N^SjcHyi3Djz6Hek@>9`gtWzidGJ)>~>T4fYIo z{MEXLGsv@z=&lqr|?a$I1wrZ7n@@8}N47A*?%eK55RVZITjeqrO>@a(}}91{=q z9vqJB*f_BBaJ)kU8}SjmL<5B3tvh#Y0B*)E_izNSlQ|quFKr?LF*gtFnim-wh-_+@ z4@%GA#;u3<4DQ&qFtVeTR_mNiLj!X*4}>FI!jaC#a0D;)ID8`*h-}`0LmV6pMf7Uy z@OqH6nv76Q!nb*6A09vM?~4rKjXr$62WZ^k^!#2UX7?PF&C89V)M{-JadM)7u}$w^ z-lM@VTXduGO}pwj(d=Df4w%TSet>4ePHazv}Du*(prIT;yYBq zcBfCFdmNgyTC;n?z_~`VoPDS#nVXl#+tm`uJRD|XYO78vr?$Y;o$V?0yeQ^b?z?6c zlG56#(N7DToTLE^L*7ze?Z;xB3`-?zAt;Nt18ZEI_QZWFl@y;kk7f@kP3GAhtVaJ1 z7A#utp;)%KF=@SI@^?yWI+H8KOjn&88U+swWNW5uSij9^GQd=79^caSFaa&F;kaG6 zVH@Tw98$wV-ML-w5@Q!!kGX8K%R?L4wWzf`7CSUNn;IoLxFej{v7vVp&dkGU^KvSs zWXwya4*qzRgV*R3zov$=&DH?lL@RQEj2ul`OKYZ|^pXl$}m}qa{CR#N1%-~thCz;;77LDO= zjS8zFQ7*m~t+^PkBl<#uzE~t^=IlfT7a&FA1@Gw04{5-1^!IT2~SU|lo${#;}RQ!CE|L?sh=4E`E z;GlPp9vGCzi-{n{pJ|FYX){Fs;dI@GWierVd9u;0a%0FY2pBgNCIo3g05AGa% zfsAj?XI&Vx1mmGs{Ok!O=>MmRpDkB{{(iCesSirfzrQa20p-uNzAt|EkrKQ-RDbPH z>#P#=r{^S`da4BdZAVyKF;``{DolF&eofQS^wxMI2*!qO#WdmSFKrU)=tmT z^bvd3ub&mo`qf!j)~go&AG6{#+vlVHg3O#JnP9UG?D_dOtJoGk&_igD>s@g9P&6DT zf!X>Mr}VSU>0gGn4J@(LE1*fg9Bo4X5lpufuf-L7h-mUbIIqCr7J4CYv3}KQ;4nSM z1~Bm0KLQK%92;1u=cEAU7LJ<0q59Rbfr!M10;F~b0LKe*^abiItBTm5zrV+DBvJ8D zl)`4g<$@d|jCYh^k6^#xF2R!pKP&hJ!5alxU*_{$!FL4zA;`&$;dmv0LVjYG{&9j6 z1vv&tpDuW?V4dJR!NUZjg3ATl1yh3S1T%uYg2xFSFL;9B$%1DJen#*-!HWgIEcg|{ z>jb|c_-(=O3*IC6px|SIPYFIN_$$Ge1^*!Urr>*m?+fB1YD!*X1d9a63swqF7d%9; zL6Gwo<-Js}MX+5kEqJ8h2ElED1A-?Ao+9{3!E*&K6ueCED}vVxepB!^!5;|zQ1CIq zrv-l@_#4631ph4fp5O<94$LFgGhc9=V7cHl!I^>)!MTEm2{sG13U&#u5j1@Ls`(1%D#=jNmT?Ul#nM;M;nVJ|*~^;I9Q=75tOnyMpfv24E&rK6!#;1t$tl6+B3=MzBfnP{F9+3c*gn z)q?mev?^zl;10oEf~N|8TJU_q%LK0$yh-r8f_Do(Ecm40F9cr_d|mKe!G8+oN% z18x5?m~p5bO|KBY2G9Ho-x`lLXHa{G8w=f>#M%FLBWKz1Xl>I6Wl3yhTvs_HwxY*_+!Br1>Y3p<^{_cCs-}mBp4U$ z7Thd&g5ZUM`vh+n{E^`Eg0BmHAXtb+7t5V0SSPqlaFyT&!6Cu31TPl6Rq$@Xp9{Vw z_;; za1z!U*9xuqxEim1Mg4YP%EBIr<-wFOza155~Ojj;=u;8JBD+P}d+#z_1;CX`k1aB3* zU+|}buL!;;n1js>mOD|fNpP9qTET6CCklR6@N&U#2;MFDgy3%k-xdsDAl;4^}M5-bku^v!}P!A*jv34TuS_k!GjV1364 zRtq)>#s!ZN+#&c$!Ak_M6TDsUM}p4_zApHIV0pDJ_aMQ;1=k5~7Cc4pJi!|UZx?)0 z@VA105iFXn^REzW5{wIW3vL!XLGaUp*9hJ!_#?sJ3I0W}Vumi~aKVh=fZ(};UlP1k z@W+DB3;spWIY{R>O|V8VF4!%2yx=K#JWD)_A6n}V@f zI{kp)$$}RP-YR&v;F#Gu{&c~5!4-n*1dkOwN$_03>jl3n_$$Fb3w|Ux_F!F3m0+Xb zk%C_ryif3H!IuRK4iUKswhQ(O?h^cz;H83J7raC8F~Qda-xWM^j?RCp;Aw)F3w~Yj zKEbC2UluH=(dp+2wg|2f+$wm!;MWE35PVm#AR_q)whJCD*e`gg;4Omp2|g|Ovf#Ud zZmrI@R=Qgy@C$-p5&VJRqk=C9h8lD^(*@@W;xCz%{_PW- z09{Odyk4+RaIfGwf>#ROF8Gk(GlH)RT1`5?0>LuDnSwQfc;;S}yHIec;7Y+y2yPVI zCO9CtSMc+K7YSY_xKHpp!EXybDEOG*(}FJwz9slq!4CwTxtiZ%!79O7g0+H&3N9B+ z3-$>13GNjR9}@*<2rdwe3$7A8TJU7S&j?;3c(vg71RoK6 zUhp@9uL-^*$iqPPnIRWlLapjyhiXg!FvQB z5qw(kMZvcO|0?)T!J>t_+_2zG!5YCP!MNZm!J`GY3+@*Dq~OJZ*9hJs_yfU51)mjs zMeswx&?3!Ox!^&9comzH(^A1U!F7V01uqf2PVk$8cM1MT@aKXr3%(`zPr>{{b$Js7 zKM*WDOw%U|&Jvs}7!~XgJW_C*;7-9a1kV$^T=46Hw+TKV_@v;k1pg@bH^Jay&DS`= zse*F^7YZf>lY$w+?Sf|uUMRRv@Ed}62tF+MGr`{rzAI=SuK6hztPq?fI9IS)utV?| z!Oem@1osGjR`7hmO9ihHyp;%>YzCna7J7$@#Pe^bq5&EuD{9(a^iHKiE#N4}B@Cc!IiGQ8o z1|sCNS#XGm^m~X%e~!>UFLSLPYw51Q!V|B_f|T!SzBvM(}td^4TePy3jvGM7oQFeyQM9M9B3zBGyv( z3;iL%$0Yn&@xLJW3K8-DNMyYP-DXV>5kW5#oI(U&Rf4s|YJ47;hGO#Q zA1io}&<_@D68a*+4x!`E4^;U_34Md$kkC&MJVWT8CZe4$7W$V2_Yon-n}{LHx>NiQ zOZa1gPYV6lg0BnxO~LnsZZAhZd8iK&`BoAkr?B8bLZ2&$zcE(v@LC^*M-vf$gWy)7 z4->~&)|uizkBE2|3SKJo>jZBTykEi}5`13huM%C$dQbfJ3Z0)Tm`?=%6U0ARa5@p` z4kkjL^M!t>V3de-?Zh%X$0Po&624vVc%h#x{?i4|7WxI^zeMoMLcdP@HwxZQL^+QT z!Ot^7|ApX7g0Bj`Dfo`y2ZB~B(nFpu5&0B}zeKQth;phVyjJLqf`>_XRKk-&UoCi~ z&^L*HtKjiMKT-Ur2%b$ud6y9(&ufVjE$h4DzmEuh9~694=sy?#^Mbz?`s?CBY!mDjTqk%m5&3Kp|8auD#Q%@IcaM{D{{R2y z+L_sFrmc2&+IFX=v>i7}O6fp|vWij>LMTE=LI@#*5JJv5pF#-b7&*&1gbJH_u& z&J}-5{YmAE;%}Ich;`b?^7k^3lmiYV1mExmB%ShRi2@orkt+4QhAN?ZsmQ- z2R&{53ze@bKhpG1lq;31l)otdP!EpzYRvs@t zS$&G~d{0~MC7OPn_)W@tG<}}(S@9Q?Zz$hZF88$Mt?;z%{6+i^Wy#=pdrOshPaD6H zr;YC)id|3P` z_2-nYdD?Q{()5qTKU1#O^q-aC5F6jgu6JdHGOujoY0KNhvvVTRLwqac0OcU%9-cOS zglFeOVyyUhtd{+_t;})elpS zQy!~4K{;7DMR~3AM&%vKyOr~l4=bNkKC66Lxk$NO`ML5Jz@+f8Wx#?Dk#3|}$D$h|~th`Ja zeSX@;-=Kbn@^0k_mm$iKU4nUY0u|_RGb-QePttMm9nEU`h2v_7kxh3 zax3xZ^U>A^sE<&NR34%{TzRVU4CT4X3zRn~Z&A)x&QU(=*)WlKLAgk|Soyv(`W&>4 z`&m8u+_QCm4(jt4D;p@wl{Lx^%INdXHok{?^f_ni1J$F?H(MX2evI;X<+;iWl$R>6 zR7Rg`E=eTjc(;5|`Ka=BSij6O$h+i|}7ManCc*C=mM-mbh?IZwGj z`LyySuDtA^MtUOG4 zl=4{RB;{n~*~;^j7b`DQUZcE0`MB~a*zxSIK2W)ba&P4*yYvZZok<)+Fll)aSuD-Tp2rW~g{PI;p8bmdvf z3zQctXDY8(&Qi`+M!yGQ+y9{Y0_D@nmz2@(iP*Sr)K@FlDt}idOXY*Ip)#jzqHL~g zqinD2tK3n!i*i@xUdnxyqm^TnM=Fm|o~S%UdA0I7<*mv)l=mv@uWY7lt*lXQuI#QHtlUkxw{kz_5z3>KQ#|c;nW@SP zm6s@^-;c5B_o+Xud`$U_a-s4K<=e^+l+o|g*mAyB|4!+zh4}i5l?{~T%67_4l$$HN zE4NW@uZ(^V$CkI3`Y7c=%HxzLD$i41sJuaWi}E4md}Z|eJGT7i)t4%lDZfyDt^8j3 zld?fB-rwl=d~7*Q)SD~YDBCMHQ+8GMQ}$Qxt=vy}l=4{RB;{n~MaoN+w<_;YKB`=x zd_(!R@?^s_dccuZ(^_$&SbV>IW(hQ;t)fp^ScS$;Mx( zeu;9HGWtCxn|{CggUZL1Pbs6{Z?bVq)jv^wpI<MmK>3{VMdgRe<;owFKPxkp@%GnOHdnS( zc2o9LZmaC8+)KHya z*;-kn?5XUn9HbnoJV1G{@&x6{$|=gJ%4?N3DsNZbrF>HPtnz*3N6OEYUn&1o7Ukpp zs#G>r+RF`zqK^8W6MJ35aP)dgwWmGDYVT?1)}1}=oS~N84$An0mCm)<>w1RE}0g+ilY)s83W*QchM*QBGA(Q%+aT zP+p;&shp*pt(>Ert9(c~U-^Xc8Ra77V&xL$QsoLyyM9(GS1H#h*D8NkM(+>U_~`us z%Z$HHZdqShrmRp_E88gBD?2JXE4wLsDtjyYD5LigY(3HY2$loIhbV_BM=D1v$0)}t z$15i&Cn_f?rz)o@rz>YDulF>MZ&uDy&Q{J*&Q(64d`7uY`Lc46aAss zD`k5!+joTQwrjNU)7aZ}Z&DW@xED6de?RL)Y) zR?bn*RX(JguUx2nS-D8LSh+;GRJly~sd9yKrE;zEcV)ugudw|{DKpCY%IJGsF!kZe5z3Lu(aJH(==*YPzKQCSl#`WH zl+%?nlvgNcDrYHYE9WTZDj!nLS3aS9M!872Sh+;GRJlUAQn^aGM!8n`yV4(sqU%Fh zrmRrrmCcmxmC^f1c08i@ku1B3_fhs!_E!#64p&C+E7^R}`%0Fh#m9TvCx_W%Ru~)+^Mjm2H&ml^vCxmEDv*mA#dHl>L;^`&qX9=>06qA>zZ7!<8eHBbCwj z`Pld|>SL7?m6Mc{l~a_{l{1uAC}%3KSKh3gqnxXJNI75mgz_2XBIRP`66I3m3gt@W zD&-nw!rxD7Yxg(GjIzG6Oj)6LS9VlJ@2}bNqW9M<`-t~b4p9zM4p)v)j!}+P zj#o}lPF7A)PE}4*PFK!QUa!1aIZHWP`H*tH@(JZL%0-@btQISmc-nhUOO?w!?L7EX z+rAW@+m$@z+aiy*Joc_sJqr)K$+HY?*D;+k4tFyQ%l|v}N~G@9$~b zF-(29r)|$z_3@szuIcJCJZ)vs`LV5Uj(6M6g_{1dr)_U^9&6L1^H@KAetu-V+S9hb zqk3mg+mHV013hhj5}l4Y;fM*N4zQeXbev zb3?k}*K%$+y>Fc_=iG4Gy07Tma7z3|oiXLBGye}?D%#1u>3+jS#NX}tPgA0A`TVB| z(f56>zfyg@=lYN@`CPXQwvn&<{D&#};?GV;AL)m<)4%y1)Mx>J53Tdp0`v!~qv@j$ zI^bCQB2oJ`e7oMF%cBlB;OK*nOVpV<_Q(V4)=~DCybrNI(Nkx{|4zmpI_@BrXm%tz z9eCss{@0%C&UNt7qmHma+wD52)2Ipdhb0d}_Zl2LUza7>6SESO? z(#P3pO!RNVaX!ue)!6@x{r`94I@*{G*Xy@s{@LA1^ly9nS$EtB>-FPF(ND%5u)(-7 z*6pt3?|+Ot#Yo-dO|+i>dsO^7f!8bSf8B9@|1jPs=pW0w+j`w`Ug{nj#=XD6xNbIX zB@44;+&gyJ?!FRz?7#n;y*S>FjqS3%#Tt$Ce-;W%X`_D=kxpa+1={j%WJ*C@jvYN*|_U{#tp{pVyy1=Ev~b__7e5q+c$QDVdc zr?$LmTaNEb@{&+HdtOiTiz3!#{1F4rsKi88!Ye2eG&;j2jm~i z`+9?MM~$+_ygD}|#(iNI*4vMy0owuJk7o9t_5Ny@d3;^hoRCON_6z#Qw4dz4ddss9 zj{5D=m$#AqXL$|m05gv-qWOt-{OmgBAJeinuI}_5xvpyhSe0zSDskr=RriiI!F|99VDT*p`9@0eyJ zr>*R1&G>-B%z+PJ#=+q+$mSY+I{ubus8`}}nky9@9`8~t1QY9g^E#gavP z+R(rM|$d0n~B6w7Gj-?b}F{sxcW7AebiY2Df@^!cW zd;Pv`6|Y1qOn38Q(~e0TohX}^tWC5@RyP~@*Ux|cmEI{?eaV=GTAQP5aJ#Re{lmf4TSaRrnq%v+rF#0(qi*Z{za5{d9lWM` zNUP?lA74ExUPE!Ku=O)*uV@+ViC^lnZl4&tqsC@hWo<-0-aEh4H6Gj9j>#EwimH8y zc2uhqm-wZ0?V+`;o2OO}EDB}?m&R+WY}K^&jiXzSOwQ?S`*V{n#q$UM!TeRN3jcEc z#D6ee>zwH4p6H zhVC?$JDukh)dp=FkE}Pb^Ui0?NmkddZ93lP-*o3>^;Khz{NbacuZm1{=Klx(^w-ff zJ3qa4amz&eZi^DF+wRnEV55=kc4{}kf3_a!KTGWAzvKhk4e)W%n16M7P&=Davr~tW z@i@O0TTirWH#$;@_D{d=TaswMK>28t4}IbL>9?gsS!JK-@_+fqreCh=TU_hcPk!J> zYe!F>u{JUN%sEA?Q}v5h_iNa%cIjGse!ezUwsdW#dg()Hy*U8`Sn%(68xZWnVzhnL{_qTqVu)6*R`)g}XtiQ)a>-ISE zmi=D0&;PS^7yg5Fr~mD`|0maT`!@Cd?e$!|Zq4kl<+^?TpRBiEo05OK-tfP$-u`Xs z|8MIZ({KH2IrCpw@02zT{EbFJEl#;f4km#|AqBVZBzDd*IWO;u-=L` zxqrLf%KyrGH?J+(W#i^s)g~@V&MLaS+emk+XvVsG%c^y2{TKHg|C8HMMVrchyTAE$ zYySW3_S>vY{@<>*$-i0e|Lnf9(SLAX*>v5S|HZNXpRK#`f3WVte`(!S|G~PO{fl+m z`KX_5>l`IM12;3Hb9r*ry!y3a?U{4JUFu!A$J#a{?RVTGlarTs8X0@+XL0fQS{;r4 z-^KrT1pY@yz+Tdc{?&cmv%Qgi_P@XVpJM<0HHK&G|5W>*vZuEG+LVvqF#R1ttYdCy^@j4jM~Y@WL~m~>5PB%dvWGO<6$OgYtLl**ip%5+SoSM%RDy7-fYSo zw}b6^<^ww-4Kfed%To=m-|%*Va#&#`5aw%SISjO}$rrk=f8 z(KvIoy&Y7UsqA5|Yh}{5Bl(QK($ggKxE-senH%hltwLsUUwgSLv$MSlvQehFt))fA zHr8GxxUI;(@+EWdX7=JxW`A2k>&!;>N_?Bl7xvOz+sr<;{Lz_}w*3cX{1=fIX0Ef> zxL(Ng*u}m8DsxWDMB=5)U^{9rXZ-8eU&-8W*W0Vv-EHk1gY2_y?aVXC?rK}tDahW@ z)4ppf$PTNvj}Qde_ja~-yn?KMx#mSd_H3K^k|4Xc9rGDMwqaNMwx%GPv@N?V$R27h z+FWi!EUpN$x7#YO46^UqF}Nzo{%ME(>L9zH9oaQOc8x9i#~_=tqxVyg?b+FWw=Bp` zx1+c=$ogM_8D5lq%I2G2lzqOPeNRL(d!HS{FO%6;wtHVCvtQV@f1S*(wySt$GJDaI#==i45wPG*k{*|M5ji^HscjoDja_8N<~!|b!RfA56Z zM+e$#v|)CMt>Imp!LH4RO0s|0kcUgMT}te`!%DI(>|i?*x0Yu6Z)JBWjk0&xAvmW|cDBK?n(Q)L zZFx;LYs(y8m3?Q&MB=Eb?71ex(N)=3>}ouwD%;d<2NSBY?T6Sm1Xg7)v}GPwmF-|h z@c63i9hG*lsq^j%_8G9$WD*J&AIi)IlqltNH zRkqi*iNxfptbfDoX;s;2o7igvGqYdXRkhvB?8zPMPr}a3?q-Le-^}bWZ4!wcW@cZs z_hoBmX8YNW?Km_0t{v+kPiOrPlni}3d$x%(@~iBh=I*GkvQO9z{D7~r$J>qMz^}3w z*~rmfWxJZ62Yr?O$*zZkzsl}syK=}^^?tD}8*hKCu3m*%c$8l_z(hLQFZi#z9pe|S zvtuy9F9f#qWBr1E8tXW}(9FnWd(Wd@bK9uX{K6@Ai$2{iEVHdW!!K0Xk(}ZeI&7Ip zoaq*k?7I)@`R9->_6yJ00ldU7jJ7SD;TQVaq)Yw6rM6)w z*cT+!>tO3T(J%P72m9-u^|rC=Fz^e{+pZV+g_rFH=znCk-Z=9pn_Hn@xXKQD#xMBCMzVgve}A!_Uzpd??pOVS{{}>Tzu>>3)4(tI-^gef5xee7 z{X){#Ugj6J8fa?yg{SOV&iRFYcB^gV7yK3J3cv7xEwHg)=wbJ8zSZ^qu)+4njT80m zwe2bL3rE;0{7>W7`#S4;VHfr^+0%ZZsU5>&zc4L22uZuXqGMqfPO=+dk`l+JPRI-pUa^dSdt0CI`aCmg&9 zC{L6wbg&pumMHzv!P|faiPAqDyaTA8C_TZoMN|g4oyNC40fFM!Y-@$T#U1xU1 zE@+pYm9^_~YrkTj)D`=H-6^F%X;Lp5Vaqt(w zt`vWdHJzx@jmxeS|B!9E2oN9g&)cO7w!P&$bhK$JbjW{dX(d@x;#Y|Bay%=j9pEF{02(GrhdO8nu$xW; zdjv_>0PK)AcCazPZcEJ_Yyz;`Qd_ z26jC@Xb+_6tyzF+e~z6trnd#y@$BUP3t zdEZw!q$cSLtbeWz?QS#akuQAL<_i70WD~_3HymXXGV?oI$=oo=pNYL<&y9_fS38AE))TDzSlGY8maq%!{b({$!>JKZeK49odbwZx`2JdwJ~ zPR7FblD>|LF+13%gddcBY^8CN8k_J@sb5YsF1Ay|a9OE8K&Ki%Zc7h8j!Gs`neuH< z-C@JRS*7v^c^`}AvaTN_r@Ca{yI^s{y` z?_V1q76my!t4QQ8u@mbs8RUFYD!;e4RFHei+LZjszEkNS_nEb+`8GaZagh7b+Kl+> z@nO-`b86guVASnT-1{N$p;0f1PfXHf>a7z^`q{B=AB2CDZDugu^}piX$Va;#2BH7L zbShD@Lnm8tCP@0+RWpLHVURxBF2*}jw%(4Evm?>Q=7O9LoD#46bh{XBOy5M)0VdcL zL0A%$`7ayiqXXX{sJr?`LD<_S+3K@)N*q=MNuR%}O;Ol1NSB$X@#>qcxBBKm&L^b` z(Q(`;K8~rN5FN-C@qx?)g=pid?tSEA|db~fI=D69&~2KtJkt!uL0 z*0l`6N8_y4`o7cc^QoVzuFTk(7?Su3yK2vmf`mMKlI|MnOq|K|vVK0}Ubg??;Go70O%(h~>%t*HJHNGD5hO|)S6Uw$B&%#_(|zqnpL94Z zC_ClvIrj)^{Myr;dj{mHawCevcT^MMg=*a zl!|xKe|i5grkg9pTG~ zj?|GsYagD-M@MRW(8@Qhf1)I54}{@SL2`SW*nD?8zwH@L2+D5p`J(MUZoTy%A2jqy zTK_z|7_Gm4qU1w+DIlB}Bu_Nfw6EPl>=t@bQ1o@xigSo5B?LH)whgR<_8*`O)wE$7TYcjqO)*^}e&tRPupBb%RVPlx-3=LBWr z{+{o=_2!%Q_k5qYIp+t-zCK@Xdk~!-P7lhywzkosqZ8r9K_Pm;$=~RYua^V`e<(`j zSKH%hI3u3cKmUf`2VNQ!+S$!%VE#ux6qf}BU&e_1k=t9lJf1cw-^gyI;T1u_@BXL7 z;{0aAqMdJ%DA~5gCSMsOPx6iFWJ{YA&J4wo9*^6Icy$Zn)s3|8j2&b%J`p7SkApVfqK&=q z7(N}8m6&_co` z6D4B@*u+4l=)u*jaK&ttBd4(GpP1+o>YE;%^WU{SKdE9m~X`+ z7se}pJ8mz>t9vJC=&M_lDEY+hXTv2yGH)wr{#8>unF`+z%F?#pXmua3x>NjI=fk+A z^5gwp`lGmI@)!8DWpS$?ui)c&1!eg|>@GZ99=G!R@3vFnCvnT=e{?%Oja#EcNzQN1 zp9M*OCA`IHesz5vG;IF19o8WHHYoEuhW!5aa$2}5DEHG?dtvCljjgT@k_DSq>;szq zVKuXq)^Ox{5`MtVYt1Qah zY^{FY|Ds2@QBiJzwX*yReyeF0w~GAN?W}bv%6)0m^7$^lgImX~S$^L>)&>;i8rZpN zbw260?cL+nChxyh6OJm%b+Kvf^M~3AS9nC+I_6)rlj`vJqTEoM);a%+Un!>-<&L%1 zEkClSweyQ|GpzN@pJTVZ@UnPh@BHmMS-T+~*(ZOm@5AhPWWW4S-?Dk}$o~13ei!vb zJaS;Z$`9{L@yH?h19!HzI377HzpFizg&)NuhvzqT{lAJwj>v!E_cUvYa`)S|jLe_h z)>RIa;kDQS2=Z~!2$XWS=J6T&CkDQ%9&2P2K;$_asxAfz(G9EcM-_x(ZU*nMv<#)HosW41M z%bcHo&>ptKs#NYWTf-CigM9zmq;ii~dnUi!k5ZRZ?h|VZ^WXd4ZWoVyIlq^=7w!^| zT$KOVAJO-TM=s9)?)U$P$0L{IPw!=IVmxwbew^J~glEPhm*q#gXP3q!Kg|!e7pB7- z z+JuUr@Sxx6D=>H`v-*veXZV> z&aJjOFer@lJIDLexyE+?G9)PMV-YS$=ll(+VL@U4l+~BgxqYn;4+@w2?!S}Hoo01} zJy!W~{v@5d#p=kQFvzd2Z_~MFtd0%}v;3a!mvrtEt7C$~>%OQ|ajwWVcC2l)dsbSU zYiV_SP`K8&s%deqkJSl5;pLsIwk^)>Z*^i&IMW5{Qk*-->ZG7B+E>)OICs0%$w6V2 zsT$T6=N4L>5)>+Sv^uyrx7_N~pm3Kx-i5>C!PA1m0e(+*Ks_sd_1mmgTflWH+rc!H`L~RC@5U%bxB<32Zj552S1DJ6G35_ z-w?i!>oY;&RKKtMvp9F0&AZS9_N%*I7}b}9!bvWFWn32pg>paat>U^kD75walTKmo zQk!>4P`J_SmT_Gg6#N_H!`iqmvs;QiP=~w5_0ynmz3;+)VeS!|cZJDNYxVFjx5Da5 zyV3ch-brDu+#W1f1%=kW8Rvw#&Q{mhRpu+YEX?g~b!|}S;dcqM!raAHe-8>D`F+=8 zVb0&`N)#1t@jZGq%q_K=Dk^;95`Gruni$R$6}IrZuVf~-kJb7`g`k1ed?tECEh{Rt z@`t~TGr1`?wW6pn$#2fRGr60r=8Foy`X23`$$e$DSy5rr7FLhUp*3#a@_q)ZGqwPncGL^G?lVYcpsU7^{e$hog zD~QJXIY2btrXOjSTlqpNQ&X6JtxxwK1}}?#UdW_}eUksMN&eiRGIa-&KJiKZYFPXu zsv7CfODa>(GSbfwqJ^~drN@`Fy6+g{X9{)3M4P0gHL^+3e(daHq92;#PcAA`J(%w2 z5b^YNo8@b?F?%w`&n)VU(Po^)WPh+u+Sd>T~@n zh^_~1xIeL}Ozp?q{(v0Mz5a&Vn3;_6hv_OwkT^f+GT&3T{qcgY|oUTKE;0+^yep)sqLBM4}8(2^$zvEO!f!DI+G>9BqrbC zll_M+(qD--SLWU3(jnezh+aJdYzF?>;Z7Yk-jqz83DpP|QdHFw#bY^4x<+RGw35J>)%qkWx`(PnGp&y4X?fI4HM1FJCw zn-uM@pBK~_6CEgx*_JVWvQTGCwBs6cAY=RtqRyCTmo?^W#`tMPoiVyn?_{!{X4ILi z>&O2HeYB;1+EHh+4)vEz_S29$lXZMEMx(j?w4}~tX;Q;vKTWAKS=V?ilh5$U8#w9A zt`UDCU70$FkvI9s=!d5JQ}D{vg-rKToOpWOTj@Pa_EVm9lWoRVnewww@gD~L#k$JW z3MRF*2kZ^E&Y6wz*X}A)Nh{G&*!dquIl%)EONe!)Tz^{VfCiG$kGw zjnU*PqtSsF_V?s`|yQ)zP^i#6v)F=L-ojI4uev0;w%ZU~i9mBs5WPJ7#P0(U) zXEAlWVDxlP8e@@bWLdTjz&wm46xJ2Yct86 z{B-bOBYImj(>J)#o+4yAbhT?Olic3l9DQyVe{=LhJE2Kt{OfH~nLAPmdvmnZmQkD; zXIFff>0wV`GMV<({yEkfJK3$5>0?)TN#<625utu&?Pm5OZ)R^h&251C(O zWtm*s-W$%GXV+^kvyYKRnXT-er6N;p&omlm&a$OdX8aGFRAnv;?bJAPfo)Zjj6IRG z&$0Hk_rVI8*K6$@In#0nfBCa`u)R{3nb*fZ&Fa72U!C#SDO+YPx3#y*+}z7Q&HAb> zvrT3r+lIE8^K3iYWu|wxFNw(bpEYQo8EH?4HqP8_e3MMto`ZErgw6c9SM} zZPl5+Lwx7Iw+#w2>79I6f7{V_^)B1J`kAHCuCD0jyZTsv-_=*`(3E8s75T1Cwx797 zp|kJm^Y(yRkvYX4)Ej3`vO`>%In}O=s?70r@{`Y8X`9|8)4S4l(!ZOySt2#pwkUH> z(yyNi|1;sK%(SxYY>OKED|?v>;x{N0sR6d5nG2KcY)b2QeU{7f$Jl^2scgISUbb~@ zx9^PhTN6|m&)pq+XiEMk-jjV2-$Zo9K+-lcEb`#ZRR=Xv#9aIZew@73=sy4OS zJ(1m1wTaapiEJm;yw#qG>}IM}R(mC~omDHXcCpRsqTblMZP(`N72a*bx~ezwZd=w( zJ?GsvZ432s@3w8-)yurw#`RDy^=@0&Q@x>g+q_=t4ZPd-ZK+=0`sTKMTd9|Lx9#h# zUeCL2-`46`@3wv0sAs&}_HC;kdbjQCqh9RYwr@N2w0GOS?bTD>ZTtGFC%xPD^;0jh z-qp5m2lc?aZC|arUDxeW**3|O?E0@M^s`%O+X@$;W>`JDykoeR$>N6WoIc53AB+qc zs99ymAXOQ%i>eG6tSUo>sLGI`sxo9(RT;9Istg&XDnoWx#gIMJF=S753>mJDA$zG~ z$lmH0vX453j8Mmrebq5!KXnY*UmZh6s$<9~bqqN`9YYRO$B@zL7;=z0h8(PpA&01A z$QX4DIaD1(4pYaF!_{L$1|+Ys>%Zm-yJyet6dQ7<-IHd=hHj1MGC@^_9IGlrj#HH($E(VaiK;T>1XUSwqAG@*q>dqz)G_2_bqqO09Yao4 z$B@bD7;>6AhMcaBA!n##$P{%9Ia3`&&Qiyav(+(Vsyc?8qmCixs$KHOj9YfAn z$B+xuG2}vZ44JMT8!|4rz^?xq|Fe(TBV$9(w<+0+LN~_^xir0C3mI~mW|bkAtICio zRAtDOsxss%RT*-%stlQ_DnqVOl_A%v%8=_+G30u647ouaLvB>Zkek#oKHOx9YgL?$B?_#G2|X~44I>jA@{0d$bIS%V3{e`J{v8*;6k)ny+D-5fXMk@UwsWXPkMRff!0l_8I*%8& z)iLB1bqsk`9YbDI$B;$p81lM0hP zsmF#ql=R=PsJY+HwzCh%hAe4om){TF95>{nbkd$UM2|AdG^-5xSXG8BSCt{3sLGH} zRb|L$sxstrRT=Vystj47Dnq_h#gMPmG30A?3|Xm;A>XKD$hYbk@|`+{tWw92)#@1X zy*h^cppGGH)G_2obqx7Q9YcOr$B?z^81jochWx6IA-}0($nWYH@`pNx{Hcy1f2qfY ze2{Es*MH52L(Pg0BSXq}u%|Ni8$F?`V;`Z;rh@d2_9UpiKbuJhn!AN{JMAr|Z)Dw0 z%R_o|>vme6p*OQ`r{!6C!MdH6*P}PJZl~oX^d{Erw7fn&Z{1GI8_=t)+i7`2dZl%L zUQ-Ha?7+6L3{c^~HnAMg$boHR4v=$T8`%g@?!dOP0#N3_HnTCH)PZehC7_`L+t4aN z0|&OH_W79jiC}#L{tTxHpu~Y~X;VNw2ezdJK-Ph6X){2^fo*AXKbR$5q1KZLT zfV2bK(rQ4;fo*9^K+=J2X)8dH0e`O38em_S6+PK$1293#QrV&)Io1Rz_rENfO$M<= zZ~G%r+aPqk+@g(x^!eM!qD`1z7ImP@qK9VLR z9gDgFuxJYa7Ig<;Q4atX^#ov1F8~&83BaPQ09e!;fJIvauxJ|q7Htc_qCNmD+75t4 z+XJwuF93`B0kCKX02b8(uxLjB7WD^U(EvbfQB9D%&jcxN*2u(ZFN;pM7v-`$1)=-p z7VQ$G-|Qoc1~b1b8bX&vL+P?;SGp|PjV_CZ(Ph!@bXl|qT^8+0mqo+rShN=ai}nU! z(LMky8UetfeF0ds9{`K?2Vl`i02Yk`V9@~pEIJT?MWX>&bPxcG4hCS+Apk5I1Hhs~ z0a$bx0E-R>V9{6r799b=qH%!OqJcqjtqD@z++P374w6Mx_JU#d$RKpT+@fQGbd$ca zXae)gqGRc@=s3D8I-V|zCemfm33OR>B3%}pM3+UA=(6Z!Iu@M*z@k$DSTq@cMW+F< z=yU)UodLk2DF7@w6M#i$0kG(702WOJV9_}MEIJo}MdtyqXc_>E&Ie%81pq9%5P(I~ z0a$bq0E;dLV9_Oj*dqI&`Zgv=`TSxN=V)21NMYjU5=r#Zr z%>rQ2?Eoyg1As+$07PMRNdHbT0sl?gL=a{QxYQ3&5gz04#a{ zfJF}iu;?K`Y|&*wa*7F3?tdXSd$}x{Z*Nj$9}YtI%Po2=NZ(@bYD5-2&it}y0bLe7 zL6=2O(q++8bXoK?T^2n0btP*02aLqz@qm6SoA&si9S}g9gDsJV9~b#EcyJd#-vhAd2LKkW0btRO z04(|mfJHw8uxKp+i+%xM(XRk3`VD|ZzXP!74*(YZ3BaPi09ceL(z8h{3IJGC1c)tK z79`7dGK)U8w_md#%c2qf@MhoHm}dURP-LYGDL>9VK+ zT^2Q@%c4@cEGnbRqH;PG;+MMVm6eEb2s;MVrxOQD?d=>Oz-Ao6}`cSGp|f zMwdlf&}C6~Iu`W+U{Oy17WD#P(Ut%#+6sV0y#ZLXH2{mY0btR#04(YQz@qH{ShPI= zi~0hvs2>1}b^u^eEdYyl1Yl8r02U1ZV9`zhEZP}>MFRn`MVk~QXPO}8&-gR_4zlQN ze?%Kp6uMt-(a@swWA@fpWYMn7FN=1g%c5a)S+qM{7VSZoMSId^(Qvvf+KVoW_NL3C zedt&;0)R#P00Li%tVz z(dhszIs<@3Qvg_WCIE}h0$|bE04$mcz@l>iSadD`i_QaJ(KG-Soe#jG3jkPjApnb} z1F+~K02W;gz@ke4STqBGMVA7w=rTZT(S)L8dlRI*Wx0uStSo9`zX+1OyeM?P+@h|jwGhG(lLdT+80a$b!0E=b; zu;_LG7Tp2BqB{XtG#h|LcLA{IZU7eD1Hhs=04%x}fJOHKu;_jO7R?1<(L4YaJpjO> z2LV|05CDrF24K-604#bG5L^@U1z^#804#bRfJI9ISo8q^ zi#`Nk(MJF*S_X(Mdb}t(*90lw(SC6>yFeB_;wMQT7lrPZTl85``mMcW(dW!Bi@u=C zq7`&m^d(&ueMOf=U(;pLO1doihAxY~rOTr4=vcH0fJLhTSoA#ri+%uL(Ha02{RqIK zp8#0&GXRU$0802ciUz@py(SoAvpi~ay$(VqY;`U`+XiKL#kV^ILWq9OnmB>`BJ z0$@=Z5L@&~QSw(4q`aAZ6gm5;EZWjOcA70thVGYJR4jF3eo%rA@T(`8Wux-4o) zmqn#?SyV=sMdfr^l%va{Ms!(JLC2!T04%BmU{MtSi}C<0Y68HbrT{D|0I;YT0E?Of zuxKLy7PSCiQ8fUIS^}`B6#$D`1F)zK0E^lJu&5mXi)sK^)EqU`}#)E9t7{Qy|B z0|1L^0a&yn0E_wquxJ1Pi*^EF(ar!Y8VJCmK>#e;1%O3^0kK7!CX;8GAmxA9uYYGd z$)Z~Om5uC>WaxgmMZ=Qm+eXTw-I-q&?Ln7Cd(vgmaJnqoi!O`yrpuyz=(1=8T^8+2 zmqq*0v1oq)7L5d8(I@~G9RR?h0|8hx8h}Ly0kG&`02Unrz@jk#EIJf`MTY^f=x_iQ zjRj!Q5dbV22f(5u0a!F1fJH|Eu;^$2799h?q6vW5qFs~8mraoJWBsFxyUC)({)l#L zGIYP(q7#zoZw`<}Co;b*I*BfeCedZl$#hwC3SAbRN|!~G>9XiFx-2@KE{o2fW6=}< z7M%&eqO$;4bT$BsrUJ0&8~_%b3&5iD09Z5)fJNs6u;>B+7F`IyqUiuEx(I+p7Xz^9 z5&#y>0ASIj04%x;fJK)Bu;>Z^7F`L5Ejm7#%pGVJJ?C%0PLxGQ*gGHDtCFGnWOBF(Qr_EsNi%zmEPB@80a=g?-7mN3>16tZLuAo2 z%rA?crOTq{=(6Z}x-42qmqjnoWzmatS@aTJ7QIZDMX%7Y=v4p~y#~OdMF1>%9e_n| z0I=vy02VCbp%p8#Tuo=hgMH9^V`sWEY$l0^^M@5g38O@{85TeKpXUT~-^`jYu&(N}a? z^fg@;t)$DMZ|JhXzjxLK<(PhzUx-9yhjzvEJuxJeci+%)P(N6#@`Wb*lYXMmF z3jm9L1z^!{04(|)fJJ`*u;@h`n5de!?0I;YUfJH3< zSkwxDMXdo?)CPb>Z2?%+4uC~904!<`z@m)-ShNWMi#h}hS z?Dy}p^;7XP{nHv)>68lHFSls(RC?!evZyQb%c5>{S+oUR7Imk~q8@Zv)RQiYdeLRk zmULOP6I=Z4egG`m0f0rd04&-OfJOZQ zSTq2DMLPkoXlDQx4Fq7(AOIHa0>Gld04y2;z@ni5EZP+iThuv~9B+b@Z|fh}?;?xF z_(#@uONH*2TeN2?ebIPXG@SWm(Oz^}v^QNA?L(JEBj~bdU%D*Xk1mV$r^}*|bXhct zjztFmu;@Sl7L5jA(Ln$#Iv9XOhXAl>3;>G`1z^!(04zEjfJI{gSabvci^c)4=tuw- zjR#=SQ2;DD8h}N|0I+BR0E>fJIXQ zSac2mi_QgL(RlzYng+n4^8r|N0RW3G1Yps002W;Yz@m!*Sab;hi)H|@=u!X{T?W9S z%K=z)1pte#1Yprs04%y1fJHL_u|+4QlE0fE&_W`izegGED1z^!U02Vy}z@i5MSo9D8iyj7G(IWsXdK7>~^8r}&7yyeN z2Vl_x02Vy~z@jGsu|?OVlG~dg<+p8b;#@C_w%XXrQ>oDXa*Lizr4Kw_7Cq1WvS=Y) z7QH~1MK982(Mxn$^fFx*y+W5ouhM1FYjjz(h>k_C1F+}~02aLoz@o(fEP4xoMQ;PJ z=p6tSEdgNBy8tYD4}eAQ1F&c*0E<2VV9|#FEcyt5MauwK^f3U7mIJWp695){3c#Yz z09f=nAhzh4RC1~bQa;nZvm^VgEV{t&n7&Ab?w4Eibt--P39@J<^UI=d=(6Zrx-9yR zE{j&tWzlN7Ec%`PDVA1aYEcye0 zMSlXY=q~^kCDMA@jzs|gi;4hPlmuW=3V=mv02UPkuqXszQ3ilTSpXK*17J}JAhzhs zRPt35qH#3@b3 z&-B;$BU+bq=zh6HTcp!loFa?5GruhAL6=26>9VL7T^4OgmqlCAWl?XsEZUkbi?*T5 zqHXC|)CYh?+X1j>djJ;o1z=G>02b{4z@l0J7VQYYqW%CZ8UVneod8(0GXRSQ013V9{Uz77YPl(NF*u?Fzu6-2hlL41h(u17eH1rjvV{Am!b6HgUSiqAmR-X^(X1 zez`?^r_(1*mPPw8zbqO-mqq*1Wzl|gS+qZ07LBCKqEU2NbO2oz9Y~i&qv=?55CDq~ z24K-404y2A_L(K&Q1Iv0RN=K-*28UTyV z2Vl_!04%x?fJM^*SacBpi!KIW(Io&ZngPI~O95DP832ne2Vl_^04%x^fJIjUu;^+4 z7R>};(KP@px)y*%*8yUSPEIF3H$lpK*cUfvPmx8-?aN@Z*QZ1G%PqP&oes~GMYk}& zEV`90i*BRKqFHoVbUR%Z-9eW{chY6iY`QGEi!O`qreo1P04$mVz@mErSacr%i|z+t z(Odu)%>!W30{|>~5P(Gw0kG&{02Vz0z@kS1STrAiMUMfn=y3oREdXHA696oF5`aZd z0kG(402Vz1h%LG?o$P3Wln?4>;@l*QuJK2-XVankK02VC+VA00_ELsl0qE7%=^eF&~J_BIU=Kw7F0)Ry;09f=T zAhziFbn<8uq`cg}N^PMms>oXTDjm9CZqc{t^d;xWqVJer7OkSoqSbU+^gUe`{XmyR zYv{7*N4hNfi7tzNrpuzWbS(M>fJMIou;@1c7X1#uqCWsw^d|s|{sLf8qF7Jcu_ypw zQ4s)(k^n490k9|yz@lOR7KH#T$^ft^3&5g!04yp2U{QSl7Bv81QA0p%(aLo4ArqwB z|D;6r8(GveX{EF{bidr9M#brO&yz(J%rA=?(`8X5T^3c*Wl^3ki<;17QB%4sD$r$7 zGrBBlPRF8+09e!lfJM~+ENThBqE-MbY7M}mHUKPY3&5gw04%BjU{QMj7Htf`qD=r; z)B%7+9RXOhDFBN)0kCK@02XxyU{MzU7Htl|qOO40qVnS8pC(B8RxVDiIDV$z+JCFD zTXE=qxkWvT(=9HLMZK6`7HvtFMO)EjQE$2|+L|tlwxP?SZRxV84_y{*N0&w0)3K;8 z0E_wouxJMW7S#fvu>dSO0)R#109bS+0E@;0u;?fN799=1qGJG9Gy#A`#{#hEH~?4*(Ukx!x(a|rR|BwUCIE}B0btR!04%x=fJN5> zu;>N=7TpMlEt*`MTx5cjpW<(NoF!W30{|>~5P(Gw0kG&{ z02Vz0z@kS1STrAiMUMfn=y3oREdXHA696oF5`aZd0kG(402Vz1z@ldXSo9nKi=GF> z7Tr>uti04LI>z6Cy;T-nT^6mS%c5WC zvglX3Ec%U(MZW{E=nnuE{RzOLzW`Wde`feb+x1j{MF9YdiU3%Y1Yl7LfJJEl7TE!g z*MdbM0E;pJEXo3~s2%`|N&r|?AAm&-09e!zfJLPMEGh$FQ8^&C=)2h5mB& zDp|DYE>?13=zh6Hm0|knt7TCY^UI<7Hvb9McdM4Q6IW2+Kw)Zwx`RYzI0jCk1mULpkq-j0E>16 zU{QYn77YMk(M|v?+8KaF0|8hx2!KVq0I+B<0E>nIuxKa%i*^NI(QW`N8V10k-2qs% z2LOxq1Ypr{02b{9z@ohYShNoywy0N_>|}zJ@9v)r*-{q0=D*cAA`IOxw`gRT9(=tl z8pZsw=m5GbI*=}lM$=`{L3CMkFkKcMLYGBj=(6Zgx-2@3jzxz9uxKm*i;e(b(KrAW z9SOjq@c=A33V=mN1F+~A02WOEV9~JvEIJN=MaKiMXd(cMP5@xhi2y7*34leD09bS~ z0EGjf04%x` zfJK)9u;_9C7F_|rqALMdbQJ)Lt_EPyOaK;L1Hhtd0a$b$0E?~%V9^Z#EV>bZMK=Mk z=w<*G-2#X$IwMRzVuF+p@b}TC$fA-8E4PNB`{fqh5vJe2Sr*;N{IX~^T^8L%mqmBe zWzju!Su}?(i|(b%qWkEw=zh8^noGx`c>pYW0Dwgg0I02VzAz@kS0SoA0Wi{=Bc z=rI5mJr2O41pq910)RzN0Q02VzBz@ldWSoACai=G2u(enT-S_r_R7XVoFA|SSC zR+voOVix_hjfr!+EE-*H<)tumzucnN!gR~qWYHq#mqoABWzidSS@b4d7A>aBqPOU> z=xw?zdWSBHme6I)6s z4S+>k0I;Y#0E>D6u&5^hi+TZKi>floH%yT7wEqQ%d?tRT|GR$+)|Q#j{c?-8$)ta{ zOBQX*{IaMIT^4OemqpvtWl>+cEb2#>MLW=CQ7v5-?MRnJ{pnaV0Dwh10kCLi02U1d zV9_7|7VQGSqQL+x8Unzgp#Ut}6@W#%0kCKo0E>19V9_1`EZP%*MZ*DDv=;!2_6A_l zJ^(Bl0l=bt0a&yjAhxJ?CYit6EE-vB;%qI87H(-}|4it9xkU$N(!J)$qS4GRiw>g8 zqJ!zO=n%Rr8bg;whtg%yVRTt^I9(QvrOTot=vXukfJH|FuxLC0i;e>PFZRv?Jc_gX z+cQ}{i5(-IhC{SWRN`Mf-3JnkfgklZBTBy5Ir7bOWcXxMpcQ@+#*1mJ* zIrm1OynXfizt`1VeY*3zcjTEf_dGKz30PDMz@lXUEUE)w(Q*J5tpH%rN&ptE0$|Z< z02b{9z@ohYShNO!MQZ_Av=0D__61f`7M%&eqKyD7 zItzeBX9KY48~_%b3&5iD09bTB0E;dFV9|vDEV>BbEIOol=sXc5D#=Sa)GYd-kA#bx zN7OI1=_`>!*Lu3&ky=t{C#bQRewx|(bjT|+jDt|gmA*OASl>&a%(4P>+EMlu%N z1i+%30a$bk0E=z~V9{*=EV>#27JUl9qR#+W zvPR+=I+4wy&SbNw3)w8{N;ZqSkIJ}}od8(W8-PW909cd-z@lsb7Ucl2s4oDE`T?-0KLCpc0I+Bv0E-3zuxKyjRwJ0|!{QB)?Q69^iMfqg2 zsDNx16_U-OQDn1dG}$Z~LpF*g%2*9FJ z02Y-2u&5k>MHK)nngqb2$p9>x0>GlF04$mYz@ps%STr4gMKb_cv^xNcDgjtD6M#jt z0M4Raii`E0M=u`j}od&?7(*ant0f0qk0I=vx02XZoV9{9s zEIJ#2Mdtvp=v)96od>|8^8r|N0RW3G1Yprc04%x~fJK)8u;@~Nv*_@o&@m!Nbgh1- ze}q}|lztp?SyDv(Qj4xi3SW7jS#&kan?=`<&7y0`X3=$Iv*>!VS#$&0EV_|w7TrWP zi*6>HMYoW#=vDw0-3Gv-+W}Z~2LOxi1Ypr!04%y2fJOHJu;^X@7TpKHqWb|@^Z)>h z9t2>~LjWv#7=T5O0I=v$02Vz4z@ogijcgYEPBx3YWP90d7WrheD1mGig~(=6Gcp#1 z0a%m>z@i8Mi<$$lC<%Z?$p9=$0bo%o0E^N9SdH6$H;X!v&7#g^v#1N%Eb2-&i@K4`qV8m~s0Z0B+L3G)^(13aCIE|i0kCK%02cKI zU{N0c7G(jjC>wx9IRGr`3&5g&04(Ycz@h;FEE)*FqCo&G8VtaqApk5I3c#YB0a!E) zfJMUrSTq8FMY{l;MeUPA7l@M- z0)R!609Z5`fJIXPSTq%YMbiLSv>O16rUS5O1^|n82VhYp0E=bL%fcf`7M%&eqKyD7ItzeBX9KY48~_%b3&5iD z09bTB0E;dFV9|vDEV>AQMHd6G=n?=HT?)XW%K%t(IRJ~U062?|N)D|OL886&TWUv} zMWb^hT$vnEzto~@lf$PzXBJ(@@@CQXWV7f7vRQN^*(|z=Y!=;2Hj8c{n?<*h&7#}L zX3_0rEV=`LMRx+Q=q>;j-3`E^djME;F93_~17Okp04#a{fJF}iu;?KG7Cj8WqDKH& z^e6y}9s^*};{Ysr0)RzN0Q02VzBz@ldWSoAEwS#))B=nfGi`h|X`e~no*Q17mv zOOB{tYSBx{;Wu9}i(Y1Vv*;DFS@bH|EP9P>7QIe3i{2ocMQ@VLqPNIq(c5IR=p8Z^ zy$isi_W)S*J^+h80ASIF04(|lfJGkzu;>#27JUl9qR#+WvV9~b#EcyQ8`&)CPBx2rkj18V9_uD77Yhr(Fgz*?E=7} zkpL{p1z=Ggz**EWC3Kt!65Ux}+;>WGuk`QURYHDBMEz2WMyG_Ye%&k@!}4ZP5!o!- zm24J`C7VUXWV2`-*(@4QHj5^Z&7u;rSu~N1MWp~NDg$6qIRJ|)09Z5$fJKu5STqHI zMNT_|CGN<{rqix#GYe|Xa@TEy~Z(PFY$w1jLHEhU>pdy>tf zTC!QRjBFOwk?X3>dcv*;wUS#&blEINg37Of|n zMW>R@qSMG`(dlF?+5o_!GXPk0CIE{z0T02ZAMz@l>iSadD`i_QaJ(fI%@x&VMh z7Xq;8A^;X$48WpG09bS>0E;dIVA16OEV=@KMOOl_=qdmfT@7#+9h(xGErLXw>&vp^ z%%X|_nMGpY5=s^G$Jp{m_hXGjh2mp&71z^!*04#bO zfJILLu;@tu7Ci;PqNf2^^b7!to&{jha{w%Q9)LwJ0GvhFrGzdLL85nVC*oXh7JVqc z5|Z>{N<{rqi(X9$Km37N^cu^XMX!_1qBqE9(VJwm=q<8Y^fuWndWUQly-PNW-Xohu z?~}3U0{|9%2*9F`09f=f0E<2WV9}=lEcy(9MVkOv^f>^Fz5rm+mjEpK3V=ml1F+~D z02X}IspS(HRJi;~G$lmft_ zQ~(yG0k9|?fJH3;Sd;<4q9_21VgM{^3BaOO04&-DfJLnVShOtwi?#z`Q5ygjZ4bbr zwg4<@2f(8C04(YNz@i-hSkw{VEcz`a)L#UN9@kaG`Q0o!Mz3g{QX}e@TGTByT=A({ z)Sczcq8?KA)7^6WGu=CU{MYLi~0hvs2>1} z`U9|N004^y0bhEUExt(IfyCO$K1m6aW@Y1z^!M02b{A zz@q5@ESdqpqTK;lR0+VMnE))B1;C=&04%BkV9^`^7F7eVXf6PY<^iy1J^+hq09dpD z;4B)G8oEmaiH_|k;uM)h&3BTpM`}dfJ?GM1B0{~cb zAOMRF0$|a>04zELfJKJ_u;?%V799@2q9XuUbR+?1E;XWlsYNHIhI@Q%7M;ZMX3@!Hv*;AES+t&P7M)5qi%uh(MW>U^ zq77uT=nS%1bS4>#HUhBdEC3dr4Zxyv09bS`0E^B8VA1&iEV=-IMHd3F=pq0XT@1jY zO8{7ODFBNu17OkR04%x!fJIjVu;?lP7F`X%qH6$HbS(gjt^+uWj!z90iy+Z;y+oW7 z%%TGQ*JQ3wji_I0(aovhMcQ z02VzBz@ldWSoACai=G2u(enT-dI5k%F9NXWB>)z^3~(0Rm>N1>1c{#2NyNFyEE+LH z!Yio}^-C>!BQ<>O_h!+XEN>RQMK+7xCYwd?kjofabD+&rk{ZPo*GfV z)S^&Y_@^JuqGoB0U+IU*W>F&9EQ*lLqUL0?D2Z$qC6mpf6tY>AN;Zqq$XJvPz@ioa zEXn|2Q51khF#r~|1Yl7s02XZnz@pXwEZP=;McVI}f5E&ykdpBC!ylUVddZxJUU&AmoDOuwbpH7%lksYN@cg?IVc zEb7VfHWp=)&7xjpvuG!>S=5_s7WE;UMOkFCD4T2+<&e#yzGN)w2f(8K04y2+z@mWw zEE)vBqQL+x8Unzgp#Ut}8GuE@09Z5}fJGw!ShNcOi$(&lC>MZ5c>pZR2VhYF0E-F% zSTqWNMWX>&GzQ=->Yf&wBZ5Q^)_=^Zhgr07u!N$ti29`#jY|t3{Hs|sp5@J=31qXV zglrZ~B%4L0WV5J@Y!;Q1&7umjSu}}k7ELB&(G&m{O$A`lGyoRu2Ed}}04$mTz@ps& zSX2qXqL~0Jngzh3*#Io60$|Y`02WmPuxKs-i{=5aXg&aoY5-WY0Dwh%0I+Bw0E-p@ zoJC{PLYIgj(TY3~r`Rk?*88HxX%Y2HEviimKl-~_w2bA=qB^o!w47`ftst94E6HZj zDzaI$nrs&BMK+7}CYwcT$XK)%fJOTNuxMWZ7VQVXqWu9_bN~R04g_G)K>#c|7=T5G z0I=v#02Unvz@ozeSabvci;e_f(NO>_IvRjQ#{jVCSO69s2f(6r04zEl;4E627Wz^I ziN266;_PV_#q{g5C!|HxFSY2Dv~V;*SCH)`t!H_&=v1;02ZAGz@qa3SabmZi!KCU(M13(x)^{(mjJNnQUDfR z2Ed}r0a$be0E?~!V9`|oEV>$iMb`kZ=vn|4T?fFT>j7AF0|1L|1UQRMN(&7XL88A5 z5OGd6i!Rw&!cA!r^-C?fEiF8`nOSr@%bP`akjm-vF@aTL2b)2f(850a)|{0E>PEV9`$i zEczP&i+%=R(Jufj`W1jhzX7o5cK{Z7>Gr}Li+q5y=*_gyJt9bSfPP8#EwiY%{&HGE zdPMzFixShr?>0A!A}ntfH7A=zNo2DqnQRuNkjE{WS(HJ>q9_21 zVgM{^3BaOO04&-DfJLnVShOtwi?#z`Q5ygjZ4bbrwg4<@2f(8C04(YNz@i-hSkw`K zMV$ax)ER(9T>x0r6@W$E09e!=;4EsE9%`N>7ERWdW#M%9O8vRRZxHjA>!W>F5=Eb2=(i~5nxqW)yFXaE_D1_H2X5CDq?1F&ca z0E>nKuxMuh77YVn(Qp73jR0WLE&wbV3BaOU02bu|uqYpZMFjvXDg$;zQnFc8 zMmCGe$!1Xn*({nwHj5^c&7vt}vuG;WESg5fqTK*kG#!9NGXPk$I{=F+0a!E>fJL(a zSTq}eMO6SSnghV1Y5*3^1z^!U02a*$U{MVKixvQ|Xb%7uEd*fEA^;XG24K+=02VC; zIE%)ohfWkhqAT@psZB78-qb7Fp6Lr~799$}qQd}K zbT|NujsRfMkpL_@3V=mN1F+~A02Un!z@p;-ShNm+MaKiM=mY>3oe039lK{@5W$B?; zM3CrL5|ir8q67O&I5|C{eyK&LrH6lxnnkCxyjiq?Y!;nCHjBv*>KH zS#%EBEIOBL7M(}NqVoY*bO8X1E(BoFMF1?i7=T5W0I=v%02W;az@p0mSabydi>?G< z(NzE}x*C8**8s5SS^ySZ2f(810a$bc0E=z}V9`wgEV>zhMYjN)MeEZ;9b;lq>s%4% zRI{j`hFjAk>X%w{XL>ldm05Hb%bP`alg*-g$Y#;KWV7f#vRQOL*(`d1Y!*F8Hj5r2 zn?(SoAyqi(UX= z(Te~qdI^9^y#r8&bwyO>v}~Cw}_}; zYEe>)@Z;N=Mae907NwBQqExb3ltwm-(#d8~3$j_1K{kt`WV0wnHj7%4v8WXQi?#t^ zQELDeZ41Dn?EqNR27pD|1F)zq0E^lIu&6x%i#hGfTEXpC9MSaO;Q9rU-)Sqk?4IrCE1IcF5AhKCBn2be309Z5>fJHk4uxJ7zFAe%*# z$Y#-GvRO2RY!*!=n?=*eX3=hBvuHZmESf>aqTK;lR0+VMnE))B1;C=&04%BkV9^`^ z7F7eVXf6PY<^iy1J^+hq09dpDfJJ)%uxKFwixvT}XfXhbmH@D5DFBQ11Yl7u0E?CZ zoJA8`g!U0Zq9yvxkW#ZK8k11hBBFk&MXOqbH|}5-t!8<%XfLu^v^Uu-T0=IA){@Pl zeaL3fzGSm#KeAc0KiMogfQ&^40H02Un#z@kF{Sac`=iw*-|(cu6rIs$-2M*^_u zC;%264Zxyf09bS^0E>i4&7yP3X3=?M zv*>)XS#$x}EV_`4MHd0E=wbjCT>`+OO95DP832ne2Vl_^04%x^fJIjUu;^+47F`3t zqH6(IbR7VTt_NVz4FD{<5r9QE0kG(102bW>z@l3LSacfzi*5%vi%xG5O71Kc-7s3j z*0r07TwG8X3>3Qv*>=ZS@ZzeEP9Y^7Cl5ZiykJMMURlp zqDRSQ(PLyRdK`d7PXMs!NdOi-1;C=G0a)}50E?alV9|2`EP5V*MK1ub=tTe)y#&Cb zmjPJx3IK~<1z^!@04#bPfJJWru;@(y7QF?)qPGE9^bWvTbXSW|i3k#XL%$hvw^{U9 zqJ(!_MAR>}=))G_J-eGlAF;ey^fB2i`h;v2eM&ZqJ|mk&o5*I-=VY_!3$j`CCD|e02ciY zz#=chUbbVA55S@X02YM+Skw%FMPUFIB?7Q00&o_+-y(Ff2ogP8-y-_JEc#I`YMv2M zztp1CjPQ*+nnh_WZx*GK&7u}$vnYdX7DdTsQH*RBwIrKGt;lB4He|D?H5rSx1z^#3 z04!<)z@qH|SkxAPMeP7s)EUu&4_Fi@E}^s2c!_x&yGN z2LOw91Yl8502XBeu&5URi*^Dyi;^=!uZbYh%v=#CCBwba&s3#)XGGL5wJ0Ye{A;FJ z)R*PWqJCtvs6W{(8bCIS29nL9L1eRNFxe~`LN<$rlFg!>$yhWDfJMUrSTq8FMY{m7 zXe0oOasgPB2f(6y02UPhu&5A#MWX;%G#Y?KV*prG1i+$Q0a!E^fJMasEE)&EqVWJM zngGC}5&#xW1UQSbGD4kuiAC3!h&b71(OaD*lx9TKFSTe=MmWE>Su~mD&7vt}vuG;W zESg3(i*_TMMbpV<(G0R#v^&`>swA65Gs##q3xGwl0a#Q8z@j+-EUE@z(Odu)%>!W3 zd;k{J0I+BQ0E_kjV9`PV7A*o`(P97=EdgNBQUDh13BaOS02VC+U{M_aipe>Ni6w%%bdK2`e)q>X%xycSiW|EVF10%bP`O$!5_$WV2{rvRSkr*(}NrbOHd2P6S}lNdPQ58GuEn0I+C10EPv)3KXS2LnbPm}pI+tt~okuo{&L^8i7m&@O3(02D zMP#$+VzOCu2^otn1z^!-04%y3fJIjTu;@wv7F`9vqN@Q|bPWKDt_5JxbpR~79)LwR z0I=vr02bW@z@nQ0Sab^ji*5yA(QN=Mx*dQ;cL1>HP5>6&1#lLfnGyO{1c|<^|5WTo zv*_!Q67J53s9$Q){TbnH`kO@$u)JCHAlWQ>h-?-;Og4)iA)7^ylFg#W$Y#;wWV7fA zvRU*b8H=6*VA0b6EP4ijMb84T=s5ruJrBU57XVoFA^?kC0$|b004#b1fJLtYu;?`a z7QGI@qBj6o^dk02aLua2DO05gICjL=OmyIQN-FSLBU^ms<2mMtHY@X3?iCZx($I%T3ZU8Lm4#1)w04&-OfJHq4 zSdZIHj9Rl&7$FCvuFevi*^BE(MSLmzNSTqiRMdJZjGy#A`B>*g% z2*9FJ02Y-2u&5m1Eb1E#rS2>i9WqhG>1P&=(65P9L?h~#S~N8p?mgTrn#S^G(Qah3 zXgb*}nn5;;b|;%fm1MJMCfO{SMK+6Olg*+kG8WANU{N&yi{=8bXdVEI<^!;(27pBi z09dpK0E-p^uxJqgixva0XbAv|mIAP7PXHFx0$qQe1LbOZp4js#%QQ2;DD8h}N|0I=v-02Unwz@l{k zEIJ;5MJE8T=tKY(odm$5lL1(C3IL1N1F+~+02ZAFz@pOuShN9vMP~r8=uCjKXiYS< zUIdArJzm6FYZj&ImyI??BkGr0bZ#_!bFNu*9?P3W=abE%3&>{Cg=DknBC=U@G1)A- zglraFN;ZowBb!B+ld?7+(X{|9x(PVMYjX6=neoD-3h>=y8u{pHvo(70btR+0B6zJ(a;+rNc2wq zrRsCcqLcKu8t;on)GxK@p=kK`e6#3bmN$zYA)7^ylFg#W$Y#;wWV7fAvRU*b*(`dB zY!*FDHjADiW6`q!EP4)rMb87U=mh{4y$HafmjGDwG60KS0btRq04#b9fJLtZu;>i{ z7QG3;qPGB8^fmyC-T`3Iy8tYD4}eAQ1F+}=02X}+z@m=;&Y}mRp{@mD(Gq=e|DahE z>m=dhXhi)|i#A2Wg`>=(&sp9q`hsj0eMvTpz9O4NUz5$EZ^&lRw`8;EJF;2yJ=rY! zfs92z0O02ciXfJHw8u;>>67X1pqqTc{m^g95HyqLXg$08qqMF{{b3IVXF832pI z04z!bU{M5sMa=q%3jm9{0Z z02cKDU{MwTi?RV&lmoz`z5r)YMl5ud2on7^B;rJ4?v?(9qa^f;Mbs~~XizNt^sZ*n zV3s$FhLFvop=7gYXR=u|jBFMSC!0kh$Y#+lWV2`_*(}N>V^JOei}C?jQ~PaNH&WOBAZ1Alg*+-$Y#-@ zWV7fnvRQOE*(^GOY!)3!#-gJDSadW1i;e+c(Xjw5Iu3wE>i}4EJOGPM0ASIH04zEQ zfJG+*u;>&37Oe+h(Ww9|It_qDrvtEP0|1N80ASIX04&-Fz@oDNSadePS+s8~bbtsF zeX^~Hv!7YCA$Y+Si>O~-PcI>lkYzUl-^atCWvec8r}bU+>;2_GyvlWyf;l z`zQTlE9EVQ!Li%r>rKOAp)$`K87r#ryn@)VlRa-t?D?slR~&0Q-SbLfvv&8q^4Ntl zJ#R{E(`?V19_v@_c{5|H=Xu_o*qt?=H$N6$=y?lcV;6hg(%8DCo>v!pvDWie#o90T zyfv|^m7cd>?Bdm)cTnt$y*=-+*noXJ@2J?``+44RvAYlOyc1)QgFSD3Y}}!qw;^`I z;huL^?Bydp@4VO!$9UdFvFhVI@3PpX$9vvYv9C__yz63vPVu~(Vrx(JyxU^;p6+>f z#gfkSy!&Dk&hos6Vke#Bd5^_jJ%yV&zyid}xG=e-vD=5o(_D>mdR z&wDSn?=_zHQSAQfJnyqu%8j1)Wo+Wjp7(9+lv_RT$Jpz)d)_aZUGDNc&(Ey6M?Y)J zyz)Ld0)FOq56B_#Gk1Pij)9-K|D$pc{LBX*m!sfkradKx!OtvvMvjA@ssEaNS3fiO z=g9p`{r9AI@-y`x1kUy|^7Y45K zGxZza*ZG*MroMggk)NrrKR@#`^##P2ex}|5e(PuICHzM} zQ^(+6d@tqZh@55Txl^u7U-^ZZFv35Jj#G7HS%gNdDa29n3(MWCxbTW>%g;)-q`mR8NxFGIhqQyHzNB87`jd(^4a{(B z>Ak!_wlXQIU2>$$V)LPjS z>>M}!=*}`-?WPAN$n;z{{ZluYp68~29WK-J-Sh*x{u(#ERF_@grVr76?%}4t(|uX! zre_S1=|yh3pp#554yJb+CkNDD8gD=U02t5Ob@kRf{DvX0RX zypcF$ds!&EW`*a!nKD73LHzxMh4hP#f zJ273i=k;%)<=Dr~s|L1~=5H7`$@c~vuB+K6vFe4MGSumF@-yH*x!CyoCdPCRy9eHY*5%=?U~`aAtS2ygu-*Q!!r^~ZjcVkU?zdSRl2^( z0OIwPHsl?x?99Y;Jtq>@%^BKJ9v4VoGo%;V-*t0be@h1YrP}Smepy1DH#lLfmmrs~ zL2}x9E8VU+M`Uh!LT66yDxUVw(-SPKejiuK0{({8Q)C~5-N{OvqPw$P`m#it+nsC& zFBEXL!s~U%a}uY#+sX4@7VxaXU?2M?P8qwS+*`_~noD!_@9*|;gn*$614#!Yw$x)@ zDPV@Qoda11Cbm>r+YI}y-1p?v(>lrjh9<^_=Zh_S$&9tqh7Xi*y-ZxIAydL5GVzdx z_7dKdiPtq`Ncc`BzLBPD^L8l_k}Bs&b7>=INJv;WW#oe3arz*+kMIs~#YT`RY4 zic~IPh19Q1tEg389thWeo6gd&g!($J(SB}ta4L07a3#x;?evo7>KJmcO27<-K^>d9 zI-VrpScO3y!>*2x2)Iw0t7F8~@oxgYR~Xc>xvOJa=~f$Qu8v8rj@#DPaX+b~pJsI& zC^Pnv7SwT1nOLGh>v)Jv9Hc?(c)CoSszK{`wM<+oZG^5VsN+MD?vu7z9e1ygI1U@rwqnX3OUC zhr*==)$Az~J*17$H3iiiDQTFre?v8syGrl&uCJyWF)y7#HTMor(h;*-wpJ<4RdbDl zrwCZ5FsSC*@FX2E9~N-0!obaa!jn4f=y|^h_)(gx=630>(*m z)jYsebG!O#>UTl>L#&z$WX9Rjf@+>G6X$BsYThCfH)+snJ}DEAYfv}emx*_!jnFj( z)%-=$kJ2`)=07xIwvv90Z(7H1cBhWxUCBDh)w!)SSH}qsmI)ZAFsNgRtK-1}_Ei|v zaiXi^Eds8S=IU7H>iCI(4-^Jgmb*Hpq{!X2G*`z8SI5@%b?m5hoN9IKE;DwJ7SwT; zOjK&nI1orFq1lVawU6H zw)3JiSI5o{wo8@!C~2;aU0fZ<3mBs?sAE@G#{&hdmFDW$-PQ400aq#v>e$28@i_s{ zNON`E(bch4eI1)?9e1)iejzh{C@rXCW}3X{mlo79UnjI_9ru)pB^tDjhswmk(njc- zf;yfl=`?AZ)p1(=m8anqTyB))en~Ik`qMvonDpq|X7Q_yJEPamqJrNx3(n|!Wec}U za~1r~!S4iop)fG<`)0uz-9yg*PSRWje`pq*(bEM?lIAM-Q?uY|bCiI?6b2RiTeIM5 zbGd*^rMU|J+$^}-#Of>frF7c=y_vh(JR~#TB`v66NblXH1r^**CR%II3ig(XUK+H5 z`7)6!ZG^5VsNgh7lca4{!GGk8zCwls|Izw7_Sb%H2+fu{{yH*vs{Dr@qLFN8wX`9p z$$|GDZ`Q)y+t#_lJkcz8v9VERI9=LMna4X;Zo=M|!yz}kezrHLouCcem(}V0Z{1^h zODi|;ax`uw~&^Fq>GcbC&W>+TA&b$6xfZckaDo3wa$Gi9~f-5f98-Qk9$u79SxJ*Ch7=%(Gx zm_v6*yY3dtR>#Ds#OY?tb=nSf3zUJzAPOwYPWhegStX3{LH~&C1{HByYP2_)1|gIJRq6es?!{GbAc6 zF{L?II=EANx_~JPgHwA4cWSQ{u(vdKYIk&}c1HcF{gTSs)lTj8GUIX5f>ZlhnRr@* zUSvL!i4QdBsr{=={H#Gw?UpgQ50W-Q*A$%EnUcCo`xUDv9zF$$I8Uf8nlk*$;3Gtw2n8+ z#ElxXj!(+O@U4zzfxlAn6pmjV_CJvW2Le~`3@f=BK zO8b}U_)tIT*YQp3m|a61k9X=lDBHPPnycdp4*n$I8-+m~Pjo)^lHt3XG*`!yLgo2V z$C(1ANpp2P#ntgR0Y@ne>bTz3@oE8AN^^BQ)zvYzzK+Lf9nY{jJ|;8XCoQOBWLr7Z z(t^oN%~dYw2rG5P{(Sg-hr~6 zwbEQ2=Q?=3fGZUSb)4sX{7}H#3IiYKhbFa=I=0(R?nI=yIxcW^EEX_EVNl0CTpbq) z*h8AD<3d-*l=?cZ(mF1+Ivyr7?k6p%lkVyE08u~ z6?NQRQfq1dQXQLXzXmt0<6V1D$H7j$U1U2$q`5i{ad1xodngR*IMn%gu7EQX26fyy zRQ`qB=D#H18ELML!(APl%Uj{iq`5kdaCPh{pocV9$6Z_he-?S zxUWpC)u44eQ6`Sppmn@hCN9*Vb-Yt1ZkIMf*A)2pf~04p{Y!N`OKkC5*4Hsp`?;a( zLaAeL3)wPMdcPFnC)v(-(p(|72?e)|ZRKr_ZKVy8D~NZ4yX^|eC#=B@;)cZd4dRnM zWu2Q6;@2{_jl<&G*pyIuiELwptZJwV3z-vZ{Th**NdujRLM#=*Ibkv3lR}v4D3Kx^X^X?16G8-9hezx0B|& zcwa(ry&NxKSA}kzPYAA;O9U*EX5)N9aJ_6>@531F-y;d`dU=G*c!0FPhx=vXUJdHQ zD>Ctt2KC_!nb@R3eF(Rg`%`HnbWMQ|?Idj{Z8IPK@wWqi?jXH8slJ+hf@T{B>PkAJ1SQrInVBncXVpPNUiAkvciqhTt}xRnfvS@?^j6+`t*tGQ&@`EML%S5<&#*du}tb%CKcQ!OFEL@v}4njQo($;xe8h9 z1Zl2g1+HU<3OG<<(6K@{=VbyeP#AP);@PInvx2-7Xn-lQefmcXDTRr2dS~_N2ev?2Jy9?IlPH&gep!$k(7}^fZ~6qCwB- zB{H!{gPzd`%fx}wM(CP?GkSxh_0s+gXY`|kq<5SA_!z8LV}HZYkfz+ z8>}_jaIHJY&7psC{aR(%l(oL6Yh58*kf-|U&=Hm^urDoFpYPySpl{oGUcV=Y%Tous zHTeBUH~wuI|zXZYmJC*l(+IOcyXk+E6)hy)UxPLuqPX0D`a{3#LCs9Q1?}TL}ocsW97+UCs)c2F00?kxeA8fAUVA42o8$A9L$Z zFnDj!?<53+#|G)>dTGJ1qHj3eu0aQ!4`f2WA`lEkDc$8`IcdRX;M!7lP8ofytVdgNS3hy|lA-d! zgS6xxviRVP3mYgZ!9J#h>OYZHbcz)FHmfkWYl-@SI zV%w;nAzex6>ZPQNNC`>JLN+P#HEZpK(uYb1hNKipk-`H!eMsycJVcuLq4W_cDe{z? z#h2%r?YTMs&tD!K!o)Th;b)V7+hKXc4JHyI?nEqJ6v@Hfsl&wYl4v>-!G% zmGZof+xR`&xJq>j2Zisvji*GuF4w=o;n}6lFu4wNwHjKty4k9OJ*=-`cdMbz)x-K4 z%oTjxRo|cbg?d^|Y$5qzOnNK()2m@G5@cxHslS|Yt~45ZH++7VHj4W6@powxm?b69 zed!n+kF0QmBQ67u#CTogX4Tdc_#odzlGxzceto>AtCUM))9pn4SmMa-PRVPdhkroB z%_VGmW1gG`0~>C{*r3A?@a2@rkwpd{ae!QYwp*7cJ29lutOABIpRRo8hR^B=F|56; zq13-AFQsDJDJfIKlZ6crdpRv_D(+cyUK{O1UZYjZ5y+3P zTKCVbT>DTUi+Qf&g?(h}jrM+&d(zf9TFW=A&Ej;9io6fj2uW{?8iOH%;y-eJd%jnq z55bL|R~~=LCgfG9%rQ|PbdF}8d@*dJJ?ACZgkCKZyzGto=++~HZqpwrh;B&*y)u1} z;aHZa&=vwepWF7`s8eiaOLcGymDO*iqTyy5)WLVR71L#XS_6I5 z^)}jDt)|<(sWKJ(xTQRQgrr@ig}mj>HtIyFG;u*6w2uki+Tc;w8_Xk*!H*v-s#w17 zWXx*_Cv6TByrTF4Y&dJYS0P!O_Nd|BxJ_*R*ewpaF-afRNc$7V&Mh&y;Szu6*v$x5 ztjA8L*v#KKc5X8j4L7s-vD;nNr^ikob-kM%JGYj2mHy1J(?064(??zJ7LJ|b&5oUe zO^%(y1aEYcW9Md#_ljfZW_EkyX8G&bdGRX!e>!%Be;vF3+4C;{KXdHd1>vvjT`&s% zr>=KnnjAZKF^i7|jG2nLdb?S+K4$)P?EVY)Dx?05$4=hp3_J_&Gz)^sN&28B$PKbS za5uQ6J8!peaMQUUSYon1u*BcFanY4G^Yq50;b#8Mjf>k%MZ?W(K7dY>HLJGzxW$`J zw-()O@YC?(H%drwQ=${&rO8dFKIqJP~Jd*eGockih@ z!7FHTl-$48+M{pi9WbjkmWKJ{D=U- zPdoX)x~`9Imdylcu#%B7m%Q4Q{|7(%?y~;uC{0(Qk0Yfuy3>~|KmT`D(rC>3>x%PV zxZ;fbxB2|nvHNeovoYeYW4HMYf)2>s*KY9!;s3_FQp5i`cK@@-ZrESP?tk{!?floV z`=32_L;r2ZuE8B|rd%%?+&1$ek9-y%Tt@WK&9b$7?|*(JjqaMNIuhtiA+NUaYBxUuu6Sh)w_QJ!$|~&Vf33eAq~D^7 zKKwQQG=0VW9~gfI{oBT$M%Rvo!D0N*ezv03aBu7C6z>IZex}f|KmT0<9bp-5|D{)L z`u>*;xBBoOICca6ZO879zjnhNhz?&`5`A=EgW2o?)L zRUh0t?&bP$ku+Uq;zpeczCB(41}JruXM&$>`M=gvA1{+8`+SW&-0UWAk%zn8b1o=cFwP}KBC%Oi{GLn~=p-fKJL`k+1D@=Wep z6Wm-d)8?Pdbdts810Q{0rp-@TH&a=|nKr+;b(d8nce`oS4L4fppS?dQKzH{JeUp1Y&4#tsIL|BUD7$=C5i-k$RP*#!UR z^fdVjVDODZIfMN^eX?q2WzAi-G;3LHRaR}~va0IJrL{}ys;la%=VVpYu3lQVL_t;c zoaMFE%NjhV^UK^rvX(BNy|AXr%bLGrQFYd=h1ILF`Yc>hHEUtkviY-WtFvmW7gsNv zwJfW;Z{@PO<#TG5WYsNMvao9YteVBkvgTD)RnDqil$DcR*{`y1cHf-JoNR@?1@>ON zWN~%x>RGdEdgo;K>DODI?juh(dMc}Can-`*bE>lz&8nJTv$*>IcQ=-;Ue>S+^X6ye z*3Ma8vv^7VlG^It@mj2^s|`xxDpFFrWPucXSytK7S+#qNTE4ilT=r#N$-?E!Dob+* zjvK%+lAZm}u03nk(wZ!BLjKd^J6pV{TC}WYSyn;yikhnGtkS~qg=M*ASw*hu|Mku+ zs#-3JE&LB|_n$rus>tlY0KswOd+Svtm|VwVurKCq;D->Qf~* zLSE&Z>bbL)FRZJqTfMY;S)ciOHzcFToSMaT666kC2CmAgC5sjRN`cnk9?nNqIHk20XW@{5q7|^nCq*zbwD7QqIe&{9x@e zw|t%7&261^NY^e>+SX-_!)7n9Sy?cM$hTC=y zhdU+i5N?|&EU{BgxTQ{Xl0WMvacs8C)G{F~!*u=92ZmT$mvnO^G@9dNH%Drs-=`73 zB;dN?jE>=0=Z><4tZ;MLUQ%Lb>p&=}Pb=MK$3_c2zNH1*Cbp6lRBk@^1I_4QpKxlY zjvYIO{hWkQqZPjP_h zp;dj{(*qkLI<^Cfv5Yu+D0fAUPQlcNO_`nDKjr+lE%lS=pmclhg9|`i(I_7z<7$*-~E{L2Mg6!(r)$Zl-NF?MIV=Ei0T7dexI%Yn2^3XJ22^!6}-; zI%vuKpe8We=g?j{B6MmgsC7JO+NN{cZu(znWqgJ< zje>NlbB_kk%68p)wr$(FoA%gZoNv>ojZm0(8os4Yd;0Vt6$bf z_VBZ0-NTmQ6nQSSb2z0#Fb6w){BqyUv}~F8)W+5LsIK9YzXmIcm+GKKOCD6eWWta} zgYGr;M>pJZS~%P#+_IN+Axn>7S~%Qo*TipS%je3qCcIrs8FE^QM5*n=t-8pyBHXG& zctq&=eMF1U)uvbij~NzFj!hS5}ps=qHAr-NzRd;@5^@35kt*@n!wBWGlUR zU(c&Q=*0;uv=?8<2->h0!y5Nu-3nJR(I#nEb+>6h&IqnA!N9tee%!Q`e%uxG77eSEETU-d(xXUff!Lk=aTw zPK*3;FWy+Cy*MwjSuYxz@!F~;y=ZL4M}Mjpn{=)}sKt?T^2S0xByP1Ahp*mhFHX|E zbQj#M)Z(tK^x~$V7msYc7dLFZ7x(e^86}gI=7m^$I{XK{ zI9^8SSm?{}R*%SWdu{cIY;gAvauR23<%rz8m0sK#^y1#F_u}@g_u>b4rT;s&IhFd(rray!5Af@#|Ku=|2a( zICSg1_-X6CIQUQ9Sv<9sUR)I1S-i6Ookhc1T+sB+qH!%Yrqv&j)R7JDufl#-lN;SD zf?4$rDxvX9=Ue{hi3k4ZiKqYQiMN9%^hQcw8+4!O?uJ|S2**YQcTBB1>)lnOQ&8_y z`UEfcOAAL=77iZcl~(Gz52ai;?Gu;btXRiSB4=X|Ro)!TDqA zXD_L&7++LgIetR9>_nk#soazImn-+EUcIFq&Mhp<={vY`l=P-Bzd#Bn>mAkKJ@)Ib zeU~}<4j7o9mtR>>9h7lY&Ei=L|7cxOI$c+JahcoczS;KZ%8`?kJ;uNwdmJ3^`l!;} zaYf@t2Yncrt=rb#jqcWdHVjk>`dkIrE}yBuVAt+=*@UJMrHNKWI|cK zRChv2WkF%N96UK%y0*TueSORs6dV|N?`!TnZ(ilB>SeN%^QsojsjiZ@xPtf6Dr@G% zyOv)%wWNGPAXQ1ObW>JY8h=ucz6qh$O(+~!DgV+`1D7iDii`5yW=G}geqog!q#`+5 zMRJ6vSr2mxrTl?H{c?i+VtrzB|Lh?H<7(E;s-0I|=L#Ti?!{L+xoA{TWo}7eK>mdB zuz zQY(ge)wQ)tYUMrBIn~<#va;ODlCk+^eY5)yt}LsWw|G{ae5^C6y0&KSYA2GMPn(OR z)>c(5s+>P-@tlR#qVX0wJ7!$2C_5%sOmwnnKg;BB1sm*_J*Y27EWV*C88GHmFK(!8 z&ElH6npq1gSIFlfOKP{aot*fos=ce050cymQI#uQA?)0$TC#kxyz{%IH3h?^bhk7o zZe?&Z@?}7B<3su(q@PzJnlCFN7&TH##29E8%sQI&zv?l|-dPFmfwe(|p7 zgqt_dEPUY(XbSlJmHm8653Q#D2hDcBB!oCCS(T=l}%Lco?w$f30=yjN?uT_47 zlQ&;Z-bSObn>VN?JE>y}=dEtFK(0vcv9CS$3m$Xb2wjjfz-_T0-rs^8H%1ra4DobK z)G7u?r=X0IYUH+Ex3+3oR~UGdBahR!y%Wj zisJJ4Q5ut5S}-}cRAw$3S14mkux>_3XGE|Y1+v*-Z|wq9(AW05uiNVaITk_D^n&1K z9B7ZW)AH|CIzGf(zId6O=+$#N%4e?i7iI>?+~U&0+=8j`VsBw@ogS5XGU(N@pmQRK2Kb>FW4y=9iaMR2CHF%H^-3R6a5+uPmETQJP;E^jRdVpRqW1 zT#1aV9Q9!Emr;LIkzB{!O^WWO90fHjxPVz_N=N1Q>o=so9I%STdaeW)R=Ez^5EWk| z2SV;t6Vcp7*;qH)t`pbZVe2={Ra2n z${<{6pF;5gRJ?ySG|XYDZb?b$gegVi+?`mk zpV{&AGCO|W3yUwpsH9i%aV5ot!kHtI%T2bF4cLs`&QZdgi7MNYA;ps+N!4~t)W z8s0^F?g|xLtSDkI+WpbM8!wlhFu8eUa`AR|wDCj5zSi%Q8$K)ZRB(r3H%fXiYnROm4m|h64NqM+)K+dbh-kS72B*!I zhd~_@;x9I~Jd3^_(c8GmrE(M7WVm!A27Ud5*LB(ldF>JmXtEE%Zf)_-Mt4$f)fn-t zI)8K@sH=6a8W4#?o>Qr>4JM2lRsUK;FCB&QR|wtX0MEUsldq&yF05WWuWo+Ox!J4b z1&q9knI-pwx_0;CAdtlBJ2`$!%28}`=PLKMe>`ZqYL!(loSQ$tx@wQUdQqnD`l4m? zmonoD<)Tw5C+2vDDdul7%&L}p&dKrAn~_F$U=0R{_z{xJjP6T(^NaywCd-9ze1W_K zl9#`1E2wK;@PeWsw>-CUe8sptyId= z$d=9ycP=%$wAR1o%dL^r2-9d^*__5DY4U8}MjMnOxqXlu(*`dwDRfZIvS5z>4elRQ104_bkZ);N z;5A8oPlB88@wvtESIyN`vzxqXR+n@1U4)=e{j%eGQB+)9I6AjDK7tk$$n9NO{AqJc zhXuJ7k15L27kL%q24puH?58bTI$rO4%4HkQmS9eKSu1nu*&e*X zBHyZOILgb(r*C}(HwmJ%oK7NZfxMuTFVx7_T!N~Uj?0zde_{jU?e;skP}K&vzUJeo zl|}M$XnBTZU@h9SiR7c`rm?S*{4a?-PGB#I6a!D_^b!yt?uh zE?GRUWAHzDpQg!v%BzDCx&7LFKjl2u(NErXabgBHD|*QKNx!%+bjPHABy9BJJm{`m zF}5tBy|4;ydmFDVJ}@&nVK3-rJ@Enq^8B>5fl{xQ_BJr6ibE#%gV}f$jXY! zMytn4%c-)=X3NTED{ZvdCmXa;8)@|W-)sHXKKm>V=JS5fcU|B6UhTr)xz}3z-fN!M z-smxhRHmldgYU!jEcHx-@c^qHbPLt|uj-k(cJ4q9St<{?>cnxmh3MD0z7LM{veGky zrn>DhiKNF~4Ry*qGUnKdMyBVC_0&zw+^TLeHwEC1xlE_l*f|wb%Yw69VNzbzJW_5w zvpbDVfHladIXU@(bTtQ>f@(Y@a*bZMX*7N`BWcwbHOOZuo@BFfwGE@!{$dG{?YH$ofax!z& z)IeT3W(K5oZfw-eTs{z*bweRD5#AQ;U^fS&&=ejS$D3F*Srmir5e-vWO24T%*jx0D z(AY>x!=9O+;cd-PUD|WJ!BMRq)anc}uDYx;v}xCEqK-6a?~G45__ZdEk5z*e)9Rra zL38MxPBnMS98a)#tC}{X|6$@GoqZZ{p$C@oD;54|bSi?A$L2{!Q$~Ky$m~Mw7B6tC zXPpsLPLLGyW?gq?;~wrqCo%;__ysa{R^sa~_jBG19Rr5km6 zh&o|x`iW?|WGR3(iQA^CQAn^&4V~5331!^sx%S4~>ajzSxA!7Vh0Y=Ao*ZJvURZL# z6j^#E=HJxtAhg=>R&~-53scLf5wqk|@t~Ay=2J|((37ejm0?Gjg9*UO8Ho7G(wQZd zMbh1I<4Ac(hW?g^oX=4cxv1cxw#W^)ANf06N@HbWe&qcJvTX!4Y{=rq@STCU?=7jW*6n0 z=*F^{m6EzTFb;Dotc4{^%nHHElKIjz!qtV>>JS*;DbJ4y);K0m8K_OLz@Zil+rYSlAB&lMG6yFQ9Gy&5{XD|tEC78b25>pO`pkiSYpVN}rVN5f$?R$6!*Lqv%)xyt`c>dO zQ&MS7b<*_e#J)2U`;JRZ?2D5M!>7RmeWzETZY!Bl)>luT3{QrUo|Nw^lk$+J ay z=o9)Ohy;3tRo9khDg{j^?;fEG0l~Z2G3Ag*7ox!U?3_ryNXJtmA6GxbwwEM zQb_g20zHartkC}b1_g{%k^S;VWT92aM0dl@$g<`vb0%h5bFdl-s9<1;%2Ra)yPOgv zv%;Xlg=Ke)>!n?hTx2Hxun?{bkZ0Y=)X-|&5}aZ(>i{OF=T8dh7VAj$G|Doh!bJ20 zObwgGDs!t8%+QsLF!5TLHG(@0@-sa_#2P?wmquv&qid(e+8=2zWf3G?SI4c2%wXfp zl38kzZq`^Y&kc0`DufV9m ztn8UkN=mEA?1F3z)l_c7x@xdtREYdwgFalSr$&^sp22jAO=)b>{`8LebL`YOp_ARt#kzZ*)qgM0;WC zh+xObBn9kK&=W`b)Ot)+D@wv_xG=tv1uD#O$nvks_o~iSr|>YwlbknO=F|0Du$c!6 zQ)HCawO7WKHC&*^6qu*t7>lAf4$I3rqv_|SYp(}~zG{ZY?cZ44ckb;PgMDHX^3{@{ zipT(pO+hxIQV!fzUf->a`kko7&HvR+O1SU4^L$fAJs&+sYe*;7`;}a=sZ;EjZwO z=1duUNRl9Jv`+`SJr3E`1W#L?Pt{tQ+z>3Cp~HtmD#K9XU8J;E0azo3ox0@UcnHGd zIf4D(I(M8^Hg(Pn2m8!wXU}ruUkydAJ%k}cdTBLW*TME$`lypVO}-f_V*A+0v9kK? z-lLvSAhV9LXpoDZrfZdHdZ(d{tE8&86ufg1OD2oZw zw~&QBG()QQi#>Rr;vnt5StD0v*Q9MD)rEL`a7ZDRV5`cb0G)jlUTX73PF1b`PH8amaKl|W|OtOf`ZJVkLs|v%!h-w(TlNr+bnoP~!NOgHx1$LXwY9xqy z_?v|SBpF%l)Y4@nq@Pk#s|E>jgj)GRnpgD$n=Wyy{2buvc3|nv+g-#mvgj{IS3c3* z@FH{hRWifEu5NHQ0_%3&2M^sClQrVR9CQdgRhnlifs>^Z#*Q94ZenoBkH#`=lMbWg zq7h@qO&IB};x^KmF^x`eh^Fflgf#`zT?kQdT5zUpK$C{vlT?G?HBK&&8Du7zMIx_< znWCpwXdNc3Y*p2MXwaIOrdT>+vR0LziOF7xgApnY zbn1ClhqUk13V|mwkUN;g%yfCf-lJR4jTa~6$>3Y|W67Qo$)8fyNu|mi1;L04={M>2 z%d@YTIZ7{2rE2e+#zqfERfweBF-6PxK~$aHi{CyHUC*To0eu!sITa+y?e)hwmxB8wf?W;_qqOZWD}%}nI9sng0D_Wgrn zIz6Pb+S39Ih099ywvWt`S<~jsk`1ivyy>0Z!I=ToFVJ>wHdUSQMk*l*f!+yeqCYrg zVoY-Ku*oSMdyaEe5jGpp!wlTykr=?{A(}>GeSzC^O*a#B{SCUA-a!WPmTJq*U_HzO zOqK0*5;8^!x6R*VsN9^f7)KYG$y^gWGb1M>w%l=^J;{25keY$SP;O)n2Ky+2BMS8< zw1T4S5$Sn$=f|CSW42S9oe;-Z`j*i{QRc`@XWFc)8YCc0Q>0yz_Nbzy67wJ!7}lce zJG~028)lc(h)TUlO2y}Y-rlGOVrL|316@oT=JkU#MC?$dprk@Ua7`GYK!;F|Zjr#@ zb2#Sq-Qw+yRY?(3*#}!8RoR>3CX4$sLN`O}s(l2!VUiHp0uyhlxxuaiP8x^LK01ea zHjYc{=^1hAbTbX1RD8j`L^|4}#`P|<7*Dv_OfA0Z)m)XzdN3lND&Rh=3bhkX4@q?GqBbpg zHhHuGmk7;D^S3D>QurSWh>jhax`)sh%Ply9t@;oZ4s9)QC|6ADJ?;uq4N3p(Jzq5_0b zZ)sG6JY&x;8Ab^>elbBWFrr^j(qu5<|`qxn%)OMZ>aSeBzmvEWk27=2u)BvxNc^ zvM94MvS3!2QBxE=$W(y$gN^a@=vZBw&M0c&Ozx|bwkud&G2(S~F8;+Gx$s0{> z3(DLfcgjABLs&6q&)Ut*DehiB?8ZVQ>fGX)Z1vs!534&Flw z6Elt}g@v&b0abk5gfdn8$n-H7{+sQ5Va5w7;RX?U zC$W_!b#UB?x-i9-Lw~tX9T?GRUZW4?V$3U#*GC?LbLXn7Vh?&5bHU?tEGTR&LN-H5 zYFTw4Q_QmlP};~bUNiNnwhfHTm*b@@_9|0L(;X(9s?(}Yk+Nn|jxiQ@$1)8wshfJz z&&wHWW?_p8aXOpxByQ<#Fvp;a3DyWvI*cNmJe7TD*a=;P9tz%&H?y*cr^duPSdn&} z;%JEJ)aU`IIBMynD=`6i)q!xi{9aTl9hN&XmKm|(>!jcovJpogW zgX>kgHI%1>+b2%<_R5NRNN~ers%&^ffXq>0HFarcd3~T=4L2Igaol>T2YfoRJ!36X zM3A&8nJPX_thjr!CD}2K({V0602!cq=KE6IMjw_^5vu`GW^m3SpzCL4>>2pF^(d+< zw+1aJ!vUw+Fc~pd?~-DvSkcakM2k!;NW2%>T(r z2AuoyX2H-EOVjR{936~F*G7d|8a?9$jz>bb=t{)kXrzuIX&Q}d(;NjbNX8EOq5wt& zaOUoMRsLaD+r3E*9SRy7a|CN9wQI%RN9~Oww+qf;tvXvLAu@i&#!SzFg^|-c5Wa;uy`63DkWK8R(%Dc%5=$z!&lyF#) zg;iw9_!2sI9>9IDBuwb;cZ`SB5YW4I)C5T-w`W6tQC`j@%o}qyOqW?tL!~MZl{)&} zAi>vP=?5G*ls{H#}22CX!SgAZ24D zrbE<3lH95X)K+go)i5T8%>5>kCyvV>?Va*+dyWkcJ?X;lnaK4tS$dSGdnMsso}tni zyR{s9BwLW4@7X&cLo%r!tPto)JyRy7s+A^E0vsHx=~0*oo?7?jrs3RiIO7#2_n6kx zbIunF#>lX$H96KTIl<~ScN})UqcOzva{5>tG*D#%udtAC%W7(H+Z40}>q_RvU|orq zeJJ1K9Fo$J!530wV2(|6W~As>Gi0#5WtcZo=(mKpY1AP5=$rNH8Zz*%3M(FUPSCw5 z?NmRGPwlTuqcq3LR==AgL%$6oLm%?Ypzouh`%W@a8L6p^RUVzqz|mQb^vqG^6tkeM zYjjV~LeCMpv+wfUOul1EzuzQNr)#FpOqu!!cBW3%OznY8{rt?qI_dSBRZQHNj?M({ zkzX@P3{#+Vjt}>44;`k4wX>eAK~Gs#&nkpyQq1$s8Cg$rpNpbb;C7DD7s2-WMk;&J z7CLTZuS&Og?o4ijYE73@m5eyBtC^y*wdWk6CrhghMs9n_L3D73jkU6F8lDC<;kYqH zxp|pI8R><=y-PXy}Z`%9mMuuM1!6qSHBRkQ<#U_`0r_ zyzbpuB5L(sS`+tXB33UHnca?(OeQ}f-Y_2>GKb0r!CUJDo9N)`p&p~D)RrEEd897J zQh7gA20Y) z3tjf~i)kcTM+|V|#I0O0aqk*>Ms0c_3C$69wKeFx%bUO?mi3U<3#pshG2I;3}l`(5bENlb43McX_*tft~45)#92{tIzD%!Ca`pZnpQqVnt9gh-uXK-ulQ{ZsyGw*la}B@``ZFUgVY~`?7DDcgqip4- z&BCZfk&7cPhW`R_J;yeSYm?r5RGfs(8$NIPB*M;I^1Zh7IEF6}*UpcqMgT*?Cf{bu zi0im8dQp?bQ5Q!piMRyM%85&!8Q1ZD6;9u2mcB!E_uuy4|8;%kRy_Z=!+WUd z_TO;V&SYdz@_R;{u4_i1uCeQ}|5Q%&=$7vTrpI~8S|-XGN?H04Sd_@u$Q<7>_!%|0 z@0fm=Xc_A?X&F7HX+*P_R*`LdhxrbVXy)<=W*U{J6-__TT-%0d5LcVO|UXjlJ z1FnD{_+*Y(gsi^+X$&LevqzpQ0-rp>r-?k5j*noSB{h5Sioj=&Lfzw|MV>1HA3qAU zms&V@ML5kYdudUER|HZc^nPz@NciF``?%oE_!WT^oTg>uA|`wCp=u_MI*JM9V(WvhQlycUAd6%XQV& z{UtvlP;-aIM=)n-`=c!Tqm;gFu9l}ZY^eTGK}-CKaB?mCT+4o}Wk1%k&$I0FEc<-RKHsu0wCoF2c!H(4 z&~ksGvJV=b82pJ}5za)*exhYR$+Dkh*-y6YCtLO>S@zy9*2?oww(L)~?w{hs(?nWY zAHMt>8{%S0h!la(qKDecXVQaLgi~bM7X>ZxE5a$Z=$^A1dd8Q?w zZpjsvJj;@+9BGjx?2^W<(0>S~wf;=^2+th}_+5fOaW5@>EA$`cfaVhWrT7zj>1nh= z|KTpsTw?z${={Bd>Q>P58E7uCZw^bbmzKB{VlznuUSdB!#6HfcugM$JYC1fK*(~7v{bF&%abho3q$PNId@w2uh2eC-QU5fx9ppH zx^xoWevsvP+I>f7a){j7Sx8x0l2%TlbFX#(+q9ROsFl;ziI#-nCHi|?atdU5o{sbxa@xxnvK2mNeuHJd-jX+4@;jFNl_ejrtj&Tk;r7o?*!sTJp`7{GcW8 zu;i~SIm**TmiRl;l80LI1WT^6`4InAjKku#j-l(qk}oaaO2fb&C$ob4Qmicj>*NTL{F)_yYst-8ny2gd=xNC# zEP0wGFRE%^yc{=kxdwdCfWDG~ANk(Qil$tPLzMV7qUl3%stA1%2<>(KZ(){+Y? z`3y_G!jjin@(Y&yxg|G|ikg>%zlSBKTXK;l&$Hx}mb}f9f3)O|hnc7A{E%VE<(7Pf zB|l)vuUhhcOKvM2H(nCn980dX0auDoN&^MaNN}!?y#`?NriBhAt#9oyeoMJU)}S*dC^_{*IqHA*NJCYP@hwm zMM1s!*Er|%jEFZ6WBD-5il<&&Z1j|8s2~3J{l#+nEbN(i{d}&Mn(YBvx!zpS=xtaJ zZtS+ur{c!nuolPGt|T3KTM=NYaVdWO^aHa>-3=SM+nh+@Gb1hsmaNWz8+ma{6E=| z8KO7r&Ruh4M7b2zpbd_TPB9&0jt1 zm4%*uGrq%-qegt!hz)%=BlHakUO$AhlDon`2{sLnJsEY4+cd5XHsQi5u@J^azhWiK zJ0FY}8tzIm2UtT>C#a}F!i9Merp|t*&>Vb!ly5Q-wh9?FqB{#@Hh4joEs( zb-Q~3-Q7Ftep9o%*6t2&Dco#M8#)TzOQyqMD)zrqWxcMU5mjnu^WUjD*hgJL6G68S z2i0fNOV{;>=JcT3EL8*>t#&R5dC$?o{TeQYj9S~X2X$-tHk@1QQ*GK~Zsi)>a;w7T znx}^LZCvw1eBq>iN`o?Bl%hyt#~0onDBt$N(IvjuxX~ju+$*o&%4WTt(7ZW{A2{J# zck}^&?G0Vt?A>gQ*qM#~rYxeq^W4dO?Up4sY3s8p;q4kx%R4Q#DF2>khN=y)TMfM%0G)Edtu8Z$s^DwV}3_ zZ)q9Ux1n~8s15I11l02qrUr5Av9r~N-f8)kmSKGxYS)O`@V-SrJw6KcZK$2CHq_Sg zEiJ?PHq@>Wwc&k>fOs%)TMfM%0G)tpv2e3(~zcZiua|+P>TJv$57kjTfq{EW8p7F(#GcWCMDzBaJ*_F5ZQdV8x4EY&kvJQ`T4 zXNFpOy7nd=Jb62eZJ1;Zc_+Fz$vwC0=nk)1+cl<3@mMDjkm;2^IRwY-24sOQs(T3eV2tPl^1eZ%+f1n;$8Dq@O+=XRJ zV8<->4qfJ`oy^TH*DD8|uXM1J2&Y9*MHNPVWPdaH;1ZTs_4d!qrE3x8vL+ z#6J%T?{%Cfgc}^^IpKYdvkmlPv&Bx~{f_g2@Jz?qCEVyZp9&vvoIS!#j`Ot;%JvB# za-1K94?9l1@Da!PL-;8E!6pU&W7vl!d>rv0+>H1W!V?L?C*gnL7RPBPd z*{l0-zq$|i<7deIjoJU*^Z&QopZGWN_y0D0CVd)<-~YGvvRy^WgIt|aJ`^{QC=W_T zIgy?4l8>Z3`OnkkN%E0g{`Go)q5l$HzWqyez2Lt>ud({;bh-3jjeITcx9M{1e+Btk zs&#OsRzc^00u%6}RSC*IGnD2jQzDJ>+C+_}qocY4P z9A}{rr$v?sQP>d$j^F2V5Ol}y_c;inY+R9329>*CY(T34KN6nEWxx?V#irs}mGK3%UJ<k988X`&6Yqzpq zdyVxP0wwz${X3BU!q<`h!Z(oqLIgHf*vseS348mTLLoMtLHY}a zBK?Ic9Oq`?9ged?h{RthT;({cg>N~|dg0rSvqAWd<2)eT={OGy-*ueFh3`4e7UBDj zvsL(#NBRqoNBRp-K>7>Qkp9ASq`xo&=`YMg`U|s={=yMRe_;UW zFC2;V7iP;p`2Q}Hf8kn`e_;;NUpNZsFC2~Z7v>`Ug=3KZ!m&ty;W(tfFc0Z3#HQjV zlE3D&9$6%N;UI&Dk?n;G9H)yAh3^=e4=#Obc!F6yUD#Isw`!Xsz?!4jG|AX7Wz>oD59tB9F z@_X`E5{DU7IHSop@-VU^*^TT?rjUcl6UYELhAbpcCa01!$!hW}@_cd;xs<$yyotPx zTusV;dr7Yc$<5?e@@4XM@?CNl`33nc`4jmE84;=VHzQk;?Z_j^qsYGG0P;98gUliG z$cf~sWEnY&tRc@KFC>?cSCZF}w~#Bzb>#izBjgtHdGb~AE%F0$H~A&GpR6b4ynw`i zlPJv=WE=7bvMbq(OeTkr8RTfPkUWK)PF9g~NjYC2&%czshLm##V!n#JhkS_KLcU18 zPQFimN`6EBOdcR(&|r!FmShLA8`*~(NFGm)B=gA0vX(rLTufd`-ay_)t|d2; zkCV@muaa_pLHxao+)I8>{!T_lYj-WkwqzoC7P*AHk=#T+O}gRSM`;jM*d1MJWo4kUQ^9mAw8_BKYTjb~D zFJue`T;jex*_%9$l=BK=e+pSiUO?87w~_ag&ya7DaxOvi_?m0Rkw=lolG)^B@-*^X zaw&NWc@Oy{xt;ts`8^pCtDoD3>_HA9N0O7sndCX-W#rA|-QIhJ2KKo7_!yh|~8UOXiT{$O+`hWHosvIgh-ETtZ$!E+cOu zZzJy}A0?kB-z4{tKaz5wQoAs-@}B5LV#GHxsrT_+(CX!eoOvNHf^Jye>gda%p}K?vTtAFqmn$Ayo9`-e2{#Ge4X4y z9w1{e@DqI<$e!e}WEPoE7L!%vJo0*S6}gdoihPayko<#e+EzcmJDEzRkz>gz_;9)o=BFGvq?E$Ch>O#c?-Fge3pEJ{5Sa> z`6n6MPU~q;4j?ngJn~d>7I`kYguH{ik9?ARg?yjfOa4MO!N6a_(VFZ?_9lmrqsf!V za`H@aA$c{qg1m=(oP3GgNq$cLNcuZy|0Ix|$v)&zGMhY+EG1`?^T{j7o5{80!{l@1 zo8%|tKJqUz_6Y5-4rEVq5Sc~hlf`5uIgh-Qyn(!ve1LqK+)jQ(eog*H#&p#FX-jq| zQ^_=PEIEZdjhss^CYO=7lN-n<$Zh0%_avE#!Lg zG4dtyU2+fk3)ut{>yn=jBfFFR$qaHlSxi=u=aZL{HhXxs+T^t|cEKUm)KhKPP`8BNMehT9aML6f%t*N1jSnkn_mP$eYMD z_}U9eF#sn!Ja6fP9qPLOw@sBVQ+Xk{^+ul3$Yh$e+nSNPk})e=%en*@irV zJenLpW{_jaX~$?iRpg=+Enh|6)nCgS$rlG|`7QFRW3~JX*d!Gt9d2)LY|i2BI63Q zd<0oILCYoNO%t_z7rAS)mcJp7nxf_Y!)ftYMSQpWtyYOg)_8# z75UOkEx$u1%+hiv^2AClPa|)x*76$ili6DSj_f%{%LB>Ev$T9J`M}v)ev16 z(@Z;Ga}2q7zLu{cw_T*=cga?Zw0tBv>0&LHk+)u=<#ptzmuY!F+4~ADA4^u(Y56?z z!K=0W4Ee`0EjPVZGvj*AapaO4wR|o4>T)f=Pqw*L%U#HmR%m$!x#D&$-%WnLQp-P( zeeTlo5OVe!Enh%ByiUu{l7HQ;<>vQjW^K?MPhNVzmaiwbKcM9g$+iz^xf?m<5iQRo zZ+}e7_mX=yYxyU#-xe(&N7g>A;Ba8E#%t=w7i?_h_!v`zx5)gMryf=T#dDTvEM{~8>8jl$pOu^oKBvD zg+6hAF}WpP%de14u$C|Ot;yUrTAoZ^jkSES{};Klot8f%J7W!B?32jSPFg;LT#E%o zv44o%*G0>Jl7qTyIg^}+wR>@Y3HfwSEx$&_U_nys4VCUO>yI zkk@5v`3~{}tZ~cp_L5!4X!#hje4Li&kgw)z`F*mUY*V1k6Ujd07;-W>T{su}QG_TX z7YX+`PMz=z$GKIAvb0|Knd3YvL|J=M2!C!9?sl9Vls_c*l0T8YLhZf<*`Dk{rjWzQ z9C89#LROGxlZ(i!$Xm!YoH`Dw@%CC^G)BF=5{LylvW@llwx6jj3qttgP2pt6*-iO7A>!!=vYzIVCu#E- zvV{=$x2N2R>`L=~lvBxLX`V@WB$-R|NtCCMB{Z)Q!hdsx2+tzgUqW6@UPu0myn|d% zZXh2aHK zzlnT;e42cje2v^men5Uk?j^q!Lhmn>eYUa5ic1+%n6OBe2Nh9R6z$d_pTD*1*G_kT`C zPStu7go((Pl#_(edki^%=2>JRSxoyM98i2eiRON6-pa`I}L-%j37K0*7Z$>)X8^B(yP z*|JnWr;~6b&Kpo3EW~q$k?AxaLwP)TBF(2#o=%=l^Rp*V|7$K)RJYw{=ZSJGdm!`FmtE`;7Tl-rSgg?R2{A=0Bvn1yjC z<@rLy(?aqRnqN!#M)Fpgucdqsxsm2iQhtVff#z>g-bsE)^SzY6A-|`2klb97T>L3xv=+g>o@DM~Ha2O^A59TbPdh`IKJ}!XMkn9W?)t z^1sQ?Y5qOspUK~89*vFIe&}gVCJ6Doj+7J09yCv(Jdhkp^IRePH(rSFoJ#wtuO_b}mkXhHCFRxRW+9%tR|tRqBs?DH2FkUZAVm1uknL&SgK{sjAI*nS zKAy~^`8di23^T>;6zDx-J-6%wO?xg)%awGW=xrN+HzC!LG-y=UF zcMGBSYs&k`sG0h?DMG~4aN%({&q8^U5b-pHETMS?ArfU!wdf`3B8Dro5ZnL-QXg*OPzJyy@xs zxh=?6Lin${5dP~WM0f_#ekhqqjwJKQLh=-{gglL`Bx{7wJCE{w@>(ID`;-v=ctwak zA|FuRBSbuXP41`ppOk&Gw0#pH?&~3ho)lp_?02J_D}{7sm@FkL$TP@u$n(hsLg-yexsF^V#B<*f!hgGkZ5`)(%6|zFPyR~H zXd&FSrhGWrk>))q_aRegKAdto8K8MS&Oi>f1L6b z@>!bip!^p39?d_e{3ZDv&3~tSfQ+ot&+jEfxCaVb;T$04JR$s3NKU4C8ReN|CC$&F zd_K8==2ud_hP*+D=R8gOSA_|V^C9KELOk~y@_U;9McH4i?W2W~UX%|fJJP%-_PS-Q^`T(31lXjOXiUigwT5`<*DRZLd44&A>wzF5PL1Q zQr<3vKi(wYrTJ%+_mbbz{5Q&fkrA`C-gqJOv?klpygTKdWM7&Op*)<-pn0JX{+ldB zc&5|-G_r;~i=0m`BrhkgB5xvZCGQYI?|RA`$Y+Ik?k_^bQ$!6Ihxr>Jp z&HGb6mK-L;ePd`pSs06R)Rb$5&@-1jkLH(9zMQ;Ti2LrK{k_6wcs~Q>mxR#sD)|QO zKcoE*MFNZvl=BJa@umsa;WQA}V;+MQsScZN# zd6#eo&hwF5g)`AE3Zegf@>6mTxu5)r{EPITrSEG_#*^*Hj%11u&pB0yd@z+fovb3~ zlJm#~C7pO9aX-;wp?A7s>A9iFCSE3z$l zB-xGZLnf1h$zfy`nN5x-Cy=L-Q_0iGDsnD4k6c7vLPlZ=R@O<8#T4Vo*5pxSZxY++ zlsj~t6i1We$cg01WVI0Mowek-244@=o$@@;>rm@^SJ_awqvQxtsiw{FZFu z)Bb5jwj>WDJCcdyQ1W;(K#n5ElM_fRL#Xf;lPJDw-STX5KDm&*jJ%S(i(E(EPd-R) zCZ8hTB|juTCHIiulRuMje(fK1J{#+)>U=iXiRS7(0g%;u0>I;GoqI!G+jGJ_0|6Umdw3i1qcA-ROCBbSkDgjnyrn|y$Ln0%6ahJ2s=nEagl zl9cbYiN2pmb-o#L%V=%hj_gRv_uIsMZ!&`nkYmX4 ze2jdOe2#pHe4Tuo+)K)L;Kbj5k*^BH;s`J-ymqj_3%p=Q$SXZ7&R+F{l zxukqYPTXBjE+=m%)wylh-%a^G@KIwubOS5sa^t|1>KpCDf&-ylCD_mY2*@&Z4JPj#Lg zjHTQ~i1q6pWFIn_JeE}F&Ec+q@*9$gB(SUB}>RM@=Wp^ z@-p&D@-}i6`7rr7xs`l@{8)(f`Q7A~Xi?lpk{!uJ@@O)NOeNL1dfYdb zay~hkJcXP=o=z?xFD9=buO{Vted3>6$c?0Yw@=KUB%dMW`+Z`*ll+eSf&7DXT4;CC zWOK4Lc{tgd>_@6|{9_zPzVj!~8B6AqlgU%aGsrolI_E#eaW11Q-~SUmx07qhd&p;m zqp(kge3g8il};U!j4!cAt#b2la=Ib@*MJf@*3etw4>y$#C%2GqknfOt$gjyiN%cMl=xL3)eTm=0$=+l?au7L`RPTAn zLOUulDBo)oo=TRHGsz3dMdVVlj=Y{+PHrS0BGvmLp#N#g+sN(Y9`bAQ2l5y4FVf#y z`%}F~0{S{q?oRe3hmgZb`97qCZxX5AF9ErX@+`8NoJ-CluOzP_)%z!K|7yyQkekWZ z$Tvv&o}@hgOY(d2XRI4R$q6givBB@4)jWEELMo zm>f-xBh`B|;J%dd9P(`PGV)6DcJfa09`b(jc_H>uyiC4MzD=t4Y{35Clz%1vBqQ7E z`(wy>vNf4R9zzZyhmu)jHd#!TlBbhZG4KSFLHw~{ZDuaRGnUy`L|``;r65!K8YB z3+~USd=hyoSw+^6my%bI*OSZ1+sQl0d&v9AXUP{y^}ZK8|0BxZkw1`8opkt`k{!uJ zvM1SxJVA)MS-lSi97TC7SxT0ZRb&l$F?ktzHF+JW-WLPC8z?_Ss`tmh{8h@Ylkbrq zk^6<{3;aa>LCOo;#k?)qf$T!|Acv5{$t*IPJe8bE&Lk_y`Q$=!DOpFZ5~9z!hTK3t zKyD_VBHtn3CqE%SC;uRwBemXWvN@^VUxVkhquh^F@3DdT5X!^J2||o@CX>ZvDOo|D zL0(K=MqW)`N3JI~kPnfMky}ai9vnRPBg&tUd&zIeD2!EQKTA_Gfoww_K^{pSOCCpN zkO6WGIi8$JR*<#iT=F7vF?lO_JGq9un|y$Ln0%FdoqUh{i2RQHfo#@Ahc}KqoIHZ; zN*+b_BU8x{WDa=}c`8{&){u+HOURqa736AiJ^7UI7{_^*+(vFE-yz>8e;|J${~~3s zLi98xTaZ1-USu*kfIObeAWtGsCCkW}WHnh!UP@j;UPso2QrB~hD;|%kdw$MWGPuro-4%M(*@*W@>22^@-}h}c{jO5h&jov zUiC6mXJ$B`LifSf`WlQYQE$qR+Ou-}CBA+F5cxA%hU=5Pl)@fn4J6NHT^*6e{y}LWBoVqL@e` z3Y45IL^ubK2%?gQk=a6oKbJ%hlw3#_3vp8^Sx(L(=L!*D^T_$+Lb6VXcw9!_K;BHQ z7N%oAC%J)qfZQU?LVZTQKyD*<3XvWkkh{oF$$dhk(~o35`3I@e3+Wdt@eQhU1KUte z6e3c(lRe2kXSWRM^q>|?gr{G)~ zxrAIw-XM(P_gBCbBFEtT0l8X;`g}dPK^V*LuYeDWjB@xmxkZ?O_$FTvqFinxw+q`~ zeUscNY>W6OcM02JevjNEM7jN%+$Zda^dRenD93-0jvsO&@;ezLM7dVqUjfzkSGps8 z#2i%LUpX52Ut};*i1M!XRe?Q4?t}S4GFgc7GJqT`MEOwP!vNDnMtR60vxS3EKFB;F z@_QkvzLSCcJw;@&SeTCTLY51&kiKNK5cySoKLeaAGV)C zEhBFbA|KsMt`H(Wtt3|qk$={c8-%ET9v~kUmLUDfEke{sTgexMsF${p+l4cb{^U*} z>ZuRN`N)HkAD<8+AMO$&|J4hT-_$-D^qFSGW@*KdAT6AC2`?JX7+)FR~7e^gj>JmUNG50V18%dMVPm zCHx}kd%Y0p+9@7HI^H2fI;!5 z9bQs$wh&=0q&!K8u+E}fEkxKBQeGlNysx0VQV734PI-$E58p%iYa!C3jSm$62;r$d zl#_)>pDfDRLZs6y%GE-o*D}gC2oqV~K;IUTk$$^quj-BNEbp*SkbH&o>@I}dQ;2lU zrkpE8qgy8l{;^jG^AVc#YKGV+1?{tINaUs1}n zm_sfVrlX%hS$)R^iLrt51487Jos>TiBELujF842lr;5-#*&^C`3MsmGTDr1Yrs4N6Lx9X-GfH>N_Q62q)z?_GuJnoxPxA!%#G9X{c#zK|RYa9+vG#-j($ z)i;w5(Yg7cs{ZWne|VGrM)7}ollmy|e|VGrM(`ot6y}S%j1~9mzB!dOwI#D=HArH) z)kF!>dUi_Di0bmPin7@yvkvj$lrZbujo{-LlfW*)z{9sVzH5ev_Q!IzNaz z$(MiY&hu^SzjbSJo$JtzI*Eq{0c_~};6XFF^w8CNKR*7qF$eYD?~%j(oT;;BPHQXz z;oSR$^1pL#Qd5_iLkxnsNtc=b^d_AZE2qsqySnyJy=P~(gGPbzo*kxxC!@K`4%8vu zWrgbCcjZ=FFWsgYDGrz@!_jjrh z^3%uYpEHW8b$k`gEG?Q=H3#0BO`DpcSu>}XO*?zqEH=QitE8RoH>0R#S{ZJusx6y_ zTvSw5DF%p1Z7r5nWfeuImz`ZyGxHqYTUs`C&Wxg&mD8)x+N<9sQ>V@@J5wisHknm5 z%`2A7E~%VR#x8+&(a>bp%t|~#+oDh5^qW>yQBhXOPJuR`KD(p>j?(kT^ed^Yojr5v zoLZ&XMHka)!dnJdx1t-Ut}ggj+@ag1F58{h$%QVdI>YsM?xeqNKewkS;Dzp* zy3mDnn&K}_N$9WPLyYLAt9dSQBY!dY3*gVI4?_#}EptF!MqdUbuf9IeC-+z5PvXGn zE5&cGzH-_D>N5I@A$j!;@aPl0M&Bj)?bRpa5DX{W%jjDK6R*Bu9(@?jxcWBYw^!eM z$TB7}m(h1G47~cXJo;i`XZ-geetY%Z06Cn#cP)Ln9(@>2x%wiY%&TuhBl-?l`U*Yz zB%O`_dRh8jfL${F%w@vc1Ma-xo#N4l;hd{a&dYiIR}Z^z`o>uLNk!*JTw zcc!H;4YIe+GWup)`nE!!kfC`^!QQ23wNULDEt}!4Y%|qz+$dZ zMt33(vGhe2_*J}#zMga^{;jd}Eonqwm8Gw{M_+G`zU7ua2jlU1us4?p@Aa0xERQ}Z zpC-J|So-EQqVGvdU#Ul5KaaleEPXQ17cTz3vh*$V=u7tK>kN;2)3+LpRXBYe;Le-A zD?R!!-Q$K=&Rcr*?P)~cC`;c~k3K0+uvYo;JWF43ba?-rZRz{eqi>K$-`$qJosH;Q zW9f@54CcSV9(^BJ`s7?&xcJ*?>Fe&%H`JrAInvV`fAam&aQfuDs5d>bJo<)t^vV2^ zS6>=#3a3xzqrCb`J^C;m=cdOTOW(td=sUyGx6q?6&7*IvrBBY8h4bH?mcEr9eHk8o zA6xoXLtnV^E9X_c;oa)dm*vrS81k<-{<>p+JDk3jaOc(csYhSHqi?jOZ$%^ePGxGBaA!wW}~^xb8Eu5 zOGcY+F5~WkFz(WfBha{88phrHFz)0$@}Y#|zA)}2eavNkKM!~E+jw2#rH>I{Zv6KQ z+mJ-jW(4F|}b4#C`Zxc7>GWsIm*!V&0A zEXJScljp`;`fk10=ZrQFgT2w$#d5b7FV?6z3J!P~cb(wQ8{Vzg`<-1~^>e4et$A*; zrEdye#8GUNz@7Qo$I`d*QNP+NA>kr|1E|)lyNau*Pd>E zNBRZkGT{|^vbob83w4Qzmos2~3I0T10{$dUOr3$BPSy~=v(r-_7=2h)4RJRQ3wGDR zFXl4tW~<lCqk9RmUXaN;x)p(BS0M!KtbEot&KF`FGHu0gwg^KK5AHB_sB3`AeP?o1{V%rN>b{ox7YnoxXebr90hk*bv*RN#K>eky)?oZGyk1_-lc` zmiRj?D`r{jvV>)AmNj1%zpVAL!b*hB`Lp84Ao1MN0!-m~vQU(%HA@qGuqo78l<<6M&(h+Px2F4A@P z)sDmV#runPINi$QU)h_`U+#|x>~UIMqcnAo3OLI;FHcw-vnFzN>ua@kqq*~Pr~Hia z`^%%B@g<5)=jA(#ja^Ehcc6`aO1Cy^oohm#+UI%KcadEq*TgD!TDQ|@_4eDo@GE`( zx@*3$!*$J$hId@KeaRPVI;3Qo=Q-EJtZN@=v(^n|pXYa6@rCmw;(c7Fz{^K2*w7^D z!}_!hAMTC4`NO?&muBuPfB&{0M#g4-xh*#1%h*__-uH5|KuW-;Vyk%{-}1zFTl9&2GOkODE>G=` z_rLCp&+7G?e_zbdR{LY(ef7TPzwEgDk;ootfv&jg<$5O%8jg#QbQ*{7KdF9Q8QW#o z7rg_Q*0;B{CrK=j+mB z)WZ6u39ZX}2AXHJE{+`4y0}~M<~@VcM7zoN^_w~c>gty!zkFZZ=(d3)%Khb$ftxaX z+nZb>Z;fw2_GdjC^bC=?}uA-?+pl4w7o@%AV4|DO4(eXbCNA;$TDjd(;*JAWx zDjYf#)tlo2-4TkEtc9hKZa8`ck^{FR6ycx$PZ)Gs{$EH3Nz1rEU00_|6iY?i=(y|- z<%^Ifn`LzA$f} zNSSHrDKm>oy`^St%-}%6aLM;I?W-qGF2AY#{qkKiw${&2*jm3ZacljOWGAtHvtLS+ zryTq@@?pd9w-_a1Z(San-8`#TpmlLXaeDo{;}HHWx0mlm=%-8Qw~Q^mwD@Jz7P^G! zGA@2I^~FD757w3cq`Ph>{{NEaRiEmpBLmIL7jN(-wFpE8>ZGSM9sR56-M05g>asm9 z>DV3fP$wknI-%Rb`nky+Mt2z1x!gCXb8%96+hSkRQN?ZGw$*m0ThD-h&BFS#RSVbz zEk_g8mvWBza7X-DBl*`k*9-}y1)6s2t#md)zw6)IgU{IgMU?AS%8^{s-l090KH$jC zXuakpH@(G4a`r8lUpBhVZHv#^5g%B!u@2AoC7rSTnaZTBXQroBWwwt`y5QZ&{gaw) z*`MH#xiL@m10%cSsi!;LN~%`vPiT5c)+77l=DsZcS!wpM`dDF z|ExQvFTnFt@%(J{{2>AT{ER@*2VJY~gb%LLJ}8X}@j<_xPPaSp{Jg-Zz>utNGeq;& z`szCA6YRVAs4<#7NIWHCNFX)PPKB{sRnI_w+#@a#{)pZ%kGWAaOsh)Dnl{7famyF& za-QCw;P}40(HDc*8LaMWx-Y(IRN(0^a8H!PSx%s*GVcjL>*v?jMFp0A5wrX$+#8+K zE=%qg8@baTDEq>sne=o1IB?(uq+6!b1G%eyu5eruDcH3f zIVOlGTO9F6M4dK? ztXn~og#qWfo`F@BnSsc){x!pkU#V}iMY+WIpkqLCpGb*;Xvwh);&RQe7Va;3=1USM zO(jlx1+rC~WHV06W~@iQ(i`rBm8~8qFWpeKeA|=$DPRATum48*8tGuvDdlS^%2(5@ z59{;hM=oo!EMi&AvZ!Uz7!f-?OHtZ}kG=|}tv7mgbJK3hIB`eJ{saBvlk#^yyuW#T ze89i6-M)zU(L1iKKRaz0N?>`_BB@QI$Egyyu2Pr45j%QTMeWaylyZQUL6w7)Kt>=& zjYv(&+ryF<#j@C>ZnY_$sQshW*sn>zcYR`DeP!g@7wet0i1jgRnyhn{MO-IkF;bPv zo~pJ@48%&gyjaSm{w3v7{}P`(`9&1#_b#ko^H?rt&A2UGx$LgnJbzML0I{ZK2V_p6 z$M#+*mr@((=So}U>(&-H0OOAg{GUY_K z-FtUOQ}|Q2ffON`pATj>SGc=LSHLxe?r`y zBeubG8%(#sbQ?@#_b0^e-2u1BLjtf%mJ%stPxl=o19^`uR%K6@*GRPH!P2J7qcMqe zOX5G}?*B-i@}D+OjVTVP%~SpFOE$z|HoRBh$F4U7ZmG|zi&k^fzHW(uh4uTATaRu% zs#7`UWe0XDKCC#aYg&Ee$x>QW0Hm)_;xpo}{d;AZAh*z)tnPv$NuLTiZ1~kga~frGs%?lO|d5{f^kV<_M=p zb^v$fZLQy#mx__oi}jItFV@H4FE&p!_Y_;q+SD&-mL2@J=_vGR9RHWs`7s*u>CsS= zeeq4+w)zn6n5O#;DrA?TCX7H$7@g%?=0~q9YFX1|%QyB=BO8Bt6y}NN*Y8W~v7@d& zJFV67tv@^+=^L=|tE~8OUuHG!u;Y>a{`kYUBQBgc6&C+GUtN>6QTuoLd|Yv;yYEN0 zPm&mD?v7FPFX;>EUvD8MM_~+}7C5e0LJ2t$on8Kut684=66@9_8Os&a+S>;5`D z2h%l>9*C&Zt28la4I|e^tn;ryZc!s&jIl%Vis~a@*v#~nFO>eMHj}(DIFMQ#GZE@lT!cPo44qd0X;-qRyz^RO($}Z+87@Vcs-N-J3Rr~97+f{K#X-50o_b0?WygwoS+~UWIe=lym zbJbTdKBvcE%ygt=eO6|A5mV-iuI8RzM6;aR_qUXOij(ZljP^ncy!tDD%m*QLtn?$Q zH%SO;Hp(h+d(|q)y7K(`;)E_co~~$(InVhO36G82H$N`&D}QWWNBFvl)8%QblP6~_ ztexa~-{n(0ft#sJ1*RFeKn#>sz;?!l(M_cG^a7*tfX}QdcOcEOd~k-wVlOji>K` zf6C8WE9ECt<5!qa!Gk{1vNNjOP(2_8ZS4}}nufIxkVFZ8OY zRjX8}+SXdHwN|ZF+gi1)TB~ify|(q*m$la0e;?NNwra2c@Ao%5yL&b#sBOLXwwL{U z=FIGGelzo%-)nv|yXPDfqld$9hr&=+qdBr#bI_gM#;558^>#}_H2CS z+aCjFf&E+{s?M|>?@AP7n$tJqw$k7_HgiS ztbHcn`LudKxdi#2)+R~(e9ptuQu5i;U&n) z_5~;4r$y{>$KfSbI|gn%VONzK#*;R`uJe?QCD-_d{WhfZv^^K|{igjzU_Rq~2Hco# zI(tA?x#|1@SQVzT<_N>6#A8cPhG!?Qna(cAaG&XPO~mVjrt=WKgmA6td=%{Z zu<7uxX|6M!Y`kH7z3Kb~z1(0rGw~&rkC@JG)ZK_)K;BIl2rBS~>D-R&52kZIUN8Nl z>2zcC|1_OHV}5@!otrS76&X$w26{Nd=@^e+T8TI}gNR>7oK0ZjYY~Tkjq@K7XDPJd zR{)~j|BE=6gKfW#ILCr-zlk{gcmeab5hsZeeiw1B$9PRq=ZE0=B7L><0yyDaL|R^Z2lqRy-6b4Apt zI|@IQ8g*VoXRD&liO`CZqs}e(g5Bza;^m@c3RH4;LmG+(R*^9%_3q&&hxmeJs!6uQcA0=R619xi!zp0p@La z&i!EW$Mc+h=<^eK&RmReNujd^W^ietvme9ePjOD9IZSc*<%-@Sr(q1<>n(ETfLVP- z&OQv=U*zzQI|hoJ0!(^)kz-?;JBplX7~zZ}rv)0jv&eZB9NbmpyoEk@7diZe^bZv| zXM?~qi=3U9!&ybnAIl8m>>_73nx9kT^aJJGBIi-)#Cb)|sUTwBerFekt=aF)0xh-s zoj-%E_4}P$pgj%yok!sz=I?h-0M8cecSgW5v_9s18Ffn^b7mr2`c!txW_}TqIh}=7Xxqoa zpCR^s7Wh@d0T!M?o9!%|3^wjy;dNN(xyPgMCz$+sES!aY&S&99h~WY$0A~*i{MU;M zS@;due-R7a;OE6G{1oQ3FNp&G0pe;Fehijf!@~D5vuj!43)~-OVI?NHs|$rVSht&n zT+E4YIA^wlMJ5ZM2F)2P{1KWGVS&Hh8)bois$;RR0BU2ia3Un(urLmgOcwaVZCNa2 zK@iz2@Ta_DEPM@ilf%NAQg~MuK7m=}vQP&V$YY@jWZ;btBl9uf6tM6xn)B_N%u%q~ zLKd!vp7EJv=JOCTU*gEz3<^ng<{6+6fB1?Cf^``z?0}z(u<+;OISUk^>zD-!zl2zA z7P??B#LCP8>r57IfosTMp%!GYosl(rI`SSfatrRWufqpPjR6S4<-S(mN7Q{n-%-H_{}k#)VQJF|elTx;E6jw8jFtMU0I3mJcck+mGEX??_u zkfyv>LCl%fel!0$P0YKBn$g6r2O8TDPcnn+l2{TI*JI zx251Bh~BzQ-Srm4If;*}y8%V$ClsMO3-%SF?vv_nmyvZEhq&F0oB+b|E-S%0WqsPr zKLvspp8c!p#85oDOOuKBISuPG=D7Ws+`@tzp}*GMip(bp)|j~ath#$a5q*#9<#F!!nUNoplwZPCthXL8^S`M{c`${PhcqcqQbZ4HjtP&xs4!Qk z;l8BqR;%H@tcF`_Wbq#ftVhhqX&4|UO3lcLQX_Jr6k|@5qRNSq6FE^5G2Aid1Iey4 zN5VJQcTvObpFj$xeI-;h!@dgOi2ZHYRn&eGE23o=0LQjB!UZ_?ePBzb{cF@_+1JB2 zW!tC0@M8A;aC15Kvv8Wj><;vhYyTFCm1px0?egtE0JFgU4Wv8Vz6SCyw5tFaVe@OU zBki|A;wbwIAf(7{K9+ISLm+gF{Yl7wti2okjI-O&|9E=>C_KU*39%L1C&BAYu+IX1 ziCr^|(bd-hFSFOc>?hhYAcaZxQD{5ae(Okl>Dyk4v8LExhnJaZ=feJvviT#{)9liz z2HxhgiXxbvVoiT8zXoZ44;@+d0#rNpM@Dg~BPMgIlL61MzYbS4%>FV+&$W*Oad~zN zB$01#s^V0?45kdXd+5^aTS4LoJCDxH=I`*2vfl*hMfQE@d9*zYUVMyw2YMc7|9%Q4 zX%t=!?wU&qt^-3x90%IXW+_{s5DU=s9YM%^Fv46Gggko`Aj^Z0A7aAhiXi0Qjss+65b_9?Dsxp3VnMd% z$wA0;j7(w1w9Mss$50-l2FTeJZp}DI&|H~!41MRQ=4{-oa?wVUDJQ!(bS&m- zw+(%cxyHSDL8#9=<_C~Y(MTw(xi&ACy%mjtl9`?EO(xXQT<6}j=HR9)Ppu@QkEP{4 zpF5nJBwjmUpXUBd==Yd;oaFPlvpET(A6S%_4PG=?jQ`MuoPKL#1M z0B{3=!%5q}Da>C3@G^m?Q?xJS&L+XLFjO3A?7fuJ4{~$4Vn+7eaL(ATk=~ay;P!LI z^6xv%pK8DZ=ZyOT%-?(^S0=Fzeeicb#=egB<}Vah#=eDPH%`O-f9U%a= z^ElU6(BM%d*b_D$`DopXqWNa-aLz2U@2YdgzB&bfw>03|bBgKr?p^}pg@#NpTQdgW zM%DuMMZk_xFgBcEE{*KF7Fi&RG&=FX z2ewK8p=2x&eglN!sVHz#OBJSBWfUV&HQok@|L!Ma4aLNTK+I~!W>O=DM`;4WC?FJ{ zf&!=aw8B)=%iL~c{dVjQqYN~GnJ0}kN_&7uu>_~+vMe-3qx1!r@xV2qe`QnY@Al=! zwC&u9dUO8~SUJXwpk?pNo%1K?IsX&=0i=mrJG%&Mp+VKd8FSAx=0#gD*HG=Y1F#io z+z)9H*CqnThnW4}-Ryg}JO#=iFAW$0ld=6(l^7rZy)N;}B~ zo|%B^K|u`#k2?@~_ItBc#v(@MdN8Go zUZd4#%Hu#b_m4ohrI^y1JC{s(12cLJX^eHO;J1<~wNdpC=wpT{;JWM3n8yrPB8~eD zoj^j(_b&ka0jU_PrO5e{idN9Gl%!CDIRj4qA$J;>mhfmcDxMcut4wVv_4iyC`K@3@ z)(+$MW}{6jDT)FtU-r zM*+I0T6n&qbhV3|Rw3F(gT_aE8Xp%LCy&%LJ~C_`X}k-g-iD+U;*ntq()cz2za>x< z;*nwNsSx~a=SC!@5RVR%Md0%QdVAv^Ch$&cZCm?wWaj8p08ihDj z2GpY=DM(5oI){l%dJTY=k(5j7940Pl9LOm|Qd-hA zOcqa`(I$|TOIklH)g^6G5(&DbIUqn(*>_261T?fu>R0svm$U;jy+(EP{#?@YCqNV> zK2wwiei9LqVoHe;#f_NJRY*z$ONNO{dKG{d2^0-1873~N4xZ>3B&C66YQDDua1)ZJ zfwM6HCY??Ln^hG|NNM2tnA%2xrO`nCC*iwjAlnbpz~5tKH{Z$eoP*N9BVdlMbI1{w z^dr#xeI%uU@8pO}Dntav{}%T&FotGBxTGsmG;j?zd*-wLsOO5gf5jX1*&K06tI;|C zd|YYZvpM3DUI5@*NJ`nhog>ON0`V%ocI~^Qy+VrTl5WKC{JTQT|Gm1TE4Y$g<euLS;-oND@i{(bkU1me3IhB-B-n)`-30QdxwQk|m|=C=UgpLHweH7%$5It-Hu z3y2~qeVVTHX%+xek;X>Jj`Ey5VrJ}{H}-2_t68D%>y>k>%yFID!m;;YAu?y?$TkJh zP{|6kV<0Pg02U@;PKqT)@fK7v_^5Yb48WHngy32}fHr5N{!7i6p{kE;f59ZezIjBD zXgyI`7aJ+IF-qfj zZ1S;Sb=Db((%Q;)s3>g*qO?ccUZib4IGVj97^~e%jXdb{Vk%#g~JzdE^Vu zmt|+D?BHXud0d+30XQ3JjBN35iOmx=1%Ut9J*IaWdb%|>k96J!z|928mj5<|`8)vM zB5?Nt3(tmq2n7y@m$oCanI>`Y)rMg%&b=`{Hw)ii;jFP5_OI2!>$pLKSY7OV`N_@ z_mI)Zz8vP693$hb9EPeHXXS$wqm-)uJ;;##Fh*SJ(gC$M%H#(&+kM_E*Lw?2Ar$Z1 zW8w{ZFv+!?z35~|OuWG}0DO%=QNLv|@dnulQ2FoO${Q?Kn6&`RMN-UL5fg8)9)Pt- z${VbT$?9?y0DF*>H#j*a-XOB?;d91`J6Np%F9YL6V#ywCP0aNP^Tyr;r*C$~T%XWd zvI=t)pKvM)KLrz-Ff%ZMJ%SU;%wgczG+{3_&nVsrJX-c?3Qt(&TXyknsHWWb|BB=% zC8E8=E@=9_ZoSXzeXZc~AEBvcmd|Bn`45(8E@vsr=f8W;Mp8zet&IFm01gr;tdA+6 zi2#)Uv8^0&jqAbFNwgHbv4z|L&7OLd2;@+|+?V8npHhP3>f zg4O9QpS_SvI|p0-YN)sQ&1}yjD$75%O!MWN*<$$*f`0yEx3c_avc>Y>1mFz<#qyuc z7R#SL3P;08%JRRJEtY=@04oR-%m22*yaIr|1d8Q$TK>NxrlA(d7QwZ+%z)*8Q`Zk+`D4HYwwHa5^0)8-umeds;+feJ2Ydv8eMrh19HTUp|DXLWB+nbP zVALVJL6@rXyuom=<$Qq+=?y*=tWNI@*vk;!;2P|D%r~+^-k|2755c9h|)^MxV+OZ}2hzFA^wmz#UoQ4N4Fa zjz&`6;L{3o1pw_xig|Zti8o+uxdTaggS)cC8}JXcZ$whw;4@jFIN)vtcoP_}6HDTN z&t|2@0rzF4j{~NG3GJ8}82YYpK)=EpDh{~Dt$vSj!2PgXbB)jC7lg}?PSspqlO>ja z3ZlYRBxU5MWQpZJ3IKPEiuFkaEW!eshol_w+AOjBHUJhQDa&7{wDD>H_9A(f--uC% zu>3Wu%Cr1q!LTz0Hl*d>8mvxl`Rru~%jeIwnx#Hp&J@1PMf9$;uT)w7w?O|BNXqid zl;!6m6w5|ZmOoM1b1eYX1d8QPQdT+uKo5ap`I8mqZ2%l3P~w0imF4pl8vYfwvivEk z`L6(Yl|ZrlsS221g3}NrW%<(vTmF4VDa#!y4*0IFAHwoW!Gynu<<|~n`K!t6dow++ zJKe)_S;p;3+GLEEl^1e*5{8a!X2wZ?@#k@aLEdM$Ht|0I%=!E%s zh50=Io+5B6ckK^kises13^WmG>_QwenGa^>);enIKMO$fOZtA{*eO_7%ttfDtbY*h7VQnKF#$tHkx7x;B|>ADBp!a=uR_Vqkqt3b!s1%~Yc#=@Rsp6odm zVxOj-0R9+gr1BNFX)u^L(-fk!)$ltY=EDPHC^0A3AA2GHi{Dfk_Ds6m7Qod6z_Gh=LRdX(Pm%NF59IJCw4(g z?gXA_$y08FlcfP4vnkQ_q4(XvPRv=9A0=y>ilT$T>dZ3?Jks<>D6Vj^9`rh9`yFV{ z=ck+zpW?eSV%2t3Z9o-A{!djEc)BHn=i|r<7}S>-1WV<`WQs2WjNF(cuvT~3nq`z8 zbSr=u=nBg6`4VvYCyr*i5 z1d3C(1A8H==MI`aDf_rCpUgYNo>9j(YO!GSwD`2=tpC z`fLxkZwDYD=p0k&oga#BAFRt({! zMAq6#8DJERUOTC~$Y6nay^Eg!McPR<1gnR1Qc164whua~-Ks{NLikRKBkxyL0nZY4 zQg^%EY9~c*JSnh{lTw-za#CC<%=>(0p;4Rre>W2{lojnhTb$I}5Wwq5%1PaCi<4S7 z4d)6-%1M3R7AJKr0DB1(C-s0WPU=Mf_}aa4QV-gxPU=gxIH^%selwAZu?UGNTn8$A z$KpGwR@Bo;J>=F0ofO>-oRl)%2f>Q(x=6~?(L2#3wRcL51dOs13o!k~K08#%_Si9+ z9gA)8PN##+tw_ptnr!h-*8^}Rfnp|0Z1GOd0q_k1#XB`C%tFl2K~f=Gi!CABdH~iU zDVMd>P7T>Q^t~Iht+YcS+bYe}R%K_WD5ma3k9&|LWcwQU;e~9!fUj_U+U4K~7fT28 zB*TXa*~Y5+v?1HEe%)Q@j&88{0k_cR_DetaJYe4e9lHhgt|8k;+@`65@!^gm*`;e65d)N|pHl-ZC2uX?giwd|4 zfYS+-knKyB__)sk@UKY98-7_~J_o?F#FUWj5rxU9)27tH%$45Yj^d5rMIJ`k&v7td4)?k825`;&n`UdS47bE7PRB|+ z7D<^jExkZpqE62EKN zjwB&lMl0AwcF?n-1B&FQD`x+aLV8l#nf#ePX7x0e5#fC}f)}^`SQe5lril zE#bD`?uKk*(I@%rhitdUz|o7NAt&|WYR%z`qvE6vVy0IkDSvcHRGd^43*4Uwl#uOG z1zZMTGm=`1_D01?T>-#eB;}+oQ+ffBM^ z85Jk>Lja#eQcmhB1)K%1%vVM|C)IJHaL{*BWI>MrJvU-_PU^Z~#Sl(PWUZal=T!Gz z$aW-p|4y)z!TZWT1*?a2Qo|tu<^94=s$A8CofJoIQB{Xr@3CZXlm9xeYKnL}E#;g|o5!;0m;6cKY?1K@HbMc|JV@NxhyB2b!TRuehx3Jye1-IodCZ(5=n9G znn)+bx)p#y=o~24Dcm6YD2109EXeV(n1`rxWXq)W$hJ*}#NYSJq%$ z5$hZ!)~7J$qa;SY<1$x?H3upaMN(otNr|-)fI1{ktaH)V5Mte(!bnf7_Z$TpihP=s zSby%(RHVdu9!A;D;f0k&N~|vd@H~OSwW5ev>vXt}5+qNoPYX>Uv0juyjVsn`5o4P_ z&j?xT{#uM6{P}r?SnDO|{Y)e!!B;ZGT7L+@cL@{%f1!Zcu)`>gU99!h46)WZ0L(=4 z#CjG6cvrDrJ+xRq2RCkh#V1>dHD0I5{z`^e>!ld;JQ5>feKbR?^&0>@Mxa>hV;N$t znJ|P5Bu}g((bo`Sy*Y)Eo>(u0OEhotX;NZ+*rVyD46)XE7-bfcV&zR4Vyzzq;2Hvj zYd2+xwf+YHKSJ`vdaKYB66+l))VN~Zi%pif*{4NWYd=U*V%@C7x&YR7B28E%c&d`% zjR0IrptzIM6!1v^9wSinZi^D@+W@?drcDsT5{Z@k} zyFrO{A=G;wk`n8DCDy$FoKK*Lb%7G=lK^}L$rJ0Z6op|Y+=PK1O~=UN$Af|iK1E8X z`#g#!D52&+pA8y~Fmi$t>Sh3v1Pae4WQeVP9)M3Hc|zTZz6PzV&!nT}#SGB$y6M>} zi8l8y!2+U$`noB$O3ihsbt1ptn_{cy0Vj92^6jSgDJK;8dJcE`L;X zf>B!*U;y!McbQ_6KLGq0B*n42OfkvhAeVB=S(tN|DJFR#0K1Sp=^cx{21)OAp9s{s zCV7d8vCs2qQPPVo)U=$Zr1vxQ{#_0$f;wLbsu>fmC$B`L7bxJ309-|&sMj7Py;lHu z5y_L@FNMH&mEM01A~`6%!a~sA>C>*Hcb-Rkr;^?bjCC}bEAF;aNv|7#HAtTHwxJn4 ztL)`drI)=_s=zT6%AT8uQLFt?mGp)+VgQj|wUXZL=zKp%6^>Oa=~)=$Edqr()uz~9 z8-NRtJn6k5q=X#mD4z&ldVG9n=J~WJ={@PulBcBiS#)?Sk`h$D64ZEL4JW1$SfGHL z062v}QLo`jdiMfw2a+efPvYi1*k0Knk^|D4d@JH)^EaN`P{ONTgvU6-#@~qLy@Qed zjC7>P?l)q1Gl6q7k|(-pxEVrp6+Q|0GJR<=hJ4B!Qc3P{Z^);_>~`S(RKi57pAxHk z4);$ICTw|1jIMMsLRlnFY@Y_gAfub@6X1z$@>-s0ebl1^N)G$qg}&6(KPnFM9NeEy zn8@d5@s}^-{s)8!Z3hGvhtQ8?5}i6I-tuhR_aS)_TaHFx(U1Y_Bt#y@{6Vw^<#hx- z#aSNFN?v?zTM>Ph$m<0R`W+G@@;Xc8m4kgy6v>kpXE21k5a>3jMt4!p)~q_&9HRar5se z{2Oo1!c87d?Xr-j?!`?F3MV2RbvQzkMf2?J%_?Kc|#&Bi2X0TA$hg9sYVjQ`%u`z8&2sK6!!CmljUm0MOfG{1H77o zbTlm6m`)lm#$7+sbdvfPYNM7Po$%s<+O{v?me;o{(>Kh(j!W#6^-0hND(OC_FOjL4{E2sx0P$71nSQ}I>{lJlil{MC_oH44f3BKpiipGeNbvH165 zU@MaIP%NGWDw&)IWATOw*is@nUx>y3eKHgd$@yF?z6m*#b5AVZR{?`Xa_)-7N26~h z=Z;wXmoxF}V@S@YV(|&!36t~jSo~lf&Tx^O1F`rHoL4Y8H^<`VqaBlTBWNoCZAi{_ zu{cG+%lU9D{*6LB|3Y&1#p3*$43l%E9d9@WbRszy#^R?Q2`7l;To8-@b`rh^i{$Ky z#VgT{$vHn3{|WkLa;~uBBY?}~oE3}n>tsyMhhp(lKns&|W-PuF-j~VQ9gF`A8o}iJ ziyi+3RFcW*kHs%L3Xj{7oYQ0R1m?u#^u^-EkPnm78;c(YdYPQd?RXw?Cg-$R{6EU^ z+iXbA=2-mOkQI}2YAn7ejw2Q%XHzVGVFW)`h2(6A#cu~LlhYlG?{eTGkev0g_@^wx zU~;-*@vAFwyo=?cnF};3tx^7V^!4e36`FEdCn$W^zu6#s7eLFga^t@v+cN zCTBJHGZXwla!!uL`4`ztPFpNq2zr^EL@a&;f^#NkDdvkYnVeSiQ-XewoEGTkFvuOr zX~r*M6_}HA3uBSoak(8u1!jH`{OKfo8FOwdf>}k}A_Ny5Wkhmk$4-o$5NkxAR@98- z&W*)zqktxW_Eg}Er$tBsEX|aH4cl;=TdH}sX*L$JNvzapEUZM6oIH%mo`)5p=UB|| zHFsEGaBVuMp5qmAZ^n4RyoFV+2u=jlY_*BI4Lwt zqm|hcQe4LDX$55_KU8BZLn-am0H|p!Wp3Swjrm8+_#m zU}hv3eK6x2tbj5bub|Az6qFf%cZOXsuUBAZ%~EVM%O9 zGo{$h>;eU4wik)Y*m{5^iUa6cDyo7)xlUCuyAerMuym)Yz-Q>W zDN2K`Y(OAXW)y>IbTDHhj+PMmRCCWJu%LMt=S4R9^J~-dgCz9WA}g;=uz=VSW41E8 zN{a2wICnrb3)H;Hg~t^RKGR+^0LAQ?kppbE^Z-jsR0T8Ap=gIOx~)F=sml(dXohjwHWb4B6`W^6^U-+GV>z#dyf2?hwpD8WiFQzWinrrIX_wu9IXB>XBp zM`&ZVQ;HqT4kD4ZwgW7wIeGe&0g%2JGn3cM4<^w+UyhI#{4%z&NQ&*u z`jDc=zys$TV2Oc>VlN7zDO`-@L-E{ar|&WOE6O{mIqrT(nJG_#x`cE#fo5y zwm~geOa0YY8OB+Fq+TvgG=LLL#ZZHxpUePG<`6hJ0i2vLj(<<3gw8TMSBf3X_DHdn z*0dR0=Jl*E5&wZB!!C2T)DVbW@_wql;qOq zP@{1-3yCe56QRK9eFA?dGjsBBV<(!K?~I)>Nj7BUT7j`WT&20d9)K~#H4Sjk%Iu&N z4|}e|p3C^>@mvX|-^{L+;^C+WYzSV5qoN=;q7sxEV4!m|AahuS@HXNKJqvwY!bJF^i|Y-KiD zL7AyX>#fX6kkr1Ir3a8OBKk;s)dLE7FjHeJXU2wrGMg>M<;>K>`K8QMuW6+;R(eb@ zQ}nH1rg}^;Q*8(BhqI-f9QY`VLF^`FWHEE11lf(oa=AFs08Uib1>?>9n7ty!4rWvhATZ;2P4rVa1b z3urJtLsv2G;Y64z^c6mOB7}=uMOvFr+HxPgO`~Iy-j$EiB}n8x^J|eHYGyY|v7INj zw<{#}IgRZ%NfUV5fw`r_k#zuhpZ3h`Q5X2XP^OI2I@TRexnQEKx+op9YN^1Ox%b@F4 zZQJ~|p3Be@;a=+?61mD;aj8vn34AC0obaLfJ_{J&IWuMHhg~r^cGwmBj;$4{A=f{) zE5>&eFbk+Uvs0zm!K_a~neA0jW;Y-W<(E;#e^#brV5a(7#%!m8GE;rYn{m3YbWcZs z8FU}2uN8h@3BNCSS4;Pm?zu^}j4pA88eLBGbqoKwiFP3z8}StqMNBurd^Hld#B7}u z+ch=BAUS6%3}$K^c?XZE$HU(vNFVdlWd4-@ZWu``ub%CA^9-f&Rp@SLw0u-NV zuIYdw4rHb}3OjPu(F(t##Nb}Cr4#YuY7WbTb4cgK>A~3%{WHhC#4R(w775&ArUqZ8 z2S0RJ2z(>px)0(OoM(1890w;3hvU!${~C)T6rb5>S>z8p_ruQpy*PK}FICR$>aF1JNeiah<#7xa%nI8O5&YedMXvM4q zNimP5DM+YbHVa8ruym}dU{>!{ppfRu1q>`?7MEfNvzbzCWu|*xDzE3TyCFHwuXnRL z!A$km?)SDd*jqw+J6_P+nQ1!H?UPWAOZhDR$Bt})u)1*_4JhOa+ycsMl@wcQlZLHW)v%yMP_V=euK@^?R+^0 zSGH>Sc4m6Oq2+d1eZi)~>T4WUU(thPrstoo8*SoI~}_tAYN0)4&Lz*=?@x`Q_9V4e`u&P-1;U1S~j zrurRC1yQ~!uiA7lJ6fQv%yjeg#sCE4a9m6-;G!Bs8<`!}X4lFNYcn-N zU;j8^@?mX;%#?Es#4U%lS!*)$e?2|4*?{I%d zip%gh#I*`=h=o~FiV0?Fly-lVL~xX)2mDdwyY*@mZbZ^tjHz$}$xL;-oSCLL5$G#H z!c|{`Ug8UQCt`52=>){C`CgeGf?rbRP;8U#bzemjYNCM_(LjqR8ip=+jLblb%s>lL z8oJyTIe`{AffhL-blkcv@&hgM11<7XTQDvsrfHlUY~Zt#-@XrAKK`lzevXe%bqHKO zzWnY12?1j>ef$*xWGS+Rdg`#68Ak~-S+^!!+IS!Sa4Q4kiCQb|2))NZ{Jlun9<$T? zRgu}3kur?k1;_%I-+xFIHA#52G=T0E+3v5i7r)~)M#64qBf;-7r7rfm2nnXgj42b}^O!lQ&nP{>yJn=AK>CeR0tr}wGy(##tHx)&H7V=u z$ulRpwR8)6k&aHS&72oM13x_&KWeIJj4DK-LJFn(+OIWB<=fMw&Zdj4u^()3iLm22UNT(RQO&&#~4W?f~%B<-O!i#xj}4YG!1q zB|H}HQl`17{5zmEJl8lY$aVRV4{CcDA0W9Rx`3QRQ86v!q|=S@2Uw)IaNCDl7C8!T z!2%hOGI48Jq(R%pN%+Z*@!q&DHfrS3-~308$x`#yB4rpe4lw5<(+s0p9-a0`d5&~+ zrweC(kCbZ;Fn>hKwFj6#g%tR*Pc(yF@$$U_f2old`N4~82`?_yyy#+hX*kafc>T3- zZKRu2H(oz_yuTHGx7#n@%Hs8g%H*{t7B!r&a`L)CWgcAPKOKT={4-tn3vT|nn}^{~ z3;};P{N7N%=eqY{IK|E@3_n+(gW(#V)yE=Ht*B0qAiazf1wV3-v_1eNkCMqBZAaQY zvX0kuq~qOmC_Lioeh=#zx#8>OKeL`?#`#o#LKI%dd<#E`E&h!j$uKJ_D*HMsH}v;b z_V;yF_9gqfx|6+q+XlM32D;Z*cJ=M*9oR-dSNHnueck$Ys}GAcK1 z+uB{(xutt&WyO|lU7cGh`!{v=byxOv_jLDn_E&aSCHn`quiw0_a$wuGEnS;BH}~{c zZtUtxcJ^(poDomXOjgCKW+Z3C2`mS&yk}cacX@Z`y3OS?;uSN?SzUqZl&Z?jJzZP2 zukWth+S#>fb5HmGG#UN7`hz5F+*Dc9w|@KPo^5s8`ntXEDKN{s3D4SMJrIjDIMjQb^sg(o3Fgr55#LAaal~pMDM&4Ir^ciLe z5gt6J+Qo3hX`B2s9gM&n>h@+hzqIkr5?UDPR-JtWsiBS`%$^ zjw+Y3Y!$_=iN#hC>X)Iu%qo%rN0)%E$iJRbZI|Ezg=2v_nv{IUkbbu;I+>^->Kf8f zftp;WS%1G8CD{G{+0JK_hD?S@MsI-O^qQJ(gG0>?}W~-FStUp22crv!s8V?|+IKmoZ=UO?FtTE%Q36;?NiB?W| zMMgBGzk}#p^#`t&R#+n@qj3eNg&EC-4rJ3DBD+eg8c=DKFT#X!?2*>wqX9;T7}A8c zms|OfKB`P!NlAv2GQv}#5iEPAP&%U2$}F+Qmy=jwBaFwKio0>5L6%*5lIp%vb>A-< ziSF%`?tkNT@3BI$<*#JO)ftCi2q^R!QU?K9<$Hi-YYk1{u*xF73%&yaD)Evy>jC@ulsl9Mj?zP&&ru-jX6RYOIaFY z`GePA8e{p}b>l!ZmD%rs8}COqz8>h_s>BLN=iyt)gi>qF1kZVZ9r@OTIDj>GU8k^Cyqds;`5Cyr!*jwEb1BkZ{rykI2^AFgtOeYYMaKeB}@^@u@Mf0OmT zS@nJt=dnQdX;`H_tYVVzZ94e|lXj#c917=>O2n8th~WHM0ue zE3>Yr$;g_a)b{VJS6>cv|3NV8}Qf^nYk( z4c4sTTC;|~SIxRI^L;bx{dlYgz3$z}y=n@)0b-F%H_x2|_tZQ>!iU*LMilWXqN}V5 z@gJ5wi?Ocj;VgR&%+-X6(#`R%3L)5pVlF0VUuaE`bv)P=;+|NAH3^M!%B)G#ff-kh zX%0tOyGU+E(C-(Q$iM?Cmd~;;kg8$!T!aPK64)j~RWnjlQc|6fnc@j9&mspIteG}~ z$jr%>c@#fK)L=L_4zuhUki`+OD1n+RyTv+6@;MSJ9bIDOa5E9dMgb9YMK$oLlf#x+ ztrOt38ORMQ=gtH%Wufdq7$Ij>VAgZd5K-_1YglQCWC&%*vT10~*jGrvh-&7;>{Zru z)ErT2O-B>pG00^IUtwjqxY%D+OsNmZP?`Qb35l5SB(hicOOl`I!N(=SOZhhk@a%ya6G*5yFzB3VWq$G1)qD zoMp~rU9GO;ZiW-gi?qn@<@?wHVS8mQD6>XSw~p9tjb=XuHmI;8Yf7Z9pu#>)3KdO6 z!p17HR@F2}tI|`g(bE8ix@2Ufi1@?V+DN?pCuV3ywpXbAXO+9PtWtVRX=5FPlBYz+ zblPg?*0Qm9`})iZYo;>kMaVK}wOkaq7|i`!{K2Xr z90J|pDCH1XELvra;!-K6NmkB0t3=$x=wd4etImAZxIUuZuEvUpl_fvYNSAONT|ym8 zb6DzrFV5kCVIiKr2j?J*mAl^O;3#JNH2*9lW#O-sV<-B*9Dmj4vT9+;AV)3x7+Lh) zgJ55_p#(ThTd9_Qt927mu$y#OSKmi2;vnq_^zEbA|;W&L_t z)_?ieE$hv)tpDHxUDhwl3n^)4f>sB_8*IB6+%PaD#kCyi4b z4(8aI`*J0&9fRQ?BJo&URo?*CKE@&g5ftn=`) z{5LMkw+~O{DK-={5a1kP$u_*qGwkt4z(^~DRxQV>gzrYQJQ5FTu-%$+ z4Dwwib|m{wv2*jZ>d>j#k7a!Bl=HAHorvAsOmr65B=fl#S8;AiQH^a77U?6@V>Rq{ z7s~^yoEcWx5tccRb!)lHLkxwz-O1J>ltyyPgcE!MW%oZDhXiGKPE#hIcBNfeZf~R` z8f%qBb~3!fzA8VmihIx_8Q^rVgdI7yK&Mq$JY*R*-QG=RRD`_HorPp4&*k#1JVX)2 zc&s&yJ>p469>T;b>`%cLu&dC@13|fytUNxw(h=ljaf2hkKD!*n!iwO-6bl<_JVq?A zGI6SkN1iw-08*tjRh^PBdK?at=2-da*aJ7{=QQnESGghFMmo?jh<5TLo!oP~TcMrR zRtZ^DX^lP+j4G|n$WL*wZ^_iqhx^F&zgts2H-fDFz%*qs<~~SMs{b}ksXv6KoImpK zp(*acf}ATfLfGo58x+Ml5%Ym=G(k@mQ(G7uGZOZcWhNhR!`{?}fDgMZQ79lPW3lY( zUDcVTRcAd_XS}G+DO8;@6*KRu7AFAJDdO=(X+}VHmCek9}n)A*P>M*pAjF~5t~G3ICs8yBn0 zDk(07dz@ou;*AnKEyhbCrRpqn@I$_<#(1v8%A8@1XhB0aSSg)p<(KlEor!S5JQXTe zubm*~;JG;bD?*YvDqNW;;Ytm-26%86E{R_Z~a%P9<4%DBR>WNC_oE&(U^*g&>8Nt!3lyF zcr3xAD)+^X)Fp;%24=ckonb9hQ3xMs9EXZYi`@h2;~L$0RG~LK)j*xK+RBlrM;|$F zBb5cRu54zsgoi4ieS3J1_l^+vfeZQI*ne^%|3oIJB2b2?$AaZM5ulb?x%1q3RPFA^ z&$LFk+I*sZiE5_2WhNRfAq0;xMfU2+1Y}=gO)91EkAsdvgRN6ns(0y{tPu;L1L}d7 zRb%Dg?JRq;)`1NSD8`E55yG315-FY@R?q|ED4Y*m2Og1OWF`3LH1v0Z6a3$1=${$? z-y-C1$uR%KLf$8@$^Ii5dLr3Y*O08~?w?V0d|lVph8}sxzoU0OUP5kF?;;!X+gg(i zi9~WqLt9(Tf`(*!OG~n;rFnr@QPdYM18Wkr5)|t8WQad^POQal=Y9t8ZA5Y+u>hkZh={OSV>3%}Ta*)HXHNrFK-?)Ka%NSzps$lWgu-QrnQ= zlv)xVQgchPt)sTBF44%k`7IsI_5K9FoQAsEq|2Sgp3MVZyF^1FU~=T(^D0hVDMEwy}9xO;clia!K2QWNpX%`53FMaaDsq6nGUFN(my+I@y7t(#$>4 zR#O$9b-bQ>ko9$7y-RtB^@)|O?JZzOQ&Y0FrLnoaAz}1x!51--Te^ET4s6myiE=b_ zt#jqa>1)+ULy1UX=JB%s+sU)#{{KF~6q1A=%c@-cFs-m98e?qS0Q%Q*3u>f)x%yrdT8Ws?fe-q^JH7g{P{@_MfmS^ zQ&-cRY){lQw=HRGm#z{GHT5gg>E^;EHFe3hg*BKRtry&`UziTBy{QfM3nZ!#Y}*^E zr48-dTfq1R*p{me{Av=u8j(Dsud}zedwue>?p>*j#8-fpb@y%FuuHT)%*cRaF*dRz z*!V^WySoctYLf3@BsZ^5N2S(pPgk^P>XbRvGzlY;Ev*gB-VC&^*CrYlENpLv&Bg%O{Y{>#6Z;A^wPsiTO3c$r-hc?H*WMb$w&af@DiaduvB~a#>4L zJDj?Y;5r3*WV-Vu4e$%~M(051#;^g`H!N#}5!H6I`Jzg!fLBYlENe*2Z)#Z{?lsZ8 z01jJuK&WfY5)YxV6|UY@q*nM;jOx`1&27*(SyhyW8ra(F*DI2>FM=yc&aY`~GN1rq zk|~-r)HN*zHKYpAFQ2F3hN9uPw;#V448dJTF*Pe6q3^q0V7=i#*T7YLLJr%u?5zxGQ54K?}YHhB#nr_tyUI0b_S} z-?mgzJqMJ^ioi)U`J*^Ie(dGy<*#&Gcj5n85`_Eq|w{#1*b9hp{3k=|~%J zDYq=^8P+YM6Y&j=s(M4w{Vng+VQmiZt9+Uq-Vf1#+WYe_D|vSnzG<7tm8AeR;q z(1vY&TRR8vWntIzCQ}@BLsL^nQ%wTya6w}m92Ud0u-9b#ENf@i=H5-+eW@KNPp<_F z&x=@1&!eNQR$^&{8rUyr9?0q$aGyeDa0Y>$iL3v*!zB$^C@C`RH#C(hoX59ulazS+ zI61%%y)^4CHRUyl1s$T1+k5&qZ|vz_UxIHy_ZeF{`v;OUlI!q=>C=*({mBh|om~T) zxAmmcD2YSFRk<;%H!1p3hFmK82~Jr2{DQ8nhl(&g+o+QrlWS8TuV-U-vb$&f=1%Mn z;M+XDH#RjjEU0O6{a&)Bz8jjGGm&k=^p1K`#Es!o6u|(s1wYYj?(ry|V zFSz}M)&aE@O65yv?n>6}eVq^hS*#`HaS_TLPz~W?*Y-YqWqTmG89SiOom-MvNe8z1 zd%NIn1dBn?!HeAvy|43)t*He83it=}sA;bA_Ju+`_UGvYx1)2*_HHkR#hx>?;A`DW z>t7G8C$1)^xD8QMmrI(bDc)!>Pc;Q8p>dGW46=e#^X1Hw1qoN1>RTjm^8!|n1gN{O z(nE>0JIOCcclY)Aeu3T#VO79d)0vs;=cx+ZyVN%=X+sd#*03a{qkyKU_)Je(uYU1l z{nGYi{X(@>^0rjoBuI>R{F1_N-IE(WEWrxik&v)lLaF&MgSLf;Iwjta56`DC`tU|j zY7H*%zrf4cj_+~m^fD82Hri1I&Uu<(XKex21vus%8w3?3 z#7$Rc=^V8G2v2lD&5|WG-b91#5ibY2*6lZJ!A5JloWH@(^ll$W;wY}u7b6q}fvDRs zMNz!IQ*51o&i?MB zO3Jr(^=_ZjwXJWUduRF9nKJK%uWQpB{F29xZ`j)1-`}~h zyIifkbK(H0CA6HL33nT|_sF7I-VgT-&)yFhdFb8y%!Ez2oD6!Ow(aXuP~OEb#l%&F z&7(ZA%7*5a4n#~I!_yd_7PyC_#C8ak!jYuAt#(5r&PvB1X*M%~a~Gcyj^b@Jl(*EB zXyJPs6&$+M)HXIXu2Sb|vK7HhV6EM$TM=)Qf}S^a_XJN+bf@)IIA-ICtLRl42anA` z0x>$yoVZaIKckQ5u(O*H_s?}1?I!!Tuj7f2?jGxH9k$`MH8|vTBiZi0F8}C`3eCND z;{qKrxO`XfA(z3FAXy(CNcfpHx==f;U@u$*f`*yiSK=tEp^nE~i*Z2ehA4U#+B-_< z5C+zP#ze#Xq{L<3#8Zypmf!%Qwq->M^RR$H<{mzHiDNVguNZu*s7t%+z*$=0WWkS4 zc&?Ll1?BbVhH75i9%PBcp_;Ku+x&Lk+O8r^_@*qe_p|hrQy|z4mSK;m`ydM3d zEjcg4X{~#*kg~|b?1K9(O)1U{*1zj{X244f+Mbew?jkCY0mm7%q^qOoh9#{yd=6R4 ztoR8yQ%^mMsN(~l;M$_+x^Ow3D%CAUC=*aaPg}HUVAJSt`7}^Jz0h6Bo`WZbd?Fyv zq`ZDo>}7uA{1$bH?y+o8_&i9R)wasjwIQ|wzRA?r)cFcc=j)yCr#j!i+b?gqzuKjK zHOM2LBm1#_YK*D`*wI|G4DN#uHhgCJ>Q~c&XDv7mIrOuY)Q**1FKB4S^DucL6I72u z`&TVISx+gqmS(O8;-O}EB&DmZO6O^n-%F+m+?9>V23`)5+3?fh-C%RsGa3!A@ zrD``V#`A=FMs2N)N%!f@<{nwJv2@94edm@fILzwm#>tI$n!sT~Pc}PR;Y}1Yk@93! zi&eW=I!KRIfjx9>2&Nr#~ZaH@7_5f#=n< z1kG^?-YC&P)a*439>;j+Pwq*$JUI2#g4*k!1i0E85VsDG)Y4~&1$&3Rng^6<8{-X6 zs2(M*%=Ls*RW^9a=1~;3YnLXjzjRY6i@!&J5`C(p4ldu+R(A?RYK3^769S)HF65+=I(U62DuyMUMN1wj*JbJkr(^ z(o@ATUPqJv(1EtDH&n3qG$N2CF}UJ*J$eswtN1Y2n;K1X(2EU2)GCjiW>mTZJn^Eu z`6R;|(-j!ERl&!(K)tT8;b}+j?&GIH0>&)D0t)QHqB_FBMq&Q@EumcNZVERq{@5G%pA5*1XPX=jzS8 z6t;0I>_3yxXNBq+B$o;|u*FhkxN#@nW(q12UWN1c=e@Myt`S1u5L^O55?RAzFHANr zOX*WF(U&)H{S&7YzVM|IZ+P$V9qG`m!-ufaJY_Whb)1v~nY2$Pw9wZy05`uLycnr6`+PU;_r?qN%fw z@M|HSE`k0XczD|DzslrwuO{s(Qc#!mM1oFzeq$4k9D;A=`G(onR;S!jXt$z8!Z!e2 zx9L5Z_TJ&+`-OTy@4(&*)50hB?pmZ=p?8|D+l%u`cckDuAsj8@@HAx}5_owp4S4Kv z)m6vvivL=3^oa6;r(Vc3kcyk=2)JEzm1?%+HjP%da05g51^=a_jRB!)ucg({JMc^n)%PC z^%DZG3*}#2%^c)k0*7zOGq&}uSIdd#Sh~Vz|C)c|{t)uE*CcqD0Iz|7KaCso$ly#4 zwWfwWoXZLI?8DNWKG!ndVKk9uv`mlrpY-su6B$n~iw*m~HSR-9?A zz!{Ktuoz+pDGoeoNj;_uOj}7FYU>{>DBi=N=tUqni!{vPi_3L2$vU3f;1oo?)}#&w zQ{H3N(x!XCv-0qpGO`JtU&B3Pnn64@Q!|kj)eZ1cUWe0zgnQ?X#a&j@^zN+@-agQi zr-~O++=X5aU7W$s(8w?&_+}G_4D6|ts)mdKU*RBuc)P)~PH`$&RXqUT)_0#0U>)KM z2|+r85qPS_Xtj|J{gcD+TSwk`0AG3wzQC-xs`NznrlECBc!v(}H-=y4_k+uz26c*x z>plYUREKv0p)2)qa$83mUMH{j>;n6)A?!jX$ahUbuUn?D$urMXCIyA0gE-G+@$El3 z5!STv+(x3@bWaXw*})TK-AHpxz5k)!tGR4>O@9QehMme98r)T?@Y zZBXmD9*}C!FOulxSbu%Mudiudj3uN24~|1oC+DEi2WfiXs|A|=(4j)gCPCIuSQ0jQ z-Ko#cH6awW|BO#VWqBIn!L=JG1S0t%{6>nksk5_`6GZow3d7BHz@TaHqv({AOA-v1 z)d2=;E~RlSdg0IyN&>H{rlVG)2lftwv@-A&ub@~0Ct>1#JeI?eZ%qGEf*aa#goTO4 z-WjF55bn90G=sp#i4!RpniwYE+}i@R8G;BqUnBYl%nZg|9F;E%cr%P+BC}Ht!bf^ zK$*EaOHam($NbYyk?|ni2)w(m2@#Lj7XIdeu5|^e{gQV)txho0d(EIT_o#FEl_Kv{ zehqPgqbZS?xw*za&_ZbIy&O*k)3L4JK*cW0TM~=iqa`s=k0d$>|DmrdLfsmxn|_xv z^|W?AzL&#|vaz79Zg$C3zWP$>js>+z;?yZ*l>c^gds57SXYzZ=H?lF31O z2bXDNoSB<5O#Yut{$mCoJMiB&wYj7B*cVzCMK6wAl5vGuo4fP$?A+0{vD4(UNj?+u zX&Cc#L*)G5vfA89d$KOfyvVuOzQnpTx;JtedZ^2dXDrOlomBhGH=cU(iLZa{tB>az zwXqsPVrWx>q%Z!5UQKTP1<^f`3(>OenXf+nST0~wH3ITh!5Mu4{!Qk>=tYr>fwwyQ z8FmX)^f)PiTQ9izd!iRcE&|^2>}TB30WS&Q4K;4Cucp+#P7d}J#5+7@DsS6U`PQXG zp#B_Mi-7-WSd*I~)4xiNN;f=tuRT1L=CC3EBMI9|YYX@rI`6t0rH~J(&y6eVZxFk0 z&m9e%60e2&&&b-`l0BIhIv3d&TbD#HjqHWJdH;z?RQ_*dZSMFz&V}|x*2U3FB9{WA zA@}%xfMN`R*?{?BKc`KPQ0@0UkGKgj?493=0$ z+Z#c%vQY2g2rhIkALGO&(eam3)> zC-4sQ0o(u|N|5x`i$cKv^lIN+q7jfQIS;68Xo@Gpz0__i^@#b?}_!GB>4ToL?Tc`AOUfiPVD&sU*k2C(@buGt~{Y{9Sh zu(G`p3lT)&sr}~&{_!3bqjdj@;Geit@pD7;FiQ5X2)L1opD+0HJQQ-vzaqx)5dQEG zJ;Qxulp^?__SF7Igyychb^*=R)KQ%Cgz)1b z{CJ3-ptmP~szUfxA$qDp{m%;F&kE5qD};Y+2>;j+J^aUU|B4_AOO@~Of`8CM@jV4W z5o2};f41P??zz?3UQ2~v9m1~`{8v4!YOkd5=Z5g-3jS>#min7oeH+2aKq~$7LiEhj zsFFvF+7N!N;Foyx*M{)xL-_TAf4PU{dtQPf#{3Ze{183!y_O1pVF-Vr;QRdXEl1%m z3gIsj{71ZA7kMRx-xR`c3en?x3WeVs!fzIQpFho^{#!%%t%5(`VYPZC)qf&{pAh^f zJgkIQQuys5{C2^Az{6_yN(z5j2!C0Ko@F8Y6(Rf;A$nGX@K=TKR|)>Z9@Z+a#6rYa z9l~E7qR02V3jdT4{wX1PP6_qDHiW-c@O}QQ4dJf~;jatPvo3_cK7_wMM9=yV{)Q0# z2Eq6Fvmu1PDTKdC@Hcr_eu*tmbeoqL$Cqz$A z2){Rk-y5Q*H-z68!tWFOgC16&S7ISz4219pLiG4EQTRJT_&Y-M>FI0bi zsQ&y={RN@=3qtjKLiKw>^%sWfFAUXR6so@{RDW@({^C&mC87FDLiLx1>Msq|?+w-O z4b@*3s=q8$e|f0hUm1xQG5#e~|1Y8TSA^=X2-RO1s=qQ+e^sdds!;vDQ2oA8{nerR zt3&nIgzB#e)n6OBzbDzH{RA(TGGwn@i+h4*Aq~fV_moh5cj*4&(EWbg6Vxj0vyBHs z^)I>gjKqdxzx!6GzBnT|ey%Ya_xj@eR=f3#gocCS-J$xM-FnskaO0s+{Y!4Wn%@ZH z%~1V#94U|_)&D4CcHoGCR)v0RsZ9SH$(NsQ8m8m zzt}ht_xh6Y-THO_hZ`lv?oj=Hx1KBUaO@u+4AsBn*4In@B;&16eX$jk-;u^_-0MsD z@7AmSry9FM^*6iqs{d)mL!tVY-1=4-f4cEzsD8Yy##jAU7_)J&FPXnvulkQ09}3mq z?AELPtBeOj^)I^hs{dKWo1yw*C&>R}jT3RNFB#vhzZ<~e*pKZF)$e!fd5%6D`>zK> z^*;&S=Vj{NmHo}cJ@xMm>A%`&4b}I%_4i8sT;s}6{b${JHU2!~*--r-L-&)iQpaD2 zdydaD{^8hvb%*LNaqDl8@#~G-LiJyB>(%)4jh939vFz0GP6*wv!M#8Kg~sks{YTyU zr)B&_#uq~MKXmKW_)W&2L-i#*fOap+vpIC%hkJki&Bm3X`g`1ZMnc2k<(>)E|JJR4 zLFyAmZjL(`GLBb;d-nf0(r}~QXbIK#x%I05WyTeu`n%nF)&C0PnNa=fZv7L||0*Ld zu;G^RanJEp|ErDWP<^jkulhg5xFS@4k6W+kUu!%Ys(;UejrIHg@%zkn24jqM$ToJ_cS6|*Aw&q-292_tELpRKge+Mri9(d3 zBtmJSQhZY>ilQtfM5U7c@9Vx_hjUId_&xsT@!)x`&wbz5XSwhD%-QbGVY%1-zRv8h z<*%}QuyW*ZQk{Ka%P+FrYu^J-u545;tp3`Ht^Nu6m&57r+#9xh9Lv4@1Dz#d%eS%I z%RkupI&AqBmalX34|VcerQGc99s1Ae_wuJXUBi}7V7ZrnxU)QL`TH!Npd2}zk<;w2NbdHC_k2_aF;)zb) z9A53-`jeb0A@N+NWk@{F=^GMHb0&nu)14(D@oeX{ka(7}FC?Dg{1g&Tc4Be{w`Ycv z6cRt?)DDR!IPF8?N1TBn@f>GbNc@DeA|#&bYzv7Wb)2E@%+=oP55?1*uq)NCb3I&z z6itc>tH`p@W5d&m%H zu>JMhA3VkxBuKygI>dsmQF70XtK)CWu3onid{SH;|In?&$3JBI4B8)>A#D6Z5?r_a zL4$m)``+e3i~ckI)SkikhirfS_NPDoAqmoNzm9+m$KRG+fBZwY4j=!J?K5b9Xoj%y z4@q#{_6H5}wej~h4_fq}@u&6-#y@2H>$gAs@efIme*3kHg1#L6pX0yj)e9^#I{t&U z4j+HZeRX?p;eRjxP51id|IWM`d{Txd{m-z5b}DSAhP3LsgA%mouI*HB^Poi;)txjs3{B7Cw$3JxI@bM4XK7;WO%@Ef9kObFlf6yRb8$WOJphf=~ zJ!%gb;taOGe*1&RID-V~x8L@0@FW5MJ%Td0A~)oDWpIY@y2G6Wm;N@Y=f9U@2kOz1^u|HiGT6pj61I)L7p}Jz zGoRPzljg6EGugc0ILj!19^a(=0P$&4ANKr3c@DifocTA$$z%SmYX(f^t!DnA>vhaa zdLP&P({VbR+WrAk^||#c-bUW1Wg*4(F-T^8_*+g!{Nr7>60z62hOW?M$0@`5jcvKg zYs*6VHg<6<*LJliuVm#uU;6nzB44EMYQFlmoyu+dLeaj^d@6VI`7_A(9r-ea*gm&6n?5KHJ{%xp{YZ$5EmDVfhM@Ps>B{DR%SeL;N_aSM3YQ_c{5B zgykznJ}nQ)r`XL`B7=ONk*`!(zFWzsFJnu3q`kbl6tIbM2=Y8URW@TNq>hsnwgYJ2v?R#0Q@>OSvr zLH(Xjx!Yg$+xivpX;{B&hV{EvSif((LBF*;q~FTt_FKCBR()+-SN2nTD>z>Zu{Skhln4- z#-U!=IMfdthXywo2Q3d72jz3eLAv9h`s!P|l=uI%{~Kkn|CQI>|H_+Wc{MJR&A@(d zqIxOcDXrh{n#aQW-88J6QE!}>rK6n2s@Bi2SZ;`?NS3U0j zS3S4TU;Dda$Co?K`lFO;aVwv`Iq8kVNb@}&N41{&cp=?(w)VN-ce3rb*>;L|vwjDQ zb-ea9+j{wI+?QLd^*7)f((+%oJ?+BUvnzx4+!NLw#cq4FetWA=?Q#1l-F~Va4_kRh zpLd?AeXr9l>raHXyKcMg4QrRa+*OP1L&m8~Si2Ov?b7-o<8{m%+Vf=w z?dciT9>s2ZwElI+DJ6q((sqI8Gd8Yv{@CMm#0TDSQb=D?tH8M2iFcd#``qt6*zxc@ z@g`~8)wfvt!(G3h&pYlEr?EWU`u0%YgBjE}Agn&cZhhL$ZIAN1$A{YE9^X1nhFUuY z@%K^7ms|Z>Ki&EdQU8z(>K_(Xzhbw3ZCBswQGU0-4~6wt%hRpz8|oX8L4Bjb>Qn62 zr|quW-_c?H)%r2k?~~rV6cK0ay9SD7Zp>%?<_Ufs$tDXwE>XdRlfyXuGkVQoCltY?vGK zV-YNcdaC7ar>82edP?A`KT)pwQ{<|La92Hay6PdyRSyxaIu%`YYPjkUb=9Hcs$J;% z2tJCB<2+o9&)_P25nsX0_!jQMJ-83QMEhQ;9Unj7&v*goRb50kMKw#P2m3;W?<9D(C- z3eLoNxCEcY)%Y^Lj&I?+_!0gOzrv$<0)N5Z@G?e5d*hTDvtwQ?j3u!m*1`sOC$__` z*arvV2%Lb^aV{>!mAD>X#~rvE_v6=i41dPo@Cy3%hs%zO1k8s;u`E`@+c6niV<+s1 z58yBygHv!8F2v=y24BUk_%80nFYpMS#Pew1leT_E>NSiRhk39c4#!FO1g^*3_yr!v zUs0DFxcTF;Jl4j0Fa?L;czhg};u_qH@8JRb4liToOkVwYu_RW*hS&zXV}E=U7vOXF z3huy9Fsq(u*?8u}d{`JuU|Fn;HSuLQEt@t*6fP3*X{0fiY5BL+F$3O5NjLhP-BNJxBJXjhlU^T3b^)VS+;@#K@ zyJ2s900-l69D@^a8qUJ`xCEcY_4uYa+vn^c{@B#qN&AVvHTC4`7_oitJYuHL`HeUt zPVr+t$8T!?^fpL2xxXLFp-IZu4W9P4u; zvr4ru!5rgrauXNBN_acoi5;;w4#9Ew7%sw9Xy1Rg`gY)6{L0kdfRn@*%~OtZ3ICxy zlfIvB z`I6-)@lR9z%$m)!20nlj@JW0hf5hAgY=`ymZXAuva24*wKQWVD5ZbuqHudI7apFp* z`dJN|U~|07)OMYTyI~6DgNTRWNXn<-B2)Ffh#%p1=*!_PFJ!8oGUgV?xsAAqsrEI; zyD0BW+znGGA4EJ1M^ZkScp5%#s-D%j4L`@rm^-J}t|F%1e5yoT*HpXeV-w2T65oTJ zO>H*{A2Zd@h2}=RuR{E)seG^F2lx^0Gqv4e;-mP3xl!j0=E&v66-}*Q$K0UzEr>gq zs;4t{r~E|5i}7hw^=!et_#p{!V#B9&h^?%wlT&{8-jh zeRp6tOvCy3imC11GGB0sr5fGpLU#Yh)_y#Z#+{ie3hNt}oUC@)Q14lA3g zrzQ5lQMeqpn9BQ}xzuqE5Fa&F?{Pdu`ESI3;uTZd71SHZW<^u^>X?gk{t|aEm9H~) zr~E2>{tSu;4qwvYfRPu znz=xq>k#iV)z1U?73Dt=pTb`#|BLtvMi%h$W;2y1C+4NRIB{t#Z>s)g*cC_P3VhpC zd-s}ib^a2cG*!>fc%Jfqh*3di<$ zwf9H-iSj>)|3>>@z_yPwwSEHTro0Go2`oc-4dU8ZkMb78t+74jJ&1c_Kgu5>9);s5 zpJl2)FX1P6OHr@9rm1!}GNlAcEpA2ij^!}uNLXNb?^@03Rr z_tuZWET-}%66ePx%F7W~!s_NEeV+$=<0M>*dram1+?=4lf5hiZwf7?aNqKY$uRIgR zo7(;s;zC%A@`}V&u@>cxiJM_7%I_t<4|`EQka#GLpnMYXqd1fDWv2SG4G&}Kl3sZe zQ|)eRj&+|CImGjEG3Bd>*WgQ(ze&6ucTxTs9>a?mRn}`~f~j`p!hELM zT@lz&A0DITEwDDiPTWvX9SFtNNB*TZJm6-VQ7BFa}1ug3M1zlD1!-;4h< z2RhELSg4{G*TVLu+S|i?P_ILYN1JNzc$`f69OC)7nDSM`Yw#t?-z46SyD0w*kKtLC zU%*SI+T*L_nF~u{C2WK(u|Lkl<@ma(e!gR-I?jILZ%p;`JN%LIUx|OmzbW@u_SVmW z38wNEAWp){SRHGdS}&RSPHati7vk>NoASZLX*i1VDa6xpmZ^R{huiQtoTWjK`d&)+KAq zLve(ub}Yng_yzuIsvTF%UV0z8niuCY)!u?wl=2G1Rj?-Ijfk6KOUgSDcg3ER48F!g#*9Z8qsdj&kCo#6VSDqh>V@<4&?Qt|N!I$t|Q{%JG?Cv;6h<`HG zjdlhmEkAsqNbncf$K9??*fUhf+R{cp^SZ`8?u< zxXe_)UcnFXSNt2Z)%4b@fbDT0PRAE<2Oh-pruy-Z*;TJ2Yk6^AQ{z|wi%?#kxH8tD zydiNiwxGNtaTn}C`CuGF`2?I|svWCv2mXZq+r0MWH1E~(3gQZ;+FJ!{Qr?KTDYm4% z6LDAUN%;WcAvm1!srV$WVEOa-qIs|0hrtik+RFp=_N#HFwt z<+X_GVgpnC>VSiAAuh*F_!<6*IqQ1cSHL#d8^_|4ruwnMY^U>y_$^cIe;ePY{C~t> z;33LS5dVbdD8EeX-0tOzHdSA4EJAq+EMux2cVcgxgX>If|AyH{kEg_+nQHHsc$o5& z#6RPC%Kstu-QjH)V=7-^tYxa6#%3$WX-C}MR6Qw}N_iUbNE}P~bmGTxF6B=XufP{f z)w2)JnyUYA^G0dS;tV9p`D{wWjKM z2{%%{gLoJ2ru+c$LHx#4zTYuheXpMUW@CMxLR`aCJ+-kOO?V|&Vb5ckG@ls`l~ z3dfnM=LLMiN~wIqz%e#aT_&lO6L=UX-{bmZiKVaUHBr zc}wCpc#o-i#^F<@>R)5(Z_gXV@0zNAH}0kUE8=hPd&++y{uTc)l`l^t&&sCix!u%r zm6pVvOx4pBds04tcnA)sd?N8we9Tn7mH3vadiI!l?t75o5OShMZp zO|72;6Dco7TnfvXs^=a|GqwE$Q?HR`6E8KD?-^W4`3B-mxP|ifi1*+prt+P^m?mC5 zIZVA~E<#-1R6Uik2IUQjld%Qm9f`YO4^#O@;apSwdD^_yan=)WF;&l7_zvZt5dROq zr2H813H+JzOT?Gam+aM34(~Eme`m9#UY`>`WUBsAIF9le#ItaoSyJzdZg9GL^3;wlTF{S2M|R9wZ)ND&J_FK>1AKIkJuHS_AvYZi2zQp8nF)n60qQr?WXCAKxS-C&$(sz0;LTO8*p z;x(r7t;bg>-%k7ven9zW#9!iJQ~7?w_~u?cx0s2Jb1QLm^OQcf$2%y$llU%dM|pSR z6ilT&jd&!EHC4}Q{LoZCKR0vfa{=PB<|)UyfR`wb)Zbt$_hX!??aJcqrt&p2vpY^l z;$Eh<>x&OkKAiYr98dWS;#oM)RK9iio~e5FnejTViBFrV=NG&{`4!@b7T$8dsqJ$R z=fV7xmn1HO6;0LC2_H7K{S-5cp0^V}W2*k=a5d!{i8tdmGmGOK!t-XV&byZ0_OX~9 zb7LVaie<4P*222j1e@dC*a5p^3iijr_=Kr;J!$@=eo_7cZop0W7QT%i;wShe9>U{z z63^prcm?e_rj2VB%!av4wW}a;5iElhuqM{Q#@Gy7nd;{NoQtoRXY_pt+>Y|jVAB$sYtcX>y4%Wk_*aF*ON9>L%_#h6#5jYwr;iEVk z=iyR(24BDzaU*WV9k>fW!cXx_JcP&a1fInU_&5HG{?^{OX2G18h=s8jmc@!#6YF3j zY>KV19d^O)ct1Xf!*B$S$4U4Y&c=nf6raNv@MYYHTX6?|fFI#!_$3~}WB3!E#XskK$uE4;SJy_#D27 zFXLw1io5Uw{1iXKLwE#F;7@n~|GZ1U2kT)|Y=P~tBkCc~ z{XTRY=0rV3aLWr}QM?t)V>8slw7b6E0&(q#-LMz-$H6!PN8=Qnjw|qaT#v8d8@LU3 z;Rm=MKgVD2SNs$I!6={C{#eY0Ik6xXL7UgczE7?xC|v7fW3>4@Y5-Rn%X-Jitnb*75l>r7>Aq?gyd&Qx(8;(}NN%VI@rjLon$w!_Y7zuRK% zeh5e51e}bI;cQ%tPvItf19#%P_z`}J?scWA_iN&d<`#Xw9skA1D6c#-y4RCxJ@_>qli<%H8Wn6?Z4@ix1!sdqeEwy>3*lqkJQ7 z#_jkH?!mqIB_6`>@kjgzeLB``oHAin%!TgtqgtLsTpVvRU)TFa*ch8(Yjm$8)p`Sn zhu}yYgOl)4oQ3Z7q}txSZgivLylLg~ZF~O2+6rRJ2=w4T8{!Ew^ z6EQzl!5ZjZU#jgJ5I4h?*bY15Kpct><2ZD$H&wpr#B*>yzGQCD`zN>s-$M7gQ!U?3 z{3(8h-{5z686Cfu*N<5+H|E16ERJQdBG$m#*b%#6FYJp0a0rgXG3Z|Bs{TAm>|XDx zcmc8f9*~X4a@>qtaTk7opWy%SYy1{3nEE6B2VOyY?PcYeFe{eAvRDOc;O*D|n_){F zY_8QjC^#D3>ups&m3Rg|feY{%d=A&*OZWzE!(I3R?#IvZH2#9W;h*Sa^4c4P`LQsT z#4=bJt7AQEgq^V)_QeNq2tI^kZ~`tdU(oxZxC+OaR=_fy?7FT#tZld`Z9a< zMPnQ$U?S$nqF55$>xk9fro?yQ-FPqFhrKZs2cdgCvGR;1egvoCOmwds)_N}xyVngX z-bnl=ZpZiWLv*hbUgz?RTYYy(iJV4p{L@;??*vZp63nZ9IsF(Y+p6c}@`jg1_RQ_z$|* z1#A7hdI4kYNy6gjULUOTio`XrHnumP*86(c9aHcDbgviIdJhqg!b$ijuE6JUJ-&kO z^}@=tgZO>?5clKfco>i3Kj_QqwL2E$FefHrAuNiwVtK5Ib+92O<9*l@`{4jg!;v@v zC*xvssop=wmAD#T#*Mfa_v1l4jK}Z<{(|k+~953NzjLPBlKNbsM5|+ktSRWgs z{ob36UmF}~&Q?Eh6plsrI(IF1uXC5PDW8Y-dvLb>)3^%P;6~hxpWy%SEBpqJ<4HV= z7cg^9ufBM6ucuf2`G}LSIF`kV*btMk6}s2iD^G9YR2+6KYB%Z^Im_?se+IVNfl2`_tnKSi$4Qz)Uu^aZnemDT#>-4q#NaFE0 z2_MHNa2;;I&A1ic!#%hU58xp@fIegQcuKkYh;U3(F2k=|`9{<8C7@fzb_%yzXuj6)n2fx6t@q7Fc|H3Qi&QGBFGwTg~ z8^_Y-R9#PlRk0@Cfeo=aw!-$<3AHO3S5KhaVNfuAE7%hg8K0z z@o7Adzu{$c@_PODV-|GhNl>1m#O{0viYpM`iFaWKbmvXbdOeBzV1FEp?z{{kg@r^`r^=?cR}UuybH1j3HtANIsl?2p561dhXrxEPT`fg6d1bt5xi(m;Xhn284-hu9X5Zd0I4?^~&ybt!r!8i?P;yhf4?tBo+vx4|d z+>YEp}g+A6f(Mi*S<`cgzkJ4T3(j8BG$m#*Z`Yg zCv@kl(Do_B_v6Dj4yWP_d>+^0tN1#;h3>o;%DcyJ0WvhweNa8ix_YqtTsrL*-8rKaDGJ z4X(%6a0~7;N9g?lJcLK^M?8%e@e(E!_O{Q3`LQsT#4^|rlhK{8L-n^M?u1=24M*a5 zoP;xQ7OuqAxB)leZu}Sz;6eNu&!IcdhuU|UI3bDtVgXFTYG#@~&&PV$2s>jp?1TMq zFs9*X9FI@p5_}d{;X2%an{g|CfnVcy_yhio=kPDQg3(31{$)aUUJ>;-7jY>pi&e2E zw!*e}FW!glJR-`MN<7sZqWQt_30#27a5=t!FXF5CI=+Q(<45=@p2lDBH~bTwqF#HV zFbihGJm}76qIMS{E`fEiJ~qV`=+1Yd?K%+OhdnV3N8)&#giqoUT!HRjj!Yg=7ac?{eVM#25mC>D-Mfqu@7(#_jkHevJF@OFV=> z;3+(Z7x4<(H5b;7d{_{RqdOmsmRBUMinZ|$ya(?^cfJ~J*PHl39E8L1VSEA?;4)l} zFQ7Yrjq<)q{5tN%{pikDqxHTaK8`2xEMCCur8Ewy`rZ!~z$7e%Ww8p@z}v9_Hp7)r7a{2zXW z-=I4`lGZ;-d=@X@Uw8#$%X|6buoRZXDp&(=#|GF8TVgxxh~2Okj>54x8K>cFoQF&B zX?z7=!)>?|Kf^Ea2p+>f@NbN);Pu~+HL(sh!lrl^-i_{jP#W+1hGO?#7SNowrKse@Xl; zevhZ{3|_=bn5&XkUtTPX#jp%k!0LD#*2l(pANIsl?2p561dhXrI2|9y75F@^$5-$T z+=d77FdoN~cn&Y3JCBye?_c7W%HDWn#&YJp`uqcHVjXOV?mSvruN84y?1Jt*T3X(h z_yKh1(Ng(H;_)~MAIB$fHLk;rxEZ(OJGck;qC5YV>N`n%7BApmcm<=Yc>T|W?mS)E zzBqANtcW$RHa5T}*cILRy_6@FxIYfV5jYMf;&QWtzGsLp;>-9tzKL(+d-yT#!!Pj= z{(z@2s;XCCEM`M@J~6f97UDu!0&m4i=*};u_3IGV!w%RPdtx8#kAu;jUrc#M6VJlA zxEP8!#ED7;B=gW^KmIYgU{nyd<9>_ZMYK;;SoH6KjE+VJ6=JXqr;BVOqdmOVP33; zwa}d>P1`jlZh@__BX+?QydMYRP@HYHbDVkT&bOxcY2sD51~=d)+=@H!ef$vjkzj183m^T#T>b z7JM7u!@am458`1wh9@wxruyGT*cf|YZ+s93;c$EyAHgX& z8|UFm_$qF}xA0xuji2IY_zixCC-G;@TubB8O7qWPZp?>CSRBh@MRez>)AqHA8( z4|`%N_Qzp30%zhJT!>3?1wN1NJa(#o7x9Pq34V@W;rI9>p272&NJmrh5?d2_u#jp%k!0LD#*2l(p7v7Bna0rgXF*pey#aTEPm*H}J0bj&DW@Eix z!2@^@kKi#pjlbY;=+4ilJWd@iUlbO=By{KF(|Tozt6&XmfvwSG(L#$3^%ouEKS=0Y5Yw=zGfeIevvl@i_j1zhYcnZ~FvH#QazkOJaGfjLoqXw#QD` z9aHcT^A64Hf-`XrF2Sd96|TXJxEZ(OJNPYrkEieqUc^iIFGk+(wJR%T$8uN+YhoR2 zh{@Or+hP~&j(za~oMviY%*1)P5TC{sxCYnbCUoaLRGuBgyYLVm!5{H7y7L}tyWfa2 zYu{LV;xRYo!z3(@w_^irhAq*ZA5r-_68FH~_#h5KcV0w2R=e{e%K26<7vVGb9InS# z@FV;bzre5YJNyBE#&Z~3&#NyEb7CSE!lLNTqp0U#?mUXJg_XgPf3@@Xj$5iWwAKiH# z73Uz%gN3memca_x%+z~9EwLST#BSIN`{Q7ofwOP{F2?1!65aVBRi8UQq})TfJ3pl2 z1H=dM2p+@J_zT80RQvT_Z~`V`ek_5vVkNAGcVI(oj;*jC4!|@ViQ{n+&cIo?2$$hz z+=}nu`?weP<3T)(KjLXTkH2B=Mj8)&rj!qpusBx0DtH^-j!m%z-h=mI5A2N-a5B2{ zQ>y;i#82W9d=^*X%eWCg#(nrD9>VYOM?8b)@o)SW^Xj>djYk1==d)Do&SxnrP+kS= zVts6iEilE@XWjSXKpcvra4arFcRoyQw}SY2T#v8d8@LU>HjC+ZQSb*mg%|J-yn+!; zyzSyJ0TVGl*2Fs45Rp@5A1hii2<%j>SiC2|kUha1Cz2O}G_z z;2zwIKjLXTkH6t%bm#TdxMbFAD;vLf%#Hc5vRTk^s$*TOk4>=!_Q8HQ7}L<5_fz@C z6Hmn%xZ1o$^ReJY+>CGId-yT#!>{pM`~gp4bTco1CQQIwm>&ycNi2iauokw%j@S)* zVLu#zX*d!m;#7PbpTJklM178q+i)j-h@ar+_!S<*6L=nf!^`M2_v$HtNmvTYVil}` zw_^irfvwS z#GCOm{1U&#@9`9#!Haka-T6?}o|qP1yNX~5EQgh_Cf31*n2c?(J$AwFINprc^#C{n zXW;@|jLUH)zKAd57JLie#oc%uPvTj;fPdi?jBe?*FB9g(M686>unyM4WV{pG;yvij zx2pcT^R3EpluyLz_&CnTMd;4Is_oqQSLG{|zlPgzCmuAj==-jC3{T)M_$$Wgy-Zs_ z0TVGl7R8cS9xG#OGgiMlfSs`$_Q8HQ7}IbZPQ>Z>IIhK)(4Ci6^=%>EiSOb^_$hvY zU*mB+iD&Tw#@*%hCjk>NKNiK3SP83P9ju3UV+Xtsd*Ub@i&JnqK7kAHMSK}I<5t{- zAK*9m9iGB7_#6I-*;;%3&x!f5FqXoy*Z`YgD{PDR;(a&_N8mV|h%;~&y7QlEf4lRa z%9kjA72m||_!+wMoofAWiND9w_zOnsvl%;nGhqVe!UC9trLi0~#AIxRZSh{b4~OD# z9E*?OG@OYm@OfO1ui#ePfnVdd_yeB8b9fQ|#(y!Utv4Q-F&E~=%2*xiVtsVyAJure z^N-5ADer(ius1%6kKtT=5?A7C+=6f6mv{){?&kc(M9hyZu?;?gQ}A_s6aPVpCklm*dno^*pYbsn-KK{M^?e zoy;W1>0uVr_eIQ-ny25qRo|O2%Q?;jv!bpuHLEzz98>QbE;3cga#Qc~t~T{v>IPHq zA-!ShHSz^I`Sh9IJV$%n9nhIZ6FDr>g(vboJkyss5X@ z)qiuY`fn~!|IJ0}zqwTXH=kDj&1cnrbEW!kzM%e_Yt?^qz4~uzu#TD=)qnGK_21m0 z{+rv>f8A_9bghKduol+EX4n$jV0-L@wrebJ5A2PD zP1UcVcO6Oj7@T10dC+8>X6m@rP`l1Cb^Ojp4Y7M1FT>@gj%N+6>uS?p=i&xauZuU~ z8)lMz#~62-I^N&K-KLKFk8z)=@tmpi<04)%Yw0>k zbZo!sd~xSPma!J=yotjEvw^M~#Jpx>?N3ZHbv_lx(x%RTnQipDu2|pH z`PLYlnL6)UVjENEUwiCicGc(H*u&KM*c($#otOP_u&MJi4M&=(`o1?#Fm=98#%ZR` z+nG4W)cHFf7nx~}vkaG;I-ghKYE$R+I^1CD{N99bm=m=Bai^*C{axH`>b(CL_nA8X z58y#_ruIJ`HT8IK98a2hT=*H!nRv6-KCt4<0`Lo*p z=*}0dgS~*oGRf5ANpUP~>T#tURxXPmZByq_#jH~2(JZrp zey7CLdDB&Gvh!uDd8gy#&n8=Go?27q#Yt1=!$%2H=fO)kq>lexIi-&KHR^*M?=$nr zUV6M%U+nl^kyobb{RZ{Pj%Rni1s%ur3n$s{{TIzUu-qi8) zsK(BYpWm1{N5<>Y#Oj$rDz7+hZJc*t5oYX7I1+VA&Nl-lp=z7z2a z&o{KsHDqqw-qb#wPpqc6$H5!K+SENBjuW3W?YQtsr1Mjm-vn+$2slb$m`Ho@VMeT}QmZ z)bYBH_<*V7_8hT0U$}Ng-YAt@eWs4%mc(sL9nXV_(@Y)L?mXREf1SlTz7MnfsHx-J zvGZEXqs(4<+#s%R_EA3KG&5EEpLmg}^T3_gTHCwxS`Spd7?oQ-Q|Co-;?icCo<9)x zHg%p%Bc5sMd|5}l!PI$kocN?ULC2F{Du04GNyig$HFK)=FL8fU=hYnI`KHdVO~h}Q zI?sM4K4m-qj+mYwDnP=RwwTcOGP&hx1v!$kh4h&SR|Q+bn)o#}CU7 znk#ku5MMT5(0T(t7riX+u3z1NYMUj7)PX^zNC~)2YyF*f6KU&_4YuSYd_1L;DQwIkZpr z`%?yV?>9VXLC-$Jx~HhHSND`b4-HJ~Gqii(K|=@hOw+vzDT4+MOB+0N&|qEja4pr{ z-P<*4(!D{Gc9pBtYSO4-_a*~VhK?GX)_h<;)qSsRksd4;dZ3p=)K_)6n&9ROts8TT|a+l?x{K~G6`!=8q&mtmzEkf1(XXP*YGm2po)v)!oD8}yW9H|%NXdKp%# z0cmto`!r~+jC&fI?M9W}pr<6eVNXNX%dk=nNKhZHvrmK8%DAVY*=|(n4SGtl8}>AG zy$mb00cq8sQTL{O2KE`MzmggCHGI8{dmFyy4Xf_ZXK25^qi$5Ox7LlT_14R2LUY8CM*><_)X9et!e$Zq(n<^{7gSxLbZnpXL#!btwH*VhI>$UxQ_8-Mde(hwks* zZ(!d+dKKW_@7b%@&^|oh_e%N?O7Wgov%=7x1Mly{O9ij!za{e5uIC^C; zKs%1-`(An9p*;s^r3QDms-Ra7L;Ll5C{1Z^{+3^>>a7EN`RU%OVF0~ccW*`Xzpba2 z)$T2PJzHkCQu?QtXg6H1lGX{YcVr-mmg!}-d(&GFj$Vp6_1#FX4!^lH96x*wb`N;{@;AQ|gf_@4d+ z=bImtFOK!Bo#*r~IG_CyLW)(*>eJSd;uvb>tFPguS=Lfg1e^C1h1m&~$=Y#XLQNG4n9=KUQ z>}K!h2j`m{luvIZUu|FOuzdFZTYEQy_g^4ii?Dplg8G{jl<%Rid?%GJHJyC+yOF`| z+ZNQmqCxqd3d`3<4?gMjcX3$013~$U2jzP=ET8?JTzZc$JHzt*9Ms>ELHSOH<+Jw_ z)9de#Vfo_pAa2LqO8qMxl+S*bGI;;C)cc0%^*3JY1&?3xpnPS5^4%7e&)%<0ufNs9 z^3_$oB;~R8l?%$(JuKf*UBdEp4QgM7pnQ*pA0iHvQG}!`>$k-XDjRFTMWS`|82_V_i`D?C~Q?|Fo%dIV@jeZIs^r zwcqUw&i8Imz8XRK>~}hY+c!-cZP4<-&FZyVVciMNcUbvs+*azJK6bd;zUE>1YUz*Z z8&(0gK)xnn`Qk?T-0yl=zS{a{>sf#8cRz#McTS(XT~vACX6xB)fbImhZ;bMFQu#{# ztE+#up5nb_~lm zM)?B!w^>lWiDCJ6=G13EZcn}c0{tBqmhXV_1^RnuP`=e+`DW%yzrQQP@hDi*`+iowgO-3>pndtYUU2*3#$L;Jx7H1`uSrvtGc4a><=Y+T zEbCeLdRV@Xm9Lh{SL$D9{R`y#E-c?ly^u_A|Jv`-2Jerkao6@o*PwiU{k;v|zexqs z?{B2m3(i+9C||dreD-^_!TByJ-@95KxLH5!X1{M6oUeCKz8+d0=x>LxeB1OHdwTu7 zJ1pP)pnSc8@{I}0XY=}}w}0*Ta)aCVZcx77LHSmO<+FM9)7!tx!}48JzQF$N8eufJ9fv@ba<-%RC8ufGk$@+}L>H!vt)|FC?QmG9j^ z<5SKmy%#cp!FMmM=$%1y2}@g~=M z_9oZcd6Vne?=0WUxLmo(^$P0s#?9obdz0&RxykiL-{g8rZ*sjiZ*sk_ZgRa#H@RN^ zIPdW#a6Z`i(Y@`}$g#&ByCrHp9r{jv3v`Qn#OJK8?L8lwuQ+i2mI}+)T@OBgMYx-| z{{`~h7Pj8KdZW3XJ(1)VSg(3my_>fBoHlxbxKisa)W1Nz&BF36`c%h7I`uXV%NLa+ z!u{@_?-yjfMopv*WhSfQ) z^&GusSf%pw`e*qP^v{kx<-2-2-qYuNq1TRqTOgla?uM+_wNQlflG+lu1=btdeOOAL z?tM~HDh#Taq+8{hm1@+gRHasx%DP{vQt9Qjg5zo3u>!`2v}& z52f9H1nMa8wtFwSnoDV?rY2oH_nK2YI{D=d*^=`l7fIewG-CC?e_Z+Z#Z=$?lr2>X z7TD*-pPzDac=u{;thnLaTfVXp`|>oidsPc&-S__a*oa$G=Q{qMraHEDQnD?{<}NRv zS~ofRd?kO$|vQ~oNc^q zT;klZc8bJkwEsKSb8c#^qqHXi<81kg7qxuRSMyyP=Q&$$W}L6(dwoM(a*ReJcXGt) zq@vcR4a%L_Jzkw+zIo53w%g)G2XwT0_l~|&L!)U&YeF--=Z;ofV4Q4>lKS=Rx1!&% zes;e~YQ&n-1ue6!n_0(YgnLXlrO)sC`h<5}o^!`(_J)|`N~%4AeueIt?El9-Q&oHB z)~kEQ_KLG3uwNo>^&Rw;@qHE7Y;eRbb-L{zdfX4;0mr=suiFK|lN+*c?$ zWsI+E)qN#eBqrxiEtA>J;=nX`@!Z=&{uJ#lEt4_VDjZ-BO@fwk0`x#BO-&YX!l(6&-v(tmBh^1dBWOm$7XK*v-bOwS8j+;)(kC0CKrudy~uqu zs5{0f*I?gP_2Q0wap&v%pHDt~N#7U0 z6qRuJQf$)UOL3Lr&L_leYx0tg0DDyWW&ea?5k()r)TYwO( z6P4YgBXvvOVrA5~;%?uvH}gzDCuo`1w_87UbX*1Z z^W1AO$7bkM62toU*s=+o(R)*jK7W6}OKS)W^Z88`a0E^fBV4mC4nTeK*_3 zq7lU&ztk*g{iUguDku9^mvMX6Og$^xqnM7s_-5DscPR6E6Y)}mqD7J`CHvg{HKC|_ z6Z!b1=5D61{AY3|;vUC=j2N0hIu z&IYTk$ChKMk!9m{lr2_VZSdBQVY>>%q2p)ANmTMn`g>+0xVmW6>OyYj@5eZ0I_-0c zHM+A%YL3)mJ)daUYJX(;cKagAH$UjB(DY#SrSr-*J{Wnvcx>y_yJO>DiT%wP`OT?n zIs9%rCKRo{bkSdnF1=Cp!N!r7mX)i%v|ZVH2c2T;FQrxLs{e;ih?!T~ttV0=6XlLf zL~``pm?i!f=f*m7YcA2>jVcjyYb?2~U{n>~+~~E|yQ5o*wCH@FQ>^CV%sqQ|`=RW~+#N6|e!=JeR#BjS8Q#JT-ti`87>B<1X3k7P6A=~NPv3TljPl>Fr%I8&n6rA*Evl#9 zDT^qZH(6^%`eG*(6A{sC_4Z?AgukMm#YaX(7tx!2QSKE&t@GKNGRiQdh=`58)1IEi z`d`sYC*`Z74>6*q=&4g=-kkOvGU^q*TNzm?S1;X7reboI-Q3Wyf z&aN+Jf}SHr#MIOOkuk+pc~ne^;@T)?n*NW8d0Fl7$5d73*q9lrBvZ`S`ag5bOL}#Z zCFa#!>TpbHeIk=J<_+~ZJ|??9UC0*GO_e0XWY6O`*<)&3yj#+Om?* ze?~(;$LIh4Rz2JH`R&5Fc|QLYG2iF6pVeL9^H)(jp7i;D(Qq#G`Il&X7Ww?!lykAq zZ@);l#OGhE&6oQ8g|+5It)k6;^Z7ql;qN~G^Q!g_pZ|Alcgg4Pr>DoABK&7mxGlmz zB)2YJi}ZI=e@{jFvzKz5(~u3UnybDF5rKwr!Mur)s!6%3nom zwu|z2(Qvkp^53g{bWfCjiFQv1ZJ@)rqp)^H`HN`td!zj4G-jQn{NHMyc8T&=*9Kjq z{AYE%Y>4vrQIm2-`-`c8xugB|QSiuUe?9efRJ8xQOq$#$+W(QZI~?slull};_K($` z`!?GDmv+vPXpMv89F6v$(&6}Bw112EKH6^|2<-Fw^Ots<{eJ&#s_1`y|8ni$&;0%p zI@AvM{h2iKpZood%joCE{Qi5@>M#BN85*;Let&}M`^xX%uPkq5@i$bpTeA3vsG>Ks z`0e${)-3*C)rjTU{43PJXS4b3!od~U{Ht{=KbOs)L%m&@&0kL)Tb0fKwtD+~Hh%#% zVp>jr5slLHoPPTy--J^Bp4#ErOZop+rw1qcKUL$0B>MNO5knLGo7KNziT-aj_5qW^KNGCa|LM8h*8(VtC>O!V93Poon3JJq9y6a5XGk5uD( zpY}goLg(FS{|`EB`kwah)&X|^=~(;mv%%SYPV5oYKg90XC8a~{&N3aB!|cvz4NRKd znXg0-*`2jX8UVX;5@t2SVJ-2?kv>i3+&D@Z9XbRcS>mFAGSN&bR5`= z#n|Io$7gr;=n=vG5X4T>V@Rak*`SgryVF}G(RL@h4yhQsvr}i8-|jTm5fp28?7hQG zc4wW2KC|6d)8-$z=usI^KHeKOzUx*zwW&acMNKPBw7l$$gF(P!cm2G1`_}V!7VuDYVdfWUSyv?71Z5rxfA^NY#ue42OYlMBE<921dlPxW} zn=iVt3KH(n5f|OVm%|3aNf>0?^z`MhMN!^n?E{+)ag!yNe!v%LU&qP5U&B=^I?b10r$cu1ZRzIa6G3AXb`vB8t_| z?uOE)+f^9S`r8{(y8-rj$T!2rScUc4w`hn=oA2cgvUfn9N7>Ubx@Xy;v3$xQ!_QUQ zNaQutegx@<>@GBMwtWo-tsMIuxDT^uU|=3@UxX@-u$z(cNc&xk$D{1uA?|4VY~(w} zZiFg~wco_ZG|mXz0YTX9{&~nhoszM>M7=~-oyol*4*M$PZrK;2>4WwY7={w$xf--C0 z%mrv)b7vrp7Y=3-rl&#oLaK0?S&CK|Gz~81J%O1cX~~DanD+)|GO43}$w~6Qz#v9E z>NPZ+xhpV;9sj6zvtfBCplg~{1VNjl0!a+Vqm=dQejoK1{G(CIt8z9HN2cl+{3VMx zI#5{)N7TiD2#vw&sg*H-O6FXLvy_gY=A>G9VfD$xq-?8WOObZw$SlpbRjb@P|2@&^-8e z!v8GC{{{N{w;47<__qaYBeVrUHX+EBI*4yIlD$ye?i9B*sO;Tvy9nW;+4xQms8pUt zn)Uu|NZNNsz}l8z4-3GQU~R)B2q9#pVsbEF@w-jbg_O+hTj8pk=oSBbHW42!UWIe; z2h_1w{qy;3;$3jKiH;E}@oWD1$HVbUIDAG&)tImQ=d&?Opoe@KcIav-iTS2qP3^vI z&04&B{Ytz)Mu2m04l9rv<`lzlwXPNdLpZ**td*);y>B(ke>$XWZjP4!1y%kVuw2pQ z-|Rn`<==yJpTar#GDywb;y;->G7||*z^PmQO#jKMQgFB(r*7o4{e#%){oCH(q|17q zF6*lZ@f(~W48f|AOOd0J{`;Or-fD!VNnPe^e>2|*ZGzKnsMXq-D84m_U&l%fyHVog z?1X_Df`pa#Twj+8lu(44TU6Ka(VBmVz-IT07-@9P$NOtp^K49H{c-A+%k|f?lAPU6 zqoWc>p1+pjxE&6c({T|BW=`bYi zj?jv-^(3R?rM?@qKV@_=obEx*e-;zPw?;MpYHT{6VOZ!WP~l+@OYEHA!r({?LC}@{ zVb)QmN?fNRHS-mptLVEC+U(AR5Jk~_H5AtiDDZPQMbUjV6xYAu@G%{=qWfy7=q(W0 z$v6k6VnQ`v_tj8_H{s-ruVwg#uZA*w8xDKvs79DKb#z=N7+=G2=xI5K{(GNviIa2} z`GaF$G?XhC^DW0NUFL0{>N4YzNQftU3I~eEG2&8NI8Zdh?J>B0BW~MHVh`H3h$3M> zs%JlfAlbDrI8eiUXY{r(@KCHbNQ%RDI0kAX^Dwe9(JJN@QCXJ5(d@p!mE{$_X_Vzz zDA{_PdI-P5H-|&`V{mwgjz5R0A(2z)xDO6|x?A_LD|O{8j1^pp8d>Qh5VR?pU%Sfh zCGxm>I>n_f=IZ>&e4}Y_J2{P7F z&Cvq94CT2Pr2o`O>gag;BGt1SPv8#gH- zqBsVMjz8mlY2%Q!65`nizX7Kb;)^gmLJNi12qDeEIg)Xd5O0I+Dx6~|M9#5eC`kXd z?oA=;Dn+;t6;(3vPQW{j(0KU20sn(he9N&XuA_^msjGT>d+z-cSDy)GLZTBYl zxzoTLCl-C3)(ROpD-q}$oq%c+O!GG)V%B+FKfYtSqf#xxncZCC>Na@CRGMvL*5Vhr zbQ|o`j$`34oQ_Jf-!+wH^BY<7aOz>@JyV92QmyIlJN9zjMjx1J7`YS?&S4~_=zlR& zSODL)N>>T9VMpEJ6s^^8BNReu*%b=Ko3j%}7zC;_CmOt1P%2ulz3DVroR+yUjGS_~ zB|;7=gL0KZDaR=4Zaq>H)x8!`liQE zy0wz7J31;hu3hLYVnfyI%z~)cF4W$1a>RCn8zW9^5Euks=n)&Fs(Sn$L{VbvWn}#k zi&t}DRBU=2&A`%LOK73lz;X0u)TtY%mgNcB@ijR7j*d!fCz=hM1J$-rDkPxB(UY~9 zqT}c(T299!L;*u7IYrFaaa0WfPyxeiHq)NLWuqDbu0!~r;#5PxYcTwl77hWUF!>C{ zIg)YI5WscCDLA9!=)=Pxs&8AZt9-AcS(WnDM(Z1jD&H64Ey{;LbzFFj z7I7q?I$Af4P=UB*Mcs13a2xJ)T8;|Pdyn=(s$-wQKySX}4s8vHVRoN_tHp73G`^&C z?IBd*mpI2QLi?I8E4Pne|A1~v)%GY&>x0Eb5a$53Tzb_R)&?lWdrhq6uOLd zMChX#LkZ}O!^X6OQkx@;Y3V4ar*p=SX`{5acT79ZjiEcIE1n+5w6OhE(~HCUU8Ia$KV>HVEE}q4*G#Tb&Zi#Fx<$w1VP-DgUZPh3Zu&= z+>G3hg8mVsY0$_!4P(nyxULKu6ZrNI&x8^F#0kkLEYE}_GigHo7~HqRnGiIS^5YjxYCz2A%fg^+AkofvCtWw_KUF0!QzFd z{X1B4ksHs1ZHRL_bd_hqg|K{sj>9uyD=af{^};jZ4177%>}!rl?w90GJ}S8}qpz8Y z8QVA9NJ=_B$)5mi6C>u{zyQOaJT2+Cq+^pRkh>Ky{mI8CCBdQ{O%`c1!ti!mP#G-b zp$rg7FNtpH=!vFT(T`D*vW<#<6A-0$KO~rx6iuv8A5Vr;5h6JSZdD*h)<32yj;P2TiTgo)|Lcu(UW_iQNs0&&c0SGA3F*nn3<`7WPx^Ot1wQ z8b)GLr>MHS5vD*IM3PD+o|N%1WNRYf{8EeZ*u!`~wuy8G1<({Y-{JmP$uTDCM@p*;w$ zO0)+}w`vdK1=jcE8|H7%j-8zFWgRpQ;NCUqoru@mSXO9mV#NE zM;e6cC@3AG5hiswGQ{05*f-&%xJc#$aXH!1*~t&iPG)pQz#b3J;5ZurOk+NAElw>q zn(ovd#Qm-ZO&@9x{Eaz0!>JCzR{q{Yx2hUcsT>$030bA3VyKy2V;y21TmtculwZqljGurB6FF??^gJt2U=wwW@BMI+l8EvwGh;gxsmA{>2 zOteijf&A@G(cv6T>+mK^)G>+O%GiLvM?8*(4^)?+reFXgwkYFV;#`~*#N6#PU4j$A ziMy3?0r3m%O6*p~9z>$A@G;tqLZZG>CSaBRiNu0k?AnuFMalg>`LXlAKA4Y^x_ z0EZo(R_hH<-K%KI!ig-1a%HT?-m*pJkoZWb*#gc4J&N;qI|?sWt>N}j~6w_rqKpj?$c<2*?yCZ8y zINlgK9xmr#fSif*mGQ7%&5()8Yc4_kL`8`XoO-~bNk?yhDdtFp4f;gr5RHyE`U91Q zj|h@Drs8BFr-OxJCc`+L>eJkeli^l^JW&CbV52ybIW^Q3Ns02}mvu908Re|Ob4AkSOkf=Q3`?wDN1Nu02iP`wXWMx!+ zyjr^wI;94f;*Mn45tHy#h5`R$Wfd z0WCxnC}ShRp7ytB#BDS7#TUfEk2`qo5A!w6hwiX><~Ccz&FJ zx!89LKNP+o>=JT=&^gj!;JC<>D{p61%Yk_~&e1qI#ySVXPsQm-pb+L_oLp!% z5vOwufPv}q%)%MM$#i+L-*PBtZ}lGklk#{P8tqpf-1M1WCFA8994H%3GcRvKN7IC* zo$V7kJC;n)-1t`7pnfxG6+U&pYDr7;>JI$$QPhv&@kNSbC$z6#yu59R zF`;$Uik1mY%Ujk?$ip|&o0d=LY{f4qP3XX{Gjuj}PG~8Jbat(7Zd)~>Yt^ddOIn-S zR(4KUwq!}9sbj^2iTRO9k%Ih!iIIu zTe)QU>gJXS__};6zqdr`A(a}{?oHjyb{|~1A-_`&WYeG|d+y7gO21V;? zTDb&Y*Y_yL|K^tYZ_7@8MuK{bfyVvD%M$j^NOQ~5rq#>4B3B?%uJ!`tH3ZOglI+g2XWfywFX>L)f30MDgx zLC6Bd6dO!-9gVq9w{Vz~H1Nsd}SCUGg(EQ^=wrTsnU2DS4 z|0x2P{#zhU=)}9WRtf}4%X0#y+y3uVpvw>l8uA_k4YEUd)SD+IR0dmVj+I&gH`QWR z)?^r=Gtmah^Wm*jk6v8wkCm095&vDiuC}pz4DB(GybgEpv#KlB0Si zTVboET0!+g%Rb3URzk^l+Jt?zPkKx@WluV^-ejY6TXBu@EZos34C^s-r zIvQmuTR3?sn+4%iv%uvP3WojkB7|c{W!w3OsWxVE=y*Q7Ana+J_jH9g+@#F5Qih=} z=3o%JNdqDlibL@TCfL6#_x8-e#Z}y+WwN^~$oR zurl$3%oP+dh8T{0nT9W5=3!{-?GA1JmCU2S%CY%6<`H8{)aHN+a6V`XPs zgNMRwXWM=0*UO%Oqy}T4g-;3wT2!TP$jbJw$%9`ug)+#8*QY)5dQ;^OkG@vQ1j`(1 zCFmg z0bu%cgc@eewEdVA()_1~teO5^A#KX?Cq8E-WFx>(tzg+!mL5oT3eLQcV+}=0roY#8 zE7jjH9j5Uim}+R6$RYk19iRxg`WH=SzB8u40oAQq~?D+1Vypa@Vvj!ZSyFdB2bHAfbSc`CnNGti_edpplg=x0r{&1_mH z(AbwLTLtz&$N&S&AAiWDPM1Mr+;6o~peIqjj}Zez~mf1nYR@ zMI-V$-tOzed-9&9KQri574spg%BsZIvhau35-Oo`Jz_2OYVZ z303T6kJA;K$ci;Pf&@9#Ccd_ZDA0t=k_Vh)pxc%G8~c>Y2%IouigRt(8{V5UUlIAy$LuuVq)c znNvd66npv!sCGYy>F&*x(`yDb;8taR8)h{8J+Nr;mZ&~GFxwhB6hg*GmySaCXR5Be zEU)LXVzF1AXD_fnP;pcI%kr$D{>+e%SFPdt+DKVlU8J$TI8t5H5UHsxt2Rz;S;rrU zlaC`t^wntO^p2+X_Lk-deY*@NVoBY?+J>4)c~K?Psi`wov~+ehEo+IiHg&d263wl! zt!!T2;)z#UP^u$D>dLB1%jznsXT_&k)Ywp7R^3ohQq)jUQymExRaBOh8Z8kn(OWt? z+~9Q!iW|d`nt5e);mVr%u5*1^b$v};q@sFWQDsGGq_n7^C|aH)RHmp}g^M&+7tKR< zMa7k6Mtf6pb4&Az&SeIFbhxIhDpFEa8mX%^(UID^ig`s1Wp1vsYs+S_Vn%0I zq@$&&*^wTkrsB^jTZkf+mMw@hEUYbKG6ngQr$%ZUiz_Qi+*F)GmlRc2#$;PoQWB}1 zGx&|tElb)FuVZ4QzHQmcrY>wfI6v~}=BmnGUsItp zp|q@_tfT<~cUro(sIH=6p=(uvOKPfWYpT&mx-AP_U+PkQLs4->WyJ|dWA(~TpYWH`Yh>Sv5mLT~T#? z6@trPQNSAspA(lgg@V8fTRot2!0DOgO~{2$nhDdkT%y1A(iR09>RpI^~X zQtn6zJCFDQ$4JY{=C-Dlk>#saE;Bk?y6|D$=FTQH4@A`O!K;aby6qHRXXOPiky%9*)vmXr5n*L)h-x+WEPCX(u!NL3B`ftI=(IjW9I8ILsPsL?XM z&$2_PV%0P@)HXIm=G9a-V9e-YNJlxm3g`@D@fuiCSyWZ)8Nk?|q7zmRWy5gNlO{V7 zsjR5Rco-=vEk(z#H{!?nf`acK=bdB_xv{drVBVk##;1lJ^05=_)ZpK48JvX3nSsmqWW?*S#uO$(L5!( zexP=R)Ss9+#VIT`G}?(P!Znd_Bc@Qt+sVk0oa62e)6uwkwb4T*Frspv;b_`WS+7dj zimmbpi|QE|V^kCaN=;*Rsajc`W}suV>SYvrgR~yp>abp@Ra^gaTGrL-U+Q&>UWUaG z1{JQcB5ePj279G{GDpQJHKvS`a*Xk1mH%nRa1uF8iSKqCl-0R~bLCn$ ztFekR(VC{^t6O?1qRdB*^qdB85^xgkLGEs!kec-ngo$JM<0Kw4i(o`@i|dZvC0toV zJd?h&ysK`EPLNviwdD)F(vL6r{F=HsGVs@9$zw#v_!Uj3w#X__)}PVeS@!75e-IW{ zapi9LE9&M(im`Gpt*GY`HM&NVHE&f}Q9b4=wuEZ!Fvh_8a!)v{D=UiY*cam_I;H=d zy`1^dnQRxgbva{1eAThe!vZ+kF^{muE9Vbw*OwPfbgL1rE2`p{&X#lp?}UODA6X)9 z3eg#a)8xXkh8|b=$`L<Jj#%VmZdHMziau7D~k z>cT}4jxQ67u|UKX5|;$c_`!GlCV3m~xL|dshCl6&X(<|2uHs56F&`I|lyKT}ipLhL zswr)(#QLgQ_lF~l4FyxxLKuse@<_!zHvvRuN8nuOPNn7QiV0fCD<gD(ebpxxOj_>Qxo(X`n5|<(I?V{TuwhLp;5vd8|It8nm=<3u_pQ`#IfIp5sZ<= z&XnX9MD(b!dQNrC{Az=jed=N}K7dmpJ$S_Af@K7oxUsINM21|aS-7BdFJI?DZw&Vxd@k!C^(wgNy)t?#(dG^HF1xMP_eQtI*C+NW7j0w1*GEC zyx5Hkw_p;2LdJFm+ny3e&*hqSs#jgy{#H^_gVvkRbwk_A=9abU(op?zBu3>|!vikY zqw}#E7n#E>)LUIqdBfAAzOf#em+E<{rwfZ(jA08Zu-3!gi(7??>UvzM+( zC?_mmO5I-VM)pVu7w{Eftn;wQ>dCvjZjL+lsm+p}rUJcA;pLuZLEuayQP0?GK~EW? zQtPn}?m|rI**Z}i%wJsmHMV2;_gu(0SNSD1)!~X+P8amf?vDH&y)VIJSXUN~s1=AS z1J%nQbZk(lfm&~=IdL)YVzD^fp$Um|P7kEsE|+ zVX1+2fgT+6de+GZt4j>`da?06n-T6VNo;O##$|(Q8gBH(RvMRu91_bGl$4c~dZxL< z_WPu1W3Gsu@+AYSQNODX9sOMQo-xXN@~%>b9&fqbb7Md zuWP8`^{U&(4K>(nD5_TbGFT(m$Jfu>lhpDsW~6raquq^B-S8OLouWFUm%hX_R&}+u zbVS-#E?sq`rFSu}U-UJox~SCK>~4YG%i5k6AJSjA&J1HZclPfc*+uI@i11G-uQPsofc}S;7Z?Zo$nuUc^y2zt*dp_>MnP-cNX^8 zQF4pmoigR(R3=qd0&0Y8#H>|YtM>mQwG|6+2`sx9Jt(1?IMfDv>=+fj2;}UkHbi^Y zuF`T|Q&WrSsj>Oitj!CMM$<{q&$*5L*d z);l$gb)E|rB~{gXdRWUwuie{X7kv6olI)`xr#3H*>ENt!Z5`IGvS0rF7bBcvxKW`l z?2n{~*vWIYVLDq^b#$rwCyuVTyBOGk{=O@phSIX=#Zqb6yb3H))z-K4LawTLPs#0T z&W$0is?}vZujrjzJu4_~QDa|LX^!j9_G7zOV2gpbetM{y3<_=(_Y%Cm9G%p4E=Dh# zBm0RxB;$sY5<$JOL)=(qw5(NoaWWRh3|gKM!>ivI>%5CuEC6Cwu+CPTM_$!!on4$l zT$vr|YQ(wUq%XQ+HY0m*Qfi51UPDnGrHD=kmFq!6DO6{&h%R;G=1os02$$%s^-g^k zPF=e8&@kT37q_ylRoK9CSHq4hp#16?%4jRNOGXYr5nR5p-x-mJb9M9mV?G7xrp2BV zyOegc&)aJ5Uaf4_#0VD?P8rsXJ?KruQ_E-%$?a^bb+fO4@UB|G89=5Xz< zZm88DBuIHfN2>KrYWDKjdj+Z$oIZlZr@o&eUF3h;Gy3v;KYv4VNl)$035(-|+V$cL zb@;7|p0$N>zVD{3Uhgn2))=1o-ZMO_t7|o3i$XZstCtGy&2HD(?ZNephuw_BVg|Qn zkeS*Lb(G&7Bs}{v-r3`@Ej~l9b|d__eGe5^W0~g(1{Mv4QQLjdSvltF#Z?S<>srli zOx)A@`XLKxef?MfUI%b`3bm)FdpJF99DAk^k+rkNRoB?AL}Kse#4l%^Vbr~e^#g`v zHE8gbQ~YQVw}&O8g&uj;z0w{ejUEvr6GsU!6?(2bC^EQ<$^qKhuiq5*r4<+!dkI`u;b+<%On@(;VXitb#w zHBe#dYxJhkVUJ3wgd%8ZuDOalE!*;O=olS(c;nJd2YJTi+>keB&#n<%2nBCB2K| zN|pL>`1U-5d7j3K-e`+9YGrASy1(N-)6j#QW%t1;Vufr-$tvrxTj$Z42s_5*6}Yp5 zd+ybEjtcw6O7i+fc8|MEZs&2tt#1ePP$*~7HqjjgS2V4SELqv5wgX(jD4F%VbYx%R z?xmBJ+e_TYj*mR1p!Y1IzV6+t0^YrH#N#aRxj9r>gG*$00BCjZ6?tzURj?m9!@rY= zlQXWFW>u>j=#CF||DCqdH!ymTjk~oLcL5N_Ebf+5Px?-eP;W)8YFXh<#D~q5x_kAI zn;I_F4oO^gjwHN~Ix)VJbaZl$i|AQubN545&`vbHbjB~qm6S{ijpm}ZsAEN_Y{lXh zK9?D4a9({>>s;rR#xX};_3Cd3eTM@dmE4$&PrC9&Rp;PKrA5i>PYSc~){@tJ%QUZ1s!8j^Az=ijxO!wa>B64V>pc zA95~Do_cy>^1$LGG>ZEdjRkXTT)yZW7q>Whhv}Q;iKo-hvAuf1m!o6!qB!|R(^u$G z2CWh$%0+)J0a4V^g}-t6mL`YLS|}k@%Plj)sLw1&G=nc-$Hgm#Hu_HS#!+UJ?O4QW z;;X&*Nfj8askv2om{FZH#7VL%}jHUd6b!D4)NufdB`LF@Hz#I z1K)Z5`S~I5!QcAx9)7+=={fv(ff650_8bBEGM9em-3NcZoPT1RKR<~PJ^c8hSZw;eRe4(7AiZ4^4SswADmJ`QQ8$bqwTtynb^Ubw zv^f7XmETr3RGMqj;nU;7r^l5qJudu!xbOp1_~~vazG@#m{OEbH3^vF2N_wOA&~hW2Rr>ahoqrDtc>%&Ui`b1{}AK3IR7uipYuVQ5i&A7LnPBbTI@t$ zes0J6())1S?d{=V?BRI7C;qxlZVu}OtoNpMjEg+`AQv(*Uiz-DEP(&xBR1Ibh<|Kc zqQ*Su7pz?y|_#L`1HQ_PDy-PJ@3l&RKxhKf%uf-YAG8K zhlPs0@Qe+`lK;nh7V#;@N#pPoW9}Lqu@>G(>C`h2J-*xGX6_B{-gZ#82P6n?&-8dp z;`>vGFMaI(oO40;{b}@gV>()@nCG{TwBy%f4&Dny_o~s+V$|1l^9GE$lI$_rn7de> zms$rAmkP_mSE z{Q2*O8!qYP35z8?j(;p)rMRC&Vj%xP`QVF1KQx?^4_7zLZ!`&c6p)a|kH{+hQA)2o zs_BmUpF-9cMj`0K1WbAOP#Gkl{1=hCxpKiz9@WE_2oDIq6n-Q0Q!Xe+ zFJX$Xzwjtwws4e?zb?#plZ3|#X9~-NbA)q+^Mxl1mk8U0tAwkC8-!;H&lCPwc)9Qz z;dbF|!n=g`2pSU6lbPFNs3 zR#+&UC9D=U3QrO)5&lScnsBXfvyf{^mg~pDD}>hxZx-Gm+$nrO_$%Qv!WV?E3i%`F zO#fZshr-W={}g^B4ES~UBw?B`Qy3DC66Oh~2>A=w%#XjUOU@R~6)q4)giD1hgk8c7 z!n1@I2rm;}CA>j+oA7SoFNF^apAbGLd`b9*@Q=dxg`WujF8r5}-*;lYg2H5Be_@tz zm~gC+zwFF-Q-%DEU)saMDq(~0MB!p#o3LGYx^R>59O1>n%Z1kpZxZeh{z7=a@G;@j z!smsr2!Ai!C;Y4MZ^DDZuZ4bm_=@#Q6!sMk6b==R6iyIM6&49+3+sg^30s6Kg{KR* z2rm%+M0lO>Rv~}omF2r%__**n;U3{1gzpJI6&@6RD-2@dVtT2x!L!gAp}VY9G9xJ7uWuv_?m@EPH&!gqzA3%?O2VY`uX9wclL zo+>;|c)IWm;n~6qgqI3`D!fj3lkj%o&xOAfJ|uix$X^C#d7c;U5xyzp@59mmJ>f^f z&xHqtUkOd@u`_&7*hkn;m?<1893dPhoG3g-I73(>tPs`+8-*tdn}o}RD}|ed+k{sM zuNU4TyhHd4;V$7L!Y72k7QQHaRrq`1JHiiyp9uL|#gxyN!f%BB-r7A;I9ymDJYG0Q zxIow<>=0fiyhr#e66@}##Qu`-Z4wtp?~45<Y2eE8uy#X-VR!pXv7VKq4pzeq0j zHgbw#tPpmH`zEoUB|J~uFBdz1N}2Jx#eIj^?-t%8?vIK63E{Ki{)*V&5WXeue--;D z!u{g@wb=O!4$RjgQSZKD?=KuA?&E~Vi2HHELK5{~Bs^PqmGCa%2PD!zK#s=ZKSkSn zlgK|+*k9bU#XdqfR@{#k`!wN9ai1gh8exODHw)Xvy-T=`L^;k9-bSK)_mCrS{U`Pp zNR;no;p^i5uGl{iek|_)6#Ku0--&xFEUktp{_GRrWg zh`oqJdS$}d;yzF8CkP|reyZ443A@CdKU&LlwhAv4_bbUv!?;cC_lW;4;ltwotk{1m zd`aBj68k&C_r?97kUu-Xd@W%j$@U?U?{E_P8dJpoSYfd+EUXdo_vx740uu3>#NHz8 z6rL{JL?WLXg!c&dktoNfByRP6CH7!{*pYscFqK5OEU|}#{AF9ZPZawU;WTj%i+#4R zM%F8 zbtKArJBdDYzu2E7QQl{T&x`w;Vt-4xPuxEh`+ng;akp^$mg)BwW|K&FgmA35Pa~24 zLg8BBMMD0D2>o9nk=~z3jP;+1{a+-~{YFULWVmD!?rFjdaUUl3QNr=!K0{a`?p4A% zabHFv-{s^nhH-}YpDDahc!}^T;dR0rNyNKD>^~PiB79u??#F;(nI!C&C-V|7PLs;{E`M{NE5B6!tnwyAKu? zk|^&S5^K*B#NI-pylujj;=WGoX9&*{_aBRWoA63;zfE|b@Nw~fO8A_(zeythe+v6! zE}(t1aJn!;qP#yMaSgRj>|05c_k7`x#r6R z|0jw3`w!NfESx1gQFs=KJ%gW;DBm^0n}t6U{zCXm;iJOc!Z%5zb4b`{h_>el%Y3^vam_mDqJpH zBU~>$Q+ST>QsL#oYlSxme!x+WEyAtB zi-ea7?-Kq(c)##r;S)l&zmIg){yzA!xW6fUOUP$SnEzKoANQ?cw}pL#eT4&sdIc#QBkVVST(SSxH0o+4Z!jE7v3ejSE%;s5$-Xu zKOt26^>BYd?5_)dFMLn3C3EPET!VSXB!gGZe3U3nLCcIm?Q}}@J z5#ck!-w59p?h}3}{8VTpXn6#Ly@jd5@xpxJRN-`CiEx&%Mp!RAQ5X>}75+$g7Kydw zxk7dS0`_fUSNAbs-!Ar_3GWm>CVWDu?sFjg3u50Vd|&v9@N=QX`w$4nA@cwv#SOjs@CPbf0o6NM4sdf_JF`NE5ZR|>Bc-YVQ7 z{Dn~6uR;1Rie258fqk#o-xjL-GI0N^*#9Q{yD&LPmorT`NH|0|R+uL|S~yJ@7S0wf z5;hB$3)_Wjg&T#Jk=O&dLU^5UyYPPD!$Ng`1>v6&`wPOCg?|wKNvQ6pApAkGe=Xz> zgEQa3!ffFfVXknB@K|A)utLZm&}BM}!jpuHgssBm!n1|v2`?31F1$|2A1i0Nw+rtQ zz9`%yd`tL_@FU@8!Y_qi3AqQrbZudZu%9qX7!r;Z<_V_=j}!7^5#Qvyox9~aP3&Op^w}tNuKNNm0{D;uy{TA%|B?{I39oW_V z9dN9;=Lx3>j}@x>I|x@Q_LGF_eh=K2iTzYzhj5MXQsL#o>xA2dKNH?5yhpf8_^5EV z@KqA~Zf^?zB>c1ROW{{S?pZOsE$k!gD;y)t6;2jT6{`D7h+iW1lZ1OK_A4~qR!;cLRZ!gqx43DtclnExhroA-BMP89YP_7|%A zQSevyqrl_Ey;wL~SS>t3c#3eT@JGTm!u3LR{|f1zEB5Pz>V6j7cZmIN;V$7r!q%Bd;YY&HgkJ~` z3H$JV6w>P}94O2Z4ik*au@W^Y1In6b=@u`*83dE%ph*Ny2HuwD36+^?5<~ zGKuoOCfrMA$@>rBKHAZ4?+ZU9(SDx__mgPHFNBB4(T4H0kT34BT?4|r0PLu*dR`Xw zJQ-%z?^P1@s^C5h>hm3mdZ_&ol>d3|N1)u@2_VW_iMTB13na>?uJ2GT^_&^Xb8Bz7 zqa1UPCi6!UhHskaGxDkxdjp9yy2QSgM0u_jdpC(R9u@m;66I6%M|!IMC}%3`2YWh+ z%+&iEuur8O*zgp~kH3f0VCXwsiv&C}+l#fv*y*67@|3w}J_Yi;V_i?`Bmbcn-Umh-3IB}H^RBagp| zjjz0V6I$BQv;u*O>ZGH}w{0<$;0;jr|S-p07}rh3w2xt#RwjZ1Is5z_mwxbzlz(!=(m zo8J3z>AisT+TrFLPJQ>m!CT++k={VKQGS@--1G(@KK{FUz<)4S1A zK5T!u>4oFcyZ8v{700FboF~0hPkPSx2pm0q8|gt6+`}nfM_hXQkzPJRvA&pM-SYh` zu6(@5+LQcv58Yee(1lU?rF+tQBQCwykX||box>^LD{<*fMS83!%ZDl6Eg$c>4~?^;iKgCrc&n-`bf z(^wC^zy#!Q%2yYc-VRTCShBd~yF4zv%h1qWPGS;{R^H?HmTxc8bMzUHwYcd$7nfcD zYrj$oKn|yTPsgRVAL&g+7`8_Urz5`u2*-Lm<6k)}P8x7_&3wm?*&w(&7|w}92Pe*G z38zD0jfrptShG2YQ`F%I=dJJPi_kAoVU}+=PN#g6ReUykukzKwC|MG6h$GAA+6NssR;dh2oZLx!;h{!DKSPA5G+ zZG?mF1_!H4C6TtRB|}!t%*zT&?EY~ zlIi8*bkaLl(qkXv@#|W{xDzsT4yMPG&ti~HxYIV^y-g>OgrPs*wIrS6QG|QV({9X{ z$F*_gYkyQro2`BneWiVWAcxlnqM%rpaACl z{E42wM<0z}pq?_NAb%t^Pe6h#cx&JZ5 z9eG7~a5xaYY3IhAl(4yDV%WHHsfv4QcuUTha7dZ+A8HFvYt0|bGHw~RVNo{XLf%Ej zh(LHic(=qI6TUiZ{FGtFgg547?+7XLYabbDPafD}w3gDREu23%r0N<754=A%BP|zAklm^1x<)Ybjg{>Dm?!-8ogsBoKzy z_(FI2KS@v}c1mg<_rxAwrDHQ5XParc4G3>R**E5FL2H>i#`GY!e+)*OMU32;FDH(l z`TM#YZp{MQyA{p#LBM(WcjZw};?ptLM1TPr;Ek%WU=I{SR$PZ)S; z%k*K76y9~zQ75kTjT^e>=>umOp}U3*923qD-#mo%*m2L6qk^N;{`mBPv;BV5ev2=3 z$JEx$()Ekz>)U5ee`t?|9-^i1cTKuJKGbRdF7%D$EVRTEXpiLZ*Ey%5Rxchh_A!N1 z!!=)Q=@=c(R=PA5x>V4rq#IJRlRfnXqAY47xx6UR;e{b|zcj@i2&y>9ZW zHT!+NjS(9bwYNTXa7zdJ-N7?YgQ?3bXe(vU3)J>G(~wBvUFd(A(f;?y9vi*RsYk$Lj`l%49#Uu7K91f-TS&B4+Gw|@jZnLB zGu$?ss@iBuOdIW1ZS(}%X!jA@=<&`c5AJR^C#msKT4_;SD=ms?C9UV?agV4mvJXm5 z{dC7j=-QSQ9Nnq+vEw^kp!HH0qthAVjqzIFoKgN5HOgy!d+MOkaaq_Hu15QV#%WEZ z0|&L0ngz~Cuk}rh^asCdH}m@(G76tO=H({|l9`4jW|*u55= zTW+@a13o-48VHRVu9sc-YmUUVR`1_ny}cW2vhwJX$M6L#e(~BL2qt3r<~Qw6aM2J5 zU^mz|ZeSS89>1AzGcK(BKC1=M{k~vj2nblaVGHbmkFO?kCBp@Rr(pBPpJ2^RB!c(g z3JK}W#;!nMI9AC1f&H*oYy=kLO3a_1z8Gff$M_Qra8D*MC%Hc&*af_Zv;Ulq)tH@x z#iGytlvg}pqH+aW#)%6Enn>~oPxFPqQZB-(syKgs?ai_PBlODIYo zo6o5x+k8qR#omS7Q|%GBbnk2DB9}CqZ(aAZFF=jcZQjxBZ$F2E46qZh`e%hWgmz1huFVC+@bbC)IMYn#XDNr_C}OB$L4*`VfHsz-43^t z@OOmWg_1YhKZd!*=F?`+**`+~-`M=Z&Ts9jQ1$0+J|*;m{Tb4H(dLsQzYFp^1LMu$ zXn5qB!Dmo|JTrI>F0v+=!Lewyd^7k2GQZ3WUXz0>1v9u8$z5&+H=@*6n88&L-A~OR zpEkbI49AkJbly`JPWJ!5BQ0lpX;AhC8E)aYeA?pLd_i+}l?0W{BsHRRp|2`Nz3#mMq z6nq{35-f|sCxH>Cvmz}C$v!9~!WTT+6{P}^Hmf^Q+Q z+fstRMs0tV5?qZ!oZl~a6Qp!Ozu-~GFLhKf4IQNKsNh!Q(4GMlcIOPR|JPd7HHv!D}e2jNtRorS%!X50LbRjNqk^ z%f^i011QTG8NsRW+msR93vJz;5ln;QmW<$Xggi4NcrW}4yMxPy;lsz>!MoAm#ofVc zP?gf|ATDr>vhLvV5LUQ5*asQS>JH99^xCI_&m;QWr-HwQTo!#Cl=buW2OY!}l~Aeu?(&py6id zWhV`MaifcdCy>x;8ot1Ix`qZm^R#6u3`MBZnKbYz-N<#~>IERL_ zk?FZKJcf2SkB0kE(QOeJcr*VeG=$-DISpkH#T7JMi|9Y4;W0#Chp&DmEP*7})36zO zzzf)f0BU8@a6QVyMRNk52ICi=6WZYtprIc}Q5v`jVAHS!#R$?6=5R{G%cw;!8j8?> zi8RcDiYC#p8=BjjhI5fl9~$`Kh-4c0DYz8ng<_=A(28R9rJ)&lrP1&%0&}I8uo?y9 zG@LLK)#*=zADYKfCyZ2;fuRI4^wFgg#o%|T6aEAt1ZYS{c`O?E83CJy|6*)}O5g)6 zCJhfkPkl7}3;Mu#MlXKkDX`M?-wb==mH1PDo|H76-r8R5*!|jG=h%Zr;)Mvb*s-TT z3XofG>yN2d!L1KplegYUq1oueRIPm}%plNb34PvGmIS=b!c+pcp~b8}`=P%X#=v!5zlNEZ&XzixlTQ>FXPNSg$GAMLX;%+yPmkt$tg zOzE=C;5WK-cVe8fa!mhXgiJ~ITM+3hjHFt5Y)t9KIi*wik2lj85Kk*8ef=}cD*v;M zG`=x1&~J?}Q&{71#)j|IbZjBND!5?#{DGyRO8a;s@gHm!C>Qu!Yplm9Vh8ofk1 zQ$@=}I>(BdiFBr!Y1H*AL^@|8UOIczX46Q+ZvYrOOlzW<%1;<+@l1*--f?E|DCT7J z%Az1#w#|h6!dvrywaHBm6>VulH!G>@qD`RW=Z4ubmNul;-&j^jksV zg%IW4Mz3y&*m}|QGuPw*J702u-7z`9Zjl_I`XvXb1jzx)Iyt~9B?s53aZ@Yoxy3MbPB-`C6e~LX4Aye(YB89#- z@5H6qvynnSdm)E#y9Q0y->$&GJiwlY@EP_s)JuB|LT1{lP@JRe78Ec`OYRnwKuIpm z$XJ5Xo8_r2l!Z|Xu?}JmFb@UNcr{>VW3I>?iG<;j&st|LLr7T4ILZz>7E`48??4K} z4%&+W)%+@u!tr`g76fg67f|EGpa)QT6JG~n0!QJu6fiK+Xbc?Byj~0RrOiBxc@;ov za2dB3%)CZ>m(qLCG+N#WBr@0_ezDN}eL#)%gQlXg<{tuTc+X<`e+=|f>ErUp$8U`c zo{gq8FVS^k#)p_+_dW=3$Z?Q9yo#|?fk{jsL#87S^U^>u8~&eu6xii~Op4`mIQ*54_o4yJD*~C+2);l(5@+Z*O7rSK zGUq)1w(~a)-32u;yS3c75I-B|(63m*>$T%+aQGe0Y?i(f39G}rJurYzm*-?+F7`tO z(7lYD-mr{-B^zfBKO!^-h7wx-4h!$#o{tmN!UfVuguNHGJ8_Pf#8kHJ*fgS08Mba3 z*?=%>5b{&B!YH$ro}ksv9fOO0@ z=_-7X6xwy3rPxp)ALenEpEvE(ssZMki6IdP? z#DQ#(QigWj?#38?J;2NeBrzP17jT;0{C3fhV;CzVP)Q~J8yfIKoI{?c5)aglAwQDC zIpi5s(aa1~@)aMxo?MA@sOrW?>2ACg4x4a>W-!gHKnh2C|F#cL4?T*+%}}6^IBXc& z9fHGfUA$e0@(Y|}+woY7IYK+~yP*4UW^))BkK+3IM4UM~kh%%;c1|H&`Km8J)0r~~ zmRn%hj&m4;4X=XBi?BU|bNC6c^ukhvuiy?}2Fo-U@^Fspf@L(ruZH0=xLk}A2S+WX zI(%AQ>DQ;HQ#ZP(eE!6*O=BdBM5TVx4Y46E1a#E+ItQ1VD#YAg+l;kFPU3(-mNEV( z@S~nm zuNw3b)Mpn?-Jnlu$Isxv*L8J+KIO0cCz@#}#tB}3=>~nqug2wiILyJR8}wO!3Rf0r z&~>^&f9vlf4jXlY{?4xk=Svag0-U-*U($}x!Qo+?(FWa%x|y%|Q)^Ia)u246szINE;c;5np!|p>Uo=$>x}V|MptCVQg>m9=8jqut zX|9c)2EE)3u`xEpc&9<5&36Nmejd&Dtd8Sb8`FFnjq(450BmSu%sFUbvohLXs`A~| z0HrmcRICU#lX-BS!e?>>t1FQX2`_W+kh6C3Ry1{C7gH>Rn;G3el!RGo? zxKKueZO{$Y=WT{G7R}RhcTFH z?^9r#hf}rp4KQ3u3)}ls81~^*?Y*1f+1|yFA3xKGV`K<_*gY2^FWug%d#+~B@+Ev7 z?Z0Qb0nT7^M+2OK6xeh(>j2T-#}vAdMJocli2zUO0KPRbjemwQ@-hT?4*}kD0w8lI zhptV==$(=ST#1k9Iv6HQksLlO77e7t;XkZYNh$or+T>s*?j{?tu%*xaZ2;GFHUI;-Jy#R z?KqrTX-w_NU99CeRjZFias69Z=72wS3QDb7{jczT52tGN6s!r7a1LWI)#`llZz4|B z>Z@TmjTW{#H-WFksapMNhG(mP4VObWag2n_RIATJUY=H0!?tR5mWXO`x*I^Xx*K5p z8U)~=J^o@C)DX>#K1Y;0b(FY1eugoAhlDi7v|vy*?~OJW(=fZUFnbSqHbHqcvX76# zJj%~Y4w*^+U;30ISL5|`RLymtuaUFtMQ}KWj%w21djRv!reZ-jCMQ9g##UtshLjo13lB_Ay3NeZZ|})~iT!2R7SIN|Tr@Dk%3HlQatiS3p`5B|x3SS`|2H|8l zmqVDEda)y9j2S>-E{m7*R$Mk{IWN;94P#ZsMW~i@t9D!qhYmU_Ik)*5Ir-fQhg<2W zOI^S1t)N)?oi_VBj&Zqg@8Bxo5b-bMa4sFn?sU{$iGbbQN z&grO!4xuKXXoy%jbKW^#2aS{S#;BZIB*5tuqF!g?muEI z(*k|RT)wU!pGORd#b`&4UPs&y+` zwAyNGt!-(mb#2uLTdB2Af1l5p&&-{B32OU#p8xOn`oErmllM7i&iS5mzUO7yCd1;=S`D8M6A1nb=YPzREerBfO8kSPB-#WL~LiI zF|01T{uMO&F+}hijPAO&#%*1G0a^#=u4`-U;k=K7ndEcsW@x=VOc9@VH$y$P*$kbC zEG=;Ey7pN&@)kr~3FmHxdfmt<7Iwam)7=d9*=93zJtD4Sq}dGhyOGZ!;>U3QvKU^; zCZCGCS7@|Z7A+Zo`p$Twg96wWM*Ynh(Q z;%qEerEoa>Ws&cwOLnHW*THl#4XHRLF7*?bD|Bs!kl=VE;F$Qfo50%)neB?%40R$w zcnY4Fxe3z7%IB>^u0#TEhTioOpeBLM(2P4(f^}G;7@8T9G>&_5#@=xcVqH5JVw+9R zNoZUfoNF;TZscW%xPXzyIELDFd`-m<5ph49YaF?*aqLCJpWs~M7@lq%`RT?{=-%q% zO@;Aru5pZUBiA9~BskN%hoHJ4DilBInRhs9ZF=`9oPGk%^zOUxybU**$xQE##j3zJ za+=;<1`l7aX?pj3cut2iy}OX<*}E?z=0!Lh{B(fnyd}jcy{kP9I*&DC@2>X~nBMgh z%vg^EX47*vJZ9?S&SfOJbElidAG@5ju6P}L*BwfUPRueFwpo1fW62a0V?XInWm}QT z-Z5elOwnwBo-|vXFl!7~YW6=*nYj4~mov_E+>cw?Zzm(%$v88Q?KYdA>k$4TT$#D^ z@r;?po<#V5xI(k{`H4Tw3(ZpTGk=uNGCQANXyb$G8m*i?F-2`joA(CAjedgEK`~<< zBp7WigooOC+D*B?@h?XL&X#+XAh1wmWNr0U7lx%F+6u8HFu=)jeN2vKjLBCo+sdLDt1=)a+GQ}_b?3V8T@dFr1L$hczp6uyn63lZ&1k%f9( z0MEG$j6#6V18#-myH2g~Dj)k!{FoDz%(0ba&FR6Ggf6_>&Y5#1w$^mvrx7?3iRi-5 z*g12VgDx^Ld-fNKF`r~I_uT7I3|;o#oVmkruZAxB-JH2aA>3wx%l=c&+%PIh7dbe4 zE?>(_m;GkW?B_5omB3OUW|fU+mT=jx<;=}S`NqAHGxr_D(S>irQ{55v)ZF}>Q0_sw zt%W1(Jmk)pV&&u&ms`?h2rr@4tnF@R55r=8eTZ& znu;PeV0=(oM&b7=&`lG9A{AGh5{J4?JlLLV=AFQHti(R9DA@j#iXR?qs7jok z1Boni2BcUNZ&@>g6{iK2_+rtARBMV@{2o!#HYB!8B8-75ZdNdkV#`ZVT#BgKCDw68 zM;CSHx&raNkCX^>7`ACCQ78bTJ$YdKTDH|hylcG6h<$LG)?T}5Cp;+!Z#UQ$KPcoU zTDo5%F9)s`kvLAQGTt`gCO8U@@1*Y~_XP1WT*x|g_D*`dD#Qno4)sGWKgpy@w*)KQ z?B~cp0`E8$o(!vOCoj}l3;J39WAc+v!9f}LYYt3S{=w`+kmagOx~uSsX;(}zj$${% zMJzlfL82_mXIp}a5Htq{jSiTkUn5UHwzb^L%!*RTYj98|!PX)L{+c5rBLmVXrWcOs z$!&19)fyCo82_k)??gByxySYTr{PJaIG#ctGbxS_rl8+Tm1*G-l+ox95bK8MdlU`^ zLr{Wy0v`YH1lZP!WHBqe(_R;Psl0CcE)vjBJ^+VqBiu^1!k2d7DuHQ;Cyck1*bO(h zoxA!(#i>>|$Fg9K!HnJ=OZ-_2?IE(^jxKGi5IZO%oj*yK6?lA-4E{mDT^>DBzg2n=CA~wO{^Fnq;pEYhL11tj( z875*o0vEdxRz@#UFmNdx6iZwYJU3W7LTJVeBx3C|F)A{4dX;xWh&D$s9VUb{-;E4r`R+ys3X@u%NG#TY8Yvmmz`t;d%YFrT zQjoN4ST*5VbxXji&$833`fL*su-vUSt$MI}1}zfZz123USUEQYk2!+rLe}OiKbZ-5 zss0tq9ZU(H<+4YNV6SWb4a-GS4rIA3n#O7@njW_I(^;;oYa}1!7=t)iFVSMW%Zcy6 zxzHBOr^z{5&L!h0T^Z7n0b3dDCNE3hnB zfx&G))d05{c})bRU~%3$e?tsIXVQ$Wmskx~yb7XLi z4}2ArksK52;h2T&hl47Kt#F)H_>65Q1FR>fcN4+Dg>dK_f;I5ZG4NG$u7$WBE@bte zxsx8Zp{A--7t00A5y~**b-y~fS(c~k#_hx9UhYieVSCs=lw}m*~jU`sOv4m@o zO~mKjSo}>p{#QL8tDXX=OY>fp@wO1`-2+*Vt57rVZ8JIA2rtKA))Scb+#Jh-Irg_6 z+>fR85T4kNvz`j1qxFzACTkPXWV|iJGB=j^j2lb1d+{dXG&dH1Q;vY`P&hVADW?%| z)wh&zQ?QJbBQSK_6m2P|5ePJwDX90snmYsM*i3Q`9D40&z!l0?4srx~*Hy=If)l9Q zyY$@)r=9Hc{t0-}4p$eZ+n>TI+iD}c9D{W`1>~Bfae`fmWtH$Mu-{JB6PL7!3?xq; zo$yizq-#nC+Q~kQ6pz3K`pnzOPD6A#90ifAjn>k86#X#h=5B${9N5W{DZ5!pS_?-> zWDgTq%ZYxtOsj9}=XcV#2`+49ZRNI>{;h8Ktl%~m=g(%C?YbBa{YzXA=bfVe+i+S) z*mEozFo(C9W#Cg+jji{pM!zTYVffj@-Z^;9k!k)?{B}4NPr5q%m_08uT&WD?7va#t zV2Ow^2lui}UJi$^m~Hj9q9)*`LA_E^ebSDX@(zb%eM!oupLG3$ZwtH~FY|AQGn-m^ zz60lN4d|!Z{2edN*gFZYIf6T0N~2>9NY=Z!v zbF4pk6C9dIFbksrb9f{95QNI%ye7Modoyv0iQbgS?6)cjU=GYF{&trlmcvm5*$Ias zOss{AK!KYw!{f~Grc6YfZ6ZF8z*%q{AG|3uSUtIQ_3CK)mx)-L6iZG`g`0`VR0tro zIlNmklownIg6((xvwQ(TorRH)dD#W#W+FXQY`UQaH@M6|M?oYDHg%_mrI~#!J#?6s zSoK@HczW1c#N)3ycrVctPq=M4j=r5OFt_pb^6CiB)ba(d)+I zZ^{u+4)+3q8No{y7`1MS{k9(|i?rLa6A3r@GEb1lK--z(Ky9Cfb8ItN28TA!16-lp zgrpp!5kd;W6WTP0Ex5_d9%R1B(MEVVl0BP&SRUixSP9b25G>iIIJa)C#5}l=HDLP% zQw--YrlT0r72{95cmikk1;J#Kkc=+N>cbOMZT(-O|&)F@cDVuFiqpu0DEoj_Lb4 zx)zl746IteuEQ!_yKzHTY5V%F&7~!HadP|m(!RCry6(s?M0@Xs(phDR*@^P9@>z*lWsIDO$eG<6ySrv~wXa$?b5>c& z?3p}Wg3~FdO4oIFtRLv?D&5fDv6io1{=Zy}zAb&hDy&&s8tv^ISl7L=a$|4TOkWq9 z`+JQ_T#YpKZaf(Z?<;NYY41IydZ0Veg0`$_T0hX2h)3tu&-MBUjr|{#{%>0Vs#V(F zv+n=Zs=?6u+q*mPitYcq#t|(3zu7SU?XK(TUAL*dzl*~NJBtJcbb>GX?BL{(=}caF3U!n?xp60NHZmVp>|}>S zCoOiyhC?yi867&R*cllPRg^eRK|Uf;Vz>d>3Y^^W@Rm`6$+7@v#yCacP)9N1LsLqS z%`TnjI1`t<|cq^GP8 zs4O&LWO%qUe6ln0VE#p0@}Z?1l(p2!GesU_gdYqojbaUKXBZkeqQDs+&U5lg<~oNQ z)Q;2QPF zREE*0IfyGZ%5jWZ@=H==?+(f?Gt!QgY+v+3)SIGDE(qs4xicN7G<>W|JIU=cJ2V_s zL04@$+AY=zA7ko~jg-h-;*3F!8yDjTqJs^)81HxU8^*$mo#AdB*fJ;V7o0!J84>z^ z1gQ%~rsI2aDyx!IOtW*Z(}>}0_X zp*ET|4S8&M%p|8Mw3!7@4UeHAIb}{ZhX4#NT_H5A=381&isG_nIN7j6 zoIIE(3(8EtJEw$~qczZ(6S_9C7%j>R{Sei#Lx&cpYvR>(O*kV%e?`C9p$oS_DQ>5i zr70yp-{|GnY(Sb`hE3XECDmyvxp+&eN}O<`QN}c1HAjb`q7rxHpkb!7!FeclA_~n~ zObt#|fd1$xNI;Lwf`1mw93Agj0unlLW}-T0o6+FFI3~05rOue65Ia$N3*8VdHro0M zYG{WZwWztzEQWUy6oEbgj`F zZU5GYSnQ36C8i!45l6ctVtLw7e{;~nXTSoIBi$Pnn?J>H{Fe&9+Zn9o{~s0pm-NC* zK5i~}mffCa^X^>G_{oO z=hI9Ge@WBJzceAZ(`cia045*Ilkc|TN}Fi`r6lYCDyk0t+l*VRpnLg=|nu% zP!)^UHZ1bbNkX)>r6$(UQd=2qscmdXR7Y#;VpUdGf*bm--d;a>e0fD{b)s=uEM8sL z*ycw!#~PX&S9)NWh~Jct4~zcS0&Kc zIb{pxC7R;3%c3nYKjY%2*do^3kMP7-M(gTQB*ZE!6HWNBEMG)Wyg7+q_DVFhR@Bv2 zTGDV|`>e9^IrSSm2iCXu#y0oh)Wec?9 zskbQ_uWec32TkJ2#`>nl258h(e7S#?5}I406}5G>$3uoH)85^=aYMtvhE-j?{?C*R zboZgxyE=>cs$j1y>Z`7?a!H_gc1FClVSj~`&rRwScU}^!23D``N_Hjtr9K8TTNH!H z<`%zi7fXt)z{7e@#(s)wh1F6Uey+j$4t*P z#bYqkWJ6{9G?pc?6^Z6pi>a2ch{~4c)=k<+fbVYMTg)Xl zMrfiR6-XKV!7+f|qP3?Dfdfr4z6p9QXp7diB%&3K@u1naHdiDnTAP!GZ~C<*9&Ko@ zM{-Reo`@#b3|iyK@!i;5iJ{QgwEu|098(>OCt~$YfpN98HP#wSi%Ye(mPV*3DPP^o zuH~e~kr!)dY+Y32*;2CoX8uW^WOeJqC{DK`5~udI_w;mivYUM~NwI>!4W<9CJ33YT zVLHDwGi)0%s+!wsTPkZjJ=5;`)}7Xs=-<%er}ZqSnxhcr-9kIYy~qC9<**m8YZ@98 z^^F)JuGanNq}dvy4VqJOzICTmPf}%Fw7w}YHF0z#7YpgrENFx2lY=I~SBZJzk~L_? zWa&qHt-@$-t!uGNw)I`zYxS$$4 zV|+!Tx-QyWW3d68NH=uO#RA*ixgOfK)^F@yQ*8bWI$?W~qE%I>Z?oSBGxibF5{CGP%>4VWsPS%<}GgD!8VQaWb^z?SE zUboq=8%IiYV{1cliHl)(pc*CWY8#gLNioG%)?k8+)uqg^T)E7C#ZRcg*w9*6muPA< z4ffCZI*Ko9t>*;2seS!G*M6tHY%merbZqZUTCka@t7@Z*5|x#WSj>_e6Mv4WO=uOByY1;7A3ERSKn6%H}KB77v zt>@nBWZHCe{km<1M@Ex;wj)M(i0Js$E;(RA+i3SRqtDZHZD2 zt`+-jaFcqdYs8#}fm;jpHdMx}PIt?gy5!f^#;cd7FO1^ zVv((^qy(-SoW{L2_uzL* zJ5%fIu8*nG8&RdkYHSm+KqMD>ug3Mwi?nDMORzQ$^!E((yH#lK?M<$bHErpeR(CNE zUJ-cez|Oh8nH!7!HD%^Z%)~8;`pVWp=1QXgKAK3HmV15F+OVXdv8^FJ+G~e9P`nBR z=eqjnqFP*9M6uyUp-{Cq6Zf@q%aFDWjdiD7J#?(=SsU1I*ES?to0F@Utj%mAQ!c*J zYe|LRlFYLk*f3Y{`B-|^boFy1(rp%g6AJb~+LA~c!j($29+xliWEtGzQuHD;Fy*q% zv(@I-X6$aOv?<^0mgVUx+Jq6iycVk~t{Q!zwGGYKz|~gPa`HRpnly zx$|P8wFmQ8z`nezoyx|B>e@x#=o)O7=owojCfRtbI$;(hUuDL$p+{VcnMu`M{JnZ% zy1~_Cz<5k@UNm67XpKiJwP5+;lG9aHw9>+(_YSj$qz-tjI#@&8ahAH=V^weEWI@B& z@1ltoW7b+s4o#RJmNnM3px%DjxYodi%Jc;gsGrKb`HDVs;FRVhu4Y#wq44 zBW`Z3Xs(Rca<5j0)gZaIGxe)&;5~pkjJ8Azlo`0?5}aVT*Wdt03is9vr+)nSy01;I z)|f(JV^y`OHPM!Yy9Esx*=hBejkx0y7qys?*hQujvunwiTz zuX<)~^fc#1R>W%;)wDEVK}%CN>f+trGFMmrM%KUbTKxNS zi3)tw#cvm`ym&9G0_%&n#`7}6}^SUua%ixS}}(=HJK~^L{sf@?C;aAqLO=M3NZIUd;o*j0j;>>kJmiuqc1t6Ig%3^GFBqt?Qs2j^@H5> zP1^)^^>%df@kavtUSCxl0I6FuPrt#g^2f8br77BOsjZJ;%i@bPSF7pf=SgLGX;+m- zV{vmaoO16rb&(Hjn459A5wkePd%HTi)@{PwMs4Nsam#*p|GlW8wYYM@0{qx=$?TF@ z#rz;-+5GZ3#nXDb)_1k{bsbhb6E}wkj_JTS@7g?b!|d6J=wFKm4B+bZ8{7M5;!~8z z;0m#m5lFeZXVcu7eLXWfXU#)QdvC|uWAL%cP4j1NDA|CaHNCU1XZq@%;+boTXEv4> z&%}qmj_E)JX0Fyf=b3IDk10bG@BVak&g2CsLaPV5JNnmc?4H?&Pc(vkh~pCMhkezW z9YwUsY&+3w4enzW+F9ydw-l@PZ*8X=wYN17E(r&|Pp1LT@e+@oi| zzup@oX>(S}CZ`@oR?)cJFUi|fxJ!Y1zbIY3#vDBL;_1}JUVJRHGg;d-yTaO_Jz~mr zM8M#21#I?FW;VxD+`xRCT)c4aw+2@neof8d73eD52=p$nQ`0mzx>v#bJ=*o_iCaXt zam`0bAEzq(_}R9pq}&2E9mQmUN9MEq-kH`WY!Y#Ypw`@t_iCTK zeOw;AeeCTCc{yCy7`UV0NyBD%QG~1eSBxjyZHIrgkA)kH_r|UbiH;4O>8rN845dy;UJHZIda?00Pu0za z+st{s5f6S7L7$P?Zvr%*0ZHE_@Y#dAo8#3et|WrlaLqrf9N!~aR9Sgs@icC_qP-i6 zWB8axXD2?G(c*n=#q7hpucI7x;9VI%+CCKSpE&SB&ogp|4l`dVVmuFi6{sS2%C_ut zv(Ag0AKvaqo+7JCW6{nEs8ueIB93;1;@@7M}YMedkw;d7nyGS3ffhoq|9YcoDGBzFwnVwyXK zUuW_Tenl!RZ3WV1)S1Mw+%Y&GOwX^MrKP9rjO8YMrAc3mG~U6lsim|D_02$|g7w{w zG-)!CDl=h3F3%kkOndR5X~XTGK5dqtHrTFR`^&9F9WvrZaP@wAcya&q)lA=J(pT-5 ze)s`Ngg4* z94__zNF#5XpJb%(qbGz{l%%FFFzGq2+@rwr7>4j|*VOc*)6$PlOFt$p{TP$}F+UY& ziR2N&+vQW`k2UF^^^=VCee{IzCEnEZ<4k&vN%t7%c??6=__Xxn)6$PmOJ8ixCnJlk zMGD}}$*}I?ZymRFKI317&XnHDayRt92d zEo;)k-D%;iY2mBW!hFG)cTnCVaNhVDiShKNcM|0JQ8>x-Tj54xJRQY=4xV3~7T%!r zTwg|FJYA?T*N>4HFJDhf|1F*8dNC3u{ygoxjVXswwCR!fcW7V=V)=2Mzu25Fur{Zi zzcJ|*=8q4E6KN9v_qA&9 zQ##Ef-n8eWCF}Zn+e^w0{GlE_Ptq3N-8$(Zk$K#e5~IhPDRJ(jB<;Bd`=F{$ed046 zrTa7=y!`}`+Tneiz_h!Ax(n;e)l;vO%b!6{dRN>OfKO!jX}qnc*~RYv{K~Hy&!^qF zkVx-C#-AWEy{&@?Ol#|Y0tfxDm|w$BzPGZUKy!KTH#)tBJe$_!1J&?fe)#BDMLARM zC*k|_UDvWCB7?dIpoNx9QVlsku9Y<|zh#B(L$c@vNF&~$4^o%?bInKNNo? zJ}v%C{H6F?@m29H@jdYa@gHIciy`ZsEe;pCFJSyZ;zaRKai%z1Tp%7N#>6G!Qn5`u zN$e2Ui5tZM@pSPl@qCd##LfC$C4NcVDc&r8Q@l(3p7@~nsQ9G#toRG@H{z?}+u~mF zLy`L!)+b9GE{+xt7N>~Q#d2|hxKLaqHi)g_iDHL%viMn%`y zZ-{q_-xGfzJ}&MSep{!Zl2T(kUl#J`IF5HqpA;`tnLq{tudVSKT8sL1^pk;0II&u+7hA*=#8u)tu}9<&fU{no7ta+h7OxVo z6K@c26~8UsBR(iTCjMCbsrXBAkNBGSXYnuMM`Flv>o-IkA&wCzh=+*yT^!S%`C?RD zEH;ZLiu}!4w!d3ERop6GAYLhcS-eTSL%c_PNZchpC%z>9L3~^Mi}+t+1Pd4IlPB^w z#TlL?P8a8h$B5Npqqtmb7f%-Z#52Tm#Y@F&#OuXxh~E+K7atR!7Jn}OR(xH2PyA2} zVNb&L3>8O<9b%98Iq^dAtKx0q55=E|zZTyT|0dRCx#cYrJH%e`Lh)Mh7V&ZMdGYt+ zdtx@;I>~kvic`foVx`z2_KI7@%fzpXcZ-jTe-QsuIB=Z1DOT?vOn|PAgA+8fQiUZ>5;#uPP;w9ou;$373UNNTdF7XBN_u@O^M`AW^ zkg=VU#5p2=1)T8>;tAqf@m%pj@rxwpiklU_i=1s)cZ>Ha{t1Pj5`UujUn%@s@fF3t ztML2c-xTlUy7IHdToUyitMGVnvf}563l(1_)+)YL;T7U4675+-Vn4oF@n?wViWi7i zieD6WiZ_b4l8|$k!gq_iNtE*^F$1q&V|cPyC3cG2#BYdCi@zh${=Fh^t}#4J94j6w z&Jm+xqj&;29WS_6coT_!JWV`P@fRt4nRvD0uUD8qyUl#xQ2gBre_#B8;(sFU5#QGN zcSRc)NR;Di|$k(Uvsp6R=%D+M6 z&t5b98}T(UYor@rOrjrVkkc&dD1{f1Xx9>vZ_{PE6BS-5b}9a|3J-{L-D8L&qe+WDeK4Il4iUAqWHgw8ToE~!(tAJbOj2J5hsdM#S*bxJc>lV zDurvrCKBcMidTzY5pNNHBtAz%U%w`&;&*oy-bc>H@7{`bftzj^iTDxXXvI%b_z-cr z;*U`HC~=|U`3_^2yGrcV`CjoH@qF=O66vp1c!zj{;_p!SF7Y14Kcesx;!jAl^LY~b zdsXpoi2o`6Rs1`NbeW?-v^z^2A&wHqi<89Z9o=KuUv&4CduTZ#JT%!0kg-;MyDt^7fJ>r1k&l9f^Z`Ap(i}#8Th>w$~ z-&5pV%leh#e=EK&zAe5-BHf1y|Cbmkbla697KmfSi6rtJu5gJsk3{+W$!l`6c$Rpf z_)YO{@(B0GuQMj#hq)DgnS@^Vh_5RCJ%#@weyI2`Zlp2&5OFwp1ok@$PY|alzD(gc z;sV7l7EciQo7t?_MdBUeJ>oCK{}KS#8^A)ZlQNJ3oUhyjwK1p1q_-=)J z#Zwi3j>7!CZOXe?@z*N6L%c!p-w_`bpCeJPz2Yd`@MCzqc$~OeJeNd!t{{=;dWCN% zQU0Cc-HQLA!jFqjDgNgQza;)v@oy>oj`+Uft%F?onPN7HdW;pPiwj89>v-{WahrIv zxLbUSgq#n^LcDAnZD*Lj)6Dja77tSVp$bnI%M^dK!VATi;+HDiDju)+)e4_1ZdCkM z67{%V{E_$@oqvzOU)lBoY!g~yAN6<@0GY;nHgs}!yg>lObQaie&; z&Yvk>E?zBuiA4D~EBp=dTZ+F=;U9>PD*h)5|4e+DL_2>+VqW=A#s5|Orx+TK^Jsq- ziF6|r9wm+!CyCR=QgJ?sd{KpCVm*oSyT!}IJH_Y3_r$-GXm{K69d*K1&=%Lhcxa$B7daKSSX%ajxQHVyn1{M7_=tZxZhipAp{| zM`8_Rxd)TDMxCMX5hU7kl(J*1Uwl}6Ox!I#E50bcEWRSXF1{LILaO)otbH$P3RPiveOq?Sw5gWx7;z{Bf z@f5LF+$3HsUM^lEn&(o`!*>+EM>Nl&5dVn6Pl?ZnFNnVs|4ib(z<-K=6U}od#GB_( zU{=UYXP!GDJVoK@VyQS!JW`B{%fyq!c5$t^Ufd>b7tM1fly|klUlwZho!ad>^@pIzk;??2~@p|!o68Brob0P2vg`X15^C85)pzxo>_r!hT zM`DQ2QIOs|CjuuZJXt(kED`653&duzO-zU#qIpgPx!np6h+D+V#H++Fi#x?z#M{JO z;%@PI@kP-*FG6{LQ20&p&*I<3e~RY05z^=J`3`unI8mG{E)XllMdC?fyLhtLEuJr4 zBwi(6BkmM$6u&8cTYOafk@&3my!gJjPvkrG*^W#xR~#uGBu)?y5f2wID}Eqm@;MvwXNjZ4BC%MUBF+-cb3f!eTH%FatynL%h|9$uv0pqx+$x?g zUL;;6UL)Qv-YMQIJ|I3S{z&|__&f0p@lWFW;y!U`j;oJ6ajZCAoFmQ`qhd__jJQfP z&n2O!ZiP3Ar-^5a=ZRkxzb1ZDG|w*~=YEAB5_gH_c_z-kt?;|zKJgy_saPRaiw$C2+(1sUtj~&@#WTcnMDu(T>2@l7qj;P6E%9#g`{Hw=dESZq zFDtx9d`)~ybod+*>CE#_aD>96#BpM=c&IpCG|xwoFQ#z4xKvy&o+zFseqKCJG|x{V z=L&_tAnp*a7w-_wb5*4Ofx?f7<~b_jf2Qzj;#=ZhMDzR<>4x)pBbYCa6N|+K;xS@O zG|x+sZ>hrOxhcXYDcmj&h+D+7#q-2l#M{L0i1&yOi;syEZ?7%?iY5Kj`#^H}6xtMEp#PrOLHOyo~$vApZV8^oK%`^AUE zC&Z`3H^o1Te-%FzZ9XrBd`BEA=81*kLEG}K=fmK`ihoReN&JoYs`!SOjT;24?=W$cSR@vU=6NyFO;@;7 zoF|&+#W){TI40JK=D9J>cQK6n=Kg3Kvw?(<;IW#y;Ve=ds;W-M=7mpJw#l>QS*eb3N>u<=~Va>aie%P zS!h}2`80Tm!dHkliMNX17XL$hLVQYmPJBUpU3^>ID}Epj&v(nu7Y`CAh=+)WiP#JIRZJV{(5o+6s(*2up};Y-CU#V?8Gc{bABr0}icW8yCHC*seRE&uyiYvvn;(D=9JXJhXG|$7~zeVBO#P5ja zc{ltID*Qw7$D(=e4gaqc{;l|y_>O3vcf{iQ-f-D#pZmajCdm zJW*UNo-A$>PZQ1aag=|a!q9~XCv=J`F!{e{B668DN9i2oErd~S~P=D9t{FN8CEhqd;Q?`rxK-RHULk%#{F-=+_#M$a_lMl46n;iDp94VruM~b)d|&*BXk(3G`^Jjn z#Y4oy#d2|;c&u0@k^cqBu>QAy$ahVuKhLyTo;3kJv9>AYLMVLHv?<|w>StP*R)I?>b@ z?P*bXC5gg1#kJyk(bOO3`xV|wqJ7)M?c&Aawc-x(dhsUlR`GW6UJ`nGKzvwyOxz{z z7GET%;r@xZM|?$mSA1XGCw?UI%kAdAv6x4qUkb!A;y7`dI72KG=ZN#gqs1B${Z%J6 zkr*c};&O7RWt}LlBw=Tr;#v~@vtH~Wsef@Z3Hv)k+)Ba@w~5=yarhjWcsU8Xyjr}L zME~s&uP32@^E?&2m0{@jcJWRU`uVQ-{Y-?>zCXgTU9Eh+fcD%)q8%l?KhN=!1)|=c zMH<%Ed_M#AH1}IkzXy5W67@Qg_xDhrTF78Mw(>p@$~T`^XTPxD=4*VS%sPdQ9YeOU zPn_>(JY-z0^VgE7&%+8EdqTa8eIWh&jEC@IwhQ4YBW8@F|a)Ck85BBbWPe}GL`WWne0tc3s z@@4^JU?m6qRUIRxlfU6)e%=iBX#DM~R`qsma!t~WS--I(7;MLzKGxtT$^-fLk6F)O zxR*p&y;Z_r-^MGzgSl4swr@b9XuQ6py&pfhy=tHzVn6MH?Tdw>XmP#gF~^1f7sJsU z6Y-bn@UZ}Mq^ILK9*4qVYWu`=Wk{1=?monM2c}VT%)nnvW7a|w!am_rcTX`3VWy#D zdChP^c{30=8gbs?$!kPJP~I-cV}8n`4m^3A;Sb7NdjNU;NEej%EaZ(r9OY52C+{}+ zgYvkZY(<=Rc=fvl5kYycLmqWSc~}yBc`v~ql*jLd--|f!@Z|j*5kYxlE=$V8a^TCe zAuK5GWypKp6Q*n-aEYdaa{?@+YEW0{_>ER=_rq% zg9_H~eaPGH2~#=-`MIf}yvqai!>vVMp7-7%&+gAaK^Iei4zGUarOA6ZAg=&vz53mk zR=+H)#e>PaCr#eF0eQGJ;>&w8O&&i7vdgQS(lPkQGrYj%6Wl#W4u-YY0?Yd{{h3%MARYUF$D?WKD$DSl6e>iAm+qmoaPHoDK! zki;CGyuE4itRK63Sjsyb&TDT7I%OWH%^VXF*xOE40N^>g+_ZH6aW_NeRk%O%<6;IT5GSZIPSUU_iZbCe&2R0zv?mg&KYyu z^ikDAU$hRHeDIhmO2WCavg+wLyS?ne*WW!q^S#XMhu>S6QB$?On&5_sgPJDKIwKcJHNg>)c ziF(PquA=_At&>o%rjDYqpMCtjg`uqJ&U?0X*o%i8{P=sPXOtQF#YnNO?3dQIedpvo zx_8miZTq%@jk6xz+m^p=-&uLv_MKf;Sv?D_w60-&tcea3O^CnSdrDQG)$c#c}McMPOIrU!NOy9@;^4d5beLk%EdG)$IvABB3;%)n$&C6e# zgC5UXd{}kGxgg_hIPw%=c9@4Nf*eQeQZp0y^IEgoJya;?2Kv-*mP zt%zOv+_U?37oRm|Yw=n8YAm#}=@Hmd)?vBZ2;Z3;pz?vd8x> zYTmZ*F|cv=<9pjiZQJ*F*|vR8G_mKY-vwf_|I5|?`yO;9dc9A1=S$u;UtZp%ZTrrJ z#Pgb7c#ZwN@4=Ayn`+np+vghXX?<=@#%Qk`h0*?O@kMt&{YJ*@r{Bng3&Um2wy&}d z-}3BnX|{06bB*tA&2sGl*0A;2eY;k=))0PgVc4~Xg|vojT0@PQ4fYyactW=D1Z?4n zy=|jq3o92?A6}htE3IMrgmKf4dNJdhkH1%(vAoEgm!}y!3Gp@eZ(fV}%f5;!GrnQp z=30hNcnU8ZBcGfp>TPh>NG2isgh&+S@8JW)Q z*sO=X&ohlhE151c@^$QwGqRi_-cienlw$*%nd$H?`Z)J8R=3a=oC%G|pMm6|H&Jw` zte^#c=N$ZrWS)V)nM-nWkuS`rRaW>N)Y%T3H^YPv!#*+;E<&l9;hD@7<~K~k;X-_` zFB0ab(XzsPiClKL34e!#`T5hF@FT;~(l9@3IV?OACFX{oM9Se|zKtg@{2$l|j0o4F zl#yY69xy-5r>_O!E3oK~3b&vlqr;n#w=jGO{*DP>jHVZb$Dk==!(T++gTnl@^SJQ& zC~JI}Pgo~}`FyT8d^hSjG0e{xPYUNl{^amZD1S=$73>_QhWU)DGhB+8uJBiocUO2X z(mxsIJ=CYdm!Ne&4zEHhc83>2=F?%m1LT=VH&V{9BM+dWGwnz{N-nV@{5VCa9Vx_? zr_7GLi5|Gzj{FiE_bcqk;}Cb19a)QWSKE;jP{bGP2;Up^MLTjD)On2^xefZc){gMy zFJFR8)ayDs@*l|lWjoS~l<(V-Ol1Fy9odb@zuFOg{QLtuauy=@*%7|nV|hm8RzyCK z5t#>-ydH|IMtk1~MQ(ty-V8;)gnVy>B4M0+I}~{cDgP9TEJ5U-LlM4%=ABUFX>`oH zp-4Hj{$41;FZ$GFM!JD|*bOo?WJbOMnT?r|&1geYX51{2~(JD@b09MEFVKUq&KBpox2PA~&H*-_MCuz)0@PiJXnd`*R|3 zWVn8Kx3!pIMxvw_0MN@U+u z7B!9k*i=!rxix(QHj$FBO_4y8HEvksONJ?iF2PXj4XqcGYcd9 z1k%>R$Z(`Qt1xmJ&Mn*#Sr1J_cSQJ>h>9H%zHFdsN8|)(BDN#47|N>N5&0=Pb6rjEI`r_XP+@w`MKvPyJOpKC(K8G^oJ|iuE6wT6 zgPy;jbiNfos}Bv#q-QIX;Lvjk3Jue96LTX~)~%?aO^*%Z&7g-Lu4Xnhy+N#xvkC0?%~A7kl9e)^NTY;!fvLJC9RJ-nvf9dE9n|j;Ml_I8WHQ zw4cloC%_(@AGznYjW~m)?{Y)iNAQz}&X4V3Ea>79L!c~Yw>^wS-;QthBhq==4zW}y z29u2QtetlfYHW)8saM>E(7y9CyO^!Z9Pu`~zLy^8PJQ365nDAVrEDH0BAP0r{`nYk{$PaPat{B0J=655TU1|JI z2oYBP8^~Z+1!FEjE9_Vxrl1H~wI^rfaJ#~zjCppv0{a}rj{x9Q^bC}R|K=FIp}m8V z&D<8n5Oo~fs2!}v_!Jg(uhOT(v%rO^m7#x-{oOY6N#loVskk4Oo-17LGI7k;us^9)MblZbP~aki$(A z(PK!#kHy}fl7e-JvjJAo^D6!&C17UMo3+c@ zY8~{ZPFn@fP)mDkzf+je-Z2%U-tCkIg$GrttbR@D-m*-##K{Z2r?WL?JRdKvd zUE`k0*o?SN#8Ex>n7F2lfO_nOR?%rV&CYs3r&F8mcii8Dr?WP*drrkiq)_gu=;#Mj z2D`+_k8HM1v&K!PhKHPrJ{ZcY=&=|>voW0P$C3)HLQZ?fBfbJ3vlmi<%@`+qG5;t| zA4uP|36WPK;zGD0#F;u@fNXw|>aORlq7s~@g1+IM&ZI#MASt@D$~u?|yb|Y;70PRp z4pBLN_1E5*tlZ0{a`#}haC>*7UCGM5fMid?xkGNF-OApbmWi!6oIAQc>-O0SL@Z^b z>D^wpcdtdnm5el_tItizx1&A^SJa@ktw5>92(6+`i25q(+h?M@9z<->=W*sXoVg_B z40@#KQi-`;XEwRQj0#}U*Xy)ZFpZNzNwUqZMSlPlyKOG9tJr2PkT#ra(IxgWws{32 z>KSP)y2M^fi~bHGZh>>#T;{eJmrfSHxawN;EVs>kBPl;^;afDn+HwGkUgw_jEt>k+ zZsI(Bm;rAuOj`8Ub@~7n&F{C+c+BZREt+Nc=5;`e{xQtj9+6aF6?947>hmu+595+x9HQo(}P&_J#KANEPDK#SljIT{OM|s zsoPf(Il-(U_s#1;E%*)D*>Dpcg$Vn;8g}g|a9xc1HM87z!pTT?9l}?`6`KX*0W&N8 z7-3$878?tH&`e)Lke1(KEvioy_7TA!A_7a>xG=jzklS9}R&}BW13zHG{)ZF}>Q0_swt%W1(Jk%^>ij|XdETWKVv=z!dGUuqA1v$02 zz{=Da=*P*lL%GN1@n)%}Y^>rYmRQt8cdnZn_K^~S>f=6KN)$?iJqM5F2-sE=F@~EvtA!Y6yiEkR`I#0> ze`he8>z`pVFD2Z}ZG^cnu$Jzh+>7Cev@L!w*nA+twpw?=%gqf7itnT^&(xrmpiK7! zePi7dgjcn=U$u-3Y)I+M!3jFUD%(j?rfn@Jh9WDY$y_*GCNJFSRh%b~#vB;gI(CCR zL%Nb$305GO0mIop;_&et$!(EsEn^mt-oc9F+2m0GFFJUJP(bNQ`FbVkx9F$79dcZvG9)1_7^s4F7P zff45qx^Bc!l~;lf%TKZk-$WNIs9(2&O?}INQ!_#5$PF%BW=F2kgJnf?s2_? z6^Ao{!)@aKjxq55t)eN6#L(!ABeyC!QfG0wa#t0~gGIVBiRhnd=da zIfb~%c$u9~P7v1`?{b0?5t|ge91(*auHd*Q z7)_&8t`5*J;Yw{yN{uI_9&mN)MMkQIbOkIUxR5aVdXQ4+Cm)8x>O{DDIN<8kk0i`R zx`Nxhnt8(5u~?nF{tc{7595q0pX%E0;KmR0Ju%04TL@P{O~gXDR1-cCF&S`-_l||~ zup}OP%wKnHqt}b)gw3PMg&)r?Q}9@*fR}HN!s+=wjl4QEE@VwWWi#x*+L9YKf2b_yRpBkqra=Ow4--RPd|Rrymwt55ZfdYd3D_Ds5liwYjteAINWCUy6^w^>&r^c6E34wfB{Fl_&c82RhenEbaGx z{kyMpO-Dzfy>~7{RO!0z zj`ahbU8T6IzLp>9|G!*~zAb&hDy&&s8tv^ISl7L=a$|4TOkWq9`+JQ_T#YpKZaf(Z z?<;NYY41IydZ0Veg0`$_T0hX2h)3tu&-MBUjr|{#{%>0Vs#V(Fv+n=Zs;%qp>u>Mw zz*jc{#_`|WGyk^kdV1GwYVYr&9pfo;0wXHHkB;IIk!2-1yH>XktnW|sZ|UjkD_P4) z2ZN{+pQJ$mdqa%d1i!bku{#0%BMw8{mEi_)pTY!jCXB}ys|MDs@1MD@`&iB;ZaNi@ z1QEnJw&j?KE%Y*OB0Kqx9Uf8aI1|H5oN-~>DVjBY;sj^h1jh-N=I1*_;k;7EndB7B zWJH-W6iMuf&d`}98F;J=zbEWNBP_oF;&Pp=a;KmX8A_b2uwCLzob5o$#F@_IWAN+< z@iX&z!pRPY3X7fL;m`@TlNXv=>|_^*k8vikh;nDrILBVdB&$oDJSHwF3D-M?@GV^7 zj4E*oXFA!F!bdryjG&37rfNu@U1B60I}y^HNk>6KX(=id%C?<7drOgPSzA> zT+}I;$kw58`OY|_G1E>bJliRU*zv_qc?tChwc1Wri8FbUlQn~F9F2;w9mU}joq6F< zj_oWC4HP@5juN3$OIR-oUm3P%Ipx!hpEag%ATM+Z6*r&i zs#px)vBirs@F9YLO0LKV7*lBp+DL0Ep6nEjPq8Ma_!!z#@px*g^jO!R(0MQ@d^{l_ z@LNWpr{hm;PzM= zYD`ldeDKVfUE-P&?WU-d)|6)kE&8m$K|Nf<8YROjfngnC20;@C!4d5ER(AXXx8s+w z;}^IczktdyRyDfbHLE4gP{^JjOz ziw!4N>cm?7vitfjtGc-<5sSwYmGKo#EscqqXdQ!%asNbZ!?I{yZB?Sau`1?AR+U$| z$rABcLscwZ+px$#CrQ!PmYP^YOKoMerM9slQ5~(Vi&a@&39kKJy}f?&`0|R@>O|wR zSiHKfvCWTejx{tl#uHxYRneBHf37mxkYGfjwIR9;a-$V>F{^VOzB}8WSl`vXrhl!~ zTp3F=#_AK5^;L;@bJTo&w<%t`EZUN6#NwvdBDTVp>lIcRt*f&(boKSMujxvW6sxRE zG|iqrC*g?-7GqA%T2P*7YOScNt@NduVwxLk6Ag_miK=drWb zbamtE$86RT_?(tkE)`SPSh*xn74|{AwPF7jLz3TOn$D_$)vLRbJ;?5;kKxb68{)1r8^D&|S@lC;%U*Lrbl0xH1HbD+CFQ2*K{n0>seEgFxRK5B}`V0|r?`&Iwu znkd>|Qy;BNcwg?XUf12e-fyMsou;rPwj$9SYcZuJ&$l$UCYqt7hCxONb4Baov1rwb zL}OE|!OxW(VO6o(hT5c3Wlq&)iK?Zrr<#_*?aH%dGjI~K`vUi+MLZ*Guz$N7Hm`~SWJJI~$g?6daTy`1t$TS8A;Q+-I;q{330kF(KR zA5~jZyI{`TnG0&>EnMJVVGA1Xmf@=6Nt0O1uySu0HWbBcGhspnI&jo)leeDOuVqrl z8g*yV*Clpmh2;g~D+9d->u%%j+gep#HUV8sO+ir+8dY_Qc&pKS*}m3x0M=-$1eZ=O z_gjD!mlsS!H7Tj68eia_w9R8k4Mwx-ijtDX^~+vgf?lbjYFbT6c|mn)NLR2m^XKfX zVoPb>Ff|^t9-GipvvvH=D`Y0wzpGXI)uQHeph6;{mat zYV73k>=KvGoVTRb*Q`^6F31exhYCI!z9Ex8M|RR*JYphqgHDj3fu9Ly9M zeat}Qsr56N>6=#UjaOb*X};8w*ii<%)3OC~8n!i=W<;bx>HlY3` zP1_1Fkk%Z6DNQkE3>8Up9WTLb^ESs!;H2?FD`nM$vEB?26Qu&bYS>zfq?e7aESEA2 z8ir(~R>@wz(PY!l%km2JX6SFqP$&}$eJg{lixm>nvhkBA=;YQ*OIcY}NkI)KfbM|aaEt^m?x!SJ+s$XVo32Phg0u8|=V#Q-i9MzJ;@rXe0&GMD{jMaeO+e$6u zRbye7%-gIbwgOd8uEreE?}iF0(a5HjVf@1q%QK^FLN#VkWrbzz*Anyul2BST&TCp_ zXvR|$IviQc3>}JvPSW6SR*B35-~Qk{xyE!io-N++S6DHjq-?CMIe|gV3u+6l5Hszn z;*uH}BD}LwIgnDUF{FP=T%@AKVwDsqED6pDGFsN;s)9ltLOgYTi!UlDw3AGKrf<5= z#Cbjj0CeG|-X;#cSU{jJFk^^aJlLZ1BSNdIM8lg>Q9cQ&@GQZk8&ec18LpEP(^XhL zj*Yc=YGHA4QJ{Zo+=H2dNtmoQHlez@&|jz9{2p5{etdy9b4(~qju4)qX2>2}JfRo^ zUqXE=FE1X8eS_-BW2y_Q%GhAb(SQ20J;{Tz30%sSqsG@vLT+J%!&(GiW%Kk~d(fMp zvJ{mi#-XD<$6Q-nNdsMQI7>){DaPP$OR&Wike^Y%czg}%x7U{VT-tFb&y$P!6! z^1!Z5pCf7sde-D!9;^?z>oEqMV)D2kxsup?ZJO$-Eq5}yu*ynVan@9pO~uqzr}<`=#|!LrFIB~3QRPgHdg%=f5RxDDRHQj0iwDT)yGc(a&Me21ryg-W*;;#IBUg3jmJ`Yvfojw+~!e=#fDjY zp()9rYZrLIm7UEdyImGoE(B-h!HtfTtyyvsgWjZqD&`7m6ES2%JcKAtpi*uWuqd`x8Uh@r#tdgG&{wKEsj_Q@N7&A258%tj-s zT{d9;uwf81)Ge7m3wY$bg)e` zsCjF9>9c~Z4I{pMY1M9An>}+p9b;=p!p)fAe3%bS_}lri$TN*8c|$KS-!k*jP3<# z$vQLhm$$(QUc%nIOj&~kVY)ru!AP9!c~gg^4j^IN9gl(^Q!&-E-wuSPA52_T`$<48 zu^H;6&&<#5;DMb0ovS2FGXpgbox6{HT~$$9hCL-@_5|EZ3#|6NdTcYzY<$T6 zvEHbgKXX~l>;(-qvyN}5wZo>jc(ONCg3BkHk*w}q@>M&4Oz%j0LeD`G37=S0p$IPV*s z4EKhF$vMki9y>d_BC-Uj!)N+X^%J>~P2#grBhy1I7m!rQ0F@!o16G@lA@o)o^hgdgRFYVQ5w zj|ggTqCM$J_OOQgM+Bb%N(`SN;dgpLSlj#~g0qR?Gn4Ge^aJBp1fLK}4BsZno;FG0 zvy#GRNqBxM+Zf=m$^x%1Zhnym#KQnYy()kDUywTq#^j6Y&7fqfb_DyZ@0jq9-E`a*?N%Buq ze-!6hV+3eO@V5_Lkl;ss3qBRzy&=?nj-7kRlD$U8P~8I#t~-Jgk(AHv1jl51zd>h! zK|P7OtKaJ zDZ5;3lnxW5iBtqn{)z^Z0;~j*A8Sc%Q$mvL#u}%%OB0`*2%b7B@xeEHD!3gdqe}B3 z<~!m{|$|v?S-=F9C0eXIaMMNdn zl_^##PF9?)c(mfNil-``rMOy=`N?>0P`p)-pVS;)RNrDqgO5wc=*QEsEsM;B|jd{Hx+4iaQlwRD50WUByon zzgGM~(Fq&9X^O2BvlTllc314DI8SVoieD-6BSNf~e6fufSIkgsr}8v1syrxTXBfueu{;P<%*LPk5D{HagpNjif1UEr$|m6+HslU9~Ey@ zyhHJR#YYvNRs5UcyNaJF{zH)i7WFq%Y@^sovAf~`#eEbHQY=-RsCcL%KWa_A^AwjT zo}#!yakU~pHOBB)DPE^|t0F%p$MZWBpHh5D@lC~#6u(yF_vUzA3~yx;TPY4ylLq5 z{FCCJ6>m|zQ*oQ(gNlzSKCSqo;%ka;D}Jc>x#G8qKPt-ievytiK03zqWGHr2>_sfa znpXWIiDN^d1Jyr{Sb{GjsDC;UA7VU4{l^h|AlRy;tlR`Gbn^@@K{d{yyXBJ_Pp?1+9B zUk;!@orrX1Dz;O3zWRG8_Eq^l>KBepTz8Pl$EmzRagxessDF;)Tq5E>OYu_0+ZA6> z{7JEAy0LR85nC_?>K{);{1X+YsGQ%_r~F98V~Du!T*b|b+ll={p{Iyhm`AGrBOoaZDj%-?5sC*8aou#qlN2u|LeEAb>d1}izl#XH z_bP5z`IG8@M)5_Jzoq{76hBt^ck2H^@fVdh&oufo6x$LJ|9*-y6;D&Vf(Sb|6VvcL zfAv2=gq{2-BJl~8zoh=ZDZZ)lPt^Z~;58)zk5XKqSg&}Z;;D)& z6wgy!t9Xgx6^egQyiV~(#oHC{R@|=mkm6H{&nmvE_;*EQmGraeiuiP)___Pb{+GM7 z#IA~c6bC34E0!r%Do#>7OtD7sB*oJdS16vRc%kAt#f^$rD_*B~qvD;4_b5J~_^{$T ziXSL`q4_+tq)!qO5lz-=Th4@529_`uRz4>XY>?P}aA= zpH(jFTlmwto&&a3BpVC;T@<@2_E8+5SgKgASgm-7;t`6o6z3|=SL7Zt0Ls8bX zkatvn7sVcmeH6*7$LnQX3*=|UIX)kvc!c6C#kq>Io<%rW&jOdJoL?m8_3IQbQ@m1f zlcKC+5l+^zz}r>MFNt#;ep&GiMOn8(F6&m{=PLhB@drhR>oc5>DW)rCD)OV`Jl|h& znBu;Q2P%$HlK$Oo~(Gf;!4F;ifa`wQRKJLssA>`dlY583i-q8e_T=4t&qQ{{?`@XQv6Wy zQ$>Deo%+)ivlMd__fqVp*iUhg;=YReD~?etQRElfslQfnzT&Zp%M?#iJWFw<;suIp z6=i)3eScKHtZOmvx}SdF!-|h9KCAem;_HfUDa!g5*M+#=1jZFxD7I0|RwRiD!{sZ= z`WN%61Ly}9DV8c$D9XAR=lPX%hFhq(RPhAG(-oI1@(bz=f4Sl{iq|S`QM^@=Usq@N zrxagQd{yyn#rGAzQ2a)bUt;I=8H(A89ToExWj&5?{Qf!TYlVsjD^5_HtT;_^hT z1&Z~G=PRyJBsmK8Z&3WB;%3F06t^n=Me#nxhZJQUkKga9|0BgO6=l7S-#@9JWUP!= z*6Y9)>Tjc%t=L&HUyD#zfk>46;DuBzbI~3d`R&H#a9&hQFhLgzg7H6kvEVik1MuNY@?X1h-MWE_cZs@ z89s-8*p){_ed$d^`x#6`JH{HkL)G0v3|G0xg~D7+Fcx^F?K5`8k?g(s7K=*5sA zDDgpmF8#nfBI4<;DDfjOru-7G*nxP5(+?DTINs9_98JXhuSjtq#}TCKL?Yssejf3k zsQrobJBaU2wkM8L2t&Pj%tz>J$$Wx7u@{qYu^0Np4*10mTr-LB!9SG<{VUbKiimVw zul_AW#J5xZ&k>>g3-y0PMEo)jW_&tN96^MC6cP4>1};8+e#6XJz=nE*b@msYWp4-# zNcp2!(g(y1tJ#*Hq z`r4(&IwQf?F@xTj^}Knnf{Ko;pE)0a3aZ8roY~M& zKX=xW2B_WRgHIlzTFSj(UNoG40tcq{a^&ML!(nPGM{+ox3 zpvlX@z5~r!`UVQ_IMnoOeej!M=onu)Tu@&F{LjJJ!|E%AAgJ#R=wm-bee6%IzN7Iw zsIL^BHz2cz)psNWL47$`#P^1b`e>Kcw*tR|`g$W{iy*Uy)psTYL4BhG`p}(u`naYK z>YE3BsnUC0lD<0Vv*}F_=zBRy-)I!{-ypMxweNWdg7$5MK9(iZi>}hMkN47p_VHd_ zs`UPxq;F>+y_o@hy_59KfWB1e<+BYz`*sD=i)|dwzRDzh!#OU{U_ESl%aimCo^HlX zrZ)?Y;aJX#5sqlv#~f59s{>;1H}BQ&NjUCZ>`6H8S>V5SFy8l>P(AFq$MGYWFUydQ z!PviKI{2K2O~>Do^o_&GVYU-MIIHioq;RKnLcM1N)x(DS2tR`HZaM}OwFt*}bKz{f z|4h>N#~z{34An)j`o2%nHv$juRN_4KasSQg%Y@DL8i+$~PZN&6dDwH@y9wI268cu- zJoV+lS$*8YvDZKxnnHb;E7-%H`VwE8f;N(lD_?Bnwt_ORj1 z)rQYI zQW6=yG0hd0?`X*gVgF8B-R4q;iIlXxw3(b~zB)@Jv6AfdX*Yz|KJj5_PVD#X*1MbI zn~c7eTfVqw5#n0~Uh`;v?r!3HBlk2fzSg4E#@B3hTk+f2UW2AsNjt;{uJppp_0GD` zS`as1XJSm>vgn@BHrTl>b8D#kN{KgqQAF(JmC=&s>*Je3Ya{F97cn(yTQW5~S=d9} z&&L&M`LBK0?$XyjY`-+VHdfL?!nIgExN~&%h|XE-BdgP}EfikejGIGioz=~LAG@f< zrq@1<52e1TcV2d9>u!(i3Jrc3E~DH2GltD*DO~7~jfQOWs2Rgm;tX(iMh3Ln=^o$= z`0(X6-QIrRzcMp$Wt(nazaNtHoK1fCd}nP;Ybqe~xaKD@qgp4?8KcNGNgkx#wb0gvS90Z6&W1HcN z4#`8fiVm!p&~O8Kx=31#_pu^r@lRcV}H|;M_e)(N8PD;xX674e_i(n*b#T%MPz9%2_Kue zui$TUHw)cg3-<>kKHWVSbBUJj?~vvU_d3|n%6$#7XSyr%$<^8+8xKjlOL0|O_c5e6 z%RL#-7`AiyfIzl;Jg#l;{tkb0+#!gogUbiuI=U?|zIJjCM3`K64dUwJ_Cn_F4xRJnqhe&L`aaVe^y1{tb$CawUUeJ&J4s#rofoMW9$e9AyfM^)84U6zjiWcml;b zyFO5?Z-&*NSTBZ2pjc0b9iUiWfJ_C&`hCbBP^{kpouF91A9jIaeJw5r#roT@4;1SM zLklR@--8eo>!T1YDAo^bD-`RC(IJ9j{YnTyv3?wcpjhvN`~<~%38DqX`ti696zkJ) z4ixL$d;-OKKL|mwz5&sKV!a530gCnSk)xnkAB0Q*#rjqNDAsr30#K|kf=*DZpNwJ# z#rlhg78L6(x(mhnTL=k?_0cdF6zgYp6^iwt$QMwoAB}+@6ze2g2E}?lE(gVWEh-Tx z)-OPOpjfZL1)x|TfN}uE`XZPFiuE!W2#R$+QwEClTI3Qa*5{)Nf@1w`)CEwiZ$*5d zSf7cK1I2nSgrHbofy+U$z7PcliuHp4pjbZ|=>x_3kuVn&>(?UZL9xCOj$8|fnxnKBoh?tSD`M0V*MKA1Sr-IhGn2w{}`zS#ri530gClIk*%OuFG1QtvA%x{ z&7oJEHx59tJ{iV?V*Mr<0gCm{5CjzKeUJuFtQSEGDArFx7Jy>C7lMFdy#sOy6zhM1 zouF8c=OeS)$7^5&DAs!;c2KMrA?HD{J_*GEiuJuwTS2j22?If~ehU%}iuKQs6QEdM zg`5Dz`Z}Z*6zl(h7Er8DM^1oZ{a#!LiuE1P0*du>a5*T}??ZlqV*Nej3n&Vm%xA zAr$MplOq)Ce}^KWSf7WkPAJyvkv&4OJ{U2cjxCimK0YKA>lH9XDAxG^q)@D1hA4z$ zeKR5ziuE5+4nnb>h4wBK>&L=mp;%vuqzlFRRmeM`SbqkW3&nafR8pZ>9}LYxv3>>W z0cSsHd!c}YV%3GO ziuFf%HA1Cb1Pg^?{Snl5p;&hjDX$APTZccSSicJX=Iii>be%2w<3}swA7lM^zbtw# z@3G!hnm;Hy%agu(d7doo!t4jHrE}{ z6Ayy8U!tjYamOI8z1%4XpXc)7?0k1Ss#jNc9~obthlcJh9}?@~{uP>gxs;u^Jsej!8?J-#ZA+03oZ5$lc?R4maBT;{DhMlCDgOk)A1LgJCg7}f+EDl?1Uo1k zZ-jj*{1k!@;j(Mk5Y{@ADGaXx_cYUYk<*q|hu1{2pGQu?Kg{^k+DB1GoOPzoh1b-z zAIGF$V*T@S5IocwNjM4yYa&A(21D4_q#D;C(UCQCTqb$V3_x{w&AfJG<8255qLDQr z7nl}V6D6ic*6{XYo6}KPB+<5I(i1wJ4YjD6Z3|Efk9D+NMne}m6*PP} z1l%KOy9OR-k;#`sAgHGBIQ)UIKeK>uDlCO-KM*zFskiBB$bt2eEc*Y-Ok3&Np{eIx{Y zQ!AI_SSZF6{f4w|9l@J47r4h!*o31me!gQrUdPcj)?X)?H+ zRV1WUCK^6I%9;~iMo14IN5~8>C1jy?q3@WE4#)Y#t3+(U&W5AV>T{*ye^S6qKMm%c z1eYsK_)}>Me06}2U*vAb=<9qsjOlw6{vB{xR5Q_-Np@k{iB|2k=}!6V3ZC*}?JKeJ zVZ>ai08b5P&E>-woL`w(pQ@%M)Xax2a;5lpN_*x*7JT3$R~q?FDf~m>p90reYW>ba zUW?Y;g*O15XJmi~ukkB!6j6JXm<{O&o5!guG4fCH7#SErWpwWFl7cvqf%Qy^WY!&$ zfhR+JJe*|AF@DD2`d3-KR(jXh%k|?is^?1YwsJ7D;woHwIb7~e%od!L;NMOe zAJTNrk*xR#em=vITZK5Bb9ze$fcZc(xX#aEByr9uWv^B$GOwZ+04#ucxn;Wab5Tu<*B&E%`IIM<{26 zN*~k9(NTtSMyv1*D@3oEQ>wymtuP(JN)__yPsY9`(+$Z2eVHk#@S4UgExcx`tpva* zNYVjmrpHDP&2g>M$1JP~UePW>G|mPNcBW`2NG)H1>^Kw76yt;mES~G(-$a=dV}%q7 zA5nRXGAXx;K`aW`DUYC-!mF5UiYH_WuTsl0Y6`D%ge_XB2bI%JJxK4|n*-WJEz3+( zmepF8Q%zYOq6JlH%5tiB`A!C>Z(VX&H>PQjNnTk_MGxDkEaw?vLRp?+WYLCDuq@YU z$m3AzqqTspQq|-z<=~RW+pl8CMlrDXy zDZ;2JLJYRd+&o+x57o_Aa~Eac$aN}Tx|T{oS3Fg#b~p~1qr2f{N5 z@zS}2;CT{3=-hqbS%KO{=MIO54{X!9J>Yp38A|8o;vV*Hc+k;xM|?{3Xd)&0|2Q6W z(zOfoxbUDyon(&oHXe64LN($JZ<~VSJS%~Fyj_5+9M7j&w)C>LVa}bCY0h&jg*ge- zJY2CeTD1C>&Zd zM=lQhF+r*VL1qNb%1;xd+6DmwYjOxQZ5l)9376U!6KJ9h1Y_6>BpfD4RUk-R!g+X1 zkm^8?MoF@lVCqP#2<7r~GGPXsF_6Dbf&*78;VigFXo-6Tf5-$lG#S4V4x@4+fgzBF zMtNa^R0V=mCa8eN1gQ=Lp814HL!BgkuJL2$M$CFzBNa zj~VbHOgd4+q~mA8F#|q?$s}qRbd-t540sVHi>P5RkR={7;6<1mqJ}}!Glw<41YVNR z5*Y?%Xae|uBSuW%RjDhS3B(t6y+Dl{n+a4E4Ai)>nMx=1n-k;I(V0L}zZnRroCioa zOc1Hx8f16%TZ7C=PyvrIxiV;S3M23#x5%ZxvuHet%aB1jHtGiJ`A62F3cTBvJ z$VCY8tBGVFB(faP=rFn@p}lbuu@PuaB-C)S*k$8rTtNaEz(Al)#$P#pCCQjzB_z4Z zOR~}9mB(~w;}~MW9j9wjL3pKaQ3#zi)Ga#NLRy$8)-gpU?|9h zdLBH#xmmHSQNC6F&-8<0+5KYa-C)~%+SV4f9gBe7)Hd+uCfIg|u?@`7iSnI|Z3dMz zl8A>PVmZ(@IF{2tmfkg%UFxTNXrhi!o6x;l$$?o?En^wOVh(tJGggQm5;(VE-gg7d zF=?OMkny&tH*gtnZy=~Zi+Td3U?b_Pm5tiueoL6x7di$;y5@l>cu;I0JS{;^IzVuc zphH?_5I3JND%KNXkW72nNBsFQqDgMsScV&!G)h>9Gu*ueK{nlLU<|aou}sFYx5g5w z9mvRgA;Ljo1u-#VLo9swD4q`ER%C!M_Y04N*{i)^TSj_VS<{Eax=6X^_LIyJD(_*5 z`F)Ycxa%okg&r&w9|}5*^e>GxzdZ5cJI%$=i$$vAm?zjL&0B20np;_4JAUS3ut`?e z&aSU*IAm@^UGePMm7wGpS9^T*l3D(zY0bBMeSTGboEH5-%_6dE*3O&%MOUhmygLAYb7n*P<{E)l8ZOUP$jl>4_iXwVwhO zE>=9TKKIDuYvi4RJ&B*+{KkjunYH!)2bsl+Un63*IiKp=&O^Nf@l(lfRep&# zDUI?Ca&ReD4e@wXZ9Kc-VXa*-yZ-n^4ImU)v}D%2xwA-?Rs5GoT)i6OeY)SWD=MXOfWzdsrEFza zwWz+fX1?@vY+2~)yxa~_z9e!R>u1dkk*hU7_;qb7ORNO{zoBSlzRj#%9PHTxWn_D} z--@_3RiBgci{xJYX@ZfgP#Io*R=k97?%P63Bz{fNw$QVuq7%01PNIh0-FO(tHGf1D z0v-|oknH*xFq@|$p8|~nsS;CLmq5^AljWKBFS5&~h(bS#&w@!{d$Lg^643fxN7BGr zY{mi3Es_V;1hR_8WDGW3>uFPYnb@BU-n zwHuwu!y&)nsdz7u|hWsLh)$-mYD0KblV324xsqZv} z>=mxhSM>!zqH+QvC41Pgmp?|vipB7 z|F2i|?D&^7V+dBg-<%^jsjoC6HK~G=nQsE@Mda=lu4B#b;DX-PWWSe9pd_=WZ4aMF z53Dl`l0gP0BVG|oRq;u%lGt@IIovbW;1qoXM)To=M>b{^^Cs6muQ0ZYbPAWEm}dL! z+%m&?DNaEvoZ6C9WVSGH&v}J|b1U}sm|7JtGhgSIF3sO}_$`=+$CMXL7*|tRS`4z; zBz7@d%88`JHb>0-=QpGv_P1E(E?BgrA-K`vXGztDlyq_V~;sn}aUvE7w4ysL2 zfWh4%v!RkAke$D9w~+J0gsGQQb2Gz8rs+(f%B#BCV0~k2F^QgETaPimcJ`dQpxL$r zY-&>wA^V$DH4AELu`FA(a4{wf3l}ss7Y7TYY?S(&Vmi^lK37exR=*mO#?5S4QeW#e zYR`r}V@nR$g{48m%zBiEwQRw{1z4lkE?b1{wEz#Ut_c1cWXYBhIXSS%B6sV#C{2+$SKO$)~V#Rj=xyoWWrDir@XwVv<9=~s^TILHy46z)60Et zBL2UWa@nu#O>b%KIURF~yu-2(T-r5-DfaFc{O_gkB{@5Py(29h6V}>}Th~B@IbkC@9XcStt{%R0F=ZtPOHS2U^C0HXT9TOzBwpVL6vPTrw-dr-(FqdK}6P#UJs_S39kCjNRD1@QR zMtlrt(L8MC)JP_#oP!0rPFsCjo8Z*8spWl@)EgqfV)AzRbQ2KL#Cag?dmd{jqZ>tFiJOZ0|s2QARsR*EEAG@ zVcXVuLh`Kt|0cri6#2=4hZ8Ey4GU$YX-uS@;wtU^cXtQO?;!sz)@{F5ryxlFZ&7lm zNREtDa@)hdH@SP(ZhwNwUX~wF;|+y`cA0{bJ4MuiHtucV?jduxZ9{f67gp#LQJ8U< zWY$TGZI70_QJ3X!mIrqQ{-dnj+B}oC{Tp$3Yp|vl9U5Ra9i`1LkZBkD1G?R8OX`gh zZk8nTLZ@Q(uC1?MSdT$!j=%QMk=4fQ5h5p&5^E?HAcn60Sv=lN)T+Q@%x^fH{+NNp z(rN1ml7i4%N3|w4iT^#CZ?95U%TDy-V!KW)#xk{19*)3{MO7_69$34yc5$$xSAxa7 zx~dR+t7@}tYOD=5RmqiMPe{V89+{y0cSyif6ol!Ey^8!Fqz6wCx$VA&c%7F`qGU(v zX@-5UqfvwK6EVR&5AuJUAw2c$EY;);8zN>0EvZu#ZgGASvwptp=zD2Oc^}SZK|$5n z$--TpB9Ep2#)CkO`tQUEa^e#cc$`I7cd{0#M3;i8kZ+7XDN}~=-;Ve@9S@QQdB5}E zw+EkNFUZL9nX|`als05!`R@+mJfCp~Pxo2T<&m?&cs(X#^b%5x;F}=+!RP1s9;`k1 zT)py%kICpgk)M`s6y82t&ujSH{g`BK?J*gZM+>#~SovEee-q>3bNXI9c@+{*&<@5? zkdbZ}#>Zp~o|2KCU+KJ~I z^JyoZZ_J;ac)l@TcH;T$pcm=&-j5Rbuk%~;wKD&Rgz%1e;E06s13uUp*|@>6%DGCdgI z{_s;|u1^mgm301GJe(FCZohK&=MQmqeH-9_nJf8EF^K55r@QECH1f|-^I6h=TpQU-<}FTjMPTn^cWYyBZj!ug zPI-OO9U!~$5O`+R(`U~mUBbzYZ%=T?!d_rc`%ftcLnU6Hq`bKCqeh-RdM@dTM0NgR zqiJLOFp1atdn-*}>xW6a*31hV-?j3L-}8y1pSMXVwN|05IE?$x7kiP|5J?v{ekfde zo910Zp*+-WB45uVvMmrtDV8WsP~?k@&C!*xx7w5Ii!>bH#bfxRi9PTKN0(mw5|@$V zRH%6$N+Iuux50r7KZZEK57&kMLHGcJo)^1^n0My73^Q$&ubp#z=Xc`yDkc#h)eywz zGeTj!#+OgTU<*|u-$!wO#WKZ8MZV}qJx3_cRy45%pf7DEw6LU#I??6mM6&M{&F2 zBZ~aiGxfZvD16NDzpMUF6u(v!zABt|!sa^RtAbznn1R_U7d~eAg^wB7PvyeL48QO( z14pY|_?Y1rK4zfsF$0B<87O?rK;dHs9;??0PZj*aQw0=0X5jgHUig^d7d~d-RVwF4 zm6&efV+P)?{(BW4RD4|VSw-PvM))_?|AC_LF+={H`h|}fe&J&VwuqScgtrR*4(iWS z6h3Cig^w91e9S=MtpW-kGf?=Lfx^cO6h3C4@G%30j~OWZRY2jd0tz29@C=Pl_?Y1r zK4zfsF$4MSOy&zeszekXE1>XL0fmnlc)y+(K4$oZj~V!a%7u>^e&MwO^7Bd5_m$%J zik!?)9#<4TX847V8OU$E^Stme1BH(nI7H>b#|*#lF$0B<87O?rK;dHs3Li6YmR=|P zR`3fSGf?=Lfx>SE6h3C4@G%30j~OU@%)l#EkMLZ8kq{l8PZL~*0ywTd?@-mUn6 z;uDH5DE?jX1H~^De^89zjZoT=t|ns!acA4R~6q>d|&ZX#jh2= zSNugWhR?S#--K5R*joKLirtBrWDQgQK}1Zp3KfM{3fE0i|5U}piIC4#|9r)IBJ^FP z=Qk4ZX__0=e>V~Oh4&fwfXa8OTzH=$e_7@4s$6)VA^%L}!v75a&w4)6+}P7rv76#B z#X`kuBJ8PCyk6yZ5Haa|Nd3{(TYc^oS*s)<5O#=tN(l=?BGYhiR)B;mHPjvc%90HFB;+QR{4D@e_Z`L6`xo6 zo9cg8@gtRgr~V%le^Gf0OwegZE5$4#(wV3J?uva>zPI{EDjukEel(qWCMZ^`yhi=A z73);qp#EiwC#(E?BJ%4>#jjNUPa;0b$WQvxzV<}K*GVx?<^9w@NO8Ez4^n@jVkr@> zjtG5=iO7>P)PFt^`qwC~Q~8zZzeaJh%D1ZjPQ`mw{)qaYP!wKk#P_D2|AL5kV_1L@ zhY@l9KqA@#zl2Z!R3hw|t~gWAFV^#?5YgA3ul`Gk2){w`N|j%){w<1IReqoPA5eTm z<2>N~OhkOgDW0Tqet(Yg^AuOBe7*XG-x}wyR{4!8zeVv5 zl|Q8Tg5tZ1-zY}VH_)y&iusEDiO@e-ac`9u5n=x{#rcY7Dqf;^z2g0fFDSNdW8!P4 z*hR6cVn0QGnU8jjP#mRLtXQVV?=Ujl6vZ0F*^2WN7bzaEc(UTzisvd~dMV=yhBZMH zry#m=!G4N^6lGrkc(~$B#X7}#if0g^{A|VZ71t>KN%1scW8SczQ}`8{I#gw93K%4Izd|6%GUtpvj# zsmQMs(|?NMa>a8LWu1;pzLtLA7R6f??^fKVDC=~DdqVxsDZZrmrlPFZ5sqIarrw_v zBV3QdA6MiDis|1=v8Q5RMSiQ8=f^0PDUMgvvHln^(2sAJ0{Bd8kn#C9*QFs4^S*t zEK}q+ka_(~Md5>nU)IyW(DDI^w>to1;=NY)a%Eu_mx)^ePj+oaUp(uRM@XLA_$nOJl zygOZSrJ}5ZA?Nph*}wl$@z07kDe_yuJTL2ApsaU+FQ}Z~1?G8K=K^J&3;bT?!s`q_ zzOpIdgx4AVF6tLvXZZW5pWpGNzOjnrZJ=M)x4g%zeVwO#k&=sRTREv{C-{iZz&32GkyzSGw?f=|DY)ATl^N@W+1=n%J_u08OU$j z(!Zag@H4|N>s;VOl}}cjt$36oK=?y3{D~g!Q!{_^h$zqAM3nnrBI@M`BI@~QBKomX zBKqq}BKmzEv4%AkpZo8`(L~r$q?pHg1AA^K+Hyy{$3VvTZX_bUhltQG{L#?A7s68CbRzVLz1U0_ zdl6Rh0e*=WVWu-a_-7EIU&b@|7txP+R_XcGM8vm2{Tqph_c`^yL`3}GsDBp`c4V=? zX8c6v^S{C8%Et~<-9J0N5wod08SlUEWNzl943%^T#oky6+$Iy&(g3S0bq8;A*-Q3B zeTutYsnq*7u6C>3zely(U`^e!N)>a{*^ziBO0G3jtp6*iT=f%|{x=iZE`tY#VL9^g z7gZPc)y>3#P~X&med!vGcDBRy zL4D=$Y=qn%RyW9)679+aD`)c^_)t4+( z%;8j^hqbRJN#AJ!eOMBC`YuS)R|f`-7dkrsq8AUo3GlyV0aJ$*l*8=%quc3-Nps$iY^swi+ zehJ$50rag#80y0%o<81pwAWBY8pmji-}bQQIwa{^c8rQhviaOc^$k`9%X(n$ z%RqWiAKmbza9zq%bE+03*;j{fdDbZCVZ1yJNV4xf*k{w*4d<$42sauRvOmsOeVIV!F~r^xorpb8#9DyA?A;VS20uAL&B;Z$8zKX)lU#sFSb zk5hGMYEIQ5gNKY5JUkD_uXCzSnlILPoT^WSuq)6lv~>lzIYYz1&j}YD7O8XkMR)e- z*W&4lFG7n$Yr~zx*VUCc*OGBFzUA;;(I1^sgTipOmGV$tnsSj^eMT49N}(+a+A>62 z#TTd5Bd(#1b%IDtbR)!KXYFU8PX<$46S{-8hGA>Z-^|u9Z0-5m*xEI;^~^1y3&V9S zN}RrJcV_f$xwA*#w#)_QK-X|*=h`}9r;TX3H_mb{{Q7;KcP{+=eW%pOQ|3d0?sm}K z3cA~g?usu)9}E5YjrHHB`bYmu`opk26SnvK57-{=+YY*0LHBQHJL>b9TO8E8<|P^Z zTA=1dx3M0B7_76iiFMWHH|yCq?+5Ex+Saxu%}Y8+sjx;1vuuLC*3j2XYI3r^e*M0K zd^B`^g)%gC_+Qc8vtOFn8TvBnIGfV8Il}vEZ2do_hv^Nv!CP}n+LnatLOpu)73=Dk zZ;4zSx+ra107MspGe~w&%YQ@4tR6`z}*=oX$P8Ja$(W41W&# z&ItO=*s$>0_*&#vyxG&EZ^Gjbn2R?Kr zM=ySNM)RjPjY;1Y=@IS`x+t*tRNe|+KTVo}yO0rAN*^<{alwVg8`*Kwj_4$`$N=B9pEioM9pOm;I)czo1d=N1{h!`K# z7$4lVAvCz;LB#kVVtf!WHUpD*XxlEdCATE6SLn-CvEI_dJhv-!-^{wJ>fWx~v1`?R zJD_I=^z4A1x92{$EAzgYbFZ4a1J}FjckJ4L^BZyg>b$*X?2>*d*iP+lTlOvLdi86$ zvrWGkdX&=^XLfDb)ma-IlGyv<#v!C%qyI}QY3=oRhO7ImEiFnSo5R;So1Xa4DT)YV zca#j>+CHd19s1d`vZu@J+E{xk-K+<=qT$Rfm`_}XaxG@gMx_6+X$WHG*0Z;S*S09Z z=GTQC>tYvOg<9`+Z{EGlT^(mQCF$FmA!V^mj@U;AaT}g-m@7hkcYlS?O&%?Z)L+19dK?Aqw2uorU({avX0iY?KL zqIJ%NJylC&ZK597wWQNsMn{Vo(M?D}H);xB6q7a_XHML;XzaJf{5auWAy@F^XDl{i~j}lR_N}FS$veY;-kuI-WyZbX#ci{;hJdC zF#H*uwE(|kJ1{3U9Otod83SO9%Ln;F?n*2x9Jd}TnXucIR=HPU)ev=iW6d0MuYnn^ zy9(>sxXTAS)7%FUS2On@gm3QhQNtGQIxHg6-Jyu9rQ08|WVo4w$;5i?AU^a&2FBLz z;RA4^((Q?Kwsps26EVwu3d^^4Za-vAw!5SsZoj)v?TbxAx1ui}k@~N$xS{1vg}jq{ zKk_%%ojVj;=PnoJd$}**Y@T~6V$65@AeOG~d(hU+eG!?_-6bV?4|h5CJ?FTY`;g!w7Jk_rkgx9Osjv6CCHC!v~J@OOP+%IPcaS_a-9o{c_0q7$1zH0>}CDhyfhu z?;}2NoPP+_;5g@#kl;99is}H4^B=Kr0>^n9XaUE09pbBs#?JwGA@`L zjl0+$0LS@!lr1>UhoFGKaqgn7fa81{l!4>C7dC*wan5Im!Et^l;seJy*_6R?z7I+f z9Ovth6W};+g}BQhyfhu6-XvH&VNJ<;5dH=tqC0GXCeo|asCyO0*>=@P{iOk=jJ>(&Tl{( zz;Qko^#vT~_u+DIoZp8a;5eUvgn{F{C$xa$d^(~9$N6?B1IPKF(XW8x{8p4ZIL_xgyZ~UcHumA3kpU! z&SxQk!g0P3osV#wZ$i!p$9YFcgyZ~=$YbF+=M$*SdHHAfAspwqXbr+~J~j`%D^FdB zRAlhSol*3${P8WSl5m_aM;PHacTmS3M zcfZKk4=2EOzL+L`8R4br=OV%)_nXWe-ZkF^ule3y)6fgo{1CYu!GwGLE&LF>PBs3o ztbeai#sjF(TioqV<|HJ!)!aED_d&-f%{&@8=I(GZo_x`;rrxi3nOpnWe3x z%;eTlrm%IC>RU${eH+8vo>u6@Q0Lu0Aa_IVC&&-SjiEro?sPQohlwi zU)IaL8skiFcPDz|KJJrwWNyC!4ZUBe?T3iWIVMf2w9^AtXT5`jLDEYqXuJK93C@_b z7Mx}AD1~!2j6`N-XCs$zYV-?82imP1+1(JeQi$Z zqOv>1MtC6vtKiy?K`uFC)1*?8E&V)L>6BXkyqrNSu`=Vo9~W?F&e?+c=^Si?FGKJ= zTn85OX#5CQ;*WE9S{FW>+Oa*Po$66sJQZEUQ;X8lJDvpzGP($VrX%^C!KS^YuCp@{ zMC+ZMDlpDhc8hj4{Jki-Z-?TtEI&_5sAfYgdNY$JStd_@hIkj8$&+>_r9)AC{ozcW zWE){E1iS@e@}#{HUJAj5a3)VW*gRNd@}#5nH<&!>Wc<8Q@gSVZlUyVGI|Q%7NuG44 zv8XX2XHZ&~ePDAJ<_WsH(9Z}WdBY$P79R7a3-hKOPPc_a9*w~tFOL>U9yJ8>C`2Z2 zKd)Xy-|T!G_v#O_4taGFYF+jUcDEnLhp?&)gmTXIOHrYb{VC3ga zv{q-kpDj`#8`fsnY}szobr^JVl5eu*0V6ygf)x}>wmfKr+aS1;LdljLM#$HCK7ljY z@^DhNJYupXADt1OS2Ef1s0lO@g1zA+TO>!AIOpYfm-(#ioOQ{mi)X^T z2a!aaDrC%jxGI~j8IycTyokbsARse(_D6joywnKiKrn+sG4%IF$ajL4!-=(L{))A* zY7Oe1vozVNf6}VQ*?5=6_n`qdK;>q}C8i!1-`4ktQ=rY+p!w6SFuo6xTysRk$5%Z}W zJ;o--+@p<+d92Cro1p8@j6}N0Qj-CEkLei-#hfxD{1JkGQ1}*y*@KNR4^=rA&g9=X zn}5c<%}tq?REJ?L`!lDXZ>@BZ8y=vwf9ffx#(sb-DMnNUaM|fyA?zP7Wj=8pdnAQ7 z_kwVM5ncend2psr8f5#Vy7p1l!@<@+FBhXj=yqdh_+$*pNo@^7Gp0Sypi6eLjd}ls zQCVVCcD$5EWl5uNA1|XZS<={Z;$>{?SgW&YfA4zZ5+X-Wb1HJsr0aWk997%~OSiz8 zQux6we+$BoAmHrRjLbi~cC_iXkp=LJ@n_~DCqfTs0@iROz&v6i<`GVnGa440%!>b( zZviS8EXYCgFc!S!meB&f`qd3C`)d3__~}f{1h`T-lZo$H3+A=I8_m{v-})D|zYvoi z=L73+$YmF8GnI22%y2Mo-~FzRj|io>XYulex^RVkA!d6SCXxtR#V-^}%u|i9H-z2cB<9!%Sp_s6g0*lGbDQ17JOQJs)7_7`T3j^wVezn&R}+YX?dnIu}NrP62iyfZ&i3H{#GL}67V#}J?HJ1H(Z<~37GFC;O*G{ zOaN~>w1R8@1bd-(V`|paP&-anod0u+}dvp)MnQ`IKn2t=-O*TCi%Q#rFX+~~u#-*jUW;&K@ zAz7Dn-JAzyHyblY!?-MIHa8pXW(d7GHc@)}uH9jpbA<^zk71?VT@fqchCmNl$zN$K z2(`PS2g07_Cx58qUnlGWndF~llK%^A|DK7GXitk(G5JF>u>OL}UWdL5N{*)RC&^`#fpPvz?9^_*1 zHyN>?$q2rHxEao5#QrA#--6(86iPi9rG4|YYh#%n$J z$(}d$z)N{k^`K8*nESRd7pr)i4{t{U_2BKO)`LP$DR*k%lNnetVrMi^51ugwgxbwz zQ@+Q~2oAK)hJH|C(tJ;JKUVWzXx!c4vYYLV^Y=!jKPZQwl)~0rP;N8AVU2j^ynLKaSRJB2QC+5Y3PWi3_-_x*#HDw>&J`&LCn=ixEbcxMy0#q zi=sW@vVUfYT@;md+6)K|rEneQ5zfU%cp(Ia2^7r8$3v;9fX0`MlKDl6lfw z9An!D=gYbmC`v zoXNb?jBp?XeJSLZM4Z!&uo{92I4Q+tO=X^zBJ%J?Hs*Q0Ri^Z2=UD^h8MVuxvVn0) z>CH2xcNqk~r%+07o+-V*LU1pflpb$RV^D2ejS%wyoWs*ZUUN64*BUj{l-^`hdLKg9 z+l)j?Z;C0X&KN@5!lLhuG&t7Go^QEV(DGD=cU&j{fKjrZ>=f4 zZM0Sj>L62kS0bv*XoD2#Xp?z6AoweV(k2Ux@M8$xr%>AD7$eNYawr|nw8=svv~BW= zrZTf}oBaJgu(rQ%ttr)!m=+sr`y0)BBdQ^Ard0czQau!cDHKYn_BW+^Dg-CONvU4n zlp!e9^I4zT`7xVPeV;K)kJrwW>K~zNBO{Sg%{B%23IxwlC~dO65vD_-3uj6-$CTrsUC}l=7fA}O{t!Y9?cYB$du|4i0V+X>pusmwdRiI4IHkbk&4Z$c1Tla#J%Z#uV0^R{I z74UK+JQsqq;qqice}xgEUoic|M(dAC4a-Lokhzum=f&T4a^6c9hY45~5lLXG&m{Df>S_a2bVC_M=SMKM%oEa8mZOMkW~& zDEo5|$m#FLY|4H+W0tb-ACa<;aed9juo;j{+4qH@C!Cc1!sJL;_HSdB?R4<9o3bB? zHI^y+4yNoULdiI4m$L6*%6>Tnr^1=C@03{fCz;q%m;ENJP@P}GUf*rX{ujn7W&cZ9 z`h%@deiLJr{vc$s_!S6VpinA=V}!pz@FRsXqX-*ecdR7y=%hc07@^l6M6KWS2j?`( z9n<`px+{geTe1&Q@sXbjQzwqca9~pLQCLQxGMG>dXG-Ryu=EFuAUK*rsS_WCr9Zd| zf(>v|C)On!6sQxdcg`z*%%)Df$e5*0yb_i=@eFi5$w;J5yb_lF;2#it%}CfE{2@6K z)`^qRFFSYp+DA!$P|^>IWPH0jEaO`qrvEu`rcT@)mi}NS1k>QmYVw}2j#{Qa*wVO8 zAiAqKdTjEeGnL^RMkkeFlc@|Fp!HHlC*^*v$=mxOxQ9Y1_svGgCp6!pQ1bRVBW!_+ z9)~j>!SzOHJA!)}Wkc%1hqaX)g)a83HHE&QzqR&aqj@l*>JMkK{$f+;hd{swgN$Jp zn?gSaf-~Wy&>u}UBv9zzA`WM{AG0a+#~HH}`f^j~cS6@zMk0m2+!Xrj5WK=jSm-Y% zN5VqCa}c!8^|cR{Lf;>YM^or?!&2yRtXO}ccIgP_nnEvya5S7L^kWhW{hd^W-nD%M z(H&xBHI1?@ zDqWsF@`BqW{bDepjWJ>(qBaJ%38u7-P3hY>?}Sa*a~W1r8V;s398780rnDueq;EK0 zhgvQvZG|#5rT2y-rPl%L=vG`yOX09POG2GQMrTMn?H{_yw3GFVW zZ?kDUVT|BYnI@%AIMSD!GJV3)GW`KPkaLd-+rY4r(t8}~G0lbdn6Rcy?{TzDA7`1a z_fu-h^m{L*>rG0pMS`yIQo7!xbQc6)cqzTirc6_Mx%Hbe{dqTK+NT4ISZR#tftF$n zUKvd3N}JNFIlEeB!XCk}lG0_tlr9UVbeT=*FD%n3eo9T5z6}+oOsANXj?BaJ=y0Y? zrIgG$~2|ZtlyOB?ozt%zA&QD7}08oO=)2;rG+-7{1&D&%!DmvSV`%y zU`mGtQ##D1^llDk?UGaaBvhD`wlgVx3<=uiC91tm#0*nWbF6<(`y*IKIyiRcGIwaG zQN^8u4&LrWVe7gM>%j|HeIv#S=SMHCkziUQn%3Uyao+h_+MB~?-TO#dzn1FTNBXj_ zrKb0hUifQMdHY_Dkk0d7D;*8HoDDZa*iQ!5=cSSM!gfh#xc<`fylD4h`^%GjFR6D< ze@W!aUK-I`Bsb2+X&i7Zb7s33@G7kqOSek{?IWG;cGErw%x6z@iv-LZW|MbIAbGb0 zl6Q+H@2?Iny4XvesjzEsxk=u|lDrd;v;|)BE=f$@rHRS=y_Y-~8%nCDjg!~=P&Sz} z#Q^7Snl0%&GmySBP5OH0q8o4)n~-0630xdV;Nn067i$8)OvhD|y#$)_<3nvGfs-YH zFCcM`dkH)wF@aMP6FALFAj|Jp6FBf|EcwFSoxN^A=*WeLIE&9eLo$$(&>$w7hnX9E zf&g6}hbSLAOP%4myaZ1PevF~#9e9qxkE7sZV$fp0q-6;9XXVK(Xl60;Ftf96d*k}6 zAX<%US5esw@NC78o8V+?AP34qgV>IE7=!rMOP6$%>hX+gKnkfHy|p*wZ(8D8} z1#p8G!h;b!7ejyOAQOFX4TB`{UJDPCq)}J|blDrChj8_FxGrqApWw#_aFUAhMyY@n z-V@_t>^Oy54uz;K{4L=I9|e!KV_Hf(c<+ygvEu=17ywZ*uI7BO%YN`2jUPwCi5*9# zvV)Jy@W_C3Hnc}~-=!}^7vQ4vsAXSxZo`i)^c2DK9)7$9m&?_SE9%|b)=#Xv(Bk0H=Mk)?F;ADk9LUg(cz0T=%qo(M9TF8+z* z4!I2W(#7A$nf5S*F8(Gw>yTi&`0EJP&;oZL;NmaiObJ%mbn$24xd$_Uy7*HFwq`hX zA>rbW;!HD`NEd$qp2Lt}y7>JFmWCQc7yk>+{0y~p@mq0bAEc2kz7?JvRCv1h&G6*4 zM*IE$*gF&Os*3afpUdSYtT8MqDr!JPR7e6Mq5^WsLIT;y0%+B1NCHGcz$75xiX!e6 zD=My_qT;?QShc9AxMN*Pt+iOSb*tLNrB&FXez zgo2e%`ZW+Xqs-)!z7b(2qcG%?el;{#p!LcpeKmw^^lAB|UkpKZVag}{A%vNLq{t_I z6*N~x@ys1Q>E}Y|j)o$i^py}!>4#^g@JW9VVU9sD$tV3RXykH8KIttG+TdS4=?xI} zM~dZ>-iR$X}y&0O?u~@3aCw(zA>YXGwH>95gO&Jm?pY$&woZABrhT)U`6@-g1 zos~~|1T7?vv?$3Lwm}-pIFyOG-E=~o)BEe2psXKUNmE%RIvIIL)EJd$B{bXy}e+PM%OAjQXq*4GRU=b>7?Dn*kC(qPM-+l8s_;#Bl1fe@2fOh)&aJ!fJIyi`<_|i!fI;fbAXQ$FE)jHcXCgjboLtW}8o?8OhP&t`x`g@~H};4~R11)R%2%i(2`j8_DoB;U4RY~ZGl*YUINjmE88A>-U6rfvE_#VBP*~zPP&roOzdEAI zlI5tC7+dfag(WypeVrzdu8^v*B+)2Sfg7UA3=vjXYS!vh3M3s;SVA312ZiMZxmccR z_k#F^6>+2vq#v67OInucE_#VBP*~z91%`UWe|5M&{AfA)N>x-+JyIFr#5T8l-zvXQ4SHxKp|tX8=-u2dtwE?B^}bq(R~D%fTM0tIC-sn(FUfi z^$kped*E=#nF>A5gy#_RU<5)O0!${Q?Fb}F36Y##$H`LODg<(Va}CQkPD$`B=`e=L zeV|l1kuTc7w6(qgFDDVq3oxa}N0QUU8NXI2!7xZ^|Kbdnz~Q!~|KSGrV{|{@K>vTW zFpW-Gf+ibrrUx1>gg(l7nm~MncS6@wrRgbo%yB(cX-~%4UM2)`^uL7x@Kh=ptm#GvHQPrCGXcm5)JNt$ptK1hSW zO+!+ljd6VlPF7!!#eeG<3>j7gV#yu07SKAu7!f zl|~3}X61);LsXd|s*DicEZ+~2G9RPh2O0Ez>Tj|-iF^ox`EWyoO4qC!;)veefq zff$h~t7**5qHFA5N$`&akHSnoexQQ?UpWbOF!78bw`ih*9{9L@&@KVj(=^jl@-)Qt zRB3whhY{bR(OLF|tD1Mn7d`Jto`>qzJ}nF0#4E-vGemMy+$jpYb@M`0nIV$Xm8Q&A z2_zxL$P7sxKUN-!;m68zo52rpX&gg&{@C->D~oW6^JCBR2jJx4>BpWYX9_j)3-t0< zazVMCIymR`bbFp4Q&|gJo7d+M`R!i3IZwrHh6p?BxMz_{fg7UA43V7LA8rWHD}@!Z zDl!P4q?L)V^Qx>cVj3!tFgRffWP%@lk>i%`|L~RIkCpjjWuirzhjdA_+y75`W?-c; zMc8hBF(wvLrsv1~eX89wd-^0O6T+ zUlxp!G7Vn3yCDQRMDq2G>#5T8lzc|*;#v|&{K2@ph?6>yJpHu|e#N^Rz;&JILM=(k zR~=4<7da-X|LzsDe6{u3pN_rI-Q-ROd#ZtMkmKW7hXE#YF3WU+SBRR z`H?A(97QfXJ0i+eum0$G#9hAYk4}%cOPQD-nbhcZAbR;O^)u1>KvajV*Y3iJ6zuxe z?Y1Mm_V;6ZcMH-kN2xbCw7YH}y1jIy|G&`QZ$V>^IvcuTw2gd|fnR=bH*-XAuE@^L zX{pVb-MTQRwWTgc|0?BzwuZX4hWebkmZb~Z79g+cK|kQFEetZe#PDil#-aiOTqx(t{;wwJq~=@=B|Us}cvh%n_40#m#k1 zi|QN9NVA(3)YUfSw9c)C-ivZn!i_AaZNY-3y1BKD&8<0e>gp0=cVuqjpv0)$Q6m#0 zbH#B497i-SXl@wMP&=z}#K_$2gGPut8|r{6r_qf*XMSxRlKj7(jMk;CW=Z^j#V;)b znf(u1|F_#6l9f}tu<^e!Y3vgJ%_WC^&{o@A*U*ah{3Xzj(X-v(qOHRO(y5!@+Sr;v zm&l$gGqgl~!|d8cO>K#`r3)Kc;fBi$^sD;D<~9fzSI|rnbqnUtU(lRDmB0-XYS*kQ zVx}34Wv-J>CwT6L6|h;08k^ciG&WCAqjfCe#1Jort=FAMEY>fUkrs(X_Ks!b#$stX zN{XeG$Hu_5TUKm>)1_-98=6tkpJqn7c8Nu!51kO{ih$8aPL0I6_s5s>1BwA@(Z`^P zrA>(SN{ft(MaIW6qf5YHUGM`th)PHQS2y}dTAx^KP+D#*lGd*aex1kgaVCUVzkdD2 zP2KC!DB-JnNWTqO4`=?6WTsv_v5M4Gd8uXr-7X3zfAKwK(7i6UD z^h(FGJzbkKC7=-lYrE4nTzi%w}eRdgA_qRT|eQkGl5Z)RF=__Yh| zjbO|<@G_{ssz;NvH}_BM-aU|JN-7xB7@ zMf@cb`8>B0@#g7Q42Oj)=eCMR}q>|l(Kv9uu=wW3Qg zQtk&~RID2uyQd9CWBYqgtF*RB<4-GtPW{fyz#Z-y4 z)8#Mqd}Luj&B_WLQg3%XB@L)Qcir{5K-y}%dBlhpz1dFr_0kH{ChX#8GM07-3q=Cl zUnW-J-gVvEPxjeX zvbUgNcaZEay+oxd?Um`eVYZX(b*`tRWZ$9Ot<(MkVUCZ6IX)HU_@;71$Ltg9hPOlS z73(%QHehfpa!4#=kZRUy(z2?1unMIEAbD=}WlIkY&Nx2xt)`l-bPI1$Yh3pZ((}u1 z!SwvSgY?|)TTPLkCsU+nyC1Th^7)ySo=qs5_R8lI-)f5VEbks(K9{-f9hA>&>A~{( zs)O|0>RU~bp2t(9XPfJu+?9F_iFF&u5#UNIIrpG>xLqmL0Pt>y3Hl-!@#q6apt%m> zjC@FcIn^w|sb*MKY#*7Gqr0U=yJtzQjN=()Y^;A;#2R=Wm6=h$eh8fz%Ro2SOa6D; zHt%vSmzVD-!2C`*AE5iChP7zJ}tTCkoTLAz+bU_N!t zwlgxG-cz+4T_ZnG!E9Ale~5y4S6SM%e{@C6%slGr(e85b6z!80+cSD%)}TRqqkwaw zX9T?MnHGJndt~_FoSeO<9-#E62lO#fN5AiCnvO-Ehuc3bw-?~{o#pmY_effHEb?e9 zwkIaggU?U@~m?-A>T!4z|&ZsTJ+qp8I9j_o`LG8$r9zpOw?o_14`bdK1b!u_KZ z?wF{Cp4l(z9qxX83io?mcirmT3xNKyJmdlw#=+^{JyElEa2>Y>O``vJ6y&0;*nnt{ zEDRfiVlj0k8=U?cP?g1=u?)Ee!=+njQGD3NDvBMj+C6P5 zbFWUVklo4epKQ->!84|iR<7^JkgD^#Y9^-LQbN5j6lU%P|GDAGeqIF=U9hR{Na6ln z3im5^3U4`gr*MDTb(cQXE7}jeFFGH6Y7m6JS+T5Wn{=>c(u4-}>mOYoG0O|HYLxZv zX}dvN7V8oH8Tx8$SFF429ligANG!T@tOqV2FmD?eRqYe43faq=5{pa-=J8XN1}vUL zzje$A&^xyxhF;PBlCCBc;Jy%c%0{|cS(<~5_&<_Gn(+AFltzJ$93KDWnX1gxxH3qs zFX6H%EeDG^>WmTXmlf+K#o}HrZ40C^7X7AoB>Ix&_8sCIkd_h4niv}}Ft)o4FK!u) zvyzC?>4l3rwHDAL`sE2(Zh4&}wd4YKRX2jPk+Gm_wvO39`(G#bjI(tNabwaizG`cY(D>m@3Sg*mT#LVak(kuo?(F=M+ zCB0_R|(SP6(ACQF(ZhkhLNqO01Pmxz$Rg)+#%PTLfC@H9h zhnlitQys6&Pn4Bc!%I~`WpzQm7jQ~N!Q@0uSyfF%MY$*v6~!|PN)mVR=oNpOVUgs)}+X&+uH0;PEOWwZ&!A<0ZxUiPEaciAgnug)mZ8 zd{lu`x2Od-K-v;>Yg^}f;ghmfTqeoGrd8aujjq>jQg<2QuD#^&0lsztLL ztUVtzD$(X;PnShuJRg}VsIE3Ed{Rk4qN1`;)pu2M9sym)nSd70;{xN=%z5}Idzag`fQ zFt`L%Z6HxnTsGAUHKVw&I1#T<>B}oGD=Wy;jk2mHFAuHUFH|HoZ&n=(Rh5P=RUMP= z71L@8Y6=pCs2VSxig;yl^^u+^{iZZtb|f25m8Vc`rK-G2B`6;~NTtWDk;z`y^lC)M z&%lKv(JvEK<%NX_&w}=n7cWaxSH{b#N{g#i9F+y}{3FBKT~TQ~FHuz#N4BLGqQB)A zh54&4sX{-5CuvCNqfXO;<~dntBwn7%t6-?Q992_*j>JYFcRp%yU-QJ4+Jy@n>J#%C zmIjL&clf3^v^36M8d}uGNa4l9E)g$Lc}kR56d0|89d=S>@#LcFGE{6*Q!UIZnHrYC zctI7i=aesM%dc&#MYZJx6FRGoLuDYLZk0(RKX^<)A$M}TBo`M~7RFV{jhs|m?K!Ja zG`~1LIZ<9yT~Sk=m|k8|jWNUbz}_z-sf@Ix1sDMQAuPXOdND@KNi|h|ldGJGfhtix zy`ZwNqNrMJIoA}%i)FOZ@zIBjpeTj%no4}Zh*5}hPqp13LPp-k zW}HWB6OD_VL<0Bc+r}CrsOpe%4p9|W+^pJJRc%w-)P|+S&GijSyvA3JJNbTOI8pn< ze4vp9io+YU%rk-O!)>2M=xd@g3rdY81?9yl1|qcTJgHGpCe)_{F z8aPpxmRCwsmXoYk4yCnqUd6~MrdV32RbgnURT#H)tCqX!^y3Vv)2~|uPyCey zB?W=WfzeXpH8^*bRqJzABBAcKHZ~{bH_UHsFsc$ofq^}w-RNOQ+Jw>0WRB(yJi($1 zsR0?I^Wup-Ou2Brb5ESijT*9bj`Rs65zou3sf_3Gl<5_95vFf5;;4@5;?e^2Bd0Vz zGm&Qu2o>l%Rh4-t^mtx%@pON{(zSqD)8sN4tvs9N*&+FCCza&)Vy{^z6_?p`S^nsp zn2OYdPO987U7goZHYrAZl(FYSmyn!4^=ZDOyvompIZ46vt{9Wkc-~Z;@Jh?`Lz7UQ zUtmoxyc4_biySkW8k*;{%}r{%dfpW1_&S|3$dwl&spviaIlw=!jV@tUJ&u=klp{S%R@BPqN^D9Aa@4fR>r5!Djb?$mT#4VIO~(0yO1#SzbXPE~|ER1dD5%7WorAJy2@X z#-)KC*`<6^c85T^gxx#5k$d;&vme9_{VSjR7sT$bxOGIbj;=b{cU$(cR7p~b6ax2sha;0-Oo`GI%dum%-9AQ`JQCFqR$%!!K& zSsZEqioq)d^op8hx!^P_N#|p7ytFj#<--djZP}Y>ndb)A2NEzk_s}t&OhDj76R2n} zK6pWU57ZRfAFhyP6iu26c)rclu}8G3>(55a?J+FrQ%M!hK(%eyRjeJ7t}4QF%;7=O z(OBj*{qvAGE27W=8hdTI%`-Fdws{_G*~YV@Hus-nV)lG@_yFW zGJP4*ifzweE8Jw*^<=-NNMA%7R+S^ogqbd_ZEb64K?Cwywd&mNC4j8tss30{R$hZS zl~`!HI&d z1I3N(&A>pUD@tclu4QFWp?GrABvl3?udBOtB*hg{#WID&U@ePsQ?aPad8Cd)mxpmZ z?6tya4U4_OffI6T(jQnqEX4}Rr1F_bMV(iIs}Ed4no~zCV`KeK&HUtwz?~t6ECL$K zB7W7%s#SvZ>&3=dq})viEcN-p+*vP9JQDs$@6y0)T5gL>z6J^J0dk?C7HGUCFWtsF zH>4cSIhJ!u;SDUhK2&lg6O(bVXjBSr#DokV@!ERbW{j27L~G-+2FE?^;z165n((4< zub-r;sI@&TD_6QxhQMqg#JjA6;nc1gBipanSiB+YD0{&2Cu}lc`Pz2R)+rjZF-ERf<*=&A=ToT>0laMg@6| zR`)(!7$*-=`aX^}r7pK*c~x$CsQYQ2oj^Ye5{sam%`b#!ob0+o!F zm&vfLMud@`i7@S`u+a{4dL%m$GN;!ONi#_rC8{clr8CG)8Mn|1>gwlWWXQ)ohsCur zNzgg>$`sM~&BYxff@e5Ry5==3Rg3(!SngM59b42KgNQ4yh?5no0;|2$>WpMJz}r17)6Ck6b$ujZ+Y{L zv#y*D!_T^YZ%`*1eX~VR{j45>CF{WST(=WlFt~?+#p>d`Vl^4TDqzyGK_GZwcual! z!|c6!5XmdTotJ_VqXBzkGHS4;p}q=tfE(J>Jjza`f59~)QG+|l(gwZqG#5v_yvkj7r?| zmAjf@O8~H%;+)MEAu~7JvqWoBi!8e0)!HytdlOYNimUUAbZY%(RFZ1>LoV-eXDTr{ zUR>tPZmOM=zyp;{iAJ0~+Zpn_yRtd~x~#EaRa4?mk)?0xNjv&iNXe*0N41wCxae4l z1(iTyd#6M1Z0W`A-N_s!cQV~j;gfxyUv!HMNsrVN?iWc0WqICE~+;0fFOhFOb@wcL>NwJsmFpQ-tUfz~FM3h_y9#|v&? z(aoR`>%Cb0PZXBKtAZD${uO1g(^z#KmUh2} z*n`wu-_+n$1cz^TY8;*-#2x7F_G~9)Av8Epx~)lCN+7ktQA4+DU1F+^gBQJ=NY&x= zt$leL7nrS-IZ!h}48TQ+;^~28SZzj9nLt%d_o6Un5z^!W?HNP2=g+(2Bxwpn5m-6$ ziomVXz)4@1fz+2;GL=d*t`~3>>;;$8kvHWC)Ha(tr4rl}IoQd?WZFMU2v@lQ_{^*rt)h#RL%j`Yc zpgFTCEH1%?aA3+UyBF2Io2sfje^a9#YW1*((^X}Q3$@Ob6q;E4jdL(jv=%%ex zq;^i~^R0H2o>N&<=2t6B1&0z{wK@blCq^-U(@#k0>*a!xG%Z(kvJf_{VG(XZEnK7; zA^VM_6mvK=J=UEaV@8NoEMCbTCcOcKn>To)$?B`HSko*sM7tn#&0&E6qg_5O*Np2p ztyI(GRHH&z(iqS$NyIO)OJ~z%XEu7Z`_ZjoDVs`M)>kZ=)znxg;TqfKER2aXhZgqWsy&R}+M8$FOPn$42JR-dR}FT*l2f8LoCTYq z*OhewR?$h04(JZfbxW@g_K4fPmL+K!axhh8` z?wOViF2dgfm1?a)mTh&hG2es|_X`PE(P-;i27pvP~0=2CRC&VJUzg!>a z?ynoToScF)Z*TNAN8k{H?)BEeWBfhWfiBM}P9U{dO-ULOOX8&!xS;d=1=_ILHaMS> z<+nDk`Mw20e7j$cEe0_MR2lo`lXS7sMfHN7c%ji>_KX%62bX z&4E=%ZO17S2A;P=;`Gi@-UY5%8ttBOQCj|7FxXpAbqTe;>fZWvHyG(M!t)Z69_$_P zs#T3VI176Yd8PS!<=RY-Sv$cPwQ*(1f2M)=cC^;Ne3Ct9=GJ3fdS;7AIw$GcHk0HR zf!WBDBg7Vdy{MvSNNG*Wl*+oq}UdTr$@M}T6WU~9*&STA-So8 zJ=Fd(dGb}7ao0;aqYNKx%-4hZ^ zla0~6{l>_=Td=sQ@g~%2O4eAXZe5vu${iJ02I>T%lcR>UDtn8+*0TC^roC%kcSEyR zCvyJw)_2U|7?)f5GL^uVRrisuU`e@87bbNZ9lM$em&N@Ds4!RccAraA(vwv`fZKLw zlvhsWQdgj3;l!gi7rHrcCgd1bnJ{P%7B zH>JybMXtO~Rp+r>l~?MvWww({giF=tO#9>h1NP+=!1|C^^m^$>O`B;n`-SP=UfTbY zwtMMBgVHzuRoN`p0}wu*(Q8HYEcE)~jI1dcy;A1gj_3cX9kcF+pnP<@C~c=*m}Mca z7-pDZ)7TgO9h+IOqYvp{UOi39$gS*=(JPLhnEH3@{%@t#jQ3=fpKdGA>f#y0=4ap) zpn-FYyk0z>(SJqktgb7gXTw*1#@L38{@!cCp;qUic*cM;(|lk5a$m69bVst8htWub zZW|RLW1hU)T#s#LIQb5D$@`>?0aH}oO?^jWX)3$&>T<7*}vzQ)FmD9y$V&oU>i zPkJfdxY@05*Zz^6BfCZiM0Shp9@!%@FtS&d!I5md@SQzc=-Gv#KfL1-R<< zw4Pg3UWscQQH;!e3|U5MId_cn++^hTk0^c(G3YU*g8 zqzv6dzX08pqG%aG|7J^&_%bZLeo?;;pK0kct^CQ^(LbX2ed}O+eSIaqMG-ovH_x=9 z-^J4JV&zYM?ZZE!7#V~1%#l*;?QZF%_xMK?BTX>;Kr248Cy2ehEdP7?#_%nQ(Jg2% z%hC_F^n+D=C7!Rr-Z%LY#San$?a7(SKcdc1OFz_C;#(9yS`Z9B%*x*|%l`qEf0;S> zM-;!u6SOznSK?dL$+q;_R{pXr|GAcb85R8_>Ws4VGTQh@6hC|wOplD#{t5sDXM_c-%E&Z{U{#Z+YoTWd`($BK=vn+kRrLVX2 zvn~B>OF!4r&$aZ&Tl(WIeUqhcvh>ZCzS+_*wDb!teT$`UvGi@0zRl7vw)BfF{Sr&R z#L_Rb^vf*$$(H_POMj}RKh@HoZs||A^k-Q5Gc5fIOTWU>ue9_lE&Vx`{v1nxo~1v} z(qCZdFHqzCah|UWyl?U)>Rf2~ztGZOWa%%m^cP$Di!J>nmi`h;f2pOv)Y4yW=`XkR zS6KQhEd5oM{whm2I|3H(UCfE&VN){uWDr zo29?a(%)g}@38cDS^B#y{XLfc9!r0prN7V8KVaz}u=EdE`iCt2CQHA`(*NAj|J>3) zV#$wL@-Hm;aZ7&ElAp5VXDsFMh{Z0X;o-nG}?iFDDS-CqMA0$GB%>Dk38r0m)o;2clc4Zpi{VZi@D=dOVN zy_{DA{cKVd9V_Ju)-yi~n_&emV7S{1coFmi~F_-S{UupIQ2y(#-r$az;VchlG*e zKa}`~;nUa2cUmp|#nij;7djg){cosu<1cc)xAc4CCvN=mp5jb`tPcrOOT8O^iF2l< zzm9r0{xWB)rT>_EH~tD|r*7K1+n#eE`|)Fou%$mCps#k;TKZ=L`svPBmVOX^57M_k z(?KGA{Pr{2%KaEMItt{Tk}s_H~@I#L{0* z{Q>aX*O}#Pvh=^AUYz?n_0Bhzeh;j#`uUsfOn|HpiT@bt55V`n&Rpj-OMeaZuKnYk z$1VLk)Vt|#a=P}?*4_Hs2eQQP+HZCWEPWmIuKk71*_Qrh>RtOS&U2RjL+Xd9^tU;^ zdk5p+7qVaei=C;KzJYqV^6u*_an7^!H&E}|U*~~}y&L`vr`ghqF8v*OFJ!e+hJbor|1XD0fxz#m;M%|8D~NOPrx%l!tsR#XrA2 zUg|8d^lJn9%bn*e{htH+E1ZGG1-^LAgY4VC%4xRrmr^e)DSe%5oK2Sg73!tf`#Ni# zuPl9^zOMa&N`IX*2C_aR{&MPb@x3o*4<}G|?cL~HN?BIw`Z_l|8!5Zxd5iNa$odd_ zUHX~%xy=~~Ss$V=3Fz-|=2`mH0sURhW=sFufc_rmTT8!3e>Z+NKleFfAnQZopF;g8 zeDCW#;51M!RPsa48J7Pw)E6oJCg%alZvHW!4F1Ggoin7(8Dczn>h5vnZc}rQgtv=A zd<1qxh%b8^k-zONxc4QsmGJFIzMa4$2&v74?v{oX?%qh5BhN=W>Gk}CrzNoAF*G9a z(SFedY@|p^l9iC63)o4W+(2TIi_W#uUeN`7w3FTriVkhce>+8J(FJ^@h$!GEJkze1 z_Hq>P(QZVv5*`r>rh^;>e58md;HSNa+RKq^gg)AhsNEc)VEp~Qsp=@`!yXlUt(y$v zsRgq~Cwc4mrDjQ6Zv&}yV@sWy@RALfP+meTv{&%10mDb?@Ew&$p!PzZkVBCLyrd|P zfS=T0TAZ68TK0x1Y+Q-Vwcu6Xc5I?C?6J8zx6RFCB#nn!E z7(PN$5U8=R{^F)0=q!OdxE8|~#HWnD;nY4@ou{~bV~t;qmQ)@_UT}JsRnAeYBstkjEfBGtv%>Y=(9_`bjDxD{P8H&{s$iS>eNrh@O&* zh>CWKDBz?0)TJyU_pzMhVsYJrMgwol7Z2_KaEx0AuAz{;hdi4_xTC z6r^f#;wRVo5eMPE{X!~eCbtyYy2ajBK>R}_dD3UCt zdZB>tJ?Y&HzAE&gUsr9UDb)*0eLH#j)w(FJ@OPqFM!f*Wi!CKkVPjQLAXv7U4la+bs(j%_EJN39}uI%@wekZaI*^k_r z+%W6nPLSO-^KKVnQ@2 z#Y4#>NHhiIK9!tC&LE}gB)n9Wu#sFqE+S7Nmy>6c7m}BdSCDJT8_Crm@^Nx2`7-$i`CIZm@?-KZz`{PG*ohlLN_p z$OFicPxt_d@yqDZWZYG~0Um{;8-y+{7KO+B3eoe}LCMlmZ>@yPfCi|0nkh0H7^!t;! zB61CR9eFExANdIR6!{YQD{=?Ro23 zktdPM$+O7|$xFy9$hG8+@BAm_DE6m`+)oJoVM64;Q1}G)-%+j=KIb?M<3wLF)3AR|;_pHB6C!;BgfHOyL-!Hn80rrvOXyxf&Y=4#Lge>c;bV@ohVptL;@d#p zLHA9RA0?ll`%9F6N&brN?^6CF`3c>>CA(#~@yLEaiLZ|k>DiO=Ao2hq(w8GdekamB zpDd-mlB}cq98&fVO8C{nmmFuE@Dazki}KHfi2oPl7P@bv{2KXdy1!5PL-JF)|AX>B z$td>uNqqgteaM4^h`)vMsltaH=R(R?2$7y^$m{8TC*^y|hv@z!G&t*9@tOVLuGUMqzC z8^{fGzn}6(@=>}!OZi3emvn!d^6$w%(p~mPN_<1Hz#!=xCA=5s3(BQJ#6OLkPWM@q zXOr{jej??Q$kXY*id-kW*KwYr{08|h`8oMdvPVDozZ2yxl=2ozd6U_6KaBDOGLP<6 zWUUZ(PN#f<@OHTLmVK9^e~Rv}lkbyX2w`tGEDT9H4dsX3EQiuzxCfCfzThdm>?$=YkiM&k+d(Tt< zE8+Ey^9Ra*5yJkLuYr`a$bE&dS3vzV;X21Tj&hR__7{?i=)Rot zS>$HY`uW8oUibFeTf93ezL4i#RC=K?5K3z3eQ!Muj@ zr9$|>g1naQw^F{7ypQg`p!_7cmF}-m-cJ6O?tdb`6C&Q7cL$N~q2xhioU9}h&P4Feh=jb$cO3vH09^Wm+AgH@-y;#A>tXbr<=|(WF9$< ztRokar;_IhPeOa8e4`NQyoJ1z?hjLbjC_*rFH?S%+)nrRD1SiyiSFMC5#R8=-1LqW zE_IyAl&ge@e+GFp-RDwnB2S?EDU_F!D}}Ik6ZQ8BPsBP7}6LH8Re-$LF= z_lGGzMm{M-JRed2rLYz6F3JLt-abOayEC~v-G@>>fXt!$;gpXc^M$ZiPyIsS3CIWK z^M$Z~5xJV~>nN`$Z=w4GlsA!&(fv8fFOjd({aqpA>pKWUe)bYBz_?BMP$A+UPfntH z8RbfH2Hoo@&mo)WzJ&70pDZe0`?>N7q{6`_;|Cs!o?%z_D8>FI-38g+L z?@aD4guTP4FBHzhdI;rOA;LG1$J2c=&5b^gT2he>8r+YEwQnHfn$5Ng} z&Y}B>Ld16yfG1Mfcg1k0%$<{Upk#kt^uFit=jm3cBAyZW1Ei&nbT^JQDX0hk{7&u0o_^ z4>F7H!zt&I2h%-HxqzG^guUabUo4#AIA>A5SP1))ws*EkwTd6e9ct%2R|@Sg)YmAcVa}vYGD7D4$B6N%xB=UqY^- z`+CY7$UEr%s1WgeLiuaqG+YM`1ChRdLd3r-IgswdC=Vw`(tSMTI9Vu!z1h^a2+Ofv zN%=w{>|ab?M)&I}-$dRfM7S-~Zxfa}&hIFHEQFoU$iLCu+23{VN_H0_U%Lqr{xHgg z!l`KIlxu~s*FYXm_r;W#k*Cr9e99M*tLeUu@_OfaL< zpq*3xUiciw`vYBe6CywTDGwm`r27aV!cV4LCCqc2S(KZFu-8JKNcS@-pG{ss_cfHS zCaerNcTV?;?E-YrTa+A2a|`|aT)rTcA^?;`IPBHWAA|5`X6=UK{s6T;5dHBD!Bic`dn~?)Q^hgs}4-@^G@4tP$eczMk?zA=1-E zE~WdqiE^@Vq_c8A8PW6Y@B^FCb4PFBBr& zeUzUhUnbuoKOw&+yB_4Grw=($*bC!2h$R;7e{fzPrklzVoINyv0(av`jBK|$dEV}2A6Ub5_!nIO9i@aRe&2erO!p@!KL*&oNE#y}6 zMIpldS=hsIx*qI???(0^cP4ii!rw3<)Ns!FeFym=`6u#A@*m{)LWCQ52>3MaTMCi>gUE4okCT;j zpH3blMEj{Fk0+bS6Umdv734YO#pI>rwdD2WZRB0#M)DEzDe_tJm*gAd@5pz_Psq>7 zzmwmQX=B~|^dS3@yOLSt5OM@Lk{nBpBMZo4vXY!mCdfLniCjo7B~Kw&lIM|^ke8F| z$o1qM$(PCP?D$H!_pljogzQN*+KSL>@v;B=gBqavFIQc`P}HoJY2iOUN`_n#ewz9%LVK zXA;YrN{{6pMKlA&aU`bLO2(ywVuHjHhLVpbo5{uGGV*8SW#l#Fb>uDN9pvNWQ{=D7 z-;(c>ACmtRK7mifrP}`uxi{rq$lb|NMLtVzBVQxmB6pB~BflnlMcsU4lJb5- z$(Pz+4UV9!_EkfkL|N^phOG8aKjx_S9?HI)*`f!JCr=<3kr$E|lWWMU$s5R<$zPC9 zlFyMZk#CT1l7At;B)=mgUEOqbCwr5F$bHE}$?;?XsrE%9Uq?|^`=KE(pse;mLtZKJ zBaU+(c`1QS5m%~d{B6&<2+10PCiAxOukBfM1D$sLH?bTYZtMXMrM-z$^C@4BcJ3batv8U z%6l-y-;v}oWIZ{TJYBfKaaNFOzcu8GD64(fkguV9Ke>_o1^FcT0=bQRlYE=}D=F{U zlz6`<)xK@WJ-WN@8RTH$P1sLBs(sp!M^c_ls(smTucSPkY$6wuCz5I(HvC^K@_Jmi zkyn%J$Op-X$;Zj3NVT6D;eSW@59CLrOmt*FP*<`ixf8iBxj&gpjwYv&Wu&|hRO}r| zE)cH6^)tDQJe6Ect|8ZwH<0qaPznDixrN+HzAe1gaehyJNdAdb`=_B#@9Fx>Ap4TT z$l>Hc7{2-!=5rlpD$UWE;7JJcC?GUPZ1YZz69c?HZ@5d-4zDpU6Lx-;m#v{daQh4=kJJefS5yo|h(ypFt){JC%`>X&?)l=t3> z`wsFw@?-KdGKLFm@zR)Yg(o^rE_n!fIGIltk;jqs$y(NVUHm z`j07pMt({DgUsyj+V4-w`-UaHy~%@x^HGoFL^7W|iaeH-_YaHzM)EXL?T3f^d6a)j z-Xxrd`w-+kq`a3{+#e&KAm1e4Cf_GNBtIwrM)um-wUbGz{qeB72j#)!P;wkOk(^9U zC65(0;=VW8NX{qEB+n*)O8$)8K;BN?M?OTpNWMaDC*LB~{`ooFKM#H;|Gi{xwMcJg=RyX4== z??|<;9_j10tDDX}gxH6)H#w9%fSgF?lT*oZvVm0l>|tjit;4fchT7m;c|KHSwld~hAzHkOt5E-l{XOaua zHu5C$G;$?*9(g^fo)dt*J1E~nZX_Qee<_^oIB$@@CEp>xBEKQK40Qdcky*k5?8he$ zBy-5IfjpPIkX%i!A=i>Okeh_qZ}lj- zh1^QMP5z$zkW|knAYA%h2tOYCR>{8PF67?iKI8~;Bw0k3km`8`*i+9lfXC8(7O9?R zfcrwq=L*N*`CM`}xrV%sypg<%ypMdCe2m;qzD2%E{*nBY{0sRlsh)E{I(FL|>B+%9 zS8@nBj2uZGOddhzkyFSraxU3Kwvs23r;=xo7m(`t2&6+j2Qdu&Slq$;$&KXWN@_4eDJcqo1yo9`* zyq3J4yq&z8d|rq#_+|19@=fwx@{i=7$uG!nNe6inJ3Yt@az7!i6%Hgvkz>ds$UL%? zoJP(hk0zH1u?BW3c@}vt`7`n|aviyzyp6nz+(bS~z9Eb`&YR>rMp zt0=D}A0XB98qja1yoG#Ih`I6GN$^d zv7R~vcEG*J!Q_Et4p|^PANQ}w3bL9!o@^!;kxR*ogty{(fAUK5TJk~iVe)bEDe?t! z8~F$FBl6GW7i7B8m6zwm72Ux@a&Mu_&dPIw{mFT4c#7ha0|3sFd$g;yf~!mE*g z;kC%Wa2@h5ydL=%u1EfbHzEH*Rj44^Ww$Qi?a06IPUK&Buj6D1???WH4meWkbfcCqa5O|E7^@i(^BpOgqyLCgUlj_khwzG9ZilU z$B`4se6m8g1=kDYO!8>*II^BxNVbtn$dk!)gylew|Mi3DLhx$O<9)IbNZvI8%uJel&TU5dFTMoGV2CZz2~8 zF%GDGTi_CrYq@_5JY8gr3oFQTgcu(#AXf=7POK)^2r*tWfDRYHuDtI0J&bmptcbwZ4r>&Xqmji`U} zZXw3e`^k+$bpA)k%|eWqTga`#&8UBJoA3$LKe=6q!Qw4)hY;iLd*nl1A!Ga+gO7|` zGldwhT7Atho)F`}nL_mc z-w4s~zZ0UrtNY;S=ZE!%jQ(9NM1QUq*5dbJh3LmW6*izegmbXJNA9;aV*V$bhjt*G zkNx>V^vgSi=#O1@0?`kL3eo>22+{9W3(?;m6r!KKBt-w(Hxop^nk-z7eLKRl9p{fi z^c(fQsPoZ2`#`=B;f3fY_;E(nFCG!1KdAdl=m&+U6X^%){t(*zVv*6_)%~CA@qCoX zXy=a!Z^Am25bb(ifACh!D}=XWU0HaiyLG?XXh6~Zc%C*{?`8l;!<-9q$t_5NYRw^d~H`?sjyAw>WGg!1P?j04|N zcDh2wc+g8I=@-_boGE7s>rl>=bA=cuN+?$dF<#VDo-4$-(MEZR5aY*c%4>ueM{cKl zw{QW*b;_HCCm{WlcL-Zi-jvmQfES@%pbtrUy9qJg452(sh;e5e<%vR!KP8madwwwv zsr|4B-z4rBk4~q4g>bp!tfRbMcqYE_@4-{gY97cJ#a2@(N<#EF6(a$ND2-o9$Ncm{tO-L{0CgBELr%}E@h;elt z<@G`gPMaxj5n`O(LHRu)2Cc6te=EfJJD?kg^sD#s-jDQB9xlXqtlrNH{Wy^~BE8g? z2r)j-q+pcYujp_>{+d?PIgN}Q?@u}d%wbgAMWsfde{6JnvVPif7qoX-+>>Q zN$Hut=F_QU&~GP`LEjxE1HVbq>Cy=J?JyYu-K>iGLk z9aoC)x5Ls1SngahI#(L5;m(#uz;{Q01XkHCg^Zr`t48paQtb}oSap{ca-ix`*w@O|2funA_-|ToeCFH z1^+_0K$&$a9MYLrH^1{^yXUvV<`J;miDE`FI@dg0!-1@}UlG3Lj*@}W?{sMd{B~Fx z0pFcVM(0YyHQd?K2>9+O8B)+Gew;9T_%(fZSR$77P9`S#_XblZ#r50SgoOMCVTfrd zz|NP6<-5bASpGXI6MFAdnFRcHHX&hUVq7=4Kl0e#S;+O#esr#%cJmtk8>ZGTj@q>q z9*8|9)rf&WAwMtLaZDkBI*uvz&yKc}ywtxenktZ6z^Q&`)GoGU-<_#G(|WsA>6`Dk z+1h?Pn~<<(YhCgt{Tyhj!b|d)>UTr!a+H9fKNA|}F|Whl0Sya<-_1<^(NEi>`)k+M z4|axl!T`~+Ck)z2Kh~MjR`6#)-35n`U-net>l@tl@tLS3taV|rUF^SrkNA;~$VcO2+G~T{3m<)Gdo$r++WWw;CuN}R zormwHz0;`!)S>OIgk;+L+^{F<()J$0chlYq$R+sbL)*I#4yL`Y4STqi;n{l^-%WdR zk0LC;zq9N)fA`Bz{Ok1ffictGThsyS(CL$Ro0#eAX4u1REYBW()-+&m2Xqth(TBE& zpF<7U%QWm|!m~~ver_~iFAH*5erH?u1{n5myUVk;#!=C&WscBD6uwnIkh-Gh$VGp-{z4j;f7EOCyVNc@Ihqf*EBF*%z zGwjJ6K>SI2mV1(>J-J64mfuyDy$yyv+qFv|<8jO0-G;rf(2GAw z-(M|z6)DQ^Gt1sa!`@+ry)4|TH1jL>p2tD24~bWff$(RR-)6&}_}A%^d#a|rRVm7^ z$g;Q9us6Z5C%>&~+LL!kg_Yk@%icD_-bBORZI(T`XRh-IZ{GKtEqmJydy@=%a0yo1Ti@7F2H?*hx7^ACUiS7O+ccQu*zvQV&L{a1dQ z)-1nnhP^Vw-k&UcvgaYJ{e5WJ%QWm&82041Yt8hHgFUHxedzDI!k?MG0fxOwcou&$ z9>_g;)851s_VO)zS%$r8!`|tZz5EpRPPXg~Gwe+_>}|B{6{WCuzhy7ius74N_qk{S@{jx+4tW!bv`2Ey`tn`LjNVQ-dU?>Cmcjj$J% z-(Okwjx+4l8}_=Rkj?yVfj#_rhyEUeKeImO8un%z_QqKDw!%PIeq~RlX>XxnZ?0i) zmSs=&Acf`kSj*lL!`|_Ry;YVy2j>Z$N6EDQet~80bi-bgVNZTj*(^WV6BU-yWxv&?O-}fzhs|E&>kNCc#-i=DSoZ2u=JvKMWLHb#FUzG&IoXxLjue^P$mS@yQ3$nW1Rdz%e=CmZ$->=~?I znfK&EuMeHy{ov26->rtdQ{h?XSKh5=wilTnh2^)}vbW8!ce-J3rDbmz?1i=GGc0@C z4SQ!8_8zqCjfTCj`n}h(x5Kcv!m#(gWp8eZ{Jvw^`@pcb(y-SDnKR2z=22n!mEYht z>*I67-Z_T7BP@GsU@xqG54Y@nZP+`{us7GTCwmvAJ?TTYm-8%tGM|xofj+dql~%mY zH|~7x1$e|3ORrtsY1z9P_DZxd`V;Y1%U&kzNxu<$*rMs#d&RQ%0qp5C!JGG8-f3r+ z^8mvhws?B>(s~E$P3ALU_PW5IX)nvLhb^L>J$cui*$!kL6=qM~jc3{$X4u0PQ_tQ) z%iiBo*lV)vML0CWU34dn!6&d!fG3<@E?2U%KOz8EY(|V|7ufnjm7M{hQw8#0Dy?i(h)W+yf z#74{BOvB!F^e6VNw(K1T$FP3B#d+So< z_b-;cg@(PG4SW0S6s+GzU{BWpym{Z{-GXNQE-~!gV%RIO>}^hAugJ1@x?%4&!`@kz zy)7y1Ew}8QW7xaHuqW>(G~2W6Z4S$?yvxwc?<&LIU535)EPJv?I?Ub<%ibEp-aUrB z-e??V`sCfbVePLw{F&)nXV{Z_P`ZD}I}lBK5-6I+bO-CPE_m<`FoXPk-n0>V`-^O+; z-tGHGoXo*)yuW~V9k0AYQri|Q&o;Tw^=OM)C(o22i{5p`2U8>Jc_2BTKaP*K_fN}S zd;y*Z@1m{was9)xS5X#G&y9$^Ck=b@4ojT|u`&`DF?S4*Z|-$2^SW%#!-srqaz1wib{XFto|i%8TI-<#)ew3WUATkw1h`kX!_UOD8Qn`ZiQ zr$?M^nBzX+Jg1>FJfe1Li#7FF*h*g|M zGjayJhql@u3Le@XqV?|CE7j2vXPP+j(EeHyt#u8F*^8R%a&vRD7vzjQBzMf%+)-mk zjmpXznVb9nsJag*C(Hcr!^tF>%uI$Mp<@FS6%Z5z5fv3h5EaEP3Kp!WDA>DV7e!IA zi@o=Ty?58H*n982Vt=2T{H}BU@1Eo0_k%Z^-MRLeJefA=|NQ&Vp+kE195!Uwz=1u} zzqV^RV$|5t`Mf_V{qNjo!T*l_Gp4V-;P*=P>r0>P`$Kfi&0T!JdXLU8_R95L=f!b9 zswJClrF8KA%d8KtXnfmC@)7O|#`16%iz`Gu6;kTJRNBP38XCTe?^*?V5d# zNJFvwQTC4%YS}+t=-+XT^!MrKV-yB<+BEz7(yVko-*{v8AJ$k*qg*U5RZ2fOqiM~7 zx#H4Y&d*vg-y@rYa>YI|7t7}Ixnkd#i)M3huGlZ;BH0|0D=rgr;cTvuEB24MP&S9= ziUVSH&*qA`;<7QjWph}rxLnMx*<2}C92m1pHV0)7Yf$XYX=jgX`PiM(&K}s{*d5c( z9@&uC9n#Jo+6u92X=jgZXzXg**@Ig#cKfumM>i~XTiV&fTPb$Cw6n*za_rV@FP}ZW zRbp4t&K}?J*ez*ik8jo3&1q+kZ?)J>X=jgb_1NXKv&T0gc4OMv<69$kDedg>tr@$R zcJ}y2#xA6tJ-)SKH)MNo_V`A{&ZnI{zR|I>w{>%|*t?KEdfjqvQnX~J1fV6oj9*;4 zd_(s4NyvJo7qSb>0wH7LXb4$9W(e6JW(XMM*n}J#n~>vT6LNfPLQaTH$c)&8 zoEV#slVTGxGd3Y7$0p>I*o4fAO~|RS>q7P{bj;qRv~vG155^2355){256284kHicikH!okkHsY9@z{hs5u1=F zV-xaJY(oAQn~YO( z@;TA7T^oV{AfxicQGRu?hJlHX*;pCgiu+g!~?xkomC*`6D(Vf5s-{uh@kA z9h;DUViWRjY(oBvT^I6h;o$7;-||Fy?(yCNA(a{F8j{PG6P@fka1@LA()rnIX6@45 zOer6ydt^I%+S_O^mhJ3mdD&hx+u76dCVP==XHUzU?S-?QJuPps7s___w7g<>&vy2- zyw&cO?d)lJJG*PPv!~^4c9(3Y`SQR>@kUhkj&@qMVF?J9-q>w$xjzTSk z>``_Sswrd-v$N1Xh3s*55!zD79%xsgT?*MF?IyHlA>HA07b+=ak8~lSC57yfE-W;s zkUi2xgr*d-N4ls`P9b}wiwTV>WRJ9mP)Z?tq&)TnutU+Zb|_lT4n+g)P&CL6Ma$cvXs}Ju5P_l<1d4_V6s;&wG)$mqC4r)q1&US? zC>kzMw5mYSY63;83lxnIC|X0HXib5lkpe|)2^5VIC>kwLw6;Le7=fa7gu0@o^M%F^ znWEY0Qq(6DJ(ozWn=dC{Nzn%R($d*$ZVMERb3PPpXosSW>`=6^9f~%wL(!&oDB8>p zMVs59XbU?OjkhV`=779f}UHL(zeDC_2avMF-oV=ny*;9cqW7!)%HU7brSH zplG^4(UAg0M+p=iEl_lfK+&-RMaKyg9WPLHffua)yicS(Jnki6pvOv)(0!6a~ zicS?MI!&PHbb+GTLS4~b`NHWLkjhfoopy2WP?UbyYw?VHIr&P8&dHZ<%RYXxK+(C* zhobZBP;|Z>issm%=mI+wU1*1*i|kNzu^oyou|v_NHbs{S6kRS*bcI0Cl>$Xq2^3u| zP;`wz(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86wMVVx?P~?4uPUO1&Zzx z>Wa?F7v9K#RMJo7EuI~UTGF^XUrxS~qWkluKNbo_4>%u+9<)QzLv|>7*bYUH*rDiA zI}|-;hoZ;rQ1pZyik`G7dP<<^e*#5M3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22! z%@ZhkMWEFb+{_l2VL z17(Zv<;%%eQuI;2lzukLf@{&o&WEB;>`?Tn9g04)L(%7UDEh(mOF6C@)adAk-CokT2|*0jcbleWbkjVJJExU5g40<>V_V zDmRpl?GcKaoDW6Kb|`AGLs7*JMXh!yYG;R{Hairxw?k3Y4n;Maq7DK@9R-Ry2^4h} zDC#0m)K#FUn?O-_fue;3iWU|qT122|QGuex1d4hH6!jD+>LpOLxIobo0!6(Aik1{8 zT1ud3X`!yD)KIuK15!C4`}ldWv7vsa|9-j_^=T+4UrAB_hSD>=LeT){L(#H!C|b@A zMFZ_nG{_D`%iE!7upNqq*r8|zI}{DIDOypWXqZ6JN&-bI3lyy)P&8biXjOrt)dY%G z7bqGbP_%|X(V7B9BL#}q5-1uaP&8VgXl;R_F#<*F2o$X=P_&*v(O99bs9!_jhYUz% ziPj9xGNGtby3=33p`3grMH@AgYQ00z#?FVLP3%y#sU3MWAR8fucPHilzz_O%o{EOQTMKc77P829QNuX$^K+(wpMW+Z9%@Qa&RiNlJfuhp|ie?KG zogq+kra;kILS50m4TVE9Ae9m6C8GU8(LL!}baq2I`AUk;Zzx^RClt+bJ``PGhoTGZ zP;`+UiY~T8(Is{$y3`Ium)W7{ayt}VVN-OaK+#nKMOO=(qG#`@V*9@|6@l)KL1kUnqLm`B3zT9f}^cL(yY)D0Lu0L!j zCtpd?rwygP147Yf&WEDU?NIcE9g4oRL(x}uDEitCMc>$==vzA!eP@TF?`?{H5GeXl zpy(%oqMrqdei118RiNlMfui39islOx{UK2Fr$EtP0!4od6#XMm^shkCe*#6hLfp1f zlou#!5GX1L6cq)ENK(}kJ~^*jAn)3s=sLOJyhwnNbnI~1*8hoYf& zC|c1DMZ@e+w31EH$^u2J2owz$C|XsZXf=VN)dh-12o$X$P_(8%(MW-!wFHVr2^5VM zC|X;fXpBJ7Is!%O3KXp;P&8JcXnldA4FrnD33WvS3Wc{aAeA2Jwrtr@^n1E6ZCEHL zUrEuXh0DUZ7|PfubD+igpqx+F77z7lES50!6zD6zwKZw7Wpj6oH~W1d8?)D4HrzG)kQw1&YoPC^}Q1=q!PvvjvLI5hyxWs4F_4 zP}n&GQu!{yIWQCrPw&yrE0mM3r0Bvz>G`-*29g429L($bXMb`)vT`N#@oj}p`0!23n6x}FLbdx~Q%>qTY2o&8aP;{F> z(OiL|+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj2biXIT^islpw*JnT~^OB+qLebl4 zJXk0vUrEuUh0=4`mzpk6^qBLZ=y5v~Jzv$h6n#-BbzC(R zed&BC`pOPPU)!PR8#@$zYloum>`?T*9g2RiL(z|RDEi5!=x2eVUj&MN6)5^mpy+pj zqWJ{qP}Ic^MO|%*x(O6@7bsdtplD%%qD2IX78NL3OrWTTKv7SDqFw?; ziwhJjAyCv?plC^fqNN0imKG@LBT&>=ps1ff(J}%>{RN5!2z5o3V&U)%NM)mREov>+ z@AP+1@6nbmmXoifX!&C4qBTO%VCO^85IYpDV27fib|_lW4n@Q4P_&XAidMEm(JFQ* z8g5gxszA|d0!6C}6paulT0@{{O@X430!3>H6pa!n8ZA(?wm{JsfueN;iq;h09a-Hz}5rucT;;V(HV7 zp=iAGp=e7x6m4aPq6u~=nrMfjt?f{>jU9@%wL{T%b|{);Q?$K6(GCJdI|>x-Bv7=o zK+!G&MUw@Jb`>bvO`vFZfubn_MSBPo?I}<+RiJ2^K+#?TMSBYr?ITdMuRzg$0!8}^ z6dfSc6>U~5w5*jW%BPQjY#xdxEx2JTmXoif=+I(mnbD!>Fy}+j;dUrG!VX2#?ND^2 z9g2>!L($Q8C_2UtMaSBq=s26A;{}RN5Ga}JXEpy&*NqB8}G&Jrj(TcGG1fueH-ip~=#I$xk@j!;*0aIvsq2Bea{!*=nI zQ1o^BG?5F6<>V_Vx};dzYfLD*)cH_!nH`EQw?oktb||{i4num+K7pe91&SUJD0)z!=plikhlRSLi;9J_G9Z<=(nmlp4n;?$_h^q4%gI+#^hB|A z=enWjN#{e+Q+6o&pB;*xwnNb~b|`w*4n@z|q3C%#6un@Fq8Dw7UJ@vJS)gd1K+!7# zMXw4Jy(Uofx5MV;(W)Y%S2UF=ZQ)ec47>`>I* z4n+&u6fG=Jw1_~_q5?&W2^94ZDC#Lt)Jvdfae<;G1d4hK6fG%Gw3I;6(gH<&1d93! z6!jA*T1KF#zd+Fdfudyvik1^78Yt8iwUr8!Ga!}p9l49`OZ7YbZ_`ulL8Wr?l@zT| zD$Up^6b*Gg6s>57qG5I@TFDMYE8C%H6+09Sw?omYb|_lS4n?cm6paulT0@{{O@X43 z0!3>H6pa!n8ZA(?wm{JsfueN;iq;h)grY0c*t}FuzLKJ?N~ISz2}Ki}4@DF0P_(rjing&s z(YAId+RhF|lk8Bmy&Z~nutU*~HbpxL6zwcfw2MH|WPzex1&VePDB4}1Xo^759s)&s z3KUHhD4Hfvw3k59-U3DY2o&urP_&;w(f$HO2M81$C{T2eK+(ZMUD5bb;g<|ZWo~*Z zv}GvTB0Whuq*PA6lA+${CQ#uIaYy@KE$dx)xnrDkon_(dDJm zgz=&13g<)7m3An)$__x6DWFLpy&gEq7Ma%J`yPUSfJ<=fuc_Ziarx4`dpys3xT39g}S0AONA#gAeA2J zTJ%&X`Z$sLs#H$ClA`ZQrOzjZqVJs#ML*b~=tnyg{bYxtpY2feiyex7wL{Twb}0JY z4n^~AivAEN`ct6jFM*=J1&aO=DEe2R=s$s?Tw~m}Qr7GlxNGs-Q1n&0?Qh>$PQH?&j*X=O z+lHb}&WEDTb|~s%hoY`_DC%a1qV9GmTF4GX3)`V+5jzwuYE!hBKv55YqMiapy#$ID z7bsdnps2S%(UJm1O9>P$El|`)ps24vQ9psAWdw@)3lt3yC|XvaXgPtRfdWN?1d5gy zC>ku(71bIG8)rZ&_oZjo9UAL*`rXrQ|B%LV@|6?~Yb@F5v?&@XP_&jn(I|nU(E>$l3lxnJC|XCLXkCG#^#qE> z3KXp`P_%(S(Kvyk4F!re5-8eOplB0;qD=*gHWMh?T%c$Rfuiw3UD43S!Z{g`%F*ea z*ovX(f%M^!EgQ?pS5mZfW9jZ4LeVzPhoWumP_&&LiYD2iXnQ*p?O=zZ9qmxGlO2k7 zwnNb_Hbs*Kigpz!+D)KncY&fQ0!4cW6zwTcG*zHznn2NB0!4cZ6zwBWw68$XegZ}N z3ltq7P;{U`(Ln-52MZJ(B2aXwK+$1BUD1Tb!h0Ez%C+h9izbGm6VrRN!yC)VS5kCT zW9h%0LebIAhoWQbP;{&vijK2G(eZXDI>8P_Gwe`wq8*A(vP02Ko1&8iicS$Ink7(l zszA|c0!60_6wMYWIzyo7Oo5`a1d7fUC^|===v;xK^8|{{7buz|P;`Mn(S-s<7YP(y zEKqcbK+&Z_UD5Q$Lhqe3MQ^8T(UGBOkp(wwjpgJkDY~k$G-`4vy4v|rbd4Q~uC+ta zb#^Ga-VQ}K*rDh~I~3hyhoYP9P;`q;(X9eSw+R%@6)3u0py&>PqB{kO?h+`vTcGG3 zfuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yKq9=vAqAMB;yJbKs zjp-$#D??HGf#b!e8q3L7QuJ(N>7?C4(R0p+qUY^U^nx9VUbI8eOLi!F*$zeX>`?TI z9g1GHL(ywCMXw7Ky&+Kara;kK0!42N6ul!*^sYeBdjdu83lx1IQ1qcd(MJMB9}5(H zB2e_HK+$IcMV|{4eIZcvr9jbF0!3d76n!Jq6+PWpxH$t-c|N^IdnOcRKXom;VQVZW zUrEuAjir~Sgrc9E4@E!Qq39Po6#Z(4qTlRL^t&C3=G&p@4?7h7X@{b}Y>NICDEddB z=wE@N{{)J1<+yF9C@)adAW&2gC@KmRl>~|!1&Yc7MNI-l%>qR&0!0;pqE>;Tb^=9h z0!8fwimC!dHKDHP`^Lg=8Ia2B>GJbKD7r2^yY5gfCtpcXmvX7=)KJvb`B2o&4n^JV zP_&R8iWas*(IR#zTGS3ji`k*5haHM~+7$H?C|X>gXbFL$-U3BS3KT6RP_(o_Q6GV# zz5+%41d5gsDC#dzG(ezeS%ISE1d0X<6b%w6T3(=Nut3oefua=ziiQexMV-op;Te$1 zkaVZtxm>@~FQ+^G70c!1D=Au~T-tiCP&C~6P_(KYidM5j(du?68exZ`HSAEdrX7k# z+M#GII~0wwDH<(Mw6;Le7=fa71d7%bC|XaTXskfd`T|882o#MIDB4hpqcR|s@3UE4ITT%zu0<2e<>V_V z+OAx>Y@bjx$@x&Uy&Z~nutU*~b|~7(4n;fLp=cL76iv26(XMtV+RdhDcY&fQ0!4cW z6zwTcG*zHznn2NB0!4cZ6zwBWw68$XegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXwK+$0W zMTZL%9U)LOU8pPCrd)U`15#Nw-Ii?|ir!A2gneYWoO~rk$CgW9?iY%Vb3POuZ-=52 z>`*kr4n-&0q39$#6wS0l(aClwI>in}vuuh^6(~AQpy+ggqS*pPX9yIXDNuBlK+)L( zMdt_o!4n;TEq3A|C6y0QpqMPkdbc-E| zZnZ(1d84k zD0)Yr=v{%L_XLXG7byBbpy)$^qK^cMJ{BnYM4;$Xfuhd@iar-8`a+=SOM#-V1d6^E zDEdaA=v#rJ?*xjz7wU?hD;LhofK;|gPlcWjMYpDF(GTTv@|6_*QZC(lXej#C`B3zm z9g2RpL(zOY6#Zd`qCf3W^p_oq{`=6Z9g5bpL(xb(6s={4qEU7z8f}N7we3(e#-?Z;fueN< ziq;b-8Y@t=zCh6i0!8BliZ&D|+DM>iV}YVg1d28lDB4V*Xmf$0Ed+|j3lwcBP_&gm z(FB2_i2_Ai3lwc5)D;bHDon|MR5nddg;otkGt#wa+op2zl@#sJR66qFwAzG}#VCyV{{>H#-#VZik{Nb|~7zrf5%rqNxH!(*%n45-8eRplBa~qJ0I5 z_7f=DU!dp!fuaKiiVhMeI#{6S5P_mY1&R(6C^}rA=m>$L=>kPZ3KShBP;|6VS2U@q zaBBvn(v+SGZ6AuBOxL1gn###nQglL7Y2LA+XomBl=tMgdon(iinRX~T*$zdg*r8~a z9g0r1L(yq=C_3GyXtqGn83ILT3KX3sP;|CH(K!M|=L!^^Cs1_0K+zn5q6-9yE)*!b zNTBFqfuc(UiY^r>x=f(xa)F{N1d6T{D7s3Z=xU*^=(wiB{0vCt!StcC<3rIBiPSYs z<>V_Vx}mAm{e)0-qw}HYCOZ_}Y=@#->`-*89g1$VL(yD26y0uzqC4zRbf-?dS z3l!ZWP;{?A(R~6%_X`v~AW-z6K+!`2MGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyZ* z6DWFGpy(NaqGtt)o)hYdu4^i+mI0}x&qpg>ABx(i_h`>Im6NZe=;fx;wkL+7dCrHT zSL{&qsvU}6vqRDAb|`wo4n=R;q3A6;6uoVSqIYbH-W4c%PoU_1fuautiar!5`bePY zV}YVi1d2WtDEdsG=yQRhF9eFd6e#*ipy+FXqHhF>z7;6?PN3*}fubJ-ihdL*`bnrO zda&o_+)Ti3Po3?7qWkDDkon_(eF*AD`tkG`Ob%;KkQKSryYv^vP03|b}0JC z4n_akq3Az56y=)ZzC9G>ZHgKMiV6ZnMS-G{KvAPWQCXmk!*6)n_UsLsk1Etj59FWg+e)88SDRh!GnS5mY_b7|0Np=eF#L(xb( z6s={4qEU7z8f}N7we3(e#tud6*r8}$I~1*FQ#4kfXnldA4FrnD2^4K8P_&Ui(Z&Kr zn+OzbDp0hUK+)y`MOz3IjTb1|QlMxnfuaclMH2;zwiYPbMxbb0fuijMiY5tlMXNU# zHqU@mHcywI5uvF2f*ZExa`KfF?c7{CV0I|l#raS)*$zd!+M#GSI~471hoUKVDB8mg zMSI$zXsR8Grr8wjB~Y}tK+!$|Mf(aA?I%#Qzd+Fe0!0T36dfc`bg)3tAp%8*3KShC zP;|IJ(Gdbg(*=r-6ev1Mpy+6UqGJS#juj|6PN*x|vAHlO15$Z9z3RAAC~8cfY;=5c zIr&P8PHHaQe`Y9}>3k?U*$zdg*r8~a9g0r1L(yq=C_3E^MYHWtbcP*@&a^2yOQ7g% zfueH+ip~`%I!~bJe1W1l0!0@H6kRA#bdf;O#R5f_2ozl^P;{9<(d7a~R|phcDNuBk zK+)9#Mb`)vT`N#@olsXaqq*==2Bb17o5d4D(fD-Re|>W~`AUjzZY~wh2}QR!ABt|Z zL(y$^D4J`BqTB6IbcY>^?zBVEU3MtC+YUwd*c9C>P;{R_(ftBN4+s=JC{Xl}K+(ej zMUMy+Jt|Q2m_X6v0!2><6g??W^prr+{{)Jj7ASf~py*kFqUQvPo);*3L7?bGp|0r0 z=0cwgNM%lX?fRxr^klk6d#Smcd?iJ%HkZ~pFBHAzd?>n1&TfsDEeHW=nH|OF9nLe5-9pw zpy(TcqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7lEQ*g}S17&4oQPAeBuLoL558b4}U! zt+||hB}IQWmuAfgMSnRTivG4k(LZ)5`qvIc|Jk7^*AjQ`p(t;Mq6Rw@73@${v?(eH z6g3JIl?95L1d5skidqDUDgs5V0!8fvirNH<+6xp_1&V3{MI8i+ItmnZ5-92{P}D`B zsH;FxH-Vz=0!0f6bw%@=3v)9dl~2?2qCY~>;4~I)DJNe^QID3=s~3i%p3aA&UUn#2 z+zv%c*rBMm9g3E;L(x)pC|cSMMSbj0)Yqn{pFq(v0!94=iUtT2Eh|v8oIue)fucbI zMav5m4HhUGB2ct~K+#Zvq7?;-h6xm{Bv7=nK+!4!MZ*P(Ruw2(O`vFXp{{7rmcpMI zkjh8t^0Qb={Z9XpG)A>l1&THkDB4`0XbXX&@d8C#3KVT6P&7fH zXre&T)&fP_2o!BAP_&&u(IkPQ?FEW<5GdMFs4H5tr7$7`QrRV&#gU=to-}r9DJNe^ z(XK6}NtcD9-JB0ayW62?iXDpfutU+Fb|{)^hoWhADB8;oMSI(!Xdj!ReFcj46DZnW zpy&XBq5}nr4iYFjSfJ<-fuchNiVhPfI$WUW2!W#M0!2p(6dff{bhJRxF#<)$3KShD zP;|UN(Fp=YGlaULU0MpqWk4!-r_0aeP;_5;P&6pr>EF~+PQH?&+geKBUKNVwIvO7be|oH?zbs=K%nSBfue^5iXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!@rCs6dX zK+!V-Mb8QpJtt7~yg<*+_1Hj zldq)cjh52jYeUhS&WED6>`?T!9g5zuL(#i-D00Us0jcEDZQ1LgXhM4T_D4%O`AUlZX(=6aeJJ|Z`B3zq z9g1?5xN{Fhc{>y}*rBLkhoYh#ib{4UYP3U9*`}yTpr~1(s70WtB2d&SP}EMKs7;`# zy+Bb_pr|HL)Ip%Aqd-w7fuha=MO_4nx(XC^6DaB~P_&Rh(ZT{niwG1gD%2JI)l#@H z15)`Uy%YO86lL$dvKzKaIr&P87O#{ZyfG9l;e06SZHJ;I?NGFo9g3E=Ls1_)6!o=3 zQ9nBrEn|nG{x(Ge1d5gwC|XXSXrMsRAc3Og1&Rg>6b%t5T0x*_s6f$*0!70FidGUR zT3MiI6@jAR0!6C|6s;yuw7Nji2!WzC1d7%a>WX?+3ZG;^Dlesv#`dbz@AS`4*P@Y? za`KfFtz9XVZV5$WoDW6o*r8}$I~1*FhoZ4|C|chRMH|?mXq+92Hnc<0Mm9wo3lwc4 zP_(H)(Pjcgn+p_eAy714plC~hqOAmqCI}Qw6e!wSplBO`qHP6=wi76tBv7=yK+z5Y zMLP-LuZK+%-~MOO(F zT`f>_jX=@00!7ye6kRV+bb~S2U|qxFZ8n**{&2P7OsHruS&K zR?5j&Qglb9^!lBl=uYQD(Oq^Zy4wy#_t>H6UON=sXNRKu?NIc99f}^bL(xMvMGp%U zJt9!_s6f$U0!5Dt6g?qO^rS%1QvyZ*6DWFGpy(NaqGtt)o)ai~UZCg&fua`$ie3^Z zdRd@ooHZd-nB!~dv+*#-ws6|*rDh{I~09nhoX<|Q1po%iaxa|`b?ncbAh5S1d6^CDEdmE z=xc$ZZv=|I6)5^npy+#nq8|i`eiSJBNucOwfudgoihdO+`c0tdcY&h$0!4oa6#Xes z^p{Xq^k${7W(K74etOmMtxz;7k@~w*PQH?&Tx)5E`$AE^HSXj?QG*?d3U(+e+M%dq zhoVM16qW5z)MSUEW;+zM*c4R+idqGV+6ff32^6&#D5?q+)dY$<2o!Y`DC#6o)LEdY zi$GCVfue2#McoC877{30SfFSTfucnPiWULF0nQ>ZKYw^BGE15)`Vz3TX1C|W-I zy<)G{a`KfFE!kSS=7CVOl=GozX*(44u|rW`I~4V^L(wvJDC%#Aq5*a&TGkFl%h?nS z6et=bP_(>2(O`k1Ap%7!2owz!C|XgVXqZ6JN&-bI3lyy)P&8biXjOrt)dY%G7bqGb zP_%|X(V7B9BL#}q5-1ua)Dk$Nw534N zRsuy61d1jK6m2a~w2eT~wgN@l2^38dDB512Xa|9!9R-SZ5-8ePplBC?qR9e9y9yNT zCe#&;X)SbmI8)Rmz3RA5D4LP|UUB!Hf$@MtKS=6opH%ML|*+o5P5I~46} zhob%LP_(}tiVm@HzV1c4T1d0w7C^}4_=x~9eBLs@33ltqGP;`_)(a{1$ z#|RW1D^PTtK+*96MJEUp%@8O$QK0A~fuflLMJEdsogz>)OQdHq3BVYqQ?Y^9v3KjLZIkLfug4b zivA~1^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!ybqE`fpUKJ>MO`zy?fuc7A ziry6JitcPJe3k*J3{97xyF$@o+3ywKYAq*UNzr@R&$E6y6us|!DEhz-MIYLs=p#E6 zeQbxKPwY_isU3p`az)RM}eZB z1d4tZDEdX9=vRTF-vo+&7bu!9Q1pjD(VqfEe+d-*El~82K+(TKUC}$Oh5i|k%5CXm z`tOFKmD8R6f34-@D=8|pE3N-*C@Qx5|L^omb|`AJLs8idMNM`nYPLgBiyew8b|`AK zLs2`MqBen|_5wv!fufo~Q3rvdjsiuU1d2Kf6m=0O>MBswO`xc|K+!@1MGFfQEh12~ zs6f$T0!2Lpih2qZ^%5vrT%c$Pp{^+3uCR9oq;hkD)6lMdkJd5!y<+cn<>V_V>eH?? z`}t7R*ZH^>^|M3KGIl8HZ-=4*b|_lb4n@n^p=h8TiU!%CXnC8W!2(4?1d3J=C>knI zw4y-KFoB|#1d3J`C|X6JXt+Spsscr;2^6g^P&7iIXbpj)H3f=B3KXp+P&7)QXtY4l z+5$ymgu0@o+7<4~fK>V>I7^43T6*`kPP=mQl@zVtuJq=Mp=bl=L(w=p6m4jSqK)iO zw6PtEHnBs|rgkXW%nn7H+o5O+o1*aoMOz9KZ6#1NL7-@&K+)C$McW7zZ7Wc;oj}nf zfuijNigpkv+EJirCxN1!1&VeND4Hx#w5veTZURNS3lvQeDB44)D_XBz;ol5M<@j_h z8XJn9OQiN}S5Cf?qP^Rdddv$&`#2wp_O(ONes(C@-ws6w*rDh^I}{ychoXb+P;`hL ziVn3YI!vJGaDk#D1d65$6dfs0bd*5R(E>%s2oxPFP;{I?(eVOBCkPbH5GXoPpy(ul zqL~6kCkqsvB2Y9-py*VAqSFM5P8aHmrnM`ql>w<#)2ohqg`(BdwP<#`a`KfFo!zdq z)2pHA9OpyPxppWz&kjZB+o5QV9f~fnL(zqHD7wfFMHkzl=n|WvO9hH96DYb|py&#L zqALZ8t`aD^TA=6}fud^#imnqVx?Z5@27#g*1&VGGD7smo=oW#ZTLp@46DXQ1P;|RM z(H#OscM5eyXSOSxm;tH0onCc3D-=DO?)2|!S5Cf?qWjvFu6sQc-S2!TdcY1v589#V zAv+X3Y=@#p>`?Tm9f}^aL($`QD0;%C=t+U1rv!@rCs6dXK+!V-Mb8QpJtt7~yg<B97GyK?fC6n)sP^y8bM=p*Mt(Z_Zu`os=JpW315GdmQ0Zik{T>`?Tj z9g4oPL($hZMc)V%eJfD(oj}p|0!2Rv6#Xbr^pil*&jLli2o(J)Q1qKX(eDC9^973j z5GeXnpy)4wqQ3=-{t+npSD@%WfudYn+?Z387wU@MZ&&E@R;K95bS?TI6#bSyeYT;k zoO~rkjcuhB-w8!!=R;AG9g3RmP}E|FqKX}gTJ2EO&JIOwb|`9ZhoY)YQB9zzgFsP7 zfuc?VMV$qTx(F0?6)5T^P}E(ZXd!{3g$0Th5hz+zplC6Hq866%VIZH0*$kjm`|PN}Var=LC3&TiP+%E?z!v`ky+u=heyf9FHd06P>d zYlouc>`*k&4n>3PP_(=qiU!-EXoww(RHn&637Ir8a zZ-=5S?NGFpP0<8_qKN`UTMHCzBT%%hK+$#rMUw=IwihVcL7-?yfufxRigp$#+C`vf zvOv+U0!6zC6zwihG)16j4}qdR1&XE$6ipNAiZ*B~e31dE^h%$1JuVdOl%8Gh)mBcv zlA`_EO3fdKqWzr@MF-fS=s-IZ9b|{1gY8gsh#iU!wL{Tib|^aB4n;@U6ipW>I#QtM zD1oA*1&WRlC^}Z4=s1C*;{}RN5Ga}JXEpy&*NqBDiMqJ7#5%Vt0-E2eAFzM<&H^z8bqwsP{76rI;r8uw`^I^X$FG{+7_ z7uccbLOT>)WQU@Q?ND@y9f~fsL(ye+D7xIH=n8?ND+P+K5-7S_py(QbqH6_;t`jJ_ zUZCg(fub7)if$4px>=y;7J;H$1&VGHD4Hu!bh|*&9Rfvn3KZQXP;|FI(LF+4(K&5} zeKR1HJ=3d>=Z2z()3xZ{wsP{76g}8hI`i{T^pNwR=wUk)Jz|HVN9|Dbm>r59w?okr zb|`w%4nWiryFMitcYK+>-&RERmiHJrIh%OrJjc zL0dWbN{T*dE4}??DEid-Q1qD{iaxhP(HC|o`qB{U}iMlR(kW0!6N=r4hyzXgi^5h(gspy)q= zqFnp9ZKo(NP}Cq$R1hdC3Ux&vwH0z-Wr`k4a6S%2hbK~{_T}U&DQa$C>h(=1YH>ak zRqRmIYKNkBb|`AILs5G>6jkj|RI@`-2RjsXv?=N&P}EtVsEa^RSAn8#0!7^giWU+m zT3DcH5rLvb1&S6EDC!|l)Kj3Smq5|t0!2#*6!jJ;T2i2BDS@J;1&aCz6!jJAipuQ^ zqcb3t^V3tIruOwa{Rk1UDCr~t2plE%8q78()qW z<>V_V+N6Eyh95%Frp||=&FoOLxgCnOutU*!I}~kchoY_QP&B~~MHB5%w6#sqHUdT4 z3KVT8P&7%PXnTR89R!MY6e!wBplD}-qFn@vCJPkpDp0hWK+*03MNsD0t(3`pgm^xE~tp=kMZE!wwzIr&P84s2ig`KM5Hkn^GF zU^^5YVuzwb?ND@>9f}UOL(vg-D4K4Eq9g54bd*ie(E>%s2oxPFP;{I?(eVOBCkPbH z5GXoPpy(ulqL~6kCkqsvB2Y9-py*VAqSFM5P8TSeEl_lZK+%~3MP~^Voh?vwj!;*$ zfBQnWpEE@#rH`W>5Q?r&pZIug`*QM?6kX81w9>Dk=tAd1(M5JBy4Vgym)N1`Qacn~ zW{0B7?ND@u9g42BL(x?>MOO4@J$(WB0XqQ~q|^tc_0p0GpFlXfV2$__>UvqRC-b|`wr4n@z} z6g?+U^t?dP3j#$i3KYF0Q1r4u(L8~oR|JY)6)1X5py+jhqBjJJ-V`W$OQ7g&fueT= ziry6{dQYI}eSxA61d2WsDEdgKD|)DX;qnYfW&Lzp_HZcblwN}TxP3YKN{T*jUwZtH zQ1pfKq3BCH6n$lfqOa{x^o<>gzO_TqcXlZH-VQ}S*rDi0o1&itihdR-`bD7VSAnA6 z1d4taD4H)&^oKyvp8`dH2^9S;Q1p*L(Z2#k{|OZ3s&U&+QC^^^L7=E0P*fBsDhU)d z3KW%vx}s0p7rx4XR7R(FVxNVg9n-a_saj6HlA_jXsq%LyYUg|?YO_O8dpi_W?NC&+ zLs17i6m_&iQ71bTb+$uM7n`E40!7^finMc;Tq(IS90!2#;6!j4(>MKyxPoQWSfujCGT~SN5FfapBd9FEwQ>oVP z^j}Qx-Ud|5$yZV|s9M_S-%zx?^Py<49g2q7p=bp=6b-dQ(Ta8`8fJ&0mF!TovK@+6 zu_+oZP_(K*(P{!ks|ys35GYzhplD5jqLBhcYY7yM5-1uiP_(u{(HMcEbp(pm6)0Ly zplGZ>(fR^K8weDQ6DZnHplBnZu4uVxVgC$B<@faLdSEEJAYGU?u9lOpq-gVM>Fiwk z1G4WtvxW1aXuKVYwzNahR(2?wV27fKb|~7~4n^D8p=et>6m4fyG)bUndx4@I1d4VP zDB4M&XlH?`*k_4n;@Wq39?(6di4cqGRk(bgWI$aRNoh3lyCoP&7lJ=tO~{lLU%p3KX3zP;`nw z(JXK+!n@Mdu0>ohMLqzED?mP_@ud$Q136 zUb{Xx6rG-~MRTg<6y2=hkSKFcJ z8aotSYg2TcK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellYT!Et71&ZzvD7sUi=q`bx zy9J8w5h%J>py)n%ik`GX(NlIP`kx(&p0-2LGj=F?)(%C_*`erpI~2WOQ}m)h(MtkFFAEgS z6DWE`py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84lDEdI4=tF^`j|7T7 z7AX2epy*SfuISNf;gk$WWk9+XJr;`Qrf1imRm;g&QuI}|bW?LE`r7$W^o<>gzO_Tq zcXlZH-VQ}S*rDi0I~4t7hoYbDQ1pvU(XRqUzX=rmE>JXIpy&^QqCW+S{t_tqTcGG4 zfuer}ivANQ%GKhwoua%zQG-BHL7=E8P*f5qY7{6c3lud86g3MJwFq@ZUsMaPWI!s@ zvswHy6m6L9^eeS;@|6^|ua$nSgrchRp{Qnuq7HT_>S%|ePIf5jY=@#Qb|~sr5%vP03zb|_lK4n@Q5P_(KYidM5JT3w)Mgh0_60!3>I z6pa)pT1%j4lt9sFfugkqipB^Ots_vhu0YXx0!3p5iq;n>+CZRaoIufr0!14M6m2X} zw245`rb1oO^0mTt8Ia0N>8a4*P}CzmyWXr;PQH?&Eo-GCtD$Hs=R?s1I}}Z{L($fD zDB8vjMcdk;XgfO;O|nDL_I4=R!KP?OfufxRigp$#+C`vfvOv+U0!6zC6zwihG)16j z4}qdR1&XE$6ipK-+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bf=6ev1Ks4Lo{R=6?)Qh6#} zi^hkd57SGK2iMBUS5kC%t@LDvP;`Xzp=i1tijK5H(NT6NI@%6J$Jn9hSUVIQXNRKW z?ND@rP0K+!1zMY9BoP8BFRO`zy>fuh+0MP~>UoheXsmO#}4R_$C8V>6b1)hlQf!)3~TsPQH?&%W9=| zokP*(&WEBa>`-*29g429L($cCD7wZDMc3M)=sG(TU2lh?8*GYh6ezk$py+0SqFV%t zZWSoHO`vG5K+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2o zj|db!D%2HSQY$Q<0jUg1pS^!+D0(ejiyo_$ldq)csak21uA%6E&WEC>?NIcL9g3c{ zL(y|~D0A33lx1KQ1q!l(Psihp9>UyA=DK;Q7asn0jYeE z?)0AwMcMsWcEeUHCtpd?x3$u_-9yoL&WED!?NIcC9g2RmL(xxmDEiqBMZegg=vO-w z{bq-v-))NK3l#k!Q1quj(O&{Ze+v}-BT)3OK+%5!MY#@f+fGqlpr}Ehs31^O6eubQ z6g3JIl?95L1d5skidqDUDgs5V0!8hFx}vXZg$FVqm9FVp^i3%0l-{GYbtoraNl}Lm zrS}&OMID_FMV;(W)Y%S2UF=ZQ)ec47>`>I*4n+&up=e<{6fI&?w5UMQVgf}y1d4hJ z6!j7)T3n!L34x;C0!2#-6fGrCw6s7`AAzF20!94Mu|!`)bI4qO4p*n9m>g9QnX@+(vpjXqG8U5qLu7Ww6YzF zR`=729g0TSp=b@8qBRAIMhXkAZZAW$?;plCyZqKyQKHWnz_M4)I>fuhX>iZ&N0+Cr!+TA@Q>-3&-& zc!D!D6g8)7(fAJK5}`R#MLZq*NKx!fYvr90(vJ*#_k$>n-i zZ|j!J^{M``P%hWMy85EI+`#IwJ#x7r)n|I;a>J^%-nrcH>K04oawDo2^vUJcs(#!r zmm5>z5Q?u6=$ zjdHn})fYC&d8mva-US^9h=L2QSE+0F857! z+Y@uSAF5Z(%;kQmetk+VH@`aQv|R4*+5xk(|NZl|`_IhY0Qp+soa`--udQ=l_9n>J zX3fdo2Km~n7iMpSd~M-NvbRFMHtDkL&5*BMbw&1e$k)UBUrRrhYD~VCey-5ieC_*( zvbRaTmVUCwruka>(G27Bwe-F9C+2JEo1<@+uchy9y<@(XzCH2ed@X%{*(v#2`UauX z^0o9G9{0`H(zob4FkegGW9`sG@jvE=R}YYma`Ay@m3%^nFHV=49Kq*ecH-X`C9tCgJ<)#^nv3S^R@JmzgP0L z^r4$K^0oBZ`#bqsdhzswd@a5D^+~>#UcUGuUrYC&-{foQ2I7Z&Ej3#kn| zI$M3Szn0AY>U?lHYb&(P%KknbSvUKu%e3s@@mk^ZrjW8C)t*t_rOsLFL^GM=zzt4KV^?lD;?>}$W^4>X* zWKSlUACs8`z3qiI)7WT7bB*CaGg@f;ZSDht*J^CDpF&HGY4#el@`rh?c(8h6$v7vm zVq*WY#e>Dl1_Dvl0&#KIniL2)WdcrO)3|1FP2xJ2G@q^B5)%lx4Fa}ACz1Y zu3S{v^=-_TrgZ)PY-NhJO6EfqycDxvX>*Tg4pvSma3|1kHeveUB0XHQQ{9iKBiYkXSX=&aoAwA}28 z*?C!cY1wr%^YW*R7?YEhpOZ6w_~@)L6Z6tW4IiGFl{+CVBR#WTX5I9<8JQXBHl~=E zGBIajc1m{EurVna>8bTn?3+`~oB#Euv@sKhkDoFkJ8eSN@X=!?{vW>@c{B2gekDeY zPHUYzV#=6_Ic;-tvr`Jb7Sr={BVQ8#E7B`BXRP^}=cV6 znVW0Gn2Gsjm^-SzZQEy>t2w-F&V&g$6HT*sgyxRfjZk#z1zoq~fA`{+j5cqM?&_Ad zhoD<5)r~a|UV_o}UHc#=nB-QE%%DI0w?;+Rb!(d(WzV%oXGXGH*1l3Ra&}a7TEW{J zM&3R>)qi`#|9HE9{xrSaiB0~G_lR6DAGq*>|8Gup(<3*6Gd9&NZC}%^VQ!UVr+jkc zrU^!0<;Iz}nHw_M9?aV!v$?so>$)YPOS&af%&TeU)u0=!8s(V#pg!$8W_C#L6tKsP z#_63hhxxBItY7eIgSG{)Hf*f-tlyZ{nv>J(cM5c#*e)wSE3;SDh!NQ%y626GTvq$G zIw`}PJ*Hbu&ZLY$_tpb5+xF;J*Z*McxQqq`SD+E8Uf~s~TX03%7P&}W)y?!T zA;WwyPUyg;wbrGzDZB*pB{A}of-^GO@}bNX z*BO>Xk#9NwQ+KrOvWHFa`DB={zxi0^zPrc`pzBe;@T!>`+yCSXJ{MG_7k(;D3a)mB z5gh2+eo$uXc6}n}ncGpHk@2e6+WqUy!1$brqmm>4^B<-%3a>~Tu|b!)%_1KFP8N*# z`&Za!YDKn>T*_GcM~akGulf4w>K5KPaT7HtygvTTANi~cZ}E&GH+hkpx}muug&w(U%Rr2M zv%Mg5EcikxakH5_6}_om!I#i{A$a$~8=l*go3!9&Y;3-MIR#h?Zxj2S!2c`?F3z08 z1sj3>Tg``!ykfo*ysh9WnU7_feX!HdJP^|RbE3IDBE{awk?$w|w~_V*XPa90sr^@q_$u_2Q3xudP!uuZx? z9-R2^X#Vi)m4Yu}hEK;{%_8^q89Kv|Df|MP*E;s-pWL=dlVtnECN(43KD9}2T(^F5 zt=#PK*;#qnwUbjO44*Wm#c=Z#%buPxpKT(MMf#N3xwg3A+UV(V?^!2iN z2?nBOCdMa3Ha{`3KRs#P#QaZ|{oz9(Xnx8aa2uy|Pwn2ibB{oDaj$!<6OJhnDitgp zEbEjDmJe14Rt#1OR*AYYnCk!hhKq_Ei>6TE_sd1!Xr2odo#v^w|Fa#UW1oB%d2!4W z@8U(a{V9<7X?|csLE|TsesBWjM_@%>oPhZWVv!doV1Bk&k;zWK_RT!K=iNaxCbNRBiM)NRj+1pXzZ;13c{(o8ahZM|8YoJ^{Nua}(HOW%Ie% zV{IK+zY6;gS9>t7EUx{=QMig=77_Ovi7>`}>%VSLXOTO~=ub{XIp;HF^GiOUFN^ z_&Ye&KQ^82A3N$e`zC+ir{nuG{k=!W_*woguVbG%{?63#@wxt9q2s~%{ywf_wLATt zq2t)Q{XI>`SMK%q+d7`T-`~yy{;~Ok{;{);w>|9d2Xy@4QGf5%G4XMKSJbiJB7bM; zxM;DzSL%4k{Pf@6KELW%V~M}(={SCwzh~(9>I#3qqvQFN{&rXS$7^5kk6m?~_oBZa z)N$t;e}AQ8v9eEMU5uh#L$PyPM7j#uyT zcOxAq?e+I9I&#xGdf;#!rx7F%suJvSvqbwi8I$ml1E{5G{IySUN z*L;7|?q-i+^XqvX`>PMt9--qH^?dE=I^Lpww~mkLxLn7zI&Ri+myTcSctpq3I$qY% zJUoe9&lnw(bS$Z3Z5_?G>B#$;Z@-aaV;y_w*hj~~Iu6k>+8)h?7t=O}$oYKSq4x2T z`8t`0ErBTW!OQV}sd+Odb%bWhF7&(9q*Y)Zbl*#Flr=3$xnljJ|{wI|uHd(jv3 zWsAI2HUDeh&++Gfyq|rWeW_{wvA6O6?)|PY@AF?j?k3ZCvA3IjX=nc7vh6l^Gl7Jf zg@xBznI3EYu}Ax|!TbfwfhLqTubZ1a@~cF9y?U8{ILEvi_}g4ozaoKGhy9oL>s>n- zm|#!P3-4$B75%uyIs^klO|u`@emwhm*yCjL59gRy1Dnm|CEHi@!rSb}D0+F5%;j0r z_VUah>w?RhXI|$V^J?Irxjg%RyzsW!CKSEA*+nid-n@CNppD%?Hl#N z+a5Bz=;bXimuEjed;QGaQo-ddHLu%q(#=2iWuAG`+R%PLz1X+ee_qm&_uJSs82LLb zdbh~?*!MHv-v4#|Le2jD_2a6pGw)aQ`aNFc^R>?!`Fzc{b8B>xIYeHnnagX+Fh~0_ z?TbC~XTa{E=Ka!5EMs2h^6b~$eoV}pR|5--zv}iCy>NNO%`Wt{x=@~`-w_(Hj$;piy)N5kiWL}1bXSMIv!T$>w{>28( zvs5nEmh+t>%k}@P*D}wQ%LE#~(fVvjXGoVJoiaPWdwzM~-SdZvl^j}f^b^6qzUcYK zmj3pwgSrjw)W7rIEc5nO=Iw!!L*qs-^55RC{pq&FTAl5k+v@E6w%xk#&Wahj^?a!6 z*7M8L_nr@B1nOMc-}6+%^vmb|x$JbXuWdgc$oSu_R%f@jZPLxWXK=f@oG<>Dm$U6( zm-D|~J^z@U+v)5bPL1y7?ZIv5UrFBf|Lb~{id?7v@7E{P#a@q+qo4G@c769`HGVr# ztV}C6#_9~sabw)TY;){gD;V)=T5z%XLl(csJZZ0ARHJ$Ks9NBQq3o?GNmt zLf&WQU7R)M9h_@QwzjXYHXqtaFV)Yy?wY43_Ct3y7a1K2)o@puw|VxzL041%UeOh1 zW&}dDG^?0dHxR0=S=r2b=KuFVvyz$h1ED&a70qlA2wkID!OVu{Kb@#q-podUP^xA* zGaCm&X_{rtY-0ZF3z}uj%rI9gL%X!y=6coDE@ij5V)e93+HI~`eeDuNU|$u-ja}rrPml*EQF#nRcAr=K3|)4%=<6UkmM6 zyUq2xRy)RSbNyOsdv=@a*GfCuZgc%wYrA%v>(@p*WVg9~ZMDtM?%LEf*RP#+l-c#n z^=q#kwA)<24%&u6Oej>%`Ow_{vG#8phN?&Y&6wDu<`G$_qqow$gB8-%{m|f!2UNS>yI zd^3q%XTITta(p4*8ycYpJuAlwdDKlXZ;S|8s8c26F--}1TvI}x(3FrxniBG)ri3ik zl#r)1CFE&M33)~nA(#-%{=Uh2zg7VO2{Tn33*#nLN;qk$UB-6vPDxuwrWbqyP6X6o~DFs z(?rO2ZG^n9jgTGM2>C!8As=cZWT!Slc4;GIw>CmP(niR~+6ehX8zG-+Bjht}gnX`z zkUiQ6`9d2Zd$kerr8Yvo(niSF+6dXFjgbA?zK{)0Z*%*{K500F-t>jEw~tA_@vIyx zsS@(NriA>UDIte7CFDm<2|1!EAwOwK$WcuR`B_s!j%gy~7j1+b*G9+* zZG`-)jgXVt2>DGLA*Zwv^1C)dPHQ9Nj5b34&_>9g+6XzTjgWKN2sy8fkPF%fxu}hh zOWFweOB*47Ya`?zZG>Fb_Jtg9^3ClZ8~M-J9*hVH&$ag%V1Oiq%->IUHX0z|*X_d-C+I6$U?0s^4|1-*=U`tV5wiMN4qo_UsMGXijYDhp)BLa#V6HwHIfTE@Z z6g4BDs5t>eEeI&OmVly`1QfL*pr|zgMQsQuYD+*-I|7Q@6HwHFfTE5B6m=q?s58M= zR5KX)do1B}bGH+!B}JcDQeA?c^<@?H2)b3xuPh>pdUC!L^%T1QZP;plCP& zMI#6($|j&_BmqUE2q+p&K+zZiipCO9G>(9x@dOl2AfRX>!B^BR=yWhZ!mpbd>Mlil z?0r#A(2M+p+9=8kx}(ewtRsr@IbVvVu%&1!TZ*Q!rD!@^ie|8-=q9!l-OQGvnQSS# zg^i+H2`HLHK+$XhisledbQ=Lha|tM#M?leh0*Y=Ypy&<)itZ$!=q>_^?k1q<9s-K) zC7|d&0*dY@py&YtiWU%1^dJF64-ruGFu_+eIq2MLfP|CHGwo2W6xn}6IP^%+v%c(o z(c?k)CG%_3h@vMrUy2s7rRYhv6fI^;(Nkj5m59z0YxtmP_&wWq8AA$dWnFdH3SsBOhC~q1Qe|$py*Wsie4k2 z=yd{$-XNf89RWq_2`Jh?@D(i#I-eUL;qNS*$D}A^$D2XV`m&1N4!UP5NYQ4_m!fyr zQnZCFMO)cY^e$V9-eXJAHntRPXG_uhY$@8oM$rcZ6n#iQ(M|%2b`emtn}DK^2q^lP zfTB+bDEgFuqR$8@`ka8GJp>eeK|s-70*byQpy(?CioPbGXdeMZ`w1xehJd1P2`D;1 z@D;rkbjq2(l@NC9ebFWpxea!4bsSc(P7S)q955(bc8KMKe46g zC|intW=qjAwiNxsmZIZqDLTPM(XRv)og|>>Hv)=I5m59y0Y#??C^|zx(H{g9{YgO4 zSptgA5m0oVfT9Zo6kQ~s=n?@%e-TjhHvvWe5KwfPfTBQD!Lxk-Ia-i_q9}r|=uprZ zVt|Bm%x^YB-%HU9dtc;4dDfRzydKv5L} zimo7_D4Bqwsst2WNkGw61Qb;xpr|^5`=S~I6xAg7irgq?xd9R`Wq$h}ijMN1>Cd$H zMYW&q&-Cd%DjRf;69S5w5>V8PfTHFE6ty6r=vo4bS`tvyih!cl1QfL)pr|bYMePVEYEM8>2Lg&Z z5>V8MfTGR>6m=n>s4D?Q-3Y#-tD~G>43O{^`%J%%6gl>pe)lNP`m&08N4as;q^J+) zOHp686!l|EQGd1+4PZ;rb!;gb$d;l(Y$+PdmZIy~D7t}wq8kY)8bUx(CILl52`I`U zplBEYMZ*aw8bLr&HUUK=2`CyxK+$LdipCI7G?sv(aRd~NC!lBo0YwuDD9RzAXc7TM zlL@|}o>5M^0TOoXeNitdx@f<>_^?k1q< z9s-K)C7|d&0*dY@py&YtiWU%1^dJF64-ruGFabr65K#0e0YwW5zM}jnXQ}}bK48Cz zO_8Ea_P*$`D9`$`ik^&eAFCxri#cD4o?=VU(`+evhAleQ1m7NMH>kydW+yIdLqi%WPpSh1Pz=;Qgq7R7j262tS_r* zOO$)yYAM>v`BL;QTZ-OeOVKvA6m4fq(fe#E+QF8h57<)lAzO-evQe~)fTG<56n#WM z(Z>W7eL_IdrvwyzMnKW$1QhKdpy&$%iuMvv^d$jBUlCCBH33EY2q@Z5K+!h@6n#rT z(E$RA4iZrG9RWp$2)?4tQBG7Hqv(G7O#dAzI&A;`&-YQD^<@k)oeCUy6>h zrRZn26dhwr(JyQ%I?k4&6KpB^l`Tal*;4cy8%3uGDEgg%qSFKvogtv;4+4t*B%tUl z0Y&EsC^}C-(FFpEE)r05iGZTN2q^lSfTDj0D7s8Qk@*|QPnw(2{6^jUsK)*_Hb_8G z6ahsJ0YxDKid=%P=x~(N$p8rtwf99oa$jUewBuP{R#Dh-$D~P79Op|>JX?wq*iw|p zmZBuK6cuAjQE|2um0(LzNwyS~Vxy=u0Yzm9C@M=pQ8@yN$`epjfqRv{0Yz64P*jb8qUr<`)gYj#CILmY2q>yeK+)9%Ur~(X+;4z{ zN87(H6zllU^mFZlq&kjgeOX0mj{9%6lJibs4iQI>anG$K3j?!u%)OWTZ$U7 zrKmAmikh%d)RcgtW&{*9C!nYW0Y%pmP}GuuqE-YHwI-mb4FN@M2`FkuKv8=FiaHQb z)RBOqP6QNnCZMPb0YzO2DC$N)QFj80dJs_5li({#ahxvRGx z%PQ*UxPR7@qW+vOMFZGUbRAoY2C}7S5L=1{v!&>IwiMmKmZBTkQZ$5(qD%sch7wSe zML^Lo0*ZzcP&9&oqHF?+MiNjoih!cg1Qd-SplB=sMdJu48c#sc1OkdC5>S*wK+z-u ziY60KluJNS9sx!91Yc1f$Ei@?D7wo&6zVHQ)9j<`DUN4-Sw%A(w^>6ex{33p=w`MQ z&16f_Eo>>el`TcH*itl`Ek$$KQgj?Fy`2-Z*PC(He1Qgv#K+#WIQ0Y#4!Q1k@B zS2WFWh8iH@pDmo}Qnb&KTI6`vmsRw%iauha z=wkwkJ|Up!Qv!-UBcSMW0*dw!Q1k@>MSBS-`jUX6uLvmmnt-Bx1QhKjpy(R{ioPYF z=l}sl2MH+pj)0;=1QdNwK+z8b6dfk`incn=2?Hct%l-!BT`AgO?~8tPJnPFU`q^<4 z%zrg0qUadsOVKZEDLT%Uq7!T>`jst3C)rZ;8(WG_v8CvDwiKOaqv#9)MSl=b^d|vD zX9*}eM?lee0*WpWP;`-iqDur6{Y600-vku>LqO4G0*cJv@AjXzqbNu~Q4|414gp0W z0*YJ$ilPZ9@(3u3A^3`Za-6ybNcbB2yZKv5+EiYgOORE2<| zD+nk`CZMP)0Yz65P;?amMb!u>s!l*r4FZa45>Ql&fTG$26kSa~Q5^z`t|6c(h2SfS z3pvvbknlDf-sl z7xfK!)|XXuUC8~etrQL9d?^~lmZHIIDY~95MK`de=ti~_4Pi@BCR>VzvZW}CjiO-$ z6b&b!XaoU8*#s1gB%o*%0Y#$;C>ldR(O3eC#t~37o`9kW1QbmqpeTocqDcf4O(viy zmw=)?0*dkpD4Ie*(NqG8rV)Ha{XNxjyFruo%XMZJQeb+FRN%t$Q{>7ik5P|6fI**(Q>vFtzb*h zb8IPE$(Ev3Y$MNzn<;m!eM7YHc2NI=mg0*d}3py+P`ivA&>=rRFC0as7kQ4}PgD2jk0hk&9G0YxqWMbQKl zc?1;25Kt6LKv9^0qBw%D=vc_9)ZHk`u>T>4U!>?E`yDOb^{g+esF>@v=qW|TIbVuO zu%)OZTZ&4trKmJpipsF1s4QEG%CV)WJX?w?uu)WzfTBtS6jdgms0sl^R}fH?Oh8dp z0*bCApy((1>hMGZM$iW;${s4-iLny{s)DO-w~ zv8AXvTZ&q+rRZ9=6t!fds1*T4tqCY|l7OO71Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTA1%iY5_IG?{>+Tmp*n2q?-Y zplAvKMN$)5Z674v?0VLhRW!?WlLko9 zY|fXWIczDqjV(oU*-|u*Ek*O$Qgl08itb=b(Vc85x{HmXy9p?|hk&Ac2`IXcfTH^e zD0+Z^q6GvLJxD;&Lj)8(OhC~i1Qb0=K+!@1iXJ1N=y3vyo*T|5fTE`e zD0-TJqGt%cqFY?2z5x;*XrGqdDn(Q5ebKY7XMI^k%U!qsKq*?m`BL;8TZ&e)rDzpf zik@dn(F<%TTFsWC7uizu5?hMauu=3f0Y$G6P_&kSqE`thdX0dh*9j@mK z^{g+e=%nj@e}feL#`#ioiY-OIv!&=XTZ+!GrRWc~6#dDTqO)u%I>(lx^K2AdAfV_X z0Y#SxDEfLML`0Jq6jE*2q+2>P~;L&6iq;pM?g^w0Y$L{ z6om;WiX)&Xo`9kR0*Vp|zM>PZ6MdsmWPk4(`c;bVun)D9qCM-&Dk>T6*36WmQk*YE zrP)$chAl;9*-})FEk)(oQdEI0MHSgnREaG`mDwn&LO{_K1QaC`P*jzGqALj~x{83J zY6KKjC!nYX0Yxt|p+U4gp2i5KxptKv60IMQH>Sr4vw;K|oPm0*dMp zd_~2hoo)t5c#wT`T_W0lroYZU?XMs0SzlIB<7jt6mJ~JNd?{+mmZD~CDQeD^q84l^ zx|S_PE!k4kiY-O0*;3SojiR;$6tyFus67Ei9SA7uNI+310*X2lP}GHhqOJrKbt9mt zI{`&K2q@}FKv6FOih2`J)Q5ngz62EYBcP~10Yw7{D7ub-qJacoQNw8GAp<0Qi~T0n zNQyStUxy5e_N*_f=*DRGwc%1Ug!82+lPyI<*;16nmZD*7DH_g}q7iH<%4SQ^NVXJ> zVxwp@0Yzg7C>l#Z(KrH%#uHF9fqFbF{f>5Pv}b);MYlz} z7qX>jF6T?pJhl|gXG_uTY$>{fEk$>-rRXlU6y431qI=j&q%y8SS(lx^K2=)z?PzmY$>|LM$umc z6#Y#=(LV$fT_&I?;OS{Qih=|bMG;Ws5Kt5%pvWblD4KvGkAR{W0*Yb@C<+r$6h}Z& zJOM=s1QaC_P?SVKQ85CFiW7WAzePKz43KcXz56*OMJw#1>k^)4eOX0iJhym`6qV(C zDJsX7qVjAhs=$__ifk#W#FnDUY$>Y3mZB@zQk2X_QB?wpt|Xx7DguhC5l~c}fT9`% z6xAf4s1^Z5wFxM?nt-A@1QcCEKv4<-MX3Z7r4dk+PC!ux0Y!BQD5^(5QGEi68W2#_ zkl-sS@wiLBu zOHpgK6t!VXQCqeYwPQSfTB(W6m=$`s0#r_T?r`aMnF+_0*ZPNP}Gxv zqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+bR7Xj0|_V^L_pDC0*bCD_==i%&P)R&e9+8L zQz?4V-WT2AdDfRzG}LpS%9Elj&X=NLY$+PfmZA}CDavL`(MYxwjbcmDXtorMVN20i zHj2g(P&A%^q6q{PO(dWwhk&9<1QbmspeUDsqC5hM@(C!KLO{_}0*a;)P&A!@q8S7f z-9$jq%>)$9B%tUP0*Y=WplB8WMY9RMq9LC1t^pFRWuKO1O3_~Xm$2t}p7muF&G+2H zQ>5s2&X=M)*iv*STZ-;tOVQnIDY}O(Mfb9$=sva--OrYy2iPcDKtR!h1Qb0)K+(el z6g@&f(W3+uEhM1mF#?JnC!pvF0*V$9Q1m1LMT-e2dWwLerwJ%}hJd1H2`E}ZK+#eH zik1;jw48vV6$D?=T+fM_Y7{LoGc-?%2HEdu&v~BpWfi^PxwWTD(Q3|@q8Hgx^b%W& z*081MWwsQ(!j_`7Y$j@~@KtR!(1Qcx~py(|EiZ&5Y z^fm!Sn+Yg-hk&9j1Qcy0py*u!iryojXd3}V+X*OopMatr1QdNhK+%T;6zwGVidK0} z4+A8;&;Gly&r6a0zr_pf@;vLyD*D88b8eENPdQ(TK4VMK=WHq3!qJ3->?I)n<8v=^HC7|d40YwK1DEf|oqC*4}eNRBq4+In)CZOm?0*a0h zQ1lZ4MMnuJ`k8>DV+0iaLO{`R0*X!$Q1mMSMJEX;`iaE2`GvppvWPhC`3S!OF&UH0Yx4GMKJ^v#S%~yCZH&efTDN;iV_GYN+h5t ziGZSF1QZn~pr`}^MI{L+Dn;-Wo%Wpl21vM){flX5q^P1LRXWDAzO171G47>XrKkeu zOHoC(6jfqNQDwFiRbflf6>KR=W=m03wiI2-mZGcJD5^$4QFQ`}Y7kIVlYpXH1QgXK zpy+A>is}$hbPWMTDFhUy5>S*zKv6mYMHvJX)g_>)9sx!52`FknKv6>iiW(76)R=&x zCInwm*%&8zmQmE%{w3LRG5$0CUG~v+(-_bCvWl*aaa+%kqL!R5MXlIU)S4|tZP-%O zmMul?*izJP$dU7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl} z0*d+)P}GlrqW%OF4IrTCIs%FY5>PaVfTFDGXX_2 z2`IXSfTCLoD4In;(QE>W<`7VH8v#Xg3BIDN80SR;B)r1@{i0z~wAGTD7vou9R?(d? z?nm>b=q}EeqPy8rbPrpK?qy5SeQYVZpDjfXu%&1LTZ$fJOVLAY6g^Bp(IW&DJxV~) zLIR2&BcSMU0*am>plA^RMNbk?w3vXRrwAx|nt-Bb2q=1%fTAS?6fGs7Xc+-T%Lyo2 zK|s-S1Qe|#plB7rS9E)fbJ_q2uL&ABcSz9|OX~R;&-${8UW#!`-YG?EIA4lhW=qj4 zY$;mHmZDeLQuG>Iie6_+(Hm?jTE~{6^=uSvAfV_?0*W>gQ1li7MVkmHdYgcv%>)#^ zLqO3M0*ba0Q1mVVMeh+%w2gqG?F1CPPe9QQ0*XE$py)#aigprEw2OeE-2@bUMDP`@ zj&T|rAmJWnhF+AS;`Te*$1$GuWfgrM;|{u8iuQ266n(*#qP=V>`jRb0U$Ld=Yqk{a zV@uI~wiJECmZERjC^|qu(Ln-=z9XRM5CKKs6HxR60Y!%iDEg6rq9X(p{X{^~Q38s7 zCZOmT0Y$$MP;{Jtq7wuZ{YpU5Ndk&~BcSLM0Y$$PP;{E$EBZ9XxzzwMcRmKrXHvAp z{vi8IjAwmWMdxDNXYQ4v^PDe57uZsCku61+*i!TtTZ;Z>OVK}UDZ0#-qCl*kw@Xow zjiM+5iW~xpLIf1K1QbORP~;I%6hlB!ECEGf0*c}YD2gYbD1m^YL;{ME2q-E>Kv8i5 zib@brRFZ(AQUny0CZMPc0YzmAzM?;4oNWe3c#^&QIV(k;9pz#@>&q&t6zd+jUy3So zz7$nqOVJfs8WK>{h=8KT1QazPpr|PUMa>8( zYEJMKRfu)M4;V$Y?E~tHvHmmt8zWEHVm<52Drz0;)_G8h+Hk%UwPj0DJGK8B zwiI<_OHn7b6m@1xQ5Uupb!DTd8v#Y#2`K78Kv7Quih2=H)SG~!J_Ho?C7`Gu0Y&`@ zC>lUO(RBnA4J4pw5CKJl2`IXrfT9}+D7uk=q9FtnWfD*{lz^fvg0HA$tkcT?2@kY) zKdq!_o%seA8W!tWUsln`Sa|Xe?Wb#<8VnJX?w;u%&1sTZ(en zQZ$K;qR9jlK+zHcik1>kw2XkFsqJ3;B+Rv7v zZ`e}wEnA8Xu%+lATZ+D8qv#L;Mc)%p^aBA!hY2Y9k$|Ej1Qh*5K+#bGihd@b=okS- zzYtJ#oPeSe1Qh*BK+#D8ihd)Y=oA4(zY|b&nt-A+1Qh*2K+&HBU(udeXS4wl?r!0H zAw^^DuV&B2de)a!bTQVwYq1nv;(RIki!DWev!&=CwiI1vOHm-KXYNuIWJ^<Z$aE z6ouF*atSDkCZNb8peTlbqF4fo!UPn>5l|FQKv4n#MTrCyB@s|mjDVuz1QeAZpr|AP zMWqNRDosF983KyR5>Ql*fTHpQ6jdPjiq6M6YYdR^clL471u06gqhi>zzO14v!tN(e zOHnfCOHoy}6kW-dqN~_aRE;e~)!9;1gDpih*-})CEk(82D7u<}qB;Z=T|+=o3IRo_ z1QewaP?SzUQ3e4;bqOe{M?g`10*V?CP}GosqDBN1H71~_2?0e-2`FktKv8o7idqm* zbS(izEeXD&%3PV8SfTI2c6b&Gt=sE(5 z1`<#-h=8KO1QcCQK+z2Z6x~Qb(GUWPG6^UeNl;c(FlUCs7=^uYJi08 zf2ko|lutm>6atE-5>PaafTHOH6wM%@=q3V+ZYH2;CILma5Kwe00Y$S2D4I<`(HsJb zZX=**E&)aJ2q>CQK+)|46x~5U(VYYo-9_*fjS4%n4Uq5vd-pS1iq_c&Nq2`m>&q&- zKkP19Aw>^xz7#EBOVNXDDSC)4MGv#3=n=LQJ<67%g={H$j4efvvr+T}0Y!@lD0-5B zqQwLhJw-s#(*zVfLqO591QabHplB%pMau{%T24UG3Id9rBcNy{0Y$3_D0-fNq8A7# zT1`OFiv$$CL_pCRg0JY_u=BnF5>gbyMXz(d6urTg zqIGO3TF;iE4QwfTlPyIX*;4ctTZ%TZrRZ%oiZ&Ba^bP?uHNWIR0Y#q^P_&2O zD_R?N;#V0(7cHDurD%2J30v5+zO16J!*0q8QnZirrD#7}ioRh>(YI_VI>45qgKR1K zjx9xp*i!U8TZ(>Qqv$XJML!ZybcBGSp9m;AN0^L|FIqTXNzr-x z!=npf&-${8{tml&FG|rroG(R}*-{jU(=&G|3bLgriY-MBTZ%$#DRS9T6wQ_*kBy=j z0*Yb@C<+r$6h}Z&JOM=s1QaC_P?SVKQ85CFiW5*&f`Fou1QeAbpr|wfMP&#mDoa37 zIRc8x6HruvfTD^76jdUis4~G2`FksKv8P~ zirNr-Magl_K?5Yb%lx)R%ywegqWtC!lBm0Y%plP&AN$qCo@{4JM%I zdIE}WAfV_*0*ZzZP?SkP(NF@4vIr;|MnKVU0*XcuP?SwT(MSS{MiG2P?cw}nQ>dDfRzG(OI4|C$s{;Cv~X$d;lUwiHcbOVMPu6y>s|D32{g`D`hg z!j__`Y!po+plCV)MKcH}x`}|In+YhINkGvp1Qgv$K+!A$ie?i~G>3qq+XyI{OF+>) z0*dAnP;@&1MRyQTbSD8tcM(u@HvvWW5Kwe4!B;dk&KYZfgwNYw=wiG?dM$uvdik>2% z=xG9qo*|&oL3Bx@FaU*v_Oh}wU4e}jq|K8t7u)E``LOaTF?1X zw1F)}Z?dImBU_5zVoT8`wiLb1mZHsUDSC%3MO)Y?+Dbsty95-yM?ldw0*ba1Q1m_l zMLP&6`hb9<4+$vRNkGvq0*ZDMQ1lT2MIRGT^a%k)pAt~?839F~6Hv5=fTAx5DB4Rv z(U$~Y(d%)}Spy{ewuSSC6fKNAVT<#uFRSRAIJfLZDf*W4rRV@#iVm`+=sUI)9b!w- z_iQQpfh|Rc*;4c)TZ)dbQS=i5MMnuJ`k8>DV+0iaLO{`R0*X!$Q1mMSMJEX;`i+31 zQv?+KPC(IV0*cNMQ1k}@MSl`dbe4dka|9HfC!pv80Yw)HD7r-O743_2nj0YDnf71J z-!DZ!SWKv8i5ib@brRFZ(AQUny0CZMPc0YzmAC@M!lQF#K2 zDiBaqk$|E~1Qb;!pr{G~MOP3|luYmy{S)WhW`Kmx+W%(AWhts_-WIAF?^$0~QT2Ft z*=8xK!TC~DlPyKH*iuxREk#$erKk>DimqWxQ3_j%QrS|J#zs*(0Yw=E6xAi5s2%}D z^$93yKtNGL0*V?DP}G=!q9z0sH6@^^839Gj2`FkoK+&}X6tyIvs1*T4tqCY}P=h^$BYVrOv{SWNu5bs%ER#BID_t+LG>dN_2)Qv4g-Puyq zgDpip*;3StEk(WAQq+enMSa;))Q^p#{sa^aAfV_v0*VF_P&9~uqQL|dT~9#K4FnY3 zNI=mL0*W#TC>lyYQ5FG3!w4uEPC(HJ0*bN;C>lvX(I^6nMiWpphJd261Yc37cqehI zQRLd6I(C*K`yZSMjf?lJFRLgg-c5T?iY9Ts6isGJQ7&7G^4L<8&z7PoY$=+`mZE8F zDVolfq8V%y-9$jq%>)$9B%tUP0*Y=WplB8WMY9PgnnOU*Z3Gm}C7@^?0Y&o(D7u}1 zqB{sEx|4vSy9g+{n}DKw2q?OjfTH^dD7v43q6Y}Rq6zU%KLaG(&OV@?C`AM8SP<`7 zUslm0@$QuEQuHY2OVL8M6g|e4qQ}`%^aNXq7O|!1NwyR%W=qjiY$ECZOme0*XE+py(3f@oXtd zV52CJfTAPOHm42ic;B9l*X2#bhZ>_u%)Oj8%6a9D5_6DQ3C>s z8WK>{h=8KT1QazPpr|PUMa>8(YED2=3j&I+C7`G!0Y$9{C~8eWQ5yn^+7eLIj)0=} z1Qc~3pr|7OMV$z~q8bU#s|HB8wuMtuisJ0Ix6TQk^<@=xPjL5qDn&gwUy6FNrKlHM zih8r9s1I9;`m&{{A6tt0v!!SNTZ*n@qi7%jMS}<^8caaZ^#l~%KtR!r1QZP+peU1o zqM-y7Wf4#`jDVuy1Qd-RpeUPwqLBm?jUu3EGyz3p2q+p$K+!k?ipCRAG=bnN>YCu3 zH$cMG?0r!;DY8E%3QbJ#tS_r5H^D8xM~d<|UyAbCQZ$7vMN`>QG>t7q)7erqgDpij zv8Cu{wiL}|qv#d_if$#KXchrQvk54gLqO4O1Qg9BplBWeMe_+Lx}AWcI|wMclYpYT z2q?OnfTDW{D7u$`qWcIax}Sie2M8!yKtR!h1Qb0)@D)u;aIQ5#!Y_ploXJwu#NHP@ zoZwksR?%Y#ZsuModYtp6=n1wIEn-X2lWZwk%$B03*i!T~TZ*1xOVP7zDO$ot(NY46 zmJv|2oPeSg1Qb0-K+#G9idGR&^gIDYFAz|)nt-Ag2`GArfTA@76unG9(JKTLttFu7 zRRW4$BcSMY0*c-splBTdMe7N^qDK>)c?L*$r~RqpLMa+!A6;)q@T@PZXj6i_;wve7 zoAae;Gh2$@VN1~#wiIn;OVPV*DSD4BMcdd?w4E(Q@3T>~gMgwB2q^lHfTEoQ6zw9Q zXg2{x9}!UWF#$!N5K#0f0Y#q?Q1m$gMSBP+`htL>y#y3}NkGw81QdNuK+!$|iuMyw z^bG+;-x7R98xx$J21t0fz597fik`5)0XdN1SzlJs_X+OteNyxT=S$IHwiNxymZBqU zDf)>mMMv3E^fOzEjRy?*tT`CZOmH0Y!fh zQ1mAOMP~^pI!8d!c>;|l7OO71Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTA1%iY5_! zMLiOo9}JN2X8ZT9drDE1eRMrJ(X+m+qA7{4b6AR|a=sKzV@uI=wiL}^OVLeiDY}_0 zMKjq_bPHRGZe>f+EH;W}6HqjVfTG(7D4I(^(L4f*<`YnKI{`&^5Kwd{0Y!HaP;@r| zMfVU;bT0u#_YqKZKLJG#5Ky#$fT9NpD0+y1qK646dW3+YM+v^7yhNv#0TRxz_eJ?q zbiaLcy)eh__~W+^&u|N88qM9=!NihfLV_a2j?Bb+ZqKe46g zC|intW=qjAwiNxsmZIZqDLTQHqF>okbdrst-v}r=ML^N-1QeYnpy&(%MSl=b^d|vD zX9*}eM?lee0*WpWP;`-iqDur6{Y600-vku>LqO4G0*V4jdfJYnAOS^D1Qa<06om-B zq8}2Siv~#eeGBKX6iv6J+$7KXvWjAp+=?fpD9rg%6vvjLc(xQJu%#%GEk#LeDJsU6 zqT*~RD#4bbl57-}BA}==0Yzm9C@M=pQ8@yN$`epjfqRv{0Yz64P*jb8qUr<`)gYj#CILmY2q>ye@D+JUPAdZ>+}J)8ib?XH=|5{p zU7h4vUsh3SlACo>iqbe=iqhFql);vwx@;+`$Cje{Y$z2ql*b(HH`X#u898j)0=^1QbmmplBiiML7f%O(LLZG66-o1Qg{F zd_}#JoZSXUc(nc5bss6JYVV8klRWFoDw>|;{(4%9W^ld~-Ncrno7qw{lPyKJu%+l$ zwiL}`OVMn$6wP5v(QRxL%_X2{9sx!32`IXqfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C z2q?OrfT9NoC|W>3(SrmOJw!m!!vqvPLO{`@1QabKpy)9IiXJEUil!zxCC(T{^X>1^ zrb*FK*Ni8UJnPFUdMe4S_ooy+&G}OF3|oqxWlPZ#wiGR8OVKj66fI{<(F(Q{J;#=! zm24EPBB1Db0*YQBplCG#MK2Oi^b!F@YX~TMnSi2K2q;=hK+&rN6um}3(dz^hy+J_H zIs%H;6Hv5)fTA}EDB4Is(OU!*Z6cuPZGx}p$s}i>0TQln?~4{oQM~<*wmHeOzO15m zliV5Sr06})m!fTKDca7KqW9TSw1X{0AF!q9L$(y{WJ}R5wiNAVqv#_7iasWw=o12p zJ|&>&GXjb}C!lB#0YzUBP_&nTqAv+3`ig*}uL&sHM?lej0*byNpy*oyiVhG^bdZ3e z?+7S5L_pE^1Qh*1@D*)Ia-KFo!aeQNvaM2-XnzEGILWiVtfHey?mHKx=x5HCqGN0+ z`h_h;$JtVJf-ObAvZd%GTZ(>TOVKH|6#dRd(P;vT&Ja-a2LVNY5>RxOfTD8*6rCra z=mG&n7YQi3L_pDB1Qh*EK+!)06kR5uC{RpK+ffuGpeTxfB8PyY5CKIl0Y%XS6nO++ z(UBzQM*}3>%6=33Ns5B@z9^=cXMI^k@x@&CFDXjkd?`v~OHmSAii)wNs5o1SO0cD< zBwLC~v8AXqTZ+oCQB;(If(jCKFIJg@B^72`HLMK+!Y;il!4#R7^n83<8Q~5>Qk^Kv5|HMP&pO%_5*^ zHX&3rBH=&ifW&*)m(E5?Q5Acne@-H1zD&`%iQt_SDVopuQgj|$iq2P;?~$MOP6}bTt7*YX~S>OF+>z1Qe|!py*mcsAz7&|JwnHd-l2O zc~Z2(Zj06@V&=;f-Ixd(x_=HLd0VuB^QGt}wiMmWmZFVpDY}I%MYpo0=r*<#ZDLE& z?QAK!gN>p)2`Ji3K+# z4--)I2mwWp5>WIQ0Y%#gD0-ZLq9+I_dXj*m?SxR#^$EX+0}`)eH$OK>(J*_A_EaKf zzD&{1L@+KUMbC1+6g|h5qUYIC^a5LoUSvzrOKd6H#g?L%*;4chTZ&#~qv$mPie4w6 z=nVpj-Xx%CHvvU&5m59t0Y&c+Q1mVVMSBP+dXIpj_X#N4OF+>F1QdNpK+#786zwCR z=wkwkJ|Up!Qv!-UBcSMWLa6AOgny9(5`WPimhF(Do9*897m1kpGDY7cg4@%j=v&U0 zqVL#J^gUaOeqc+{k8CO0&z7Q}*i!T}TZ(>ROVO`v6#Yg((E$RAekY*lAOS^x5K#0d z0Y!fiQ1mweMgI^`^e+KLhX^S0vh}bXMG*puQV1yW2`GvZP!teQluAHRjDVsv0*cZJ zD2fw8MPDWSR~(Rdv76DarRe+Q1Gem#`7%XW*};z)Qk39)DavL`Q8l&{RcA|44Ym~3 zWJ^&kwiMN7OHm!R6xC&;s2%}D^$93yKtNGL0*V?DP;>+VML7f%H720wNCJwEBA}=V z0Yyg>P;?9dMaL3Q)Rcgt;|M4^o`9le1QazVpr{1_MJ)*^$|Zz~s$}~$GM%Em_F2cO z+2JGowRT&SmmM=-rl?JJ(6*`+wdH&%YR8tM_G~HYz?PzpY$@u*mZB5bQq-9(MP1lZ zbRru?T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`K7EK+#DA6!j;d=wt$l1`tp* zkbt5=1QZP>plApIMMDWF8b(0TZ~}@(5JE+*vi;K?kofI(SE#iV)wO%qBeP@X%M_iK z9h{qxqSHBFiq2q5(P*|5oynG>v)EEpz?PyhY$+;aOVL=i6pdq}XgmQ$MFbR0AfRX> z0Y#GtD4I+_(G&uT&L*H}Dgi~)2q>CPKv6LPMKcH}nn^%W2?0f=1QeAKP&A8xqS*u# zokKv;90H2w5<*3%X8SifAn~W|wrG?Too^q}=4Hpsmnk|wJ9w&^6fNLe zTFjQBC2T2L%9f&KY$>{cEkzfyrRX9yiY_LgXgL8zmk?02f`Fn+2`E}gK+$Cc6s;nl z=yC#zt{|XjH33Ce5>Rv%0Yz66P_%}CqO}ART|+?8Is%HWC7@_M0Y%plP;@;ZR5U-^ z|H1)@H?fkoYV1S;w2CsMKzY zc4WuQmnnKaI~Z77ieBJ+DSDADMK7_XXct?GUS>|k|W zDf)r)rRYbt6zykA(NAnC`k5_7zp$m~SGE-W#+IT3Y$^JkjiQ4D6#YR!(Vqkq{Y600 z-vku>LqO5L1QZ=2pvbGHhwUhe5KxptK#@;CQIvq9fPkV@0*Yb;6r~YRlukfVoPeSX z0*W#TD5^pT6@8oSKkR_Sx7uydcT!Z&iPVQgDpih*-})C zEk(82QdEa6MRnOyRF5r1_1RL?fQ_Pt1QazQpy&t!igE}jYD_@UkpvVSML|sE{p1W7$$Pjx9yw*-})*mZAx46ipCEK+#+RislhebS?o!^9iA%)2sQ*9gujT{mqawq^N~`qwIOrV&=;fEvgpWd88CA z=6oqy!j__?Y$;mCmZA&TQgk6(iY{VH(Zy^jTF#cDOV}t{K|s-^1Qe|#py)CJidGR& zbU6VT|BfTHUND7v12q8kV( zx{-jQ4TMn9f@=P24oLh9H=_%s=tmnjRg0M~ud0_4Ju1EaF%d88Huoi4FY5&Zm-Vgt zG-X;=758W^Gb`8KHBV#>t>Sq#vaZVVygFI$XM0|Qtj0AwFDGkaEzfI`bypqFYnt^- zJf>?QHCM9kMc-cwXnMp~rY$x2!cyJ+D{R2giF}zpSHLc;0}l z$+@04Bc&l{2TTWil7m32Zp&l{b!sDtN?$$GAn=Z(**(#7*8WexA@c~i5l>F#+m zvOenRd1YBg_wl?rS!eh2y!l!8_V>JnS-%hPyro%P27BH`Sxbg`-ioXjhI`(stgKT! z@5-!^qdaeI*0ra5-ukSMM|<9lS;rQ5-o~tHg`T%5>;7?`w>j&NBG0=gtLr4s+nTj( ziswC?_0m+&+m@AG?0MU>PMzs_JF>1T^}Oe^KAq)xyRwdRKN91$tm1i|w>#^B`JVS~ z)?ep)-rlV4i#%^%)`d$v@3X9zmwDb-S=BG{yzjD3Tkd)Lvu;@7dB0|TzS8p!W;MIq z^ZriET)cfkNnE_%T?diGtJk|LA(E)M!CecH#2Gic zt09uuaErShA_@Cx_Dv!Q`*Gw=BMJL?(#<0Y`+>lDk%aw3*EW%a{YcIZk%awB#mJy#NW%Wg?!%FU{hiBgk%axFx$TjJ{jH}Rk%axV zmFFV~`+EnwA_@D#@oSNUedTX=Bw=5=c{h@<&%N)BB!dNnUfT&8 zr`qVOG0fg%7mY*i4|e24jY7LzT{R}yCFmB88dKb`3;C0~F{l|C5@fb>zq}ewcQU6P zdsx0e`G~{wmCEf7&-W=0JUnk#9)Eatq>^v)+{3f;lgw8fp567E%(ow&?em!S+u442 zwhx__-#I)tSN`Gf+(S8VXH;19RLRK9uFg~hl1~Jlm#yE4-bl5Uk*;;Q5XaWdj#NwSR%cC*y7m^Ux2bgT z8n{gTTU$=S2#7dbW&kSQEo}m^rF(j(%hm}1*K)P#!oKJEh{dbI&MFJpKRoi%~kawDNmm;-uW}CF5sJo?hIuxTL5>`TJr{SxNF;623=< zloU^K@AJ~!;WG+L&h9g7dcg?ydzm<7>a5a&VcpveZ2P})HO($8E3)^N=Y?1Fgjv(a z<>lqK9A^{?#urT}oHezqplt4pqSBU=Oqjd6#!sGJ=7ziR9^SKefxDRFdKOQcRy^G` zrwTBW?Nx`#b03s~q)xweBnYbiPrrglsy{IjRP*cSG|xRE2vT!{YN_so^5c>2Zd{~h zkYR_cAjb~w`N^5%UaXb9cz*N7LC#S@wfZhJ{*Uu{egAJ>Pi|1%y?AcWIPdV+)i|hr z*k#H)>@qd3e3@D%FH_Cb$Z0|K7Rld+d%Da2@U-4m^@hn841eGMi?2KR8>!x)(kthk z@xS&)+Q^$#xy|l5INBx^r?~oA7zPd+KHK-3w11P+UAC-y7I{R6)-{BU**8yBDXlEq{CM zNv$j1ZmaUQ+q2TE)CFwC3GK>Xs$=pp&6-|1dE)e<@j32KUGmNK)aAr+6u7fnw<-u<7Z8qHaC1tdf7I- z;qD6U%P)X?hnBzQ@;B0kx6!NOo#EaEdO>%Q!*`>5E#VWDE<$@wb??07Gu=B@=d~?= zW$yCuMqBCSTUT6;p5;ngMSQGS{1k7@FSx>sDdURY?Y=au8&jpuhLe^vPv{_p~q{0flnccC{8l5!62 z79n{7@+)-ZJ6>VSa=(f2Jf5(tC3$O9an-sTC|#6%cUgEczv4Yo z=?ZSI)438tJN61YRJ^;~J2QM6t$1SUY;rcuK_;&GnGqL%(;fg^uNy z*S&vraVu`8xQg0VT%PdiPyVheuJQazS9ztYx}Ccq6%M(T%SVho+g_17mcOHvxZ2$9 zi=NfG{9WkY5xjWC70-3bRa$;Ec5v^%;&QAN*9jj3?3P2X&Yi<6b^^n9p?kB*C)|62 z=apY1_qJTKdrBkRy(qmrC%Wq+S?o$qerO3lqVz65+g$^CjTM)G>)5@A^t|%x(p?4N zTd1(%ZZq6VC0}{+S?;>kS?(5JPnG{hoV)ORccW>yUM1msB|kjq!(D}j{0a``0xJ}_ zkEHJPmrg1!DJ%cr<*;!n!YjS}`Y!)4>;9M|U&OAHq#*a+2%o4#pyDdeuei?hE3R~| zk$iVylP9~6!^tD>@qFhue65wP(2DENy>Y#7^4&d$@CDtUPd!ooF3bQWy6? zXm*Dd(^^h*52c!oFP+hB!i=026LVS&Zk5x*-FNRY&Ru{O6Q&iFmKIJdYB9BF`oywH zUGiKC?`E{HYuzn-AW$~BczTOc_ZY+-OI;gZSXNlR!*_-IP#r!|K{mg_ta1FGKDvY~ zD}4kkx9998UuVT#Hq&VDaeuGk?w-5j2&VAQgk9Kj)!bFAxEELH zP8|0XEAFxJ$HVT#h3_V@4DYQa-w$>dQTG~?zu)lBVEOxiKXc`>fo*pc&n~|i$$ZmfzVczh77B&r-#oh>Ck{Bn@t0tC2m-@?6Rz|$;9o@4E?XwtOB-cF|bZ9ZK<-qPI4f0a6V*}Iucv`h+ zjY!Q%ZNE;WZlqqMexyO9QOc2#mi9@S|M*ooMZKR6RerW_592HS^7Tm~l5daVEB*4_ zBlzq}+diG-zW(7pp-rs#^pX|dbDyZK^vn0$=j$r{@;&#pl}f*S`?kwUzkJVqy`|DG z-^;4B?DZdhX?!p7AJ4Duxlbb|f0y!s`Qd&}N3Tt|tLWIrU7_~!!*yKIA>7yK_(rF2f23m_ zcg5SwAFbnAUBi90jvKp&`(7Qt=^5_dbcS^XA)p5+Ia8J|m*3-j%zmDIH4)-5AwkimBR~_dRhI^Tg zPdMoI{&-2p=!9@*>)3x%xKGt_)s%2wr{mjG!~Lm_4T{5koQ`8>hPznDO{L*}K*t|u zh5IiZ+sp}fcOB==3-^UOZl53Smvu~C5bo+a4pNtOOxG&c6>8ry1s*Y)E!(CIyLF>YOhK^UR z5BCNg-@88CU+S2%A>1u=oN#lvOLg3QOSm7=@#ovZeMrX+cZ9pQj^}R<_a!>+a5v!Q z;dLG3_lCQ+jzjJb_nA6g{Xn>H)^YDc;r?33BOeWSu8xzog?pBcTb>B_V>@u5cIVxb~HB-=gD(uZ8JQA2qA>#&!ejsAE(2RS(;3b(|gx_qjT5 zbzhvf=Rc+6pYE&lwqx!NgB`oMFW1{~ppF-~FZJ49t>Z5D1$^6kbgbsSl5hJ69Y?t@ z>Dw;S@p|{QecN~H_?i16zwMuNJl=iH*mipzXXJ$YJRKiAGThJT*uZ@O-Cq7U9rNrM zcwSfS0Xm+h;{+W`bzG?9r8=(D@irZ|>iCq7uju%`9o^gcS;utuwQSotI=0twkd8$< z&ew6Zj(6zzl#cJ}_@j=g?v9$h-iA81(XpQ$-S2yVj;VHkD9wHS*N*Px?Ux44Ryfuj%SyuIB%X2)|I56V_ITTCIkvRaYw12i(9&Yd z!|%2x`*{0Yv-<@9gkpC}^6A2{V@rx=hi9pj*!^3*qA>lRWvYFtRIkEa60hYr_jSD@ z_hpAlZ)QSC;WYO`-G>cqSy)z9GI{K*GWTl#-~MuUz1*J`_qBYT;O^QS_RGDilD`_e z|J%#?;k3I#hyAkW*{@^Wf9_rXe|@<;_cH(ab}N55+^#G8)!hB(?w)$x+<*3Km%Ed` z&>ii%vzM{|?Cte)|8W`Iliu@gjC3CO#Z$dpsQmf{bd7kMT(H+??*m@n2=_GSxF@}a z$4A`XL9(a9Up(pVsvP!mbKPIR&C$!)ftMTWp050Mf9)4Z`n0!eowqx;(mC!)?;7{| z%rU=seY0Gs{Q9CNRlGiXM91s9#68V9_Bw8NuWye%Q@?oLg>F}VeKp+cv-hiAKKDnf z{PnGIPun?m{n@X@c@Zx!Gkn_qZ_l&;ZqkvLyRUP^>+c%Bc)7b>u&4R;w|hCe&iTbf zz0-xtm#;yk-*2{i9>3ph?rCRq2In{J67f1Q+>y6sM{L`($Gewvzm?=;IbNT=-|cN; z-d^rX=dXi3pzMooSY7A^V_>;xnE=A3wjUe6aKA`@D)egBTQbe6?>n!UqKuDzk6P7ua?*Q=bqW! z4h${nc3@f084nB?(0I&_gVDx24sOibeK4BuHT&zm!TU$&9s2#>Lw+B7YR5q@|NpkS z9oX5k<3RV45qmvv{nyvC^RUl>~yd1?f?4vo;~dK z{r6R4fa{U}@4v5TfBQXEpLA{H@7;rc-9G%y!WoZyiCW!;y4#V^VKnlG`$Lg=wOef} z>v8Yylt}6Xd)ypJD~r2BO7KI>4zUs!{aWsdNf}sYpuJo)NOP~lUu-WmxbB!_iv8f6 zrKGvP$Y6(9OD8EB4eYamDbd*L?nV3z_u_u@>fP<>JKdZ1^J>^lRB)M{A4%Qh-dJih zdQ4z{nKowsV&Ad)F03Qm%=e;AH5<9v%8MSS+0f0_?x#d(HgL0z7j33l-_5pOw7F(I zH`}>?Xi~GTo9(@5OU*iNcJQLPnzh~R=>Dw=&022eyNi{tUDLL^T&=Wg*mf7JwRUye z?vl09u4da^w6@yWw%uiGr=76vE?j%}CjJZV`cGeNevVFlA5nTQCnMT7cAI+v6LNB3 zf6+QAWPnbUkb#;KGDuTG25U;l5KRdgswpAEG$mxXri6^pl#r2{2suR?A*X61WRx~S zPSZxn>DmZ6LmMHZwGncrHbTzQMo57+LdIw#q);0nW3>@7P8%WPwGmRJjgSf22$`sj zkV)DInXHYFDcT4*TRRkTlK-u{{?l)BH#E`yp^)M37AiV5W^zo(jKKa9ep1Lxohl(E zni5i~DIsN=5;99uLS}19$T^x4GDlNF=4wjFJWYh0tBsKP+6XyM8zJXwBV>U#LKbQx zWRW&P7HcD9i8ex(Y9nNsHbO4YM#zQQ2)RfbAs1^SWVtp%F40EF3T=d3s*RA9+6cK! z8zHN-Lm|`sD()sDy}J8=6Da%LT=JV$j#aa*{F?>TeJ~!t2RPz(?-Z9 zZG_yejgULE5pt(CLN;q7K)kes3+6Z}G8zC=fBjiPGguJAUkX_mcd087FuV^FWRc(a4 zrj3x-wGr}$HbUOiM#ye$guJDVkhirF@{Tq_-ql9P9&LoYryUA;*dOYy|MY`)-{X-` zNN>AO@_x+Zn2?VG`^K)MkbOE;LO#}%kWVxvf6< z)Rf$uUslE8PF z9!220Oq&oKkSft=O2mKE0f}$5yC;4mRP?>wZ#g;=GhU|XxJY2%Hkwp)Jm*VMGqw~p zXG>8FwiLBwOHnRcit^Y}l+Tu;R%|J1%|=lh0*cxaP}GiqqV@z7bs(UqBLPL72q-#% zfTGR>6m=n>=tKgFx)M;-jew%=1Qhikpr|JSMZE|p>PV8SfTEKKp`v3W zzWZA$Ui?zKDQYT3uNtZTk(l{1MS~)NecN$T(O}M(q9JT48p@WUVQeWH&X%GPY$+Pa zmZDSGQgkX?ibk0ukbJ$txi5clo2Xqyy$YWJ=`jKs{BDf%Q5*gw0HRP-t5OVMX+Df*l(MPIO`=u5T~eZ`id zuh~-c4O@!7WlPa_Y!rP@K+z8b6#Ym*(S8Doej=dgX99|TA)x420*Zbkpy&VrMZXhJ zbdZ3eKL{xLlYpYX2q^lSfTDj0DEgOxqC*4}c`49>Ekzk@DavF^Q5CinRb@+27F&uE zY$?iSqo^7IMb!x?szE?eO#+H)5l~c{fTB7C6xAi5s2%}D^$93yKtNGL0*V?DP;>+V zML7f%H720wNCJwEBA}=V0Yyg>xGg${fTCjwp`swg-{^qEXS%PPM^jV6NBVp0wy0@J z%zT-m<|%>wvrkDyEjV9_TC$}mmn}tkY$?iTOHnJf6t!kcQ5&`twPj0DJ2r~i6HwHF zfTE5B6m=q?=mY|aIulUTg@B?H2`K7HKv6dWinsAzDCpXY$Y$JlMr5GgvBA)sg}0Y%FQD7t`vq6-Nqx`=?HiwP)N zPC(Hm1Qe|xpy*NpidGU(bQu9fs|YB%oPeS$2q;=jK+%;16kSC?(ba@dQCW&V+X0Dp zvQH7slA>*PTeK!6X1+|(wJE`xrc$(?^QGuIwiI2@mZBTjQgkC*iZ-yN=q9!l-OQGv zjch5pg^i+H2`IXafTB$V6x~ih(H#U7-AO>vW&(=tBA{ps0Y!HcP;?IgMfVa=bRPjl z_Y+XGm4KoL2q=1xfTD*8D0-NHqDKfQdX#{o#|WXKYf}7e4oG}e#KBo7MFZ`&Xj@9m ze3_!{DS`d7m&x0rr#N4Vo@PtYGi)i^!Iq+(Y$WIP0Y!fkQ1lN0MgI~|bclc=_cxHQbyuVNin_ZQ zu)lU1A)qLQfFhrOq9_4H0U=cMX^P*^0f~>X+oI2;XupkAKW4s6QQQygpWRK~7G-e0 z6lJods0v$(sR=nr?I8zbhZ?o!Iq-YY$-aE zEk$RsQB*)c(HH`X3JEA0OF+>$0*b~HP*g-f(F6jDCK6CIiGZTX1Qbmnpy+G@il!1! zG>w3w=>!xN6HqjRfTEcM6qOKAR7yZm86i|O%=hcHaf-fhe`hf|T#9zvC$eYxG4o}L z=K6vCv++qq^Eh9M&Sgu{e6|#w$Cje=*;2HCEkz62QnZLIMT^-|w1kbKr34f$BcSL4 z0*Wpqpy(n3iY_LgXgL8zmk?02f`Fn+2`E}gK+$Cc6s;nl=yC#zt{|XjH33Ce5>Rv% z0Yz66P_%}CqO}ART|)>Jo#Xps9FTZ#yDgd{MeXb(+B!dGzD&{eeqcX#AgSmE&X=Ma z*;2HDEk!r6rRZk16m4Wn(JgE#x|JwW)L2PA&HDY{OITG@EgkC`u1^o$?akF7{5+QIo!w397G&$6ZHIkpr%&z7PW z*i!T&TZ&#{OVKX26urzw(JKTLy-GmQYXlU%PC(Hc1QfkVK+$djiryli=xqXu-XWmq zT>^^s5K#0U0Y&c=nn#l{v@F2F9M4GCZOma0*d}6py&_*MP5`7 z+ffuDpeTiaBA$Q0Y#|<6vYTAN+X1dzVQ844oJMYeY*NfDLU8gU8hH5=F1dS zi3av#bCQaxa=sL0v85=%mZEI76jftOQFXQy)nH3eO|}%(VoOnNHj3&HP*j(IqIv`r z)hD2+0Rcq~2`FkrK+zEd6y*?5)R=&xBMB%vih!af1QZ=jK+!P-6dg-IQBwknjw7Jx zcmj%=5m3~efT9+JP*FzIpW}eUPqwdsWJbeB`cK=v>z2`&`7%YVqQN!YrKmOMOHmuP z6t!hbQ9HI2wP#CF2euS-WJ^&ewiKPfmZHvV6m=n>=tKgFx)M;-jew%=1Qhikpr|JS zMZE|p>PV8SfTEKKDC$o@(a8i94IrRsAOS^#2q+p%K+zBaiiQ$UG>i}` z%8U9>I3V#QZbtK^Xs_KC4Ufjmmnk|m8rYBRO5PTY;(RGOjV(o|v!&<^wiJzKOVOEZ zDLRWSMFngr8pD>NLNPabfTHmP6crIrG=YGki3Ai)BA{q80Yy^?C_0;fqNxNF zO(URaIsrw+1Qg96plBumMI{6jl@d@?MnKUl0*Yo6P;?FqN@lf zx|)EZH3Sr`C7|dU0*clVP;@N;Me7NnqIprjzXKA_vcGqIt`vQ4e@*1NXv}<>q7Bi& zer#Y;(M_B$MK`mhXd_#SZedH&t!yc}jV(o+*iv*mTZ-;rOVOQd6m2G;=q>_^wh&Ns zHvvWW5Kwe40Y&!_P;@^5MOz6ddVqkU2MH*8h=8Jp2`GAmfTBkUD0+;5qHP2eJx)N; z69g1JNkGwd0*am@go1T|+DEjfqcQVkik^)I_G2fLik{$Q0Y#|<6vYTAN+X~soq(b^0Yw>vP|?>>zrjGKXr+Bb z`$md>w2x?+LCk!aqC^nbkG)MQ%I172s>YV0>TD^h!Iq+$Y$>Y6mZI8hDXPPkqPlD; zs>eoAeFBOa5Kz>RfTBhO6dgf8Q4Rq`jR`0^l7OP42qZ|8AL;k98>ajqX1+{O z+aRzXo19eCj`O9cJzI)8u%)OYTZ%fdrRW5<6m@1xQ5UupoyeA=u51)_BcP}|0YyCs zDC$W-Q7;0DdJ|C8hk&BK1Qhinpy(t5iuw~!bTR=&0|+P@NI=mb0*VF`P&9;qqM-y7 z4I`jvH~~c?2q+p!2o<#s{7nu>{3yHmX(L59+BhYMnJ-gxdJx!;-A*bxgY%_mG+Td?u*#s1wLqO3S0*dAmP&AJaDjF5| zKR6)qEp}JvG%4C*w?*d$G4o}L76gI)*!HBNg`6)%i`Y`Mm@P$1*iy8VEk(=NQgi`Z ziY{bJ(M4=2x|ofk zpy){ginbF_^b`R_PZLn|3;{(u2%(~z0)L(Z5}##%@A_sbdd@vBx-*EGFH`hF5L|n@ z6urp#QuGpAigvN3=w-GPy~38FSJ_hZ8e589XG_r=Y$ zF9|66ih!c838A9r0)M*$5_dn8!izpHMV;&;+BZSWe3_yjg5cxPQuHI|OVNI|6#c}O zqMzAP^b1>xeq~G1Z)_<#z?P!l*-~_njiNsYDEgCtqQ3|z`kR2Fe+Vf0mw=)}1QdCx zdf1Ml2mwVY1QhuM6h#Rr3J54lC7>uqKv5b2Md<_-#R(|NAfPCdfTAh{6jddJioOf{ z)H9tT`?_oNdnx+N9`|%~s-7AgTOdU>IA4ltvZbgNTZ(G4rKk>Dit4hZs2*F2 z>a(S&0b7b1vQgBCfTAM^D9RzAs4)RWM-otU6ahs|2q-$5fTCjvC_0vaqNW5C9Y;XX z@dOk#BcP}`0YxncC~8SSQ7!>Rc?1;Y6HwHOfTGrfP*HZOKfnQrKWO)^tEGmI^sC#$ z{x+#G^JR)Uqz2OprKlt4OHn7b6rI49qRwn7>cW|%~Ix{u6f1DJZ z#raZHz?PyhY$+;aOVL=i6pdp`(Rj8L6|tpg0$YkEvQadNfTGC+6ip$Z=xhRtrV>yz zjew%*1QZn$P&9*pqL~B~l@L%=Nhxx`_}fTA1oLn&1?* zvOCm^q^MT%0b6R!e3_!#QiHCOq-Yc8OVRCYDY}C#MR&5LXfs=i?qW;P7Pb`K&6c8j z*iv*a8%6gKP;@^5MOz6ddVqkU2MH*8h=8Jp2`GAmfTBkUD0+;5qHP2eJx)N;69g1J zNkGwd0*am@py+7=ik=~$Xa@mBI|(RymVlz?2%(}|QvLA`NZfv;R`gaWnrF8~&!@)B zmnqtn8Z4V4MK5!{6urWhqF32c^cq`=US~_u8*C|hlPyKN*;4ctTZ-Ohqv#z1iryul zXb%BJ?-5Y+J^@902`Ku2fT9lxDEf$iqJ0DueM~^nCj=CINVOVMv^DLTNGqTkt4bdW7Yf3T(KPqq~O#YWNJ1Qh*4K+(Sh6dfX<$cyP= zJBlI%6r~VQuEpeU7qq8I^1X#^Cd6HpWvr?AUy5$Ad)L)sG4o}LYQ=)=VkxT4`BGGeEk$+NQdEyEMfKTI z)POBT4cSuEh%H4&u%#%6jiSZ`6dg%G(NP2xH6ftrXab6kA)x430*aavP;?vtMaL6R z)Qo_l<^&YAAfTuv0Y$k46y*_6lutlWD*}pI6HwHKfTFep6tyFSifY9Cb`D6qr9ING z84DljN9>V)`&i6;nW7V7!KpK)s59qFQ5UupoyeA=u52ml#+IV)Y$@u&mZF|)DeA?R zqTXy2^&z0BF9AjU2q-#m5>Rvs0Y#@0P&A5wqSFW{I-P)`GYFxgjxm3}0}^*XpxXT?J}J7^Zi`08V&=;f zjfn-j@~jj)0=;2`IXOfT9}-DB3_k(M<#t-Aq8yMgod% zA%u#S#Qe0`PSFN8qf4deLA$GcYb<8IOwk>&;J7(bbSLLa(Pp+3-NlxoEo>>en=M86 zu%+l;wiMmRmZJOFQnZzgq6Y{ldXRvkhX^Qon1G^32q=1#fTG6;DB4Cq(c=UZJwZUx zlLQoPC!pvl0*am{py(L_igplCw3C3MX9*~Jj)0=)2`GAjfT9-(p`uMOe~<$b-(%k! zd%F}(vD>1TVlne&ie8Nc#q*@-HO`l!*V$6^23v~WWJ}R*wiLa^mZG=WQuGd6ir!^Q z(H=I6-XoyseFBR15>WI30Yx7YQ1lT2Mf(US`j~*CPY5Xblz^ho2q^lTfTAx5DEg9s zqOS-j`kH{EZwM&*mVlz~2q^lVfTAA=DEg5QDtbBQU+I9v$Jkw=SEOjO-4^YS#mtu} z`ZX3jFkgy(<9sPPz?P!l*-~_nEk%E@rRYz#6#d1PqQBWv^bcE#{$-=+5CKJAnjW^J zC_+F{3IRnv0Yy;)iUIyfKv4}ssOaaI|DFR9pKG6W{6&iD8>yOUG4o}L>ZS#Moi9c8IA4nDv!$p3 zTZ$U8rKk~GijH7QQ4U**8ndP7NVXIm#YRyR0*a0%py(I^ijF0qs3`$O#}QC;JOM?` z2qm|v;RF6rD>z(R>1m&Lg1c zd;*FV5Ky#`fTBeN6fGv8XbB-yRG8*(c0l4Oc2{Vu6g4tZOVeWJ%M@Ld7QDPniZ14S zDO%2!qD$CPw1O=~m$Id3C0mLvV@uI0wiI2?mZB@zC|XTG(Uk-gT}43A)dUo+A)sh2 z0Y%pkP_&MKqH75#T2DaHbp#Y$Pe9QP1Qgv!K+y&Qif$sH=wRv- z0Y#e#p`r`Y{GT0=_?C!+bDS*yKv9B#qHF?+su56B zoq(bm1QgXIpr{rBMYRc`qTkZ|9S%r*hTZ%ekfNB4I_WXvf*nNxH@s)JKMJ$$79sEsb^G4o}Lx~B)tE|;PnoG(Q^*;3StEk(WAQq+enMSa;) z)Q>GiC$XidKU<1UW}|2T0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)I)#9u zQwb;udG4o}LCZq>5S4+`E&X=M|Y$=+|mZB+aDLR`iMN`>QG>t7q)7er~%$A}VY!uBT zps0j^qEZ5i$_OZ$ML^MP0*cNdplA*OMRN%#nnysANQ&%kQuM;~nE5hAm!t;|T_r^; zIA4k`WlPaYwiI2)mZDW`DY~33MOUz;Xf<1ku4GHmRcsVpO+e8a0*clWP;?CeMe7JC zx|V>V^#l}MM?lf_1QgvsK+%l^6m1}&=q3V+ZYH2;BLPLX5Kwe00Y$eFP_&7FqT2~5 zx`TkCI|-qpi_`tR4oJMWo6+S`)Yl&NZ%&VyFH>|+dhpL0DY}>QrRYAk6y493qOEKx zdVnoO53;4`A+{7f%$A}@*i!T;8%2*1P_&JJqQ?m+dV+wWCkZIpPC(I91Qb0@K+!V< z6zw3OXeR+h&k|7d905ho6HxR50YxtoQ1lW3MY{+ndYOQtR|qJ2m4Kqx2%(}a>Hd*x zouaGl6ODIEQKP_(*VAL>%M`tp9`sx%MQ?My6urZiqIcO+w1+K4@3E!meYODB4dz(N6>v{Y*g7F9a0*NHZ`KBtFm{-0zm6=j=S*yKv9B#qHF?+su56Boq(bm1QgXI zpr{rBMYRbiszX3gT>^^g5kf@=)BPFxQ4Z%z zQDe3g9m$rWqu5f^ge^r!v!&=5wiF%9mZGL?DLRggqT>lDYDPd&a{`K55Kz>TfTCOi zit-33$|sl&a(GUWPh7wRTjDVuy1Qd-RplBokMW+x@bSeQwqX;NE zjew%l2`D;)fTGa^6rD*x(OCo(6%bG~hJd0%0*b~GP&AH!qVa@KQIELa$pMMmzf=_M zDMh#2D2m6-mnoVY56-w*il%VB6rIhMqN!{tn#Pu*>1-(~W=qiwwiL}|OHm11ib~li zDkGq176C=G2`D;;fTB4B6wM`|XdVGY=MqpfpMawC2q-$AfT9Hi6fGp6Xb}NLiwP)N zLO{_{0*aOqP;>zSMHdoKbP)kX7ZXB76XX6u2PA&K-TX|FqU!b$ZFxLqzD&`|c(CCX zDY}gFrDzpfiY{kM(G_edTFsWCE7?+X6j@~j zj)0=;2`IXOfT9}-DB3_k(M<#t-Aq8yMgod%A)x410*Y=UplA~TMYj`BbO!-NcM?#v znSi3Z2q@Y@2o+RFJ-^Z;9m9%M_= zLu@H}m@P$*u%+lxwiG?amZEKJDSDiZq9+I_dXj*m?F1A(ML^Nh1Qb0(K+z5YigprE z^eh2I&k<1cJOM>75K#0Y0YxtnP_&DHqL&FMdWC?ZR|zP3jew%p2`GAlfTA}Ep`v@^ ze&!~p=ud-lpA@CpZPD&{%zT-mcjG~eJEUk2=S$IhY$WIR0Y#q^Q1k@>MPCw7^c4X`UlUOD4FN^p5>WIV0Y%>vQ1k-< zML!Zyw4Z>Yp9m=WnSi2S2q^lMfTG_BC^|qu(eDHl9VCQ`-j4gj9FX{_2In0q8fhQi z{)orSmnr%u9+YmDqJKGGiVm@*$ji_pcPWanr6`3hMLt`KqHHM&*iw|rmZBINMQH>S zr4vvTC!i>UfTBzSimDJ$RF#0DECPxW1QcZxP*jb8qUr<`)gYj#CILmY2q>yeKv5k6 zis}+jRF8n7`UDg;AfTurAyo8N++XW}#NV{rqQ9l+YWKWoql}pOGDSyb1dnWyqN6xp zikh&c=xDYS9mAHQW7$&Flr2Tav8CvEwiGpEOHp$+idqm*)RKUrTmp*n2q?-Ypr{oA zMXd=aYC}L#TLOyO5m3~gfT9ir6m=w^s1pH2ClFB7nSi1$1QeY}Kv7o$inU+t(+DU!oq(b< z2q+p&K+%~56rDvtQ2_x(V+bfJB%o+40Y&2oC>l>dQ4s+}69_1pNC*}6&hVSu>lFQC zpLOgbMVGkeMJHv%%$F&eni2HAUy7!2z7$PoOHnafie|8-XeL{VO4w3V%9f%swiL}` zOVMmLiq0XRXbu5Ia|tM#M?lfJ1Qg9Dpy)gTiq0pXXaNC53kfJ%L_pDE0*aOpP_&eQ zqGbdWT|hw5g#;8`L_pES1QabNpy(0;idGOpMN=~TDGo?{qj@~jj)0=; z2`IXOfT9}-DB3_k(M<#t-Aq8yMgod%A)x410*Y=UplA~TMYj`BbO!-NcM?#vnSi3Z z2q@Y@K+)X<6x~BW(Y=IF(PbI_Jq}3xWxFj}B}M)1Biel#G4o}L9?S?{e@KcR;(RH3 zm@P$*u%+lxwiG?amZEKJDSDhOMNhD$=t;H|ZD*tCDFTX~CZOmU0*ZDJP_&bPqGt&x zdX9ji=Lsl!fqli_!EK;nDs zvySgcQCB1NcSg*7nIbPUICGm6MKbkBUW!uKQslFxD9VSfTB(W6rDgoQD*{*x)4xwA^}BR2`K7DKv8!Bih2-G z)RTasUIY~NCWMNP%JiRiK;p02ZBdiV@R9z}nQrvSjF~S})IT%$db<>z%=uC@fGtG> z*-|u!Ek%RbQZ$4uMMK$AG>k1p!`V_af{mh)1QeY@K+&lL6pbRF=rjU~PA8z~3<8Qq z6Hs&}0YzsKP*gxb(HH`X3JEA0OF+>$0*b~HP*g-f(F6jDCK6CIiGZTX1Qbmngo^rQ z`c4MGFWhT1Y_AA_9sQ6Hv5-fTE=Y6fGm5 z=mG+YE+nAnA_9soCZK3J0Y#S(P_%-8qDu)VT1i0BWrR@Cv`l}50}}6Lcc`aJ(J3}o zWyZ{xDY`NmMulsu%&1nTZ*n_OVN6^6kW%bqU+fxx`BYA z8wn`dKtRz=1Qgv&K+#45if$pG=vD%XZX=**69GlH6Hs&q0Y!HbP_&tVqPqwv+Co6l z-2@cfLqO5J1QgvzK+*jK6m2Dhimu4?*Et~ZQ|#|uua=@cHXg`~nJ-iHNM`WZb5isu z=S$IJY$@8tmZHbmQuG8{ik@Uk(RQ{JJ;j!yr`b~U3>!r|2q@Y~K+&@V6g@{k(enfp zy+Aie4q4=rsb0UMHaF4FZbZB%o+F0Yz^SQ1mtdMeh($ z^ezEKdkCSThcf+r4oE!DZhjt?qDJm{(f2ZA=F1d)m>EP~l%kI~UyAmzrRZa}6n(;$ zqEFdU^ch=sQ1mSUMc)xn^gRJZKM+v#BLPMG2`KuB zfTEuXDEftfqF)Ip`i+310|XTPPC(H?0*d}1py*EmivA*?=x+jw{vn{~UqYy8Z>E2Y z0}_whXB|I~qBizO|4?Ske3>G@O3-(g6h*5X{zyMyOHnFYiehXjN@Gh=I$Mh3Y$?iM zOHn3UimI?tRF#0DECPxW1QcZxP*jb8qUr<`)gYj#CILmY2q>yeKv5k6is}+jRF8n7 z`UDjHKg8W67m+|HDRhvcU|*a-QL#5vY}l}iq9P(<<@~<0?<)zO=fBQ*@tk#73wG`+nUa}LCX)oQApu2=2qQ6w?00N2z5>PaV zfTBEtujshy!FwH$q}B$fr4%LGr?>p-5%Xn=hExx~y-SLQa(XEm#+IVtY$+PSmZFht zDH_F=qS0(AI*~0!W7twOmW`ru1Qd-Ypy(t5icTh=XaWI66A36fg@B?W0*WRPP*hAn z(PRRON(d;LLO@X|0Yy^@D4Iq<(R2ceW)M&`lYpXG1Qg9CplA-kS5#O%c*FroT4j$# zgQdv6O%$42Jz~C0(ZcHCdT&cn8K;+`MQkZr%$A}hY$-aGEk#S&Qgj+yik7jZ=ybLe zEoY->1p!585Kwd`0YxhbC|X58(OCo(olQW|Y66PZ5Kwdu0Y&E$P_&kSqVotST1P<9 z`2-ZLC!lBp0Yw)OP;?;yMH>ky+C)InMFd~b{OZ9I9FU|W`>x{xDe7U5MVqTf%$F&; zta`ZU9Vyzv>80p$wiI2#mZB@!Qgjtting+)=xVkUUBi~5YuQq?jg6w~2q?OqfT9}+ zD7uk=qMHaPx|x8YTL>t+m4Kq{1QgvyK+)|46x~5U(VYYo-9ICB?5|GCZOmQ0*YQG zpy)LMie4w6=nVpjb`enYCILln5m59t0Y$qBD0+v0qIU@>dXIpj_X#NafPkVs1QdNp zK+#78U(uu0gD*QENv-YgT|Xv8hwXvsDf*HvMPIR{ z=xeqVeZ!WbZ`o3`k1a*tv8CvHHj4HWQ1k-V8PfT9cnikcHp)PjJb;|RW@P)cx&1Cn%?!3n4MU+KGN+U^Us zl!*Bdcm+E^HKaC7`Gq z0Y%*jDC$8#QBMMjdJ#}`JOM?$2`D;&fTBJG6y*?5)R%ywegqWd5>V8ifT95e6b&Sx zXb=HKc?1;Y6Hrt@Kv5yVSJXNsc$EW^w9~%p*hY%JGE#$6BIe5!4NnO_u~&*laC#{k z$(Eu~Y$+PemZB5cQZ$AwMPu1gG>$Dr66rDmqQ4s+}lL#m( zCZK3C0YxPQ6ip$ZsFZ-BsRR^FBcNzH0Yx(iD4Iz?(JTUrW)n~}hk&BF1Qg99plCk9 zS2Q#w__+g;)WH7U^)M+avS-%|QX=Nd6fI5(2fvV_C7fQ0PGw8cQnnPG#+IUGY$-aO zEk(=OQnZ3CMQ5<3=u9?>RuWLOih!cC2q-$6fTGm|6s;kk=o|uy&LyB|EdfR65m2;_ zfTHsWC|XZI(FOvFE+C-jLIR355>T{>fTD{CDB4Uw(ZvK5T|)2`m8Aq*IUq?F*kjQm zDf-@?U0<3KF<++Wij;8vS5kB(rWIS0Y$G9Q1k`?MY{+ndXs>nw+JYDn}DL-1QfkPK+(Gd6un14(fb4xeLz6b9s-I! zB%tUc0*XE+py(3guO2mAbqAydz@9dMJuQUr5nXBNdKD%$F&u8VxttFGWe5UW$_0QdEsCMb+6-l){#x zC|inRY$-}*OHmqIifXV?RFiqK<4S>cp0!&TJ{_!j_`0Y$@u-mZI)# z6!jpWs3!qMy$C2eo`9m>1QeY>Kv5q8igE}j>PtXTKLUz!2`K7MK+ymKiUtx;G>Cwr zJOYaH2`DNcps0|5qQL|d4I!XtD8X0ME*d=MZd+rV2eh~mnj+*4c~k~ zibivKDLRoYMPt}fG?pzzfTfFw<~?_H0SqNes(v?v-eU#4hjH2lLsDLReQOVKj66rIkNqUCHU zTEUj0GuTpeCR>VDvZZJhTZ+zNqv&h`idGX)w1$A9a|kFpmw=+R1QeY|K+!q^iq0pX zXgvW%8we=6fPkV42`Jh~K+z@wiY_9cXfpvt7ZXr)2?0fy5>Rv*0YzH~zM>`3VA?NE z(Hi?P{;5)QH0;LZ(TMpnMO&lcPQOag)tp|6u3<~jwQMQc#+IV%*iv*oTZ(RAOVN#N zDY}U*MK`libPEARw-Qjaoq(d-2q?OpfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C2q?Or zfT9NoD0+~9qK615dYFKsM+hi-lz^hg2q=1-fTAY|zM?Cm!Ep{qQfGTCx=M;>*k`mS zqY?9Eik^vvPy0=Zp5^pXw397G&#|TGdA1b2z?PyH*;4cpTZ&$0OVKNADSDNSqSpv0 zdYyoxHwY-&ML^M;1QfkRK+)R-6zwLU=p6!z-X);uJpzi}C!pv90*dw!Q1l@IMIRAR z^f3WNpAb;=DFH=$2`KuEfTGU{zM>t`;MERD(lGn7>}e^QW#5AQA{sGYrs$h!_^IEe z=vz)NMf=!N^c`D@zGq9(ezp|-z?PyP*;4cqTZ#^_rRZliiVhM`^a}w+hX^S8m4Kqd z1Qh*7K+zEbihd`c=nn#l{v@F2F9M4GCZOma0*a0jP~^q*Wjl%j1QaC@P!uGfC`3R} zn1G^00*WF8U(r|5;Fk_a(pLK<_O%q9Vvj{tViEIYimJuJ;lHG)I;WSS6t)ya*-{i^ zOHnFYiqhCpRD&%=HQ7>Bi!DX9*(j<*Kv7)+is}(iRG)yN1_Tr}B%r7f0Y!}oC~87L zQ91!dO$jJ!MnF*p0Y%LTC~84K(QyP6wIraZ6#+%92`FkqKv7!)irNu;MM<$>8wVum zg{lrta?Jlq|0(cWW(eVTn^(LU`1Okfs5KxpuKv7=;iuw^yluJNSe*%gI5KuIbfTBSJ6y*_6 zlutlW0RcsY1QZP>plApIMMDWF8b(0TZ~}@(5PU_MvEY0MBx$HU7G+7%AsZuO5%Xn= z#>B##JUfFdFEp0ZOVK#C6pd#~(MfD6I+-m+6WCHTku621u%)PoEk%>qC@LnPXfgps zB?J^rA)u&~fTF1c6ip+bXgUE!GYBY}NkGvo0*Yo6P&9{tqPYYV%_E>_J^@7w2q;=e zKv5Y1MT-b1T1-IE5`wR2bS(Iw1Cn%&{pjpODXMN?>7N>lm@iXwdMx~2f)p+1^is5f zEk$RrrRYqy6s=@S(JHnSoyC@-v)NL#nk_|Z*eE)OfTD8=C|XNE(Rlmnph77H;JJIf(dU(Kb#mMc1*V=z6vk-N2Tj z8`)BH6I+UIW=qj6Y$>{xEk)beD7uY+qT2~5x`TkCI|(Sdi-4lL2`IXUfTDW|D7ue; zqWcLbdVqkU2MH*8h=8Jp2`GAmfTBkUD0+;5qQ?m+dV+wWCkZHeih!aW1YgnBv0y(3 zB&n`F{9GeNciGoyPsbwW%M?8q3ztNs=y^^rMK7?W=tZ^^y~LKHm)TPE3R{X^WlPa( zY$WIN!B_NbEV$MINor}2MLVVFdV6;L zbu41OOwo6-@U2y)=zC5tMf=%O^aERpeq>A0Pi!eVz?Pz)*-~_nEk(burRWeFMZXeI zbeMpm-v}r=LO{{)1Qh*2K+&HB6#Yd&(cc6V{X;;}Q38s*RDIcwq5uI!2?P`c2`CB? zP!uMhD3O4o2mwV^2q>ybKv5FGSM+Tx___mV8RfTH#U6m=k= zD3jnTs-7CGS$iC~ClInk@zr`MlvQi`F%M^7^4R=YAqAr|Xin_9;s2f{~y0fLI z2V07IvZbgOTZ)cnOHpsO6rI3EQ6B<|atJ8uOF&US0*Z18DC$o@(EtL91`<#-h=8Iz z0*dkpC@LVJsE~l7!2}cyA)sg|0Y$?IC>l;c(Fg*HMiNjoih!cg1Yc3d)Zj@DNK&GG zjn+wume{lF6H_DR%M^`I4WAy9qLVni6rIeLq6us%n#h)-Q`k~e#FnB-Y$+;cOVMPu z6qT@1G=+eoQUZ#m5>PaafTHOH6wM%@XeI$gvj`}fO+e8c0*dAmP&AK#qWJ_AEg+z1 zApu2Y1QabIplC4xMN0@MI+cK;r34h6M(`DlO$}b_fFwO*k4598=tKJ!&~ zT}eRERRk1mC7|ePg0E z^Z)@x4-!!H5CKIG6HxRB0Y#4zQ1lo9MUN9u^aKG#PZCh{6ahs$2q=1*fTCvzD0-IQ zE83PCZ0CR^wY9&!f1MQVvd5yGsS)#Kie5|&52+(XFL8P)dYLUnudt=)Rkjqp#+IVj z*;4cdTZ(qErRYtz6urep(c1(R?Ixh;9RiBpC7|d%0*c-zpy&eviuMpt^dSL79}!UW zF#$!N5K#0f0Y!TWDEf?mqR$B^`htL>F9|66ih!c82`Ku8fTC{+zM|(-g9{yyq|fau z{THO@5BIvzzSM~MGDSb6hBw!fq8~ZE6#c}Oq62Ix`k5_72ia2e3tNf~v8Cu&wiF#^ zOVMv^6dfU;=yw8&{ve>}PXdbmBB1DR0*d}2py((8MP8b|Y)4UmfT9Efih=|bg$O7L z6Ht^$Kv9H%qACOwRVAP(iGZSH0*a~;P*k1ZEBZb)_^<<#lxmMf`=w}>eMU=3iz1dQ90$Ymuu%#%6Ek%9VDC$Q*Q7!>R{Rt=PalfTAG;6b&VyXcz%S!wD!FK|s++0*XcvP&Ar=q7w-y8bd(QSc0#p zOIonM1CrF%;B=LuN%mMYE-hldOwok2aH;!0632gzHj&dy(J5>xDq>5~B(@Y4v!!S< zTZ&59QZ$7vMWt*hn#xAeGy;mI6HqjRfTEcM6wM-_Xf^>wa|kG!OF+>)0*dAnP_%%6 zqJ;z$l@U<1h=8KS1QabHpy*Trik1>kbQ%Fg%Lphsoq(d{1YglfX~A_4NK&!=z3Y>u zXq|m}TagwqU#4hPTKKkRQgjxlm!h-TQnZ>aMQhknbPijJ&Sgu{TDBCO$CjdXY$-aQ zjiU7g6m1}&=mG+YE+n96BLPL52q?OUfTGO=6kSX}(Io^FT}nXFWdsy$A)x4T0*bC6 zpy)~himoD{Xe$9lR})Zl4FN^h5>T{_;43;aEx5}8N&4E&&`K%#$;NeQ5%cAxcnP75 zstt|{c+s2Pk8Hi@O9n3bz59u6m1uSM)m*h`rh950i;k%7c{QV#L_M!=^utuoYZz@> z)AQ1!(`tKO^XMIQJ+D>tm-?R9F507!=Ve9DY~p#Hqt7+?C9lvJ#T*W(_GJ66m2ok^Oi*_q_L`f1craA4U7F^1Qv#bIk`wr_{KPXaOfKYNT0#O!~~ zFfI_Ye_MY-AZGtK`lLY2{&njqftdaC#M1*Y`}bvM2V(XQgw7Ad>|c0X6o}bB(YG`Z zvwvf4c_3#0NY=_g%>I?5)q&U(d)+-0h}pk0vOW;Ae<)&OAZGui|HXlr{ioVn0x|n< zZLbQ%>_3*gHW0J_+UHwwTLLlr?@ewG#Oyy9xH}NDzwv#4AZCAM_u)Xy{?6s& zftdZJxgCL+{jH~+ftdZZl@|js`+Enk24ePu<6VK6{p4?VAZ9V)hvPSHMd>}vP% z7wDnaT;|R(&{N|MJ54W*`)wSrG14xwx5iQTfgLzO<4L<-eKe-pHOTQt%{Fe>mHgQ~ z7}N?34_BMuet9+BM`1iyX?aW@sNCe(JX*Qyv3a5LkYn>oeL&?CivI*xfFbZWH?+sohi!kInXJ*>b02 za_x4?6=&ep+2HOI`yFl(O!5M$ffgw>l7lG?QckRs>OLerFQK`YoP2^yo)@g`1ygz^ z_e$=OoL|EU(`%}@6L;~fB-RKdC;M*@a5GZf3s&Lnlas3_S4-~h2vwn!zFDegq!it7=r?yj9(axDHr*z;2Lp6Ei-It2RE z<4Uxwml{Y*%&B`>zj}6wH9A+idJWx~)I9I3fV-WtYuIaRtvf5=CDh&2ude6S<`te- zr-Rq0-tqP3ro_+GU5dL?8@k`_c6PtqCpP`E56H^DD(^w=&4S((cans_pDES7fcxd% z*8L82=#aUvICE;*{LHe2C7BD0%1TO$<}aMLsI+8J>6FZpg{RG5G|xgw>6FC_OUo*~ z&fea=b&t&X3unxkv1rDUQZIA*yg8+r#j{J7W_Fl8ucUZ(X4&-Og{7GbOXrrB6_;g} zb}TAew0O#ld6|pm&6`~^y?Dmlvdn2EB}K&x=VWGQ6?H1=nAI`6C_Bqydl%c!oj13% zeQELJ8SS&PI&^ApukPSpeax#eXUr{`y?9D#=A7b^=`-g3f4>@KrLyH&2+bUS>~wu#S3Q*Ts*gEw0mEs4WGTZtY~E4 zu0y)~H}0k-#fwVq*77|6j-I-BZb?>F#||Y%p=e6!)Z)dn7Zoi!ZGLH4hv_EF-Ca{= z%w6P$d+;8WJD|v2&63=CbLPyO>zY#qm>G7~e)8NWrEpwluu~u$uJJ$p3a2Fo!Zk9( zX_?_bu(U%sEm$u-98Sy(*KpmA_WE#QmU}W6s1;7OLp0pf4z9;%2lwiZ;aZ7-@!=Zn z<0o-1_x>MVw##Xn6|T|f|IK;(XWp>Vng7?{0lW5%-39#DZjto=c!uefZ(_SgI>zsb zK<|X0d*B#3U{KM(tUS+-+1<19iYEIncI{mLVwc?V7rS=XTXybF>&uC=I{U91kgK=J zc5ggm@Vt5Rv%MjG#}(xc9o^AC@BW;mOZnw>BXz2{+>Yg!n_KBDbp<P+?lyv7jesQ_FUfBaV7xx11=793|Bimh>_}lkzZ&p;~PTi?vk$(=^?!q|1 zK+dhN&aGd?Ik;QEz1ft-bLO1ppOfCUGZ)-fpKqyJ%c^+qdX&E>+0L+6IADBH-~J=xr*n6$-bqJTFZDm>l%8Fs^!OkD8?)?+E7DJr z0O#(;_yr)W+>kHUKJ*5}Pd(ExN(nudOx$>JIagM6*qS!J>7I=xrcq2c81+6?hAKM`R`Fj z-n9x@*%h?1E7@{)zkiYnMcm2R{dB`}7xyT?zV6P`)vb6CE{cXIsmmjCH$ zK>4ZNJ)m=}xCY$E?iSMP%I`~e7x*nN_ZAGyV|onQZ4E8U?L_n*6P-8R|o zX^H=a?&DK0l;4Ee{=I8gv(lq{woc*h)ruR~y)Q?JJS2?j1X) zw^~>_yR^8hv~_y>IVJNK_bzd_Sn1OCb2@c$VbS!(b0)jv)Ytm^cIn({i>CL^a>;)V)86iNx9qWN(TsU>+n2d7DcrHlwJF7m zip#fuQ@G~={tFdkvn$LR$N%Y5m(Q}&r`K|O&TjlXE1nOUM!StGo)%U-8O-*9$ECQ3 zdR?uGd&pN_{<$-bx~S;bPweq$qeb>Hs)y|Oxl}wg1(7|O8a8lL`KRw}o{3gGtE_l3 zS@B%bJu3y1|1n`#wp=yOLo1#lR(giW)6j~igM4_{GerMp5=;N7VElHl=bw5?8h?NN zkHPZWfRDLy*}%5vp|i>#26?(!@szOQ86m{W@Bi{AoaN6X%bzq>`dF&?h^TnV$K74= zgs=Q=^q)0)gK~3wrnj<>p1up`qz{-gxpc}D_iTGK-vEezK=Flr>;L(~%YDD1n)`j! z{c_(XS)Ss)edE4SQvS=n-7zR7wmP&Xcuv9v0k3Zl_o`z1&Vd)mbT5Xxw;$4BNZa|2K*K=egl2&b_KlH${i>Wo-p@xXzuJ9GRC&6u zll^bZ5QFxWbERKF_f>OhrETBBaX)i#-?S!Hd`rhl(2IY&l~=m$zDHK+SI~1me( z=-D@jDt-k$_cM-4zk*)0(z5eE_Syu!*uP$1!*k!di@%q48>hMJ+oIB2#NYbg-%V(~ z$ZI~u8+ptJrL+9+=jz9~^GQl`-^JIlpN_+IoU7w<9oOl&MMw8-{rKtKH|^ucJvx4? zqx+V5yxZSIx67%oqx()~eA_LXU_TDBqq~{xmat?~5HXbhPgk+8&_e$?j#_({#MnQLuf7j$gYQ!1gaXwsSCT_t0^n`>~kq zGj)8}eE`~iPRD=h`#ZUTf9&smXlAb;q2szH{=Q7dUG9dp*MF>I?dJZ@&~btTVy~Z} z<8|&1uzi<~-@5Pa+x}I@4(!~A`sju(vZ_mw*C9_8=PbgVzd-z{~VG|u01biC;#f8VF${t5p6UB`|^ z{_dmW(qezF(eX(K-ENOpbPP@PcdCvB)BQbG$Bi@ny;a9|XZ!mL9UIQ`cWWIdFYxy~ z9d9Y~_X9fqxY*x+>ezXyzx(RAY?;5$)p3V=V6p4_nvRKQ`n!gXgID=`yp9*0?eA-J ze1DCFVJ!OdVfEp;{o?GA-nv)b?myy-?=(2-|X-6bbRI#f4`w) zl`a0RrQ^^m{C%>H7hmP?Z949`+TY*kn7+;5?RA`by}!$Jy!}RhKceHooBe%M$L`zx zJwV4ZZuj^3I_|vF-*4)ebdSI5=s5g7e^1o$(g*x~y^bF}G8HF<-~CKJoX3I=;Bq z-|y&{@`b+}=s5Z-e;4a`#W()GS;xKm{QZND$L;rbCmm=1=K_YrT>YEBH|hAY`-!%_fA8rS`^(>rbR6@Kze{wy%026_x4%`#&)rWhZU3ZW zEBBKI+g)^=8}aw)I^OSoAa1XJTE{=!PsVLW+!F#j=C~h`+i{4F=eQq%+TN_=tL}&9 zwm;A@&HeP;b`u@PxgVq3F4ggB_w#hyx9Rw$`@y>HpLJ~GewJ#xn~w9-{k=lR2b=l( zSsfd?A6nbnx7IPsj$zO1qdi#1@j6b`u}sI6I&RSM3LS6O@qQhj*70>6KeVH}oP#=6 zbw5A0ovvdy9f#^zs^fAUH|w}v$ES6CU&o(xOmt7g?0g&P*jdLsJG%FKu#SoLe5i{1 znX4V$+uJWYx~D<$W0^faa@##k@e)$pUn5cXI+UF@XHoHFcU-j4KThW*_ci(=uY-M2 z>~)x2R_1kZU&eQ^*x}fxt?@p^zT51+#XohPJ4yWI;>nX2mM-y6rLxeT-|CF~^uL$c z_Tx#Ng}WwRhZ6U*v{Ltjhe{VSbz$)w_eOn34(U+5XwkwMlNT>?XZwHq%RTjSA1&_Z z=Q@FVYIDplcT>fGHFba5+Xej@e-5q};|F`4{c7ocyPN+1_;y+DZT@|^m45_n_m%x> z=YG4Vr(TZxZNCom4tOiw(e68Y8~bgSm*;+S9o&oVuiUuj)6N6Gc&Wb&mCtYf2?6gG z7wr7(HsJh5yO%kQd(nHXb-?|-AA8CF#f$E#$}w-(+WnQ+biIuoc)Q8&<;s^^H!l$P zX_srA%RQ~qY21rmzB@m2%rDMwu?v;YuT`bHyx^vyG ze16^C`PuDi*Ux=um7m{b?qxfT-GBD$hRlGMRn33d{Bk4+_c@!ZdYcQCuU}53_cztOj`#O*_p&oOpVJR^=hu_rj$D=)tNQ z#aixV&d+XlyG+cx7rlp_zwY*eesO+wn#ylC++Dv{c_Vk^?J9ri+o{96O!p&>uHCab zcJJ6R-F+`3E4$L4UAuNpPw&yaYgSge{hE|?=77Ni{lAIfpK-u_g~|C^$ypI!;m+|_ zxAN+_N46smtj}LRcthcaf^Cz-12^Pv$UFMmKSx)l+n+-Y@5(KiTrzV@!e6^{4hH+4 zTX5Rft^M{w%Yp-@C zmVSC+SwUWjy~R~-2h*1p&eQAd-181s3(kt4-p<)hzo2lMUVnuvIfoOxxrLK;4t9B= z^jU?c=q>Cr?Ho>upMzbVox_yEF?zjSqMgH}!jU=$yUcM-Cl(GJ{LGP1>N7|7X6-%_ z%J$m+x#vLqJx?4sws2g*xcu>XJCAt9c3ar*F@<9b#^#TU-$Gu-utO^oJ}=&RWLNeV zGsY))Kc9Eb$ih+iqY6gHU!U)8yRP{q?)|sxKkU%!qdLW}on7~wgPTTW#&0>h=C<0E zU-N>4PX}AYUuV}klzw+ci-NVq=a+1rF)sYmWzs2W z&lN52m-Ox_ZN@cR&}MGRH}@X+sO@FjFLIxScP;W(`nTo4!_`V|D}Vpo%DuV#wzPFa z{B`!;*}As;wzSi2jla&`J6o3z9W}WuehY3X+){9P{^jv|&hF{Tdt|dMg%=Kf{z$0l z^G9};JMrY?qQcDuoAWO&cj8nm>31-rC zgBcmi3SKNOoHT0s$=+Y@ymiFOUNd;f(2Pm;Qi=VUYA@~Fmr$c@dXamJcaL~Y-S6xb z`8)T8GFZ#+5x#^ozUXt1Dgd1YPnt z|B~aEG@GJYqqwm6n9IE-V|?C#e_d|n_xOZk z-{bh@_HdUQt8}?(|9XE5+~w9RzuZCYa%*P{Djamo<=&dnE3f6hF1PagoBki(-v;h- z>sGql`u}==v)tu2EWh0L?s6Mvv@dLb%;mPpXp~p=Uzc0?{Y{8pZoj?WQ}(fvv7(^& zu;|9sUo_c1e)v7>AI&b=a9_3O=hU2a@zd{(ZP#+i>S|R2r#Gs(>($ZUP3(KcNoOU0 zn=g#8}=X%cFMg5xZS$9iOx0x-T{p7%lcih}= z>JKIvf`uxtvV*|JNLGlM-#sZ?$|#t>9cZa@!S0l_x`6>djFgK>vq4% zz5mV2-~a2~`+r=<^@Z0T^ZvKZxHj*~f4%>eZ}*G;!|i^dyWCclF1O9UZubrDa@&<( z?mBn59WvGxt~=&(n`NApx8h%yTlsch@*kWnaF?4^>2f>%>-{Zrm)p7ga_76t?V2&a zaQ-oun~^akujpTwyQR{{)i_9e+d{%;n4#I(;2L)~Yl zCgqLDt*o#cBtQ^R)r~*K5OS5%otrI z{o;(O1=S|yO?zc>4IZgRH%iYrIBh|&aCh;p$@V$At3HkvZvOJ!>3>8oeeLTtMfbd! zGs!*{e!qO)g9DzKS5W=BFW)FiuU)Uh#3kEW&#%9KP4I=br^W9RJyR-PTDVxB z-+897ApW*I)0i87Yx~@vo<6s5rfz-v{Frli)2ONO*KT!d*r6jQ4m%X8nVw!+Se*Y( z@$O>(`I}t>dyX<8{+4zP+*^)zZ<%UZ#^miTcGC1r#NKXX`7@Ee2RGFi8b6g?7o93L z?9c_H^7GyO>P}S{f4*p^>OZ*9J=458;n`nuPW;2(cC5RE+WiZ^Dehm;KYu{p*YRgz z?sHu53wzEr;)@v*-E*#%XE{^FClq$k^HTrXdBwd7vxeAno>}qF?%fM}6!ggNS^n9* z@*Z~RtjXOATMV9AGRs}Q-Gcr{LT7iLUGlrePc!V$+6A2p8|pIr_hs$;>~igP+YUQ4 zcz)Z$8q)4R2OYe?X&-FYqhzMt!uDCZO4H_rRdr5w%T`HmS{T-SV%I*D-ncLjf5z8i zuYKOAa<86GE%#RLXymPYEpo=~TkmLp>p#m@%v{^z;0e3_^4;Fu`p9GBFB#Zk`r%jC zeqLDbl=TDu${ODLoFiA(y7cA#i$|WZYm2wC&s*PLpIqhl`5S*()Obwm@S+{{+<7*3 zr$69+yXR?Hu?%nXjPdq7Gu`fkA4gr8zcGF<#h-(_d+D%l?fI1(l^By6<*|? z1#SKh_fnC&mm;eQo&U83_LYO(GKB}LWvq@rlGv>>!0BEUR}zN&AVZ@cF-dh8vObGS+^d)pcriw4gtc)j>(_f}84 zx2iJ99#1aUBeeVaAa`26Z_e&P`+A`yeyMivRcSi4aFRZX>>8Tf3311E4f`J6R%2ZG zHOzC5gC~|h4(1=M5*!hKo&WLJWng;zn%B%2F}TpK`M<6;pQ-F)I@dm9xZA|8&!EDb z_<8!4yh;5Fk3Yszmw`F)^G(a>HMq-vINz=Q`#I9yul9K_yYuxQJM5#abwRGX6uW-* zk#^i*^LWKEA8Ab!Tf2|6)&*_y+x&<7@Z^MPPQ&m4%?n!;w8%fsJ=fho+$^tbKI~B4 z*r3CW`lc2(EqM0G{&f3uZ_fM0?&a8?;v-MEufs|k6*ekpoZqfBC*GeJ9-b zPt!lrnr^xJv7FzFzdd!z2Upy6-Vg4Fuid@$NnWqmFK1mB{_?5p;-Tl?)Bl4}{8s7hC{Vl(rduiK4FZJy)Eqln-?E~@eFSzeA1P;1yid6gEeOF*W#7~I?XFxm?Wk>c?Ye8H*mhU1hjw+_?)vrA zuI6?}cl~;4C);+{?|AJb+wS`H)~;&XUB45wtJrqeua9=bw!3~g+KIN^_3Nu0w(YK8 zKkblhcl~m;-QV8m*U??S{@Mv{cXHQnfVTS{UB6E5`VG`}_kYz;sCn=WcmF5dYl>R< z|AIq1=OZ*Ia))~Z6H*v{!+panE@ZGyDj`EOC1j|kgbdS^kl~sVGD1^AMrumPC`}0& zttlZVY9eHeHbTZ~BV?R5LdI(&k1t~Nr}Y9r)4ZG^1T zM#%Zv2wAUkVn>IqO(?-bk z+6cKp8zDDpBjhG+gxsu+kXy77a;r8%wreBgHf@C5u8oj8v=MTrHbU;wM#$aT2)Rca zA@^z{z02ef@5n}c24{hu_|9z!nng}h}iKNvANCgjm@7x$nN7xI`+Dj|<+ zO2`wM67r;`ggm7wAv-iBU|9$hVpjvQHBs-)SS{du@d5*G9+>+6ehk8zDbwBjkWKLVngp z$U$v{{GyGJL)r-WRU09PwGr~0HbRbQBjk5&g#4k6kUzB%@|QM3{?W-PmpS zv^>IYg+mhyQk$T z?AmVI*ELZ>Eeq}%#t1bnxT}~-sA0if$23Bk1$QND5K=9;Ygv;Jv*4~~Eke|SyPmZP zDHhxntwX48!Clk3glaC>S2*a7Z9)iJaMv`Q5VGK|X;Xsxi|6q#b(#?pT(GZoG6(?+?wU3yI3OvZP(mQM!vRTt z&YqqG1HK~D6KWBN7%x-QIuQQM{fIuUs12u=qPA=)YR8tM_G~HYz?Py+wiIQtr6`*% zMIG5v)QOFv&IA;7A)u%$0Y%*iDC$l?Q4a!&dJ<67i-4lz2`K7KK+y>V6!jsXD2ITe zz62EYBcLdkfTI2c6b&GtXdnSag9s?fBcLds;45kw2qvaEMG<=_Y9&Q`jZ{G(V!lk# z&_KAQ`wKB~MZ-9~6b)xf(FnE_jbuyFD7F-hW=qkDY$+PUmZGt2DH_K{(Rc!iP9mV_ zWCDsN5KuIcfTB|fC@LbLXc7TM#RL>hCZMQW<`7Ucm*6WJ90(3}K$7owGc-hsw%KFRyg*_?$N@{uEk#$crD!W# zimql$(KT!-x|S_P+t^Zc9UDd06Hs&m0Yx_wP;?UkMK=>rbPEARw-Qjaoq(d-2q?Op zfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C2q?OrfT9NoD0+~9qK615dYIrVx-<}c-vLQ( zZeM;~CPn$C=#fCge3_yr0^#55OVN{@UW%S#OVJLt6g|zBqG#Ar^ekJ7cCw}DIkpr% z&z7PW*eH6DfTEWOD0-QIqE`qgdX<2p*9a(joq(b@2q@Y`K+&576um`2(c1(R?Ixh; z9RiBpC7|d%0*c-zpy&eviuMpt^dSL79}!UWF~L{#SRmNg{T=b-#`akBxD*Ys&uE_n zBIe5!eI5w+asSO;{ITc@PA^4YvZd%NwiJEMmZERiQuHlbiuSRk=sUI)eb1Jn{cIHd zKtR!t1Qh*5K+ypLihd@b=pX?_zYtJ#h=8JB2`D;DK+$gm6dfU;=yw8&{ve>}PXdbm zBB1DR0*d}2py((8MP5SrSNZ5(vJcy@B8q2PFA^`>!xQlcFc>u_%}jF<+)A zk`P|gM2f0#dMT>PmZBuK6eY8zs2W>}sV8PfT9cnikcHp z)Plfc(QyP6wIuk8!U@6c4oLEN_cQoVVuJsbey%+hwMvMXFH_VmA^b{HDQeH@rKkg2 ziZaYfTDf`6y*|7)SrN&0R$8cB%o*z0Y!NP6y+08R6sycApu2$3BIB> z3BdynNb+^|m3~_(3ffotLlPq9%M^`B2&XoeqLG|libk=eXf#`jPGn2b7`7CRWlPaG zwiJzLOVLSeDLR>rq6q{PO(dY`6atEh2q>CFKv6LPMUx3ADj}d~3IRo>1QbmrplBKa zMbil=nn6I(Oah8#5l}RnfTB4B6wM`|XdVGY^9d+gK=2g}O9*y#K$7$9v1qsy^|8-r z3lk#d%M>k12#-BZicaP9QnZvUMW?Z)Xc=3IPG?Kea<&w$U`x>%Y$-aEEk!HYC|X58 z(OCo(olQW|Y66PZ5Kwdu0Y&E$P_&kSqVotST1P<9`2-ZLC!lBp0Yw)OP;?;yMH>ky z+C)InMFbRWCZOnI0*Wpnpy*P9uV_(1aJd7Le4Bj|TP#Jd*<;aV2@&&UimpruZ*3(- zS8;kN+RB!qtJzX?4O@z?WlPaEwiI2*mZIy~Qgj1bif&}1=q3V+ZYH4U76OWHC7@_K z0Y$eFP;@&1MRyQTbSD8tcM(u@HvvWW5Kwe40Y&!_P;@^5MGp{A^dJF64-ruGFabr6 z5K#0e0Y#4yd_|Wh1fOw0k~an%oGYZLi#--So)9r#rf5e(_=`4D^fafJqG#Ar^ekJ7 zcCw}DIkpr%&z7PW*i!T&TZ&#{OVP`06um+~(W?X$y+%OM>jV_NK|s+i0*c-wpy(|E ziryxmXg2{x?+{S*E&)aF5m59#0Yx7WP_&1Dq7Mlu`iOv{j|nLHgn*(?2`Ji2@D)9o z5UkSHDSFht(tk>d>|gK?eU=b0U#94*gmCNjQuH;am!fajQuHlbiuSRk=sUI)eb1Jn z{cI`vfh|QpvZd%JHi`}qQ1mkaMF$Be`h|d^Lj)B4N;fB@j>)B%mlnKv9_BEBYcK zIMe}2o@9?jUrNyd8;QY)`7%XG!SK9HDN5$_QdEsCMb+6-l){#xC|inRY$-}*OHmqI zifXW>s3sdlwFoGxO+Zl{0*dMqP*jhAqWT0BH6Wmloa6}1lr_c$QQr`S`W4pQ{BJr)fQM$DHf8XXM(*-45{>O=L^aDQpxK5l}RVfTCgoiY60KR6;<}6atD$ z2`HLMK+!Y;il!4#G=qSmnFJKgBA{qC0Y!5ND4I(^(L4f*<`Yn~fPkWf1QeAKP_&5P zD;gOLrgwIVK6QU*F*Hhw9=C5~FAhe`mnk|e81CCuik5MDDLS1kMa$Vzw1O=~XRxK{ zOtuuQWJ}R1wiKPkmZG!SC|XTG(Ha7Z&LN=aTmp*L5>Rv=0Y&QwC_0~jqV)t6Z6KiN z0s@LIB%o*`0Y#e#D7uJ%qRj*pT}(jHB?J^*N{dEk!r7rRXNM z6y400qFdM~x|M*U?F1CvMnKW+1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?lg21Qb0$ zK+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qb0%K+%%~U(r>;;O!1ba+)dHDn<2eJQa+X zFH`hvF#MYPCy(Nac5-?tdX6nc&$FfI1-2Bu$d;m)*i!T|TZ&#`OVO)rDSC~KqSpy1 zdV_$XT?7=pNkGwC1QfkZK+$djiryih=v@Me-XoyseFBO;AfRXu0Yx7YQ1lT2MIRGT z^a%k)pAt~Cmw=+r2q^lTfTAx5zM`jt!GjJ+@=<$2{frbXv&W(@gAwy(ioOkoYq)=> zHm+zNr=qLe2?(cW|U$&ztKtNFf0YyOqib4bw zg$XE1B%mllKv5NfujuPwu)712+}plg{f!izZqKf(h9c(66jcv}$M=z<6izQiQMMGt z*iw|rmZCJa6xCo$QBAfK)nZFgZMGEEVWX%n0Y&u)D5_6DQ3C>s8WK>{h=8KT1QazP zpeUVyqNW5CH6x%XgMgyu1QfL(py)UPidqs-)QW(j)&vx_A)u%&0Y&WyC~8me6(xs) zXE-3q&)H*9wUGan{&stI-60e)U#6&ID11#{DeA=OrKmGoin_3+s4H8Fy0N9GJ6no+ zu%)OcTZ($IrRaDzih2`JbOHfIeF!MZA)u%)0Y&`?D9RqB#T<%_X2{9sx!32`E}XK+!@1 zipmHmT0}t6Vgibm5Kwd~!B=!*D45jWDXMKh0U0Aj*V<#z(on>FnWE*PaNB`Ww1U%1 z(HU$hI+HC$E7?-CiY-NFv8Cv2wiK;qOVJv(6rICH(YXW^ttFu7JOYZ=5m0nK0Y&Qx zDB3_k(FFt)T}VLDMgod95m0my0Y#e$D7u({qDu%Ux|D#T%LpjiLO{{w1QcCCK+%;1 z6kSE|6)g(|hdUt2zuA{%r%TZ%_SZzVh9c(66m1KI7vxFNb(~&`u4hZp4Qwg8ku60x zv8Cu{wiMmMmZDqPQnZ~dMYpk0bUOh>cMwo?Cjmuw5m0nD0Y&!^P;@T=MfVXB)YC%BJaRd~#B%r7j0Y$9|C~8AMQCk9v+7VFHo`9kb1QcZw zP?SaR6{UoO(;blHjrRAhqhbFm{dV@ilpT(kFH_Vd96oP^6m{kFQq+wtMcvs_)PpTW zJ=s#!i!DXRv!$pvTZ&F#OHm&-igE}j>PtXTKLUz!2`K7MK+ymKiUtx;G>CwrJOYaH z2`DNcps0|5qQL|d4I!XtC;>&o2q+p(K+y;SibfJpG>U+t(F7EoNbnVP3J33WK$4T~ z;it0{t+g>G95G*}=%jG?jZso`GN+fK32Z5v$d;m0*iux)mZC{)DJo`5(PXw1m9V8~ z3L8bG1QbmrplBKaMbil=nn6I(Oah8#5l}RnfTB4B6wM`|XdVGY^9d+gKtRz#0*cBA zC|X27(P9FMmJm>MDgi}H2`D;^fTCptU(vX5@Q?$NeAu1}jhCWJ?Xl?eaKwC>qBFzc zT4SVWC8w97Rct9bi!DWGv!!S?TZ-1OrRW^C6rIbKqP1)(I**N_bp#ZhPe9Rn0*W>e zP;>zSMHdoKw2^?KO#~EOL_pDI0*Wpspy(0;iY_If=rRI|wh&NsIRQmi5Kwd_0Yz64 zP_&hRqN@ogx`yB@S`iNRbU>2F*_UN!NYN|ySafYTV!lk#4dL*~F9|66ih!c82`Ku8fTC{+DB4Hx6}=D+KJS1eyZ<$z z7kW{On%QTx@4^xDWr}_bhrgL1ML%(RDLTNGqMzAPbdW7Yzp$m~5L=3VWlPavwiNxw zmZBqU6#Y&>(H{g9{YgO4Uj!8WO+e8<1QZ=5pvX(qm+dGD5KxprKv9r@q7VT^VFHR0 z2`GvXP*jD0qN)TGB@s}ROh8dJ0*a~=P?SRO73~iPt4(x@?B}kbAEfA2`?5cp7%^X_ zs77MAeUTK^fDg1QazPpeUVy zqNW5CH6x%XgMgyu1QfL(py)UPidqs-)QW(j)&vx_A)u%&0Y&WyC~8kYQ3nEwG6^Wk zBA_UnfTE5B6m=r_ic%AUBOQ?B`u6aXmgs+_zs0`n@0=JhU#6&gVz{hWih6K*DeB3V zqF!t%I-V^>z1dQ90$Ymuu%#%6Ek%9VQq+%)qFe%s`V&wzfPkWb1QZP-peT=kqI?31 z3J54FB%o+80YyUyC>lyY(J%svh7(XUf`Fot1Qd-TplCD!MJEzaG=_kpu>=&2BlwEC zCI+`SAj!Ad^P+B2^q&1VWPD=8e3_z&iQz{|r05h*FGWRcDVoHVqGGlbO=e3`30sP$ zu%)P!Ek#q=QZ$W?qUi(_%^;v?CILmW2q>COK+zlmislkfG>?Fy`2-X#AfRX=0Yzm5 z6fGj4XfXjrO9&`Bm4Kq91QeY{K+!S+icTk>XgL8zD+s=#lM{oVI3UT5?cryF6wS8J zXlEow%$F%TD=~buREo~#^is5%Ek$eCQgjYmiq2(A(OR|?oyV4{nEk$>;rRW|uitZ(#=sp69?kAw=0RoC1 zB%tUa0*W3cpy&|-iXJ7P=rIC{9w(sa2?C0qB%tUi0*ZDJQ1mnbMb8jW^eh2II|(Ry zj)0=)2`GAj;48W@F*wr!N&eOzer}SY$u?e0jF>M|^lD=G{Fzep8mE_{*V$6^23v}D zv8CuuwiLa^mZG=WQnZ^bMenes=v_97-XoyseFBO;AfRXu0Yx7YQ1lT2MIRGT^a%k) zpAt~Cmw=+r2q^lTfTAx5DEg9sqOS-j`kH{EZwM&*mVlyt1QdNoK+*RE6zwPYie63( z-tB-S53$c^uSk*mzf!v|*b*b=%M|^b7=ClM6dmOBQuGU3iVm@*=vTHB9cD|>Z)_<# z!j_`n*;4ceTZ;Z)B%mlnKv9^0qC^6U zA_NpwA)u%#0Yym!6eSZ-RE>b5>I4*}5Kt5)peRN_Q7XY#^iyK+umh6(h&}uqkfNRT z>^dzHF<+*rb|hS9o)p#L^ioupEk*U%QdFNUMGe?e)Q~Mjjo4Dum@P$3*iw|vMp07& zikcBnltDmIa{`K55Kwd+0YxndC~8GOQELK<+7M9GmVlym1QfL=pr``@MVSN?Wf4%6 zO+Zmc0*X2jP}G@#qAmm!btU+UYDR*`J0Quc?dNENw@Ac%nWA2i@WcgD zbUde*qTXyNI)N=keb`cz!l;c(Fg*HMiNjoih!cg1QeY}K+zZiipCO9G>(9x@dOl| zL_pEW1Yc2)NboENB>59JLp`PFQF|=TbPlJNqI20&w3aPJ=dq<|9b1adXG_s~wiIn(OVI^v zDY}r2qKyO;Z6cuPA_9sw6Hs*V|6=bx;G?Mjb&tv7o4k1yn>VDE0>SieT?zM@0oi#eToPo#>J?9?vp8q}P-q*?N z1;2fs-QVo&%zI~dlTDTaMJp&!bO{BDE~P-xN(vNRMuDQsDNu9;1&UTtpy)~p6s@K} z(Nz>Ex|#w-*HED7S_%}cp+M1E3KU&O5hz+131`hRMb}tNK2wVF-6Pudk%;r<6s?c= zd9$VHCgw}g2C@|0OqQZs$WnAGS&D8WOVLKM6x~jiqC3b^w26$OJ1J0f7X^y$ra;j> z6ezlv0!8;xpy+-I6g@zJq6aBZ^biG#9;QIiW(pK-p+M0i6exO>0!5Eepy+W56g@$K zq9-X(^b`e(o~A(2GZcZMb&>E00}}n*{ch}yQZ&pRi=K@{oG+*7g@`|Mt`u!!z7%aI zOVNvDDSC-4MK6=3=oPXQy-Jp%*T_=zI$4U|AfxC_3KYFXfugr5Q1lK3ir%F_(R&mq z+ChP$_bE{H0R@Uaq(IR}6e#+b0!5!tpy*Qy6z!xy(PtDW`kVqqUr?ZE7X^yGq(ISE z6e#+dB2e^vBz(C6iOzRVg|=1WmsvJ}-LOHqBY6g41A(E(&B${|ZpL$VY# zB1_SMWE3@~Kv5G46dgo?qJt?=)RY26%_vZG2nC7`r9e@03KX@VKv6CQit;E>luv=8 z0tythq(D(C3KX@bKv5eC6t$&5Q9BA0wWmN)2Z}&Z&D8Kg1|)i(`w2*`)ZmqV%srxY zOpQ2SPEnUszwhZ%)Rp;C)Qv1f-N{nagDgco$x_sdEJeM^Qq+emMSaOq)Q^m!{uC%0 zK!Kux6ev2J0!4!;P;>+ZiUw1lXb1(0hEkwt7zK)kQ=n)B1&WTOK+#AF6dgr@qEQqm zI+_AS$55c?SPB#!M}eZ_DNu9*MWCotYIw2%iMDlcI!n>D?pRcq8gagyqOqy|xeKLe z9P_29m@Gx($x<|dEJYK^QZ$JyMJJM_=p?cfO(sjx6f%mYQlMxW1&XFqplAjKib^O@ zR7!!OG71#Uq(IRu3KX48fuh+ID4IioqPY|(I)ws7^C(bsDg}y8qd?Jo3KT7%K+)+G zC^~}zMGGkcMMbIM+YLx`viqAMW27j>kvcOq;(R$pOH%!p7D>_B%$K62WGOm_EJe%6 zQgkj^iq0cT(fMR4T27Xt3&>J*AsIy%QK0Bz3KXrNK+z=>D7usaMJp*#bQuMTE~h}z z6%;61MS-F#DNwYU0!3F*py+A}6kS7sqH8How1xsjYbj849R-T6r$EsS6ewCp5hyw< zHN4M&L~jWhoW)Xfo+EW*YQ*_+if&HzYcG+aTbM6Jx00pkHnJ3LBumllWGT9XEJd5h zQgkO-itZvy(cNSe-9v$*dnr(K9|el;r$EsI6exO-0!0r|py*)=6m6zJ(H066Jwkz^ zM=4PB7zK(Rr$EsY6exO<0!2?zpy+7|6g@+MqGu^k^c)3>o~H;D-IN;cVnCutSWMm^ zMUC7e+Sb&F^W_x1nCcfUm7$Xcq;FzNA3WR}?7vngT_;DNwYB0!80Y1d6t$hR-x0cJMJc+ok9&_l@jtQzOoo zQ}jcsf88=E+Q)n;`jIR}Kar*AXR;LiLYAUm$x`$iS&DuqOOcnR*X>diBBLmY0!3j8 z6eUxj$frP23I&QH6evoiKv5b6iqa`i6s15>1_g>TDNvL}fubrDD2h>_C{BT*Yzh=r zr9e?N3KUhRKv4|}6xE~%6n&Q(e#U@A&v%EP@1>}g3$@ZB&X-eEFU|krJSnQrd?{)` zmZAg5Qj|lMqK0HCYDAWz1IbdPUg2!zfVH zi6T%`CoLR1-xN)Cf4``1TJTE$S{FK}MVv3EsC$}UaDf!{V7?UfBuh~*vJ~|uOHm)P z6!j%bQ9rU2^(RZw0J0PfB%|nX3KR{ZK+zEtC>l(Gq9GJ08cKnpVH7ADPJyBk6ev29 z0!1S!P;?XpibheO=x7QQ9YcYlV<}K{90iJwr$EsO6eudBK+$Ll6ctefin^wSM;egm z$?oveO^QxUykJX(G?UZT1A1PD=AR4ngT^vQK0B*3KU&Kfud_EP_%{uMQbTgbR7kX zuBSlJ4HPI^M}eXnDNwYY0!24b1d7g13x8lhqP;C9FO{Oc?q&amw21TN6y28QhgV9` zM&?V=?PMvsgDgdx$WnACS&Hr=OVQnADY}O&MfZ}W=sq%v?x#S}0~9EFkOD;yQK0By z3KVUoK+zTo6g@(LqDLuE^cV$-9;ZOj6BHJ8f|-8#QAcHUP<%&UoJ(jGGB^bBTLci zWGQ-sEJbgUrRXiP6unKBqIbwr^e$P7-Xo)E2L+1Wr$EsM6e#+T0!1HDpy*=?6n#R0 zqE9JMw37lwpHZOba|#rFL4l%O6e#+V0!3d@py+D~6z!%!(H;sEeM5nwZz)i;mjXrK zQ3Q%!N()alAkjGv&dXA?In~1VX%XkkDf%hRKYx`J{mgtR`h_e-zmlcsH?kD{PL?7s zU9a4wC`6W`B(fBR$x@U|Mv+f}q7(`gMJP~|N`ay@3KXSNpeRa#q6`WYWm2FhivmSe zC{PrmKvA3mMcEW6s!D;PY7{7{PJyBt6ey}mfudRzD5_0?qB<0TqJ3%MO$H>|*gY@$ zQHn}@3w6^Y&X-ekK)V0RYAMQLz7#biOHm`T6dg#GqQ+z?YC@KxgUC{JFjP&&6E)*#0N)afkpC10nfJ9$$ho1)N!7Kf>E_6$eIA2at zuXMleHB!`@`BKz}EJc0EQq+$uMg7TAG=MBc1Ibc!I9ZAYk)`MeGKvOMplApMiiT34 zXcz^GhEt$u1OC>le7qOlYx8b=W*>X9DqW0ee0eiElrO&Ury0^>HZDZNzwVtm!jolDY}3xMHiB#=pwQd zT}+mu6=W&8ge*mulBH-R8AX>-py+Z66kS1qqE!?qx{?A#t0_=)6$Of}ra;j(6ezlu z0!3>mP_&i;Mb}ZF=z0ni-9Uk&brdMNkpe~QDNuA11&TIMpy*}_6x~7*C|Z^te$IeI zA8_AjJXeZx+$;TC(<9E8Q*=kV|K$x*w2AprbSGJg?jlRk-DD}chb%?+lBMWAvJ~A< zmZAs9QuH7hMGsM+=wS*JZKgoc777$SLV==3DNytn1&SW0K+zKvD0-3tMNd(n=xGWR zJwt(_XDLwh90iJ=r$EtG3KYFSfud~`DB4beq8BMp^b$p&Xk&Ufdz~rz$-%i@iaNUY zUB8?jalV|Q*VFx0>!s)o=1b9=WGQ-!EJbgVrRW{96unE9qW8#Bw1X@~?~|qI12T#} zq(IR}6e#+b0!5!tpy*Qy6z!xy(PtDW`kVqqUr?ZE7X^yGq(ISE6e#+d0!6ziP_%~v zMc+`M=vxXD?WI7`cN8f4o&rTbP@rfZMWE=_^zbMH67A|Ve3KX@X zKv8Q76t$s1QCkWWwWB~$dkPeFpg>Va3KShifuc?nDC$gsqAnCD>Pms4ZWJi$PJyBx z6oI0gX!s)o61~GcFKQSKUg@9ejzvAA5$DS(>Kpa_jZ)N)`BK!MEJXvzQZ$e(MTe86 zXb@S7jv!0XV6qeqAxqIvGKz*#plCP+ibhbN=tv3_jif-)Q4}Z|MS-HDDNu9_1&WTP zK+$m&C_0`3MJG_8sE`6hqbX2SM1i6)6et=?fueB~C@Q8v(Rd0JO`r%A^^S%QF(A>8 z-FF@PNYOcVUh>3f#QAcHCP)2&cSz9`=1b93vJ_1tOVM<)6wM$@Q3+X!O36}GMwX(P zWGR|OM$yR>D4I=yqB#^OnoEJAQz%e0j{-%fQlRKG3KY$!K+ysU6rE0iqBAH^w2%Tt zXHuYO5e16QqCnAN3KT7&K+)M0C|XK^qH`!vw2UH9bYe6--GD@IazDmDNs2CUuk_E2 zMw~CF=z^$!!JSfcA@il^BC-@+OqQY*WGT9YEJc@+rD!EtiY_Bd(dA?*x`K?NRTLmZDU$6s3`+D4mR=CQH%mbaS9Y=Q=q6S1&XRspr|?p zifT}xs3rx9YEhu5HU*06P@t$T1&ZoXpr}3tiW*R$=l}{7=P@t$S1&Z2Hpr}0siaJoBs3Qf64x>O(CkhmGra(~_ z3KVsvKv6de6m_RSQ4b0f^`t;iFA5a(rU(=rm=WG;K%z&wV^QOb;FbP*7y4vGoG+(n zK!*SIW+@uTd?`AdEJcIJQgj4aiUyOVXb4$~hLWXd7+H#jlci_`8AV4@plBooijJZ{ z(I^TO9Zi9vV<=E`ECq^=qd?K|6ev1@0!4)sC>l+Hq9O_ujiEr%SPB%4qd-wH1&YQ~ zplAXGiY8K^Xc7gAPNWDF^~(rX+hU4*_g%;SQsn;NO!7$?5$DS(nwH_Wc~pv~Ghd2k zkfo@EEJdYcDJmmN(M+-w%_2+D$z&;-O_riLWE9P%K+!1_D4IusqEjhQbQ%SU=2M_( z0R@Uqr$Ese6ewCqfub`hP_&2wMQ2fFpy(zF6m6hD(ajVnx`hHow^E?!HVPDNq(IT_6ezlb0!5oB0!0^Qgs(Or z(JtIi}nf^OcRL{NA|2-q(d^tto zOn=aGQk0yz|0{i;EJZ0~DT{Z2 z4woYLZKC965G8ItmnBPl2KvC{VPH0!24cplCe>if*Dn(FO_>-AsX^TPRR;D+P*fqd?I{3KZQ= zfucJoP_&5xMR!u5=q?Hr-AxfFT9FxEYCxjTxbHe%B1N~jSNiv4Mw~CF=z&cCrq`tC zLFP-*Lu4s>m@Gw`$x^h1EJcryrRY(z6g@_kqQ}Wn^aL42Pg0=hDGC%lO@X3kC{Xk) z1&W@dK+*FQDB4Paq8BJow2cBq+bK}=A_ailBMV) zvJ`zxmZDF{QuHZViguEv=rghueNL95FUTm`MS-F(DNytk1&Y3=K+$dr6z!ov(Ki$* z`j!Gkdnr)#9R-TMr$EsU6e!w9fubKNQ1lZ8ihia*(JvGz`jrAjzfqv*cM24FS$biP zq7X%(=)KHvjWmZBDx1Hd%>0!alV|QL$mx--<6`~%$K4TWGTueOHm$Kit@=)R6v%ZmSibvMV6x0 zWGQMxMp0V|6t$y3QF{s$b)Y~|M+y`jMuDPE6e#LUfub%HDC$aqqHYu@>P~^89uz3* zNr9qX6e#LVfucSXDC$drqJ9)8>Q8~90Td`2ND(M%mKDC%fJ8UA_c|UTMV>nr9iA0& zzMP^VS^lFtq-ZGfrDzygiiVS=Xare`jwDObNU{_iMV6vbWGOnDEJeqVQFJT?ijJc| z(eV^0I)MU3g%l_nO@X2!3KWf@K+#wV6pf=mQ85LI##5kZ0tJdDQlMxO1&U6jK+#DQ zD4I-xqA3(8no5D9X%r}$P7x?NA}hSpfJA4w_gxQ`qQ36g^^B~D^W_xH%<|Jdl%iS8 zm!gx&QZ$<^MRUkfG?y$zr;w#+9$AV`B}>t1WGR|YM$rNa6rE0iqBAH^w2%TtXHuYO z5e16QqCnAN3KT7&K+)M0C|XK^qH`!vw2T5p=Te~PJPH(@Pl2N46ezlY0!0^6py(nB z6kSY#q7@W@qSCBzt^tY8a>t@FDVpw{U0;$FalV|Q%d`B!A4|~{%$K57WGT9mEJdry zQgjtrimoP0(KTc#x|S?OYsgZxmW-n7C{T1g1&VHyC_g}HwB9Bp+M2S6ezlnB2ct4 zD_mwkqC?zw9WRrjHSSn+e^$i#a*7_#@>hH+MVpx~MO(;H^axps9wkfBV`M3MoGe98 zkfrEJvJ^c8=s5}$Jx_t6trRGFfdWO_C{VPW0!1%Upy(wE6unG= zqE{$T^eP34UZX(K>l7$@g91fwQlRK93KYFffueUPQ1mVZir%9L6g`*~zR!R}+q!4h z4@uE4?j!ehWJR1Wr|6?B|EpN`a!^C{Xk}1&X{XdfASm5Cw{oC{PrpKv6P9py-3Fu=lwsddL>fr2Hxo z=gTQdtKv7@B}M7Xm!c?HiZaMjlu4GNEV2|;Axlw=EJbm$6lIg8s45vn)hJL@odQKQ zC{R?B0!6hbP*j@&MRh1pRF?up^(atOp8`bbRY$a8dIRC z2?dG{qCnBX6ewy+fud#T^vrB(@E>2GwT4yh7xzMP`mD*lA8q$rR1 zQj|}Yq5`rMwIoYXE3y=|CQDHpvJ|x?OHn(r6tyR#r~?IxI#QtMFbWiPqCin+3KVsr zKv7o;6m_FOQFjUy^`JmePYM+EqCin^3KaFBKv7=`6!oJ(QGW^)4WK~LKnfHcPJyC9 z6ev1^B2d)4N_d$8iRQbXqqUHtA{Pc%i8xKt)M{BB@`&SlmbO7DFQ{as)TEOYl=3yZ#14PMW4DK zs$Etk;(R$pS61;md?!V#nJ-0Gk)`NrvJ_oImZEFPQnZFFMQh1YbRAiWt|v>;4P+Fp zqd?J(6ewCxfufrzP_%&pMK@ER=oShT-AaL?+bB@9kpe}xQ=sS$3KVUkK+&BPD7uRR zMR!x6=pG6b-AjR@`zTO!KLv^&pg_@s6oH~Es)SE4Ako(DShPxt9(Lb?e5gvq`ErUL zsp8N7L5dz_z7#!1mZHbWQuG8_ik>7((Nkn8dYUXn&yc0)S+W#8M@G@}6e!wCfua{E zP_&H#McXM*^dbd{UZOzJ%M>Vjg#tydQlRKH3KYFgfuc7kQ1m7Rir%6?(c2U#dWQl< z?^2-XJqi@i#T6SQAW&<{vt)0%$K4pvJ_PzOHqt0 zMRBqeWs{|-Dp`uEk)^0QS&C|qQB;!xMYSkURGR`tbtq6&mjXrgC{R?N0!0ldP;>wV zigGAW)Q|#2jVMrbAO(sVQ=q5`1&R)$K+(YzC~8W9qGl8*I)nm6hf<)ZIYpo-Jr>S4 zAkocf1}7Q|UgjnR1our{w75&nJ-1H$WqjrEJba|Qq-0#MeWE^)SfIw z9mrDDkt{`rkx|r%0!5uEP}GG2MO`US)Qti~-6>Gig91f8DNxjl0!6(kP}GM4MSUqy z)QUx1&T^3P*g^NqL~yZnne*P8W9UWU_hda-H*Uc=nS$HEhJ0PnPe$iL`KnB6ewCufubc8C_0-0 zMN27AbPffImQkSSTnZGOM}eaADNwYW0!0^4py)yh6kSAtqKhd|w1NUfmr$VSQVJBU zq(ISS6ezl!0!3F)1d8Uw!bxFM^qTud<6J4)?v6#PViD)dDY`o5A83CLB5^FbhWS!- zEm?}zkfmrXS&FVBOVRaYDY}6yMeE2?bR$`c){{|m69tMkP@w2$3KZQ!fudU}P;?sw ziZ)W9=ynPe-9dq(O%y1)lLAF|QK0B<3KZQ#fuegUP;?&!iteXC(E}7HdXNG|4^g1# zVG0y&rU(?Rj)nUfkZ3J;__<1oE_JWbw!|XNms9k3%%2pIq9>RyMNg8Y=qa)kJx!LP zXUJ0YELn=4BTLcqWGUK8mZBHPDB4DWqU{tYdXWM}FHxZAWeOC%LV==JDNytp1&Us$ zK+zi%D0-6uMQ>4{=xquVy+eVbcPUWx9tDbaP@w323KV@nfuav7Q1lT6iaw?Y6g?UX zpJza#E8Vf^F)3Q(o?U+ui#T6S(dRM$)-);lg85Rki!4Q7lBMV?vJ`zymZIHcDcVDp zqHoAj^etJ6_L5Qb9R-TMr$EsU6e!w9fubKNQ1lZ8ihia*(JvGz`jrAjzfqv*cM24F zalLFuQHTOXNfamwQ=llB0!2Oric%<06rn&-Dg}ztC{UD65h&Uj3%_hYqSGuUeK+%B|C~8cBq9zn5I*0;A2UDP^DFup} zQK0A$3KShmfuiOVC~850qFf3T{Q`9={ zAC@IWZI~}bZOKy9jx0s($x_sTEJYp3Qgj$uiaL>{s54oLx{y)Sl>$ZGC{Wa$0!2M2 zP}GwGMZG9c)SCiDeJD`WmjXroC{Wa&0!0HTP&AMNMTb+MXb=U8j-Wu%UsjUh|XSTc&nQJ|=p0!8B~P&9!8MH4AdG>HO5CsLs3 zBnlKwra;jY3KUJHK+!Y`6iuf<(F_U{l~ACllmbO%6eyZWfudOyC_0$}MYAbTG>0Nk zbW}Wiy#a~7?~X;Ir08Y$Ey%g?i1XzXofh|>%$B10%$K4CWGOnGEJbIKrD!2piq0fU z(IT=Gokfs<``1d*)9zUGSUlo< zIYm#!{oysG=xOFl(KBQzdX_9j&yl6*d9oC3B}>r@WGUK4mZI%sDSDBNqL(O8^fCpC zUZFtIs}v}DjRHllQ=sS#3KYFbfugr4Q1mthir%3>(Yq8VdXEA{J19`}J_U+Cpg_@w z6e#+L0!1HFpy(3{6n#p8qMa0hq9@|v*#;y!!M$VlNh$it&P)C*9&x^$qA%nAWwoW~ zE9Ohl*JLT$O_riPWGVWFEJfdvrD!i%ioPRD(f4F2`hkq1eH1AAkpe|OQK0B&3Kac9 zfudh2Q1lxGihid+k(aHP?I;RSpeTs~MPUjQB~zftr$A8(1&SgRC`zS3Q5pq`(kW0B zr9e>z1&T5$0!3fM!w(sd=#TCvAiJb!xO+s)%8oc+PEmHY|6W}ws>*yRsz#Qg>SQUZ zL6)MLWGSjemZI8ZDXK%3qPk=$sz*jqeF_vcpg_?96e!A}Kv6>q6g8qi(SZ~wYD|Hm zCKM<-hyq0iQ=q6R1&W$cpy&_^6dg)|qUIDRYC(abTnZHBQJ^TF0!0NBC~8R&D2io= zlk1tH58bzj;@QC~{Y8c+xm9+=`ErWdW&2GUNKt#{OHl{16m=v^(P3mM>O_{J&SWX- zLYAVgWGU)KmZI)t6!oA$QBMjK^`bygZweIkp+Hez3KaFDKv91R6b+z2(Lf3m9ZrFw zK@=!Df&xW@DNr6F1`Q=n)D1&T^2P*h5RqB05; z&7?rlED98zOo5`=6eyZQfugw-C_04#Me`^EMaN`^mm84ix$b?}$4XI&d#ZhEcEtH| zicZh=H#U-@Gng+$3&~P+CRvIWk)`M?vJ@>QOVJXt6rD|$qNQXhI){v+WfUknmjXrS zQK0C23KT7;K+y#hD7ugWMHf+^=wb>Kt)M{BB@`&SlmbO7DNuA71&S`GK+zQxC|X5< zqAMv-w3-4%S5ctoY6=uxLlG#NpB;YHfJ8sBn7lxWzINf-?1=N_Rq>LN4@_%#P{@nj zY(KK~VlOywu|4)}%G6j@do`C4Yhyozi^Y!0^t@`ZE2?;2t=Ri<&#Mt>+yVTio9BM#rA-=y~H}RXcm$#MseY zJ#TXCs_vdQJ@#==&nt@^+Q;)|$7b~Nym_&^2YB9s*sq6s-kGtUgFSCa?ChbQw=DL; zaL-#Ft3J~6E{+{L%JWvnt~ti@R>eL&&hxI0wJ7wwwXxD7&s!I}cdX}ai2YvddAG%S zPxQP^v2#xJynABXCwtxlv6|C7Z*%PU8J_o8Y)z@>Jr(iJ@2E~ON%^jXRP)T&)XF%Tpy zZ7WZO;_iJ1&xPXd2gln&arcwImqT&)qnp=5areFVw?lFF&C?yBxclzcN1?d;_QlRn z+`azX6^gqT5W7Qh_Y81vDDED@_l4r_82n4f%YNJLG|6j&yIj@tZD)41yH&M$cH%wX ztG?LoMt+-ku5~q<+g&Zx$}Vo3zKWe()x1T>tND4@wGC}Qdg<;g`>J(Z#JV47A7uME5kwuoipEEtfRsTx3t3)R=LngVOYpQXN8zsT9+Wy zZffft>Y50{ZSjNMii~$F(k-|^9XkMcZv6)x9P;XhhNQ&beEOa3r_~J&O^JWG>&18M z)UcHJy>GnquALh0XY@Sv)lX z$|n06h4Xr(C)R7n15dBBrPzAids6#xUY${zQroWBZj7ICp_i1ExW4nYKD%gsV$R#I zz5Vjs#GHCF4w>rJ$+pdv*Z{$tl=!v}Zh!fd#Pxi5!1|*Tb6!}zdF|}PoC8lC(Ale3 z!{$tJ>)1$>mvV(iH9vS(;tIc5ch*CvCT?KH6H}@sZs5iz?p$?>SEq~3aU1H&U`{CC zt20E4+0J63JF|u-7PDp3=NH;F+je?x#OKE+7W4Cc+ZNb9ct&$lnrX*9cjfYX>?RKN z;}1S_j@?4rZ)dMM{{dSG+qla=J>&OzUY#EH_~34A$6%75@#fNXg^AmGTVapJi8=4S zzve5qeNy6gzr5lyn{%J$Ol3}w+?(1aR_=y3p8CmMk)N^e)MI)l=Ind@g6C&@bz1tt z^{mmH_~O@Iw3}h5)_t_{sQ}fkb8lSYP^HAr+Is#1yP}qc-L2ef+@hU(AHHo)V%9g; zUwC)0H8*bWHrgin8P9*RsL-pkUUQ;{Xpi@PWZHnllppVS=nmVBwsM6zHEJiW=iJ9G zbQ__O-F4jcbPwjF#Bbd3*$!J1Tf1BCdqbOU*LSz<2{yx`#j9?a&CsfOQC{MjmYlKoCff}6*c`X3mjrX%u1-x2uKWQOv#igU&WXjmd;jt; z?AF?D+j+^YXV|LSjeKV4n~l6WSvJSr-L?gD5_h*->>%TAM6$h7Nl;(X3(Sj?4g-Su>E6P`bR--mO(I=eNeJ##)7So?&;b?@AD#}fgwqgV84lDG-Cy|m-K zQ@nb6ZO&Y~o;sc#N!%5dF}c^wVZlbb;-=SMPTZH{+kRTvE3w|o`ut+IwU$j;Y*Us5 zQxfalSc|!z#f)s`mnGJF`L|^a68kHf`s4J(Dm=XQ)~n`v^`_gDi`^=WutTF;g&&xE za*dadORWDzuikrG;G@P-NrMurP;W-x@wN(C!IVSou;MmT{JLKk4^3R%9V@%rT-(}D ztp4OhcMwU5Fa6<+A8a#qvN`UkH9DA+62JVt>vsh=b?4U?JR4lk{oQ^nN=&-&ksW)D zM~Nn_&=qBD>~&R##JX*KSWj>j$653Sh;uZ`|i15+)aN4sOH zpYh#w_lCUsjWj3Wq{D;)+d$^z(7jK0Ph7>yZ?D>9@a*FCHr-dp^BO#F_jvcuPYS0r zxYh8vfBx%9DGgTJL!bNSHwmXV_}DJu{`q0M*l*^<{qx_ni*>bQll$lUc1|7JeeR#V zgE^(aVRm`<&ws;0hPCdW|5j3p7mA0PWL1rZv+8CYSu-Ar)%3ii#$Ghq#VXGW*YLtw z9ixXuJ4E|ewFhdQ)+3f_tLd&eo;YF0$86msT}jnY zsDD+r_-YO9l6iK4>a8oSRM*;_YI|Od+)&rrtm(nE$#Pg znw3}&TYGylU|%77?A2Gci{217BpZp4ccdFmu-%yKeH$8bl{+=Y{@EFBa8IIwGgv@| z7H0Q%FUiZl%8l+)VJ~&TRb0qD32`ra++@Dog(`nl&SeL<1&p&PNui&!GHrzu*J7(3 z%FWFyDaspPIz6wnWNcnZVd>c7!s#W`%8JL96_3jsTQX;Q*)&&-Egm*wQz*pmI*^9&nzt**1heZHvbvB zX;x8LvD;dn7wqWqGpCNt&u^7G);xNJchHKnSbeSoFTcGBG`^85xirsnu*DLp6n zHSBcbe7{Bmi?Zy#M`m}I##(qHx=XkGfAzu*{l<;_8ujfaG)&xt|KOG;Zg`HLxZSxn zsj*F}8Z4t;rDgo3W&O*y+TXlw|MK6xkx;sRk?hrbzXhSxseAjn(ftG%4o0m4wui4*CO3cd7Yv4Dw`$pYLi(zqp=f07b zxUqlv-sx7RmaRzpA_Th7>xP=gv$^+5a~E8;3JnOrD=s;Eu3vO9as-AK>CZ zw`KloZ=-FQmVQ-t%*k`xKhLlBmu^<#qIR>Y1ve{*Hu=BB%}T6|-K=W=bF+fS)c?x8 zmDKw`Jb?bs{&FuFDm@4KuiRh%;S;p~*;{{aZ}DiD{|_DwYjkPhH$Kp>863#m^JsUR z4#xj*N7=>x!Qyz!)6zdb#rumJ@*iB+KU>4R|FhQtd45fM z?qx5x_J1Ma7^bBpb=?1G{BJx9tC3R2Eunt+bxcj7P0@+ zrGM|r!?W#qS2#V#uNj{8f3^aD{hsnSpA8#^zxrzSpCS00>+?5WUH`K?z~5S*JP{6_ zI0rj{r|XP=WH z@bJOCInQro_wI}wKQpDLU&lRUG;QS9sc*5Ni#BRcRSmvn(^Rk964A|S`Ojv#7mEMr z>N@|!dH?L%{%_98b63{zA8r5ttXWB&^!V^^@9o6S&+!vy=Gwk*Y-?QAZ<_!2!6YU% z_}}a5RIaOqopOZh^miu`+sRIJ_Uk5q=J^NN7|ZeFM%aDhv3b7Vpn)aHtr^H|F1d;5 zF5L28d*QsiM)vKC=8gRZ;W_T=f^Ulc`(wkz>io5}&U4>2NGy7;TQpPucop=2Wkcj8 zHe3BlOZzLc{?@i`=r?cVH~5!c#ot<=f8B*Ec70<1{BggK|8MLc+v0!qzF-9Y!T$Mg zbX)(^@ArvghCLB=hmKskYuKIHJw(QB2fB^wj!6v;b0^rNo&5vs0OaoEhuByx$FH8! zCh-Vc-5zNBTgvnOR`!FIstxlFwI7rWw3F2<|L}z$5C%Vtu}6cnl<)<1_((jFvB&Pj z_eTAA_%XjzaJaB5?w`26>fy^mNgYFfxU$Ufg3~&=#}z-*4x8@qnU_@6e#$R9PquBZOSW!L*PY4vt%LJ=_ta$y?81`{pEhlJfj6l8 zsKTB{jA$7wyBAa1lwV&vs#X=(+p_$6dsbScRp~PA#1@VQTTX9Q&bg z;_7;8y$brU6g$Dq>|K643T$N(m+xQ~D=f6xty&faODM1_V?rO6)?G{MQLzNu0(P-+ zGp9_M6D&!WZOs*TSJAF~1#E+sFS-0mT5}z}DmI2~0$tEnIoOQ0l;A|ARcOal+jxmH zZNq9_oAQO(`f#N!b@^5m>(R4(MnO-m%2wRXD0Dwx*H7dNO9~QK;7C+@Q^kMQTM2p< zkC{2av-e+2olsm@JaycpqN#)N_v^$kRD@$%b?y!?ur z+o6236c}o6VDF;~yZ0KFm}mQ1+sRDpRImMJR@x*5`K>&+f;ox*{-m&=Vzqh*8Xj#g zC$0{F<-`Ke?w;8@G5bV!XG&Z&UyCr?TCX1EYv}I9i3@eFSk+#pq5H7D!5%Aj!xa~_ zFJDYS1x+X+si4BD-2!*Dl{mD41E9+3*wG`gHU$+D3yfmW<#T2Q&VoMdwF;B$NV`SB zJWjYhmN;^0ua~b;L4JPX3_G;#x26U8!8Rx;sMubWFtpS1*hSo718?q{+E;8;+vLHO zw`46Uz!X%7DX2uo_G2)mf&+W2pocb!+gI+II+TmCJ)yl^ajb5yt} zs05=Dh_*JpLMw+#+iJmeyR+SbY}7Ru*cvA)_NN`BbXKeKO=%l~i;IXYgPqO3F5kcH z?S@V(Cv9*vmj@De_)%qZSg=_QHlbZ@;)HDp&Z}5NVwK#{YJ|O0NS9}#?TyCIO!B!~<20dn0Xeg-QP%f}Sfju1C@=GU9D=8~~1Z3AaVTqkyzQ4;KtL^@iSO>RH z5`t`N1ScvHsMzHN75luPVyCl53T$N)lkLGgF|x%A%x|#NN;|Y-|Jjvm+Z5Q-kKlrK zKh=p~6PDk@^YdGC%qcKhnpo**UZ6$TZm!tkcB=0YN9OeG&>_dYTQ9dD$Gu-KzkSQr zIZaE7Cl?o$7B|ajF=g!ZnVrYlCM=%aVoIx4R+LSgIc1EE<0nrmDr;eH_Uml>X`CzU zlH;e(YSW^0dW&%dZLKLP89TAFz58!g`xaAjr`Y=k4;@!J{m}8#b6QNuX)(BEP78a( zTIaF00xiZ*DK0H7no!(ga`Ds&WfME+TNONcY2g@Ha*wrTlcr5=QEG3zv$52=aYbcC zg}QDL~C0$%)k_cx?kbfZqsyh+JteWi70)uAeK)J( z$!5h<%!1(Vlvt=eDCjnq-=zwI`&9WuZsIOfSh)YQ1D@knJjG2Qt;DJAeh+Bv_DdbS z!F`68KQAcYId8@D*NUgD70+7j`7fMl$`8yu(XDtg zTJc=8pyH^_-L2eW`Lo{gr?chHTr1ttEAE{Y&pXkfXPvgy%J+Kk)Ya?TvuDSgrtY5H zy<|#G?s_I-k#sfgPjQPcdpC9+o`!s*uCGi(pT8t z>l&|=-5am%w@AI#<+C}{=Q1t&2L=(rtpe4io45)J^SUMN?-Qw@=D2_U%n!VKJ0!4 zrqY-FVsEA7E?<5{i9Y;?trhm{jr5hi!k&AFe8pGTtM1u*_7i)>xyZKL+qB|rFJ`Ch zcWcYPT<%+*Y`fU$WB!mQ{vpr$Lq78l`J6xG%l?qp{~`bBJ=BfMyvF19JF>M(JcyPb z1{2Sl%aa~s?cnjJS7GIsNj#%2Px<+k52Nli5l6O47wNFy8U!yLDxKXfvE|e4SDo#* z9K7@fwyo`sl5W2s(AbSRp8XQ8jSb!J-P&lE8==uYXf~1EZw;n5vR{T!?&wCFf4K4! z8oL-dH~%h;xn|$xt8Gj=(DQPQpv%{5Y+%1J=JF*PH@VT4n`|^)pYBFm-}Uwj6)x}6 z=zg^;y|MiwvT`+}n%>0oa@=T_o9xDe?AL7=Ok-EuJ}wW` zSY&r?m#1jF-nN6wcWB&Y8^GlsHMX<^jmup%&bDpg@*<57*=d)b)tFp2$Z?GWY+tzZ zkJ7l@_PNVfYJAl;tjiy2tY`b$* zcMtO28h7^$@~;}(_6c%Njq~~i`D~4k3<&ZI8dC=axw^(91_$|AjTa9M@--UY93JFP zHRg;Aatn>)M+Lc5;|4p>y4!QF#&3=b^6whk7Y4bv#?y*|e2&J)47!`YU1R$AAlKA5 zWMYty*LcZ^L0+Tr?a4v@Ok<;ILC(`SaYm45YP_X1$oFg9J2S|kS;5$Gb};tUxL|IO z&(-+Eydb}%F=Kv^Yik^KdXNh>u3Q-8>omT*D9B%EY`i4M1sYFW8sw8T-nJ~r4{H4W zyda0q55`Ux1Y>`VXIvEI^EE!TBFL|3%vu@bx*A7Z9^@j8m#+%)4H|c>4)T{854tAE ztu#(v6XZD>Z@(_c4{O|aLy-M-!PsSeFb>ps=7u0&pz)bog8Z7s*v25&*EsTyAdl6! z>dqkFsPTilgZ#C|ruPN8jmD`D1o;$=n;r`C7L7k`4sv8mFm`)17zb%Q>+v98r17~Y zgZzfZ>}P^}fW}eJ1-V$`>a9V(N#jS`g1krLAuk2FoyO^}1o>2rcfA(mM>YQPMv&9q z48|UB2jgIkOWqCg3XNNL1o`K#-SRQ{t)C#HE#Pc$nR*Z@k@{o)Og%)L7t@X zT6@;$mVc|pok>CdPGhe9KAJoKFpXuAAfK-BzO*1esnPyyN#gRE8vEEE*>LlRYg}f3 zZNufuG`?t0pj>`WV=epp8!k7|c!K>Q4wp~TxYqt6hszr^er|u7!{r||=G))saJjR_ zSvf&osPTbDL4I0eBm2V~?(*F<9bgyc(=yK zG;Y`UuEsAk?$a2yKU(3gC!#UKjkbQZ-DvA`gvK!%XK7ro@eYljXmo!{BQa0oQ5w(D zxLV_j8YA{M6x`(x(>P7zT8*!3%&b<*s2aP>6&eV9e z#s@S$u5q8n=JsprZhn!*OEf;M@mGy4>{r~~_A1cWQDYa4eKii$I6~tnjYS%ZHBQx7 zqVW`s^EEEfxJ=^;jhAUmch56zy|Xk{*O++TYkiKgJsnG2E>~kqjU6=F)1Soo!!;hI z(ViwG`mq{Q+-NTkW6Cxp&bOztiLul@&$a6{VqTK1gl(!s_Hs+-OerfGV`EuKFizx@ zeXp_1%XQz}^K!?OmU_AN?Z{kL=2reWOXB5P;;eD*2W0kR%JI`|R^oKgm@y^Avx131 zW53{BITn?;*Kt~OaEU)RlijZ;Yl*gQUhY`?UD{&%S!$(g9bZy3#V*u+*r42^va*s% zV`i4wV*mP=J*~DQq5W9^O|hq~`+eEwOMEr7|J~)nLG=E3Id`7>I@tcD+Q0wka`|?d zKVEO;UqW~L&wVwwfA-SD>t_Gl*OF-=`%_Q$3;uT6UB>-$*Ei7qu?}|9n_b28t~HZ< zajLHsm6vzVbUVjh%edvaZNT!JH|E$$uTJNX_h6-hlau~%x!1bbU;c0t^u^_hE$?@| zr-Z!e*179-J=Z(iPBX_&dIP(Lyc~BzU!3Qzqw?~a&a=O5W}RD}-JJ5}onxn&V<)|n zY%1o?f*y-OHAH#xLxOQfzjYa5*Lmch zt}}VhNb8UKQ$K3Ib*XRbGOGM~lJ^{4>GUy`P9Ix-I(2m4#JXIfb?LR=x*TWMdHkQQ zGkMPm)))S%Z?oUJTxshvy8L>Q_Y_q+J*Lv>vE`>zM>kHa%L=Va!~ND}oLy(}pRO}` z&v@%6{Hf30Z(XX{x=bv;p5#4~DxE&D(&>}RPp6I!*}Bx(;XUldYIIxB%FC~I(1=iu z7qQ2>u=iWz`$FA3-+T4w`$Hjbu~)B4hPOE!I{o3ryAy|*q=^^kHgwwWHcYm4o${x3 zP2Mxr`e}daTkLlm>ey|VUcP?GduCKRT~g_EY5D2Y(e)DBQ|3o@`({j=Zr?muQnUXP zMVswjxq07XIot<&d{Z?ic~6^XmMJhwkwUeUbVYBooZ)?^Q(=p)4qNC#Y=Jj+4ZlrYm6i(ALP3q z_@ufII6hc^wEh5#1zvJf#Re8zddbZc>sxH)B_E<#&thx)J7$V?Ew=HJn=96_*w#Lm zTd}sqc3yI>Vl9j9z2rQ_nif0QM|&yOuvlQLRiIqmWm~V7%GF%96>Ftj)n!|=*2>u~ z+p4uuj=OB@)>b*@vaMV@awk0C*^dP zZT&hcr@3tF*F`ziWm~_l$`O}s{kkcqxNPg!UD1$Wh7&8KsPnqm>bI zj50!wRYu5h$_P1L86hVqBcxCnA)}QMQlyNKG0F%TtBjCw$_Ob|M#y+&giKII$V6p? zOj1V3iOL8$NjVVGKfK%afBG6b+9VGMgp9MpRPyAAljDR;_jlWw2_Z8yRYFP>C8ShQ zLdp~+WTv8o%uJH86oqO5pt?BLQYdg$b4mlEKo+s>B zLm43pl@W5LGC~$9BjhY)ge+D@$P#6QoUM$IrOF67M;Rf@lo4{SGD6N%M#%Zf2wAQi z2$>qrwnIjGGkerYo)!pkeM_tRFsg_iV|{_B0{cKM#weF2)R}nA#0QovQ`-(*C`|9dS!&%pp1}p$_Tkp z86oSH5pt6>Ammzi z40$W!d`#*iVd+zaWLP#|6SKqx*#L;md z%8?xMFSqaGB|h544{5eOlp}?#59NrE^`RW8WPK<{8d)F8kxtf!azx4cP>u|;K9nPq ztPkbLBJ-gfRVesSju-_W$`PmFLpic3_)w0j6nrR0H3~kIqdEm2%29)Y59O#y!H06x zqToY0YE$r`9Cax8P>#A3d?-gf3O#kF1|%yvIVlu=*nmXi?$8nr1&Y3N&s&;=B950+)GXxhu}S&9nCQq+fuar+DC$Uo zqQfXq)QJK`oheY%g#txgDNxjn0!7^^P}GA0MLj7{)QbW|y(v)ChXO@?DNxjp0!95P z0!0Uh!oK}sTvJ?#`OVJ3j z6dg&HqLE}NI*KesqsS;angT_~P@w2o3KShjfuiFnP;>$XiV7)EG@1fMMHDC+LxG~P z6et=;fudpx6pg1q(F6(i~>dHQlRKO3KX4BfuiLUD7t_GMHf<_=pu?h(Tq^|0s|7AW3RN6OQh(s#Oth3 z#QAcHR)+lB?L7twMVB#OiY_Nh(G_GVT1A$kE6Gx{nk+?Ek)`NrvJ_oImZEFPC|W~- zqO}w#x{d-x*HfVA1_~6dqd?J(6ewCxfufrzP_%&pMK@ER=oShT-AaL?+bB@9kpe}x zQ=sS$3KVUkK+&BPD7uRRMR!yDFZS*_I_kUM_x22v$p8ak1}RX5x*-8dp)GCEQWxr_ zr4(kJ{Mu{XP-zcb>HOuN`8~c%$1QOB^2Ez z)D)ePFT9!oDGx|bzfKKB+a^V~=S#^~QgnB|_}hY^=pM(1qI>O7be|oH?zcnH19m8S z&<;fp*`erRI}|-)hoVPqiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFKpy&mG zq89~Mc)b(eJ4=#y+F|q0!2Rx6#XPn^s_+GF9Jos3Kab&Q1rV%(H{aue+m@+ zB~bLYK+!(}MgIyEW&dHxnb|d8m!~K%P}D-GDS9to7?%MlKbHM~T;2Pj=!JA!RA^C3 zzLKI+i{e4q5BN0QqqTH=C~9SgqSkgOD%+u`jU9^G+M%ey4n^(kP*kx)QPrlXy+Bb1 zfufEAMV$nS77!@vEKt-%ps1@r(Sia+3kei0EKszFK+&QCMT-d(brUG+E>N_%K+zHc zMN0}4EhSL2v_R1^LQPTj+m9~KfRuO1zI|R--=g+R|NV4Zv}}t~@|6^=*rNDE_fXWs z@u8@v9g2F{p{TbViW==u)W;4*eeF=x&kjW^*`cVvP0`8%MFRwi1_~6dB2cudK+$Rf zMS}#2Ru?E*L!f9)fug|zMMDINh6)r76DS%kP&7iIXf1)Fkpe|)3lyy*P_(W<(RxBn z(ef<{-)2C{J+mMFt6L!y6|!%8)~(;7lzb&c8@DJ{mJCIkI6f4OvP03Pb|~7+4n>>W zp=b*`6m4mTqOI&uw6z_Iwy`N1El{+rK+$#rMPmetwihTGD^Rq9K+!mXqVWPn69kGT z3KUHeD4Hx#G)16jM}eZ91d65#6ipK-nl4Z@L!fA;K+(=ZP0@xe3M*wm$`jIU(MF+Y zRJuo-)uNPqB}KcmC~m%VDB9KWp=dWd6zy(@qCMp4y_6d?iI^wkV#p zY$!U*@uBE!I~1K`hoW=sP;{Ohiq5w~(FJxWy3h_q7ulicVw<8%1d1*dD7s9b=yHLg zD+G$J6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCc=yrjk zI|PdE6l#i2Z&A2E15!RNpTRjJ6s?_Zi|%SsO1_e!`&tw~SUwcp@Ay#kfE|h+v_sKD zb|`w-4n>dHq3BUN6g_5#qQ~t}^n^{(lLAFg2^2joQ1pyI(X#?Y&j}PgFHrP?K+%f= zMK1{yy)01lia^n;0!6P06umA`^oBsun*v2|2^768Q1p&K(Ypdg?+G%~6 znx5(38;UkhkFMWuQA)m&qK{h?m+cXXK5={~`qU0ZpV^`4b2}7$VTYnG?NIcU9g4oT zL(w;ODEii>=sSU;?*)o}5GeXlpy(%oqMrqdei118RiNlMfui39ivAEN`ct6jFM*=J z1&aO=DEe2RDEl$w+S7K5@&ZLI1d0j*MRfv2MWLqX!xn}0Ga%*d({0g5q3F9b>IS$BcNuX!}fuha= zMO_4nx(XC6C{VPJK+(biMT-a&Eh;69tMU2^38hD4HTrw4*@LP69njug$Q=n*PfudOgMY9Ep<_I-Kn-mI*^~)6fmHo_O-KbFXT>3)x+(Ie& zN{V(b6xZw@iuQ1PDB9BwMSIzyXm2|d?PG_ceeF=RpB;+!w?okZb|^Z~rsyDnqJssB z4iP9iRG{cEfuh3&ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%R zP7x?NRiNlJfuhrenxb6`g$Wsu^5Aq^v|A`zFWsY^Q79!}Nzpll;voY<(YcNfMd#U} z=zKdAU0{cz3++&JksXRIwnNb+b||{k4n>#Q6kRS*bcI0Cl>$Xq2^3u|P;`wz(X|3a z*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86x}XRbcaCEodQL72^8HeP;`$_Q*>6L zaAgLhymV4@b|^~!VqM+6g;MgB6g^ldK9&8K<4xa3d&u#j=wUk)Jz|HVN9|Dbm>r59 zw?okrb|`w%4n|C9 zl5UGWDwLA1r0BEk=OG7$qR$;4ioUQz(U*28`pOPPU)!PR8#@$zYloum>`?T*9g2Ri zDf&^M=qG`qp9PA35h(gqpy)S&qTdCI{tzhoQ=sTCfug?!ivAHO`d6SRR~Jv)Das2J zwGb#O2o%)`6cq)E>II5Q0!1x_nxan%g_ScPR^YWj&>;OWQU>!>`>I%rl^ZRQCESY1qF&05-3_& zplA_+qD2LY785AyCQ#H}plES{q9p{1mJ}#jN}y}*>z;L`DC|X^hXbpj)H3fknIG)$mqxIobe zfugkpibe_)tu0WrjzH160!8Zy6s<2%w1Gg;h5|(!2^4KCP_&6qQ`Ebz@L&d{d|)=~ z8bi@r>9%N8T`BoWingdLel#=`ZRz+>w3Qu-wzfmjHg+f)ZHJ<5?NGFx9g4=-p=f(M z6pghh+CiXboIufdfuaclMH2;zCJ7Wx7ATq`P_&~!(M|$IQw55q2^38iD4HQqG*h5x zXMv(w0!6b0islFu%@ruxMWAR`p{8iFxr$A_YQ>`=6?9g6m|L(%?rC_2CnMF-lU=pZ{39c+i9Lu`r;6(~APpy+Ucq9X)~ zjua?5N}%XyfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMSQv`}m6(~AQpy+ggqB8`F z&J-v*OQ)WQU@Q z?ND@y9f~fsL(ye+D7xGZMOWCN=t`TSs|1R!7AU$#py*nGqU!{Tt`{h}L7?bHfufrP zif$Gtx<#PqR)M111d47KD7r(S=uUy6y9A2v7AU$$py*zKqWc7j?iXr`&aEq)oB=8K zNVi4jg`%C)J=z0xrQ|CqdZey+%Q~UxQOAd($Lvt_xE+d~utU+4b|`wv4nSO z6Day!py&^QqCW+S{t_tqTcGG4fuer}igLwx+D=hkps0mFQ9+=nPN1kLP*g8aR1zp^ zDNxi(ps2M#QCX-d`n;~tef><)5$PW7i%?Wd-wtV0EG1t_QKeWMvSBEyIzAM&w?k3( z`^alQh!Bc8+M%eE9f}sPLs4ft6m_vfQCB+@Eof7;kU-JG0!51m6fG)Hw3t9q_KR9; z9~DK}ue+}WiWV0rT0)>`Nr9rJ1d5gxC|X9KXjy@x93h?m>P?vkM9 zw3a~8NP(iY1&Y=YC|XybXgz_V^#zJH5GdMEplBn3qKyTLHW4TqB~Y}fK+$GGO;O)s z;pz-Xd9n0>x?d=|IE~GVrQ|Cq+PYYLCj0lio4y0GjpIYnXgd^bYlouk>`*ku4n^DB zp=hifigvI=(KtI4jkhV9AW$?>plFgn(PV+5DFQ`13KZ=mP&8GbXqrILbb+E70!1?g zigp$#nk7&)TcBu;K+#-*qFn@vb`>bvO`vFZfucQxnxZX>g@A@vvgZ@Ua^#XB}Eq%i(79QiY|71 zD7wTBMVH#4=rTJLU2cb>E9_8or5%c{vP03;b||{Wrs!IMqU!{Tt`{h}L7?bHfufrP zif$Gtx<#PqR)M111d47KD7r(S=uUy6y9A2v7AU$$py*zKqWc7j?iVO}K%nSBfue_m znxYGeg?%$1<@7JI)?FBi9?f1?_i(Y4d?iJX7mMd@9g3cCd?YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc z5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiarr2`c$CkGl8Pdg_@#Ai-m_XAm!}00p;o* z3q}3YJ=zz=Qu37)eN!xcGCCA}>-bRgogIq4w?oknb}0JM4n;rNq3CBj6#Zg{qF?P$ z^qWo5?*c`C2o(J(Q1q8T(cc0^{|FTQD^QfHk7q3uY$yZX;p}x4{ zm{8Qw@u8@b9f}sPLs4ft6m_vfQCB+@Eog_Lh3rtYupNpPu_;lMxba}fuiLEik25BT0x*_MS-Fo0!2Lqih2nY^%f{<6e#K= zP}EnbDXP{NHqL;Q?@5oY+t=5g=`Wd{_V=qVC0|L=fcoOBv7u<7<3rIZb|_la4n?ck zp=gjDidMHn(HeFrTGI|igY8f>#HMJdK+!OPqTvEXBLs@p5-1ueP_(u{(K-S}>k1UD zCs4G$K+y&QMH>nfZ6r{%u|Ux#0!5<)iZ&G}+DxEmbAh5Q1d6s4YKr>T7f#K9lwV1Y zi&hRrozmEF9q3BRM6dh)VqQmV_bc7v>j5qut}jftiF_dB}Grw7mwI66g}9|;tF zEKu}`K+&fHMV|>2eJ)V+g+S4l0!3d5HAPR<7p~2KlwVKxXitWs?3YGnPuS{9$yZYJ zeSPt{siEix$A_XH?NIcS9g2RoL(wmGDEie7MZejh=yy95{b7fqKW&Qs5-9pxpy(fg zqJIU7a;13MPElT*S)izmKv7$Pq6UGY zb^=8efugEVQ}k_p;pYrU`RR1?^Ia%vk?zsjmrBW3QnWy+xWJ51)YWdw?r6)0Lx zplEr4q7?*+Rum}eAyCv)ps1HXQE!2wMuDO}0!4iViuwr@tt3#?U#KbSSSqZV0Vxkl z&-6Q$YR~lBr)T;rmrBW3QnYHRIC|$$w3_2X(I7h%t!{^+HSAEdrX7j~+o5QP9g2q9 zp=g*LiiX=1jSwhWOQ2|^K+)O)Me7I@tt(Kpo|0K5GdMGplBs_}Sc0bco|a(V=!II?N75 zhufj(2s;!VX@{bt>`-*H9g2>zL(#D|MaKyg9WPLHf>luF50QglVB*mJi~bfx1%(N%URy4ns!*Vv)xT00b7XNRKe?ND@s z9g1$WL(xq(MK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZWP;{?A(R~6%_X`v~ zAW-z6K+!`2MGp%UJt9!_s6f$U0!5Dt6g?r-6kS#-jLLwN`=>jx%R|w`bX)Xfsg!&r zMbDOsbM^>D&pAF6J#UAi7wk~K+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mtmjXp! z2^4)TQ1p#J(YHcP(bJ{E=^2pn-AU0iq3G^(Tl8J2lzb&cKb4Ai>=lZBc6=!M#STTk z+M(z-I~4tHhoV31Q1quAivF@g(cg9``p2f|UxA`r%Xr#OQC^^^g+Nh3pr}rus3=fW zFHlqxC~7HC)JmYJwLno>ps0;NQCoqc27#h>0!0;pqN+eqdx4@30!1B#nxY>{g?BR` z<$cl*ru`U-c1xr>wJarHNm199#oWH3XhFw^qJ`{Gw6GnD7O_LoqIM`+%nn7}>`>I* z4n>RGp=b%4q9p~2mJ%phTA*kdfudyvik1^7T3(=N1%aX!1&VqI6!jD+>LpOrTcD^> zps0^PQD1?gegZ`+2^94gC|X&dXn;V`K%u6nbIZa~8IbY?={q1@TE_SE(>>ZMElbH) zQnY%@;)wl2(Hf2qMQhrjXs{iMhS;HKs2z%i*`a8-9g0TSp=d2T6pgegT3euK9f6{C z1&Y=aC|X~jXaj+w4F!re5-8eOplB0;qEP}xn+g+b}3lv=-P;{X{(M1A97Yh_!B2aXxK+$DFP0=AO3%_PS%GcyGIERL!r4p&jTb7cq zr0D9F#V&`1qH7!fqIU#}-W4c%PoU_1fuautiar!5 z`bePYV}YVi1d2WtDEdsG=yQRhF9eFd6e#*ipy+FXqHhF>z7;6?PN3*}fubLTnxf}g z77omSWH&w;oaaN)AL$F(Kej9-UrEugEsGZ&6^edyd?@ z^p72i{7QN2J>Nua2uKv64!qSgXMWr3nL0!3{F ziW&rp+6fd@1d6HxMePNOItUbX6e#K>P_%$RQD>p1=;xM&$1@=1r_;^PFQI6B8eLkI zlCPv_;a0^jjtNDJI6f3DYKNl5>`>Ir4n^JVP_(!mik7fL(UNv3TFMSZOWPDJBT%%g zK+$pnMav5mtsqdeqCim(fuf!QMZE-ydJ7aa3KaDbDC#Rv)K8#jC4r*;0!1qe6b%q4 z8Yob-ia^n-0!6C{HAM@yDzrN`Q*=Om24|sGwP*Ubq%o*fDfvo@2Dd8qK0Xu;aeOEm zYKNj>b|@NdhoTX7C|b)7MI-G{w6-0J*0Dp;x;91Y2^6g_P_%(S(S`y=8wnI`EKszG zK+!0HqD=*gHWMh?T%c$Rfub!1inbCc+FGD!8-b$H0!7;j6m2I^G)ACkdx4^{LQT;c ztqPlEK*~3#o1Zm9(Lzm6*jkm6ucT;VtKu#vhN4N14@HyhP&CC3MLXJ|XeT=qO|?VO zG&>Ycw?okkI~2{dDcV_}XqG_HY=NRV0!4ELigpnw+Et)vH-Vzv1&a0%DB4q?XfJ`H zy#x=f(xa)F{N1d6T{YKjhTRd_!GQXZbox+6l-TIp&3Rjo?NS5kCct741OLece( z4@EcFq3A|C6y0QpqMPkdbc-E|ZnZD zP*ZeGtHLrFkn#!X3ys%?q6LfDc)nFB`AUjjZdDw4Mksp4@uBEdI~2WUhoaZ*Q1pf! zir%zC(OY&XdfN^~@7ST}U7Mo!1d84lDEdI4=tF^`j|7T77AX2epy*S9qR#}1J{KtZ zLZIkNfugSjioO;o`bMDWTY;kQ1d6^FDEdL5=tqH~p9G427HW!KY*m<+0V!XSp4`6_ zir!A&n*F6!Dfvo@{%BP^=B!Zkr{hD>Uv?<^+YUwl*rDiOI~3(w$20d(l($1s3p*4Q z>`+u^Q&bcvsuw6K2^6&yC~758)LNjZEKt-&ps1}tQG-BHJAtB#Kv7kosJ%c@2Z5rF z0!5t!iWU$k>MT&yMWCpwK+%FiP0??y3O8mz$^+8lqTfT&A?dbgq1L73D=Av6b@8Qh zLQyxzhobIwC|cYOMN8PBXh}O1EoFzIrR`9(j2()WwL{TzHbu(|6s;gow4y*!4}qed z0!6(9ih2taH3}5<5h&^_P}EPLXeEK7{sKiS3lt3yC>khGw2DB{sscr;2^0+yC|X^h zXbqvJXpz>1-!mZPAJWawqOEJs^zTn&&DN#lD=8Y*y13x^p=h|{L(vF36s={4qLFqe zTH6jq>)4@aT{{%5XNRKo?NGFVP0@w|MH>keZ7fi%=3KVT8P&7uMXnTR8u>wUq2o#MIC>k%+6b)%zSR(^cPXAI- z-Ox~Uc^VU1my)lfXiDqi_7{et9UUKvcCtg!R67(+vqRBzI~2{ZL(xn-6zyz>qFHt* znr%}wN1$k~K+!G&MY{?V?IuvPyFk$%0!4cY6zwHYw6{RfJ_1Gi3KZ=pP_(~5(E$QQ z2MQD&Bv5p)K+z!rMTZI$9VSq8xKL9xsdeGt3`qI5bn`Pg6tzqDXh*azC0|L=F|CW2 zTpWsyb$lo~&JIP#+o9+LI~1L0hoY10P;{~#icYaZ(W!PQI?bl&bb+EX1d7fSC^}1^ z=xl+aa|DXc6(~ASpy+&oq6-9yE)*!bNTBFqfuc(UiY^r>x=f(xa)F{N1d6T{D7s3Z z=xTwYYlNDjqgof9%z%_fr7tud9g4c8XZqK+E+t<{(T%N(UtJoCZgPAmy4emzx7eZR zRy!2kW{0BN?ND@w9g6O>L(yG!D7xFG=pKQhdj*Q_6DYc0py&aCq6YeSfJ<; zfuctRiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq8EjlqU&21s+VPo z{z!0c2t{@2w&S_%}k5-4gd zP*fHuY9mn8R-mXsps1ZdQAMDrDp1s3ps0gDQAdHIP69;>2o!Y|DC#0m)K#EpL4l%$ z1d0|GC|X3QDf+W@;p_}Z`Necw^j9c4C3{`nqUBQZl@u*rF5YuZC|bhtp=e1v6fI?k zqNVLnw2U2!mbF9Ca&{I6b%+A8Y0vbbt@M>%z%{F zNso)Vmut`T&q%jLL(8S)D=Av5T&%l36peIzC|cVNMeEq1Xk9xLt!Ia#_3co!fgOrA zv_sKGb|~7|rf3s^qEP}xn+g~(dM%cbNi zDVka?u5)83n&$XWG~EtGGwe__(+)*D+o5Qd9g1e#p=gdBisss(XcwEJT?LAE6DZnU zplA<)qCEwQ_7W)CTcBtkfuel{iuMyI+FzjP0D+mx)-DZcP+wD+vhaHOUv_sKdb||{r z4n_Caq3B*a6y0Z2biY8+0|G@43KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`| zv_R1_0!7aX6g?+U^t?dP3j#$i3KYF0Q1r4u(JMkt(M{#TpBa$y0twE|q3GLmTl8wV zlzb&cZ>n z1&TfsDEeHW=nH|OF9nLe5-9pwpy(TcqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7lEQ* z1&V$XDEeKX=nsLSKZTm2*UN>$8IbZ9>CyEYp=ekl^;fx+d?iJ>HpLz83Pt%g@k~Ax zwXj1`!45@rb|@;^p{U*tMI}2FwX{P~D?1dmwkawL6txj3YAaCGAW+m!pr|5HR23*{ zFHqD$ps1rjQ73_-1q6yZ3lwz`DC#Ouw4gxILIOn#3luFPP_(E((P9Ec-GrK=f69eJ zGa%(r=_h9Y4Mlyj*VT1zQ%b&)qNUmtFS{ocE$#SFw2U2!mbF9Ca&{Ls3sV6!o$x>Mc;zC{WZ#ps24vQ9psAl?00V3lyy^P&7cGXrMsRDgs5T3KXp- zP&7!OXmx?2H3W**6et=jP&7oKXsAHZFoB}sLQT;UZ3<6kK+5l@+oC1g)Sl`0Z`*ky4n>>V6m2F@ zw7Edh76L_E3KVT6P_(r`(KZ4_qXmk#6)4(HplFOh(e?sGV+D$K5GWcaP&8hkXo5h| zM1i770!5Prilzt@?I_d~jcilsaDS$#n7-<`b|^~!;7r|4ZA!^kQZ%DYvEPHCXr|*s z(av@#nq`Ng*>)(JV~3)-b|~7#4n@1#p=dWd6zy(Pw1+^^o&rUC2^8%uP_&Og(Y^vj z`w0~7FHm%VK+%B$MF$BK9V}3Eh(OVy0!4=j6df*5bc8_Bkpe|W2^1YIP;`ty(Xm2J z(X=*&tui3xv(p3W>7nS_G>&UiO1_e!liC#bcsLZD?D$Z0iXDnhwL{Tqb|^aC4n=3! zq3BFI6rE*5GZ<5py(-qqNfFlo)IW|R-ouPfuiRHie3;XdQqV0 zC4r)s1&Uq~D0)?(=rw_&*M*v*TiX;q&VZB;Pd7ieg`!2X*VVnzrj&doMenpJ);|%7 z-gSH^de06;@7tm113MIbXosSY>`?Tv9g04&L(!*pDEiE%=yQRhF9eFd6e#*ipy+FX zqHhF>z7;6?PN3*}fubJ-ihdL*`bnVZXMv($1d4tYDEdvH=y!plKLm>Y6e#*jpy+Rb zqJM;%qPN-**q>(f^q-ws6s(=+{l+mw>8q^QugxZYEtsIKjQe5PNtLs7jQib{4U zYH5d}R(2?AZHJ<=9g5o6p{T7*QG-BHJAtB#Kv7kosJ%c@2Z5rF0!5t!iWU$k>MT&y zMWCpwK+%E%MGFZOEi6#9h(OVz0!51n6m=6Q>Ml^UxIoboLQPS=ZDHpONcq|Xr$yV^ zbF>cG>*|(lTS~r?qGj6_Pk1I2E$8^SEn40VMJw2$Xhk~|^{_)xPdgO#vO`gCI}|nA zp{S2dQD1?gegZ`+2^94gC|X&dXn;V`K!KuF1d3J_C|XURXplhB>HkSBw7o#lSb?G)1d7H96pa@snjla#QJ`p&K+$A@qA3DJI|>x-Bv3R} zplF&2*r8}oI~46@Q?$20(LMr2`wA58Cs4G%K+ypLMF$EL9VAe6ut3ov z0!4=k6dfi|bhtp#5duX=3KShBP;|6F(J=x=#|ji3Cs1^}K+y?8P0`G@g`pXca{KgE z$DKpb3F)@z#I~j6D=9j)ZE^g|q3ATnhoaN%P;`bJiq5n{(OGsVI@=CK=h&g>Tsst< zXNRKmZHg`sD7sLf=puoliv@}<5h%J;py)DzqRRz}t`I1?QlRK6fugGgimnkTx>lg* zI)S3=1&VGED7sOg=q7=pn+1w)5h%J#D0)_)=sAI+=LL#h5GZ<4py(xmqL&4VUJ)pIRiNlKfuh$1 zirx??dQ+h2Eup69j<$toGa%)q($8Jr8H!5jJ0NejEhS$`(fe(S-@P7+K5%>}`p^zV zAK9VkV>=XmVuzwn?NIcY9g04;L(vy@DEiW-=qrJuuLX*}5h(grpy)e+qVENYeh?`7 zQK0B2fuf%UihdC&`cN=r4hyzXgi^5h(gspeWZ6Ps}OG3pGXW zwk>peBU5xsx-EJy6s?`^(ONW=lCPwwzM`>Is4n-B4qN+eqdx4@30!1AKiaH4tEg(?TS)izkKv7qLq6Gzt77{30SfFST zfucnPiWULyUsU7%=jfubb@ik1{8T1ud3X`!a5uA#6^2Bh33!6`P>p6O?gw6iB{ z4W;BODO#bSxYs+OXhp||q8@fA>S>3fUUn$zZHJ;pI~4V?Ls4Hl6!o)1(MmQ&{RN6v z7AP7ZP&81WXcd8?RRxMx6DS%aP_(*0(Ha6pYYG$%7AP7bP&8DaXqZ6JaDk!`0!3>H z6pa)pT3euK9f6{Cg_@$}8VcuUK+5-}uR1OtidIjg)@vvwUrEtM4aEoE3q>0{J`` z(GCJd;{=Mv3lvQdD4HlxG)bUnvOv)kfubD+igpqxnkrB`=6~9g6m`L(#rAMf(X9?JrPtfI!iK0!0T26df#3bcjIFp#nvR2^1YJP;`Vq(UAg0 zM+p=iEl_lfK+&-RMaKyg9WPLHf1qEd z4W&=t%ibtcbVfsQgO5YenT`)dXW60XY&#U4V~3)1?ND@{9g5DkL(v6xD7w%NMHkr= zT`W*^i9pe%0!5bz6kRS*bcI0Cl>$Xq2^3u|P;`wz(X|3a*9jC|FHm%YK+%l?MK=i) z-7HXai$Kw>0!6n86x}XRbcc`uX{f6^t)VbG15%!rzUp{-D7rP>7TwuUO1_e!dmD-; zeHx1Hb9^Ye-ws6&*rDh_I}|-+hoXn=Q1pl$iXOE?(PMTfdfcYy34x*~1&W>$D0*6; z=ox{cX9bF$6DWFKpy&mGq89~p`az)RM}eZB1d4tZDEdX9=vRTF z-vo+&7byBepy*G5qQ3-+{uU_uN1*6mfudZyc-l@;UZALjKv6-Us7|OU`kLO6oRiJ1=fue;3iWU|qT122|QGuex1d6%|6m=IUT3n!L z34x*|1&WpuC|X*eXc>W`Wd(|s6KaY|?Fz#)AmvNaL!p-KYR~llZjp`U+m({9q^M`R z;>2%4Q7^}bqTY5WYP3U9A3GHFwL?)qI~1*Chob&=C|cPLMFVV#1_~6dB2cudK+$Rf zMS}#2Ru?E*L!f9)fug|zMMDINh6)r76DS%kP&7iIXf1)Fkpe|)3lyy*P_(W<(RukAZZAk-AC*sgG72BiEmg)7zDjucYYg zcEtfdhoW;FABxVkL(zG5C_3K`MHkqi=t4UbU1W!%i|tT!i5-eAwJEwxpy+aeqALW7 zt`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*py+miqB{hN z?i47xOQ7g(p{D4}c7<&-Amx7Pw&<)-v~RjcyQf_#`AUi&Xjk0l*HHAJ<3rIyb|`w- z4n>dHq3BUN6g_5#qQ~t}^n@LXp0q>JQ#M6U3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JA zMK22!y&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAk-Ay*RF73 z2BdsddRlgWD4LYM1o>gRQu37)ecG=0(C?w>GslOb&+Sn3g&m5%v_sKXb}0JV4n^PC zq3ByX6n$rhqVH{reh?`7QK0B2fuf%UihdC&`cN=r4hyzXgi^ z5h(gspeR>~r|lHw1&Ue-6cq%D>I9040!8%#MJ1u8=;L;U&odz9)6<>UC!uIgx-Dv1 zDJ5S?QJYG!^Z&cgB^<6*`cUnhoY(-irU+usDmAfI@+PAlO2i{uqo;+P}D`B zsH;HHf&xVg2^1|XP_&3Z(V_xHiwP8U6DaB~P_(!}(GmhhO9~V%B~Y}qK+!S+Mav2l zEhkX4yg<plFgn(PV+5DFQ`13KZ=mP&8Gb zXqrILbb+E70!1?gigp$#nk7&)TcBu;K+#-*qFscVqD?D>J2N2VGt;-uHVZ{<(=+{D zE2ZQsDcZAAe5*w$+RO2wXm2|d?PG_ceeF=RpB;+!w?okZb|^Z~4n+sqq3B?nqC*6V z4izXmOrYp+fubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vm69kG*6ev1Lpy*_QqEiHl zP8BFRO`zy>fub`6ip~^jigvFQ@`X&%^z^msJwnmP>9**sN-6nDiq5MP7tj7Vh^E`3 z^Bo_GF0ezq$PPsp+o9+ZI}}}NhoZ~uP;|K+imtFJx>BI%DuJS_1&Xc_D7sdl z=sJO->jjE#5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ37x>KO&E`g%E1&ZzwD7sgm z=suyQ=$uMntqe%HOS<_vHxyl&o}=AgDJ5S?(ZiMElQu37)eNic1(<&5w>G)9el^u${wnNc3b}0JR4n^PDq3C-%6#Za_q95&0 z^pj1|&jLli2o(J)Q1qKX(eDC9e+U%)DNyv6K+)d6fdeLyUsU7%=jfubb@ik1{8T1ud3X@R0;1d5gwC|XXSXnBF66$FY_6e#K;P}EbP zsFzSv)V5ma+9p%9Qu+=^L$&ry|Fm>l)Vo?rzLKJT)#54*p=c$?hob&=C|cPLMFZ?m zG|&!3tJtAvRXY@|W{09db|_lirf3a;qBRAI1`8Ao5hxleP&7=SXt+Sp2!W!t1d2uq z6s;{#w2na0x&lS(2^6g_P_%(S(S`y=8wnI`EKszGK+!0HqD_UGqCVBam<&j{MS70b zHx$iEkFGbXmXfceXsc>*ze*_D+VP=i8#@$@wnNdjb|~7;4nXvP0`^3MMnq}9Vt+Blt9tZ z0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(a8curwA0CDo}KqK+)*}MP~>UoheXsmO#3twhH%6q4qpS?rT8)=+dEhS$`(S_Awn@*wVBFBfKi|tT!i5-eAwL{Tm zb||{s4n2C$CV`@x1&VGFD7sak z=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj2biXIRsdQhk-I=@Xlg^>&amRVeB2cubK+$3XMco97x(gI7E>N_DK+%!{MN0`3 zEiF*Aj6l({0!7OS6fG}Mw1PmMc;zC{WZ#s41$nFBBHe6kV9U zL{x2Gd!~PIhNrG?`%?0i6s_F8xa6XtXn^BG(Lg&Ctzw6wRqar;njMM;*`a84I~1*9 zhoUv@P&C-4Xox`3P=TUh0!70Gibe<&ttC)2QlMyUfueN;iq;h^BlOeIIRG$A_Zr>`*ku4n^DBp=hifigvI=(KtI4jkiP51UnQ>v?-b-P&8Sf zXo^75jsitH2^38gD4HfvG+m%*hCtCwfufxSie?EE%@!z{BTzI~plBC?qFn`wb`vPt zU7%Zh|huWd&Fgp|-Zik{H>`-*1P0>*TMMn!19V1Y5tU%Fm0!7CQ6rCVY zbfQ4fNdiSD3lyCqP;{z5(P;ujrwbIFAy9OtK+#zOMP~~Xog+|mu0YXw0!8NwHAVZj zFT9)qDSwj9y8S}Yw`p9^zLb3B+T~i*Ezzpm()nEFs_a{~xymyMT;;p$JGLz=?Xzcd zZ7Th;hvt>a=52Gij+Hao<#Jsr?^ScTg)2*U%;maOrY?}nEm^stOD?x;<+lZMxfLs` zFOtjkt{k*jF4wQ}ME6{7K&7%|F1K1`^QCjSH7jQ=o68NWe6V~jH?p#9k6doO%Jg2j z+(wm~8gsc#D}VIO<+iM>**}*XT{&bxF1LN*R9#RsLEpmpiC3WW!wUu*zW@=W<6?o*9+P9arhN zc`kQSW$P_-xzj4=ZJo=VRrzFeE_YsK#WA_uMU`1&bGgeZw~fo?uB!YqA(y+ZGHh}# zcT?qv9do(cD$h;L<+AUU&&cKOtBl?`mwTvk!R%b_vC3z2bGfG~J+ohl@myuj9=Y60 zl{@yz2&gDLL|t5xLxVm5Ywb<$kJs zaZE1vTc!8$x!hmXT~5p{|9thXld~%zUu|((b`9jKBhSdLf_(Luv$E?TUw!GE>`KU2 z7d$_^7V_2YFU+oneD#uxv+E&WO~1{4$$T~aI`U=n)%5$MSIk$_F9hzLucqJV+Am*C zzmju6zM6ig;%fP7`lWbl=Bw$qnhncW)32o(nXjhbE3{s|`ptdWb&{{9-|VqzzM6hD z!OucrTC;JSP@{lxc8`D*%+-P`ij z^fQ-t<*Vt3=I+Z^(@#A;l&_{ATX`&BO+R<=RKA+Nar|7qn!fY*QofqLb@N)jn!fh_ zR=%3Pc=}$xn!ft=QNEhKeDPVnnx21tm9M5J5Z~pi=@H;h`D(fg|1Dolx50nqbM4b7 zP2EMcPq_}~Wmo2a?9-}auD(b1SEprK=5ob8ol{!isqE!^-|Vfkk3IWz%b&H_GWlHR zWz&m&yB(X=?Db85y3EYJU65a?A+=nWOlmIQKSqc2nw4XGQOL%Ch69`4?Aq+}H9s(3 zb7J;h@~gzSJRP%YjO)@^EygDKYz&GqI-T0;F&=51jWuFSOy^+D+UPny8|jQMnBOSh zJC|GNi|qCz{ja!Gp>-}_%`er^puOzdxdnRW*XZh8F4MJ|Z(qM=ms5vyO~-UD&iCdm zI^Q}ZyX?Bme-aC4@44&Y2jsKMxG{VC1&=r&pKHXW{Js)15=={-n2> z|IhsU)a-tvkQ<*J(jxz7L)%o3;DQIWtliH(~tTSrcZ@_qz1<*;^0nHFMUKX;bD**=0hm*W?+~CiEIR zb;54FdQP1&ZtT=vvnP+8HKEt63DYOc9y`0&gg#?t&zU=Z%8XufX3Us6Zt~bE(`WaZ zG;Z9Ov9qT2YV19x@0dQl`!tSe?44qdEcTc_WBP<16UOc^rAK4$o_%|ySNF_b{U2V{ zYs&O-Q|FGK&}-V*ag(P^|9|~#%-((W{FlU}$-M^88b5c+^ch2E%$m?+-es}doLNm5 zN$nEZXx5A!v&(#TuTe9{&f00j-05RB%|4b%8%>=%d(0+-`>(&!|B0(`jGIbn9s$w^ptb&a1geNHyAo1jrchmXn5 z=D49VrcIkMJ!_dbV5X##uBBXd!(MFCS?HTD7CZdU{uJ}|g-Q8h`@%xq`WN$sZM$VJ zcJ0=PotJuCizl4_-SXlaR{5>c;w8LWm=?y#f=)U57se3y4Z1>I{Yvnr?%jvIn z#qQ~^tT)Y`*{k~$JJsj2bJe(F_hPptiX9f3?>=0B-!O(&J!V~6ah zUcHLl7caI?r`5gKq3LY==hOP%o~=dd^MiWyDt746bOxMAR(q{o?2yiR_PW{!SnQtu zZaOzh{4YMv_Vo+&DlW26vBNq|2WO}BzkacH@nx4veaB+^MYCi6TOWS+-v8Ab{}&f~ z`bhrkkMBR%-v9RltV#X9*I-gVAKd@{5p8+bf9E#n|MQ=OO*gW|^kJsEjsJWb`@g+y zZC~HHxX5z<_039r>c$>!Tji;vJ95Zx-P5abNdzeF3n)m)zmijio-#+u+@6h>9GR|Nh2lSu!Rs);P)7YNybcy)y@laB73& z)P^*lLUsvcZ#I7Jv}wE7PAT5DpLaYs!pif`Kz4!7JLP%rq@VXOtog#oE`oT&>@3$V z#_UvTFU)rqR(5E1;WfQ7yI|wEmFAsTc7D9mKJoT_o6pD4c}Fx3^{%or9!Der^F7S| zKlR{p*n}PCPRjkCd@>NvC7K^%W)JtLPns}h!u0V|#!eqIb;k5bwM#F%zO#=ldwe|K z6&@dVzvhb~!&Q6pd6ylF6EPr()Ba_KuUtJ~QH+44HSH z(rrM~8x3wgbHg%AgEv{Lv8m5f=N&f=n0GRb&9Fh_u(4Ts_7TLprEi|I?53vaoisMH zZOq)(T5qpxmfSeP)zS>uHI;n;wd1^yu9Bvkx#p`iyXA|s(wLnWFE%z`8uMMbE63rk zfSQ|hf&-c_s_cTSy^lWLS@RX&*nG`5&Ue*k*G}z_<}2BC&^RPM_H+%T_cUoU6v zYVV=hMs|CVy;akRH@zymZsVxzt|VTX_km>YYR6}{#<}d4YgX-2X{`Mf_oK}k8k;%H z6WFXEyNk|FfA-`Vv*ygZSIn?E7qu&W-t|52{yY0LX?l}%os1eYV!gqmM#ekNE|%K4 zo6kb?b>G;0vYC>|8e;oZZtm{q3S}%pliJb-ru1`HIZWMO;XY*<+L18)l!V z@j~sg9FwlyxWykct9Enwt+l~s-G&Yv*e!jvr)Oig z^!1+J1N!vqw(P74Qzwj_Jz=?SJ*JJDId{;w?6RD&TaRgd`(|Oz(@d*%ug zXLjo`sauZ?`*iD(eZgbUxa_Dl^qhr`h}{ zF*!|_ar1-4=7)%lHTq4rLfP$foUP_7qvn6!on907F=PJYJ+jBB%@0vIN)M_w95HI% zJ#C{$q|J{mn;%p*Kc>tco$^%s{77eS9&C?Cn;$C9_ejyh(dLJRK2;js1gD3LwM!_7 z)*c%+T?FX?X*@=4`cP}1nDah-pNR96L!KU(?lkYV(c{nN$B4}j5$T?H)z5nbI`5(7 zyhoAqeO@(xGBiI1bWJxu0-SdZ)*eRY)*3o=m2S(XPn^NCrga-WZHEct$7c_}H}w_P zrq3l`IbH65{+X3)lYL3}-|SEJ#p}Hq+O*B3uQL0SzM4F^q052w2Ne&lJEU-Ei(~S+ z!2`3`j!j>j&ET5MW&660`A+%Hg)aH7`33U}wBS)FgEuaalq8qIAw z@6Bqj{~wIqb(oap|M%hDof&4?Aw^77P;5ckRs;(SQ0xR0#6$(VMaAy!PHeFQ?8GiC z><+N7f7iA5=k&m@e>@Mzf%m>&yZ7z@r?WG=!*JXjJHI}Et-bj1&kN17RM-5SA+Jmy z&9{S!RH{o~UZ3MfsqWuj?s5$5<&s+(($mCx^3m%atj z{JWC>T;@u@zNO}Pi+1VdRsLuH=L^1F$Jce;scw`1y~a-eL;UZJ^nX6}3{UT~sbl(m zO22On>ATGNccmfyQnQk0+rgHN! zeJi>7I3SKg6^OE=N%o#)8cqt9Pi5C??@l#kvP7Yey{TWIF7%i zUqIe1(l_4nu~YhE%*UnTxO)1vhx>M`}R0~m3{;Ao*l=Y302;! z$8rDkdzSanaeOd+e<<%~;#gX+*zMvtD1F~Pzkc&Lp1Me}FN))9={GjN{=+yf*tOV8 z#c{+E#ojZH*QP&!{PuUo@tb9e{aYM+r|0RPz9f!stX%AmM?7IDm<4Ok<$93X(_(8=!DUOdH zQtX%GSUbGf^Tl!FBa6L#9M7Fl?5pDV?lHywGLDNKSL_~f+~tH~?-$2gPAc{Tas26& zVmF*x99KELIIb7RBhM`MDRF%A>|(zf$JXZ+dx1C(yP(*^<9Pl>#l9wv@23ZQS8|>$6u~3cKN#ExY`ZHac~?bOe*$iaeVsbV!s~8wzn0# zQye$Dqu3+kc;Vz?Ul+#@?k@JXaa{7gV)u#T9uE}zpg7*~P_d`P@z*KEZZWkuuJLGb z+#rs}JYMWG;`r>7#eOr6?Vl<3!g1W6uVy>$G%qV zL*h93jbc9%$KT&7cH{KoxaK>>aicg+e6QGN#qs$W#hxC=4j&b}a~!w&q}Ze5clV_QS3$IxXoY19uvpQ(=CMj{%?-sXX$}AdH)#4Zs{Afd9NJDap|Erc^?tS zd(&fb@_r(Yf2RlMC+}6`xNqlT9~H;@)5Cu9>z|5am-Nt{ zyjPFo;5crakCnQ*;jwqi$5wT9W8*kJ`jK%wC5{)y@wzxpj^iV7d?AkS#PN$b{v5|r zdTdU1gU6kfyhd9m~$A#m#XdIV|V~;qt$j7Gi{$r;@^ZQ9R zcbbpm^6jAX{?pBox`y`YF)Y#Rx{o_>kMSc$rsMd1isKkBr90W<>$>NAwRPP`jvH6k zJ>3uQo@4j_+;nVy)lT{A$mxssqsOMRnqM9-N_u3-oO8rJ`6g$)>*6i` zTXxTn>xlQ5E?Zsq9n*slMy2mC%<)l2?=xbL^hRrLvSIfT1NHpex%>N<{w?sfAiawius?n%dg8nmP|kMpXvYW?ed@B|9;##AH9?R z{PK_d=bdhv*7Z+6^N$|uqz8$n<2>nSew+L=f4ue6PnRLRST`lTqFXZNhnLn(Vb1s0 zKfS-9DdhK;EqQ-iq?etOUab3O+4{N@=LlZh<$vDpfNu451M&&+!`qEYd(Mx0+K~F@ zUsL|Lx%;^3X2-ui?tSU~bxzF>?{9nxbH2Y9)BE%Ll5V>H^ZrguFFPl{kLl_C<+t<0 z>n5f!=lh#6$NOuYUgz>%oL+WLeji_^_jh4FF@AX6`DxGj{=QG|FaJ5^UvJy=)BC$V zy`0a<9`cW4R!H};^OZsT$gj&k?~J3jdtzXH-QakeeDHQt<7KaEw^sc>?>o2rar2J{ z)6Y3C-|RVlz4h(lLMB{39RzzmoSM>FxGPF<+16>z@4n z^6z{8nEu~LFV=m%c75Gi`Gxr5{iUm_f4yDf(E7UcDg2)w-fqsvH1+L1cKP&8jD9Qj z=(S?6UY*ldJ$m$<KNyC~~ zzRQz-ELAsuy7rtsdHq>a#vRe6yw39*K0kQckjH0#-8mgMDvs&DJ<`v;($C@Xa_6T9 zr`&P$hN?teZ`d1l8s zUY=);m*@TG<;LObHeZ%A;<60<*JYV6ea!j)^D)aa7f5}<|MWipx-93X%hKtek5itx z&>Sx>Jjct6{PS|-@UG35<=nU|o&R-NI;W4>GRLWDbMUX$IJcZczK0?UTz$|M)PGMe${_nmKD>-T!(yf?P=KM^QuDToQTkM~|o>$*^Lb|Ek z&`|lknh(_pDVF9*SMm)T&X>MElpab|>6kuAm(I&?HDvzb&8b?>tFiJ-x)t5fSnZoW zdzH(T{0)PKa`mP3CZ#Uv4NA*(STnzTd-~9&9&>M+Uaq7sQPj1_|4AQza{7qXa(RhL z{tG^h`B{XQjK3MaNSZzC%1gyuIL(A+>6i|0k}F6IJh z_DfHG9drIPSEws@k2znOiN^9V=S_2^^!!;d=Sj0?x>!A9cg#Cou3oX{&O2SO-myF6 zoi16Q*mLEbE?VE%?ek8TtzYbRd8Z4vLhQDAr%ShD>^6C)i?>qj)_JGPw{q-OY4=K( zZGG`>yJg<#@~s}bG4FKw)`(rrJ6*p1v0LPwF5jB5D|x5OHz0O7 z?{xVF#!lZ57|<(SzO`aEq}@ARzO`egn|lL#r^~la?8KmDx!kohE&cg7U62ti-u!o) zn>J1|%Ij7qr8mez*01Eh{M9UEgE%#WY#1|yY!owu42c;+hQL@YsZmh)u}I z*o5pDn~6IMm)L~t8k>;aVi!UNmA+4Z{!QDbtFiLnLdZ_( zYO1_@HOt9D_Np}h#lU(6)kbPr@ko{tYko{wZkON|dkOO0e zkb`0pa&T-y4v9_3p|J@$EH)vB$0p>6*n}Jzn~@$0p>2*o2%In~;-Y6LNBFLQaWI$f>ajIW2Y}WY5xE=_;dX>GWBrJhl+>d7@E1 zy_)4@A!k?eUm9(`4ml@I4I$^o3?b*m3?b*o3?Uc93?UcB3?UcA3?UcC3?Y}q3?Y}s zB;>N#gj^n*kSk&na%F5nu8K{_)v*b=CN?40#wO&t*o0gkn~)n~6LMp0LMFu~YL=6Q z+*iqep}1Md{c&mtc_3y8c`#-Oc_?NGc{pYWnG!REOpO^r9*G%39*r479*arH6Y^|qLY|9F$n&uYnHHOn7h)6gVr)WQicQGNu?cx4HX*OZ zCgio)guEV`kT+rz@@8y8-il4g^w@=vdrF(9KmVpmy0u%rw-B;HzD@FWHOt9D-mm1p zY~CznMw}W#K8P7YK8zVcK8hJaK8_heK8YDZK8+bdK8qPbK93nfzKBW4m$3=?DmEcs z$0p>P*o1r=n~?8f6Y_m*LT1J$WL9iKeuz!TkFg2)DK;TL$0p>L*o4fEO~|jY3HdEH zA-~5aeckDvQyQKrupMTR!`L@S<%|dGD=IfBU`f8?=pZTI(U&&8J z(ER)MKyxPoQW8fua=!idGURT3MiI6@j8v1&US^C|X^h zXbpj){sKj73KR_xC>khGw3a~8+5$!E2o$X=P_&*v(IBBvv}Ap$k{%3KyCh!~EftDh z&!h&|SF^9IXruZ{ekzn^MMIn)iiX;uXk$ARZDNO_VRk6m)DA_P*`a82I}~kUhoUWQ zinbCc+FGD!8-b#21&X#4DB512Xa|9!;Q~b?1d2uq6zwQbw39&5D1oBU0!2Fu6paxm z+C`vfSAnA41d4VSDB44yXiuR~v_XAo{RE_TXPV^=Ls5SEi1OI_YW9^CjjONZr_yOw zG~W54XkR-N?PrIg{q0b6fE|hsv_sKBb|^a74n>F9q3BSXqQeA=4i_joLZIkKfuf@X ziY5pY9W79Fj6l(`0!0%AijET~I$ogY1c9Ox1&U4*C^}i7=oEpXQw54n6DT@epy&*N zqBDg;(cbl?(-V+dpL9>VyiX|FwE2EkeKq^aiq5OA7eL(v6xD7w%NMHktj z=wdq*U1Eo#OYKl}nH`EQw?oktHbqwo6kR1ybhSXyH3CJ~3KU%@P;|XO(G3DcHwqL@ z5-7S!py+0SqFV%tZWSoHO`zy@fucJEitZFBnk-Osmq5|o0!8--g`#unOK&6~wL$qy zzvqUc`Ld#W>#NyUR`g(fB|nu{v!aKbABrBfL(vpF6iu~5(Ia*!deja@kJ+K-Xxb*;iKd zVSOb(6N_DK+%#y zp{UYOx;_D^P0U|VY|&8M)Bhk}7cJFL&AzgtoF9t1+o5QAI~4V>Ls3sV z6!o%0QExjG^|3=yUpo}_vng6ZplC&bqLl=SRu(8)MWAR^fuhv}idGjWT0@|yzd+HN z0!0G^iUtZ4ttC*jwm{K30!8Zz6s;#vG)SOmut3rJ0!14Lg`#B|O5Y_QweINwkmY4V zQB%IBzhOf)`^t(oZm8s^GHt#t+Qj*xXqX*}Hnl_1W_Bpr+zv%s*r8}kI}~kYhoY_R zP_&Ir(Y69b+X)nHFHp3DK+$l4q7ec`BL#|f6e!wBplFmp(P)99odt@<2o&uiP_(N+ z(QX1oy9*TUAyBlZK+#x%qP+x)_7)07LmEnb6Oh_|`MPLmC~A{GqwUjB&Azgt{TeFy zsc@SW?eF|hbbuX-4zxqjL3SuQ*bYU9*rDi9I}{yehoZynP;`V%(UAg0M+p>75GXoY zpy(KZqGJV$CJGcCCs1^}K+y>TMJEarog`3nvOv)(0!60^6rCnebh<#%83ILT3KX3s zP;|CH(K$k)XnaHI-~^;LAb*Ky-%#{uzAieqp_+YVMHe3}{E4s+}q3B{e6kTG6 zqD$>ibeSEBF1JI`6?Q1P(hfye*`erao1$w3imnwXx=x_zdV!)F1d47HD4HZtbdx~Q z%>qTY2o&8aP;{F>(d`07cL)^SDNr<7py)1vqPqo(?hz=uSD@%Vfuj3`LecpRrKt%> z?X>y?=YmjF&euf`G*q*%tY}I@B|jB+v!bca4@HmIq3BUN6g_5#qQ~t}^n@LXp0q>J zQ+6nN+73m}*c3f0Q1qNY(enaD(*%lM5GZ<4py(xmqL&4VUJ)pIRiNlKfuh$1irx?? zdQ+h2ErFux0!42N6ul!*^sYeBdjdu83lz-|3Ple!l&Z@nMOWl|`VWVq&GW764;rf3 zS61{%LnS|zd$XcXoga!mvqRD6b}0J74n<$uq3A0+6n$-nqHpX_^sOC=zOyO%UZ7~E zK+!CLq8|i`eiSJBNucOwfudgoie?KG{VGuOn?TX;0!4oa6#Xes^p`-<-vUMHVaUbZ zc8cl+iW&rpN&-b?fuf2~DEg?Ov|$2L8=kL=J`P2{`>I!4n^(kP}JTIMRVDqsDmAf=CC{Q$yK+(JcMe_+1%`Z^2fI!iL z0!5t!iWU+mT3DcH5rLx40!3W}iWU_pT1=p*t3c7>0!2#*6fG%Gw3I;6(gH=x2!*1? zQt8YDq&7A`T&QKKxTpU{zAjp}RL#D!qUB4K{7*?VE9&9=P}I{7MZN4$)Y}e4ee6)w z*A7Mf>`=6V9g0@8L(xh$MJo#wts+pgszA|d0!6C}6s;jp)L)=zO@X2T0!0G_iq;Y+ zT3euK9f6{C1&Y=aC>kVCG+3Z$eSxA41d28kDB4J%XoyfK>Q*Yfm4MW`<(op?L(w<+ zx@c&rntf$Oo0cm1pCV~iw3+im(dKq2+QJS+TiT&$D?1czZHJ<5>`=6=9g4QIL(%p& zMLP%-4HqaHAy70@plC;dqMZbaMhO&+7AV?TplFOh(Jlf-y9yNTCQ!7yK+zroMSBVq zjTI=`OQ2|Pfuel`ipB{PjTZ_0!1eX6rCtgbdo^P$pS^E2o#+vP;{C=(dhz3X9yIXDNuBlK+)L(Mdt_O8%#iniXB@{7`h69f~fuL(vs> zD7w-PMOWFO=xRF@U1Nu$Ywb{UolVj80!23n6x}FLG)bW7CV`@x1&VGFD7sak=r)0( z+Xag55GcA+plGr{(Om*XcMBBVBT#g&K+$~yMfVF7Js?o@pg_?>LZRrQQt8G7r1n8p zba5#9B9Dhl)$A)PdbCu@|CCmPuZd9X*(1>V~3(=?NIcb z9g3c}DViow^nyUqivmS22^767Q1psG(W?SQuL%^rE>QG_K+&55MQ;fdO&2J7TcGG2 zfueT>iry0_dS9SuhCtB=0!1GR6n!KVil&xI>96V5)y~OZb$lcgt(>omJ}ydJAqouYbyq6UGYl0Z>epr|5H z)Iy-BDp1rY6pB7Al~zbVYQ6K9t3L}x2j^SYEz8yHD=TVUuH=8pulc&Djq^iMTRRlB zvqMpPI~2`jhoTO4D4N?2MIG%>G>;vM=CvuBPoQXifuaQjiWU?o>LgIKkU-JG0!51m z6m=FT>LO6Is6f$T0!3W~iWV0rT0)>`Nr9rJ1d5gxC|X9KXjy@x;{{}g1iqTbFAMSbj0)YlG0{p?V*f*p!hv_sKK zb|_le4n?cjp=ec`qSXY7Ru?E*L!hX?K+&24MFRwi1_~6dB~Y}sK+!q^Me7O_ttU`4 zNT6u2K+*aFMH>hdZ75K*kwDQ9fuf-TMH>qgZ6XwkdX!6#CLpy5X_kA2qL1=*(Xetg z`^t*8C|B}7CEBcLOXr88t?W>=wH=DKu|v_eb|~7;4n^DBp=bv?6b-jS(FmKOkpe|K z3KZ=mP&7)QXtY4l&H_ba1d4VMDB4w^Xg7hP-35yF5GdMHplGZ>(Ov>YdkYlpBTzI> zplG~6(Y^vj`w0~7FBFP4E0q;*hpk-AzOtf2%9Z?2(KahO)cK+4 zFgp|-Zik{H>`-*19g2>!L(v2~6di4cqGRk(bgWI$M1i8?1d5IqC^|u)=tO~{lLU%R z7AQJJpy*VAqSFM5P8TRTL!jtPfugenip~}&I!B=BT!EtV1d7fVD7rwP=t6;_i-bba zLFLkr1f=#v{;K1_q3HMgFp-PP)$A)Py1ZQ3YrRl(h4Vwvm3An)$__4Qyd8?B*`eqKI~2WW zQ}mKR(aQowuLu;qDp2&AK+)?0MQ;ccy(v)imO#;Tfugqsirx_@dRL(6J%OV41&U?} z6n!92^r1k}M*>A33lx1KQ1q!#D0-}1dOHEBZIC~SJsyfC<$L;{m8;oTR`gZ5lK(07 zW<_5+KNNjqhoW!oQ1qQ0ioUl)(M&rO&9Xz$4|XW}(GEpF*%bXOQ1pvH(QJXDUj>SO z6Day!py&^QqCW+S{t_tqTcD_}5_j7vsuw6~5GX1M6qN;vDgs3<1d6HxMU4VQEd`32 z1d3`xq3DZpsmq2*(S`YM5`7tpD*4+Xtt!>*D=TVOsSFqrirPCr6wPIaq7HT_n%fRV z9qmvwj~$BUwL{T-b|{+P4n+&t6fG!F)JdRdA%UWW1&S6CDC#Uw)J33ZQGuex1d6%} z6fG`Lw1hy>k^)6b2^1|YP_&Fd(Xs+X%Lx>96DaB~P_(>2Q4gU|)TUC}IRUA4%8$El zTPg18|DGRg)U#5}zOtgemCA7&hoXMY4@E23p=d=r6s=^3qLuAXw2B>yR<%RXYIZ1E z-3~=-*c9~_C|XmXXn;V`K!KvQ1d7%cC|XCLXkCG#^#qCr2^0+$C|X~jXaj+w4F!re z5-1uXP&8DaXk&q*O$3UD2^4KAP_&s)DC%7)-IRdTdgL3_eL~S)d2C*(W?xy+)|JY% zVWDUn=ZB(g?NGFx9g4QML(vX)C>m~uq7il|8fk~39qmxGlTFbmfuhj@MLP==jS(o? zMWAR`fuh|6igp($+C!jdPl2Mb0!4cX6zwfgw2wg1IDw+^0!8}@6zwNaw7)>n0Rlw_ z3KShA6pFU2lzvD+YIo(ELR*ERQTayF!If(El@%Rcsm#53C_2LVq3B3E6dh%Uq6u~= zI@%6J$Jn9hSUVI=v_sKxb|^aDrsxELq7wy*P7)|OS)k|?fud6dicS+KI$faX41uCE z1&YoRC^}o9=p2Efa|Mdd6DT@gpy&dDq6-CzE)poZSfJ<(n<+PZOeSO z?66SudA=^XtWwRsvZAXhm94i7MOQmN6kTJ7qHFC?be$cFuD3(c4R$EH(GEqE>`-)* z9g1$YDY`|V=vINE+XRYk7bvZ%V27d??NIcR9g1GIL(wZXMXw4Jy(UofxN(Z>Qsp9mCvDp2&9 zK+)#{MPCSoq9-e*#}klR`WJKR%1?!&nVHm=m1_2t6@6Q&e7bEY`p)^G=zBX9&9p<& zEISnaV27d~?NIcS9g2RoL(wmGD4K0k^s7M8ZvsWX3l#k!Q1quj(O&{Ze+v}VwTQdz z6x9n9H3$@y1d7T6MHPXf76L_8fucr%qLuW`Wd(|s z6DaB?P}E(ZXnBF69s)%@1&VqJ6!jJgMeSRZHcmil59M3ebG0b$>37X{`}?%0W?xy+ ziY+Spj0i<5IX@JwY=@#%>`=6-9g0@7L(%GXC|bh~Mg8qiw5A=32G|r06ewCtplEG@ zqICp{))gpPPoQX!K+#}g+S4kLZPT%i_*CXNbU6eNo<8s^l<)m$W|??*;iJyU5m;+JBFg|oga#JutU*s zI~0wuL(xb(6zyn-qMhteG|CP|qwP?%vrW+$fudamigpz!+D)KncY&fk1d8?)C>kqJ zw3k59-U3DY2o#MIC>k$Nw68$XegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXwP$=4_Md{rH zq&7J}zG&M}bb9`bc36vQ_LUVK)uQs(s8BS)`Jw1&I}{ybhoWQcP&CmFMaS8p=y*F6 zonVKe6YWrRl1kP(2o#+uP;{0+(b)n;=Li&?D^PTvK+*XE zMHdJZT_{j=kwDSK0!5by6kRG%beTZW6N;{Leki)$4n;TEq3A|C6iu>2(M@(Jy4emzx7eZRRy!2kW>a*#K+zon zMRy7mO%^D+OQ7g(fuef^itZICx=*0!eu1I~1d1LMD0)bs=wX4PDFQ`P1&SUKD0)<& z=rMt!#|4U>5GZ<5C=^}YqO?l_Qfr;RM08CknwYPPo@!CezOtg{T2xNhH55JX{7^K_ z4n;56q3A_B6uo4JqL=MZ^okvdUbREfYj!Al-KOXbfuc7Birx|^nl4cEwm{K40!8l% z6ul=<^u9pR41uB#1d2WsDEdgC=wpGRPXvlS6)5^lpy+dfqAvuBz7#0>N}%X#p-}Wp zi_$F#NbRls8SU9nv|7H~|4oZ(_LUXQY*Be}_fRy;`Jw0sI~4tBhoYbCQ1r7Mihi*} z(QG>u{c4Az-|SHIyG_v_0!4oc6#XSo^tV7!T{Z5uQ&cZd)F4n)5-2JQ6jcO@S_l+X z1&SI4idqU3H3<~e1d3V-6txy8Y9mn8R-mYzKv8?4Q1o4k(oYFU?Y(^U^L;3qly6M2mv zOQ5K?Kv5roqP_w}{e(i%+||-52}o_Nd{4h)wYaB0SH7peLbaNGWksu0E8FfJidJ=g zC|b=9MXTGPXbn3Q^|wROnsz7}V27fCb|_lQ4n=F*6s;prw5~wWdICj*1d0X=6s<2% zw1Gg;h5|(!2^0+xC>knIw6Q?ZCIUsn1d28lDB4V*Xmf$0Ed+|T6e!wCplEA>qHTmi z(Mr|QkqJmG|I@qWl|#`L`MPM^YBl@HiiTG!SBwiqBb*`blWQU?rb|@Nc zhoYVBP&CF4MZ4IcXjhw}-2{qu7bx08plDBlqOk%+dkGZnEl{+NK+!mXqVWPn`wA58 zCs4G%K+ypLMF$EL9VAe6ut3ov0!4=k6dfi|bhtp#5kjG8`)cXQ1f;fVzFW3KC|Vfub`6ip~@$I!mDFY=NS41d7fTC^}D|=zM{q3j~TT6ezk#py*4n;TFq3C8i6y0KnqFe1ybekQDZns0x9d;b2^2jpQ1paA(USs2PYDz~El~7~ zP$;^tS{jys)Mn(r8+&~y+CN_xJzK42Us=%$)ynvTLeY!P4@EE8q3C5h6un}HqF3!u z^qL)tUbjQh8+Isq(+)*%*%VC|D0*9<=pBKgcLj>x6DWFLplF6b(FX!W9|{zGBvACR zK+z`xMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&c93KV@O6pEg&md;N=YCGqfLeoOg zgZaAX`)W1&%8GuhR_;3_6#eAu{c4Az-|SHIyB&)DutU+Gb}0JG zrs!{hqPoVo+fGrvKv9E0QAwbvEKpPtC~6^4R23*{6ewybP}C$)R1+v_B~a8_ps0;N zQCoqcb^=B11&ZbpDC!_kG`CPFnpG{mpMca(&0lr=Arvi|Np)qA_+T+QkkH#-#VZik{h zY>M_2C>kqJw3k59-U3DY2o#MIC>k$Nw68$XegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXw zK+$0WMTZL%9U)M3q(IS80!0&qLeYrE(rpPyttsCW8X1a~&7_WQtY%+X(Q%EHmyZcW z$2&h1onVKe6YWrRk{yapwnNb=b|^a44n?Qgq3Cow6rEvHbf!SjSpr383lyCrP;{<9 z(Rl(z=L-~FAW(FnK+#14MHdScT_R9)sX)|P;{pqiYD8k=q@`H-EC8Jk3iAA0!8-;6x}aS^ngIog91el2^2jnP&7rLXsSTb zBLYQ_3KTsiQ1rM!(GvniPYM)0B~bLVK+!V-Mb8QpJtt7~yih2*v9YvT0#e&3&GMvB zG++LVHm$LmePu;2H&(VkAr!sh{803&9g1GFL(%JYD0;&VMQ_@n=q)=GO}9hQ+jb~= z$EN6Afui>WiryC}njuj1fk4rR0!1GQ6n!jE^oc;xrvgQv2^4)UQ1pdB(U$^6UkMa_ zEl~80K+(4XMc)Y&eJ@ZnQ=n*;P$+t_u{0q8Nmo7z&P$vqPYZ$ItUcaEl|`^plBX} zqIrcv(NB$~rxTFc{`uhoUZa zC|cAGMT^;?sH+`{7Pmvu5;jFk3KT6RP_(o_(J}%>%L)`NCs5Q)ps2e*(eeUCJp_t+ z3KaDcDC#Xx)JLGGuRu{hfua=zidGaTT1lX2Wr3nq1d3J_3PlUFEVVr~DOxQ*f6;<1 zi+lQe=doJLYW9^Ct=Y2DM_4DB4G$Xq-UNc!8pQ z1&a0)DB543=m3GD0|kl>5-2)Ypy&{RqC*9W4ihLkT%hO(fubV?ijEQ}njlbgv_R1@ z0!7CPg`%BWmM%;{YH#MRI*tlO^W+B`O>9}szOtedTUH)8I~1Md{7`hV9g0q|L(!>r zC_2p!MW@@L=nOj)ooR=nv+PiGwoTDF0!8Nv6rCqfbiP2*1p-AE3KU%=P;{|C(Io;! zmkJbJCQx*_K+zQfMOO+GT_sR-wLsA|0!7yf6kR7!biF{)4FW|s3WcKMTb4dZKx%8J zSw0~Yt())mPik4szOtfQTUHv*3q`j%KNQ_=hoU>|P;{pqiYD8k=q@`H-ED`Wd+bnj zuN{i+vnje?py&aCq6YeSfFT%K+#lzqDKUZ9u+8hOrYp-fubh_ik=iGdP<<^ zX@R0=1d5&&D0)ty=y`#nX#zzr2o$|26pC(cSz0mysa=`B(0EHIdM)2ad#PnL`^t)5 zYgt+Ef>89j^Fz@ab|`w&4n=R-p=i1tir%(E(K~i1de;s`@7bZ~eVd{g0!1GP6n!XA z^pQZ(#{xy42o!xPQ1qEV(dPn1UkDU^DNyv4K+)F%Mc)V%eJfD(oj}p|0!1?gie?EE z{UA{Eqd?J5LZRrDmZd!sklKh0=haa3ZvNKn&n>IjS61{}%gQMig`(e`ABz64L(!jh zDEi9|MSt6&sIDpQxrd^9I}|n8p{QhsqOwgN_FP$*icsq||CQk#{peim*j?&-grNB^d3_LUW_ z)l^yF@=&z4^Fz@(b|_lc4n^zPp=gjDiU!-EXni{rZD5C@4ee00kxkJMfuf-TMH>qg zZ6Z)KOrU5}fuhX>iZ&N0+CrdcOM#-T1d6s6DB4D#Xj_4z?F5Rp7bx06plG;2(FlQ} zkpe|K3KZ=m6p98kmDWf=YWbOp$^%2u^?8hHs%BqV(JoDu;a7&DU7a6_cC$m#?sh2J z!wyAz+M#Hy9g6m{L($%LDB8ykMdNIW#tRhfD^RqbK+*mJMF$8J9Vk$AkU-JF0!4=i z6dfv1beKTV;Q~cR2oxPDP;`_)(FB2_qXmkN5hyxVplG5%(QyJr#|wp`otsL>Bp|h? z^VQFoQ1nc`k#s^+HT%knPHC!Kb9E>>)%l_5G&>ZXZik{X>`-*39g5DfL($oGC_2Xu zMd#X~=scUE^97175GcA(py(ojqKgHJE)giYRG{cGfuhR=imnhSx>BI%DuJS_1&Xc_ zD7sdl=sJO->jjE#5GcA)plFgn(M zplGT<(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`|v_R1_0!7aX6g?+U^t?dPG=ZWQ1d3i1 zD0)et=w*STSA;^*ZB3>2*Cj>u`O*8ghoXm@@31vhv#+e^&8AAP8$!`r&JRV??NIc# z9g5zuL(#i-D0QG^K+%^1 zMPCUNeJxP*jX=@20!7~m6n!sHG*h5xmO#-D0!2Rx6#XPn^s_+GF9Jogg+kHmO{Fao zkXoC3x9p8jv|Il4_G?o$`^t*`Y^oeEDHQ$X{803_9g6B|anC&z)!U({!45?wI~0}e zP*kx)Q42d1Rc(qI1&Ue<6g3GH)dY%K2^6&!C~6~6)K;LVoj_50fugwtiaH1s%`H&W zQJ`oZfueZ@isln2nqQ!30fC|g1&TTe6fGnaihge@U7Uc_rsq#$e}tlQ((B3#*Q(i9 zREAHvvn6HZl)~eZ8R^quG{_D` zgY8hXz8#7-utU*?b|~7&4n;%kP&CvIMH|}`Z6Z)KOrU5}fuhX>iZ&N0+CrdcOM#-T z1d6s6DB4D#Xj_4z?F5Rp7bx06plG;2(FlQ}kpe|K3KZ=mP&7)QXtY4l&O)JR?OJK+ z1f+InelW;7q3Fc)y7HJ>HT%kncCS?i-w}%TaDFJ-(+)*r?NGFr9g6n0L(x8VC>m#n zqVaYp+Sd+6``HxjFHm%VK+%B$MF$BK9V}3Eh(OVy0!4=j6df*5bc8_Bkpe|W2^38b zC^}l8=oo>bV+D#P3KShDP;|UN(Fp=YCkhmuBovBvt(C?mAhq4{xAAuiMTg~E*C*Gi z*;iI{daZKWLuZK+%-~MOO(FT`f>_jX=@00!7ye6kRV+bb~A=Q1pmE(W3%Ij|mh#E>QG@K+%%| zMNbJ7JuOi5j6l(|0!7aW6g@9cG)-m^o|`*tXrVTYm*>`?Tf z9g04(L(#`}DEh>v=u?5B&jgA-7byBdpy*41qOSysz7{C@Mxf|hfuipOioO>pnki5; zOQ7fnfubJ;ihdF(`dOgp7lESL0!60#P}EAG zsI@>*8-b#>0!8fvirNbl%_UIOL7-@EfufEAMe_(0%_~qepFq+40!0f56fG!F)JdRd zA%UWW1&S6CDC#T}ivFsVCMF=YKl4`|{|-gH((B4yT2-^JtZ4C8mFpe~MN2q86fJ3o zqNVImw6q`>I*4n@n`6!j1&>M2mvOQ5K?Kv5roqP_w}{RE0u z5GYzvplBt5qLl@TRuL##RiJ1!fuhv~iq;S)>Mu~Vra;jEfuex|MQaHZtt}La7Hd^{ zJ^`tHkgtonwkq!F_iL5LI<2bNS5`E*Rpr|$p=f>QhoTMaP_&^PiZ-%C(GWWn4Yfnj z#&#&$#12Kn>`=6+P0?loMVkv0Z6Q#!r9jbE0!3R36m26=w5>qVb^=A)3l!}jP&8bi zXoNt~NP(gq1&VeOC>kYDG+Ll&XMv(I0!6zB6zwV$iq>mY>M%7as^qUa4hlv231`Z? zwW?-cS<%>5l|GM#qP?6SiuSfc(LQ!48fS;1@pdTM*A7Md*`a8EI}{yYhoS>*iVhMe zI#{6S5P_mY1&R(6C^}rA=m>$LBL#|%5-6G=P;|6F(J=x=#|jip6ev1Qpy+skq7wv) zP829QNucOtfud6cicS>@MSHX=ZIyu3w#+xE_Y6h5=5bo9YW9^Coz<#x(Bq-#Z0Cof zbL>!bt{sZbvqRDOb||{Q4n-H*q39wz6kTkGqDyRwE)^)cOrYp;fubt}imntWx=Ntv zYJs9_1d6T|D7sFd=z4*o8w84O6eyY`P;`?((ai!yw+Iy7Do}KrK+)|2MRy1k-6<4` z&S+J-Gy$pYm>+k2W+?hJkIAj7*;iI{Z>!3bCqvPF&JRWR+o9+II}|-=hoXn=na9QHwB8`5(-6kw<>*-fYjE?S3mcJqJ`7z z%F|m_v#+e^y;hYL&xE4)oga#3*rDhHI~09rhoX<{Q1r1KiaxPJ(WiDO`pgbRpW76D zAyD+CK+#tMMPCaPeIroxtw7Ot0!7~o6wMSUnk7*5gFw-b0!2Rw6#Xnv^ou~zY=NR* z1&V$XDEeKX=nsLSKLv{Z5(-7{v??u|fYheu@9DoAiU#L<`hT~oW?xxRsdZ(8=R#4r z^}p}wSL{&K!VX1MI}|nAp{S)Dikj?DRI@`-D?1dmwkc{OP}EkSsGUGjdx4_41d2Kc z6wNJA)KQ>l9)Y5H1&ZbqD4JiOXaRwu1qF&a2^1|PP_(c>(INsxodt@z2oxc6dhtybf`elVFE>m3ltq8P;{g~ z(NO|L69kHm7AQJKpy*hEqKN`U#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@6rC`-*69f~fqL(%0nMOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8Y zP&7%P=q7=pn+1w)5h%J4gNOHX~pC+#ian`8y!*wytJhSeQJlI&+Jh2xgCnWutU+8b}0JFrs!*dqHhF>z7;6? zPN3*}fuflLMY9Boeh?`7QK0B2fuf%UihdC&nk`WDt3c6j0!6gXbGWERBlt+CIPA4 zmEly{6!-MgE$wuNtxYxi%8Hh4Q#s_lP_&%$Ls2(76m_>l(eidE>S2eXo^~keWrw2P zb|~s&hoZhVMg0VdRuCv!QJ`ogfufZKidGRQT2-KEHG!hl1&Y=XDC#dzw5CAO0D+=` z0!3>H6s;{#w2na0x&lS(2^0+yC>ktKw7yU%TDnc?@&u%IaDJ@gGNI`6OlpHR)$A)P z8rr7v$c#|5vGYUGCUz(qW{09p?NGFt9f~%$L(vv?DB98vMO)dSXlt9IZ3K$86)4(H zplEx6q8$W^h6@yp5GWccP_&~!(M|$IqXddZ3l!}vP&7uMXcvK^T?LAE6DZnUplA<) zqCEwQ#tIbeB@~J_YE$|w0jc%OkGmccigwSpuJ>+J&AzgtecMzTKMF`-)|9f}UJL(#!@C_2OrMTgp<=rB7J9d1)}gh0`e0!2p&6ipB)I$EIU7=fZ=1&SsL z6dfl}bi6>(2?9kY3KX3rP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owooV<*QV4h z0jaH>uZzZqqCfK8{&U(?Kbw)>C@H$2O=Y7`LeYiJ4@DQ*q3B{e6kTG6qD$>ibeSEB zF1JI`6?Q1P(hfye*%VzZP;`wz(X|3a*9jC|FHm%YK+%l?MUw=IZW1WES)k|^fudUl zif$7qx?P~?4uPUO1&SsM6x}6Ibhkj!Jpx7d3KZQZBp_|d<@4H<#w8%N!}3=h&ksdU zHKvlYI1%ks@b8al^u#&+o7n9 z9g5o8p{Si5irU+uXf8Vxb+9R#TcD_;K+!w`Me_<2%_mSazd+Ff0!0f76m=3PT1cR1 zVS%DW1d2Kf6m=0OT2!EDF@d740!51p6fGf8w4^}MQUXOw3x%R;+tS(zNbQ<@Q>d|R zaZmr+Olq07)$A)P>fW|8`rA;nyz@g*4?7g~v_nxZI~4V{Ls1_)6!o=3Q9nBrtzd_u z6>W-E5-3_(plB6=qE!WoRud>%U7%+M#GWo1*Onigpkv8ZJ;YLZE1* zK+%o@MLP);jS?stEl{+xK+zb1qFn@vb`>bvO`vFZfucPGiuM#J8Y@t=mq5|p0!8}> z6pa%KMH{y*y_A5|#^kSEZxV`@%GX8X+g7u$tmuHYm07bw(SgnnMF-iT=wLe(9b$)~ zL+wy>m>r4^w?okpb|^a14n;@V6ipB)I$EIU7=fZ=1&SsL6dfl}bi6>(2?9kY3KX3r zP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owm{K20!8Nv6rCp&iuP+;n)ipK==}VB zwEaWTU6nM>Z(Gg2vZ9OIR#yBe6kX!{P;{vsiY~K5(dBk1y21`cSK6WIDmxTiZHJ<3 z>`-*AP0@7%Mb`@y-5^kOqd?IlfufrPif$Gtx<#PqR)M111d47KD7r(S=uUy6$pS@p z2^8HeP;`$#(Y*pi_X!l;FHrP=K+%Ijq3FW4rR@@sTAzGfbWtceJby-esBJa-%8DLo zTRH5PQ1qztL(yY)D0o}eQSrJ@9a?Yy&Z~X+7!(aDEdL5=tqH~p9G427AX2fplG&0(XRqU zzX=rmE>QG`K+&H9MSlqt{Vh;b*Dmh1Q&cZd)F4n)5-2JQ6jcO@S_l+Xg+kFMZA)Jy zAhk{NC$UdM(fE8_)Yz_?ePuTMRVtS`un%5W?xy+!R;#VG=!oaMP7o+MQK0A~fufTIicS$II#ruqk>`py(xmqL&4VUJ)pI zRiNlKfuh$1irx??dQ+h2ErFux0!42N6ul!*^sYeBdjdu83lz-|DEdI4=tF^`j|7T7 z7AX2eC=@-~u5@w&Qd>S>7d;k=ZpgQ;KW$gdzOte(+f{CE8H&Dgekl6d4n^PCq3ByX z6n$rhqVMfcG}8`6v+PjxgB^-~v?=;Ypy+3TqF)4xW(ySkDp2&BK+*34MSlns{V7oN zmq5|q0!4N0<8C`e^#Vl=0!1Z(qOw3yMWCpKKv7kos8OJ(r9e@WP$>GmUFnqsq&7Cq z@)x0Kc)q7!YhTU2vZA)_D?ipkQ9I{{qV{$un#&GF9qdpvw;hT)+M#G3I~2`phobrH zP&B_y(EyR<%RXYIZ1E-KJ;_fujBbMQaKa z4G<_AC{VPPK+)O)Me7I@tt(Kpo#~3lxnJDB4A!Xjg%v-2{qu z7bx08plDBlqOk%+dkGZnEl{+NK+!mXqVWPn`wA58Cs4G%K+ypLMF$FnqAl8&u1-K| zPv`5REkn`F{3XbP+E=r$tmv@zl_%y3MTa{-6dhrQq9g54bd(*6CfK3qXgd@gV~3(+ z?NBt)4n@b=6df;6bb>(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaK+%~3MP~^Voh?vw zjzH150!8Nu6rC?nbb&z8g#twv2^3u{P;`k8k{!wqm~eIW!cVoyVo^tJzmp zbY=TWtB#@QD(8oytL;#9jU9@vwL{T$b||{u4n;ToAA9#19#!41@qSI#tV}WqFcW$Y zML;1Wp@Sm5hTcR)LkOYw1Vlvz5k*8qMMcHld+*q>E23g=*t?=4Vn6@itoxfppJ(s= zyx7+{=f&o_aOM7HW-^)iFqssAEk!r5rRYYs6y3x|(ai)D-9kXotppU^MnKW+1Qgvt zK+&B96x~HY(cJ_T-9tdpy#y59M?lg21Qb0$K+#qLiXJ4O=ph1%9wwmZ5dw-HC7|dr z0*W3dgo-Xp`h^ZiRzLgc{mZ53Q+q7hmW-J%Q}lE)7*}74p5gpb^ekJ7o?}bV^K2=4 zfh|Sb*;4c(TZ(qDrRXKL6urzw(JKTL?IfV+RRW4$BcSMY0*c-spy*8kiryli=xqXu z-XWmqT>^^UBcSMg0*ZDKQ1k%-MIRDS^br9?9}`gY2?0f)5>WIR0Y#q^LPbv|{i7U^ ztRL+&{imepSNFQ;7s;6UGDY7cgUt=4=v&S&Mc=WdXg6DmzGq9(4{Ry=ku61g*i!Tp zTZ;CwrRZliiuMsu^a}w+zY`O$+obWUKH4aa-b56{BnWFAFLF;Bx)PwU& zQBSrM^laQ z(NF@4h7nLSoPeSt0*XcuP&AT&qEQ4CjV7RI3;{)B2`CyzK+$*tiY5?HG?9R!Ndy!f zLI@Rg&GCmhAX)7VPB$s4Z;wTjb7JPp6ivwq=D2^6IQ4zBBRIbl9m$rWVzv}bWlK>B zTZ*Q!rKprGMbp_*RK}K~8Eh2IB%o*(0Y$S3D4Ih+(Od$G<`GadpMatT1QabKplA^R zMT-e2T0%fkIRQl#1QabLplBHZMMn`(w48vVqX{TFhJd1D2`E}Y2o)WcaMJKVPXboG6PG(EdDQqcP%a)>3*;2HQ zEk&oXQM8_bqSFZ|+CV_j83YtxLO{`_1QcCH2o;@>FWPR#pbfpx1XXEmmnECQ* zd1=vBnYnEuUgAdgEn6?K-M}SwyDw8_By!wmbJ>Y5?x}eqF{y^<)k$1X%kvr}b|pQp zNuo_1&&y5BtLJ&G6Sp_;ympCwjXbYI;^3y9SCBZVx#x9BJln$adL$C9J@25zq&A+{ zH?gIi=M7AJc!1{(O|;ANyb*~7`JOi>ac80DO-TIO+4CkR`gZfYDT$MNc;3{+^SwN8 zdLpN{=gmq??&Ep$5*PRLyhVwR2Y6mZ;()=Pw>+_EsOPOn+&$d$RwjNQ;dv(|`j7U! zwTZQ3J#T$t`*_dWn5Z+!^EM?8o9ua;6PF(5d0P^nPVu};6CH{@@5;oI63@Ffac`;T z-I(~Z%=2zd44mb8cP7@&@w|HzJLY+w`(F7%&wC^>WwGaNOI%*=c~2)kU+Q_!Cpx-+ z5@ScA;uz1{nYe$2=e?2ePVl^U5`$NH-mb*@)t>ip;^j4-_j#hhTF?7BapXGB+nu;_ zz31&oe7V8%_9Y6=^t|7b%g%PUerLg?mmblcV6u7 zgh;Z{W$s>xB&S~C?uJP6>Z{!S5J}pl;bhziKuxlC*!8YG@>B|E|!8Nb=i9+xpMYlJ@t@&Wj}NF9=-}N!s7=SP@CuU(vTb zlC-~LZABz$e@WKLNYeh6qmv@Z$9B1UD3Y|lXJmaOX@60~#z@lsPybDkr2Vhjn9fUL!sAno;hpM0#o5Z|XpF705AC*yAP(U@V^pl>)DPItquc%#UeNP*`y-sB!X?02xAANL~3 z$bL0zXZbZ7*PK{C8A;UlytLL{R@T8Td7fX-^K16XIxwqe*09>{M$>ETChF>0NpF)n z#A-*fvcl6vT+OKA`5BxoE2~CUc2*Df&SuvC+o|I2RMjp#OEU=HR<fqe<<1mTU5`W!ckS#gCsQxDyD&%Zklsk`NMu-TyZAaS+>KPXOSLQ1r{O^j zJ+EHJNS}sW%eD=Zk(~6t4bJP|(9YwYEApCQwbSa~)8E~84XR&66Ze)Io_b=$-NuFP z^o`b?81d2?oY}vDyAwKk_68QzOkIMzHYTFluc_|kh&RR#Q%#;X!47NP@2FSt;0c%5 zOGYy4{TLZ@i91#5R}=SN``}=mUv{eMzpC$v?#=q%ba$4t$Zs`kcoFx@oz{$X?3ll# zB!5QvqWtnDrTI&W%S+3O7cE&>QC3<}Ha)*|$d*&}% zGJF2)irLG`y!=@U=a=P|%qv@--*Mi;(vo@k<+Dnbl;tleTToVBQl4Mdskppi>GatP z^D7oEoL4%lWcGsc{F$Yt#U)GT=NA?fcP{Q!(5bMvu)t!Ti+KwcE-1?@E15PsudtwF z=RA9LNB8Q#y()k9g3@_QrWbWXl3yLSW_hsgoc}vTS$Mx$rvg`lG-L$Nv zqRehB&kOJ98A}(G78G>tSZWlCrzVW#t`bnJ{;EO`pA>!VUKjG=9LK zVs|x52P~XFf8hex96rFzwu=sv=N{ODluo~MBnWE%SHFTtx<4}#`k=+ZLG5Plwg2OV<)qik51KX( zY9ExkEIaRi`(k+0xmzT?PLN}7;XiuUTNM1e6aSl=+`aw$Johf;{p~&bceNmBVK-mu zrf&7$+=-R%;P9$<@V|TU|K7oBe-5hf{@*Jr>7;7&Gu>HPUehnJ+&cHs^8Q|MlK1>6lDRQ z>W1U?s=7_wEuqu9YaZU3?!v+ss$G-rTuXNwre5i8U!AXO<%PMc#oO+r(|4}AIs+=t zQ8<7%<*vWZVGyc)uJph48N$G_X-j8%?$fFTGs}w07EGUAvY>e0!UZ$KchKE4?#;W; zL#o|1x@ujjuB~Gbp1kti!&^bsd)Kq_Jt=gQy`n*f7WW%CE_FV459^(DlJ(NSzn#;w ztCXAi&%bCZthyro1qycqbt4087xt*Un8GT8Sb<7ml}Yy=*qbf3&ztm_R`HVX!Vyzx!#zr* z-fCeLwL)htYz4fsN?+k%?x!kr+;#3f3eU$2b|0l4p{nj@_n@Vlq|jX#UM#G-d8*yp z-F0^Ekr0wyV2`TX&fT)%+vvm_tCCPyMWL{o1$TFaXQ{f^xl;=J>wUMo#NJZR%IoWH za9!Q1$F9!0q^?!hC$x}yudD9vRWiZ`gM=N@zP zs?L=+p}QeCxg@yD;6CLpt-Kq1xJz1CDYxoA;p2imjOgOrdAMLlGQ0`hn@zpoZV6sj zd6nGTa?KP@aG%-h^qkS%AE{z@^8e=7g7l@Ns;@BEEjXz1I=TB**R$&VLXNxL^}0$S z?v4$wca=Ezu;fmadZ16e%8Ajr+{YHZRC)6_&Efgok z?Op0_y0YbY^E-ETp<>q3`P1BS#=M0k6?yJUeZAfNGu?ta<%~tky5^NH%9~!;&6ScR zrL%gwul+6SkvG5NeD~GE_S4H3wV$ylH*aQc-sn!bdG5=t5tPpgxo7Xl%{kS7ytd^ zJkL?9o}$9Wo>Ywwd46{)ld7DXbk$S8%6l+;{^$)EFrZg%JNtvv zZ^``JLG!1TO`qu<-Yl_qGomt&%R5*FZ*sl zznTqJr=Jw8iJt7AlC~k@_3POV+U)5jj+gF#X{qps_3zBbNT(0)ZcVAde zR@?Sn4)?8XuW#ka!q-<++xB|boMgeJ}N$J-yC0-_8q@@40WQSNr9AfB!Cx z`)+@=*V_4O{bT?A+WMaRCQ!9szL!&N+4<{w?psKyTgC2|9QXdUt9FWnd-=eB?0@-! zed`LZ_4I#za_Rm^{PW3w<;R+-?lR+b-S>mt?Uv?#O2BTFH21EWn>6=E?Y*$0J4x#3 zzAfgZxo-}(u%mmI?K;})&59k}4+W%-?nePq$NoBw(Q%@Vr8>^haj}l>oARmiouuPN z9k12#Zu@?fdpnQm_=dY%ZGWueukIbNo$kJIYR4w-ZnR@N9S?Tzo9*E`PIY&q?Rh$0 z<=!XTx9j+oy8&$P)3MN@vVE|QN4eX~_DMQE=)S*a`&k|R#^FxrIL!Urg}r`~j%PFv z_ZA&rbvLZN{zDxbw+?qZ9ZTATdx4JExI4g3f2WS$91!kbb?oeZdc$7dSI48>9cBAu z9Um?X_wzaiUBaECW0AW&$ENO%x6>b>V`-moFVgY4e&N1b z$L|J&`*$6?4i0yJ9giIv?zK8TIy~Ilb&QP+cO4x^jt=)>I-Wf?+?VS3=J;@bs$=s> z;qIVg+2n99(eZ}E!hNrf-%knmpE`Cg4);JEk1GlHIvpQ((Czlvp=0KZaM#mu^sI1C z(ea!);l5nQx95fXa~)eO40lHzXD$wRg^o9shx>jVe_R@FZ&`TkxjZ}$*71a6!o6O{ zCsu^}WgW9l2zLV=$F2(Zkvg8YI^0+4`0ko;f2m`uwc#$%arU}!FVpds_2J&C<4+sH zopwfeJn+o$I8?_~XNP-(j!&Hv?wvZ;*c|RgI*z{}+*5Tte@nQp*71G!!#Z~Ve68bt zmxa5Nj&rXF_i`O?yDHod>G<b`I^OY6xF6B+mq)^#{%CmY^LTh1q2rn- z!hM#G&pj3HH*`!s8}4R09`by+r|Wpp_HbXX<3~Hfy<5lqUkP_N9T&bD?iD)T^?JA; z)A6@A!=3R~c@x ze-C#{9S{FA+_QAN%soS}%fDI2&)g4A+1{gLp8H0-?Or;TyC0>py;8^f+|N|mep1K3 z+z(gT&UXKIvmFPypR%&!I2})OKW=4vvyLyhpS!aCo{sh14`A7Dt>Y2yC$VhL(eVoR zBU!d@)$t4Wvst$H>X`3-NXzy?Ixfu(_lY__;C^h&UjMX?E!>Z0**;ju;X01BW8isH zwddL~+w&IcSfRd3#|=7OsN=Od-lgMXI=-mmJ34-$<6a$o_p?=YeG+zbZ$DSNwT>C~ zyv22QRZ_>=I@Z^*nT{=W?4V4JC}P}^S58_=1cu*;r?r<^TYWs zr?c1DueR>D-KYQ4>Foad=i9CR(^q!?*)O}l-BVMqulsGk_6&7D72ecc14uWBlT!Aud$Eyy!6ZlVmQ~<(VZe?-2Jg=W#E3-*u+b!FHTqHcJ;SA!TqpeU)SvITIcP$ryYNLyAQd`%XN)kTwa9>)h}<8yF6|e z_td@e@=kLva~`{l_uS>#>G;L#PI007yn$>qi0X|RYChTHGaaN5re}YY78$n;yzpD za;;o>cxu_FJnmOJ_rBEgdfavH@NW`=W(A-EXh`Z*O_I zc3J*lFL&EMukc@Aj{Fz>zdC(YkGAOdLxDekxVzlQWhGaXo;`a?@c54_bANT$?c4D) zhixpe>$=%pv%Wu^IlgqbUC-3}v1i}J(R-qG`tHr>S5kDu&{s=#me_kaAoYH^+J8#X z`1+bcIlDa?nUkO_U+yox;NWzo4T*U_h9?@R;f#|Yj3wkZt8X1Hccwu!tfs+ z^&6&MXO|kyy|q={;cH7ybGNPCvWEwD+pe76v?$?j-3h7p-!4DWvQbgi(BV$PfI0RS z?5)R!576zMXi>YU?XLT?r}e+#<=^xCC97KAlUzQ|OVsPTV~e+P$5!`yhx@(9{a)dI zuXVp~^j5a>->Z4RaBUSn73l?d*J$Qm?aXXKQ@wb*X!1Z(84R|CH5tbkXo? zvPSReJGH1%R`@5e@6@41{d5|;)M$%AMZK$CSM$=d^19ls)vfZnj^5)>?N!uCQp3yh zr*<#Ot9E&b7F~+=uXcHM3Hw!Ep55LpD=#mjMQ%|uoz^bRZpB8a)7mw&TeyDZ`)jLq z>bB5*(JE2xa%vT2SGyd$r7|in$8OW0@^WlN+~w5U}}jHv&bGZ9^3bI;+2vf59+q!HnKl|x}Ch-soq!a z`BnJwG#a_yeQ?j-?w$yAss2&Web`8gq}O*jEt0XHdzzk>7F-guL#&mHem(aACT(N` z_q8eaqj<+hq{YQk4D=B_V1U)>@S~gtG`g7xtoPvw4G)%H#>RJ z{WY7q+1dSrXPQmi?BYe+Yc_VXs~7E{*~raq?(a<3Z0KfpFWOPFftx+NXuf8BH+y=~ z0?m4E7P_lds9o2#yI!5N>)3Wzth07)+wPim(ay2$u3A^^q-}TIx@jkDyDQgSyOwQt z?Rsd}wC%25Pwg7E-Sz9Go$Yofcl{33&a&;U-$B}O+wS`H*3Pu;uHV7h8MfW^>!TgB z?XF*6?R4Aj`t{QeY`g2%Ups2sUB3a^zHN8?25P6d-Pv8gLD~`9?)nYZb__D2(boPm z?*7j_+x+a8`d{KRe{#?EqeEiXxD%L=qTm@vIVEI-&MF}zH6>(}ri6^vl#nr+5;9g( zLdI!I$aqZ&nV=~l6EzVsNgE-DXd`5@HbM^7M#y2>2svCEAyc#wa)dTQj?_j-u{J`c zY9pjX8zIxQ5mKs+km=e8Dbq&C3~hwW)JDiGZG_C$M#vm(gv`|rg$(n*a`%7cWK%Ib z6cTlhP|$MSbx;8>KXd~ndZG>#p4uvf6Yq$?4ncLh4oan+($On!_^vsya zF(Ky!HQXyxLeAA$CFDF!3E8YEA?IsK$OW1ba-pV#Y|)gEi!>$VVoeFTL=z#GY9r(_ zZG>E|jgTv}5ptzALax$A$ko~ixkeiy*J>l=I&FkpuZ@r!v=MTnHbQRFM## z13IgOY}J&I2Q?++Ax#N+SW`kC(Ug!!H6`RRO$m8iQ$n_BBIF5eggmK@kf*c}^0YQW zp3z3gv)TxGP8%W5Ya`?ZZG>#sM#ziW2-%^Hke9R(^0GEUUeQL#PHlv|s*RA>v=Q>U zHbUOeM#!7m2zg686mqXW*4_V^*EtT+`$8du>^aHXF_U9L-VesQFSn(H?9y2!9Q+6dXBjgX(T5wcesAwO#)WS=%de$htAui6OtO&cMi z-OO$Gv^>Uc>b84Yp22S7wtHHh$!_ends-f6H*(uOEze>%blW{G&t^Ap+dVC>!LIMN zds<$TUC(X%yrveRt_61u6NEYz+*M2xYFlvEF^7<2!ClGPgro&`E$a{x7TndWOQ>bR zUC(-inikv@txu?7!Clh^glre=Gn|HmEDP?MHX_6=xNF*&kZHkP(s0DXTTM&E;?wYnFq`6?9>$D<7EVyghn&5!ch(^;Q{{0R} z{7!p%;zvS77rW1^qx(f-#>*7#9|_)eUt~@xI)L*_QG2!&bznx z)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gPgiul2Na|EOs%a)>XY$+PgmZAx4DVoTZqDgEiI)p7nli4Ublz^hc z2q-$7fTAe`6dgf8(UAlc6%$Z2m4KoW0*a;)P*h4l(R2ce$_OZ$K|s+=0*Yo4P&Au> zqB#T<%_X2{9sx!32`E}X2o;Tp_=6pg_?>P>M@rEL_E@wq5=;Gzr&ClO31+%)45l87 zDmcFsEoDp5GPV>Q#g?MwY$-aLEk(z$rRZ3;6s=%O(Q#}P9Zx{f2?P|aB%o*&0YxVg zP_&wWqLTRv%0Yz66P;?CeMb{EgbR7Xj z*Aq~50|7-h5>Rv#0Yx_xP;?6cMYj@AbQ=Lhw-Zow2LVNQ5>Rv(0Y!HcP;?IgMfVay zMdwERmmQG!HwNcCDax^NUnFL}Owogp;KxQ%^bqHlqKDa1^axvu9%W0>V{9pUoGnG$ z*i!TaTZ*1!OVLwo6g^Eq(K7@TJxf5*a|9GUPe9QN1Qcy2py)*cigplC^b!F@FB4Go z3IRns2`GA%fTGt3D0-cMqBjUAdXs>nw+JYDn}DKs2q=1&5Gr~g;x}+VH5K>mv1qFl zZL*JO??qzf%M^VW33@h_qK`Pg6n)H=qEFaT^eJ14K4VMK=WHqZf-OZ~vZd%NwiJEM zM$tC}6n#rT(RTzC?Ixh;djg7nAfV_+0*dw!Q1lZ4MSBS-`k8>DeFPN!LO{{41Qh*7 zK+*366#YR!(Vqkq{Y5~L`+q|&boYETf}#ikMQMak(XNPpqyrK^&V6Sy`hgUkVvj|B zTFiWzqF7pRLUSp~;QUgQ$(EuxTZ*#SQk2b>q8e-|s>zn3T5Kswu%#%;Mo|s{MYRbi zszX3gT>^^g5l~d0fT9Kj6g4EEs1X50jR`1fLO@Yd0*aauP}H1&qFe%sS`bjwl7OOC z1QfLU#6%-TJS^*Dazyg zQq++xMfq$gDqu@dAzO+%v8AXpTZ+1{rKl@gin_5;)SZB$9t0HiB%r7l0YwKAP;?Lh zMZF0qI+%c>J_Ho?C7`Gu0Y&`@C>lUO(Le%<1`$v+n1G@o1QZP=plBEYMZ*awDk7k0 z1R+#(K$`!h0}^lVe(o~bUW$DCOn+or%zT-mv1vh8YbhGX`K4$)TZ$&IrD!5siYBq8 z=n%FPO=e5cp=>ESj4efnvr#mKfTAM^C_0jWqGAGyrV>z8LO{_p0*XorD4I?{Q5gY6 zGYBY}NkGvo0*Yo6P&9{tqPYYV%_E>_J^@7w2q;=eK+z%siWU<>MWfUF0tY0Xw8x?` zQj}pI(Uzpe%$F%zmKKa{BSlAXekoecmZGECQgjSkijHMV(F(Q{9mkfU!yQAfV_B z0*W>gP;@2%MQ0IEbT$D+n+Pa6hk&AU38A8jG=G@`6939Rh%J?(t@c=SURun2nW78R zg7ex*(H71xMHjK9=wh}MUBZ^4OW9I%8C!}jXG_r)Y$>{uEk#$cQFJu{Mb{8ebS(iz z*AY;3Jpn~G5Kwd@0Yx_vP;@f^MYj-8bSnWxw-HcuI{`&^5Kwd{0Y!HaP;@r|MfVU; zbT0u#_YqKZKLJG#5JE-gr}jV_NK|s-)1QfkRK+)R-6um=0(Ypi`y+=UN`ves2 zB7}+_O7qj&J4GApGyR99DD@9jevlS3U#94jw4ha<6n)D1rRX!Z6n)N?qA%D|^d(!0 zzG6$!*K8^JhAlQl+fTH>Y6g42As38GGjR+`eOh8c+0*aavP}GcoqUHn?94dWN$vfZ`7%ZM zesD{n6cuoODJo=3Q75((b!JOZ7q%32WlK>vwiI<|OHmKD6!m1Is22f62NF4E{Rt=sAqDgEiI)p7n zli5;qC|imSV@uKDY$=+;mZBrrQgkF6Ma2XZO(meHgn*)H1QeALP&A!@qA~)CW)M&` zlYpXG1Qg9CplA*OMRN%#nnysRw10Y&QwC_0URqV)t6olZc}1_FxCAfRX? z0YzsLP;?dnMQ0OGw26SCa|kFpmw=-42q@Z2K+*YxP|;DoKh*(=?=?8frRXywb%7r< zU#93{KUmd6iZ0>&QgkU>iY{YI(dBF@x`Hi5SF)w(Dz+3|&6c8T*iv*Y8%5UDGXX`n5Kwe00Y$eFP;@&1MRyQTbSD8tcM(u@HvvWW5Kwe40Y&!_ zP;@^5MGp{Aw3UFO2MH*8h!85;;`>)SAn~_N(M3}9k&TD_nE5hAkNd$>?tj`({ba~C z&M!qzu%+lpwiG?ZmZGQGQuGX4ik@Xl(Q|AmdY&ysFR)Rxoq(bj2`Jh@K+#JC6unG9 z(JKTL?IfV+RRW4$BcSMY0*c-spy*8kiryli=xqXu-XWmqT>^^UBcSMg0*ZDKQ1k%- zMIRDS^bsLc^r-KD?SRC)+0QyYCPlB>W6{Tc%zT-m&;6iAZz=kM^Gnf}Y$^JREk$3m zrRW>B6n)Em`s5V=Q>aeA# zE?bJ~v8AX!8$}HWC~8PRQ6mD18WT{|gn*)^1QazRpr|_dP2q8JwiNYbOHnVj6dlNxqJ!8d>P=&2BZP_yqW(h;NPM-M(LyPD#~zEuM`Py86de)`-X9=ElR3W> z9mx2q-#= z5GtA&^`irwqTlSRj+3NlcIp$hXv}<>q7~6#zrj*;9Osv!zSMHdoKw1p5VIwtB5cR=Eg*jF8o zm7;U)$3!lQ#>|%~x-1&Z9V$habABnhf-OZ?vZd%MwiI2>mZEFeQgkg_imqcz(e-R8 zx`BzmB?5|GCZOmQ z0*ZDLQ1mJRMXwQ1^g01WZxB%QCILln5m59t0Y&c+Q1mVVMeh+%^gaPay9g-yfPkV8 z2`KuAfTE8HDEfqeqE88-qHR(CH3uX<*gl9oAw@&%srF~lnE5hAUqyqTM@Z4voL`E* zVN21sY$^JVEk(Q8QuIArihf{A(T{8?+QXKjpV%ncOF+@j1QhKfpy(F@ihd=a=r;n2 zekY*l4+4t*B%tUo0*bsqpSGhYLO@X(0YyFmMNtBZ0s@NC2`GvYP?SMHQ6>RJaRQ36 z2%(}cqJEQ+PEjBGiyXd`qD$=~T6PdKU#2J#1ieQ~QIhjZQ4U**YO|%N4qJ-qvZbgV zTZ-zlrKka0iW;(|s1X}QjR`1fLO@Yd0*aauP}H1&qFe%sS`bjwl7OOC1QfLm<9mJNR-fSs4m@P$p z*eL2tKv6#eiuw~!G=PAjfdmu{BA{q60YyUyC>lyY(J%svh7(X!L_pC90*XcwP&A5w zqR|8tjUk|DECEI12q+p)K+yyOiY5|5MV$lxS_dS)(;kbuNYPk(ESeO=%$F%TEC`+% zFGYuQekq#5mZBrrQgkF+ii+7%G?gtyC2T30#+IT|wiHcgqo|C4q8S7f%_N{`76C=G z2`HLFK+#+RislheG@pQ?1q2i=B%o*!0Y!@mC|W{5Q8@uc6$BJ5C7@^-0Yyg3t2n{dEk!r7 zrRXNM6y3~5(JcfN-AX{wZ3GnEPC(He1Qgv#K+#f^c-7?o@YzZ3v4Oc&X%GV*;2HFEk!S}rRZh06urVm(M|%2 zUL~ODH3EuWC!pvJ0*c-wpy(|Eiryxm=p6!z-X);uJpzi}C!lB-0Yx7WQ1l@IMIRAR z^f3WNpAb;=DFH>F5m59w0YzUBLPbvn{v!@Zyrw-CJuOA{S9M0e3}WWX6nz^6A54*= z?>N5{?Pg2S_iQQpfh|QpvZZJbTZ(>SOVM7o6#dMWqJ3->{X#&|uLKnRMnKW;1Qh*2 zK+&HB6#Yd&k(aJd+ffuDpeT)iBA$Q0Y&Kq6vYTA${?U9lYpW)0YzB^6lD`o zRD*z`nuJi%*MXmYgi~bSca44{Md#R4?ON$E^JR)^rw46|rKk?)m!i6CDXPboqWWwp zYQUDFhHNQn#FnDQY$exdaroAfTuv0Y$9{C~8eW(S8IJwIQIW zEdfRC2q@a0fT9BkC~8kYQ3nEw@(3vENI+3O0YwD_6crLs)QNzi&V*1=GTk5HfW&9o zv+JDn@H72w_Gy2Y^qBcFMLp7k`6W`+lk-baFSZmN$d;mm*izJ+Eky^jrKk^Eiu$sp zs2^L3`m<3qfPkWb1QZP-plC1wMMDTE8cIOXFanB(6Hrt{K+y;SibfJpG>U+t(F7EY zA)sh10Y&2oC>l>d(F6jDCK6CIiGZR*2q>CN2o-fp_s?=b;>XzsvF=iIuYEh@(Da!3 zGDSzE2X~Z8(UF{Aii+7%G?gtyC2T30#+IT|wiHcgOHmnHie|8-XeJv)vj`}fO+e8c z0*dAmP&AK#qWJ_AEg+z1Apu2;2q;=iK+zHcipmKnsvw|fDFH>x2q-#=fTHCD6dg@K z(J=%R9ZNvb3Id9bBZP_$Pxs$&K;jea;b)2zb+wOZ$EU~4mnk|iJ@}cMwo?Cjmuw5m0nD0Y&!^P;@T=MfVXQt86KH zjg6w$2`GAlfTA}ED0+*4qPGbsdWV3bcL^wZkAR~02`Jh{K+y*T6n#iQ(MJRneM~^n zCj=CINine0*cZIDDnv?iV{#15Kxp(Kv9fExqI$6)xloGgbABmmz?Pzh zY$g-WuvGC0YxndC~8GOQELK<_9LLE4FN@M2`Fku zK+*mL6dgc7QF{W4IuKBlM?g_W0*dkpC@LVJsE~l7P6QNnCZMPb0YzO2DC$NC71fFP z-5ikk`}RK%)s2Op>ECV-OxDeA+PqP}b?>c^I% z{%k24z?PzcY$+PVM$upbiiQwSG?aj%VFVNnC!nZ^fT9ru6pbXHXcPfOqX{S)LqO43 z0*b~FP&A%^q6q{PO(dXb5&=br5KuIkfTBYQC_0RQqQeQHqMk8-g#!||fAKfkONuVE z$D%2*nE5hAQ)9tJV6s;tLijIu=k2xUmcJ^smu@rq|KZLz17BgR_XiY5mXsHyP z%=xA06t)ztWlPbiY$;mDmZHRv&0YzsMP_&7F zqH_o+I+uW=^9U%~OhD231QcCBK+%N+6m21(=pq7&E+(Mp5(0`YC7|ds0*Wptpy&z$ zimoJ}=qf^}Xm!lbSmqR6=4SLHDVk{?(XNig%$F&;J{Ii1T#9bs{8DryTZ(RCOVQ12 zDY}I%MYpo0=r*<#-OiSxJJ?cmCmTg~5m0nD0Y&!^P;@T=MfVXY$*|#3Mu-D^GnfQwiNx$mZE)ZDf)#iMZdD8=r^_${mz!6KiE?ACmTh7 z5m4l1=+kx-MF=QLBcRA9peRZ}Q9wXZIsrv70*W#SD9R+DC{93876C=s1QgXEpr|GR zMYRYhN)S+#B%mmVfTG$26xAVwihhXsZ#f|G1MCOWe&n&pNY%}VnJ-h+FeCWwcqwYc z`K72aTZ)>nrKl-eikh*ds5x7Ta@kVUf-OZY*;3SsjiS~B6zxYqQ5yn^+7eLIj)0>5 z2`D;%fTH#U6m=k=D35@mjsz6t6Hrt@Kv5w9MV$yJ>P$dU7Xpg95>V8QfTHdM6!jpW zs3##*R6oPdJ;5nD#C}M&K}PtQ{+ssfx>rWbe3_zyGlG7rq^J+)m!iIGDeA|TqW)|t z8o-vKfov%n#FnDLY$+PTmZG6-6b&PwXgC2yMFbR$AfRX@0Y#$-C>l*b(HH`X#u898 zj)0=^1QbmmplBiiMUx09I)s3t$pjP~NZFXA`7%Xo zGlCb^NYSaBUy9bTrRX%a6s>1V(dld{+Q62gGuTqJku61MvZd%OHj2(BplA~TMduJu zbS?o!=Mhk}nSi462`IXNfT9ZtDB40m(M1FlT}(jHB?J^*N{%Ek*aRQFJc>MfVXdXIpj_X#N4ML^L91QdNpK+#786n#uU(I*5HeM&&l zX9N^|PC(HY1QdNqK+#tO6n#xV(KiGXeM>;mcLWseCZOnh0*Zbhgo<`#_{TdS?!m{w zc}a?Hu`gu*m=QByrs(I4;F9%Hw2$*k(JyQ%`jst3zp2Lg)n2q@}EKv6ycMFj*D6%tU?iGZTc1Qc~4pr|VWMcoJ}>P|pW4+4sM5>V8O zfT9BlC_0D`Dr%JJ$Iozzy4w@##+l(~`g2pCuw}-~mnrI(8MHrBiu!YYDH_0*qJeBF z8pM{O!E7lS!j__;Y$+PXmZIToDJo*4XaoU8BMB%PML^ML0*b~EP&Af+qHzQijVGXJ z0s%!62`HLGK+z!t6ip_e=uiTR4kMuGZ~}^^5Kwdk0Yyg=P*hAn(NqG8N(iB%KAHX) z2P8h(9)9{t(Kh!1E;=nUX1+|(jLcy1*-|u<^GnezwiL}~OVJ#*6wPHz(LA;k&1Xx| z0=5(_WJ}Q^Hi{M#P_%@AqH+R?DhMcANz z(Rl))@W**l zbQ|ZFqTAV0bO&3C?qo~RU2G}3n=M86u%+l;wiMmRmZJOFD0+Z^qOAlJJxD;&Lj)8( zOhC~i1Qb0=K+$6a6g^Hr(KZ5#o*5&=y?K)ULc@o zI{`&65>T{*5GuMk({H)iDH>wm#=k|1UbN5AUdoJ_FH`htW-#CaDSD0bOVR6WDSCq~ zMQ^gD=q{(69S4pC7|dt z0*XE-py&$%ioPVE=qmz>z9yjP8v=^HC7|d#0*ZDMQ1m?kML!Tw^dkX9dk84{i4ZD! zCDWhffW$`{oSjm%+`cutH#26wOwq5I!KquM=r_(UMZdG9=nu9O{mGW1zt~db#r2uH z6h+ull*X1KpDjgEHi`lQiqZ)viV;whK|oO^0Yz~Fin0hO$|j(w1_4Di2`H*XKv9B# zq9g%DIRq5dCZMPe0Y!BQD5^(5QGEi68W2#_kbt5_giz7GO#fyFB>s&(FZxA_4z$rY z9y4F2sChhi@nR{;<@{3Af-OZY*;3SsEk&)_QnVjiirTQHs4ZKH+Oef*e>RE^AfTu{ z0Yx1MD9R(Cs3QSI`2-Xd5KvS|Kv5?GiaHZe)P;bet^^cyBcP}|0YyCsDC$W-Q7;0D z4kV!HAOebd6Hs(80Y!ZXp`xa7e~$waKiwXFn#IG<^yk~?8;_YUQ#3Fh)V)lK2628V z8qAiWA#5oc%9f&GY$+PfmZBoI6pdg@(MYxwjbfu{Gyz3p2q+p$K+!k?ipCRAG=YGk zi3Ai)BB1CH0*WRRP;@8(MTZekbT|P;QwS(Jf`FnU2`DNiplB)qMI{6jO(USFlz^h? zgiulcxZleGiQC^)6dfQ%*V!nG$IO>0njH@gze0-UaDFM8%a)>fY$=-0mZAl0DO$*u zqD5>eTFjQBC2T1wXQQZsfTE=Y6fGm5=qLh;mJ?8PGyz4&5Kwe10YxhaC_0XSqT>lD zI)Q+ql>`*6BB1C*0*Y1>P;?RjMQaEsI+=i?QwS(pOF+@7giz7UxWCc?iBGqOpIK70 z&7LH!i^t5DDcTSZF1t#K&fxq~w2>`EXR@W}EVdM#&6c7~Y$-a2Ek)Rv%0Yz66P;?Ce zMb{EgbR7Xj*Aq~50|7-h5>Rv#0Yx_xLPhK2{*w+!{73sj z`0N@fx|8!u(OqmQx|=OU_pqhtUbYn7$Cje|*;4cXTZ*=_rRYI6iXI}M=wSki9wDIU zQ38q{BcSMU0*bZ~Q1k==MNbk?^b`R_PZLn|3;{*Y5>WIU0Y%RfQ1k);McWA|dXa#l z9Rw7;L_pEY1QfkO2o>EH_p`5ciheaXw@cA|sZZGAG4o}L-iQZz*GtixoL`FGVoTB6 zY$uQ1l%EMY{=YYgB?9;N>r6}D#y!{f7nJ-iHM?5IMQHuWL{8IE6TZ+6aedaDj5w;Yiv8Bjo zOHq_9MFCri(%DiJW1}d8fTBzSisA$mWf4%6O+Zl%0*Y!9P*jV6q67g&Ndk&;2q>ye zKv5k6is}+jRF8n7`UDg;AfTur0Y!}nC~8bVQ4<1+ni4`qzs3E{4oLhJdo220iq3Vf zi#E%OnJ-h+GAp?6W+`gL`K72eTZ;B$OHmuP6t!hbQ9HI2?a!8?1K3j3o-IWk*eJ>) zpr|7OMfn626%bHVNI+310*X2lP}GHhqOJrKbt9mtI{`&K2q@}FKv6FOiVh^8=pX`$ zdJ|A|Fabq<2q@}HKv6#eiuw~mMY&o2dk#qaIs0yGi>&Z7{lWHFG$1QxzD&`Otl+O( zrD!PUm!e^8DH_g}q9V2wjbKaBNVXJ>VoT9zwiJzFOVL<1ipCL8G@gK>2?P{PB%o*# z0Y!%pP&Ao1QeY> zK+#G9idGR&bRq#os|hGNiGZRt1QeZ2K+!1#6s;wo=u`rV))7#28UaP?38A7nS^gXc zB%W@cqs^6~Iri-O^sJcqGDT-*1*hF5MQ3q-DLR`iMVr`CbPijJ&Sgu{d2A`#%$B0_ z*-~@?TZ%4Zqi72OMHdlJbTI)%mk>~NDFH>75m0nF0Yz63P;?~$MOP6}bTt7**AP&2 zEdfQ>5m0nJ0Yx_uP;?^!MK=*pbTa`(w-8WtD*;8f5kf_0Wcjx`Ao1hvv1p?d{bt{q zy*(>tzD&{GS;0&9NYOo$d;my*i!T{TZ%qmqv%rtiasNt=yL*!z969J zO9G0%BB1DN0*byNpy*oyioPSDXg2{x-xE;u0|7-p5>T{|Xe?Wb#<8VnJX?w;uu(LTfTBqR z6dgi9(PRRO4ke)IFanAWC!lBw0Yyg;P;?{#Ma2XZO(meHgn*)H1QeALP&A!@qA~)C zW)M&`lYpXG1Qg9CplA*uR5Uc(ulcA`6xdfChe?tBg)`B)*)j8FiWX)E`HxG{BF-;G zi`i1Nge^toY$>W>OVLuc6fI**(NSzETF#cDquD4rhJd1D2`E}YK+$mo6dg}M(Fp_; ztt6mm6#+#j5>T|7fTEKKC|W~6(a8i9okBp-S^|nrC7@^>0Y#?~P_&+aqSFZ|+CV_j z8H7;L{A_=M0}>x-PpB72(Iguivt#DV6m7~5mOddx=Wu>0I+ra)=dq<|Gh2$zXG_rq zY$>{sEk#?{QgjhpiY{iO=n?{oE+wGoG6IS&C!pvG0*bCApy(OMSwY9W!61=)UaWfv2SCe$FpN53r?ZD_e>lWJ}RQY$0*ZDJQ1lW3 zMK2Rj^a=q*I|(Rym4Kqx2q=1;fTA}DD0-6+D!M1z-{pYB3+&T{oir&fg+c+Tc2kd+L?@G}p_E_{+cFcU4BELp3q^1QgXGpeR8=QIde790H1J6Hru# zfTFqt6xAc3s6GKj4G1V|NI+2|0*V?FP}GEgqNW5CH6x&?IRQnv1QfL(pr|DQMXd;- zqDT#Yo&yp;+`a*uRwMizt+snzv~`V``7%ZAY6Pcmm!kbSzaEPYU`tVZwiI<>OHm$M ziaN5TD4#7w1#BrQWJ^&eHi|kEP}GHhqOJrKbt9mtI{`&K2q@}FKv6FOiVh^8=pX`$ zdJ|A|Fabq<2q@}HKv6#eiuw~!G=PAjfdmu{BA{q60YyUyC>lx#6}741-|m3K_cu6g zr6|ijybY@nGhe1?WR2jJ9a1!k^GnfawiJzFOVL=i6pdp`(Rj8LO<+sWM79)7VoT8> zY!po7=x_pxrVvnc1OY`y5>Ql3K+#kJib@D5nnplTDFH>(2`DNfplAjG zMKcK~nngg-Yyyhr5KuIifTDQ>6wN1uii&FZ`y7yXCwnX!Aw~9OqUeGeG4o}LmedFu zz9L2CoL`D6*iy8VEk(=NQgjqsik7pb=xDYS9mAHQW7$%)f{mi%2q-$9fT9x!C|XHC z(JBIpP9&gcH33B@5m2;-fTEKLC_06JqO}ARok~E_Is%GLBcNzK0Y(20dG`SwRlT?I zeorPllMIlVgf1unK~RJwbWo)C-V_mq0HH&G0D_``fFjaSK|lo+v0%rJ3W$n|ief=T z#V(499ToNdf3u%&63=_yb^Z)@xTL~z7kbt6x2q=1(5GcB)OnANn z5`DqG>UgabU1*Q4A1MiuMvv^eO>GuMtqR zkAR}r2`GAlfTA}ED0+*4qWuIEy-h&T0RoENA)x3WAyD*KneYn^Nc4c+{X8y3o9){n z@0N*}FH`hE8UM?-rRYOWFGU}*rRZa}6n(;$qEFdU^ch=eihd%X=w||ojuBAw3jsyH5>WIT z0Y%3NDEgg%qCW^I`jdbnFI}IQqbNiO6un<296#U`J!JPqhotDJ{rGHBdc=I0qLg$$ z_n;I-IK335vZW}EEk#kb6qRC2QE9dmm0?R!I$MfjY$=MfQItVIQ6>RJWeF%MM?g_| z0*WdSP*jnCqDll5RVJY51Okex5KvT=fT9x#C_0INqG|*bWf4$Roq(bm1QeZ2Kv7Ks zifR#1bP6F*l$;(u+X0E*V{rWR;4^*qNZWnFmL4%*rl@YZf8l#lbULS(qIzs8s?V09 zY_=5Tu%#%MEkzC3Qq+(wMUB`})R>K;CIl2UC7`Go0Y%LTC~84K(HR63ok>7ZO9G0{ zBA}=h0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7pr{i8MV$#K>Ow$KR|1N<5duZ0ria%% zAkk^|vyP`p(I-Z#dwRrtnWEn5{u76!s1K)?qP}b?>c^I%{%k24z?P!3*-~^4TZ#s< zrRZF?6b)jd=sW_71`|+pJ^@7+5KuIPfTE!U6y*_6G>m|v;RF$0*b~HP&9#nqKO0)6%bG~i4Z92nI8Vo0g3LhU!T@XisJU@dUATi ze3_zY>3;YlDVomdrRYMo6wP2u(M+}!UBs56i`h~%i!DW$u%+lywiL}~qi7BRMRN%# zx{QFLc?1;AC!lBn0Y#S+P;>o_3MR(4-BRf^Wzqw8zaBj(E#txfm4d?H2bIK33D zXG_ubY$>{dEk!r7rDy|NiZ-&P=q9!l-OQGvTi7VtL_pE41Qcy1py)ONif$*M=nevk z?j)dS3jsxU5m0nD0Y&!^P;@T=MfVXuQ1l%EMc)%p^aBA!KN3*%69Gj(6Hs)FfTCXrDEgIvqTdK8 zI!-{*?*tV6K|s-;1QdBOecFzq5CKI=1Qdk{C`u*-iatya|LTB5pEWoiNzn`=<;NoC z%M_)>{3=JJD9Y)js1#d@O0%V?3|orQ*-{i^OHrIHMHy@<%4ADXSvHEw5l~c~fT9Wn z6jdaks1gB1l?f<1fqFgS*!K+!M)iiQ(VG=hMld;*F_5>PaXfTGa^6pbOE zXeULi= zH5M^nrf5dY|LQv_n#t*<=pwchUCfrES!^k~ge^svvZZJ?TZ-nerD!f&iY{ZLXdVGY z^9d+gKtR#u1QcCCK+!@1imoJ}Xb}NLR}oOOn1G@s1QabLplBHZMau~&T0ub3N&<>j z5m0nB0Y%pkP;@N;MXL!YT0;mFO^<~$zjulj*!R&cl%jimH?E6C%$F&;KIS+4QHpNh z^ip&qTZ%TYrD!8tif&>{(amfrx`i!8o7hrxD_e>-vr%*#0Y$eHP;>_YMRyWVw1t48 zy9g+{n}DKw2q?OjfTH^dD7v43q6Y{l+Dbstg9H>kL_pEQ1Qb0&K+&TF6g@^j(c=UZ zZ6l!Q2|}P~T`WA%0f{!U`=a$ybb@_EdomU=U#4hh%%AzQ6g|!9rDzvhik@Lh(X(tR zdX6ncyV+9oJX?xhU`x@9Y$@8qM$t0Y$G9Q1k`? zMQ;*N^cDd{`w1v|n}DJN1QfkPK+!=0iryul=sg08-Y1~w5CKIW5K#0XAyBkE7QVp& ziT1Kj%XUanRr?a;N3n?cGDV-o{HK1AqR%iGZS?2`D;7K+!J*6#Ys-(QgD49VejZcLIw3 zAfV_^0*bu2K5a))h=8Ib0*b-}6eSZ-^ib}_Q|F{&D;q+3J&X%GWTZ-arDav3=Q6^i8%Ce=X99xRYv!$p48$}ffD5^w2 zQDp*(P9UJD3IRn`2`D;|fTEKKD5^$4Q5FG3)d?u7K|s;T1QgXIpr{rBMW+x@RGWaJ zIs_D*NXV~}AO2vcE^q;a1Z}s94^JR*1<9@e4q^JR> zm!gJjDQd))qQ-0~YQmPHrfex{#+IVyY$KwiI2!mZBkSDH_T~Q62$B!w4uEPC(HJ0*dkpC>lvX(I^6nMiWpphJd26 z1Qd-UplCb+MH2`pnn*xV0Rcsm2q>CNK+zNeiV6uRno2;?Gy;mI69Ps3}J+_c?2q?OWfTG0&6fGg3Xej|j%Lpi1PC(HL0*Y1=P_&AG zqN@ogx`u$FYY8Y?O+e8a0*bC9plB@tMe7KGqM7mVaR(%tZeP2;NQ&0lebM@O#C(~e z4RQZO_v;`M_eC2yy%gQVmZF>4QgjPjiZ-#O=vKBAZDvc+ZEPvJoh?Oouu*g;0YzH~ zD7uS)qPqzwx`%+GdkHAIkAR~42`GAifTFDg6g@~l(L)3jJxoB+BLoyZNWIm0Y&c-Q1m_lMTZC|`hb9<4+$vxh=8Jx z2`Ku65GZ;&9$x5xMEBdLWxJ&4W_xt~X*^=SOwku{|MoN~`jXR2(Gj*3eZ`iduh~-c z4O@zivZd%-wiJEGmZI<3QuG5GML!Zy^b-L^KNC=NjDVtF2q^lMfTG_BC^}9+(eDHl z{Xsy{p9ByXKv5O}Mb!x?szE@}$pjSDB%r7k0Y#?}P*j_M zqB;Z=ok~E_X#^D2C7|eZ0*dMpP*k6QqHIE-s7ywwiKPomZFwyDLRXdqE-YHwI-mb z4FN@M2`FkuKv8=FiaHQb)RBOqP6QNnCZMPb0YzO2DC$N)QFj80dJs_5lYpXL1Qhiq zpr{W4MSTe<>PJ9Pe?p+BK}L9x0}_4M9tt&-qT2T8dO$|Re3_ziGyIF=QZ$IuOVN33 zDH_a{qVw5ObOBq6hOnh*C|ip1*itl%Ek(oGC>lXPQ9c1hBMB%PML^ML0*b~EP&Af+ zqHzQijVGXJ0s%!62`DNcplA{SMUx3AnnFNPApu2G2`HLIK+$vpiY_FeXa)gAGYNsB zb27pk9FXWvyDu6jMT_kt+C>==^JR)I&G2_*O3`diFGX|MQZ$z>MVGOqXdYXN=Ch?} z0b7bLXG_r)Y$;mEM$wf76fGj4=qdt=786jkgn*)@1QabJplCS(MJos>T1i0BDguhG zCZOmV0*bCBplCG#MQaEsx{iRNwFDHcBcNzK0Y%pnP;>(!P&6we{HX&HZD4mlmq^hv z8#iV|%$F&;Im3^Xm!exZy%cR?OVO=tDca1IqTAR~bURy$?qEyNoop%E!j_`D*eJT2 zfTDW{D7u$`qWcIax}Sie2M8$INJXqPccov@0WGzD&{X48KQ3 zDSDpMOVJB#DSDADMSIv%^b%W&US>7*;4cx8%6sFD0-cMqBjUAdXs>n zw+JZOPe9Sz1QZ=0py(X}iVhM`^ezEK?-5Y+J^@9C2q^l1fT9lxDEf$iqK^qE`hY5mZHjR zDLR2IMOD~RRF#dQ6A36fiGZSN1QcZvP*k0Oq8bDgolHPcO#+H)5m0mr0Y$Y5D5^t1 z(WwL!okl=WT>^?uC!nYv0Y&u*D9R?FD2ITeTmp(35CTQ<%fy!Iq*k*iv*RTZ&q;rRXfS6t!YYQERpowPB;E zEdfRC2qQ6w?00N56CZOmXLZGN|X1Kir60K`+nn+QG-4_kajF>M|G&s}GcmE=B z;`?alb9yPdfGtHs*itlqTy^Q8o`#Le6|#gWTR*l0Y#$;C>ldR(O3eC z#t~37o`9kW1Qbmqps0X=qDcf4O(vjd3IRoh1QbmrplBKaMbil=x{!dP83Yu~B%tUb z0*WpsplB8$P&6nryvPBG=Gjk%oF_$R*k6>rBr{^ZOwrs-|IQjxbQ!0YqIqm7n$MP^ z1#Bt0oGnFHu%&1rTZ*n^OVJ{>6kWwe(P9FMmJm?1lz^gT1QabNplAgFMJov?T17z7 z)dUn>LqO5B1Qe|%plA&NMb{Bfw3dLPbp#ZxC!pwh0*Y=Rpy);diZ&2Xw2=@fnw=Tm z>wrW*bu)R66n$gkrp$=>^3uJe^ynl<~ZBv1?+US1I;RhUZm{RWIjxS+P+SJg;W#u1cO)C-(gbo_Bhz`H7yF6PsPl z^BTpTsqT5rVx?+&-kGsJr+8lL*y=i-*FN^{X`a_Pc5*$>>mD1E?RmXp_vCtB|JaWW zJ#S#_j3%BpI5xML=M9ZL*TVBg#LBevywS0Ktvqjh?7B9dH!1dhJI|XMtJTr-X2iyI z_PklK`?`AGoY>FZJ#T)jWiQWL7@OC}^A^XR@8@~TW3jV6@9Nlqfu6S}wr-H;t&e>$ z*z-2TY7g@^w zWY60byS~u#cE>)N=6QQ!r@DUana~FBu(b$cPJ@1FuCrdr=Sgh^}&pRHUyvkkwq4>ksxEml8|9!Q) z1w!$5Yu!x{ieI_j-3FofD>t|sArvpa(cKE6_<1+Gn;{h6xXIlPp}75P_BBIs`{&5( zgyQz^NuM5y+dl}L6N=lv=-Mb0w||neStxG*rsA2Qxc#GetwVA9SIydo;`Yx{bq>Yt z-xcZ}iXYzYZj(^l{$-E;p}76i3gS#v^h`z=TFL-8jLxmzd{x8F0eI25;E z6tO%Mx4-FsbtrCsReMb+ZhzNyeJE~!S#m=tZhzbDmQdXOy3%c-xcz;TEupymg@JoR zar=qyt)aO6$nGPdxc$uKwou%DXl{EbZa?+3D-^dMTiG3o+s_^B3B~Oj$9qF@`_A9% zp}2kPW`8JdUwc0oirW`Y4~63P)vu33ar^Sc=b^ZL{&^%6w@)CBhT`@J@P|;`K7=0& z#qB=$c*x7xnx)T6yjm~!=P%S;FX?Qr)AMDUs8U=Q_ zT4{{5OVBzP<VTYymEGqmKqeNDM}rR)1^uSm2$muiq$6r~FD-Ft8EiF+?nGH!hAnfaF{-i^}+HcLso8(jx==#h9g>V)5O?{&qE z?mo}{^OM3U6_>bc%l`9gg`-|5BUCHBY^iX1mGl7>Gu$5*&r7Q5l`3_XOP&|5;Dys$ zlscnS^HN>Py4zkaNp&Y~>{&@E8!A;Qc!iLgkuqL5mDev-s!XZUrJA`LH?`tlUMtPL zR*7?sYWl$&DW$V?)6TNA&NA`R;aprI+zS z?#aEbNv~f&drDsR$ihk4g;R!SPZ?4;Jb%cfDFsvWhfmEPkv)9M%t=!VEDX;dF>OkI zVTqU7>$}%(o;_*Gm zVRn9lA%#TCSH>_tbuJ2y_mltJ^nK*p>v=RB)6Y_?S9y9U(^NUe9v#{hfF=}*n zn<*ovjhR@`u3$=jy`t-4#?&c^t0cHadQT}B>#p;{?0%E-ri|-2ZQ_vr?tK~6d;GM* zA${94>CyP#aWhTNo0@OemgfaG^vG!whv(!psXyE(3>lF>GH=@WsY9mDoRnW!f3yj6 zH`joCM!%;D_{CQK-p=$gX^m@#(NLGs*(3qPSV+%V+(W&gJ)Ka>(4 z=5&_?BIH0X1NzPNW5BBj-PqbKlsYo zepU@X^TdDlO_Z(fS9fnEI9=JqMa%iiMXO%&qSa4awDKvTZhl#NZ?b*&e9M2+^L}P_ zb>F?qWveF6Ik=wwq3bJg^<@Ruo?XP6?%FGBXZ6otAOF-q@}GNm z{!7mJpSoJkbl1JzZI%t#{TJU9?%hf{t=xb3&gq}J3IC}p`d|C_^iN%$|J*D8|K~mZ z&s~TA+Wq=}|Ed1lZ2VtdWB+aM`+wWz`Op1n`mcRYQ|JHX6M=uj=P3WVEAhYokIMh$ zCH%j9TmQM+^gnmb+1c48KT+lpdv@Ysf2ev=+CpM$#w+^db4Hetfd;GFcj zjd;Ut6q*)Y0C$BJopaF}X~f%TUwmb_t3a>lE^=@+x^oGhDRB{+a#DBYC0^*RSe>qM z(V4l+!y9d&*Kb&SIocJSBDWoH%3W}s!UUA~`ryCot77f*hfN#hxi2M79F;#Lf8vNS zc@u|>FPJzgcn950;@-Ub+FOa+L>H}5@uhXQfAH!>?;g-{ir>5DMej+jGwgNiaPE*c z?fWK9=WbfPla8>SYyX#1dUlbr694-j%yNq_NLxt)oVytlZvbIMh61tnN3TQT)MM>W zOX5{?bQTV;E=k*>%Vd8{6R*^!_`; z9NaxZ;sWFr>&kV!f|kPzi^1h~e6U-bgp?5c`6qeTg$SCnxa& zcXy==mg_DV&*m0iKP7JNraCijl0cH3eY4^#&t0{_TWr9aE~b!MY$3M<26uY}Cn>(! zxm9x8>YCs-XP;_c{3+Nn+F9El) zyN2|#qTABl1i@Pu=IOv04 zv4-4Y4n+cs6}XS9?)(c!7fhL2^r6gQ<5C1SdeQA&^g-ACp-H@o-6jb^?%D{RDM6t4 zCeJOt&2x)ybZ(JccVQDJb{~}!N3QW)=QlXl5;th^?dRUOuA5xQ8Xr)2ch7a8liold|fK%Bt6^K~_EYO_Y|y-36#OazcJ# zVcw|xdgJpaj+#2UWsXb1gN}N3tGi`)S5wCnOsrSvz8U0>g|3aro0?a&gR8=Q;0~TC zCYxJq);RueA8P`ZB|aV&*>iRi=UMy!&NSL}T>Ln$_|aQ#06ZbZ-8buE72iUE@}duR z3DiS|{PiO-4U0N@vw(?Fy%oWK7 zwmonhS9CYX|aK#VdAYOF)7d=8Odgxd5D6hnyrQ$yk#gEarxr0Y&|ITj%>$}Ls z-(0jSr^ra~7}D$1u3d|)I`&7i&6EjQ9VQIRA2Gr`_U_O3g%f{T`F`)I|NEa^_kDc# zo$No|ll$iRtaSHHefRD2q9^+%c$@V2yyW@e1xZUoUYq9bMS1r9WG|HMp7op6>ruZ) zn=U=Ql#ED^v~V;vGr3%-e5hi$QmAt1giw`G)zC>vHA406+vR`rR5B%d-~L(h#bNt~ zYKf zxgE>vSlN#5>Zxu=_m0(3H-GkeO>}fWrf7Ob+n&2vE4z(^W6Jtdz6kF-1}zx zE*(F0&)fc9$I~4|+s$>H;;u8>vvqvL{eiXpjE;Yt5bRP_f@6F4Ly`9KJ~}R{7VOnJ z?sZqJz5HDrE7T13$vO@`CD>zhyvf}F_WJke`1xtU{!z#J^@4qdj#J$YWv@S1$H#Jm z{hW?oqhOcOv7@^|?e+WVxVTxcuha3h7QudB$4c&ox7V+w;{~mPJx<44+64PP9lvN7 z?4Nba=@{&mI!^B#?0GtF>l*Cmbxi6J?3j+7dj)%dj!XLld!3H2_Y3w1I-YQLuxsl$ zbYQS2=y>a(U_YSak-@?KMaKq1g565T8F|58pyQJcx?LYH>X~=cNS{3Xob=-MPuwT(Jbxp9#>)3N`u+P)+>h;0isN(^5M`*XtXF6tW40b&oN8TLl zLLIkk3ihKqez!T;f9lxmj$n7t@zO29zDmbkcL)1b9i#UJyP}T09|-pOI$rx=uy5A! z;KRW_tYeMGf}O47=xxECrsLgD2K#Xxf7l-E(2n5P;_2YnNyjUjUrU_YhfvG0QIe;*vr`Y||m({cXK!Cs-`3+^YD?d`p#WBhoqPt@`3KY~46 z$Mx<}hQ0pnI)3PWs@e88I@WPNuV%ZkjuRunzF5bt?gyUj{VcTYRXXl*KNM~IZ5=b+Pe; zbv(`e1hws^I!?+8_9Z$#Ro&lEuzjkIId=3tua$Op9naNqq>hC;&e3s+ zj%#(?tm9T4cj)-Cj_=sfy`3`d$BFHjrDH=KJL-6@j^lNlt>a1^H|h9>9o_r!wvHd_ z_^FO5_IRhX`^j88y0>Rfc61MO630S&{NuKJ7~&;my1xdX?$s}xIbmwvFn63fB{+`e zIrsH|sa}2i1l+4Xtgz6l@4jSE-(vm0KI}~N5%#5M_x1mg1@0t?=ktaQo0300IF-s2 zdqk=;3ex{9VIv_A+~_?fy%3|NXzcUXFX6zkRzU ze^A+OD|zy9udPUD{SvfU?sgG&USbq_`U@_JWghrBF1fu4B1VQ!avyBh|D z5JHP(UJWssr z3KvSA-*$I?cD>r=E93s-{8qc??KF1#*;A}-$UDpZS>wrGX8+x!Bd^z^XUOZyE9qtS zdiUsgUbM!&p55j=+1s_JJKcXJFW>GG@2|TnD7t*x-1E-fBzH(W?Q-YWg5i$#Htord z*iM9AA@>(+g3r~;yI^nEu6KKzSa#2PbDY19_Kco5Kf4SiUvIy=e0z8$cjWa-{j!5Xa-TtR zzE*a-_tic5jqLyKWfi>&Ub~-$P3rZ-q`XJEKH4q5b?33<(9UCf<2#S-%6aWra;{hR zw*y*^X+$Lw&gGdS`8^@;x< zO#FXi_tc>;468AEMdbS&tC;q=a@&AK~|1Z*cuhe;8{+IKPXRaS#bl&4<|K0OmU!&@T#Ca$FzdrH* zgNgqa>b#fhybJzv-jy=fPb@m`iKGASd0$_nYC+<>6aQbI`2WG6{LOVT@Gs|`mAUWO z!q%MozGI8CdjH+?Us+?{vE{ApE$lmXwT^3aT%S0${hRCOtiQaSI_~Y}&x z@p$4`p>t^`IBB$$^)K5sqsy+m?ZpSKZL}LJrRxs& zCn|Ml+0p9)Oa0D2mfUS$-lR@;nVyJvtvi&S<9+KM2L<RSyJ$(hDi2Mh$UE-- zDk;^s4`oTIkt*&UDLL76Wwg+{)I-(s%|#&lIv<#akH_P ze7fcdZZ>iM$b)8OH=BCN^))NG+00AM)~x7ebN729H7mH8>n>KVc6r^n@4c+DIpdGU9E?-A&#~?L1xn}rzcl)Q!F+a5uzr!Of*U3ok6xr-v z!Gv`4?Jqeegml+QC8UR@g!I&ukY1V+(pytP`e;f>Urh<=rzs)*H6>(#CPL2EM#wqZ z2pOo2kaM*WGDsUC=V>Ekur@-@*G9+%+6WneBV@ETLdIw#WUMwq#%Tvax`e-Uw}0Bz?v5t8YapbPyN601A2B&5WRh=x0X`vQ zvQ8=?Q#2){P*XytYD&m7O$nK9H`{f7;A=m1p60%xTLe^+X z$aR_$vQ|?<)@e$}dQAzrUQd)Gm~X#0BO&B*om4`$X-dcwniBG)ri47DDIwc6 zC1i)DgzVImkf${zWS1sFp3z3gv)TxGP8%V+wGr~XHbP#|M#ziW2-%~Jke9R(^0GEU zUeQL#UTuWDs*RA>v=OpT8zHZ2BjgQjguJPZkhioEvR@k^Z)+pufOa6{k#HY(`=@iKCFDa*3HeABLK`7pY9r)`HbTDAM#$IN2>C`EAxE_l@~t*PzSBm?_u2^gK^q}IY9r() zZG`-+jgVv72>C@DA-`%P&>o+{5vGp6CqHO(!r&4VF zhNseO{f4J9Z2g9(bT+@?DMsKoJjDt8hNlbyzu_s9z;AdeOW-#=l_T&Qp2`#W4Nnya z{D!BB1b)L)B?7gbp z>I8nnQw;*Y;pt=ozu~DS!2v0goSYO2Kjwf$H`>FKa41l8z#g~M3Pp^UDLOUe+pla& zC_0VPOHp066rIkNqIzs8s?V09Y_=5Tu%#%MEkzC3Qq+)*qDBN1H71~_2?0e-2`Fkt zKv8o7idqm*bOr%MXA)4zD!ZikZ-^8E1{?trl*b(HH`X#u898j)0=^1QbmmplBi?P}DsX?&yF- zx4N0!LyBq|sRH+7S@w+^r>HRG+pmmED4NRYrDz&kil(!r=t8y>&0tH>OtutV#FnCq z*-|u%Ek&2GQFJK*MY9PgnnOU*Tmp(NBcNy=0Y&o(C|W>3(d7gbT|q$6LIR4eB%o*! z0Yz64P_&qUq9p_rEhV66839Gh2`E}YK+#G9idGQT|6fTG(7D7u}1qB{sEx|4vSEd&(ZML^Nr1QgvvK+(Mf6x~Na(ftGz zJwQOwRsxD1B%tUa0*W3cpy&}opy=9A_%#P4da8Z;wOWdLnxaQT5%Xn=o(TE&D=QO< zp5*jW^b}i)wzH*Z2V07EvZd&0wiNAROVKlIDSDPIMbEKOw3~pU=Lsl!fq0Y$G9Q1k`?MQ;*N^cDd{`w1v|n}DJN1QfkP zK+!=0irysziXIPzE4iOCi5|62+_y>5UVC)?UMOO|OworS-+tw3LeWQ@UWz_uOVKB6 zDf*NxMW3;y=ySFd9cD|>7i=l|k}X9?*eLpnfTFJnDEfwgqN4;9eM>;mcLWrDPe9QR z1Qh*9K+#VG6#Yy<(J=ywej%XfR|1NDBcSLw0Y$$PQ1k}@MSl`dhwiK0S zOHmoN6s5DJD8`neI9rM`*eJ>*pr|YXMdb)6Do;RB1pQl$fTGF-6rDgoQ56D; zsuECiA^}Aw5l~c(fTAn{imDS(RD*z`lL;uQNkCC80{2Cy5KvT`5GZoLob(n4Bzl4S z?t5}dQt+AnvvyxpCn;jSOws8{zWvJOgra(!UW)3or6`*%MLBFK%4JJY1GW@3WJ^&a zwiGpHOHmUxikcEo)Qo_l<^&YAAfV_B0*cNgpr|DQMQ0IE)QW(j)&vx_A)u%&0Y&Wy zC~8kYQ3nEwIucOSiGZTc1Qc~4pr|VWMcoJ}>P`q0ot6~-!U2h9xSxAVt}8`h`%J$_ zQp9|jqCQE!{mSlyqQ0D7iu$pos6ShZ2C${*Y_=4g!lmU(QpEaMi5YxPe9Q~0*XcvP&Ar=qA>&%jU}LH905h+ z2`HLCK+!}3iV6rQnnXa+WI~{*S5i2~0g3jo`=Z`b)ZRX#O-YKFFH4--)I2mwWp5>WIQ0Y#4!0!7y)g||5% z(d8irXRQ>qu=}EINfGm9inb^D_D@bE?u&MCdMVn;mZGQGQnZULMbEIM=vlTDJ;#=! z-E1j(o-IW$uu=3P0Y!TVD0+#2qL&FMdWC?Zy#y4!NDDFmLwE?%IT%(Gqx0c&X%IXY$^JJEk$3lrRWG-ioRk?(bsG#`i707 zqXZOvOF+?g1QdNwK+z8b6#Ym*(N6>v{Y*g7F#?KyA)x420*Zbkpy)UOMZXhJ^alY& ze-cpSegb)&yBXbg)ZGneKXw`-peTueqA&qP$pjSngh0_pN#V{8NOY*(7kw;6M{T5p zBj(E#MZ>=RlQ#)Pr8vD5m1av(8MYLqv!y7;mZCUYiZa+zl*yK&vTP|T$3{_k0*WdS zP*jnCqDll5RVJY51Okex5KvT=fT9x#C_0INqG|*bWf4$Roq(bm1QeZ2Kv7KsifR#1 zbP54QwFxMyLqO4~1QeY{2o$A;!%H2I=m7hwV_G=)On;l*7u5|%%$F(34*T{`CM6W* zaC#}qWlK>5wiGpFOHm`X6g6f`Q4_WlHDyatGqw~pXQQYE0YzsJP;@2%MJ)*^I*Wj! zRsPA3OcLIuf5Kz>U zfTCW6KvBJL_;m*)I@}%#)t91A?Y^jYIAXp`QU9=S|KwIe(Ev^_MQ5|6=p42b4P;Bv zxojyK#FnD-*itl@Ek)lpV(Rc!iCJ<0Gk$|EC0*WRPP&AooPeS$2q;=eK+%;16fGj4=qdt=786jkgn*)@1QabJplCS( zMJos>T1i0BDguhGCZOmV0*bCBplCG#MQaEsx{eSix-c9b>VQNW*nQCqDLUCcqOA=_ z%$F&;A?({f`Ik_1Bd3?54Qwge$d;m;*iv*eTZ(RBOVK8_6y3^}qRnh6x{ZyZ+X*PT zgMgwt2`Jh^K+#EC0I zuInd9%$F%@knCUAMv5A8dMRqemZHXNDQd!&qNZ#qYQ~nL=4>fy!Iq*k*iv*R8$~S% zC_0OPqE-YHwI-mb4FN@M2`FkuKv8=FiaHQb)RBOqP6QNnCZMPb0YzO2DC$N)QFj80 zdJs_5lYpXL1Qhiqpr{W4MSTf@qMYRLlMYC9o}0o|G>m|v;RF$0*b~HP&9#nqKO0)6%bG~iGZTX1Qbmnps0|5qNxNFO(URa zIsru&5&}g7lEcaEoubd}tBz+&(I&eunvonaU#4hQvTy(7dP319oL-79WlPa)wiL}_ zOVM1m6kW!aqIqm7n$MP^1#Bt0oQT1i0BDguhGCZOmV0*bCBplCG#MQaEsx{iRNwFDHcBcNzKAy9Nta=5Dl z5rRZk16y3s>qD^cmx|J{vjiN0C6x~HY(cJ_T-9tdpy#y59M?lg21Qb0$K+#qLiXJ4O=ph1%9wwmZ z5dw-HC7|dr0*W3dplBNbMNbe=^dtdAPZ3bGoq(bpgh0`a$>HS=NOXtY7j2ND$@UR# zXL7`RnWATt{rkE~(Q}+$igvT5=y|pjy}*{D7uiy@hb=`fv8Cu`wiLa>mZH6E6unA7 z(Q5=0?IWP*bpndsAfV_?0*c-uplCkNPaC#}qWJ^(5wiK0P zOHp~Y6jfkLQAM^CRbop~WwsQZz(!FO0*a~zMJEwZRE>b5ECPzE6HruxfTEKL zD5^<7Q7rxtMNQdK)Ql}f&Dm1af-Oa7u%+lswiLBw zOVL?uDQd+=QELK<+7M9GmVlym1QfL=pr``@MI8w!>O??MX99}45Kz>WfTC^$6m=({ zs0RT>Jqal4MLk1p!`V_af{mhl0*XcwP&A5w zqR|8tjUk|DECEI12q+p)K+yyOiY5|JR6sz{Bm#;i6HqjTfTBVIil!1!G>w3w=>!yA zNI=mH0*Yo5P;?O?P&CjFf9-%om)Jw0bERmV-4|W#N6eQgn(h0sv!!Sbr{o zEk*O#QZ%0}MGM$cbU9m!u3$^iLbeoL$wtv40*bC8plC4xMN0@MT1r6CG6IU06Hv5* zfTEQI6s;nl=xPFrt|6f4S^|nz6Hv54Jpn~G5Kwd@Ay9OQ zA8zD;Lf7`-O84t&1@;UjV(pDv!&<`wiMmT zmZB|eDY}a-MR&7NbPoYV_YzQa9|1-86HxR30YzI0D0+~9qK615dYFKsM+hi-lz^hg z2q=1-fTC>#6g@#e(USxeJw-s#b^?la5Ky#}fTE`fDB48`6y4;9FLFSl!|dm-Zjp{D3!GkxUSvzr9<~&{#FnC$*;4chTZ;CwrRY_*6urilqJ3-> zy-q;U8w3=+NkGwC1QhKjpy+J^iVhG^^bP?<2MH*8mw=-82q=1=fTBYL6n#KI(T4;S zeMCUf#{?98LO{`{1QdNnK+)#}6dfi6ik|bs+Z~W-y4@G;mZIAB5$y{S*zKv9%{qEZAD zl_sF53;{*ygh0^|Kb&&DQ)J(FP5w%XUbRpAV<{2yWs1tC__c>fQ8`X8MdjI2RDmr; z71>f$i7iEy*-~@@TZ*c%rKl=ficVys=p+J)su56>MLsfTA1%igF1kYCu3yLqeb^BPHD3 z0g2vhkFGOQg3t6L_SdZ&r9{k^DQcGDPso#^=A2%NTCk<)47L=V$(Ev)Y$-a6Ek&)^ zQq-C)MQzwp)Rv8+b_5i)C!nYU0Yx1NDC$H&QD*{*x)4y*m4Kpd1Qc~Apr{7{MLh{9 z>P0|NZvu+?5Kz>YfTDf`6!j;dXaE64XA@9#4gp0234x*}DdCk4Nc1^-T+~#GHrcmB z&P|D!FH>}WivPfHDY}5uOVJRv6b)rdQ65{0hOwn+I9rNFu%#%UEkz^QQZ$Nw3w=>!yANI=mH z0*Yo5P;?OiMHdrLG>d?uO9+9Y^HRe59gyf6`>Nw$DVl5_(JoDim@iXwS&IKlz7);l z^injREkz61Qgk_6imqTw(L%NqUCEZBMQka$iY-Np*(h2jTH3Sr0M?le90*clVP_&+aqU#ALx`BYA8wn`dKtRz( z0*Y=T1d8UQgijjj6jiea)N`dMocM$-C1Soz(dHDt)o3ZYjnhlf?QAK!gDpjOvZZJX zTZ-;tOVQnIDY}O(Mfb9$=sq@z?kAw=0RoD)5>WIY0YwiHQ1mbXMUN0r^e6#Ej}cJx zH~~f52q=1jfTAY}D0+&3qU{6}?I56NCjmuI6Hv5^fTCvzD0-HFqUQ*KqD?8`5e`W7 zE4%x-RfdX+6jud$_QA6trEXG_r= zY$*DB4dz(c1(R9U!3S9Ri9D5>WIm0Y&c-Q1m_lMTZC|`hb9<4+$vxh=8Jx z2`Ku6fTB+cDEf?mqR$B^I!r*(7X%c2NkGvNLZIk{l<*x6NOYThM0-(+TH2@mU!_FM zmnr%-#eZ?U6n)3(rRaOM6#c-Kq955(^b=c(er8M2F}4)_!j__6*;4cy8%4(nDEgg% zqCW^I`jdbnFQQM|Q4}JeD2afgFabr$1QhuM6r~VQ6d|A}m4Ko&0*ayp6qO>Ns5AjZ zWe6xrC!i=sKvA54q6|Wy=$n-AQ3oXYq}}}-m7atSDEKtNGL0*V?DP}G=!q9%ku zQMpLCi31X?VxQ@kj|89T|7dqiO(PNWWs1&-_~%TPqBA+Y6t!ea(OGOMYQ>hK)@&(i z!OnwJPXda15m3~d zfTBJG6!j&bs2>4E{Rt=sibk@fXcSwDMzf`83|orE zvQadSfTHmP6ipzYXd(ec1q2jLBA{q80Yy^?C@LhNXet3k(+DVT{(fTE2A z6x~EX(ai)D-9kXoCPJWSUL>44-6`7WX7YR~y2C!A-5QCQFH>|!#6NY06y3?`rDzLV zitb`d(cNq*x`!=A_p+tvKDHFy&z7PG*iy8WjiLt$D0+y1qK646dW3+YM+qo;jDVuY z2`Jh|K+zKf6g^2m(NhEzZ6}~;2LVMp2`GA+fTCRl6g@*g(X#{;Jx4&%ZUTy)C!pvB zLZIljNVum15`EVGZtU$+bdKE@y%>p@FH`hN#4or=iuQ7PDSDMHMX#}?XdhdOUS~_u z8*C|hlPyJWv88A~TZ-Ohqv!wuMeh($bdZ3ecL^wZkAR~02`D;5K+y*T6n#iQ(MJRn zeM~^nCj=CIN?6G66+C0YxbU6h#OqN+qBujew#k0Y#+Rwo|mqz5`MzHTX=wynRG#ks2{yrs%9xzs+1JYQ^cLs5M)P z+OValEnAA(v8AXzTZ%fcrKlrYiaN2Ss52WyT?i=ZNn(0}?&M;Ix#YNp@c}BsF5bOwsUE|B881G=kGhQ9fIWMzW=76kCc$v!!SZTZ+cA zrDz;mipI00XaXBW6A36PAfRXx0Y#GuD4Ie*Q6T|EQwb=VMnKVY0*WpqplAjGMKcK~ zx`=?HiwP*2ML^Ld1QcCLK+$XhisledG?##)%Lpi%M+g+P_%}CqU#7KT1!CDIs%H;6Hs(L0Yx_uP;?^!MH>hx+DJgrO#~F( zOhC~s1Qcx|py*ZtiZ&BabQ>X1ba`s{I|n3scgVrHLW(l%(e>@A5%Xn=?n?E`E|j9X zIlUC!!80p(wiLa=mZCS= zQuG#EiuSXm=xw$X9bik*J8UUB$VSn-1QfkTK+*dI6dfX<=mP?ZJ|v*%BLa#(CZOmO z0*XE*py)FKiasZx=r93AUl36AB>_c82q^lBfTFJnDEfwgqN4;9eM>;mcZ5LE-qi4= z4v71B=HR?4MPJ$%vcFG_m@iZGbE<#iVktVt>80owwiNx!mZIO-QgoaxMZdG9=nu9O z{mGUhFHN7fOHqi8q9g)}!UPm06Hw$6P?SPIQG|e^R04|92q=mYP*jS5qS6Eul_8)g zoq(bk0Yz~FiZTc&$|RtuECEI32q-E~Kv4w(iYgKUML(v7cR3)@^X&okPg3-Q-4|6# zisfTA1%igF1kYCu3yLjsB#5m3~afTAV@6g4HF zs2Kr8%?T)KK|s+N1QeY~2o#-=7LG1+iVE%b7gb3MKGWZ9qh(see3_y)X@1=mQq-2y zOHn(v6t!ndQ3tjZb!1CXC$z(I5hf&Lf~`Fabs96Hs&k0YyUyC>lyY zQ63>s)G969+X0Dou=}FcQsmjA>tSgT^JR)grumasNzo`yFGZu-QZ$AwMPu1gG>$Dr z3(dC3d(TKG0wGK!$-R^$! zrRXdBMf_K!Ma-8ex+=|o_!=o%%;}|Q30sPmvZZJlTZ)#mrDz3PidM3vXcb$Eu4YTo zHEa}JOF+?T0*clUP;?yuMQaHtT1P<9dIE~BC!pvC0*Y=VplAaDMH>kyx`}|In+Yho zg@B?>1Qgv$K+$Fbif$vI=yn2%?jWG(PC}sQ%Czu72PE3T&E!Q=)X6^W-;x$FU#95Z zH2?S2Qgk1um!kXGQuF{@ing+)=s~s=J;auxhuKo}2wRFCWlPaxY!p3CK+!e=ik={# z=t%;Ko+6-VI{`&I2q@Y~K+)3#6zw9Q=otcvo+Y5@IRc7y6HxR#0YxtmQ1l`JMSBP+ zdWnFdmkB6(g@B^Hgh0{VY2g}coT7R5g~ofNsFd%T8P z8}^2Z3W|z)e&1Qooy7Ou@4L@+u6_17e{8NxSDrgrlOgkAGHHOKy#y5PBZP`})byu0 zAn|VY!TnAt+H7B%{k3Mye3_y@Y6j=6lcGO4Uy2T}rRXoV6#dPXqJP*@Lu?OHnhn6dlZ#qC?nH)SN9vhq9&UFt!vO&X%GUY$7lAfTut0Y#k%DC$f=Q5OP=x)M;-jew#f z2`K7LKv53@ijE?ns3##*)FkfjbwJ`T+TBmnc=(b2Z8mzvW9G{g^@|5})=N=;&X=MA zY$+PZmZCvyDH_a{q9JT48p@WUVQeWH&X%I1*(e%8K+#A7ibfGoG@5{-F$5HiC7@^= z0Y%3UP;@K-MdJx5I*x#%;|VA_fqG6qT{1sGN8^Sp*a zqN@lfx|)EZbp#Y$LqO5B1QcCIK+*LC6s;$q=mr9cHV{yBBLPJ>5m0n90Y$eEP;@H+ zMYj=9bUOh>cMwo?Cjmuw5m0nDAyl+7?my>%#5>t18ZVThJo`xho_NfBnW9bc;Hz7t zXfx+a(fw>GdVnoO53;4`A+{7f%$A}@*i!T;TZ*=@rRXs>iXJDR=m`Rfwh~bEBmqTF z5m59r0Y%RcQ1mPTMb8mX^gIDYFAz}lA^}A&5m59p0Y%#gD0+o}qE`thdX0dh?F1CP zPC(Hc1QhKcgo-xC{mfgPqCX7IeNwb9^#NNvX1+|(JMo~+?NanE=S$IhY$vQ1k-S*yKv6aUMF|3mk^~gx5Kxp$Kv69MifR*3 zREL0~x&#!}BcP~00Ywc6C~8PRQ6mD18WT{|gb*tFGw!c-K;k>>zUY7yUE!V=ZJH4? zU#95bjNswBrRWgOm!jruDLRxbMTfDa=y0|awO~t8OSTjp!Iq*{Y$PSFQCjyE(6HwHJfTFGh6m=t@=tu&Jx)V^;gMgx= z2q@}FKv6FOih2`J)Q1o%%FFOSazNq_*;iwmWrQE;pJn$&eKTU_%M=aF2>!WOiUx7M z6b)ue(Ga#24P{HwFt!v8XG_u1Y$+PSmZFhtDH_E_(P#pS#t=|6mVlyh1QZ=ZK+&-T z6pbgK=r{t3jwhh#1OkdC5Kwd?0YxVfP*g-f(L@4@iU}y1L_kpq0Y#GuC@LkOXbJ&E zQwgD>{uzGrjZV?G_F2aPQgnfPUUXVU%zT-mnHfRUBdZNbSYbkE@Mm4(UMH>hxx{-jQn+PbnnSi2O2q?OhfTG(7 zD7u}1qB{sEx|4vSy9g+{n}DKw2q?OjfTE3rP|?L1{=E)J{1Lk^S|vrD?LFFk88P!^ ziXO-aUVl)E9^`x}dWbDW53{A{5w;XP%9f%nY$Brip2Y$@{DQWRxNQNWg> zbhZ@5*iux3Ek!liQWR&SD1(5aOah9s2q?-XpeR8=QIde790H1R2`H*XKv8W1is}$h zRF{CFdIS{JC!nYS0Ywc7C~8DNQDXv%nh;Rblz^gx2q?-Ugo^&o@XvBU;-A?!?EfQ0 z?cDRC%`#)=%M=}&8Ekl5iVov^DLR}jMJ?D;)RHYlN3f-+6M-foe zlYpXL1Qhiqpr{W4MSTe<>PJ9Pe?q9}kWBvt2PFQC-4`{_3_sFukm<&N%$WHyMME-! zZ?;O&P|la4VQeWH&X%I1*-|uuEkz^QQZ$M!MWfkLG=?ojW7#MgM?ldr1QZ=hK+$*t zijE_o=y(E(P9UIY0s%!Q5>Rv!0Yyaw6ipsXjY~_ z)&YqZ+5_s@QqOVPD#6kSI^(e(rrttX)91_FvU5Kwd@0Yx_vP;@f^MYj-8bSnWxw-HcuI{`&^ z5Kwd{0Y!HaP;@r|MfVU;bT0u#8wn`7kAR|01Qcy1go-Z7^sjP2;(hJ=t}m6M=WN`c z88cs|=;6%Z(dVV;5zd#QN7+)eg)K#ov8Cv7wiG?VmZGg}DSDDEMNhG%=xH{Jo*|&< zSptflBcSMc0*YQBpy)*cie4h1=w$+mwh>VD3IRp05>WIS0Y%#hD0-cMqBjUA+Cf0k zP6CSFB%tUm0*c-ypy(X}iryuJiXP1LcR3*OCU*DpkQ6m_&x^j788cs|=%dUa@{$yN z%=uEZi!DW;u%+lzwiJEFmZHzuQuGB|ioRq^(N}CK`kIZRZwM&*mVlz~2q@Z3K+*RE z6#YOz(T@Za?IED(CjyFoCZOmS0*dw$P_&PLqF)Ip`i+31{R9;KPC(Hg1Qh*AK+ypL zivA*?=x;)(=z~oEFb5?5n|)3HLn&%zAL;*-88cs|$j=G}Zj+*D*1tc}57<(a&X%GW zTZ(G1rKl!bisEc3%3w=TCR>WK*eJ>-peR8=QIde790H1R2`H*XKv8W1is}$hRF{CF zdIS{JC!nYS0Ywc7C~8DNQDXv%nh;Rblz^gx2q?-Upr{!EMF$g5bO<3-6v^^uIw0{i z1}7~m{1~m4dtS78R?K{vq83@fg|A9cOU~DQ(GhGZYQ>hK)@&(i!7lAfTut0Y#k%DC$f=Q5OP=x)M;-jew#f2`K7LKv53@ijE?ns3!qM zy$C4kO+Zl}0*d+)P}GlrqW%OF4IrRsAOS^#2%)0Gvi$oTka$ajbGQ`kw=eJy&Wf2Y zQ#3p)*s)!Tj^=zR8o`#Lk!&d%#g?McY$+PUmZGt2DH_L?qGQ-nbSxW1;|VA_j)0=$ z2`D;&fT9Tm6rD&w(Mbdp6%kN0k$|FN0*WRPP*g%d(PRRON(m^MLO{_}0*a;)P&A!@ zq8S7folHQ{Oah8#5kf^nv;6%INPM>47Y&ml`!rE>c2>-MnWD0+pur9)D(8GDs$fge ze6|!VU`x>{Y$;mEmZC*$DO${yqEp#YbQ&8)rxQ?g1_4D&2q;=gK+%~56rDvt(J}&x zmJ?8PHUUNF5Kwe30YxhaC_0aTqVowTx`2S9l>`)BNI=m=1QcCNK+!4!idGX)bO|9; zG&jpX$^nW0W?$2vCq;+ZL+wkmV&=;ft;q_C-jt%XoG(RJvZd%MwiI2>mZEiRDY}L& zMc1;W=sLC(UC)-H^=uT~KtRz30*Y=Vpy(z7if$&L=oSKsZY7}THUf%nC!pvK0*dY= zpy)0FitZ+$=pF)!?j@jTBLPMC5m2;=fTGO=6x~li(E|h&JxB-@U7qDHcR=DV*=HTE zkfKfYk^VzjG4o}Lwqyl2y)8wLalRBi&X%Gl*iy8WEk#eVrRXWP6g|zBqG#Ar^ekJ7 zo@1lvc>;=FAfV_)0*YQDpy*`+inb9@^a=q*uM$x78UaPy2`GAB6n)E(H{g9{YgO40RoEt zBB1DR0*d}2pvcSC2j(b>5JE*CXZgwZoT3NpzG#;eeQ1xa)3Rgc%M_(&2ZbLF#$zQ2qSdDQeC6Qq+bmMQzzql+Tu;0=5(t zvZbgUTZ-DVrKkg2iaN4U)QNzi&IA;7A)u%$0Y%*iC_0jWqV5C~^&p_=C<2Ol5>V8O zfTG?66!jsXs4oFU{Rk-PPe9QC0*VF_P&9~uqQL|d4I!XtC?QnTGTUG0fW$Z2_c|US zMQ<3XVc9YBWr{{-2aoNNqEVbLMWfkLG=?ojW7$$Pjx9yUu%+l&wiJzLOVM#`DLS5w zq7w)xnm|C&i3Aj#L_kpy0YwuDC@LnPXc7TMB?J^rCZMR4fTAe`6ip?dXc_@U(+Mb= zK|s;T1Qg9AplB8WMY9PgnnOU*TtcYm=xqN}2P9s@K1LfMMZ@gT^}Otu`7%ZGvjhJ# zDO$k!QgjMiiWah^Xc1eA7PF=3RJIhI#+IVf*-~@{TZ)#jQM8nRqB997I*Wj!Wdsy0 zC!pwT0*cNdpy*rzidGO%bRGdk=MzwL0RcrT2`IXdfTD{CD7u({qE!SGttO!85(0`Y zC7|ds0*Wptgo?_u{T2>L{8YOys*s|O?a}oW*)j8Fimu8I27e(%S987;tz%2kHEb!m zmMulsv8CvGwiK;rOVJH%DcZo6q8r&Lx`}|In+Yhog@B@42`IXafTG(8D7u4yqB{vF zx{H9Ky9p?|hk&Ac2`Jh~K+$~!6m24)Xfpvt_Y+X`00Bi05>WII0YwiJQ1l2PRJ1nR zpY4Fe$Ju8cuau%&?Y`*I?3np7MNec07k?#1TRC5fo@7hWQ*0@Enk_}ou%+l(wiG?b zmZIm`QuG2_ie6-+=p_P*UM8Su8v#YH5K#0g0Y$G7P_&(ZqSpy1dV_$X9Rw8ZB%tU` z0*c-upy+J^iryih=v@Me-XoyseFBO;AfV_&0*XE&py*>lsOYh5f3pJ;&$Wj_k4w=z z_U*H~vSa4U6n&l@y!nk3eZl!s^d(!0zG6$!*K8^JhAliElDEpGi@vkqQzq^JR)^CW1!0 zr6|t%Qk21#qD;0FWwE6wn=M5NwiG4VQk27%qFlBV)ncQlHUUL-2q>ycKv6vcis}9Zo<| z3j&H-5<*3>gx|{niJxZ=g=!?ikMu7zQb#0W=F1edO$5b1NKroLOHlz^iVE3M)Q&Ah z?b%Y)fh|QH*;3SrEk&K#Qq+ZwqOJrKbt9nYNCJww6HwHHfTE)aDC$W-Q7;0DdJ|C8 zhk&BK1Qhinpr}6qMFR*Z8c0CVAOea86HqjSfTE!U6b&PwXgC2yM-xIttrPw^4oG~H zeT>#diat+$z?O)aFHECPyV6HqjVfTFns6wM=`sEmN3azdzRRKnlpfW)WS=dMRfQ8T+Qsz}7lmnmA9 z2)_SWiWYIc6fI^;(Wz`HI*lzwr?aK#47L<4VN20cwiKPomZG!RC|X89(Q*Qc&L*Jf z90H2YC7@^p0Y&E#P;@>4MHdiIw32|L3kfK?h=8Jt2`E}cK+$RfiY_6b=u!fTE+e4m zasrC3AfRXs0Yz&Gp`rx|Klc}>=r#K?{wY$lJ8M@eWA5gWVUclcHnnJ=)`mnE5hAPbGpyze&;4oG(Ssu%+l(wiG?bmZIm`QuG2_ zie6+((MxP8dYLUn+t?_2g@B@02`GAvfTHaL6unMB(HjI5?I56NCjmuo5>WIO0Yz^U zQ1lJ~Meh<&^d134?-Nk;0RcrH5>WIJ0Yx7ZP_&DHqE84Y`jikV+M4jMbwJ|X?ZdJs zrD(i;3i7i=%zT-muM)u%ze~~AoG(S+u%+l*wiJEGmZIHkDf*r*ML)2m=ts5`?O{vN zPiz$ZOhC~u1QhKhplBZfMZXeI^cw+1`w1xeoq(c02q^lKfT9Bg6#Yd&(cc6V{X;;J zm(+*tD2fnJltw_2Pe4(WfTDnaqI3d^VuVo97YYA!2PA&Jy%YOViiX;KQH^BGe3_!m zWDp#XqAbprqHMMlCD>AwWJ^&FTZ(eoQdEmAMYY*dREI4^b=fGYM?g`10*V?CP}Gos zqDBN1H71~_2?0e-2`D; zOHoI*6m?=tQD?Rkbzw_USGE*&V@uJIY!r1Tpr{7{MMn`()RTasUIY~NCZMPf0Y!ZY zDC$Q*QGWu81`tp*kbt5=1QZP>plApIMMDWF8b(0TZ~}^sCZK2p0YxJTC>liw73C-W zxeiGDNV_j8kfKj)j84YPmnk|X8Lal~0t&q7v79eOVgiaL5l~b@K+$9Zib@G6nnFO)R04{o5l}RpfT9@$6rD^!(M$r0 zW)V;{n}DJ@1Qg9BplBWeMP&pOl@m}@K|s-b0*V$8LPcYf{sRt3e5HNqY@8Hj*+=@P zBxB~w6rGw3-cFOE(>Py>PG?Ke8Eh$9!j__?Y$-aEEk$RsrDz#jik7pb=xjEM&LN=a zTmp(#5Kwd;0Y&E%P;>zSMJov?x{!dPiwG#Xn1G^H1Qe|%py(0;iY_If=rRI|E+?Sq z3IdAO5Ky$1fTAl2D7uP(qN@p^qD4vnfCCaAWuLoVEJbhGebKsP%zT-m>ytqf_t!zB z?u*uQz7*ZSmZA-8DY}s@MK`gf=w`MQ-NKflTiH@{8(WHQXQSv20*dY=py)0FitZ+$ z=pF)!?j@jTBLPMC5m2;=fTGO=6x~li(E|h&JxD;&Lj)8(OhC~i1Qb0=K+zTgiXJ1N z=y3vyo*LZPM@KfW+(D-OqJWw9Y<8domd_U#95UWKa^5qUShYik@dn(F<%T zdXX(fFR`WQWwsP;V@uI1Y$LqL(2 zqYv9r6d|A}jesJbfTAb?MF9at=>!zT2q>ySKv7KsisFP&(bq};RR<(K$Ia+BQqF#$zQ2qw_0>cp0!&TJ{_!j_`0Y$@u-mZBrsQq-L-MLpP3bQBv!Jqal4ML-(V1*1I*Tnu%h*!1oGnFXv!&=9wiKPq zmZBAG6rD#v(fI@vT|hw5N&<>5B%tUb0*WpsplB5VMXL!Yx`cqDO9?2tjDVuc2`IXP zfTA@76s;wo=t=^Lt|Fl5Y66PZ5m0mu0Y%pmLPe+L_+L68@!59wbGj70Y~#9|nE5hA z8*+kJ9Vxnz^QGt}wiMmWmZDqOQgka@if&^|(d}$0x`Qo6ce17EE;fqpCZOmZ0*dY> zplBljMfVX)$PPe9QF1Qb0;K+!`46g^Bp(IW&DJxV~)76OVMBcSMU0*am> zplB-rMNbk?^b`R_PZL5#>vR0p4oJMdefRziQuLVJ7d?{`Ghe3Yg`8k`Jt=yT^QGt| zwiLb0mZEKJDSCx1MX$1@=ry(!ZD&i->uf1{gN>pc1QhKgpy*8kiryli=xqXu-XWmq zT>^^UBcSMg0*XE$py)#aiasKs=wkwkb`enY2?0f)5>WIR0Y#q^Q1k@>MPCw7^c4X` zUlT$_&*k`K4oLhh`$+$JDf+`bFZxYR%zT-m?{k7n8%WU)oG(Q`vZZJbTZ(>SOVQ74 zDf)#iMSIy&w2v)Czp|z1H#Um)6HxR!0Y!fhQ1mAOMF$8d`ip>~zX>S%hkzn4S0A>c zC_+F{8UaN<0Yy;)iUIuO3 z1!T7rjkot`*|{7C|x@;+`$Cje{Y$%>5m0nE0YxncC~8SS(Gdg` zwIZOXH33C!2qg#AHa=sLu z#FnBWwiHcdOHnafiYBq8sDv#=li5;K%9f%jY!po;plBKaMbil=nn6I($pjS5B%o*( z0Y$S3D4Ih+(Od$G<`Ga-MnF+H0Yw!A6wN1~XaNC5rw~xIkbt5^1QabMpy*TricTYh zijL3q&v!uLN89&ZpCCo2*hB5pb7SVq6rGtH+;OlJoyGZ5w2Uo9%h^(NHd~6$VN21u zY$;m7mZJ06Qgl9BiY{QIXe9wf7ZOl(5dlRP6Hv5@fTGm|6kS3<(WL|wT}D9Bj)^ihJd1L2`IXbfTHUOC|XYl6)nm2w>u#5FWrnT zm7*VQ+>jeHUtYGC7Coe9qr)Oz;uiNMTQBjVflGYnK22F8k>x&`%S`0Ehvvz|s4UN` zowz*VdG!~^1Ra$8;5w_ z(!_7WJa2iT#|Y0`kytj$^HwHa9OHSb5{Y9x@3O?W@t(IfarN<@w=VI?1kbxZad?sE z-I$nF?0L5)HkEkZor&K|J@4K`&uN~wIdS$3&wD8G@=VX$lE|6kd0P|5&hxxy64#V_ z-V2G(=6l|@L`(NiVr);$S?qZ`6ZfCydG93tJj3%oNc29_^L8c9UFLb8Ctf+*^S(~h zTH$%S6UUwJd3zGqt@OOTi7zhly#0w*t3B^Pa^9ux?H@@#c)7a)BFVqjxLY8S?0c2F z2_nh!*16jtl6>u2cOyiSb=JFEA(A{{gS#0b$@Mq6+aZ#)f6cymBx(N~d5cKW{ypi| zk)-{Dzy*<{{fn+0B1!uvIlDxX_HQb7k0k9M#p@MG+P`YnFOsx>mTFKWY5%U!ut@To zt?o97B<)}J7#m62Kg}>clC-~De?lZ_e>wWZNYegx>&cO%{q@AtB1!xEWoJf`_7{ZC zjU?@Fc&vyd?XT!t7)jdSv36P{X@5!9(n!+&mZRm7S&zsyCN!kw#+#5;ScYJS- zB<)*vABrUHdoH&`lJ-q=TO&#PuBT@rN&B{y7a~dfzJqO%q+?v`K7H|ZBxxUi?v5nw1BgA5q&))M8%f%`@cogb-3K3t zcsZZAKQz%B!#{Gl7rPs?tNUYB>ooVo$AMQn?*14B9dlZ^R_F4#yQSN^7k9sT-#xjm zZn68wCDJk5&hqLyl3t{fM%13uS!1!ibeHU9sTaG%U1FrGp0nItTBMuCRd&vi8tZLz z*BBjfqld*4)d;ILal@ z^XqzkcDIZpGrDFBuI1hWdQJ`d?Rr+yYeh0L!WW3R8O!qg8oYc)Mpi~LRmrk$S0YcT!MwJrY^&+SzMPrk)5qFGs%< zy^`EWWNBtx0oU~K204-3^j`JX^l{IrTm6L_ zyVv72cK_L(ta~G+{%`-Y+rRp+>btJHNqldzJ0&ghXLgnsalhQl+D+KDZGKsC{*>~$ z`Q>FL`DI1rC8b4k%jQ&+mQ<8Z&MzrjG`C`og_6?A^UF%ht3A(N-o13!{JCY*XHBn| zzM$00pEhS!X@2p{(uMhLXU-`po|#`ht+=c-zpQk2X?byZerda+@{0MBr_af+m@{W) z$+Y6>v&-|RmXs6~m(9vAEGTMU)UKdiVNqd$#WpUsnLTHAX`9mGNz>aD7PM{O#-82Q zJ^NqJ%AY>FWaj+IrTMdpOQubq{r~yZC|^`w{Vg$dT7K`c$@8brp3`?uS!tWfx5dJW zvecU-e2a`Mn=`|`&CB!0%q=cEdBFVHMPuFXW$MV8^UI4y_wF>j+M^ibZov%iB&fVeaOdJbiYB8&21lzWs~b)hy{d zXV$Davt4ue05jb#I!vCsgA7tS{q~U{sP$j{3TmZCg53O|R+}LA;2`3c<^{F<26;h{ zo*(48XH^{w++&MKogl*wiJ+Ms-1Aejt$VR{K_fSt9U3%hY!_zd*+tv2QF^U^r~m0i z<)+tlr!@*{g;&Hb`M-TKFTGBX+r+)HX1dY`|Le-;Rll-!k?m41)~q1NZR*y)U-*Cc zJ9GCJwd_Uz{hMlba8S!$EA{{UzW&ec_5Z%Z*44y?f4Cgv|A!9kPp(~t`}6hRJ^8=o z&)5I?ef^hrt(EtO|J{vL?NHW05$I5LN z)N1*k{;1iz%74EjsC--V4)fpdPX3GcJrVcPZGuR%w3vGwIJ*D9q5%biJUbS4DHv2V zDSWb1hsq~A_N{!fQy0Bthc2|1?~KWo;a z@RIbh9eBmP6*^a50rv*2yyVJP(t+2}uj-BA-UNCf8QU3p`$F}`SC(WN4{%+jc-@PvP zaJkwIpzG10>Z-XLJACoV-wUb=s(ve7E3bB;1M3a#e_T=Texp<8x!X~{Bj;65_50VE z-po0(r{<;p_n%A^R$Y-kVuLPso26a>oGQVDJnhd}|J2zt?2kt3MGJHhPO7d+pUUfG ze||kZkj4oc5D5w{6JG5r&fLVVsBRW77DKvPuOjqx?ihuJ8`z&<7QJyTU zdUIFP(^;o;3x_c60=rb*7Vee`Uq?G$S(U89Dq4lrY`L31Jf%tzH*#Sgy9X75-c%xU|-j(mL-5-SXsGJ$2+QUg-RWms;%xt-Af(E7#km&^-nTU(o&e)Dx9&!ou*@wX0d}UcOLgxLdXA z4eXv8c=WiuzFoWK+2@ej7UtP!kqWxB>yX!?taN5+ad~OWyf(8+=Faa?;@)DV3){?U z-`<6aY4c}Ia>pq%=M-18ai4W=ge+X?mivlj^(aRF0Lr9+~J$Tz0(h$s3KcfW!5Z`S?z@nOomCGZs~$O4J#cgnLBSOMnXoHcshS6!;p4$EMT7eH z9+`S=)gBe{(6j0xAb(2iQDN$(@f<$2~+^zRF+r zDeHmR(d7~U!N@c23j)2nx@Q&JXMep&zI!t0(q?$u;k^eR?WO0$hS&7tHFBf1BXuJ6 z{Q8jwk%o~*k;ajxX$MEz+9$XF!>{To>izUj^=JF`>CbAve0_4ATaUj_+(h0ot#ZQJvgR$ffir|s?KeJ}MDobc4tc3<Zb=Y9jW zBkl`dcC6=a20I?2V^{Zkv)y0E6Ws5`_Ea6OcTd~COUEzW8^HE2I<|IiBimhdEOTE1 zx4lHihuj|y+t2Fwcf)XJGzyRX+!x60`J;3^|DbTM(Q&(b!`kyd)Uj^!a37-Mgu}u; zUB?^T4PY;SkB(m-5$=6DwrvycBXz9E5BHfmK2jL&=XLZtggZ;e0qzF1%O9iT$}Zu) zQpY#Ch5KV2>$@A?Uj9%WPwE-&lXbkYcepp|_-)^C|E6QXfN=NFalxQ)FVk_$kZ`}K zW7_a=Cv+S%BHZJ2yl7Oouhwzrm~elhW5Z*@eYlPj$A^2CjyE44?oB%Go)GTeb!=A@ z?w&d>EDrbCIzH~8+uP%19ivmioulKBY2iLr$5k`JeT|N9%?$TvIyRmY?v^@EniuXl zI^J3y?)!E8VSc#()Um_DaQD`6@#1iwtK(MpC2PCBujrV*B;2)h9Cl{7kJIszW#PU~ z$9K*S_ZK=gT@mh9I!-=6-1Bt2ePy^G)N#*6;r>gP1 z+Hlv=@#w3h9p7``Rbjv1uXM~?AMQ3fPT3IdavkryDcle1`138{{zu0y zw}-pGj%VB%?hAB$=I(I6u48;-xa;XSa#OfZ)bWb@!@WVr4;~EnH##2tNVxNLoVF$0 z^L4!Y@o+z?GQ|<8#l4dxwshFNM2-j-$7QyGX~iuZH_3 z9Y5M0?(cMLz9Za)I?i}A+^6Vx@7v*iOvhi}4Y&VZcFFgjdUFQMYxM~yy~lP-=gC#_w6U<;d>nq+a2!qI?ntd+>3O)Z%??N&~d-}78N@` z_$53ZwJ$sl)p7Z6;a;udOTUNvZ5@*b!res2WBv|ziH_^sdwje6+jRWYeTR$fA9ZZu zzLIOZqmHxP_q^CXRmaWln_p}{spB8+yI^d`+>fE!v6uUH7&{Kv@f`PkF}5$&ahv-F z8QbsbnCre%#`Zxvj(6WOW4lzxYu)$G*uF!@&)qlC*#1e!Biwh>*zT<3+`Mp~uHysl z`)lm^PwUv&eG854ZaNOoakw1=_pM6Wr8<`BxJ1X5I$o*c%{p$v7#(IPU9)}@oRl@_$<2tw}y{+yF>~kLY#Z&!UsD61jy35OR z!7k6-aCu|h)12d;^zJ_*;=cXPo(g~Qq~YQNtc_dKrO7WcHf>F2sb>euJ)^13nHk=JEM zY}>Q*`bOM0RE8fz)pFY|FX{fX*NJ8Kq&L@jseb*qJi89nU+#dre%tH>{o>`Sf4JAB z?VNn~>Hkh$3fgsP*DlX}fL~Bp?f;!Rb;!%>(y_h!gqr=D7+=zV*nsdm%)$$exR30( zTq_?8POYFr>e(&4y6z*wUO)T2ONUGuTCjOk$(TuFW?Y$eU}v;h$|Z1nSS1=p+oiDtK1&^bEZEq^;~-md3i&I_S19i@_YY$X02YS=h|iW8`@(qm)iT+ z^|iWIUh1HqpY%JWo@bXb=-14??NZOP%P45pacI7N7j`LjnXLxf@4&8I{?HbcmtvRM zJas8{%|`59I`+~>yV27k>0|6;=17fV_eVS}EjS})hggw|eqDznZFqh6F_`-rez4X($Dd;_HKM`9 zREnM9E-|e}u))1&Osf%Vy@-FcdjY?7t={(ZTKB5`g4$!<)4|1d zek8q%yU6rt^svCbQ9WjV8|LBq3CDxnEcBu+G@H8F&WpCxY~p5n_b;$$Hg>av7j324 z$jy#kw6$hKH#@n%#8tC_o1MLATh01zcJZS5n)Tf5>i!-W&AM(Dx~o;FUB|Y&UhTAN z+jdv1y>>0z?wWPb&b95XT1V|1+wQt`(oWiTSFW>m!nV71U9_`pyQ|k#JIl7ae%-V) z-EQZu-;vrGw%zsXt{u1Su3r!Bnzr5bJ4(BTZFl{8YR7E5>(@&=-L|`ay|n||?)vr7 zj@owDudlXm+g-nY+G%dLch|4KcEq;3egm`}gBsCjbN@wm``27*ehy9jj9$&1?mcUC zVC)w60w!c=U_Zo=5;9DuO2}|c2{~F*LPlsx$Vg2I8Ko&9qctUDjHZN))s&ENng}^Y z8zIMPBV@cbLXOi$$nn|;IYApC6SNU>qBcTK(nd&;HbN$9BcxaxA(ONbQlgEJ$=V1h z)keq^ZG=qKM#wa6giO~)$P8_SoU9!R8SH=OZvUE{O~sHM#$OP2suX^A?Io%WQ8_D&eKN7`PvA%KpP<|wGncm zHbO4aM##n52w9~a3YqO^xpyWtH@J5=(K(@zR~?P$>X^wfA(sdC!%rz8SLjp;S)(Z- zYc(b0N=*s5N>f6v)|8NSni6u2ri5IpDIwQsBIJ5)gsj&_$PL;E*`SS(8?_N~lQu$b z)<(!J+6cK-8zHx8Bjk2%gxsNxkUO;za+fwj?$$=gJ=zGlR~sQ4wGnckHbOROBV@BS zLhjcNgDeTA-`!OWWP2-e%D6GAKD1{QyU=%v=Q=`HbVZ^M#w+fp^y*#3U~Y0yvrVYe3TLr zpKJFa?hBJf$9{r48VT%2YEyp?KoHT{`U&oIwtj*;#@0`8*I?@>xNEZY6WnpOeu6uL zt)Jk|Wa}rmv)K9x?rb(c!JQ!R6WmDxKf#?t;3v3q3H$_iEdoEmU7Ns9aMvO56WnzP z`~-JB0zbiBpTJLWHz4p6+zko*1a~6>Kf&FYz)x^DA@CF2O$q!2_dx`Hf;*4EPjELQ z@Dtnz6Zi@4LkRo?cXNURk`;}nMf^t`kobCgc;ZJwMen(ftD}cTV#do9wTuMzBiSiM zM{vFrwPH(AYqk`%VM|e4wiM;FrKo@{MTKlBYR8tM_G}b&AfTut0Y#k%DC$f=Q5OP= zx)M;-jew#f2`K7LKv53@ijE?ns3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF4IrRsAOS^# z2q+p%2o)V3@!fZaxWC!P?uuGS(H0{$BoZ@Urs!z*!+7q~u_;9(IA4lJvZZJgTZ%@r zrDzOWipH{~XdGLLj$upDv1}V6ipzY=tKgFP9mVFh=8Jr1QZn$ zP&A2vq7nj%CKFIpNPaYfTG!iP|>i6KfnQr zZ+0^}T#A|)sX6XjZJaMtR2~WJuY^b`s^EMnn$MP^1#Brgg)K!3*;2HKEk%pjQgkX? zicVuo(dldyok2j+5(0{r5>Rv|0YzsKP_&GIqU8h>olQW|IRq4)OF+>I0*cNfpy+%8 ziY_3aXe9wf7ZOl(5dlRP6Hv5@fTGm|6kS3<(WQh?(Y%Pi(gBHQxsSA?Wm428^>J1t zX1+|(+DKr3rASKAm7Fg{SFxq&YPJ-uV@uIBY$>{yEk)O{rRaLL6s>1V(G6@AZ6KiN zMgod%BB1DI0*Y=Spy*Ztif$vI=yn2%?jWG(P6CSVBB1DQ0*dY-py*x#iZ&8ZbRPjl zn+Pb{OhD271Qb0$K+%H)6g@-;6);-X1+|(W0AoAN}80S z$2nh$o?uJSR<;y9$(Ew0*i!T~TZ*1xOVP7zDSD1AMbEQQ^a24zFA`An5&=ao6Hv5` zfTC9jD0-EEqSpv0+D<^x>jV_NK|s+C0*ZDLQ1m7NMQ;&M^fm!S?+{S*E&)aF5m59# z0Yx7WQ1l@oRP<=XukXG?A-=~xaNiT{{fTCXsDEf_nqWuIE{Z2s99|RQrNkGv70*d}3py+P`ivA&>$V;pIC_gjx^{5B| zMQMak(XNPpk^>T-V0S;CNYNC#WAf8t=F1et(gOP{u~Ld^aK04PWJ^(;Ekzk@DavF^ zQ5IW@ve{CUU`tVwEk!wO6y*|7REvP3+5{BUA)u%(0Y&u)D5_6DQ3C>s8WK>{h=8KT z1QazPpr|PUMF$a3lt(~OGXjbZCZOmL0*aawP;@AP`=Y}LC_0=FDhks48y%2%#C`QW znw}PZr2m}V7qv)>nJ-h+IxTp%nH06*d?{+nmZE&N6cwi}`IwH;g)&Ysf-S+QUZ#m5KuIgfTC#x6ip|fXa)gAClgRKlYpXG z1Qg9CplA*OMRN%#nnwr~jY#tg9FX`P`{Kq(Df-IZy_KcK%$F%zkQUfq>6lV<3g=7F zLbenwVoT9twiKPpmZH4EoGzVOah9|BA{p)0Y%FRC_0;fqH_o+ zI+uW=6$BKWM?lf}1QcCBK+#G9iY_Fe=pq7&E+(L86#+%72`IXRfTBwYD7uV*qRR;= zx`GfYsz~z}I3V%E?NdbarRX-hFItlpGhe3Y>a<`@3n^O1`BHQZTZ*n_OVM>~DY~95 zMeEs8bOT$8Hn64WMz$2)#75E01QgvuK+&xP6x~KZ(d`5j-9bRnodgu!ML^Nr1Qgvv zK+(Mf6m2A+=sp69HW5&?nSi4E2`GAifT9NpD0+y1qK646dW3+YM+u>#E7SZf4oG}e z#KE~riaxaaqAh7L^JR**rUmv_%BJp%p5%NfdWtPYPqU@y8MYKX%a)?&*i!U7TZ&#_ zOVNvLDSC;GqL&FM+D1UpD+Cn1N1Grxbn3`BL;1TZ+DBOVKxMDf*TzMc=WdXg6DmzGq9(4{Ry=k&U7~ z1Qh*5K+(?x6#YU#(Ov?I_7PC@D*;8n5m28(I+%c>LkK8pPC(J21QZ=c zK+)j@6ty6rs3ieKM-W0qHGKaf2P8huKI>T14?oi1VjtC$Obx0$YksWJ}RWY!np{P&AQ%qGAGyCJ|6nLO{`E0*XorD4Ie*(NqG8rV&sy zoq(bl1QeZ2K+#MBie?c|G@F2;IRq5VC7@^?0Yzm56qOTDR6z(8jrRS99h{;C_E2by z6iv2A*Yo|D`7%X|{J{Q6hLobkoG(SEvZd%WwiKPtmZCG*QnZ9EMN8RIbS7Jh&SFc^ zGB%2q6Hs(E0Y&E!P;@QI*)*&^9d-rfPkWv1QcCJK+#166kSX}(JBIpRufQk z2?0fy5>Rv*0Y#S+P;>XXgynsZeUB%2DTL4$d;m;*iv*eTZ(RBOVO=t6x~KZ(d`5j-9bRn zodgu!ML^Nr1QgvvK+(Mf6m2A+=sp69HW5&?nSi4E2`GAifT9NpD0+y1qK646dW3+Y zM+qp}LO{`D1Qb0^2ow18Yz0p#uI+be3_!B{lNZ7n3SStIA4mMWlPa> zY$%$F(p+7IlX6iO-jhV!N9TecK^$CjeqY$^JlEk!@D zrRYbt6zyS4(NAnC`k9TQUkE7LOF+>+0*Zbmpy)ROiuMyw^g97Xe-KdgCjmtV2q^lC zfTF(%DEfzhA}^{B+ffuDpeT)iBA$Q0Y&Kq6vYTAszC@9ed+t{9FTZx`*ihJ zQgo_4x~>_GnJ-h66%Fj4q)I8u=6oqiu%#%;mZBWC6y>s|s1{p_YO|%N4qJ-qvZbgV z8%6aAC~81JQ9}ZX8WB*`n1G@t1QazTpy(h1it-33YDPfO!2}c?LO@Y-0*VeLpy)6H ziVi2Bs09HlvX(I^6nMiW9s1yTQT2PD4C&1j(%ePH)RW1=zhWr~iC2KGCP zK+y~WicTh=XeI$gvj`}fO+e8c0*dAmP&AK#qA~)C$_Xf{AfRYI0YwW4C_04@DjFB{ zqy3zsukEvr$4Jqj)CX+QnE5hAr$qz%ClynQPUn0nI)g1mOW0Dhlr2SPvZd%OwiGR6 zOVM(+6rIhMqI1|NI+uW=6$BKWM?lf}1QcCBK+#G9iY_Fe=pq7&E+(L86#+%72`IXR zfTBwYD7uV*qRR;=x`KeBH3Sr`C7|d^0*bC8py+A>iq;WAMT?{U5CsbR%1eZemN(&1@;Ug)K$5vZd%YwiMmYmZCe@ zD7uq?qPqwvx|@Kadk84Hmw=*;1QgvzK+z@wiZ&BabUy(_4-ioFAOS@W5m59n0Y#4x zQ1mDPMOz3cdW?Xg#|bEUf`Fo}1Qb0<2o+ry^;bC{@h9!R=z1xdXYbLTipI>BDS9p% z*gxr-QuI9MOVJB#DSDADMK7_X=w-GPZDUK(D{Luxl`TcDv88A`8%3`ZQ1k`?MLP&6 z+DSmsn*oG(S+ zv!&<mML)Bp=ohvW?PW{RJ~oPeC7|dx0*dw%Q1m+iMSl=b^d|vD z2M8$oi-4lP2`Ku9fFdu@hwUhe5KxpxK#@;CQIvq9fPkWO0*Yb;6xAT0s3rkLaRQ1m z2%(~HqJHDyPEk|)UdL~xXoMp!2U_;l%gEYm!e#@6xCu&QEj#q)nQ9f zUA7d}V@pwewiGpBOHo5MiW(76)R=&xCIl2UC7|da0*dkoC~8JP(ZK{19YR1+a{`JE zC7|dq0*VeNpr{1_MJ)*^I)Z?rRsyz zjew%*1Qg96py*@*ie?f}G>d?u*#s2LA)sh30Y&o&C@LeMsGNYJ3IdAe6Hv5(fTB|f zC|XEB(INth78626;{*Q(2PA%>Jrp`lijJ}eNv8%e^JR*b1VQ2$DO$?;QgkL;iq2w7 z(K5CaEoV#7*=#8~hb=|tvZZJRTZ+zOqv(7BiY_3aXe9wf7ZOl(5dlRP6Hv5@fTGm| z6kS3<(WL|wT}D9Bj)^ihJd1L2`IXb5Gp!7 z@H;pl@$vRy*%?wa$?l7;4`Sxa6x|pE*Kh?y@_^kNWPeY_OC#Q9S6GFytav8Cu0wiLa}mZI0#QnZ~dMX$4^=nb|M?O>y5 zCjmuo5>WIO0Yz^UQ1lJ~Meh<&^d134?-Nk;0RcrH5>WIJ0Yx7ZP_&DHqE84Y`jmj8 z&j={`oPeS)2q^lJfTFJmDEgX!qHhSHqUQsDs{;~u{~(1IeL;#|GE(0LG4o}Leh7k3 zCP>kboG(Rt*i!TpTZ(>WOVKZEDcZ}HqJ3;B`jst3zpyaKvA54q6`9x zG6^WkBA_Un5GvXo_~|D)MfP>q==V}oVGp$v=`r(VifW|?hZjjvZO)gXI&3Mb%a)>g zY$>YGmZAo1DQd`;qDE{fYRs0RCTtWnC7|da0*dkoC~8JP(ZK{19YR1+a{`JEC7|dq z0*VeNpr{1_MJ)*^I)Z?rRsdBU( zUTi7q&6c7*Y!vk+pr{`KMg0jV8bCnNKmv*e5l}RkfTAG;6b&VyXcz%S!wD!lnt-Aa z1Qd-VplB2UMWYEQ8bd(QSOSX15m0mt0Y%3WP&A$pD(aN(U*dqoXV^Qj&Qf%feL3W~ z^qBcFMJJ{Qn@XhUB+i$jBDNGwWJ^&oTZ$&JrKp50MU&Z5RLYj3DQqd4%0|&N0*a;+ zP&9*pqLT?Inn^&>ECPyV6HqjVfTFns6wM=`sEmN3asrAf2q>CQK+ysMicTS*XdwYb ziwG!MOhD181QeY{K+)-hP|*qL{yPpxe6@Ynae@@pw)bdfq{qycDLN}X_`Ot$mT|rm zEoV#7*=#8~hb=|tvZZJRTZ+zOOVRmkDY}3yMJw4Tx{!dPiwG#Xn1G^H1Qe|%py(0; ziY_If=rRI|E+?Sq3IdAO5Ky$1fTAl2D7uP(qN@ogT1P<9H3Sr0OF+?e1QcCQK+$>v zif$l;ik7DPO{X|TPuYFZnNsAZK443anJ-gxOM1|AniSp2`BHQnTZ(RHOVJ%{DY}y_ zMR&2K=x(+Y-NTlmd)ZR7k&UAJ2q@Y_K+$FbitZ<%=m7$X9weaXAp(jXCZOmM!vDqG zeLzQ9|LfX+CX->3NtsFL)gWDj5IRWjy*FzJ5IO{sfPg3)rdTz0WzUrBCiF^CUy&lVQ>TMb8jWw4H#WX9*~J zj)0=)2`Jh@K+#SDie4a~=tTmGb`enY5&=ao6HxRD!B=!gx!?o`B(m1-e(sc_h>cgv zh0T{K+FdTRe5w?^$@x zqns~Azp|z17+Z>dV@uI-wiNx&mZB4EDf)vgMSrrT=p-9OrwAzei-4lP2`Ku9fFduf z58F``AfPCLfTAD)MTrCyg$O7rM?g`SfTAPs0|JT~5>V8LfTA-9 zC~8bV(U}AkH6fs=DFH><1QazRpeTocqUHn?wIHCVB>_dP2q~7( zhbo5skMw`CJEk__u=z4YXN5zfXG>8B&X=N&Y$@u*mZHvVDeA(OqONQy>c*C$?rbUQ z!Iq+)Y!vk(pr|(iMSTb;>PtXTKLU#S6HqjOfTDo}6b&MvXfOdqLkK7uNFA0aumnm8v4jpp;aBuuOLoVZd zDY~33MJw1+bOl?AR$>(L5=-m-D6QKDHFy&z7QXY$HIBdR5(c9rr!2&7T!}(J54qJ-eWlPaswiNASOVN95DSDqRMIW%G z=tH&?eZ)r5egcXQ1mGQMV}E+bdZ3e&j~2{f`Fn!1QdNqK+#tO6n#xV z(KiGXeM>;mcLWrDPe9QR1QZ=6py)>eihd%X=x2hj=*@8O8V4jY&>jlCB}F&bebJF{ z*nF9yW8u(a3#I5c&X=O&Y$^JkEk!5TQuGH~ivDCv(Mh%xonlMTUu-G*n~kD>2q^NB z^kF-S0t6H#5Kt5(peT`mq7VT^vcfTDB)ilPJ* z#Rw?MAfPCdfTHpQ6jdPjijIbZ`yG%-vVCLPuTqp`q$(zb&6g>vniM*Di4;}id?~8V zmZBPLDXPhqqFQVzI*lzwS!^k)&6c9m*-})8jiR~)6xAc3s6GKj4G1V|NI+2|0*cNc zpr|ncMQ0LF)P#VdrUVpa6HwHQfTA1%ikcHp)PjJbmIM^FBA}=>0Yz;HC~8YUQ9FXK zsB%&;Ymrmb+P+D)N|OJP{*(46TKlB1`7%YFl0sdVNKt3bm!d9gDeB6WqHb&{>duy; z9&9P<$(EvCY$@u^mZCmv6!j&bs2>4E{Rt=siYBt9XcAkBCbOkz3R{Y%vZZJmTZ*Q$rDz5l zMKcK~Dj=X}76C=G2`DNgps0v|qGAGy<`7Ucmw=)R2`HLJK+${xiWU%1bP)kX3kfK? zn1G^72q;=aK+$3Xik1*ibSVKvO9{TByrkfL4oKu@`~ISFQnbxTElUcUFH^K4DfH%Y zDY}C5rD!Evimqf!(JHnSUB#B7)odwR!H+ zXa@mBI|(Ryfq_A5q_FuiMeins&R!`+dpTc<_OYetJ+>6R&z7PO*i!T%TZ%qn zOVNI|6n)H=q62IceL_IdrvwyzMnKU)0*XE-py&$%iVhJ_^d$jBUlCCBH33E65K#0j z0Y%>tQ1m?kML!TwbeMpm9|iGZS?2`D;3K+!J*6dfh_iuNQ0FL6NJpJxuvJ5sdT zK9T)vQrLW%qTiE3x2%$)6Pzzaf3T(KPqq}DWJ}R0wiNxvmZHDeQuGg7io9ff+%81{ zHi{AmC<+o#lt@5Ph=8JU1Qdk{C`uxrD4Bqw2mwVY1QewbP?SbMQ91!dQ38r$1QcZu zP?SkPQF#K2DiBaqk$|E~1Qb;!_=f=&$%PO~)7Vm!#g?MlY$-aOEk$+MQdE~MMfKQHRG*Ea1_Tr}B%r7f0YzsJP}G=! zqB997YC=F!Qv!;z2`FktKv50>Ma>B)YC%9zO9F~o5m3~cfTA`86tyLws2u@C?FlG4 zi-4jI1Yc3LlsW(I5hf1`|*;gn*)<1QZP;plCP&MI#6( z8c9IWC<2N`6HqjUfTFVrC_0CLqH_r-I*)*&^9d-rfPkW00*b~GP?SgT6?IMy4sk#t zJ?*}zixheG=z3go*nF9yiOHea>!oNC=S$IKwiHcaOVL!e6is7G(R8*H&0tH>Otusi zu%&1g8%47TC@LhNsEB}~Vgich5KuIifT9ZtD4It=(R>1m77$Q$5dlRD2`IXlfTBwX zC|X27(P9FMmJm>MDFH=G2`E}dK+$pniY_DgiY6onuX8{m57}oO^QCC5eY4T!$zk(l zimpr!J#noRt>Szsx{57DtJzYthAl;F*;2HQEk#$erD#1{imqWx(Y0(8T}MFC^#l}c zAfV_50*Y=Vpy(z7iZ&8ZbTa`(n+Pbng@B@42`Ji3K+$ak6m21(=yn2%?jWG(P6CRy z5>Rv(0Y!HcP;?IgMfVbXMOP#T4>%x^o^B?tl%n4DVgG%}Ve@5*9!w7Xb-ffl#Q9S6 zFk6ZqVN21YY$;m zcLWrDPe9QR1QZ=6py)>eihd%X=w||oju24v3jsw(2`KuNfTCjr6#Yi<741z9PIf>d z?G4U8DH?5GnmwKzHeaUb&*ab*8>Q$Z=S$HkwiNxvmZHDeQuGg7irfQx{~v*qq5xZp z64+7{WJ^&Z8$}@kipmjC6egf3iGZSH0*WF86r~VQluAHR8UaP=1QbOHD2fqKltDmI zCILm|2`H*SKv6{kiYgIMRGEOHDg+c&C7`Gp!B=!5Ik?RMiR`w=MSn<9H5=6c2Ee}IiHk+AtPMLi;+ikqdVC+AC1FSZo* zW=l~YwiNYcOHn_z6!m9I(Ezp-4P;BvAU28y6HqjSfTE!U6b&PwXgC2yBM2xONkGvk z0*XcxP&9^sqO%DoI){Lwa|tLqkAR}{2`IXNfTCOiipCO9lt)0(I0A~s6HqjP;4A7D z3AT4YBK9{GC3cshyKUr0!sg2qO^Jlg-6BO(IbVvVv88A_TZ(3|rD!HwiVE0LG>a`o zv)NKq$d;laHj0V~D4Ih+(Od$GE+n969sx!32`E}XK+#166fGp6=wbqjE+L?35dlSu z2`E}ZK+&ZH6fGs7Xc+-T%LypDjDVuc2`E}YK+zQhU(uvUaIpgt>27yFlci{jJxE#^ z37aodv^o;ne1{aR;e07t%a)>bY$>{$Ek*0uQgjVlimqi#(RFMox}GgX8`vnifqWIO0Yz^UP_&1DqIU== zdY6Ery#!y;Ly=(WT~5)T2IpZZ+7SPMEfO|grs%^+sL4H2^bzMv(SEiReax1k18gb! zge^s%vZd%VwiF#?OVQ_SDf)tqqC*4}eMvykR|FJ&O+e8%1QdNsK+$&u6n#%X(GLU^ z9VVdYM*@m|BB1DJ0*a0hQ1lA{MMnuJ`jvp9V+0iaMnKVV0*Zbopy&j_SM+`)ILrZw zd}DAvkfN{blSh9Nzrxgd5N`B!sg2q zot_eUYMT_*;e08o%a)>gY$>YGmZAo1DQd`;qDE{fI)g1mjoDIkCL2Xf2q8($|0brIRQm22quP7@e_^AUDdD6ZbTRX-7NWY#v)b5@VHeaTwcS`7=2c@VF=Sxvv zwiNYaOHqHe6b)cY(LlBo4Pr~tV73$uVN20aHj0K3P&Ax?q7eiXjU=FG6aht}2`Cyv zK+)L*6rDpr(YXW^oku{?`2-YQKtNG00Yzg8D9R(CXdD4W;|VC5KtNGG0YwuDD4Im@ z74=LB)_uq+y2`#8q?Z(3>7JK3IVEhqOwsg|P|ruCXa?s?(M+}!6|kjf7F&vDv!$qz zEk#9aDJo`5(HyoE&1IwLLIR5B5l}RrfT9Hi6kS9>(Lw@>E+(Mp5(0`A5m2<4fTAS? z6kSR{(NY46mJv|2oPeUs2q?OofT9%y6kS0;(Mke}t|Xvn6~R|DH6=LJ0f}^rI5^X! zXtX^@x+*1XzD&`&l+cxrNzv7uFGcIwQgjVlimqi#(RFMox}GgX8`x5G16zu2WJ}Ra zY!q!Ipy*}-iZ&5YbPEARw-QjanSi3(2q@Y@K+)|46x~5U(VYYoZ6%=SE&__~CZOmZ z0*dY>py)mVitZ<%Xd3}V4-ioFAOS@W5qw2!Qi2aUAd&O!zG$r!?YBqQ52u99mnnKY zCG^e{QuGApOVN{TDSC=6MNhM(=oz*YZD&i-vur7Pjx9ycv!!SU8$~+_D0+c_q8AA$ z+C@OoO9T|XOhC~q1QfkWK+$Ui6unMB(HjI5?Ixh;O#+JEBB1DP0*dw!Q1lJ~Meh<& zw3mRQeFPM}M?lg01YgmkDZ%3oNaP-a^OzJZjeo$F5;k9^=;M@7<)@|S0Ow25Cu}MD zlr2S{v8CuBTZ%qsOVJl>DLTZKqA%G}^c5RLUlUOD4FN^p5>WIV0Y%>vQ1k-u8%50s zD9RzAs5t>eEeI%TNkCC60*YD_P}GKiqP7GSwIiUYJpn~$5m3~DfTE5B6m=q?s51dY zT?i=ZN|PtgV<6um@P#^*itl|)YG}?&QgkinOVM>~DY~95MH|>sbOT$8Ze&Z*O>8OJ$d;m; z*;2HLjiOr!D7uw^qRj*p-9|vs76OWHC!pvK0*dY=plB-rMRyTUbTWIL z0YyI(P;`WVqF)FoI!Zv%uLKkwBcSLv0*a0kQ1m+iMJEU-`h$R?KM5#0NkGvl0*d}3 zpy+RcujoK(u)YHlxiRG6d?H1=?7rxq)Uf$7MZvUC@7+?AnD(z9>4(@-RE{l0VYU<{ zv85=PEkzNw6s54GD3vWmX>1gw6HpW-peRN_Q3e4;nFJJ-C!nYT0Yw!FD5^w2QDp*( zst{0Am4KpZ1Qb;#pr{4`MKuX1szpH2X#^By5l~c{fTGh0D5^v76$R3Q(;bjVd;0=x zLYn_ET6y=p#JXu=^JR(}riHG0ONttCzV3_8U`tVBwiKPomZBzXDQe1=qHMMlHDgOr z4qJ+vvr*K7fTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP;?dnMI8tz>PSFQCjyE(6HwHJ zfTFGh6m=t@s5=2gJqRf3NkCCA0*ZPQP}GOuE2^IseAoerG%`31r09fwfxmBB*nF9y zfoY+=d!%R(=S$IGwiFFvOVLoa6b)lb(QvjDjbKaBNVXJ>VoT9zHj2g&P;@o{MduJu zbS?o!=MhkJJ^@7+5Kxp$K+#wNit-338b?6Ucmj$h5Kxp)K+!}3iY5_IG?{>+DFhTv zC7@^;0Y%dZD4Id=74=UGo^U`S8FpVZK#J_sM2R!g!sg2q6{dx%?vMDFH=G2`E}d zK+$pniY_Cd=yC#zRuE8h1p!4X2`IXffTC3d6kSC?(P{#U)(}v%mVlyl1QcCO@D0YwiGQ1l=HMGp~B^e_QMj}TDwC;>%}5m59v0Yy&`d_~u$1(!J>k=O0Bj@L=i zD0_7MWLnsKnWF7!p*ud1qGvf@ik@Rj(erF6+QF8hoop$3fh|QZvZZJjTZ&#{OVP`0 z6um+~(W?X$y+%OM>jV_NK|s-N0*c-wpy(|EiryxmXb%BJ?+{S*E&)Y*2`Jh}K+$^y z6unPC(FX(+eMmsjM+6k@C!pwK0*Ve0d__;E1z&eSB2U@f&ofeV$i5u%Nm|%^nWE3r zLO*;YMPG2f6dhtq(U)u~`id<@U$dp?8@3dE%a)?=*i!U8TZ(>Qqv$XJML!Zy^b-L^ zKNC=Ngn*)72q-#AK+&%R6dfa==r;n2juTMyI{`%}2q^l4fTBMMC^|_%(J2Co{vx30 zZvu+`A)v@h*9Yb(3J`onpQQz3`<OHmSA zijvt<6k$tI3R{X&*;16omZEgF6h+xm6l0?(gMgw;0*cBLP*j0{qKX6*RU)9MG66+Z z2q>ybKv6XUimDS(RD*z`ngkTpBB1Cr0*bN-D5_0B(dh&f)ghp$E&)aL2q>yg@D(Md z2S+&|k&Ol?lqGoI<%3(`U zbG8(PbLRF9M2s6HwHLfTF$x6!jyZs6WA1)F?f;(E*8!u&;oeAw};R zsR8L>^JR*Lq=%k8C`Cg#Uy6pYrD!-?ibk-dXe3*TMzN)6G+THi{M#P_%@AqDu)VT1r6CG6IU0 z6Hs&+0Y#S+P_%-8qALg}T1i0Bl>`*6BB1Ch0*Y1>P_%}CqO}ARts|i5Y66PZ6Hs&w z0Y%pmd__g+!G;bpy){gik>2%=xKtlXhV8%rUMc= zVISPzAVvLcJd++aU#95!^w64bq-Y1{OVLiY6urQfq8Hgxw2Li8FR`WQWwsQ(!j_^} z*;4cx8%3`ZQ1k`?MY{nw+JYDn}DJ{1QfkPK+(Gd6zwITXdeMZ?-5Y+J^@7^ z5K#0X0Yx7XP_&A^=GkVvLI6nc*PBK!8)gXv-O zWs1H`554!D6n(|{QuH-jioRh>(YI_V`i?C{-?OFY2euR)W=qkJY$^JQjiR3kC^|ww z(JurP9VMXXR|1NT5m59S0Y%3NDEgg%q7wuZ{Xsy{p9B=0B%tUN0Y!fiQ1mweMgI^` zD%(B0c!00}^?};2e^od?OW#hRv5LN{)uAAC{sB=Sxuv zTZ&TIQk2G)qI9+tMcGmmV@pv6TZ%H-QdFLeq6!2QRV1LO5&=b(2`H*UKv7i!imDM% zRGomL8Uz&8B%r7k0Y#?~P?SYLQEdW>PA8zK4gp1V2`H*ZKv8`HiW(45)R2IpMg(6` zI2!EYfJ82}heAnF|0DgYjMN#?u=z4YO{1Z_pQI?8^QEX6TZ(enQq-I+MJ?D;)RHYl zt=Ll3nk_|b*izJ%jiPo06tyRy=qv(?IuKCQk$|F31Qc~9pr{K0MO_If>PA3OcLIuf z5Kz>UfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo^-(V5ZUWe!N>5&Jq?6Dj)A z#^7k!e3_!*(a_c-QZ$0|rD!Buibk=eXf#`j#;~R6Y_=4g!44FN^h5>Rv<0Y%pn zP_%*IE1DY(X8!6F724O)E|j7*AvbP_hRv5Lx;YwZ@tYKF;(RH(g)K$5vZZJw2gqG2M8#7kbt6x z2q=1(fTBkTD0-BDqQ?j*dYpiwCkQBdl7OP82q=1*fTCvzDB4ay(X#|!(M{3d7zZTM z((a2kO3^6$6YaTZ*nF9y7ows0ze~}JoG(SY*i!ToTZ&$0OVKNADSDMHMX#}?=ykRf zy}_2E-E0)SNkGwC1QfkZK+zroiryih=v@Me_7YIEkAR~02q=1=fT9lwDEg3qqK^nD z+D|~y#{?7|AfV_I0*XE*py)FKiVhM`^f>`VUl4pnJEFl&4oIYfeOR_ricZ>n(V=MA ze3_zeqM_&ikfLunUy8nCOVRgiDf)peMTgl^^dnn}equ|}&ul3=!j__6*eE(mK+&%R z6dfa==r;n2juTMyI{`%}2q^l4fTBMMC^|_%(J2Co{vx30Zvu+`A)v^M>BDvu1qdig zAfPBnKv5zAMIi!;$`Mc$CisfJiUz-QKq5^H&eu}Z-|mZ&Vqx=Tic({t&?zZO<9sPf zXG>9(Ek!Z56lJibD3dKk<=IkHfh|Q9*-})AjiSl~6jdRhs44+P)d(o6PC!u&0*Y!9 zP*jV6qSFW{$|9hsHUUMa6Hru#fTFqt6xAc3s6GKj4G1V|NI+2|0*cNcpr|ncMQ0Lx zMUhzW3P|pW4+4sM5>V8O zfTG?66!jsXs4oFU{Rk-PPe9QC0*VF_P&9~uqQL|d4I!XtD8W~h9ShEKKq8;oqw8i; zw9M|9hQ-3>%M^`@h1PlY0-AY=qd8xS#;~R6Y_=4g!CGK+$XhiV6uRDk7k$n1G@=1Qg9B_=-lvf{!~Ok!<_Y*+?l$vyb#IjD^jYDY_^Y z`XE7y7IMB6UCfrEOW0Dhh%H5n*;2HGEk&2IrD!Qzik7jZXgM22ml05OIRQm02q?OO zfTEQI6kSO`(JBIpt|FjlH33Cy2q;=hK+!q^imoQ0XgvW%*AP&2EdfQ>5m0nJ0Yw`K zD7t}wq8kY)x{2T`njZ_EazG;e>~q%(q-eg~7j2A%&6g>GebHvlm!jL) zQnZCFMYpr1=nl3N-N}}st!yc}i!DWWv!&=BHj3^gpy)mVitZ<%Xd3}V4-ioFAOS@W z5m59n0Y#4xQ1mDPMUN3s^f&=UPY_V_BmqTF5m59r0Y%RcP_&(ZqGt&xdX9ji=Lsm< zLGTrAiUqqlAdxC|_j8LBb+&I4*%=F)FH`hVEHpkWMK5!{6urWhqF32c^cq`=US~_u z8*C}s&6c7!*;4ctTZ-Ohqi7ESMeh($^ezEKdkHAoM?leg1QfkbK+y*T6n#iQ(MJRn z?I)nk8COWi7iDxv!&<=TZ(>ROVLrb6#dGU zqGN0n{YF61aRQ2dC!pvA0Y!fhQ1mAOMJEX;Iz>RyUj!8WO+e8<1QdB0`mh~E0RoB= z2q+2?P?ShOQHX$|as(8G2`EY;peUJuq6ooP^ldEomID$ga5M2cDQaUM>8E6b&6g>P zW`urDk)jyqOHl?}iZaQdE_VqG|*bRVSdR1_4Di z2`H*XK+$Og6lD=mRGWaJ(+Mc5LqJho0*dMpP*k6Qq6P#MH6);@5dlSK5Kz>ZfTA-A zC~87LQBwknvI)MTw2WYdRHx`Q`>bPnhX0ZN2D>k6mJv2zrl@5`s8zZYwc>m!YR#6S zHf$+s%a)>cY$Q6w?00N2z5>PaVfTF4UCNfCrEDo$#+IVxY$>{oEk&2JrDz2kMOP3| zw32|LD+wrCML^M21Qe|%plA&NMQaHtT1P<9)dUo+C!pvW0*bCBpy)aRimoT1XafO7 zHxN*CBLPJ>5m2;|fTEiTDB48u6)nsNe(iunGVJc>Vkw$w4--)I z2mwWp5>WIQ0Y#4!Q1k==MNbk?^b`R_PZLn|3;{*k2`GA&fTHIJD0-fNq8$Vj?IfV+ z1p0LpX9Ul5KqAlBXB}^oqOo>gv@0WQzD&`p8KHrdrRX)zm!j9%QuGE}igvT5 z=uNg1y~UQIx7kv(hb=|#u%+l-Hj4HVP_&PLqW1_WdY^!z4+tpwkbt6(2q@Z5K+(qp z6dfR-=o12pJ|&>&GXjbZ5>WIx0YzUBP;`iZqAv+3`ig*}uL&snhJd1P3BID2GlGQ< zNaSt%NdFZn`qMox@w<$$`7%X6W`x#Pm7FHi}LVQ1k}@MSl`dbdrFgQv?+KML^Nt1Qh*4K#`ZJ58F``AfPCLfTAD) zMTrCyg$O7rM?g`SfTAPQdE^KMb+3+RGlqFHP|SsNkCC8 z0*X!}peT!gqS^!$olZbe9RiB#5>Ql+fTH>Y6g42As38GGjR+_@gMgyO1QeY~Kv5F{ zikcEolubZUGXjco2qm|v;RFl-h6}8F?_HaNVjSWs~DLP{JMPo9<=F1eFml?`;{~~ex>uBe5z7$=+mZDs?6pdv| zQ65{0#<8VnJX?w;u%#%UEkzUAD4Ik-(PRROrVvmxm4KpY1QbmtplAjGMKcK~Dj=X} z76C=G2`DNgps0v|qGAGy<`7Ucmw=)R2`HLJK+${xiWU%1bP)kX3kklWb25V~9gxT% zgLAGFRkOdI@8Zm``7%XIGDG*CE=8Aez7#EGOVKj66fI{<(PeBYx|}UVE7($W1zU<% zvZd%sHi}jeP;?amMXL!YT0=n5S^|pJ5m0nB0Y&QxD7uD#qH75#x{iRN>j@~@KtRzA z1Qgv!K+#PE6m2A+=wT|6;44~`8QkN5M80-2aj_KrY~!}fu=(=R zy@bR%$<^xzyy#Z66iss<&80@|pHYuRho*U6h3K_W&#MysIK%U5 zL~B>@ysYS?N}g9YdVdwqYZ(2tn&+JvZCBItnnf3#=6NlnFV*(Ew$YTjp4TBdw7%zc ziC*8(^Lj)-Im7e%MC&y1yaCZE*`7Bf`aq87jfno%!t=&N&uZ;?=S7#a^}MmsSK52t zglJkv&zl?_-r4h}M{nrrd9$LQb@#mDXuV#ZH!nJ^kLN9nKGe_i7Ds;{;CaiU9S3{f zis;gzp0_Ic+HlWX8;y?gylbK($9Ud`=uPK%-p1(X=Xu_((FVDmcYAb3p6A^aePq1n z-532M-}4@fcAo5ck4BeI^}HveZ%p^R?a_<^&)X3lJ=^nkMQ<+hyjP=#=6K%jXe0Me zV(f_)EbzR2(Z?2g-iOhXmw4WRXxAm4cQAVSQqTJ``sQ-a`!-sBh36fPp1soZjzn)+ z<$1@VU#<4M6Vb-&JnvL&_ImgB55%6h*4+Ss*k9MXTObhYexthy0ps|7hPKh zV)jpRwhhGW-&E`nh}l1i*Ci0Mf7PrDA`r8G znqf>JW`DQ-d4ZVy<>+GrG5g!CCj?^l*Aq_;#O&{vogRqUUl2Mg5VODGu{aR3zoKtm zAZCBZ+QLB0{*tW4ftdX*N6P}SXAintC=j#1XJl0%W`9w{+Ca>H(*K%3%zjjRLm*~9 zYr8QJvmchcH4w9(cDp?gvmaNwD-g4vH@PnmvmY3EFc7ov__K+L}Kw=WR0FWr0?h}q}f4+LWN$@ zn0@x^%RtONeerD|W*>hZ4#eyOh$DfRJpw!yh}j?ECjv3M4?Y#}GM2e_n#9}vce%`K zBksm*;fjM2a8GV5pXfd~3A9RIW2wAT=LK48Y;_k4w9!})bfazh()h)$bnknCc6v?& zyI6aTj`q^d(&%BMgT^p>bsaShyLak9CyjgUI(62VXxE^NKipFpfqLoXQ-bN$(??d$ za4I}6p{|#b(#a*y3s&-i>Fra_N@N!cC7i#5MDOWy_lHy+=;AS|@3np>- zl$5lT)ReaFcal{3UoMsGE>-5GMl?hID@oCdbkkmBs$OLLxuq{MO)pZHN_QuPO0P#W z&0RZt&9V3sAs^@L#% z{^S3*|JhAj_E*_`iMvsP-cWZ+Lf~Y2nip`t+-2?7Y1%ZqFfV&z(X8yE!tvRKxkcmi zb7vJ66z7jG&YzGyzHt7m;sOif^C!$H%r7eQJiENRbi3?Xg;QosDV{Pn-^-p{Fe5)Z zZ+iZ`?55KT#^+7XE}EQIn4evkKQq55uP8ged2UhhoC#A3vWp7}rjMVTH)Uo~_N4LS zbMp#kWal)?ZIRo&S@WFSoMslAxY%T7!OZ+7`FZ1}G|6e!v_%tpc2oE4e|c8+l$qnF z&zX>)JtJ@Yl5|bupcP*SSXUfci?gfSUO-kMt^NI`OZxa74GNiCz zs(YIkWe=Z~S2(TLoSC^J-0x-5km+-Za))(oJ+Re($IUc1uQ=b{TAt_M&=cp(9N(;2 z+ot1~HzMbmjl&F8sg8@4t9` z9Ps~w~kwr*MSWUKBaPquEWOSWuF>&nT^TKdoH*#CR5t@I_hw}89YggG;2%=cfCF58k<+*P4X$rW&K(2|#2@=99rI(n48G2EL#7j#$I ze>1w5;y+R5DzxEL_r{Aq)4gGJUaOK9=B^K~w7D+dqV#%nFF7NpJFm)Jah+iT$~>C- z?|KZ;BY)hSN&fG~z5U(mat}+&+yJ^BElaPOyRrR?m;7E()vWZl(yruc=Qyxl|DI>( zcI`1NexAD>^*eH2^;D04In$e7FmqB?{D1$>R8Hv?=_WSla<^Ih6~L(kjL*~F&w9qs zo@(zJ@ryRoi*QnPO}dp_CwrfaU#M&8mFvL`-$KtTk-#g@XA#NVyt2|8Kd1E8&na{ByIaUVrSyj8cF5_b z-#fQLyOQhc-oCoJrFTl)M6F7%kAL&Wf7hkAcutv{yv$AA+Fg-Shuo#*AjY0;FUTEB z-cU;1Z0^oP&uUTfCUkEIE?#=WbDMILmfVbO-P^CA1Z(MS!X3WdP3XnBb9li{p#LUx zuQvXKdrR=VlB?uimuvR;eS~{#ugi0yyFKE?Zsho%BmN&BJxk7Zw}4(^={4Xsc5fj) zujICLH-Y~eN^Q9N40oyc3y(j`-L^W*-M#CnlHZ7P=b!KHAwBmoVxj+5$?*^Rv#nG^ zPAP{Hfu#!EADiyw7fmiGEH3$z%3h5!`-T-Z(#RS??EH8y0>eWWgkvA&B?M4sGGHI-ZHCUVgB^|yrTR@Sxsh) zpEalBc=r~|pVwqYixw^vPo6VloI6gOUXWMZ#CLnUvLJaPzDt?jy>M?4;Uh+2J9lGS*hW8qK&^fK-K9S=s!gCdUx;MKC7XYw;AO4$PWmBT}%RgnG z9kfp{mH8Far!PrC`}|UwUqSb|rHnG$KGEsE#^XK*Pb~e!r|fsL+&T7%`2_p&mL1)fw(R$9$BH_-&j5P~?z6tN?dUGlP~C1XyPW$9 zRs86_E)_p^({YH7BXxA2^@~4$s*difNAbN#$7MRM)p3iC580=U-RpT)$Gz^iX8SW8 ze{;V9+X43`w_|1Zd$D639oxCrMiFY;l2oH&mXGe%G3OPy^ed_8`hrxiH?=(`n!&f z=hgT36diAKH-KIK0Uf_R!{5K@*tChi&(g8j-B5P`+q?SvAsxT(?(g4qY}U))9d(@B$KOkJ z+}_XMuj!aD(BDxV`waH?NF7%X_4iFW?i=p!&vmRe%HIui96QF}GjzQ39DhHe^Irpqjg+6)!#Sk`2KW%AJVZ#fxjE+ zIBvGT3v|4z$ls6Y_|qJJpVYDCJb!o9alrzAU#{bhh5mk1$8wAOU0%llOZf~VWq!k>v+#9e?Ot)k=6eGOUKsh{M}v0h3ox&g^n*=>+iR9 zOxob@iaHLu(ckClc+EzCZ`N_Y`^vH1KHun=wb|cIbey=w-$gp!cZa{9((&k4fB&On z+k5=oQ^!m0^Y@iH?%L+>cXW(ANsq-zjJlm@Rq;t z(DBnf{{BJ7x_kYdqvO=~{C%O04}Re9XLUUOk-vlc{bPp%{;{u)mwxK+H9Ed}(BJRr zn10CL)pZ>4mA~_Jyzv`TiFK*Kwo!Q{7(v-8z2ZzKU=AXB`{5 zFM-)^rQ=NZb$#0x>G-Jo0>AB@I{xXt(r-KLe$>v6UEG)a?Kn`!%iP!gZLimHxBDgl z+aKwe>AoAl_Gvnfao-kTJ7335?)w95->c)7?i&Sc|Dxj=?mGr-x6yG{mcK97@p1P( z1or$Fb*$mOBgb|l9h=!Po zeZkz0?)BL(JGzG*@#9!~JmR){Sl}h3yKh5L_nH>XpHZAQ&K-*j{o`bwav#zbdrj?Q zNU!O*q9U)Ug{J@dkgTcuNVw?)`$Vbx?DWI}ck%esdE>?v=Fj!YJU6c}Z|03H|m(|q?i^D<{mEXi^KW0TJ@)07-A?wa zhx@Ngw(n2zK6JM+zj&&P3+^GKXGi7s;zD`%wB7vn^6YvIasP3Sd(zw2FyPfG z6L@mmzq#D+jRIblouFS_?gF>VzTN|U0&#QpdhPY`dgr*OImbQeRX)SNoIP#7c;0OH zblI18xXjCoxaaZmE-!PAd(vy*Uf!i)d&>XC%UkMZ*_U_9y*#^KcKuS_f4sc)?rA%x znfuRv-JKKgYT5<#%bsWdZPJm;z1%V2_0whSz~%1M(>yEIDNypVt=a3fUt8UOWv^di z-_p0Az3+1Uo^($;d$Zgj{;P|7dF>hQXs_3P*%7n07rM)3xoGd_8SX!OdG>Pcbz<2) z>1}jg>e&b@ToT>oZ8pr=(^z-_Z>d2|J0kb7WC`yo_C8|{f_Po&W%5BlUs>d57sH_w<7P# z@$09YAA0fE#aVyuOQ>7We`epcc_YT#OW5cx)#rF>a7z3oY;Y^9_T>H(`wVr@?H+$^ zJ&vb#AJ@0LyX=kbxxJ6>30@GttiA47?F;&!tINh;ySwb@_+{<24?ebd?CAc(`}G-b z*Y0Llg0)BVAFRvAU-QvD-TTKcZ?Ab!|32}TY`@3B$Goxq`}gQOBz`UJHFr7QuVSC0 zb(-B#r`Lc^{dS%>JY?sIgI$uwzA>)+cr@q_qj&&K=(3h__<#o@1_U zwC0WvdW-kD`%wRVFfs6xyF*B|zh`Y-+4md=FCkEFxP9CmNSfmAdlC{thul3(LP9v# z#b70eGGSnqfp)pX&|mI3!3*tDgR72>r|=>7K9-OaN^*Y`CnSaEx%Z;P#E^Y*Eg>=d zj=Me{-)o*sQ_`_jG8DogXN7vwM-{5)>GN+_O}K$&`*M$=4OtU z*if^Uo6Wt%Mw&I+wOWb*REjOU9lG01puw!3Prv@>kG>(*L3 zX4_r4Hri3!?%K80PPgr@UOVkH+wS_c*G_f2xx0R6X{XqB*RO+i#J0PB9kr8fyX)6U zJIS`Yex0?$w%zsXqFv6myMA4@L$=-Z>!zJ(+g-oz+V1me-I}}W*F!tO?H2C(_0$g7 zcGs_$wquZ#m{>RXn!Ejz)8ri9Gbl#m6Q2)RfbAq%w;aE^jgY0<2wA3$ zkmcG4xl9`&mun+rg*HO2&_>8gZG>E@jgVE^2)RldA*;0!vPK&rYqfnLGlOaFE+aX~ z{rQww;0tMNe;%z1n;a8zZODE|BrfDSohl*MYf8ulO$oU{Q$lXkl#rV=C1j(fgxstt zA)7QMx0?u_D?Rd`;cpVA)ndP zkB3c;33)nXKR^^0@{CTEknNfh@~ozWJf|rk&udD^4owN!sVN~ZXiCV7ni8^06Cp2Y zBjjamguJ4SkXN-4@|re6Ue`v*8`=ojt&Na3wGr}`HbUOkM#vs*guJ7Tkax8avR4}+ z`?L}Ao;E_>*G9+(+6ehj8zCQQBV@m}FXYMKP~PLQ_HxX-deKniBGrri6U0DIwozO31gG67roULcZ5V$Pd~GIjoJ4 zAGHzklQu$r)<(z?ZG`-yjgX_-2>DeTA;+{4@|!k7j%y?2cWs26&_>7~+6ehm8zCpP z5pqf!A%AHj^{VOantD7Pr4=sLiVGF@t>Ct z1$4H4(zP60Kj|7~>nB~4*!oG=WVU|NHNw_Ux~8!8ldh?3{iJIeTR-WV&gLgwqXd4^ zHAdhkT{8&$q-!RDpL8ux;3r)x5co;giUfYrwGx4!bgfL_Cta%$_(|8Q1b))B8iAj5 ztxn)4U272dN!OYLe$urTfuD3ejlfU3W)b*F*V+Vr()Dx#Kj~VBz)!l?B{(2yiHQk; z;L{FBO??M zX99}45Kz>WfTC^$6m=({s0RT>Jqal4MLG6wPN#(E_#_YMRyWVw3UFOy9g+{n}DKw z2q?OjfTH^dD7v43qHP2eJwQOwg9H>kL_pEQ1Qb0&K+&TF6g@^j(c=UZJwZUxlLTMU zb%Ef!4oD=&KK!~~ibk2DrvhQ~Ws05+gzT^Gh%0)I^QGu{wiNAPOVLiY6urQfq8Hgx zw2Li8FR`WQWwsQ(!bZ`n1QfkSK+)?26um(}(QX2Y-Xx&tEdq+(CZK2!0Y&c+Q1mVV zMSBS-+DAaqdju4{Pe9QJ1QdNpK+#786zwOV=wkwk4iHfE3BgzNOdwdreaAy&pxqa3 zm!duP==#$@*nF9yF9IR^t6$=Z4spH|eaV)huh>%bHCu|lVN21sY$^JVEk)n6rRWE? z6dh)x=tlyIej=dgX99|j5K#0B0Yyg%DEgIvqGJRU{YF61aRQ2dC!pvA0Y!fhQ1mAO zMJEX;Iz>RyUj!8WO+e8<1QdA*B_HLd#=jmFAfPCL;43;92wvcTM0VQu6MZg4Z`gfN zFd=NdOi?%?WPf!~Tu~C|OHndgiXv<&N?}V;DqD)u*iw|vmZB(IiehXj%3z}?lYpY~ z1Qb;upr|4NMU@CBs!Tvp6#|N?5>Ql)fTHRI6xAT0s3rkLwFoFWjew#o0*Y!AP;@#0 zMRf=$s!KpoJp%Vd^$93yK=2iX5`wooAd!jgtM7^B68w+!U$*82 zMLqbs?arD*;8_2q@}KKv53@ih2@I)QfS*!K+!k?ipCRA zG=YGkd;*Fl5>PaWfTGC+6ip$ZXet3k(+DV*;2HCEkzfxrD!2riY{hL z(IsptTEv#3#cUKUA)x3|0*aOrP_&GIqU8h>T}D9B)I5;;-Q8&9U+MW!MPR^I27uZttB3p`fv8CuGwiLb0mZDeKQuHcYie6(&(d%p!y+J_HZUTzlB%tUm z0*c-yplA;PMeh($^ezEKdkHAoM?leg1QfkbK+y*T6n#iQ(MJRn?I)nWIj0Y%3MDEf_nqT>V< z{Z2s92?C1#AfV_^0*X!&P;`obqQ3|z`kR2Fe+VdY-+_FSyBXbA)ZN{HecNe(fT9Ef zih=|bB@$2+BKV39B?S98Ad#_lU-YFE9kEd^7&c#~C=v|WU;P`uFG}HjDN1EaQ5su{ z(%DiJWlK?vEkzk@DavF^QF*o$RbZp2A^}B}2q>ydKv5L}imDP&RE>b5>I4+kAfTuw z0Y$Y4C_0URqAUW6Y72q>ycKv6vcis}{(>Ldik@BmM1mU(`4lHeaSFI~cORIy$bX8Rtt;4qJ+vv!$p7TZ&q;rKlBKidwU! zs0~|++Onmn9UDdM2`D;?fT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(q8|<;64W=GR+wiGR9OVJXx6kW=eqNQvUEhC_4IRQnN5m0nF0Yxha zD7u1xqLl;`T}eREDguhGBA{qB0Yz&FC|XPSU)0?PbW~-d_WeCfb|#sWnS?Ga6e%Kv z&_R%1LoWh?h7dxBKoSrT1q4I^1qA6*#DandDppWH1jL47MN||~u_6MZqI~x~`}!w& zp0mz+&pGR?_gx=r;m-9>_N2^@$xMO-MN0`Nx{rXOWdsy0C!pwl0*Y1;P_&YOqE!SG zttNPiZt?qv8X&>u_O@uM6xFt$(bo6_)|XYZ-tXEUeGpN!f%BzkBU_3#v8CuiwiIn< zOVLAYDSDVKMUSwh=ux&5ZDFJ6F#?JnC!lC60Y%#gD0+f`qU{6}JxM^(4g!jH5>WIM z0Yy&}Q1lD|MY{+ndX|8q=Ljfzo`9kk2q=1yfTEWODB4Xx(H;VdUM6^o*7^O97$Ct) zR?!1eWPdn7)GPjg^<@>k>UZsr&WI>F!1+@28e57EvZd${TZ#^|rRa6G6dhqp(Hm?j zdXp_hZ?RGIHUUNN5KwfKfTDK^D0+{8qGJRUy-z^V2Lu#-NI=m?1QdNtK+z`z6dfm^ z=u-lUP7qM^839F~6HxR80YxVXDEg9sqOS-jIz{jl?eqJ8G(dv6_N$KjrKqgEE&AFY zu)eIK@BFU)(JK)}XEvpfT92aMKJ_V(Kmj7eFG$TxBb@Hw^DSgy>}fO6|lanqJ${d{^*{F zqD0P@q7Yk(!fYu@VoOmnTZ)RarKkj3ib}Gjs1#d@O0!W^hJd271QcCGKv6jYipmpE zRDpn^iUbr@BA_URfTGF-6jdRhs44+P)d(oMnt-C}1QgXEpr|GRMYRYhx`u$F+5{9` zOF&T_f~P1h%0JZr3ECgk5)~iiJ<@;9-n*_F6|lanqWV$p>NZl;fb*rOAzO+Xv8AXn zTZ)>nrKl-eikh*ds5x7Tu47A43pR>c5>RwK0Y$9{C~8eWQ5yn^+7eLIj)0=}1Qc~3 zpr|7OMV$yJ>P$dU7Xpg95>S**Kv6dWin0ukbJVD1OY|c2`GA!fTA4) z6zwFS=qUn>uf1H z!j_^p*i!T+TZ-OdOVQhGDSC%3MMv2vdY6Er_XsFDMnKW~1QdNhK+%T;6n#WM(Z>W7 zeL_IdaRQ1yC7|d80Y#q?Q1m$gMPCq5bdrFgF9|66ih!b11QdNuK+$OeioPLuiVj5i zKQuss3+yMc*Q98neWd?wRKWVOihhW4?T=24DEg7}rRXQN6#dMWqF>ljbe1hezp|z1 z99xQhV@uI_wiI1pqv#?5MZXhJbcukXKL{xLlYpYX2q?NtK+)d>6#YX$(G>!U99Iw9 zQRE|_s2Bl7egcZ32qmO!-1TWb~`XSeQq~FZmFr~Qx>&q%?KGJ-(r9S%h;QrhEjCD9XGfE>&q&-(RJ;Q{*EXb%=uC@ge^rkv8Cu{ zwiIQsrD!NyiZak1pS!^j9&PGu-0YxJSC>lvX(I^6nMiWpphJd261Qd-UplCb+ zMH2`p$|0a=A^}B{2q?-WpeT=kqI?31CKFIJg@B@42q>CLK+!Y;il!4hMFU;`&jv`) z{;2M#K~l8Y-WJ{J2COfuXr}Ah9~~c2G>h}4Xf|7l?qEyN9JUnAWlPaKwiMmTmZJG= zDY}a-MR&7Nw19x3g#;8WBB1CV0*dY>plC4xMN0@MT1r6CeFPLOBcNzG0Y&!{P_%-8 zqLl;`ts!ueA4 z23v~WWJ}RoY$tuP`veqyKtR!l1QdNlK+(qp6n#QK z(QyKbJ|&>&1OY{#5m59w0YzUBP;`=jqAv+3`ig*}Qv?)!O+e9U0*byNpy*oyioPSD z=nTPAbjbDZH9&&qhgvvMhovahen$J=4Om}R(a)~?ziPpn*6!{1! zDn>w&pMat$0*YJ$ilPZ93J_2fLqJh10YyOqisA?;iYK5bfqhoS@4msM0e+O3fxMI|_2ib}Gjs1#d@O0%V?3|orIvZd%MwiK0POHp~Y z6jflOs3HMHl?W(GA)u%-0Yy~^D5^?8Q8faJt|p+UIsrvB2q>yaKv69MimoA`s5Svb z*Ah@vhk&BG1QewbP*jhAqBH`E>Jw1ZfZ!=giuQLiK!P>w%};W)_ekIV?2M>}(E;nr zDry?-j?a{$W}GiY&Dm0P9b1Z8u%)OaTZ*n{OHnJf6t!kcQ5&`twPmBI9RWq{2`K77 zKv72miaHTc)R};yE(8>HC7>vsfTC^$6m=({s0RT>Jqal4ML(If(jatSEPBcLdsfTGC+6ip$Z=oSKsrV>yzjew%*1Qgv$K+y~Wif$u#iUvpf zKQ=&uOYK)3he**h`x))_=z#TQ72Of-{*f(3b2wj$=CY+|9$Sj;WJ}R}wiMmPmZH1a zQnY|AMGM(dw1|zOdk84Hmw=+h1QabHplB%pMfVXv!&=swiNAPOVLg?ik>2% z=xG9qo*|%U7Xd}j5>WIU0Y%RfQ1k);MK2Oi^b!F@y9p@TLqO5X1QfkOK+#?TiuMsu zw4Z>YR|zOOKtR!J1QZ=4py&|6Q}l4Of4Bh>ykKvB9+9FPI}S$&tS_tR&1iSt7%6&- z^QGu*wiLa?mZGCvpfT92aMKJ^v#S%~yB%mmcfTDN;iV_GYN+h5tL_krPfTARVr|6ex|5*bh zc+lSboRy+q{AMHv0@jyRR4U*mf$ zi7iDbY!p={pr{G~MO6tXszyN3)dUn(C!nYX0YxRfTBhO6g4Jzib@3hjSY}sRr`Ikk^%3L{?GP?sYxJU zeOX1<1>6CXq^JewOHoU<6kX4jqE>7vYR#6SHf$+s%a)>cY$PJ9Pe*%hbAfRXf z0Yw7|C>lgS(TxNY4JLSsng#qb43OaGW=1uaqSN-aXh(If(j zatSEPBcLdsfTGC+6ip$Z=oSKsrV>yzjew%*1Qgv$K+y~Wif$vI=yn2%W)e^|i{L4` zIpE)KfCO{x!?Fx1s$oC9%?<>tFRN%?z&&MtuyEvi`gd}^6wPN#(OqmQx|=OU3)oV$ zkS#@v*iv*4TZ-;wOVMIBik1*iw3L9N`v@pnMnKVW0*dY@plAgFMJov?T17z7Y66PZ z5Ky$1fTDE-6g@yd(Ru=kHV{y>k$|F21Qb0;K+$FbiXI}M=wX7VXimT%GsP&{WMQQ*0@Enk_}o zuu-&&fTCv!D0+^7qUQ-HdVzqV7YQhOiGZTr1QhKdpy*`+ie4e0XfFXp`v@r7Pe9SD z1QZ=0py)LMiVhM`bcleW!vqw)PC(HSf~ROpz~93F30AeA#2%BP40~JjMj&8)Sw-&z z+??rBbd>X@=v}rHy~mcKV{9pUpDjfnu%+ljwiJEDmZFc@QuGNMMaKy!`jmj869g1} zMnKW$1QdNiK+#D8ioPVE=qmz>P7zS_H33DZ2`Ku8fTC{+DEf|oqB8^(eNRBq4+Iqb zNI=m~1Qh*DK+!J*PtjWe|8fH)__$T{wiKyeV0~FdWnXMJ;0dBMgvWI}4|!6uo6{i!x#Y)|XY3730pIBSphG zUy8EXQZ#}sMI+f#G>R=nquEk4hAl;7*-|u)Ek)zmD4IY(Q4Rq`6A37qL_kq40Y!NP z6y+08G?{>+DFhVVLO{_}0*a;)P&A!@qFV_lnn6I(Z3GnEPC(I20*Yo4P&Au>qB{sE znnUmuWybio86d%5>{lI!Nl|f2YHm!x`m&1digDkXCq;L2z7#EBOVL8M6fI&)(LHP_ zx|c0Qi`i1Nge^r&*-~^L8%4_qC|XWH(ftGztstOiB>_dN2q;=jK+zfkiq;ZPw2pwH z2M8!yPe9QI0*W>gP_&7Fq6Y~m+Dt&vLj)8(OhC~i1Qb0=K+zV0r|8ZY|2YFBxZP*q z%$K5|y?6asOu+iGik^sZi{B+h+c{r~o@7hW4z?8SWJ}RgY$;SYKAr zdok{y1yXd3^QGv0wiJE9mZA^YQuGm9iausb(I;#vI?k4&PuWs*f{mij2q^lTfTAx5 zC^|_%(U$}ieMLagDFTYVCZOmv0Y%>sQ1mSUMc)xnbcTSU?+GaSfqNs5HS- zbRounzyJxpXm5TlN>Oh+%ESh&FRQ40tb6)iDXPHvQdE&GMU~i6l){#x%4{jB!j__{ zY$>Y7mZGcKQdFIdq8bDg)g+*(76C=q5KvT`fTC*&D5^t1QC$LxQVA%kM?g^;0Y&u* zC~81JQ9}ZX8WB*`n1G@t1QazTpr{!EMa>B)x{iRN76ebxRk8lyVx#ERXalEQtoKO& zNjqA`2COfus7$Cje@Y$@u%mZFYqDeAcW)!>5KuIffTB!-r>Iq|zn1|Le9+$fw3Z^r-n$+a8?e5tq7kv~q-9bx zlJli#6kCc$v!!SZTZ+cArDz;mipI00XaZY`a@bNdk&U8B1Qg{GP?SeNQ9c1hlL;uA zLO{_i1QbmrplBKaMbil=x|M*U83YvFMnKW+1Qg9AplB8WMY9Pgx`TkCIRq5VC7@^? z0Y!HbJVnD}{VNQRU@3d^lPyIT>_5amKQ>@}Sw#zD-RJI?qD7o9Mfb3!=w7xIEoMv6 z61EgAWlPb0Y$;mCmZIfsDY~DHq7?)btt6mm6#+%72`E}aK+#$Piq;WO^Z)@x>j@~@ zKtRz(0*W>fQ1l=HMVkpIdWe9chY2Wpgn*()2`Jh^K+$6a6g^Hr(N=<|=6qJsn!9U`FU zFabrc6Hs)7fTA}DD0-8CqPGYrdYgcvcL*ptO7IkIkM&nsWfU#6Uub+%isD=|-i-}d zUsllvv2MFHQuHC`OVLMcDf*Z#MW3*x=r~)7K4nYM3APk{#+IVb*;4cc8$~AxDEg9s zqOS-jIz>Ry*8~)uCZOmW0*byRpy)dSip~&F^gRJZKM+v#BLPJ}5m59q0Y$$MP;{1n zqF)IpI!8d!Zv+&bC!pv8!BccB)<4Ps39hsc?%$W9-S%6v7h?m~msRve*AYH{Ef8GEIzH4uO zDh9nr`aA7t9Sm4sR#E$)TXK^Wb>Ms{>d2O&PHZXa%$A}qY$@u>mZEgF6m?@uQFpc! z^lyYQ6>RJ!w4wKBA{qE!Bf;W=x=U-1ns|66xB|O9GYKe~ML^MP0*dY+plA*OMRN%#nnysUR^^UBcSLQ!Bey|=#SrG6#Z%8JS9aJA`jSt z0qe^u`Z(y;d0dJ<;e07N&X%H2*-~_ZEk&QPrRa0E6n(*#qLXYX`jRb0U$Ieiih!c8 z2`D;EK+!h@6n#rT(RTzCogtv;djg7nAfV_+0*Zbjpy+1;ihd!W=qv$6zYJdCwr8wn^HOhC~P0*Y=Tpy*}-iZTc& z8cIM>CILmm2q?-TplCP&McD)tjUb?CB*9bEAkr=@5-=S$H9wiM;CrD!5siYBq8D3>iod2A`lXG_s!wiHcaqv#d_il!1!G>w3w z=>!zrNd?u*#s2bK|s+Q0*dAmP&AK#qB{vFnomH{T?7=} zO+e8C0*V$AP_&5PDH;>!A7g+7y9N!Mu~PJmyky+C)Ing9H?9 zCZOmc0*W3cpy&|-iXJ7PXbS;Fj}cJxH~~dl2`Jh|K+zKf6m2J<=t%;Kb`Vgsli(>@ z9OvI*fCTs3+oB~>)XIKFdnztqeOX1%#<}l4Cq>V3z7##rmZBHfQuHEQie6$%(QdXB z?O{vN%WNrng)K#U*(lmaK+%2zie4q4=l}sluMtpmkbt5?1QZ=6py+i1ijELa^acS% zZxT@S76Cv{Y*g7F9Z~wC7|e60*cNNQ1lxCMdt}9 zxyf+^6=O@0pDjgEY$km{*BoyQdHkOFRF5U!1}U^u8wy%zbr-7IbVuuu%)ObTZ(G2 zrRW;A6xC)+(Y0(Ts>7C|x@;**WuvGb0Yzy96xAo7r~v^*4GAb}L_kqv0*aatP}G!w zqGkjXH7B6xIs%GX5Kz>TfTHUOC~8GOQELK<+7M9GmVlym1QfL=pr`}EQ&ctHf7k#C z?ycN(xo@^=V#g?MpY$@u) zmZH9FDeA{YQGWu8ZXlp&00Bh<2`CywK+%l^6b&YzXb1sCHxW>DGXX^z1QZP=peU1o zqG1FSWf4#`oPeTi0*XcuP&AT&qEQ4CjV7RI48c>>Io_YR&nR;3R~@@Zk^Ki}qQ=Gt ztS_r5C*DncRf;BZz7$PjOHnRcit^Y}l+Tu;$!sZ_!j__2*itl=Ek)DVD4I?{(X9j& z%^;xYHUf%nC!lC10Y$S2D4I<`(H#U7%^{#@E&)aJ2q?OffTH;X6x~HY(cJ_TEg+z1 zApu2;2q?OTfTDW|C|XSL6pfGf_cK6(_u4zu6QpRP9ZTW^)|XYZJl>uBniSp7`BJok zEk!HYQnZRKMXT9Tw1zE3YuQq?jx9wGu%&1{8$}xkDB4Is(Ix_l9weY>GXX^p5m59n z0Y#4xQ1mDPMOz3cdW?Xg#|bFfNplCY*MNbk?w1a@6odgs;ML^Nh1Qb0( z@D$w_?_Xnp1k>%`yIv+mZ`-jeK45)WMK8p=FCCJi7dc;wUSdnpZnhNdVN21=Y$ zFGUs2^P-N&2dpov=<|5jcSMT5;Cv}M$(Euo*;4csTZ&GxrRZz66rE;E(Kl=<`j#z4 z-?342hJd2)2`Ku3fTAA>DEf(jqMr#U`h|d^vji0VNQl$fT9!v ziYgOORE2<|ssvAwFTp>~010leaEc{(kI{;o=S5XZ2v}cMQOyMRp0}l_7U%1>=o+>Z z)n-f4wQMP>!PSFQCjyE(6Ff!L z6Z}sZAi-J|P7NvQZ$G_tNeEb9R#Eo^_t;S>>cRO^)RQemz1ULJn=M6s*izJ&Ek*s< zQq-RplApIMK=*pbTa`(83Ys!C7>vifTCdp6lD=m zG@O8PaYfTGz16x~5U(HsJb<`PgekAR{(2`HLRK+#WIO0Yz^UQ1lJ~ zMMnuJdY6Er_XsFDMnKW~1QdNhK+%T;6n#WM(Z>W7eL_IdaRQ1yC7|d8!Bg~Ng8zsC z5-epOqrD_Wr|h>wK1&E#UslnV3GNS{NYPiEFGZ)=QuH-jicYho=o_{aean`j@7Pjw zhAlOwB z8Le1i!1}U^q7&V;6H*l5d?|`yOHnLaih^t@iepPrJX?wq*iw|pmZA__io$FZB@s}R zOh8d_0*XoyP*jqDqEZADl_sF53;{)D2`IXXfTD5)6qP5Sr~&~+6$vP+L_kpr0Y#Mw zD5^q0QB?wpsu56hH33D{37(>;ME?y2NbnE)J$*OPd!%pfX`2UZi2>`&Dyp66-txH= zUCa4WREI4^b=gvs%9f&fY$-}(OHqBc6g6N=QA4&AHDaTvF#$zQ2qc^I% z{%k3_fh|P?*itl*Ek%RaQgkC5MS}?_8bUzPO#~F(Oh8cv0YyUzD9R+DXcz%SSp*af zC!i>sfT9ru6pbXHXcPfOqX{S)LqO430*b~FP&A%^q6q{PDxnk?8-*011Ze zW3--9)X(0#o|G7{zO16jiLU>Y6iwlLDY}I%MN`>QG>t7q)7esVD_e?Yu%+lWwiMmY zmZF(#6wM-_Xf^>wcMwoChk&BF1Qg99py*BlislngbQb|dcN0*wfPkWf1QabIpy(a~ zitZ(#XfXjrO9&`hNfC$2`GAmfTBkU zDB40m(PIP@Jx)N;RsxE)5m5950Y%#hD0-5Bq8$Vj?IfV+DFTX~CZOmU0*ZDKQ1mPT zMb8mX^gIDYFAz}lBEeI%D$zf|014h?zv{SJigwuBqL&f_)|XZEN}{{?TPfPh`BJox zEk*m;QuHcYiVm=)=ry(!9b`+WIm0Y&c-P;`udqW1|X`hb9<4+$vxh=8Jx2`Ku6fTH6B6n#oS(Fp>IJ|m#$a{`LK zAb5)QB>JB*K!Q2;-u25;)X0vLi2>`&D*8In{osrgo#uQg`i3n<-?F9XJGK;^VN22X zY$^JIEk!@FrRXQN6#dLb(JurPoh6{?R|1O85m59S0Y&EtD7rvE(M1A^ekY*l5&=bj z5K#0d0Y!fiP;{AqqQ40!`iFp`D+CldAw6tIk&l3)VgwZV2`Gvpc#6JC^#5sq1j822 zDJj}-hZ_o5Ush3U$SwDy6a_h7isIN(6wj8T1hy03?6$jB7#x>&q&t8*(#$ zmZDV7m!f)XDN18YQGK=)HDF6oL$(w(VoOnDwiGpCOHorcikcBn)SQ5#>j)@nK|oPU z0*bCDpr{oAMXd=aYC}L#TLOyO5m3~gfT9ir6m=w^s1pH2oe3!FLO@Yh0*cZJDC$N) zQFj80dJsHC*M|Ie8X&=^?PIh$QuKA?0b3|weOX0)L++zzrKlh0OHqHe6y3mG)8JLG@U011w= zU%T!jMYr4AqWn<6`m&0qhTNadNzpXUm!j!xDY}&{MKjn^bQ@cWZf8r;OtuuwVoT9% zwiMmLM$sGsislkfG>?FyI|(S7Pe9RK1Qgv(K+ysMiWU-3w1|MBdk84Hmw=+h1QabH zplB%pMfVXkc-WIKsqMPk!w3kBx>&q(IA9APtE=8|$z7!o` zOVMj=DLTlOqC;#cI?R@$*V$5Zge^sHu%+ltHj3UNpy+J^iryih=qLe2?-Ee-9sxzi z2q=1=fT9lwDEg3qqK^nD`j~*CPY5VFPC(J81QeYhpy)FKiasZx=nDdhP7+Y`B>_cW z5j;hEL;m#!NN}}%Shi1!hT1Pdo(cu5FRSR=ko(FXQuH0?OVJs&6n)Q@q952&^dnn} zequ|}&ul6Bg)K#A*;4c?8%5^`DEf_nqVoh4T_B+7A^}Ce6Hs)CfTBMLDEgCtqQ3|z zx=cXP-vku>LqO3L0*ail9=4;%M?g_A0*d?u6h#qGt2?k1kRVDM79)#*isZ`OHmSAijvt9_k}XB0 z*eEJZKv5Y2ipmmDbQJ+b zimDS(RD*z`ngkTpBB1CR0*Y!AP;@Q9Q)IqSbd3QL+#PG+#D%>_`mfkeZ*{@}>&q%i z3%lw6NKt*xm!bx2DQd`;qDE{fYRs0RCTuBc%9f&LY$*ofb*qjAX|zC zv8CunwiFF!OVJRv6y3y@qMO-Ll);vwp==ao5>PaZfTAn{iiQ(Vluba<2m*>m5>PaX zfTGa^6pbOEXe(If(jatSEPBcLdsfTGC+6ip#`iu#59 z&l(`X<@Q@={iSG(eWZU&IADEQMYo3CkBUjr49=IL+t^ZcJ6noovZZJiTZ(40rRWZ} z6wP5v(Ok9^&10kJP6CSN6Hs&)0Y!HcP_%%6qJ;z$Eh3=k9s-K)C7@_A0Yys)C|XKD z(R~CIEhC_4IRQoY6Hv5*fTEQI6s;nlXf**vYX~S>OYjs;3;Qn{Ai=KoYuD4I=yQ8p zv@RU5zO15+VYh<$=O7}tMVmNZiXLQ3(Pp+3J;auxhuKo}2wRFCWlPZ(wiG?amZHbm zDB4Ou(KZ5#o*T{*fTEoQ6g@>i(bEJJJwrgzE&__4C7|dz0*am|py&kx zie4n3=p_P*b`wyvhk&A&2`GAnfTFzwPtp3YzpVihoNRA?Hb~J!_A%PNaKQSqie3x5 zSpg|J$oW!qh%H5j*;4d6TZ)dbrRWW|6urroqPN&m^fp_H-eIHYC;>(95>WIW0Y%3M zD0-iOq7Mit`jCL4j|eFGn1G^B2q-#EK+&fJ6rCWT=raO}J}02)3j&Hx5>WId0YzUC zP;`obqOS=kI!*8ty&Cr4Wq<@r*xRB5QncCLyZ$B|u)eIK@5An6u~PH{=S$I#Y$^JQ zEk!@GrRW#76rE*D(XVVNI>(lx-`G-go{gdl1QcB)py+o3iY^gQ^alY&e-cpi7Xd|= z2`KuTfTDj0D7r#Gk&~o{?I`jQP*jY7B0m8|Q3MpZ1QbORP!u4bD29NdSOSWI1W(a- zVgK6(NHE9Ds54U3%0AMMOA1(DR#7O){UuI{!kjNfNo*-fW=m0VwiK0MOHoO-6qRC2 zQE9dmm0?R!SvHEUBA}=o0Y&8rD5^j}QAGlZDiKhWLO@Yv0*a~-P*jzGqG|*bT}?ny zbpncN5KvT;fTCIi6kS6=QEdW>t|g$T4gp1V2`EY>c#0B|{3YUzqU!cLAc;xdBmGtO zwy0iG!1}U^8Ya1o5~ZjS=SxvzwiGpCOHos{6g6W@QFFEwUB{N97HlbM$(Ew)*(hp7 zKv8P~irNrR)Rusvb_5i)C!nYU0Yx1NDC$H&QD*{*x)4y*m4Kpj0*bm3P}H4(q8XHyR+pzwBM122wQE-n;If6tKRmqCrXStzjv; zk@KZ!Fk6a-u%+lGwiMmWmZA){6b)rdQ6^i8hOwn6i;be;1QcZxP&9&oqLBm?jUu3E zGyz3p2q+p$K+!k?ipCRAG=YGk90H0a5>PaWfTCOiit-33$|s;`G66+X2q?ORfTF1c z6ip*|iUuV4HyR+pczatkP>PP)FF{UE3RquO(d|j@zGNwy$@x+=i!DX7*-~@|TZ-ne zrD!f&isrGU=uWm2&1Xx|U2GKHO+e8C0*V$AP_&4EqI(D^x|e{W#RL>BA)sg}0Y&!_ zP_&GIqU8h>-A_Q#3Id8&5>T{?fTGm|6s;kkXe|Ln>j)@%fPkX)1W(b7B>y)CNN|e1 z`MFJsj@hvxDPVnBMVph{KuIZji1VfBVYU=K!j_^(*;2HHEk%#9rRZ_C6m4Zo(Kfae zJ;6rNb^?l?B%o*q0Yy6rD0+&3qNfQcdWL|aT?7<8OF+?c1Qb0_K+y{X6un45(Mtpr z?IxgT4*^9l6HxRD0Y!TWDB4Fr(S8DoUL|;nHYNG5H9&$X_HXY$C`GT?+oA(W0qe^u zI-KNoFD*r{bG{TEVN1~)Y$?8d{QuL>JUeuYSfc0e+{gmV`D=S4mbG{V) z!j_`5Y$^JcEk)~C*?1Z!J3jiso+y)7D;9I(Euq9Ms{ zw)u&~k?*73#Q9QmGh2!>*itlqAa!)4QESHHd~5Duu(LUfTB?Z6pbdJ zXbb^GV+kl4M?led0*WROP?SSJ(L@4@CJ|7SOF&T`0Y&))6ip_eXbJ&Ew-8V?m4KpY z1Qbmtpy*Ztie?ZzMK>n<7Z@PHt@e@rU@4kuKfT?S9I(EuqS?vr)+$nT2j@%C9JUnA zWlPaKwiMmTmZJG=DY}a-MR&8MXaQS_7P3*ah=8Jd2q?OjfTG0&6fGg3Xej|j_YqLE zjDVu$1Qgv*K+y^UidGU(w2FYD)dUo+A)sh20Y&QwD0+Z^qV)t6Z6Kg%BLPL52%e&u z$^N4TNbnmoqh?9bFLpeb9I(EeM5kC()!1^?eNO06^DSE^^tuHX`oVmeGA5K@9?ivv z?2l0ohk7SCPKnU{A;&2b`ZURL%7-eKaGaFT$Wo3|E%Zbg$Eg|m?JCE)Hq@+ws1gcE>ppYBSq$PKM^sah$J1 zZ_RU@??T1za-1JSgBCc>+0ceXj&nYA`d-Jm6so<{aW01^Ei)f~U--HE%@yDa|Gm;& z1HN#(HRdYth3{Txt^;5Ao%QBQ@P$imGS`AHJb1IY8hqhR51Z@37q&mmzM3y=e;j#D zU)cUU>1%yq`vZaN`NH-mx;FHM?T_Sa>I>VSso267wm%fFwJ&Ucs#$wq*#20m&c3ky zxkBB1;WK;9b>a)#pX|}k7q&l|VW2N;|84ytzOenr(TDoN_FuOi?hD(0o_LfmZ2x`P zalWwq2SO+M!uDTy%=d-uKhZbU7qkS}ciosmVp zu>FT3miWT<|MXw(3)}xydzCM2|6kj6zOenDB{%xQ_WyQ!$QQQ%yV4e4*#7?}+k9dB zKMd^fh3((?e#RHJe`WW1U)cVg%iX@P{Y!IuePR2zo(}lJ_OGoR_J!@=J9yII>WN{JrlB+i%@`>$qxk0mD#`)^FcO$uzc%^k2Zfj%hxDzu}#H| zI>*;oBi=rziN;5MGnyvOiM-fC^JmZ3OwUO|3LW*tejyH_TH>zN-_9$N3Y>CH60!WK=j#v1(3S-1R0oj=z-SPi!7{U0k!c zF2&6|sprHvj@!twCAzpTF3x)apP7LK#~;JX$HgVY#m6-@?@3JQe|f1`^HN1FHK^%& zuOvO}p@v1?xbo&Aobu+ky@@pMf8@XRKlZ9E`m5+}Yd$=Fr?+{DV!po; z6C9uUWnR`^J9X=(=4Pgj$eWm&mz$NEn~|55oiQ;tCqFwYKYMs;R_?Tk`8hUZWe=a6 zo1ItWdG_VaOE*iMm^*s>=={-BvYpgXIpecaGsk65O|3gFCo6MYYTl^K-0alc>51*Xpm9AUj4L;w0btyF|p2s zoC(==vNMN`u9H@;Zi71Z*>%mc|K(Y!qbFpIn>;)_b$n*lsL>PtpT8M-)AEXbBu0)( zZIe5E^5_XU?Q(Ln>lAz}rsn5HJ|x~pq*rdv81pgDOYJ)`Gk0vq$rCdAnfGO6uW^&} zGWxV>+`ZBN#?>?>Ge6sYv>eB~qDM@gkX5flXjde!0ofKG)|T*}_fs zmrZfq=ql#3y|1JjXAdDa#U9K{M5cXq{m2O^_1xr&|Ic5zvYS%HO|D?xj>?g@>i_V@ zN8Xnd?_H^DPO4^3D(+oI`68F`U%IUS$p_-U`R4vlUWNPLxnlk=ygjM^y=zGC^8bZ5 zEb?~!R|Wsi-ivyv72OnLtemlxDxVzxJH}E|tLT#a)9jx>&gHWH{mAqGD}Rvx|9jby zEAW5%$M%1Ah5p|>>%aB~*;l_<1#_RFPlrw!9qV;=>@lrrz0MiKyeAtsEO@d}yMiYh zH`PlvY)Wgx$@Lm~&+E`mFOz0ocyza%oQY{p_cjAF+V$vH-@EMgoYJV^^)(?iD15#3 z3tn%#A{VJQus$a=E_kVCk+*5`guKxsCu9##F`wchudbcmuC$I^ig|)}vqQoAk!IeQ z$jdh~FP4#E&TddY!@Gnu^U64(BbU}jm)5rM63j=yyx8!`&V-REk^lS$uxW*FNL!hNt^pBw1z0W6=-Ia);tr9s$Jjr2kr%C}i!gr-^p>AYsx#N@CxVpNNcN)0oO*eg16gzob_fG z-tuu(H7b02JO+{XzVMn)D{|Erxyl=xH>A)bx0`9mvCp;_WR3+NFeR=&bBm>CH7NK{ znhyjoUI>8emaDel>TGI0emMnb3$GhKtJs?hU7R_G3pNtH521OrktfVYg69>yN#=E# zW*_MEGY^9F@|nKw3a zviZy&Ir0%tGk(2GEpmkxUVrA5>tmBOadOKn^AXFQT4#KN z1}5Z>nmm4(IgS{YlbK(~eA%L>#3_yH z1@?^H$YmDZ3A7sR$GGsmVBtN$G!J-0in&$Rn^kxXdCChu%|%dWWc=&rVD5qz-UE%W z$*_NFbr-_v*|BfIXV^6Eb{5`+EWGDfc*oJ)1qG4!XTiRa1)90jS$Kc2$lXEia~9tB zIo7kU5folV{UjJ%)TpS^@q5*C1bdD{!`QyH2;r+kDyMNFw zxZVryT^8JJEVzeQwp%}6v~YfUkmU-pZd?GwXuqvrYVEH>Zg zcYKEqzIGtdY17QSM5g^Zq2o(6Pr6O(bg$dJO_v@{bW)&utUnl&996!f=sae#d+{y~r=WW4@AG(U%Y1vT$g-DbzGPnH zm){8&S@!v%f7{89`FeZgy|f?eWcxL~fB#xxwS1@AaHr3|{DCv)*l#ctv)`t(NAoQ@ z`+nPFNgd5svYle)tJjt7(Y#Pib$fl;mowjKiyY1O*CNNZI`-1BzmDdsmyzd>(b0St zEV5_nI9JCdI&Ri+r+I(u>)E5@G4rn3{e_Mf%sXJW&wR-3v9x(#?6Inj&CJ_wcLyB@ zo2Ts_spCfTp|tx69ltRj0K0$F@mh1m+ucmZT=VTpyJzb7y!pnZ-LL8R&sE-zE9V{C zn{Q^?=l9leK_zdm)bXhKz}n}3rempU-ma?Skm}wZt>c5{3a~H#q>kTRvYUFSCoDE**dneuY8`KG z-ggkZ~viV{S0rn(s630x992jvVm?t9&hLv zHNx9TI(8l9?EyM28RP8-bo_9fw@>LoJ+r@S4Hrv~Sbi8klw>Rkc@jP#z*0JJU-mb0V@CDwUq~qg@ zy#1VxXYcj)-#Rv4>g{$q&RFK{yLH@uzqjAfF=mywOX}ETjkgEuxO|i?Z(q@|>Eqt+pyTb^yuDDz1KYj*u8zT--Y%_U zucy6zla4EPd3&>tC!X{686B&<=-qk@pf4q`@HGx3>{a!?d^wk{QRi5f6%eoF>j~oIOYRy-=gD=kG#D{ z$BUnM+kf0Uwm9J(yXbhw=iXkdj$fO<@L>0^I$mS`=7Zf$bex#t?b~#G*8E)v`}|jREN}j1k=?a)tY?p|<6NiR zS;zi54%0D5#~C`_t>X$EH|w}V$2~e8(J|WI|A;Z)__s&%`s^=zG;wlFCKY1bJ(!l>?ux>=Vs<+P8gYOE~M~;|5(P^Z>;Mg%v<5q%`)Ew&Ng2+ zFLKt1+|2Rjh1&G#UN%7$@%7D|Es^u-5ev+yB}%KF?S>W<(K&|MSfK_|FtjY z_vU|iIr}{OtA_b)KJ5R;m%G-y%)h^0d*7E|_Ik3v+MC~8w%z&WWj;37F~4}KwF%}f zqhpWuS5zCHQ^thi=4pHN+sm_WS1kaIc68VycXv2?2FmAFW&s-@|KyW?K$<#Z~N!uW zwemS#^)mLr%Wc)uJgb{|xuUl0>$SfgHNT6#eeH|9zxLz9+xNVA+Sr?D4v}B8%;hy_ zn4^8Y_Ln^tVdU&KFPCDX{d1mVe%s5lmup`qmd%sSiPk>nYWswKae4NfqA%CaynTmx zA#>#AiacC1U%SdlHD51p+_YZ(ru7@7m`C09(u(}IapQ(5Db1QTu3s<3{u&yb*`ZrU z@9zeA7wj{S(zsk(`rQ^;uJ`e)>6A6MR+o0U9T#?6)MZinJzekVylL1yU9SB8&y|`T z?SH#pJlZa6Sk{7M7Ep|__`>C!99K6kw-;gnm`bGvrVvM;gDY=6qs^a*;tz4Xo(q35qLrS-*P&V=+#U4ngmQ7L27Z_-QH*J&?dP~;Nq>$8_IJiWi3Z(pOmgrVuZ zbqV%$4y=4rdiQSoFGVHozjU(R`1f)i(SwRPzmC4MPkP@jeY^IHJim+i*fr{sW!``L z_V+yhcHjDux6Z!pt}a#BqpU&x-atayzZnEE@hO@cWMs& zb!h3({`WHHpWfW=-MO8Pe&@`JSyIf|x7V3zN+i$E~_KgoV|97?mkskr7!Mw@KRLegO?5zIC13UzVu~XmvvcQ;KZny()L`{ z`j1y#(s_0lqhsiSO9z}PLr)Eh8@0w~CG73h`dpQ&)4LwdOdr~J)L`fG2k%{S(&lxW z(xd87`&5?wZ<2lLz?ovj^G0Qum-z6KQ`!7ZyRFNCGf`Dp(>otH6J2$>`IBegX7ieF zv9Eb+)mu7ebvbzH=tT4OI`xPCW?u99BCmOfUh_cjHAi04fF1|V#1t=ly+QMO2Nij} z!_DiBFL=F~=Jh64%`|@=i@x41RR?wM@NciT=zDzqzrM$j*W1jz-f)rEoBVI@Z&&kr zOBB4`PUiKNs`~%2b)WH3mHXSbA(P1@LkmqnKq-m}q6mrzDoqp!h>9Q<6s(A-VDD1w z4LhjVd+!Y!*u@6+E{ci;8zN%A*OmDlKDwX(i@iUdUs%i}IkIL}5{7MRw)xNP-rTXz z;C24zcK`kMw);Qc-qzXew*1%auKqu7Z@27r+x&C8U9;O=qhr^auK&5+&K=thuKJ(b z{rB5jR(rbx7T0+qeZCB7^jpQvm4ll1duGyVe@%O5!#BTf)A`%BC;oKn+T$0UxoY=o zPO4v7_qMGMF7NWn?Q`$A;+^l;Y4h~!Pn^1VKss;VGWVP5!{>~uzgmm=M}E7_Fa5IK zZ?{d$9-4H^u@AQHvFX4cn!W$ijGKQP{_b(}+HCgXwe#0p^wv3N-aog|Q~Uoq{`|Y{ zd#eAH_s#l8TJ8J&_U!F%_pi6V!~eYBZ^+*Mwf=egug%{6P93kUx%NMAf0vF|4ZiGu z-u{2T-!J?>-tRNB+gdd=O~d#-=?pz^dB+_q+g;ePYH0m& zgZF!J&!!XRl-`D&`mL;7ZQ#m|b=r1pJFM=Ix5xL2&!e>usMr3EJ}bBC^iYe%?|-@Q zzVx|p=)@`G9)GrS=9z5|dG3}@^}lM9duz{Uo_p$;B_ECYam=&5_H8-5?k3H5ed(89 zcRH}gg1c^f@8zmG{q~vN@xg{O2i?>A>A$L5Zq>7IdhA*_IQ!q2?0=7Dk7ISto%ZCa zW#h8v2K}nXy`G&z<72&Jx>wa5&l>vD_{wqV9$ymg_4M94b#V4x&mNW2+dnjWel(-@ zkv6^U(`u&v^SG2fI~jjM&2jOloZh$T{eD#K?@fLb*z;evx@yPlcQ#J9HFoeD<4gB6 z-FmvcG5_3p|K;a39re$xk62NARP~4z=ZqXNABMQCHwE5Jy+^JeZ-0ZD*tAhCjZk?KX@h7GGU*2x5nnFBR+c`Z~YnR?5-;FFAa&GoM z+dTYM-V@J{j;k|uUfViT^Un_IcEW)(j-5H{$+w?9@YUW6|0p?}QaJ6fu~okxJ!hXq z^XDD<@Jj~_S-xK1i`QLu@iE)3ckz)E=PaCEXX+KN-r2p!d*6TG=etSA^sX8+Xs3yynz?yt0qhsLRS~KVCa!AFtJxj-ORCYv}AD zvj>0i-;dVzOZML*`)C!W)nvBM9-5x{r}t3J^7kNyYzW-(y$YUWS>WqOP@>2w)_8mK8?;k)0?N?+qC1+!wwtz%J})KmTfmb`>gxV zXV-Sw^ZS95hWvl}()0ZZwYQo+ik0mTsM#kzpVB={hR4^6PWQ0?%B!1>{pTJI&dy`I z{Bs@~vb-`k`d`{N*}7frJ#W@=^sw#HJ~%-X}@cu$n=&e`d*4 zopD2I`v1q&CR_Kb{d1di>^H3U|MBNuUOJ2HklwEDgBN6f?!ekBrSy5X!O(%(t)z27 z`WSW@mRw$%KIcaH7`Ct2pl0d#4Tf$wWW)dCW4LQsw@l)8gVw9*JhbzWF4=R{W!t4^ zZd2D9v7%-5HY?lqU#+Io(5F@{YnT3iald!QXa8OO-uP9IWuKG#bjUt~Iu7ah&rwU3 zrrNHi{m}M9I{Z`LsjX|)tU0vZkaqvnmzSpJK7$+F_Gi5X?cVr)muK!@eBQ&`SJpXg z+PucuIW|5QCQR-;W48tm^?bJ1%TxE7-s=4UgXd1HKJ$)EH*2=fs`p-Pa7^|EhF*2r zjjQwKlN&6);D^cce*g8(<@o#=kCTJowZX|K9ZUi^ts9xYevFw|+Qw z+x0&^?7imw()}#2$q&sBsrcs}owT&h6TkGVH*CAR+IKFD`KwLY-0feuxNF_o>-p@e zzV6uUg1-K^>^k|pe_#D)pHO9WD;B5k9oDUUC;R$ISy{eE_T`VVvcj?~=2puNC>!2# zc=~YP&4UE|)n;X|D?-H|hHaDqLzJAQrv)MEIhX-P|%I2nZ$~TDFGMl~X zly4ZbMK(9fUb`^nYT4WdcPvZ5q2#+S$G96}w^D+1=YLc7wFD``0^m{cLy7?q8qS_0rDn-{!H4X=nFu zi`Z3ZXZLT**p+E#_pfj4LfYB=>leEs?d<;bkDX6DyMF^>m#3ZGzk#u{pA8t$J-dHf z#V*TskL>;pid{GD?EY;XJ7Z8;UcOfDh3w;B^;ZU@eC^uTm8hDU$td5ZkiPzvgw*8I zU%agqGAs@aA;V*akZogzkP$IM$aXP9$o4Tq$PO_>$jF!>WXG5xWK>K-M#m;(r`Uvy ziA~7Pu?g8FHX*ylCS>rzuiLnVeAa+T}klZ)f$G>VxcA_aCS`zYdc7`gSR7i4?kjeSB7$RRO9$e}Sq$YC)<$l)n#NOF>px%u>B4z)rai9<1s_X6EQ=`yqF-Xu?blen~>LH6Y_d&Lf(i?$eXbVc`G&{Z^tI&o!ErD z8=H{#VwZ$Gl-oZ0_*ZR_J<%HkRM_b z@?&g5md7UKr`Uw7h)u}Pu?bljn~+~(6S68cA-~2Zf733c-5h5!K)567QE_E z6TzzvH5I(-P&2`+4mB6N>d30c-5hnf>#}CC3w}L)djCQ)LQVWLu~}FI@DJ1 zszYlCUUg_q!K)6n6TIqBd%>#?br8JjP)EV54y`3*KpK>nm(|V9&43ger&CL=Zb{Kj z>Dlbsbqk4CQnX&(e0mw7T1A~5ABwuzp=fN_EK+%>0MSTT|`Uw>E7bqGaP&81W zXe)uDK>|fv3lwc5P&8PeXoyf!v`+RH4Vq+%3h7j|ZYWwmks4aJkbEUY+t$su&wjL{ zR?!H@hobH5P_(@rigvI=(MUTK?P!OhQFbUAZHJ`*kurf6q@qFn@vb`>bvO`vG3 zK+*03MSBPojT0yuFHp3nK+#?TMSBYr?ITdMuRzg$0!0%9iuM;MnkZ0ofI!hCfuaKi ziVhM=iiXwAZJhxr-j~ht;i2g2bS^qL`zr^TucYYEy7}}nX0?hAb9^W|+zv%Y*rDi1 zI}{ydhoYnHP;`tPijK8I(Q$StI^L$}1c9Ox1&XE$6ipK-nl4Z@L!js+fufTIicS$I zI#r&^jW$`-*29g429 zL($cCD7wa`=vslI>ja9f7bv`?Tq9g3c_DSBR@=mmkI z1p-Ac3KYF0Q1r4u(JKN)uL=|`6ewCGQ1qHW(dz<5ZwM5`k zoK2l(r0CPS`SdcJwThNFJ`{as zhoaBzQ1pczik8};=u0~kePxHDukBFujU9@X*%W;%Q1qQZ(f0yHKL`~4C{VOqpy(%o zq7?!~KMNGC6e#*dplFpq(XRqUzX=rmE>QG`K+&H9MSlqt{Vh;br|h4r{Q9-ukE$zB zR3?-ZEv}o}Jp)p#OsAhuLQ#`+V#<{jlCPwwP?k?G<65hz(($3F$__=U7)D7Kv5fk zqP7A>YX}srDNxi-ps2k-Q3rvdjsit%2^6g@I2UyiC|XA-Dax1SuFHTFA4p$NtSBp8 z=?_fjqIJs($yZXeepx=f3~;TYu8t2y8`z;}Lpv08vqRBFb|~s@hoT;KDB9Q#MVr{6 zsHaWQrUFI11d28jDC#Xx)JLFbbAh5Q1d6s4DC#Rv)K8$Ozd+Fdfuex|MOz6J4H78Y zTA*kffug|zMMDINh6)tb2owzyN{Tv{<-X2<6t78F`dvcNxa`}W<-^Mg$yZXeeOW%e zjC8G{9ULEuM%tlhM>`aavP02mI~46?hoUidDB9T$MZ4IcXjhw}-2{rp3KZ=wP_&0Y z(Kvyk@d8DA3KZ=nP_(x|(LMr2`wA58Cr~s&plE-AqKN`U2M82R5-2)Qpy(ihqJssB zCJPiz5lV_il;yf*K#JF=bJ2F8=z{d{c1T$v`AUk8D9fjpA+J?*q~k-;QFbUg+73m> z*rDiHI}{yfhoa-{P;`PFicYjc(NvqFX#z#l1&U?}6rChcbh1FvDFQ{O3KX3tP;|OL z(HR0oX9^UZB~Wy>K+!n@MKcA8&J`#+PoU_0fuaipiY^o=x=5htVxgqyu(I3{8IaPqB{kO?h+`vTcGG3fuef_ zitZCAx?iB^0fC|i1&SULD0*0+Xs$rfBSJ~hC1trsGa$up>t=8+4MnG?bJ3$^h2$$K znpc)j{|rLyxoE!QL(!9VD0<2cMNiwI=ovc{J!^-e=j>4Qyd8>OutU)To1zy5ie3^Z zdRd_86@j8x1&S656fF`cdQG6{b%CNc1d84iD0)kv=xu?bcLa*w6)1X7py+*pq7MX$ zJ`^bWNTBFrfuhAiNzvnFxw0;qqKfP>7%`aC|6Q zYKNjP?NIcU9g4oTL(w;OC|YKRqHpa`^qn1wzPBm*L7?bIfuiLCML!7?tq>^sS)gd8 zK+!J(MXLmgeibPCO`zy^fucVIivAQR`b(hbZ-JuhCy+18K8)FS)U(q-`mxix0!3v4 zMLB_@a)F|}P*Sv{EH^jY>Ju-6s;yu)Iy-Br9e?Dfuhv~idqX4wGk+4 zD^RqCK+&24MePKN+6xqQ5Gd*>P_&jn(b@tSc$b&1{N#3l#McDB4`0XbXX&Ed`4D3KaDdDC#dzG(ezepg_@90!4!ainbOg z+D4#gut3oefuf-TMKuCN!vu zMWE;qfuchNiVhP>igw85R^K>NG&DUG8X1bJ6RE>c?tR0Gu zvqRDGb|^Z*4n-&0p=hcdil*72Xu2JWX4n*+Bv5p+K+!1zMW+fBohDFpx`-*Q9g1$S zL(z?PD7wj}=w^YUTLg-36)3t*py+miqB{hN?i47xOQ7g(fuef^itZICx=*0!eu1I~ z1d1LMD0)bs=wX4PxdKIx2oyakQ1qBU(c?l%(VSfFh73q?-=ygBP;^ilPvi>8S5ov; zE}#Ax!`er*ryU=Pp0PvGvvw$Y&JIP-+o9+MI}|OjL(z+ND0;~bMK9YFy&_QbszA{~ zfucnMMXw1Iy)IDnhCtDq0!42L6um7_^o~H$y8=b;2^76AQ1pR7(T4&>9|;tFEKsyq zpy(5UqE7{imIx(9^K-dn8Ia=N=?V3dq3E=9F8VB2NWPMyFLU|y&tTRn`pWU4=xaL^ zePf5BWp*g~)(%DA*`errI~4t3hoT?tP_*2p=qG`q6#_*+3lyysDEdX9Xq7FEje(opnHy6mqiFCC~9F-)KZ|Rl|a$z0!6I_irNSiwG}8@L!f9)fueQ-MePNOItUbX6ewCt zplEG@qD}%u>j)IBD^RqaKv8FbqAmhO>kAZh6-tWgmFJGifE1re=c4-Mr7Qiv(w87N zC@&;mNm2Lm{3ZQEQ4hz5qK)lPw22*xdfK6AQ#%y(vP02kb|~s?hoU}qDB9enXbXX& zEd`4D3KaDdDC#dzG(ezepg_@90!4!ainbOg+D4#gut3oefuf-TMKuCN!vu;bfO)KrrM!snjMO! z+o5QN9g0q}L($20C_2Ta=v0BC(*%l67brSIpy*72qO$~w&K4*-N1$k?K+(AZMdt|= zoi9*yfk4rP0!0@I6kRM(G)tgpwm{J(0!5b!6kR4zG)E{YI;K1~Gy_tsNk86rY$zI% z{e{=^%gYPNS5kC!c|QF!^0kVtaeOGc)(%D2*`erqI~3huhoT$pP;`?Wif*<;(Jgi; zy49xWHi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>py)nB~bLXK+!t_Mehm}y(dugzCh6j0!1GR6n!L6^szwEVu7Mh1d2WtC|V*=^qD}> z=K@7v2qi^Nm*?KffD{*{2eD^D(QoNWe`$Fk`AUkuDbN2hEEFwsd?@CwKiQ#Zg&m51wkcXEQ1pvH(JFzWUj>SO6Day!py&^QqCW+S{t_tq zTcD^;J}%oSsw+@bCQy_UC@L2y$_o@#2ox0riYf()ssxIP0!8(NlA^E5b8UuaiWa0t zw6829HMK)gGdmPDw?oltb|`9LhoY8tC~9Sg zqSbARS_>4l5h!XaP_%|X(V7B9?F5S23lwz_DC#Isw3a~8+5$zL1d7%XC|XybXgz_V z&H_bU1d7%dDC#Ouw1Gg;h5|+1gp#6$`P`lvkm9-N=dK&&OIP|wr4!Re`9kuQ6m62v z&)7Z`^>lnF+SCq3z3fo5nH`FH+o7nB9f~%$L(vv?DB98vMSX3G`Uw>E7bqGaP&81W zXe)uDK>|fv3lwc5P&8PeXox`3P=TTvfudmoMZ*P(wiPHEAyBlPK+*OBMLP%-jT9)_ zQJ`p)P*T(*pSvjoQk+nk!Pz(z{glS&d?EQtigwB8UlN(Z>Qsiv@~45h(gpplFFe(Psihp9>UyAyBkbpy*41qOXLKqUZ9tc^Qym_7C&b zDSti`9h6Q?U*`+SS5ov{KL5#Xq3C`=7Irs!9JqTd9HeitbEL!jtSfug?zivAWTs#6h{?G)7&C@K>u$_W&e3l!xAiYf$( z3Iauy0!38HDtb--e>~(zEME6@}z0DQa4g zUuTa{)XedrsJR`ARj~$9O zw?okub|~7?4n=+KP}I*3Mg8qiG{B~4pg_@90!4!ainbOg+D4#gut3oefuf-TMKuCN z!vu#~2^5VHN{V_`pr1qhT}ugNp>hY*$zdg*rDiDI~1K}hoaN%P;`bJiq5n{(OEV{XA2aaBTzI`py*tI zqVoib&KD@UK%nSCfuf59iY^u?nk7&)TcGF?fuc(ViY^lZtYd?5r1H|$XK zrX7mjvMG97py(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFZ7u|Ux$0!5z+6fF@b`b?nc zbAh5S1d5gl6n!aB^p!x-*8)Y~2ox<7N{SX#9spmf>)ZABsZN{W80 z$iFx#6fJjrDEi3`MJw!3^s^m`R@$NH7dsTKvP03Yb}0JI4n@D)6#XGk^rt}4Ujjvc z3l!BU#AQ20bp?vb1d4J3MdboTd4Zw|fue#yQKdjpl|WHZps1ceQGJ1;1_DJ51&SI8 z6jcipH5N*WzOTsrkO3(+Navy-LQ!>kL~BwgBwtC4}qeM1&THiDC#Mc6g4a4dS*b1=NB_L z%?qU~{ZrD3Y12X>`AUlV6!JSw2}PSbJ``kYDG+Ll&CxN0d0!2Fu6zw8Vw5w23v{@l{Tn420Q8vqahoXvfF50b7NWPMyafSTl zhlZl@jt@n9+M#GKI~470hoXJ#P_(ZdiuSWZ(F8jb?Qe&oi8e(C2oy~cC^}G}=pccj zg9VBv3lvQeC^|%-=um;8!vu;B7brSHpy)_}qN4LuZK+%-~MOO(FT`f>_jX=@00!7ye6kRWr6wN5)Dv!t%U7gMH zlR{Cq^oVvtp^$tfMYk04>m3z}ZgqSpy3Gznx7(rU4m%XxX@{b_>`-*K9g6O;L(#o< zD7w$4=zf8s2Ly^96exN~py*+NqPYS^j|db!Dp2&8K+)p@MNbG6%@Zh^FHrQPK+#hI zMNbP9JtI)`tU%Fo0!7aY6ulr&v_L2+x~Y)cHUm=ZnakkZ9Exs8=b{%2h2$$KdbN;0 z_?S?%(D9*YksXR&vqRDAb|`wo4n=R;q3A6;6uoVSqIc|2^sY_Odjdu83lx1IQ1qcd z(MJMB9}5&M7AX2epy*S9q9p=Fp9vIwE>QG^K+#fxqAvxCz7i<Xgn!KNJedS5ma1kiY-9Q1r9oL(xh*6#Zg{qE&V% z`qd6azuBSacRLjQVTYnW?NIcWP0`;1MRh9UvYn#30!3v4MLB_@a)F|}Kv9K2Q9+=n zQlO|xpr|NNR8OF&zCcj}fue>2MU4cCss)M~3ludGC~7KD)J!NTT3*P#mjNlhl&L0!2dwifROkh6xl6 z7bx0RplF0Z(RKnw+Y1!!AW$??plC;dqEP}xqXmj~5-1uYP_(l^(Jlf-y9yNTCQvk1 zplElYq-gWX+`bu*;u#6f7NO|7bS~PXvXFcwMSE4|Pn{8p_I7+I+Q$w>``V#sKRXmn zutU-Qb|{)?hoS@QP&CO7MF-jx9VAe6ut3pdfubn_MTZC!9V$?Cm_X6t0!2p%6dfs0 zbd*5R(E>%s2oxPFP;{I?(eVOBCkPasC{Q$2plF&v(R6{L8A3_X_{!XE8IaLuZK+%-~MOO(FT`f>_ zjX=@00!7ye6kRV+bb~X7iq1)-ZmujOUrEvJmHDQp zg`ztgAByg@L(yG!D7xDYMfcdD=w3S%-DiiQ`|VKlfE|h+v?+Q>py*+NqPYS^j|db! zDp2&8K+)p@MNbG6%@Zh^FHrQPK+#hIMNbP9JtI)`tU%Fo0!7aY6ulr&v_PQfMS-H1 z1d3i3N{Vi+%=OBE6t~T0`E8--p!A6LN@XGWN{U{q%JQnau#cR~gv`z~4r zXHh6xCq32vsj`rKB}Knf=C3>}6s>Z6DEie7MZejh=yy95{b7fqKkZQTmmP}!wnI^! zs<>_sMRje8$^?pX0!8HlMR|du3W1`6KvAVYQI$YZQJ|=vKv8{xq6Pv*4F!rC2^3We z6g3toY9dh7RG_GtKv8pnqSXY7S_maYKUe0S&VUr(Pp6-ip=j?kT2>X3ucW9=RsQpH zLQz}ChoUv?P_(8UirU$ssJ$JEI@qD8qaBLYvP03@b|~s(Q?!mi(YgXf>j@Nf7AWc> zP_({4QCESY4Frld6e#K@P_&UiQFno&9s)%h3lwc4P}EbPXj6frUIIm%2^94fDC#3n zw7F1Hw0c#pI5Si9WJLz2byev~e`Ok5R27o1q^N&YzRP)`Xn^BG(Lg&CZDog|L3SwG z+73nA*r8~!9g2q7p=hWbifU|%h6xl67bx0RplF0Z(RKnw+Y1!!AW$??plC;dqEP}x zqXmj~5-1uYP_(l^(Jlf-y9yNTCQvk1plEl2qCEtP#t9US7fOoyR^_(KfE1rfr=NbI z==jhY&<;fh*`erQI}}Z} zDVicsbcjIFp#nvR2^1YJP;`Vq(UAg0M+p=iEl_lfK+&-RMaKyg9WPLHf}gW@sa1vKD=9j&D*xa` zq3A5fhoZCXP;`zRie}oO=v+G#oo9!l^X*V{fgOr2v_sKFHboZ;6wMMSnk`Uti9pe% z0!5bz6wMJRx?G^>3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^ zfudW5lA_bAavx+sii5IQenu!7Q8yd6RTYx2r0A}y{GYQz(cO*@MfcdD=w3S%-DiiQ z`|VKlfE|h+v_sKDb|`w-4n=cqiXIUtdQ_n3F@d7T1&W>!D4HiwG+&_TNr9rL1d5&( zD0)Vq=vjfH=LCwL7bto`plE?W(Tf5_F9{UAEKu}{K+&rLMGJ+JqC2W`9cE{WUQ1tS zyfYLHP1k6PstUB#GJ&FR1&Y2C zDEeNY=m&wK9|ek*3l#k%P_#mz=x3p%==G}HgbYaWne(BT%c$*fua@yMJ)x2 zS_u@bE|e6ls>5 zMQhoiXl*+bb+SXzI(8^p*A7MN*%WmaDC#0mw7x)5SAn7p1d28kDC#Cqw2?qjcY&fF z0!14O6m23<)Kj2nQ-Pvh0!5n%6!jJ;>LXCJxj@kt0!3R26!jHKirN-)D>5L(e(ChH zMzM6I-zbfK#X|Cx6m3<^H@`X*4RU-a+S(39+t{IKupNqq*r8~s9g1q~P&CXAMZ@h- zw5?6i2!W#Q1d6s7DB3}wXrw^Vjsiua1d2ur6zwEXG)ACkXMv(!1d4VQDB4Y+Xskfd z?gB-72o#MIC>k$Nw5LGPUIImX3nfJZin-nykYakJqVj>E=;k!`DHf8iq-g(Qe%EV5 z(L~3Gq66$uG|3J{2il?NAUhNtY=@%Bb|{)+hoVF5P;{tG(P08bhYJ)PAy9OrK+#bG zMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fRDq&t0!7mWie?BDog`3nvOv)(0!60^6rCne zbh=Pdv|lkdH3L$tNT;6(p{Q?qL_4EcNWPMybBg(^uMb5t9UqF$wL{T)b|^aE4n-H( zq3A+86kTM8qKoZNG|LV}vu%nl5h%J;py)DzqB#OZmkShKAy9OsK+#nKMOOU&P3lu#eP&7}VXud$vlLAFg2^2joQ1pyI(X#?Y&j}PgFHrP?K+yt$q89~0I`-*59f}UKL($=OC_2KX=tzO0qXdeM7AQJKpy*hEqT>XLju$98L7?bF zfugAbMbiX|rVA9!5GXoHpy*_QqEiHlP8BFRO`zy>fub`6ip~@$I!h=inpiJ4F#}S3 zIDH%cfKc>l`gX|K^$N*XQgmLu{F(QMqVpXeiY~B2(S>#>y2uVi7u%s|mK};_+o9+Z zI}}}NhoZ}DislFuT`o{`g+S4j0!3E|6kRP)bd5mKwE{)g2^3u~P;`Sp(TxH{HwhHo zEKqcdK+&xNMYjnQ-7Zjchd|Mt0!4QT6x}V96wR!cyDI}ytV-vib3@V0^oVv(y+ZPp z6g^Nczv#hG^q}KI(L;79de{y{bL~*{h#iU^wL{Tkb|`w>4n(R_iTCk2Y0 z5-56Fpy(NaqGtt)o)ai~UZCg&fuaQhMK1~zy(CcdvOv)*0!6P16fG1eS|m{Pnn2O( z0!42K6ul`>^p;RkbYH#P$_z+xj|AubP}H#Yf~{U5`AUl3ua|EzHxzx~_)zqr9g04( zL(#`}C|YcXqEGBl^r;<+me`@_GdmQ0Zd3GyK+#fxqAvxCz7i<=2_;2;)yqxKfD}ijpP2nS6m`#jt-O8xLh_Xq ztzAEV?c<@SljB3tI(8^p*A7MN*`cVj9g4cxp=fh$Kv92zq5%R$ z0|kn<5-1uZloWNWpL;$7QXG}eMQhbBUFqMF#@6)<$yZV|w0{1pd7-Gr@u6s#9g2qA zp=et>6pgS$(ROwy+TIRDJJ_LUq#cTOv?&@TP&8VgXeWW9F#<(93l!}lP_(N+(QX1o zV+D$K7bx08plF;x(RhKPJq3#P5-8eRplBa~qJ0I5_7f6dfy2beurZ@d8CB2o#+tP&8GbXqrILbb+E70!1eY6rC(kbc#UH zsRBi(2^5_!P;`bs(U}58X9*OYEl_lhK+#O0r0BrBI%DuJS_ z1&Xc_D7sdl=sJO->jjE#5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ37x>KO&E`g%E z1&ZzwD7sgm=suyO==}P*OEVzF^V6071)*q-+6%V&h2$$Kdboc6k>^6uT*rr^N9<7a zs2z$PvqRD2b|`wn4n_0qP&D5TMNitH=qa0`rv-|h5h!|Apy)Y)qUQyQUJxi+AW-z8 zK+#JAMK22!y&_QbszA{~fucnMMXw1Iy)IDnhCtDq0!42L6um7_^o~H$yFy9PgY|QZ zGa$vA(&^_Rin3oTf3JQa`AUjDs-LgBAQXM<_)xUi4n?2Xq3BaP6fLns(Pwrj`rHmh zU)Z5&sU3>Gv?=;Zpy+FXqHhF>mI)MnD^T>EK+*RCML!4>{U}hhT%hPDfua=xML!D^ ztrRHwMWASvK+&%PMZXCY{Vq`Shd|Mv0!4obB}E_9&vnXx6t_-4cl}`~Iy#+;{;pq0 zzLKI`gZwrxg`)BX|Gm=B+o7n!4n+k!6jj=xsLBpSMLQJLvqMpRI}|mrDQYNC)JUMH zTA--0Kv5HcqNV~x%>;^?3lyy;P}D-8sHH$rD}kcb1&Ue=6txj3YAaB*hCtDp0!8fv zirNblbr2}(D3lb{ZIGLk0V)2O;FL8eU86P4eyx1128HA+DO$Hd{_Iym(Rz-Lb5UnI z6m_vf(fW2M>S~9g4eU^~p&g34*`a77I}~-dDe56mw6Q?ZCIUr01&THmDC#9pw3$Fr zZ-Jsd0!5n(6m20;w532%UxA{20!94=iUtT24HPKaN}y`=6w9g4QML(vX)C>m*pq8;r} zG|CP|qwP?%lTFbWfufxSigpnw+Et)vH-VzD0!6zE6zw5UG)|ysyg<>O0!4cX6zwfg zw2wg1z5+%22^38bDB543Xre&T0Rlyn1d0w6N{VV48F4yVJSof(C`;D=C`QAiu|(p=h?_L(wI6 zD7w@RMVHy3XpS9@Qd}qftmDO@s4ShB9%@iXzLKIx8|1HlI}|YdR3rkp+M0hfuh$0 zie48edPAV-O@X4f1d84kD0)Yr=v{%L_XLXG7byBbC@GrTAh#d`QXG}OjsHj}I<|f` zK5S4(zLKI(8sxuuHxzy9_)xUO4n?2Yq3Clv6n$ZbqNR2y`qB^sS)gd8K+!J(MXLmgeibPCO`zy^fucVI zivAQR`b(hbZ-JsZ4dcR`qPjv!(Z>yP)$e7Bnx=En;!w0xdPFO0SV+E-qKbz3jXnrP z1;>Y?N;?!)*`cUthoX9RD5`IVq6T&-YG{X|Ms_Hwwkc{XP}D@AsHs3vGl8P!0!6C{ z6txg2YAI0EN}yov^H$$%8=r0;-q4n@Nf zsbLKZ$yZXeUBmoii$l@&jt@mU*r8~o9g23eL(wQZ6pgk+(N1|ew3lvQjN{Y5^nENyXQamyJ-1Uf1bXg)brC}lYN{S9|n9nTtzT#&v4a#$#uoSt1@+^~>*B}JDu%n$iI6kX={P&CI5MVH&5=n6X&U1^7+ ztL#v8wH=DCu|v_db||{ers#Tsq8kK?ZWJiGNucOvfudUkif$Dsx=o ziry0_dS9UE1A(Fs1&TfrDEe3^DSE77?!F92ae6L;^LQv4oW|mYh2$$K`mAC8&96ey z=Z+6WU)Z5&sU3>Gv_sKXb}0JV4n^PCp=g;MioUf&(RVgQ-wPD|AW-z9K+$r6qMrnc zRtOaREKsykpy(HYqE!M#zX}xnCQ$UdK+zupMSltu{UuQJw?I*yMse9rQC)$eGJ&F; zKvB6+QuJxV+;16>V#fq$Nhn&9M!r!Y`AUka8s%Fr3q?i8hoX9RD5`IVq6T&-YG{X| zMs_HwwnI^4I}|msLs3(kqGkd`%>{~96DVpSP}EYOsFgs`>H=XWVuzxhb|~7^4n@6e ziZ&A{>Mc;zN1$kPfub!0inbIe>MKyxPoSv3K+yn!qJaWMTL}~m5-8eQplBO`qQL@1 zLj;P33KZ1{6b%z78ZJ<@tx!_5exuwe8IWSP^nJ9hp=f*>BN`QwucT;Xqx_9OgrXfC zABslVp=h)nigvO?(HJ`v?QDmlUF=Y_s~w7VvqRBXo1)zXiuMpF8YfURUZ7}Cfug+x ziuM*L+DD*hUxA|i1d1jI6zwliG*O`F0D+=O0!0T36dfc`bg)3tWPze70!4=i6dfv* z6m8!q_fiI=_)Plg{T)Kl3F%yPSffJnl@uM-DF5y9P;|88L(wsIC_2^-MaS8p=y*F6 zonVKe6YWqm)ec3|>`*k_rf7yh(MbYDCkqsvB2aXyK+$OeMW+iCogq+kra;kI0!3#F z6rCebG*h7HT!EtV1d7fVD7rwP=t6;_iv)@;7ATq}P&8X8DLSH2uE|fCqCe9Y8jlP` zebQzBC5;NnS5kC&qkNB_L(vtE4@Fnnq39|*6kTnHqHF9>bgdnVuCqhY^>!$_!45?? z+7#U+P;|3E(JcZ+w+a;9CQx*{K+zonMRy7m-6c?Tw?NT70!8-<6x}CKbiY8+0|G@4 z3KTsgQ1q}s(OiL|M+Ax<6)1X4C@H$EQEp5Iq_}xH7tIMpFQ+d-KHjL1d?iIsHp(CU zODKBE@uBExI}|-*hoWcgQ1qM~ik`Pa(F=AcT40Bw7wu5=l1VDqudo4kmB5QSvEfu-I&frOBxlDucT;cqx=)UhN3SWABw)RL($iEDEh_@ zMa%3^^sOC=zOzHo_jV}y!45?~+7vApDEdjDXoW!0&jLj&1&V$VC|V^@^s7M8ZvsWX z3l#k!Q1quj(O&{Ze+v}VsgBEbis}j!l?fE(1d7T9it++Q6#_*Cp`_^ZM!C;2AjNm{ z8JsUd(Ua+1R9Rg}zLKK))%pA%p{Rl5Ls3IJ6g9F#QMDb48rz|$i5-fX+M%eK9g3RU zp=dRmq80*0Ed`2N2^6g^P}EwWsEt5TTY;iA1d7%aC~7BA)Lx*dgFsP7fugkpiq;k= z>LgIKjzH160!8Zy6m=FT>LO6IzEDzBtj=}LfE2qVIQ6PaSNd(zv+J(ah2$$K+Ne5T z^H(V9?)XsD!wy9o+o5O^I~4V_L(!&oDC%X0qRs43)Y}e4eQb(07bx07plC~hqP_w} z{RE2o3lt3yC>khGw3R^7Ac3N-1&X#2C>ktKG(@0is6bJTK+!OPqTvEX+X@to5GdMC zplExcq-ewH+~f>Mae6uzbqht^(j(dq)rI6MDH>g!Kd(;u1G?2I-^uZzXp9|-cD6&& zE_Nu|)ec3w*`a8x9g23hL(v{~C>m!|G+v-+Pl2Mn1d8?+DB4G$XkUS%{RE082o&uv zP&84X=m3GDNdiR&3KShAP;{_B(PV+5DFQ`@2oxPEP;{6;(cuC`M+hZFJ67i&$bb~z zPv1Hl6^bUNbJ3C2h2$$KI<`9hc3CJo&heq>csmrGV27d;?NBt;4n@=KP&C~RMKkPB zbdnv4PPQpJMWExHo{O$_d?>oc4n^16q3Ak06kTtJq8sc`bfX=LZn8ts&2}id#ir<1fuh?4 zif$JuxE9u_E?D^T=^K+&TD zMUM#-JuXo6gh0_ep`_@F>fC?~Nb&G=`nfU`eUlW;uP!8CNzpUa`MnCE=vl{yqUY>T z^t>I4Ua&*a0y`AFXosSg>`?Tw9g1GDL(!`?MGFOr76}x+CQ$UcK+zilMQ;iey(Lie zwm{K40!8l%6ul=<^u9pR2LeSO3KV@LQ1r1t(PDw3PXvlS6)0LFQ1qEV(dR-*(NopA z(=s5%+38&LbSSEmNPSUVNWPMyudDMnSB0W)93P67*`erLI~09qhobN8Q1pWxihi_1 z(Q-Q!{bYxt6*fgb3lyysDEdX9Xq7`>Ig4n-~PP}It%Xmx?2)&fOs z1d7@U6s;jpw5C8&JAtD10!1AJiaH7uttC*jwm?xQfueN;iq;hfSiF zO9rGkAYG&N2u1g#%l=V~3&~efv~%P9vDKky7srR9UF}e`n;nYA+M#H7I~46n2vqCM?Uw3kiM-U3DY2o&urP_&;w(FB2_{RN693KSh6P&7%P=s0!0rC6wMVVdPJb;QGuez1d1LPD0)JmXr4gPe1W1T1&W>$N{X&- zoLfHwQk9sFd?iKCH_i`l5sF@Ld?;FAhoTqlQ1p@=ie9!u(JOW+ zdesg^3++&}$PPuX*%ZAlQ1pgC(VGHAZwVB=El~81K+(GbMehj|y)RJofk4rR0!1GQ z6n!jEv{<0%6M>>n1&Wpk6n!R8^tnLM7Xn2~1&Y2DN{XIsoI4}~Qrs{7#O!mS=(p_G z%D-w{NWPMyZyV7Q9Xg8`T|7_gp#6f8s{F$fD}ikbJ4O;bY*&YYuKcad?iIqn&jVY9g3Pd zJ`^>xLs4@(6s=~5q84^2YH5d}R(2>_-3~>q?NHRlrl_qz(Ha6pYYGDVpgP}D)7 zsG~s9S^`CD3lwz{C|XCLXkCG#^#qDK3lwz`C|X~jsH;HH1_DJJ3KVq{DB4J%sJl>7 zRNW-^R|cf`V|oy4+@y4+|7nJ&yhoEl@|6^A+9bc`8vl>I`v8xsY}>uRCNnFOWCBU( zp-ELlAqgF%cLWp#6%~a5p*IOwQBbe}7A&BM*gImwu83l<*t??GD|YPrx@MjKB>L=k zzv}ls``zC@c8&w?InSAU&6-)iS+gdYNu;O?^QEXOS&F)mrDzYb6m=&{Q4g{d^(0GC zFR~Q%CQDHtGK%_Apr{`OiuzNaXaEI@22!AC5Cw_`Q=n)F1&a2hK+#YN6b++5(QpbB z?L~p2y(v&Mf&xYRP@rgE3KWf`K+z})6zxZWqWvjQbO1%9sAG+Ie*=+ZijJf}(NPpAI+_AS$55bX0Y#+fpc?U|1|;WIf2Du06us%Bj;)b&U#{r* z8sT-#r04|ZOVMJo6fGf3(TQX!I*BYrCzGY<6tWbZN|vIfWGPxkM$vK#6rDzaqSGl* zbOr^A&ZI!m3JMgRMS-HTDNu9{1&Yq4K+#GH6s@8_(RmaoI-deXt0_=)0R@WIP@w2S z3KXrSK+#1MD7u&eMVC-SiWb(0Z!sV_A6QH*lAmThld%PX=U!sX}fQ!NN;<(-=s1oiS>F9?E$c};5tL6f}6b%LNp z-u3l@pjF;C^@CvdysnLcpg3>gPC?Ki@1dqa&?PU`A_%(Y?Xz(yf_Hn%X{j?AowV+<|#q&S>Az5gJ65!MazTW z+r0Nr4}u+eyR8Umk++KF``?q^J(ll(5V$y&?|;#?LoDC_ zBxjdczW+_d?y-FTqjEE`zQU+iRJr8wa<&?`)6&} z#Pa>ak{8GF{nKuj$MXH-N>|77{qrX4V)_1ofg5A_{*Lbrv3!5a?j5mwf6wJTv3!5i z+@@H*zw7D2SiZk)<;$@VY`I~KIEuJ&#*+tTgrG3JjoJGrJsn^;h%lRfle?VI?_>VB4e z)xFV{8S7ZxyP&R74Pu=XM*2CO6?Viebg8~LeX)AE7P{)3=j~cz-4s6dIeRE<_t0J8 zAYY>%3S)d}J)=;sm92NIS2`H+V1}>ABwvx<(FF=^2N3xB58Ndd)Q^qGEO_Vil@}dd zKekVp+wa*WgX+ij%`8~8_LP;!){l)0b6bu6YFtp*(B_oboP(k{8S{gnu#T-lPwQr> z%la-TY-Qb0>n>&4=ihkcvIXg7XSd$m-(?%^Rkg{N-0<9GM+SwXHK&$cbNa^I_|8kK zkF!ac1)o1~`3}1cc8%NL-n>(K(j#}SSh^r6tYP<8`W}cTg}J{S|4LE%ih4gZqfUCt zHCY2{r*Hp|yq_|I26b#knXh9rOEV%B8CCmK!?3(ZX<${Ij*)M+5 zuys(_(nwJMqvD-H@rXgN=^oU86QbFIy`<*dK=-QVmM*mAC0bNh?Oq?fa9;OsXD@tlw=L7I z=Z!B;*<`2edbVHl+1hA*8?^7-FDSfAlcq$I!rWIEY-(t8!raBzd^J2h<)TYp|K6_9 zHpHDP&p6HQ({^EWMQfO|dFqe0&1}xHTkpzC&$)l&bN3#Vo^#ea&t2$q%(}1K7Urzq z<9jn=b6QSMHBHZX{n^b|`dyG&aOL*579AH9UaL7_Yu%uYr(L$g*2E^2PdjW}deXH| z-T0{8gEnc|-H+aFSJccNI(|i6qDf)yLyv5Z#5at;G~VWfxuYNMGATV}+r2L@T^JOu z)|44s&$+kVw9)P)yPkT(V;$4i^Y}Y!UyL3lKOQi%eNcFZ&GGHLFq-4rIV&r==37|I z>1$V>72W^u-+20+e*fD7`*-SP*B$0|d+@jXps>2l@dw)@(VX;yZBkCOoS&jD%zb#~ zGu>=$>``>X(v1=G<7O`QyDH2LA0A*=eYK{vwY^vRp|R=1_uu!&VrIdbCmuT8PT5r- zlKr!9k}&tM6gB#`ODUKPOoF%!FNqFxVFFd8B3Wl>HUlMO|RO|-`sbuDX~>M`<=~;?LM}vdGW-% zk2kr4HE9#;_WPHYZ}7V`vtY%U7rx=!BeP)9NAJBH&02NC+LvwR4%Mu0xvF`u)wTz? zO?q?9O)H}P#HwxAe;zp;eN{nW&~Urvr0;yTCV50}ceOI2BFj$#;HNlJ^f=!?wNBGczqF0z^ysY_M2Nnz!B`{Qqvb-v#DLO$SzQ;LzR{4RoJ~S2x_;D^(tgdcPT80)yV8!Z&lwypI0ZW za`BA1xA(O>u5Q&uG_-54SGCZE3Qs*DW_Nl?`r7L+Js}ok)LYTlUI;X>GXg)u4o|s^ zsc0Mc%FL>sUJqM)I|Q(=m_6ZE`La!AhixN#Xl$3T2aykrEhmC+Vk0i{Q_bw3o#De9 z6=(RVtnPp!gym|BJ88k8k|tl&=I|zDiZUs^(uB8_{5* zP05J;T)mpzE9rH$^^LV{TQs+{Xj1u{qVl;Disp_jpHMb-&fMAa$|lS!n^-hq?oo5* z&GuqK*~IyC%gU>q=a;ujcP*MTck0Zk^QInN78FgHJ+rK+bVk{cMQvxyo=`fYsC-K4 z+_Iv%WwXl4OUsMO+KnxrH-F;P*+uha&z>=1O6k;DhRy4D8!j!4A{@Yih z{HXG(_r&BWMSbQ@oIiEe?0&Q7mbIz4FOHlyH+`2x_sEF3v!~g8US2eEPU+m~1Lw~g zJIZd$|0_1r;idD+{NA!>&Gd$zG=J8FV!LA}82Di9#Ii}H^JmN( zJMXADW#w(BxG>vX6Q|CaXTf%tBl`^)YpXe--|U$)XV0?E@BwD3FFL9MdnpvAb;jGr z!m#Fl^cBW3Y)w0W65?Ry8Y+F{Cvys(K6)~BOg zKC_))tSD^KEUeMUCu&x+zc4FoV%OH#CjGSw+co^v3;(nAY5I?D#Xp<%w{H7CyE*@C z*8fd6r=~%z(KKw@EUf7^i)6F-4>p@t72P&1y0*g~8rB@*lZuKahcz>6hBbDw)Wc5t zgQ6&GY-3iFFgvr~3uJ^L(j!VGAuh9sSbn{{MR6reTX_VVy>H6Pl)P z!hdp0(>J_Hn7-X@ZBh%HR5Mye!z#=8OUwGV-)n#Kw*A}J=ii6vUvFtf&sx#L;r}|Z z|DJnsvh5D)+T*=W)39Z;u&zHKiu8ccenod=%c>83e+aY-3vFKZ(6H_hpOl_eT+}#h zVULXlRTjhI{?22gD1Br9@}tvNrk<@#&9-5SmSIi5_NEj%S>$JCXa4av{ZDphwwR(Y zyTtdfeosWvChz2NsNXaHy|>ZsnRa1K-{%zh{a+N;`b#$}eNnqvwW6C9MVtJ8#LY^t zjoqwT|LvSo{y34eRu5 z6Sim`){S;#ejM%l>1g~~w{4om;_5brPEk^kVj z{@EH9{eOEMP{aX6{Al0%XY5f^V1UE;w+^79oAOUzoBRWZj{NUAvkmlDUt#{U4f8kG z=Wo2?{bwlu*7_8QRdg^L?LrX1_*WhYfAdPy7yqYh{?>K6M=ofDH@4awQQ8W9N!tO1?#_^;4>Y{H{{>Nj}^y>VzwN5|r zrWb8byao19^_%^#i>Ci8cSKS8ZfjI!X@6zb-@31xhPyWl8~UXN|lN#^g zC)mP0!kzR;Y;9w$CSmQ&j_GIE+V(^{#8OchwznUC)NER`oBi-&sGY1`^#>yS&@TD` zi9H)+XT~qI-ADQ$%AUK^->(eq(^p~l=rM0sJj7O@D6AbnKi2(ES5+;(=(vnNv1os3 zyG`GH7G>nxPrLUWFlg++;=zHBC0&XKj~ySK?9`#+WXFCLCp&e~B|CJX>%-*Y4$*l7 z`sp$ycHybRX3w5e5)AJ%dThVFMzxEU-JdBPE3U6IRr|{8ZC7!<{i-ZdE7*<+ohmNX zHN8&rXO&N#JgaPC6Z_$8`s(^=y-EhM6g$Dq98hsPN^E7)m+xv98#~r!w{JH#T0)6k znNJw&KjzgBhR4n=iEd0EEwyjulI)(ai%*%gt*qubfJ z;?~*L;&$35*2xas9sMisX}f=QuH7He&9bFLC#u}8&P=r}lRne7n&x$^SeUI3SK3aO zZ(q3{{VHaZ^y8{*#WlluRe7Vtf7ROq`j?HLKRK}XRLq)OHnwcm#HppT#?F{MYjSi0 zZF}3*+nW%oY;dhwhsw1zT+ziVZXSw@D{o!bid#}*50GH!fCI<&>A!D!-oT2p?D3(S z+y4(UtN1D@ZXfsxHc9{YFQQ8-SF5kkV%s)q`s%=JSF2lDaa{w_v#0q3GksRE7GaMQ ztykZQHS|3~`a*pwrkC`$jo)YAK@tB7CR}kzmx{%dR7yk+a7rp^+AZ*_t$b`1cjU2! zp9(3qCyH)OCA<=o7j?y)S!uCkAX}}HARE$dQ8bSezQxjeL2dPlH7Y4CPM@L2P?cW0 zfRf7ls|tqBS{|E-$7kftuc=GrooaV^bmi?>i%Kvhm0}E7bg?RQYh#A6=6x=EtNh>ssO11qmxaqRLkzy?!D-`{cK;5jk@L% zTjO-acC~$z&T3zAm)ae|#YM%I!A57BS8V4lc0*@Z&^ADt%afDubyV3L7HnptyU?yS zeZuYu&Z}HRdX@YsV3fTJNS9}#ZI5*08$JD;7d_PtsF-bAKufG#1Gcr@LprZwTiPaw zuA$P1?QiT->4m4yvTdtb_7tR36*t5jM)Pfl>wCVr(Y;a<4SF7~)KF5%p+aKCuA`EJ zJ=fb6l~0*HcV5NQE8EbirMG^?hOamfum@CnWqjkLDcRi;ov31=a@&_wZv2wUt%Vw07mY40?q|M9; zbLRJ$V0UQQk!@zSZ*RrCDf4HJw{g;p*`@Q^*!%l>*yfw)gjT5 z%i7E+n>Bgflpe)aMaM~PT!$q;s+c!*_N+GL_Fg+1%dMMOIj{@_;w3s>&AcRMl2-*I@5~BP*WEOE~7OJbtY_Y^^+Mwc}siEj~dfE9i5? z8y$>}96NYGpAqTXQst18<6a$q+8x3}sf2yCADc#Zp7cfspXqzYk9>77oW2*L2X4hZ z!vnSA0f2u$0-j#66XgK6@_4cGaIvIv56feq0!YPyX~hv|#ldBjM_=Vbrt;7b50wXo z727#Fx(o*O>({MGD}Q+PnLD$|fSKdVCQh_N{!zSjHvNd>EwQ`)$B#dISFn9HA^6?C z>`l}Qs@pro{SCx?`5T4%RIj%4A6{e7oZzT)UJIiq8M2O7`>D z**o>Cp5M?uQ9$N|4{B6NzCN`BdxL&@tGJ6Ac7L|2 zatVJgyM21L;>+`(iew)nu+sYuE&(JnViV|9B-c=nG4<}|a< z7ASY~(dG|Repq8qdz-dj{x*$m&A#W0ZOmvM1Z|C==PNZfwvUB*Ua4_|kG9-|(eysY zM_b?V_F*Z{muvJ7aOJeHPs%Dk>0?X#z_RkrMmJ|?`xvv0e!cm&Q}X#Q7-1iG_-MDg ztvyzJ?62`4jh|`sM@)t>_I+B0-Fd!0@UgZ=`#?&NVV@ecyDrEu%aQr6EsfKXrIhZ&s(U`-THFQ)OeZ3n{40X{kotC0cYx<_H12LY9M4@f&b9l(^Fobx*lEuX zY5c8zlv53&vA=B#KYt&MOKsbGUZru1-LanE)L6&1x##8@$JjRZJXPbRwgEifpz)*D zQT|S2+cr_&L*qQ#P=5L2HQrSce)*9amv@Qs`5K?=7Uj1!*0T-o zmv5=@&|XoVuJQ6dQNBszC;g)QgT~^4QSPDf@WD}Dtnr>bqx_i0jNwtv(>QqVDDS87 z^nIdyfyNg`M)@6$_4kkRE*i&;j`B>6SK1EOZ_h0nKN}O}A2qfc8|7Xak1UPyi5fQ= zbf5o(#>Av37iipbN|X=Kc;>VyU#Rh=8ByM*vEl3}@2YY9VNsr~@#^v@->UHo`*gNn z|IZpb92w<48jn6Y$|q~wv>?h)Y0O+0<(e9Y9UtWbHJ-IN$`@&T<-{nzud(qdQQl4C z#HCR_Oyjl7qkOx@?WafiSB;%kM7f{F1!qV3RE-au8|7y-W}O%1+8Xy-9p!^Hp0g&( zmuP%#ZInOM*yNHZx6wH1vM85pTz5s3@6`D9RZ;$3W0z~AJV4`d>!Q3&jp(vlG@!?0J{Jh58$D>@Rao;DSJXYg*Pe=I*jc;v<@~0YGJRju}jniI?@(~(u zd^yVZYW)7yD92xm#_n%K;}DG}ycOj$G(NgD$}eiHzAefPG>&>d%B31te;DPfG;aMk z%Aaf8`Ligu*Er*gC?BQq=Iv3wPvefSqa1z{jXl4M#-SRQ{1D|88Xx~L$}elo|0T+e zH17XflqYChV@Hqvc)mvCyY?G0Jb$UNm3=>nfRFsps(b(I5 zorcdJuJI)My&9g+*7&3yNO^u$V-5RF8=iO4INE;YhUYSkYwdS$c)m{Kd-h8>Jb$IJ zwf!~@&z&{SX%gjQHQv@N%9}Mdv|qvDm+z)=pvK`ohW0y7lqdUW&(YI0&QX7?#-$op zX}nzHO&T|9d_vn4wCjo4@2T)H(??ssnm*e44AOY8#@QM#)3{FKR*kjo zz%)Hi;|Pr>YCKQlQyK&NbqRj?jvA+Gyint_8Z+&81^DHt1XR`=sfTW^2;;A8rD*G4;BOJ_R_OOLHIw$o^b zN9o=Ud(vYcjYBos;Yhl-!;JKJkjA4m9;fjnjY~D!(_Z@W=W4u2<7FD{X(oOCdX0Bz zyho$$*3;+P?mInZ`e-*UU)hFqZ->w6vD}ZV?e-ewAj59FZJKlr+Lj+Rb6)9q8|Tf9 z#wnb#Z#>Qm+WL3;g0|z!%Y(M|y~(y-wyp9aEqa-lK5L@?FwK5EI%&4eN}nzrKYni6 z;nBpXu@5*`jiqz_^`jOYUE*Jx8UFEPEz#C3Xgk3^OIv0?!>w|yljfGrv< zdGqE@9Y24bE%vW}*{~D`F+6h4zSbAv6I1b_UEEER4F()^-q^Osb?&B)hFnS%avLF z!}T6xzu3t-zh3XT-XrZabL?a=wpT1@;wSXQdGjn+U0(MEvGilWmuEMpVtLE#G;{1^ zu+Wz0j}^W+?_?{gE^kN8=dz5{XGA-K_i#zKRp)gX&ql&?tUx$G+$@h<(T80-wyw} z*Zx&qzll|DZ%sRo+xxVgHp_EtNPlgz<#i+2$aVS1W5v(@#V$9;in?~Xq5bpa<=a2M zP97U}GMF(d7Wh7nFP2weMb*pAv-Pt>!iq00SM{U$C2eOHm2@ud)TOvxmv-%%*!Osg zORD_esZ)n0O}cdIRBVHNjmud$VA#N_zlS1b-~C{@enrdoN~bV-thcg#XWbxw!`|P{ zDed?D_<48ldH2u|K{}n z&*~EWzHZ*)oaPx*@81zL?VJApg!KOpr2oHS&)jiOjITN6{Mauq?EUSgk(Ug4zLc5q zX&3Hkvr76+^Zys8|KFVcpKG^eH$As`V!B;-pZ@9pm!$uHF#Z4O!wSYdKfd{t)mrw_ zA=@gKJ>#Tk*)!71PXE6-{eRVEuW6o`nO=7K|0U`FA58y$gqD4QmR(+T*|TOx%bt~9 zcKZL#>Hn)P`@-gl+397c|6h{+|H1VC3!eH+xz7=M3_7yEhs19+0~z_`;6gqkUW=w%vBPxfj^8TICNsqWwokEOWFyNo2&brsvp@ z5x$)CAvw{?xc}iY?ZYy%LjRTK8Cl5&wwFpI zLjTEGMk4vFT_m1i7mx2=vyY!X&-Q`w;##BZba;l(k7cf~MP?>EBom39!|Ux5S^oEg zchT>N-^pT0kZ7gY*kZdNv8!Sui|vC%YsH2ZI|PZ{6dPFV7$kOAtZ%WC{TXbmS!)l#jq2OZ)~~;EhUNCQegl;4 z`M+;_Tfc$Iw*9jci5Br^Z2RXdaz!np-*Vo@d?W@XueS@hkfGr-20ATdn5Ig|a778( zOHo4hR+NwtiW0JqqJ-?LC?O*iC1jMMgzTq?ko}bra)2^IMk^!aKxKp+q>PY*l@T&V z86k%#BjiwJgp5^2$T($$lqw@+yfQ*2C?jN|GD6Cf5i&^`A(NF6GDR67Q(2%t*Q%7cwXO%Fav+IZRU}WUiuwlq*WeJVgnauP7mh zD@w=_iV||9qJ$i!C?Q8HBIFolge*`-$g#=@IZhcN3zZSFNEso=D`2JdMkBEz>2h4ixnWIv(nM`2QPbwqiDP@E_t&EUolo7H;86nRqBjh<{ggmc| zkQbB@@}e?AUQ$NL%gP9OMHwNlDkJ1Iq(d6Lf#G! zuy2H2PS33*3RLf%!BkZp<*@}8oEyss!BA1F%5hl&#Nk)nirtcZ|Llo9f&GD1F6 zM#$&N2>C)8AzvyZWV z{H%E(SNzL$mh`lw#=>)lnL?RYmVBg%T z=C5YLm}c)}*$#U%$&D@BVR@3=$g&-lXOSCPw!`vlas$hDSe`?!Z`lsZQ{+O+c37TE zu4mZ}%d3&=TDHUT>f}0>{dG+qMQtx^4f82#d10$qKvB~RTgMs{HN3EutVvPeg{@^R zihM6@HEUDkd132WhoZU{wxV?@s(E2+T8|>v3V(%DNRjfw*0erFju*D34Jfj`ur+N+ zk>!Q0X(NiH7q+I2DKfpVHQk9K^upG(2}QySThpc#aW8C5n^9y~;jeX?Q^dTmHEls* zK&mGa8L{{#1CqML4^QH;NYP7v+|n|ZbY8A#*I4+Defux1s5SGYXg9JH?M{}WHe@Mk zOO~P{vJ@4QrKp4~MeWE^)Sir@4iqTrNP(hG6e#LUfub%HDC$aqqHYu@+Jgc`-6>Gi zg91f8DNxjl0!6(kP}GM4MSUqy)Q!sAr4%R{Pl2Kd6eyZVfub@B z6iuQ)(PRn~O`$;1R0 zyr&hN&wMFbO_rhy$WpY1EJYWRrD!c#iY_8c(Zysbx`Zr6my%I*83l?ir$Esa6ezlq z0!3F*py+A}6kS7sqH8HobR7kX)={A7dI}V+r$EsS6ezlp0!24bpy*}_6x~9Bq74)% zx|IS&w^5+zb_x{TK@llh8H>MSKvFIJ<<}}H`rLlNkhn9JbYHIM-dOl!eJR?=d?~t* zEJd5hQglCAiXI?K(Ppv~JxG?KhsaX&Fj$=t~L|ZKpudR}?7vngT`NP@w2r z3KV@ufuipzQ1k-@igr+-=tl|^{X~JHpD9rE3k8aPr9jbd6e#+g0!8-ejtgwdCt@gy zQJ^S;B2u(97N2N9QlowM^Ntja_h+VW3KTV>Kv81~6zxQTq9zn5YD$5kW)vuDPJyBp6ewy*fufx$P_zq0q{#l<(6t66 zb&&lGK9QLbz0!Zc_eHJj=j`Uo744o8KG9T)+Av>=+LEQHh%80LWGN~kOHn(r6tyQy zQ3tXVbtFqsCo+mUQ=q5|1&X>-pr{)KiuRyDQFjUy^`JmePYM+EqCin^3KaFBKv7=` z6!oJ(QGW^)4WK~LKnfHMqCnAL3KR{YK+&EQC>lzEqG1$~qShJl?FJ;3XYYth>?TEV zf2BV>Bk8_e(LNbrK?^C`m-$jOk}O4|$WpW)S&H^2OVI&jDH=_dq65iNbP!pJ4kn{$ z3{QlMxS1&U@?}n`Fkgy}BumjzWGOnDEJeqVrDy?JijE~q(Q#xcT1b|nMPw8mPl2KnC{VPR0!2$G zP;?>%icX?H(a97jI)ws7r&6G3DFup_QJ`o!1&U6iK+)+GC^~}zMQ2i=Xaxm|&Z0ok z*%T-`hXO_CQlMxhMWkq6Mtp$*Nj3Lx5zUvPYkXg{DkJH>T+sy?;f1ZFXbtnF=t8m- zttCs*MPwo~J<3 z3lu1Nkpe|8QK0B$3KYFUfudI_Q1luFie9Hc(Hj&fdXoZ0Z&9G=Z3+}^rHB-5%!p_0 zW{QsR?>gQmMVAm+dHuQJ^S;0!48O6eTE76jDTrwq?ZkG9amOzAt)D zine>mj3?cfE6Rz7vx}rC#e6BsB}-8?vJ_P(OHm$Kit@=)R6v%Z8e}P|NtU8oWE9n= zKv5kE6xF3bQ9TM26;hz6J_U*zP@t$G1&SI`pr|ngiguzvQ4Oz*Hu4EK-qd?If6e#LWfubH1 zDC$XpqFxjz>P>;7J`^bGOM#+(6e#LXfuaEvC>ltCqCpfW8cczrArvUulLAFUDNr#!{eY90iI>DNrLV=>G6eyZTfuiXYD4IcmqL~yZnni)4*%T<6LxG~hC{Q$)0!8H%D4ItR zDcUz4Z_>dOy=m`ROpKJGaej0?Kb~}7uIQ+E*r$^e9nE|xI)*Go3&>J*ELn<MOVROUDLR2HMT^NOT0()M6Dd%15(SD*ra;jt6ev2C0!2$HP_&E!MawBrbQ%SU zPNzW885AfwlLAF6C{T131&Yq5K+!oAC_0w{MJp*#w2A^n=TV^Oe2PfX5%KsW1Cn~y z;T$PNZTuN+bv)_5T+!Nicybphx`_EwbTL_qE+I?NrDQ3(j4VZ$lcneivJ_oOmZGc3 zQgk&LMb}WE=voRCT}OeUbrdMNo&rVdDNu9+1&VH@K+#PUD7u*fMYm9(Xafa`Zlyrc zZ4@ZFodQL7P@w2e3KZQ%fug%9P;?IkiteRA(MF0$(VBRCodHSR=87(qqKzKziznTe zE7}|npR$irr+<$2AoHc@A+i)bOqQZY$WrtuS&AMbOVQ(GDSCn|MNg8Y=qWOao~A(2 zGZZM=LV==ZDNytr1&W@hK+y{nD0-0sMK4jH=w%8Ny+VPaS1C~R8U>18r$Esg6exO= z0!438py+K16m6wI(K{3P@w2n3KacDfui3jP-O4#j$XE-C`N&z3ubYHHhS|U8KmlRcJz7*w= zr6`{)MFnIjszH{bnq(=eMV6x4WGSjcmZG|36xE|ZQ6UA2>QkVo0R@U0QlO|21&SI| zplBxw6g8nhQBw*OHKRaLa|#r-pg>Ve3KZ>3fuda~P}GV7MY~d%f7v(0RSNePTGg{k3(tWw2c8Tz!K2p@4`BKz@EJYp3Qq+koMV-k~ z)P*cXUCC0^jVwibkfo?Q8AUxPP}GwGMZG9c)SCiDeJD`WmjXroC{Wa&0!0HTP&AMN zMT00%G?)TKLnu(RCk2XzQlMxU1&W4KplB}&6zxrcq7f7*+J^!~`%*-TiWBh%4M=LS z#YBk|z2Wrm9(yC_g}HwB9Bp+M2S6e!wAfuj2; zP_&5xMfX!giY`jTR~nGiy}mEHSc(qwXS4?rN%!T79!`X}?s`WGQ-_ zEJaU{rRYhr6g@?jqNmAH^bA>wwvbWuECq_5qd?K~6exOu0!1%Upy(wE6unG=qE{$T z^eP34UZX(K>l7$@g91fwQlRK93KYFffugMxD0+tiMekCeXd4BJ-lIU#`xGepfFe@# zU?Tp80ZBFWC$Wd5=rn(&|6wBOzFg6#iSXB9QuG<~rRa0A6n#OKqA$r(w4E$PUy-Hg zYqAu5Lzbd%$x`$k8Aabypy&q*6z!lu(T@};`iTNXKU1LS7YY>pN`a!^C{Xk}1&V@D zFWXTRqd-vx1&ZPnC`wSED5OA9CIyO;6e!A~Kv6aYigGAWl%j|feVm9l8*Yk@@J|wb zB1IqgGg@w#bYHG0KMecrEky;)m!cYEDY8Ef9(_kcifWOis5V)O>X4iXjcjpwWdJPZWJimodQK|C{Wav0!8-MVxwD&BKsrsQ4uMs9>%8_kkqgK zNY~Hyf3NN%!T7I)>q?`$$nI=1Wm$vJ`b8OHo&{6m=s@(H>+e>Q0uT9%L!% zNtU8sWEAzLKv5qG6!oP*Q9lY4^`}75016Zhq(IRi3KR{dK+zBi6zxfYqM;Nh8b*Pl z;S?y^ivmS^Q=n)B1&a2eK+(PwC>lwDqEQqm+K(bq)IN-_Hz288-~DuuqE#OD50mc8 z6&)0Y&y19!gPAWyW5`l;2w92_B}>s*vJ{OYOHnCVipG0x2T8|-N%!T77KUN%{iSFT^QGu` zvJ{;_mZHUEDOy67q7%tdbP`#LP9{syDP$=+m5idL6ewCofuiLUC_0S-MW<7s=nM)J zok@YB6%;5sivmSwQ=sS^3KX47fufZZC|X56ezlv0!14sP;?&!iZ)T8=za18r$Esg6exO=0!438py+K1 z6m6wI(K{3_XVbXoMqA$Ym!!c6yCG(|dJ6VdpB1_TNWGVWFEJfdvrRY1d6n#&Yq94dow1bSI zA1P4u69tNXra;jz6e#+Y0!6=3py+oB6a|@j)qTFjTC+GHuJLzbetWGSjgmZCzk6xAn7Q3J9RH6%+>BQlB_Q=n)k3KTV=Kv7c) z6g8tjQF96uwV*&zO9~Y2Oo5_ZC{Waj0!6!0pr|zkigu$w(e4x|YD0mdwiGBTqCinG z1&T^2P}GhBMeQjfMFpAheGN$JB0svWkr}| z_8?19cd``qAWKnCvJ~|qOHpsK6!jrXQC~8O`ca^$KLv^gP@rfa1&RhyplC1!iiS|2 zXio|h4W&TQFbWh6r$EtO6e!x80!1SzP_z#PiuR>I(MSpujiNx&eiSI$p8`b(P@rfu zMWm=xX8b$@lA7dCVx6Vv3jcA)ftgA7<%$l;4DXyEMTat9ipG+qXdGFJO36|*o-9QZ z$Wk7N z>o`V=X8JSQahXZ?<%&+o41X_^qQ%UYq9tT0I*}|zCy}M-WU>^ULYAUa$x^hGEJe%6 zQnZ|mqSGi)bUFo!&Y(cinG`5mL4l&PC{T1Z1&Yq0K+(ArC|XH@qE!?qI*$TH=To3) zH3f<;pg_?Y3KU&Pfugk(D7uIOMHf?`=n@JPT}lxtT9g@YG07Bd^nKCsQuMp;i!RGd zx-VCBRc1I~iWFVVd?~tyEJfFnrRX}c6s;pm(e-30T2Gdu8^}_0BUy@WBBSVL3KZQ! zfuao*D7uvbMYmC)=ynPe-9dq(J1J0f7X^y$ra;j>6ezlv0!14sP;?&!iZ)T8=za*Q1k%>iaw-3(MJ?0`j`Sm zpHQIaQwkJ)MiD7`JTrcy0ZHBE&uC9bQ4fFF|9NK8eYv8qGQ($QNYU5Km!faTQuHlZ zioPRD(f4F2`hhG(JIGS>BUy@mB1_TFWEA~Efudh2Q1lxGihid+QIOQjb`-@ZP?SM| zqBsSL5)>#3DNvM2fubY@in1tBlud!6910YrC{UD3fud>@D5_3@qC5%|iXjcjpwWdJPZWJim zodQK|C{Wav0!2j>C@Q8vQ3(Z#+EJjWJq3z7P@t$I1&TURM2c!93`!prq0Qv`*KBlB*Q}vlcMg-m!ckIDe6gP?oSK4dBCOO~R3WGU)TmZAY< z6b+<6(I5&G4W>ZR5DFCSNr9rF6et=-fui9QDB6nxMSD}AXaog{_Mt%0z7!}LNr9qK z6e!w{0!8~%py&V!6pf}p(SZ~wI*0;A2UA3fx+dc%7?70zE!IRgDLTdXMPrgl_vMPl zCBw_grKptoQZ$|{MH9$UG?6StWn?LuM3$n-WGR|LmZGU-DVjz`(R2zF&7eThObQgu zqCnAX3KY$uK+$0oD4I)wqH+op&7(lkdfuh?eP;@&5iteC5(VY}1x{CrucT=F~9tsrQOM#+| z6ezln0!5oBP;@^9iXNaq(Pj!1JxGC~hbU0=Fa?Spp+M226exO(0!5EgM2fCX#zz^D z)WiPS*lVO{r0AVuFXUy8mbOVJNxDcV7nq94gp^b=W%ekM!NFJvkDl`KWSkx}$J z1&V?!y=+HOi~>a&6ex;QpeR9sqL2bbnG`5WQlKb{0!7&rD9WKgQHlaZxfCd>MuDR0 z6e!B0Kv6ygiV7%DRD%LVH7QV3iy~6=buzxyfTZU58`Hj#qAVv>J1gnFTv1_G7+WYs z^_ee44aic|kSs-w$WqjpEJZt!rKky6ikgz8s2N#`nv+q~f&xV?DNwXC1&Vf|Kv63S z6zxiZqSh2B+KmE5yHlX34F!tYQlO}a0!76XC@P^qQ9BA0wWmN)2MQE*q(D(83KVsw zKv5S86m_MD6xGd&?`%L)?fgx$^|GQ@`UU=s)-5aPzFbkytZ>lrQq+t2Qq-F)MSaLp z)R!zp{m4?(pDaZK$Wkc&DNwW*1&a2jK+y;a z6zxNSqJ1e)G?D^EqbN|c9|el`r$EsG6et=^fuaK`P;?LliVmhg(HII89YTSkLn$If z-Lv8|3`nZ8!|5SKb9`SkHY@4AT+xKA@U+EJG?DpIR7RGfNn|OSOqQZ4WGR|TmZE87 zDVk1}q8Vf|?l<7y;*JLH#mn*tH zD=a)kiq2nC8Br9jbR z6exO}0!2?ypy){o6g@=|DY`Bz-qV1j_Oh5*Cq=*c%l@aclJ3hDJ(m@ZT`EP-Ghd2c zAWPAUWGQ-yEJZJqrRWv16unB8qSwe$^g3CJ-XNpsO$rpfMS-HXDNwYP0!8mopy*u+ z6m6qG(R&mqdY=MCA5fs^LkbjqM1i7@DNytY1&ThUK+$IuDEgcNMPE>$=t~L|ZKpud zR}?7vnj%uPB`dzffY{E*;5;iuOZ^+!-()4-mn-@qE4*U46zyQX6#Yn+qMyi8^fOtC zej!WIuVg9ujVwjKlcgxg*6VgDijh&2L4l$;1&R_BC<-Z1lu3c2Bn67HC{UD5fubA= z6s0IoluLo4Y7{7{PJyC43KZp2ps0WXMKvf;RFeWlwJ1sK1w@Z+%}>FFWbJTv5a9@YB$YrDNwW<1&Vg3Kv5eC6t$&5Q4s}-iYZW3LV==o6ewy> zfuar+DC$UoqD~Yj>P&&6E)*#0N`azo6e!w*0!7^^B1QGH!bS&D{`rD#vG6b&V#Xcz^G zhEt$uFA5axO@X2j6e!w<0!8~$plBooibheOXg>-R?N5QC11L~5ngT@!QlRJ{3KSho zfub=KC_01!MTb(LXeEj#JHT+yWL@QAae zXfpGqXbM@1rjn&-8d-{_lci_|S&C+orDzseie{6gXbu@ghf$ztE(MCpDNr2PshW z5Cw`Jra;jn6exO>0!5Eepy+W56g@$Kq9-X(^b`e(o~A(2GZZM=LJ=uipB-;yKvE0+ z8;v(e(Y5{>?b+<4`*KAuW`{#oOVLZrm!g-+QuGR0ie4p4(Q9NWdYvpqZ;++vO|lfd zMV6ws$tc=NfueUPQ1mVZindXp=sgM)y-$In4=7OdAq9#)qCnBd6e#+H0!5!vpy)FS z6n##CqAw^=^d$v~wo{1|;>U9~b>7MRhzh$Vs{{SF}@3_~KeAYQlUe zYD$)(W@IU9PL`q;WGQM%mZF`>QnU+MidvDSXjd|dT2r8CHwqN(PJyB}6ewy-fubS` z6ctmTsDuJV?I=*xo&rT3C{Waq0!5uDP}G?MMO`RR)Rh87-6&AB2L+0{Q=q5^1&Vr7 zpr{u`q^MC&{3ipFdfsl$FqHz=`Dy2ZtcnTCvpg_??ibzr4oOo{o zlJehFl;|f#*LWz)NxCmrG&LtIy-bRxF<*+Nlci_|S&C+orDzseie{6gXbxG54kJs^ zT(T6ElTkE}0!8yFP;@v2ijJT_(UBA=I*I~CM^m8a7zz|Epg_^F6ev250!0fcP_&2w zMaNU1=mZKBEv7)x5(*TZNP(i0C{T1V1&U6gK+&lbk)p{t@skWl>RR9ZOp&6C{2*y* zPSSn3qSJH2tFDluGng+$XOg981zC#DB1_TPWGOm_EJf#%rD!EtidK=O=sYrt&Zj`p zY6=uxK!Kt)6ezlo0!3>nP;?OmiY}%=(Ipfpx|9M%mrc6gBZz`Zwex-Ipu6B`5s+ zDk<8)d?~t>EJe4GrRa9D6x~6VqC3e_bQf8Q?j}poJ!C1mmyDu~6ezln0!5oBP;@^9 ziXNaq(Pj!1JxGC~hbU0=Fa?Spp+M226exO(0!5Egpy&w-6g^3SqNgZO^fU#Eo}oa| z777$SOM#;2C{Xk~MWpDaoOq3^P0>#d=VmE7C;fsgC+WUi(JMJ&`)j4>Rpv|4Yh)>U zoh(IfkfrENvJ|~VmZG=GQnZyUMemTM=v^|3wo#zyJqi@PPl2KjC{Xkv1&ThRK+(q( zDEfo~MW0fj=ralweNKU*FDOv-B?XGMQ=sT83KV@!fue6HQ1mSYioT;j(f1T6`hfyP zJ18PWFXhBX8<5mChx4)&_4KE=A9IrK%N6~a6CSlrihg6h6#Y(?q9CPL?ot#ZOHl?{ zisED`N|2=}Buh~yS&EWm6lGDMD4POBITR>LQJ^T70!7s*P*j})MR^n`%BMh40R@U` zP@t$L1&V4>pr|$lit13Hs4fMH>QSJmkOD>ZDNxja0!0leP}GPbQuK39e60aVJ@5OX zU!-WIotJ2wO1dvs)GQU=w_b{xGhd2Ykfo?4S&DWhOVKW5DQZQQqFu>S)S4_syOE`6 zcQT6FP@t$S1&WF&P*hBTq7n)ewWB~$dkPeFpg>Va3KVssKv8E36m_9MQCA8Sb)!Jh z9uz3*PJyBx6e#LRfudd%DC$jtqCONT>PrzRYLbe-XFyWB`EgOxRP;)Jx$lemrIPN; z6%9&-;Z0IBnE6sPge*mSlBH-US&D{{rD!-=iuNK)(cWY!8bOw#eaI-Qgl99idK`Q=mIi|)=;46LJAbEr9ja|6ezlw0!5clpy*Nx6kSGvqRS~z zbOi;9uB1TGRTLBTLaHGK%h}K+yvfDB4Vcq6aBZ^biG#9;QIiBNQlllmbPMQK0B?3KTs-fubiV zQ1lc9ik_xG(K8e%+CqV%XDLwh90iJ=r$EsQ6exO;0!1%TM2a?~;=dS>RNUd*Dn$#^ zFW6E^_vMOSPlb){lA<@5FGX*XrRXiP6unKBqOD{pdWS4U?~Lfui~pC~81~qJ|VGYD9se z#uO;pi2_AUC?Z9_rQ)X;kkmGR!~XA5)XvUJG|f%AFIUtuH@s$}6z$A>DcXfBMXktE zv@2PPT9c({H?kD%PL`rJWGQM(mZBmuii#;vR6>EGb`&UTPl2Ki6e#LQfuc?nDC$gs zqAnCD>Pms4ZWJimg91g}DNxjd0!2M3P}GY8MZGCd)Q18^eJN1Xj{-&gDNr2Eq87Q)EB(5;76#@f-IpucGdKKllN1eQz7!23OVMz$6zxTpqP@vdG=eNe z`;et*U$PX9BumjKGK%)2K+*mbC^~=wMWZQDbRY$a4x&KO!4xPOLxG}0C{T1L1&YQ} zplBQgib^R^G@b%Q6DUwLkpe|!6eyZRfuhM2D4IfnqNx-pnnn>R8k`%ib-yVJ{kx7s zq{x5aOk#R&(tWw2*|}lI%~CXn`BHQkS&HV8rKp@NMgN1n`;3mN?%TeqM{){Xaa#GAR-C~C?X;j5ETmoVnZz0u@~&3VsF?RDvAXa_4)s@ zk8cvs>%P|gytvkLKQHdAb)GxNH`&P~^I zK+#zQ6fGv8=xhRt&LN;^2?0e*2`E}dK+(Ab6fGy9Xaxa9D+wq%kAR}{2`E}cK+y#R z6s;zp=t2UD)(}v15dlSO2`IXl5GtBo)j!z*Nz1W2)N`b$r;T-0W9G{gU0yXf>uD)k z&-qfcfh|Q>u%&1tTZ*n^OVL$qDY}|1MVr`CbPZdIu4SX>Is%HWC!lCE0Yx_uP_%`B zqOAlJZ6l!QMgoeq6Hs&$0Yx_xP;?6cMYj@AbQ=LhI|wMcoq(d91QgvtK+&B96x~HY z(cJ_T?IMJVF0JZc?|`KBwBNhFOp2bcaZlBl`7%WhR1F^ABSjB#z7##gmZIHkDSDVK zMUSwh=ux&5J;s)z$JtW!1Y3%pWTWUQ0*am{py(L_iuMpt^eh2I&k<1cJOM>75K#0Y z0YxtnQ1mhZMXwN0w3mRQR|zP3jew%p2`Jh}K+zin6un76(OU!*y-h&TJA_cteO3K0 z9FVj+cJp(;6g6}&i@sYmX1+|(hwk6AeqM?`;(RIE&z7Q(*;4cgTZ%qqOVMX+Df*l( zMPIO`=u5T~eZ@x6*8~)OLqO5D1QZ=0py)dSioPeH=m!Fd4iZrGBLPJ}5m0o9fTEuX zDEftfqF)Ip`i+31!vqxlPC(Hg1Qh*AK+zEbivA*?=x;)(=>4jGYX>B4L*U?iAVm%A zk^VnbW9G{g`RT#17o{kg{_jWn0b7ca*-{i^OHm42imI@sD3vWmX>2K~%9f&ZHi|L` zD9R+DC{938f`Fnd0*a~;P*k0Oq8bDg)g+*(76C=I2`H*VKv7)+is}(iRG)yN1_Tr} zB%r7f0Y%va6g4KGs0jf@M-f6rk#xV<0ZH3zaFWu)$7t2u%c4!wW9G{gwMY*xds&KF za=vbhj$untE4CE1W=l~HTZ-DSr6`vzMQzzql*g8$c5D>2C!nYU0Yx1NDC$H&QD*{* zx)4y*m4Kpd1Qc~Apy*fvih2-GbQ}RiJqal4ML|Xe?Wb#<8X71hy2N$VSn40*X!|py*@*icTS*XaWI6rxH+f8UaQ51Qbmqps0X= zqDcf4O(vjd3IRoh1QbmrplBKaMbil=nn6I(Oah8dC!lB+0Y$S3p`sz_{@)Hr+CsZ6 z8Y)HhZKCL$^qBcFMaAhsqt~UVg!84Slr2T`*;2HCEk$RrrD!2riq2$9(IU1KoyC@- z#cULvO+e8(1QabHplB%pMau{%I+uW=4MXLxXx`2S9)dUn> zNI=mV0*WpoplB@tMHdrLw2pwHO9&{sln^SKo9_2>K++D`&-CX>Q4_nXeOY?Ue3_yv z(u2Y`q-Z1OOVO2VDY}X+MOU+>XcJqCu3<~jwQMQ6jx9ykv!!S=8$~w|P_%`BqOAlJ zZ6l!QMgoeq6Hs&$0Yx_xP;?6cMYj@AbQ=LhI|wMcoq(d91QgvtK+&B96x~HY(cJ_T z?INJ)9s-K)C7|d&La1ncy1&{1NqgSD>$pLRcG@HT`_p6Q%M|TS4{m)+iXP^CDSCu0 zMUS$j=rOhwJtQ1m?kML!TwbdZ3e9|iGZR*1Qh*DK+!J* z6#Ys-(QgD49VVdYcLIw3AfV_^0*a0hQ1ll8MSl}e^bY|=UWOi+qbNcM6@8TM*L>G0 zy4P-t_Dj(_cJDeVBWAu#QF2Dm`F$yhalRC#u%)O9TZ&TIQk2G)qN;2uN@q(^23v|U z*-{i|qbNZ@Q5FG3)d(o6PC!u&0*Y!9P*jV6qS^!$)ghp$E&)aL2q>ygKv4q%iW(A7 z)QEthYyyfJ6HwHIfTE)aC~8VTQ8NOHniE1r(F}ir1CqAM-~<`rBYk&I+dW{*h?y@_ z)G8x5`$H*e&G}N4!p{s2y91+Owso16ztZvQgBDfTGR>6m=n> zs4D?Q-3Tb^PC(JI1Qhikpy)UPih2@I)Qfn|h?y@_G%_Q2a=#Rf;(RF@&6c7u zY$+PcmZEWNDLR2IMJKYQXgphrPGU>Z$!rvzLO{_30*X#0py)ILit-64nn*xV0Rcsm z2q>CNK+zNeiV6uRno2;?Gy;mI6HqjRfTEcM6rD~$(JTUrW)n~}hk&9Y0*dAmLPf(f z{I494v@Cm!HbRO9*}dy|88P!^isokoRX&xX1)MKMXRxJcAzO;hWJ}Q^wiKPkmZHUM zDLR`iMdz@kXbBrdO9?1iMnKWI1QabNplAgFMJov?I*)*&^9d+gML^L71Qe|%py)yZ ziq;TNbP)kXYY8a2n1G^n1QcCDK+&ZH6kSF@(d7gbttW(vN;3R54oF&EyDch}q7Ure z^@fa?`7%XUWdtKWm!hjVUy3%drRW;A6kW@fqU+dFbUj;&HnXMZ2DTJ!VN20gHj1_p zP;?^!McWA|x`}|In+Yhog@B@42`IXafTA4)6x~ih(M|%2?jWG(P6CSVBB1DQ0*ZDK zP;?IgMfVa=bRPjl_Y+X`00Bi05<*2AGyGBqByE&^*YQdz+G@8&4`sy6mnnKQBUt~X z6g|fIQuH`mik@Ig(UWW`dWtPYPqU@y8MYMdVN21oY$}8uFxY=^tS!_?EZ|H`7%YHWd!eiEk&Pmz7&1ImZC4& zQuGyDioRw`(Kl=<`j#z42iQ{d9b1aNXQSu`0*Ve2Q1l}KML!WxbcleWp9v`Xg@B@8 z2`KuFfTF_$6#Y&>(H{g9{YgO45dw<-BB1DR0*d}2pvcSA!*&!!2q;P-pvWhnC`t$w zeUjmO-#A5g8=Oz2sL)6SnKAQaimGG=jSomsD(6d48e590vZW}UEkzk@DavF^QJgJB z3APkvv8AXQ8%5O#D5^m~QB4AhY7tOWn}DJ^1QgXJpr{@JMfC|NYCu3yLjsB#5m1y( zKv81?ikc8mbQA$aO$jJ!MnF+>0*a0%pr{1_MJ)-TqFAOszyV1+-|h;fWQLFQFEUcc zWX8;wDQc4$O#5Dnayeg$+Onl6k1a***izJ>oytbhX#^DI6HqjffT98diY5_IG?{>+ zDFhT15>PaifTC#x6ip|fXa)gAGYKd(Nrw*lvqTGh^n<6fMjQ4*euWXL7z2En-X2S!^j<%$B0F*-~^4 zTZ)#jrD!Qzik7jZ=v+36mJ?94f`Fox1QeY|K+*XG6s;nl=mG+YRufQkApu2e2q?OU zfTFbo6kSX}(K-T(E+L@kQUZ!DBcSMV0*clXP_%)7qALg}+DHf$Ey(n1A99N3*w4|< zkfICi7ay<8jF~S}bWLW^^%p6+mh+|PI<^#D&z7RiY$>{dEk#?{QnZyVMcdd?bR%1e zwzE-m69Gjx6Hs&u0Y$eGP;?ssMLP&6x}AWcodgu!K|s-+1QgvxK+)X<6zw9Q=pF)! z?j@k;J_3sFC!pv70*W3apy(k2igpuF^e`b*bakeGngf#7!ETE-Nzp|6iuOom%zT-m zCo+R2ze&-PoG(RBv8Cu~wiG?XmZCjuDSDPIMbELN=y|pjy}*{D7uhI!iGZS)2`GAn zfTFzw6unA7(Q5=0y-q;UJ_3r~AfV_?0*c-upy+J^iryih=v@Me-XoyseFBO;AfV_& z0*XE&plCkOaX`{q8k{erXq?>^rNm?A%M?|O2Wdy7D4p}AD1$9UnQSSFv!y7(mZB`S z6jftOQFXQy)nH3eO*V>Z5l~c{fTB7C6xAi5s2%}D^$93yKtNGL0*V?DP?SwTQDXv% znh;QQ6ahs|2`FktKv8o7ijF3rs09HPXda15m3~dfTBJG6!j&bs2>4E{Rt=qB#T<6%kN0mw=*q1QZn$P*g%d zQ7HjM^9d+gKnN9$jr+SDkhE3yqqA{Rlx~mo&xps&mnk|c9(<4_MT zTEdp1rEDo$#+IUU*;2HeEk!HXQnZqdqVotSI-h`|RRk1WKtR!I0*WpqplA&NMHdlJ zw3dLPiwP)NM?ldf1QcCLK+$Cc6kSe0(Ru=kHV{yB1p!4H2`IXffTF7iD7u;uDmpXn zC;3j%2>agkA}N}0w?&)cG4o}Lu8#*txxWsg?6zn#=S$HIY$@8pmZGg}DcZ)Cq8r&# zw4E(QH?gJYX0{aF!bZ`p1QgvyK+z5Yif$*MXeR+hcMwo?Cjmuw5m0nD0Y$qAD7uG$ zqI(G_x{rXO`w1v|fPkV02`GAqfTG<56g^Bp(IW&DJxV~)V}wxAwQ+xt1CmzTZho$l zqVD!&2r05yWm!dsvDSDPIMbELN=y|pjy}*{D7uizu5?hL1W=qj4 zY!vM!py*Wsie4k2=yd{$_7PC@1_4EH5>WIO0Yz^UQ1lJ~Meh<&^d134?-Nk;0RcrH z5>WIJ0Y&=>DEgRyqE84Y`jmj8&j={`oDeE{GVZT+K+@uNTlAC^ZLxdTU&LeP%M^VR z4|Z0OqHj50iVm=)=sUI)eb1JnAJ|fKkS#?&vZd%JwiF#=OVQ746#YU#(XRv){YF61 zVFHSNC!pvL0*d}5py&tzMSl@c^fv)T{}52*CG@ZzMG*puk_agB2`GvZP!teQluSTT zjDVsP0*a~-P?Smt6@3-=_cJ zRE;e~)!9;1gDpih*-})CEk(82QdEbHqPheW)gz#&J^@7y2q; z69S5kBA}=#0Y%LSC~8hX(a{7HwIHCVB>_dp5Kz>LfTGp}6y*?5)P{hfTtcWQJ>l1_ z>J&X~-*wDLgpc$$+HFzWM9h4dq7I3mdxjKsx)R%ywegqWtC!lBm0Yw7|C>lgS(eVTn4JM#y z2mwVy2`CyyK+$jlibfDnG?IX#Q3Mo?CZK2x0Yzg8p`vyPf1(4DcB$PJYA;1ecJF#z zB4)l!(MgG5SzL-v=6oqSg)K!B*iv*VTZ&F&OHn>siYBt9sDLd+lh{%;nT?_;1QZn# zP&Ac*qG<#aO(&pe1_4Dg2`D<9fTCFh6wM}}Xbu5IMFbShC7@^?0Y$|G6qOKAR7yb6 zd;*FV5Kwdm0YwW5C_0l6DmpRY-{^p(?X=sX@ly1feG76?B4)l!(K(4=PnHxd;e07t z%9f&KY$-aIEk(=OQnZ3CMJw4-bRJuZ&Sy)}DmIEPAfRY90Yw)QP_%}CqKgP9T1!CD z#RL?sBcSLK0*Wprpy)CJiY_OhXgvW%8we=6f`Fop1QcCKK+#nM6kSa~(Ix_lt|6f4 zT0*F3al${~fTX3{&Cl6VG}Fd)iJ18^MOzXzmb^?la5>Rvp0Y!HbP;?goMRyZWw2OeEdk84Hmw=-C2q?Or zfT9NoD0+~9qK615+D$;w!vqvPLO{`@1Qb0+K+)p_6g@#e(UXKw(dLBT&H+iQZoj>M zgB0zt+oGouG4o}Lo=pT}YDv*^oG(Ssv!&<-wiLa{mZF!~QuH!gie6z$(O$L`y~>uN z*Vrg}oq(c!1QfkNK+&576um`2(c1(Ry+c6Jy95-yM?lg01QdNhK+%T;6n#WM(S8Do zJ|>{(69S4pC7|dt0*XE-py&$%ioPVE=qo~~=$VAS&;d!?XOHyvNYNkeWznw_G4o}L zzDopG){&y`IbVu?U`x?KwiNxymZG27QgnzdML)Bp=ohvW{mPc2-`FTROhD1^1Qh*2 zK+&HB6dfU;=r00_{wAR49|DTJEIn*TQG|e^Bm#1(tf3Tj;e09T%9f&TY$@u_mZD?XQq+Sj zMaQwFs3%*Bda=&2BcSL60*X!~go-+5`GXyhv{nYElN24W z+oJJVG4o}LCS(PtyMK|m?B{5wa=sLu#+IUdwiHcdOHlz^iYBq8Xfj)hrm&@`kS#@1 z*(jPuK+$vpie?Z{G?Rd$(+Mb=ML^MP0*dAkP*g-f(Od$G<`Ga-Oh8cy0Y#+*6wN1~ zXaNC5XAn@dkbt5y2`E}bK+#zQ6fGu%icZe**Et|*gAL9pQnbwOYM-4IGhe1?Sypgo z6Dc~E^QCAxTZ&e&rD!Eviq2z8(fMpCTE&*43)oV$nk_{avQe~#fTD{CC|XNE(ZvK5 zts|i55(0`YC7|ds0*WptplCe-MH>hxx`KeBjRX{3NkGw61QcCOK+z@wimoA`=vo4b zt|Or6dIE|z6GBBxvivt4khCw{j4qX;A8g!^6*FI6rk4~ws!HSL5ih>O{m9mfzhdCx zKe}&Iro^kcM{`x<9o=2?c>Kh4&#NB4I@9xN$3ISZUj6vd)jcmeKD(ypHI3h0+w)q) zf3NF#t>Zl#cwXE1%0`~oA^t*R&+8ITH1)h=<0m%vyk7BZT6kW+_@~Es-k^BP9M2mX zFUs}2k@0)-Ja26L&-R`-KHj^N=S_&8-^KGL#$W2@c~j!mdU)RS_(?rIZ&v)e-kvu% z{&`=|D~-1r;CTz<^9Fg|;`n`oJ#T6Juc4l|BHnj|=dFrgFv|1R#9tZXdF$dePVl_T zNaBra-IWkY)Z6T?g-D`ci@O>kiS66m z^$VwlCXb{yhS8o|DJT~NW%U>;I@&3{fn+0A_@B^IlDv>_HQa48%fwdiq|WW zuz%I8UnF7wEY+Y$!v0;Mp^?N7kGbn4lCXc-V{9a0|1`t+NW%VZ{RxqT{pIKrBMJN4 zt*1m1_SX|nk0k8xmz@G1#JWhr{!9PMBMJLYwKql*_TSoWiX`kmmb^Zau>aa^Yb0U+ zxzbIMg#Gs>w?z{69}L_PN!V|E?}{YsS9b4@B_T8_~A_@EU#aEGpJ^nlp zN!SC3gOP;Y1N=FXurJ|H5S>aT{4!Jz1lkW=P}Y%FFDG+he$V# z4R%giwkn6mdwp9DW05LoL@4zFn?}wQEB1i(!wdZlZ(%sTUumca^aNu z#f2r6US_ZFUb}1V+~OItXOzxZQ0V1OFPdGLTQI9|VQ!mQMUx9=<(5n@C@#z`E}TBzM~6$@vAvvvc#>=C{vp*S1|=eqLLPIWFeR zDVkH5Q&=!*MowPaHtlol#ckY+|MjBW8FMDjnm?s5cXq+#=`-g1AHNtSXO>j{OiY`e z+q-zm{26nK`W6)z=9GUf7M2#5eM-X5$jIWNneKC5k~?N@LGkGW=FiC=>pqrgBWKMo z$sgUj)3A>J6IauMg3?0!Yz%oKi^%<$$g7v&n}wdn%yF~Tgae{qTfCe1l9h#ry!E-Pm2Uue%?3L1HpsG% z>))^ZzxX)p693d7C|KiWb z|NS`r^UueBy&l4wz9GT?53Y~v|Bt!K4H`H3_pSB+_6tc?a;>0R%OI;=P_2HYuOSnbr*tfTf1OF~ zE8cIr^7q@f(wo!;Y{v|L%RcyQP(`09}p_ z6&KB2+2N~~e=MkKTk)ZEEx*`#4y-q%|4I41`;9I;&s~rDh@4kF*Y96vdb5h=Ov^6& zzyD$?ui}FA5gT;5>#Xb@z^NQe$kYCu^)EYnrv1?(*T4is%>_rZa&T?Nj^j!I8$)OI3u zV(#m)d;2BRi;7FjzXUqTT#8UsIi~V2*6z<>*{j$UUdGdXHo|8r`Ks`gR{<)oLKIhb zp1ZJRC%doa-spV0j`f)@t9IpvU5hX%g%A%xacw2U4WdavkOZ~3Z@n2 z%qpBSt#o>iwl0NtU2@ETTlP6Col!I=r^I~&#vMysn^I6(P`<-Yh5Pa!K2rfWuR^fl z{O`Vqg-9!Xp)Hr_B$vI-io1bk(>}))_XaEO1LlR?%dS&*!>@}~aSes$%fE`25zo*6 z_m_C?gjU=K1(Drr8Zlr@`IqiI?s8V#eXO|GSaGM(-Tj15_-Dc{Ub$-Sa8}$GtaMk9 z`%|Z(!fP-LhNQADrIB zv$Olpo>Vwxio1V3mhY67{aNBWpe_IVKUwxo->U9^|G1}!m$W#eYPwh3qMqy;Rbq(-EcUprDK zQa4gBQa{o#sY#@beGBc`W80Hx9>4ldh*@(7Za7XeY4yB z^w2vTe&^dgrB%qqtX2fy zbDz9QPretgwCo%1S^u&B{n7aDqj5h1DEq9~b&_S@PyNsD%Qh|bnojwT+je)3{fH>Z z{kXuc=Op)T?Je7}hK}yX4PKJFc#Z9t>3J>G?fSLXb3ZFBJG!5cmL2=(I8w)PI!@Mc zrjGM;bU&*sJ8y-K>vY_r<9+TrviI|(j_pd+c9?)*s+280fik~>e$nL zY_^B!Sm1t;Y_T4%jaGwC%zw6k}L9yLa$A#_(&bC+T_=x)hVfzIgqxHg_ z&~dQ)akRbsL><>P3imZSzUe-(_VQ14tlu=;Ep?pKJlsV(-sG+Td;NQK{Qj75|EXgK z_d{)ad2byTxhu-{`8qz97w(sIOzsfwYB~;eSE#-INjhHICEVBP_;$B&f39Ogcg5T5 zx6*M+&v4Jv@s{4-g@NaDS;|_6gz6(Q)edaF^(K+sWa6K*ygZg!>;IyX1$vzmDe=g!@7rpK{Rc z^YN;VsZ+yUOUIGZ!+olb8)k-ki;nNl3isDKHYo~su8z~^g?qk^x0i(bAsv67AMVJ4 z@Yro(cpRwX(naCENXKUuhx>IMt1bz59UVt63wOSb8<&TBn~oo@4EMJ>HeD6&JRN7Q z4)+;4-mxa!59|2r+Hm_9hsR?t36IC?c*qTin{N(xdmU$O3HO;g-nA{uP4LfFdff(I^37(_~M>$zoTQ;^Wko!wb5|b`KpFWQTjXj=SA&v)Id@)3J&B-7wp^I(D*S z;J&_T54B@e&l{=ZIQ2<77U{TH#|w1apyL)D@6hpK9iP|nEge78(cSGRd;cjqX6jf? z$7DOEx?h*lc89Xp=e&t_KgL~tcXz@|O1NL7;`Q2;oH@I+V3OCSq_j9ZPUkuIxVF@5 zV-F;~Hj_$9yfzlv{QF^g8~1Ry%@q5ltou&*)FSulWzQE(np9l4z^n99_uCYeXF+kn zoN0ybZC0HBU&}1}T?oBJccHvClid&Q3*EQtE1fm9xL~$>rQV~5wJ9hqEuJxHeyMx2 z|F56i-6bbHygzCuxw|9(dUBt(vZu!G|LyhsaQ>IqvzOV^(e8hC9sTcKueE!f|9ro8 zADSn--t4KL`yX%H_CEJIKRFXT@mwz#++9!4j`q~LU&L$cLJjx4yV~uZdD-O}>5iP^ zp7owNCgOe_&YlaOcy^MTJZ~>aZXNNOg|AZf|Gexpw<^Ei3Bw{@wrlo&?eoC)G4v`@q{Lp<60wWoXC|0-X;t(87r zdo;)8b6;l7=v;Rwds^t;UN?q2+WWO9JMw41_Ad8&BVDZNp10c)dwceIxA$3zuNQUx z{#RbyP0znxZ!j3F7ro;-YDWcdH-_I$Sc-$ZMAzE_o@?zvvJ=I(a?@45fQ=MMDZHG3^>@3qZ# zkIj3zkF=Nj)3?w4c@3|hXyglrrD|RGC$dB3&#JpnNs;6+_E<5JQsA5?B?a%r>=4U$ z(XZ()aMG~a?y-ma33c#`dx>9UuQj61#Ih87&wc)rQUZHeos<%*=dOupG_daxZJyI1gASLY?f9+kbcW*K|8f_kIcQ1?C-?@0S{yVxxZsvK> z7Mcy+Z0AK=YBq4Qz591QH0!(B!Hc%itmkG&FWOqOuA80QUlpoZ$IZ@Ow2fwMH@kSz zT+Lc;c6EQ-h-OVU^W4SC)2?CLU9NW8)or^A)?T}sZFk8!XlL1W7p`7m#?q3``%EWcJA`^(@t``y}Nww7^Fm_P5tNG^W82*;n2;gCbB=PEkfAzNLWXHd$Z$;w z8KEg5BQ+&tl%|A?)|8Mjni4WrQ$ogRBIE>Zgq*02kn!3GIY}EKCu<|*6m5h|&_>9q z+6XyK8zK4H2$`sjkOFOlOwvZkWNm~@(MCw2HbSOqBV?L3LZ)jYWQI0EW@;nkbnQ^c z@&32&`mb`iyP=5=4u$k`w@}epF_U9L<_6!o7nTW`r&A@QSW`kuG$o`|Q$przO2`6D z2{}VkLKbRD$eEfFvPcslXK5p3u{J`^)<(!V+6Y;qjgY0<2wA3$kaM*WvRoS>E3^@^ zQX3)XX(Qx(ZG^1SM#u%)2wAO-kPEdDvPK&r7ilA8tu{g~)<(!W?NG=ZKi%DARIz(& z(V|eu%Z^6$l9Gxl&U?uF{l{t2HHLlct1RqbVWR zYD&m;nh3dG8zGyu5pshzLbhllWUDqpwrL~eMs0*_*G9-q+6cK>8zHx7Bji?Xgxsc$ zkR93xxm_C}JGBvVhc-g))JDi%+6cK@8zH;25ps`qDC9Cf*IoZrPPf~T%R?b=+4J|t zOpXb8FvxW`DrG_*(y0=%TT?33*BrAx~=~ ztmyIUS(H*nkCEl*+BciY`9ufne9w!2%N%C76SyIY>duH&}5TV9o2 z+iiEZJe^(3ZFjdkgI&{Ydt8%AsA0if!Z@M21$Pk>glZPtWy~UES#TG!8X;l9UCQc& zxCM7HYY;LmxXW3SkYT}H&{~9a3+|HECRBC79^up>q*-v6v@Rjlg1e;k2vsb&OIn|h zV!>U~285UecS#!(k}bGP+K3QXaF;Zj5VhbgX=8%>v3A)*ohF1N7woalQG|#EcS)NP z9FX*AG%4ag=zyedw!0^OBvkaG-EV0Yi5V|b)G`vh=e}uCrsx>Xm!ei|DQeA@q8zpq zwP8z9E?bJ)vZW}GEk*6vQq-P}q7DQUbtIsu69Gk?2`K79Kv7o$inO(+LUjmBy5m3~hfT95e6b&SxXb=HK#}h(DM@PzjPa<`Z z-4wNuqTNPna3p5FOwn-nA4|D!mz60R!TC}&k}XA}*itl_Ek$G4QZ$w=MdR2~bOKw7 zPGn2bcs7boBB1DG0*X!{plAXCMW+%_bQ%Fg`2-YAB%r8(fTBqR6ip_eXbJ&Eg#;8$ zC7@^;0Y%dZD4Ib)(M$r0PA8yf76C=G2`HLF2o(*D_yZh})Lm{yhe=TbBUKcMmHi%$ zQ&bWOrnzstmMJRbd?}jGmZAl0DLR8KMGM(dbS7Jh7O|!1EVdLaW=ql8Y!sbCK+zHc zik1>kw2XkFa|tL~PC(HL0*Y1=P;?#vMduSxw2FYD3kWD$O+e9w1Qe|ypy(n3iq;ZP zbTI)%>j)^ign*(;2`IXZ5GtA%@z*#Ysp;;KcC=WER+l}_ip0#9-4<<(1UuZ1|H>3y z$@x-r6T{_fT9}-DB4ay z(M<#t-Aq8yEd&(ZN zdV(!QPqL-xDYg_n&6c8P*iy8IjiP4>D0+^7qUQ-HdVzqV7YQhOiGZS)2`GAnfTFzw z6unA7(Q5=0y-q;UJ_3r~AfV_?0*c-upy+J^iryih=v@Me-XoyseFBO;AcTq@iukqN zPuEiq+5`99QuKt~yZ$f|Ghe3YlSt6j{f1)MZPBNkFGZiRrRa0E6n(*#qA%G}^c7o* zzGh3&H*6{TmMujG*eLprfTHgSDEfhbqJsn!{YXI3PXrVlBB1DJ0*Zbipy*cuihd)Y z=r93AzY|dO2LVNY5>Rx6fTF($DEga#qJIb|@{-CQ<%f^aA_NpA5kf`#BmQX)Na_Rb zN2bw_rRYh!E%K9M=F1etl7c0Tq$q{+rKk#9ic;B9l*X2#s%$ArXG>8ATZ%H-QWR%P zQG$)4ECPzE5l~c}fT9`%6xAf4s1^Z5wFxMyLqJho0*dMpP*k6Qq6P#MH6);@5dlTn z1QazUpr{D}MMn`()RcgtW(01FniEiTG$B+JB>7t%kkr%MPv4`-N#P^?`|Y-cmD-X99}45Kz>W zfTC^$6m=({=vV@ZdJs@_905f=2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS z(eVTn4JM#y2mwVy38A86lKgKRkknN7dpyxrQsmns{b5Nl^JR)gB?W0srD!zgOVJp% z6pdv|(Kxmgoxql&6WLNUo-IWuv8Cu_wiKPhM$rTUicTe<=rjU~@(C!KNI+2m0Y#Gt zD4I+_(G&uT3JEBhN;G} z8j<9;bwE;w*=^BCDe7lm(TbB|=F1ctstOiB>_d}5m0nK0Y$3_D7t`vqSXWxT}VLD z8Ul(gBA{q30Yw)RP_&MKqDu%Ux|D#T%LpjCoPeVB1Qcx`go;X&`~?n3>e2QsqWMyE zv)vY5krXpurs(RV;EEPfw2AYj=o+>ZUCWlD>)29sJzI)4v!&<;wiIn)OVL)g6m4Up z=tcsHwi8fv69Gjx6Hs&u0Y$eGP;?ssMLP&6x}AWcodgu!K|s-+1QgvxK+)X<6zw9Q z=pF)!?j@k;J_3sFC!pv70*W3apy(k&sOZWhf42jYx-R12TqQ-_?6zokQp|jrqQ{bg z4~~(d$2nh$o?uJSlWZw^iY-M?v!&=6wiNAQOVP7zDSD1AMbEQQ^a24zFA`An5&=ao z6HxRD0Y!TWD0-EEqSpv0dYyoxeFPM}K|s-)1QfkRK+)R-6um=0(Ypi`y+=UN`veqy zKtR!l1QdNlK+%3esOXU-KdF^dbe4VB@lh$tv3u7aC&kQ{Df&DqI4VbqzTkW*`jRb0 zU$Ld=Yqk`9!Aw#g?LKY$>YFMo|p{ifR&2REvP3+5{BUA)u%(0Y&u)D5_6DQ3C>s z8WK>{h=8JO0*V?FP}GEgqN4~XYDz#+GXjd56Hs(C0YxncC~8SS(J_QjQHt-cbwE@eQ_~9e{+wHcfl^-)-rYP4BcIHV@Th5oFJhl|IV@pwcwiI<>OHoI*6m?=tQD?Rk zbzw_US2l{e5m3~ffTCjwDC$8#(QyP6^(3IE7Xd}R2`K7AKv7=;iuw^y)SrN&0R$8c zB%o*z0Y%3XP&Al;q9Ftn4JDvx7y(7Y2`Cyt2o>e{{yqmJb+X+RY9mEo*lp2BKW4s6 z(O5tDrM(o5<9sPPfh|QRvZZJ|TZ&F%OVP<}DLREMMHARkbShhlPGh4epMau?1QZnz zP&A2vqR9jlO(CGDkbt781QbmpplCV)MKcH}nn^&>=>!zbBA{qC0Y!5NC@LbLXf6Ro z^9U#^CZMQ5qO;gi zw3sbLXS1c~9JUlKVN20cwiGR6OVPP(DO%1((Fy{JRuWKj9sxz?6Hv5@fT9ZsC|XTG z(S-yQts$W3A_9um5>Rw80Y&QwD7u7zqDu)Vx{QFL%Lyo2Pe9QI0*bC6plBljMOP9+ zMQ8Z_LWIO0Yz^UQ1lJ~Meh<&^d134 z?-Nk;0RcrH5>WIJ0Y&=>DEgRyqE84Y`jikVdffL9I3TIT_Fcy(q$pvxMW6XG^JR*@ z@`H5uxAK%J`kM2l=o_{aean`j18gb!jx9ysv!&<P}G8eqLu^{9Ya7-D*}pI6Ht^x z2ocWlaQ(NF@4h7nLSoPeSc1Qd-VplB2UMWYF!qP9{05eFo7xtq~E zDSF>-i^fD_=F1eF7!5w^D@EfuUy4p*OVP<}DLREMMHARkbShhlPGd_^K3j?=vZbhi zjiN~e6ip_eXbJ&Eg#;8$C7@^;0Y%dZD4Ib)(M$r0PA8yf76C=G2`HLFKv59^MRN%# znnyrUF#$y-1QeALP&A)_q6GvLok0i{jf?uxeooO>_Fcylq-dMn7A=g%%$F%z91WTc zkfO6WUy9CQOVJXx6fI>-(K5Caoy(S@?|pI&3;YfnrO^?nWD|n;PgRKbOYy0(H6E8ZDmW* zHntSq$d;n*Y$>{lEk!r8rRWy66y3^3(QO12?I57&b^?la5>Rvp0Y!HbP;?goMRyZW zw2OeEdk84Hmw=-C2q?OrfT9NoD0+~9qK615+D$;w!vqvPLO{`@1Qb0+K+)rbP|?_(6(U|!%MbAWoI|obA9?qAdXW3Hp99xQ>XG_rwY$^^UBcSMg z0*XE$py)#aiasKsXg>i(9}`gY2?0f)5>WIR0Y#q^Q1k^MRP~zX>S%hkzn4(8G2VMF=QLBB018peRZ} zQ9wXZG66*~0*X=yD5^q0Q7QpNX@pSG*HORzFsJA&`!9*Uk)rqQD_YecX1+{OJP3M> zkfH?VOHmeEimI`ts5)DUYOtlKCR>VXv8AXsTZ-zirKm0&MfC_Ms!u>s0|JT~5>V8L zfTC;yiW(D8)P#VdqX;N!N0Yy0k6ty9s zD3^euwuDeoM&M6!KvECeBmK-Ee5Ak6e%UB5h?y@_)G-K_kCLKJoG(S4*;3SnEk#|~ zQq+wtMcvs_bSztnda$MFIJOk^WTU7T0Y$wDDC$E%QC|Xz`VmmnpMatP1QZPQ zMaL6RG?;**Ap{f+C7@^+0Y$?JC>lXP(MSS{MiEdnnt-A)1Qd-WplBQ+RMbB3Z*o9V z<974YL5eQ2aY7I?U#95fAb4(!6rIBPQZ#`rMW?c*=rpzz<+G(|B3p_I*itl!Ek%>r zQZ$8)qCx_SrV>yzjew%*1Qg96plBumMW+)`G>d?u*#s2LA)u&;fTFns6wM=`sF;AF z5(0`!2`HLRK+ysMiq0UQXdwYbXA)4fh!83oANb!pAgLGGU7?et=xV!@bXE{EU#4hD z5M-VpMN2tfik7jZ=v=lGEoV#73bqujWJ}R`Y$-aQEk&!?Qgi_uMXL!Yx{!dPH3Sr0 zL_pD60*WpsplBTdMVAmzbSVKvml05OIRQoM2`Jh?K+zQh6m2A+=t=^Lt|Fl5Y66Nj z5m0mu0Y%pmP;?z3RCIRWcW^*b$J@iQbEN1|yDhpth?y@_v^5CEjhCWroG(Q;vZZJ{ zTZ(RCOVQ12DY}I%MYpo0=r*<#?O;pM?Q9h7B%tUH0*dY=py)0FitZ+$XcqxR_YhEY zF9AjO5m0nL0YwiGQ1l=HMGp~Bw3~pUhY2Wpgn*()2`GAufTG6 zXfIoeUS&(sYiuccosFV>1QfkNK+&576um`2(c1(Ry+c6Jy95-yM?lg01QdNhK+%T; z6n#WM(S8DoJ|>{(69S4pC7|dt0*XE-py&$%ioPVE=qmz>z9xi<_5}W84oIr|hZwx* zvr_cDk@_ZxnJ-iHeGq&+L5hChd?`A}mZBfoQuGsBiVm@*=x4SR{lb=_U)fUh8(WGF zvr+Ur0Y!fhQ1mAOMMnrI`ip>~zX>S%hkzn4Sr6M$6d|A}iGU)XfTAb?MF9at$pjR| z2q;P+pr{G~MX3Z7r4dk6m4Kpj0*W#Sp`rtUpM0uQWIuO}ekVn*+Qa_LV8LfTC;yiW(D8 z)P#VdqX;N!N0Yy0k6ty9sD3^euwgeRA z5m3~QfTH$V6rD&w(Rf0rs8h0k zsRNQa)4qsxmZEL;fTG0&6rD{76`hjozwLmeUSi*MoFGN>>?_(i z$uaX~iq1_AelL`w<(w}?E7(%Bk}XB&v8CvIwiK;mOVI^vDO$~zq6^tlw1$nMiwG!M zOF+@Z1Qe|!py(0;iY_If=rRI|E+?R9Jpn}<2q?OOfTE2A6kSO`(NzQ#T}?pICIX7C zA)x450*bC9py+x6iZ&BabORw&v^3doIMpe7!fuO}Ns(XnfGs&@zD&{fqFdQgbQ@cWcCe-BcD5AlWJ}Q{vjiS28(=qUnuP;`J0DtbQIzr_Jb zy~n|y_R$uaX~ihfKEUYI3CKXJYk9b!w-&ul6Bg)K$DvZd%ZwiF#^OVRIa zDf)vgMSrqUbcBGSzX&M$n}DK!2q^Mmdf1Ml2mwV&1QhuM6h#Rr3J54lCZH%rKv4<- zMO6qWN+qBujew%61QewcP?SMHQ6>RJaRQ1Ggiz5B$^JnHB=r%y`8g;>m)gDStXRx^ znWCDpAW8(YED4W(F7E=AfTuv0Y%3UP}GWmqSgcy)i{7w!?YCU_TUn3Si(*NFWm^#N|=F1dyj|C^rlcHleUy6FL zrRX@e6!m0FQ7^U>^=3;^AGQ?rWlK>%wiNYeqi6sDMFR;a8bmlmU(QpEaMi5Xml7OO71Qd-XplA#MMPmsl8b?6U2?P|KNI=ne0*X!|py*@*icTSf zin_-9#STcS`$w7GKgB0StL(ODLM&#!Owq(xa7~F66>z>3O=3&YWVRGdVM|dVTZ*Q# zrDz&kil(!rXa-w~X0lOqIsrwq2q>COK+zlmii!v*noB^@JOYY}2`DNdps199qWJ_A zEg+!i3<8Q45>Rv|0Y!@lC_0OPqQwLholQW|IRq3fA)sg}Ayjl)%zwfGNv&ZI%krhD zk$rhv7K@oLQ?xP`d^%r>&f|P3I-e~?tJqR>0b7bzv!&=lwiK;lOVLGaDO$^xqKnxm zT1P<9B?J^*NviZ&2XbOixL8wn`7l7OPC2q?OmfTB$V6kS6=(X|8= zT}MFC^#l}cCZOmB0*bZ}P_&hRqHTmw(ejv|vcM_Y>}GU@6m7AuXg9`U=F1e_5(`=` zl%iWXUy5#HOVJLt6y462qMd9hx`Qo6ce17EF18fi&6c8FY!ux?K+(Mf6x~Na(ftGz zJwQOwg9H>kL_pDQ0*W3cpy&|-iXJ7P=rIC{9w(sa2?C0qB%tUi0*am{py(L_iuMpt z^eh2I&k<1cJRwwcQ_LUkfTTWS|84BeQgou-7QGOQnJ-iHN-QW^Bt?5UUy5F3OVMj= zDSDkPMf=!N^afjs-egPBTWl$Mn=M7}uu=3b0Y&c-Q1m_lMIR7Q^dSL79}!TrpMau| z2`Ku6fTB+cDEf?mqR$B^`htL>F9|66ih!c82`Ku8fTC{+C^|qu(RTzCeNRBq4}?(B zOELd)2PAcv-4%LSimtTVqJy!R`7%X6$AWtnOVKZ!FGatyrRX=d6dh(u(eG?2`hzV+ zf3l_M2wRH&VoTBAY!v-NK#`ZChwUhe5KxpvK#@;CQIvq9fPkW80*Yb;6r~VQRE2<| zR04|92q>ybKv6mYMHvJXWfD*nC!i=nKv5O}Mb!u>s!j+M{S@=xbwE<5+ApRZlA;tN zRU;*4zD!Y_l;F>Eq^K_EOHnnrRXR&ikcEo z)Qo_l<^&WSO+Zl#0*YD^P;?9dMXd-ZYE3{<4gp1N2q?-Wpr|bYMR^1iwIiUYJpn}> z2q@}EKv5?GiaHZe)P;beu7prgtrS0diBoi${gQ0$l<<*$4f~4LEhT2YOwn;ELGNW! z)RXh2s25v`db6dd4_k`*vZbgWTZ;O#rDyAk#}iOAn1G@o1QZP=plBEY zMZ*aw8bLtONCJvR5l}RmfTA%36pbaIXdD4WClF9{A^}C?2`D;=fTEKLC_06Jq6q{P zok~E_X@pSGu_^vk2PCz-!RaAIbM3Y$KP6_qOwr_&;QZxMG==k}sE{p1Q`u59jV(pf z*-|uvEk!fgQgk|7ie|B;Xf_)~a|kFZBA{q40Y&o&C@LnPsDyx`QUZ$R6Hv5(fTA-9 zC|XEB(U}AkEh3=kECPxa6Hs(E0Y&E!P_%@AqNM~BEhC`lTmp)g6GBA=DgJE^Na_#v zUB^jMlxCz>q{PgZDO!~hytGn^F5rAATFsWC3)xb%hAl-Gv88A&TZ%4bOVK*E6kWoW zqD$E*x{QFL%Lyo2Pe9QI0*bC6plBljMOP9~bQJ+bR})aQiGZSO2q?OifTHUND7v12 zqRj*p-9SLm76OX45>T{_fT9}-DB4ay(M^O<(RnHUPYy`x?GXp(d?`w`d)GIo#LSl| z+L01eTO~!ebG{VqWJ}Q{vEk$>+rRZ+96zyV5(LHP_x|c0Q_pwoQKLJG#5K#0W z0YwiHP_&zXqK646dW3+YM+qo;jDVuY2`GAkfTAY}D0+&3qNfQcdWL|aJp>dzOF+?c z1Qb0_K+y{X6un45(MyC-(XA;m0RoD?BcSMe0*Zbhpy(h0ML!Zy z^b;Xev^T{+#{qF)&m5drrD&~vBl}QF%zT-m-%^6>)=1G|&X=O!*;4ceTZ;ZONnP?StSQH+416atE>5Kxp#Kv5b2 zMO6tXN++NwgMgw;0*c}U6eS2K$|9hs8UaPs2`H*TKv7KsifR!;MZcu@PdOl|r`jFr zU!~}0yDh3+C1$=%QT-~x=WC^?0q09mL$(w(VoOmrTZ$U9rKky8ijHDSQB$@QHDgOr zb2f^OCZMPV0YxndC_09KqE-YHwI-k_hk&9s1Qg{GP}G)yqC5hM+7VFHo`9kb1Qc~7 zpr{i8MV$#K>Ow$KR|1N<5m3~ffTCjwp`yA~{M3t`q7wW2i|SPgAL(zm(W6Ste3_!& zRf1NRNKqfom!iIGDeA|TqW)|t8o-vKfov%n#FnDt*-|u^Ek#4vC>lyY(J%svh7(XU zf`Fot1Qd-TplCD!MPmpk8cRUYI0A}JAfV_(0*b~HP;}D&L)?8wM^*Q2+uxHtJ3}UA zCZP)|2qGvDLI**5k)l*ZMM8kk1OiDwnu-Dz1VIr&#e#^~D=I1~c0{b$MaAAwv7o4^ z&+j|?Jd#}3z3%nAe>`iwtff2Wk?ds1e3;B6BoI(^Isrvz5KuIlfTA-AC>ldRQ6T|E zV+klKB7};%W%xrJka!=vE$S{sp5411mk~2xrf6bDFl)6GP2zkhn#`7>DQqd4%9f(D z*itl&Ek)DWQZ$1tMI~%0n#o4dECPy32`DNfps1XHqS*u#%^{%ZYyyhr5>PacfTH;X z6fGd2XdwYb=MYeIE&)a75m2;}BM)2?&DO%3?QnZ3CMVGOqXeC>UR{u zEk$eCD7uP(qO}ARts|i5Y66O`A)x450*clXP;?yuMb{HhbOQlJHxf{^fqT%cQ8EJ?y_TBWAu# z(Y+bL-)p7lKF*h-``J?T09%T-u%+lhwiG?YmZFE*QnZyVMUSwh=utL`9wVS=8v#X+ z6HxR70Yy&|P_&(ZqNfNbdYXWuX9y^ImVlz?2q=1F5m59w0YzUB zQ1m4MMPCt6^fduR-w;srEdfQ}5m2;`fTHgSDEfhbq8|w;+D|~yPXrYGOhC~u1Qh*B zK+yq0sAzYFKiL6^cQ!b0O3@bk((G>;G4o}L{>%t2SuaI@alRBCVoTBAY$^JOEk*yb zrO1oxk-HQ{*iw|nmLi`mMNu}20s@NC2`GvYP*jb8q6`9x;sg|B5>S*yKv6aUML7f% zB?u@=5>S*&Kv5n6Mb!x?szE?eO#+H)5l~c{fTB7C6xAi5=rBU4=wOC_w*wMyX7`K! zkfO5#H|oV>=F1cv84q5)UWyuUz7#cNOVLqmDQd))qQ-0~I+`s-P1sU&3|oqtvZbgQ z8%4(wP;?vtMa>B)YC%9zO9G1W2`FksKv4k!MXd=aYC}L#TLOyO5m3~gfT9ir6m=w^ zs1pH2oe3y9o`9k*1Qc~8py&hwinl#ZQ4s+} z;|M4kPe9QGLa3-`-0$pw#O)^)MSG#hMsYl5zD&`ScyPu>DVoapQgjwuil(upXgXVp zX0WBGge^rg*-|u%Ek&hlDJo;5sGNYJ*#s2LA)x4N0*dAmP&AK#qWJ_AEg+z1Apu3_ z5Kwe30Y&E#P_&4EqVowTx`2S9#RL>BA)sg}0Yw)QP;?OiMHdrLbO|9;G%4;cazNrY z+Re{oDcWdvl9t6|=F1da77sRTlA@KIFGZ`^Qgk_6imqTw(Q397UCEZBHEb!miY-NJ z*;2HQjiRdwD7uD#qH75#T2DaHbp#Y$Pe9QP1Qgv!K+y&Qif$sHXd?kdHxp2_iGZS8 z2q@Z2K+&xP6x~KZ(d`5j-9bRnodgu!ML^Nrgiz7)xc|HZ63@3!G_H`M2KGq*o_NfB znW6{c!B?B5Xba~{(SvL$dWbDW53{9cD_e>lVN21YY$kfTAn{in0kP$|0aAK|oQGfTCOiit-33 zs!l*r4FZa45>Ql&fTG$26xAW1s4f9ThY?UzkAR~31QZ=k2o?Pm_t!Zf@!fV?bV!P> za?gt%kr^{zrs$~5;E}tfs1fH&QDe3g9nF@aCTuA>hAl-+*;3SuEk(z&rRX@e6g6j~ zs09HWfT9x!DC$N)QFj80dJs_5lMpIukm-NqfW)`jS7RGyhL7|wu-l?unKAQaiuz>+ z|K2M_{W)KXPGn2b0JanjWJ}Q?wiFF!OVLSeDLR=gMMKz9G?a~^VFVNnC!lBq0YxJT zC_06JqEiVd8bv_SX#^CVPC(Ha1Qd-Xpy*5jipCI7R7gP4SOSWQ2q+pyK+$*tiY5?H zR7^n8L;{K?5kf_MGX2K)IYr;vXC3=W(WUNr(aD)H^JR*rWd?m7kfQ0FFGVxhQdGj0 zqM2+dn#Go)QnnP8v8AY-Ek(20QZ$E+qO%DonoB^@JOYa56Hv5(fTD#26rDpr(YXW^ zoku{?A_9ueC!pv80*V$BP_%@AqNM~BT}VLDMFbRGOhC~k1QabJpy*Npik1^XMN>2V zsSZfIXWYR#ONvglJ4q`tW9G{gU7i_S`k)kD!TD0Onk_|FvZZJZTZ*n?OVL`k6s==R z(ba4zx`r)9*RoNxo`9n32q?OqfT9}+D7uk=q74KT-9$jqMgod%CZK2&0Y$eEP_&tV zqFV_lx{ZLM+X*PTgMgwt2`IXYfTFtzD7uG$qI(G_x{nYlTAAtJ>wv@`wcDaqQq;jd zqTQbvGhe3Yq0Hd*ho$IY&X=OCY$dV(!QPqL+GI~zq$ z5m59r0Y%RcQ1mPTMb8mX^gIDYFAz|)gMgwJ2`Ji0K+#JC6zw9Q=w$+mULm09RRW4$ zBcSMY0*c-splCM%MQ;*N^cDd{ZxcdATQdFM9FTa-;5;Zri&GESGGpe;6n&5x)P7Wo z_He!weaM!gkJwW5F@V#9D@Co{^P&y2V&=;f9i0_yd_szvaK02B!fs0CY! zTC$}mpN*nc1QZnzP}G`$qBaB+wI!ga9RWq{2`K77Kv72miaHTc)R};y;|VD0LO@Yh z0*X!`pr{)GMcoM~>OnwJPXda15m3~dfTBKxP*I~Se}@ASf81`18fS%%^z*XZ=$jQY zU#4h4R`AVsDH_Q6QZ$GyMT6N=bP`*NPG(Ed5VjNzWlPa8wiFF#OVJ26ibfJpbP54Q zrxH*!ih!ci2q-$8fTA-9C>l*b(U}AkjUk|@kbt7G1QZn!P&AH!qVWV2O(3ACn1G^* z1QbmoplC7yMNf-MQe;1HCVEy@%zT-mlB^*A87Z2{`BF5C zEk&hlDJo-2Q8`MGFWhT1Y_AIRq4)OF+?i1QabI zpy+%8iY_3aXfXjrO9&`hNqQ}@$w2duAkF%xd3APkH$(Ew+Y$B)=s5z4o+qH_1pCea!h%w3jVKpRlFqQ??X+#+IVb*;4ccTZ+D9OVL+sDf*g?qHhQ&`j&vA?+7T` zM?lf{1Qh*1K+%r`6zwOV=qCb-ekP#k7XpfYC7|d40Y$$NQ1m+iMF$Be`h$R?KM5%M zi-4j-1Qh*EK+!*hP|=<&zlj49|2=SUK9r({_DKKVteE*SMSgbBZtawF=nsL5vi;iVW(Q#}kYR;CT7HlbM$(Evg zwiLBuOHlz^idwT#)P{hfwgeQlBcP}~0Yx1MDC$T+Q6~b5IulTIJOM>r2q@}GK+y>V z6m=t@s5=2gJqRf3NkCCA0*ZPQP}GNjqP_$a^&_CDKOt1qB-_8=0f{#=ILAoQLHh## ziP>=>!y=K|s-H0*cNgplA#MMTG6qRwl z6qU23Xf|7l=CGycY_=55WlPaKwiL~0OVI+h6fI<<=o|uy&LyDeJOYXq5m0nK0Yw)O zP_&qUq9p_rEhV7nLIR2|BB1DE0*WpnplBHZMVAs#w48vV6$BJrMnKU@0*Y1dA??}<(oG(RBu%+lpwiIn=OVLwoDSDbMMbEIM=vlTD zJ;#=!=h-NFfqWIS0Y$G9Q1k`?MY{nw+JYDn}DKs2q=1&fTH&ZD0-iOq7Mit+CvBxJ(}(BbU@;d*v-#lQuLX9Ipo9a znE5hApJWH$y(dMVa=sLO#+IVb*;4ccTZ+D9OVL+sDf*f%Mc=Tc=v%fFeaA-8J_3rq zC!pvD0*ZblplCkFh@~@5GwjO+fTml6g_0OMSG>_L%VmKmJ>5yrYJopDA*%K zG0vBwYHTUWU`tV)Ek&7ZDav9?Q8rtOa@bOoU`tVwjiOuvit-33s!l*r4FZa45>Ql& zfTG$26xAW1s4f9ThY?UzkAR~31QZ=kK+zEd6dg%GQ3C>s8WK=+6ahtz2q5yrs%kw;Ovj2s5$3LQ46*dwPZ_CK3j@f zv8AYhEk&)_Qq+bmMQzzq)Q*j!_5>7lAfTut0Y#k%DC$f=(eVTnbs?arD*;6(5Kz>O zfTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OFok&2@00N2z5<*4Ia{ToUNc=wg zyN<_7(Hll;P)^KznW7;%!Q*?SXej4P(J;0Y4QETy2(}cBWJ}R0Y$-aGEk&c)Qgj+y zicV*v=nMjiMiWqUCILlb2q-EfplB=sMMVS@jU%9FJOM=$2q-EhplBiiMUx09noK~^ z6atE-5>Rv&0Y%dYD4I?{(F_8LN(d;LNeC64l;eNufW)iWW3-c{Xpr5zo|O|bU#4hw zPT+qgMRPb`iq2+B(Ok9^&0|Z^e6|!VU`x?LwiKPimZEdnQgj|0MT-b1I-h`|3kWD$ zOhC~R0*aOrP;?;yMHdlJbTI)%mk?02jDVs`2`E}lK+y^UiY_CdXe9wfs|YB%oPeS$ z2q;=jK+%;16s;kIipp~QrVdDaf!!9BOVPV_@A|5onE5hA*W?5zej!EIa=sL;XG_s_ zY$>{)Ek!r5rRYYs6m4Kj(M@bA+Q^ooo7pJZL_pCk1Qcy1py*Ztif$vI=yn2%?jWG( zP6CSVBB1DQ0*dY-py*x#itZzz=zao<9w4A-3jswB5>WII0YwiJP_&hRqDKfQdXx|< zT9@O`a6sZC?X!+oOVO=%Tl82?%zT-mCv$?8UrEt+&X=O6*i!T~TZ*1xOVP7zDSD1A zMbERP=moYE?O;pMi)<9_B%tUe0*ZDKQ1mhZMXwN0^eO>GuMtr6Isrv*5Ky$6fTA}E zD0+*4qPGbsdWV3bcL^wZkAR~02`Ku2fTBGF6n#iQ(MJRneM|@yJ)YxlaX{jEc30>L zZj0=%&+g5MnJ-iHc~0=wH&XNk=S$I-Y$^JREk$3mrRW>B6n)ELO@X(0YyFmMNvYi=+hkkPX{FafWi4pii(X?kcgQtQg|)FIOj`ICR>WK*iw|umZBWC6eZYFlw?a$E?bK7*iuxTjiMR^6xAf4s1^Z5wFxMy zLqJho0*VeJpr{@JMfC|NI-G!_BM2xul7ONH1QazSpy((9iW(76)R=&xqX{T#LO{_m z1QazTpr{!kR1{12-5rql1$I}cS|WU;zrsizn~0e&Q`9mM6#XDY`J69Bt=Ljjz?P!c zY$cEzwj%*ZlBA}=<0Y%3XP}GHhqOJrKoj^cQHv)>f6HwHH zfTErR6!jvYs5b#ceF!M(OF&US0*d+*P;?>zMFR*Z8c0CVAOea86Hs&#Aym{n;a}*0 z#5dVvv=&nIdFlaMB4)l!(eOmDdA}5m;Cv|>$(Ev1*iv*VTZ%@prRX%a6rIkNqBGc1 zG@30%XR=W=hJd0%0*b~GP*g-f(KrH%#uHF9fq8CZK2u0Yys* zD7uh?7I}iJ18^MNcP!dB021Gn_9)&$6ZHIkpr%&z7PW*iy8E zEk!S~rD!Kxie6$%(JnTMUM8UE6#|N0C7|dv0*YQIpy&+(igpuF^dU%W*E=BbF7~kO zDJdFdpMv}>5i?(==&MBVHRnswH*6{TmMul!v88AqTZ+DCOVJN(Df*EuMf=%O z^b;FJKNC>&3jsyH5>Rx2fTG_BDEgg%qJsn!{Xsy{p9B>BML^LZ0*d}7py(e0ivA^_ z$V=*BJBlI%6r~YRuEpeUVyq8K4m^hLt|+yRL%vkzilO3^^OEvlA`nJ-h6 zl?;MIQk2d4Qk27%q6Axtl58o;WlK>WTZ*c)rKkp5ifXc@s1_SVwFxMyLqJho0*VeJ zpr{@JMfC|NI-G!_BM2xul7ONH1QazSpy((9iW(76)R=&xqX{T#LO{_m1QazTpr{!E zMaL3QbQ}Ri%?Y8Rc+x-C0f}$PaBwn{;UoPg?ZaD(WXyb-qJm^F@E<8^&G}N)hAl;H z*;3SwEk*6wQq+MhMIG5v)QK%co!L@!JR3z_2q@}GK+y>V6m=t@s5=2gJqRf3NkCCA z0*ZPQP}GNjqP_$a^&_CDKLJH25>PaNfTDo}6b&MvXfOdqClOF|G66+H2q+p#2o>cg z{h1C({3E+}-Aal+u^Xmg$(Z>vMW-Z#%RPGqt-R=|oG(SA*iv*FTZ&F+OVJr@DH_d| zqBGf2G=?ojg={Gr%SKTV0Y&2oC>l>d(F6jDiU}y1NI=mf0*WRRP&9>rqNxNFokc*= zGy;mI6HqjRfT9utie?f}G>d?uQUZ#~2q-EiplCJ$MRN$Dq7g~|AqOPB+`e=+Qi`(e zk^b4qnE5hA3zES*X;QS1^QGt^Z)@xTL>t6kbt6x2q=1(fTFDg6g@&f(W3+uJw`y$HUf$s zC!pvF0*am_plCZGRCImP@9BWV>)6fD4N|n;9-}>#jF~S}^jtC+ACsczIbVuiU`x>s zwiLa{mZF_(DSC-5MZ4Hi^fFtDUSUhot85g#MnKW)1QfkNK+$djiryrk=q&<@-X@^v z9RiBpC7|d%0*c-zpy&eviuMpt^dSL79}!UWF#$z;2`Ku6fTB+cDEf?mqR$B^`hpND zdM4>#?102;*lp3XQnbRfTE)aC~8DNQDXv%jwYa}2?0gN5Kz>VfTCsu z6dg-I(QyP6H7B5`1p!4Z2`I`Zgo?6r{Tf+L(Tnz3$DG{ok^VZnEozk;Ghe2tZEnym zM~d2Uz7(}*OHl{56m?`vQ75((b!JP^@oXvT!j_`0Y$-Z{jiPP@6m=({s0RT>Jqal4 zMLCLK+#zQ6ip+b zXgUE!GYBXuA)sg`0Y$S2C@LkOsEmN3asrBG6HqjVfTFVrD4I(^(L6$^=+s>QMh7H* zkKGoHlA;~j5m0nF0Yz63P_&wWqALj~T0=n5 zRRk2RC7@^>0Yz66P;?CeMb{Egw4Q*X>j)^io)9WpnCpM(fW&j{=I0zKddbEOxiRx) ziZ{xEk(DnrRa9H6y3p=qC44AbQc>%cN0)_4*^B@ z5>Rv>0Y&!{Q1k!+MOz3cdXRvkhX^Qon1G_K1Qb0&K+&TF6g@^j(KZ5#9w(sa2?C0q zB%o+J0Yy&{Q1mnbMb8jIMH_Pc<_<`_j{WWZo22M*yDfS)H)g&}(T?0;aBV4ik@KZ! zCtHeMVoT93wiLb0mZDeKQuHcYie6(&(d%p}dV`Ik-2@c9NkGwC1QfkZK+!t{6unD8 z(R&0Gy-z^V2Lu%DA)x3(0*XE&py*=)iuMvv^a%k)pAt~?839F~6HxR80YzUDQ1lf6 zMPCy_MbGE@r4C5^RePlWf)xGfo)`TlH)g&}(f7H*>bg?&1LsT8k8CO0&z7Q}*i!T} zTZ(>ROVO`vDLTNGqTkq3^gA0x2MH+pgMgwx2`KuDfTBYL6#Y#=(LV$f{YyZRm#2sA zD2fnJltw_2Pe4(WfTDnaqI3d^VgwXbBcLdQfTB17MVSN?Wf4%6O$Zfzm+NnJK;r+{ zS3vej(O>pOwVb?|`7%X$dBJ=2q^LUQOHmEB6xC!)Q7yI<)n-dk9kvwJWlPavY$>Y8 zmZJJ>6dg`L(Gdg`9Z5h@0|JT~5>Rv$0Y!}nC~8bV(a{7HH6ftr7y^o#5>V8PfTCjw zC_0XSqUHn?wIHCVB>_eG1QfL*ps0X=qSk~^Q8Lf}#{r4Yw@(q}=7o>+mpVMrHhD4g zWr{lF1xFqsMIAX`iaN2Ss54uNj%Q0z7q%32WlPZsY$@u-mZI)#DeA#SQBMMjdJ$06 zn}DJ|1Qhippr{`KMg0jVI+1{)0R$8cB%o*z0Y!reC_0INqLT?I8bUzPPy&jE5l}Ro zfT9ru6pbXH=oA8qP9=nj+U5DZ9gz5O2B*Cg?YG;aQF$@*Wr{}U1;y@PBu;%D?M%*> zqA_eKDr8I1Shf@uv88AnTZ+cBrDy_Mii+7%G?9&>Ndy#4CZK2v0Yy^@C_0OPqG<#a zO(&pe1_4DS1Qg9AplB8WMWqB3l@U->PC(IY0*dAkP;@o{MRN%#nnys{k zEkzfzrRWm26fI**(WPt@EhnI81p!5u5m2;}fTC3d6kSe0(G>&~ttO!8N&<@35Kwd# z0Yz&GC|XBA(bWVLT|+?8wFDHcC!pv$0*bCDpy&nyif$yJXagZsbY7nSngbI5(#_~1 zDf-dIO?ff%<>h#3(MB2dnnb+BX7?pqFY%&*OMK@(O<66G?HoOh(>wM{(N(DOPb zG8=ndm&DK}p4UCGwyEd!PJDQ*=k-rCYTxU$Z%E>v0?!+fIMBxPMkS7K?|GvW z=XdnHv56Ntd)|aZc301voEYBC^QI-P?%{be6Cd~Tyz<1+eLZh(;;jCjw=i+v0MA>L z_eg6-nB^=-M`tw11MbV!(*9Ar?vbSZt7g3;N&9E1`bU!X?+OiyB){42 zu9Ha8{$-C5k)-|845K1R``P-VBT4(==wl;E`{~vbB1!x4#FHaQ`}wldB1!uJp)(^% z`w5Tbk)-{IzPXX4{fxDRk)-{QtVNNe{gk66k>ulh-8B?R+RqtT9!c5{idYp%+IRY2 z8A;l=YOjkV?R#z4N0RoK-5W{TXTLs=B<<4|Uq_Pm_;X(*X%8UwN0N3A@YhJvK7=2PB<(i%P{hmq z#QmX(-W>js%X>TSuFN*Bxc8a+FS5RRk$Z3wX_vFoQgx@!i?r8>+H*Q+%=g{sn6o(b zVwbuF3nT8Cg5msqnnC#$IOT2`+h_U(54zI%giA*(vkH>h3qG=T!5&pq*zWy?P`w zGkk%Fo3U)qug1$~W@cw*Wp;GGlWMj9s9Kda@g3ZyGv(pIhlGQ@Vs38PV`3dT1L9nwoX3R|~oT~Jui%3=!_Tg)h#QQV@qXxx+*1+7}PX<^T9 z>7M-`&&r=NWBjz)6N>Yv7mc4hWyb&S7o%)mS=IN%q{;a`N+-;oGNYtdNojG5iuc9b z^3v41Bz%tyDJ_}m-sffc!)F$ip4E5ujKUG__cCe7wAp2a!+NwI-0uIy)ikH5yx87b zo)=!x6KBsD->P-%mg9{=;e_IeMYE@s7naYPSzOj~vI%on*MuoE%H41`1;cywDRdWe ze6Nz}(@SQ!X87D~S&*XWw}}Kn_5bZx5J~qZMS?uPUW5EbjT-uM8U#W5z#uQ(os{0y z9cvunp2%1Dza8xaJ2BtA+8RM#<*AYUv`nXaSf74{eOvYS>{!sTRsX_q;gjv#Ry^6R zSH+XBJY`Tx$;<+8aF0=iy-pg@I(*%|Ii+32+v`AT zQ~7pVSG?U`RbHhoU~5ijU-43%QkQA=jIt?{W)x3o;I53+o9m^^RnV8$;-28Q*{9<7 zQQ$62>g7AR7b`4uXSZox7`}!A_r^G(FR!hKUR%$~*Wlg*?!_j|o<4nE_?q;xZF$2z z6gpH~0QU~9c+C}Wq%CiwcjY_7y$ke$?jncpM)z96C#qb84xH-Vd8uc*cdX89SMkc+ z<>8IC*2}l4yd1qM&M4@`n{pRiXPAI0w_X3Q{>1h!9yfbZ_`7lMfA_ZBjX;$vK$oL! zcKG5IzZX=ss{E~Vs<_w%4y-q@&uN7{dJjvT=dMTnj+|FL)%!or^rn@}nA9Nk zzyD#Xpz?zB6dQE8>n!yK;8X!7D7;0`*SDZ z!?)3zH&%J&7gS#R1y!zocMW;}FF)Mt-a_REk<{)TZ@l?f8d-uDnM9%GH0UYhw_KMuG;#yF`guA8Ev)WW#KkmKE zi&v@w3|=aXbaYovNyVRp$}60YCUzU7SLe>*6+7PHRqEbs>IwIr;CU4n$-OPt>_hPg z_hDKu&x!8JP8AcB`XCj4Z0b{Swz~%O8Y?dWfZTgX&od~gcec9xf>++QmI#- zdX~Fxb(Z_sp{FW-BMx@V!zH9`u2;QbR!{hYH@63f#wJ_xj5wmz0)Q zd>C}txD?@)UU7X_e86^p22(F$*GcL(<=z|N6IBRQUgZUq*LgwZmCiL%;4Wux>;QWTKwaOJ*dHuOJuJ=uWyAKk+p!>tGCo0~B1>v=87qiN(e1Xnz*J|ZE*ge(n zq>&AJb?Vf>?isf%Xkhn^TXk&Rwn5X<;%UW2WyQ@Jw3t4A=IpNH-FvKfZj0${+PF|Y zdG_>i?l^H;Nl|$VcgMP`yILk#a4$J==A3pd%4W8hP|)6$qSEn`ySjVYb2_$|-g3IT zuYTNwvYE$CoY|noqy{ZcZrz}TyK~reyt@D`CQdIdD=V5*++tesj7jB_yS8#Eyu;GM zu64KUMxuO5$&40d?oO^dmbo^esJy6RhwlpaK|g$=l59bxS>yP>edr2VR{8K+Vb9r3 zz0S%zf2Psi$CdX1EAROgguqi$+)ceMR^>GmDzEt1nL=Gy_@5uxx$9YZ&l5IwU+Lt& z!z(^u7jQ?j@=jyreZ|VVitbLQUGs(Z$6hzL;ROr-OxT63P|cmr%KL*=?hbOFv+}+l ze?08&VEAql%kX|*>iuAMHg*3q_4^I~3|71k_%l}_8`yTI^Q?-SLGD{t-v6t-`v>ug z>%ZdOWyRgbihGDv{w!7giKx7P$JJeV@2=u%4DTX({d)E4+@Pub>FH5Ay+NPp#(uK(AsswwLI^l#N?`}TmY$}eA^E+F~#c&^GX-#wPgt+MSC3+{8Op8IU3 zepP;=!GiC(PheE}<$LbaK2?7Cp8JGMm0!N+KHpR2m-{qwm1VEby>qJk^1Wo0WzSFi z*Ut0Y=Y>+gOM5@(*<;cFeoWiA+-p4Hzy8#?m$grXrP-&G?dU$0Y`I1w zBE5!obT8CY-L5ZtIrkai)X{w&ICbo);}9K3>gXP2r=CAmNB7y<)ILwgB|5Isaifm+ z*{5mT+j(5a-R`$$`(qssxZi;7h3E}iSK7Wy z$1mMG!1gaXHg{LN?M^zDx=*XyK2OK3?i1{`pVRT5!@`|eFFf{kpLDn957lwmk>Ose z<7@66YtR2s$6AfU-AKpLO~O4z$D7<0U@w1G*B0 zaR07jtG?mxs^gsg;a;rcwgKUOQOC5w;ZEq-|KxCw)bX;R;l5VKH;0G&6CDpbCEUm8 zICfOHr|Wpj>EV7r$9?V(l>Pqx(6M!4xVz~%wx0ioO$LPdx=ju3Ma=1^` zan;mtU#H{S)586kj`d5z-Au=Ev%+1X@keo)6BW{3MP9oxS-5BEc>D5jKdj^a%fkJ) zj_ofGcP||mt`7GlIzGK7+^_0bZC$u)>Uh#M;XXshE7ym6gO2aJuhiJ}^OcSbHiWx{ zjuSVAyG+MBH--BV9e>^&?tgXcczd|}=y>j(;l5PIXYUU8>pI5o3wLcDhddDOGj+V` z!EkTXanHly{zk{69u0TCj+3{Ad$x{uKN0T7bo_ODxFb)6$Ij1$$9_64dM?~6bbS7W zaPQVJYiGFY>NspyxC?b$_e!`o>G;uW;r>p?#=FB^pySlH!hN=m_r4SE$94Sey>R>Q zhsQ2^!sCfLUhq-4SL(Q9Z@AymG3T>z*VA#t7vV0_@tUu~y;;Y-?n_$c;d>pM>Uhw7*~`ukehH5!90-pCbzJg$xG&dn=O5vIN5|x$a38MYDgT6f zypHSLM|FGsx9Rw)`>L7kA9ZZ%KILq?osKiy*U@Y*&~c0Vf|~88bo|qOWzBZXeQS#y zySp#3*>SLr7rL*t*< zpL9IdeTB|;2OVcN2=_TUKIFb;XU~5|$NKIo;I^CT*vgK9=N+%zU&oO;j?=M3$Avmx zqT^LMZq)H!9Us?mr;h1%|D&4w0+k)z+p}MGbay*a$FX*Q#BF!Cz)Q<<~uJoR+Z zxN)V$bG$0gEh;UVF{#+SlFAeQXPIVS0Me^)m%?i~-hH*A*nQT#%2^Xji>A95>M?9^ z%cAn~(kbI+m%CT{|Mi!Q_Vee|tGUod4tH?0NR<826uh zxBp*XuDN@e|9-opUE`NsPxh;~`;XUcdzJg|U3VSxi>JD~;O;VdcC=qRIz_xXE>w3< z+tqKc&o0*x_aEoDC%wtXM7%~-0#ADX~b(_C+HV1H^%L%Z+CCcNXneOU3+`H z-P!JG&T&tAcevMQHu=T#X1P%H_3f|n`r__+yuORv)0|_k<1zR8_H$)bdER38bk*1A z^@^k}mtDRr_aCoswa#hfj`r&g_t)$Ww-?Yadt3J3^*Zu$J32(X0eTrb@N#$PX`WT1 zW5nYeYxZ{S*Jk%$)yr4ST|Rri*yXb$mv5_k+S!}w4yj+g-RtYja7W%3cC7Ml@D{n3 zYv7{&InQyE8kH*k-+TNPCKfBW`r8#L(Hrb8$9Eca_{{JcJc`i5V_4qtJ^Jxb&CTG{K~ zru!9ye>R(XwcMk-nOg?_yuGwmlNycl8Z2sukiYbM!s~2vu3(m)3#OL ztM1aIMbcA`$s*N?oXfPd;DeYQVnf{nHNTd-z-fc)47Qhx1_#`8{1SVqlk1L6rPv4V z{hwAX*y#Rfrd5m8bMN73G_X&-q(x(|yBF~fx)<=9SMOm@uXAtOZ&hQ2dpcNY=SR}l zxL27TjW!AFFIUCvCpaCWzmqU>#tmkGs zFWOx5FgM$~A3Ua6*Ub)Iw54VpH#>UKe9hW!c5>gltXa#=0(Y?rv}@XSm#ejQ4cqR5 zwb8C_+g-A@+IhC!MQf*>YujD6_S#9??!tA@PS|#ruA_F2ZFliHX=mGZm#?#SmfNk} zOU9{u2-R0}5onhNuz7w>o*>;z&n|92$yL{cX(`~!U*F!t7?Ji$W?Wk>c z`Fd%)&$;w$?Ji$$?KHRBxXaf^J7U{izP{RyLA7YKvHzmG{xcStpQBTMuRNo`$%yug zZFVnULIwu*7w=L+2I*7@8LTNGCuvH^$(j-}L{mbBYD&m3O$iyUDIp^?C1j)~LQc^} z$f?>08KsSo)3gzCx;8@2&_>8;ZG@bujgT?g2r1M?$XIQJ6lo)5oHjznYa?WWHbRQE z5i(I5A(ONbGFclTQ?wB>RU08^X@^2i^uKf0e?|v)3l<#^3Tf?bp`z1bCdY)#4D2su zri9GWsS;AEDIsN=5>l=yA+t3lWR9kUoUJJ#b2TMoo~DG%*F?wyZGLN3-u$R*kcS*DGUOSKWQTpJ-P zv=MTdHbPcvBV?6!C}f78?QSwM>~p%&l2FJijz;wIn8`6AYXbWVyD1@8=~M|>t0^Jt zG$rI}O$oV1Q$nuQl#unB5^|lUgj}yFAvb6u}h(5~LeUcAiCdY()9N1sD4HAwO#)DAJA&0aP^0ziZ{?SIrzuKXY5B+j?{b$@@_dPyJ35maK zw;}EeUq;8i>nIut?At(6-@6t>bhf_hD4nhEI*PINT}Rc}`mUo4w!Z5q&enGwWwP~M zM_Fur*HJcG-*uG3=DUs(1itGiN#MJVatVCbQ67QsI;u|KyN+rQ_^zXx1itI27J=_N zs!ia#j_MHjuA{mHzU$~P0^fC1kHB{w)hF;>M~4&muA?IeeAm&D1itI20fFy2YDnO_ zj*cSmT}O=weAiK9f&-ErjiyEXM;(y(2D^LWM?yur?0(D9k(lu^Ma?3CeH&3q(XpH_ zMaQwFs5x7TTCk<4C0mN}*;3SsEky-vDQeA@qBd+4wI!ga9RWq{2`K77Kv72miaHTc z)R};y;|VD0LO@Yh0*X!`pr{)GMcoM~>OnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt>K zkq|06CgQulVc^B5*-cSXDcWYF21H`!%M_gy3GCa@Qi@LId?^~jmZG6-DH_I>qTy^Q z8o`#Lk!&eCg)K#=vZZJg8%3uPP;@#0MQ0FDG@5{-GYKdfLqJg>0Yzg8C@LbLXdD4W z;|VC5KtNG30YwuDD4Ik-(PRROrVvmxm4KqN2q>CHK+$vpie?Z(MS~)KUk4<<#m(qo zDM}cr68Bd*oG(*U776Uz7*mSMIbVuqv!!SbTZ+zROVM1m6wPBx(R{WPEnrL0Lbep0 z!$#4$1QeY|K+z%siq0pX=mG+Y786jkgn*)@1QcCJK+#166kSX}(Io^FEhC`lQUZ#W z6Hv5*fTGI?C|XHC(JBIpE+?Sq3Id8&6GBC^BK~p*B%bXaX-7+?s72~=RwQP=OwqbX zVBZFtQgk)vOVKrKDY}*|MeEs8bRAoYu4hZp4Qwg8ku60V*iv*88$}xlD7u+|qD=%8 z-9kXoW&(_^?k1q<9s-K)C7|d&0*dY@py&Ytinb6? z^dJF64-ruGFabqd38A8^BK{i=NW7Un{8}qTKe;b0L?4O7%$F&8JQCQqQKu9=!TD13 zBwLEMv!&=MwiG?hmZE3aQuHiaik@Rj(erF6dV!6i9Rw7;NI=m}0*YQDplBBXMK2Rj z^a=q*uM$x78UaPG6HxR90Y$qBD0-8CqPGYrdYgcvcL*qYmw=-82q=1=fT9lwDB43n z(T9Xk(PI(6j{9nOe7`+#-zG&*+r8_LA~Ex2iaw15_HFnnMW1oL6n)N?qA%D|^d(!0 zzG6$!*K8^JhAlzwiLBz zqo@M`MI8w!>O??MX99|jC!nYc0YzO2C^~_FqHY8fbtj;x2LVMr2`K7CKv8c3iuw>x z)R%ywegqWtC!pv=0*VF@P&AN$qCtdE(Xna%w+=`=?*1N6^f)QiiWeLXark|MzW>o6t)zd%9f&0Y$-a8Ek&oZrRWScibfMqbS42sV+bfJ zB%o+40Yyaw6pbUGXgmQ$69_0OCZK2{0Y#GtD4I+_(G&uTrV>ze76C=m2q>CPK+y~W zib@D5nn^&>EJCR0x>w?#vw=qvm1R+<(wU#4hIT3|nhD5dCZ&X=OOY$=+@ zmZJG=DO$jmqJ?ZJI)^Pq=dz{fJhl`qVx#DM0*WpmplC4xMN0@MT1r6Cg#;8`L_pES z1QcCDK+!S+iY_IfXgL8zD+nmMjDVt*1Qe|zpy+Y}imo7_Xf**vR}xUPhJd202%)0# zG=Gi*60d8YBAP8lx7lsc+O(MYGDX*>1#6p1(R$98qU+dFbUj;&ZeUB%jch5}z?Pz$ z*iy8SEk!r8rDziyMYj-8w3&dSTL~z-jew%t2`IXQfTBAID7uS)qPqzwx`%+GdkHAI zkAR~42`GAifTAq~6g@~l(L)3jJxoB+RsxD1A)x3{0*W3Zgo>_C^S3!5@l_EA=Nc*c z&~A&irNzvbDcYVE*pER=-4;E?`BL;WTZ*1xOVP7zDSD1AMbERP=moYE?O;pMi)<;{ z$wtvj1QhKepy*`+ie4e0=v4xWUL&CBbpndsAfRYB0Yz^TQ1li7MQ;;O^bP?f-WQq;okU4N1mGhe3Y zi?pCo3n}`N^QGu3wiJEMmZERiQuHlbioRn@(LS~meb1JnAJ|g#BO68g2`KuBfTEuX zDEftfqF)IpIzT|tZv+(mPC(H?0*d}1py*EmivA*?=nw%#e-lvj4*^C05>Vv+2J*G; zYII*wcQ*s}*G?k@6r~YRuEgo-{(^ZPp>@v(MW^tlx6w~_A0%$F&O`+@x! z#?)<5Cg)307F&w4*;16lmZAh(ijr(8%4JJY9$Sj4v!$p88$~q>JU&= zmw=+f2q>yYKv8`HiVi2B=m-LejwGO{0Rcq~2`D;>fTBhO6g4KG=x73pnh;QQ3;{(= z2`FktK+&;;P*FACzsv!NkF?J^X87SF{k!e9=r})SzD!ZRAJ~uaOet!``BGHCmZH{d zDQd%(qPA=)YR8tM_G~HYz?PzpY$@u*Mp0)1ijF6ss0#r_T?r^UfqP0|NZvu+?5Kz>YfTDf`6!j;d=tKgF1`tp*kbt5=1QZP>py(t5icThkidy*o zn+`}k-9FLSQi{H`+oBQk`K+!k?ipCRAG=YGkVgiaL5>PaWfTGC+6ip$ZXet3k zXAw{|jew%*1Qg96ps0j^qL~B~%_5+vlz^f#0*cBBp`u~Fe^^_mXt(=2i_zgyG{Np& z&-P>H%M{J?1N$+;DMj-+Uy2s6rD!2riq2t6(Yb6XI*%%}5m2;^ zfTG6Tj2M@`XnQuMTqC;gcDGDXk$f&Ccsl%i)jUy7b%OVRUeDSCk| zMLXD1^deh|cCw}DCAJjpVoTA>Y!tmhK+&rN6um}3(dz^hy+J_HZUTzlB%tUm0*c-y zpy(X}iryul=sg08-Y1~w0|JWn5K#0X0Yx7XQ1meYMSBS-`h2liv|Q;NRfd@1^tEk)n4rDz{pioRz{(GP4X`jIU~ z``J?T6I+UYW~1mA0*Zbmpy&VrMZXbH^g97X2MH+pgMgwx2`KuDfTBYL6#Y#=(LV$f z{YyZR7uCad6h#OqN+Y1iC!i=wKv6(IQ91!dF#?LJ5kf^@`hIH%B;MRUUHz35EwFpn z8PS;eGDX?Z!2TJ9l%gEYm!bq)ijr(8%4JJY9$Sj4v!$p8TZ(G3rKlELifXe_REL0~ zx&#y*MnF+L0*dMrP;@u}MMn@&bR+>q4G1V|NI=n11QazQpr|ncMMo1*)P#VdV+bf} zNUDznPbLRF9M2s6HwHLfTF$x6!jyZs6PQkClXLJfPkWb1QZP-plC1wMJEwZbTR=&LkK7u zNF>EO+WJ}RlwiFeyQ8bQ#qVWV2O(3ACn1G^*1QbmoplC7yMN3qqvk9T1kx@U|+bR0m zKI?dj6!lL%V2j4gmnm8p4eXx*N+~*r^QGuqwiKPmmZC*$DLS7mMHjH8Xfa!gmawI0 zDO-vzWTWUJ0*Wpspy(0;ik1;jbSVKv%Lyo2K|s-E1Qe|#plB5VMVAv$bOixLs|hH& zl7ON$1QcCGK+#$Piq;WObTt7**AP&2EdfRA38A9-QGb8~5{#Ek&EyQgjPjiZ-*Q=vKBA-Nu%p+u2fd2OC9q5>Rv( z0Y!HcP;?IgMfVa=bRPjl_Y+X`00Bi?2q=1xfTD*8D0-NHqOAlJJwiayqXZN^MnKUv z0*W3dpy&w#ik>8(XgdK#PZ2^zH$?qa4oLhdyDhp=ie}kIw5Ovn^JR*jj|TS7kfjv8 z!1+?NgDpibvZZJzTZ&#{OVKX26ur!rqF2~b^eS75USp%^bpndsAfRYB0Yz^TQ1li7 zMQ;;O^bP?^q6Rm7+cN5iKi-nJ-h63Y6dg`L(Gdg`9Z5h@0|JT~5>Rv$0Y!}nC~8bV(a{7HH6ftr z7y^o#5>V8PfTCjwC_0XSqUHn?wIHCVB>_eG1QfL*go<(kf1Cpn|JEMqCxY;i{+srf zjS7O8`7%ZAg24V6&6J|{oG(Qk*izJyEk&K!Qq-9(MaQ$Hs0&+)y0WF{1hy1)W22}$ z0YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMJEzaG=PAjfdmu{BA{q60YxVfP;@c@ zMMDTE8cIOXFanB(6HqjQfTEFvP*Iz}ztsVWC++5^trV@WaY_&~U#95vAh3UiHKphb z&X=OmY$-aEEk$G4QdG#6qOoi#Dq>5~IJOjxXG_rpHj0V~D4Iw>(If(jCKFIJg@B@| z1QeY`K+!Y;il!4#G=qSm5(0{55>PaYfTB_YipmHmDkq?5HUUL*2q-$6fTFns6wM=` zXg(oSG%E0aa6sZK?5@yhQgnjdNm>xZ%$F%TF9__P@l7dO#Q9QmK3j?|U`x?rwiGR4 zOVLuc6kW)cqKnv4bTM0sE@7i+839F?5>T|9fT9%y6kSF@(Mke}RuNEiIRQmi5Ky$5 zfTAl2C|W~6(NzQ#ttFsn9RWpG6Hs&w0Y%pmP_&+aqU#7Kx}Jcd8wjDIa{|Au0}>x) z56jM#q9^UP=*A#szD&{0L16z3bV|`C&X=NF*iy8aEk(DorRX-c6y462qC419bSGPi z?qW;P-E0)yLqO5J1QgvzK+*jK6g@yd(G~)V9weaXAp(jXCZK350Y#4xQ1mDPMUN3s zw2gqG#|bEUf`FnY2`Ji5K+#hK6g^Eq(K7@TJxd4`-4yuq9gz4qyDPL&ie7Nfi#`{` z%$F&8F$nCR5l<=F$@xmZDeLQuG>Iie6_+(Hm?j+RaAMn* zIRQmq5K#0b0YzUCQ1mqcMc)uYMK1*Yb_XQx{=ow;xzM=yiM8pGc3HFH=-KJvgRNifVAa6xC!)Q7yI<)n-dk z9kvwJWlPavY$>Y8mZJJ>DLR~uq9X_>I+B2*1_Tr}B%tUh0*V?DP}G=!qN52YYC=HK zF$5GfC7`Go0Y%3WP;?vtMa>B)YC%9zO9G1W2`FksKv4k!MXd=aYC{MW<)-_C9FX`L zyLavW*>C%%6Zd;?qiuT3e3_z->B00ODeA=eQq-9(MaQ$Hs0&+)y0WF{1hy1)V@pwY zwiNYXOHofYih2=H)SG~!J_Ho?C7`Gu0Y&`@C_0gVq5%XH4J4pw5CKJl2`D;=fTEKL zC>laQ(NF@4h7nLSoPeSc1Qd-Vpy(6=icTeqB#T~MVGLpXc=3IE@ey6ayE)q5Kwd(0YxhbC|X58(d7gbT|q$6 zY66O`B%o*w0Y(3ZxciQdstnk*zb7-pB$G0e(0dT1hY)&|-g^~m2oRb;APESF6ahg* zX;P#kB2@$d#e#qWA|j$#v7y*Sr78--d7kY1O5*E!*ZKZ9YkgS@ckV0M$t3e*GLs-I zA)sg}0Y%FQD0-5BqU8h>tstOiB>_dN2q;=jK+zfkiq;ZPw2pwHrwFd1sRg`c1{+1M z+uNdPQsm8fz*Zn&eOW~t3;3H2m7-0YFGZW#QnZCFMO)cYw2duA&$6XxJ6npLV@uHv zwiNATqv&}8igpoDw3~pUJp>fJKtR!p1QhKhpy(w6ie4t5=oJErUL~Mt9|1+L5m2=yd{$-XNgp5CKJp2`D;3K+&57SJ8$7-a!UP@K<~D^NbV?vEyigfc0e+ z9WUUYIb4d~;e07N!Iq+T*-~_pEk*CKrRaUO6rEyA(FbfP`j9O}AF)yNF#$!N5K#0f z0Y#??DEf?mqR$B^`htL>F9|66ih!as1QdNuK+!h@6rClY=vxAcz9XRMdjg7nAfV_+ z0*Zbjpy+1;ihd!W=p4aSbgY1PivbecXuqPpEk#Z3!~S0j1gtNs=t2Si+asjtBIird zCAJh@W=qi(wiNxrmZCq|QgoFqMSroS=x??ZU1Ou@Isrxh5Kwf3fTEiO6gdGsY)6rY zfT9Qjio66A`3NZT6HruufT92aMUey)MG;UGB%mmofT9=zied>UiX)&XL_krPfTDPU ztLXOv-tz`X@HKn$b6$!T+I!atfq?a86%`5i<1?hFDCbL2F}4&HXG>8DwiK0QOHnDd z6qRO6Q5m)rm1Rp&A{#~J2q?ORfTHpQ6jdOg=vD%XDiTmsiGZTY1Qb;vpr|SVMb!u> zs!l*r5&=au2q;P>pr|GRMJWUn)gqv%HUUL-2q>ycKv6w{tEf=GTh9Oqmb8!b3kTds z`e*D7Q~f}|`m%}|2mH5>k)kG?FGWq+QgjrQNw_Dk^vI@(oA0?DVl9>i|!5ttS_smf55*g zON!DsUy25>rDz~qiUzTzD4i`ugV|Cvge^rw*-|u&Ek(oGD7ue;q7eiXjU=FG6ahsU z1Qd-XplA#MMVSN?Wf4%6O+e9D0*b~FP;@^5MdJx5nm|C&L;{K)AfRXx0YwiIP&Ao< zqA3IvO(nRB?hSZfH$Z}g?ZdKEDJpBfyiE%PtS_r*X25^e{G+ouKLL4|^QCAOTZ(40 zrRWj16wP5v(W7iBn#-1=$JkQzI9rP5u~9UifT9Hi6fGp6Xb}NLPY_VFn1G@s1QabL zplBHZMNbk?w48vV6$BKmB%o*&0Y$3`C|W~6(OLqE))7$j6ahu+2`GA+fT9fqSJCu< zH*%a&w9ZW53@KV{zoI=82v}cM(UyR}%6KW-%K1{XjV(pbvZZJ{TZ*1zOVJLt6zyb7 z(erF6+QpWl-E0)?A)x350*YQFplB}vMK2Lh^fCcOuMkl5Dgj0N2q=1ufTH~b6dfR- z=pX?_uM<%81_4Ef2q-#CK+zEbiryrk=qLe2ZxK**jNmHT6!3O6K!Qi?{~Nnmif*^J zMQ;ZJ)|XZEZor>0QHoA-z7)O3mZJCBQgn(fMIW%G=tH&?eZ-cckJ(c630sOjWuxdc z0Y#q?Q1m$gMPCq5^d$jBUlCArhJd242`Ku8fTFVm6n#rT(RTzCeNRBq4+IqbNI=m~ z1Qh*DK+!J*6rCfW=vM-Yej}jhcY>?voq+cV10>kR-W56_MUUFsqVs`(^<@=Z4*2&> zlAC~_k8upLDn0*WFC zDDo0efs0CY!TC%066PtY;?F1C{BcSLG0*dY=py)0FitZ+$=pF)!?j^X2nnZdB8z8~P7EV(s8f|ZjQX>P_ zmsK<{(m!ju6b<5hDN1Kc(O|X|4Pi^sP_`5eV@uI+wiMmRmZA}CDH_Q}(I^6nG6*Od zO+e8Y0*W#TD9R$BD4T$yu>=&2BcSMh0*b~HP&9#nqKO0)JwQOwBm#;aB%o+A0Yy^? zD4I$@(KG^z9wMMA+x7U|t)fCRs`-*p@yMbVbjjL3lXWfjei^uIGxiXP#7DVoEU zqDR?MG?y(!kFllbakdoAV@uI|wiGR3OVL6$iWU)2^aKG#iwP)NLO{_{0*aOqQ1m1L zMau~&T0ub3N&<>j5m2<6fTA@76s;woXdMAXPZ3bGo`9mK2`Jh?K+!V<6m2A+XcNIz z^l+s2q5%@z?lEv?NzrvnYI9`3`m&0ijr13sEk)ZoUy7b%OVJLt6zyb7(erF6+QpWl z-E1k^!_8+WWf5eir$a(-!VsuPI0~zeZZEY57|=m5nGBrW=qj0Y$^JbEk&osP;{1nqHhT(`i_92?+GaSfqUiX)&XL_krPfTDN;iV_GYDo8+4Ap(jD z6HruyfTE%VSJ9P7?;!&uc#pk9{f87?wzoyaq5{^JRa7d<|J~zKRGRaps0>?*%Ce;> zku62#*iv*0TZ+oFrKkd1if&~~QAIY2DiKgrnSi1y1Qb;zpr{%FMb!x?N+O`B1_4FM z1QgXIpeTiaqFMwL)h3{*4gp1V2`H*ZKv8`HiW(45)R2IpMg$Z!CZMPZ!Btcu${U<# z6cw?5e^JRO_mO@_JDNrXtS_smMU=nV0x4?A`BK!1Ek&)_Qq+bmMQzzq)Q&Ah?b%Y) zfh|QH*;3SrjiSy36m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&z0BF9Aij6HwHT zfTBAHD7uq?qPqwvx|@Kadk84Hmw=*F0*d+*P?Sb+6*Y_Ub~iwRZR~APb1AxLzQFkg zLS*yKv6aUMPmsl8b?6U{R9+^C!lBo0YwuDD0+Z^qDcf4JxD;&WCDt&5KuIgfTC#x z6g@;h(R2ceW)M&`lYpX!39h0+QQjp6NN}h9u4B3s{c8Ur{#j80>&q&7G|KG6wPN#(E_#RrE-d_j3az*v3rX94TsNANFsH3RquO(T*tpKTD-(C+ADi^K2>F#g?MoY$@8q zmZBHfQuHEQiuSUl=q0ukz05|@D+Cn1NjV_NK|s+V z0*Ve3P;`WVqBjXBI!Zv%TLcsxBcSMQ0*a0kQ1lJ~MJEU-dY6ErlLS}M_9*Wy%Z#Gw z_8X1QNzr!u8122Nfc0e+eHi6$wOoom;(RIkm@P%0u%+lzwiKOaOVMX+Df*l(MPIO` z=u5T~eZ@x683KyFCZOmW0*cNOQ1mSUMc)xn^gRJZKM+v#BLPJ}5m59q0Y$$MP;`!f zqF)Ip`i+31-w7x>Pe9QH0*WpYP;`laqRRvnT_L!NPDOc#8X&<&7S0D!wA=n@_K&E5 z^<@?P9p!&yr4(J`d?~ulmZE>yQgnkYMK{?}WbW9z{|KBEdDv1E!ImN~TZ(*a6!{4# zDnLL{fPkV%0*aytC<+o#6iq-;3;{*41Qf*)P!uAdC`>?6JOM=s1QZn{pr{Z5MTH3{ zDndX}Q38sJ5l~c|fT9uvSJBld?{)(uc--DE`b&yR*ikYVu)eIKvO)j5tEDKB^QEX9 zTZ(RBOHp~Y6jfkL(XDJLs>qh2N^B{r%$A}mY!p=`pr{%FMb!x?N+O`B1_4FM1QgXI zpeTiaqFMwL)h3{*4gp1V2`H*ZKv8`HiW(45)R2IpMg$Z!CZMPZ0Yyy-D7uY+qGkkF zQR$%fvH=o&%ijEy3A&H;H`~!X7_h#qqSirw;dN5fhV!MUEnAA(v8AXzTZ%fcrKlrY ziaN2Ss54uNy0E3FD;q`K2q@}KKv53@ih2@I)QfPaV;3{ev^fod;g7$AJ^0h*d z9qGY<^<@!CZK2v0Yy^@D4Iq<(L)3jO(&pe z1_4Dg2`GA)fTCFh6wM}}=n;aeXh_gI)c^^uwKqRQrD(mqlQbt7u)eIK$AkWL8>DC+ z=S$IiwiGR3OVL8M6fI&)(GzSbTFjQBC2T2L%9f&KY!p37K+$pnidGO%w32|LRRk2R zCZK2y0Yz&GC|XBA(NhEzttX)9X#$Ei5K#0C0Yw`LDB46o(PjdQwh&OXm4Kpc1Qb0> zK+$%Bt7vY}d&B? z+roKXik9U(U<(GUFRSR2pg(Dg6n)D1QgoUvMW3;y=ySFdeZiKZFWFM`6kMX;sF%a$S^TZ;T_DJsC0q5vC3kpvV)5l|E) zpeUMvq8I{-VhJdUBcLcmKv9^0qId#|5(p?NNI+2`0*VR~P*j9~qM`&86(gXiH~~c^ z2q-E^Kv5|Iib@k)Mc0DfWd=y_l)WvwE=5bs%Y0>`1J;*SbW61VrR`Ewp7W)s0$Yl1 zWlK>-wiH!jOHpOE6jfnMQB}4SRbxw0bvBBU2q>ySKv6OQMKuX1N+F=A76C=I2`H*V zKv7)+is}(iRG)yN1_Tr}B%r7f0Y!}oC~87LQBwknZX=+m839Gj2`FkoKv7GAt0*zr z`=tRA+-rXtTQ1str2mk;Eov1Vu)eIKcG3QuJEW*R=SxuswiI<_OHn7b6m@1xQ5Uup zb!AIYH?|aYXG>8JHi~)@P}GZnqTU1)^&z0BF9Aij6HwHTfTBAHD7uq?qPqwvx|@Ka zdk84Hmw=*F0*d+*P?SbM(EtL91`<#-h=8JW0*VF`P&9<#Dryt$t+3N5`q}(m; z`w1u-Pe9QG0*WRQQ1k!+MUx09dXRvk$pjQlA)sg~0Y%dYD0+y1qUi(_%^;v?CILkc z6HqjZfTGz16g@&f(HsJb9wne?F2PkaJlZ?l0139Ve;DLGDZ1U>NqQ_gV0~Fd3!?px z?vbK}oG(R-*i!TaTZ$I5rDzFTik7maXc=3Io@7hWa<&w$V54Xy0Y$3_C|XTG(Ha7Z z))G*(j)0=42q;=lK+)3#6m1}&=otcvHWE;@iGZTb1Qcx{plB-rMcW7{dX|8q?F1A( zM?ldI0*ZDLTt)Muy*mt$;63)XXucHHw_nkoj}BO0R?!R5{`X##q8B+|iuSUl=q0uk zz08)PSJ+bYDqD*7v8CuWwiNAWOVI%~iVhM`^g01WZxB#)h=8KQ1QZ=1py*8kijERc z^cDd{#|S8Tn}DL@1QfkPK+y>Tiryul=p+F}?-5Y+J^@9i2q^l1fT9lxDEf%tD%u_G z{lfqW1}vOCQZzm10b6vy`m%~Xi}n|NS&BaAd@1^ZEk$3lrRXcR6rEv9(bsG#`i3n< zXW3HpEnAAdW25MM0*Zbhpy)>eihd%X=w||oej%Xf905hY5>WIT0Y$$PP;{Pvq6-8R zT_m9B5&=b*2`IWkK+zur6#Yp+(NzM9{vx30Zvu+05nM%|MthqWAi=%%yN;)&sJbO} zJvv~0Sw&8a|DIQ+$P=SS@=_GRmLe}(ihOJ-^0TF=09%RzY$=LlOHmYCih^tuMH5gI zLqJh10Yz~H6om*V3KLKiPe4%u0YwD~C@MriQDFj#iV#p#lz^gQ1QZn~pr`}^MI{L+ zDn&q1X#$GM5KvT>fTBc#tLR3w_aOr$c-H=b{hLx$%e>52E+$}oSw*+T_}9NCMHM+; ziYl?Cs4`oMs<5S~DqD)Gv8AXwTZ)p{QdEO2MagUw)g+)Og@B@31QgXKpr{T3MRf@% zsz*RkeFBOa5Kz>RfTBhO6g4KGs0jf@O$jKvjew$N1QazVpr{1_MJ)*^YDGX%YXXYe z5L`v&W4uQVkl=Inwx~jk`$#__#*DTx0qe^u>KNny>3|e<;(RIU%$A}qY$@u>mZENK zDeBIaq8@B1>dBU(UTi7q%|=ll0*d+)P;@&1Mg0gUx`TkCI|(Sdi-4lL2`IXUfTDW| zC`u)us6PQkX#^AvAfRX<0Y!rdC`u=wXfOdqLkK7uNd?u z*#s0lLO{_R0*W3bplB`uMUN3s^f&=U^9Zh@kul!h21qc)-k}~PMXl_Z9}}>?tfD7k z{9_MG(PGY*q9tr8TFRE9Wo#*Wk}XBc*;2HEEk!HYQnZRKMXT8;T0=n5S^|pJ5m59L z0Y&QxD0-TJq74KTJwrgzMgod95m2<5fTAq~6m2D-Xd3}V&k|6yoq(d}2q@Y?K+#SD zik>H+XcqxRy9utMg)!dc21u}#{d3ogr09qpdtw6CmsRvqjQ^E4rRZhOm!enLQuHcY ziuSRk=ry(!?Pp8T0k#w!WJ}TOY$+lz^hQ2q-#6K+)R- z6dfm^=p6!zP7qM^E&)X+2`GAxfTH&aC^|(z(FX(+eMmsjM+6joOhC~m1QdNra2356 z<2_@51WVhSpS@C4#=OjTIwoL!Sw&yQ_&vv@=qt{bqBCqM`kF08->{|VEL)1cWlPa_ zY$^JlEk!@DrRYaCihd%X=w||oej%Xf905hY5>WIT0Y$$PP;{Pvq6-8RT_m9B5&=b* z2`IWkK+zur6#Yp+(NzM9{vx30Zvu+05m0oUfTDj0D7ry#6@4D#t!RJ*m-`KzFQllP zeWZUgCSZM8Mc!C{yW>*ii~aW_eLq`@3b3Upz?Py&wiHFNr6|ajqG+}h#jvF)mW`q~ z0*XQe6om;WiYK5bfqNs5AjZ zWe6xLOF&T~0Y&8qD7uA!qVfb+ktfzW!T<>_wQwS0-N$GJ&C7fhVguHfRa80F|JVsB zs>1oYEvm|vqH1g@s?L_8B(@aQU`tUlTZ(G3r6`3hMYY%{s!c#q9RiB#5>Ql+fTH>Y z6g42As38GGjR+`eOh8c+0*aavP;?ssMa>8(YED2=3j&H-5>V8NfTGp}6ty9ss4W3S z?FcApPjD4gjP*WmfCQ^pIF+R6s{H|fhuDDiWfgUa^`AN^MO`^xin_6-s5@JVda$La zCtHeov8AXtTZ;OyrKm4kif(74s2>4EcMwo?Cjmuw5m0nD0Y&!^P;@T=MX3Z7^(UYx zjew#71QZPQMd<_-4JM#y2mwVy2`CyyK+$jlitZzzXaoU8BMGjePO;vr21sy} zy)Ei2MfTf7zEQCO>&q(2jP(~kB}G}BFGbmGDH_X`qH$~~x}PmYB)XgdK#&k<0xgMgx)1Qb0_K+!G& zigpuFw1Dy?9P6E7fCP`(?>a7#qFwfp{@&Pt^<@>k8tdQiu@vp&d?|X3 zEk*m;QgnbVMF-hZ^g3IL-e617A+{79W=qi#Hj3UPpy((8MQ;&Mbc}$aw+SdZPC(H+ z1QeYhpy*u!icS(x^d134?-NjTih!aI2q^lHfTE8GDEgRyqE84Y`jmj8(*zWKMnKW$ z1Xt0^vEE|_Nbn_l^Ye-neQ19i@(Rl)jE)Y<3k$|F01QcB+py&z# zMSl=b^d|vDR|zQki-4lP2`IWoK+$yqivA&>=mr5rHwh?m;`G2AMIM5y=&M+7__R^< zg1s#|BSl}>d)EQl*fTCLnC@N1tQ3V2uZY7|oBEePUi}Ut1K!PhR9DkhqNZ;JkHV@e10@jyR zR4vYb|Cdr!o%5wAi7iDn*iw|tmZF+$DN12WQ7yI<)n-dk9kvwJWuvGb0Y&u*C~81J zQ9}ZX8WB*`n1G@t1QazTpy)ONikcBn)SQ5#76cTvB%r7j0Y$9|C~8AMQCk9v+7VFH zo`9kb1Qc~7pr{kURa7O;yV3v&_O^f4v8oikZ%K8I3s_%PQTI6izB5wPgY%`RCtHeo zv8AXtTZ;OyrKm4kif(61Q9rg6-NBZkJJ~3@i-4lL2`IXUfTDW|C`u)us6PQkX#^Av zAfRX<0Y!rdC`u=wXfOdqLkK7uNCEK+&TF z6wM`|=rIC{9w(q^9sx!32`E}XK+!@1iWU)2^aKG#iwUlxtT=CF10-0+-WFv`(J_1P zdP!Ws`m&0a$N4*aCq*kbUy4?;rDzpfidM6wXboG6*0QB&9b1Z?VoT9_wiG?hM$rZW zik=~$Xd?kdn+Pb{OhC~V0*ba0P_&JJqGt&x+D<^xa|9IaAfRX`0Y%RfP_&DHqTK`( z?IED(1p7l-bdW7Yud}7-4Ym{=VoT9swiF#M7YHc2NI=mg0*WpZP;`ZWqCW^I z`jdd7s{|DNML^Nt1QcB(py)aQMgI^`bc2ARn*g4y=2P-Mt`r2m*DRW%f_ zzO14eA%EI$Qk2a3QdE;IMJa44s>PO~+H5JR!Y8mZJJ>DQdt*Q9}ZX8WB*` zn1G@t1QazTpy)ONikcBn)SQ5#76cTvB%r7j0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7 zpr{i8MV$#K>Ow$KSAwgkddT~*0TSF`AEPBn(MLHC*g^s8%PQ&>@^3sZMZGy+iu$mn zs4rWJZf8qTKeiOz!Iq*s*-~^DTZ-;xOVK@S6x~ZeQ7QpN{Rt>aBcNyi0Yw7|C>lgS zQ91!dg9#`aLO{__0*ZzaP&Ax?qWcIa8bLtONCJvR5m1ytK+$LdipCI7lu1BQ7Qt22 zBji19fCPuy?_KwlqH^}OC_5CezO170A^)!zrDy`@OVLEO6g|L}qDgEidXOzeli5-< zg)K!>*-|u(EkzHpQ8b-^q8S7f%_N}cVFHR~5l}RnfTBkTD4Ih+(W3+u%_X4dF#?Jn zC!lB^0Y&o(C|W>3(Lw@>77TUy-8KoG(Rd*iy8XEk*0tQuGvCiq^BG=xMeTZD32$Gi)i^$VSm7 z0*W>hP_%`BqOAlJZ6l!QSptf-6HxRV0Yy6qDB4Lt(enfp?INIPHvvU^2q=1ifT9-( zDB4Rv(Mtpry-YySD+Cn1NF9|66ih!as z1QdNuK+!h@SJ8oxceMc$Y+@gl9h9PL_O|G3C}4eAML&f6`~Q-nA30x&equ|}&ul6B zg)K$r*i!T>TZ(>TOVRIaDLT)Vq6=&kT_m9B5&=b*2`IWkK+zur6#Yp+(NzM9{vx30 zZvu+05m0oUfTDj0D7ryF(MrKliViVCr% zs4!cKim*{slz^gQ1QZn~pr`}^MI{L+Dn&q1X#$GM5KvT>fTBbKipmjCbPEARDit4hZs2*F2>a(S&0b7b1vZbgITZ$U9QPhNhqNW5C z-9|uBGXjd56HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*Un zrKlfUitb=b(Vc85x{EDEceADF9<~(S%a)>4wiNYeqbQAlq5%XH4J4pw5CKK$1QZP> zplApIMMDWF8b(0TZ~}_%BcNym0YxJTC>ljTQ3e4;qX{S)LqJg`0YzB^6lD`oG?sv( zaRgUU@38j;10*=t{^+ca6vf&{`uB$e)|XZEK-m9rgcMEUd?|X6Ek%>rQZ$7vMN`>Q zG>t7q53!|aI$Mfnu%&1w8$}NjP&A8xqS*u#Jwiay90H0SC7@_70Y#4yQ1mzfMe_(K znomH{0s@K_5>T{=fTAY|C|XQF(GmiRmJ(33jDVsi2`E}lK+y_}}D?aKQSqiq?kxrOjUlk#k$Lj`OAHDYg`?XG_u3Y$@8nmZE3aQnZmRMVr`C zw3#hMTi7VtNwfwx7kv3oGnG~u%+k(TZ-Ogqv#|7Meh+% z^gaParwAzefPkV82`KuAfTE8HDEfqeqE87ZI!!>)X9N^|PC(HY1QdNqK+#tO6rCZU z=xYLsz9FFKECEH|5>WIV!BzA|*gM+*2^O%oMTewly}ft+eK=r!Sw%mG{hOnt=oikH zqH}C1`jst3zpK(RBif{vn{~1_4Dk2`F;n^{^d99s-IY2q^LrP~;<^$WK5~0RoBw1QbOQP!vT# zQIOy&`Z4T1VSofP%=G;vMfL3?{pk3B^<@=>;{CrzOHr8fr6`^)MG0&vD#(_iLTo82 z%$A}eY$+0Ra7V5UpG#Q>TQB$@Q z-Nr^yGXjd56HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*UUgW=qj5wiL}~qv#O=isled^e6#Ea|tMVjDVuY2`HLJK+${x ziWU%1w2*+JMFbQ*K|s-B0*aOpP_&eQqGbdWJxM^(asrB05Ky#|fTC3d6s;z>iYCQ- zzc)aF@%HBDK`9z#$C~(n^<@>UkM{=(OVQJuFGU;JQuGX4iZ-&PXcJqCHnXK@3tNh| zvZZJnTZ*1#qi8z;Mb8mXw1a@6odgs;Pe9Qw0*ZDMP_&1Dq8A7#dXa#ly#y4!L_pEY z1QfkOK+&rN6zwCR=rsb0_7hNafPkWd1QfkaK+zinSJAq7Z*>DCSj_(E{imd8pS>+Q z6d$m@tfHgw{w_tO=q=8dqGN0+dYdgp$JtW!4qJ*&u%+l-wiKOYOVN95DSDrcqEiGE zeLz6bhXfRTL_pEU1QdNjK+&fJ6rCoZ=raO}J}02)3j&J1B%tUk0*cNMQ1mqcMc)um zbe4dkZwV;+j)0=?2`Ku3fTAA>uA(FH-b@1|c+fu5e^ZM7HZSx26d$m@tfF7z{fmlA z(QlkDMZdG9=sa7BF0iHOB3p_sv8CuTTZ*o*rRWc~6#dCY(NzM9{vx30Zvu+05m0oU zfTDj0D7ryF(MY$+YS!vG0R zwBI6%PjDaU&op>^wG#r?msM0h!C$tF6gA*{DQd`;qDE{fYRs0RCTuBc%9f(r*izJt zEk(`QQq+QtqLu^{wIZOXH33C!2qPtY;?F3g*-2`uI10-0@!l@@k=k0A#zl4DG zWfk3>;7>RIB5}^o(eB}VDY};}MX78l>d%&$0*dY@ zplCb+MH2`pnn*y=0|XRJBDjj~Oz_SzK!RN@oV%pxetTE@!GwVIWfe_J@Nd0EiXP&8 zDVolfq8V%{n#q=;huKmzi!DX7*;4cfTZ-nerRY&Mislkf^cVp}j}uTdkAR~21QabG zplBfhMT-b1dV+wW#RL>BA)sg}0Y%FQD0-5BqU8h>tstOiB>_dN2q;=jK+zfkiq;ZP zw2t5^nv&o>X@CU3H`6y&ihj4_sf2*_<-|D=zVcBeD|(#JM)MBIZlI6bOpz066#UWahivgR(71$p)aaBPWw>#B**C-8kX!h-9yi% zI8N`-mD-NeFVwi6eJ70mW5W_ z={PGxU*GLGYeSV%9p~xL$TY{<6xub=akhp2N_U(cp=LuJXLo4kaL3sjdV7T9yc&wn zaGV37+s8Q0q0p)<$2l50JJxZIhpL!=660hjW1{1H5ZW`zaXtxMo9sBBhgwW?oHL>>|gzs8!t_Dwd-3D_#c*6Eyv#;O@ z+kcL{vL|f+J?ZM6u>A*tYkI==Uv#bG3EO{?vwp_sfp(gzaAtI@%Mqf5T(8Cv5+UzVV*0{X5nsdBXND$(rg3+rQ;#h9|u5jJbw9 zVf*)t%=LurUlcLl6Sn`S{}Z0D{a>}0dBXPpwO#26+y7Z|ttV{%Z?~sCVf();ZSsWe z|8KI*6Sn`uzz$E?{)zA1p0NERyL&xh`)4j+^@QyonmgbL+duVm$P>1IY~`pYZ2#QB zaZlL(;P|8`Y=83ifhTN#bn}TPY`^#ZxhHJDd3weZw%`5w))ThhzWC7-wvRv0dBXMq z#CcEH-UGbs3EMB>S3O~S8+_g4#D8sm)A*itf6FCYG{0*+wM{XfGxN){vS6BdaN?;O zH_xVmMxEoSr{S|Nsjo57Yes{(={c|VpnWS1^^!{Ft$7-0EVt)0)>vmp6OEo8Gn#6g zGry@lw`r^jn$b*Su)PG$-C>@K_uLv+FxneeGOkb2c%#B`A}To1(YKl8INlg9DiNMmI4Jm(b4WJc+3pMI^IZLKRP-#Iwrb-`A8y*{_C}(%xmR) zt3ge_`%a?uCe5^OGDdGQ=cRdXGFER=uN7xb^5m5RrE5(+dgwzOq&a}CwWci~EzH{p~rzwAw<`S^4GYyV@f+Wb%XxBb+6ogU`D z5uR&tv5v<)nb)<~PK_GLnQ6&`vqmRpWe!ZvOwAgYo;o@+BRhRycKV>?fteFVXJ^#d+eZL8Ohlh86yS`O&c~UD|yJkfvIVkBa>5Vrq)iaRkKz~YD!HT zlT1t+l`$$kDLrk#u%wilHEJi>7uPT^{@06=hm9IIV(g&wuncFgd4n=QmkKbSLe|z$K3V4Tj z{0ZKYiOJ>5m-CKG^!p2R@+TB9ClzRFj)lsYXOb2EZ%2EAJu%t5*+Tw=yi+~N5z$6> z&o=E++tzIF*kekAn(b2uxX;$BllyGlR=LmCYoOPx(}323lWW#-U)H9TUMI!8^03Ys z8KYC2E-m_{w(8oumix9_b4uOZ_g9}(JMaD0%6-4B^1Vr2z*?M8FZZDkzy`P&g(Zcua=r>&aPc6)qM*o=ACguTi#j= zy|tEkZ^3*9%&QF=J96X%_busl>+p_SDAdor0Ok{#`<8RxNgdut>%32f`4s3C%|&)U zjpnVm&*ZxZ^*Pmi@^W5iKCwElZtfd1mxp&+ORrx$?{c)tJtL(R@5)?oonZy!yY2da z^*gq8`hc-R+>ge5{>}R`Hv;*t09}qcc^A!G+3u_7ek`b}nfIYI%)Qtt2CUPm%^j&N zTKCL3&s>lCh>TY~*ZN;)IwLYh4N1)T&wos%)!nK&$$38d6ZI&CAZb&g?YMC+H%$8q2k&yAB1}z&)BOa=cXs`sx`Mpx+p2; zvhZw5-e)A=6>F&5_vtd9O!s}%;+^GP`6+qVeoDTp-&{lPDS1~k*F#E6 zee7Hd4RbHA`TXkQ=G`c971hnVJnq$>^HJwr<0<*B@_biyJ##_w9CDMEf*AW^`-aRh z_Y9iPC+ryf4kJBrbyaK+HR|Uy6I1FVng(Tq<*A=M*a_=Zlp4wW&?+ zXUkl@`cU#dJOG(bzh0IL#azGcd&q-lZjj7t<-GBn7a2G@%Y5z7bGe@-gW5gc-26J` z?p~(*DNk_^`oftwK?3RhGvrra;s=J#OEtJo_% z=Tm7u8}2jteC2sc$pe*=CyJ{(#a!5&lg(H3oFkv{6!V+IeXIGjxH#-PHSb)Xn-p^& z#C=8cn_ti5ehO3EYuBEU?^ZrVXP9d>?-OjEYuB|;VylJ?6YV|Y8YzkPzH!Y4wdy2R z&P*SXo|ctfB{6B_z|muy4m6*!^zlg}Yu7d*d+6Aa1I%&oh>W!CBy-2QskvGP*zXAjF5m6T=f)Cv5C}rEYC|<$l3V;f`kBoyNTTig|Yx&7Ds8xW5bR z#mjZf-ORjufcfqKaxXLQ-X6ap>>WV&6C;T3J-wWd+}^#^JjFYgW?sB^FJ-20QccNBB)6XyHfllOZd?;c&w6`X2s5_O}Q^HJs9 zyUV>A-MffRyH>3lC04e-ds<|UOl&i9K>DCT=B{;b9+Kw#hT@@SmH+*>mwEIPV}9K< zPaY>?Qk?m|fPG-jlYIc*A}(fzcV@)Ho_miRK4iXo(W0S=Y4-7~<4HEp`Wqy5snMlH zhptY6_&}E^Z!j{!SIAS?Q`B3`Q`}R+Q_@q)QzqgTPYwHU{eL{=Pd?|u&HOL++6Q#` zp1k^Y0m*A0&*gjan#XeS`L_MWg881RW4@cIr@U`8*x+@{H!$)&c^&g@pL|bV$9zL3 z-;>ud-|xxyWWJ4@Z`rqJJ~{cGyiPdZvM&$)kDcI{?+fL8l=kzSU>}SA&&RYCvYiTp zoSy%ZVP4mMBP_yxJJ}x1x03D0ZI6X@G~aP?%%e!BoIRRXs;q9WFZ+7tJHk0f^L^l) zV@n;o>)1y}^C&y#<->I}->uErQ*@l6<9r?0>$uZ?o5sAKeL9{pADZ1?>3GF_0Cs!K zr`#TknvcaE%j?+CTz0$L=y;cT-tHkft~H-ZyPwtZd-Dmf`;v~;%@uEVLme~Cx7F>Q zqT^ok4R*T^>v*GtyQ53G$JXYX?)K$9bevPx-Ai>mX+E*`v(rXcMsF? zDRTwb*MCmOAFI0iijFms+}&8mY;#4~*Po{2%PH=DQ%9$cyJK~1YpziH`n`0V+rZsV z>iB*mcYmd0F>}S+*S}TAdz-oYJ{_NK;qIL}{@lvlf9hDXt-G7*IIg|Br|bA?M|Z!a zV?-BshjeV;&E0);e7uLdSLpabFL!^fV~M`*uB2oCe(oNr<1=@c+oGTdE7#{py9 zouT8VEO+nG@wc(=zNTZH@$PP+JyWD+`j!X8qd%cdIzv%9tbiCzdcPHyO^i_9{)p7f4 z?tVqb%Lm-;Ip`i6z2P3)={WVUyC2i>$eZpyrDM!7cNf>O=W%zZ>bUHLyEo|gn&o-setvL1fbvEn&**Vb{wZ|rCT_s2Shue-anj(u;qd!UXh%~y5%_BZSJjrpmW-M{Nt*?h~{?z%dT zGCxPN`vDzyn;)pzeNe~0%}>_s4w(P7#U7iRAFJ@z>e$cx7|!l=9ao#5$JxDA$8XIK=Ip+pV^#ALI=k!ZI6BeY59;`W`I()4`5QWx zGCu*gyNZrA?a}WzjkVkB*hj|!I%eoNNykTYT%zN89e3!sPsd|A7O?j}BFzt|?9seG z`(%&iZb#0szr8H!NvL=koPBY&H$;!@jk3)IRJnqbPYS;&QPK^Os zSxyZbYW({ySq<}WwZA@N1)pMRt8!#XUIqlToLH(#?0x^PM#~Gi{`Kr4~KA)JV(D&Kx#iY_@r`|6iZX-5ev+y&q}M zF?S>W^<+LxIZx%xf9>me-T9x_voEtxmCP^mY5%{zUUl<2|MUIcZ5mJZda_Tg%`e`z z-Sf?_Pt0}96VEj_!Q5qZ?9o0QZRl}|nNZL?Z?As)_Uz^AZhmo&dDaWsI7kGBS z|9HJeD|?(odxD;Ly?f2h|9;Q3^yHYc@7KOR-tSoRJm;8aovr5WS(`lZvN0y)e|zWi zy}h7$8E!Y1ST@f(YmJv% z?K67f?b&nkzg{tO`Hu2R=E&>if4Ek+Mn|(n&e!%( zmqQ&7cRPIbT%tL4)$!`Nn&!FD=2w67%RZlYprifoe*52??Y%O~yRW17O2I5s!dnI$ zzIv$UhgW?mPPJ>Noy41e-niNFkAQbi*B3f&?Qr<2<1sHcZ|h8Awf@mVmwB##(CzYp zzODWkFt*#}(fzk~daC1zw1ZcDJr0_GkMy8dc;AJIraxeMxv+g1eSU}cuKLP3Rj-|Hb+LTn{9Ak%Ci#0^y|w$nt4_4Ubu>lc77w9r}yZq4D*&Qc#IFi<8V9Nm=hcAq{{=xmZ@56Uts<{-? zBHT-NOQLx%9`mc5@4`c-PybIJntP_bbj8f2o00pTeHUitd;Z~k&(F$zKC*wmoJ+Sf z_tMQ6o7S;c?xkB|E?u|W_u;!R+gyrA{&OjO7v`A$=zn^P+%xT^TVO8T+}!u#=>rhL=@#Z*x|U-Lb@b(4x~1mQIUUNKal%EK zPp$3Ld?9OwC((Q_r@8qZe9Mxpp62E&L6ILDcs$N5r_^mR&H=Ay+WuMYt>%GvXX=3j z^Q*A=Rm7Q!LEnXC=3{yCKOc+l!gAAB{HHJZ*T=Zfe2gn|FTd}?s(jC{&iDM9+~*_v zKb-S1E^$A`o)2|+JuUCDtTpd*-GAPv@4{22um4Za`qyPyWG>6ox$nn!VMD&>pUL<9 z#@y#4`wz^op=av9F3TqKJ~#j8eflnJF@5WQdiQ@_mgVNMY|DK=z6;OhdwzSq=by`c zKC*xFoXeu$)jga1>$2=H?{nvW-ly-v^QQ0mPfz;SWm#b^%kJFwuQC>s8044&ffO;JK9^&$o>U~u5cCfI+b>HpR?b(ZWA-rsbcQ4xL-ego`Cs6 z7E{aI)2NgGtDgCy5#cFtzx|$>CvuLt-w+YuUmdWAz;qM6Ma&nJh%Uvt*w^#<_nMb@ zm)Y0qR=j^s3i#}b^uJ>6Iz>bVYM8HpKA+!yqddYFc+b3wx14zeZ}oyL?DJdAyY|*B z)Z0AopJ)D4!2ZX)|9^7IKfp(nT z=HfNfjeE?-maD7($&yG=XNZgcsXX$R~!m#?{Y z0lUrRYoYD8+g!eu+CIC@i$+G-mHQ9fS< z?+J7L2NzjHx4QrH&pGq(%-1fk&AfsY(#e0qc+L^hS*J=!7flK2swpAeG$o|FriAp+ zl#rg964FakLV9aTNFPmv^wmbl?b-)Mri6^sl#u&1C1kv&giO$s zkcpZIc|aQ>le7`?pf*A#Ya?WeHbSOqBV?L3LLSma$aHOl%+N;2Ol^cbtc{Ra+6bAg zjgUvQ5i&;`A&+V!WUe+s9@9q1MevPx4zR%=Sg8cl?()kerV zZG=3fjga-)2zgo?Ase(2@{Be@HfkeelQu#&Ya?WfHbS;)BV?O4LY~z|$aZanJg1G2 z9oh)lsg025wGpyQ8zH;35wb_y6|%@%$6WuxiuN|-30KHM`}_+5E5{0X*D1GAs=fa zKq|wbgG1Wttlbj zXiCUgO$qr{Q$oJel#uT=CFBQ93Heb|LVnUj$j{mc`9&Kc=d=;>t2RP@(?-be+6XzX zjgSl42)U?@kW1PKxvY(lE7}P8LmMG~Y9r*THbVZ=M#$gV2)U+>kn7qA`9~WeH?$FQ zQ`;5tg?ECv{)6w?`yOBB2#KC;Z$r$VPOx;G7@yDQ@h=ZKPON=2{4c%yX8^rl4hH`HI~cb0P$Rpopss>YV0>TD@WVoOmCwiG3^rKl!b zic;88REsS|wb>}DLqJho0*dMpP*k6Qq6P#MH6);@5dlSw2`FkpKv7cyif$vIs2Kr8 z%?T)KK|oPU0*YD@P}G`$qBaB+wI!ga9RWq{2`K77a1~YZc>M`R(Q12BR9TANwWKC5m0tS_r5%i|wWM2fOG zUy8=ErDz;mitcAi(Rj8LO<+sWM79(?z?Py(Y$jiSi}6ip$ZXet3k(+DVfh=8K$ z1Qg96plBumMGq5DG>d?u*#s0lLO{_R0*W3bplB`uMUN3s^f&=U^9U%KPe9QE0*V$A zP_&5PDjMVQE-*l%OPNR7zDy}aMQhknw3aPJ>)2BC6dOhB2`GA+fT9fq6g@*g(MAG_HW5&?nSi1#1Qcy0 zplBNbMb8pYw4H#W=Ljg;K|s+?0*am|plBBXMY{oUU=S$IkwiF#;OVL5L6ur)tqBq!5bciiQhuKne zge^sHvQc!DfTFhuC^|+!(c1(R9VejZ9Ri9@5K#0k0YxVXD0+{8qW1|XIz>Ry2Lu#- zNI=m?1QdNtK+z`z6n#oS(P;vTJ|m#$a{`LKAh?QN@pwy{Ke7~k(>`#2Rf>MG_pZP6 z1gtNs=o^p!HuJ}|b8d^ya=sLO%a)?=*i!U8TZ(>QOVN*PDf)>mML)Bp=ohvWonxcu zR|1NDBcSMa0*cNPP;`NSqKgC+T_T|9G66+b2q^l4fTBMMD7s2O(O(1<{Y^m8H3EvR z6HxRI0Yx_mD7r~NkrR>oDBpdI<{_Xcg5WATQl*fTCLnC@N1tQ3V2u zZY6MARFQz9N(5JtKf=4&0Ew<@e){e!5aB-3|JvRbRgMT)Ush4|2>-EiQk2B`QdEO2 zMagU_s>zn36t)!AVoOnNwiMN2OHp066xCy+s6GKj4G1V|NI+2|0*V?FP}GEgqNW5C z-9|uBGXjd56HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*UMlh$ z?U%RAh=BEF6^)DV_pK;J_jA4!jb}^I1hy1SWJ}QlY$=+=mZAsQQZ$(@MN`;PG?k5_ zX#^BKL_pDW0*Yo3P&AW(qK646nngg-YyyfNA)sgu0Y#4zP&Ai-qQ?j*dYpiwc?1;A zC!lBn0YwW5C|X27(Gvs|EheC73BgsA9pQbz0EupCzeO}wie9z1MN1WIJ0Yx7ZQ1l4_MV}H-bee#o&j={`oPeS)2q^lJfTFJmC^|!M6}=YW z4OBCV=GgB#?w6vz_TKf^5drJVD*7(MUpYyNzUO=?`hhJ)KeDChC$<#*%$A~G*iv+k zEk(bwrRX=d6#dRd(Rl)jE)Y<3k$|F01QcB+py&z#MSl=b^d|vDR|zQki-4lP2`IWo zK+$yqivA&>=mr5rHwh>*e++qrxf;z+)XleQ>`!Ao1QbOOP~;_`$VWhtpWrGw`+wNG z@93!Ng>U z$`epjfqs8WK>{h=8KT1Yc2%>#j3ELKE$G9b;Ypk^Z~(w&*-JXnk2l>8|%k zrW9pxz7%D$rKl-eikh*ds5x7TTCk<4C0mMGv8AXrTZ-DSQPh@zqVowTYDYj(djg6& z5Kz>SfTB(W6m=$`s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^9N5Kz>YfTDf` z6!j;dXaK=il*-~@~8%0?J6pbOED4T$yu>=&2BcLdUfTCOiipCRAG=YGk zi3Ai)BA{q80Yy^?D4I$@(KG^zrV~(yZn(KORv<0Y&QwD7v12qV)t6-9SLmjRX{JAfV_bg0JXO*UdFRLf=|AbEK%R{fc(88??Tx zqT5_=S!*fU#Q9RRnJqz$ZqWL&ik@@5gXX`~FZyZh^PDe5 zFR-QPMYa^}XG_sbY$}fO6|}yrqJ$`KL`Nw~yc zKv6vcis} z2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&z0>0s@Nq5>V8S zfTI2c6b&GtXdnSag9s=ZOz;(DM7hryAfd%(MrBITF?(AyBr0fqSw$B{c_+F`(Fo3$ zqKnv4G?Fbv7qg{k6kCc$v!&<~wiIQtrDzOWin7@#8cRUYI0A}t2q?-WplCb+MH2`p znn*y=Bm#;i6HqjTfTF1c6ip+bXgUE!c?1;AAfRX_0Y&))6crFqR7gP4ECPyV6Hs(1 z!B;da%8l)26#Z(y>o{DB#uPnZiwas_R?++@uW=74x}5W+=nA$JEnrL0LbenwVoTAL zY$;mImZBwWDO$>wqGfCpT}43AasrC3CZK2q0Y%pkP_&YOqH75#T17z7Y66PZ5Ky$1 zfTHUNC|XBA(e(rrttX)91_Fw1B%o*m0Yx_vP;@f^MYj-8w2|N|niu5`FhD}P>~|e6 zlcLl1*F4--)I2mwWp5>WIQ0Y$qADB4Xx(c=UZ zJwZUxlLQp)A)x3f0*dw$Q1mnbMf(USdWPUD+7#ukH$Xy%?QPL!DVk}&qCFcGw7#sO z7o)t#`bg1!&X=N>*i!T|TZ#^_rRWv56dhzs(W`7JI>eTu*Vs~Yn2n;>2`GAlfTA}E zD0+*4qPGbsdWV3bcL^wZkAR{h1QZ=5py+)9ijEOb^Z@}y9}-aX5dlTV2`KuQfTB+b zDEgFuq7wuZeMUgh=LBET^HJ{m21uy6{UY{)6z#B&^uLG-T3=StH&Nc1zEX6O^QGup zwiJEGmZI<3Qgn(fML)2m=ts5`on}kXPi!grnT?`f2q^lMfTG_BDEgg%qCW^I`jdd7 zGXxa=e*p8wA0Yzm9C~^rXiXx!MBcLdnfTAD)MKJ^v#S%~yM?g`C z;4Atn%B|JUC~9f`UXQ4+rRXpF6)oNiT3=RC*z>v!kfI3ZOHndgipsL3s2p30%Cn`Y z0$YkIvZbgJTZ$^PrKk!UMO6tXszyLjbpncN5KvT;fT9!vifR#1RGWaJIs_EeC7`Gt z0Y&u*C~81JQ9}ZX8WB*`n1G`52qSr4vw;LGTqNdhP@RBvj4*-gT1a zKhpoy{<2Y~7qq^tq86UFe2^5iPA3OcLIuf5Kz>UfTCUm6!j*cs1E@}7Z6a?mw=*v1Qhir zplARAMFR;a8bmJU5KuIffTCdpUr{s9z0Uv%y=iZYnoH46ds{Tz3tC@R(MZob zG(?In=6op{#g?McY$>{gEk#*uDH_9;qHMMljb%&GIJOk!uu+stK+$*tiY5?HG?9R! zNdy#4CZK2v0Yy^@D4Iq<(R2ce@(3uJK|s+=0*dkpC@LVJsE~l7Sp*c#CZOn20*dAk zP&Ai-qIm>g(Fo5yZGeOxvv-9qlA_`EPSRyw(E7597I6s;tn=vo4bRuNFNnt-A;1Qe|$py)aR ziq;WObUgt@>j@~jfq;MLXFjx}Sie2M8#7kbt6x2q=1(fTBkTD0-BDqQ?j*+C@OoZUTxPC!pvF0*am_ zplA;PMNbh>w3mRQrwJ(9M?ldt1Qb0>K+$sq6g^My72WQ+3k;CZOnX;os}$`w&x?A& z3tC@R(aWBTZ#^`rRX)b6dh(u(d%p}dV?)RZ?aMJ76CUOVMez6#c}OqMzAP^b1>xeq~G1Z)_C(PC(Hg1Qh*AK+zcj zivA*?=qv$6=LjfrqV=#HMF9ee$`DZG5>OOHK#@m4Q8WQXK>~_m2q=mrpeT-jq7VT^ z@dOkl5Kxpz@D-i(+|X#F$o||l>RTzg-rm(tiVj*|R#Dk#uSu2^mE(LVD$kap3T!E= z$d;l?Y$>YDmZBS*vKv69MifR*3REL0~x&#!}BcP~0 z0Ywc6C~8PRQ6mD18WT`-9sxy72q;P=peT)iqI3d^G6*QjB%r7%0Y%LSzM@F9JIDYD z?X~x=lcW7d`gQHY{^rp^>&q%?9qr|3OHmunm!h_8DLS7mMeW#9)SfLx9oSOTku61? z*izJ)Ek#|}DC$Z;Q8xmLx)V^;gMgx*1Qhimpr|(iMSTb;x`2S9z62EYBcP~10Yw7{ zC>lsW(I5hf1`|*;gn*)<1QZP;plCP&MHdoKG=ktOY8ma`Xn=&~+Am_Qq-eMOamYo{ zLF>yZ8XfKJ9w$YYaK02}v88AXTZ*#TQZ$w=MdR2~l*5*yT(%UAXG_rpHi{+^P&A2v zqR9jlO(CFYDgi~)2q>CPKv5n6MKcH}nn^%WJ^@7q1QZn#P&A8xqS*u#T}nXF90H2w z5>PacfTGI?D4I_|(d7hR(Z$j32L?#!QTzKvqok;b{fc%)bkO>;imr_I&gM$dV$PSM zC2T2L%9f&KY$>{mEk(=OQgk(2idL|t=o+>Ztz@ISutf*0FRSRTXs_EuDca8YQgk<4itb@c(YB)=s5z4o+qH_1pi4zX1|DV!xujB1P@(!~SohgVvW- z^h30Fc&Zfr$oW!qnk_{?v8Cu|wiNxsmZD$TQuG^JihgHH(I0Fn`jd^KGXxaR zfTBhO6g4KG=sW_7nh;QwN0Y&Kq6lD-llu1BQQv!;b5m3~efT9)z6tyJyipmAu z^9_(tH~UDxe9(WSpKKrLw+aTWFRSSMpf_r!6t&}gDQeG_q7G~+>d2O&PHZXa%$A}q zY$@u>mZENKDeBHfQ4a!&dJ<67i-4lu1Qhilpy&buiuw{z)Q^Co{sa^aAfRX<0Y!rd zC>l&a(GUWPh7wRTjDVuy1QcCJK+y;SiY_9cXe0qe7ZZF%ZG!G110?jJnNe+}=oWih zG%6UhzO14#LGShgDaz)2DH_X`qH$~~%3(`UE?bJmv!!SPTZ$&KrDzgciYBvBG=+eo zsRR^FBcNzH0Y!NP6wM%@XeI$g`2-Xd5KvS|K+!A$ie?i~bSVKva|kG!OF+>)0*Wpp zplCh;MVAv$bOixL3kWD$NbnV15_I<)AfdYUVOf?G9ksuNy(k#8zO169LGMfRFM}8T z1Y{ZKOVL$qDO%2!qN~|bw1O=~*RZ8%C0mNFWlPa2wiK;qqi78QMQaHtx{iRNbp#Y$ zPe9Rn0*Y=Rpy);diZ&2XbQ1wZHxp2F3jswN2`IXifTG(7DB46o(PjdQwh&NsI{`&o z2`IXQfTC>#U(w>An=sob+G1wZ5-Hkm?`q!}3|e1S(LF&gZH^S(%lT5YgDpk(v88Ay zTZ-;yOVI;tDSD7CMGvv1=wY@LJ;FxOqXZN^MnKUn0*ZDMQ1mzfMNbe=^dtdAdk83c zih!cM1Qb0@K+!$|ik=~$=ve}ao+F^>c>;=FAfV_)0*dw%Q1lW3MK2Rjbb#P1+8%U= z7$Bh|_P>q2oBKufuJ$Xzp!H=Hy%zKe=Sk6F&X=Os*;4cdTZ-OfOVL|wDSDeNMenes z=v}rHy~mcKBWx5MC7|ei0*a0iQ1k%-MIRDS^br9?#|bFVNtzt~cAmW`rw z1QaB~?BqXnk2lm18_-ffQBY zd?~8RmZEBGDXPwvq8e-|s>zn36t)!AVoOnNwiMN2qo^(cMfC_Ms!u>s0|JT~5>V8L zfTG3(6rD#vQ4<1+QVA$ZBcLdqfT9cniZTf(YDz#+GXjd56HwHGfTETJ6tyCts5Jpa zZ3w=iiZO0I10>Yl{*r8^82^#}VSDeoZA{SmvWhyycs&+LQAf^~qE2in>dcm+E^I04 z%9f&TY$@u_mZBbPDeB3VqF!ti^(LUG4*^9N5Kz>YfTDf`6!j;dXaE640|_V^L_pDC z0*ZzZP&AZ)qG1FS4JV-JLIR3L5Kwdx0YxJTD7u({qEQ4CjV7Sz5`wR&U5q=$015qK z;k1{c#rC!+D<)`tSw-Vwyp@ZkD2MZiorQZ$7vMN`>Q zG>wg-=>!zz5l}RPfTEcM6y+08R6sycApu3R2q>COK+&ZH6wM)^Xf6Ro^9U%qjDVu~ z1QcCPK+zQh6fGd2XdwYbiwG#Xl7OPc1Yc2hjQgMg5{k2Tg~m$Jij)^io`9nD1Qgvs zK+%l^6m1}&=q3V+ZYH4U76OVk5>Rw20Y$eFP_&7FqRj*pZ6ToOb^?mF5>Rvp0Y%#g zD7uq?qPqwv+D`BlEsJq~H9$f;0|w4jQdG~9x;rLleOX2K#dwvLOVLiwm!kXGQuF{@ ziXLQ3(L-!0dYCOmkFcfaQMMF4#+IU8Y!vM#py+V|ik={#=t%;K_7G6?6ahth2`GA+ zfTDc_6g@*g(X#{;Jx4&%^8^&VKtR!p1QhKjpy(w6ie4t5=l}sluMkjlkbt6B3BICx zW8C%zNT|P=Q9Gn4V!xstiV0d@R?!;yZsut^gy-JFz zbG{VSU`tU=wiKnXrKlELifXf^s193->awM%9$Sj)vr*K5fTD&36g48Cs4)RW=MhlU zgn*({0*cZIC`u=wD1(5aOah9U5>V8PfTHFE6ty6rs3ieKtq3S;O+Zl_0*cxaP;@>4 zMePW_qAIa&(rTk9&EBD|8tXsOA6xW*EjDO=y^OU|)P?hPaZ zfTH096kSL_(Fg*HE+U|4BmqSi6HqjYfTGa^6kS36kSF@(R>1mE+?Sq3Id82 z5Ky#`fTBeN6kSO`(P9FMmJm?1lz^gT1Yc23tb2DGXX`n5Ky#{fTCLoD7uY+qD=%8Z6=^-3jsy96Hv63fTBAHDB4Cq(VYYo-9_=>KMbw4&hLfy@bS|LR}?Zf^Zu|ez0DtaK+E3-k09^`x}dWbDW z53{A{5w;XP%9f(X*iy8MEk(Q8QuH`mik@Jj=t%;K_7G6?6ahth2`GA+fTDc_6g@*g z(X#{;Jx4&%^8^&VKtR!p1QhKjpy(w6ie4t5=l}sluMkjlkbt6B2`D;5K+$Ui6dfk` zigw1j4GfS_KYLqrzZ5-XAEUh<8??TxqPJtcUN=k8JDe{?@3N)nJ+>4bVN20bwiLb3 zmZD>9Df)mdMIW-I=p#0YjuTMyF#$!N5K#0f0YxVWDEf?mqR$B^`htL>F9|66ih!c8 z2`Ku8fTEKG6n#rT(RTzCeNRBqDFTXqAfV_+0*X!(Q1lZ4ML!dKMQ_Hs(+rSMZwu!w zDSA7`j9+4d)|XZEN36GMqZIwg`BHR-Ek%E^rRXeMiq5g6$cfVgY$>YGmZAo1DQd`;qDE{KH720wJOYZE5Kxp#Kv5b2 zMd<_-We`x5NkCCk0*aauP}H1&q80=cwIraZ6#+%92`FkqKv7!)iq0pXs2u@C?FlIA zKtNGPg0HB0ocp^068hTS{M3l^AL$>kqf=ba`m&0;#d%e>NKtprm!ckQDeB3VqF!t% z>dls-K5QwvfGtIR*;3SxEk*s=C>lUO(Le%<1`$v+n1G@o1QZP=plBEYMZ*awx{!dP z5d;)nL_pC<0*WpsplB2UMWYEQx`cqDECPzg5Kxp&K+#wNipCL8ltb_pb%}F38XzJ2 zHx)&7m7=@t$c+nHUslniIB(2WDVogrQZ$7vMN`>QG>t7q)7es#$CjcQY$=+_mZE&N z6cw;hR7gP4ECPyV6Hs(10Y!5ND4I(^(L4f*E+e35J^@9S6Hs&o0YwW4C|XEB(INth zt|XvnF#$zO2q;=gK+!S+imoD{XgL8zR}*|i6XM*Z21w``d-F3ao)+hr05aOm!e16 zQuG*GigvN3Xg6Dm9%oC@6KpAZk}XAh*i!Tq8%28wD0-TJqJ0DuJwrgzvjh}9M?lf@ z1QfkMK+%f?6zwOV=p_P*UM8UE00Bj>5KwfGfTC9kC^|$y(Q5=09VVdYbpndsAfV_? zg0JYoI5)E0DEh;~c}R-xDtf>c7qq^tqW9vwruRtE5zd#QqiiX9pDjhl*i!TXTZ%qp zOVLMcDLT%UqL0~9^a&e9pAt}Xf`FpW2q^lTfTAx5DEg9sqOS-j`kH{EZwM$lNkGxJ z1QdNoK+*RE6rCcV=m!Fdek7piGyz3F5m59q0Y$$MQ1mMSMZXbzMeoG97aAa;Uo4z= zr6|#UdHX#sXnk2lf5mxoc1Y1#&X=NdY$B)YC%9zO9F~o5m3~cfTA`86tyLw=zIc-+7VFHo`9kb1Qc~7pr{i8 zMV$#K>O$}prG(s14UkYDd%vhw$bY22)!r6$4F#<)tEgwli+WIsdU3uK^=3;^AGQ=- zz?P!EY$@u;mZJV_DH_0*qJeBF8pKA?U;>JU5KuIffTCdp6b&b!=t2UDMi5YR5dlRb z2`IXlfTB?Z6pbdJ=n?{ovIr;|LqJhB0Yzg8C>lpVQ4Rq`xdarAC!lBo!B^BhW~*-})%mZCzo z6wP8w(QGz~E+wF74gp1T2`HLJK+$Cc6wN1~=yC#zt{|Xj0Rcq|2`E}bK+%;16fGv8 zXbAyDO9?1iMnKV31QabNpy+A>idGO%bPWMTD+#`$$ssq-00~X8KgORTMdR(Aq-#S# z>&q%y8}imXDn-|Ez7(xvOVRagDO%5#q8r#!bR%1eHn64WCbksa%$A~C*eKdaK+&xP z6x~KZ(Ix_lHWN^^g@B^l2`Ji1K+zop6m27*=uQHP?joRQI{`&^6Hs&y0Y&!`P_%=9 zqWcIa+DSms{R9*}KtR!h1YgnWko%|s5}IXii`GbyYrmpB6bf2jR?%Z2@10#zw2Skl zXg6Dm9%oC@6KpAZk}XAh*i!TqTZ;CwrRZt46zyZ9=otcvo+Y5@IRc8FC!pvB0*YQF zplCkWIO0Yz^U zQ1lMLSM*58{nG#m9kBmt{-aWKUC{%!P|*6airx=-)t-=|W1KHVAF!q9L$(xs#FnDt zY$^JfEk&QOrRY<(6rEs8(PwNFeNI5p7X%c2NkGw81QdNuK+!h@6rCiX=vxAcz9XRM zdjg715m5940YyI&P;{DrqMryT`k8>DUkE7rm4Kq(2q^lUfTBMLDEgD&D>@Q#I~yRO zukF3-qf+#nC3Pkgw7#q&C*B*oM~VXRdL%DJW!O^WvZW}BEkzz%ilW(46l6qId#|5(p?tB%mmXfTAz~MG*puk_jj(OF&UM0*cBLP*j0{qKX6*RU)9M zG66+Z2q>ybKv6XUimDS(RD*z`ngkT35PU^vL+(`uNaz>)cZQskqNe6~QMKZO)|XXO zFW%d}SBmO$z7#cJOHo6%6g6T?QDe3goyV4STZ+=zD9Rw9D3gGqrUVo< zBcP}`0YxncC~8SSQ7Zz9S`$#zhJd2B1QeZ5Kv6pairN!U)PaDajsz5SBA}=<0YzO1 zDC$Z;Q8xmLx)Xdwb>iJu4Uo{s_O_^Qy#GkQWxN?Z;)B+gRn#Zm`);2UUBLNL)R!$q z{n%2}pDjfL*itl*Ek%RaQZ$$?MMKz9G?a~^VFVNnC!pv;0*XcuP;?OiMI#9)x|o2X zQ3Mo?CZOmN0*bN-C>ldRQ8ocZV+kl4M?g^y0Y$k46pbgKXaWI66A37qL_pDGg0HAo zyj%7eqsX)0b?hxg_Ai`?ni3zhzO16Wc(3_$QZ$3}rD!Hwit^b~RKS*^LbepmVoT9% zwiI2;mZCXqDVobh(L4f*E+e35J^@9S6Hs&o0YwW4C|XEB(INtht|XvnF#$zO2q;=g zK+!S+imoD{XgL8zR})aQf`FoH2q;=fK+&}X6s;nlXf?rCG%en}$N&j-vUjMbOVMCE z*2D*`FRSSKcyHbdQna4)rRWB>6y3;{q77^*x`{1CH?yVa7Pb^^WJ}SlY$>{pjiOBi z6m2G;XbS;Fw-Zpbm4Ko<2q@Y{K+&B96x~HY(RKog?k1q<9s-K)C7@^r0Y&!_P_&bP zqWcLbdVqkU2MH*8h=8Jp2`GAm;48W=-rZz?gwEPW`s<|V>Y@j1@j>g$DtbKL+qYke zp5S~bdXgnw+JYDn}DKs2q=1& zfTH&ZC^|y$743?5KQll=P3+CjZYio^o)>jAK4^VeMIXj{(FdgHBhHti<7_GVm@P%0 zu%+lzwiKOUOVMX+Df*l(MPIO`=u0+=z9OLLYXXYCA)x3a0Y%>uQ1l%EMc)%pbc%qY z9|$P=k$|Gp1Qh*5K+(?x6#YU#(XRv){YF61?*tV6K|s-;1QeYipy)3Gip~;zMaSaZ z^9+#CL!N>2ffRjfZ;Q^w2dyuw$W8G29+aY}gug%1_t;Vt&6c7dTZ&@XQWVRUqByn` zh1gOQ&z7PDHi{AnC`uxrC`>?6gn*)C0*cBKP*je9qVfb3RUn|KA^}B}2q>ydKv5L} zimDP&RE>b5>I4+kAfTuw0YxbU6xAZ2s5SvbbqKzqK!Q8d01553->xo`;6FwyYn~TX zHz8lpVQ4Rq`xdarAC!lBo0YwuDD4Ik-(PRROrVvmxm4KpY z1Ygkw3GQD8NNBaaE$S;p_S-~J(-VT$msOOX;MI6jiV8SiiVE3MG>a`ov)NK~DO-x> zu%&1&TZ-nfrRXxY6wPO&=yC#zt{|Xj0Rcq|2`E}bK+%;16fGv8XbAyDO9?1iMnKV3 z1QabNpy+A>idGO%bPWMTD+wsNmVlyF1Qe|%plA&NMQaHtx{ly0nvvjkH9$hi_PdTV zrKp9yEn1flw7#sO8xy>ox20$U=S$H|Y$>{#Ek(DmrD!8tif&~~(QRxg+QgQk&1@;! z!bZ{U1Qcy0py&<)inb9@bSD8tcM(vuoq(dd2`IXUfTDW|DB3|l(R~CI?IfV+egcXf zAfV_$0*W3Ypy*)&iXI`L=urZS9wVS=7r|GwKEb`(00|wi-*vn}ie}q;*Siyf)|XYZ zC&9btT`78s^QCAnTZ*1$OVK{I6g|V1qG#Ds^c-7?o@YzZ3v4NRk&UAL1QfkQK+($t z6dfR-=oJEr4iZrGDgi}@2q=1ufTF_$6unMB(HjI5y-7gPTLcunO+e8*1QfkXK+$^y z6dfU;=qLe2?-NjTjNmJJBEfyl013ThZ+@QSev$nN$Oj2Q>&q(oIKex0M2bG)d@1^r zEk!5TQuG;Hiauvc(HCqf`jRb0U$Ld=Yqk`9!$#3b0*byRpy)dSioPeH=oA4(KM+v# zBLPLH2`KuBfTEuXDEftfqF)Ip`i+31-w7!CgMgwx2`D;4K+#_W6rClY=o|q>PNE)| zqbNY|6@8T8mOp9~J!WryZica)e9+RRV=SxuxTZ&@YQWVFQq7Yk( z;@MJ^z?Py!wiG3?r6|lsQG|e^WCDuH5>Ql*fTHpQ6jdOgs3HMHl?W)ROh8c;0*a~< zP*jb8qUr<`)gYj#CILk$1QgXGpr|$hMRf=$s!KpoJpzjA6MRKciSES)Na%hG$4m4d z>6?4n<^fw`(E759&P(*>e<(#wIA4lV*;16omZEgF6lJibD3dKkP1#b^j4egY*;3Sk zjiQzW6tyCts5JpaZ3rl8OF+^21QfL+pr}0oMI8tz>PSFQCjyE(6HwHJfTFGh6m=t@ zs5=2gJqRf3NkCCA0*ZPQP}GNjq6-MVqDG1C76T+S)&2yeu@rr5N%c((T3=Stz(nua z<5Dz;^QCAoTZ)FTrD!NyiiWYJXgFJnE@Vs52(}bm#FnCwY!qEgK+z}yibfMqbO`}P zSp*b~A)qLmfTFPk6pbUGD2ITeTmp*56HqjPfTD>66ip(aXfgpsQwS)UNx`u$Fl>`)BOF+>o0*Y1>P_%}CqO}ART}MFCIs%HWC!lCO!B1QgvxK+$#ritZ+$=pF)!?j@jT2LVO*5m2;~fTH^eD0+Z^ zq6Y~mdWe9chY2Wpgn*()2`GAufTCRl6zwLU=y3vyo*) zY!n?Jpy(9>iVhM`^eO>GhX^Qojew%V1QfkaK+zin6un76(OU!*y-h&TI|LNHOF+?k z1QZ=1py((8Meh?(bc}$a4+tpwkbt6(2)?4H65YoQkWf8)S7@&kePe%p_IP5@`m%~n zBzi}`lA_NzUy43wOVJl>Df*HvMPIR{=xeqVeZ!WblWZyamMul!u~GCr0Y#?>DEfhb zq8|w;I!!>)PXrYGOhC~u1Qh*BK+$gm6#Y&>(H{g9{YgO483Ky_BB1Cj0Y&EsC~}hY zupLDK0*cBIP~;L&6h-hAeUj*&GeANwS~#Cd(Hu+4OA186TZ$6dQk2A&qA**EB5Wy2W=m07Hj2s-P*k3Pq6!2QRV1LO5&=b(2`H*UKv7i! zimDM%RGomL8Uz&8B%mmTfTCIi6xAl6s15-|bqOe{M?g`10*V?CP}GosqDBN?Q83Bv zZh(aDw0DJKlKe;dn=PrvNkQw&DoRW8#(yV8>6|Y`8Eh%aWJ^&~wiGpEOHp&S6t!SW zQA@TIwPH(AYc`775Kz>XfTHsWC~8MQQF{W4IuKCQk$|F31Qc~9pr{K0MO_If>PA3O zcLIuf5Kz>UfTCUm6!j*cs1E@}7Z6a?mw=*v1Qhir_==h&xz`vVp+ojDTB;PCD|*0| z6tupqq9IA%j#E-Jl=G!%7+Z>lv!&=lwiJzEOVLGaDH_R^qKny5G>R=nquD6Bgn*(f z0*b~EP?SwT(O3eC#t~4ILqJh30Y&2pD4IY((L@4@CJ|6HnSi1x1QbmrplBKaMbil= z$|Im?1_4Dg2`I`Zps0Z0D;kvKzHWeoCfe^^50;`@_O_@nDQJCJMRSt8AAgjhxtuRW z^Vm{!8C#0xv!&>AwiI2#mZAl0DO$*uqD5>ex{{5e#RL>BA)sg}0Y%FQD7uP(qU8h> zT}?pI3Id9*A)sg_0Y%pmP_&AGqSXWxts$UjEdfQ>5m2;_fTHUOC|XZI(G3I?-AF*u z27<3>c9L81v{AIk{v7R6DZ0xu^n&h?qS&DAsd@0(*mZHsUDcZu8qTAV0 zw3RJIcd(^s8(WI*WJ}RqY!q!Lpy+M_itZtx=w1Sfb`Vf>9|1)>2`IXsfT9NoD0+~9 zqK615dYFKsM+hi-lz^hg2q@Y`K+$djiXJDR=m`Rfo+O}X4*^9_5qw3rB)OvvkWh1b zTeMM%7TB+7dy|6JmsRv^l6S?gQuG|>OVRUeDSCk|MK7|YXg^zuUSdnp%WNq+z?Py{ z*iv+mjiOfxC^|$y(Q5=09VVdYbpndsAfV_?0*c-upy+J^iryih=v@Me-Xoys2mwV$ z2`GA>fTCjr6n#KI(T4;SeMCUfaRQ1yCZOmOg0E;_lDpLa2@S9h%bt;(Mh%xean`j@7PlGJzI)Sv8Ct-Hi~{Epy)IK zML!Wx^fLiPzYtLLD*;8n5m59y0Y!fhQ1mAOMP~>o`ip>~vjh~KBcR9$>tQ>J0t6J5 zA)v@5peTxfB9DNgXab6Y1Ygl-N$yt$NT{9tBKEly724aPm~hbgvWnuvUfdZeO5l7c zN@Pn>5?hMGY$=Mcr6`##MP=DiRE{l0<=IkHfsLYy1Qb;wpr|qdMO6qWs!BjnH3EvN z6HruxfTEfN6r~VQREvP3+5{BUA)u%(0Y&u)D5_6DQ3C>s8WK>{h=8KT1QeY|Kv5Hd zuP83;rW+ukw_^>QP}qN@|Fr$`mKqLPUsh3O*c*6Oikfo16g6W@QFFEwwO~t8OSTlX zVoOnLwiLBtOHo_46rImTQ9A;P+7nRJfqPkRSHv)>f6HwHH zfTErR6!jvYs5b#ceF!MJfPkXD1Qhinpr}6qMFR*Z8c0CVAcC(bJ?zdhKtkWzd)FCK zw9(!$4GssbFRN&H*t@~87m(pZUC8-TG=eQf7qO*iBwLCuW=qj1wiJzKOVK54Dav9? z(HJ(0vI!^}OF+>$0*Z17D9RrqNxNFO(URaIsrv_ z1Qg96plBumMfn626%bHVNI=mn0*Yo6d__aU?vn;cXn_6E*)SwmJv{N6#+%d2`IXn zfT9%y6kS6=(Mke}t|g#o6#+%72`E}aK+#$PimoG|XdMAX*Aq~*o`9ko2q?OdfT9fq z6x~EX(ai)D-9qpc%?-N&*C?89zjr-Piq_iOqK)C8^<@=p4turDUk6ciTeOAqrRa9H z6m4Zo(H(3l+QycmJK0in7h8(9v!&>6wiMmNM$x?l6zw3O=sp69b`nr@KLJG#5K#0W z0YwiHQ1mbXMUN0r^e6#Ej}cI`i-4lt1Qb0^K+zKf6g^2m(H;Vdo+6-VF9AhQ6Hv5| z;48W} zY$-a(mZDeLQgnzdMX#|@beMpm*9jdXIpjBLoy3 zC7|ei0*a0iQ1k%-MIRDS^br9?#|bFGrnh zc`4dz?_GZ$4q9JU(br*bXRH)`!}(Hlk}XBwvZd%dwiJEOmZDQ^Df)peML)8o=rmi3 zeqy8OX99|TA)x420*Zbkpy+o3ivA#==uZNQ&Ja-a7Xd|Q2`D;8K#>#C!*&z}2q-E; zK#@y8Q4|419sxzs1QZ1cD2gGVD3*YtID)U}%dq>V0TRkHGwLfT8e<>nhay4i%PLBW zct3@tD9rg%6k$tIGFytuvZbgTTZ+oFrKkd1iYl_Ds1jR>Dzi~kg@B@}1Qb;xpr|?l zMKuU0s!2dm3IRp62q>yeKv5k6is}+jRF8n7`UDg;AfTur0Y!}nC~8bV(RlF)`vl(%)cji!vfX>&q%?9`V{HN>K~Wm!g(zDQd-* zqSkCFYQvVIwrnXnpDji0*izJPbLRF9M2s6HwHLfT9ZsDC$c&q&-DB>*)OVLQqm!gZ=QZ$M!MWfkLbO~FEve;5IhAl zx`u$Fl>`)BOF+>o0*Y1>P_%}CqO}ART}MFCIs%HWC!lCO0Yx_uP;?^!MH>hxx`}|I zn+Yhog@B@s1Qgv$K+$akU(x)C`;7q-O0hRTmrKzyJ2pjv)|XYZHR8pWm!dm3Uy8P| zrRYw!6y3#^qU~%cx|=OU_pqhtUbYnNU`x?`Y!vMzpy+-AiXI@K=s^OC9wMOVVFHRC zA)x3{0*W3ZplBBXMY{E*XdeMZ&k#`bECEH& z5qw2kB5tMu5;|eO>v+2qeQ0lso{t2rFRSRKh&Q;R6ur#(QgnbVMX#`>=pb8)US&(s zA+{8~#+IVPY$GOMQ;&M^fm!S?+{S*E&)aF5m0o5fTE)W6unPC(J=yw zJ|LjzLjsCEBB1Cv0Yx7ZQ1l4_MV}H-bb^4Q&j={`oPeS)2q^lJ;46AD;$CWigihN> z`unBm5A(dJuOdO~%PRUd;%%rbMc;A06n)Q@qEl=s`hhJ)KeDChG+T;(VoTA_Y$^JM zEk(bwQS=)DMZXhJ^alY&e-co1hJd2K2q-#BK+!n@ikxIUY)4UmfTA)46uATxMG;Ws z5l|FOKv9r@q8I{-VhJdUBcLcmKv6saMF|97(KiwIDFY<*jJ+*7DMfMiD_UZ5(E759 zl9Rm;t4dK>&X=NcY$+W3Mad6HKS;&{T5Lq*?*+J)ZmF~mK?OctfE%QUfmi})SC09s0~|+ z+OnnSe6|#|V@pwcwiI<>OHoI*6m?=tQD-)ax)4y*m4Kpd1Qc~Apr{7{MLh{9>P0|N zZvu+?5Kwdh0Y!ZYDC$Q*QGWu81`tp*kbt5=1QZP>plApIMMDWF8b(0TZ~}@hB>0M2 zB)h#0kkEM+PD?2|XMeyyA~|S%Sw*9gy~*ZZBrf_n+Gx&~qD$CPl*N{!F>EQyW=qjn zwiJzHOHmG6igMXfG@gy32?P{PB%o*#0Y#GuD4Ie*(NqG8rV&syoq(b|0*Yo3P&AW( zqI?313J54FB%o*(0Y$S3D7ut@qB#T<%_X2{9sxy{5l}Rr;42!L?5;LILZdC5i=}9T z{SRd?PYzmNR?(tl?}6G@4i+W-lDZf4X%Df-@y+mnOVmy_g_iK-Ku zQa|8?cbFg9I^jbWT=vb=&BNj0364`Pd~=fHR02{c?_z z5}sPYaq5O2s^mBg!@pH=oF?H8)g31zyrib%G!GxBPrsPjq#h!f@jrjx#4bqnG2%4?ot&aTbQp^mUvi;VuIlXL)$}Ajer5 zJ~YH})`ZIqcbx0PBS$#ShVbT*jo^aD zyG?YQN5U&6JI?O#;i-;eepa66IQzn*W;)LE;oA!w=cVwMvmEDOIL-W%7>C1!^Bm`` z@DuYL=e@AAz;TX+dn|IC&(YL5ZSZdTmgYdnGNO|2t<0_Y_5VpWYtD<9Rwn8-Da+YK%~kRb1eiS zW44;BArQH9o4FnW5&N&%*9}DMKS$m$5V8NBbdx~D{)507fr$MVU7H6Y_MhZz9f;U} zQ?XqjV*gRRPJxL1SIxQwBKDu9>J^CCe^;n)AoATlbDabt_FwiG8i?3`nqfpBV*hUa zQGtm4%hAUKBKB{$&Iv^9Ur#(S5V3#1?9@QS{so~k0ulQ+JQfBb_OIxh6NuQqV{LvQ zV*iq?g@K6uTaK0lBF`Q-*H9p0|DKVRfr$N!BGv>V_P_MMJ`l10srH6I#QwLo8v_yh zA4_fyMC^a03Vt-|KcOYVa=W*@JG#QxgKOM!^}y@P{+i2cFw;XuUxG&3)4u6EBnxv^%0fK%}m*VdHPrpDN3nLm}P z*_UjQXq!{XNOb}&HJ&!72U=-dYfo*RxVY%W?l+&Wfi`+hNBd%JHAdS@J6|Kmj&>S@ z17@_>IA?AM0v$A7j5DL7#(4V{bn-{#95d`2UL`Ovkl{F0uQjLH|9SP?I42MZ)JrTI zaucg24yzamgey8unYvCW)WIajaVt1(V%yO9p*Er3Wz7do&oS?|*TS(Sx_;3iST+y} z`7akRH73DvV>m4oN(jY=TAOz^w&LGjD$cxAsS6Kjdj9K**F~CXFET+FS@hhJi%ir- z>ZOv*NnXj@5l%2~oqf%bq9@E%n5=h5ucT}s(7UX?_;R((2dRAXQg2Yl%IzvUPKC5U z$I85w4Jtcz`c+||W=>?)PMh-&6FSHAknfcY3_nwPJ#;>v(i zrqbFjmCTip=Ga#-J+bJr&0Awdl=?HqJRNWb+QR`W&lzeDKbrqVIfXA=vB^GVNk%!R z0|Pgimn!;G&HTUp;$S;}>`RsYQ+n5rH&?NfV@@d(_%kuV379|TWv#KawDkP!^zj8V z(hKs(rRQfAjLXfMk)KzXJFYM{Cw*N0+!=*=HjK;7nU$YgQ0jU1<;_dCNuQBFY1*X1 zNwagE^oe=Xa?`V?=FUk^o0>N+dun>Y#O(as^!(iExdqt;>A6j_3JPcCOv+0y%*&fP zZesSN=>_Q%#*NF$&YzZ^nUU2jt7%5l%&g1|8&ge8ot`&6H#IkV?4;DpjI?H{_StFX z*?)Uh`lRXOrq0UAO`n!MZsMfr|F6Fp1#=5Ze82TcfSF`3+E0$TVfTu3y3GQfSN6aA;{~GK2>~zJt(wx(3%H|G%#)Q4onh{41xeQLT_Hnr#t;6hAI@9mYfZ@GD%{|0b4! zUfDiHC!0(9_fPsCKJ!tDF6SlJFz5Uy@4k7@Q_OpAuS~80j{o-bTFw50_rSjM|MiFD zpEcuuKPLb3k^0|{$-nCPzw2XCrtZJHo%{dkXOCAa}2_wrs7JY~GsInUgb` z`_Jp%RWFliUU*X9yu2BiPQT70vby#k+SI@7Zk*Dh`1Q3SH7j|&O^aV|*HRa$H?S!u zv@Cw9HbrmKtmy@lCQQ%GNilb0i(XwtB*ywmGl3vqG!lH^6*Ai!ZtOl{Dvd zbSwE_m=A$o(7eh1htXV$|3s-bp%tf^4_?tT%?DQJwJ5$Y^Y-vco9gA8mAoBYi_ggH z%BwPOxX!QwNwO>)(Iz;&%^d871#so8tE*(-?Lx=zdXF=Wc_G&NEl7-bq7PPj&m-nT~yv zQi}fXUzlZmedwV!(3i_V^GKU<1kG(#6*@aiq;Qv5dAPt&3o z>Rj^1bu(9Y=fOQQi+V8(UU6pY;)}^Fv4<6?WR_qw?}1(|K#D1tTZ5ukl35}v)6nu; z2G12$6D-;KS% z)+HY*^MUkVM^j!|$rYbja?NL!y6Vlf0%%XM3PeYQ52lvgaa>;iHgh; z7R4k>G?*`|=Jgaz%*!t<{z_)_@z(fPe)08Q{598n-W0uvy>5nN_2}DqNH4u&^WpK| z%Tgvv3}lud$ShI7Rg`Jo>Y|g)S7+yc@*9Zy{$t6vrHb^M&l3MlEybopiFwy_4P=@- zDgFzZn*%*jd_`sYhU^8Fy3Nnj8OBb@)o7mT*?(9{*EVfZ>^B|LGE?lg9Wz=tZJyFF zKX+#97nEn&bGXdD(@j=6jay&6S>GgL%pE zGiJ9)Etrv-liAXg?EG;P+naA<&TgGLEp3|lHt2ad1vAbYKO-e|LQ3j@rYWiB`)=*W znKvMH{IuMHg6s*osZ(>OPbi$&KEovc9!;t>WtRPD6;8^Vo?2kOe`t;crsZT8W*2Y& zLt*X}_)nC4Vq}(lX7EX5@&9*U(ELw=QeSkrY0EU9DMgoEaxc-Ew;$`0JBuZE5i|Wy zr=siDd=b!_S8`4HpHszOQHwrxvaQ0M$1F$6k!< zn4ck*`r{V=c+!uqV}4Db)F0RR`%j(BZ!eU3uD!gZf9$`%wXS1+s8#BZ>m-+2_WbgW z`H@)BN5x(*$>#lQSn4Ih=IQhQvH#@<5OoWkx;f6^e|`ZqpAr9j2vGcWY>c_gxbo)5 zgwa@=V$EtPx-B8Eu`u?7- z<6Y(ourL3Jj^8%+_a8boGrx^upWjKxx#o(pdzp?;XZrh~j$U(rC+m2DxkByBkI-># zYk%LSeXQ11U$6*~~$NRg2jsqt8dz6mrC;R($9p9ho?=N+%mFMp?9Vg86 zccG5=75MuJ9Z%2lw=>&6wwdD}d+4}ep1)V>_`-aDzoBDjfxj#1IB1c-FVXSF#s0oS z#}AhJ`)eKREcbVYj+0jSd$x}Euk`mG9e-Zs?=q|Xww9(&p>iCiQ@F5Bj^Bj>8`I_gEcodDP$Ab^LgjzrWM5!4v*&uH&>l z{+_4f!+ZU`PsiW)`8)a<|Jd<4|JYZ@r7!sVIvrox@9+0?j2!TH4IM8$=$vF)fA7%oGxJ+o*29lFo_EsUt#zFFoxiWpan~t-Kd<9o<~OeXK{XJ2~E#@AAz5JazeqnwQ%3EBd+jV?Y$7gkX zO~+$8ex>6tI=bd}#q8S?wny{&Q?%>q7-R3Zm~P&bqGMSdE9zK7$J#nJ(J@2EXnTw^ zm#=LOMVDjl?i3vh?EN5f`R4A3Qzl}5r%K&PE0{a2Fng>y7UuiMi9BTU_yPUdc z|0VvlOtrsfq)Rk!o0B%q{8CJ=`4K~@*E&8wdzyKn&V&1R+y zGM_2_{aSmLxm)wMKjy<%^rx2jfBSN-KmX>qo5o4ck?C-Xo1C!>$~rDb!hVE$)c#{SQ~z6;F%cpJ=ot3N#NCbLUl-YIi=_Imn%$hr$KDa-!v!?Qax z%(6o)A)icSH7aI+Hx4AIEHzJ;wh3e!ukVcV|EU{d!MrUX>e~ z4#bc2Yw73Q_-Eu?-QcQ!e(%)MpPPO>lKuSm?OXP*w>Mpb+`jDHbh11x`^WMheY4-M zw~_rb{h8@U`ltU^(mp(Uy=hrY*Rgc%NxxtE|2_Sg{@ci2%zZPYDmNg#5I_8W*`?}# zUaw}Ws$BLi{GT6Q@84fzw?U_U*3Ujg(z93RuD!Z;Ymi12hF8edHAL$`a_G7KwO4-$O**#k4l~*n z2E8(T;gE$Ro?7-z-NGU1f3u&R7o?Y_Wj`mTmH+AZeEz3q`(-buUv2Z$vL`#gwye-4 z*YWqab8Y_q<*&c{|6IyHwdK=8AIr|=skPGa*q)| zPMrAY7WWRFH)-y&!l=2+=I7>Sztb!6JKeuUVM(i8VM*(%G0WQI#w=@F_jvYuWj~t~ zmaLlf)w15UF8!K*^^gV23T<=i{Qh=fNt^67+E!OiwrevtJDL4#TUgRA>#P5#pYzYj z&6aj+vqHPVlJ>mUPPc`v2)u{yCZ6ie}kc(fOZS zSXk2KUoUt4*UR1hdAVldnB{N9dGS_^{GYd?d-iAc_|KnNSkg1=8~msD`{%Y4mh{SA zW5fTvMqx?stZ($6-u0i8>8)s;y%ih(a|;Vg`uywVP5$-rrvJQLGqK(Bx8mG*D^~rV zx1w+MXZHKgpIKPaKkJ+Qr#JrRwiK2O$X;XMe_o@oWKh;O|4*+P(sWVov0Pn?zT+F` zdJUM+xvEX}U;ZV>_OEKSNrT*+eAUdyj$gd|(!xo4Yg=V+?cjgjlERW9|9W}ozh2(r zpO>iqIvdKZ1vAAEG*gjUoVgS*UQ`d^K#9^(aYb8Gb(SzHhq7d+;hZ_xdVm|9X8~d zNpqGJvY+!u&RO>iZRPB3oA}S|E-ab!ua_tP>*byPdAVldD$C!txHfFvcj+VhwixnM_7?r$ zTho7Ovo?h#Q?fsM`L!y$PVM}!mv^b&wR`p}BgZUj-==npbWKXvvf|KmwXB)gZ0bdo z|JTMWoV4tbin+{IZeW8MxwW(VN|pDGg{r@@chn6w&h9jK|Mz>e>|H>0RlS4K#|5iu zW@mS~tE-D&mC`>-v$B|Pk-f919^NwhI8*kez{NuLd*shguQg(&iOW;zhwOb{bxpBx zb~mfKrqn5WFIXrP(`O#43#A3wtK{2eubyAGS-l?dX z+S%>v7rU5tcKiCrE~K5^zRhB1pIGSMHM@NSVpnIoTXy>f#?J0G_V1S6zCp1w2K5Vt z_W60)zyI2^5~4Mh|DFBXzL|`|=B1mnS4cv(D5k&ExLnAvI2uBR#|$A`#tb1NVup~B zF+<3xm?30z%n&jrW(e6TW(e6jCLv>E6S7TgLdL}=WZT$;jE_yocCiVW5Sx(gV-vDN zY(jR7O~}O9giMM}$mH0B>=c`jDX|IJIW{4?#3p3d*n~`tO~`Js3E4e1A$!EG2pN)J zoc;T+y(+uf6oyuWOvx@&g*{72P7*S$xco1?rfbObI2uCsjTu7riy1=pj~PM^h#5i- zj2S`>iWx!fm= z#3tm}*n}Jxn~>vU6LLaqLQafL$n4mJoD`dolVcNdN^C+-jZMgDu?aanc16hE`KH+= zqjv4=y-s1DijWU88ig}TNlp@SPBHyu=;hatbK__TIWJ}iIX`9yxgcf;xiDr3xhQ4` zxj1GBxg=%?xin@7xhy6jm&YdLir9o)8Jm!+ViR(8Y(lPyO~|#e3ArvdA=k$yBqs@Zu$ca${Bj`=#nBM*aLf?$NX!uOXv`4uSj-SICuRtl8#9DF z9y5eI5i^858IzEwViWRoY(k!iO~|vc33)CyA``93xwi(?bABsL*SV-xa2Y(jpFO~_BN3HdoT zA-}{XWLa!NevM7YZ?OsaJvJeK#3tm=*o6EQn~=X_SA@KmKP3D2U%MdP_jrG~kn+3f z8j`CjB|7ODT?$pj^b{M*pBJcD6{q7FUFzBKj4mZRp3$Yoj%ReKZ^tvb)Y|ckE@eBO z(WQYM&*;+7j%RdfWP3)J#)4;bsS`Y-OB2B}x-=C$qf0ZvGrBYvJfq7Bf@gGTA$UfY z6$Q`e(o*n@E-MM1(Pd@9GrFuIct)32f@gGTEqF$kRRz!JvYOx-UD^nq(WR~68C}{5 zp3!A>!85wF7cwA?3We&b{9_rA^4;m~NxrJ0=%;kQWsRy*;*}JwT~$m^(Xw38I?jip zj&>+o*A7MN*`cVD9g5bsLs4ft6m_vfQCB+@b+akzE>P4%ps1%n(FOuVy#$Ij6e#K~ zP_&Ui(Z&KreFTa&5h&VJps24vQ9psA{sKjt2^0+wC>khGG)SOmbAh740!2fFilQ~E z^2O|n>dKdKuOC>k$Nw4FfF1c9RM1&VeMDB4k=Xre&TB!QyI0!2Fs6ipE* z+F77z7lEQ(1&XE$6zwKZw7Wpj9s)&s3KZ=nP_(yDQ8cV7zeNV5e0Mer!$VPeT9m>* zRi)%BDcY~9n4ThPxuX4@4@C#qq3A$66dh!TqJ!;Fbch{_4z)wkVRk4w+zv%Y*c2Tp zP;`_)(F}p2nF2*e3lz-~C^|-<=vaZG;{=M17brSGpy)(_qS*pPCkYgtEKqccK+&lJ zMW+cAoi0#xhCtDo0!3#D6-Cpl@@Hf~%B`|T+J${X(FMyNXH}JwucYYws$zPIvE_;` za6S}WXosSU>`-*E9f~foL(!#nD7wrJMVH&5=n6X&U1?Kvl|a$e0!7yd6kRJ&be%xa z^#VmV2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c z{X#|2xmEc$G9cw%>EYLTp=kT0=z*$I@|6@lQdLY(QMX*tqt1t-$Lvrv#|}kv?NIc% z9g3c?L(!9VD0<2cMNiwI=oy=$X9bF$6DWFKpy&mGq89~fucVJivAKP`dgqV`^z2|W&h?2RTNbT6jciqMT@HPJ7qx1&t{)DEqoY?UP;%Y ze03@LN{UL=#q<=J%N5l)AByVRp{UjlMP)k_HLycbLpu~TvO`g0I~3K~p{R*XQB#4U zW&%ac1&US>C~6^4w4y*!OM#-51d3J`C|X6JsFgrbYk{Iw1&US^C~6~6)K;LVoj}p* z0!8fwiq;S)>L5_GrchB-tj^z%0VyAtefqpmue$O`|HE`GTC2L0d?iKeRu`Xd8;aI* zJ`{DbL(%$nDC%s7qAqqQ>S~9gZgwc@Zik{Cb|~s;Q?!9VQ7?g_4F!sN3lwc6P_(f? zQ6GV#O$3TI6)5T}P}EPLsJ}qbW&%Y61d0X<6b%w6+FYP$ut3oefuf-TMOz3I4HGJg z)~U{ap8+X%%D#}Y&@mL{(H>Oi$6f{8}{H`A{^*4nDB512Xa|9!9R-Re3KUHeD4Hx#w39&56oI0h1&VeN zDB4w^XsSTbZURNS3l!}kP_(B&(Ov>YdkYlpBTzI=plG^KQ8c1D-y;K3-Z@>1Muws> z={?%M)urSsDLSyan4aQ!xuS!d4@C#tq394h6dh`ZqQmS^bhsUgj<7?~k#;CL$__;{ zY>H+I6df&4G)ti97=fZ=1&WRnC^}xC=mdeH69tN93lyCsP;|0D(J2B&rwSCECQx*` zK+zcjMP~{Woh49owm{K20!8Nv6-E13=MT$(l>4U-5gibU9!}Sy^Que9S5kCQbum3f z_;N)TJ0FTJu|v_Nb||{c4n>#Sq38-b6kTbDqO0ssbhRCduCXb)R-ouQfuidLif#}n zx>2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj2biXIRs zdQhO~A)%t^g6jO-3`qI(stnGBp=e0D7Cl^DO1_e!In~AV6!Xg!&2>H$J#L4hC+tx4 zq#cT$vP03+b|`wr4n@z}q3Ag~6g_WK^nyUqivmS22^7r}D0*3-Xud$v0)e7e1d0|4 z6ul}?^qN4?>jFh@2o$|3Q1q5S(c1z=?+6sVD^T>FK+*dGMIQ(hEfOk<9<9!oI%bMy zr;j>57K+BEd)FUUmy)lf=+o+A`W6Mt6@BJ>DEizEMPJyV=u0~kePxHDukBFujU9@< zwL{T&b}0JZrf9K1(Gr28r2<7i2o(J&Q1p{P(a!=!zX%j96Dayspy)S&qTdCI{tzho zQ=sTCfug?!in1?5t~_j~s7j!yTA(N|P*e~oDhd@vA6MsxXF$pm)3xZ6P_#IWdihfF zl@!(Hi|JcjELT)^J`^>uLs3IJ6g9F#QDZw4)!Ct_i5-fX+M%eK9g3RU6s;go)Iy+W zMS-H00!1qc6s;^!w2DAcD}kcc0!6C|6s;yu)JCAFtw2#bfuhv~irNbltszj$ci%7B!orjI(-&sQGlzmcv*9rLB+D=At(UrgU3Wx1lx&WEBd zb|~sS>3f4eU_V%ML{w+7$H`DB4J%Xk&q*J_1FX2o!B9P}EnT zsGmSle}SUS1d0X-6b%$88YED(xj@lifubP-MMDLOwh$;9CQvk7plC~hq7gzx(R%s( zTN#k@zUi(|r%?1+x)zPhmy)lfXsdiNeT$vtinew>6pgh*(KdD{8fS;1ZS7Dr-VR0E z*`a8H9g4QML(vX4MLP-T6 z0r^t$l@uM4FQ#wNv|Q1l&WEDI>`-*L9g2>yL(!3TC_2gxMKkPBG}8`6N86!jmQB$y z0!7CP6dfl}bi6>(2?9kY3KY#2C^|`?=wyMSQv`}m6(~AQpy+ggqB8`F&J-v*OQ7g% zfueH+ip~`%I!~bJe1W11go>hr^7)-JAmx7PT6AzI8kXLpU6?N=UrEuW`C|GOU&|F; z=6oo++zv%o*rDi3I}}}IhoYPqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XU zM}>-_i}U%LG9cv+Nzo;ts8bq`YMbFxy z=s7zSJ#UAi7wk~Xiaro1S|m{Pp+M0`0!1GS6-9IN`Rp%^=gQ}%k2*dc zih8GO(I@#*@|6^Qk$pX6pHTFr^P%V~I~09whoW!nQ1q=GioUZ$(f4*JT5N}+C3YxU zYE$%sK+%r^ML!7?{VY)Qi$KvbfudgpihdI)`dy&t4}qdT1&aO>DEeEVC|8Jw?G#lB z6jcipFC4r(Ep`z%se13xrNO|4#;p)#r(P8P{b^Ssq`AUi!7K-Ux zR4%_3HF7=_HMT=hogIpr*rBMY9g3RSp{ThXidL{gQ42d1t!Pu!QlMxhfufZKidGRQ zY9&zATA*lEfuhv}irNSiwG}98Cs4GyKv8>vqBR7HItUc4DNwYQK+)O)Me7I@brdLC zSDVv{sGIYlsJk7Cdf1_; zryYtmutQNVI}~kbhoatgDB8#lMH|}`^${rAM4)I>fug{}E3lt3zC>knIw1q&?FoB}s0!3R26paul8YxgTN}y=8P*K#mkbfcrQl6E~ zLYGkVZn_qYDU_10q-dK$F@1~N<%-5RABwiML(zCU6m4gRq6u~=+TIRDJJ_LUM>`Zv zv_sJ(o1)1AMLP);O%W*CS)gbafudanilzz_?IuvPyFk$%0!4cY6zwHYw6{RfJ_1G4 z1d65$6zwZew4XrH{sKh@2oxPCP;`(`QM7d-Uw=TR=$G_S$FZU4?sP3WxKK*IlA^;4 z#q=$fmn%BL`A~GE9g2>!L(vR76wS0l(b0A&nq`NgW9(3LtR0Guvne`Wpy&jFq7wy* zW(yRZBv5p+K+!1zMW+fBohDFpxjyFM%weU-jUFGV%3?1* zC0|L=*M;IA!$Q$F&WECJ?NIcc9g4oUL(yV86fLns(Na4U{a}ZpAMH@|lTFdj0!6N=r4hyzXghN#dz3GQI$YZwLno`pr{~FR1_$xCs0%p zD5?=CsxMGfD^OGxDvG`=1&US`C|XURsEt5TTY;i> z0!6C}6tx#9T0@|ygFw-m0!3>H6s;{#w2nYgM}eYs1&Y=aDC#6ow7x)5XQ85~Q8B-3 z2Bh37ecg5AV&#$k$LWiWx)e*vS5nlYSUh1=DC+5aDB8ddMZN4$w4oh}dfTCBBRdpr zY=@#gb|~7!4n>>V6!jG->L*atU!Z6+fuaEdMFRzj1_=~xE>JXBplFCd(NKY+Ed+{& z2^0+%DB4n>XoNt~NP(hJ0!5<*ipB^OZ6#2&wNO#it(dpgP_&aBil*2U?JQ8Vi$Kw? z0!32=igpty+FhV%4}qdR1&a0(DB4?~Xdi*1X#z#l1&a0+DB4e;Xn%pC0|bf=6ev1K zpy*(MqC*6V4izej#uf8FWI)RIrn^GhhN2tOoutExrQ|CqI;vP~J~kB1a6S~xv_sL+ zb|{)8P_C)yOv7AQJNpy*_QqEiHlP8BFRO`zy>fub`6 zip~@$I!mDFY=NS41d7fTC^}D|=zM{q3j~TT6ezk#py* z15zHB9+n*$irz@qqRWe=y`PE)-qkd?>os4n^15q3C)$6y0Elq8sf{bdw#5 zZni_wEp{ln)u!k+fuh?5itZ37x>KO&E`g%E1&ZzwD7sgm=stm>`vr;~5GZ<3py(li zqK5^F9uX*dRG{cFfucDAMRNs;9v3KjLZIkLp`z%@V*aQMNO^j?D|A&TdM5j|!c)ak z@|6@lS1evWJ`_Fgd?=K@7v2o!xOR1`f^%s-U@DQDk#Cs%kj6up&5eN`+aUrEt-#o}iZLeclmhoZ%H zC|Y8NqNR2y`oRuGKiZ+_Cp#4VY=@#>>`=7Krs!9JqTd9HeitbEL!jtSfug?zivAWT z%GHa9?G#lB6jcipFC4r(Efui~XMYRG&Wr3mw0!0l4iW&(OMc)+j zGQ6IZ$r_d^sv8iy;Aa(6g8_?TzAJ%)ZF<{w1ORqTG*jzMLQI=v_sKKb|_le z4n?cjp{SJ|idx$gttwEonm|z-fugnoMePKNRu?F0FHp3GKv4&QqBRAI))FXMTcBti zfufEAMe7O_ttU{_NuX$bfuha=MO_4nx(XC^6Do?D)XR^`fRrCi_pY1Pt31+gpC0yi zuUAUGlA>Pqiu+CqMH@OFihA3jXd^omZET04K6WVD#12K9+M%eg9g6zdp{T!2(Pjcg z0|bf&3KR_zDB4`0Xs|%h5P_nh0!3R06b%z78ZJ<@r9jaLfufNDMWY0YMhg^;5h&V9 zplEA>qOk%++Xxhm6Do>&*2|xl0VyAn-id7xitbOJ4%xO|Dfvo@wy#&bf2UBigY%(i zM>`Zvv_sJ(I}}Z}L(xulD4Jr2qMhwfw2K{zcC{&*Dp0hWK+*03MSBPo?I}>Smq5|p z0!8}>6ipK-nl4bZuRzg$0!8}^6dfQ?bf7@dK>|ew3ltq9P;{t3(P08bhYJ)PAygD? zS1Z*Uq76mh++L7&{alYloua>`-*P9g0q{ zL(z$LD4K1DqLb`Ubh1s+DFQ{O3KX3tP;|OL(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMLq zzCh6h0!0@J6kQ}xbg@9uB?3j43KU%?P;|LK(G>zkR|*wHGwS76-z8JDAYF@QhN7m+ zAF$OcC0|L=b@hq^riP;HoexDf*rDh~I~3hyhoYP9P;`qOif*+-(QS4py4?;%ci0r& zDNuBmK+)X-MfV64-78RZpFq+50!0r96g?>n1&TfsDEeHW=nH|OF9nLe5-9pwpy(T+ zqUia0`P(ue<+sv%v=>5ApY*W*+j^zsD=Au1uQ-3tP_)$fQ1pWxihi_1(NA_L`q>Ue zzu2K@nH`FLwL{Twb}0JYrsxlWqCW+S{t_tqTc9XciihnKRS6VT3l!xAiV6ZnMS-Gv z0!1Z(q8fps`T|9@0!3wkq6Pv*4F!rC2^2LJD5?`EY9dq=eP1vCQwF5`Qo8&s4n^0b zd)G}%rQ|CqYEde-*e4XN=zJ(@X@{bf>`=6_9g0@5Ls2U`6t%WP(W-VRTFnkcZET9# z3KX>yC|X^hsJ%eZ8UjTf1d7%aC|XOPXl;R_bp(n!3KXp?P_&*vQ73_-^#zJL3lwz` zDC#Ou)J>qMyFgJ7fuf#5MN#uoexnRXc|dxkze1_`=6c9f~%!Ls4Hl6!o)1QGYuWZDxm}0d^=FXj3#uplEY}qQL@1Lj;P33KVT2 zP&7=SXt+SpmI6g11d2uq6pa!n8ZA&XMxbabfugMiipB~QZ6i=LPM~O8fuivOMcWA# zMH`m#GczFN^eub~y+hGO=~^_QR7$>*qKT#AmHUOFNzR9&$#y8($qq$R>`=6`9g23b zL(#5wD4J@AqTTFJw7X5w9s)&s3KZ=nP_(x|(LMr2(*%m93l!}uP_&;w(f$HO2M81$ zC{T2eK+(YhMTZC!9V$?Cm_X6t0!2p%6dfs0bd*5R456ZEhf@BT3`n_sdRVq&DC(5n zz0E9@lCPxb*i!L}147Yp&WEDo?ND@r9g0r0L(yzI6rE&;qLb}Vbc!8{PPIePX*NZt z3lyCpP;{n1(OCjTXA2aaBT#g%K+$;uMdu3?T_8|&p+M0^0!0@K6kQ@vbg4kmWdcQ) z3lv=;P;{k0(NzLPR|^zfBUBX4D&-pov4n?=vq3BjS6y0WrqTB6IbcY>^?zBVEU3MtC+otFqfuef_itZCAx?iB^0fC|i z1&SULD0*0+=n;XUM+J%=6DXP^P&8Md=y8FfCj^R~6exO1py+9VqGtq(o)sv1PN3*{ zp`z&eQhrPZr2JO;yRkQfqFvIp=!H@#`AUjjE*1AbG!)HuJ`^pmL(waCC|YQTqF3!u z^qL)tUbjQh8+Isq(+)*%*%ZAkQ1p&K(Ypdg?+FyWFHrP>K+z(Bq7Ma%J`yPUSfJ<= zfuc_Ziarx4`dpys3xT391&Y2BDEeBU=o^8eZv~3J6Day#s3>}=l)oSYQl6OZ3e5{e zkECnS;!-L3N{W6g6(2l26#e9UDEiqBMZeggXqg>~ezil6*rDi8I~4t8 zQ}nk$QLZK)wo_CkP*g2Ylou!}2ox0sis}gzl>~}v1d8el6x9k8l?93#2oyCGC~727 z)L5XXPN1lXKv7eHqGkd`&4r4hrKS7_8Ibak=?l|-2t}(TQY+MylCPv_rJ7>ys8F=B z^Py-JI~29DLs4rx6s>B9qSfqB)W!})ZS7Fh&JIPZ+Z44IC|X0HsDnV!ngT^@2^6g@ zP_&LfQAdHIbp?vn6DaB=P_({4QD=doE&@ee1&X=}6m=IU>LF0nQ=n)AfuddlMH>ng zMJv|i*T{gBuS{Pg+p;D;r=Q-V^{y!;UrEs>HN``=719f}6q6b%t58Y)nM_4 zDB4G$XqrILbb+FM1&a0)DB543=m3GD0|kl>5-2)Ypy&{RqC*9W4ihLkT%hO(fubV? zijEQ}njug$Q=sT*fudPLMbV_1{2dvPa&5XRG&vNloJbv0Q%b&)q7!P0uN)hSPINvL z&9+0)Np>hY*$zdg*rDiDI~1K}hoaN%P;`bJiq5ntI!mDFY=NS41d7fTC^}D|=zM{q z3j~TT6ezk#py*XtyLME<3rIJiPQ}>rQ|Cqx}~Pr@`O-ytMj4gHaisEZik{f>`-*49g6O< zL($!KD7wcEMfcjF=sugG`vr;~5GZ<3py(liqK5^F9uX*dRG{cFfucDAMRNs;9v3Kj zLZIkLfug4bik=oIdPbn=S%ISG1d5&)D0)Gl=tY5|mxPLs(zLKI}YKm8%9Ez4X zABujpL(y+`DEi$FMSs|#=ubNo{bh%uzwJD5@_|R4Y(a7AR^UP}ESMsF6TXV}YVNfube?MNI{Ynh6v&7bsdmps0mF(TYMv z(N8t`=Q1GWY3cIwb0{jM(XxIi`AUjf)h~W^YA9;$d?;Gg4n?ckp{R`=irU(tsGS{( zR<}b@dpi`ZVTYm)HbrX+6s;vtw6;LeIs!!<1&Y=cC|XaTsFOg^`T|9r1&X=|6m=CS z>LyUsU7)CkKv7SDq74L!dI=P5C{WZ}plBn3qK$=$qLu6C8=sabI=Ws4XO;SuNBZ}s z(WibX`AUlV)h~8FBNX*_J``m&oqCs{j+T0FBgY8f>#12J6?NGFZP0=uc zqTvEXTM8775GWccP&7)QXtY4l7=fa#1d6s6C>kqJw2eT~IDw*V1&YQC6m2I^G(n(f zdx4@I1d4VPD4HlxG)br^+O&Rt>kLSFT)O=94MnRgf52A1lzb&cyVNfpcvdLd)%j2~ z)ec3w*`a86I~46)ByT!EtV1d7fVD7rwP=t6;_iv)@;7AU$zpy*P8qRRw|E*B`e zLZIkMfugGfimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n}mv@6YJ+c%z%^!X0tFm6m6a! z_TOB;lzb&cx7ROLpC5|ua6S~>X@{b_>`-*K9g6O;L(#o1 zy7Qsv4LcOQX@{b>>`?T!9g5zuL(#i-D03)KH+Pkw8&n zfucHrq9y`GO$CaY2^2LKC|W_FsD(h$iULI~1&US@C|X&lC|XuOe^&;i+$-HL`ZW}- zUChQRwWZ`MDO#m!DN@E06T&rqQ>ylzb&c18R#aUlEE1 zIvNil*D4XkR-N?PpW8zd+Fe0!0T36dfc`bg)3tAp%8*3KShCP;|IJ(GdbgM+y`j zB~Ua&plGH*(a{1$vjmEc5hyxVpy)V(qT>aMP7o+MQK%@|wKjij2Bds{y8KKHMR%q< zNwaH9$yZWzYHjh_YeLa!&WEDY?ND@v9g5DhL(y4wC_38?Md#R|=v+G#oo9!l^KFVQ z5GcA(py(ojqKgHJE)giYRG{cGfuhR=imnhSx>BI%DuJS_1&Xc_D7sdl=sJO->jjE# z5GcA)py(!nqMHSZZV@QDRj4RBxiyaQGuez1d8Se6wMVVdR(CB z34x*~1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq89~p#R5f31d5gl6#XDj^rJx0PXa|h3l#k#P_#^_D0;m%zfA_D{BwfyMkpGe z-o5==TS~r?qCabk2j3iu{&GGP{cVS$Tsa=OhoUMw6jj@yC~t?Nf*p#Ab||W6hoX{A zQH?-ReSxA{fugcNQ3HXZh5|*61d1996x9h7H4!LkDp1r+ps2Y((Fy`ZEd+{I6ewyb zP_&Xj(aHivs|Xae5-4gdR22PQo4+IjQeK#@MSp~%bF*J7tXeK5UrABBa`DkyL(%Ha zhobg&C|bh~MIG!=w5A=3*0Mv<+IA>f#|}ju?NGF?P0@M+MV$nS))y%1EKt-%ps1@r zQ8$62?gB+U1d4hJ6m1|-)JvdfLxG~+0!14M6m2X})JLFb6M>>l1&aC#6!jA*>Mv9j zwJGO6&VZDMru#*0%aup^7p7~`X5~`yl@x7WE*9r6S z+o5PnI~0wuL(xb(6pgYe8ZA&XMxbabfugMiipB~QZ6i=LPM~O8fuivOMcWA!O%N#B zUZ7|PfubD+iY5vaO%f=YEKszQK+zO|qMZebb`dDrRj4Q$SkAAV0V)5QKI%9q6rGg) zT48Frlzb&cdzOns?+QhGIUkDlwnNcAb|{)=hob3rDB9N!Mf=&IXn#8t9bku|18s^9 z5-2)Ypy&{RqC*9W4ihLkT%hO(fubV?ijEQ}njug$Q=sT*fudOgMaKvf9V<|DoIug> z0!1eX6rCtgG+UtPB!Qxng^Hrx%lUmWAmu&Mr}6g)MZ2UsNvD)c$yZWzM!9(UJ)!7K z=R?t1b|^aA4n^nKq3B#Y6rE>>qVw%gbb%d;F0@0@MK(nj3lv=R_ zE`PvQE+t<{(L3d0s|Q2TyUvHA_v}#gz8#7_utU)zI~09rhoX<{Q1r1KiaxPJ(Wf>= zp9vIwE>QG^K+%^1MPCUNeJxP*jX=@20!7~m6n!sHv{;~Mi9pd(fubJ-ihdL*`bnVZ zXMv($1d5gk6#Xht^qWA@??Oefn4RTGI|iYuTY_Z95dLV~3)S zb|_lc4n^zPp{SD`iq^L&>MT&yMWCpwKv6e=qV57kJp_t+3KVT1P}EDHXhVUb-U3A% z2^4KCP}E1DXcK{=O$Cbj3KaDdDC#dzw3$HB0D+=`LPgQ)4e~E#K*}GcYf<|Kl}GwL z8)RcpgHrO96b)@q{BBMt+QRuzG|Ub~!|hPCr5%b!*r8~o9g0TTp=h)nipJQXXe*nd ztp$q43KVT4P&7`UXj_4z@d8EL2^38bDB512Xa|9!9R-Re3KUHeD4Hx#w39&56oI0h z1&VeNDB4w^XsSTbZURNS3l&9!8|0hK%@h^WM;(WRqV$9_g*_USlCPv_p9aP5PlTdr z&WEDub|~7{4n_Ofp=f_Q6dhoPq66(vbdVj24z@$lAvQ&a3KShCP;|IJ(GdbgM+y`j zB~Ua&plGH*(a{1$vjmEc5hyxVpy)V(qT>aMP7o+MQJ`qHK+#D8MJEdsogz?lszA|c zLPgPD4f5M&K+1j79qPS9(daZzZ%|6UlA^O46c2qW6rJOIC_2{;Md#U}=zKdAU0{cz z3++&JksXRIwnNb+b||{krsy((qRRz}t`I1?QlRK6fugGgimnkTx>lg*I)S3=1&VGE zD7sOg=q7=pn+1w)5h%J`*k<4n>dKq38*l zq9+B4o)Rc}TA=6|fud&xik=fFdS0OD1%aX$1&Ur0D4Hiw^s+$Fe1W0`0!6O~6fG1e zdR3t4HG!hn1&ZDfD0)+%=q;h5=)MN|PctCpb<^eN{!p}P_G^W=8p#R5f31d5gl6#XDj^rJx0PXa|h3l#k#P_#^-=vRTF-vo+&7byBepy*G5 zqQ8WSqIVnQJ7z%2_0mTj-wQ<>rbqgJHz*}vNm0IGaoCHYsL=3#AL$qEP*l$jMI}2F z)!3n^z8#8c?NC&C~6^4w4y*! zOM#-51d3J`C|X6JsFgrbYk{Iw1&US^C~6~6)K;LVoj}p*LPb$k!~FCNNcpw|r@CR~ zFc0>S%|eb?s2Jo*jxh*`a8CI}~-cLs1ty z6m_*J>LyUsU7)CkKv7SDq74L!dI=P5C{WZ}plBn3qKyTL`Un(lB2cucKv7?TqJ9EJ z{RN6P6DS%WP&81WXplhB<^n~7g^HpM4fFS9K+0<;IBSNYQhN6`q+u!fN{WUzEWSBE z6m98zC>mjhqLFqe8fAx~(RL^rV~3)x>`=6|9g4=F9q3BRM6dh)VqQh;9ju0q1QlRK4fub1#MKcA8jut4IB~WyXK+&-RMaKyg z9WPLHf`-*E9f~foL(!#nD7wrJMVH&5 z=n9*nD+P+K5-7S_py(QbqH6_;t`jJ_UZCg(fub7)if$4px>=y;7J;H$1&VGHD7sys z=njFRI|YjF5-7S`py(cfqI(63?h`7C&S{uGF#}S5K7G{j+)(s*dZd4U!&35<6g}Lq zc;g$P=n>~b(W7=Kddv<*bL>zw*A7LG+o9+QI}|->hoYzKQ1rA-(K7-?&k7VhCs6df zK+y{VMK1~zy(CaHPoU^!fui{WMGFLqUJ)o-C{XmOK+$UgMXw7Ky&+Kara;kK0!42N z6ul!*^sZ1*^kBpM%NdaJv+45lko!gHGa&CZEG1t_(T5F-i{A=GA2}b2KDI;ACw3_M z)DA_T*`erjI~09khoUd-Q1q1@ioUif`bMDWTY;kQ1d6^FC|WE~v_zn2sX);W0!2Rx z6#XPn^s_+GF9Jo&1d4tYDEdvH=y!plKLm>Y6e#*jpy+RbqFkeRU`|n$P*L`>Iu4n>XZ zP}JBCMRhhsO$3UX3KTUHC~7WHw1PlU3xT2)1&Ue<6s;ssw6Z|aDgs5V1d3V<6s;;y zw30!8fvidGjWYA;Zq&K|HeDkWb@ zQO8Eb!`}}@>pCBb*0V!VCp#3aZ-=7Jb|~s%hoY`_DC%a1qV9Gm>S0sVQ=n)Afuddl zMH>nf^%f}FNT6tAfucSFMVkl|Z7NXISD>h$Kv92zqRj+~1_%@l6et=bP_(%~(O`k1 zAp%811&X#1DvH)_l)oYaQl67O>bOoQ`Y@3i)~J+xB}F3}6(3&|ibgpfibmU^Xp9|- zwz5Of)^;cwYlot3>`*k$4n^DAp=i8K(RKnw69kI37bx06plC;dqKN`UlLU$;3l!}n zP&7rLXlH?g9b|{1gY8gsh#iU!wL{Tib|^aB4n;@U zq3B3E6dh$#G((_hra;lr0!6a~ijEN|I#!_QIDw+$1&U4(C^}J~XtqGnNdiSD3lyCq zP;{z5(P;ujrwbIFAy9OtK+#zOMP~~Xog-8f?bj&3UIwH*J6((R4@G~ZhyCX^Dt*2v zd!`-*69f~fqL(%1SD7wN9MOWIP=qfuDU2RizjX=@0 z0!7ye6kRV+bb~LubK+&B7MRy4l-7Qdbk3iAA z0!8-;6x}aS^ngIogF*(RQK4{tqx^mukn&#XqmCDZqWjXd=%GfX+Z* z3lz;4C|V#;^ol^yLV==J1&Ur1D0*F>=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp% zp`z%KM)?OaAmugEU7<%q(bwtAXBRapC0|L=Cyk14e;JBCbv_h*W{0BB?NIcE9g4oR zL(x}uDEitCMc>$==vzA!eP>hjy+F}ofubb>MN0*Weh?`7QK0B2fuf%UihdC&S|(8R zt3c6j0!6`AUlFH!imMCKS~=ABxI$C~9DbqK0-TYGj9^#&#&GvqMo6I}|mwLs2uE zqUHicD+m;|5GYzvps1xl(MkeED+?5@B2d&yps2M#(W(MPs|ggf5h!XaP}EMKXmx?2 z_5wv~2o!Y?C|XmXXf1)FwS|hJQsex<3`qIfbXTaRapjTz<%!ffjZ4W_Qq-w&ahLBx z(fZDZqRw_G>SBkYu68KuW{0Bgb|~s$hoYW#DB8ddMZIi_HWVo8El{+PK+(nmMSTQ{ zHW4V=RG_G@Kv6$|qW%I!n+X&R5GWcbP&7!OXmf$0!2(4?1d4_V6m20;G)$mqxIodC zLPgQKjq@jEK+5ydW3=@`(cjA-ur)3vUrEuJ#>JZ#hoY^V4@Fzsp=hifing&s(KtI4 zZEJ_3@pdTM&JINr>`=75P02ixj}Ap` z)3s>-#--#dDLS}uap}@fbcpkz=ukTp9cG83!|hOXgdK{Gv_sKRb|{)*hoYHwC_37v zXqG_HF#<)$3KShDP;|UN(Fp=YCkhnJ7AQJNpy*_QqEiHlP8BFRO`zy>fub`6ip~@$ zI!mDFY=NS41d7fTC^}D|=zO7~=)lJL6@SPS%}k$1J17+WUd+Y?jZ4W_Qglhiry0_dS9UE1A(GN0!1GR6n!LA6wPUzzbXS#9+4iF z%?(AnrVl}W+_;o{B}Jb%E&=fBK=lrKo{#6Al}`=@JBOI+pMGc(~MUCuG)YuM1b#^FfVuzxpb|`9Qhoa_oC|bb|MJ;TKRum{|DNwYMK+(zq zMXLxDwGt?5El{+oK+$RfMQsF%+6ol46DV3;ps2k-(Ha6p9R!Nj6ewCtplEG@qICp{ zItmo6D^wKK*5%jFfRtaXpTQ~DRUYX-mfpRsS652DlATZXk z9(E||X@{Z>>`>Ip4n-TL*atU!Z6+fuaEd zMFRzj1_=~xE>JXBplFCd(NKY+Ed+{&2^0+%DB4n>XoNt~NP(hJLPgQ~b@>A_Amwk< zz3a}QXmPqQjjk&tUrEu}y5hOH^c!@}6}E9c6pgb((YAId8gGZ9?d(uA!45^++o5O& zI~46`hoXr#MUw=ICJPkpBv3R(plD}-qFn@vb`>a^Dp0hWK+*03MSBPo?I}>Smq5|p z0!8}>6ipK-nl4bZuRzg$0!8}^6dfQ?bf8dCv{haHp$tg*qV%b=twT}6^hp1px>E9$ z6dhJqe78Cj9qxQ6I>HV`N7|w2C_5C*utU*II}{ylhoV__C_2UtMaS9{9Vbw9yg<GE?~D7q;Wt*b;0!0f1ie3>YS}0KTszA|e0!6P26ulu(^rk@3TLMLI3lzO0 zQ1q@q(R%_#?+X-tAW*bOpy)$^qK^cMJ{BnYM4;$Xp`z%Cy8I~_kn;NJTJ&Tnx+>kf z{;aN)d?iI+)fI28ABw(qJ`{aphoW!oQ1qQ0ioUl)(PBFkEwMwT7bvO~DvG|S%P-7;l=sPI;mc4oF+I{RHz_4wNm1h_#UIO|sLuIN z)Wi-&P3=(B%nn7(?NGFW9g14mp=d=r6t%QN(MmQ&D+?5@B2d&yps2M#(W(MPs|ggf z5h!XaP}EMKXmx?2_5wv~2o!Y?C|XmXXf1)FwFQdS5h&^?P_(W<(RuMKyxPoSv3K+$FbMFRwi1_~4n5-8eSplGl_(GY>6 zp#nu)2owzyC>kzMw534N2!W!J0!5<)ibe|*jS(o?N~kF6+9bbY2Bch_9;0;&MJuFx z*IPF!C0|L=woQsN>O#?Y=R?tUb|{))hobH6P_%;`igvU^(L_5GO|nDLWIGh?WK%Rn zplD}-qFn@vb`>a^Dp0hWK+*03MSBPo?I}>Smq5|p0!8}>6ipK-nl4bZuRzg$0!8}^ z6dfQ?bf7@dK>|ew3ltq9R1|H~B!5i?r2Kfg7L5xrt~$J(LjI6D*_Z-=52Y>G}4D4H!$bdo^P$pS^E2o#+v zP;{C=(dhz3X9yIXDNuBlK+)L(Mdt_!~=q}(Q5evSx5Z>MotlTz}P6kXM%*kFZFbhY!L=o&i|U2BJ;>+Dc;y&Z~f zutU*}b||{Z4n;THq39NyqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&ZzyD7s&u z=mCME2L*~A5-56Dpy&~SqDKXa9up{VZ~H=(FDy+>=*w3K`$MNOL)-(MvZHFG``HMc|23U(-JVTYm> z?NHRx4n-^3p=f106s=;1qE8LqtuQ zRvzgeo8c*RYg$UalA;Zo7Td2Hih4O8iZ--EQExjGZDfa{jqOm>#|}lC*r8}sI~4V` zLs37QqW%I!n+X&R5GWcbP&7!OXmf$0!2(4?1d4_V6m20;G)$mqxIodC0!1SPibe_) zjS?stEl@N@plBUABuLcL(z_QD4J-8qDgirnrw%no$OFF#STR~+o5O|o1$F>ilzz_?IuvP zyFk$%0!4cY6zwHYw6{RfJ_1G41d65$6zwZew4XrH{sKh@2oxPCP;`($(ZK>mhX@oM zDo}KoK+)ksMbY@C`O`8WD}8AO-spFQZ%z^@%DD1=xFCd(JVU@9b<>0 zW9?9MoE?gew?okhb|^a04n?!=P;`<_(a8curwA0CDo}KqK+)*}MP~>UoheXsmO#?ZTs{8fr&t%WeB$*^+=-q%QAf(Yj>AiQw8UlnS zH3#>EQ&^uY7MWN99 zS$!6VLi@5-ED41^%X;mCQ0S|y+82dF`?Jni9ts`ETE8L``Z?>Hm7&m~to+rX(Bb&p zHSX;njz6*1-2mZu($(%32*>+f>u!Q@eC74-HVDVxxY6AR;dtGf-K`LgkG<914B`0g zx4GLP9JhbXzDYQ4{~UR6YQR{e!^y;kf;au5H3``zJX&gyZ&aDxMII+dqoe zEgZLh)vQ-IZvQM*zi{0CU7#zw9w89Jha(VN5t~KU@E_aNK@4`q*&X ze!BI9aNK@8@#Jvae!lFqaNK@C=&W$ue!^o}IBq|pZ(cZVKVxlSIBq{A>%4H>e#+6( zaD4kdcMFB%_H#y7gyZ&uB36at_BZ{n2*>TOYF{0W+uyalJ{-5dEV(Wmx4-SSJ{-5d zuCyT>x4&<)F&wwQFmQi3Zr|~}DIB+N+1(P3+xJ{P5suq8&20_G?Yo|KgyZ&YE6<1H z_I(F0h2!>x<2~WHedX_saNNFh^G-N!pL>5l9Jf!N?hD85vtOTuRa;LqW>y$e4Sj@y0k;c%#`{h^7h5B|tiTjy@f4(^Xt^-yw-JJe{J5(@dP zYFVo3r@0%twR>rY#dl9$e^k?OsMd>~)$Ge$buXLvReP5EazVIlrnOLQCp8pqr%}zG z(_Z6JJGDdRlEjPM=l;BgJL)-W+-nJU(zw&kIbP#_8z*Rt2)of)2zSwV)~;(; zjfr**x&@=oFgNUq*9{K~=Z8Y|E_J8bfBrFES|}V3ACp-v=4IB)99=6O&Z-p(B{d1f zVqIJcg}j;}FSAqZ_*lnS|7z}yrsvq3sBOqf^0A3Sv|2b83tlelYDz}POX0LwEF+d4 z>)?K~skQ#$rPAC>Rl4w)rXRenbX}yIc99vn$i#CiE;3UWsh6taPVy_RM^=WrcJ`X% zi6`7mSXI9vy^?C-aQ|v{@zoo-H&Tr@m99|NIw#Z#g=*%8yVl`aHmws6S559#`>Gyw z?3`MDr58`C^+*r*wyRzFBI>)>T<7BR!|rWd;9kD&^7F%?q}r={)OI&QZpdE2jLgJk zyK7@2D*YPdo(_kG+2IzG7aC=UUGBd~sO*|WH`!B0G7|bJJnSY;tnZ$%cMjJ1WiM6v zSLHq1y;?6c!JU#6{xdTp6n4Md%bKy=+`N*ayosf=@=8m_=am$ejxR2pRWh@zczjv$ zguL-3^JkUKv@pJS!km)g(n`;>mv=ASF>hAMl<8B-rpzr4oL5pjqqwxFG_SZ-VQJZ%2~%d~mCc+vZT#e-DKkp*CXF9oSX44SuOPp$ zbz!UgRt1Fx`4)3r%$YHBMsZGY(YPr&1^KzHbL`osrmdbY7m{sIgzwE~}AWE%6)RGC2OXSF1sCxN}aPUo9tbg}4w`^ZNVM z?3%mhB`!JNZ)C^BwK@8~_Dqp*!b)^agE||L-07@MOC-p!44X>kD#T&!D3G{;QDhF>ycPYUWm99d2PIYg*#53I+R_C=Xzc6=w zc%`lM@~tbbN6+#z3VQOY+!fauCZN&>Q2(h98+sLwn=>ioKGvEsskpFs#)K(FGYY58 zoG~f*4Z54ey?Xb-Nu}FFSFKIOwRN|D@Z#maJ)q@R{O&rI|4s^=;n2X|Cl_|_H6n4I zyJ_{CbcFR(uYWi*WLGIW@xOmzR#0(8dPoxB+|8JH1qdrQ6o|Dydc6~8PqjZSi5Jb+ zML4{=COyipll?JGyioUwE7!~2+}%g?ElBio7`)uAL*tGM9{DsK6LN;kc`b%IkWZe+U+{*#}T&?hx2 zKGsdV8G7gqYd5cjj^%F*cjM`8QE>;@T354e#cwunmAI@5N(GfHRWj7hon8T)yUzkB z+OzF~+_C&t;1%lXxjQaBt9AM9M{Ta46?pp}@V1c9&l|d1gsj`FlktnQIZ;=;gO}`TKA8XE5<1cAJbW>@%qQ$bNdo z?#&WhyGj-+Zu^3Y8^569*5{@vaMwCq{C=#5n19-9O& z=yJ7(Lb?Q#pU?GtzT9a^=?ZdOt} zt+=SPxOsNY^zpOibRO^Cbj9;>rnheGLfPaw)5p2v#A!2&%5vOi{W`nbXMzRyk`rgm zZJSd%D`!GMJ6DQI#!v3-J`FgxL(cTv>FyJWEhd!CYB6zEcFv^ioT06fyl~g=RG^h4PuXwOn@er{f zpr5!Ga_FB)CBj!!hd{s&tuezhp0HR2USD+j4XdQUce*Libt0f4=O7j zQ@Tf|cnbb}*wrhC&EwIEhl-URDe`c%;$b0wR0_BYwug+tTS!EM$A*bFfjuDAW7NcN zHTZ*B{@dpdV!3jV+XK@x%kLX`{8{lBvEm^j+{-PLKLRa(Xj%R!veKWcia#9{j{&)* zD;@!s--5xz$WY&&Jv(JLvp-4QOQvV{o<6R4!UXs5dla8LPyFHHbK=ea?|;~ ze@EOe_l1dtnduoJ`w9ZT>?;M`GixtNUg}>ExzJmdv@#s(-qAg`$UgBN3g@{e{SG;U za|d_tKO~eKj}A`t(o(8Ms)uWYYk9T9b;5PS^}_YT4U-y&bM5O2|MaVJii8dxsr+ou zKJ#4Zm#435kUaaubERLN`=oQc(zdUFxG#H$#+1KU@cf09wmtu)@~@6me8t2r#tS9B z>Ss?TetG3z>SMbvxmWt-h5qp?IPNwqhfbw@f_64Z48t$vZ z?(LT3zJtKtDoO6QYHpI;E4AN+9o>s0j_yllp(OW(!$x*=zh%3Q_I$HqNB0c_iKF{A zfyA+gj>B{ut>btdr|LLcNB0H$#Cc0~T&3d%9Ur!@Wx3b0UB`Fa&1(BI9sh8@0o%#$ zi>h|4?`}prHq)_-`@Pv7pyOC~Guob}<8AKuWcxuKzjbc_+lO>4aHwo|(eW(zHnY7{ z$0yy_{%r5k(W@8iEFJs1@5!*|pQz(yM+N(O9p7|sSbP2_I@W6v>}EO^9UJT!I^N-K z0DJjOI(~Otu>a7pwfoKvdww?^=erxq_Juk=T@dV-boAQhIt>f^;!9GLBtCj?Ny^bGT z5bSSsJo=(w=j%9Sd9df|c;AX(KcV9{U9xaBr~R(y__|!LG04=!b$mPRHvu2YZ8#A3qZ8?{#eYSg_mZIQ@xW zFVOL!r-Hpz$KSUGJ9%4h?D|Y_9Hip~JA-|>jxRnJ?00mG?+SK99Zz~G*b{WTVRx|a z((%(h!9Jj4^VfsjPRE&V27957o8J!hb{+rR8|;*KgJbvigX0h#mwg!QD|CE$U$EcR zvD&A>&erkd&x1Wt$D6(k_C_5)ci-`39)8rZ#r|M-&~f(n!9G{VM-BvghmL=_?~1bX z(|!t$J%0&~!*sm(w_snX<14=h`+Xg291eD49Z&r`*pqd<**!wA%fDC0FWom)+5TC_ z9QQ?d+nsbQb>C)X`#c>Vb>DAg`&k{2xNp3&o$mhTvmJZ8@4&L-2punR-->1XY8_v7 z-;-tgLmg|mZ_cvaM90(JcWK$4s^hKh+qG=pujAM5`?hTVs$-t}1}@tt=r|`k*yro` zxcinad;aq}Hgey#WxI=x19Tj2M?VxAt9_;&(?g+|I+m#~)^Vkd*Xg)H$IUu!*YOn{ z-`DYL9e>r)bKiGm*C)%4?)7JDH_LP;Tk`>19RZ+_9`AI8Np%_i=YwDAzvF4dsq2 zEe++m56yEe=Kjk=$HcQH*k_X6r|&1ubY~@=E*dwkq@fbIRPs{?C88hh6SZ zO7OVW&T)@UYr8^io&KSRVs;>)`FK@EDykRcb z<(VZe?q4MP&a+k;3#XWQ{zr0J_)0|_Majd&MdpUmbyk#y_zPyx? z6_=Ocp2zjO!9C46b{Xy5<;}5Is9!wq8n-K7UTt@Ic01Ycw~G6Z%e&J(ZReN=`*n9G z_c6BJ8R(Zi&;Hw_BQLkVPdGF{FJlK@ZkwLwSsnU@%P-rSyC|L}78?)tfR;pM-0xys+K)**Lhp8Fa}yAJuSI<#t)?LP03Ur_1)?b@}; z&hF5*qx&?W{TiFLsP~{g!8bex7aMjTt#Y|mHVsTH`;f=|Y8I;F?mZ7}9{A(d(y_;$ z*ErH=?cgi>UpaK=q5WA`_P77L|MIV}r)IhT#@h0JS>}1aR4a8)+jFyb9@>%r=AlSI zsKuY}hO&?R_Vf57gdZHFSmw;kFO+U73lHC@u#1IO0Cx&FvQ*`bk#8fA?<)MVK9L!sgBzp(o+ z{;_*bqtMj;wqHFIX%sr{&v&yMjB60QeBG5N=?8w2|?sX^LqKzU4>r{HWZc@EA z?m5HUZIc}zXm34xi~9rYR!kXNZSr-&C69c)=+Kj)r$bpayPZ-c)WMrjGo0=I6dXCZ zUATUi^w3r>y!h#52NHkGdZ(WkYVPjegFnxa@PqEoCB479BWhFmPoZO*6i%+|a#A=Y z$309)O7d@v+97(Zi(X9!JZW%k_p!12c0qrOdyaR!z0}Y;V-qQQhx_xIl;S_*9zi6f zM04Gr+(^W?PnRY|qOZCa@piZu@LE>uZcpFsUbUBBeUy9JcORaGlI?%)^^b9v8;wMc z_3baNq}Wf#ZK}WVe3Y97p-3~$hHkbBMVf0iaI>}h7nwBcyV)ibX`xxq&9Ol8MfW^>!h9Tb}M)Nj@ORa zcGvF&?KIo&`gPV$we7B77wr_=?)r7rj@owDubXzVZFl{;Yx}m{_3NP>vF)y3Pi^pSa_3Ndb(-ri2XDl#pSX5;9y(QT&j(b zmD&ioOdBDqv;!eCysGYa30dpgUxrNFhg_*sCFCki3AtKR zLax!2kZUz1$o<*~c|aQ>4{9UiA#H?g(niQ; z?Lf#HuZ_F?({k-T)L zri5(Ml#uP367r0ugzV5n$WCp9Jgbe6=d=;>yf#8!&_>8EZG^n2jgXhL5%RJ&LUwB- zC-BA%AKk{6vRp1b(7Jbpk)pp$37U=unfu zPjsk7;3qoNCh!v->Ja#e4s{9qM2C6=exgHt0zc8A0fC?B(2&4SbU2E@Pjtv8@Dm*x z5%`G?jS2ijhocGnM298>2P88RNeX*UJ0P)5_VC0D2a2wCA6!R{2}g~WDQX_}?ME~u z6dlL;Qq+PiMJ?GP|pW4+4sM5>V8OfTG?66!jsXs4oFU z{Rk-PPY4t>4ST-(Mxa=CyDMrYMXwmC0pY0mGDSnezWs=ggrcFGFGa)HQZ$?`MI+c! zG?Fbvqu5e3nk_{qvZd%GwiJzFqv&J;icTS*=u`rVP9vb`bOMUbAfTv_fTFPk6crIr zG>(9x@dOl2AfTw2fTD>66ip(aXfgpsQwS)UN1QbmpplCV)MKcJ2qCsJApaT-y zX-7(=XmH}=tZ>wP znWC%1zWs=ygraLWUy80}OVM>~DY~95MK`de=ti~_-Ncrnb!;iRnJq=Puu*g?0Y&Qx zD7uY+qT2~5x`TkC4FnY3NkGwE1Qgv(K+#45itZtx=w1Sf?jxY+egcXfAfV_$0*W3Y zplA~TMVkpIdYFKsM+hj|LI@OH8TQ_GKw|q1&Q($rxAAB=YQ9X-lVRU}L{&o3Q=BhF zPqU?HD_e@Tv88A`TZ*1xOVJLt6zyb7(X(tRdX9~v=Lsl!fqWIS0Y$G9Q1k`?MQ;*N^cDd{Zxc}T4gp1b2`GA(fTH&ZD0-iO zq7MjxqQ}Et1NW^Pu_N|@`x8>M(%z$e7>=4RQ}jvLw;yqqQ1mJ1OVMX+Df*l(MPIO` z=u5T~eZ`iduh~-c4O@!7WlPb1Hj2I@py+!7ihdxV=l}sl2MH+pk$|F~2q^lQfTCXr zDEgIvqTdK8Iz&Lx?*tV6K|s-;1QZ=6py)3GivA{`=m-Ht?ifTC;yiW(76)R=&xqX{T#LO{_m1QZ=hKv7ddpvX`1?sPz6$GI=TN0O6* zkMx(?eNnTdsQEHQEtC9Rjie}t^Q9=4Ek${3DavO{Q2|?uTCt_5HCu|>u%)OiTZ-DT zQPiG*q7DQUbtIsu69GlX6Hs&l0Y#k&DC$B$QC9+rx)D&+oq(bq1Qhiopr{uCMZF0q z>O(+LUjmBy5m3~hfT95e6b&SxXb>S#bX=16g98%Fb>I9IX(2_PeWX7)DQdn<(eNbS zene;DzGwvJOVLQS6pdm_(P*|5oyeA=lh{%;hAl-Wv!&=1wiKPpM$u^m6rD~$(HR63 z6%tT1mVlxn0*b~FP&A%^q6q{P6%$Z2k$|E}1QbmsplAvKMNRv>0Y&!{ zQ1k!+MGq2C^bi3>n+Pb{OhD1Y1Qb0&K+zTgiXJ7P=rIC{9w!8fu1WH?IUuoBVF%}0 zDf-JEYCn+_HD9J^Ym#q2VmhH{8|O>WcD58f!iuMpt^eO>GuMtr6Isrv*5K#0c0Yz^SQ1mtdMeh($ zw3mRQcL^wZkAR~02`Ku2fT9lxDEf$iqJ4xw(NjrYw1rc2oqg8vX({^MeW5<`aZ=QL znWE2=eESjQ2}NIUz7&1QmZGoNQuH-jioRh>(YI_V+Rv7v@7PlGJzI)?V58^&0YwK1 zDEg6rqMryT`k8>DUkE7rm4Kq(2q-#4K+*366#YR!(Vqkq9VVdYF9M4GCZOmD0Y&cH zkb@7~Q4}ViD2ad~kAR{G0YyF`Q1oe%H`oD*jkWut&!p&pjbtxszD!Y?=i86CPbi9U zz7(air6_|fMVV|Vs=}6{EVdNI*-})MEk)JXQdFIdq8bDg)g+*(76C=I2`H*VKv7)+ zis}(iRG)yN1_Tr}B%tUh0*bN;C~8DNQDXv%jwYa}2?0gN5Kwe10Yyy-C~8JPQF8){ zjw1w$Qao>s0}`8TpLI<2f{*kU*n^}NUetVPA3OcLIuf5Kz>U zfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwVy34x*<&)e&O#E!KO z%W|dY3%f5G=0(kyDH`SZ_D^gi6piM5DLRoYMJKVPXbfA5PG(EdDQqb^l`Tc5v8CvA zwiKPgMo}RFMPmslDk7k0905h+2`HLCKv6LPMH2}qnnXa+WCDt&5KuIgfTA-AD4Iq< z(R2ceW)M&`lYpXG1Qg9Cps0j^qEZ5i$_Rm?5uSHc8>i?ddnhzgik8}=>p5Q3e3_#8 zo^Ss|OG42C&X=OI*;2HSEk)LkJX|<$1*pNbDDbGf#?sFjCigQS)VrZuETnCw>x&ZsL3?TE~{6 zo7qxy3tNhAWlPa|wiMmQmZIC)QgjDfiZ-xObSD8tcM(u@HvvT(2`IXUfTDW|D7ue; zqWcLbdVqkU2MH*8h=8I^1Qcy1py*)&iXI`LXbS;Fj}lPy7y(6(6HxR70Yy&|Q1lcb zP;|ZL-R*$H68|*y4N~-pk$T#TnlDrIjOW`w5tUH1gY%_mCtHf1WlPa>Y$?}oJbG{UP!?ry zAK57SiGZS?2`Ku7fTCXsDEf_nqC*4}{Z2s99|RQrNkGwI0*d}3py+P`ijELa6pHA> zb`*sPC`uxr$RnUALO_vEKv6OQMNtBZQV4;fFFdck0}^X#pRWE=iq5u2*Qt@H`7%Wr z5#Roay2O1^Cg)306}A**v85=^mZGX`DXPYnqUvlZs==0`nrtbm#YRzW0*dMoP*j(I zqIv`r)hD2+0Rcq~2`D;>fTC;yiW(76)R=&xqX{T#LO{_m1QZ=hKv7cyikcBn)SQ5# z;|M5fK|oPU0*Z17fudN%JI4Wu9kCDY(<8x0`X%-rEjJQ1U#6&4#J7LqFrlb5=Sxu= zwiLBxOHn(v6t!ndQ3tjZb!1CXC$Q6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZ5CV#Z5>PaZfTH096pbJR zit;1gGY&{>iJOrEDSF@Ti$+GG=F1eF6!Gn!$V@02!}(HlGFysHVN21eY$-a8Ek&oZ zrRWT{6cw_iXe?Wbir6R`M?led0*WROP*hAn(L@4@CJ|6HnSi1x1Qbmrpy*5jilz}z zG@XE=83Yu~B%o*(0Y$S3C@LYKsFZ-BG6IU`5KuIifTFVqfuhk7FSVCb^qYOw@kA+_ zocMq(5;b3@Xko;+e_}PE=p4?MqI20&w1_Q5=dq<|FBC!pvO0*Y1;P;@B)MJov?x{QFLRRk2RCZOnY0*clUP;>f+dbSkZ#+IVn*-~@|TZ%TYrRYw!6y3#^qPy8B+DJgrJp>fpOF+?m z1Qgv*K+yvP6g@~l(L)3jZ6cs(GXX^p6HxRB0YzH~D0-BDqQ?j*dYpiwCkQBdl7OP8 z2q=1*fTFDg6m25}if)Q{YaNi-9=k7ECq=XEJ=*q2)O?wuXCuD-6VHkJqUShYik@dn z(F<%T+QpWl7uizu5?hL1W=qj-wiLa>mZCju6unA7(Q5=0y-q;U8w3=+NkGwC1QfkZ zK+!t{6zwIT=v@Me-XoyseFBO;AfV_&0*XE&plBZfMIRGT^a%k)pAt~?839F~6HxR8 zAyBj<;=Sj9#CqF1v7J&h)E;Vo8Ht)NQ}k`bw|^o$p=dwnOVM|1Df*r*ML)2m=m1-a z4zi`_N46CG#FnC;*;4ci8%4hoQ1lxCMTZC|`kjEHKL{xLlYpYb1Qh*6K+)d>6dfU; zDCFzIb`*sPC`uxr$RnUALO_vEKv6OQMNtBZQV1wYC7>vcfT9>7Q1o@gYc$v?>S900 z;TtL1VDHh={iyjeMOnUY|HOPkQJnLos482EsF#$zK6HwHIfTCjvC_0vaqNW5CH6x&? zIRQn-5m3~EfTETJ6y*?5luJNS9sx!9gg{ZI?@e+*V)gC&uB-ULNBTe8HyaiBQS)Vr z+WP)Q!=OHoI*6m?=t(eZ34I)N=ko!L^plApIMMDWF8b(0TZ~}@( z5KuIdfTB?Z6pbbXidy^LJq}3hb-OQWBSk0MebI@2)O?wuQ+$8-NGUp%^QGuCwiKPt zmZCG*QdG#6qOoi#Dq>5~IJOjxXG_rpHj0V~D4Iw>(If(jCKFIJg@B@|1QeY~K+!Y; zil!4#G=qSmnFJKgBA{qC0YxPQ6qOQCR7OD290H2w5>Rv&0Y&o&D4I_|(E>uCXpHau z&~ttFu7 zN&-?zsGDYis|CBLObQ|YO(d}$0x`Qo68`x5GCtHf{VoTB8Y$@8vmZE#uQgkmHMfVX< zbUy(_4-ioFAOS@W5m2;=fTGO=6g^Bp(IW&DZ6ToOQ38q{BcSMU0*am>py){gik>2% z=xG9qwh~aZjew%<1Qb0(K+z6Dpy(FgTjYSm&bNm`w@T4-?s<`&e$;%Kq8EIB-6>ME zi}R)EMYa^Z#FnC$*;2HdEk&=erDzXZie6<)(Q9ledYz4;HwY+tlYpYP2q=1+fTDK@ zDB4Rv(Ypi`y+=UN`veqyKtR!l1QdNlK+!$|iasWw=o12pJ|&>&GXjb}C!pvH0*byQ zpy(?CioPZUik|bmoeoIM{c9ni$n#S4jgk7skD4!2^u6zYaheqU!1+>ifGtG_*;4c) zTZ(>SOVQ74Df)#iMZdD8=r^_$9b%*CcLIw3AfV_^0*Ve3Q1ll8MSl}ebcBGSP_jO3 zM^Tu7q9g)}JOYX$1QhuM6eSZ-6eXZ2g@B?|0*cZID2fqKlukfV1_4Exgh0`L-;15@ z6xr8ZBi~8U74}fON^;bEnWAdRe#=5Bs?PaRRD&%=HQ7>Bi!DX9*-})8Ek$+NQdEyE zMfKTI)PRkmh6EHHML_b_1Qg{GP?SeNQ9c1h1q2keBA}=>Ay5=g_J%tku_AkPT{SuQNWY1F*xx2O zYQ9WShh)E`NQydgz7%z0OVROcDLR2IMV;AF)P*fYUD;C9jV(pp*;3SljiR0e6!jvY zs5b#ceF!M(OF&US0*d+*P&9ymqJaby4I-duFabqF2q+p#K+!M)iiQ(VG=hMlkpvWt zBA{qA0YxVgP;?RjMPmqoqISvNRSrmOxxEu>FGXAI%ONKxN6nWhIz8FnGG2<#;Cv}6 zWJ}RlwiFeyrDz;mipI00XaZY`irG>$ku61&*eIGzK+zNeil!1!bS42s(+DV_J^@7w2q-$6fTD#26rDo| z6rGyvec*t^Hrw|)o+d?Y>^<7K$x-uViq22=|1OrIC7drsOW9I%0b7bLWJ}R9wiI2& zmZFQj@~jfqWIQ0Y#4!Q1k==MNbk?^b`R_PZLnI zm4Kpc1Qcy2py(L_igplCw3C3MX9*~Jju0riE!msmfW+>%yPw;o=r|kCCr8bfDS9c{ zUp`feUgmr$+Rc`tSJ+athb={~vZd%XwiLb2mZCSWIW0Y&c+}4w%6XHy(mSU?Zf`>lB4F!6dg?V_e_(bA30x&equ|} z&ul6Bg)K$DvZd%ZwiF#=OVRIaDf)vgMSrqUbeMpmzX&M$n}DJt1Qdm$`mh~EVFHSh z2q^LhD2fnJS(IRGTeDb=Xo=mn}v0*iuxVEkzC3 zQq+(wMMtrvD4UIatSEPBcLdsfT98didqp+)S7^zHUt#4C7`GsAy8C3>K*TZ#J;q@JX9kZe57C1 zKGJU=jhZi0bbQo5ZMGDh!1+?tnJqCQK+ysMiq0mWXdwYb=MYeIE&)Z0 z2q-#_5GXn$>OJRx#G2TLWrb4oiG36H;%L--nW77#{#SFP=t9nyqGfC;x`-`B7qg{k zIa`V@VN1~pwiI2;mZFtxDY}e}qE!SGttO!8asrCh5Kwdl0Yz&GD7un>qN@lfx|)EZ zYX~U1mVlz`2q?OqfT9}+D7uk=qMHaPT1P<9%>)$PLO{{21Qe|&py)P2plC_d%b4pF z-Rx#$sT4hD54CTPM$MNgx-07E&Xc0MIbVu4vZd%AwiMmVmZJOEQglCCiXLD~(SvL$ zdWbDWo7gDYOhD1Y1Qb0&K+zTgiXJ7P=rIC{9w(sa2?C0qB%tUi0*am{plB-rMcW7{ z+D<^xGXxavAfRX`0Y%ReQ1l!DMb8sZ^a24zy9j}z4N-5T0}|V7e>e6{DXMD^wO@=z z&6g>9CF++gkfJ@DFGa7irRX)b6ur)tqBq!5^d?)1-eOD9+iWR%hb={W*(iFKfTH&Z zD0-iOq7Mit`jCL4j|eE*M?lfX1QdNjK+&fJ6n#cO(dPsdeL+Ccmjo1jML^Nl1QdNk zK+(4Z6zwOV=sN<6z9*pQ2ST9e<*0X!0}>l+4~2G1(UW#xbRZfvU#95isQ=hPDf)%; zrRZ0-6#d4QqC;#c`kgIBf3T(KPqq{tW=qjuY$^JijiMt26opdsVLOV#1QaC^P~;I% z6d|CqfTAb?MJWUnr4mq-MnF-FfTDB)iZTc&$|Rtu3IRn~1Qf*yD5^?8Q8faJ zsuKc5KSsTe9FSNm`^L1Nq^O>es*w^kU#6%|iXU1eMRhq}it4eYs6JbY8nC6PAzO-$ zVoOmrTZ$U7rKmAmijHQZs0jf@#}H6-ECEGL2`FktKv8o7ijE_os09HQMS}?_8bUzPPy&jE5l}RofT9ru6pbXHXcPfOqX{TFk$|F; z2q+puK+(wr6rDmq(WwL!okl>>=>!y=K?oF`km8-`fW-bbIGv?viQN|!rbNw`DH@;R zuUH~Q6F6UrirG>$ku61&*itl^Ek#qRv{0Yz64P;@l`Mb{8ebS(iz z*AY;3Jpn~G5Kwd@0Yx_vP_&MKqMHdQx`lwETL~yyPe9Ra1Qgv)K+zop6m1{`iY`p? zese%#_l6yuWm5FKk-9S_YQ9X-Jt=vY2P8Jc&B#V6irag% z-6>J?Wr|))@y}Q;MXz(d6urTgqBq%6^cGu+-eybDJ8UW1%a)>d*;4c#TZ-Oiqv!(y ziasQu=pzD(_7PC@F#$!N5K#0f0Y#q?Q1m$gMPCq5^d$jBUlCCBH33E65K#0j0Y&=> zDEf|oqVEYP`hkF=0|XQuB%tU=LZE0*inqi8aUa?{IIl|4z4nRhpHiac%M|^V;;&yJ zMTaMoth1n=dBB014peRB>kxxKT zG66+V0*X=yC`u)uD2;%k7y(7;1QcZuP?SkPQ56D;vIr=O6Hru@fTC&y6jdjns0IN= zH3=xHMFs^lXP(MSS{MiEdnnt-Ac2`D;=fTA%36rD^! z(J2HJok~E_X#^CVPC(Ha1QZn#P&Af+q9Q_|sB5Y>+5w4;vAdscQuLHPx*nGrHD9J^ zVyZuPjTBAdd?}jDmZB+aDVoZbqBGf2G>t7q)7erqgDpif*-|u%jiT8E6qOKAR7yZm z839Fe2q>CMK+#zQ6wM=`Xg&c&3kWDWn}DK)1QeY^K+(Ab6fGj4=sW_7786i(J^@8b z2q;=gK+y#R6kSLN6irC=u5&2sM`(~qMsZsM~iY`g@pI9qJD>z?@E@ey6 zO12bT#+IU0Y$;mJmZHnqQnZFGMOUz;Xe}E>R}xTk6#+$86Hs&w0Y%pmP;?yuMb{Hh zbOQlJHxf{E69Gl*2q?OlfTCLnD7uw^qV)t6-9|vs?F1CvK|s+40*dY=py)0FitZ)^ ziY`v|K6XH2z1@r~m!iJ*VgJU|sQEHQ_owE*Xe$9l+XyJyPC(H!1QhKcplBxn zMb8pY^c(?2&l6De0s%$42q=1yfTEWOD0-QIqTK`(y+T0I9zvk#-c+xt0}|_FU&g;r zigw$_Xs@P5&6g>9Gu7{RtrWe*`BL;YTZ-OcOVM7o6urxqqW9QR^gdgPK444HhiobO zh>fCs1QdNtK+z`z6n#oS(Psn{eNI5p7X%c2NkGw81QdNuK+!h@6n#rT(S8Doz9XRM zdjg7nAfV^~0YwK1DEg6rqMryT`k8>DUkHJs*HgXe4oIxO!FfZ9&a*Gg{+b#!U#94f zRDb35QuHV1OVMGr6#d1PqQBWvbc8KMp)`HuE=6Is6eY2x$YV=UgpDGffTCmqilPJ* zr4Ue*N0YxzaiqZ)v${?U9lYpWs1QcZvP!uPis44+P)d(o6PC!u&0*Y!9P*jV6 zqS^!$)ghp$E+J5KDAjw&0g3Im$3?$OQ70Sq(xT?e6djf3zj31!Wpln1HDXIqW406> z&6c7jY$-a1Ek(z&rKl-eikh*ds5u)&#}QD}f`Foy1Qg{EP?SqRQ62$B`2-Xd5Kz>L zfTGp}6ty9ss4W3S?FcApPe4%z0*X2kP}GTlqT>lDI)Q+q&IA;7A)u%$AyCvH&HLQ} ziLJG}pN46{NBVPYbW4kxFH_Vj&98g26!qqODeA+PqP}b?>c^I%{%k24z?PzcY$+PV zmZHIIDH_5?(NF@4h7nLSoPeSc1Qd-VplB2UMWYEQI+1{)lL#mpLqO5V1QeY@K+&lL z6rDyu(dh&fok2iRApu2W2`DNeplBQcMdJx5nm`B?^+@x&Iv_FoNkx&KQgo+{;t7q)7erqgDpif*-|u%Ek(20QdGj0qEa@B$_OZ$LqO47 z0*cNeplBWeMe_+LT0lV2*#s0VB%tUV0*cNhplA^RMduMvw3vXR^9d+gLO{_{0*Wpm zpy)yZik1;jbP)kX7ZUfp zO9&LLNb_EFKw`hzCmJu6qHOy}|Gu=S`7%WhrTP2skfKeTFGZW#QuHueiXLH0(H6E8 zJ<67%$JkQzI9rOIU`x@HY!p33K+)3#6m2D-Xd3}V+X*OohJd0S1QhKgpy*iwik>5& z=y?K)ULc@o7Xd{t5>WIK0YxtpP_&zXqE`qg+CxCms{|CiMnKW)gh0^)XMkkT%lT6DE?bJ;V@uKdY$^JHEkz%)rRXEJ6zyY6(Z_5l z`h<<5PYEdcjDVug2`Ku4fTAx6DEf+kqOS=k`i6j_ZwV;cPe9Rk1QdNwK+z8b6dfR- z=pX?_KN3*%69Gj(6HxRE0Y$$OQ1lxCMTZE1qPNn#lN^v()IKbGTZ%I6-P`YJQS)Vr z{z~)bZIq(FIbVv7u%##z(?{-76lP0N5?hKqwiHF!QslFxD48uqQ8tQF2q;P=peT)i zq8I^1=>!yI5Kxp!Kv5L}in0hOiW5*&m4KpZ1Qb;#pr{4`MKuX1szpFiZ32qw5KvT? zfTDT?6xAo7r~x5R^k7lAfTut0Y#k%C_0{iq7w)x>P$dU7Xpg95>V8QfTHdM6!jnkin3$g zrw&N$J9}KzC>DIAKg8~fdd8yW%M|sE`H=^ts2}G`QGd1+4PZ;rK(-VOVoT9rwiFFv zOVLoa6b)lb(Qr13Mi5Xml7OO71Qd-Xpy)&bicTV+Xbb^GClgR~3IRo@5>Rv+0Y#@1 zP;>?XMTGX^T3vlLy< z`BJooEk#$brD!c%imqf!(N%0Ix|%IT*RZANTDBBj$41fh1QgvsK+%l^6x~EX(K-T( zZYH4U76OWHC7@_M0Y$eFP;@&1MRyQTw1I%4I|(Sdi-4lL2`Jh~K+!z}6x~Ze(R~CI z-A_Q#1B5`)WifBF0}?yO?u%AQk!SDG9*jlJmnnKU=D+ob6g|TEQnZCFMUS$j=rOhw zJICB?5|GCZK3H0Y$G6P_&1DqE`thdX0dh*9jDEf|oqVEYP`hkF=0|XQuB%tU= z0*Zbjpy+1;ihd!W=vM-Yej}jh5CKKM6HxRA0Y!fj0!4dcUUvs1_Kp43{CB13kdZnZ zi<&P}6iWBUJt0NmbbTZ*MM-Qa^4L-oVM~$EmZD^~6h+xml){#xRJIhQu~8HwpeUVy zq6`9xG6^WELO@X#0Yz~FimDP&RE>b5>I4+kAfTuw0Y$Y4D5_0BQ5^z`>Jm^?kAR~3 z1QazOpr|1MMMn`(luZZ}{T=g`IUuoL?PrD@k)l@ad67oxQS)Vrj!E}7JS9cPa=sKb zWlK>rwiGpIOVM#`DQdx%qLyqa%3(`UE?bK7*eJ>;ps0X=qE-YHwI-mb4FN@M2`Fku zKv8=FiaHQb)RBOqP6QMkPe9QL1Qc~9pr{K0MO_If>PA3OcLIuf5Kz>UfTCUm6!j(q zijGeAUUooYAKQIVll0&t{dVbY^huAJFHD{ z#+IVtY$+PSmZFhtDH_E_(P#pSP9&h{Bm#=Y5Kwe70Y#?}P;@E*MW+!^bUFb=XAn?S zNI=n80*ZlpV(Rc!iCJ<0mOhC~@0*WRPP&AoT{~fTGI?fuiZ@-pLL~teZWco*_jeY^+L;nlDpyMY_LW zrxdN_d?~t;Ek#$crRZw56kWrXqHEbwbRAoYu4hZp4Qwg8k&U982q;=dK+(+v6x~8V z(X9j&ttX)9HUf%nC!pvK0*W>eP;@5&MRyTUbT}r{4oEE79#F55qKgwBu%$=MmnnKQ-QW706g|fIQuH`mik@Ig z(UWW`dWtPYPqU?HD_e@Tv88A`TZ*1xqi6>KMLP*7dX|8q=Ljfzo`9kk2q@Y`K+%f? z6um@1(aQuB?Ixh;6#|O(5K#0g0Y$G7Q1m(hMQ;#L^d}PXdY#6HxRQ0Y!fk0!8nqdo3K0*kkrJ{STz* zJG(DBk{&f*rpU|i2fZXkk&J)*NZ)5mQ8HVKqHHNjVM|deTZ+=yQWRrLQ94_SGT11} zB%r7Y0YzB^6vYWBs!BjnH3EvN6HruxfTEfN6xAZ2s5SvbbqFY`OF&UQ0*dMrP}G2c zqJ{(%9YsJlQM#j(W<%UMVe$p&6g=^mf>H% zTZ)=qTy^Q z8o`#Lk!&d%#g?McY$-aCEk!4>Q8b2tqLT?II)#9uQwbL$s$pjQlA)sg~0YzsLP&AEzqUnS{(ZCGvF9#&n z$?l5=Ns)b;C^91>YQ9WSNrvC>btx+4d?_kpOVJ#*6wPHz(OGOMn#Y!+`D`g#z?P!3 z*;2HSjiPf1C_0ybqD2H0oku{?VgicJC!lBv0Yys*D7t`vq6-NqT1G(8MFbRGOhD0c z0*WpnplAgFMVAs#w32|L%Lpi1ML^MN0*Wpt1d3*5cs(7E*k=2h{%k2~YxhNKGNR_o z6kV0!Pk2*`uI79xx`r)9*RrMPI<^#D&z7Pa*iv*OTZ(RCOVK*E6y3~5(JcfN-AX{w zdIE}WBcSMZ0*dY+plAaDMRyWVbQb|dcN0*wk$|Fm2q?OjfTH^dD7v43q6Y{ldXRvk zhX^RzL_pDI0*W3cpy&}oplEG|cd-K!+hw11yi$th+N0|&8Bz0Pik`^u?|NH`p5%Nf zdWtPYPqU?HD_e@Tv88A`TZ*1xOVJLt6zyb7(X(t6Jx4&%^8^&VKtRzh0*YQFpy(w6 zie4t5Xg2{xuMkkQhk&A22`GAvfTGt4D0+i{qBjXBdW(Rfw+SeEhk&BJ1QfkXK+$^y z6unOf6g`&Vz2bnx_S)Ug<2)|1uYi1z5j9_?=;I9kz+Nf(g!857Q??X+#+IVb*;4cc zTZ+D9OVL+sDf*f%Mc=Tc=vy|5_7hO_9RWq(6HxR60YwK0C^|?$(T@Za{X{^~&jb|x zLO{{41Qh*7K+z!rihd`c=nn#l{v@F2Fabq>5m59u0Yyg$C<T&rYJenZ}+|wMLA!JQrJ?I%9f%uwiLzKQk2e?q71eaWwNEH z3R{Y@*eHq zWr|v4`U^jlqL!R5MLBFK%4JJY9$Sj?*-})%mZDZ{DQeA@qBd+PYRg7ZI|7Q@6HwHF zfTE5B6m=q?=y(E(P9UJDGXX_i2q@}GKv6dWinv)_LeQcx#Wk$`HDH@jPZ{H_H!#Q7yMzE!5 zBwLC`v88ARvj0Yw)QP_&GIqKgP9x|o2XPC(Hb0*bC6plB^2P*j@fpy)mVitZ<%=m7$X9weaX zAp(jv5m2<5fTD*9D0+l|qAdgzJxV~)V+02zGZMKv(<^mAVvX#xj@L-hnRZ|FcxKdm znWCpN{VTqdqOF`SMcdd?w4E(Q&#iGZS? z2`Ku7fTCXsDEf_nqC*4}{Z2s99|RQrNkGwI0*d}3py+P`ijELa6sn>R+ffuIpeTue zB9DNg2q94PNv3zi0f{|pa6Xlyc}B{w5;b3@D7A{8yqIPU4YR{IU z4r~;4B%r7h0Y%3XP;>$TMV$#K>Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq z0*d+(P}HA*q5%XH4J4pw5CKJl2`Cyu2o$xf;$7l^#Ae&q(Q>5d78^sWM9r5e8d=5P zctDCqalRCd{y)UscX(8Fzqb7~S+g?9gfbI)4~P^YgwR3h9YLy!iiQB8Lm&wVhynsq zLZ1jn{}N@?)%>RdG;Usc;6fcu3TrbCPU`KWKsmS z6rIGDqLbNDG?pzzr?92yRJIhI#+IUSY$-aOjiNIMD9R(CXgmQ$`2-YAAfRX>0Y#Gt zC@LVJXfgpsQwS)UNj@~jkbt5M1Qcx~py(n3iY_Lg=n?{oE+wGoG6IS&C!lB(AyhQKs$c6zr|2U4KH8a5 zv@399bJdvnGDTNa4Z8d+MOSma6kWrXqOEKxx|S_P*RiE&8(WIDv!&>IwiMmKmZBTk zDB3|l(M<#t-Aq8yEd&(pB%tV40*Y=UplBBXMYj`BbO!-NcM?!^7Xd|g6Hv69fTDW{ zD7u$`qWcIax}Sie2M8#7kbt5+1Qb0)2o+sf)j!<<$>?DBMO&n(iG4(SxN6LNnWBAF zgL8hBqQ^L2iXLZ6(GzSbdXg*(myffTAA>DEf(jqMr#U`h|d^UkNDs zjew%x2`Ku5fTBMMC^|ww(O(1<{Y^m8KLiwc34Pj*q6h&+DFhVx1QbOHC<+KDN+qBu zMhF#sTGc<~fMg7_4`QE5Q7yYKN=wAdmno{02;xVis50kEQ5CinRb@+2f-OZ!wiIQu zrKlQPimJ1vs0Le#YO+yOi-4lq1QgXFpr|eZMfC_Ms!u>s0|JT~5>V8LfTAn{iW(D8 z)P#VdqX;N!NAygDk_&E+p#!~w}T1F!L zO#c!4@Rps3nJ-h6n+QhyEk*4(Uy9nZrKkg2iaN5Ts1sX?I&X%Gx*iw|omZI@&6y+08G=YGki3Ai) zBA}>%fTGC+6ip$ZXet3k(+DV^9U%KPY4x_N%#*sAQ{8$TW2RqQDyr~|I9?pe3_!N62XBKDO$|=Qgk+3iq2t6 z(Gs>4EoDp5GPV?*%a)?$Y$;m7mZFtx6rD#v(JBIpRufRPhJd2A1QeZ5K+!q^iY_3a zXgvW%7ZOmkfqXG_rwY$qaMXwN0^eO>GuMtqRpMav*2`GAlfTA}ED0+*4qPGbsdWV3bcL^vuKtR!Z1Qfkb zK+y*T6dfd>=tBaEJ|dv#V*-jkA)x3}La6AmgnxkplJTm2TK2dUZL>$$pCw}E%M^W? z2yRQ4qOUk#ioRw`(Kl=<`j#z4-?63WFk6bgXG_r!Y$^JYEk!@EQS>tbMZXYG^eX{H zzY$RMI{`(15K#0d0Yyg$DEfR2Tiex|?4?u*(cW9G{gbw~!?sz^~s&X=N2Y$@u@mZC0fDeB6WqHb&{I+iU( z$FZfTJ6no+uu;^LfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwXM z6HqjifTCdp6rDgo(QpEaMi5Xml7OO71Qd-XplA#sRMal%=Q$u5_t-U&SOi_Dz+4@W}|2g0Yz&GC_0~jqIComT|hw5dIE|r zB%o*m0Yw`LD7uJ%qKgSAx`cqDO9?2tjDVuc2`Jh`K+$Fbimo7_=t=^Lwh&Ns6#+$8 z6GBCclm1r@NJg&R{hTdD>up?{tEk!%nQgjnr zif(30(JgE#+R2upTiGbOjew$E1Qgv)K+zop6x~Tc(Om=--AzEzZUTz#A)x490*dY< zpy+-AiXI@K=s^OC_7G6?5CKIG6HxRB0Y!TWD0-BDqJ0DuJw^x>U7PfC9gvJq?5mE~ zNzod+FM2!~Ghe3Y>0~gfmJ~h1`BL;OTZ*1zOVRUeDSCk|MK7|Y=q0ukz08)PSJ+bY zDjP+w5m2PXSIoG(S+v8CuRTZ+DCOVJN(Df*EuML)5n=x4SR{lb=_U)d=7jew%x2`Ku5 zfTBMMC^|ww(O(1<{Y^m8KLiwcnfkOHMG*puQV1yW2`GvZP!teQluAHRjDVsv0*cZJ zD2fwMltDmIB?5{n6GBB_CH;pSkc>y|zUXTys%Ib3s$|B@mnq834BoFNMb$W8imJ1v zs0Le#YOp3B1&e4pXsl3c%tnyW9G{gbplApIMaL6RG?aj% zVFVPNKtR!O0*XcuP&AT&qEQ4CjV7RI3;{(a5>Rv!0YxVhLPZ@j{lN}MMk|BUNs1D7 zUo`xl8zzmIl0=S$HUY$?iPOVN0?6y>v}XaZY`CbFey5?hK2*itl^ zjiM<86ip?dXc_@U(+Mb=K|s+=0*Yo4P&Au>qCx_S<`7Ucmw=)o0*ZOcZb2(p%mb0a31zU<%vZd%ewiK;mOVMh!6s=)P(OR|?ozF(mIs%F=AfRYH0Yw)Q zP_%)7qKyO;T|_|9#RL>xLO{`_1QcCHK+)v{6m24)XfpvtR}fHiB>_cS2q?OWfTF7j zD7uD#qOAlJT}ucREy?s>cR(^eb2GYBioUaPU1rRDc~!lX=uzoe%_3f6r~8(zmw3^@ zB@VkUQ>G;{-Dh)^5*^$_^F-pL%AQv}aYa?ntDQKQ^t}3sX4O3}D>1XC=QT~-S=;kk zBz~*wd94#Y8hBpY#EM3q*CFw2W6$f7NHq1l;}Rz|^SoY(EiF8+U*e-lK5<#=WR{2&hxzOiK2YZ+mX0$qUY^Q{9WLAwv@M0+t+#CPl+$rd){w}wi`X~NOJzg z?)@K0?zz<60Fh+MCU*-&l7p^rH$f!1ev7*eBFX(%yBi^rtb47y6(Y&;+uY3%N#1b1 zyB#7)``7H7Mw0f=k++B>?cbAb9ZA|h2;4T3w13gHLnLYcBxjdM(*8}w<047>NAY?^ zlJ>8f^@}9!pQRcUN!q_FG&GX@cCWilB1!v~J;p?m_D?g6jU?^w)*ly1+Fy=7K9aP* z-Fi|aX@5QO)JW3)e%YCkr2PejpLUiN&C*<{z%fkb@NsvXPY*_t_SLUXB1!x5#TSvJeg64% zBx#>O9F8RI5#UdeqN_7 zqjE;2j4tjsn_lZ*UMucitHOn6Xa?cis-%l_(=M{IF0%BcP`yEuScS? zyLR@LlcmoDo|mcLklskONMvv|yZGvj-8-p9hYDAyXPx8fcwWsmk)Cz9md)!VBblka zYG2-`j-690sPO73weIcX-gmVtUPOKOmg}rJH{#yMx$gDru01#6rPSWor?$Hh+IaQ` zW>+b_YirlQaSi9ych9)!o}61f z*=tpNs<@XqbG|ppy+%sp&nlI@hi4*hki)Q8I zw#{pw*RE~5+`Qbj7PDQN%N-7F6>)aRFGZvzF1IFRQfIn-yA7G~0MTg0A z_v=9^M!$U|2&(;ePeCNrpArc&{d!q#j|w9G_$>E)ovhpjL6DjgWTv`vQ@iVEyGF$q z@CtUUKB&SOyr8Xn7!|1zWZ0o<(AW;{5=&*-N-xT;Yc==UIXOY&CPAiMR^y;r>2H9`;Q0T%S`AVojT<-0X&qFvtC>@F zFHp}$8oA5J{+ElgH}UVaZP3`RZ|U#tsQ=4*Ei<)dPSBuUP;E%* zMcTFbzdjq@jP8A$T0O|L>-;}@XEtv8U%m2waU;67pOgJx{RaP|{!f2{|NEEt|H-?| z$#d^B`xDYwe`NljI5Jaf1r1vM*Ee5|^O5P^uXc--8_Y_r5xxyH|Br6WNcXIi8ty~R zsQv@<2DBaI*)g|E+d+8~!e={mD0{YJ-?C>rbZ?3PdSMC5V#XZAsvwzv|BiCJ-(%0|mUM(-ro!!1&UU&()?u~K604}Y! zF0D`bCAjy1d$mdPX3bg{UXot718=yuLg%t8;NGESmt6KnI`B67mA^CGyFjn#u5$Qp zbe9r7Q{gIf=2Z92D}AAR$LhR}Wf$hI4{x-cUcY_$_2^r6Ms8o;l)K_O!vs`#K=Hrz zVYFYtgn3gu_t<0hl!Cm1*^{Q_&(51!ID1O?8+12`d-Lvtb%onRSFJ<&wRN|D`08c9 zJ)pHM|J`*h`<>)E!`|`zPs!`uZ&c}d?xxjm(h=5k{r=@l&#qEd>3{x%S#J3i=_5&i zb2nq@8$ei@p-`;-(d%D&_H_HxQu?ZGbrBA)u1TM=>tugSOJAvX`IYPEZtmWr2IiLb zG8nw!+%9DolUr^ND^STT$LM|sdb0p2qu}lhO5aFsxvX4AD{O6fVL7(k0o*JymS>Mx z^cW|vD7;JHrgOie@Pc^8Zllt>rt;g_-COCp<+>}!v$^H(o(i{iXPwS15<;>I>{9-| zbMM*kZM5T!l}pGir;uC0g1foGQ_633Zj{_UdS}>8VsEKy+4Xhra9!Qkm+ zC$v!dyDq=^b1U5b6>j%V?(}k$+~wuM$6jm~YUd;;Ds2C1oGU95${+ zc%zry-en(i-5-yXu=s9fp>oIj-?duGAxDJ4_8w{^2c-KkK%Ge>7{o%?tWTVtNg|YxtD#=E7hHs_pcw3c^Fy#C=xdIxM%o) z(PbZLb9vBM{s6H2abNkvKKB3;KH(n+yLx4gdB|A)Xs*J8IUX^VKXT(wMlScb_NXp= z4@qSB@U8S+V2>H~FtYTw8vZ#f`|b1Rt_-!ig#XPi+2|`ip+s?Ae#pc(N~@^{!HT zdFqN_W%N9MRm%E^*So8GX}*0W%8TTuQ7j~?nqx%xEm*QU7*pBX9VAs)J zZWiq5zCl)cbl(;$J@(Pjz9w%kKT${bwYSneUB|gPx^GaG_7ysA&~b;3_t^Dxm$OgD zx7^KY`x71iaK8cD_RlffvA+Ag*s+C1P`dx(zX-S5HnOdYRxH>2%4b^OY`18o1M zW3GE2+3um^nKi?`LdS>P*ShWH&+6#c3wJ`t!R~vI_VSZ-ys%NYx9Iq~d&k<#Khm*Y z({Q)YF~3>3XX|*Qy8-O=@7D2~W5WH1j_tF<-Al)X?uN40KTpR;a>M<+jzNcTXX<#o zyFu;s$LhGTOSrGr@y%}G{zS(H?uNJ5KSsxiJ;Oam$D4YG`yL&?>l^MPI(8fo?mjx6 zH7MMxb$oP4xL?#UHZ0uLbsRQ4+^6bz@yKv*)$#4o;r>j=Mkj^4wT=a2!(F7~EvJV2 zJ{`Xw7w*4x?3@?wemb6=AMUj}KIWj?`{QLD(hI^cjmrf7&bvnK~Gu&V3 z*tjs#Ubwya;j!z2@HjxnC5ytnPRAz}hx=6>GnRzAwvHp0 zh5HO0FJB(+?K-}e9XD?Y_YFFJ;J$Hfx6ju)9(`@N+vzxCTeuhKc*phO zepts}Zwz;IM|kXhb9fx0JsaPQFZ!+XR1 zt&Ytf2zLh^XYC31A|3B~INW=6{C#h@Qy&eFJs%5?Lv>vFM7S@~@wunM{g#f&XT#l4 z$CIBA_aq&!dNJHL>-h1@;XbTm%h$r)Nyoz1!@XF?-EW3_pN@aN9qzPu!ej3P;qe3= zSG^zZOLTnUV7TAWvD(Ms&eHLePs2S~$7?cQR1KX9{|LJGP{_ZCZ>^Mrt z^WBdg*xsb$EAD3yY`?E#E%(C+wwvmBy8EdF+tYR2=6*cE_U$?zazCeF`xhN^+z%|+ zK2FDZS>Zlc#|PbyFxbnV*0HhsF$LQ_bR44NNIM3eH(q;&9pj!?sAGxxG9B0Jc%_az zblk1uJ{@1u@qmtpbo@m}-~F6{U7v&<-P_O7ZmMINJ#KNml8)7MtfgZ^9h>ObO2-@> zQ|;(3B%$pNrI+U(?vx&j?QxL1eD`p~OR4Ie~x{^Oxz>5C@Wmx|rj=O-7svr3=OpD>}QV19UFSlqX{E6)5P zd&sGa4qxLx%S`(wwJypw(fQQ{q0u# zQ3SjF?5VZ;#lgVGsY9o4RoR6 z; z{+{gZTIcP$haLa&cJFtWm*pByTwaL_6)$g#yFA`6?xB0x<(==I=N!9?x83F0>+!_P zR=H5|@^)6ZyvpunT)(T_^PFRsamZcXN_)rYiI;75yW-{TahGSell^|(AH%ZCyU9Io z=a>h3n%&O5|Lo2{PxdnVb+?YZ-mV@IZ-`#U4!qu@dY%^@aj(ZY*6jCTPY=0Y6|djp z6@I^VAH?tXMfbe3JjWeMpIY~fc-KuAlo5UiQT6Rrmpo_HEk~=D2Tybn4=MR-;|}Ecb>aLA5M=CKO9LPe%MbNemJ$t@WatcvF7!TuQ#;*pvQjux|jQvs5{vG z*K@zd+j76MY7Mdfx?fw}uU_ug2KUQzzm~dR_8JG>uPpa#g!|RY{TlCndG6O<_sd>B z$NkE3zeYUt#o<+6qGm5|wby0q-Ckm^`*qO$+V4L0gtv1v@{>bXsh(SXD&9Kox04b{ z9qs<0q(ssR-G{-Hl;BXz4zWBJ{ig0Wo-(Yq`<%)Bq(k7l%ka;(*BV}Dd})dua<^kj zT2RHwPf3flbhlJA8rT=%QlhaB+^hJh?$!O))q30WH@G+Lx2-vc3(baZw)3JbH5<6u-ubBh#Yp-3+ zw!3B>v@>nHtJYCFY1>`5PTC3E?#gx6u4>y|yDr*QY`d%1RlBlncm29)S8}_ZyMD)N zXV`Yv?>OzaZFl{;Yp2_G*RO|mnr(OedTPgPyX)6WJJq(ke!aB=+wS`H(T>`7*RQX( zZ`)nJe%dK+w|CdCzjnm7yM6<-9fP!Jw5k7$yZzJGo1ddg|F@;|o=!$|VC+Ws3MS_AtN*;WTd8qjM9{l(V7x6MpHsg)I`Wh+6XyW8zE!0 z5ps$)LQd62$Z6UL8K;eq)3p(DhBiX-v=K618zK4H2$`Ubkcrv|nWT-70&Rp$)<(z_ zZG=qKM#wa6giO~)$PDdJ$YB2~cl)Pb=k92tLqZ|F+&xruX3XT6kU7Cu?uDg7=IT@l zDbkdXVoeDt(Ug#Rni4W!Q$o(vl#m6Q60%TJLKbNvM;jqav=OpY z8zIZI5pu3JLY8YIWQ8_DR%#>UJZ*%m(niQ?ZG^1RM#x%igq*L9kagM!xj-8s>$MSb zp*BJ`Xoo^(`<2~YMtT+Z0Vi4*3OV3tL^sAvjtRLmsO&yml?u5`r%K4>ni8@}Q$jXt zO2`$O5^|-cgly52kgGH$#sM#%Nr2)RKUAvbCx zWQR6FZqi1`&DsdLMH?YIwGncwHbQRGM#wI0gxs!;kUO*ya;G*z?$Soc-P#D*tsM%v z*w1mdfBHhZ54j{1@~J(4Pt4?)kOzVscc)S+~X(QxqZG^m|9SXV6AL(xY^dIf9 z$Nl;!V~ZM#wMP z2>DeTA-`!OnQ0X(QxsZG`-z9SV8RFLAej`mOfZFj!L zyNBg*c3rpK!}1Jv9k<=X@=EO5Zo7x&mD#o2b`Q&|uxq+)pVw3+)Ue>LVS-TIg1d@I zLNyESI%X0wEx0RLjgYk9u4Q#X!h*Y+H3(HLxa(PyP{o3~qO}N>Ex2o1n^4IG`wXWJ zA;W^ZrgaH%3+|fMBcxk!*R(z%&4Rn84G1v{?wU3vq*`#-v=Je&;I3&FA!@;0)5Zkf zg1e?o2q`Yu=Q>9bA{N{=ZAx%JDo3L!5&r=PB)-cYp7@ba(L46I<>*Mvc$uP>k>FkT z#g9@&$8f$BwPH(AYqk_+v!$pFTZ(enQq-0$MY(J#YR8tM_G}b&AfTut0Y#k%DC$f= zQ5OP=x)M;-jew$K2`D;_fTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF4IrRs zAOS^#2q+p%2o*Jtl>Tf;e39K1wUDA`jnt4x%zT-m6Wss(QeBFMbG{UfU`x?RwiJzG zOVMby6pdj^(TQv+I*BbsC$pt!EE`3q5Kwd~0Y#?~P&AH!qSFZ|I)i|sJOYZw6Ht^- zK+yyOiY5|JG>L$s0s@LA6HqjTfTF1c6ip+bXgUE!GYBY}NkGvo0*Yo6LPbL({s0Fg zzR%6*Fez$aqzWUk(y!P$Ma7X|iu;0f>3vZN=S$H%wiL~0OVOEZDO$jmqJ?ZJTEv#3 zv)EF!m@P$Tvr%*o0Yys)C|XKD(J}&x&LyB|IRQm02q;=fK+$;w6s;nlXf**vYX~S> zOF+^21Qe|!py&buiq;cQbRhvn8we=cNI=m=1QcCN2o=qZ`0E^y_yYHtcC<)}HkE#! z6^WTIyD!=l32t@Yb}Uu2ne(OS3bqto$(EumY$>{mEk#$erRW;A6m4Zo(Y0(Tx{i&a zZ3Gl;C!pwh0*Y=Rpy);digplCbQ1wZHxp2F3jswt2`IXifTG(7DB49p(d`5j-9bRn zodgu!ML^Nr1QhKipy(a~itZ(#=srTI=(33assj@5Y@dEzE=A)^(fyH_`7%WhMS>se zO3}ldFGY{ArD!i(iXLT4(LS~mJ;s)z$JtW!1Y3%pWJ}RgY!p3BK+!V<6g^8o(Q^b8 zJx@T<3j`FsNI=m`1QfkYK+!7%6unA7(Q5=0?I)n(H{g9{YgO45dw<-BB1DR0*d}2pvX%p`z$~F94$gX zQ3@ecbTHzd;ef=Saz8T@{ZNWtvHK!FC1$=%Q7k1`(nyNZIA4m=*-{i|OHl?}iYl?C zs4`oMs<5S~DqD&YY$-~zQIttQQ8faJsuNIDgMgx%1QgXGpr|$hMRf=$s!KpoJpzjA z6HwHEfTD&36g48CD2sri#sm~KA)x3e0*aavP;@kb`=Vw96g4M=ih>k>y8{xR>ArIw zO-%_u(|^+Li&~__%$F%@of16JScplApIMaL6RG?Wl3Iwr;c(gBIb-OmF>TS-yUKGPqT5;I?> zXkI_7SZpC1$=%(fpKPWHTu`lk=r$0b7a| zvZZJdTZ+zNOVMJs6rIhMqI1|%w1h21OW7z|MnKWI1QabNplAgFMJov?I*)*&RRk2R zCZK2y0Yz&GC_0~jqIComT|hw5dIE|rB%o*m0Yw`LD7uJ%qKgSAx`cqDO9?2tj1Vd+ zN%7}9Ao1q*C8Bv!bg$hPU7iv%U#95Fl;H9fQnZEhrRXZQ6kW}hqHEYvw3RJI*RrMP zI<^#TV@uI?wiI2@M$ruf6x~Qb(GCKNZX%%QW&(6qWuIEy-q;U8w3=+NkGwC1QfkZ zK+!t{6unD8(E$RA-XoyseFBO;AfV_VAyo8mil5TTDf-O5>iCEh9cz!SKTL_4FH`hs zN^n%R6n)0|QuH}nioRe=(IK`JeaV)huh>%bHCu|lVN21sY$^JVjiSQ@6n#%X(GLU^ z{YXI3PXrYGOhC~u1Qh*BK+$gm6#Y&>(H{g9{YgO45dw<-BB1DR0*d}2pve6_n^(G< z(S1kVec9N)8yg{@D20F`pMat$0Yw2JRP=F*Kga=z&$j!bPo(H?8>xQGe3_!SA56=U zq72TLqDpKjs?3(6Dr_mL%9f%8TZ)owDavF^Q8l&{RcE891_4Di2`H*XKv8W1is}$h zRF{CFdIS{JC!nYS0Ywc7C~8DNQ5FG3jR`1fLO{_`1QazTpy+40Y#GtC@LVJXfgpsQwS)UNzmCIX6XCZOmR0*ZDLP;@H+MYj=9w2OeE z+X*PTgMgwt2`IXYfTFtzDB4Xx(LDqd-Ah2xeFPNUPe9QF1Qb0;K+zroiXI}M=wU*r zXp8UP;DE%BHbqxSQMQdo{FwPNMUVNxQ|^BzE&a)m$2nh$o?uJSlWZw^iY-M?v!&=6 zwiG?fmZIm_QuI7qie6x&=tTmGULv6AWde#`A)x400*YQEplCk5l|Fr`WFS4&X z?vtWMc3<>~A2VO3=nFrn++B(ealRCN$(Ew8*i!U0TZ+D6OVPJ%Df*5rMTgl^^gUaO zeqf{MM*@m|BB1DJ0*Zbipy*cuihd)Y=yw8&{ve>}PXdaL5K#0N0Y!fkQ1lN0MegUj z!%y2$6d|A}g@7WTfTAb?MF9atsRR_o2q;P;go-}%{dNvW-2TOg=;uJw1ZfPkWg1QazQpeT!gqQ(RiH6ftrC<2O_5>RwB0Y%LSC~8hXQ40c!S`tun z3;{*02qo(Dt`7%ZAqQU0gQq-RFrKkg2 ziaN5Ts1sX?IJqal4ML}KH29#e6piJ4DLREMMW?c*=rpzzjblsE>1-)F zgDpjQY$+PgmZE$%iY5?HG?9R!Ndy!X5KuIkfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4 zP&Au>qCx_S<`7Ucmw=)o0*Zk$|F$2q?OkfTBwXD7ut@qRR*< zx}1QbO#~EeCZOmF0*bCAplAyrRJ17S4{<=^ar?RJv!v*t{g}vA(U|!%Mb}1y8H1$g zI?k7(ZEPvp&X%I<*-~@^TZ(REOVJLt6y3y@qMO-LbPF3rI|(Sdm4Kq#2q@Y`K+)|4 z6x~5U(VYYo-9py)mVitZ<%=m7$X9weY>4*^9F5m59n0Y#4x zP_&nTqDKj#qHCi51_vbmlHC_=m7*o~5p7>IX1+|(lhNRgAyV`d=S$JkY$6xCu&QEj#q)nQ9fT{ep95l~d0 zfT9Kj6g4EEs1X50Sp*a{CZMPZ0YygTfTCjvC~8GO zQELKlyY(J%svP9UIYH~~c?2q+p!K+z}yibfMqG=_kp z6A7WB_JO~{0f{%XyPpnHbft}xf|&U-MW+VAGoz*GG|rczacn6%oh?OYu%#%EEk)zm zQk2h@q6us%n#h)-No*7q5KuIkfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P&Au>qCx_S z<`7Ucmw=)o0*Z5r7 zyDvH`h?y@_v?K_so+L#}IbVvFv8Cu-wiGRAOVJ9p6s=@S(RpksTE&*4)odwR!$#3s z0*cNjplBTdMHdiIw4Q*X3kfLNKtRz(0*Wpopy*-(iY_6b=u!fTE+e4masrAr5m2<5 zfTAl1D7un>qAdgzT}43A)dUn>LkJa}9rzs_koaW#wCo%ydcp3CwgxftWs0^3!HHv~ z=z7kVq8r#!bR%1ecCe-BCbksa%$A~C*iy8UEk(DorRX*`igpoDbUOh>cMwo?Cjmuw z5m0nD0Y$qBD7uG$qI(G_x{rXO`w1v|fPkV02`Jh_K+!`46g^Bp(IW&D?Iob-Q38tg z5m59P0Y#4!LPggF{vrn?{(}A7^)@MT|1N|3ge{1fFH`hP5L|hx6g|uNQuG{Kik@dn z(F<%TdXX(fFR`WQWwsQ(!j_^}*;4cx8%6sGD0-cMqBjUAdXs>nw+JYDn}DKs2q=1& zfT9Bg6un14(fb4xeLz6bK>~_CB%tUc0*XE+py(3Sr4vvTC!i>UfTBtS6jdgms0txe^mX8;p6(Rc_g$mkNYMxO zX@Aw!nE5hA)l!4zc~VrJ^QEW;TZ(G3rKlELifXf^s193->awM%9$Sj)v!$p38$}HX zC~8DNQ5FG3jR`1fLO{_`1QazTpy+4| zs4M47Q8%^}9m|%YPtXTKLU#S6HqjOfTDo} z6b&MvXfOdqLkK83o`9mE1QZP;py&hwiiQ(VG=hMlkpvWtBA{qA0Yzg7C_0gVqLTPaYfTGz16crLsG>3qq zxdapy5l~c2Kv4++Me_(KnomH{nFJIqAfRX=0Y!@lC_0OPqQwLholOW8otEmq<$%OD z+E*RNNzoGfh;~kD%zT-mb5n!g3#4c{=S$HFwiK;oOVN33DO$yrqSb6ETEmv2wQMOm zpDjh}*eJSyfTHyT6kSL_(FOvFHWE;D5dlRP6Hs&s0Y#S*P;?mqMVAv$w26SC%>)!( zK|s-!1Qcx{py(5kf^vQ~idMouX`eK)pF5m59w0YzUBP;`iZqAv+3`ig*} zuL+@|XH)%~9gz5L`-t|O6diA$_J5NaGhe3Y`_$mMnNsuv=S$I#Y$^JQEk!@GrRW#7 z6#dGUqTkq3^gCOM{$NYdpKKHzA)x3l0*d}7py(e0ioBRUZAVdrfT9!vihKf!q68EL z1QewbP!uDeD2;%kbOMUv1QcZuP*jP4qRIpmRUx3LDgi|a0*aD^P|Y4mZG|BDXPboqWWwpYQUDFhHNQn#FnBg zHi{Y(P}GEgqN4~XYDz%S(F7DVBcP}`0YxncC~8SS(J=%RwIZOXH33E01QfL)peToc zqP7GS1b&dIp9gz6fZbrLF(PegDG%gl1U#4h$EV!yzit;&MiYBn7Xd+vR zCb6ZcfGtIn*-|uxEk#q=QZ$V%Mbp_Rnn6I(Oah8#5l}RnfTBVIisledG?##)A_9tv z2`DNdplBWeMe_+LI+K8+1q2i=B%o*!0YzsKP_&qUqO%DoI){LwB?J^LC4`F3i23^* zkoZ#jv@B1GvhBm$vRKS~nWB}k;Ny8xbROqR(JHnSt!7Kn8nzUzWlPcdY$;mDmZA&T zQna2eMHjMBw1I%4jRX{3L_pES1QcCDK+&ZH6kSF@(d7gbZ6cs(GXX_c5Kwd_0YzH~ zD7uP(qN@ogx`u$FtppTZOF+?e1Qcx}plCY*Mb{HTMayG;+I**Imz&WQQnbxJqTLXS znJ-gxb1Z1NK#FeRd@0(=mZDqPQgj zpy){gik>2%=xG9qo*|&r08YN zm!enLQuHcYie6(&(SEiRz0Q`RH`r42CR>W$VoTB6Y!tmiK+(Gd6dfR-=sg08-Y1~w z0|JT;5>WIZ0Yx7XQ1meYMV}B*^eF*FpAk^>IRQmq5Kwf8fTAx6DEf+kqOS=k`i6j_ zZwV;+ju0w(A?9D=fW%L;he9t((Pq0ZIvk6cFH`hWEZDtRihkyNDf)#iMZdD8=r^_$ z{mz!6KiE?ACtHe+u%+lPwiNx%M$tb66nSa-v>ine0*X=yDDnv?iV{#15Kxp#Kv9f< zqBH`E(g`Sv6Ht^vKv5+EiYgOORE2<|sst1z2q;PtP?SkPQ8faJsuMy*Kg9fZ9FTa4 z{b1UUQdHAO)kuq(FH=+}E%@^sDXPo)QdEyEMfKTI)POBT4cSuEh%H4~Y$R z?FcApPe4%z0*X2kP}GTlqRs>qbs?arDcy6#-fSuA!JU5KweH z0YyUzC>lmU(Fp_;4JV*z1OY`O2`CyxK+$LdipCI7bRq#oClOF|G66+n2`D;+fTB|g zC_0URqHzQiolZc}8H7;LacTZ!2P8h&;B=RwbL_q-FD+)iOwq)&VAXOdn#B21RKS*^ z$!sZ_!j__`Y$=+?mZIrwDVo8SqM2+dn#D%ZYyyf32`HLFK+#+Rii!v*Dkh+)gn*)X z1Qg9Dpy*5jiWU%1w2*+JMFbR`ML^MF0*cNipy(U|ik1*iw3L9NWdszROF+?bLZ~P| z&EM&O#J{tzI!=(HI!0{cEk*0uQgk6( ziZ-yNXd_#SE@GqTVgiaTA)x3|0*Wpppy+Y}iZ&5Yw3&dSD+nmMl7ONu1QcCGK+)9% z6kS6=(N+SAt|g%8Is%He5m2<9fTHUOD7t}wq8kY)+Cc~votNhS;DE&U*tgDBNm1M$ zUEh=zGhe3Y*0iA7YAL#n^QCAPTZ(RHOVJ%{DY}y_MR&2K=x(+Y?Pg2SJ!~numyM$P z2q?OrfT9NoD0+~9qCEr@Jw!m!!vqvPLO{`80*W3bplBZfMUN3s^f&=UPY_V_BmqTF z5m59r0Y%RcQ1mPTMb8mX^gIDYFAzdSx1{-99FX`4Zbo-XQ6>9`_F`Jhe3_zG(}Gjh zO3`baFGc&=QuI1oir!#L(VJ{3dW$VZZ?mQ79kvv`%a)=8Y!tmmK+*dI6n#KI(Ln-= zJ|v*%BLa#(CZOmO0*XE*py)FKiasZx=nDdh4iQlFB>_cW5m59s0Y%>sQ1mSUMc)xn zbeMpm?+GaSfePA4(u>=$yM+g&%ok&2@Ndy#~OhD0C0*X!{py*TricTY-XdD4W zrxQ?g1_4ER1Qd-YpeUaZD(ac;k8nWZqwVgemlS#S=z2nW%zT-m$?3t|i=}7^=S$I4 zwiHccOVM<;6wP2u(M+}!&03(Lw@>77T{8(=qUn&GXjb}C!pvH0*Ve1Q1m4MMPCt6^fduR-w;srEdfQ}5m0oPfTHgS zDEfhbq8|w;`iX#|p9!I&*V6r|4oLiZ`{aJV6z#Kb&Hj=eGhe3YkMv;87Ag9Z^QGtr zTZ;Z-OVQtKDf)*kMP6K=xl2)mEk!A8De~D;6lJ3*AfPCffT9=yMQH>Sr4vvTC!i>U zfTBtS6jdgms0sl^RS76c5KxpPpeU1oqG|*bRVSdR1_4Di2`H*XKv8W1is}$hRF@Dc z`YqkR%>jvbw#P-kOVLWZFRB-hnJ-h+C?33YwG?G>z7#cPOHmWH6dlEuqNZ#qI+`s- z&Dc`ZoGnEy*izJzjiO@+C~8GOQELKRv;0Y%*jDC$8#QBOjss6pKS$pMMKX?H&j?xK@h#bG{S}U`x?JwiFFwOVMDq6b)fZ(eZ348p@WUVQeWnfsLZ! z1Qd-RplBokMWYBP8cjga7y^n;B%tUd0*X#1plB=sMW+x@bSeQwrx8#zj)0=m2`D;) zfTBDCipCRAlutm>1OkdC5>PaW5Gv{u_q#bDar>K!qJ2?hqaYqLU#4hUJUDHe6iw%R zDVo8SqM2+dn#Go)*=#8)WJ}Q;wiL}}OHmP9ii+7NDj}d~9sx!32`D;~fT9Hi6fGp6 zXb}NLXAw}en1G_Q2`D;;fTAS?6fGs7Xc+-T=Mqq~oPeSg1Qe|#py)gTidGR&w3>jT zHH1*nl(@gt0g2yccRy35sEU0=TN{s=FH^KW9$b696kW*qQnZ0BMH|^tbP-#ME@n&7 zC2T3Wlr2St+ih!c42`IXTfTFDg6kSU|(RBnA zZ6ly)I{`)46Hs&m0Yx_wP_%=9qMHaPx|x8YTL>uHNkGx91Qgvy2oE6_1%OQ*>86`20pGx|{Q*Xg6Dm?qN&Oy=*DEk1a*_v!&<(wiG?cmZCju zDSC*FqK646dW3+Yy#y3JN6sbGhe3YuXs?rQ;PoPd@1^e zEk$02K696%2wRF$*iz)Pr6|glqJS+$scb2Vu~C#pKv6mYMR5X(G6*QDL_kqx0*a~- zP*jzGq67g&Ndk&82`H*YKv8u9ifRy0RFifs0CY! zTC%0+7`7C(VoOnLHj1(dC~8AMQ4Rq`Z3!sKC7`Gs0Y&WzDC$5!QAYxbIuTIRnSi1$ z1Qc~8pr{)GMaL3QbQ}Ri-3ch_K|oPY0*ZPOP}G}%qCSLBQC5ckz5^0}(!LwpI3xT_ ze}ml@_05QxFHkw2XkFa|tL~PC(HL0*Y1=P;?#vMXLxXT1`OF8Ul*e z5>RwL0Y&Qwp`z&-{&WWw1t48s|YB%nt-Bf2q@Z0K+&}X6kSI^(KZ5# zwi8fvJpn~G5Kwd@0Yy6qD7uM&qMHdQx`lwEodgu!Nh`aCTsOr9L`+KryXTp$VCZS6UQUobU=pemGSDK=t zAwXyX0TK`t3j&IW3St*~?*+SH#fDu`v7^{U1sfm;&+j|?Jd#}3z3%nCe?0GcSxa}$ zBiYH2`7oJD0Tk^dpy(F@ihd=a=r;n2b`emtn}DL<2`Ku5fTBMMDEfp`wqg`#l_x_{;WL$4{iFyOBCjJ!Za4k(U{qyitlGnR+BIMQLm) z^4U@pWlK@OmZEgF6vfz5l);vwYHTTrvr$x?fTBzSin0hO$|j&FK|oQGfTA1%igF1k zszE?eO#+H)5l~c{fTB7C6xAi5s2%}DhY?UzpMatU1QazSpr{c6MU4q4$|Hn|4p#Ti zbwJ{~?X!-Dq^P}nUbIPO%zT-m=9$4Q&qz@V&X=Mi*izJzEk&)^QgkF+idwU!s0~|+ z+Onmn9b1a>*(fR?ps0|5qV@z7bs(UqBLPL72q@}IKv5S0in^L(J;=JqTy^Q8o`#Lk!&eChAl(9x z;|M4^o`9n91QeY>K+%Z=6rDss(F6jDP9~t}6atEh2q>CJKv6LPMUx09noK~^6atD$ z2q>CLK+!Y;il!4#G=qSmnS@Z$;7mXJd8ep`eb#Y^6rJau7dL zd?}j8mZJG=DJo-2Q8`^^UBcSMg0*ba0Q1k%-MIRDS^br9?+XyK7m=G#@Jk#IqfW%kY&Ce53)W|(A`blQY ze3_yzGK0t#Df*K0rD!`_ioRk?(bsG#+QF8hZ`e}wEnAAdV@uKZY$^JIjiMh3DEf(j zqMr#U+DSmsF9a0*N9=q|;(>kE@pCE4w@3PiGGpe;6!}@f(QimmH0wVf z=?82nN@q(^j4eeOY$>Y7mZCUYimJ1vD3dKkS!@(#6Ht^OpeRW|Q4Rq`xdar|AfTuw z0Y$Y4D5_0BQ5^z`>Jm^?kAR}X2q>ygKv4q%iW(A7)QEth#sn1Q5m3~GfTF_*C~8Uw z6-BcASq@12HiMIv6+T9*;hq<5mK8H!rl@6BaM4>*)Qa*-})%mZCzo6t!ogr~?5-9SJDvL_kqz0*bm2P}G%xqHY8fbtjU zfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{9Zf*dU_z*Ek)zlQgj?!ijHTa zXgmQ$ClF9{A^}Aw5l}RNfTEKLC_06Jq9Ou{CK6CoOhC~j0*WRRP&9>rq7nj%rV>yz zjew%*1Qg96plBumMW+%_G>d?u*@RHhuq=PC0}@|iw?)IH$Zmq7bFyOQ%M{Je3hKQt zMP-~XMdfTMTELc~g={H0jV(os*iy8ZEk&oZrRWT{6fI$+=u85N&LW`bYyyhTA)sg} z0Y&E$P_&GIqU8h>tstQ2JOYZ&C!lC00Yw)OP_&AGq6-NqT1`OFMFbRGOhC~k1Qe|y zplB@tMVAsnMRT+KUJginPu#(oCq--RwrE{e%zT-mE3<;452WZS&X=OA*-~^3TZ*n_ zOVN6^6kW%bqU+gGbOT$8Ze&Z*O>7k1OhC~s1Qgv$K+$ak6x~ih(H#U7-AO>vT?7=} zO+e8-1Qgv%K+$~!6x~li(E|h&JxD;&Lj)8(OhC~F0*W3Xpy*KoiXJ1N=y5`*=<+Oo zxdRg4W}kJuLW-WZNBU1>#mtu}+L#sG_K_5A;(RH3hAlQOVN*PDf)>mML)Aq zw3C3MUkE7rm4Kq(2q@Y`K+$djihd`c=nn#l{v@F2F9M4GCZK2!0Y!TWDB4Fr(LV$f z?I)n<00Bk+5>RxIfTBYL6nWWtV2+{)Ayo8bmY@8@DcWqeMcbw5XZ!ZqwCtGqGDYdx zLE&do6ytm;%3w=THMSJR*-})UEk&7ZDav9?Q8rtO5^O0-vQd;nKv6CMMKuU0s!2dm zEdq*a6Hru#fTFqt6xAc3=r96`>Jw1ZfPkWg1QazQpr|ncMR^1iH6ftrZ~}^&5>V8P zfTHFE6ty6PilW*6aSllQZi5qKhmZ8#J#F`ZEjwnuOi}CX;IuEKs14^!QCqeYwPQcmD-X99}45Kz>WfTC^$6m=({=qLh;dJs_5lYpXL z1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6dg@K(O?3Kh7eFRlz^gPgiukdY=6B2 z5`We{>v*ITZ8uWGvt#DV6dju#Y}zhGqc~rRMzf`83|orEvZZJoTZ)cjOVROcDH_j~ zq7&FsbRru?ClOFIfqw3w z=>!zbAfRX_0Y#@0P&A8xqS*u#%^{$ulz^hSgiz7QZ2xNqBwpJdqa7nfC)&O1dD$`Z zWr`ML2mTHzTFCiQbQ)WV7O|yhF(ZvK5T|z+78Ul*e z5>Rw00Y&QwD7uV*qRR=PqOxqir2`Vbz;27mrD&VoyS^ejX1+|(HQB+CZ>8v3&X=O~ zY$>{qEk)O}rRWB>6y3;{qMO)KbTeCuZedH&t!xzCMnKW+1QgvtK+&B96x~HY(cJ_T z-9tdpy#y59M?lg21Qb0$K+%H)6g@;h(Zd83Z6KiN5dw-HC7|dr0*W3dpy&w#ik>8( z=qW;|=&Edgjsp^(Y@cWIR0Y#q^Q1k@>MPCv^MVqqyM;wrN zp4}CCMvA_(Z=c+0*d}2plCk< zMF$8d`j>#Bg9H>EBB01i=wUmGA_Nqr5m4k4P!uJEioVYF|8YR#&l{W_QdDN7f<(-G znWAcmp#DxNigUgcRcA|4CR>WK*iw|umZAh(ijr(8%3(`UE?bIfuu)W#fTCIi6xAl6 zs15-|bqOe{M?leG1QgXLpr`=>MGXlkYD7R$V*-lu2qOHoI*6m?=tQD?Rkbzw_US2l{e5m3~ffTE)aDC$8#QBMMjdJ$06n}DJ| z1Qhippr{`KMg0jV8bCnNKmv*e5m0nA0Y!reC>laQ(NF@4h7nLSoPeSc1Qd-Vgo@fE z{PP@;_y&87)>ewXNj+do#LSl|8j}d_*d;|{IbVv#v8CuZwiF%DmZI@&DLR2IMJKYQ z=p?ojO<+sW$!rvzLO@Xw0YwuDC@LnPXc7TMlL;uALO@Xo0Yy^@D4Iq<(R2ceW)M&` zlYpXA2`HLHK+$XhisledR7yb6Tmp*b5l}RrfTA)&sAyEef5QQZFSO5HkCvi*yDchD z#LSl|T9gQW`CW<@bG{Uv&X%Gx*iy8FEk$RtrRXfS6rIhMqI1|%w3IDH=dw|>jDVu$ z1Qe|xpy)gTiq0pXXe9wf7Z6aiih!aE2`E}kK+#166kSX}(Io^Fts$UjEdfQB5>T{` zfTGI?D7u`0qALg}x{`pRs|cZ@g$Y0R52xsJ`!fD%QuI&Y#?^_K`7%Yf+ZEPvJoh?Oouu*g;0Y!HaP;@r|MfVU;bT0u# z_YqKZKLJG#5K#0W0YwiHQ1mbXMH>hxdW3+YM+qo;jDVuY2`GAkfTAY}D0+&3qNfQc z+DJgrCPJv_+Jrye0g3ms+oJVSG{rumJ(Gx;FH`hFB3QgfieBV=Dca1IqL^^UBcSMg0*ba0Q1k%- zMIRDS^br9?+XyK7n1G^B2q^lLfTGU`DEgd$qAv(2`jUX6?F1BkML^Nlgiz6Q3IBQr zBtFz0mOU>;Q|(ibI}$PTWs1H}1kdi1q8~V4ihg8E(NAnC`k5_7JK0k73tNhQWlPa- zY$@8smZIHk6#Y&>(H{g9{YgO4Uj!8WO+e8e0*dw$P_&PLqJIb|+D|~y0RoEtC7|da z0Y!%hDDske*p8wI0Yzy96!`=cMF}Vh2q;P?peRNN6@8oVzi~j~SJ?-#@1*DiyDiE{ z#>|%~%1j2q0V&Gjd@0IiOHqO?MM<_4<*=nFmn}s#*iuxJEk(81QdFCbqB;Z=)g_>) z9sxy%5l~d0fT9Kj6g4EEs1X50jR`2qBcP}W0Y!%sP}G!wqGkjXH7B5`1p!4z5Kz>T zfTC6e6dg%GQELK<+7LoT@uYvG0}_9snuAk489vf~(>}blO~%ZZDJo0`!wyPOd(M}l z4s0pv$d;l`Y$@u@mZC0fDeB6WqHb&{>duy;qu40wK|oPY0*ZPOP}G}%qCNx^^(COF z9|1-E2`CysK+!+~iUtu-bTk1)g9#`aLO{__0*ZzaP&Ax?q7eiXjU=Gx7y^opC7@^& zAykx~^yfMt@ga6wR3Jsa*%+OSnJ-gxTrybe*()gUqQ`T-6pd#~(FtrRI*~0!C$Xhy z0$YksW=qj2Y$+;YOVLC&ii!y+nnXa+WCDt&5KvS?K+#kJilz}zG@XE=83Yu~B%tV2 z0*Yo4P&Au>qB#TwoAe)ZK;qZfm(IpX zQGI))e_AqTzD&^>$>5_jDO$q$QgkL;iq2w7(b;S%I)^PqOW9I%E?bJ0v88A^TZ&e& zQFI;wMduSxw32|L3kWD$ML^Mo1Qe|%py(n3iY_Lg=n?{o)(}v%mVly52`E}eK+$Cc z6kSe0(G>&~T}eRERRk1WO+e8#1QcCM2o)_(`Uf14_)z=Y_32XdjolWlPsYrbDY`Kk zGz_HZCeD|lo7qxy3tNhAWlPa*Y$>{(Ek$>*rRYw!6y3#^qPy8Bx`%+GdkHAIkAR~4 z2`GAifT9NpD0+y1qK646+CV_jBLoyZNF9|5xPC(ID1QdNuK+z5YioPMB=vzXl z=*6VJ(gBIrwA-T1QuL7ByZ$a2Ghe3Yr(|$fH7WX;^QCAfTZ(>ROVO`vDf*2qMZ4Hi zw3{tOzq6(254IHj$wtv%1Qh*EK+zroiuMvvw2y$Ie+VerPe9QD0*d}6py(h0MTZC| z@^bXB9YqlWiqZ%u@(C!45>ONnP?SzUQH+413<8R(5l|E-go=Jh`foWP@iX0w{wPHQ z?U8=aeA#E?bJ~u~Bpw z0Y&u*C~81JQ9}ZX8WB*`n1G@@0*aatP;@u}MNJ7PYDPd&a{`K55Kwdk0YxndC~8GO z(UAlcwI-mb4FN@M2`FkuKv6y+RFswD*UWT^KC;g`X6J;D^l!J@qJo^5`7%WvbAnFU zQq+m_rKmGoin_3+s4H8Fy0N9GJ6np5VoOmEwiNYbOHnU2ih2`J)Q5ngz62EYBcP~1 z0Yw7{C>lsW(I5hfjwYaJFabqF2q+p#K+!M)iiQ(VG=hMlkpvVSLqO571Qd-TplCD! zMPmpk8cPTjwa@WSbU@+}dyLjWissq9>v1_T^JR)o$O+C!O3{g&FGVM@rDy_MicV%r z(J5>xDq>5~M79(av!!SfTZ$&LQ8a~sq7nj%rV>yzjew%*1Qg96plBumMW+%_G>d?u z*#s2LA)u&~fTFns6wM=`Xg&c&WdszJ6Hv5(fTD#26rDyu(INth78626$LIJrIw0{) zc3U)FiaxYYL7tuyGhe3YteoKaTq!!6^QGtxLO{_P0*clWP;@B)Me7JCx{QFL%LypD zf`Fnc2`IXXfTF7jD7uD#qH75#T2DaHbp#Y$PY4w)$??B)K;ld6=I2Z)`q;(|IWhBP zif+jXVzs2`R?e5A+t^ZcJ6nqGU`x@RY$>{nEk$>;rRW~E6y3{~qWjn=x}Sie2M8#7 zkbt6x2q=1(fT9fq6g@&f(W3+uJw`y$;{+5vK|s-y1Qb0*K+)3#6m2A+XcGZN&k#`b zECEH&5m59z0YxtmQ1l`pRCH60-^Kxnx3KTtzgdc2x7(u4IWhBPieAkLM%0m_*EnB_ zwy>q>b+#0}!Iq*o*;4ctTZ-OhOVK-QDSDSJMengu^gaPaTL~!ofPkV82`KuAfTC># z6n#uU(I*5HeM&&lX9N^|PC(HY1QdNqK+$#rioPPC=xYLsb`VhX4FN^p5>WIV0Y%>v zQ1k;KRP=I=Ki>g~zip57Uy-5=hbQ`DPRx9nqF-`?b@im^SI(EB-`G;Li!DXF*;4d7 zTZ;Z*OVOWfDf){oMSruUXb&4jdkHAoM?ld(1QhKjpy&VrMgI~|bdZ3eLj)9gxq8@+ zq6h&+X#^Dc1QbOHC<+KDN++NwMnF*p0Y%jaD2fwMRGomLOah9s2%(~%bNnY9ka(uu z7VVUxsrC^qJ2z&&Oi^xb@Ns=9s=@hERFf@5wb)Wrn=M6k*iuxNEk*U%Qgj$wit4ka zr~w;A4GAb}L_kqv0*dkoC~87L(cuIXH6@^^839Gj2`FkoK+zEd6tyIvs1*T4M-ouf znt-A<1QfL;pr{=IMfn626%bHVNI+40LZ~R2>mPJL;w$Y_L^-+PBmH%DTht*pX1+{O zm)xLnBPr_2`BK!4Ek)hgQgjqsih8i6s3%*Bdam|v;RFPabfTH6FC_0`HD(aN$4{$)@-3(4=DLTn+i^k{1%$F&ekQqB#T< zl@d@imw=*q1Qg9Dps0+1qH+R?77$Rhkbt7o2q;=aK+$3XicTk>=nMjimJmWkC+7OA z9FX{v_I=kUNzn@X@OEZy%zT-mrMba9hfC49oG(So*iy8dEk!HXQgj|$iq22lB(Z4os z&W)KbFWXCtHmz2_MZ`yB?$KOk!u}ccWMWj7=haMHp76Z7 ziBEGpuR)?oP0!0qOsnmA%@X(3^}LpeKMwP}Hi>QxJ+B~fc4N=$n0Tp)=XFg~Z{~SD z5~EspUZ2F3Ej@2Q;`1XtZ*Zb%ThAMwn33;!$0i;q^t`c&zdCr{_{342J#Ru{X;;si zn0TeT=S@ju_4K^yi7~xBZ&u>!zMeNX@nwI{D^D~Z@h+4JsA>?`rS2NS)gd)_076*E2WiNx!(Ja1znr_}SFOB_GX^EM~0EAzZp6FU}o z-W!Qli#+e0MCs|Cw>9zT63^R~*ngJieU|9E)bq9{&R^zv-z45#;dwtKYOM6Uorx1x zdETzX4XZux&&0PEd*0qe>$RSDAUSWHd;dq0k6-StfJpM+E8R5^N%p_ST?LWk1?$~) z5J|p$y}J@3$yztLYax<6=@xf2M3Oh%=B|fG(*8C3W|5@*bL1@}N&EMt+eDJ~4+0lN zlJ+mUc8nzLpXBTsN!q`u*dvm(e-y7zBx(Pu*?>sW{#mNQk)-{*Lc=4;AD?sANhE3i zvd7p+(*9|N@sXtc-TD(EN&CyuCq|O?w_8t%B<-&!o*qfs-!D5WlC-}dbZ#VRf5T&W zBx!#|-=av;{*JXJk)-`4S?5HO_O~1@k0dv3ch^uPX@Aei>PXW5qKGw-r2VA-Ws#)) zsP(!S&Skx0_MW%r3l z(!S?%VJ#&whOqN!q6`euyOP@#oG+(jGwUiX`nG;GdDCeF)zhN!o4jfryv$n|+(Z zt>GWJT!+Prba2I8YI|~hjZ*ii|466oODxrJ>byv2ja++97mby^8(p)PrC#hp_h&EC zP0zX1y|zeqjXUj}qck3{(L-Zm#EqUB|F}QYkzN}2#NFtvG1V?XpK!RRaw5&MYgG5M z>t~OvljBr)URpD+di7o|d7fX}^Rv5GKdO4S>O*R{-=vEb-hYA?Nw&#Ri>U>`6{#YD)my? z?xdjdawM|crL(u3Og#~JUXFezdLy~*BE9QzA&#h*6Uj~QQ}@b#_1rbovC4&O;9iB- z!2M@8k?!}O`oI0puG*@Ov#@-fAQS%QVWwyrYx9WQdZ@8_VVtfyXDWFKV$Zc@)-+D zy!`20p^9u`#Iux}pXkS=VSYWZOi*4tW&M9eIQaou!+rol&9opKn+qq}| z$FuTh%$YoE!IYBx*~OEm&zST7`^6|*TvqixF>QK&-}zG(%$QT!zjS^{+lu$aqVoBv zcS-mjId*>OO!q!7%O5khc>bw_7R)Ic>wYiOj-9ojtY~!K&LcYg-?*9<7MGXUd&~2} zD|+gJIg<-I6ttUc6pE&lOf6n8tGuXu@!XQKcGFFmySk>#m{abC6Evp(z#?}sC-*O% zJ-c*{YlhF=mIWz_euqd9)cD_i1-a=pf`~sgFUa*9wQJ;O=J|{A3JMB37Wk*;6*LNh z^nCXs?lq*2HUB&CjH<_;RZghdtG=TD?|URaEz|vZ8a?pnqCo|NJv$b5Ef`!hDSWbX z$BHLA^{;rcb634&$F8)#oLtZ`eBQwRdYMA^!ZU`Kmd-8oM)VzD)PLmI_TK0syE1h3 zg>Pv9ub@-KTkk^ZPp2 z;UHd%dxGEez>42hp}R1tm+$6YtfpQytcl2ZT%`=gL{9t7n`zR z_Uy&sYtqYht0AyQN9}?g}fN7CNY5E8v-xbPES@y;q8bf_o2z=kbJH=c!w{N;mF?Pw(PFcUgF{ zu=3qqMNb!<&NUpuv{%@*^15)>RQNX9^TsM=6;{$JtYXVu{oyHd)&rGD3yoC>RWs^X}#yC9XwxxFleqdnVRkvmqrqm;PX+%1)! z)uG~D=-v^$c&N%=2iGZAX~osp)xG~pEB+)@UMGBPvD+ZMI(H7Q*zpeEh3?I!o^bC8 zo>y^^+}m=^KKhJxcN6sToanBPRIw{L^&!iBq;i*YV8z+)8qjO3yaZgw?meXERa}?u zDhS^~r44t3_)Qi}4k`mg_YNN zVda(1HDVVwb+Y@2o;va#FLZvx*IMNYt-Su+8`t}$(A^^mU(o&e)Dso&!ou*{wToHh zR=!YYxNEiY9qgVudgQpg{@uFe**)`ig?V=0yr66Qj(IKTm&__DE-Pu3*LL>gxeIzu zcJHy0MQvwy=-@*6^aZmgx#QGXrN!lK-5vX$?rNE0!M)_vxeGhBEt}hRN?~VLisw(B z-qYRFU)Z(n>~^!=V};gJ%I3D7IybNFw7j;*w9jkn?wt0V>@Gmtsk2MU%8I9zw4GHl zXIlC6o&_$2cUaomweFVPVwTS+ozu3=-N|;xGS{XQmls#;@Ll0P=!Z{Kk}a$>YaIW# z4_zV4Dj!}e>^Zxs*I9X2&@`t0{8n5mmG=V+L*OYX?$%frtMVEOl~;W1Orb6+`p*yS z+!3w39|{}0uXN0yF%=)M3%T1_d8e`RzGCHFMRykzKH;ANyLc6jxtm#e53tG|K<;H$ z-rM63gxvuQ-!Xz1-qTC{&h74{?s2AmhvA>Pir+PV$|@{F+3seZT5-e2y~)aZe3f_j zKwWW-SKObhxT9EcpRmfGp2|N1mG|hlf-CRORa|l5okH*E{{6e>wX{Dkedo{48#sGX z$&@MX&h%Iw1gHK8@!+=A|NaNc%XE*p4!K_uFKtP-`#eOR+x)Tz{Qa}@mS?PpotJ)o zurhjqzbftGh}XB9dq%N6hV~-)?#ZBQ+Y#+X^c^zNOV5dosOHBra-%gPwIX%=x{-R3 z!y@$~4I+)w4v)06PZ9jruc|5P?LJiX*}gr9tn$m(rzl9iJ%+6E%Xg0-bE<6nWQO}Z zuD7P5+2hN~U%ux)X;S5v@3~JkRr%$6?vp@Oe)*pJ98;BF?o-!QmVH9ReLAViFW*a6 zS@!(If9+h)eJ(2XyR`Rpu08(!@5j;2%DrY&{_EkHds+MBTbg|e+m7zj*Y^9iV=W!s zXL-Cd_nDn0c62Y)Qr)gEdpY-6=+x1D?m2brr{l3Yj?>XSvQIsKrjG72#HoF@j>~nl z_p!a+TXcNLJ~ia_CLP~*zct%m>iC!Y4cNBt8Mb2`_j|EpQysgx%Wiw1jwiXNZBNtj zM)$6?eV>lsxp#o=KXh#4u6Wzsbe!)#m2dlO9iMQY)VKYTjt375clG+=ae(_ozde7H zj;k7n`$`?(aqn1r{^vT@ZWivQI!oa(6}9 z%P-aOslsr-qNCR_+*vvfa#yIm{1_cqcMbQ|I=9Ur-k{^o3E|$SWBa0T_ttSyaky9L_>6;Y?~m7Yj7|-Aj*dg8 zhx>RP*USv}bvk}HE8IJDY)~5RRyt0a7w%FW?<@=VqdNY&Al&G{icrTXNS9nj>DIR`ve^?T^8;eblkQg+~4ZhXl1xt>o{dqxaaA3_v&yzuH&wY z!~L(0o!5rDzm7}Rh5G^>U${KnZ|j(GRk&;EIP#ispQPhu>%)DMj-R-%4%zkdy^eV| zg}beeQ*Q}(nU43~7Val?{QZt_AJVbw-Qgan<5~BH`$8Qz-yiOGb&Nk0?m9XiyCK{s z>v+YZ;l4%3&mIr=k2)UyRJikXoW3#K3v|5ynQ%X?-F+F&Jp7_# zi=E-_pyRAx!@XF?hj)ehSsnMfFSXhE!5`tV*I(grn2yW$gnO-yTlR(fBOQ|m!rf5E z;|_*LSrE;`Q53-_5iKIXnoXwQF9#|G}J?zUU$SYXG%^N!LUtm8NxC+S$K z;}RV&(D4c#Z_)8V9XIK?MaOiz|B>OoC}v0Z_UxA(-QAAVaiZNHaogQ3@Y1r~mzveR zc4doamlwNFu9cO~50BG%%01RB_uAQmJFnfOvNErog?9h>8S{4TA!@rR_UTdgIq9jT z?!{A27f+frzht3T<+;W4i|0%$aj&HEg#TG)*%zJkD%_>;+D&#}At`a6DX((Y)cM7; z-3#>{J)&K4dHMVqlNOY_SNs3=m%E$eWQO-6?HqSE;y-@5cT?(D6Ze06IX|5Lg&6=%Ik}}=kfZ^cTaPUy$-)s#GAyGQ{{Qf z+|yNG-$wWP>~h)V%XI(o`qsIp?e!J7|Lj*un~2xYUO>O>dG_D+I`VSoc8z#L^)hzg zq&(PqP%4Q)Q8`QSr)4jyVgy!o)rdp8$s-5V|RTJQhF%d^^K zSmTkK_j(a~&WCzV!_>=12Q?VhaA?CJjRwEG*XwI9TWeU&5ih%!``|xbL!DvS!(Vc* z;iW3CyGH6Y9Q}90emU-K+H2pLx1)IOChysU$qA4AG_`U1z8{BnIqC1Av%F;OKAGJI zpv0xaik*@1(R5bw}9CMT1w|bNs&cQpePr zm`btx+;yIo5xnPa4$?AWJ>0b#jRy7!pR{P~UH2mX7WV>vn;L!X=_lQr_6ur`bx#ME z*!hw4Y3@~~N24tQ`zErO{Y_Oz=%)`FyIJT(TWU6Pv%ME>rP=4;k*vzz-FZOz(l7P^a7s9nppyIk$H zYua`ftb=w9+wPKe)Xuf-E?Ot;9NX@)b=FSWb{DRTcEYy1bX~QxZM%!tO*_lByL{cX zGu>|QF5gkw)or`W*F!sQ+g-k%+SP2k%hyXg!?wG8y|rVu-R0|}oo?G*zP{RlZFl+l zX-93l%hzAqeV(UZdw2N;Xs5Z|!Ck(A+7a9C@(t2<3^Jn8X8vpL`mc7A`Dvc|{`qRY zlMy{Sc87Zb6EZBYZ!k;=8Lm?$WQ3-KjMS8nV>Bh?SWO8Tr70n!H6>(>ri6^ul#p?n z2sut0A;)VYWV|*)PS8fkiP{J`NgE*(v=MT$HbPF(Mo5u1LMCb>q*xmvle7^sSsNi! zv=LIGjgYC@2$`mhkm=e8nW2r4nc4_BRXY?i#Q)h{|J71|YwOTZNYvdzMQ6oKjtQ9? z*f*c1gv`^a5;9*?LdrBHq+C-%7HCSyLQM%dO;bV^X-ddqO$j+&6Cr14BV>s-LeA7i z$XVJ5Ia?bc=V&8jsWw8+)kerNZGM#u_ngq)|1kn^<>vQir%7ic47l{P{y)JDi^ zZG>E;jgX7A5psz(Le^-9Lgx5c?k1z!d+q~Hv@{g*o1+n38#6g3z02ec9Lpf*At(niR`+6dX8 zjgUvQ5%Q>ZC}f?V@2>x9J>AVj^s-RMUH0^2F_U9Lo(k-n)>A^B)~OP*QBy)TX-dd5 zniBG?ri47FDIw2mO2`YE67r&^glyJC$V=J?d087FuV^FWRc(a4rj3v-+6Z}F8zFCK zBjinOguJDVkhirF@{Tq_-ql9Pd)f$jUmGD?wGr}xHbOqsM#x9n2-&8MkdL(y@`-jR zV6C$Pbzl@}nj~e$qzB&)Nvtsg00dv=Q>FHbQ>WM#wI0gzVNv$nV++`9m8a ze`+J-FKvYUt&Na9+6dXJjgWoX2>C}FA^WuvazGm)|7s)Tpf*AdX@^2S_siY&U+pcs z@9{-SNc;x74RK#=GdlLuRnbUbKkkzHdv}9~&el&?rL*TLaVRVG_MU6sYwPgiBL`RS?zfuF8Q68Pz=90EUGl}q5Kt7;JV>8hFpe!8j_ zfuF9bP2i`i>Ja$ps=5Szx~d+5pRPKLz)x4zC-Bo%4G8>nRYL+lUDb%dPggZ2@Y7X! z1b(`z34x!kI-I~yS2ZQ@(^bs~4oFrsnilb&azNrQ*xeI95-PghJ+6*6kHn0ZDQXo7 z?8l{2ijL%bDQeA@qBd+PYRi_Qc5EriXG>85TZ#(VQq-O;MIG2E>PSFQCjyE(6HwHJ zfTFGh6m=t@s5=2gM-foegMgx*1Qhimpr|(iMSTb;>PtXTKLU#S6HqjOfTDo}6b&Mv z=x73p1`|*;gb*q^BI3L6YVhLM+D%bQDf-+<4UNRimnj+<37WW1)1?$0!}(HlEL)03 zv88AWs1rof&I8MrIOVI+h6fI;+(P?ZcTEv#3#cU}$ zoh?OYu%&1TTZ+zPqv$LGiq0mW=o|uymJ(2OE&)Z$2q;=kK+y^Uiq0dT=zIc-RuWKj z0Rcs;2q?OcfTGm|6kS9>(ZvK5T|z+78Ul*e5>Rw00Y&Qwp`v*af3*V=Z|5FqN9Rk? zgw*4#NX&ehqN^f-{kU&R(bb$UMc1&U=vuZEt!GQob!;iRo-IW;u%+lmwiMmOmZF>4 zD7uA!qFV_lx{ZLM+X*PTgMgwt2`IXYfTFtzD7uG$qI(G_x{rXO`w1v|fPkV02`GAq zfTD*9DB3_k(IW&DJxV~)V+0gEPC(HUgiz5H5&u00B);F^Tq#9)HlB>c%$F(J6bbCd z#Z!u&;e082mMulkv8CvFwiLa?7J2k(l{1MPEk(`|Ac$igs|m6n(>% zqHoz!^c`D@zGq9(4{Ry=ku60(v8Cu|wiNATqv#g`ihd=a=r;n2b`emtn}DL<2`Ku5 zfTBMMDEfC^|qu(Z2)~9VDRW5CKJATE(OM%+%MT zA_Nqr5kf`VBmOB4Nc=+gmCfi^Qgpf97Wrv0^JR)+X@UK96)8m-oG(Sy*isZ{OHp;U z6lJodD2pvc*=#9Fu%#%;mZBUsigF1kszE?eO#+H)5l~c{fTB7C6xAi5s2%}DhY?Uz zpMatU1QazSpr{c6MU4q4$|Int2?0fi6HwHYfTCsu6g4MsThxMpq9X{Qq9Dz`)d7hY zxUarP)6>F7`m5}=sAXEre3_y)X@UK9Cn-g3IbVv}v85=VEky-vDJo=3QG2!&bznUfTCUm6!j*cs1E@}eF-S)M?g`3 z0*VF@P&AN$qCo@{9Zf*dU;>JU5KuIffTCdp6b&bYijGY4e{w+Lt=;zyMO#Zzjy=*J zkrp#wrf5`JV1HdsO3`S}m!dIjDH_X`qH$~~I*u(x$FrqqJX?xRU`x@7Y$-a4jiLzz z6rD^!(J2HJ6%kN0k$|FN0*WRPP&AonJ-hcFfFjZZYibc zG|rczMQkZr%$B0l*-~@{TZ)#jrRYqy6rIJEqO;jjbPgLuO9?1Cmw=*W1QabNplAgF zMduMvbUpz^D+wsNfPkV^1QcCJK+$RfiY_9c=wbqjE+L?34FN@K2`IXhfTDE-6kSF@ z(d7gbT|o#Hm8ba&9gz6X_Caic6m7BFqASy4=F1dan-*NzQi|4dz7$=@mZIy~Qgj1b zif&{}(M@bAx|uCSx3Hz?R<;z~#zxWY1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?lg2 z1Qb0$K+%H)6g@;h(Zd83Z6KiN5dw-HC7|dr0*W3dpy&w#ik>8(=qUnIRQmq5K#0b0Y%#hp`vHf{Iu3i(RzEN|Ev@p zvhV--DlKNdOwqS#LDRNU^d09*(f4dA`hhJ)KeDChC$<#*%$A~^Y$^JMEk(bwrRX;{ zigpoDw3~pU-w7!CgMgwx2`KuDfTF(%DB43n(Ov?I_7PC@4*^B{2`D;1K+(Sh6dfd> z=nw%#?mLjLbyuVNin_ZQux~q!5KxpxK#@;CQIvq9fDkI$k>(F}K;jeaw&)uvI%p%^ zkC`u16!!!B>n2mTMb$Z9iZaRfTBhO6g4KGD35@mCIl26PC!vp0*aauP}H1& zq80=c9YH`*O9F~o5m0m_Ayky%`xiSP@rCy7Le>26k^VV$C#kg`Ghe1C-w*7sD@`dX z;Cv}6WJ^(dwiI<>OHoI*6m?=tQD?Rkbzw_USGE*&W22}$0Yyg08tVu4*WIQRjpKYNI*u(x$FrqqJX?xR zU`x@7Y$-a4EkzU9Qgkv~icVppsEB}~i3AiC6HqjXfTGC+6ip$ZsDyx`sRR^FBcNzH z0Yx(iD4Iz?(WwL!%_5*^HUUL*2q-EgplB`uMe_(KnomGc839G*giz6F-#@IQQ*@i% z6&fQ&>+BQR3;dY*GDVC1!2Y`Al%mr)Uy9CPOVJXx6rIVIqO;gibT(Ux&S6W@QnnPG z%a)>LY!odgplAgFMduMvbUpz^D+wsNfPkV^1QcCJK+$RfiY_9c=wbqjE+L?34FN@K z2`IXhfTDE-6kSF@(d7gbT|q$6l>`)BML^Njgiz6GzCY0ciAU|WXpt2CWu&h0W9G{g zUGE3>*KMa1-N5-$bR%1eZemN(&1@;Ug)K$5vZd%YwiMmYmZCe@QgkO9MRyTUbTGP6s5u&c4_21u5ELw?*IhG4o}Le((eP>;6-Ue&l>9`iU(?KeMH1CtHes zVN21kY$^JUEk(Q7QnZ^bMZdFA^alY&e-cpi7Xd|o6Hv5=fTFzw6zwCR=pO=#_7hNa zfPkWZ2`D;9K+z!rioB>EwxcLQKv5b2MLq#VQ38qr0*cZJD2fqKltBm;edqh_9gui; z`*ij9QgnvhyRH_EnJ-h66%Fj4i%2QT=6oqiu%#%;mZBWC6y>s|s0Le#YOqD5^(5(P0D>)hD2+0Rcq~2`FkrKv81?it-33YC=HK;RF;lC7`Go0Y%LT zC~84K(Gdg`wIraZ6#+#@5>V8dfTA`86tyLUimFHbMGi>(fIYa+jE0Z&m)b|PcF~ym zGDYp9!PR}Gr~~IqQAf5Ebz)0VXSNh|VM|e0wiI<^OHp^W6dlEuq8@A%^(3IE7Xd}R z2`K7AKv7=;iuw^y)SrN&0R$8cB%o*z0Yyg>P&Al;q9Ftn4JDvx7y(7Y2`CytK+#A7 zijE0HaW?un0PKr*m+oDC$nE5hAOQM1Ob4MvfXL7z2oyC@-v)NK~4qJ+rvZd%; zwiGR6OVM(+6s=%O(RpkXolii~N&<>5AfRX!0Yw)QP_&wWqKgP9x|o2XO9&`hLqO45 z0*WprplBTdMVAp!bU6V_cO5m0nB0Y%pkP;@N;Me7NnqSK@PPzNObmOaux zLyB&-ZxgvL8Z%#}=%#33|6Eo|(aoGMMYph}=vKBA-Nu%p+u2fd2V08nWJ}RqY$>{% zEk*aRQFJc>MfVX}MdR$Q_V>}4`7%X6M+5uk`cjH^ za=sM(!j__6*;4cyTZ(qErD!)>ihgHH(I0Fn`jah1f3Z>YHvvU^2q@Z1K+!$|ivA&> zXg>i(2M8$omw=*!1QZ=2pvVjKupLDa0*cZIDDnv?iV{#15Kxp(Kv9fsak;6|?biaK>%M4=X%M>Mp!2Y?%l%gEYm!e#@6xCo$QBAfK z)nZFgZMGEEVM|e6wiMN4OVMF$6xAo7r~v^*4GAb}L_kqv0*dkoC~87L(cuIXH6@^^ z839Gj2`FkoK+zEd6tyIvs1*T4M-oufnt-A<1QfL;pr{=IMfn626%ay2*?~XF0g2bM z@4HR};Uj(DZkP&#nE5hAor1vrxzLoN&YUkrUD#68l`Tcx*izJ;Ek#GMrKks6ih8o8 zs25v`db3f~hk&BK1Qhinpr}6qMFR*Z8c0CVAOebxCZK3A0YyUyC>lyY(J%svh7(XU zf`Fot1QZ=ZK+&-T6pbRFXfy#uV+bf3OF+>$La3-i;NR(h#J{%NqK;BjWVc1f1u^qw zicSmy`{!m;icaEuDVo5RqLbNDbP8LFir7*#ku62VY$=+=mZHgQDVoAYQ3(M>Qwb=V zMnKVY0*Yo3P&AW(qEiVdnngg-Yyyhr5KvS~K+#+RislheG@pQ?G6IUq2`E}XK+!@1 zicTY-Xb}NLiwP(?oe(M-ANapIAn_u*D|CVs&9>X3GlH1;GDT+xf&FvEDMjaSz7#EG zOVPP(DO$#sqUCHUTEUj0^Vm{!K3j@bvZd$(Hi}jeP;?;yMXL!Yx`=?HiwP*Ygn*(o z1Qe|$py*Npiq;WObQu9fmlIHQ1p!4@5>Rv%0Yz66P;?CeMb{Egw4Q*X>j)^io`9ko z2%(}g1HYpK5+835%g&ObwRT%{V-Pc6rs&onuz&74rRX-!m!jL*QgjDfitc1f(OqmQ zx|=OU_pqhtUbYn7$Cje|*(iE|fT9NpD0+y1qK646+CV_jBLoyZNY0*d}2 zplCk#Bg9H>EBB01i*TZ%cMF=QLBcRA9peRZ}Q9wXZIsrv70*W#SD5^$4 zQJjFH>I4*J5>S*yKv6a!RJ1ej(@%Da?CY-4U!>?3yQ`f@kC`u1R3kk&qDYEra=sMR zVoOnNwiMN2OHp066xCx((P3;Us?V0925c#6$VO2k0*V?FP?SeNQ4<1+4kw_fDFH>z z2q3(Lw@> zP9vab5dlSu2`D<9fTA-9C|W{5(V2u$(Mjq4HU}jBuzj!N1S#roAJNWAkC`u1bZ&aE zuSANLalRBSXG_rvwiKPmmZJ07QnZpSMHjH8Xcb$EE@Vs5YBq{4BB1DE0*WpnplA&N zMQaHtx|D#Tbp#Y$MnKW!1QcCCK+%;16kSC?(bWVLT|+?8wFDHcC!pv$0*bCDpy&ny zif$yJ=q3V+ZYG3^&Pn$hO?8TP+ilTODQcE_z?L2}U#94e^q}{2DY}#MrRXlU6y431 zqI=jky+C)InGXxYpOF+?c1Qb0_K+y{X6un45(PjdQULv6AWde#`A%u!< zOZTTZAn|AI=I3@P>Sp8B^qBcFMQ@}BD`ra3o18C2Z?UE5ZMGD>!WIL0YyI(P_&Z}D%z6n-|c|JKeUf%uS-!+ zd)WU=ddz&8qTT7i>$9Zjcg~lhKiE?ACtHgCVoTBAY$@8qmZH6EDcZ-DqJP*@w4aTl z0|XTPOF+><0*Ve1P~^q*upLDa0*cZIDDnv?iV{#15Kxp(Kv9frluA(@ z&X=OPY$>Y8mZHPhQdFNUMGe?e)Q~Mjjo4Dum@P$lY!o#ipy+S{ikcEo)Qo_l<^&YA zAfV_70*YD^P}GWmq9X|?YE3{<8v=^j5>V8RfTDZ?iV6rQDkPw&Jpn}>2q@}EKv5?G ziaHZQMKxo7X9pzyi~aCWtyuU-KVgsbyToGV%M=|I3yz;BMLjrQih8o8s25v`db6dd z4_k`*vZbgWTZ;O#rDyCwrqX{S)OhC~P0*ZzbP&AByqTvJ-jUb?CBmqUo z5Kwe10Y#$-C>l*b(HH`X#u898j)0=$2q-$9fTHmP6rDgo(TM~UokR!~b&L5+9FX`I zZbrLH(Oq_1G$9rgBOVRmkDO$;vq6^qkw2Cc77qX>jHCu`{gjiNOK6s;wo z=u!fT))7#2839F?6Hs&o0Yz65P;?amMOPD0bPWMT*Ah^)o`9n32q?OqfT9}+D7uk= zqMHaPx|x8YTL>t+m4Kq#2%(~7F+XFWQ*@J?(dAOK+3srJ9*dbTQ*?JMXthX+?%{kX zx|c0Q_pznuezp`nz?Py1*;4cnTZ$fLOVI|l6g|R5(W3+uJw`y$;{+5vK|s-y1Qb0* zK+)3#6m2A+XcGZN&k#`bECEH&5m59z0YxtmQ1l`JMVkpIdWnFdmkB6(g@B@02`GAv zfTAsgP|=++f20Ev|K5H!_AV)EWp}k-kHyTFDSA5=l%6g{?{K~py~~!O_t;YOK3j^m zvZd$)wiJEHmZFc?QnZaNMIWyQna5fMF-eY z^e!zT2q?-Rpr{%FMR5X(suNI@ zNkCB+0Y%va6eS2KN)k|%LqJh30YxOeqIM*@mE5m3~b zfTAu06m=z_s2d?vR42pFJKHHLv2T*Cn-Mf3_42U`x?JwiFFwOVQD6DH_a1(GUWPh7wRTjDVuy1Qd-RplBokMaK|O zbSwcyqX;M(O+e8Y0*b~GP&AH!qT>iCI-Y={@dOl|KtR!n1QeY_K+yyOicTh==oCVz zs7HoB)d7jyzYrYlDMf4Twx}p0X1+|(8%1*nC@LkOXf6Ro^9U%KPe4%_0Y&8m6fGd2XdwYbrx8%Jh=8KS z1QeZ4K+zcl6fGg3=u85N&LW`bYyyhTA)sg}0Y&E$P_&E?Dk{$K?{z@p8|?dwCP~rf zc3ZSOBWAu#(aMbA%@tB~0q0B6Dz+3|$d;njY$>{kEkzfzrRWm26s=)P(OR|?UCKt$ zIs%F=BcSMV0*bC6py)~himoD{=xPFrt|6f4S^|pJ6Hs&=0Y%pnP;>(UMK=;qbQ1wZ zHxp2F3jsy95>Rv-0Y$eHP;>_YMRyWHMdxMszdIoDjS&aud?|X%NZpkYGhe3YzKo#8 zN-4UZ^QGtkwiG?cmZFE)QuHueiZ-yN=n=LQJ<67%$JkQzI2%Pz5K#0a0Yy&{Q1mnb zMH>ky+C)InGXxYpOF+?c1Qb0_K+y{X6un45(PjdQULv6AWde#`A)x400*YQEplAyL zMXwW3^acS%ZxTX9_hk589gz4)H>3ATQDggv_EtvBe3_#6GJ+FUNzwb9FGX9~QuF~^ ziaumZ(MN14+QycmkJ(c630sOjWlPa#Y!rP?K+zWj6n#lR(RKogz9OLLYXXXP5K#0D z0Y%>uQ1l%EMc)%p^aBA!KN3*%69Gj(6Hv61fTCXrDEgIvqTdK8+C@OoZUTyaCxnXL z$?(r|K-`UwgY&KwZL&{f|B(?hU#4hJMsUMwDcZ~VQnZgPMgOp+Xg^zu4zQ)@U$zt- zWJ}Q@wiJ2Q^tfG$B5V|;5m4k4P!uJg=>HIRAJ9?N|JwHVWX~{UQf3mmv`~~LB%y=! z-aCkbh5(^MAPESH0s>YP6%_<5h`nPk*s-IcVsF?RDmDbMyua`4`%2>fyk|XUJ?pIX zu$J!JSF$HV=EG!?kPsoDs0sl^Q38sp5>S*%Kv9f3CZMPq0Y%jbD5^m~QB4AhY7qiOzg6{jIUun!?C$5F6xFa%J2h&)Oi{hm$QKt% zQGL#rq6Ta!YRHzN9JUlSVoOnDwiGpCOHos{6dlc$qGQ-7YDPd&a{`K55Kz>TfTC6e z6dg-IQELK<+7M8bOF&T`0Y&))6tyLws2u@C?FlIAKtNGP0*X2jP}G@#qAmm!btRza zI0A~g5duX=rTVe;PEmh*KwURA_(*@5jqa&Y^JR*9r$$;`EJb}dUyAy&rKlfUiu$vq zXaHM^2C}7S5L=1{v!!SVTZ)FVQ8bKzqTvJ-jUb?CBmqUE2q+p&K+zZiipCO9G>(9x z@dOl2AfV`Y0*WRQP;>$TMJEzaG>L$s$pjRgL_pEW1QZnzP&9>rqC!HTsAsA_$^nVZ zu)CjLQnbsxg9}ehjhZi0G$S>#XoD2Z>asrA@C!pvI z0*Y1;P_&YOqE!SGok>8^Y66PZ5Ky$1fTFVqfuiZD{^brxY@dDBu}F#@x4&$3c52jo znWFPkBM)3AMe8_UiY{PF(S>X&TF;iEi`Y_hF zpy){gik>2%=xG9qb`enY3;{*Y5>WIU0Y%RfQ1k);MK2Oi^b!F@y9p?InSi2K2q=1$ zfTBHwK+zqke&bC}(RlmZ^_^1mp?!?@T58mMnW8sSBYihZ(OaA^MQ^jE=pD8cy~~!O z_t;YOK3j@DU`x@5Y$^JPEkz%*QM8YMqE84Y`jmj8&j={`oPeS)2q^lJfTFJmDEgX! zqHhQ&`j&vA?+7T`Pe9T41Qh*1K+%r`6dfR-=qCb-ekP#k7XpfYC7|dxLZIl4RDYHO z5}Raj_Da!N_NCc_sZsM~ivCEAoV!(uj&Qyd{mGW1zt~drH(QGSVM~!0(?{-76k%P2`EY>peRN_Q5pe7=>!yI5Kxp!KvA54q67g&Sp*bi z6Hru*fTHRI6xAT0s3rkLwFoGxO+Zl{0*a0z1d0x&`gb@Wu_N}l=&%$Gwox}0HD9Kv zVJ!0MRZ^70`BKz~Ek%vlQq+VkMNQdKbTnIvj$untGqw~pXG>8FHi}vjP}GWmqGJgt zYE3{<8v=@Q2`I`VpeUb!qP7GSwIiUYJpn}>2q@}EKv5?GiaHZe)P;bet^^bvM?g_G z0*bm5P}GBfqMn36QT>?zs{<0-Vs}3cV!=oHr`hNgi<&P})GrpPu}zBlbG{S}U`x?J zwiFFwOVMDq6b)fZ(NMM&4P#5uaJCeUV54Xx0Y#$-C>l*b(HH`X#u898j)0=^1Qbmm zpy+r4iY5|JbOHfIClXLJiGZTX1QeY_K+(wr6crFqG=+eoLIR4W5>PaafTHPyKvAEV z-_-$$*-t78_m!fXZ4||#=F1e#jzuPIm!dhGFGX|NQZ$b(Mf2HGw16!|#cU~B$d;l- zY$+;XOHnBsMP&pOEheC72?0f?5Ky#~fTCpt6rD;y(P;z}EhnJpbOMUbAfRXk0Yxhb zC|X58(U}AkttOyo4FN@K2`D;?fTFVrC_0CLqH_s>qM0#&r2`TxvAdsHQuMk#NIEYT zHD9La!dPV6^-{E+^QGt_wiI2=mZD48QnZ0BMVGRr=rXnxUCx%Gjch5}#75B-1Qcy1 zplAyLMOz6dx{`pRs|YB%nt-Bf2q@Y{K+&}X6m2J<=sE(5t|y@A1_Fw1B%tUf0*Y=X zpy(C?if$#K=r#h1ZYQAV4nm-4UCe*h0g3%$pJ=>5igN5D{X1h(^JR+eiABD;QHt*6 zd?~t*Ek*aUrRV{+6g|k6qKDX0^e|hB9$`z-PPP<1%0|&+1Qb0^K+zKf6g^2m(NhEz zJxxH-E&__4A)x440*am^py+u5ie4a~=tTmGULv4qHvvU26HxRD0Y$G8P_&1DqSpv0 zdYyoxHwb~E9Wg)sCa0*X{q6m`rRcfj2W+vZ`7%ZC#3HS4k)n4wUy9yiOVRsmDf)md zMIW-I=p(iieax1keQYWEge^s%vQhLI0Y#q^Q1k@>MPCw7^c4X`UlUOD4FN^p5>WIV z0Y&=>DEgj&q8|t-`jLR50|XTPL_pEc1Qh*3K+&%R6#Yg((Ln-=ekY*l5Ft?XR?Hvc zfW&Irhh=X|QFVLwb~qL_U#94yeKv5k6ijE?ns4f9T^#~}cPY4tpiTRrxkk}{oPV7%9y4*c4+#oG# zzD!Z$w8%quNKq5cm!hU@DLR@hMaQtEs2N*|nzN;-1zU<*vZbgMTZ)clqo_3jMQsQu z$|ayEkAR|l0*cxaP}GiqqV@z7bs(UqBLPL72q@}IKv5S0ind9FW+%_SM)%X~9SO)zqCuQ5 zMT6N=G=wchL)lU^j4egO*-|uuEkz^QQZ$M!MWfj$8bd(QSOSX15l}RqfT9Tm6dg}M z(L@4@P9UJ@L;{K?5l}RlfTEKKC_0&dq5=YnrVvn6NI=n40*a;)P&A!@q9Ou{W)M&` zlMpECpXN8+;S}w(zYH=!iq3b>3(rc6nlDo{FD=sl9x0m7`BJoiEk(s_DO$*uqD5>e zDq%}eDO-xl*iy8ZEk#S%C_06JqNM~BEhC`lR04`lBcNzG0Y#@1P;>?XMJos>T1i0B zDguhmB%o+D0Yz&FC|XNE(OCo(olQW|IRq4)OF+?i1QeZ5K+!rvplD8-KgR)yRkx4P z=1S30dvtw4TGV`*qKnfa=ietqmvFumZD32$rEDp>j4ef%v!!SwTZ%TZrRWN_6m4cp z(H1s}wh~ZuB>_cO5m0nB0Y%pkP_&JJqH75#+D<^xbp#Y$Pe9QP1Qgv!K+#PE6x~cf z(JcfN-AX{wZ3GnEPC(He1Qgv#K+#Eo#0@(fetUS`SOn2b?cO zAF`$BBeoQM%$A~kY$^JLEk&QQrRX!Z6n)N?qA%De`jUX6uLvmmnt-Bj2q^lNfTHgR zDB4dz(f0%t{Xjs`j|3DQAfV_c0*Zbnpy(F@ihd=a=r;n24iZrGI{`(92q-#CK+zur z6dfT1ir!80yE!1Suk2g%-;<)hjntoMQS)Vry!6OPJEbU;u8-uUD1|LWK3j^yY$=Mc zrKk#9ilS^Os>+t4RJIhw*eFUPpeUVyq6`9xG6^V(6Ht^OpeT!gqHF?+su56Boq(bm z1QgXIpr{rBMYRbiszX50Q3Mp#C7`Gt0Y&u*C~81JQ9}ZXatMKqrKkm4idwRzs1;j^j%7zMUx09noK~^Ndy#~Oh8cq0Yy^?C@LhNXet3k(+DVgW=qi$wiKPhmZGI>DO$!x(WwL!okl>>asrA@C!pvI0*Y1;P_&YOqE!SG zok>8^Y66PZ5Ky$1fTFVqC_0;fqH_o+I+uW=^9U$9pMauu1QcCBK+%N+6s;!&isq;L z;~bFK7<)jyK#Hc@xF|hpzD&`j>5;|HNYQ1SFGZKLrD!8tiZ-#O=nA$JZDvc+7Pb^^ zWlPbOY$>{mjiRdwD7uD#qHP2eT}wdGb^?m7BcSMd0*Y=Rpy);dif$sH=wDUkE7rm4Kq(2q-#8K+*366dfX<=r93Ae-Kb~gn*(y z2`KuDfTF(%fuax6{bL-E*bDYG{ST$+7rQU|Cp~JuOp%`v8Ms@D!WsYmNI$}sqAF}D zin67sDqD(D*-{i^OHmqIiqhFql)*+(CILlp0*Vp@6lD=mlubZUH3EvN6HruxfTEfN z6xAZ2s5SvbbqFXrih!cJ1QgXHpr}3pMGXijYDhp)4gp1t2qDH*}XXw}^F!c8-x=F1c{&xl;`iWIfreBBqdWJ^&iwiF%9mZH{dDQd%(qFlBV z<*}tGpDjgg*(hp9Kv8=FiaHQb)RBOqP6QNnCZMPb0YzO2C_0XSqHY8fbtj;x2LVMr z2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lfv6djY{-|c|JS{R&WQdGy@y$#NY znlDo{JR|bP9w{2Z`BF5JEk&c)QZ$+^MPt}fG?pzzhi9KRp(_bV-1MR+OLq^nmnWBvuk%Bj+XcOm4(G_ed+RT=sEo>>;%9f%l z*-~^BTZ*n`OVKrKDcZ(H(X|8=Z6~1UIs%HWC!pvC0*Y=Vpy(z7if$&L=oSKsZY7}T zHUf%nC!pvK0*dY=py)0FigplCbTH~8Wg$RM7k2Czldrr|VyD!=&MSt6uW>Yew=F1dS$&BQGAVpEm zm!hg{DN1EaQH(7`X>2J8ATZ%H-QWR%PQG$)4ECPzM2`H*YKv8u9ifRy0RFiA*M^bbw=Sxv*wiLBtOHnRcit^Y} zl+Tu;wrnYC$Cje@Y$@u%Mo~usiaHTc)R};yE(8>HC7|dy0*bm3P}H4(q8laQ(NIF5s70o~)d7jEw!iDx zQi^^tQo}N%=F1d~%8Wd^Pl`r!z7&mNOVL=i6pdp`(Rj8LO<+sW@oXuY$d;lL*iv*N z8%2`{D4I+_(MbdpolHPc0Rcr*2q-EfplB)qMbiiCKK+!A$ie?i~ zG>3qqxdar=BcNzL0YwW4C@LnPXdxj`G$Pag)B%aTXFon|q!cxvFoz9k`GuTqJf{mh;1Qe|zpy*5jidGX) zw1$A9wFDHMML^Nn1QeY^K+(Ab6rD#v(fI@vts|i50s@LIB%o+L0Yw)PP;@Z?MVAmz zw1I%4O9?2tj1VX)&Gef)AhF?gUsNVVhwU#LU7i^=U#4htW@PXeQnZEhrD!W#imqf! z(N%0Ix|%IT*RZ8%8(WI5WlPa^wiI2*M$z>I6x~2T(TxNY-9$jq%>)$PLO{{21Qgvy zK+)|46x~5U(VYYo-9py)mVitZ<%=m7$X9weaXAp(jXCIpH$ zW%>&okXSSOtm73@bgJDKJ(3wUU#95s%*gt$r05CGm!c=xQuGvCik@am(JrXG_rwY!tmnK+#JC6zwLU=w$+mULm09RRW6k5K#0Q0Y$G9Q1k`?MSBS- zdXs>nw+JYDn}DKs2q=1&fTH&ZD0-iOq7Mit`jCL4j|eFGm=Gv>G}FJ=0g1JAw#g?LMwiH!kqo_IoMKuU0s!2dmEdq*a z6Hru#fTE)aD5^_9Q9S~R>Jw1ZfPkWg1Qg{EP}GQkqQ(RiH6fs=DFH=C6Hs&v0Y%LS zC~8hXQ42z#C>r;BIUup^_E4y5Jorfe4kOhv9yMR4s7*Xl_=6PXa=sMhv85=VEk$kF zQq+zuMeW&A)PXHU9obUUi7iE)*(mBlKv7o$ijE_os2c%A-3ch_K|oPY0*ZPOP}G}% zqCNx^^(COF9|1-E2`CysK+!+~iUtu-G?;**Ap{f+C7@^+0Y$?JC>lWs6dfD)&vHOw zr`XrgT1(MQHb%yy=F1d~jYn=gAVuRiUy8=FrDy_MijHSX(L}Zsoxql&6WLNUi7iEw z*-~^88$~A*P*gxb(G&uT3JEBhNC!pve0*Wpspy(0;iZ&2XbSVKv zml05OIRQl*2`Jh`2ox=e``N!ZMH}qvXs1ZgV-Yv5h)2zrDY`NqY4@8HUB&rQbTwOw zu3<~jHntR9%a)?;Y$>{qEk)O}rRWB>6y3;1(M<#t-Aq8yEd&(ZN5JZip7(NporvfriXY0j6TU2G|OhAlMSMPJ1uj~|wzuQ^|ezF|wzw`?i;jx9y|*;4d9TZ(>QOVN*PDLTNG zqMz6(`k8>DUkE7rm4Kq(2q-#8K+*366dfX<=r93Ae-Kb~gn*(y2`KuDfTF(%DEfzh zA}^s2+ffuEpeTiaBAv_eE6`QS)Vr z(i4%$pHh^;`BIe0mZCUYiV|!o%3@1VHd~6Sv8AXwTZ(G1rKlzwMYRYhs!c#q9RiAu zBA}=)0Y&u)D5_6DQ3C>s8WK>HLqJg@0*V?FP}GEgqNW5C9Zf*dF$5GfBcP}`0Yxnc zC~8SSQ7Zz9jwJ+&VhO*c0}?ySzK)ib2tLw(+1|aiPDIU@DaubohW;%@Z8=|x+Oegm zJzI)8u%)OYTZ%fdrKmGoin_3+s4H8Fj$@;!8v#Y#2`K78Kv7Quih2=H)SG~!J_Ho? zC7`Gu0Y&`@C>lUO(Le%<1`$v+n1G@o1QZP=plBEYMZ*aw8bLtONCJvR5l}Rm5Gcw` z_zNA7Sccsf;m$<@bR24MHAUlbOKw7PGn2bB(@YyW=qjY zY$-aKEky-vDVoAYQ6T|EQwb=VMnKVY0*Ze@&8 zrzE20%M_iKh`gO5Mawx~icV)s(HU$hTEUj0m24?m#g?Ko*;2HcEk$eCQnZ$hqO%An zI-7u^a|kFpmw=-42q-$AfTDE-6kR|-(S-yQttX)9A_9soCZOmN0*W>eP;@B)MVAp! zbU6V<8wn`dL_pCM1Qcy1plAyrP_!)J|LK6l=Gy13PnDvZ?7nDgB5J-&(KU%kefQ%a zlJ`a1IA4mcWlPa^wiI2*mZIy~Qgj1bif&{}(M@bAx|uCSx3E!kD*;8f5m0nH0Y!HZ zP;@5&MRyTUw1a@6y9p?|hk&Ac2`IXcfTH^eD0+Z^q6Y~mdWe9chY2Wpgn*)*1Qb0= zK+$6a6g^Hr(G!F~(Nzh*j{_1r#_oQumZAmrG1`-fsQEHQ&mnw+JYD zn}DKs2q=1&fTH&ZD0-iOq7Mit`jCL4j|eFGn1G^v1QdNjK+&fJ6n#cO(dPsdeL)Bm zJ)Q8+aX@14*oS4iq-cjdy8bc|HD9La+eGB%R4Mw7^QCA%TZ+DCOVJN(Df*EuMF-eY z^b=c(er8M2FKj9Lm5rj`2q-#8K+*366dfX<=r93Ae-Kb~gn*(y2`KuDfTF(%DEfzh zA}>oHwxcLSKv4<-MLq#VVFHRG1Qb;vpeRZ}QB?wpQVA%E5duYDC;V3&kXW&s;cuiU z)kvjfMa`Efif2WBOp~Gn=Sxu*TZ*#TQdEsCMb+6-RD&%=HQ7>Bi!DX9*-})8jiRFn zD5^_9Q9S~R>Jw1ZfPkWg1Qg{EP}GQkqQ(RiH6fs=DFH=C6Hs&v0Y%LSC~8hXQ40c! zS`tvyih!bH2`Fk!Kv5e4igF2oqKquRdb(5et$o%pGb{K={|37+%FBwHFH_V$E7BoT ziaKz<6m?`vQ75((b!JOZ7q%32WlPa&% zjU}LH93fEDHp@TJ0f{|h4~5!EQ3rc;Jw7XHzD&^xS&`EcQgkBcOVK2@6isGJ(MfD6 zI+-m+1#Bsr!j_^!wiHceOVKnoil!4#R76103<8Q~5>PaYfTGz16wM)^Xf6Ro^9U%K zPe9QE0*Zm!g$yDO$yrqBGf2w3;nNYuHk>mMukRv8Cv2 zwiKPiM$x$h6rD#v(fI@vts|i50s@LIB%o+L0Yw)PP;@Z?MVAmzw1I%4O9?2tjDVuc z2`Jh~K+z@wimo7_XfpvtTL>uHNP^1pOIV!iC{=X5E$(#F+UQS)Vr zwr546HKgb|&X=O=*-~@^TZ(REOVLeiDY}_0MYph}=vKBA-Nu%p+u10(gMgwt2`IXY zfTA4)6x~fg(LDqd-Ah2xeFPNUPe9QF1Qb0;K+!`46g^Bp(IW&D?IfV+Q38q{BcSMU z0*am>py){gik>2%=xIWrXj_(ltOFAJ);{ZatrV@d`=VW0QS)Vrp3jO5uO&qROVO`vDf*2qMF-hZ^gA0xhX^P-OhC~e1QZ=1py*EmivA*?=x+jw{vn{q%hreO zC<+l!ltMs}Pe4(afT9QiMO6qWiV{#%m4KpD0*Yb;6r~YRlukfV1|d-NU6%i#0}|U~ z_eJ}qsHMF}%gm0NFH@AA9eKB|6jkGVDXPwvq8e-|s>zn3T5Kt*&6c7%Y$-a5Ek$+N zQdEzPqWT0BH6Wm1QazQpr|ncMNJ4OYDz%S(F7D7LqJh80*aawP}G8eqLu^{ zwIZPCSOSV#6HwHKfTCOiit-33$|sldR(O3eC z#t~37o`9kW1QZ=l2o!b5_WL;?u~r7BqZBo?`=W{2QS)VrCTB;A+`mYi{5sl6oG(Qu zv!$qjEk#q1-(~VoT8sHi~8vP&A8xqS*u#%^{#@E&)aJ2q>CQ zK+ysMii!y+T1Y_AA_9s^2q-Egps0+1qQwLhEg_)j6atEt5>T{^fTB|gC_0URqUD4@ z(TUmqc@9Xd*#6%2BqT|BfTD{CD7u({qDu%U+CV_jr34gRMnKW! z1Qcx~plA~TMOP3|w3&dSEd&&8C7|d^0*bC8py+A>imoA`Xd59=v?ANz|49}|` zzbx)~wd3z+d0xGEqw1cQ6Q5br^P0wQukCrwUq=S8Qnc^R(xzv&zl#&qPOQQjDOtM^UC5!5AeLD@wtOMZ+U#j5YJl~ z|9zO}t%-LZ>3QeGSC96*b@3O*dfr9x_yo_pG(LW!=WU8_InndB#y^?tdDq076?oot z@%e?GcT@bHX`Xjm{BV)y-4*XS%k%Dyubtz055`}b=XpEhS;e0BMEv+gp0_K0WvS;q zAOCEz=k1QSaQ`I6o_O)8p0_uC-*V4;Cw}A%&-)x+j#oR! z^Y+J2IM4GA#IIiGdB4WLxX|+s#amtMd4DDrZE$b@P~w5h+zk*){I${D0-;3T&F&@$ zCC=UIZi7(b)vMf%5K7e8=5B>hV$ybZGlUY`u6MUXC}IDaebZ3F{yFmIp@jW=(#M7p z_74K*g%b8Jy0#A`?4RW997@=~sn{))uzwVj?iLCq?B|TE3nlCaMO+k0*mwG0 z8cNu=YHtc9?0apuh7$J8lGlV1_T6sRg%bAdN;icP_WdTeg%b7+19ycI_BX!o4JGWa z>^>Mu*x$L_8A{k+ntLLYu)p=RE0nOmw(@)^VSn#ncPL?BINlRV*jN7ch7$Irn|DG9 z``r5np@e<%bYCc8pZ)qgl(0`u;I$DjK{3Ht!zKqz640Dlc7>|OYwP{Qtm{|tFq z_qaba;p>7wa@m_g?#68Aio@al3vJ!dEaX*d=RQCQb;w+Axtf#bg*s}yGYhc?&J=hl`7Rj zX=%X=gxri~cz#u0J}oUHEj_KXyKSo0`qxXPx|gbSsWHt+@JiBjk#5>Wrt2b;&#kz~ z3|*vND$|`5skk2T40rA9H7Al!L_9A`zZ1QZ>^7mEb+{7E>STqotMsb9u}>X)jn&#$ zx_b58g;YQH%#eFKX;y&*Fye7|ZZ{jvy&pO@eEXYh=sCzB$R;cIx zv-cS84VV1C{m-OV{#AKj>J<9kbazTh=tyRU7jnPc%No=+ZE{Nrb7zz;%q=aMmRnL# zI<2T+VM%dW(X_In>ABNNmMttRwlJ+|`r?wJ(n`;>mv=ASC3j)T?D@0HW-lr7a%UCK zFUl>PSF|*@&Aj4ih4XStXBCzd<(3pJC@L*1%`IwMP+GQl`t0J|vf|=-(`FUUUQn7l zbK10m!jk#9`FREH3fkti%`eE$v)J0j)(eUk6tylYoI1O8eqNh)t?k)u+_V4ntlZfP zrp;SCy(o8n;j~$^7yLiJ8l}rhE59XX&dTjwGJWyv1;u@fONv^Tzb%%Ql_cLJ!CPch zN%0)_HZRQ`yRfii?tsM$3dXtL%gj;p7MB)`>D_U7hyRV6X-Q#Ok-fD%FSwy+EM71z zuYF#dX-1)7deMx+#q-Jv%9brGDs3~%gt?n*`s@W|Za6_>`}QwzS94n5;`#H77r5r| z0cN&cbdWrEZy!nO^xK6Zk!t_luSlqhKhwQ{Uni%^%t&?>_hgk}?jcdAMkLJ+@kk>( zxSpJC+_T$8YPgx*J<_Ogq*{F!a&=zb|Kz;L&`7nxc2aPbyNv7xZvKzX{l9&k+1+y^ z)$Fx!O@m{oQA&>cQ#hvoz=8pJgFHLtcg`DBFg19xWBc+aJM=AovSVkxWc$vv-khA* zK6qaLzIvH__rkM>6&Eke_lEbLSkQOGxVFJ%_v4ff<*%<3sa?hEZCn0&`&PP0UBR}T z(6Ribx+JgD;svF%XD%q3p5xFYUtM2aulxaAihF|JX8-cvN4~o<$(QfqUaX+No!zc& zL2wEA?v-)E04}Y!F0D_+CAhbMd$H+@=g(gjT#{b4J+HX8LZ|X8;NGC+mt6iz+S`j2 zn05W>(3`E|P2=7mI?eqCg6F!+44$ZTg*tI%-J3G`O!sEic^%3x%w0RKLR-CjyNYYo zxBQI!zPu{;+t3;2q0&9>|JMCXzoMy&XL|0=dBM!0f}#b}XBRFgm{+`DX7C$yH;{Yv z?%u4@Eu^c~zT(UK-F8LKa-S0xL8YJZ$-2FrFmafp1?|20*k7rhZ z%OAi^Q{jwT%l#&T^LWB;mgIetZrbuc7WsL3$!EAbFI};Gcg=V*zvAsv>E`aF3*#mU zB-zDxu6X0QH*N45+w!U_DCAdI$ghOK-Cn^d6*oJ#N`4=`CAdwxlwV)>*4EXnxDVq7 z>rioh0u0HwLB;K#UkN~^8@{8vA{8pR2Xt?$;QHCK?SkB~{0*hVjp*)s^sIK}Z$kHm z;KeH#a0_z-m*1$J-P^CYoNmQ!!utoiAJN6RbGTsVF?bWYSDSpoy(M^F`BieS%Qd@W z9OoV&=;b-l-5$weH*)gbPVnBQfBD(&7SJVDTmx=n_ZHIg%5O_|69liJ!iKvCaW9p; z@Z_`HZL71~djmaH{u^=bg7e*7sNI*91aFo6;GlPf6&ms@IFt*lP~hIny2~$}Ra{b5 z{*KLI<5~nadim{L{w~=4p-H}o-6lyv?yV6#QHemsO`czIo99>D=-eXt?#d=lcJHH; zN8aN3&Tnw3m2S|A+t0mny>0T{ql(}K-JefAQT`^(4{lw%nw9RB^L2*1RV&`W?x}$z z#^?0y(j~_plefvwu}9^3o!hq0Xd>ASm|Wx56Tk~0=A>Cn1#Ve9Gn9bG9bnKrAtdyK!NbL;tS=DUv) zT1_uq*lNbYoYpgQT90g-)7m{O?LN(2fz~tT7nPP4&May@uV}%{vRU2pTnZk7w6r(gd+8s+>n_gH}SiXZdg?q;xJW)Y5zrw6>{O{h^1S~7PKP?SX> z;^CZWw6}4^qq>U6a`^%9q!f4GtgBUV3kAx{-`OQm7Zm*aJuwd^D;`V2#vc8Q95A;0 zJ#0P?9V;FNRy_Kvc<|>QM#3lfQ(#xG+%XRvD<0ETdPv9P#)`*p{DH8Cbio@&5QE2V z|C=9*>Lb~T4{(xiR(mw62dK$6U+_n|{7uRq;qpHy{5i2lrE|;gReA8~-ks}hQ}Kw9 zKQZN;${&6vA6L3JUViz5#!7!QEB=60Jmf=9#RI-_6~UuMZ(!fPU2~e-AI9D#^K<&o zpIS71x_j(Bj*qRAe?Iw`xy66~r`3HbAl?1*eI}uIW@1fv zt$$X^g(0tZ7Z(ccgK{sF>z<5sZauus@ZN(*cvZ5Z!&CiO)$DNfP>oP6zjmlj=%`TL zP`yxtl*XYp_Bn_D_*FTDy`TQ6{A}MoDy{U(*XKM)zI{+y>6h<5AkC_@?Xx59^W@&8 z<*nkgC6;{8eL}C&FW+;Yeya4#_uS{;EB*34``k;#FW+;Ym#_58_u`e7UH-qXjqfG? z|Uj`o&Hu`fy3(fzjVcV@>LI@YnHd-F81qkEy|>gK~<&V5xO zd30Y(NFMv>I7-LyI=W9yB%eP=$3;4>&~c597wNcN#~tny4)%H;)$t8?Q``Pn$KTv< zz;?)erq+(N-0#JXO?0$RtJ&_a<0SXA?U_1W<8E5px9j+&djr`1MaN?uG}~QtEOB3& zvAsga2i+ei+t29u_ff%4s~a5qxi8$<^GEA=Uc+E-)Nzk{!`kyd)UjsMU^mfm@-e}l zt>d-s2C$dEQ^&7c2KzT1+q4e$aXOZ{8_HgOm5vYR2m3i4z4pP*&~bpfLG9(o>bS0R zu&>bZbqC6x|FMp>-3@R1XdO@P8SJ?_Ue`O=J9PZEZ?J#YF>gSyyX&}QP_S3)xN}Ib zU(hjSc(CI-4jLKk@j6~OI@nuu+&ebdpXhkhgkU$*amvJC&)4yW6N7z^j{7GE`>>8} z3xeHK$EAhAUaR9{4!XTPUeYl!q2q|n!Jee!rCWo&O~?1H3iekz=4=agYaM574|b`Jw_P9Xhjje;#$f-WW9M6f z-CxHuZVUGLI_|n7*stjr+Y#(qI*z(0*eB_D`F+9OuHy#}1p6Bu8$TTETpefa4EACj z?|3ZOkLdX86TuEW863Ml9UKShxbm4`U!dc&&jtGp9n)V7b{!qZ><)H;j+-eJks;d3|-qtbkXRzz*IN|SLPt$R$dlX?Wf3uFCy05(2{!z!~ z?vwJiJLtF|8tl__yw`nE)}H^Qj(@nX&f1Q;Z;!HLFZX3yI}X?JEcf+V+Z%M;?Y?kp z`&}Kg-B)mJH`H;W`%aHtB#+$FYem@NynD%tGu>5>9{Z_*r)4wzx%qc zJ^yJP>$$&0VY`Knd3KC=UQg{|I-a283>`~#T&d#)I&RkSMjh|f@kt$D(eZsdy4REG zzD#PzMml!ZalVc#b-dJ$?s{(0ahs0U>sZAe&s23^UbLgTJo{xw_b?`TEVaisZo7vW zUP`9>s|e~|o6=?T%L=EuV_8XXoW)b_L+~=MjeX4PwV7I4>a}qnrMI!z=HH*^PWI{c z*T^`EeXz2DX~YCx}YHa*D}w(5~quB*Ticx&3)OZ$bDI$(yN(K zQaIneQ13Cr+Z2|SmCT;HxXfMb|MZu8=;XA!FBR(q_t4~DzucQD`KyupzrCCvOnWHv zuV3~&`_;_-=ic=H$Ct}Zzj&&j3zaW#rMtXYF4*PS+knd(=bq*q_oR1s^N{#l4)}=KQkXhyA+M{a5+=CEWG1 zw~JlBEcYM3-<|Gh_uE_O4#{8Z+~sv;xFfI2j@Y(mKkr_ymy0#r(_EfizP-*$Z!WK@ z^D@9SesOtrPUV-&ao2A*FXWEAT;;DBw`)_Jo8Kv~W9PiKo!hp{ai3er%dhnRjvd?Q zg@RtsP3l6!D5V>3{*9=XrNc-foo4b#TYkG(7TRCLq&{cz1 z4f^NzzyBHfbFc9ufBkx4pM%x>Glrcpc*T%ihxU(h|9QI(?Mv)Bv@55{lqR#T4*j`z zQ8(KDG@!-XSen`HQdkqst{<<&u z8Ws&M88Us?Gl%w1asPSGxYzKEdkwAJYq&Bvcl_L;bBD|uJa5n!$#Z)hT$k79VAP*I zd>ydy@$g2 zUaKSTc{%obbY~41bnvnw`@Iew+`+wdywI*gd#1Q+4FeyyE}&b$WW8-G(;* zzj&SY`tk<18B)i+b<1C)yFKjp-)h!o{r;N|Z84<9;Fg2-2e*fNYs3eq4{>kPL@Rf_ zwgfLVYT&{8y&DhRQ|NxDi8l%lJ?cH)u36U~);{@Wjn(~bITRc8;s`HMvscVJXH}$X zRqw8jzu&r|ZC2ZJ8-My(Z0P0bkNQuPU-Fiw&bft@a zO?N`d@Y=)e<-(Ds?m7Nd_EID3Oi89_%vRM%uDc6QsT#e){YeamBlfAtlyLMl_ac5X z_X7U0)q300HQlrQyz1lJ(~sJr_QhmVQaUm}g#PpWIC?>=hiX1*70uGzrN zwqCe}W_>r?xqlr&v!0vny>Khdx^8yx!pCYJ=~hqjti!yK#Ut=+g-gb+8MUp_3Nsg?si*u{f^U4v+b^5H|>~hcm29+r`mScuZMP3+wS`H z)Q;MA*RPj$72EFm_12EqcGs_ucG$MNetorl+wS`H(@t@_ox6VhwL`Yu^&6n=7*q|1 zoBA)f+dnn=FQguw{QjBLDNaUsVDv`!0w!c=#QuVDQphl!Dj~x)C1ixAgpAabkWrcv zGFnqY#%M~&SWO8Trzs)hH4!pF8zIMQBV?jBLQc>|$cfqrnWT-7$=V1xNgE+2Ya^sU z8zED)5mKm)kg3`TnWl}9>DmY>(niP(ZG_C!M#wB}gv{1P$Q*5i%+(Hr4EDcsw}0x> z?v5rrBoI>Q?xDi-q9(_LER5J+K2Hi+q*EoNL{maaH6^4>Q$iMNO2`sT2{}bmLY8Vu z$TCd{IaL!Or)eW(xi&&h*G9-0+6Y;pjgXbv2wA0#kTbOrvRWG^$AnxKv2RRB3b|aTO2|e{3E8A6Ay;Th$YxCm*`g^STQw!*N=*s5N>f6v)ioKV)KWcJJ$ior) zrj?|SM|7%$?9`NyM>QqnF--}1TvI}x(3FrTH6`RJO$m8gQ$luWBIFruggmQ_kms}! z^1L=eUeHF!i`oczNgE-%wGr~NHbP#}M#!t$2-%~Jkk_;k^13!c-q1$KUTuWDsg01g zv=Q>QHbUOfM##I`2zgIC5b~fu+TH%C)!hT#@I!%+yX-#X{iw+?As~PLQ_J%)Rd5~G$rI~O$qr%6CvMfBjh`6gzVQw$oJX^`9T{Y zKWZc7fHp#Y(niS7+6ehY8zH}HBjh)2gdEgH$nV++Ii!t{!`cY>LmMGSv=Q>BHbVZ= zM#$gV2>C}l5b~j4=5GJgSM0IJM@b>EKkfd+eR0<4*mqZkLlOISx8(QeMnXDU-(6XS zt?#akvi04SRoVLP%2c+#yE4YscUPvd_1%@}Y<+iS23y} zQ6B<|`VvsokAR~71QZP*plBcgMS}<^8cYZjH4FLfZ{2vYEp}JbT#C9HsUe}L`7%W# zLJ|9R+oYnAoG(SA*itl_Ek$G4QZ$w=MdR2~G@dO*6WCI8JX?w;vQcyb0YxVgP&A2v zqR9jlokT#<$pjP?5KuIQfTBVIil!1!G>w3w=>!xN5l}RPfTEcM6wM-_Xf^>wa|kG! zOF+>)0*dAnP_%#$C>j>>2RIT|BfTD{CD7u({qDu%U+CT^t zEeiST9FW-g?j!ARi4;AQ{5UHVHD9J^Qz&BJ?w?e21?NlAX0{YRv>0Y&!{Q1k!+MGq1JMVE*C*By}9MEjt8 zqZFNPiXI9@&6g>9G!(HP7m-x-80SmT<7_EGdk83cjew%p2`GAlfTFzw6un76 z(OU!*y-h&TI|LNHOF+?k1QfkbK+y*T6n#ht6g?91YrDT)5nEvQMLVVFCwp}LQ7CG@ zOwp&Ii2b;cq@vF_Uy43wOVJl>Df*HvMPIR{=xeqVeZ!WbZ`o4x9b1a_vr+Ut0YyI$ zQ1l}KMF$8d`iX#|p9v`Xg@B@82`KuFfTDv06#Y&>(IEng4iixH2LVM#2q^lKfTF($ zDEga#qJIb|@>0q_%1=*zJt{;%Q3@eYv@hhJ?103+w!gphi4^^8_eFk6)O?wuXiCI> zTuo9@RnC{9RJIhw*iw|nmZEgF6lJibD3dKkakdmC*iw|mMo~5aMb!u>s!l*r4FZa4 z5>Ql&fTG$26xAW1=qLh;>Jm^?kAR~31QazOpr|1MML7f%H6oy>F#$zQ2q;n6QVwIHOBmJ-JzNmRh)O?wuV^bpbwP8z9 zE?bK7*iw|wmZG+7DQd@-qV{Yl>cEzwj%*ZlBA}=<0YzO1DC$Z;(QyP6bt9mtI{`&K z2q@}FKv6FOih2`J)Q5ngz62EYBcP~10Yw7{C>lsW(I5hf1`|*;gn*)<1QZP;1d3Xw z_}@Apu~zQydxcv`(E|5n&+zb+sQEHQqf;XG6wN1~XaNC5#RL>BB%o*!Ay70j#m{pwqGfC;I+ZO&r?I7IIa`WOXG_r;Y$;m7mZFtx z6s;nl=u85NRufRPhJd2A1QeY`K+)L*6rDpr(YXW^oku{?`2-ZLBcSL40*WpqplCe- zMHdlJbTI)%mk?02fqfJ zMnKW)1QfkNK+#?Tiryrk=q&<@-X@^v9RiBpC7|d%0*c-zpy&eviasQu=pzD(J|>`O zA0bfmSc;$0$|*W*AL&0XMU(B(^(QG&^JR*@NQpFQEk$2)z7&1MmZGoOQuGa5ioRt_ z(RXYq+Rv7v@7YrH16zuIWTWT+0YyI%Q1mkaMZXYG^eX{HzY$P$kbt7!2`D;5K+$0W zivA#==m-Hte-cpi7Xd|o6HxRI0Y&cb3~zBaqx*`wyBn~-b{Zm}D20F`pMat;0Ywo) zpy;y{e~<$bd&%yLK9{0N_UO8bA2na5DCS4($IT}1i_$n>iqhFql);vwOtuuo*;15X zOHmeEin7^KRE;e~)!8VjK|oPW0*Y!8P*j_MqB;Z=9YsJ^^g5l~d0fT9Kj6g4EE zD2ITeMg$Z!CZMPZ0Yyy-C_0*eqGJdsYDPd&a{`K55Kz>T5GbnZ`xiPOu{Z3YP^uq% zr2nDa7q#-E=F1f2`Vsqa#YshZoG(TBY$d2O&PHZXa%$A}q zY!r1Rpy)UPinQ zMS}?_8bUzPPy&jE5l}RofT9ru6pbVVidy^rUI!$0i9Hl*BSoX_zG##mHD9J^oFB0t zcb!x;p7W(>0$YlXXG_sUwiKPfmZB5cQZ$JzMU&Z5bP`*NPG+O1fPkVY1QZn#P&Ac* zqG<#aO(&qJh=8IQ1Qg9AplB8WMY9PgnnOU*Tmp*b5l}RrfT9Hi6crOtw2*+JMFbR; z5KvS~Kv5YXP&CH(k81A}rP$riSSdPSpU7V9N6nWhTINUW$E7C~oyz%AbQ)WVmb0bk zbhZ?o!Iq*GY$;mFmZDW`DLRuaMXT8;T0=n5S^|pBBB1DO0*cNdpy*rziq0dT=zIc- z))7#20Rcr95>T|BfTD{CD7u({qDu%U+CV_jr34gRMnKW!1Qcx~plA~TMOP34MW^`w z6bB?$X!k`+rD%+i+U!Tomnpi+kJyjfPb#{a^QGt-wiIn+OVPD#Dca7KqU+dFbUj;& zZeUB%jch5piH)M02`IXSfTCLoD7uY+qT2~5x`TkCI|(Sdi-4jX1Qgv(K+!z}6x~Ze z(R~CI-A_Q#0|XR3NI=m;1Qb0?K+z)v6zwFS=urZS9wP*bw)*}J4oGZ(DY{aMM%Z}V zkD4!2^t2zbf36{^Xcy;8(KBo*dX_Ck&#|TGdA1b2z?PyH*;4cpTZ(qGrRZfgie4e0 z=v4xW_7G6?8UaPG6HxR90Y!TWD0-8CqPGYrdYgcvcL*qYmw=-82q=1=fT9lwDEg3q zqK^nD`j~*CeFPMJLO{`{1QdNn2oyc(`}-Y`*arKo<5N=PzL(a0z~)EImnr(%kJvx= zkyP{z=S$JIY$^JVEk*m;QuIArihf{A(T{8?I>45qpV(6LGaE&}5K#0h0Y$$NP;`)h zqTdN9Iz&LxVFHT&AfV_70Y!fjQ1ll8MSl}e^bY|=URWQtqbNi`Q3?S?J^@8x0*WF8 z6jdRhC`v$4RYIWXOW$wnfW$W11M07&=u7*sKQ$aRU#2J{9I<~cCaEZs^Q9=xmZAh( zin7>Jl+Bi+YHTU0&X%GYY$>YAmZDm06xAl6s15-|M-fm|mw=*r1QgXLpr`=>MGXlk z$|0br5dlSw2`FkpKv7cyijF3r=okWunh{XcoPeSh1QfL-pr{oAMaL3Q)S3_|N(=i- z9gx@wc3+ep4nETV$R1s{2}jMBDQX*zT+v&K+Ht-VwP#CF2euS-WJ^&ewiI<{OHmiL z6m?}w(Q#}k>c&PUfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{ z4JM#y2mwVy2`CyyK+$jlibfDnG?IX#Q3Mo?CZK2xAyAYT_8)UVVyoQ@=S$H*yJH#~ zj+!r1bbL5s|6En_zGx!nOVJ5zDLRoYMU&W4G?^_$C$XjIWVRF)u%&1UTZ#(VD4I$@ z(KG^zrV~(9L_pCD0*Yo5P&A8xqS*u#%^{#@E&)aJ2q>CQK+ysMii!y+T1Y_AA_9s^ z2q-Egps0+1qQwLhEg_)j6hfeAeAo~7bBbozS3o96(O$bRS{ja;FH^KU9I=1yEUD;p z&X=My*iy8DEk!HYQnZRKMQ5_5Xf<1k*07~$EnAAtVx#D60*cNdpy*rziq0dT=zIc- z))7#20Rcr95>T|BfTD{CD7u({qDu%U+CV_jr34gRMnKW!1Qcx~plA~TMOP3|w3&dS zEd&&8B?O924f{hJkXS4Gd)KE)QOJG6Yxv4=)O?wuZQ+Rhb9qTc*K)oTZD&i-b!;iR zo-IW;u%+lmwiMmOmZF>4QgjPjif(12=r#h1ZYQAV4g!kqB%tUn0*ZDJP;@r|MfVU; zbT0u#_YqKZKLJG#5K#0W0YwiHQ1mbXMUN0rw3C3MM+qo;jDVuY2`GAkfTAY}fugI! z{zVQ*tf$=UOVI(g6#c}OqMzAP^b1>xeq~G1 zZ)_ADB%tVb0*Ve1P;{7pqCW^IIzm9vp9B>BML^Nt1Qh*4K#>>GhwUf|5m1yuK#@;C zQJ8?D2mwV^2q=mYP*jzGqErHkVgwYW5duZug#CKMouXUpJ=(WYlxFYI(j!sxWr`A! zi2ZY~Nkv(lFGbmGDXPYnqUvlZs==0`nrtbm#g?MlY$>Y4mZGEBD5^_9Q9S~R>Jw1Z zfPkWg1Qg{EP}GQkqQ(RiH6fs=DFH=C6Hs&v0Y%LSC~8hXQ40c!S`tvyih!bH2`Fk! zKv5e4igF1k$|D4dG9&&}2P9U<{@!&w5`3gT#qOB$BT@5ZiaJCh_Rj?;6?No%DeAcWHCZK2t0YyUzC>lmU(QpEaMi5Xml7OO71Qd-XplA#MMPmsl8b?6UctW74 zUBti10g3gj>fp4OqMbG-M55-)6rC7}*grR&R5Xe6rD!r+icVrn(aCHnDqu^|6t)x< zvZZJ$TZ*Q!rD!@EMMVS@%^;v?CILmW2q>COK+zlmislkfG>?Fy`2-X#AfTw2fTD#2 z6fGj4sDyx`QUZ#~2q;=iK+zHcicTS*Xej|j%Lphsl@KVJ81a8_Kw>-Xq0k9Z^#2ie zAJ9>ijoSD3Fxi=8Qf3l*H58?jgbvbs?kw2XkF`v@pnPC(K91Qb0$K+%H)6s;hjXe9wf4-rtbih!ck z1Qe|ypy*)&iq;ZP^a#OIbeHR|Z-4~%+J|M+r08dRTlA)!}A)x350*ba0P_&JJ zqU{6}y+}aOO9T|{AfV`F0*YQCpy*WsigprE^cn$0uM<%81_4F82q@Z3K+zroiuMvv zw2$B^dd&4tF+hT+>?8g4QuMZYTGX3v!1}U^-gVv8w@A@`&X=MCY$-a(mZJCAQgnzd zMennv=rCJ~K444HhioZ2!bZ_i0*a0iP;{JtqK^nD`j~*CPY5VFK|s-`1QeYlpy)FK ziasZx=nDdhP7zS_B>_cW5m0oRfTFJnDEfwgqHhT(`i_92?+GY6L+}*6?fQ2aAVKqw zayU`%NYRbTZ+!JrRX=d6#dSYq6=&(y2zHI zOKd5+%tp~41Qh*AK+zQfimnn+^cMj|e-lvj4*^9^v>vvj$VWg?5dw<*1QbOPP~;L& z6iq-;fPkVH0*Yb@C<+o#6h}Z&JOM=s1QaC_JVj?+fApSr4vw8mw=*r1W!>?w7;7H65MC+T_;C-kMt|rhyC@V1J;*S)HvE5lPN__IA4mI zvZd&HwiGpEOHp&S6t!SWQA@TIwPH(AYqk`%VWX%m0Y&WyC~8kYQ3nEwIucOSiGZTc z1Qc~4pr|VWMcoJ}>P|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk+!fqS*!K+yyOiY5|JbO!-NlL#o9OhC~T0*dY=plB)qMRyTAMFXP!9~&US7wq>J4V0os z?I*IQMF*@et7ulV`$v`(&E|Y5n!}c&xoj!An=M82*itl~Ekz61QnZjQMfb3!Xb~Gl z_YzRFn1G@s1QabLplBHZMfVX>cWvQZzI2fGs*;eOW~tqurJx zr07Y`m!hZGQuH)iik@Lh(I&POJL;Y=L3>;DPISQfvWgByyK_fL(R-XPMTgi@^gdgP z4zs1`1GW@>$d;lbY$-a*mZD>9DLT$Z(MJRneM~^nCj=CoAfV_|0*X!&Q1lrAMV}K; z^aTM$rwAzel7OPG2q-#DK+)F(6n#TL(YFK?eMdmi_XHH3A)x370*Zblpy({YQ?x(Y z|Fi)TJZ?Xt9gw0`_F?}|(E;nrD*83rJuq5|&U3yL{l=D}-`P@hfh|QB*-~_gEk&2v zQuGH~ivDCv(G@m|t`bo67Xd|o6HxRI0Yy$g58F}XBcP}V0Y!cSilPW8atSDkCZH%l zKv4_}F1qmpMBcLdrfT9EfiV_JZ3K38gCZH&Z;3@hg+JDXf3I1ene$Giz*nUJy z4g{<(tEfc4P0E&{lAJF^rPxwbnk_|T*iuxMEk)(nQdFKTMHSdmbPZdIQrIY}NI+2~ z0*WdVP*jD0qH75#x{iRNsst2OBcP}{0Yx&q&-KH%OoUW%G= zz7#cQOHm896t!eaQ7g6-wPs6E8@3d+WlK>zwiLBzqo@M`MI8w!>O??MX99}45Kz>W zfTC^$6m=({s0RT>Jqal4ML6EXnR{UFc7f5tfD~y_u*VA%H(`08qAiWA#5oc%9f%m zwiFFxOVMz)6pdg@(MYxwjbfwdb^?k<6HqjUfTFPk6lD`oG>(9x@dOm*5Kxp$Kv5n6 zMH2`pnn*y=9Rw6jBA{q80Yy^?D7uq?qNxNF-9K-;NN3_1eaSl z8B)~4et4T12v}cM(cFN0+We!#k*~(y&G}L^k1a*>*;2HCEkz62QgjbniWae@=w7xI zEoMv65;lsK5>T{^fTH^dC|XWH(ftGzJwQOwg9H?WIA0Y#4zP_&MKqQ?j*T2DaH;{+6KAb5&q2mCP;jiPmCM$M6;efF;Q6M=yB zWfeUgaH~&}qGvc?iZ-#O=vlTDJ;#=!=h;%UnJqzQgngyrRXACiY~FG=rUW1{$NYd zpKK|*!j__|Y$^JSEk%E`QS=W1MNW(!wxh^LKv59_iu?o=MG;Ws5>OOPKv95zq8I{- zVhJb;5>OOJKv6saMF|8HB@$2+BA_TtKv5C_Macvd6(yjk7{OC?KHxuLfCL|~pLP6= z+agPF#$zQ2%e&nG5(b4M$sPo6_8Rf-Xr~X_9I%;n1Jl zv!!SRTZ%@qrDzmeif(61(P*|5jbWo`ECEH?1Qd-UplCb+ML7f%_YMUx09noK~^6atFwB%o+20Y!HaP&AEzqUi(_%^;v?CILmW2q>CO@Dydn_%|6K z!LYq6G+2t7T2gaj0@jyRG(X0DZ>|(A;Cv}s$d;me*iy8JEk*aTrD!o*ik7gYXenEY zma(PiJ~oP$6Hs(N0YwiGQ1l=HMJos>T1i0BLj)A9BA{qB0Yz&FD0-NHqO}ARJwiay zqXZPKBcSLp0*clXQ1mzfMH>hxdV+wWjRX`uN$?ci9pgW5fCNk1zb0g!6xFn(o{9-r zUslnxF>cZMQuG|>OVRUeDca1IqAhGGdVwuPTiH^yjV(pn*;4c(TZ&#{qi6>KMK2Rj z^a=q*uM$wSlYpYv2q=1;fTA}DDB49p(QX2Y_7G6Cmw=*u1QfkVK+#(S6unJA(K`eb zy-PsRegcXP5KwfGfTH&Zo}y=B{EZEeU=K5+Hc8P``w{I>Ou+iGiav~SZ(b-xM>t=K zjtv!&=GwiJELmZDGCQgnhXMW3>z=p-9OpAk^>IRQmq5KwfAfTAx6DEf+k zqSFKveN8~oHv|-YOF+?g1QdNwK+zcjihdxV=tlyI&Js}c69Gj(6HxRE0Y&EsDEgIv zqVoh#(cu{XGy}wZ70tl;K#I!PyV}3S1gtNs=u(XP$Ra7a%=uFE2V08%WJ}Q%wiI1u zOVM9!Df*i&MgOp+$cfeCb}90)QB;J0B0m8|Q3MpZ1QbORP!u4bD29NdSOSWI1Qf*) zP!vxMnF+<0*XoyP*jrODY_8j-)DdXKeabM z7o{l2j#9A!>&q%C7wdkrSc=MXz7$npOVKrKDN12WQAM^CRbop~WwsPmVN21qY$>{q zjiRaq6jdXjs5${fH3%rGNkCC80*Y!AP*jJ2qErHk(g-L@C!nY<0Y&u)D5_6DQ3C>s z8WK>{h=8KT1QazPpr|PUMb{Hh)QsRMDiiAuE-{K8i#Bk|#(IzRkK55aHeh{OMXh7q zn#-i94d+WyTecLnV@pwcwiI<>OHoI*6m?=tQD?Rkbzw_US2l{e5m3~ffTA7*6!j#a zs22f6y$LAlLqJhq0*d+(P;>(UMK=;qbQ1wZ{Rt?#nSi2O2q+prK+!+~if$#K=r#h1 zG6*OdL_kp{!Bf;S*5Atj3GTHwKdq#wV&nl^Y{2@miiX9y{(Ek&c*QZ$AwMPu1gl+Bi+acmTgC!i>YfTCOiit-33nm|C&L;{NLAfRXx0Y#Gu zD4Ie*(VYYoO(me{E&__C5l}RpfT9@$6wM@{XchrQvk54gLqO470*dY?c#4L``X4kv zg3ayCPnHywGk24s=EVlAFRSRDSofs|q-YW6OVPb-DO${yq9tr8TFRE9Wo#+Bk1a*Z z*-~^rTZ$fFqv$~bidGO%w32|LhX^QIML^MN0*clUQ1mbXMQaHtdW3+YM+qoeM?leI z1Qe|&py+V|iZ&2X^aKG#8wn_Sl7OP82q=1*fTCvzo}vY@{*wksu)Ud43#I6BpBbBC z1J;*Sv^m!OYlReT;e082fh|Q_*;2HPEk)beQuHEQie6$%(GIp0z08)PSJ)_em4Kq1 z1QfkSK+)?26um(}(Jlgtb`wyvhk&BJ1QhKfpy*8kiryli=xqXu-XWmqT>^^s6Hs)3 zfTDv06un14(IEng-Y1~wFu_ywT&%y+N~7on`-#TqrKqWWjP^ln!1}U^j>WodS4q)v z&X=N(*i!T{TZ%qmOVJ6o6n)B;qLXYX`iw0_pR=Xt3pR>Q5m59c0YzUCP;{DrqOS=k z`i6j_ZwV;+j)0=?2`D;4K+z8b6#Ym*(OCkDej=dgX99|TA)x3S0Y$$OP;{PvqTdK8 z`kjEH3j|Nmky!r-10=Y^ewW%&DLQSxGTZ)RXrO3~gq9`_sTmp)s2`CB>P!vNzQ7i#PK>~{62q=mtpeTWW zqC^6ULIf0r2`EY;peUJuqM`&86(gXiH~~c^2q-E^Kv5|Iib@kuREFRwx*Y3&&HxGa zxA%+wkfJB-ZBf}^!1}U^t_iyDua%+{&X=N!Y$>Y5mZHjRDXPMjqHEbwbRAoYsvcfTDB)is}+jRF8n7`UDg;AfTur0Y!}n zC~8bVQ4<1+ni5cSJpo0{2qduy;9&8l#B%r7l0Y$wD zDC$E%QC|Xz`Vmlc0|7-h5>Rv#0Y&`@D7u+|qFV?k8bCnNKmv+xC7|dw0*W#SC>lgS zQ6>RJg9#`aLO{__f~TlW(BISm3EID@D5|X#J!MB$FkpRIMI(dmfb~)|iu0xDcD59a zW=qi+wiJzJOHnpkipH^}Xgphra@bOo%SKTi0YwuCD4Iw>(H#U7O(LLZG66+X2q?Of zfTF1c6x~HY(KG^zrV~&!gMgx$1Qg98plCJ$MRN!!noB^@-2@cPBcNzL0YwW4o}%GF z{|o~p_`bdQ86icf_9NQDV8HsaiWUdmbsMB;3Fk}EQnnN=V@uI}Y$;mKmZJOFQuF{@ ziXLQ3(F(Q{tz@I+D|~y0RoB+5>WIW z0Y!%hD0-iOqQe9feLz6bhXfQIA$W?m1pV<(8bw+5J40TOqAK>b=x8uteOW~x2i@9F zOVKBsFGVNVQuHZXicYen=rgtyea@DmFW6FaiY-N7vZd%NHi}LYQ1mqcMc)um^eq8J z-w{ysJpn~$2q^l2fTAA>C^}0((N6>v{Y*g7F9Z~wBcSM40*cNPQ1lxCMZXhJbb)}P ziv$#1BB1Cp!BccR=usKv5h4Mezg_B@j@QNI+4DfTAz~ zMM(q{B@<9olz^gQ1QZn~pr`}^MI{L+Dn&q1X#$GM5KvT>fTD5)6qP4 zs3u#AYOzsNn}DJ^1QewbP?SbMQ91!dbqOe{M?g`10*V?CP}GosqDBN1H71~_2?0e- z2`IXrfTCsu6g4NHs09H@BmFJ*wy14f z!1}U^I>x#GY?h)lUO(Le%K3LzseS)sI>hGNCzpp$2=`+L|nl7vWiB>x$U<~(HPE` zqOoi#%4SQ^IJOjxXG>8ITZ(eoQk2J*q6us%n#e}c9Rw6jBA{q80Yy^?D7uq?qNxNF z-9wa|kG!OF+@x1Qg99plCh;MGFWhT1Y_AJp>dj zB6x~M#ra1WAi?qW%lNlT(J_0&bZ=b1`m&0a#ku!vm!kVPUy7EqrRaXP6g|L}q6gVh zw1O=~E7?-?5L=2?v88A=8%1jfD0-NHqO}ARJwiayqXZPKBcSLp0*clXQ1mzfMH>hx zdV+wWjRX`uNkGw41Qb0@K+!V<6m24)=ve}ao+F^>c>;tRg4gy>+J)`Qr6RUW$sa zrO3~gqA0c$xojzlW=m0kEk!YGDT-xFQIL(II0A~|2`EY+peT`mq7VT^VFHSh2q;P> zpr|MTMa2jxDo#LA2?B~r5>Ql%fTGd_6qO;Ms4M|RzV{YQ%Gnx{ooj1O2}R?)Tb?)ulI=sM1qqN;2us>YV0>TD^h!Iq+$Y$>Y6 zmZI8hDXPPkqEt4D(g-L@C!nY<0Y&u)D5_6DQ3C>s8WK>{h=8KT1QazPpr|PUMb{Hh z)Qo_l<^&YAAfTuv0Y$9{C~8eWQ5yn^+7eLIj)0=}1W!@rc>g;FNbqxeTT~_9d!%14 z-i!|M0qe^u>Jsms*(F6?IbVvpv8AXxTZ($HrKl%cih8l7s5e`R`mm*_FI$TGu~Bpb z0Yx_wP;?UkMg0jVx|x8YTL>r`KtRzz0*Y=Wpy)ONiZTc&8bm-*CILl*2`CyuK+#YF zin0hO8b(0TZ~}@(5KuIdfTB?ZPf@3Mf8uVV$hBWO>nug~FPw?GJw9N4Sw-3LZt7ks z8prukG@dO*IczD)WlK>WTZ$&IrD!5sitb=b(ImDMO=hEL3IRoT5>PaifTFtyD4Iq< z(R2ceW)M&`lYpXG1Qg9CplA*OMRN%#x|@Kac?1;AC!lBn0YwW5D7uG$qD2H0-Ah2x zVgibm5IjX=;{E*$kl^$7!Tne%+HJ?u_<;3g72O~2PIyy_9^iZ_dXOzeE7(%Bk}X9K zv88AgTZ&e*rDzRXiXLW5(ONc&9wDIUQ38tA5m59P0Y&QxD0-ZLq74KTJwZUxMgoeS zB%tUi0*am{py(L_iZ&5Y^eh2I&k<1cJOM?U2`Jh^K+y{X6m2D-XdA&(bYHxGl>rjW zv7dEZE=3pY*d8CSzO15`sH(QGK zu%&1(8%6sFD0-8CqPGYrdYgcvcL*qYmw=-E1QZ=0py(h0Meh+%bcleW_X#LEOhC~G z1QdNpK+zEbijERcbc}$a;{+6aL_pEU1QdNj@D#li?>}XL1XtUepB++E!8|SMM0~*d zvWh;BcYXV%=nKx5qEl=s`jRb0U$Ld=G+T} zPXdar5KwfLfTF($DEgb=DLNVNzs>*&US~h+_?Z;-vXAuti4Ry`R*^r!?RZd%q7we~ zk-p28qG+}h1=vy)!fTD5)6qP5Sr~&~+*AP&YLO@YP0*WdTP*j=V zDe@)wM;jo)w=A3@3EpG0qULE)RT2W$msM0P!M*p86jkSZ-4@kgOHoa>6xCu&QEj#q z)nQ9fDqD)u*iw|vmZG|B6xAc3s6GKj4G1V|NI+2|0*V?FP}GEgqNW5CT~9z!GXjd5 z6HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*Us^{tEk!r6 zQPiJ+qMHdQx`lwE0R$8cB%tV40*Y=UpeTcYqCo@{WfD*{n1G@o1QZP=peT!gqG1FS z4JV*z1OY`O2`CyxK+)|46pbdJXbizq)HT6>*#HSXY;TLYNs;|DQPkLkfc0e+_J^@7w2q;=eK+!z}6fGj4=w1Sf786jkgn*)@ z1QabJpy)n=r)XS)zl8x3EM-6II9`e#x3@*h69U$kRkR|(%{V4SD>+|^9%4(;Dz+4@ zW=qi;wiG?gmZG(6DSCu0MUS$jXdN3xj}cI`o`9mq2`Jh?K+zKf6m2A+=t%;Ko+6;= zX#$F#A)sgz0Y%ReQ1l!DMb8sZw3&dSEd&(3KtRz}0*bZ~P_&(Zq8AA$dWqmEdLY3+ z#{da7u;1(WpcH*&AL;K%2v}cM(ar>S!$(r|8s|&V>uf1{gDpk7*iy8cEk%3SQnZ&X zMf=!N^d?)1-eRNZZ32qkA)x480*dw%P;`KRqJsn!y+=UNAp(ltC!pvs0Yx7WQ1l@I zMMnrII!Zv%F#?K?6HxRK0Yx7ZQ1l4_MJEU-`jmj8lLSxED+&Jn21u~I{WAWmQWO<$ z#%Bou>&q(oGQs`v6Dj(N^QGuCTZ+DBOVKxMDf*TzMc=Wd=zF#loncGS4{Ry=k&U9W z1Qh*5K+(?x6#YU#(K!N&ekGvjJOM?&5m59y0Yw)GD7r{M(IoRx7 zfTF7e6#Yd&(cc6V{X;;Jlc)#gDDn|JMPDTN!zYZQiuShXloSoHAJK{=2COfuC_2$i zKPg24&X=MXwiLy(r6|ajqByn`#j~X-fh|ReY$*z{r6|lsQ4#?~$pjP?C7`Gn0Y$|L zC@MifQAq-dN)b?0nt-A*1QeAepr{-HMdb-7sz5-|H3Sr;5KvT+fTBtS6jdgms0sl^ z*Ah^49l=u+mFU0G011|{aNI=ik-oX7Z62^C2COfusAi&j$LCU1i}R(ZHd~77u%#%K zEk$W;DN1KcQC+qa)niLheYO-eV56uZ0Y!}nC~8bVQ4<1+ni5cSJpo0{2qXqoec1ntRbG{VyVM|e8wiNYaOVJH%DY}s@MK`gfs6ShZ zZe~l-Eo>AGAfRX<0Y$eGP;?ssMHvJX4I-c@lYpYZ1QZP+plB!oMOg$C4I`jvH~~c? z2q+p!K+z}yif$*MXfy#uV+bf3OF&UJ0Y&2oo}wO!{;v#>U?cl|*FB}^PJ8cqd}6@* zvWg}oy8hErG?DYA=nl3NO=3&YWVRGdVN21SY$=+`mZH1ZQZ$V%Mbp_Rnn6I(Oah8# z5l}RnfTB4B6wM`|=xzdv<`GadpMatT1QabKpy(a~iWU)2bT0u#iwP)NLO{_{0*aOq zP;?&wMau~&x}Sie2MC^`+(dsh10?vgy)DX+Q*in zH`!A37F&wmW=qjKY$IJ|&>&BmqUA5m59w0YzUBJVmc1`nMS%!KHo! z=XEK%(T-Dz0qe^u`a01)c1DW6;e09jmMul!v8CvHwiKOVOVJN(Df*EuMQ7Pk^b=c( zerBWS7XpgT5m59i0Y&EtDEf_nqTdN9x~?=@!muDLQS38wyxoR#9xo zEqhjqf}Af!acn7yXG>86TZ$6dQWRoKQJ5`7No*-fW=l~~Hj0W7P*j|Nq7noYl_a33 z6ahu02`DN5l~c> zfTC&y6jdj9iUJ{jD+46B-rg0833-q7Ow$KR|1N<5m3~ffTA7*Pf@Lq|84^$ zc+@^dt1U&YCDk(&u)eIKz9DzxIVtML`BHQPTZ(REOVLeiDeBLbqMO-LbPHRG2C$`Q zAX|!VWuxde0*W#SC>lgSQ6>RJg9#`aLO{__0*bN-C>lmU(QpEaMi5Xml7OO71Qgv) zK+$LdipCI7G?sv(YyyhL5l}RqfTA1%igF2_qTV6@K?5Xs#D4dFA1PX7Kargm3RquO z(WH?3(|IYH%=uC@g)K#QvZZJ$TZ-;tOVKp86isJK(G0c}&16f_EH;W}6HqjVfTFns z6x~fg(L4f*<`Yn~fPkWf1QgvvK+z%sitZ(#XfXjrO9&`hN z^Z)@x4-!zcf`Fox1W(b#kU#l1qv)LdMB^P&RMtN1e<&2NzO15$LvFnbQnZ%yrRWj1 z6g|q8qIGO3dW)BHDI9rM~u%+k;wiIn-qv%Njik>2%=xG9qo*|%U69Glf5>WIU z0Y%RfP_&tVqAdgzy+AUOVL@j6#c}OqMzAP^b1>x&atKF zS2l{y6HxRU0Y$$PP;`NSqKgC+T_T|9G66+@5K#0d0Yz5`D7s2O(O(1<{Y^m8KLivx zVLfa|k&l3)A_Nrq2`GvppvWblD4Kwx0KrrAP00VX0TO)KHE_O_qAB*aC?*`RzO177 zuJMa9@sRGckECDs!l*r z4FZa45>Ql&;3*1*{WT1b;OSTcCob$g(yw9fUDpl=tS_r5J?wV0Yz;HC~8YU zQ9A;P+7nRJfqPkRSHv)>f6HwHHfTErR6!jvYs5ik=lp6Mr zGeCl)>}^q+6ou_av_9d0^<@>^7ldR(O3eCvI!^}M?led0*Z17D9RRvx0Y!@lD7u$`qQwLhEg_(2DFH>x2q?ObfTHCD6x~li(E|h& zJxD;&3Id8&5>WII0Y$3_C|XVM6ip8MuNol1+wCVBr$~`&Z;RH11J;*S^k~>EZ~i)n z$ZgR&&X=Oc*iy8fEk%#BrDy|Nik@Ig(MGluJ;|1$r`S^TG#f?F5Ky#V`VUl34qih!ao2`KuCfTGg`6n#xV(KiH7(cZ9s zz5xmML)Bp=ohvWonuSUuWTtg z&z7R!*i!U68$}lgD7r{M(IoRx7fTF7e6#Yd&(cc6V{X;;Jlcb03 zDDn|dRD^&cKLJHi1QfXh6h#wI6d<4|hJd120*ZnJPto^b{~-e;m~Cd%87UfOAL+*> z1*|WtD3s*>5+_Ar&X=MjwiG3^rKl)dii)wNs5o1SO0cDyeKv5k6ic$%lqJ$)Wv3R4Xqx}jQ6B<|`Vvso zkKie)o8-U600~yIkJ0K$(S7z|{|!k2>&q&-Imx{l>dQ4Rq`xdasD5l}RNfTD>66x~5U(If(jCKEhGHzoNWH9&&3?QKzi zDY|4o1vw=tV0~Fd(~{iX$x<|(^QCA8TZ(3~rDzsgie|H=XbxM7=CY;eZnhN7V@uI| zHi{MyP_&SMqI(D^T0}t6y#y33CZK2u0Yys*C|X89(R~CIEhnJpegcXfAfV_$0*Y1; zP_&YOqK615T17z7Y66PZ5K#0m0Yz&Go}#Hq{%;MC;KTOj=PoJw(~d`y0@jyRv_8oV z6qlmMIbVu4u%+k;wiIn-OVN{TDSC=6MNhM(=oz*YZDLE&vuqSSM?lf@1Qcy1plAyL zMK2Igw3UFOZ3Gl;C!pv>0*YQDplAmHMK2Rj^a=q*uM$wSlYpYv2q=1;fTA}DDB49p z(QX2Y_7G6Cm*6Q{m*lTyfCM|*@7{k*iq6{GqJ2pL>&q&7C&}$zQi|T?d@0(`mZAe} zDLTlOqW9QRbciiQ@3W=oFk6Z~U`x@5Y!n?Kpy((8MaKvzI!-{*M+6joOhC~m1QeYh zpy*QqicS(x^cev~pA%5@1p!5;2q^lJfTFJmC^}6*(bohNeM3Oew*(Y@M?lf{1W(ah zN&XxIBzVp~(tn%VBJ;GUGf4sK%PRUQ$z5JrihkyNDf)#iMd#R3^ebD6&a|PmZD2+6kR5u=nn#l{v@F23IRn|2`KuDfTF(%DEfzhA}3i7+fn2rpr{A| zMScQ`q6jE*2`GvtpeR5=$a2`GvqpeUYzq6C7c=*J}g4g(}u+ujzPm7;m} zBU)l|!1}U^l9Sy}%1TjD&X=NMY$+YY!sCz zpr`@?Mb{8eltMsJMFNT{5l~c_fTAh{6kSU|(RBnARVARP8UaPs2`H*TKv7KsifR#1 zRGWaJIs_D@5>S*zKv6mYMRf_DqHwbRZv!Owl>HP@QnL3*|D3@SRWCVUeOX0~lHF@6 zNKs?Xm!c+YDQe1=qU+gG)Ql}f&Dm1af-OZY*;3SsEk&)_C~8AMQCk9v+7VFHo`9kb z1Qc~7pr{i8MV$#K>Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq0*d+(P;>(U zMK=;qbQ8f-)F9d4&HxF{w{RLt(Nud|)IT|3eOW~VlijQoDY}*OrRX-c6lJibXb@Y9 zGTBlzm@P#^*itl&q&dne0AONs4B1z7)-7OVJ#*6wPHz(cNq*n#Y!+`D`g#z?Pzg zY$>{jjiN;a6x~Ze(P9FMmJm?1lz^gT1QgvzK+$pnitZ<%=m7$X9weY>1p!4X2`GAq zfTC3d6s;zpXbk~H4--(dmVly12q=1#fTDE-Pto*b|6v0p_^p{yGoy9YN^Rg(}x}oNl3!sgBbt^nAMG^b1|6=Q#aC*Ee*WfuWg=9cNJJ?WT@1 zG?dWXaYlstwsf4)p@&*K&bZJQZ5<~sbZrO6nH0LcljBScZRz4TGeVcTInJC=^PY|~ zKQz0y<17lj+t+cHhC(+w&i$bq`a90b(CS+pXHDqKfsXTNsA`7eJRTa8={Qe@whnQe zO`$)s9A|T=ib*%i8JyyNT(J)G+}?}ScIaGZmo>gJ!s zI2_8J;y6b`+ow9t$Du3J9Oq=H^-RY(6`D8OalQ_{H`j5#4;7v7IA=pQFLa!9p+^=u z&hMdb7CX-6P|anIb2U7Exq1Kl!Y@5wt^i;7uNCGR@P*s1GFO2wykL#F4t(MF*P1KA z7cRceTnoPNfc55T@P*fHFxP`GZ2vX;D!#D&=g6!1!uH>juH_5ce-Jp$7qY?+SJEh0p9V*NHD||7DMUzOenL z8T$Le_V3mo=nLDw9DR^4Z2xxap}w&F>xoDB!uIc%9qkL-zaVs+FKqvY$2?!y{uOJzOema$wz%*`_pcZ`@;6em7es4?a!NR@`ddW3~cs=?RR`{^M&oV?C$V|?e|>n z^o8v=&F%7q?RP!x^M&oVt-Rw4+wVI#=nLB~93S?D?N|Pe`oi{0Hy``L_H*wiePR2_ z(^I~%{p{D*zOeoD#rM9jef)XW7q$-|&iTUj9^mi3u>BBz*%!9A!B>4wQrLcO|8eh+ zT=I6GxiagSKSt)QHGi;tYl>9!IYpP6XYn;iTw-%kBhT?Q)Tn2l(n#a7-;BnIvm?*8 z$^7~AHPKVHnwRKns`0Kp=X#C9b~Mv?-oEzc8l&t>YoT#4XhutoVfGTV@lGwg*- zsOocy`+B+Y!A|>o6!-OZlV&e?s(o=^pXj8mhra)HT5(@rH-7H!W5u0fU35wt@094I zg~u_)*=bHO!#Q%{p5ZmUyzktmDUq}8+w%Us=68MEq_vw5n+t3% zU6161{!Xzv=A95SZ_w-BIleTf*kei`NB{=}wn*T*%9>s-`G(Nki~$qgJ^qKo?C;=E_@nHflM{4qR#TwFq2 zd|YEgA*STNJXfrFu0k(0sOfsIBu+2VO#33^^&%rrEqIX$dXajrM01i`a5+K==F-{M z9FF|PyyZ!HOY};T>-buh=0a30o#ac7ZdGbUo6`0*7Oh|C;*~Qmq}YO4KJ$J`FKVA! zeBmsgQ>4_gHs-@e37%ly#dVyPrJI!=n;3ba=CznBznleN{xk2m$p7vC>>sSczY6ap z^9RN63^mVD#CIhz!SR`2=6TJ3zB+YMb23wh<&I0u%^8xKlaV_lD`Q+vc3#$yysV+A zLvkjM%geT5NY>B^Ia#@do@SrlJa?1SaXBN$jLaK3G0RCEkv%3WHFI>n>{wGc2?%#k+sv)>eQ=kpIpa0`Cp!tI&$og(G!MdrH;uQGGgS| z|K}GYcXDpw_r&lKsjYK{P8c~hyKQz(R_*-v#iYEP$h*XQkMzpP9%bI=xv71}W#-)8 zVZzvqe&%f%-fQ%P+>Ac08+LE-pSYSPX69wt_m<;$SM;z6V~3>GuUBV?rI0Z+Ygp!l z(RmqplgDM{))`@inX7B)$gz25n48VMZQEy8a+IThzQ+=6zPNlAG+mjC_z%7ruKOPloSIs}{u%fe48Dp*+L#XkecE@-=#bXQ zvB&hrX`M0#d%ta1KmWH4+UEbZVPidK{l>J`oSatQds_RpdY*Li%p<#HXOByFy0`A1 z(Y8mwy57rf$0-f+Utc3qy@JeKPE=uwIULp><|`-p1Anjq=}CbKT{?p8Qu?pV!!~ z;Qemi+j>Ux-tn$6^HRLu6uLl-IMrNFktdq#Q0Fzse_`hG@Jj3I`Rf&2j<)${q_^c& znG3EnEVe@TCH_+%LEB{wo-o`ocRR)o&&tReJ9K2`*o@KHV~2Zhpt<(Vt2ZB~y{q5* zW8uAh^$RYoq2@h%{+oyCw1T&;N&Z`sZvMD9UEANB(Yjrq$a&_9)*EU5wCH#3{^d-^ zUZj-B|Ne{U^nwf0Mrg5ZuExkK0CT=5?+=H4bJ|DF9%cVvMxHfIFT(se(IshTO$r#H@jQRxN#@B)|g0+8md(5nVXJ_mE-6S)BC1-jA=FR!KX z!~$^X9k^-=oN;ZLH^MuQ-`J}qat-UM&HrPSo|YDQg1KeX1xq)VjNhggynhN^-Hr6Z zxJo=p_Qf|Yc;}gSt@j%1@~R6cq!(C7FNDEdU*0JNS3B2AdK! zWtzQV?Pu=#>iId*Tpy8QujI(bH19)M`~0)bHK3PRa0$4M&3i~s%fBwoRp7mb0vqNQ z#5`Bzg-4!bu3MdDJ{stE`EQ7E=bdkELhWr?j`v_F@*gSx(m(=2|Uy z2b~TX%+a^s??4!*(=_&T{W?JLA^;4?lWR1?s%+0EvQhUshaTA&kG4HXgNwvq+ zt7k&qhzVl`o8z$2*_nB@&4bnE=4u&ggL%$j<0dw!ojb1f(Da6;WabPR(cC!#E;54f5SF&CirurXP=xtYVWYLCtuJ3Mbh^E8vZ z`!}`iwQiQZ7mznHdu;7o^T5#@b4?qXnU|Try?2HA!0r8}fNXk!Sd6@^FYu*8N|E6Ot1J3Ry zI_8)!N!mSK#~tRg%XYu17%)i*)yPNXJe+y?uj@i+g)}wT?&odizTq%iQSgsyYtp@9i-h;x9WIy zptt|fv2KR9Tk1F|)7x`(eBD5|?~emIMh)|Jl8#+Qc>5+DmyYuG!#W-}e{k*jr*$ls z?d|G14j%9AY#pD>_4alhf1cp&D>~Mnh1S*jGpf8qB?e)>Ft|! zyl=L*AJOsSx!(Rp#|rbkT~o)Q3%xyF$EO#0`z0OEE%x?bIyPM9?Y25jUGD7#I_`PE z+wbcbv(nqeb?mXq+XHmGe~q`->3CwTx4+XdWu3Qc>o{z^w{vyew87gi>v(>nxBt4|@%LTc_U-nLP4{}ojyleG)7$sz_}1IrKB8m%es7o7vClzoXXv={kheGJ z`1xUP|EOb?Bi>Heanvzy-=X8?kG%bwju*|>^R0jX3GdkKq<8GB#7 zj)|weT~^0_-*`Jy$5r2Xd!vr0&UpJL9j`m5tt}*u}?DIdR<5%W84($F#$7<%Q zLv}aNacscbcj~y!d^3W5`feTnG~bnAcfkBupgp!S-=1KP-F3X%e4m2d%XK_xzG1=c zPjpN+-??D-H9Gb;-@;&bmX2%9_cGZ1jE-NMZ)&jnR~>7Z?{2WWk&fe1ynUCBFIMvQ zULDJs?;f(xUtPyEdvqPArFJ(RZ`N^`j=4I{(D7a!SLwJ>$89?9*71;zpW35&J&ERv z`S#dW$4NSF((w%)Kh)80zS?guZ$QVej>UA0w)bmd%-6f^(Y##y%O1_$naDBM-p?`H z+}&`BB${uI zUd^za%rWMfTKDN*Co?ZEXXM}sdFI9bZ-1G)P)5CXAJv{??xOt5FY~U7{HkdFZ=cWa z&HwUz_G$K4Rr8;D*Z&`%FU>s9zrS94f1Y3Vy0X7&ng7h)OsAFk&;I(omCtExj`q5< z&tw0yudkE&kIP_w>+CQutGw~RFMij~gu*YcR%@R#&IJ4NtQ%flKl6LeF~4<=nLGCb z3k7~_?sELg^QG7FIVtu8{o?rsn_c+zuIb{7__VLrc3$sf^Lx%Qzjb<>muDUGi>FO6 zq43MwROsc|M_jzTd(7`S$G(hA^YV(@H&nlP+B~xhzr3C1<=OYEy?o}6TK>yhVSaDV zvDcsdHL*E8n7 z!k2Gfp|>~5JdL+^r}@1xI?fy-ztYUhYsxT3UY9)@BKf~Yo9Am~VsTS=dG`HoUnl16 zGjB4_)WQBnzj%4}oWjp{)Lg!UJd-){e1*S>p?;n0RP&XBhKb?bRo)WHx|!G4(Y&VUp68qiee7##UA=3yZhJ15JGJNX*5RY+hqZbScrfWT&&4 z_OiA)U$k=Z&hcH|yu2@5(_F6A-gEWpc(HuzaM#0`=Cy{8WL|#Fd860qsXexpnBzMW zXu7@M;oS$EaEVq?3)?xT9N)}hi({P*`*wFPcj5Ra8)nT|d2!aepSUsRPe;li=PvUx z$unxcy~ALM|ImD3X;WC1xiX6QqVw!yV_(eDpg9zAgXZKSMFKNS^p`MKT9NLhy4&ZA za;uo9_}AL!>REbFBn5(Y#ki^FPi>KyKr^E(D$2E=dMgqY_`p1izp8l#f32de?eAYU zuiBqh%-(#tOYHf+=zRfm(-swVool~AIAH%4!m9eovTMvtccQ9kRxq=!6IETayqWdP zzkH!t&dmBwR87sYW;Sr5YH5}+v!VIRGc`+_*~p2iqgl$##!ghKW=S)fn7@BRvxJ%H z=3=F57q{D7uDaUA>^2vyo_0~Y%_Xa^oou(cXbrTJ>^7IJp?27AbKx3khwL_&uCaEa z-R9yo(N3`2T)w8-@n+XGm+yM*IJ?c|Yo;Bv+g!fp+Oc+<%hy6X#%^=@T51REHkYrJ zcC_8*^0n4>?KYRMjdqmX=JK`G_SI^q@SjQ+@Oh&8?_N~lQu&7Ya`@lZG_ySjgSG_2pOo2kXyA8a+@|nGPDsgNE;!U z+6Wn}jgTSQ2pOu4kSuM44AVx)aBYN)&_>8eZG?={M#$~jo{-M|AI42pO+aB_u~vLUJ`FBu`U9CTL2?L`?~~LsLQ~X-ddsO$nKz ziI6+B5i(U9A$MsbWSTZYrfVZ)hBiWGY9nNpHbQ1=BV>*?Lgs2C8YZG_yTjgUp!2)S1qA&a#UvP2spOSL^AWBm!{CL=c0e87py_JsUmXhbawSUFb6 z1Frp{lZcQ9b*hA{(3FssniBGmri850l#tb$60$~9LLSzXkhPi;@`xrv9@R$3I&FkJ zrj3yG+6Z}E8zCFC5%PpKLN;n6IqWYkNYL`%}&JAG^xlhTQK7iMAhQUJO_{R>&)^{eh&2kXLo8 zgzVImkk>RN)9CPLoSM#x**2zgr@A@67-{LcVbA535CloYJWh@};JPe5ENN zr!^(yYfTCHMpHt*)s&F$G$rJFO$j-piI5+(5%QxpLe6R<WM#%5l2)Uq*kc-*~xulJd%i0L}LmMG~Y9r)|HbSmyBjhh_g#4|Ikbks2 zA)op4%=I68$lmw(JR&4`)!v?%FF;y4_9thfe6Iab#>n4e?D}-JesVUNt)H9?u=SI( zF>L+hY%E(pIU8i_Cuif>`pMaNwtjLpfvumMO=Rj%1X#zhvTZX_-&Xy(cle6Ur{N!wT0zWxh zfxu7BUPIs~XHy9LYEmZCarDN1EaQ5su{(%Di}mn}v0*eI$` zKv4q%iW(A7)QEth#sm~KA)u%!0Y%pnP}GcoqUHn?wIHCVB>_dP2q7lAfTut0Y#k%DC$h`6jk;4&3BkM!PWMrsG1agW=VDN1*|WtsE5zBKS~`@ z)RXh2s25v`db6dd4_k`*vZbgWTZ(RAOVN#NDY}U*Mg7?*x|x8YTL>r`KtRzz0*Y=W zpy)ONiZTc&8bm-*CILl*2`CyuK+#YFin0hO8b(0TZ~}@(5KuIdfTB?Z6x~ih(P#pS z#t=|6mf$Js=JR(jK!V%MjOs2$Ei9>Q^DQ;TmsOPObM24fM-=68z7$PhOVLEO6y3p= zqDgEin#`7>DQqdalPyJ4*-~^D8%5IyD4I?{(F_8LW)e^|i-4lp1Qg97plB`uMRyZW zG>?Fy`2-X#AfRX=0Y&!^P_&4EqI(G_T1-IE5(0{r5>T{^fTH^dC|XYN6pi=!7a1VI zI_8mfRE`wA9C@7O3s_%P(Mq3d|0;)wqK7zNidM0uXf<1k*081MVYU>lWlPZ`Y$E*=otcvHW5(tECEH&5m59z z0Y#e$DB40m(F+6=Z6%;+8v#Yz2`GAzfTEWODB3~r6g}wke`tUN``ZWQE2QWytLSB4 z!1}U^Uh}#3uL6lEdY$v7=nb|M?P5#OZnhNdVN20owiNASOVOKbDSC@7MQ^iF^bP?< z?-Ee7pMatR1QZ=4py)jUiVhJ_^gaPahY2Y9fPkV82`D;3K+#bGijEObbew>qj|eFG zn1G^B2q-#1K+&fJ6rCiX=re++=vAM;l=;qqV3NHp+9^f9+I!cZ`vTUNRrHn5wSSdN zMA2!^m!hxPQuGa5ioRt_(RXYq`kpOCXV_Bo16zuIWJ}RmHi~{Cpy+1;ihd!W=o|q> zzYmm2+qZl_DlbsfMyM%zFJIU$15!RR z{oS1RL(vcEwy4milzb&cr8dR%qlj7*wRL`>I+4n-a8P}FFLqKX}g zs&*)9vMK5)P}E7FXdZ#0&H_dA3KY#JP&B_lQ5S)t1q6x~6ewCqplD%%qD2IX78NM! zDp1r-plC6HqQwP@mJldfQgBXLju$98L7?bFfufTHicS_NIz^}{n$@PTO9rGoB0WVkI}|;U zZi`NBQ%b&)qBGkRPhBPyo#psYbhaIe&ap$$xppWz&kjZB+o9+JI}}}LhoXz@P;{|P z(Io;!mkJbJCQx*_K+zQfMOO+GT_sR-wLsA|0!7yf6kR7!biF{)4FW|s3KZQWP;|3E z(JcZ+w+a;9CQx*{K+zonMRy7{MW?qZ+?4?-r+`?Tu9f}^YL(!vlD0<8eMUUH|=n0#mCk2Y05-56Fpy(Na zqGtt)o)ai~UZCg&fua`$ie3^ZdRd_86@j8x1&Ur1D0*F>=na9QHwB8`5-56Gpy(Ze zqIU&~-V`?Tz9g4oOL(#W3Mc)Y&eJ@b-gFw-b0!2Rw6#Xnv^ou~zuL4EC z2^9SS%|ePIf4o$EK*WK+(JcMe_+1%`Z^YMWAQ_fuaQkiWU+mT3DcH5rLvb z1&X=~6m=6QT1=p5ae<;G1d5gvC|XLOXla3>Wdw?r6)0Lxs3~e&C>)akDesd0x=_19 z?UDZ5>9%P3LMi!5ih34`=|@qwDC*_-P}FRPqTY5W>SKqZzIG_;XNRKxb|_lW4n+g( zP&Ck{XeEK7l?94c5hxlYP_(K*(P{!ks|yqj7ARUnplFCd(NKY+VFE?N1&Y=bC>kM9 zw3a~8+5$!E2o$X=P_&*v(fR^K8wfQ;-3x`6G9cv>(p{k*q3EY{TeM-Jlzb&cn-q%a zN13-M+SKu(Xfrz$ZElC6E$mRVr5%d4vP03bV+D$i6DT@fpy&jFq7wy*P7)|OS)k|?fud6dicS+KI$fwK+O<&FJ_Ax7 zooOnsWS?tm?d^;3fV27d$?ND@)9f~ftL(wI6 zD7w@RMVHwWT`o{`g+S4j0!3E|6kRP)bd5mKwE{)g2^3u~P;`Sp(TxH{HwhHoEKqcd zK+&xNMYjnQ-7Zjchd|Mt0!4QT6x}UQbdOL|bXK8oNd}}mJSjRm6s@1ey@gWpl@vW# zD5hV<(W2-f$A_Ya?NIcH9f}^cL(yY)D0YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k; zqW1-gJ`gDSP^c-ozfkxp15!RQJ?r>DC|W(;7JXDGC0|L=XN6+=RW2=xK6iX5`oa!H zU)rJQD?1c@ZHJ<7>`?Tr9g4oQL(%tkDEh&s=tqH~p9G427AX2fpy*eDqTd9HeitbE zL!jtSfug?zivAWT`bVJXUxA`rT|8{3C@)adMxdx5P*f*SR1_$x7bq$T6txvPpF1Qq-ZYn0^&di=sxyhoXudimG-fYO+I7M>`aCvP024 zb|~s>hoX7yP&A)S(fk5MT?C325GYzuplBh1qJ;&D77-{~RG_G8)KFL0Edx^CGTj!nud6-M-#^{E z?on4tzLKKeb;Z*MhoU}?4@G_LP}I*3Mg8qiw4xn~2H2r!pdE@JXBplA(&q9FoBLj{V42^0+%C|XmXXoNt~S^`CD3lyy*P_(W<(RukAZZAW*cSK+#45MI(ipqF!}{dom#91G8Dz9E!e3w?!M*m6ETdX!E*a`c-5tw?$hx zJ``DQJ`oifuhL*MNEyQC^}4_=x~9eBLs?$6ev1Mpy+6UqGJS#juj|6PN3*` zfua)xicSP;{XkiY~H4(ZzNsy2K7em)fD|GCLGqZik{P z>`-*2P0>{XMOOWb-CX|^bO)bXL{F*_7JZik{L>`?Ti9g3c^L($WAD0;>YMbFxy=sBCB=LL#h5GZ<4 zpy(xmqL&4VUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_XUbR5GeXk zpy(rkqK^fNJ`rk)9;z$6k^w1ilD>#N9Exs8kMuvSD`?TxP0=p`MZXFZ{U%WKyFk$&0!4oc6#XSo z^tV9KKLSPn3KZpv@vxnuyg*SKfue#yQJp|hQJ|<^pr|BJ)K;LVoj_4ppr}EpDf+yw zu+Vy$qASu@v@b$YL;8x=zF11WlA>y{n0}RSi=rmShoX*lDC%T~qIv94)Y%S2^V*?k zK06f6Z-=5Tb|_lFrf5NdqJ;#C78WR4M4)I6 zT3VoJ8G)i@1&WpvC|X{iXa#|y?gB+U1d4hJ6!j8niW-ZB9Wo&0F6r-GSBkYq`h|4E z)LbkjUrABFVln+H=oUr&9UqETv_sJVI}{DHL(xihC|cPLMXT7MXpkL>R<%RXYBoiy z3lt3&C|X0HXox`3P=TUh0!70Giq;e;8X-`$mO#zw4OlG`T|882o!B7 zP_&Ui(MW-!jRlG}5h&VJs441GEL@fWDX-QxgVQ$@-Ic~>#ZvN>6m3;3re7uAqG)T! zhoWulP_(Tbing;u(I`6!45@Z>`*k;rf8f%(RhKP2?9kE1&SsK6zwQb zw39&5WPze70!32=ilzw^O&2KIS)gc!K+#NrqFDk(vjvKF5h&VKplCONqTL0G_7G}{ zwkQ_9$$*saN_T~}3`JAYZPA{^Qu37)?OQCSUq#=dXg|k?qW$eqbbuX-4zxqjL3SuQ z*bYU9*rDi9I}{yehoZx6ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ul zqLT%RP7x?NRiNlJfuhp|ip~%yI#ZzNEP`?TgP0>pNMK22!y&_QbszA|e z0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keIiiwsX)k^)6b2^1|YP_&Fd(Xs+X%Lx=MFHp3C zKv8#rq8Lb(?HPsi^&4832O82fi*4G~CcS{fZ`_`9|ucT-| zeR0a@P&Cl-p=c#L6s>HBqE+lrG{_D`tJkM9w3a~8+5$!E2o$X=P_&*v(fR^K8weC_C{VPKK+#BnqKyTLHW4V=RG?@x zfuhX?inb7Hiu%_VPRM|ik4#_0Rt!atq;H38Szk)NlA>+vi#Lu5McX+(6pgY&(e`#I z8f}N79qdpv#tube?NBt%4n^bbP&C1&Xre&TB!QwG1&VeOD4Hx#G)16jszA{+fuiXG zMLP==%@8P>DNr;^plG&0(Jlf-y9yNTCQ!7yK+zroMSBVq?IlpOw@_2Gb$#Kr3`qHg z^!JOl2}S3nC$jgcFC|||(E;_v-^Ycb105fV4zfeh!FDJ*#12J=+M(z$I}{ymhoU3w zP;{gnijJ}=I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5-2)Zpy(8VqEiKmP7^3PU7+X; zfub`7ip~-!I$NOV9D$;91&YoSC^}!D=mMdpXutZxBI7ef->2K6{X@|bEf3i0OUYMK zbZLEYwTYqVGRKFa%k5Bfg&m5nv_sKVb||{q4n^14q3BvW6kTVBqU&vnZV)KCQK0B1 zfufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>py)ny12eDHUm;#DBYpHBov*JZi^nPFC|||(Np!sgLe!?Pdh#oJ!6NW zXYEk*oE?guw?okjb|`w$4n;57q3C5h6un|o^r}G7YXU{D3lzN}Q1qri(OUvVZwnN? zBT)3NK+$^wMehp~eIQWup+M0`0!1GS6n!F4^r=A6X97i^3lx1JQ1qoh(N{uE(G&HB zD>5MESJGFsCqvPo^sxWy`cm?h6n$S`d~$Lq`oZy`=tnyg{bYxtpY2feiyex7wL{Tw zb}0JY4n=?1q3BPWqQ3-+{uU_uN1*6mfudX~9=21I7bt2YP*e~osuL(G3KZ1~6qN*u z+6ol46DTSR6g3DGwHGMrAW+mOP*f2pstOb}2{lFE))&6ZfRw*ZH$UHnq8rn_>yD*T z@|6_LTPik93q|ueJ`~MwhoUZaC|bY{MGM-YXdyckEo_IPMeIHbuh)iq;e;8X-`$mO#z zw4OlG`T|882o!B7P_&Ui(MW-!jRlG}5h&VJplCCJqRj=0wh$=VQlMxnfugO2nxcWF z!d@AWa`sE8vtPv*iY`yLMcb50$yZXeeW`f%%uqDi@u6r3I~0wvL(y0}6pgb((Re!) zO|V1JL^~8svP031HbpxL6ipT=nj%m%RiJ2^K+$x8qMZebW(X9`6eyY{P&8YhXcvK^ zT?LAE6DZnUplA<)qCEwQ_7W)CTcBtkfuel{iuMy~inc2i9>{={`=^Ixqe9X8>C4;x zrBd>h6dhbDewh72-Inj^AL95>bf_JQ4zoki;dUrG!VX18+M(zuI}{ylhoWQbP;{(K z(QyJr#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_6rCYZbf!SjSpr383lyCrP;{<9 z(Rl(z=L-~FAW(FnK+#14MHdS-MF*A&ZFk8OouAFRgF?|m>8|!ArBd>h6kSm&F1uSO zy3+BX=qfuDU2TV=YwS>TtsRQ4vqRDKb||{R4n;TGq39-?qMHSZZV@QDRiNlLfuh?5 zitZ37x>KO&E`g%E1&ZzwD7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRG{cFfuhF+ zik=W^iY_Y^*3W>HKTZEO_VQ44NV+Y0vQ$dGlA>oz#c6wlqURhRik`Pa(F=AcdeII= zFWI5!WjhqTVuzwv?NIcZ9g1GJDSAVo=uLs5w*-pb7ASg0py*wJqW1)f-WMqPK%nSD zfufHDiar)7`b41UQ-Pw-1d2WvDEdO6=u3g3uLO#|7AX2gpy*qnrs(NX;iL>md1|^V z^h_waBi$B#S1Ki6NzqTG;>~-7qMscfihi*}(XVzW`pphSzuTec4?7h7X@{b}>`?T# z9g6<3Df(BSDAzU~wo{ZBC~6~6R1het6DTSQ6x9n9l>~~~3KX>yC@KpSH3$^77bxl= zP}C?;R1qku3KTU76m=9R>LgG!k5E(eL#gma2Bds)de-sBP_%3!)wyjc`AUkqv@QO* zPbgZz@u6rzI}|NshoXh;P_&30iWap)QCB+@b+bd!Vs6T3VoJ z8G)i@1&WpvC|X{iXa#|y?gB+U1d4hJ6!j7)Y8EK!El|`)ps24vQ9psA{sKiS3KR_x zC>ki#6wTMR&~@KT(YW-NWan>Nd!#=!eMMWTZ7KOmidJn~9K3%hTFvpHXmvXj4Yotk z8g?ieVuzxkb|@NVhoa$jC|c7FMI&sA))FXMTcBtifueNkkHw6Q?ZCIUs93KVT7P_(%~(G~(lTM86yB~Y}rK+!e=McWD#Z70+et`*k`4n-5}P&CmFMU(7Mw4)u0cCtg! zWIGg1u_>A=P&7@TXu3er&H_a<1d3(~6wMMSnk`VYi$Kw?0!6zC6zwihw1+^^o&rUC z2^8%uP_&Og(Y^vj`w0~7FHm%VK+%ChP0{GKg{v|k(L(vH~MJEarog`3nvOv)( z0!60^6rCnebh<#%83ILT3KX3sP;|CH(K!M|=L!^^Cs1_0K+y#PMHdPbT_jL+u|Ux! z0!5b!6kR6N6dlsG@IwZqd{;h$b7&}9K9Rb-Z7KOmimq;3>~vTty2kOL=vq4zU1x`) z>+Miie9oq(aUxydc_V!uiByLH9Hi&Zik{b z>`?Tk9g5zvDSBI==pBKgcLj>x6DWFLpy&gEq7Ma%J`yPUSfJ<=fuc_Ziarx4`dpys z3xT391&Y2BDEeBU=o^8eZv~3J6Day#py&sors%o0g?%z0*>}-0IM0WoyVDcdKejC; zUrEugZHwm~6^edyd?@^p72i{7QN2J>Nua2$Kv6q^qOw3ygFsPxfuarqMU4VQ6@j9vKv9!GQAdHIP69>q z2o!Y|D4JKGXg;B)=;yYDhcY1LebUX(FQKS&8uPa+C0|L=LhXtl9}|iec6=yW#12J^ z+M%ec9g4cyp=dEX6fJItq9yE5w4@!1ma-{YTA*kdfudyvik1^7T3(=N1%aaO0!2Lp zih2qZ^%5v*7AWd1P}E1DsINd#KY^nD0!1qd6b%q48Yob-l0ebQ0!6C`HAM@wE0mAT z6kSlC!CA0f?UDW~X$)#tO1_e!!R?C6A0LX=aC|5lVuzxkb|@NVhoa$jC|c7FMI-D` zw3Z!;*0w{@IyOb?3KXp;P_({4(FOuV8wwO{Bv3R`plD-(qD=&fHWet^OrU6Ufub!0 zinbIe+Df2kYk{I|1d6s5DB4b-Xp}(F_5wwtg_@$(+7&j;fRx9lo1fJ~QMZ-{Z0$

R!v@*;7jL zN4sN5QE;5VQ|_^JiPzE|ym~E17Z-ai-NWsc7F(9T!`Le5W9`er?kn@-3f(D*r}IaT zE-IK={<-cuZRKZvk$nwWuQxd7e=n2m`(%2J?t*zO$GC6m6u566BrZ*G*0`elDei^3 z5ANSGzoevS;^-MA?$!Q({^jm+x!)ya-z9f|<>&=Lgg70{!QgJi%g7WD*Oz`;$Q$K?y*_iq>l^Bx<{bB=ce8t4Q_BUObazqy^KwZ| zLSC+&pkKV)Xt&G1-O0T|o_!4L?ONyU&Tvn2j(gH;?OtDfdqTf>-gLLizrNM(^_hQr zefCI<*LRJ3nseNf-Vpct?B)2y^A@>K{`GAv_xdv2^LTykF2a9a-x&A$!k{Skyj%ar z>wCt%KD(am^10uFrLXT^_q1IG`&iho3C%-Z&-CDF`@cQU{&S!D|MPMWb_jWAxyCPE z?pYV?X?~q>FURY)X77jna(4y(^ZxEE_x@IL&*S}l-97Ezy=m@{_|>>$$m_&#N8Xkl z`MqM#9_wCipo`Vq)AqR0UY~v3?PFZ-!{u#pp8L4QFJ7PB=9PcBz3%dT%nP|AFIWCs z#I0KvX1lKwwd;`6sza;R_1zaXa&pW4zg@dF_3L+N)4D@Wefu>kI zJyPZMTG`S&vBJUc^~PQecgq>ydc~&D4gdc3&%dFDY5hVgcb=G^W6NvU^H@r#=dtQZ zJ5Ma}^7BXM?>w$wY+)W5oWEaSd|9B$yAP75t13Ohe;Ze`cTrat?W?eU1dC5&Q>$ut4{SEY*wcTvvB{$Qopyjq`8hf9GYY8}IvL4lL^ik= zFd=7$?GJG#g!I#?64GB&LI!9`$T^x4GEh@O25CyjU`+`bqA4LmH6>)2CPL2DM#yk& zgpANe$a&fbIbRzg7ic47q&7k>)JDif+6c+hM#v~_gyd@@WVALy#%LpCtTsXlv=K5+ z8zJMh5i&s=ArrL`GD#aD7i$MX&h)=`*MI5`cSDnWRv=`YyM;=g95Fd2WLnt%fNw&` zbe$?8MVb;)tSKQSni4WYQ$l8HO2{Re5;99uLS}19$Q(_CT&j(bx!MT1OdBDWYa?Wy zHbUlWBV>U#Laxw8$U<#|EYe2EmD&ioN*f_pYa`?uZG>E_jgZCK2)RxhAxpFoa=kV} zmTDtpnKnXh&<=!5_3h89rZ#h*aFPoHAtxM-2D5rHPO=+6Y;zjgY&w5wcDjA@^t_WW6>*?$t)f z25p4gr;U*NwGr}wHbNfMM#x5Oggm5;kcYJq@`yGpwNi z-O){cG7vJ-?vs2RF*zpWv#|ZpNJ7W~ohl)pYf8u$ni6tQQ$oJfl#oN367rR%gnX?j zA>U|9$hVpZ`A!=l-)ke}ur@+|&_>9Q+6XzKjgX_-2>D4HA;+{4^0PKVe$htAaczYB zs*RA}v=MSb8zH}IBjgWlg#4+EkiWDM^0ziZ{?SIrzuJM2Py7;h{ip7+`yQVrghYS0 z+Y|Qb+FeF8th)_}lI zu$@HUC)gSi_zAW~1P3G|IXNlhKjnZ#U$?s_ekf4%o850YITSHorl?6MY(J8gP}G$3 zrKlNOikh>fs0CY!TC$}mn=M5-Y$?iROHnJf6t!lfs0{%{Z3!r9M?g_~0*X2iP}Grt zqD}-9okl=WX99}45KweF0YzO2DC$N)QFj80dJs_5lYpXL1Qhiqpr{W4MQ0FD)R%yw zGYNsBQ{B(7xUY6a*Vs)_V=4N|NSzgmm@iW_AQZMAX-p_Ohx4UqAX|zCv88A*TZ)FT zrD!NyiiWYJ=v=lG4QETy2sVn&BcSMf0*WpmplBokMHdoKbP)kXc?1-VBA_UrfTGa^ z6pbOEXe(If(jE+(L8G66+X2q>CL2o&`T`F$La=yo@g z`%6(LBUR}B$clY6)hQ|th3!XT6N*YWUy5e1rD!HwiY{SG(JZzU&1Or{9JUl)%9f(J zY$>{ojiSp5D4It=(R>1m77$Q$1p!412`E}bK+%;16kSC?(bWVLT|+?8wFDF`CZOm# z0*aOpP;@;3MN0`NT1G(84FnV|C!pv?0*Y=T1d67I{3Q-Zw4-~Zom?bEk0%~yg(Bw5 z6s-(}?MJE;if-e4DO$yrqTAV0w3;nNcd(`CPPP=?#g?KqY$;mHmZH1aC|XBA(LDqd zttX)9UIL0X5Kwd<0Y&!{Q1k!+MGq2Cw2^?KhX^Qon1G^32q@Y_K+$FbiXJ7P=rIC{ zwh&OXm4Kqh2`Jh|K+zL~K+&xs|6KT{h3%3(b{%f^o$h!VE3*+4MohCDf%K5w!hLLq39szOVO8XDLTZKqOaIe z^fgzrFRAoVetP2jQ6U0~k_dsK z10nw+2PAsPeakfYb16Dvw?%$Z#C(~eNK)ATN|1!26wa5TRJIgF*;16omZEgF6lJib zD3dKkF}4)N*;16nMo~oqiYgIMRGEOHDg+c&C7`Gp0Y%jbD5^m~QB4AhY7tOWn}DJ^ z1QgXJpr{@JMfC|NYCu5INdy!%B%r7f0YxVhxGg$`fTB|gfueAde~$waz1F^m`D3>iot=Ll3nk_|b*izJ%Ek*6v zC~8kYQ3nEwIucOSiGZTh2q@}IKv5S0icTk>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1) z^&z0>3<8S!5>Rv|0YzsKP;@o{Mg0hYqNYjycMeE2$NgEIMcDH@a% zw!e}naa%N)^QCAATZ)FVrDzyiiq2(A(QvjDjbKaBd2A^+DFhTv zC7`H~fTC#x6ip`tiq1*$a~zQ9EW0flC`HrkGg?tn#C(~enMq;$E3FcWF5!GBn#Go) z*=#AA!3~Fg*_ViBNYNgeP;?&wMfVd>^Z)@x4-!zck$|Fy2q=1(fTBkTDB46o z(PjdQ9wngYF#?LV5Ky$0fTG6^J(CnMU#4hBQrP}Vy~J(N^PDe5FR-QPMYa^}WJ}RYY$wrWj+HKL7QuMox3Vy_VnWCs4 zw!hLdp(u^>r6`>(MHy@<%4ADXj4efRwiIQtrKloXiYl?Cs4^QxRR}1mNycKv6vcis}6 zY$qIPU4YR{IU4s0pv$VO2o0*X!}pr|teMO_FeI-P)`t^^cyBcP}| z0YyCsDC$W-Q7;0DdJ|C8hk&9p2q@}HK+%~56rDvt(b)tP^&_CDKLJGp2q-#-5GZQl z`+FUb=rX%2)KZF$*lp23KVrU2(NI5Zf2D9j(J;=JqI20&G@LC(BiK@O9$SjeXG_rq zY$+PamZA&UQgjg;MR^1ijUu2ZpMav#1Qd-SplB=sMFj*DjU%9FJOM=$2q>CJK+z-u ziY_LgXfgpsQwS)UN6kSU|(P9FMt|Opm2?0gd6Hv62fTCpt6x~2T(Q*QcZX}@S zCIX6XCZOmR0*Y=WplAgFMJov?x{VMhy2STKIUv!C?6zo@6b-P?Xsi5)`7%X!`eFMk z%@d05;(RGu!{%Ek*0tQgjbniq^BG=w7xIZD32$eQXrnPe9QF1Qb0;K+#45 ziXI}M=wSki9wDG;69Gk=2`GA$fTG6;DB40m(N+SA9w(q^8v#X65K#0a0Yy&{Q1mnb zMb8jWw4H#WX9$5|D-}f(YKs0Mc=Wd=zF#l9cD|>4{Ry=ku60> z*iv+qEk!@ErRW$NML!cz^a}w+#|bFN#>`XE#Gokk) zNKqh!4ubS5y$A{#0)!?IAOQhUKtK_ZBA}=!V8eod73`>}sHiA*QBcH+iUq~W{eEUY z?*xD6oOSOXXRVvHbmw^|ds61bWG0~yQ1k}@MSl`d^cMj|e-lvj4*^C05>RxCfFdtR z58F``BA}=g0YzZ~ijoK@@(CzPCZH%nKv4=IQ1oRu+|&VycCl|)e;%q6(VoOnJwiK0NOHo<26qRF3QF*o$RbZp2A^}B}2q>yd zKv5L}imDP&RE>b5>I4+kAfTuw0Y$Y4C_00HqS^!$)ghqhOahAP5>Ql+fTH>Y6g42A z=qv(?&L*I!Apu2=2!W!sr0{G9Bzm#k7NsWzkMuvbd)JMVBIe5!HBItw>Lf+YIA4mI zv!$p7TZ&q;rKlBKidwU!s0~|++OnnS9JUm-W22}&0Y&E$P}G5dqK*Uo zBDNG=%$A~DwiJzGOHm#hMWYEQ8bd(QSOSXj2`CyzK+$*tiY5?HG?9R!Ndy#KLO{`E z0*a;(P&Ac*q5=YnrV&syoq(bl1QZn#P*g-f(M$r0W)Vdv!!SOTZ$I4rRYkw6fI&)(PFj~En!R1 zRcsVpO+e970*bC7plBHZMb{Egw48vV>j)@XK|s+;0*Y1uHKnN7gO$zsRK%({S_g!BmMgQ10vTsd_m@iYb zImx$wk}RRd;0^^o1|#2eMNgdDPq1%(Mw6b{gZYHMK5!{ z6zye8(JO2zdX+6jud$_QA6trEXG_r=Y$~_CA)x3}0*Ve1P;{7pqR$8@`ka8GBLozEK|s+_ z0*byQ1d8?~h2L{PqTB3?*o#uM%^vB0l@u{wrs%sQ-~LI&grZ}dFGb(8rRWE?6#dAS zqT_5S`iU(?KeMIi7q%4r%9f%NY!v-QK+*366rCiX=nn#l{v@F2F9M4GCZOma0*d}6 zpy(6g{$^; ziniESv~Q&-Vm}T^_ao-Z6vcht{z=V*qAbprqS9Y1mZFMm zDXPSlqRMO(RUx3LDgi~+2q>yfKv4|>ifR&2REvP3GYBZEO+Zl{0*cNgpr|eZMfC_M zs!u>s0|JW9BB1DO0*V?EP}GQkqQ(RiWfM@;gb*mo^uwbakZ5)Leb+HRc%<*y4O5OE zF<+*rh40%x$(m5qlJljg6lUO z(Le%<1`$v+n1G@o1QZP=1d5vZ;d>mAXgj+@-CT-x**M>im@iXwq3_#2>6=hAg7c+l zBwLCuVoTA*Y$?iROVKE{6y>p{Xf#`j#;~PmEE`4n1Qd-UplCb+MH2`pnn*y=Bm#;q zA)sh70Yy^?D4I$@Q2_x((+DVwqHEYFT1G(8wFDF`C!pv$0*Y1;P_&YOqE!SGttO!8dIE~p5Ky$1 zfTDE-6x~2T(TxNYttX)9CIX6XCZOmR0*W>eP;@H+MYj=9w2=@fy4(*pcR-?f_OR>< zDf-rKi#GWY^JR+e^nLp$#S@C|;(RH(n=M6K*iv*4TZ-;wOVNF7DY~C6MO)cY^Z;9m zwy{yPoq(bp1Qb0;K+!`46g^Bp(IW&DJxV~)V+0iKB%o*)0Y#4!Q1k==MNbk?^b`R_ zPZLn|3;{*Y5>T|8fTHIJD0-fNq8A7#+CvBw-R_6yIv~*%_Fcz2q-ei;S<;Js#C(~e zSA5_8N&1AMS2W79VDRW69S4pC7|dK0Y!%iDEf?mqR$B^Izm9v7X%a? zC7|d_0*byOpy+D?ioPKPieC1^yB(0I`-d64q`gw~o00m~kC-o0^n>qzHd2ayROVO`vDLTQHqTkq3^gCOMPO?$-2LVNY5>WIP0Y!fkQ1lN0MgI~| zbc%o?FIf-UQ4}Jes1yN3VFHSh2q^LiC`u-vC_+F{3IRo_1QbOHC`u!sD4l?!3<8QW z34x+xemMCer^tTpn)JOC{bLXNW62ToWs1rq`}K0As4VA8Q8~60m1j#)1-2AbWJ^&c zwiH!nOHmcJ6jfzQQ8hM-suNIDgMgx%1QgXGpy&(&ifR*3REL0~GYKfFOF&UQ0*dMr zP}G2cqO%AnI-7u^h6EHfBA}=-0Y%va6g45BD2ITerUVoOpk|#xNIA4m|vZd%8wiLBvOHq5a6rIbKq7G~+>d2O&PHZXa z%tlcc0*bm4P}GfpqV5C~^&p_ACjmvh2q@}JK+$;w6!jsXs4oFU{Rk-PPe9QC0*VF_ zP&9~uqQL|d4I!XtC;>(16HqjafTH1qKvB!&@bwNz^alGP)=G-rwI7FEkQ^~zrs$$% z|KTxGbTQ{kQ7&7GMzN(Rk1a)`*-|uyEk$G5Qk2h@qH$~~8qY@21OkdC5>PaWfTBwX zD4I+_(G&uTrV>z8KtRzn0*a;+P&9*pqCx_SiU=s0NkGvo0*WprplCJ$MRN!!noB^@ zWdsz>BcSMVLZE0wa`*!WB)Zdnf6+)Oy4Aj-U6C9yU#95FWdDzRDO$w&QnZ*YMN8OH zbQN2Qu4YToQnnOb!{yEk(=OD7ub-q7?)btt6mm6#+%72`IXrfTA@76s;wo zXdMAXHxN*CBLPM02`IXWfTEiTD7uA!q74KT-AX{wZ3Gl;B%o*$0Y#e$D7u{xC|Zyl zu0GBw`oV6C7D`ce;sIN7#C(~eEy;d|2~u{rEk*aUrD!W#iXLD~(Kfae zZD&i-4z?6M$VSma1Qb0?K+z)v6g^5n(PIP@?IfUR7Xd|&6HxR70Yy&|Q1lc5MNbn@ z^b7$-&k|6yn}DL{2q=1`VM+hkTf`Fo<1QdNq zK+#tO6n#xV(KiGXeM>;mcLWq2BLs?GO%C7ZfJ8sGuV}AHQFnXT|9x`Ae3_!3lKs~v zOVQ7qFGatwrRZ0-6rEs8(Qj-i`kgIBC)rZ;2V08%WJ}RsY!v-XK+!)06#Yv;(J2Co zyoesQqbNi`Q7Hn7!UPm05m4k4P?StSQG|e^6atD;2`GvZP?SbMQ91!d83Yt%5>ON) zpeRm2Q5GRk^kZ`PxC0XX)^2`|OVRUo@49p(V!ljK`G}uYAVn28Uy3TSrKl2HiYl|E zs0v$(ss z&LW`bYyyfJ5>V8LfTG3(6lD`o)P#Vd90H1(5>V8PfTHFE6ty6rs3jp#R5lWB>3~GL z+avvQk>HVjS$m}4DiSeYrs$lAKWw@bwc~s#YR{IUbJ(RlCwr z!2}cyA)sg|0Y&E%P&AByqTvJ-T|hw5g#;9hAOwoqM8fkNkmy%#CbgBKU3ObEG7>Rg zrf5{ezqL?`@;G0LMzf`83|orEvZW}WEk)zlQZ$||MHARkG?6Vulh`P_gn**S1Qbmn zplB)qMFj*DO(URaIsrv92q-Efps0v|qL~B~%_5-aQUZ!*6HqjVfTFns6kSF@(L4f* zE+?Sq3IdAe6Hv5(5GcAh5`NwRiFUGwWw}yxo_%>+7>SrKQ?w-FA94RsZQ|!>S8=`+ zUCoxFrEDp>hAlWIM0Yy&}Q1lD| zMb8pYw3~pU=Ljfzo`9kk2q@Y^K+%f?6um@1(aQuB?Iob-6#|N0B?OA@iG=$(AkpLY zXJhY`qD6LF^jaihzD&`Z5x-!r6z%7HDSC@7MQ^jE=m1-a-eF78yKE_Xk1a*-v!&<* zwiJEHM$tzE6n#uU(Ln-=J|Up!Qv!+(5m0oPfTGU`DEgd$q9X(peL+CcQ38s-B%tUk z0*bySpy(R{ioPYF=sN<6juBAwJpn~O5K#0ZAyD*sB)rxEiC$`Vh2D^&XYID=cqC%J zOwq3q|Iv9;bb|Ax=r^_${mz!6lWZyagDpjWvZd%RwiNx%mZE>yQuHqyMW+ZT@>2A$ z9YrAmib@es6egf3iGU)XfTCmqiXsFQr4Ue*NJU(LCILlt2`H*ZKv8`HiW(45bQS?c zXA@A=kbt5_1QazUpeUPwq9z0s4E{Rt=hAkpy#r@a(y zvfHBEl!*BDQpx? zC7`H)fTC#x6ip|fXa)gAg#;885l}RffTCFh6kSR{(QE>W<`7Ucmw=+n2q>CIK+)v{ z6kS0;(R>1m77$Rhkbt5q2`E}b2o&X|gts~%(R8~jG+K&U8L7o75%Xn=mZtcxFOi~a zIA4mEv8Cu*wiGRAOVM>~DO$mnqLpkZTE&*4)odxco{ge41Qe|$plBTdMK=&obRz*p z>j@~jiGZS;2`IXSfT9fq6x~Wd(QO12Z6u&*69Gk=2`IXqfTBAHD7uq?qPqwvx|@Ka zEd&(ZLkJXIl@k8h0g3LkADvw-MfHr-y(tm%Wr`k1@yjfgqHUZnMcdg@w1X{053;4` zA+{7f%$A}@*i!T;TZ$fIOVLg?igpoD^f&=UPY_V_BmqTF5m59r0Y%RcQ1mPTMY{0Y$G90!8_7&}ol!*BpiuR|3uW&%zPthElx1{I^`$qOJ zDG~E!ihfV=H!hc=lbkO_f3T(KPqq~O#g?MK*;4cmTZ;Z=OVKH|6nUw7+%82SHi}9S zP!uMhD2ad~pMaud0*WF86r~VQluAHRlz^f%0*cZJD9Rw9D3gGq7y(6b0*bN-C@M`r zQ5gb?$`Vjij)0=_1Qb;u1d2|ig!ecg(d+Ey=Qk;;Zlhvq#C(~es;U0b6;f1<^QEXd zTZ(G1rKl!bifXZ?=nS?L)n-dk9kvvm$(EwJY!uZapr}3pMGXijI*Wj!vk53_NI+2| z0*V?FP?SwTQ4<1+atJ7DNojG5My0E3FD_e@Xv8AXxTZ($H zrKl%cih8l7s5e`R&SRsf4*^Ae2`K7EKv91JiUtr+G?0LzK?D>HCZK2t0YyUzC_0~j zqG1FS4JV-J0s@LIB%o*n0YxJTD7uJ%qKgSA$|ay^6ahtfgg{Y;)bIcYBwAoMKOLp0 zTH*m)YQ%h*qH(GI^fgj6p7W(>0$YkEvZZJeTZ%4WOVMPu6is1E(Nwk+6|kjf8XHB^ z2`HLDKv5w9MMVS@%_N{`76C<<5>PaofTB4B6wM`|=rRI|<`GbIIRQmi5KuIqfT9Hi z6fGp6=t=^L77}Fs=src z6fNg`DY}j=MJw1+w301FtJqSsnk_}wv!!SaTZ-1QrDz=+MK=&obRz*p>j@~jiGZS; z2`IXSfT9fq6x~Wd(QO12Z6u&*69Gk=2`IXqfTBAHD7uq?qPqwvx|@KaEd&(ZLqO5J z1QgvzK+*k#K+!d+;e!rHw40kr%cN+4J?!6_8Zlp{Xh*95&y7;_Am>ZbLu@H}m@P$* zu%+lxwiG?amZF_(DcZ%BqQ}`%^aLA4PZCh{6ahs~6HxRF0Y%ReP_&zXqUQ)GdY*uy z7YHcYLqO4s1QfkQK+($t6zwIT=oJErUL~ODH3EwE5m59x0Yz^RQ1m7NMf(YXqHU?+ zGuAsr+wB{T+ok9udyMv0YQ%h*qIXmME;mcjdz>#t@3W=o1GW@>$d;my*i!T{TZ#^{ zrRWp36n)B;qC;#H9VVdYGXjb}C!pvE0YzUBP;``lqAv+3`ig*}uL&snhJd1P2`KuG zfTCjr6n#%X(GLU^{YXI3aRQ2dBB1DJ0*Zbipy*cuicSy$MF&#D6C9A}ID_+!6dkf3 z&Hk1eF<++W&s6`K4N~+M=S$JwY$^JOEk*ybrRWq}ioB>Exl2)qEk&i+QWR!OQ4$+P zJ^@9^1QbOGC`uuqD3ySsC;>%j1QewcP?SMHQ6>RJF#?L>1QcZvP*j?LqA~;&l_j94 z905h;2`H*SKv6{kiYgIMRGAPcI++^Y=72KgUSZI+^LoG(S)*;3SlEk!-qQq+qr zMZMWlbRJuZ`mm*_FI$TGu~F2YfT95e6b&SxXb=HKg9#`aLO{__0*cNjplBEYMZ*aw zx`2S93kfJ1K|s++0*Wpopy*-(igF1k8bv@+9sxz82`CyvK+#x2pr~^++|~h!+Mmcz z>LNuC*~pJZ%$F&e81+ZoAw`ooUy3eaOVMPu6is1E(Nwk+6|kjf8e58{v!!STTZ#(V zC@LbLXeI$gvj`}?Fy%LypDf`Fp=1QabGplBfhMOP9~ zw1|MB#RL>BA)x3g0*bCCplB%pMb{7lMdPF41rA8`HM{wlAVqK5oup;ai1{)_E2949 zyQF9(=S$HlwiK;qOVRagDO$spqP1)(TE~{68`x5GBU_5rvr%*t0Yx_xP;?6cMH>hx zx|M*U+XyJyNI=mh0*W>hP;@&1MRyQTbSD8tcM(u@HvvUk2q?OTfTDW|D7ue;qWcLb z+Dbst0|XRpBLs?;N5d~UAkm@rjmGPwsDVAw-yV&aFH`hz)cc>;=FAfRXu0Yxto zQ1lW3MK2Rjw3mRQR|qJ2m4Kqx2q@Y|K+)?26um(}(VGMm?I)nAG4+CAX|z)VN21cY$-a# zmZHOKDf)~pMW3@#bcBGSF9;|)N4{|`FW$aYCmZExWDXPzwq6Ta!I*TnuXS1cKAsa=F2qz2qV8M zfTGTXKvB)K@TU$)w2$2{s+ATz(tp5ii@Kym%$F(Zk>;P;Aw@koUy6FMrKmSsiq2z8 zQ6IJx^<_&@KeiP0XG_rlwiFFyqi7HTMS}?_8bUzPPy&k1C!lB;0Y$?JD7t`vq6-Nq z8bLtONCJv3BB1DE0*Z18C>ljTQ62$BqX{S)LqO430*dkpC>lpV(Rf0js9RdN&Vx=- zdHV@ScPU!yUY0Z=En>b*(d0D0+rv^ch4ZCoDqD&Q*itl&Ek)DWQZ$1tMTKlBDq>5~ zOtuuwVx#C%0*Yo6P&9{tqPYYVT}D9BJOYX?C!pvG0*dAnP_%%6qJ;z$T}eREA_9sQ z6Hv5-fTF7iD7u<}qNM~BT|+?8G6IUOC7@_IAy70aEj-BqiB7Q}<6k00i|pR@b!idv zWr|j(`PV)wMb~q_6s=)P(OR|?tz%2k4Qwg8ku62**-~^9TZ(RGOVKTC6m1}&=vD%X zZX=**BLPL52q@Z2K+)|46x~5U(VYYo-9py)mVitZ<%Xe$9l z4-inajew%<1QhKcpy)wDplD@Uc!vWL{nCB{vPz0Z+gG%Q(jw-|6g`&azqM0}c5=QH z?P5#O<7_Ei(ZxK-RHUUKk2q=1ofTDK^ zD0+_&D0(C<{F?(3ZDw#Dm7?u-Tl9Wf#C(~ekJJ1LPe{>0&X=N3*i!TMHsFW6Fal#QY<2`KuCfTFJnDEfwgqHhT(`i_92V+0g^Pe9QR1Qh*9 zK+$mmihd%X=w||oej%XfR|1Mo5K#0R0Y$$PP;`=jqCW^I`jdd7zX*Y%57WZ!9FXWS zyLbJO6b&;{f2T#vmnrhn{fnNGqENaX$xBfwwiJcgQk2A&BA+cq$!sZ#u%#%4Ek&tp zDT=aDltw^NIsru)1QcZwP!uDeC{93876C=22`DNrtW1)wbCQz%M_iN z?%(l@6xHQ?DXPboqWWwpYQUDFv)EE}Hd~4svZbgITZ$U9r6`+?q9z0sXfTD8%wiNYeOVI$f6b)oc(IB=I4Q5Nx5H^a25>RwL0Y$?IC>l;c(FFt)T}VLD2m*>m z5>Rvz0Yw)RP?SqR(I^6n@(3szO+e8Y0*b~GP?S$V(KrH%#uHF9fqie|H=Xbu}ia|tNAjDVtf1QcCPK+zQh6wN1~XaNC53kfK?l7ON`1QabMplAsJ zMOP6}bTt7*O9?2thJd1F1QcCMK+$pnimoG|Xaxa9D+z(3De2)M4oLJOyF)!yiVAG3 zN{^T?Q?xeSpZTH`t>b(tx`8c4H?pN@JzI)yVoTA@Y$>{hEkzsHQgka@if&`0Xd?kd zn+Pb{OhD1?1QgvtK+&B96x~HY(cJ_TZ6ToO9s-K)C7|d&0*dY@plB-rMGp{Aw2gqG z?F1Ci(ZxK-RHUUKk2q=1ofTDK^D0+{8qW1|X z`hb9<4+(*yo$2Aj4oI|@-Tds5qU!EtNgt(0%$F(pG~ExqDn*AlUy2U1rRX!Z6n)N? zq9bf6`hqP*N7+*JC0mNVVoTB2Y!rP%K+(4Z6n#fP(J=ywz9*pQ2Lg(IB%tUx0YyI% zQ1mkaMZXYG^eX{HCkQC|jew%x2`D;AK+zur6#Yp+(O(1<{Y^m8KLiy0O9&JlOb^#} zK%%wnyN;hoQ6GDxe=0pBBcP}}0Yw!ED5^+6Q6&P3Dicst zg@B@}1Qb;xpr|?lMKuU0s!2dmEdq+pAfTu=Ay5>`2v2rEqR$(gQW?Qxv@-5xNp&(J z=F1e-&+xB%Ly8)3zHW=oVoTB4Y$ESpDjhh*eDuKK+y#R6kSL_(Fg*HMiNkT z5dlRP6Ht^(K+z}yit-338cjga7y^pM5>S*+K+!k?ipCRAG=YGki3Ai)BB1CJ0*WRR zP&9=QC^|1Ae9{4l-ek8$eWb|l4kb;^h?p-^G$X^WbU=y zie|H=XbxM7=CY;eGPV@WW25MD0*bC6plCh;MGFWhT1Y_Al>`(mBA{q70Yys)D7uP( zqN@ogT1r6CH3SqbBcSM70*aOsP;?yuMJos>T1i0BDgugD6Hs(LAy70eBYds{5-n@r zb(}6mgY33wO-96gnW7sr{M>h?Xg%jk(M@bAx|uCSx3HyX16zu2WlPa*Y$@8vmZD8; zDca0N(d`5j-9bRnodgu!ML^Nr1Qcx{py(a~itZ(#=sp69?kAvVD*;6h5Ky#@fTHaL z6zw3O=s^OC9wMOVVFHRCA)x3{0*W3ZplBx{P_!;1yx0MW9WIJ0Yx7ZP;`(GD0(6z{Hg;IJ!&^UPfAg0x*MNlM9h~d`Ygl$?n5d1ob#pV z2wRH2U`x?awiJEImZGoNQuH-jioRh>(YI_V`i_mFV+0g^Pe9QR1Qh*9K+$mmihd%X z=w||oej%XfR|1Mo5K#0R0Y$$PP;`=jqCW^I`jdd7zX&M$n}DK!2q^lOfTB|b6nU9? zV2+{?Ay9NEBOL$8DSFm!iw>j6NR`Trm@iY5oayHrl%fddOHm42ic;B96lF_M8e59e z*;16jmZD6y6vfz56lbF-i-4li1QeAapr|YXMdb)6Do;RB1pQl$fTGF-6jdRh zs44+P)d(o6PC!u&0*Y!9P*jV6qB966s!c#q9RiBZB%r7+AyAZ*89v_uiSDzX>HC?% zBYk&I+dW{*jF>M|batkH>8DcEkn^Re5nGBHv!y7TEk#Y(Qk27%qNZ#qYQ~nL=4>fy z!A4O_0*YD@P}G`$qBaB+wI!hF90H2k5m3~gfTD8=DC$5!QAYxbIuTIRnSi1$1Qc~8 zpr{)GMcoM~>OnwJPXda15m3~dfTHsVfuaVP;SCN*^b`B8<5^PluaWAL88Kg`Xh5d_ z^kFF)$oWzCJK+z-uiY_6bXfgpsQwS)U zNQvp8RhE@ey6Y_=55 zVN20mwiI2)mZEuVDY~33MOUz;Xg(W73kWD$NI=n*1QabIplC4xMN0@Mx{83Js|hGt zNP;@;3MQaEsT1!CDIzphRFf&}= z0f}z0+oB?Fi|k?l4Ve-1Wr}Xj^m`qZqFXp$iZ-yN=vKBA-Nu%pjch5}#FnDXY$>{( zEk$>*rRYvJitZwy=xzdvwh&Ns4*^B@5>Rv>0Y&!{P_&hRq6Y{l+D1Upb^?la5K#0W z0YwiHQ1mbXMUN0r^e6#Ej}cI`lYpXK1Qb0^K+zL~K+*cl@KgsRy1>5cc#{;pW4A?5 zW=71HDS9^3U-^|3?dE(bdX6nc&$FfI1-2CJVN21AY$Y#h#vm@iZGMW+AmH&S$z z^QGuZwiJEEmZGoOQuGa5ioRt_(RXYqI>wfw@7YrH0~RxUfTEuWDEgUzqF)Fo z`jvp969g3fMnKW;1QeYlpy&?*ivA>^=r00_{wAR49|DU0C7|dO0YzR+58F``BA}=g z0YzZ~ijoL{qR%tKe>x!1Pwa1dI3h*sOpzapm@iY58uP0hlcFf+OHmqIiqhFql);vw zOtuuo*isZ{OHmeEib}Jks0{cEkzfyrDz0Oibk@f=pr_XE+(KTmw=*C1Qg{F zP&Ar=qA>&%jU}KcpMauq1Qd-YplAXCMH2}qnnXa+B?J^rCZK2v0Yy^@C@LVJXc_@U z(+Mb=K|oOj{CPS+Q{G zU!0=b?1vtgN>N37*nd+jV!lk#tuepZ2`Rdb^QCAbTZ%TZrD!u-if(61(H(3lx|1zM zcd@1DZnhL{VWa3C0*dY>py)mVitZ<%Xe$9l4-inajew%<1QhKcpy)vYiXI}M=wSki z9wDIUQ38q{BcNy}0Y$qAD0-ZLq9+I_dXj*mrwAx|nh+?uB^Dm;fJEEdZP5lPT4-P1 zo{2@wmnnKa=Fj?i zMQ;#L^dUOVM$*6#c|T(a!`F{X#&|uLKmGAfV_s z0*Zbopy(t4MSl=b^d|vDe-TjhHvvWe5K#0l0Y#?>DDvWZ*p8wQ0Y#+Jm^?kAR~31QazOpy(_Diq0mWs39Rx6pe?^azLVo zQXQPMc<@MnuYGxI6pxrMQPbLR zF9M2s6Hs&>0Y!ZXDC$c}inSi1x1Qbmrps0X=qG<#aO(&pe z1_4Ed1QZn!P&AW(qFIDM(U5rfF$W~N%YJk=REo;mBmGO`5%Xn=E{pr`my)7+oG(R} zv!&jT>j@}YLqO450*clVP;>(UMK=;qw4Q*Xn+PbnnSi2O z2!WzG@$lacNOYQgqj9bjm9pES4e^NiGDVx>el=f;Hgmod-OiSxJJ?cmCtHf{VoTB8 zY$@8pmZE#uQgkm{itb~h=zao#{Dr7DSC{(AOS_65K#0f z0Y!%hC^}3)(Psn{eNI5p5dw<7AfV_dAyD)}JiOEaiRRdC(H<$SOVQ74Df)#iMZdC9bb^4Q-v}uBoq(c~ z1Qh*2K+&HB6#Yd&(cc6V{X;;}zXTMWBB032(!+KXg$O7rML?*%Ce=X99xRYv!$p4TZ$^OrKl1cMU@FCszN|fRRW5t5l~c}fT9`%6xAf4s1^Z5 zXAn?Sn}DJ^1QeY~Kv7)+is}(iRG)yN1_TtHML^Nn1QazSpr{c6MU4q4$|eMgGP1&D z)19Id_Fc!!tl*LUX1gtFk`*yurl@(A-@^ShS&7GJEjV9_TC%066V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZn zqTU1)oku`X9|DT{5>V8SfTI2c6b&GtXdnSag9s=ZOhC~PLZGN=R`@~(BwE8BqcxMF zruMLZXja60nW77_{LA7}bRp+U(FnE_jbuyFMQka$m@P%QY$+PWmZChi6pdy}(HJ(0 z#u8AJPe9Q)0*b~HP&9#nqKO0)O(LM^5(0`Q6HqjTfTF1c6crFqG>w3w=>!zbAfTv_ zfTAJ-ie?f}G>d?uO9?2NO+e8cLZE0^R(O*G5 zqWPRJMGM$cw2&=DSF)vO5nGBDv!!SWTZ*n?OVQPADO$=#(KQ4VEhC`lS^|oe6Hs&= z0YxhaC|XHC(JBIpRufQkJpn~)2q;=hK+!q^if$mF=tcsH))P>469Gjx6Hs&u0Yw`K zD7uw^qT2|8qIp^2FCCC*d%O9$T#A0Tu`w%RzD&^_S$?FP6y3@BQgjzvitc7h(H6E8 z-NTlmd)ZQSA6ts2@jl+HQ;XWJS!EDcYOm_pKmBuW-H;y~>uN*Vt0Dk1a*7v!&<_wiLa|mZJS^ zDSC@7MQ^iFbbx@OcL*qYmw=-82q=1=fT9lwDEg3qqK^nD`j~*Cg9H?PLO{`{1QZ=2 zpy)6GMV}E+^f>`VM+hkTf`Fo<1QdNqK+#tO6n#wy6up!cp5cH*PuL^6#YX$(Z2)~og$#fE3Jp^C<+l!REmJ2FabqL1QhuM6eSZ-6d|A} zg@B?|0*ayp6r~YRlukfV1|d-NT~>IP0}?&U{v^>cDXM2*(K1U%%$F%DUE2S!iWHUM zd?_l+mZEZODJsvFq6%y&s>qh2N^B{r%$A}mY$>YBMo~2aimDS(RD*z`ngkTpBB1CD z0*Y!AP*jJ2qB997s!KpoJpzjA6HwHEfTFVqC_0;fqJ{(%H6oy>F#$!{1QazPpeToc zqNapEQM`2cUk4<5mwk&Ut90;4e}&x^H7gx4U#6&4X}?BwDQeC6Qq+bmMQzzqbPijJ z+OegmJzI*-WlK>9wiI<_OHn5_iaHZe)P;bet^^cyBcP}|0YyCsDC$W-Q7;0DdJ|A| z9sxyt2q@}HKv6#eiuw~!G=PAjfdmu{BA{q60YyUyC>lyY(fI@v4I>1KT9giVbwHxc z4Nglbs%p1I!%IiZmnj-q+Rv{kMHg|t6kW`gqFlBVjbckt9$Sh=v!!SZTZ+cAr6`{* zMdR2g8c#sc1OkdC5>PaWfTBwXD4I+_(G&uTrV>z8KtRzn0*a;+P&9*pqCx_SiU=s0 zNkGvo0*WprplCJ$MRN!!noB^@Wdsz>BLs>rEFE6vfJEoo@4Fr$MYr3Rx64aM%$F%z zSlYk;3@N&j^QCAJTZ$I5rDzFTimqZy(ba4zTFRE9YuHk>j4egivQf00fTHUNC|W^4 z(Mke}RuNFNnt-C~2`E}aK+#$Piq;WObOQlJHxf{^o`9m82q?OlfTCLnDB3_k(X9j& z-9|vsMgod95m2<55Ga~oI=tTjiT>zj(gGV zdG%wzRQ9}vu{PB_uSslv4bN*Hd$E@1wT`9L@w|4ifptBvW9-KIp4T<@$yuJ)GgiBi z=kGoPtThdd$70XEr|Wz$MY7)+V}UorLjc=J#TsJmBF63Di%B6 z^VY_O4)?tEv0EMta_+SiM}&yE8T=&-3nyJv_$qw#NR*_q-jk4ih}@k=T++ zp0_LZ+GNjrDwb8?dAno7rhDF=*sX=0w>NfVrswU8HJI&r`(p)jJ@1{^qw_rPgV=N*e(u*~z0$2KnaykBESS9spZ*x9Q+@9+5Z zHSY5titk+Ku7FVdpBvpZ5Q=xX*e7!YSuLrw||zZXDDv}u27#){F~kGItj(?U-lRhirYWUFgz5uzgvG~C~ki_`lwLc z{&wrJp}76^#1les`}<`lhvN1ZgiZ^^?QeK23dQZO=$jpi+uyM^FBG@GBx^w^Zhy}KP-fxnD-^lkENrZAh&b z^2&T2wpwkaD~T7mW7+H6X`vRG*1WP#ofm4U(ZpWTO5;8|wRPsA#H&5%eocnj=p{Sc zMTOdGykzH`qw%_pb{Zo>ZnW1ZZ>S%A?Kx!waYI`e|tyY3XUL-AA8N z;XkjH>R#)#OO0y!!5c}_MY?GhnXZdWytL#ZGjx%9txR{4U-Ev$GTeJ-Z#kZL#`nA| zeI$A#r5lGjRN|eeS1Bu0I=N%T8#`CBx9I-)cV5z~OsNVxJG;+G+2*IUs_ufzU2~;V z6v}b0U*0|IK8^Nlg=Mams<^tdy9z2c_BvE*S7~Zy;=LNRKOgw*ikvk-ws=EKXtI9pOn|eKU zjJ)h|h10SNXN<|7ky|(>KX=-Uf};E}Mfqd1$IO^Bt*F4lnEbIbXXF>2_A+~Y_u6f; zr_Go+Wn$69S@~Y}gn}vg*?E)mXJda=QqtQESfoX zVnKFMLBZrP6Y?fbEzBN2W=wA0j49bUO>&#%Hf_>0CpV{w#YQeRnp!Y5zfpeP=!uPT znlx_K$X?voz4$*b%APoN%;cG4^RuVqjhQfU>i_TWM&X>o(?1jACuDb;F?Qy}sRdmM zX5=?2{#?v1nvwXF1fP)sGYTfT&v{|?;Awd?F6lmVYVHvCv5X%ud1hhmpiV9Ow)nqs zHOB$czhsTE+`+m4m&E#yq zbaKcq>kc)1->tH4mC5l-SI=&k*!EICxmMz}>{uqTvvq9Z?gE9%`Du2D`8Dm}UY?jW z{ZP}!rAj&SgSz#|?cSuPXUCk@O?u{z4xVkt6u;qCq-G`WK-1!Ppv!3&srR%gC$ubn ztu~2wZsyd&iQ}i{kFDvhs>GY?!aLZVOL5Qe@pdczfO6bBlX(3$?$vU0-Pz5W<_4FL zC!rvT!Q;lxK|rHbIO!C!6oT+oAZV{DYPnn2i#}2_>zm?NORss*OE_$ z`xNLE-Mbuo8r`J?&z$xywBl6v$xFP@ePVT9i{cA&?+7z`_NH=; zx_)s4Z_j-gI^STNc02cf>sNQz{LwSVd+sK2>iGQJ{HbFn=1t9=TrhQf@aEkW!8GW?uyn2=|JnbuKzjH zvv;Xx;(z}Ox}1`Cq_bSX&t0ki`K0FX=Je4Ozm0B*%a~-pf)X!kq6>1M_5O4&e$VXJ zaN?CZ6`!8d)e-14s7G-5#aI$=KJlx*_+oNOJmLpFIVC{d$Dub1ngkEKD0fp4yz?d6 zavZmyHQ|LN0CT!?<&?PN`f?vYa30Ut6_dD`D!FpqEtlSv9QVHPY);8%VqD9FE8@NhbdsqEe7Uc4x*T^6=(&>j06^|Dq?Z|# z#3$Qb1;H~V@Z3$3d#%KUCtl>PTb<>;yy&^&55%Dk&Ud%acH=lB_^jjv2YqcV(U4QZ zp_q4x0{8XXU4G$&f*D1{Unw0n-izQ$FTTEuzoxrigNawM>%=}NzG&v0CZOaR&ndae zb4spru8T_?K=zU%uU`}x5+IxB0 z&3ul|a93){=hr>gqu56YBriOX4=g5 zW85b!e|DoO&6>GTG-2kH(e5~IazS2EBX`HVy}MS%T5zv9ZrZFCjS8nV8k^J7mAn~a zCbW0=)MvGBG^OzrcVGYPv4zvl9yhIKqwzHx^>13Uk-Kx*evEqu8jYKhUs#woKEKiA z{Hf!MCbVzjQgD~1kzMI-*=?gnxGHc zH2$Byb_FU=`}$f;&(Td>X370T!KS#oc({vf{|jA!uSamN(H!JWdyr@-!s>dtB6Lk)iQ6@U2rYAZ&KX}d>yN%0LJcRWk( z9G2WSM0fF3UwqfI_&#Ov-N(~@8I}BED7o{;HC=LNulO1a?mv1xx^!t?X z&2Cdh=Z_uh?spI2(QM+^5|2_F{GWei*<s?prHfr#9|?dG=V?3uU`!{nm~8HtyT0S3fT~E7CVL98D>mR5nyDR3Th3 zR4G(BR3%h3RK3(0p~m)5|9?E4o|3$uPM!YZuss+&?J2BpHITygSn#x`uzMVsb=tOX zO1SSUC%%CZjL_VR%`E~^pj8+F|8KC$-lPjoC_C)l-h z99cKm6Lq}ZT>~|>E7V?p zu#U@H2m2-+-)LcnL1wFA=sDbcxR_zKd9rkU4s3)j!n7;ySKp8sjy?Mad#H{p1_t{U9p4!o?9X(pe15R&={Rb5u&3yF_l3cJSjS@{ zgZ+n&O>=|YLC4v7!Cs={GY-0aK3>x?XiFK|U?0)3YC*6Y z=s0?MunTm&r!d%$>iEOVVE?6K^Vz}fq~qMV!M<9@-SdL|x{k^7gIz|)J`00=fsWTN z3id`FKUfm%qdHb!8tk)m9J?&o({;RWd9Zitczi{$|IxAK>R@-#ao(C>U!&vm>w^8J zjw$PdT~5b-HwSx!j%zmrd$W!oxu1sF_4AdEH8%&lk&ff;2zH^4Tki_?<2wGlCD^BQ zY<*v_yXknv)?i<&jJt4tD6d;Mn$s;MhaQ1uq8sIvrnnIoJnuOn)`lm2@1mFW9*{u74xg zcj@@){$PKnW1R!R&e3twyTQIx#~tqn`)M72b3ga9>nHqCaBO!lIQG)<%1?v6QpdfA zgZ-|KnMZS(Y3zK-#~gI!I>^ZyO@7#%mbdkOaX_v-k$`^lv3 zA9bwnzV~grg^p7r!M;q#N8ArB?d8wu_^12nrR|9O<3o1r=zff8$G$pV<$j)NdyS6! z+z&Qwf2d<=_Y+RrHFO;Ae$;6@U&q_r&pd74uj3c)ho828((x?!Q&8KjbevW**q7`0 z*crioLC31@cNy60H_)+(9evO1pxxV!QP1nA<6!ksI!@7Xu8vphxK_u_I&RbPNgem< z_^yth>-eJ`-P=E@W7Pe8)84;K9V_TqMaN{jALCx%y^D!smX76gbax99y_SxN*H3Xj zFw}O3#LL~?oy4)w?gzQcb9YC)QZe__J$0{f;hZT&d86I2Xhv|Hz;o`gbdlHC9=v*u zM;8`)joriT#ugj@_xsL?KGwc1?7lNUuE3p=cs_6R=o$I5g0q6+e$saO%$s4~L)PU6 zukpW@$@X(HU7~x(yvAeP4|Ve0j}K0JtK(+mO>wW(X;9zBc|}DtCXSw2~n3e7Y?S~1^UmEz098Kx&Pc%@&EdIP2B7J&$rvrHJ*)SVJe?CtT+ij*u-CEw?Cte*|M5P!XT2i#UmfR(C!Xu-!s(Y6cb7NH z1-m?R#N`cf&vTA@)?4o`YwBr%XWdzrD=ckgK* zZyEP8KHk^d^X|i&<_?LchHXM#TZTLGw(Q8S6?^dn_j&_dtl*xvN3wQ#_IbC@@oAqf zZ&%xp*WERqxIDYfJN@-OaPQy8yplWedZ+)0xOwA(Z1;VlmaUsKZQZn4P4|tBCON15 zzh%qjHEXtR-mFE-n)Wm*I=@?=?!oUd2rf9}9;tG!-bEy?FVKP2I1T;B%c6N^u`_`XlZFH=h0( za=TP0+5Q%sQlXSZ?zX;EDgQ*o4v~2-h6~*rFV(lAd(7f~QtZbZp73gWt^SopB~s)c zcd?~X{L1c^ZK;&VP42Uml;qp@s!AnA?As~f%I?*}4a;bCqz0PR+-&Clrg_b(ZZ`Ll&ep8r zW(zN=p=M<_Te`ojPP3Amt-Pehnibt_?ImSvR&cY8`}6La<=xD2?^cd>Iot02YN}n< zwtL5#X_v9>-m~V~rER-+t%Y`$ZTG&l)Q;PB?_4YGm~HpowbstG?cTjM+8MUp``1=G z-R-9C{X0iH&9;00+G$5^yZ5iXcB*an{++9xV%xoc9ke61-TT*3JK45-|2k>=w%z;J zSv$$Ld;hvfBjh4&gj}qRkX&tqjM7F(o;E^8Ya?WgHbTZ~ zBP3rNA>*_WGF}@Y6SNUBQ5zwXv=MTNb|9oz_&ay~r*3mMG)cV!As4w@sHDjelVd`r z`Su%m6GEozR0)}(DItZL5>lioAu}~4WR|9cT&gJ{vo$4Tj;4gn)kMf;+6bAajgZT= z5psn#Lgs5DWPvt97HT8pN^OKJ(niQ)ZGqT-;uPGrnX-de=ni6u0ri5(Jl#p9BCFC|u3E8NLkWJbM*{qF_+qDsLhc-g))JDi% z+6cK@8zEb?5ps_pyjg-G;0Ug#2XBKNc}LCgcg<{s2Hi$dfu%LY~r;kf${zAHbVAmBjhb@guJbdkOSHXc}E)|?`k9DJ#B=%uZ@rov=Q>5HbOqq4utFq z4|Lam>M6VL@pvF)huwyJ95Fd2|3qA4L?XiCUYO$qr@ zQ$oJdl#s7ACFC1TgnX-wkngk+a!eZ`-)ke}2W^D>sEv^0+6ehc8zDbyBjo=f?yiHQ zy#Kgg?`E@E*g$pzv_O?Q6xRR^7FBZ z`8YZrsn%e}Bh^ZFJW{Qd9gkFNZO0?k%62?btk!o%2c%)jB?U8B~!6VhG zf=8+~3m&P~PVh*z_JT*Mbr3vKZ6U!U)fN^!Qmv!lk!qa;k5ua{c%<4Qf=8+?DtM&Y zVuDAiEiQPZ+7g0Csx2vaq*@ojBh{7?JW_3G!6Vg{5j;|DSs??`w!XeDU$`>^QeHBh zS_=7^qHnW1%Js|TONm!fv|_%P9(vZIXeGyoqLuAXw2B>yy4j(qyB&&p*rBMW9g2F{ zp{TbViu%|T^%W@UCs5R1plDTrq5%R$0|km!6DV3;plA(&qBRAI))FXMTcBtifucbI zMS}&3h6of56(|}eP&8biXkCG#^#qF67ix-D$R4YbeO9Y{dO8(#4MnRZQXAw;$yZXe zalV)yy4a#<6UT?5P3=&$nH`EYw?okub|@NYhoUX*P_&gDing{x(Ka?k+X@tICs4G# zK+z5YMLP->6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(Uof zxv-UHL+%>?`W!@#$Q2cPRQeeRTb9zLb0=MIYvi=|?xT zDEi3pq3B~f6n$ccqEGEm^qC!sKDR^B7j`K6(hfym*`erbo1$+7ioO*n`c9zedx4@K z1d4tXDEdjD=x2eVUj&MN6)5^mpy+pjqCW(R{uC(sOQ7g)fuer|ivATS`cI%JS2zD& zew&uBN96^I>V%r2_w$9FG9cxbvhP``{~#2-lg>qjx>E9$6qV|V=|_LGC~D>SP}JHE zMP)k_HQJ%5jU9^G+M%e)4n-9^6jkj|)NE7KPN1m0Kv4&QqJ;#C78WS#C{WZ%ps2Gz z(INsxiwYDiCQ!7vK+zHcMN0}4brC39N}ySXa0> z15%!oz9`X9SG%YGW;z#jtt%y8Nzp2G#YdJ3Mco`9in`mOsD~YjdfK6=mmP|F+o7nB z9g6zep{So7iu&6WttwD7K%i)#K+$RfMXL)Gtszjfra;kJ0!3>J6s;prG)SOmut3oe zfuf-TMZ*M&h6@y}D^RqaK+*aFMH>hdZ75JQLZ~TPsjl#42Bf?~_B}cED~F<;voCwr zZ&X)GzLKKN>Wb+{54D_&Hg|j|+QJS+BkfSMr5%d4vP03plGT<(KLag=>kQ&3pGWX)D?PWK+5COxoFc+v{QPIHlwbTd?iJD)D_c@u4+-V zr{hD>96J>4Wrw1@?NGFj9g6m~L(zVADB9l+MF-fS=s=sIg9M5W7AQJIpy*J6qQeA= z4i_joLZIkKfuf@XijEd2I!2&qu0YYT0!7CO6df;6bb>(9i2_9@2^5_yP;`nw(WwGO zrwKJhv+4?aWI)QRr_Vah4n-@Z&pMu7S4zH;qOTU(GJ&GY1&Xc^D7sRh=qiDts|AX#5h%J=py)b* zqU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q{nA=*+sp-5HSbH|evE zXN97X>0ESoT`BoWiteu~rXQWxaxQwn@uBEJI}|-+hoXn=Q1pl$iXOE?(PMTfdfX00 zPuQX8Nt>dl1d5&(D0)Vq=vjfH=LCwL7bto`py)+`qL&1UUKS{NMWE6m60|y8fW9lzb&c zpVSr8k6vt1^r_=R(Pwrj`rHmhU)Z7OOFI;OWrw1#?NIcM9g4oSL(z9OMc)e){UA{E zqd?J50!2Ry6#XJl^s7M8ZvsWX3l#k!Q1quj(O&{Ze+v}-BT)3OK+%5!McMZZpPk)| z*;mxF8!&y_XpShoX(rN7oI7Qu37)l?%o6 zqdQv^H99^NwXs7{TRRjr*`cUnhoY(-ikj_E)Xok??d?$1!KP>-fue;4iaH7ubrLA* zEKszFK+&QCMT-d(EiO>Bgh0`f0!3W}ik1>6T3VoJ8G)i@1&WpvC|X{iXa#|yt^!3X z3KXp*)D*QU6pqV)lwV383biiO?&&|D&P6L1O37DJ)T2;LKl-&rQBTK*qF#0=>TQRj zK6WVTYlotKb|~s^hoV*OP&B{}MFVY$Rud>%U7%keZ7fi2>=wH=DKu|v_eb|~7;4n^DBp=bv? z6zyn-qMdAtMhO({EKoFBplBC?qA>zRV+D%F2^8%rP&8hkXo5h|M1i770!6zC6ipT= znj%m%RiJ2^K+$x8qTL0GW(X9`6eyY{)D&%AC@j)9Q}j#rJ&W~Qgrc|7C$eW3O37DJ zv{#{+e)M#UqP-m-iuSQX(Y|&l+RqL}``e-D06P>NXosSM>`-*D9f}UIDLPc3=rDnz z!v%_t5GXoQpy()pqN4?hju9xDD^PT-K+$mmMaK&iogh$jqCn9}0!1ea6rCbabgDqn zX#z#33lyCpP;{nHQ?zHHuyY2aJR+To=7geQ={?$6g;MgB6rEcrrXOA2qUb!whobZC zP;`MEiY~N6(M5JBy4Vgym)N1`Qacn~W{0B7ZHlfCD7sRh=qiDts|AX#5h%J=py)b* zqU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>s41FP zC|sHWDfdc>&Iv^W)3~otO1_e!hYH2?qwiZ3J?!{U^oSjb9<@W!V|FNd+zv%g*rDi2 zI}|--hoYzLQ1pyV(X#?Y&j}PgFHrP?K+%f=MK1{yy)01lia^n;0!6P06umA`^oBsu zn*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ+@MGq7TUuQtd$EVLaJ{XGnq;t{7 zg;MgB6n$POreB@VqUa09hoUd-Q1q1@ioUi((KmJ|`qmCb-`Sz)dpi{UV27d~ZHj&p zDEe8T=of*aUj>SO6Day!py&^QqCW+S{t_tqTcGG4fuer}ivANQ%GJl+c8c->MRfv2 z1%aY^fuf>7QG-BHNua2eP*e12q0l=6Qa(L>K>b-LdOh9kZ(UzXzLKK0^~Ln7H(C@m zIX)Cs>`+v-Ls7FGirU$ssJ$JEI@qCTAv+W;Y=@$bHbtETiaHAvEh12~s6f$T0!51p z6fGf8w4^{$7lERs1d5gxC|X9KXjy@xEKszHKv6fL zrl_&LFed|2-ZGtw+SJ$X=|7P^y6#?IO1_e!-u1;Z2Zf?Ojt@nB?NHRu4n_U#P_(KY ziU!!BXrLX6RUJnv!=`9Wfugkpiq;k=T1TL0kU-I3fubP-MMDLOh6xl67bsd+ zplCgTqV)xeHV`PqgZ6Z*#sX)z3 zm`+Sv)R&U4q-g8fub`6ip~@$I!mDF zY=NSALQT=$^@R;GAmxSA_g(K3ihfStCUQ=FDfvo@E~qc2Up>~M=t9SbqKoWMbg>FQ#8z*P`e#$A_ZF?NIcD9g3c`L(x-qD0xW4de2BbVMy%T#R6t(=4;?L?! z$yZYJRedr2>cbXAUpqb&ePf5BZ|zX@ogIq4w?oknb}0JM4n;rNq3CBj6#ZgT^s7M8 zZvsWX3l#k!Q1quj(O&{Ze+v}-BT)3OK+%5!MY&?!ZKo(NP*f*SR1het7bq$U6g3DG zl>~}f2^6&!C@KpSH3~IFU(^>C+bC0XYI=|MWhnYLy+>{pP}JEDMT^)JEh`6b-aP(Q0-m zTHOvsYuKS^O*<5=Wrw1*ZHm?rC>kVCG+3Z$h(OU$fudmoMZ*P())gpPPoQXhfuaor ziZ&D|8X-`$kwDSL0!5n$6m2R{w3$HB<^n}q2o#MJDB4n}De6-!T%G|buar(deM8Z8 zX>3(2C0|L=cEw`))x9l>ws(9e+QAM*JKCXWCp#34vP03%b|@NchoW8VP&CF4MPqG> z#t9VdDo`|DplE_X(L{lwNdiT?2^38hD4HTrG*zHznn2NXfuh|7ie?BD%@in_B~Ub5 zplA<)qCEwQ<_Hw+B~Y}tP*b!`vG8pMqUoheXsmO#hKmtmpDEYU22D-%j{5exgCnG zutU+6b||{a4nFXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M(ZfPb(S^mr-Wibc8|kx- z7loo_6RAgvrQ|CqdZJiNzk0q!(UXo3MNiqG=xI9?J!6NWXYEk*oE?guw?okjb|`w$ z4n;576um4^^ol^ys{%!@2^769Q1pgC(VGHAZwVB=El~81K+(GbMehj|y)RJofk4rR z0!1GQ6n!jE^oc;xrvgQv2^4)UQ1pdRQ}kG|aDN7*yjz0vcqkf_-lKh4EG1t_(YM9o z2RnqK?;IbBzPCfs4|XW}(GEpF*`erXI~4t5hoWEYQ1qJ}ihj2#`a_`TPl2Mp1d9F^ zDEddB=wE@N{{)J14RN=fqP##+oj_4Rpr~G;s3=g>AW&2iC~758)LNjZEKt-aP}D}C zsI5RzlTcIib+OQ}W2Pv5-L?LkQ1n&0+h1uYC0|KV`-b8Qqe4*!$A_YY>`=6@9f~^I zp{SD`iaOh&Xc0RUEoz6N#q3bDxJ}U#0!2#-6m=0OT1ud3X@R0;1d5gwC|XXSXnBF6 z6$Fa93KXpmvlqMhwfG};bDyV#*;69tMU2^8%n zP&8SfXo^75RDq&t0!7mWigp($njug$Q=n*;K+$Z0qCEtP_7o_ZBT%%LK+)a;Mf(U8 z?JH2UpHNe@eM8~(3`qIf^!-IUgrZ~8d$j!s5XXn2L+wy>m>r4^ zw?okpb|^a14n;@Vq3CEk6dhxSqPaFj#|ji3Cs1^}K+y>TMJEarog`3nvOv)(0!60^ z6rCnebh<#%83ILT3KX3sP;|CH(L8~oa|DXc6(~ASpy+&oq6-9yE);5t4s0kav1_Ji zVETaipis1T%N@3cQu37)UDi-sdqOC>-0`943Of{CX@{b#>`-*I9g428L(#Q%D7wxL zMc3P*=mwjj8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&Zzy zD7s&u=mCME2L*~A5-56Dpy&~SqDKXa9usPcE@>!?&483k=~G0PhN6Sgx#;nRQu37) zJ>5_|Y*HwC#_^%(SvwRxXNRKa?NIcB9g1GGL(xliD0WiryC}`aq!QLxG}?1d2WuDEdU8=u?5B&jgA-7byBd zpy*41qOSysz7}eVo@^*wnE@%knBJp36^hPEcl*C-C?#J>(GLy9rzVG@9~~cxezHT+ z&vq#K#STTk+M(z-I~4tHhoV31Q1quAivF@G`dgsrAAzEO1&aO?D9V-MZaYPJfucHr zqJltCy+Bb>pr}Ehs3cI-N}#BlMxba}fuiLEik25BT0x+wt3c6;0!1qc6s;^!w2DAcH-Vz= z0!2Lpih2qZ^%5xREl|`)ps24vQ9psA{z6Srhf<+`2Bf@Zx~IQTsdi7lG2PQ&wNy&J zlA_g1#jSS_MQb=d6s>88qP6T$w6-0J*0Dp;AUhNdwnNbnI}{DIL(wpsqTvEX>k1UD zCs4G$K+y&QMH>nfjSwi>NT6tAfucMWY=bigvL> z(HJ`vjkQD3I6D;WYKNlnb|{))hoXsgD4Jwbw3|TDWPze70!32=ilzw^O&2KIU7%=& zK+#NrqFDk(vjvLw5GdMHplFUj(Ov>YdkYlpBT%%jK+%2zMf(dB9UxG2pion^Q>pM^ z2BbVU!5I~b2Bvp!2bD_6S5kCXsrXU$3u#-vj&``?L(vg-C_2&(MMv48=x93>9b<>0 zxppWz)(%C-*`eroo1zm0icSW ziryC}`aq!QLxG}?1d2WuDEdU8=u?5B&jgA-7byBdpy*41qOSysz7{C@Mxf|hfuiq( znxbb)g;O#h<)@OOXG77g>0I=Esg!&rML(B{x9l5=esO##`qd6azuBSacRLjQVTYnW z?NIcW9g6<8L(xBWDEil?=s$s?T&uX-PElT|6ewyVP}EkSs7auxB2ZKnC~6icY9~E7bsd)plE6b-XO(QrEyt!sy(^=yjP7bx05plCyZq7ec`8wnI` zEKszGK+&cGMVko}Z7xu>g+S3rfub!1inbCc+FGD!8-b#21&X#4DB512Xa|9!9R-SZ z5^9RpXjRxX15(~H!C5mDeVfijqgs`cucT;9tKt!dgrc#I4@KkbP_(NZipJZaXo4Mz zCfcEBk{yb6vqRBjI}}Z^DVi!!G))ftd-A$=&cODI|{ zkvg#L(%beC_2FoMJL*!=p>t> zlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugeoislIvog+|mu0YXw0!8Nw6kQ-tbfG}e zMFK?^3lv=L?~J!k-DN)Dfvo@u4z?le`F}S z*72d}Iy)3yZ-=5A>`-*09g1$UL($E4D7wWCMYr0a=r)_8+Xag55GcA+py)1vqPqo( z?hz=uSD@%Vfuj2biXIRsdQhO~A%UWY1&SUKD0)<&=rMt!#|4U>5GZ<5py(-qqNfFl zo)Kz_u4+{nkO3)goXz^HL(#tJJ=(LaO37DJ^kS>xwnvAemmD98UbaKgD|RS))ec3k z*`erlI~2WPhoU#_Q1q4^ir%&U4f$a1d84lDEdI4=tF^`j|7T77AX2epy*S9 zqR#}1J{KtZLZIkNfugSjioO;o`bMDWTY;kQ1d6^FDEdL5=trTZ==oNK{WBohSJ5&! zFNC6E`cV6)R;A=CDf+Ed@w~aA=y%75qCf0V^rsz){<1^S-*zba#|}mR+M(z_I~3(w z$NlzDl(#9W6DTSO6x9n96$OeK1d2)mMXdyiS_>4F1&SI4irNSiwG}985-6$&6jcR^ zngxp52^6&#DC!_kw2(m2!U9Ddg_@#YS`{A7fRx`#r=MR#(Tp@YwJs%JNzr1hi=P}9 ziWYZ#C|be}MN8VDsEZwnma;?9(sn3X#tucx+M#GUI}|N%Q?!CWQCESY6$Oe`5-3_( zplB6=qHY33-35wz2o&`cDC#9p)LWpak3dmhfueo_Mg0YeRuw23AW$?=plCILqSXb8 z)(~on7HM55AD<~YwjqPFXzSWN{Rh%mvvn!?N{R-xF0OoHC>reeP&C92MMLdSG|Ub~ z!|hPCt{sZjvqRDPb|~7w4n-T<6paul+DM>iV}YVg1d28lDB4V*Xmf$0Ed+{23KVTA zP_&gm(bfV*+XxhGD^RqZK+*OBMLP%-?I=*RlR(iZfufxSibe}HMQgV%Y?=WnKa@^C z>x7~XEqB;jmy)lfXxG-o-A@ih;~gK0CfK29q8*AR*`a7RI}}Z}L(vpF6iu~5(KI_0 zO}8o9U7%=&K+#NrqFDk(vjvLw5GdMHplFUj(Ov>YdkYlpBT%%jK+%2zMf(dB9UxG2 zpg_?<0!0T46dfW^bf`elVFE>m3pGV!TNh5tfRwwY)6ck2RLMR}sz0K2Dfvo@j%i)I z?bJ{-*YTm~SUVIQXNRKW?ND@r9g0r0L(xfgC_32=MW@)I=v14c(*%l67brSIpy*72 zqO$~w&K4+|Cs1^bK+(AZMdt|=oi9*yfk4rP0!0@I6kRM(bcsOGr2<8l2^3u}P;`Yr z(Uk&4R|z#mN3|}zodGEi%Vz!2q3Gg#Hm+`6O1_e!>suH9IXx8J;P_B?dS3l!ZWP;{?A(R~6%_X`v~AW-z6K+!`2 zMGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kHq0*S0P!eMY9} zob-vt>q60T=|0*EtxL&QQuIpe;*hgK(W{ORMX%YR=yf|3yQG^K+%^1MPCUNeJxP* zjX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvXQ}j~n!h{S+`G)jeYA=VPSJRhfe{Ee# zzLKIpTNjU-7mEIJd?@W1v?bg+Y}WA ziW&rpN&-c#1d3V<6qN;v8U>2l2o$vyC~6WYst6QS1&W#lirNVjwHGMrAW*cBK+(bi zMI8l-ItdhY7ARUos44orb>Z3!NO?&5xaf~ibYeOeEm|%mUrEuD<>GVahN3Qx4@FDa zp=fD46fI+iqGjz+w45D^mbXLE3U(;!YKNi~ZHiVBC|X&dXcd8?ZURN!1&VqI6!jD+ z>LpOrTcD_qKv7?TqJ9EJ{RN6v6(|}YP&81WXf=VN)dh;y5GYzxplB_DqP2yZqQ%RF zpEDrkuhQvfiE{0p{!?kJQ!XW6Nzu@9aiI%B(J;q{qTzNZTGtLm>)D}beLECwV27d& z?NBtr4n-T;p=e{9qD=&fHWet^OrU6Ufub!0ibe_)Z7EQ+l|a$f0!7;h6m2U|w4FfF z_5wva2o&uoP_&ak(I|nUodt?U3l!}lP&7uMXsl3EG`L(?Edx?cKdGpGNGQ4@jdA5t z@|6@#EEl)GC=^X{d??z@4n>pgP&CC3MN{oiG|di0)9p~SyB&&V*r8~qP0=iYqS*pP zdk7TmDNr;=plC0FqP+!*_7N!BSD; zbfO)KPO?MM$#y6@#STTM+M(z)I~1L6hoUoVip~@$I!mDFY=NSA0!8Nt6rC$jbe=%b z`2s~32ozl?P;`+%(ZvEqmk1PHDo}KpK+)v_MOO$ET`5p>l|a$e0!7yd6kRLS6wNIc z9?gK1N2E_Q9vh1GOZW7zE0>b5r0Aw{@w3Z9(anwzMYq_Y=vF%v-DZcP+wD+vhaHOU zv_sKdb||{r4n_Ca6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2oj|db!Dp2&8K+)p@MNbG6 zJtN}%X#fue5&ioO*n`c9zedx4@K1d4tXDEdjD z=x2eVUj&MN6)5^mpy+p@rs&mjVe)&fOkfucr%qBa6WZ3T*& z1d1vGMOA^KW`Ux10!8fwiaH1sEhJF1us~5qfuc?VMV$qT77-{~RG?@vfuhBQnxenT zg)=fB<(}zW^miyaEqhx15{;$gD=AvKv3SR|p=cS$hoWWeP_&#Kik7!S(F%4b>S~9g z741;8k{yaxwnNb>Hbvb8inABB zG^DYVd?iKeHWvT8J`}Cz_)xUI9f~%vL(ztIC>mjhqK)iOw6PtEHnBs|rgkXW%%*5_ zfub!0ibe_)Z7EQ+l|a$f0!7;h6m2U|w4FfF_5wva2o&uoP_&ak(I|nUodt?U3l!}l zP&7uMXskfdIDw*F1&YQCHATZ33(MY+DXLFj0T~{Oj>(=@KcTUdd?iJb8;iqk3Pn>K zABv{hp=g>Nil*D4Xm>jl&9Fn!Ogj|KvP02qI~46xL($20C_2RsMW@=K=rlVN zoolg*I)S3=1&VGEYKo3;EL@)fDZiY)0&+qq z+AO_CyRos9d?iJ zQ1rIrL(w~SD0x z3Kab%)D*qZSXd(iQvN7?bp2*18lFh~-B?P#lA>Ij;*NKRqI{dUCm)LH>`+v&Ls7jQ zii&n9YOq65$qq%W>`>I&4n<{~qDFzDHUdR$1&W#kiYfv{Re_>rfueQ-MePNOItUak zBv7=lKv745qD}%uodt>(5hz+zplC6HqQwP@mJldfQlO}dP*e18W8vToNO^Snj@kc0 zQSa<&^-HxWC0|L=a&3wi-5ZLQcYG*X!45@T?NGF$9g0@6L($51C|bo1McwRB)ZGq6 zJ#3143KaDcDC#Xx)JLGGuRu{hfujBbMXL%F4G<_AC{VPTK+);~MQaEYttn8nmO#K+!Ovrf8Wqg~u}>Y>M_4DB4G$XkUS%{RE2k7brSFpy)t>qJspA4i+dn zM4;$Ufuh3%iVhbjIzpi6NP(iG1d5IpC^|-wWM2^1YK)D%r=Qy7^6DPNvG zpq?6v?o8u^Hl^e%DLSQ1arPsj=v2ptqSNe9bh;gi&agw#nRX~T%ML|n+o5Ql9g5De zL(#c5Mdt|=oi9*yfk4rP0!0@I6kRM(bcsOGr2<8l2^3u}P;`Yr(Uk&4R|yndEl_lg zK+&}VMb`-wT`y2{gFw-Z0!23o6x}S;6rI$ja8?GSykq*TWrUideA~k03`qHo1gEZT?LJ!j>}mDOwk;)J zNm19f#bcihMJqZ!&P6NPp=f106s=;1qHcC5>TZXk9(E||X@{a-b|~s?Q`ASGsINd# zKY^nD0!6C|6b%q48Yob-nn2O&0!3>G6s;*xw3a~8+5$!E2owzxC>ktKG(@0is6f#$ zfui98Me7O_ttZqJE#J0qV+N$WVuG_mD4Leuy{+H2lzb&c8?`OI^n57V*zuug6FU@b zYKNlD>`=719g4QFL(xb(6m4mTqOI&uw6#sqHUdT43KVT8P_(^3(GCJdI|>x-Bv3R; zplD}-qR|3Hy9gAG5hxlfP&7`UXjg%v@d8B?1d1jK6ipH++D)KnvOv)kp{8iVwuRp_ zAmt;|xoAWv>YVQOPi3Pm#=ABtw#p=h=piuSNW(VliFnq!Bez3fo5 zw;hW1u|v_mHbwgh6zwlibbvt7fdWMb2^1YHP;`hu(V+rGhY1uNE>LuYK+%x`MMnt~ z9W79Fj6l&`fudstijET~I$ogY1c9Ox1&U4*YKo?}Ev%IRDL1CiI_@5d&PnH@liQY( zucYYow#8AegrYMXABxVjL(y4wC_38?Mf2=XbdDX0&b33)d3Go|-ws6=*c4qTP;`+% z(ZvEqmk1PHDo}KpK+)v_MOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?( z(ai!yw+Iy7Do}KrP*Zej+rpt4kn#%YdmT>;MbD&r`nR_&C0|L=-EE7PycUY?aeOGc z*A7MZ*`eruI}|-&hoT4VQ1p-;iXOH@(Ia*!deo-qF@d7T1&W>!D0)($=qZ7srv-|h z5h!|Apy)Y)qUQyQUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww}qOb zJKGkX%z%`8rtiDHD-`A0WaFK-rQ|Cq`k-y`t2aW?hmH?LAK9VkV>=XmVuzwn?NIcY z9g04;L(vy@DEiV4MPJzzeJxP*jX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqU zzX=rmE>QG`K+&H9MSlqt{Vh=Rk3iAC0!9A`6y=)YjyXknp{D4)wuS1OnWFaTT=ae@ z8kyds)isrpucWA`>I!4n<9ND5}_@sA^Nx zEKt-=ps2k-Q3rvdg#?Ng7AWc{P}E7FsIx%PA_7H=3KT6SP_(!}(GmhhO9~Wq5hz+p zplE4oq7bsd)plE=wH=DKu|v_eb|~7;rf7SCq8$W^b`&VuNuX$yK+(m;ouTl)mqJlTfs4 z`sjN1rc&~i6wPib7Cs6^dpJH6?P-UiId&-8%ML|*+o5P5I~46}hob%LP_(}tiVm>O37DJbXHSw{ZB&C z*^UoI^XyP`jvb25wL{T)b|^aE4n-H(q3A+86kTM8qKj>cE)giYRG{cGfuhR=imnhS zx>BI%DuJS_1&Xc_D7sdl=sJO->jjE#5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ37 zx>KkrI-{vDH3L$fmOkrvW+-|vor~^jDkWb@(S1$D<39^U_d7lmJz$5T2klVwkR6I1 zwnNb)b|`w(4n>dIq3Cft6g^>6^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JA zMK22!y&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R)Ho(LGItn=>Hg6ABre zdqdGyX}sT5O1_e!kDH3Gd=ZL1aeOHH)DA_T*`erjI~09khoUd-Q1q1@ioUi((KmJ| z`qrlCJAtC_1&V$UDEd*L=qG`qp9PA35h(gqpy)S&qTdCI{tzhoQ=sTCfug?!ivAHO z`d6UnKY^lLCGNIUlou$f6DTSO6x9ngMISa5{>*@sdnGs@g`$trC{{|zS5nlvQe5=w zP*iq&C~CArQ5!oHwY5W0lO2jGb||Xap{UsoMeXcR)ZV73gFw+j0!0f86m=9R>LgIq zS)gbUfucnPiWU2(Fy`ZT?L9( z6l#h}mBKn1kn(xyL!nlc+CBZoq-do|Dfvo@x>t&$zYRq_93P5$+M%eI9g2F}p{S1? ziu&52sGl8*`rDysRXY?7uqhfSP_&vr(dq(4YX}srDNwYQK+)O)Me7I@4H76CEKoE= zplGN-(J+Cc;Q~eL3KXp;P_({4(FOuV8wwPS5GdM6plD;Erf8K);qVMd`LT2#ty?Ji zz2y#DrIdUnMO##gmwg|KMmjzeZE1(1t?W>=wH=DKu|v_eb|~7;4n^DBp=bv?6zynJ zw39&5D1oA#1&T%s6zw8VG)ACktU%E?fudanipC2RO%N!WC{Q#>plCONqR9e9Qv`~p z3KUHfD4H%%w7Wpj41uDVLQThoXJ$P_&;NiuSid(E)ZSI?xV92ic+MV4I>t1d0w7C^}4_=x~9eBLs?$ z6ev1Mpy+6UqGJS#<_Z)YD^PTtK+*96MJEUpohVRrl0ebP0!60?6rCzibecfX=>kP( z2sK4}R0{2W$`pN(KGC>mC~8P|`_HVDlCPxboJz6JFQMpM$A_Zx>`-*R9f~fnL(zqH zD7wfFMHkzl=n^{=U22D-%WR4+7bvPuZd9 zX`7;F1d5&&D0)ty=y`#n7X*r46exO0py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ zZGob91d84jD0)wz=zW2r4+M%n6l#j@uN2PBfRyh{A5cFKie{v9(MOe1@|6^QRw>^1 zM=1K-@uBDoI~09shoZ0SQ1rDOioUT!(YJOe`pynT-`k<+2b-cF1&V$WDEe8T=of*a zUj>SO6Day!py&^QqCW+S{t_tqTcGG4fuer}ivANQ%2nfTJ4JbcqB?=1fK+!OPqTvEX>k1UDCs4G$K+y&Q zMH>nfjSwi>NT6tAfucQOCB&w!M-Oy{DWq3EwPHm{bFucTi}tLRlCPv_pK9^7x=^&Q<3rJYb|~844n+sp zq3A$66dh!TqJ!;Fbch{_4z)wkVKzmF3ltq8P;{g~(NO|LM++1kBTzI~py*hEqT>XL zju$98L7?bFfufTHicS_NIz^!9RDq(?1d2`J``POhoXz@P;{{!iY~E3(WQ1My37tmm)oJ} z3Of{CX;XBSK+)9#Mb`)vT`N#@oj}p`0!23n6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07 zcL)^SDNuBmK+)X-MfV64-78RZpFq+5LQT=R)xzKmNO^WT{hSwyZcX>m9;lX*ucYXa zYH>^{6g}$rQ1qA`iXOK^(GzwkdeRO>PuZd9X*(1>V~3(=?NIcbP0{lLMK1^xy(m!h zl0ebR0!6O~6ul}?^qN4?>jFh@2o$|3Q1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$ zkwDSM0!5z)HAN3q3rA)^%3agB=;2V5OQb%nmXfce=*w#Hiq@g%E60bTukBFujU9@< zwL{T&b}0JZ4n;rMq3B0D6#Zm}qMvPwei118RiNlMfui39ivAEN`ct6jFM*=J1&aO= zDEe2R=s$s?TyxxQrzkH_R3}hW5Gbk_C@KmRH3$@y1d3V-6txy8DhoA5pH~adWQ?!Uc(V_xHiwP7hE>N_DK+%!{MO_4nmJ%phTA*kdfudyvik1^7T3(=N1%aZj z0!1qd6s;ssw6Z|aDgs5_1d6%~6!j2lirO|8I<(0Yt&_e2($rkLr~gZar@m)%Dfvo@ z`ZgE)HHD&njt@os?NGF;9f}6np=h8TidM5j(du?6TEh-SYuce`Et{gX1&Y=YC>kVC zG+3Z$h(OU$fudmoMZ*P())gpPPoQXhfuaoriZ&D|8X-`$kwDSL0!5n$6m2R{w3$HB z<^n}q2o#MJYKnR{7q-iQl-s8JXnjJ_e(9s@Et^ZpS5mZXb8(+)DB8~Pp=f(M6zyP# zq8;r}w38i*M%kfgXFC*)wnNb_b|@NSQ#4kfXq-UNt^!5l1&SsJ6ipN;nj}!Pn?TWI zfubn_MN0Go;DEcye3Ucq}Qu37)?cZE{pj{|B!11BzKsyv2WQU@I?ND@x9f}UML(yS&C_3B@ zMMv17=t!HQqXdeM7AQJKplGf@(Xj$W#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@ z6rCKWGD7sFd=z4*o z8w84O6ezk$py+0SqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s z2Ly^96exN~s42Rjxv)wGq})4w_x^>U=)H6b^7d?YdR3t4HG!hn1&ZDfD0)+% z=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiarr2`c$CkGl8Pdg_@#An+r2C zAmy*qJ^jZ*(bgHB`Y)PG$yZYJO>^<&?5EMRd`?T*9g2RiL(z|RDEi3` zML*l2=odQ_{c4Az-)xG07byBepy*G5qQ3-+{uU_uN1*6mfujEeigNAZZaYPJfucHr zqJltCy+Bb>pr}Ehs3cI-N}#BDC#Ouw4y-KN&-bI3lyy)P}EJJ zsJlQ>4}qed0!6(9ih2t*Mb&nNe={KEdFfL`&FyOU^gm4JqCV|P$yZXeYP;f+ON62U zjt@lx?NGFu9g0@BL(v*`C|c7FMQhoiXl*+btz(CxK{iE$1&W3U6b%(98YWOQT%c%O zfui*Uiq;n>+CZRaLxG|Z0!14M6m2X}w245`rUFHq2^4KEP_%_W(MW-!Ed`3U5-8eQ zs442#t}rwMQa&=l=^u*5r*qLZ?Mlg4QnW+6;l3e zu|v@qI~0wzL(w=p6zytLG+v-+fZTXyu)ia=G;?%XG`-MpP#D$mKSzT-Pg?8(I0KPcFAjW%d5K+zyq42IO)(R~}m} zmm6DYyJjvop|Zu=x!mN+nS*k<>6Q0}E9>+<}$fM&xpb zR@U4kmpig@$Y#0R+{zPMreDqH1pr&PAwCYL*-a`tw)+`P&MJLGcbS5_F6%UxWV zGCG&LymHf+T<+@1ALDYl>nm$d$mMRX95yMJyS?(%lz-Jabqs z_j#rLk-6O0m2HpC<-V_+H#e92x$?OZT8FNtLfK~ zcgmTJ9x zHT_@fu(+@}AIbTgb-Fj@kntnX-gnTvq zeA&tQYWe}8)AQBz6CP*ftLaDd&B<5O&sf_xUrj$G>%e?9{gk6a^VNIa&u*c7HT|5C zx%q1PK@lh9tLc&cr{t^Yq1tEUtLd?}^YYd7V9E3I)%0k$i}Tg=aHY%h)%19itMk?L zfPw4t)$|?TH|MMATXt{HSJU@g-kqucnUx zf6iCayYS!h)pQR2JD+R*D}9^8#kIe3?e@?9Hs$+dCA&GYfAjOYu8_~Q@1Onc%J*6P z_^f1qYWb)A>Md=R)K<>^T`v2#!#>%U3G)4#Qp)HYXW z<@p;M+cvgo9FV>3tvdc6&(%76uK#(d<(S3VD`|`una%Vf+r*1(dFp}}**0EeJXce8 zP;tTKsI<*4U3$&cmOm78x#oCF;+3@Po?pAO3$a4y=6t(`bvm6sxN~}q?Ti0&@#;F> zHaNRZI`sXYwpjLp7dqweO$orq2EnY?}U;5Z33i+v+?|T=4(evu&3Cw{-SzKDTB1pCdM#f5c*0&2G}{ zA9!oe)so^r=_vm^n>}+OH#YlkUH-48wz+)vPxiEAu6y?$Ge-B=b>{RQGiQwHF=N!s zG2=!}pD}ILxG}TFjqNdJ#$MBBO-o_SxUsWmjGOsCPfO3AJ@>#K(`QVaGI7?#J;vpF zOqe!hT#wO{$Ia={ee$$1qbK*6IbrmSaXn^?n>udh=$Spn^&T~I*6gtpr}daMZQA59 z6Gl&*IsdZySdi`}M9n>w!BxY4^z?AEJi_deay zle=e6{y(17W8%~?lV^_|*JH})F%u?E{r~-9%-n0{|6UX0C-fLJW9;mSQ>P7?He+13 z`PapqSu5OTUvg>?ik1eK;p0V5T*;7Z2%-)vqn@*lRbJXU8`ft?l|HjR< z$LLw((zTV#)o$orXHOl|vtQrtV-kf?W5?|}diLa5qh{?jeca6M6Oyp(<{CS3>a1*J zr=%^03>%eQ%rQfzO_?%nYSuD*z)Vapx|VX;3BK5(v(P7BEVlpu`lpz0D2&f{DRwAy z?$W*3F8jk$#db>;iw#Q^J2d2r?R!}5vsG;9QB42O_vlhr$oy_TY~4}Ad#;yD|L--R z=X#@dsr|8k-}!&+H)Q@F`wxic>^ndkERi!=)UT^RDuXo7*yvXbV{@?to7JpM0+<@td=e(JcfU9#J<Fae2U2sij z*Ka&yc9CnhQT9@5fB2t^u&P6|Tc+iS*{v4G^_%~~vdiO@_KxT8v*2pyhdF0;qyvUBFt@#98~n>u#l=&7S7Pn$Zv_Uf}6 zD0}tUN#=iUp}0=^F1YNOhT5~we`A^Mx!`RbIR7o_mHlYT#&)x3cu_|ZFvQ}%@x}W zl;e^No`0Fr8KLEw1}(U7L$e!y(B|v*O8@Z}8jJz+Uq-J546&i6*8-Q>#gEs?N{fng zF3Qe2Ew8!P0%W~1WwqAR6BoGaHQa5ofSa2syY#i={2|>QEoZz1w`q0~jEmAMyDa|L zYr$3VKez0vaky*0h9{_h7j^19`f?K`Uf}6e9|J?4`O;bB$!7c0t=ruUr z_H^~9*EDec<;||&xVQ^WSAF6o^;>XxYPWmKTfN|>?)5*n_5a+){j2o{G+p5AYS5v zOW-!nuAz9^{M$0S32LulfsO2Bkv&(-3vYQ+cH72L*@-{?H2)3B+|`cH&YkJBHKTT| z^s4nPUTOL0#ypQn1}*;N_q zew0%_SDwdMonbz@&#!3nT~C7fqyb6KwtH2WuiWl4 z&*{cKw`*DcPhVbKo-cd}e0FcZ7*2Vc&+i^umG(M*elPL)eZyE6dWslxtE`Ll{Da|Y zfA;k)1$W!F|M|t2JEza@o5IK5;YqC3_}LfLSni5GzgzkI-sJN;ljd$IeB93ld-0xm z=8ov|yKyhvi{pOi^Sf+(V#IQTYwymv*N{ZI_uEpg0()ms_a9T$3eZ%MX-=5!nL-(@}{j+M`E2&bZ)dL7uARO-QnjWIaK}%(K37Md}r;S2eD_CnSx(UYHXe zn%0{>C__*tCv#AipsYdJg0ctY49*=?)IL!EucsH2*K_;ni!U}0j$WMRaa+nmv1iS( zkK|r>a?GQ+G%sxXEd~2Mq&&~s^KUWOm*0Npj;GZ2ng4#Y zn`eM0Psjhd7jJ0)_dRR-o`;*i-o6ccwC{Pa{Z_m^n(vp{OKOi9bj)Ip=7qWJ(Y%}X z^4OQ#kGDOV@2005&G*n#j@5K*pkq@V&ExZwmv`5(uZ|;i9IN9D9hd94$$Y5o-}AYS zr_DQH_eCA=n|HwOAoC3-d(33s7kiA+(SFOy?wUHbHt&PoU36S(K2&ypq~kSn1=xL8 z$HE4V-Q{)cXMQAM_edRgm`@P959#%%>+WtkeqcTT_Vqv3@z;XxzOQ4^BJO@g#{uR8WnX`^jyq%BeOO0NDR)Qe zSj&7s?dvzzacVhtzo+A=3hutBV`lS#x3B-Qj;~jC_ZvE{sOs)bI{sGO-4AsvUd!E; zbR1O2-D7mz74PmZbqucO?o>L~NpyEp9j7&P_d*@dG?w+9I-r?^4TE~!)?oOv; z-O=uDspG6M?p~tf_v74sRmYqY-Can>j+5QpSI4ze-MwAMThrYAua0GAy1TlL!)LpD zl8*c5xcj({q4V9HLC5+F+}&EocNe*PnU3epPr2;%b6v;iW$rGbW9Q}W?yuwemG1sj z$2+Ut{Zz+tYu#N_#}Vt@Jw?ZZ8{B#)opAT>I_5d;?pPhWf9vkSI&M7c?$336V1AxwKR(WR_gL|QdyLcZ?VsE| zUB@Gr-2JVNQJ3AFO~)oz-JPW4g6r;Ht>dK|?*2o^yf@ulQpX;Dx_hXOpWJfy9vzd- zj|}bQ_1$%kuikf$2|A8_=$3^B|fPMWnI{spQ z;%N6@I_5XunYO#Mj=lWuepAOS=7*8?<@^r{fj#LruGH>sZkIbkpv#I`)Zn z_ggw{Ge7UNFF&ATcJtc>5b?l-(K*!NKPSbIr zjvwl{Rmc509@p`LjyH6Cprd1cU}-N`W*rOIqq*EgbToHYQeGaaV=5if=~zg|Vmg{H zzbUU@LC2~(*3>b?9?cs|t!)k|ug~Ap-`-y`m&e>~@dTT{EHkfHwExha1Cq>l?)wku z=N`NAoOv`oz*E#deDxG<-@m`7sCmF$)W)L!`OV>!-qC*V)_nWCb8mA>%JWI>+xP1< z$UVy~=I3QE&ZK_!?x^0b`x^gy>0y7`rMGAk)CG|9~RJBpP zqDcb=^y}7s-~jVx|6f0uyJqII$-VDuPcnCX{^QA9btzA|%%Ar49C!Y2uV-IopYoZ1 z?8o*0_Ikz5>-_iMo8L5^?8nYN6*m8vyRV)q<{$gCw?a_L$2p^U-oB3g$NqhF%s*TP z^Q@q^c=7Gcf8p&#nwRnR7MSNb$G(k8=IxyV$qO%= zYo34c?R{w8p8Yu4%V$5|d3&qO^Y-mo5B8~b;UG_i2={sWr+u0I$J|BukJp=1F31ya z8c)35ZWHYDJY6!cXASXW|6coK?lSzx<=gne`)hB9xO~UV^Tu)?b4YoLC~qzw!yNg$ z?D2)G!BfY)UKJBFnQkA^+P7z~cYB@ixnZ95Of>$=*=O{`+e>5ii?6rWT)rQ8C3EEU zUVP|VwrKBS=I0V+$`vnBu0+Xb^R12Iu`m2trc9~m=<;Ps6)zWUpW20wtXa2~`^G)opBqVK78`D%AKUx zt?}Cu_9uJO>`z`%{8X|x)>G)w`G&b-x_+FvKiL!8p{xCKdCH%cQ~q4{?6uG8wLQ`H zZ5>Yb1lePw+$$26);*l;&2>2WVDU5m@j7+x_+u8wzZZAVyzar|OVKgy0$mpdJwB6o zZ*PMtcT&a7ia(MRXqT?*61O$4e&UJ$tK9Q~qXut;q>f z;-|z-tz+J9UwawsKh^JCsoEm zH@eP|WKUJj9g#3Heq`LJI_~>3GNDJ}5p(tt^Zxwj``jpZ*Mv^yef0$WKfk~B{j_hx zlh3?|PVEOl)yyS{zMOP0`9$B#-O}9}S;uqh$5EHNIk!eu-+Vi|x967UZB}u!+Ky&b zF>C#^mo+eJ(->YhqpjzbGd47LL`>o>^IzM`HNV!(TIXwheIqy~Xs%~wgM^0h4dWW= zeW~(bZ1wVW-Rt7NKRSuGM%AwK;82=schbcak9R*tC;A*rKA1Yjd`#xMACtzXld9ZF z8`HR5zWBynTY4UUYYo+Surl2#^S*i()inPlcKck-OZHkC#XRgI6iTA2i zACNdOZlJjqz55O(uQ1o*36H%dJGA4yFWL2Ca_U+3eeR#~d9^v^&$}sqo=f)h2`%Qi zwQEd)S|w_wkM59gI@w#*Q~1&O^xZ;ld!r7RYo$pye-3+mx0~m7XoP+4OgH;yo30(r zN9DA6E_I2z?d;KWJ9YTfl;^%m`Lk+r>O}K5R0*xPs%G%12DNV0I(|L$cBprS$9p@q zcyIjh#Cv1=l~0JRwY!yoomnJ6GyevB9^Vog; zTru{w-I6E%<%E~x@}|80^S78g{-tf`o_669Ip3C$gSr9nb?&jZ=>HmLH&^qMnPdxASZa&{MN z+y7zT9`lxz8(n=xvs*_4hYo(4yMM#Kf3~;ZI}$#P|1@rA%H{qv!CouN+ow0zL+*C= zz14eCF7Z~Ls492fHt)^F>FBxrnjkZ1=+BNRl+GwyJrvxL< z6FVj4&toZn8V8jpR{P`R2X$kf-Qq4ySQ@`9Zdsk{N%n8DpW90k7Ffk;jN)fsAB^#; z=2jxzcgds7ZL%lmyX3JtPSkN~%5i`4iPSU9=kUSQlj7`Wux>-lZGGC9vF5fu!CXFj z8)7fnsJe%e$EJunlsr+#sXERuxA;ejw+?x9W<@b zPki5mzH$9h-fG{3a>i$0qco;n`WW|Y_u39N*LIKii^*5^HA&3fu8Fx;3SaWwA7wwc z|36&YwO+WkTPC!MZxz@2g=@P;!mIy>Yugj#UfW(BLv@TuIofNxbjr0|WW4X3VCzOdV6Ib@x=TPBzbKQ-|-OgNl{c^{cYrSaVz0iII zYI$bW(DiISN8^j?voz%X#Qx?wHlJI5bA5-H>)SUhX!f=%o;_WL{(N}K*JWBZ8}akQ zv-S3wN8(F76DGQ!R}0HkT5%_>_sfM}{{F?99ToGhG@oA=`_4gZ<7<6ON=_1CU@)U5IJ`Azn_s({ z)#Eo0T~c|fjEx_cFfML<%KJag+>;pcw*6eRpK0bdMD*EcZ=*&g7O0i4oonSSBXop> zCf;+*ZC-Fcdxm?9SEFC*7<-%NF}Hd4^I5k3NqJhb#u*DGuLd@6v?4ioZFYHJNFC3bdB#C*R76o=kFN%7P|b`*QSn% zo#HxKXa9$NWB(Eq=_IxVeP)O>aN!hCg#Hur3@ zhbG?29F}-1eR%3TiMJvmywRT7rOa0+Zr}cIU!4lZ7fL7;S2*QkX+9S7pFZsOS=9gV zRqxdQ_%{x^68~A-D<8%UTe~rH!Oxv;Pqw8vGsgTs=k_i9_}rz)jIlqaDmtUtD|br8 z?TtRO_>&oR3gll=J>9oWFPtbmwcd?g=hk;P;ru$h;)5DnTKzHWy9@+L-JTy5Qr*1C z5U(A6uQ#vnBl8-e_P@=WPyfF4OJ>G;y!kbAnpwi*Eufjh%#!B+2c??wbR*cE?FtS+x$eiS_yOcYG?n%d_31l3BK%U4U=eEh?_-aO86^YIV2|6Ygp zW%u70KIu2l*YsU||2X(Ob$HbPoxBc!D^LRx7fq_s9e+Gr!>HEo2vu8okk+6ZZKk> z*G9-&+6Wn;jgXPr2pOe~kkQ%*d0QJHW3&-6RvRJXv=K618zB?45i(I5A(ONbGFclT zQ?wB>RU0AiXd`5rHbSOrBV>lQE2Ni`&fo|yZob@kd%HsZH8i|4{Z@_@GRK$Byf8(` zT%9T*^E4%7zNUn{rzs%|G$mxAri3igl#s=m67s&Lge=iS$Wm>DEYn8F2igc(u8oit z+6Y;xjgVE^2wAO-kPo#HvPK&rYqb%wP8%WXwGr}>HbORNBjjUkglyDC$R=%se4>qz z&DsdrqK%NP+OCkI#`+@7ey~w{onIi@xUO2PP>(F6mSW`B_s!e$kYW%bF5$MN>kq zYD&m8O$oWKDIvdVO2`dOg#4zBkl(cta#I^2e`q7*Pi=(!rHznV+6cL=jgULq2)V0` zkbBw)xv!0o2igdEsEv?hZG`--jgWt|5%NeIA&<2Y@~<{Ro@gWFskSTRM`xJ%_=iuj z_dR|}5fbQWZ$r$l?J_Dg1)yS*XooMxN5<$iV!v(4S| zP1;5UF)bmj4dz0oBc!pxT*~x>)HaxlnSqeX26H(x5~6G{7c>(g z(gt%$GZP|Au#a%E5CS%sOPZAsZiBg`*$81am`j?S5NdjV5?)FqbqJ!Td68%0r#pgkTfwW1Sd6kPYUN<{=m$QC@Fwkh9kS37oKZPn;lE z(LAHa`*M)q^0JBw1o?h8KPF63RFLzfs1RF<3bUoC2wRGZvZbgPTZ)Rar6`syMJ3o$ zRFaLNQUny0CZMPc0YzmAC@M!lQF#K2DiBcg3IRnG2`H*WK+&rN6jdgms0sl^RS77n zMnF+@0*Y!7P*jtEqFMwL)h3{*4gp1R1XoeMAScB9>^YENZ;J9u(eIX2e30MzvWn^l z`SPWgqD0P@q6Ta!YRHzNMrJqal4MQ|0>4RY!lAb~Ardh1Eid3#&bJIHT+Sw;PWd_B#tcBI@E4d8q!8pxKS zL2M}+%$A}dY$+PbmZD*7DSDGFMZ?)r^cEXMBM2xONkGvk0*XcxQ1mtdMPmpk8cRUY zI0A~s6HqjPfTD>66ip(aXfgpsQwS)UNECPyV6I?}o zgPd6gNMN7+23|iYDwy&(E68tsSw-`Me4EWL=cOomkMpHy0b7a|vZZJdTZ$I5rRaUO z6fI#((NeY)En`d32W%8AC!lBr0YxhbC|X58(P{#UJ|v)M4FN@K2`E}eK+$>viasKs zXafO79}`ftk$|F21QdNjK+$Fbinb6?w3UFOZ3Gl;C!lBt!BsRj$obv?34Cec%#)%& z%{TSDp9cA@FRSSDAm86vrD!+jOVJ*-6zye8(LS~m?Pp8T0k#w!WJ}Q@wiJEAmZHOK z6dfU;=t}~MjuKFGjDVuA2q^lRfTC{*C^}9+(Fp>IP7+Xbih!ci1QeYipy*oyioPSD z=qv$6-xE-Dj)0=`1Qh*1K+y#Pihd-xiarZ+a+=?J4Xm)YMZ2Wv9s3pSry#%eWflDr zTOVRIaDZ0r<(H{g9{YgO4 zUj!80BB1Ct0Y!HRD7s5P(LDl+?h{b-fPkWh1QaC`Q1mweMgI^`^oW3>#{?ApOF+>R z0*amzP~-`I_9)+dj21*dQ82+(bScQ`Xn+J-+MA!BrKp3wVRC}~)|XY}5B80FNs2-_ zUy8!mQWVaXq5xZpBG^(C$(EuhwiKmeOHpdJ6s2LKC@ld+=?ExFPe4%y0*W#cP?U*) zqRa#oWg(y_D*;8>2q?-n{!k($*nOlw#@-g?5B6JMR#D+#-?3a$RD|=Ts3=>Cim|1rI9rNh z*-})3Ekz~SQdEj9MWxwNRECYBvIG>BBcP}}0Yw!ED0+o}qKX6*RU)A1RRW4C6Hruz zfTF4d6jdXjs5${fH3%rGNkCC80*Y!AP*jJ2qBsJI;t429AfTu&!Btc+*tunZ1g_af z`h}$ECHqLfUa;T#vWgl8`_kl*qDGuAMUB}~)PyZXP1#b^j4egY*;3SkEk!NaQq+nq zMXlK=YC}NLYXlU%PC!vx0*cxZP?SVKQF{W4IuKCQk$|F31Qc~9pr{K0MO_If>PA3O zcLIvuAfTuR0YyCtDC$K(QEvi@`Vdgmm*6T&40g&GAc05rhZ_x~=!*UF)-Tv^eOX0= zf_=^NO3`4>m!ctTDH_U_qG4<)dXp_h!`V{w7F&u&u%&1uTZ%@pQ8b!>qPGbs8bd(Q zSOSX15l}RqfT9Tm6ip<}f%QQK&H^bqZ*Pls1^cZpt7vbq?{YyY+Q<1)w4W_S2iQ_{kS#@r*i!TbTZ#^| zrRWG-ioRq^(NQ*vjuBAw6#+$G6HxRG0Y%3NC^|tv(MbY|P7zRant-A+1QdNsK+$&u z6rClY=z9W+&Jj>_o`9ks2q?NhK+%r`6#Ya%(M1A^E)iTsyMvw3LPk*~^Kbup_ehcX z_lnE|wqU>YWfffw_7x~1Mb|iAimtPz=vTHB-C#@6Z)_?0oh?N-*;4ceTZ;Z*0*dYvQ1pO+qK5<&B@&q%C=J>Y8N>Opn zm!ep<6qR60QAxHGm10X#X|@!VVM|e2wiK0POHp|?iYgFL^a=q*6$vP+L_pE21Qb;! zpr{G~MO6tXszyLjbpncN5KvT;fTCIi6xAl6s15-|aRd~_6Ht^uKv7)+is}(iRG)yN zM1rfRh~u0$Kmv~aMq^Pa3bwaJ4IIDqWfe7Xe2+>>QB%&BqGoIOnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt=v ziasKsXafO79}`ftk$|F21QdNjK+$Fbinb6?w3UFOZ3Gl;C!lBt0Y#q@P_&bPqR$8@ z+C@Oo=L8h(Cb)_gInH_mB(U8oS}a9-?AYV@tuL$SfaCkx{AX8E6dmMzDLTZKqA%D| zbeJtgN7z#IC0mM)vZd%4TZ+D7OVQVC6n#TL(QyKbP7qLZl7OO91QeYnpy&(%Mc)!o z^c?|3X9+0!o`9lr1QeYopy&qziY^dP^dkX9KM_!Lk$|F01Qh*DK+!J*6kR5`iuO6q z9Rnm#-Tnk*zZ6}tw?$VRzx8Dm{p$GAng2FtilQ5wFGatxrRaCI6y0P?(I0Fn`jah1 zf3caY$;05mZA)7Day!}qD*WQ zWhS5~3jsx02`I`&Kv8xAigFN8l#_s>mk20|CZH%60Y$k9D2gGVC=UTeFB4Fdmw=*t z1Qg{bpr`-=MFj~cDnvk0VFHSZ5L`t8uQS2`2|Te6?jyYJBmG4C6|Jb(Z+%%sCA_{R zRi&sT=Sxv3wiK0SOHmoN6qRL5Q8~60m1j#)1-2Bu!j__nY!p=@py*WsiYgOORE2<| zsst2OBcP}{0YxlsW(I5hf1`}LGO}$Qd4Wnq0 z{jOs(DXN+BfX(Z-zO16*USFYFQuG$*OVJ3n6pds{(I~bQjb=;H+iWQs!PaYfTGz16unD8 z(HsJb<`PgekAR~21QfkTK+ysMiWU-3w20s;8s>Ex7$AW~_PdU6O3`BbD{G6re(TFB zTITijts_MraK02RXG_rvwiK;oOVKK}6s=}U(T8j)TEmv2wQMO`$41e50*XE&plAaD zMIRGTw2^?KO#~EuLO{`G0*bZ}P_&hRqHP2eZ6}~;2LVN&5>T|0fTGU`DB49p(dPsd z?IxgT4*^Ac2`Jh}a1|}_I&%$>z%l!MHs zFWFLblr2Ta*i!TrTZ+DBOVKxMDLT%Uq7!Tsog|>>6ahu22`D;4K+(4Z6n#fP(OCkD zz9*pQ905h=2`Ku3fT9Zo6#Ym*(N6>vT_m9B5&=a&6HxRE0Y#SyD7r#G(NzM9t`S^C z2ffY(10;~!ei1t)MfL4n?dx8@^<@?P?)Cj!SBh?Oz7+kzmZCq|QuG&Fif*x`=r&u5 z?y#lkE?bK3v8Cuf8$}NYD0)ahQ8EEVe-lvj4*^Aw2q=0?K+(Sh6g?rJ=qUk39-khz zqbP`gqF@4w90H2G1QhuQC<-B<$WK5~C;>%b1Qdl6P!u4zif(wF-1Us2Y@r6uZ&I|{ zenpG$`K>RjD7DX5JyD9%aK03!WlK>ywiKmjOHl^46lG*fQ6{z&WoAoJ7Pb^+Wuqt? z0Y%vfD9S-VQBDGiULv3^<@>6_W33? zl%g`6FGXe9QdEvDMdjI2RDmr;udt=4B3p_ov8Cu$wiH!nqo@i2MO6tXszyLjbpncN z5KvT;fTCIi6xAl6s15-|aRd~_6Ht^uKv7)+is}(iRG)yNL;{K$5Kz>RfTBhO6g4KG zs0jf@O$n}|l0IjH0TS44Z;MJvQ4@Px)Xe9%zO15FKHu@iQq-FBrKk;Cie6(&(d%p} zYRi_Qc5Eq1VoOnbwiI<>OHoHQiaHTc)R};yE(8>HC7`Gq0Y%*jD0+i{q8laQ(NF@4h7nvvEqu;B10>MG z-W6&oMX%U9NpJf6)|XW@(&x+2Oo~Qvz7&mSOVQhGDH_9;qOoi#8poER@oXuYz?Pzk zY$=+=M$u#filz`yG?jp&cL*q&MnKVY0*Yo3P&AW(qFDqK%_gAeT>^^c5KuIifTDQ> z6wN1~=sg0877$Rhkbt5^1QabMpy+)9ik1*uMQ{0>3I<5P{;warBcy1uy)9bm^IKn5 z(F&ihbqgt4$@x;WiY-N}*;4c&TZ-1OrD!c%iq^5EXgynsK4MGJ1~!U5CZK2|0Y#e# zDEfqeqRj*pZ6Tm&D*;8@2q@Z4K+z5YiasTvXeR+hpAk^Bi-4lf2`Ji4K+zroiuMvv zw2y$I{R9*pAfV_V!BzBu&lzQa1oGIsLd&J-uz8vHkk4;@Sw&y^e9Kx%(NWHqqGN0+ z`id<@U$dp?8@3c3XG_ruwiKOYOVKH|6rENlU?`m&1t^!cuv|JhT@&-DM|d?~ucmZIBiDZ0a!qPuJ< zy2qBH`)nzCz?PziY$-}+qv&q}ivA&>=n(-$j|nLHmw=)t1Qb0bpvV)VhwUf|BA_Uk zfFg&0A};|&J_3qD2q^LsP!vi)Q5XS5;RF-~2q=mmpeT}nq9}r^=%&w!c+DuXKX>*1 zAw?tYUF}pMe(TFBN*CfQ(pHMnbG{U1U`tU(wiIPzOHpRF6lGycQC7ATWn)WGcD5Ad zV52A}0YxtnP!vr-Q7!_CauZM#LqJg;0*YQHpeQc^MfnIQ%1=O10RoB&5>Ql#fTF?# z6cr($s3-wN#Rw=WPC!vC0YxPUC@M*C6{QJr8W|vgcJ|(N+7S1V{ssH6zf_3d`m&13 zh4}g>Nl|&um!b-6DSCx1MHSgnREaG`ud=16GFytOu%)OfTZ*c&QB<9Pq8bDg)g+*( z76C=I2`H*VKv5h4Mezg_B@j?lmw=*r1QgXLpeT`mq6P#MH6);@5dlSw2`FkpKv7cy zikcBn)SQ5#76eyOnGk2b0TL)|zlfEUqSp3Dvn@mX)|XZET8Qt{4pQ_w=SxvrwiLBv zOHmSAirTZKr~_MyIx)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1QfkVK+$jliryl)idu&_ zKN%o__V(tdjTEJ^U(rT{_^mIi=x2q^l1;3^sw;^gUU6z#FMMWdx?yS*)1 z9^$vYtfJK+zM5U7=tItzqBU$OTFaKAb!;hG&z7Q(*iy8CEkz%*rD!8tiZ-!P^a%k) zn+Yh|LO{`00*bZ~P_&(Zq8$VjeM&&lP6CQPBcNy(0Y#q^P_&zXqCEr@?IoaS9|1-C z2`D;1K+!=0iVhJ_^aTM$hY7Btl_5@d10=A}-u$eRBEKC+Lj2a3RrFPeZ%TJ5`kM2l z=o_{a9cN3?3APlSWJ}R0wiKOaOVJs&6n)EhrRi^ zB}H}YSG2T#zx8DmW%Tl!GlrIoVS55?hL* z*(l0IKv8Z2ied;T%0ocW%LEkVC7>uD0Y&)Kv8J|ipmgNMd|%cMFS*oE!@D#;CCPCAGJ43W&M8Z%PM-s z?|ZGU6jkJWDXPSlqF32cRGBSBRoGHgl`Tcp*iuxTEk!lhQdEJd;>pMau70*V?CP}GosqDBN1H71~_2?0e-2`FktKv8o7idqm* z)RKUrRss6AVXIPtXTKLU#S z6HqjOfTDo}6b&MvXfOdqLkK7uN>O=L^aB(@YyW=qi&wiHceOVK-Q zDVoNXqUmfD%^;v?CILmW2q>COK+(Gd6wM)^Xf6Ro^9U%KPe9Ro1QabGplBfhMT-b1 zT1-IE`vep%A)sg}0Y%FQDEfeaqU8h>tstOiCBaoR#_vQ8GK!X&=^ZOY1MF9{Rerzq zWfiUU`-%;bqIH}vMeEs8^buQ%Hn64WW407+WJ}Q|wiJEBmZHsUDcZtD(N+SAwh>UY zoq(bp1QdNrK+#SDiasNtXcqxRpA%5Dn}DJ{1QhKhplBZfMf(XTIzT|tK>~^n5m596 z0Y!%iC^|ww(U$}i9VNJmKJ+_H43NNm`|rlCk)nt8w&LOVMMt6#dJVq9<$=Jtd&X6RL;pC<-E=D42jEhkzn40YyFnib4n|@)J-LN<_5=d`})B@!Iq+&Y$f|**0wwJ)$z~39AL(zkU(qUr`mHak=+#hP z?a@+Hne(Nn3R{Y*vZbgRTZ*c)rKkp5ifXc@s1{p_YO|%N4jV;r1Qf*+P?SJGQC$Lx z>Jd;>pMau70*V?CP}GosqDBN1H71~_2?0e-2`FktKv8o7idqm*)RKUrRs0y8bez0&VNm1UE2W+8!>&q(Y5bAqpj1+a`d@1V0mZHvVDeA(O zqONQy>c*C$?rbS~gDpip*izJ!jiO!z6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{ z4JM#y2mwVy2`CyyK+&576b&b!=q&<@Mi5Xml7OO71Qd-Xpy+J^ipCIJMM5Ky#~ zfTCpt6n#KI(Q*QcRuE9Ml7OOB1Qe|%py)$_t7v?vlWc$ljs_Vx6Qt;{CAB8hZ+%%s zABFm|Oq8MxoG(Qmv!!SwTZ%TZrRWp36m4cp(H6E8ZDmW*HntRPXQOBb0Y#q@P_&bP zqR$8@+C@Oo=L8h(CZK2!0Y!TWDB4Fr(S8Do4iHdukbt5?1QdNiK+$0WijELa^d$jB zM+qo8MnKV51QdNua22f!bzU_<0`<-Gu9u=B_TKe3p?>SjDmoSFYdcwrPIJB#oncGS zw`?i;jx9xJ*;4d9TZ+!HrRY3cihf{A(FHb&ek7piCjyEt5>RxBfTEuXDEftfqRRvn zT_K?8Dgi~;2q?NvK+&%R6x|@8=r;n2ekY*lCILl%5K#0d0Y!fiP;`rcqT2)%-66P& zPJ}vR4G?qVW8j>WqKWpGjqZl}tuL$SVW@BAR4Gd4d@1^yEk*yZrRWh`iXOA2=wG%J zJz-1HQ??X&!t}UZih|fE3MQb)A)v@hK#`Atq7VX#`~(z*5>OOIKv6gWMF9eeA_ypo zB%mmYfTC0c6s0DhC=CHcX$dGwM?g_}0*W#aP?V8?qD%x=(fv^8r~wj4XYWuykfIoS zTa-D>Z+%%s*~5IlPm`h?oG(Q=*;4cpTZ*FDQk07=MY-8h6vLLHJZvd?nJqu_VhJcJK|oPS0*XozP*j?LqA~;& zl_j94905h;2`H*SK+!7%6jda+in4||si#{-_6~KnF!zyu?UV;>VSek&Dykahi=8P& z)i_^@sDisIN(6wj8T1U8E55>Ql+fTH>Y6eSW+)PR7Z zh6EHfBA}=-0Yyy+C~8VTQ8NOHniEjef`Foy1QfL*pr|zgMQsQudX0dh*9jqIsUk(6r#xT_^IKn5QRgt<;Mr2th4ZDTD_e@Xv8AXxTZ-Ob zOHmKD6!m0FQ7^U>^=3;^A2y2m5>V8SfTI2c6b&GtXdnSag9s=ZOhC~P0*ZzbP&ABy zqBjXB8csmbTLcu1AfRX@0Y#$-C>l*b(c1(RjUk|DECEI12q+p)a20h7a~2sOferS% zj-8}vhy7)v31NQg%PN`@=KFk(6iwxPDSC%3Mbp?)G@UI)GuTozlPyKF*itl`Ek*CL zrDzTtMRN%#nnys~^n5m5960Y!%iC^|ww(U$}i9VMXX7y(6J5m59s z0Y%>sP;{Jtq7wvH(S|T5zX1}62{mv&mZEj`G1|#6zx8DmeH-SBTOdW>alRCtWlPcb zY$-a&mZI})Df)peMHkpo^dnn}equ|}MK+2q5m59q0Y$$MP;{AqqALUxT_vFC8UaPu z2`KuNfT9}&6#Yg((eDHl-6Wvs4+4t*B%tUo0*Y=CP;{GsqB{f>-6f#t9sx!739h2k zVNNdtB=DzwjCMwfUba8ee-P%kzO15u!hF*gNzo(Dm!ijPDf*W!MNimL^pq_{o^U;K zm!crH6a}-T$YD#7myIGH0YxDM6!{4#3MHT@jDVtW0*V3z6h#nF6iGl)6ahu42q;QT zKv5b3iqaBLl#YO+^aK=TAfPBC0Y#YzD9TJgQ5FJY4mZCVe6veZpD1j|Sb=gu>k1a*@*(gdRpr`=>MGXlkYD7R$V*-kr z5Kz>VfTCsu6g4NHs09HRSb}T{Vx@Ht4q-uJ358?tuL#nTevT2xfFHhd?|W^Ek!-pQq+?zMZMTk z)SE3ueb`demn}v8*izJ=jiLbr6b&SxXb=HKg9#`aLO{__0*ZzaQ1m7NMZ*awdW(Rf z5d;*CB%o*%0Y#$;D0-WKqA>&%jU}LH905h+2`HLCK+!}3iY5_UMP0(3@diksi@o{j zDn(1}z3a*0e(TFBnilR`y;6#%bG{VKU`x?VwiL}`OVMn$6urxqqB(3Sn#-1=d2A_~ z&qmRE1QabGplBfhMT-b1T1-IE`vep%A)sg}0Y%FQDEfeaqU8h>tstOiB>_dN2q;=j zK+%T;6s;kkXe|Ln>j)@XPe9Q}1Qcx`xQeERJ6{ijl==*SA$+c2+j`OAHJX?x> zU`x>jwiNxymZG27Qgo3mMVHu8^fOzEeqp2NG66+b2q?NrK+!bOOIKv6gWMF9eeA_ypoB%mmYfTC0c6s0DhC=CHcX$dGw zM?g_}0*W#aP?V8?qD%x7WhS5~3jsx02`I`&Kv8xAigFNKMUTRr_YIK1U-paGV=0Kv8J|ipmgBRF;6Eas(8WC!nYT0Y$G6P*jnC zqDll5y-Gk)Wde$-5KvT=fTC&yS5b7pxnh6>Zrb}rxdQGZ{WyD9yL!NHeOX1d13up- zDXPQyQWVFQqIk9xC9tKaE?bJ~v8AX!TZ$6dQq+JgMGe^~YD7R$V*-kr5Kz>VfTCsu z6g4NHs09H% z-WI(fMFD#!>79Vz`m%~<27EKOO3^INm!jEhDSDSJMRV9vG?y(!^Vm`}pDji2v88AM zTZ$I4QM8DFqQwLhy-z^V5(0{r5>T{^fT9lwC|XWH(Fy{JRuWLOih!ck1QdNpK+zfk ziq;ZPw2pwH^#l}sL_pC70*XE+plBljMVkn&qUix=n*kDNWp9gSNYPb$@A{K~-}&X=McY$^JbEk!%oQuG;HigvN3=ySFd?Pg2S9<~(iWus^x0Y&=>C^|qu z(Ln-=4iQlF1p!5e2`D;3K+%^36dfg?=okS-UlCCBH33E65KwfSfT9xw6rCiX=oA4( zrwJ%JLqO5D1QdNoa20I{IFAjGz*Y-qs}%K4dB7I%TVGbu4*_3}olxF0-ZR3R{YWI9 z0Y!fjQ1ll8MYjkjx=ldQ9RiB(5>RxHfTH^Z6g?oI=pg|`$pjSrO+e8<1Qb0YxQfmN zoN5M0-~;d6a}-T$YD#7mn}s;wiJc1rO3~g zqENOJg|Ve5oQn zfT9uv6qO{Ps1yN3r3ol1LqJhk0*cBJP*k3Pq6!2Qy+S}yMFNT{5m59h0Y#MwD5^q0 zQB?wpsu56Boq(bm1QgXIxQb#ToNo+}zfdwk^K+Oc;ATdTVGaD?+9P%15(t7^QEXSTZ;OzrKmq!iUzQy zXdqjP2C=1RFk6a-u%&1y8%4tiD0-8CqTvJ-y+uIL2m*>m5>PaXfTGa^6unJA(HH`X z#u898j)0=^1QbmmplBiiMUx09noK~^6atE-5>WIG0Y%dYD4I@i74?j8S{WdLtM+#t zdr8qlJ7z@qtuL$S-3Z^Chooo@=S$ICwiL}{OVNC`6urlmq6KUzTF927MQkZr%$B0} z*(h2W7Z6u&*69Gk^5Ky$4fTAq~SJA8pXQ=@axNINk&z7PADG%5p{MMIM^l5}| z-(e}*$@xRxAfTAx5C^}3) z(GdcQz9gXNC;>&s2q^lBfTFJnDEfwgqT>VVqv!?!MZXbH^g97XHwh^EgMgwx2`KuDfTCLj z6x}AE=nerzcL^xEM?lei0*W3GQ1p<1qGSS!{wAR49|DRV5m5A)fTDj1D0)J06?SqLb~ zNJMa9@sRGckEv1}P7m_osgpX zoG(R*Y$PkRSHv)>f6HxR90YyCs zDC$XY6(vMEPYjSic6(b?SBmVniM+ic{nnRN)GyNa(rGE`&-qd`fGtG>*-|u!Ek%Rb zQZ$4uMMK$AG>k1pZ?dImI2%Q85l}ROfTEEE6pbRFXfy#uZxc{7hJd261Qd-UplCb+ zMH2`pnn*y=Bm#;i6HqjTfTF1c6um=0(KG^zrV~&!gMgx$1Qg98xQhBjIyDTCz!v*6 z{k~Fk-rg3?j`Uk!R?)mjU#D-SXg=pl(R*wuTELc~g={HW#FnDPY$m8AP>&q(I z73o`dR*F97d@0(^mZCjuDcZ}HqJ3;B+Rv7v18gZe$d;l*Y$^JJjiSQ@6dfU;=t}~M zjuKFGjDVuA2q^lRfTC{*C^}9+(Fp>IP7+Xbih!ci1QeYipy*oyioPSD=qv$6-xE-D zj)0=`1Qh*1K+y$)t7vDWbHV@#Y_mVc|4fSZ*q?y>80ojZtfHSIeYej^(J!1YMVHx9 zbcHQNSJ_f@jV(pj*;4c?TZ(S5rRX=d6#dRd(M}PXdbmBB1CN0Y$e7D7r&H z(Om+H?h#OQpMatV1Qb0apeUJuqQ40!`iFp`M+6i-CZOnF0*amxQ1q05B2Sban4>6& z;3~Qp>0~@_6rHlSMVF*#ru~W*9ObvZtfG)8U)c*%OHl+{ ziXz!k6vdXJRBS0q%|=lg0*cZSP?U~;x3$AfPBG0YxtnP!vr-Q7!_CauZM#LqJg;0*YQHpeQfFRpgCw+87{#Mi!1Q%6+77 zzMz>0Y*Bve%PJ}q<$LQVDJsnQQdER3MMc?CRE#Y}#o1C6%a)=NY$+iYgLNREdD1R|zPpOh8c;0*a~yeKv5k6isA?;iYK5bf#51C5aoPefCL)apMVsUqVbkg-6+5HWfe7u@*TJ& zMGZM$iW;${s4-iLny{s)DO-w~v8AXvTZ&q+rKlxaidwNz)S7^zHUt#CMnKW)1QfL; zpr{=IMM(q{wI`sc0|7-H2`K7BKv8D`inlpV(Rc!iCJ<0Gk$|E} z1QbmsplAvKMNW-X)-D4#8E_Kgua;fCREx zI0K|;i@kR}H_C5)Sw#z?e2G`3Xd&lI(IU1KEoMv6`)ny%!j__?Y$;mCmZA^XQnZ{c zMJw1ST1i0BDgugD6HxRa0Yz&FC|XNE(K-T())P?l5dlRT2q^lPfTE2A6m24)=o12p zHWN^^g@B^11Qcx}plCY*MLP&6`jmj8odj3W{3vID0TOWRcOBo8qGtAy{%28s>&q(I z6Xlz8U5fT{z7*|aOVNI|6dhno(LuHp9b!w-7i=jy%$A}fY$^JZjiRFj6dfa==qmz> zz9yjP8v=@s6Hs)5fTEKG6rCcV=rjREX9y_zmVlz~2q-#BK+*RE6rCfW=sW>MKM+uK zfqrSj#vDMjI&FGT^i6h*M5D3UEjQEVwn#g?Mf zY$-~^mZG$5DN4siQF;Q3G7wOdk$|F11QcZ^pePFgMOg_b%0@s@b^?lW5KxqpfTEWO zD2gVaC>H@mxd|wWA)qJ^0YxtpP?VQ|qI?7t7JKtNGl0*dMpP*k7bDk_}HnQDLp`q-bN6_KK4b|j|qTVGaD<5a$nZb?xS z&X=O5Y$hK)@&(i!7l zAfTut0Y#k%DC$f=Q5OP=x)M;-jew%=1QfkNKv53@ih2@I)QfDF~#{1O@3xm8xQe0HG*N5)c#wtk_X3s3`V|y`iF_VsF^H zVsEI34HfmhuAT2EiFn`7b3gy{ob$fty#GCCbItcN^PBn2%x7k2Th=V<;_ss!EsM_Z z4?bR0E8%{*MVHnJd;BDeE~C9HT1%Eimy>1D6=Yd-C0Q0-MV3WZlV#C0WLb1ASr%PK z#-i&1Sabsbi*5v9(M

S_iJEZPjfqL%xOa{q`d+TrJ-k835|FSqFPTH)ir z%Azl5FN?k;%c8Hyvgm8FEZRzzMcVu;(R8H>iM}SJDG65+@k8qFn6acszG~MRFf== zYLR78k}Qi-WLcC)mPNJ6vZxMO7S$!oqIzU3st>@T1^_H-2*9F704!<@z@jDqENTkC zqGkXrY7W4nd;k`;0ANu|02Z|ZU{PxT7PSFj(QW`N+8uyJZ2?%+4uC~_0I;Y%0E;>R zB8zg8@gfr>cd5URmYa;8>A&L-Zyl2f_scCRPKKlZltrCrFN->pWlQ0tLJ;<_XFS0D!n~X(00a(-vfJOTNu&6fxi~0bts4oDE`T?-0KLCpc0I+Bv z0E-3zuxMWZ77Yeq(GUO@4FzD)FaQ<}2Vl_%02b{Bz@m`=EE)yCqS1iJqQYc+feDiP zj$d6D$)e?cVj7c7xLi>3gus1$%jQvp~s4S+?{0a!ExfJH|Du;@qt7R>}; z(JTNK%?4o68~_&01z^!p04$mZz@jn$7L^0AXg&ao762lP#wFt$Opx5Y{H?S7Wl=kS zrhjxY;eNSA$0oz~GGx(W+RLIPWLb0^Sr#oN%c5muS+txii;gGDq7%rn=tQzCI*E)$ zCj+qP6aW^j0ASIn04zEUfJLVRu;>f`7M%&eqO$;4bT$BsRsyi-8~_%b3&5gP04zEW zfJNs6u;>B+7F`IyqSXK_x(I+p7Xz^95jgtw|=_FSqFO zWZ2679Yp$EbOr5Y(UoLbbQM_^T}_rn*N|n=wPaaz9a$D#PnJbDkY&-0WGuP~fJN&7 zSadT0i*5m6(X9Y1x($Fuw*#=~4geP23BaPe09bT40E_McV9~t*ELso1qWb_?bUy%# z9spp`1^^a42*9F;09f=e0E;#PB8x6d#s`}qxn2D9vsM=M^pA-=l1#W?Zqeh(a7IEF zJwba}^dwmpJw=v9Pm^WQGh|uxELj#kN0vp;lV#BhWLfkg8H+Xpu;?WK7QGC>qE`S| z^eO<0UISp!>i{fz1As+u0U02aLsz@m2mSoAIci{1lZ(fa@_`T&4MTL4(}Apna$ z0$|a{04(|hfJL7IB8whN#?LZAa$oYNWt(Kt!+v%BSu){%xkX+sLx$d$KIrPL@SKkY&-2WGwm#fJHw8u;>>67VQ9F(XRk3`VD|Z zzXPynCjg870ASId04(|ofJH${PusC52Ed{W02ajoSdXKzqJ+dsSPnJau$g-#*8H*YLu&6Nri<$tis3`!8ngOt=IRK0D0a(-mfJH3y8*ChcK{Z(1z=G-02b{5z@qj5Eb0KjqK*J8Dga>Zu zKMYbc6+P3x%g;qcsf7FG7IjI5d)JgjU1=|ix{+nko@80noh*xbkY&+cWLdN~Sr+vq z%c5RnS+oxsi+TgFs1E>(`U0@19{`K`1F&cS0E-3!uxJnfi}nRz(O>`;4FO=$PyiMU z17Oi`02Yk^V9|a6EE);GqEP@W8V$grF#s$Y3&5grfXJdwsrW<_BzKix3U!u6alg9W zKb3I5+@gb0;qs&`I+*sd=n%3jI+QGn4kOE=!^yH}0$CPKB+H@_vMicJmPM1vSTqHI zMWp~NnhL<8X#gym4#1)r04zEJfJH|FuxKU#i)I0^Xf^Me_kzv;crbM+2~EApnaO0V0bIOvSG?L2^s|Tr^%5t@4*3k4YumFSqEpRQP0` zELuu?S+tBSif` z7M%&eqO$;4bT$BsRsyi-8~_%b3&5gP04zEWfJNs6u;>B+7F`IyqSXK_x(I+p7Xz^9 z5&#yh0btRk04%x;5LvW172j%ttfMe6}rbRPhV?gwDe0{|@A0KlRL0a)}90E-?5V9`bZ7Ci#MqDKK( z^cWzr=!#UllL?ahgum)|r7T+E=b}xig!|=bpRH<0l=a+0a)}F0E^xRV9`4O zEP5A!MehNy=zRbdeE`6sEdVU~5P(G=0kG&}02X}$z@kq9So9eHi#`Wn(HDToq9;=E zg(gVuP5!Fmld|YH8<+WID&c;)Mc<^tiyF$JZ)q=!z9Y+`ZDd*WJy{lQC(EKA$g=21 zvMlW02T##dfJXfF#r~2 z0I(19U{PBD7PSLl(H;OS zY7fAo4gf6b2*9EO02UPju&4-tMa2Lt>I8@^O6J8go0vrd{UxGQUi3`=3X>G!TGAg8*2xF93@M1F&ca0E>nKuxJ#5jn7NCUvAN%dEt@vi^S>o z(GH`%EIOPlizbj|(L}N=Dk00FNn}|xnJkN@kY!ORSr$ztW6?AK7EK3W(F_0<9Ra|i zBLP@66M#jt09Z5|fJJivSTq-aMMnX!XdVEI$^ckY4#1-M04!Pnz@no8ShNs;MT-Df zbPNECjs;-RVnAfk!FlnOCP;3Ei*tx9YU5v&U6Pk@zucnbdExCXWzq4pmqjO#WzmUb zS#%Ov7M)C%MW>Ku(F(FGI+ZMoP9w{r)5%zL1^|oB1Yprw04zEifJG|-Sac2mi_QgL z(JBBIod>|8^8r|N0RW3G1Ypr>02W;Yz@m!*Sab;hi`D?J=u!X{T?W9SwE!%-9Dqev z03wT)=EYw(L2^H{n7K?AedpoIyoCD|)Cw{(TUBeZTP#T4Y;V~H$rt^lrR4YaYCv|f zw)s{)+0`BnlgR^X1VNqTCAET}LGr^?5Hv~dUMC3hle6jtLF?q54T7L;^4CT|&>`8o zX%G}8Pih_nU6RkX2!ig(RO=wlg&XlXD7#U{vz% z;vg88{JnD!j8FFM76gYTPw5^66O+&H6$Dd~wR;7@^yERkgJ5QIZQmf6oBXtY5R@m| z4+?^X$)g4b!Q$k-LxW&h@{i#`aALCm$RJpeJau#soRNHSY!IwW);%By&PyILJ_uGP zuQ)ge)+9eaGzczFcAO9dS0~F#g5dh(eUpP=UGlHeAh<0#aC#8jl|223AXuM#X=V^? zNY-&E`wOZkuD^@*kYSIq{*QvS14 zgJUWGU7_Kz)OQdvqg|U?XkF~|Il>d{gWwDh1m!lJ7smHe19*U*>|BRdw zOZh*FSQ$(CH~r6xrTnYft79quuI-vw%D*gmc`W7McDp*3@~enZ+l)rrOMJ(mdKextG{sdxMEag{#KgLr25WXXp z@^kRcSdh2eU)#SrI^=2}YsXI5qyE{pPwRBI;aF!oq)Zw+m||;AFNg(oXWNk$>)gV2 zTaX@QwQgCO6+7F@?*7A1br+^tUuTQ#ZvF-JV%gTVYfYc~+jhUr?)6RNAl5C-g8Elm zUt)VI6!{#w*EADtvO}v|=n;*n*V-rBD;+ZJ@c$%c6Abow@2#dIJ@ix~q;~huzI^KWk;rGc;uSl`=@94?iC;ZvM@cvi%#3TX<^W)$l5&T zGwf*tz71y4_{*ag46(*psV(2$bE&nlZ4fU#zgBu1)Smy=*r369^FX8r`C%th@x_@s!_WX6e!nT=@GKm`OW^H^mKdzWx zgDJL8eKrl+X)PyoD9lUG=EwJrKgSx|cH8;N%b(i*v+cHd)AM&78#J0^c75iJ=GlO6 zqj6E|tkh4xoVMMTZM%A7-la#SSM&Z&H?&Rn;go0Uj|&={Xia>9D`;}739I*c;_QLxo;}uNw^8Z!TCr)_718DyH7sXV(BLC2rrI9qZIO|k&tiVmVp{!e zj4vh#qtzK7jmb)V|K@u;Z6$1VZhYwZ2bQK+XXSN4Mtb{w_Vd}>Z2M(eqZ-!h2K8*f zyMHY6?c+=I`F64~zGZJ^zCT>~>Dks<+p>>uy02w=wg+r`CO19X^~axedNWQce5kVcID^WPkMN9(BK7YZ|$#y7@8%yq}w4a;n~ z)|YF~UVZ+ObYHgJ^6^$1vc9alW#>*?wGP(GSKxbA;Df^AzUf9cZTaoWXmbqMmI%{* z*+1+!K4{R#nl!R5s&>&Yc;dp(U`D$_4B)#qSk{~)-T`ehg(?vnUg=LpYFiV zAO3XtaY2Itb|&=>l+os<-wzm@Zu9&t>tBuz(ciB5=y~sTSUvZ|iKBx?ekx9HjU#Me zck9Xp>Pq$iYnfJKfsOI4@eH%Q^RQ1FrDuEjjt}mS*6Z`#4vf?|`|Bs~USeIb$0P4b z&@sJYS*a6V{`KDIsJrd<>%X)iJIaQ(Hg-=tzd8PedlpvT@YcG?>5a5*^*zr-8|k&1zCYPEZIBaf z+R;&)tkk;?yuLa*1HAqAvv)_O8{oQ;z<;0yAFq}E*h`^5AndgqJR z_1LgF1 zMDct0c}7-~sW#yE@Cyrm-tl`Fv&lM`Pks**7WT9``91u>CL3r2eh+{2VAK0O+-_m4 z4fs9$$wG+@_&xkNBP)odVr^>H&W+b>Tyy{WsaUdp5M;Cta&z}F6a?{lLA>T(xqIjK z$Q@GKuAMZ-m))0dn|57=7gX_d5)+Fh!2p?AZc z4ee^MAlADf{o1`@Dwdbkr@@8&8hR({hE*odsDE!i+g|mm&O)qyRo29o-{92aW45h} zYx`Upo_2gJ$Y^j*KfCs7WFrC}5d@8y#sn$|yfd?Fru$)iwR3IdEzbsH!6+~D(u3o? z_?2sB@I!3WS_}WU+1|7^qrLdQ(1`^Hco}cHc$?8{eJFkH8`$%(f8LUYV!;?MQS<$) zHXl=^`TjJv*;|t!X19O!*T+@4+4Xsl5fr6o^r-d4hx6=ld@sAlg2Vk9+pjAed-VtZ zc#xgH)(6(veznkNtq=G^q)+8_p*>ior}BY(drYvVPX%nM z0c(B0&!|3?S3m8g7vck7MPb=mADC#T6rbugs~hbe3&wkSQ@DZcmjb&R_R`7j@!+`3 zwLaim+?%o?(!KI6=G)Ak7p3nNIhv~KmO5OU#5a#$T=~4b`V~-m#eKj}9qFF?fVS1d z^tSp<+sYrywRr}lH_!BRM~c?^!r%dyDb^$-_Iu45lFK%25GyDsoL5pfwQO!-*}Tbx z^Cpx{E}bxU-kkE%$>pU}3MbE7G`D2qe47M9E`U07H!bI#IX3Q?PVCR;x{Rd94Zcgq$XV$Da zvyGX22s6WH9U*(XwFhulG2S^AhPD6QEsSNwr`ZJYh6VNrJuTmddgkX>4CiMRhPAU| zVP3DWcJnZ_lxHc-DzcaMVs*n@FZPeiyckc%0vp}Q8r2IMHVIqo9@dU8ve{}rVV2D( zJ%`GgmsR_JIP8YK zx`w_woqR(ShWSNdo-ekAw#$FksX<fEH)hTM-4RWl)WtqpA=A5{>xn-SK~j;bBaw4G*}js;;2o2d)iDnD%O zsnAo4uyOM$!yOq88=KaMr}?$5IzJn2F~jEBI$f;~UgL8M!sh9LBvZ85Wr{gWk+NQ- z+g47IZu)O=xAfHUSp{K3AF@?X11-9zhoNDOcvIW{@#`~sw)fLi>-bAcEZewPR;y5( z+q>)!A?fIQt5aI^#=d`BM1#H)stnqpWz*YsGg{kDdkwSV>#PIS;;$|#$ck?cR=N;F z!)mRyGQ$Jgim})@zpLu8qy3u(tf@6;(tktR0!<`#L?Tjj-lf zEqeX4f%r63`$voTB}+4gMXI(y)7oJ*n`OE$_DC4bJL*hf@m_^t+cwtag$V4c%iMRZ zHkVjrT!ZjG6Xd_%x&Jd2{3Mi-6<<&g*7G4LVB5BJ+|I`T{q9b0TU(_e>79{2tm+kp zZCZx)efP1hdIbCT2Wh>m`bA;W_@V+o*?BuZYX7T2_99E@6}HZ*6YY<`pAr6rqSj~g z*-VNIi%j}&Te-KbJBN)Mr~6l7aTTGf4E}wE|JDazzfRNKv8kqi{NtE`_+`iS{HILu z7N1DsilZUj*Oq@j1`5;K)h_PdvM^eqwpk5LKD&O4c0ja2qqSsn{a@+qRQ3Nm>Dc?j zY}L(*gTi`ynwX^Im!Bh+JGnZzR?0Ty66J(*E< zX2W=gg0OLXoS&bnTp3guta2jdBB706BOGEEEb%r|?b75xyF`e$NMD)6A6Qb5G0a|= z88dL-34@9T2VRT27Y&{;DH`n7rDCva|BAtG-8E&G?y$ZzF6t7E8`xjd6x+lzhR>NZ zw>TKlcl?C@`;F@q&3gb%x>hW2Pf+K|<#wuAZvQH?R0liJpj*XMJ<@%eKf7$kwArOo z^6hnm^y2!fU&Vu%iw&@v11r{}*gBJ*zK2aVVS=^p+-X8Ihhke84F)l{zM5OV$~o8; zu*s&(pEYYyFlK_ke35>^qf6(%r7qD@G@mYXs;|JF6`iwDp11dL^Z5~Z% zs}pTvn@coMrF(nQ)HZB-q-}Jy>sm20>kkXr_ zh#F8jY5ugpUcH+=t#m@^>?t!!W>1(oXZEyc1#NfP;_cr&ZUb0eC(V)c-) zsB-OkRIEv{`5g=!c+iBt1IDD=*>2ZLn%+KCxqG`6|1Cw15BS?$t4vT_)H(3Z=coVt zL)PNTF87m_}_f>R4=}!6-~b;=cfP;f(p%}gUUw@On2=FKcLf_q)7d<<4c>S zU&Y4tGf8@)zLncyfLYgf%)Z6`r<4D&!@^HGzFyJUr(#CMl?MUR;%sr{QDGZM3&zw6 zC+(CK&9hSRVskuVMU1SpzIYIRNcPIz+ue4rbrXSXg`&AI;HFfyq3CbvZ-;)j=+G~g zmlew>F0w|p3_B11O|9ahXxYWZl^eE-u6wF0h!PzMKBMlHTiy0a)Zb2Yyi(<2xt!h$ zl}&6%M@=eaWOo+#(?;~2ncgfF`@nXT_D1CyxwGcf^=~uRWW|-@6jw2)iZR`+dF8Rf z`P{Zvv}_;keXz(gtj4=ywV`#z>NwYy4#A*sc_yzQ(GSG{5&XR zZJ2R)T(iZdJ7imeah0=3cgY_n#@Q?2>B)-i;V&An6G(c%cXIkcG&-*gtY~d}Ky$3@ z0sGjtkj7Q)OWOs}j4R!+GoVeCo_Ttd?OV07$2JXBtcZD6MQnRtB$}H&Ao!ViUbKyh zqoQ#=Dtb{|DMy8ml}^|dge|RX`kZ;?6%X3%NcSzRK*ip#xV*5VDBTC&L#{!wZJTJI ziV&3o6jvHhT&V#2r`S51Zp;o~`xl$d(OfHc@87qDy`eE-p3Y^JyV-iBO;~J~Qqdgj zFxEhNOApy^?6?U7`i|>6VeF8D2d2kVc?2p}D-)n{U)a#T`|Y3KzekUJe}Af=IN#r) zD(c>;OMcsVr87%Q%1YbicbqkO?)+YpZF80`>^Q4)X9MNa=g*pCb?VGHCFLFM?X6z6 z&!#xADW}d|(6wXP+>TRmJiQJS^|6ciR{c!3#Z&v=mS(8eqOtGg8<9MeyeT4B2aJzqhyxAL%_EF&A zFT2^tMHbhrUL)w>??&q8?~C`V+4{t4CuN_UI3;UEcxvWp@zXQTiVd#WJzg5iso8o- zZr>g@af!d}9K;H3FznuOM8Sx@L-q@@Qi&1O;yKxQnRQ}yWA)<=Vhv-BVvS=>V$CvI z#_Y3B|F~5}nZfseRh=O2@4HsH#r3W}DDH2&R=LIPEmwOhzsfB$ux~2_pF|%9u%T$Y ze<~%qMdSTf4#?i#Kg~e)_ABl43S=MepIspP_~8|wEvWpwfsc<@e8M}L+CIq;4d`z? zsF+cj#QmdTRc`hLkSfXNS8JF2_qB}&_IaNww|L+m=Bd2JgSvrzv?#q*eLv^f_Gnu< zI`GfoblW8l*(D#iOD^3dm+g|5?~?tq>)d>KmlCXczG;_y-!A#dUGnR@{7uGC|eLK6|bl=hx;HDSb^+k&6ELw5-aw zqF~nt-zp=kcBaU#+3mAtcF(cToK5uF$iArIwXuEwLfOAN;C!oB`>@P5ulDtwdUm)u zw@-$rxqY@Y$Z6(Z9jK*s*Algx1-9AFCX91tF@nK$CqdS98pew5cpRfd^yX! z8o$MB3;S4;*OvAvAMy9aw~6l*_s>`7v@&14+VllpZGP8Vwa*m>cX_t?KI7Hq+r>VY z<@sgRH@#Z>KfPM}M)o-*Z{OCdP3QlpGN(-tT&dj04pZm;*vd(RiEEe;-7f6`R&wr|4fr_uj+PeI^Sf~*U!2gWZ0qa z=j{yJxqj4pt*dHX2{P=e*e+|SKEogdR)?b}r8+D~YzjlMQ?Bt-7#YluuH9$UYJ22Y9|)_1it7{JUxw`vRPg@2h%@?I_QusBSEd^7E=$ zU7~CsD@{)~+;*r>e~{|A-J`r#_07Ga{Hba)+wneqd(|nuqkNR=jeVnhuj;n`QT{`< z+n^}-S6w_f%BQM6IyA~Js%DRfa$VK^Mn?G%)$>M2`3lvy$42>c)%*jZ+);Jv_$ZgD zt~)r&_o;3_G|GRecApUCfvU%qMEP{pO(wc;kC#+)rbfBG>Zs{aK1}t3Bcgnj>boat^^e5UFXi=+ICYW1a2 zZm2qDd6Xxpu0A2k*QmaKQk1_|ZM`DO#i~b~7UiQ=Z#yH(532rrR+QssN44iUQ5~Xs z{HiFQt@_mYQGQLe=ISUnRvmY7luJ}EUK8c(RJU9fQhpC>pF3RVqK66Wy-%w579_6O02izIu$*ODaj`9tvAKe?}?^N5~ zALXv9vo}QfSk=28it;0>zio_i;*qHKc`T|UR8M|9%BxhLdos#zspdTs<>sp6pNn#- z>SZrP`6ks*Hb?n;)jeK`@}8=5UyJe*)qCEE@?)wy-->dzx1-wc-KdUKUGaXD&sTk6 zOO)SHt@Ck|Tc{rVX_Tj_UjBKMZ&v;6%P9Y#+F@&yd#KL)Hp)v?*KdpRGER1f_#$}?22v@2>qo^MtC!aif|`6pHT0B1Vy zty-Rl@^aPtt3~-qRr~61diolwgK9>3tm+x|ja8rjMXE2`S64lMpxVH`!|J(>>f!cf zR?kPOUTxoM^?bYPSN8Q*&%dY^+4o#M_flPuALSENH?)lM)2c1)d*nWSq3YhM{k(=j zFk1OguSvT;R4o;st6Z+SNc=?Q6{=^7uU1~8dWHBcst>3>rTUuc7O%GaPgK7Y|5-I| z-~9CTNUAnf-9vRxueLr%s4h`GS@j~-n^iwl{Yv#u)lPPS?ep1Nb++nq)$>#@ReeeI z6V-SEQ~R6kMuQ?;{wiO$l>#;RRZr>h>Xx<>Uy)i+hQtL|nmH28eR zs2-wvhF9CaD^)L2y;SvD)f-jsRJ~Vqqv|Hr=T%=)eOvW?)z4MGR{c?Rhic5eJm>uh zRcor|sWw(^uG&_$gKCyvf7^QIsHRlwsy0#0SKUi>AJu`XLsUnpj#E8cb&~2L)g`JY zs@i2lx*v9Vkgls#FIBaN?KHQCi*$Wo^)uD4RP8jK9{;oIAFAoEt=M{2i$&vWsQU9& zUw{ARw%1mwc9^BJZKibXtmLA9%D57mCE zgH%VVj#WKGb%N@2)tRd0stZ+@tDdBKrs_GW7pq>TdY$S`s&}cbSKX+(Nj2?%&FFO_ zUw^-OwWpowTBhmj5DPNwplBc-6qGHRRbDd5YWcjVPG`v8geVUR{8j&;U{YCGP+;#< z6gVuXeCb9n8Kp-}@pt>};}=usSgZ7K$)rj1N*6>8BVyn6sTxb>`HM@Mbu`64$xQ#I zj^=263koLN*Gfw5Ga^-%I(1&jESsqBm=Ogf<>m8cOqySAv;EI+_Vm}TSStSyMVDQg z+U85&TG(HoE*`~T*Xewm-*&fqw%z}`>56QcU6)(+`&hpJ{MNzl)$HEK?tZ(?4oE)+ z>e;YQ<9A=)FuT(S8w_^Z>j+)_;Ma|zeJxj=-?Az8_5144{M;qxcc2Z^#%EEycPzN6 z3Se-?F4MhhCzw~+XjR6Q+Hlq7uAXaiu#M#F;hg2#)4#th_qN`#Am11_mRoM%Z}YPg zl3muM=Vz;4F~8Gom^L;TY_|FNblezsih-*0yS~c&YS=jX=jU_U_&m1Q{BH6G9o-mr zk>#rMTW|C8{p9Og%kIqY1{?M^?t|Y>9~}#Rwf(`($NBv(Ri-=f@K`XEi8Riqdql&G z+HBMHAz1b0`t3oxSMA@%D(hR@#?e1}y5zfQu9fsHIU$z*|14x*rr*3)+3mq_n{KXw z`o{g7t58U zd#BF%_Wn;%ah1Q_x^>CV@7|@Gy=UsTi8)IL4j+{MKB#6IvsVq7ucK{)(kYCN^|rPy z^@1ID7Y{8S)@ewm!GHbo=U;<=?z8`#ZA<$P+1@8Pa@(?_#eAAAtqwHSPVVM05 z?4I1TBeTV(9h-_?-H}-wwEz9>Am7{e`?+?!^^n#>Ta4JWBZ%2}n{G>ftBLKWUmV-{ z>c}5Aj%zlo`OxM=@&|7%@#$?j``YpjwPn>Cxh*L7_KgPD8Il_M_>Qd`?LOD;6YbvT z@g19j$9HT=wx3vg`X$l4M(z7^)4sKaZ7zA#`twT3jt3t&toJV~zArCN-uUygm%UlN zTac{Rr}`cPf*J+cc5RTky#KEsT=rg2f9p4e`@i_w_ZL1?qrmoD{>0!&yRe8HvTxWK zs(ylPsI^u1yyc8oR=FL78L{k@c3qZ{5$2fs85xOX2IICPgNzXk>~%5wAb!}|#>6l4 zsYW)Om_~^lPuXFiosKfH6Bn5UnVF%#YnhRmu&c%(zPn8j?@+t1O&+gjqvJ(&#@TR~ zzV?b`ZA#ebJTr5*&>u?^{@a1O>;J(vw^$rxwpDCqu~U%QPO+)Q&OzoLicKtb2{PL& zHn!L`$n2ol$YQr3v!h}|i+cu{1&R$Ub`LTO73*8<5o8uA*0We_-6~eD>)HC%Nx6<^ z>sV*y+McavU6k`YTi3cOr#xHVx+y0;Tj%yvuI1T!*Il`$XX{=Mk{p+oq@NE6-qnzd0`qx)E^lbg>r=028`qy7M z?%Db`Ksm#5XY1cU<(Oyd-ymgkAv-g(b^K}D|JD9#qZMVy7)2Q}R#AqGQGKP#- z#*l-QG2~!n3^_y@Lk?BOki(QQWUSDPzcFWel03j3K4U7&28E zL#8QX$aG~4nW2m!M<`>+k;;)FL*ifC{;&3!ooF(LMuwEw87gyT!p(6*=7wL}$h09x zsi_Q^rzk_p6lF-cq70d@C_@$~%8;WKWynHB8L~)Gh8&}aA;&6X$YNy-S)z;~$0=jT zQe_NTri>xWl`-UaWehn%8ADD~#*mYgG2~=r3^_#^Lslqb$f?R0a+)%RoUV)^XDDOH znaUV)mNJH%t&AZnl_NuD$7|RrqgtUo;AGB;3>og{lXDVojvI1*Si>F#(}rB2rZVJ0 zMH#YMQHETkC_^q*lp&WW%8)gRGUQT48FHDT3|Xs)A(ty-$Q8;Ma-}kcT&0X5S1V)4 zHOd%rtulsOr;H)jD`UtF${2E^GKSowj3MikG2~`t47o)aLvB^ZklU0o{l_47xWyphy zGUOpe8S=2A4B4nCLmp9-A&)A`kjE5d$R0b+CzUbeDP;_KS{Xy0QO1yG zl`-TwWej;<8AD!B#*i14F=VqchP4OaW>;us-Gi@*G$vYXedate15FNe9-=x`0{^te^D&H62(- z>jP>yu%0#mR5#$ya2f(~9av8r0dgEzPa6ZOIk28K0c1O{o;C#}99U1A0kRxePn!cm z2iDVkK&AuhX$wHyf%UW{Aj5z^*J%ZaIk29#2ACiGlK04(YTz@j|?SkxVWMLhsmv=;!2_6A^4PXHG60$|ZT04(Yaz@k0?Eb0ruqJ97@ z>JPx80RSu-2*9F204&-UfJK7=STqC>S+sjB{dw7(OZ-&SRu=8$N)3%A+%LCizgXC! zjw~8Uds#G!EQ>~yWziV2EE-FeMdQe_Xn(RSI)E&T4kXK>@nkGI2!KTg1F+~202Unz zz@ozdSadi5izWcDXd(cMN&r|i34leD0a!EzfJLPMESd_yqGgN!g2anImM;KCaZ9SR(y-Y_q5=7EZGl!_()Ya@xzH z`D9tNfGmrSCd;CQWLdO`EQ^jI%c5h+vS=|`7A+xT(QyDQS_;6TWdJN%4#1-00a$bb z0EGkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO-2=d)djVLq z9uQe{K`j2V36eA3pOjxHiADl8i-90kG(402Vz1z@ldXSo9nKi=GEy(F*`9dJ%v{n*mt# z5&(-{24K-E04#bHfJLtXu;_IF7QF$$qBj9p^cDb%-UeXNI{++t7l1|Y0V0bYh{YS& zCk1l+TO64iWYPD2b^U%U;eNSAAH~8RO=Z!?w3kJnkY&-QWLfkXSr&axmPKEXWzm;p zS@acI7JW^YMO(>O^bG)uz6D^>cK|Hf2Ed~40a&yhfJHw5u;@ns7X1XkqMrd+^a}us zb^x&GR{$3M2Ed}<0a&yXfJJ`*u;@3{RPFWjOdyE=YB3~ zn~`w8+@cN{;o~i2QAgU#q5`rkDkRIIBC;$hCd;BuWLeaiEQ`93Wl>kMEb2zaqCEjv z)E$6DJpfp=7XXX)24GQ702cKEV9`DREb0xwqCNmD>I=Z4egG`$55S@U04y2^z@k9_ zEZP@KRL2}yLXN@x3%c6<)wrA#ujD-8;7LCpb zb6d-zF|?OOW682;99b6aPnJaokY&+b02ZANz@jq%Sac=;i_QXI(b)hjS_#0Sa{yR$E&z*G0kG&i02ZAO zz@iHPkwxVh@dYMG&R~CuXud4k-CuRQFeBl9xkZ;`gcr7zMQdm;i!LS0qRYs#Xf0V5 zT~3xoSCD1Vm1J3T6S_iJEZPjfqL%{R+UM-vC(jI{=Gz z0002ciTz@onZSY)3WzQlH;y`yd~8~eMlF#r~20I(wFO{NI{+5#0f;Qhj>pe3L2_R4OQCA<=$Za| zelBVsPq<%hQDHp1wOAGv(Owo6lVwpSvMlOMmPK92vZyOr7Ih=bqCLs7s5@B}^&n%> zUH~lG8-PVU0a(-vfJOTNu&6fxi~0bts4oDE`T?-0KLCpc0I+Bv0E-3zuxMWZ77Yeq z(GUO@4FzD)FaQ<}2Vl_%02b{Bz@m|W$fAz%_^T#J&bfXmR3MA``?+XTJmG%1MdRY( zPn~7a{ZE05dbVY5`aZB0a!E(fJL(bSTqNKMRNgI zbQA!K<^iy%41h)DfXJdT@pz*yW>JQpe#Xk8ZT>>`{CL9sa*Gzl!@ax7qGM<;i;gAB zqQzucw1g~+jw8#WrDR#Oj4X?mlV#EIWLb0q8H-K?V9`kcEIJv0MW+C;XaxX^P6c4m zX#gxb9e_n=0I=vx02ZAEz@oDOShNy=Mdtvp=v)96tpZ@tc>pXrAAm&{0I=vn02ZwV zV9`Z@$fBd;@rfo#PKlq37RsVAuGGcxg!|@bQ(G37Bx)FdyHvzC{9RQ1N24K-G04%x{fJL_fu;_LG z7Tp2BqB{XtbQb`N?gn7dJpe4a7l1|U0a$b&0E_MiV9^5rEZP9Tq6Yz3^bjDjXiYqR ztqGDd$St~57VYQZ;dsLRa*G~|hfmr+dq{sWWE1UW(c@%U^aNQJJxP{DPmyKO(_~rn z3|SUEOO{2?k!8{IWGs3CfJH9?uxK*?i(Ud?(aQiVdIf+*uL7{>H2@a94#1)}09f=U z0E^xNVA0zEEP4lkMehQz=sf@yy$`^m4**!S1%O2#0K02X}=h%9;}9^Yz$Z!y3J0(U-KBMPHF+(br^Iw3RH2z9Gw^Z^^RgJF+a=MwUh2 zlV#C%G8X*+z@i@kSo9MBi+%=R(Jufj+5y0#UjbP38vu)b2Vl`o02ciLz@k3^So9YF zi|q5=(K9eCiUF`F1As+w02XBeuqXszQ5FD;5&$g921FKp7LRu_L2@qi3+m5h(VPCX zzglL({c?+HWQJpV%c7dJmqoS6vM5QGMJci@$|K97+GJT&hb)Wgl4VgnvMj1k#-auQ zENTeAqDBBLY7D@lCIBpI3c#Xf04!<_z@mHr7PSCiQA+?8wE|#KYXBCt0btQ?04&-a zfJJQqSkw-HMSB3Ss67CSIsmY!BOtOUH#5G_1j#wb&qdWUqi6c>`_*+pX2Sh)i#lb7 z7xk4zooO$Nx{zg2SF$YXMwUf;l4VhMvMlOBmPLD!WzpVbS=5t^MZEx6v=0D_dIPYi z4*-k$0fm|FKc#*vy3c78Gg`T7LBL9EINoR ziw-8sqC?2C=uomOI*crf4kyc^31nF`kt~Z!$XGN9fJKu5STqHIMWp~NnhL<8X#gym z4#1)r04zEJfJH|FuxKU#i)I0^Xf^Me_kzv;crb zM*|{@_RoxG4ls+R`a2*8$f8&MT(mGV;eNSAi!;MEgJjVX+RLKj$g*fDSr#oL%cA9E zS#&&E7M(zrMJJMF(Me=kbTS!>P61%i3IG709bTB0E;dFV9|vDELsh~qKg1nbTI&nE&*WC8bD;xF`4n9 zCP+?u|J?PlvM6R>c+I>tGvR)@MOS2oM-G-nSJGYzhMYjO3=vDw0-3Gv-+W}Z~2LOxi1Ypr!04%y2fJOHJ zu;^X@7Oe+h(R~0cx*vc=4*;-e0|1L21Ypra04#bKfJGYtSo8=WvS@8)e5DDJ)7#HQ zm&>9T{ObDA%!K>p7Cn&}-ab?oJxP06^b}bZJx!KH&yZ!&vt(KH99b4UPnJb5kY&+} zWLdPCj72X2u;^s~7QF(%qE`V}^cnz*UI$>&8vrbN6M#i;0kG(802aLiz@m2nSo9tM zi{1xd(FXu5+5*6$4*^*85de!m24K-A04(|xfJL7HB8xU<#$PuS;R`#Q<280l=a-0E;pK zSQG-VC<}l^2>=#l1F)zX0E=<}Sd{SmEtm~g+`qGTBM z8YzoXw3kJBWLadtGaS95A&cy1y`wCP>XKzqJ+dsSPnJau$g;?O96OqyENVo?qQ(F$ zY68HbrT{Ez2Ed}`04&M}V3GX<^?EzTS0f0pv0a#=|Cm(eTi|nVTBY;Kr^Xn0aEUFpCCz&8Q4gGW1 zwZiC`{zN}96^9A;%Pr~}h9``cMcrsGi}obTqV8l_)PpRG_9Dxoy~(o3eyuv{pDeN; zY>%=m+J`KQdXurJ4*-k$00kCK^0E@-|uxKm*i^c)4Xn#OtQRgszy$O=jJKMzR zB8xV7I3P^8UvAOCVfge|S#${PWznHzS#%g#79CEOMH9%fXd+n_m5^o8B(f};OqNAc z$XHYgz@n)DEV7?lk9HOoO$T7n3;-4#0l=ao0a!E>fJL(aSTq}eMRNdHG#7wHM**;C z9srBV09aHGz@qs8ELs4-qN4#=v=D$rivU=33?Q;-d>H@M1j*UpmqG{0BL4xY%wxlZ z`{fob4Z~Uo$f9Mmmqp9TvgmlSEINTKi%ulVqLaw7=wz}iI)yBYR*+@UsbnlV4S+?b z1F+}}02ZAIz@oDNSadc3i&g@#=o|nRoeRLCRRAnH4}eAI1F+}<02W;cz@pUvEV>AQ zMHd6G=n?=HtpQ-sr2s6t41h&z0g**Z!gv=GB{%)EV`B~i>@QfqU*`B=mxSZx{)l4ZX(N~b!1s|Gg%hhLdK$70a$b!0E=!1V9^}_ zEV>hbMRx(P=xzWO-2=d)djVLq9)Lyn0kG(P02Vy}z@iNREP4=tMGpb6=wSdBZ3JM^ zBLFOV6o5sK0kCKjAhPJnFn){)lC#C1>0c#_TDww@hY9z~EqXc(FF9BiJwtn0^ekBx zJx7*B&y!`*3uIaJB3Tw~Cd;Ci$g=2VvMhRqj76^ku;?`a7QGI@qBj6o^dk02aLuz@iTTShNLzMIQpN=pz6YeGI^&PXJi-DFBN;17OkT04(|f zfJI*dB8#33;~PzooFiSFr)1Fq{)qNfm~g+`qHn|S!$W1!ceIy9+sLx$d$KIrPL@SK zkY&-2WLfkRSr+|FmPNmiWzh~Y7X1pqqTc{m^g95Hb^@^I4*(YZ3BaPi09X`c>0%3u zVgM}40ANuZfJK=AED8Zwlm)<|1OSV&0a#QGfJHd~EXoC7QFQG!TGAg8*2xF93@M1F&ca0E>nKuxJu~ESf-;MH9)gsDvzwCXr>)WU?%pLY76PWLY$oEQ_X*v1mE~i)H|@=m-E7 z9SOjqnE))B1;C=&04$mVz@oVTEIJB+Me_hyR0hDJasU?12Vl_x02Un$z@mi!ELsG> zqGJG9bSwai76Y(o2_UlQkgWKdCP>a5{`sOqWzpsSLiTZ43HQq_IzB7>wNw_JKzmtq zB3TxlM3zM-lV#BjU{2Y^NA z00E;dIV9{Ct7F`a& zqALJcbR{6NXjxXg*;KP=Kfj<}E{m3@pRi>m+%LE2x~#DGbXjyg?PbvoWLb10Sr*+y zmPPBxvgl^AEV_j(i*6;$qT9%_=yoy|-2uR&I{{d97XXXy24K-W04%x}fJN&8Sacr% zi|z+t(E|W1+5o_!2LV|05CDrF24K-f02Vz0z@kS1So9bGi#7qU=y3oRJpsU?CjpT~ z*JQ<~m>@Y#{DS&gS#*J)i=N6#xL0btR)04#bBfJN^Eu;>E-7Ht7w z(T4ym`UrqU9|N%H695){3c#Yz09f=n0E@l=V9}QVEcyz7MPCE3Xe%JH=$WkejV4IW z>;8!LtSq|NpZ0%~m2kh@qVKc9XJ^Wy?X;IgKage7k7QZ&6ImAhOqNBzkY&*hvMlMSlRW=uZF^{RP0HAfc!2SQG;r~z3PH6+WTMr2vkm@JE$kY!O*vMg#wmPO6UvM8U7MJ)hW z)DnP2tpHfm8h}M@09dpe0E>19U{PBD7PSLl(H;OSY7fAo4gf6b2*9EO02UPju&4-t zMa2Lt>IA@|&Hyax0>GlK04(YTh%Bm;h<7tVa)$ad{kn+UEb2#=Mg7ULXaHFj4J2dHAOIHa3&5hm04y2; zz@ni5EE)#DqTv868Uetf{Qy`r5`aac09Z5{fJI{fSTq)ZMdJWiv_Alg4gg@$fdDKT z55S^>09bS|0E-R*L>Bc(#21?&Irc-V_EUVaD9g`9hb9v4ms>P35nfs*i%MuOizbm} z(PXkLnnIRErDRz&l`M;};(JTNK%?4o68~_&01z^!p z04$mZz@jn$7L^0AXg&ao767p5XaE*11Ypr302Unsz@lRTShN^`MN0r!bQ}PSmIAP7 z86dLg@I?Gk6C`Jqi!(tM?dK0~%M%Ir%Pl%75q>;h7M)CcS#%0n7Of!5qEpGT=rpn{ zI-M+w&LGR8Gs&{(EV3**n~X&(0a$bn0E^BAV9_c77M%ycqVoY*bO8X1E(BoFY5*2p z1i+$;0a$bi0E^ZDu;@|%7F`CwqO|}lx*UK-R{*f+N&psJ1;C=K0a$bmAhPI$L_B+e zS@fsH%oAnNCco6aHj!|@+@c#3VY`L0=qB3BqIG0hbTe5N-9nZ{w~}SiZDd(=J6RUp zL6${#l4a3dWGuQHfJOHJu;^X@7Oe+h(R~0cx*vc=4*;-e0|1L21Ypra04#bKfJGYt zSo8=0iyj4F(PIEC+62I&#{pRM1OSVk1Yprq04#bMfJM&$B8#q1#P>5nat6droEv1( z$$l<+Hj!|@+@co~;hbY+(PrAqqL;|B=w-4jdW9^DUM0(-*T}Nyb+RmagDi{QB+H_= z$XN6?0E^xMV9~n(EP4-sMehT!=mP*2Z2@4>hX5@42!KT&1F+~502X};z@pCpSoApn zi@pG0(U$-$`U-$WUjwjcD*%hW0btR$04(|r5LxtmB7U9;lJl%v^nxt9-_J$c5()Rq zE&4GL-o02B{X~0N^fOr&{X&*SJIJ!=SF$YnjVz0PC(ELpWLfkFSr+|C#-hIfSQKRI zX*(9h09cd(z@j(+i!uRN6aug)3xGul02XBfu&5dUi*f*1lncP3>HsXN0l=b~04%Bn zz@j7oi&6kA$^&3gZ2%V40YnyUPsHCgL2}ObR~>)gT;xjC%}%&qZc)SR@b}|nQ6t*R zqQ+!d)PyXHnv!KvGqNmdPL@UaWLeaLEQ?x_Wl<|K7PSUoQ5ygj?FPW2-2qtC7JxSu&6Tti@E@?s4D=Ax&g3gPXHEm z2VhYTKx9$MN?=mi%Q9|XewD2O(V;q>10_ngDi`V zAj_g7$+BoBSr*MAW6^8?7R>=*(Odu)9RpXb17J}(0E^}WuxJ4Qi;f0h(Lw+g zEdpTCF#s$&7Jx;I0a&yIfJMgvuxKd&iOM zE*Xnf0kG&i02ZAOz@iHPSacx(i&g`$=pq0XT@1jYO8{8327pDE0Z02ZwUVA16O zEV=@KMOOl_=qdmfT@ApZYXDeuEdYzI17OkhfXJegv*X)MkepoqHzB9UqV}%T4cQ6z z%PqP&JFLAz7TrR7S#&E|7TrdcMYoe>(H&%2bSGIB-9?r~cavq&J!DyQFByy01F+~m z02bX3z@i5LShN9vMGpe7=pg_WJq*C2jQ}iq1b{`40Y02XZmVA10MEP4WfMNa~- z=qUgeJq^I3X8>6AEC7q117OkffXJeovg6%NkevN2X0DS(i~SMph3tg;yYUG#NKV&D|FSqEI>~QTFvS zS@auO7X40^MLWr|=nt|i`jae+{vykwpqiey%c2+=i!uOM6bE2YCIE{<02XBduqXk* zqHF*bRRdsA4giaC0a#QWfJHR`SX2{$MYRA}lmuW=3V=m<04%Bvz@j<;EUF8@qIv)< zst<@P`YAiU$pp!H$4@^$%c6N68dOWTUv5#8YT>76$)cvTmqpFUvZy&(7Uh#=Q46vx zYDtzwt;n*dHCYz5AIR)4FN*0NkBjp6c9la5EWD`2#URTQL#5vR8;IJHWU>_6czRN{meez zNxZIgujl^bUh83NfTHFE6y*|7)PjJbJOYaH2`DNcpr|DQ zMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIClXN9i4ZEPm+r?`IYl>Bad7IVhtKri zv(Y&{X1+{OxAdUd8Y$||`BKz_Ek!-qQq+qrMZMWl)Q2raec4jfk1a+0*-~^e8$|;M zC>lsW(J2HJok~E_AOea86HqjSfTE!U6b&PwXgC2yrx8$eIsru^2q-#(fTA-AC>lvX z(I^6n&LW`bYyyf32`Cy(Kv5APRMaKiALM|E4u2R$}^@J@wX1+|(`1D}bS}B^q z`BF5IEk%>qQZ$(@MN`;PG?gty)7Vlpoh?N(*itl;jiOlu6qOKAR7yZm839GJ2`HLF zK+!n_6wM`|XdVGY^9d+Amw=)L1QeY|K+*XG6fGp6Xb}NL7Z6Z%Apu2;2`E}ZK+#eH ziY_9AipHh;S2-Z@&UW`xEJY36!=&i4^qBcFMVF)pk6bB5D>+|^E@ey6Wo#*0#g?Mg zY$;m9mZHnqQnZ#WMOUz;=t?$EkzHprRZU{6g|S0qDR?M z^cY);9%rNI2?C0?5>WIc0Yy&{Q1mnbMcW7{dWL|aX9*~Jj)0=)2`GAjfT9-(D0+#2 zqL&FMdWC?ZR|zP3jew%<1QfkaK+zin6un76(GEhW=ybKv6mY zMR5X(G6*QjB%mmZfTC;yiV_4AB?&0XA)u%l0Y%jbD5^m~QB4AhY7tOWn}DJ^1QgXJ zpr{@pRCFlazuN(ckFdu@e@M|Sc3)IK9y4F2=%{$`=Jit4kn^Re5nGCmW=qjAY$_kVRj;)m?+ z=g4^YOn;Y+uJM@pGDSV(LCuX))Qj__s5e`R`mm*_FI$TGv8AX#TZ&F*OVI$f6b)oc z(J5>cok~E_AOea86HqjSfTE!U6b&PwXgC2yrx8$eIsru^2q-#(fTA-AC>lvX(I^6n z&LW`bYyyf32`Cy(Kv59^MPmpk8cRUYI6|nXd))8nfW+-@DvI`yqAK?2x;P#)U#4hM zJQ%r2iY9Zu6is1E(Nwk+O=C;ZbhZ@DU`x?VwiL}`OHm11ib~liDkGq1HUUL*2q-#- zfTFns6wM=`Xg&c&=Mqq~fPkX&2q-$AfTD#26fGj4=mG+YE+n96F#$zO2q;=gK+#16 z6fGm5=wbqjmJ>on6XO0N2PFQc-Th3IqCESEwjv%gU#94?c(CziDO$z(QnZ>aMQhkn zbU9m!*0QDO3bqto$(Ew4*iy8PEk*0uD7u<}qH72!x|V>V4FnWjM?lf_1QgvsK+%l^ z6m2A+=q3V+HW5&?nSi332`IXSfTAq~6x~Wd(QO12-A+K!9Rw8JNkGwE1Qgv(2o>9#!IE>Ji9NtCmu6jrs#oq@XZz}dXV#_=pnWgJ^fUoQ+XyInhJd1H2`GAwfTHIKD0+c_q8AA$dWnFdmkB6( zg@B@02`GAvfTHaL6unMB(HjI5y-7gP4g!kaBB1DP0*c-tgo^Hq`5zBGhe3Y?|4vp zrxg9e`BL;RTZ+64J#&|$2wRHM*iz)Pr6|glqJS+$RoGG#W22}l0Y&Kq6vYWB${?U9 zlYpWu0*bN;C`u4elq8@ihk&AL1Qb;#pr{4`MKuX1szpFiZ32qw5KvT?fTDT?6xAo7 zr~v^*M-W0qf5rXv4oE!T?u!mf(E<0e=#d#Q^JR*T&Ilg6TZ)e1d?{+omZD?XQgj?! zikh&cs3}{Dj%Q2J32Z59#+IVyY!u}ZP}G8eqC5hM@(Cy^AfTuv0Y$9{C~8eWQ5yn^ z+7eLIj)0=}1Qc~3pr|7OMJEza)QNzi&IA;lL_kp&0*bm4P}GfpqV9xHQNs-XQwJp8 z);{alC?kBPf1lkK^~i{sFH_VfBl!1TDeBAlQq+$vMg7@QbTV6t2C$`QAX|z~VN21e zY$+PVmZHII6b&JuXea?i!w4uEPC(IV1QeZ4K+y;Siq0UQ=u85NMiNjoih!cC2q-$6 zfTBVIibfMqR76107y^pM5>PabfTCgoipCRAG=UH*>XqR)zRxMDYhMBBEk)nDmqjOL z#LSl|nwk;xdO(V%alRByXG_rxwiL}|OVKR06qT^0sFW>5Wo#*$&6c7$Y!sbCK+#+R zislheG@pQ?a|tL~KtR!X1QeZ5K+!@1iWU)2bO8ZH7ZOmkn1G@s1QabLpy(n3ik1;j zbTI)%%Lyo2K|s+Z1Qe|#go-9-_>&!w_$>P}{uC*C*Y21u&4`&VQ?w={xa1)zx}5W+ zXf0ccu3$^im24@xiY-O!*iy8fEk#$erRW;A6kW?k(FOvFt|Or6dIE}WAfV_*0*W>g zP;?UkMVkmH+Dt&v%>)$PLO{_L0*Y=Wpy)ONif$*M=nevk?j)e-E&__~CZOmZ0*dY> zpy)nAsAyG&f3E`)-)mn1SuI85?IYU#88P!^iXP4g-g-oe9^rf`dXz0ikFllbakdma z!Iq+}Y$sQ1mSUMSBS-`i_92?+GZ{M?ldJ1Qh*9K+#VG6zwOV=w||oej%Xf z00Bk65>RxIfTG_BDEgg%qC*4}{Xsy{p9B>BMFfTD(kP|-gb{)G-myvY8OnwJPXda15kf`B zWcn{VAn{M_zNm3#_)Nc5rW?I8W9G{g_0J6UZj+*uIbVtfu%&1qTZ&F$OVO!pDH_C< zqQPt_8p4*Mp=>D{#zxU_0*X!}py+f0ibfDnbOr%MXA)2}l7OO71QeY`K+)L*6crLs zG@5{-A_9uW5KuIhfTD2(6crOtG@gK>2?P{PB%o*#0Y#Gup`yN-e)cm?(HQ&ESwAVV zzi=ixB{OEeOwo+YAn!RTn#uW6G>a`oC2T1wWlK>RTZ(40rDzUYiq2t6(Ok9^&10iz zJ^@AN5>T{&fTHsVC_0~jqJ;z$Eh3=k0s@LIB%o+90Yys)C|XKD(M1FlEhC`lVgibm z6Hv5*fTBwXC|XHC(WL|wT}D9BDnh7eTBbkD0g2yZPwuBn(K9wyXU5EzDY_yvnEiqj zUCH@UbQN2Q*0H5%JzI*dW=qjEY$>{yEkzsHQgj_#imqp)=mr9cZX}>+BLPJ>5m2;= zfTGO=6x~cf(JcfNZ6ToORsxD{BcSMZ0*dY+py*BlitZwy=xzdv?jfM)UIL2lBcSMh z0*W3Wpy)wDsOa)c{~8A*USgkhTq{KfZ9J42Ghe3YvCQC!m!#-%&X=Mm*iy8WEk#eV zrRXWP6g|zBqHSy`dWJ1U&$6ZHIW~%(C!pvB0*YQFpy(w6ie4t5=oJErUL~ODH3EvZ z6HxRz0Yz^RQ1m7NMLP&6dW(Rfw+SeEhk&A;1QfkXK+$^y6unPC(JlgtJ|KjO9?A4~ zJ0S6E?e6DMDLT@$Y z^#9F_nJ-i1X9az>OHnlIzt8jowiH!iOHqt1MOE2Sl+Ko-I9rM`*iw|qmZB^+in0kP zN)S+#B%mmVfTC&y6jdjns0IN=H3=xHMLGqw~pXG>8oTZ&q+r6`XrMfq$gDqu@dOE!vH5m3~cfTA`86tyLws2u@C z?FlIAKtNGP0*X!~pr{i8MV$#KI*EXyE(8>HC7`Gq0Y%*jDC$8#QBMMjdJ$06n}DJ| z1Qhipgo=*K^6z&*;>R1DCQ>xVKD_nIikUA{G%zc8XNMG>!ue8kDqD&Mv88A*TZ)FT zrD!NyiiWYJXgFJnPGd{a>1-5@AfV_B0*cNgplBokMWYBPI*Wj!vk53FB%o+C0Yyaw z6pbOEXe(If(jCKFIJg@B@|1Qbmpgo;ki@((#6@$2lq zXn+*ewWs~lvts7U6qRHJb>ESqQqGs6GPV@WW=qi=wiKPimZG_ADVoQYqWNqoI+ra) z3)m<+kAR}{2`E}fK+z%siY_3a=t2UD786jkgn*)@1QcCFK+!S+iY_LgXgL8zD+nmM zgn*)z1QcCLK+$Cc6s;nlXf**vYX~U1oDeFSndP74fW+(AXB}rr(Pq0ZTALL!U#4hX zR#5n^6s_lcDY}|1Mc1&U=vuZEZD32$b!;iRo-IW;u%+lmwiIn-qv$3AiZ&5Yw3&dS zn+Yhog@B?h1Qgv$K+$ak6x~ih(H#U7-AO>vT?7=}O+e8-1Qgv%K+$~!6x~li(E|h& zJxD;&Lj)8(OhC~igiz6yS^g3SB;LgStm9Qu^o2dse>5v*zD&{9tl;MNrRYh{m!hZG zQuH)iing((=oz*YJ{|VTecMKWlPa_Y$^JljiP-76#YOz(T@Za{X{^~egcYqCZOmS0*Ve0Q1mMSMF$Be z`i+31-w7x>L_pCW1Qh*AK+#_W6dfj@=x+jw{vn{~UjmA}Y&|hYQG^gG`Yg*&e&`fc zxBH^qQZ&*&qNQcW%$F&uk{uL$EJZQSm!hg{DN1KcQJgJB8Eh%aWJ^&NTZ*#TQj}mz zQId_K90H1}5l~c}fT9`%6xAf4s1^Z5wFxMyLqJho0*dMpP*k6Qq6P#M9YH|RkpvVS zMLAOeT?g?9V%zT-m zX4%0xpGr}4&X=NGwiLBsOHm$Mit^b~RKS*^mTW0%#g?MhY$Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq z0*d+(P}HA*qLT@sqT{pu4Gu_rw|&;}1SuM1qy}Wi%$F$|lpQ>|TZ#sAz7!2%OVLoa z6b)lb(QvjDoyL};)7erqf-Oa7u%+lsHi||PP&A5wqO%AnI-7u^LIR3L6Hrt{K+zZi zipCO9G>(9xVgicB6HqjPfTD>66ip(aXfgpsQwS)UNEx!dvrZ3J7&I2(d_KN-y=nHIA4m+VN20mwiL}{OVNC`6rIbKq6KUz zI*%75m2;>fTGm|6s;kk=yC#z))G*31p!4@5<*3#*?v<8B!0Wy7nMoTANI8W zs_dBgGDX*92mQX1qH8%{iZ-yN=sLC(UC)-H8`x5GBU_3#vZd%IwiIn*OVMUFif$&L z=oSKswh&NsD*;8f5m0nH0Y!HZP;@5&MRyTUbT%}5m59vAyl+J+n?@$#FyA-9j}(6_wByuiR_s9GDS~k2dlo3 zqHUZnMbEIM=vlTDJ;#=!=h;&90$Yk+WJ}RYY$SSMXwQ1w4H#W*9j^^UBcSMg0*ZDKQ1k%-MIRDS^br9?9}`gY z2?0f)5>WIRAyo8aw*R055?}2*I8RB@X*PCe$IO>0`Z7CscdrzE#rab7HCu|lVN21s zY$@8ymZI<2QuIAriuSRk=m)kG{m4eqPXrY0C!pwO0*Zbipy&VrMZXeIbdZ3e-v}uB zoq(c41Qh*2K+&HB6#Yd&(P09L{wAR49|DU0C7{Sl=xIBOA_Nqr5m4k4P!uJEioVG9 z|8zj&1qNr26z#DQBx2^v6s0GE`un6P&iPW5!Iq*-wiIQtr6`*%MG3YPCD~Gx!YFMo|p{ifR&2REvP3+5{BUA)u%(0Y&u)D5_6DQ3C>sjv%1uNCJwEBA}=t0Y!}n zC_0*eqGJdsYD_@Uu>=$yM?g^%0*aavP;@*YR1{12T^*44CVMDUH4#43&oD(NBx2^v z6tzeMML$YW9_LF@K3j?k*izJzEk&)^Qq-C)MQzwp)Rrwp?buS(o{gdo1Qc~7py)&b ziaHTc)R};ylL#p4LO@Yh0*bm3P}H4(q8Ic{EHlr_)dF{mMcYpkvcUIGhe1?Xd>9MUy6otz7!2-OVMd; zDLS1kMI+c!bOu|B&SXo`NVXJ>VoT9kY!sbMKv5w9MWYEQDk7k03;{)B2`CyzKv6LP zMdJx5nm|C&L;{K?5l}RlfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P*g%dQ7Iu*G&tdJ zcR=DV*q8B#NYVNBiR`jO%zT-mxryM1U!-Ur=S$IiwiKPqmZAl0DLRiWMd!1nXdzpQ z7O|!10=5)g$VSm(0*aOpP_&eQqKgP9T1G(8#RL>BC!lBr0Y#S(P_&YOqDu)Vx{QFL zRRk2RCZK2y0Y#S+P_&kSqALg}x{`pRs|YAsM?lefLa1m?!moC~DcWzJXgo)X>f6)) zs}nKvWs0s#1g#EA(e<1!MK`de=ti~_ZDdQ)O>8OJ#FnDXY$>{#Ek(DmrDzKqMYj@A zbQ=Lhw-Zow2LVNQ5>Rv(0Y!HcP;?IgMfVa=bRPjl_Y+X`00Bi05>WII0YwiJQ1l1^ zMUN6t^cVp}j}uVz1OY``2`GA!5GuMh;g4`Y;%n@_XoD0jwGVGkC1U2w6g`^==KU^3 z&vCvKJY$W7eL_IdrvwyzMnKVS z0*XE-py&%isAyZlzup0fKW-1GpOKS`2-Y22`CB(D5^q0QH&5O`YPdn z>43x^3mlxUrD(q07gbHh%$F(3Oa{SWDazt}DavL`QGzW+NwyT_u%)OPTZ*c)rKkp5 zifXc@s1_SVwFxMyLqJho0*dMpP*k6Qq6P#M9YH|RkpvVSMLcEzwj%+D9k&U8G1Qc~9 zpy(t5ingo^T#{!9lXKH2Vz@}($gAJK*+W9G{got6yNcy&%jU}LH905he1Qd-Y zplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gAGYKe~MLOVN33DLS7mMGM(dw1_Q5 z7qF%1LbenwW=qi$wiGR8qv#?6ik1;jbTI)%%Lyo2K|s+Z1Qe|#py*NpiY_CdXcYlP zs|hGtLqO5x1Qe|$py&z$imoJ}=qdt=))7#&o`9mO2`IXTfTC*&p`v+7|F8oRpJJbA zoG(Rz-4|_0#>|%~x-l6X5lGQS&X=N_*iy8KEk&EzQgkz0if&;`(H6E8-O84t+t^Zc zI~zrJ5Kwd{0Y!HaP;@r|MfVU;bT0u#_YqKZKLJG#5K#0W0YwiHQ1mbXMUN0r^e6#E zj}cJxH~~dZ5Ky$0fTAY}D0+&3qNfQc+C~T!U7z&3J0S7dcK36G6uoAOo=L{cmnnK7 z8H|ld(TkifMK7_X=w-GPy~38FSJ_hZ8e59Cv!&>DwiLa=mZCS=DB3|l(OU!*y-h&T zI|LN%B%tVB0*c-vpy+)9igpoD^Z@}y9}-aX5dlRX6HxRC0Y#q@Q1lrAMY{ZAVdrfTA=4ihKf!q68EL1Qb;vpeRN_QB?wp(g`Sv6GBDb zCjB=YkoXKYqkE-jygk#;$cdRRQaeA#E*nMl2q>ygKv4q%ijE+l=tu&Jjv}C_Apu2=2q-$5fTCjvC~8bV(Xj*+ z9Y;V>69S5w5>RwJ0YxVeP}GcoqUHn?P|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9Sh1QZP*plBcgMW+x@ zbSeQwg9s=ZOhC~P0*ZzbP&AAXDr%YIpXq?akGAJ%t)%F3d)hxdCuY7((HS|xxk)KH zlk=r$BwLC`v8CuNwiKPsmZCzo6pdy}Q4w2;#;~PmEE`4R2q-EhplCb+MH2`pnn*y= zBm#;i6HqjTfTF1c6ip+bXgUE!GYBY}NkGvo0*XoqC@LkOsEmN3*#s2LA)x3S0*dAm zP&AJaDmp#KztI7S=h}VI2r2sAJ_R{HCuY7((fK*SGu5PMA?HicBDNG=z?Py5*;2Ha zEk#S%QnZvUMHjK9Xc=3IE@q=>IRQm02q?OQfTEQI6kSR{(Pab_tshxx{iRN>j|Nv1v&oL4oLhu zyZbp$ivF~5Lr%{(Ek$>*rRYw! z6y3!}(cJ_T-9tdpy#y59M?lg21Qb0$K+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qb0% zK+#qLik>8(=qUn{(69S4pC7|dt0*ZDMQ1m$gMPCq5w1&9U`FU4+4t*B%tUo0*Ve3 zQ1mweMgI^`^e+KLUNt>!M^S`;qBH`Ed;*H11QZ1X6jdRhC`Le0RRW6A2`GvaP?SMH zQ6>RJS%gs0_c{Kf4oE!L?u+(G(K7ppmR&7ozD!ZIYQYEfrKmdROHmEB6xC!)Q7yI< z)n-dk9kvwJWlK>#wiMN8OHl(hijE+l=tu&Jjv}C_Apu2=2q-$5fTCjvC~8bV(Xj*+ z9Y;V>69S5w5>RwJ0YxVeP}GcoqUHn?(*cQJY;f92(E__K8c{7~ zzD&`mYC&;BDLRYurRZ$76cw_iXf#`jir7*#hAl;7*-|u)Ek(s_DH_j4(F6jDCK6CI ziGZTX1QbmnplB)qMbiiPaYfT9utib@G6DkGq1HUUL*2q-#-fTFns z6wM=`Xg&c&=Mqq~fDkG=vzouc0f}$7XZjwqKnv4w2Uo97qg{kIa`WWu%+k{Hi}jfP;@B)MVAp!w2FYD)dUo+A)x4T z0*clWP;>j)@XPe9St1QcCEK+&}X6m1}&=sE(5t|y@A1_Fw1B%o*` zAyl-mn!m#ViTAMkqD4|Pz{XA0V&==s_R^xqq}M+#;w84YudjKDR}5U@d-oOFs);Q3 zY%VjA=N_6T6N9rnuSVj^gy+>se3avP4HAuNcwWQAgj$~0IB{1U&uf}EP|x$4CpsMA zdHIQjM|ocB#0!l)uYDq;vFCM43_i~Dx+c~&^}L>mPfqZ>zKLUUJ#Ro_Ql94xO59W6 zdBYM1TY27y#EES^Z&c!f_MSI7@lr?68<)uH?0FLtL%Vq1)Wp@@Ja1;=vmTyTmN>Sz z=gmz_>Faq568H7@yhVxM2YB9+MCVgI@8ZPb!JfA=@ybxoTb)Rp=6P2nhL7;P^@(fG z^t=s;&qsOQjfp0Op0_zMt;q9kO*}Bx^X^RiQS5p5Cb~@Yyay9YCwtzbiPxrj-qu8p z`#RFL#Obp<@A<@arJnb4V$W>P+nzYy{gW6w5;Nv|-p<5B3p{UE;;-{P@8d+b3p{Uk zV%cKP`!ezRQqTJ~QT<}i+m|?Fh3D;0+_2K~eocIJndco!G+X0&hm*6`y7zx1`N);- z28bm8UgvIsNV3N@?k0#Nmv3;lK_vO+_3lQ9Bx`PTw?ZU2a+A9mBFT+6yW1g>w13UM zaU^N~9C_17(*8Z^=8>fRgTVQbr2UJots_bMCpp_klJ;*Zc8VnJAI0k$N!q_^)-#f{ zf0n9mBx(Py(11vC?>2XvM3VL|dkl*t?Vn~C5lPzLtv@P~w7(pEbR=niyY;w8(*Anl ziIJrJ{jyUdN&5>zXGW6tH$0X_lJ-~h&5b1O?^s(9N!nkMwJ4IbzvXC2B>CiScMC<5 z_V<+IRY25lPy&YOjwZ?R#xEM3VN+k~c<@_T6rqBT4&qrCTFO`+k!< zBT4&)fqNrK`xD;}Mw0eNb{~x-?ay3pjU??4&25V$?N2>DA4%FDTX{K>v_E&SJ(9F9 z9PfxE?JIvfBT4(x&8|q&KKK4{Bx#>K-5p8VXTQFTB<<4|-$s)5{BvIbN0Rmk z@YhJvK7=2NB<() zKen)DWN46i@y}&tUXA|loFe!7jly#x`Ccve`yh2O?jow>yu0VKU(Zcl#t)zE{4>0a zPcHa)_xbKJs^mQP%fG+P^Ss)bfkW>83)1{5wGX*>oc$LZ>&LxFPUP6^>KT4^{p{hj za~xLBOKa?9WSr!Z=lQifKf7bbi5VR-`c-%Dd%dKpJGqT#rAqZkMn?Dw5jSI5o?n&M z&&bHi$joT(-nmt4|L3*R-D_34)VO94zL5-Fq?>k;nYzf-ODiriOBbov%62CO71tw? z<*uE*sb-5Bv>gGhMRq0x1UH7{77OS_eboCmz3#qaE!ial6 z6;!vE)?9I6#7nEQrn|dCuEh)7ySRndrEaIX)3Z|->fVaGks7%F>@MHE<5K^h`akF9 zKR+t%osN<3jdQ1@MgGdp@*?hsdtH;(qD5XwQQr8{nR%rpWAjQ1OUD)$&McWxRy?+> zcwFAtl6f=BW>^?oJZ^SLacQNO+3UO4?vOXLWYV-rWs~LO$^P;>-)5lJoJ+3%!TG7~v zlcxXw{c4oXE3N#Vm@qM~TgkZDlcvw;F{7k7xBPuEx2z=fE(zZwgGy#hcJK4jyrDCT zN~ZLlJ-u+4`?X9MG<9}q;gD`^2e$ctaWl;+Dl4}4mgj{x^!VA+$L6=`&|<7nC>&Qj zzG(K;vcj@?GmA@GOf+Hc<{CF?dYKze(9j;e3fRPiUcSMcjLtTG{}Rwa^`mlsse3#v5;f-0RYxTBj@Y967VgrR!* z3vB1RM?sOA?pv(gArUmPgL`>uws0?Q8Ps&MT9@XHf`-Qg)$9M~k}BSWUDDD2xuk}b zFR5Ybl2Whku24U>8rc=Ao|~Un5MFXMf3CffRj&5`&GG-{ZRX`2X>ag9mmF!7c7*#~ zJfv5j!ru9PJv$b(&+l6}Cj4pJ*5yBK)1&;SZQJWLTeqimh1l%y#LVMPlZbRb+zN|wW|0!wTVUU3QT-RoX$-0W%7=7pD}*KN%k?xxVL{0g{RtNfD7-$-lT zM$d|OhI<$272Q=1ZzFdp;ZG`Eg?60k-g&7Px_7M3Yg2w&Ra}oA4zEFLp^g6BSROrKC(SUi2)q@wACQ)f({5dL!A z4dkwjyQ{5q3+alsuDI?_L-^|DzgSG?SNvK#l)q03+;11}1E|qc;f}_%P*>+LL+*>Q&7Rv{VMdPAybaS-T9=hKtYAI z0*5VZ`Mj`#UqNqfnhJH?TJ9GSp2tt@W=Y-g>833wSdgEedV#xV)D-4Bv(B&8B|h-V?m6 z{3^M(<(l0I4ReoP^!l9WZjV&48#(ncE&Nc{tNd(t3+NInt^v2Pdk^Vl<+r7~3BtEf zVZ+^nxYtTuco7s@<2BgzuGt@Su;g6&eaEIFt*lP~bj< zyUQ<~IHRPj`~#cA#RyG>Gp+4T%a@D zty=L8c0cQL%J7CgI&^4gPZ(MhG_cxrJ`Y4Pz5bEl1+IlJ>%_Z};r zn>(#lD;LTp&Ym{L9mh|dQB;=eo^Nz^H_JE+?ls5HoYN+^bY||jg0`*{m5iO(**yW7 z(>`}vi)rpDOtW#NGn!qVgTSE8K_i@Fx{y3o6VS$N$sEnvi9s zkB8;cYbRekA6RYQ+Op z*w~|=Q+p3B{|H;a=nx$^T4sKn1 z2zy8uzGDP2eC(F`mD>YGJ%&vE3d7%Z<-clvmz7(FvORE|QhvwBV!vE*dl*9f%A8)&FeRh`{ zujYBZ?dU##HAmatBWd>K2Rpi7p8X2!SX0Nkc69HCMs{?s)KuLZ*z38kAf%4&>jtS~ zcO3`mI9x~fS&Y=nC+j#%$AvmB(Q&non{>R-J`LvH&XYR6<8D&hpXqqe{Q_)9+-GI& zSlj(t?0Afh_8BuMuer|h$jyJlS(Dq$Ae(l}?wh!po+<~&)LC2C>;a;fYqwe#6 z_VO2W{HI>HGwO%Op6-h@_VU3xt~e^(>vY`V-m&)bPjsx+INZnRIO@1?Ptx%wcLUh# z-=pKVCxrW;jxBP-eWH$K?uN40zd*;w3&Q=9j$Z3u)KHOL9_;$x| zf2Ly{cf;H3AFJcpUBW#@$IacseV>ls^$7RxI_CEdcV`{v^bPl79k=!m_bWQ44Gece z$G)eAd$^954G#CUI_?}A?$33scUric=s0>rxTooO%bDSRK*xQf!u^MiEepflMaQ{C z;a;laQx3YlKVH)@IzHSvI`*F!?$dQ#JvrRh>GpE6h81Cvi4!9uPXXtqO;&9)f12v{Lp=6&u*V@bZodW+_^fA-xTgr9q+t3+>hz_%a(Bet7H4y!`(~A^Y0Az zB|1KTcevluF@9gTYwI}ZfpDLt<5drZdy|eIKN9Y}Iv)Laxbt+JxHa6fb-eqja6h5r zuiL^Mc_ut|d@elp(Q(lW;l5PI7hekZJ33~*8t%F}4%r^=LLJw?5$>CH{B%dSzt^$x zJK-+Saq_$2K1auU-w*ebI{x-Sxcv{qW2cY9V?P}){50IFbbNVtxZl+=dr!FQ>p1MI za2M%#%{SrRqT}wp;r>C#5seUy$P z+?Q=_7wdSv`}(czJ9PZgeIeKO&pMvqzM^ZposKgbhWk7nA9i2kwURL5&{+@j-yIzFT08#;buNB4FT?hCGVJX*)$c68V0 z3?0YlI9|sp_PC|0`--C--Ff!Ij_%<~>R4)zW88KRC%m+5_s0v=y%weOrj-?qamTWf z@Hmm5xhKA5UJHAs>9rVBTI#iM&y8DHZ1LaE?Y?@f6Wl|P|NL<8s??80?*Hxe{BYVsmjC>)m)Vad?mzdg|Nr@V`R;Z8 z*W2Yn+{^5?vLDUef9_$V*VX-JKbCZgq;4;}?d)~zKYM$9-G7x%cYgxJ^JX{?{NQIj zU8sC{8{Fj$a=|Xo-UnRXF!yuLaX%850mCkWL^^Q6rd_DWQ{owLuyPsFSyu+0)&z>=Hd6!f=$NkjH zbCA7xo&^ zJN$D9;RQ$BGeIub$_D$RZ|=ijYx{rqvRdv}6K&Mol3F2?){loHOO|q)zYfQ z=DPP-G#c1vfzqNT$@8nYSNEG&@8(|JKj_}HpI>8``+2a+&W}{t$%z1{pEI= zb=_>|MO$drakIS_&C{&yW(W8E@tU>VEO1w=K)a@GcfDF_*RbubSS#)7w%s*rtzFHw zyJ~H;b8Nfo)>b=d+g-VK+6mk4+O^ltw(YK72kk7|?)r7q&UCw_yM8BXXV`YvuakD% zw!40vwbO08>vxiNRom|Rb{` zLMCe?WQukuq@Vx2yZzH|a(6V*{-Kbr?j9;SHD+>5$jre0;BQLEES)MLC7Kdaswp95 zni4WwQ$prwO2|2y5;9j)Lgr~o$b3zNoU4tH1=I&NE;!`v=MT#HbRzbBV>g(LN3up$VzR5T&j(b%d`=)N*f`owL>A( z{VaEvk)G{7;6!JHLYmqA$(oqSF(Fq5_J_h#Lax%O60%NHLe^_a$kmz>a*d{hT&pP| z8#E>4I!y_=UQ9E+6Z|_I~20k&vUnb`aHW2 zxgr$umHqtTn8`6Aj|cV*11TX-=u`>Wswp8)YD&mcniBG~ri5(Ml#pjMCFEI633*Oa zLY~(|$P3yCc~Ki7FKHv>Wo?AKqK%MOwGr}~HbS;*Bjj~$guJ1RkTaAoi;+g z*G9-bZG`-wjgTL;5%QBZLiTGTaM#v#;g#4k6 zkUzB%@|QM34r?RiZ*7G9qm7V%wL>AF_+{?)Pru6^dwiM_6935VL);h3jE;S0TQm~b zw;H9s<3EV#Y<*{26}G;!EymV&wpC^8JKNIP`p&jETi@B1!Pa-SWwQ01ZCPx6XInO# z?`%sD_|CQ@f$wa~A@H4T)d+lNTXh28*;a$Vced3e@SSb72z+N-Z35rfR)@fMw$&x@ zoo)39d}mvI0^ixzfWUXQ9YNqb+m0mgooz=E_|CS51irJa5rOY)JDR|EwjD#@JKGu) z9FVMNG%eyk?tsMqagSW1ek4@%p*?OnHWD*lrs()cVBe~iQgj06OHnhn6g6i{Q7&7G zTCk-kk1a*{Y$+;WOHoU<6t!Zbs5JpaZ3rl8OF&UO0*cxbP}G5dqK*UPtXTKSHReNyK-5+QEy@ zx4WXIQdHMITJ?{_%$F%TB@)=TI;Iqz%K1_>h%H5f*-|uwEk#4wQZ$S$MZ?)rbQ)WV zPG?Ke2sVn&AfV_>0*XcwP&A5wqO%AnI-7u^LIR3L6Hrt{K+zZiipCO9G>(9xVgicB z6HqjPfTD>66ip(aXfgpsQwS)UN8uBxb%$(fUYW-)fywbT#Ko z(KT!-x|S_P8`x5G9b1a7XG_ryY$>{tEkzsIQgjm=MVkmH+Dt&v%>)$PLO{_L0*Y=W zpy)ONif$*M=nevk?j)e-E&__~CZOmZ0*dY>py)mVitZ<%=m7$X9weaXAp(jXCZOmM z0*W3bgo>_;_-{KP@pks~Yn>F0GDVL?V&=;fJsAn?TlG_lp5lBddYUao+t^a{3|oqx zWlPa>Y$DEf(jqWuIE{Y*g7F9Z}FAfV`10*Ve2Q1lxCMZXhJbcleW zKL{xLlYpYX2q-#CK+)d>6#YX$(Z2)~d1>X(@-tIkkBSgbltu^@?T+|oJ0S6w?9Z8e zE=6zIeUYCQGhe1CmKNAw6_Qd^mGh-2oh?OiwiIQsr6`jvMOkbq%4SPZf-OZ!wiM;C zQB;k9qUr<`)gYj#CILmY2q>yeKv5k6is}+jRF8n7`UDg;AfV_70*a0#py((9iW(A7 z)QEthqX{TFhJd2R1QZ=h;J)ZM0*aatLPhQ`h1l$X#HYHioJXsqh0pX~wELo_X)*I< zikhbd_E*iM6y z2q@}EK+%Z=6m=q?s51dYClOH8g@B^21Qc~6pr|_mMLh^8>PbLRF9M2s6HwHLfTF$x z6!jyZs6PQkClgRKfDkG=A=&2BcQ05fTHmP6ipzYXd(eclL#o9OhC~T0*a;*P&AEzqUi(_%^;v?CILmW z2%(}=)BJn~BtFvaiv~&25c`N$k`^;xrf5!DV1LzBO3^u-FGX|NQZ$b(Mf2HGbS_(p z7O_^?k1q<9s-K)C7|d&0*dY@py&Yt ziXJ4O=ph1%9wwmZ5dw-HC7|dr0*W3dpy&xgsOai6f2#u$|G_@%c#RbGwfmy2X)*I< zingT%_E+tt?u(w`d?|XCEk)0^=r00_4iixHHvvWe5K#0l0Y&a_$-CCwjP5Jy?ry;T z*lC1-qBH`Ed;*H11QZ2?P|=<=zpn!lf70%YzLcVY_UO8bA2VO3DDDULSAC}Li!wN0 ziZaid^DAo2U{p-{RXKGWZ7_eIV8nE5hAd46DjRcuO8KIcnO0b7b%vZbgMTZ&q< zrKk;CirTWJs2y91+Owso0~P0|NZvu+?5Kz>YfTDf`6!j;d=wt$l1`tp*kbt672q-$05Gu;`{hba-e3m^F zY9U2E?7nD_A2VO3XqX?^Up1UkG@SFL=rpzzoz9k`5o{?sgDpj8vZZJwTZ%@prRXfS z6rIgRQ6T|EqX{S~BA{pt0Yzg8C>lpVQ858U;|VC5KtRz%0*WRPP&Ao=u&Df-;~nZ@W(DSFdBkv-dwnJ-f` z&kyXcs!l1I&-qexE?bHgu%+lcwiKPumZF7hDO$vqq6^qkbRk=c7PC>bgn*)@1QcCF zK+!S+iY_LgXgL8zD+nmMgn*)z1QcCLK+$Cc6s;nlXf**vYX~U1oPeUW1QcCCK+%;1 z6kSC?(K-T())P>4H6c`Vj_;3lK;m8PzG$u#71&3#Yy6n`GDX+>f&EqIDMdGMz7*Za zmZFVpDY}U*MVr`Cw3#hMH?yVa7Pb^^VN21iY!ux_K+)|46x~5U(VYYo-9dXIpj_X#N4 zML^L91QdNpK+#786n#uU(I*5HeM&&lX9N`OCZOnZ0*byMplA;vRP>DR?{h%nCH7gz zXQk*UyD$3EkC`u1^sOJ*Kedojw3qXx=sUI)eb1JneQYWEfh|QpvZd%JwiNAWOVQ74 zDf)$tq5}jJ{YpU5K>~_?BcSMa0*Ve1Q1k}@MSl`d^cMj|hY2Y9n}DK!2q^lOfFdud zr|l?;5KxpxK#@;CQIvq9fPkVZ1Qf*xD5^>b6@BgdEgg`!{qqLVZ=`6KJ?&4A#>|%~ z%8CZ|Pj#deWpln1CD>AwWJ^&FTZ*c&rKmbvifXW>s3u#AYO$rLHXB8C2q>ycKv6vc zis}ceh-OB^XZlatqw5yYnE5hAEu+EJ-K3}$=Sxv* zwiLBtOHo_46t!bZQG2!&bznplApo zRFog}pK?Iri`|SCNKps7V;UNbnJ-gxdNik!&d%#g?M8 z*iv*hTZ#(VQZ$+^MMZ2BjUk|DECEI12q-EhplCb+MH2`pnn*y=Bm#;i6HqjTfTF1c z6ip+bXgUE!GYBY}NkGvo0*XoqC@LkOsEmN3*#s2LA)x3SLa1oC`>Q{CIz_$gDx`cqDl>`)BN4QgjPjing$&=vKBA-Nu%p+u2fd2OC9q5>Rv(0Y!Hc zP;?IgMfVa=bRPjl_Y+X`00Bi05>WII0YwiJQ1l1^MUN6t^cVp}j}uVz1OY``2`GA! zfTE`eD0-TJqHP2eJwpf;-4OLxJ0S5R?Y`(nDSE>mT|XO*nJ-iHVl=RS>Mo_|CC-P(GE6>-XfsrZ32qkA)sg{0Y&c;Q1l)F zMeh?(w2OeE4+tpwkbt6(2q^lPfTB+bDEgFuqR$8@+D$;w=L8geK|s+S0*byQpy(?C zioPaQjx)%HQ`1u0r%&-A~E#>|%~`aT-iKb4qLw2$+p=m)kG{m7Q0pV(5g zpDjf{v!&=4wiF#;OVO`vDLTkT(QgD4{Z2s9Ap(m2AfV_^0*d}3py)6GMSl}e^bY|= z{}NE-1$x?!q6h&+X#^Dc1QbOHC<+KDszN|fjDVu51QewcP!uPiD1#6x+8gy740MW? z+eftTr06^Qh?W_|%$F%j27&!kn<+&(oG(Sy*iuxTEk!lhQdE;IMYY&cRGTeDb=Xo= zmn}v0*eI$`Kv4q%ijE+l=tu&Jjv}C_Apu2=2q-$5fTCjvC~8bV(Xj*+9Y;V>69S5w z5>RwJ0YxVeP}GcoqUHn?N+Rm!fuTDQeG_q7G~+>d2O&6WLPKi7iE)*-~^8TZ+1{QPh=yqHY8f zbtj;x2LVMr2`K7CKv8c3iuw>x)R%ywegqWtC!pwL0*VF@P&AN$qEiScI+cK;K?D>H zCZK2t0YyUzC>lmU(Qrbjs8!(K>VU+Lw7Z|yQgp42(}I}!GDT+wf&EjzDMceWUy4St zrRXfS6rIhMqC&P5jb=+x5nGDJu%&1$TZ+c9QB+Jo(Rc!iCJ<0Gk$|E}1QbmsplAvK zMNbV|`8&X=MK*iv*MTZ$I5rDzFTik7ma z=pwchEn`d3#cU~B&PLG+0*WpnplBrlMVAs#bQu9fs|YAsO+e8a0*WptplB@tMOP3| zbR_{rR}oOOj)0=|1QcCOK+!b>6kSU|(FOvFt|Or6dIE}WAcTs}3;fm&Nc9nKHwH2DWr{Wjf&EkCDMdGPz7*ZUmZB|eDY}&{MYpk~=ytXg-NBZkJK0in7h8(% zW~1mH0*dY>py)mVitZ<%=m7$X9weaXAp(jXCZOmM0*W3bpy)9IiXJDR=m`Rfwh~bE zBmqTF5m59r0Y%#gD0+r~qGt&xdX9ji=Lw;rn*x8n0}_AQp6PFrqQ*w*g&=0WOwlVr zVEWIJ0Yx7ZQ1l4_MV}H-^cev~y9p@zoPeS)2q@Y^K+%^36n#ZN z(bohNeM3Oew*(aJC4`Dz3jA#jNPLRHd0C3u*hjSQf|&U-ML!0?=cAVOVL5L6#d4QqTkt4bcl_jKL{xLlYpYX2q-#CK+)d>6#YX$(Z2)~ zc~$hZ9YqlWiqZ%u@(C!45>ONnP*jD0q8I^1RS76cC!i=!Kv4z(MVSN?Wf4%6O$Zh3 z3;Zf)IYst$*XR#Y^qD>FPgIGSFH=;#O3# zwiMN8OHl*16#ak1-FI|Ub>FuAJ()}RfTBhO6g4KG=qv(? znh;Rblz^fv0*aauP?SwTQ4Rq`xdaq7C!nYW!B>=?5bWoGL^j)_>x=~dnZEt|ZSgG= z!sg2qwM__3&y%8doG(S~*;3SjEkzyKQq+kpMQ5|6s54uNy0E3FD_e@Xu~F2WfTA7* z6!j#as22f6=MYfTn}DJ|1Qhippy*rziuw^y)SrN&0R$8cB%o*z0Y!reC>laQ(NF@4 zh7nLSoPeV92q+psK+#Bouc&oG@OlR%^13}PY9mE)HqK87n=eyzVM6GM@ltdV=S$HT zwiJzJOHm$MipH^}XgphrCa|R_pDjfb*-|u#jiSi}6ip$ZXet3k7ZXr4jew%*1Qg96 zps0X=qL~B~%_5+vkbt5h0*ZCQK+&ZH6fGd2=rV$@ zXjDRQzXK9kW8ZZgEkz6ME867=Ve@5*u1E--%$K4ioG(R7*;2HOEk#$drRXZQ6fI{< z(F(Q{tz=8l)odwR#YWLJ1QcCMK+$ys6s;zpXbk~H*Aq~*mVlxg2q?OdfTEiSD7u+| zqICom-9kXodIE|z5Ky#{fTCLoD7uY+qT2~5x`TkCO#~F(N$?ddN(k1T=oDqy1M0<6 zG`8dkTSC};nWB3WLY*f|(S4jRMfbC%=mEAAJ;;`#Eo>=zh%H4Av!&<}wiG?emZHbl zD0-ZLq9+I_+DbstHUf&CB%tUi0*am{py(L_ik>B)=s5z4wi8hFJOM>75K#0Y0Yy6q zD0+#2qMZa3y-YySD+Cn1NtQ1m?k zML!Tw^dkX9M+m;6w-SO6I3SU2_7&}IDOzt&`+rIZn=e!JOG4=FX;Snn=S$IVY$^Jk zEk(!KQuGH~ivDCv(FwK`on%YVUu-El#YWL-0*d}7py(e0ivA^_$P4RfJBk7X6vYux z6eOT1o`9kd0YwP}6om;WN+h5tiGZRA0Y%9K6r~VQluAHR8UaO70*Yb;6r~eVfTAn{ zikcBnlubZU4gp2E1QazVpr{1_MJ)*^YDGX%Yl5$+VmR2^0f{uWXZn@G{xkib?T)EU zIBdR5QHOA7#4IW5$oW##i7iEEv!$prTZ+1{rKl@gin_6-s5@JVda$LaCmTh*2q-#- zfTG?66!jsXs4oFU=MqrVkAR~71QZP*plBcgMS}<^8caaZ5CV#Z5>PaZfTH096rD#v z(Fg*HMiNkTJ^@7+5KuIV;45ku4lZy&A|33DSbHftZ1+W@!(sDfipGXRw-!lJ9_LHZ zIJOjxXG_rpwiM;FrD!5siYBq8Xfj)hrm&@GDjP)?6HqjbfTHOH6wM%@sDOZ?nFJKg zBA}>{fTAJ-ii!y+noU5_90H0iA)sh30Y&o&D4I_|(WL|wEg+!iG6IS&C!lB{0Y!@l zzM_l5!JQ6Bq|lz0jgg`(`|`Fp95!F3XjwRP$o=E6B|k^IlJlkLDz+3YXG_rvwiK;o zOVQPADO$yrqHEYvbS+zou4AKUH33Cy2q?OqfTFbo6x~2T(TxNY-9$jq%>)#!BcSLO z0*clXP_%)7qKyO;-AX{wZ3GnEPC(He1Qcx|py*BliZ&BabQb|dcN2U?OTxj#IZl!L z$IZR?rBbxnzM|a|4x2Ai^guY&c&-#Z$oW#Vg)K!7v8Cu?wiG?WmZC@5QuG*GiXLZ6 z(GzSb+R8@JHUf&CB%tUi0*am{py(L_ik>B)=s5z4wi8hFJOM>75K#0Y0Yy6qD0+#2 zqMZa3y-YySD+Cn1N``A*npDjfnvr+U30Y#q@ zP;`KRqR$8@`ka8GF9;|)NI=n-1QdNmK+z!rioPbG=r93A-w;srEdfQ}5m59!0YyI$ zQ1l}KMMnrI`iX#|p9v^BO7IoE6As?sfJ7cJMej<{Ep}gYEF3mprs(%@XxjoQI?nl0 z^aopt{$xwh3APlSWJ}RsY$-a$mZH;aDf*i&MgOo-^e+KLUZS41qbNW?Q5*q9K>~{6 z2`CB?P?SJGQJ8?DL;{ME2q=mWP?StSQ3?S?sRR_I5l|E*peRN_Q91!d83YtnAfTus z!B_NaIQWSJ5-GMnnD!g@MMkPpV%U6{qH2kuQYEmZCar zDavF^QC+qaoxzr(dTbQcC!pv|0*V?CP}GosqDBN1H720wECPy}5Kz>VfTAn{ikcBn zlubZU4gp2E1QazVpr{1_MJ)*^YDGX%YXXYe5Kz>XfTDH;Us09BVCF)nXp{W}q-vu7 zOuwFeMQfiJHeaUb?8H#l#ZuIn^QEW@TZ+1}rKlTQin_CPJ9Pe*%gI5KuIbfTBSJ6b&YzXb1sCLkTDvMnKVU0*cNfplAdE zMI#9)I-h`|3kWD0ML^ML0*Wpqpy(okuc%{UaH0be>0@v@NzprYUo<8$Y`#p<_{7jv zOQdK5=SxvOTZ$&KrDzgciYBwAXbM}3rn05zVzv}bV@uI=Hi~8tP*gxb(M$r0W)V}imw=*q1Qg9Dpy*NpiWU%1bQu9fmlII5kbt5^1QabM zpy&z$ik1+3MR|$AEe=TJsD0OQoD@|vQcDxV=F1cdV(!QTiH^y zjV(n_vZd%LHj17mpy(L_ik>B)=s5z4wi8hFJOM>75K#0Y0Yy6qD0+#2qMZa3y-YyS zD+Cn1N``A*npDjfnv!&=0wiJEJmZAe}6n#cO z(dPsdeL+CcK>~`tB%tUk0*Ve1Q1mqcMTZF}`i6j_ZwV;+j)0=?2`Ku3fTAA>C^|ww z(N6>v{Y*g7Q38sN5m59C0Y$$Od_}txgO@uX?(3O@^S%_Fv~OhpmKZi)rs&Va(Cw?F z=mh6W(Mh%x{l%7|Q*0?Z&6c9S*;4cmTZ;Z=OOcnP=j~DyV52CGfTAD)Mezg_g$O80 zAfPBrKv5zAMM(q{MF=QLCZH&VfTC0aiqZ%uiV{#1BcLdqfT9cniYgFLRFQz9N(2;D zCZMPa!B=!VG5CrD5_#6{e*Tc6!8WQUh0T{Ks+klze61AK;(RHp&6c7%Y$?iQOHp06 z6rI7AqIzs8s?V09GucwqfQ_Pt1QazQpr|ncMQ0IE)P#VdrUVpa5m3~OfTC;yigE}j z$|azvIRQm22qi`rB-DN(!4VQ`9vn)MSkmb>n;~>duy;9&9P<$(EvCY$-a2Ek(WAQq+enMSa;) zbS@i3{Rk-PPe9QC0*VF_P&9~uqQL|d4I!XtC;>&o2q+p(K+$;w6pbLDXe0qe=MzwL z0Rcs$2q+p&K+%N+6kS9>(HH`X#u8AJNAMMOP6`fkKq7bA-A@-O^6b&|xTLW8GDQ=U zLbKLN(In27qRDJ2n!=W%scb2_m@P%q*itl|Ek!ffQdGc}qM2+I%_5+vkbt5h0*ZCQK+&ZH6fGd2=rRI|E+?R9Apu2;2q;=iK+zQh6fGg3 zXej|j%LpjClHeRw2 z0Y$eFP;@&1MRyQTw26SCI|(S-OhD0H1Qgv(K+!z}6x~Ze(R~CI-A_Q#0|XR3NbnV{ zND3ZsKq5Wej9)25ciA5{+L9DDU#95Mq|o0tOVMMTFGY{DrRWK^6m4Zo(KfaeJ;|1$ zr`S^TG+TH+=mi3bUL>Gs2LVMd5m2;~fTEWPD0+o}qE`th zdX0dh*9j6pXG_tUY$S*yKv6RSin0kP$|0aAmw=+? z1QfL(pr|DQMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIod_s8n}DLu1Yc3DNbq+D zB(l%$eriYjXZlas=n@H=FH_Vb5~{RGih6Rs6!l_D(K&1>>dls-K5QxK%a)>Z*;3Sx zEk*s=QZ#^#qJaby4I-duFabqF2q+p#K+!M)iiQ(VbRGdkBM2xONkGy01QcCBK+z}y zibfMqbRhvn7ZFf2hJd261Qg{FP&AH!qVWV2O(6J+x&~Eg_(2DFH>x z2q?OefTF7iC|XWH(F%gEXi_A&$N`BwYfP;@5&MVkpIx{H9Ky9p?|hk&Ac2`IXcfTH^eD0+Z^q6Y~m+Co6lLj)8( zOz;)0iUePCKqA@pjmB%F=rX%6dL$AyU#94ZNa)*prD!YXOVKvA6g|n7qNmtW^fX(F zo?%PTvur7Pjx9yo*;4d88$~Y=Q1l`JMLP&6dWnFdodguUOhC~q1QfkWK+$Ui6unMB z(HjI5y-7gPTLcunO+e8u0*c-tpy*u!iryojXg2{x?-Nk;0RcsO2)?4nBEgjVoT3r- zCqo{WqM+Ru?Tv)ZmnqsG31vMXMIUp%6n(;$qEFdUbbu{IpRuLrbG8(H!Iq+fY$^JZ zEk$3kQFMraqOS=kI!r*(Hv|-YOF+?g1QdNwK+z8b6#Ym*(GdcQej=dgX99|j5>RxE zfTCXrDEgIvqTdK8`kjEH;{+7_K|s-;1QeYh_=-M?1cx{vks$_WpA-$UFK;I!Ve@5* z{*Hu-wn))GoG(THvZcsN)-!i03b3Upjx9w&wiLy)r6|Ofq6D@Sh1n=dB%mmXfT9Qi zMacvdr4Ue*N0Yy;)iedy5r4vw;K|oOj0*WdUP*jP4qRIpmRUx3LDgi~+2q>yf zKv4|>ifR&2REyv%Iu!}7b3h_Fc3*T_if(dmi?5v=HeaUbjO5TW4@*%!&X=P4Y$-aE zEkzC3Qq+(wMUB`})R-+rXR)QI30sPqvQd;pKv6RSin0kP$|0aAmw=+?1QfL(pr|DQ zMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIod_s8n}DLu1Qc~4pr|VWMcoL#qRiyr z=MG4ul6}{)ZnFPOf3@8gbx#hPFH>|*a_HYjrKmUOOHm)T6!m3G(Yb6X>c^I%{%k24 zz?PzcY$+PVmZHII6b&JuXea?i!w4uEPC(Il1Qd-RplBokMduSxbO8ZHqX;M(O+e9w z1QcCFK+zZiipCO9lt)0(I0A~s6HqjPfTDZ?iY5|JG>PCV>X{s@|Cm#B!oKU+ONy>` zZ;PLt95!F3Xj*cp=Mz#io%5w=23v{>*itl;Ek(1~QdG#6q9V2w6|<#iHd~73uu*gg z0Y!5OD4It=(R>1mE+wF70Rcsq5m0nF0YwW5C|X27(P9FMt{|Xj2?0e*2`E}dK+%;1 z6kSC?(Q*QcRuE9Ml7OPC2`E}c@D)u>4o-DIB7-6h&c#x+)$W+CNe-JYQ?w>IboDkV zx}Ni;Xf0ccZeUB%jch5pi7iDpv!!SqTZ(RBOVN6^6m4LmXd?kdw-Qiv8v#YP6Hs&q z0Y#e#D7uq?qRj*p-9 z@DB$hQpw~Qv_ep$H~Et4oKuR`>x|BQqyRKv6{kiYgIMRGEOHDg+c&C7`Gp0Y%jbD5^m~ zQB4AhY7tOWn}DJ^1QcZwd`15x2d{8IB3FAy&E4DL>!yUwmnk|kCA9ekDQdv^ zQq+(wMUB`})R-+rXR)QI30sPqvZW}CEk(`PQk2a`Q4Rq`xdaq7C!nYW0YxndC~8GO zQELK<+7M9GmVlym1QfL=pr``@MI8w!>O?@%*#s1ICZMPb0YzO2DC$N)QFj80dJs_5 zli(|=mlAx#0f{_s_eJ$n{AcldR(O3eC@(3szM?led0*WROP?S$V(L@4@CJ|6HnSi1x1Qbmr_=WIW0Y$qBD0-iOq7Mit+CxCmUIL0fB%tUc0*dw#P_&WIP0Y#?>C^}6*(cc6V{X_5-9Y_f_a6lp<`>x|> zQj~4a^#4r>n=exoObwm0ON!!C|MQuCh%H44Y$*z}r6`dtMM-Qaim;_9nJq;rY$-}* zqbQAlq9_4HF#?Lx2`I`Spr`@?MHLAsszg9hWde$-5KvT=fTC&y6jdjns0IN=H3=xH zMLG@>NDWSNKq7Y=oVZl~Ia&qxw)py~Ve@5*8l{G= zc~^=WbH472&SFbZ6SfpJWlK>OTZ)>or6`*%MLBFK%4JJYb2f@v5Kz>TfTC6e6tyOx zs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9olQVdX99}45Kz>WfTC^$6m=({s0RT>Jqal4 zML^Lx1Qhiq_=*~&1|N4oB8?4BLn#_=U*7tphRv5L>Yp0gvs;P=aK01`WJ}Q?wiFF! zOVJRv6b)rd(J;0Y4QETyd2A^f!A8+Y0*cNjpy&buibfGoG@5{-3kfK?h=8Io1Qd-W zpeT=kqHzQijVGXJ0s%$&1QbmqplA{SMUx3AnnFO)R04`FCZK2<0Y%dZzM^wegC`u2 z$O5}B>L*3j>}mgu)Uf$7MTM!MYI~%pi1VeWm@P%K*-|uzEk&2GrD!f&isrGUXg*tt zE@ey60yc^+BcSMV0*V$AP_&4EqQwLhT|q$65(0{r5>T{^fTAl2D7uP(qU8h>tstOi zB>_cO6Hv5@fTC*%D7uz_qU#7KT1`OF8Ul*0C-{nHrUuV;Kq7zI&-7_^?k1q<9s-K)C7|d&0*dY@py&YtiXJ4OXbS;F4-ruGFabr65K#0e0Y#4yQ1mzf zMNbe=w3UFOZ3GlONkGw41YgmOsllZVNTi|tS;w2C=p}om|8#2De3_!{siC{~NzwD1 zFGVk~rRYVr6zyP3(MxP8+R2upm)TPE3R{X^WlPa(Y!tmtK+zin6un76(OU!*y-h&T zE&__)A)x480*c-vplCM%Meh?(^Z@}ydk84nOF+?w1QdNlK+!$|iuMyw^f3WNpAb;= zDFHV=4NI^QGtzTZ+DBOVMGr z6n(>%qHoz!^c`D@zGq9(4{Ry=k&U7w1Qh*5K+(?x6dfg?=okS-zYtLLD*;8n5m59y z0Y%3NDEfndqCW{JIzd3uNdk)gBB1CL0Y#??DEga#qJIb|`j>zrFHKL(Q4}EfioQq< z#y)Y1D%gF|K`Cl)U(w>y!sg2qC8ULN4@gm%^Q9<}Ek#LeDT=VAD48uqDQqc9WlK>S zTZ*D=DT=XClukfV1_4DC2q>yZKv5+EiYgOORE2<|sst2OBcP}{0Yx?XMfC_Ms!u@CnFJIyAoz;n(}L$YAd!>yGyPDS|4iRK(sobS z(!%D;6g5c;UGljUHRXIM%3@1VGqx0Ev!y79Ek(I(DQeD^q84l^YRQ(OR%{ftCZMPd z0Yz;IC~8MQQF{W4IuKCQk$|F31QeZ3Kv8D`in+#lFD-1oOwpjU(DMhSXfWqX z(Ga#24P{HwFt!v8XG_s}Y$+PSmZFhtDLS7mMHjG9G>U+t(F7D-NI=m=1Qd-SplB=s zMR^1ijU%9FJOM=$2q?-YplBiiMUx09noK~^6atE-5>Rw80Y%dYD4I?{(F_8L3J55g zN$?d7NDF@DfJ7?WbF_g{bb&p(o|P6hU#4hwS}1r(iso>>6kWoWqPc7-n#Y!+`D`h= zlr2RI*iv*ETZ%4cOVL6$iWU)2w3vXRD+nlBLO{_{0*aOqP;?~$MOP6}w48vV6$BKm zB%tVO0*Y11Qe|$py&nyif$zMii*;LjU1533cD{V zmZJUk==!F#u=z4Y>(fGg4olGn&X=N%Y$>{xEk(DnrRa9H6y3p=qD^cmx|1zMo7qxy z7aK))6Hs&y0Y&!`P;?&wMfVd>^Z)@x4-!zcg@B@m2q=1(fTBkTD0-BDqQ?j*dYpiw zCkQCoNE*=otcvo+bE-)};k!I3SVn_FczYr07YzFM2L5Y`#p< zi)o?jzLlaKoG(Q$v88AyTZ&$0OVKNADSDMHMX#}?=ykRfy}_2EH`yq9i-4lH2`Jh{ zK+!t{6unD8(R&0G?Ixh;eFBO;AfRXu0Y!TWDEg3qqK^nD+DAaqegcX`VUl4pn&!+{qIv|k(dvyJR6t%K(FfDApOwreAp%1^8qQjgoMc=Tc z=v%fFeaDuf@7YrH16zuIWJ}QzwiNxumZG28C^||&(J=ywej%XfR|1NDBcSMa0*a0k zQ1k}@MSl`dbb^4QlLQp~ML^Lh0*X!(Q1mweMgI^`^e+KLUQ|!pQ4}DcD2{-lAOS`3 z1YgltX~Dl7kVwqn9Fn4)HbT*``7%XG(NK*eQWW8QDN1HbQ3_j%QrS|J#+ITeTZ&?A zDN1KcQ3hLzDzH&hk$|E~1Qb;!pr{G~MO6tXszyLjbpncN5KvT;fTCIi6xAl6s15-| znFJKoC7|dG0*dMpP*k6QqB997YCu3yLjsB#5m3~a;42D8gIyeu$QAZbC^70k)BnM~ zd307ZY`#oUvuG&qXDQ0&d@0IdOHnRcikh>fs0CY!TC%0666m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqH_o+>PRw50Y&`?DC$o@(Ex(4sA)8Kr2`Uq!k(jLNzvCOPuQYi^JR*LMnm@=lcHgq zFGa)IQgj|$ibk-dXe3*T&Sy)}1#BrA#g?McY$>{sjiQSPC>ldR(O3eC@(3szM?led z0*WROP?S$V(L@4@CJ|6HnSi1x1Qbmrpy*-(ilz}zG@XE=83Ys+5KuIefTCFh6crLs zR7CI<4UPtPIUtc&?Z@~-r08f8x8&Rs}#-Sd?}jGmZD49QnY|AMVGOq z=yJ9cEo4j4BDNGQW=qi(Y!odaplB%pMau{%x{`pRs|YAsPC(HL0*Y1=P;@l`MXLxX zx`u$FYY8a2j)0=o1Qe|ypy+x6iq;ZPbOQlJHxf{E69Gjx6Hv5{;47LF4QBl26uoEP zXuL#<{tCHqOEhf0Owp~;P>bVIbQ|YO(d}$0x`Qo6o7hrxCtHd(v!&=RwiMmXmZE#u zQgkmHMfVX2%=xG9qo*|&8A zTZ$^MrKloXiYl?Cs4^QxRR}1mNP0}&IRq5-CZMPf0Y!ZY zC_0ybqJ9Jv^(UZc00Bh<2`CywK+#}=uP8efoaul>`q+I@juaiWF(ei?U#951SZIxB z?;yvEAHn%jG?Fbv=d-2g0=5*5VoT9zwiI2+mZFQ;QZ$AwMPu10$|Im?905h+2`HLC zKv6ycMH2}qnnXa+WCDt&5KuIgfTD{DD4Iq<(R2ceW)M(RKtRz<0*Yo4P*g}jQ4s+} z#RL@1CZK2z!B;da7JSkHiLAFDoeh_wsdisOwpyW(7re+TEO{IbQxQUE@w;8 zLbenwVoT9twiI2#mZBwWDO$>wqGfCpT}eRERRk0*C!lBr0YxhbD7u<}qE!SGT|+?8 zwFDGhM?leP0*clUP;@;3MQaHtx`BYA8wn`7iGZS;2`E}eK+!D(6s;$qXam7lG%prB z?SMr3+V`&KOVQVMU$ik6HeaUbj##KxNQyRbz7*ZbmZHsUDY}a-MR&8M=pMEd-OHAu z``A)+KU<0(V58_k0*bZ}Q1lQ1MGq5D^aue(j}lPy7y(6(6HxR70YzI0DB4Cq(USxe zJw-s#(*zVfLqO591Qb0-K+$#rik>H+=mi3bUL>Gs2fWIJ0Y&==DB4dz(Z>W7eL_IdrvwxoAfV_o0*XE-py&$% ziVhM`^d$jBUlCArh=8K62`D;D@D;rr3ods+A{Fhv=oKmQjMO)=u=z4YKg2@!CrQzd zoG(R3*i!TpTZ(>WOVLrb6dhwr(JyQ%`jst3zp1-*=U`tU2wiH!l zOHn1Z6jf$RQ5CinRb@+2H8zT>6HruxfTEfN6xAZ2s5SvbbqFZRB%r7+0YzsJP*jhA zqWT0Bok>7Z0|JT~5>V8LfTG3(6rDvtQ4<1+ni5cyMLCLK+(kn6ip+bXgUE!GYBXuAfRX_0Y$S2C@LhNsEB}~Vgib06HqjV zfTBwXD4I(^(L92$XheGO4hJNXV)sQOrRXF37UcZ&u=z4Ym#2qb%8;UkoG(R-*iy8Z zEk#$brDzFTik7maXc=3Iu4GHmRct9*&PLG+0*Y1=P;@l`MXLxXx`u$FYY8a2j)0=o z1Qe|ypy+x6iq;ZPbOQlJHxf{E69Gjx6Hv5{fTCLnC|XZI(FOvFHWE;DD*;8f5qw1p z(u3bPAdv-j_j8#PeQe|Q^sxCdMVr$@;Yw0;7w1dS-E1kkhb=|-vZd%gwiMmZmZAsP zQuH8Oing$&=piLdf0rKqBqh*{i{gPo18C2Z?UE5ZMGEcVoT9GY$ir!~S(Fbf4 z?IECOF9Ag#5>WIJ0Y&==DB4dz(Z>W7eL_IdrvwxoAfV_o0*XE-py&$%iVhM`^d$jB zUlCArh=8K62`D;DK+!h@6n#rT(RT!2(QE0!LI))Bo;}llU5Z9HJn`SBhs~EM`YAoM z*8OcXB|icAne(OSC|in-v8Cu2wiNx!mZIO-QuI4pijK3T=nu9O{mDkr2?B~v5>WIP z0Y#?>C^}6*(cc6V{X;;}zXTL{8G71|q5uI!aRd|v2`GvupeRH@Q33%)VFHR02`EY; zpeRB>Q8EEVDFhUy5`0BJrU##PKq4u2Uvxx@CfZlDw2ZL%GDR5~p^s}wQ3cMIqKa%O zs>GI}%4{jB!j__{Y$>Y7mZIuxDXPJiqMB?J)gqv%HUUL-2q?-Vpr|eZMQ0FDRF8n7 z`UDi6NkCBp0*V?EP}GQkqQ(Riokc)V69S5w5>S*yKv6RSin0kP$|0aAmw=+?1Yc1s zBlwR45?OBFB1+HjpXq;P_eCu-!sg2qwaEz8sVzlqIbVv}v8AXzTZ%fcrKlrYiaN2S z=xnwWb!JOZ7q%32WuvGY0Y%*jDC$8#QBMMjdJ#}`4gp2I2`K7AKv7=;iq0jVs2>4E z{Rt=$Drwa|kH9 zgn**C1Qg99plCh;MVAs#w1D6%x*#LC(gBG)XwURVNzpR<@^)E9*nF9y#TlUo&yb=k zIA4mEu%&1zTZ)#krRYkw6kWxZqUCHUTEUj0m24@xnvJ4W1QcCEK+&}X6kSI^(P{#U z)(}v1Jpn~)2`IXOfT9}-D7uM&qMHdQT1P<9Ed&&;C!lBp0Yw`LD7uw^qT2{4x}AWc zI|wM+MDP_Y%n0swKqB4kzG#sY^|NtjM%a9LXy`&lq0$%i9_wzL``lf-4{^)*U zn;1=X&*oC1_RpxtqJvXCuVVDZsOMFUewyxiHKTPadR}I9Qf1GpAAP8*=QWD{R^9WO zM%&f$yqxI5I-b`u`f6RzYa30j?|B`ggBy5Wm*~xnJg-Oev$H&}ceGxX=k<$D$@aWK z(MNJUZ&>tr3(p%F?a@sLG5aSu+XiCxZz^^S#Oxo%>k^3BziQSa z5VL=ls&^n}|E^HKK|gd67KqtD%`h?$v%gz^bRcGbIr`W@%>H)k34xgX z^~93{G5h;vrv+m67lh6X#O!Z)EDpr%ujrc_h}qwAZCBd(b7Qd`Gf8j z3dHR18CeyG*(0If~M@GPnP8xme zy`8P`V8o5i8WZgrbn%CKEj@5%T7~3bT8*^fRnnab&x@u<*r;!_b$Ae?mxSWbie+R|F!?Io3{K*`Td={aL^m<{x>dg zDlOFuxEFU>yLFm1%P!2zo>(+9yQpw{cHx+!@%dwB78Vrek1x)jkUhR|-pt|x3*+-A z%r49?D)%cwnH?OX$RL!W~O^{^OB2Y=7ch8|36>2W9fwhb>o6g_K=?EjOmrr z+p}YC+nnBG#`&+dZdv+jtL~+*wr;CSwror5%E>t`{kQe(uFK@Q3s31+P%tys>)&=iyyMEERy?8I~6+VYOOFv1u?pIoJ`F8GNW5&3%TQnczzlU7+ z!8oB8@2#ueTeq_J;6APuDH%H zUgho-|8LzD^vEAKdy@aFai4$pvE02&xf?*&qh;Aub2qks@zP%lWOK@XDeX$HcCP!~ z;GNs^{4rg73@JI!-H!Sdx!(+Wt;c_y=}jw`F)6d;fBuK5+_EduO>EHRZnKgP0H;zg zK2PJ^v*hfl_WQ2nqB(jOPO7d+x6}DA<#_osp zJKleD*$wUP_;kf`-8JLY+_KM4xtqI<-a9vmFUdaRZOcA+?o;c3jOJXIG77n67IMpB zaJQF#O4-fMt&-bKp9yZ0cBR+XeYSOV%kHAM!CIAFA0I=>eS6vMpIZ(?2FgI}NjoQ|I{t8Ozmfa?NZLvEI zy*qaf@7Q_tKZWkYmb~IV6TGeTD!Gs4nqe5`zF_O}oakE!|Dve}pm{?jFQls^p!Qyvg0RI?LVJ>$TEfh;!$k@9r->_rR~v z|E%Qt2YneW(~w)np;Ta*0{0c#z5k-g1%<_>U$-1Ku7!W2m)_o`U%uUMlahP^zk!icN*_LWBGHlrnhL}LhZt+HFl zS6=$Xt_1a%G5`6Mm3)*wHaxX#mye+-lwr?W1@1J^&N?X}C z6)Xik_sxoOFG0_Ji>KU6&~x8>Dfbfe-1m0My|`}~ms|G!+_!Pcy#&2jxn*yU{@2d% z-1mS=ewFrl&9LX4|NZ>6ez8}7!hbzBa+kGldd1ndj_v5aZEU}8J66)seRsu+bKg;^ zYe#n>`yANY?e?;x`|fYa(S6UibP3R%{o5j zZYujY&+E9y{nBiIq2qD)3$Sf}R@aVI+^@xs^>l3KuDk7?I*xL$+n%K39qvC=~(E#g>HMHj!(O9rrUm1$A7B(JGq8`?BTw_Zf_r~$I%V^Jw?Ym-3?%ue?-Uc&hqzh9h+tOyMvC!?uN3h2HsE(`J`ui3gKWOjoFLbQxZg{)=nL1w7+20rIcvn|{Kc?dk-TnQi zjyb*j-ATtez5TsJ$L)Rn{icp_{rw%)vG+iK57+V9!T#Q$sWiaznkbdVWq!k>G;4Ze?O(;v1|SPw~npX_`AD~ z3)cF3g^oLK^!Ix@Ca&{$B^?K>_xC6rZ`kPXO*($!ekxi&-y!C$I09MJzK|zU-0*HI{v=H-+`C>WBZr=<2gDmdez_8==j>}{@$Zw%3J=f zrsI%Z{vM;_x_AA3w~n9h_VG+rXDVpuD`@gZ+v5Wh0njQP= zc%}Qfn(ehZ?s7k1v;DD-8SW=-w(ICP(*4NIcD|0cxu3n+eo)7+-4Eex|Dxkr?x%6K z+vqqm)8Cir_@w*!oW1>J9c#LucH3^OV~!m|p4UOUw~oVg9H(P}jtg{Lq2o7_BMNI=>Bt`_W#$*HFcNy z?~iMZ7rUM8rHA{E_icNu`)|Lyjd|gzw0W^)7Yq z&usF-+h(~?{{3w!_x>X8ZM?s$-0PfU@8fFs{*G{Cm3!L~_j>vFx81!zyIywvQrv&M zzqRgldw)6ZKYO{PNx-XR7to8n&HlShM=p0mn}F9>m$3tvdr+_Qri1QsnGAQdk83aY zy8p^wzgNordhPSW^?TaA?(EHU2mhsQz-!Oz?r0y^UhG)z)8KVyWIQcZZFCG-tlk8_`q?8Dy5VAoz}AaXWw1v_e;VeVzNz!JLZ2-0Pw1?EFB&M)xig;%$WE;~Rt? za+gT7zuT#y{=9x2H*>xCMw+$VZ0^N3)~w}b3-|YlYu0qLr5E2svxb|ky!fV?)!l6E z{z@{(T>`7*RHL0nr(OW+G(fScGs`Hc8c50-Sz9Boow4( zzmD1w+wS^x(oVANuHV_(iMHMK>#QBN?XF)J?F8HI`gPR~*>=~jn|8cycm29+yYI+! zYwoUJ5A8U&Te$1jQ`_Cgb!*|SUoUNU`zOW6*AKquZvV)&rsz!nPn@@PKH|>_Kjbc8 zLe34@-@RKRq@PZekp7wyGC)&825L&kAWaDwtSKQwG$mxHri2XBl#tE?jgX795i&*_A!D@>lBbQ3aoPwOuZ@ri+6c+lM#w~M zgiO*#$YgDVOwmTjRBeP@tnCZw6a2;9{*evt?k2vkFQnwJXqpx_IVNOg=ok0K5+Sp6 zs)Q73N=T8WgcNH^$ZSmsnWHHomuO1JTulj?rzs)xH4$>DHbNF?Bjhq|gj}wTkcHX^ zS)`4S#o7qDLK`7Vv=OpY8zIZI5ptzALax$A$Z~Cjtk6ctN^OK(t&NaX+6cKu8zI+f zBjh@5gsj%~h0F+6aCaGz74FMje1R|IT}LB+P1xj^kQ+l4+!w79Avft%3AtHQLe^Ih`sY+chQRc})p6i z{GpAIKeZ8ZLK`6`wGr}{HbPEmBjmI;LjKl9$UoW$`B&Q)@>y`cyZs|iIVSO+mk3GT zYxg1U$7DvwONoz<4}>;EJulUs&4dCvyN=uLVQ&Jvw%hJud6-?xZTGM|kzLbm_pm&P zUBhknusp)9?zVeap3JW1wtHBf!mjGJdsv>zuHv?PSf0kN?6y6xi4rPVaMv(KsA$1m z#dJai3+_5*5Hc*dD_Mb%Zoys4iiDU2cQq>!q88lstV~F=;I3#DLaGIKO{)@8T(D<2 z)dIEh*)sfv<4x`g1e?Q35gcmHLXPmTX5I3HX*@+yQXyrAq(!BW)k8pxNBOM z5VYW~=^2DL7woxCJwm{OyQcLC4oF&jd|V*7!vRU&WDie*0bkLl?&)&;nSrqJGDVF8 zp)cLHI7$?q#raayge^r)*;16nmZD~CDavL`Q4U**a@kVUoGnEy*eGgAKv63Kidqv; z)P{hfwgeQlBcP}~0Yx1MDC$T+Q6~b5&L*I!GXX_i2q@}GKv6dWinOR`Nb*)U2%9fcR1^qJuPjByoG(SQ*-|uzEk&2GrD!f&isrGUXg*tt zE@ey60=5)g#zxWQ1QabKplA^RMT-e2x`KeBB?J^LC7@^-0Yz65P;?amMau~&T0ub3 zN&jTH3Sr0Pe9RHg0E;+Ab7n4l3dX}(~d8cqBSMY zvjSoBWs24XLQl9K=9SzR-NN}&w4NQeLq=S$IxY$@8omZF!~QnZsTMK80Z=oPjUy~>uN*Vt0@IvYiA5K#0c0Yz^SQ1mtd zMY{+ndWV3bcL^wZkAR}x1QfkbK+y*T6zw6PXfFXp9}-aX5dlT}2q@Z5K+(qp6n#QK z(We9y9U!3SGlH+^xj?YC``LN&pZ3IkyA-`|kFGxtgw2;J`YI6W?Ec(f$$ilw&X=OE z*-~_vEk)n3rRZC>6n)2*qVL&K^aERpeq>A05jKi`BB1DJ0*a0jP;`udqF)Fo`jvp9 z-v}uBoq(d_1Qh*2K+&HB6rCWT=p+F}e-Ti0ih!ci1Qh*EK+!)06#Yv;kr!9`EZ={Q z79gM~j^Hag7zj>qK$3U3ADqU2DMfGDeNiwjY`#oUI4-oTjua(wz7!>~r6|IdqGYxd zrLd(al`TbSY$=Mer6|UhqI5QjG6*QDKtNGN0*WdTP*jQl^fTA-9D5^(5QGEi6&LnVO)PR7Zh6GXfTDH;6tyRyr~?5-9SJDvL_pEm1Qc~9pr{K0MO_If>PA3OcLIuf z5Kz>UfTCUm6rDprQEvi@`Vdgmmw=*k2`K7E@D-gE7d+;GBv*8Q>L>e*d_z z`7%X=<3j26rDzD}OVLoa6b)lb(QvjDoyV4<5o{?M$(Ew?*-~@?TZ%@pQ8b!>q6-Nq zx`=?HF$5HiC7>vefTD2(6pbgKXaWI6`2-YAB%o*#0Y#GuD4Ie*(NqG8E+(L88UaPq z2`HLDKv4k!MKcK~nnmyx4U7x6c0iJc*?rLf6BioMK#DHmd?}jC zmZEuVDVoogqD$FQw16!|m$9Yja<&vLWJ}Q^Hi{M#P;>D zob^)F)$WV7$A!(8DcTViI&_v4y~O!aw397GFSDiS6}A+;%9f(n*i!U5TZ-ObOVOKb zDSC^IqPGbs+C@OoI|LNHOF+?k1QhKipy+)9iasEqXb%BJdkHA|kbt6(2q@Y|K+%2z ziasWw=o12pJ|&>&00Bjx5m59w0YzUBP;`*sD|#U=nApTAy4t?$_@Webv`5!p#)Zw7 zDLNb%YMdoS-*CPZean`j@7PlGJzI)?U`x@DY$-azmZG27QuH%hijJ~Tbc}$aUkE7r zm4Kq(2q^lUfTH6B6#YR!(Vqkqogkp-BmqT#5m0oBfTGg`6#Y#=(LV$f{YyZR`*X+} z+|B5IqVB#`V?T`z5Kt6HKv9r@qId#|LIhvYp}61x2PAo{-4}f=MaOI;1jFXb6h(re zf@~>D=6oqiVM|deTZ+=yQWRxNQH(7`>1-*=U`tU2wiH!lqo@)AMU@FCszN|fRRW5t z5l~c}fT9`%6xAf4s1^Z5wFxMyLqJg`0Y!BQC_00HqIv`r)hD3nOah7;5Kz>RfTBhO z6g4KG=q!S-C@~nk!2wAgZ{KxH3i{9VpSSy>CjW=H`;LyPY}jzWhn<~CGAT2mOAAE= zB#jP&^xm5y0wF-?5J&<7qI5+-0TDz*k*27K1r%(E0%Ac$v4Emt!HSB4ii&WaC;PsV zyzjTZb8|&5rW9pxz7%D$rKka0iW;(|s1aL= z8ndOS30sPqvZbgQTZ)>qQPhHfqN@lfYDqv*D*}qHCZMP_0Yz;HC~8YUQ9A;P+7nRJ zfqPkRSHv)>f6HwHHfTErR6!jvYs5ik^l&q${;ClZwl%j#0FGbg|rRZ9=6b)ia(RFMo8qAiW>)BE?ge^rw*-|u& zjiM|9iiQ(Vluba<2m*>m5>PaXfTA1%ibfMqG=_kpu>=&2BcNzJ0YwuCD4Iw>(If(j zCKFJUOF+>S0*a;*P?SeNQ9c1h1q5GFKi5rZWE6dA{>)-je<^y+ej|ID8??TxqM5GO zwuuzY;(RH(ku62D*-~^9TZ(RGOVJ#*6wPHz(LA;k&1Xx|0yc^k5>T{=fTCLnD7uw^ zqQwLh-9|vs5(0{r5>T{^fTG(8D7u4yqU8h>tstOiB>_cu5>T{?fTFtyC|XTG(Ha7Z z?k1pUEdfRM5PU^9xbA2JB-GsA7R`{N2KFo3IyY#2Sw;7|-mT4~Xana<(F1HL+Q^oo zO>8OJ%$A}pY$@8xmZAsQQuGj8ing&)^e_QMj}TDwC;>&=2`GAufTA4)6g^Hr(Gvs| zJxM^(Qv?+4B%o*)0Yy&}Q1lD|MY{WI70YzUDQ1lhSSM;*${$_xLX4~&Nz9K~_ z_O|G2H)wrXMc=tzY4dmG6e{|j^QGtqwiNxymZH;aDf)>mML)Bp=ohvWoncGSuWTv$ zjg6wS1QeYkpy+o3ivA#==uZNQ&J$4d7Xd|o6HxRI0Yw)GDEgOxqKgC+T_T{!{P}MG zVLOTf1QeAbpvWblD2jk0kAR|R0*ZnJ6vYsHMc=q?GXo@4-+sILTPeEH-n)*C3R+)Q zQ9_h=U27>yybKv6XUic$zDs!l*r4FZa45>Ql&fTGI@D5_0B(G>&~)ghp$E&)aL z2q?OefTH>Y6r~b;MWHD7W&PtXTKZ36) zBg#EsfP@y98I>tTC+uxe|EQq#Wfff;<(+CTMT0nBimqcz(O|X|UC)-HA#5oc%9f&G zY$?iOOVMz)6lJqfG=hMlkpvWtBA_UTfTGa^6pbOEXeC^xQyQS^)buH!XQwB6no z&4>zGUsloVDDTQnQgjpNOVQ12DVoEUqPc7-n#Y!+`D`g#z?PzgY$;mAmZDqOD7uw^ zqQwLh-9|vs5(0{r5>T{^fTG(8D7u4yqU8h>tstOiB>_cu5>T{?fTFtyC|XTG(Ha7Z z?k1pUEdfRM5Ky#^fTDW|C|XbO70rrr`xqc0*Z#Td8>Q$A`^QA?iwas_R?)^NZ)z7Q z+Qj)%w3#hMTi8;xl`TaNvZd%DwiIn+OVPt@DSCu0MUS#kw4H#W#|S9eK|s;t1Qb0% zK+%%~6g@>i(M|%2b`enYGyz4=5Ky$6fTBGF6g^8o(Q^b8Jx@T<3j`FsNI=nE0*YQD zplBZfMK2S4MH`~rH3mp1$v!N5K#Hc?uV}AC1+6cu=+!81cQ+|I#Q9S68e589XG_r= zY$JWLy95-yM?le00*c-zpy&eviasQu=pzD(juB9F zoPeT_2`Ku6fT9xw6n#oS(Psn{eNI5pNdk(#AfV_=0*byOpy+D?icS$w^bNsRbRfz- zVSt1h+b?1VrRYve>f5NG^<@?P80G!jLyAswz7+k$mZG28QuGU3iq5d5=vTHB{l=D} zvur6k$Cjes*(myhfTBMMC^}C-(O(1<{Y^m8KLiwAAfV`90*WpYP;`laBFEFib`%8& zC@MujkxM{P6ahsZ0Y%XS6a@(=iXosVmVlx-0*XQeU(xqbZjGKs(R}+A?FT9P(SAjX z_kz}!RTTET_PwPj!ue8^%$B0kY$+LNe zm!hU@DQd=+qULNVYQdJGtJqT1k}XB8*iv*gTZ&q2q@}E zKv5?GiaHZe)P;bet^^cyBcP}|0YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z z8c6UJHT2va21uy9z4>V*MeFUj#tT|sR?%S3d#Aq?UC;SaG=wchL)lU^j4ef3Y$+Pf zmZEI76pdg@(MYxwjbfuHhk&Bd1Qd-SplB=sMdJu48c#sc1OkdC5>PaWfTGC+6y*|7 zG=+eosRR_|5m1y*Kv4k!Mbii6y3s>qFdQgw3sbLx3N*Q zgn*)@1QabJpy+l2itZqwXgL8zD+nlBNkGw^1Qe|zpy)0FidGX)w1$A9y9p>-OF+>* z1Qe|!py*x#iq;cQbRPjl_Y+XGf#55;$#Yv6AfZ9_VcE@6^tQb%dcX@>Usll;&%1t* z6m8{vDSD7CMGvv1Xd7FK9%f6?BWx*plr2Tu*;4cvTZ(qDQS>+gMNbe=^dtdAPZ3bG zlYpXK1Qb0@K+!V<6zwLUXb%BJ&k|7d905ho6HxR50YxtoP_&nTqL&CL+DAaq%LEj? zLO{`e0*Ve0d_|i)cdh{v%CmQcHcQbV^RlReUeNloieC4;jf17=4bGRMH`!8jm@P$b zv8Cv3wiLa?mZBqUDSDSJMenht=qMXS?-Nk;0RcrH5>WIJ0Y%3MC^}9+(Z>W7eL_Id z2?B~fC7|dt0*XE-py(t4MPCq5^d$jBUlCCBH33DZ2q^l7fTC{+DEf|oqVEa5qC=kh zssR!*|2%>d^_moYY)Sp#1+6cu=x5LSc8C=H!ue8khAl7JKtNFR;46wmyZsE1&=z~|Iyu^Zq#tJ=_BV7vx|%ITt=Ur4hAl;H*;3SwjiUAh6m=k=s3QSIod_uEOh8c= z0*bm4P}GfpqV5C~^&p_ACjmvh2q@}JKv5q8iuw{z)Q^Co{sa^aAfRX<0Y%pkP;@N; zMS}>wq9)PqS_33B%YG4SDn&c(k7lon4q9JU(a>n`*^yE-jPs=^i!DXN*;16vmZA}C zDH_R^qET!q%3({l>d(F6jDCK6CIiGZTX1Qg{GP&9>rqNxNF z- z(K0rQZYQAV4g!jn6Hv5*fTEQI6x~Tc(JBIp?joRQH33Cy2q?OnfTFbo6x~BW(K-T( z?j@jTJpo1c5m0nL0Yw`KD0+Z^qKyO;Z6f%J=0>}n|rDz-HOVPt@DSCu0MUS$jXggbq9%D<<4z?6M&X%Gl*i!T)8%0kMP_&bPqFn?O zJxxH-GXxavCZK2!0Y%ReQ1l!DMb8sZ^a24zFA`9+mw=*|2q@Y|K+($t6um+~(S8Do z4iHdukbt6B2`D;5@D**1cE=kap>y`;=Rql&Y{zTSLF>yZIvnjS9WO<1alRD2&6c8f z*iv+aEk*CLrRY7j6dh$t(fe#E`hYD(AF@&O5dlTV2q-#EK+(qp6n#QK(Fp>IJ|&>& zGXjb}C!pvg0YzUBQ1m4MMPCt6^fduRrwAzehJd1P2`KuGfTHgSDEfhbq8|w;I!*8u zy%Fs`VSt2QvR~2Ol%iJlVgFCjLF>yZ`Zd~nccK*i#`#iomMul+*i!U6TZ;Z*OVOWf zDLT)VqQBTu^fz0I{$Zo&0s%$;5>RxJfTBwT6gfdXY)4UmfTB_a6uATxMG;Ws5l|FO zKv9r@q8I{-VhJdUBcLcmKv6saMF|8HB@$4SL_krPfT9S&SM*D?`-cG%I%scx&PdS% z_TF`JFlc>QMdgBC`CKU~&-qeRfh|Q9*-~^FTZ$^NrKmDnimI@ss482Es z1QgXEpr|GRMYRYhx}1Qb+5{9`K|oO*0*dMqP*jhAqALj~s!u>sDgi}l1QewcP?SMH zQ6>RJ4G1V|NI+2|0*V?FP}GFrD=HIoTN)stdiIfi*`WVO|Gd3nY8nh$UslmoL2u|( zDQe02Qq+nqMOU+>s5M)P+OValEnAA(v8AXzTZ%fcrKlqtMV$yJ>P$dU7Xpg95>V8Q zfTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF4IrRsAOS_!5Kwe20Y!rdD7ub- zqQL|dT~F{8H4nP;4Uo`hW=6G;qBZumXh<+4EoDp5GPV@m z&X%G(*iy8djiMC<6s;tn=uQHPRuNEi7Xd}92`E}aK+)X<6s;wo=pF)!))7#2F9AjC z2`IXcfTH^eDB3_k(E|h&Z6u&*69Gk=2`Jh^K+#r$uV_KgO`L8NZ8S4#p%gu4zoI=D z3|e1S(IY`GeTEc0%K1{Xoh?O=v88ASTZ$fMOVJZ-DSDDEMNhG%XeV2WcCk_PGyz4= z5Ky$6fTBGF6g^8o(Q^b8Jx@T<3j`FsNI=nE0*YQDplBZfMK2Rj^a=q*`w1vIKtRz! z0*YQGpy&_*MXwQ1^g01WZxDP%+k)-@10?jS{eNR0mZD+yw&=}Z(E759-U)isW=YWz z&X=Nh*;4c#TZ)ddrRaUO6n(&!q7T_p^buQ%j+t4YHTS=VM|eUwiMN1 zOHoZWifR#1bU6Vc#vi*wIA|_~k zSw&aJc%A1-QESeZqBd+PYRi_Qc5EqX&z7PNY$@ulUO(Le%o`J+k}au)F+uCgDq0-l9bF_vw{gA{En!R1QnnN=V@uKPY$>{fEk(=O zQnZ3CMJw4-bSE1{s|YB%i-4ll1Qe|ypy+M_iq;ZPbPoYV>j)^imw=-61QgvzK+*jK z6m1}&=m7$XHWE;@iGZTb1Qcx{plB-rMGq2C^bi3>+X%j*TVmYv21sZ}z`(gxibD3@ z^}{hi>&q&7EXJ$2Sc-OVz7##qmZB%vQuHKSik@Oi(N4A$?P5#O(`+evhAlY0|XQuB%tV30*Ve1 zQ1luBMXwW3^acS%ZxT>+n1G_U2)?36W8A9^kWeo(qqa-YMf_<7F+8 zqNAKIMennv=mWMCeaM!gkJwUlj4egS*;4c|TZ%qmOVJ57iasTv=raO}J}02)BmqTV z5K#0b0YzUCQ1mqcMW+ZT`i6j_ZwV;+j)0=?2`Ku3fTAA>C^}6*(N6>v{Y*g7F9Z~w zA)x420*Zbk_==9ixC;#sbK_&+yemcb+izr_jR{&`R?(j^-qvMObe{92=r6Vu{mqu5 zf7nuVfh|SYAmZDm0 zDY~33MYY)|x`KeBIs_EeC7`Gt0Yz65P*k6QqErHk(g-L@C!i>UfTBzSiW(45)R2Ip zMg$Z!CZMPZ0Yyy-C~8JPQF8){S`bil6#+#p3BIDsV%_j^qi9yNfm12gf26;|j#jZj z>&q%?8|!7Rl%jT=FGcOyQq+MhMIG5v)QK%co!L^49|1-86Hv5)fT9No zDB4Is(Ix_lHWN^^g@B^11Qb0;K+!`46m27*=wSki9wDIUQG&1NwpjN|10>YZ%%~+& z)Y(4l-yR#ZzO14rVm)`Q6g|oLQuGvCigvQ4Xct?Go@PtYGi)i^&6c7)Y$|kMK2Ig^dbR8dkH9diGZSg1QfkYK+!7%6zwOV=l}sl2MH*8m4Ko{1QfkSK+)?2 z6um(}(VGMm9VVdYEdq+(CZOmY0*a0hd__BA-8u$HXo>wsz5>RxGfTG_CzM`YC?qmZb)XlYCMo~QiimoJ}s6GKjsRR_I5m1y)Kv4z(MVSN?H6WmW%cN(xo@^=V#YRzY0*d+& zP}G-zqJ9Jv^(UZc00Bh<2`IXTfTC*&C>lgS(RBnA4JM%IdIE}u5KuIffTCdp6lD=m zG@O8f3BcSMB0*clXP;?&wMfVd>w1I%42M8$INI=mh0*W>h zP_%`BqOAlJJxD;&Lj)9UBcSME0*W3Xpy*KoinbF_^cVp}I|#m_WpVCd10>Ykexvbr zDN3=A^dFB4T3=St&N%O2Am$$#-g4UN+^lzLubGsB>7JKtNF<0Yym! z6om;WiV#qgOh8d-0*cBIP*j$HqH+Wjl_#L60s%!82`IXZfTBtS6jdgms0zVX^iQ07 zzX1|DYHy1!NYNVevZ$(|p!H=H)d+bn?U16HoG(SS*iv*kTZ(G4rRWN_6xCr%QC+qa z)niN1m24@h&qh%y0Yzy96r~eTltDmICILka2q zqMHaPx|x8YIRq5VC7@^?0Y&o(C|W>3(Lw@>77T|5fTG(7C|W{5(NY46 zmJxhK<3sKg10>Wp&cK-&q%y8S+*>Ek$>7z7(xuOVM3yDO$~zqBU$O zx|=OUYuQqC4_k`Xv8Cuw1I%42M8$INI=mh0*W>hP_%`BqOAlJ zJxD;&Lj)9UBcSME0*W3Xpy*KoinbF_^cVp}I|wLxoPeSy2q=1z;44}la-T6kLND9f zq7_nfwf&0rR48bDSw+u;ypMKE(QeL{qCIRWdX_Ck&#|TGdA1b2z?PyH*;2HZEk!S} zrDz`;MK2Rj^a=q*`w1vIKtRz!0*YQGpy&_*MXwQ1^g01WZxB%QCILl<2`GAtfTFhv zD0+v0q9X(py-PsRdju36C7|ei0*XE$py)$_uV`1uy*1GZ4m`m%~X z33*kXlcE!xFGZiSrRX!Z6n)N?qLXYX`hqP*U$Uj>E4CDU&6c85Y!rP%K+(4Z6n#fP z(f0%t{Xjs`j|3E*CZOmi0*Zbnpy(F@ip~&F^eX{HzY$P$mVlyj1Qh*FK+zur6#Yp+ z(Rl)j{vx30Zvu+`A^3`phun4sNa%>Ycm1&xHMFEIgo4(WRpi8bBVUlBK)fEwOHnDd z6uE3EiegKV$CjdKwiE@~QWV3MqFA;R#j#NoBA_UqfT9EfiV_JZN+O^rOh8eDfTCmq zib@kuREB_}vIG>BBcP}}0Yw!ED5^+6(Pab_RU)9MG66+Z2q>ybKv6XUic$!^qKhGS zu>lhL%Km}#wiI2-mZJJ> zDN1EaQ5su{(%C4=AfPCdfT9Kj6g4EEs1X50jR`1fLO@Yd0*aauP}H1&q80=cT}41q zO9F~o5m0nB0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7_=;-AyKfsHp+okzs8+oGKmB+! zI>iUAFRQ3qy!XpKDeBJoQq+SjMLpS4)Qc@ez1dRKhb={Y*;3SxEk*s=QZ#^#qJaby zT|+?8wFDFmBB1Cx0*VF`P;@;3MMDTE8cIOXFanCQ2q+p(Kv6aUMI#6(8c9IWC<2Od z2q+p&K+zZiipCO9G>(9x@dRH{mw30#%SMrBzw6jlitJxF6Ez_|Xnk2lx$$1({ZcfA z^QCAiTZ;17Qk2h@q5`%QO=C;ZbhZ@Tz?PyJY$=+_M$s$+if$yJXf^>wHxW>DGXX_& z2q>CMK+!w`islngw19x3g#;8WBB1CN0*Y=WplC4xMYj=9w1j}7r34f$BcSMZ0*dY+ zplCV4S2QW!9c+Mv+S)tRlclJ?9V_C4)|XXuSG;%QK`C0z`BJooEk$>;rD!c%itb@c z(K@yi-OHAu^=v7+k1a*_vr)8xfT9NoDB4Is(Ix_lHWN^^g@B^11Qb0;K+!`46m27* z=wSki9wDIUQ38s#6HxRR0Yy6qD0-ZLq9+I_dXj*mrwAz8NkGvqg0JY#c=rJVB-G9R zx$9L@^p+h@#|N!1tLWKy@8v^M^c?3)(erF6dVwuPFS4a*FI$RUVoT9JwiLb0mZDeK zQna6qq5}jJ9VDRWRRW3*5m59R0Y$G9Q1k`?MQ;*NbeMpmw+JYDn}DKs2q-#2K+(Gd z6un14(NO}5-Y1~w0|JUZB%tUc0*a0iP;{K&E7~3Jeq(@yYT28gJyKNFye#VD_@MP= z6@6y@J?l55=yT4OqLXYX`hqP*U$Uj>E4CDU&6c85Y$^JNEk)n5rRY00ioPeH=m!Fd zek7piGyz3F5m59q0Y$$MP;`cXqF)Ip`i+31vjh~KBcSMa0*d}1py*Emip~>I^cMj| ze-lvj4*^9N2q^lOfTD{8U(tzpx4r=qy671=pGr|3`$+#%e9-!`irfUR=V2*|O8C!5 z`W{<~qS;auWJ^&DTZ&@YQWVFQq7Yk(;@MJ^z(!Fb0Yym!6om;WiV#qgOh8d-0*cBI zP*j$HqH+Wjl_#L60s%!82`IXZfTBtS6jdgms0sl^RS77nMnF*t0Y%jbD5^m~QB8uc zD3IXh86cqtEu2yb{$sS#=4DZ}5`xy3Ra7UzTlKaS)#ZHM7S&@*(Uoi|s?V09RJIhQ zv85=TEkzk@DavF^Q3E!L8WK>{h=8KT1QazPpr|PUMa>8(YED2=3j&I+BA}=x0Y$9{ zD7u<}qSgcywIQIWEdfRC2qpy+x6iiQwSG?aj%VFVOq5l}RofTC;yibfDnG?IX#Q3Mp_5KuIlfTA%3 z6pbaIXdD4W;|VC5KtRz%0*WRPd_~<8+=~WCXqvq(>LEq;+eA^56N1*4Rg{{dEk!ffQZ$n-MYGsabR%1eX0uUr69Gjx6HqjVfTFns6wM=` zXg&c&3kWD$NI=md0*Y=Spy*ZtiWU=4bQ=LhO9&`hN`*sN$?d-NpL$DAffa2XZlm6sENI+y(%GSeOX0!CwMs@NYPr(m!f;vQnZdOMfb9$ zXgyns?qf^Q{cI`Pz?Py1*iy8SjiOBi6m2G;XbS;FTL~z7kbt6x2q@Y{K+(el6g@&f z(W3+uZ6~1UF#?Kq5K#0u0Yy&`Q1m1LMNbh>w3C3MT?7<8O+e8z1QhKi_=;91xJwL> z&>Qx{|VTecK^$Cje+*;4caTZ(>Uqv$jN zML!Wx^fLiPzYtJ#hJd192`KuFfTFVm6rCfW=yw8&{ve>}PXdb06HxRQ0Y!fkQ1lN0 zMHdJt`j>#Biv$#1BB01g)B|%A1qi;P&lB8o9~(u_*xRC$QuMXGcU>wmXnk2l(TQHu z6H*l9d?|`yOHnLaisIN(6kV8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}GfpqV5D=QQbs$lK~Ri zWB;sUJt;bFN%cq!T3=RCpG0r}Nh#{f`BK!6Ek*s=QZ#@qMFZJVbPZdIu4PNnAhr}; z$CjeOY!qEjK+zBaiiQ$UG>m|vECPy#6Ht^*K+y;SibfJpG>U+t90H0)6HqjUfTFPk z6pbUGXgmQ$69_1pNI=mf0*WRRP?SqR(G-HOs8^!vDguh`BA{qB!B>=@=%yJUq51Zw4NhY$@8vmZD8;Dca1IqAhF`Z6%=SK>~^%BA{p+0YwiJQ1l1^MUN6t zw4H#W#|S9eK|s;t1Qb0%K+%%~6g@>i(M|%2b`enYGyz4=5Ky$6fTBGF6g^8o(Q^b} z(b`0}zyJvivEOyPM~WV|w?)q<2CXlv=%qw&^|w;AkMpJIWwsQ(!j_`_Y$-axmZF1f zDSDMHMTgi@^cq`=UT34|4FZbZB%tUp0Yz^SQ1mtdMeh($bcBGScL^wZkAR}11Qfkb zK+y*T6n#iQ(MJRn9V4LVH~~c;6HxRC0YxVWDEgFuqR$8@`kde^dNI*`&HxFe*tQOVN*PDLT!TqMz7O z^fMbpzYtJ#hJd192`KuFfTFVm6rCfW=yw8&{ve>}PXdb06HxRQ0Y!fkQ1lN0MHdJt z`j>#Biv$#1BB01g(!+KX1qdiAML>~DKv5LISM+6~>-=C8?X+;dlA?S|%1a7bUsh3U zl2`q-6vc7A6ouGQ6wj8T1hy0ydKv5L}imDP&RE>b56atE>6HruxfTEfN6xAZ2=yC#zY7yc@D&A<+)f5aXqmk$6qDpX(!br3s+SbBzO16OByY^mQk2g5Qk21#qD;0F zHDF6oL$(w(VoOnDwiGpCOHos{6g6X`s5t>eEeI&Oih!b)1QfL*py+A>idqv;)P{hf zwgeQlBcP}~0Yx1MDC$T+Q6~b5IulUTg@B^21Qc~6pr|_mMLh^8>PbLRFM_YAev-S) z0154~kI_=4=v3hYwxpo-Wfk>L@*X=QMFTiriUzW!=o+>ZUCWlDL2N0yjx9xl*-~^p zTZ)FTrD!M{MZ*Xv$|9g>H~~f31Qd-RplBokMWYBP$|0a=Gyz3p2q+p$K+!k?ipCRA zG=YGki3Ai)BA{q80Y$k46ip$ZXet3kc?1;Y6MRK|lic?VkkDBBz3YBbRNdYd6(j|% zFRN%ql6UquDVoXoQZ$P#MK`jgXf|7lZemN(&1@-}!T|AfTG6; zDB3|l(c=UZJwZUxlLQn!ML^L`0*ZDKQ1mnbMb8jWw3~pUJp>dzOF+?c1Qb0_K+y{X z6un6B72TWU4l_VPjqGjFdMV1WU(xm^1+6cu=#?aI&Yx1WpYx^Y09%RWIR0Y#q^P;`=jqAv(2`jX%)+Lz>RF+f7y z?8CB`r6|jO3-YU^p!H=HeVgPR{7Z_y<9sRlo-IW`u%+lnwiKOaOVLkkDf*c$MZd76 z=nPwmer2QRHv)>z5>RxGfTG_CDEfndqCW{JI!{2+Uj!8WO+e8<1QcB$py*!$iY^jR zbcui>C#;9shrQ4RDN5jcDN1BZQ4(8773GI(Ha6)1Kk^W2e%UfzVXnk2lnPIQ*MJZ~)`BK!7 zEk%vkQq-6&MNQaJ)RZkn&Dc`ZoGnEy*iv*A8$~S%C~8GO(bWVLwI-mb4FN@M2`Fku zKv8=FiaHQb)RBOqP6QNnCZMPb0YzO2DC$N)QFj80dJs_5lYpXL1Qhiqpr{W4MSTgr zqV%vk-2e&wY;TJ)r06?)@48<&Xnk2l*Mz;h9eV*8PSmxWFGYjcQgj_#iUzZ#=z6vk z4Pi^sP_`5eV@pvMTZ)FWQIt(U(Fg*HMiNjoih!aV0*XcxP&9^sqOk-NjU%9FJOM=$ z2q>CJK+z-uiY60KluJO-6atE-5>S*!Kv6ycMFj*DO(URaI>A>oAnd+ifP_}rADs=9 zq6GU$|AuhT`m%~{411rJlA_t1FGV-8rRZk16wP5v(Ok9^&0|Z^e6|!VU`x?LwiGR5 zqv#d_if$#KXfXjrw-HdZgn*)@1QabJpy+l2itZqwXgL8zD+nlBNkGw^1Qe|zpy)0F zidGX)w1$A9y9p>-OF+>*1Qe|!py*zLuV`l2E#(?T1MK&%XGzhg_O@t!IB0!YMGu6% zn&z*AD7-D&$oW#Vi7iE&*;2HHEk#?|QuH8OiXLK1(KfaeJT{@fTE`fD0+r~qTK`(?IED(SptflBcSMc0*YQB zpy)*ciuMvv^b!F@`v|_G`@?P*10+##g?MC*;4cl8%0M5D0-KGqW1_WI!Zv%`veqyKtR!l z1QdNlK+!P*ijEUd^f3WNpAb-Vf`Fn=2`KuEfTGU{C^|_%(H8_1eMvykR|FJ&O+e8p zg0EonxcucLIw3AfV_^0*cNPQ1ll8MSl}e^bY|=7YHc&mw=*+1QcB& zpvZ~nVLOTf1QeAbpvWblD2jk0kAR|R0*ZnJ6vYrw6iYx+9Kl!gUD$o!014%q8TGvs zb+V82Ly@5MWfdhwyx&7o6y|&>im;_9nJq=7*-})7Ek$M7QdEvDMdjI2RDmr;71=1d zjDVs_1Qb;!pr{G~MO6tXszyLj3IRpc2`H*TKv7KsifR#1bU6V{$jiS~B6ty9ss4W3S?FcAp zPe4%z0*X2kP}GTlqRs>qbs?arD*;8_2q@}KKv53@ih2@I)QfMp`?|NV)Xnk2l*G0T}VJRBS`BHQ}TZ)FTrD!Ny ziiWYJD2pvc!`V`l&6c7OY$+PaM$sq&igE}j8cjga7y^pM5>PabfTHmP6ipzYXd(ec zlL#o9Oh8dC0Yy^?D4I$@Q62$B`2-Xd5KuIYfTHOH6x~2T(F_8LW)gfw*GAk24Uo`_ z_O@t{6n$jB1vx7cw7#sOn75K#0Y0Y!TWD0+#2 zqJ0Duy-YySD+CnnC-{msM%)GlNT{0q)BBsG=&-#lIuHq3Uslm;5wCxFDSDmrrRWW| z6urroqQh({dW$VZZ?mQ79kvu5VN21wY$#uK^PB>}}C$ zDGJ%IXo<-|>&q%iPWC>pBt@k;Uy91GrKl`hipsI2s61PWDzK%fB3p_sV@pvbwiH!n zqo@i2MO6tXszyLj3IRpc2`H*TKv7KsifR#1bU6VjgetfHpL z-sM%Ls2S%=QFFEwwO~upRctA0$(Ev4Y$>{$Ek&)_Qq+bmMQzzAYDYj(djg6&5Kz>S zfTB(W6m=$`s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+ zG?0LzYX~U1mf$ODoa}ZpKtfkqI8CI;vA0Eol7rTlRWu~on_&J$;=-S!4dr|(8pf8Q zEVdL4XG>8wTZ%@orD!Buibk=eD2FXYquD4LLqO430*b~FP&A%^q6q{PO(dXb5&=b% z2`I`XplAvKMN{pEk#S%QnZwfqGbdW-A+K!9Rw6DC!lBr0YxhbD7uq?qE!SG-9BcSMh0*W>eQ1k!+MH>meqB+U#hXzRK8#ANkO3^QN zY)TGVUrv%!Dyn8|_1Xa^{FwQXtrLF7f(zS!+%YCx+B}+z4>vY<&BNhq6C9^Z_}(PP zsSy4m;y9JVSCny_l<=f-j#DeVvx4K)3IBDOW@|*aSNQrtj3GN46MlE1+sP&dH2t@2ZOVuS1vHz}6k3i&?edam|MC`xp zF(44J|1`s(K*avt`a=Q{`MjYX|AC_#Qr@a%K{Pm7e%ZHMC||Re^(%4 z|5xp`fr$NoZPy1P_J5XqAP}+tx7(IL#QyI}+X4~$|C?+NMC|`C@I)YD|HSvMK*au$ z-93Sb{WF&@1S0ki&Fu?B?4No%5Qx}6w(?paV*lL1;XuUx;P^-&Vt?}Yejs9hbaN~a zvEO??5s27to}LUu?03Ju4n*v?FTM*z?BmbVfrxzoaV8M4_W;iYBKAx8`9Q?p244s` z$={hzny4-Qr(Ee6*IbzmO)Wvfa>lvHQb>>$&`%IuoVROob>?<_YSZpt$S>gio3QoDz=2JD$TrXK_-b$c_#zuS2 zRT|suXsOXJU`8vA)8;lHaJ9zvI5S#njJEGV8-JMRB7w^jONZRVN{Iu@M*`vUj#H|Z z6AE2zlH<7L95=B==&DfjP}kDtW1^SDIF8rYu_ZdmysmvFSUM02`L7u;GbX`tV>mGs zN(jY=nwj5HZ2A9qtvK^qB`!Xs>G^LhUKeSmy~qSzWZ_GTFEUXVsn<#}Cway1M>xT} zoAxb73ZL;DCt1HGy^+#sfz}myC$6X%2_#3isc?6@ismZyO1yKW%I|JxJ~U+;{m)je zWUFl6REa0cAmH?|2XiarxK6?B4fYueDatt;=(E8*^B+$ZPr&JG54=*}qE{*vFjsNm z(`DwrrJRfn_E_SL*wYH%NZ~7)|5P@=>{kQ(=6JG~Tk@&oUTzS&PG56MslY#p2~NN~ znb)@sD6Gx8C9yd8Zeay&_S=o7$(lax%8fG=fXpotenPFq9iK&xwC+DQ* zWRDn^nwgQ-Fx9>|&Aj+OUX(s=^2mwPM&+bW${sm(+~oh?-;Mm4`6WLRW5%Yp%^Njs z+~nN$xp_IMMIVb91$l)Z68|I8Cogxr`IzUY_n(rTH=)zC$yo!;?`2G%iPQ44`n7G+ zv+@7M)igc3Ajf{R9LK++M^BqPGNVam+DJ}eAVvI=HS$;nR}YlWGsYt*>O z1!fpQ{o8lUGVkWd_PLWLPLXIkM)OGP*Es+e5L zo?(yf%rvjOeWtNqp8j7ipP`r6`5!MYJdKMjK25n+;ahR1r+H=Vb9!^;&8D~sDTQx4 z5M9#?nU|UOG{qjw%L=D?sd+C0(WSlQYF?mKsc7>F*so*ftWFtS9DB@cmeD0^g#T=l zMn%syZeR3llV*C&M$Kq#IXR<||FVwl^*Wj6mB;nS&7G3z^lUpQt9`El4gAaQz$uN3 z-dGzaQ<3&d6-fn=peU)A=S_`kf zUkdGeZLeE*Ki8;MkH#eJ^IJ7Ue z7i5k_AAH`R-aT`Jr580Ux?0Q!msc-Vg%g+*(P(BaDYxiTp!j;`i;BG|(#4r`xM0KE zzgowfVo4V*XKlY9Tyf0r|@f){~6S==xlQh=n{+H1KgO8 zkX}~g!(0XaTPXHsZkNn!6<&DZi_GVb&N5#@^jy(z#8~#vH@Cu$xnr8=e^fI4gFd~B zHDnfZC{kUlz z<(b9Td1mpI&NY&0-r2&F%@_8S6vs@RVXocc543r%bFYCZ?VC4GvG?WEGE?lm`HW@_8l}|9%bA#you5-T zC3VusDbrewG#|N~8L5*RHZ-AN?6gTE%yIO@-0Xr>^H89bxq3#~U|w_dlCI9nrA;!AF0LGvKjq5NQ&LjLq@?z4kdkWd&bAt9-htH7lXCL& zv&ZD5PRyA+reJKV43qr(FRAw0H_P526pYKAoSJX$mYZX~X``|WvWvF=p)mIW{AY^k zW)|DEEdRH!T|UneUu}!-R~W;EmsxyY(5kc_P=g*Ix9+ zvk-Sy)_;DT=bmWs9Z~q$yH343^)LGRoyq;q;`@-rcO8rGIhy;R@bNzz?7LUwnR}hZ zcL+<|ALLGF@tr?DF*3QqwRa5tkB~(A_W%n&1om#H?ui!uR{c-IqTfEBc15T$ZSQ_g zD7q!&US{zhg-@Zjk z9s7yXHg8f&$4Mh{MvXFevIp?^x$tv|$HjI3_s=XR-aJ^lWS#;}so9C~2~LF)-z>1- zD`=Y-v#`{nz>I?j5}mfqO~|$nyPZI~dDd%|+B2IZ(A!jX)aT$S85yB~z61>!lJeG7loh6=J^N=%A zV%zV3lrejDQL_(8i=SNkbG;Hzu4BHlR^rKZ%=f%XJh_hfmRgA?xA3D@99+kI_pHQ| z>x4@z`~D~Y*Z$A<)-~^~`F>O3@7jLMlkG$3|9&W5tH7x>>c8$6o7c79lPqPw;ct)T z-LRKzk7ac<-`jFZnHN^KNAtsgI_mcNv#)2qXJ2?U->EM=w$rhXjstZx-yA4>`FI_t z>NrP7`+nQYTcP7-9e10n&i4H}9yh-=yHDx(kNFMQ9W+;gJytQl7kjL$V{7w0HoLp) zm~DO!c2Cmr!6bk0)bX_W0N9uRrDFpF!S2>N&M-gtuzQh?dkuKI-_$XxlD{K5b~8T~ zu`jjWnh&gf`ByqtuI2B#I*zFA?_3?XnJd7){?j`CT+iSC=-9~oaK*m7 zt&X$I6=nCWI_}H#_ggwfn{No(mzUPDhq*%SzD~zG&36gy-k{^L7XCh^V^wp-+m~Od zE`cubd2fg@3K1f>h16Ab-b&u zzc=dmaese*t7FPF{!Z0#^dNud>$rWezn|6dw;}$%q+_!ze|OaJ=4^j2)$xFVZa*IH z>KHfL-{p1eGuGcjbzC#v-sTY#-|0Gzo$BvtI_}8#_wzcQo96GpbpP05 zhJWm=-ssN)}Z_}g9XA6u^Uk6m?~zsldsb$o5Lzdz71ajm~A={R7Wzq55*x8C0m z>3GuoEY1FYf6}q`Mt?WdapGow&(!g$t^R&V$MX;Q+uPp1xZf8VI%uD$+#S;xQk`8)Ws ze{8egKlaq|mV^FYrQ_j4{ywf_@*DoHrsJT){?5_y{NC-ml|@c}L?`MC{(Q(fie;?HGqWQt3^%OemA3OZ+AN%UKclu z{Qaqp7MP!O+C5Ll=gf~h z?LMTV`LS~0PSCNF`5~x%d4C<3nV*K*eUFasnIDVV{ke`6%+E*dzFfy)<_D#APtb9T z`H89BPwM!C`O&G}f9jZFeuipyD;=k&_{VDVQnY%SksU-6U3)G#o{F##qvPYO>L7smc%X8+zbAgj)AFVoR zBl7c|G#k?X^INTH<}r8LDEsYS^F8;`x#raipU)mKA}?pUQ{tuO2YDrDc3$@6F*)Wk zi_ia`WupBtoG#J4Q%>4Q^E0Cy^MipBXN}Iwo@8FBZNHvr*#!l8<3>y?FcA~e|^3B=5_x2?JhKp zCwslwrw-;9mu>eR^DE(s;=*%nOgDFd9ecD-Yp)78gG{jg%++4_LpJ+<^)bIV$2{vC zG?z7?MBv#G|Mhwm>js>q_5?lgdc({v`F78A2sm?1vv1eFJ^TBx$EoHQ=a^@mE#~r4 z>@#}eWs}S=yPf;xbP78)P+P7<;?2*p_yW5!8%P_H=d7jI&A9wpUOMJMTDaPOBrt!q( z+1tgEueZ&-f99@0(G#y%^5JZQwA}Q}rWs9|Wi)8kpka#n?nFjriT^ff(kLaRS)<10 zdw2F}c-)+hJv#Y+G{L{vfO!nZ#ydYQaLh5#f9xRV!Uyl2cQOy3kIL|m zF*?Q<9($Y*w_euqhj+bhrN`bIxbS}ObNl)aJs;KmX!exO&Pz_XTpRPPgf_cxJ?X@n z&qMz@j0*g2K*dirt5M01ym`k<1)_)A$F+f&DduybR4MPvpgjb~ndp`?zo}9^E11Vg z=7+}K1@jX3X8T&bD-JJA!5_?ZR4T>`nlBZlVuE$ewGb8M*>7Z(iVD7KUd8=?sJaU{ zDa$?X!!tWO%(BBSGc<}=h?pRups0wAiK3#Sh=3vnNSLVDg@K8RfgRZ0-G$xVii+L( zKKIW5df)T<`FP~_g&X&rz0R}qEIYHM?3Wi-Zogjo@to{mUFg$cME2ui_E0_jtLJ9F zWvlu$O7-D7?3T^`x%!o2 zE}qQ+x%!o3E|$&JvlrQm*)^MMJA3=qkDYz?YG~i=?b{%BUAFsWZ{LQov+LW?e%af%QS9vf z-@3lON8!cn{oi+02-zZL2-z}b2-zxT z2-!Mj2pJwTglrQtglro#gp7z8Lbi)Z$o8=b*&#L|BV!Y?V{AfpicQGQu?ZO!n~+^% z6S8Y;LPp0XWVhIajEPOi?y(6O8=H`Eu?ZO;n~*(X6S8M)LMFr}WUttSOpHy)-mz;! zHZA;+z5g38$Syba!)ii?W!I_teM(7A5;D2i@&(B08nS;J4IxuvhLEW-L&&t4A!K^Y z5OP4w5OQG55OPq=5OQ$L5OPRNLJo~h$c)&892T39!($V2L~KH4#wO&**n}Jvn~$Yrq!xjZ%@SHvdd%GiWl6`PQ&V-s>s zY(lP$O~`ez37H?8kn3X;azkuFZj4RHO|c2NIW{4;#3tm{*o52`n~>XM*Myu|7?8dH z8>gge$XPWZ@24N%QA%=>kb8>hi3=@4?v0}%)3>R6Pu8Qu?hJ$HX+}|Cgl6rge;0p$Pcjz`7t&jKgA~G=h%e&5}S}; zV-xaQY(jpIO~@ay3HdWNA%Ddtw(@BhX-(_@eKTZEKf zP1lfIzLe;sXV}%}i|Hv(Ezi>|=Hqlc!>*Mb&#)`m@eI2LJDy?J+Ky+~HQMnEyRse6 zuxn$-Gwhn|c!piG?HP7$1<$an2%ceA6+FYPo!}XE?FG-U>mYcBT}Qz)>^cdaVb@vk z47)CZXV`TWJi~4=!87a@7d*qRo8TFCO9-A}*In=oyCntBuv<#-47;TT&#+rY@C>_U z1<$bSA!I$5M@EKS|MLdPnl~`w4(E&XeB!o zt!#&)RqRl-svU}Y+o7nB9g0@7Ls4Hl6!o(y>Mu|~m)2W74IlS17tKks6jSC0|L=mic0O%4Lh9t(*@jaAC3lv>1P;`Sp(TxH{HwhHoEKqcdK+&xNMYjnQ-7Zjchd|Mt0!4QTHAUy- z3vXsX%6-!9*SVo+yQJvud@1=#itf)B(@O@lD0;y8Q1qZ3iXO5<(ZhBqdc+PzkJ_Q= zF*_7JZik{L>`?TiP0>>VMNbP9JtI)`tU%Fo0!7aY6ulr&^rAq~0)e8J1d3i3D0)Sp z=v9HD*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui?>nxcF2h3?s(!-Y1e%C-n1xM#raUQsvU}Y z+o7nB9g0@7Ls4Hl6!o)1QGYuW4X{Je>NZ7d2owzzC>kVCw5CAOS^`Cb1&Y=dC|XCL zXkCG#Ap%9~2^0+#C|X~jXaj+w4F!re5-8eOplB0;qD=*gh6xmHCQ!7wP*b#GU13oM zq}(C2Fb2O1_e!;dRCIl1VL!wsAfbZEJ_35q2or&JIP}+o5O&I~0wy zL(z_QDB8&mMLXLRjS?u@MWAR`fuhj@MY{JK+!mXqVWPndk7TmDNr;) zplC0FqKN`UdkYlpBT%%jK+%2zMUw=ICJPkpFVqxmRaaO&15zH5u0>miqRrArv?+C^ z#Qq3Ciu6kTCcbfrMiRRTp<3lv==P;{+8(RBhv z^972o7bvqL>G=%K`JrgNbS=8Cu9SQwMGw^#(@XxfD0=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuawEnxY5l3Joh|iato6b$l=s z4Ni})KdLJwUrEttb;b0Oku8cocRmz-VTYnG?NIcU9g4oTL(w;OC|YQTqHpa`^qn1w zzPBk_BvAB&K+%r^ML!7?{VY)Qi$Kw@0!64rY}3q3l!A}6cq%D>II65LQT;pb%iZ6Am!cCwdm7Ov?z^M zg;MgB6g3u#=_N;76qTJ1MQ!X*)MSUEW;+zMwL?+G4n%L)|r5GYzsps1%n z(eeUCy#$I@5GYzvs3~eF6wbRl+Nm#l43)W`Wy zw3;1?`r4tWpB;+&+o5QH9g0@BL(v*`C>m&oqCqxAYYG&tB~Ub2plEG@qICp{))gok zB2cuRK+#ZvqV)xeHV`P(XKW{qXmj~6DS%ZP_(;1(O7|^aRNo-1&a0%DB4q?Xo5h|UIIlE z1&a0-DB4G$XkUS%{RE082^38hDB543Xo^75RDq&tLQT;&g~C$(GesX~U$a=hZ76yw zeIk2$p_F_jMF$s(=_RvU6dmGxC_2;*MKkPBbeJ8A4!1+m5q2n=X@{aC?ND@-9g2>& zDLO`==vaZG;{=M17brSGpy)(_qLT!QP8KMdB~WyVK+&lJMW+cAoi0!`TcGF+fub`7 zip~-!I$NOV9D$;91&Zbf6rCs36dhP7?2!Q}4@%dfgF;c?^bzg+LMi!5iY_V?(@UT^t?^c3j#$i3KT66D0)et=w*STR|JY)6)1X5py+jhqBjJJ z-V`W$OQ7g&fueT=iry6{dQYI}eSxA61d2WsDEdgC=wpGRPlTGHhYN)tGa%&|>9dZH zgrcR=wdm7ADfvo@zAO~ew|r<(^p*3W=xaL^ePf5Bg?1?V)(%DA*`errI}|OlL(va* zDEiT+=qG`qp9PA35h(gqpy)S&qTdCI{tzhoQ=sTCfug?!ivAHO`d6UnKY^lLecZNF zlou$f6DTSO6x9n96$Oe~2^5tCiW-EPqR$J3ff~RqasJ&JIQG?NHRg4n-a9P}Io|MV)Pmx(F0?6)0LvplES{ zqHY33O9&Ko7bsd%plB(9qNN3jmJujgR-mYdK+$pnMLh+ImKP}MB~Y}2K+%cr2U3Qq;G;n7-vqi=uwchob&=C>mgg zqSftCw1ypu2HK%$kR6KFv_sKab|@NbQ?#}~(K-S}>k1SN5hz+uplGN-(fR^K8weC_ zC{VPKK+(nmMVkl|Z7NVSOrU5pfuhX?inb6a+ESosD}kb|1&W3X6m28a6!obuJeC0| zADzwm)k4v`=~}dHeJS}$igu_krf*r)qG+V^p=d`t6zyb(qMhwfG|CP|yV#*04g4C_2pfP;|H*ijJ^D(M&rO9chQ6qwG+0v>l3$u|v_Zb|^Z|rs#Nqq7wv) zP829QNucOtfudOgMW+Z9ohndtnn2O%0!6b0ip~%yI#ZzNEP+b}3lv=-P&8MlDLSOSuyqEcTu5JceP}59D1Dj8h4rQ6D=C^+UrgUJtwqtL&WEDQ z>`-*M9g427L(!FXD7wlHMOWLQ=o&i|U2BJ;>uieV3lv>1P;`Sp(TxH{HwhHoEKqcd zK+&xNMYjnQ-7Zjchd|Mt0!4QT6x}UQbdNyMy#ht|2^8HgQ1pO6(Srg-4+#`KEYuWT zTwgdR15$3AZp$tSMf<0ZXphvFlCPxbiTYytmU}IVo^(DGJ!OZYr|nSmj2()ewL{T! zb|`w@4n;56q3A_B6fLkRdP$(@Wr3ns1d3i2D0)qx=yidjHw22_6exO2py+LZqIU#} z-W4c%PoU_1fuautiar!5`bePYV}YVi1d2WtDEdsG=yRc_=&}03yBU!3iRpvbfucVJivAKP`dgsrAAzEO1&aO?D9RP%wwP$El{+KK+&=SMLh(HmJ=xIDNwY$Kv6G&q7?*+Rum{&NuX$DfudCeidGdU>Mc;z zN2n=kE*2(aK+5SA?CaYWYj^qs(}iiZVk!AbiUt&m>08FOC|ce5P_%{}iU!)DXpkL> z*0e*>T6QQJY=@$??NGFi9g5bqDH7lpTt8u|v_Wb|@Nchoar=P&CF4MZ4RfXsjKI z#@Q5&7bx08plDBlq6q>;dkGXx6e!wTplBa~qJ0I5_7fCs1_0K+y#PMRNs;E)*!b zNTBFqp{D4tVqwh;NO@$sEjv6Ey^yX&mlR9MS5kC&v6#N)d5fYeoDW4;+M(zwI}}}Q zhoWojP;{*wimtOm(R@1;U2lh?8*GYh6ezk$py+0SqFV%tZWSoHO`zy@fucJEitZFB zx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^96exN~py*+NqDKUZ9u+8hOsFZkv{;y#0V(g5 zzV7<6Q1oQ>bM=oGOUYMK^mMT}Z>Lc7jPs%BSvwRxXNRKa?NIcB9g1GGL(u{|6uo4J zqL=MZ^omW_81d8efii!e7tptin0!0l1MXd#j8U>2V z0!3{Eikbw9nuVI8g~dXfT{1=K&t2=k4MlIJ+y1t#O37DJ)V@`5mC>Q7gY%)NqaBJm z*`cVj9g4cxp{T1JiWaj&(c*R}>Sl+cC2Wei3luFWP_&dl(b57%%Lo)LD^S!!plCUP zqMiap%L^3s5-3_hplC&bqLl=SRu(8)MWAR^fui05MSTQ{Rud@dD^S!=s41$pDr}Ph zDPNu*UAJphyVGw>xBdNFm6ETdXke@2)G?uGkn^EvO*<5=Wrw1{b|_lg4n^zOp=ez@ z6b-RM(Ry|$8fsItzCh6i0!14N6m29>w6Q?ZCIUs93KR_!DB4V*Xmf$0Ed+|T6e!wC zplEA>qTvEX+XxhGD^N5-plCaRqU{BWb`U5UDby6L-l{Ms15$n=JuX@!6y2KsXm-a| zrQ|Cq+ND+T?y;e0SLZ{~Xgd_`W{09Nb|~824nx)K(qJz>$w8LAKlCPxbs8+@Q#)qP#oexFF z*rDiHI}{yfhoa-{P;`PFicYjc(MfhFI@u0Ivuuh^5hyxUpy)J#qSFP6W(yRZAy9Ot zK+#zOMP~~Xog+|mu0YWofui#Siq01(x+Mi< zgB^-)v_sKNb||{prsx)dqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&ZzyD7s&u z=mCME2L*~A5-56Dpy&~SqDKXa9up{fT%hO)fubjcnxZRO6((jt%0H*e&y}HQzcij| zRZ6~+qUTx_Po5Zxo_9VJyQQ1qG|ie9%VdPAV- zO@X4f1d84kD0)Yr=v{%L_XLXG7byBbpy)$^qK^cMJ{BnYM4;$Xfuhd@iar-8`a+=S zOM#-V1d6^EDEdaAXrWM3^h~S5O&O5#gXtsMv!Q71bld-Jt5Win6#dYu_|iV1=tt*6 z(NA_L`q>Uezu2MZS34B_W{0BR?NIcG9g6<6L(yM0MSlwv{UcEHuRzg%0!6t}+_qDc z7bvO|C@KgP)e96A1&Ue;6qN*u8U%`33lud96qN;v+6WXi2^2L86txv7st6QSg_@%8 zTNQrIfRrCkm!CzU=#up4x?QQ1d?iJlO2y8TLQ!YuLs1ty6m_*j(PDNeTHFpr-Rw}b zgdK{y+o5PlI}|NtQ?#@|(J}%>%L)|r5GYzsps1%n(eeUCy#$I@5GYzvplBt5qLl@T zRuL##RiLQ1Kv5roqSXY7`U({F6DaC0P&7cGXmz2cs6(kRI0I5%G2Q8REYt zHA$tw7NTfuijMinbRh z+CiXbq(IS*0!2Fs6zwe36b&jBj>>?P-_K_KnxW{NbS)ZHDkWb@(Qc*UWm7}Z80SOL z?sg~|Ylot7b|@NehoU{~P_(BViYC~hXfHbyO|&W6TcBtkfuel{iuMyInj}y(S)gct zfubn_MNqJspA4i+dnM4;$Ufub1#MTZF#9WGFGgh0_up{8ip zQsJo#NV!|OEgKz*dZrI=N0v&-S5kCrsrc3OP;{L0q3C!!6rEs)q7&^h6unp~PCq0REpR>* zy<~@?m+esWiXDnxwL{Tsb|`w?4n=R+q3BIJ6uo6r^tM3JI|4=T3KYF3Q1re)(FX!W z9|{zGBvACRK+z`xMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&Zq1&Y2EDEdyI=zF22 z==oCN{0vBW=k!qMg-~=^x)v=em6ETd=;u=L-Wj3j7w1FKuXZT<%??Gs+o9+WI~4tC zhoZmiQ1rJQivF=f(Z4oD{|OZ38sfH{qP##+oj_4Rpr~G;s3=g>N}#ADP}Cq$)LNjZ zQJ|P7PmuDH#-z9VTYpbb|_lX4n<4Zp=fD46fI+iqGfH0dI%IP zCs5Q=plEr4qFw?;D+m;=C{VPLK+(zqMXLxDttwE|TcD_qK+$RfMSTT|`Uw>E7bqGa zP_(*0(Ha6p0|kl(2{lEX8wx!$Am#JZpMZ2}sNLyzOCQnJY$zpPNzpnD#f^^)Me8~r ziiX&sXgxa=4Yfnj`gSPVzz#(l+M#G8I}~kfhoVhviZ&G}8YWP*nLyFz0!3R06m2O` zw3R^7)&fPt1&X#2DB4z_XoNt~b^=A)3l!}jP&87YXh(sfodk+@7AP7eP_&Cc(XK*G z(cp%{J{gem&;)1gP;_{@7L9HwC0|L=*oNXMM~9+u&WED$b|~7z4n=#~p=g2~iuSTY z(L_5G?QMsmee6)QuT9Z@0!5PqiY5yb?JrO?MWAS^K+!aTqUi!f2M81$C{T2eK+(Yh zMTZC!9V$>XL!js|fuh3&ijEK{nki6pq(IS80!2p)HAQ0@3b$lH%8Sxx9d{2!?GmYD z8cNAmQglK?@s(pk(TUE7qLb`Ubg~_aX4#?W6gw21YKNlJ>`-*N9g1e#q38^oqB8}G z&Jrj(TcGG1fueH-islFuohMLqzCh6h0!4ELiY^o=x=5htVu7Md1d8Sf6kRG%beTZW zP<3mw7J-WW8p_F_jMb|eJyPgn=Zg4&n z-DroRo9s|@vmJ_Vu|v_Vb||{d4n?=yq38}f6y0f4beBNU-2z4T2o&8bP;{R_(ftBN z4+s=JC{Xl}K+(ejMUMy+Jt|Q2m_X6v0!2><6g??W^prr+(*i}$2oyalQ1qNY(epx0 z(RB@lbuu93EwfoaKNS6&Zu?(oC?#J>(aR0R(I`?Tk z9g5zvL($uID0;^ZMeo`ay(dugzCh6j0!1GR6n!L6^szwECjv#E3KV@NQ1rP#(H8MGFOrz7;6?PN3*}fucnMML!4>{V3EFEodkllL5&tJ{g>sLeY=u z6WKpCl#;Kc=(mRA6|+Lo@6Ly!KkQKSryYv^vP03|b}0JC4n_akq3Az56y;jSeS0X% z+Z5Fa6cq%D>II650!6I^ib?`S4FW~21&SI4ipl~-Z3K#%1d5skirNYkRRoHv0!8fv zirNblbr2}(C{WZ%ps2G@Q}jzi;h79bdGGXq`qxnObGjCFX;{i{G3Yik5Ib z6m_>l(UNv3TFMSZOWUDn89Nj$Ylos9b|_lT4n;j}ik25B>LpOLfrW~C|chRMH|?mXhS;`ZDfa{ zjqOmhi5-eIwL{S`I}~kZQ?$82(G~(lTM86yB~Y}rK+$l4qHP3`=6?9g6m|L(wEV6iv1% z+Fzh(ia^m+fud;wMbia}4iG3hP@w1_fue&2iVhJdI#i%&hCtC_0!4=l6dfT@G*h7H zNP(iG1d5IpC^|-<=vaZGGCr^6#boEi2wN3rQ|CqI=OZ6{DK+*F8MK1^xy(mz$K&UCYp>?5G2Bdsa`b6W6 zp{QLk8!xpkC0|L=Ypsi$o*#-{cRm!oVTYnO?NIcV9g5zzL(w~SD0E`~`Q1oa+HhyhgO1_e!KU)`1 zn;VM$ay}IOZHJ`?Tt9g6<5Ls70V?%YFB-VQ}|b|@;?p{U-bs3=g>N}#ADP}Cq$ z)LNjZQJ|Mc;zN1$jmfugj)IBE7TM%(OCF115$o7U4FVZ z*6#H0N@GZ4Dfvo@HfSs^J}(q)=zJ*J$PPst+o5O^I}~kdhoWJ2DB8>pMVs59XbU?O zZD~`ql|a$f0!70Ginb9b+E$=wgh0`D0!7;k6zw2TG*X~wM}eZ91d4VRC>kYDw2MH| zt^!4)1&VePC>kSBw7WpjSb?H(LQT=o#=?*cNIAVyQT_U%=$bUfH``V#sKRXmnvP02iI~472hoUKVD4J?hG)EGB`O1_e!TN{htUKNUNb3PQ^Zik{f>`-*49g6Ob2^2jpQ1paA(USs2PYDz~El~7~K+&@TMb8No zJugu7fEx25A0C%p&g1ovP03wHbtKZ6n!dC^qD}>=K@7v z2o!xOQ1q2R(bob+-v|^f6e#*upy)e+qVENY76}ynAW-z9K+#VEML!D^{UT8Gt3c6j z0!6FBLidqX4H3}4!1&Z1T6g3GHH47BA6)36*6jcR^ z+6ff37bxl=P}EVNsFOfZXMv(F0!3W~iWUCaBrqV>zApMVs59XbU?OZE1(1t?W>=wH=Cv+Z1ghP_(T;(FlQ}?F5Rp z7bx06plGB((T)N|I|&r+EKoE`plBC?qFn`wMhg_}CQvj+plEl2qOk%+;{=Mv3l!}k zP_(B|Q?y~Zuwn+J{6qSz<3^$A`*k_4n+sp6dfo~bdW&N!2(5x2oxPEP&7lJ=rDnz!v%_t5Ga}{ zP;{g~(NO|LM++1kBT#g#K+$mmMaK&iogh$jqCn9}0!1ea6wMN9iYAr|lQSUY;f)!b zy+hHi>CyEm ziY~Aznk!Irp+M0^0!0@K6kQ@vG*6)DQh}n&1d1*fD7r$R=t_a2s|1R!7AU$#py*nG zqU!{T<_i>EFHm%YK+%l?MK=i)-7M4;omMW~kpU?`oUTQuhoW`TN3>hYrQ|Cqx}#it z`-*C9g6O=L(%Y6e#*js404@To{@GDKAKm zuHOzt{Sv9a%cbNiDay4ej=e7w<=e!ad?>23Ls7vFMfG+lD%zo_l^u#ob|`AFLs4rx z6gAoul?9602oyC56g3MJwG}9;2ozNXirNVjwHGMrAW+m%ps15TQD=doE&@ee1&S6E zC|X>gsGC615&}it1&WpwC|XLWDf+iuI3WX4{v>_D{(qsUZ}xNbOSdT{UrEt&ZHm`C z5Q=&_ABvW@Ls2g~6s=%~q805>w2~c)R<=XYDt0JZ)ec3yZHoE`6s;yu)K{RWpFmN6 zfuaEdMXL)Gtszh}P@rg#K+&24MQaHZ4HhU`TcBtifueN>9@(oMr}&TS5h>rP4WAOLeXZv z(N=aS+S(39!|hPCjU9@%wL{Seo1*OminbRh+CiXbq(IS*0!2Fs6zwcfG)kao7lEQ( z1&T%s6zwKZG)ACkcY&g@0!8BlipC2R?IBRKr$EsJfug+xiY5v*MVquKba*&ZR7{_B z+%y!W7o4fzyG<$iN{S}6DGqov6is$M6zy+^qA7MLnrerlX?7@@Zik`+>`-)|9f}UJ zL(#!DMTZC!9V$>XL!js|fuh3&ijEK{nki6pq(IS80!2p)6dfZ_bgV$paRNoh3lyCo zP;{a|(MbYDCkqtK5-2)Fpy*VAqSJ($qJ7&GcFKU12c`$q`-P%mX`J4slzb&cXSFFF z`gkZh+xbv*jvb25wL{SyI~1K~hobZCP;`MEisss(=t4UbU1U>qu|Ux!0!8x#iY^r> zx=f(xa)F{N1d6T{D7s3Z=xTwYYXpj}6)3t+plH58(e(mFHwYBnC{T2hK+(+tMYjkP z-6~LYn^049Mw`MV8Iba@^mW%~hN9=wxV=p&`AUlJZc}{t$xw8U^P%WoI~3h#hobxK zQ1pNuiXOB>(L;79de{y{kJzE;QJbR21d1LPD0)Jm=t+U1rv!?g7ASf~py*kFqUQvP zo);*3L7?bGfuaQhMK1{yy)01lia^n;0!6P06umA`^oBsun*v2|2{lD`wkdp`0V(%L zm!G>rQTOcU>fdftO1_e!_p|S3{Y)tO!1+-0p&g1ovP03wb}0J94n?2Zq3AO^6n$=o zqA%=F^rcPFR{}*}3lx1LP_$5>=v#rJ?*xjz7bsdJQ1pX9(T@T}KM555EKu}|K+&%P zMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N%zd}vXyKM?9XF$sTra#kvFBJ7kcl!UeDJ5S? zQK6~0#dD#kzUlwJ(=XbgsFfXxN_Hq}utQO6I}|nAp{Q(!qBeFYYO*P67AR^fP*f2p zstOdf6DVpgP}D)7sG~qpCxN2Q0!3W}in)dh;y5GWcbP&7!OXib5l zwFHU=3lyy_P_&Lf(YgXfLj;P}6DS%gP_({4(FOuV8wwO{Bv7=mK+z^bO;OLL!d)4V z@(Kyg@}cOzLN+#SDkWb@(H2d`w-$t=Eu9ZVTiKy#YdaJTw?ol3b|~7`4n-sEP_&&L zing~y(GE66BL#|f6e!wBplD}-qEP}xy9gBRDo`|9plCONqA>zRy9*SJ6(|}fP&8hk zXb*v+Jq3y;2o&ulP&84XXm5d{eFTd36>5q$YbyMk0Vz*U*P_isQTjAd{eDfQ0!1eX6rCtgbdo^P$pS^Q1d2`(C^}W3=rn<% z(*=rV3lyCp)D%r_Dr}GeDgU1SOn?7Sv`TuYeP&ZB`AUk;Z7Pm`EfmdhJ`|m2hobZC zP;`MEisss(=t4UbU1W!%i|tT!i5-gO*%VzWP;{9<(d7a~R|phcDNuBkK+)9#Mb`)v zT`N#@oj}oifuidLif#}nx>2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+s3|(Tsc=#T zr2I_!tm8SM=$>?^e^*l}`AUlJYbsv%Mku=9`B3zL9f}^bL(xNaD0=6g@3a^o&5!vjRoW2^2jqQ1pU8(Tf5_3j~T@5-56Epy(BW zqE`iqUK1#KU7+XN_jK+#eHMN115EhA90tUyr@fuiLEih2q)MfJ^v zQ5lf(wFyqKxpt?YJ<`r@*qTepS5mZ6bMdhEL($64hoV*NP_(KYihA3jsE-|rR`=759g23aL(xb(6zyn-qMdAtb`~fa zB~Y}BK+&!OMWY3Zb`vNXBT%%vK+#x%qHzL6;{}TL5GdMHplE_X(Ov>Y69tO)7AV?B zplDx#qWuJlCJ7Wx7HW#NY%YA60V#J*_h?&%qHWWo>;0Qc$yZV|y}8)>lTdVk^P%WK zI}{ychoXb+P;`hLiVn3y(F{8j9cG83!|hOXgiX;*fubV?ijEQ}I$EIU7=fZ=1&WRn zC^}xC=mdeH69tM+5-2)ZplFsr(J2B&rwSCECQx*`K+$Z0qB8`F&J-v*OQ7g%p{8hR zb79pCNcpIAEt(dJK2DFW&uK0tUrEvV&Bd)g3q=<=AByJMq3A+86kTM8qKoZNbcr2` z=Gmd>Qacn~W{0B7ZHlfCD7sRh=qiDts|AX#5h%J=py)b*qWJ?dS3l!ZW)D+EWE=Oy_vpz_QU2<@|6^Q+FX3+t5Ecr z^P%W-I~09khoUd-Q1q1@ioUi((KmJ|T4;x&Z|zX@olVjA0!51iihd9%`ca_hCxN1$ z1&V$VDEd{P=r@6)-vx^P5GeXnpy)4wqQ3=-{t+npSD@%Wfuda7xNWB>FHlq`P*e~o zsuyaCK5j1LzRncgn&5mAil!z~#kQs7D=BK-wz%}dP}JyrC@R~bsEr+pn(R>2Y=@$@ zb||XYp{QzyqIPyDYHw52L7=FkKv5@wqRs+ET?C4{3KT6SP_(!}Q8$62B?OAP3luFW zP_&dl(b57%%Lo)LD^S!!plCUPqMiap%L^3s5-3_hs3|J7Eo_tlDbGp|g&Nw{?(|Pd zq*iQOO1_e!RofQ#{4Nyrc0LsKu|v^nb|~s=hoXLVDC%#Aq5*a&THOvsYuKS^piR*r zfuc19iq;Y+8Z1z>wm{K30!8Zz6b%t5T2G*8s6f&B0!14L6m2L_w2?s3#sWo~2o!B9 zP&7=SXfuJL%>|0K5GdMGs3}^xZDCdhq`blWQU@i?NBtz4n@1z6zwWdG+Ll&H-Vxt0!6zE6pa-q z8YfURUZ7|XfucPHiY5pY?Iln&QJ`pVfuel`iuM&K+E1Wpl0ea9fuj8dilzt@O%-a2 zhPN%eoB=6MNT0jjCKN55u0_+@mXfce=%BX6pMDHQ2Rk2%4zWYgp>`;mVTYo_>`-*L z9g2>yL(xn-6dh@YqN8kzjut37Mxf|efuiFCijEg3Izgc5M1i7{1d2`;D4Hcubc#UH zsRBi(2^5_!P&8Yh=nR3PGX;vy5-2)bpy(WdqH_g`<_I-K2ed78`6*NMdirDh14GeI z=?~S;Yg`-*29g429 zDY{yq=o*2dYXyp~6DXQ5P;|XO(G3DcHwqNpBv5p-K+!D%MYjqR-6l|UyFk$$0!4QU z6x}6Ibhkj!Jpx7d3KZQZP;|dgQ*=Sw!mb&Ra{qKKnj4D7r;lh4v@IoHNzo&1i%0wx ziXL@76g_5#qQ~t}^n@LXp0q>JQ+6nN+73m}*rDiII}|-MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zW2r4+M%n6e#*g zpy*?vrs$!zh08M_N}#AD)D(Tzw(xZZq&z!) z5c@n7?Ub%X4V6;zl@zt96w7~yq9*4P}EhRXfc7J#RZDG2^1|MP}E(ZXi0&hr38wW7ARUqplDfvq8|6b-aP(I7h%t!am%wQPz83lyy_P_&Lf(YgXf zLj;P}6DS%gP_({4(FOuV8wwO{Bv7=mK+z@wMVkr~4HGEZOrU6Ufub!0inbIe+Df2k zYk{KSLQPTcO5uPENO@?w7WD~5U#785rIdUnMcY@3=jPIH&?i^FgY%(iq#cTOv_sKO zb|~7}4n?EvP_&C3igvX_(P%pq?PgOnMxbbSfugYjMdJjD#tRhfAyBlZK+yz&qP+x) zCJGeoEl{+NK+(PeMf(X9O%f=YEKsz+K+zO|qNxH!(*%m93ltq7)D(@V6zjaAC3lv>1 zP;`Sp(TxH{HwhHoEKqcdK+&xNMYjnQ-7Zjchd|Mt0!4QT6x}UQbdNyMy#ht|2^8Hg zQ1pO6(Srg-4+%9z7gY+IWI)PY(&gvkP;^T^t>I4Ua&*ai#A0I1d3h~D0*3-=oNvYR|Se*6DWFJpy&;O zqBjMK-V!K!TcGG2fueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6KaYctrSkp zfRsC?YtdsArAODFS4zoOQuKADcw_5O^o{eOXrUd7zO_TqcXlZH-VQ~J>`?TB9g2Rm zL(xxmDEir^=of*aUj>SO6Day!py&^QqCW+S{t_tqTcGG4fuer}ivANQ%2ngGoua%z zQJp|hL7=E!pr|NN)JmYJBv8~KP}EwWs8OgX`m$1ZH3L$fl+F6DLeWO)PQP3&C0|KV z+iLNbaww`eABw7WC~9YiqV{$u>R^YWj&>;OWQU^8b|~s%hoY`FMT-d(EiO>hO`vEA zfuimLMN0}4EhSL2v_R1^0!7OT6!j1&T27#-r$Ev20!6(9idGOPT2Y{AC4r)q1&US? zC|XsZsJBp4)Ko1j)+ST5Abr-cxmvr^pOdadeX6D8D=F$PoQY1K+*aFMH>hdZ75K*kwDSL z0!5n$6m2R{G)$mqGl8Pb1&X#1DB4n>Xe)uDtp$pP3lwc5P_(T;(FmcYsBg8fTLz^3 zXL=~qFBDBokFK|?mXfceXvb>t$Vw>M$@x&UvmJ^?*`a6`I~46|hoaGTDB8^qMPuwx zw7VUO#@ZB(6DS%lP_&0Y(VhZD69kI(5-6G|P_(x|(LMr2`wA58Cr~s=plGr{(f$HO zQv`~p3KUHfD4H%%bbvt7fdWMb2^1YH)D-PdEnJxaDc_&2MI%Ge8|hP!hg3_+S5kC% zwfJPaP;`Xzp=hQZijK5H(NT6NI@%6J$Jn9hSUVIQXNRKW?ND@rP0@)0MJEXqoh(o^ zOQ7f!fud6dicS+KI$fY>wm{Jt0!3#E6rCkdbhbdzIRZuJ3KY!|C^}D|=zM{q3j~Vh z3KU%^P;`+{Q#7MmSeOARPfwSh!$Q%^X+^P%VpI}}}MhoY#0!23p6x}3HbhALwEdoWi3KZQYP;|RM(H#Os zcM25UB~Wy?K+!z{MfVC6-6v3Vzd+Fg0!0rB6g?zR^sqqDBLYQ_3N=OZs)fE8kn)o0 ztM@MrMbD*c(PPz8@|6@lRV{AYITStZd? z9|;tFEKu}`K+&fHMV|>2eJ)V+g+S4lLQT;V)xtp;kn&sUPXEbJ^k?>S^$yZYJ zZMAq_*HHAG^P%W_I}|OlL(va*DEiS3ML*f0=w~|={bGlrU+qxzn@!R00!4oa6#Xes z^p`-<-vUMd2o(J*Q1qWbQLbIwwo{ZBD5?`EDhL$S3ltRvidqR2l>~|!1d3V<6g3JI zl?9602oyC5HAUZ43lC&K%EfdoS{RB(r;ljO?Mlg4Qq-N_jK+#eHMN115EhA90tUyr@fuiLE zih2qZEiX{iOQ2{4fua=!idGURT3MiI6@j8v1&VqL6!j4(T1}v+uTWD|X;-N4mMJf#|}m7 z+M#HO9g5boDHP&C#KMdR#HG~NzHd)O51DNr;) zplC0FqKN`UdkYlpBT%%jK+%2zMUw=ICJPkpFHkf^plGT<(KLag=>kOu2oxPCP;`($ z(ZK>mhX@oMDo`{-s43d1UE%Z$NO`;Tb=NzGqQldNx5L_%lCPxb$ack>mkC8jIUkCS zwnNb|b|^a54n@b=q3C!!6rEs)q7&^U^~<(ix@SIDxjy?N+g#LTxAB*L3D_7QC zBA4q^Id;ihu7Bm(rE|G~m1>V%Zg6FXp1ItR%7wjhxeY3xteDGfQdwb@TyFEqq~5vQ z)|J~=%jHH?{_2;@jjXJrEG-zt|op>pEzTy9q7#cgxB(<>df z&*jdl>^w4;n^T#$Q!Y2R^2MlJ?vlzXqjR~-D^thha#vUG9-GU}ulzSYm%FL5;e=f7 zw#vy9bGf@JFYS}d-B;;6DVKYwvdjLt++&r?rsi@_Rlb^@%RN`=oqbD;1(oTC`ZWJwJOFT4He?}U7H z@p;*MAzvMHS@v$oSFgGvdq3o>>ATtY$XC<1Bkz^3rtc@ca=x0rA#k63HGN0d{`qS9 zmYf6g)$~0T2j{Elo8k@0SJQVj+aO;}-&xzwucj9Wot&?xS9qM3ucnviJ1AdG zudy~GUrjHPH8WpLuX1!uzWV5g*?TBoO|LUDD_>176mfdKnx5%@R=%2^sy!!PP0zKR zo3ExPOJ0(%rf0idp0B2-D_xzhrstc?&sWnE25!n%(^q`omanES*}W@YO4~`e)tLabvUd>n2AKko}ucptvznib7Po935 zucps_eVVVPPhWhQucrIYh52f_fmoEUrbmE3=d0;M`0x2@x(5H9&$at9`#(+n<+cCI zwQne7@63K#$^J`cf9L0Rc%r2&aay)oa`w*-&$hHxvUgoB)1K>}{oQdwDf{IEn$xe# zbAMjD^`XAiqwG`Hk6FH^v_64H;4!*^jFE<(k`<3(bo+Z`Zk+uXN7k>U!kL z<#n=@%N0813e9Vl*D4PxZ`wZl-z0vfA(tx-$feS%ZT4%^4@&Lx<#O#;=Cj$*lq)ni zSS~k}+mr`p|IJ!={{MbeWA>~5=eIA%EY|*QZQ{4gX8J9g;+X%wi!oJUddC|Eswvm(Tvnep!;W>Z-k`jOo3{)XBZ4P8r*K z%IK+M$B&*oWzw|qW2cQD*L&=ggC|d$l)~8Y<)#XN(#@x$E@FlP8QEH+=l0X#I(e7$F`w3Tiz&mW z?mBqJq+vtTuVw6}6J|^swt2taLwfz+xSDn!K7DllXw}sfSM-<}lSX#y-M!1mOkvol z(PM_sm@s|V^u4Bxp4Met7M8BAQR62~Pa_H1V!)tb>0*u?FnQv{$&*sc_|naGxkjC!I>| zy3|H}tEJ1;6w~F(7oa{}fZEKzsP462Onuk#+?~tyOE$DlztJ`ywC=FM-PWti$L2oW z)*CjWc(!-X+0XVGF#Flwed0BH_R;z|xm(ZTWrGI9>oliV9>3A#$y1u^hVD7h}OK11!KCE~P&FP&vVX(K>FWy@JmbZ{T0_oL8 z&6qfGui`Dm>-O}H`$brF_60~E(AjT!_B-k6eGF{*V5AR0ykfe@#fLGymExH>F2br# zO&`443)2TS&g(V%jit-uopz7c@6mEO2FyOAd4PA7E_j@g1=XR(bAP&y!z~43sv1(ekpxtU+m@twr;~g+YakDaP!)E>3WP` zQSzFf8E-WXi7`4m|5@47*? zvv|bO49a?*(ek~VnV7jLJZN6@E{-57q6!e+>Hkw<^F@i{Q z3&M2q<9&iLn?Sl1sJ-Xr7E#TKRMEP5VGFY6!LFeeTlq@+zxfG0?hmwln#do|^r0y( zlxOl)U%Pp0;gfFh;@8=nexaUiZuvORfoRn@-Bnxo%x|zy%axF>qT+pY_s&{?HHWZ# z3p)p@biEg+wD585HusMYY`$*ud+Iy;@}?^GoFSn;ABvp9 z4Vry+x(4Dcwp;?&ary|w%VuAf=_)ARLyL`cyOdt5_Qq>3O4n_il|F^UbF+UT$z5@N zx)rWVcR;5WAC>0f5Wl@!G&Hwxm@TkHLHg93-u|?4lc!Ff{n;>Kb18}|efIS|`}21C zZBl!ce4W$;rH@AO%p3$-uJY!V>%6(;N_UMkrwdy@=Wn-%j~Hdza=; z`CfasKHYnET4Czw38RNk8@*zu&J#yYnX%@`^pP9AXXlAMdZaLY+>D7M(s9g$$-}32 zPIvj&OjpmS9MWr!nX-GY&eNuJ9@X4CmEluIj$1Q52H3q%=ZRe=rbiJgkD4}Rm)ZTk4h zlR8gJcfZqdT56+)Pai&e7axjrAE0=qg>G|;-OTd;^tr3xImc()+4n1w;o945xi6Si z=8tj9UBZ?-g3Sf=nwWHx9~Z0T$|$tY{^VK1J#5(j{5Bh| zYafDqw=?dE)_$qQZ^PNYe825xqh>na{oHl-EunjvE%yXl?g-L7`>LOPKXdjS$l3Q5 z=lE^Z@|&UMo}O#E<$m7mYp}SpShwzg0jqUdA^*ndH+5pCK@&%e9yKc6$sX!)a_#q$ z$G@Qz<>PoNJDqzs@ml+S6yZ{Lr)IsZ^J~ z1T@D}sV;p5ZH}i>UHaPA98aaX^rf>oo=UZkT1zO^)jmA4L#eLg?C0|{rMkKQ*Z!ZE zwv;Yy`npo>S3NTw=gtq6|Mx@gWv16HGwOfcFHWzUzxLRWzp$T=>0;!!oR9OxF?|iI zt|7f}$$U&-^j{%*zW(y-rLWD`j_E7%wPXJ{ZW_leKM%+8&Gbvl`_nl7m3{$vSJG9GkBg;WOFpg`$FFThA@7NC zysSg9Z;sw2o{zn|UCkT139mhS>7t8WKG>-Qr@OeKS$Hqm9Jy#qzNZp>azv9?4eG?_Wyk8vm zPFGakhsW`O=3+k^$5uUyJx?4rN>^xp{cYoTQu;!4-si{hjn#_%X&e_%SA2f?%5faE zcCmMh<5m5NeR~{#7*Ong;@Ep|u?NI)-}Q=pWE>ybpxDpHvGtH*&lksyH!1e^aXe+S zVqX}?x3(zu=W*<`Rk1tAam+Two)*Vzwk!6Xar|kAV*eM%KEsMVD31FNFZR)Kd?Z27 zACDK~*fgft3&e5LamC&-j;HNX?2F_0&V*ur8ONn27rSd5$L&_^8F9RBTCwkr<1aIc zUB7#ATy4+dxNaP0?p^F-% z6uUW&yBt;QJ>q!7F~z<&j=vpO?9%bYag7s;9H+cm?ET_++v~-CIF5h6S?o4%703SX6vs{Cc*J|fJ~fWdeNgPT z<2dif#a=Rw+kIN>v2ncM^I~5c$Irej_Rn!#<(p#njpNksihV#F@A#qEkH+!e^bN@T z`@Q;eaUA$-aojA9NBv&x)8qKUAH{w*j`ROr?4{$l!@tEIAIFQ*XZ8H{uaDyw>HC*? z{~E_G=_}%SuO7$g={uTv9~j5G(ziDAemsup+sC!tE{=oKH#_sow}|60>ARkJpBcxO z(zieJem{;2rtgF1y=)wJO5YI8d)GK#lD;#V_lCYnM-8GKA^Rb*hzs24tADhy*r{lO~^qpgmisSg`yT|e1IGzy4 zbK`hb9B<9X^mgxz<9*Sej^i6~{4|a~#qqy5w#xTk(&bEVqIR4sj`PKF@i;CO$3Agf zBaQ>&xNaQNr<>Z_85zf226#4o!0U_`E|lRTkUDd^#A;NrDE2;S0B&T4*6yIY5DYDx*GmJzTPV7b^iDJotc`ae7)tTf$2YQ zJMUZ4f9;lUDV|#=^>i1wE+6yLzN^>QZIeRwm#+5OH`DUv+BE&=ob+tngXwJzog;X5 z#Q%D|`Btp2J35~bPhM}QwC8-kuMDiOo0(dEzxn;;Uq?Rfmi}{2dbaL@^!7UCXX44r zCZ;{-+Z#G4{n@0{^4rV5x4gYW((}$q&(=MV-d=t^PhK`Ng*o5es5#zV+w?MT@3i#1 zbJDYQFQm7(k1KnQmz|WJpY!caPj4^(`ts#VH(Rsc-bLy8{Pwz~|MJs@o$KqC&+jmv z^2_pn*T&K7P3>D>w?Vv4K6t(K>HmLRzI)Q^Wka6wuOmO*mj0Xb^6fjvuQxxc^y_^* zJ)eGgQ_`XK^hJ7ms~PE--*0}(N52R1US_rW^hb))pJ7PPdwcogp5NyjAFjHg$=|Z6 zdGhx1?c$uTcTBo`>8`-+C$Bf>!`U8PCU;HWx9HucTlYTQdvr=)o#@s)$Nzix?%AnR zpPs#XrbBw#x#@sG8x1c02tx5@>(irHZ#S2jgKMi?{9a!n-4-rT*X`B;zYU+U$uCnz zExN&?8$L9vakGbJ-LTF>vo7gY_v1RHGx{(6Qr(Y@?WYaud4K)V9ha{EdS=_YuMe(E z$NHCMH8$6+{MTFW%&P0w_Q#HGADUIyyu+-vYaBDEc&_yt#j&w={QSkn4dxklcKzS4 zZ1T$kTf98H+r4%7*L9qKoy(tmp{`B(y;xk2jrG4KRBhKtAE};me)Q9YZ>VpzV}5K~ z-+D^={m{@*{-}}zMSr^=XZThdXudh z^Qbg7E?3TfXs~tuo5_}spEg+{&E~qs6=E))X7{?r6=N=zW{>o@;m2Gw&7O6QE5}?U z&0ckltHfM5&EDxR)Qh=Lnyc0|c8R%QntkdTyT)7~&A#bp@?*}QW^=k&&9UdpJ6*2s zvFFV@U9cXp=gB)=vYxT$&O2SSUa{xOJ6*Qku{-9SF5IfIJLH`%U7y(P^G+A9Z|rt? zr^~lm?6zrlPnU1?*wwt#GG`|yOMXheCxz+m3O*) z{bHB%PM5EL?8dy)(5cvP*12c8y&KS-vU6LLcALdc}jJn1H*>B#iy zu5of9py_9*<4P6R`<-GBzPk#U|wG*n~V2n~-N?6Y^YaLY|LJ$P2Lvc`-I2 zFU2P0<=BM05}S}$V-xaPY(id-O~@Ou33)R%A#cSlgxpcuI$i%w-{kuqcNRjr=ldjY zSF)Te$Ff@_Eb<@MNN} z{%N|#`f~p9rrOVBmh0o}_-VRUcKkG5#g3n*Yi-9*)3veVr|FvP_-VST9Y0Oi){dX1 zYiGw#)3vw#G+hV5Pt$c2{50KMf}f_FTkz9#^9X*LZeGDp)6FONX}b9ZKTWrQ;HT*p z6#O*ZLV};BTUhYZbc+annr>0SPtz?X_-VSu1wT!-cApf8<(xGWL{a(iuL9E<8d`bD>*+Dt!#&) zRqRmI*$zcr>`>Iz4n^JUP}FRPqV9Gm>S0sVQ=q7qKv8djqE!Wo`Un*D6)0LwplEf0 zqBR7H))XjOOQ2|NfueN;iuwr@^%p1_AW$?=plFal(O`k1bp?vn6DV3=C=@MUUuu=U zZdN@c-xRG7itfpzHmI*;Us=({_2vBIl{H11I6o9^YKNlD>`=719g4QFL(xz>6m4mT zqOI&uw6z_Iwy`PNR-kA*fuijNigpkv+EJirCxN120!2Fu6b%zRV+D%F2^5VNDB4A!Xjg%v2?9kE1&SsKg`$n>OB*F1)mzeR91@Ba&!i^TSF*3H zXj*+a|9Eaq(RAmBq8WB5+T9LCd)T39PdgOtWrw1@?NGFj9g6m~L(zUVMf(dB9UxFN zQ=sTTfue&1iVhYiIz*u8P=TVu1d0w9C^|x*=tzO0qXdeM7AQJKpy*hEqT>XLju$98 zL7?bFfufTHicS^^MZ49PPD((k+oea^jZ;I>5w*uz^_A=^D>|dToPWH#rsz!PhoZCW zP;|B(iq5e^(YbagI?oP8=i8y^0y`94XosSUY>F-xD7r+T=u&~A%LIxp7bv>6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACS zK+!7#MXw4Jy(Uofxr0EL@5NWw%(q4NgrXPo zz3cbtE7@08^ih2||Me0zMISpq6n$ccqEGEm^qC!sKDR^B7j`K6(hfym*`erbI~09m zQ}nGs(RTtx-wPD|AW-z9K+#VEML!D^{UT8Gt3c6j0!6b|`9Rhobg&DC%H`qKlQ4c#5^|V7#FFO?VwkcXwps0^PQD1?g)dY%G7bsdoplD5j zqO}By))pvQN1&*mKv92zq5%R$0|kl(2^0+$C|XybXgz_V^#zJH5GdMEplBnZP_$A* z>4yZQI&b<@KaDGgqEddOKcu0OePukYDG+Ll&j6l&? zfueB&MdJmEb`dDrRiJ2sK+!~jqDcZplLd;V2o&um6pA)!DD_T2szdW_(WarOfBuX% zwV{%IWktI;l=EM&Ra3Nw^Fz^|b|~7*4n=$0p=cjF6zyw=qW$bpw7(sS4zNSfOq-$u z1&R(5C^}f6=n#RTLj{Ts6DT@dpy&vJq9X;0juI$3TA=6{fudstijET~I$ogY1c9Ox z1&U4*C^}i7=oEpXQw54n6ADGs8%p~oAk`J}mxyMBqAT-l(diA9>?`koSO6Day!plFsr(H{aue+m@+B~bLYK+!(} zMgIyE{U=bA{v7hz>1s^hQBPN3{$r>00!0l1MJ0ivMuDQTP$>Gip|o)VQr$V<7JU+m ze#oO$sgiwVMNOr0{_90+imJ{JMQ!a+)Xok??d?$1!45?o?NBtA9g60*L(x2TD4N%% zXg-0W`2~s=5GYzuplBh1qJ;&D77-{~RG?@vfuh9)ik1*4>LgIKq(IS90!2#;6fGlA zw5&kUasoxm3lyy&P_&{z(Mm$0sCB7yN&-^7GXHU*Hl^Z`{=NCOXysBR`^t*Cmdg3B zr>!aK=KN69Y=@%mb|~s$hoYW#DC%X0qTY5WTGb9kee6)w*QRJSfuhv~iq;S)T2r8C zErFu71&Y=YDC#Fr)L)=zfI!hefucbIMS}&3))gpPPoQXhfuaoriZ&D|+DM>ih(OWC z0!5n$g`&=-(pw2gb$Grj)Fl*smT!wTEmg9wtY~Pdod0^`nxZY8ABwiJL($fDDB8vj zMcdk;XgfO;ZEuI79qdrFqaBKNvMCxSP_(l^(QtvH5duXc1&T%q6pa=r8Y56NR-kB{ zK+$-CqFn@vb`>a^AW$?>plFgn(PV+5DFQ{i2^38gD4HfvG+ihZZC)yM>X{UMl>W?O z;})Ul{``gP8Kp}0l@;w(D(Al*yQXMw=ZB(w>`=6?9g6m|L(%?rC_2CnMKkSCbf6uI z4zfeh!8S#Q2oxPEP;{6;(cuC`M+g)hDNuBjK+(|xMaKvf9V<|DoIug>0!1eX6rCtg zbdo^P$pS^E2o#+vP;{C=(dhz3X9yIXDHMwKD3!(}Ak}X9wrI~#)IEPjJF8U5zOth8 zO6C05tJf5r@BC17fgOr2v_sKFb||{o4n>#Pq3BXO6kTSAqRZ`2bcIdPl>$Xq2^3u| zP;`wz(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86x}XRbcaCEodQL72^8He zP;`$#(Y*pi_X&lfb4sOa5|HYAS<$(nXt6x*FIBRytmxrVIsf(iHARm&KNLM`hoZ;q zQ1rMRik`4T(UW#4dddz(PurpB89Nj`Yg6=`K+*F8MK1^xy(m!hl0ebR0!6O~6ul}? z^qN4?>jFh@2o$|3Q1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$kwDSMLZRrvQt77z zq`GhZs^deUs8hZz`lM9JzOte(O6B~|JJb|?>HJXil^u${wnNc3b}0JR4n^PDq3C-% z6#Za_q95&0^pj1|&jLli2o(J)Q1qKX(eDC9vjmF%5GeXnpy)4wqQ3=-{t+npSD@%W zfug#`c-T%+y+BceKv7Acs8OJ(EKt-+pr|5H)LJMMeO4;khGG)SOmut3qe0!8Zy6s<2%w1Gg;h5|(!2^0+xDB4({XcK{=O$CZJ6DZnT zC=_*TEIpEdR1Z$Gu{jjIlW&W*Xsl#kS<%*w<^0bR)f8>x{7|&59g4QIL(%qjDB8ge zMLXJ|XeT=q4YNbh&UPpoZc{WuplGB((I|nU(E>$d1d7HA6pa%o8ZS_^i$Kw?0!0%9 ziY5vaO%f=YEKoE>plCONqNxH!(*%m93lz-|DB4}1Xb+)Kv}I$dX<$;+D}M)Mt59@t zzAf6bv66jdMf*0E^FMD@Q?#G+L(%?rC_2CnMKkSCbf6uI4zfeh!FDJ*#12J=+M(z$ zo1()7ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%RP7x?NRiNlJ zfuhp|ip~%yI#ZzNEPwq9^T8 z^pqWnp0-2LGj=F?)(%C_*`erpI~2WOQ}m)h(MtkFFAEgCB2e_IK+$UgMXw7Ky&+Ka zra;kK0!42N6ul!*^sYeBdjdu83lx1IQ1qcd(MJMB9}5(HB2e_HK+$JHq3Dsu(mM%A zb!Pq~_Gl<@=m$F#{b+}xpX^Zd zvmJ_lu|v_XHbuV)6#XtxG)ti94}qdT1&aO>DEeEV=pTWie+7#E6DX=H$HR7t>II4# z1d2)mMU4VQWr3nr0!0;pqSgXMZ3K#%1d6Icq3FxT(o#c`qJ#2J5`7hlzRsV~+LkNX zS60-qT+aWzXHC&u&JRU%+o5P4I~2`phobrHP&B_CiWaa#(Smj;TF4GX3)>VeB2cub zK+$3XMT-j*Eg?|UNuX#+fuf}Zik22AT1KE~S%ISE1d5gyC|W_FXhngdl>~}b7ARUp zps2GzQ5S)tt^!5fghEmKa%o%wQq6yhePf4m@kqaGzF}%ESF*3Hs8_k1|9RM&qTbFA zMXTDOsE-|r`r4srH9HioZik{Z>`=6(9g5bnL($qcMe7I@^%E%SFHkfS5~xLxt#xb;hLiDoga#JutU*~b|~7(4n@Q4P_(lh ziiX>vXoMY#M%tlhluglSfub=2MPmhu#t9US7bx0AplDZtq6q>;69tMU2^38hD4HTr zw3|TDRDq&t0!7mWie?BD?JiKXhd|Mu0!4cX6zwe(inb}2en~*8=j6LW+lHbu^KH>S zwWM2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoi0#xhCtDo0!3#D z6rC+lbdEsLxdKJ!2^5_#6pHpMmsU$as@vp;W&4Ms=kjgQ1?5Wil@(o5F6V#Vyr$?< z=ZB)p>`-*M9g427L(!FXD7wlHMOWLQ=o&i|U2BJ;>uidy7bvE9u_Ei zL?{$pR4&a-K&sd0uR2~FiXKldYkag^$-c6pC(Gpvw+ls2IX@IVZHJ;~>`?Tq9g3c_ zL(%hgD0;yTMK9W+=p{Q8y=+tTia^n;0!6P06umA`^oBsun*v2|2^768Q1p&K(Ypdg z?+FyWFHrP>K+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mtmqMZF@p9?01f-h&`G~s4 zCqmJ(`7_#AO zcODjs=5>B3n$HeJ^V^|l0Xq~eXosSO>`=6@9f}sQL(!skC|b;>XmNp}B?O8(2^1|U zP_&dl(b57%%Lo)LD^RqYK+*C7MJosttte2ml0ebQ0!6C`6m=FT>LO6oRiLPwKvA`om89h!~UMFD%n?7)TdQ>+VD`+*ZHAnH9Hio zZik{Z>`=6(9g5bnL($rHC|bu3Mg8nh)ZeCPfI!hefucbIMS}&3))gpPPoQXhfuaor ziZ&D|+DM>ih(OWC0!5n$6m2R{w3$HB<^n}q2owz!DB4n>Xe)uDtp$p<5eh}UTb0g8 zK&rRr`$emUqCfHvglyZYl6_@GJGLs{IWiROP zqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIC=^}V zsT^t>I4Ua&*ai*_h_$qq#? z+o9+cI~2WYhoaYPie48edPAV-O@X4f1d84kD0)Yr=v{%L_XLXG7byBbpy)$^qK^cM zJ{BnYM4;$Xfuhd@iar-8`a+=SOM#-V1d6^EDEdYy6g}0dbVCACy+40OdpZ=YnIHCl z+p3a%Wko->D!(`(6#eAqT;1&VqI6!jD+>LpOrTPPIG zTPdxPfK*q?kM!rO6p!?0u0YXx0!8Z!6m1|-w4p%JMgm1c1d28mDB47zXj6fr z%>;@z7bx07plGN-(Ut;5TL~0xEl{+LK+(1WMcWA!Z7&px`c_H@B_P%J(rjEU6upyg zi*~3~vahUY=SunFX`yJi^Fz@HI~0wyL(wQZ6pgk+(HJ`vjkQD3I6D-Lw?ok`HbuJ% z6ipB)nkY~-NuX%5K+zO|qTK|FrV12I6DXQ4P&7lJXm^34Jp_vO6e!wDplEM_qJ0F4 z_7y1FPoQXjfuaKhie?IhqMa(GClZkAi2Sf@SSVU7e|kHxQpvuuqC+d?FK2|J!<-+A z4!1+m5q2m#(hfyO*`erYI}{ybhoWQcP;{IfijKD_Izgc5M1i7{1d2`;C^|);=v0BC z(*%l67brSIpy*72qO$~w&K4*-N1*6jfui#Siq01(xP>o~@M5NvO7@i%{Zc94y>BS` z)%l_5H#-#lZik{-b}0J84n=?3q3AC=6#Z?7qJQjA^si0Pe*#5yt>a-kMfCzj4FW|a zfucr%qOw3yD}kblKv8RfqBa6WO#($#fugnoMePKN+6xqQ5Gd*>P&Ai7(cA(>^9U5p zD-?=;s+2xRK&lh-A58l>6t&Kz=4)NazOtf)T9@k&2t^A!KNKxuhoVL8P_&pGiWav+ z(Gqqj>STwaCGAkOlpTtewkcXhplDfvqU8jNmKP{mL7-?wfufZJidGgVT1B9!vp`W7 zfugPgMco97ngxow3l#MbDC#Lt)JveKw?NUV0!4iUiuwwLq6J!)mPfEZDku zq@Vwx*T&UaSF*3HXsy=ebq@?hYdb#_tz(Cxes(D8Z-=4*b|@NXhoV7tC>m^sqIK<1 zw4P1T`T|882o!B7P_&Ui(GY>6jRlG}5h&VJplCCJqRj=0wh$;9Dp0hgK+#qLMOzCL zZ6i>$tw7Os0!7;k6zw2Tw4*@LPC}t*jn<_J2}reXhO=fUdL-W#4QpM=zOtf`t;@$A z9EwIcKNO9&L(v#J6pgh*(KtI4jkiP5E_Nu|)ec1y>`*k(rf8Bt(PV+5DFQ{i2^38g zD4HfvG+m%*hCtEo0!4cW6zwTcw3k59-U3DY2o&urP_&;w(f$HO2M83+6ev1Spy(ih zqJxD((eT!#n-Y-f5BaN(BSKM|OzM!(L(vI#C_2#&MJL%5oh(pvia^n+0!60@6rC)L5Br~MUCF+(qL*5i zhaDA)UUq&cdc_V!uiByLH9Hi&Zik{b>`?Tk9g5zvL($uID0;`H=v{%L_XLXG7byBb zpy)$^qK^cMJ{BnYM4;$Xfuhd@iar-8`a+=SOM#-V1d6^EDEdaA=v#rJ?*xjz7byBc zpy)?|qMw99(F?6hha@2B#wWpfF%*57zmWZN>q_>O75(12eCaWvXqNLs(I0jw`qK_Y zf7zkvZ#xwIV~3)D?NIce9g6DO#N+l*RBuz%AW&2iC~6caDhm{~5-6$&6txy8Y9mn8 zBv4cpC~7NE)J~wNy+Bb1fufEAMRN%h%`H$gk3iA90!8x)6wNPCw17}3`n7fGsRX2Y zW4=TETPXS^-xe*{rjmVSMT@p6e|=miTFm*OXmL9fEn$bEPIf3-(hfyS*`a7@I}|Nr zhoWWeP_&#)(eeUCD+m;=C{VPLK+(zqMXLxDbrvY<>nJZQGe%$q5*a&8fb^2L3St_Y=@$C?NGFy9g5bsL(v9yDB94bXd{85Ap%7k z3lwc4P_(H)(Pjcgn+p_eAy70_plC~hqOAmqwiYPbMxbb0fuijMinbRh+CiXbM}eZ9 z1d4_U6zwcfG+ZbYt=*=yRRU5yGv5}i6N>8dz3UNeD%n?7G^R~?kCQ{uSm%eLads#g zZ-=5?>`=6;9f~H{p=hEViYD2iXtEuOrq~qiCQvk0plF&v(R6{L83IMS3l!}kP_(B& z(Ov>YdkYlpBT%%jK+%2zMf(dB9UxFNQ=sTTfue&1iVhYiIz*u8P=TVughJ7%Hl=eC zkZRj}^D{aW{hj|J{=?f;vahV@=r-khPYp%KI6o8}Yloua>`-*P9g0q{L(z$LC_2dw zMJL;#=oC8?ooZ8bnn2O%0!3#C6rCwhbe2HT*#br92o#+wP;{O^(fI;J7YGzxC{T2f zK+(klMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)k2}@$Tp>q5|HYkG#if!MeF8={nxaq zWM5g)4Qb2^2jpQ1paA(USs2PYDz~El~7~ zK+&@TMb8NoJugu7f>0>Bu1#r$1f+UY{zBvRp{PwcjThTgvahV@)i&kz&k9AaIX@J= zZik{b>`?Tk9g5zvL($uID0;^ZMeo|7=si0Wy>C!C~7BA)Lx*dgFsP7 zfugwtislw5nn$2$UV)EAqV?=hw7wmRHn2m{hIT00$PPtA>`=6^P0=O-MVkr~Z6;8(xj@kt0!2dw zinbIe+Df2kYk{I|1d6s5DB4b-XnTR89R!MY6e!wBplFyt(ar)z!v%^)2o#MJC>kXc ziuyN|)=5CB`EM#}91x1G%wu#@CHu;X#y6FRUmS{daegS;)ec1y>`*k(4n>pfP&C;N zMN{lhw3{7@rrM!snoZGkfub1#MY{_W?IBRKr$EtO0!4cZ6zwBWw68$XegZ}N3ltq7 zP&8AZ=sYM zM>SQludL{}rt;;NhN9!0ABs+}L(z$LC_2dwMJL;#=oC8?ooa`o)9g@mx*dwnuqirI zpy(`tqO%2x&Jid&SD@%Tfui#TiY^c+x=^6#B7vfd1&S^aD7sXj=rVz#%LR(A5GcA* zpy(=rqN@dpt`R7@R-ouQp-^;8Q|Xxmq}n%sq4C&I)G0sGzrLxGePu;AH`?Tf9g04(Df(ET=o5jWPX&rT6Dayzpy&&MqAvxCz7i<SO6Day!plFs*D0;1_v`qq1?Vlf(y&j6z z&!67@XsTpiSIc?n4M<$PQ8cPKh7y{vKZY9;&1ik7OD@4qe- zE$#eJw2U2!mbF9Ca&{E z7Yaq4s-;g7kZQMlzi7#7@ksx~d|Nc2TFJh$qIIj~@{OTrJ?Dp__3co!fgOrAv_sKG zb|@NRhoX(`P_&61iZ-=F(PlP9n+p_eAy70_plC~hqOAmqwiYPbMxbb0fuijMinbRh z+CiXbM}eZ91d4_U6zwcfG+dx)gh0_qfud0YMWY3Z#t0OR6$(Xzs-=|@km?uttB!+1 z(b4H;jpM47>?4n>pgP&CC3MZ4LdXsR8GrrDurx*dvU*r8~5 zo1#4giuM#J+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bg@3KShEP;`($(ZK>mhX@oMDo}Ko zK+)j>MMnq}9Vt+Blt9tZ0!7CNg`!=mr6~zWb+e`fXV*}4NxpY|Y_*boWkn}e%O~C% zicWHVC_32=MW@)I=u|rtoo0uk)9p}nh8>E|v_sKZb|^aArsy1jqH_g`&J!p)U!dp$ zfuaiqiY^i;x>%s-5`m&i1&S^cD7svr=n8?ND+P+K5-7S_py(QbqH6_;t`jJ_UZCg( zfub9QLecTn(rpPy^^Sa7bV4XvD}P42sanatvZC9n<=1ZyMYlUY6y0HmqC4$SbeA29 z?zThGJ$5L%*A7MZ*`eruI}|-&Q}m!f(L(}74+|7MB2e_GK+$6YMUM*?6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_IK+$VLq3D)s>F)%j+CIa% zH59#`?Tf9g04(L(#`}DEh<> zMW5OfeI`)!xj@ku0!3d66n!O7^tC|IHv&c93KV@OQ1rb((GLPeKMEB6BvACTK+!J( zMZXFZ{U%WKyFk$_fucVIivAQR`b#Jjy;&{wPe7_K0(P}EkSsGUGjdx4@3 z0!1AKislk1np>b~9)Y5H1&ZbqD4JiOXaRwu1qF&05-3_&plA_+qD2LY78591T%c$P zfuc@Aq3GXg>4*fR`f>gP`~QWa?&)QXOSY|KUs=(zZOd2Q7mAj1ekfYr4n-^2p=d=r z6s=^3qLuAXw2B>yI@_VBiyex(+7xvYC~6ic>Ml^!L!hXqKv6G&qTT{Us|pnL5h&^_ zP_&vr(dq(4YX}srDNwYQK+)O)Me7I@^%E%SFHkf|ew3ltq9P;{t3(P08bhYJ)PAy9OrK+#bGMMn!19V1Y5 ztU%Fm0!7CQg`$aVOWP$N)&27w>PeyKggj1YTgkq%qEp(I_jxoFo$CBhbebKCPPaqR z8FnZ-(+)*v*`ercI~1K`hoW=sP;{P6(fI;J7YGzxC{T2fK+(klMVAN^T`Ev?nLyFy z0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mFHwYBnC{T2hK+(+tMYjlrqLbQ|E=WMC z8{|KCeR3#zHji7|R4-ED`Wd+bnjuN{i+vqRDSb|`wl4n+^z zq39ty6g_NH^oT&wqXI>b2^2jpQ1paA(USs2PYDz~El~7~K+&@TMb8NoJugu7fb|`9RQ`BCdsDnUJM}eZb1d8SsD4Iv0XkLM$ z`2>pQ7bsdlplCsXqJ;#C78WR4M4)ICKfuf!QMZE-ydJ7b-Dp1r%ps24v(P{!ks|ysZAyBlYK+#$P zMQaNbts_v>PoSv3K+yn!qJaWMg9M5O3lyy@P_&*5c@Xx?+a2d?*@}KfSHr zu9AIaMMK(^-+UnyZS4F|w22*xHnl_1W_Bpr+zv%s*r8~s9g4QJL(x`tDB9YlXd8i| zZ3T+96DZnVplAnyq8$Z_b`mHWCQ!7qK+$l4q7ec`BL#{^2^5VMC>kSBG*+N!oIufd zfudamigpz!njla#Q79B`*sk<%0#cokZ;LhxMfuA_jg#6{vahUYYP<3hFNdOO&JRV? z?NBts4n@1$p=b{~6zyq;qP^@;w6`6K_OV0JzBWbs2^8%wP;`Jm(M*A&0|kl>5-2)Y zpy&{RqC*9W4ihLkT%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5(-6A z+LZ<-Ak|s?}&<8iAr~ z1&Xc{D7s#t=mvqJ8wHAP5-7S^py(EXqFV)uZWAcFT__Zt+OBj|0#bb{f7S7{P;^&* zq<=@dO7@i%-P5jo_3NSNUgw9R`|MD3za5GmutU*!yGr(z6@A#Q{NtOU z=p*NcqL1xR^obpcKD9&9XLcz1+zv%w*rDi4I~09ohoY}-ioOvj`c|OmJAtC_1&V$U zDEd*L=qG`qp9PA35h(gqpy)S&qTdCIW(gGiAyD+EK+#_UMSlwv{UcEHuRzg%0!4N0 zN}yR;`~t5+73l+>`>HX zhoY(-irU(tsGS{(+S{S1gB^-G+7!(tP&Btd(L4f0^9mHrCr~uMK+ysMMGFcPEhJF1 zut3ow0!51o6fGuDw75Xg5&}h?1d5gvC|XLOXla3>Wdw?r6)0LxC=@leFYSXMp)Y%S2UF=ZQ)ec47>`>HfhobIwDC%K{ zqMmjr>Sa^ZTcBuFfucSFMSTT|Rud>%U7%DvahUY z)Ar?uKL|yeIX@I_Zik{R>`*k+4nH_&O+9siBi+t~TxAv9nD=V7OzTD>HP_(=AL(v{~DB9Bw zMSIzyXm2|d?PG_ceeF=RpB;+!w?okZHbpZ9iVhSgI!K`CV1c4T1d0w7C^}4_=x~9e zBLs?$6ev1Mpy+6UqGJS#juj|6PN3*`fua)xicSF-wD7s9b=yHLgD+G$J6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Ar zx=EnuW`Uwx1d47ID7sCc=yrjkI|PdE6ezk&C={L1zBD}nsqT=!>Ud@-x<20)-QB*D zePu=Ww=bXic_@0o`Jw1RI}|-+hoXn=Q1pl$iXOE?(PMTfdfX00PuQX8Nt>dl1d5&( zD0)Vq=vjfH=LCwL7bto`py)+`qL&1UUKS{NMWE6m_se zQAaxz&1Hw8x$RIik4@3M0!8x)6wNPCw17a-f&xVg2^1|XP_&3Z(V_xHiwP7hE>N_D zKv5@wq9p~2mJ%phTA*kdfudyvik1^7T3(=N1%aX!g+fuKLuqgVQavW$6>8m~c%*-9 zCbd$BO7@i%b?HzZ`&}sN>ikgD%??G)b|~s@hoT;KDC%j4qF#0=>TQRjRqasJ$EK*S zK+$RfMXL)Gtszjfra;kJ0!3>J6s;pr)K8$Ozd+Fdfuex|MS}#21`8CeD^RqaK+*aF zMH>hdZ75K*kwDQ9fufCtLeVN6O2;H1)m!pow9cXE)7k^J4wdXHE83z%`Pv^s(NO1y zqAl%Ew3Qu-wzfmjHg+i5)(%D6*`a8AI~46;hoT*Aigpqx8YWP*vp~^sfua!tMI!}@ zMhO&+7AP7cP&8JcXq-UNc!8o_1d4VQD4HNpG*O^vl0ea9fubn_MY{ri?r0jZA5U%TEs6fK!=i>7y|WM5g)o*l|R{}hV$a(*b<+YUwh*r8}&I~46_hob%M zP;`JDie}oO=s-IZ9b{8TMJEarog`3nvOv)(0!60^6rCnebh<#%8A73G_YS26e@=?-&tGWVBNTm= zzo~X+hf4O96`k9m-1pZ|be{7=(fM{Ly1))a7uuodB0CgaY=@#t>`-*69f~fqL(%0n zMOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2 zMRy1k-6>FXmq5|o0!8--6x}Nniq7s(+9?64_RP0M=Y*os`7_#m9V*#ZR`gJZ@&Uhx zqKBOyiXO2;(W7=Kddv<*kK3W>2|E-$X@{bx>`?Ty9g3c@DSB3*=sAI+=LL#h5GZ<4 zpy(xmqL&4VUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_XUbR5GeXk zpy(r^Q1n2D(j^H;vM=Cwo7 ze0C_B-==5*fuaQkiWU+mT3DcH5rLvb1&S6EC|X>gXbFL$P69 z%L)`NCs4G!K+y^UMJoyvtt3#ivOv))LZPUsW2svLQhm5hf>Z5SJkq~Ee|qcOv66jd zMa><{oBbP#x;sA<^{_)xPdgO#vO`gCI~1*IhoU}qDC%p6qSfqBw7N~v8UjUY3KXp+ zP_(u{(K-S}{RE2o3lt3yC>khGG)SOmut3qe0!8Zy6s<2%w1Gg;h5|(!2^0+xDB4({ zXcK{=O$CZJ6ADFLJC=4&K&pN7ZBe&S^nMHQM>#|e~*rp>?XLju$98L7?bFfufTH zicS_NIz^!9RDq(?1d2`92#R-4FXmq5|o z0!8--6x}OObe}-c{Q^Y~2!*2aI+oT;K&lJoo1gPT(OLO1+JhY{*;iKdXvgySN+^2F z`Jw1>`~M;CzN4e6`!?L~$)24_G6~Ft-a%17NJ8i!NC!cXs-mJHK*SpU7<6Y}yE#0}VWG6%B!(=8QAVn{* zrRYVr6urcjqL8%4hnQ1m+iMSl=bw4Z>YKM5%Mi-4lP2`D;1K+!)06#Yv;(Ln-= zyrdqsqbNc^Q5pe7J^@8h0*V3xiqZ)viV;whK|oO^0YzDaP|?>3|4j!ZUg~D_8z~xO zkM!fonE5hAHIu<_aVbi0z7!?dQk2VgY$>YGmZAo16g4EE zs1X50jR`1fLO@Yd0*aauP}H1&q80=c9YR3Sp#&7QB%tUp0*VeNpr{oAMXd=aYC}NL z5d;*qC7`Gs0Y!NP6y+08R6qz79mPgbZvu+?5Kz>YfTDf`6!j;d zXaE640|_V^L_pDC0*a0%plApIMMDWFI);FvVFVNnC!pw90*XcuP&AT&qEQ4CjV7RI z3;{)B38A76Nq>R^6938W3U!pCV!L;JTry_9OwozSU|B+nPU3tiI+-m+JTZ$&IrKp%KMHAUlG>MI($pjRY5KuIQfTF1c6ip+bXgUE!GYBY}NkGvo0*Yo6 zP&9{tqEZ5i<`PgekAR{w0*cBBD5@Z!Xg&c&3kWDWjew$s1QabIgo;i``ZqWrao=u> z#!1mT_9e*0$(Z>vMQ0|1=X0g#EY6prrEDo$#+IV9*;2HeEk!HXQnZpSMdz@k=v=lG ztzx6-JOYYV6Hs(M0Yz&FD7t`vq6-NqT1!CDIs%F=BB1DE0*clXP;?0aMVAs#bQu9f zmlII5fqJElK)&9gz4eyZJdoie9v_DH$_grf5qt z$f+Ym*K@uUZDmW*4Qwg8ku62r*iv*8TZ(RGOVKTCDca7KqFdQ0x{ZLM+X*PTgMgwt z2`IXYfTFtzD7uG$qI(G_x{rXO`w1v|fPkV02`GAqfTD*9D0+l|qDKiRdW?Xg#|bEU zf`FnY2`GAsfTE`fp`y)6zk>r3Z)Sgb|2iq!VYfxkBxB~w6upoP#?+Id7dc;wUSdnp z%WNsy!Iq*|*i!T=TZ&#|OVLiY6ur)tqBqzm+C@Oon*IRQmq5K#0b0YzUCQ1mq+ zRPmTioQ<A0KDHG7#FnC;*;4ci zTZ(>VOVMv^Df*o)MSrkSw4Z>YKM5%Mi-4lP2`D;1K+!)06#Yv;(Ln-=yj(qOM^S`; zqBH`Ed;*H11QZ1X6r~eT6eFN0gMgw;0*bN-D2fwMlubZU4k1+ZUDAKd0f`58TeMe- zjk1a*@*;3SiEkzC4Qq+hoMUB}g zYC=F!Qv!;b5m3~efT9)z6dgi9(V+wswIrbEFanAWC!nYm0Y$9|C~8AM(Gdg`wI!ga z9RWpo1Qg{HP*gxbQF{W43JECcKnN8ja{Xvyr|3NU5>YZYe5Ak9;fZ$4jhQb~)HOFa ztf>@r<9sRV&X%GcY$-aDEk!-qQq+qrMMtrvs5e`R`mm*_FB?Vu2q@}LK+ymKiUtx; zG>Cwr!2}c?O+e8Q0*ZzbP;?9dMZ*Xv8csmbu>=&2AfRX@0Y#$-C>l*b(HH`X#u89; z905hg6Hs&lAym{k*B|PD#M>I2E>d)i-4>0@jhQb~G(I<&>HbCH)c4U&;e07Nl`Ta@ zY$=++mZD;|6isAH(ImDMO=e3`30sP$uu(LXfTC#x6ip|fXa)gAGYKe~ML^MP0*dAk zP*h4l(Od$G<`Ga-MnF+H0Yw!A6wN1~XaNC5rx8%Jkbt5^1QabMpy+f0ik1*UMJMI@ z>l~2yRrW~#WGOn+KE0ih8#7;~XjyJ>=OI#bHs?#xa<&w$U`x?TwiKPimZEdnQnZRK zMdz`lXf<1k&S#@&4FN?L5Kwd>0Yz&GC|XBA(M1FlT}(jHdIE|rA)x3|0*Wpppy+Y} ziZ&2XbOixLR}xTk6#+#X2`IXnfTC*%DB46o(X|8=Z6<_@&dT-Qc0l4^x*1(6ML*iO zE;nYryqaEG^w7)}hey1`t?pa4Ug9+am#{BWW+ZC4M|0VU&hD;xB5^{F=haSJRnzn8 zCq7AfUgJco+Md@uF}tqkwM^Vy-}720{%q)Z?GnA4cwYO&%4VL|De-a(&+C>*w)DK7 zi4zX@ygrGmTYKJs#Aio%-qDFRd7d{cQCi@6BNO))dfwQ?-yJ<~T%vCm&l{gOx0~lp zNW9X+^Cl;1_42%Fi4%K!-mJu?zMeNX@kM{nt4OpR^1SVdgC(AKM`GYK&$}ma{tVB1Ao2Pv&wC_MuhjFNNSrdy^PWj;Dfhe=65q`C zyd8-G_fKN%Ow3>Gd2c2jUgCN0CL(8f-tNTUWuCVualvxW`#iC0rRRN}Xt2uj_9lu} zd)~gp)-|5@YvQ{LJ#T-a@FLGUkUVX@`}jwak6!AofJoBc;I4s4a>$kLDu^W4Zgkf{ zB>C1g?n;Ox8*O&iLL^zd#a#`NVulC*!0ymcgL|DJTaNYeg6;P#QE z{fn-hB1!uvIlD!Y_HQcoj3n(J#p@GE+P`WxAd<9ymg?w8(*9kcVUgsIPq^zOlC*!> zV{9a8|1`t6NYegp{qd2c{pIKrB1!w(ttUs4_SX|nizMyumz@5u>euIyq<#6~>qycbf9{PW?E%ETNYd^B{u)Wzr||ueq}>J|h%-r2wRXDSN0E-MxL>XNFS4sBheW9?+B<+-cQbK1R5?!P+IV(!&D*Ra=f zHoX(we|7DdNS9Re>ZaK%bk%s(ccWX4X)Q>+$m|1ziZ@p5%=U?*JS1A z7nBtjOevpRP+m5vpsc8TQc2O=veJr@NfjlN3nrBL)m~<=?_Rrm z!Q8Uxv!_=~Ur^!|Oe>vTQcygrWMM)6tkOxvvkJUX;%L~TLEiRimX#Sj{vF_J0b>yu1Y;SrtVUi{_S;=T9?X?&_L6eNKfNPSBYC z1B=|noYcQ`_UzI*t{FaevmK-;`W+)dQ0sqt3L@$L)JRavZ_qr*EeLAm1-XX=wVDP& zdO?tz?#`@stP=^ES;~JX$aHsqBI%t1yBid#861|Hk#OdxUYeHPA!y=qnw?=se^Gu= z&z|Y5mlyok%NOe9t^dc%Q>XD}t4>pHnR+k&g8ZP4J*Ri)-feR~r+MmqN74@s;_hYc zk~X)4ds%9_m%2-7zsyLlv~>5oZ}h;yMT6QO?b)%gTl=GnCWg;;=~Ve_=l+$?cIl?q z?9`3cmy_Ff3STy`zh0-%z4G*7rKNKVz2SYw74<)MY=`h|58#x}mG7@Bsbkgq?NIrC z`&WCDx_})xp-bg!bx&QU`E$yrPn}aTxw*rVdUySGxe5pIR@^iEG6z=vIttx|Nxgn| z_i9B&?(B{oio&;0=-wG84C1Zz)m!UV^%mSmz`fe!`Lky)3g41mw-fKUuR_<#3*bJW zm2bK7opj=T45<2GxDSC|(Ou;5!|2{h_)N8n(3Ml&2QT$P_kq=Uoh#p%yF9$p4to8L zRhOfGkJc6?Y8y*>K0`{$;A0n!(Wa2_`CPzZltPR0lFNWsxF$lvcp%e z{I#H}ebq0ed*#J0bYQ(>2A){dcfjb>dG31DugH1Ta|8b4Om9}{oT<%I|N9@N3R4&4 z|MC--KHpW{45of#>PmDDQWqMcl?X%f_NoI@muQClc1yi#duew1^{eYw`Rlab=c!lf zTlEVb;NDf=(Sr-^fBZJZQn$*tQCKAxX+SHiqTH|YYJyiKBzIeqde4PbE(;yZu(juf zRa6THaXnWF<*Ij=K0J?S>^dG@WS<-KVGLhfrN-UR>4Q<|E*Z}jR()Wq+3Bjc?tU?; zHxsh74|TVykDB|KhVP>Tm!-;8VHK>xYO>rF6`m3rO1(i+KYb+Z%CHx7ue`kOqpgcu zb$i!Qr**EnJfQ+RwXo`nFRXUWSG&f$xYMhMb8A@$9DA|7A$P3&K=BTB@!ai{UevMj zL+Cybym}P_u3@g=$}6>-drPI2W~;6fK9|@nklvg-hd1mzh95%rZd1>=j|4BPyh!eS zxn>x~x;qhieNJ@ON2=JBoca_Mk{?)kwz~%O7OO4+*RlHu>1CDIB}fY0brHU+DkSc9 z$-R2&y`)~`u4J9=K85JH%3qNK7@qHLg*|t#v@HDa6ov==#;jsdSmmOUVigDXsoA~# z@@b`I6_uY2ojNW>cSXtcJ$2+mU+5r*Z?)>0t^CzjU7_wm=wnpq?vjKjxZkjPrt(8s7+&3}-!xURP-nQS zx#|P$o*R7Zan1X8@7~<*$mbU}x4ZJ~yLIT)ymeX0tdipLk~YorW>1RBpFPnXr_3rXuE=wb1A4iuXR-zNnp5U3=$uzRH*a!b7gvhQCQa+*9vCd> zmNz?pwtHyNc5?aLwo~Rd&zssjZ$yXYdG5Y!uSxC#wIpv=$(*Sb(|Wac zDZKxZXV<=4c2ia{y>w1qxw}v9j^(aRF0Lr9+~J49-3JJtsWMzxh1gjBZ=cCRp4C3v zR^G30hEs2|>b{_ED> zEw9}%3_n5=8Qud-eF*Gsr|yZSeyQPa!^&SizwIhfW7_V1&aAviMQSOR^EZEysud8w^7w^hN^pdT+>ze^D3{w@Xn$)xPSj1&0E`VoW5nVn-82lv1IaO zcPD!+51v!Mmv~Uz=70a4WnUM_cK;o8PZ2L|Nsa6ruf9b++1CpC*2rGruS~npzA(_Y zyZc|UJ?!=(1@76PTi)>e;eCf3>!l}S!!!M?jNEALNS#PMzkZ}aq+z5{q;aHa+98pA zJNdt!s;8*;)4}R5_U&#S`!#z*OoBM|QejWGq5BEPh zb{Q1z{yHu>I^5^!_|(vFzouix@Nn1B@z@dJK3T_0MumH`j_;2N_g6YLKR(=fI!+lE z?s6TspA_x~b^LjJxDV>stti|Bbv&~;+~@1~jDv0;kJoj~niB4MI*yzc?o)KUY(}`Z z=(u}UxWCcykkW7$=s0a&xaaG5TY0!2*74W*;f^c_k3ANK$H6)-T^#NUbbQX;$l2xH zrDOJ4;clSg=w;z9(s9G`aBtP|qm|+QPREw3!djO~*Udg!@q)f4?x?{@U=^ z^P=!LM8~t&hkLD#FI*b#w{)zrA>5609D8NBi*>wmW4LeBagY06n*Dme*YWVp;qIv8 ztS#YQq~l#%!~M99`)>?)uq`|ub#r(;M#mM~!+nvCFWnaIcXUkL8SW-J9)EYZC+WEH z-f-Wf zAMW>b%zY``&2${MBitoAUh`_WZ_)Ado#FmT$0K%yyQ_|K-wO8`I^OqAxS!VXzOiDnw#-w?Q{}LVt{1zTZ>A3oja9^(D&OgKbp^kMAg!@n($NwAd z={jELKC9c?zg@?#-S;(Z|E6QU`%1a(BXz8B-|4iyOvi`Zw>)h>ucQ06a%$)3ILLhy z)LuSD$2IP|p|-Ek@eTKFQQIHuSl@kr)b?RIp6b3)YI~-R*SqhS+P+iAZ{4>}ZU3QT zd-pw5+r4yL&^+ABb$rBqSJhtrqK=2SKcir~K*uh24BY28?O}Gza^JSr@i_Gf+LLvh zu3n+NP{%XWSL=AWj@RpWr;d;5__B`g>iC6@KkIl<$8@{@;x4DVXsKgT$2vMT)$tG= zyXn|d$NoAF*3o^sNxhv(I?mM5eOgF$cXOXQF4i&i{xjSkAJBG()XUx7rqpqQ-Jf!o z&)u!@(rUUtSfK9ZmoJ)KQ9RKdE6T#-G@f&hpDVn4d%)`DPb@F@@-5{5=U3_S-NWwu z$@Uds_ht7frS8>J&lgXeSXQ#YtM*d&jlAl!xU6{2)DrhLtIq$QWtM##PH)j&C@+7K z`<_vW``$pcv!;|4&vviWcl7Z5;);s0=@aKyxHtR%`N`dFbHCH7zE|(=7X8PQ`>>^+ zTDbq)>-phKeGgyHrVjQpdurwWb63Ov>+7|1uk+vUcZF*_+4W{m1KfYSZQBpH|8iPY z6`t$ky1NVP+0mXh92xP(xnTa>)t>q$n_aGv?my0P&w9_gw>7p};Ms})^?D83M7;Cu z1U>P3r@CGJ{q7qO@s_$~@7La+{W|P8&;7?a?pg18_x76GGkW4>v)!)#_T~7RS9Z0R zUF@E({`S_nw`adTyL|3utMct#=bpE>*WUeSPm}W^UMqWtda{?z&^{;tkd7 z*n!t`pZ@>j^1bU`&kXTozYcr4&;3{Z@@=U0>$OLf{Cb~v&%0mVTz5!4MSDcN9t?N1 z_iImfKJN9}yI9vf&)c()yS>k9A1-gM^LLnQJn{DIcCq^FZF85;-4&>O;`ORO zob8lfTHwCv(4|}Z4&6F*Z0^25(Y~G8;+i9;jbEzS16Tkg4IWX!a2-hsE?*zXnY*dJ{l9y4^zP92BsPxM|h@Y~n@ zp|z%66*=(ch+m%=v#U7qsF$eQ$NjOqKKGxy$IEoT2gB)!57 zrblhWqS3bFq&zGhuF3*E&k)UIROU9Jw=wQai# z)=|5bZFk8!Y3JH@7p=2)(zd&7U9=On-G%F_UDLL^bltRT*mf7MyLOIkclml~XS?0O zUA`l=#3b(+g-k1+L^Z9A&W#|E#5^=&;n!Ph@@I z?terF$L!Y3gd7vtA23Y`8KzSuWVoh;9IGiIBQzysq^5+7(v*EkwKhV|*G9-1 zZG>E)jgSkq5wcbrA?vh5A#?m%?o&!uJNM}>S{e#@)zOGv6f-#{yf#8!&_>9M+6Z|`8zC=iBV>m* zLSE5E$gA22c}*K3JGBw=x;8@I&_>8EZG^n3jgYsr5%RV+Lf+9v$h+DIc~2W5?`wxb z9`H|a*MHVp$07P)D5QhkC;1>|a!km_f&D;BO2{6aDj}a}O30_067rd*gnX_kAzx@p z$d{TD@|C89e61-V-)JJ_TWy4Vr;U)k+6ehx8zDbvBjiVIgzVEs$WPh``B@twzi1=m zS8as+rj3x_wGr}%HbVAmBjitQg#4wAkiWGNazGm)|7auRUu}dO)DDGw=r4BHf7VHk zN%W(XkoakK8{$P`M#p}-E*c5!$DL9?qZveWwtl)Uovoj)i?Q|7bs22^bX_J}KV6r_ z)=$^P+4||aY_@*7E{Cn3uB*Z3r|W7G`02U?fuF8R68P!5TmnB`SBt<;*VQKQ({*(S z{B&Ji0zX|>kHAmY)hF=NbqxsobX`LNKV8>|z)#mTCh*gBO$hvST~h)-UDu4jPuDdk z@Y8iI2>f*2Aq0N9?oa|hUDuM}fYgY(KcekF;ef<9+uajC5-K{=?#&(+i5V|b)Fu+x zkISVL9l`lh)Rrwp?buS3$CjdewiFexrKmkyiVE3M)PXHU9oZ=AL_kqz0*bm2P}G%x zqHY8fbtj;x2LVM#5>V8WfTCUm6dgrCQEvi@`Vdgmmw=*v1QhirplARAMFR;a8bmJcCZK2tAym{V;-|Z>m&IGzO;Kwpdc;T#jl|5CDLOV1*pFML6pi3~DH_R^qET!q z8qJoXF>EOs%a)?!*iv*nTZ&F#OVKzsicTb;=p+J)P9~seJOM?g5Kwd~0Yyaw6ipzY zsF;AFi3Ai)BA{q80YxPQ6ip$ZXet3k(+DV1O)=t;XRDviX)DMb~WFGcg&QnY|AMW?Z)XdzpQ7O|yhFrbPEAR+X*PTm4Kq#2q?OpfTBAHD7uq?qPqwv zx|@Kadk84Hmw=-C2q?OrfT9Nop`yzo{<{uHe3!wwT#EL)Z!kn3jKs{BDS9*#*k2cr zQuG+-OVQ(ODSCn}MNhJ&=qa`oJ!XPhrZpR=Xt z3$_$}$(Ew8*i!U0TZ+D6OVPJ%Df*5rMSIyO`ksKI9|$P=k$|Fo1Qh*5K+(?x6#YU# z(XRv){YF61?*tV6K|s-d0*d}5py)3GivA{`=l}sl{}530F9Agd2`KW?Dj((Nq`n^& zA)qLY5GvXe@h3YV@kw^`^NAGAwi_ltEoQzLO{`>1QfL-py)6Hw?&5&P}GVLDhks4n;npNhJ8~a zJuQ5sKf`W|TBpU#mnmwO7T8~Rle#U+<9sQ~XG>85TZ-DVrKpfCMIG2u)R8Sko!C;; znJqPtXTKLU#S6HqjO zfTDo}6b&MvXfOdqM-xyqgn*)<1QZ=ZK+!NlsOX3^f1d*qukHS{PqeKR`SwVEcv{SS znW9l?f&Fz!DMh0>Uy8=CrD!Z$ijHGT(eZ34I)N=k!@jvOQi^`CPj6*uG4o}L7NiCC*KMT~oyPf6 zw2&=Di`Y`Mm@P%8v!!SWTZ+zLOVOEZDLRWSMN8QzT1G(8*#s0VC!lBr0YxhbC_0CL zqH_r-T17z7c?1-#CZOni0*clUP;>zSMHdoKw3dLPbp#Y$L_pES1Qe|&py(0;iY_If z=rTg6s3Of@;()|owohX7rRXNRExJ4{X1+|(RcV3!b!{m{8#!N!u4YToHEb!`#FnCK z*;2HbEk)O{rDzLVimqo%(N;E!ZXlrOMgoeq5m0m!0Yx_xP;?6cMcWA|x|M*U+XyJS zoq(b{2q?OffTFtyD7u?~qI(D^x|e{W`v@qypMatV2q=1xfTD*8D0-L>D!L-gf64)g zuZuW1S4z?6c3bpFTFiWzq9@V<`|JKvik{?rDSC=6MNhM(=oz*YJWIW0Y&cMfd>iD=6eeAwb zAN?dPX1+|(7ioe0b&)AWUvj<_eZ`iduh~-c4O@!7WlPa_Y$@8ymZI<3QuG5`ihg9H zXdeMZKM_#$GXX`v5K#0h0Y$$NQ1m+iMSl=bw4Z>YKM5%Mi-4lP2`D;1K+!)06#Yv; z(Ln-=+@C|f%3Y1_JL>KVv_EzlA)qLYfFhrOq9_4H0U=cMS(<;W0}`KLw?&^z(LNjL ze$0HCqAWkKziu?8D9-s(l+Bi+9JUnIU`tU=wiG4UQj}y%Q7&7GYO$rLHXB8C2q>yc zKv6vcis}{YxB>_;L1C$4ozbq(8y#B(?Qp=F1cn_<{X(wJAmI zIbVtj*;3SjEkzyKQq+kpMV;AF)P*fYUD;C9jV(pp*(mBkK+%x|6!j#as22f6M-foe zn}DJ|1Qhippr{`KMg0jV8bCnNKmv*e5l}RkfTE)bC>laQ(NF@4jv=6E7y(7Y2`D<2 zfT9tEP*I-mzwdy=bL1XW9G{gjr9Zj>yA^3j^lhOI-V^>C$Obx99xP` zWJ}RWY$-aKEk)zmQgjMiicV#tsEB}~2?P`s6HqjffTBqR6ip_esDyx`DFhTvC7@^; z0Y%dZD4Ib)(M$r0W)V;{n}DJ@1QeALP&Ai-qIm=ql@U->PC!uwAyhQl_nUWeidNcP zp)pc4)9zi*_haVE6fN=t`|Gk(iWYOe6rIkNq9tr8I)g1mXR@W}EVdLaWlPaAwiKPs zmZIfs6s;hjXe9wf=MYeIE&)ZW2q-#_fTGm|6rE2%(Ha7ZE+C-jLIR4`5>T{`fTD{C zD7u({qV)t6T|z+7r34gRMnKW!1Qcx`py&!hsOU7`pW=YTcN?6AQuLOQy3&uCFH>}l zAJ|{Fo>H`l^QGuowiIn~DcZu8qU+gGw3RJIH?XDXMz$1fW25LM0*Y=Xpy(C? zinbF_bSnWxw-HcuI{`&^5Kwd{0Y!HaP;@r|MfVU;bT0u#_YqKZKLJG#5K#0W0YwiH zQ1mbXMUN0r^e6#Ej}bye8-0Jf0}_AI6kRPvsed!@aX)6hOwrSRV1HeIO3^c%FGbI? zrRX`f6g|(Dq8Hdw^deh|USdnp%WNsy!Iq*|*eH6HfTGt3DB4Lt(dz^hy+J_HE&__) zB%tUm0*c-ypy(X}iryul=sg08-Y1~w0|JV66HxRa0Yx7XQ1meYMSBP+`hONnP?SzUQH+413__^rOW*J2fW+I` zm#e>$qSNi(b!IeXzD!Y0G_ZdzB&DbZ=SxvdwiG4UQj}y%Q7&7GYO$rLHd~77u%)Oj zTZ-zjQBLO{`>1QfL-py)6H ziVi2Bs1*T4tqCY43z)um|_q(eRP}iT3F&KN>S% zrl^Danfbm_)RFV0s1sX?IlXP(MSS{MiEdnnh+{#AN8McK;p~Yj224KZo4fS6OEZKQ*=T!uz#*7bz3x!^QGuS zwiKPjmZFo{QZ$||MW?W(=v1~86|tpg0$YlT*(jPwK+z-uiY60KR6;<}6atE-5>Paa zfTHOH6wM%@XeI$gvj`}fO+e8c0*XorD4I(^(L4f*$_OYbC!nZ;fTH;X6fGd2=rls8 z=(wn#HNYwQ#J=iyycCT{Jz$H*%$F%z5)JI1yGkiKgY%{6OtuuA#g?L_Y$;mCmZG!S zQnZ{cMJw1+w301F=de+9E&)ZW2q-#_fTGm|6rE2%(Ha7ZE+C-jLIR4`5>T{`fTD{C zD7u({qV)t6T|z+7r34gRMnKW!1Qcx`py&z$imoJ}=qdt=HWETbi=+NX2PA%jebw=F zDOzEFWbNu`%zT-m&C$UAxwMp`>o{MEwy>q>dbSj8WlPZwY$>{tEk)bdQgjnrif(30 z(JgEgZ6~1URsxD{BcSMZ0*dY+py*BlitZwy=xzdv?jfM)UIL2lBcSMh0*W3Wpy)vY ziXI}M=wSki9wDIUQ38q{BcSMU0*am>py)|LsAyBvzsv!N-(?TWu9c#B_8IM|Xv}<> zqUWN4{d0RMMbC4-6urQfq8Hgx^b%W&US>?iMQ;#L zw2OeEHwh?ui-4lH2`GApfTDK^D0+{8qW1|X`hb9<-2@bUNI=m?1QdNtK+zroiasHr z=u-lUJ|m#$a{`LKAfV_=La6AOsK46*iMO*)V$VuZXS=KYRWxS4Owo7I!2Y?$l%lpB=rH@Uj^9erh4vXOJBXPtQPO~+H5JR z!Y8mZJJ>DQdu$qK0e~H6oy>F#$zQ2qfXdNPMe( z)v;y}KGOfd{;*MD5HnwCwr!2}c?O+e8Q0*ZzbP;?9dMZ*Xv z8csmbu>=&2AfRX@0Y#$-C>l*b(HH`X#u89;93fQHG4OA5K;jSCZBZvF>TS10#|JU< zWr|J;0{iENQ;JUJd?^~wmZDSGQgkX?ii+4$G=VKe#cU~>$d;l>Y$=+|Mo|d?MNwa|kFZC7@_70Y&o&C@LeMsGNYJ3IdAe6Hv5( zfTGg~C|XEB(INth78626;{yLz2PEFx?h2hKMFZ_l(&<6We3_!Ng24W{>Xf3ToG(So z*iv*hTZ)#mrDz3PidM3v=p42boy(S@Rct9bkBy?$1QeZ5K+zfkiY_3a=t2UD))G*( zj)0%}5m59v0Yy&`Q1m1LMNbh>^fUoQ&k#aI*9HDk2PA&7 z-4)s*MbEpJMV}2~=F1el7zCS7lA@P5Uy5F4OVJLt6urWhqF32c^cq`=cCw}Db+#0} z!Iq+3Y!tmoK+#(S6unJA(K`eby-PsRdju4{Pe9QJ1QhKipy)#aiasKs=wkwk_7G6? z2?0f)5>WIR0Y#q^Q1k@>MPCw7^c4X`UlUOD4IxzYeBeLlfW+ND8{tJ?kfPU()VD#* ze3_yjg5az1QuHI|OVK{I6#c}OqMzAP^b1>xeq~G1Z)_?0oh?Owu%&1}8%2K-Q1ll8 zMSl}ebbx@Oe+Vf0mw=*!1QdDcdf1Ml2mwWD1QhuM6h#Rr3J54lC!i=sKv4z(MVSN? zWf4#mC!i>sfTA1%ifRx-MSBB3`xK|hzV90SUW!h)yV^C=W9G{g)k+WYilnGE=Sxu? zwiMN6OHnlDI)Q+qafDD&mvn!F0}`KPpTxRK z(N_D`?1||y^JR)oNe>>JBt@rkz7!R)rDy_Mii+7%G?6Vulh{%;nJq;nY$=+;mZGU_ z6ip+bXgUE!GYBY}NkGvo0*Yo6P&9{tqEZ5i<`PgekAR{w0*cBBD5@Z!Xg&c&3kWDW zjew$s1QabIplC4xMW+)`w1j}7GYFxglhgf=9FX`?cJnh{iW=Exv@_FV=F1eFogN%4 zk)q|CFGVZZQnZpSMdz@k=v=lGtzt{jd2A_K&6c9`*;2HIjiL((D7uhVBj<<+Q#`(bQ4>OZe~l- zEo>>;&X%HE*-~^HTZ(RHOVJ%{DY}!5qPqwvx|@Kadk84Hmw=-C2q?OrfT9NoD0+~9 zqK615dYFKsM+hi-lz^hg2q=1-fTAY|D0-5BqNfNbdYXWuX9y^ImVlz?2q=1<5GvZ5 z?$2;Q;+Naa&ka(PwDCfE%zT-m9qGaOGoTZ(>TOVRIaDf)vgMf=%O^e0=2{$fkf-)s~e zAfV_U0*d}6py(h0MP5t~+ffuDpeT)iBA$Q0Y&Kq6vYTA${?U9lYpWu0*c}U z6lD`oltVyK4FZa45>S*NpeRWQ75$j*|L%aqr`gTVJ}J7`KBMKvV&=;f)r|%9N~NeC z=Sxw2wiGpBOHo6%6g6T?QDe3gHDOCpQ??W}V@pwUHi}vhP;>|ZMTZhl)RKUr!w4uk zoPeTM1QfLm5>PaXfTGa^6pbOEXe*-|u(Ek)DW zQZ$2&qL~B~%_5*^HUUL*2q-EgplB`uMe_(KDkGq%oPeSV0*dAnP_%%6qSFW{T1Y_A zA_9sQ6Hs(I0Yys)C_00HqB997I*Wj!rG!w?sWJZr2P9s@9-|dW(Tnznu$RSR=F1eV zj0NA!m!fkxUy9CUOVKK}6rIPGqSb6EI-e~?YuHkB0b7bLWJ}RnHj35}P;?OiMHdrL zw4Q*XO9&{slz^hk2q?OofT9fq6kS0;(Uk-gT}43AMgoeiCZOmV0*W>fP;@N;MVkpI zx{iRNEd&%@Pe9RDLa1nY%&)P)DcbC2bcGa+w9jZa#A4>l6x|#P3KmMyEu1e!+u2fd zD_e?gV@uKPY$>{fEk$>-rRXlU6y431qI=jVx|e{W`v@qypMatV2q=1xfTD*8D0-NH zqDKfQdX#{o#|S8ToPeSy2q=1zfTE`eD0-TJqGt#wdX|8q=Ljfzo`9kk2q=1yfTEWO zp`vXuf2;!%f6jh3_9iKc*j??HV=?n(ie8Ha^A}6ePR^I2*V$6^23v}Dv8CuuwiLa^ zmZG=WQuGd6ir!^Q(R*wZy-z^V2Lu%DCZOm;0*XE&py*=)iuMpt^a%k)pAt~?839F~ z6HxR80YzUDQ1lf6MPCz8^bG+;-x5&t9RWpq2`KuWfTAA=DEg5QDtaa6U+I9vhudAD zSEXo>-4^YO#mtu}`ZX3jyhMtA<9sRloh?Owu%&1}TZ;ZQB$@QHDgOrbG8(PSFQCjyE(6HwHJfTFGh z6m=t@s5>E4R4>Cn+yROAvOgqSKO=mk|G3?|?vW8QU#94&j9~CGDeBGnQq+enMSa;) z)Q>Gi{n=79fGtG>*-|u!Ek%RbQgk#MMMDTE8cIOXF$5G1BcNzF0Y%3WP&9&oqLBm? zjUu3EGyz3p2q+p$K+$mo6dg}M(Fp_;jU%AwL;{LVBB1DG0*b~HP;?3bMW+%%MLje8 zSq@123xm^3isssFQBg+Be3_z28Nmh1rD!teOHm11il(roXewKZrm>}HI$Mfnu%&1w zTZ(3}rD!%AMRN!!DkY$3E&)aJ2q-Eeps1XHq6z|v<`Yn~fPkXY2q;=eK+z%siWU=4 zbUFb=O9&`BgMgwl2`D;?fTE=Y6fGm5=xhRtmJ>on#Toux4oG~x{rRGaQgpA8T9FYm zU#4hPMzCw86rIQUQnZ>aMd!1nXboG6E?`U1g={HW%a)>bY$>{kEkzfzQM8_bqDu%U zx|D#T%LpjCoPeSY1QcCCK+%;16kSC?(MAG_t|p-98Ul(o5m0n30Y#e$D7ub-qAdgz zT~9#KRsxD{AfV_*0*bZ~LPh6f`1>7@_-zpf=Ugee%}Cvp5i?(==+=y&!73@bjq|1G zcD5AV!Iq*s*-~^DTZ-;xOVK@SDY};}Mfb6#=zcbe9w4CTK>~^%BB1DD0*W3Xpy*Ko ziXJ1N=y3vyo*5&=y?K)ULc_8MFNUmBB1DH0*ZDJ zQ1l8RRCG&*f0P3fKi19Yb}9PT9`?VQ5i?(==#7k^XtfmW;(RH3lPyJWv8Cv3wiLa? zmZEprQuH2Mir!~S(FbfP+RaAMhXfRTL_pEU1QhKdpy(3uEpeUVyq8I^183Yt%5>S*yKvA54qHF?+atJ7@K|oPW z0*Vp@6eS5L$|azv76C=I2`H*VKv7)+is}(UMZabEFF7FbQ|u1)?^5)u-4@l)jF~S} z)HpNv?m{VQ!ue9vlr2Tg*izJ-Ek!NZQgjGgiVkH+VMQsTvYDYj(9sx!91QZnzP}H7)qCx_SIuKCQk$|F31Qc~9pr{K0MO_If>PA3O zcLIuf5Kwd^0YyCtp`wPFeqyat)Wq&kH_8kj>5oc1V9Sh|FH_VvGbp@Biu!TB6!m9I z(Ezp-4P;BvAhr|@W=ql0Y$+PTmZG6-DLRIYqG1FS4JV-JSOSVh5KuIdfTB?Z6pbdJ zXbb^GV+klaj)0=$2`D;&fTD2(6rD&w(MbdpolHQ{cmj$}A)x3~0*Za`o zv)NKKhb={=Y$=+{M$tS1ipmHmDkq?*f`Fp=1QabGpy)ILiWU-3w1|MB#RL?cPC(HT z0*cNcpy*5jiq0aSXej|j%Lphsn}DL_1Qe|xplBrlMduJgMUylAjSfis0sE?Bi4<+J zKWubvX3Ttkyx|)EZYX~UXL_pEC1Qcy1py)aRinb6?bUgt@ zTL~z-fq5&=y?K)ULc_8MFNUmBB1DH0*ZDJQ1l7` zMXwT2^cn$0I|-qp+cN#u4oE!DzKwso6y0l&(O%DtnJ-iHR%S5dN-27q^QGt=wiLa~ zmZJCAQuIDsiauaV(QdXBeaM!gkJwW5F&jmD2q^l5fTB+cDEf?mqR$B^`htL>F9|66 zih!c82`Ku8fTC{+DEf|oqP+wZeNRBq4+IqbNI=m(0*Zbjpy+1;ihd!W=vM-Yej|j6 zc4hi=9FTZNgY%{oP04WM_sp32GDUx725UD;(chdeMF-eY^bcE#{$)$iLADfmS$gCy zMG>|XrLm>RXG>9(jiP{nqI3d^VgwXr5Kxp!Kv5O}MR5X(vI!{4A)u%R0YxR5GvZA>EGjk#CO^KqCcgmg^fm8 zG4o}Lnq>uVT_Z)!IbVueu%+k_wiF%8mZFwyDLRZTMTfJcs1;j^TC=674I4#A5Kz>X zfTDH;6y*_6lutlW0Rctr2`DNgpr``@MI8w!>O??MX99}45Kz>WfTC^$6m=({s0RT> zM-ouflYpXL1QZ=bKv8c(sHjPn|Ca+2KizJAnr4NM^iQ_YCo5*YOwoX>pwVV28p!!l zG>9!lgV|DaG+T;>u%&1yTZ)chOVKd46b)xf(Xnh4jUb?CBmqUE2q+p&K+zZiipCO9 zbQ}Ri#}iO=0s%$i2q-#{fTEKKC_0&dqVWV2okBp-sRR@i5l}RNfTCgoiY5|JG>L$s z$%If*zbwCx0}{8tsVLfCif*z|k`*&wrf7OrP`pKoW^ld~&16f_EVdNQW=qi=wiK1J zrD!f&isrGUsEjQ|77fP;@N;MVkpIx{iRNEd&%@Pe9RD0*Y=Rpy);d zinb9@bQ1wZHxp2F3jsyj2`IXifTG(7p`tZe{tgEuzT3Xgc!3l(w@3Q7XT{8yDY`o= z`2I#Ix`*?n=w7xI-N%-q``J?T09%S4WJ}RQY$5&=y?K)ULc_8MFNUmBB1DH0*ZDJQ1l7`MXwT2^cn$0 zI|(Ryoq(b@2q@Y`2o>F#<>zj5ivBVIA4n1XG_rs zY$@8!mZA^YQuGm9iausb(H^!GeZrQaPuVE?jDVug2`Ku4fTAx6DEf+kqOS=k`i6j_ zZwV;+j)0=Q1QdNwK+z8b6#Ym*(LMr-ej=dgX99|TA)x420*Zbkpy+o3ivA#=Xg?uT z^mdj%&H;)4U~t}%qP_OTqd&7^=F1fQlNBu5E=B)xz7!o~OOY4XBX=o^u%#%CEk!^^g5l~d0fT9Kj6g4EEs1X50jR`1fLI@T8o#kKSfW&v%ZP5WKy3D;S z+B6lD zI)Q+qaRd~dNI=m^1QeZ2K+$*ticTS*=u`rViU=s0KtNG30YwuDD4Ik-(PRRON(d;L zLO{_}La1n9+&{triC2ofeOoFH>LIR2w5m2<4fTGh0C|W{5(HR63ok>8^Sp*a< zC7@^-0YzsMP_&$Yq7?)btt6o690H2YC7@^(0Y&E#P_&wWqVowTT0;mG&4~MR9gz61 z_HF!`QZ&-;BwY}XnJ-gxQ9QWlUMaem^QCA#TZ%4WOVOolDY}d;MVGUsXaie{u3$^i zm24@xijAU;1QcCOK+!b>6m24)=vo4bHWN^E9RWpK2q?OqfTFDg6x~2T(TxNYZ6l!Q zCIX6XCZOmR0*ba1P;@H+MYj=9bUOh>cMwo?Cm~d{Htyf&fW#-;ZP7X@`o!*C-xZIU zFH>}1Jb34RDY~EYrRV{+6g|k6qKDX0^e|hB9$`z-qiiX9j4efvv!&<>Hj17kpy(+A zik>E*=otcvo+Y5@IRc8FC!pvB0*YQFpy(w6ie4t5Xa@mBuMkl5Dgi~W5m2;~fTGt4 zD0+i{qFn?Oy-7gPTLcunO$Zg;6Za1|An`j5&b?B!I`x1p9y4F2=!1CByeKv5k6 zis}+jRF8n7`UDg;AfTur0Y!}nC~8bVQ4<1+ni5ddjDVu%giz7HaetKq693Hp!2Urg z>fl}$ZIK-_U#94=?BJ%yr08(Ym!ei|DQeA@qBd+PI)W`lZP`-Pjx9xbY$?iTOHlzE zMePYFDkPw&0|7-H2`K7BKv8D`inYfTDf`6!j;dXaE640|}v`L$m!?9gz48yDe&&9X`@;obAS-?3np7MMJZL zAD@t-V>n-mhOwn+I9rO2WlPZrwiJzIOVKE{6pdy}(HOQAjb)?gI0A}}C!pvA0*b~F zP;?>zMJEwZbTR=&;|VA_g@B?{2`DNeplAXCMa2XZO(dXb5&=b%2`DNdplAvKMNdv!!SOTZ&F&OVL8M6fI(-XfXjrrxQ@Lgn*(m2q-#}fTFVqC|XKD(J}&x z&L*H}IRQm02q;=fK+!n_6rD>z(JBIp&Lf~`H33EE6Hv5FH>|$c5wQ$QgkWjOVMR)DY~33MH|>sbOl?Au4GHmRctBR z$d;n3*-~^38%3K4D7uz_qRj*pT}MFC76OW{C!lC60Yx_uP;?^!McW7{x`}|In+Yho zg@B^%1Qgv$K+$ak6x~ih(H#U7-AO>vT?7=}O+e8-giz7N+5WW-Nc?+yq`zK@=B6I7 zWyj2yDS9wFc=CBEdWiF-=wY@LJ;IivN7+*J7+Z=SXG_r&Y$c>;=FAfV_)0*YQDpy*`+igplC^a=q*uM$x78UaN+2`GAF*?SJWj#OvD4&jV7_)V(bFes;`!nWB%}zi0iD z6n)J3QnZIHMW3*x=u@^7ea4oe&)HJ+1zU=~WJ}RkY$^JhjiPS|DEgLwqVEVO+Dkyu z_XHIEKtR!t1QhKfpy($8ihd@b=obQtekGvjHv)=&C!pvL0*dw%Q1mAOMSl@c^fv)T z2M8$ohk&Ag38A9h*?v0*B)&Ota6Xixm+iLbV0O%WnIbPbLRF9M2=BA}=@ z0Y!ZXDC$c%z4HU_7a6#eA8F(fBu zzD&{ZoZ!8kQgkfmOVJ3n6pds{(I~bQjb=;H7`7CRWlPaCNKv4++MNCwiGR4qv#9*iq0gU=qv(?mJ(33jDVuE2`E}l zK+y^UidGU(bPfSU=Mqq~ih!c?2q;=jK+*XG6s;kk=mG+YE+n96EdfRA2q?OUfTD{D zp`y7t{s0FgewF?CqIpu(%{iEk&EyQgkg_iZ-)RbR7XjTL>t+o`9mQ1QgvsK+%l^6m27*=q3V+ZYH4U76OX4 z6Hs(30Y$eFP;@&1MR)u^#N7vURAs~V`#ssSGs%P`Gokm;1cWqtmEL<56b%7FhX4tP zhynsO5KshBQS7}7iinB=qGCZoL`6jrDP_&h9yL$|fq;2-*=M^bhWxpNrWpc>+vWmV*_J03N zioWH1DLTxSqVL#Jbc8KM-?OFY2euUb$d;m?*i!T}TZ(>Rqv$9BMZXeIbc}$a-v}r= zPC(J`1QeYhpy(t4MSl=b^d|vDe-Ti0ih!ci1QeYipy+P`ip~;HbdG?ce+Vf0mw=-4 z1Qa&q&NPw`qFl%f#lOHl$_iW1pU z6lP0N5?hMOu%#%OEk!A8DN1EaQG|`6C;>%j1QeAepr{-HMdb-7sz5+dMFNT{5l~c_ zfTAh{6jddls2Tx9)d?u7K|oPW0*cZJD5^z3QEdW>>JU&=mw=*r1QcCB@D&A9+))Nd z(s~QWOYtA+n|s>k0b5GQ`m%}|rFd6=B}I)nUy3r=Qk2P-qAa!)WwWIyhb=`-*izJ# zEk(`PQq-J{q80=cwIraZ6#+%92`FkqKv7!)irNuS)SiH%iwG#{KtNGP0*X2jP}G@# zqAmm!btRyv8v#Y#2`K78Kv7Quih2=H)SG~!J_KJ;!xZ;^10?BE`yG%ArD(S$)i)(% zeOW~VQ@rhmq-YT5OVMDq6b)fZ(NMM&4P#5uaJCd(%$A}NY$+PamZD48D7ut@qEQ4C zT}D9BPanfTBDCipCI7G?sv(aRe0Q6HqjsfT9Tm6ip!PVo{COVJ$8m!d1! zQZ$z>MOU(=XdYXNu3}5ke6|!_&6c8T*iy8BjiQAF6fGj4=vo4b786jkgn*)@1QcCI zK+*LC6x~2T(TxNY-9$jqG6IU06Hs(B0YxhaC|XHC(JBIpZXuxPRsxDv6Hs&;0Yz&F zzM{euH`4$~s%PO8Nzqb!?|N-Y$ojI1?o9Cp9Fd~CIA4m^v!&>6wiMmNmZA-8DY};} zMfb6#=zg{oJ;0Wt2iYikh=8Jp2`GAmfTBkUD0+;5qQ?m+dV+wWCkZHeih!c02`GAo zfTCv!D0+^7qUQ-HdVzqVjRX{JBB1C+0*YQDplCAzMK2Rjw1wa+T9@J$86ZjL?SuO} zq-d}mucU;mFRSSF6mQKBQnZcprRWW|6urroqU~%c+QF8hoop$3i!DXF*i!U1TZ-Oc zqv%}%igpuF^d134?-Nk;0RcrH5>T{g9H?PNkGw81QdNu@D;t9;%+fOlG5y5q1UA7fc^2=Ln$Ha%PRUV z#rxtXDLTUWQuIArihf{A(T{8?`iU(?KeMIi7q%1~WlPboY$-a%M$vBs6dfm^=yw8& zP7qLZl7ON=2q^lKfTF($C^|(z(P;vT&Ja-aHvvUw2`D;8K+!)06#Yv;(Rl)joK!t* zM^S))qBsJITmp)M1Ygm&DX#OgQS^d^b6AS zkfbboS12LXf24o2C3RtH$ojI1GE=fy z!Iq+yY$o61Egw%9f&0Y$>{ojiSp5D9RrqNxNFO(URaIsrum z1Qg96plBumMY9MfDkS)d2Bo?m8z4y&?bogcOHnO*TU3-9vc9aMxvAdC6H;^~=S$H% zwiI2(mZJG=DY}|1Mc1&UXaQS_7P6&i5nGC`Wus^@0Yys)C|XKD(RBnAT~9#K4FnY3 zNI=m|1QabJplCS(MK=>rw1R-5l>`*6BB1CN0*Y=WplCG#MYj=9w1$A9wFDI1PC(H* zg0E;!s$1!#Q8dMVAMFY$T5Ess@s8Ax^<@>^o$9szQ;P24d@0(%mZE#vQgk0%itcAi z(F1HLdXOze53!}_VYU=K!bZ`f1Qb0+K+)p_6g@#e(USxeJw-s#(*zVfLqO591Qb0- zK+*FA6um$|(MAG_HW5(tA^}A&5m2<5fTEWPDB40m(JKTLZ6%=SRf4bRu2lDO10<=L zy)9ZVMG5vZ+H0vH>&q&7Gu2ygN{Y5~z7*|XOVLiY6urfkqFrn$dYdgp@35ulUA7eM zW=qj~Y!tmuK+y*T6n#iQ(H;VdJ|dv#V*-ly5>T{{fTB+bDB4dz(We9y9U!3SGXjb} zC!pvH0*Ve2Q1m4MMPCt6^fduRhX^S8hJd1P3BICjsqTXYNK!ldu@fJ=}#DAp!y8ZN)5eZpeR#8sG8}zRfHQ{_IYRZPbLRF9M2s6HwHLfTF$x6!jyZs6PQk0|+P@NI=mbg0Cnm;?6NZl8)GW*V$6E z%-%2!j)bf)t7v${yWO#GAlnIE%=uC@f-OZO*-~@~TZ%4aOVKE{6kW!aqRZJ*l*^W) z(QFju5l}RSfTFPk6pbUGD4&3$@dOl2AfRX>0Y#GtD4I+_(G&uTrV>yzjew%*1QZnz zP&9*pqL~B~%_5+vkbt5h0*Yo6P&9|&D;gScw;CWxE$p|>hDlMfeWZUyBxHSAMOQ_< zFXN)#!AfRX^0Y$3_D7uA!qFV_lT1`OFZ3GmpA)sh20Y$eHP_&MK zqB{sEx|4vSy9mCbDICB?5{z6HxRr0YzH~D0+o}qOAlJy-GmQYXlU%PC(H% zg0JYFh}+WuNvdRTel|!^cl#LajY!D)vWj*_yh$M`dW-X=Xct?G-eybDJ8UU>mn}uR z*;4c#TZ-OiOVI~xDf*C&qCEr@eMCUf#{?AZC7@^@0Y#q>P_&RxQfTHgRC^|y$6>X2WD-4jN&Gxov zhZH?v?_GZ%30YrO(a#a@nM5i2h4ZE8C|intWlPa9wiNxwmZIZqDf*o)MJL!&bdoJa zf3Q*XCjmu&5m0oBfTGg`6rCZU=x+jw&Js{`j)0(K1Qf*+P!uAdD1m^YL;{M!1YgmQ5qF;fl2l-3@FywyDfWOZ8nV8uqSUDO zXOa{}IA4mQY$-}(OHo<26qRF3QF*o$RbWd|MYa@GVoOnFHj1hcP*jzGqG|*bRVSdR z1_4Di2`EY@pr{rBMYRbiszX3gT>^^g5m0mi0Y&u*C~81JQ9}ZXE+n9+5dlSw2`I`S zpeU1oqAY^1C^_m@DPt79X}{{267?VHud}yB+0l^oWfe7xdTmprs5$3LQ46*dwPZ_C zE4CE1W=l~UwiLBxOHn(v6t!nd(M4<&bs(UqBLPL72q@}IKv5S0inQ6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZ5CV#Z5`0BXqV8w| zB=n~GCqD$FQG>R=nm$9Yja<&xZvZZJ=TZ;17 zQZ$AwMPu108b?4;J^@AJ2`HLCK+!}3iY5_IG?{>+DFhTvC7@^;0Y%dZC@LVJXa)gA zGYKe~MLqwd27NYXR*wrGSD&9k4;=0!u+ zmsNC4)Z3LNMGH7ziWah^Xc1eAu4PNnVzv}5VN20cwiI2*mZIy~Qgj0wMK=;qbQ1wZ z%Lpi1PC(Jk1Qe|xplBrlMXLxXx`lwETL~yyO+e9Y1Qe|yplB@tMYj`Bw2pwHI|wMc zlYpYT2q;=lK+)X<6x~Dc70r*jM-7mqO7`aGYAKp+$A)Og`m%~1ht6g@B^11QfkWK+$Ui6unMB(KZ5#-XNgpO#+Ix z6MRMYMcpO_NYb13tB&_eQGvZJ+7S&|UsloEQEx~^DSC(VrRZI@6zyh9(R*wudY>&t zAF!q9L$(y{VN20RY$^JfjiS8-6zwCR=o12p_7hO_DFHdrMllIGi= znB65sf18&De~N~zFRSR+sCP$YDLTgaQuG^JijK3T=y$dhonTARNwyUI!Iq*w*;4cu zTZ&GxQFNMsqB8^({Y^m8SptgA5m59G0Y(23P;{PvA}37`+ffuCpeT-jBA0-oAOS@l z0Y&iy6om*VN+6&pk$|Ew0Yym!6qO;MD4F0Z`X%bVW`HC;YHy2QBsjFyrXvc9aM zv^4MQs!~*z^QEX9TZ+oFrKkd1iYl_Ds1jR>Dzl}i3R{Y*vZbgR8%5O#D5^m~QB4Ah z(g`T4MLRfT9ZtC~8DNQDXv%G6*QjB%mmZ zfTC;yigE}jYC`Z8Mbg}0HKVAp{ilaQ(NF@4h7nLSoPeT>3BID{ zX>M-=B&m^w(?W_)*>CWVNDEnCR?(<5Z;JUBiDTbKyNvUt=yJ9c<+7z{G+T=D*itlx zEk$G5QZ$Y&Mfq$g8qY@21OkdC5>PaWfTGC+6ip$ZXet3k(+DV|f7!by~>!vWga^dC%3BqH8%{iWak_XbD@2ma?VjI<^#D&z7Pa*iv*OTZ(RCOVKhm zik1^lbTa`(D+nlBNkGvm0*Y=Spy*ZtidGX)bQ=LhYX~S>OF+@>1Qe|!py&<)itZ$! z=q>_^))P>4HvvWW5Ky#%fTDW|D7uf}D_W4|?l(Y^zBeO!Dj?H&Mr_7O7v( zand8xDmYHv$P1Mmr$OXQ6~}2D=}_HqvLj1tI!?35?plu1DiW>hIPD@AU*I?$BX>7& zoUW0>7dlSQNW%=r=^H7?a-4yYO*xJ;G;+47g_lSBmeYuoF$Pi103gu$c=*> zXL;nqA&#>uQhvDO+!ncXgyXD>+;@rNtdIOK%5ms`tGIBoO zah{EIo9H+jBg-Z`&gRHRQyph(q+)^NY>Qkr({Xl09w>C2w~U_*b|vO z&vEueUYYMW2O@z5j&m^5W0B(=irl=|alVV}UFtYLMk?RnI7cJ7H#yGn$V1B==a0xQ zD;(!^BOYX3F+x`C+u=g1obqW0gDZXAf(e-Jo35VilJYqLPq{*#=o z0#W;KDz*zm?LUgwF%Y%?s#(`S)c&(nJp)nu?+Wz|M1R|6u9HC2{>vUi15x`=GmHpC z?cc3GDiF1QIr`{8)c)<(;{s9p*Aq_+MD5=%J2eose?jPsK-B&Xk41r~{VV$B2BP-w zSeqY++P@@gVIXS%mZK$s==MYA8VW@1-!rm25Ve0%#Hv8l{-6H01)}zU)m|5f+W*&f zeIRQ8XUTg5QTu}6 zvh&TKqd-$r%OMbBuPUnfX;dDP&%+d5V2Kr@YbW z1X^f3ZO#j{)R<>aZI!Y(_G+!npV2^T|0NYN?W?tk4SV`X`*yn8H`-RG_OYX##^8V% z?KO^?+kn7D8Uw;+bkG=YFGxp!nCGH_dMRa-+?1**!zxAtk&2EJSJz2Oy2vEQaVt1( zN}Hs%Nv)H5l{Fs|y(GbLyylKA@u}u@?K7dWfutn=H3McQBs*>bCnhB&CzVOEzq7=O z|M6O3^IE0ee3GW;zqc}alV;jCnXES%duhp=OwpUvYo(f#ypqciNj4YLzUOG{8P9Rj z^jp$9DVrJSP?-x+zj8E?7T>Yb?VT%|tJEuX;o>U3)Y*J!$~P<3s+l)ip>)tI+3QhH z_TT#oI0NlrwE5*a*UaBwpRtgF&dI>Q4d$8ucrrJb=8Qr1z$*rT*a}c3g*9Y zPWA?SEcH(8X|Z<_dnNOqYUY>yY+&CVPxkGWek#3Z8jG$o$ea=vIGd8}1k96pT`May zGiz2}*7(91S%tI4X3fei9GjmzV^%>?{@9}Yaam($T{)wuz=pB;<7UswFD&&k`}*d! zTW8IfHEG(UqDgb|oveuk)AFu6=vl($t^6J zJ#JD#R#8F0)UgxuCQUEQnlN^3Zr-eESvlFcO>>)MH_6G($+j`W#Ej_$)AKX(^Ttfd z$jQ!Znqgm@XB>qQa;H-kl=3`!%HDpHKtSQ}RPtP4{elHUSPMuwtJGfJee$D?k zuBJJ8MfvulwP5&zn89D7Wa!8To~o6Rj|Fb&Z=ey~qqB zXh@fCx#nVy?NTspTETSFEIxCy?Zqg%O#_}+_J4Zv(&Ec`0XIL>OLHrydtQ7WQ_KnR z?RBi>l@E9|ZOYu@C7OFZf%s;gz4sGH_3FlEz@O={m&V06@zPC>GiOw_$4up{|8Lp8 ztGIY~PNrAhK4&hD-buQfoEaN|_&Q#aiRNMU&@jkkid@#(1K(A;nvj1T;Z^eJ6 z)J15?spf+hd!hNj>b&N~Z_HdC-f0uPe$$f6(WUr|oG!d8bHR0n6;SF1^ndGSqig<{ z*%SQVjrsVS_hoL0N?ifE9L-8Dnz^$5S1Zgb31h%96Qfk zkNO=MuX?WQf1K$|EtozbJ@%jf%T!Lu1?em{=rY$?>>a?V7>v);{yFOwJA1PIqY-=6 zY`qC1RhOi5@ny1qCS$MEspP_SHP>yY!98;9fA}NC_1>!ZZRC_FLj@>uO4yl;ulEUs z;w#49>MT*1CE3UtDqxn;Ruv zupD#Acs8fx15@gHZmGAS1TAL>>mA2sta_1{MmE=!4loDu{%r4*Pe%0H##`sV7$ z>8y{0y)x{3YF&JJ%|}}ox8$~|soqlalFQ>Oh~4g%T=6-juK7~ecnfoS2}f?(a)4uB zY~PSM7Js04hq`#?HbpOLTKpk29|&H(gaOwuS8(x_+RD78f?~5J*9o`#_SQmg&YZ&= zHXi*Cp?SBlXUs=}mla1h9>Uw=nG}lM0*ef~q>BJ}Bt@vzn4d^YFTmr6R z^AXa^imyv^75ML=#D=-)Fs~JRsDu(TX{WK{2MXu{PWEXrDN_L&hkGhIsQR^ z9!oUjlyE2(Sfapu_B3z5aALu%qT)|j1{;^cztW4Z@8VCb=8sA2RqS;V6J$Ob{xhWr zlw9RGCD(aQ$(7DEl4CAx>}2z~H+JMBo@4y_Z?)tKE&kn?T#x2L=wp;)?lt%)m_Mg_ zruajd<6q0MKPx3MM`xI8x8wtDp6k(nSbCS%t<&ut>dc&UdzU)9Rg-4v4QAy}&Ce^$ zZjjQX-%7&P&9G&v@zy5eriEpQHHrc-rih2<7_amIex~R<{5=E zGREb!FePu+*op1U9rQV^GNxrtGk5VDjVqkdX#9-yj0x!(1Dd2~nERCN$C?X}F@9Qp zVPW2c{EVsj(tdB$8NT-7 z&vr4~xw-%OshB&9CHEEKWAEJz=su+QQ)~`*4NLCkmE5~4xpQakCc?-6(_k-Nv1jfW zmfUA6b(f9%g(dgT_=Azd4X(ZK=6{4F(!Y}y`w-ZBhPtyD`>pza42ysJ{IM%WjcI!i zaZ2$mA$J5z?yQyES3`I4RbPBpu=qY+@!h#ne~e20FqGUGD{J{$sae)+{qrwBjng0R37;@{Gb2Wng?TL%&+t2 zDd5D-Pbrh^n6CgAKiRJbbV*5A61O7YbZTuzo_$#D1hUMtUaO3Lnf*HT>hHuyL;Vun za6($JT%dfQqFX6YIZ!1~HBc>3Bd&HJlP^>hztz|m5sFvP`TczHFweO5ab>9|S6{Ut zx%OdYsVCPwq>Pr@_Ujw=_b{Wl*@v7ZPp)IW^i%4|b<9`JNz^TqxK>h}7xuV=qVWRK=6@v&oP9S7<- zOh@zJKlbv;I?mK_fsRXbT&3d!I=*DTdSu@Ib{#)6zcst<{~K+OXU%WG9z*6Tu*d4= z_hOF?b?jiiu4Z>19rMiZ!R~1~KAh_B7j!&oJ^=RRXLM|0AlThO$GPTs=uQ;_BP-4u&;lyj;m_=`)(cgn-8pg`C%Qa)%ABn9mibY?*bhkHCKRr{Y^R^ zyU^cfb!=w7d17DQNymBSin9B99k=E9`+XhboB6w}j(yD)YF~e(j<=dGK-;}R#{+Hr zeMH9^=8Cs3Z=~b64*s60BIeNs$szc15q?PPyHpyR=*{{BhF+6Dg3(sANUf6vzO=|X?M zqT?U4{T-O&AKT3Jk3Do;IM3fV>-d(r!LXNiua0FF_`9->gBSTbSI2dW{r!-RUoG|b zFFMw}!QVMLPQJz^GwZB*D`1Trqf1+c`I)7Ky zap;}?&eQSE_5OZD$3y0OW%l>`tBx1k=kKOEPJO`NSL*ouL;ikU$J3Aa+k4bMUi7$s z?4#q7C;fekj_*G0?@x7%Jm>G~Iu3uq-(z)LzscW^>GTyypXdKcVAy zd;I;oju-CrcS{{-eB$q`b$szte{a|E+-Lqy{Mo z4$|?aQ~thP$318K{iTi-&iT8Jj-&qd_aq(fH=ot5*JpJ6(R|<1?musZNr|I_Yz zI$mzR5o-4o9UnB`5w-g{9e+088nyeBj@jmWq;|L0aZb9w7wfpyeAm>z{2d)@o1a0j zJ4?qF_UM_Jmqt>ZBD(c0s5oTNTS$Hh9X((!H`AJ=h{J({=svW~B*@7D2v zjz@Gnq2qZS_IAeVI7LVEX(86l z&3)`RPsiB%PcT0opluGZmz%pyvEyiaf681wbGOEcOEo_@pzdTAUOBBOZ;Uw>&GL^E zdCoj8FLE;N17Rm~OktsuX+!3Je$g+}JeX64UuO1;#4 zqptMKo0T_xLcV#MCFlR&Wvcx)o8F?iP)_Dp^F5(_^KF4rXN{kgH_g0Kr@{R)^NNaQ zO&T-1$h_JA*H7kdoB5Mg^1XO-x9C5f%!e)ZRLlI=zMkvP*!Sr5Z0ulPW}oVtU*>A~ ze|){h=5_x2{mwUyCwslwr>^D~Z`r-sNVOe!p*b4LA!;v+viwKl}Tz z$C>6A=a^@m_2%uR+h_E|%chxK`t9}XW_~8gH2e1KpDo_r67xLgm}i}>=IzbB=k|dC$DP*<9JBUUsW_zVzFhXx^Uv{n^WBZnlcw-u>oz z`}VTUFZ1q7cGmR(Sp1oZx{dx<{kZ6f=?c#2 zO*y@D`ZVd)r04ll|DNypSI1!m#}{-o&O5Cb$iwAU8~=Y(@wy=+`QhQ^g5#(O}sO3Zr^}E zwhgV(r)KY(z0!Lg&9kp>-cJwn{zjSiRbjw!r^udPrDwTb(cU{xAKhkt%`m@4n_nGw zp5Ec?JbftAXmr_$clmE?V2{75cS`NEC+|&jdG_X=esy5@(CznT{nmAOy;FbeTmItr zPNYJ|G8cAr%48;(AM*+Q2 zn&&<9P{F?I9U*fw9SmOJJz`!KvVRX+ef_^JHOfQb?`u{w zvzZfYq*>L>=1#D&W)(AAn7_VHv$B~jonWSBB{N$&!7R;+X0|qe1At})Gjq(v%F!-w zx4B$Rw9DCTE?86TvUZzG)=WFiZgbI^Ye(%im#u|%#BOupT56}-Z7y9a?G(Gs#cQpd zY`3|5ZM4gn-NanJw%SQ{o6FZuJ8ZYPeC@Rp?KYS1BJBjb&E@N$9kSb8zK+`QcALxB zN!zpAT)xiQLA%Z6>!NMGj@G$}xqMx<(_ri2XEl#n5s z5;9a%LWXG~WVkj$F4jiK2yKLn)JDi9+6cK+8zG~#5ptO}LN3=vNUkYft+6bAV?F;GU{$j5G#O>yWCfM5-l4owA zf>T3QjukS)`^CI4CS;~gm5^DQ5>lusAw`-JGFwwZ=4eXD6`B$ zJ`2W#tktO!a=WI4tkaZ`J2WNaPE859OH)GDYf8x7ni6u4ri5(JM996`2)R!iA@^$| z#pM#v^@U&v}V%Uu77ciP*K+k7GM_Or~3AuGoU+2YxM-zO&I6`d*} zTQw!*RZR(bO;bW%*OZWLniBGcri8qyDIwc6C1i&tLUw8+C!8As=cZWREsNKGH_W$Jz+ltBsI-+6ehX8zK9(5%Q@vLJnvn zDGLA;+~5^1C)d zPG}?Kq&7nS&_>9g+6ehe8zHB(5pr4^A!oD^^0ziZ&T1p%oHj!K(MHI>+6XzX?F;$R zEi%`C;s^G=$5$~S;dA!(#0i8f9VaOm3?&rPyX8sj%4VCpJ5NCpYtW$>&u)$o?x xIcR=1+}&b;gg4r| zCvL!3bk^Q)sTT-YURF`VfcJ&@!b(ihg`6)%jo4Dum@P#aY$?iQOHmeEin7^Kl*5*y zCTuBc%0^K$0*aawP}G8eqLu^{wIZOXH33C!2qH+=mi3bHWE;@iGZRP2`GArfTGO=U(wot`>_EM z9$_Dp-!4U0TSYGiLe`g6^lHF6Sw)Io<9sQ4oh?P%*i!TcTZ-OfOVM_=6zyP3(N4A$ zy~UQIU2GJ+O+e8*1QfkXK+$djiryoj=zRi;J|LjzLjsES5K#0H0Yx7ZP_&nTqJ0Du zeL_IdegcXGrm0s}%ii?_GZt z2w7iN(YFDwwfSkz*lp2a&X=O^*iv+aEk)n6rRWE?6#dASqMz7O^fOzEeql?|Q8tQx zC7|dS0Y$$NP;{JtqTdN9Izd3uNdk)gAfV_^0*d}3py(6R)|XWj zit`rKl%fRAm!d?r6ouJRl*E>zGHfYIW=l~DTZ&TIQWRlJQIw6MGy;ms5>Ql*fTHpQ z6jdOgs3HMHl?W)ROh8c;0*a~}^qlxRCW_6*Z3YcGi-j49=ILOtutd zv85=REk!wODQd!&qNZ#qYQ~nL=4>fy!A4O_0*YD@P}G`$qBaB+wI!ga9RWq{2`IXV zfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(q8&%jU}LH905i71Qd-YplAXC zMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fsDOZ?83Yu~B>0L3#JSl9NO-=zEgC3Ah4wSr zthkW%Wfjed^9EfYMOSdX6wPHz(Uoi|n#Y!+tJqRBpDjgKv!&=7wiGR3OVL6$iWU)2 zbS(iziwP)NLO{_{0*bC9py+x6if$mF=tcsHZX%#)839Gh2`IXmfT9%y6s;tnXcYlP zw-8WtD*;8T2`IXafTA@76s;xrii+agIR;3$r~MMqY$@7mZ;Nh^3t3-Q(Oq%g?G2=8 zJ?Bf&-E1kkhb=`L*iv*aTZ-;uOVRyoDSCh{MGvy2=pi8(=qUnIRQmq5KwfGfTAx6DEf+kqOS=kIz;dly%y)j zH8P6M*hl)WOVKEM@A{j#ko9F19f|YmWJuBXoG(Q`u%+lnwiNxumZG28QuGU3ijK0S z=vTHB9b-$;Z)_ADC!pwe0*X!$P;`=jqCW^I`jdd7zX&KgML^MM0*cNMQ1mweMP~^p zI!8d!KLiy0OF+?i0*cH}Am3%KM)MtY^Q9X5-PiyDMR5caxdapi2`KUizM{i%ZchUw zJlftCeJ4f7?TB|n)|XWjcD+eiQk2B`QdEX5MagU_N?}V;DqD&oY$=Mer6`RpMP=Di zRE~|J@&puBAfTus0Y#MvD5^|AQ56D;suECCjew%+1QgXEpr|GRMd<_-)gqv%HUUL- z2q>ycKv6vciY_3as6GKj4G1V|NI=nr1Yc2t>#i_B!h7wH3njY#BmFP!ZBZjPWPMph zS+4g?jud5cz7*xKrKky8ikh;es2N*|nzN;-1zU<*vZbgMTZ&q~ zMI+c!G?Fbvm$0SiQnnP0VoT9wY$>{&jiOuvibfMqlt)0(7y^pM5>PabfTDZ?ipCRA zG=YGki3Ai)BA{q80Yy^?D4I$@(KG^zrV~(9KtRz90*Yo5P&A8xqCx_SiU_`d?~t$Ek*O$Qgk(2imqWx(E_#5m2;@fTHCD6x~cf(Fy{JRuWLO zih!b92q?OhfTGm|6x~KZ(Ha7Z))G*3I{`)O2q?OP;48Yqbw?W@;XHd=G*^lSTT*wr zA?wR3y2tevwUVL@oG(T9vZd%gwiMmZmZAsPQuH8OiXLK1(Zg&hdW0=SkFrtp7y(6( z6HxR70Yy&|Q1lc5MNbn@^b7$-&k|7d905ho6HxR50Yw`LDB46o(TfBWy+lCKW&(;{ zCZK2w0Y$G6P_&hRqE`thdX3;KTJO3K8zAA>KNNqr6!o{HUUx&*msPag^>&&6Q8o76 z*d3fNMLXG2^cGu+cCn@CZMGD>!&00Bjx5m59w0YzUBP;`)hqAv+3`ig*}uL&qRL_pCu z1QdNsK+$1>ujmceJ!*i2SKF^Tz9~f=?QPL_ZpiwwihgvxWb-!|#T5O-`BL;VTZ(>R zOVLrb6#dGUqGN0+`i(6`$JtW!J6noQuu*i9fTBMLDEgCtqQ3|zIz>RyX#$GQ5K#0t z0YzsCC^|<#(LV$f{Yya6c>;>e&v*L|+ffuCpeT-jBA0-oAOS@l0Y&iy6om*VN+9@( zzIWXw21vNE{c`mWQgoHQcbymvSzlIBa?l&nL5fm1Uy4%MQWRlJQIsu3X>2Jf%a)>Y zY$+yeKv5k6 zis}+jRF8n73kWExPe4%v0*V?EP;?;yMU4n3YD_>;2EkX96m;hrAmNerwx~?df29AF zy?31%3|U`RQInu|M<*$2%K1{%j4egY*;3SkEk!NaQq+nqMXlLV)P^lZZP`-Pj*X)B z1QcCFKv4$*iaHWd)QNzi&IA;7A)u%$0Y%*iDC$l?Q4a!&dJ<67i-4lu1Qhilpr|ha zMg0gU>Q6w?00N2z5>PaVfTFlpVQ9c1h;|VC5 zKtRz%0*WRPP&Ao z6kW@fqQz_}TEdp1rEDp>j*X)02`IXOfT9}-D7uM&qGbdWEhnJpW&(;<5Ky#|fTC3d z6x~8V(X9j&ttO!8HUf&)5Ky$1fTG(8C|XBA(H#U7-AO>vT?7=ZC-{oy1>N2TNVt*x zx$CQ>C}94F*Wlg3ko9F1-52zx^pv9eIbVt%U`x@1Y$5&=y?K)ULc@oBLPL52q=1yfTEWODB4Uw z(aQuBZ6ToO6#|O35>WIi0Y$G7Q1m(hMcW7{dV}CA+7NVC86e>f_O|F=DVk|NqrDjn zSzlJsTS4!+-cq!S^QGu*wiLa?mZEprQnZ^bMenht=zX>neZZEY57|<*hmE3-2q^lP zfTFzw6zwCR=o12p_7hO_DFHMj;Dw1C<+iz6h}ajOF&VOfFh58qId#|LIe~g5KxpzKv9^0 zq9lT^=%=7tt)Ef!xc!XwvlJ!S&uC@5ko9F1MLe(l04a)cz7(agrKl`hipsI2s61PW zDzK%fB3p_ov8AXoTZ*c%QB;+HqG|*bRVSdR1_4Di2`EY@pr{rBMYRbiszX3gT>^^g z5m0mi0Y&u*C~81JQ9}ZXE+n9+5dlSw2`I`SpeU1oqAUW6vI)MT6we)FfP^dCpSw== z{73qu?G00o7qY&rqUN5rc#sse;Cv}+$(Ev4Y$qIPU4YR{IUi`Y`s zfsLY$1Qc~5pr|teMO_Fe>PkRSHv)>f6HwHHfTErR6!jvYs5b#ceF!M(OF&US0*d+* zP&9ymqJaby4I-duFabqF2q+p#K+!OQuc)c#K5Br3J0uu5&7^3n9mBnl^<@=Z;(6~3 zk)lgEUy4StrRXxY6kX1iqFlBVjb=+x9$SjWu%&1$TZ+c9QItCCK+#MBie?c|R7gNk5dlTB2`HLFK+zQh6wM`| z=t=^L<`H~FBRuz*0TSM7?+T5SqId0W(N$i^`m%}^cwXvoDO$++QnZLIMc1;WXfa!g zmawI0DO-xJV@uKXY$>{dEk!r7QFIdlMau{%T24UG%>)#!AfRX^0Y$3_D7uA!qFV_l zT1`OFZ3GmpA)sh20Y$eHP_&MKqB{sEx|4vSy9g*+Pe9S#1QgvvK+y(*ujp#eZDxRk zN7#pD*GSPZds}p`7qY&rq6a;1*a#_li1VfBVYU=K!j_^(*;4cvTZ$fMOVJZ-DSDDE zMNhG%=xH{Jo*|& zinbC^^eO>GuMtr6Isrx72q=1kfTA}EDB4ay(GG&I=zhhNYO6yvfxfH zWPMph?|9x_mq^jOoG(SY*;4c#TZ-OiOVI~xDf*BtMSIv%^buQ%K4weNUN(yM5m59A z0Y&=>DEgFuq5}jJeMUgh=L8geK|s+#0*byQpy(?CioPbG=nw%#-w;srEdfP`2`KuG zfTAM=6n#%X(GLU^{YXI3PXu4lF3;U&fP~FITHyrWmZIVIGuqEy$ojI1j(OfUqon9J z&X=O&Y$^JkEk!5TQgo6nMSrlR=ufs3{l%7|Q*0?Z%|_7~0*d}7py(_CMdt`8`iFp` ze+ei$Pe73quZQg@3J_2fM?jHFKv9r@B9DNgcmj$-1QaC@P?ShOQJ8?DBm#=c5Kxp% zKv4?8S9H{K<1aIc?Dt)RzeZA)z6ipa-1(k<=IkHfh|Q9*-})A zEk%{tQdEU4MOE2SRE;e~)!8VjK|oPW0*cZJD5^z3QEdW>>JU&=mw=*r1QcCBKv8`H ziW(45)R2Ip3kfJ{L_kqv0*W#SD9R+DD2sriYyygM2qwP8z9TecLnV@pwcwiI2&mZA=9DeB0U zqE2in>dZz_7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF4IrRs zAOS^#2q+p%K+zBaiiQ$UG>m|v;RF<2OhC~Hg0HAWynCww68_QNFKQ`8b?g`!AF{rz zqRZmF7sg7_<(w}?xojyK&6c7(wiJzFOVL=i6pdp`Q9fIW#)BFt16zu2WJ}RaY$;mCmZIfs6x~cf(Fy{JRuWLOih!b92q?OhfTGm| z6x~KZ(Ha7Z))G*3I{`)O2q?OPfTBAID7uS)qV)t6-AzEzJp>eOAfV`80*dY6qSpy1+D1Up8w3=+NkGwd0*ZDJP_&bPqPGYr+C}gcJrwVbGeE-C>>cWd zrD(0aEqXgXWPMph@5OsdCri=$oG(Qmu%+ljwiNAQOVLMcDf*Z#MSIy&w2v)CpRlE9 zKO04#5>Rx2fTGU`DEgd$qAv(2I!Hj#mjo1jML^Nl1QZ=2py(R{ioPYF=r93A-w{xB zgn**&2`Ku3fTAA>DEf(jqMr#U`h|d^qXb{kyYcSh21t0n{fxF-irU+U{lCVCtS_tR z_jqsjR4F>a`BHR}Ek%E@rRYz#6#d1PqEl=sI?a}%Gi)jPn=M6W*(f?kK+!)06#Yv; z(Rl)joRA*2qbNW?Q5*q9E&)YB0*X8WisA_<3K3A0KtNF<0YzZ~ijoK@Dnmd~G66*? z1QewbP!u7cC`#}Z{TA;YH$cL_+MA!_QWUYD(b7U8>&q&t5b~l0QdE)irKl2HiYl|E zs0v$(s3CZH&XfTAV@6g4HFs2Kr8%?T)KLGTro3%M-} zkZ^DNNWXl@f25ykAL+LYg{&{DsBOr*c%~G!<9sP<&z7Q#*izJiEkzyKQq+kpMV;AF z)P*fYUD;C9jg6x21Qhikpr|JSMZE|p>PV8SfTI2c6b&GtXdnSag9s=Z zOhC~P0*ZzbP&AByqTvJ-T}(jH2m*>m5>Rvr0Y#S*d_}E8?tB9z{FRx(Hc}LCZ;M8S zLe`g6G&Ek)zlQk2h@qVa4gn!uK#iEJsF#FnDTY!po)plB)q zMbiiCKK+!A$iV6uRDk7k0HUUL*2q?OOfTFns6kSO`(L4f*t|Fjl zJ^@8n6Hs&w0YwW4C|XGH63-!wqNt1X;dDe7-Oy)6obtS_r*X~;V~TZ*pZd?~t~ zEk!r5rRYYs6y3y@qGfC;TF#cDo7qydf-OZW*(h2?K+!D(6x~Wd(P{#UZX=**4FN@K z2`IXqfTDE-6x~5U(VYYo-9CZOmZ0*W>eP;@T=MfVX}gG;1nhrO%)a42MbSw)YByoPh7=n2l3q9@r>^b}i)o@PtYGi)h( zmMulkv8CvFwiLajV^SBcSLF0*c-wplCY*MLP&6+DSmsTLcvCBB1DP0*c-tpy*wKujtW`+ur~Qe`f#R z*vF*kI(u8RI~20MtfCJ?Uco#m+Qa!$^buQ%K4weNUbYnNV@uH|Y$@8$mZDGDQgnbV zMW3-z^f>`VUl34qkbt5u2`KuCfTFJnC^|$y(KiGXeM>;mVFHT2BcSLA0Y%>vQ1k-< zML!Zy^b-L^KNC>&3jsw(2`KuNfTCjr6#Yi<6}=yFZ!?65&=bJ2q;P>peTiaqErHkA_Npg z2`EY1-*g#g?MlY$>Y4Mp0b?is}(ibO8ZH^$93yKtNGL0*Wpqpr{c6 zMU4q4${?U9lYpWu0*bN;D9RzAs0jf@O$jJ!MnF+>0*YD?P}GuuqE-YHwI=wADkiw; z3yh*S?RP*bCHRl@yV}oaZ4yG(msNC8g4b!06m{TyDeB0UqE2in>dcm+E^I04%9f&T zY$@u_mZBbPDeB2aQ7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVAOea86HqjSfTE!U z6b&PwXgC2y7ZXr4f`Fot1QcCDK+&ZH6pbRF=rRI|E+_bk+9kN-4Uq6;3#Yvl9kaJZ zxd|cb%PJb1;9b91ipFui6y>v}XgphrCa|SwB3p_kv88A-TZ*QzrD!T!il(tqG@XE= z0s@L=5KuIefTCFh6crLsR7610Yyyhr5Kwdl0Y!5OD7un>qIm=qT}43Ad;*HDCZOmV z0*V$8P_&SMqD2H0T}wdGVuG(IFTs7%00~FzU7;~j)W(upk`S`KtfCtdy!V$%(T$uh zMK`gfXc=3Imb0bkX0{ZqU`x?TwiK;mOVKTCDY})7qSXWx-9|vs8Ul*e5>RwI0Y&Qw zD7u4yqB{vFx{H9K^#l~%O+e8-1Qcx`py*x#itZzz=zao<9w4CTK>~^%BB1DD0*W3X zpy*M8ujsl2_k;lwemY>_TrWk9EUCv5Le`g6^i+aZ_68|>n)9XT8MYKX%a)?&*i!U7 zTZ&#_OVLKQ6m4Ql(Ti*;dWnsq%>)#^OhC~V0*YQCplB-rMXwT2^cn$0uM<$Tjew#z z2q=1!fTHaL6zw3OXeR+hZxK+mi-4lH2`GApfTDK^DB4Xx(R&0Gy-)BJJ(1wHGC;!p z%?v&%MN92xv=0(O)|XZEae_DUCMnv>`BJoxEk&QOrD#7}iaupa(E+v;ea4oe&)HJ+ z1zU;^vQhLU0YzUCQ1mqcMTZC|`i6j_ZwV+mOhD0h1QZ=1py+!7ihdxV=tlyIej=dg zX99|TA)x3e0Y$$OP;`udqTdK8I!-{*?*tT`Aoz;*B)HcYAm+Ph2F^!PRK?!aKA8}* zzO15C3Eqa~QgoX0rRWS>ivDIx(OI?>onuSUKWr)bmn}u-*;3>r>T$ai1=uKxBcRA7 zpeRT{kw-vLJOM=^0*Vp{C`u%tC`>?65&=bJ2q;P>peTiaqErHkA_Npg2`EYWq*-})CEk(82QdEa6MRnOyRF5r17qC%OpMatU1QazSpy)yZiW(76)R=&x3<8QW z2`I`UpeUPwq8tK>nh;Rblz^gU1QazVpr{1_MJ)*^YDGX%YXXYe5Kz>XfTDH;Us07r zH@wm)xlgS(O?3Kh7eFRlz^gP1QZP?py*-( zibfDnG?IX#O9&{slz^g91QcCHK+)v{6y*|7G@5{-Jc6&NL!vv-010omH$NSvs8;L& zTVlxivWmthdNWr`(FD$yqKRxNn#7i($!sZ_!j__`Y$=+?mZIrwDJoz~(F`_PacfTF7iD4I_|(bWVLT|+?80s@K_5>T{= zfTC*&C|XQF(GmiRmJ(2O9l=*LF40|UfP~xIo1c6ss%Gvc1+PyGSzlJsvPAEtHBz*k z^QGu!wiK;kOVLWU6s=-Q(JgE#x|Jv zT?7=ZC!pwV0*dY-plAaDMfVa=bRPjl_Y+X`00Bi05>WII0YwiJQ1l1^MUN6t^cVp} zj}uVz1i@EyW1@S|010<9GkB8}^{@~7pG*u{UslnxiQYfAOVM+jFGbI@rRW8=6m4Wn z(I&POy~viLm)KIYnJq;xv!!SY8%3`WP_&hRqE`thdX0dh*9j=vMnKUU1QfkVK+$#r zigplCw3C3Mw+JZOML^Np1QfkPK+(Gd6zwLU=sg08-Y1~w0|JUZB%o*y!B_NjqFZ~N zQS`k1LgO=1)W$wW`zSGFeOX1HBzj%$l%oBdFGZiSrRV@#iaujY(dTR_`hqP*2ia2e zC0mNVVoTB2Y!n?Lpy(R{ioPYF=r93A-w{xBgn**&2`Ku3fTAA>DEf(jqMr#U`h|d^ zqXZQFN7C|x@;+`$CjcC*iuxVEkzC3Qq+)*q6-NqYD7R$V*-jY2q?-VpeT!g zqHF?+atJ7DLO@Yd0*aauP}H1&q80=cwIraZ6#+%92`FkqKv7!)irNuS)SiH%iwG#{ zK=2h+54(RDAmP*Y=BGy3f24oFj*j7w^<@=x4SVJ9lcH{%FGbziQq+SjMLpS4)Qc@e zz1dRKhb={Y*;3SxEk*s=C>lUO(Le%<1`$v+n1G@o1QZP=plBEYMZ*awx|o2X5d;*C zB%tUL0*WprplB2UMVAr&4{`S$9aY`8ZGTVp>5Y!s~~py)aRimoT1Xbk~HHxN*CBLPJ> z5m0n90Yz&GC|XBA(Ru=kHV{yB3jsy95>T{}fTG(7D7u}1qB{sEx|4vSy9g+{n}DKw z2%(}&t6mVlz?2q=15m1y%Kv5n6Mb!x?szE?eO#+H)5l~c{fTB7C6xAi5s2%}D z^$93yKtNGLLa6AkxWCE)iSM%eqJvU&jeA}6(5#sGGDU}H1&`e$MMrSH6g6f`(UEK^ zI*KhtN3*4<30sPeVN21mY$-a9Ek#Y)C~8JPQF8){3J54_K|oO<0YxndC~8GOQELK< z+7M9GmVlym1QfL=pr``@MI8w!I-Y={P6QNnCZOm90*bm2P}G%xqHY8fbti<1^0WMp z9FTZh`>JE3tniusCc7`{krgvvrs%}1;NSbCs1N5$QD3$c^f3_42U`x?JwiKPj zmZCvyDH_a{qLbMu8bUzPPy&jE5l}RofTB|fC_0sZq7eiXokl>>=>!y=K|s++0*cNg zpy(_Dii!v*8bv@+F#$!R2`CyvK+#wNib@D58b?6UctWVCSC-#+lT%dJz5~)*iY{@l zi%!UjnJ-f`B`fIlfD}#Td?}j7mZDO&6isJK(G0c}&16ea8C#0V*-|u%Ek(20C_0;f zqB#T<%_X2{9sxz?5KuIqfTD8=C_0aTq6GvLEhM055dlT#6Hv66fTAS?6fGs7=mG+Y zmJv{NApu1f5m0n70Y#S(P;@CFR5U5epX7kVXV|y#Cri+|^RgP;?ssMYj`BbO!-NcM?!^7Xd|g6Hs&y0Y&!` zP;?&wMVknrqUBlseGW+cYx@q!3Mm?ApV98mikUA{^l(=2`Xf^G2wiG?dmZGQFQuH)iik@Lh(PlP^wh&PCECEH&5m59z0YzI0DB4Cq(RKogULc_8 zMFNUmBB1DH0*ZDJQ1l7`MXwT2^cn$0I|(Ryoq(b@2q@Y`K+$djiryrk=q*C1=)o-i zHwPr%*5EuOMUnIqwyc=>GDYua1+^cSq7OJWIPAyo8kmfy(%iGOKdb$m~X&M;C3 zvts7U6nTl@%qOKNlF&1GDav3=kRfTBYQC_0RQqI^QA=$|bAdfXNyx5*jF9< zN|F7AGttS3nE5hArHP>6IVqaX`BF54Ek!fgQdGv4qH?wr&0)fq@RmYW5^s9}B5;5~-iXKY@Pi&W>$2nh$o?uJSlWZw^ ziY-M?v!&=6wiInWIO0Yz^UQ1lJ~Meh zJq}3xdb|61REiFDuZzByh?y@_^id*+yd*^*bG{VqVN1~`Y$^JbEk%3TQuG;Hiauvc z(HCqf`jRb0U$Ig2H33E65K#0j0Y&==DEf|oqVEYP`hkF={R9;KNI=m~1Qh*DK+!J* z6#Ys-(QgD4{Z2s90RoEtAfV_^0*d}3py(h0MSl}e^ba9a^g+Tu$^nTVWnXptP>KfI zGyQ)PG4o}L{OsVw9a0p{{_ivWfGtItY$=MdrKlQPiVk5*QJgJBS!^jvu%#%QjiMX^ zijo8rr3fg>C7>vefTHRI6xAT0s3rkLwFoGxO+Zl{0*dMqP*jhAqWT0BH6WmRv)0Y&))6g48C=x_pxjv$1JBH8{F2PD4D;ACWn&(W&8*F_s=$IO>0YLXpX_No*e z!}+=|I+iU($FZfTDO-w~v8AXvTZ#(UQq+PiMTKlBYRN`XD*}pI6HwHKfTFep6tyFu zs67Ei9SA7uNI=o?1Qc~5pr|teMJEtY)P;bet^^cyBcP}|0YyCsDC$W-Q7;0DdJ|A| zA^}Bx2%(~*vi(ZvK5 zT|z+7r34gRMnKW!1QabNplAgFMOP3|bR{8FG(Fot!2yZav9CJLkfIHCU$iniX1+|( zwb?<@n^Lrj^QCAtTZ*n@OVRagDO$spq8r#!bR%1eZemN(&1@-J%SO>U0*clXP_%)7 zqFV?kx|M*UjRX|kMnKW+1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?ldg0*dY@py&Yt ziXJ4O=ph1%9wwmZ5kjcw>TG|B0}_A9zUp|56n$#X^dHTRnJ-iHWOi`N+fwut=S$Jk zY$WIS0Yy6rD0-cMqBjUA+C@OoZUTzlB%tUm0*c-ypy(X}iryul=sg08-Y1~w z145|i@ofJk2PEFhzK#Ec6h#wme3%_GU#94j?BLsXrRY=6m!iFFDf)~pMW3^!=nJ+K zeaV)huh>%bHCu|lVN21sY!vMypy)dSioPeH=m!Fd_7hO_BLPJ}5m59q0Y$$MQ1mMS zMZXbH^g97X2M8$ogMgwx2`KuDfTDv06#Y#=(LV$f{YyZRm!l`Rc?1+yC!nYX0Yx>JU&=mw=*r1QgXLpr`=>MGXlkI+TE- z!w4wKC!nYi0Y!%sP;>+VMU4q4I+B2*qX?m*XpVo10}`)iaDtrhnZA3Z?VhmZ#LSl| zIxZ(T`y(l8%K1{%j4egY*-})%mZBDHDJo=3QA@TIwPH(AYqk`%VWX%m0Y&WyC~8kY zQ3nEwIucNHJOM?W2q@}IK+y>V6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)ok&1Y z9|DT{5>V8SfTI3{P|-0t{u&1)zQ?}mc&ro+Hc|s}V&=;f4bBOk+9O3LbG{S}VN20a zwiFFxOVMz)6rIABqEp#YG=eQfr?I8zbT*34AfRX@0YzsLP;?dnMMVS@jUu3^n1G_u z1Qd-SplB=sMI{6jjU%9FJOM=$2q>CJK+z-uiY60KG=+eosRR^FBcQ01fTHPyP|-;_ z{-+K|yq*2N>p@a{(amfrTFaKAb!;hG&z7PMY!ux> zK+&xP6m2A+=r#h1ZYQAV4g!kqB%tUn0*dY?py(a~itZ(#=sp69HW5&CKLJG#5K#0W z0YwiHQ1mbXMUN0r^e6#Ej}cJxI3ZNDD#xGZfW(*BR~=VN(c5-k^h8d~e3_zWa)RYw zO3`M{m!d6fDSDPIMbELN=y|pjZDmW*HntRPXG_rwY$OVQ_?FGXLlrRYnx z6n({(qOaLf^bK2zzGX|%KDHEn$Cje+*(myffTH~b6#Ym*(N6>v{Y*g7F9a0*Nine0*W#SDDnv?iV{La zpXT^~Iw0|F24}An?KM(CGG@L^(ILs8{yr&+bG{U1v85=%mZEI76y>m`D9M(h6kCdN z*;16pmZIux6xAT0s3rkLwFoGxO+Zl{0*dMqP*jhAqWT0BH6WmRv)0Y&)) z6g48C=x_pxjv%0@F#$zK5>Rv$0Yyg>P}GEgqGJf5qFB=J>VU-8+e4vh$?%!}%|`0j zWXyb-qUOn<_5Kz>WfTC^$6m=({s0RT>Jqal4MLPJ9Pe*%gI5KuIbfTEKKp`xZq{{jajzT2LoHIt&iNDWHH%$F$|nhZAXm!e^uFGa)I zQgjMiicV!q(FnE_oyL};)7esV23v|ovZd%uHj2(7ps0v|qEQ4C6%$Z2nt-A)1Qd-W zps0j^qHzQijVGXJ0s%!62`HLGK+$9Zilz`yG?jp&X#^CN5>PaqfT9@$6wM@{sEiOQ zIyvd@a6sY{>}%IUq^ObI7nLVt=F1e#Ne18jBt>&MUyA0jrRW^C6wPN#(Yb6XI*%Rvz0Yw)RP;?0aMVAs#bQu9f zmlII5oPeSg1QcCCK+%;16s;tn=qdt=t|p-98Ul*0C7@^(AyhOw>F53I6z#V!G@dO* z_3df@>SWA(nW7t#L91V-=tj<$qMO)KbTeCu*0QB&9b1alv!!SQTZ(RBOVO=tDcZ_D`Xd~Wcx$^aS|deE?bF-S$(Z>vMb9RK zxxY)%bDS?l&$FdyD_e@Tv88A`TZ&#_OVNvLDSC-5MK80ZXa^fbuMkl5Dgi~W5m2;~ zfTGt4D0+i{qFn?O?Ixh;O#+JEBB1DP0*c-tpy*u!iryoj=zRi;J|LjzLjsCEBB1DF z0*dw!Q1l4_MV}HvMVpiUjSfisaeG>}MT(Z$ebL@z%zT-mFO$JDe@M|+oG(RRv!&=8 zwiJEKmZE)ZDf*5rMc=cf=m)kG?Pp8Tk8BkEL_pEc1Qh*3K+&%R6#Yg((eDHl9U!3S z4+4t*B%tUo0*Ve2Q1mweMgI^`^e+KLUP@2fQ4}GdD1(3^pMat$0Yw1;MVSN?#R#FI z&y)UV4oLj5z`^-KisspUQMFXee3_y|DhLirQ8wpGQ4U**l58nTv85=NEk${3DXPwv zq8e-|s>zn3T5J^6CZMPe0Y!BQD5^(5QGEi68W2#_kbt5?2`D;@fTDZ?iW(76bT|P; zM-Widn1G@q2`D;>fTE)bC~87L(J=%R9ZNvbaRd}KC4`FNDgRgpB)<0$2PZ2PKGT23 zKD{+d#mtu}Doh3a|B<4WoG(SK*izJ*Ek$kEQq-0$MeW#9)SfLx9oSOTku62Xvr*KE zfTGR>6rDgoQ5OP=x)M;-jew%=1Qhikpr|JSMZE|p>PVMWYEQ8bd(QSOSVl z2q+pyK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@D4IqimoA`=vo4bRuNFNnt-C~2q?Oq5GtCR@((&7 z@yYgu#(7c{*nQEORLp#tqMK7eL-*G~r0WIR0Y#q^LPgJ|{0kkBcpJMfdR~gw+oS6*QZe&oioQt&w;v)! z-*Ubb?PE*PcWf#8o-IW`u%&1}TZ(>UOVLkkDf*c$MZd67^eX{HzY$RMI{`%p2q^l4 zfTBMMDEfSpw7DH>bjx#2VYRd!$0A~$BfOi}CHpiPbxwc&gzYRi_Qc5EqX&z7PNY$@uV8KfTF$x6!jyZs6PQk z0|+P@NI=m^1QZP-plC1wMJE$bG=zYnp#&5SBZP`t=K7~QAo0WPIa(_zy3(HZ56_L6 zFH>|{Zg5UYicaTzDLR8KMI+f#bS7Jh&SFbZ5nGBzv8AY(Ek&c*QZ$B*qOk-Nl@L%g zj)0=^1QbmmplBiiMUx09noK~^6atE-5>PaafTB_Yil!4#G=qSmnFJJ-5l~c4K+!A$ zie?i~bT$D+a|kG!O9&O6n(N=}fW({GebERh`rW<+IWIS6zD&`1xxtn^DO$k!QnZjQ zMT^){bUs^(7PF;j30sPmvZd$(wiGR6OVNdF6kS9>(ZvK5T|z+7r34gRMnKW!1QabN zplAgFMOP3|bR_{rD+wsNih!c42`IXTfTC*&C|X58(P{#Ut|Or6dIE~p5Kwdj0Yx_w zLPhg){VyDl_ziaVbFLKqY2&8cnE5hA>vMxxO)1*I`BHQXTZ(RFOVLKQ6y3&_qTAV0 zbO&3C?qo~RU2G}3n~kD-2q?OjfTH^dDB46o(ftGzJwQOwg9H>kL_pEQ1Qb0&K+&TF z6g@^j(c=UZJwZUxlLQn!ML^Nh1Qb0(K+$Fbinb6?^eh2I&k;gJYjgdk4oLh&``!EN zq-dYr7d@XFGhe3Yh1_6ZZ7F(@^QGt|wiLb0mZBYODSCx1MX$1@=ry(!?PN>Q>uf1{ zgN>qH1QhKipy*8kiryli=xqXu-XWmqT>^^UBcSMg0*XE$py)#aiasKs=wkwk_7G6? z2?0f)5>T|4fTGU`DEgd$qAv(2`jUX6uLz-{ZMptT2PD4Vp6PGrzR0~U`gLy1e3_!} za)Xt1rRaOkm!cooQna5fML)8o=qI)m{mho4U)WOgD_e?wV@uKRY!n?Jpy&?*ivA>^ z=r00_4iZrGHvvWe5K#0l0YzS(p0=YXLO@Xl0YyFmMNtBZ0s@LM2`GvYP*jb8qC*HM ziW5+jMLY6mZI8hDXPPkqPlD;s>hb1`fMp`z(!F+0*VeLpy)6Hit-64YD7TM;RF;NK|oPs z0*a0#py((9ijF3rs0jf@#}H6-ECEHw5m3~WfTCsu6g4NHsDOZ?76cR(5>V8V5GqRL z`TsZ|@!Rc7M7eq4GySCwPqbBD%zT-mc6q^Jhe}a<&X=MNY$@u^QGu4wiFeyrDzmeii+7%G@30%W7twOmMujkY$+PY zM$vcziY5?HG?9R!Ndy#4CZK2v0Yy^@D4IqFwOSnE5hAi}Hdy z50|3zIbVtvv!!SWTZ)#lrRV~-6fI**(S>X&x`-`B7qg}45;lr1C7|ds0*WptplCS( zMJos>x`KeBD+wrCNkGw61QcCOK+!b>6kSU|(JBIpRufQk9RWqx6Hv5};E+iJ;d_iQeaEN~CaQ^}LFJ+DUc>ZIq@Nxq-!c@2_{YIt6La(pe%Yn;5hj^{N= z{#?)VnkG9m^t=|y1&4WF>*Ur(p4UE^)!6eoB~L!e^SUOlZQ^-7lOG=Id3};cH1oUx z$%zG?H#m83q2~=t{@Tj(MkJ4K>vX-Ijb{jOX2z{G-J4?n`!=;CT-wmrnA$ zN0Tp4@w_LKxuu@BIeF>~&wD<3Lz(BjklZ`V^L8YUasMR7&SdF4&)c1RXujvYll<#E z&-)=LlQ&)JdA}q-zufZsWaBQn<0`~ zdyBgrA}RaV>>Ec?_RoMW4 zT_Y*`SIv4xQufbM^@*hH-xV4VNqxQ9-6oNg{mUN1A}RZ)8Ae1>_IK-#jHK)@M;{eQ z+23wGHj=Wxo_IneWq-fylt{|{g3#%al>H5l<&l*A6@7CeDf>It=0{TYmt-xBr0j1w zS`tY;wa48;k(B*CBbP=}_7_F0h@|XK`d<}E*&o$j6-n8jwOtcQ*&mj?Ig+wJ?Y1G3 zvOlhLTO?(F-sG-G%KpH>eUX&?j_(H}Df=zEk494VdoG`hr0h4%ZH}bucRf8HN!f2( zc_EUr-*>PhlCp0c?~J7EJAb<)Df`yVJCT%q?frvD%D#BICz7(Seti~6*_SWAilprM z=e|hFoj z@v5(IZxU&fv)pQRC(nzt)o5j}X{T|(PHvyGIQ?dKxnF;g4tmW4?h+#%HD0uHj@Q^} zqm#xEdzYOx{&l~wBPVF=h`Z56W1L-suHmSWEg?$z%-bY9KK$(gxt zz4XDx1vMi>GIMucweXp_H6ufV#LWdi^z>@{*CmbH06lvkra=#GLm*XxYNQ}R~ zPk(n2LE_%mx6Ddk!mfMwZ*Z47G&A@69}g~_?|HQofiv#@3o`u7+LyU2YySmD`f)Fk z8#ywkdX}G4KWBLDTxZquG8%hXStq#Ud44U=&*_+Td{&37zSZ4_UazU84#|LKm5SZRJH~ z>mv15IqsyO@_Hn*-L1Yw-&AA#Uzna-qxTsZ(cC7xL{n_^n$XPV+v*# zm5nJWnm)6%yktyy$=HH1Gv`h(FSRhHWbCY&C1q7!XK(M`xf@ET1^L#4DIk zI<=&rcuL8fg6307#}rQ~D4S3`v!q~V$+VKP;?tzDJq^hwV<#?QLCbsEm{^96}GV0%*AHYN~e`HD=8j5u~}h@=B=99tDC!5|L0W& z6Q_-tGHYx}!PMe06DCgk|NUx|%`L0?kr+Rrpxex`vnEa}?NK_jq*=wsVov$Y^oJz; zhzy=tI>~*^%L;~0FP=HM_pE6}!`#nh{NO3G%8G_`Ydf&b|Bahzc5!)$eY89;yrIX< znl`3I+xE@J7=@y-CF6=`O(`!bpF6#ztoZ~J=5DUB6Q`BC;RFrs(W}T^%`rVnr%o-M z=9eHIiP zYVYtrmmF!7(a`-W9@6W?qTVg~cy=so-=a^^=P}~ zZ7bfYL;5<+npQS({Irs>`3_zB-SyD*D(uarxEJ_o_Nw@K6uK*ue)|sY&5DZL*{xa@ zg_lt1-WezK=F+<9(z;h(g8K-#Hyb-^>eRX6CFyNj^NzbIw5zxR?gLtJ$rbOUHSeQm zTDu*9NcPZfuRjxuiPIVu=^ef#5R_C>;xG;Bpc&9D(_N^+fM~{j#3VZOb z+!fauCZNiF^#84Urk*9EXN~vV-TAcfB}FCE#!f7rRy3t_+W7D%=x!4C?%n-gmD@yD zt##$Kb+>=`<`q9ZptY#{*>$M+nG`z1UjJUF6?N-5#IyI6pZ>r9`1!y2sZF05EAKGV zzw|1uj{9Y!4{^``Tw8BQk=<+RwD2cb`E%|rwAglH(r*Ih3a;TV4ttlq(q~VyUzq7P zZJ~>BzfN=ox>sBkyGKaBQMbzL)Dw2C^tuX%yz|2L6&F=lNgbNVEUdKeeinMyc&w1; z?tH?Zb0y?LCpl~_cx9#S!rmyTBn=GrlL*h_1rw0Ih}JH?edPzweQ3k?*phecZXqtWl0ab<1Mc<;PbsXpGTbVK-Sv^+ zHtA6DChnuHi>5oC>?O#|0K$RQ5t-B(XzfQP&bswtm`q``Pg4~gx zkh{j|#Et0g*z~Ga6(2(Pf#A(68E^}816SOr?cK+(w1RHsZNeuXyUWtWxpTN+=P~>c zx_6s?!F?onUBy*$@5?p&wKmK>dePf+qPsoP#ct&E=d|!sS+9z--7TO?th@%?#_l7e z*Hzq>?j{J|L!}LOXXV~1ec|a>x!YD}xlc8Esp2Q%+=b`6duzMfoEd&p3d4gw&sJ(E ztmIH3uu_5h6z(p+Y(nYG@`}%z+;k=^eWO?0-W8wU-7lK-b+FqcEy#T|!WXI#sJzJw zD{u3{${U?qq|ja2^vUi4K>El>ywLd#FSW`IT6z1qcdn03p?k;@zM=c|sTV3fgoWX) zYge<%XMjST;cnH+53qab#FK{S_vp|e-<~iuFU+^63@zHXY@Od^X33P2;qqD!pAqw>{fTnJ~5O}ES=V@%suvZ$1>N(7MB-S?C?Y39wUS=RFW;M zG;19H_h-NKjT+*u`l+|Vp0k_2%*w}#rqRx-e8^b&K(R0cp1x3b->j=uc?*TgD?a_E zQ5O~c_me)4R4X5-!p0t24eC8K{mDH2E_hs8`53eEp=ISGOZONRKH;wdJGa6yk4h^a zFjjfI$b-_#2Z#KEu*Zwx2SyOX2ZrgZWsgSn05$zH41d*C{H*y^R$&>+_Na7n#T_3H zJ}Vy}Rz5xib;T`S@$j?aab?9r$SS{jDt`@BJ^jVV*VNG^W5>G3-otoqp8h4obM9mQ-+w{5FC`@0fB(84?kgDcbKF-}>?;%%Kirec zZaH-pXD$hrMlbM}Wn3Qdx^-}`Ew(52UZlXi7_@ITu=&7leNXZ-b7KP!@#EFl+n^6_?~_Jrt*jHxv$Mv`QdxX zD$6eazt_h1Qvc)i)jju>weV-@eyVxy`W{*3E$ppZ{g3^>p8Pj1_ZpA=pAS|4^Ki;( z|DTWT-5-5+mmAOXyxw+nU%;BJZ6A>g`}Tt!-A~Vc26n8eV_iGC4?`n6x;JW~ZVv42 z+;9X4duX^n(Xrks;XYc&Q6s`VRmWRT5BCE)?i(5I zKXhza6z(oM&M6M}QXQXm(Cy>#vX0Sl;m*~u--K|Vs^f}D;l4q~x2A-9uZ|5$!+ng7 zqi2M>RL9%O!u^nr-_Hv7Upls)6Yg$0&YKtRWjb!2AMRIl%v=!e>N*Zs6zymE24 zZ_@FdrQ!Zu$3rg+_i;Loy*S)6biCuza6h8s{>#Jtw~lSE2zL)1=dTR+MLIrvb+}*C zvD&I|*VOT(>%x78j#sS-_gWp_bKlvs+viIi^Vf#EnU3Suhr3M2yKV{hV>pUZwhy99S1)U?lX0~=Am$}*YSf#!u_?5hd&*_dUN4Sf0T=i@Yv~t@Yq+!^FIpravfjT z6Ye*4%-I|6`Z^B#Jlw@PUiW3VH|n_O>u`Uk<5By<-AczP--mmyj`!~m_cJ;kaNj1i z>l^$W9#8l+JoeXd$?xI5LdTcfcTnx^-_|j8Fx(AwJmsHokI`|Bd$eG0f4h#Ky6>{u z{z1nk?hE*~+vqqg7VdL&e9(OZ)?U9w$3NY7Vr|FVABD1GSNAPhI}X(G0{6XH+beb4 z;l4?0`&}LL+;?kjAEx67_ibC-B|6^dzJF``P8~mU-^jK7qmIYA@95fYr{nbeaG$H= z!|r>$_WI{^Y~X&!gzaN=Y+=X1^SWpc(D5`K$LUz6<3b%T)A2eTH|qGHj$3qmRmb=3 z=-yAteZSR?N9Z`rj_&%5(6Ly@5*;(`aZ5FKo*mtJ_QQ_u;Y#{gW{+dsb`K}Kj2!pd z3)H>lWpk&N7ms$w@|odr0x!8|zU5wXd#dR*A6-`FHFr;rn_F!D->+Dv`&j$>uKS|; zxKejY`sL!$qi2@P4$o4VX^#+fL1FseWr}@wP8Z>>iPwCL`&Lqk`%-_EcQbBg@l^Ll z-G&ToUR+*2bK>Y(gBC*mp9l2yFB|CaCyVr%beq0^wu?rxZe+AFNHsN(LJR2 z&)fZTOvKCA+t`7(8|_}M`hNHIillwo`?b#dom=G`_o8>`vEkd<%l3oIo8?}vdU*${ zT%J8+;_@!3a*lh^Ywj-Z9d5)buUqC`u6lWi-jVdj)vllWrB-oy*XkU*{p?4kdxCjF zB7E8Y->#qiw@ydiu4l)H*UvS6@OJmQz|YBEx5B+0=h(KNhyA$I{a5w+)o|A@<(gf; zT=yS8-zVM6?x#219nwEGyUXjya7W&k9kFe%KIq=AtBW<=%UqsazP-;XA1<$x^U~Wj zesFnqPSv+-?5^Jq-pCz!yQ<$u?$Ernps=0$esYVJ?OV3WcV91PQCQ{w+qP|;pWnW1 z%QkKE?Z>G2f?fl9hrbaayx@p?CdlPlsWvdZg4XF*H}UGaUnvJ3D(zR=KiWIHcWIx} zzW@II&%dQ7mG<9u;Q1DB9f%fs$Nlx5mv41)|A~XP9q=Odnz!|u@qO$yOL~v%Kfd4i zz7zUvKj3Y#()XwQ$e{fTXO8VZ@}%tt_NCl^`P={3C3gQU=AYU3%zi_;+|;%Md-7Y2 zI)1`+k%PMj{jz!Fsr^Uv8`1YPcexEV+vT3xzmL1T4HegH*r4J4PCamBi(!4;H7lIl z;M4<0v>4LIUcNK^vc2?e#Y+SG+huh9>8Y}|{kFMFc|$*o;~Ls|z570Emyv$iUb@p> z8rAKm>eXXy-23ocD|Y`yo;|Q3byVN#qp~JkA70DBU4JTW*}i|HfiDzqIS_5M#a;57 zy5z$rwCcb0fY+#aLd$;cn7ejDVIMnwGQs}8ApOyHXBRf>pXXj5&D~n%TAlb?!*2N# zoAkH$IclQ)|IO+D-;@6TXWd72SMh>t%?p~LZ@bbOLqNWobAF=C;bx)6fy-&Tj zhTk}$bL_7)`6Dm+w!z+)i*A4Z@rPfZ^1zp^dnFcn!MtkThgo;jy<_X@1yh%oEZMa3 z@bX}u)1N=eo9FKP!e58c$YCxeI>p>?v8(#4$AQa;WG=Jk_mOJX#oZwz@ZH^VMn-I< zi+(K!Gh<+#f%bOMprLz>f1AD4pt_^dDOST)wcus~;4h zexZ8(@m)X4_rAuG*Ql-Sz9H9oTl)ue)~Cw!3~kwB45kySH@Lucvl~+pXO7 z>!lsB?XF*MZFl>}qtV9xZg=}Gr)nc)gf>D>(?-bY+6XyA z8zCdL5pt$BLeA1gNRc)|Mrk9YSQ{auwGlE#8zE!05mKU!ka5}w8Ly3y3EBvmsEv?G z+6bAf9SZ5||K@K0tRhpo@uS^S>p;IMfrly3HX-Y`Bri9GW zl#tn)5^}btgv`;Dkhz)?GEWmB=V&8jzBWS6)kes9+6Y;ojgW=f2w9|!kn^<>vRE4- zOSBQPR2v}|Xd`5qHbO4cM#x3l2)S4rA(v<)4{9UiA?;AeO24DK{j=KIeaKaz zkahO*!!eU%LLPU&8CpV~(5Vvgq^5*Cr70m#Yf8v7ni8^EQ$n_AO31UC67rm;ggmc_ zkgeJX*`|$)Hr;LmMHx zv=Opf8zFCMBjhb@guJbdkax5Z@~$>Q-qQ|+JnD~hw|`c)-G@9D3K?pTN#2i{924?! zFw#B4PTz;@(Ww&hiKc{nswp9RH6`RTO$qs2Q$oJbl#nkqCFCnj3He$RA>U{tXM#xXv2>DqXA-`xNDwZA^&J2vilJC{ZymlWk;jYNMPS2 z&9P@QK}2UC=C*s-o5?=ZZTGM|#%}1gdstqL-N0@4u>25qeYf4i@;JMm+wNg`7Q3$7 z?qPX?UB_+rusoYx+imx-JcnJ&ZF^pmB-FIvu3?H$!-BhtxrFK#+;z+&^^l9n1MrbR1iXnzE&+ z8C!~)v!$qjEk!NZQdG#6qLyqaYQ;uTYXXYe5Kz>XfTDH;6tyRyr~?5-9SJBpo`9lG z1Qc~9py&hwinl#ZQ3(M> z;|M4kPe9QG0*WRQP&A2vqR9jlO(CFYDgi~)2%(|@5&vWdB=Mk|(ScIb$4He%V&=;f zl|=&kZ9Hj3<(w}?v)EEJn=M6Wv!!SbTZ-ngrDz^oiq2t6(R{WPoy$hic?1+KAfRX= z0Y!@lC_0~jqQwLhEg_(2DFH)0q-Pe9QI0*Y=Spy*ZtiZ&8ZbQ=Lh zw-Zow2LVNQ5>Rv(0Y!HcP;?IgMfVa=bRPjln+PbnpMatV2q=1xfTD*8D0-NHqDKfQ zdXx|R6QqhkhG4o}LK8*zS8%@)S_Hw=yea4oe&)HJ+1zU=~WJ}RkY$^JhEk)n3 zrRZC>6zyZ9=sN<6z9*pQ2Lg)r6HxRc0YyI%Q1mkaMZXYG^eX{HzY$RMI{`%p2q^l4 zfTBMMDEfm`D9M(h6kCdN*(k~* zpr|?lMKuU0s!2dmEdq*a6Hru#fTFqt6xAc3s6GKj4G1V|NI=n{1QZ=cKv6ycMU4n3 zI-G!_BM2yJOhD0*1n!HDBB1DKLa507#Ub}PAc^Jn1;xya@R|OPc3;#aBWAu#QPYgT zep7o|Q8Uh$qULNVDqu@d3$_#$vZbgcTZ&q-rKmMqirTQHs4W{s?FcApPe4%z0*X2k zP;@*2MV$yJ>P$e<2?P{%A)u%$0Y%*iDC$l?Q4a!&dJ<67i-4lu1QeY}Kv5q8iuw{z z)Q^Co{sa^aAcTsJ&G3J9Koa&_x1z^Mk#EoR2WG^~mnk|qBd|XTkybQ>^QCAgTZ)FU zrD!-?icVom(Wz`H8o`#L)7VmUI$Mg)V54Xx0YzsLP;?dnMMVS@jUu3^n1G_u1Qd-S zplB=sMI{6jjU%9FJOM=$2q>CJK+z-uiY60KG=+eosRR^FBcQ01fTHOH6wM%niUwu) z$2%a2^X$H8uoNZjGuq6InE5hAvoiww12kzxXLG(3&0$N?T(%U=V@uIFY$=-0mZEdn zQgj|$iWab?XdxR#iwGz>pMavp1QabHplB%pMHdiIw2XkF3kfK?h=8Jt2`IXRfTBwY zD7uV*qRR;=T24UG3Id9*AfV_<0*Y1=P;?amMOPD0bPXX?RG#54azGM8>`O$mr07Yz zFS<4(X1+|(^%;Tvv8%MAHJmR+H?XDXMz$2)#FnC)*;2HYEk*0tQna2eMH|>sbPF3r zw-Qjak$|Gx2q?OpfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C2q@Y_K+*jK6g@yd(SrmO zJw!m!!vqvPLO{`@1Qb0+K+)p_6g@!*6|K(jw>uz-6%hyLIw?y3la5bj#LSl|+ME&C zAJ$7N+QRu#^ekJ7o?}bV^K2>F%9f&SY$@8#mZBHfQuHEQie6%)=w$+mb`VhX3IRp0 z5>WIS0Yy6rD0-cMqBjUA+C@OoZUTzlB%tUm0*c-ypy(X}iryul=sg08-Y1~w0|JUZ zB%tUc0*XE+plA;vRP=O)pM9KDbhSOxe@2SZ|BTuv88P!^iayT>?2mY+6@9_^QuHNT zioRk?(bsG#`i3n<-?F7>A6tsPV@uKZY$^JIjiUVo6#Ym*(N6>v{Y*g7F9a0*N<6rDgoQ5OP=x)M;-jew%=1Qhikpr|JSMZE|p z>P`(Ni6%FTnDLREMMW?c*Xark|PGd{a>1-)FgDpiP*-~^STZ+zNqo|00 zqEQ4C6%$Z2nt-A)1Qd-Wps0j^qHzQijVGXJ0s%!62`HLGK+$9Zilz`yG?jp&X#^CN z5>PaqfT9@$6wM@{sEmN3azdzRi0>cifFu%j_cK(AF10UY&+=pD%M{J^1N*Bh(u(GB zz7(CqmZJG=DLR)eMdz`lXaQS_7P6&i5nGDRXG_syHj0)IP_&eQq6-KpT1G(8g#;8` zL_pES1QcCDK+&ZH6kSF@(d7gbEhnI81p!4@5Kwd_0YxhbD7uP(qN@ogx`u$FYY8Y? zML^MNLa69$-=FM&B>pxybEIgbk-E;0nJ-gxqaWB`c#>9h6X#3O&1@-J%a)>bY$;mL zmZA-8DY}I%MYpo0Xd_#SZeye9b^?m-AfV_@0*dY;py+M_itZtx=w1Sf?jxXR69Gl{ z6HxR30YwiIQ1lQ1MGq5D^aue(j}lPy7y(6(6HxR70Yy&|Q1lc5MNbn#MQeP2lLM0Y z)D+zyMc>$X#*djVQ}mo4*k6;AR`fjQOVL)g6m4Tm(RQ{Jy}*{D7uizu5?hL1W=qiy zwiLa>M$xMT6um}3(M|%2UMHaF4FZaG5m2<7fTA}ED0+*4qPGbsdWV3bcL^wZkAR~0 z2`Ku2fT9lxDEf$iqK^qE+CxCmCj=CINFGb(5rRZC>6zyY6(RXYq`kpOCKd_}}KU<1^WJ}RcY!v-WK+!J* z6#Ys-(QgD4{Z2s90RoEtAfV_^0*d}3py(h0MSl}e^bY|={}NE-et&oPv>ine0*W#S zDDnv?iV{#15Kxp!Kv9f zIh-#=NwyTF*iw|smZChi6jf(SQ4O{f)nrRiEw&WZW}~PM0Y!BQD5^(5QGEi68W2#_ zkbt5?2`D;@fTDZ?iW(76bT|P;M-Widn1G@q2`D;>fTE)bC~87L(J=%R9ZNvbaRd}K zC7`GoAykwV^%pxJi79qpl!%7U^yk@UwC2&6`7%WV8KfTF$x6!jyZs6PQk0|+P@NI=m^1QZP-plC1wMJE$bG=vZ;Y7zBcbU+e| z-HaAW(Fb;4G&CABU#95PXkdT+U;4gi1m{c9X>2Jvoh?OYu%&1uTZ+zPOVL?uDJo)1 z(I~bQ6|+$^nt-A)1Qd-Wps0j^qHzQijVGXJ0s%!62`HLGK+$9Zilz`yG?jp&X#^CN z5>PaqfT9@$6wM@{sEmN3asrBG5l}RnfTFVrp`zhYKiShM%CPT%oFYZj(@)rsbPHRGZe>f+Mz$2)#+IVn*-~@|TZ-;vqv$RIitZ+$=pF)!?j@k;J_3q1 z5m0nL0YwiGQ1l=HMGp~B^e_QMj}TDwC;>%}5m59v0Yy&`Q1m1LMNbh>^fUoQ&k#_w znSi1#giz5f&B%wX+_&PUy5E}OVNvLDSC-5 zMK80ZXa`%0USUhot86KHjV(nx*(iFQfTA}DDB49p(QX2Y-Xx&tEdq+(CZOmY0*c-x zpy)jUiry!n=mP?ZJ|v*%BLa#(CZK2!0Y#q>Q1mGQMSBS-`iy|0&j~2{f)FZtKI(ts zfFuUmC$X(k^rVscG8!{qrs&&fV1KP~TG2kvm!j|3QuIArihf{A(SEiR{m7Q0pV(6L zGh2#&VN21kY!v-QK+*366dfR-=nn#l{v@F2F9M1V5>WIv0Y(21Q1mYWMP8t%?I?;6 zP~?7(Y52q*MLq#VQ38qr0*W#TD2fqKRE>b5LkK8}6Ht^z2o-%D^^bNy66@XH>k<7% zifYs3u#AYO$rLHd~77u%)OjTZ-zj zQB0*VRrT2Wihm!fuTDQeG_q7G~+>d2O&IxCZK2t z0YyUzC>lmU(Qrbjs8!%U;D99BS95S$OVKtPrvx$cWr|J@0{e^i(~8dEd?^~qmZCG+ zQgjwuii+4$G>R=n#cU}W&6c7uY$+PcMo|d?MdJu48c#sc1OkdC5>PaWfTGC+6ip$Z zXet3k(+DUkC7@_J0Yx(iD4Iz?Q5gY6fC)2`IXRfTBwYD7uV*qRR;=T24UG3Id9*AfV_<0*Y1=P;?amMOPD0 zbPWMT*Ah^)ih!ck1QcCIK+*LC6s;kk=mr9cZX}@SCPJv_+`#YRfFwrP)3WoV=z!f9 z-5kWsmnqs11fxbs(Jh=WMYpo0Xd_#SZevT)?QAK!gDpjOvZd%QwiMmXmZE#uD7u$` zqWcIa+C)In{R9*}KtR!h1Qb0)K+(el6g@&f(W3+uJw`y$;{+5vK|s-y1Qb0*K+)3# z6g@*g(PjdQwh&PCECEH&5m59zAyl+3@RvFuiTU}fTA}ED0+*4qPGbs zdWV3bcL^wZkAR~02`Ku2fT9lxDEf$iqK^qE+CxCmCj=CIN7C|x@;+` z$Cje{Y$8(YED2=0RcrV2q-Efpr|DQMXd;-qTEdXR0kySsy({S%M73C zx3;JKtutfh%M`WG4D25-ODpQY`BK!8Ek(z(rKl5IiaN8U=mfSDbzw_USGE*&V@pwY zHi~)>P}GxvqFw|P^(LU`L;{NX5Kz>YfTDf`6!j;dXaE640|_WPiGZR(1QZP>py*@* ziiQwSG?aj%VFVNnC!pvQ0*X#0plAdkRMa-pzrg`XEU`~w?WAa%{eh6vGGpe;6rGtF z*gtufR&*BUOHmP9ibk=esF*E9quEk4hAl;7*-})(mZEWNDH_j4(F6jDCK6CIiGZTX z1QbmnplB)qMbiiCKKv5Y1Mdbt(%_5*^HUULv6HqjVfTFns6wM=` z=o|uy<`YnKE+JHOMy9{l0ZDAN-(NIRidNfawDU4!=F1eFpBdOcl$chunDeD*30sPm zvZd$(wiGR6OVNdFDY}R)MHjQB=n}RRUCKt$WdsymPC(Ie0*Y1;P;>q4FN?r5Kwd@0Yx_vP;@f^MQaHtT1N;K zEzI5`U#4hdW?=ukW?Ip0oG(SUv!&<`wiMmTmZH1ZQgk<4 zitb@c(YAwj2}RX7Uy7=;rKkp5ifXc@s1{p_ zYO|%N4qJ-qvZd$*wiM;CQB;qBqWT0BH6Wmc*C$?rbUQ!Iq+)Y$@u+ zmZIKl6!jsXs4oFU{Rk-PPe9QC0*VF_P&9~uqQL|d4I!XtC;>&o2q+p(K+y;SibfJp zG>U+t(F7EYA)x3K0*b~GP;@E*MW+!^bUMLT)FBdF-R_IVMIz?Q z6itYP?H`*@C@SK7DVoTZqDgEin#`7>Vzv}bVN20ewiHccOVM<;6wP3x=u85NW)e^| zi-4lp1Qg97plB`uMe_(KnomGc2?0f=1QabGplBfhMQ0IEw1|MB#RL>BA)x4N0*aOr zP;?FfMduPww2XkFao}_k$CPR&%}- ztzk>i1#Bt0kS#@P*-~^7TZ-1PrRZX|6kWoWqV;SPT}nXF1_FvMBcSMV0*bC6py)~h zimoD{=xPFrHWE;D4FN@)2q?OifTGO=6kSI^(G~)Vt|y@A1_Fw<5>Rv_0Yx_vP;@f^ zMYj-qMJpn~N(-H$t!{=^O3?@QQ2W+M#C(~eJ0juMi=^mI&X=O?Y$>{nEk$>;rRW~E z6y3{~qWjoVbU#~)9$-t+gKQK%L_pEQ1Qb0&K+&TF6g@^j(c=UZJwZUxlLQn!ML^Nh z1Qb0(K+z5Yik>B)=s5z4o+qH_1pie4q4XeYr}v@H@m)d7iq zWdCpM?L02BhuW`2BIe5!y%`BFSt3QdIbVw2VoTB6Y$!x-2`I`SpeU1oqAUW6 zvI!`P5l|E-pr{f7MU@G@qJxp(Hx5YjYWu3=Z&FmtNL5LRm@iXQBPE=?Op0o9z7*AB zOHpmM6xCr%QC+qaoxql&9JUnIV@pwewiGpBqo^SPMU4n3YD_@Ui3AiiA)x3a0*aav zP}GcoqUHn?wIHA}HI$Mfnu%+lswiL}|OVKPg zie?i~G>3qqxdar=BcNzL0YxPQ6qOQCw19x3g#;9xML^La0*V$BP_%@AqO%DoT1r6C zIRq4)OF+>w0*aOsP;?#vMduSxw1VI(DoP1H;($bJ+C!m~MVGLpXgynsE@ey62DTJk#zxWQ1QcCCK+%;16kSC? z(bWVLZ6u)R8Ul(o5m0n30Y#e$D7ub-qAdgzT~9#K4FnWzC7|d=0*Y=Tpy*}-if$pG z=vD%XZX=**8^Kq!Iwkmz0}{PE;NYy0qBchA_LPYEGDUZ#gzH`)MR#+)6y3v?qI=m= zbRS!a?q^HU18gaJkS#?Iv8Cu?wiG?WM$w}L6g@^j(c=UZJwZUxlLQn!ML^Nh1Qb0( zK+z5Yik>B)=s5z4o+qH_1pie4q4XeR+huMtqRi-4ln3BIB` zQ-VDmkmwLML))b&W*^bsNQsy)Q}lL9c=B2)dWZ9+=v}rHy~mcK_t{eP0b7bbWJ}RU zY$@8qmZFc@QuGNMMV}H-^cev~pA%5Dmw=)#2q^lJfTFJmDEgX!qHhQ&`j&vA?+7UR zo`9ks2q^lIfTEuWDB4Fr(a!`F{X#&|uLKnBC!pv60YwK1zM|bJ!3!M__l+|L=PfCE z*uIecTS~-ynWEoQ!gs8bqNAKIMSrlR=ufs3{l%7|zu8js4_k`!x-2`I`SpeU1oqAUW6vI!`P z5l|E-pr{f7MU@FCszN|fRRW5t5qw35Q-W_gAklN}?&pXUMQl`0jhHV}R68}i{}L&x z!}(HFmn}snu%#%6Ek*U%QdFNUMGe?e)Q~Mjjo4Dun2n+n2`FkpK+#DA6g4HFs2Kr8 z%?T)KK|oP10Y!NP6y+08R6sycO9F~o5m3~cfTA`86tyLws2u@C?FlIAKtNGP0*X#1 zpr{kUS5z}KSY^Fa)Wsf9*Glz2)1Pmnb85tVnWFBg;kFy3s0ZguQBSrM^n|Gy;lFC!lB?0Y&2pC_00HqCx_SCJ<0mMDP`LO%0yzfJCR* z-A^|uYL@tfEj41kOwp9o@Y2hrXe#GR(KNOcO=nBd47L=V$(Ev-Y$=+>mZI5gDVoEU zqPc7o%_E>_J^@7~1QeALP_%%6qJ;z$okc*=A_9sQ6Hv5-fTFVrC|XKD(K!SZol8K` zG6IU06Hs&>0Y&E%P_%-8qLl;`ts^aMr%?d=F1da zlp22SN-0{$`BHQ-TZ%4WOVN6^6kW=eq77^*x{NJFm$Rkl3bqto$wtvt1QcCOK+#45 zimoA`XcGZN*Ah^)nSi3}2q@Y@K+*LC6x~2T(N+SAZX}@SCIX6XCZOmR0*Y=Wpy)ON zinb9@bUOh>cMwo?C&5>AVQTO@2PE3t&CpsY>T93&Z%>VwFH>}HYB*)16y3-9QglCC ziXLD~(SvL$dWbDW53{A{5w;XP%9f(X*i!U38%0kLQ1m1LMNbh>^fUoQ&k#_wgMgxE z2`GAwfTHIKD0+c_q8AA$dWnFdmkB6(g@B@02`Ji0K+$Ui6zw9Q=yd{$-XNgpO#+H` z6MRK?rv_U%AkjPRYuEQk(fjr}+FPj+^JR+OOAQa%Bt`FYz7&1HmZA^YQuGm9iuSOj z=wr4NeZrQaPuWuR8C!}zXQOB@0YzUBQ1m4MMPCt6^fduR-w;srEdfQ}5m59!0YyI$ zQ1l}KML!Wxw2y$Ip9v`Xg@B@82`Ji6K+ypLiVhM`^cw+1hX^P-Oz;)GlNu~>K%%1z z&bw0dvwds!NNU7S*yKv6aUMKJ=3;sg{` zBA}=;0Yy~^D5^?8Q8faJsuNIDgMgx%1Ygn7)Zk+dNc50BF8V`?df2Fy7BOF@=!CTJ zo-I<8!}(HFk1a*@*;3SiEkzC4Qq+hoMUB}~bRt`dny{tlBsPkg5>V8PfTHFE6ty6r zD3^euJOYaH2`DNcpr|DQMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIClgTAiGZTc z1Qc~4pr|XsS5zl0c+3HbCfQ%*SU1i8O#e%}FY1;SF<+*rS6Vn{s}%L-d@1U~mZH9F zDeA|TqW)|t8o-vKfov%n#FnDLY$+PTM$u3LiiQzTG@O8<5d;*CB%o*%0Y#$;C>ldR z(J2HJjU}MyR04`lBcSMX0*b~FP&A%^qB966DkPw20s%!u1QbmqplA{SMUx4>q8@3% z-VR9A{-&Z(Pbs?HMsZrie3_!@Y2hh1Nzn|>m!dP-QZ$n-MYGsaG@C6&bJ$Wemn}u} z*itl~Ekz}46qOQCw19x3g#;9xML^La0*V$BP_%@AqO%DoT1r6CIRq4)OF+>w0*aOs zP;?#vMduSxw1R-5l>`*6BA{qB0Yz&FD7t`vq6-PWqN!=YiyV;XM|Sr!O^RN#2T5zw zBIe5!U6K~wev1^X=X@!;lr2RY*iv*ETZ%4cOVJfK+$sq z6g^Ks(F+6=y+}aOO9T|XOhC~q1QfkWK+#SDie4k2XcqxRuM<%81_4EH5>T|8fTFhu zD0-WKqIU?sqWjW<)wVfBe;Sz=rgtyea@Dmy=*D^f-OZ~vQhLE0YzUEQ1lG}Mc)!o^c?|3-xE;u0|7-p5>WIL z0Y&==DEgUzqF)Fo`jvp9{R9*pAfV_V0Y$$NP;`iZqQe9f9U-9TcLIuz5`0DPrv=A5 zAki%QwCn>ZDzOi5f22jsmnr%uEqv~FDf*Z5rRW%2ioA4v<}O76wiG3?r6|ajq7Yk( z!fYu@W=m0ojiM9+ic$$EN+X~soq(b!0Yw=E6lD@nltn;MHUUL30*c}U6jdUis4@XX zRR}1mNqQPhHfqFe%s z@(3u(C!nZ+fTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*Uc{y~ z)SoRy1K3hDkS#@n*itl@Ek#4vQZ$q;MZ?%qG@Om15d;*CB%o*%0Y#$;C>ldR(J2HJ zjU}MyR04`lBcSMX0*b~FP&A%^qB966DkPw20s%!u1QbmqplA{SMUx3ADkh+43IRn^ z3BID<>A^e)B>Is3Fi0OMy2w2*G%Y=1zD&`~^zg6;q-YlBOVMn$6wP5v(Ok9^&0|Z^ ze6|#ou%)P!Ekz61QnZkbqO%AnT0}t6Vgibm5KweB0Yys*C_0CLqH_r-T1G(8asrCZ zBcSMf0*Y1;P_&YOqE!SGttOyo4FN?L5Kwd>0Yz&GD7uJ%qICpc(Tw!q0tX~|wtXA_ zOevaYkFGCHkC-o0v>`ow)k9Kr8RtvUmZFVpDY}L&MVr`C zbS)c2n+Yhoj)0;q1QcCQK+z2Z6m2D-=tcsHZX%%QW&(v z?IWP*X99|TA)x420*dw%P;`KRqJsn!{YF61Ap(jH6Hs)7fTG_CC^||&(H{g9{YgO4 zUj$##N9n=74oLJ*dvv`=ipCqMztbb;%M^Lh@U$nTC=k_W@=}zvSfTBzSin0hO$|j&FMnF-VfTBtS6jdgms0sl^ zRS77nMnF+@0*Y!7P*jtEqFMwL)h3{*4gp1V2`D;&fTA3Nujt?O;KdF|^oaePA;+Ys zrF&keUNmC9Oi`m~`0l5rs4?eD(TQv+YQmPHlh{(!lr2Tg*izJ-Ek!NZQk2V=&I zN66ip(aXfgps#RL>hA)sg~0Y%dY zD4I?{(F}sGs9!W#<5{ODY+rTkFGY*o^Fn7vBj(E#&54FPJ}*UcIbVwAv88A}TZ&59 zQdG*8q6KUzTF927v)EF!h%H5n*(h2)2AXg^i-?2`IXOfTFDg6x~Qb(M<#t-Aq8yEd&(ZN^Z)@x4-$MumqmlOI3UqX`?>4OrRWzM4@D#9 z%M?8p4ZrlV6g|%QQuG8{ik@Uk(NkY$%bHCu|lVN21sY$^JVEk)n6QS<`=ML!Zy^b-L^`v@rdnSi2S z2q^lMfTH~b6dfR-=pX?_zY$P$h=8KQ1QZ=1py+o3ijERc^alY&e-cpi7Xd|o6HxRI z0Y(23d_|u`g9Q#q^f~*U{-;tj!ambK7LAxMQxwbykJu$ep^W1{(+{(yD48uq5w;Yi zu%#%KEk$W;DN1KcQIsu38Eh0~5>S*yKv6aUMKJ=3;sg{`BA}=;0Yy~^D5^?8Q8faJ zsuNIDgMgx%1QgXGpr|$hMRf=$s!Kr82?P}75KvT)fTH>Y6g43DiUJwIvmB7cjU}MyR04`lBcSMX z0*b~FP&A%^qB966DkPw20s%!u1QbmqplA{SMUx3ADkh+43IRn^2`HLIK+$vpie?Z{ zbS42sGYKe~Mer33%m@bGa*D3E`=UWoWM3u<&CZCJFHBi!&EDJtQ7DJo@4(E_#< zEo4j4S!^j<#FnDPY$;m8mZG!SQnZwfqH_o+I+uW=Wdsy0C!pv&0*cNjplAgFMJov? zT17z7Y66PZ5Kwdh0Yw)QP_&kSqKgP9T1P<9#RL>xLO{`a0*WprplAaDMVAqLMRPNP z{T+~Kefz58JSpmC_eGayM9h~dx;i5~<2@~DcZu8 zqU+gGbOT$8wz5%lBLPJ>5m0n90Y$eEP;@H+MYj=9w2gqG+X*PTgMgwt2`Ji5K+#^mTzW<<=FDf%KK zeB>i3`jYdd=qt7qea)7lZ`e}wEnAAdV@uKZY$^JIEk!@FrRXO%iuMsu^fLiPzYtLL zD*;9O2`D;1K+!=0ihd)Y=nw%#hY2V;LO{{)1QZ=5py&?*ivA>^=r00_{wAR49|DU0 zC7|dS0YzS>J~2m8fZ!|oJR?|Zk5lxp-52eZqThpVBxOd-mnlll40rlOiXxmZMJa44 zN@Yt?8e59e*-{i`OHl?}iZa ziyV;XQwArT>3^p09%;Kz*fJyL%M>-s44?m*6gB63DQdx%qFlBV<*}tGpDjfNY$0L>$_(D-fJB$t&pI}hqJ2hc zP-et@nWABt;aB!b(QwX}q7iH<8p)QTQEVw1&6c7uY$-a0Ek$G5QgkX?icVvr=yU># z#t~37o`9k=2q-EfplAXCMMVS@O(dXb5&=b%2`DNiplAvKMNW<`7Ucm*6WJk{SHj0f}}`b8v=AQ8jyXJufq2zD&`A%y8ycQnZls zrRXfS6fI&)(PFj~En!R1*=#9V%9f&Y*iv*ZTZ)#kQM8vrBW2NN7q+nM$DHf+LRd{^^Fu=%lT5YnJq=vv88AWTZ*n{ zOVJH%DcZ`Gq8r&#bQ4>OZf2wC76OWHC7|dw0*bZ~P;@&1MRyQTbSD8t+X*PTi-4lL z2`IXUfTDW|D7ue;qWcLbdVqkU2MH*8h=8Jp2`GAmfTBkUD0+;5qQ?ooqK%os#STbx zwSCp`8Y$Xs_eD=+M$DHfdL}cx={qUf!TD13EL)16V@uKVY$P7-*CPZean`j@7PlGJzI)?U`x@DY$^JQEk*m-QuH%hihg0E=vM-Y z_7hNafPkWd1Qh*7K+z!riVhP{bcBGS-w7x>NJ#@2P7rS|4jb|Bh@r3V!ljKZdQ2aFH)4p`BIe6mZAc-6t!eaQ7g6- zwPs6E8@3d+WlK>zwiLBzqo@M`MI8w!I+=i?P6QNnCZMPb0YzO2DC$N)QFj80dJs_5 zlYpXL1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&YzXb8bq)I2M=!2yYWW}lx8q1cVQ`u5<8e57^XG_sIwiJzL zqv#9*iV6uRnm|BN5dlRL2`HLGK+$9Zii!y+nnFO)R04{o5l}RpfT9@$6rD*x(M$r0 zW)V;{n}DJ@1Qg9BplBWeMe_+LDk1oahGzvoa6qEd>}%H}q^O?V7nNp3%$F%zlodXD zP>L3Fz7#ECOVQbEDO$>wqI1|%bS_(pma(O1Ia`X(V@uKbY!s~^plBrlMXLxXT1`OF z8Ul(gAfV_%0*clWP;?OiMe7JCx|o2XO9&`hPe9S71Qcx`py)CJiY_Oh=n4Xgt|Xx7 zDguhGCZK2|!B?~}D_G|@r)ZshAMGqDdc=P4@tUlN`7%Y z6m4Zo(T!{=x`{1CH?yVa7Pb`K%9f(r*eKdYK+)|46x~5U(VYYoZ6~1UE&__~CZOmZ z0*dY>py)mVitZ<%=m7$X9weaXAp(jXCZOmM0*W3bpy)9IiXJDR=m`Rfo+O~?DT1%) z+N|It2PE3s?u#}{(R%yv_HvcfBWm!ju6Uy5E}OVNvLDSC-5MK80Z=oPjU zy~>uNoop$3jV(pH*eH6PfTA}DD0-8CqTK`(y+uIL+XNK7LqO5H1QfkTK+*dI6n#KI z(T4;SeMCUf9s-I!CZOmO0*XE*py)FKiasZxXfFXpUl36ACBav;BP)2j0}>r?pO!r< zMGfprkY8m*%$F(pE-SqA4=MVd^QGtqwiNxymZG27QnZgPML)Bp=ohvW{mPc2{cI^Z zz(&zQ0*Zbkpy&_*MTZF}Izm9v?*tSbC7|dJ0*d}5py)3GivA{`=pO=#{w1L37y(6I zwmxk~QGkG=Bm#0}>r=AH=?uqLp@El#(4WU#2LU z9nSt+iZVD~iZag0CnoJJ`kniT-SVYkGRN|C#PtXTKLU#S6HqjOfTDo}6b&MvXfOdqLkK7uN;m$=&?%fRMPu1gbShhlPGd{a>1-()$Cje; zY$-Z}Ek%WFDVo4WQ4s+}6A37qL_pDG0*Z0L(We1;iK%x)Yx6VdOQHFh{ ze^z$He3_!Nv%_B|Nzqcym!fmnQgkj`ik7jZXgOPo&SOi_`D`g#!Iq+xY$;mBM$u{l ziq;TNbO8ZH7ZOmkmVly*2q;=dK+(kn6kS3<(Ru=kE+wF70|7;s5m0nF0Yz63P;?~$ zMOP6}bTt7*8wn`7hJd0?1QcCM@D(l24n~4b(Yf}8#wAj;)$WTnXGhGJDY_v$+{FEL z5Q+Put(-4KH?pPZCbksa%$A~C*iv*WTZ(RDOVKvA6y462qC40qx|4vS?F1CvML^Nr z1QgvvK+(Mf6x~Na(ftGzJwQOwg9H>kL_pEQ1Qb0&K+&TF6g@^j(c=UZJwZUxlLQn! zML^Nh1Qb0(K+z6@uV_nlaIgast!{Te*Gth<`yB1r?1=d?MK5NDXGf&yCC-RxE zfFduZPuo!xAfPCTfTAD)MIi!;!UPm06HpW(peTiaqErHk(g?ny@3Vs+IUvzFZiar4 zqPg~&etIlozD!Y8Ec|D>6lHV16vfz56lY6OCAJh*W=l~OwiH!mOHnnp6jf(SQ4KbV zY7$UXi-4lq1QgXFpr|eZMJEtYltVyKJpzjA6HwHEfTD&36g48Cs4)RWClXN9gn*)x z2qSn!0XQ}mU6)iE>Xf2P0D?u+tc5%Xn=TF1iO zGNq^u=SxvrwiLBvOHq5a6m?)rQAf5Eoy?Y^PHZXa%$A}qY!r1Rpr{)GMcoM~>OnwJ zPXda15m3~dfTBJG6!j&bs2>4E{Rt=6wN1~sDyx`QUZz=5Ky#`fTFVqC|X27(PDzH=#*ISP6s5q z+wP0TN>RW*qAiI<%$F%THx}L%m!f5yFGb7QQgj|$iq2#{r23?SCG6S&II2&kOw!iKv50>MfC_Ms!u>s0|JT~5>V8LfTG3(6rD&wQ4<1+P9mVFDFH>z z2q92BlLapKv^JR+K z#lubON>O{xm!b}ADeB0UqLbND)QK%co!L^&%okH*xwTTCZIv~+z2B)nQRk!=1vGIucGDYL!;koW#Bu;!EZ9L~o(HU$h zDr8I11hy0vv88AtTZ$&JrD!r+ii+7%G=+_#sRR^FBcNzH0Yx(iC_0mXqL~B~%_5*^ zHUUL*2q>CMK+!w`islngR6;;eDFH}0Jp6EdDLS9?rDz3PidM3vXcb$ERs80|@?&dH@VwTs-Ss@LeXMFj z&+8N$*VyyA#cpikdA(xaH}$-JvD_A(Hz-z`=Xt|oj~95}sF>H<^Tx*dwDr7kv32b| zZ$j+tj-EF;R=u<5O^cn;)$?Y?Ztm`Rb7MdD^t{qoejm?U6kFKO^OnY*9N>A&V@ZQO zZ)L3CP|v#{cFAzhTNitGq~~24t2xH=u82(->vnV$D#to9tw+Yy^M&+}f0Z7cD-S7N^` z@Vs5I*6yFg*d1H4#Pi;b?O5u0AI6fGdEO_nLFaki-q>X;Jn!q+hpRmA`&iuzJa1oY z@>3n=N*dezr^#7#@cT1yuag1FL!VMK>WEY-3<_kr)+e$Kp;M3le-B5@hdjF z+aM6%v&G#Afq2eVcPj+qQ*LrMLmpCfM)h}*v>-8>Mte-Jo7 z5VwEPwRIqF|0HMoK-~UK#ZG~^{iAr@0&)9S&3Xmm_RmuF3⁣6&e(X+dm95ED*PU z*<(~7ZvQmH*g)L=ZvAnAxc%km69RGj+pQ-D;`Y}QPYcBD@0Xn!h}&NfIyVrvzu~bo z5VyagZ&4s_f5+O=K-~V4tmT2Y{Vhi;1Mye(x?3m^x4&m(T_A3MQN*Qzxc#60R|Mkr zziMv`#O?pJ-5iM9|15b!Aa4J++s%Qv{qIWK0&)BQO|}Q(_CE~V8;ILad_Ne7+mGx% z8i?D^Ts|3y+Yim{2*mBDo?ZyV?Z;ML3B>K^4t53N_KoA+fw+C=@7+M$zIF3qAZ}lK z|0EE%FP`oV#O_tNey@80PGn5lGqOZU4*bN6Fjfi{`eyc$lg7ig>TraLdtPUBiTwSDG_ z#EU)S-iHGn^qisgVjVS}vr9W!<5e4-G)4s6=&W(fu4fmG_tV_ysxif`K{tQYjJsif zm~kftyjp=_;pqB;wmG!|!^6>jGvDq~D=;ECw)xY`4==727#WUkd8|vwtJ%bzGS{6l z$3G>I@73&~w3OV`yEaSCfB*xy|wLkxKS|83&aAAGApGA zGizmzt`-YqSM$82hF*Gl7neLQSk((=c1%Axy+eBcO3t62W7^tyR+1Yh4v{Q(itUt2 zf%J6$gn*l=8D21j^V8Ea(xd6^9hS6e$Gud#d#MVqC8`c$av;#Zl3je2dhX_^+PcCO>RO|ddlOd6 z4Ro!+wLGy#ED%rbR{iQ8HS8Ss_?zeSuas2nksj`iSfk=a)ON4A=7r}6+#9dslCj;IvJ3MXgJ>Dog*!y_M`z1w7XRI%aPG9d#Q@QD()-X z+cW4*b}x|>_{-fs0r$(jtot3v&CQ!%lsBbhZeGd!NqO@NOC}W;&YeG}w0Kf!@#MTo z^B2!8onv8A@#F>bi%Tjz&tBfWbcejT^QX_6UOIhYv6nY(&aC3RqM5~u@^WX+nN&10 zuVh-${NlX%#j}e`ic0c|TNaj-E|@%hPG0GpIWs3sE1EvLByZ}ZNrgr8XXO>-7q%*F zncuRYupr-J3m03=o-@0+MRC!@=`9NKb6d5rXXm9Z%zTrjyfZ&uNyY13!_ z|9&+}7ME0fOH7@X*M0uv1=DBG={aY9af`CI#iG*ri8qP=78y2w&J6c9FUcD@w`l&E zeHP3v9OeEjQ-{r5P*OOed)vWn{x@!>g+-;s_SW(||AwBjVD_Z^wjFXO8HK{h#Z!tF z%q%S|T|BqABzKw#b2r!I>9b4Sa34-a_Uv8guI8kkb7sw&Gut(X4=~g1qW$E#54GV0 z#$c;JI9%!f_A4An4o-D15Ui0C4g{y>+EckXImvn9c(TjMgS@0rph`I14q4%Pc5pp0 z-ODDo3|Db8-Z@;aez;N{7dS8fe{x=UV7O9$J1KFN`>(r{cxE& zE7kfxTmqL=|G4XwQ}NG}<4$Yo|FPXmmtU{MwW{l$`QQGT>e!pCVYrU_BeV=x^8X-- z)|EGotxBB|*RTA^&WTrAFFzdrAHSA(w~Civ;S%Fr!*!bHge$d3ypBqCh01P|yl_r( zW&f4@kKPQG+?%2NHmMgr{?h*2w?+;Bt)aI=;$(N@_(&4Vk+DB;o-Vj^=fo5KtNee% z6i==iuGBOfZ^Vu7UseAC!^!1GAGMDmP%kH`r@I#((YtS9pZtEF9Shp$_bZ&}KiRf* z*^_O0mOa_Fy4WCXnOoou?mo7#=a5k?{mbsfDQ(JL zUprE(^4Ht4?Dh7naFM!#EjgiW*-LduT&D%IOQuhqT|7C*-DxCVT~A%Ff<9b|dxAe^ z@3KEffx9w^m+#Uq2^ej80peL`&U2&aZ0xEor{one?(yMslf~lVSa6EfzabfZ7$-(YL_1ST|pmip>l5AXztqk=kbKyI*B_a-NI#W;)4AA z#53HzmabTVyJkFDQ2vIgaI3e|g>hT>pzPw?m%r8A+th!JEqT@DA_~e$6jU(bZYckh zg0d^a%~8-pZwb3G>@{^LdlC26*3~V)^J=9_YEyoFd00>F8Ol%HD+T4Z(|-GvF5H1}?i%+q+AeQ)agOHsJ$< z-JR&-+&NsZ^XR_`-K$MJ;ocHFuk0$h*X5eMlZ|qZ4E6Gy=x&chu^Tz@@x~|LyX^wsre|^Ai_+-c$Z?*lsTOF-BLe z?5*Tb`&Z80P22tDeE&^e;2-qPUQVr`+*%p$a$@ddx4Zn3X>;b6mVLN%lKCV0qRKFp zePDO*k%G8pF!P6_R}kNZ*%|JRe)9wtDsy~K{+jM_X2mV6DPZe0Er{FYk_+& z@h`QUP1&2FT#LIldSey12QU5!?%qI8lwm0FEhXL~%VUAgaE8j?;_j)wLq_NH?9d^{ zKK08j$gxlU^4qs;ozrA~@yz0)lH!wcTFja>cR}Y#?oC*{sKu;Stz0ObwqVvocbqbF zPElzK_nBj7cRNkC;9hdd+=Xpgl+0~0*?nEA#jK+FlcsfcpGq!l-(ptoEceN1v&kiM zn@yRU(_(5)i=i!ZTDZ@CI!|&}pv9C~#U&+0Q;S>7ES^2JbXwOoo8=EO%O7L9N2~Dh-!1Iwm3ijzY57CP3XdFlcv}82k@t`S?$+%g zr2iI@NdK{7;!R)=Q1zHK@kjOFAItvuy#JM<#``Tfccb!mhVsXR+|uQb2+M9k|6!%qw`b3eIZf;xr~CX_IlX61ES@~sJscm! zms=9=OMDsSr2qSSmVG73zK(Uw{c>LjTbk*<=4W4Z;+K7Ose5Mi70D~Zt3s=TYmzPr zc-=d==N8!)YrH_7dotX<#o*k*-TM#ml4FsdZ0$2W}sG}cA#!j z{XnjLE$YAgs+dCFfnyb)9kj1jRQMIt*TP6a`(j0fUqSbUidcnhUo~^zymH?iAeMg> z%}TKB3-JE)gP!|xYK31x&wXR8!mprr{FecPp8IB5gS)*7&VSObr#rr)<7bYF?H_gY+_y|@M|G_4{w%h0b?oJ6 z*dC_i6!&MaJzvK=9Sz%$>UhAt0c`)PV>|b@wcSg{bE^7#t&Y#TuTR_ack7s1%imRX z9O}LsYtJ92QbsX+)P<#0^biBH~zi-y@Q}=x^d;X6)HgGq* z?R*`lclGx|9q;Mx?@2BH={rr82jxP`J_q#e~4EA?T9Y+rJ z_XHiU8Sd{}b^Ls!zxV0bXpFyG>Uic@e=pMUzSI2uw2r@z^LJ>xf9zc79|!2TqR8Ku z>iDXIZhxNlbG;J=fB&N6iF5qjTE|)Q{JliS2TJ_C zL&rZB_&a%_f9$%*KMvAy)e?VSrsHc%{r#biv1R_QtK%u>`FpaC*RAmP9Xfus%HR8S zJm~^|x7BgZT7NIq@u7A8eon`~F7bEDdjHscgMS>Ney_nzuW6L?-dcO zNeg@aE*-<}|8=w-*Kwfx*$dlab==^72*dUk9Y1hCjbZz19qYIs%dp*4$4TzzGi=Y* z@pkuv8nz$S@mKc~8@B(}v5ouD4ck3*JUhqV7wGt``(X}y{u?@;=zd_sb}t==>3E7A z!=5)qd!8NBJa2)HOVn3sU#R0H>euSHO~;3Hd``zVb^JufA9OsTW6=Hhf?cm{9qZ`W z)Q;|Yjn{Fmj%##$T*udSbU!SVc=^^kPPU`F+-W+_({X{0$@aL&UB3IHCXO*3tLRu; z#~d9y>exlc-a7WzahQ&ybaWr)5|>+~W8(FtxId@1J0za(9)2Z`CHAX*}h=R#58Y+9&5;?!=N3FV}rJA=hH=@ehX+eX@OR+z)4oxyOLSMv%bn!Dt6J>7Yf|C0 zPMKdc%e_$d5rcD!N=xTYpSYmZUF`q(mwO24-fPQ$oX9=II_{Ty(*jvjuXWu6UO#uN>VDhH z*l&A%*0>JtNpF$6;^#V#{NkxzE>yg{cirXP>w;aLIpXrn8t1qty(3Kn-qs3%C*4D) z<6iFS<^iwbo1d4P=w7bk>s>i8;LUZ-Uaxgt?*jKU=eQ@mv=#v`$DYtHo;T0!ikElD zU7q>3%d^ikxx5S9)12d;^qRWMvzOx+&s*t2#mfr~D!;r8_dG6dlY5$T>@qsK%iHMQ zxA?{Lu5zK`3+~9>OXD&wddJy_fX`xmut{9 z;0m7^pZ7KQv@<`~9TLB8aF=KI zSN!62*^&1Zd)_DRj*pu&IKwsoz2yH@R5=Gdf`^A zkAJ}d_n9-7Yi08A#0vZG>rK2G?w<4LLjw=)C|O>A*WlOthx)vDbYJ$a{=51mjzf3# ze|?C1D&PH{Yei2_a7XWDdl~)rC41Ul%5%T7U+Axu{hU4J|JR&dj{W}cu^vYv!AFKXGGLoK+Y7koyVtijr`d$`X&VE7 zzdQ8MjxjxsOk6PZQ2vB_23|kljiP6dhK4_Tbhr1cyQH^uNp}nk9q8qS4)hL;JeuQ; zJX$aNId@s^cPwA|BK)>+Fqm70=d(;~q zI?%tu(*r6zJ+SQQlnG1w?VOl2?K1y5j#$+HxgstxbYPHsor9D7>ry|*U1q@jt`|Bm z#Py;7(Wf7GT{gMvGOXkJ(j zx-Kn`yDsD0>m2_duQPPu z4A%?)qc=G2x?Jb3%Y?Gm6FN{-;pvGLo}N_pbjpNEiR*Huu1nT&*JZMMoyGt0IztDh zxIXniy4SzKUN5_9w{ESx{2VXrKAuIq-unsy-Q0V5_QL}M%M(4~Rc<^g@NdJ%T@QQj zpZY`~;H~j$cZqsCf`Rj%S+hTJ7lRX%SK0lkrj=de(1Ga{o}N+R=`+ioPMOd-@u%9L zKUK%${!}yFwV(AL*FJP$w(E2Lqc=P5EnL%Gm$_xHCv;$5g{S9Nc)FzQ>68gI6W2xW z1*5wid}@Bx{x25oIQl{kf65*QE9Ha^l)BfQcu#Qe1q&)Xy)fyl*6umOMjmaLlQPiW z`|Ld>Jiy+&-R(E+TK`Wu@|~iiPubhQcXYXTl6ze1e;jZ>H0JJ*qeCN}*Sq4qx4ZL8 z3M8LpUyloxaSo%Jz^W?7qa{CEI`8 z>wn0-#z-jCIK17xK#Kj{t|#jM*FC|_0x#4=v#y&hz0gUTb=+*_{yibh+HSV?Ld`U5 zx!J}GHP@`^W?T1H5^L6Qvz-^p)vWGjdoPrySRcyQK)l$2% zZFj|5X;-rCu32mCxNUdU+GxjYyX)3gJKMIqa_zLUY`bgMUOUsayLuh8Gi(@g& zWZPZ8p4#r41U*{1>(@&=$?aC|`t{a!50QGba@VhqwquYQ3N;MA;cox5n+;K;#Q$-c zcE~+c4fTy|cQ0T<28Q2oo)ba_=~M|BtSKQwG$mxHri2XBl#t?@MH?YwwGncvHbPF*M#$;f2pOl1kn!3GIYS#Eh1v+2ppB3sZG=qJM#v;> zgiO{(NU=6Trf4H%sy0HVX(MF1HbQ1-BjikNUr7Jpes}w)onk5m_(CSTyQ$F3h{-V_ zbHn@HGZRAQ=~M}suPGrVni5i~DIp6qC1jzdgq)=*A&WF6WU;1%EYU>B+1dzMs*R9y zv=MTyHbRzZBV@TYLeA4h$obj`S)q-PmD&hdrHzo)+6Y;rjgSkp5ptn6Le^>{nRNwGncuwl8FMFz!B>q@CnG>V)R_LJm3_p$!p}V?wSB$K8j*gpjLr zs)SsvDIps*CFB}S3E8A6A=he3$YxCmxlU6;wrEPo^_mE|K^q}kwGncoHbQRFM##z0 z2ec9Lpf*At()NX19&GJy|Fm4Y54pk@vdNx)IAU^4$m8MG?oK5kAHbQo5Bjhb@guJbdkax5Z@~$>Q-qS|N``QTkKpP<+Y9r($ZG`O6 z_Juqe9OG{Pw6J@$8+yzaGR7X0d>k=3Cgk(*827cJgpj>DRYJbdl#nkqCFCnj3He%6 zLcYNHbQ>UM#!()2-&ZVkOSHXIjD`0 z-?R~ONE;!CwGnbe8zH}IBjl(yLjKT3$e-E>`AZuie`_P;A8myEtBsIj+P;uagNxnm zpZ1nL_V_FzB>hsm5AgyKqvJ(Gp->>a$$kAV!#F&$x81|?GV0I)sP?cTMXOk}bGvdIBMA z!CliFLdb%eMGBxnQ5`G#~^lxNF*w;DBU?LP>$(GY&}li}vs&81NMx zw#O}v0uke7icSiI_qwl;CKNU0d?{+imZIitDQdx%qFlBV<*}tGpDjfNY$O??MX99}45Kz>WfTC^$6m=({s0RT> zJqal4MLP7DOY?#u4!TkNi=i4^TMQUd}J^JR*L1j3Cg zOVLoym!e^8DH_g}q7iH<8p)QTQEVw1&6c7uY$-a0Ek$G5C_0sZqSFW{I-P)`aRd~N zC!pvI0*VR=D4IY(Q4s+}6A37qL_pDG0*ZDLRLZqH_r-T1G(8asrCZBcSMf0*Y1;P_&YOqE!SG zttOyo4FN?L5Kwd>0Yz&GD7uJ%qIComT}(jHB?J_$C!pw30*W>eP;?mqMVAwNMe_o| z4Gu_p3-_6JXucE;PJEsfh?p-^v@sCA-~C)dLeVvxFGZW!Qgkg_iZ-*Q=sLC(ZDC8% z^=v7+fh|Q_*-~^P8$~w}P;@f^MYj-8bSnWxw-HdZjew%t2`IXQfTBAIDB4ay(Om=- z-AzEzJp>fpOF+?m1Qgv*K+yvP6g@~l(L)3jJxoB+BLoyZO7In36$pOdfTZs;I9E$i z%*JDZi1{)_PX)q9Yf916oG(Ssu%&1RTZ*1#OVM*|DSDnQMK7?W=tZ^^y~LKHm)R(K zg@B@02`Ji0K+$Ui6zw9Q=yd{$-XNgpO#+H`6HxRP0Yz^UQ1lJ~Meh<&^d134?-Nk; z0RcrH5>WIJ0Y!TVDEgRyqE84Y`jp@+dLj_4<9_5PJ=^Y!o|K}W?9ugSfr$AsMPCNO zUFt~DSDY_JU$dp?8@3dE%a)?=*i!U8TZ(>QOVN*PDf)>mMf=z&`k8>DUkE7rm4KrC z1QZ=0py(h0MZXbHbcleW!vqu^A)x4Y0*a0jQ1k}@MSl`d^cMj|e-lvj4*^C05>RxE zfFduc?6Z9TbF=^fMM(r-(cVCCk^_>y)O~w1^o10yw)>)BQp9|jqDWGBlUO(Le%<1`&KkO_PGZIw0w}?uQ0L z&7`QZeWpJ+DPq1%(eR{jc0(x|!TC}&k}XA}*itl_Ek$G4QgjMiipH{~=v1~8oyL}; z)7dB*M?led0*cNcps0|5q6q{P6%kN0k$|E}1Qbmsps1LDqA3IvO(mdc8UaPq2`HLD zK+%~56wM@{XchrQvk54gLqO470*dAld__Z(f^8g-^o4d`G)#&j_7QDG} zF^#3@EY6prMQkZr%$A}hY$-aMEk#S&QgjYmiq2(A(K5CaEoYT|3fTD{CC|XBA(ZvK5T|z+7dIE|rC7@^n;s0aruA`*7 z_xxX1QC$>JNEL)YLIe`xK^h2wBqTvY++7F(0wh?FxVyW%ySux)ySuyVZ-0A#9^lNJ znLBr_S?k_EeynxQ=Kbp4)lv`DRn;A!=y-vm69kG*6ev1Lpy*^FS2VL(X^#v@bx3-O zXjUkCD%}>H(yWqvB}Hd6E1$V!C_2;mq3A3-6rF8{qI2v}bgmtW&a*?&`F1F}zz#(h z+M(zoo1%*aiY^f-x>TU(GJ&GY1&Xc^D7sRh=qiDts|AX#5h%J=py)b*qU!~UZV)KC zQK0B1fufrQif$1ox>ca)Hi4qs1&Zzvaz&>#E8Uj?sh(HN;G7RIuzaK{7`hi9f}^XL(zkFD0;{aMGxDd=n*>>6g?$S z^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(UofxeMVq91*Y7o}BwtCBogy zmhwmXucX_eWlELgD=F$#D&N=`ih4Ug6gAqRsE-|r`r4tWpB;*pvqMpTI}|N%hoS*? zC>m%}w1PmknIG)$mqxIobefuhv}ibe_) ztu9cshCtDp0!3>H6s;{#w2na0x`=6+9f~%yL(%4TDB8jfMO)gTXe&DuZEc65ZET802^4KBP&8VgXgh(T zF#<(n1&YQA6m2h1G+v-+f6>U%|E!;0t^k?=niwzrwq65>t>sh5r@|6_rRw}RBKNRim{7|%q9g6m}L(yJ# zDB9Z&Mf=#HXkR-N?PrIg{q0b6fKAbX0!0T26df#3bcjIFp#nvR2^1YJP;`Vq(UAg0 zM+p=iEl_lfK+&-RMaKyg9WPLHflg*I)S3=1&VGED7sOg=q7=pn+1w) z5h%Jg!3-S)u6tH0~)?lCPxbfl~R& z?7ui~`pJ+7oga!GvP03sb|`wp4n>dJq3AI?6g_T-q9^Q7^rRh%p0X)=TA=6|fud&x zik=fFdS0OD1%aX$1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2fueT> ziry0_dS9UE10h#*U#aw62Bdm&de-s&P_#n2E&8xjNxqVzPqUwg92AN^bABlL+zv%w z*rDi4I~09ohoZ0TQ1p!*ioUf&(RX$z`rfAK2Z5p=1&V$WDEe8T=of*aUj>SO6Day! zpy&^QqCW+S{t_tqTcGG4fuii^yYq+b6cq)Enh6w@1d192ipl~-%>{}o0!1x^T+zp+ z(()OQ>Y()C{*zF2WV(0VvZ0cEB}Hu-%A2hcirP9q6t%NMQOyoTbvqQbw?k0}I~2`h zhoX*lD4N#}MV)MlItvudCr~uMKv5Tgq6Gws78EF2NT6t8fugPgMco9777-{~RG_H4 zK+$3XMT-j*Eg?{}q(IS90!2#;6fGlAw5&i;4|%| z8!E|HQq-rReD>f_)Yti;sGl8*ma{`qe>)T{Z-=4*b|@NXhoTkiP_&{QidM2I8YED( zvOv))0!6C|6b%+A8X{0MRG?^>K+$l4q7ec`s|gg16ewCnjug$Q=n*;K+(XLju$98 zL7?bFfufTHicS_NIz^!9RDq(?1d2`#davV#12K5+M(z&I}}}RhoUQNimntW zx=NtvYJs9_1d6T|D7sFd=z4*o8w84O6ezk$py+0SqFV%tZWSoHO`zy@fucJEitZFB zx=WzwZh@kE1d8qzD7sI`6`j*iIw=EEeJ_0nJQ+6nN+73m}*rDiIo1*6gik=rJdO@J*MS-H11d3i3 zD0)Sp=v9HD*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>WiryC}`aq!QLxG}?1d2Wu zazzg|l-|gIREMW8Vh@F)E7K$WPZ}!8S5ovvL;26OLeZDb4@FQG`K+&H9MSlqt{Vh=Rk3dnO z91q(mDhd=e6DTSP6g3DGl?95L3lvoZidqO1wG=37B~Vlqaz&ptl)9~*DOx%Edp#OH z4@Kql?U2^xO7fKy)ym}|>xQDb^FvX4I}~-WL(x2TDC%g3qIvC5)X5G-o$XLGpB;+k zw<+o(P_%$R(Sia+3kei0EKt-{ps1Tb(INsxiwYEV7bsdxplES{q9p{1mJ}#jN}yLF0nQ=q7qKv8cYSJbv#8lM5FE|7lix?MScr2k{OtKC?xBwtC=& z>xZKL&JRV)+o5QH9f}6pp=bp=6s>57qLu7WG{_D`E8C%H6`P_}1&Rg>6b%t58Y)mU zOrU7EK+y<+qSXY7MhXN_FK+&24MQaHZtu0WrjzH160!8Zy6s<2%w1Gg;h5|(! z2^4KCVBc<<}@}bSCX%!Xp3_B=?z2Cmd+1FTiKy#YdaKeV~3(q zb|~7`4n?EwP_&&LipJQXXsk`qIDw+=1&YQC6ipB)nkZ1TgFw-a0!5PqiY5ybO%W)X zDo`{{plBz7qUi!fGX#oe3KY!}DB4+|XcvK^T?LAE6DZnU$Q5l?F8z=JsotFK3T+;W zwn=xA_9$19ucT<7a(SLjLeaj?4@LXgp=f_Q6dhoPq66(vbdVj24z@$lA$BM_)DA_5 z*%TcvP;`Vq(UAg0M+p=iEl_lfK+&-RMaKyg9WPLHfE9_8or5%c{vP03;HbvJ66kRJ&be%xa^#VmV z2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~ z2oyai!nU{my>K+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3 zTLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keIiiwsX)Ue zzu2MZSDT{W1d4taDEdR7=ud&7zXXc@7AX2hps3J19=20d6ewyYP*f5qY7i(Y3ludM zD5?k)wGb$3DNxi(pr|TP)LNjZjX+UbAy@Qexm4XcQ?yPt8@>uf-=&BB?V4ATucW9$ z^YXHzLeV_V4@DjAP&BU{iaOb$sIwi4=Cec5{B|hnVuzvy>`=6zP0>OEMGFfQbrmS; zCQ!79K+&QCMcoC878591T%c$Pfubb^ik1>6T3VoJ8G)i@1&VqI6!jD+>LpOrTcD^> zps0^PQC}ffRBv8dKLb*|JKei(-#mY$-#tC-@7KJNd?iH#nwO`K4n+f68pe z_3-pXZ23_1So(Iz=FKa~S5mZf^YX1@LeVzP4@INwP_(TbibmU^XgfO;jj=<~SUVJr zvqRDLb|@NeQ#3)KXre&T4gy6x3KUHeD4Hx#G)16jszA{+fufxRilz$`%@8P>DNr;^ zplD}-qFn@vb`>bvO`vFZfucPGiuM#J+Dph4ZP~o^RtBVcQ~LR$twK@1^c8LI=9T0t zDcZkz`R{R|=m6)3q66(vbdVj24z@$lA$BM_)DA_5*`ergI}{yZhoU2GijEQ}I$EIU z7=fZ=1&WRnC^}xC=mdeH69tM+5-2)Zpy(8VqEiKmP7^3PU7+X;fub`7ip~-!I$NOV z9D$;91&YoSC^}!r746%+wCMJkqW9Bn(SD(5(WVD%%`3@QQgli4@~{b^=u+p0qRZ@1 zbh#ahuCPPVm3An)$__`?TwP0=d?MXw4Jy(Uofx!gSM zUp22JUrEt-&CAbD3Ps;LKNS67hoT?tQ1p`>ihj03(Jyu=`qd6azuBSacRLjQVN>*{ zK+#_UMSlwv{UcCRsKmo|ii!e7%>;@{0!0l1MP-4a<^n|(fua@yMJ)x2S_u?Y1&Ue= z6txj3YAaCGPN1kJP*fLkMc*_p{geTzzMXDg4=T z)Y%S2^Vy+jemfL(u|v@Ub|_lV4n+&up=e<{6m_*J>LyUMh(OVz0!7^giWUW`Wd(|Q2o&`cDC#9p)LWpaQJ|=gKv7?TqJ9EJ%Lx?q7ji}O zR7xvmK&r#iBmIt*{E>e9^hkgCN+tP9idL+Yx7sNbt>pYrG{_D`E8C%H6+0BIYKNl1 zb|@NRhoYf&C>mymqTx10BLs?86DS%fP_(*0(Ha6pYYG&tB~Y}sK+!q^Me7O_ttU{l zzCh6i0!14N6m29>w6Q?ZCIUs93KVT7P_(%~(G~(lTMD_NftAvJ8IbBX*=$%L6kVBa zi?*s%lCPv_+e-QT8KG#j^Fz^gb|@NShoZ4|C>m#nqV4TaG~NzH6YNkl(GEpB*c9z3 zP&7%PXtF@j6oI0t0!7mVigpqxnl4Z@L!fA;K+!CLqMZebb`dDrRiJ1$fuh|7iuMpF z+EbutFM*=H1&a0&DB4%Z6>U=~J(2;bE|(sbjS5BYrys)JuTn|AlA?nu`zIy)3yZ-=5A>`-*0P0>vPMK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS z3l!ZWP;{?A(R~6%_X`v~AW-z6K+!`2MGp%UJt9!_s6f$U0!5DtxuQ!er42J6)z8y^ z8+%zOnm^suexg!IzLKJ6D&?8GhoWblABvu{L(%hgD0;yTMK9W+=p{Q8y=;e~SL{&q zsvU}6vnhIApy&;OqBjMK-V!K!TcGG2fueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jW zPX&rT6Dayzpy&&MqAvxCz7i<bq`FhOEA(_Ix+~oleOsv{UrEuA zmGbR-hN7RGABujqL(wmGDEie7MZejh=yy95{b7fqKkZQTmmP}!wki5Yps3Iy9=20d z6ewyYP*f5qY7i(Y3ludMD5?k)wGb$3DNxi(pr|TP)LNjZjX+UbfueQ-MKytf zNVao}{E_~v>E87UEh@=ZQnYf5@`(LH(JIalMXTDOXs{iMhS;HKs2z%i*`a8-9g0TS zp=dQb6pgegT3w)M4S}LH1&Y=ZC|X;fXdQu~bp?vn6DV3=plAbuq74O#HWDb>SfFSV zfucW)%5dd4OfPuMbcNar(0B# zucYYt7UgXY4@ECHKNP)ahoYD4Q1r4Lie9lp(W`bSdd&_+uiK&M4LcOQX;bu;K+)R* zMehg{y(>`koQ`AhLs3cI-AW&2mC~7WHR1qj@ zAyCv(ps1BVQB|O*wLnoDfugnoMePKNY63-dfui;TMI8i+<`F3BC{Q%7Kv5?lSM*bh z(qkEr>VE0w=jTw=IgQROE6G<RF zp{TnZiWaj&(c(5mO9&J#DNwYOK+)0yMau{jEh|veL!hXqKv6G&qTT{UjRHk|1d93! z6!jA*T27#-zd+IQ0!0G^iUtZ4tsqdeqCn9~Lau23mZf&bWQzKyJJelT=8yDuXnMfb zvXXoyMT1+Gdmk5yhB!YI4YfnjFgp|tw?okgI~1*EhoX^oC|cbPMQhlhXib}YdkYlpBT%%jK+%2zMf(dB9UxG2pg_?<0!0T4xuUTx zOJ`(2s?Vio9mj>DdD9OY9n!Lrd?iIkv@G9wQYbpo`Jw12I}{ylhoWQbP;{&vijK2G z(eZXDI>8P_C)%OtB%7j>1&U4)C^}W3=rn<%(*=so5GXoRpy(`tqO%2x&Jid&SD@%T zfui#TiY^c+x=^6#B7vfd1&S^aD7sXj=rVz#%LR(A5OPI_wJg1t0jZ|{mb&5aP_$Wk z*nefqO7fKyUE8wU?9@!$_!45??+M(zsI~3h)hoW2TP;{#uif*$*(d{-x zcL)^SDNuBmK+)X-MfV64-78RZpFq+50!0r96g?>n1&TfsDEeHW=nH|OF9nLe5-9pwpy(TcqHhI?z7r_=UZCg)fubJ; zihdGuMK820P0oN+w@7ea3`K9HZ_WPPvXXoyMZdQ!AAM#h`osC5=ubNo{bh%uzwJ=; zj~$8%t>Te;C@R{asF@v#N_Hq}uqi4F6g3wpst6Rd5GZOXP}EAGs47s@TA-+nKv7$P zqILpBHG!hKKv8>vq7DK@^9U4m6eyZkps15TQD=do`2>pQ7ji|vwk+L{0jYkO?ic+Q zidIOYORGxql@u-9s{G>Fp{T3#Ls2(76fI(hqDAdc)ZGq6i`k)QaXS<(VTYn6?NGFo zP0`WX)%JZKW ziiSHs6pgS$(Q0-m8fk~3)$LHUh8>F5v_sKab|_lg4n^zO6s;>zw4OlG`T|882o!B7 zP_&Ui(Z&Krn+OzbDp0hUK+)y`MOz3IZ7EQ+l|a$f0!7;h6pa!n+E$=wv_R2z0!3p4 zipC1Lq9LtHt7Jf`pgP&CC3 zMN{oiG|di0JK3RVx*dvU*c8naD4Hcuw6j3bE&@fn3KZ=oP_(;1(H;UtdkPfoB~Y}t zK+!$|Mf(aA?I%#Qzd+Fe0!0T36dfc`bg)3tAp%8*3KShC`=2C)=Uu6gw21 zYEyKYK+)*}MP~>UoheXsmO#l|a$eLayk@R;4F0Ak_`i6OBiOqQ>+{|C&~nb2^2jpQ1paA(USs2PYDz~El~7~K+&@TMb8No zJugu7f{-h^u2rdiX{M-}etQ4`=ZB)#?NIcF9g5zx zL(yAyD0YCLieMMXOlHM2ue$qq#gb|@;_ zp{ThXiYhimEd+{M3KX>xD5?q+wH7F9BT&>P57ps0gD(L4f09R-T! z6)5T?P}EtVXg-0W`2~u)2ox8uP$^~3Zl3;u|v_aHbp%Iih2qZ^%5xR zEl|`bP}E1DsINd#KY^m<1d93#6fG}MG(ezepg_?I0!1qd6s;ssG)SOmWr3nq1d3J_ zC>ktKG(^Z1b*+{@$beMWNcW4nRr5#sSESpbq18(Al@zU3EjL^jibgs=6s>NDqBZPL zw5A=3*0Mv<+IA>f#|}m7+M#GYI~1*NQ?!9V(S`y=8wnI`EKszGK+&cGMVko}Z7xu> zg+S4k0!3R16m2a~w2eT~D1oAF1&T%s6m2I^G)ACktU%E?fuijNipC4MqT$ujQW=oy zRq2O8MuejDG*QEZY9;wfiY8UdYupfuCObbAO|e7KR67(+vqRBNb|{)|hoTvFD4J=9 zqFHt*+S#UP7lEQ(1&VePDB4}1Xb*v+Jq3#P5-8eRplBa~qJ0I5_7f=DU!dp!fuaKi ziVhMeI#{6S5P_mY1&R(6C^}rA=m>$LBZXYi4%O1s3`ljy^lkhdL(wkj-t|${O7fKy z9ak+Mds8Sn-ua>E1UnR+XosSc>`-*F9g0q|L(!>rC_2p!MW@@L=nR{pGX;vy5-2)b zpy(WdqH_g`&J!p)U!dp$fuaiqiY^i;x>%s-5`m&i1&S^cD7svr=n8?ND+P+K5-7S_ zpy(QbqH6_;t`l-a$5cxL(yG!D7xDYMfcdD=w6$m`vi*a7bto_py)w?qK5>E9u_EiM4;$V zfuhF*iXImzdP1P+Nr9rL1d5&(D0)Vq=vjfH=LCwL7bto`py)+`qL&1UUKVmiH&#o3 zWI(D*Bse#Pq6^Y((JR$T@|6_5Q7tc!J)hn5cZR&_{803k9g5zzL(w~SD0=K@7v2o!xOQ1q2R(bob+-v|_aD^T>E zK+*RCML!4>{U}iMlR(kW0!6W{0AZ9f}(4P*k=hqKv8FbqWJ`h<`*dHB2ct| zK+%E%MGFZOEi6#fRmc_nT`e7w0jXBfPt5)kiiTz{Yv|Uxl6)mai?uFadUq&V-1(ts z2|E-mX@{bv>`=6{9g3E*L(#H!DC%K{qMmjr>Sa^ZTcD^>ps0^PQD1?gegZ|y2^94g zC|X{iXn;V`K!Kta1d3J^C|XINXplhB$^u2J2o$XfuhX>iZ&N0+CrdcOM#-T1d6s6DB4D#Xp}(F zwgN??1&X#4C>kSBG*+N!oIug`0!8BmiY5pYO%y2FLC6)2Y+dSbU#4i@^sM9Rq3E#e zWeq#Ft|VVc(bU%Eeh-AAY0eKtJK3RVx*dvU*r8~q9g1ezp=f726zyV%qFwD!w3|)Q z?gB-72o&upP_&mo(cS_@`v?^6D^RqbK+*mJMF$8J9Vk$AkU-JF0!4=i6dfv1beKTV z;Q~cR2oxPDP;`_)(a{1$#|XKi$*oJ9XF#g!r#sYBLeZEsj%{5@zLKI7TbFl#C={LK z{7`hV9g0q|L(!>rC_2p!MW@@L=nOj)ooR=nv+PiGwoTDF0!8Nv6rCqfbiP2*1p-AE z3KU%=P;{|C(Io;!mkJbJCQx*_K+zQfMOO+GT_sR-wLsA|0!7yf6kR7!biF{)4FW|s z3b~@=TbItsfK;2OpSwOG6n&h=O|2`*S5kCa>+-#igreJ>AByg_py(liqK5^F9uX*dRG{cFfuhF+ik=WCdQzb1DS@J= z1&W>#D0)_)=sAI+=LL#h5GZ<4py(xmqL&4VUJ)pIRiNlKAy;%u>(WOVkm{gx^K)w` z>Xp5$;q}&)SO6Day!py&^QqCW+S{t_tqTgVl?*}Ak$2Bdm>`kwwR-mYzKv7Mgs4h^{ zUZALhK+!w`MI8l-<`pRFBv8~@plCjUqWJ}ix(F04AW*cRK+!@1MGFfQbrmS;CQ!79 zK+&Q?uBh0iv{MG8dT)Z$tWEwHt$X&ehVE@D$yZXeWSjEwPluwVoFBJEOWUDn89Nj$ zYlos9b|~s;hoW9~DC%v8qDDIu^|2}HD^S!=plCUPqW%I!%L^0@5GWcbP_%+T(TV~^ zD+v@05-3_(plB6=qE!Wo1`8Ao5hxleP&7=SXt+Sp2!W#21d2uqxuV6}ly1p@R98rF zmIy_i)0el^+fEAqV?=hw7wmRHn2m{hIT00$PPst+o5O^ zI}~kdQ?!{t(dGh0TL=_wDNwYPK+)C$McW7zjS?u@R-kCKK+$#rMPmet#tIaT6DZnV zplG~6(FB2_i2_AC2o&uoP&7%PXtIziTC+{*uM9}_lyqCPRw#NZk($z`l6)ma)7z96 zdLb0eaDFJ7X@{a&b|~7}4n@1zp=eh-6zyh*qTTIKw1*vv_OvP5OQ2|Pfuel`iuM&K z+E1Wpe}SR{1d0w6C^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1 zI!>VIcp+CbtxaiY2Bg|PJ?pqrC>oJ&i%w`$NxqVzQ`(frz7&d1b$%#1%??GU+o9+T zI~1L1hoZCWP;|B(iq5e^(YbagI?tx)e1W111d1*cD7r|X=wgAQO9YB86)3t)py+ae zqALW7t`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTZCNENo`7pWk9NL zq-PyZ4n;4dNBXz6sU%-X(VcC|m%kEH6UON=sXNRKu?NIc99f}^b zL(xNaD0(`P`>Iw4n?i(P*k-;QENLCwXs7{TRRlBvqMqMrl>AZ)Lx*dgFw+d0!1AKislt4>LgIq zS)gb>fui{Zin<6CEg(>|pg_?=0!0f86m=CS>LyUMh(OVz0!7^giWUK+!OPqTvEXBLs?86DS%fP_(*0(Ha6pYYMrdrP`Lx%Yam8rk{0OIuw1MNUhbj zl6)ma>$NT4|86K+-}#|v13MILXosSW>`=6^9f~%wL(!&oDB8>pMVs59XbYR7Ed`3U z5-8eQplBO`qEP}x+X@to7AV?IplFOh(O7|^aRNo#3lxnPD4HNpG*O^v2Z5p;1&SsK z6ipT=nj%m%RiJ2^kSkiJZRwK?NVPHj-1WMls9m~uy;Ivt@|6_LYFlpcK`7eU`JreR zI~46|hoar=P_(-piuSNW(VliF+RF|_d)uLCADg0m1&a0)DB543=m3GD0|kl>5-2)Y zpy&{RqC*9W4ihLkT%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5^_Z| z+Ln4`K&mUJ+oGAF=+E@9|KzrnPu|U5DN}TM+wwXeg`zW@ABxVjL(y4wC_38?Md#R| z=v+G#oo9!l^X*V{fgOr2v?;nspy*fY&D z$J0X5qv^Kjj<%KLD=E6CZTZAcLeag>4@LLcq3C`)6g^;vq6h6z^pG8j9=1c#BX%fy z)DA_D*%Uo4Q1paA(USs2PYDz~El~7~K+&@TMb8NoJugu7fp9|Vei6e#*hpy+3TqF)4xeibPCO`zy^fucVIivAQR`b(hbZ-JtJ1d0mn;$b^Q zMS-Gb0!1Z(q6Q&X^nTmYKN*nfD+$gAq3Ezgs@$%Ud?iIK+m*Y18H!ptKNMB%P}JHE zMQ!X*)Yc9~?d(ugvqMqc4n^(lP}ISuXdZ#0jsivV3KVq`DC#UwG@n4x`~pQ?1d0|A zC|XdUXd!{3g$0Vb3KVq{C|X3IXiyedM*P}-7P(Ly+J7IlWvPbV+D$i6DT@fpy&jFq7wy*P7)|OS)k|?fud7|T+z<$N}Ybl z6dj+wkG4xFx~80s)7n*%ucYX#cI5#-g`%^aABxVgL(#c*C_2v$Md#b0=mI+wU1*1* zi|kNzu^oyou_?M#py)DzqRRz}t`I1?QlRK6fugGgimnkTx>lg*I)S3=1&VGED7sOg z=q7=pn+1w)5h%J~YL4MG#l6)mapR_AK_**FY)cK+4 zGdmQ0Zik{T>`?Tj9g4oPL($iEDEh_@Mc>+?=sTOD?*)o}5GeXlpy(%oqMrqdei118 zRiNlMfui39ivAEN`ct6jFM*=J1&aO=C@R$AVLL@dfud#tMJ0iv27#ioKv8pnqKc3! z`lwy$vkXXe?esd#Qr#`&SBtsRQm*`cUrhoZV2irU+u zsDmAf=CMOjM>`bFYg5!ops2Gz(R>0$^9vMp5hz+fplCsXqJ;#C78WS#Dp1r-plA_+ zqD2LYx(gI7CQ!7vK+zHcMN0}4EhSL2v_R1^0!7OTxuRCJQm+h1^{ti}oN6t9r2lOC z^46nPNxqVz##(v3ze7Hj)IBD^RqaK+*a_uBcb7G%EvA{X5;e?j4FQOgBs$)GEnWQnX2}d~zXOK<`4s zrp^yVo7tggb2}7mVTYnE?NGFp9g4QLL(w*NC>mvlqHS%8Mhg^eCr~s-plGZ>(Kvyk z?FEX)3lvQdD4Hlxw1Ys=jsiuK1d1jL6ipE*nkrB3ptyC;!il(IJu6GYb zr={DXGi#OPD=9j+R$inWiq3O>C_3K`MHkqi=t4UbU1W!%i|tT!i5-eAwL{Tmb||{s zrsxWRqALZ8t`aD^TA=6}fud^#imnqVx?Z5@27#g*1&VGGD7smo=oW#ZTLp@46DYb} zpy&>PqB{kO?h+`vTcGG3fuehbT+!LJ(rOuy>Qd?E=bTV9Dm_NKuU1LElA?!dB~bLXK+!t_Mehm}y(dugzCh6j0!1GR z6n!M*iXNzyj>>>kd!^f=2Sd?~>E89nwMz1p6n$PRU)?ekec}92^ran&zOqBn*LEoS z#tuc_+M(z>I~09yhoT?sQ1qis(N6+JKMNH7B2e_JK+$gkMZXIa{UK2Fr$EtP0!4od z6#XMmRH(K+$l4q7ec`s|gg16ewC>don{P~T9rc)EAJalMj!B}JRp%lpDNr;^plD}-qFn@vb`>bvO~@5(S}$Fc0ja)_Zi_Yx zMc<{TAa}1^qBKQ(c^X~dcqDxPuijA zDLWKBZHJ;~>`?Tq9g3c_L(%g#MK1^xy(m!hl0ebR0!6O~6ul}?^qN4?>jFh@2o$|3 zQ1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$kwDSM0!5z)6n!e>iXN_)cFBNLe@Kt? z9|=X-+?=sP%r5-4gAC@KpS zH5VwV2o$vtC~7HC)JmYJDp1r~ps0glA`6?m%A?%iUv486b-aP(F%4b zTG0+gE7_rFkR6IvwnNb>b|_la4n>1)iiQXj4HYOFCQvk7plF0Z(P{!kBL#|97bsdo zplD5jqO}By))pvQN1$k3fui*Uiq;n>+CZRaLxG}=1d28mDB47zXj36qv|Rhr>KTyg zN(oN?P*h8|MVqy+BwtCbPYvYJ3ka{V~3(qb|~7`4n?EwP_&&LipJQXXsjKI z#@V50dz+&10!0%9iY5va?I2LJqd?IlfuhL*MNXh`8AzOx`bJLf%z1mljucTyrsdZDmDZSi>ug|4+p^A-x- zYu9%!6qc<0I)9F7YfsA9}X=PX4aM-Q7G(Mn>Mmg*t2%?8im5XwLjM?6b`HnS+`I) zw07wFg~E}wr#CDVj;+nJNuh9JZHvtcg;Q(iZc!+lS^IdaLgC!nvZD%x3v1Iy7Ydiw zZXHu7Tv_{jT%mAnZPzISZ{V}b`2EkBTvt+ zf@1yXGqdZUSby>C>`Exs=RYsI7K-(4FUYQjV*TQavg@H(Pyd>I_hLQ$bL2}F>*?Q< zUba|I{~&PhVmIQv zE!NX_{$4EB)3?{60C>B-Y~i}m#E*N4S=divtiVm&?n{IXb243TXSuC`_Fg>?_Vg5(1!@1d&IUxIEHBX^=kL=KKK#M}5+^17Y^LEHy zR_vR-c19`t<5oO#;U$WNPH&b{?RrdBv)66<)wz52BVEPi+NM_MJT3dbV*ePAWTzLG zk8yT7bwJw#nqKXi?9Xd)V7z3t^lB@_xIJCkiZSj>W2G2lirE+xqn0jh*|2)gKgRAUtX(K_F8jYcr|7@e_O5NBD0w;vQ1oM(@W=EWZSsNc&&EXN#!~3 zN3Biv-lex(Z~9HSP-q_?P`r^2#p3E6(#6lyE&C*O>^Ijtw90%d%~vSQ+q1aJeBR3? z=BpRmH(#~$DMRK<=X5I1_3F(!-7+Nm+;yJ&A{NNr@_dKwU(7zojoItZfB62zLbJ}t z4e6X+2|Wwx4NPgEou1n=yJuuW@}w&6qiB z?8K?PW=@?tY0QMt6Q|7RHGa&PQKP3%?$y|PRNqm3diQA@)z~}59$D-$W$Ki1J;sgR zZeowd-aY&FNH6Z0z4%{V)NA6DF_UJE9oK8}=rI!}PWk`*-I%f4jJZD(<0teQJbmn} ziBqNyojQG7kJ+D#U1v^j`jq6Kk@coe-68v&&*-(`w9(Ud95HLksEx9ZW&C=RX3ZG2 z!QlRDFZaK3HSIil=D76PDirc7diz;Z#`Ipkch512!l<$1wjVuf(#%macbhhDM$ZXJ zSax-doj7G?HnN+b4TlaNmA#u|hEAP4dFqs`W#WLDm@Ya`h3tmC+@!PAw^%NB_^*DI zi_J^pi{W%f-_8p4pzSYq{LKSGj%j;^L*<{k}uDMHZ0%UmORei^*O; z9Xl-iU!3@FU+{0w=-8v%GXLg6y2V@Ro!xmWb}U!Zpr?KS&GxG- z+pXMn(Q=0_|K^gKKJ2V7@-LUvb?!?_pOHRIZ?Hr5+P!*}yDd^~pDwFgxkJ;(>M|Vv zAK$A5n->T5=vD5}qv;)TAzAIUdbvY-$Fr9;U2^Yow{&cJZx;P;KFs#b=j~NquuHka z8cio>m-OHNHouOt&r0)o%Iz1*&iNmG_}zN{yI1}I0Ty$p|Mwb9 z>gR&{|4X9H7XR;VZ2s?c_`h)-X1A}|?aYGNjne=4R=$1nPUQuc`u8_^y%tV4+T{-E zR?f|8uk41eWBxYWX8(_F0E>gVHfzZ4%xy4ywNWE_k1V8P$>mt*8oSo3e3H@ik*1)FsY1Wh(6UR>(H@0hb zXQb&hhsOKWIKri5zllp}96tNwXw2T3rq>^sz1pZz+1Y*jjLI*eF?(Z97~#?e$E6LK za|zjJAbYj3vnEg8Ex)9A-G1Ki;0Vjleh0Eo=|KMva>?cH-zMqb5zAGCuzRv#TU~^V$94xvrCV*ZR$QZ?o$^ zfA!fP9%#Mid~^e6e5Vkbk=2;d%3E(QoP(`# zgsWwaG1pY~0p#cTO}a{&Zkpy?t=X+ryeo~_`{K8avp=T*4jXvJkoGZR@&NbgS*HxcgJNYSdu4LCi0LZ(!km8Z}$0(cX!ThRNuIy z<>tIU`BmTaQO~)y8|S*Z=enBvXQ$6G=oYS#mh|FuLD_NkC(0X)cQ3nbi5K;q{VB{o z5ng@H74JHAmCn8z2V|EtbvD#F*NNNzbgK~;m!0E+GlBW1FnhC2zsWumUN-w(%HCGi z(wC!+vImy&`cBNQkEW8YxLdWw-Y6yV)N|=C1I+`IJaJqcZ1#c1|L@{<53J>G`L;F+arD(K*x_ z=UAJ~dk(SeOLX?m&zLZE`pns16*I{`#9Y*DOtZg!XMYBpUL{@O8;%;W*5D0C#v9H) z=lQ2@E@*RLHO`UMIER+&y)k>Qn@-NY(l;GluZ`KClKfKVVlzic_Flv_(3ssf$zL(M z6^P%=zM>j)Lrs4Y=fuW1BeOH-YRrDO+BzF|9XfDe*Yu20&&IClIiubK`t<9%DT3fXIJ zKW*pbdd!&CV{Bvptc;#MX2PKC8K|8H^qAapa`qh7GGk{Q*`0y>H*@}AG|u^xkP~4%R-RQyN?=oQS;l?rb|lqq1GL-;q0&4 zjqZTXxidNEKIELcklCG4eDXgI>D`;{*xk=L_YCK{W9Z)JoO^-(WHh=tPxlb>&rpcW z?+P}33ex@0xJ%mfq2_-MXMgzq+|5SKbh;n9rOv+qgH zzSB6@AEP;c80OsNb4|~=!#DdH%Cm{*zT`ojtAmPxdQ&0({T5t=kmRGu3{jXQT(W?R-G<1Iq_B99%l2+0n(q z;DOmoN2e!v3&md9Z_5LEtle|%!K<%RXkM?Z-LllGMf-+%iXDrcN}Y@I73VK@DK1c4 zsM#XLp6U7P|L|+>)KK{DpSfRLO3!f4^{W)mpG&3m1m|48O4*Z}^|^L>rak-iYGI|> zua>|3z`1sMd3wG+|26wJO|w*J`tFh!W^c{6l=4(6WKYr0^{Z6)*Y6Z$-*KMnrRmxH zcK>1j>w8-&WZ#IG>sP7Jey)|y?^wvbjnVX3N!LsJ?BiQp z?qmP+L(S|D#DBcQKl>}q(b;9T>R2f3n|>E_w(lPsx)BBiSo~)!}|2Ssfj&9mR;<#QMH;&_&IPMU~o#L2%W4P(O1LJsX z950RI&FOn4+1t54j<05)tF%9i~&>}pKMCF8hq_OYeCMjW@zuEw+{ z#qpx-V@mt_IDV0R0@D69j*S_rv{#PfF4^ZS?E~X@SN1)ov>%USsY||Vaa=w7-hX=e zCUHDw;e4MN$Ct8CYH>3shl$G+K55Tuu{ z8pqwTD=O`S<9JVFzMqU^xnI89$8pW<3Qe!SSsafWkngkO_{s|T{xFUUW>5bt~(*$TgCCD9rAsC9N(Cf?@!~{ZEC)I#&P^k`JNfat7hc;_Bj49 zE8m5k^W(r>^W%s(?z4NokBs9(d*=K3I9B(`cjq{+zhAz$iQ_2;G|F^j;EcO?~CL3PWA&M>Fs?P$HmUecb_=!ctO5*jpKC}<@@e9{&Gpa8!pX{ zgD%gHYsB$@EAxG993Q(n-!I3p-F5k1AdVZ~knio{c*afnzBG>S-IDLG>^_c-2gcfRk9<8SxoyZL?jag_)1<63b%=%IWcAIB#i$@i;qtUsRbh2psBlldMS z$FrW!_vLZ?;MshC8^@(y$anuZPJJogd&cpmSMq&-9RGMN-z{FxkAvULkL$$okhk-F zVjQ1(H{Y+vvBL-X?i$C8! zjN@O~Pv0a@t$xUlLx0MT>&5Y~U-Er&9H03u-*3jT8JTJS4kS_n~ zIDV4-@J`x4#<55C&EB+Eh~tdx$9dA;H;%VuKi8A?!*TpSjNNy5ll33(;kHRgX$lk& z5Jdz87lkZgHcaqPTGHg?kTB6!&?)&FA*wcl_fV zt_zd*i#~0X+owqz!avy)eA2GX{)BD1+$?*hPr4i#m#1Y<`APfYxO_Q#?oZku#AU1O zNkD0LjLY4!X9J}@F)pvoo)(n$opJe9_WYoQ-{*8 zFNn+b+0%p4-Z(CY#N~)|S*WNO9edw&SzA$YU|dd#eq3Ch8J9ET@}{_)9hZ;C<%@Co zUR-_^m%qeiE_;4Yx;=I2GW+=LVt0(o>U6&)>)B1Izib|tt>Ut6Ty}`dE^*l{E*qrF zn(Y0@&MxZTPj+{w{&I4`*-^5lxH+2io8DR%wOcPZ+BXKYOE1Mh@*dX3CUF z`;47BC40C3|39+3UD^LB<@>eisO)ad|NO}Q^VR=opZznvU9LR;^LFXi(vLN=pXvAX z|Mhn1_wWDyxXV8SDE#L5+mKzY zSeE_5I+-y)T-zcG%fG)zviCPU3+eqOOWxlO*>%TcS1USosjN6{x!~$P|JU2yxlU!p zz;rOO9Ex8r|4?vm{Nwac0x-rtlgEdTzt&fcH@F4%UH_t7kSAe!FJ55G1e3(LR1U6*@*jj~^J`!3I}J0`u44%z$rFdY~_{Msei zUjF^6qjp{iy7lJ;qKagZPntE&aSVF1_8rO)D#g#M`6` zZ#OTl`=!&fw{uKt>Eos!bF!by-@Yl!{rjeKklUAinogDv$}Z}EJd(Y?enxhgK5qJv zF8#lf_Ok5l4$5LWkEL@@dVh7<&-5|9TG8N)LImA8S^$&d#38W^c7*?&N7577Tr6aDMao%f78!FnGb1^_RmI z41Q*t>{_?%=Rv8&_0id7#S`gm;-8PF>*=j3vY&Nx2gj;=G+itIGyQ5^Zt0BN!-I26 zn@`SGyY%zsvGbQb+3odZ`R)~+|9GdO-9Nwn{m;N(in)8Xxo60A+0hl1*{^3GZ&AC> zqe~O6sQmM_VL#8^e$X#trw;r1pwYK(HFL4vRFx4F8_ zsAcUcMlEY!H)>hO;g2t?7?J&~%zifgDEpQ66{inQ`{iZ%_7!XY@y?(ntF>FHL#I_n zE$cLVUiP-*|Gjqozt=wd_geMnqqcl@Y}JGd%C~6b;e#I^<2~gUS6Ad0H>@gu^bYN^ z_g0zxY@c6Tll9Vn`ozJGOt)d>4*A8k1-Bxi-Mjv_oEx{L z=l|T66|;}o`ad5tzj&prul%3h@qcd1CE0Ch^Y6#WFJ5K2>us02zUsf%t4BAlzbzNV zZK?a8+tM!knC<`bG4qQ%WPP>&^vb~<7gan~QP*<7fSwiI+Eo;?bA7R*-@v0Q2W0vDtiC^NM&WkjEXiJ*H+BURUY@)j34VyDa-$UpP&7E zb^P}>=NETc?)vJ>U0>th>(!&D*Z+H682?_={^#Fo&FuEC^`G0HU%YnKJO8I2{6GJV zFUW37mw!J_e(^fXUGKWw^>zQfUOjqr{cZ98!EXO^Te6p@UEKXYA2YwWN7j4(r*HE= zx8<_zw)Fb<8!dNzBKX6I& zcKO8vvX5PVj>ygrn=E&IVAY^r*{=-G&Ry-Qw@PQEbPg#DNoToC_Jo<`-~Caqj#)M* zx!kOFTE$w~{iE{d!|d6g*(avj>}xa?=PdtOEZbF;4Gv9T3#_a@HM^T#RaN+-m@bOb zvzVKleS)YOx?=XVrR*t|g%;T-_}s$aQJHN%rQs>g<(qWV2UAzH`i#v$F4xzD;5m(#~$*z}We;v)eZ) zcJ|GLfjzR@w`uIEZ1>D=-)6D1yNUyQX18zi*cpR{`FzLR!tD3I=EsDnQ~jT`D98{?PgNf-Ja&R0PLMFuwA(LZvT6LNfPLZ-(iFSoEV#slVTGxBQ_x?$0p>I z*o2%Kn~>9D6LNZNLe7Xy$eFPTIV(0HXU8rJIUv_8J7v_Ym3`L9A6OQ$aXO!zQ%rJ_ zkP8aw53SapLoSR%L&!xjL&(K3L&zmDL&&8uL&(gSA>^`{A>{IyA>@jfA>_)Kgj^My zkgH=8a!qVPu8mE|b+HM#J~kmY#3tm%*o52^n~Cu0&aKQ)3>R6Pu84V-xaS zY(l<|O~?AuGY^+HPDrE^F{Wiio7ue_13ETor0sQ)`z z3YBqmyz)i^J6?ICXvZsWRNL{&8x8Gv<&7FUUU{Qr$188t+VRR8jqG^kjmEZD-e@9t z<&8SQD{nLvyz)jf!7Fbx7rgSu3W8VOXd!szjh2E}-e@Iw<&6~uue{M(@X8x230`?) zWx*?Nv=O}W#wvnW-e@a$<&9MZue{Mt@X8zQ1+To(LGa2Os|j9tqoa@kX`IhjRpuVc zfRvi1Q%kP0tY~Sv-_ohFn0O^cYgHD~OKH?ATHEoVsIwi4y4ay;9Xk|twL{Umb|~s* zhobIwDC%K{qMkNIy#$KZ6DaB}P}E1DsINfL`T|A$1d28gDB4h`*k)4n?EvP_(Tbing;u(e`#I+QAM*JK7ZOBv7=o zK+!G&MY{?V?IuvPyFk$%0!5<*ipB^OjTI=`Q=n*^K+$-CqP+x)_7*6bAW*cAK+!~j zqJ0I5_7f=DU!dp!p{!`@%G_2NkW$m^D|Y#zp(wq4MgG9bV)B&~O|C4Ym-4AsG{y0u zXsR8G4zWYgp>`-b%nn6|+o9+PI}{yhhoYnGP;|6S(J=x=#|jip6DT@Ppy+skqUi!f zCkPasC{T2gK+z0=qLT%RP7x?NRiNlJfuhp|ip~%yI#ZzNEPqJ`_D>hoZT5D4J)7qQ~t}^n@LXp0q>Jd^;39Wrw1t zZHg8M6g?wQ^sGS9a{@)r3lzN|P_$5>=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQ zfugqriry9|dPkt>U4f$a1d84l%8DMY%&n3=^{KRfIu|_>ioQwru0N$CZWj zQgro-K5={~`qU0ZpV^`4b2}7$VTYnG?NIcU9g4oTL(w;ODEii>=sSU;?*)o}5GeXl zplGo`(Gr28p9G427ARUOQ1pvH(XRqU%LIyk6Day!py&^QqCW+S{t_tqTcGG4fuigW zc+AXx=kt{mRSFbU31vl#Dsy{gKuT|CPcY1X6pB7c=b~IyG5Jc0idBX5Qik=4svRGS z8rq?##tua#I~3L0p{S7^iW=LYsEHkl>g-U|)TXGJKv8pnq7?*+S_l-i6ewyXP_&{z zQEP#sl>~}b7AR^XP_&9bQCoqcRRxOL2^6&#DC!_kw33@{YMQc_Sldq(xOI6|7_MvDU$A_Y>b|_lc4n^JUP}JQHMLq0L z)YA?{z3fo5o*jyM+Z6Q?DC#Rvw7x)5KY^kR1d28kDB4J%Xk&q*{sKh<1d28hC>khG zG)SOmQ-Pw*1d28nDB41xXiI^j!2(4?1d6s2DB4;mD_XlM_d^Dx)HQqZWWIAK8l8RH zGe5Mdn0zHgBdQANrBv(BMI#*_ibmO?Xj?lJZD)s~?d?#sgB^-?v_sKOb|~7}4n@1z z6zwWdw3|TD?gB-72o#MLC>kSBG*+N!Pl2Lw0!8BmiuMvH+FPJ#f=wP9&XjoNly$nd{kaR8@9*V}L&uEjXipf_}bVyYpy%cY~ zqC*`YiVm|w(cyL|I>HV`N7|w2C_5A#ZHJ;`>`-*99g3#e6dfl}bi6>(bb+E11d2`+ zC^|`?Xof)1$pS^E2o#+vP;{C=(dhz3X9yIXDNuBlK+)L(Mdt_{C*R8>sAlA@Vah4fO+^@=WYd?>oy4n=y;7J;H$1&U?~6x}9Jbh|*& z9Rfvn3KZQXP;|FI(LDl1_X-rv7AU$;py+;qq6Y+u9uz2gNTBFpp{(eVs@%K`Na?%u zRmV$1(az~y^hi}P`AUlBRu$4qf!8aV=lD?cxE+d~utU+4b|{)}hoYzKQ1rANiWbXiaro1`cR-~kx*9jXjQJ*Ia8GWKv4d%P_%uzcl}XSG5Jc0 zKC3FEmy)kn^tt0h(HC|o`qB$Xo0!2B2qP##+K`1Nwq$)Qw15%ok&PAVwqM_;Db%R_n`AUjva)tC)5!5RxIX)EC z+M%eC9f}&;p{R)+it6l8)YJ||&FoOr+zv%6*c7!8C~7HC)JmXeMS-H$0!1qc6s;^! z)JC9a6@j9*0!6C|6txp5YA;aKL7-?gfufEAMV$nSRu?E*L!f9)fugkpiq;m&imG$D z^D-c%`RT4u!(921{+sDs)Hzp7zLKJKbA|L*S=1})=J-(5-3~=P>`>Ix4n@7}P_&*M zihA3jsE-|r`r4sreVd|w0!14L6m2L_w2?s3#sWqC1&Rg;6m23YdkYjz5GdM5plG5%(Y^vj`w0~7FHm%VK+%B$ zMF$BK9V}2ZNuX%5K+zPTtY~B|w`#9U(Vy9K7W1P*(MRbE*;8}H*rDiHI}}Z`L(y?|C_3H_MbmAHP7o+MQK0A~fub1#MJEds zogz?lszA|c0!60_6rCYZbf!SjSpr383lyCrP;{<9(Rl(z=L-~FAW(FnK+#14MHdSc zT_Thf9h%FH&w!LhrgPC@p=j&$8STeSfJ<;fucDAMUM()MVIArw`M>}eUhTf zLs9=U9?KPzucYXSTp|5cUiFHebbKh9Z-=6%>`?Ty9f}s%q39Vq6g_K)qUY>T^t>I4 zUa%=zC{XmGK+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_# z?+X-tAW-z7K+z(BqK^cMJ{BnYL?|nom&;{;Jh!5BVfw1$$Xo0!2B2qP##+L7=FC zKv7Yks9Gp1`aGBGlL0B6lI~D{5sKbQ5BnSDi^*3~)F@v_f0bbUxu~(@Ls1hu6xG?G zsHq)_n%SYKxgCmDutQM`I~29FLs2W6q7?;-S_>4dBv7=nKv5fkqE!Tn+6ok{Dp1r; zps2k-Q3rvd)dY$<3KVq`C|X^hXbpj)H3f>+5-3_*ps2GzQ5S)tb%e5_Qa*Qd2BfrW zIv3UE%a8P5O!uz4=8MT!Qq&_~NPiV&y`r9u4@JG~P_&*MihA3jsE-|r`r4sreLEEO zvqRAab|~7=rf4I9qKyTL`U?~d5GdM2plF~#(IA1MO$CZJ6DZnTplAz$qAdlA1`8Ao z5h&V9plEA>qM-ss+Xxg56DS%kP&7iIXrxe9)GeQTA_G!dl+AqiP_%wJF^$R>ldq&` zhkPOZRi^cdc659w+Q|+@JKLdX7dsT~YKNlT>`=739g6m_L(ynE6pgVd8Y@t=r$Es- zfuivOMSBSp?JZC=L7-?Kfue~5Mf(aA?I%#Qzd+Fe0!0T36dfc`bg)3tB!QyI0!32< zilzz_9U@S4s8Ck4T|U=v(@fF$^c|4xL(%+nE;=k9g0q{L(z$LC_2feXof)1$pS^E2o#+vP;{C=(dhz3X9yIX zDNuBlK+)L(Mdt_+MiLubK+&B7MRy4l-7Qdbk3iAA0!6b0itZCAx?iB^ z0fC|i1&SULD0*0+=n;XUIRZtG3KTsiP&8MdXr543bY(twK?bC>aXJ@W6^a(7d)JTW zi^*3~^i;l({wnVJbJ5d|4@C>?Q1px)ik`JY(Q|evdfpC2FW8}Ip&g1|v_sKLHbpNB z6ulx)^r}G7YXU{D3lzN}Q1qri(OUvVZwnN?BT)3NK+$^wMehp~eIQWup+M0hfufHD ziar)7`b41UQ-Pw-1d2Wv%8H)M=ibeLl&(pi#O8;hS?Q7f7x`lHl@xuGFQmW9ysJR`ARLgIK zxI6s;vtw6;J|XMv(F0!8Zx6m=CST34W`n^0ENxRBdB15#>}o_F1(P=2I8 zBAuAJ7mCSOQnX&7aPo*y)Z6i)sE-|r`r4sreLEEOvqRAab|~7=4n-T;p=e_}6!o_$ z8X!=#i9pdnfucbIMVkr~Z6;8(xj@kt0!3R26b%+A8X{1%l|a$f0!2dwinb9b8YWOQ zT%c%#K+#BnqEP}x+X@tICzKWSEaYy>fRwtWJJh{G(S2!bUnnMDNzu-Q!opFZXcxza zqFwD!w3{7@cDF;(9(E`iZHJ;Ub|@NahoU|0P&Ce_XuLqtUIImX3lvQdDB4G$Xre&T zz5+%22^8%wP;`Jm(SZU*2MH7%EKoE_plGr{(G-EAsRBiZ2oxPEP;{6;(cuC`M+jv_ zI~H<3Wk5>zrMp5qg`$Vkx#-A3G5Jc0jx7{c*gh0Zb9^W|&JIP#+o5Q>9g0q{L(z$L zC_2dwMKkPBbg~_aPO&LERiNlJfuhp|ip~%yI#ZzNEP`-*09g1$UL($E4D7wWCMYr0aXqFv{ZnHzt?KVYs z2o&8ZP;{3-(cJn{g{yWBMbA1u z6g_8$qUY^U^nx9V7TTfcMLQI|WQU@c?NIcJ9g1GHDSAzy=yidjHw22_6exO2py+LZ zqIU#}-W4c%PoU_1fuautiar!5S|m{PkwDSM0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2h zR`hfsH$MYX+Bd;j5Q?@)pV7W96qB!{==(z9^Ib#H4~`E-KiZ*au^oz**rDhrI~4tF zhoYr+DEh??MZemiXqipXZvsWX3l#k!Q1quj(O&{Ze+v}-BT!V)ARe|;R4GtYB~X+T zD9Q^I6$FYJ2ox0simC;Q8VVHE2o#kBifRRl8VM9N7RrjgE#ykOWs1`GUGv|CqQ&W9 zf0G8q57qSkgOTFDMYE8C%{jU9?su_32*I`+GGgCSOTW-v)(AV?xpT zjt@os>`=6U9f~%zL(xWdDB9Q#Mg8qiG{6o;o7kafpiR*rfuc6b%t5+Df2kYk{Jn0!7;h6b%z78ZJ;YLZE1*K+!0HqHP6=wi77YUZ7|PfubFS zvZCG%au;PlN?)Y=MSVii>S^rMpqP9mMY}a9Jg{dd+THP?Xb(FSjkZJ47&{b=wL{UK zb|@NWhobRzDB8;oMSI&6O%N#BN1$k;K+(PeMf(X9?JrPtfI!iK0!0T26df#3G)bUn zvOv)kfugAbMTZC!9V$?Cm_X6t0!2p%6dfs0bd*5R(L!0#E)8<;XFy7`)ANgV4Mpdq z&uGUqC?;P?(eVume~%AE(;Xj*POwAKiFPPD$qq#`>`-*F9g0q|L(!>rC_2p!MW@>o zogq+kra;kI0!3#F6rCebbgn?rc>+b}3lv=-P;{X{(M1A97Yh_!B2aXxK+#NrqRRw| zE*B`eLZIkMfugGfimnzYx<)7~n${q<+FqHW{^<_&aiM5h{R6fJ#pEj~y0JlF(+Q#I zCdY@Oo9$3^iyew?wL{S?I~3h!hoal>6wMbXdP<<^ zX`!s>`UbguG9aZ!=}Sa6grXVgT(qD;G5Jc0o^Mb%bz&%b!SSJJp&g1|v_sKLb|`w; z4n?onq3BgR6uoALqSx(E^oC8*n*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MT-QA zJ`yPUSfJ<=fuc_Ziarx4`dpys3xT391&Y2BDEeBU=o^8eZ-ug=XB*`1$bgjIPM^`9 z3q_ZvhyC9*C?;P?(c%V$m-Y)qOB^4HezHT+&vqzUYKNj<>`?Tp9g3FOq3Aa|6#Z_8 zqCaek{uC(sOQ7g)fuer|iYkinu$`hxfubsbqMSfcUZAKTP}D%6s3=fWEl|`@pr}Tm zs3cHSD^S!(ps2AxQ4@ipI)S35LRrxd4RT8}Af*q|>F38#)I5DgYgQ~KUrABRVxi@M zp{SMPL(z(MC~9qoqLu7Ww6YzF+Ss9J6+0BQwL{UWb|`9RQ`BCdsDnV!Y63+a1&TTe z6s;~$w1z;@ngT^@2^6g@P}EtVsEa_+Is!#q1&Y=cDC#Cq)Lo#chd@zJfuddlMe7L^ z^%lyCRw(8+$bghKO^@_j6w8nFo25tkeTv28D=FHbSlIR8P_&`rL(xWdDB9Q#Mg8qi zG{6o;o7kafpdE?^*`a7tI}~kZQ?$82(G~(lTM85n7AP7bP_&gm(bfV*Lj{Vq5hxla zP&8biXoNt~NP(hJ0!7;j6m2I^w7o#l4gy6x3KZ=mP_(l^(Jn$+(fY;QaT$=(2I-Sn zzfiO+myKPE#pEj~8eJ@0GdUEEaeOEmYlose?NBt%4n^bbP_&mFiuSfc(F8jb?PG_c zi8e+13KZ=pP_(~5(E$QQ2MQD&Bv5p)K+z3W1_41&Xc`D7spp=o*2dYXyp~ z6DYb~C@Y#?%r!bBQ}lN>^CyI&r_){S8;Zr`D=E6ASm=6KD7w}0p=g#Jif*$*(d~99 zy2B1dciN%oE;|(6ZHJ`-*CP0?(DqWc7j?iVO}K%nSBfue^5iXIjydPJaTjzH0) z0!5Dr6wMVVnkP{7xIobp0!2>>6wMbXdP<<^X@Q~z0!7aV6g?}H72Qx6DWFLpy&gEq7Ma%76}x6BvACRK+z`xMV|^3eI`)!xj@ku0!3d6 z6n!O7^tC|IHv&c93KV@OQ1rb((GNmd(F?`gB^i*?oTO-BD4LVbML!mc$yZYJbFuKy zQK4w5<3rIeb}0JQ4n@oCQ1qJ}ihj34(I0jw`qK_Yf7zkvZ=0fj1d1xE<6%2Rl>$Xo z0!2B2qP##+L7=FCKv7Yks9KxS z{78Sj^ck&Rbusx$iZ-q;Y<^rQ>hJhaG{6o;o7kafpdE?^*`a7tI}~kZhoa5xP_%^| zing>V8Z1yWM4)IZfugMiiiQdlZ6i=LOrU7EK+y<+qLBhcqXde!6)4(HplEx6q8$W^ zb`&VuNuX$Ffudamigpz!+D)KnccH9k!|L3=8IaO03C>2LXi+*B?NMD!zLKIns|%-3 z4@Kh~ABx7?p=d8V6zy$?q6u~=+Q$w>6YWs6uN{i^vqRDTHbn;r6dfo~bdW&N!2(5- z1d1jL6ipE*nkrCqh(OVy0!4=j6df*5bc8_Bkpe|W2^1YIP;`ty(Xj$W(*%l+6DT@f zplG^KRy3wMcUK0aRFm!sjSWSe6R8ubi^*3~baHj!l@mkJDUJ_Cr`nZXZik{X z>`-*39g5DfL($oGC_2XuMd#WSohMLqzCh6h0!0@J6kQ}xbg@9uB?3j43KY#0D7s9b z=yHLgD+G$J6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Arx=AQ2I;lGMYX+oLN-q;K zBNTN?q;9S*CSOU>ZPkSpPYy-5J3bWMVTYnS?ND@=9g6O@L(x5UD7x1UMYHWtbe|oH z?zbs=K%nSBfue^5iXIjydPJaTjzH0)0!5Dr6wMVVnkP{7xIobp0!2>>6wMbXdP<<^ zX@Q~z0!7aV6g?|Y^qfG^^8!UL2xUdLR_8X#fRwh$W`0&EIv{;UTUcF8zLKI>stdcH z8j4=K@7v2o!xOQ1q2R(bob+-v|_aD^T>EK+*RCML!4>{U}hh zSfFT$P*(I(b#8hFBs=+Ja9$2YrF2*Or|M$zl@$G2UAXS_P_)ePq3Aa|6#Z_8qCf0V z^rsz){<1^S-*zba#|}jm4dZcpD5|t6suC#52^8f8iV6Zn4Frmc0!7sVMGXatY6OZ( z0!6g~MU4cC8VeLP5h$t?C~7KD)J&kLxj@kh0!1wZidqU3wGzsTmR9GU$$*qzNT;7) zLeaQ1R%}>IzLKIg4GUkN8H!eMd?;#bhoV*OP}I&2MeXfS)WHr#tJ$HbqaBJm*`a84 zo1!%Yiq;e;T1%j4ZGocB0!3W}iq;V*>MBsQu0T;YfuimLMLh(HdI}Wv5-3_vps2S% zQ6GV#z5+$-3l#MeDB3`vXhWf_Xr+d^CTC@e&TEjtS-D~Pk^a+ZY}Bxrd?iJjG%R#G zCln2Id?*@ZhoVjGP_&sHiZ-`H(H3?n+R_e1gY8f>#12JU*%WOpP&8DaXd8i|VFE?N z1&T%p6pa)p8YNJ)tw7Os0!7;k6zw2Tw4*@LP69?Zo3RfX?8mO3qP-dx4mmFr?d|wbG{Fu<``Dpqq8*C% zwL{TWU5*b$ciW-p9y=7>YlouQb||{f4n_Cdq38iS6g_B%qK9mX9u_EiM4)JnK+&TD zMUM#-%@rt`Cs6dbK+zKdMNbM8%@-(oN}%XzfuaQhMb8KnJu6W3oIug@0!1$f6fG1e zdQqV0C84b7_J+ANG9aaE(-#`=2t}RKW3-nW7L%`}==Fw$EiVm4Z#X^_y=jM{x9m{# zwjGMzu|v_jb|`w!4n^I90K3KTUH zC~7WHw1PlU3xT4R0!6I^idGaTYAsN-l2BH(tYPk+3`l8kx?l8LD7q+}i&m~FCSOU> zsx^hzt_Vf#93P6>+o7m~9g0@7Ls3UN6m_yg(du?6TEh-SYuce`Et{gX1&TTg6m=0O zT1TL$t3c7Z0!7^finv(O^3i4Y5PfR(2@b+73lS?NGFhP0=ucqTvEXBLs>@3KWeJDB4z_Xgh(T?FEW< z5GdMFplBz7qMZebb`dDrRiJ1$fuh|7iuMpF8ZA&XMxbb{K+&E8MdO6BqJcHJ{uz)` zdZnWLpitBx-Mb!NQ%t^+qJ3%#qpuA`6CEFl_O(ONes(C@-ws6w*rDh^I}{ychoXb+ zP&CO7MU!ocrU(>G6(~AHpy*J6qQeA=4i_joLZIkKfuf@XijEd2I!2)ASb?Hx0!7CO z6df;6G+m(R1c9Ox1&U4*D4HQqbh1FvDMDG%-Zi-sGa#jB(&=YHC~B8Jqn%n)Oumw$ zGiwSrTpxP;|9G(KP}^*9sI}Cs1^~K+z2XMK=l*-6T+Svp~@;0!6n9 z6wMMSx=o23^qSmr8IaPb^o7PVLebIbTy#fGG5Jc0?x`t!dt)fN*YTlfwjGM@ zvqRDSb|`wl4n+^zq39ty6g_N*qDSmdG{>gsQGuez1d8Sg6wMPTdR(CB34x*~1&Zbi z6g?$S^t3?H0)e7u1d5&&D0)ty=y`#n7X*qH3KYF4Q1p^O(aQowuLu;qDwGx7Rg-Ia zQ>JK#^vsaELs5%#E_$t|n0zHgZ`Blf+!Bi3c6=y$#|}mB+M(z@I~2WdhoTScQ1qc4 ziWb?S=p#E6eQZ`aC zvP048b|_lI4n=F)p=d2T6s>KCqRw_G>S9y0jzCdYfueNC zN<-59qV}coBmG;`xoA+Sn0zHgTa*gC_2v$ zMd#b0=mI+wU1*1*i|kNzu^oyou|v_Nb|{)@Q*@a?(d7a~R|phcDNuBkK+)9#Mb`)v zT`N#@oj}p`0!23n6x}FLbdx~Q%>qTY2o&8aP&7-R=r)0(+Xag55GcA+py)24tmv## zZgvKw^iKK?$l0N2boz{Tcd3|sB}Mm@3UAyWitcxOD0;vSMGxAc=pj24J#2@fN9<5E z#|}l0+M(z%I~2{eDVirx^teFL69Pp~3KY#3D0)hu=xKqX1p-CS2oyalQ1qNY(enaD zF9;MZ6exO8py(xmqL&4VUJ)pIRiNlKfuh$1irx^)ita7t{>Xro)<|$>hoXx52W+Kc z@|6_5TPn19C=|Wt_)zq|9g04%L(zwJC|YEPqL1uQ^sya^KCwg5r*p9|Vei6ewCOP_#s#=qG`qp9PAR3Kab!Q1q)n z(K3Oe-vo+&7byBeC@Xrql-nc&Qu;dGyM8AWZI?*>St=%9Nl`^@VeBKJsIoR5$%mpU zI~3*YP?WbrQNa#H4eU@4dBv7=nKv5fkqE!Tn+6ok{Dp1r;C@cEAl$((O zDUC|cnEfXd^~ioL-@dk(d?iJlY6~|#8j4nTd?;GO4n=F)p=d2T6s>KCqRw_G>SBkY zb?i{o)ec4L+7xvYDC#ay)I*@Cr$A9Jfui*Uih2ta^${rQD^Rq)Kv6$|q74L!HWVn@ zNT6tAfujBbMFRwiHW4TqC{Q#=plDNpqRoV|qSb11FJwSUAEk3q$J+8E{ob|N*u1uw zd?iIgY75`b4MkfyJ```=6=P0@A&McWG$ z?I2LJqd?J40!2Fu6zw8Vw5veTZURNS3l!}kP&8VgXpBJ7Sb?HF1&YQA6pa@s+Do8l zZ-Jr-0!8}>6ipP$ingrHHJ_I$8k@d#HaHZ$p8Z;W-`ZmGl@uLVTj=#fC_2dTq3B>c z6iu>2(PTRmO|e7KR67(MVuzwb?ND@>9f}UODLO)+=tzO0qXdeM7AQJKpy*hEqG)WQU@Q?ND@y9f~fsL(xn- z6kTSAqRZ`2bcIdPl>$Xq2^3u|P;`wz(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw> z0!6a~if$7qx?P~?4uPUO1&ZzxD7ssq=pKQhdxf&1b8B-~WN6g_H(qQ~q|G}jJA^XyRcxE+d~uqk>{plH58 z(Nh9NPYV<+5GZ;^py*kFqUQvPo);*3L7-@%K+%f=MK1{yy)01lia^n;0!6P06umA` z^oBsun*v2|2^768loj1yoBJ#SQo1yqejW%#ZL?p?zf)UGzLKI3Y6}gX4MiV1J`^po zL(xZeDEinAMW5KA=uz7;6?PN3*}fubJ- zihdL*S}ahsM4;#=fuf%Uik1o#{UT8Gt3c5*fui38ihdU;`a_`TPl2Mp1d9F^%8K5r z&2`Rzlv<^)I=&x@hNMUO|I`+fucRo~sIc|(p(x+ze;?@=>`>Ie4n;*f6jj@ysG%K- zYV1%{vO`g=9f}&+6g3toY9dfnCs5Q>ps1NZQFDQ!6$FY}2o$vxC~758w4y*!Yk{Jb z1d3J`C~6~6w2DAcTY;ig1&Z1U6tx#9>L5_Gnow3$*(i5#2Bb7M!KrFgevH;U`?Y+> zM#bbSDO$5p;oOCxXf4ObxoB-W6m_;kQ5QQDtz(Cxu68I|*A7M9>`>I*4n;j|ih2qZ z^%5vrPoSu`Kv5roqP_w}>kAb16DZn1plCyZqKyQKHWn!AFHkfWR&SKMKLb))E5TVK6irQ^-Uc@+CSOU>&_;!~UJ6CqI6f2& zvqRBvI~0wuL(xb(6pgY&(YAId+RhF|+uNaN2b-cD1&VeODB4+|XcvK^T?LAE6DZnU zplA<)qR|3HV+4xE3KZ=rP&7`UXuLqtUIImX3lvQdDB4G$Xre&Tz5+%22^8%wlof5& zDEC(eq;yd_7i}GiTBnEo2Q(@sUrEuVMuoPohN8)i4@Fb#P&CyJMTgj-=ukTp9cG83 z!|hOXgdK{Gv_sKRHbqAZ6dfZ_bgV$pG=ZYy1d5IqD4H%%bb>(9i2_9@2^7r`C^}i7 z=oEpXQw54n6DT@epy&*NqB8}G&Jrj(TcGG1fueJTvZ8|;`?T$9g3c?L(!9VD4K7FqNi+%o)#!tAW-y-K+&@T zMb8NoJugu7f=na9QHwB8`5-56Gpy(Ze zqIU&~-V@4-9%__(F#}TSoxY9#a40IK?|{7DsF-{uMISXP{P=b#`q=TI=o32>eQJlI z&+Jh2xgCnWutU+8b}0JF4n<$vq39c%qHhI?z7r_=UZCg)fubJ;iWUnLEfFaCNucOw zfuf}XMZX9X{VGtjOrYpDfui39ivAEN`ct6jFM*=J1&aO=D5_{256mg56v~P|Y?N#9 zPNt}NIu|VpMLVa@XjP4i$yZX;pmCx1d!eZ4_)t`BhoXjdD5|kTQOOQPwRR|KWQU^0 zb|`9MhoU;0qNV~x%>;^?3lyy&P}D-8sHH$rD}kaF1&Ue=6s;ssw6Z`^8-b!#1d7@U z6s;;y)J~wNy+Bb1fuhv}iaH7ubrL9AT_`KcH_q*n0V%DL;1n8{AL(cJw6h0njf=@w zQq;L|;iwNnQ5VODqIK+0)YT3}>)N5Hn;nX}+o7n39g2F|p{SP~iq^9!>Mc;zN1&*$ zK+*aFMg0VdHV`PH@t8wn?3`pta^i{{TL(#BAYU{?u9g0TT zp=et>6m4gRqV4Taw1XXrcC+b}3lv=-lod^GoLeUYQkt30MN>l2pXp)$g^i0} zEXv*}Q*>$L!Zx3UqM42lMVHy3=yE$0U15i!EA3Epl^u$%wnNc1b||{m4n^156kRV+ zbb~PqB{kO?h+`vTcGG3fuef_ie?KG z-6v3Vzd+Fg0!0rB6g?zlKpN-s7dOsL&VZDTNndrmBor-3=c0!j7n84~=&{Cy^S=m1 za~&Uw=Gmd>aXS<}VTYn8?NBt|4n$==vzA!eP@TF?`?{H5GeXlplGo`(Gr28p9G427ARUOQ1pvH(XRqU%LIyk z6Day!py&^QqCW+S{t_tqTcGG4fuf2g@vxnuN`ay(fufv1QC=u3`nYlKpA1N8wFKvr zQ1p5lg(k)1D=BK&q|ol$P*mgiP*k!*QLP<{8rh+!u^oz<*rBM-4n-K3a&B}HAE6!!W) z6s_y{P}I#1McwUC)WZ%%J?&7`%ML~B*`cVn9g6zcp{TD-(fR^K{RE0O5GdMEplBn3 zqKyTL`U?~d5GdM2plF~#(IA1MO$CZJ6DZnTplAz$qAdlA1`8Ao5h&V9plEA>qM-ss z+X!VvU7F-h%Yc*?rpIXOgra}yAFwqkCSOU>s3wJ3KZc@h9UqFevqRDLb|~7x4n;fK zp=c*N6zyz>qFwAzw5uJ8cC#tkU7%YdkYjz z5GdM5plG5%(Y^vj`w0~7FHm%VK+%B$MF$BK9V}2ZNuX%5P*yaeN$%wgNNIlhHvY&^ zbWA!IO=(h0zLKKDniQ5S2}OrHJ`^2choU3xP;`_XijKBJ(J^)?I@S(F)9g@moE?ge zw<($~P;`Po(TM^@CkYhI5GXoXpy(8VqEiKmP7^3PU7+X;fub`7ip~-!I$NOV9D$;9 z1&YoSC^}!D=mLSF3k8ZU5-7S@C@VUoNv_pTnW7)k7a9)@MYZW+|0PX|$yZWzd6Pol zrJ?8w$A_XT?ND@;9g42DL(w&MD7w}TMc3J(=z2R8-C&2J8*Pei5-7S^py(EXqFV)u zW(gGCCQx*{K+zonMRy7m-6c?Tw?NT70!8-<6wMYWx=*0!eu1I~1d1LMD0)bs=wX4P zM+A!I2xUbxo8)%OfRxTj=c3C((Xr_>+M`X1$yZYJc$300zlNeG93P6Fv_sK+I}|-- zhoYzLP_)1fMbFrw=vg}yJ!gla=WU8!5GYzGQ1qfe(MtkFFAEgCB2e_IK+$UgMXw7K zy&+Kara;kK0!42N6ul!*^sYeBdjdu83lx1IQ1qcd(ISDOj|7T77Rrj|HpyL^0V&N& z56k9-qQla;=#wVJ`>Iwrl^%b(TV~^tp$o! z5-3_(ps0;N(JBH(Z3T)}6)0*aP}E+asDnV!Y63+a1&TTe6s;~$w1z;@ngT^@2^6g@ zP}EtVsEbfmR8yB*Hv>|7zhMTaR9Aka-zMF=UZ<{@d?iKQ>k7mF4n;j2ABuX~p{SP~ ziq^A3QExjG^|3=yUpo}7Z-=6Ob|~7wrf5TfqKyQKHWn!AFHkfz zmvk=b7K$pI~46=hoW8WP_&yJ zigvd{(H?dv8f{ZFMxbb{K+&E8MdJjD#tRhfB~Y}tK+yz&qJ0F4CJGeoD^RqbK+*mJ zMF$8J9Vk$AkU-JF0!5PqiY5ybO%W)XDo}KYP*${UUGCuwNNHC3*4cKUXkt1S9a>jR zzLKIN>k98xg`%SzABv8)L(wsIC_2^-Mbqq1betWEj<-Y6bUPHCV27d;ZHi73D4HQq zbh1FvDFQ{O3KX3tP;|OL(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMLqzCh6h0!0@J6kQ}x zbg@9uB?3j43KY#0%8CxJ%T?wwMF*s>T^|vOen}^$%j$~BS5kCUU7~dN^t2s{7TBTa89Nj`Yloue>`?T) z9g1GCL(xJz6uoFu^pZf)%K}BO2o$|4Q1qHW(dz<5ZwM5`k zoWGJdgq&}}J zCSOU>*L8*48-}8993P6lwL{T&b}0JZ4n;rMq3B0D6fL$x(Goip{bYxtpKXek3Kab! zQ1q)n(K3Oe-vo+&7byBepy*G5qQ3-+{uU_uN1&*pX*_JFs8XP)N}wnwP?Q%aDhL!c z5GX1N6jcipH54eS5z30btjoQc0VzG7&HPuPXmom{Uus%RzLKIQO$$GlLQ$RLLs3&Z z6g9I$QFA*Ktzd_u7Ir9VX@{a#b|_lW4n?hPidGURT3Mi|jX=>V0!3{FidGdUY9~N_FK+&24MQaHZtu0X0S)izkK+!q^MO_7o))mT%8a2(e zuFVu}p1uRpxM}&3{?ZIjzFX5`@|6_zYFg;mI25ht_)yf_4n=+JP}J8BMeEz4sGl8* zHn2m{hIT00$PPst+Z6Q|C>kJ8w245`K!Kt`0!5n&6m2F@w7Edh76L_E3KR_%C>kPA zw3R^7)&fOC1&X#2C>kbEG+dx)gh0_qfud0YMcWExMLnA4_Q-&gny1HTJwws-bnkk* zrp4qdDcY%NVOm`%+S&1;Xcs#a?P`aj-Rw}byB&)5utU*kI~0wvL(y0}6zyqKG)|ys zyg<=j0!4cZ6ipB)+DD*hqCnBU0!8}?6zwlibbvt7fdWMb2^1YHP&7%PXtF@j6oI0t z0!4=i6dfv1beKTV;X+x_4o!2{XFy8b(z$5IP_#IG3G#@h#pEj~I;Lsisb-<*SjUH= zX?7?&&JIP#+o5Q>9g0q{L(z$LC_2dwMKkPBbh1s+DFQ{O3KX3tP;|OL(HR0oX9^UZ zB~Wy>K+!n@Mdu0>ohMLqzCh6h0!0@J6kQ}xbg@9uB?3j43KY#0D7s9b=yHLgD}=J5 zqnhTv$$*s3OsAitL(w;BT-mgkd?iKKHZ9b)2u0U9J``PVhoT$oP;{dmif*z)(am-! zy2TDfx7wj-mK}<2vnje=py&>PqB{kO?h+`vTcGG3fuef_ie?KG-6v3Vzd+Fg0!0rB z6g?zR^sqqDBLYQp1d1LND0)nwXs$rfJb|Le1&W>!%8IUTn(LkcDQ%LTy?;$8`aGSB zo@`o7zLKH^O$#Gig`#I1ABvu}L(y|~D0`ko zTG^p!MLQI=wnNcMb|_le4n=KjidGRQYAaB*sz6aYfui;TMI8i+Rud@dC{WZ%plEf0 zqBR7H))XjOOQ2|Nfuha=MO_4n))6S`Dp0hpKv6e=qV57kJ%qBNx@Ngtn@rKQ=}SaS zo0T8wf1J)mJ)0GiucW9?vqHzVp{TFpL(%$nDC%d2q7Cd&w4oh}HnKy}#&#&`Z-=4* zb|~7!rf8r*(IA1MO$CZJ6DZnTplAz$qAdlA1`8Ao5h&V9plEA>qM-ss+Xxg56DS%k zP&7iIXrw^VD1oAF1&X#4DB512Xa}LJXuW2+!5NU!$q7#HP_%zK7wy=rn0zHgyEZFK zY!`}lb9^Y;-3~>2*r8~&9g4=-p=hifiuSZa(KtI4jkiP5UN%L03lvQdDB4G$Xre&T zz5+%22^8%wP;`Jm(SZU*2MH7%EKoE_plGr{(G-EAsRBiZ2oxPEP;{6;(cuC`M+g)h zDNuBjP*${av)ox3kkWJMk^U~B=&JPT?dWF3s^9(X@5#*0B$EI$ zgkA%o38c|Gfl$)uUBM8N&}$Nk2+}*!RjSfdL{vnvASxgz77!H`6%|Frf{K8M{rTLp z?<)y@J?D3xwSH?oe>{h^aOZs`Q!?|)WKvXnZ%tJ+m(#1Fd2CfQpRI}(uvO7Qwklf0 zRz-{1s%QyY6)k0}qGfCpEhnJpP6CQn5Ky#|fTC3d6s;zpXbk~HYY8Y?M?leC1Qgv( zK+!z}6s;$qXafO78wn`dL_pDI0*bZ}P;@T=MfVXU{Ei1u4zq(~L@xNBXvRe54 zwJfWRzkeOeO7d^6XIY*6pVzmn6o0)~%gXSNkGHIz{wEVHtFQmJ#+EhEpVZ8<2KyJb zu&kl}H(FU%j=ywU%Npq)*xs_n`tR*vSrh$VBwJR2zkV0Xn&zLFVp%i%Po-JbZ2un_ zmNnnsv4>?X_Al;bSl~1s&L;k^&EbFL$d%k5I_kTUv zvfl8=O|z_1{(|Y2b=rSmhGm`cTeB?dtiQ_~%R1*@KF_kg@V~vlvcC3LSZrAr{kJZ) ztV{l#%Ps4w|JxOob={w^+Oqx#Oj&Dge^=n(UFHsO1wz)Fd%zV)*=X(pS760vb04?@ zr|&g)f-6vIo4FTUfuTFh-QWs5aKE`9TmkvN+1GLfmlo39f+r zA6=Wc0`kA)Y~c#X|5LGzD8^8Xdea0PxiWbPAJK>p7j zeO&?hUo#AJ1?0c2KiCzJ|2Xibb(_8`hZ>-I51>`@HHQN=C|H{#PSK!Dwa}T)!^4}R*?h43%C}Nc>ApfTSI#)pc zRqgezfc(3*n_U6#+DTgX2@Kfc)g|v@0M#x;f(t$oJmQ zx&rde({rwXeD~`MS3tgf@wF=;Uw>Y71>_5eORj)C1H9@A$fxk@u7ErS|KYMqyX1TO zJDm@?sIBJCY+*jE%2=VX=1{gpm}S|G%1bI2Vm`)Pjm?Lc;bWT@H&?IgvdXs%*65X{ znzs%9sW8W!rK@R4X;uYu4_U5eI%>&ln(O%1ZAOcd^MY^onE7~hwba+_G?(IPrQ?8{ zrnQd4GTP{P%w^yJY2({mKVi{_>U;Qp<{nXlIgTxyxDZlC2_IN3@JcjWRcyzD91Mrk0e@ zI>CcC$`ujeyq(L`uo9L#jFUw~l!%CoXkp&j@bWjjmCw9Yu``d*X*-t{sb^`XoMj0; z%iwE^&a$MQrM^`ub0WLwdiYD2YbTc+2)4ikOT&YoV_GN0A8>wuQVpphr z#Woc!t6ZF`eMPQi-HHKM>CmJK_jIf%rzvk2d-IU;Pj@u8U4`OjQN>(x#U*oH<~B|= zZ(nKYT$dG6VRgp}=1z#SsJ}P?3VYA4y`pV&``RlO?o}YD} zyd)$&))iOJ`#510^MZVGkj@`@tKxr(?+xZ+-Byk{Nr>zBk|ivc`D5NzjK#&p=ViqY z&z~5dpO+njIWLP2hJL2gcbcHV6h3noa&&dr&emz!Vgb@KM+ty{)V%o{as zRKchzxmNth3FC6(v&QC5i;o*SAvZoUKKxTeD>JMIl1xUva&~x8vp z$P3;i&Mne2Z^CGEo9D;(nV6L~rpx5QR55DFb_d}k~?RbtC^iV zVcfV0<4rU805eL?+DVpqV7G%h-Hlzg9ra)Rv0b6=5iYy5yK=PKALkw)ZM)nf;>@lX zZQG&ocIi-89rtuzj;c|!3iKwCmF=iD!Sj;S{Z&| zy8qn+&Ho~m2QqUT+ELEO=Kp>a{{Ql$(0q0@pDC)EN9zCa=jhU*Nrw1+4=oPH5u1u5+@!O`>_@|C>+n_3MM8r;VdBCQO)^Xm#r_Ff+M(-$u?A z@5J?KTKLX1Cp9j5ry3Q$Q_01yufF$9aidJ<91_iiae^+KTL(S2jz#BSZeH_dIg`hY zyUjT#ecL8na0d;|3$K8=w+hd>@Isn!8J&u54099c8=9-^+>GX2oEM5+h31^p+<3uP znj2P6*R=4=%=O_y8|m9OF1jAcg{MeN=Az6M*HZ|uVqeAm-}>66Q|_?IBP{a;-}n)^ znYrV0MrDo996MqB2_ChIK zlf)K{YYi?h?xN$Yd9cw}H7>jf%?-hu7v1sPr`)B5cVi24P7?~{ z7TqU&wvmSsJv(z6&e#ZaZbEah!57Re!RrdIlDRC?1b<)iJqLYzPH66rV39jH_<6?p zxaeGXYI6_hITl?5?qhQc>FWybOLG@Emr!KGJb;+D3Z8lJRp!3cQ<;ZXFRbME)Efbx)Irza+6chCn=I$-JrOiuSyZ4JuZrL(gzTX#@ z7%kuNOK8!kNp!uu+_AY?`MEbm$BxUMIJs@Mx#@DJ#g1#-*o1^KO^%Twdg4-Y~*=Qk1l-*Khq}ijI`(pVA1ow zqNjc4*(rRS4+pt=g^qd3SoCbJ*poS)F%~^@<0B)HM_hSU=iEXn(s}w8yb0tvqdtuc zzN^m1Vd1;a$6X<6Ov`h}F@+C>JVh*e8dvlz4&8-!ec_YD!e@VlPxOj?7!`dm6g^Gj zo-TTlR(KCO&-ARW$;qvv>&XXBhrDsooyQH!&B-y(ko)pI_Ta}7-#fqQzy8QFKN5&E zfB!ar%nvYTl#DE4$xj;iBR^5-P_n|j(E0WP&qDX2kQFYgLre48Ecph#<%%~i+AU(c z#dYhD+T98bc)NwWePN|NWn5)l<=qur6&Bn-nBN#E_F6f8sekMnudUlMKS(O}$8D7^w&e6>E%Rfj z;H@I}OKJ1|)hqTEe)Dqcf9(JGrhlyht5(i`KKnEu690UfUii6Yg*i`OS@SbxbGwC@ zpIXVS5@Oy}aT8)LRNf0Ynl}j^&5zcs5c31Z8gex6vRp@by;zZBGd-GLCkXD2dhDsk zetOK-<7hoj(xdsoe(-ej^|(rpyY%>!{LIT-&JjJHF?Xx%FZB4Ec?V>NnjgN(v5L7H z7Z0J5*^G0~us-A<2F&21)oz8;@9KO>a= znjYPio$c3Ss`=dwd3}F9uB`6t&3b&-+_3Wc&-GZjmb2^WF{_TV$LsMya|g)VKdHy> z>pS~5JvKJK0V1zY(&KIBj*`7lk1r-V`wczXO`Kg?kLl(PmA4*%S5nPzPr}rN9NO1XAjonU89}7U5_7)b@tbKtTDmaae5pv$=L;Zd?er5 z2lRMlva_uz&ave*=h#J$v!*+HxgL+raQ54JjF{!@3VQ4{$Jw{)@t%3k-l@lr7dZP{ zJ;p3{c7h&9Ep_%3JwCSF*$4Ibvw1+0+bd+Hb8NlZIi~1w&RS=$(Bmt2Is3F8ORRTx zB|Y}p=2b^sXHV1PL&TgW|aR;3} zU5`(^;Os+s{PmEtLk~O0_Afcd3_UJ5=Ik|keEk(?pV4FBHD_1TMf z#+o12%WkE|eDmvAvS;h@S@U~YvR~HY-{u#zWJj8RLt2iV&2MVSv9}(VnP1tGy4b?qHj**r%L5~I6=jd^T9yjT6mmc@)@rWMZ z)Z^0wEA3njHD)@5Nuwi+*Q=Ahz#r$?q@tKt;PdW9h zowxYUGFE=KN6*n*H!CjN{31%O`7uDTOC6qV9xe`{>MD+ zG9M|<^IAETd0KPBA9M2s|I{%5l(%y`^FQ8BUMGL*n!j?N{-54X?!SLtZt>sXlKW5o z$o*}enp#Qbuly-UHNPlqj^)f>c^mmFmzQq-avjWz!FMRu7~>Bwbv2>*`OP=y*V6K||SjQK*Zqntqh@OHUo7r)%oyO}FFe0x=4DPJ=TRx%c{_Po{_wg*=H=q&SF70h zl`ya4`fVw88uOx6-<;nTxj_BH`E4+}`1v(4=O_1*yuYQ)U(W9#^Rk>qJjkC{TA8o0 z<-tJz$m`_qlX~Rs!n(SwG<_R6@OFpwWnR_Syd9^JCYLLJo;QDsU%xiR-d}kP;`*6S z(_(p|IRyXAH|N)iVUBXS@<)z*tjIoO-fp6a@;D}sJ#v12^H(mDj}7ypm0}S&M{5@(o1ueUF61V*hN`%(Rv*nwjqk z%AcXWS)DVwIKLR_oUO}zwaWQQ={YmF%06arI=MM!{<**FEX->OOJ7TTZUItOkYGJniyfcirIYM5(U`kGre*|{go`(7zESuZQ?+9`MW!pjP)Q9V5>rC0E6<xsADS^CJ=hn|^Q=kwXu$L_D(aMQ!>Tp4j80~Yr@@Mrfg>kesM zGxJn|HQTu@yIhORez@@cGb{PQ!rM~T&fx3hy_2=I@V1oGZ3(_k-aA{@jkh&pw&&j=8eD|)oK7D1z%hx?MUcP>`(21o^)}*gZTbsJB(1}qorQ_w8M!REH zrOZh+I))y-e$=Wt^!%`hksDni;ZV<{%Qa)Bryb8qAKGW+E!H3JzJ1+FT#zxPd(2RI zDO>&-ke7~r6B3m_GSj@pd)KWR=5ON6)T7^cVp!8tj(!swGu?dT$#piDJXJ3F;h3o@ z*{LsIKQ+-@U#rp3E9R2#Eq2L+^^ylVmmIvL0o{*&6Bbo;xju8bgNj{lj=9{(!pqGv zms>I>%X~Z*zua9hgHk&G<8q6?$L(%>kAs)n(p;{;*yWb~$NQURF1JkK<#sifTP~(+ zde<8+_o0~9DRuvGxy9e#=zn>CE1S!$Q0#Im{p0;jFqd1U@N#3#4Bp?A@`i_S1>(HZvD(yLKple#F%FfrBU7O}za3 zkvHc@hPkF}|MAy%%M42o$r*7rt=+iCUtDx9_|#+Jn(@&q-n@Ct;m{WseU?1@km*VD zZ-0Dr(=)bj%^F|Wo^o$DNZ#*VcJz~3b)K$r*K|+F<5O=R@M5QaZ;i>A-s9YsP7PcA zP$(^UyFX&y|L9`xf6af~?hlyvzgFSoiHpyIWLb1zj z^pE#9-&}5!!pog#F1K0C#Po?bTy9KEPD;N|wNnRIP_a>pJ#^1QE~p`1saj+diix}~;Gd*!<2 zdgc02f9s)9BR4tMrdQJC(lJfCzm?Tz=#7sa9nGaB6<%7BxwMWk?bDNjm*#xNm(Npm zQuFn*wtW7t8GOW)&ko(qXQt|fpB>Eefuu(1mG$$fe1-^#j!!SIpK;~0T#u_sLmQ@- z*0*q;7jzt2FTJF`jXXjpUykV;7QHSeJS}o)%81v8MUC9-yblACu7#CLz7}Iujj5X9 zN_{`8g?=0*Z@KQC)OvgLh@3}vR~Y#4ck;0iAAQUfQDV&HuOq^fT71=Q?{PcxtBs2% zJ+Ub)H+}BP=KfY0@4wY;*QLikuehP%mP4*#C&I0y2`BFwv3$t=L#r$}dHVY9dSUXp z>r{&QJJ9?+Xg-fwtL7ZJesQRIZjj_3`i^-F)%&`yTq}Rf^0YUy!iLH<-k`U-+**rL z%&l%dE6e+zW}Y9-3x1}R_kB+K?847W=GjTs9qBXlv$EW_a=T9pzO8(2l4k@3!MB#% zH9EQ=eUjd0&U2yFeZ~b}>)guM`}er&DH9z%Hho0uds(NmoM&A;vlv$FQm^+lZyAuw z8j^B4%ekg<>2i4k3opIH<<(LB3NO9K)!?c8J+7|k(i?U0FRl+ZmtdZJ9KBxUP+D4AYI@3r;Ik+5xygNAo-1XYA9bsFuGDC5kEDg23t=X+cxt1Rv_ET)b*01f4{_^>k4plVgSq^(a~pYqj>_g1g-qcY9C<(-pm zY~PtC&-~>UO1~T#vn2RPAh%9u<9uPzOVHA_u<|{wHtjOBw)1f^KVw#^`8b;Bd@Nn; z`5zxo{mn;uS$W&2nAg~c&TzPhSeC8 zo~s{Eat+0BR#3ED!w%QBMGYyuhAHN8?B>G9vDC|9?*7HJH|-J~yyj(M`e*c%Yi=F^ zieGC!)5u46iag?*+eBn#q<0RUr(?<*nws9>22)MDBn8j6bWBo4tA9D)EzYAzZ+X8O zrMza&H#zu~l6>67r6rq7k;ekL4;y5N%Z>6e*N^+KMrd66g{-)=_|*7+xesp%NiY(7 zcD^aSep>z12Ijfy#h&uaZFa35S1b6tUaQ)nTzZ|fm#$xomVcg0I+JBy_J5dl{dw~- znOoC*1jVGr6rSq*1*y^LHPULN)-0@Ng0*^j^|a{J=)!v9f;{(G5L4^r`0vlJv>H7< zdTxp6%3;>xIfnw~F;+ho9@&|C>2moJzir!>QgPC?H@7W2{J~=-W1<$s|8Z-R3$1di zn{Otzu%d@r&+Kma`}Q}Ngb)0@%fU0=7pp97miqb&Ex!Hz{G)ID{N|~hU2Ar5ElK!m z+lQ0OExLcv+Uh;!dV13BG&?o4@EXm(V7>TbYW!cmm%q4U>$Kv|K?R8uF!Ml`ywH(urubhAtCl>UO9L#nke5CwL-d8Fh7$s z|MrdjyLpZKD|xFP6^90s*OC=x|8Bl>84~90X1-(K@!0Zf8X+F<=jKh^Rm~f?8%A}I zmk*kYb|;kSYhJd^kA>u-H<_~x^?2&o51Q9`<$v5!SN~&7)y+(_JoR)|GqaK9xk+bL zGaH-#S**?~W;U@r4RlsEv#I52sI!up&CLIAMrTDcn_HeZofXV%VR_#W-)+g!gcx($OckEfRV zRdfG`?-M_@ga0|9@a9H_r>plt^9CX$-G0?j4hqT8ld6zzI#oz_ohqb5t8cu&fNdu zE6w-5J!y`R6Xp@hGuA6|M94(@JM+q*kV$${6_Te@h2-m0Aq6^B$Yh-=WQtA|GF7Jv znWj^P+@@27OxKB!+jS#khHiw+)QylkbR%SzZiLL%jgUFI5i(adLgwj4$b8)hS)dys z3w0x8k#2-6){T%Qx)HKeH$s-_M#ysA2)R=?LRRQT$V%M^S*6<%GTvRnJYzA z9^D9eL^nbn)s2wHbR%T1ZiGCp8zK92BjgF)2zgRBLiX!+gsgSPoBKa}xIBiebA-Gt zFF)lKIU?kME&n5pppfVEq$=c~P8IUJP8ITkP8IT^P8D)UrwTc&Q-vJSsX|`TsX~tG zM94AS2zgmILSE60kmI@$@~Uoxyrvr=uj@w08@ds4LN`KA>PE<$x)E|pH$vXhjgYr> zBjg?32sy1AA@Ax&$a}gG^1g0_oY9St4|F5sL*0&$XWYHa{U83FJok9k5t1X%Nj~z5 z91-%V-OK!#F(~Amo>YZ=rc;G{u2Y4a*Qr9j(5XVc)Tu(g(y2l&=u{zJ>r^4%=tRi3 zx)Ji7ZiHOajgaqkBjg9&2>DSrLN4h>$WOWva#=S*uINU{Row{rSvNwi=|;#ex)E|+ zH$r~Zjga4TBjk782>C-dLjKf^kiT>zqN$7SDTesmluU(MJqJ+=8_PrjT9WmhxXJT3RKtD0?|mWQ#cm~EbxhqEi2ZJw6< z*p9zXWqN%MwaSFxRsjp`-+JMavUPNHEv50wK}_`3k2ZAwq(= zrj-aj3FewsCWK2c*R%>DOoF+lRS8}R=9*R`gi0{iv^v3-V6JI2!6U(3(;5V~1anPm z5<*OnuXSPwE(zwE)*=`nB|M%Gm-~PL;yWf!Puwm?(ExciTifLoUZUtGm;I6X;d)R} zeNL~68n9JSL$)f4Wvik%wknEetD*$9DoSLlqDE|0)R>K;CIl2UC7`Go0Y%LTC~84K zQA+}fS`kpxnt-A<1QfL;pr{=IMePYFN+O`B0|7-H2`EY?pr{i8MV$#K>Ow$KR|1Ms z2q;P=IEw1Jg8%M;&npi_^;FS0A(iIxiZ4;r-TVh)%&&C>74_iss;DPh74>4PqTXy( z)Q7E#`m$9~Kej6B&sIeP*s5qC8%2W%D7u+|qFV?k8caaZ5CV#BC7>vifTE!U6lD=m zG>m|vYyygM2q?-WplCP&MI#6(8c9IWC<2N`6HqjUfTFPk6pbUGXgtADl;LuBF+hCB z%=C0qMcd@DXoAZd{C8W7qI{PqB#T<%_X2{9sx!32`E}XK+!@1iWU)2w3vXRB?J^L zC7@^-0Y%FRD7uq?q7?)btt6mm6#+%72`E}aK+#%)qiB-Lz1#rtWtgwDJ$b5VLGbG= zmsfnrW6^q-{fPOs)}W#doL&`eWUHc0Y*nVj!qHSzdw4IHj z9Rw8ZB%tVi0*W3Wpy)vYigpoD^bi3>y9p?In1G@^1Qb0&K+&TF6g@^j(Ov?I9w(q^ z9|1*A5K#0a0Y&=>D0+&3qNfQcdWPUAy4&S`+W_&!%a>pGsG?L+^sLJ(zC_XUF8fL) zRrCU$JnaqWwt7Mg^i-)1QfkWK+$Ui6unMB z(HjI5ogkp-BmqTl5>RxCfTFhuD0-WKqIU==I!!>)y95-yM?lg01QeYipy&eviasQu z=pzD(&Js}cF~L#voXcIIvM7?rqJyfan|wz5#N`!VqUdv%-Lk4GI?w4<(HCr0^d(yr zeZ^Kq7uc%kYql!-hOLUeWvim^*sACv8%5s}Q1k-jV`2N*LjMJ;4aJDM)u~kt7TNOpJ zRZ$7HDk{lVMWxuP$j??q0XB+C6HpXIKv5Y2ipmmDRE~h6@&puBAfTus0Y#MvD5^|A zQ56D;suECCjew%+1QbORP*j6}qM8I0#SlcN!qR9P_Uf zctS&*uk@4Uv8Y~%SA2=0h9UN`8mcIk)2pI5wknEetD*$9DoSLlqDE|0)R?V`ny^(- zQ?@E<#zs+d0*YD?P}GuuqE-YHwI-mb4FN@M2`FkuKv8=FijoK@>OeqIM*@nH2`K7B zKv8D`inlyYQ5FG3!w4wKCZH&XfTCOiiiQ(VG=hMlkpvWtBA{qA0Yzg7C>l#Z(KrH% z#uHF9fqZyv_%V)H_5U=lTUUgK_R8FsormVdy zqU~%|w1cgRcCuB`{cIFHKtR!h1QhKepy(k2igpuF^e_QMdk83cgn*()2`GAufTFzw z6g^Hr(LMr-o*28eH)%fQ*F zikiw}(ZLX}_!32jLhO(0tD?i4UKJf-tD=|Ks^}jV`2NCiaZ1q*#t+?`4D%C0pgn^k40aoBJ+I$^97sRE51aL&ux#2S49z= zUKK^MRZ$7HDk{lVMWxuP$j??q0k$eC%~nNGY*kc-jiRyy6qO^Os5}8h6$mJ*NI+2~ z0*WdVP*jD0qN)TGRU@FNIsrw|1QgXEpr|GRMKJ^v)gqv%HUUL-2q>ycKv6vcif$sH zs6N3_6y|oXFhG2Z6dMC5rmG?VlT~qJErS74>JUq5*7GG?1-|2C-Gq&1_Y43tJTpW~-th zY*lnC8%3D}6b&VyD2sriVFVOq6Ht^xKv6CMMZ*aw8bLtONCJvR5l}RmfTA%36pbaI zXdD4W;|VC5KtRz%0*WRPP?SeNQ9c1h1q4S?Z@0Tr6Qk(5`JF{iA60ZvzL7oI?G<05 z=r*_Ax|u4P&goUr?QB&vgRP2YvQ^O?Y*jRit%_!|RnZ)_Dw@kyMf2DwnomH{0s@K_ z5>T{=fTG0&6fGg3Xej|j%Lpi1PC(I}1Qe|xplBrlMXLxXT1`OF8Ul*e5>T{`fTFty zD7u?~qI(D^T2DaH27;q#s@px(0P)4jW6?BKlp@crH@dyzOBCJfw&%1^MfY)fRkW3@ zing&;(RQ{f+QC*uJK3t}ezq!lfUSxiWUHcGY!p32K+$djiXJAQXb%BJj}TDwC;>%} z5m2<3fTG63DLr&mSC*sADdwkmpst%{Db zRne<#RrDHL6}`?@MQ^ZG(Frz+P7+Y`CILmK2q=1sfTFhvD0+v0qSFKvy-PsRdju4{ zPe9Qb0*XE$py)#aiasKs=qv$69}`gY2?0f)5>RxGfTGU`DEgd$qVoht(P6jyq5 z6q(=ecD`&!k&A$$5CV$a1QdA)D6$DC3MHV(OF&T=!BO;;+ug_j@wJsN?k}jK^jcl6OeqI zM*@nH2`K7BKv8D`in9Ps^}KBDjLjI zMMK!C=vKBW%4Dmep=?!@#YWLE0*bN;D9RzAD3^eu;RFl*b(HH`X z#u898j)0=^1QbmmplBiiMUx09$|ImCpMatQ0*WRRP&9>rqNxN&Q9qB{)5$2RD?b70 zuZp(HW6?B^SA2=086LZK7gaQq)2pI8*s5q2TNTY_tD-qltvsKZ90*am^py(h0Mb8sZ z^a24zFA`96h=8KQ1V_<*9``B(#3%pBA>O9r1X@mneGKV?UmzieBOLs^~ad z6}`$I^aTM$UlLIC z6~R$-)Z>270P)R~Ph!VZ(QopV{soU$e2Jp(JoYacs^}u8S4H2mRnZS@RrDiU6D4c*I9|1)X1V_;~9(R>)M$sJk zjP|W6a>Rx+da$x@vV~IyDnurU+FiL2c|^ZE51Zg zQ`?@`OBFTa^s1;iTNSlntD=@{Rn&^DidwT(Q5&`@YRgtd?bxcQJsU+y1Qc~3pr|7O zMacvdbt0gsGXX_i2q@}GKv4<-MX3Z7r4dk+PC!ux0Y%*iDC$l?Q4a!&dJ<67i-4lu z1Qhilpr|haMg0hlqQCJK+z-uit-33$|s$j7K->L; z0pjz>cO3_*qPyj>=yuyHzC_V1+b-2#70u@Ks%Q>d70qR8%0YAC|X89(Q*Qc?j)dS1p!4X2`E}cK+$Rfiq;TNw3dLPbp#aMML^Nr z1QgvvK+$>viZ&2Xw2^?KO#~EeCZK2w0Y&!`P;?)`Q8d$bH!(nbqvXr7J5sOh z_KGi2w9~fx4OB(90*am^py(h0Mb8sZ^a24z zFA`96h=8KQ1QZ=1py(w6ijEQ-McZxnbOXe;x8 zIK3)*ovn)AV5_1NY*loUt%}}ctD;kERrD5H6}`hf50Tou)n&uHJ;UhyT0ez5J&2CJeUIlU^n#8yQ=u~pG! zwko>9Rz+9Ys_197D!Rs2MZd6B(RDV8ekGvjHv)=&C!pvL0*d}5py)3GivA{`$O_dj z+fn2qpeTfZA~yj=9s-JN0*XQjDDo0e6h=T%H~~dI0*WFCD2gPYs00B;B?*qAi?%y- zh*8wtOwaeK=zaOJzf`DKe2Jo{P`hrXDk{V2RZ&^CDk{fTMdjJ5r~+FRRb;E8N^DhB znXQVduvJl2Hj1hdP*k0OqG$q&Y7kIVlYpWa0*Y!8P*j_MqB;Z=)g_>)9sxx+5l~d0 zfT9Kj6g4EED3*YtI0A~|2`EY+peT`mqDBN1H6}QU0-^2<1H@NJ9)3!PI$!CpmoNL9 zgnGr7C~6UEkIPa;Ejhg^YQOnwJPXda15m3~dfTBJG z6!j&bs2>4E{Rt=APUQ zY*q9)8%6sFD0+f`q9+L`+D|~yQv?(}O+e8z1Qb0>K+ypLik>5&=pX?_&l6De0s%!Y z5>RxAfTF_$6dfU;=p_P*juKFGjDVt-2`GAn;3&F3)SY91_^!yq&jYGxoQ&h4UhyT0 z-Uzi9j8;V_IK3)5$yP;gvQ^P3wkmpyt%}}etD<+MPCw7^c4X`7YHc& znt-Bj2q^lNfTHgRD7r{+6ulPe-fe*Ry2)p>*Huw>`Lh4}P_OtBML&hwua8wlmpQ#E zy24gPSJ|rQXSOQ3##TkYuvO7@wkrCSt%`nQtD@i8DEfndqCW{J`ip>~zX>R^y!vH3 zid+N~g%D8WCZNbeK#@&AQ78dLUIL232q+3CpvXr+Q3L@+kpvW#AfTuu0Y#+BX&DtcF*U6=NH#g`~5=d}Y9R8e_OuZk+LRZ&H@Dyqa*MU~mA zs0v#ZRb{K9YHU?hovn(Z*(j<(Kv7Ksied;TszpFiZ32qw5KvT?fTDT?6x~EXQGEi6 z8W2#_kbt6C0*c}YD2gYbD1m^YL;{K$5m3~afTAV@6g4HFs2RagRL1LWW`OvTdlUO(Le%<1`$wnGXX`n5FAA6hS)5)K4P&dKY_=-OVXLBCwkjIVRz)M&s%Ruz6^&x6qS0&=jUk|DECEI12q+p) zK+yyOiY5|JG>L$sJOYaH2`DNcplC7yMN`V=LsnKf`Fng2`KuCfT9Zo6n#xV z(KiGXeM>;mcLWq&B%tVf0*Zbhpy)?}qv(X!z0Lsf&61}=Csk1$c`Ul*^@=Z1bk%F` zpP`C==JcxQ8e0|p!d6As*{bMQwkrCKt%`nUtD-;Hs_0L)D*B6!qQ40!vcmMsb`-e? zC<-B<$W1_zhkzoRfTB zMGXlkiY1^Zj)05%!kn-4E6ZoJR$*T8C5qaG*&XJnqV}9#6(zA%Q3tjv>d00_$!t~BiLHt{ zvsFPbLRF9M2s6HwHLfTF$x z6!jyZs6PQk0|+P@NI=mb0*Y=Xpy(C?iUt!CGK+$XhisledG?##)c?3sMR+xK_0pc4gzr8<96$OOU{4lTh5=D!{>=O%A(GpIt zik7lf(K5CwTFzEQcd}K{3bra*$yP z1Qcx`plBljMVkmH+Dt&v76OXyC7|d&0*ba0P_&JJqU{6}?I56NCjmwG6HxR30YwiI zP_&ESC|VfizHET_UX&l5EmB1*gw#V}UhyT09tpFf7OSF1IlU@+jIE0HvQ^RJY*n<6 zt%{yttD+~_s%Sr36+OjPMNhL)^b7$-&k|5{fPkXs2q-#8K+*FA6um$|(TfBW9U`FU zFabqJ2q=1qfTE)W6dfa==w$+mULm09H~~ek5>WIS0Y$G9Q1k`?MJEW3qKCuWEesH! z{63mzk1DDupV3Z+dBv9~dOOS>v{V(n!|7GgX|^hQm#vE4W2>U~*{bLaTNQo4Rz)AO zRnbRmRdkk(qK^qE`huQ1l%EMHdMu`ksKI9|$P=k$|F01Qh*5K+$D_qv%wa`wj!d{1nZ=c}o?2B;Uxs z66O_OqUe_}`@ZF>=sKrYMZdCD(Qj;3^gCM>{lQj6f3j84Uu;$MH(M21;reyEDsr(= z6hc6en}8w@0Yx?eMWF-~c?l>ABcLdpfFd6OMG*uPMG{a{f`Fou1QeAbpvX@^QGkG= z(gYMm5l~cyfTFSl6qO^Os64?@^mCZ|r~%?zDGxu_R8a*P6~evZOB7WJx4&GWimGyY zRaA|wimJ0!Q8Zf>)nKclnru}R!&XJL*s7>DTNTw|qo^(cMfC_Mx`}|I`UDg;AfTur z0Y$L{6vYux6i+}=0s%#d1QazQpr|ncMNJ4OYDz#+GXjd56HwHGfTETJ6tyCts5Jpa zZ3vE{O5twbN~36esDV>C-1$m>yNtHsUhyT0I)vK|R;!|poL&_rvsFPbLRF9M2s6HwHLfTF$x6!jyZ zs6PQk0|+P@NI=mb0*Y=Xpy(C?iUt!DkCs!4fHcyj0i^9F)OB5{& zx1YXC6)orVs_0I(Dq6u-MJw5=Xcb!(t!AsDHEdP1maU4`u~pGsY!uy1K+!z}6s;$q zXafO78wn`dL_pDI0*bZ}P;@T=MfVX4zNPqd4+FRjX@g<7h4Y!jws-pKey()U2t%}aDRnZ4*RrDcS z6@A23MQ7Qn=wr4j`h=~DK4qim905h25m59w0Y&EtDEfkcqAv+3`ig*}3j`E>O+e8% z1QdNsK+$&u6kQ~s=z9W+ejuReM*@m25m59K0Y#SyD7r#G(NzM9ekM4I-U)Y)G(dc} z37pfa=mYuD?6q*O_!33Gh1*LutD@gIy(;>Ht&09+tD?Wys_1XFDl-4+BG+Wu{ z6@bI_1LQDCN_%d6HwHE zfTD&36vYxy6h}Z&JOM=s1QaC_P}GQkqQ(RiH6fs=DFH>z2q^4=@nbWJH zE^JlQm92_W*s3U%t%}mvswkbUiZa-$s2f`qb!Vff2LVMr2`K7CKv8c3iuw>x)R%yw zegqWtC!lBm0Yw7|C>lgS(ai)D-9kXoU;>JU5Kwe00Y#Yv6b&VyD2sriVFVOq6Ht^x za1?d)xmy_^z7b}6l2y?G8M!{M_!32hP_%`BqI(G_x{rXOtppTpBcNzI0Yy6qDB4Lt(ftGzJwQOwg9H@q zBB1CY0*ZDMQ1mbXMSBP+dW3+YM+uIiWIe0Y#?> zD0+*4qPGbsdWYaBdfexZ++`F+$ZzlOQ$?-h_pVR-yy8m~o$=YRyH(K#oL&`u$W}!k zu~pGowkrCVt%^QjtD;ZYs^}bB6@A85MW3@#be@2sF9<05l7OPG2q?NhK+)F(6n#TL z(YFK?eMdmiMFNVxC!pvD0*Zblpy(0-ML!WxbeVvnD+Cl>C7|eM0*bB?Q1lA{Mb`r@k6}i}|D1@zw z+-z0kVXGpWt%^d~s>sVmQ5XS5;RF=<2q=mmpeT}nq7noYl_a336ahtk0*V3z6qP2R zD2jlhG6WQrC7`Gr0Y&8rD5^j}QAGlZDiKgrnSi1y1Qb;zIEsGvxz`&YzAxmH*dMCM zeD*S5utj*qmnfakVPO>9+EpRI}-uvJk* zHi}{iD2gMXD4u|#1Okc@2`FkrKv81?ikc8m)RcgtW&{*9C!nYW0YxndC~8GOQELK< z+7M9GmVlym1QfL=peTueq7DQUbtE{7q9fd&7$CkU)$PLO{`A0*ZzZP;@H+MVSN?4JDu`i-4kG1QcZxP?SSJ zQ7!>R!wD!FL2wjxj&Rp{+$j1|zU$aU70I`WJR>8#;!6~bjj%gEp^CN^lXf0b6tz)aAyV$DeZni4Ahpmd% zvsKXswkq1lRz;iGDB4Uw(G~)V?j@k;J_3ri5>T{_fTHaL6zw3OXeR+h_Y+X`00Bi0 z5>T{@fTD*8DB4Xx(Zd83?IED(5dw-HC7|dr0*dw$Q1m##QM59`z1INo?U%=*RjR11 zd`8&s2q=1)fTC9jC^}9+(W?X$y+%OM>jV_NK|s+70*X!&Q1m7N zMW+ZTdW(Rfw+SeEhk&Bf1QfkXK+$^yN70iJ?rR2!uY|zauZoVyW6}E&UhyT0K8mo* zo9|~wc1*B5XF0tp`k1YXK4Gh(PuZ&I99tEA##Tk2vsKY~wkrC9t%|;6qv$IFiY^dP z^fduR-w;srEdfQ}5m0oIfTHgSDEfhbq8|w;xc z{X#&|bpnchC7|dx0*ZboIEp@qaJMl)e7DNCh(1(BjfB)65nk~nimXU`$U#-)iqx;< zRZ$3A6}j1}$ir4eHd_^ivQ?3nt%}0fswkYTihOJoMG#OFNkCBv0*Xo!P*jS5B0m8| z0RoCj6HpXIKv5Y2ipmmDRE~h6@&puBAfTus0Y#MvD5^|AQ56D;suECCjew%+1QbOR z97TUcxaS%mKCk@7?BA*=*}TqEBho9rL{aTXd&di^s1B!BMRnP#s2*Dt-NaT!_1UVZ z0b3O{WUHcBwknEatD<-|iV_GYN+h7D5dlSw2`FkpKv7cyikcBn)SQ5#76cTvB%r7j z0Y$9|C~8AMQCk9v+7VFHo`9kx0*X2iP}GrtqGSS!IuTIRncygjiF6+~Kz#k=v8Yz0 z^OgQ?8C@d1;!6~zMcUsSQbp;UUKM4qRZ%y#D(cQwMLpQ6s3%($^E*(+McLoq(bl1Qg9A zpy&<)ie?c|G@F2;IRq5VC7@^?0Y&o(C|W>3(Lw@>77fq*r{2qIHq>5qC?q;i^d)TUI zJzEuRV5_2yY*n<0t%^3YRnZo7miq=HB zHyR+mRQbK@wW{b18T%u>;!6}g8)-lHiYhw5=~dBlY*loSt%{y!tD+a!s^~?wDmuhg zMTgm{=m=XCy~IY*Q38sN5m59p0Y$G6P;{JtqE`thdX0dh*9j1_VU~lF)mv0*V5PH3SGnX;PG?D2OO1 z_TGEL-mv%Huw%#GP_ZDWsPA>nI{!(0o_Fu9e*4*bfA6t#9B|Kh&fGI=X8mT(nqBcNxGz`q zZp|?Ev=qI^d@0&UmZJB`QuF~?iasPu(MMz{`j{+5pOB^KQ?e9&Mn=)+6e#+F0!3d^ zplA~XioT*i(bp6x`i25Un<-HAEd`3cqd?L36e#+E0!3RWQ1l}OindaqXd4BJexg9p z&lD*7g#ty}DNyt)1&V&7h!nkDGrpq%Nq*;l(|<>bcJgQXzt>E-FIN=L4Tn4{McKK3 ze5N0gr6`9iMG3MLRU=DLb+QyC$x>8Dfue>KC~8E3qQ(>`YC?gcrW7b@MuDP23KTV`Kv4?{ z6zxC}DT?LBryG#uy$&ZUH+qiN(vHh+nVWE5uBdfxc;fR?v@`RyE!u@FMZ1!vs0~?) z+LEQH9a)Ns$Wl~HmZB1}6tyR#r~?IxI#Qsh69tMoQ=q5|1&X>-pr{)Kin>#vs0Rg# zdQzaM7X^xXQ=q611&aDopr{`OiuzNaXaEI@22!AC5Cw_`Q=n)F1&W4JM2dFIjo)HG zlHDE7PEypxAKr%LCft`R8krluyk3fSXTB8eL6)LXWGUK{EJb^frD!x+ipG$oXe?QZ z_9jcwK4cV)qd?KV6e!w{0!8~%py&V!6dg!`qJt<!cS&EjBQFH_aijJf} z(NYQ&9YuknqbX3di~>c=DNu9_1&UTspy*f%6s@E{(QynKpPmI6iBQ=sSu3KZQ)fufrzP;@f|if*Am(XA9Hx{U%w zw^N|#4hj_ANf9YJBR77G0ZG2)zjZuQith4f`s;EN?#mV3n;Ty7x)j~Vd?~u0EJY8H zrRYJj6g@8=s5}$ zJx_t67bsA)o&rTLQlRK13KYFefudI^Q1mJVie95Y(d!f_+CYJ#Hz-i_CIyP#qCnBx z6p^C4bK_4NkYsg#j&_d}Ev{+do!o@`az*dwhF`uRMISIQbPn9tDc(Q=q5;1&RtNP}GnDMU5y>)R+QAO(;;* zlmbP~C{R>LfuiOVC~850q8%tu)RF>4tte2mBSoYrJ1@Ss0ZG0WH#lKl^i1FOwCxF7 zUc!C3qFwXC!{3#nHq4izwqz-4N0y=@vJ@4QrKp4~MeWH_)PXET9m!JEiHxGo6e#LK zfugPyDC$OmqV5zZ>Op~`o)jqRMS-H;6e#LLfuglnAqTMJ^G@K$*v~ynkd;^kP>#ud(MT+u$TQnjs;l5nasJ!sLjZ(BH z^QCAnvJ{ObOVJpz6pbZI(cWY!+J`Jf6iuc;(G&_4O{GB5Gzt_QOo5_9C{Q$=0!1?@P&AVQ zMYAYSG@Bw)w0mCs0|Sz5>#w`sLyGqDz3W5s67I_t&Cd(tA4<_-%$K6W$x^g{EJX{+ zQnZLHMT^N&w1g~0N06oHNU{_yC8Ovl3KShpfudy;C|XW|qGKpfw1NUf$5NnZB?XF( zqd?K|6ewCnfuhwEC^~@xMJH0AXblC5PNG23$rLC$g#tyVQlRKG3KX4Afub`gB1Loa z;;jux@-W{P&6A?pzIT0QUc!C3qI2`YVIND;dCZrh^T|?l0a=PJBumjnWGT9sEJc@) zrRY+!6kSG^qRYuBx`F~lS5lzpDhd=`O@X3oC{T1Q1&XetK+#$X6kSh&q8lhsbRz|d zZlXZZ%@ioQg#tylQlRKI3KZQ=fucJoP;@5+iq=t}=q?Hr-AxfGIy)~u(|{!R_uo36 zBSkm(w&eJVu{GGB@wB1_T3WGQ-tEJcr!rRXuT6g^Isq9@2w^dwn| zo+6{@X$llQLxG}aDNytr1&W@hK+y{nC|XZ}q8BMp^b!S%UZz0ND-$YtQK0B` z3KVUiK+zi%D0-6uMQ>4{=xquVy+eVbcPUWx9z~?+zP$Kt1|-?p_pa}kqV4{s{f&7E z_vMN{$_ropT#7zsz7%~zmZDF|QuG;FiasYx(HCSX`jRX~o5)i16c5`ZqhNT~Z16<%-&+!m_WWsEGMeR7{ql60#JvCreQW zvJ`bBOHn7X6m=#`Q5UilbtR*y8wHBGQ=q5^1&Vr7pr{uGih5I^s1F5-`cj~%9|el~ zQ=n)71&RhzplA>UiUw1lXb1(0hEkwt7zK)Uqd?Jc3KWf?K+#AF6zxtCDQc67A8SC8 z#r}7+wo+8)VUJY8eYv91sqm`JQZ$D7QZ$wZfqV~QmnwLtr zFITi66@K-d6fI=F6fGi4(PFX`Eg?(M5o9Skk}O3_$x?I_S&EJ(OVKhiik4HL=oktV zt)M{Bu@op;Nr9r{C{T1f1&UTtplCG(icX+F(TNl&T0?=NlPFMhG6jlGp+M286ev24 z0!61&py&(=6rD+dqO&MabT&n#=&)40*7v69X8%Rw;ZpQzXyKex!hN}-3sPZ+EmCwL z^QGt_vJ_oRmZD3@QgkU76m2F;(YIt2eMfH^a}-w zwo{|x|5}-2N^{@DNxjl0!6(k zP}GM4MSUqy)Qig8yHTKMI0cGEP@rfe z1&Vg3K+zr)C>lk9qCF`hMMdfOYy*<)?AxMZDSF$(Ug?DUaz%Tm!&3r31N-EeeV8vr z6iuc; z(G&_4O{GB5Gzt_QOo5_9C{Q$=0!1?@P&AVQMYAYSG@AlNhf<(u4h4$lQlMxa1&ZcV zpy)7)NYR*d{0;+>Jk|enHdcz7`ZN8*(+T(GiWaBC*R!N(3G=1s2(lC%NtU9eWGOm| zEJa6?rDz#hik6e5=oqpTtstZ5SPB%aq(ISe6ev2L0!6DRP_&u?MJG_8=tK$>t)W2C zNfanLnF2+pP@w2k3KX42fuhqXP;>?biq51!(ODEII-3GT=TM;NTnZGOM-eGnn2v8Z zAj#ML7mbUg=tbWaou5v)FIRMNI&2b3(Iw26qD#qAbQxKSE+tFWGVWdEJZ(%QM82uML$xYXe$MZ zwo#zyCkhn(Oo5_bC{VPW0!6=4py)RW6#Y(tq99*S+ffvwKv5P2isBR~%BDb3NP(gp z3KS(MP*jZqMb#-#l%$9heU^?tZ$OeqSq zifWOis5V)O>X4D6ewy&fuceR z6g8(nQ40zb?LdK|mJ}#zMS-FnDNwW%1&UfzplD|b6zxKRqFpIa)P@2@Z7ERHjsitR z6p^Cb{CJ(3rl^|#1tc#&dZvGkZ;Oia6Yk3ub<7Vts$2DLTmauE*vl+?OlbH$PmQmZJTbFGc&4rRV^%6dg#GqJzj%R7#ej@nk6~BTLZ) zvJ_1uqi7NZipnWaG?@ZLQz%e0l>$Z6C{T1T1&R)#K+$vx6wRPO(M$>y&7wfjYzh<| zN`ay|6eyZYfuea7D4I`!qQfXqbT|cy7EqvQAw{HUpZxg61|<2N{{>{66n*8tf?SlJ za9^(I$o%l3T2i!>`BHQgS&EJ(OVKj26fGx9(J^ExT0xegW64sqk}O5Xkx_I!1&UTt zplCG(icX+F(TNl&T0?=NlPFMhG6jlGp+M286ev240!61&py&(=6rD+dqO&MabT$Qw z&Y?ijxfCcmj{-&KQ=sSq3KU&P5h+@dAOFOFB&Yf2=Lji!+`~or3HRlSF3S%Sb*1QX z=1b8PWGT9mEJat5rRZw16kS7>qHD=gbRAiW){>>@dNPV`pg_@$6ezlh0!24dpy(C~ z6x~XJqT47?bUOu#?w~-?ofIfqM}eZdC{T1a1&Z#WK+(MvD7udVMfX#n=m828JxGC~ zhbU0=Fa?Spp@=ROC&&TWuTYkcQxuUP~!_x|+=xgRn(Klo%+Dw+BZ^=^h9a)OL zCri-}WGUK0mZBfYQnZzfqHPo?`iTNXKU1LS7YY<@r$EuK6e#+Q0!6=5peU%Nr|l?; zQJ^S`0!48O6lGJOD5OA94h4!56ey}jfuiaZC`wYGs0Ia!YEqymmm*U1Wqy2}0ZC^2 zwrGhyjltO<%(+63g2iXMYWkPMRmwhRF^D8^~h3GpDaZU$Wl~5mZFAaDQZNP zqQ+ztHK9OJQwkI{qd-w11&W$epr{1}iguttQA-LGwW2`Ljua@`i2_BfDNwXC1&Vf| zK+&!gC~8B2qP7$$YDa;hA_^20Q=q7X0!8g9B1P$1@!t$c@>~BEQGTuHnf{r+E$UD! z;l5l^ms(-7rc%_E`BK!4EJfYPQq+SiMLo$<)Qc=dy~$G4hb%>X$x_shjH3P&C>lV4 zqJb1B8bpDj!4xPOLV=>86et=-fuh|gP&AwZMI$IsG?D^EyHlWO4+<2GqCnA}6e!w@ z0!5=KP&9@DMPn&Yv^NEc_MwOrb*dE~Xh4!Z9ZqK{8tU7kakUce%M~3^D=aURq63*P zMF)|ksFW;4P!1IWwlhUJ)5hU zDzZPqrBi$620@+F8L1#>ka{aW2pXrF*9n5c)RcNb&@y#>gCJ;~`o3Whv`KYq5(LGm zrOkq%W9qTyLC`f-qh%2EOzpX25cEx*)j9|Urry~l2!^J1Xd470Qq$}MxJRXKED3@! zsVyCXU|gz4=O8#Bb#&Jt7@vBgdk{=Y<@O4Ksj1O@f?#^;oPI$tJN4dxAefhGH8=_6UOGQp@)Yf)i3tjShm7Q>nd!;PlkkaY1l)>b(7e z;QZA42L!>zshvuL;PTXrvLLuRb?d|+SeyE(JP2+|^_dz3x20Ab90co9&rA=3dsF$d zg5bf_K8FUuqp1t#2Emi559bHLv#FgI1i|{$tVKcaO6v9{L9ik9%aK9wcBWosao9&oO$f>`?a^KBi((l1`{WI2<#M1sDSx3dv{wYVt#M1X|v^5k<`{#_D5KH?9 zMVuT<`#b$lkEQ*s+Goeo{$AVjV`+c0AW+OZyuJZi=P- z72mhT(*Ba&b+NR+=JMWH+FvyHU@YygdU`aL_Lr?Z8B6=?4xWvr{SU|MV`=}(-z%}S z|LJB!EbYI0e>;};U!HD^rTw>GAH~xC>x<7~X@CB?DVFvp5SwFZ-vj(1miCA6ZLzd( zgSW?m{I~sg`OA7Vz23nb;|QDs6X5Oi*;5=`Y~M;*80@0dCM~=Yf#fdHyyLo zE+y7o;bNcDL*Xh9JryR#Ec8-H`?>XwLW9<}+_65HV8nyzz95JDg7l3}P+%K?z?XmU zPO+e2Y*bkD?7YL8cfYzK zFLTzfH~qL}(5Q_~8Dmoly4nF>u6J3kHs@W}J2Q3L^xGR{7HjLX$E~z;8=aGX{fo;V zUmO&S)0}*};LLS7ut$s1%yoJF+Ah&n!m=kX`0$9# z`Mg?Z!f;>k{2w2^e~+NxY0dd9niJMs^TK|IWG?yGQ)d=tmizsc=Pb8{vE_c~#O?Rl zMfbNy2fwn#JL~r8v>{Ap<{Y#5=7TervbNq!yZWWnJoVIMwV>c`&6voHN8eq#V`jk~ z`QpM2cH`R`%+9*`@XVAu8=tW#C}7jhO;#=dySh|Gm7-sgdVnFV`v!)M=`EL*Uj zFFg92g*L~S`+_~goI`tDYS+P5!hj35MJwU#o34K+n)B(CcfD$tbFJq59?i+gUw!V{ z)0So?6%{@f%Usa9XYX9*Yc8z$S&iy_ZGG9D#xJMCE}0u3C;!}29zQR-p`Tp6{T4fa zyFSZK>XOdPIj>sz@Sxya&6&cS=hi>`y9>$5zx(WW)*GE-Y^MnJh7@t|%Sh3F#2nzCSir>v1 zil$`lW|NcA*=*r#dOfvMqIWz6D3)X3JIg_`Xam`238%&|JtZf9?T=UAVC%rn z=gA4*w#_W~-7l@!xFBe>i*3A)^M$Bm+eE+dzKmwuI?63`QJLTHqI$|J{wZjmli$^-o>7Y-v!i z-RAfPYjiXxtodp8@@ARKDcXKe$IRuddHmU{qsv*n{L|muyKU`#&auqdka(bR=8A22 z^t=zED|YD%$5;0oD1Y6nx9l4f4AqponexK=%ZFs9eE7~SH<)2twEMrk+BRLb5?6h7 z`I~li4$_=&n6vV8^KG9d2(nrRHEQ&>DhT5Bf_Pr{8a--st1--$CR@k&x@oJpDMvdGWHEVRWWvEvF52vbbr>b(UNyRX_kQzEmi++|hb(Wc9 zE6*}lXQ@-=*`%;?Ia0Z{bbiU{%mLdf=Ifg1LTbfg!)p84*KTg7EV2{S=~!i<`V{mm z2!gupVtoo&(wz$OW3_VnHaM$)fzPWKRylcA{X6^H4OhSFSv0mwZ&0<+i3*Ni7PA|@ zBy;HvS1pSLSq)CkBz#>54Es=c7zXaR~+GoHbzJI;JZ}O49>h}%zg-&F>U{61;rQn z_@8`XzHj4CrF^ZaMl~0^kKB;KpoQ1RJ&GKSm`K0-C%I8)&&QEWr?p8E=&a@fR=1n`S zJSdtvYesod+4S-SMeU}~npifyXztXqIpsxj%4e3(Et^|Z-oAA1y!n%+%_^EVYu5CM zQ_H5!oLe+y;>6OjIWvk%ic33`wl8j9Qd&~%Wm_xT&YU%~ylr{eglTO{iraN)>qob< zqyKPJ(X^Qpr_Y~MUNoa@;?!v~|JxU1?!viMZ;2^Wi~7x(G=JL6Sp#OxDQ{bGTP&D2 zCv%fTx5%hDvktb~d~VU`*=2JM89aYx=@`2%Q$|gnKeu$Rew{~l`p;NRhn3AM_ggCn zq7^-P{>+KRT{^UzXyAj=N#&Ev=1-qjI&b0Z^11D%x-eT^lcvp_XTdg#qX!HswZ)t` zVAhNovu0Xn_y9A_&pN6Cdm0pGbjCZx!m#$g^%KT&;!|RUVXb&UVHg&NwYrC4PV?Hm zdWE%eY+g=p`@KP|Zdk*IR9NVP^_gg=&uQ-`D+&u+gteOZM9pgPCuW6(c4AL^DtMm6}{l9c|Y8%vA&BNv`!rE@LNH&ZAV6%Bu(d{y# z>pJ}5VeMf)si#6T zTk6a+(NEp}|F0)*9=2=|)@x!{p?T&i{0G-GbHxk8%=K<(lUmxO+R=G5u5uoK>b(Bt zx7uI4ZvXP-`PX6k=WCkPyH0d>_tnYV-BHbahUC|BM zs_I?e?*i?^0-INTcvyd!Ps+?HE@~RKwEIS*Drdvl{gwMhQRd42>3gRyOaoh(+U>%Y zt-{)V>CGv0u*i?Bp7Y1+^ncl$+1V6@)k}N}>$gM{ZE`b@!~K@|@4b$8%d`(``!=V@ zZ~vmO&Y!wknUmVpsuNwUDB9%z5mzg-G{O{F@9#j82*H+e`|8N8Pzw67NGE~_I z`tMv{|KSeW|E{gSwzhaQEdCphhV^>44O{LI){i!1z8~$|>1g~9SCpOXZ#?e(`}TTe zF8qJS&b(c@zp~4%-O_*F#ru;t7cVq( z^1sXGFJ0DOIDcWM8XvwHc3 zHUC?;|9{D>%&IR8Gi$z`t@)O=ytTvD#ed|I)kizw|1Ox!w5I>QuAUXT+S;M!c3BOF z`GF$8o$Nrbuu*0#3U{9S-2PvC;-aD!_A7-p zEyJeqg?@3-FDn1-v3X{3{@hY$9(XfnZ4bQpc31VQ{m*Aj|7UK9qRh?Kq{_MdnOT47 zwr(D_X%RO4mtMqQTAqL1i7QuqX8rtItNy=Y{n#!3XYUI};BTy-|3TOFKmC56*=7`m znN3DJyKC5;*&ibFZH4-c>f5BIJ^TP`xL4Rr_rzUntWy})&FPeRgsp22w8JbFg<%K# z<45i0MZ4M`FNWK}x>f%m!XNFTKakj?LG_&Y1-ALf>_pjPcjot%p}q4e>>1tX?ShBd z0u+UH=I=Faf;A2VG;-RGzg1t)p z&zaF5K#NP~w2zMK+%a>UpRCh>ii4fIYHG)>bp1HD;*QaAg9hj{C3fOzBWBH-T@sA! zH?DNR?qhV`1DVn(S^&F{E>s;VFSmWgE(su>f|1R-ALig>>XH23Fn}b`$7?w#b=tFR^op4pdo$ zE=;u>FLR{bu$tGY;>>J$xX|`GeTT~B7*H{zWB?as3$7V1pvsFI{pwbq#nl5^apkq^R&h;A z%y2M#(7vVp2JV%aXRB6M(g^F&z(35aa$hMa?hyC_7H0nYCv+v1i`8GQ;Abl}b8&d9 z5Ec1#+=DW+5BB>`=A^|s3#07IRpky_!X37M#UlINIy0+Z<+2Yn4gK~SQj+N_+^{4i zT`R7+qtaD}5|T(;H@wsp`sb*fyR2ubGVkPADP zk}3|WtpCn7y;3V%M!VIb%l4!FjBL~;m)H_#D%PiMlXO&viks4I2u@xpf|bp>u2{ca z?TXH-AZ>6om&Xm?+NiQQoUzf2ZbG}*%mKS4IIi+6GK=I7V`Jpk+vM1(GH0GSs`5hZ0YmdEu9H!W z=G!*cH-2-X8>l22^k`WLqoh(s1;$Dc_CRdsKX>Y^IrAzW`&f&PEwlbBR(-{zwB405 z%iyaggUN1<=s*<>m21DGa`l%~u76fei7jkqvOSDf-A;-!>RnbmNTSsBZ_s-@`n>DlTTzh4l zjdQJ=R5q`yB1boc?Fd8%Dn*x6l6I~C)}vLVw#wsc1x=%!InT-+LdWV-D)$R3_XbNM z{~1WOK@a{jUsS2rWLCaZFLNo;-KydNICC#5E&b!Z0(-pL;f=PoRRI=v{zK{(>@j$B z#eP8vySSCRtCf4Hl{=}ny9?6juIP(bac5!&H`@0cT{?77zfqZ6vC1AOySbISo7_45 zz7VZh_Ioq;AiIEQpEGky_>QjjeKWU0v?-{#Ww`5C+=I9S`3~V&v2Fr7f z30Gtv8(*2VCKmMTX2+KK>u!TsksS=XwjJ4SWWQm%2RZqPk=5hLYPGWK#OlWC#~Z{7 z>}@QKVvS=>vs%R3{qZHxnTx1eWe4B>&gJ?T_ZOa4`HAag%~WxJ-D#DdxV`2yze@HO zK-+sngO1Uwq3uv~{MstnkDp{OT#tUD<3FpC{rI)^O8u(GH@3H>lKuGUdO11g|526f z$B(zyghxNo`TNVo$$tC~RWir;7!NY<(5tB8LB)b(x_D5rAj%aNtZZ)vsqzyK{`e~J z_&?lQ@yvTADksE)T9v^L#e=$my+A*+R@_A`yFFW1IfcKL-QGD{@#A?&MY6XM*x~*D zAy55>eAqwaWBwtp{)c?dKjdrwA^+2BnOn{aT289EWzz%gANQLpQgN5e^MBiT{L{0r ziqmBFs4G(OA2yu+oQN%3m6LS)!xBW#SSpXUT?4=6llDetdrO0T#FgFFc2`K+Tbf(? zSQyw_Y;A1r@2a)YPB%tlp4}xp`?~^@E$qDo%H4gm`6HAc*Vx-$rtPP{Lt{I$@A+aI zvvvrAc1FSKMoi~G2PMt|#y=Rq3xx7)?@6pa_#{nGRG z8b7fc!1MPS+t>!jb2p81?6&Z{RO323?D;W`zcq|w@Lf`DTq@42bepjm3kb z+)LwOL!-Q081d4G+kpC9E*G`@LZlt0y2cuADoYMgvol;>((dqtG* z()is~QT|b9XzXhrrQ!2OYCP6HQ^WIV8lSZtDbH_ctYx3F z;klW{arSW=p35~}XrH^``8tgs*#~fV{#N5I_DLL`yJ(zU808~0-q9k;k7#UcAHU(J z@2+vM#*sdT_W35tQ+%|?=tDHlR)2)XRT|IIc)7-#HQulB8I2n>eys63jlcS6mlLxO zsqit!M_azyKHBmO(YU|HSsE|Zc%8=gG}f{m)66`Lqck3)@hpwcX#8DciG2ow&zq$2 zY>m%q4D8ba{P>O=FZ;Zy3 z8t>7#Sz~j1-@M;mtu(gN*j{4~jeRr@)i^@qSdIH?oS<>C##tKYYFwi6D2>N!JW*qw z?`PU_`|}4MGyA(X+U{B=+iqB9Y^|}qM%z8g^tRiR8T)A*uF-Z!GQI6)WXAn8F4B0U z#$z?E(r6ERnbV)4@gj|vX|#u#%<(s9T&M9~jka0O9B-TN%$Vb&UAeTf4Vm6{pEKiJ z->#y_IWK7EzdH=tO_)13XlK9eZ0BXW zs()6>{602w)Fl7Ioc%R)@+_N`Ib1ej!kqHMqKQ#sZ*Z;}%jWp=N1b(aihpjV``eRs zj<#$;yNUK*+H(7oZIw%%Jg01iov7blBiohDn>T0Lg!%LAZ2$a^?Z(@d*Y4+<((xar z+Rc~wX>R}f>EcoJ-ReL5_;LQTll`k^|Nf)X729e4@p7xa3EkJ9|Fp4x_Eab6YybSG za8}GdGRi(Fzz+Lq{GVT*yJQ*cpnb@fJtwvM06!cWVnx;S8#mjIvFA>HetsKpe*4&A z=GejDdHeW8|H2=BI5^D;4*PM-ddGq{I8l}3%I)wUE_bngsFQVmx!!ZR3+!;!^V`2q zEGV>&AC8-6Mb-1`x+Ipl5BT}n)u}kY)pnRUb}(3M=jZnoemHKW6;;n~XqEHJwc}X6 z3+ym+{5)3M`324VQ1rub=UA+Ie&g)?d_DQ{*{Z2HziaHU&v6g_v-+S|aC^<@u>bGJ z`M=vVa=N~U#Dd+d8dWQ8B*=L9<)bG-BG;Xn7;zpBeOzRLBjZO3tapSQzidA1Fi zpL^~6x)W^VvV7#e;zw_@)6KS`z8!9C|NQ*Y_RlYq`-UA1rp}B7zK!FD^UJrQ>gi_N z^4Tt7#Sf>e`quo8?Pe9(-;_IdEpFeneTPE(9dB_-mH#_;?pRpZwL`ZK?F;>9d~)fa z5reCK4n@p<`@#A81x+8ANnvzfZ*A+YZm{|G;om(tr^!xxY~G<}{T+{LUbj{4mIcG# z+qPh1!O%yxZQA(Ww%Hqfw10*6??L+)=~a8tsE!~`qj{&8PfBOBQBZhJ9gm}BP=Kgv(FN5S|^mDptKE~}copvZ^B z0$V%T*`fc%AS*lZqMamO-A*2FQ@fuZKHDxnUR-C49S%?O`LUcU?ZR@hvv&-yvf~o| z?WsHI6S13FED5q(D>k**KFHo#v5CbFLG~_+jV*QzvUgQ%WU*6_-A1vY#m@GnzlsGG zy9C+o6dPFV8e|tK*0E7$RC3)Vrowr5+ij>@$>+oE++ z&i8D~)>%32*%q#ga>}zUU03Bi&$f8olyg1X@^x3PX}P^EUk~LPo^APhDknYL^7T@# z?%9^Fw{kVlwtRh*6P|7P`YPvmw&m-m9D26p>#v;c*_LmBa@?~m-$3Oo%N=a_1}Vop z+wu)oHU`zQvs=cWvh`p69rx2J^O?@o`Mo~h>Dk5ZWWrXabjF5542-#N|A^RyKWPfFZ9H5Ml z1C7iEcZ-A!uq{;f^n}ZCA+tmOK-7$oLp4=G<|s3dO2|S*30b6wkj2UfS)z=PBa{(xq%uO5DkJ15WrQ59jF4r@2wAR-kYkh) zvO*al$0{Rar7}W}Q%1<~$_QDdjF8pJ2suF+Atx#$WQ{UHPEtn5$;y$CneklPWK_?$ z2b}C#k&s<|dvZ#`<+zYDLjSPbjF2-mRYJ~El#sI(CFC4M2{~6$Le5i^knc9u#mWe|L>VEMDkJ1FWrSR=jF2mo5ptz6LatIq$koaSxkecw*D53AI%R~c zRYu75$_TkZ86h_+BjhG!gxsu*kXw`ya;q{zZc|3c?aGmm)8a+8{;MzXZOG}7kk9<^ z9SN7?LhcUzgOoEu?$J~UxmQs_?o*VI`xPbR0YwRUP*Fl2Qk0N~6(!^mMG1LS5h0H$ zBjj;qggl{)kSCQ9@{}?{o>oT4Gs*~gRv97BDI?^0WrVz-jF9!p2zgN%AulN-rsHqb2zM_PDpeP|9DoV&liW2g%qJ(^+C?TIJO2}u567snsLcUN&$d}3p*`$n+ zuapt;wK77!QAWsSWrTdIjF9h?5%Rq@_mnYGeVN@`ZmP=80~cY6aTYgp??H>O@B5M z#xz@>_@6`8C;lhM`o#ZgWPRd)b+SJ3KS|an{?{Pu6aQrn8C|8*(&#Q%B}eByt73O@0_0R^A+pr|_qih59>s3!%AdQqUL zHwB9NP@t$U1&aDnpr}6uiUv@iXdnfO22r4BFa?T+P@rfi1&W4IM2dEbWnO!hJi<3c zt)-~IAFXzaCES-Q+C3KfS3qPG?ZJF08by|(J;_qE7g>r%lci`3S&GJzrD$)m6zxNn zqH$yt?Ms28{U}hhKLv^opg_@q6ev1~0!5`1C>l?JqB05;O`t&0L<$s5qCinO1&St9 zplAvOil$PaXc`5I4yHiSArvT@PJyBs6eyZW5h)rGiw`y+$=fVukCdW9CpF7nUgduw zGevV_p?`%)M$tUxOVNC?6dgvEqQl8jw16x{3&~Qnh%7~m$x^h0EJa6(*QuMO#UB4SkxGz`qK`ivIz{)84koi*d5m|~pCQH#LWGVWT zEJdG@rRa0A6n#OKqA$r(w26$OuP9LTH3f>kp+M1Q3KV@yfuipyQ1m?oihiI#(H066 z{YZhLtrRHQMuDQAC{Xk>1&V&5K+$#z6#YtpqTeV`^g9KL?Dg#D*_zLep(sXyqAZF? z(Z*Q(AOn(o+FmD<{k{~v;@hHlR>FO`qC{5cU!j&!RE_ykRGlnENwO5xAWKnAvJ~Z# zr6`XqMJcirrO8s1PexHK3KZ3*Kv5kE6xF3bQ9TM2)u%vF0}2!sP@t$G1&SI`pr|ng zikeWMs3`@Cno*#rkOD=`DNxjc0!2Gepr|DUids>iXh#YZ?L-kNvM*S<+<+u!*89ed5~|5MoH0Fe?*&;m2h9K=&-ENzXCL) z=y2vs(E_p*EhJ0PBC-@MCQH#0vJ@RbmZBrcQnZvTMMsfQbTkEumQkQ+IR%Q2p+M0J z3KShnfufZZC_0V;MaNU1XcYyDR#Twp1PT2xGz_9URHQkYbiRP`BHQNS&A+s zOVLGSDY}>}MVFAJ=u)y2T}GCo%gIu71sO$GQlRK63KU&Ufud_DP;@N?imszT(OL== zT~C3c8z@k8BL#|XqCnBj6ezld0!6n{py)OV6x~jNqB|&1bSDLh)={A7E(#RgO@X3& zC?ZAYWX10_Ajy+s2IpKU8t&Vod$SVm%N0GC75Y~YXSPKTF<*)vCQH#HWGQ--EJcrz zrRZ_86g@$fq9@5x^b}c&o+hK{8446VOM#;2C{Xk~1&UsvK+$>%6un4+qL(O8^fCpC zUZFtIs}v}DjRHllQ=n)A1&ZFFK+&5ND0+(mMQ>A}=p70ay-R_j_b5=bks?xbe^xwe zS5x%4Khu9eihBFr_4`=~_vMN{&I zP@rf#1&V&9K+$g$DEgfOMfM8h=xIBOViYLKqCioc0!7&rC<-YeMIUCxhZ>ONc;6O% zBt@G&Mo|ssOHoa-6y=hoD32^fDY6u$$x@V0mZDl@DXLADqB>+0 z)uljDJqi@nr$A8y3KSJkpr|1QiW*U%s4)eKnoyvqDFup}QJ|=h0!7U!P}G6~MLSTS zs3ir8T2Y{AM+y|}M1i8#6e!x60!6z}M2f1#<7*5^@)q9}sveJ?=|AAxqFv(&_vMO; z;^B=YQdG=*DJmgLQG2o!bs$SoN3s-kB1=(cvJ`b8OHo&{6m=t`s5=FUdQhOKCk2Xn zQJ|T0)khBgj&8Bw31< zlBMVS#T0w!LV<}Lyk^)7?QK0B}3KXrPK+$Rn6rDhUq7x}l zw1xsjCsCm2WC|3WLV==FDNuA81&U6mK+zc#C_0k@MQ2f<=xhoUokI~RIy@d9Z$Od* zd|R|YiaPou+PU$B`*KAW#>1n#O3_8km!gZwQgjJfiY_Hf(Pd;Qx|}RUSCFOXO0pDP zMV6wg$tb#p0!7zSpy)aZ6s@H|(e)H4x`6^kH&USJCJGeYOo5_XC{T1O1&VH?K+)|K zD7u3JMR!u5XdMNL?xH}^-4rOghXO_SQlRKQ3KZQ>5h*%99>3CnBwM?p3#6#n!vpbz z`*KB(#KR}-4Wya9>qnU{MURoC=y9?XJwcYDC&^Ou6j_R%CQH#XWGQ-|o zie8{V(RvCLy-0zgmncy5G6jlWp+M2A6exO)0!6P=plAaHir%0=(VG+~dW!-@Z&RS? z9SRh^OM#;IC{VPK0!8mrpy&e%6n#h$DS9X#-(*0N^ZmDu4@*%C-xhroPq;5v^jSR2 z?IlH@Ghd3nAWPAgWGUK2mZGo7QuH-hioPLB(Ppv~eM^?2@5m_no&rTbP@rfF1&V&8 zK+#qT6m6qG(N7d8`k4YnzfhoPI|YhLP@t$9MWpDHc)YyVW3KTV>Kv81~6g8nhQBw*O zHKRaLAq9$>Q=q5?1&Vf{Kv7Ey6t$v2(T)@-+KB>1ttn8nGX;uvp+M2D6ewy#fugn) zk)j&e@dXAX*~7O*HM65<`Vacvb-V0@`*KC?v%_=xNl^#pOHoI%6m=p?QD?Fgbs5SF}%d_}&018pnJo+LtUv`;nz+f3g%EK$fBd$x?I>S&B-@QZ$|{ zMP+0ZO`t&0L<$s5qCinO1&St9plAvOil$PaXc`5I4yHiSArvT@PJyBs6eyZWfudOy zD4I=yqC+WAG=~C3b16_Xj{-&WDNuA61&R)*h!l;@j%N=vMSJ^SK=ziRJA7NTAUol{ zT+x#3u+?BGI)eF9bR=1dmXf9DD6$kCO_ri%WGPxsmZD?GQnZ3BMaPm+w2}fv$5Ei@ zcnTD)qCnAV3KX3{fua*BP_%{uMJG|9=wu2MokD@4Qz=k%8U>0@r$Ese6ev2A0!3$0 zpy+H06rDqXqH`%wbRGqY&ZmeJEy|AXWg!^(umt=>B43(lw znJ-0`k)`NzvJ_oGmZB@kQgjtrimoP0(KTc#x|S?O*O5`QmI6iBQ=sSu3KZQ)fufrz zP;@f|if*Am(XA9Hx{U%ww^N|#4hj_ANr9qu6ezlj0!4RIpy(b76x~aKqWdUNbUy`( z9-u(cgA^!wh$2#SQFi=f1Cng&+oFr5=um$|dpJAczFg7c+2PH*NzoI`m!c=hQuGvA zik>D*(KBQzdX_9j&yl6*d9oC}K$fEQWE8zffuffvQ1mhdie8~W(W?|FdW`}_uT!9C z0|koSpg_@^6exO&0!43Apy(Y66unDS$Bv11PvB#w7bbqG*X?DVWxuP$#!>uEvXcP0L=qs`meNC34Z^%-#nJh)$ zlBMW7vJ`z!mZBfXQnZDPq8}+xw3Pxy+bB@<69tNXra;jz6e!wGfudh2Q1lxGihid+ zQ4s2BJBnfyD9WNhQJexr*%T-WDNvL{fuaNjimFkds5%9Tk`ySaK@lnXJUiZaq$xVV zAJM*$qObfBt!9{TU#=(}hQ0QXqI~8{Q7y6*+1DXQFGP@{I%FxTOO~Q~WGSjomZAn^ zDJmdKQA09{8d0FAF$Id6P@t$O1&W$cpvb-_GP+hMvTxgt3KZEFmq!JPcA!8}O9~XV zqCnA(6e!w>0!6JUP_#1ziguwu(XJFIYD0mdwiGC8M}Z>ye$42~p~${=J1QbYd0~8l z0ZIPi&-7Da^i03MZJ7A`BKz{EJa<(Qq+wsMcv6#)PpQVJ;_qk zi!4RG$x_sZjH132DC$RnqW%;p8bE=fffOhjM1i8g6et=(fuf-lC>lnAqTMJ^G@JrO zBPdWbk^)7$Q=n)M3KWf^K+&EQDB6nxMWZQDG=>62V<{p<9m4q41|-?sH$NSv=t2*B zhY9!PiuMb`r$$TB{>+!61ISWzAX$nIB1=&zS&GJ!rKpT7MH9$UG?6StlgKD4r$EtU z3KUJDK+#kR6iuT*(ZLibI)nm6(8;UnyGa+oHu`!hN}-rD2%bTZ)ci zz7!ozmZD{3DOygJqGQNXw1O-}$C9OJC0UA&BTLcoWE8EUK+$Rn6rDhUq7x}lw1xsj zCsCm2WC|3WLV==FDNuA81&U6mK+zc#C_0k@MQ2f<=xhoUokM}5b16`C9tDcdr$EsK z6ezlo0!0^5M2e0G;~fo1a-2UcJ5q|)`?l!fFyX#j(dA({cAOMl!F(yYk}O46k)`Nr zvJ_oImZEFPQgj_ziq?{)=z6jg-9SdsjT9)li2_A8Q=sS;3KZQ+fuh?eP;@&5iteC5 z(VY}1T1SDRyC_g}HwB9Bp+M2S6ezln0!8;zpy&Y#6g^0RqK7C@^e_dA9-%oq9^RQ?8m}{`*KB3h2eSoNzv2Hm!fCLQuHiYik>4&(eq>}dVwrO z>&a5|B3X)FB1_TBWE8zZfudI_Q1luFie9Hc(FO_>y+MJZHz`o`76pplra;j<6exO^ z0!8mpplBlnir%L{(FYVL`j7%eA5oy_V+s^~LV==BDNyto1&ThWh!i~$#ve2wN&6C# zAp1!v>gtbZUxW$w<%+%z!}kx6qHmZlMVrY|^etJ6z9UP~_hc#hfh$Y-QK0B|3KRu7|L`0wMuDO%3KYdDP?Sx9qL2bb zITR>LP@t$91&XRupeRX!q8bz^s!4&OTnZHBQACP1h4GvNO_BfIHTx?m`oN#|r*abR z%N5nm33n=$qB_i%qPk=$sz;Wh`eZ3;K$fBcvJ^EWOHm`T6g4JGQ4=zXno^*s83l?8 zDNxj$0!1w-P_zRDids^js1*gsmR{GyS-~-MV8=!hN}-t~ue1GAZiD zd@1TqmZBbHDe6gP?oSK4dBCOO~R3WGU)TM$rHY6b+<6(I5&G4W>ZR5DF9x zr9jaz3KZ=|fui9QC>lY5qLCCR+MNPLdr+Wg6a|X*q(ISL6et=^fub=KC>l$FqP;0l zv=0S}#!*CyI_JbsH6Y0izF*Wuin2WHo0D)~uIRv=@Yab^bP)5UsFW;471SrRZwrOVKrCDY}*{Mc0v~Xf0Wat|v>;4P+_0kt{_wk)`NnGKy}Y zK+&xfD7uXTMYmI+=ne`L-ARF>brdMNivmS=Q=sS`3KZQ-fuj2;P;@^9iXNaq(SsBy zdWZr=4^yD%5egJNN`a!sC{Xk`1&W@ah!kCs6Q5*2lE3-p=SnGB;Ni)fg!^(u&*p?H z4wjedbG11F{qqkfo?0S&ABwrKmAk zikgt6s3}>Bnvtcbkc^_{6ewyzfubEKP}GtFMXe}Mv?B$IcA`L0YYG(YOo5_ZC{VO3 z1&Z2Gpr|bcirP`2sE7hZ#S|zip+Hf43KVsqKv72u6m_CNQD=%sQJqA*vjIuA@n`yV z6VWsMZ+*kmC6RDnuBb;M+~-g!>dAa5>P42K-ef82LzbexWGU)LmZJV-DH=eQqJd;7 z8bn6XUlGC2L*~oQJ`o~3KZ={fuhkA zC>le7qOlYx+M5DJ`%s{090iK@r9jbs6e!xCB2v^X5np0JlK$M zS2R8mUNBdR%9t-j6Ub6Dkt{`%$Wl~JmZHgIDVjo-qN!vlnnsqQgUKj5gaSp=DNr)qJJD)xqoD2j@DKJVH0mE?K8=dAPlkyx}Jcd8we=6k$|F`2q@Y_K+(+v6m2G;XbS;Fw-5qF^P+z0 zbf;*Oo8kFVbgO+tyEPg$U#95xXr##uDY}F6rD!`_itc1f(GIp0-NlxoyV+8-lPyK} zu%+l;wiMmRM$!EQ6g@yd(SrmOJw!m!!vqvPLO{`@1QhKepy)9IiXJDR=m`Rfb`wza zBmqTF5m59r0Y%RcQ1mPTMb8mX^gIDYFAz}lA^}A&5duZqqW+lWILAyD*6)L-L(#BMi5uS(HIyDd5xjhZi0^lLP7|12pw z%=uFE8(WHgXG_r$wiNxrmZCq|QuG&FijK0S=x??Z{liAlzXTL{se0Isq7VT^DFhVx z1Qdk{D2fnJRE2<|C;>&O1QewaP!uDeD4l?!3<8QW2`I`UpeRm2QG$S?YyygM2q>yb zKv6Y9py*K4|G)u>U2K0b?H4I3GE&u3qvp#L)lQB4b-5HB!}(HFhb={Q*-~^YTZ)cj zOVROcDXPboq7&FsbRt`d>a$VQfPkWt2q=^&XuChoG(RP*izJ$Ek)hfQq-L-MLpP3)RQemz1ULJ zn=M6s*eE)kfTA-9DC$cRvn0Y&o&fuh1xf4c(`J7k}A93@3{jnw?qsQEHQi&7)6ERdqboG(R7*iy8V zEk(=NQgjttik7pbXa!q}R)fq{*EkzHorRYI6iXI}M=wSki9wDIUQ38r~5m59P0Y#4!Q1k==MY{bG}5VrRM;-Y!Mw z*+;ZjQ={g~6up@mIcJF!?d5zadW$VZZ?mQ79kvv`%a)?|*i!U9TZ%qlOVNjHDcZ+I z(MJRneM~^nCj=DjC!pw40*XE(py+b~ioPJA=t}~Mz9OLLYXXYCA)x460*byPpy+!7 ziVhG^^aBA!KN3*%69GjB2`KuRfTBZ$K+)@|{^bsc`*`NyydgzL?GxF*q(;q`Df&G% za^o^7I>Px<^aopt{$xwhUu-El%9f(P*;4cmTZ;Z=OOcnR$L&%SVxuU9fFhrOqA&qP z5dw;;5Kt5)peU7qqBH`EVgwYW6Ht^vKv5MO6tXszyLj zbpncN5KvT;5GXpF>ObRv#2&GmpWmctkd0btQS)Vr>ZV1$TrNe&a=sKD$Cjew*-})G zEk!4=rRYSq6xC--Q3JLVoy3-+hHMlyBA}=-0Yyy+C_0&dqNW5CH6x&?IRQm22q?-W zpeT=kqI?31S`tvyih!cl1QfL)pr|bYMePVEYEM8>2Lg&Z5>Rvs0Y#@00!7E9`LPvF z(fle7PMx&ik^VzAI;BO;mnrI+7HPUlin?*W6m@4yQ4h8h^<+y?FSZo*W=l~YwiKPt zmZCG*Qq-4?qJ9Jv^(Ua{Oah7q5KuIbfTBSJ6b&YzXb1sCLkTDvMnKV71QeZ3K+$jl ziq0XR=v)Gd&Lf~`1OY|o6Hs&k0YwD_6pbXHsE`mS>YU~ebU!^{BL{ z`7%Xg(;^qGmZEW-FGb_oQZ#`rMHAUlbRk=cCb6YxGFytKu%)P&Ek#q=D7uJ%q7nj% zN(m?`BcNy+0Y%dZD7u({q8S7f%_N}c5(0`YC7@^)0Y#S)P;@x~MY9PgnnOU*Tmp)& zAfRX-0Y&o(C|W>3(LzF?XiS>F&H;%XZ#O?hQuL4gApR@UqUOsKElrC&xK@gmalRB? z#g?MwY$;m7mZFtxDO$yrqN~|bw3;nNYuHk>mW`ry1Qe|&plAaDMb{8ebS(iz*AY;( zk$|G>2`IXOfT9}-D7uM&qD=%8-Aq8yW&(<~5Kwdr0Y$eGP_&hRqHP2e-9|vs?F1Cv zK?oErPV@IUAhDiqhL=cDZ+qCkJuPa!OwrwGk-yhV(N4~nqI=jE*=otcv zo+Y5@IRc8FC!pvB0*YQFpy(w6ie4t5Xb%BJuMkl5Dgi~W5m59xAyBj<%|CI2Q?$lD z(Rh~>)s49EMq1Q-nWDGTBHgc*qIWo7ir!^Q(R*wudY>&tAF!q9L$(y{V@uITY$^Jf zEk&QOQM8|cqE87Z`iy|0&j~2{f`Fng2`KuCfTFJnDEfwgqHhT(`i_92?+GY6KtRzC z1Qh*9K+#VG6dfd>=w||o4iQlF3jsyH5>RxQ5GdN4=8tzkV%zM&{aaG>tbJ+rx3sAF zGDUx;MHX+AqQ5v_ijK0S=x??Z{lk``f7w#x#q`Ksib8BDN?}Wp&z7Pv8$}TUimDJ$ z6eXZ2m4Ko&0*Yb;6r~eTltDmICILlR1Qf*yC`u4elubZU4gp0~2`H*YKv8u9ifRy0 zRFiV8NfTGp}6ty9ss4W3S?FcApPe4%z0*X2kP;?3bMW+%_)QNzi(+DW)Ob8Sm z8}om4Kw=-*&ChYM;F10#HoC;3=F1fIh()SzlA@lRFGaoBQq-F*MSa*(bUIs#&R|PX zU$zwWV@pwgwiKPoM$rHQiUtx;G>Cwr!2}cyA)sg|0Y$?IC_0OPqO%Do8csmbIRq4) zOF+?i1Qd-Rpy+%8iY_3asDOZ?kpvVK5>PaXfTGa^6pbMSin_)8jt)r7eo|4myA<7K zqbL?NU#4h6EOOpvDVoUnQgk6(iYBq8Xfj)hrm&@`m@P$9*-~^7TZ&59QdG)DQ5gY6 z(+DVJQnZ5e zrD!EvidM0u=xVkUt!7Kn8nzUzWlPaIwiK;rOVI{4imoA`=vo4bt|OpmBLPL%6Hs&m z0Yx_wP;?UkMVkmHx|x8Y%>)!}A)x3M0*Y=WplB-rMcW7{x{ZLM+X*PTgMgy#1Qgv# zK+z6DplDglf6f7kwX{z(UL{5K?2-Omv8eenMfb)cUvHJ7`#4{U?q^HU18gaJkS#?I zv8Cu?wiG?WmZC@5QnZULMUSyj^f&=UPY_VFn}DJx2`GAsfTE`fD0+r~qGt&xdX9ji z=Lsl!fqRw3AyD*J%-`UE#P-^4(NQT{=bjfnES*!Kv6ycMJ)*^YDGX% zYXXYe5Kz>XfTDH;6tyRyr~?5-9SJBpg@B?{2`K7BK+$Og6m=$`s0#r_T?r`aMhFzu zOZPu^Kw{PHvyLaE2aohu+ig+z^r-nVMZMD_|K2S{eK=o=PG?Ke8Eh%)%a)>kY$@u` zmZCG+QZ#@qMFZJVG>DC&!2}cyA)sg|0Y$?IC_0OPqO%Do8csmbIRq4)OF+?i1Qd-R zpy+%8iY_3asDOZ?kpvVK5>PaXfTGa^6pbOEsEB}~u>=&2BLs?iruz+cIz@lkXB~S< z(Ng!k@c8to`7%Y5(jz_Zm7>XQdG>AqN!{tx`-`BC2T1wWlK>RTZ*Q!rD!@E zMHdrLG=qSmnFJJFLO{`_1Qg98py)CJiY_OhXf^>wa|kG!OF+>T1Qg99plCh;MGFWh zT1Y_Al>`(mBA{q70Yys)C|XKD(K14yXkxlQ(E*7Ki8(kIO3|}+!*o@8)O?wuRq2tX z_e;^$oG(SI*;2HIEk$eDQnZdOMeEs8w1F)}*RZANTDBBj$41dc0*bCDpy&nyif$yJ z=q3V+HW5&CGXX`L2`Jh^K+!D(6x~Wd(N+SAwh>Tt8v#YP6Hs&q0Y%#hD7uq?q8$Vj z-98%0kNQ1lc5MNbn@^b7$-&k|7d905ho6HxR5 z0YxtoQ1lW3MK2Rjw1Rw30Y%3VP;@*2MfC`QqJPr;D;$tm7yBEt|4LCy_q^~48Bz0PicZRiY<^sd z8gjlAHDXIqW407EVN21;Y$e@-BQ$-^QEXCTZ;O#rRYqy z6b)cY(LlBo4Pr~tV73$uVN20aHj0K3P;?dnMQ0OGG@O8ldRQ4s+}V+kl4M?led0*WROP&APcDC(2pXFcf@ zMeMVVr%RFjz?txc8Bz0Pii$HLxlc>cRL+;8i`Y_B!j_^^wiK1IrDz&kil(!r=wh}M z&0tH>Og4%xA)x3|0*Yo4P;?mqMVAv$G@F2;IRq5VC7|dE0*dAlP&A)_q6GvLEhM1m zN&<=&5m2<4fTAS?6fGs7Xc+-TR}oOOoPeSggh0{c41cHt61&mvP*0JfoiW{6R+4e3_z;Ga{jvr05gQm!kb_Df*NxMW3;y=ySFd zeZiKZFWFM`6^=r00_juKGxHvvWe5CTQ}GW>=PNG#Pp z>-dorwX{e2|7JwZmnrfyBfa-XQ8@EIAL&QfQdEU4MNzgCrLv_cjV(nnwiKnar6_|f zMVV|AWf4#mC!i=nKv6aUML7f%RVARP8UaPs2`H*TKv7KsifR#1RGWaJV+bg!LqJho z0*a0$py)UPijF6ss2%}DClF9{A^}D934x+era#F6iET4DDVf1zw5slT;Rcye^JR(} zXGX4iRf?K$zHW<7W=m01wiGpEOHp&S6t!SWQ7&7G^4L<8&z7Q=Y!tO3pr|zgMQsQu zYD+*-I|7Q@6HwHFfTE5B6rDmq(WwL!bt0hXGy;k`6HwHJfTFGh6m=t@s5=2gJqRf3 zNkCCA0*ZPQP}GMIC~BDL-{XM9ni!l$QZ&{+yq%sIHD9Kve`aLw>r!+k=S$H5wiFFy zOVJ><6b)ue(Ga#24P{HwFt!w(#g?M8*(e%LK+!n_6rD>z(RlU+t(F7EYA)u&;fTFPk6pbUGXgmQ$69_1pNI=nr1QbmoplC87P}Dcm zKjMJIX4`F1KPj?L6NRT_M$MNgD#?u0-YZ3=oG(RXY$=+?mZIrwDY}>~MKjn^G?Ohw zm$0SiQnnP$Vx#CX0*WptplCJ$MRN!!noB^@6$BK`BcNzL0YwW4C|XEB(Uk-gEh3<3 zF#$zO2q;=gK+!S+imoD{XgL8zD+nlBNkGvm0*bCC1d66+`lmS{u|Mr=`WH#j8oMo8 zof$P>rf7X;q~L8S+Q9izbPZdIu4PNnb!;ix$d;n(*-~@^TZ(REOVLeiDcZzF(ai)D zZ6=^-3jsy95Kwe00YzI0DB4Cq(QO12-A+K!9Rw6@C!pv~0*ZDJP;?goMRyZWw3C3M zdk84Hmw=-C2q?OrfT9NoD0+|(C|aB8&v!s#FWF}u*GbVc_DKJs%&7S?MY}R1x4bJw zk8!>fJT|4fTFhuD0-WKqIU==dY6Er_XsF@pMatd z2q^lHfTDebK+z+a{!0!>tdae_>qn*NEBkWDN10LcWr{w{jC}vT6n)0|QuH}nioRe= z(U)u~`id<@U$dp?8@3dE%a)?=*i!U88$|~QDEfhbq8|w;`iX#|g9H@)OhC~g0*Zbi zpy*cuiVhP{^cw+1zY|b&gn*(y2q^lKfTF($C^||&(cc6V{X;;}zXTL{S$bfOq7Wfa z^hu_l_`oT8z;287OHp6@h?bHSHD9KvN>(I)pA(%Dj!!Iq*- zwiIQtr6|spq68a7*#s2j5KvT=fTC&y6jdjns0IN=H3=xHMLK+%Z=6xAo7r~v^*ClOH8kPs*eXZdG2AhAE}YxQL_pDL1Qc~9pr{K0MO_If>PA3OcLIuf5Kz>U zfTCUm6!j*cs1E@}rxQ?g1_4EV34x*}S^h=`B=(ej*70O1%C*~~epylTWr_x7MIPHP zMT0nBiUzZ#Xb4-1hO(t-7+Z?YVoTB4Y$+PfmZEdmQgkjGMduMvG=hMl^9d-rfPkU` z0*XcwP*g}j(I^6nMiWpphJd0X0*b~GP&AH!qVWV2O(39XA^}Ag5>PaWfTGC+6ip$Z zsF;AFsf0k$nOXj44oIxFJw_WKMd#bS>x;6Y=F1dK%Zm7)OVM=Bm!gZ=QZ$1tMKjq_ zbO~FEE@ey6EVdL~#+IVX*-|u{jiNaO6wM`|=n4Xg<`GadpMatT1QabKpy)~hiWU)2 zw3vXRB?J^LC7@^-0Yz64P_&$Yq7?)btt6mm6#+$86Hv68fTA@76s;u$ib}Km#tukq zncWtZNzsRP?|NNU)O?wuYqKJ!e{dEk!r7rRXNM6m4Ql(amfr z+RT=sEo>CsLO{{21Qcy0plBNbMYj=9bUOh>cMwptoq(b{2`Jh@K+#f+NQuMIh7Co93 zHD9LaiLA(qucc@==S$I(Y$ie4q4=rsb0UMHaF4FZbZB%o+70Yz^SQ1mtdMeh($^ezEK?-5Y+J^@7^ z5K#0X0Y&==DEf$iqK^qE`h*ZDdMwMo&jE=Q+r8_@rKpXK{aI1-Ws1JYioE@;6n)A0 zQuGyDioRw`(Kl=<`j#z4-?63Wd$trEU`x>tY$^JYjiR3jC^|?$(a!`F9U`FU7XpfY zC7|dq0Y$$NQ1m+iMMnrI`h$R?KM5%Mi-4k|1Qh*EK+!)06#Yv;kr&s)b`*sOC`uuq z$S0sEOb8TxmgWEHfW#68=W{7~%0?s}HD9JEEgq?JK#F3VFGcBWDav3=Q6^i8ve;4- zXG>9nEk)UEDav6>QB^jIsu56Boq(bm1QgXIpr{rBMYRbiI);FvIs_EeC7|e70*a0! zpy+r4is}(ibOHfIClXLppMatU1QeY_Kv6>iiW(76)R=&xCWJsyH12nCKw=B*u25<` zc%*+-iW?`#qvp#LwTMRwf0UwJ&X=M*wiM;FrKlxaidwOys5M)P+OValEnAA(v8AXz z8$}%mDC$T+(J2HJok~DaCjyF2BcP}=0YzO1DC$Z;Q8xmLx)V^;gMgx*1Qhimpr|(i zMSTb;I-P)`GYBZ^OF&US0*d+*P;@3CP}D5$FLXd+57=Y0=2G-^@&Q{sYQ9X-ka%S4 zK`9!_`BF5DEk$RsrRZ$76b)xf(K&1>I+ra)=dq<|1Y3&EXQSu>0*VRlvXQ6T|E zqX;M(O+e8Y0*Zl#Z(KrH%#uHF9fqRvz z0YxPQ6qOPJMT6r09tR{g-adCdSc*=t+oG~~)O?wu8S%&uhoopG=S$HgY$>{wEk(1~ zQgj(xiY{kM(QLL9&0$N?T(%Tl!A8+M0*dAnP_%%6qJ;z$T}eREA_9sQ6Hv5-fTE=Y z6fGm5=qdt=mJ?94f`Fox1Qe|zpy+A>idGX)w1$A9wFDHcBcNzK0Yw`KfuiYgKj#;x zXuo};@nR|ZJL1MQ@u>MSMc2n8tqx1k4V*7UH?pPZCbkr9VoTA@Y$@8zmZB|eDY}I% zMYpo0Xe%2<+XyJSjew%t2`IXQfTHaL6x~Tc(GCKN?joS*ZUTyS5>Rvx0Y&!`P;?&w zMfVd>^Z)@x4-!!H5CKIG6HxRB0Y#4zP_&DHqQ?kP_&?rypV=rnL_pCm1Qh*BK+$0Wihd)Y z=yw8&ju24v2LVNY5>WIP0Yyg%DEga#qJIb|`j>zrFQJF+C<+l!ltMs}Pe4(afT9Qi zMO6qWiV^}vU&j3}9FW*`_Cf3`DH>t7MX8CX`7%WriAdzA6lHS06lJlcD9)Cm1Y3%- z*;16lmZGX`DXPYnqUvlZs=-E4O#+H)5l~c{fTCjvD5^t1QC$LxjwPVzI0A}}C!nYv z0YxVeP;?>zMfC|NYCu5INdy!%B%r7f0Y!}oC~87L(a8i9H6@^^86i;QK2dbC0}^{S z&A~}e1dsHeun%v|6H)VJit-bYzW+#3OU{>~R%|J1&6c7zY$d2O&Q`jgvm4Kp71QeY{Kv8D`inYfTDf`6!j;d=u85N1`tp*kbt5=gg{Yl!k_AZ#QNE7QJxeXvN1RjHD9La ztVCp$XRjd73!lyTQZ$?`Mdz@k=v=lGoyV4<5o{?spDjffu%)PgEkz^QC@LhNXcPfO zqX{S)LqJgx0Yzg8C>lpV(Rc!iCJ<0Gk$|EL2`HLGK+$9Zilz`yR7^n8R04`FBA}>* zfTB_YipmHmnnpm;bV8tLXu^NM0f}92UpgBmMVa0ukbJdv88A}TZ$I2QM8bNqALj~T0}t6Vgibm5Ky#~fTCpt z6kSC?(Q*QcRuE9Ml7OOB1QcCOK+$Rfiq;TNw3dLPbp#ZxC!lBp0Y%pkP;@N;Mb{Am zMKcrrQ3oW}-#&MJi4=Wpw?!KhQS)VrZc0Rsbw3Uwd0VuJ^QGu!wiIn zqFdQgw3RJI+t^Zc8(WHQXQSv20*ba1P;@5&MLP&6x{H9Ky9p@TNkGv(1Qgv%K+$~! z6x~li(E|h&JxD;&Lj)8(OhC~i1Qb0=K+!G&iXJ1N=y3vyo*P_&LO{_U1Qh*AK+#_W6dfg?=x+jw{vn{~UjmA}Y&~p8QHX$|6atET0*b-}6h#Oq zszN|flz^gC0*cZID2fpRMc*X+R~?X8v76ym!fR8 z6y>m`s482EsJw1ZfPkWt2qP$dU7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl}0*X#2 zpy&(&iuw{z)Q^Co{sa`ANkGv60*VF_P&9~uqQL|d4I!XtC?QbPGTT4b0f~j}F$0*b~HP&9#nqKO0)T}VLDBm#;i6HqjTfTCgoil!1!bP)kXB?J_e z5>Qk|K+!Y;il!4#bTI)%GYBY}NeC33o$cS`fW$KFwrIE%y>Fj_yd*nnzD&{O*^wu6 zq-ZwhOVJ#*6wPHz(G_edn#Y!+`D`g#z?PzgY$>{uEk%piC|XQF(GmiRmJ(33jDVu6 z2q;=kK+y^UidGU(w2FYDs|hGtO+e8a0*clWP_&MKqV)t6Z6KiN8Ul*0C7|d!0*W>g zP;@;3MK=%vMYFQ~uN;urY`ginOp5l|xG_6wzD&{P>`1h_6m8*rDY}I%MYpo0Xe(Qa zwy~w?HntSq&X%G(*iy8eEk$>-QM7}AqPqwvx|@Kaodgu!LqO5J1QgvzK+*jK6g@yd z(SrmOJw!m!!vqvPLO{`@1QhKepy)9IiXJDR=m`Rfb`wzaBmqTF5m59rAyBj_+i&K8 z#G2UO-oIIjUbWkzXR@Q_%M`tk9qC_FieBV=DSC-5MK80ZXb)S8USUhot86KHjV(p5 zv!&<_wiLa|M$ujZiryli=xqXu-XWmqT>^^UBcSMg0*XE$py)#aiuMsu^br9?9}`gY z2?0g>2`KuMfTGU`DEgd$qAv(2`jUX6uLvmmnt-Bj2!W#Kvi%YVB=)8~(tlox{&dd^ zf14dOU#94X?8xfcQuHI|OVLkkDLTlOqMzAPbciiQzp$m~SGE)#W=qj;Y$^JkjiMt2 z6#YR!(Vqkq{Y600Q38toCZOma0*d}6pvcS7!*&#f2q;P+pvWhnC`>?6gn*(d1QbOH zC`u)uD2;%k7y(7;1QcZuP?Sjs6n&rVKjeVK;&xkfK#C^VN3^V*sQEHQIXRK{>qt>m z&X=NUY$>YFmZBPLDXPhqqFQVzs?C<7W7twuhb={Q*(f@efTH6FC_0{iqIv`roj^d* zi3AkYC!nYS0YxVfP}GosqDBN1H71~_2?0eX6HwHYfTCsu6g4NHs09Hcp0!)7VnfnJqJqal4ML`*6BB1DM0*Y1>P_%}CqO}ARts|glJpn}<2q?OSfTC*&D7ub-qKyO; zT~9#K4FnY3NI=m|1Qcx|1d3+o_^&%4v9H_=&yk{^Y}}j^HD6wqmlCd@R;OXei*I#b zvi0IG8o2oP?kl#b@l5wLE%=Wyx@e`_fUcLCZ8lKl6 zerGMuYaIXO7|&}K?{KW=<;7Fjxv z;@5Qbys7a|x_e$({G?uMe%uqJa1Y2#UY-z zG9Ew6^VY%@kRxnw5mE1q5KdAs9hU*vhu#IG;)ycgo1PxHJz@h0w{#CSbke2M416~BL$ z=e-yI>vGTA7w zyQ?9T*mR4#9zqHG*X$dF686uLHx4E2-;-_@O4vULoEJ*izv$XJl(2u2vwbLG|EA)p zp@jXTcwIsX`&Z3+gcA18QuPTX?B5mY7fO7)+g&H2g#F7NLqiGsrx}Ka685w8M}!jg z!_h~E686)r$Al90u z_W1KaC}9sE4u%qT5AfGe!ajr_2_@_{_-M$>KIHz;gtr8LL zehtsh>X?2?dWZDWtGeH$o|Ec%kv5){Dpf=2>A?$x+>B;=ekw1Yo}QVWk>1|@PEu?B z$4jNTm#XwyW15lRjil>Ux@oU6L$5OV+=^G3saL6&%5o<~DlSJn(_K1y%ZcO@5zouk z??i7Tr$wl9Z7xKk+S#F;DqU)=?^fGgL#-=axVr9Dcy-->b`$A-|H=Q`|Lm%*{HyY| zpF!YzgWM@8p}(>+y^#CmUe>Oi7A-1@2;w?p{23a`6<`44=C#izF%ftwNDV)&JA4 zNT`ZGE)>b}>(py`Y}-b4>-)v^y3~zCs^ms;s<;!Y^wp95e>-;4%m4TBe|KKBW|iL1 z|Lz6s0{mwW<)*~lACtj7dl&S|>*LumzkObxf>FVfZCjT=*`|B>lWp7UC0n-x| z*1_|7cGt_~yBD6&uef+>zSqC&@Ph7V4s98{?jD@dru^--Bekk{yDiJ#Zud&BQWvl# zC$uepsSe4@G;K=hgmF`f#?*7yYVyr>*X7FZ#cOd-@Z0QJ{`<&x7bf}g9o&l*6u7fn zwJZo;L%w@soY0Hc)>W^qTg7W|?*aE>W2Q}>JTrJrdfC>z;jRkp$}fO>hnBzQ@;B0& zx6z~Go#EaEdO>%QgLk8QEx{9&EQMeZ$#;JmyuLlpDd^f`aPmBdMDH&5he1#E_>VKaNySsf)l2^G ze}K)exFFqR61omV@(p0MTw`G0emgyrXHT?0cgYvc)2ncQ40K7lm0u?N1D|}Mt`!%q z2dY}>dF9M_9XLjT$;PF(JLx{nS3WV zXn8!d!g78uuB!^dTz&3$6`aQtc0DDp@`~%)-S+9C-o-TPM;x8f#{>#R-1 zw#_loD5)yXn%iT9v;G-8+I8uejp5 zPPt0Uug3Q7{a0MBx8geC!;9T0>D9S&c*Txn@Gf+3Hu;2mPw>3*i{##xYo>Ony91z? z=R|jXB#T|i$&XsW2dkdtXS-`aud(71a2>n%ke*k5UAn6vcncLa+>MBPspKn9KFeLV zI?H`9(NpEW5$7&A-`yU2?v7+h@LtIe4*E!1p&`G5L%F~T1@42id;O*3i%ZJNKQ20K zT#DdIFTcLaKZ3hICdn7E>m(`2y*GjC0 zICfHTVOeu`m%Wp_TEos?GJ3Ebb7ohpr$wj55h2x5vPb!)+u55g#JePudFwN~+cgt>K z%O(_0Xi4hLnGh z&F7wH#l6UiJC7Cj9o@Z9_ym6n?9G%r=6+|zUBXKD2)Wx?arciu5O$9+c*h80aMv&S zJFxqkx(k~89R`2u%754VDJ!=OWxL;bVfhUocP}gM0#@7u1a_Y%F{-Me?J*Vz8NbS;@&ujk}ZMPtUed)GsGc$@qq#KYDm z|K~qY?vYf6`|n@(E99lj%5tA$um}14vIp~Bv#QOHEC?_3uS{8PkKVg>aQ`c`$HrbL z*F70&-@Jc|{#{Q$)2osl?VskyQgg!9Le)bx{aT^gp<_aILUlvOrJNXQVJH9BugWRx z{rqp`XZ!Zxu+lGIpL!tq_Smq}FW)^b%&xTUlN9drv)-)oR`E#-OTOnm8B*z&@3~JQ zRr=+7?vp!}e)*pJ+)<@p?o-m0mc2grX`)KMd@oUH+4JN7wR1f8Ii}?A(%#QG_PF-H zA0Ia;^BRot2LJb+I{TzrihXL@j_%Xa_WQPDbsgPjZ@d)u8JiRA=w7I?x?NxPa_+Os z$)o$6a`M{wsN4(_ts?y2K>?rGcObiB#ED{bGY<5%t-VEY#xo4G6Ab_X3x z+^6Vm&(`swTETu+$A69qc6y!Q*u#AS-(G%@j!TXY_Ie#(ckftx{zp32Xb|lBI*w=< z>*0DwNV4tF6nY*Iw<>%`7NPe)N*U@Vo>`WbdxhvFOeu$3C z+6Vg@9pCI2>`!#8<*s;p`IB_KpmVS<)NxDKVDHrNyY9jMUB|p$!S1Bv^gh9!r{k_O zg8ib7DgA>T*RjulU=P!A`JiB5r{h~gg8iwE$D9@HMmmlh9_-0F-g<7Z@73|Zh+zMr zW6OeIch+%6VXznI__%{^?~j*t437veo*Qm{YQv2Jm&o9H;| zqF@*6xUDqU_v`rMv|#_GW9u2g?yBP@mjwGt9e2AMHM_j8=vZZTu&e6WZ*H*9(edhe z!M;()_Z9^EOC66}6zrxtj#(1yi*&qwS+F0}@!;}c|E*)&Rl)AA`gj;;J)f(zu&KQthXuH&2=2RIoPE-Zoehi59@enYq0;- zvHk7A?y2MD+k?GS$7gl~`wbmqJA++Q$AR|-`+ObO-5>1DI_`Tg*x%}S;v>P%)p7i; zU{BL=$K%0%RL5U;2Rrm+aP0VWaO|z)oM(f5m5$FnAMCw4X1o;a+By#26YK&VH@q6` zTXg*R^$uQ;-Ol!E9rw5| z;Msm(#~k;SJln_XINW_n&vucHH@L6u*}g-^FWeXTZ2zp|$?mItw%h4AwO+6<)A0fK z^*?+5(>m65Uro2&M8`ZkMm+Bn?LImV({YrJ#X8Q?aj}l;blj}t-8w#|<4ZbLvHKsX z?u%V^bZ^go+0otYNFGPp{Smj_-2yKq%Y6x1-D^=gb8=bXD0eI?36A4=%01F7^IF(L zJFms4(o(O5g%N0Iy7d8M<)mK08QFVuB#{}zR1WhE0vO)GP+_W$!QcUQ;h zbYHmC8SbvcfBbUqs^qT|-2d(6{9xK$kN@~(&$C~R+<)#}|9^eCX6|MF`|Y|91LeQ$ zy0Txr-G97p+wP{zd(U0Z{NkzZF1WjmUKc%MV8@VG%Y~|L8v%QLcDaVQ|2W4z>1}Bg z^6FO#JX!Q#FZX=okXO%6&@W!D(Cx}^cYOCy(w)6sdwaay8SZJ$aZh?*yVqwv`Ni|f zT&Vo|W>k88G50)P-xBvU=h*A`-MzjJTsf7Vx6nOZ`SmSwug@-*UA_$WAFpqnd)i)K zp8L;!(>!aVdpXXrW^dPi-R}OYeEC*Z z`u*Dbhs*brn*D&*Bw{7{E)3pi{jk;c6n{v=e4xYTe-*GdHI$8-?pu5 z?OSzd)v})b8X242vtO^^YvRExwoAh6wKAzkaz%nabB(`}-c+T~fEvfP*Jy z)Mz;8glZ?{G^pM8lOr?s*Y5N5kpufbIWl#>9o>KR+<&{>f1aM6nmxchrT-_APwP1& z?WMfKUY_FRz|Ec1a#1-dpa^W^mnxLti;) z89%vOme!T85%(KP2~|1E9@B+V3!Ukdl*orsJ48ph=+|(+*_8gZ`rFHeBZu8{{9=2l z0kuaaQ}jc3-KC^PHoHI8DXGyq?%D~5BlfAAlyLM7_agog_X2*is$K2r4em|*dDVux zrz0!u{7{v(?p0O^hZ{!hFM37or%5%^cL*HsX1*70ta+T9Exm9P&12nc<$i*>W?eU1 zd*P;R<72EFeb=8j8 zc9*Z4cG$MNeBHI(=WM#QbeFG(c8c4r+~w=39kT5%UoUOPAT=Cr;J@gu|Fk*g=cMG{ zaZh{8Sq=A&ZgnqULi$GRF99Zn^wX&l(qB_T&eW8U0h$srP*Xw%X-ddoO$iyIDIr5O zC1jW;LeA1g$l2Nm8Lo|xbF>k1t~Nr>(?-Y$ZG@b!jgSkp5mKOykdfL5Dbz;DC~bs{ z)<(z}ZG;qQBV?>LLdIz$WV|*)CTJsMqBcS<)DDE4?tkyD|Fm|d;*3B@cXtaFo)k4X zCS+>F{(@*y$VEC;LP|6xq*PNv$}}Zpnx=$I*OZWpH6>(*ri9GYl#oj_5pt@N=|g{;%5 z60%-XLN;hh$TgZ0a;>I>T&F1^8#N{5dQAzrK~q9*)I`Wl+6dXCjgXtQ5wckuAzQQ& za*H-XZq-J}R&9iA(?-Z`+6cK_8zFaSBV@ZaLhjT?$PR6U+@+0>yR{LrQyU@oXd~oa zZG_yXjgb4b10k#ZTzCDaW!Y`Wnn1`U_Vfc$lVd_2iP&E(PYQWdr%K2!O$m8SQ$ils zl#nMhC1kgzggmJ!Ax~*a$kUn<@{A@zp4CRkbJ_@bUK=4VXd~oBZG^m}jgXhM5wb@c zA+Km7JyhBiXp)JDi&ZG^m~jgYss5%P{ULf+Lz$a~rdd0!hLA7}?c z9`Xmd>p$&F$07W1Af%<;C;2dHa!kl45&Nctq>%kORYE@1l#tIfCFFBW3Hd@(LcY|L zkgqf)XM#xXv2sx;Yke{^?a!4B?zi1=m zS8aqG)<(#0+6ehw8zD!u5%PyNLjKf7$Y0tBIjW72zqJwak2XU7)eeMwpP%g zY<&k*I$PfXmBH3`KxMM^9Z*?pz5^;w;5(oa1ik|*o4|KK{?$bu5AJfI5!AcR(Fa;5(q| z5%>XfTDH; z6tyRyr~?5-9SJBpg@B?{2`K7BK+$Og6m=$`s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P z^(LUG4*^A|69PqzLcaSO3SR6oyD4fcMZ1jD8KJ28GDT;GBK9qDNks!VUy25@rDzaa ziUzZ#Xb4-1hO(t-7+Z?YVoTB4Y$+PfM$tJ06rD>z(RlU+t(F7EYA)u&;fTFPk6pbUGXgmQ$69_1pNI=nr1QbmoplC7yMNJ&&_auDXM3rirrrYalTAZX((dfQkhg##`#h-jV(pf*-~^dTZ(3|rD!HwiY{SG z(WPuDn#Go)%h)KooPeU)1Qg97plB`uMOP3|G>?Fy`2-X#AfRX=0Yz65P_&4EqQwLh zEg_(2DFH>x2q?OWfTHCD6s;hjXe9wfs|YB%nt-C!gh0_nA%B?z63cXtw8JG*)I9k( zD-<_YMcWA|x|4vS9Rw8JML^Nr1QhKgpy(a~ zitZ(#=sp69?kAw=0RoC1B%tUaLZE0}$bZuTiS02s>!s*t_oapK!=b48GDVMtBK9ra zNkxxyz7##dmZIHkDSDDEMNhG%=xMeTJ;RowXW3Hp99xQ>XQSu^0*YQFpy(w6ie4t5 zXb%BJuMkl5Dgi~W5m59x0Yz^RQ1m7NMSBS-dW(Rfw+SeEhk&AY2`GAxfTH&aDEfea zq7Mlu+DAaqM}$DpqanYR`$~H3pgnNkB}Gr!z3Y!dQS)VrJ_|+cM*<`jea`t(^aWdr zzGO?$S8OTznk_}&u%+l*wiJEGmZI<3Qgncgq8|t-`jLR5p9m;ANI=og1QZ=2py(F@ zihd=a=r93AzY$RMI{`&U2q^l4fTBMMDEfdic&dWiqhCp6k|(KI$Me| z*iw|qmZB`S6vf$6lweCyHXB7b1Qb;zpr{%FMb!x?szE?eO#+H)5l~c{fTCjvD5^t1 zQC$LxjwPVzI0A}}C!nYv0YxVeP;?>zMfC|NYCu5INd#_-8WK>{h!7}>r1)DLkk|$8 ztMB0|DZwNChwQefaZ1#DnWAPX5&MxONkz>$Uy53=r6`vzMR{x~%4bVaOSTlXVoOnL zwiLBtOHo@kirNuS)SiH%4g?f+B%tUN0*X#0pr{i8MW+!^)R};yE(8>HC7`Gq0Y%*j zDC$8#QBMMjdJ$06n}DJ|1QeZ4K+zcl6!j&bs2?FvbaIOSodXifbbkjZ+*FEud!*k# zC2GD*(V&!w{YaanqQRUmMMKz9G?Xnx!`M=E7F&wWW=qjl>d(F6jDCK6C|Apu2` z2q>CNK+zNeii!y+no2;?MT9`nfD}K^0g3gu+oFL|l>E1pN>ZZc%M?vdiP(=sN-DaT z^QCA8TZ(3~rRWm26kW=eqFHPyx{NJFm$Rj4Hd~73uu(LZfTAl1D4It=(R>1m77$Rh zkbt5q2`E}bK+$3Xik1*iw3L9NWdsymML^MV0*Y1;P_&YOqE!SGT}?pIY66PZ5Ky$1 zfTDGTKv7wWKivU|oot^XnkGfJ*=^DKl&JYKMc1W7*1NyJmsGTo^QGu|wiMmKmZBTk zQgjnriZ-#O=w`MQZDvc+7Pb`K!bZ`p1Qcy0plBNbMYj=9bUOh>cMwptoq(b{2`Jh@ zK+#2E6$gquh~-c4O@!7WlPa_Y$^JlEky^|QuG5`ihg8E(NAm? z9VDRWX99{25m59C0Y$$OP;{7pqTdK8`kjEHBLo!vK|s-;1Qh*6K+#bGivA{`=pO=# z{w1Ku{SD;n+|}s5qV8@6?5~}M2q;P+pvWhnC`>?6gb*nDJjL(hfW$`HZP6D}bkIf> zKWe^AQOu9nkAzI#7Nv8(6lJibD3dKkS!^kav!y7(mZEI76y>m`s482EsiiW(76)R=&xCIl3nOb8UE`u=hUBsR=G>zL*TkM!+l8-|Rvs0Y#@0P}GTlqSFW{ z>P$dU7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl}0*X#2py&(&iuw{z)Q^Co{sa`A zNkGv6LZGO*@4w}M#H!dQ8e2%wS9V)8(2trgQ#90%*pH-5DjLT5Qgjwuiq2+B(QvjD zox_%*bJqpI( zDZ0Ur*pI|cD!P&LrRXNM6m4Ql(amfr+RT=sEo>>eg)K$5vZZJ%TZ*=^QFI#tMYj`B zbO!-N+X*PTlYpWf1QgvxK+)X<6zwFS=pF)!?j@k;J_3sFC!pv70*W3apy(k2iXJAQ z=n(>n9wne?7Xd|&5m59vAyBl@_iuGTVvm@j>!s)^8&CLA^JR*j_9ONq)su>z;e082 zmMulkv8CvFwiLat zY$^JYEk!@ErRX4AihgEG(IGa9ej%XfR|1L-6HxRU0Y$$PP;`WVqCW^I`jdd7zX&Kg zNyTKv9%{qEtel=qulE>43zV z*{7?&mZD4T-gR0yYQ9WSW;kO1q(f3s7UxS*oGnEOwiIQvr6`9jMOE2SRE;e~)!9;1 zgDpih*(j<-Kv8W1ijEzrKlC>OHpgK6t!VXQCqeYwPQ?XMSTe<>PJ9Pe*%im zB%o*j0Yw7|C>lgS(O^QLC@<_k?tsMRxf#xvqJ4H-G$b4~U#95naK!#endEKJaL$*a zbJ$XJE?bJuV@uHpwiKPumZA&TQdGc}qLFMVDrBQ*6aht}2`CyvKv59^MPmsl8b?6U zcmj$h5KuIcfT9ZtD4Ik-(PRROrVvn6OhD080*Wpops0j^qEZ5i$_OZ$MnKVY0*Wps z1d4`*{csPb=o|a2<5^PFC;5Oa95r92XjV94|0GdT(Pf-3MVGUsXf|7l=CGw`E?bJO zU`x?FwiL~0OVI+h6fI<<=t=^L776kSU|(RBnAZ6pMWE(!Z*I3Teb?X!-T zO3|D4*F>%lN6nWh+7yo1KWUXzbTj8m(Pp+3ZDC8%Eo>>el`TbE*;2HPEk(DnrRa9H z6y3o_(RKog?j)dS$NwVk&f{#Z|NsBLjx(=0GiR1_X6#v_6tax56WN!tWGzLF!Pvqu zGlY~1CE3~}sYu!rp;VMskxFS#rG%79i&9G8=VM;?+swS*pYQkb{r&O1Tz+%8)NAgy znb*uQ=jzNkGX?^Ro+O}XJpn}<2q=1rfTE2A6m24)XfpvtPZLn|3;{)32q=1%fTHIJ zD0-fNqOAlJZ6l!Q1p^%M^W|;M+f`SFGqL=S$HK zY$^JYEk!@ErRW%2ihgEG(JyQ%`jst3zpLqO3f0*d}6pvd#}upLDq0*cBJP!uMhD1m??pMau70*WF86eST*luSTTlz^fX zLZIkKLb!S#r|2sCiyXd_qJ8!mE!B^hFH;ovefuXFixp*Xz7%D$rKmhxiYlqo^YRMV$yJ>P$dU7Xpg95>V8QfTHdM6!jpWs3!qM=MzwL0Rct52q@}JKv5q8 ziuw{zbRhvn{Rk-PPe9QC0*VF_P&9~uqQQhfQ8PdMumci}+s#jNDOzOXB0pljOwpyj zZ~r80v7(`zFGa)HQgj(xiY{kMQ4U**hO?z8mn}sj*itl-Ek&c)D9R(CXfy#uV+bf3 zOF+>$0*b~HP;>2%Xd?kdn+Pb{OhD1o1Qb0(K+zTgik>B) z=s5z4o+qGaD*;8@2q=1ifT9-(DB4ay(Mtpry-YySD+Cn1N(dC)?}ukPAkh(aS7?nC z?Qkzkc+HQPFH^MB_wAoFFIKdR^QGubwiNAVOVL|wDSDeNMenesXb)S8-epVCdu%D% z%SO@r1QdNhK+%T;6n#WM(Z>W7eL_IdrvwyzMnKU%0*XE-py&$%ioPVEXg>i(UlCCB zH33Bj2q^l7fTDv06dfX<=r93A-x5%Cgb*m&;fJ?7AW`=ZCU^;NNYO4M^_?FvU#93s z-~Vcu6#c~cQgns4D?Q-3Tb^PC!u)0*ZPPP;@>4MHdiI)QfR=nd2A^f&6c7uY!r

Qk`K+#kJilz}zbR_{r z(+Mb=K|s+=0*bC8plB8WMOPC7MMD$AA3Gq?+wH54!=z}6eMY+`F=D<<(e;V`pLtR= zhx4UqE?bJ`v8Ct+wiMmSmZJG=DY}U*MGM$cbTeCu7P3*ah=8KS1QabHplB%pMYj-8 zbSnWxw-HcuI{`&^5Ky#?fTBAIC|XWH(Om=-tstQ2ZUTx{5>Rvx0Y&!`P;?&wMXLxX zT1`OF{e(c#wTa=Hqn)Cc?Y8JTKBE;sU`vdcFH`hTqTgYx6g|xOQuGL0iXLT4(PL~W zdYmmqPq3wE9b1Z?WJ}R{wiIn(qv$CDiZ&8Zw26SC%>)!ZO+e8z1Qcx{py*iwik>5& z=y?K)wh~aZjew#T2q=1yfTHaL6um@1(aQuBy+T0Is{|CiMnKW)1QhKc1d7%shDSLd z(I4#Q=RqkNW8;m)i1{)_yA%C+dY>&t zAF!q9LpF*&BB1DF0*XE%py*QqiasNtXdeMZpA%5@1p!505>T|CfTFJmDEgX!q5}jJ zeM3OeK>~^n5m0oPfTC{+C^|ww(RTzCeNRBqQ9__-S7P{42PC@1KBK)UMeXfj{||`~ z^JR*DPW0cLAVt4$z7+k+mZIO-QgoaxMZdG9=nu9OonTARpKK}mi!DVb*(my(fTDj0 zC^|(z(Z2)~c@aHqM^T7?qH+Wjg$XE1AfU)6peT`mq6h&+Ndy!n6HpW-peTiaqErHk z(g-L@C!i=sKvA54q6|Wy=%>W+F$X02g5CTalcHPg-gRaqV!ljKrHG%AFGZC(Uy7=* zrKl=ficVuoQ8l&{RcA|44Ym~3WJ}TMY$>Y6Mp117iq0UQ=u85N>JU(L76CP|pW4+4sM5>RwL0Yw)OP}GZnqTU1)^&z0BF9Agt5>V8S zfTI2c6b&GtXdnSag9s=ZOhC~^1QcCNK+zBaiY_6b=u!fTh7tlrZ6e`W4oKAf5w2F{nF8`)AcpDjfd5Kwe00Y$eF zP;@&1MRyQTw2XkFI|(RSPC(IJ1Qe|xpy+M_idGU(bPoYV_YzQa9|1+H2q;=jK+*jK z6s;kk=m7$X))E3mb0XoSX-?5t6mVlz?2q=1GsI{`&65m59p0Y$G6Q1mJRMXwQ1^g01WI|wLxgMgx)1QhKe1d1Mx zg!?)m(bw%~V;_;Ci|wxVn~{k5GDYu1{QQ|xw1@Mh=v}rHy~mcKy=*CZpDjfnu%+lj zwiJEDmZFc@QuGNMMV}H-^cev~`v@rdoPeS)2q^lJfTH~b6n#ZN(bohN9U!3S8v=?B z5>RxAfTF_$6n#rT(GdcQz9XRMdjg7%5>WI50YyI&Q1lZaQ1n(Le7ge@?PGU^-j<@3 zc3X5T5;0$<=(mW!d6pC%=X@#poh?Owu%+k(TZ;Z6rIkNqFQVzs?C<7GuTpeCL2X{2q-#>fTFVrD5^_9Q9S~R z>Jw0O4gp0C2q z0Yz;HfuhPu;aanuqL%iDWUC|vkMy_Lz3a9~5%Xn=&P(z;T_;5yIA4l7vZbgKTZ%ff zrKk&Ain_9;s2f{~y0fLI2V07IvQczC0Yw)OP}GZnqTU1)^&z0BF9Agt5>V8SfTI2c z6b&GtXdnSag9s=ZOhC~^1QcCNK+zBaiY_6b=u!fTh7wRTjDVuc2q?Oo5GZPw6dvt> zM87aN?WJh4-4^8}Ma-8e8kywZI7f;`alRDgv88AQk`K+#kJilz}zbR_{r(+Mb=K|s+=0*bC8 zplB8WMOPD0bPWMTvk54=mVlz`2q?OqfTB5sKv8Z|_;Cj$`jvgvafB4DGg5PtBIe5! z%}?^*nkPj!alRBSU`x@>Y$;mEmZC*$DO${yq9tr8TFRE9Ti8-`D;q_(5m0nH0Y!HZ zP_&GIqB{vFT24UGT?7=ZAfV`O0*Y1=P;?IgMfVa=bRPjls|YAsO+eB81Qe|ypy&Yt ziq;ZP^dJF64-ruGFdKf>Me8_Uik@Uk z(R#KNZD32$Q*0^P$d;l_Y$@8zmZGQGQuGWPMOz3cdX|8q=Ljfzo`9mQ1Qcx}py&kx zie4n3XgdK#FA-4mG66-e5K#0g0Y$G7Q1m(hMLP&6dV_$Xodgu^BB1C^0*ZDMQ1lid zQ1n<*xU~Zk?dxX3<5G0W9`?VT6fs|>=)ENWk_A$T|CfTFJmDEgX!q5}jJeM3OeK>~^n5m0oP zfTC{+C^|ww(RTzCeNRBqQ38s7AfV_+0*Zbjpy(I@ML!cz^a~+Sv?nQijRWFtd>ov2 zrD(BzA^X>)i1{)_eQl+fTH>Y6rDpr zQ3C>s8WK>{h=8KT1QcZvP}GEgqHF?+ni5ddjDVu%1QfL(pr|DQMXd-ZYE3{<8v=^j z5>Rw50Y&Wyfuhrr!_g&9Q6;-WT`f6yq<=y21GeOd`7%YFlKlp^NKt3bm!d9gDeB6W zqHb&{>duy;9&9P<$(Ew?*-~@?TZ($IQPi7&qCNx^^(CO_LIR5V5m3~hfT95e6b&Sx zXb=HKg9#|Qh=8Jt2`CyuK+z=x6kSR{(NF@4h7nM7839F?6Ht^xK+$jligF2oq7KR7 zehx^qo81<5l%ikUC%A+W$r1Bqibf~LqO4N0*bCBpy)aRimoT1Xbu5Ia|tM#M?ldHgh0`#X;`*KiFTy ze`9jQe3_z~ll^DzkfMd0FGY*kQnZ*YMN8OHw3IDHx3Hz?R<;z~#+IVn*-~@|8%4_q zD7uq?qU8h>-94--)I2mwWp5>WIQAy9Nva(JHu67A+@!U8GkVGsKsPmY)`Q?x$W|L0CA z+Q9iz^b}i)HnOE?6I+Tlv!&>1wiG?XmZB|eDSDPIMbEKO^gIDYTL~!IMnKUE1QfkU zK+$#rie4h1=w$+mULm09RRW4$BcSMY0*ZDJQ1k`?MLP*7+C@Oon**;4cwTZ;CvrRa0E6n(*#qA%Gf+D|~yR|FJ&O+e8B0*byNpy(h0MTZC|I!r*( zw*(X&A)x3x0*byTpy((8ML!Tw^dkX9KM_!LjDVt_2`Ku7fTCXsDEf_nqT_@>(ca|n zSO+B9*5JG^MVstfv%e=t%$F(pE7`wkr4*gyd@1^yEk*yZrRWq}ivDFwk-K9b{3CEu z6kpeRZ}Q3?S?sRR_I5m1y)Kv9fQm0fT9Wn6jdaks1gB1l?f=SLO@Yf0*X!}1d2{1hu1kE(cN~x=uas+%|^9o z#C(~e)1&@7_exPM&X=OvY$-Z}Ek$RtrKk>Diq2w7(b;S%s>_z5dTc4G&qmQX1QazO zpr|1MMU4n3YD_>;76C;~2q?-Xpr|PUMa>8(YED2=3j&H-5>V8NfTGp}6ty9ss4W3S z=MqrVj)0=}1QeY|Kv4%mpr}SP{F?(3-Dx*JHKV~J{YPwcj7H3tDe4;aE3THJZk#Vg z-PuyqgDpip*-~^qTZ%4VOHnVj6!m6HQ6IJx^<|^zLIR5V5m3~hfT95e6b&SxXb=HK zg9#|Qh=8Jt2`CyuK+z=x6kSR{(NF@4h7nM7839F?6Ht^xK+$jligF1k8bLtONCJvR z5duY>qv5s=NYwtOqJ%CevXK{!m@iW_F6s|mBSqsmUy80^OVI?j6isAH(ImDM<+G(| zGFytKu%)PgEk%WF6crIrG?jp&X#^BqNkGwb0*Yo3P&AW(qN@lfnngg-)dUn>LqO4N z0*bCBpy)aRimoT1Xbu5Ia|tM#M?ldH1Qgv!K+${xif$qVipE64*E%54Rd(|;R*Kfx zoumcPi1{)_i=+PPwNkW%^QCAhTZ(RBOVO=tDY}g2B3U5Y|%DJsX7qA**E64+AY zv!y7JEkzMFijoK@N+zHvNd!{e00N2z5>PaVfTF(ZvK5 z4I!ZD5(0`YC7@_10Y$?ID7uV*qRR;=$|0a=H~~eu1Qd-RplBokMWYBP$|Im?Gyz3p z2!Wz*Dd9RBoT5eche5ha(ar8<31d?t=F1dKNb$REl%k28FGZ8sQk2h@qRDJ2n!=W% z0=5(tvZbhqEk#q=QZ$W?qALj~nodB`3<8Q~5>Rv%0Y$S2D7u<}qH72!noU5_wFDGh zM?lf_1Qg97plB`uMe_(Kx`BYA8wn_yPe9R41QabGpy*}-iWU+AMdMS#;~kJ_XZyn- zS4h#tb|-03O2mAbqFYk@n>S0*t(-4Kx3Q(@cD5AV!Iq+BY$>{vEk(=OQgjzvidL|t z=x#QORuWKj4*^B@5>Rv>0Y$3_C|XTG(ftGzts$W30RoEF5>WIY0YwiHQ1mbXMUN0r z^e6#Ej}cJxH~~dZ5Ky#^fTAY}C|XZI(FQ`GXh}+Vy#o@x%x;U8N>MBOjP_JY#C(~e zr&IiQpOK5K#0k0Y&c- zP_&nTqW1|X`hb9<4+(*yO)25u9gt|m;B1znImHjyQX=Nd6n&QBSAI^4_Hn)xea@Dm zFW6G_C0mO2v!&=OwiJEMmZAe}Df)&jMF-g^Iz&LxVFHT2C7|dC0Y%>tQ1m?kMMnuJ z`hkF=9|iGZSG1Qh*DK+!J*6#Ys-(QgD49VejZcLIw3AfV_30Y!fjQ1ll8MJEY? zqEAx7?HrKkPW!6kr&83=Nd27>F<++0OZ6|?Dn+4GJ(8EAa%?FIv!y73Ek!4Kd}F=6g71( zOQ@Y1F<++WtWL1xI zMZGv*ih8r9s1I9;`m&|yLbeq3V@pwgwiFFuOVL2K6b)jdXfOdq7ZFf&F#$zG2q?OQ zfTBwYC>lyY(J%svE+e4masrBS2q+p(Kv6CMMI#6(8c9IWC<2P|2q+p&K+zZiipCO9 zG>(9x@q|E8&(v`GOHPq*Uv)fRitI0(Nw^|4V!ljKeyX4KiWE)ed?}j3mZAc-6cw_i zsE92^Q`u59jV(o2vZZJ`TZ(3|Q8bf)qN@lfnngg-)dUn>LqO4N0*bCBpy)aRimoT1 zXbu5Ia|tM#M?ldH1Qgv!K+${xif$sHXaNC5Hxp2_kbt5^1QabMplAspP&6?$Jjelw zX4@U=NmA6s#?sV?`7%Yfr}|T0lcGB~Uy7EorRYw!6fI{<(OqmQTEUj0yV+8-k}XB| zu%+l;Hj3^eplB5VMXL!Yx}SieH3SqrKtR!20*W3apy(k2iXJAQ=n(>n9wngYF#?Jn zC!pvF0*clVQ1m1LMe7MD+CV_jQv?)kB%o*$Ay9N{YIubM5M$xMT6um}3 z(dz^h?I57&4FZaG5>T{@fTA}EDB4Xx(OU!*y-h&TI|LN%A)x480*c-vplB}vMeh?( z^Z@}y9}-aX5dlRX6HxRCAyD*8YIwf`60Ko3KU<`zrh8e!r>PP1Ws1H?^+UU)=u6I* zqWx?s`id<@U$dp?09%T_VN20LwiF#=OVMGr6n)D^(GdcQz9XRMdjg7%5>WI50YyI& zQ1lZ4MaKvz`k8>DUkE7rm4Kq(2q-#EK+*366#YR!(Fp>I{v@F2F9M2A5>WIv0Y(21 zP;`nADB71AKHC9_uJ9e4&!wogJ<|U-HDbO@Q8>--v0I7~(*E<2zR#ATM79(~*iw|l zmZD^~6h+xml){#xRJIhQu~C#xKv9fQm0fT9Wn6jdaks1gB1l?f=S zLO@Yf0*X!}pr{%FMb!x?szE?eO#+HeC!nYn0Y$Y5C_00HqB9ABqEK3Rf&&u0)8Ld# z3m&7DcP~q*lNK>wrl?+;zvyi#s?YhlEjouSMGe?e)Q~Mjjo4Dum@P$FY$OnwJPeP#R?6mMx4oI}V!Ko`nC+r*i=ch%?mnrI# z=I`AjMSVG6iY{bJQ9rg6^=C`b0JanjWJ}Q?wiFF!OVLGaDY}@Aq9FtnT|z+7r34fW zC7@^+0Y#S)P;@x~ML7f%4JV)|mw=)X1Qd-VplB2UMR^1ijV7RI3;{)B2`CyzK+$*t zimo7_XaWI66A6K$UTNVI4oGy8-4^whBKtB?!lbl_`7%WXX@1qcQdG$KQdGp2qN!{t zn#Pu*E7?*soh?N(*itl;Ek#$crDzr#MOPD0bPWMTvk54=mVlz`2q?OqfTB4B6wM`| zXdVGYHxN*CBLPM82`IXWfT9Hi6x~cf(Lw@>775r@yQ_U$TEu*rqC3<4oDZaEIp<5!U2G{@!Iq-C*;2HUEk*aRrRZL^ z6y3*`qE&1uTFpk${R9-PA)x310*clWQ1l=HMGp~B^e_QMj}TDwC;>%}5m59v0Yy&` zP_&MKq9+L`T2DaH1_FwnBA{p^0Y#e#DB4Uw(bEJJJwpf--H{fa>wrXe*;gHxNzq1o zq`xICV!lk#)--?ZM^dzn^QGtowiLa{mZI%!DSC-5MK80Z=oPjUy~>uN*Vt0@IvYhh z2q=1kfTEoQ6zw9Q=uHBOb`wza76CElkC-o0l$h>k?~|ek=Sxu%TZ)p| zQWRxNQ3_j%QrS|J#+IUVwiLzKQWR&SD1(5aOah9^6HruvfTD^76jdUis4@XXRR}1m zN!zjBA}=?0YzsJP;@2%MRf=$I*Wj!vk8Hsg!J%5 z4oGyR!SU0BNBZubwtK*q9x-30s6o1aqNZ#q zYQ~nL=4>fy!A4O_0*YD@P}G`$qBaB+wI!hFTmp*P5m3~gfTHsVDC$5!QAYxbIuTIR znSi1$1Qc~8pr{)GMcoM~>OnwJPXdb0C!pv80*ZPO0!8)H!z&$-=pg$J$T?E5m0nJ0Y!5ND4I(^(L4f* zZXlrOMgofF6Hs&$0YwW4D7u+|qJ;z$Eh3<3F#$zO2q;=gK+!D(6x~Wd(QO12-A+K! z9fUwpVS2cp0}`!iw?#!#^qJkeUX~s)U#4h9x_|ybDY~2UrD!Evitb@c(Y4--)I2mwWp5>WIQ0Y#4!Q1k==Me7JC zdXj*m^#l}cAfV_e0*W>gP_&7FqRj*pJxxH-GXxZEA)x440*am^1d5iYhbK88(ZTjr z$GfEHVY@AQK0RW-Owo(!{*uE|w4L*%=q0ukz08)PSJ+bYDqD(PV@uKNY$@8omZCS< zQnZteqFn?Oy-7gPZUTzlBB1DP0*c-tplA;PMeh<&^d134dkH9dpMatd2q^lHfTE8G zDEgRyqE84Y`jmj8&j={mM?lf%1QdNiK+%_kK+(4J@FoW&nrU~1UXY@X?T^pyPmh={ zQ}j)`|G^O{I>`A_bciiQhuKo}EnA9?u%+lbwiJEOmZGC2J9xEk$v*6lJibD3dKk<=H5zKtNGN0*WdTP*j#Y7tOWn}DJ-2q-#}fTB7C6rDvt(b)tP)g_>)9sx!534x+W zEZorniO#dTLP@dUk^Ukhbxtf|zD!Z$n4kNj6lHO~6g6Q>Q8rtOnzE&+8C!~)v!$p7 zTZ&q;rKlBKidwT#)P{hfwgeQNOF&UO0*cxbP;?#vMI8tz>PSFQCjyE(6HwHJfTFGh z6m=t@s5=2gJqRf3NkGy01QcCBKv6FOih2`J)Q5ngzJx$g!&vwR2PC@I9-}pqq7RE7 zu*D+g%M=Za`41hFqCuQ5MT6N=bP-#ME@n&75VjOu!j_^-*-|u=Ek(oFQgj&`MVAv$ zltVz#Z~}^Q2`CytK+#A7ibfGolt)0(Xab7H5KuIhfTD2(6pbgK=n4XgCJ<0Gk$|E} z1Qg{HP&Ao{yEk)O{rRaJ#isledG?##)c?1;QKtR!r1Qg9D zpy(z7iWU%1bTa`(3kfJ%L_pDE0*aOpP_&eQqFV?kx|M*U+XyJSoq(b{2q;=cK+&B9 z6fGwNil)WFnZG(k1@?WkE2U_O@5WuRi1{)__r&~W$EE0A&X=P5*iy8LEk&!@QglCC ziq^2D=mEAAtz}EmgKQ~!h>fC$2`GAmfTBkUD0+;5qQ?m+dV+wWbp#YWNkGwh0*W>e zQ1lc5MH>ky+C)InW&(fJOF+?k1QhKhpy+)9iasEq=tBaEJ|dv#V*-jkA)x3} z0*XE(plBZfMV}K;^aTM$UlLHXpMavT2q^lR5GdLn3*YO2MBCZJvX`Xjq}>)Bh(*ko zDLNeUU;I;wzU6!=I>MHs@7PlGJzI*7vZd$;wiNxymZG27QgnybK+$Og6jdXjs5${fH3%rG zNkGx*1QgXGpr|$hMQ0FDbS42sbqFXri-4lD2`H*dKv6vcis}7v zYR#6SHf$+s%a)>Z*(hp9Kv8=Fiq0dTr~?5-9SJDvL_kqz0*bm2P}G%xqHY8fbtj;x z2LVMr2`D0Y#GtD9R_G zXfgpsQwS(3AfTv_fTAJ-il!1!G>s4_8Wayd?SMoV+PBUIOHrCV(!VkuF<++Ws<{7A zIVqaO`BHQ>TZ*n>OVMn$6kW@fqU+dFbUj;&=CGw`E?bJ`u~Bpb0Yx_wP&A)_qMHaP zT0lV2%>)!JB%o*!0Y!@mC|W{5(NY46ZXuxPRsxD{BcSMZ0*dY+plBHZMRyWVw48vV zy9g*+K|s;ngh0`Zc=&GzB-+Qmc0E&yX4q}f%6Pc>;>I5>T{_fT9-&D0-2AqV0r0 z(Y^6-X9px&#cqD?lcEmx$3$L=N6eQgdM)mcj7ZVzoG(Q?*i!TcTZ(qFrDzvhir!>P z(QdXBy~UQIx7kwk4jV;#2q=1&fTH&ZDB4Rv(fb4xeLz6bhXfRTL_pEU1QdNjK+&fJ z6n#cO(LMr-J}02)3j&J1B%o+N0YzUCQ1mqcMF$8d`i6j_gM>iQEAjAr2P9hAZi`-( zqBVB!`cOP#zD&_~asQEIDf*uCrRXSIihf{A(T{8?`iU(?$JkQzGh2#&VN21kY$^JU zjiTcO6#Y&>(H{g9ogkp-PXdbmBB1Cb0Y!fkQ1lN0MW+ZT`j>zrFGCO8Q4}Jes2l-B zVFHR02q^LiC`u%tC_+F{5&=cY1QbOHfue8Y;kO--Xug{XN2I8gJCD5^$4QFQ`}Y7kIV zlYpYr2`H*XKv8W1iq0UQ=u85N>JU(L76CVQO-*x|@Kal>`*sLqO5Jgh0`(jPM}`B${D2KUYi9Bpdf-M9h~dT9e^NDoW7w2^?K zO#~EeCZOnP0*am?plAyLMb8pY^c(?2&l6Czm4Kpc1QfkMK+%f?6m2J<=p_P*UM8UE z6+)nBbw;?M0}`!be|rCZDcWYYMXzQ=%$F&8Bg5}gS&DXYz7*|ZOVOKbDca4JqPN&m z^fp_H-eF789<~&{%a)?|*eKddK+*dI6n#KI(T4;SeMCUf#{?98LO{`{1QdNnK+!$| ziasZx=nDdhz9gV%KLJHw5m59s0YwK0DEfwgqJsn!9U`FUFabs15&}i9XM_tJkm!5% zNPmYE{pDVka3mvQzD&^%8UAfmrRYb_m!hB8QgnS%hk&9}1Qh*CK#`ZJhwUf|5l~c)fTAz~MF|8H z`2-Xt5>ON&peTueqGSS!q68GB5Kxp#Kv5bYQ1pF9c#8uPJ!RhkIVwdb?VD=pnGy44 ziZV0(PpU~#dCr%j3T!E=$d;l?Y$>YDmZBl#Z(KrH%#uHF<1p!492q>CJK+z-uit-64noK~^ z6atD02q-Efps0v|qNxNFO(US_N&RLyE5Fd?}j4mZG_ADVoQYq8r#!bR%1e=Ch^fCbkqUU`x@> zY!oddplA^RMT-e2T0%h4QUZ!@A)x410*Y=Upy+l2itZqwXc+-TcM?#voPeUc2q;=X zK+)X<6s;tn=pF)!?j@k;J_3qX5m2<65Gb0R8Q$Z7L=U-{aIF;mWaIwKi23r;y>ba> zCRaN<ap4t zJg-)4OeN2&6MLeH=hch-dYb1ojJ2uZc}-%oPxrj$vDa#QUh7y&9nWhQ>wmWAb&TCv z&-1#*K0n9vddALdu^nwaZ&WO; zz2}XM4ea1~6JmFD^1R8hFS~eNQS7Ylo;N*qMNiM0729xu=Up57qqpbHjkUkf^XA9q z^!L1lv7G}wZ)q%ck>}kW8$87GmdEbC)bm!xz8dCvt73I?Jnw6fL?|Iu}7fH-IWlE zS6uC`g;0Fx8h15>;;YxX>md}kf6cy5C~p58dA(5F{ypi2p}75nz)eDN`xjlChvN26 za<&e|?cY>v7mC|Iiq|m|w|~{FYbb92ELG1?-2Ppm-l6!B?e01W#qD4A7!-=zKg}>C z6t}-ye^@APe>wW_P~84@>rtV&{q@9SLvj22WhaE<_7{Xs4#n+ncq|IV?XT#Y9*W!F zu{J9dx4$Io+ECp7mZQ0$__qD-8Vbej?-^MbirZflu{0F7pY*>y6t^GMULK0u&)TjG z#qEbBSB2vC({2xh;`ZZ84~OFR^Cpjn;`Rdr>qBw-6W^Ocar+~?TS9UBGnZRKar;Aa z+e2~tQ%|pk;`YZ@-U!9*&mHUz#qAr%dqQ#h&foi?xP9y9<51kb_P#F^w=bUV55?`P zU*Ck{_T`IjLvefjc{CKa2N1_Xak~fjTPSXy!cTYN_#%d$mw2jhSILTBpw`eznE+R@&$#b?w#K zYOJugcCN;18|^d(gxqMaan${$4xOiQPt=VL8l&wJbPR@jE+ceSdij)adbRYyl{1_Q z&ns8QOG!D;CC>|2^1|tDQ_f9klX8A}_lwj^l046E;aN#6A4*9HULoXWB+Uya@%kw# zX(_2Gt=+FAsq%lkR?VzyHL@2sb}#;q7iEo`G;+e! zQF&Ptb4QLHH|hWPi%~eEu1*4{po0Q)rzaXzs$;V=PQ9<#CB>0H*E65-3 zKIVm411IMeT+w~%q?|$S*D|KxgsFu&13IR05v>bb7}ai%vRf6|y*#sB*s zrm{;fNN2G@m%Gl2-vOLTzyv()_gS~%v&Y+SjpA2rqBr5B>XLLWxlHzZviOxcm0q~6 zT=C8HvJwfr^X%3oZz{VK8#u6$U8>LhD)g=qQF7h8-~PoHAiI=OwzCwpCcLmzS9W)< zno?9;TkaPToX0bEwG`j2$7yz>dAa)}6M>ddhKVIx%%BT6r56eMRPr5ch;|+YoSfa<#iulUEI?o+Z}pA+5n zQC#dwF8(|ceER5Ca<;n$^cG7m0oSqn2z5PZn9gM&VCmQu?uwN}Erl$iUR?B0Ii z*!+T`l23z9GM6F{Rf4JH6Sn(3So|t>g%|%?+=n`Nri`yrPuZoQvP(sAb!WQ^TYR$n zj9z@?>dbb(IfA!ZMoTFU_s;dP$#(Zaf>(6E`Snc6hcG*!V;8f`t$eo5aAZn9!0x#o zeFxX-(xy!5V2fYvw}H z*r^joxZ~&v`ME`n+&%R6?rIrj!M*0_$tdB&LxJ*=&z;4nb8`Ok6FYZ3OYeEY#_lU! z*nMEhC+uwQXqMh-EWNK-dRNii>4Z=4yTC49iDT|&mfi!@9l#vB4bt!AoPzA&*TUV- z(z}2B4zYWL!AD9mgS&pk9}2s_sk@-XzvSSzVabPq-*zRqv2FJ|uPC{h6oy0P~ol1XGl-|YT8ZW(rS8`1T_Y%DxUAnZbRnL9{bt;%xtJ}m8 zd80(ksmM=Ox?_ zzOme5d-UF^jr(7&JvR12S?*cCb)!Cw`*b?Lua}q+>609eCS@j62vrPK4p#|P4V@OM z7OEbqS?-KbV>|i3p30^K@8^HZzBp_T4$C}+^`!?=*d7~}c?!G7g&AeGeUZX_eb$>* z(n`N*VJYmnFNTzP3VZHLNM)YFp8MiXnWwPlzIIgR$$d$>%(A!VzD!i+DeT3|EPHwE zzjmhQzQ$DitF(`Erai9x@5je=io80byaE6H8^OM)R?faOZAbTIY5R5Cv7(Odt2bUb z_Z6Gkc66^)Pu;FBdp-Bn<>I6JnsV{6vyT0A9IT^z#9sXJ@jAM%{1)%oI?mN`sg7%O z++bhwaqnlFj(goN&Gwf%9(TV0+adQMw_|1ZYq8^*I<|3_-F7z}hq~u&kI`|J`%v0` zLdQey17Q1C9UHnU-gX-u3*49JZO_(mOO;^1rsJv8f}K(=ICgbkz_-`$uj7K#gMFut zd)x=sUjDg`mFfihOdW@v9qe&B-tVped;KSM{Pvt+AJ?&QqhOz_W0AX}?DenH@wx0^ z@6gd}9_%z7ySppYUVosD3tI>KE*;-%8|*K2tm3YCd;PO?yu3rOuh8*f>v)bYVfgS}D5qr-yzr;bf?g55#K>AAt4r{fC_x_vy})G=XnurqYLU~I52)^X|h zVBe$ThZBN*K*#F&!LG04h$+F&*YV-PU~ks($Em?Ssbll$!S1Bv%$dQyQOE7>M$Ino zTRJAr4t9ARdtVpqOLV+-PO$IO@#A^HKB!~O`N3|Wi@U`yU-! z-V*FCI?lQ+*f;6;@*Tl`N5`b)!LF!d-xa|gs^je|gS}eEPu+KY?ALo($6Bj{-AKpL zYl2;<J*++xjOved7 z2788%PaO;Pi#ncg-$JwV{a=IQdB=leFCFLp5$s!Z-1TR$KhiP&cd%>dc+sg~kJNFc z`>bwn{}CO(cHe=s{gaOM+?TIyx6pBt`<|Tbt90DtzBy<6B_02A-=(u1aX%(w$BypX zb$0Bd;|=cncD8TRaku*hp6yR`%yi$$vwgabL)^FYZ0G5CulwGf?ZGWR2Z}*2bgk3#RU?)T8s=8O6`%ju=sp zH_a>a(%gdFNn`Td+bKQaf0haM{Up5!cR{?yBi%PY^4!edAJRxVsYn@#H>K#ZR@}|Lyg{!L+*`|M6rmv!}Z5Klh>k zzrJ2W_d5Ume%+^mk|(>a?5T(QkGE~x-E?^$yX%=Jp6lX*yW8k>)C>Bx4S7{uDDSor zu(xNIYoPm&bKJAu19d~*nPmdc=Ka^}?Wh;>YS{^T;`MUfF8hARb_o@`v-fN7kM}#> zJ?-o_v9?X}^`Df6-$-1BAM-hB7= z>~h)VOLhP8_LjNl?d>&j|JhTMhVIvEub?M;nfyUSWUdIl+-a0+ci&nbV z;~Z=De(mW|_g~q|x3tW!*FHX6zUSTZ?w2>&9g3fJySLYt;g0rx?a7XqwVl+){W@H< z-|HFfKYM%jcI|zZ`EYsloR@m8@x~6ig2j3G9-mqN~-maDP?tQu^KlnXY&#UAf z;Z5Gu>zC~XRnHn;=k!|F){gdy_I>5V(c!`W-E+0vfBoEl9qswaTiyRX_g{Q+4=-M+ zqi}k3{Sc$#F4U z=q^~fK2`eI>m~SM_cp>;+iP7|b$D@#9C07#a!G!=yLl;>6q)Wmk_idEeVL_PLd3ol z5KeTj9&T8^lY8~>ardsnO)3m>&-+X4{7~W=_s$X%63+JR4`oH{Z+@z)Kh1x-o7rAM zJTszaYyJ#)6Gi1oe z+g-R;+A-Vi(zVu3x9u)o8|^gP?(((OPIbGfyL{(rr`UFvubp<(w!3`owUceT%Xgl3 zl5KbSI%r31yUW*6JJGhge4Vs?+wSsp)=sePE?*aI_w|*|P2J_|s$I_QX72KJ(+=5o zm#@3FV~~`PP$#_8UH{3&|Ki|T#eW_>xr39D&?EAYdj%8H%eOzUS1hErPL+^8niA4i zQ$jA(l#qU!64GB&LI!9`$UsdA8Kfy8gEbLykv2ju)<(z>ZG>E+jgU*V5i(R8A;Yv0 za+x+lF4sm#jy6JuYa=9A8zCdK5i(L6A)~YrlBbQ3(b@+%+^N8wb}@|P8%WDYa?WiHbUlV zBV?X7LT=DT$c@?vnXiqIo3s(KKpP=9Ya?W#HbNF@BV@5QLY8PFWT|!_WKuZI-DD)E zyH7X?`GJrI_W9_Rh{-V_clh=PeT#)G)2R}2r>2A~*OZXEG$mw(ri9$BDIqI0CFCAW z3AtBOLhjQ<$SQ4wtky=z{n`jwqm7UUv=Opa8zB#BBjh1%ggmT`kVmu;@~AdK9@9q1 z8HbT~GBV>a%LY~q_$VP31Y|=)^X6-=8ZQ(3;{U^_`+mPD>AqVaG zrz0lEggocl9|A8H^1M!!kgb{$vQ1M$UeJ_~7d0hhyQYM^q$wdUYf8u~niBG=CPH4* zM#$^h2-%^HkTZG^n7jgWV=5wb@cA@6D<8wQgs49tyF`+Pb<|V@Y71C6ZmPRS_FPtsWyS1Ryu>gPb-~C;HQ=95FC)SgoJXT z@N*7G^pv~jnh*{JiaxdbEoX%y#>*7d5Bc`vN5zWH;e07-z?PzhY$BA)sg} z0Y$eEP;@H+MYjlIg$_t`x_hLZP#{Iiiyvo&BIe5!Ef4wjT0=n50|XSUC7|d*0*W3Ypy*)&iXI`L z=urZS9wVUWaRQ2-AfRX+0Yy&|P_&+aq74KTJw-s#Mgod95m2<5fTE`fD0+r~qAi3# z(XvqZJqIM(${v2*DMiCf(X*k5`7%Y@Lcaa@b+MusIA4lhWJ}R@wiLa@mZF#0QuGR2 zie6<)(Q9ledYvsrJJ=|CgMgx)1QhKepy*8kigpuF^cDd{Zxc}T4gp1b2q=1&fTH&Z zDB4Rv(fb4xeLz6bhXfRTL_pEU1QdNjK+&fJ6n#cO(LMr-J|_f$J_pZMPMa-8e`a0y>kM9>NI>7l-^bK2z4zi`_5L=24v!&=;wiF#NZsAt-QC^Y-QC^Y z_1^#N-$A(UXI<~^wI0?w&&~If?2ybHOlF2O`9`4VTY;kQ1d6^FDEdL5=tqH~p9G42 z7AX2fpy*eDqTd9HeitbEL!jtSfug?zivAWT`bVJXUxA|k1d0l6WJLq(xD8=ZB&mb|~s;hoW9~C~CGtQExjG^|3=yUpo}_ zvqMpTo1zs3iUtT24HPI^NuX$DfudCeiUtW3ttwEonn2O&0!4!biq;S)8X{0MRG?^> zK+$l4qBRAIMhFzGB~Y}sK+!q^Me7Q=qUG9@zRZABtJ&AKhvUUW9NsWP3%y#sU33Pn^La~NOhZZTeM*)+Bkhio8G39d?iJ@wkfA?U(}*#H|K|<-R)4c zhaHOcv_sKeb|~804n_Oep=e(_6zyk+qWx`(4iG3hP@w1_fue&2iVhJdI#i(OFoB}O z1&WRkC^}N0=qQ1rqXmkN5hyxVpy)V(qT>aMP7o+MQK0A~fufTIicS$II#tLO&1_TJ zH3L#zIz2@+D-^X&&pMvgrjmRmMQ61spSDaWI@|f7=o~u~ook1p^XyP`z8#7#utU*> zb||{Y4n-H+q39BuqDuveE)yuaT%hO*fubt~imnnUx>}&<8iAr~1&Xc{D7s#t=mvqJ z8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFitZ9}MQ5}r-JJocev_VcJTnxHNVi3I zx2YswNzwgn%IVvuwcHjx;QUbZpdE@HvP03sb|`wp4n>dJq3AI?6g_T-q9^Q7^rTJE zQvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3 zTLMLI3lzO0Q1q@q(R%_#?+dx2d)t)SET1X*G(FP4FBGku?p=S-rjmRmMW3`OFVQ^| zed_#B^qC!sKDR^B7j`K6(hfym*`erbI~09mhoW!oQ1qQm(f0yHKL`~4C{Xm1K+(?v zMZX9X{VGuOn?TX;0!4oa6#Xes^p`-<-vUMd2o(J*Q1qWbQT7el&dRRF>|fNgn}PIY zr$vFHHUdQ@fuaV1qOy=H`lwB5L)MSUEnjMPjb|~s(hoa7QDC%N|qPc8}<`yWLN1$k4fui{Yislz6T0o#^ zL4l%$1d0|GC|X3IXi5-3_)plBI^qGbh&mJ@PC z?MkI%Ga%I)(_NwVrTmfp-RZVy`BEkMN{V`x%IVvGwkYc5{7}?vhoatgDC%Q}qP})0 z>Su?d{&px@(GEoe>`*k&rf4OBqLl@TRuL!~Bv7=fK+$RfMXL)G4HhU`L!fAgK+#Zv zqG19>!v%`g6et=YP_&jn(b@t<>j)IBD^RqaK+*aFMH>jYqVA>A%NdaBF6pjNk5Duu z-4<jU9@%wL{T%b|~83 zrf8%<(GCJdqXdd}6et=kP&7uMXskfdIDw+^0!0%9iY5va?IcjNvp~@#fuhL*MNcA)h&w7bABi~-ws6=*rDh` zI}}}HhoXz^P;`kMiY~Q7(Pefhy4sCydsl`6?sQuI)%oWA{ei=u~}ABrBaL(!vlD0<8eMUUH|=m|R%J!yxcr|eMl zv>l3`u_=01py)Y)qUQyQUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vw zw*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|Ay@Q3sq}RQq&hu4>-bcA`7MgRaDFKI(hfym*`erbI~09mhoW!oQ1qQ0ioUl)(GPYg`q8H7CxN1$1&V$V zDEd{P=r@6)-vx^P5GeXnpy)4wqQ3=-{t+npSD@%Wfuce~JZz_^C{WZ!pr|BJ)F4n) z7AR^fP*f2pYA581J}s4cXF#e)q&w7~g`(Hf!~XUSmEex_DKYpP_QIqpSQOyoT zbvqPwvO`g4I}~-XL(yDzD4N?2Mf2F9XkMG5`2>pQ7bsdlplCsXqJ;#C78WR4M4)I< zfugPgMT-d(EiO>Bgg{X@fubb^ik1>6T3VoJ8G)i@1&WpvC|X{iXa#|y?n17pv7xkk z2Bez4-F`!dhWwHKJ?Y+ckA_O}l@#@ED4#Jn6!md_DC%p6qJDNL>Tidl741+ozz#(N z?NGFm9g0@AL(wWWMS}#2Ruw2(O`vFXfug|zMQaEY4G}0BDo`{`plG;2(V7B9BLs@p z5-3_*plBU|qICs|))OdNU!Z6MfuaosiZ&7`+E~aH^=c^Hn*pi5pUsBmP&6>zFm2LM zNxqVzEgH({$G^1P7H#SLP_&gDing{x(KdD{+SU$5+u5OLdpi`3v_sJjb|@NUQ?#Q% z(P)99F#<(n1&YQA6pa@snjla#QJ`oifufxSiY5sZO%^DcB2Y9{plF&v(Jlf-(*=rV z2o%i}D4Hcuw5veTZbGhTvxZW`&`i-L>0dxL4@Ebn+oIhYD#=$;w0A=}{rI33Mf*5E z6zyw=qW$bpw7(sS4zNSffp#c5$PPsZ+o9+XI}{yiQ*@X>(cuC`M+g)hDNuBjK+(|x zMaKvf9V<|DoIug>0!1eX6rCtgbdo^P$pS^E2o#+vP;{C=(dhz3X9yIXDNuBlK+)Mk zu4vDO(%Ko2YBhb`^6y2_^LYJs9_1d6T|D7sFd=z4*o8w84O6ezk$py+0SqFV%t zZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2ZUVFc@3rGGa%JP(rwZC zq3GFk@A|=pO7fKyJ=#!CKfbI*(PPdJMUUH|=m|R%J!yxcr|eMlv>l3`u|v_bb|`wz z4n@z~6ulr&^rAq~O9DkN3lzN~Q1q%m(Q5)luL~5tAyD+DK+#(QMQ;lfy(3Wcu0YXy z0!8l&6n!92^r1k}M*>A33lx1KQ1q#gD|)!0^lApAdVKmM_DCo?AwAOntf7*8B}HE~ zl+%yDYf<#I^Fz@$b}0JR4n^PDq3C-%6#Za_q95&0^phQmezrr=FE&NL3Kab&Q1rV% z(H{aue+m@+B~bLYK+!(}MgIyE{U=aVD96Kgii!e7Z3K!+0!0l1MP-4awgN>JfueQ- zMePNOsscrgLaykGhSEaoWr~hSpV7VyMPH`RXdTLx`*k99g60*L(x2TD4N#}Mf2IAXns2sEnri$pg_?=0!0f86fGi9w5UK)SAn9%1d0|H zC|W|GsGC61k^)6b2^1|YP_&Fd(Xs+X%Lx=MFHp3CKv8#rq8Q^qOAHUh6sK4_=(Ta8`8eoT_fp#cb$qq#;+o5O` zI}{DFL(!^sC|b>?Xmx?2!2(5V2owzwC>knIG)$mqxIodG0!1SPiq;Y+T3euK9f6{C z1&Y=aC|X~jXaj+w4F!re5-8eOplB0;qD=*gHWPA1eafZFGa%JP(#=obP;^!ro0lue zS5mZfxtxA{Ym1_7oF9s|wL{T%b|~834n-sFP_%;`ibmO?Xh%B~jkZJ47@MN80!8Bl zipC2RO%N!WC{VPMK+(kPF1d3(~6wMMS+Et)v zH-Vzv1&a0%DB4rV6>V8AeVYNPo|WzjZ54{HNVi3Ml`F|tQnX*WoPPXoi=zFVABqmJ zL(zeDC_2avMF-oV=ny*;9cqW7!|YIWxE+d)uqirHpy()pqN4?hju9w2R-ouOfuiFD zicSzHI#HnLB!Qxn1&U4)C^}W3=rn<%(*=so5GXoRpy(`tqO%2x&Jid&SD@%TAy>3d zxzslUQoSWTEZa8}J(F&W&M#MzucYYWayk9@=oUqnI6o9!YKNlB>`-*M9g427L(!FX zD7wlHMOWLQ=o&i|U29Wxoj}p`0!23n6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07cL)^S zDNuBmK+)X-MfV64-78RZpFq+50!0r96g?HJXilpTtmwnNb~b|`w*4n@z|q3C%#6un@Fq8IH@^pZ`{ z%K}BO2o$|4Q1qHW(dz<5ZwM5`koMxdx9P}Cq$R2C>|D^OGsC~7BA)Lx*dDp1rYP}D)7sG~qp zlaMR=x?F0zU8d;FY&Luoirz~P`)h40$yZX;rEPiXk)dcV=ZB)X?NBt29g60)L(zP8 zD4O36MGM%WXhAy^Eo6tHg>8x!5hz+zps1@r(P9EciwhJjAyCv!plC^fqNN0imKG>l zMxba}fuiLEik25BT0x+wyFgJ7fuf!QMZE-yngxn_3l#Mcaz&lmme$RHR4+>Rt~>l1&THkDB4`0XbXX&ErncB|F)$QGa%Jh(*2?pLs6SFwrX2RzLKKt+Lmt` z9g4PhekdAghoT+qP&CR8MLXJ|XtW)Q#@L}~tR0HR*`a8>P0<8_qKN`UI|&r+EKoE_ zplGr{(G-EAsRBjQ1d4VMD4H%%G((_hra;jwfudanigpty+FhV%4}qdR1&a0(DB4?~ zXdfY0v`yR6>lu*h3F%qKZ9~z1=`-5CZ7a!FQgmS3@*iVE(Lv4+MF-oV=ny*;9cqW7 z!|YIWxE+d)utU+2b|^Z^4n;@X6dfZ_bgV$paRNoh3lyCoP;{a|(MbYDCkqsvB2aXy zK+$OeMW+iCogq+kra;kI0!3#F6rCebbgn?rc>+b}3lv=-P;{Y?E84$pX_0Z6qVDMq z^#P%1O3MSbww2^7DY~p}d9?|l=yK9l^ z$WEc?8Rv(hXYEk*oE?guw?okjb|`w$4n;57q3C5h6un}HqE~H-UK1#KU7+XL5_mQJ|NDqQQ13TEh-SL+nsA)DA_%Y>I{p6s;*xG(wSmq5|p0!8}>6zwZew4XrH{z9&3`%3A-3`lkV z^ssDXDC(X*y&X`gBwtCt{f!OQcU?SA?Rm>9**pN+tP9ik_>Kr|ubwo_BsIdch7w zFWRB#B|8+oY=@#(>`?To9g1GFL(%JYD0;)D=uLs5w*-pb7ASg0py*wJqW1)f-WMqP zK%nSDfufHDiar)7`b41UQ-Pw-1d2WvDEdO6=u3g3uLO#|7AX2gpy*qHqVI%U(KD6O z$r+I9l}XXFq3DcsTl9UUl6)maKUd1P>>Y}JaegTJ)ec3!*`ernI~4t4hoV32Q1q7_ zivG4k(LZ)5`q!rDKY^k`yLi}6QBk0%jX+UJpr}Ehs4P&_R-mXNP}EMKsJ%c@RiLO* zps0gDQAdHICV`@wKv7+wsFOfZXMv(F0!4EPxuPE{r8hGm)tTuF(|&SWlt|6pu9AEu zMf0~S|Fv%@TEO|CXhAy^Eo6tHh3!zZh#iU+wL?)?I}|NuhoZ&pP_%?iQ8$62B?XF> z5-3_)plBI^qGbh&mJ=viUZ7|NfuimLMLh(HdI}Wv5-4gGDC#Xx)JLGGuRu{hfujBb zMJoyv4G<_ADCCOfZCC2LU#94S^e-UuwaXvrFOfc@t<|6b-RM(NH@S4YNbha61&OX@{Z_HbrX*6s;{#w2na0x&lS(2^6g_P_%(S z(S`y=8wnI`EKszGK+&cGMVko}Z7xu>g+S4k0!3R16m2a~w2eT~wgN@l2^4KFO%W)XDo`{{plBC?qUi!fGX#oe3KY!}DB4w^Xg7hP-35yF5GdMH zplC0FqP+!*_7N!BSDo3`q66^sM8Kp=ka@>fm;j z8P_C)yO9Bv5p+ zK+!1zMW+fBohDFpx36 zIy)3yZ-=5A>`-*09g1$UL($E4D7wWCMYr0a=r)_8+Xag55GcA+py)1vqPqo(?hz=u zSD@%Vfuj2biXIRsdQhO~A%UWY1&SUKD0)<&=rMt!#|4U>5GZ<5py(-qqNfFlo)L0I zSG6k*$beL@%4WmWp=g`*8SUA2mE`?T& z9g5ztL(!XdD0<5dMQ_^_y(3Wcu0YXy0!8l&6n!92^r1k}M*>A33lx1KQ1q!l(Psih zp9>UyAyD+CK+#tMMPCaPeIroxtw7Ot0!7~o6#XDj^rMg~dcIw0-wa6h`7DF;LMZwp zJ(2xWyGrtv6#dq&eBRNa=y&IbqCf0V^rsz){<1^S-*zba#|}mR+M(z_I}{b#$K&=; zRJ18-BT!TlC~6QWDhm{~6)36*6txp5YA;Y!6)0*HDC!_k)KQ?QNua1EP*fKv>LgIq zS)izkK+#+RMRN-j%_C4WuaGPHrCsUa3`q6Pbo29TDB38E`Px^KucT<9_T^8G4Mht( zKNKxuhoVL8P}J29MT^;?XmL9fEn$bEZgwbI(hfyS*%U1;P_&Fd(Xs+X%Lx=MFHp3C zKv8#rq8LXCpSD>h$Kv92zq7?;-1_%@l6ewCrplD@*qE&=k z(E{yD)#EZn2ei%LEZ9DOq<>2qgW6Y;ucT;j`||Q9grYT^ABu+9p=hWbiiX*tXt*7U z*0e*>2s;$5Wrw1*?NGFiP0_jnMe7L^tuIitfk4rQ0!14M6m2X}w245`rUFHq2^4KE zP_%_W(Ut;5TL~0xEl{+LK+(1WMcWA!Z7)zXQlMxDfud1Du4uLPr42J6)eF- z(Jlf-(*=rV2o%i}D4Hcuw5veTZURNS3l!}kP_(B&(Ov>YdkYlpBT%%jK+%2zMf(dB z9UxG2pg_?<0!0T46dfW^bf}Ok8q>aXY6hgbP`ddU8;br)--!RP_Lbx-DLSfs`LkP(2o#+u zP;{0+(b)n;=Li&?D^PTvK+*XEMHdJZT_{j=kwDSK0!5by6kRG%beTZW|Zm>Fo?i^}=j692tr(PG4+vb^A*4l@wjyzWmQ=q38zZhoT$pP;`?Wif*<; z(Jgi;y44Ovx7nfSb~_Z^VTYnSZHn#^D7ssq=pKQhdj*Q_6DYc0py&aCq6Ye zSfJ<;fuctRiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFK$Q51NzO?x1nW7WY z6OGq}qWRN5hrH0fl6)maue2`@IWrW!>ikgjnjMN>w?okzb|`w&4n=R-q3CTp6uo1I zqId03^qx)8`vOHD2o!xNQ1p>N(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1%l|a$g0!7~l z6n!gD^qoM__X0&f2o(J&Q1p{P(a!=!zX-Xam)e&mWI(EyqzCsehoT45Kh6HyzLI<; zMSr$0A8~dl`pfyD=x;j|{bPrsf9+88pB;({)p+C{ii&n9YGa3@k{yZ~Y>LVPMQsI& zDgs6A1d7@V6jcR^8U>0v2o!Y`C~6WYstFX;1&TTe6m=FT>LO4ymq5|n0!8x(6wND8 zG@n4x`~pP_2)Ux)+n27*fK*pZ_ly1rMTex@q6Mp!vXiYm5jj%(}T6QQ}+YUwR*r8}$ zI~1*FhobduiZ&1^+EAcqBY~og1&THiDB4t@XfuJL%>|0K5GdMGplB^?zBVE zU3MtC+YUwd*c9C>P;{R_(ftBN4+s=JC{Xl}K+(ejMUMy+Jt|Q2m_X6v0!2><6g??W z^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0kSn^OTIz6lrf7@wl_58VqEfmodbwIj zzLKKXtL5%jhN3r|ABx_zL(yAyD0p9|Vei6e#*hpy+3T zqF)4xeibPCO`zy^Ay@QjwX|^tq`Gl}^I9m{FnxOaqgqM6lA?dAHTZi|LA zR+6uzXwAm*f7gei5zY@qYuTY_Z95dLV~3)3?NGFy9g5bsL(v9yDB92tMH|@^Z7fi< zi9pe&0!5n%6m2e0w1q&?mI6gv2^4KDP_&Ie(Y69b+X)nHFHkg6plAnyqEP}xI|>wy z7AP7cP&8JcXq-UNcp+Cbtg+PXhD_1#=~>6&q3HAMWepP=E6G<`-*F9g0q|L(!>r zC_2p!MW@@L=nOj)ooR=nvuuja7AQJLpy*tIqVoib&KD@UK%nSCfuf59iY^u?xO7be|oH z?zbs=K%nSBfue^5iXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!?g7ASf~py*kFqUQvP zo);*3L7?bGfuffLie45ddPShYZ=ucWBZp}gJQp{Up)9?6HIHg+f~*`cVx z4n<`<6t%TOQN<2L?d(w0-VQ}oo1#X6q7DK@9R-S-1d3_`MRkFqP69=p1&X=|6wM`2 zG`B#}JOV}Y3KY#JP&B_l(EcEo+COGutQOII~4V> zLs3tgqFw?;%>qTe1&aCz6!jG->L*atU!Z73fuaEdMFRzjRuU*$S)gbYfucbIMXL%F zttL>kxEAqV?=hw7wmRHn2m{hIT00$PPst+o5O^I}~kdQ?!{t(dGh0TL=_w zDNwYPK+)C$McW7zZ7Wc;oj}p{0!1SQigpkv8YNJ)qd?JUfub=2MPmhu#t9US7buz_ zP&84XXeS|8G@?VP>48kqj_IGy)(SGwo0`%ML}m+M#GSI~471hoU`fiuM#J+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bf= z6ev1Kpy*(MqC*6V4izXmOrYp+fubV>ijEX0I!d7EXn~?*1d5IoC^}Ba6;19?+B5@F zJv-f@o)U_#P2>0umE%s-5`m&i1&S^cD7svr=n8?ND+P+K5-7S_ zpy(QbqH6_;t`jJ_UZCg(fub7)if$4px>?8-o!FstW(K6XQTn>;lS0wUY24DGl6)ma zcXTM<^;jsn)A^z3E;|(6ZHJ`-*C9g6O=L(%4(c2wL zOJzW+<@BuMJE5p&dZhnfhf4C56qP!b*L*q@HFW%+kMzrSC~9kmqKX}g+S#F~y&a0G zb|`AJLs17i6m_&IY7!`_2^7@@iaH4tbrvYW%Nn|M ztR!Da(J~#&$2=Q~mUVvI7A@jd>R7rl15#Z!!C5*KjZUB5*6LVEzLKK#I+kC0J`}C*{7|%k z9f~%zL(xWdDB9Q#MVr{6Xj3~BZDxm}&FxUMg-y|x0!3R16m2a~w2eT~wgN@l2^4KF zP&87YXa|9!Q36Ff3KWeNC>kSBG*+N!oIufdfuaclMH2;zb`mJsS)gc=K+$9&SF}#Y z((f6N>fY(LXx&gWe|p$IrDG-eN{Xg;EYJT^D4OB?P&CsHMYHTsw5uJ8cC$m#?sh2J z!wyAz+M#GKI~470Q?!pj(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3Eh(OVy0!4=j6df*5 zbc8_Bkpe|W2^1YIP;`ty(Xj$W#|ac2FHm%XK+%apu4r1v(yAGd>Tl`a^mhqGC#2h= zlR8$CucYX-j^&Zrb4V>;8FISwL(v&_C_2*)MQ7Qe=xjR_onwchbL~)co*jzLw?okd zHboZ-6kQ}xbg@9uB?3j43KU%?P;|LK(G>zkR|*teB~Wy=K+!bdYo=z;V||MrfREK+*RCML!4>{U}iMlR(kW z0!6GKvAJ79+*>96mmuHbu882 z%oKG=w?*%Vq7mscTAQXy@|6^|Z7Mgv9f~T>4@K?lP}JTIMO8Z#HQJ%5gB^-G+M%e) z4n;LP6xD5tItdhY7AWc>P&Ai7(cA(>^9U5pD^N6_K+*gHMGFWNEhtd5kU-JG0!51m z6fG)H)K#EpF@d7R1&WpsDC#Cqw4^}MQbMk%p{cZa2Bi8&`ZxV@Q~pRlyQiH!U~8%* zUrEvOP37I*4Mi(BKNNMhLs1Vq6!o-2Q7=0bHQS-6w;hW5*rBMe9g6zd6!jMkkHw1Ys=D1o9K z1&T%s6paxm8Y@sVPM~PKK+yz&qKN`UI|&r+EKoE_plGr{(G-EAsRBjQgj~`3O{EVr zAk}%&W3&xI(bnnS^)5}70!5b! z6kR4zbh$v$6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z2XMK=l*-6T+Svp~@;0!6n9 z6x}9Jbh|*&9Rfvn3b~@wn@UqMAl1?7S;sR%(XHvW=&q(p@|6_b*Hk|4vru%u^Fz@C zb|`w#4n+^yq3B^d6g^^xqDSpe^q3ur9=Ai$6E;Op3KTshQ1rAw(K7-?&k7VhCs6df zK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1Q1rGy(K`Y~?+O&XC*+Fm zX)4{E0jW++_pa{^Mg7uvzp0XZB}E@Mm0$TH6n*0SQ1q!CiaxVL(dTw3`oa!HU)rJQ zD?1c@ZHJ<7>`?TrP0@D(Mc)e){UA{Eqd?J50!2Ry6#XJl^s7M8ZvsWX3l#k!Q1quj z(O&{Ze+v}-BT)3OK+%5!MTJ^CY^SIwP}D}Cs3cI-AmoZZY%2Yk0jbs#oR31$gK3m& zmE9A%UWW1&S6CC|XpYsH;HHVgf~r3luFOP}EJJXi0&h zr38wW7ARUqplDekS5&E$R?mP`4@`H3+ST$$`d_9ekCv-dlCPwwN3A^S+fdZg`Jt$n z9g3RmP}JKFMSbj0)YlG0{p?WG-ws79+M#HGP0>JsqLl=SRu(8)MWASqK+&oKMXL!E ztu9bBSfFSPfubP-MMDLOh6xl67bsd&plF0Z(OLpUYYP;uBT%%iK+$>vMe7T>q7`bT zLo*=No6=*n?xE=8mIrLLO7fKyZBi>=_I)VY)cK)kGdmP*Zik{R>`=6&9g4QHL($fD zDB8vjMcdk;Xgiyt?FEWP3KZ=iP&7)QXh(sf(E>$d1d7HA6pa%o8ZS^ZL7-@&K+#SD zMLP==O%f=YEKoE>plGT<(KLagT?C4z3lz-|azz`}N>67%s*j|9#@{#;?VE0kX4Wdn zS5mZlt^Cc8p=b~1hoU|0P_&mFiuSfc(LQ!4+Sd+6``Mvre>)T%V27duZHf*OC^}f6 z=n#RTLj{Ts6DT@dpy&vJq9X;0juI$3TA=6{fudstijET~I$ogY1c9Ox1&U4*C^}i7 z=oEpXQw54n6DT@e$QA8cD|P-UQ}j-HqH(uS^k+F6XVfamS5kCNt=#9AP;{>IL(zG5 zC_3K`MHkqi=t4UbU1W!%i|tT!i5-eAwL{TmHbs{U6kQ=ubfrMiRRTp<3lv==P;{+8 z(RBhv*9#QgAW(FpK+#PCMK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZW*0ii!e7 zZ3K!+0!0l1MP-4awgN>JAy@QCt@LpQqucW9$yK+!OPqTvEX zYYG&N5GYzpplEG@qICp{))gpPPoQXhfuaoriZ&D|+DOP1^{khsWk9NHrQ4!jq3F9b zHm+BaucT=6dijJxdIP-*4O=)r6m4mTqOI&uw6z_Iwy{Iewst7m&JIP}+o5Qr9g23a zDHplBz7qMZebCJ7Wx7ATq`P&8GbXqrIL zE&@f<1&U?}6wMSUnk7)QtB@<&v|hS315!OR{nOcIp=hUcTeMrfl6)mad)3RYwFyOg zJ3kcdV~3)B?NGFz9g6n1L(u_tC_2y%MF-iT=wLe(9b!{-s6f$S0!4=l6dfT@bfiGh zQ36Fr3ltqAP;{(7(QyJr#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_6rCYZbf!Sj zSwgO8k9z6v3`lkD^xXBHq3GjuTXc54l6)ma=hw>%mqXD7&JRTw+M(zoI}}}PhoVdD zP;{vsiY~K5(dBk1y21`cSK1U^B~Wy=K+!bdKq38)a6g_E&qNnUo^t2s{p0PvGvvw$Y z&Zg*jfua`#ie3~bdP$(@Wr3ns1d3i2D0)qx=yidjHw22_6exO2py+LZqIU#}-W4c% zPoU_1fuautiar!5`bePYV}YVigj~@>_0r)Pkm_9Nw&>wdR7j*gtyhw-r0C0f`HJ?T z=qu-kqOa{x^o<>gzO_TqcXlZH-VQ}S*rDi0I~4t7hoYZtihdC&`cN=r4hyzXgi^5h(gspy)q=qC%&5*iKPVps0;NQAwbvL7=ECP}EkSs3K6*PN1m0 zKv7l56@6YWJ(~fkrvD1I;fqi-EIrb1>{LmCt@^_7)sP6nw)X5G-o$XN6#STSt z*`a7|I~2`hhoX7yP&A(%isrW|T0o#^L4l%$1d0|GC|X3IXi5-3_)plBI^qGbh&mJ=viUZ7|NfuimLMLh(HdJ4Isj-5(#b;uMgmHq{! zsZ;()|CbC;L$6MizRV+D%F2^5VN zD4HNpG*O^vCxN1!1&SsK6ipT=nj%m%RiJ2^K+!G&Mbia}W(X9`6eyY{P_(N+(QX1o zy9*TUA>@j-=u|pC15)jfZi}`IMX#o(AouK4NxqVzeLIyO=p2gnbABk=-ws6w*rDh^ zI}{ychoXb+P;`hLiVn3y(P4HdI^3q{2!Wy_1&WRmC^}l8=oo>bV+D$i6DT@fpy&jF zq7wy*P7)|OS)k|?fud6dicS+KI$faX41uCE1&YoRC^}o9=p2EfbA?>d-knOHWLayk7PNfwxAl0SPSMOgKik?chMGtqXBwtC< zXiaro1`cRx3Kab%Q1rJz(LVx3 z{|XfSCs0)A91q(mDhd>}5hyAN6g3DGl?9603KUfYirNVjwHGL=3KTU86m<|N>L}!j zzUoxEJp)qhkZy~<4n^bAXSAlymEfE{f#)6@!i}OR#Ty`j$+YUwZ*r8}%I~2`l zhobrIP_%#@iWam((Ly#w3kwu2B2cubKv7qLqQwM?78fX5LZGOdK+%!{MN0`3EiF*A zj6l({0!7OS6fG}Mw1PlUcY&fF0!2Lqih2nYH47B=7IH=P&ZU1dAl1XuQ$(FQ=a2M1 zOt(dSI#-gfq-e#?MFX54iU!)DXeB!ot!#&)RqRkS$PPuT+M#GQI~1*MhoZqY zMQaEY4G}0BDo`{`plG;2(V7B9BLs@p5-3_*plBU|qICs|))OdNU!Z6MfuaosiZ&7` z+E}1y6M>>l1&THkDB4`0XbT}%)UR`CXa=Nuc!JYE6m64ki?-}sNxqVzZ9A98b`3?_ zIX@I_Z-=6hb|~7x4n?EvP_&~RibmU^Xp9|-#@eB1oK4YqfuaclMH2;zb`mJsS)gc= zK+$A@qA3DJQw55q2^8%jP&8ejXof)1Oo5_V0!6zD6zwKZw7Wpj9s)&s3KZ=nP_(y@ zE84nq>BtO7^^WvNf16NrNc!})Pv=VVl@uM&xqQ{)q3A&8hoXb*P;{^ziVm?u(V=!I zI?N75hufj(2s;!VX@{btY>JK+C^|-<=vaZG;{=M17brSGpy)(_qLT!QP8KLSMWEmns%&mu3IHR;WFZz}3FW{>8Rktz-6Ru0t*T81;H>qmG5b zT(whbg~EKbw>lLH3)L2zt5E1#8$VB>(5-gOe1*a?wVxI!6jrDWT)0r^RoidTLZNT% zk;Mvy0ky_%g~BSejg~4DR4zC@wQK4{j?TJkah2v|r%?pK-YnyFZD4bq9 zYwJSc?Aiz077FLrmL6FsTwI$xs!+JRcGKuW;p*BSV+)1rYpYEt6mG5^vQwdOd+n)7 zg~HvnPE!ko`)gb5QYbuJJ7-3r@ObT`S%t#WwPklN6rQh5-Lp`5xpvFmg~IE#zxFK@ z-mVQkpip?fcGy9M!pF5|4k;8quXQ=RQ24sG)scn5_qFqmE);&QeR6D}@Oy3f6AFdD z>${wkUH--TZKq^cK(YSMY1uVUtPeRey9$c+BhJpQgJS);bF(X{=++x49_0 z8jAG`F3GNkVmrymI1t5{Dz(Y0@}o_-|ffMPxUOvP1- z_4GsWRxj4mPc<7_tfwDKHKJHgKUZkoV*QKzv+JZ-Pe0jX(_%gSXof9|_4K{09*eUaY6@v9@=yp1w)e z{>6IwE=LC!>-W5$T|>os`aUB^7whR8MI2wOr~lIb*>F>J-b*>|FPux z#d`X$-7YTH(|@jXd9j}Udy}h+_4FSMTwkoGulT;XSWjQFdwa2-zUK1oVm*D)-2KIR z`l_dgi}mznD~}iJ>FW-jF4ogO96w*Ir+@i-xmZvCbn|+#o}PPuyI4<8p1xnKr)R%D zF4oi27oQjF>G9{+#d>-G@qMwL?g9Q>tfx=mzZdK2Hu&#iq0@Ki%N#Dw|H^glnf*N~ z_Q^_i>1O{cp50|?_SAo|U(<0Zb;&O6La~30&gms9#(1rijR8#uwY=I<+26h5z<9}t z*;^~F6yx%A&dM>aOJfzIn2kX()=F<})fiV*v$0x?hthkndOot>bt*2|)TOc1v|!U_ z^LENq6bfy+6&f2?%~GLInx{}|TB&j6#(|A%b;&-+cuBiLq1>;KO4}~Q#>V^=irK7m zER@=L{l>ddjDXO11ybM*8*rp=t1!sxMMW=$VEV~&@l*Uw&i zV9#mOCr+L?bKjGxeR z@bodWCQg|;Wa{*>-Dh7GyU(27a*^bh$cEFW?v!2TGkR_^ZPfIghtHZaa?|W%8NcDA zSu;j%Jh=aQ{r+EEO}mboIW}Edg+hKskDE1Rbgvcr_ZXchj2ts|+^AWTW{#Y>$F#9C zdQ3>dva4&%#3?hgk^SY}WXQ0Q*}FM<$kfS`r%uUQ!k68am0Kv5`V`CMF8|xFakH0sq7iW5p27AwX_09j_ zVMF2_XwKe~iR(_CI<2{|-ry}q4q1QG-uXK|)G7UDe=sXbeOf=L-m^cbA#=RR_~?5( zq5tgH8rbpy&zdr0;`k|J$8^oE(3U@LNW5Ro!@ZU4H!j0rE$6gcve`S+^7;d_R~tDp zJG)Qsk@;I_&i*hb4ENRs$6H&Y^(|zVK=x{5W=)>FNB)-Lb^H2*2S-?O_B)VWTeIKt z>_4QhKVxX?g^^tZ@rv2IoL`LDTgiVj$GfniQ?m=N<%QV=8|U?#{l>EQ#~<1|UcXQ4 z`!Qtp8O=ldQQ12lXCz*8-2VN)`ddGA?2fa>=O0aW`DcGtc0)496%g-7-`006yR!3F zpZ&2=)vNVG894jhZqEKT6xJEG)yTm^H*PsEyB^~s%Dl$!hW?K;3zMc!8Q-<#|NcLw znp@wIHG&OY*>%?P2jDatOwKb=8`g66PU){k%d7T^H<3w=_hgOP?^F5<-||X>Ti>~% zuJ}Ijve^<^{_v6M7A*dfww&5LVD=ksZl#9`Db1}GvyUm>5k6*1$Zl!!x7iA-Ig^#Q zUS8O0t$DaBs+E}QF8h%3^ZX`VNiBaDTd(NshA-Zg=Inj(+ve8GXO63T#W>wnl1oZ& za6s#YmtC~^pV8YN)=Htd)k5-gH@ke}-EF;za)tG4 zeSdNcEgyC3_1`=PfH|)C{@FXys?rTyGe7CY=?!Ja*%wqKS6g<|5-;jA`y$LP2(R9H z#k)>jrL(Wb0omm@bvE7B>%`4}y3vR?m!0DcX9Dw!F#BU$ev@4iUN-w(%KogZCB2(w zpPS?LotRx8EhSyaEuU5LPbR}=pPgL;@fKU(1J`kO3B}81UzgcckpBs-HnLlg?6q3n zc*~2j>o(5HZtUZCvp%6)3N_UMkXYXvw z$=RpimZM9&IrE#p)j6)v*6T0(!{f4P&hC-qubBP)jNi<@2%Gb3H@%y4+$=Z88QHbk zdI4v@TXX%*x(*pQuxq+I+@rZ`x@OtpDfIrFl+LT*>T*YsiS6g&+bhR%C43%DP*rXZrZN>y3d%_eN1!ztc;pIdcvUW z?)9z%x=-#gIlF_t{FoWjmLE5*YxnV8yKm6DYxnFP;h@pkJJ5aH^pID{OxJ|JJ5O;%oW^v2W<8gm*0yktT|-JN?n&pe_sYq zpWJoWP38I#@n-P9w`mcK$CQ7-$x|Ak5qsyk%=`!D-dEVS9XDSP~%9)SCm9%v74 z>Tq!BkT!=FH-GezhqGrX1`o{QsPwqCQ0$rgwmhKwdOg+~yw>`Kww)^LwJ%lMb#9oe zICpX0(tO4FiwhJNEG|@Bq|M^R9_eBE|MhFm)KK{0zd2uAN)O!T_*IIh1*B4X+&0Ir zQudgw(;PcJfsj3STF9Q?j9=+7UF)w>A$y`?j$frh_Vmsize3ulgBr9yp6krboIdV!oI8%$Gb@EQ*|RB&rDOI=%S2DtS9-ndnctRU_Iz*4ag8`` z7{|@xm_3?qdHGIp%$}8P+55%u;5Z&1$BW{4LwY(U`*ZGz<4f6xmiBvb{3ZJU(oSEe zn~w8lA4@te5yyeq`=0i&IBt{uKJD>wJU_cA)4nE-pJo?8+CRl{h3tw?dte-=XHTD} zyc99W>-{t{R857XLG(Ei({d0zB|Tocy@)R*WVwMo7 z$FH}|_aAZWJu=^`#c}sh`936$_h!)3GTJJ|~W^PRjR3 zaa?F>zL$;Tj=SW0Y8)@0k?&jL`0cEG{}so+yXSjw9QWKa--pHV{=M`4OdQ+pm+vld zT=#%{ZxzQA56bs>aeV!de18(hMGnvR@^KtD0#~&}t_kVF5aAm%S#c|)O^LclXkkdJAo-ySp28cXxMpcXxO9 zv%bu8zi;mT1hwAaNviHjEP1OTuW#6CMKdML2%5GLqVJWx6s)y3b?TWcQw0caf?2~f)RQ2Fm z*{|nzVD%_l*;C|po$BGXvPb0hoa%A6vaihTN7VyxWq+UBnW{(P${w2AQG?ohpWNP3 zJvLYV{K4E#T0PQT_Kdk5Qf?cy+5*|jvDT{ZlB0) zk8=N`XZ1i-xvl=b@~hldcRR-3Zc^@#RJ*!cQ0wehJ-nM<8@%%#+m9Yzedc`U(L1$o zxAIbTsX4kfxLn)S25-9a&b7fM4E~>Y$p%+fsDn2zpU$j4hrGqe>ea`-JbcqlcN(#4 z?LU7ye5c_%Y&oKOBme&a|7Y2*JkXOjQN0(n!JAc&N{pyJv;Ci=w%BR-_SGvby4s3^ zhmRh;)7G2rGP-)R|F6HQyE&E2_Wj6mOm#QnfBdTcGmZTUZ^@{r~!UvsAD1zyG~URL!sQ?^J%3=53c%5C{IX10?-mmih^{IY)dnZ*dm$x^h`dxnQIdeyCvhoV~RsO8}J}0+c z@3f&EwdL|U<;Lq>nV0?1N7d^&rnK_+mS2}vzyJIGz4o8~d&_?x@850J%ay%R)y>#n zs5biXGf3K%e7ZW&ykhC&d$c?&2rP+xQg}ht9Pt(#R*p| zuh-S6S8t=fPkF7CC)#9eYJOh*ckb-j=vSSNJ9{=Kss2lLbv4T8SUS6!&sVQf?@_&a zeU@<+EiaF${_6UWao4C`ZX8#R@91%1^_TVN>YA=mzF4YRz9ZB0`6~M#>{u9-6@spj0Zu30iCuI4<|HxkR7sG37-U4t_xtmeG6 zuGumtsOEgtbCEO0ujcI4yES|Ecx6}b*Bsg7mR-GLb7qfIcJ-dkl|8WR>Rp>VdqCOM z`!-K@|FWxhZfJIQ+0}bDZ+5@3t9Ng{?7n4J@8A5{eX2c2_5Ll8-Mj4S{aY}*Rd)6M zEtK7>?CSknIJ;-r)%&+dcC+m2{Tr6uqwMPaTQs{-cJ=-(mfcl$_5LlMU43q4u{o;u zZ;9;AYR_4{e@kX}lwG}lOJ!FKdUkb9Q-8er_wTiT@iXn%uM_XJNF}3d>1H{96d}tu z$`{g&6|zDOjgS>HBV?t_2w6EZLRQI)kX17yWVOr)Sv@mC*2s*IH8TlWE1QtDvk6%z zn~-(030W_jkoB_(*&v&c4YLW^D4URtvkBQGn~>qzglw8k$Y$AuY@SWXh-^Z($R=dV zY(lomCS>buLbk~!WZUevkY(#%R{#FJE~rj4UCXtF46DviUE4K_oFZgYqkNI&SRp&+ z&1a!_*9pxcrwBQvQN93otdLW4XoQ@W86jgb zBjohV2stA&Le9*Lkh3x)$fMbWJeEz!)C|7k=+(@TYc5)-@n(7 z<-W)5Z6R}%`y_8Ri<~0l-A4Js{joyc%b^kSerAMxkQpH#W=63TeGr z&LPzUT!l_~7ExD6qdcu+?6a#I9XUGBBI;r1Swu}c&m!t+=UGI(>^zI8W#?H$z3n`U zsE?gz5%sn6ETVq4XAyM^o<-DO@GPPMf@cv86g-P)9Ko}Q#uYq^XgtBQh{hK@i)aGD zvxp`XJd0=|!Lx`a7Ceh+62Y^GCKWu3XfnaGh$a_2i)aeLvxo)>o<%gJ;8{dd37$nX zwcuGq(+CxizFl3N9rZgZAg%Mu-IIDpThSZke#^8S&BCiFnz5r%o)$D#(M*nyqM7X| zn#GQyS?wqqY)8>-b`%YW`Wren)={xGx zR}$1(dzMqt3{iAfA+=mbv-m2CR_bV!rSfFSVfui98MVkr~Z6;8(xj@kf zfub!0inbIe+Df2kYk{I|1d6s5DB4b-XnTR89fY=`6*}rmRX|!dRkLfwD4ML08d-hG zM&+w0+PR}qo|ZUP(P+m<(Jpor?P^ESZgv#yZb#7`b`TMJEarog}ms?buO2x&qRgq`K1X+9`_0jJ?k4Xck{Z(U^`#d0OjOMW;JH ziq5d3=uA6`&a$KEY&(k1v7_i*JBrS;qv(7)iY~Azx=^6#B7vfd1&S^aD7sXj=rVz# z%LR(A5GcA*py(=rqN@dpt`R7@R-ouQfuidLif#}nx>2C$CV`@x1&VGFD7sak=r*CP z=+ut-3l)&o&~o{8S`=+i6y4s@EWV1OyE_`?Y0+a9-Q)Nuy4Q}P`|K#X-;SaO>?nHB zj-rR`D0!D0)($=qZ7srv-|h5h!|Apy)Y)qUQyQUJxjH zQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww}rN%J3HzVR*!nO{wWvkcSX^2 z<=*u>9nIpaDEgqIQJz*mR?&x!kD`z4DEiorqEGB7`qYl1&+I7r+>W9z>?r!uj-sz@ zioO;o`bMDWTY;kQ1d6^FDEdL5=tqH~p9G427AX2fpy*eDqTd9HeitbEL!jtSfug?z zivAWT`bVJXUxA`p=l^$=-)HROQ5^zBokCmDdmZ(SDj=;#%h!~=A4SiXb5XssS$q{m z&CW*owhUtx^>lm`^|GU=Wk*qOJBs?)QPkItqJDN1b=y(Y-;SaIHbnykipCKr8dsob zJb|L|1&SsRD4I~9Xd;24i3N%#5h$8eplC9IqR9n{rVuC^Bv3S^K+#kJMN9cVoj}p_LR(Rzvwl$pq_ti3$az7F;>y6j*p_j zb`;HKN6`>Fie|T?XbwAy=Cq?|E<1|mwxehso1&otMe_<2%_mSazd+Ff0!0f76fGoB zw6H+YA_7Ij1d0|FC|XRQXmNp}B?O9=6ewCsplE4t9qrTCM8qb-HGbqI$W~U$L`Ud=*8jb~ehlg&C`8HOEKM>UI>ZVMo!Lb`-5;N734L z6s==N(YkgNt!GEk`Zh%y2o!B7P_&Ui(Z&Krn+OyQ7bx0PplCCJqRj=0MhFybAyBlX zK+#qLMOzCLZ6i>$tw7Os0!7;k6zw2TG*X~wlt9srLR-CJBs$QqiAnCiuSRiXkR;u_OqjCf19EM z1d0w6C^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o5 z1d2`+C^|`?=wyMSQv`}m721kMch+~UfV8GBpCZ~NiY_nbqSHE?#aB^uW@qEH8KUSc z$4AlGb`+gsN71=<6rE>B(fM{1U0_Gig?1EOWJl4(Hbs{R6kRG%beTZW zJBl8$qv%mPiXOA0=y5xWp0Fu;QlRK5fug4cik=ZDdRCz5If0_*1&Uq}D0)$#=p})o zmj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J)y1Wp3Zvb%$1@e%4Z$# zjiLq0z3cZoo5fdA^l@in>RF@c6URrCxJ2^4)VQ1pX9(T@T}KM555EKu}|K+&%PMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N% zzXCEsGl80-F6i9x1(r)9Yq7}C>qC(qH%4C#uF$S zU!Z6LfuacoiY5{$npmJ{5`m&g1&SsUD4JZLXbOR%K>|fn3KUHxP&Bnb(KG@@(+U(# zCr~uKK+y~WMKcN%%_OuH^{m&At$?)FET47kRc~ME-&M{;ucL+vP<*N&q3Y>MU=C|W?EXhDIZg#?Ng7ARUo zplFyt(V_xHiwP7hE>N_DK+%!{MN0`3EiF*Aj6l({0!7OS6fG}Mw1PmDV z(Ry|it#3!s26hx}Xh+dTHbol?6m23kM9w1q&?mI6gv2^4KD zP_&Ie(Y69b+X)nHFHp3DK+#BnqEP}xI|>x-Bv7=oK+$NSt!TA+ed4()MekQ%v)HwI z6g^u$k-ba3S$q{md(<1{+X9bOw5Q{vXfHd8_O_#FA3KWnwWDZ1JBs$Vqv!xTiVn1+ z=pdV-g9VBX5hyxTpy)7xqQeD>ju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(C^}J~ z=p=!nlLd-S5hyxUpy)J#qA>zRrweUGyVdKPR6tt8%DHIwD4M-|L_4G2EWV1ObLx%q zZKcO5I@j@0be?nHLrsx@gqGtt)o)ai~UZCg&fua`$ie3^ZdRd_86@j8x z1&Ur1D0*F>=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuawEwxav%^{*-*t)0qe z9Uq9IDayI%qk6OWDvCa7+N<2V?$y;SzKWv0 zU5)Z%5ymR&=lCem%-(KvP#jcZ5Icy<(xZ%5GtHboN(6ip;hG_gR@ zBmzZ~3KUHyP&Bzf(G&tjg9M7E6eyZXplE7=qG<$*rWGifPM~Odfub1%ie?ljnn|E& zW`Uwv1d3)A+KPI2)pxIew92=^@9NXlzS6(D+`As!)hxb>qB*)6r!N{sb2>hX=CY$` zZaa$Rv7>0H9YyonQ8b?&Mf2NHw16E&3)&PdBv7=lK+z%sMZ*M&78NL3OrU6Sfubb@ zik1{8T1ud3X@R0;1d5gwC|XXSXnBF66$FY_6ewCrplD@*qE!TnRuw2(O=v3`(pA5w z0@6CDnq9L;(OczQw0c*w_$rFl?rM}D%QE&{w2tGWXk9ys*0ZB%eLIRau%l>0JBl{4 zqiAD0iZ-#MXt+($rUFHq2^4KEP&7iIXbXX&Ed`3U5-8eQplBO`qHP6=wi77YUZ7|P zfufNDMWY0Yb`&VuNuX$Ffuhj@MY{+T?J7{To6uIYW>>vyiAvEg<+F}!MbVArT(o;v zv-m2C_U>wwAL}z#(LRokqJ8Zs+Ru)n{p~0^z>cB=?I=3Pj-rF@C_2QBqC;(p4ihLk zT%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5-2)Zpy(8VqEiKmP7^2^ zBT#g@K+zcjMP~{Woh7st?b%gdt^(3(m9M+rD~jGLUnX*PSF`vkiq7w9lphN}&<8iAr~1&Xc{D7s#t z=mvqJ8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&ZzyD7s&0 zD>}EUetZR_b$>Y*ofkzrmXBx;bTx~wqUe#XM)|Q~V--E>_$YeJj-toyD0;$aSElTE~|UVh=~r z3FS)v)2?RmRTO>M)hIufZmgoO93Mqr+fnq59Yx>TQS_Z1Mc>;|^n)EmKiX0BlO07r z+Z6pGQ1q)n(Qg7pzY7%oAyD+EK+#_UMSlwv{UcEHuRu|)k;`_9Is}S31&ZndMO^|# z4S}K_0!2-MqMiapy#$I{0!6)rwxZ9w>XWWmDLSHjMEfF&z9=8j`ZSuwS5efz(I`LG zaIB&Mj*p^&b`*_cN71-;6pd#`(fD>0O<+gSgmx57WJl4&Hbs*N6iq5nG?_rrLiZ-^RXcIe%hTBoJsU1a| z*-^B)P0b!NFMv~Cn#Ud}~(HJZg&QM6y9 zQGP7%SVj9gK8g;oqv$|8iVm`)=wLgF4zZ)?P&aMP7o+MQK0A~fufTIicS$II#rr5#0A*->=09YxpJ6kRJ&be%xa^#VmV2o&8YP;`?((ai!yw+Iy7 zDo}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p<{R&+t5zGnrb zHL85w^@UONX!U1Z4>y{{S5fqMqfve=_*g|xI6jJ=w4>-LJBpsRqv#nsik`Kj=s7!z zp0}gu1v`pfv?+Q?py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz z=zW2r4+M%n6e#*gpy*?PqE7^hJ{2hXOrYpJTXE6ey|-6m6Xox`3>;gq|2o%jJv=t5L zQD30~(z>wRyB^r1eWhQ1enQt=J(|T=Q8aIl#`eRbXg#WCz1%Mv8bueE zheOuw(Ja1-q78dAZrm)2HgbFvZEQ!;CUz7Jx1(rNJBl{5qiAzGibmK`w1pi-TiO(D zB~Y}rK+!e=McWD#Z6{E)y+F|p0!1SQibe?(?I=*RlR(kV0!5<*igpnw+Et)vH-Vzv z1&a0%DB4q?XfJ`Hy#?k_aj-tctC_3DZq9g1mI?|4!qwFX;+NS6jfudstijET~I$ogY1c9Ox z1&U4*C^}i7=oEpXQw54n6DS%ZP;|OL(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMLqzCh6h zLR-=PJ?fKhQ7M|W+@U@oiUy3mVC&H=zKWttdo&i=DvB<1d=y=7N6{5_6kTaY(N%U7 zU2R9vHFgwTYe&&_b`)K2Q*?ts(TxH{HwhHoEKqcdK+&xNMYjnQ-7Zjchd|Mt0!4QT z6x}UQbdNyMy#ht|2^8HgQ1pO6(Srg-4+#`KEKu}_K+&T@ThYZm>YG~psvZLr{JBog>qv%&Vihi@B=yyAc{;;FyPn)8@1d9F^DEddB=wE@NS~HjJ z6mMKcK$%`8wf zi$Kw=0!4!bie?ii8X{0MyFk$#0!4EQ6wM`2G`B#}JVIO1xXt=J6_D19P$El{+KK+&=SMau~kEiX{Cf)vmQ_ZgVqv-H*F4~~kEWV1OO`46fcaEar zj*p^E?I_yJj-t)&C>mi$(H3?TZD~i*R(2F^ZAZ~IHbvVC6m2I^w7o#l4gy6Z1&T%q z6zwQbw39&5&H_cF1&VeNDB4w^Xg7hP-35yF5GdMHplC0FqP+!*_7N!BSD{-t*Ogp*~U>cYx(eYK(kqV6-9?M8y{9bTz2duAcs0WiVm}*=x{rVjI$ogY1c9Ox1&U4*C^}i7=oEpXQw54n6DS%ZP;|OL z(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMLqzCh6h0!0@J6kQ}xbg|G@bWpS2bJt4I`PJ+? zIEpSTAJHypHjA&K=!#}z#@(anO2cp;;Sfnw%HiD zXB0i>_$Yebj-nUrD0?nHOrsxfUqBjMK-V!K!TcGG2 zfueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzpy&&MqAvxCz7i<zT`TiaG>}It7aA0!3W{MGb+X9s)&8fuf!Q zMZE-yS^`DA1&aCz6!jG->L*atEl|{7plEqi9k)iYBw8XmUG>rm&-EkR3%++EFx>9Ys^y z6ip*gG_63JXwK+&86 zMRN%h%`H$gk3i8-fueZ@islpAiYDk;AGBY&UsN6enXqU3N`LC|5pDjS&El&lTDWIp z(F3Ar5ywZ-FguDCwWDY;JBk*!qi6{`ik7saXem32mbRm48JnVI1&WpvC|X{iXa#|y z6$Oe`5-3_(plB6=qE!WoRud>%U7%{;KU0@7Nxz*#7YMwN5X#yy+GS5dTC&&FW~MbYMtkD?KF6m4Ng(Ux`; zZDmK%)^-$aV@J`pb`))AN742+MLP%-jT9&vB~Y}ZK+#SDMLP==jTR`{MWAR`fuh|6 zigp($+C!jdPl2Mn1d8?+DB4G$XkUS%{RE2k7brSFpy)t>qJxCCqTxO3S5-h--sx;jd_S$q{mSNCj; zb9fY8?pe4j-ngvD7w*(qMPg}y4jARTkI&h)u!k+fuh?5itZ37x>KO& zE`g%E1&ZzwD7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRG{cFfuhF+ik=WCdQzb1 zDS@J=g|?zAd)DWzfV5VsX4h3w^iR3$f2L=%_$rEC=-F8J$S8Wz@lo`W9YrtOQS^!( zMX%aX^qL(-uiH`dh8;z3+EMhDP0`x|Mehg{y(>`kodp6EJI*NXCd=&j|N6{a46#Z#O(O-5H{cT6lKXw%TYe!M7 zSFYQmsKchHQ=q6WP}C(*)DS4@AyCv5DC#Lt)JveKB~a8`ps0^PQD1?gegZ|^0!94= ziUtT24HPIEN1$k2fuivQipCcxnm}kP`nhNQp$bTA!*YlEmnizFoQo#x)hxb>qDgx- zK0Y>zCUblgO>Rfg6m}F1vZH89JBp^VqiAY7il(unXj(gprn4!UUZ7|Ofub1&ie?fh znpvP|7J;H!1&Rg>6wM}3G(@0ic7dWf1d8SqD4I*4Xl{X`c?61v3KY#NP&A)F(fk5M z3kVb~D6|z#+^gO?u2OVBj|$Etz1mm$Hik7pZXnC8W6$FY_6ewCrplD@*qE!TnRuw2(O`vFXfuc18 ziq;e;T1%j4ZGob71d7%bC|XaTXnldA4Frld6e!wAplD-(qD=&fh6`;)i}b3mQUPf# zSG&wx%8sI~?I_yDj-qYtDB8}BqV4S{+QE*Z zk#-b~vMJh8plBz7qMZebMhg_}B2cueK+$djMY{_W?IBRKr$EtO0!4cZ6zwBWw68$X zegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXw&{nj0ullJKkk+K-^fMxg{w&{!|FB-o;;Se+ zs#oLIQ=;f-$4AjIb`%|JN6~S16di9z(Ft}GooGkVNp=*SY)8>4Hbtij6rCneG)AE4 zbb+EX1d7fSC^}1^=xl+aa|DXc6(~ASpy+&oq6-9yE)*!bNTBFqfuc(UiY^r>x=f(x za)F{N1d6T{+KP_oRe!4j(ps{bT}MXI(&e)Ms$R|Ft0=mzSL5%~qUd_ZN6`&-6y0b? z(M@&~-E2qEEp`;$YDdv+b`;%iN6{TNMRy7m-6c?Tw?NT70!8-<6x}CKbiY8+0|G@4 z3KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`|v_R1_0!7aX6g?-j6`CiT9t0;Q8S7Y%rqUaUJN71Wx6uo9g(d%{;yEYQWQN<9-957SF`vk zivH-;IO41*`qS}I^p_n)f7?;?j~zw-+EG+%<;p#ZI_xOww4kJ8G*F;u9D$;71&YQKC>md&Xaa$v z2?dHK5-6HjXe;`ySN)m_NNZ@hU-Wwv9nz@AB&}xgRTNFpYCL;R6b*8G6isPI(NuO6 zO>IZfGSfFSVfui98MVkr~Z6;8(xzJX$SgSsN1*BEJQ&HFAQFM73BU;Vkt0>yK z)mZ<+DB8yHQM9ccMcdg?w7nfgJJ?Y)(vG50b`$XvTU(GJ&GY1&Xc^D7sRh=qiDts|AX#5!#B5Zq*;DfV5^S zpJ+TLiUyS{{cBsz;;SgSvDNtW(kQyg@lkZM9Ywd;QFN;vMYq{ebh{lzci2&MryWIi z*->=2P0>99MfVC6-6v3Vzd+Fg0!0rB6g?zR^sqqDBLYQ_3KTsiQ1rM!(GvniPYM)0 zB~bLVK+!V-Mb8QpJtt7~yg<U}P&6#Y@)+z>^VjJ;rMHH)vJ=(Sd3 z)+?gub;n218+H`EX-Cmpb`-sBN6|ZW6uoOl(R+3jy>Ca+2R20?3KV@LQ1r1t(I)~$ zp9&OxCQ$UbK+zWhMPCXOeI-!zwLsA~0!7~n6n!U9^u0jQ4+2F$3Kab$Q1r7v(Jul; zzX}xnCbSj3(yFgk0covPF3VnxqE*U=x8GaM;;Sh7yVcnFswn!$@lo`z9YwX?xpI%9 z4m*lE?I^0-QPgEeQNxa+9(EKpZHjsd6!j7)Y6%qe7AWc?P}EnTsGmSlw?I*UfuaEd zMFRzj#t|qQSD!noyu zXcn8ISp|v)3lz;JP&7oKXm)|3IRuL46eyZYplEJ^qIm?0h6)tTD^N6_K+*gHMGFWN zEhtd5kU-JG0!51m6b%z7T2!EDF`=z!Q1ALX6_D0#<k1UDCs4G$K+y&QMH>nfZ6r{%u|Ux#0!70GiZ&G}+DxEmbAh4} z0!3R06m2QA6)oAjKF#%&qTkAA9hZutqpCma+NyW6_$rFF>)lxL#wgm}@lmvc9YrJU zC>mu)(T;W$?PN#M&UO@ywxehlJBoI-DcVh-Xm^34Jp_vO6e!wDplEM_qJ0F4_7y1F zPoQXjfuaKhiVhSgI!K`CV1c4T1d0w7C^}4_=x~9eBLs?$6ev1Mpy+6!t!SIx^=&F3 ztyNkToNc3MM7ei;Oz&p#RTQ1jyK&UbQFNl?qv#|%icYqp=oCAOPPL=xG&_pM*im%4 z9Ytr@QFNwF(OCjTXA2aaBT#g%K+$;uMdu3?T_8|&p+M0^0!0@K6kQ@vbg4kmWdcQ) z3lv=;P;{k0(NzLPR|^zfBT#g$K+$yqMb`^$MaT87UsnNXJyy;|$4AkU~X zQFKf1#`CvE(XEb;qTB2!y4{YVJM1XB(~hFM>?pe1j-q?)D7x2i(c*BEWV1OH+wfGxFd?*a(ooMZAZ~N zb`-s9N6~wB6uoap(Fb-EeP~C~M|Ko_Y*X}!K+&fHMV|>2eJ)V+g+S4l0!3d56n!mF z^o>B#w*p1q2^4)VQ1pX9(T@T}KM555EKu}|K+&%PMZXCY{Vq`Shd|MvLR-=6z3U5B zKw6KK&pN&lMe`R@fAww_Uqw-^Ph-QoqNt-!uH>Vr(~hFL9YtMs6gBK9>S0Gw(~hE^ zb`lqgXk3A!@dS#-7bu!QplCvY zqKO2GCKf1~M4)I=fuhL-iY6B*nnIvxkkD52Pw)DH6_D14?qpR zj-uV{DB9hQqCISi_7o`EOQ2|Pfuel`iuM&K+E1Wpe}SR{1d0w6C^|@>=wN}OLj;Nr z6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!k#dK6hbUULjN|(> zi?5>SLhmC^}D| z=zM{q3j~TT6ezk#py** zqPy%Uy4#MTd+aE>*N&q5>?pe5j-m(bD0ZPMW-h0n+oEXl>d(5~=+i8|ilTS=G&-J$qIVr1Meo^B^u8TMAJ|d!p&dmZ*-`Yd z9YvqmQS_-DMW5LeeJ)V+g+S4l0!3d56n!mF^o>B#w*p1q2^4)VQ1pX9(T@T}KM555 zEKu}|K+&%PMZXCY{Vq`Shd|Mv0!4ob6#Xqw^pDV1^j4qxbQO?RqkPu!?I@b9TJgbqyj~g2^38(P&9== z(IA1MDFuqA5-6HlXe;XITi>n%(z>|7>FnFSMjNO4v#x3SHjA&KXokLxW1fkk86BT< z(M)y}&1^@}EOr#lYDdvvJBntrqiBd7MYG#cG>1*moB~C22^7sOP&AJ~(NKY+c?F8* z6DXQrplAVsq6Gzt77{30SfFSTfudmoMT-g)EhbR3xIobo0!2#-6fGrCw6s9cGD2I? zbbaeLR6trY7C6&KQIGQBZP~uf;;SfHv2WwW=b~sO$4Al1b`-5*N71Tw6s=}Q(du>- ztzk#ensyYeWk=E4Hbv_Q6s;>zw4OlG`T|882o!B7P_&Ui(Z&Krn+OyQ7bx0PplCCJ zqRj=0MhFybAyBlXK+#qLMOzCLZ6i>$tw7Os0!7;kZAHuXt^Za5Y3*IkMJq&6`7}}2 z4t<-&S5dT6-^N5QM$yiWkD}3b6zyV1(XMtB?Pf>O?sgRIVMo!Pb`0!1eX6rCuv6^-g!U$_F&`n5c!zhe~5RnA2x^=%ekMbT+}8ymkIMPnQv zMW@?QbcP*8XWCJ8mK{ZB+fj6m9YyEbQFNXiMd#ZTT_8|&p+M0^0!0@K6kQ@vbg4km zWdcQ)3lv=;P;{k0(NzLPR|^zfBT#g$K+$yqMb`@y-5^kOqd?J30!23q6x||FbgR%- zbV}d)!4;6!6Xmmxr$*8J#eP~C~M|Ko_Y)8>2b`*VTN6}|?6n$<-(HC|UeQ8tl zl|a$g0!7~l6n!gD^qoM__X0&f2o(J&Q1p{P(a!=!zX%llDp2&BK+*34MSlns{V7oN zmq5|q0!9A_6#XkuRO^=ubBa2IwxW0Y*89IvDY~Vci{6W(FUyzDcJ^x)Uqw-mevR4R zilV0Dqo}7HMZN4OYS~fL+m50>b`|fn3KUHxP&Bnb(KG@@(+U(# zC$trH^{cN{0co98;57QRuk@>X+SLVHzh?1O6wTbPvD-UQG>hY-XjVIl2HR0In;k_% z>?oSuj-om2D4NrbqPgrSn%kym9)Y5v0!8x*6wN14G`~R60s=(~3KT6QP_(c>(INsx z!vu;J6)0LvplES{q9p{1mJ}#jN}y)27Wt{p|| z*%YlWP_%(S(S`y=8wnI`EKszGK+$l4qD=*gHWMh?T%c%#K+zTgMOz9KZ6#2&wLsA} z0!7;j6m2I^w7o#l4gy6Z1&T%qZAB~ftA9`dX^mg5(N>P4^~$~L9s4zlucBy|evSHv zQM9Y$qi8ofigvf7Xb(Gz_OzpDFFT6%wxehtJBs$Tqi8>yqWuMm4iG3hP@w1_fue&2 ziVhJdI#i(OFoB}O1&WRkC^}N0=qQ1rqXmkN5hyxVpy)V(qT>aMP7o+MQK0A~fufTI zicS&QigxZ-pP>TMI-;D5Mn}?k_lj-m_fD7w&&qKj;bE*2=dM4;$WfuhRja9f7bv?nHJj-p5GD0$D0*6;=ox{cX9bF$6DWFKpy&mGq89~QG`K+&H9MSlqt{Vh=Rk3iAC0!6j%T((oxAyCvQ zP*fKv>Jr+DKIm8fqXN>pvB3E-ibfPtjqYagRTTB=ZcOr36tx^5MZN7P>SISyUptEW z*-_MOM^S$}iU!zGG|-Nsacqjl6(|}{plE!7q6q|wCKM=|NT6t9fuczSiY65(noOW* za)F{L1d0X;6iq2mG?hTn)B;7*2oy~#P&A!D(ewgEGYAyTD6|zdyX(U$Agu$-U7?=c z?JNCb3aOd8o5fdAG`PDl{F^A6&GAt*#Ezob?I@bVj-om3D4NTTqPguTn#Yc!p>`C_ zYg06zK+*gHMGFWNEhtd5kU-JG0!51m6b%z7T2!EDF@d7R1&WpsC|XjWXeoiBr3H$X z5hz+#plCUPqU8mORuCv!QJ`ogp{;0^?)sq>kk*am8g14n`e^J0TX(bgDvDO`Ze03Z z6s_U-C|c8wqP6TOTHB7Ib?hiw*N&p~>?m5_j-n0hDB94bXd{85jRlG}5hxliP_(H) z(Pjcgn+p_;5GdM0plC~hqOAmqwiYPbMxbb0fuijMinbRh+CiXbq(IRqfubD+igpqx z+F58TTD80WR0X89Rr%cYYEd+0ITwxYZWdof(eB-iuYZW5JsclJd)iU7mmNiW+flTS z9Yy=vQM8{OMf=-PbbuX22ig=JBv5p)K+z!rMTZI$9VSq8xIobn0!2p(6dff{bhJRx zF#<)$3KShDP;|UN(Fp=YCkhmuBv5p+K+!1zMW+fBohDE;MrbSAwYxs>$4b%u<#Dv# zqUeuCHBRqt7GFit+1-sfe~zMa93MsJ+EH|#9YyEcQFMVFMHkvpbdeoJ7u!*Ei5*3k z+7w+TP;|LK(G>zkR|*teB~Wy=K+!b?r!yj-v1EDEi)}=m&wK9|ekj5-9pvpy(HYqF)7yeiJDAU7+X>fucVJ zivAKP`dgsrAAzEO1&V6@bJ|d6DC*O{(fBKh`Z_*}`q@#`ZAVdmJBkL_Q8dtwqH*jf8rP1Z@$4uX z-==5+fuacoiY5{$npmJ{5`m&g1&SsUD4JZLXbOR%K>|fn3KUHxP&Bnb(KG@@(+U(# zCr~uKK+y~WMKcN%%_LAXvp~@-LR(R*e|@G3Nb7-K6`bDv+gJMcmJe^U_HPznMbYg2 z8_WL_MRPblisrPVXf8X7=C-3~9y^ML+EFyG9YyomQ8d3DMGM#zEhtd5kU-JG0!51m z6b%z7T2!EDF@d7R1&WpsC|XjWXeoiBr3H$X5hz+#plCUPqU8mORuCv!QJ`ogfufZK zidGRQT2*K(nyr6*R0X89Y&jPViK1`ISgn7v_$rFl>fbn_R^GsnTG!f+kD_(#C|cK! zqV?=3THlVM4eTh|(2k;w>?qpUj-pL$iiQgmZ7NW-nLyFz0!1SPinb6a+ESosD}kb| z1&X#2DB4z_Xgh(T?FEW<5GWccP&7)QXh(sfodk+@7AP7mP_&Cc(XK*U(Hi~hw^Tq{ zXOxG|){LUQ|d6DB7!kL z=)C@o$*OM$G4@<^zT>0l0y~N>w4>-EJBlv0qv#SliY~RI=rTKsF1MrT3Y(%U1&Xc` zD7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&Zzx zD7ssq=pKQhdj*Q_6WWT->0e*00@9kWoPN%YqASWZ+Wq~T#aB`EaR0_;%_w@r@lo`s z9Yv4XQS`VSMNimK^rRg{PuWrQv>ipy*irPXP0@1#Mb8Tqy&zEZqCnA00!1$i6ulx) z^r}G7YXU{D3lzN}Q1qri(OUvVZwnN?BT)3NK+$^wMehp~eIQWup+M0`0!1GSZAB0E zuOD6kX^mUXMGr;Mh2`G$C;gknS5fpu|HkFLqUcMJF6OgR?~8PF`gilVs&H0JIXMRPko zisrGSXs8`U^V(4~pB+W>+flTD9YqV;QM8a9MGM;$Eh11fOrU5{fuh9(iWV0rT0)>` zNr9rJ1d5gxC|X9KXjy@x|n znqxqHy$VRHqg)TPZfgME~+EKKT9Yq`4 zQM8F2MZ@hV+SHDs&1{M`7bqGbP_%_W(Ut;5TL~0xEl{+LK+(1WMcWA!Z7)!?gFw+p zfud0YMLP-e5mL+vO!%#NbNZHkT% zC^}N0=qQ1rqXmkN5hyxVpy)V(qT>aMP7o+MQK0A~fufTIicS$II#rSn zU2I3uC3X~DYDdv!b`)K1N6{5_6kTaY(N%U7U2RizjX=@00!7ye6kRV+bb~LubK+&B7MRy4l-7Qdbk3iAA0!8-;6x}aS^ngIogF;); z`2*^+R6ttOm9O5vAc~$W=c0!OG>fmI=&=Ef6(@+I#~mLHKFW3~lC{Xm0K+($rMXv}Hy(&=jnn2O(0!42K6ul`>^p-%;+X6-J z2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&nb21B$bkAz6_D1mfmI=<5NElO~FyZyX;*-`Y|1ogGEr+fnp`9YsIdQS_4?ML*k7^ot!uzuFZ2 zCQ$UdK+zupMSltu{UuQJw?NT90!9A{6x9aivYnz1fuc@r06q6zFMn$V7-iR>tv*p8w}>?oSlrf4#OqR9n{rVuC^Bv3S^K+#kJ zMN+td^q5%WjSNexkc)I2s*et$^qM-vDQ%oL3^Ey6?=Ch+{emja5u%l=} zJBk*vqiA6}iWae>XqX*Ei`o<|CQ!7vK+zHcMN0}4EhSL2v_R1^0!7OT6fGxEw7fvk z3Iatd3KXp*P_(i@(JBH(s|pmYCQ!7xK+zfkMQaKattC*jw$N5I_rUrR6_D1<1|5<-^-P1DnNHQFOq- z#+6e=(SeSSqJ!)xI@pe)L+mIz)Q+OV>?k_ij-n&%C_2)PqN8kzjut37Mxf|efuiFC zijEg3Izgc5M1i7{1d2`;C^|);=v0BC(*%mf2o#+zP;`bs(U}58X9*OYEl_lhK+(AZ zMdt|=oiDT%?KiOgTm_`{Nj1CnkD_nOxL{zj_^S1*b#_hNYm(_YYTcJs582kbA1~m# zzpNgy?b+S8x|-|LU4D#u|L#@$)@tK+pVD2cP1ybBfLd+R?kUHu)dqEMIex7+P50Fk z)@n0!|2T22HcR(>lhtZNy7!x+R-3E);VEmidAoa0Q>!i5z3Oze+OY1^W~kMc=ze>q zT5Xx`sb{U#R_NY(wpwkK?rUeS)z;|#dCppGo$dwZsns^WkEB+jXD5XstG?``yKBwb9+vE>)}T-o5QIwc6g@*DqJA?ce?D3boq7-3zT; zs~z5b(5kiC(cO=)UaKA7-Mv<=c5?Tc>(pvvy3bs%Ry(Wv{S9ih^SYex&6#s%Ar#u3wP|)Jv^VSTt3#m!S)Hy8g$`!jFgFxBob~SfQ0SYiayN!T zN3$-xITSjU^}vEq=y=vww}nC{vKrnV3Z0BkS?u2b;rO$6xho(X|7WSY2Ey?!_qeMd z9KUI~yAHzf_wRRCLO5Pwg}WBQ@rzfwt05d;vD#e^;kf;4_I1N?`{&5(hvW9|NjD0| z?H>fr3CHbUbZs7v+ds+KIvlruQ?Xq*ZvQA=$8g;KRkN<)xc#$KJ;QPPcZK?f;kf;*?ecKkepvFsaNK^{ZB;mKKd!VU9Jil0Sr?Am4-9Mw$L%}5H-_W( zExXT!`f} ztKH)M?1kItC3m>D7H+Gt#?Cog;|Uw>GzNyb9{h#TMhA`2b_qHL!#!6f zd`4!uG%vGS=8#HdoQhB=sctAO?HrdvA+KV{%WRu=c3PXXUgg|xQZGpfh5QyFE6L@; zX=%YLgx!p0guE19KP@dIEj_KZ`<3;u-|J(oUsxAFgdhc?t?1j#A|4$14otY5|yC?U$cI`B2l07vq zdvxLC?82!dv!@O#9GO3C^3;N&{E zj+;2HXx#MtQ1;k@iTT-i6Y^(dHFB6=vr*9adO0ZPd7e z?4p8#2_whmjhj@MJ!a&{VR=(0X6NP%Yc{NDPSf0Bxj7aayV!VA!KD1g`FSJ8HO|dx z(yXz)xQTo5f4nGr+@z5crj5$ao|rds?6^t)zh8{PnT4g_6Jy3^cbYnC+PFytT?(e= zH!gl(%qW_gc$Wn4kpWW+#=G}k z)TP@ncQHqHDVR91V3KQw&)t^!35s5`u$drr@g9dldf^c*%Kc(!Hp;%8fQ zDSozPYrSUk*0fHXoYOpbS+_2Fom}_Iojy&m;QsB25-A7r?e>k^;(gd zmHfI*i+|lNrQW12U{g+LS^QdU5|?S(q{4AyCgqQ+<=*FsU#^QTS8jLSihG9NX1C(s zN3OdtiPvxAUTxSgcXqR;!-BVv>wYm#=+0Z~q_@_&Z+ElOKtmJZZDLx~&3%``R;5x$ul)8!fzxspOHGjmkF~RS~z5m^><^HUfx&m}L znwMNOcV!2!Ui^DORZhuorA_h0&UIizeY#yZtW(#4iSyj`sNa$Es^_}?$C;rC1(U|q zO8oDCn941=Af3eqUG6$d`~q+)1{3hKKWE(%XOFi(8i`lU(VK8mbxArGUncuAnRum6 zB^RzMS9~+QtXM+g7awLfGP+qxoSNIZ_zmZl(1Qw6a!V|_-;*u~K8hu{8-w6&mcYt& zvVxYw3rno!cIS#JA;xv*eoMi5JY!c<;)bZ?igve6x+uBsvhZwf$@{0&)!oXS{(t$g zSRcwuZsF~+aeW6&t+Xz=X594_{05rxJ1KFNTLLY&lr)DSIHklCS9xw{y<@q;+Z4Yu z+?A*IMak_S8d{WGo}WQbL|v&s=cYi|q}$WAU}1gb8=Mr580T zzJA<0f>$q51sJ>(8)@y{e+9*VE=sO&KDO8`lHQy-9O&T_1^Jf)XFHf{#?)iqCe}fZk%sCEz-C?;*Xc__}mgLGUY-*l;&b z?zIwcJnwhmA`STvb)1ga%@&D*xj3M@2-|n7Tjx&o;*=i< zPi!*L-9c|Ss&I0{(UWU69#gCFxlL;|cJ~O|k8~HH@#u;9g@t)z@*7XcpERauZ2KIS zg1aw`?OJ!sZhVTy6-;Ve=;nD`*<+eOz*nu;hMVZU8(X#og5FVwGG&f%4*yqzTl+hW+P)Q};g;zr)~9UGeXlKV`+1p=@_LFE75~xls%|UcmJJoPvKC~>`eFg-yVSTWDm4EWv0*b<|kbrKL3r^x4F+! zbZX;bo;_|2g|pqWe(T2ln)K_`tA8lDOtfFB7fUG{DIcy7uH;n?R|!`QR|{7U*GxJ+ z+{7N1|JPIL6bb!&s`QIJd*D{;$*!wBKH-&QpEkCm`;@W$zU^2+NB5bPP?Gy> zN^Lv3SE{dW*O$GX`^<0R=sw?@ICj=?fR00SbdRPJFCVX?`>bqY&(U$7j*E0$spFIO z=@|FxY|(L-`>omjT*u$sZ@{*FpROG%x!;Q&>*(0VU3S~ubiCL-Z+nc654v}y?Z2uq2bbPLIuwU2l->Sh*s}>x)x=*g#>z}9N&8G!>sg66{ zJJw$Qsg4!v2D^@qmz){waXLQat^j-eCv^PgtYH79W0S_gK3m5kcSYIjU#sH_xxs!@ z$58WNXXx17U7_~+gLGWr(A&OS#}C^E`*R&DyDQ#aeuj>hbqMz5I?d{nu1m20 z&@rcbu-of6y=SoJ>bSXgu;0=#sb8?ObnJO5?x5q0ykO7Q@g)b{-XCx47#SVxGCKAi8|({oTr@t| z_v!f2gkT@iv3fzU8|XMN zoM4yJvG29PzEHbP!ou%FlQmq&tqO2^iZ1-qM$SFa29Ejn&nAM6iwj6E6bN;(dBI@p)$xMWkXSL%4+ z*_N_X;@n*1h>6pGF z*j02K_)f5g>A38@V6WEkvz@{IUdOt-f}N}5_&veCLdOjs2YZW-zwZmSw?83H2|!Ct82_JhIRqhscwU{}*|@K?dk)A61o!G1)?gYHXL=HUk&&paCJW;#yzG1xP8 zeCk-RU)J%2`|_5Z@BbPc&-pDl_R(?PAHlv|#~ptL`(qvBCxcx>$MgRU_DCItWnb{_^qd);-+6VG*Y!QEvH+0mYswF!qRyHL(OZ&$y)J-b{3 z+<%KJyM_zAft8l2dUdIl+-da7+iw?Wj;~Z=D z>)O*J?!VHPZ*QsJuf2b`e9yV(oxREKka#NJIvi@ta7X)f?a7X%-VLDv?)7T9Xn)Sj zxc}_!+1s^W6U*+|&}8T340}dTygfUo^y_`&F5h-u$sKvUQV-W!=QJtE&TW;`vUN^V z`=ph7(4CW8>i;cUy4JdRPSc!P_B1>;r(56d!PlyTHyn14(s;X8mUm4oKlrm*-#u2W z7;3#Kt8Z4HZ6~(n>^>364K@6Gf2h`}KmI+{`S++7>zCFm+I!oHP}seEz_t?y<8_9Y z8+&i~df?=Q6T!^!q9 zRU}6uXZrSyQ&Icdnd<2~?oV?wHx#L_S<}s?p-2PG8g4doe8mZG>E?jgX795puCMLN3up$feo{xl9`&!?Y1HTpJ;I+6Wn;jgXPr2pOe~kbG@~ zjMhfT7;S`%)kerTZG?>1M#$ybfskI__wM>n-Q;d)BE174gWN4tWJ1*Bn2^c7eZyr! z$P}F_AyYLaq)<~riZmr;nx=$I*OZVeG$mw)ri9GYl#p4P2)R-lA+xm+a+NkhuGU7# z9BqVLqm7VjwGnciHbUlVBV?X7Lgs5D#f}9*_KXrlKhTItlIbqK~6E!&|8h5i>8FUq$wdUYf8vg zO$m8LQ$k+Vl#tgnC1jf>LSENK$Q#-Sc~cu9+qDt$mNr6mXd~opZG^m|jgWV>5%Qik zLf+R#$WCp9e4vex5491pOB*4(wGpyM8zCQQBjjUkgzVKu$Ubd^?AH#2Jm;O~uK(0z zcSkq!d?4f@yHD~-)a00u&wcwQ{)CW&I#oix(3FrbH6`Sbri2{Ul#s79CFE;O2|1!E zA>U|9$hVpZ`A!=l-)ke}s5U}=&_>9Q+6ehc8zINE5%RM(LVnRk$gkQ6Ij)V6-?S0( zyEa1p&_>7!ZG`-(jgY^z5%RY-LQZNU{Hu+SQ`&)$PrV{{{iklV`yQVqgv5Td z+YtA~E~8^VQ4|UL_9GsNpG)(@I$J+cl+4yo6h+zkiJ}y?exfLqt)D20vGo&0X>9#O zQ94^cQIx^fPZVXc`H7+|0zXj{C-4(RWeEI4QCR{%QB;n=PZX6W@DoK92>e7*MFKxj zREfY(6jdhh6Gc@B{6tYz0zXkyjlfS7RVVNhMKuWgL{UuwKT&iVfuAU9!l zgV|Cvge^tqv!&<)wiFFzqv%2ciY_9c=wbqjE+L@kQUZ!DBcNy)0Y$?JD9R(CXaoU8 zBMB%PMLldR(O3eC#t~37o`9mu2`HLCK+!}3iY5^PMSa6wcLyZ4(alId zDatWY1@7B7oG(*U820T)6cdVyIA4mUv88A_TZ*n=OVJFr6wPEy(JZzUUCEZB*=#Ag zijAVH2`HLFK+!b>6kSU|(RBnA%_X2{9sx!32`IXrfT9}+D7uk=qMHaPx|x8YTL>sx zKtR#01QgvyK+!@1iWU)2bUOh>cMwptm=GwM68082AhE05BkjmkDO#I&oE46mFH^KE z?AwpHCKTPx`BHQbTZ-;wOVM(+6y3*`qWjrW^Z;9m9%M_=3bqtI#75Cd0*Y1UXIW6_}#u!%_2PinfG(`w{7cqL(;die6?* z(N?w;y~38FSJ_hZ8e59Cv8CvBwiLa=mZCS=DB4ay(OU!*?I57&Z32qkA)x480*c-v zpy+)9igprE^Z@}y9}-Zsi-4lt1QhKdpy(q4iasWwXfFXp`v@r7Pe9Qp1QZ=0py*RV zpy{|VTecK^$Cje+*-~_rjiMh2DEg6rqMryTIz~Xz&jb|xLO{{41QZ=7py)ROihd`c z=nn#lP7qM^Cjmu&5m59u0YxVXDEfzhqJIe}Iz>QHD5>~SetP2TQDFj#k_dsKgJJJ7 z2PC%NzQ5!PDLQPoMP5?We3_zXl5c-SLqbss=Sxv4TZ&?ADN18YQ94_SGT2g-$(Eul zwiLzLQdEYGqOt@Ol_Q|2JOM=&2q>yZKv5+EiYgOORE2<|sst2OBcP}{0Yx%_Ck2o6_t|Yx z{iLY*GDVG&eETat5{epgz7#cKOHnpkigMUel*^W)rfex{#+IVyY$PrX|ot5N$=YYiQdv_uYrO2~K`u&ok=F1eFm*m@D5tC3f zkn^Qz5L=1{v!!SVTZ+zSOVI^vDH_U_q6^tlbP-#ME@q?X5(0`YC7|ds0*ZzaP&Ax? zqC5hMMi5Xml7OO71Qg{HP&Ar=qA>&%jU}LH905h+2`IXpfT9Tm6ipRv-0YwW5C|X27(d`5j-9bRnVgicpB%tUn0*aOp0!2kh-gE~f z*492nG);;&+ilU(q^S8aMfWE8OY2L~a?Y2c``A)+KU<0(U`x@1Y$;m7mZFE)QnZpS zMXT6Sw3>~ghY2Wpgn*(o1Qb0=K+$6a6s;woXdMAXj}uU|o`9k!2q@Y>K+%%~6g@>i z(bEJJZ6u&*69Glf5K#0i0Y%RdQ1muf1{gDpjGvZZJ{TZ-OdOVJKCiryxm z=p6!z-X);uJpzi}C!lC20Yx7WQ1l@IMY{+n+D$;w9s-I!BB1DF0*dw$P_&PLqWuIE zeL_Id0RoCXC7|dt0*XE-py(hWQ1nugm(ok_4 zuQ^|ejQ{`wrxL-PP#6qV8@6 z?AuPm1QaC^P~;I%6d|C?XMQ0LFRF8n7`UDg;AfV_h zLZB$c^KNrMVz1k`3#EF&BmMX7wy2>OHD9JE+w<+O=u9Ze;e08|WlK?0wiGpEOHp&S z6t!SWQA@TIwPH(AYqk`%VWX%m0YzsMP}GiqqV@z7okKuT2Lg&Z5>V8MfTGR>6m=n> zs4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&z0BF9AjU2q@}LK+(B`Kv84Q+wFkF=Gk4L zCQ|gZ-4+e-qUOsK4fcHdD_#?dhH$ ziY{ZLXcz%S!wD$LBcNym0YxJTC>ljTQ9c1hqX{S)LqO430*b~FP&A%^qRR;=nm|C& zL;{K?5l~b>K+$9Zilz`yG?jp&LIR442!W!3o>#TGQ*_*Y&thbd6n$x*$e!j!&6g>f z>G}3o1Sb^D;(RH(k}XBE*-~^BTZ*n`OVJ#*6kWrXqHEbwbRAoY=CV;VkAR~21QcCQ zK+z2Z6x~Qb(M<#t-Aq8yEd&%TAfV`00*Y=UplBfhMT-b1x}AWcI|wLROhD0{1Qgvx zK+zHcik1>kw2XkFy9t4!D?D$w0}>l#w?#9gsH=TMyT^-~FH>~C=i6T~olx`u=S$Ip zY$;m7mZFE)QnZpSMXT6Sw3;nN53{A{5w;YqVWa3#0*W3ZplB@tMe7JCdYpiw^#l|> zK|s+40*am_py(+Aik>E*Xd?kdn+Pa+hJd1H2`GAwfTHIKD0+c_q8AA$+Dt&v76OW1 zA_R(-d)~tiNUXIfx=)Ha+IZQEnlDrIn&;bJQJzq=jq|1Gb+#0}!Iq*o*;2HfEk$p! zrDz9Rir!{R(K~D@dY6r&_XsF@pMavB1QdNhK+%T;6zw9QXg2{xdk84{h=8Jx2`Ji2 zK+!$|iuMyw^a%k)2M8$olz^ho2q^lTfTDv06n#NJ(U$}i9U=sZUh%x64oGaieb(_+ zDQarBMTfnp`7%Y{c)tA=_X$Pca=sLO$Cje+*-~_rEk!@DrRYbt6#c}OqGN0+`k5_7 zzpzpCD*;8v2`KuFfTG_CDEfndq7wuZ{YgO4Uj!8WO+e8}0*d}2py*!$icS$w6pH9! zJBq>t6eST*2q>ycK+zcl6rD*xQ9S~R>Jw1ZfPkX2 z2qHX3PP=#ABoZ}Wrl@Jezq^wZHRF6KYR;CT z7HlbM$(Ev4Y$qO;jj)Q*j!_5>82LqJgn0*X2kP}GTlqRs>qbs?ar zD*;8_2q@}KKv53@ih2@I)Qf~MVGLp=u);6 zUB;H8VQeWH&X%G)Hi||NP&AT&qEQ4CfTC#x6ip|f=n6uhXh_71baje`+E+l%m!dc9 zwrEBqYQ9X-?1*pw#7{!eRh%zHSF@#P4qJ+@VN21qY$>{qEk$$LQZ$b(Mf2HGbUhnI zHxN*CBLPJ>5m0n90Y$eEP_%%6qFV_lx{ZLMg#;8WBB1DY0*dY+plC4xMRyWVbQb|d zO9&`hN zpNL8*dWiF-XeC>UR2%=xG9qHWE;@iGZSK2q=1%fTHIJD0-fNq8A7#dXa#l%>)!}A)x3b z0*YQHplB-rMXwM7MGr*0MGi`V2MH+pf`Fng2`D;5K+$0WioPPC=xait zXj{bl$N`D1v=3shOVKKOq<P`@a1XhY3YxIA4m&vZbgTTZ+oFrKkd1iYl_Ds1jR>Dzl}i z3R{Y*vQboxfTHRI6xAT0s3rkLrx8$8i-4lq1QeZ4Kv5k6is}+jbOr%MXA)3UkAR~3 z1QazOpy(_DiW(A7)QEth#sm~KA)qLmfTA2ipeWP#MmQj`H2c2mEI)XpKhSQNa{Z|J zGDR(X-~Nfrgrb(5FGa1`Qq-C)MQzwp)RrwpXS1cK9b1apv!&=9wiI<>qo^YRMV$yJ z>P$dU7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OFol8K`00N56 zBcNy?0Y!rdC>l&a(GWtQsG0AraX@0ZcJtF*iq_jW-;bIvQ*@E<+dr|IP;@cpOVK54 zDY}#`MVGOqXc$|HhO?z8k1a(b*itl-Ek&c)D9R_GXfy#uV+bf3OF+>$0*b~HP;@x~ zMH2`pnn*y=Bm#;G2q>CNK+zNeil!1!R7gNk5dlTh2q>CPK+zQh6wM%@XeI$gvj~Br zp}zN{0}@+rcZDvLqRn<&bfq6PU#4h|@7q7on^1HO=S$JGY$>{qEk$$LQZ$b(Mf2HG zbUj;&ZeUB%jch5piH)M02`IXSfT9Hi6x~Wd(QO12EhM055dlTF6Hs&q0Y!@mD7uq? zqPqwvT0%h4QUZ#W5m0nD0Y&!^P;@T=Mau~&x{rXO`w1v|fDkCU%J-T(AhDtLuweUHnWDFR z-~Ng4grXgsFGX*&rRW{D6urxqqW9QR^gdgPcCw}D1GW@>$d;mAY!vM#plA;PMIRAR z^f3WNdkHAoM?lej0*XE%py&VrMV}H-^cev~pA%4Ykbt5u2q^lJfTBYL6dfj@=qmz> zz9yjP2mwXk5K#0jAyD+D?`?HJV(uR~2t~F_QBV7b_MIO!U#93s-?x8aKB4F*&X=NN zY$^JgEk(burRZ0-6dh+v(Qj-i`kgIBf3T(K1RF(v5>WIP0Y!fkP;`=jqJIb|`j>#B zQv?)+lJ$@qMPUMpk_agB2q=mWP~;O(luSTTlz^fX0*X=zD2fqKltw^NIsru)1QcZw z0!2rCFZoiZ$iD6x`9X?)v4{Ox$x-uVipnMX^@d4NdCr%j3T!E=$d;l?Y$>YDmZB^^EAfV_>0*dMpP*k6Q zq6P#Mokc)VLjsB#5m3~afTAV@6lD`oltVyKE&)YN2`Fkt2o#k`_WC*?v1jbwb=ltugoo)op=d?{+nmZG!SQq+zuMeW&AbPijJIPtXTKLU#S6Hs(60Yw7{C_0aT zqJaby4I-duFabqF2q-$AfT9ZsC>lx#6tztD?r=b2-`M@4R#H^K#)ZjI^JR)IP4=H2 zDMgoYz7!2(OVMz)6y>p{Xark|MzW=76kCe&*-|u`Ek$G4C>l#Z(KrH%#uHFCJK+z-uiV6rQnoK~^6atE-5>Qk~Kv59^Mbii zqS*u#T}22KU7YOgbwFaP?E8x@k)k{7Bihx;QS)Vru1og+%$K6MoG(T5*itl~Ek)O} zrRWB>6y3;{qMO)KbTeCuZedH&0yc_nC7|dw0*V$AP_&4EqT2~5x`TkC#RL@HNkGwE z1QabHplB%pMau{%x|@Kadk84Hmw=+>1QgvzK+*jK6g@yd(SrmOtstQ2Awr<&nq;r$ zXs4*7-J!l#iV71C*pj2>%M?A5>~|O|MQb=;iXLT4(PL~WTFaKAb!;hmoGnG`*;4cb zTZ%TYrRYgEik>2%=xG9qHWE;@iGZSK2q=1%fTHIJD0-fNq8A7#dXa#l%>)!}A)x3b z0*YQHplB-rMXwN0^eO>GuMtqRjew%p2`GAlfTA}EfuhyP-Y5qo=KevUP~>4Ly3uZn zwkJo;mnnKD*`GgNir(dXDSD4BMennvXeV2WK444Hhioa@#g?MoY$@8qmZFc?DEgRy zqP+wZ?IWOQKLJIb5Kwf0fTB+cDEf?mqR$B^I!Hj#7X%c2NkGvd0*Ve3Q1lf6MPCz8 zbcBGSZwM&*mVlz~2q^lVfTE*>K+%q5?=c4?w%tCWy)8xU?P329$x-uVihfS^-<}{v zzi_@3{mPc2<7_GVjV(pLv!&<{wiKOUOVOWfDf){oMSrtVbdrFge+Vf0mw=*E1Qdm$ zdf1MlFabqL1QdA$6h#Oq@(CzPCZH%vKv4<-MX3Z7#Rw=$BcLdqfT9cniZTf($|9gB zPC!u^LZIlUWbc>*68qe4evU~|l6^!g8;zPTQ&chPmno2Jd;>pMatU1QeY` zKv6>iiW(76)R=&xCIl2^6Ht^xKv6CMMNJ7PYDPd&a{`K55Kz>T5GX1i^;$Y0v3B-I zzd|&4q#w3N`mLf-^JR+8j`|l&k)n2-FGcOyQgjYmiaM~Rs3Tj7IQ zMS}?_8bUzP`2-YQKtRz@0*Wpqpy(n3iY_JuirPfI*$znTGdCk`rRap`#wF3H`7%Yr zqyBw`Qk2K}QZ#}sMI+f#G>R=n`D`f~&6c7uY$+PcmZEWNDH_j4(d7gbO(39XA^}B{ z2q-EbplC7yMN0*Yo6P;?am zMOPD0G>3qqYY2g&%c9<^4oGaieGnTaMIG(K+qKcC`7%ZGqy8cH56vdN0&+d)OVJH% zDY}s@MK`gf=w`MQ-NKfl1#Bt0l`TcLv88As8%2u_dN2q;=j z2o%kYdMVSLq7`mN=1I{rc31o1Xw-a}qQ|0sgBen^mh+`(9b1YXXG_s~wiG?VmZA-8 zDSDDEMNhG%=xMeTZDgZp69Glf5K#0i0Y%RdQ1m zrD%rT7QG#fnlDrIe$+3RB}F?qUy43pOVNjHDcZ%BqTOsM+QXKjkJwW5FTh2E2*b#_~HEE+Xmrs#Oo z-!xl_e&c*8`kgIBf3T(K1Y3&!WJ}RsY$^JiEk!5UQuGg7ivDGz=oA4(p%guAM^Tu7 zq9g)}JOYX$1QhuM6eSZ-6eXZ2g@B?|0*Yb;6r~YRlukfV1_4Ex1QcZvP!uPis0;x` zWeF%MM?g_|LZIlEsJGt%iQQnIb^MjvA|q8HC2GD*QI!<`@2jP#D(6d4HMSI0XG>8H zwiMN5OVMd;DXPVmqS|aJI-M;=b=WAXOF+>X1QeY~Kv6vcis}sNBS-8BU;;(sQEHQ=cM?Zu9cz=oG(Qk*;3SrEk&K#Qq+YlMP1oa)Qv4g z-PuyqgDpip*(mBoKv8c3iuw>x)R%ywegqWtC!pwD0*VF@P;?#vMFR;a8bmJU z5KweJ0Yw)OP&AZ)q6-Nqx`=?HiwP*Ygn*(;2`IXZ5GZPw;*EAdVwV`4_EL1vZi|Mc zM9r5e8kyqXFjtC3alRDgv!!S>TZ+c8rD!Z$ipH^}XgphrE@w;81hy1SWTR*j0YwD_ z6ip_eXbJ&EQwb<4B%r8>fTC#x6ip|f=n4XgW)M&`lYpXG1QcCKK+$XhimoD{=xPFr z<`7VH4FN^h5>Rv<0Y!5Ofug(=Z=C}YOR~E{Bc!O2k(!qhHD9La#uWeE`BHQf=S$Je zY$>{hEkz61Qgka@if&^|(L%NqEn-X2?QAK!gN>ra1Qgv#K+#&=n1wIZD32$lWZw^iY-M? zv!!SwTZ%TZrRW*96g|sE(Q^b8Jx@T<3j`FsNI=nM0*bZ}Q1lW3MK2Rjw3UFOR|qJ2 zm4Kqx2q@Y{K+)?26um(}(VGMmZ6~1UEdq*m5K#0s0Y&c+Q1mV#P_#D1Ywdu<`nwrf zCqWIR0Y#q^P;`)hqAv(2`jUX6Lj)8ZCZOmm0*bySpy&tzMc)um^eq8J-w{ys zJpn~W2`Ku3fTAA>DEf(jqGJRU{Y*g7FN8qR&J^!z2gH39&B6IViqh?__OB^X^JR+u zNbw(7AVnuQUyA-@OVM9!Df*i&MJL%(^bcE#{$)$iDYg`aQuVl9io$FZB@s~M5l|E% zpvWhnD4BqwC;>$&1QewbP!uDeD2;%kbOMSp2q?-VpeT!gqBsFXWe6xLOF&UM0*cBL zP*j0{qKX6*RU!n6eoOJTIUuoj?dIoqDH>&?a%$9knWE~c{#Un2Q4P+QqMB?eI*lzw zwb)Wrn=M7Bv!$pGTZ-zkrRWT{6rIUNQ9S~R>Jw1ZfPkX22q8(YED2=3j&H-5>V8NfTGp}6ty9ss4W3SXA@A=ju0rSn(DcN(xo@^=V z#g?MpY$@u)Mp0h^iuw^y)SrN&a|tLKKtR!X1QZPQMS}?_8bUzP`2-YQKtRz@ z0*Wpqpy(n3iY_Lg=n?{oE+wGoG6IT*5l}RofTBD?pr}KtH^2djZL*u6j#5-E@qjHg zYQ9X-=v05oVksKK`BF5NEk)zlQZ$||MVGUsXaZY`CbFey5?hK2*itl^jiM<86ip?d zsE~l7A_9u05l}RpfTAl1D4Ib)(M$r0W)V_dV2`IXXfTF7jD4Ih+(KQ4VT}wdG zbp#a6C7@^?0Y&o(D7u~yC>oXOEpb3%*>>}jFGZQ|Zc^li)TsF~MYp8-&)y|P3pihj zZe>f+ZEPu8$d;l-Y$>{(Ek$>*rD!o*itc1f(Oqm5Eg_(2DFH>x2q?OnfTDW{D7u$` zqU8h>-A6#t{R9*}KtR!h1Qe|xpy(k2idGU(w2FYD)dUnhOhC~i1Qe|ypy*KoiXJ1N zXe}X7bW^H#zyXPMb2DnZvP)v{9r6|mnq9nEyd2A_)uuS*yKvA54qA~;&l_j94905h;2`H*SKv6{k ziYgIMRGEOHDg+c&B?O92qaeA#E?bJuU`x@NY$>Y8mZJJ>DQdt*(OCo(H6);@5dlSw2`FkpKv6aUML7f% zXfTFVrC~8MQQF{W4&LNo(@JN4$jgGOX`7%XaV}6AdQq+y}rKmewih8i6s3%*Bda(UMK=;qbQ2*^G$!U<XG_rwY$dXIpj_X#N4NkGvD1QdNpK+!HjpyEk&QOrRV@#iaupa(PwNa`kXCA2ia2e z1zU=~WTWU10Y!%iDEf+kqOS=kIzm9vHv|-YOF+?g1QdNwK+#bGihdxV=tlyIej=dg z7y(5;6HxRE0Y$$OP;{JtqTdK8`kjEHKL{u~K?oFm6!Qi;AhCRd^RX0-v=488#-irS z6#WzP3)e}}znm{cr`S>yO4B2EDGIZtD2Xja9$ShcY$@{DQk2Y=q9_|hDFhUy5>ON) zpeT)iqI3d^G6*QjB%mmZfTB17MP&#mDoa37IRc8x6HruvfTD^76jdUis4@XXRR}1m zN~;q!cZ2FN@Sni<&P}bb6Zq{CX*>!}(HFmn}tS zu%+lswiMN4OHqBc6g6N=(OGOMYRHzNMr;%{CZMPZ0Y%va6y*?5luJNSQv!;b5m3~e zfT9)z6tyIvs1*T4tqCY7IjIBnlDq-Bh5dxL5g~Ez7+LhOHpsO6!l?CQD3$c^ zf3_5z%a)=6Y$-aAjiP}B6b&MvXfOdqLkK83pMatZ2q+p#K+%N+6kS9>(ZvK5T|z+7 zr34gRMnKUp0*ZzcP?SeN(Fg*HMiNjoih!bg0*XcxP&9@RDC(Bx)qT<_O0%zkbeE!A z+{+?k)1v0f6irC;yFD#M6FFasCb6ZcfGtIn*-|uxEk#q=QdG#6q9V2wO=C;ZbT*2v zAfRXl0Yx(jD4In;(Uk-g%_gAeDguhGCZK2z0Y%pkP;@N;Mb{BfG?##)c?1;AC!pwh z0*Y=Rpy);dif$sH=w!`qBre^>DIKU`7%Yfr}?*R zlA=2}Uy2s9rRYw!6y3#^q9tr8TFRE9Wo#+Bn=M86u%+l;Hj0)LP;?&wMfVd>^Z)@x z4-!zcf`Foj2q;=fK+!4!idGX)^e_QMj}TC_hJd0+2`GAufTFbo6s;qm=y3vy))P?l z1OY`G2q=1z5GY!h=5265VxQPoKo&{SQ2U7XR9e)0nWAUX{12X$qGvf@ik@Rj(erF6 zdVwuPFS4a*Gh2$bu%+lFwiLb0mZGg}6um+~(W?X$y+%OMHUf%XC!pvJ0*c-wplCY* zMQ;&Mw1a@6w+SeEhk&AY2`GAxfTH&aDB4Lt(FX(+eMmsjE&_^n6Hv5=fTE8GfufCR z-tP`btiHk7Bt_xG1GcoN`7%YHr1_OzkfH;eFGZiSrRX!Z6n)N?qJwNH`hqP*U$Uj> z5L=24v!&=OHj2I`py&tzMc)um^eq8J-w{ysJpn~W2`Ku3fTAA>DEf(jqGJRU{Y*g7 zF9a0*NRJSp*ct2`DNeEeI%T zNkCC60*YD_P}GKiqP7GSolQVdI|7Q@6Hs&x0Yx1MDC$T+Q6~b5IulUTg@B^21Qc~6 z1d8gUd)pn5*iO4Gs+%4>(mx~Jjqd4D^JR*9r~BV-m7+eJFGYRXQq+$vMg7@QbS_(p z2C${*Jhl`KWJ}Q?wiFF!qi6^LMduSxbO8ZHLkTFlkbt6#2q?OkfTBwXD7ut@qRR*< z8b(0TZ~}_*2q+psK+#A7ibfGolutm>Xab7H5KuIhfTD2(6pbeYih8DdnXfoSzJ1oQ zmlWAwI1{-%J!-y8Q9-(&{hAa_=6ord!j__`Y$+;aOHmP9il(upXgXVpu3$^i47L=_ zWTR*n0Yz65P&Au>qN@lfx|)EZIRq44LqO5B1QcCIK+#+RislheG@pQ?>j@~jfq{%Ek*aRrRZL^6fI{<(S2+wx}S}r2M8#7kbt5U1Qb0) zK+#G9idGR&w3>jThY2Wpgn*(o1Qb0=K+$6a6s;woXdMAXj}uU|o`9k!2q@Y>K+%%~ z6g@>i(bEJJZ6pMW?nw9UaX@0D?6Z!GrRa!_P3ckdWs06p_g{QdieBJ+DSDADMVr}D zw1q82FR`WQWwsP;WlPa3Y$WI30Yx7YP_&DHqTK`(?IED(BLa#(CZK390Y&==fud*A zy@L)&>{h$^c}|LIx|c=vr$^0~Df%qk5ATqo&pBU;4zi`_3$_$}$(Eu+Y$-a-mZGoN zQuH-jijJ_Q=o>bQz9pdOI|7QnC!pvk0YyI$Q1l}KML!Wxbc}$ap9v`Xg@B@82`D;F zK+$gm6#Y&>(H{g9ogkp-PXdbmBB1DR0*X!&Q1lN0MgI~4MF-NoGaZmvW&5n-r&83} z9_gP-kD4!2(%4dz&X%GKHi|L{ zD9R$BC{93883KyR5>Ql*fTHpQ6jdOgs3HMHl?W)ROh8c;0*a~s|s3{vo%?K!JPC!u$0*YD^P}GWm zqSgcywIQIWEdfPm6HwHSfTH#U6rDprQ3nEwIucOSiGZTc1Qc~4pr|VWMcoJ}>P|pW z4+4sM5&}hMW_V9IAh8Apr=ApzwGVH-GNR_o6!pvSckPs-{+usG=dz_}09%UAV@uIM zwiFFwOVMDq6b)fZ(fMpCx`2(Mp#&6NNI=m=1QcCNK+z=x6kSR{(Pab_4I`jvH~~d@ z1Qd-RplBokMWYBP$|s;`Gyz3p2q+p$K+!k?ipCRAbU6V<69_1pNC*`5$?#4%AhCsZ zThv#I?9)V%Nf}Y|Ws0U|_*HgEQ6c9`Q4w2;rm>}HI$MgaU`x>qwiL}|OVKR06kW-d zqS?Fy`2-YQPe9QP1Qgv!K+#PE6x~cf z(JcfNEg+!iRsxD{BcNy@0Y!@lD7u}1qB{tIqRAQFISxoHW}kJOB1KE=wrFui)O?wu zr5XOPJyNuc^QGu+wiMmNmZE#vQnZ{cMfb6#=zg{oJ;0Wt2ia1zf{mhw2q;=fK+!4! zidGX)^e_QMj}TC_hJd0+2`GAufTFbo6s;qm=y3vy))P?l1OY`G2q=1zfTE`eD0-TJ zqKyO;Z6cuP83Kx)B?OA@%JAknAh8|xS;r+(wA&u(KbH|TU#4hthQIn_DcZvMQuGpA zie6?*(N?w;y~38FSJ_hZ8e59Cv8CvBwiLa=M$wxD6m2J<=q&<@b`VhXHUUNN5K#0k z0Y&c-Q1m_lMLP*7`hb9<4+$vRML^MR0*dw!Q1lT2MIRGTw3mRQeFPNkC!pvP0*Ve0 z0!1%mcsm@BSS$N7{)S8OTznk_{~ z*i!TjTZ+DAOVM|1Df*s`qN4;9{Xjs`j|3F`L_pCo0*Zbnpy(F@ihd=a=r{pIzY$RM zI{`(15Kwf2fTBMMDEfn0*XSJdSH&CFdE|AhqA2G}Q3_j%QrS`zV@pvQTZ+=zQk21#qD;0FWwE6w z&PGug0*cBKP*je9qVfb3RUn|KA^}B}2q>ydKv5L}imDP&RE>b5>I4+kAfTuw0Y#?~ zP*jV6qS^!$olZbe9RiB#5>Rvo0YzsL0!5Kb?|cU&mTqwT%;1r}yQl3Quw_QgmnmwP z>0j}g6gA>}DQe7?q9$x9%4SPZ4qJ+H*;3S$Ek(`PQq-I+MJ?DUYDqv*D*}pI6HwHK zfTFep6rD{#Q9A;P+7nQ84gp0S2q@}EKv5?GiaHZe)P;bet^^cyBcP}|0YyCsDC$W- zQ7;0DdJ|C8hY%=gkm)UVKw=--XC2RyqRvLDZ)VhdnW6!i{+5GMbROqR(LlBo4Pr~t zV73$uVN22ZY$>{cEk#4wQgk6(iY{WK=wbqjE+L@kQUZ!DBcNy)0Y$?JD9R(CXaoU8 zBMB%PMLldR(O3eC#t~37o`9mu2`HLCK+!}3iY5_IR6sz{WI~{*f2Q}P z0}^Xs-*Ek!HXQuGj8idM3vXcZeps|hH2 zn1G^32q;=ZK+&TF6g@^j(OLqE))7$jH~~fL2`GAkfT9fq6g^2m(NhEzJxxH-Mgod9 z5m59D0Y%ReQ1l!DMb8sZ^a3GJv@Fw`IU!KACDYsJfW)rz9GsV=sHcsCnNjm)iVkP`d%l&TuQ*?dzGh3&5w;Y4!} z1OY{V5>WIP0Y!fkP;`=jqJIb|`j>#BQv?)+vh=VWMPUMpk_agB2q=mW0!3eDdVe_} zu{Z4BYCI%GdrXm^6*XU`C^gHkc2tUDoG(RbY$-}-OHl?}iZa^^EAfV_>0*dMpP*k6Qq6UOOQ8dfz=zzrTvb#blS-~Uy2aVKOSyA(4 zikf8kc|S@~Hs?!G4qJ+H*;3S$Ek(`PQq-I+MJ?D;)RHYlt=Ll3nvJ411QfL;py+G@ zirNuS)SiH%a|kHvKtNGP0*X2jP}G@#qAmm!btRyv8v#Y#2`K78Kv7Quih2=H)SG~! zJ_Ho?C7`Gu0Y&`@fucrP-t`Vh>w-ENIYQ6ikdG|G$_k|Rv- z0YwW5C|X27(d`5j-9bRnVgicpB%tUn0*aOpP_&eQqGg0Y(ex~@?5|GIG5bX06;hO8 z5Bu-VikdG|bYGU=>^CX8pYx^Y0k#x9$d;lNY$WIQ0Yz&GC|XBA(c=UZttX)92?B~X5K#0a0Yy&{Q1mnbMH>ky+C)InGXxYp zOF+?c1Qb0_K+y{X6un45(PjdQwh#hE_hxxR9gtXayDeHSMOWBIw3o7?=F1eln&r>@ zLyBJGd@0(-mZI0$QuGE}ir!>P(RQ{Jy~UQI9c(Fjn=M7}uu=3b0Y&c-Q1m_lMLP*7 z`hb9<4+$vRML^MR0*dw!Q1lT2MIRGTw3mRQeFPNkC!pvP0*Ve0Q1mGQMV}E+^f>`V z2MH+pf`Fng34x-mS>F8)NNk-wEPF+YX4-Ahp{%I+GDSzS{FncfqHj1~ioRt_(RXYq z`kpOCN7+*J16zuIWJ}RcY$-a%mZG28DEftfqF)IpI!-{*Zv+(mPC(Hg1QeYhpy*Em zivA*?=x+jwP7+Y`4*^C05>RxCfTB=b58F``CZH&ZfFh58q6h&+J^@9^1QbOHfugUn zyu%JiY_0F$d@V&2?6xQ+9yMR4C_V1`C#5KZ^Q9=0Ek#*uDT=eDs0>?*%Ce=X99xRY zv!$p4TZ$^OQB;Y5qRIpmRUx3LDgi~+2q>yfKv4|>ifR&2bQ%FgwFoGxO+eA<1QgXF zpr|eZMQ0FDbS42s^#~}cPe4%v0*cNepr|1MMU4o7qFCHJ%K?e)Np*12;=v>Rm+iw_ z<9O73nWEgd-{)T`YRdUi)Ql}f&Dm1af-OZY*;3SsEk&)_Qq+bmMQzzqbT%7B?FcAp zPe9Q*1Qc~3pr|7OMgI?RcODgG9shs-8m_q*7*Gb>(_B*1ask{m&E3pBwX(7h6}MCr z(6lV~EVI(AG_%FDvNGGt%1X=j&Gx-4+p{t&v#h*7@3~%2pzrtm&VB#!JLmSCx_CX| zf{}SR%z$7|0*ZPOP}G}%qCNx^^(COF9|1)t5m3~hfTEKLC>lUO(Le%<1`$v+n1G@o z1QZP=plBEYMW+x#MY#!oh655GZMQ{vQj}sJ(S|2t=F1eFmIzjP_6qX6=;@pvNc?X5(%Gp}RK*_YpO=W4FH>|uB6u%Fiso^?6kW)cqKnv4G@mU+3)oV$kS#@v z*iy8ZEk#S%QnZwfqKgSAT1G(8B?J^*N))Yv+Z-&=S$Ha zcEhwj5i?(==;lOlwEJ-o$=jk0oG(SUu%&1tTZ%TZrRY|+6y3&_qTAV0w3#hMcd(`C zPBx0}BA{ps0Y!HcP_&hRqI(D^x|e{W`v@qypMatV2q=1xfTD*8D0-NHqDKfQ+D1Up zqXZN^MnKWy1Qcy2py&w#ik>8(=qUnDSD3crRaIK6urQfq8Hgx^b%W&US>WIW0Y&cWIR0Y!TVDEgd$ zqAv(2+Dkyumjo1jMFVOVMv^6#Y&>(Ln-={ve>}5CKJh5>WIP0Y!%i zDEga#qJIb|`j>#BBLozA*?QQHq6h&+DFhVx1QbOHC<+KDN+qBuMnF*-0Y&Kq6vYXl zqHh!aYYs@f*v;s7QZ&jQ>1Sle%$F(3$_{?ckfH?VOHnpkigMUeRE;e~)!9;1gDpih z*-})CEk(82QdEbHqN4~Xs!KpoJpzi3CZMQ30Ywc6C~8PRQ6mD1jv=6^F#$zQ2qe#}QC;JOM>52qPtXTKLUzQBA}>00YxVhP&9ymqJaby4I-duFabqF z2q+p#K+!M)icTS*XgC2yBM2xONeC6S$@b55K;qTyF|zc5p#L ziq7PGDLRWSMWfkLbT(Ux&S6VY0b7d3u%)PwEk$G5QZ$Z@qVWV26%kN0fqQk|K+!A$ie?i~bRGdk za|kG!O9&O6p6%c4fW#ZvZP6$x`p!NDd46`xe3_z)vV)yDQZ%3QrDy?LiWah^Xc1eA z7PF;j30sPmvZd%^wiGR6OVK546kSR{(Q*QcE+e351p!5u6Hs&o0Yz65P_&YOqE!SG zT}43AY66O`CZOmV0*bCBplA&NMQaHtx{iRNbp#Y$Pe9Rn0*Y=Rpy)v@1Ji zzD&^z*}>piQuHF{OVLYgDSDYLMX#`>=vB59y~dWJ*V$6En=M6eu%+ltHj3UNpy+J^ ziryih=v@Me-XoyseFBO;AfV_&0*XE&py*=)iasHr=u-lUJ|m!L4*^A=6HxR80Y!TW zDEg9sqOS-j`kH{EZwM&*mJlj>F5540K;mE6BmL*4=r8xY=y%yM^JR*D%nnx9k)oeC zUy6QaOVNI|6#c@Mq62Ix`jst3zpY!n?Lpy*EmivA*?=r93Ae-lvj z4*^C05>Rx6fFdtP58F``A)qLQfFhrOq9_4H0Rcs+1Qf*xC`u!sD4l?!H~~c&1QcZw zP*jBwD*7SY-{yeC8`y2pJ}H`OAJMAj#LSl|%E<{ns4GR)IA4mYv!$p8TZ(G3rKlEL zifXf^s193-j$%tuUA7d}W25M30*dMrP}G2cqJ{(%H6ozs7y^nK6HwHIfTE@Z6dg-I zQ8NOHniEiT905hg6HwHGfTETJ6tyCts5JpaxdasD5m1y*Kv5e)s3?)+|LcInueVPT zW#@#C^p`q3(Y84;^JR)U<^&DuOHn7zm!i&WDeA(Oq7&Fs)Riqo-PlreB3p{Ov!$p9 zTZ($JQPhioqTU1)^&z0BF9AjU2q-#{ojiMC<6kSe0(G>&~T}eREN&<>j5m0m$ z0Y$3`D7u<}qH72!x|V>VH3Sr`C7|d!0*clVP;@;3Me7MDx`BYA8wn`7iGZS;2`Jh? z2o=rG@pn5Q@vq&CE|8+1ZQPO*Ghbd+FD2SIz3#CQFY9*qC0j4+MFW@hgZqkYT2>YJ zXf87=*WEQwWSvsQ^QvcEljV7}vp&l9yn0!Us(W6;tcf)}uSwS3wLPzS)~`o-Udyb` zM|)mg*8B#Z*DmYXMxNIxE2D|$bv_Yn z?#cJOky*dD^}JD8Cv@<<(OC;SdES_;=eu~`_^c}3Ja1Cgi0+;@HS4;bo;M@wv)-Op zmesVM=grAFx4-Aj%errX=Pk(kW02=9$?7)L^DfC+e2V9-$a-;v=dH}jI?eO0&N_9J z=dI1U{!GtXpY{1@&$~IRS%K$m%9>W_d7HBy80UFgvi>acynC~{Px8D6vzAWrylq)8 zPxZX*S=q&&wR>xNR#dm(G@EYEu->p1sMV(iW;KHu}+&U$E`=e?hG_#)5y zIIHJE&)bu=Y_aEknf2;Y&-*s3+9jU1FYAoup0_{irWKy|Th>=sc;2C`7OOn(@5Id2 z?)@K0JaUb@0wRfj*0^gRlIXq8T?LWErR&{w5J|j#qq`C!i5eT+wGc_1wb5M-k;H~u z-SrSj*uQ4qB$BXyj=Xs!VgH_V%SgihLEyYd!v00qc9DerlboF*3Hvt{yG9cBkK*-+ zBk~=XKTFj=lCXbQXiy~a-41u1L=yHddyI@E?4M>B6-n67)*l^7*bhe^6G_-l zw;mr!*pDZk6iL|6mz^3(*bfMu5lPrjcr1$~>__y?i6rc2tj&ug?1yA6h$QT%94(0? zp4j8Ap-94h&d7>L!hTT1%1FY#)Boy7!oF2|Z6smeYr8&@uy2;UIg+sNcH0z5*taWf zjwI~+O}0c5_6-B~MiTZnz8{Pv?62%@izMvtTyBpf>@Usjh$QT9J?)Al?60l75J}kI zJ9s6MurD0%jwI|We{V+;_NANmBMJN5`^S-lee!fqBw?TZ`ZAKRPhWf+N!a7heUXGc zfY={N*ge4CA_@BtekhW#+u*+=UUrIoZhuqwM=s}0_va|m*8MSZ?@0GwWc~N<&seoZ z?nNT)t6pijnv>^6I%qVt=XBKg-gl!@)y2sdyV3pmi*(j=ZgsCQ(naHOJLd$Ar)_lA z7#?w>o5pB+Z6|6x8F!<*#ss?rJ;G7l{So%;Le_{3i{yD;&CA{Gf&CXW_2XV7JJPgj zwG6*%-KwY7%64izFQti>k#V9+p6A!}{Hk3tPRQt-adI{HPSA7G+{x`dE2-5Y85!XV zMBI#3@%%JiJ|m+_MrKAQ_q$B1^`DnYcP~}xwZ=7r@Qq~XRk~@fGE=WI`P_ zFICl@6jWS}tSau(*;`H|p9nlJTfY;%k(}0%?sd2j&FW-Fa#DNLUel|Ny~S$nDqXyK z?v+%(bWy~;pYq-FYAjzA@ltB9>gC?4HCub#>vXL%y=wCHxL54n&-L7Yc600ASIPg| z|BOlHUzK+acNO~Hcy~%l(;p?g}D<-XXKWajLR)4C>>W+Fr%cn ztY};*~`0^?wmWLWb(AhWs_$YdAXB{rxoQEPA!^~ z+j?s8xWcKqrIQLvigHVerWchKmgW|ZUoj7h>L1D?X z-2A+PwgqkS+T<7H=UHs!Vyo%J(~DXa6^@Eou(8efz< zt#I6=$gqo}m?BopSYuJMznm$~5tjp*ICz+KF7y^E(!E1vF}!v~nj_Nv3= zxtq!$snc&834&_>r(Z!N)t?v%a{M|CgCKQ~yC)H;5oFjQD`;eg)JQm6yJxovYPgxx zy=9}IVdJ1$U6*o$9GCw0@tFU-riPVYlf9uf$s_w1P8DX)LQ z*zm~??aH5Q-@E+D4xRLp?K;tVa&lg~@OgcE>t*uY3r`+YTs$M+8{BhLLGK|W+k~&X z52v&*e|sHCZ7bexoAS5YyV9%F1#H6!9m-#-bMi9HnqE42;`E~N4c)btd~>~Zx$^t* zTHF)-Hv5+UKJwj#Nxpn%_hJPF?(DX03c}Zr@7@?E^y9Vl)NAWi@fzHFz`fY`S<|M? z4PTR9wjFP{r$Wc_3*g?N<*&K?jkM!!^r?7fxOahG&|T#4-RNFR_(Y|P(2-N!J1_Z6 z_m0(h?aN=8yF9$nHhTHC6_=xT`5F1Wc~kC!>kJc6=|=AV)*tOYMPp}8^xW;?^od0U zMbpPmE}UL4wRrl(@HgnL68Gla4M?TyL>H}H#ie!EfB53%zdfMkC4YDSH*e_maiZep zBl+j2bNRa|-~9pc2KGIppl6@q$qVJ&=soEEeCVk@74LL+rf0w3hROf^FT?p2zsp`? zie_gd`3B%y4mAAZV3(_J^6V-0M=|-Ld3qJ@Plhf@uky=ew*ko)>REB&`T(u1o>wl9 zH=f_A{8i;w;07ZW^DDHw--X^Z0?Vzro15eX$giNA@9c&xk7rhB&hN+dF2n_PGp%bT zc@{9-Zz+5&JYiQ-@`|faqjv)xdZgzuI7@Su;Z6&ms@IFt*lP~bjjyVqYjsko%9{Ntp<#-#|a^z!Sw{3E*i zW0HIkyH1jV+^|ftkG#k8o!{`aR=Pqfu0Qw2 z^}fk>cT&O^bbmheMEScgKfHGBVph6Y&es|4TCI2oyQfYXa%#igojW(Q``E4X8`{0> zyiRS}HEdo|G_|O(wCK2ot)`8eF{|4+_Z};n(`s7Vwl0)Snl){#J5HEdTv*o1-9_)_ zu9oo@+)GZFF}r=M(iyGB=XY?Wuw>k%Ztgz&>`twwwVvkg^|u&bI-|ve84X)aY}jgO zn})62-OO&|+y!VgVOmjXY2n18R#S_nPb{0%EzhO!9!)E|*4?t3wzA2^(_59gyUXra z>e~3ivcmEmzAN0lg7Aq7viTKejpP66V@=4i(g)jed(Lk1bynOvG>!H?uDFv}an~?E z1fG=QZku(nDz2eWdHDysBQ`p#@siFNwlz)WH=bmWAy~>I^lNI+R z-Mv!ygntU`;*~q*erUyA#7g%Nxf@z>caT32b`LRp#|UD0S1|cIxBH*EOPc&0hJWhH zf7kpeE4K_~yB~UP`3)a;H!JQER@@^5b@?@3euuOCo@Du*#!7#BD*g;q+~wm6uDHWj ze#M3N8oiTx_wLfLx&3+RSu(9*-)Uou#*cURwny@CHu*=0hpET?pZ`F)N8g$5za#FK zd!#?Fs{8zdeFBAF_Tar|)x_fH5`SsR6%nszXBP_Xaj+N3bx#JJS`BVJxaY}3ywvR2 z;B-HpmJ_WWsS&B=*N)VQ92Kb>sTZlAa!jPPJP0DmV7VyDXsG7`kwnFPo-bJ=RRj#>6h=>r#mWs z`JVeca;0CsmsM%m>;Lbi@x8?Vcz!j{eeNmwyR`Rlj=Q`~E4@VWrT^z+<0fTZlkwj0 z|J<>1mjCB{b^CqCbKEDZ+%d&I^=(IYaqSY>v4)Oy?C5@5jqK=NsJXgbul928v)9R^ z`bOzI``lx5dp%F+_?EkhY=5TX@9sBX zJK{bgXvbRa_hQG!I@)KTZ1>giEcdkSi8|iwt`ggK>-e>M2iX2q$CmCLWxKPECGJZA zw&&}(&HX{J{j84v9u@A4y5X^p`vQSI{}dgUHwgC{9e2BTtUdn|9cwlTcVit#9~00DJj+bo}=CaR07j>sH}DLB}$8McKUd7~aG$H=rk>%xPsi_jhx-p5^ZJFmn~t;lhkLP(+XsaE zMIBQHhdWEh{zJoks*YEj67K7De0xN=KiBc7)56_M$1$VAJx#~k&J6bhI_?`C?mu;G zQxNX%I?gE!_fj37bkObn@v@H53E|GxaloW-pRVJ|DdE0B$9JcOd#{f5io<=Jj$>zr zyI9A~rQv=^$Dd|}`>>Af=7hVaj_02r?qxdem>2F>bxfTf?rJ&?S{Uv#bi8VDxNp+& z{iWglO2_(_gu8`~62=^m8?!O}3|LE9ZRk(ZWIB#{hFV*qsYr_4yj%jPd zT|>tq>%x7Oj#sY__XZt5bYE4n>*pIC8*T`9D;+0n40oxHTW$^aqdFeAJ={lh>~v?i z`|5bnmT+IDc*zTAm2em6xc0Sh->T!M zyTkp1j!oVQcfO8O-U;`4I^O$UxS!DRp!@onT|fSZ;j!z-;qhc07kwJ;D|LKfPq^RF zvFhG%*VS?4SK%(yaosoJzFo&X--Y`}9gp1??zTEk{VCjYb-aInxS!JTkoyvyUEbi= z@Oa|y;c=jjOa2J=Dji>PU%j)Je^1B6-{C%5$J71|_c$HbyN~|%@^|R?h5HJh?VojQ z?mmBQySQS1JCQOJxIqhbey1Lsg4VDyj;h1I^M41gF5ci@iiSkvZH%D zKWP7~W2)URNpoLBv!i>y{j#IGJCZz>+Wi!_-Q5K*rKTo4idfqbk zbmiB#&AmQ*zuM({s=c?){e;K5hTE=h=U^=*Y|U=@jt>xW+GD z?j9HHX@0GAFK5>|zwGy6zwUDXRla;XD*b-5-ShbUZg)?+-`)&&NdDUHUSAi6JMy;d zh;4iJA@_25F4k~Q^ZM-lZf~>FyUT0tymWGnU%Wm$r}E3~c9-uJUdSDJxyla(^II3^ zy3fjY=#G684qzy=} zpk4CW&AmGAmaX@JCcRpHx4-AW1ABT8-Creh=>B-soMrxRUKQEU^wygiW+%d`4``~9CG^lQ2+Gi7k? z!S-^|pr-r7=&!Vw8d_&eGR6LOuQnwu*yTQwrKH7LJAKh;V4waXYu0wNlNZg^tmS5B_kHY| zHQmg27b{=8hHZDb+Gtm|?Jihb?P|8&C2OahW7}P{_S)ID-DT^bov`gLTu1FJ+wRhJ z(ynUTUA)fPRcyP<*F`(i?KbZ6ouHjz+g-k{+Hu?N@^#Zrx9u+9iP~wl-R0}99kcB& zUk~k6+wSu9)DCRB%hyXgYTI4D-rBxxclr8gr?}nLUB15B5!>$a_0x6?(xTBO{)_JV zPhV|*nkK);Al*J;6Fn(*yL$l>GBB{egqajFNT*83U`+`bqA4LmH6>)2ri7fLDIvo( zC1ixAgpAabkW)1ga+)?mPS-}rC~btCp^cC;wGncbHbO>gBjjvtgq)*|kOFOljL}9& zp*BLsY9nNvHbTa0BcwK~OnL1TMN;D;;R8vCAG$mw~ri9Gal#uf@C1j4Kgv`~Hkn=SW za)CBN=4m73LT!Xxq>YgI+6Y;ojgW=f2w9|!kj2^vS)z@QrP>I&SQ{bBv=MTNHbO4d zM#yq)gj}YLkQLepxm+6|S7;;TN^OL!)DDGA_p7)MCh3jb2b^eeDCBcTBf2VPa!klI zf&Jy}q>yWMs)Vf3l#sQW5^|lUgsjt)kn1%iWWA<@+@L8TH)=}AO_~U~SsNi6v=MTP zHbORPBV>~{LT=SY$ZgsPxm_C}o3#;ghc-g))JDi%+6dXAjgY&w5wcYqA@^t_MHbP#}M#!t$2zgB#A+KvAWVbd#-q1$Ko7xC@OB*3?Ya`?xZG^n5jga@W5%Rt^ zLO#$&$cNgYkZt}c?)pzpb$4{5kA_0}+I^CbVkXCgd=}U@eI$kK(Ww&hxu%4Cp(!DI zH6`RrO$qr*Q$oJhl#p*UCFEO83HeSFA>V5wU zM#uqeg#4H2-G;a?EE*mA4zy?_ux|-Uejj5H(b@VAv{bgf11-kZcc7)Q z^&M#GY<&k>oUQLb%V6s}&@$Qj4zwz4eFs`qHs67kMc_No5(K^jEt|l1pyd$w4zy|n zz5}f~f$u=8LEt;kY7+Pkv|0qd1FbfJ??9_V;5*QcBJdq(bqRb2T0H{afp#>3??9_h z;5*P75cm$Xh6KI?tr3CmKs$!Occ3*U@EvGP2o6YM;ux}|#DmtF?rKkm4idwRzs1;j^TC=4nmn}tkY$?iTOHmuP6t!ies2u@C z?FlIAKtNGP0*X2jP}G@#qAmm!oj^cQR|1N<5m0m@0Y%*jDC$8#QBMMjdJ$06n}DJ| z1Qhippr{`KMJEwZ)SrN&lL?`sW)a{0O%E@Ax!n{sm!j8=)PP9Le3_ylk-)wsF{x-M z=S$HrwiKPhmZIToDH_3+qLFMVI+ZO&r?I8zbhZ?YVx#B`0*cNgpy(_DibfMqbT$D+ z=MYd-KtRzL0*VR=C>l#Z(KrH%#uHFfL_pC50*WRQP&A2vqR9jlO(CG@Tmp)w5>Paa zfTHPyP|=`>-_HSwKj>z3uoUGPsbcq6Wt=ZlR2m8FTUwKf$~a$&X0fGcHd~6$V@uH- zwiL}}OVRmkDY}3yMf2EFbRio>7ZFf2pMatT1QabKplA^RMT-e2T0%h4QUZ!DCZK2; z0Y#S(P;@B)Mau~&x{QFL6$BJrPC(HW1QcCKK+#G9idGR&bQJ+bs|lf^nGt`50}^lO z9%)BQq-aR;aaJT|zD&{DNMPR*om6xk=S$H#wiI2@mZJ4+DY}6zMK`jg=q9!l-OQGv z4Qwg8g^i+(1Qcx|py*Ztif$vI=yn2%HWN^E2LVNQ5>Rv(0YzH~D7u?~qOAlJ-9tdp zy#y59M?lg21Qb0$K+%H)6g@;h(Zd83JwiayHbSWA+KB(A0}}ty;H;6N92<{DV&=;f zJrN1)Tk4aFp5%NfdWtPYJJ?dRlPyJ0v!&=6wiNAROVP7zDSD1AMbEQQ^a24zFA`An z5&=ao6HxRD0Y$G8Q1luBMXwW3w3~pUHwY+tlYpYP2q=1+fTDK@D0-KGqW1_WdY^!z z4+tpwkbt6(2q^lPfTB+bp`ynler@+R3gW)q7HyZJy>{>V(@4yGnW8Tuf&EB^q@ul? zFGXLnrRXcR6n)K>qHowz^etP8zGF+#_iQQpfh|S**eLpufTEuWDEgUzqWuIE{X#&| z0RoDCC7|dx0*Zbopy(h0MSl=bbcleWKM5%Mi-4lT1Qh*EK+!)06#Yv;(GdcQyp-}s z`I*VDM@0xIN+E=b_C)-19FX{h_IGwZm!f5MTjZz2%$F&Or3CgPJ(7yjIA4m=*-{i| zOHl?}iZa^^g5m0nA0Y&u*C~81JQ9}ZX8WB)*3;{)r2`FkpKv7cyw?)SiP}GbNDhg8k zO%6zWzI{S5H6?tc|AE~WHBX6|FH_VqC9od}lT_4-^QEXYTZ(eoQk2J*qI|X#wP8z9 zTecLnV@pwcwiI<>qo^YRMV$yJ>P$dU7Xpe-AfTu#0Y%*iC_0gVqV5C~^&p_ACjmvh z2q@}JKv5q8iuw{z)Q^ColL#p4Pe9Sh1QZP*plBcgMS}>TqT^Hi?;Vi%(eCd!MO#Rb zZ;$i`r^L*cDLN%3upcRuR5YCPrDz0Oibk@f=v1~8oyL};)7erqiY-NFu%+lswiKPk zM$u>jiq0mW=o|uy3J53~LqJg>0Yzg8C>lpV(Rc!iiU=s0KtRz%0*WRPP&AoT{~fTC3d6kSC?(P{#U zt|p-98Ul*0C4`E~QvBHtNW6=EifEP;ZMWN^H7POkWs0s(3Dz{1qV=3FMK`de=ti~_ z-Ncrno7qydfh|S1u%&1tTZ%TZrRY{Rif$vI=yn2%HWN^E2LVNQ5>Rv(0YzH~D7u?~ zqOAlJ-9tdpy#y59M?lg21Qb0$K+%H)6g@;h(Zd83JwiayHUf$sC7|dr0*W3dgo>_9 z@wYo5@s$w=XPp%NYj?G`r^L*cDcX?|*pI|Z-WKiTd?|XGEk)0;rDzvhik@Xl(Q|Am zdY&ysFR-QPMYa^Z#75D}1QfkOK+&rN6um}3(dz^h?Ixh;4FZbZB%tUm0*c-ypy(X} ziryul=sg08-Y1~w0|JUZB%tUc0*XE+py(3w;u0KzSnJ-iHRZ7sfl@xu=`BL-^TZ+DAOVM|1Df*r*ML)2mXdhdOeq>A0Pi!gr znT?|T1Qh*3K+ypLihd=a=r;n2ekY*lAOS^x5Kwf8fTBMMDEfP0*c(xQGe3_!SAJ~uNOx_k{aK02}vZbgBTZ*c(r6`LnMG3YPWwWIyhb=|b*iuxTjiMR^ z6xAf4s1^Z5wFxMyLqO3{1QgXJpr{@JMMo1*RG)yN1_Tr}B%r7f0Y%3UP}G=!q9z0s zH6@_vSOSWg5m3~efTH6FC_0`HDoXSHD;$vcB>U?^>3;Y~|8=`9YT?Jsmnq8i1N)J# zNkw^_FGcxmDQd%(qPA=)YR8tM_G~HYz?PzpY$@u*mZHvV6m=n>=mY|ax)M;-jew#P z2`K7LKv53@ih2@I)QfPaVfTF|t4JDf-%Oi-!3z^JR)g`hopO;H08cIbVuSV@uKLY$+PW zmZCG*QgkL;iq2w7(P*|5oz0e_bJ!>UQZ$b(MHjNA=pwch&1Xx|0=5(_ zWJ}Q^wiGR9qi6{MMN0`Nx|o2XWdsymLO{`_1QabNpy)CJidGO%bU6V_b% z2`E}cK+#nM6s;zp=xPFrt|6f4S^|pJ5Ky$1fTHUNp`!DAe~beXKWK2~NKqgAh_=p; znJ-gxqaWChBu^^3iSwoCX0{Y>=77XMGDSB?(Ow%*`7!flik|TU`;qoZMY}j( zik@Xl(Q|AmdY&ysFR-QPMYa^Z#FnC$*;4chTZ&#~qv$mPie4w6Xg2{xZxB%QCILln z5m59t0Y&c+Q1mVVMeh+%^gaPa9}rOVApu1n5m59o0Y#q>Q1mGQMV}E+w1Hg;R|r5`h2rs!KguzwOEspvb-m!j|4QuG5`iuSRk z=ts5`{lu1{pV?BhpDjhdu%+k#8%4hoQ1lxCMZXhJbdZ3eKL{u~L_pD>1Qh*6K+$0W zivA{`=pO=#{w1L32mwW2R1e!x6d|A}g@7WTfTAb?MF9atsRR_o2q;P;go?iQ{WcCr zyrq4*`Wq>_!0uhAM`Py86jg}^_D^ag6;ycKv6vcijF3rs6GKj4G1V|NI+2|0*a0ypr|ncMNJ4O zYDz%Su>=$~BcP}`0Y%3VP;@*2MJ)&@YDqv*D?+F!BkIp_K;i@KwkR_iKGH9>k7%u< zG4o}L+C+ovdP-4S&X=NgY$dcm+E^H|}fh|Q{*(mBpK+%Z= z6m=({s0RT>Jqal4MLlgS(O?3K zh7eFRlz^gP1QeY@K+$kQs3CwRcNuT6x(J0QB zqBGc1bS7Jh&SFc^Xtorc&6c8b*iux$mZC9iDJo>6Xe z(If(jCKFIJg@B@S2`HLMK+!Y;il!4#R7^n83<8Q~5>Qk^Kv5|HMP&pO%_5*^HUUNF z5kf_$M*V0Xr|7VK*6}ncnw)&V7LA!NQ#3Cc*gpxCRCFQdOVLGaDVoogq6KUzTF927 zMQkZr%$A}hY$;mGmZFQ1fP+ znWE>Sf&G(oNkz|dz7)N{mZBHgQuGpAie6?*(JO2zdX+6jud$`*b+#1kW~1m00*c-w zpy(|Eiryxm=p6!z-X);uJpzi}C!pv90*XE)py(q4iasWw=o12pJ|&>&GXjeC5K#0v z0YzUBP_&nTqAv+3`ig*}uL+@|T~YsC2PEFlK8QUlMVsuA{x{K>`7%X6L<9RL4U>xY zalRD&$d;m?*i!T}TZ;CxrRW#76dhno(XVVN`i(6`zq3(vkbt5;2q-#4K+&HB6#Yd& z(P09L{wAR49|DU0C7|dC0YzS*hwUhe5KxptK#@;Ck^3oO;aBWY6cA99NYFmZBPLDXPhqqFQVzs?C<7I&3LAijAVW1QgXHpy+4r zf2;!%&#=FDofU+S^nbU%Y?L3w%$F%@9|ZPKswNe6;Cw0S$d;l`Y$@u@mZC0fDLR2I zMP1oa)Qv4gC$goeI~zqk2q@}FKv6FOih2`J)Q5ngz62EYBcSLc0*d+*P;@c@MFR*Z z8c0CVAOea86HqjSfTE!U6b&Pw=oA8qh7(XUf`Fot1QeZ02o<#r{LKzXJl}49+DXw? z8>a;^^JR+83(If(jCKFIJg@B@S2`HLMK+!Y;il!4#R7^n83<8Q~5>Qk^Kv5|HMP&pO z%_5*^HUUNF5l}RTfTFns6rE296^#n~pB#|*R=X>7h7=XpoumtbnE5hA^Mkvif$mF z=tcsHZX$$=E)4v34oG~IJuJIOiuTxT(ak~3e3_z6L16zRcv8`=oG(SUv8CvCwiIn< zOVJ%{DY}y_MR&2KXbW44?q*BTRyK<6A)x490*dYE*=otcvb`e5Fw*>zA z4oG~l-4)s>MbEqEMV}2~=F1el7zFlD$|n`Q#Q9S6GFysXVN21gY$ zir!#L(VJ{3dW(&sw+SeEhk&AY2`GAxfTH&aDEfeaq7Mlu`iOv{j|nLHgn*(?2`KuE zfTBGF6n#!W(H8_1?Iob-O9G0%BB1DN0*byNpy*oyioPR+ik=Vr9S%s`{eu!-^aUxh zAJrNCK8TqwQ}k01d_G!=e&&2B+Rv7vU)WM~fGtJ8vZd%ZwiNx&mZF1fDf)vgMTgiZ z`jdd7zX&KgOhD1!1Qh*4K+(Sh6dfU;$V=5jZWKibC`uuq$S0sENs3u#AYO$rLHd~77u%+lIwiMN6OHn0*a0!py+r4idqm*)RKUrRs z=F1cDGXX^#2q?OR5Gq=b>erv(6z#R!qJ>gaGx>lmHD;rD!W#itb@c(Ypy){gik>2%Xa@mBI|(Rynt-Bb2q@Y`K+&@V6g@{k z(es2*(XFZecn2h2)jmaZn-pDQw?!|c#>|%~dL=bjIz@_J<$Ni6jV(p5v!!S^TZ-Ob zOVOKbDSC@7MQ^jE=pD8cy~{??dju4{Pe9QJ1QdNpK+#786n#uU(I*5HeM&&lX9N`O zA)x4U0*byMplB}vMPCw7^c4X`UlUOD4FN^p5>WIV0Y%>vQ1k-D50!1+@2D_e?wV@uKRY$-a(mZCq{QgnzdMSrrT z=r6Vu9cH8GZvu+`A)x4A0*a0hP~^q*upLDa0*X=yDDnv?iV{#15Kxp#Kv9fEx zqMETFyI6{9alRDQW=l~WwiF%3mZG|BDXPboqNCYTRG%$H4cJoDkd2~71QZ=ZKv81? zikc8m)RcgtV+kl~MnF+>0*a0!py+r4idqm*)RKUrRs|vEI56p6m{i%DeA_S zq7&It)SWFwJ=jvzlPyKP*izJ+Ek%9UQq-4?qJ9JvokT!Ue*%h5CZK2l0Yw7|C>lgS z(O?3Kh7eFRlz^gP1QeY@K+$jlibfDnG?IX#QwbXKEDH;v1}d?u z*#s1wM?ldW0*dAmP;@>4MHdiIG>?Fy3kfK?h=8K`1QabGgo@6I`A<6_@#glhtU!wP z+F!z67>k)NQ?xV|>~;UpZu0AB7jwQ8En`d3C2T3Wlr2Te*-~^FTZ&e&rRZ|D6kWlV zqAS@bT1i0BDguhGBA{qB0Yz66P;?CeMb{Egw1$A9wFDGhM?ld!0*bCDplCe-MK=&o zbRz*pHxW>DGXX^#2q?ORfTE2A6m24)=vG3gXmQL>o9z^Ba5K6@iXOJR+PB4G=F1e_ z84He^BSm*{z7%a?OVQnIDcZ`GqI=ji(GCKNb`ntZGyz4=5Ky#>fTCv!D0+^7 zqUQ-HdVzqV7YQhOi4ZE<9P@`bAn_0Edt>jAqB(X~`{h{7e3_!xV?puxQnZ`%rRWW| z6urroqPN&m^fp_H-eF78yKE_Xk1a*-v!&<*Hi|wZpy(q4iasWw=o12pJ|&>&GXjeC z5K#0v0YzUBP_&nTqAv+3`ig*}uL&snhJd1P2`KuGfTHgSDEfhbqJ0Du{YXI3PXrYG zOb8Xd8uPDqK;mQUuFz{zw8d_V_Qzu8%M|?<3m%#$MZa^t6dhzs(I0FnI>eTuKiN|B z7h8%Bv!&>7wiNxtmZE>zC^|wwk(Z{2?I?;6P?SPIkxxKTlz^gufTC0aiedy5r4dk+ zPC!wdfT9cniZTf(szN|fRRW5#2q;PrP?SwTQ4Rq`)d(o6P6!npi1{BnAn|4PS;t?c zsIHN!krp#wrl?L@aQGrAI*Rk9s4iQI>anHhXtos9XG>87wiGpFOHm`X6dl8sqQ-0# zH6fs=DFH>t5>V8PfTHFE6dgxE(eVTnwIHCVB>_dP2qPSFQCjyE(6GBC`()@<=oubq2FUi(U3m@r!VE3-Oq{YmaDLOGN z=($jex^uo1^d!{e$pjP)AfRX<0Y!rd zC>l&a(GUWPh7wRTjDVt32q+p(K+y;SibfJpbSeQwrx8$eIsrwa2q-#(fTA-AC_0OP zqR|8tolQW|IfPJA*ED~E0}?-CaJos+V!JIWNQ;>-Q#39uShiS-#&ffP;@H+MYj=9bUOh>n+c(!i_`oA4oG}!#KBo6MMoQ{JJMq2 z%M{(67F4@LinemT6y3v?qI=m=bRS!a?q^HU18gaJkS#?Iv8Cu?wiG?WM$t9`iXJ7P z=rIC{9w(q^I{`&c5K#0a0Yy&{P_%=9qMZa3JxxH-GXxavBB1D50*am^py+u5ie4a~ z=tTmGULv6AWde#`A)x40La6AjG{2Jr5+CAbbc+;a+eft5(qiVz6up@ioUvSr-r{^I zdYdgp@35ulUA7dx$Cje^*;4cYTZ%qpOVLMcDf*a=qE84Y`jmj8&j={mLqO5z1QdNi zK+#?TioPVE=qmz>z9yjP8v=^HC7|d#0*byTpy&qziuMsu^dkX9KM_#$GXX{W2`Ku7 zfT9D0P|@x*{~`y(eHG2Yc|(fsu}@_Gniex(rs$8f;HDK)bcpk%=ufs3{l%7|!)z(~ zn=M8Eu%+l_dP2qPSFQCjyE(6HwHJfT9x!DC$ZG6&;oC$FFpXI@%rTy6NE~{d1EK*wSO>%M|rY z4_d5}qF$UYMZMWl)Q2raec4jfk1a(fv8AX#TZ&F*OVI$f6b)pfXb=HKg9#`aLO{__ z0*ZzaP;?3bMZ*aw8bLtONCJvZC7|du0*X#2plB2UMQ0FDbS42sXAw{|nt-CS2`D;; zfT98dipCI7R7eOFbx-$)IUw;-cJtFiimD|au%*Y$mnoW%9?V=VMH4w+iYBq8Xfj)h zrm&^xT(%TVWlPaCwiHcgOHnafie|7;G?Rd$5(0`!2`DNfplB8WMY9PgI*)*&IRq5V zC7|eh0*WpmplBWeMHdoKbP)kX^9d+gKtRz#0*V$9P_&qUq9p_rEhV7nVnV2Be7b+F z0}_AJKI>Q{MOEG1r0BBrnE5hAm!$`fTq8v*IA4k`XG_r)Y$>{uEk!HYQnZRKMOU$< zXf<1ku4YToHEa}JOF+>Y0*clWP;?yuMe7JCx}Jcd^#l~%KtR!r1QgvwK+(+v6m1}& z=oSKsHWE;@iGZS82`IXafTG(8DB4Uw(H#U7-AO>vU4&54rRo014oJMOo6+S`bdo*n z-;y3PU#95Z^x&U0Qgk2ZOVRyoDSCh{MGvy2=pnWgJc>;=FAfV_)0*YQD zpy*`+ie4e0=v4xWUL&CBbpncZ6GBB>)BR)CIz^l8%lP+5(d+gY?Tz%9`7%ZCqzAp% zNzuEUFGcUMrRaUO6n(&!q7T_p^buQ%K4weNCu}MDlr2S{u~D>#fTGU{DEfkcqP+wZ zeMvykR|FJ&O+e8%1QdNsK+$&u6n#%X(GLU^?IWP*M*@m|BB1DJ0*dw%Q1lA{MF$8d z`jvp9-v}uBoe(N|E8U;ufW!wIoVTUu9sAPk!StB|XrLd*QXG>9(jiP{nqErHkVgwYW5m1y)KvA54q6`9xG6^WE zLO@Yf0*bN-C`u4elubZU4gp2g2q>yfKv4|>ifR&2REvP3+5{BUA)x3eLa69ay1&%{ ziT`N#i~f|N6KvFt$IO>0Y7h@zzfp=Ba=sKbVoT96Y$7lAfTut z0Y#k%DC$f=Q5OP=P9UJDD*;8_2q-#{fTHe%P|?wG|2GFD{=MD&)Q^Xc^k1^kBOWtf zrl?OmsIftc`f|P$^qVotSnnOU*Tmp*DC!pv8 z0*dAlP;?;yMHdlJG@pQ?1q2i=B%o*!0Y!@mC|W{5(NY46E+(L8839F?5Kwd}AyhOm z?k{ja;ydl;XOa}{vO7u3<1zDPimr$U8*Y`ND>+|^RmZEFe zQgkg_iq^2DXe}E>*AY;(j)0=;2`E}mK+z2Z6x~Qb(M<#t-Aq8y1_Fw1A)sg@0Y#e# zD7uw^qT2{4x}AWc%>)$PK|s-+1QgvxK+zTgitZ+$Xe%L9v?A_5=YYg}*(Vw=m!gLD zNdKOA%zT-m2jamuw@cB3oG(QWv8Cu?wiG?WmZEKJDSDJGMUSzi=yA3bZD&i-6KoVc zNkGw41QhKcplBxnMNbn@^b7$-y9g+HmVlz?2q=16zwIT=t}~Mz9OLLYXXYC zA)x460*byPpy+!7ihdxVXdeMZKN3*%69Gj(6Hv6DfTCXrC^|qu(XRv){YF61?*tSb zB%tUI0*Ve1LPhV!{oxKsJk1`Ky(dNE?8Doi@tFBCMgPQu(k)W-FXv0q5w;Y08G7U{ zMG>|XrLd*QXG>9(Ekyxaic;B96l0?(jew$b0*c}U6lD-llu1BQ6#|N?5>S*yKv9B# zqHF?+atJ7@MnF+@0*Y!7P*jtEqFMwL)h3{*4gp0+5l~c@fTDT?6dg?n6&;TIYaNjI zTXtLYw-jCLo)@j35i?(==$MS)(XCR{nDeEm30sPqvZd%)wiGpEOHp&S6dlKwqT|_8 z)PgNVE!ik)MLKv7o$inD{#+IT}*eDuKK+y;S zibfJpbSeQwrx8$eIsrwa2q-#(fTA-AC_0OPqR|8tolQW|IRq3H5KuIRfTBVIipCO9 zG>(9x@dOkV5l}RNfTD?nP*L9uzsY@0(N_D*ApNB1GWWdbq>PyPGDTA}g1!$((KODN zqUmfYDrQU347L=_WJ^&ATZ&5AQdGv4qFHPyn$1Shc?1;AA)sh30Y&E%P;>zSMe_(K zx{!dPiwG#1Pe9QE0*V$AP_&4EqQwLhEg_(2DFHT}D9B z3PPx8N`^nh0f~>ZFXNvpMN{nF_2n5c^JR)wWdxT!Bt=(oz7(xyOVQPADY}L&Mc1;W zXboG6*0QDOI<^$8V@uKXY!t00py&nyif$yJ=q3V+ZYH2;0|7<15Ky#{fTB$V6x~Wd z(QO12-A+K!W&(=tAfV_@0*dY;plAyLMRyZWw3UFOdk84Hmw=-C2%(}YGyHoUkoZM* zTeMP&M%hQS`!izZ%M?AF5xnt;6g|TEQnZaNMUS$j=rOhwJRJRR}1mNn|Gy;lFC!lB)0YzsJP;@2%MQ0IEG@5{-vk53Vhk&920*b~EP*g}j(O3eC#t~37 zo`9kv0*WROP&AQ%qDcf4O(vjd3L#X~Khv+e(5Wo#*$#g?MkY$-aAEk$$KQZ$#1qVowTx`2S9c?1+)NI=m= z1Qg9DplAUBMGFZiT0}t6Vgibm5Ky#~fTD{DC|X89(Io^FT}nXFasrAjBcNyn0Y#S+ zP;>)29sJzI*_v!&<;wiMmSM$t_K6x~cf(FOvFZXuv(BLPL52q?OhfTG(7D7u}1 zqRj*p-9bRnodgu!ML^LO0*dY?plB-rMfVU;bT0u#_YqKZKLJG#5K#0WAyjl#roYYs ziI2CxcfDGQzOnI8X3Tt$Dfy?$2eb#9%oC@cD58f!Iq*Y*;4crTZ(qDrD!Kx zik@am(KBom?INJ)SptflBcSMc0*YQBpy)*cie4h1=w$+mULm09RRW4$BcSMY0*ZDM zQ1k`?MQ;*N^cDd{Zxc}T4gp2)5>WIW0Y&cv4_k^pXG_r+Y$@8ymZC4&QuGyDioRw`(Kl=<`j(BN?+7UR zo`9ks2q@Y|K+%r`6#Ya%(a!`F?I)n<7Xpe75K#0h0Y$$NQ1m+iMF$Be`h$R?Lj)B4 zNkGwG1QZ=6py+P`ivA&>=wCvp=;KWPSO+BjxP49k6DjItkMxgZ#>|%~@~Z?Vy&^@? zD*t_?AF!n;l`TavwiKnYr6`>(MRB$iWw50vlPyJ6*eI$>Kv5O}MF|3mvI!{4A)u%l z0Y%jbD5^m~QB4AhY7tOWn}DJ^1QZ=bKv7)+is}(ibTk1)^$93yKtNGL0*V?DP;?9d zMU4reqDU2gssj?=W^hufgpbjxx#vZjREe1{Q`EdlaQSOebR6gFw&-}a6t!SWQA@TI zwPH(AYqk{SvZW}GEk*fkDf)ldyU*yT>c4IKd$MO|l7VC0P8rQB*Vp z2u&bB0s^9lfFe@Gf{Fr)y({*Hii*8~1yQj#R4gb~?%#Lzc_i_FKiBm!y=K|oOf0Yzg8C@LhNXdD4W;|VC5KtNFu0YwuDD4Ik- z(PRROrVvmxm4Ko%2`HLIK+$wUsOW?&|BwR`Ut_mLgQUnlO%$Dx6*FI^Xm(am>n$lN z;e077WlPZ{yEk&EyQnZ;ZMO)Y?x{iRN>j@~@NwDS9j`xZxcsdYtp6=n1wIJ;|1$?QAJ}iY-M?v!&=6wiNAP zOVP7zDSD2LqUQ-H+DSms3j`FsNI=m`1QfkYK+!7%6unA7(Q5=0y-q;U8w3=+NkGwC z1QhKeplCM%MQ;;O^bP?R`jjn2pRuLrbG8(H!Iq*g*;4csTZ+DBOVKxMDf*U;qWuIE zeMdmi_XHIEKtRy}0*Zblpy($8ihd@b=obQt4iZrGD*;8n5m0o9fTG_CDEfndqCW{J z`ip>~zX>S%hk&BP1QdDMdSH&C2q9GTQI?>z)y z6va4SiZa+zl*yK&I9rM;v8AXoTZ*#SQk2b>q6Axtl57;^5Kxp$Kv5L}imDP&RE>b5 z>I4+kAfTuw0Y$Y4C^~|GqS^!$)ghqhNCJxL5>Rv$0Y&u)D5_6D(a{7H9Ya7-0|JT~ z5>V8L5Gsmh`zJXd@w*I8kR3kKclWg21Gem#`7%Y#vV*fel%nRGFGVfbQq+!cr07J>m!jcpDH_3+qLFMV8pW2Plh{&pGFys9v!&=1 zwiKPpM$u^m6pbOE=yU>#&LE(ufPkX01QZn#P&AH!qVWV2O(3ACh=8Jr1QbmoplC7y zMN(Fy{JE+(L8B>_dN2q;=jK+zfkiq;ZPw2pwH zO9&`hPe9S71QcCH2o;rN`%N5>cz3%kDwU#d?cVj}*)j8Fimu8Ij{jVWuI79x+Q^oo zYuHkBEnA8nw+JZO zML^MR0*c-ypy(X}iryul=sg08_7G6?J^@902`Ku2fT9lxDEf#HDtbKI-{yeC8`@o= zC%7%LZ=cWIL0YyI(Q1lA{MF$Be`jvp9-v}r=L_pE+1Qh*2K+&HB6#Yd& z(cc6V{X;;}VFHT0gdVn|C_+F{8UaN<0YyJd;>pMavH2`D;-fT9Kj6g4EEs1X50 zjR`1fLO@YdLZ~Q~@OwBQ@yqP4P(~trq`%on9h-=mFH_Vq5fpweMXfkrit^Y}l+Tu; z)@&(i!R=nC$XjIWVRHIW=qj2Y$-aGEk&oX zrDzOWicV*v=nMji3J53~OF&T}0Y&2oC>l>d(F6jDiU=s0NI=mf0*WRRP&9>rqNxNF zok>8^Gy;mI6HqjRfTCgoie?f}G>d?u*#s1o5JE*KCj6HjkoaW#-1TrNs&BVNrHPpN zGDY(e!FNAN(R|LAq6KUzI-4y;3)xb14qJ-OWlPZ_wiKPmmZHUMDLS8xq9p_rEhV66 z839EX5Kwd>0Y%FRD7uJ%q7?)bT}(jHN&<>j5m2<6fTA@76s;woXdMAXmk?02o`9lD z2`IXZfTGI@D7u1xq78&l(cFZe`?FKD-oB1@mK5C`xN&77X1+|(HHo0jK`FYH^QCAL zTZ%TbrDzLVimqcz(e-R8+RB!q8`x5GBU_4YVx#D00*Y=Spy*Ztif$vI=yn2%?jWG( zP6CSVBB1DQ0*dY-py*x#itZzzXd3}V_Y+X`00Bi05>WII0YwiJQ1l1^MUN6t^cVp} zj}t;gS10_@4oJMM-4<<>qOY!tmhK+&rN6um}3(dz^hy+J_Hn*%qHoz!w4W_S-?63Wd$tt)z?Px| zY$^JYjiR3jDEgUzqF)FoI!Hj#uLKnRMnKUa0*Zbopy&?*ivA>^=r00_{wAR49|DRF z6Hw$O^{^d95dwQ7&7Gs<5S~DqD)Gv8AXw8$~q;D5^<7Q7rJw0OGyz4&5Kz>BfTD&36g48Cs4)RWO$aDz zN|4IAs)*=}*U#2KO8JzHs6t(7jDQd%( zqPA=)YR8tM_G~HYz?PzpY$@u*mZHvVDLRggqAmm!btRyv8v#Y#2`K78Kv7Quih2=H z)SG~!J_Ho?C7`Gu0Y&`@C>lUO(eVTn4J4rG1Okc%5l}RkfTAG;6b&VyXcz%SClW$M zt&;vs2PA&j?p^0e(G7OPG&~tIU#94!WU$V&SCHpLPv(3n8qJoXQ`k~;DqD(9V@uH( zwiKPtmZCG*QdGc}qOoig6%tT1j)0=^1Qbmmps0v|qKO0)O(LLZG66+X2q>CLK+%~5 z6ip+bXgUE!GYBXuCZK300Y$S2D4I<`Q3(M>r34hsA)sh3AyhOn=|A9r#P6^#osE*B zEPJGXRx)P3OwrlN;GHxnTFCiQbPijJ&Sgu{BDNHr$CjeSY$-aQEk#S%QnZvUMa$SI zx`2S93kfJ%PC(H`1Qe|xpy*-(idGU(w2FYD)dUo+A)sh20Y&QwD7u7zqV)t6T}nXF zWdsymPC(HW1Qcx`py)~himoD{=xRc!XnxZF%K?d>ZlAkeAVpW%ZPCVL%zT-m&B@?M z_t!zBZi}{Xz7$=@mZIy~QnZyVMK`de=ti~_-Ncrno7qxy3tNhAWuxde0*Y=Ypy&<) zitZ$!=q>_^?k1q<9s-K)C7|d&0*bZ~P;@^5MGp{A^dJF64-ruGFabr65K#0e0Y#4y zQ1mzfMNbe=^dtdA+XF1QdNpK+#786zwCR=wkwkJ|Up!Qv!-UBcSMW zLa6AOq`%w&i8r>}q8(Cnz1_S1A{jGZrs$hwa7(5Xearb$w4W_S-?63Wd$tt)z?Px| zY$^JYEk!@ErRZn26#c?R(Ln-=ekGvjHv)!zT2q?-RpeU1oqBtQ`^i|S-)d7hYyBYmj zibmTb{Yp78^JR(>Il&K=q$tVxQk27%qFlBVRbfj}RkjpWV@pwWwiMN1OHoa>6xCv* z=m-LeY7Ym7Su!_F2d5obZwU2D>fF%ZZsUQ`9ym zXqPQT?KoeG+Owso16ztZvZbgKTZ%ffrRX@e6m?-sQCGGUbz`HbI{`&K2q@}FKv6FO zih2`J)Q5ngz62EYBcP~10Yw7{C_0{iqJabyoj^d*AOea86HqjSfTE!U6b&Pw=tKgF zh7(XUf`FotgiulI9RE}YB>te?6>1|zjqTp`sGOMjGDWB41ZO9u=v2;^qSM$?G=?oj zr?aK#47L;%u%&1$TZ#(VQZ$Y&MdR5hnm|BN5dlRL2`HLGK+$9Zilz`yG?jp&GYKe~ zMnKVY0*Yo3P*hAn(M$r0W)V;{n}DJc0*XorD4Ih+(Od$G&LW^_9sx!338A8sbNtN? zNc?HLEgCIFU)!f37v#jumnk|oCwMAXiWYIc6rIPGqQz_}I-e~?OW0Dhlr2Te*iv)> zTZ%4ZOVM&RiY_9cXaxa97ZXsll7OOB1Qe|%plA&NMQaHtT1P<9B?J_$C!pw30*Wpp zpy+Y}imo7_XafO7R}xTk6#+$86Hv5~fTC*%D7uyqDq5K1f8l_{TieagIa0L7#-^N@ z`7%Y<=LE58QnZ!xrRWB>6y3;{qMO)KbTeCuZedH&t!yc}jV(pDv!&<`Hj3^fpy)0F zitZ+$=pF)!?j@k;J_3ri5m0nL0YwiGQ1l=HMGp~B^e_QMj}TDwC;>%}5m59v0Yy&` zQ1m1LMcWA|dWwLerwJ%}h7c;+lH)gbK;oV3yZ5h?q7Uu1Xh%-We3_!1IlQuG4n zOVNvLDSC-5MK80Z=oPjUy~>uN*Vt0@I$Mg~U`x@PY!tmkK+!G&igpuF^fm!S?+{S* zE&)aF5m2;;fTH&aDB4Rv(FX(+eMmsjM+6k@BcSMG0*XE%py*QqiasNt=yL*!z969J zO9G0%B7};b%kgJBAn{M^k^b{i^oM(1^y{3M`7%Y{LO@X(0YyFmMNtBZ0s@NC2`GvYP?SMHQ6>RJaRQ1e5l~c_fTAoysOZ}q{~-q? zew5u7?U$lD_7N>RH)g&}QEqPVUTrC=!ue8El`Tcp*iuxTEk!lhQdE;IMYY&cbOc+9 zYO|%N4jV;B5>Ql^fTE)aD5^(5QGEi6jwYb!7y^nK5Kz>RfTBhO6g4KGs0jf@O$jJE zmVlyW1QazVpr{1_MJ)*^YDGX%9sx!91QfL#{A&9YQBH37NPn5b6K#_l zGhe2tLvC zQ6B<|`VvsokAR~71QZP*py+r4iUtx;bOHfIg9s=ZOhC~P0*ZzbP&AByq7w-y8csmb z2m*>m5>PaXfTEKKC_0%CDr%SO_i;et%?wU^Dax_iqS3iA^JR+0MUx09noK~^6atE-5>Rv|0Y%dY zD4I?{(F_8LiU}y1NkGvo0*Yo6P*g%dQ7HjMa|kG!OF+?C1Qg99plCh;MGFWhI-7u^ zg@jPisk#0N2P9r--x+e66m75%Z|CI3%$F%zoEzMBv=p7s`BJomEk#S&QnZXMMHjH8 z=t8y>EoV#7MQkZr!Iq+n*(h2`K+!4!idGX)w1$A9wFDHcBcSLK0*clXP;@B)MVAp! zbU6V%Z=R#J_Me zdY%;hVB@;nnECRuy|m~tnY9~5yu?lJOSWF(1p}A()_s~XBa!7E%~ejca(B&>i4(It zuWI75gy+>vyr1KFbrSWfdS1Q6r0Sm6AaO@c&ufzS`3TQzp6GO>=jA099p!m#6VKN7 zypD-V4Lq+);>1Rt*CTO76VL0D_~2O28<04rh35@QOljqL!xDGpd)~;z!8V>ZI&oZk z&l{6i+|l#KCZ6x?c@q*@T|IAdVnlb(o0hn;r{~Q~eAL_XN)rwHdEUIlnFBm;Vd9>F zo_Aj2w?Uq_G|_da=PgexInnc0CSDlfd217ilRWRz#Hi7pw;^%$sh+nn@$neX+ni`z z;CWjU(+fTC=EQyDJ@59!??s+>ccS}b&)b$*Hr4YUO1w19^Bzm&6nozG#L2TfZ%5*q z63^S2_;ilvy_{(3{z;726U7TWZ&%{}g`W3r;?HwEZ*QXKV$a)`xNwQ*eU^A-ndg0# zsIuJi_9sqR;duuVn^t<>FNx1rd)}c$vvr>LS8~>R_x_J0AH2+60g>e2SGa2+lI(qz zy9y%7i#EFJAd-CTT6ZNxlGV1jYax<6?Rs}LM3P%>aMwd5Y5$sigGkc;Ir1ivr2Tu+ z%_B+s2Z8e=H@ZKZ@5QlC*!-tWP9q|18yjNYegYp+S-4 z*W2B75=q*>>@hNuw11jmbR=nixBi$&(*APvv5}v-Qk)(aw%FamAzVG1WNYcJ={CXs5U-{b=N!pig z-i;*fbMJd2N&DpKzDUwO`}J8QX`jCMDw4FvpZg<8djN4DlC*n(zeJMuA^cDzX}7_D zMZBCF+#j0g*6@#9?i}~$DAL9idl$GTH*RVi@v5BfzC|n2E_;ousb{%kRR_?Ev`;m! z>Q0v<9W++?Zgk9E;$Fb3dae6o80n!>p^#$P(3m%?JUo$wpJ~}b=M+&ylPvOYAf~gsy(FCQfYu! z%^69(vYtwVylVTDMk)>Qs{NugIZSC8^}K2s?xNepI9o5)&8t>NX|+-huSTAdUC@l9 z-Jgn8?l)=w1r7bU7s-h<%&t<&&#s+4sz#2Z?s;hqyh@e2x#W3%b){N}b8**>iU59CDM$A3oZcyCv@;2GApZhQHI?wj%Y_ca$O3h9- z?IrD39rvF*)BSRPX!Ohe&{X_YagTPtXWyIPPDzXWnVscD+%NaC?!QROmaS$NwwhQn zvsKCL@vUYTl#DMbm^r(+v}k;3(S%mxXV0HmT5Mr_(S$j(i%Kdy&tBfWbf;D`XHS_v zrF6>NBCplt;^{@L3a1s#Yt?dE@%X}Ntx6^r&Ms;-yJ$vHNnuH=qSgf^rE?}sDQ;C- zTs&?3TIaRSFUZfc*uupYGm2*vwJ0haH>E{>UduKu z?Aa~dv;Xz1R#Rq-pEhSgQLE{N<0ns<@&Eh9D4AbU@jWqVa;u)RC(M~LqqukR?4lNB z?~8e*vs3Sq@I5kYcJWmAJ}+rCVrJp&GyBb%Q83c|UM3BjHm9Uuc+d8O+x<^mO>+xN zi|oDSdEpg3an6kKc^&gxjyDPg6N)Al&Y4zPP&$8RQAx|mCd^%36Q;~4b;I4Vj_BRD zz+KGoy^E($FP`C=!v~lt_Nv3=xepvcN~hl@5(HKLt6xEGdL)SWlUfG3{*f(PHEUPD zRsEn!E4NBo)^8C6>F&w&s&(~*drhhE-yKg#y~=;TT#efQ?TJ;~Whg%(&)vC;R0}HE zAraKKgL{5zwsbGnI;iGm{cb@OyHx-8h5rwFZ&dFdRB0AeZ`7>5Go-6L5@fn-(61T< zc1TYK)$Mq6SRJO+bXREVrT&{;Cv|$$AlHtLOKLj0jnk6umUMXE{ssN=26%SN@0d5B zU|jfQ`?h6Iw(DK?Wc!YK$+jJ7JvlkAZTP&tz4bEr?uDleDlVRx?+xxbx}f)vk*&km z-G@`!mA$H@arg!W}G)hTtE=FBLWGHFK9gnI4|e(KHj*5%6Y z$7^v<@Z0QL_WQ_p7bf-co!pBR6u7h7v@Qr=L%w@soY0Tg)>E&oSNUsj?*aE>6Xr~x zK0ka-dfB$T;hqW|$}WI=hnBtOvNzI}x6!Bko#EaEdO>%Q!*`>5E#VUtE~? zGu=B@=d~+)W$yCuMqBIU+mv69-eqUx_vTHx3$8OvK!uN!|5G0w`V@_uGs$xwQfEvm zDkz#UVM^hQf@#GwCWXI2ca^v|?>+`qxK4D@+Lm8hcm0PiUiRAqT3-3@u2b3XB;OhK zPUw3|LC-$JQ|Gy>R=-I{SWor&*O{JOqTze@s&^)U*7;^}#|LJ+BN0Z#=(a*{jMg_lFm_ElKo3eMIdq?o%aM&m%e3ZyK6wNvHTKn z9lQ6Co@dwP|K#HcJq#(ocbd8;-Srz@{Bn5i=E+@z)Fn?n%fZn_avxmuRM~sUp$^Y? zx6gJ%IXirp=Z6P}s$P*fSFvXAKQ&tU3B z>J{a!>i?pz_N_adqdr3!6IGeaKH8xjOURACB;~R?t$8!@Y66Z}Q!p zl<)=JAAUVi_Abm1>Da}raGRg6GaQ-ncd&b^|BzAjdUxtn&mN|=%&%t;)bcvEZd$R9Ze&(F66mtGikzSa2^n zapv51ElOs#n2_JzmBQKMCwFxZ`{s6RF}>w<_rS5)gp!%fCeEzaVp6>pLtEEt;U1}U z9q%qci;2^VN=gbR6}6aFG-FcfGk?fA6GPCg1fgplFx{w{s{4zj;8+bko9Y z_o*@av=G1S(?5N(Yc5S+7F-a$&|jXmI^y;0_%$Q7B1c4ON9siCrX3w=X`d|mk6#s2)cf&p#b^8B=d{X_uTNGH zeEV!dgB|Why(mPwLw5)Q;73tYt^{%=&h8@1`c|=EYvleWfXNbYEXe9ee3GOvh0=y3aAC zonR0u**XwwXeUj4c$8~(mUG=s<(($1C4cLyjPuttEhWowP@faQL z^QyM{>Uf&_J=mV4<7RhN+rC4`FWfu8_Rl&tckpa?(s8!?a-Ho(IzHq+t84pN9sfBZ z+?8sF$3E_hdG`DhbzE^&xUbOhb@z_7=YODM^#)aJ!FMpSgUmY9n zgF3cs5$@x3EOl3uz5HSwAIT5*^E!HM!=0sLKX--N%a71;Wyf$|spFfS!~KztHQg0& zFW*qdGrEWSOdYrO4EH@ce$zYLzv-CQFWg;qoI4=gOLTl}V7OnP?T6FLqU8tzd# zu0Ao`SL?WIM7TfJ@raYc-B`!5qr*L2#~V)#_kB9<9~181b!=S_?(RCyD-8EC9iMQ} z?fvnRj?szX&e3t;SPwQ zj(gl!fbIJEQpb8*!rem0iPwj_M91522=~J}{&Z8g59`?R)^PXL@!Z?PeX))^?hN-E zI>zq_cMTnf-52iDb-euka9^+E-Uq||wT?$W67E(yPJS%hb9B7(iEuxv<1gF89eFA| zc77&2_Sf;eXT!Zp$LF38_ggwvelgs&bR7P2xC?aL@M^ek(DB39!~Ly}4c-cOzK&CO zhx;rY?|vuTkL&oW`&zeMKmMNZ*kx~cJYL81KMeO89e3^v_ii1tKMi+n9Y=m1?m``} z`ZC-%>A3IfaDS&`qy6D-qvN#i!#!Wedk=*BNgWUU6z<^X@YwBOcsxPJrN4!HosKWM zue96m?;RbJe}(%<9Z&iv+~alJ=%ip5oC+@59wtvvEiTmn`?RGlOh=u!X9k;nJ z)Z6o)((w=X6?@w;_ak$5?BTw2Z^ywpUf{llZ+pFtFS{@1+kQ{ST=!Ld+ehg*+I@N7 zc9D+Py07!wzD>u^+!y?9|ES}!?koScJLovGUbxTE@d5X}0QUT6bga`T+)Z`Nvt!_S z-L(hWG46RobR3~RR>$c&F3|Bp9WT{!i;j2d_^6IMb=g?cfU{FYgsaXdTHS}cPyP99w+mZdmvuwwX{dRUdwSMC0=?yC5IeYrgMGXME@D}Gttt~>kH-2Lb7 zzIr{}fA(vCw}>~)9nFHhjQwYCZ-D!c%ix}L-_PUj$2w2^;;B9^RD6A1x<|a_F4*fc zN4&m~?rF|(PkN^`jks?{vZumdJn8Pr{OjdjI5y&S%i`RF#3l(2qRrmVrda}#s{s@-6z8l@s zc88^4_B{K~-9`A<%RSyD;th0-U%cECF4)uj%IF%tpV{{NuwU*j z!@n+HoeIC-D(-pweqVA=JM%N$A@!@Hdwrc5?#SD+BY#%x*`@B~dbn7_J#DvN_WJDo zZtoNR47n%0ZO-%mlb4+Tc)8~8^1W{-=ofFd{Gqe^w0z6rR_?1N?K|eRwofm*Pmko~ zSNMPX_O5ko+p%5idiHB0^?{zt z`_<@Iw_ony+(FMC+R2n|csj4_>F7ZB5|K9# z?aX`M|8v*lUmaNNC9C&X)j8qKb$?#N>n9q?b?>Ok_LsA^t@vJb7b-21zQ7*8Mlx2p zj}K{S!Qq%4Vi&mRS9cdUZE#KZc*uPrI;iEq`St@CX+vv`O{G}ORz^_U{ZUWLh_!UD zKN=0}vt((}*cxv%f{J zv3@e@C^z%HXcNu4ZnpNKO*M~nvyJ<+186T)2!`gJ1^Q?^9VQFyTANVvzD73 zyl6|!nr?RVqOCM*xY^15{Slhg-OP6vD_^^sZFjj^Yge`HE?67wDz@DvYpb1W+g-GF z+Bvq}WoxgUwCyfj2knGycj-E6XWMocuakC`ZFl)PYgcx=wYz-BX;-rCE?*bzxNUd& zx@u?Ic9*Z4c7|&h1KaNM_0o>oc9*ZWwr|^AzCPM%Zntrl zudjB*w!3`&v>k(tXtaU(niS1+6Wn~jgV8c5pt?FLQd00 z$QW&eoUVppB5R+6XDsM#wmAgpAil$OLVK6lo)5qBcS%X(ME^HbSOoBV?*J zLeA6#qOIyW9;;bYLiClDmb9PK%iw6EZWfZ;Vd~nWa-DWVWV+lxRvwsiuU? z(Ug$6ni6uBri9GXl#uzF60$%OA!lnNWT7@f&e2B5x!MR>q>YgCv=Opc8zJXwBV>s- zLY8VHWSKTXF3?8Eh1v*Nu8ok3v=OpG8zC2KBV?sELRM)bWVJRz)@UPSt#&A6hM(nb zGBR&;AEctip^%Rqjp(|V$uS|91@=P|DIu5ZR0+94Q$jXqO30O(5^|NMgj}sDAsaO% zE}jgYO{2)RKUAvbCx- zc}p81yR;FqTN@#7Ya`?xZG^n5jga@W5wb@+6!MUNqPzYxGwn9y;ZR6lyHE0d%;cDm zj{^H)tCWy^I#ohG)|8M>G$rIyO$qr-Q$jx1l#nkpCFDy@3HeG>LcZ2S$T!*u`Bobt z`?V4Boi;+g*G9+>+6XzIjgTL;5%QBZLVngp$S>LmIjD`0U$qhPn>IoYX(Qx!ZG`-x zjgUXJ5%QNdLjKl9$UoW$IjkKD`M@uA*MH_NyYKN~N=W=GyA5$)Bs4nqlb_K@U_XkN z`uX7?qOnA@m+4{-PI9osYS&6Nm{H)B@Pkv^x^^>33Y<}`H zLEtAplLUV9Gl#%We&!PR$XB`4R`FSLPpZu&#;3q$iBJh)+^$7grXMF-c`FS*fpZq+Az)yZQAUGgd z(P&!4f5ZWaZ?n56ek4?M$URVwHjKoKmnmu*3G7EXQ;Lq|d?{+imZIitDQdx%qLyqa zYQ>hKJhl|&v!$ptTZ-DSQPh@zqILunwI`sc0|7-H2`K7BKv8D`ijE_os0#r_T?r`a zMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+bUYzc)Hss*-jMhfyD4fS zMXwpDfsvT`GDSn&&yZA=qM@8GMZ?%qbRt`dhO?z;1Y3$mvZZJgTZ&F%OVP<}DH_d2 z(J2HJok~E_X#^CFA)x4V0*cNcps0X=qOk-N6%tT1j)0=^1Qbmmps0v|qKO0)O(LLZ zG66+X2q>CLK+%~56ip+bXgUE!GYFxgK@q>70}|inW^}L=9cQG9-M78iXIh=2l1N}b zN}jqcD&>4Bn!}c&xojyqi!DX-*itl~Ekz61Qgk+3iWah^=o~hR&LyB|5dlT#5m2<4 zfTHsWC|W{5(NY46mJv{N0Rcr95>T|9fTD{CC|W^4(ZvK5tt6mm6#+%72`E}aK+#$P ziq;WObO`}P>j|NvSrLDw0}?;WJ<^WOmZH>;TwfZAnJ-hcArjbMMUYZ-CFe`gRctA` znk_{e*-~^3TZ*n_OVK8_6m4cp(H6E8UB^bz^#l}cC7|dA0*Y=Vpy(z7if$&L=oSKs zZY7}THUf%nC!pvK0*dY=py)0FitZ+$=pF)!?j@k;J_3ri5m0nL0YwiGQ1l=HMGp}| zMVCkXHyx08AN$nr6;d?C?p;3|iJ31`^mrt&zse$|=n2l3q9@r>w4E(QPqC%wX|@zS z!WIj0Y$$NP;`iZqTdN9 z`h$R?KM5%Mi-4lP2`Ku9fTF_$6nSZ7kMb+0z8)1JpeT(HD%uzE&u~EEyWH2}qaRDr zhjv@!r^U>dDT<{9_E+ho6lHL}6lJodD9)CmN^B{r%$A}owiIQvr6|Fcq9j|2a@Z)! zC7`GZ0Yy~_D5^$4QFQ`}Y7kIVlYpXH1QZ=XKv8W1is}$hbR+>qbqOdsih!be1QgXL zpy+4F(FhGr1@JNkofub3B~lZ@R9y!c3adWEoQzq z9Y;V>7Xpg95>V8QfTHdM6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF4IrTCcmj$B z5>Rvk0Y!rdp`v5c{BInPc)t5So@g^E^6ioS;Ix?eGDRn*1@>2YrEZIcbG{UfU`x?R zwiJzGOVLSeDLR=gMWfkLbP8LFPGw8cX>1gYA)x4V0*cNcps0X=qOk-N6%tT1j)0=^ z1Qbmmps0v|qKO0)O(LLZG66+X2q>CLK+%~56ip+bXgUE!GYBXuCZK300Y$S2p`xK_ zex3sopJlg2!=$LdKBCP|i6rIOL(P9FM&L^N~2?0e*2`E}dK+y#R6kSL_(Q*QcE+U|41p!4D6Hv60 zfTC3d6s;zpXbk~HYY8Y?M?ldf1Qe|&py*NpiY_Cd=yF1+s5H%=>wv`VXP%;Sr06lb zExIBtX1+|()oH;MO{8ce=S$HwY$>{yEk&EyQnZ;ZMO)ZXbRAoYu4hZpR<;z~z(&!H z1QgvwK+(+v6x~8V(X9j&-9|vs?F1CvK|s-+1QgvxK+)X<6x~BW(Y*u|-A6#tHUf(7 zC!pv70*W3apy(k2iXJAQ=n(>n9wmf|u1xbEb3o#2BM#10QZ&kLiyljhnJ-hcJuR@m ziZXRu^c3ey(bH@xdWJ1UJJ?e6EL)16V@uKVY$@8wmZBHfQuHDlMK2Lh^fCcOuMkl5 zDgi~W5m59x0Yz^RQ1m7NMQ;&Mw2OeE-2@c9O+e8*1QfkXK+$^y6zw6P=zRi;_7YI^ z0RcrH5>WIJ0Y&==p`s_!{Iq6H(dYI^|4Au2#qM2yoE9@*rs(su!2T-Jl%g*DEf(jqMr#U`h|d^g9H@) zNq zr4dl%6HpW-peP`Oiat&A2RI<{v36VZnG_wck?zOLmnn+-f&EpuDMghyUy3TTr6`Ln zMcHgAO0cCU$(EuVwiM;ErKk#9imI|vRE>b5>I4+kAfTuw0Y$Y4C^~|GqS^!$)ghqh zNCJxL5>Rv$0Y&u)D5_6D(a{7H9Ya7-0|JT~5>V8LfTG3(6g45Bs3`$O#}YzC8NR>T z0f|3m-!7EthmZ94*lkfWKW4s6Q7b>Nze+i!D39}{D4#7wt=Ur4hAl;H*;3SwEk*6w zQq+MhMIG5v)QOFv&IA-4M?g^*0*bm4P}GfpqV5C~^&p_ACjmvh2q@}JKv5q8iuw{z z)Q^Co{sa^aAfV`Y0*VF_P;>$TMS}<^8caaZ5CV#Z5<*2Se1De%5)A=rf8%e*k8q+QZ$P5rRXHK6rIeLqS0(AI)yDor?RE!G`19tVN22JY$-Z}jiLeq zipCO9R7gP4I0A~s6HqjPfTAJ-iY5|JG>L$s$pjQlA)sg~0YzsLP&AEzqUi(_%^;wt zn1G_01Qg98plCJ$MI{6jl@dZl!+rmVwocJu_dScz5mL0*K9N1gkC`u1G~W;GuX0Z* zTEO{IbT(Ux7P6)29JUml%a)==Y$-aAEk%pjQgl9Bik7fZw3L9NWdsymKtR!j1QabN zpy(n3idGO%bTI)%D+wrCML^MN0*clUP_&kSqIComT|z+7dIE|rC7|ds0*Wptpy&z$ ziZ&2XbR{8Fbe8XrbwJ{S?Y3y16b-eHXjl0$^JR*z^#l8-08)xJalRC7W=qi)wiI2* zmZIy~QnZyVMK`de=ti~_-Ncrno7pJ3g@B@42`IXafTG(8D7u4yqB{vFx{H9Ky9p?| zhk&Ac2`IXcfTC>#6x~li(E|h&JxD;&Lj)8(OhC~i1Qb0=K+$6a6g^Hr(G!GF(MI3D z(E*9KHbvJ+QD+-Z`Z4omik|TU`==yQigs|m6g|t9qUYFB^gLUNcCw}D1-2Bu$d;m) z*i!T|TZ&#`qv%xvie4k2=yd{$-XNgpO#+JEBA{p&0Y$qBD0-WKqIU==dY6Er_XsH3 zLqO5{1QhKhpy&eviasQu=pzD(_7PC@F#$!N5K#0fAyo8~@9%d&;#b;d9iNt>u6A4W znIAJ>rsyj_uz!jqrRZzUm!fajQuHlbiuSXm=sUI)eb1JnAJ|fKfGtHovZd%JHi~{G zpy(F@iVhM`^eX{HzY$P$h=8Ks2`Ku5fTBMMDEfMy0}Y`b@z8I74QQ|%~Y8?%(>?uWUIA4m|vZbgUTZ-DV zrKkg2iaN5Ts1sX?IQ6w?00N4RC!lB`0YxVeP&9~uqQL|d4I!XtC;>&o2q-#{fTH1qP*Gmgf5HKY zFL5)PFGYLpwrE5&X1+|($qEpyXbShhlPGd{a7`7Ch&X%Gx*iux$ zmZGt2DJo>6XdD4W;|VC5KtNFu0YwuDD4Ik-(PRROrVvmxm4Ko%2`HLIK+$vpie?Z{ zR7^n8Oah8#5l}RnfT9utib@G6nnOU*Tmp*DB7}-YMg3?Wr)ao+1>__t+HSW+^P(~H zWr`L?1N*1gQi{&ud?`AYEk%piQgj|$iWak_=zO*mEn!R1QnnN=V@uHmY!qEcK+$pn ziY_9cXaxa97ZXsll7OOB1Qe|%plA&NMQaHtT1P<9B?J_$C!pw30*Wpppy+Y}imo7_ zXafO7R}xTk6#+$86Hv5~5Gq;_^#?j2@f!Ah*Jn%7KlW`R*F6y3;{qMO)KbTeCuZedH&t!yc}jg6w)2`IXQfTBAID7uS)qPqzw zx`%+GdkHAIkAR|W1Qgv*K+yvP6g@~l(L)3jJxoB+BLoyZNx4zf}7D*;8n5m0o9fTG_CDEfndqCW{J`ip>~zX>S%hk&BP1QdCJ9=4+> zLO@X(0YyFmMNtBZ0s@NC2`GvYP?SMHQ6>RJaRQ1e5kf^@NBug3ouWMp!2T)Pl%gEYm!e#@6jfnMQB}4SRbxw0b+#1MU`tU=wiMN3OVJT*6xAl6 zs15-|M-os}mw=+92q>yYKv8`HijF3r=okWu8W2#_kbt5_1QazUpr{D}MNJ7PI+lPU z_YbiB`#VFL6HwHGfTETJ6uEzvEqom)$|Hn|vIBpd0}?;VzVA8_gpc$G*$q>E5Hnw< zs9g})KV_U!)SmODr~_MyIPJ9Pe*%gI5KweH0Yw7|C^~_FqCo@{4JM#y2mwVy2`Cyy;I`;Q z0*ZzcP&9&oqLBm?jUt4K+64a14oJMM-JxzPMGxCJDTtXbQ*>$&*gu7xQgj;UOVJp% z6rIkNqBGc1RKS*^v1}2ii!v*nn*y=Bm#;i6HqjTfTF1c6rD*x z(KG^zrV~&!gMgx90*Yo5P&A8xqS*u#l@L%=NFuk=S$IIwiKPumZBwWDO$>wqGfC; zx_~W37qX>jIa`V@VxwpU0Yw)RP_&YOqE!SGttOyo4FN@K2`E}eK+z=x6s;$q=u!fT zE+e4masrC3AfRXi0Yz65P;?amMOPD0w2^?KYX~U1mVly7giz5rf#22viI292W#>xK zw{}~!If$7rQ?xY*Mva!D8#rHzZe&Z*O>8N;nJq=Pu%+l$wiMmQmZIC)QgjDfitc2i z=q>_^?k1q<9s-K)C7|d&0*bZ~P;@^5MGp{A^dJF64-ruGFabr65K#0e0Y#4yQ1mzf zMNbe=^dtdA+X*Ooih!c02`GAofTA6QP|Bzigj%yk3f)ch8GH8^p|)DS9CY zu0B&zuf_eyMG+Qi|&-7UiJ~~n;>SsOwsp2@bMTa`hoMM=m1-a zeq>A0Pi!grnJq=Xu%+lATZ(>VOVMv^DLTYP(eDHl{Xsy{p9B>BML^Nt1Qh*4K+$0W zioA3^j6qR^fTA=4ihKf!q68EL1QewcP!uDeD1(5aOahAH1Qb;wpr|qdMOg$CWfMY0 z`vX7ybf?I^?i&40iVoVt{zQ7re3_yu=|STHDXPl(QdEsCMb+6-RD&%=HQ7>Bi!DV* zu%)OrTZ-zirRYdDis}+jbQA$a^#~}cPe9Sp1QZ=ZKv4q%iW(A7)QEth#sm~KA)u%! z0Y%3WP}GcoqUHn?wIHCVB>_dP2q?-UpeUb!qSgcywIPIxa?<@l4oLhdyLX+N9zN1< zY!Ca}rpL^eDe9OWOfQt8PMj}Ao!L@!99xRIu%)OgTZ+1|rKmewih8i6s3%*Bda+T| zn}DJ|1Qhippr{`KMg0jV8bCnN@dOkNB%tU70*VF^P&Al;q9Ftn4JDvx7y(5m5>Pap zfT9ru6pbXHXcPfOClOF|G66-S38A9)>HZ}SNPL&wFX|vgm2I4o9y4F2==Aj9zVT9Y z2Iosr0b7d3vZbhyEk)zlQZ$||MHARkRK%8|iEJsF#75C%0*a;(P&Ac*qB997nnpm; zbOMTI5KvT1K+#MBie?c|G@F2;5(0`!2`HLFK+#+Riq0aSXdVGY^9d+gKtR#i1QabK zpy(VzsOYqG|6Kn;tV?rs(|i;P)aaTEh8Kw3IDH%h*zM0b7bL zWJ}R~MJw4TT17z7Y66PZ5Ky$1fTDE-6kS3<(Ru=kE+wGoG6IS& zC!pvG0*W>eP;?~$MOP6}bTt7*8wn`7hJd1L2`Jh`K+$Fbinb6?bR8j7bY8k&ccN3& z+3rv;mZIsY2W;sv^JR)|N)NhEmZF^Z)@x4-!!H5CKIG6HxRB0Y#4zQ1lo9MUN9u^aKG# zPZChHoq(dJ2q=1*fTCvzDB3|l(X#{;Jx4&%^Mp{*4e9;_2PB?jpCYqMhk6 z^JR)&P7jt%m7-TTUy5F3OVMj=DSDkPMQ^aB=uNg1y~UQIU2G}Z&6c9K*(iF4fTDK^ zD0+{8qCEr@y-z^VUIL0fAfV_&0*XE&plBZfMIRGT^a%k)pAt~?839F~6HxR80YzUD zQ1lf6MPCz8^bG+;-x5%?pAaf~G2Oq_0g3Omk7zGRk^A?&+yl1snE5hAKc)vSO_QRZ zIA4l>W=qj8Y$-a(mZD$TQuG^JiVm@*=y$dh{lS)^KiMeyi-4lP2`Ku9fTF_$6nQZ{ zY)4UqfTA=4ihKf!q68EL1QewcP!uDeD1(5aOahAH1Qb;wpr|qdMOg$CWfM@8AfPBo zKv51MRP;l-f4~8We_}U32c+nC-;LZ@%zT-m>aifFSc+7C|BiT|^mn}s{v8AXU8%6aAC_0*eqGJdsYCu3yLjsB#5m3~afTAV@6g4HF=vV@Z znh{XcoPeSh1QfL-pr{oAMR^1izMZ*aw8bLtO zNCJvR5m0mz0YxVhP&Ar=qEiScI+cK;(+HuWPBDL>0}^-tP_+A}_@w9uyDb_MiPaYfTGz16qOKAR7yb690H2w5>Rv&0Y&o&D4I_|(EwqIA4k` zWJ}R~MJw4-w2Cc7tJzYthK-`N1Qe|!py(0;iq;cQbSVKvml05O zIRQmi5Ky#%fTAl2D7uP(qN@og+DJgrH3Sr0OF+>k0*W>hP_%`BqU#7Kx}JcdtppU^ zKnN8riTN3GouVynMwd#_i*{H0##qdJnW9@`LDP9sbQ|YO(d}$0x`Qo6ce17EF18fi z&6c8j*iv*aTZ-;uOVKtqitZ<%=m7$X9weaXAp(jXCZOmM0*W3bpy)9IiXJDR=m`Rf zo+O}XI{`&c5m59r0Y%RcP_%=9qGt&xdX9ji=LsmEN^M^Pf@%QX! zV{eh7v+cI%rC7{-nWEQXLGc19dY$v7=nb|My~&oMx7bp&i!DXF*;4d2TZ-OcOVPV* zDSD5MqCEr@y-z^VUIL0fAfV_&0*XE&plBZfMIRGT^a%k)pAt~?839F~6HxR80YzUD zQ1lf6MPCz8^bG+;-x5%?pMaw82q^lVfTAA=p`uq}{-q8`e4E`BdR2Ex zqF-Xc{R^e&Am>ZbuWTv$jV(oo*i!U6TZ;Z*OVOWfDf){oMSruU=pQzU4iix1W$0l$ ziXsFQr4dl%6HpW-peP`qD4l?!7y(5Y1QcZwP!uPis1gB1l?f=yBA_UnfT9EeMM(mR zatJ8OC7`GZ0Yy~_p`xE+{vHP;zQR81__Gw%Hd56xV&=;f)yfF|JXea2;Cv~n&6c7% zY$-aDEk$+NQgjqsit4eYs6JbYj%G{IF>DkyAfTur0Y!}nC~8bVQ4<1+ni5cSECEH$ z2q7lAfTut0Y#k%p`scY ze!WFb(Vg}ckeV6cBmF%4h}JnHX1+{Ow~V0YVkzp*`BKz_Ek!-qQq+qrMZMWl)Q2ra zec4jfk1a+0*-|usjiTcTC>lsW(Fp_;4I-duFabqF2q+p#K+!M)icTb;XgC2yBM2xO zNkGvk0*X!|py*@*ibfMqbP54QrxH+f8UaOP2q-$8fTA-9p`tDs{zL~Pev-lIDn;+u zZBao+%zT-m@fpE|OQdK5=Sxu$TZ$&KrDzgciYBwAXbM}3rn05zOtutFV@uI=Hi~8t zP*hAn(M$r0W)V;{n}DJc0*XorD4Ih+(Od$G&LW^_9sx!32`E}XK+)L*6fGp6=o|uy z&LyB|5dlT#5m2<4fTHsWC|W`Y6%}Uqw>u#5EW0Z-PKp{Csihe)^JR*bX9TY-lcI|_ zUy4?+rRZX|6s=@S(JHnSt!7Kn8nzUzWlPaIwiI2$M$vi#iY_If=rRI|E+?Sq3Id8Y z5Kwd_0Yz64P;@l`MH>kyx`u$FYY8aYL_pDI0*bZ}P;?yuMb{Hhw3UFO8we=6k$|F` z2q?Ol5GuML!~e+viQgG5&=y?K)b`ntZ0s%!Y5>WIK0YxtpQ1l8RRCHU0-_Zey z4{TnV&=;fy_pf5vO&td)X-ZfPkV82`KuAfTDc_6n#uU(I*5HeM&&lX9N^|PC(HY1QdNqK+#tO6n#xV z(KiGXeM>;megcZVBcSMe0*Zbhpy&VrML!Zy^b;Xe^m>MWt^?w}issS z`2-Y22`CB(C`u=wC`Le01_4Ex1Qf*yD5^w2QDp*(vIr>3CZH%mKv9x_q8tK>atSD^ zLO@Yf0*a~;P*k0Oq8fxy(ZLLVhXWGdVK+a&N>R*4&CHnjGDUSVgU?q>(UF`lMRnOy zbQD{P>anG$K3j^8W=qjAY$PapfT9ru6pbXHXcPfOClOF| zG66-S2`D;+fTB|gC_0URqA>&%olZc}83Ys+5KuIhfTBV|sHl6UKgH%A3%zT-miJ8Hy^-?s6^QCAqTZ*QzrD!T!iq2$9(KNOcO=nBd47L;%v!!Sz8%47S zD4I<`Q3(M>r34hsA)sh30YzsKP&AK#qWJ_AEg+!iYyyfF5>Rvw0Y&E$P_&4EqVotS zT1-IE`2-X#A)sg}0Y%FQD7t_UDw>e#U+#d!o7&A!krdT(cax$QX2#5yDY`f_ciZ&8ZbPWMT*Ah^)iGZTb1Qcx{py)aRimoT1Xe$9lHxN*CBLPJ>5m0n90Y$eE zP;@H+MYj<`MHglIdmWH?UpJ#Gq^Q3=?7uxTX1+|(-I>APS4h!4oG(T9vZd%gwiIn+ zOVRyoDSCh{MGvy2=pnWgJH+XeR+hFAz}lA^}A&5m59p0Y$G6Q1mJRMXwQ1^g1C_bZ4f2 z^aiKsCi_I=T~gG@9;3aH88cs|Xm@7N`zk4VoAagU9kvv`%a)?|*iy8IEk*CMrD!i( ziauaV(T8j)`iPC9eFPMJOhC~m1QdNrK+$Ie6n#!W(H8_1eMvykR|FJ&O+e8%1QdNs zK+%2zioPSD=z9W+ejuRe00Bim5>WIL0YyI(Q1lA{MF$C?qPH^r$qq<-t9_T+E-Bh) zUz+_jGiJU_(I1(?MH{8)PtKR3zt~drH(QGSVN20rwiJ1BJ#v?#2>X8#ci+)b)p6VI z_hiq`z@*G1bU})ufItepN-rWPO+*1hfY1a2Noa}+0*Z)&VnM-**hN(AiWNmg#oiTr zSL~=L=l7j`UrBu4^{jLLc-J~vOLy)o*~yUkWHL!ekfJoU6!~l^in37@5Kxp(Kv9f< zq8bDg)g+)OPC!ux0Y#Yv6lD=mlubZUf`FnV0Yy0k6y*|7REvP3+5{BUA)u%(0Y&u) zD5_6DQ3C>s4k3h!_Sf{cIw0}>cE9LPDZ1EhiyFpb=F1c{i3cxVEk#W^Uy7QsrRXrW z6dlf%qULNVI)W`lN3x};1zU<*vZbgM8%0MEP}G`$qBaB+wI!e^kAR|l0*VR``sLnxc#Q0Xg?{s#YRay zX1+|(jCe3^vlPwbd?`AWEk(1~QZ$<_MRV9vRLYj3xojz#$CjcpwiK1KQB*-d(R>1m z77$Rhkbt5^1QabMpy)ILicTk>XbAyDXAn?yCILlf5m2<0fTCpt6rD{#(Q*QcRuE9M zl7OOf2q-$2fTC3d6rD#16-|r#OC6B-ZoB!JE=3LPBiibC%zT-m3**6cTcl_$=S$H# zwiI2&mZFQx&Uue8QikjMI`gg`-=F1e_6A!+;Ns6{}z7*ZdmZJOEQglCCiXLD~ z(SvL$dWbDW53{A{5w;XP%0|%+0*W3Zpy+V|ik={#=t%;Ko+6;=X#$FN5>WIE0Y%Re zP_&DHqUQ)GdY*uy7YHcYO+e9$1QfkQK+($t6zw6P=oJErUL~ODHA1N9uDG9hvs3h! z!MR(Cl6G74dOT*nOwrr%pzW$d;my*iy8YEkz%* zrRWnjiasTv=raO}J}02)3j&J1B%tUk0*bySpy(R{ioPYF=sN<6z9*pQ2Lg(IB%o*? z0YyI%Q1mkaMZXYG^eX{HzY$RMI{`(15Ky$A5Gr~z?vHdp;zb7MEh(C6AKw0q$IO>0 z`X?Tg-!4V}a=sKDWJ{5kq0iiJ;(cf`@g98$O&2EbhNYQ2PY0<_RG4o}L4$BB0+$u$fbG{TcXG_r$ zY$-aDEk!NZQq+E!G4o}LW@Q8e?vbL|oG(Rl*iux=mZG_ADVoQYqB6D=m9wR&f-Ob!*;2HCjiQAF z6fGj4XfXjrrx8$eIsrvX2q-#(fTA-AC_0OPqNM~BEhC`lYyygw6Hv5*fTEQI6rDpr z(YXW^tsRv<0Y%pnP_&tVq8kV(+Co6ljRX|kL_pEa1QgvuK+&xP6x~KZ(d`5j-9bRnRsxFd zB%o*;0Y!HaLPcvc{A~_M{0;jK$T}$+XCKk-&WM>WQ*>WO@XGyCbU)`y(F1HLdXOze z53!}_VYU=K!j_^(*;2HFEk%#9rRZ@sik={#=t%;Ko+6;=X#$FN5>WIE0Y%ReP_&DH zqUQ)GdY*uy7YHcYO+e9$1QfkQK+($t6zw6P=oJErUL~ODH3EuWC!pvJ0*c-wgo?Ij z_`f?K@zw_CUMc$CZj0W^h?y@_^j=0#?;$CApYx^Y1GW@>$d;my*iy8YEkz%*rRWp3 z6n)B;qR-e;^f?_cW5m59s0Y%>sQ1mSUMc)xn^gRJZKM+v#BLPMG2q^lA zfTEuXDEftfqF)Ip`i+31-w7!CgMgy_1Qh*AK+#_W6#Y#I6}^+;_i#Ys-`l2L-*-{i`OHsg3CZH%mKv9x_q8tK>atSD^MLR zfTBhO6dg)HQDXv%nh;Rbln^TVH^V>M0g3-^zcb{Z6t#0ti#E%QnJ-gxL}svghZG&j z`BKz^Ek!NaQq+nqMMtrvs5M)P+OValEnAB6*iw|wMo|F)MTG2q@}E zKv5?GiaHZe)P;bet^^cyBcP}|0YyCsDC$W-(a{7H^&+6CHvvU`2q@}HKv6#eiuw~! zG=LB)Iy}?g<$%OLv)iKPnc-*pT{GPnm>Dx)rf5iJ@b%+TbS&pf(NMM&4P#5uacn6% zo-IYg*-|uuEkz^QQZ$M!MWfj$I)Q+qF$5HyNI=n80*X!|py*@*ipCL8G@gK>2?P|K zLO@Xw0YwuDC@LnPXc7TMlL;uALO@Xo0Yy^@D4Iq<(R2ceW)M&`lMpHzoatvj;S>e- zRmWqb$bR8W^wi9l`7%YNnL++jQZ$$IrDz^oiptnhRL+*73bqu@XG_rnwiGR7OVJ{> z6fI_>=rjU~PA8yf2?0fC5Kwd`0YzsKP_&eQqGbdWolQW|asrB05Ky#|fTD8|$ zW-x!J6kW>sQgj(xiY{kM(FV2@UBQ;3E7?-Cku61=*iv*ATZ*n`qv#p}imoM~=sE(5 zt|y>qGXX_65Ky#*fT9}-D7uM&qMHdQx`lwETL~z-jew%t2`IXQfTFDg6x~Tc(KZ5# z?joS*ZUTz#A)shGAyjm6rhlaa5}#&YbzCn+-`Kb}GiJU_(Sw=6!_P|5L!2)~53{A{ z5w;XP%9f%XY$dYXWuodgs;LqO591QhKepy)XQik>H+ z=mi3bb`wzaA^}A&5m59p0Y!TVD0+o}qE`thdX0dh*9j{o8BhHtiy=*D^m@P%0u%+lzwiJEF zmZHzuQuGB|ioRq^(N}B~eN8~oHv|-YOF+?g1QdNwK+z8b6#Ym*(LMr-ej=dgX99|T zA)x420*Zbkpy+o3ivA#=Xg>i(e-cpi7Xd|o6Hs)3fTDj0DEgNWDtbTDKhgn-=h{~t zKaipU_L=^{%$WHyMSfN=Xtxwav;O;;e!!NZbhZ@5*iux3Ek!liQWR%PQ3hLzGTBm; z#YRy!0YwP{ijo8rlUO z(Le%<1`$v+m=G#DGRwc)0g1OVI4z`Tl6`nPCM#yXOwq8c;I%zcbR6eP(eZ348qSuY z5o{?M$(Eu~Y$+PemZB5bQZ$AwMJKXRG?sv(lL#m}nSi2k1Qd-YplAXCMW+x@R7610 zL;{M62`HLGK+$9Zilz`yR6;<}R04{o5l}RpfT9@$6wM@{=u`rVW)V;{n-D5GHp}1d zfW$Ah+oGXTWM3wV&dG|IFH=;O6*PEFipn`(iYnMrG@mU+3)oV$kS#@v*iy8ZEk&oX zrRa3F6fI$+=nMji&Lp7dECPy_5>T{^fTFVrC|XWH(Fy{JRuWKj4gp2y5>T{?fTHsV zC|XTG(fI@vts$W30s@LIB%o+50Y&QwD7uJ%qKgTkqPbcA(GEzwj(yc}o)oRK+oJVZ zG4o}LF3$>z-jJdVoG(RJu%+lqwiIn-OVK8_6kWxZqN~|bbPZdIu4PNnb!-$}Pe9RT z0*Y=RplAyLMK=;qbQ1wZHxp2F3jsy95>Rv-0Y$eHP;>_YMOz6dx|4vSZ3GnEML^Nr z1QgvvK+$#ritZ(#=sp69?k9wbF3s{+I3V%o?W>NLNzq&Onf?P=G4o}L9?1%}yd_1C za=sMpU`x?sY$~zX>QhKtRzy1Qh*CK+!=0io9%nVveE+Ayo8H zmY;mrDZ0;Yi}p&85TZ#(VQq+zuMeW&A)PXHU9oZ=AL_kqz z0*bm2P}G%xqHY8fbtj;x2LVMr2`D<6fTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$ zqCo@{4JM%I7y^oh5Kwe1Aym{V+u!7X#CO|Q9gmWt9!6?tcFcU4qT$)WqkE-j1m{c9 zNVXJ>VoT9zwiKPfmZC9iDLRoYMPu1gbP`*NPG+NM905h+2`HLCK+!1#6crIrG?9R! zVgiaL5l}RlfTAe`6qOKAG?jp&X#^BaC!lBs0Yx(jC_0sZqFDqK%_g8|4gp1_1Qg9B zgo=*K_CIkz;vMYoT^}z+bM4;syzH3yGDY*V1OHPgTEO{Iw2&=Di`Y`Mm@P%8v8CvA zwiGR4OVJr@DLRuaMQ5>5w3L9NWdszRO+e9d0*Y1;P_&YOqH_o+I+uW=RRk2BM?leP z0*cNjplA&NMHdiIbRhvnYY8Y?M?ld<1QcCNK+$>viY_6b=u$$cs65+m>43y9v)iHy zDLQDM_FtAAGhe3Y%Ix5n&!uQ1=S$HhwiI2(mZGcKQgjVlimqi#(RFMox}GgXo7qxy z0~_^?k1q< z9s-KC6Hs(70Y&!_P;@^5MGp{A^dJF64-rB|8?ya54oG~lebw;_DcWtfMGt4k%$F&8 zEIU~Hr4&8R`BL-*TZ*1!OVLwoDSDbMMLXG2^bA{yo@GnXF18ds$41ff1QfkMK+$dj zie4n3=p_P*UM8Su4*^B55K#0g0Y$G7Q1m(hMQ;#L^dVtN^l3YaA_Nqr5m4k4 zP!uJEiayEq|8hX$&lsFfxh*nMK_X_pOi|55(C|AcigUgcWw50vlPyJAY$?iSOHqO? zMM<_4<*=nFmn}uL*eI$^Kv5k6is}+jRF8n7`UDg;AfV_F0*V?EP}GQkqC*KNYD_>; z69S5w5>V8PfTF_)C_0>gqUHn?9YH|RkpvXAAfTuv0Y$9{p`uvA@9luZZ?U^VH4@=x z`qvt%qY^RmWs33=LGce#l+XE6RKS*^LbepOV@pwcwiI<>OHoI*6m?=tQD?Rkbz!5Z zD*;8_2q@}KKv53@ih2@IbTk1)y$C4kO+Zl}0*d+)P}GlrqW%OF4IrRsAOS^#2q+p% zK+!P-6b&Ju=vV@Zh7wRTjDVu!2%(}j3I7}iB>swhj@DL+(u~yciJ18^MWYhIP5Y#1 zH0Mjv32Z4E!rRZd~6pdp`(Rj8LO<<$w6atEh2q>CJKv6LPMUx09 znoK~^6atD$2q>CLK+!Y;il!4#G=qSmnFJJ_Nz(JBIp&Lf~`H33EE6Hv5< zfT9ZsD7uh*r{Z}Mn=F1dal?dAZCPi0sz7$=>e zku60xu~Bq00Y$eEP;@H+MYj=9bUOh>cMwptm4Ko<2`Jh|K+#4KMK2Lh z^fCcOdk83cg@B@02`GAvfTGt4D0+i{qBjXBdW(Rfw+SeEhk&AY2`GAxfTH&aDEfea zq7Mlu`iOv{y#y3}OhC~mgiz7r3IA#bBz}s0iRcL_D!1FBPZKfoWs1H`1dshGMPG5g z6n)K>qHowz^etP8zGF+#_iQQpfh|QpvZZJrTZ(>Sqv&S>ihd!W=vM-Yej}jhcLIw3 zAfRYJ0Y!fjQ1ll8MSl}ebbx@Oe+Vf0mw=*!1QdBmecFzq2mwWD1QhuM6h#Rr3J54l zC!i=s2o-&v@IP}v;#&d-=L;!XXtzZ*k}>mTiZYWya6pQ(IA4mg*;15XOHq<7MLBFK z%4JJYEw&WZW=l~WwiMN6qo^JMMfC|NYCu5IAp{gPB%r7f0Y!%rP}G=!q9z0sH6@^^ z839Fy5m0nE0Y%LTC^~|Gq9X|?YC%9zO9F~o5m0m#0Y$9|C~89p6~&YOQ4UCaZ%qd$ zBN=|C|CoJvYnzOjFH=;Q437O*irR6$6t!ndQ3tjZb!1CXC$Jqai}nt-BS1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&Yz=okWu zh7eG6ECEGB2`CyyK+$mo6dg}M(QpEaMi4?p`AL7S0}>x&w?zd~bil^QWXyb-qA|(f zBF|nxffqfI^QCAkTZ&F%OVP<}DH_L?qVa4gn!uK#Q`k~e#FnCoY!np}P&A2vqR9jl zO(CGDgn*){1QbmpplCV)MKcH}nn^&>sRR_wBA{qC0Y!5NC@LkOXf6Ro^9U#^BcQ09 zfT9Wlislngw15yQ8lCj-b3o$T?0(S+Qj}$%=`T#i%$F%TJsG@}CPhm)Uy9CPOVOEZ zDLRWSMN8RIw2Uo9XS1bfIa`WWu%&1v8%5_3P;@Qo{MEu4hZpX0{aFz?PydY$>{t zEk!r6rRZk16y3s>qFdQ0x{ZLM+X*PTgMgx~1Qgv#K+!e=itZwy=xzdv?jfLPI{`)a z5>Rv>0Y&!{Q1k!+MGq2C^bi3>4--)I2mwWp5>T{*fTG6;D0-X_D!Mx9_jN$x_3h^8 z8Y#NpK1X{Z88cs|XlF8*9FwAFIA4mMWlPa6wiG?bmZIm`QuG2_igvT5=tZ^^y~LKH zm)R)VLqO3h1QfkWK+$Ui6unMB(HjI5y-7gPTLcunO+e8*1QfkXK+$^y6unPC(FX(+ zeMmsjM+6k@C7|eI0*XE%py*QqiasNt=yO7-=&7W?$^nVDv)iJlrD(I=yZ#~>Ghe3Y zn`CfHO)2`8^QGuJwiJEOmZBfnQuHHRiuSRk=qI)m{mho4U)WOgD;q_>5m59y0Y!fh zP_&~zX>QhKtRzy1Qh*CK+!=0io6_s+K!?K0Yzy96!`=cMF}Vh2q;P? zpeRN_Q4Io$Y7$TsCxnW=O8PH3An{T+qhCwWWcy4%BPV9QOi>~y_%TC@lAJF^IczD) zWlK>lwiMN7OHm!R6xC%*Q9ZU4)n`jl12&2dA)u%s0Y!}nC_0pYqQ(RiH6fs=DFH>z z2q-#?fTF_*C~8hX(Gdg`9Z5h@3j&H-5>V8NfTE)aC~8eWQ5yn^+7eKdM?g_NAykx= zQ6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZF$5G1 zA)x430*ZzbP&AByqT>iCI-Y={;RFl)&6}8LpPj*1!+4ebFdnr28 z?p>dd6Ek0?=%k$B^rRG>%=uC@jx9yw*-|utEk&oWrKpH4MHAUlRLqv5No*;a%tp}^ z0*XoqD4I$@(KG^zrV~&!gMgx$1QeZ0K+!A$ie?i~G>3qqQUZ$R5>PacfTA)2ipmKn zsvw|fJ^@7w2q;=eK+z%siWU<>MJML?*E%5ax^`PMR*HVLFF~G`6Ek0?=**npiCif< zi}R&uDO-w`v8Cv2wiGRAOVJ9p6s=@S(K&1>I+ra)tJo+ykAR}p1QeZ5K+zfkiY_3a z=t2UD))G*(j)0vHUf(7BB1DQ0*dY-plCY*MfVa=bRPjl z_Y+X`00Bi05>WII0YwiJQ1l1^MUN6tw1a@6#|S8ToPeSy2q=1zfTE`ep`z<@{5B3q zyodem{p+RZYr8FaIwxknOwq2KU|2mVdXDp@=y|pjy}*{D-E1j(ku60pv8Cu`wiNAQ zOVKNADSDNSqSpv0dYyoxHwY+tlYpYP2q=1+fTDK@D0-KGqW1_WdY^!z4+tpwkbt6( z2q@Z1K+(qp6n#QK(We9yeMUgh=L8geK|s-$1QdNm2o*h(~zX>QhKtRzy1Qh*CK+!=0io9HX+K!?K0Yzy96!`=cMF}Vh2q;P?peRN_ zQ4Io$Y7$TsC!i>UfTBzSin0iyqHlBj2ON<2VRl>eofMVZN3`tRnE5hAxw*kR4W+0S z=Sxv-wiMN2OHp066xCx(QGK=)HDF88A#5pX$d;l;Y!n?zKv81?ikc8m)RcgtW&{)+ zMnKWw1QazVpy&t!ijE|ps09HrKl@gin_6-s5@JV zda$LaCtHe+W=l~owiNYdOHm&-iuw{z)Q^Co{sa^aAfRX<0Y!rdC>l&a(J=%R4I!ZD zSOSWM5>PaZfTH6FC_0{iqTvJ-jUb?CBmqUE2q+p&K+y>V6pbOE=tM%OsAI0*-vNoY zHaMN6Xu91Njm?djFHCKK+&lL6wM-_Xf^>wa|kFZC7@_70Y&o&C@LeMsGNYJ z3IdAe6Hv5(fTD#26fGj4XfXjrrx8$eIsrvX2%(~rbN$s0Nc;i&On;mdZL|+>XXM7r zmnmA78{Br76rIiaQnZ{cMJw1+w301F=dh*dT(%UgVoT9^Y$;mJmZJ07C|W~6(FFt) zT}VLDS^|pJ5m0my0Yw)RP_&+aqDu%Ux|D#T%LpjCoPeSY1QcCCK+%;16m2A+XcGZN zR}oNjH33D}5Kwe20Y%plLPclg`gFeAk;rnN&1EL?-Cgr!Vnmkb)lOWR@Vxqo_i{Y1QKDIG&uf~PR@d{I zC+?{4c`Xya9O8Lx5?v4Vyn@78O+2qdVrMhY>ypT5?s+{DBaZaE-igawdS3s;2S<6{ z;Kbo=J#T1YM!x3_PuyAPd7~4*wfDTSiSC^|Z+v1|7tfoRc($A8O-W?+^t|bbQN28G zR^p02o;Nq~Q9sYCNE|WH^A;se9qf5a5_b*pyrqdhhI-zLM9-`C+?Z-dABG2Eb+W;iC)t^ zZ+l|pOwW5D@xm<6dnA!l>UobRPMqg?PbaP__q<(+Pv?8y?nEp1Ph#vzl%D2!uP5$Z z;(2c;{yx+5-cR&d=6QP)=PviW&k`@L^t`VUwN`oFcZri$d)~gpHETTY*Tm-+dfxs- z>x(?^Kyu!C_x6t@@4wVt0g>cCm%D2qlI(Y-y9y%7^ESEbAd-CfYIh|>l69_g*Fq#Y zZnL`@BFXEvxa%R3w13UMc_eB79C^z~(*8Z^Hj$+LgTMumr2UJo9U@8lCpo)BlJ;*Z z_J}0yAI0k(N!q_^)<2T8f0k-+Bx(Py(9lTo>&M-75=q*>>@hl$w11jmY$R#FTYr2c zX}=tOVkBw5-FiwSX}_L$dL(JTUv^d`X}=(JZX{{H;jto;v|rJ;D3Y|_v9=_Vv|p07 zG?KL6amo_}N&ibCN&8Xl4Uwe%tnH>q(tcR-+DOuV z+UU!O&i_T`JO zB1!xF^SemWK7rU5N!mTYUn5ET5WYW>wA7>!bp3+(4W8aM~*~?SUcDH+fj&#*iu5p(z(oJKBozq=or;Q#O zBO`9~)HvvFC?ZE|JQsJPm&R1P1iiyir?DIMhpu~+9vS3Dy~yx1_x@7Xy@#isI8JS$ z6Wv$Mo@ar3yuk(T71@8m5q{i@4tfbe9WMqWT5OFh><@q&u{)~*QjLeKK?(I^e-hZB}rhBex zFEy?igs&t+FVanWk(qjtsi#)G$Sl1`Jy*6nDX6*}i7a>N>@_D-j|85Vqd$pWNp4=G zR|76Yiv~H7-1Oe{FYnvHUSqAG+Qmz&cYj~^HmTjAT5IH9aGmqcb~Yo0?)mGwN8OvT zu$G-%Z?)@b^)KpM-@WO1f_tOqdA%C+XfP)`^*Y^!a90Em?uOmHPYt(&nT~qDM226( z6RVElvyHIBX!l>l8*2y781cWJF|z866RV#w@_#*JRMi<{s-H2c@{C6AH9JA>f%muY zlBAOUXP1nJdhR{N_old0(jtFnXL%9#;GSmu^YZe`iu0$I&&@9{o19-(R6e<+Xl_|) zMakrfk}3I<%NEbAD77%TWXk-qlJaU#v*&lu-8Fx1*^JpUDrPJw@$#pa&MwI>o>j6a zKW|p) zN6jrRJ9XgvIYp!0pJm$cS@X+_M)v76tmFTUt7$=TMTxz&JTJVWr_P@b)4qKd_HOUm=6n=p5EO_?#L!VM>ARKEd5?qW{vS2}xk=^WP_KETYd7ab5*{exhJ;^>ZC{V zngz9*xRGz8=l}9}(6k_^)!02(!GB(2)BnE2NV~kWsC!2kIbcxHz=FY^9Sge@3@(}! zKH8~6<)a<@RX*COi=MMX7g`@qF6a*&=Mqxi*mAl|N!vs{jnft%>&fULc()?+jyG5Kct)!@A z&XgI&bBbn_&Y2ee0o_&NUcI{ssdk;{qIIacwC?&3pS|*r2eg8!KV8?#KS`l8>>WGc zq@q6kN2bnmSFQe#j<6o<|DQ8GyGTt_|NB3f6{ar8|IH64`e;;jBb9nz)%EIVq%JgS zD_w@~1@^21QkQ6^y$7bAwLrk#JB0ppeJlT*_O73Lrao1F;QsDa^%*&+(EiuX{@33A z*CF+6g}na4E|o8>u!=PdQCL{zyl>?dhP_Hg6yzZ^7i(7SL*j}e~thzj* zht%7kia=pC1J$nkPVV$7?A(;PkCox;wkO*Qa>vRy6t7Sh&)taWN$o4&gzgQ&vsW?T z8s-YFyi&WkmsDD*x9U3K1C8B0>BYHoc)`wN_$G9(HuZ>mOYpSHi{xIHYbIc{`(Ur< z=R|jXq>5e1sgGabhphpXXS-`aFR|(pa2>n1ke*g~U4o?0T^Hf2szTy!q1>~lUQ6mp z?n>6_?&FIdtNar=fZ_S>CfaT*%fdHLVR+C7*D4l;RW2$iR&j72x82JxpI%y4QTd_L zspC?F*M8*{U-?1Zz4xS^#jczbCHH0tAE{=c>bftiy7CLFu6?eWLU&?Dp+lsF*%~ z_9S#1{_ww>0r?eXoJwsrS8dro#2pzYMzCFSMC(@NUTDw#8_VtUU4m%=+YZSC53 z%Wl6aW|YopTkh^VyJNX)Q;I8!D|h&&aCZ>GN2&}LRv|W)|J%p3kY}}zyOno3oZ-~V zth%FUD(!7tb$_wyUSeSgJtfB7SnFa{T^XVF$`7h3+(kwI{fN)q)T(=_@Ui<<#}6D; z`H{SkJEc{3FstrYR^6?1cTnLIzBky#tMtrW(yDul)$S~EkF@HZA@3N4-16GJ#_%m9 zk>TCL)SJNWlj?42>W><}8&>}DdAF-XjcL1YdTQlOB6mTn?j}~G>kNgG)_A#l4oB5 z_#Y3|Q`GzEVD%^a_Bmp;2VY--Ao=zwVzmd~eR`NvZQIu>YP)S;(Fh-^zII{T_flV0 z)YELcFLPCU@ICi+`)UuqSN)4P_WbT^`PCkLFHvpT)Bk&Ee9wKksM>??eyGu;X0n6qx(WY>iK5s zI8Vp3bX=k1IvqFbc$a-8$-VqXb$rcTm9{_9@i+GeupMz)znDGa81+ z{_ZPmw(YBVc3j;gJYKHj9`}Z|{(+8ln}_>w9ml&X&YnI)$Lrk{VEaxTzj9w3w*8xq zd2PepUB?P{McLDr>G)7#xS!S0>k#fN9S6EA)SiEoj%&Jv`wAUj?H2Bjbgb{LczgaM zbUdY3xKGvbhCboGOUG~eh5HX33kHU}r;ZB-hkLn>j|>U-b2_FC3wJ`t!N-UD1RXCN z5$=sTzCJ44AM1F?m~gkyapKr;&(`tAlf!+Fj^DX=Nc;2ssbjmMaQD)2QE|9e>bS!} zx95LB$LQ2>=jb?Odbm&2aox;tU!~)lv%>wUj*Uvg-Aczv^TJ)KiGDQaKETy`dQ(wrQ^_L;XX;ni=y=?f;U1^sC7Z&1 zosREb9quo6YbUK#a6hW!@9uk@_Wt9)8y?*BR5!7t(Q=-NqDB?$dSL?!HlL zPk%zkzub3hZO7b?Oxdxw`_`=;hv|5Z`yQ_C^*Zi$-^{iBj*hwRySlcU=s4DWd)Ib} zj#sArDK5|1JCQF zJ;aW2&pS@XQR=5?PttLkdYSeD9Zy$3M|-u7Yt=XDc#Dqr>G+h6dvyFj$8U7}L&vE5 z{;Xa89330$*xHWn&(T50!8(rDakd@ZdGmC1cXv|HUqi=)jg+U`!YeE#k~LC z4Nmnb_GNDOy@jcz?v&Ky#gitLl`II)3XA*3Vf9&DW_O?Ua>M8NKg%rpwx3?2yI@}4 zWcNL)688;|YOi%_S@CT5OnpWU%PX#^D4Q{9euaCn|DPY+T}Suc?!M)&Gu&OX|2()i zUFxBk`@cP(A5Oa~_n!xQnmx2||CyWrx92Nx&+|WD?|9dEu4yT>`lJ?iy7 zD*W@>_2xG=0DH(a@UAA#5Epxz8x;u<2*F#7O8yM*6j7#!$a=B>X+}@YJXn4o#XPo z;2w8>yt(d>dKl_np54yz!0WOj?<@ASRqpwEyI9XXp6mXzmuGKxd!5zZT;8tk5wDAD zJn-^zT&Vth+uY@Qk7sg6p0E0+>V%XJ6TLUyvy%toHv-om}hEp-abh zP3>V~{Hy^(2Zn!TB7DIS_Zc@Y*UFkfsTG9p>n*(o?v}Id*Zcac8dz^&Lf}1@8SdyndpQn0rHI{_ftQ9jd=o-Gxevq?g*~*O40bJ89F>f?s2Hh@I}D zU)NpWv|;t#=WFiU;z70p=dZKpI=;cgREiyNFE*`4(7?T`r`3p^@7}`EXkcHLON+){ zanIs6aL?|ysny3Gzs>0z?vi!T&b93>T1V|1+wQV;(oWiT z7p}8*!nV6~U9_`pyNlOVJIl7aeBHD&-EQYDUw7>c+wSu9(2m=7m#?RGP22AB9j#r% zw!3`2v}3m2y*H7EG?Ji$`?KHRByURB~J7U{izJc1# zLXBv&x&NHI{%h_tKS!i~_N3+zCnGv2c9VMs6LM@|e>pcLWT;M+kYSnni4WvQ$kMAM93Izgq*02kg?hbIY}EKCu<{QoHjznYa?WWHbPF( zMo5u1LMCb>q*xmvle7^sSsNi!v=LIGjgYC@2$`mhkm=e8nW2r4nc4_BRXY@NjQ_2> z{%hXhZfK%ILLuYbEmU+?%;cDmxq&#*loxqp^$y{_xV?rJZ z><2zlLLSzs67qkmt1#@`5%(c55T#MQwzYf5wGpyM8zHY~Bjil@`g4- z-qc3OTiOVDTN@$oXd~oZ?NG=A{s?#d*ZkM+dpsBlx!&%RycaV$Cgh{Qei$evWUo$@ zkdHMbD(cAwOs% zn9V_ z+4{-E7+XJ?Sc9#fOsvV)PbS9M`pLu$wtg}(ldYdj%wp>&6SLX;WMYEAPbMY_{A6Md zfuBswCGeApwFvxVVr>FHnOKLwPbStS@RN!42>fJXeF8t3*nq%KCLTiIClebI_{qdZ z1b#B{Py#=h*qFdiCN?4PlZj0U{A6M?0za8}7=fQmJeHCZOmTLa3-kB=vVu;+NS?QA;U$*+>nE#LSl| zIxZ5}kE*5=9nbkvG@LC(BiK?jk}XA}*itl_Ek!4=rDzOWicVxp(O5Q$P9mV_WCDuD z5l}RqfT9Tm6rDmqQ4s+}6A36PCZK2%0Y#GuD4Ie*Q3(M>Qwb=VMnKVY0*Yo3P&AW( zqEiVdnngg-Yyyhr5JE*mBmO`KB);9v=rAcNFjA%NujSZRTAiZuNMJweoKjT5`BF5W zEkz61QnZjQMT^){w3sbLr?I8zbhZ>NVN1~&Y!sbIK+#zQ6fGs7Xc+-TXA@AgoPeSg z1Qe|#py(U|iq0jVXcYlP=Mhk}nt-D72`E}aK+y#R6kSL_(OLqE))7#25dlRP6Hv6C z5GtA%@z*#Y@uluF?P!@4ZBBij6^WTIQ?wxx*pJGm6kWmjQgkI-iZ-&PXcJqCu3}5k z)odxchAldV(!QPqL-xDYg_n&6c8_Y$iba<0*cZIp`yJJ{}cx#{;KRfTBhO6dg)HQDXv%nh;Rblz^gU1QZ=cK+)j@6g4NH z=m-M0MMn}))PfKy3ex-=9FX`z_nq@-dRq9I{yTPC)G{q*zD!Y@w7`BHCZOmT0*ZzZP;@K-MMDXp zqNCFMZyb<#q5FG0(biJr+h_X2(qiVz6pcs=>{m^t6piG3DH_F=qS0(AI)N=kW7tx3 zB3p{avZd%GwiKPrmZEWN6pbgKXaWI6rw~w7L_pC*0*ZTt7Xd|g6Hs&y0Y%#hD7u$`qWcIax}Sie z2M8#7kbt6x2q=1(5GuMN&40uJiLZ+|I9E#1D7!6sBrRsXOwr?Mf&Hq))NRodoG(RB zvZd%LwiG?hmZF_(DSC!2MbEOOXct?Go?}bV^K2BoKtR!M0*YQFpy(w6ie4t5Xb%BJ zuMkl5Dgi~W5m59x0Yz^RQ1m7NMQ;&M^fm!S?+{S*E&)aF5m59#0Yx7WQ1l@IMIRAR zw3iSn+L7j`wRVbru+Q`#lcMA7-u1_6G4o}LK2HnmS8b*geZl!s^d(!0zG6$!*K8^J zhAlV8LfTBYQC~8bVQ4<1+ zni5ddjDVuU2q-$7fTHFE6dgf8(UAlcwIHCVB>_dP2q-#=5GtzS`xiPO@tyY9g=+fY zXZkPOZBc7KX1+{Oz8~1H`b{Y+;Cv}6WJ^&ywiLBzOHl{56m?`vQ75((b!JOZ7q%32 zWuvGY0Y%*jDC$8#QBMMjjwYa}7Xd}R2`K7AKv7=;iuw^y)SrN&0R$8cB%o*z0Y!re zC_09Kq9Ftn9ZNvbPy&jE5m0m-0Y%3XLPc$T|8)l>zQpbdCPK+y~Wie?f}bSeQwvj`}fO+e8c0*XorD4I(^(L4f* z$_OYbC!nZ;5Goq!`-gOJic{pGa6rINTQgk|7ik7gY z=nS?LoynG>v)EF!lr2Te*iv*hTZ)#mQM7`9qLl;`okKv;xdargBB1Cz0*Y1>P;@>4 zMQaEsx`2S93kfJ%OF+>&0*Wpopy*-(iq;cQbO`}Pml9BP839F?6Hv5)fTAl1p`wMp zKhXh+A8WToi=?Q(eMGy`kC`u1bhRJYuc}Wex`y+m=vuZEUB{N9>)BGYnJq;(u%&1V zTZ(REOVLeiDY}`BqFV?kx|M*U+XyJSoq(b{2q@Z0K+&B96m27*=q>_^?k1q<9s-KC z6Hs(70Y&!_P;@^5MGp{A^dJF64-ruGFabr65K#0e0Yy6qp`uN`f1?8uFEB+{Nl_OY zkNGk4Ws08i1N)~AQi`7Dd@0(=mZE3aQuHiaigvN3=sC6&JW7eL_Idr-V?^6TbhQ0}{W`zUug-6t%P4qR;%8`7%Xc`GNgY z87W0ybG{UP!eYyHeDY9Qe5Um-FnJ-h66%Fj4T1hF&=6oqiu%#%; zmZBWC6y>s|s1{p_YO|%N4qJ-qvZbgV8%6aAC~81J(IEsBH6);@5dlSq5>V8bfTAV@ z6g4HFs2Kr8hY?V8H~~e?2`D;(fTAM_C~84KQA+}fS`kom6ahu82`FkqKv7#ls3;@q zFLFTQqwTgRGa7!Tzsv4j=S5@Y%M`VX23PcvqV}9GMIG2u)R8Sko!C;;nJqPbM+(F7FrBA}=@0Y!ZXDC$cPC!uw0Y&o(C|W>3(LzF~=!B>r?e7$gv+sb6k)j=TTeK(|Ghe1?Ni?v3DlDbw z49=ILGucvf7F&vzvZZJlTZ+zROVM(+6s=%O(Mq-yox?`axdargBB1Cz0*Y1>P;@>4 zMQaEsx`2S93kfJ%OF+>&0*Wpopy*-(iq;cQbO`}Pml9BP839F?6Hv5)fTAl1D7un> zqKyO;Z6bt(0#>|%~x-J^nKQ)(9bUo)w(Pp+3-N2Tj zEo>>eku60xv8Cu{wiMmMmZDqPQgj;|MYj`BbO!-NTL~z-lYpXa1QgvxK+)X<6x~BW z(RKog?j@k;J_3sFC!pv70*W3apy(k2iXJAQ=n(>n9wne?2LVNo5m59v0Yy&`LPgg^ z{dEpVyqSGkcC8f6vyW&`Mq}p76g?9S?4K%3DSDRkrDzvhik@Rj(erF6dVwuPyV+9o zB3p`HVoTA>Y$@8qM$sz-6unA7(Q5=0y-q;U8w3=+NkGwC1QfkZK+!t{6unD8(R&0G zy-z^V2Lu#-NI=m?1QhKhpy*=)iasHr=u-lUJ|m#$a{`LKAcTsZj{0vpAn}d%L2RcK z-C(4?jK<8DDf%`V*gtidQuH0?OVRgiDf)peML)8oXdhdOequ|}&ul6Bg)K$DvZd%Z zHi~{Hpy&?*iuMyw^d|vDe-TjhHvvTl2q^l8fTDj1C^|?$kr(LGb`(VjC`u!s$S0sE zNvP|?>>ztJ$K=o0&g_Kg(%V;|8ngP8d;Madwr ze=0SlD2MZiowb)Wrn=M6k*iuxNEk*U%QdFNUMGe?ebO;+o4GAb}L_pD@1QazU zpr{D}MNJ7PYDPfOVFVN%PC!v}0*a0xpy)^fidqm*)RKUrRs<9sMLZ5LpXm>=8>Ye_X1+{O#~`qOYB!~*6X#1&XSNh| zVM|e0wiI<^OHp^W6!lpy(I^iiQwSbSwcyLkTDvMnKVV1QZ=lK+$jlibfDnG?IX#Q3Mo?CZOm9La3;H z;NR?k#9P_TPX{U5YGX_gGhe3Y{Y$+;YOVLEO6cw|j zXcAkBCbOkz3L8Zw1QbmrplBKaMbil=nn6I(Oah8dC7@^)0Y$S3D4Ih+Q7HjMa|tM# zM?g^-0Y&8m6jcyVG@pQ?1q2i=B%o*!0Y!@mC_0T0DjFO3KR6)qt#()FBq`c%w?(H1 zG4o}L&I$tir@m8)mU6xnEn`d3*=#9V&X%GTY$;mFmZEdmQgkj`idM0u=sY%xRufQk zJ^@8*2q?OMfT9ZtC|XNE(K-T(E+U}lVgicR6Hs&s0Y#S*P;?mqMVAv$w1I%4D+nmM zl7OO(1Qcx|py(Efimng*(;Sfa8}?Pl%~JHNds=j75Hnw<=(!-+c(N2d&-qgH0$Yl9v!&=o zwiLa@mZF#0QnZIHMX#`>=vB59y~ak->jV_NK|s-)1QfkRK+)R-6um=0(Ypi`y+=UN z`veqyKtR!l1QdNlK+#?TiasWw=o12pJ|&>&GXjb}C!pvH0*byQpy(?CioPa;pSmsjk@KZ!A6trkVoTA_Y$^JMEk(bw zrRX=d6#dSYqCePDw4aTlKM5%Mi-4lP2`D;1K+!)06#Yv;(Ln-=ymWoqj-m(wMQH>S z`2-Y22`CB(C`u=wC`Le04FZa45>ON;peTcYqD%scvIr>3CWMN<3;gs6PLX}zHTu02 zePf^YC(>i)%M{g04_XvSQEkqbqB?9Ts>_z5dTc4G&z7PFY$-Z~EkzC4Qq+hoMTfFc z)R=&xCIl2UC7`Go0Y!%qP;@u}Ma>B)I)Z?rBMB&KK|oPU0*YD@P;?XlMXd=aYC}L# zTLOym2q?-Yps0X=qCx_S+7VFHo)9X^N%x03Ao2U`-gRzz_?dnS`?SA9ddz&8qAuyd z>|!bE%K1{%jV(pp*;3SlEk!-qQgk$1ih8l7s5e`R`mm*_FB?Vu2q@}LK+ymKiUtx; zG>Cwr!2}c?LqO3G0*a0$plB!oMZ*XvI*x#%;|VAlPC(HJ0*XcwP&A5wqR|8toj^d* z7y^n;B%o+4Aym{U-M`oYiGN`Ci#khD9UCX5$IO>0nvfpcGg*pG;e077VoT9PwiFe! zrDzgciYBwAXbM}3O4w2~l`Tcn*eIG#K+y~Wie?f}bSeQwvj`}fO+e8c0*XorD4I(^ z(L4f*$_OYbC!nZ;fTH;X6fGd2XdwYbiwG!MOhD0T1QeZ4K+zHciq0T}ipHh;Z#y9I zJM8ZljhCX;_7UyO^qBcFMQ5i6f0jtma?Y2c6>KS5$(EvX*iv*ZTZ&e(rRY4i6s=}U z(fMpCTEj-s1q2jbNI=nA0*clVP;?OiMHdrLw4Q*XO9&{slz^hk2q?OofT9fq6kS0; z(Uk-gZ6u&*69Gk65m0nB0Y%pkP;@N;Mb{BfbUh(dv^3psJk=@cVt1&QNzsDTCv534 z^JR)|N)LKXm!g|FUy5#FOVO=tDY}gE*XeR+h&k#`bEFo01CEcImfW*`7OGGzH(NeoD+LazNU#4hxda!b)6urp# zQuGpAie6?*(H^!Gy~38FSJ_hZ8e589Xa7IM-FI|Ub=WIN0Y!%iDEgX!qHhQ&`j!wV+FQlH z%>juXu+L~ONl`a@*#BLXi1{)_KUN99G((Dh;(RIknJq=Xu%+l%wiNxwmZIO;QgoCp zMSrlR=ufs3{l!Mn-vku>LqO5L1QZ=3pva5pVLOUK1QaC^P~;O(luSTTn1G@x1QbOG zC`uuqD3ySsC;>%j1QewcP?SMHQ6>RJF#?L>1QcZv0!2Sm@sBtl(Rb|T=ZF*~*=Mxu zNW^@Zq8gEKRV6g4KGs0jf@ClXN9lz^gU1QazVpy(t5idqm*)RKUrRsXG1)esz1K-ysq)U#6%_Bs^-46m{i% zDeA_SqLbND)SWFwJ=jvzlPyKP*izJ+Ek%9UQq-4?qJ9Jv^(UZc00Bj(5Kwd~0Y#?~ zP&AN$qCo@{4JM%IbOMTo5KuIffTCdp6b&b!XaoU8BMB%vgMgw@1Qd-Xpy*5jiq0aS zXbd4x)G6XGazLUVxtZKqijMkjjEzLhmnj+-313?(MTML%MdR60G=VKe6WLN!#FnB- zY$=+|mZB+aDVoZbqG@atO(&pe1_4Dg2`HLHKv6LPMY9PgnnOTQ2?0f=1QeAKP&Ai- zqIm=qol8K`d;*FV5Ky#`fTHsVC|X27(fI@vT|hw5VgiaTBm|1iiTF=BAkkI!NvuGM zI@+hVC6S2vGDXWH;m_Rv#5VCAkQJOSMJw4-w2Cc7tJzYthAl-Gv!!S)TZ-1PrRWm2 z6s>2YXafO7ml9BP839Eb2`IXpfTAl1D7un>qN@lf+C)In)dUo6CZOmV0*bZ}P;@N; zMOz6dx{iRN>j@~@MnKUG1Qcy2py);digpkJMN1=o$~>oNo14kYr05B|t9?@>V!lk# zZIN*E`BHQ{=S$H}wiMmLmZCe^QgjzvigvN3=x(+Y-NTlmd)ZQS9~(ux2`IXsfT9No zD0+~9qK615dYFKsM+hi-lz^hg2q=1-fTAY|DB43n(USxeJw-s#(*zVfLqO591Qb0- zK+*FA6um$|(TfBW?Ii??Zi)DV9gygI_Or3KO3`e)EqW;uF<++WwMe*lp%lH&`BL-- zTZ-OfOVK{I6urfkqWx?sdYdgp@35ulUA7dx$41fn1QdNhK+ypLiasQu=pzD(J|>{( zAOS_65K#0f0Y#q?P;`iZqR$B^`htL>F9|66ih!cS1QdNuK+!h@6n#rT(RTzCeNRBq z4}?I`D-r*42PFEK-4%LOigw#=(UC~Re3_zOBH`VOr07@9m!jX;QuI4pijK0S=nu9O z{mGW1zt~drH(QGSVN21!Y!n?MpvX(n!*&#f2q;P-pvWhnD4BqwFabqX2q=mWP?SPI zQ7QpNQ38t62q;P?peTcYqD%scVgwY$2`I`UpeUPwqN)TGRU-t7ev0_-J0Q`;_EpE9 zrD(p9s-6-tU#6&bO8Bn}r06)#m!djsDXPnsqIzs8s?V0925c#6$d;l;Y$-aPEk!4= zQPh}#q9z0sok&1YQv!;b5m3~efTEKKC~84KQA+}fS`ko`LqJh30Y!NP6y+08)S7^z zHUt#4C7`Gs0Y&WzDC$5!QAYxbIuQazHBl&a(dh&f4I!XtC;>&o2q+p(K+y;SibfJpbOr%MqX;M(O+e9^1QeY`K+zZi zipCO9bT$D+=MVx#T~qu?4oGx_!RaPN2ko|~ASGhHOwojt@XDo9G?DYAsE92^lh{%; znJqM5dlR@34x-*6o01! z5>2wZLgS^Vv5{Jq5;0$MwiG?UM$v-=6g@;h z(Zd83JwiayqXZN^MnKWy1Qb0%K+zroik>8(=qUnnW8sS!e_3LqJ5k% zMQ^dCXg^zu-eybDJ8UU>mn}u_v8CvJwiJE9mZAe}6n#iQ(MJRneM~^nK>~_CA)x3} z0*XE(py&_*MV}K;^aTM$UlLIC6#+$u2`KuSfTC{*DEgLwqVEVO`ksKI9|$NqLO{`v z1Qh*52o$}Z;$Pr^xbLDlIB!Ui`)AtS1Gbci`7%Ynr-ZLtD@8{+UyA-Sr4vw;K|oO^0YxzaisA$mWf4%6O+Zmq0*a~;P*k0Oq8bDg)g%OpeogV8aX_N4 z*v-#xQZ&&4ugGc&%Y;;SFm@iY* zGd0}eQYq@i`BK!IEk%9UQq-3%Mg7=P)SoRy1K3h@3R{X!WlPa%Y!nS7plA>QMS}?_ zI-P)`Ap{f+C7@^+0Y$?JC>lXP(MSS{&LE&@6aht}2`D;~fTFVqC>ldR(O3eC&L*Jf z90H082q+pyKv5wfP}DuuAL4*SciYWR4=Jjec)*q#F<+)=Qfhe4Mk$)i`BF56Ek#q= zQZ$V%Mbp_*G=nWgGucu!i!DXPY$=+}M$sGsib@D5DkY$(jDVuK1Qg99py*rzislng zw19x3g#;9xM?ldc0*cNjpy&buiWU=4bRhvnO9&{sh=8J{1QabJplCS(MJot_qKT>g zl@3U>sone(Nl~V|o0PmVHDbO@(Z#9Z2d)29s30sQRv!!SQTZ%4aOVMR) zDcZ=EqRZJ*bOjqlR}xTk6#+$?2q?OmfTGO=6kS6=(G~)Vt|g#oD*;8<5m0nJ0Y%#g zD7t}wqU{6}-AF*u4g!j9BB1DI0*Y=Spy*Ztif$vI=ypP&XmzT8zyXQ&bu)R56!o`< z{X0`5=F1fAN)7*Wl@#60`BHQbTZ-;wOVNF7Dca4JqWjrW^Z;9m9%M_=Lu@H}n2n-G z2q=1#fTG6;D0-ZLq9+I_+CxCmlLQn!ML^Nh1Qb0(K+&@V6g@{k(enfpy+Aie4q4=rsb0UMB>K?o9QM-{cf+u`e{ zZAG1+(kbt632q^lLfTGU` zC^|$y(dPsdeL+Ccmjo1jML^ME0*bySpy(R{ioPYF=sN<6z9*pQ2Lg(Y5K#0Z0YyI% zQ1mkaMZXYG^eZ7yv@g}4;($c&u)n4DmK5!`Z_WOe8Zlp{=+D&f>Mc_A7w1dS-)t%R zhb=|_vZd%4TZ+7>9=S_Vh%H4)Y$@{DQk2X_QJ8?DDg+co2q;P+peU7qq9_4HX#^Cd z6Ht^vKv5Kcr}b-4@k}M$DHfY7h;-wpEH6a=sKbVoTBSY$-Z{Ek%vlQq+VkMJKYQ zs3}{Dnz5y*IU7YM5m3~EfTETJ6tyCtD2ITeTmp*n2q?-Ypr|zgMQsQuYD+*-I|7Q@ z6HwHFfTE5B6m=q?s51dYT?i=ZNxNI=mN0*WpoplB%pMau{%T24UG3Id8&5>T{?fTGoe zK+)u=f1v{sebR1zrbtn3`;4|G8Zlp{=#pr7+YTvO&-qfcfh|RsvZd%UwiIn-OVQ{*EkzHorRYJn6g|Y2qKDa1^axvu9%W0> zV{8;XPC(HU1QhKdpy){gik>2%=xG9qo*|&WIS0Y$G9Q1k`?MQ;*Nw2u%dx;yHp-{KVgX>jh5q8E+SThWO5GDYu3 z!>w+UqW3soir!~S(FbfPI>45q57|=m5nGBrW=qjQwiJEBmZDGDDEf?mqC*4}eNI5p z7X%c2NkGw81QZ=6py+D?ioPMB=vxAcz9XRMdjg7nAfV_70YyI&Q1lZ4ML!cz^a}w+ zzYJM{3qG#JDv3I0sjD33hBN{PZrs$t&xOAr!{mc1Mbc`)U zUYZ`cOHqg|MM-Qa^4U_9%$A}sTZ*c%r6|HiQ3?S?sRR^72`EYO??MX99}45Kz>WfTC^$6rD^!QFj80dJs_5lYpXLgg{ZlH2)(9B-+b9i8V?K9_eql z+oIlS5%Xn=`lp4D?UJGaoG(SEu%+l!wiKPlmZE`dDH_C$n=M6i*iux&mZDO&6qT{1Xf9id=CM(9E&)aJ2`E}XK+!@1iq0dT zXb}NL=MzwL0Rcse2`IXdfTAS?6kS9>(NY46mJv|2oPeSg1Qe|#plB5VMXL!YT0=n5 z#RL?sB?OA5rTNnwkmv;aHvV)e+H2nqS(g?uU#95NwD85drRXxwm!geqDY~33MOUz; z=t{N}UB#B7O>8N;nk_|}*-~^38%0|PD7uz_qOAlJT}MFC^#l}cBcSL80*ba1P;?^! zMLP&6x`}|In+Yhog@B@42`IXafTG(8DB4Lt(H#U7-AO>vT?7>EBB1DQLZE1Un!n2d ziSD!SfNYSWA@&*Vp0tShGDY{Nh2MBUiXPy6DSD7CMGvv1=wY@LJ;IivN7+*J7+Z=S zXG_r&Y$@8qM$wZ56g@>i(bEJJJwrgzvjh}9M?lf@1QfkMK+%f?6zwIT=p_P*UM8UE z6#|N0C7|dv0*YQIpy&+(iryrkXdeMZZxK+mpMavb34x;f()`~XkZ41Lvs;ROv)iI~ z(jw-|6n&5uuKBPO9pHQ^`j9O}AF-wAW406>WJ}Q}Y$^JbEk&QPrRWe_iauwf=nDdh zz9gXND*}oR6HxRu0Y%>sQ1mSUMc)xn^gRJZKM+uKgn*(S2`KuBfTEuXDEftfqF)Ip z`i+31-w7x>NK+$_?epd%1`kmdoeqW0E8mYh2BIe5!dFkP^AC;m| zx*o|(Q4(8ey4Od`lUzAmnk|mJ$!hN6rINTQZ$e)MT6KC!M0Oebw<4DYAcXCV6^##C(~e z;`DIt(^52>^QCAGTZ&59QdG*8qB6D=&1Fl`Jhl{_%a)?~Y$;m6M$tk7iq0dTXb}NL z=MzwL0Rcse2`IXdfTAS?6kS9>(NY46mJv|2oPeSg1Qe|#plB5VMXL!YT0=n5#RL?s zC7@^>0Y#S(P_&*9D4Ln>k8nVuH`*QQSyFVrjScA$^JR)IPY=(1R*J6Rd?~t;Ek#$c zrDzjdimql$(Pp+3UBi~5Eo>>emMukF*(kb>fTHUODB4Cq(G3I?Z6~1UMgod<5Kwdz z0Yx_xP;?6cMYj@AbQ=Lhw-ZpblYpW-2q?OffTFtyDB49p(cJ_T-9tdpy#y59M+g*M zmhNwMK%!&qtBxC`=wlnZ(+ zwiG?dmZGQFQuH(%Mb8jW^eh2I&k<1cJOM>75K#0Y0Y!TWD0+#2qL&FMdWC?ZR|zP3 zjew%p2`GAlfTA}EDB4Fr(OU!*?I)nj=pb8)K4DAIr)(+uj4efn*i!U4TZ+D5OVO8XDf)_y zqQe9feN8~oHv|-YOF+?g1QdNwK+z8b6dfU;=tlyIej=dgX99|TA)x420*Zbkpy+o3 zijERc^alY&e-cpi7Xd|o6HxRI0Y(230!0VX{SzIKXxzT)_@NYawnzHM(j(@}6!{t9 z{x3^Wa>joj>4(`;RD~@?5w;Yiu%#%KEk#kb6s57HD4i`u8Eh0~5>ON)peRm2Q5FG3 z*#s0-C7`Gp0Y%jbD5^m~QB4AhY7tOWn}DL@2q>yUKv7)+is}(iRG)yN1_Tr}B%r7f z0Y%3XP;>$zP!!7WXE-3y2MtbAM(`M|s(V>-WTZ;18Qq-D_qBaB+wI!ga9RWq{2`K77Kv72miaHTc)R};y zE(8>HC7`Gq0YxVhP}H4(q8xNI=mN0*WpoplB%pMau{%T24UG3Id8&5>T{?fTGm|6s;kk=wbqj))G*(j)0;| z2q;=lK+y&QiY_If=rTf}Xm*BwvI7#0+E*RtNYT}HTeLAFV!lk#RT<%e{Zh1v^QGu& zwiIn0*ba1P;?^!MLP&6x`}|In+Yho zg@B@42`IXafTG(8DB4Lt(H#U7-AO>vT?7>EBB1DQ0*dY-py*x#itZzzXg2{x_Y+X` z03lFxMTWo30g3LluR2~SMK9YU{RcB5=F1d4ni1adjubt{`BL;aTZ*1wOVJ*-6g|n7 zqNmtW^fX(Fo?%PTvur7Pj*X({2`GAjfT9-(DB4Rv(Mtpry-YySD+Cn1NV6g4KGs0jf@ClUfh$(jBc4oEcJ;Dj@SNBZubwtK*q88Kg`s6}S@+>fNFCFe^~ zE4CEnu%#%MEk${3DavO{QERpowP8z9TecLnW22}&0Yx1MDC$T+Q6~b5IulUTg@B^2 z1Qc~6py*@*inQ4s+} zlL#o9OhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q-EhplCKBP&7Ex|I`7AHn+cbeYzAC z*}dyInGy44isoj9{m-Om9_LHZxojz#&z7PEY$;mEmZJ06QnZLIMd!1n=mNGBEoP(W zLIR4G5Kwdx0Yys*C|X89(Q*QcRuE9Ml7OOB1Qe|%plA&NMHdrLw3dLPbp#Y$LO{`a z0*W>eP;@B)MVAp!w2^?K%LypDf)FSw&Gef&AkoY1wx~>sj@iThD>EbJ%M@+S44?A3 z6kWslQnZCFMc1;WXe(Qau47Bl^=v8H#+ITR*iy8eEk!r7QM7}AqMHaPx|x8YTL>t+ zm4Kq#2q?OpfTEoQ6x~5U(VYYo-9py)mVigpuFbUy(_4-ioF zAOS@W5m59nAyBj_)1T#lL}%Go9j}(6C+)WAk<5tsGDS~hhSz^7MSD13ik@Uk(NkYBMo~2a zimDS(RD*z`ngkTpBA}=?0Y%3VP*jJ2qPheW)gz#&J^@7y2q6m=n>s4D?Q-3TZ; znSi411Qhikpr|JSMZE|p>PV8SfTI2c6b&Gt=oA8qP9>n|Gy;kS5>PaV zfTF>KKvBz>zrq2DK4*{7T1nCGi3e=4i1{)_!(-u_k4Vu7&X=N*Y$-Z}Ek&c)QZ$+^ zMQ5_5=q$DrjbTgCShf_M%|_8V1QZnzP&AH!qCx_S#uHF9fqCPK+y~Wie?f}G>d?uVgib06HqjVfT9utib@HAqMR7~lnWAfB z;WocY(N@lvqU+dFbUj;&wy~w?2DTJ!XG_tIY$@8omZF>3QgkyLMYj-8bSnWxw-Hcu zI{`&I2`IXQfTBAID7uS)qFn?O-AzEzJp>fpOF+?m1QhKipy+-AiXI@K=s^OC9wMOV zVFHRCA)x3{0*W3Z1d6VS`J)|>Xj{82+9E~g+Gn)KV-fRZik^yv7yK?oPjkK$J;Row zXW3Hp99xQ>XG_rwY$Yw+SeEhk&AY2`GAxfTH&aDEfeaq5}jJeMmsjM+6joOhC~=0*XE%py*RV zplDCb-|B!wciO|UC#7hP-4=ZoiuEd)UGG zLW*YCZBa@*V!ljKdORHdTZ%F`Uy3r>QWRrLQJgJBS!^lFW=m03wiH!kOHp;U6xCp( zs3rkLwFoGxO+e9c1QgXFpr|eZMfC_Ms!u>s0|JT~5>V8LfTH6GC^~_FqQ(RiH6ftr zL;{MM5>V8PfTHFE6rDssQ40c!S`q?9(YSw-0}|bz>fofsgGc&L*r&Hv@rd~{MfvgY zY5z)5YtEOVHf$+s%a)>cY$dcm+E^HKaC7`Gq0YxVhP}H4( zq8Nv1}u%)PgEk)zlC@LhNXgmQ$69_1pNI+2$0Y#GtD4I+_(G&uT zrV>yzjew%*1Qg96plBumMY9MfDkh+4HUUL*2q-Ecps199qA~)C<`Pgej}Ryt5%=$R zK%zVBTW2GsD8nA}0Jp4|Q6fNR>DLS7mMHjH8Xfa!gE@Vs561Egw#FnC^ zY$;mCmZIfs6s;hjXe9wfs|YAsO+e8a0*WpsplB@tMe7JCx`cqD^#l}cAfV_{0*Wpp zplBljMVAv$bOixLR}xTk6#+$?2q?OmfTGO=6kS6I6fKDRe>))2N%pntg;Ml`-4<<$ zN6eQgx;`GR=l(f}#BI?w&X=Ma*iy8eEk!r7rDz9Rif&>{(amfrx`i!8x3Z<^Ha3cG zC!lC20Y!HZP;@5&MRyTUw2OeEy9p?|hk&Ac2`IXcfTG<56x~li(E|h&JxD;&Lj)8( zOhC~i1Qb0=K+$6a6g^Hr(Gvs|?I8q;w#NNl4oI|?-TYi9MZ4`W+LQ5!`7%Y%#={dL zQuG|>OVRUeDSCk|MK7|YXfIoeUSdnp%WNrng)K#|vZd%XHi}*+py&+(iryrkXdeMZ zZxK+mpMavb2`GApfTDK^D0+{8qW1|X`hb9<0|XR(NI=m?1QdNtK+!=0iasHr=u-lU zJ|m#$5CKJ>69Pp~$Ng0fNVKWl7Cj?H+wI=<7x9SsGDTm z6#YX$(Z2)~9V4K~%hJPk6om*VN+O`hC!i>qfTAz~MO6qWiV#qgLO@X}0YyMY)7PQAUVYTp6L%nBaqZ?fB> zysU`%GDU5(!tFAps2%4^QG2!&bznx)R%ywegqWtC!lBm0Y#?}P;@E*MW+!^G?0LzK?D>HCZOna z0*ZzZP&AZ)qG1FS4JV*z1R+q=I?F%H0g0yDW3)C>w8-vVkIaggFH>}8R`|TQ6rIKS zQZ$AwMPu1gbT(Ux&S6VY0b7d3v8AYxEk)zmQZ#{$qKO0)6%kN0iGZTX1QbmnplB)q zMbiiPaYfTCgoie?i~G>3qq5(0`!2`DNfplB`uMe_(KI+uW=`2-X# zAOwm=W%<`TAkhYPTQpjV4%?R?7iLAwmnpg+EBs`(6fNd_DY}p?MN8OHbP-#Mma?U2 z8C!~$v!!SSTZ&e)rDzo!MXL!YT0=n5#RL?sC7@^>0Y#S(P_&+aq74KTT}nXFWdsy$ zB%tVW0*bC6py)~himoD{XcGZNR})aQnSi2e2q@Y@K+&}X6m2C0iWX)0UpOGqm3H%U zz7!p@aa~r#e3_!{S>Z@^DY}vKrDz9Rif&>{(amfrx`i!8x3Z<^HntSq&X%H`Y$>{f zjiNgVD7uS)qFn?O-AzEzJp>fpOF+?m1QhKipy+-AiXI@K=s^OC9wMOVVFHRCA)x3{ z0*W3Zpy+V|ik={#Xb%BJPZCh{6ahs~69Prsviz0~NHpL6_Wli0^pV{bJ(CqNU#94V ztni?kQuHF{OVM7o6urcjqL`VUl36AB>_cW5duZeW%(rzNc1;*r2o7W{pntod^js&zD&_~S>cVfrRaOkm!coo zQgnnZML)8o=qI)m{mho4U)WOgD_e?wV@uKRY!n?Opy&?*ivA>^=r00_{wAR49|DU0 zC7|dS0YzT69=4+>L_kpz0YyFmMacvdg$XFCLO@Z3fT9!vic$$EiV{$iMnF+I0Yw>v zK+!i@{(}xkw5Ht_eJe$C>@!+scEo&{qU`MOdv&C!D(6d4HMSI0XG>8HwiMN5OHnPh z6xC)+(Q#}ks>7C|x@;8HBcP~00Ywc6C~8PRQ6mD1jwhh#1Okd06HwHIfT9x#C~8VT zQ8NOHniEiT5&=am2qQ6B<|`VvsokAR~71QZP*py(6=icTe<=rjU~1`<#-h=8KO1QeZ4K+zBa ziiQ$UG>m|v;RFqD4I+_(G&uTrV>yz zjew%*1Qg96plBumMY9MfDkh+4HUUL*2q-Ecps199qA~)C<`PgekAR|c2`HLRK+ysM ziWU-3bRGdkiwJ?Dv$Fj)4oLJ#d!#=`iZRv*0Yw`L zD7u`0qALg}x{`pRs|YCCL_pEi1Qcy1py(O`inb6?bS(izTL~z-j)0=;2`Jh|2ox>O z_Fs2EqF=a~e4!NmVB?1Di23p|y`x^hMwqoJz`fi^SnN>4^Q&E0kIQWdEUU-)LhRS61ywk^G3ve zZR2^PV_n*N-q_fZj-EFz_Izj0n;6UJ=6O?M!@GOljM&vZJ#TjG(9N*h@1!@6lLRvFGiH zjhf?m&%~}R^}H8ipUw5Wmt)P{{}SW%Sn)#7dn>kkk>|Y|`|ASFI}q!+#PbfuRxb6t zL$Ozud)`;Es;fNj+t`_FJnu;Cy0xD7OYHMYJnv|%#igG2cYMx9_wf(KAGpF@0ipOm zSGj8-6z{#+T?L`|>Mia%2*qF9>aK)Py!tkGErjA@w!5n#6yLVPT@RtS{om{xhvN3X zBX1Up+y76xWhid{L*Tqn-2RWQZ9{SUUvhQ~#qIy8*fkWl|0!ONP~85nW_?0&``=Ox z2*vIHD>N_^KfK3XC!x6gpFKu|;`YC07#)h+zpXzu6t{mIeOxGR|GM?WP~84`;whoH z{rj>rLUH>CLT88K_Afk^h2r*4^vw^&?cZ2i6pGtFl67GyZvV>BvQYf7gYFs%#qHl2 zSsRMmKNPVc6t|!BzdRJTAJyIzirdfHZVAQhhb6BM#qFovZVbik$CYjg#qH-!c822i z0|UE4ar+zJ_l4s2S9Tu^#qIB0J{pSKUz*z!ire3MdL|UNzqay1C~kl6;N?)x5uB~hT`@B;z%fN_W*wh z#qCr0(NNrOgZ~bBS%11eG|4vxf8?^$!tTm!s@ir zC7!CbO0<^NTDV_L+^?#w6RnH2v)!*z);c8Gsn+b*YWJ(!Lig>2P`gaqUNtA#3$@p% zXD{iX@wM+p$IPXPSG(E$c@A~bORja7Fw|M&UOT6Y#=|zcY77gx(M@Bly|t4y9*?@w zU1O46f*!%BUf&J-P1iU{&-8brW@t!~`}0!6{RvOJaE#iyPINCdd!2di`P%E;Et35T zH}RuhC@a(?vuc{3StoO3%`E5E^O72SX=x|BEQN=pk~A>?Kx!}C*k{j{`RzkTTa9XlgLjgqH|eIm$#lKR z#7isQWQN|PUMtg`6t1`&u?%^;X5&p0$$`km;VWaoss*XBYrt(_IhuF|8{RlRE4 zd#oC+bn%jEKG4g3Osci5)atr7Tz&OL&Sogzy?zb%totzLSGALCu5mr7)}_5_xeq-r za3Ay>uY2vTwP$4}-lw||?uy{a-LShqQ$y@vrjxy&Lqo3Pg%!u()rQ((g!>ipM%#fi zhW@W-468U}ROK^<{jX;XuQ=n3%4ZBOKclXD&-Qt(;?G-fNfJr_u}j8NO=sKpCc0CS zLVsmucp>-XUS|Ara&k)wb0?L~&MhsOkXuqvI-#gwc1dwr(S)+1iMbO>7R)XywlJY+ z;@py=(n>G0*LSboDR*|s)R|Murp_z!a;Fr}EXpmMQ8Yg{XGZaa!Wp@xQwmFpa!ZP4 z6_pm2<`%UsC@q^iacXgHS#j}<2~!HE&MM8FJYhmXVad$g{JerT1+DX1=NIJXS#0HE zt69afidq#Fj-T2pKQE_ED|>N{d+~o>lsk3Sgc)-u7Uj+?oG@kTtpDFHM(Kjm${&fz zQ*wKjOq@G)R&np*lA>1SAB*{AC5aD7@DUkOQasIl%u92J&n_&P-f!-#f)VcbGI_|1 zxupfedbS_b?*GQsG_SC%$Ua)07hKVk=FXaspO>FA!6+0=ESgj}cSc!3*@D?cr8!ef zn7g_rPMuZeh7&Zrci#ecF(>pco;kC4mTT^&8!%JtO$W(ypOeA~oqn58I9&CAdkTlD z_>)69;cUNl*KoMXKzE-lR6U$#hgi6g9jb(and4sEI$XUXf)lb7z%Kojj{(VncVmCEi_cU9S9oycPEhzsw@4dZ{C%=;5x$uRJxh_zx9W^Pto|flRbBfIBRlILD8&i|IJ%{ebT77ElK=Qa(_U))B2uS z(6i65#D#Kh^bvG_KJ;9l|6DB3e!mS9|M@=*=U4nLdxs zEx*Dy9^sf@0p9&a^xi>O&duH81aG`TZ@%Ljv^-u|0Xn}QSAB(JG`QbKa30UtH4|J# zUtkHM?tSA1M58S0?7z*Q0Ow71!@;)CWsq`}*0&HJk$kY8aSzY+p> zJ?Y(+Uox(Z{9gL)+jU{@sZ;r@xDT;DjukhBZSOJQ>pozpa=WfFEqBi9pLid5-)hn)hu2!zq@@ulA`;8WtlXXON zE}v%X#!1PY!y9%8gAbv5w~1%mM}n7Cyotm`vMYOp`&6&j=R|jXB#K?hiO*iaC#}Ba zXS-`aZ?WPMa2>mkkX}}PUAn6vcn=je+|81Et;8EoyvSX*I?H`h(R1a$5$7&A-`y_T z4P;61QOOSu`ixqkA-{q{xxfkq?vu59`=wKgOUlYWKXTQXu*8*KetnmJCU-ZoiOXQu zNkWkOXavtxB2aOa=T}_k`4v|>*GRs*u!)o1r~1T^k9fZG8@$zuE42J~UvWLU3!#ru zzPpnWoZ$YP>Y4HnWxf-o*9&g*6Bj&RXSi#(;sfoT>pys8!`_`bHMD!#Ir$Ckes*5R z)@>U$D=C^$R9ITnykV=E6K2otHo<-5isrYP*`|#PWmD$P9Pf^kW)v5ewQ_gTySb}p zq6PPwlV;Cr*Q#`OtBLvTT`4S?Fr}Nj*FLXftC=}7-TnR+6H8~em^8a#tH}*po!+`( zD|bh;+XQz3T1}c+R9ad%xv15QqFIy6rgY15DY!?|%C3F4>=vqQYVoXArS1;1JC?dO zv9PSLdb^8s-Pk z6CZeY!>o%{aSa99%RkvAa2FK(_tQN0O)Ku2!pH7Ro!)PF`DfUC?ul01tE{*)S#e*| z-7AGp@Tb8pUb$!PhgRH0taJ~NyP*|#2l<1M&ke5KRSZ5t5*gelOneCJj;QXNCVs2I zAH(wBK7Z`WQDfTfkWMeZCFFi*#eKtyyN3A{H`5nnhf1)b>TvXf* zkXtpV)cs>L(o^%CWBi{Ew%~DcSq+SmhV{ z_876!ldrEpkbHZHSn0`k4-c~{ZTnh9HMi|68o`r$_*m)5_Yz-LEHA$2zRXqW$@kpX z?JGU`Uga<1*w;7Q*YYbp`ChEjvX}q&()gbHa#5ux-^;GF?DeaA?ki7;-?e?*v)$#l zuVV5Pw`cz6!|29kUgL@X3ALmYux_5t~j;(b(Sx5UwB-ytq?C8D@XqViM z)pe|GNB6=;c67h(X6knR+w0laA??^r$6h)P(Q%}X?h65l*PEu}932+xX)dcwm;VKSN9vR9dci7wPQ{9d$HpQI@;IYZ1>f1jQc&~>IBC=?kjAz?W=iqT+<*p zUZvyf?gMN6Lmg{04)zH;j&)a@y?m;UH@GXn_FX!D<-Ry<`&S)vS_Qj{j%DtOvX?K> z@!|YnKd+2 z!EUPKxY5C$spCy&1^Zqdzjc2g?f3VGj;#xV-Cf7|g~48~mX4=R z3HB%*H%trmwK~2%BiNtmShqOX&2=0^VB#wl>%g=y>Fk zVE?0I`%8n}TgOEkgS}eEr>+S0YdWTE3U+lJ2X7Ac7#%O)66|d{zP~ltU+UO!Td-T{ zIB9#ZOLg42BiIk=_|wh7KBi;G+k)L!#|w4_`(hoRxii>r=oq~_*fn(=a&NHD*73^S z!QQUpfd_(pSjXcZ4tB1NQyvZWTpjOxJlK!u_{*MPhn@_Mou3Yl{dK(X*5U7+KpSA)Gn$B$kQ_BT2<-WTkA9jEON_PILldMDVA>G+%bUZ?%} z@!t=QT@M7uQ*^xOqhPPs@r8rI-mhckXTh$chuovif&yiq1q2tk?f*t-jIG+4#a6C=NWxogeQXTiY@3h+Q?;RcEe+Rpsj%WNE z>5YjQ}^9i+dt^o%zX*mb~_zsMS^{vj`z85)Y{9R)bUUE9b4NG_ajqw z?BTw3YsW!4u5jPOwY^ctm)$pWZNH~uw)?KG?FKrIcHiE$U8Lhy_kCX5x9fPweZ$xG zk2;>@zVmClgO0Ns2K#&+?>|1+PwQCM{mlw{{pLF6*)i;S-L+4(W7P8o>o{Ef9PRNs zPF63`o~Pq^>MOL@=(t{ei;lPIc)yNM>-f5kAL{tEj=$@e?7ly1mp@C#`Z~6-qx*fd z)p3B1V|AQqM|a*F9o^lX#OtT%7}K$;jxBV|)zN+WPP~3+9ee87SI4t;EY#6`I!e6$ z3>`~#JXgo{I&Rc)vyNMJ+@a&GI##ixyRdO>cSyW_ejlZFf6o2>-Q6lL$^B+(@p?I> z3ucxTj`wm(%SwXd6rOWm4k+_-?D4mkGrqLc%W+>Z$g!C7->)Yo`b7IOxBK40q+)kU z;`zey<4cO>1!o1tedDn5EG)6R&w9JTYy6*OhJD*lZ_!;aFK2@L9#xV121up%I;o^^ zrhBEH!v^IPmX(!E9Y43sz1jcIPwuXx`_t~e<*qZ_U9*0PSp1Ov-hVGdf?w7re{j&Er z!2RMfxM#f$?$<)+nJ1p><3i=P*U-JaTU@ZWXCDLJ-U#R6wdd`Lm(6j{SAKi* z`-Kwz?d{nkNZ#J6O6Ry|y>agC*`E`hczerSsQmU;ReF0F?q$3^`?JV7_BLj_w^xTN zyVA?9bkA3Qdz;+bv+Kz&pWUAD_HJ^|+uJh__H=Qpkk=+qP!!*Pb4Bzbaq8>nr_!?RJjK_mX?w{q|%DT-C2;zxw^+gW?09J^DH4?XtPktN;}Uc5$+b)7T3dG60?aJ?jlvfT$L-9B-w zs{GM(J1JCUp*^k+rL1$Gf|HWM$0Bx!tZ>nv<}PT`pjz&6n)`NmxVD4l+YbgLonCuf zB1Iy$Qo?oIAMvD=$OiY3O->Hmm*$d^BTd}Neq;9ve#@#o-K+b@+`IPks@Y9IIPtkC zRArZYXH}AuPYl~%yo}ht?$%U4vD3iKd@s3~W_>qXd&$i;>$%y+{T~H1>$=(2OKzcA z$IW(La!bwQ+-&duQ9{kyZg%jJb2MwY+0jeR)vW1eC-?6fXx4Bu-(9SH?drDOZM3V}c9*QJcD8MI(b{Qe*>;z$y>{HTyKo(}W47I;>!_V++g-d)+8MUp;z&t9I13yL{cWQ*FD;cd~YhZFl*)Ye#Im%hyA@ifwoKdTNJlyUW*0 zJK46oe7&`O+wSu9(N1!^jk|n(wL`YuDqyiQ~Yn-^`Cl|yP-)wH4rk{-9jbLh?pD`GCOR4 zVLKsYj!u=35={vy)s&DjO$nK+DIxPTCFER937M}cAqzAmWT7TP&eKN7B5j16uZ@rk zv=Opc8zC2JBV>s-LN3xq$Wm>DEYn8Fa&3gH&_>8gZG^1SM#ySygsjm<$i>nRNwGpyGI}kF<&u}*xsW-V#Qpv@Ekal)^a%sfmn2;;N_Lun+Lax-Q5^|NM zgly83kgGK%WV5D(T%#!=TQnu)T1^SrswpAYX(Hr$ZG>#oM#v4?2-&WUkQ=oTvO^mo zH)$i}W^IJrqK%MSwGncgHbQRKM#xTWgxsNxkUO;za+fwjc4;HzZf%6zqm7VzwGnck zHbQo52SPUbx$gQ;U17H&mj^d)GaM*s(BO&Awohl)ZYD&msniBH3ri479 zDIt3_CFDs>33*CWLY~%?kY_Xz@~k#Op3_Fi^V$e`K^q}2Y9nN?HbP#~M##(B2zf;t zA+Ks9BBFLdZd#Dj}a}O30_067rd*gdEb8kk2(GBS{otXXd~oXZG?QMjgarP5%PmJLXK!7* zX>9#OVmeztk(j~OPb6lt`H93BfuBf>6Znb5ECN4~m`&g(5~~vUiNtCIej>3tfuBgM zLEtA6YZCa0#99P?BC$4spGZ88z)vLBA@CE4bqV}LVm$&skyxL=Pb4-V@Dqs*3H(H2 zBLY8>cszlhNIZeSPb4-bI3O9x$w?vqVFx6dVmB>*C{T3NJy1?=5{eivQ`9^ZwjVJ} zC_0JrrKkm4idwRzs1;j^a@bOo%a)=%wiM;FrKmMqirTPI)Rusvb_5i)C!nYU0Yx1N zDC$H&QD*{*x)4y*m4Kpd1QeZ2Kv8!Bih2-G)RTasUIY~NCZMPf0Y!ZYDC$Q*QGWu8 z1`tqm3L#L`G?e%|DA8?pQ`Ag~PB2oZh9c(66b%lA?MGA-icaTzDH_6-qM>Xl8pf8Q z;cO`y!Iq+tY$-Z}Ek&c)QZ$;4qB997I*Wj!F$5HiC7|eR0*cNdps0X=qHzQi6%tT1 zo`9kW1Qbmqps0v|qDcf4O(vjd3IRn^2`HLIK+$vpie?Z{G?Rd$S%g5*z>we10g0x# zFV-awlAj5m2<6fTA@7 z6kSX}(OLqE))7#22?0gx2`Jh?K+&ZH6kSF@(MCd`Ximsq>wrX;yGPo|B~r8_@i;3K zF<+)=Qz&ddBA-xnHRnswX0{Yv!{yEk#?|Qgj_#imqo%(Kfae-M~iCb^?lS zB%o*q0Yx_vP;@f^MYj-8bSnWxw-HcuI{`&I2`IXQfTBAID7uS)qFn?O-AzEzJp>fp zOF+?m1QhKipy+-AiXI@K=s`lD=*p1)rUMe~V_*8cN{XhMqK85e^JR)23x(~USV$;( zob#pV3APmNVN21IY$^^UBcSMg0*XE$ zpy&VrMIRCZMURC1TJF2=(J6LY^r#elZ}+Z03PsG9Df%=Nwtu1{q3AQtm!d;#Df*l( zMPIO`=u5T~eZ`id!)z(~nk_}&u%+l*Hj2I@py+!7ihdxV=m-HtKN3*%69Gj(6HxRE z0Y$$OQ1lxCMZXhJbd-RiKL{xLlYpYX2q^lSfTDj0DEgOxqGJRUc}eAu^3xOFj|ve` zltc&=9Sr&BI3Urt+~03W{zQsCvfCm*DPq1%Q6wpB|HMl|Q3~fvQ7T)CqHHNjV@pvw zTZ%H+Qk2P-q8M9>;%q6(VxuUVfTF4d6jdXjs5${fH3%rGNkCC80*Y!AP;?vtMRf=$ zs!KpoJpzjA6HwHEfTD&36g48C=y(E(P9UJDF#$zQ2;3H(NI+3jLZB#|!s%B%1I3{!VfWDH`Rz?U_6% zDPq1%(a@x@{S#9OMZ-8>iiWeLXark|MzW>o47L=FVoT9zwiKPomZG!RQZ$B*qOk-N zolQW|IRq3H5KuIZfTBVIipCRAG=YGki3AiC5l}RVfTGC+6ip$ZXet3k(+DVMgB}L4aDY_;pd{r|k+QRu#bS+zowz8$@I<^#D z&z7QXY$>{dEk)beQgkC*igvJ3bQ1wZHxp2F3jsy95>Rv-0Y$eHP_&bPqB{sEx|4vS zy9g-SML^Nr1QgvvK+(Mf6x~Na(QX2Y?kAw=0RoC1B%tUa0*W3cpy&}opy=u(|4|1d zddR-&xLJxu+HKLJNfGm9iuNRh?Vm_Y+!j5_`BL;0TZ*1$OVKlIDSDPIMbELN=y|pj zy}*{D7uiy@myM#A2q=1)fTC9jD0-EEqSpv0dYyoxHwY+tlYpXq1QfkRK+%2ziryxm z=p6!z-X);uJpzi}C!pv90*Ve0Q1l@IMIRAR^f3WN2MK|q$CLb|7EaO6_DKH;DLT{c zU4N1kF<++W^Q5r-6PpP|UvRz@eaV)huh>#_m@P$Lv!&=8wiJEKmZI<2QuIArihf|D z=m-HtKN3*%69Gj(6HxRE0Y$$OQ1lxCMZXhJbd-RiKL{xLlYpYX2q^lSfTDj0DEgOx zqGJRUxqs5|8h16i@2I;g(Ei$Kh=8Ib0*ZVBijoN^3KIfFpC$PN9FXXJc3X5viu%~S z>neW4e3_!CAGUv@HK8bt^Q9=AEkzk@DavF^QH(7`akdm?v85=REk#w?QdEtNqUr<` z)gYj#CILmY2q>yeK+$mo6xAW1s4f9T^#~}cPe4%v0*V?EP}GQkqT>lDI)Q+q#sm~K zA)x3)0*aavP}GcoqUHn?okR!}rTG3O4oGyb-4#mpgGc)B+ig(`KVrU2QLZ1hf8sZx zD39}{D4#7wt=Ur4hAl;H*;3SwEk*6wQq+MhMIG5v)QOFv&IA;7A)u%$0Y%*iC_0&d zqV5C~^&p_ACjmvh2q@}JKv5q8iuw{z)Q^Co{sa^aAfV_J0*X#0py)ILiUtx;G>Cwr z!2}eYP6!mW^8L3Qkmv<=S13n{I@@j05I+ zDFhTvC7@^;0Y%dZD4Ib)(M$r0W)VJy5t<9sQ)o-IY&*iv)@TZ*=`rRYYs6#YNM-FI|Ub>FuAJxq2cnUtA? zUZhAbNeI14FVedxXb2FRKp+VSiX9XXdqY7K6+y* zH|=46azey>nWD4=-~Ne}Qbp;UFGVr76vf$6l);vwOtutNW=l~OwiH!mOHnnp6jf)V zs0IN=H3=xHML$TMRf@%sz*RkeFBOa5Kwd?0Ywc7C~8DNQDXv%nh;Rb zlz^gU1QazVpr{1_MJ)*^YDGX%79miSk`P|xfJF1`wkS0rc%=WT-Mh|Ch?p-^)F#2d zsh1SB<$Nh>$Cje@Y$@u%mZFYqDeAcWP0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_WPnSi1}1QZP>plApIMMDWF8b(0TZ~}@( z5KuIdfTB@^KvC<2@Y4=R^aD2&a;2!X-7t+#h?p-^bV`D6|HM=2ZP9qnm!ebIQgj+y ziYBn7Xd+vRPG?Ke8Eh%aV@uH_wiM;FQ8bx=qA3IvO(meHfPkWD1QbmtplAjGMKcK~ znngg-nFJKgCZK2z0Y!5OC@LhNXdVGY^9d*_BA}?4fT9utiWU%1w2*+Jvj~Bru?gXX zzE063`w7T6DcWJTMT-(5=F1c_cO5m0nB0Y%pk zP;@N;Mb{BfbUgt@HxN*CBLPLL2`IXWfTEiTC|W~6(ON>F=AO|E`-TvJ5Ia2hG z{V|bS5+dfy6s=G2?Vp${RdhS&OVJ%{DY}y_MH|>sbQfESHnOE?6I+VzW=qjMY$>{z zjiSv26x~Na(ftGzJwQOwg9H?9A)x3X0*W3cpy&|-inbC^^e6#E+XyInjDVuY2`GAk zfTAY}DB4ay(NhEzJxxH-GXxavAfV`3LZIl@gz!}kNVJtbEW1sLUa))D&m~06mnnKN z!MA^+uvF1YoG(Q$v!&=2wiLa}mZI0#QnZULMX$4^=nb|My~&oM-E0)SML^Np1QfkP zK+(Gd6un14(fb4xeLz6bhXfRTL_pCV0*XE+plB}vMV}B*^eF*FpAk^BkAR}j2`Ku4 zfTAx6DEf+kqOS=k`i2lF+L;i3-vNobiN9|RN~CZOmD0Y!fjQ1ll8MMnuJ zIz~Xz-vku>LqO4S0*X9e58F``BA}=e0YzZ~iV_GY@(CzPB%mllKv5C_MacvdMF}WM zAq0xPPYBl;>J;5zU(tS$q9prqNU9$(U#2MT`}R+ymMY5Nd@0IgOHpOE6jfnMQB}4S zRbxw0b+#1MU`tU=wiMN3qo_6kMRf=$I)Q+qx&#!}BcP~00Ywc6C_0gVqJ{(%H6oy> zF#$zQ2qljT(P#pS#t=|6mJldv>xVZvAklVqhq|2_cO5m0nB z0Y%pkP;@N;Mb{BfbUgt@HxN*CBLPLL2`IXWfTEiTC|W~6(OLqEZXuv(9RWqR5&}i% z`r&pCNOZG3EIUt%eze=7+x&?6GDUa#zWo#NrHVFiz7*ZXmZFVpDcZ!AqPy8rbPrpK z?qy5SX0{aF$Cje|*(iE|fT9NpDB40m(L)3jJxoB+BLoy}C7|e00*bZ~Q1lo9MUN9u z^aKG#PZChHoq(dJ2q=1*fTCvzDB3|l(X#{;Jx4&%^8^&_Bm|0X_rqs9AkjVcUB^45 z$o<;@?g5)0F<++W72jWTniRdt`BL;6TZ(qErRa6G6urTgqBq%6w3{tOZ?UE5ZMGD> z!$#4&1QfkTK+*dI6n#KI(T4;SeMCUf9s-I!CZK390Y#q>Q1mGQMV}E+w2y$I&j~2{ zf`Fng2`KuCfTFJnDEfwgqHhT(`i_92?+JmTm;CS!2P8V#;JhqFz3nU74}QdanWCS4 z|8w`(*O%TF{lfWDbbu{Izp|z1H?|c0&X%HsY$-a#mZCq{QgoOtMMu~u`jdd7zX&Kg zN?60s%!n0Y!-f6h#OqN+O^rnSi1w z0YxbU6r~bSltw^NIw4TB-w!9A?iAV2T@!wiqW$);Kb9CVU#6&XqTe)6imGtF6jfzQ zQ8l&{RcA|44Ym~3WJ^&kwiMN7OHm!R6rI3EQC$Lx>Jd;>pMatU1QeY}Kv6>iiW(76 z)R=&xCIl2UC7`Go0Y%LTC~84KQA+}fS`ko`MLaLvc%M|)G5)QlP^V`IbVvpu%)OgTZ+1|rKmewicVrn zQ4h8h^<+y?FSZo*W}~PN0Y!ZYDC$Q*QGWu81`tp*kbt6-2`CywK+#|ViiQwSG?aj% zVFVNnC!lBq0YxJTC>ljT(P#pS#t=|6mVlyh1QeY@K+$+Ypr}J)_!L^9E zY@C`HF<++W^hE#RDN=L>=Sxu@TZ$&Jr6`{*MU&Z5G=(iiQ`u5fz?PzEY$=+~M$rrc zie?f}G>d?uGYKe~O+e8c0*dAmP*g}j(L4f*<`YmV>j)^io`9ko2q?OdfTGm|6x~EX(ai)Dts$UjEdfQh5Ky#^fTCLoD7uY+ zqV)t6-A)J;U62^AJIyKTVt1%7l%jJ=AFw4x%$F(JnCSPIAw`=wUyAN#OVK@SDY};} zMVr}DbRS!a?q^HU18gaJkS#@9*eH64fTD*9D0+l|qOAlJJxV~)HUf$sBcSMU0*am> zpy){ginbF_^b`R_PZLn|3;{(u2q=1%fTHIJD0-fNqMZa3y+AVDSDmrrRWW|6urroqTOsMdW$VZZ?mQ79kvv` z%a)?|*i!U98$}-wQ1l@IMIRARw1l1QdNrK+$Ie6zwCR=yL*!z969J zO9G0%BB1DN0*byNpy*oyioPSD=z9W+ejuReM*@oW69PrACWh~EK%#r?E81&PbhSO~ z|0ywIzD&`tiT-P|rRX=#m!jX zivA{`=pO=#juTMiMf9*8MIi!;DiKf=CZH&RfFhrOqC^6UA_NpA5m1y&Kv9%{q7(v( zQVA$ZBcLdqfT9=yMR5X(G6;d9UlPLy9FXWocJp&UiX!$EEi)1^U#6&9#Lp;{qUxM4 zMK#z`RFf@5wb)Wrn=M6k*iv)?TZ-zkrKlcTit4jb)PR7Z6A374NI+2|0*V?FP}GEg zqNW5CH6x&?IRQm22q z2!Wz1k#GkGBs#zz=~s;ekMyhBBmIt%i1{)_T_gS}^QEX8=Sxv{wiKPjmZBbPDeB3V zqF!t%>dls-K5QxK%a)>kY!vk;plARAMFR;aI+=i?K?D>HCZK2t0YyUzC>lmU(QpEa zMi5Xml7OO71Qd-XplA#MMPmsl8b?6UDFhUaC!pw50*X!}plAXiP}DgRUgCg6+t?Se zE>iS&*o}#ii1{)_lOp~t#Zr{d`BF5QEk#q1-*Q!Iq+#Y$=+> zM$wrB6wM}}Xbu5Ia|tLaB%o*>0Y&o(C@LbLsF;AF5(0`A5Ky#`fTFVqC|X27(P9FM z&L*Jf90H1#5Kwe30Y&E#P;@>4MHdhPMQ239&p9B`%k7I;o)mSlFK-t{BIe5!EsOYH zx_`X3^d}&faK02>%9f(#Y$;m7mZFtxDY}d;MXT6SbU9m!u3$^im24DUML^Nj1QcCE zK+&}X6kSI^(e(rr-9SLmjRX{}CZOmh0*Y=XplA&NMQaHtx`lwEbp#aMN&tAF!q9L$(xs#75B`0*XE+plB}vMV}B*^eF*FpAk^BkAR}j2`Ku4fTAx6 zDEf+kqOS=k`i6j_ZwV;+j)0=?2`Ku3fTAA>DB4dz(N6>v{Y*g7FN8qR>yhwv4oLJl zQ}l)u?XcUT1CfaNGDQa?{?;W@bcpk%=nu9O9cD|>5w;Zl$(EwO*iv+qEk(!JQuH@l zivD4v=r{pIUXmWRqbNi`Q6&P3!UPm05K!b3P?ShOQG|e^Bm#<(2`GvZP?SPIQ7QpN zX#^Cd6HpW*peRm2Q3e4;nFJJ7CZMPaAyD*NB)rD~iLSKoI{q$2g+{7sQp9|jqMAwm z(etFJ7UxS*ZMGEEVN1~oY$>YCmZExWDXPzwq6Ta!I*~0!4cRDaL_kqv0*aatP}G!w zqGkjXH7B5`1p!4Z2`FksKv5O}McD)tQ0(f#%lkQzzBBmLI)6|GBB#C(~elal;i7fMkN&X=N|Y$@u+ zmZIKlDeA+PqP}b?>c^I%{%k24z?PzcY!sbLK+zxqiUt!lvX(I^6nMiWpphJd261Qd-Upy(6=ipCRAbSeQwrx8#zfqHCu|VVWa3;0*bC9 zpy+x6if$mF=tcsHRufQk69Gjx6Hv5hxx{H9KjRX{JA_R&qNechwfJ7_VUlVev6g4wacPB;6mnph0$*;Uzitgup zDSCh{MGvy2XbW449%4(;!)z&fge^r|*;4c$&1QewbP?SbMQ91!d zF#?L>1QcZuP?SkPQDp*(st{0Am4KpZ1Qb;#1d0wNg?Bn2(YNj9=MO2GV53HI#C(~e zI?4XmS4hzboG(Rn*-})GEk*U&Qq+JgMJKYQs3BX58nLCQFXfTDH;6tyRyr~?5-9SJDvL_kqz z0*bm2P}G%xqHcshQLW@~^h&4bibMyec5?7Y|2Z4olOyKK6!l8>TV5?iy*Xcs`mm*_ zFI$TGv8AX#TZ#s-rDz~qicV%r(IB=I4Q8Wg2mwVy2`CyyK+$jlibfDnG?IX#Q3Mo? zCZK2x0Yzg8C>lpV(J2HJjVGY!R04`lBcNyk0YwuDC_0^hqB966$|Im?5&=c|gg{Y` zIHi{PdKfx}^`;k|XBJ6irL^=U*#D(>Y&?X0WAbCR>VTv8CutwiL}~OVJ#* z6wPHzQ6XE3=CM&UpMatw0*Z=o+>ZUCWlD>)29sJsU+g z5Kwd@0Y$3`D7uM&qMHdQT0=n5S^|o0A)sg-0Y$eGP;?ssMe7MDx}AWcI|wMclYpWP z1QgvxK+#45iZ&5YbTWIS0Y$qAD0-cM zqBjUAdXs>n-Go5V{mJ1IS35=POwj{U)Wja6y_Fm>U#952WWUeNQuIFOOVI~xDf*Bt zMIW)HXb)S8K4weNUbYl{!j_^>*;4cw8%6sFDEgd$qAv(2`jUX6uLvmmnt-Bj2q^lN zfTHgRDEgj&q8|t-`jLR5{R9;KL_pEc1Qh*3K+ypLihd=a=r;n2ekY*lAOS^(2!Wz^ zlEX6`kmy79r_|n+qJ8$G**}sa=F1fQmF%xrD@8{+Uy6>grRZ6jfqNQJ5`732YSk1QaC_P!u7cD2afgWCDt!1QewZP?SnQQ5pe7=>!zT2q=mZ zP?SMHQ6>RJl?f=SLO@Yf0*a~;P*k0Oq8bDg)g+*(79mh{BsqM)0}}0P_ly3NqHFB7 zsCG1BzD!ZQsQ>0VDXP!;Qq+JgMJKYQs3BX58nLCQForKmX@MJ)&@ zYDqv*D*}qL2q?-XpeTocqSgcyPSFQCjyE(6HwHJ zfTFGh6m=t@s5=2gClOH8gAgb>AsRmDfJ6`3%}?EE@JRnX8$F{D^JR+qM*XVmrKlh0 zOHqHe6b)cY(LlBooy?Y^L2M}+%$A}dY$+PbmZD*76b&b!XaoU8BMB%PML^ML0*b~E zP&Af+qHzQiokBp-cmj$}C7|du0*WROP&AQ%qSFZ|I)i|sJOYX)5m1y*K+$9Zilz`y zG?fr2>KzStaX_N?xS7yLivG4y5RI5GQ#3Q`Pq;&hW^uk0oynG>*=#AA!G6wPN#Q4w2;irFYCA)sgh0YwW5C_0OPqD2H0EheDoYyyhTA)sgp0Y&E$P;?#v zMduSxbO8ZH7ZOl(5dlRP6Hv62fTCpt6kS3<(WL|wEhnI81tCy0JsQ5i0g3Lio1Ym{ zRNKCyt&B#@mnpg;>aX7*MOSjZ6kWxZqN~|bbPZdIu4PNnb!;iRo-IW;u%+lmwiK;q zqv$3Aif$&LXbk~HYY8a2g@B@U1Qgv$K+$ak6s;$q=yn2%?jWG(P6CQH5Kwd%0Yw`L zDB46o(cJ_T-9tdpy#y3(CZOm(0*dY@1d3Kg!!J4@(Q)>T#>=Is#2)EC5RI5GQ}l4u z|8}DkJ;M1?w3RJIkFup`8(WGVV@uKFY$WIU0Y%RfP_&bPq8A7#dXa#lmk20&nSi2K2q=1$fTGt3DB49p(dz^hy+J_Hn*Xc+@&bQmZC~* zDGIZtD1j|SK3j?s*-{i?qbP}hqGSS!q68GB5Kxp#Kv5b2Md<_-#Rw>h6Ht^vKv5PbLRF9M2s69Pr`Q^KD*Akm?Azo(9xQwS&;Pe9SB1QeY{K+yyOiY5|JbUFb=XAn@7M?lde0*dkpD4I+_(G&uTrV>z8 zKtRzn0*a;+0!95&!i}~#MZWz6q`wq>=3bUCBPC+KOwsHVzu&`BG>7x0Xf9id3fWRL zk1a*>*-})*mZD;|6qT^0XaQS_7P3)v76CJ{qEk)O}rRWB>6y3;{qSb6E zx`{1CH?yT^4I4#k2`IXSfTDE-6x~Wd(QO12ttX)9b^?m-AfV_@0*W>eP;?goMH>ky z+C)In-2@cfLqO5J1Qcy1py)mVitZ<%=m7$X9weY>3n5T+WlH!#2PFEQ{RHGHDVktk z(H=^Pm@iZGXo~;VHYwW1`BL;4TZ$fMOVJZ-DSDDEMcdg@^b}i)o@PtYGi)i^!A8-u z1Qb0-K+*FA6zwFS=mi3bUL>ICB?5|GCZOmQ0*YQGpy)LMigpoD^g01WZxB%QCILme z2`GAtfTFhvD0+v0qIU@>dXIpj_X&ZbM^eInI3UrM24|}j9ktt{4^krL%M^W_;#Yq{ ziuQ886n(;$qEFdU^ch=<_OYetbG8(H!Iq*g*;4csTZ+DBqv#s~ioPYF=sN<6z9*pQ z2Lg(IB%o+N0YyI%Q1mkaMZXYGbbx@OUkNDsjew%x2`D;9K+z!rivA#==r93AM+hkT zlYpYX2q-#A2o!yk67J@JM1Qh-*L$RBgpoRy5;0$<$V>H4-!4U=R6UZHqDpKj3bUms zfh|QoTZ$6dQWRlJQ4(8Ql)fTHRI6xAT0s3rkLwFoGxO+Zl{0*X!`pr|eZMfC_Ms!s?M{gV>D$N`BC zvOh6Xl8pf8Q;cO`y!Iq+tY$+PWmZH&YDH_8@(O3eC#t~3- z3IRpq2`D<1fTGg~D4IY((L@4@PA8z~3<8Ss2q>CFKv6ycMUx3AnnFO)R04_$2q>CH zK+$vpie?Z{G?Rd$S%g5*z|?U1vrf^e_M@|trD&IXS;CpA5%Xn=3RC@@=cQ;K=S$Ii zwiFeyrKp%KMI~%0TELc~g={H0i!DWq*iy8ZjiR#&C_0CLq9p_rol8K`c?1-lPe9QH z1QcCJK+#166kSX}(NY46mJv{N2?0fy5>T|9fT9%y6s;tn=rRI|RuNEiIRQmi5Kwd_ zAy70YH9W=viQa8@sOL)2lQynOjhHV}bX}^y-~}nVp7W*X2DTL4$d;njY$>{lEk!r8 zrDzRXiq^8F=oYpVtz)C;RsxD{BcNzK0Y$eHP;>_YMRyWVw1I%4y9g-SNI=mh0*dY? zpy(a~itZ(#Xfpvt_YqKZKLJG#5K#0W0YzH~D0+y1qK646dV~-tx+XPzvjY-6!@lcy ztrUH3V{2-}e3_!hQ~f7jlAsO3`PWFGc&-dQj^|MF%$5SKb%M^vv`~mL1Qt6)zNl5$m zBYmGOMTu-Fim;_9i7iFRY$=Mer6`3hMX78lN@Jraoq(bk0Yz~FiZTc&$|RtuG66+Z z2q>ybKv6XUimDS(RD*z`ngkTpBA}=?0Y!BPC^~_FqPheW)gz#&J^@7y2q-#{fTD(k zKv5_yJlg?@K5uX;r3H`CD!Z2@G)jw@FH_Vk&A0Y#@1P;>?XMR^1iO(LKupMavt1QbmnplB)qMFj*DO(URa zIsrv92q>CKK+!A$iq0gUXf^>wa|nT=!D-Rvz0Yw)RP_&eQqGbdWT|z+7r34f$C!lBr0YxhbD7uV*qE!SGT~0vJ6$BJrNkGw6 z1QcCOK+!dXK+(Lk@JS9xw5omAalRC-v)iI;(<0`}6y2ES=e;LIt2tkaZemN(&1@-J z!{hEk*0tQgka@if&^|(RwzDZYQAV4g!kqB%o*m0Y!HaP_&VNqD=%8-AzEz zJp>fpOF+?P0*dYHwBd!+wZTEu*rqU~w^h7Y9ZDbAOor`b~U3|oqJu%+l(wiG?bmZIm` zQnZsTMK7?W=tVY)ULv6AWde#`A)x400*YQEplBBXMXwW3^acS%ZxT?nn}DLX2q=1+ zfTDK@D0-KGqW1_WdY^!z4+tpwkbt6(2q@Y^K+(qp6zwGhik?Udzv_TQbM4PvKPg4g zR5w0Jis|s0~|++Onmn9b1apvr*K6fTE5B6m=q?s51dYT?i=ZNPbLRF9M2s6HwHLfTF$x6!jyZs6PQk0|+P@NI=oa1QZP-plC25P}Dp66rD~$(HR63rqNxNF6%bG~jew%*1Qg96 zplBumMY9MfI+K8+*#s2LA)sh30Y!xb6wM<9iiV|!zi>dJ?d;E850|3pcJF$Adc=I0 zq6O)G_)95T$oW!q7F&uIv88A+TZ+zROVK%ODO$poqI20&bRJuZ&S#_O0s@LIB%tUb z0*WpsplB%pMau{%x`cqDO9?1iPC(HL0*Y1=P;?mqMXLxXx}1QbD+nmMl7OPC2q?Om zfTC*%D7uz_qU#7Kx}FdyDozhKb3mdu*lkgX6dkvR{WqjX%$F&;Io&_`Ybjd8`BJo& zEk(DmrDz>nif&~~(QRxgTF;iE+u2fd2V08nWTR*U0Y!HaP_&VNqD=%8-AzEzJp>fp zOF+?P0*dYv zc5t4Sq8>K(rAN${Df%kifA4!K`kM2l=o_{aean`j@7PlGJzI)?U`x@DY$@8$mZG27 zQuH$$MZXYGbbx@OUkNDsjew%x2`D;9K+z!rivA#==r93AM+hkTlYpYX2q-#AK+!P* zivA{`=pO=#juTMi#q_WpMIi!;DiKf=CZH&R5GeX0J^Ysg60K!$zLcUpHvCw`e3_!; zm|uIp6h%2-ic;88l**Q(G`19_v!y7;mZCUYiZa+zl*yK&%4`%>A)u%#0Y%jaD5_3C zQ4Io$Y7$UXi-4lq1QgXFpy&hwis}+jRF8n7`UDg;AfV_(0*V?EP}GQkqQ(RiH6fs= zDFH>z2qs| zs0~|++Onmn9b1apv!$p5TZ%ferKl4dMV$#K>Ow$KR|1N<5m3~ffTEKKDC$8#QBMMj zdJ$06n}DJ|1Qhippr{`KMg0jV8bCnNKmv+RCZK2#0Y!reC>laQ(NF@4h7kfqtzzLz z9FXW+_82WoiYghY;jxJMGDV|f{>B4RG=}q~Xe?Wb#<8X76t)zNXG_tkY$-a8EkzU9 zQZ$h*MW?e-bOr%Mc?1+qBA_UrfTGC+6ip$ZXet3k1q2jLBcNzH0Yx(iD4Iz?(JTUr z&Lp5{HUUL*2q>CMKv5w9Me_(KnomGc5dlTTgh0{ASa_EM65Vb;#vdg`3+%S2Bo;AW zrf5;j|LHd=TFm)UbT(Ux&S6W@61Ehb%a)?^*iv*pTZ%4VOVNdFDY}S_qKgSAT1r6C zG6IS&A)x3|0*aOsP_%-8qLl;`T}D9BDgufwC!pvG0*bCApy(&ivge`oX@@c$O4J>|y^+v55IHMYqKKwuhu>9p_8Y zt!yc}jV(p%*-~^nTZ-;rOVOQdDcZo6qPy5qw2_UXO#~F(O+e8-1Qgv%K+$FbitZzz z=zao<9w4CTK>~`l5K#0G0YwiJQ1l1^MOz6ddX#{oZ3GlOMnKWy1Qb0%K+%%~6m2J< z=qW;=XiY3U-T{d&x7(t%Qgo4hd3!n*F<++WxtPEBuoOMd`BJo#Ek!S|rRYVr6urcj zqL8%4hnQ1m+iMF$BeIz&Lx9|RN~CZOmD0Y!fjQ1ll8MMnuJIz~Xz-vku>LqO4S z0*bu29=4+>L_kp`0*b-}6eSQ)9xEk$v*6lJibD3dKkmDy5Mg)K!@*-})EjiTxV6xAT0s3rkL zwFoGxO+Zl{0*X!`pr|eZMfC_Ms!u>s0|JUpB%r7v0Y!}nC~8bVQ4<1+ni5ddjDVu% z1QfL(pr|DQMXd;dqG&wa!U2iyOLlNl;`-D3cJDeX9x-30C^zm8{zr=1aK03^WlK>z zwiLBzOHl{56m?`vQ75((b!JOZ7q%32WuvGY0Y%*jC_0INq8$JuRBYbiQrV^ln1zD&`$xPP^0Z=ki8a0=&3(Rj8LoywM?)7Vlpfh|Q7*-~^m zTZ+zLOHm$MiYBp9lutm>WCDt&5KuIgfT98dilz}zG@XE=83Yu~B%o*(0YzsLP&Au> zqB#T<%_X3ykbt6j1Qg9Dps0v|qGAGyN(d-gKtRz#LZE0&Jp8Bw65VJ&IvXoR`F2}$ zRy<<9Owl=U|AR_Ww1o4e=v=lGoyV4<^Vw2#0b7bLWJ}RSY$>{!Ek#S&QnZYXqDu%U zx|D#TT|AfTE`eD0-TJ zqGt#w+Cc~ut&4|yJ0Q{7cJp(q6m7G|XwSwY=F1el5cj7CeG`wEFH`hG+`l_nihksLDcaALqMz7O^fOzEeql?|0k#zV%9f(v z*i!U6TZ#^{QFMraqCW^II!r*(5dw<-B%tUo0*a0jP;`udqQ40!`iFp`;{+6W8G6`` zq7VT^l?W&b6Ht^uK#@;CQ6d3F5dw;m2q;P>peRZR6nz&Dzu|yHpLa9idnuY?kMvVA zBIe5!#WMU~Qlu!(`BId@mZD6y6jf$RQ5CinRb@+2HMSI0XG>8HwiMN5qo@`EMYRbi zszX502?P|?C7`Gt0Y&u*C~81J(TM~UH6);@5dlSw2`FkpKv7cyikcBn)SQ5#76cTv zB%r7j0YzB^6lD`oltTy?a`U8Nnm{{dQZ_IwNAfOi{ZGzkRwCwdZ^( z>cEzwj%+FF#FnDYY$@u(mZGj~DeA_SqV8-dI*E;<9t0HiB%r7l0Y$wDDC$E%QC|Xz z`VmmnpMatP1QZPlXP(MSS{MiEdnnt-A) zgg{Z7jPPj=NHpCZqqUWy^X%UB*o=tzGDW9m_~*F)>$>!j{%M>qMHARkG?6Vur?aK# z47L>Iv88AdTZ;18QZ$(@MN`-)no2-X0RctR2q>CPK+y~Wie?f}G>d?uGYKe~O+e8c z0*dAmP*g}j(L4f*<`Ymj zEgCOH2kl#sXJ*iv*U zTZ)#mQM7`9qLl;`T}D9BDgufwC!pvG0*bCApy(OF+>r1Qe|!1d5hqguih>qATp?=UgfJ#>TA~5%Xn= z?#S>XRi)@o&X=MMY$>{nEkzsIQnZOJMR&8M=pMEd-OHAu&1@;UkBy@H2`GAifT9Np zDB40m(L)3jJxoB+BLoy}C7|e00*bZ~Q1lo9MUN9u^aKG#PZChHoq(dJ2q=1*fTCvz zDB3|l(X#{;Jx4&%^MpXr`iyWZ2PE3f{`CIsQuMvu7VXT4m@iZGa)v*&x)i;_`BL;M zTZ&#|OVKX26ur)tqBq!5^d?)1cC)4EEw&WB%|_8X1QfkXK+$^y6unPC(FX(+eMmsj zM+6k@A)x4E0*dw$Q1l4_MV}H-^cev~`v@rdoPeS)2q^lJfTFJmDEgX!qHhQ&`j&vA z?+AgS7c;^|4oLJ5d!+x86b*BD628xfm@iZGQ-*(SO)2`B^QGt)wiF#;OVO`vDf*2q zMZdG9=pb8)4zZ=^54IE?W~1l`0Y!fjQ1ll8MMnuJIz~Xz-vku>LqO4S0*bs$J#0r& zh=8I>1Qdk{C`urp$S0sEk$|EI0Yym!6eSZ-6eXZ2g@B?|0*cZIfubKX!jCy1(G%^q zXulK{+gG&o%!v6iMVXoYN42G>GUrQC6}A*rWlK>twiH!oOHmEB6xC!)Q7yI<)n-dk z9X5(iAfTu&0Y&u)D5_6DQ3C>sP9&hHApu2=2qK4{-eun+%E$~J>3?LmMQt-9=F1dy z%=GKkm7-3ZFGZc%Qq+YlMP1oa)Qv4g-Puxf5?hLTu%)OcTZ($IQPi7&qCNx^^(COF z9|1-E2`CysK+!+~icTh=Xb=HKg9#`aLO{__0*ZzaP&Ax?q7eiXjU=FG6aht}2`Cyv zK+#wNipCL8bP6F*)IKxZ*8z#1Z*V$D(G0sS8lM?4U#4hcre9EBicaTzDLR8KMR{x~ zn#7i(e6|!#W=qi&wiHceOHlz^il(tqG@XE=83Yu~B%o*(0YzsLP&Au>qB#T<%_X3y zkbt6j1Qg9Dps0v|qGAGyN(d-gKtRz#0*cNeplA^RMT-e2I-7u^a|kF}LI@O{mKk2@ zfJ9%kNBR?_XpMb&J2x|8zD&`Dnf|>eO3_7}FGUx#rD!Qzik7jZ=n}RRUCNfC{ojiOZq6kSe0(G>&~T}eRERRk1WO+e8#1QcCMK+$ys6kSh1(G3I?-AF*u zY66OGBB1DI0*clUP_&kSqFV?kT1P<9tppU^MnKVeLZImU%Mk-K&()Fu8VckpU@x1!6>D4^1QS81Np4Tk)do9mv73+M0=e3TVU(fT}#a?LOd7WY@jXbYg zY-AJ9>lwSTndkM5ebU172F4m@dESuN%pA`f5qlul^Txyuwe`I5v929FZ({7iPM$X@ z_EHzmn;J{&?s+p}qkDMX?AT4cJa1m?vp$|z5^LPw^A^R<9O!vVVp|4z-UYG4Lp*P3 ztov}!TOPZ3r01=Qy)xSKu8PIRdERxgvEw~&b!^RPp0_sk`9#mVE!H&8^X`nz$@jcX zv4^L4-sae!1)ld{tj7$`dnC4OmghYddu_JoZI5LXdftxMDf2yVXY7_@&wDxcGl8^LEDy&-T1`V_TPa-iNWH=Xu`VSg#8`Z(r=vi#_kF*z3zY@4Hy#<({`ccIryc zI}p2dmFFFdeSL-J9f`HP+VhUZ=U?kS|DpJ{>)jO)ivNA1y9Pq>J~z9oAQWG*)?Ejo z_?zq8l@N+oUGJ`iP<+B2?rI3d*KcswLnvTZiKI zFS@o1#qFQu>=cUIzp2-?_ar@h?r-tJ8*AveO#qIBxogIqXUl2Mk6t}UD?lb6qh1Sk)8uBVqn z>uT+E_v;jE-AdaaYxZk}`&DI$`*A|3eY$P0io15bPzQ~A_L7bozu1N8lzwsPt3Bj? zKZiQ&CAYdu80w<2)z0avvE4>Djk`i_bk`VdZ|x+FSE6q8&~TKzP|sjgt?Pz;(A8S# znE`H84~?kge!o<6zr#ykI6>_!C%U(qz0N}Se9h0@Et3868;7G_C?nK3y>d!8y>|N8 z>KV?h=T&OtrKFtXlIMl1dExXfDP2=Kr<`2beRB1ZBzJOq&q`wDP)bVh3L!TmXb26{Nq+g| zh^4tpXYV;)`i$>+8Tv@{PBODYJ!*0xn%2w+WhVBlabxeA_8u$y6)s+->f3s|&qS z2zN#BhB}Jv5lHfBkqNs3|`1J+{Uk(7|L$oSFYzqj*agB<$1qywjavLuH-xBqxucV>)(2y zXUE)5tq0~!4xa7MuI$lYp@-eh8`xrWs+LnJTZOT5DJ{8`iKIk@_(4p+LI+uQ&3+5Kj zoIbZ;YJGQ2m%h6`?R0ti^H$t5eCqm@eQt8yg(-dg&hFLn^4!^N+vEjrA=kY#PUz2D z>!r8WyZkM*F1_qi7tEQnICx8X-FCd=UJ4z{E`Ym|%HDF>J88%J=v)5DaGwIbqPxh! zr_sHY;F$^+p(CfdPhRN@-6vM(wJ&>P?(*8yV;O;&n{s7(*OJq zbh+ghtG8Ui&t0jd?+$Neq5{9AzlBQAo@KvxN?*0L-h`v9%hkK=650(x=_~arzo>oP zmEUXBfL!}e8~aaN`%k;lSIg!7=XNT4Yq{kh0fe92a-r@6(R)WtnGbif6TI6BRG#|?0PD_$t%CE-L0T5O0K&sJeynoNvUv+chu=z4*@27 zgPqDhWA5`AypJ}#vvLi&`PIcOzu{`D zx75D;^0+t7M^%2M=T^AZD_q+h-09^Mx!KDFjlI||gFEsj-6bwfTy5?KM=xqy_9=9q z2wuJXisw4zDlNMjJGl?Eu*_@ub>eOkgU_p@qBrNx;SD>1!Asq{Eq%s)CU{xdMRM=U zHT!)x#(gQ*>vN*JK1z#S$)#Uwf-f=s%FcGzfZk&HCEz-CpCP@h?7DPULGT{RZMYi| z_gbZIy!1uxy46|kOMsp$`#_w#;Cy#0YBy&^!Dl5mIOywNxrW?w4rKz%6}T_gdi%Nd zc`Tk$SX5H>WsU35sFhy(WmkOJ7hw1MrS!tsl~ei~$bDLZXDV1IzwUF(ul(HdYoDto z*Inw;ligS7(j%YxTn9OLtL4{h*{7lW3UwEP560bJ2~KdoVf9Se=QKCCx=Vl4l*e41 z;jZTL&$xSTz_79P`*iMH-|kLl=hnA7)U7+UX;;5lQNiqj{NjS<^|R(onYW<(6!)1c zSd=xVZCe*gW-OR9*&V0NF3c~G zFYJ^xCwq>&gWqy$@w}GP=GD)dUO#JioBCPq9%c6_?gC^@n^RC+oIkxFYj(lh=_NC| zw{|JGBa&qd+_JA4B{K`>W)-`8#_m|`+SL4#{IVT=YRW(6F9B# zHL~mug2P<;Hp}lQ8c+Kim)~D3zn7RBh%Xi6Zk~0q%CC%oec6}1QssGh|NiRC-PH1X zsqnG;K*RfwF8ivRYj;XZFG`vA^80}0cLCjSbmqT{2m>; z%dYyeJB(%b1k3L9RrqaG{+prvE*sZ$`5m^hYcROi=MCu7r%U~2_8X^H(VY7I=1eY_ zI@R4<9>YV}(%(xwG;RLhe`mRGrnm>)$K8|r7R8cu_nj4c9M6+IUhkb=V`<_t|B{4D z!^Py9=bSJ^ZWi6m}2&GAeBQK13C_hmbPhl@sVcE<7eQCm;`&Lke zr?8hXwC z$Li=FcR9+fJz+9Q(TOp4qnV)Y)-mz2JDGj=S9_*7_$pR%;aOhB{7kSDd|krjEC}E5P;x zI)2w8*oSn?&I)!{9ZTF5Wv_psj!)zU`z0N{cEL{5vA?@Q?e$0NxT;gIZ_@GYF2Vjx z#~SX6x7Tm1;~71IeWs3g_6qhE9e?N(?87>??jP*#IxZX-?2C2W?!M({Z~qk?D-8{H zOvi!4gFRNqD@F!;jgIe*4)*6d)*2V=raDdjr#rsIJtg8jFS9j*>`A03xm8|)Q2K6ibv-_$W_b+D`IIPB(N zPtftYwZUGmw}%8^QuLirOj-z%3J5R^eZv=aTj-T!h_K!L?dMDVq zI?j48*k|eZ;0M8eO2#>t2Ya!O4;={hGddpmE!h6=!SSR+!EvyTOAiP8 zY8_v7KSi~V?*kp<$AW!=j^q9b_7ol0x_bro`giO2h5JdX?O$|k=DxjcySiC!YX{_yt``@AL*wg)3){aAUyu|%{*7mhJ?s7kv-c7cxT+|O`r->c(S?uWUyf7P*t`>C$&jyle(AMA5=eDuU%Kd)mQ_opW8^_%P1 z+K#^G_0S$<$EfEG({Z%=8QPO|oUUG^y->$<)GyIqspFOEYjwO^$47O1UdP=!exl9b4*{qoe!s zUHbZ6bnK;LKOIlkF<(db<*4-aXX{w3<5@ahspGXe-mK#~9XIHBw~mQ+bQdm{#acDSbYF^5mj|g~3@taX%ESIP;6_?z7%*@EZTK%(frt z=`Feo=4DTDKYuE4KdPwkUZ)l1&vCERYt+!}{F0KQnUfckxHtQM{p9XCy5H^Y$LTu5 z-8K8yll#<_J~eRvwbu&=)9%Xs>&aebPfgt~bMycAdad2-{O9`};~GzP-Puzs_siYA z_IkQs_VjMokXPRwtGQqHI`+%n-$3_^%ix~%mb+hPJI_4vTwfO|zP*F)?QL?w-kyC9 zczbqPILAHfRcaRU&Z!W1*4@?m*Xy0zJmfuTC+LaSo9uSQ_q(=V$a~N=d%xCszYE;+ zoa3JLI<*KsUVGl2c-egSe8smnq<^T?zr8(s1j*a8&jaVUXT9<6?b+`Wo_N_(7b?EJ zi51>nntK^<&wej*j=hZ;?(O{vk_s=o!98E`?ag*?&#ouCe0F=n+q=s>Z*R{$*i(L1 z$m^RLJa7NCm)S3O7v^8Dx1n>W^baGrT>8Z8J?)k~&(i_-dc19G_I~Z@3HPhwaJ(HU-tIw^KS2x-y7~( zZ>{s!$)3>@Z!g2`im$iSUA~WbC3ocYDn3+in_ZZb+p%?rPOaP6_ch(OV_N4{_-}^} zu61hHzICVi_B1Jaem|!s#9Okr*{tmC+Pkv%>7M-H_j)t;u~hSV{x<5wPFq_HX)$=` zk%R_2kL+yy?vaFCujSD_Uj5^T|2f`xaKoWHk9Z+_$$S5LNxi{!hP>cj^1}Z(r}uA_ z8`e0v>L8sLZ#b#)jGIEo-W`5$$B0o4Di2N{vOE8|BMBML{ePaBdUE2w&Ri3mIr^Ra zPEUEyc=2jIOFDX?gYK7~l<4*C5OK#8FU#FF1QrrP5qG7ecC{~%6|X_}kyi>OPP51I zp(OjeZ7Wssk45YdDRMDf&3$qz4XxoG8@eCZ`_&xo@KyF&!)s0|O_5{n%~neC8@QX5 zN=cD!?%GU9@a;Q*l@cOvxmO9-bgv$6Rk@cvf3JJj;nr2`X2&o6`WH%k)V;IBgoGx( z{Xx!%{cUkg^?v}>b2HaVXr@`$%{E>_bIlXnZ0r7o0?j&Zw(}BNYSwnMy_e8RvzD73 z++T92S<}sqUP88J4L3V^2|1e8-R$iCo&?QmZsxj+m8)IVw!2(yw5!;57p$#zW!vtO zwbRbD?Jin-?F`%QvUSjo+jbYOqjt=;yL6qj(`~zp*I7Hww!3^?v{T(~<1SxU?G)SY z@^#aW+IE+(yLPf|cll1zPO|MTUk~kwZFl*4YA4!um#>$$Z`)nI-r5Pa-R0|}9k%T* zUtjG?Znt%pub+0vw!3`&wVj2egoH-nSKRfVyx#mYF8zO4l1Dii2?HV<-7A=o!M^<= z-%=q%bgG05)s&E7ni4WxQ$j{)O2|k}2^pm+A)_@VWQ?YSjMYTQIBkTSqK%O8+6XyS z8zHA@BV>X$LMCb>oS}`7JZ*$b(nd(WHbN$ABV>v;LZ)i}AL8yhO0II>^KeyH z?^L=v-Blfd1Wkb8F@jryyIar@A|wza0>L$Ca0?LJ-QC?GxVuAe_t|gP@40jCAG6l1 zHM3^!TIb&T{dC?C($CplySuBJkdd(o85Nt5-D49nIyNC=ViU4QY(n;oT^F)J>8t$x z-*jt!p=sQ(E@Z3x3e`Baoa7`S6SMRU;O#>8ilZT9Qp^xCIc5l%5;KHMjTu7rju}Gs zi5Wts#S9_)#tb3*#Uy0^*n}Jqn~(!z6LL^&LJp2i$RV)_IW#sQhs7r3@YsYL5u1?d zu?aacHX%pFCgkYYgd7u_kYi&La$IaeX2d4s_}GM;5Sx$_V-s>x?7EQgrI!4X(bOyd zfYUgkE+l;)ZsW=2Bqs?uJxfmxXcuxu91S67#tb1dV}_8kVup~jV}_7(Vup}eF+<3? zF+<3CF+<4tF$uXKHX#?rCgh^ngj^h(kV|3{a%pTrE{jdb<*^C5A~qpc#wO&d*o0gi zn~-Z_6LM{ALavKV$n~)axgjNA$P~o5OPn<5OQzK5OQD45OROa5b{9G5b|Km5b{vW5b|)$ z5b{V&LLQAx$YZeyc|0~DPsAqV$=HNE6`PQ!V-xaBY(k!mO~`Yx33)y?A+uu>@LI6Y@rELf(vB7jj2wi~RlH)FFSM+jwVulu3_C z-YO?KNyvLydQwrlkoV(g2>Bpp2>CE(2>B>x2>Cc>2>B#t2>CQ-2>C2#2>Co_2>Bu= zAz#KOVr9iR9nWy=V8=5Y%XU1&v7;T&aBQ;U8IBb@p5fSR$1@x|+3^g= z7CWBd*lK%*V^#1B$C}_7j%|WxICd61!?BCt8ID~A&v5J}c!uL#f@e6+EqI1wcfm6p zdkCK4IFH~Nj`Iqh;W(e*8IJP{p5eHF;2Dk!3ZCKEQ}7JOUV>*hE+lw{SKqZ zzIG_;XNRKxb|@NPhoWWdP&Ck{Xjy@xkbEw3|TDaDk!`0!1SQibe?(?JiI> zTA*l*K+zroMSBVqjTI;wCr~tAs4LpISXws+Qn@9cjhlp`{)yCt{9Az1XLWN$lZ#n; z%5=M;Db9zYsdgyZ+YUwh*r8~e9g6m~L(zVADB9l+MF-fS=s=sIg9M5W7AQJIpy*J6 zqQeA=4i_joLZE26K+%x`MMnt~9W79Fj6l(`0!7CO6wMGQI$ogY1c9Ox1&U4*C^}i7 z=oEpXQ-!*sy^5t7Igm=<{7$=ZQYgB*{XVN$PQH?&nZ+zU<-T3fS`?Tu9f}^YL(!vl zD0<8eMUUGQJt0u^q(ISA0!2>?6g?wQ^sGS9a{@)r3lz;3D0)Gl=tY5|mjsGl7ASf} zpy*YBqSpk9UKc2OL!jtQfugqriry9|dPk@$y1Q8Fo`1!^(w448_k^O4(xdBli{<1i zDf+OOrI-9@SM-tdq3B~f6n$ccqEGEm^qC!sKDR^B7j`K6(hfym*`a8TP0`l^Mc)V% zeJfD(oj}p|0!2Rv6#Xbr^pil*&jLli2o(J)Q1qKX(eDC9e+U%)DNyv6K+)dx{2&y4oUTQshH~OQ2|O zfuimLMLh(H<`F2GSDmG6!o=3Q9nBr^|wRO z06P>dV~3)Fb|_lb4n@n^p=f!Vq7?*+Rum{&NuX$DfudCeidGdUT1}v6b%CNm0!4!b ziq;S)T2r8CErFu71&Y=YC|XybXgz_V^#zJH5GdMEplBn3qK$>Rq9q$jU*`=6|9g4QGL(#T&DB8{rMMLaRw7ngQ zcCbUyjy6R*2^8%tP_&Cc(NKY+T?LAU2^8%nP&8biXoNt~NP(hJ0!6zE6pa=r8Y57& zhd|Mu0!3p5ipB{PjTb1IAW$?>plC0lu4uD{QvV!CWqi68Z61n7rjKZo8p_F6QnYtN zmR|C#UC}`-*6P0?inMVAW{T_I3(r9jbD0!3E~6kQ`wbge+q zbpl1#3l!ZTP;{d}(MdIq3Cft z6g^>wq9^T8^ps7}(*i}$2oyalQ1qNY(enaDvjvJ?5GZ<4py(xmqL&4VUJ)pIRiNlK zfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_l3Hm`x;6OOXZ3#O?UeDhoVi>qw5bE z%E?z!^hraOUb3@Y(WlObqR;G5^tm01zOX~lmv$)n$__`?Tz9g4oOL(#W3Mc)Y& zeJ@b-gFw-b0!2Rw6#Xnv^ou~zuL4EC2^9SB74n^Ok(Vkxzw4OlG`T|882o!B7P_&Ui(Z&Krn+OzbDp0hUP*>EaRC+lF zQaK_$6zUs_K26u6%}eFvD=FH#l% zI#QtMD1oA*1&WRlC^}Z4=s1C*83IMe3lyCoP;{a|(MbYDCkqsvB2aXyK+$OeMW+iC zogq+kra;k5fugg7x}tqbrCoC%m95gXXj&**JAFhuyHrlTlA`lUS$fI)c17nqABrxp zL(zqHD7wfFMHkzl=n^{=U22D-%j{5exgCnGuqnDypy(=rqN@dpt`R7@R-ouQfuidL zif#}nx>2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%Vp{{6F zsdQNmq_SdCbZ#gboW}j7a`KfFJzUDtk4$J+^oaAJ=utZqJ!XfZ$L&z`gdK{Wv_sKT zb|`w<4n@z{q3BtgqUQvPo);*ZEl~7=K+%f=MK1{yy)01lia^n;0!6P06umA`^oBsu zn*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ-uMGuxrb8;Y+>FKkM4~3#-(zWR0 zQaSlbiasx8=|^s~EBeCuQ1qo8ioUW#(HuJzeQk%LZ|qR?tsRQKvqRDMb}0J6rszk3 zqMrnceikVDMWE-oOn;Of>S5nl{n57@t(ypl0 z`A}4~Ls88RMQwH{>THLiE_NvDYKNk3b|{+54n=d@6m=IU>LE}xk3iA90!8x)6wNPC zw17a-f&xW71&VqJ6fGoBw6H+YA_7Id1&S6GC|XRQXmNp}B?O9=6ewCsplE4I6s;vtw6;LeIs!%O3KXp; zP_({4(FOuV8wwO{Bv7=mK+z@wMVkr~Z6;8(xj@kt0!3R2bw&LfOZVkKDu?H@aX=_~ zJ6(&mYAh#TNzrzVS^AMt?bo6q&WEDy?NGFX9g23eL(xulDB9T$MZ4IcXs8{EcC|y% zFq@*?1d4_W6paul8YxgTN}yZa4YFs;4)RevgvTZ1OEM1GHHI|dFr09UgEd9u_ zc0~s|ABqmLL(#!@C_2OrMTgp<=rB7J9d3uBBkWK#-3~=Z+7ulnP;|6F(J=x=#|ji3 zCr~s)py+skq7wv)P829QNucOtfud6cicS?MI!&PHbb+EX1d7fSD4Hoybe2HT*#br9 z2o%i{>WcPjENz$rsm!0g?|T1G^ke!qk#if%$yZWzVPlqlWL>+Wi<}Qd7u%ue5<3)K zYKNlB>`-*M9g427L(!FXD7wlHMOWJtT_aF*tw7Or0!7yg6x|?DbfZAgO#($X3l!ZV zP;{$6(QN`nw+j^AAy9OuK+#`kownNc3b}0JR4n^PDq3C-%6#Za_q95&0^phQmezqz4MWE z=6opXY=@#Qb|~sC|cbPMT2aL1`8CeAyBlYK+#$PMQaNbts_vhu0YXx0!8Z!6m1|- zw4p%JMgm0}3lwc4P_(H)(Pjcgn+p_eAyBlXK+#qLMOzCLZ6nkb4a`bc$d1d8?$DB4q?XskfdIDw+^0!0%9iY5va?Iln&NuX%5K+zO| zqNxH!dkYlpBTzI=plDx#qWy%rq9Ix7n;b~xy7W+J`%rXGdXTh#R!+W>qJy(6{mAfk zMTa;aiVn3y(P4HdI@}ILN7$igx*dv+v_sKRb|^a94n@b<6dfy2beurZ41uEK1&U4( zC^}J~=p=!nlLd-S5hyxUpy)J#qSFP6&JZX%Q=n+3K+#zOMP~~Xog+{*OQ7gnfui#S ziq046iVn<5%jQ5TL(*;8L80jVbS=6dD<@w`(Ir`ye&l?+qD!3*MVHy3=yE$0U15i! zEA3Epl^u$%wnNc1b||{m4n^156kRV+bb~Lub zK+&B7MRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el2^2jnQ1pmUS9DQU+AjxEnUNj} zT^x!Y&)?SgXjV?XlA{@I@*k8@XnZ0R{gg<3nU#~Tr0AP0 z`(UR~^sV!u=sP?QQDJlvSH3$@y1d193iZX$s4gy7GfufEAMNI-l6@j8=fuc?V zMJ)nFtwLSVoUGJg=Uh?xx@+Utq3DNn+h6TaPQH?&E*-MPhK8c9&WECIb|{+54n=d@ zp{TnZih9_gXdXKh&1;9E`Rq_MzfI8s0!0f76!jD+>LpOLkU-JG0!51m6!jJ;T2!ED zF@d7R1&WpsC|XjWXeoiBr3H%m2o&`dDC#Fr)L)=zfI!hQ0!0Ibx}vrYrHykSmD|#z z>&_kOcluq@ZU3?z%E?z!v|@*B+^|rzlJlWxWjhqDVuzwt?NGFu9g0@BL(w2R6b-gR z(HeFrTGOUzErFu71&Y=YC|XybXgz_V^#zJH5GdMEplBn3qKyTLHW4V=RG?@xfuhX? zinb6a+ESosD}kb|1&X#2DB4z_Xgh(TAwpfz@*PU2m*pqEU7z+TEsTv_R1qfucPG ziuM#J8Y@sVPM~PKK+yz&qKN`UdkGXx5-6H1P&7rLXsSTb-U3DY2oy~dDB4$`Xg`6X z{RN5+5GXoOs4LpBL+SM#Nad3B{Y5*4qEpgGw1Ya7ldq)cunyVpBSX>Q&WEBS>`*k_ z4n;@Wq39?(6di4cqGRk(bgUhUj+Dc; zy&Z~futU*}HbplH6x}RPbc;aItpY{22^8HfP;`et(VYTCcL@~TEl_liK+(MdMfV95 z-7iq|fI!iM0!0rA6g@0Z^oT&wqXI>b2^2jp)D>OYp)?`~QfW<}BDyRT9i6U4Pjo0J zUrEt39kS_rgraAi4@J+}q3C%#6wS6n(F=AcdeII=FWI5!WjhqTVuzwvZHitKD0*F> z=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>n1&TfsDEeHW z=nH|OF9nLe5-6G@)D=C|p>$Oar1C`ii1u_SS}oo7f8C*+d?iKScgUU|8;X8#J{0|E zhoYbCQ1r7Mihi*}(XVzW`pphSzuTec4?7h7X;bu;zU@%@ zE(cP1FI|4V3q?1lN7tRp<>V_VnyZ|(O$bGEJ0FU=+o7n39g60$L(#l;D4Nd>Mf2OC zXaPGEEog_Lo;F3j1d0|CC|X#cXc2*;-U3C73KT6SP_(!}(GmhhO9~V%B~Y}qKv5ro zqP_w}{RE2o3lt3yC|X9KXrMsRvI0fR2^1|a)D?9tmzK|gR8~!Q`rXR)JN;t1(_f)n zPQH?&Rm$0RdxfG^oexE;*`a84I}{DFL(yP66s=*0qBZSMw3Z!;*0w{@IyOb?3KXp; zP_({4(FOuV8wwO{Bv7=mK+z@wMVkr~Z6;8(xj@kt0!3R26m2C?w6#FdHUdT43KVT8 zP&7oKXnTR89R!MY6zYmrDwht(fmGhjXXDDD=*o00+NoSlzLKI{%h|b;L(wqjL(y(_ zC>m~uq7il|8fk~3QFbWW-3~>g?NBtv4n=#|6zwTcG*+N!oIufdfuaclMH2;z_7W(X zBv3S2plFIf(Nuw=y#@O1EW0L($;$;qB0JIr&P8rkAsi@*kMn{?*tcoexDv*`erYI}{ybhoWQcP;{If zie}iM=y*F6onVKe6K#r45-2)Zpy(8VqEiKmP7^3PU7+X;fub`7ie?HFoh49owm{K2 z0!6a~ip~`%I!~bJe1W111d1*cD7r|X=wgAQO9YB873zu(FPA#*oh!O9pN&U^qTA9# z?aRvLoc4n^16q3Ak06kTtJq8sc`bfX=LZn8ts&2}id#ir<1 zfuh?4if$JuxE9u_EiM4;$V zfuhF*iXImzdP1P+Nr9rLgu0?D%B4+nAeA@Lb7QXzMbpx?=;?Af`AUkOFJ}|>3q`Y? z4@EE7q3A_B6uo4JqL=MZ^okvdUbREfYj!Al-3~=>*c81fQ1q5S(c1z=?+6sVD^T>F zK+*dGMIQ(heJD`$kwDSM0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2R(Hw!IuLX*}5h(gr zs4IH5TskcWQW>8f3OyH!u1VLT@5<%mD=GS^oZWgrDEis?Q1pu(ihi|2(QkGr`rQsi zf7qeuPdgO-Wrw1_?NIcOP0_ysMTL%W+fGqYpr}Ehs3cI-C{UCM6m<|NDhm{K6ewyE zD5?k)H47AV5-4gBC~6fbstOd<1d7@OiaHAvbrC4)D%2JIP%gch1F0O9KI`~nD4I8s z>ejKGd?iIaI%aS>3fUUn#2$PPsd+Y~J# zP}EzXXi=ps1ffQGbD=0RlzK2owzzC|Xva zXgPtR%J0&=)g`$(wwPX@{awb|~824n?Ew zP&CF4MSIwxXiqy7jkQD3IGdvJ0!0%9iY5va?Iln&NuX%5K+zO|qNxH!dkYlpBTzI= zplDx#qWuJl_7^BRK%nSAfue&1iVhYiIz*u8P=TVu1d0w9>WYSSEM1cWsWhaALc4{c zr4y+mI+l~Kr0D35*|XC_(J{`4qGRn)betWEX4s+VcsmrGV27d;?ND@*9g0r2L(wTV zMW+fBohDFpxE9u_EiM4;$VfuhF*iXImzdP1P+Nr9rL1d5&(D0)Vq z=vkqz=<1H86>}h!P4n4!O(<$hAJLxcSWdo@q8B@6+aDW>UUEJZy=;e~SL{&qsvU}6 zvqRDAb|`wo4n=R;q3A6;6uoUz^o~H$y8=b;2^76AQ1pR7(T4&>9|;tFEKu}`K+&fH zMV|>2eJ)V+g+S4l0!3d56wMJR`dXmq8-b#41&Y2CDEeNY=m(*$Xm-caK{=58t7ti# z7edh;=@Z#Mb}T1fNztzzv-4+!qTiekMZepj=np#-{b`4yzwA)-w;hW9u|v_nb|@+| z#eI7yD%un^2o#kBiW&uqGJ&EF0!3wkqK*PZO#(#~fud%CqD}%uEdoWY0!3AUqMATa zn?O-#fub$~MO_7ox(O7`B~UcCP*?PG$I>G?kjg>n^7Bh5DyPxCshoTzMe{XfpPUei z=6606EntVD1?^DO(+)+w>`=6j9f}sVL(w93DC%v8qD5_r78591T%c$Pfubb^ik1>6 zT3Vo}k3dmhfueo_Mg0Ye1_%@_BTzI@plDfvqU8jNmKP{mL7-?wfufZJidGgVT1B8} zRiUnEo~Bae#9Yy79dbDHHr4O+pGaf1rgHL?6s^&eEp>7zTGRPZw3Z!;*0w{@I(8^p z*A7MN*`a8CI}~kThoTMbP_&Uv(Z&Krn+OzbDp0hUK+)y`MOz3IZ7EQ+l|a$f0!7;h z6m2U|w4FfF5P_oY1&VeMDB4k=XeWW9odt?^5hxleP_(N+(J-N|Xi!sW^BhQJRJ!~O z4nMWAS^K+)a;Mf(U8O%o{ESD`=2C)=Uu6gw21YKNlJ>`-*NP0<+wMP~{W%@im)OQ7g% zfueH+ie?EEohwjuo`-*49g6OeSfJ<; zfuctRiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFKplG&GS9D!dX`z|9qD#^z z8m|vUucv#o7n;h+S5ov!Q?}OGq3BiTL(yw?D0A33lx1KQ1q!l(Psihp9>UyAyD+CK+#tMMRNp-z7{C@ zMxf|hfuipOioO>p`az)RM}eZB1d4tZ>WW@!Dvi#8R7NB?FNdO6(wAm`X(}gQNzoro z*)g+1(VxzTqQC4=^tT;~{;@;Rzji1pRN~G(6cz1I)L@6Ak{yZ~ZHh91q7DK@Wr3oO z0!2*%MHPXfW`Uwk0!1wXMXdrwRe_?KKvA1OQD=doE&@ee1&X=}6wM`2G`B!ecY&fF z0!8x(bw$55m9EQyR5nbHi+&G9GqZfmTPY`BNzsCp?D_LTQBUVXQ7=0bEo6tHh3!zZ zh#iW0+o5PtI}|NuhoZ&pP_%?i(UJm1O9>P$El|`)ps24vQ9psA{sKh<1d5gsC>khG zw5&kUasoxm3lyy&P_&{z(MkeED+?5@B2cudK+$RfMXL)G4HD{#=C71~%7IkAOqZVp zD)l@4r_vZ)DJNe^(b|=)+l8TM9p^*Qx^^g9&kjZF+o5O!I}~kbhoX(_P_(ffiZ-!B z(WW*N_EK+%>0MOz6JZ7oo=jX=@10!7;i6b%t5+Fqb&2Z5p;1&VeODB4+| zXcvK^p#nv_3KR_!DB4Y+Xt+Sp2%)ZM%}QzI97rX-Qc>etq3FsqMpnwnS5h>llI?hL zDB8pMP_(BVipJWZXq+92#@nH2f*pz`+M#GKI}}Z_L(ycLqA3DJQw56l7AV?BplF&v z(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3Eh(OVy0!4=j6df*5bc8_Bbb+EH1&WRmC^}l8 z=oq1{X!lC#kQ_+m!F2f<9g3b!50Z|pl#{Qd=!8mk;iaMIMCU`%Np>hY*$zdg*rDiD zI~1K}hoaN%P;`bJiq5n{(M+47vjmFH7AQJLplFsr(YXRe=Lr;@FHm%WK+%N)MHdMa zT`W*^i9pe%0!5bz6kRS*bcI0Cl>$Xq2^3u|P;`wz(X|3a*9mn+Gb*LWav+s8(}P;{3aite^U(LHu3 zy4R-YK7pe91&SUJD0)z!=plikhXslr5h!|8py)AyqQ?b_o)9Q{QlRK5fug4cik=ZD zdRCz5If0_*1&U@16ulr&^rAq~OF~`Ijg?ZTD{@7DBse#PqKDdV*ed1ZD=B)tlJ&VN z6usemD0->ckNL0o*jzbw?okfb}0JLrsyMqqK^fNJ`pJTRG{cH zfuhd^ioOsi`ck0iD}kap0!3d76n!I5^sPYAcLGJ<3l#kzQ1qif(N6+JKMNH7B2e_J zK+$hPUD2zR(v~@pN?W=udo2_VPaocXuauLor0DNTHu;)R^pEqQ=wCY&6`JGDJrot~ zP}E?DqLLko8tqV&*`cU|9g4~}MI8l-ngog}0!7UNMV$nSS_Fz(1&XQyMKytOQ2|OfuimLMLh(H<`F2GSD`=6{ zO;I0#qP_w}{RE2o3lt3yC|X9KXrMsRvI0fR2^1|aP_%+T(TV~^D+v^>EKszHK+&oK zMXL!Etu9bBNT6u2K+zfkMQaLmMLnBK@8&=%Z=|or_G+%*>0g|#MQb&eldq&`z2@xS z8$!|g&WEB6>`=6!9f~%xL(#@|DB8phMVs28Xfrz$ZElC6Eo_Rm6e!wCplEA>qHP3< zwiPJaPM~OrK+*OBMLP%-?I=*RlR(kV0!6zB6b%(9+Et)vm_X5P0!70Gibe<&jT9&v zB~Y}xP*=20b7_$qb4AVRDH+H6rC$jbe=%b`2s~32ozl?P;`+%(ZvEqmk1PHDo}KpK+)v_MOO$ET`5p> zl|a$e0!7yd6kRJ&be%xa^#VmV2o&8Y)D@lBT)H6#Qh6(V1>~eqG$egQyQ#UHd?iJ< zHD@o}9*S;vJ`~+yhoU>}P;{3aite^U(LHu3y4Max_t~N7emfLBU{my12X-j>&<;f(*`erTI~09lQ}n4o(Psihp9>UyAyD+CK+#tMMRNp-z7{C@ zMxf|hfuipOioO>p`az)RM}eZB1d4tZDEdX9=vRTF-vo+&7byBepy*GbuIP>C(yBR- z${Xpkj&FvdO%kcUn#;*oQdH=a?R-xtDt3xH`B2nghoX`liW==ul-Z%EgB^;>b|~s- zhoUAs6jf}BngxnF2^6&m6txNzRRxM_0!3{CMV$qTx(F0?6)5T^P&Ai7(cA(>-35wz z2o%jDP&BVV(R>0$^9vL$AW*cRKv7SjuIQiU(qTD}$}j0PL;ej#%j9os?A589d?iJ_ zJ7pK&7m5~jJ`^oxhoZ&pP_%>{ik7rP(NcCOTG|dpee6)w*A7MfY>N5|6b%q4T1KE~ zpg_^G0!7OS6fG}Mw1PmJW`plGl_(Ha6pYYG&t zB~Y}sK+!rvUD3jwN>AiKDznqIXpv6!JN@3B^098Ga`KfFZP+RM;(<`Kk@KNwV>=XW zVuzwl?NGFt9f~%$L(vv?DB98vMO)dSXlt9IZ3K$86)4(HplFCd(e?sGI|vl*C{VPM zK+(`*kx4n>pgP&CC3MN{oiw6`6K z_OV0JG&>aSYg4qJK+*mJMF$8J9Vk$AkU-JF0!4=i6dfv1beKTV;Q~cR2oy~hC^}N0 z=qQ1rqXmkN5hyxVpy)V(q8S23#|splAW(FoP**grQ)%lQNM*o=8kfdNoyy5q zQgm9UZ0e(-=yc~p(HV9qI@1nCGwo1xmK}=DwnNc5b|{)#D0)_)=sAI+=LL#p3lzN|Q1qfe(MtkFFAEgCB2e_IK+$UgMXw7Ky&=>U-QKD6 zeh#FvUb_6;5sDVb-`4nMr*iU@6usLiD?Sy9-g7<_y>Ex25A0C%p&g1ovP03wb}0J9 z4n?2Zq3AO^6n$<}^o2mtmjXp!2^7r{DEeBU=o^8eZv~3J6Day#py&sIq8|l{eiA79 zS)k|_fudgpihdI)`dy&t4}qdT1&aO>DEeEV=pUi3=`ZX*`cUnhoWXX6m_ygQHxDct3Xjz zpr|HL)Fx2WS)izkKv7qLqHY33a|sm9El|{5ps0sH(L4f0^9mHrCr~uMK+ysMMGFcP z^%N-TB~Y}GK+(cNT~V>6G&ToPxg)`8XsO?$b;;k>xJXMm`AUiwZ^@2-E)*@{d|Zo` zv_sKSb|_lf4n=+JP}J8BMg8nh)ZY$81ME<=j7`x%fudyvik1^7T3(=N1%aX!1&US@ zC|X&dXcd8?RRxMx6DV3;plFal(O`k1H3W**6ewCtplEG@qICp{))gpPPoQXhp{{7r zmeNf*kjfGX&SIgcNBZ!#K}$LLN{TjV$zGZriZ*pV6m4dQqRs74w1pjtwzNahR(2@b z+73nA*r8}!I}~kaQ#3@NXnTR89R!MY6e!wBplD}-qFn@vh6)tzDo`{`plCONqTvEX zBLs>@3KWeJDB4}1XtY4l7=fZa1d8?)C>kqJG)|~1+Nh=UTMndhV!9S>9E#GXi5kbZ zl#{QdXi`hoTU(GJ&GY1&Xc^ zD7sRh=qiDts|AX#5h%J=py)b*qU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qsg}S2C zTS`adKq^nA&pMtFie654`ggRHldq)co|f#=*Fw>~&WED=>`-*S9f}^XL(zkFD0;{a zMGxDd=n*>pEYZcEpq_e0S?>Dy-;TFc2-Qq-X}8}N20 zDmx#FI@+PA$qq#oI}|nBp{SD`idyVY)M|&KsvU}IHbrd$MV$qTx(F0?6)5T^P&Ai7 z(cA(>-35wz2o%jDP&BVV(R>0$^9vL$AW*cRKv7SDqFw?;3kei0EKszFKv8djqD6(e zqQ=(JwmFc>y$Md%TEElJA8F?|Y^~+wD=Av4HQVRiP_(r3p{S1?iu&52sGl8*`rDys zfE|jKu|v^7I}|Nzhoa?dik25BT0x*_MS-G~1d3J`C|X6JXjOrt)dY%G7bqGeP&8Pe zXbpj)H3f>+5-3_*plBU|qICs|))OdNU!Z6MfuaosiZ&AJik4_C&B}pPUQC~LTrw2> zm`H8hT28)_qRm^gd*2U5TR0zzwzNahR(2@b+73nA*r8}!I}~kahoT{NDB9i*MLXCO z?I=*RlR(kV0!6zB6b%(9+Et)vm_X5P0!70Gibe<&jT9&vB~Y}xK+$M{qA>zRdk7Tm zDNr<4plF;x(RhKP2?9kEg}S0mTT372Kq^b5@4MbC6pc%duJ>v!Ctpd?)Yh!@Q7GEm z`B1cv9g3#ep=e(_6zyk+qW$eqbbuX-4zxqjL3SuQ*rw zp{{6hYiaQuNM%;K7EK97U!_OaXS9}+ucYYg)@*}MLeV+ShoV__C_2{;Md#U}=zKdA zU0{cz3++&JksXRIwnNb+Hbs{T6kR4zbh$v$6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~ zK+z2XMK=l*-6T+Svp~@;0!6n96x}9Jbh|*&9Rfvn3KZQX)D_KaEsf8CRQ67vbv!E+ zJ(;dWcej?4ucYYy*6hU3LeT@xhoT4VQ1p-;iXOH@(Ia*!deja@kJ+Kgl)ioT{nm2wl@xv4n!WNx zDEh?tQ1q!CiaxVL(dTw3`oa!HU)rJQD?1d;u|v_~|!g}R~-TT6fBKq`+VI3IphE`g%C1&X>06!j1&nn$2$UV)~o>gRkY>Tidl0d^=_#tuaT?NGF=9g3E-L(%efC|bb|MJw7A ztt3#ivOv))0!6C|6s;yuw7NjiAc3O60!3>G6s;*xw3a~8+5$!E2o$X=P_&*v(fR^K z8weC_C{VPKK+(nmMVkl|Z7S3iEnO`gnFFajmhRE|grZ;DZ`i8kmmiqV4Taw1XXrcCk$NG(n(fqCnAJ0!5PqiY5zn zMO#!$&*VTVqtoZEw+uzS(zR$xwVZq)T%V27du?ND@( z9f}UNL(w62C_2;*MTglG9WGFGgh0`BfubV?ijEQ}I$EIU7=fZ=1&WRnD4HQqbi6>( z2?9kY3KX3rP;|0D(J2B&rwSCECQx*`K+zcjMP~{W%@pd2_O6yX|ClS9mA;O)Pbg|h zxBX{T%gI+#bZ#{p_;V;a&-qYvz8#7#utU*>b||{Y4n-H+q39Aj6kTeEqRZ@1bh%B@ z6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z2XMK=l*-6T+Svp~@;0!6n96x}9Jbh|*& z9Rfvn3KZQXP;|FI(LDl1_X>4I=Tu8Wav+su)3s<;DB34|M7ytAPQH?&hpO4WzlNfR zoexEi*rDiAI}|-;hoZ;rQ1pZyik`GX(NlIPdfE;}&)5__D^T>DK+*F8MY9EpUJxjH zQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDS zP^c?gzO_TqcXlZH-lpgWfubJ;ihdF(`dOgp7lEQ*1&V$XDEeKX=nsLSKLv{Z z5-9pxpy(fgqJIU73bnXxr>H1U)F4n)5-4gED9QwiItUb%g}S0os-=%}AeF1L9L}eq zXl%L`b*z<>ucW9`EzAB2MJ>*UqEM2mvOQ2{Wfue;4iWU(l>Mc;Ts6f$T z0!51p6fGf8w4^}MQUXOw3w1@6T4~7~NadBL98Pnsey4wb`ta7LR!+W>q5-vRqklrt zGR}vhfp#cb)(%C>*`a88I~1*8hoTkjP_&XAidMEm(JD4Ys|pmYCQ!7xK+zz9qQL@1 zYX}srDNwYQK+)O)Me7I@tt(Kpo&1iW<^Kv@L7p`jwyu?K%Yjs`OV_V+P{{)))0yga6S|rXosSM>`-*D9f}UIL(!pjC_2mzMTgs==mw^sTq2U6KNeeQa{Q1olMFwLr!ldq)cf?76z z{&EoQ*P;uZ4@DQ*q3B{e6kTG6qD$>ibeSEBF1JI`6?Q1P(hfye*%VzZP;`wz(X|3a z*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86x}XRbcaCEodQL72^8HeP;`$#(Y*pi z_X!l;FHrP=P*-$bt+Zwiq|!ZIe$Ed?_ok0%57x@bS5ow7EgN1AMUOcjiXOK^(Gzwk zdeRO>PuZd9X*(1>V~3(=?NIcb9g3c}DVi-%^nyUqivmS22^767Q1psG(W?SQuL%^r zE>QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?(2^4)SQ1ppVSM+eLbaW1+ zvRJwnJras8PLHlXt(B9nr0C09c4bp2`pWrGG{+7_U)!PR8#@$zYloum>`?T*9g2Ri zL(z|RDEi5!=x2eVUj&MN6)5^mpy+pjqCW(R{uC(sOQ7g)fuer|ivATSDzwFIJ4Ho- zq6UGYl0Z?TKv5=8)Ip%AEKt-@pr}cps3O!AeO@a)mjkIx$YS~9gZgwb|%ML|z+o7nt9g2F`6wM=0G_OF>d;&%D z3luFNP_&>xQBQ%QUIIl62^1|XP_&3ZQE!2wMFol$6DV3-plAt!q9p~2mJ%phTA-+p zKv7?TqJBbMQA=B?Yo}b%m+7;Pt!?!?{h8@n)W5Bqd?iK8wq?t;hN9)14@Jw{p=bp= z6s>57qLu7Ww6YzFRktKw1z;@ngT^@2^6g@P_&Lf(YgXf z>j@OCFHp3BK+%Q*MH>keZ7fi zb|~7-4n@Olibe<&jT9&vB~Y}xK+$M{qA>zRdk7TmDNr<4plF;x(RhKP2?9kE1&a0( zD4HZtG+Cf%ia^m+fug+yiuMsGnkG=RuTWRCU0dmb97tt$x)u!yMPH;(LGIU9PQH?& zgW9qOJBOl!oexEa*rDi9I}{yehoZynP;`VHil*D4=tw&h9c722qiu?g5hyxVpy)V( zq8S23#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_6rCYZbf!SjOo5`a1d7fUC^|== zXqG_HxdKJ!33WvWw3R;1fmD`HU(-J@6wOK3qVwCz$yZWzaa&gI7K$!$J``PQhoZ~u zP;|K+imtFj(Uo>6y2=hkSKFcJ8aotSYg2TcK+*LAMK=f(-6&9WlR(kU0!6n76x}LN zbellY?E*!22o&8ZP;{3-(cJmir!7vqDR`w$yZYJL|eAW+@a`6=R?s`b|`w<4n@z{q3BsV6g_8$qUY^U zG}{hEFW8~zMVq3R1d3i3D0)Sp=v9HD*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>W ziryC}`aq!QLxG}?1d2WuDEdU8=u?5B&jgA-7wU>0Yb#C4fmA+BclwWqqCfJtHGa`n zPQH?&uiLUydxWBIoDW6c+M(z>I~09yhoT?sQ1qi6ihi;~(a&}$`o#`KzuFZ2CQ$Ud zK+zupMSltu{UuQJw?NT90!9A{6cswhZ97FpfuaV1qLM&Sqd-w6P}D)7s4P&_QJ|kJ8w2V+!RO?*& zCkIkFCw+>jt#kcOe|nCmabV|i@|6^=&^cRhfl#!f^Py-ZI~1*KhoV*NP_(KYidM5j z(du?68f1r}!FDKG!=`9Wfugkpiq;k=T1TL0U4f$Y1d7%dDB3`vXhVUbjRcA|7AV?8 zplDNpqRj+~HWw(`LZE0%fugMhinbOg+D4#gTY;kOgu0^TI+xbYfmD`CaF!26^Q3Fh zkj~}gD=FHkb2c*niNx(+N88!?P_&C3iiX;uXjeNF4YNbhZgwadZik`~b|@NYhoVt7 zMY{_WjTR^xBT%%5K+&E8MPmhu#t9US7buz_P&84XXfJ`HNdiTa1&XE!6ipQ<+FPJ# zAAzE20!8}@6zwNaw7)>n0YY8T4xLNK=0Gab(mmRap=f6M@OEJ5a`KfF9ojj&dZAEs znDe3Na61$oVTYpWb|^a14n;@Vq3CEk6dhxSqGRn)bev7m41uEK1&U4(C^}J~=p=!n zlLd-S5hyxUpy)J#qSFP6&JZX%Q=n+3K+#zOMP~~Xog+{*OQ7gnfui#Siq01(xJ}}9Lf7i))k2|r^{uu-VZLgwu7yI+>h5zD3X4>)?OrG>Uj1>N zLSgCZO7j;A{i_ErSST!8eY97huwu1&kwRhB>K2O@3WKX>E?y|CU43WCLSg;t!hH&b zjjLn&6$+bIuOCn-Y+e0%V4*Oiy2|o}!cNsgS1c5EtvexYzc^~Mbgg+r>pZd@oFQC)4bLgDD@;ae06GpbK+ zRVbWPt!`T=oL1dtNTD#Zdd?1o!mR2CI~58SR2LgsC|pt^;&qI&c2LgAX~?;{I^ z8>)jw7Yesjr|(fH+);gcY@u*ZwQWM7@IZCDy$Xd#s^?BF6rQMlG__E8rn*G_BQa)I zC+t@!yj;EYfI{K*>YoP{3U61}IJ8iBzk1Z+g~G?xXQvkmpI5saT`0_{Zhvf{@Ll!% z8HK`6)lW_+6n?8Nb#kHbS8cCT^S}RM?e^32cR;cB_nG;7pjcb$?EGC&tQ|8ee;*WU z&!3mS6NbF4ocy1nys~ zrJv}!Y_XPpBC&gO& z$sSu5Yw1Tb3@O&qYwPb+tfd!6-?dmvuWmh}SW7QYJi1s*uP-~cSW7PuIyTnCy~@!M#oE2^=kK9nExpdjjAAXlP{c{aT6(7cX~kN4 zs`kucEj`zER++vYw5e59x2w+x2-%;tflWec&1oOUpSs!tfjB~yeO#=iPhWgqtfl+UImKGKf%vXiOOF75D%R46@ZXBHbPfKiSZHfV zpWDBr{$IJyeM|W}b71~oqZ~^9pW>{A7b_OJ9G3r*;&QDgrraf$S12wYqj!4C3Ng+} zhgWPpy#1G*m;d*#xKh03()@QUt{mg;bY_(p52dkcj4g}#SS`lC`G2vCtH-#nl8-?# zMx{T&;QHv=Gau;>`E`CV=vLgk*uT(q)`)G{D48epPFJDEps(j%rK(r%V6jTKoT#6$)+fZxa8I&V7r6diX;u z)}yW1xx?V@XRg^J{S&(^`yYS2`SRbS>oJEF^S`G7UD8{-9eY@@(9r$lHSw^*5&4mZ;-9T8 zg<}3c`L9h@`u6QNX;{BelPC6@JZX5pNkbBj`k<4Q9fc`@V4qc}I zG6RMV=$~SrJoXtsVf@HGBZuuarq6)>eFyeQZ|_5BspE$a=s&RU z@I+zgh>@d)O&vRB=#+gYj-1?gbP|@oyGD!|KP4aeg=wp`))|`rF^8`;VcfV0W`k$;zhhkPN?cO)*QtHt&>)b2rvS5~V=$CcQd)A?U z{s5)eEo)Byr<(Oj|0nP5vv2<9WwLJh?7UjmYoV;m{Qu9+t==c=xp3BHzW?|K`U5ZY z-~PZo|ML&rv;7a8{=K^7zq(iYGj~qEMgFhc{_pCy_}}|?{y+UQ6j%Entlf2d)ph*; z{cUH51BXVj0~=J3Q356sCStcDjY>(_-QC@a-Q9`Z-QBIIsMy#0z0d2;_*$z8*&d%8w)U`=B0b2}SfB2B@8`R`uL*MQj3?ErM+o#vOXL}Ev_iUfO z@tVE*Y6G0yy;t$F!2{!U8qzE8w#nqlQyOZ94%lw^z)iR6QM~OzPU$`G{jDzbYFl08h8J(4A-yvv4Dr?m#9Ldh=`Ey>Kzg;&GbT>lw|GnOy1l&P0TEW8 zcLCA|blzK@_fC3wAA_1c80kY0ub3`!@nKAFrFdq(i?F&=(+98dh3Nwu=k=cV#?s~S zPJ6`b_iVZx1LvL5Fwnb77d+0$0_MAc|NrY|ZP1vJGse}V&jpjljTt^>(&*hrOd396 z@}zOaFECvt>D{Lr&-t#CxM;naE^WI0i&vlb%LA=@)32`IykAK}GF-Fq;O&PG7_>#> zdFiT+Ut}U2&kgz?XVz>nJm37q4Q5TgfSnru_kW;kXu4SIg)98hmD>33c$+7x@SA@l z4sJYq_xyXO@m0IWn@E)7a;-P-66W8ujjuGI>7ouIqi4Kq9u@Drq3^sm)zGAo9(Wp> zc&1-PylZ3{(xq&C$Mck=8;Zuz(1flbsViD{FKlwyFvK<1#LtzOel^8;p2^o%zL!sjT&pSt$tIGIE|mhicemH=bfFd zfq08emw=n}5sH`jP12CAg5o_ic}q7>>9rc)c;k!GbsJ};PcHG?ykAJNT%4b7pYsjn z)Z(MkP#oejYmGM8MCTuQ6ai!0@zUO^LPrvmVUnO5B zje^ogqj+XM0!>$WL(_HM&~&A{MjFzEZ9F-B%5OaSh&Lp^#ao^43T?Xn(mRijO+&hq zQoLgNJs;1^`w%u1*KWR;^WEk*#2M*YZTbMG=hokJ>rMmv_3M-$Uvz8elpkSq@7tqS zr_NKyOc*m_+L$h#x=tK5WyV^g(noB}K3ymF?3u#!@iQilOvkYkCXbljH9b68D_t$4 zb4af_cFJD8yH1%)0GJ4vSRmM)~)OB2^uETnC z>YDCiuQe)NfUaXFj+r)X#JDkCCybdiZu%BsSeO zY$$*?N=diyaj}}Np+fn*&z+5^hY$aspXS{+ZMtiUO};ZVY{-`LK7BX1C)#wcvgyub z(|yTwuN0r+cR{{*^BlV$+H@CjzI%x7hBn+3{=UwCT?r_e#Cpqs<<9xq+ntl&7-Q{xy zH{Iczcf}R=8f(@cIIw@G&iVJtfTqO{?^^ zhyT)3`f|qsZPJ%v(ic4DJ>@T33~bZx@cJW4N7kKGTQi_v3M2AY0BUMiOV5`3b{*Pn z=ztA3t!dW2GPFgh+Pp*kg0&rM7cMPQyJ+oVwTss-QM**#vbEjv7dZac)BLHv=BNMW ze{m^41fK7y6klMGO8F7+d{3qH=(qiRJAWxAeOzgG1?|bU`%Td)1H8tt0_l?KR;+VeP-MI6wye@xB zAs^E(BVW>d>=?&I^D+H$m&wQUN}Z$U>pQ<*e!KaYz8BDVTrZCK{p7xN9Mjh|8u#vT z+%t{`$MJ|bo)X8Ial9peVJy9!2jci@y6W=&Fpj^bUqIfq=_{@IxN!Ql%E{>O^t19ms;`l}S0Ob8k99K!EL{Ql^>2#fS1T9$ z*En|TTI@CAI6Yla`SlNtq!zfMVYg$8QD}`}a6@A5!eK;<(oa#XdZa_it3}r{h>RwAgLq zxWTYuZym>zHZS)1aeQsdVt*XR#kMK-N^#tEyJAm_1(&;y62fqauI2{)uCsQ;R(?jt87x>|^6N>&#-m z7{})46uV;_H$AV|JI3*h3yOVd9N$Ubt;_H4%Q$wrwAfwaICf^Sr^WI5D~f$j9Dly5 z*#E_`@3qAq9LIyMFZS_qeC)Vm}ba-_rLb^Yv4Dr#PVwir*ExXB;Q|Q0#r< zc06)q@|J%oj%)u~95;^R5x*Dv)HptqzAKtv|IIkI`@7gn#&Mf}i#;li z7o>Xy`Sq`f<0t7mr+NPv$Ij_1`g!+`6@zg<&VVi&-C5ZyesL)oAPnp z^ljFB92&=?()U~QK0S`lrEk3E{dOEXr0>Ayy>uM6OW%skdrTZJO5c;s`?@%OmcBWg z_fK(LIenKl@73ctrBksFjN_f@`?mSzkH&F{^o`HFyTq}3K9*~0)``7I9Ji0-*f>s$ z;~{Z8F^=cO@v1o99>+)G_(B}t&Bye9eu!gj`qpaR3&wHzd`y?Ca~zxH`zy`U_a5^x zy{&N}9vo-0ra7{z<;K_4?Qkehk^-XVY zgB0@H%O3-8Z>#jYbJDXlT|3vNKiiR?E1o=??n?ZR*E_aLaryrD>y1od{`Y&x;Mzu? z`TgeZ{qCEd_qNlsHP@uKmmPcZvKcAN|MpIq@9pJBMBd)<>3Qemw{cH;dmZx&z@9mwPp3mpx>n}gO(6zRvd#mF4{Qvy2{NH79^m_mHtF756 zHBVmerWEq?o;K)T+jyPZF6wnD%zyc=p6}P&KE2GZ_x|*JGCIZi)6?7QZ=|F5m5*%a z7vG#-uX~Ce)AQb5{p{~=gj|lcc;tuoL5Rmuh;a@u}Amr z-6pS=z7x==Z}%SgD{1K~0o@zs`+uK4srBvIw@2Sj`Dxec!Gkv$Qv8X8;tkiPM}XdL zF7<;NSGiZ?i#yjWlzug{Z||_t0^=Y3W!(|y*Z%oh?Q+BBbYFPboL&nJoAdD2!{+o| zaM+wR+ikw^H5E@ zh1Pv7-3AxeNqy~{1f4vn|{2$5m&g*KMZJ8hA)i$48O^3Sj*Oh#z3{SDNP`Z$H zLl+sEU$4GgN^hfdV1BJ(i|*Q(D*5L%>(bx&m3}+cHLon5KC1Qg<@`mUy86n?=~YV2 z(yNzNU0^_d{+#r#OWhaDzg^2G=ksfu%}npCS$+MA<@^WsD*0~(TPc3hW9c*-YU(@3 zTq?~THT7L$E}3S}^f%GRTq4b0HTA2+Ts+O*HTA2;TrAB#=`XX3xoDcJ*VK25xk#FQ zYwA~vxp12OYU;bkTqw#@cg#Cot{$-$%sXAMp0O9mJ6*C~u{-3QE?V!{?ek8T ztxxQBd8Z4vdhE7&r%Ts2cALD@#p@Tlb>8Xn^^e^u?H=j!tr5Fr-s$qK8M~Tyx_oQJ zZjpDod~3&Uo_D%@>%^|)oi5+Hv76(cI- zF5lqTwRxw@Hzamq(7e8W`O?$r`fqVa_On9c&nmQNNHXfzuUwU0Aq&~Koc}OqqmWJF z)DSW>W(e6dW(XM;GlXmwGlXm&GlXmrGlXmzGlXmvGlXm%laOs<6S8e=Lbi)d$o8=b z*&#L|JH{qtr`Uw-9Gj3`ViPhvHX*ylCS*ixLPo|WWK?WIM#m;(Ol(5N#wKK3Y(mDz zCS!w?%`U#aRCkvTU&VSIiQOKTgY6zJc zGlWcw8A7JV3?VaOhLF8thLF8uhLC+?hLC+@hLHVY60(16LJo*c$bqp5IVd(E2gfGl zkl2JA8k>;AViR(BY(kERO~{e42{|e@AxFn1sY(lP$O~`ez3AsKtAveS(Yko#kXkOyLhkOyOi zkcVQ1kcVT2kVj&MkXbQ9$fGes$YU`Hc|0~DPsAqV$=HNE6`PQ!V-xaBY(k!mO~`Yx z33)y?Auq%xk``d=fK+d>S)^d=@i= zd>%7|d=WE*d>J!@d=)cxaJZ(wwSdlQiArTOkjskTt`PQKr=LTx4U z%8I(wmh+FMH7Z)!`JrePI~1*IhoY`_DC%a1qSfqB)ZGq64R$E%VTYogHbuPzih2ta z^${pqU7)D1Kv6$|qW%I!YX}srDNwYQK+)O)Me7I@tt(J8K%i(nfuex|MS}#21`8Ao z5hz+;plAbuq78*Y(Mq+Y^d}x_s{7@eqRye{{!D74+Di776>VBu&Oh4NsA!n;L(yh- zDB9c(MO)aRXiGa3ZDog|t?f{>jU9@%wL{T%HbvVD6zw2Tw4*@LP69Lz1toXj*MK|7dKZqUp{LMKkPBw3i)<_O?UOK6WVD*A7Md z*`a8EI}{yYhoS>*iVhMeI#{6S5P_mY1&R(6C^}rA=m>$LBL#|%5-2)apy(KZqGJV$ zjuR+4UZCg%fua)yicS(JI$5CT6oH~s1&U4+C^}sz6zy4CIw1k6woZ?<>!*gI;~F1l z)mE~vtmvHDa{kfkMn&g3KNOv3hobZCP;`MEiY~N6(M5JBy4Vgym)N1`Qacn~W>Yj% zpy+aeqALW7t`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t* zpy+miqB{hN?i47xOQ7g(p-^;IZRwQ+q}nAv{5m@nZJHI`Q(MWtvZ4oS%lSw18x=k1 z{803e9f}^dL(wC4D4J!5qDSpe^q3ur9=Ai$6Lu(i(x&Jsfug4cik=ZDdRCz5If0_* z1&Uq}D0)$#=p})omj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J%OV4 zg+kGNwWUSUcgm}?^8@$$L(xn5-t`BymFz1k`lPm;|7wRuMV~r96n$ogqR;J6^o1RY zzO+NpS9U1++73nE*rDiKI~09qQ}n$+(GLPeKMEAh7AX2jpy+3TqF)4x<_Hx1Dp2&B zK+*34MRNs;{tzhoQ=sTCfug?!ivAHO`d6UnKY^l}x_OWCTQz<^s#c(=PAC+8R9o65 z0jb`T|18SKq3F?kTU4s6WM5fPrLLU+YLG@n&7B{LTG*keYKNkhb|`9PhoaVYC~9Me zqPBJ@YG;R{_BKTw1d0|AC|XdUsG~s9LIOn#3luFPP_(E((P9EciwhJjAyBlWK+#eH zMN115brL9AMxba}fuiLEik25BT0wAIw4y-KNuR#!aIZ~UjQ zJJ(gRudHa*x^n)jWf~QAb$%%7W{0BH>`>I*4n+-iDC%K{qMmjr>Sc$b-gYSJV^g%c zKv7?TqJ9EJ{RN8F5GYzxplB_DqO}Ez))6RLSDvMFRzj1_=}m7AP7bP_({4 z(FOuV8wwO{Bv7=mK+z^bp=jm0(l-f6wVM9yPW>vOsFWY+53Q?YUs=)Sb>;k56E!N@ z!ug?SOFI;8Wrw1z?NGFh9g4QKL(z72DB9i*MLXD`Xh)l(odk+@7AV?9plG;2(XIkT zBLs>@3KWeJC>kwLG)ACktU%E?fuivOMY{MMnq}9Vt+Blt9tZ0!7CN6dfy2beurZ z@d8CB2o#+tP;`<&(a8curwA0CDo}KqK+)*}MP~>UoheXsmQW~~URT;H0V)19qZy&- zntWSyc3ma=%8JgfE1%st6kXu_P;{XkiY~H4(ZzNsy2K7em)fD|GCLH_v_sM5b||{S zrszt6qN@aot`;b|Mxf|gfuidKimn$ZxM6Ae&UvAzf4(iczpj#fWknCymGfV% z*LYj>i1S0yEISlEYKNl7>`?T$9g3c?L(!9VD0<2cMNiwI=oy=$X9bF$6DWFKpy&mG zq89~x6DWFLpy&gE zq7Ma%J`xH=57w3HR!NHX&tG+XC={)cAL)NwSINGzqR;Ef%XJM!UpPM$eQAfHuk29t zwH=DSu|v_fb}0JJ4n^PFq38!Y6#ZyZG+UtPCxN1$1&V$VD4HWs^s7M8ZvsWX3lz;2 zDEdR7=ud&7zXXc@7AX2hpy*$LqW=Vn(w{&+KV6OKJL>6XApfz`T7jZEfufQ?QN2J> zStt~JT36a20jchqZ;L()MYHp0R;pxQSy8oA&VRLM<84t(=ZB(Jb|`9XhoUxiC~9km zqIPyDYHx?44t6M7zz#(V+7xvZC|XFMXkme(MFff#6)0LvplES{q9p{1mJ}#jN}yj)IBD^N5*plCgTqJaWMg9M5O3lt3zC|X~jXaj+w z4F!re5-8eOplB0;qM-ssn+g;S6ADFLOQqKmkm{&>SEySk`Xb*JZC0veUs=&srE>nO zg&P%Z?fg)*jU9@%wL{T%b|~834n;fIp=d`t6zyb(qMhwfw2MvAaDk#-1&T%p6pa)p z8YNIPTA*l*K+#x%qHzL6;{}R#6DZnUplA<)q6q>;69tMU2^38hD4HTrw5LGPRDq&t z0!7n>LeUnb(qg@mqL0&`S*+hO6g`r^kUgVR$-c6peM{y1S5r4C+Ryo+Xn#8t9bku| z1MN_BkR6H+wnNb&b|^a34n>FAq3Cd%q9X)~jua?5N}%XyfudssijEa1I!>VIc!8o5 z1d2`+C^|`?=wyMSQv`}m6(~AQpy+ggqB8`F&J-v*OQ7g%fueH+ip~`ZMSGV@yCxvj z9{ILtpHS40Kck&js$^eT(M6?l{;SO!6=y;7J;H$1&VGHD7sys=njFR zI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaY6LeT}K(v=BFb>Xb&!ceqy9uJi&*;iKd zXsMk4YWzk;k2yaSJ#L4hC+tx4q#cT$vP03+b|`wr4n@z}q3Ag~6g_WK^nyUqivmS2 z2^767Q1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?( z2^4)SQ1ppF(WgS8=#f(Cy9A^?n^HGjGK%TTm`zIWZCzLI@qMXl@0`Jd)!RMf`#p{T7LirU$ssJ$JEI@qCT0Xq~e zXosSXb|_lN4n+&w6fGi9w5UMQVgf~r3luFOP_(2#(NY3MOA8cr5-3_mplDfvqU8jN zmKP{mL7-?wfufZJiaHAvbrC39S)gbYfudCfinNDqP})0>Su?d{&px@!wyAj+7zuN zP_(u{(K-S}>k1SN5GYztplF~#(IA1M!2(4?1d7%dDB3`vXhVUbjRcA|7AV?8plGN- z(WU}L!vu;p6DZnTplA!BP}IG?^k4!~Jv`0&hEVigzAf6azLI@qMcdYw^FIyLcw4lc z^Fz`0b|~7x4n;fKp=c*N6zyz>qFwAzG~5nFyV{{>giX;%fud0YMWY3Z#t0OR6(|}f zP&8hkXg7hP-35yF5Ga};P&84XXp%tDWPze70!4cY6ipQMPk-R&+ppIsemAjfxI*ekeM~4n+ssq394h6dh`Z zqQmS^bhsUgj<7?~k#;CL%BJXOfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMSQv`}m z6(~AQpy+ggqB8`F&J-v*OQ7g%fueH+ip~`%I!~bJe1W11ghJ7N^`(sxkm}$0VcGtn z=%f6{L@unaWM5g)rS;|fPm?t&y3F~ZXr>*CF1JI`6?Q1P(hfye*`eraI}}}GhoWok zP;{M5(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS6x}IMbeBNU-2z4T2o&8b zP;{R_(ftBN4+s=JC{Xl}K+(ejMUM!DqKoTGrz9ZNNAhjaC821~{26UleI@(Kik_%1 z=YQI+QPGpm4@FPeq3CHl6g^{yqG#<;^qd`vp0`8M3w9`a(GEo~*%ZAjQ1psG(W?SQ zuL%^rE>QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?(2^4)SQ1ppF(We4M zp9vIwE>QG^P$+t=zVt={Qf>SPuOAOZr{+icU)EQ$udL|X`f~oK5gQeK=loFgy&Z~v zutU+0b|{){hoYbCQ1r7Mihi*}(HuJz{c2P6n?TX;0!4ELivAEN`ct6jFM*=J1&aO= zDEe2R=s$s?nsPjBr>It-s7|1$Bv4c@P*fHuY9>%r5h!XdP}D-8s47s@QYaLCU0+&a zXi~I){z;;5LeV$*Gg_;1CHu;X+Lg=spVn+t)ZY1_sDmAf7O+Fnf_5nCXosSO>`=6@ z9f}sQL(!skC|b;>XmNp}B?O9=6ewCsplE4sfub$~MJo#wts+pgsz6a!fue2#MXL!Ebr%XnZOWyQ2}pHrex%>FTs+c$E&pMo zhH@qQ%8GiI%lV&XZB*39`JrfaI~4V`Ls36F6!o`5(HeFrTGI|iYuTY_Z95dLV^g%Q zK+yn!qV)ud1_~4n5-1uhP&7oKXnldA4Frld6e!wAplD-(qD=&fh6)sIDo`{`plCCJ zqRj=0wh$=VQlMxnfugO2LQ&6h>FNZex>UaT=@p93&tsc%CHu;Xb|{zgKkeJ7Xh-LV zqMhtew6h(GcCkaza61(3YKNi`b|@NYhoVt-C>m{3G)ACktU%E?fuivOMY{kPF1d8?&DB4?~Xdi*1eFcj46ADG! zl}kS)Al38pU7_tM%8&H-FITd!tmxo!IsenpjfxI&ekeNB4n>FAq3Ccs6dhrQq9g54 zbd(*6j`?Tw9g1GDL(!`?MXw1Iy)IDnhCtDq0!42L z6um7_^o~H$y8=b;2^76AQ1pR7(T4&>9|;tFEKu}`K+&fHMV|>2eJ)V+g+S4l0!3d5 z6n!leik>W&9!@~2=^s$2sedXIJ(Ed&Q?6uRS`=709g3E) zL(!5pMN0`3EiF*gNuX#Mfudyvik1^7T3(=N1%aX!1&US@DC#Uw)J33ZWr3nq1d3J_ zDC#Ou)J>phHG!h;0!0l1MLh(HdJ2W2_RUJ0Bp}t9`QCMhX2m1@{BOI}_i9$jzOtge z&B_x;gra`V4@Ld$P_%{}iq^D4(OPyWTH6jq>)4@aT{{#FutU*$HbnykiUtW34HhUG zB2cuxK+y&QMH>nfZ6r{%u|Ux#0!2dwiZ&G}8YWP*nLyFz0!3R06m2O`w3R^7)&fP_ z2o!BAP_&&;DC*O!bXo#Z-93L2TRjwAk-r_XeX~mTl@;yWtbE(3P_&ElL(y{7yqQjb%{}>aB4tIViI>HV`N7|w2C_5A#ZHJ;`>`-*99g2># zL(%beC_2HW=tO~{lLU%R7AQJJpy*VAqSFM5P8TRTL!jtPfugenip~}&I!B=BT!EtV z1d7fVD7rwP=t6;_iv)@;7AU$zpy*P8qRWIr(IL%BON~v6X64(WLqk!i@c~=2O7@i% zUDd3-&iGJtwev&KHFhYv)(%D2*`erqI~3huhoT$pP;`?Wif*<;(JeMbw+a;9CQx*{ zK+zonMRy7m-6c?Tw?NT70!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyyvjmDB6)1X4 zpy+Xdq9+83o)ij2S2Qb)PC%-E<(r=?L(#ZAo@!RfzOtg{nw5{-Jrq6f{803Q9g1GG zL(xliD0aBhE36%0!42L6um7_^o~H$y8=b;2^76AQ1pR7 z(T4&>9|;tFEKu}`K+&fHMV|>2eJ)V+g+S4l0!3d56n!mF^o>B#w*p1q35B9(nw73i zK&p4-&uGtvqP6nF{_mSrvahV@r)K46CxoJ(oga#Ru|v@uI~4tDhoax?Q1rVUisss( z=np#-{b`4yzif*B7AX2hpy*$LqW=VnYAW%touXQSqB?=1l0Z?tKv7wssF^@fMWCp; zKv4^UqN+eqOM#+R0!6I_irNSiwG}98Cs5R0C=~tJtTa0TsXmu)erAWF)AGIR4wXvw zl@%>iDYu^-iWYW$C|bl0MT^>@XfZn!EpCURCG1eNq#cTuvP03*b|~s(Q?!gg(Xs+X z%Lx=MFHp3CK+%cLV127Oa%|Bp}r;`H_CdO7TelhkV1ddZm(mWkqXL%G>T4iq>>~C|b)7 zMQhukXdOEgt!sy(0d^=_&kjWc?NBtx4n>1)iiQXjtuIitfk4rQ0!14M6m2X}w245` zP=TUN1&W3V6m2F@w7Edh76L_E3KVT6P_(r`(KZ4_+X@tICs4G#K+z5YMLP0hohp^=D=XTyQoe9nC>r7XP&CpGMWgIcG};bDW9(2g)(%DE z>`*k`4n@1!p=fuTqCEtPCI}Qw6eyY`P&8SfXo^75o&rTv1&XE#6ipW>njuiMmq5|p z0!8}>6zwZew4XrH{sKh@2oxPCP;`($(ZK>mhX{qDT`Hwn2}m{n8?W`lL($Ut)7zny zO7@i%9a$-Vn*IUV#_yvY<@``|v>l3$u|v_Zb|^Z|4n@b?q38rV6rE^?qLb`Ubh1s+ zDFQ{O3KX3tP;|OL(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMLqzCh6h0!0@J6kQ}xbg@9u zB?3j43KU%?P&8AZ=yHLgD}+MP;gwSJy^^9!)2u%t6wS<^(XOmivahV@+Df_0KB4G3 z=ZB)}?ND@s9g1$WL(xrkD7x7WMYq_Y=vF%v-DZcP+ii;O5GcA+py)1vqPqo(?hz=u zSD@%Vfuj2biXIRsdQhO~A%UWY1&SUKD4Hcu^r%45V**8w3lu#eQ1qlg(Nh9NPYV=1 zBNU3Ru9P-SK&nsVpN+jH6m6Sti=M4ivahV@#Y%bdexc|k=ZB(~?NIcJ9g1GHL(yw? zD0)&fOs z1d7@U6txp5YA;aKL7->>fuaS4LebBa(mM%Ab$b4TX}^S`=9yH-=9TO#D_XR9`LBaQ z(PGXIMT^^^XbC$MEoq0MrR-3&v>l2%*`a6|I}|Nzhoa?dik25BT0x*_MS-G~1d2Kf z6m=0OT3MiI6@j8v1&X=~6m=6QT1}v+yFgKcKv55YqMiapy#$JS3l#McC|X^hsINd# zKcP^xaPv~9gOj2@`47o1(!6-2-!Xqi>)*VRePu;!H!lx3G!(7l{7|&69f}6np=doj z6b-aP(I7h%4Yotk5IYpDZ-=4{Y>GA%DB4J%Xk&q*O$3UD3KVTBP&7=SXfuJL%>|0K z5GdMGplB(Y$nh0#f}kf7NkhC~BEW9nrj!ePu<*G%r7Y zWGFh;`Jw1II}{ynhoTegP;{alicYda(aClwI>in}r`nTU(GJ&F*0!5b#6kQ=ubfrMi zRRTp<3x%SinwNe~K&m&^COAijqH4Z(eNFR9_LUXg(7e3BF`?*2=ZB)3>`-*G9g1$T zL(#2vD7wuKMYr3b=ngv+-D!uSyKIW?7AU$$py*zKqWc7j?iVO}K%nSBfue^5iXIjy zdPJaTmO#;?0!5Dr6g@6b^n^gslLAFg2^2joQ1pyI(X#?Y&j}PgFBFQdYhLP`fK)e4 zv;O)}^lyIH|3dRh_LUXA(!9L=aiQo{=ZB)#>`?T&9g5ztL(!XdD0<5dMQ_`o=p8#0 zy=#Y}_iT#Z7byBbpy)$^qK^cMJ{BnYM4;$Xfuhd@iar-8`a+=SOM#-V1d6^EDEdaA z=v#rJ?*xjz7byBcpy)?|qS*pPKM555EEI}fYF;`h0ZE_F5}cPq(MkCW*}pWeWM5g) z@6F2>pAd@XIzJTsVTYnW?NIcW9g6<8L(xBWDEik9MgQ5MsHR0cZVyGZHbr#;MJ0iv zdV!*{Kv6S+qKZIKbAh530!3AUqLuL^gOkU-JGLZRr_=B39Hkm}C)4)t%LXimN@TBJoK`^t)zXi@(Bq)@b^^Fz^6b|_lf z4n>{pP_&F4ik7uQ(QG6s;)~iWX~8s-Bz_ zP0N3O(c&$NNBURgu~v&p_LUV4Xi;9})KIjZ^Fz@`*k>4n#D0)_)=sAI+=LL#h5GZ<4py(x`P;_I9(z53yMTh4vG~N`7Zp@F- zUT#szzOtg%Ta*W$7mD6+ekgj=4n=R-q3CTp6uo1IqId03^qw7x-nT>12X-j>(5C1k zfufHEiarr2`c$CkGl8Pd1&Y29DEd;M=qrJuuLX*}5h(grpy)e+qVENYeh?`7QJ`qH zK+#VEML!D^{UT5_N1*6ep-}W{i_-W6q}o5jc`X#p%HNv(twkmK%8LGMQ9ky9Q1qAc zL($)MDEh|^MgQ8N=s!CY)l}n=dnl^4Ls6X_ib{4Us<$aB3ludID5?k)H5VvqAy8Bm zC~7HC)JmYJwLnoDfugnoMePKN+6xqQ5GYzeplCsXqK*PZ3kei0EKszFK+&QCMT-fA zqPZ*`a88I~1*8 zhoTkjP_&XAiaOh&sEbX}$^u2J2o$Xg+S4k0!3R16m2a~w2eT~wgN@l2^4KFP_%zkR|*teB~Wy=K+!bT3B5jVFepPWh4k zP1Q>Fl@;AqEq{4cD7xMGq38}f6y0fuqPy%+bhjOf?y*DBy>=+N&kjZR+o9+Io1zB= ziXIXudRU<75rLvv0!5Ds6g?(T^teFL69Pp~3KTshQ1rAw(K7-?&k7VhCs6dfK+y{V zMK1~zy(CcdvOv)*0!6P1g`!)krB+ubMSo^Ew}zr~8XvG#E7@08^j5Xp_1aMMw(~>L zJ9a2~*A7MR*`ertI~09jhoTSdQ1p=|D z8`aVl2}t$J4Cl>Iv|0Z2_D8jnePu=eRLj$@4@LhvKNS6EhoYL6@yI?F5S23lwz_C|W?E zXhDIZjsiss2^1|XP_&3Z(V_xHiwP7hE>N_DK+%#yq3Ew_>6`?l`f9!{`a2Yzm0niA zRLe^Cl@%@9vV6~tp=dehhoa@}P_%*_idM8k(MonG>THLiE_Ntd*$zdk*r8}uo1(4) zMco97Rud@dE>P4UP}D=9sHZ?tFM*=o0!4iUidGjW>MKyxPoSv3K+zfkMQaKattC*j zwm{K30!8Zz6b%q4T2Ckxb!u7qAOWe~oxdBqOv~bt{wevkXkg1q_LUW_-?IGQ&7o)m z=ZB&V?NGFl9f~%#L(wL7C>m;qqD}2kG|Ub~o7tggbDN?q1d6s4DB4P(XlsF@Z3K$8 z6)4(HplEx6q8$W^b`&VuNuX$FfudamiiQgm?J7_-LZE1*K+!0HqR|3HV+4xE3KWeK z3PpokmX^OIDf%XV)p1BDIzGLuetgSH_LUV)XjvY7TPT|7{7^K>4n>pgP&CC3MSI$z zXsR8GrrDurx*dvU*r8}Io1(o1iuMsG+E<`xKY^nC1&R(3C^}G}=pccjg9VBX5hyxT zpy)7xqQeD>ju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(3ProOEbX3vR5z<8ID3Sm zZS$R^6I)iYudL|QmgVE`2t}tkKNOvAhoUp=P;{mpiq5h_(b;w=I>!!0=h~s@JUbMf zZ&P%EK+%N)MHdMaT`W*^i9pe%0!5bz6wMSUx?G^>3W1_41&Xc`D7spp=o*2dYXyp~ z6DYb~py&pHq8kN@ZW1WES)k|^p-^;k%hJsWNcG-)TXae&8k|3)-P*E}ePu;=wk*GV zS17v6`Jw1;I~3hxhoXD!P;{Riite{V(F1lUde9C<580vUVVj~y1d3(}6g?_X^q4@= z;{rub2oyajQ1p~Q(bED&&j=JfD^T>DK+*F8MK1^xy(m!hl0ebR0!6O~6ul}?^qN4? z>jFh@2!*2CTb6!HK&l-xoI66%;f)X2T2`{JtmxgA<%RDJMejL36uobUq7Up)^r0P! zKC(m6$95?C#12KD+M(z(I~09xQ}l&E(U$^6UkMa_El~80K+(4XMc)Y&eJ@b-gFw-b z0!6b0ihdF(`dOgp7lEQV0!66T3Vo}lTax7w`J+D1f=?D{sa5}g`ytmW%bLns$^eT(F(1~ zGan2^D>^?Etz?Iy&UPs3VuzxY?NGFe9g0@9Ls3^d6m_#h(P}nD-35vo1d4hH6!jD+ z>LpOrTcD_qK+);~MSTT|`Uw>E7bsdoplD5jqO}By))pvQN1$k3fuaEdMe7L^4HPIE zBv3S1C=@N%s`OL>Qhgxb7A@bZc%``=6s9f~%$L(vv?DB98vMO)bvZ7oo=jX=@10!7;i6m2h1w1Ys=jsitH2^8%t zP_&Cc(QtvHT?L9p2o#MJC>kYDG+Ll&j6l&?fueB&MdJmEb`vPtT__Z7(5lqtk))`c zzv{SQD9V4~O#L3MD%n?7G`UrIwMRqI6z7McJ?&65)ec3|>`*k_4n;HUP_&mFiuSfc z(LQ!4+SjINKY^nC1&R(3C^}G}=pccjg9VBX5hyxTpy)7xqQeD>ju0q1QlRK4fuf@Y zijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlZ8Uj#8#!P5|C;`zC%4J6b;Pdlvb7OD=Rvq zRe8qaq3BHKhoZCWP;|B(iq5e^(YbagI?oP8=i8y^0y`94XosSUY>F-xD7r+T=u&~A z%LIyM3KU%~P;`Yr(Uk&4R|yndEl_lgK+&}VMb`-wT`y2{gFw-Z0!23o6x}RPbc;aI ztpY{22^8Hf6pBu3RXQ&LsSeD4?)vml^jaQww5nuZSMj z>XP~9=k8FnRC-zcJFP0&S61{vt8(o#q3A>BhoX<{Q1r1KiaxPJ(WiDO`pgbRpWC76 z3p*5jX@{b(Y>K`XDEdaA=v#rJ?*xjz7byBcpy)?|qS*pPKM555EKu}|K+zn5qF)7y zeiJDAU7%>LK+zupMSltu{UuQJw?NT90!9A{g`)Rbl~znZs=t>LocBY~YWb1=f2}In zS5{PNU0(mWP*mUge?HPL+o7nL9f~S;C~9tpq84^2s@kEbr5%b|*`cVlO;H z?F5S23lwz_C|W?EXhDIZjsiss2^1|XP_&3Z(V_xHiwP7hE>N_DK+%!{MN0`3EiF*g zNuX#Mfudyvik1@!MYXL<6B3Z>6&X%l>*6um0_kP-%eSs%Us+M-*5wml2t{3-AGbv- z+o5O`I~1*IhoY`_DC%a1qSfqB)ZGq64R$E%VN=vops1HXQE!2wJ_1Fn3l#MgDC#Fr z)L)=z4S}LH1&Y=ZC|X;fXdQu~bp?tB2o$X+P&81WXplhBV1c3`0!8Z!6m1|BidJl0 zx-|i*cFAy73Pp4CH~2SfUCF+(qM@zJuf7zDHg$d|8fJ&0&FoOLxgCnOutU+7b|~7) z4n(2?9kY3KX3r zP;|0D(J2B&rwSCECKQUMv@WfkfK-3a-_zeS6s?%=YMddIq3Cft6g^>6^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22! zy&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R)In=-$?)XA+R=J^AM6zEJdO z{&vXwtt;7AR`hY}^0#k?qEDP3iaxbN(Pwrj`rHmhU)Z7OOFI;OWrw1#?NIcM9g4oS zDf&*J=zD>p9|Vei6eyZ4Q1p{P(a!=!zX%k~5h(gqpy)S&qTdCI<_Z-3AyD+EK+#_U zMSlwv{UcEHuRzg%0!1}#;(<9uwL+oj!`7vC?<7Tc=G&r=LecyA-gRA@O7@i%HEUCD zcrO%HoF9ss+o7n19g3=UC~9ekqE>b&YHf$2Hg+g#YlotCHbw0PiaH1sEg(>|pg>Va zfue;3iWU|qT122|QGuex1d0|HC|W|GXi0&hr38wW7AWc@P_&Fd(Xs+X%Lx=MFHp3C zK+%dqp{Tx1X`2M3dO?O$Zc{wcPxrLb1GYAm>?M74?@wZ&JRUh?NHRs4n?ck zp{TnZiW=-t)WZ%%J?&7`%ML}oZHoE`6s;~$)K{RWpFmN6fuc18iq;e;T1%j4ZGob7 z1d7%bC>kJ8w4OlGK!Kt`0!4!biiQXjtuIitfk4rQ0!14M6m2XNin_EZU66oOZ^?hw zaph3-N+z{Qn@aYT6>Zk0{J=+{XmjU>qAl!Dw51)2wz5Of)^;e`#tuc>+M#GWI}~ki zhoT*9igpwz+DV{jXMv(!1d4_W6zwWdG(w`=6?9g6m|L(%?rC_2CnMF-lU=pZ{39c)u{h(OVy0!4=j6df*5 zbc8_Bkpe|W2^1YIP;`ty(Xj$W#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@6rC#Pq3BXO6kTSAqM3Fmy44nXiaro1`cNnoJSUWs<&l0pN66_nN+!LCHu;XTC^=M{#_`lIzJS(v_nxV zI~29HLs1($6t%TOQ9C;nwYNi22RjrkU{kc9Kv745qJ;#C78WR4M4)I`Nr9rJ1d5gxDC#6ow2VN}vI0fR2^1|aP_%+T(TV~^D+v^J7AWc>6pAWsOY0^e z)x+{#q2_IiNBSpbQY*KuWM5fPx3=XGKZK&yoF9t1+o7nz4n;leP}I{7MZN4$)Y}e4 zee6)Qx*dx8+7$H@DC#dzw1z;@ngT^@2^6g@P_&Lf(YgXf0|biJ6DS%eP&7!OXs|%h z5P_og1&THhDB4h8J#xdRu;s)-@D;*7$&}Z6*84 zineT9zG`+T+RFK%XlpwZZDWU`ZS7FBogIp{w?okmb|~7>4n;fJp=f8DqFn@vh6@z! zDo`{+plGB((I|nU(E>$d1d7HA6pa%o8ZS_^n?TX-0!4cW6ipB)nkY~-NuX%5K+zO| zqCEwQrV12I6ADF}w=F%FfKvahUYpSI=ie-1_aIzJTcXNRKw z?ND@p9f}ULL(xHYC_2~xIobn0!2p(6dff{bhJRxF#<)$3KShD zP;|UN(Fp=YCkhmuBv5p+K+!1zMW+fBohDFpxS+nCHu;XE^J%w`D-Y;$oZk@VmlOFVuzwj?ND@?9g1e!q3Ciu z6kTD5qATrCbd^of)dEG=2ozl_P;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+ z0!4QS6x}IMbeBNU-2z4T2o&8bP;{R_(ftBN4+w>#^V^oTOF*i<@@>%tp=fmejP_vL zO7@i%&1zfT_xDirsPjY7V|FNd+zv%g*rDi2I}|--hoYzLQ1px)ik`JY(Q`IM&kGd2 zAW-z8K+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-t zAW-z7K+#76MIQ?keIgW!9&TH@C;_RinID!t5{kCVUxNI!Z6*84ioR@He&~--^p*2N z(bsk;`o<1L-`b(*J3AD8Z-=5E>`?Th9g1e#q39=@qMrqdei0~|BT)3KK+$gkMZXIa z%@rv6L!jtSfug?zivAWT`bVJXUxA|k1d3|f#lv=rY6Xhw1d2)mMfCzjWr3n*0!0;} zQ1p4*(q{=swQK$)_C+Y#KHnBKZ&%5_vZ7Y)%H_X9QETUiqBeFYYHNq0c6KOgZ-=4| zb|_lF4n+&vp{S!BiWagdT3DcH5rLvb1&S6EC|X>gXbFL$B?XF>5-3_)ps15T(J}%> z%L)`NCs4G!K+y^UMJoyvtt3#?S)izkK+(zqMXLxDttu3Xs_jZECm_{XEfSoT?TSbG z59Lp9UE5W%udJw{U3uewLs1XshoYW#DC%X0qTY5W>SKqZ)$LH!*A7Mf>`>I-4n=F& z6s;*xw3a~8+5$!E2o$X=P&7cGXgz_VfdWN?1d0X=6b%t5T3?`O1A(Fq1&THjDB4({ zXcK{=p#nvl3KR_!DB4V*Xmg=Zv|78;lmw*uLB4n0JrsSMZm~uqFrr@MhFy*6et=cP&8Vg zXpBJ7Sb?H(0!8Bmigpty+FhV%4}qcy0!0%AiY5sZO%^DcB2cuaK+#lzqGc z6dhuRqC@RabeJ8A4!1+m5q2m#(x&Jrfuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!n zlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugeoip~)zI#;0RJb|L~g+kH3?MiT^t>I4Ua&*ai#A0s2^767 zQ1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?(2^4)S zQ1ppF(We4Mp9vIwE)o3|>vahV@n|9@ET7;r+oga$6 zvqRDMb}0J64n;rOp=h=pihi;~(a&}$`o#`Kb8L!!6)5^mpy+pjqPYS^e+U%)DNyv6 zK+)d|6s>88qP6T$w6;yr zIs!%O3KR_xC|XaTXrMsRAc3O60!2dviq;n>+CZRaLxG}=1d2BPe~7#9=&0(x4flJp zXJ?X0nF+m#AV`rCLI**5QRzid&=4Rrfj|-v5CsIpf{LPohy@Y5*cBBO6&p6}T~X|! zqM~9yzwhk(O7cAKde=FBylWlS(w+NCb`mllCNrr76b&JuXea?i!w4uEPC(HJ0*Xcw zP&A5wqR|8tjUj}J+UNNvJ0S6&?WRx%DN46n*JJZy=F1eFloyyzjew%*1Qg96plBumMW+!^ zG>d?u*#s2LA)u&)fTFns6wM=`sFZ-BG6IUq2`HLRK+ysMicTk>XdwYbiwL2j6Z8D* z9FX{(c3m`1ir%shK`zdVnJ-gxR$lN#H7Q!k`BJouEk(=OQgk+3idL|tXeC>UR{lEk!r8rRWy66y3^}qTAR~bURy$?qH*68v#Xk z5>Rv(0Y!HcP;?IgMfVa=bRPjl_Y+X`00Bi05>T|AfTD*8D0-NHqDKfQ+Cf0kqXZN^ zMnKWy1QhKgpy&w#ik>8(=qW;|Xmg(5+5w3-v#;L29z}Ltv@0)WzD&_`dBM=yQuI9M zOVMt&6urQfq8Hgx^b%W&US>WIW0Y&cYEmZCarDXPnsqIzs8 zs?V0925b}^MnF+R0*VeNpr{c6MU4q4I)Z?rCIl2UC7|d?0*aauP}H1&q80=cwIrbE zC<2OF5m3~cfTA`86tyLwD4&3$b_5g^5Kz>f5GqPm^Z#)`;^*3ji1Mn1_w-jeJkbu- zV&=;fb*UB{-cX9Va=sLGV@pwYwiF%BmZBbPDeB3VqGQ-n)Qc@ez1dRKhmE4X1Qhin zpr}6qMFR*Z8c0CVAOea86Hs(40Y%3VP;@*2MMDTE8cIOXFanB(6HqjQfTEEE6pbRF zXfy#uV+bf3OF+>H1QeY}2o-gz=J$6%;;jr$XDK>h*G1#1#mtu}noun$cE6E0^?9^Y zIA4lRWlK>ZTZ$&KrKpH4MU&W4G?^_$Q`k~e%$B05Y!po+plCV)MKcH}nn^&>X#^C_ zBA{qC0Y!5NC@LYKXf6Ro^9U#^C7`H`fTD5&islngw19x3(+MbANI=md0*V$BP;>?X zMN0^wqLZun=Q|+rVFqVB*G2a3?aXR1^JR*bR|{@CLW<7jd?{MNmZFtxDO$yrqI1|% zw3;nN=dz{fJhl{_&z7PK*eF^(ZvK5ttFu75(0`YC7@^>0Y#S)P;@x~ zMOP3|w4Q*X4FnWjNkGv?0*bC8plA~TMOPD0bPWMT*Ah^49RWp~38A8;)%-mUNc;;o zqsye|2OHN{iL6Jg-jT{XEZWkZ4@P^BN_l)$+Wii970eUW>%f^*pb2qT6Af*DkU2aL?cVc}D&+DJ~@F>q4oM_U<^M)j5Uk3r&vy5`DT$n(o;N))x|iq8N?h5;^X4W#?&o>si6aMk-onIbgFSCa;_l-- zZ&~8EA)dD~(Q~-xots!O((~3No*(UbYZHkRJnyo^*m0h>A#v5op0_FS$pp{4F44Tu z^KMAYF7mva6ZcN`yxSAM7kl1aiC)t^@4m#UnVz>j@xm<6+mXmC@w}ah6X$u}uEf=4 zp7&g0-+a$|G11cfN{l^;lEt3)M&kY@p7&1T&$B%5gG8U@p0_u#dWGkGmUwBE=Y5r^ zey->3Pn>kV=N(8~yTM-dzHbWWSB> zB8Vi<+vF~TNb;3y+=UQH*4*qag-CMz7I!g3lAE`>%OR4q-)7%5lC)n(-XfB;-zVKV zlC)n4+%A%|-{{&glC)pR*)@{1->KLmlC)on*E^E5-)h!BlC)n-H8_&A-zzjElKgt7 zyG$ZU`^_F>B1!wz4C5k6``P*vB1!w<=o2GJ`{~wGB1!x4#M2{5`}wl7B1!uJp>rci z`w5Tbk)-{IzJ-yb{fxCGk)-{QtYwj;{gk7Xk>sO$-6a%B+RqtT6G_?+idY*-+IRY2 z7D?K-YHx@n?R#xEMUwW-lGjC&_T6qbM3VOHN;gN6_WdTeN0Rmp19wG|_7&gvMUwU< zyW1m4`G-V;gMXa3%ZB<)i-??jUJ zvG)%mN&DdG-bm6u`t?~PX&=7$Dw4GOpZg<8y903`lC)cZ2O~*)7k(&`wCmu%B3|An z?jKF`hVY+UwKeXGu_7H@ac@ZXUu0ADA}gJ8FSb)7h=T=H_@2_s2c0T{>;s=9d=bPc569 zUsgIfzqGJya&h6@(vtGx$>qgU@+X%rnp<9CVRG@5`K85WRUT(g@1D9_{@l_TvuBjg zSWxWcPcNBWoL@Ancwv6qStXN;X62VnFDfn0FD;%^Tvk+;U);X1tbG2I872AUB_*>a zPcND=r!0TkvnAXUq?E}|9*Vsj-=NJsx_>5R+0R)sQb4t zYQUhvf$au+b}Z=HZgAnG@WIXDqoL&6=xLm<3+hwTxXboD%W)X zSO32I7f+f$E&SWKx4(N??kc0o1)$fXW96&nF6{8hEB-F1YFGJJ=~nS-7dWuq@dHjO z?9+c#>O6Nj>Tl${>Y@Jsai%w`WX`lkssH^CQw5c;NMEr*m%GeTF91#zU_zeu?`%No z?3wmYBlV>1^emiIy(WDtUMKrEnR=o=m9JcXF8B_5T!jQ)ctO{SXH`&%4IJ1gsMP2F z7JAW$sJQIiKmXJ#P*6#!z*!1gJ04l7t6(4(O(iNWE%%oQ&*K5RSW;I#l^3nMHqxt7 z;9eIVEU0{oRJnk==yWcG(2hOBu9a^t_r?rgMtfdZ<%M5RdFdBax%k~B6rNIfL3242 z^wrFVB!B^Cb?Dlc%}o7i=b zo}D{~XY6=~mydg~sR!I!g2z?7O73O3X79MixOeJ$dQNl~cB+`5)H|v0eba!7v)#q3 z=UDj~0LZf8mL+LX<0Go_%jD@CP~r}uQX(ie1XGrR3x0&aFz-h`~YosTZjqX%K0cc0{DD-M#;>KUGuI`|;nZkM`{jV3j|< zKDgjx}|3AEEKm+(%^^+tEEy3w67^?CIP`kW)wZapTmnua5S5 z*yG3Q=$vChsE)6@znbljb^OKs1#Cy$o7|4I z-QUHIO?2$$UU%CAbR6#)e~t_8mHY;obnYf7Y?JyWnki)3MZj7~b|$9k;s= z$lHEe$A9XDJF9+p?C(BEZ;v0Tac z{!SggIx5`1=-9SRxR2Jc++9%i^viX8xFFom>gaV0caDw&-34k-KU&8%UBi8)j<0nO z_s2TcaTmNj{gFDJ+AG|r>3Bn*aNn)tH~qr>n~v=UhP$VZ3kHXKg^oLp3-|LnrVR~u zLdU_w!#!5Vi$;d~DjnY#9qvzbtan1Vo9j4nT)1cJc;m_8zE{Wn6T-Al)X zMd4nh<6{oGy**ygF*-Hec{(09J=`bixOQf^uh#LcS>fKNV}p`#x72acyl|K3cyn2} z@7MAB`QiRk$Bqlb-ABj8i^IKI$DK>U{gRI9OT%4V$05tZeUgrst_b(FI=-_i+@I^% z@Z4~>(s9c9;hv}Ct!u*lppFMF3isbScD^Ls{d8QiF5Kto_~hl`enrQO4dJe-Y07hdW=#={v$bU&n2ah5Hd5 z5AFPl1_-?{sXoKinO3ob`RU7wLG^M}%bKK|VY_HStMfXWM+wbaF&3(4c z_Tf5?bDy@eU996Z?(=uHZ`1KJ_lZ2)Kk9gt`;4CLE;`O_6z(&1e87E<&mRAjjt$&r z%x$;Sv7H?Q&pTRsu#RJOoTOukj!SerPsb~C+@j-MIzFo7ZXMI@_D6>Mgq9uM%dOv$BA}(#BF!8z)Q<@pC(rK+LkSvU0yWF9m`9@<8&T!_chDCwsz;vYdfi|%xi0* z?SFnypsl-$+IEV4u+)8odTNP#^3=mclO~lGFYu~7wy3md&a`6pOe#gqL4SC>z<$4fdw%wM+3T0>{^R+ra}V3|Yv=y6KQFm2%R9`T zK!5CU_TM!+@^s&HiFn89Y3#t$-KK|mRL8E7|1e`O*Z$n({;T@>wXX8_wYLwi-*)$~ z`|Hhhht!|x?)i0RxTC#X`(sDU+P=X(T_YFm-+7+<&z_$>UwfHV-dx@;=jBM(_`~zF zbE-aF5BK^##}m0DPgnKsTKl#o`R;@9ox8ScZy&XC_qy8^RQZ4B&aQRs;2zz`{!EN7 z9WZ2I_&M+J8Asf`G@h@Ox$b4UKSB6!vxQg7?%f?R{NTbZw^HF~#b?jY}RFIlVi8}8pq__mHl4!R3Idwb0NBd_`va?d#}l0Mq*Uqv!X zoUydDz`iIWEiG2)qF>9s@U)?IhT79bgB#sr{4?#ThS!~#O0loq+cGU9*y8?~rDeqG zySG*}8rTO?(xS0f-IMs~?#cbu)%)1P8{CWb+tnE39u6+H^CRg4-Lp)OMw8 z=}pb`75Rs|S>Q!mXf|}Sy%%k%d6=6W+)oVGY~W@`FWO48zMGxAXlu=SZgzG*bWF3Z zn_awUTg^IdcJ-q9nzh~R=Du%PvzD6$?$s*Lu4&u7UhTDO*mkd22kq*%-D}oSyP9qH zs&&%Nv+Z8D&e}=a?v?AJov`g*yRO=~w%x1OO*_Z7d;Pj=XS?0ry?#e)XW4eIUk~lL zZTI^1)Xuc+UcY0sGi#v>Wb_e(R4bYC*cCX(+ZO0%Z8g1%7?=Jt$W#;F|)Yp_}zTw`BM+e1ja!+7Fjt}gM z?ovXA=u`qBcUtX(Qw$ zZG@bxjgax$2$`UbkW;h~a;i2$3bhe3Q5zve+6bAXjgZOO2$`adkYa6wOw~rnG;M@T z*G9+;ZG_C!M#yQ}p^#(!Z{6je*~L^G7Yga^uA!o{VkXCg%nj@dGE+k4=~M|R)s&Dj zO$jO2l#uzF60$&3LQdC|kcFBOvPe@x7HcBp3~hug(MHIb+6XyI8zD=z5wc7hA zb|_?ypX1({WaheeIMI?&$jgpK^pcp#F(H=+_Qkp>Ay?>B30bcxAsaL$1HbORQBjkE*gly49$PL;E*{Y3@8?_N~lQu$b)<(!J z+6cK-8zHx8Bjk2%gxsNxkZsxsxlHLr%K2UO$m8aQ$ilol#s_YC1j_jggl`sAx~;b z$WxjUvP%;oPirIO8Eu3-tBsK7v=Q>WHbQo5Bjg2bguJMYke9R(^0GEUUeQL#9&LoY zs*RA>v=Q>UHbUOeM#!7m2zg5zA#ZCV8v`sMEO&%DEKdwi4<5}#|=A?}k{M#sM6 zC>jauTR>9Zw-!Wnw!Y&iovrUUim~+_M;UB=$5AF*-*FUY>pPCJ*!qs6Y_`7RD2J`@ zILc-79Y+ZQ-*J>A@Eu2a1is^_8iDUPs!rfLj%pD2j-#3czT>DCf$un~P2f9@>Ja#j zqq+pXMSY;5&{Q5crOx!w7uGQ9}aXadbF=?>K5i;5&{Q6Znp!BM5xQQ4<2+ zanzLHfaFA@X%YWn2PD4PZl3s&P|P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_V^L_pDC0*a0$go>I+eD~D? zUVO1#6}6C}9Y*T7NX&ehqG6GsvHS2>O3`r6m!c7DDH_R^qET!q8qJoXF>EOs%a)=O z*iv*NTZ+c9QFIakMJE$bG@gK>2?P|KLO{`}1QZn#P&AQ%q9Ou{CJ|6HnSi1x1QZn$ zP&Ac*qG<#aO(&pe1_4Dg2`D;^fTCFh6wM}}XbvG%G$i5=bU@mARwQP=Owoo&VBZ3pQgkKf zOVLKQ6kWxZqD^cmx|%IT*RZANTDBBj$CjeaY$>{)jiN0C6x~2T(N+SAZX}@SCIX6X zCZOmR0*Y=Wpy)ONif$*M=nevkwh>TtCjmuw5m0nD0Y&!^P;@T=MfVXRvOcIxv{5dwdDT<{9_9GlpiZVD~iZayfKv4|>ifR&2REvP3+5{BUA)u%(0Y&u)D5_6DQ3C>s4kMtbApu2)6HwHM zfTG3(6dgf8Q4<1+ni5cSB!TOqW&{*9CxnWEH2($%BtFZ1_C1=O7T(i;#;%K6q{Yma zDQcY-*pC27DQd&{Qq-0$Mfq$gYR8tM0=5*jXG>8BwiI<_OHn7b6m@2!s0#r_T?r`a zMnF+_0*a0%pr{7{MLh{9I);FvUIY~NCZMPf0Y!ZYDC$Q*QGWu81`tp*kbt5=1QZP> zpy*fvijE_o=y(E(h7dwUN2U4SI3V%3`Rv+0Y$S2D4I<`(HsJbN(d;LOF+>) zLa1nXn%~X=iI2DIq7hQ`rM-JAO^cZ?Q?wv0updE`Qgk}!OVL8M6fI&)(PFj~oxzr( zC2T1=lPyJOv88A!TZ)#kQM8j5m0mv0Y$3`C_0ybqVotSI-h`| z3kWD$LqO4m1QcCFK+(kn6s;wo=n?{oE+wF79RWp`5m0nF0Yz63LPh0i{sIRi-rPP! zG+&BtvFoDsX)*ITtCjmuw5m0nD0Y&!^P;@T= zMfVXDEf(jqMr#UI!Hj# zF9a0*N+VMNJ4OYDz%SkpvVqBcP}`0YxncC~8SS(NTm@ zQHJkdP|q>(F7FrAfTux0Y%3UP}GZnqTU1)^&z0BF9AjU2q@}L zK+ymKiUtx;G>Cwr!2}c?OF+?a1QZ=lK+zBaiiQ$UG>m|v;e=388{dD!0g0#E2O8T- z(HC}IG{TRWFHK+!}3ii!v*nnXa+WCDt&5KvT1K+#kJilz}zG@XE=83Yu~B%tUt0*Yo4P&Au> zqB#TJ`ol8N;nT?`b2q?OhfTG(7D7u}1qB{sE+D1Upodgu! zML^Nr1QgvvK+(Mf6x~Na(ftGzJwQOwg9H?9C!pvd0*W3cpy&|-igplC^e6#Ej}bye zn|%L92PFQmDY{yUp0x3}A2VO3=qW$2A7P$Sw2Skl=xMeTJ;RowXW3Hp99xQ>XG_s; zwiLaW<{rwI|ywpDG_@opa zZr4Sh`7!flioWs#`w{plMPGBi6n(>%qHoz!w4W_S-?63Wd$tt)z?Px|Y$^JYEk!@E zQS>tbMF$Be`h|d^UkNDsjew#<1Qh*FK+zur6#Yp+(O(1<{Y^m8KLiy0OF)qq)!lX! zMF=QLBcRA9peRZ}Q9wXZIsrv70*W#Sp`tH*zr6zzZ*3p0{!)t0uv^!e(U|!%MLE&H zeuY9xQ7-38QGzW+NwyT_v8AXQTZ*c)rKkp5ifXc@s1{p_YO_&Phk&BG1QgXHpr}3p zMGXijI*fp#h6EHHPC!v30*V?FP;>+VMNJ4OYDz%SkpvVqBcP}`0YxncC~8SS(NP2x zwIZOXH33C!2%(~^sK3wwiQA9Nk7h^1d-|j7JzCpn%zT-m_R-+VK2p?y^QEXGTZ%fd zrKmGoin_3+s4H8Fy0N9GJ6np5W=l~IHi~)@P;?9dMZE|p>PV8SfTI2c z6b&GtXdnSag9s=ZOhD1G1QZ=dK+*986b&JuXea?i!w4uEPC(HJ0*XcwP&A4VDry(? zA9FzBE8L70NYMv&T{JoxGhe3Y#Asl@!X-G7=p?ojoy?Y^@oXuYz?Py@*iv*V zTZ#(VQZ$h*MMZ2BO(LLZG66+X2q-EhplB)qMbiiRv+0Y$S2D4I<` z(HsJbN(d;LOF+>)0*XorC@LeMsGNYJ`2-X#AfV`ULa1nL)Q|ReioUXsI-Vd!gHw0d zqA~Mjik3tJ`xQVbMQ3up6rIJEqNQvpTE>>5(ZvK5ttFu75(0`YC7@^>0Y#S)P;@x~MOP3| zw4Q*X4FnWjNkGv?0*bC8plA~zRJ1tiALoF?ueFalo*_kh?aM^2j>gQFDcT$j>{m#o z6kX5xQnZCFMK`deXe(QaZe&Z*O>8N;nJq=Pu%+l$wiMmQM$zpA6x~5U(KZ5#?j)e- zE&__~CZOmZ0*dY>py)mVitZ<%=m7$X9weY>I{`%x5m59n0Y#4xP_%=9qDKiRdW?Xg z#|bFfNkGvPgiz77QGcxi5`V(3i>{NRdG;Rd$!N@cnWAT+f&B`yl%i)jUy7b%OVRUe zDca4Jq8Hdw^deh|USdnp%WNrng)K#U*eH6HfTGt3D0-cMqBjUAdXs>nw+JYDn}DKs z2q=1&fTH&ZD0-iOq7Mit`jCL4j|eFGn1G_a1QdNjK+&fJ6zwCR=raO}J}02)3qq)9 zSJZ#Y0f`@J@5G*#qD$sIbVvtV@uKZY$^JIEky^|QuHHR zihg2C(a&rtI>?ryU)U)6m4Kq(2q-#4K+*366#YR!(Vqkq{Y600-vku>LqO5L1QdCJ z?zW>SLO@X(0YyFmMNtBZ0s@NC2`GvYP?SMHQ6>RJaRQ362%(~{qke;-PEkYqK@Q(Y z(Kq%UEjx&rFH@8Z0{az+DMfjlFGbbZQdFHSMK#z`RFf@5wb)Wrn=M6k*iuxNEk*U% zD5_6DQ3C>s4kMtbApu2)6HwHMfTG3(6dgf8Q4<1+ni5cSBmqUu2qWQEvi@`Vdgmmw=*v z1QhirplARAMFR;a8bmJcC7|dy0*a0&plApIMMDWF8b(0TZ~}@(5KuIdfTB?Z z6pbdJXbb^GV+o<64uOBO0}^j&S3e!4=qej01TphvicSs!`xUGyMdLYNiYBn7=oGdT zoywM?Lbeo5WJ^&ITZ$&JrD!r+il(qpR7^n8R04{o5l}RpfT9@$6wM@{=rjU~W)V;{ zn}DJ@1QeAJP&Ai-qIm=ql@d@?MnF+H0Y&o(C|W>3(dh&fEhM055dlSu38A8Kf&aY& z62HoB3Y{cH$JmXeGlH1;GDS;+z4qJ*= zv!&=?|pI$*zm8 z3u5NW6x|R6_A8)MinemT6y3;{qMO)KbTeCuZedH&t!yc}jV(pDv!&<`wiIn+qv%co zitZwy=xzdv?jfM)UIL2lBcSMh0*W3Wpy)vYinbF_^bi3>4--)I2mwVq2q=1#fTG6; zD0-ZLqMZa3JwZUxlLQn!ML^LmLa6Baz+dcu#3$KJp)FGMtb1Ja=^$plOwsc}V822< zrD!+jOVJB#DSDADMK7_X=w-GPy~38FJ!~m@l`TcDv8CvBHj3ULpy*8kiryli=xqXu z-XWmqT>^^UBcSMg0*XE$py)#aiasKs=wkwk_7YI^2?0f)5>T{{fTGU`DEgd$qAv(2 z`jUX6uLvmmnh+{_Ht=^kAaVE03%uxaQncGheG|mYmnr%_2<%tTrxg9b`BHR%Ek!@F zrRXQN6#dMWqJwNH`h_h;zp|z1H?|ZVVx#DH0*d}1py*EmivA*?=x+jw{vn{~UjmA} zblq)7QG|e^Gy;lz0*ayp6a@qnr4vvTBcLdQfTBzSisA$mWf4%6O+Zl&0Y$llP|^Ot zPd~*evd_ClzmuY~?QVY}J!Za4QT6nod7%{5;Cv~n$(Ev8Y$>YEmZCarDXPnsqIzs8 zs?V0925c!hjE$m(1QZ=kKv5$CiW(D8bOZrKO$aDzN0Yz;HC~8YUQ9c1h?Fc9;AfTu{0Yx1Mp`yHWe~1GT-(t6}tEGqc^zC;f zL_4O(%$F(ZnjXw9lA>;$FGbziQgk$1ih8i6s3%*Bj$untFSZo*W=l~YwiNYcqo^MN zMg0jV8bCnNKmv*e5l}RkfTCjwC_0XSqT>lD8bUzPPy&jE5l}RofT9ru6pbXHXcPfO zqX{S)LqO430*X!`py)&bipCK_MV-_AOC6B-OnWERMT)lCr$bIkkC`u1bV_<~?_?=D zmGh;jkS#?M*-})*mZC{)DVofdqA6@CDrQU3RJIgNW20y~0Yx(iD4Iz?(P;z}%_5*^ zHUUL*2q-EcplB`uMe_(KDkY$(jDVtY0*dAnP_%%6qSFZ|T1Y_AA_9sQ6Hs&p0Yys) zC_0l6DjJ{ezvFqKyO;T}43ACIX7CCZOmV0*bCBpy)aRiZ&BabUh(dv@G3kIMpe7 z(yoh^OOcpy){gik>2%XcqxRPZLn|3;{*Y5<*2=)BPz9Ncl1QdNrK+!$|iasNt=yL*!z969JO9G0% zBB1DN0*byNpy*oyiuMyiMZ44eTOE-2{q`R11u5!jcl*CfkC`u1^kaJP!YnEJiSwoC zXSNg_WJ}R6Y$^JcEk(bvrRWe_ihgHH(I0Fn`jd^KzX&M$n}DK!2q^lOfFduZyX`27 z5KxpxK#@;CQIvq9fPkWO0*Yb;6lD-llu1BQoPeS%0*bN;D9RzAD3^eu1OY`!0*dko zp`sts{R0k2yu_}44oK0ZcI&!YEM~q;QLR{zS0Y8VIbVwEu%)OjTZ-zjrKmnziW;z` z=rFbvHDpWC;cO{t#70qL0*a0xpr{D}MNJ7PI+B2*W&{*9C!nYW0YxndC_0LOqE-YH zwI-mb4FN@M2`I`Zpr{=IMFj*DwI`sc0|7-H2`K7BKv8ExsHjHF@9coYTiQMSnz8Vn z{`Ypp)Fl=(U#95jSa9MzDeA%bQq+?zMaQtEs25v`db6dd4_k`*vZbgWTZ;O#rDy;f zMFR;a8bmJcC7|dy0*a0&plApIMMDWF8b(0TZ~}@(5KuIdfTB?Z6pbdJXbb^G zV+klafqapiq5s`q6x8>`7%WlW5LyB zQdGqGQZ$JzMU&Z5G=(ii#cU~>%9f&OY$=+~mZBMKDVoVf(P;z}%_5*^HUUL*2q-Ec zplB`uMe_(KDkY$(jDVtY0*dAnP_%%6qSFZ|T1Y_AA_9sQ6Hs&p0Yys)C_0mXqO%An zT1r6CGD4{6)R_OI0}`)kcgqT;=t=t`?B%hT`7%YTV!=N53uIHD0Xc{BrD!!{!jiR*#6kS3<(WL|wts|i5G6IS&C!pvG0*clX zP_%)7qALj~+DJgrRRk1mBB1DM0*bC7py*lximoG|Xfpvt*Aq~*g@B?P2q@Z02o{vEk$>+rRZ+9 z6y3v?qI=m=bRQc<_Y+X`00Bi05>T|AfTD*8D0-NHqDKfQ+Cf0kqXZN^MnKWy1QhKg zpy&w#ik>8(=qUn1qMKv>Fb5?5jD2tHEmHJ{ zT^GF&ifTC6e6tyOx zs0{%{Z3!sKC!nYu0YwD_6tyRyr~?5-9SJDvL_kqz0*bm2P}G%xqHcsxQSA)B(Nd?V zvwe|los96F{&sth);%L;zD&_E89|@rQq+s{rKmSsiu$mns4rWJ`mv>`KU<0hu%&1q zTZ#s;rD!l4MaL3QbQ}Ri#}iOAgn*)<1QZP;plCP&MI#6(8c9IWC<2N`6HqjUfTFPk z6rDgo(TM~UjU%AwBm#;~CZK3M0YwuCC_06JqEiW>q8=IkR0kyfk-_OHMRV=Cs4ydD zzD&{Nj9~Q&DVoChQdG>AqN!{tn#Pu*>1-*Q!Iq+#Y$-a8Ek(1~QZ$>5qB#T{gEk&2IQM8VLqRR*Rv#0Yx_x zLPh6f_&+%y@ofc>;=d6HxR50YxtoQ1lWZRCHU0-_-$$4|6km zyA=Incl%$?h?y@_^jb!6()m*KI_FE#8*C|hlPyJWv8Cv3wiLa?mZEprQuH2Mir!~S z(Fbf4eMmsjM+6joOhD0I0*XE%py*QqiuMsu^cev~pA%5@1p!505>WIN0YzUEQ1lG} zMc)!ow4Z>Y?+7URo`9ks2q-#0K+%r`6#Ya9746CJ&vHQA`!fgURVlj2K9K!$M$CMf zqTe!tYu8B8As!l*r z4FZa45>Ql&fTG%jP|+_L{w@b3eu~|o{#A+&+I3N#%$WHyMGZ28&o7dq!#H1x8nUJ6 zaJCdRVoOnDwiF$~mZBzXDQe1=q9fT-)QpXy<^&YAAfTuv0Yyg1Qbmqps0utD(aQ#k8nWZ1MIq}w-kAH z>v~dV%zT-mshPpNby75q^QCAyTZ(3|rD!HwicVuo(JZzU&1Or{9JUmdu%&1&8%6U7 zC@LkOsEmN3asrCx6Hv5(fTGh0C|XEB(INth786i(1_4D&2q-#}fTFVqC|XKD(J}&x zmJ?8PHUUK|2q;=fK+!4!iq0W~il$`xS2!T?yX~Wn#ZvUA{UH9;nKAQaiY~|u9=u$N z)^NTQUC5TAi`Y_hFj@~@KtR!z1Qcx~ zpy(5m2<5fTHUODB40m(G3I?Z6%=SMgod%BB1DI0*Y=S zpy*Ztif$u>iq6aQKX5?e1KfG4o}L?#c}QUN1#=bG{Va!jF~S}^k!zzZ=)2w#rab7Hd~6`VN21wY$WIL0YyI(P;`)hqF)H1qSrJ1=?+M|yTN%wik`Gj z&HkDhGhe3YkIdk_O;YqH=S$IFY$^JiEk*yZrRZO_6uBGr;V*%cq6k}x(%4euv!y7? zMo~aOQ91!dF#?J*2q?-VpeRm2Q5FG3*#s2j5Kxp$Kv9B#q9g%Dc?1+yBcP}{0YxUfTCjv zDC$KB6&)7$4>}<6x9#euVLZI2|DcWD@tFBCMg8MJ&COCYfb*qjAX|zCv88A*TZ)cl zOVM#`DLS4lMMKz9G?Xnx!`LVqPC(HJ0*XcwP&A5wqR|8tjUk|DECEF)5Kwd?0Y&2o zC_0INqLT?I8c#sc1OkdqA)x3~0*VR=D4Iw>Q4s+}lL#o9OhC~TLa3;3-0$vy#O)^) zMf*w7EjEhdG4o}LX2gT>Tcl_v=S$IPY$=+>mZI5gDVoEUq7t?g&1Fl`Jhl{-vZbhu zjiPb_islngw19x3(+MbANI=md0*V$BP;>?XMN0@MI+K8+vj`|!NT1i0BDguhmA)shA0Y&E$P;?$4R5UH_FLOZR+wAIRx)g1(8%gKKW9G{gT@(*C zZiuMpt^eO>GuMtr6Iw4ea zcihju*(v(N;M^lc8&Y@J;xY4Oir$F_ZElsKcR62*-eXJA`)n!tfGtHIvZd%FwiJEL zmZH6EDf)yhMW3=!w2y$I&j={`oPeS)2q^lJfTFJmDEgX!qHhQ&`j&vA{R9+!M?lf{ z1Qh*1K+ypLihd-Z=qCb-ekP#kAOS_c5K#0h0Y$$NP;`h8DtasKk8(ibUmBdZrD%k` zd;2{eGhe3Y?|4vlyA=Jy`BL;RTZ+6a-E)_s2wRHM*iz)Pr6|glqJS+$>1-*Au~C#k zKv53CZH&XfTCOiiV_4AB?&0XBcP}n0Y%jbD5^m~QB4AhY7tOWn}DJ^ z1QgXJpr{@JMfC|NYCu5IVT4f8pK*VK0}_ATu8aPXqAT3vq7AcR=F1cvkrh0&O^TXu zz7#cOOVN>RDQd=+qULNVYQdJGmTW0HiY-O0*izJ*jiNRL6tyLwD4&3$b_5g^5Kz>f zfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(qN52Y>OnwJPXdaLA)u%i0Y$wDDC$E% zQC~u+s8N>xkpmLnZl8^9oE6^FUu)Mz{jy@_%M=aD3jV!IiUxDO6dlW!qT|?7bUa&% zhOnh*C|in#v88A@TZ%@orD!A@MWYBP8cjga7y^pM5>Rvk0YxVgP&AH!qLT@S#mtu}nw1p{xL1m1bG{VKVM|d7TZ-ngrDz^oib~m1RK}K~a<&xB zXG_rnHi}LsplBfhMT-b1T1-IE83Yt9A)x3?0*cNeplB%pMau{%T24UG*#s1=AfRX^ z0Y$3_C_0CLqSXWxol8K`c?1-lPe9QH1Qe|ygoNv!!SQTZ*n^OVLKQ6kWwe(Ix_lt|p-9 z8Ul*0C7|d!0*W>hP;@;3MOz3cx`BYAtppU^NI=m|1Qgv&K+!D(6x~Wd(QO12-A+K! z9Rw6@BcSL`0*dY;py+NwsOaJ>|1Jk4eu`Zet(Bqy_8#q?teE*SMGs^JuRbV64|2W~ zZD&i-Lu@H}m@P$*u%&1RTZ$fKOVML&DSDhOMLXFjdV+wWCkZHeih!bB1Qb0@K+!V< z6g^8o(Q^b8Jx@TmLi`mMNzgC1#BrwXG>9xEkzk@DavF^ zQJjsUECPzM2`I`TpeUDsq67g&Ndk)U2q>yXKv8u9ifRy0RFiqI@=r+7VDxKtNG@0*X2i zP}GrtqD}-9bta&w3jsx42`K7DKv8!BijF3rs0RT>Jqai}hJd181Qhiqpr{W4MSTe< z>PJ9Pe*%gI5JE*wvi;{Akoco^UDPx?yr*9++l_(QG4o}Lj>`_d-YG@LbG{S}VN20a zwiFFxOVMz)6pdg@(MYxwjbcmDXtorMVWVg)0YxVeP;?>zMdJu4I*EXylL;sqPe9QG z0*X!{py*TriV6uRnn*xV5dlS$2q>CNK+zNeii!y+no2;?Gy;mI6HqjRfTEd%P|@IQ zKlcfzD6o$@9xFxm181VAWyj2yDJsbh@}H8TxtuRW^Vm{U%9f%swiK1KrD#4|iWab? z=ybLeEo4j4A~uQ^6Hs&p0Yys)C_0mXqO%AnT1r6CG6IU06Hs(E0YxhaC|XHC(JBIp z&LN;^H33EE5>Rv=0Y&E%P;>zSMQaEsx{!dPiwG#Xm=G$Oo$ZftK;i{^|P@y zJ7&I2(Pi1e{HLYpa?Y2cE7(%Bo-IWi*iv*QTZ%TarRXZQ6m4Ql(ba4zx`vISYY8a2 zj)0=g1QcCQK+zTgif$mFXe$9lHxf{E69Gjx6Hs&u0Y$eGP;?ssMYj`BbO!-N+XyJS zlYpYT2q?OnfTDW{D7u$`qWcJ;qD!;=jSfis3%jSkPKr*qFT%b*J7&I2(L>q6BhO0F z!<;WgkFcd^2V06BWlPaxY$yXKv8u9ifRy0RFisirTTIsDLd+?b#^mKtNGP z0*X2jP}G@#qAmm!btRyv8v#Y#2`D<6fTA7*6!j#a=okWudJ$06n}DJ|1Qhippr{`K zMg0jV8bCnNKmv*e5l}Rk5GrbxwBbV80SmT zaJCeUU`x?RwiJzGOVMby6pdj^(O9+=oxql&6WJ&lM?ld@1QeZ2K+$*tiY5?HbP54Q zrxH+9NI=m<0*Zb@>TWt=ZX0Yw)PP;@Z?MQaHtx`cqDO9`Q(xjFtZ4oLhr`<(tf zDQadnwb$ju%$F%zpA!_mDMcGNUy80|OVLKQ6kWxZqD^cmx|%IT*RZANTDBBj$Cjea zY!qEjK+zTgif$mFXe$9lHxf{E69Gjx6Hs&u0Y$eGP;?ssMYj`BbO!-N+XyJSlYpYT z2q?OnfTDW{D7u$`qWcIax}Sie2M8#7kPs@mJjY+@fW&v(M;)(_qA7Mye|t{Me3_yh zIlH+ zXg2{xFAz}lA^}A&5m59p0Y$G6P_&1DqE`thdX0dh*9jdXIpj_X#NafDkHrILF`ZfW#lNtDi@tXrFyLtQ1m?kML!Twbbx@O9| ziGZS?2`D;9K+!J*6#Ys-(QgD49U`FUcLIw3AfV_^0*d}3py+P`ivA&>=wAYgyjGd!^_@yLFwG8#7;~C_OhQ_&|zcoG(QgY$?iQOHrIHMOkbq z%4SPZ4qJ+H*;15XOHq=IqC5hMsu56Boq(bm1QgXIpr{rBMYRbiszX3gT>^^g5l~d0 zfT9Kj6dguDQ9}ZX4kw_f5dlSw2`D;(fTAV@6g4HF=tu&Jnh`=p(Omxo2PD49-~_qh zJ$-je+udQyjhQb~)G9YP{Ua%A&G}N)hAl;H*;16xmZElSDJoz~QG2!&bznRv;0Y%3XLPafe{Y?%?e2jet6 zbgvYRZ$!rvjC!lBo0Y#?}P;@E* zMTGZ0 z?!Kd=s{1zF@5!E>NhZKdLN6i+3Q7$f6zN5z7ez%wfY1a2NkBjp6i`H@hyp622ns49 z2r72PuBfQk6?;cTv0y*H@9g_Z@;vW)*ExT@YaQ0oo%>35GGsnXW>R1Y0Yz63P_&eQ zqALj~T1G(8RRk0*C!lBr0YxhbC|X58(bWVLttO!88Ul*0C4`EKEBTEbka%5#QzAug z+r8^Gm15@06kT5_IPG&Ox`FehXgynsZe&Z*2DTL4#FnC)*;2HTEk(DmrDzjdiZ-)R zbSnWxw-HdZg@B^11Qgv)K+zop6x~Tc(KZ5#?joRQI{`&^6Hv5+fTEoQ6x~BW(Jlgt zb`wx^F9AjO5m0nL0Y!TVD0+Z^q6Z0~qIH%0X%0wytbNw;Iw?BK9_c?+DQ3P*(PNc@ z6<W}E0mE4AL(CZ zq)tl2%$F%@o(S^4m!cM&FGVfcQk2V7vYR#6SHf$+s%a)>cY$lUO(Lh3|sAu%&1eTZ+zQqv$*Wit-338cje^J^@8z2q+p$ zK+!k?iV6rQ8c#sc1OkdC5>PaWfTGC+6rE2%(G&uTrV>yzjew#;0*a;+P&9*pq9Ou{ ziV2~jAqjt<0}`KTpSvC^MfL5rs3Z|HU#4hwBKYnnDVoFiQZ$z>MHjNAXdYXNE@Dg3 z#cU~>&z7PEY$>{gEk&2IQM8bNqD2H0EheDoG6IS&C!lBv0Yz63P_&eQqALj~T1G(8 zRRk0*C!lBr0YxhbC|X58(bWVLttO!88Ul*0C7@^x0Yz&GC|XAd70pWcIY*qLBKtbp z1yZykaO1i}%zT-m8xuk6U!-UQ=S$H|Y$>{#EkzsIQgjPjiZ-#OXfs=iZe>f+ZEPvp z!bZ_n0*Y=Ypy&<)itZ$!Xd3}VcM(vuoq(dd2`Jh@K+#SDitZtxXcqxRy9p?|mw=-C z2q?OrfTBGF6g@yd(SrmOJw!m!!vqvPLI@Szknl%3An`VKTeMz^#@R=-M-wsgWs3GD zf;qoQ(UY7nMNhG%=xMeTJ;RowXW3Hp99xQ>XG_rwY$&3jsyH5>WIT0Yyg% zDEgg%qCW^I`jdd7zX&M$n}DK!2q^lOfFduchwUhe5KxpxK#@;CQIvq9fPkWO0*YdU zP|@cJ|1$?9-pt^9Aw_4|ZBa%tX1+{Og=7%?B}ElEUy3TRr6|Fcq9j|2ve{CU!Y3mZGX`DXPXsQFQ`}Y7kIVlYpXH1QgXKpr{T3MaK|ORF{CFV+km#M?g`10*a0! zpr`=>MGXlkI-Y={69_13L_kqv0*X!~py(t5ikc8m)RYh^iYNV(9FX|lOa~_`89vf~ z%s#v|OUBHXDauU-r~e~GtvFwbTC=674O@!ZvZbgUTZ-DVrKkg2iaN5Ts1sX?PG+O% z6atDm6Hs(20YzO1DC$Z;Q8xmLx)V^;gMgx*1Qhimpr|(iMSTb;>PtY;X#^DYBcSMX z0*d+*P&9ymqJaby4I-duFabqF2%(}DNq@Qn50Y#GtD4I+_(fI@vO(CFYDgi~)2q-EfplCV)MKcH}Dk7k$n1G@Z z0*Yo5P&A7WDjJ^j?{h%no$X6!Bc!OJJ<`7*88cs|=)z?1R+<#e<9sQ)h%H4Iv!!T0 zTZ$I2rRWm26kW=eqJ?ZJTEv#3#cUK^MnKW!1QabHpy&z$ik1>kbR_{r%LpjCih!c! z1Qe|xplBrlMXLxXx|)EZ)dUn>LqO5B1Qe|yplB@tMe7JCx{iRN>j@~jfe` zK;r%EbJugFXpY?$txv|xmnphA864yOI*8P5(MHafqFdNfw23W6o7qxyD_e?gV@uH% zwiIn;OVRCYDY}D=qB{vF+D1UpT?7F75(gw+#cqq9lA=v^@A`{m%zT-mZ<4|7 znNsvE=S$HcwiJEGmZI<3QuG5`iVm}-=ts5`{lu1{BWx-9nT?`f2q^lMfTG_BC^||& z(eDHl{Xsy{p9B>BML^Nt1Qh*4K+(Sh6nWWt*p8wI0Yzy96!`=cMF}Vh2q;P?peRN_ zQ3e4;nFJKY38A8|lK#sMNW9R^=+{!z%O2@xWyj2yDN1AqKV(T!lJlh~n=M5-Y$>YD zmZB=&=BcP~00Y%3V zP}G2cqJ{(%9Zx{f2?P{1BA}=-0YxVgP;?RjMNJ4OYDz#+GXjd56HwHG5Gtye?N_Pb z6g_XBb*z*fKGI)jw?!?pW9G{gwaE_JR+6H&oG(S~*izJPaZfTH1qP*JOF|7-^&zQ*nfwU(lEyLUYz zJ7&I2(OKESg-IzooAagU9JUmVVoTAvY$-aAEk${3DH_d|qI|X#jbTgCST>5r5l~b> zK+$*tiY5?HG?9R!Ndy#4CZOni0*a;(P&Ac*qG<#a6%tT1oq(bl1QZn!P*hAnQ3(M> zGYKe~ML^L71Qg9CplA*uRCH#xf3pJ;zuRt$MoQ6}_9@7@*)j8FiZ0F$p2(4+`J69B z3)oV030sOTWlPaQwiGR5OVMJs6kW!aqRZJ*w1kbKD+nlBN`*6BB1DM0*Y1>P;?CeMb{Egw1$A9wFDHcBcSLy0*bCDpy&nyiq;cQbRz*p z8wjDIdD;FK4oE!PZhkJ3qG>j6%8r>YQ?w~Nh*g!M&73bqx3Z<^HntRPVN20gwiMmY zmZCe@QgkOjV@XAfV_C0*c-wpy(|Eiryxm=p6!z-X);uJpzi}C!pv90*Ve2Q1l@IMIRAR z^f3WNpAb;=DFH>F5m59w0YzUBQ1m4MMPCs@MbBjWMGi>(6?>%rtQ7s>o)`T(J7&I2 z(RbOw>Y7sYJ?Bf&4{Rwq%$A}b*;4cqTZ)dbrRZn26#c@MqF>ok^cx#RM+qqUoq(c0 z2q^lKfTF($DEga#qJIb|`j>zrFGmmCQ4}GdD2;$3pMat$0Yw1;Md<_-#Rw?MAfPCd zfTB17MOg$CRUn|KA|X`tZMMJ10g2yjUjaEJMSt2C)hgx0%$F(3$qC-6Ek%_%Uy7=* zrKl=fimI`ts5)DUYOtlKCR>VXv8AXsTZ-ziQFIIeMRf@%I+lQlDI)Q+qMg$Z!CZOm<0*X!|pr{D}MNJ7PYDPd&a{`K55Kz>TfTCOiidqpu zMadlh9|t79#6CroofAINU+nNiTj#{gmnmwW6C7JtiaKz<6m?`vQ75((oy?Y^Q`l0} znJq=9vZbgCTZ+1}rKlSlMcoM~>OnwJPXda15m3~dfTBJG6!j&b=rjU~`VmlcIsrxf z2`CysK+!+~iUtu-G?;**Ap{f+C7@^+0Y$?JC>lXP(HR63ok<84waxK+Iw0{T2B)1A z9k$z|kvTE*Wr{}S1O@J2Bu;%D?Oe{6qVw2Nl*g8$(QGNoXG_r-wiJzJOVK#C6cw4MN3qqxdaqlNI=m%La6BM9Dk_;5+7)A&f&Jm?rL9@6Ek0?=#re^ z&f}!$QqGs6g={HW#FnDPY$>{oEk&2JrDzFTimqTw(NeY)UCBn#G6IUOBA{qF0Yxha zC|XHC(JBIpt|p*pH33D}5Kwe20Yz&FC|XNE(K-T(t|Or6dIE}WAfRYH0Yx_wP_%)7 zqMHaPx|x8Yjf7Cq{2YJ30}}tj&FBIt`oYF6IWhC)Rr1oJ4Kiz=5b+XQ+?Q;<#PbF& z@vZwbWk#Z+do))eVgHPJGBKp0=T%8uoAA6EiTAQSuTG+V70;`em{8608Yb?l;dzY{ zM{0Rq(?rK(Jg;S9{;{6dCh>HA&+CxLYUp{VB!-;ed0i808+%^Q#0MvNUf)E6W}eqS zF{y>;4Nlyh>v_WyzqIzek%^PrdEThRB^^9(bmG}go;NO0v9sq*ObqMdc~cVCb@ROG zi4S{tUP&s&*DoZ)%b zBu0$%ymg5i&i1_ZiH}El-pz?dd7ig9F*V=wwkCFs^}KC~-wQl%N21F_&)c0?JlXU1 zBwn22c@HPD3q9}g#F;ZZ@2SL%#h&+E;?tR)w=Z#``zJB>Ckp3!-hsru^E~hE#Ge;? z-usDemw4VsiOUyy-e-xI7JJ@TiONen?@;2brJi>9)qIh)+o5J_&l z)m;yfr2T954I@eW=g1pJlJ@UOH;p9i9|Ue0N!q{Y+9r~;f0DC9Bx(Pq;wh1&{iAqY zBT4&L&3ZJe*L(+P9jPBmpz6@lJ-wCjEp4h@75m`N!nkIK01=L zzukIVBx!#=@x(~d{(jjhk)-_vq0=Kt`x_ohB1!uz`esLx_IIq!izMwY$yyLe+TU`t zD3W~SBXfiY2Wd^JCd|-+1(RK+V@;O97)soizMv}$NM8m`^w*eNYcJ^^L8X@pL>5llC)2reiTXCXTLs+B<<4|UqzDk`14RC zX%8R{N0N3A@aIUbyuhjVjZ+vAH#%z^ za(}2Jr)u08ccY8Oc)J8$!{MIFjvQa9a+Y7IcBK*3vz-dhOKa$5Wu5Ah=lRtQ&kNdmR?;g+va-S#h`1T6==mAEd{$P)tO{8j-0vi#`hUDsrhBP! zuQje2gl{BEuhLC>l@;_VQ_n4Xl@;|W^-`7GNkQ4=NK|x}&fan|^+e!#+4`O6jpQ_s zbg9XOXjC&hl9S%G#@g;R-8Iyv+=Z*-UWHf3{bx6k?)RVizx~gy+Va23@5kH=``!@u z|Fp=Tl`47>_shMkT|3R2w>uEp4*InzrD zEsQM~H?ydqxZLyX<=snnY%#rP($q;MlV%loEhZLDEohNHrC@f8=2HsC=1*x+JTbqh zphZ!^w1VRN;uZz1@`_7lj+<22qNK2J%Gindlcp87m@sy1UVhQk7P&3+TIaQD*(x_L zx245qE;gH1IIW;rLH?LY&2n2dZ{5tE-P}F;T zbBfEqCnij6(XD9Q%t_MKZp`T8SI(reIi)UU}|fj_px6b!y=>*9@P#Eelc<{nn8nsQkbE3UbmT z4RZat&4VDlMNm22y{tRBSngO~n`8L=Nd2^^13R==pS<2J`+9cF?a;Ds-k9*oc5OuN<+-z4x5^7&L#}&coY0%s)=jUid)aGn?*aE><7Q5sIwyQhdf7I- z;cg1;OD}+XhnBwP(l^qEx6!lgo#EaEdO>%Q!*`>5E#VX8E<$@wb?>~?Gu=B@=d~?; zW$yCuMqBCSTbEsq9;IjG_TWvq3$8OvK)IWv|EoWQJqyOnoDlwQ-230XE%)cT+!dh9 z(WdO8xhp$-@zUQ5s#=!)Ryvkm>|6)dJH6LgdEI&rO`YeiNBxeRS3TA9KhE@~6i%B^ zFZI9wVJf%mf^-)fbh+y+^#w zm0h@=T=A{-yiy6g@!SrjuPV0;8#u6$Tc*$bF7&1mQF`6GKmMr;kXuG6*I5c%OP*P# zE4MdSO&Kb#E%%!U&*KTZT2ePXWmm1cHPS`Nb(e)FbIaZ%<*wlNI-M&av}3QZL)p8_ zy)(nN(TX=#cID@mUHiG^u6}n7g{PEV(OeI?-SvCtTIg7MdENV07q{$2iL0n>+2skZ z{?zZf>>AH4ca@jBs@u5>Qs$7Gv|Pm4v+WhRW9d6eiL1@snCMxpOW%d=9l?v2UGZF} zT&1N~V+Z&CD=fuYcAap8Z#NTqb?zKqu@e}+3*DPdJ>lLHJg@X3xwqw-eE=NpJ~-;- zIniAosbW`h>f=cG;iFgS+3p(9Yb?72T*vM`r011hm+mSE-$I!Ucbnl}D)q`!&vMtT z&T=>JdaCp{;@o*d^X$Uv<9qnp-0h|3?s64{@1xxCppSHAHgd~wlzJ>P;Xa7Ew^lr{ zu&AW;H@7o+!PxazjXVG0WZN=jsdx zsO-9QPxTo%qF#@V9qZX$-{!gX?9Ok?4z1eMYg|+?r69k!;KX{(rjDIHv-4PYbrj5Q zHnnwY7fL41oI1uG$4@EDFKOoPId^u~`8W&iCC5*n)wWsj^k(C7+qsfoGuoa?AdBnEe0k16lYd zpxg)B6m$2E%yoZEQm?b@uAou3_i@=h!m|5;x#6FsloWTvuZvZ74TXQ8N0?v z{pW{y?ueG%4~320a~jlpSm}rFT<&(3-GwZ>=U8^f(cJ}wPxwd7E?%i)?sS&jA1rrw zko%lv_x;?5sPK2ieNX6y_xn=6bGx&t`=6=bVfaV7^mol4;Zn;`wmY5Ym)^#5-?Hrf zU)kM1P?uigrS~pN?>3g+LoD~Fr|i!_+5J1N;IeynrB_^d7t!m}qerKDjqT4%x1y=_ zdQBZuFm9Z?YdxGtnW;ZQJbFCwfByqz51=c!|NeEqB3|0OO75|~ZGPE<>TVs~|MKlI zsTXPCo(wuP8_;|}x6=lC>DjRXnSMMYCt4*^HB#NL5vdue6{#Jm6RDeaT%@@@T; z@{@dfOjhof?;ek3m)rKq0rz=P&wa*Izsf#YV8Qp?Cn3uH z@;&#dn{vN=&wWy*+%MmApR+0V%Y7=i+_Kl_K0Q&uSrv%0CH`&@47*j>lLI*!oMJyK3Rf3lA5Gp?yUU&lo{uGDdpjyvsBE$;0+qT}oC zw`Ti89e;7Z0oxJxF1KTK_j|Ep106fM%Wk`uj_0_iZBNkgX7{eNeV2}3xOaf4hH?fFA=TzYJ{*Xp?6y<_e9ALv-E zVYnOUIO>FOPtx%gcLmtX->u_UCx!bL9h)}`_sKezxGTzD{t_J@%nkRmI(luwT~Wv0 z?h3V+AEx874&lB|$JaWA`$HXTxGUaX{&*eF>k{tsb==%7+&gvrrboDc)3IgmaCg>m zR^Mh~{&-Qx==gAF>)3B%xX;va<>YYRsNe%6qaQD*j;%(u+QpcyZhx=6><2%D$UB|(@!hNoeYwivACLQ0uKipsIc-({G zZlUAEhr>Nn$L)`X`ym~FemvZfC&FW=C&ObO9Tz+u?yGcs=Gkz+u49E4!d+9xq5Hy} zr{lVp!+ooc2lt2jTOAv|9`0NnC%+Ny3v}G^R=6M0@z;04?Y|oyPkBE)o~Gla2gAKW z$LBr@_ZvD^`ZV0NbsYYAxbtyN0(eWeqWhwLUosK6Q3U_NAr+gpoIXd2RINXov zc+`FA%FYjtgvV2V36H1ixahZVuhQ{_-^2Zuj>*5meT$tCC+dfgpmUaw0?_}-1I*!nBjE;pm&eQP<9oOi%Nyi;JKBD6b zI;PwGj|}%kCOf*fXTR*|?slY(qwW5P+wN|GmsZJr=~mrqUOZ=NN&XmjEGY_)6M4!# zv@G$O+haMe`IzEjuepWh|M>}q=I#+`^KtgMQTGYy@rCZiQ%~oQ8BvG zUw^r~IZkGHKhn-|cO(AemwPv*e${vXx0mz7`9EIHo@c)rx&Pd|{r~mln!1~alu|8b6c z(reQw;x#B2cyi2tz1*3NBVIi_LBDvp^V}}~cBglbq|DjdwYSIHo#~$D9QUMmfqQ*s zlV3b$}`N%{lfuE_bi*Nv^DN&s*r8F8}&gy4Poy%PwC9_aCos zwR_rLUrYC&{p#nwRqhyj0sXS)*?${!eRfXym)q(t-*dc>JMwbnAFj1+Uf9BY?!8@ymaXiQRPI4` z%iMDRZ`aPX4z1g_ZdK2IjgHUn)xUT6b?ERFN8F<{UaytSJyI(O|7~h%D>0l8%&F&53|Qxk&GPo+_bb{S7^E*jkCp5xcEml{-abSlM`x%X{aMzG2Ku}jN{)pqZ_Xf&|TqohS+ueulUZ+9=? zH?7>wo?hqPwBNGIaQAeu!p@JR_ja!`JsLeBuy1~f+263#NZ&Poted%Bw6SJgH(Pnp z6E%-8o4M{{8?Jid!@APw!3_tv@5vX%3Z#bwX~kh8TBa*j4aMrkADTy2D$r;U(2 zZG?>0Mo7LkLdIw#WUMwq#%Uv@KpP?BwGlEw8zB?55i&^|A(OQca=vybOtAzj@qRCG$rl)wAtjm;GE-ARW@$>u1)35vTT?>j zXiCUjO@v&ijgWcT2)RfbAs1^SWWF{+7HA{n5^aQBs*R9^+6Y;sjgZCK2)RrfA(v|- zWQjIHuFyuvQf-7>sg00j+6cKy8zIZJ5wb!XAuF{*A=CVd?t@9@PWJ&PS{Mp>+0lru zikTb}a&2JWP@596MyE>1T1^RArzs)VX-dfTni6t@ri855l#m-WC1iu9gxsWwkejs; zvQZl$w`e0|lQu#&Ya`@VZG_yWjgT$c2-&KQklVEpa)&lT?$k!eHf@C5rHzp7+6cK@ z8zDQi5wcSoA@^t_WS2HVc55T#UhPoGYQKfM{xd7tZOApDkh%8seKC_`LLLn4o2^qq z9@422^020aJfbNfk7`QDW1153xTb_Wp(!DIH6`RpO$m8Q6CqD)Bjg!vggmQ_kms}! z^1L=eUeHF!i`od;r;U)8v=Q>MHbP#}M#z3`guJSakk_;k^13!c4rn9f4Q+(Hsg01g zv=Q>QHbUOfM##I`p^!cP5O@7&u5lcq4}?Nm*?p4tVkXCgd>Gg_;-`dsq*Ep2V@(P9 zL{maO)s&FWG$rJ7O$qrzQ$oJfl#s79CFE;OgnXlokZ-jSa!4B?-)SS{du@dLppB5j z+6ehk8zDbwBjkuSLVngp$S>Lm`BfVsziA`ns5U}=*G9-6+6ehm8zFybBjj&wg#4q8 zkbkv9As_f9?)uNX%kFy|ObLlkx7!f+MJ=OaKNS>>1omSZsh=$iB05_?6_n1_PX)!; z`l+A{wtgxoldYc$inH}oL0N45R8R%Bek!OUTR#<4iOo+1B?$afP?Eq;1!WWXsh}JJ zKNVD&z)uBLA@EZ{RSEo5P&EQS6;z$TPX*N=@KZrG3H(%0EdoCkRGYw01=S(&Q$fcN z_^F_}1b!;$SOPy4RFA+<1=T0;Q$fcO_^F@<1b!;0A;AHu7>%Yy{0AM7_(r>X;zvS7 z7rDpP(c>dA<7J9Yj0E;$J}E^falRBaVM|d{wiGpEOHp&S6t!SWQA@TI<+7!y61m77$Q$2?0fy5>T{|fTBeN6fGv8 z=rRI|E+?R92?0e{5Ky#~fTAl2C|X89(NzQ#EhnI81p!4X2`E}cK+)9%6s;zNie^Oo zWe!NZqI;wrEs~;UsmEE7nE5hA>mq^um}*MVb(}9n*R!SQ2DTKfXG_tIY$@8nmZF>3 zQgkz0iZ-&P=oU7LHW5&?nSi2O2`IXafTAq~6m2D-=yn2%?jWG(P6CRy5m0m&0Y%#h zD7u?~q8$Vj?IfV+9s-JX5m2<7fTDW|D7ue;qWcLb+CvBxt%>-rIUwc>;=FAfV_)0*dw#Q1lW3MK2Rj^a=q*`w1v|m4Kqx2q=1;fT9Bg6um(}(VGMm zy+uIL+XNK7LqO5H1QfkTK+*dI6n#Jl6+IO3Yq+m;#}C^B_lKpZ*zR2)jKs{BDf%Q5 z*pJDl6n)D1QuG;Hiauvc(HCqf`jRb0U$Ld=Yqk`9!Dicstg@B@}1Qb;xpr|?l zMKuU0s!2dmEdq*a6Hru#fTCjvD5^_9(Xj*+)gz#&J^@9?5m3~CfTD&36dh0Cw&(-` ziW(6@MM0Xs*#U_s+*jYD>1p93{YiFP)Hp3>zD!Zmw7~wFj+CNioG(Sq*;3SkEk!Na zQk2V7vYR#6SHf$+s%a)>cY!tO8pr``@MI8w!>O?@%$pjRgLO@Yx0*X#0pr{K0 zMO_If>PA3OcLIuf5Kz>UfTCUm6!j*cs1E@}eF-Q!jew$l1QeZ4Kv91}sOY3L{~HG+ z9(UiP6Kx_zzCF?(kQOsvrf5i7V1La^O3_fxm!e^8DH_g}q7iHz(Rl43!lu`g~6mZC51!&^~W z%zT-mS!sd&H9;vw7jV85&1Or{9JUnAWlPb8Y$=+@mZFQ;Qgks}isrMWXaO5Vmk>~N zDFHM1p!4%2`IXffTCpt6kSC?(Q*QcRuE9Ml7OOB z1QcCOK+$RfimoA`=vo4b)(}EPC29UF2PEFeK1DQBif*^tqP1x;^JR)|NDJ0BmZJ5X zFGV-9rDy|Nif&>{(amfr+Q^ooTi8;xi7iE&*-~^X8%4JfP_%`BqOAlJ-A+K!9Rw8J zNkGvy0*dY;plCY*MRyZWw1a@6odgu!LqO3k0*ZDMP;@T=MfVXMFNWU5m59J0YxtpQ1l7`Mf(XTdX<2p*9a(j zoq(bP1QfkNK+&576um`2(c1(Ry+c6Jy95-yM?lg01QdNhK+!=0iasQu=p#a?=+QJk zt%*}~p?%izF)2D|-~aP*TFiWzqR-QU2F;}C3(l9KFWFM`6zr_Z`SLxU129Mcv&D*teZV2q;P;pvWhnC`v$4KnN9mn&$U) zK;onAw&*h{I&34|kC`u16!!!BYZ6npMOmCLMHSdmRFN%3mDp00U`tVwEk)UEDav6> zQDwFiRbiv3Dgi~+2q>yfKv4|>ifR&2REvP3+5{BUA)x3O0*dMqP;@K-MfC_Ms!u@C zaRd}KAfTur0Y%3XP;>$TMU4n3YD_@Ui3Aj#LzL_>kM#5Gk$w|D zX1+{O3qP>GW;3OzCFe^~E?bIPv8AXrTZ-DSrKl}iirTTIs6AVXIQ6w?00N2z5>PaV5Grcs`v)A5c)ER}vAGm|VYfwt{h0YOMZ^8T{+ia5q7j@g zMQ5<3=uEa0jbuyFS!^jfn=M7>u%&1eTZ+zQOVN336y*_6G@5{-d;*Hb5KuIhfTD2( z6crFqG@gK>2?P{PB%o*#0Y#GuC_0~jqA3IvO(mdc8UaOx1QbmtplAjGMMVS@6%$ZY zLI@QN_5E6HoT5c`S7?|Njk9~#GyRzPGDUOz!2X)wl%lzuFGUx!rDz^oiY{VH(Zy^j zn$MP^1#Bt0ge^svvZZJt8%2uT{?fTF7jC|XTG(KQ4VT}wdG8Ul*e5>T{`fTHUNp`r_Xf3yPUuwBzD&^uKd`?hI;H3)&X=N_*;2HTEk(DmrDzjdiZ-*Q=vKBA-Nu%pEo>>; z%0|)c1QgvtK+&B96m27*=q>_^wi8fvHvvUE2q@Y~K+!z}6zw9QXg2{x_YzQa9|1-8 z6Hv5=fT9NoD0+~9qK615dYFKsM+hi-ln^Rf@B6noAn^xH(T!5H*T!Rh%zT-mC;hsPr#N4Vo@PtYGi)h(mMulkv8CvFwiLaQjoo=6osohAl# z`V&wzfPkWb1QZP-plC1wMMDTE8cGNiwT$|YIw0|dZboyZ=zY5_8WxS2FH>}8G_ZeW zC3RaglJlkLEVdM#&6c8b*itl#Ek)p{Xf#`j^4TaFLqO430*b~FP*gxb z(Rc!iCJ<0Gk$|E}1Qbmspy+%8ilz`yG?jp&X#^A%5>PaqfT9@$6crIrR7^lo2?0ej z2`HLHK+y$+P|=8}AMNQBePy3@JVT25rXH|GW9G{g&5H*1&-A1eUBvlPbTM0s=Ch?} z0b7bLVN21aY$;mEmZC*$DO${yqRZGQx}1QbB?J^*K|s+`0*bCAplBHZMOP6}w48vV z6$BKmB%o*&0Yz66P_&wWqH72!x|V>VH3Sr`C7@^>0Y%plP;@;3MK=&ow4M+unj7`| zIUw+QgQk&1@;Ul`TcLv88AWTZ*=_ zrRa9H6y3p=qC43r+D1UpT?7A0Pi!eV!j__+*;4ci8%4hoQ1lxCMMnuJ z`kjEHKL{xLlYpYX2q^lSfTDj0DEgOxA}`Rxb`(VjC`u!s$S0sENB}@WgpQh1TphvijqNK|4d;@Q8wpGQ4U** zDzl}i3R{Y*vZbgRTZ*c)rKkp5ifXc@s1_SVwFxMyLqO3n1QgXJpy*fvis}(iRG)yN z;|M5fKtNGL0*a0&py&hwiW(76)R=&x6A36fiGZRe1QazTpr{!EMa>B)YC%9zOG2oq zQs9qqK;lR3k$xfwAL$>kZ#K#eV&=;fwG9IMXD(BU+Ht-VwP#CF2euS-WJ^&ewiKPr zmZDSGQq-9(MW?c*s0$lKT?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`D;^fTDf` z6rD~$QGWu81`tp*kbt5=1QZP>plApIMMDWF8b(0TZ~}@(5JE+*1AnUn5`V&Oi`q!h zsdig*Mi4V!rs(V-uzw~srRW^am!eT@DLR)eMdz`lD32{gquElF&z7PwY$+PcmZEWN z6crFqG@gK>2?P{PB%o*#0Y#GuC_0~jqA3IvO(mdc8UaOx1QbmtplAjGMMVS@6%$ZY zLO{_>0*Yo4P;>zSMY9PgnnOU*TtcX5WZ-}AfW%L=yFzE7$nGRv7{tt%DViSy_Rs95 z6fNLT{;fTFbo6s;qm=sE(5t|y@A1_FxK6Hs&` z0Yw`KD7uLdD!M4}+c+Tck@m3cVkw$#w?#JxG4o}LHV1+IGtDVQw{pG|-Nu%pEo>>; z%9f(r*-~@|TZ-;vOVKvA6y3#^qU~%H-AzEz4g!jH5>Rvx0Y$qADB4Xx(Y*u|-A6#t z{R9;4A)x310*W3apy(k2iXJAQ=n(>n9wngYF#?JnC!pvF0*dw$Q1m1LMNbhzMYjb0 zTn8jR#_kGjlA>qb^P*1&G4o}Lo(}^1XTDR4Uf_HwdXX(f``A+S5?hL1W=qj4Y$@8$ zmZDeLQuG>Iie6`<=l}slZxB%QCILln5m59t0Y&c+Q1mVVMeh+%^gaPa9}rMB)YC%9zO9F~= z2`FksKv8Q#s3<$#@9%)bd)vM1ob>RKzWtjC(KhKZ^JR)Uqz6;;rKlt4OHn7b6rIeL zqEpyX)R`?sr?RD}3tNi1vZbgSTZ+1~QPhKgqMig4^&+6CHvvU`2q@}HK+$Og6!jyZ z=yU>#`V&wzfPkWb1QZP-plC1wMMDTE8cIOXFanB(6HqjQfTA-9C_0mXqLGA9QM+{i zY6m1f**=K1m!ezk%OPi_$IO>0IyXJoHCBqw<9sQ~V@uI!wiM;FrDzOWipH{~XdGLL z3fNLKo-IWa*eIGvK+z-uiY60KbUpz^QwS)UNH-Zi_CFB0u$jEj?zwOwpF~pvy!l+RFJ- zbURy$?qEyNoop%E#+IVH*iy8eEk$>;rDz9RigvP5bPoYVy9g-SO+eAT1QgvzK+*jK z6zw6P=m7$X9weaXAp(jXCZOmM0*W3bpy)9IiXJDR=m`Rf_7YI^BmqTF5m59r0Y%Rc zQ1mPzRCH^)Kh6P(Z?K!6+oULNF^j0g2yh zAJJZvqR#fP|GV^<`7%X6rUx%hk)oeCUy6>frRZn26#c@MqF>ok^c!1>jS`2-Y22`CB(C`u=wC`Le01_4Ex z1Qf*yD9R$Br~&~+6$vP+L_kr3fTAP;McIT<(GThVVFx5$Xg5EHrRZwAcbyZ9nJ-gR zEf!=KN>O#rm!cYMDXPhqqFQVzs?C<7I&3LAhAl;P*-~^YTZ-zjQBiCYCu3y zLjsD9C!pvA0*V?DP}G=!q7w-yI*EXyCIl2UC7`Go0Y%LTC~84KQA+}fatSDEMLlyY(J%svh7(XUf`Fnk2q-#}fTEEE6rDvt(b)tPokIu} zb&UD*9FX`yH=~`TXo=kxjf%z0mnj+@3vMiyqI}MmqA_eK8q1cVacn6nU`x?>wiHcZ zOVLEO6is4F(PTD?&L^N~3IRn^2`HLIKv5w9Mbil=nn6HO5dlTT1QeAJP&AW(qFDqK zT|hw5Yyyhr5KuIifT9ZtD4It=(M1FlT}(jHd;*FV5JE-g#r(YvNW7{&EX$Lkz4lGm zm&9V`%M>k+1)sWqP&V}ykjpq4UBQ;3rEDp>k}XBc*iv*ATZ)#mrDz2k zMJov?T17z7)dUo+CZOmV0*bCBplA&NMQaHtT1P<9bp#Y$Pe9QP1Qe|&py);diZ&2X zbQ1wZHxp2_k$|FG2q@Y_K+$Fbif$!@iWbKFj9E_6MmM92q-c|UM7u2(Ghe3Yj#zNw zY$>{v^QCATTZ-;tOVM_=6y431q8)50+R2upd)QL6i!DXF*(kb~fTH^dD7v43qCEr@ zJwQOwg9H>kL_pEQ1Qb0&K+&TF6g@^j(c=UZJwZUxUIL1qB%tUi0*am{py(L_ik>B) z=s5z4o+qH_1wyE3Ys??$fW)7%pN+j;ivFQ1mGQMV}E+^f>`VUl36AB>_cW5m59s0Y%>sQ1mSUMTZC|`i_92?+GaSfe!fSifVDb6xC)+Q607v9mAHQx@;*rmMul~*iuxVEk(z%rKkZLMGXlk zI-Y={69_13L_kqv0*X!~py(t5ikc8m)RcgtW&{*9C!nYW0YxndD9Rwin_9;s2f{~y0fLI2V07IvZbgOTZ($KrKk^Eiu$rqbQ%Fg{Rk*Joq(eL1QZP* zplBcgMS}<^8caaZ5CV#Z5>PaZfTH096pbLD=nMji&Lp5{BmqTd5m0nC0Y&E!P&A5w zqH_r-I*$-4Iwiv&?|{S)8l28jG~I5C@-kxP%M^{x2rgeJMdLVMiVE0LG@dO*6WCHT zku61&*itl^Ek)w3wLIR4W6HqjRfTAJ-ii!y+Dj}d~CILmW2q?OM zfTGz16wM)^Xf6Ro7ZOl3kAR|!2q?OkfTH;X6fGd2=n?{oE+wF7At6+hpW$zFK;l>1 z_ZN+kqU}a%QAW&snW7~b!Apy!=nBr4qNQvpx{@tL%h*zM6T{(fTEiSD7u+| zqKyO;-9kXoCIX5!6Hs(30Y$eFP_%`BqOF8b(PbI_PYy_Yd&I%HT#Dj$@A~$PnE5hA zcVz^Xmq^ie&X=OQ*;2HFEk!%oQgjbnigvN3Xg6Dm?qy5SeQYVZpN*nD1Qb0$K+%H) z6g@;h(Zd83JwiayqXZN^MnKWy1Qb0%K+#?Tik>8(=qUn2C6=pTF7|8hpme3_!xGJ>;~O3~|_FGUB~ zQuGE}ir!>P(OYaOdYdgp@35ulUA7dx$Cje^*(myefTDv06n#iQ(MJRneM~^nCj=CI zNf0*byPpy+!7ihdxV=r93AKN3*% z6CqTzKf}M+0dXJC9Gq9BXt{kN`$$I2e3_!(GJ>0yNzqZxm!jX2`GvZP!teQlukfVjDVsH0*W#TD2fwMltn;M z1pQl$fT9EeMM(mRvI!{4A)u%-0Yy~^D5^?8Q8faJsuMy*zhwANIUwdBU(UTi7q&6c7*Y$@u?mZHlaQ(NF@4h7nLSoPeSc1QeY?K+%~56pbXH=qv(?&L*Jf90H0)5m0n40Y&E# zP?SeN(P#pS@(H1$E}8yd2PEFhZi~7~k!Sa=$7IILmnj;b8O&HMMH4t*iYBt9XcAkB zCbOmJe6|!#VN20ewiHccOHmK+$sq6g^Ks(F+6= zy+}aOJ_3qfBB1DH0*YQCplClKRJ1+QKW?25m59U0Y%>vQ1k-2q@}EKv5?GicTh==oA8qIulTIDgi}Z2%(~5;{MMLNPMo{{M3zykMz&B(KQ}3 zU#6&MJgB-+ih6Or6!m6HQ6IJx^<_)ZX>2L#$Cjeg*;3S>Eky&^QZ$f_qCo@{4JM#y z2mwVy2`CyyK+$jlibfDnbOr%MXA)2}l7OPK2q-$6fTD8ljT(YXW^oku`X9sxz8 z2`I`ZplA#MMPmsl8b=5fb&va<9FVyEO-0cjQgpkGf_Th)nW9PY;G9iTG@0|I=zO*m zO<_yXRJIgNV@pvXTZ*Q$rDz6Qii+4$RLn+E2?0ej2`HLHK+y#R6wM}}Xbu5Ia|tNA zkbt6j1QcCFK+(kn6wN1~XaNC5mk>~NDFHM1tC;4 zA?`15K;lE}=4YZ5ZL&K_OXD%~Wr~)^gN?UJ(F)F&qLpkZTE&*4tJzYtnk_}wu%+l) zwiK;lOVL`k6s=>U=sE(5t|y@A1_FxK6Hs&`0Yw`KD7uM&qMHdQ+DJgrEd&&8BA{q9 z0Y$eGP;?ssMOz3c+Dbst?F1CvK|s-+1Qcx}py)0FinbF%Ma$y;GY&|+g?*y&Dk-XG zkM!@3$IO>0+7%DJ+#*H0IbVwIWlPb0Y$>{*Ek%3SQuF{@iXLQ3(L-!0dYCOmkFZhn zC;>%}5m59v0Yy&`P_&nTq9+L`dWwLerwJ%}hJd1H2`GAwfTHIKD0+c_q8AA$+DAaq zO9T|XOhC~q1QhKjpy*Wsie4k2=ygJ&tAF!q9AX|z)WJ}RUY$^JfEk&QOQS>PRMV}E+^f>`VUl36A zB>_cW5m59s0Y%>sQ1mSUMTZC|`i_92?+GaSfqJZ ziXv<&N@Gir&z7PnTZ#g<6s5DJD8@!n1_4Ex1Qf*yD9R$Br~&~+6$vP+L_kr3fTAP; zMcD)tl;c(Fg*H&LE)ZOah8V5>Rv&0YzsMP;?FfMWYBPI+uW=^9U%)BcNzB0Y&))6pbOE zXeK+$sq6g^Ks(F+6=y+}aOJ_3qfBB1DH z0*YQCplCk-s=9B({hsXEnJ^@oNdN)qiWDg!^eP>ZUKMKy z5SliKD>jP0CZOmW0*byRplB}vMc)xn z^gRJZ`v@rdfqFIGdO*l6h$)iNM4H4*iz)Pr6|gl zqJS+$>1-*Av85=3Ek#w>QWR&Ss44+PnFJJN5m1y(Kv9B#q9g%DIRq5t5>Ql)fTHRI z6xAT0=m-LeY7$UXi-4lq1QZ=fKv5k6is}+jRF8n7`UDg;AfTurAyo8FRsTE(B)-S~ z!v4Qf)Yd&O+9)$-zD&_EnZf2KrKkz#OHos{6g6W@QFFEw9m|%Y7HlbM$(Ev4Y$PXda15m3~dfTBJG6!j&bs2>4E{RyF>qci=N9gz4Fc3adqGkm0Dl#C7|d;0*X!| zplBQcMJE$bbP54QrxH+f8UaP86Hs&p0YwD_6pbgKsE~l72?P{PB%o*#0Yyaw6ip_e zXbJ&EQwb=VMnKVYLa1n9rl0+cQxw=|9Z!%V`v+&DXJ*FCmnkaF4Dz0nqS>4;MRV9v zRKk{`QnnP8v88A(TZ-nfrRXfS6wPN#(E>J#77|c&HUUM82q-#-fTD8=C|XQF(GmiR zmJ(2O9sxzm2q;=kK+y^Uiq0pXXe9wfs|YB%fPkXa1QcCJK+zfkiY_9c=wbqjE+K@9 zW@h?h9FTav-JzZ(MSX3o&5W5ZQ*>EoF!u#1x}5W+=nA$JUCEZB4Qwg8iY-M~v!&=7 zwiIn-OVPD#DY}l0qU#ALx`BYAO#~F(NI=nM0*bZ}P;?UkMK=>rbPEARw-Qiv8v#YP z6Hs&q0Y!HbP;?goMRyZWbPoYV_YzQa9|1-86HxR30YzI0p`uGO{i_|2_}BJGf4vl) zm3qLI88cs|=+VsJ@t36NG0vBw$JtV}jV(n_u%+lpwiG?ZmZGQGQuGX4ik@Xl(Q|AR zJx@T<3j`FsNI=m`1QfkYK+!7%6unA7(Q5=0Z6~1UbpndsAfV_?0*ZDJQ1li7MQ;;O z^bP?)FlEBT`h~JumuEX3TtqHowz^er1jdkHA|j)0=?2`Jh} zK+z8b6#Ym*(S8Do4iHfE69Gj(6HxRE0Y$$OQ1lxCMZXhJ^alY&2MH+plYpYX2q-#4 zK+$0WivA{`=pRC;Xji7+!~uz49XL3jNYUGNTl8;c%zT+5KPxzXyA(yU{_~N3z?PzP zwiLzKQk21#qAF}DinFDtDqD&&*;16nMo~5aMF|3mk^~gx5Kxp$Kv6XUimDS(RD*z` zBM2y}NkCC80*Y!AP;?{#MRf=$s!KpoJpzjA6HwHEfTD&36g48C=qLh;jwXbPB3b?n z2P8hwz5tt+6+T9*=AIXAoE0-)rl?s~aM2r5)SUBmTXZa2idwLxs3lv9TCt_5HCu}E z*izJnEk*fkDQe3`Q9A;P+7nRJfqPkRSHv)>f6HwHHfTH6F zDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*ZI-Y={frL;|lPv#!2PEFy;53z@gZ2gf z6S89F%M=aG3f|cvMZ-8>iiWeLXark|MzW=76kCc$v!!SZTZ+cArRYSq6rIFI(KrH% zP9~t}6atD)C7|du0*X#2py&(&iV6rQ8c#q`Apu1b2q>CJK+z-uii!v*noK~^6atE- z5>PaafTHOH6rD*x(F_8LW)eb0gR}gD4oJL#-4+dzBKtH^bXHc(e3_z>tf2NgQdG+M zQdGv4qPc7-n#Y!+v)EEJpDjfT*iy8REk$RurDzcwMduJubS?o!iwP)NLO{_{0*cNf zplBHZMau~&T0ub3`2-ZLB%o*&0Yw)OP_&wWq6-NqT0=n5MFbRGOhC~k1Qe|$plBTd zMVAsnMYFT~;~bFqA8`j~jubVqyV~osV&=;fU6~aWyeCB)IA4mcVoTB0Y$>{iEkzsI zQgkg_imqcz(e-R8x`8c4o7gD2k$|Gj1Qcx{py(z7if$&L=oSKsZY7}THUf%nC!pvK z0*dY=py)0FitZ+$=pF)!?j@k;J_3sFC!pv70*ba0Q1l=HMGp~B^e`b*ba|G)+yRNd zYM*tyLW(BYz3WG^V&=;fZOaO7`ap`F;Cv~1k}X9~v8Cu~wiG?XmZE3bQuG{Kik@dn z(F<%TdXbHymk20&nSi2K2q=1$fTGt3DB4ay(dz^hy+J_Hn*WIZ0Yx7XQ1meYMY{;0qQ|oQR~?Y}qjvN2xD@TNFNb`R z6*FI^=<}@L`wyk)3(l9KJ!~oZk}XAFv8Cv1wiJECmZERjQnZ&XMc=Wd=zBJb_7PC@ z0|7-p5>T|CfT9Bg6#Ya%(a!`F{X#&|uLKnRMnKW;1Qh*2K+!=0ivA>^=r00_4iQjv zn1G_c2`Ku9fTDj1DDtxPz#K&pLa6AoEI;{?Q}mGC7VVazPwd`xT6WBQnWFUUAb*z> z#W-JzGT2g7g)K#KwiH!mOHn3Uin7>Jl+Bi+1Y3%dY!u}XP?SqRQ8faJsuNIDgMgwV z2q>yaKv69MifR*3bR+>qbqFY`OF&UQ0*dMrP}G2cqJ{(%H6ozsC<2O(CZMP>0Y%3U zP}GDFDvD+TXxKRnW7fi!C9Y5QA^I3qE>7vYR#6SJhl|I zVM|dyTZ-DUrKlZSirTZKr~?~C9SJDvL_kqz0*bm2P}G%xqHY8fbtj;x2LVOL5m3~V zfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P;@*2MFR;aI)Q+qK?D>HCWMNbXZsr+koXw; z3dpfi^tO>2k{vT&rf5WV@WgH@8p-)mG>R=nquEk4hAl;7*-~^OTZ&F%OVK#C6rIeL zqEpx?I+cK;(+DU!oq(b<2q-EbplCb+MTGT{`fTBwY zC|XZI(Pab_T}}uUm1g_R9FTZ@gHt9&JMG@}71=TKWs0uO4o>(=imu^&DcZ=EqHEbw zbRAoYu4hZp4Qwge#FnBP*;2HbEk#?{D7uM&qMHdQx`lwETL~z-jew%t2`IXQfTBAI zD7uS)qPqzwx`%+GdkHAIkAR~42`GAifTFDg6g@~l(L)3jJxoB+BLoyZNL0!I$kA3C)*?a$FpPR%M?A89bEE_6g|!PQuGX4ik@Xl(Q|AmdY&ysFR-QP zMYa^Z#FnC$*;4ch8%3`YQ1luBMcWA|dYyoxHwY+tlYpWf1QfkRK+)R-6um=0(Ypi` zy+=UN`veqyKtRz>0*XE)py(q4iasWwXcqxRpAb;=DFH>F5kf^zWcynkka(`$6?&4} zBKzyJyR&2F%M^W?9lWU zqi8ygKv4q%iW(A7)QEthqX;NEnt-Cl1QZ=ZKv5F{ikcEo z)Qo_l=7dmDEaCTZK;q}wU7?Ib_(=aEBXw*dX1+{O>qJoaqZH+Fz7(}#OHn>sirTWJ zs2y91+Owso16ztZvZbgKTZ%ffQPhQiqOJrKbt9mtI{`&K2q-#^fTErR6!jvYs5b#c zeF!M(OF&US0*d+*P&9ymqT>lD8c0CV2?P`kBA{q60YyUyC>lyY(J(@&sAa-G-vNoA zXkSNbB}FT33{S+&mnj;Z2yQtbMPoQ$ipH{~=tQ;@oy3-+acn6%nJq=9u%+l!wiKPl zmZHfW)WT=dMRdQ6sx8Doe!7mnoW` z2!8lkiWYFb6fI;+(b;S%TEv#3bJ$XJE?bHgv!!SWTZ)#lrRY31ik1;jw48vV6$BKW zPe9R10*Y1zSMXL!Yx{!dPH3Sr0L_pES1QcCDK+#$Piq;WObSVKv>j@~jjDVuc z2`IXPfTAl2DB3^>70pZdxxY9?CH8f+v!v*fz>TXCG4o}Lu1y5(ev_i>IA4mcXG_ry zY$@8rmZBTkQnZ;ZMO)ZXbQ4>OZe~l-Eo>CsNfpOF+?m1Qgv*K+yvP6m2D-=s^OC9wMOVVFHRCA)x3{0*W3Zpy+V|inb9@^aLSP zbWOq^=YYi9+ilTCDT>)gv?miW^JR*jO#}=6kfP@}Uy7b*OVJB#DSDADMK7_X=w-GP zy~38FSJ_hZ8e59Cvr+Uq0Yz^RQ1m7NMLP&6dW(Rfw+SeEhk&AY2`GAxfTH&aDEfea zqMZa3eMmsjM+6joOhC~t0*XE%py*QqiasNtXg2{xpA%5@1tC=Qbi%*R0f~3Fhh@)5 z(ILAn+LMTxFH`hQB6#XgDf*W4rD!i(ioRn@(f4dA+Q*inAJ|g#BU_60v!&<&TZ(>S zqv&S>ihd!W=vM-Yej}jhcLIw3AfV_V0Y!fjQ1ll8MTZC|I!r*(-vku>LqO5L1QdBm zJ#0r&gn*(n0*ZVBilPJ*1q2kO6HpW*go?gO_+L68@m2=sYbiQxUk=Gg#>|%~%1j2q zVJXVud@0IiOHqO?MM<_4<*=nFmn}ur*iuxTEk!lhQgj3xMKuX1szpFiZ32ppB%r7c z0Y!BQD5^(5QGEi68W2#_kbt5_1QZ=bK+(|z6g4KG=okWunh;Rblz^gU1QazVpy*fv zidqm*)RGV?iYNVJ9gujD!Ks=IAL&13AKqFeW9G{gdcm+E^I04%9f&TY!r1Tpr{7{MaL0P)RTasUIY~NCZMPf0Y!ZYDC$Q* zQGWu81`tqmJOM=m2`D;&fTBSJ6b&YzXb1sCLkTDvMnKVU0*XcuP&ASdD#}axvmKE5 zr*`kUjT9}n8>UgonE5hACnke+p1p!LUi2i+m!ffODLR=gMW?W(=v1~8oyL};)7esV z23v{>*itl}jiN#ViY5?HG?9R!Ndy!X5l}RlfTAe`6ip?dXc_@U(+Ma#lYpWb1Qg9A zplB8WMa2XZ%_g8|4gp0a1QeALP*g@h(Od$G<`F_gW0L+u4oJL*ed%nh6lK{X{j-uW z^JR+8P6i*ONzo$Cm!fmnQgkj`iWak_XbD@2ma?VjJhl`qV@uI;wiK;kqv(7BidGU( zw2FYD3kWD$O+e9w1Qe|ypy(n3iY_Lg=n?{o))G*(j)0;|2`E}mK+$Cc6kSe0(G>&~ zT}eRE1_Fw%BB1DM0*bC7go+j<{lgAOe2{(adZ838u-l@I$(Z>vMK>gadhVZtNZl4~ z;(RH(ku61=*;2HHEk!r6rRZk16y3s>qFdQgbQ@cWZfB$D4g!kqB%tUn0*dY?py(a~ zitZ(#=sp69?kAw=0RoD)5>WIY0YwiHQ1mbXMUN0r^e6#Ej}cJxH~~f52q=1jfTAY} zD0+&3qNfR=qU(}=9|t5}%Wi(Im!h8b*F>I4#>|%~dLbE1j7iapoG(Q$v8Cu`wiLa> zmZDeLQuG>Iing<*=ykRfy}_2EH`yrKK|s-41QfkZK+!t{6unD8(R&0Gy-z^V2Lu%D zB%tU+0*XE&py*=)igpoD^a%k)pAt~?839GR2`KuUfTAx5DB43n(U$}ieMJZrJ(u)X zIUw=sc3bqk6m7P9*Iy@N=F1d)mke&JB1PYGz7*|aOVJN(Df*EuMf=%Obbu{IKe46g zXSNjm!j__6*(myrfTG_CDEfndqJsn!{YgO4Uj!5#BB1Cn0Y!fkQ1lN0MgI~|uEpeUVyq8I^183YtnA)qKu2o-&s^xtqm;>B)8_e#;XsRwL1 zG4o}L5;?*Cs#28Xd@0IdOHnRcimI`ts5)DUYOtl~2(}c}WJ^&kwiMN7qv%Kiis}$h zRF{CFdIS{JC!nYS0Ywc7C~8DN(NP2x9Zf({V*-kfA)u%U0Yyy-C~8JPQF8){jwPU| z1p!4Z2`FksKv8P~it-4dqO2UhdZttKihb5GJ12akzrk*c+T_H{mnmwW6LiRyq7Ixd zMIG5v)QK%co!L^cZJ$XQM%o`9-9+0U#95foZ#%F6rIBPQgkX?icVuo(dld{I)g1m z1#BrA&z7P>wiHcZOVLC&iY5_IR7610WCDt&5KuIgfTC#x6ip|f=u85NW)M&`lYpXG z1QZn$P&Au>qB#TqFdQgbQ@cWZf8r;9c(GOlPyJeu~Bq40Y&!^P;@T=MfVX< zbUy(_4-inam4KoL2`GAqfTD*9D0+l|qDKiRdW?Xg#|bFfMnKUM1Qb0uf1{gDpjGvZZJTTZ-OdOVQhG6um=0(Ypi`y+=UN`veqyKtRz>0*XE)py(q4 ziasWwXcqxRpAb;=DFH>F5m2<7fTGU{DEfkcqCEr@eMvykR|FJ&O+e8%1QdNs2o=4U z45qpV(6LGh2#&VN21k zY$^JUEk(bxrRWbfiVhM`^d|vDe-Ti0h=8KQ1Qh*EK+!)06#Yv;k(aB7?I?;6P?SbM zkxxKTlz^gufTDB)iedy5We`wQg@B?s0Yy~_D9R+DD2os(`aZ{h!~u!lW4A^7r09@+ zQ7t<+X1+{OZf@{l9Vx2D`BGG!Ek!lhQgj4cifXc@s1{p_YO|&2NVXK!VM|e6Hj3&I zP*k6Qq6P#MH6);@5dlR<5m0nA0Y!}oC_09Kq9z0sH6@^^839Gj2`D<2fT9)z6tyIv zs1*T4tqCZ~BcP}a0Y&))6tyLUijukhKMqK|h5f~}oZRq{{tAaD+AcR{zD!Z4+@L{y zDeBDmQq+YlMP1oa)Qv4g-PuyqgDpkJv8AXdTZ($IrKmR>MSTb;>PtXTKLU#S6HqjO zfTH6GC>lsW(Fp_;4I-duFabqF2q+p#K+!M)iiQ(VG=hMlkpvWtBA{qA0Yzg7C>l#Z z(TM~UokR!~b;$MmIUw;C2B)JG9kAP?ak(+`Wr|MA4T{`PBu;%D?R3tUqBGc1RKS*^ z@oXt7WJ}QmwiHcdOVK2@6cw?hXfhi`QwS)UNECPy( z2`HLPK+zlmib@D5DkY$(jDVuK1Qg99py(_Dislngw19x3g#;9xO+e8iLa6AJTz|C# z5+7!8PL-l&_KmXVXjts$W3A_9soCZOmN0*clWP_&MKqDu)VT2DaHWdsymPC(HW1QcCKK+y&Q zimoD{=xPFrt|6dkBLPL%5>Rv<0Y%pnP;>(UMVknrqQ$xX4hJOuwVTl;QncU3jkz)N zX%g`gx419adWlyIT;hB8Y08X5mU}dpnXn(Do=l9)^1SMa%M+egEAerT z=haO#s_uCW6H|`xyvB*UYI$C>#4ksBUdu$6dY;!NvABWfwNJdz$n!cUsy6n#?un62 zJg-;c%4VL|FY(E-o;NUYbSuvrl9-m~c_R|{a>f$l55?;hN!m{}>laDdkEI$IN!rg98WKtFecD|ok)-`(k1>&? z{b+`9k)-|G`lm&b_K%~Fk0kA1x1JP9+CNV`HIlS{Uv@?$Y5zdz>`2o7g~zf;(*B9Q z`H`gk8*7UqN&82#mPC^FuN*CpB%j#ruAxZM{+*FEk)-`Y5o;q!`%eGMB1!vJ?G2Hn zeXs4tNYcJp@`gy#zT0g}Bx&ESbZaDO-*0kfBx&C;aBn1Of8%>=Bx!$T_mN1_{?6sL zNYeh&+|!Yy{jI0xBT4&fD=$Zq_V*69N0Ro1;~kNtedX`nNYcJ^von&k&%N)8B<+)@ zyCX^a?AMo(q<#A0+ep$Lf9{JU?E%DrNYd^B{u)Wzhwy`uq}>J|j(9oC-5;9hmhg{U zZk~H65^3j(dzZWaA{(nkt#rt~#8Ne<&Wm)^xW&C#q?5)%-;K`M%Th0Pq5HEJ>7wT} zwHNEEG1y*PH;qv?x-%kf^w8Mn{!mAb(-;AXy9B+$;hxHg9FtwGs-Imadu+`d zr^55n8hcf%9_Nzh`A2wucGs%is&=V*LN)iB)N?XCFX-S|Nv{^ES~Yxuh?}u2&(GlH zt5(gbnpw58`<-Oe{EwHa;$EuKYmI9L;Tx%{SLvp`%1ph=)N?CdWtLv0UMkz26jWS} zM3%dB_Lh^WCj!sQ(eFfWB)4^>XKgM-)7m+a-1J_xuIy9WT|@0FUAVgLRd{vXe|8h; ze*dZe+yCsUt^BL<{?NU!?~Qc-Pm3JN&hjGemwQ>ec3QX2D=EyITsk|iv}9slNkQqv zqJr5a#brek%ZeuDO)Ob3yR6v4#G*-aONvS>Jyqn*(K9vPAi)>ugJ@rT0FBT zuW&}u{JhpPiYFG%$Sa*%SW=W%QZ%cmw6HX+jB&r0DI;dgEiD+;yW`Lf{})%&yuz{~dvAGOctua1J8NRw zHXT||GztZiiY6D%ol#a$wqSNqY3r#b%w1iRrp+pI!`&2&?%Th>UCfDni)YR(p5>b1 zbGKzdilW~x5(L%$w_icE^hgl#r?d{L`L!DcL3$ha(LPcmsA`8q(9jOlE7|>>*XUF``Z3Y%h2%qfOzWm7! zeaoNh*jX>xzB8>iC%0)IKCgdYy-dD);b}vPi)ZJ1Lwk=a=sRpo+wgVw8Yp?lA#-dtZ@uKWSK7WV|d&Hm-T zk9>DwQZL`dy;wnkJG))mg77uuyEn!O19)w{_1gMWyax9ka4$A#?#!7B!q=piZOf4bQd{%H@epnK2hl+bmCO^&PzShy<>G=hw@kE zE)Q?CtzN!e#pUQ*enx&@-juuGI>Q81x}o~N`s3NJXu{kn;qS)1|J~bif8r}$0lFOR zD=wP5vcnfI|Gl89O~r4eOZmmlcVNB2{ZB6F-EUOtJa;|ncjUb4seb=)rZ=N_)|7^+ z|NReB`4tzWkJzBgU1zB`0H<;=Ay4~r)<1Rjbo--`deJs|6;7%yNuTn|WPc`8FVwr@ z!u8{dZ>Q&#OW=*?cP@Wb`4!l}fsOnMeeQRmH;st$>)!qGPhEig3QGCTQrOz?%nDuk z1Gs7`P;qU!-$ZyGPuSIxy6LI7YTd1oE=s<;EIgTC@gAvk1$WZvTnV8adxf1V-d*mU z8NQ9Sys?TaKfmJI&#!d#yK5*srQ(X_ddTmi-#gbrm-5T&-oLuI6*o#;MI9ugD$C-%(0jZSKZI&uUlxE_Ck*UcBOp=Q`yo zEx#H&yZ2vlIo68ngd2Rjnb50q=kSW1!0=t@-fZd#_nzQ+tR#FN<%b7-q^q!zUxB0CV}%L#LDapq(y7HI zW#u2Y96c^mNTB@MFaHSZ{?Mde#IB)~C-=SypQr?)0ziI+fcy#qTtE5l!lq7kAA(ay z-v9YdbNE^-UA-08rhDUhPvyHi4dDyAKdpMA{2iJfUe|UpE8Q&T>kM}tSG>F3Q^yY* z+puq!E)DH|YwP@mcF(m<=eF$|HY+KbQB+u3)VyJ(HuncB@JG9bG9bnK-qFyB|ESbE}!HXS#dR zEhd%DZZUaw!&Xxowi@2HVJmmnt;a-n0a{I-SyWnDIHjo7jG|dn%BJ>c<5GAJqm^Cj zZkdL%X~nZzmAbp2?pW&Dq{6bo@*Tb_+(+r~i3-5^6@m@t|MsyaL|W{6%;3jXsWG4~ZK?kd8@?%WI? zFuMFBY(Do4EAHi0+_|f`Z|CkM!YBMwU>DCE|6e|~(nGU~d+e$A0e3np?hjVFJIH;` ziu->2X|ub7;d@=m!~1=yS7~=Pb^kNfR^0!q zxckSSm~u|#_b$utHkRK*tn^2-;tyEG{X6tj+`B7R5#B}gj_=#IYr|&thp~6b%!d7E zPAHl*$=$Uc!{g7?pHCiFHvixMw7Q4=?$OS_?pMT1Ta@iS2T-fhqiuVz-8VbBJTmfm z_c;pB>)pluuh1U1dXYT$WYD?Q(AGnHpD@fz&xsAK;>R;`qtzodA~pS5k=l_XBXuHm zBlXjcinO+e<^T1oa*BFC{ag9jzCCcO^vl<$1xUU*JbxS^I=nntj^Xj_y;&_WQPD4ISNQR=hO# z*_1|hbT8CQ-L5ZtIro|0)X{yuH+Afz;|Lwc>gXO#r=CAuNB3FT)LyLPavj&|xLL>h z?9(ys?L495JMOn;`!gMXbH4%G5%(^)V@>yavE$J?c5#>8c7GjDbx+%#qT>zjU1|F+ z9lv((0NcOl*wS6`w!7$9;y!(Dd$Ep>IN-Kl(D9!m!(Fvbc$67Fd_-sr9Xd-;2G{Px&z|E6Q>R^jfZW0||6?B$p0_*j0p zU((S~+w-$@9N?}{+oN?{<3QQIO2@amhWj%eYq=}lo_~yvXY>sBnL2Li9q#*d{H|}f z|Io3`fN=NFao)giFVk_`pm4vUW7^PgCv+S*Jltb-ym(}|uhH?{(c%7F$0JV+cT*k5 zj|=xq9dAA*+z;ru@3e6LsbkxMaQD=4eqp#*==h|AZtsuRbc{|8caDyOriS|@9oJ3| z_q95{KO@|GbgWw(?&dm9m=o?|9d9iS_k%kAI5*sfbZkFA+`V;NxG>x+b$ohJxL?;X zeQ~&}={RI*xKGyc(q-YkUdNp)!u^$w^;df$6;58`&1n-+ZgUmI)3E7B4gLjH##=l6z*0!PTm~u zQXTKSDcq0h`138{{#VD&w}-pGj_2MP?hAE%{_b$UrDOcQaM#pv!~@|zUB@dP4EJUo zcRd{Ly*eKCSh(|aoVqRCb9KD?$#6feo{tAxC?aL@J6_A((%(B;r?F7#_xnXU&rb1h5IZW@BJX$Pw4pjhvD`=3Xk1) zg~tol%UgDS@Jo0+?ziwbSjXjmgnONiul^bC4|Gf(4tG5rPy8p`6Ls9^ zKC0X6zfH$4+*ikJ@7J-J`_!`S4m!?qUoW$LwvJof7tU-yqvK!hD`>W3?ps*w*vow> z&5lELJl}my&Gvd7x4SQ{+5S++T=!Kr+YNLa=f2!#yGY0D+}GV~-=X7|?hA0Xf70<- z_mw!?ophYtFx=lYBoIU?J9qYQUblYyOV;egLp4Ux#ppIj8oSK*uX| z+^plhIzFM}t2(CJ{f`Xyg(y3^w`afX=D%$EiH!9>JD*t?ePB*Lp%}sn^;<>;L>zLu>cIxAi3ZEUEj{^yFgq;;E+#Crl_Q zn&(w|ZedB`tSLqAl~kPYKg$gJLXTdByA)pQiSDZsMeY;kmCl-6QaIDSQ14MgTNjp< zl}wv3x6HlT|F6H?-5e(~ydP=jxVsVm@yorNQokCx|J%#?;rt&jXV0@=P2GR)-Twdj zaxLA<{P)}K>>9u9da_^r+<&}o+cVsMJKc56FP`e)TrC^~K%uczr9~)0|_k<4X7XKHB_I~dH4G4 za@pm}bpP@C*1Mnk$Ji74#p|L<^+%(DeHJAx8hgvVh@b9W+;3T} zw>`bVy=lKq^)c@0;1WAOlD^r!vGi!PNnn2|DrW!kQd9kH`UY<1d(mc^_1$diMVo8Z zbF-cM*SciB2>CvCe6*GW5J+g-ZO z+S#_<#p|M-W!qi8uG*Pyw{@4Vn|4*(?(%ilj@x#ZuZMOO+wSrmr=4NjUA~^$G28C) z_0mqa?Ji$$?ZCFXe0{W|w%z6HtL;9A(x;UN&S8BD)~-E^!S+FPMDCvf&GQKl#n4hRYHbpO2{xx2^p>_AtN*;WTd8q zjM9{l(V7x6MpHt@Y9i!BZG@bpjgWEL2sv3BA*W~~)8ri7fODIxPUC1io7 zge=rV$l2NmS)`4SbF>k1t~NpzYa?WdHbRzaBjh}7ge=oW$Z~Cjtk6ct`Pv9ssg00T z+6cKo8zHN;5ptn6Le^*_l#nZQs)SsrDIps)CFCki3AtKRLax!2kd2xWa;>I>T&F1^*J~o=25p3F z(niRQ+6dXKjgT$c2)RicAvbFy9e+6cKz8zFaVBjg@! zgxsr*ko&X|a=$i09?(X}R&9hls2vJf@8`Mezsi|*8**7FUe!j(YuX6eu8ok_wGr}$HbUOiM#v6rguJDVkhirF@{Tq_-ql9Pd)f$jUmGDG zXd`5&HbOqsM#x9np^!)Xk?#7h@{8T~cr+B!*6x#h95Xp4v3f__TKZk;M2pKD6U z7n%~XM^i$+)Rd5~G$rI~O$qr%Q$oJgl#soe2>DJMA>V5wWS=%de$Yn9kJ<>?uZ@rc z+6ehc8zDbyBjgutg#4$`M-@ZCa36ZmeS#smi>D;iCU_>Vat@lAI3#E*oE zKC=5Q$3$Yr%M>+_1orJeDMiO}z7(}!OHoU<6t!YYQERpo<*}ux4O@!x*;3S&Ek*6v zC~8kYQ3nEwIucOSiGZTc1Qc~4pr|VWMcoJ}>P|pW4+4sgBcP}!0Y$wCDC$i>Q6B<| z`VvsokAR~71QZP*py+r4iUtx;bOIq%)HLF|zcJv&7uroxGb!3;qy|M|=F1cfiv*3_ zr@&H*hI76YjbKaBNVXJ>VoT9zwiJzFOVL=i6rISHqLbKCG>(m;lL;s~g@B?{2`D;^ zfTGh0C_00Hq5=Yn#uHFfNI=m90*WRQP&A2vq9Ou{CKFIJg@B@|1QbmpplCV)MQ0LF zG=qSmnFJKgB7};DMEn5`NPMfC(VMf2EF zbQW8R=Ch?}0b7a|vZd&3wiGR5OVK%O6rD>z(P9FMmJm?1lz^i12q;=cK+$pnidGO% zbUpz^D+wrCML^L71Qe|%py)yZiq;TNbP)kX7ZXr)2?0fG2`E}eK+&ZH6s;$OisnT8 zH4aF8x_hJ@Es>(tsmEE7nE5hA8zO;y`)W$jRh%zHSF@$)8nzT|WJ}StY$>{qEk)O} zrRWB>6m4Ql(T!{rZ6=^-3jswp5m0n90Y$eEP;@H+MYj=9bUOh>cMwo?Cjmuw5m0nD z0Y&!^P;@T=MfVXi( z2M8$oiGZS?2`Ku7fTCXsDEf_nqTdN9`h$R?g9H@)NkGwG1QZ=2py)6GMSl}e^bY|= z{}NE-rIkO*&rE$iDndX}8X;7)JK~?=fW#lQzdQ1|6g_9RMSfb$e3_zHT44YDLP}8v z=Sxu)wiLzLQdE^KMVV|V%3@1VHd~4kY$-~zr6`AuqFe%ssu56Boq(bm1QZ=XKv7Ks zifR#1RGWaJBMB&~LqJho0*dMpP*k6Qq6P#MH6);@5dlR<5m0nA0Y!}oC_09~ZBY{f zikcEaMM0Xs#Q}-Wa9=r(rl*CE^k1~wqGo9^^JR)!rUmxTccc`x;(RG;&6c7(wiLBt zOHn>sirTWJs2y91+Owso16ztZvQgBDfTGR>6m=n>s4D?Q-3Tb^PC!u)0*a0!pr|JS zMZE|p>PV8SfTI2c6b&Gt=y(E(1`<$o0s%#X2q+p%K+zCFsOZ=<|2qdH z9(R8)C)z@ae0!unG%aSnOwq`+!2bD{l%i3bFGZu-QZ$AwMPu1gbRt`dPGU>ZIJOj> z%$A~4*iv*V8%3uPP;@#0MQ0FDR6sz{cmj$F2`HLCK+!}3iY5_IR7610WCDt&5KuIg zfTC#x6ip|f=u85NW)M&`lYpXG1QZn$P&Au>qB(?6(eO0CjRO)t)ozPMNKrrgh*pvo zGhe1?URq%Pd{9c!S)4CL^Vw3gfGtG}*-~^iTZ$I3rRW^C6rIbKqQz_}TEa%rQUZ$3 zBcNy*0Y%FRC|W^4(fI@vtt6mm6#+#T5Ky$5fT9ZtC|W~6(M1FlT}(jHB?J_$C7@^> z0Y#S*P_&+aqRR*~DY~95MK`deXcJqCZe&Z*X0{Yy)2AL(zi+oBeJ z%zT-mJU_61elw-04d+WyK3j^~vZbgUTZ-DVrKkg2iaN5Ts1sX?IlgS z(O?3Kh7eFRlz^gP1QZP?go;}E{<{uHe4^bIYAr=y+ilSZKW4s6(HK9lf4()PXe{ST z(TQv+I*BbsCJK+z-u zii!v*noK~^6atE-5>PaafTHOH6rD*x(F_8LW)e^|i-4kH0*Yo6P&9{tq7nj%N(m?` zBZP`Z`TmjZoubd(-&u@~mZE3u6WMe9nE5hA3;e+T`QMbHg`6)%XS1bf5nGDRVN21u zY$;mImZBwWDO$>wqVw2Nw2Y0SA)x3Y z0*Wpspy(0;iq;ZPw2pwHO9?1iPe9RS1QcCPK+zQh6kSO`(FOvFt|Ekr&hq{74oJMM z-4@N4qI~;^cC{ZfU#93fKd^s3I;H4(&X=Ma*iy8KEk!r7rD!u-ing$&=q9!l-OQGv zTi8-`D;q_(5m0nH0Y!HZP;@5&MRyTUbTIe||ir=y}eUq8Hdw^deh|USdnp%WNrng)K#|vZd%XwiIn=OVR6W6um(}(VGMm z?I57&Edq+(CZOmY0*c-xpy)jUiry!n=mP?Zb`ntZApu1n5m59o0Y$qADEfqeqE87Z z`iy|0-2@bUPC(HY1QhKdgo>W={e2Edyu?21_$-R-w&+VgX1+|(w|-#%e0@sMUe1@I z@7PlGJzI+Qv8Ct-wiNxymZJS^DLTNGqMz7O^fMbpzYtLLD*;8n5m59y0Y!fhP;`)h zqCW{J`ip>~Lj)8ZCZOnV0*d}2py*!$ioB>EwxcLQKv5b2MLq#VQ38qr0*cZJD2fqK zltBm;eeL^g9guiS`*ig;QgpW6yRH(AnJ-h66%FjiAEXpzbG{TM*iw{aOHmG6igMXf zRE;e~)!9;1gDpizu%)Ob8%4DUD5_0B(UAlc)ghp$E&)aL2q>ygKv4q%iW(A7)QEth zqX;NEnt-Cl1QZ=ZKv5F{ikcEo)Qo_l<^&WSOF&Tz0*YD^P}GVLDykaw=Q|*A`{(YX znbGi({ylc@x^*;WzD!ZuXmC|;DQd_0Qq-O;MIG2u)R8Sko!C;;nJqPXda15m3~dfTBJG6!j&bs2>4E{Rt=lXP(MSS{MiD|qZKD2@4oG~No6&qJ+GV#zqoXnNWr|LU z2KM7uQny9pIA4lRW=qj2Y$-aGEk&oXrRa3F6rI7Aq5`%Qjb}?yAsa;#2q>CJK+z-u zii!v*noK~^6atE-5>PaafTHOH6rD*x(F_8LW)e^|i-4kH0*Yo6P&9{tq7nj%N(m?` zBcNz50Y&o&C_0M}DjFO0qy3zs{`M7+6Q$@TyDgd@jhQb~v?v&0*WprplCe-MVAp!bU6V_bn2q?OWfTF7jD7uD#qK$-5 z(ZZ-d$N`BTwufbBOVMuoYa-W1W9G{gZHfl=>ei7iDpv!&=3 zwiMmUmZIC(Qgl08itb>e=uQHP?joS*ZUTz#A)x490*dYq8Foq{rIqyqL(;die6?*(JO2zdX+6jud$_QJ6nogXG_r=Y$c8)R#Lu%2VlPP1I(wx5O*Ce{ zOwsqzz<&H(O3^;fm!cooQuHHRiuSXm=m1-aequ|}&ul6Bg)K$DvZd%ZHi~{Hpy&?* ziVhM`^d|vDe-Ti0h=8KQ1Qh*EK+!)06#Yv;kr(J;JBlI%6r~YRuEpeUVy zq8I^183YtnA)qKuKv7jfsAzB0uRGK!I@`XJ=sPL;&OV}L1~KzxijqNKKfW-fD2MZ< zD3>io)!0&0oh?N**iv)^TZ(G3rKlELifXf^=twq->JU&=mw=*r1QgXLpr`=>MGXlk zYD7TMQ3MnnO+Zm&0*a0ypr{D}MNJ7PYDPd&a{`KvC7`GU0YxndC~8GOQELK<@(3tu zLkJaR2mS;HB!18y=_i8lk$%42Fy#j^^JR)U1cCkd%ao#yoG(S4*izJ)Ek#|}Qq+|# zMcvp^)SWFwJ=juo99xQdvQgBFfTG?66!jsXs4oFU{Rk-PPe9QC0*a0&plBcgMJEtY zG>Cwr!2}cyA)sg|0Y$?IC>l;c(Fg*HMiNjoih!cg1Qd-SplB>1RMal;Z*@T8_3h@T zy%b$z(E*8HV|Rs4Mv>hXogKu?mnm8t1oq>1 zQ;L>wz7#EGOVN33DO$#sqUCHUTEUj0^Vw3gk}XB6*iv)>8%3)LD7uhxLO{`40*clVP;@B)Me7MDx{QFL%LypDf`Fnc2`Jh?K+#nM6kSa~(KQ4VZ6u)R zS^|o$BcSMdLa6ARz;Ew>#K+mgvU8>Ab-OLPA&8kTQ?w-r?8i5!6y3!6Qgkz0if&;` z(XDJLx{WPGx3i__4z?8C$(EwK*iv*i8%6gJP;@T=MfVXX zEJaQ2BieUC%zT-mAA`Vte0)mLe$JPo18gb!i7iDxv!&=4wiNx!mZIO-QuI4pivD0r z(Lpwf{v@F2F9M1V5m0oPfTF(%DEfzhqJIe}^3wIN9YqlWiqZ%u@(C!45>ONnP?SzU zQH+413<8R(5Kt5+pr|SVMVSN?Wf4%6O$Zh33;gucog(|XYxD;x`ph2oC(>i)%M?{h z51JN8QFYFjq8e-|I)W`lHQ7>Bi!DX9*-~^QTZ-zirKm1jit4dZRG)yN1_Tr}B%r7f z0YygplApIMMDWF8b(0TZ~}@(5KuIdfTB?Z6pbdJXbb^GV+klak$|F;2q+py2o-fq z_b+uo;xF0#qE1reeu}$$z?L2}U#95v^x%PsQgjCAOHlz^ipI00sE{p16WCHTku61& z*iux)mZHgQDVoAY(NqG8rV&syoq(b<2`HLDK+#MBie?c|R7^n8Yyyhr5KvS?Kv5|H zMP&pO%_X2{9sxyX5l}RrfT9Hi6fGp6=xhRt77jtFGb7QQnZ3CMd!1nXeC>URT|BfTGI?D7u`0qALg}x{`pR4FnWjML^Nj1QcCEK+#45 zimoM~=sE(5t|y@A1_FvU5m0m^Ayl*^-LF5{DQaMMsFzC7_|yZo^qBcFMYp5}J*P_1 zt(-4Kx3Q(@cD5AV!Iq*s*-~^DTZ-;xOVK@SDY};}Mfb5$bUy(_4-inam4KoL2`GAq zfTD*9D0+l|qDKiRdW?Xg#|bFfMnKUM1Qb06R&qmP)1QhKgpy)#aiasKs=wkwkb`enY2?0f)5>WIR z0Y$qBDEgd$qAv(2+CxCmmjo1jML^Nl1QdNkK+(4Z6zwIT=sN<6z9*n)A0brqYPx^B z0}_AGKBB!QMLq0c{}1Ug^JR*DN)KL}Aw@rPz7+k!mZD$TQuG^JihgHH(I0FnI>?ry zKiN|B7h8%Bu~BrGfTF(%DEfzhqJIe}@?v_}j-m(wMQH>S`2-Y22`CB(C`u=wC`Le0 z1_4D?2q=mZP*jzGqD%scvIr>3CZH%mKv9x_q8vh~Xn(qYzyXPGx0{~>QncT9BR3W^ zU#94YSdddJMKw8JifXZ?s5V=Qj$}(w9kvwJWlK>#wiMN8OHl*16g6a{s1X50M-fnT zGyz482`D;-fTAV@6g4HFs2Kr8%?T(vmVlxb1QfL-pr{oAMXd=a$|Int4FN^@1QfL; zpr{=IMePYF>OeqIM?$Emdd%ExqVcid+EOVh zAKsS6V&=;ft%wDC+z*jWeFfxv&X=NaMHjNAXboG6E@Dg3#cV0M zgpH!L1Qe|!py*Npiq;cQbQu9fmlIHQ1p!4@5>T{(fTF7iD7u<}qH72!+DJgrwFDGh zM?lf_1QgvsK+z@wif$yJXfpvtTL>t+i4ZDU7V|UaIYpb?j4qd=&Gr%P=2*;pnWEcc zLG$@ibO+~4(Vc85x{EDEceADF9<~(S%a)@1*iv*qTZ$fFOVL&~iXJ4O=ph1%9wwmZ z5dw-HC7|dr0*W3dplBNbMNbe=^dtdAPZ3b`Gyz4=5K#0i0Y%RdQ1mWIR0Y$qB zDEgd$qAv(2+CxCmmjo1jML^Nl1QdNkK+(4Z6zwIT=sN<6z9*n)9|1)_5K#0Z0Y&=> zp`zDg{$&nGe5lyT zKvA54qN)TGWfD-7MLQMS}?_8bUzP zPy&jE5l}RofT9ru6pbXHXcPfOqX{S)LqO430*X!~py(t5ipCL8bTR=&rw~wdDgi~O z5m0nG0YzsJLPgy({K*bTyqm%4Aw{$8wx}Q@X1+|(#Ef9&GAWwG`BGHGmZHgQDVoBT zqN!{tn#Pu*>1-)FlPyIv*itl;jiOlu6crOtG@F2;IRq4y5KvS~Kv5Y1MRN%#nnys< zSp*c#C!lBn0YwW5C_0;fqD2H0okKv;xdap~CZK2u0Yys*C_0aTqGg0oQDKIErvnn- zZ=ZFXAVpP;)bfm&`7%YTGJ@AvNYMqHFGZ`_Qgk6(iq^2D=pwchUCfrEOW0DhmMul= z*iv*U8%660D7uV*qRR;=x`KeBD+wstKtRz|1QcCOK+!b>6m2A+=vo4bt|Or6dIE}W zAfRXy0Yx_wP_&tVqAdgz-9$jq%>)$PLO{{2giz7>8UD`>Nc`@IgR@eK;&$))wv3qh zGDUY~1l3ka(cPRcMfb3!=w7xI-N%-q``J?T09%T-vZd%jwiG?YmZFE*D0+l|qDKiR zdW?Xg#|bFfMnKUM1Qb0yuDf%NLxPFZk9pro|`jah1f3c7wiNxtmZE>zQsh<9<8~>Euu+soK#@;CQIvq9fPkWO0*Yb;6lD-lRE2<|H~~df z2`I`WpeT!gqHF?+5(E?_2`I`TpeUDsqG|*b{XfLrcXU*B-?sfd*|QlkDKiPZ3W5|V zN$6F25kb15pdmnL0)ZqTAPNe0R1_6dEQkvBhKh=cT@e)(d&AyPQ9-dkzwhkxNOE2G zd$0HX<5}xvE!{bfWG6%B!(=8Qp(X)EwFoGxO+Zl{La69qb^jR$Bz}_Jq5f5h4%lr` z-Sn9GGDQv3gD)8twiGpIOVJT*DQdw+QA+}f zS`kpxnt-As2`FkqKv7!)irNuS)SiH%JOYaH2`DNcpr``@MI8w!>O??MX99}45Kz>W zfTC^$6m=({s0RT>Jqal4MFv8Cu3Hj0K5P&9&oqGJgt8c9IWC<2N` z6HqjUfTFPk6pbUGXgmQ$#}QC;JOM=$2q-#%fT9x#D4Iw>(If(jP9mV_WCDr`2`HLO zKv5APRMaQkALW3=2ia{=Un%nJ-u0C9nE5hA)6;_mYo%xg=S$H{wiL}`OVMn$6rIAB zqB(3Sn#-1=d2A^vVN20`Hi{MyP*h4lQ5gY68^Sp*cVB%o*&0YzsMP;?Fu>X$qnE5hA z_oN4ZualyCIbVwIV@uKfY$@8xmZAsPQuH8OiXLK1(KfaeJH+=mi3bUL>GsCjmt-5m2;? zfTEWPD0+o}qE`th+D!-*-IeYizTPQXX`g7kTZ%FQH(pDRnJ-iHW_mE-YAJe)^QGu* zwiLa?mZEprQuH2Mir!~S(FbfP`j9O}AF-wAV>XKR5>WIB0Y#q@Q1lrAMV}K;^aTM$ zUlLIC6#+$G6HxRG0Y%>uQ1l%EMf(US`ksKI9|$P=k$|H81Qh*5K+(?x6#YU#(E$RA z4iZ8|Z>0M(9gz4sdvL!;ik`AB&HkDmGhe3YkM!XD4N~+c=S$IFY$^JiEk*yZrRZO_ z6nSwya+jhATZ+=yQslFxD9T1rKtNG70*Yb;6jdjnD4l?!H~~c&1QcZwP?SYLQ8ocZ z2?C0e1Qg{EP?SqRQ4Io$Y7$UXi-4lq1QgXFpr|eZMfC_Ms!s?N9ZL7_azNs(?S9ek zQgo`_7Bz^+%$F%TEFQdiofI|Ud?{+mmZHPiQq+tsMa|h#bOc+9TCk<4C0mMGv8AXr z8%0MFP}GKiqP7GSwIiUYJpn~|1Qg{HP*gxbQ3nEwIucOSiGZTc1Qc~4pr|VWMcoJ} z>P|pW4+4sM5>V8OfTG?66dgrCQ6EC6s8QTM;DE&6wws^E@$ixULpJ)xW9G{g4U7l1 zHcHVT&X=OWY$+PTmZG6-DLR@hMZ?%qbPQXHhO?z;1Y3%ZWus^$0Y#$-C>l*b(HH`X z#u898j)0=^1QZ=dK+*986ipzY=mY|aP9&gcA^}B{2q-#%%I_^K`fW-6c6O9*1Q4@Qle|J1) zzD&{m@!+e?QnZ!xrRV{+6g|k6qKDX0w2duA53{A{5w;XP%9f(-Y$K+$sq6g^Ks(F+6=y+}aOP6CQvBA{p&0YxtpQ1l7` zMXwT2w3~pU*9a(joq(b@2%(~T<9_BAr|1uZbDtC)Og&(W$IO>0dM6&VyG@GT<$Ni6 zk1a*-v!&<*wiJEHmZFc?QuHxfiuSUl=o7XSeac4BX9N^|PC(HY1QdNqK+#tO6n#xV z(KiGXeM>;mcLWseBcSMe0*Zbhpy)>eiuMyw^b-L^KNC>&3jsw32q-#8K+&%R6#Yg( z(IG;p=&iUv#sP^Bv=3r$OVKF%@b-H=X1+|(-|?XA4k`MF^QGutwiJ08dgLxe5w;Yi zv8BjoOHq_9MFCrisQl+fTH>Y6g42As38GGjR>KlKjZ#-2PFQ6-4^{N zMOV7#MH^?t%$F%TJR^AcE-7lp`BK!JEk#GLrKkm4idwRzs1;j^TC=6-NVXKUVM|e4 zHj3I2P}H7)qC5hM@(Cy^AfTuN0Yx1NDC$H&QD*{*x)4y*m4Kpd1Qc~Apr{7{MLh{9 z>P0|NZvu*rBA}=b0Y!ZYDC$Q*QGY_Hs7Z$ZkpmL1Wgo=GDSl& zf`9LkqM@8GMMtxxXc$|Hj$upDaJCeUU`x@lY$+PamZDK?DH_d2(HH`X#u898j)0=^ z1QZ=dK+*986ipzY=mY|aP9&gcA^}B{2q-#xRw3aPJm$Rkl3bqto$(EvZY$;mL zmZGcJQgk(2imqX!XafO7*Ah^49RWqx6Hs&m0Yw`LD7uk=qD=%8-9$jq%>)$PLO{`G z0*bZ}P;@H+MYj=9bUOh>cMwo?Cjmuw5m0nD0Y&!^P;@ULRCGy(e~$waf5dK!)=1GH z`-pa5M$CMfq6agA*B+9hhd5t~wy~w?VYU=K!j_^(*;2HfEk%#9rRZ_C6g|O~q8)4$ zJxM^(Qv?(}O+e8z1Qb0>K+$sq6g^Ks(F+6=y+}aOP6CQvBA{p&0YxtpQ1l7`MXwT2 zw3~pU*9a(joq(b@2q@Y^K+&576um_V6>ZJ%e|13OwG7S!Qnc4@i{8$NnJ-iHenwE| z5h?nB^QGuRwiJEDmZFc@QnZ&XMW3*x=u@^7ea4oe&)HJ+1sg?Q5>WIN0YzUEQ1lG} zMc)!o^c?|3`v@rdo`9ks2q^lIfTH~b6#Ya%(a!`F{X#&|0RoB+5>WIj0Y$$NP;`iZ zqTdN9`h$R?KMA3tcQgE64oLht`>f-8Qq;pp{gn|jU#7^*3{KiEMUhNBl9!@1wiNkn zDT=bCC}2xbHMSJR*iuxTEk)^UDT=dEltDmICILlR1QcZxP?R8`C`mw34gp2E1QgXE zpr|GRMYRYhs!c#q9RiB#5>Ql+fTH>Y6g42As38GGjR+`eOhD0L1QazPgo^&j@XvBU z;-A@H*#B3GI=JUWn`Xw$mnk|TGuZUF6t&=dDQd}7vYR#6SBiT~ahAl;H*;3Sw zEk*6wQk2I=Q9c1h1q2jzAfTut0Y#k%DC$f=Q5OP=x)M;-jew%=1Qhikpr|JSMZE|p z>P|%~8kQM+vqOrG;e06?&X%GPY$-aHEkz^QQZ$M!MWfkLG=?ojW7$$Pj*X)61QZ=d zK+*986ipzY=mY|aP9&gcA^}B{2q-#flb2I&M4oLiByF)!sif*v6CNpNfOwr|;!NO;y=nBr4qAS@_w2m!B>)BFt6yy$zGG4o}L zKFSOtJEiDj&X=OSY$^JLEk&QQrRX!Z6n)N?qA%D|^d(!0zG6$!*K8DhLqO5D1QdNo zK+!$|ioPeH=m!Fdek7o1KLJHQ5m59q0Y$$MP;`KRqJsn!{YpU5Zv+$_BB1DZ0*d}1 zpy*EmivA*?=x+jw{vm{lKFIW2I3V%g>}&cTN>QFY(*HLzX1+|3pA`(*B}LJ!|9qq$ zu%)OPTZ&?ADXPwvqI9+t#o1Dn!Iq*-wiIQtQIt(UQG$S?BmqS^1Qg{GP*j6}qM8I0 z)gqv%HUUL-2q>ycKv6vcis}HCZK2t0YyUzp`sR9{(TNeytTn;DMjP$ z!`snWG4o}LMq~wV?3SWqIbVuKvZZJgTZ%@rrDzOWipH{~XdGLL#L$slL#m}nSi1~0*WRRP*g-f(G&uTrV>yzjew$J0*a;+P&9*p zqL~B~%_5*^HUUMa5KuISfTFpCP|-12{vih>zRYfmhD(usnkYIiD`vh-QE66C?+qy` z<9sP9XG_sSwiGR5OVO!pDO${yq9tr8TFRE9)7Vn9jE$nx2`D;)fTHCD6s;hj=u85N z&LW^_B>_dN2q-$6fTD8kbt7q1QcCFK+(kn6kS3<(Ha7Z zE+wGoGD4_mewKff0}}tuzNWuGidNcf(b}w-`7%Z8vVy`lrD#3pOVL$qDY}|1Mc1&U zXaie{u4PNnb!;iRo-IW;u%&1t8$~w~P_&7FqMHaPx|x8YTL>uHOhC~V0*Y=Wpy)ON zif$*M=nevk?j)e-E&__~CZOmZ0*dY>py)mVitZ<%Xe$9l4-ioFAOS@W5kf^*WcjNc zkoZpftmBnZ^rSt~-XA)x3@0*c-upy+J^iryih=v@Me-XoyseFBO;AcTq@$?|tPAo1Gv80}Fh`pmu@ z@?loYe3_z8vV!m4m7-5MUy43sOVQ_SDf)sfMPIU|=qt7qea)7lZ`e}wEnAAdW20yv z0Y%>vQ1k-Yp9m=WnSi2S2q-#0K+!=0ihd=a=r;n24iQlFI{`(15K#0d z0Y!fiQ1mweMgI^`^e+KLUbY^XqbNcM6@8rLC*O059<%$IO>0s+JuT zd>}atSD^K|oPW0*Y!8 zP*j_MqB;Z=)g_>)9sx!52`FknKv6>iiW(76)R=&x!w4v9LO@Yd0*VeNpr{!EMa>B) zI)Z?r7KBhyG}}MU0g3NovSa4U6t&3?PW?!V+H$@WwPQcp0!&TJHQA)u%$0Y%*iDC$l?Q4a!&dJ<67i-4lu1QZ=b zKv5q8iuw{z)Q^Co{sa^aAfRX<0Y!rdC>l&a(GUWPh7wS8Gyz4!2q-#+5Grb&?Qd{E z;`iF$bv#mv^6a)~cy`QunW9nI!DD-+Xf)?b(HOQAjb%&GIJOjxXG_s>Y$-aPEkzU9 zQgi}aicVysXd(eclL#m}iGZS$2`DNgplC7yMMVS@O(CFYDgi~)2q-EhplCV)MKcH} znn^&>ECPyV6Hs&t0Y!5ND4I(^(L4f*N(d;LPY4wqo9%z8^ zSp*cVB%o*&0YzsMP;?FfMduPwbRGdk=MzwL0Rcr95>T|7fTD{CD7u({qDu%UT0=n5 zr34gRMnKV80*Wptpy&!hsHiO4Z{>i*PqW*iaw&Sp?pjV_N zK|s+S0*c-wpy(|Eiryxm=p6!z-X);uJpzi}C!pv90*XE)py(q4iasWUiXO}Mw>lv4 zT)TJuIJZUi*Jt-;$IO>0`aC;$^BXDpg7c;5OSTk!#g?M4*;4ckTZ+DAOVM|1DcZ-D zqVL&K^aC43KN3*1pMavD2q^lQfTCXrC^|qu(Ln-=ekGvjHv))9sx!52`FknKv6>iiW(76)R=&x!w4v9LO@Yd0*VeNpr{!EMa>B)I)Z?r z76cTvB%r7j0Y$9|p`uvA@9TiX&$7Eh)f3?({fms$k%^f3GDYnZLD3IVl*jo}l+Tu; z0=5)&U`tU)wiI<@OHpUG6m?-sQCGGUbz`HbI{`&K2q@}FKv6FOih2`JbQA$aeF!M( zOF&US0*d+*P&9ymqJaby4I-duFabqF2q+p#K+(|z6b&Pw=okWuh7(XUf`Fo938A94 z3I7}iB!0g=Mr$WUpQj$MC1U2w6pc*;oA*o6IL?=%@oXtNjx9yUv!!SPTZ&F#OVNpJ zDVoTZqDgEiI*E;CMK+!w`ib@D5nomH{0s@Lk2`DNfgo;Kd{9O)6e5QTwdW;k`wcDcd zM9h4dqQ!~e`=6y~3Fk}EQnnPG#+IUGY$-aOEk$RrrD!=@idL|t=uEa0oyA7cN&<>j z5m0nC0Y&E!P;@Q0mZBTjQnZmRMK`jgXcJqCZemN(&1@;Ug)K#!*(lmVK+&xP6x~KZ(d`5j-9bRn zodgu!ML^Nr1QgvvK+(Mf6x~Na(ftGzZ6%=S0RoC1B%tUa0*bZ~Q1mbXMUN0r^e6#E z+X*Ooj1VfiCgD$TK;oV3wrGPCO|y?^k0)a0%M?A82$uXNMNf0S6g|V1qG#Ds^c-7? zo@YzZ3v4NRku60#*;4cpTZ(qEQS>qaMXwN0^eO>Gy9p?Ijew%p2`GAlfTBGF6un76 z(OU!*y-h&TI|LNHOF+?k1QfkbK+y*T6n#iQ(MJRneM~^nUIL0fA)x3}La1m*!oSV| ziTARHWlu`c1p5@^XNj2kGDTk{f+v2LqOUn$ioRh>(YI_V`i?C{``A+SJzI)?U`x@D zY$@8$mZG27DEgUzqF)FoIzT|tK>~_?C7|dx0*Ve1Q1m+iMSl=b^d|vDe-TjhHvvWe z5K#0l0YzR?58F``A)qLYfFhrOq9_4H0RctT2q=mXLPcLB{LdYb_yzVs>`N&+!ETGH zCu8Qz6lErZ;4dl4;(RH}W=m0mEk#MT6y>m`D3>ioHP}*AlPyKH*iuxRjiNdP6xAi5 zs2%}D^$93yKtNGL0*V?DP}G=!qQeL%YC=F!Qv!+(C!nYq0Y%LTC^~|Gq80=cwIraZ z6#+%92`D;}fTA`86tyLUisDKCNCzbTRJwzckqjT{KVcu<+9hM=%M=wPgJb@Yq7Ixd zMIG5v)QK%co!L^P0|NZvu*rBA}=b0Y!ZYDC$Q* zQGWu81`tp*kbt5=1QZP>plApIMMDWFI+}o@VFVN%LqO4R0*XcuP;@K-MI#9)8bv_S zXhNtcFX_*BK;k{^wkThUKCv+-88cs|=(uEXsb{Ys--{m4`BF52Ek!4=rRYSq6isAH z(ImDMoy3-+li5;K$d;nXY!np{P&9>rqNxNFO(USFn1G_`1Qg96plBumMY9MfnoU5_ zDFhVFA)sh30Y&o&C@LYKXg&c&3kWDGC7`H`fTD5&iWU-3w1^NY8kh7RbU@-)+n3J9 zOHr0R(mypBGhe3Yv}EvhniMVLd?`AeEk$RrrD!=@idL|t=uEa0oyC@-m24?m#g?M8 z*(f@PfTD8=C_0aTqVowTx`2S93kfJ%O+e8_1QcCNK+z=x6s;kk=u!fTE+e35EdfQB z6Hs&o0Yz65P_&MKqV)t6T}43A)dUn>LkJZuN&0^|An{@Lx$C7;^p@QgZAiw8N;nJq=Pu%&1-TZ*=@rRY|+6y3%~(d`5j-9bRn zodgu!ML^Nr1QgvvK+(Mf6x~Na(ftGzZ6%=S0RoC1B%tUa0*bZ~Q1mbXMUN0r^e6#E z+X*OojDVuY2`GAkfTA6QP|l1QdNrK+$Ie6n#!W z(HDeJ(bGx)JO?CR({78Nk)lm@@A}JR%zT-mZ}PXdbmBB1DR0*d}2 zpy*!$io6^>Y)4UqfTA=4ihKf!q68EL1Qb;xpeRN_QFQ`}(g`Sv6GBB_C;e9(ka&rk z(Ql+^kUi4R$cdRRQ zkBy@G1QazOpr|1MMU4n3YD_@UVFVO4A)u%!0Y!%sP}GcoqUHn?9YH`*3j&H-5>V8N zfTGp}6dg%GQ5yn^+7eLIj)0=}1Qg{FLPc3Qe$7m$sD*t6Bs(X3q`%&7i}G_~=F1dy z$_YAWOHpUem!d9gDeB6WqHb&{>duy;9&9P<$(EvCY$@u^mZGEBDC$E%QC|Xz`Vmmn zpMatP1QZPQMS}?_8bUzPPy&jMCZK2-0Y%3UP&Ax?q7eiX9ZNvbNCJvR5l}Rm zfTA%36pbaIXdEF_)FH<|(E*A7Vt0i)O3_ricRfBQX1+|(2|2-ONhvy!^QCAaTZ$&J zrRXHK6rIeLqC&P5O=e3`5nGC;u%&1!8%5IyC@LnPXgUE!GYBY}NkGvo0*Yo6P;?3b zMRN!!noB^@JOYYJ2q>CQK+ysMib@G6DkGq%oPeT*1QabIpy*TriWU=4w1f~UIzGq0 z!2yY9+HKJUDSFF31-UdQX1+|(89Bj|xl**8^QCA7TZ+zPOVL?uDO$;vqE&1uI-4y; z=dh*dT(%UQ$41fl1QcCBK+%N+6s;zp=pq7&E+(Mp5(0|W5Kwd}0Y#S)P_&kSqRR;= zx`KeBD+wrCM?lef0*bC8py+A>imoA`XafO7*Ah^49U)Y-EXV)S0g2DEo1fFA=p`H1 z=fupHDcY11#A->=O`I=9H?yVa7Pb^^W=qi)wiMmUmZIC(Qgl08itb=b(Vc7*-9ZG%+d3fe7WTLIZ$y#Z7Cn;_Ghe3Yg`8kS9VvQ| z^QCAfTZ&#{OVKX26ur!rqF2~b^eS75cC)4EHMSJJ&PLH21QhKdpy*8kiryli=xqXu z-XWmqT>^^UBcSMg0*XE$py)#aiasKs=wkwk_7YI^2?0f)5>WIR0Y#q^Q1k@>MPCw7 z^c4X`UlT$_&*k`~4oLh}d!+xo6#e0z7yTwDX1+|(_c_7ZdQ$WQ=S$I#Y$@8$mZG27 zQuH%hihf~B(E+v;9b`+yfKv6mYMR5X(G6*QjB%mmZ5GwjE$KU3F z#53)-XrB~Ku#afjxiRx)igI&Y4mZG|BDXPboqWWwp zYQUDFhHMlyBA}=-0Y!%qP}GEgqNW5C9Zo<|GXjd56Hs&n0YxncC~8SSQ7Zz9S`$!o zBmqTj2q#{5<;%Hj4TaP&9ym zqJaby4I-duFabqF2q+p#K+(|z6b&Pw=okWuh7(XUf`Fo92`Cy#K+z}yibfMqG=_kp zu>=&2BcNzJ0Y%3VP;@*YRMa`wALxL@+ZdcKQZ&MDizej8%$F&elp7Sge~~!#b+nT> zUy4pkbQ%Fg z%Lt*O6Lb9w9FX|!_DFvsw?+2h?eyH3`7%Xk<_5PPE=6Z?z7(xwOVKK}6rIhMqI1|% zbS_(p&SOi_`D`h=fGtHAvQe~}fTD{CD7u({qDu%UT0=n5r34gRMnKV80*Wptpy&z$ zimoJ}XdMAX>j@~jih!c42`IXTfT9fq6kSU|(RBnAT~9#K4FnWzB!r5V=lZ)HkocEw zMpsDDk2Y@1jhQbm+e?c!OK;F3;w3h_FWGvD7Y$tEJNIeI>WM7(Xf88h|BQMvF*?ih zY9_8ocwXJa`#GN1FwwN8=QT;psO@>p6L;42yjF={>U&<>ME6FXm!DXEnCEp$JloXs zx+OB2dtR@^=oX&WH?gjj=M7AJc%^8<#lP(eoxGdUo-= zNr^MNdEVs2^F2IoS|Y2r=gmxv?c;fK5?A%}y!nZb2Y6n2;)ubXw>WXiP|sVIxObT6 ztw{Vf-1Al?dXMzH^AamZd*15Ai(@@+O(Joe=Utu{Kf&|XC$2fs^EMM&RqkMsn_xho-(thLcy3z6i+P3~%lBsbpdu7^m{{x$pNk)-`|!z0OW zcDU;#lC*!>V_YO@|1`sdNYZ|`{-j9KemMH%NYZ|~^|VORemwEaNYZ}3?3_r_en9B_ zNYZ}7V|gTLKca7OBxyfmZCNB~KO}2KBxyh8XjLTn*j{%HMUwV&Mpj3X_JbnUM3VNM z{+CCR_O06MBT4&S+YOPVeY4~Zk)(aM+f9+AeY?_@NYcLF(vzG2{=NYehs_tr?# z{>tvQNYeh!<@QL@{?gozNYeh+(=(Bz{k4@BB1!vu2fHFk`@-?=NYcLYwA=aHm+`r_+I(jI^AizMv<#QsRq?g1W%B<(}^p-9qhga3+n zIiI*cG|`*FKXSRN-CxFvbacgC5AMInh8jgyI%i*EsfJVMMY?E2?KxdFmilgV%U+p! zu?yXwy-0UGXO(+xkscab?3|t&ciZTtF(%?hZ;gHK4|U`yjoagH^wF4Zm!NMr+*3J` zBeH8`_}LAz$JfbmDm*W(xtEb~luMrH*Y^DE9vM9|x@R0+!~G`poa&wzboQ)Ns}ae_ z2wx!LW-QC|tMl?18Ce;b8Qt9PqkO{Dw%r~YsMv#Yl1uc~{8dtu)j?f#z@`7=Aqi@0CzW$oH&-#)LjC~tb% z{JgT#sd=S^WmAg_=a-h07f&rOo|ZSYbjkek5(`s{r!6ckF01l9dwKWL-Sg&`&YC-` zeAc33FK=ea+~T~VImL_f+RrJOS~MrGY-Ukuab9WhyyCK=vb^FBg=OUnr_CzKD=#UT zGj(Rsta)X5Gp0^0EGnIwSCC)Wv9Lpahl0X_e2eW|Y&WlDUU9qPqA9c5738 zJTJVWr!Sm0wL^ZF_EU{Q;k4rEMGNPY7nU!XUtHFHrU`Rb*R)yl%H41`1!D&cDs&ff z>VT5Db4%vAX87D~S&*XWcZ>u;-28QIjG|IQQ$62>gBt;7b`4u zXLsyS7`}!A_r^G3Ft4qjUR(dl*Wlg*?!~4poI7_(_?q;xop{6j6uMSi0QU~9c+C}W zq!VvrVC6f*y$ke$?jncpM)z96C#qb8uAJ)Ld8uc*cdX9qT=B}><>8HX(93tMyc`26 z&L|kbn{pRiXPAI0w@3fC{uB-@p0aR8_`7lMfA_ZBAM7eufG$U;%8TZ%?C`}aelMuX zul%iauejI+4y<>~pc4xF4IGm?&s~rD9XYRhYT$pI>CGvbH={}FfB(Z&LFEPMFE;3M z*IDWfz^MXE$kYCu4N9Fo+x}>zUNm2?!bx?P;KI^>jk zvdUFn<*M%DE=VPEZZ8YqXwSB@-Lc{wrNq_dZmIOFjur1h_m1GjE3bI2Q?AmAtFfDV z|CLnyNvOO|_-JCcL3(xW9A2>#7`_YLn@v68-V;2p;v%`X<(hqX9p^su>g74nT_34p zS90ouRQR!JP{rBq8qjO3yaZgw?meXERa}?uDhS^~r44t3r#-Mk{R;RN|=cSZTt2gm!POY-UMmdBq1s zM~}-C5~#TLD?WU?KQyTqv1=%W$h~jEC#ry`1W-^ZprDcf*H3}Fu&I;X$M@8c_kV%Y z9KO~nS8wID>E5{BQw8oGN%(^9Pph7&c!w5**R@^DD!2IsI>TMZmG5r%)R1GxHyO~q zdlS3w+rFTQ-TTe&)}d3AR;9&rii^sMTQ_Mpck29wy{EeOSn=X^b31l)p?v1Txl`P6 z`ka!Y@^!2)jENzGDP2yx*7l zo!gyF-TzGe4#Pin6~Al#lvP-Uvfb%CrQ&9g`<9jW|0?hPfx6-vuef(vaksJJ9%7Y0 zJ(Yh3D(~NM1y|m?tGMFAyNKS90Rwt8X=Q(2`jyUYGHC9U;%U>|UF&f?%uM|e;^AZK z|NRe?dqk7z{`=Scig;cZ6u8fkdaWv27 z<(KcdPq0+^<$Lb)H&uSQPYYLB_WDxqo{Hvs$%?1#3ExZn*Ut6a=Xp}UOM4&Z+GETA zevI0@+-pAVzdrW3m$gr9rP-&4?dU!=Y`UkJ@5PSIbnNafyX`?bPIOP(o}uFn?p@wU6` zSn57aZhN_o+Z=G)&+7P3{cvYA2#*8ZC(-TsqjkLCuyC)_akqQN+Veluv3B!tH`8%a zi*V1<@kVzA*vsFo!(eTt4Z^$YjCI(|DK+`s9VKRDdIbzC$w+$(k5 zJ}lfX>X9UGq)?lwA3yCB>Pbi8eKxF6DS|Ha|{TgNV!hI@dH%hrbbd>x;~>qY2kCgm9pS!E$7k*e_iH-F?+tey9Y@_C?vr%9@_}$~((!|b!u^eohd&bTJRN6l z5BEYH?|MAkkLq|}N4O(ThQ}UHhsPm0u6Q=w7wP!i^WlC&$IPAKuBYReUEwa&as4ad zzFEhQc8B{r9h<)q?gAZWzZvdRb-d^8a6hKwukVK2e=j`t`XD?Wt>alAh5Hg6U)US& zH+9VZEZhxr9QQ@Ii*&sDt8j1Daj*Llm3jDH#}@m--BHImKZJXUj`!^k_Y*oEa$m-> z^MhZ)<5360<1sp}`Yqg->bUdwaKEi%@~?0=(($-|!aY^T4eq15z5ZKu{M3CF%=V8u zwsN0Bw%u9BdG70CwolV>tNQ|(?I(5o!+oX9cFcXNiXHp9FPYhKgpTL9ubtUmtK%;B zMKs&*>X_@knr8bj9VfUitJyBr@jCbQHQTrA___N+o9&-;Jkou|&30EE=Qj!W={i2> zz6NK{e_F?e?kn21TkDu_$H4P?Y7f& z-F?Byj_&Q*FFU%s9jW7FyFcQ#yIbI;WxFrqs(bCrmdq_La-ZKTD=!U?GkMBA$}IQV z+rv7q{gkpYuf2u#|M}^F_U^%H`)T%RQun#(=_T&PQ%@I7nNnK3$gA?)qSB&yGm70S zsXXC-mO1tX9lZ*7DZKVm-B%xq-Dk|JoHf0)Xs&yqeq%Ofx0mz7`9EIHo@c*Wy8qm}{r~ml+Patd@3(7>Uv@p& zuYvAAUbpSZ?!R~3b<8iG>g$5L%jntBe$DJ2@#?xz!#!T=enmk$6m*U?)5#xl~v_=E8WvoU*8Sx_1WdJ%a`f?Cd5-(fUZ1^Qdz)BxPkMcw zmm};6{o?i6IaOb7o4b53@Ivm$%T;~2*0p^}p8HIBmu~qT?DJLb@pgVemH&6?;##+k zT|4DBv0szp%Lfe~9DYqYe8my>D2>-^<&FWV6@-5_TY0tZ(Ot95VacsyCqH#4TJZXz zE%{IXvLa_>KyKO{*Ska)0d7s>d3*_g*v_*r!y|qOsT9i}=;ti~DVB^s}ee zyEpCU*Bs}b4lc3tBh?1GH&!hgZ4uaCgo@cuTWYDlL4TN=1zxn3W@9%yc+u9Hjoj?$ ze!{nALpM8l(Keb5-0bW{+iKQ#vy1y7VVd>a?CM3^Yu0tMn-|T~tm9^P_kG5iwcRXm z7pp+KmTh;rI%wCl?JihH?Hab-CF`V}YujD4&e}P)-DT^dowV&PTvzRcZFlLqX=mGZ z7q7c^mTh#JSO zw!3`&v;*7j^7Yq_+IE+3fVTU5O8*Y-@(t8ZbGxIve1o(jw%z3$tnC<7k4BsOFS_eL zeTDfsBK3E`)AzWK>d_%FyUj2m#{~A5r@FDp(!E9YD&mRO$iyLDIudZC1i}I zgpAdcka3z4GF}rQ$7v(vcx{AC&_>7!+6XyO8zB?55i&^|Atz}g zZlR)cVkXCg%n$4@P^N?|(5Vtqswp95ni5j3DIp6rC1jDNgq*4=A&WI7WQnGPEY(EF zY1#-`rj3x(wGncLHbRzbBV>g(LeA7i$XVJ5S*eYXRoVzSTN@$gXd~oYZG@bsjga%T z5psbxLN3%s$ZBnbT%?VVi?tDQi8eykXoo`P`C0CRNqV;XfDog_gdQF7fppB4?+6cK( z8zGyt5pt6@LT=VZ$Sv9k*{qF_E!qgVRU09Ker<$o)keqz+M$rOexAGj)3fb1IQ5zvU zwGr}?HbQo3BjjamguJ4SkXN-4vRfM=uW2LXb!~*ap^cC|+6Z}58zFCLBjjyuguJ7T zkax8a@}71mWSc+QUH|DXM#z3`g#4t9 zke{^?@{2Y?4rn9fpf*B&)ker~+6XzMjga595%PyNLjKf7$Y0tB`CA(y|7auRU+qxH zhkm)c{?qTY`yL;qgv96DZHW7#meH~A5Q;_u`<9K=_n8F|ovrT>s>arL2*ud?4x#F7 zeTPswTi+oRXX`tJGT8bKp-i^ELnw=_?-0sn^BqD70^cE&B=8+VIRw5#D3`!@2-P6) z9YQq;e1}ji0^cE2o4|Jn)gka5LUjpzhfqBN-yu|=z;_5WAn+YR4GDaQP$L50A=H?_ zcL*Iu;5&qx5cm$ErUbr2=x_qxA=He(cL+5nI3QWkXj;U7!~uzKw7VyMBvkaC-ETP} z5;I<=sC6W;Z}~|nI+F9Hs0~|++Onmn9b1apv!y7HEk*fkDJoz~Q3tjZb!4Nc69Gk? z2`K79Kv7o$in6=no1#`ywB1Mzi^R;ADLOV1*td+O6piG3 zDH_F=qS0(A8pD>Nv1}I+K8+vj`|!NkGvm0*cNipy(U|iq0jV z=sW_7&L^Pg0s@LIB%o+D0Yw)PP;@Z?MVAmzw1$A9O9?2tjDVuGgiz6fh`-taiD$V- z+R;)eYL|MP6^WTIQ?x!3*te{v6kWynQgk(2imqWx(FV2@UCWlD>)29sJzI)yU`x?P zwiMmSM$sk$if$sH=wkL_pCtLa6AXQSu^0*YQF zplBxnMK2Lhw2OeEmkB6(g@B@02`Ji4K+$Ui6unMB(HjI5?IED(O#+JEBB1DP0*c-t zpy*u!iryoj=zRi;J|LjzLqe$N(THEyeWg3T-yXPcm!jQv@A{)i%zT-mPa}bS%X~`F zXPhrZpR=Xt3$_$}$(Ew8*i!U0TZ+D6OVPJ%Df*5rMf=z&`ksKI9|$P=k$|H81Qh*5 zK+(?x6#YU#(E$RA4iZrGD*;8n5m0o9fTG_CDEfndqCW{J`ip>~zX>S%hk&Ag2`KW? zDjwx$roJ8(A)qLY5GvXm@lSR@;*;#==MyQKZZ}MRTFiWzqF7pBKXM_Zs5<9MQ94_S z;%q6(U`tUZTZ*#SQk2b>q6Axtl58o;VWTLQfT9`%6xAf4s1^Z5wFxMyLqJho0*dMp zP*k6Qq6P#MH6);@5dlSw2`D;@fTAV@6g4HF=x_pxnh{XcoPeSu2;3I6AfTuvAygEk z`8PQr@j31*=h13u;UoR$?6#;?TFiWzqPA&){m71#qIR4wMeW&Al*g8$e6|!7u%)O2 zTZ%ferKl5IiaN8Us0$lKT?r`aMnF+_0*ZPNP}GxvqFw|P^(LU`C<2Q55Kz>YfTDf` z6!j;dXaE640|_V^L_pDC0*ZzZP&AZ)qN52Y8b(0TF$5G1CxnWQO!L2WK;m)tcXXm{ zq{z2N`Xka}=F1d~P7CZuzN8e5;e06?%a)>XY$+PgmZIa>Qgl39iYBn7=mfSDoyeA= ziEI>2BB1Cb0*X#1ps0|5qR9jl6%kN0g@B@|1Qbmpps1LDqUi(_%^;v?CILmW2q>CO zK+!1#6wM)^Xf6Ro^9U#^A)shJ0YwW4p`wv#e!c?|pJ=y5qon97`|wtp7BgR_Xi-{V zKQbt#=v2;^qQz_}TEdp1rEDoWjV(pX*iv*lTZ+zLOVM(+6s=&R=u85N&LW^_B>_dN z2q-$6fTD8kbt7q1QcCFK+(kn6kS3<(Ha7ZE+wGoG6IU$ z5>RwG0Yz63P;@0BR8*ekFLFTQE$vf83#I5*yDeIm7BgR_=$f=(T`MWt!1+>iEnAAN zV@uKXY$>{dEkzsIQgkC*iZ-#O=q9!l-ONVOEd&&8CZK2w0Y$eGP;?ssMYj`BbO!-N zcM?!^7Xd|g6Hs&y0Y&!`P;?&wMfVd>w3UFO2M8#7kbt6x2q@Y{K+(el6g@&f(W8V= z(N$^wb_XQBCgR{+Ekz&NZPE6$nE5hAJJJICk!7jdq9-|Dik@Oi(bH@xdWJ1U&$6ZH zIkpr%&z7PW*i!T&TZ(qFQS=f4MY{+ndYOQtR|qJ2m4Kq%1QfkSK+)?26um(}(H;Vd z-Xx&tEdq+(CZOmY0*c-xpy)jUiry!n=mP?ZJ|v*%BLa#(CZK39Ayo8unxEFjDLTzQ z>-dBe^|X7}pQOdimnr%pEojzGioWE0Df)^nMPIX}=o_{aean`j@7Pkbk1a*tv!&<< zwiNxyM$vu(ihd%X=w||oej%Xf00Bh@2`KuNfTG_BC^|$y(eDHl{Xsy{p9B>BML^Nt z1Qh*4K+(Sh6uG~Fe2u#r-B;Az&4B&2(+B}YX#^Dc1QbOHC<+LnqR-O&p$b59@^Q9=0Ek#*uDavL`QGzW+NwyT_u%#%MEk!lhQdEdr<{4+4sM5>V8OfTG?6 z6dgrCQ6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZ5CV#Z5>RwB0Y$?IC_09KqTvJ- zjUb@tSOSVh5<*4oe1DGv60c^TXlySL_pES1QcCD zK+zfkiY_If=rRI|))G*3IRQmi5Kwd_0Y&QwC|XZI(N%;{(W$;a*#U{aX>b-xQGtC# zyV{SLFH>}#AJ~tKPAR&c^QGtpwiIn-OVN#NDcZ!AqMO)KbTeCuZedH&X0{Y0dfE@{M~WIW0Y&cSOVQ746#YU#(E$RA4iZrGD*;8n5m0o9fTG_CDEfnd zqCW{J`ip>~zX>S%hk&Ag2`KWSdf1Ml2mwWD1QhuM6h#Rr3J55wMnF-FfTHSzP|=sZ z-@yTix3y1KeqO53O|KveRQ8wpGQGzW+NwyT_u%#%MEk!lhQdE;I zMYY&cRGTeDb=WAXOF&UQ0*dMrP}G2cqJ{(%H6oy>F#$z~5m3~GfTE@Z6dg`LQ8NOH zniEiT1OY`Y2qqZ3rl8OF&UOLZ~Ps>MwRc;`Sr%qnXk0k^UI_ zh}J$DGhe2tLo~RmpA>cEd@1V0mZHvVDeA(OqONQy>c*C$?rbUQ!Iq+)Y$@u+Mp179 zijE?ns1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwVy2`D<6fTCdp6dglA(QpEa zMi5YRECEF$2`CyxK+$LdipCH^Mfp+xaR(&6(#>dr6n$W~MPs8e^JR*Tj|TQnuB2{@ zCUCwKoxql&6WLNUku61&*iv*7TZ&F*OHmT|7fTD{CD7u({qDu%U zT0=n5r34gRMnKV80*Wptpy&z$imoJ}XdMAX>j@~jih!c42`IXTfT9hAP|?z;Kg5=ExJL97T8C$ zr=l_QWs07Q2KG;er4&8S`BL-(TZ&#}OVLiY6urcjqFrn$dYLUnudt=)RkjrEW~1me z0*YQIpy&+(iuMpt^dFA1TdXQKXF4oLh6`ylqL6kTeM^uLP6%$F(pE*jWB zIhRtjkMpJId$tt)z?PyP*;2HhEk!@ErRZn26#c@Mq62IxI><)RuLKnRMnKUa0*Zbo zpy&?*ivA>^=r00_{wAR49|DU0C7{R)^spU85dwaeA#E?bJ~v8AX!8$}HWC~8PRQ6mD18WT`-7y(612qeM-Widf`Foy1QfL*pr|zgMMn}))P{hfwgeQlBcP}~0Y!NP6y*~_McIKr z#Q}*QvPb%fAbh01$NsWWK@c-vrl@le*gtuhQq+a>rKl@gin_6-s5@JVda$LaCtHeo zv8AXtTZ)ciOHm&-iuw{z)Q^Co{sa^aAfRX<0Y!rdC>l&a(GUWPh7wS8Gyz4!2q-#+ zfTH096pbLD=vV@ZMiNjoih!cg1Qd-SplB=sMdJu48czrnbqxG14oJMQ-TZWtqHAm% z7sSk$DLOF-?4L|cDVoUnQZ$JzMJKVP=w!AO6|$vhGFys@*itlwEk#q=QZ$W?qGAGy zrV~&!gMgx$1Qg98plCJ$MW+x@G>3qqxdar=BcP~+fTH;X6fGd2sFZ-BG6IUq2`E}f zK+z%sicTec%$koYxrSLg&OI?C=OofgE*mnm8v1oltvrWCE< zd?`AUEk$RsrD!EvidM0u=xnwWox_%*bJ0*WpqplCG#MHdlJbTI)% zmk?02hJd0=2`IXZfTFbo6kSe0(G>&~T}eREIs%H;6Hs&&0Yz66P;?CeMH>hxx|V>V z>j)^io)9WJJ@7j@An^(IuuEpr{%FMKJ=3 zsuNI@PC!wdfT9cniZTf($|9gBn-D767x>jqa*FKhuF>zM=q!8KpQsiyU#6%=wV-98 z6xHN>DXPVmqS|aJs>7C|x@;+`$Cje{Y$gfTDZ?iV6rQ z>OeqIM?$D5rd!{e00N2z5>PaVfTF>6|$vhB3p`z*itl!Ek(s_DVofdqA6??O(mdc z8UaPq2`D;?fT9@$6wM@{XchrQB?J`BCZK2z0Y!5OC@LkOsEmN3c?1;AC!lBn0YwW5 zC|X27(P9FMmJm?1lz^hM3BID!lY{R&Ad!pgyN=_esG5C6Tb3L)U#94sr^Sah0{yXt!yc}jV(pDv!&<` zwiMmTmZH1ZQgk<4itb@c(Yn9wngY zF#?JnC!pvF0*am_py(+AigprE^fUoQy9g+HhJd2o1Qb0>K+$sq6g^My72TK|oaBH+ z{;<2Bo1`dW{(69S4pC7|dt0*dw$Q1m$gMPCq5w2y$I zF9|5xPe9QD0*byOpy+D?ioPMB=vxAcz9XRMAi-DkQgZM%2PE>KeMNg&in`d-{_m5+ z=F1fQlpK0_h7=v<^iuRQTZ)dbrRW#76dh$t(XVVNI>wfw-`G<0J6nqWV58_y0*d}3 zpy+P`ivA&>$P4RfJBk7X6jdRhC`dq25&=aa0*aCeC<+r$ltMsJDgi|i0*cZIC`u=w zD1(5aOah9c1Qf*xD9R%EihfKE9&$h;C3g37NQy4DN7vcmu=z4YHNv5+5-F<5>7}R^ zTZ(G4rRX@e6xCr%QC+qa)niLheYO-eU`tUB8$}HXC_0{iqDBN1H720w1Okeh5Kz>V zfTCsu6g4NHs09HzKiC~p$8gwunWB@zq0{C_(aD@%in_3+=oGdTb!AIYH?|aY zXG>8JwiNYbOHnVj6!m7Ks1E@}eF-S)M?g`30*VF@P!uPiXdnSag9s=ZOhC~P0*Zzb zP&AByqTvJ-jUb?CBmqUE2q-$0fTGg~C>l*b(HH`X#u89;I>A@eDI8qtfJ8oZGpVx_ zt+V^0apAD}GDQ=@p{q-!sF2f3(L}Zs6|tpg5?hLj*-|u_Ek#qW<`7Ucmw=*D0*cBAD4It=(R>1m77$Rhkbt5^1QabM zplAsJMN0`NI-7u^Wdsy0C!lBr!B=!x zLO{`_1QcCHK+$FbiY_OhXbS;FR}fHiB>_cO5m2<1fTF7jD7uD#qH75#x{iRNZ3Glu zPe9Rj0*Y=Rpy)<|uV_^`m@?lf+U91`YAM=oU(s#~hs~EMx-A@PzEFy8=k!u^2V08n zWJ}RqY$>{%Ek*aRrRZL^6y3*`qWjrW^Z*-04-!!H5CKIG6Hv5+fTBkTD0-BDqQ?j* zdYpiwCkQBdl7OP82q@Y~K+)3#6zw9Q=otcvb`wzaECEH&5m59z0YxtmQ1l`JMK2M2 zMYn{5gB_5_bN2tn-YP}E+kMf?;jsBKMX!fLC5xqK52u%+H`r42CR>W$VoTB6Y$6}=h`Uh05E2H8WQ z*QDqQyDvHv4x2AibR-;laH$mi!s(^xC|intWlPa9wiNxwmZIO;QuGH~ivDCv(O+yS z`kRfSe+Ve@QuMSPMF9eest`~VB%mmXfT9oqMacvdg$XE1A)qLgfT9QiMQH>Sr4vw; zK|oO^0Yy;)iedy5Wf4%6O+Zmq0*a~;d_{-D!4DmfNSXb?w4bFY#Yk0837aodR68Z~ z$1*88j?+s~9kvwJWlK>#wiMN8OHl*16y>m`s3BX5j%Q0zBQ}Z}6Hs&l0Yyy+C~8VT zQ8NOHniEjef`FnE2`FkwKv63Kidqv;luJNS9sx!91QfL)pr|bYMePVEYEM8>2Lg&Z z5>Qk?Kv5@xuc&59FlV__)WQCcY^@aknf?y@iq<(LY`#pdls-K5QxK%a)>kY!vk;plARAMR5X(1`<#-h=8KO1QZP+plB!o zMZ*Xv8csmb2m*>m5>PaXfTB|gC_0URqR|8tjUk|DECEHQ6HqjcfTA-9C_0niD>^wP zIN1S-d}?sINYQM&FB+c`HeaTwC?&LZl@v|l^iovJmZHgQDVoBTqN!{tn#Pu*>1-)F zi!DVn*itl;jiOlu6qOKAG@F2;IRq5VC7`I3fTA)2islheG@pQ?1q2i=B%o*!0Y!@m zC|W{5(NY46&L*H}839Gh2`E}YK+#G9iq0XRXcfU%RG1RH!vTr>Xy0|5C`ES}snscA z^JR+GrG#ExBSq(NdMR4ZmZJ07QnZ0BMHjH8=t8y>ZDdQ)Cbkq^#FnCq*(kb%fTBwY zD7uV*qRj*pT~0vJ76OW{AfV_<0*bC8plB-rMOPD0bPWMT*Ah^49RWq#2q?OqfTHaL z6x~2T(TxNY-9$jq%>)$PLhu!xn-V}9N~r2ODY}c( zOVQnIDY}O(Mfb9$=sva--OrYy2iQ{dAX|zaVoTA(Y!vMvpy&|-iXJ7P=rIC{9w(sa z2?C0qB%tUi0*ZDLQ1mnbMY{+ndWL|a-2@apOF+?c1Qb0_K+y{X6un45(Mtpry-YyS zD+Cn1O7Ioko)Ro@Kq7z9yjP8v=^HC7|d#0*Ve2Q1m?kML!Tw^dkX9hX^S8iGZTR1Ygmfl;AQ4 z#C<(;aNdxj3+)@(Kc|Gvmnr%+C3NiuDLTgKrRX=d6#dSYqCePD^e0=2{$fkf-)t%R zhb={3s-Cw?QGku2Dg+b-2`EY;peRH@Q8EEVVFHR$2q;P=peRB>Q5pe7=>!yI5Kxp! zKv9%{q8I^1Sp*bi6Hru@fTC&y6jdjns0IN=H3`0=Us8g*9gxTw_JI1R6dkeqqFSk8 z^JR+ariS)kC`I)+y%g1FOHl*16y>m`s3BX5j%Q0zBeoPZW=qitY$m|v z;RFRwH0Y&2oC_00HqB9978c#sc1Okc* z3BIDPsllNRNTj#j7j=^&&mLV*ObweaQ#3g>H0Kg2n!@R&XewKZrm>}HI$Mg)VoT8s zwiL}|OVKR06qT^0Xf_)~a|kG!OF&U60Yzm56wM=`Xg&c&3kWD$NI=md0*V$BP_%@A zqNM~BolQW|G6IU06Hv5*fTEQI6rDpr(JBIpRufRPhJd1T3BIC9slm+-NaSAou4Azj z{b7F*|Ju~B`7%Z4r-mNBOo}#edMUbqEkzfyrD!8tiZ-#O=pwchUCfrEOW0C$DO-vz zW20y@0Y#S+P_%`BqALg}x{`pRs|YCCNqI{`&E z5Kwd@0Yx_vP;@f^MYj-8bSnWxw-HcuJHc0UUTW}T2PD$l&7}2G)YqQ&-;o+NU#94u z)X-m-OVPcYUW)ExOVRyoDSCh{MGvy2=pnWgJB)=s5z4o+qH_1p zie4q4=rsb0UMHYv55ZS-S8DM1ElyDr`xCQwOVM5S9PN$Nu=z4Y@1%x$UMWTIa(XFx zk1a*-v!&<*wiJEHmZFc?QuHxfiaudW(Wh)F`izaDy#y3}PC(HY1QhKfpy*2iiuMyw zbbx@OuLvmmnt-Bj2q^lNfTHgRC^|?$(f0%t{Xjs`j|3DQBB1Ce0*Ve3Q1mkaMMnrI z`i0;tdMhSr4vw;K|oO^ z0Yy;)iedy5Wf4%6O+Zmq0*a~;P*k0Oq8bDg)g+*(76C=I2`D;_;437lAfTut0YwD_ z6m=q?s51dYClOF|G66+h2q-#*fTFGhUs1hC@Q4EvdC%^C>PP%%`VZUa773d#Q`9RG zs=iH%dUJXy>cf_zzHBM#$Cjf0Y$+PRmZCUYiUzW!Xb@Y92D4E#gn*)<1QZP;plCP& zMI#6(8c9IWC<2O3C7|du0*XcxP&9^sqOk-NolZc}I0A~!AfV_>0*b~HP&9#nqCx_S zCK6CoL_pCbg0HAYB-q&jiP+y%l+;s-ZnaSy37aodG%XT3eY+G*=k!u^7F&vDu%&1w zTZ(3}rKp50MYGvbG>0ukbJT{`fTHsVzM?6S;0gyM za+lrxOqHVT_8@6}By7G+(S?!Fwi~5rBd3?5O>8N;h%H4Iv!&<~wiI2;mZHnpQnZ;Z zMVGUsXbT%fR}fHiB>_cO5m2<1fTF7jD7uD#qH75#x{iRNZ3GluPe9Rj0*Y=Rpy);d zif$sH=wD1j1yYn_&-Cw( zgw2;Jx<3;7>Sif=fYVFSgKQ~!h%H4Av!!SUTZ$fGOVOijDSC`8MUS(k=m|E8o+O~? zDFTXi5>WIs0Y$qAD0+r~qTK`(Jxf5*a|9GUPe9QN1QfkUK+#JC6unG9(JKTLy-GmQ zYXlU%PC(Hf0*c-spy*8kirymlitddB({FK#em6MxNzs2q-#CK+(?x6dfU;=obQtjuKGx zD*;8v2)?3sBf;SgNaQPn^PUt9wJ&eKMZ)IG6#W$mmEIvme{*^%`iCt=UYee{OHqI= zMOD~R6l6uqKv5O} zMcD)tRVARP8UaPs2`H*TKv7KsifR#1RGWaJ;|M6KLqJho0*dMpd_{jmf?FJr$Xj+_ z^rsYUcCSmSpB6S>rs(*z&?9$AQ6o+-MUB}~bOKw7ny{s)DO-w~v8AXvTZ&q+rRYSq z6t!fds1*T4tqCZ~C7>vefTDZ?irNrR)Rusvb_5i)C!nYU0Yx1NC@LVJs1pH2oe3y9 ziGZS$2`K79K+!1#6m=z_s2c%A-3ch_LGTsjqy;~9Kq5Qrr?Cyw{Ac=`?7paHTG)J< zqP}UNf9{c@ew<#4`m?2I09%UUY$+PZmZCvyDH_a{q9JT48p@WUVQdr)C!lBq0YxJT zC>ljT(WwL!okl>>Xab7H5KuIhfTGh0C>lpV(HR63ok>8^cmj$h5KvS|K+!}3ii!v* znnXZRF#$!B2`HLE@D=q=3pT#jDZ0S^Fi0OMI^Vr6X=+;7e3_ydX`$ZtOVLbDFGaK1 zQdGj0qSRTZ-nfrD#4IMGFWhT1Y_AA_9sQ6Hv5-fTE=Y6rD{# z(J}&xmJ?94f`Fox1QeY^K+!4!idGX)w1$A9a|tL~OF+>&0*cNfplCe-MduSxw1MC& znw}P%?tnywMjV{8r06tzkaR&>*nF9yi_${pKPW{Pb9yPdge^svvZd%UwiIn5&=y?K)ULc_8MFNUmBB1DH0*YQCpy*Wsie4k2 z=yd{$_7G6?1_4EH5>WIO0Yz^UQ1lJ~Meh=PMGvF}k2)Zc>IUaQDO#0y!j={`U#94z zv{21QrRZZ$FGZiQrRY<(6n(~)qP=V>`kXCAU$CWUA6tsPWJ}S0Hi`}qQ1lf6MPCz8 z^bG+;-x5&t9RWoL2`KuWfTAA=DEg6rqC*4}{X{^~VFHSNCZOmD0Y$$MP;``lqF)Ip zIz~XzZv+(mPC(Hg1YgkyX~B~nkjQiPUB?flsI!s!Gc9bsOp%u!I^%IE3Z(0qycAVo zOHq(5MM-Qa3bCaqnJqUfTBzSilPJ*#Rw?MBA_Un zfTF4d6jdXjs5${fH3%rGNkCC80*Y!AP;?vtMRf=$s!KpoJpzjA6HwHEfTA3Nujucz z;5iORWS{+k{ePsWjeA{E!}PHEGDRn(hqgZ{MNK%p6g6c_Q8Ts_HD^mv3$_%U$d;m( zY$XfTDH;6tyRyr~?5-9SJBZAfTud0Y#k&C_0IN zqLT?I>Ow%#DFhUCC7`Gq0Y%*jDC$8#QBMMjdJ$06o8T*IlpcJ+0f{_e_eG7<{b%~w z>2CB%51TJjG$1|n%}yzbb9yNn$d;l(Y$+PdmZBkSDH_U_qG4<)8qSuY5o{?M$wtvA z0*X#0py)ILibfMqG=_kpu>=&IPC(H(0*cNcpy*5jipCRAG=YGkLIR2=5>Qk`K+z-u zii!y+noK~^6atE-5>PaafTHOHUs1pGVCK_KQOLgQ*k6k5FPup_D?Mz!Oi@XCDEApD zn$78@XbxM7=CY-zlr2SNY$=+@mZJG=DO$jmqJ?ZJTEs@tVgibm5Ky#~fTFVrC|X89 z(Q*QcRuE9Ml7OOf2q;=bK+$Rfiq;TNbS?o!YY8Y?M?lee1Qe|&py+%8iZ&2XbO8ZH z7ZOmkk>D$unI0VJfJE}`0re~?>S<$Bdf0rKqD#|5^PZKW%Q(FhZDvc+V>j)^?MnKW^1Qcy2py&nyif$yJ=q3V+ZYH4U z76OWHC7|dw0*Y=Ypy&<)itZ$!=q>_^?k1q<9s-K)C7|d&0*dY@py&aDuju0R;FS(Y zA}4YNTif|FH_VkBXq%QQq-K&>%OQ3TZ&F(OHoU< z6t!YYQERpo<+7zHk1a*{Y$WfTC^$6m=({s0RT>Jqal4MLdMO&hmZG6-DH_I>qTy^Q8o`#Lk!&d%#g?K| z*-~^G8%3iDC>ldR(O3eCPA8yf905gV5Kwd`0Y&2pD4IY(Q6T|E6A36PBA{pz0Y$|G z6ip_eXbJ&EQwb=VMnKVY0*cNeplAjGMKcM$qIgE|m;(}7YWGD0rO3Wblr$?NY`#p< z+>B7|x1^|)(@RkqTZ-nfrD#4|iWab?XdzpQ7O|yhF ztstOiB>_d}5Ky#=fTGm|6s;kk=v)Gd))G*(j)0=`2q;=lK+*XG6m1}&=mG+YE+n96 zBLPL52q?OUfTD{DzM|O~!BZTN$glP@{W((9#2#v2k`Xpvrs(pF(D-+xXbY#8qAS=^ zbR}Dgu3}5kR<;yf&6c8T*iv*YTZ*n@OVKtqimoT1XgdK#HxN*CBLPJ>5m0n90Y$eE zP;@H+MYj=9bUOh>cMwo?Cjmuw5m0nD0Y&!^P;@T=MfVX$q8pCfPIn9T{QsWr`lp2;KOe6g|P|rRYhv6g|b3qMd9hdYUao zyVz3n3|oqJv!&=+wiG?bM$z*G6um$|(TfBWy+lCK%LEj?LO{{01QfkSK+)?26zw6P z=nVpj-Xx&tEdq+(CZOmY0*c-xpy)jUiry!n=mP?ZJ|v*%BLa#(CisdT%?Q5afJ7d# zyPwCTXrKK!vQ1k-IlUC6u%#%KEkzNw6s57HD4i`u8Eh%aWJ^($Ek!Xlin0hO$|j(w zDgi~+2q>yfKv4|>ifR&2REvP3+5{9GM?g^>0*dMqP*jhAqWT0BH6WlUhk&An1QZ=l zKv5$CiW(D8bOHfIO$ffCq|D%{4oGCH!3kyh&-C3RZTEyNGi<(0(TSO%1)oY$OHMCE zt=Ll3nk_}SY$?iPOHn>sirTQHs4ZKH+OegmJsU+G2q@}EKv4k!MV$yJ>P$eP|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9QC0*c}U zUs3bS;8q7DGSYqm(n5;fG*SaI!{*Br4b2Qau~&+Qae65l&X%GPY$+PamZDK?DLR!c zMW?Z)Xf#`j#;~PmEE`3q6HqjcfTA-9C_0mXqVWV2O(3ACkbt6z1QZn!P&A2vqGAGy zCKFIJg@B@|1QbmpplCV)MQ0IEG=qSmnFJKgBA}>*fTGz1U(w*q;1>=^q=r358zMzN z8mT#%Ve@5*=4FP0`=n?-rRv*!BZ53&T>E^MfP3CE2Lv}s0~|++Onmn9b1apv!$p5TZ%ferKo_7qD}-9bta(bBm#;~CZMPb0Y#?} zP}G%xqHY8fbtj;x2LVMr2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yz~FiUtx;G>Cwr z!31AX%V_Xi2PAU8Jx6OLMPDYKutme>%M^`>hHgG2MI$-A6pdm_(Wz`HI*lzwquEk4 zhAl;7*-~^mTZ+c9rRWSciq0gUXgmQ$69_0OB%o*_0Yyaw6ip(asF;AF$pjQlA)sg~ z0Y%dYD4I?{(OCo(%^;v?CILmW2q-EcplCJ$MRN!!noB@YDZy7XEE;^p0f|ht?_Cd< zqK0-~R2B`JFH^KI8v6dQ6fNTPQnZ*YMN8OHw3IDHXS1bf8C!~$v!!SSTZ&e)rRW?s zidGR&w3>jTH3Sr$OF+?D0*clVP;?#vMe7MDI-h`|4FnWjKtR!j1Qcx~plA~TMHdlJ zbTI)%mk>~NDFH>75m2<5fTGI@DB42s70r(ZvwwDq=GxEE7D&;?kQ-M-!{*BrT^$Xz z{Y8qd;q+2;EnAANV@uICwiI2@mZI%!DY}6zMK`jg=q9!l-ONVOEd&(ZNfpOF+?m1Qgv*K+yvP6g@~l(L)3jJxoB+4g!iEA)x3{ z0*W3Zpy+V|ik=|&imr+VM>`;qc6ML1Rf;CrSF|UiVe@5*c11&rewCtUIK33@W=qkt zY$rRW8=6uronqLWIW0Y&cWIR0Y!TWDEgd$qAv)( zqMgy;H4aGRWP4inv=see_eJ}nVe@5*zKVvP`b~Lr2`UaWpEBi z(HOfgN{NNdmnlk*g+hNyQ3j`%qD;0FMcGmmV@pvMTZ*#TQdE^KMb+3+RGlqFHP|Ss zNkCC80*Y!AP;?vtMRf=$s!KpoJpzjA6HwHEfTA1%iW(A7bUXn?jR+`eOhC~I1QazP zpr|PUMa>8(YED2=3j&HxB%r7z!B-TC1zR{EkzJ_{PFl==rvH?Ed21C5n=ez89}C6* zmZCPCUW(eXrKlZSirTZKr~_MyIQFJl^MO_FeI)#9ut^^cy zBcP}|0YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*ZiW5*Ykbt5=1QZP>plApI zMMDWF8be3_zCW1)*Ydk1-5(rKJtibk`gXbfA5 z#yz zjew%*1QeY`K+y~Wie?f}G>d?u5(0{56HqjVfTFns6qOQCR7OD2JOYa56MRJ@W5I_U zkVqH%(b*^|%CKkp3u0mOWr~)>Lhn_PqNSW(iq2+B(K5CaEoV#73bqujWJ}RGY$;mB zmZH^cDO$ru(YXW^ttFsn9RWq>5m2i(N2P|=$crthXWF+Wp_WNw)Vr&6g?qHWs=yRf@jj^ip(?Ek)n6 zrRWE?6#dASqC;#c`iU(?huKo}Gh2#|uu=320Yyg%DEgIvqGJRU{YF61?*tV6K|s-; z1Qh*6K+)d>6#YX$k(Z^X?I;QmP*jD0q96f9Ndy#y2q;P>peRg0Q3?S?sRR^72)?4P zW5L%PkVuJ}N#96OZ+oVnmK8Q%rYM>f`Y}z4Vw_%zve;6T&6c97Y$>Y7mZIuxDXPJi zqMB?es>PO~+H4dZM?g^>0*dMqP*jhAqWT0BH6WlUhk&An1QZ=lKv5$CiW(D8bOHfI zO$aDzN7}RxTZ%ferKo@{MV;7E)R`?sC$XjIWVRG_VN1~|Y!r1R zpr{)GMcoM~>OnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt=TZ+c9rRWT{6rIVIqVa4gn!uK#Lbeo5WJ^&I8%2`{C@LnPXfgpsQwS)UNECPy32q>COK+zlmislkfR7yZm839G}2q>CQK+ysMiWU-3 zw20s{xEk(DnrRa9H6y3p= zqC43rx{H9Ky9p?|hk&Ac2`IXcfTH^eD0+Z^q6Y~mdWe9chY2X!K|s+X1Qb0=K+$6a z6g^Hr(Gvs|JxM^(Qv?+4B%tVN0*ZDKQ1lGJSF|lF*wO)sG_gOuf4vmFZ1+XGv%==f z6upoY8dOt?UgY#r^b%W&US>2_aqP>TMrAF5?$hs~EM%FYgbP)CZYa(XGM#+IV$Y$>Y2mZF+$ zDXPVmqS|aJI*u(xb=Xo=myM!&1QgXLpr`=>ML7f%H6)laQ z(NF@4h7nLSoPeSc1Qd-VplB2UMW+%_bQ-}|)IK}d%K?d;XmC16(ILAp8l4?BU#4hW zcBt6>i^Peaqn*L&rRYqy6pd#~(FC>>6|$vhB3p`z*itl!Ek(s_DVoei(G&uTrV>yz zjew%*1QeY`K+y~Wie?f}G>d?u5(0{56HqjVfTFns6qOQCR7OD2JOYa56Hv5(fTD#2 z6fGj4XfXjrO9&`hO7Inp%?_@2Kq7+;>A2*_XGov%}`g6s^n--G00jox|y+Xcb$E zR0*W>fP;?OiMHdrL zbO`}Pml9BP839F`2`IXpfTAq~6kS0;(Uk-gT}43ARsxEyCZOmV0*bCBpy)aRinbAa zMa#2;dmNC+0XLIYNYRfruFnpeFE7)plGG@*PLqHaz1jW9){DMq;G*BTZ&Rj3Gu*Se z^r-za>apms49}|;y)5c^wW1$od0yRU!)l(F6P;4S^BPC*tmS#lqCX$!c`c)z>UmyX zba?~MYZraCq30Du(;9o;$288R?7Xe+HVDLCzsB7Nfmroz?p6rIPT%fshCpoFjqY{`#OzN_=`(~%RO#(6dmpw)XV)jonj1I)?@75m|h}mC`J|PgZzukILAZC9(@zg-f z{(jjRftdXTp|b-q`x_q10x|n5`W6Oa_IIo;4aDp($yyPJ+23-sIuLteue*f;G5dQ) zHUwh!7e#Ce#O(j{zcdiD|5bZSAZGus?bbld{%6VS0x|o)-EIiP?0;9fB@na!-{g)! z%>IXgdjc{06Wg&{1P?(2au3Rf#t{-+k@{I_Wh{?aexC#O=MEq%qva$&7#-T{I55PwK!a8n;K> z=&CWp<7qT!^N%vjW-4 z-D+Llqqe(++Eu!6b=|x0>bl={7wJC!#DDEScGFh=Re68z-Zg30Sejeh zW_)Scyh+naa?46eW)w{=oHna8cS=#w_`O~WL9yj z;=+m3TIJ`pZrjRU-P*nSU$4rYHmhjHyh+8mGYgBRPMh`r`^6|-R9g9(m@+lD``k(M zrp+qpSu(e{Rrz(XuxxJPD)Fz8p>s>7yX(9(cf{<%xo7p6H*5Sz_pwYFI%8hx_~G3< z3~K*>aWl;?EGxEa%k%sjdh)zkMQ!prwk|RX<0lnQE}S=`Y<$_G*~O);rY+3{L_;}ta6K^xxL3Ea6XxdDPn^Quhn+HzTrHH{(!H4LzuVj@ zK}ULc@4n;vJGnO-Ki-|XZJY7_d&qZZ#tHiH z-n#3(^{99c?iz4!Hfi3>nT!1Qq_=Iy8FyFcSbhQA6}8=h3U;%5YbK-q2lS z|7vva#ebpFMd-*$-IbSkrMqHvy7uMo%v~PNw2j`rZN=s2S$>NAo}87t;5vl~sC0+* zfAwkFt9atPDgH;}u77u4?lZsA4WP@>uHvG(8{2>L@{a{oc@-Z@r}B%P@4$NT-ebmh z?=?JeI(IwjBXVB#Qm=oV(wk8-Yf4VyKmWy4e#HgpAvWl8w^`y0;8YIA=V_m3y%VRN zZl4;7H_g+#a8h+idX!%#`ruPeVT z-A&-1Lxl}@pW)sr@y-*ka<{Ec6`}&?Za^vQ^PZj^YR@YEl3mP7_xbrcg#%P^Te_F}4jz@$vs0%WdvM%3KgS*(=M}VRm(y%+ z@r>fa(&FYht!5U@p4X+w-5kXWTg`0S)`haE^JY$T$H_BF3d>r#$JSlkZ9d6@d&|kQ z=eKWFI=j`R{0^=Z&MlhS#XZ=bU(jl1>zVH1`iYZDXP-EEc227)Ijx4Y$!X;tA9g8n z7ogSTnZ>20g;R=K%_yEVrEF@KJeT~3FRhG}TXu7mO)Htzs?ys@jfda3L160jw>D!Ry+>O_dk~s zQrsQCE>^`YtAqGw~7npVH+Y zHJ@eWmZ5A9I?pP9eQebD-k!9XD{rqr37O z&VPvL_3hcSb51k+eCa-SW=`*!6N@KJau2OX@;o&0Da7;3=Ku32lzaN`p7s3Weg(WL zOEcZ~0%}!y)@@I^duArB4h-MzzE|OS-8;Ge6x#DwFOchA3>CB*)Ot|&{)4^btni@J zU?e3wsal|Vpk}aEpmyN6K%GF{K>aGm2U^?H^Z)o&IVE{N{ZskX?)gvU>7K16o|Bcg zpgn)9^egC|yJc0{_KgJhJyfq=d9cSBf&;NW5+qleYJn28auDQ3h zZ+um;Zy(#yee2jhZaY@j(S3)-tKz<^($J3Xjhd<3?PYK0z5|>%y6^iYjy-f7s^cgf z-LvY%>!<7JzB`-P%XM6><0c)q>v*rbsqB27(D5zzq1paS$6wqBU_0Qhay!;^AB!Cu z>Db9#cH6ymJl(x)dy0ut^9qGj%DtKvbSHUcheqKjIZLiPJv5&h!ZI94#g9Byz3LW3c@}!f1cb)bXaV{=Q$wgX8@Dn~rV9`@5@-3k&_dM#m=| zbh|!Y)-h?azq524FxB6u>9}dSzpvKu-5LJgr(@j`e>c~0;v9dM=y*%1zaP}`hk5?~ zL&tUt{oP&1#f$yDR>z%7{r#$r$;hC>VKvc=!kbsT)9zfafk(yjj9 zrsIe1Co^{Ye5GT~Hh;I$aq@P5m+E-OjsAW_$HO=K`yU+(Zu56<9hcqV@AGxseV4!A z&@pnazia9^^nQPzq2uNU{k>hsk018;H##2wsK0Y{ocg%G=jnLYlm328$0Ixa9eCP5 zc7Db`_SJF4v;Mw7$LF5+_ggxqzvS=QIu3uu-{W=M@|wSI)bZ0j{{BwK#&7vMU&rb1 z_Tym?x$q7f7G#=`xdk9_BzgTKR2_zM8^l* z572Bst>f?RCuz3B?tf*mV>kCBH9HQ{@m%+_HQSfy_=@`>o9z#D%yvI*v)w?)(eB4? zwu^PV#{K-w_U$@;>3$Gr`zIY+xSz<`?x^GJ9Dkp!<3sLeboTmZbgb)s;%&RRj(K(r zdEQCd{d63q<3t@xbX=TL1f74XxdC z)7F#hyQJ=0)00cwn->#*5oBurD0@wIux0C(q<$m+NZO?GO-*>k$zj&#e z3+^GKXGi;WX{Uf!%Y~}$WxM(9{n_Oj>V9(?_oCOUX~1h#De&UN|9HD8%>rJIoj|{M zyEEOce7<+|2qete`P%t$zVqD6oW{NAt#$9uZ1RiO&2gdf`+L07`-`~O@&4AjmpP5S zkIUWr+s}2<5z%az~XEAIW-<+96{?tb(BE^#m0`^$5`?blNG$Li|Y8|at4&VFB` zBX4&_$AC9LZ(|4E?smP*tG;w^XSX@O?0oIl&F**Q%lCGrkJqjrF5eFKva>ha9TLA{ z1p%)!!yWB>?Ux-ZT@Btq_jWlh+UI$e`)%*f-mje}mfefq4CmzpdqKZ=e|DP6Z}+9U zd@t}u?#SC!JY8#>m)E)^*L@ehLqT2}`*xLkx}BF_>AxL1xYns-yS#!N`!yl5y!XI9 z{?DxacN}of(s;jCzFwGEA^&r;nR~8S!)x`;u^~eaHAo+Fr0b|5hrDk6kM8MlS$uQ< z%|o6!b}+Vi@aBP+_jfPtbiZf2-xJ*Lq3(A#_uF&7V`C?doqlnZKi}?oxMg7NfH4zC zOuyEx^W&@gkC+&revNy%`_XMxR}P4~*IeyZ-@|)?XD42_)vbPqpAIfgyl#tIRT?gf z&+j*^XvD;x)30#5$I+I-x&3>(_j9FN^W!Cnx4g=|Z0~c%z!4LR+_^pTbGK2yzuoO< zQQDA0fz;{!KRb48oBO?T_pyWbxQ}R{J6;#easS;k*uH6JR`GtiW=$`5 zsRs@i;XWe!7~G}o*+20S*~c(2-Y0P>?eg2D?2&klU4HvmyOw_hDLDh;C-oodKGt~R z8XI!No82egaX`N!yQb`VOUdaTZ>zVkYtG)HYrM7I!p^x$&dKo>dJ8*myS|!~pL>gV zqr`c0eYrE#tuy3E&Yafqx&!T+E^_DPUxPyq1=CkFb=Ogidhupt(dURD=6IK<;-r;WAlw&Kdyb?!KR}h-|meX2xg!>o%EQehK@y_b@r} zI=k)dS}RJtj$3|Oe7tUHyXD<2ID2w@tSs1hrZg;ypIYg2r`yr)Rfm^Mi2iutY|6bBPtK4UK;imXS0}6}Kv@yPMz^4A25}LXl z?q79%xhA`=&rN*%_L(;1NZq1UiH~2`#)##K*V(mU*XYv3>!d5VF!4IOwwJ``C0=9K zwOylg6R)xBdPUBx_$*1V+jd36Iq~UoVCP})b#lUiokxXPJCEY{gz|H+_d2fpJnT}B zDL)Up)T0uwvvY8_;fUdh*V+5G(+y6%&fb5w!@aA<|Cd`d?rzaZpW7`O{ON@e+kdGN zbT6;ie)R7~_LS@9t=yV@ypzk% zr8r)ccrT{e-ply%_ivYGT=_ZJXV2*JbLf7!d(}~i*V#v5_m{&Gud|P0Mb7Z}U|njv zRZ?<>#0UJxed54)?@ITHroVf|ePaBSit}-o=%kACahIWE`T5wTZTH`p?hx;g_zK*? z#13trxNmCzKYRt=z0$t=9H02=W1mAU<1GiY>ffsTt54m;{e^vub(}jMZ`e6ksI%*- z!kyhl749LFuiJJXIwHL6 zrPtrP_?y2Mb=`kp$WsqAJZt=uJA3C$Kjqm@#ZP}dX#a@B=gFG*ntxr|a}wukw}w3u zS{`3kNtNA;_>Uv)Ud(Ri`H9ooy_l`ie_iI1f882060b|#>J86|Pt|Q|=VSL&lM=V7 z$+C~HF!8o_9%sbQEI$XkR>qc}gWZRnmUx|gF52rxBwlB?fZekUj}Os#*m>G{#1rS? ze`Ixw`X%1l&e7geuf%(@bF^!_d*XG8`{st-<6ZQA68D_$qwJJ;KX$J6F?T3G*A+SK z<85?pah|OcueI~ETl>Vsx!8F&b&vh*aUx$08kc{Rc4-odgvNFU1Ud$eBn+VNfPF}3?0d#mt?ua9lCYoK~Os{2+u$ExwF1FH3}mhk$|ufra- zYb2b|Y?mP#j}3_R&q}}TNt{m@* zeNNkB!)}MeMLG7hBd2IW(bTctpYObV%nR6S+%?yuPX9XblnM3~W?$l(^B+HtxNmRz zq{ie*cIqFWxt#c4M#BwWIHdJzM|Ok$-Ml5e%$MJY#g%;ma)o zUQ%Kt1?syex9Qir?|}8F{7l%rvPvNNZ2LJ{Ams}8y@V=NLK*H`0adDm&vP-@*geUt zGN{%dd%L7iQ}>$S&GuG9YEMX{a8+9=p?5-d2q*q>_@t2iq`XQ}_%rt=!94c{!Io9K z+slu*vkvA}8|hvSZFK)hw*TDYeutO3|1_|R@_g8RizF$jN$6qswyE~F?l#r`N!`HB zd@re)W_>r?cuCDQ>$%z1{Yy`pb=_>|C7q~Q$IbR$QcKO_-0a}~vS`iPZg%vNT5HyF zv%pKr)vW1eC-?VFY1VKv-(9SH?drDOZMCb~c9*Q3cD8MI(b{Wg*>;z$ zgLcfeyKo(~qqg0pE6~og?Jiy??F`%Q@^#iuce{;!jWbKG;clo+#r`mRx z?-cD6+wSsp)ehTsm#>?4vTb+yx@(7QyUW)@JIS`Yd_A>;w%z6HrCr7Cw(j!v)(+Tq zm#>eugAhqdY8?E)-TrCYg6^9$CnWw~;ItwqBdKrrVfO|mBp&*}(M|{%sFO;_AWaDw ztSKQwG$mxHri2XBl#t{`LW;E!GFclTQ?wB>RU0AGv=K608zENnKN=*s5N>f6%YD&n} zni6u2ri5IpiID5G5wcAiA=hgoWV<#(ZqP=^joJvgNgE+IYa`?qZG_yajgZ^45pugW zLhjH;$er22BFttlb9G$rI2O$php ziI8Wt5%QciLY~(~$P3yCc~Ki7FKHv>Wo?AKqK%MOwGr}~HbP$4M#vs*guJ1RkT0KtBsKF zv=MSp8zJ9oBjg8dg#4(DkVD!C`AHighqV#%vo=DGXd~noZG;@vM#!()2sx&Wkl(Zs z^1C)d{?JCqpV|odOB*47Ya`?zZC}VI!PV~ePy50idwiM@lKzj~pSVA~Xmq@cq@<)k z=*Fn~zy0mmOemmJH*niM>`i9ZciTNI53}pJ?H-n=u$vS6mPgpfx$Pd7 zr?G3h?H-n=vunBS9+qdYYr5?omS?hSxNXmCqJ-)e+$D?=s#$OsF^f>ug1d~_glr4$ zLRKYYS#X!K8X;!EUCio)s0DX9YY;LmxC>g7kYT}H(prRc7wj2MZ9s|D32{g`D`g_!PSFQ0Rcsw2q@}I zK+#DA6rD^!Q5OP=P9dPED*;8_2q@}KKv53@ih2@I)Qf66crIr zG>L$sVgiaL6HqjTfTF1c6ip+bXgUE!XAw{|gMgx$1Qg98_=*Mwf~Ptl>AT!a8YD%1 zjZ{e>Y`#oUX&|(qh7^@?dMTR6mZJG=DO$jmqJ?ZJTEv#3#cU~B!j__?Y$-aMjiO}) z6fGy9Xaxa9D+wq%hk&A01Qe|%plA&NMduPww3dLPbp#ZhNBDopy9@Xz?|t9*GnqUY zAVXjVid2EpmI_kpO5NR^QlNzvD^j8EE|dywsk^(oySuwncfZd+^Ly{T&OK+JyXf8B zXYG5}>($kMKjfc;$(v_pk^mGPDNuBjK+(|xMaKvf9V<|DoIug>0!32<V_VnpVv2$iKz1^;&eQ^P%W8I~1L6hob3rC_2Lq zMQ7Tf=qx)Foo$DrbL>!bu1(Q-0!8Nw6kQ-tbfG}eMFK?^3lv=&7fbKvKq_0OC*`Mv zqPdfzTZ-l6D=E68n3eKxSZ!5wr}LrcE;|(6ZHJ`-*C9g6O=L(% z4n^(kP}FRPqKX}g+S{S1#STRs>`>Iv4nMBswO`xc| zK+&uMMY9PM%`Q+hhd|Ms0!4EP6!j1&>M2mvOQ2|Ofui05Me_)*Me_<2%_r0qWeuh4 zb0C$I(J6s;rF6)n(E`XvWa8I=ECjK&2+Q8hi& zU$>#0d?iI2He|E)4n-R|ABr}%L(wL7DB9ExMVr~7XmdLhZDEI^E$vXWl^u$x^t&jt$9Fnd@8-$|n=^kx-Lpk|Migs(rhRhp^c6UA$ z?O}(aJ?&65*$zc}*`a7}I~46>hoXJ$P_&;NiuSiDIzXW4K!Kuz1d0w8C^|%-=um;8 z!vu;B7brSHpy)_}qN4QYd;fU5id>C?{V@(diA@MSViibmv3S8FnZ-(+)*v*`ercI~1K` zhoW=sP;{Ohiq5w~(FHa|7YY=+N&kjZR+o9+II}|-=hoXnQG@K+%%|MNbJ7JuOi5j6l(|0!7aW6g@9c^nyUqivmS22^767Q1psG(W?SQ zuL%^rE>QG_K+&55MQ;fdy)D!g-Pus8Eto5so}TI76^e$ZN7wH(l#{Qd=!1rAk-nkm zL+3-$M|LRs*bYUX*rDiCI~09phoTvFDEizEMPJyV=u4ZTuLO#|7AX2gpy*qHqVEKX zz85I^L7?bIfuf%TihdR-`bD7VSAnA61d4taDEdR7=ud&7{13xEJ^wJ~Us2CLRg=CN zTNEg25GX1M6g3JIWkOxidkv*6av+s4>00!DDEcFfrcyciN{ZT*vOW8UqGsnqQN<2L z?d?$1Vuzv*b|~s-hoY(-ifVQ!>STwa&NfA}2o!Y@DC#Ou)J>qMyFk&b0!6b46wNMB zG>1UZoB~C22^94ZDC#Lt)JvdfZh@lS0!8x(6wND8G@n3GAAzFz1&S6B>WbQwN@wOk zD!Zj`7iwFoKhys(U5gehm6NZesDCNDYvE8d!1++LupNp9+M#F>I}|NyhoZ&oP_(!m zik7fL(UNv3TFRzqX@R0;1d5gwC|XXSXnBF6K>|f92o$X-P_&Xj(aHivs|XaWDp0hV zK+);~MQaEYttn8nmO#zw4OlG`a)e%-%{!Q97tu!^iZf@DEcm4i#8~g zldq&`lTw!c7=YH#U2p1qDB8>pMVs59XbU?OZE1(1t?W>=wH=DKu|v_eb|~7;rf9H0 z(e?sGLj;O;5GWcdP&7=SXt+SpjsitH2^5VGC>kkHw6j3bE&@fP1d2ur6paxm8Y@sV zPM~O4fuivOMH2*yCJJ>$8GHF2C^|WPB70J)oO~rkdzP}b7Y{{~oexEO z*`a7}I~46>hoXJ$P_&;NiuSid(E)ZSI?xV92iX)IEKqcaK+&NBMTZF#9WGFGgh0`e z0!2p&6df&4bc{gJu>wWM2^1YKP&7rL=mdeHsRBhO3KX3rP;|0D(J2B&(*%l673zw1 zFO|mSKq}>QE!ra#ZJkJ+Rw^f7Nzs|5Y|4_M=q%?$(b;w=I>!!0=h~s@JUbMfZ-=4_ z>`-)}9f~fpL(#=HMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mF zHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS6x}J*6-_UdZp?vHW~9r{8Sc^2xT{o7 zzLKK*O4&>KALP?|k9NQFq38iS6g_B%qKE8I^spU@9%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+XWc0um43^CRHmoTI^G+K)=bx;_eLyUsU7%=Ifuh+2ie?umnnR#yPJyDi1d4hH6!jD+ z>LpM#w?I*EfueZ?islt4nopppk3iA<0!0f56fG!Fw2(kiU!kt3xv_M34y3X}x)xO$ z>(BHLPWNd28q3L7QZ%qJyJW>sw21SeXi+;9EoO(J#qChEgdK{Ov_sKSb|_lf4n@n@ zp=eo~qU8jNmKP`*Bv7=1K+%cj@OCFHp3BK+%Q*MH>lqMFSd3Pv$@>Q}Wrka47mTU5hquEGJ({(dLcW zmn(;&Eu0TUTiT&$D?1czZHJ<5>`=6=9g4QIL(yP66m4&Zq9Ha#I|vjF6(|}eP&8bi zXh(sfodk+T2o#MJDB4+|XcvK^Q36Gy1&YQ96pa-q8YfV+t3c6sfuaclMH2;zCJ7Yn zCQ!7yP*=2RW2y5hxuUk|D2EfnqJd??!24n_Ofp=f_Q z6dhoPq66(vbdVj24z@$lA$BM_)TZb#fuh3&ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C* z;{}SQ2o#+lP&8Gb=tO~{lLU%R7AQJJplF&v(WwGOrwJ6DE>JXGs4JS>SlTKFQt6kz z?|QFL)Gq%GuZ?FkmXoif=$yuEuQfu^xz2~8^XyP`z8#7#utU*>b||{Y4n-H+q39Aj z6kTeEqRVWGE*B`eLZIkMfugGfimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n*@q(7AU$! zpy*bCqT2+DZWk!JL!jtRfug$vitZLDx<{xhI;*jCb`GTSZu$zy*`a8^bdPp#V>$Us ziXLpt?pZ4oJ>+~Sde{y{kJzE;Q9BepW{0B3?NIcD9g3c`L(x-qD0x z6DWFLpy&gEq7Q|-qWc?5ALc+Ro2NUm2SU+p>6!jVjpgJkDf+B2E3X@hW;h>;KDR^B z7j`K6(hfym*`erbI~09mhoW!oQ1qQ0ioUlg`az)RM}eZB1d4tZDEdX9=vRTF-vo+& z7byBepy*G5qCyr=+bJpv6g3DGl>~|!1&T6(q9%c&vOrNAfugnoMePKNnuWTePZ~=L ze5E_NvDYKNk3 zb|~s@hoV_+ie?iinq8o14uPUM1&ZbpDC!|l)Kj3Smq5|n0!6(Aislh0npdD`K7pb> z0!8x+6fGc7w4gxILIOp71&aC!6!jM<8X(jawPdC7Igm=<^nKSIvidXqrgULiI4dV# zNzr0iHg&^Lw7B!3XbC$MEoq0MrR-3&v>l3;u|v_ab|_lT4n@n`p=gjz(Fy`ZD+&~? zBv7=nK+!4!MXL%FttL>kxI6s;vtw6;LeIs!%O3KXp;P_({4(FOuV8wwO{ zBv7=mK+z@wMVktBMT=ymn{yzQmD=QR77axYq_J66PQH?&t+MQujYHAa&WECH>`=6= z9g4QIL(yP66m4&Zq9JxD+QAM*L+wyB%%*6#K+%o@MLP);jSwgrDNwYtK+!G&MWY0Y zMhg^;5hxlfP&7`UXjg%v@d8B?1d1jK6ipH++D)KncY&fk1d8?)D4HzP6>X7~{>Xt; z9!L*`whTq%(zR%>teku$Mf+vhT$_cW{hbd*2iT$LKsyv2WQU@I?ND@x9f}UML(yS& zC_3B@MMu~a9Vt+Blt9tZ0!7CN6dfy2beurZ@d8Ct1d2`&D4HrzbfQ4fNdiSD3lyCq zP&7@T=v0BC(*%l67bu!8P;`bs(U}58X9;yh`(&k6av+r*)6=qjL(z}vT6A_+PQH?& z^RsOD7NO_@=R?tjb||{Y4n-H+q39Aj6kTeEqRZ@1bh#ahuCPPVl{Q6J2^3u|P;`wz z(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86x}XRbcaCEodQL72^8HeP;`$# z(Y*pi_X!l;FVq#Co0X2tfm9AkpLIMh6y<*xT>gYDD<@w`(IZ)Q*;b+GQRhR^V|FNd z+zv%g*rDi2I}|--hoYzLQ1px)ik`JY(Q`IM&kGd2AW-z8K+#JAMK22!y&_QbszA|e z0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keInEqJ(QK6 z&Vf{BPuHS{L(y-E)TdcF`AUku$g;1u2}NHzABw)RL($iEDEh_@Mc>+?=sPfucVJiV98fw4I`&Kv9E0QAwbvQJ^Rj zC~6WYDhm{~5h!XaP}EMKs9B(>B2d&`pr}QtE1Hp&x@?;(N?&(v{5%wu(mh&-rgHL? z6m@FKmKYq0Iy)bVX0bz27dsSnwL?)iI}~-dL(!~uD4NXx(Lw@6eFcj82^94gC>kJ8 zw6H+YK!Kt~gu0??Q)!zVNacz2=(^Taf2O}!dfLBeQ#tucik583_8Ah2mU2E6Ep3OQ zW$aM2tR0G$vqRDHb|@NThoTkiP_&{QidM2IT3MiI6@j8v1&US^C|X^hXbpj)H3f>+ z5-3_*plBU|qICs|))OdNU!Z6MfuaosiZ&7`+E}1y6M>>l1&THkDB4`0XbYjPXz`}f zxjB%^QRz->iBR-l`f|vYP37b(DcZIvyKiVH+RphkeFw5veTc!8n`0!0%A ziY5sZ?IuvPyFk$%0!4cY6ipT=+Do8lZ-JtHgu0@wn@S(&Kq|MT?=RXW6rGnok-cwI zIr&P84s6QW?ih*=ay}FtY=@#l>`-*59f}UKL($=OC_2IpMMv79=qNiB9c@!|j6l(` z0!7CO6df;6G)1831c9Qd0!1eZ6rChcbh1FvDFQ{)1d2`-C^}7`=yZXi=>kP(2o#+u zP;{0+(b)n;=Li&?E7TS3-&E?C1F3wMu0;ogqTa1f*qX}8S5kCQQ?~wyP;{~Lq39Aj z6kTeEqRZ@1bh#ahuCPPVm3An)$__PqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SUL>WVIC zDoxCRROU(#s4omfr>1Ms!%gMnD=B)sDLZNBQ1pcJq3B6F6g_2!qNnXp^o$*fp0z{K zb9N|t-VQ}C*rDh}o1&Klie45ddPShC~6~6)K;LVoj_5u zKv6}YsJ%c@i$GBafufEAMOC4$=*y;3VRWwOt91GKDimFp9$nYU<>V_V>Qc^njtxa! zoexFb>`>I*4n?!tp=dTc6wPjjqB-nPG^ZVk=CVUk51XQ%0!6(9islw5>Mc+-k3iA9 z0!8x)6!j4(nqQ!30fC|g1&S6DDC#Rv)K8$Ozd+Fdfue;4iUtZ4Eh12~s6f$T0!51p zbw!=arPXpEm5tLg{aMQOXZmxeXZlN&%gI+#v`jhMY1dG+tn;C0IXe_BZ-=5mb|_lG z4n-^4p=c#L6s>HBqE+lrw5mvMe7R` zZ6Hvzp+M0_0!14O6m230gitiZ`B1cj9g2q9p=g*LiiX>vXh%B~?PQ0d5q2mVX@{bn zZHjggC>kYDG+Ll&j6l&?fueB&MY{?VjTb1IAW$?>plFgn(QX1oy9*TUAyBlZK+$A@ zqP+x)_7*7GN1$k5fuj8ciuM=kinc44p3Q+&7Ee#h28W^z)7{$v<#O_s6dh8|zMT|` z4s|{h9cG83!|hOXgdK{Gv_sKRb|^a94n@b(6oH}>1d65#6rCtg zbdo^P$pS^E2oy~dC^}W3=rn<%(*=sA3lyCpP;{n1(OCjTXA2aaBT#g%K+$;uMdu3? zT_DsI9aJuL+bvggRX!UJ4n+jS5-uY1UgB^-~v_sKPb}0JU4n@D%q3BmT6#Zt0qTlUM^oLE+p8`dNHt~d- zqM|@igFsP9pr}!xC=)1Z5-2JQ6txj3YAaCGPN1k+pr|5H)Lx*dMWCpIKv745qN+eq zO`xcgKv8F*uIQU`>C+rY<;?V1$8ST?{E5^oZOX}4Qq;Xo*1TURn$`JGG@BiYX17Dp z9Cj$0(+)***`cV19g2F|p{SP~isrT{>Mc+-k3iA90!8x)6!j4(nqQ!30fC|g1&S6D zDC#Rv)K8$Ozd+Fdfue;4iUtZ4Eh12~s6f$T0!51p6fGf8w4^}MQbJu(*EXdAIgrYT z^i8te+SH%vub%GFmTpr{zLKKl+hiLa5Q+vlABtA6L(z(MC|b!5MJwB(XcapYt!js& z)$CBTx*dwvuqj$oplB_DqO}Ez))6RLSD|0K5GdMGplBO1c&eZc|Ra zlA@t)vQrKUMZ=sAMZ@h-w4)u0cCtg!2s;#wv_sL(b|~7#4n?EvP&C@6XpBJ7Sb?H( z0!6zD6pa@snjla#QJ`p&K+$djMY{_W?IBRKr$EtUfug+xiuM*L+DD*hUxA|i1d8?- zC^|r(=s&L(wsIC_2^-MaS8p=y*F6O|e7K2{uJj1&U4-C^|`?=wyMSQv`~p2^5_wP;{C= z(dhz3(*=so5GXoRpy(`tqO%2x&Jid&SD@%Tfui#TiY^c+x=^6#B7vfdg}S0c+msp( z%@y6AzI1k2C|Wd;x};4x`AUkeXp_x-cqqEk`A~F~9g42DL(w&MD7w}TMc3J(=z2R8 z-C&2J8|_eZlTFdh0!6n76x}LNbellY?E*!22o&8ZP;{3-(cJgZ7Plk=hI zXFC-AVuzw%?NIca9g2RpL(w00DEiY5MTNHUygd{ZZHgKMib?`SjRHlPKv9!GQCXm< zjX+UbfueQ-Ma=?56@jAm0!1wXMI8i+Itmn31&V3{MV$nSItvudB2d&tps1@*SM+_G z((^fx%D(CH^Ft__C5>)v%gI+#G<)0Z`(s1V9L|TLIqgt1mmP|F*rBMW9g2F{p=fS9 z6!o@4(L8o2n%AaiK7pb>0!8x+6fGc7w4gxILIOp71&aC!6!jM<8X!=#ut3p3fucnO ziWU_pT1=p5ae<;G1d5gvC|XLOXla3>Wdw?r73zv+ZCjf4xLna1O*x#|+SZ@x@14eS zZOh45QnX^*Y?&#cXeH-E(aLrxTEz}UtJ`=6(9g5bnL($qcMe7I@ ztt(KpoPQH?&tJ`Mnr-hWiryC} z`aq!QLxG}?1d2WuDEdU8=u?5B&jgBQ2o!xTQ1pdB(U$^6UkMa_El~80K+(4XMc)Y& zeJ|7%J=eChM-HU2b%OJJD4LPJH2Xu_a`KfF{n9o&b$TfJ)%j5Ln;nXNw?ok%b}0JO z4n>7_@ytCG741;eV27fT9f}%liZX$sCV`@|Kv5fkqP7A>?F5RN1&S&HMePNOS_FzZ z2o!Y`D5?q+)dY$<2^4h}D4Io}sEa^RSAn8#0!7^gie?q+ihgQax-$n-`6E3p`Z*M> zlg4cA%E?z!G*`RqtusSW59dQsPdgO#vP03_b|~s?hoX7xP&BU{isrLJQ6D=L&2Lk* zfI!iL0!0f66!jG->L*atU!Z7!K+(biMFRzj77-{~RG?@vfuh9)ik1*4T2i2BDS@J; z1&WptC|XvaXgPtRL(wDB3`vXhVUbjRcA| z7AV?8plDNpqRj+~HWw(`LZE0%fugMhinbOg+D4#gTY;kO1d0X=6m2h1G(@0i2Z5rY z0!71wx}ufZmDb9ERMMYR)VOjex+#s}?aIklQZ%w%w##{;XlLg`(Jpo<8fAx~(RL^r zV~3)#b|@NWhoW8WP&D2SMH6g_CJGcy5-8eDplEl2qCEtP_7o_ZEKszUK+)a;Mf(U8 z?JH2UpFq+60!0T16dfo~bdW&N!2(5x2oxPEP;{6;(cuC`M+kLAJGCnvp9879oGw2j zLeUH9LDG@!%E?z!bZooqnhQeFan6UL%s-5`m&i1&S^cD7svr=n8?ND}}nEquZ5U%z;$4OrK~xCKUBc&-AZqS5Cf?qU+ja zKVB4yu6I5Z-C&2J8|_eZlO2j~wnNb^b||{l4n?=wq3Cuy6y0G{bf-YkT>?dS3l!ZW zP;{?A(R~6%_X`v~AW-z6K+!`2MGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyX#3lu#g zQ1q-o(Q`sw(KYQ#vtOJmYLmWu|JqRWQX=(yyK?fC6usOoTkg_O^osML=v6xuy=I4^ z*X>aBh8>FDv_sKbb|`w=4n^9g60$L(#l;D4Nd>MSbj0G`}5+7O+Fnf_5lc$fl^TKv6$|qW%I! z0|bf|7AP7hP_&3Z(V_xHiwP7hE>N_DK+%!{MN0`3EiF*Aj6l({0!7OS6fG}MG)SOm z1%aX!1&US@>WX?am%hk>R9;D6jqTZ7f2MzHx)!b6Tu#1{qSc$T4%dXDHJlGcYuce` zEjtvgZHJ`=6>9g5boL(%$nDB8ddMH|`_Z6r{%u|Ux#0!5n&6m2F@w7Edh76L_E z3KVT6P_(r`(KZ4_+X@tICr~t4plEx6q9FoBI|vjF6(|}eP&8biXh(sforJogRhvtT z=0Ga5r>}sl7K%>If2?stb2<4+ibgeOn_d@+Mmryh#@L}~tR0HR*`a7xI~0w#L(v2~ z6iu{4(Ih(*?PgQ7yFk$%0!4cY6ipT=+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bf=6ev1K zpy*(MqC*6V4izXmOrYp+fubV>ijEX0I!d7EXrZoX=jPJn97tty`ZE45p=givO#hhX za`KfFO=-?fzabQz;Cv{WYKNi|?ND@*9g0r2L(wUAD4J%6qEqcqbebKCPPZwVE>Lua zK+%~3MP~^Voh?vwjzH150!8Nu6rC?nbb&z8g#twv2^3u{P;`kv(WL@KmkAVIE>LuZ zK+%-~MOO(FT`f>_jZjx~TyyE}97yH3^o?o9hoZ6R9_`xZa`KfF-PoMHlYb_%_4mf! z%D0*I?=mmkI z7lpc_>zhkWH|L6$N^ounMdzn$(M!$c1i^P%VsI~2WXhoZOaQ1rGP zir%q9(Ytmide06;@7tm11Dm1`1&TfrDEe5S=o5jWPX&rT6DXP?Q1rP#(H8Mc)b(eJ4=#y+F|q0!2Rx6#XPn^s_+GF9Jos3Ux)VG?&)NfmD7?pCWoS z6b(zHerql#UrAA+l8wGS6csD+Og`>I!4n^&3 zikbzADgs6A1&Ue(iaH1sbrdM73KZ1@iaH4tbrvX^MWCpQKv7qLqHY33-35wf6)2ib zplEi1qB#VL<`gKJOQ5KSP*?OvbLoT}NTo47NBc7r4a|S6v1g^6d?iKmRI=;t3`O%g zAByI)Ls1_)6wPmkq6O?ww4fb|7P3Q8Upo}_vqMpTo1y^%MGFfQ4HPI^M4)I`Nr9rJ1d5gxC|X9KXjy@xEKszHK+&o~ zUD4c?(#tuJ$~Wm+)VmVDPrs6n)hgxWD=Av5lKp&lC|cY3P_&L6iq^G5(Ry|$THg*u z8`z;}Lpv00WQU@S?NGFdP0^+TMVko}Z7xu>g+S4k0!3R16m2a~w2eT~wgN@l2^0+$ zDB512Xox`34gy6(1&W3V6b%NicYmd(P?%lI^7OM)9p}nh8>E|v?)4Epy+IYqH_d_&J`#+PoU_0 zfuaipiY^o=x=5htVu7Md1d1*dD7s9b=yHLgD+G$J6ezk%py+CWqH6?-t`#V{PN3*| zp|0qJO6k%ZNM%y`tmD*B^ivu)RLaR$Qglltd+ec5bgT2B=r%hP-EN1XJM2(&ryYv! zvP03`b||{X4n_Ccq3AxFqWcAk9uO#cP@w1`fue^6iXIUtdQ_n3F@d7T1&W>!D0)($ z=qZ7srv-|h5h!|Apy)Y)qUQyQUJxjHQK0B0fuffMie3@wif*cuzRH1AmQRN}%X#fue5&ioO*n`c9zedx4@K1d4tXDEdjD z=x2eVUj&MN6)5^mpy+pjqCbSXqSq^>#d9E)$J5vJ-v~uprf2$pR?5j&QdDZ6ZT@&D zYHa^MKGVvAW+m%pr|TPR1+xb zBv8~@plB9>qAmhOT?LA|2^4h~D4JEEXf}bO*#(N`5Ga~cplB|Eq88_Bldq&`-S*jgPluxQoDW6o+o5O!I}~kbhoX(_P_(ffiZ-!B(WZ7N+RP3` zo7)s^AyBlXK+#qLMOzCLZ6i>$tw7Os0!4!binbRh8X{1%gFw+xfudmoMZ*P(b`&Vu zNuX$iK+#BnqMZebb`dBVB~Ub4s4H5#eW}eexuOfxwP>AClrBMyW7?OKucT;v`)vN_ zLeT{0L(xP#6iu>2(QbAq+T9LCd)T39PdgM%wnNcgb|~80rf465qJ0I5_7f=DU!dp! zfuaKiiVhMeI#{6S5P_mY1&R(6C^}rA=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZ7}- zK+y?8UD3GqrS)+MW@-J=yW?2 zO}9hQ8FnZ-(+)*v*`ercI~1K`Q*^FC(Rl(z=L-~FAW(FnK+#14MHdScT_R9)sX)Z*E^szLKKb+h;et6pHR}J`~+)hoZaeP;|E)ite#P(Y<6g??W^prr+(*i}$2oyalQ1qNY(enaD zF9;O9C{Xm0K+($rMXv}Hy(&=jnn2O(LS50V?MtubKq{Z5%g=40s9X99$Q$j;$yZYJ zPW$ZFS3=Rd&WED+>`?T+9g04%L(zwJDEi0_MIYOt=o32>eQJlI&uofj2o!xTQ1pdB z(U$^6UkMa_El~80K+(4XMc)Y&eJ@b-gFw-b0!2Rw6#Xnv^ou~zuL4EC2^9S)D|)MasmH6iqWjae=P$El{+KK+&=SMau~kEiX_sNT6s1fua=!idGUR zT3MiI6@j8v1&US^C|X^hXbpj)H3f>+5-3_*s4JSkrF3}?q;hEbUdIJO(YJ}zIxXeo zD=FHbC41uSP_&`*p=cvJ6m4vWqD|~jw5c76HnT&~=5{FB!VX1S+M#GGo1(1+inb9b z+E$=wJAtCX0!7;k6b%t5+CiXbs6f#$fui98MLP-(Kw;5XuX!wH#v~X3hi<@>xZI!)1&KMTgu5-QZ%V0>-1hI+Rgb;w7VUO z_OL_Io^~jjY=@$~>`=6~9g6m`L(#r=DB91aXn%pC0|bf=6ev1Kpy*(MqC*6V4izXm zOrYp+fubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vmDFQ_&2oy~fC^}J~=p>=8XhKVA z$s9;!gLEyL7>e4bN7pB}l#{Qd=(Lt>%MU`)>CT6u>2@eO!wyAf+M(zyI~1L5hoW=r zP;{;xiq5k`(fKw-7YGzxC{T2fK+(klMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)dEG= z2ozl_P;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-73@-O=~Ibn**sFlRoQsYAAX&U5jpO zDJNe^(OoUsSs#U>yPXe3_t>H6UON=sXNRKu?NIc99f}^bL(xNaD0<6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0K+($rMXv}Hy(&=j znn2O(0!42K6ul`>^p;RpbVp0+{v1eUk@QgL&QSDo`c3<9x0I8wr0D&Y?1N82(Fe|l zq7Us*^pPEkKDI;ACw3_M)DA_T*`a8L9g04;L(vyDMPCXOeI-!zwLsA~0!7~n6n!U9 z^u0jQ4+2F$3Kab$Q1r7v(Jul;zX}xnCQ$UdK+zupMSltu6*|Pzc8ZDuMGXQ)C4r(w zp|0rNmQuSB+pY15(pO#jM6 zYJm>r`=6=P0@A&MS}&3wihTGB2cu0K+#Zv zqG19>!v%_V6e!wBplF0Z(MW-!odt?^5hxlZP&8VgXpBJ7Sb?H(0!6zD6pa@snjq8_ zZP=modJd$rTl(DfMxm&Gx)x3BP)@#*qCGlfzkd^o_H;fJO}0bPUUn$j+YUwh*r8}& zI~46_hob%MP;`JDiVn0XI!K`CV1c4T1d0w7C^}4_=x~9eBLs?$6ev1Mpy+6UqGJS# zjuj|6PN3*`fubn_MJEUpO%*6QQK0A~fufTIicS$InkLj0?be~x>)Tw>)bw?<-9ynm z=^GzU?NCm>lA<#@WGjCkiq3RC6rE*75*`b_#B}Mmk$d33i z6y4{1D7xPcMGx4a=s`OaJ!FTXhwV`Gh#iU^wL{Tkb|`w>rsxTQq9+B4o)Rc}TA=6| zfud&xik=fFdS0OD1%aX$1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2 zfueVXx}v)~l&;KyRJKh|%kBw9ebc8P-|J9LzLKJkI%H4%9Ev`6J`{aohoVpIQ1qD{ zie}iM=yN+1ePM^9FYQqDl^u${wki5Xpy*qHqVEKXz85I^L7?bIfuf%TihdR-`bD7V zSAnA61d4taDEdR7=ud&7LdSU8PEk>ys6n8pBv8~SP?QN2H3<}zg}R~-I+VW4fm8;k zJFyQ#(Lw22)TU!O`AUi^9kW?}3q|dn4@E6@DC%H`qKhoV{R zP}IeysH;FxH-Vz=0!6b56wM}3G`m3290Emi3KY#HP}D=9sHZ?tFM*=D1&VqL6wM=0 zG_OF>d;&#%1d8StC|W?EXhDIZg@n4Ib{$Jg=Rhhm(w~~%+_C;l|A}<>*0*Ch`AUiw z?wD=;M<^QTd?;GP4n>RFp=dEX6fJItq9yE5w4@!1ma;?9(sn3X#-?alfuiLEik25B z8YED(f!zhwy;Cd zmUbxG$__x-Bv3R$ zplGB((ar)zy9gAG5-1uiP&7uMXskfdIDw*F1&YQC6ipB)nkY~-NuX#qp{{6?j->~4 zAeB4Qm(Df~MYE-6`nz{5Ctpd?ULCWK8bZ`=6?9g6m|L(%?rC_2CnMF-lU z=pZ{39c+i9Lu`r;6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8oR0!1eX z6ipQLeV+ShoW=sP;{Ohiq5w~(FJxWy3h_q7ulicVmlOFVuzwjZHg`vD7svr z=n8?ND+P+K5-7S_py(QbqH6_;t`jJ_UZCg(fub7)if$4px>=y;7J;H$1&VGHD7sys z=njFRI|YjF5-7S`s4F_NV`-xtNM+u1`8g{T?V6sW-P5t0d?iH>bj&7{L(zlIhoXn< zQ1q}JiXO2;(W7=Kddv<*kK3W>2|E-$X@{bxY>J*1D0)Vq=vjfH=LCwL7bto`py)+` zqL&1UUKS{NMWEy>WV(@Sb8%DQrRb;jh}>~vFVw9 zbG4j&B}E;o*`Lj!sH5|tsA`9znjMNd*`cVj9g1eLLs1ty6m_*jQ8zmjb+;*+RiJ1# zfuh+3isld~np2=?E`g#R0!2Lqih2nY%`H&WTcBtjfueZ@isln2>LXAzzd+Ff0!0f7 z6fGoB)K{RWpFmN6p{}TXwbZ+kEBZ8j*0H5pf2Mz7x)u$nmXoifXwho6YD*|u%=u8X zxE+d?utU+3b|_lP4n<4bp=cR96fJ9qqUG#Rw7gBxAc3M41d3J^C|XINXk~$-RRoGw z6)0LwplEf0qBR7H))XjOOQ2|NfueN;iq;hZZFHkf=plG5%(IkPQ-2{qu7bx08plDB_u4waW>FOLv<>_=S+9DJc(mmSb zYB~8ziuSE$&(uQEe$I!Y{q0b6fE|hsv_sKBb|^a74n>F9q3BRM6dh)VqQh;9ju0q1 zQlRK4fuf@YijEN|I#!_QIDw+$1&XE!6rCVYG*zJJM1i7{1d2`;C^|);XqrILsRBi( z2^5_!P&8ej=nR3PGljaMy{n}kav+tJ)8%KMP;_=0XI0C|S5kCdHS0P{C_3NyP;`ME ziY~N6(M5JBy4Vgym)N1`Qacn~W{0B7?ND@uP0^JCMOO(FT`f>_jX=@00!7ye6kRV+ zbb~LubK+&B7MRy4l-7Qdbk3iAA0!8-;bw%e? zOUvd!DjTHl-aj`KeV@J@a(}g)d?iH>SF>%qhN4HD4@HmKq3AI?6g_T-q9^Q7^rRh% zp0Y#H({?C&#tuc#+7vw}Q1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(Uofx$==vzA!eP@TF@9j|ZgB^-~v?=;Y zpy+3TqF)4xeibPCO`zy^fucVIivAQRD%9d>J4Ho-q6UGYl0Z?TKv5=8)Fe<;7AR^X zP}EkSsGUGjvp`Wrps2l2SM*u6^l%QOG9X=xW`v@?=^m}6R!+W>qFOEcWVTS$$@x&! z*$zds*rBM49g4czp{Sc3in`mOXjVHE&1Q$9*=>sE5Ga~cplB|Eq8ps1ffQGbD=0Rlw}3lt3$>WVtn zN-eYJimpu$sH?U5GySRQTC_;5oO~rkOVqOdbB3ZNoexDz*`a7@I}|NrhoWWeP_&#K zik7!S(I7h%tzd_u6>W-E5-3_(plB6=qE!WoRud>%U7%M^-9;G zEo$ZDD=FHhmQCsrinet=6m4gRqQQ13+TIRDL+ntrgB^;7+M#He9g2qAp=d{&qMZba zMhFy*6e!wRplBC?qEP}xqXmk_2o#MKC>keFw5veTc!8n`0!0%AiY5sZ?IuvPyFk$% z0!4cY6ipT=+Do8lZ=tSet6J%_97tts`o8O}L(x^~?roo1Ir&P84ya|f^$JA?IvFBq3AF>6di7dq9g23bfg`MjkR51&YoPC^}Q1=q!PvvjvLI5$cNe ztCil)fmFWBXXE~%==U_vt(B9nLdQZwX7z@Lg(rQ9SVhR)z7Mh!tB+BI~NK)s=Ie76namMauSREG{K6h>7qS+P(U zSN(G3LSbTcvDFHNJ*s=HQ7G(Py=SdLVgG7*-9q8u>bmO}3WryxZdfQBU43QaLgD!8 zT$>dNCsv1VQ7BBSUba=CFunTqHig33)g=ZO3g=h%8B!=*T)l5-p>TP%?T&@Q)z$S! z6bjc@PujUqxVie;s6yfPYR|ES!rj%Kb}ba{uU;{sPcN3oXvjJ3Uswe*K%?O&{=KjrA)V(p2y^N&!mmj0ZPql>ll2SprTtfk-Se`2wg zeyjGhVlDk%+v&wx`puGO7i;NvyPaRGrQfb}aj}+uzscprTKWwGR~KvPJHD?k*3!4^ z-dwDu@439aSWDkDcXzRtzU%4!Vl92!%EQH4`o4q5i?#HHC;^{}0h;e!;A4|3z)cRsKxt!Lgn=hdtB zEp**JKXZM4=0Rr;+WDz-S6z#dgh0xpLuVO)-(4FSbn$k zh9)2Q>5umn3tb21hteB5xqc|CjGp`6U0dI|`-V^2ul1d~>c(ql`z85p{bqhDy=w#KkK5p$XKuPQeNeN?@((OE zy!8#;y=sr0ThE;H;_u(&xAn1=`kCR*ym-*GuhQ+7Rr)Qm;wr6Y7VEI*g01h|4V!f6 zU+8*y9GO->l2sO;_WV|@CpH-T&~~jSI$SfR{#It3_1eq%d)6+$KT7Y}qmDG+wc!q} zM;abny?$g^?-z0x`E9oGwQpAnUFVGxe>$ z9(~6Px#~6I(4zU9%6}m=Ri_;J&29CY?Y?iOJ)1tDP1WBYee9?FgPgymeMdjFS)uEW zacF0UKDg+e$MaX4-qiJ%ep0`!FaG_cyYv6bZ|kXFfA`4Vg|2(&r_x9045wba`0K-x zovdx^g;}r4@3zxFSwpF5)`#-{NdIJ| ze4L*Dx=jCM^OV{Ziq+ygEuET6Ewi<3+O=Bj*tJk-=v`=TUOrESLa9rk)UtH*GR;dh zuh}WTmc@^xE7@X&RGNy#H9Hma|0ws&cmMoi)TUFhxw(EM^|tK`r8Zteb94LVO7oKW zOSS9zKfF|P{!;(&b}BKm`kQSZuQH$MRkp;dZ2i%Hf0Z5LRmMwo%nxP%{(e;3=kH&7 z%eB`3$bThwil1A&k2X$m>$d)X`oDCa@Q?rd$K7Y{{KHZhmLF*-{+izu#r%Ky%ce_uzkdD459z<-gmL{R zj33&6{NM>ghYub%e(c2ILnjU&)_>^uJ;zNPo5IlH!zPU%KH(pJEWLdG(o6LpH-6;k zkrPMmHoVY(#Msfp`wtm4e2@P9MvWahWK{nNBZiD0-hce?F~cVenb3duz`+wHP8v3H zZ2yU4$Br60V#vrb6Z-Eobm-tA<45;jc);LA1`ixCaN)rV4@j|Z9{Y|NJ7##_;X`&9 z*>~Xq{TAt)ez;%$!~eq%^&dHA=%`7ZLJa+u>zW;Vx>@jhC>rGO>MK%~ecIW&ypU{8faYM%Mvf89EgEz^4E<0^7YSM(k z8?Ctbx{Lj1e3*6{GI4miwF-s$2YSazV}>p=U_ig2iNfGv!*?7qY1G8Q6Zaf9d_unw zNm%~j8a8sw#C+s;mm9CV>frp{9J=z@(WA$X$y<&On33sK*Ha;XjFh$NEG<&ZvQGce z|FU9JX{TaVE6tjJL@_ENkkY)tWl@>Q$QDBS!uzTI0<8yI1~vq&Q2~oc`4z z>yiG|RIJbRY6s?TqnPy=kk!&#{O4Y{*UY@|Ougp6>xFw}J@R*Yj{IlXv-Riu&;Cqj z>izjozgb#8SUu_=tA6?W-aEbT0|v}7V8MJO99$7?Un@&NWv` zO*1M&qZux)K@1a~@ zdN%z>*O$1#{^J|CZBwbTY}O^e*7P2bb(u43>n^E7{r;jS-i;?mqd>)k8sGDm*#?b&*z{?ETg&%^~{CO^{uBCq-H z0{7RhWq<9|-+9abUANEQ`9A-jrS(r;7uHHo?dlKMTAw5S&kxxC?Ll!|4m=Y68!ro; zdM=b@3;)Ao@qFg*<-b1`@8rM#rzfNNqs40d(PG=Cz8~(ulQWo|Djv@zvLI183^`Rr+w>hCaoaJ96E=6KC$gs;%$S%>Qh%_W94|z-;Co zl$55&yVo|qMb}I>aJpsxFV^llI;u17`*o7ZFv*~$?$oJ32~Y}cX^WPYQloAZuV6*$ z?(XjH?(XjH?(VMVzO#Q%4!Qtkv#(Kgmvp%*A9TBrs>U^j!bui~WD`#kjfB z-Jp4f=RfG3r}^tFtzXBBYpL{ZsY~5T={sXK8nV`?p*@DxYeBDW2`qyXD!H z2DLofr*FJw@4ngqC->-Gyllvzc%7#F%A@kPQN%Z1)a~2vBShE76-YsJAvC-rB&{w~#&_>D9)~ znml>;;w{DN_V$hkL|D1y0;CUb%Uf=FC%wIo!L1*R^dX2>Oc%NMFs8RsJTu!xSlOxR zgV+4R^ns1@R%&@;>GF7|J>&IzwO)=vEoU?h@~+Yak2A7|*}etcf-0 z8>XgA96xIOlyN(Zo-%6E)F~5-UtqdQ(z{RJVKm!y5*Mv^>!nTCfAQ)qzdX=-wEpV) zwfst&lIWV@L$(+-VDLuG=cTJQevt`uJU941XV&D4)TQ}<|BG2u>jfDYl7LHBWAi&8 zti@0vHvdK((tP%g`FBh6tM-UDk?_VP8Q5}}@^9MaR~pcI;RdtND_+)u!#i*4+w!KG zTK(~YOH(Vz^s9(>4M_`!bom}>*0m1;F^ZIYFeGSw$d-6IL|ZrYH7Z0 zimSHe_9T51Rr3qdjaR;4v-PIpgr?RH(QMcF%JKGGD+Q+f9{RR^{L)9acpE*v_f`!} ztsI(W^N_Bxc(*MdC|69=!1!ReTKcuTO8S7uN452a%XPL=>*XmtG=CUc2{g@SV7BYN zPr4wjFx~8>k5+N{@{98uO2>H5P04C=ay_OSoOn^MmJeb2KzQ|539e+Y5CQqt2cfrt-m~g(uY4@)&eD6zr}lKg_mxj(rY!p z@#YsLIB{0`{1VT#e3TOE;{0?Ioo_3r7a#Jb;t-!)Td6g*T5I9mN-TXAPj7$5_EV?N zZ245lMdsTqss&Tar}*@nviUOPD|}@7#?2AMB}yNY;+ff$wW?}rW!2Q`%9Y-fE^_n9 z>2rVc(Z{_h{T3TG5TBF(>jTRuWf>Ap+xis>dGo@x0&HWk-#K4Z2U|E4%2UAL_t z=JecJ>uu6yP``d%@^|BQZ|ai2AGb%}p1r$toj!ij_|Y@QFWaTtbx@*m{q#sbJpxTQ7YEh>O*F4Hec~KBYF(9yRK} zpYPpeZN0~eO}wU%9?kc)J z+IqjxZ;O0avG~9Q#Ns|-^RGPL5smw%&A-Cp_g>4d+V8a%%P8kNq&v0Twz}Whdf%}1 zu3=N_4KLp zVEW`PLne{gqw}}X*VLw;ldLKC?KYzOhyiP_ zSJNi_sAFTP+R(XvuG+b4=Pk`wJAds0wF}lRRJ%ys;fO=pYX6N%ynr-KoUzb17%}>So-_5r3%dbj5F;hIX z{`^JWrJCj+&x@Dk-SUo`Td5}fB-CtArJDTH9Ia2KnwB@*97{DFTVI%-EB%j;Rw@1D z?d(sbnmKFI592gn3)w^G^zmD2wpYln-Rpns0smuf{6F^p`cZ);XVxq^ZnpcE=?4gA zTg~@E|8w6n{bv53k6Mb)j5Rg+C(x_uhgnug*Ka=dNIdd!>wHW<0K7-KUh}>pAJhIP zeR%Wkp03}#*UQJWuSp-)e0(DxQ$HeIU-@`h9NVN1Yu<~;ac~^R#BsNLOy{4FkBg+A zM@k>Nx<%7ZDy5G_UHTcEeD&9*4{WxQk8{T{{k%_2T^ft!WBL*1uF>=FvHW`JCy<+u z{o^<=jvK^rlQ@oz(6`FI9`|d<$ZS?e@P#Jyi1*n<7(+QL*8r0@qqL($otqh zK9+uzDesr#*dhIBcis!eapQEI4{dzy7^({B5~nmzOV&t9L7o!{c~Rx}x&yA0Njjnu`5u96R+c_QG-8G+m+j^~c8X ztiHv*JdPi%QtWTz*fm}8`Sn+d_tj^i^4dj5F48OOOM6nn8aZn=H2C&ux-^cy0-{?&2( zWKywzjN=MZi`_4d(|0cRzHz*5MzJ4`<3F>C-FBDaIC!_>xM3WR*rV8|#__qmiv4yR z=h?T|OT=;O{foUr94|Pq*w@DKvxAHMa~!)LR_s;dIP-{N?;poIjw<$}ajZGE*zMyu z^!Q?rjN?%!7W?!#zHoA}-;LvZrxkmtIBt7Jv3H8&MQ0WJ`Z#`ZPO*QDV~_KT-9L`I zTv+S_<9OG_#eO`Fb(a;pV;qNFQS43Pc+6GBJ~NIlT~qA$(wxX=^DUN(+no+|d#I9~Qlv2Tv!H_sLO&p7sevDgFRxW~)IJ~WQ^y;|(2AxX7I8e`onoIG$JgE~_Q!EtRIQC6HikM$MB#!%3ihX1pA8IW2^Kq=Ezd|{`{=9MA zApMmNd2bWPQ_|npFFtTu)|)jb_(&YvDvii{tj5OJDw&S<^j#y`iT2m>Dx_x~H#@bkDJS>z8KpUFYULE`NPL{h`W)sp*vF z=SPnjGkyFnv%hro^n5=$-ca#M|GP}eKmQzWB3+W2?qkyr>yA%<)HB<=nJ|6yM=Tl(Er+&9kWq`OA{c}gFu=BLHd|MTmWiuu1@FTX55 zEtCFhNdNtRyI{)+i&i*s*`MSzaE2RI@-P@Wq(|`GC>&dk>=cQx5?(*y8|ML4A zmi}`Y(z7*#JJi%Xn>={(+~5>ue|vwWxA$2J`R!#l-rmOPdFP~OYvxRUb=&^41<$6t zI{$gSlUAv%>5@-~C$Bdq?b+Y&N4wTG`^@h*ckg%i^t^M@vo$xRx0fAz^0HYe%>MR% zn(gi7N1@){k?DEo|1YmM`%mgOb)ULo`a`8YeS7rGUvy1hDeBQQ z+yDFYNv-cnz5Dj8WeYJn2_6;D@fI z$?J?9Gjhk%>;8Ia((oPE9ywo?dchTEl+0zcjY_Wv8XJ_7C-? z?V4Yf&uUm~)bOo`Z8&!1m_g02JNSnON}I1eD7~Hhx`ThIFKyEDx&wb%p|oMk``BRk zdM)oEzrW!v?_qFye{22ctidg34IDn;KWFv-&snRqoYk<{D#QECcDaV8%hj{xat-~Z ze$a|7ubVE{pygZM!*avB{^va`)$$&OrpvY1f6iK@<*bEI@&(`>4#?;3NFG<(+6FB@~=G<((5 zFBfy6G<(<7FCTNkG*_yrUm@lKY4%C~sA|ml(_FcxzI)91((GGPzhcaJ)9jc2U6z>h zq}h}%R#WV`^G=tmXY9H1P8Y0K>^bvJm#lZ}&UvScwo>dl@=lknPwY;4rwg}o?2dV- zOV>AchrH9p>leFy-s$qK61!d6J=5h|HFn#))8$(&b~W#G`TECh%sXAa)nhm0oi5)R zu`79}%eQ9iHhHJZHz0O7?{xVF#;(shUA{rFOL?cuH#l}(+P%`{8xp%V?{xWw#!d_x z>g$&*J)W-r#$&RdrJDcF+{O>mXV?0*Dwn2L$U=sfA5WBH2RRl2xoz2>CGG64g(tWI0*LwDOnfh0Q{Cj#ER(^q3)JM$8a0GiC^x6*GkF z5;KJC8Z(6K7BhtG9y5gO5tEQTV-vDhY(n;qO~^j63E4L`A^XK9WdGQN91xq317j0% zP;5dDj!noRu?aaeHX(<_Cgkwggd7o@kRxLga#UsLxh0Q`viBm(!sWC&yX)!~{=`lmd88Ji1nK47i zSusP%*)c=NIWa@XxiJYjFE%0P$0p>0*o0gdn~;lQ6LN8ELN19-$fdCfxhyszm&YdL zir9o)8Jm!+ViR(8Y(lPyO~|#e3ArvdA=k$yLMiKP|O_20Nq zz70945OP?4{+3FXlZD(-&VL_WvyeOE)DUu4%n)*S%n))<%n)*K%n)*4%n)*a%nqJQ16aCu0-xRBS??j!noju?cxLHX+Z& zCgl0pguD=&kQZYU@=|O)ZbnR zSu@`!d9#w`WFhaCH%t$2n}xg=r-qRCV}_6qVup|pV}_8AVup~9V}_7VVup}UV}_8= zVup~YI%5OL?_(44Lu^8Rj7`W-u?hJ(HX*;n zCgj)Hg!~qpkl$ky@<(h!{)|n?U$F`KJ2oNz#3tn5*oBa{OEc5;-?%|yQvXh~km^49 zHl(JulIhg6t*@`IEuY*mJ=)5TX3Dj3_M&O0yS;7fMbb`p%PaQ6X{Wp84faB5r@Q5i z_JV1ryX94Tfwa@z^0xN;X{Wp8?d5?uiRB}j{bP=IV4(XCEDwK0bm$Zve zpF_H&iwUJ1(j{G7s7oO~)>%SGe`|X4gPkRX1SI{H`*pRYI}(uUwfXKzskTtGcfL2f zRBa{m%8Hh)Ex(z*NYt!oIp>F>kPAG*qByErFt80!3>Jg`#C@OX)j&(l@r`o1(6v=!r~fo!UzFl@+a5TV5=E$+KC} z`pyqU8`z;}Lpv00WQU@Wb|~7|4n>>Tp=eV(6m4dQqRnlJwh$=VQlMxnfugMiinb9b z+E$=wlt9sT0!5<*ipB^OjTI;wCr~tAplE_X(L{lw?FEW<5GdMFplBz7qDcZplLd;V z2!*0`YfD2Dkm>_z){h89_vPE7skN2tD=V5&Tb?*iD4OZ~P&CU9MZ4IcXjeNF?PiCf z-R)4chaHOcv_sKeb|~80rf465qJ0I5_7f=DU!dp!fuaKiiVhMeI#{6S5P_mY1&R(6 zC^}rA=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZCg%fua+ILeb8(rK1v%>VoN!cK!5F zv}*I?tlCQUl@*;qTY2o&8aP;{G6C_1IK^g;qseIvs;H5C1u{~-SM+Di7772RE1 z{&9g&bdU2x(Y`?Tu9f}^YL(!u)MUM#-JuXo6gh0`g z0!2>=6g@3a^o&5!vjRoW2^2jqQ1pU8(Tf5_F9{UAEKu}{K+&rLMXw1Iy)IDnhCtDq z0!42L6um7Jitel}&6oZ}w)#(g;C@#qnvp-Fy;EDszOteZYRmo7cbzuh7JcaaQ1p=< ziaxeO(I<8&`qU0ZpV^`4b2}7$VTYnG?NIcUP0`l^Mc)V%eJfD(oj}p|0!2Rv6#Xbr z^pil*&jLli2o(J)Q1qKX(eDC9e+U%)DNyv6K+)dgXbFL$B?XF>5-3_)plBJPP?Y{9m5UOPYRB}a@AYl! zibwi8kYD zw4FfFXn~?J0!3p5ipB{PjTb1IAW$?>plEx6q8$W^b`&VuNuX$wK+$A@qA3DJQw55q z2^8%t6pGfbEA>b~s{iCa+}I!#{hU9&O|PqDUs=&Eb>$704n?~P_%~~ ziuSZa(Oz~a+S?9A``DpqUpo}-XH&GlK+ypLMF$EL9VAe6ut3ov0!4=k6dfi|bhtp# z5duX=3KShBP;|6F(J=x=#|ji3Cs1^}K+y>TMJEarog`3nvOv)(LZN78U1^sDr20hu zBsMD)<$v|F{?xik_LUW#Syw)_YbZL)`Jw1+I~1K`hoW=sP;{Ohiq5w~(FJxWy3h_q z7ulicVw<8%1d1*dD7s9b=yHLgD+G$J6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Ar zx=EnuW`Uwx1d47ID7sCc=yrjkI|PdE6bePB*Ol%{K&t1|COBt=qA&Ap(Oq?w>?`?Te9f}^ZL(#)_D0;*WMUUE{=rKDKJ#L4hCv1wI6exO1py+9V zqGtq(o)sv1PN3*{fua`#ie3~bdP$(@Wr3ns1d3i2D0)qx=yidjHw22_6exO2py+LZ zqIU#}-W4c%Pbd`KQ&*~6J}Ejpf7S8cP?Z0*$@=%}D%n?7^l@EziEg3j6X%DbPwi0j znH`Egw?okvb}0JN4n<$tq3CNn6n$fdqHk@Az7r_=UZCg)fubJ;ihdF(`dOgp7lEQ* z1&V$XDEeKX=nsLSKLv{Z5-9pxpy(fgqJIU7(!VBIJZz_^R-mX(pr|BJR4-6e779fl z)|G}OAk``Pw&| zDC%s7qB-qQG?z`$+yX`O2o%jLP&A)F(fk5M3kVb~C{VPJK+(biMT-a&Ehf!uQ)MSUEo^~keWrw2Pb|_lO4n=+JP_(igiu&52sGm*IDgs5T z3KXp-P}E+7yivDB4b-XtY4l7=fa(0!8BlipC2R zO%N!WC{VP$K+z5YMLP-wWM z2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoh}rLb}f~*OF*h0W;nZrqL(tMGfI{0 zD=RvuRNg=R_+|5-qn+#gP;{Ohiq5w~(FJxWy3h_q7ulicVmlOFVuzwj?ND@?P0{57 zMOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2 zMRy1k-6>FXmq5|o0!8--g`%@crArc!>SI~a*`esUJnk)3vahV@!BY9r^h3AJiXL)) zD0=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuawE zLec%D(pL#cb?*GVjt_*Q2l8#vN2N;kl@)zfD!1<+iavLKDEh(&NvYH`0jaK%zg+!k zC^|gfyKbznWM5fP`}*?8H9}Db=ZB(>b|~s(hoU*`P}JEDMRVGrXf8Vx&25LGdF)U$ zuT9Z>0!8x+6fGc7w4gxILIOn#3luFPP_(E(Q5S)t#RQ5L7bsdnplC^fqNN0imKG>l zMxdyxK+&=SMau~kEiX{Cfp-|MezO-8cQhhT&xNlcqJksATe@5$GU&+3*qMr5T z(+7m2Ud|6iz3ou6k{ycr*r8};I~4V`Ls36F6s=;1qE+osw3vMe7R`Z6Hvz zp+M0_LZPTfed(SAq`=6?9g6m|L(%?rC_2CnMF-lU=pZ{39c+i9 zLu`r;6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMS zQv`}m6(~AQpy+ggqB8`F&J-v*ODGiWQD0go0jXY{zv{SWC^|5I%i7uXmFz1kI={ZW z)38uq$PPsp+o9+ZI}}}NhoZ~uP;|K+imtFj(UmquR|yndEl_lgK+&}V zMb`-wT`y2{gFw-Z0!23o6x}RPbc;aItpY{22^8HfP;`et(VYTCcL@~TEl_liK+(Md zMfV95-7gf1&aE#Umw;5C&9_D8g`$1)XS4_EE7@08^hkaA`gKClqs|XSkJ+KzP3ZrH+Crc)(%DA*`errI~4t3hoT?t zQ1p`>ihi~!`bD7VSAnA61d4taDEdR7=ud&7zXXc@7AX2hpy*$LqMC9%Y^NywqiMzC zc#7%-ib?`S^#Vm@fuc47MHPXf27#hRfugEFQCp!<^m%=0p%F>Z3i*2-zX(M~=g(;E z%9ZRZE9z7(_g_C0&Efn|)Y%S2>7UyzJ`$lQ{X4wH4n^r7=q+|An#T@B^V*?kK06f6 zZ-=4E~XC|XFMXkme(MFff#6)5T=P_&ppQTm5Ri(eN-O9&LDf1|i~4T_c$C|X*e zXc>W`t^!5N3KT6TP_(>2(Fy`Z>EHS*E*M4WpI|HkMd{!ED*{F7pQkhGG)SOmut3oefuf-TMQaHZ4HGC@TcBtifui98 zMe7O_jSwhWPoQXhfuaoriZ&D|+DM>iq(ITe0!5n$g`!^N(q#!q_5OTY)H@Wdo^Ojb zEmyLytZ2(}`SFpVXe;N3qOI*vw2d8#wzWgiC_5BwXNRKEb|@NShoZ4|C>m!|G+v-+ zf`-b%nn6|+Y}ukP;{g~(NO|LM++1k zBT#g#K+$mmMaK&iogh$jqCn9}0!1ea6rCbabgDqnX#z#33lyCpP;{n1(OCjTXA2aa zBT#g%P$=5FTGR43$zW&4DpY5BJ3ymBS`%8D*3mp9ow6kY86P;`kMiY~Q7(Pefh zy4(&$SJa=`U z=)zF+a(Y?)!{ti$l@&c+E}yw&D0;&Aq3B6F6g_2!qNnXp^o$*fp0z{Kb9N|t-VQ}C z*rDh}o1&Klie45ddPSh{Qk!j(qWtHs^lMxdyxK+&=SMau~kEiX{CffuimLMJoyv^$;j(5-92^P}EB(6wT45v~B`Y z9h&c5cWzTW($D|yUw!X3mFz1k>f5F~d2}f1=loE#iXDnpwL{Trb|~s^hoaT(P_%{} ziq^D4(EvLX4YVm5Bv3S1plFCd(NKY+wFHWW2^6g@P_&Lf(QtvHbp?t>2o$X+P_({4 z(FOuV8wwO{Bv3R`plD-(qD=&fHWet^OrU6Up-|MPP3eRLq`F)FB(`!Wx-tK8$QErX z*;iJyO`GzKV?)ul&JRVS>`=6w9g0TVp=gX9ipJWZXq+92#@nH2f*pz`+7xXsP_%1&XE%6wMGQnki5;OQ2{Mfudanigpty+FhV% z4}qdR1&a0(DB4>n6m8X}^jZQ^?VZ2sxOFI6Jby;pr%fgM%8CwXQ~rH?C_2#jq39qx z6di1bqC@OZbf_JQ4zoki;dUrG!VX18+M(zuo1&uyijEN|I#!_QIDw+$1&U4(C^}J~ z=p=!nlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugeoip~)zI#;0RJb|L~1&S^Z3Pt<1 zDJ?P~DS9s77VRI3=4gJv)~1quWkr{^DX+18D7wt~q3Ciu6kTD5qATrCbd?>7uC_zb zHFhYv)(%D2*`erqo1z;8if$Arx=EnuW`Uwx1d47ID7sCc=yrjkI|PdE6ezk&py+Oa zqI(32?iDDyPoU_2fuaWliXIdwdPtz?VS%DY1d1LN3Pl&UDUC}&s^{dJpG!i~e0e<9 zrjmVSMNhRUAG~8IdfNG+=ovc{J!^-e=j>4Qyd8>OutU*{b|`wu4n;59q39KxqE`iq zUK1#KU7+XUezu2MZS34B_W{0BR?NIcG9g6<6Df&yG=x>3de*}vD6)38y#KU%q zY6Xhw1d2)mMfCzjWr3nL0!0;pq6UGYMuDQLKv7$PqILpB?FEWD2o!Y`DC#6oG>1?q z`nFB!y9A^lMxdyxK+&=SMau~kEiX{C zffuimLMJoyv^$;j(5-92^P}EDHsJB4TN&-cFghJ6=l~SJsr216;;i0)J#UuT1 z@(t6PsJ|VGR<}dZ8g?jJ(+))g>`*k&4n>3PP&C*MMMG?g zh6)s|B~Ua>plEG@qICp{h6@y}D^N5-plCgTqV)xeHV`PqgZ6Z*# zsX)`=6$P0>yQMUw=ICJPiz5h$7}P&7@T zXlH?<=>kPF1d3(~6wMMS+C`vfSAnA41d4VSDB44yXitHny#$K(7AV?BplDx#qWy$I z(YBS+0|`iViTto^R495be-rlpl}h%N6&+kDf0+L9-sYc;J;eE;=ukTp9cG83!|hOX zgdK{Gv_sKRb|^a94n@bXLju$98L7?bFfufTHicS_NIz^!9RDq(?1d2`< zC^|!+=uCm4vjmFH7AQJLpy*tIqVoib&KD@UK%nSCfuf59iY^ukMF&<&4Z9>o*QQy2 zP$(LjKcihzsbpVS(G`{Qvb%+%E1e&TuChbX)pjVl#tuc-+M(z=I}}}ShoT$oP;{dm zif*zgx>=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaWm ziXIXudRU<75rLvd1&SUMD0*C==n0`vbXldeUIJ2mDgSKj<)Nq{-_?GyQpvuuqGv1R zse6Q?=bRskp0`8M3w9`a(GEo~*`erVI~2WQhoV>QQ1qG|ie9%VdPAV-O@X4f1d84k zD0)Yr=v{%L_XLXG7byBbpy)$^qK^cMJ{BnYM4;$Xfuhd@iar-8`a+=SOM#-V1d6^E zDEdaA=v$#s^mL_kQUX%lD&G})CKRofZ;QUGRI;zE=%-5g=DkAE&(04;zu2MZS34B_ zW{0BR?NIcG9g6<6L(yM$DEiwDMgQ0o{VPyZ(-05aDXJAHsuL(G2^7@}6qN;v+6WX? z1d192iW&uqsscrA1&Z1U6tx#9>L5_mQJ|=kK+zlmMV$qT<`gKJODGimP$|8UfK=zr z-@sEZwn7PCXq z;&v!n!lr0Rfuf}Zik22AT1KF#t3c7R0!7OS6fG}Mw1PlUH-Vz=0!1qd6!j1&Y7!{w zDNxi)ps2S%(MkeEeFTbD7AWc~P}EN-6wTXE>auTAG&p~g?0gNyBmGD6z3WvPD%n?7 zw0c8%!2Y3V4d;iVHSJI|zz#(N?NBtx4n>3QP&C92MMLdSw3Z!;hS?OYEl{+MK+$l4 zqICs|MhFzGCs4G$K+y&QMH>nfZ6r`MQlMyKfucK2qz-DRWM5g)VGZS{4-Q3#J3ka1VTYn4?ND@-9g2>&L(wsIC_2^-MaS8p z=y*F6onTXRqCn9}0!1ea6rCbabgDqnX#z#33lyCpP;{n1(OCjTXA2aaBT#g%K+$;u zMdu3?T_8|&p+M0^0!0@K6kQ@vbg4kmWkR9okcQF^2}t#>{6}YphN7!8smmKG*;iI{ zbwhd1!$Q$D&JRV`+M(z=I}}}ShoT$oP;{dmif*z)(am-!y2TDfx7rllCQx*{K+zon zMRy7m-6c?Tw?NT70!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKd zMNbM8Jta`|v`{FzvZ2&B0jaK+X8l#6s9pYy_Dn-1`^t)5Xee)SL@0XE`Jw0~I~2Wa zhoV>PQ1q%Die9rr(d%|7dczJyZ`z^gEt{gZ1&ZDgD0)|*=skg=_XUbR5GeXkpy(rk zqK^fNJ`pJTRG{cHfuhd^ioOsi`ck0iD}kb~1&Y2ADEd~Q=sSU;?*)o}5DG=lHI(*A zK+=s*g7bVRIxBx6`^Sb#_LUX=+E70Cs8IBq^Fz_^b}0J84n=?3q3AC=6#Z?7qJQjA z^sgO?Y8vBldnl^4DXJ4FDhU+T3lx`=709g3E)L(!6UC|b%6MN8WhEhA9WRiJ2D zfuiLEik25BT0x+wn?O-_fua=!ih2kXH3<~;6e#K?P}EzXXeEK7J_1E63l#MgDC#Fr zw2DB{sscr;35B8s8cWq`*k+4n=F(p=g*Liq^J6(K>c08g5gxu0YWUfui*Uiq;n>+CZRaLxG}=1d2uq z6m2X}w245`rUFHq2^4KEP_%_W(Ut;5TL~0xEl{+LK+(1WMWY0Ywi75CEfk8@Xe@1z zfK*53o1Zm9(S_*~T>Y5FO7@i%O=v9dd}1h?==@N$y&Z~nutU*~b|~7(4n>pfP&C;N zMN{lhG}R78(`<@%7ATr7P&7lJXr@5XEP?`-*09g1$UL($E4D7wWCMYr0a=r%hP-EN1XJ8X*X6ezk&py+OaqI(32?iDDyPoU_2 zfuaWliXIdwdPtz?VS%DY1d1LND0)nw=y8FfCj^R~6exO1py+9VqGtq(o)sv1PAC*z z(^y*kw4|ta{$u=WL(yING1~KumFz1kdbzPY=!{VGit|I!t9B@Q%??Gc+o9+UI~2WX zhoZOaQ1rGPir%q9(YrQ9?+FyWFHrP>K+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mt zmjXp!2^4)TQ1p#J(YFFc-w70bFHrP@K+%r^ML!7?{VWuUUTiFFpMX?{WjHT|qVf5U zW`Aj{WM5g)AC2Y1&k99GXv2;xWQhg)eFZw+cb`=6{9g3E*Ls3^d6fJ90w46ZE@&ZLG2o!Y_DC#ayw4y*! z4}qd4fuf!QMZE-ydJ7b-Bv8~xplD@*qP_w}{RE0u5hz+!plCILqW%I!s|ysZAry)h zu9kjEK&pG>o1aCh#UuSK^H{T5$-c6p!PWBI=ZB&p&JRUH?NGFq9g2q8p=fP86s=>2 zqTzNZTGtLmBkWMLo=wsE0!14L6m2L_w2?s3NP(h_1&THiDB4t@XfuJL%>|0K5GdMG zplBijY=@#Lb|{)^hoWhADB9T$Mbqt2G{dH7ra;jw zfudamigpz!+D)KncY&fk1d8?)DB4S)Xm5d{eFTd36)4(IplE-Aq5}kq4iqRlNTBFo zfuchMiVhVhI!vJGaG_8%v0B#G*;iI{OtpOe#i8g}=ZB)> z>`-*P9g0q{L(z$LC_2dwMJL;#=oC8?ooa`o(`<@P7brSIpy*72qO$~w&K4*-N1*6j zfui#Siq01(x0!0rC6g?tP^r%45V**8w z3lu#eQ1qlg(Nh9NPYV=1BT)3LK+$soMb8Tqy&zEZqEINhzFKN`SyI%HzkC0NP;^Q2 z1GZ`<`^t)5tCqW65sF@Sekgjw4n=R;q3A6;6uoVSqIc|2^sXI>-m^o|`*tY$z^3R! zfufHDiar)7`b41UQ-Pw-1d2WvDEdO6=u3g3uLO#|7AX2gpy*qHqVEKXz85I^L7?bI zfuf%TihdR-`bD7VSAnA6ghJ6P)zU@@NcHCo=haa3WB%gN@6}57l@0$^9vL$AW*cRK+!@1MGFgs zqCcyp(-M&C`}vdDU!mxt^s@Rz+E%i!tZ4DJ<=d|bMN2q86fJ3oqNVImw6q`=749g0@4De5Lr)Lo!xMS-Fo0!2*%MLh+IdI=Qu7ARUtps0^P(aHiv zeFcj82^6g&P_(K*(P{!k{RN6v7bsdoplD5jq5%R$1BF6Sm$s#M5|HX6`A=gPYg;_h z@0IUr4{BSqkXwB+?k(V6+1L57B+)6>i9w{Kg?zOtf8ZOcP$ z3`LWjABv{fp=hcdil*72XlFYVO}9hQ3_BFfv_sJ>I~46=Q?#o<(QX1oy9*TUAyBlZ zK+#?TMSBYr?ITdMuRzg$0!8}^6dfQ?bf7@dK>|ew3ltq9P;{t3(P08bhYJ)PAy9Or zK+#b`p=igpr5zKH>W}%4@plSE? z6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCA{2^lYFqjx0jb`W;oKaGj&FXz*0z#; zWkqkcEzf&LD0<8Jq3CTp6uo1IqId03^qw7x-nT>12X-j>&<;f(*`erTo1#wyiar%6 z`b?ncbAh5S1d6^CDEdmE=xc$ZZv=|I6)5^npy+#nq8|i`eiSJBNucOwfudgoihdO+ z`c0tdcY&fm1d9F?3PrECEv=S-R3FJdn*T;9dOMT)t8FFw%8F{*mAAPo6xFtiNAjVl z&JIN-I~3L1p{Q(!qBeFYs@S2Z!45@@b||Xa6txv7Y9~9A%UWW1&S6CC|XpYsEbf2`loH_ zfCQxaeg3NBzoDpSdRhHq?JC(G zutQNdI}~-dL(z&hMLh(Hngoh^3KaDcDC#Xxw30wkAAzEk1&aC#6!jA*T1B8}Re_?_ z1d93#6s;~$w1z;@ngT@w1d0X<6b%w68Z1yWL?{$3(XRAZ0#e;B-xe*|u6U&1xm_AV z+f}l!tZ1Ef<Xe)uDtp$p<5h&VLplFmp(RKnwqXmk_2o#MKC>keFG+v-+ zf^s@S$+EucztY~Vx@`?|JqG`?# zMLXM}Xu2JWX4s))ByT!EtV1d7fVD7rwP=t6;_iv)@;7AU$zpy*P8qRRw|E*B`e zLZIkMfugGfimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n}kBq3GGT}Bp}tF@+18dL(#6y z57^pOvahV@_IBkv9}Pu!I6oBKX@{b_>`-*K9g6O;L(#oDK+*F8MK1^xy(m!h zl0ebR0!6O~6ul}?^qN4?>q4RE)^?@$5|HZh`R3=gP_#&TS^XRBD%n?7^iI2S?GvHs zUFV0Q_v}#gz8#7_utU*@b}0JD4n-f^q39Dk6n$!kqR(uKJ{KtZLZIkNfugSjioO;o z`bMDWTY;kQ1d6^FDEdL5=tqH~p9G427AX2fpy*eDqTd9HeitbEL!jtSfug?zivAWT z`bQ`fz16O?bOKVnteoJy9g1Gaw?+T9t7KnUQK@}-t*1g!ef$4D(l6VgsEr+pDt0Jp zutQO!9g3=UC~9kmqIPyDYHw52L7=FkKv5@wqB#VLItvudDNr<*K+)U+Me_(0%_~qe zpFq+40!0f56fG!Fw2(m2!U9E$2oxju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(3Psb}msU?es%KOa zoSj2a?|fTyV*5(=l@*=ZzC7yXP;{E}L(%DWC_2LqMQ7Tf=qx)Foo$DrbL>!bt{sZb zvqRDOHboZ*6kRA#bdf;O#R5f_2ozl^P;{9<(d7a~R|phcDNuBkK+)9#Mb`)vT`N#@ zoj}p`0!23n6x}FLbdx~Q%>qTY2o&8a6pBu6UpgoOslJxK>Uc^h8kg@~-`2j8ePu;= zwJ%@%YACwf`Jw0@I~3h(hobxJP;|c?iXN~-(Svp z=na9QHwB8`5(-6kv@bo8fK(sNH$QiVq7U;QhrHdsl6_@G@3$|1`Fbe&!157q8@fAYO+I7PdgO#vO`gCI~1*CQ`ASG zXk~$-z5+%41d3J>C|XsZXf=VN{sKj-3lyy(P_(8%(Ex#>fdWN?1d0X=6b%t58Y)n< zmO#-kfugkqiq;V*8ZH!ymhDhFD*>sF$$tW}Tqt@klUlb!CHu;XHt0~k`@K-Kq4Pu0 zMs_F~X@{bX?NGFd9f~%!L(yh-DB9c(MO)aRXiJ--tptj;7AV?AplDlxqEP}x+X)nn z7AP7cP&8JcXq-UNc!8n`0!0%AinbRh+CiXbM}eZ91d1jJ6ipT=nj%m%RiJ2^P$*ij zL+OJAq|b?dF_uw(V5NB0ti^p-%;+X6-J2o$|5 z6pHTdP`W7rsdmYCh3*MOpX6_!eXm0$`^t(w>QH|9^HB7$^Fz@mb}0JP4n?2Yq3Clv z6n$ZbqA%@G^pzcozP3ZrH#SAz3KV@OQ1rb((GLPeKMEB6BvACTK+!J(MZXFZ{U%WK zyFk$&0!4oc6#XSo^tV9KKLSPn3KZ3JjEC(M)e02V2^5tCit2?z(FYw$eLO6Im_X6u0!2#* z6fG%Gw3I;6(gH=x2o!Y{C|Xu16jeHw)=WUEOXa&l4IPU|`e$ZR%XO?|Us+N2j^)wc zgrXIlABuX|p{U6YMLq3M)XNSkVCG+3Z$h(OU$fugkpiiQaktu0WrjzH0HfueNzn*SWFTPQj-kM%oNvahUYWXJNQ--V)$oga!eu|v_Ob|~7+4n>>W zp=b*`6m4mTqOI&uw6z_Iwy`PNR-kBMr?f*BgbR z74vP;%#M}pD=XTqWBKbJLecKd4@G;}p=eJ#6zye)qP^`mhX@oMDo}KoK+)j>MMnq}9Vt+Blt9tZ0!7CN6dfy2beurZ@d8CB z2o#+tP;`<&(a8curwA0CDo}KqP$=4^W2y6xNzs1!&(U@bMQ4}OIK5*f`^t*W?pW^i zb0|8;`Jw1sI~1K~hobZCP;`MEiY~N6(M5JBy4Vgym)N1`Qk$a71d1*fD7r$R=t_a2 zs|1R!7AU$#py*nGqU!{Tt`{h}L7?bHfufrPif$Gtx<#PqR)M111d47KD7r(S=uUy6 zy9A2v779gYb}Vh4fK&(O+oH2VQ6+yyyQgC%`^t(Q=vdzU*HHAJ^Fz@?b|`w-4n>dH zq3BUN6g_5#qQ~t}^n@LXp0q>JQ#M6U3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22! zy&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAQX!3>sUG`0jaK& zAC}!8iW>8mAV2I_$-c6pPdk?H{XGII6*0!3{EiYh{(=;My1j}nmTs`-=HC!y%C{Kp{;ohsQ^ zR@AOjx%^isYVZ6|)WHr#9qmxm$qq$x*rBMi9g60(L(yDzD4N?2Mf2Dc%_~qepFq+4 z0!0f56fG!Fw2(m2!U9E$2ox^U!Z7pfuc18iq;e;8X!{ObT zfKt*;iJyX{Yk>HTeznsHxw~`JrfYI}~kUhoUX*P_&gDing{x z(KdD{+SU$5qwG+$olVhbfub=2MPmhu#t9US7buz_P&84XXnTR89R!MY6e!wBplFgn z(PV+5DFQ`P1&XE#6zwcfG+m%*hCtCwfudOgMY{-vqK!M1Zb?9@{qrB4Z4!zW%#ZYU z?NrIWvZ6gZm0zt3MSD3v6zy$?qJ8X8w67hC_OnCL{&pxjzz#(R+M(zmI}{ykQ*?+x z(V+rGhY1uNE>LuYK+%x`MMnt~9W79Fj6l(`0!7CO6df;6bb>(9i2_9@2^5_yP;`nw z(WwGOrwJ6DE>LuaK+%~(p=kF`rN0u8>eu;U*&d_jX=@00!7ye z6kRV+bb~LubK+&B7MRy4l-7Qdbk3iAA0!8-; zg`#shl?Emt)ur>z&$*#!M1G8Rf2T_Jl@&eQsXVq4iXL%(D0ROVI(g6#dGUqJwM{9U`FU zFabqJ2q-#AK+$gm6#Y&>(H{g99V4LVPXdbmBB1DR0*btJec6tp00Bh_1QZ1cC<+l! z6egf3k$|EI0Yym!6eSZ-ltS7l zAoz-^qz9`cyN*@U{jcJU5KuIffTCdp z6y*|7G@O8f_`1F_*oy7U2Xfj)hrm&^xWVRHY!j__ZwiHceOHlz^il(up zsF01K=>!xN5l}RPfTEcM6wM-_Xf^>wa|kFpm4KqT1Qg99plCh;Ma2XZEg+z1Apu2; z2q-Ecps199qQwLhEg_)jGy;m25>T{^;43;IJ$QoylJb;27EO|(W%e0ud3wZrnW8h( z!`m~Y=q%1JMP+O$TFI88v)NL#iY-Owu%&1^0*bC9plB1pSF|EM__YI)(#Rfu&XA%NHm*;Pm@iXwb9y*ZLyB(U{8Dr)TZ(RD zOVRCYDca1IqC419bSGPi?qW;P-E1kkhmE3p2`IXcfTH^eDB40m(E|h&JxD;&Lj)9U zC7|eG0*W3Xpy*KoiXJ1N=y3vyo*_cy2q@Z1K+#tO6n#xV(KiGXeM|5ay^tPUZ1 zq7)@LJfZK>Bj(E#{g@uUw2l=0#QCM@XSNjWXG_s9Y$-axmZD$TQgo0lMTgi@beJtg zN7yJjNzn3T5Kt*&6c7%Y$>YCmZExWDXPy#Q3C>s8WK>{h=8I@ z0*V?FP}GEgqNW5CH6x&?IRQm22qc^I%{%jNtAfRX<0Y!rdC>l&a(GUWPh7wRTjDVtC z0*ZzcP?SeN(Fg*HMiNjoih!cg1Qd-SplB=sMdJu48c#sc1OkdC5>RwJ0YxVed_`R{ zf`c58lpY4Bs}%iZKj5E~5iwt;Xi7%7C{v0~=KNB03R{Zu*-|u>Eky-vDVoNXqC&P5 zO=n9{5nGC8uu(LVfTCFh6wM}}Xbu5IrxH*!mw=*q1Qg9Dps1LDq6GvLEhM055dlRd z1QeALP_&qUq9p_rokl>>QUZ#W5m2<8fTGh0C|W`A6`hn3T<3tKOffifP;@;3MK=&obR)r6bXG=irvs95(9KYp6#Z%Ari_UB@~V0Xp{B|8S_Hhb z+ue_By|kANT-p!r+muOZRoqu|(Xv~?hv>pvSFFWn5MxNI>?fJ%@*F7z@ndkLR8{5M3`lVgj%JT-L zecHzJhNU&l^1Kmgvpaa+n6&$HJa0nUp-!GRDXmvm&zq9Avb*O^O?$DY=S@$m(#P{= zrH$|Fd2`dQ?(caE(mo&Pd8KL1hj`x7v{Q$9-iov>!#%Go?Z^nvJ14ErXwO@dwrZ^B ztxtP-yytC5OFQ24E=!v@$@8vCyY?i{+nDyn6wkXMt!2LF-I6x1!1FezJy_^@cc=YU zuXOi7AU5zCcNYX=Yd5<4AP{?Vle-fF zu^KnJdm#{;e6zb70K7j!vZn;{|b!=#J=0+?vp^w{?8s00x|nv zGfWD^?C;i}5{TJfjy^RIv%lSXdLU+hJ@KqS%>I7axq+Dd1)&Q9G5Z@HO9L_cEBclO zV)l2etq8>IFUcwk#O!Z5Iwuf&YPY+G0x|o0M%D*n_7_EL2*m8a^uH_+v;S24szA*C zTicC+nEl6+Hw0q#U%TBBh}nOxv^fy7|K8;8K+OJwf%^k7`;G610x|oQ-A4m4`<=@t z12Oxhxov@%{npctK+Jw^<)uK(e(&J5K+Jw{yfYB9pZx6##Oy~m9|U6dz4uQ7G5hA} z?m*1G`?WU^vu|H~8;IH0pZfwa`vPKrAZE`14+diPDg0<4W{<(g0$%zh_PzaE{13Sd z$I1(Ia>Wq|xED88%Wz+u1iDnc$Wpa=?q7kf8e84T0^Ky$1l{OfbyfUi?cK*-pod=5 z#ZJ~!BhTJiFO6|FdTUIzi|eEDyZfLH9H%iV#f`oirFISa`NO@G9%x>*T57Ory{Z#y zr8^a#m(a{hO+C&f&kNS{f>nE__Db!Mnp@4ilX^{(=Y_j?RuZcPQd9jC1l){N@q$U5 zJ~g#UYBaUGdry*T{o_>0?o^fDYKmsqzmQbDNjL3HM)fA+udR5KRrDrxs;cfx;fm{# zR>fUAyX08>g|O$P>pjthWV8?Tt;3aQStmV^k=U>Hl>_Ryd#H1zD_7sW39r8U#~vcx z`ycOjTA9q^2ciOk_u&AKJjFJT%N){D%Sd?E< zSd_nDQE_QeVQJCy4uy-BEhsIvP*^m5@uH%VO0ToiyHoe*uwc>bd9zDrFDddm%qpH& z)S+N*(b5j>=N1C~V9~q|IobK0@;hdC%*oHmwwUE&*8Jl6MOj4!(`IMoWVi2>Wv_1UUj2_(b(lTB zaPH#iMIGi96waDG|Nrx=QL?P0@+~oQR)_wJrZ1j7zj$ErqN1$w+hS?yqWDeX-y&lc z70+?Ec}a)y3knvUI%M(u{0Z)TnK@?e;*$Jv{kx9r^51bcEh#81vRljZ{5yKa;`xQ0 zvUA!O8ioAnMKcN(&n?X_UACa8r2Q-t=I*ZPv*(w(;T{Uc4;-BDu4duD;(7Cm=euV3 z++$fdPBGXi5Dr)SPk+K0iSE^jBi!fsK#g#!9n!*?c5ppDGu^8@#!r^nB%IOEttS7a z6KDTVIC0~!UFinyN;lSf`oHMP$FKYUvK#z=$aVhz@Av=kA^iW|N9F&%2Z#S5R>PV9 zl{+QSF(Ji0KNvT7X#SAwVV)gxx@Ql|pXR^VwR8E4T?UrF*tNS(*||HdKWEPF?7wdC zK%FMXPMmL_O!Vo;n?0hqctMUgvj3#~fukmL^e<@;Z=g&0rFSEBs<;*%%df@2N*AE3 z+mSPLEk9L{_%&QSzhw5z`9;$+-6yyB#SPT8%o)O4aWC*r4=#VNa@>`PpT37XS$@7d zcc+f|{#(d#7seTe@Yee4tqrJn3-0!CC!4-_-n?c0TheJebHV);x|Lr6ck`CN8K=v;Bt+@0;8y!?GZRd&U@ z(xd!p=QzGz-ry7S`wtoyKcBlF^&UCBdTG!<&gso9o6HcnG$$;|fWFMjN6ZNmSa)Y?zJLz@h61ec3?&WVP zrve)|u#r=t&%GDAXhf9X_wKS6}obUaMx6z;@)!agnvF>u)8Jx zKvZ$py2mD6l^l0ncrmBq7O8XxchlLq6MQ@N2D?|>T<*s7FQX$DR&nR&RNVVHmF|9b z5BX=QxTCorat7#q=U(Vhetq5TtE*e_pu}C&rQ-VdcYpl7uDHi@D&6Ik?&_}Yic~n{ zAuR_n_G)`W?pS_9DRH;C2NS)jQ~6EkZU|0ZamRC?a+j9hjosbtS6q&@;y&Tw-ySCP z=G=LB!%m=o6S|9yzu;~OURQpV+-13DpD-r4uS|4$&gkxsc(FS<{&~dz^f9>n-0mLG zTdcSS+{f+~((B6aOLrIemr!BDJ!ZI5#ou`RRqnpkx!l9MUMhb_oIC&g?h(>+U*RtD zZ&#Ac2b1Lq1?vWgKW#eadpLF9#Zt)!F*MF;(?$C<+&t14~n;iF~!9St< z_|yyKH(`!{@7mR@^gx`WbGUo8;s$mv4IMQxb6}4infA?q_BomM?SSm=9Xn^XT2wT* zsGy{%b!OJQ!Uc=_6uMiiXld5GPMusRowa!0G=M-6Xue)W>Zc1kt&(A7xU)Q^1iEGmfN(;)je^a>6 z%l-=$WOFLa8pr?i*~MpB=`&!tJ!d!mHY=X3nMS*fE1tAfJXOo_fybq|M`K;BihIac zUjFGVjyga8pPzequ2}I@5jOU8X7rHp<)2e?cxG7fysqNuT*b3F_bd@U{zrjby>iDq z6RdcWR_Qq!PXsHTknsUw&(ZuFMiBicWAXRgo&oAfVf;PxKkCZgYd*@#EkoI!37%U1 zz{eB5iYH|i&&fbtevjKzzW>hezv_U6C*shmRIFMn5lbHN(Dl_pjdrY*y+uoBl6fnz{4X4-OLS$8UCYKYFwG+m1DK zbl;)&65MyC8{5&HsFk|iUv@h86SVlz{oE{m9H8SE9VhDOzAG7j{Tv$t_ft?e%7DIMQ&@0#t;bv)$W0owt0liRVDdtdC>RL36fy4xPC<7D@;?U_2> z;BHFW_vrYwy8&$fs$)BM$J_3q<0AKCNZV)W_^A7Vr0wT*{Hw0NQ|tN1LGFi?_WH3p zu50A)D|OuIZdiN$r#jYb=I^FDPHExq**f0j?f^UeeL8;I#@~l@Y@g-tUOJY#JIYSK zQpd-0{QaViUT1$-(Q$~oL+$kAbzI-w-&gDSc29qQu48R?$J^v&3Ef1j%3E&cty zMaS<4`um8E*+cx@N5>_@{Jl!YCx`p{WgQbn`a4a>VWa&$QO66%`ukcPca8V=7dqBG z-rp^CoI1(h^K`uJB!54shJzKE?@5N^K{&{ z!r!m!n0S`ItLZpmrN2+q@sd^kzFx-x;A_xGDRCSB$48aj@;#@~~5ylkVtZ`AQ4_mgeAf4W!8)FKx4+NVamT&>eoM!cE&i^hM zZ1wleI)3tqzrWM5$>aX+pyRA3{k>Snd!P3A6FMH;=I_9E|Jd_6|2R~~vgiGMfsQY{ z=gKk<*bI-dQRzc149rQQC1SI4S*{9RAS319iUK*wvo@%QaI?smTdU><(dvBf@r zchYh0PySw};{*Hs{fv%B-LDDQ`NO~Z$Kww9$2=X+IpXh&b$sPFf4{F|?3lkB=y?2J z{w~yUqx-CGZ~qP*zjVK4VEbnsTe%<6+3up_eD`|?woljbA@>Uiwzuo}yZcQ9+mWb$ z?B{+Z!S+ZU&vn0>VEa-XUvs~tVEaQIGu&@0*lwibB=>6zwu^M! z%_}XK=8mO{{NpTMa$mHTdhPA2M6dm{k`k}Ih4%maZh3q6wQl?A_N`F&{pT6Q?&R^8 z3#Lt5RJ6pa^xA?&1@mVXxi?aAhJP<}?FZ(16Yg4g?F-#ccZ=M2#Veg_#-f6G?nM2^ zjci{~TDoZVw8f?F&Hh*axTiTzrvE(B&f}g&{Ns}Y>x^$U2lU8v?> zw!7cno?Wjo?jO$MUi3a_74Vu?3cNV&UrzT&>wuSOXV4!`cZ%DUFSjf=5I1L+YnR96 zE_N?-9`~YGuZ@2?d)fZ*x`poL%5QH&rMH*jUdP)zuhMzki(Xsz_Bz@H>JM*kmD`oy z-VN^U*~#qsMcqHVy-VH8cAjkakNr8hW58=*C(s{zo&B>(M^3l=xPUiYr?CU4yGt+g zsvYihnGAQd%e6nZyMHQQzs;52U;EhQ`aSAicJ>yyL;TNP_x5@++|e%A{@4+-wln*> z%XQH{&ePpL_V(=U+GS$dz3BDp7x0?f3;M&`v-4Cw-J|aMy~K&!k<(TFa;;Xh(Si1IO?w+-YUJ%W zy1VR~g1?Xa_4n5WJC5!gyJz-^32k?cKKO8#w7l5xSZ;d!boTn8hZ_v2>Q28eb5Frj z-|k=O#cKB3c9GZJTkm!MZOWkb{n~k%SDZMwtljqq?s;V0a|cd*{E6T8wp+Yr*VeaQ z`ReY?S9qCIy$yL6$FIqT+>7IvykXcsFZ-l~e!mo~%00YuVBxgFIoBo}+coe&yWpDP zh115*x!$dF^H%4MpO!aglY6=U;Tx;19G>T1bDdj559|z{8GqeIw}u_q9$X%O-BoTS zG+vf>+OV;OuJ}_UG~5U@#|^VY+T;h_+{I*vdbPBe~n!$dk=<}U$3OhQF%jh z$GG<(FMd0WKIpkCJz)5-LVN%1)=0`6oOhf~VYi2!Vqjhmox(0TA+ujz7oEZ`+ir!N z@=MRoYahRCZiTk-*Vt`7`e5e5j(IId*zH&7F00~pDQjuBOuM|S_Wylrb|_v?bT z|Cd|iWOr*cTV2+;`tas?_O`~y?+d$iV#Dm7vG>|;ooM`?vFnkVmt1}=?AA$i_e|FA zMjv?HPyK7q)T)>Fd1KA*-QTF6H?XN$+)~Gj?HuNnrEfo_<$zPl8U;J8|LeMfKeuj6 z_saUGcx7Xgy|SGnys{hXcxC<8c-=oeH=$+j-UTmi{_UmfKfj{Q;q7H!+5heRyD;w} zee{IgN6(6;_Fe`LoIl>)&$YSh{=<8E&N-vpd$uYr*KX~z^UfZ=DtFZ|`$#g=XT(L= z{eD*7@_*d&OUmEpA?_`d#9wFku-!Jr@z-(xF3LMq_ov;z?tWS@KX0b)al6c<#;4{L zR&w9(aQ|xgb>(UnCja5SeQ=fg=qjj}7ad+uXpc;G9qci-Zf@Q9{oC(AZndzxe>?0pXPfSCI&<;; zXaBzN;u(X?Y5jLU-SPIM?!#|A|BhB@^gSL`x)T(L{Ax9UHx*k#zYZdraAcCDM0-;3^k8=o0}oxOcKUxV^{ zvEPBg)$06*d$CqtZTozcT`T^`Tq}Mr*3A9)N9IZHvFO>e?Ou%KCF)+ZORADrb$Hd> zwD`T)WViPWk1KZDKReZb+}ON&>%oy{{*-*@?z3MywEWk*w%_2DwOAG0wdAv_zS-X7 z@m0}9TT9pGtsA~B_x$+VDQn>#C2Oo5v3B@6`>c_f@XN9R35RB7Bpg06%{_)pU7dUG zu&?5uJG`duvq!?0_Sqw6&+L469ebV4=R&*vGMlW(J1uvbGnW@PXCDP6<+s_Ayan-F z%naBqHaGqnd#~(sk?EbO0F)jW&yM&^={P=4yFggAjGhpYMRDM~b z4<;;_oHs#_K6V-QQ9UO9db^DAdH!cIy9B!~x$)Q7C6qOGpUEmcZkU|`<&PV7ZH_Cy zlmU6Y{_!4lkH5w)&8|)7^7qI--YUfPKhVEgR{48mk9lq4=d<^zEHgW=MWxSyNts!B zO)AN@&zi0C8tN2$MygwWxefAam0zm8U)AETvG>xhL#+H#?RC-eOSR7g$?@0OEotv# z*u5^(`TDqdx2

eysa#J>P5j)83*?^R^?^>wcug3Hk3=8!~I{6UXZBoZ^+)V}yMk zGl$#zxzA&l`Jc!9kN?$rR>VDjcKP+S+sS`cq>s$t>E+k>w7jMNxW1+3*Vpcoh5xv| z^Wv|wkNr7$bKRbLk*&|Bt^7qN^A77JQf;|p&%j>Mm zu=mU^BRhT>rp?}utoU29_sZT<>-bx;_sXt$i}>q&-7WH(RMKtlNyBp8w(7-C>%U)h z^J@Le`&F&{{j!gzSp2khDbc(t|9HRr=S6nQ*|kah$NQDw&XwY9nHlr+R)X(lc)%<3 zz1aKPKd--@(fRM;!(EQc>pQ$}Za?>!mH7DRgU3xw_+^)SoVq8YcV5DQmk0FD?Opzr zK)(Z#!k+FCc6Vms)WTV(c*ow|b<_*+HA3gyE_q2)?U8PedsO@WG5;2_&y#k2JLGj3 zo}HT=e`Ngo$nq!bmTnY(mSnd{+q`ze+vR4(Upwt9dtL4L>+GDZ+-LdLxozUF8@bos zhgR+@l#0*5>9eZ;{(lZ~0aCK6nMq@{)84yLXznkM*XxO?8S+k9*J9W4GN#4c_Rw zDU>tktH~ey*==Co%YOgqy@9Ro48QW?@h|;$URf}(GX9mD`}(C*>svnUdgg$Ghex%3 zs?L@Z+pfH+@w?C6vh9syn_eyHI^@}dw`9Ei<99z6esbvg*B`&VsKxU;H+yB18-Dop zojtl7?f+fDbq|ece*VriUfF_=dVds~zhXk?At&~V-m|vbF8B3)D1ITKKtuP%YqXzR zy()jD>t2}%SQq)X6!u^bB9Pu3Gckq_KSg4yl_!FJX9+shBQiwAEs#*CMfeeS+GP7%$y@4gnrP%^ju&dB+0f07UZ}NZ z12;Rl{}Y~OeK$LMp|+a!-0b3o+G*Bxv#a~d^fl|a+06^J*R1VkcQ4dIvzD7Z+~3Ei zS<}rNceQe~YuI+ztD|;x+wO{W(ynIPU9-;G8MfV3>!O`*+g-P=+A-Vi%5~FDv+b^3 zckQaS-PP-%UB$M$em%9LZg+Ioua|bJZFl{8Yp2+D*RPLuvTb+$j?+%E?XF*6?TBr6 z{rYJq+IH8kzjoNRyM6<-L$=-Z8>k($?XKS-?F6?wx$8GrJ7C*gzaiQVLP{vqEcl_j z|5L9qPtD_hS3+u`lMxykdBmN-gye-kbeQ8pM(C^(GE!4QMrlgOXiW(jqbVU{H6>)6 zri6^wl#mIU5;9Q}A;)VYE2w9_z zkhR(fS*MMV^R*GOUK=47Xd~o8ZG>E;jgSr6zL5FB2JRsvwY&QS6e{+GeCue0E{>QS z6LNXDf%~i&7jlKpDj`>DO2}235^}Ysgj}O3A=he3$VN>GxlU6;Hfc)8^_mE|K^q}A zY9r((ZG_ycjgVWk5pt_GLT=MW$nDw)*{qF_JG2pUr#3?F(niSL+6cKv8zJ{c|aQ>4{9UiA#H?g)%Jy48tm)t|I{n&G2}8|NP>Nqc{pNnOvvNmzV1OK zF60TFRYIQBl#r)1CFE&M33*0SLbhp2$aYN$c~(Kni)JDi#+6Z}D8zJv#BV?C0Lf+Lz$a~rd zd0!hLA7~@wLv4h7r0olNG+5y7|I}LUiErpJU&si1PV#ZYWM#%5l2>C-BA;+{4@~1XJ z{?bOs-`c*APlM;U`#<$dd+zaBTuAh&J)XEx-b=`JP%Tw8P+;&gPqwLylyQk$< z*tOhtPs^*aYr1V;*Q60@Sa8=cMyPJVUBz@lH4E-KW)LzgxGPzWkZ!?U%j$%f1$Q-T z5YjBT>sgaf)q=aCwFp%#xNBOQ5Ou-6!l^?@wcxI4T|$ZlcTMXNk}bGvTAz?)!Clh^ zgop)qO&bytEx2pih!D2mu4yJAWWin2#sv2(yzwt}nh+9Pu&;HR5&{<7HEl+4K+-~? zgh22W2PFE0Jv|8qd_^G>)jSX}UZ$vZApC>-!E#(t8_q99ZP`-Pjx9x5Y$o zYIq=GzD&`mKsd+!T0>mXXwEN1W7twOmMul&*itl}EkzU9QZ$h*MaQ$H=mfSDO=6?y zL;{LVBA{q80Yy^?C_0&dqEiSc$|s;`Dgi|W1Qbmpps0|5qUi(_6%kN0gMgx$1Qg98 zplCJ$MRN!!I+cK;xdar=BcNzL!B;dQ5Io)ii9X?GXrvSkHB!Zai1{)_C4um1HKnMO z^GnfUwiGR4OVMd;DO$>wqGfC;TF#cD)7etAf-Oa7uu*g-0YzsKP*g@h(Mke}&L*H} z6#+%(5Ky$5fTD8=C_0aTqBR5*ttFsn9RWq>6Hv6CfT9ZsD7uhx zLO{`_1Ygm@Kyaf25^d?e(he<>BKw=DLYD<1=F1da6$n4&euXmrSadb#m!fOfQgkg_ ziZ-&P=sLC(ZDLE&^=v7+fh|QhvZd%IHi~X0py(C?if$#K=r#h1ZYQ8;69S5w z5>V8PfTHFE9*bHKP}Gv(D+(tBA96sVSJ*cc6BGQe^!M9iQLBWA`7%ZA62k8`mZB`q zFGcOyQq+MhMcHgA%3(`UN46AoVoOnHwiIdRn}p!+4oI}G`)@5mZKWv1zS19=5HVk-Xlz2bUNb2g$N8mbJX?w;u%&1sTZ)cn zOVJ5zDVoHVq7&ItbP`*NCbLmAg@B@y2`D;+fTDZ?il!1!R6sz{Gy;kW2`HLQKv59^ zMKcH}nn^&>ECPyV6HqjVfTB|gD4I(^(L4f*<`Ym_ce6Hv5@fTD8T{`fTHsWC|XZI(FFt)T}VLD zMFbRWAfV`C0*Wpnpy*NpiY_Cd=yC#zt|0h|N)v+TIv~-p_AR2tQuLfX7G0STF<++W z+Jx}!t)yrp=a-`E*iy8KEk)O}rRWB>6y3;{qMO)KbTeCuZedH&t!xzCMnKW+1Qcy1 zpy&<)itZ$!=q>_^?k1q<9s-K)C7|d&0*dY@plAyLMGp{A^dJF64-rtbm4Kp$2`GAm zfTBkUD0+;5qQ?m+dV=69x;i2FngbHOGT`7`BSl5_SoCB<#C(~eZ3*EY+ep!N&M!sJ zvZd%bwiNAPOVRUeDSCk|MK7|Y=q0ukz08)PSJ)_em4Kqx2q=1;fTA}DD0-8CqMZa3 zy+uIL+XNK7LqO3k0*c-xpy)jUiry!n=mP?ZJ|v*%BLa#(CZOmO0*XE*py)FKiasZx zXg9%E^mIZnqpeePz`oLd21WMl`iq2!`7%XcC4@U=NzvDwUy8nAOVPJ%Df*5rMc=cf z=m)kG?PE*Pk8COWi7iDxvr)94fTCXrC^|qu(XRv)9VDRW5CKJp2`D;3K+#bGihd)Y z=yw8&{ve>}7y(6p5>WIP0Y!fkP~`q+0oS^_(fvf-eXGWP8XF*>D1m^YAOS@o0*b-} zU(ud~;3NkmI@2DD_Daza8;QY)`7%W*!SJ#UQk2U1r6|glqAF}Ds>+t4G`1AQ*iw|v zmZA){6jftOQFS(oY7kIVlYpXH1QgXKpr{T3MRf@%sz*RkeFBOa5Kz>RfTBhO6lD@n z)R=&xCIl2UC7`Go0Y%LTC~84KQA+}fS`kpxnt-A<1Yc27Fu2J9i5AHCZK2t0YyUzC>lmUQ7!>R z!wD$LBcNym0YxJTC>ljT(P)CNC@UD;>wrWrw5LMtrRYa{EE*Gxm@iW_AsDv*%s>9U z>xrCSijHSX(FtrRn#7i(6WLO95?hKUv!!SXTZ&F*OVKH86y+08G?jp&0s@Mr5l~b} zK+$vpii!v*nn6I(Oah8#5l}RnfTB4B6rD;y(Od$G<`GadpMaub0*V$8P_&SMqD2H0 zl@L%=O7Inp3kKUbAkkEN_!%!n`|KOpi-QsKWr~&s!+Bk$XgTMXqSM(@w1O=~XRxK{ zOtuuA#g?KnwiK;oOVQbEDO$xw(K!SZttO!8Tmp*DBcNyv0Yz&GC|XBA(fI@vttX)9 z0s@LIB%tUb0*W>eP;@Z?MVAmzbSVKvml05OIRQmi5Kwd_0Yz64P;@oHS9Dr1xWEC4 zo@|drOQmSCk-8=rF<+)=Q!spScPYA_^GneUY$>{tEk!r6rRZk16y3s>qFdQgbQ@cW zZf8r;W;TlMAfV_@0*dY;py+M_itZtx=w1Sf?jxY+egcZN5K#000YwiIQ1lQ1MOz6d zdYFKsM+hi-lz^hg2q=1-fTAY|D0-5BqNfNbdYa%X+87Kz?0`fEn4;^XXt<4Mf)Vp& zik=IG-*M|^ldQQ!2J!S zaYf&8ekuB%Ek!@DrDz{pihg8E(NAnC`k5_7``J?T3tNf~uu=3Y0YwK1C^|$y(P09L zju23Elz^h&2q^lUfTBMLC^|+!(Vqkq{Y600-vku7-|zOnY)4UmfT9Efih=|bg$O7L z6Ht^$Kv9H%q9lT^=<8r`fCCckWZ$m-MvBh1XV=N0i1{)_RYKvyzEV_`^Gi`0TZ&?A zDN1KcQ3hLzs)9sx!52`FknKv6>iiW(76 zlu1BQV*-kr5Kz>VfTCsu6g4NHs09Hcy6#-fR^0A)x3u0*d+)P}GlrqW%OF4IrRsAOS^#2q+p%K+zBaiiQ$UG>m|v zTmp)Q6Ht^#K+y;SibfJpG>U+t(F7EYA)sh10Y&2ozM||<@C^qfy3Wl|juh>&$D;9} zi1{)_CxpU350s)woL`DgWJ}RWY$=+|mZB+aDLR=gMW?W(D4#7wQ`u5fz(&zD0*VR= zD4I?{Q4s+}GYBY}NkGvo0*Yo6P&9{tqEiVdnoB^@JOYa56Hru4K+ysMiWU-3w1|MB z5(0`!2`E}jK+zHcicTZ=iYA7F)dx963HB3^imoA`=vo4b zHWGYA%R|AF9FS;B`@QSar6|Sy2d|;)LJ{+2if#;rPah^lH*tO`x|uCSx3Hz?R<;z~ z#+IVn*;2HbEk$>*rRYw!6y3!}(cJ_T-9tdpy#y59M?lg21Qcx{py&YtiXJ4O=ph1% zwh~bEFabr65K#0e0Y#4yQ1mzfMNbe=^dtdAPZ3b`Gyz4=5Ky#@fTHaLU(xlU;0+E) z^ke%8$PH3te=BY1*-*rMnW7g$;qAkv=ta&iMK7_X=w-GPy~38FSJ_hZ8e589XG_r= zY$}&H;(uW1rE!m!j(S87&%)m@iWl3x`LJmZEgd zFGU$_DXPYnqUvlZs==0`nrtbm#g?MlY$>Y4mZG|B6xAc3s6GKj4G1V|NI+2|0*W#T zC~8bVQ4<1+ni5ddjDVu%1QfL(pr|DQMXd-ZYE3{<8v=^j5>V8RfTAn{irN!U)PaDa zY=W<-YB;#a0f}bW?_H;b{jc<=*aK5eIAXp`QI~M|(y>z1mGetcH?|aYXG>8JwiNYb zOHnVj6!m6HQ6IJx9mkfUzHAirBcP~10Yw7{C>lsW(I5hf1`|*;gn*)<1QZP;peUDs zqTvJ-6Us0!U@KFaOIv~lx z=`2Oh+c-WPF<++Wq;UAd@lrII^GnebwiKPrmZDSGQk2h@qN!{tDqu^|G`18KvZZJ` z8%0F~6wM%@XeI$gvj`}fO+e8c0*X#0plB`uMe_(KnomGcF#$yj2q;=eK+z%sib@D5 zDkY$3F#$zO2q-#@fTE=Y6fGm5XgR@GG$|bX%K?c#Z%>6zl%f~xvFP-0#C(~ev%=v< z$4gNe=a-_DY$-aMEk&!?QgjYmidM6w=v=lGoyV4U0*cNjplCe-MHdiI zbRhvn7ZFgjfq{(69S4pC7|dt z0*XE-plCM%MPCq5^d$jBdk84nOF+?A1QdNuK+!h@6n#rT(RT!2(Tm~WP6s6F{wH%@ z=p`u{XP?o&4@bgY$>YGmZAo16g4EEs1X50nFJIy zCZMPZ0Yyy-C~8JPQF8){S`bjwl7OOC1QfLm|vTmp)Q z6Ht^#K+y;SibfJpG>U+t(F7EYA)sh10Y&2oC>l>d(F6jDCK6C|JOM=~5KuIU;4A8y z7`({=iGE?vi@HhCGxp<<6B8rm%M_iQ7=Er$icaDDQk2h@qN!{tDqu^|G`18KvZZJ` zTZ)R1miU}xMKtRz#0*V$9P*g%d zQ7HjMiwP)NLO{`J1QabLplBHZMau~&I-P)`6$BKWLGTq#P7HqQfJC3L-!GaXMK{|w zvd>J6m@iXwc49brh7_&h{8DrdTZ&e*rRZF?6rIPGqBU$OTFaKAb!;g*pDjh}*(kbz zfT9ZtD7uJ%q74KTT}(jHB?J^*N^ z0*bC9plA~TMb{HhbOQlJHxf{E6Tw$hmKbdBfJBGe6Y7;x)FA!^TVlj~nWEbh!=q{*Ek#?{D0+Z^q6Y~mdWe9ctppT3 zOhC~i1Qb0=K+$6a6g^Hr(Gvs|JxM^(Qv?(}O+e8z1Qcx}plCY*Mb8pY^c(?2I|wLx zo`9kk2q=1y;48W{F<9z=L>t)?>f5B~YI`htDKTQcOwntJ;mhYp(d(RFir!#L(VJ{3 z+R2upx7bqjHd~6`VN202wiLa~mZJCAD0-iOq7Mit`jCL4j|eFGn1G^B2q^lLfTGU` zDEgd$qTK`(eL+Ccmjo2;A)sh40YzUCQ1mqcMc)um^eq8J-w{ysJpn~O5Ky#_;46A1 zG5ELx68+vjqrECcgY3)x9}^?y%M|^R82)&!6dmCFQuHfZiVm`+=nz|q4zs1`2wRGd zvZd%ZwiNx&mZCq{C^|+!(Vqkq{Y600-vktS5q;T?q5uI!2?P`c2`CB?P!uMh$bI?Z z|0+I;A_NpA5m1y&Kv4<-MX3Z7MF}XXLO@Yf0*cZID2fqKluqy!{hS!|<~c?C?cry? z6y0slt}`ML^JR)^M#7DYrKlF?m!jHiDXPPkqPlD;s>hb1`fMp`z?PzhY$qbs?arE5TP(JrW$^fJDdJSNb&~{#W`9!lgV`t=LO{__0*ZzaP?SqR z(QpEa@(3szK|s++0*XcvP&Ar=qA>&%jU}LH905h+2`HLCK+!}3ijF6s=mY|aCJ|6{ zA^}Aw5l}Rl;4A7839ffQqF=cg>M2Dx*<;a^NW^@ZqN$PaJtb09!1<+U8e57A*-|u} zEk#9aDVo8SqM2+dn#Go)*=#AA!$#4m1Qg9BplBWeMe_+LDkh+40Rcq|2`E}bKv4++ zMWqB3EheC72?0f?5m2<0fTCpt6fGy9=yU>#RuE8h1_4E95>Rv&0Yzm5U(qR%;M)#J zw1a(FmM=wP?bF-JNW^@ZqScY`uZyMVT+S~==dq<|4O@!VvZZJpTZ+zSOVN6^6kWiU zq6^tlbP*dx8we=6n1G^72q?OgfTGI?D7u`0qALg}x{`pRs|YB%nt-Bf2q?OifTE2A z6kSI^(Ix_lt|y@A1_Fw1B%tUf0*Y=Xpy(C?if$$NidIE}wU;+cER~|WIKLF#&6c8j*iv*aTZ-;uOVRyoDcZu8q6gSg^dMV`9%7?tD*;6h z6HxRB0Y#4zQ1lo9MUN9u^aKG#PZCh{6ahs~6HxRF0Y%#gDB4ay(X#{;Jx4&%4g!jv zC!pvB0*YQFpy(w6ie4t5=oNymXmccZiUSheZU1fT9a6N`9*bU$M9h~ddNUF}Yq=Ed z zDEf(jqMr%AqSqtATO5$+OnWNyh7>(#k45_<5%Xn=4o1SyyZ-@n{J+yb#QCM@Fk6a_ zu%+lITZ(>TOVRIaDf)vgMaS4u^e0=2{$iu(Zvu+EBz-}Rq5uI!2?P`c2`CB?P!uMh zD3O4o2mwV&1QaC`P?SPIQ7QpNQ38sp5KvT=fTA=4iedy5r4vw;K|oP80*a~=d_@N$ z!S5ZA=qCHF2Lg(+ z2`I`Tpr|7OMV$yJ>P$dU7Xpg95>V8QfTHdM6!jqZifSbVvmKD=)AkdP+DZOb`a|tA zTF<12`7%YvC56YXl%l?zUyAy%rKmq!iUzQyXdqjP2C=1RFk6a-u%&1yTZ)FUQItzS z(QpEa@(3szK|s++0*XcvP&Ar=qA>&%jU}LH905h+2`HLCK+!}3ijF6s=mY|aCJ|6{ zA^}Aw5l}RlfTAe`6rD^!(J2I9QSYSS5(gwY&*1ctqILFIl%EtaU#6%qDSYKBDVomt zrKpH4MKjn^G?Ohwv)EEJn=M6i*iv*VTZ-ngrDz@-Me_+LDkh+40Rcq|2`E}bKv4++ zMWqB3EheC72?0f?5m2<0fTCpt6fGy9=yU>#RuE8h1_4E95>Rv&0Yzm56s;tn=xhRt zRuOzf1xdjt9gt`pdnz*|DO$&tqVw5Ow4N{!Ek&2GQFJK*MVAp!bU6V_cO5m0nB0Y%pkP;@N;MH>ky zx{iRNO#~EOPe9QP1Qgv!K+#PE6x~cf(JcfN-AX{wZ3GnEPC(ISg0JY@q+r6iPSIBT z(b;)Y)Y(YgkrXjsrs$reaMLwXbT8+ZqWjoVbU#~)wy>q>0k#x9$d;mq*iy8WEkzHr zrRWhhiXJ7P=rIC{9w(sa2?C0qB%tUi0*am{py(L_inb9@w4H#WX9*~Jj)0;a1Qb0_ zK+y{X6un45(Mtpry-YySD+Cn1Nlk|O5I z6uq4kp1n?r-r@XGw2Li8@3N)nJ+>6R&z7PO*i!T%TZ%qnOVP({Df)zsqE87Z`iy|0 z&j~2nO+e8X1QdNqK+zroiuMvv^c4X`UlUOD4FN^p5>WIV0Y%>vQ1k-diV52C3fTAD)MIi!;!UPm05>ON& zpeTueqGSS!QV1wYC7>uuKv5L}imDP<w^NjDVta0*W#SD5^$4QFQ`}Y7kIVlYpXH z1Ygmiq~Ify!A4O_0*YD@P}G`$qBaB+wI!ga9RWpI1QfL=pr``@McD)tPA3OcLIuf5Kz>UfTCUm6!j+fis~i@>t5s(ZAx@->LvSM z>A!8GPjbY3nWFy5;a(R@(E!dbMFZJVG>9!lgV|Cvge^rw*-|u&Ek(I(DH_g}qC7T= zMi5Xml7OO71Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTH6GC^~_FqDcf4ok&2@Ndy#4 zCZK2v0YxVhP;?3bMfn62O(meHfZ!|Yn;e|#fJF1{;isPzwTXYhmK-r(rf5cTc;%&1 zG?Vj7(JZzU&1Or{9JUml%9f(JY$=+@mZJG=DJo`5(E>J#77|djh=8IJ0*XorC|XQF z(GmiRP9vabDFH>x2q;=kK+)+06s;hj=nMji&Lp7dECPzk2q;=fK+)L*6s;nl=o|uy zRufQkF2PqcJvn%r0}}0F4?jgx)ZBjA=)B~J`7%Z4Cx>6WT#D9nekr(UMK=;qbQ1wZHxp2F3jsy95>Rv-0Y$eHP_&tVqB{sEx|4vSy9mCbwaLMK z4oGyco1t}5G|Im0zdJc%zD&{m$>AzjNzoS0FGUZqrRYJn6g|Y2qOEKxdYCOmkFcfa zQMMF4#+IVT*(iE~fTAY}D0+&3qNfQcdWL|aZ3Gl;C!pwA0*am^plAmHMb8sZ^a24z zFA`An5&=ao6HxRD0Y$G8Q1luBMXwW3^acS%ZxT?nli(}5H#ykR0f}z4Z#3Q~MP2P{ zw6~HY=F1eln;ag0jTF7d`K9Q6wiJE9mZA^YQuGm9iausb(I;#v`jjn2pRuLrb2f^0 z6HxR80YzUDP_&1DqP+wZeMLag*8~)OLqO5D1QdNoK+*RE6#YOz(LMr-ek7piCjyFo zCZK3P0Y$$MP;`KRqF)IpI!Hj#A%d^yo#fzB2PC@1eoJka6z#Jg%^psUm@iZGdvf^d zjZ*Xn=a-^mY$^JaEk%E^rRZAY$-}$OHq(5MIknd!UPm05>ON&peTue zqGSS!QV1wYC7>uuKv5L}imDP<w^NjDVta0*W#SD5^$4QFQ`}Y7kIVlYpXH1QgXK zpr{T3MRf_jqNB;dryY>!1bbfen-tw-k45!TBIe5!HA)G8zDbHQIlmM&W=l~MwiGpG zOHnhn6g6i{Q46*dwPZ_CE4CE1W}~PL0Yz;IC~8MQQ5FG3?FlIAKtNG80Yy0k6m=w^ zs1pH2oe3!FLO@Yh0*bm3P}H4(q8aYQ>3?C5Mg3AD=F1cfN(nc=QHln0ekmHlmZG6-DH_I>qFlBV4QESH9$Sh= zu%&1uTZ%@pQ8b!>qA>&%jU}LH905h+2`HLCK+!}3ijF6s=mY|aCJ|6{A^}Aw5l}Rl zfTAe`6rD^!(J2HJSxiQIrxf zU#4hwO8C^9rDzW4m!ebIQZ$z>Mf2EFG@mU+#cU~Bz?PzgY$;mAmZB0iib@G6T1-IE z5(0`&BcNz00Y%FQC|XWH(dh&ftstQ23<8SIB%tUl0*cBAC|XHC(b)tPts{gEk&2IrRXxY6kX1iqAS=^bR}Dgu41F;Y66O`A)x450*W>gP;?yuMVkmH zx}Jcd8we=6k$|F`2q?OlfTCLnD7uw^qT2{4x}AWc%>)$PK|s-+1QgvxK+)X<6x~BW z(Y*v;(fX9&dk#qSMEgeL1ya<~zS6%hC1Soz(Ss@BBezS@L!4iVwz8$@VYU=K!j_^( z*;4cvTZ$fMOVJZ-DSDDEMNhF&^fUoQ&k#_wjew%<1Qb0>K+$sq6zw3O=y?K)ULc_8 zMFNUmBB1DH0*YQCpy*Wsie4k2=yd{$-XNgpO#+H`5>WIO0Yz^UQ1lMLSF|N1SbwuU zFS6g>e?W@fH&VM&BIe5!eUK9FbEg!2$oZw{BeoQM%$A~0*i!Try_XW4=728FwiLBwOHnJf6t!kcQ5&`twPj0DJ2r~42qQ6B<|jw7I`F9AjU2q@}LK+yn# zuP8G$_>%(?ecOH-+c?$#O8;?tEE<>^F<+)=XlgiZixdsx{8E(5mZIToDavC@(FnE_ zjbuyFD7F-hW=qi+wiJzJqi7rfMdJx5nm|C&L;{MAC!pvA0*WRPP;?>zMJEwZG?{>+ zDFhUqOhC~o1Qg{HP&Ac*q5=YnrV&t7NI=na0*Z6Hv6C;47Mw8eHyxM3>u-@lTbaH|)nD7oDY}I7OVOolDY}d;MVGUs=nA$JUCEZBtJqR>HCu|VVN21qY!q!Ipy)aRiZ&5Y zbUgt@HxN*CBLPJ>5m0n90Y$eEP;@H+MYj=9bUOh>n+YhogMgwt2`IXYfTFtzD7uG$ zqI(G_x{rXO`w1x8Lhuz`lp5UTfJDEtpMY$TqGJ1u_CRXHe3_z$Q^Q|8B1MmIekppC zEk%#9rRZ_C6g|O~q9@r>^b}i)o@PtYGi)i^#zxV00*am`py)XQigplC^gIDYFAz}l zA^}A&5m59p0Y$G6Q1mJRMXwQ1^g01WZxB%QCILk|2`GAtfTFhvD0+v0qFn?Oy-PsR zdjwz6L#e^UN1dV`24|}j{cev%@25u0mnr%RxIfTBYL6dfj@=m-HtM+qqUjew%x2`Ku5;4AttH8{cniT+{V zBKk;*rW>hasS)#Kio9re-jh-ki0UhODN0~VQIIV~A+{8S*;16qmZAt-ijvq;l+6A= z?A-@=RQ00o{WV#$GL%V~q4!Xvr%^+b-a)#8f+0X?0zncGlnyFQP!TI)S4327*b4%R z9TcpnD0Wd1X)40~|7ZQaN%lVPIcMYDp1b#ZFVCYZzi(zGlguZRLK38?6dOgQ2`CB^ zP?SJGQ6d3FNdy!n6HpW(peRZ}Q5gb?$`Vjij)0=_1Qb;upr|4NMU@CBs!Tvp6#|N? z5>Ql)fTHRI6xAT0D23oFI$7Gi+5idvVZZ8lN{X78#|3MKL)Mp7bVk^FkCrUoAafp4_k`*vZd%OwiNYaOHqHe z6b)cY(LlBo4Pr~tU^a?|5KweB0Y&E!P&AZ)qG1FSol8K`c?1*xLO{`M0*dAkP&Ai-qIm=q%_pE}0Rcq|2`E}bK+$3XiY_If=rRI|E+?R92?0e* z2`E}dK+$pnidGO%bOixLD+wrCMer3(4!dIvknno@0reCqddiL~!y)U-D!L}@UAkS0 z)^NTQUCWlD>)29sJzI)yU`x@BY$>{lEk$eDQgkz0iq^4FbPEARw-Qiv8v#YP6Hs&q z0Y!HbP;?goMRyZWbPoYV>j@~jmw=)T1QgvzK+#45itZ<%=m7$X9weY>69GjJ5m59n z0Y#4xQ1mFlS9EpQ-C%%(r`xYOu9l+Xc03jiSzlJslVR_*m!;?_&X=O6*;4cjTZ*1# zOVM*|DSDnQMK7?WXbW44USvzrRyK;Z5m2<9fTEWOD0-QIq8$Vjy+T0Is{|CiMnKW) z1QfkNK+&576um`2(M|%2b`enYHUUNN5Ky$6fTBGF6unD8(R&0Gy-z^V2LxZy<6-xp z0TOO$?|z<;qUz>x!4JbB>&q(oB zE4CDU&6c8X*eLpzfTHgRDEgj&q5}jJ{Xjs`j|3F`L_pC&0*Zbnpy&_*MZXYGbeMpm zBLoy3C7|dS0Y%3NDEgIvqTdK8`kjEH69g3fK|s+-g0EQl)fTHRI z6xAT0D20HcngkTpBA}=?!B-SWaAzAJ;kPWDxCH-mv@+&#!8!>c>&q&tpWxm6rW7^c zeBBo{WJ^&awiGpHOHnFYiqhCpl+Ko-47LV8hfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4( zq8Qq-R|Pt zgV<6um@P#^*iv*hTZ+zMqi84rMZ*XvI+uW=^9U#!PC(HJ0*cNjpeUPwqLBm?CJK+y#R6ip(aXfnZ9)H}f~vCAmB+uj%T zks|v+b#O{T$ojI1rX_d{-jSkw&X=MBwiHcgOVJFr6kWuYqM2+dn#Go)i`i0i30sP0 zvr#mMfTFns6wM=`Xg&c&3kWD$NI=md0*V$BP;@B)MVAp!bU6Vv zT?7=}O+e8-1Qe|&py*x#iZ&2XbRPjl8wn`7pMatV2q=1xfTB$V6g@;h(Zd83Jwiay zqXZN^MnKVK0*W3d_=?sfxYrmU;a&Etj@L@jm-aLLClW%|msRvkg7?^aQuHk6OVM*| zDSDnQMK7?WXbW44USvzrR<;yvV@uI?wiLa@M$yXz6zw3O=oJErUL~ODH3EuWC!pvJ z0*c-wpy(|EigprEw2OeEw+SeEhk&Bp1QhKdpy*u!iryoj=zRi;J|LjzLjsCEBA{q5 z!B_NDg8QKX67Fcf@A_#es%ZZPEk$3jrRYnx6n({( zqOaLf^bK2zzGX|%cWf#8o{gdd1Qh*1K+%r`6#Ya%(Ln-=ekP#k5CKKM5KwfOfTAM= z6dfg?=okS-#|bF6vc9aM_(ZScUMUK3z7&;UOHoO-6qRC2QE9dmh1pV+z?Py!wiG3? zr6`$=q6h&+Q38s}5KvT>fTD5)6qP5Sr~&~+6$vP+L_kqx0*a~-P*jzGqG|*bRVSdR z1_4DW1QgXIpr{rBMYRbiszX5083Yv7CHRVhiSAefB)r+e@e=*d^vy@w<`cHWko9F1 zHA?g@|3r!!bG{U%vZW}EEk)^UDav3=Q6^i8ny{s)DO-w~v8AXv8$~S$C~8SSQ5FG3 ztq3S;O+Zl_0*cxaP}GiqqB997YEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u) z0*ZPPP}GZnqTU2wQG-NxqX81$YrpE)P>K#%QhgFb)|XY(Khb+*pA-$?d?^~pmZCvy zDH_a{q9JT4I-4y;=dh({C|in#v8Cu-Hj2(8plCP&MI#6(I-h`|Yyyf#5>S*wK+z}y zibfMqG=_kpTmp*55>PabfTHmP6ipzYXd(ec7Z6Z1iGZTX1QbmnpeT=kqNxO5(OHS^ zAp<1bp_GBsPm1Q+kFGCF3|U`R(ey;G%zi1F!TC~j5nGC8vZZJiTZ%4bOVK54DVoie zqB(3Sn#-1=d2AHTC!lBn0YwW5C|X27(P9FME+wGoG6IS&C!lBv0Yys*C|X89(Q*Qc zRuE8h1p!4X2`E}cK+%;16kSC?(bWVLttO!88Ul*e5PU`XiEfqw629Bs7ZpfRg8k_F z+Qg9cWfk3+=neZ)if-b3DO$^xqMO-Lw2m!Bx3Hz?R<;z~#+IVn*-~@|TZ-;vqv$RI zitZ+$=pF)!))P>4F9Agx2q?ObfTE2A6x~li(E|h&JxD;&CIX5cBB1DD0*W3Xpy*Ko ziXJ1NXfpvtj}uVz1OY`)5>WIM!B=#BqC3|B314Bq>Ue_`eQ58Co=yx|UslociQX+= zOVJCQFGX9}QuHEQing+)Xd7FKwzH+^CAJj3%$A}ZY$6qSpy1dV_$X zHwh?ui-4k?1QhKepy+J^iryihXg2{xdk83cmw=-82q=1=fT9lwDEg3qqK^nD+Dkyu z#{?98LO{`{1Ygm!iS9N7B;443DD<2Z9kSm(yDu?heOX0cBzj+dD@9*&z7&1MmZGoO zQuGa5ioRt_(RXYq`kpOC2iQ{d16zuIWTWUO0*Ve2Q1mkaMTZC|`h|d^!vqu^A)x3e z0Y%3MC^}9+(XRv){YF61?*tT`AfV_E0*X!&P;`obA}2|owxcLOKv5h4MJ@qFL4vR7 z^F+7QcSg}07S4VtnrBIQNg?aYDk_=eH98>JU(L1_4EN2`H*ZKv8`HiW(4nMWH0OzX1~7X#WPJM3VoR{ymmd z!=#Y)Wfi3*c^CdDMd_R`MHy@<%4ADX6SfpJWlK>rwiGpIOHm896t!eaQ5G9Ttq3S; zO+Zl_0*cxaP}GiqqB997YEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPP zP}GZnqTU1)^&z0BF9Aho5qw3BliX_!knqR$bF@?`O0=ZS*wK+z}yibfMq zG=_kpTmp*55>PabfTHmP6ipzYXd(ec7Z6Z1iGZTX1QbmnpeT=kqNxNFT}VLDGy;n9 z3BIBMN$y?)B%Eizc0Evv>f8IGf~1i3Wfjd#^8Pp^MYA|xiY{hL(Isptn$4D?IczDK z%a)>fY$=-0mZAl0DO$)z(INth786i(DFH>75m0nF0Yys)C|XKD(J}&xmJ?94f`Fnc z2q;=fK+!4!imoJ}=qdt=t|p*pH33D}5Ky#+fTC*&D7ub-qU#C1q8UkUtzV3yZ|z^> zUnE5p?5F)VB!#RmtLWw=uk#TpTF3cPbPHRGZe>f+ZEPvJoh?Oou%+luwiMmPmZH1a zQgja+Me7MDx|e{W4FnY3M?ld=0*dY@py&YtiXJ4OXcGZN4-ruGFabr65K#0e0Y#4y zP_&tVqQ?m+dV+wWCkZHeih!c02`GAofTCv!zM`9w-0=oTxQ)FpS}R2>?Yp<tY$^JYEk!@ErRX4AihgFJ=nw%#zYtJ#n1G@q1QZ=5py(I@ zMaKy!`jvp9-v}uBoq(bf1Qh*2K+#D8icS$w>JU(L1_4EN2`H*ZKv8`HiW(45)R2IpMg$Z!Cisd=&2BcNzJ0YwuCD4Iw>(FFt)O(LLZG66+X2q?-UplB)qMHdoKG>w3w zd;*FJ2q>CPK+z0>uV`?x`;q|?e$M{Y*$^ozYd_P!C^=+(Sw)v5dtb*%(QM9_qB(3S zn#-1=d2A_~&z7PEY$;mEmZC*$DO${yqD$E*x{QFL%Lyo2LO{_{0*aOqP_&$Yq7?)b zT|q$6N&<>j5m0m`0Yz64P;@l`MXL!Yx`u$FH3Sr0OF+?e1QcCQK+z2Z6x~Qb(M<$j z(X3=Q>>5P{_6v;{OHshy7p+YWSzlJst;t@hCq=h$z7*ZgmZCe@QgkO)BFtFI$Q>uu*g$0Yw`LD7v43q6Y{ldXRvkO#~D@L_pEQ1Qb0&K+&TF6g@^j z(PjdQ9w(sa2?C0qB%tUi0*am{py(L_ik>B)=s5z4o+qH_1%j_=U9vmS014NycR#mC z(aToRmgJE2Wfg5t_VPng^b+Sw(aUTp+QF8hSJ+bYDqD(PV@uKNY$_^vMC5NmptLVFA z@5z!<^gZWG(E+v;{lJ!@AK6m$6I+T7vZd%}wiF#=OVKZEDLTwX(GdcQjuKFGjDVu! z1Qh*BK+$gm6#Y&>(Fp>I{ve>}BmqUI2q6ea#tS_r5DdL?fEk((kFGUfy6h+xm zRE8}@W!X|xjx9yy*-})2EkzaCQdEhJqRIpmRUx3LDgi~+2q>yfKv4|>ic$zDs!2dm zEdq*a6Hru#fTA-9D5^_9Q9S~R>Jw1ZfPkWg1QazQpr|ncMX3Z7r4dk+PVf~aMBF;& zH(-VL+pjt%M*Pq8Z?X498Ih3nWfe7xcwG~vs5$3LQ46*dwPZ_C7F&v1v8AXrTZ-DS zrKl}iirTTI=u9?>+7nRJfqPkRSHv)>f6HwHHfTErR6!jvY zs5b#ceF!M(OF+?C1Qhinpr}6qMFR*Z8c0CVAOea86MRKYBJM;3BwXEoj@DF)R@zVd zheSfwmsK<@;w?{>qH{T4iq2z8(QvjDjbKaB`D`i5W=qjXwiM;CrDzmeibk_hG=_kp zTmp*55>PabfTHmP6ipzYXd(ec7Z6Z1iGZTX1QbmnpeT=kqNxNFT}VLDGy;n92`DNc zplCV)MKcH}x`=?HnFJKgBKV5ViMX2#knk(^zG$cvIrcr;#gUNpWfjehc)OxfG>`M8 zXg*tt7Oj@~jfq>!Xm-RsYJh}quy;Rmr0A#}w?snLmsNB}#H&zFitglmDY}a-MR&8M=pMEdt!GQo zy=*Dkz?P!>*iy8SEk*aUQS<--MGq2Cw26SChX^Qon1G^32q=1#fTG6;DB4Uw(c=UZ zJwZUxlLQn!ML^Nh1Qb0(K+&@V6g@{k(enfpy+A|UslnMh&Q5w6urXvQuHcYie6(&(d%p}dV?)RZ?dK6Ew&WxWJ}R5 zwiLb1M$tP26zwLUXb%BJ?-Ee-9sxz~6HxR40Yx7YQ1lT2MSBS-`j~*CPY5Xblz^gr z1QdNnK+)#}6zwOV=nDdhz9gXND*}qXCZOmWg0JYMh`Z1L2?y;D54|i!0fQ&_Z6suU zSw%lYygMpM(T|)jML)5n=pb8)er8M2A+{9#!j_`LY$-azmZGCQl%fTGd_6om;WN+9@(zK^&&43Kb!y)QZ-MT_ivw8Uu0`m&0mQSaL-QdEZXrKl`h zipsI2s61PWDzK%fB3p_ov8AXoTZ*c%rKls!l*r4FZZ%2q>yaKv69MifR*3 zREL0~GYBZEOF&UQ0*dMrP}G2cqJ{(%H6oy>F#$!X1QewaP?SzUQ3e4;nFJIyA^3`t zqi$kVqv&D#0d*wmf2O~}-WN5EhO95EsAbekuP#MdoG(SK*izJ*Ek$kEQq-0$MeW#9 zbS7Jh+Owso16ztZvQgBDfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&z0B zF9Aho5m3~RfTI2c6b&GtXdnSag9s=ZOhC~P0*cNipy(Weuc&#{9c+Mvn^-t4q-dtS zFB%#RSzlJs@TfOEMT$mnz7(C$mZEI76pds{Q4U**MzN)6G+TlpV z(Rc!iCJ<0Gk$|EL2q>CFK+$9Zilz`ylt)0(R04`FB%o*-0Y&))6crFqG@XE=83Ytv zL_pC@0*Yo4P;@Z?MVAmzG@IZnIydUxXn=&b+wZ$RPl_J2@80G_L)Mp7v>@s|T}z4< za=sKTVoT9twiI2;mZHnpQgk_6ik7gYXenEYma(O1IU7YQ2q?OOfTEQI6s;nl=t=^L zt|Fl5Y66N@6Hs&w0Yz&FD7uz_qU#7Kx}Jcd8we=6k$|F`2q;=hK+(+v6s;qm=oSKs zZY7}THiEBcUew)ZfP{ZAGdN$0j@og1G-Q1_$xd9bcF9I{15V^|^H;V`D5x0ut zG>-JF<~SLVRW%%^S!7R5$H|IRspB|pBRO>)r$gkP`i|2j@NtHOv(g=> zf8_a0#~B>)nmNwUNbeSoGdyxtmg9_!yw}=s#zd;MbDZ&!(d`{)Qsmx_jx#m#Q)kC1 zh&1o!I5Q)c^l+TnkuAL(XMQBq*Krm{`u202C6Uzw9A`!3gF%jSWu(U0j&n^Ucc|lB zAGz;b$5|WsdAQ@;8flsBICn` zarQ;7TjV%jL_WUMalVPvUg9_hA`_N5&cVooD;(!=kH;K2}JF`>@heHwf{83&_LAwZvEkbsQu;WBLh+U+pWh0 zqW0Glj}Juc@0Xnvh}vHeIyDfrzu~bU5VgOeZ)PBBf5+PFK-B({toebc{Vhj}1JO73 znOi6jwZCU%MIdT_QN)#jsQpR*YXVXGquSR8qV{KP*9M~Yhb3-L;B8t>TAR%2MejCLCF_Nkqzv8R+7?KLKwXAtP%j|v55*eltnUcgA}A0OGc`?a4g zt{52Lg?}C1C9Ps$V0`4-N7gKySurpuKJxgQmDkR5DqUkvde)p&!Twl~J$t-=wimA2 zyK`-Ga(ravhNC~vHfMX`3r=u6q_w})o+iandP8;;#=UL5;ZJNDUJz_aPO_jz-L%C!$Eom~ImbSuTR7+beqWf^zInCnc<#O5{O2>gP4h9a za~?kR=ymg)3WLopZJ*C>uH5?N@80FV4vrjo<5P2!nJd?K?vEv7CvDiWe4Dv)i_J;) z8I^3H*FkvNW9Bt%p3#==-`s3&Q*-T(KC}NB|JvPs*~(kZwX?wNNo_gl$1ieIVlUC% zt=~1TV)K0FetIG+_Iy5iZSTF8I2DfS%1z;vrB9!z8aw5^GTp|r8Ws7d}?^ zoNTAUy0HJ^-0q(dA9?r6ub($p$XvAz%hx~W-=weHIb>q&oFCuq+`y^yggNI`bHyrr zWgf8Ca39aE(nG@<#m+r?^IhNC*PnT%pICakdG#2ykGy^559Y-Rnm0&$QaSTqO#0>( zOYgR?Kreh^-D~-=leWIH@Ths#=A;GNFT2;Al%kV*bJ9Jp-EgnHdE+BTp5Oeg|E#|K zXw`nh#GG~KT|0i9>s08Vv*vTwqqnX3z<=SkynXriv+OG*vf-EA9b+eb^voBV=Q@=~ z=_GUAym0vbr7dGuty#BWZDOy#fyRKkp2;loN;q&PXg%+D)vIIHW=(kX*rW;_5i1OP^_yEvrND|5UOc*y17>>Q6^Bjw10~2B@-OC1W%!K>4ehZ(plzGr7HZ* zrAnJi6?;BmP0xR}33`%d+9#Q)CmDNe(UVNllhmb>%}HL-^@t>x>t~;HH1>dbU6j$w zre{*NS+T3ozEayt=KeY@(7qDat6rr@AR6DH;&q)W*(*`L_{FQ5r(0p^!hm^YX2xC{ z6_+hE_be5!>QvEjDw#((_7RR#nah~lC(W_XWJ+S}>6`0d?kcOA|Ln(J<`o_Lzx|(m zKT-To@qJ@0a|=0R%qek!-_2_!VE&lP+PnF*wDf5?>0|S!rsq!^ojxr)e{^p4)Mb+Iin_|W@e-{O|_3sGmrk8N2O1gGJ4YVF}dlJ zb4HJ!Fy;UF)ySWfU;H&OZhU&jX=A2On3C5yZ(43@;p<{%!L-<`#D9(SpO!b#yw3B} z2TjeHc0sr4Q?dt}mt|c4Nz?PQ2X<`HxA{NgW}1;xkZWICj^p3ZW2a9U-87>~+GtB5 zdra=woavJavI}NS&CO36Z-tqgYs`cx1!kCcX@fd<%{EtabmzRulk=vSX7B-Kf_>6{ za?Hm~UQDOkG~jt<{vj3@_m3qN z!nIE4!l(6=|Edeu^y-@{UCq3NHT7!w$6nIYx<3E(S4-^1O7U;2G;`hSnCo6PqhV(C zR5Q}!%X^ip#vUl=zi8G+>{d*VFXL6NVPDvEy|nGTDlrV{UR`rcwl}<6x~(4B=O4P! z|IfZE{tVPVccZ8ODJuW^&&&JQcpE>>SMUGVn?RZLnvJ{!^TzPMuixD1{-t*bfB73t zTt?ad>aF)5d-ZjX-HVtzkH)bF%$87(x`~%C{--M`Tb_>bM~+7Cxh=VP|QyWMoJaV@WUHFL*WGj=b0I`_YE z&Hu}H7=QWwv@ZNtar$%jRDbTQzw(v&SG|7z%Ikbu0RHJ0{ug|!kE>I` zD>>eLk)TXX^M!-VVqZrX!`Bf~{jVcbFrPEVzNXObKYl5}jqs`BKk~(d{}Ianzt{OM z@dEyjeEjrRy`=vm4o~Y&3{~hmA|J<$f=g#`KX8f;qKMh|F?fFSf4_e5zNumRH`s z>i8Q?|L^+D7l{_mIlV8=yKlrTJgu+hyWh<%IK2}t^G`VaFI>4-%!^&O(?2t=ulZh- zfnB?2cgyJE*kfi^Mvv@K{(~)=6+YO!bK!$6vUJI2S+tIvoYBmGT-VOJOs2hXw*AHh zeXE1hx8u<4&Swp7;y;TnoY}na*|sD#EqeA%3ZH%FVozDuvk51(D7;jw*j1Z8C4a)W zDY;`(%y&@4o?T~Mz07Vr74rZuZP&sVC(~S+*yUT9i)Ck{r!s< zzIZ^(D0=By6}}{yhO*PU>#*#OT?WR^GdHbXNF!Mfb@`h!9eb5hV*mRO%rc9vNGC}G zoVgie&j4YChJ3O1EwF3s?1_Ey@}|ZvnxQ9Q@amd$D!fkitu=O`jzw3l3l^H{afLW| z=9yWAPb#y>A70>+Sp?F&6nfSmDdb@87@U9Rx3K9u;EKL6Dt4z-L^spejlIN~8N8fD znlrm`yB8sbf_V-3=kb8O&0|koZVK*HgKy&8&qWflWg3|0$sMT*pOpK4xP{`Iquwok|$^_(-!8$v8uB=%9}-b{~bTKFn7 zuLv$)#Ecu6+qm#{%`#6ZukcO7XwU}>b+9+hAoHz~ef?`>UMKzo#XJ<<{+UGpGK&Oo z^JJQ<96Q;32oO8+>d!Qo{ij;&)-Ad*%~jBADARoG;$P6bvFd@sSERk`(B+D~56ILR z<|ZzBHJgXJpEV?eHlns1+NXKtJ^HkeC}ojRj=YW~#JF_|q)$(c5Kd^_{~ zv@^0&C#Ov|-;vvBO#akHW2dI1j!Q}H*CZv?d<$s1(dG)Ij-8yFpPw@>H+53(lyL>) z+hv&Ke}t22Z+o-s-DbgryeX;q=380KG2gT?IR!a|+kaJep>h;k)xpK0qz{D6{B;%c74h%?GRS@!uBg)hl$&$E8IdG8X%Ykq=9Y zK0M^j!hXc)zhVT@|Ije@lG~3*^&x8PCG_9+3SVm8)(R~{*?wGlLE*h1AAS~nh*g@Z}6YLZJBS9H$NicoHBpRx9QJLG(T@(zxSR$_IvER zCste>f2ns_@N#!a+{%E{v6Xpjj{TN(Ct!X~(ebiU`=<5n*z+tW-u$RxNw-vqXs~Rc zT%dwmF;FQ`IZ!1~HBddSRv^uONB-aaDV~DP&!>t%+O^-aUF?smp9mni_FJ}#{c+8= zYe$N0`?CXO&Azj+`Hz3U*tUZq2`>8cs{HMRf{78@g z$AA0_#kM{F8}lQh#UEea{D>LbKE8{+0b+mr^M@AO_VMEjf9|2^XCdsxU8nGh#Ljjd z^TQ~`{&&4!un+swE0+v5Y~_P56m?a^FrnYsP#e##!r?r&~iyXV`Z z**kPRq<*8h{p{l(wZ|04`P?4O$*oywV)wYMLJ;G8c_2=f7RXnV-F} zrtQ(B*wH-b#FK|<;+hC$ByRbgJZ`|I`-Fbh>oLmoT%f4I?mH^ zv5xljWuNXNI&LwqC%f&x3u}-24NH6cNk`AT9_)_jSkExDyQz*n4MV$!=y-vBxy`;v z$4!Qz-OuWH)Vu=hcBB5Wt$CxcyQhu|&5v8#y-LR&=5=EC9vu_Sk6_zfMaRMBhq3L> z(eXxeo7jDij{D3j*6ts4tXs$5O?8}9*Wa^reAwIo_VUl`c)X#%y+;1=%vAr_TgS!b zhO(ExO2=0-{r#Sf$<6#-O~HaP~!#{SJ z=^qE^xa?woU#H{F+5Y}m$MW<1U0cWD3;aDn$J-bA`#~MQxzyiBbWB^~?>0IXEc5pQ z9iLj^@0WFSR{1+Y$8J~odytMRR{Q$~9p7H#?@x8Cc)h>R(DD2m{e6LscdqsKLppx9 z&fmv$%(%_p?R1=Rhrbu;_{?4YenrQ)_5M!MvBw5~57BYuMt|R=<8Jc{0POAinU0ko z@^?KQM?T{3$vWQsn7<#<@xbH${#C~&Px-sOjx(R}_oX^M_ng09(=oWk-w_>qZT0s# zI$pWm-#6>{?#uq(uVd9${oO#vQLp-;9pgXrcNrb~?Dh9B9k2ex-?!-a{yu+ysbls1{%)k>m@oZ(p^h8A_V?pD9{kqd zf9TlafWJHIIQvI`FV*qIgZ_R?#}dEzyPS?^9r5>hI$m?k-?!=b;jjMwTE~`8y;>$uT;#AE$DspFwIf1lDZ%lvqteSB9P=Z5^fT*qxC{k==aQs!43+sjwbvA_A% z3wDpt@mljc80@}7$Gzs4G1&dBjoZq{+DjyrYySjX>lJZ6vP`7}1a!9>o`HjwL0$7(KWvZz+Ns($4NTgs^cCV zOPQaMx0h?DW1fz8=(thG&vYzrerDZXzK@OzbbQDj&Fkke9iP+jMIB$$@hu(W?Z;K- zW0_=oG*8d|u}AaaRP2~q(ev;-rl>KS-Nv{%)w)vl%-rXR^6a$ANv*ataEjO&B%3z&zQ1^pE)v z&b-z6A0yjy%!f#S^T)iZVt;Cy|J%#C{`?P@vyZcX>Y4vanE(E}%Vn6${QdK_pY!m? z-d6TcWAmT+FxTl|{Yr(qV=?yjybB=k?Igu4GzeC18pL_GaPwU1uJ)=h)lN{yBR@z!@0!AGZIukF)>Xt|OOQ zKOx}sGL1i6?m-jm!~8jHF2^~x+2?Ej+-LqPe*M-KdwC<~aa_M=%)`dsRC9>^sWUO) zv}Twi&&wX;iuIA^aw#U1GtGP&6MK5e=4hWMmd%6CeBIq z#C35ecK0|G>^QvlfKlg8Tw_-6Ln+;ZbvqwAziWp>@j2)88QNn=udT-qOf~}Ue4jIH4xofCWBKJEnU)9lx~;z+0dc{`ojJ^Ormyx=zT-&N+nhXSiRAFbi0 z)a`hvaf$BzwjDo^vF&)B`J*RZZ=Tn%v@nExk#nB#7G_M3yNIvi~ryLSKGwZF-{Bo%sB z>{+o_rPy_N=40=cfJd>wdw5MV#Fe!F3S~Y0X5kuUW;((8n$^v0;shILRx`7y6Ktqi)y!s2u#sjJ zGn+fX#+sGQY~ch`H7l9f(g~(%Rx~rq38rgSFte2t%+M@vW~RAXncC&-HrK0(c3Hd4 z6>F+p#%^=XnrTPvHdn2=cEoOT-CAfT+ik8~OYJ1P&9%$YPPE%xy;j-@cAM+hT03lZ z6LbCAXqUFzT)(#3rR+A>ubp;DyUq1GQ@e!S=K8hQ4%uz4UkB}YyUq3MsO{Npu3snZ zpxx&Bb=EdtEA7<8T)!^bab`C)*RQL#`NdG3nwsm^P1`^y6%5vKKQOm{>FcehGh)9R zw{*Ob5$qm%++4s4>FwEH9vBnSN2f|iUrh-)OH)GnX-Y_cO$iyGDIo(jC1jAMgbdb{ zkRh4~Ia?bc=V&8js5U}|X(QxZZG@bsjgaBm2pOS`kn^<>lC6!9k=h8!(MHH9ZG?>0 zM#va#gyd=?WUMwq#%UvDyf#86Xd`5zHbO4Y_J#Cxe>b;(=?UgzwO}t_$V79G6`T~Z za;%W4p8ds=F(DV~R0)};DIxiq5>lWkA=5P_WQL}MT%;)>Gc_e-mZpSUtcj3Iv=K5} z8zFPF5i(aBA@j5mGG7}Z3$zikP#YnOv=Opc8zGl!Bjhq|gj}wTkR{p(S*neYW!eZ? zu8oit+6cKq8zC#T5wc1fAy;bqLZ-OY%w0z5Eb|U1nCA=m%Fqa26|!=ykTstDrK2$+ z*XmRWxlU6;uGf^18#E>4MokI1NmD}BYD&n>ni8^3Q$lXhM98h$2)RugA-8KICoV(MHI6ZG_ybjgSr62)R!iAse+3a=$i09?(X}gW3q$q>Ye=v=Q>K zHbNfJM#!Vu2zgA~7qZ%IZ*Kq69qfI`HNKFI_TkMTE5{0X%Co;@Lf+Lz$a~rdd0!hLA7~@w zLv3Hk6K;;V{YyV(KlXUi7t+gqO!864%CSN|_3SSzjtSYPQzhgxO$qs2Q$qG@O2`+Q z67r>{gnXqbAzy1s$Tyl2@~tL9zSBm?_u2?KppB3pv=Q>7HbQ>VM#w>Jg#4_HkVD!C z`9&KchqV!ML>nPTwGnbm8zINF5%Q}xLVnXm$nV++IiZb^KeQ2YQX3(sw0$8TyNk{3 zU;1rHYeTWkXSvvMNrw0R`{Z-b9_Olr;ptJRx)8pCt&FLYwesg*WwtjPZ zNw$7-dMUPkb9!mEesg-5t>2uUz}9b0Ph|6((~}7N=JaF&zd1cZ;5Vm73H;{tG6a5e zdRYR$IlUZ#-<)2az;8~kK;Sp0S0wP8(<>49&FPg1{O0s31b%aRRRX^`y&8evoL-&4 zZ%(g4;5VnI5ctjMH3|IY^jZXdb9!w8zd5}Q!2n4L2IB(ms|HB;N&Df68}Jnct*A2s zA2Lg&Z5>V8MfTGR>6m=n> zs4D?Q-3Tb^PC!u)0*ZPPd`0yFZnF7Cj_{opPJJobZAtYCgsd;C=&XQef0cerQ9sU? zqW)|t8o-vKfov%n#FnDLY$+PTmZG!SQgjYmiiWaLG>m|va|tLqkAR}#1Qd-Rpy+%8 zin0kP8c9G=4gp1@2q+p&K+zZiigF1k8cRUYI0A~s6HqjPfTD>66kR|-(If(jCKFIJ zh2Sgd6L8NqK*CR&8SE=X-7TrSK*;*Cit+=V{ihgWiV8Siil(!rXa-w~E@Dg3Otuuw zVoTA*Y$>{gEk(20QZ$E+qPYYV%_E>_J^@7w2q;=eK+z%siWU=4bSVKvml05OIRQmW z2q;=gK+!S+ik1^lw1R-5D+nlBNkGvm0*bCApy(jR$sr#xbcZs2?=x{)nKH?gH?EnA9iW=qjJwiMmMmZDqPQgjhxx{rXOjRX|kPe9QF1Qb0;K+z@w ziXI}M=wSki9wDIUQ38q{BcNzA0Y#4!Q1k@BS9EQ_{oDWvpR{nUlcL&oJQ)aCUslnx z0nh$ZFfm2XalRBi&z7PW*iy8GEk!S~rD!W#ing((XggbqUSdnp%WM?wAfV_K0*YQG zpy)LMie4w6=nVpj-Xx&tEdq*m5>T{@fTFhvD0+v0qTK`(?IED(T>^^UBcSMg0*XE$ zpy)#aiasKsXfFXp9}|2WIr0Y!%h zDEftfqQe9f9U-9TC;>&s2q-#EK+&%R6#Yg((eDHlogkp-4+4r#5>RxCfFdWZ@U#5H z*xyG52q=mp_=@%g+$jb~*#289!Ox`VdV62w#)Yget0)xb*?)>Erls!l*r4FZZ%2q>yaKv69MifR*3REL0~GYH%l)g_>)9>G`S#kr3f zAmLW#FXDsoasFre2km`P{kV|zWfe7!^Xxxm7E_eU`BId|mZEgF6lJibD3dKkP1sV@ zlr2Tg*izJ-Ek!NZC~8SSQ5FG3tq3S;O+Zl_0*cxaP}GiqqB997YEM8>2Lg&Z5>V8M zfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&$9*8pgT586e^I=KHOJjijiA z{Y<}aT*&&eiU!1a_MgIwDH_Q6QZ$GyMT6N=G=wchXS1c~9JUkl;c(Fg*H&L^NKn}DK`1Qg{EP&A5wqR|8tjUk{Ymw=+N1Qd-UplCb+MH2`pnn*y= z1q2jLBA{q80Yy^?D9R(CXet3k7ZQ9${o>pX21vNRy)Wu7MV0J(v}ti6>&q&d5$EO9 zm7fY$=-0M$rNSiWU-3w1|MB#RL>x zNkw2XkF1Pq)Tr6|eX7d;afvc9aM7venoPr1evZQ*<=dXX(fTiH^yjV(pn*;4cp zTZ&$0OVJLt6urWhqF31{dX0dh*9j^}t@Q}h+*OVQVCDf)&jMc=Ze=sUI)eb1Jn18gb!fh|Qp zvZd%JHi`}sQ1mkaMTZC|`h|d^!vqu^A)x3e0Y%3MC^}9+(XRv){YF61?*tT`AfV_E z0*X!&P;`obBJ+<$-ehh@^Ec||2DIOH8X%x3j({SUfTAD)MIOOdv_H-rYJh}u?S0V~ zQgp&;C==F-4_0Uy8zPDN0~VQ6gK4lGsv|%$A}ETZ*D=DJsL3qOxoh zl_Q|2JOM=&2q>yZKv5+EiYgOORE2<|sst2OBcP}{0Yxs0|JT~5`0A^Tz8!T5}s_oU8tn%f2RMHy)SCyhO95EDBbn! zKSdr>l)?E@l*yK&CTuBc%9f&LY$zSMUx09noK~^6atF!2q>CLK+%N+6ip+bD4&3$0)nq-pzAg? zK*FW%-OnH?y4HRnd%7F4zO15IuGhPT6kW{uQgjJhie|H=XbxM7=CY+|9$Sj$v!!SO zTZ$I4rDzcwMT-e2x|D#T%LpjCoPeSw1QabLplBHZMau~&T0ub36$BKmB%o*&0Yz65 zP;?amMOPD0w3>jTYX~S>LqO5B1QcCIK+*LC6x~4Z6UbG@swr05pTm!ezQQgjT{>fTD*8D0-NHqDKfQdX#{o#|S9eOhD1&1Qb0%K+%%~ z6g@>i(bEJJJwrgzvjh}9NAMM`b=}PdNce!g`?*<)4%_j(8?wHvqOGp?p7~+j*n6~X zoG(S&*;4cpTZ&$0OVJLt6urWhqF32c^cq`=US~_u8*CK4NkGwC1QhKgplBBXMQ;;O z^bP?`V`w70HEv|dQ012eF@<1qdjLBcRA7peRT{kw-vLJOM=^0*Xoyd_`ZmZYKjI zoN2#Y{k0U$w;x@X42G;Pt0*DpjczYRiJUJ*No*-fW=m0oEk#kb6qR91QCYSWm19d$ zdA1Z)V56ua0Y#MvD5^|AQ56D;suECCjew%+1QgXEpeTiaqM8I0)gqv%HUUL-2q-#( zfTFqt6xAc3s6GKj4G1V|NI+2|0*V?FP?SpW6_pOUOAL_kD0^QN4*H+zFShT|(t;uD z%PMLT^zQ8_MNK(hikh*ds5x7TTCk<4C0mNJ*izJrEk&)_Qq+bmMQzzAYDYlPnFJKI zC!nYU0Yx1NDC$H&QD*{*x)4y*m4Kpd1Qc~Apr{7{MLh{9>P0|NZvu+?5Kz>YfTFVq zDC$Q*QGWu81`tp*kl-uI2)b_?AmJru1~aATGkae&C>XN7tfF&*-cOySXej4P(J;0Y zoy(S@^Vm`}oGnEo*iv*pTZ*#TQZ$k+MLBE~jUu3EGyz3p2q?-WplB=sMdJu48c#sc z1OkdC5>Rvj0Y#GtD4I+_(G&uT@(3uJNP;?CeMQaEsx|V>V>j)^io`9ko2q?OdfTEiSC|XPK6HJn}Z?i%PP7p=v~r7if-q8DY}C#MR&5L=q|Pt-OZMwd)QL6o-IZ9vZZJPTZ-;u zqi7=mMfVd>^Z)@x4-!zciGZSq2q=1(fTBkTD0-BDqQ?j*+Dt&v;{+5vK|s-y1Qb0* zK+)3#6g@*g(X#{;Jx4&%^8^&VKtRzJg0JY7pnIzU68^yc4aluhG{e3}dodWYzO15` zg5H*1QuH$COVJLt6urWhqF32c^cq`=US~_u8*C|hlPyJWv88Ay8%4VaD0-WKqIU== z+D$;w9s-KqC7|d%0*c-zpy&eviasQu=pzD(_7YI^F#$!N5K#0f0Y&==DEf?mqR$B^ z+D|~y7X%c2NkGw81Ygm%p!<~p5ZMF%)vihf{A z(T{8?`iU(?2ia2eGh2!dv8Cu2wiF#^OVJTFijERcbc}$a;{+7_NT zivA#==p+F}rwAx=Jbl`Zq5uI!aRd~(1QZ1cDDns>iYK5bL_kpq0*Xo!P*jS5qS6Fk z(YHaju>lgczhOT3ofMU|@6p0u$ojI1l0C0)KPifEz7$2-Qe^%yb^jX?q^K-gipsI2 zs61PWDzK%fB3p_ov8AXo8%0$JD5^?8Q8faJsuNIDgMgwG0*Y!9P-Om1LjUDPQEdW> z>JU(L1_4EN2`H*ZKv8`HiW(45)R2IpMg$Z!CZH&lfTA=4iqZ)v${_fP5+dHOAFJygLMa?~L^#Cbq!TD0uk}XA9Y$Ow$KR|1N<5m3~ffTA7*6!j#as22f6=HJNlC8DSg z0Y!ZYC_0OPqJ9Jv^(UZc00Bh<2`CywK+#|ViiQw;MNK{T2?HejrM)j|CPmvzm~plj zvc9aMb3N~aK~i)c=S$IWwiJzEOVRmkDavL`(MYxw<*=n_6kCc$v!!SZ8%4PU6pbaI zXdD4W;|VC5KtRz%0*WpmplA{SMUx3AnnFNP9sxyD2`IXdfTC#x6y+08R6sz{bOMTI z5Kwdx0Yx(jD4In;(ZvK`(NNDlX@G>c+Yg0?Nzqh$Uv!BVvc9aMd7f9}Y$=-0`BJoi zEkz62QnZLIMT^-|bSYbkE@Mm4x`KeBl>`*6BB1C> z0*bC8py+A>idGX)bPWMTYX~U1mVlz`2q?OqfT9}+D7uk=qMHaPT1!CD%>)#!BcSLO zg0EH+=mi3bwh&PCA^}BP2`Jh|@D<(exyuZY@FM$F z$2+9R{?hB~{_j3V3lLBgM?jHFKv9r@B9DNgcmj$-1QeAZpr|APMWqNR zDosF9n1G@L0*Vp|zM=!3TYiL5WdGhZ_=6PPZ9mjbiVs;|R#BOFuVuCrmF0XXD#wY5mZHjRDXPMjqN;2us>Vi9bpncN5KxptKv7KsifR#1RGWaJIs_D* zLEyfqE&)aL2q>ygKv4q%iW(A7)QEth#sn0l5>S*zKv6mYMHvJXWfD--gn*)^1Yc1k z-W_g$gx|0qT}R{n&-9zyPy3t2hpaEFC@bEZlOsi~IA4ldv!$pFTZ-DUrKlZSiq2$9 zQG2!&bznPtY; zSp*dIBcP~10Yw7{C>lsW(I5hf1`|*;gn**62`D;;fTE!UUr~#A_jUs$yxhJMYbiy~ z+P@AN79X;{tfCR|-qz7lbUx=xQ8rtOMzW}in}DJ@1Ygm4@$NSUNcd^{{YAs2sGEI{Ha9+GeOW~d`)B zML^Nj1Qe|%py(O`iq;TNbS(iz*AY;3Jpn~G5Kwd@0Yx_vP_&kSqMHdQT1P<9Ed&(Z zNH+=mi3bwh&PCA^}BP2`Jh|K+$#rie4h1=w*Vh=&pFT zzyJxqXzzaRmZG+H?1&FpUsloU@!pz=QuGGrOVOKbDSC@7MLXG2w2Li8Z?mQ79kvwh zW=qi?wiLa~M$vl&6unPC(FX(+eMmsjM+6k@C7|eI0*XE%py*QqiuMsu^cev~pA%5D zpMat-2q^lJfTFJmDEgX!qHhQ&`j&vA?+7URo`9kQ1Ygms@$ORwNccPZ9_=+L>SRCd z{~ON*pvWVj$b9ycKv6vcis}8( zYED2=3xcnxY{>0qfP@Fx&-BZM{Ll1j+t2h{hCdHn@Hv)>f6HwHHfTErR6!jvYs5b#ceF!M(OF+?C z1Qhinpr}6qMFR*Z8c0CVAOea8|1aY1JG`m-efdQT7no$QDpkRNT05fuP_9MR9}T77-8;1@-s3bM9wbe1H7DKYx6#>(}cl zC-*ZsX_`FF$w^v(fT95e6b&SxXb=HKg9#`aLO{__0*ZzaY(;I{&J_lT=ZqOc+p40S zvM;*X?G|66XoTDKkogaJgMX_rll4_m7PBhKW>!TbnN?8^vnm?Jtcpf6tD;3qqxdapy5o|@n-OhIn5Kl{aS(c%SE|oFEJhxkXiK0br z*DvNj{S7Kw%=)Tm39~9%%B+f(F{`5G%&O=%W>vI;Sry&Rtcq4LtD;rRC|XTG(Ha7Z z))G*(j)0=|1Qcx`py&<)iZ&8Zw26SC%>)!}A)sh00Y%#gDB4ay(VYYo?I56NCjmvf z2q?OXfTFtzDB4Xx(LDrP(E_)#;#8yPUNeR+R7G#eq4vFQxA+o854c@zrmLa{Szi_H zWmZKGF{`47nN`sv%&O>7W>xeUvnqO=Srt9OtcvzAqv%Njik>2%=xG9qo*|&GM+hi7Na51CcbN6aYtn1G^B2q^lLfTGU`DEgd$qEiGEohG2@3j&J1 zB%tUF0YzUCQ1mqcMc)um^eq8J-w{ysJpn~O5K#0Z0YzsCDEf(jqH_ck{Y zqN~iR=o+&s`jc4|{l$!;zX>R^!t@0-iW~$Kg%D8WB%mmifFc(GMP&#mauZM#MnF+G z0Ywo66h#tHF#$zQ2q;P*peT`mq9g)}ni5dd zjDVu%1QfL(pr|DQMXd-ZYE3{<8-lHwUKSrw%)qsUJ{Q7QpN0RoEB z2q@}FKv6FOiqZ)v>PV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*ZzbP&ABy zqMHdQx`lwE;RIXJO<~Td28btC4u#sQqNTDg$_R6dFHw{o=GwSG6^&$lRg}Z5ibgT3 zqS4H%D3@6kjbT>)5U`EkI0*dkoD9R_GXc7TMlL;s)AfTv_fTAe` z6ip?dXc_@U(+Mb=K|s+=0*Y=WplB8WMY9PgnnOU*Tmp)U2q>CIK+${xiWU%TMVVpF z=M4}~B{>wzQbng_U$ijHExtt2(lFO&i&W7v)>lQ#nN`tk%&KSwvnslsSrx5hRz<6r zRncl@RkVg#6|H4P(K-T())P>)fqqKcXe zsr$p+;!6}g6y}Ows)`1D>yy{f3ZJfpoG<`!R~=-n{a znB}VIJ=Rx6Czw^y`^>8717=lpl35jf$gGM!Vpc^TGpnLcm{rlI%qaSdfTGU{C^|(z z(P;vTz969JO9G0{5K#0L0YzUEQ1lG}Mc)!o^c?|3-xE;u0|7-p5>RxOfTEuWC^|<# z(a!`FohP8^0s%!A3AUnRVa}BXi21>pfpc6Hy&!L7{}SdFU!v%@FxMk1RM8dIS4F=w ztD--cRnb*uRdkJ675&MqivD6&MSnA^A}d^9x2qxtGm1h8C~^`|6iPsmi-4js1QfXm zC<-H>D4c+z2m*>C2`KUqP!vT#Q8WQXF$5IF5>VtNpvXr+QCR|t$`Md>0|7lQpl&tcq$ftD;)W zswkdW71d@|MRk}}QC(&f)gz#&J^@8H5>V8DfTD&36g48Cs4)RWO$aDTAfPCbfTAP< zikcEo)Qo_l<^&YAAfTuv0Y$9{C~8eWQ5yn^+7eLIj)0<@2)3fi;m*pdjG`1dpso^b zztW#2L;G;I_!32(!d>mwsG`oSuZp@btD>&Vs;C>YD(cRxih3}sq7-ITK0a0*ZPPP}GZnqI3d^dJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVAOea86HqjSfTE!U z6b&Pw=wzGy1dS+F$ff+@25Ky#{fTB$V6m2G;XbS;FTL~!IMnKVa z0*dY=plAmHMLP*7+C@OoT?7=}O+e9Z0*dY-py*x#itZzzXb%BJ_Y+X`00Bi05^P1w z!kuRg5KlKVhAvk{Y4WmvZ@620iK0itT~V7<(PONyiXLZHMNcrRqJ7M&=t*W(^c1ry zdYV}kJ;SVuo@G`=`PW>xeFvnu+OSrvW8tcpHo zRz;_nQFNMsqAv(2`jUX6GXxZUML^Nl1QdNkK+(4Z6n#fP(f0%t{Xjs`j|3E*C7|dh z0*cNNQ1mkaMdt}9xQ5|;+a)ZZDv(ehglWXWmZM?m{n1IW>s_}Gm07zP}GosqDBN1H71~_2?0e31QaC_ zP?SVKQBwknnh{XcoPeSh1QfL-pr{oAMXd=aYC}L#TLOyO5m0m!0Y&WzDC$5!QAdKU zs9JQ6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZ z5CV#Z5>PaZfTEiTD7uA!qTvJ-We`v_f`Fn-0*bN-D9R?FXe7Z_)H%YLYJhm;Un&ai zqKY1tAt%BuzC_WO2-mo~Rnb`1S4HEPRnd56RWyNF6-{JTMS0AsD4$ssO=4C>lbKaf z0W*pU2`HLEK+#kJilz}zG@XE=83Yu~B%tV40*Yo4P&Au>qB#T<%_X3yh=8Jb1Qg9D zplAUBMGFZiT0}t6Vgibm5Ky#~fTCptThZtU=V}AQ^P%j1a#hj$a*(tvJ2Sru(!M$u*hinb6?w3UFO zZ3Gl;C!pv~0*ZDJP_&bPqFn?O-9py)mViuMptbUy(_4-ioF zAOS^t2`GAqfTD*9wxSgg&JPR_&k%W|@pe^IM_%ba65$qKqUebT*KhZ!qJ6Bdik@Uv zMNcuSqNkZv(KF1d=vih}w4YfOJ;$tyo@Z7?FEFF%MFNUmBB1C10YwK1D0-QIqC*4} z9VVdY6#|N0C7|dC0Yyg%D0+>6qSpy1dV_$XHwh?ui-4lH2`GApfTCjr6dfm^=v@Me z-XqwG9*b~R-D4E}EpQ%JMJI*Si3qp&5=9?IxY|FUiaug}RrE2lD*A+36@ALAiaujj zMV~XPqEpPO=rpq``hr;%eaVcXGXxZUML^Nl1QdNkK+(4Z6n#fP(f0%t{Xjs`j|3E* zC7|dh0*cNNQ1mkaMdt}9x#L%_nN^V$sju8sk%L(kg)plkC$lOFWmZKl zW>r*%SrxgNQ4~f%Q8)ob5d;)P5>VtJpeTxfqG$q&VhAXTC7{SlK#`AtqOt@Ol_Q|& z1_Fx86HruvfTD^76jdUis4@XXRR}1mNos%49sD~W@vN_kYBQ^%I?Sr5F0(4C$E=F#GpnK-nN?8(W>wUXSrs*6Mp0t| zikc8mlt4gHA^}B71QazTpr{!EMa>B)YC%9zO9F~o5m3~cfTA`86tyLws2u@CHxW?O zo`9kb1Qc~7peUJuqD}-9btc$~;v${r3=q#T`Dtv;Nc)xke%TjwiFAuEQPd;S74w)X zN@0CfwUSSrw%-tD@e_s;Cb$iuw{z)Q^Co{sa^aAfRX< z0Y!rdC>l&a(GUWPh7wRTjDVt>2`IXSfTH096lD-lG=hMlOah9s2q?-XplBokML7f% zjUu3EG{IKXEz;TC0P(yezYNk{6|FYsh2}=O#g`}=AL$zKgescA`l@ImvntACRz>;D zs%R3kDw@o!iVB!jQ6aM`n!>D#rZS^w8UaPq2`HLDK+#MBif$#KXchrQvk54gLqO47 z0*Z1m77$Rhkbt5^1QabMplAsJMN0`NT1G(8asrBOBcNyn!B#Xj(mB%r z@ywJT^iqH6YnRrECLtDXW)yuxK+(4Z6n#fP z(f0%t{Xjs`j|3E*C7|dh0*cNNQ1mkaMdt}9x;<+ks5q+$R+_Epa7U>pWqR8^NCOof-93FiouZlvL zRgsff6@@aZA{VnND#NUb+{~&dj9C?hGpnKqW)wvdP~;(?D2jlhXab622q=mrpvX%= zk&l3)vIG>BBcSL80*cBLP*j0{qKX6*RU)9MG66+Z2q>ybKv6XUimDS(RD*z`ID)O{ zuSn-w1H^Mx{>_lTRZ&xOUT95^TYQP4Iv&>(FRG%ttgnjdF{`5b%&O={W>wUHSrs*8 zRz;1NRZ(MRRn&x86(umED3O4oBm#<>5>V8PfTHFE6ty6rs3ieKtq3S;O+Zl_0*cxa zP}GiqqMHaPYEM8>2Lg&Z5>S*(Kv5?GiaHZe)P;bet^^cyBiM@KJc^~# z`ZJ?w00Bh<2`CywK+#|ViiQwSG?aj%VFVQ2OhC~s1QZP?peTcYq7eiXWfD-7ML(K^sA!T=Dg5x9=G@sMR^`q z$3vJIBxY4KnOPMTFsq_MW>qwWSrtuXRz=g8Rnc^2RWyScMKcK~x|M*USp*c# zCZK2z0Y!5OC@LbLXdVGY^9d+gKtRz#0*V$9P_&qUq9p_rEhV66839Gh2`IXafT9%y z6x~ih(Mke}RuODP6Fkn528gGx98gbGMI&Wc?Qx4QQMBIUTJ(x4+Q9m%=niI8w2@gA zZDLkMo0(P77G_nnm01;SV^&4mnN`u9%qZGHK+#SDigpoDbQb|dcN0*wn}DKw2q?Oj zfTH^dDB43n(ftGzJwQOwg9H@qC7|db0*W3cpy&|-iXJ7P=rIC{9w(sa2?C1t5o|?k zJQyOch;|ebL_@xA+o8 z&M4QQH&sz+)b+3QUCgSe46`b7GpnL7W>plMk{O13#}dH7GI*Mew1tb+p6eB*4KSe z17=m!kXaQqVpc_snN?8}W>u8HtcntuRZ$YNDr(A%qGkjXH7B5`1p!4Z2`FksKv8P~ zirNrR)Rusvb_5jNL_kq{0*X2iP}GrtqGSS!IuTIRnSi1$1Qc~8pr{)GMcoM~>OnwJ z3c*%XH_G|40pht);M7w^vGVlhk8+DIQPeZab>^5V>c#r1D4kgq^=4K@eVA2IUuIR* zk69JqwZ8AXE$C>laQ(NF@4h7nM7GXX`n5KuInfT9cnibfDnlu1BQ z76C=s1Qd-VpeTocqEQ4CjV7Qdmw=)%1Qd-WplBQcMdJx5nn17>1)`i`$BiPt?2FP= zk-Rhuofzd7U!rJolvI{8AW#yP;@r|MY{&U5m59x0Yz^RQ1m7N zMQ;&M^fm!S?+{RQjDVu!1QfkXK+$^y6rCWT=zRi;J|LjzBmqSq5>WIJ0Yx7ZQ1l4_ zMV}IEMf;o>>+Bz^saXWJb|h0*Zbjpy(U{ML!czbe@2s3j`EhB%tUQ0*WpX zQ1mMSMVARE`i+31D+Cn%PC(Hg1QcB*py(O_MSl`d^cMj|e-lt-Me7T56gddCqEk`M zxQ~sZ=VV`WS{3~&zdjoh?G|66s7$o0)2FJ)&HAb+j9C?hGpnKqW>pl)tcpC$swj$C z6-6_vq8MgX6w8bvF9Ah90*cBKP*je9q8kV(Do;RB1pQl$fTGF-6jdRhs44+P z)d(o6PC!u&0*c}YD5^<7Q7r}vMcc3R&5^cw z!4~ZnU!tgCv}?)ds;Cj`tD?rts;CLGDoS8hMTyL+D2Z7WHDy*s&6rhDb7oc4f*D0E z2`FksKv8P~irNrR)Rusvb_5jNL_kq{0*X2iP}GrtqGSS!IuTIRnSi1$1Qc~8pr{)G zMcoM~>OnwJ3IRoa0*X=zC<+j4MK?w}_ZlFc#qzt34OGz&LMkoVExtri?`YRsr&UoO z)>lP+nN?9gW>wUmSrrXnRz(AuRnZ`3RWz7c6%AolMMIfUG>m|vn+Yhog@B^r1QcZu zP&9&oqD%scvIr>3CZK2}0Yy0k6pbRFXfy#uxdarAA)sh10Y&2oC>l>d(F6jDCK6DT zM?g_N!B*5O+Ii6c@gzqWIO(dWrW{>Qigt@HQ8XpmRrZW3n#%gBXd1IBn$E0>W-zOw znarx_R%TT+i&+)TW>!UWm{rkSW)u|>P&AK#qWJ_AEg+z1Apu2;2q;=iK+zHcik1>k zw2XkFT{`fTHyT6m1~biVC8gtql-Q zZ`l_Ws-h@4y1paYExtt2mT1?IuT{}j)>lQ_m{rksW>s`2vntxbtcrFrtD;@Zs^~6e zRdhGAD%#DAqI(D^x|e{W`v@r7LqO5}1Qb0$K+%H)6zwIT=ph1%9wwmZ5dw-HC7|dr z0*W3dpy&w#iuMsu^dtdAPZ3b`Gyz4=5K#0i0Y&=>wxUhZ&N&8%CsE#Y+^mXb%f9Hj zXt($hMK49Wc6_Uf4zRu|I>@YwUS?KBhnQ8-VP;kI3bQJDm01-XVOB*)nN`ti%qV)D zfTA}DD0-8CqPGYrdYgcvcL*ptMnKVV0*c-xpy)jUicSzv^gaPa9}rMxepvnu+ISrvWHtcreMRz*KDtD>{as^}+XRdkLSML!czbe@2s3j`Eh zB%tUQ0*WpXQ1mMSMVARE`i+31D+Cn%PC(Hg1QcB*py(O_MSl`d^cMj|e-lt-#pug+ z6gdbe3L&7#NkCC3!B+HTv@_xdqv#ERbB2A9kaESi#g`}wk8w3TtBN96Ulm0%t0E7x zDvDxOMbXTvD27=T#WJfRFS9E0F{`4o%qS{HK+z2Z6qP5Sr~&~+6$vP+L_kqx0*a~- zP*jzGqG|*bRVSdR1_4EJ1QgXIpr{rBMezg_)h3{*4gp1V2`H*ZKv8`Hif$y>irg{I z-Uf(gulxigEXIDNe~*xA5aSkKqNquXYtlJYl)(C`D3MteB{8d_rp&6S8M7*C&a8@B zFsq`L%&Mprvnp!MjG{IK6tyLws2u@CHxW?Oo`9kb1Qc~7peUJuqD}-9bta&w3jsx4 z2`K7DKv8!Bih2-GltMs}pMauN0*V3z6r~YR)RTasUIbfFqZsEM28ib~d5zXs6-5iF z^cc7J5=H%DTu+}@Mg3V{6%AlkMFW{t(I943G?-Zx4PjPALzz|4FlJSBGqWnXg&9S| z2`I`SplAdEMVSN?Wf4%6O+e8|0*Z17C>ljT(P#pSatSCJLqO430*b~FP&A%^q6q{P zO(dWwkAR|l0*WRPP&AolO{nN`uP%&KS>vnra+tcvC^tD?Egs;G!r70qK-Me~_aw19x3g#;8WBA{q70Yys) zC|XKD(J}&xmJ?8P8v#Wt2q?OpfTEQI6s;nlXf**vYX~S>OF+>&0*clXP_%)7qB{sE z+DJgrCW5VKYK*hiFGkTi`8nD&Rdi5(@o{sETYQP4?J=${zpA1;Szi_HU{*ytnN`s) zW>s_-vnslqSrzSORz>$PtD<|ERndLSDB43n(ftGzJwQOwg9H@qC7|db0*W3cpy&|- ziXJ7P=rIC{9w(sa2?C1t5m59b0Yy&{Q1mnbMb8jW^eh2I`w1v|j)0=)2`GAjU@O`h zh>_=rFS?dWBgPy~?bLjxejDqs*%4 zHD*=xIxefvno2vtcreORz>HSRngDPs^~nk zD!RaoqKgC+{X#&|B?5|mC7|ds0Y$$NP;`ZWqTdN9`h$R?s{|BXBcSL{0*d}3py+P` zimX_D*^VLy0YxDM6gdef3MHV(MLlR<4 z$P??j;hHLnVtrK<&8&)Im{n0Mvnuj3t0Et>Dk{sYipnvoq8pf1QF&$*RUn|KA^}B} z2q>ydKv5L}imDP&RE>b5>I4+kAfPCYfTEfN6xAZ2D4u|#+5{BUA)u%(0Y&u)D5_6D z(TxNYH6WmlR<4C@I!8>@QW+l=W3n zGiFuPoLLpMU{*yfnN?9MW>wUhSrxTmRz+=@RZ%-;6x~EXQF{W4IuKCQk$|FP0*X2j zP}G@#qAmm!btRyv8v#Y#2`K78Kv4<-MScQ`QVA#u5KxpxKv7Quih2=HlukfVZvu+? z5Nt&WvCbj`#O!ShoJ3Xhlni}i-Qr6W4UBc|vg8U9tMiEdnnt-BQ0*b~EP&Af+ zqHzQijVGXJ0s%!62`I`VpeUb!qDcf4O(vkIfPkVx0*a;(P&AcbE9xKXeANK)WXg}u z2B;#RywaZ*>lR<4=+;=*w;`%%7VE2`+03eF4zntn%dCoum{rj{W>qwwSrsi{Rz(Y$ zRna156fGv8XbAyDO9?1iMnKVW0*Y=UplAgFMYj`Bw32|LRRk2RCZK2y0Yz&GC|XBA z(Ru=kHV{yB2LVMJ2`Jh`K+$Fbinb6?w3T2hni1>tIE|u0d82WrDtb`%McZQC;!70m zjCD13siIx1uZr$sRz-I+tD@b^s^}hORdg@2D!PwZ742bGMfWqSq6e5!^dJF6dkH9d zh=8Jp2`GAmfTBkUD0+;5qQ?m+dV+wWeFPLeNkGw41Qb0@K+!V<6g^8o(S8Doo+F^> zc>;=FAfV_)0*YQDpy&X>R&-~qv#$Z-sV2Lh9ja)Oyhb}1>lR<4=#^Mkfm;>5%KED4 z2(v0W%B+fBV^&44GpnLEm{rl6%&O=uW>xeyvnqOr8AZnkC^}9+(Ypi`y+=UN2?C1V zC!pv90*X!&Q1l@IMIRAR^f3WNpAb;=DFH>F5m59w0Y#?>C^}6*(H8_1eMvyk83KyF zBB1DNg01LKtaFnA;^`p!qQk0aj~rcp6YCaVqUeWM*R$cO=ttI9MQ52+(ND~(=p3^u z`k7f3oo7}>7noJiMP^m>3$rS^#Eha}2`IWuK+$gm6kQ>p=yw8&{ve>}Dgi~;2q^lK zfTF($DEga#BFn2U+fn2opeTfZA}0Ywp#&7U2q-E;K#`k(qA&uA!U-sfAlQn&i*5=Ajy*WZzV8LfTG3(6g45BD1l%rit;*ZdyJwl9U(ikf>}-J(@d3)WXfEtyqOD`r*HnpqXKVOB+LnN?9cW>s_(vnp!Otcp4?qo^YR zMacvdbt0gsGXX_i2q@}GKv6dWindisrJuDk@@DMe~?d(R^lAw18O^ zEo4?jiVrEsegjp3WWk%650*aOsP;?ssMJos>x}AWcl>`*6BA{qB0Yz&FC|XNE z(K-T())P>)fqs`AvnsleSrzSJRz>$StD*;(RnddYs%S5> zDtd?+MGq5D^aue(j}lPy7y(6(6HxR70Y&==D0-5BqNfNbdYXWuX9y^ImVl!D1Qb0- zK+*FA6um$|(TfBWy+lCK0RoB+5>WIq0Y!%hwxV5L=S>EP=NEa`@h(;LtNb|Ru-7fV zMA1>N>y`?t=rz_?MXxifqBodT(VNVw=q+Yd^ft39dWTsR9b;BS$C*{pyUZwhkAR{R z1QfkbK+y*T6rCiX=tBaEJ|dv#V*-jkA)x3}0*XE(py+b~icS$wbee#oF9<05l7ON! z1QdNmK+)F(6n#TL(YFK?eMhhrz3O$&H$Xh0@|TB>sG`5kd7&#a0rFsq`A%&O=YW>s{FSrz@ttcor(tD@hSQFMiXqTdN9`h$R?s{|BX zBcSL{0*d}3py+P`iY%YLY)6rUfT9orikt)#g%VKYBA}=Y0Yz>Cioyse3MZf_f`Fn( z0*X8Y6h#qiML&9-M-33qd$KP&tBM-SGg`FIExtsN&*%ESiYhA0`l_fLvnslQSrwIM zRz($ycKv6vcis}cotq&IA;7A)u%$0Y%*iDC$l?Q4a!&QV1yW6Ht^&Kv95zqBH`EdJ<67 zi-4kZ0*ZPQP}GNjqP_$a^&_CDKLJGp2q+pzK+zzAt*C|1+1~*1Bnq6Cs;HLiiw67L z;!70W>~l?tQ$@G1zA75dtco(2RnZ7$Rg}rBin5qhQ8u$G8p*7Ra+p=oC}tFmCZH&n zfTA%36pbaIXdD4W;|VC5KtRz%0*dkoD9R_GXc7TMlL;s)AfTv_fTAe`6ip?dXc_@U z(+Mb=K|s+=0*Y=WplBAsRy5S-++u)u^5plfhpD2z@)u=i``qG76wULwo~xyb=Ci&k zTEMJ|7BZ`%Ma-&bF|#UK!mNsxGOMCx%&KTPvnslc8AU4yD7u}1qLl;`tshP_%`BqOAlJZ6ly)I{`&^5>T{*fTEoQ z6zw9|ist&9rwtI#k7f)lQbm_!xXb4jUskLY5*i=gu&%@MK5c$vYk5BsaNeutZOSlj zHS=oDRs2zvQ~IM>StN2y)_0})_QNwV9VO%eQ>B{ zZS!8Z*|K(eTV+_*Ztv_&%i7~Tlxrrodu4V1>ZWwD>&v-u>Z&}ZKYvx(j z0q^KZmUYEyzgW&Mh*<~IDhi}~7=3#L79=pdp4i2CEZ}znvKKbv+ z>pOh%|4BD;_~btXPIUO>e{^l`@X3G4+1lZg|5NcMhfn@fykv(@{#UcE4xjwDR4ERh z{J%nJ4&Uzw%wyv4$^Y!p-{F)0nqjcRC;zto%?_XZ>4+&lBf5eDd$h zj(7Ov9|+BN_~c)BEOhwfpXi(J@X5ciHp}6YeF~+lcH8an$zNC6T*A>J zdX=eRa+dk1U@%&amceFK_{gl`Xk`!O*E-G6I(mV*K)`%dbXy(r zrGSyjziTlqS@AM8;_E`O_B-sPzp+of6X;x8W^cB55M zo(1LN$L))k@jmeCcXv%UmoMWz{`k39%_;LW?%e;=adWDlX^%X;=~k=CLS4&zBW1kL z+6z6FtW~ z@U9k?lrj#7zpTTYaMv_*f_Y@a$~qz=?Ny|QM_JA=t|2lqD$*0#+FUB4!gZI5G?yy% zbv!z{>@ORoS7}DM%4ogH;JGDN8KYOJmx?tjxk_$_H_F^T`O3cF372J+)$dKeNV(>v zZbHXOH&rrQKodvDO5Cn`mAnpLndFKaJ6Dn$QNHxWLn=Jo+1zmzO1G-!YgJq}-(l|H zq~JYNY59DI6;g3c=Zcn9*_>g?8J1Or%b3Tki6vinVs!9pn%gA`&8K&(~o#R}=iGYW|d)Yn%lClt1M5l>R6^A2Sbv(;8`332|IC z530j_n9G_^N0TNAlQR=W733!rOwLZ2oKcXSlaW6;uP`UOFlS^!_T(A)g?SRPb4E^? zoKsNhJh{BNben|y$zvvrDI7C3$4bb}n~;-`IX-84LX+`%*_q=L3UV_i=Oj$dnV3_M zS&)#^G^3z!%E&Q!359uioHy3o=LHG<@-ruo>po>-Mt}3YjP5;tNHx6HPPt05e9e+D?{vB6S6II-5CMuCo93;c}F5jy4x? zR%+sMI7g?-skkx;E?*fF%cPm(PR9+dNLj?V;$&fZaEvo&Hw|7aF45(yZl+rQiwh^z zOlnlq6&LUFIcLZ<@P+={^1ohpthrs$=GMzK$}Klj6Ic0Kt|(`XIG5L1Gu0LCd~t3Q zS9qCPuJY#G${m}#$~&jUnULTr?{Gzxb5%Aus!XE&U6i%I<@)+92gf*bc2m8W-k|?> zu@3*cYx{p(>?Zx9WosrhG$-5Z*H0*8Zg6!IYL+SMs$9dINC@az?Oj!Z-${b2u35&K zZ@-MQdXwOz7vk(R%2nRnrVxiKToz@_E;=+s9@vmF&X=t?`%JT1JxR{z?2|2<7oTj=rTApa)_Te2t!bTDIkCBYUbilKnIv=JF==^u`AJsa4B6^+ zKVg4?uB_Lh_=~n8H7ohzO^d&Hmr~cOx3VcKv@E_*HJH1>Tx{f& z2@_`6*QA$i&KK^ap;hq>F!yTlH5Y%8=6sE=C3l9o3-p5KCfj$Txfc6GshiM>Rn46j zJk#8Ju;FWOWu->l?zbSYjVsS97q+;Ck(7?gUF{=a%^>Y9@^Wwd3U&nJ$~ z$;g>Fa!lsLjPZFBN88_^c}UEcH&1}29uvK3%}Z{rdHn5*7k_&|ODy^B+7y2$Nd~eN z=r$yyQ`f%1^~^)7-=uM@r@CIZrX@EiF8IfPFiR@AA)Qqc;LO7q`~nCoHe`#H?XO#K z?Xj}S1TUJXS7Gq#E$Li*n`B!JUZ_*ajq8eqW_n&R4!(F&>*A|QD)EOGxFnT;G~b2! z(mgv3&gjysf79R>L`$&?vwsMlkyOGg$vCrHB4?J!OX|*JR058N&3rfZdYq8QC%A9Y z$GCV$l9ZSjJj3j~DK4DGa3$v@|!Q zL@4_|b8p$VPtKMrGE4o+Nd|2&@i>}2kDk@6_%1Ye1Q)kS$aU}_^B5ODuC2}emsiZ# zfYEh%ijaMZCbJG#Y;4+hq4~1G6Xu@ayppR3-XwW8>2HoN_42G}9*1SR8^t5l0xlim9r680%@JS_)d{W6n&*LIDIk>WUo(?X#-;<1D`&#XX_5bo!p}wdr zd94xL97>3o?@#akBy;Ry-wLw}&=bXvQj)={mn-!wkfduEI3;^@NM_K7Ch$2g4zmYL+9DIAkGv2lTU z0ce&5rj5)j%q*VmyTTkN*e6Q1ilmawLd5^uQ=2Wn)YESue0Q!QNRax5ykg* z$q{3cy$#uqAGfAtJ4&)Qq~hn+;C7Rdas3lNhpZ(>teBL;tMu;uil5MvI6y5q&MY~+ zEIGO~2dnV0H#E6<#TyAnrX>fBrH&anFfBPiWSf&?M*EIYi1xu@@H>|yQawlweuwsk zUHo0MAs1VQvK*O?E8e$q09ta8SaOV*RI=m6ckzQ?d^B2om|1*8S!zQn*&Ira2YIYZ zjt0%MxGl;)q_lc;>C!f?zHB<3CQpd#HX$o#9d{k)<>xir@pa9a>_d&r9PbIT@P=mS>A#(Kj$((svwrUB`3vc z-pnig;VgbH->y!}{0yzshtrbxB1=A;mif6_sSl?WQ)-gyzy8)ZE%Q!isSl?mZ_bx| zIISBj^9E}0yOzhnXKsI;lC#av`z)*3Kj!ZLn2X=@G+i$LAMYmBF0^WoEOlsS-eW2? z$pN6*a{lAB!gWW2_A{P&3))j}<zOFsb(BwTXngwlRY2Q+-3g_IyZ}*KW4w@LTL<=L~z9 zuFIvF_PjxtZyV_H{d}U!a-;0IrY?u(+Vf~#?lc>OT>c?lely;lf6-;5JbP}V%gK}M zd9E&>DX`~Pbotj5dybrHFS|~+mwj}(e5O5b)a9{R_WYSH%g?pvcwOE+&z{HV@~#E; z{D>~UTV&6_>axjFdv2%8!sYfnPnY{w*z*xxTC40iN|)W&*mFN!u2^T!n|1l_275lG z%Zi)qxsEP}Z?Wfby4=0Zo*&cY59TNTa)1A(%fwyw++LSc@3!X!x_tf~dwxxqA$#mO zMwclM*z*8guH0+STXlKjVSD~Umz5v0=X$yv@q|53(B-{P+Vc~-Jo~gg|E|lX`|Y`- zE~h_l&x>^V;*0kDhAu-7+Ot=esfX-&kSvf9kU3S$poH%US2_d6_O>K5x(O=rZgV zd%i)Jy?(XlVY*!Zn?3K+<;UhXEX3cpx{SMK&y96C>MwgP(B)op1R|GzR+kse&pu`T zTbHfPPmyHqrpq~Qd%jJVhs`f&$oa>08Daj4q|6m`+1vcehRnC<@(%N3T$%6I<)`MC zIAs1_m$l4qbI6>a%Utto9WqbR<-_LpJ7j)NmzT^hddO@JJA=!%=9dj*?xD+~ID5Wb zm#@~c=l68k$owc-F5gC%-E^5IOP6I0(|MFEBP?sIF7vd{(&aK;uGjN7>2kaF2Xy(g zE)VPSxGq1}<&V0&qDzWT%m$AAmr^{-(tf|W| zISw+{@6n|>3<=H^bs48ibGQ)f<}e_*OweUOm+873q|0Ht%+}>-T^8tanl2aUa)~b2 z>2jkk%gEB)$XK1tBKY+~by*F!K2qLOH$TW2m1kB7p3cn5nw&GW^tt9|?4`%d z$#PJw*K4oypJlxKgj}!D+%T(2w)t^xj`?XzsjoU}a^?hcp-z2!Hpwh3oIECLN};*h z|MiDCL^NBqeGD!unM1JaKFnPg{HSUEl*>8o@josn=gCJs^C@2b+vO6?W&ZhfOaB^# zJa+QY$b6c^Xe-%#%E!`94y(0UmN%br8Tpj2mtsD-4d$d(-`wy9#xEb7>S{vi>pNhs zZ>I@zed37g>u*l8jyY-dZD1}}Dsa*qQeAhsiwzytgR+8taJeiqm;SmV0_OTmldmhC zuRFz@W*u|V+TO@v#mNc%;Jis@E`5FG7yW|%<@zGcC)c;soMs(!(t5#MpKK?5aNa@_ zN?%`Wsq2d}=W%^o%xTt<>v+pt-wCsA@xgg_m{9uq;>`8Q<0QAwY=Xttcdt1u>xc*W z*wxfw^_3lse#m+9X%1DcyWB4w99F7cMiyM|MLo?~$sHZVcBIMoAs^<@<+|Hfzts0z z)||)p`-VAfEa#g=@T16FUt0#Vl&>ovvNYt1Kb|+2%QvxtDe|gbu21fFxlhTr0)#$yf|aZp(|%&&1c;9RP(2me7R!tEmx=>=WcXdJCT0rK%eA`HJYwU`zW*Wi1^$)9fy8N&iO<7;G%lzm+F=|b*1)~r>^XM z`S6vhMau$*uhc)iEcNh}vj>*?4_`T*zcl5W%)fv8>+keSMb0yshp!y#b7ssfAt4tM z=civfT`W!n?mGk6=lu|6sGja?w8eN>}FGvFV5?i@9&Zo7`w$xDHjhq zC!_|hQo_S;PIqQ!`S`_tRUxi(3N2Q-}LA zQsngDTB$v63A}P8wB{>UPA9&9B{a!uc=h9pnp*CyyT0AlcgnJ9@s7cbHtgfvbkIBN4mFs?Q;HOncSo15gAb_5SyBkE%%$;uj!YnW=Ew&>b)-a ztuGK3yw~Mk?P~7D(BQppKb|Z5g{P#QwqCMg%O^X`!eN=C1E-_N*?G;ye*M!vzWdME zKbBo8m+r8Ntb;{X(V9wD=o+sz|Eqm9629;7+U5s(7Ct`zQtFX+QjawGvt9Uz3%5pm z&~w{O72+&M(db>X9TguM@#fG!=6n~{FRa6dk+@)QYrnNMcfc3d zzMlWVk%h0M?Z5g%!+tN%nsQ}Nb!*Gj>@*;&Ak-zrPxk7GbSS>EqEVgo5xO+Rtv}}(JA+hoaUaXkb0Mq zpB;1_S}V%XlZme^r)}l!2f0(DjKnB^bZWFn%oi!oe=GN?+*fkHe)9H5>3z>{%_w_+ zqecA&744V%QSQ@+yWUpj-1$##XxQ)4Q{Np~^rJj_>;2ify{rqYDc)Y>)~&p5ds&gP z{JQOBSzz%$wwL)S0kfUTEnbkeFt9Lnk$+*KcL&0aXfWr z9bbG=T2ad6)Pq;fjxe9S4_-N)95&(&BXP4WagcqvxcKR5(^GQ&Co^9*mo%TfUpAMF z9r0dPWbPII!bon2)oDToka(V~a{A0^$lhUHpmg5g3UAN^lxo*p8 zl+xfjogD&o|Dm(ibvkPWs;9LyIvaLxncC9d>R)tDyH02Qf7Kavoz5EnqO*r&e0>>Eg|!;}2yYJ{#Gl%;e)s+67|91oo|~RNXo-&)M2x znPri4fx}u?y~WyuT`RxZd8GR8KLXv|vYnRRC#1#RGN|Qk{{86-MvXq%_3p=SHQR5f z*)Br;u2fg?b}{$cHw&$gUjONlMln5?|B!wn>6)0|S!{ksVEc9Ew_Im_Q_3CJncomt z`w#Ogi_Nb}TOC-Py2hAa6Lh}XY)xzYYlElP1lFdm^{)$_9$af)+8U!Rw5HkPCZ5pe ziIu_g4(s#8ZT=O36{)ueTdnvNsp*%Nj;Lk!%(A5~3oK7v?!PT~UizigBcv@2EK6PH zUmk3-eT`4e^~>JGelBAhTadOOCF|d}v76;`z3Zf0j8Ci;KQn!1+93bSSE?S^nDwvQ zT5zk(53UgxKQS$k`i^XI|JZ`{xuk#B%N}RnD zuDdUW`iBLErQWRfh2Pv4n~U#@LFU`eQo{jjPidq zyZ3&1-aC1`qhoDSM(n^}mJPoc+Gt;1d}G{$HI=thFn!tEX%c@=Q2R_Tl~I z$j3g)+!olDYL1B#xB1P{R{qw&wv=3zH;SQrytF8uj4}N1<9A^m0gu4$4>It z_PjV{%38BEt}|PsxR6`SET_{iC1);7T@#RFPWvcyaLrXIs{(V=R?8#jHIH|(Q+pd^ zn_cQ(X0}3m8>}6_%pBXT@69&5IItvjiGOL(aPq|y!LPa~usC(Ge@U>}TV9vT@eW`7 zg4Bg6X50NA3hP#iw7l z^%m9bd2#A2bNuQ`O*fClfmC@8&i9+|{PYOF-=Fd|k7$S$&+*hy^Oz6DG5cJ(rN300{K*>+%-A;}dfTn%Yi4YG?)!FoQ?{Ol!t@QC0hbp&9p7}D9L@gB~{dmip_zI!ADw-@#P*}AH08g z?X=dvI%SR7Uv>$;c3K@+5qwQ1kA)anR{U7VbjdJgw%<_Rx5sj(f2^{ zbH~`gxYTj}@%p_#9(?W?6BwI1);})TWSa~#&u#9cxcGsoqs=zi@Bgt)cDeXz;o!JV zfwW#d{r;XOGuLI^AtwItFnf(y9*^$9Yv&bV-$38ge*S*J=8NweyoJ0X99*ld z*`|0!$v!tVcv<#3DgKmzKh+;>vGJXQuPE8;nA_eoF20Muo_&lO8}FBMB6H1FF=DGD z_zc)zo&l?wy~EMqD`9z5%#p3-i*J=y!94r(+;*q^+}2kfPjAZWnR1*jk5H$JYsyBY zcG1_+@)$)JHGNKt`LC|sGkQqdcOFmrtizMJyQW2sx_Qu$@$ZIp-yh=J^?UUlFUvNy z%wfMSG0PCyMzT(ibF69k%aEJ9R9^MngfBR#SPu>c`GmcV8>&j$3J}f zn~@`5z4TQ1XSe5jE6?5fp5GiB7Og$KXiGZYtA`Wjuf-)Y7B^pY(}wyVK4rv~!>W4}H5I%DPH z^R9a~E2^7(`R|)#zdbg%-yR#>Z;weGE3cSFjPcw1?dx9$4>o(*a!axUBU4BEbAs2N ze9@hq?e8Od``GLe{c>-%uD$=R9{&#Sl{mtx-|m=I$B4^KNjr7rz?z}vYt=5YUoQ_1 zzD|+n9r@mPoh;8?{q%K;JSw5Jdh6>H_DsCK?tJ<5tX6^4?ssRk>29_kITAP^d&y?G zjusDge*MF4f$pi@{XK%WQ;s((mamuAHPB6-84|n7Eza*6=<4rgo=xoU)$A+s!)gw$ z6)*RMWjfcGUa2APISqU$?Of(VfrnEc_CJ!cH~1_id!74= zpP3#A>`swq9-f(Y2A?B%X4;yv?YdWNI|G~k@rrG|zN=@prq4a_o5>{oZ}^A`rsW1m0YKR>V_bwRMzil1+`El+Ru`9*=E)Or4S!Sj+Y zrUj1_=LY7c7Ws>U&3@luPHJY#o-A|Z8<&}Sqj~?Z_#L|e_Wo>I+A#B)rey!U;~#sp ze#Luyxfkud*SNG^rS@JM%pSj}X8NU${d-=VlW*SL9cJ#Mwj<1YCv#ewJkp8gKIW1@4o%>c(Z-*J}Ot2XUDbydF32G;+vqO*5-Zh zadXULm6(2hgr_L3%f*i;rC(~^Wn(SVTb;VHuP92ka31Fa=CnM*midfrkkUXN@x%tf zE%e4z*;@=T&vQlQwbQ)d_9xrhxBnkw_Zc2lz4v_^G8rbo&;%7b2v$H5DWXVK1VR%F zh@uohY=9zGP!PpV5gQgnv0?9G$KHFz2KI&uih})F|IF{)mtOb1pW}WJ55FH=d&lIQ zHM3@7=Clu*o;rC{#k5-+ZgofR2FIt{PdR|)#Jyd$1YoY%);zr?o-+K{pRfX?iCAePFG^HZ_2L3R!q%4mS-PJvX2Sb z$MEc7c}<^ddYAT)&9AAv=Kpwvb5+$p>wDO!+5CS!s<|wE7bmCh zMfwiDJ2CqlyUp7?$vnLMvb7(4GCO?_muDZof5WrCPv67VGkeWU|GxESrtf5v^Qyjw z=`*T&uBCVB*_I)jpOXDE|GxE>uG`#t8#Svscb6ak@7ryksp)IcB)gqvUybF%r}kP= zb@fuZ7yKq&k?!#Aq5GG0UG?0wu0Iamd|`f=SNDINIR{sE{$FR#o&V>|nO#+lU%lVts;@+0kIH_17LM#! z*}v)*vT)VQdoBFAQL|CIrTeZvy}oo6_n+5$(iPXs)3Wo)Eyz$B(|4iYk7JM9 zIJ+f|?VN6%nb4!M^HRqFE1Ohw&d$jdS7qO`+p~`a*+=W0E4Qh-dQX49Q~I7R&pwu9 zA5~}Mbgxo%mTpof-B-8HzAm#zFZX=Mj=!z_`?Znfm)396?eZQ&cRH!?@R0szoxOFf zLl^DyKza9f9!$5*bbp#2JEq&z$=PjY%sZ>U{&0Bb?{cl`KHd6;>o?o3$^-Y}?I zv-1{ya_~AEO-i@r^Q_Zh2xlKcw@*v_ZR;wQ6(Aq7%=X z|JwaO@4e7@q1U%R-F-rK-13#@Uvl)`!>*hD=KUk@9#;FEpC-P$`)faq{4L#f(``IG zzD>8^CfTct>9+jj+Llurj*VxW(z9^KG|tY|%O_6ie{8>Fd%ZK_qLJyDsTEzbkNRFa zOXtt=Rp0T_YYOQ(t|R&${*TAK@l4&m{eC=p!jPsT`;Dm_)wlE<*NSTY`%F9hU$@cv z&4&H!%6@3}jNSgdOV8P5pWUS9&9m1Ys|{Gaw%dTp!Rhrz_YUd&U;n)k4}Z0GR(1v6 zx^&Cfy?2dOQ+sCL!)n+4y#1C}rR(sfpN@Pxo+))3IdfvCeotq&grEK|w~==LNc`dhZA(xb?(*|Q5xtL}GPvu;}T z?85wXEfCKxw5V*^r)BR}|CeVMhGo{DpYGX(y1nbAv(tZ`U2yAmjh?T%M&Gz{<35}8 z-XyNk|6bE_aWa%FC6~!UGV1w&Ij5{YtN;7$$JM#)iRKsQdK^@($?$69UmSVtqVs!w zGjH^`nZtK~ZqL<+H#qmqK0D8U^2uNO?b2%Us+s-Ermx@T)c0mTksDO8__;fqcdU2L z<~w)$XxkyzRX({zkB0w#j(PdS?0KztKDl(IK6UsR*(*AwR{=|pyp~U#o;_;$pXUUo zRZgk0mL7Sh`|%V1bI)Dg^w_@Hm3^-ZMwVXJO<&{VDvz%Er_)zBIUQH^Pgi|~v&U$q zM`xw;LOM%K-EwSYQnhjOx#<<_%<;0dPfp9M&(1!kE?fIh`unNL{>bbac18W6>95PP zk0sg1gzRJZoRPy)%U(T7w~^)b2lXz!hIB>gI(MHTn-A=@Pi4QpFJ;e~{qJX|2mVWb zqh|g7B|q8e(kH!wovyCBRCfB$Z1k_MLW6&Q7546(y^>J3 zSMC2icbNW-8df&!)2Mf&s;@zVFY+h1pEv*MgUi}n-|mJ3=We}%(eye^GCQYcwelqm zve$7Nr0e_AdF-EdPy6D}UfUjd`@BD^H=ei0Ivci4=eBgtn^`%l&#de@rgVEu*NHQG z&-%}G;(q_QPCUEnI&s&yPMp#Ai~-pr(eq2!iRmnNNcJpX^5rTqX-rp%Cs$o1jy!Bm zw#zr4Ty>Q=^04!>mGq4oIr6Z%+25zD#AEwZ_Pl!J)vIoBvw#^h4=vJ*>}u z|LayYx^ka?+^Vv(VS|Cq239@FedB*UMo8BI*<;&@L;Iyy`>R#Y?&k)UUf+mUD)t=M ztb5ZY%B`rqFwuEEo-xqR~u|K%FI$B#`qY}#js>=nBmdhgJuP5SCgNZ;>= zzHD9Dx=+?h-~C@M?~uJ-+o}66^V;|LvD2jV)o+>Z@h7y%{w-DvZ_&HOKfbP&4^(?} zMiw=dYM_=rI zeDU&@vo7q?X6Uk&^A|pG+=Cw-y6Ew1FLP?a*uW z4`V*-alwLZZcGBE^f~!|2{@_pg#Sapr2k(5Z$F9L@D9|8`l+`sQZRj(Fj zKi`u5M9cq+fWiM&z#jh+(Eq;(7_hqE;BI~P$OP=syH}rH{}9l#a*sY)`-gzZnSe_( z0S8nG=w2nDdzFB0y}SQMz@KYgeKdRYT;*uj%FcZ{_wG{lzwy_a48_p`ceb;D_` zd))r`fYqD4^xMM+G&$gnYu^~K>gX}34Ut9mxK7TCR_}sNOZ~s>9U9%@)(~Tp0D)x}<2i=N4SI>TV-#>pUF8iah z>NTFuen7FTdc`N%k4l%7<@e2gEU>Js@L?8n*-I4F%KA0V{=1s&x3}acWPg%dnf|E( z8w{^Xg#*&6$RCpZsAgG3;oj^g-w6o8wZR~Z@&OWtvu^XhF zeQxbz*H1h9mIv2?dDG`qLS zKEK^!mt}j$?DN|_cJ;Kg&#!0f3_`8)^5(gv+4sM8`bCN5TU7n7@Ya9{Qh zBq5dg^vhJMg!GL=LrA}vA*6rI5HcWU2pJeNgzOnJgba!qLiUOoLiUasLiUMC$iA@& z862CCA+ZVBFE$}VV-vD}Y(fr*O~|m=gd7-~kb`0qGCVdRBVrRWGBzQjViR(3Y(hrI zCS*)(LJo;d$k^C~92%RD!(tP1c7UTi{U#wKJ|Y(i$oE(sZz+ax<>)Si~z0hNz02{|;~Kg}s5IZ4Qc`SeSetAtz> zhlY@gV}_7RVup};F+<3uF+<2@F+<4ZF+<1|F+<4wm?7lKn1n2dO~_TT3As8pAq!&@ za!qVPu8mE|b+HM#J~kmY#3p1>Y(j2~O~_5L3As5oA-BXPymx{Yrme(As3W{bWZm&_ZE_zB;@_lSVeuz!T z%GiXgicQFmu?hJpHX*BH6Y_IxLVk%&$eP%Mtc^{`udxaFEjA&)$0p>D*o6EUn~=X^ z6Y_WLl8_H`r)A&&+U>LdM5_FwDj~(T=^Rq6dLhwC?<7%PJ)eHHf8BI7ldm2}$2&>X zu;ZO13U<7cM1>viBvI3jcao@O$2&>Xw&R^7igvt{L>)WcNusXpoh0fB-btdq;GHBI z2;NCz9l<+EG!(p(L?gjFNvtb)CyDh0?kYDbg)3tXn~?J0!4=i6pa-qI#i(OFoB}O1&WRk zC^}N0Xq-?|)VF$W-wa6c@obj&3q`XNsqxhd$yZV|v3fqeHBFVGV;mofCfT9rSUVIQ zXNRKW?ND@r9g0r0L(xfgD4J}CqA4~-CkqsvB2Y9{plF&v(WwGO(*=r76DT@eplF6b z(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMK8Ia=a^nm)}P;^gHbbs|i@|6@l zTs@!O8mmgtBaRP6kJ_PVi5-d_vqRD2b|`wn4nSO6Day!py&^QqCW+S{t_tqTc9ZWJ(rhd-}&%YYP{q|?vGp=jH5V#<{jlCPwwP?k?`%~z$U!ttS~rX7lE*`cVm9g2!} zD5_(JqPlh{s%M9y`gSO4U{kb?Kv6@1qDBHm>k1UDCs4G$Kv83Xq74L!HWVn@NT6tA zfuc+Pa=&FjigVMGjx9pbIoZpe<^9SE$yZXeXIVbI zHE7kjXprMW(Oz~a+S?9A``DpqUpo{HwnNbnI~46_hoYf&DB9nq=m3GDVFE=53KShA zP&8biXoNt~NP(hJ0!0T46pa=r8Y572h(OU;fuchNiVhPfI$WUW2!Wy_1&YQA6pa@s znjlbglu%MMpe)xl15$iBor?yBqMOp)+tFo(eEax*d@#Y@wj z*rZUjTYA><;<7^Wl@wi8mQQa@Ty-wG-0`943Of|dw?omDb|_k4hoY2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1v zqPqo(?hz=uSD@%Vfuh9%MfVF7Js?o@piojYuPpas2Bi34^$gCXq3Eh~E_$e}kbEUY zOUm-;t*xsRJ?8jO^tc_0p0GpFlXfV2$__+?XoVe$zOzHo_jV}y!KP@XK+!6Jq8|l{eiA5JEl~8cK+!J( zMQa3#)(RB;Dp2&BK+*34MSlns{V7oNmq5|q0!7(dJ(n)qDXK0|R3=cA6DTSdD9Q^Z zMW2@ChGamB=cIGdXQAl$^ys=qu8@2sMYVGI6SfaUwH+UdigqZfV~3);b||W6hobs+ zC~9DbqIK+0)X)w^jckh66)0LyplE%8qQ(M68weC_C{VPKK+(nmMVkl|Z7NW-nLtq! zfug1YMVkv0H4`XmE>N_EK+%>0MOz6JZ7oo=jX=@1LP=3YE;l~|Qe2rH3f0V&uJqG8 zkC(T|6_T%{X!~6L(H%ljYsZJ89qdrl#tub0+M%ee9g5o7p{TtbiaOY#XeT=qb+jqk zS)gbafuc?VMY{?VbrvY z<3rKDb|@NbhoT{NDB8~sMMLdSw7(sS4zNSfFgp|-Xj62MK+$l4q7ec`BL#{^2^1YH zP&8VgXpBJ7Ap%8X1&R(8C^}4_=x~9eBLs?$6et=eP&8hkXo5h|Q36Fr3lvQhC^|+c zDH@c^ZJPlp?wuYA?G=i)PNXK~3dvVebV4p)**+AV==e}{k{yaB+o5QR9g0r2L(wUA zD4J@AqG@(0I@JzE(`|}Q6DT@eplF6b(HR0oX9^UZB~Wy>K+!n@Mdu0>ohMK`-)-9g42DL(xJz6kTJ7qHFC?be$cFuD3(c4K_uK z1d47HD7s0Y=w^YUTLg-36)3t*py+miqB{hN?i47xOQ7g(fuef^itZICx=)~Ju|U!N z0!0r96g?3lzN~Q1q%m(Q5)luL~5t zAyD+DK+#(QMQ;lfy(3Wcu0YXJfui>WiryC}`aq!QLxG}?1d5gk6fGAh`dFao6M>>n zg_5Gja=AY;AjOsG0rlgd==^jp`YcySzLKJ^a`{bm4Mkr&J`{aphoW!oP_)7hMc>(> z=zBX9{a}Zpm3AmvWrw04ZHj&pC|WI0^s_+GF9Jnt1d7%Q6#Xht^qWA@?*c`C2o(J( zQ1q8T(cc0^)ym_toucXjMP&j-If0^bfug)XQ4N8jfd45!vP*m6Pp{Sl6it5{;sDT}d*0DoTLpu~TvP03jb|_lU4n^zR z6g3to+CZRaLxG}=1d28mDB47zXj6fr%>;^?2oyCHDB4`0sF^@fbAh5Q1d6s4DB4P( zXlsF@Z3K$86)0*UP}EYOsFhGsRJ%NPW(K5qQ#uzF%S%`K>!o|N?aB+uS5nlbJin-0 zDB98Sp{T7LirU$ssJ$JEI@qCTCp#2%v_sL(b|~7#4n>`8igpz!>MT&yMWCpwKv6e= zqV57kJp_t&6DZnUps1%n(H;Uty#$JS3l#McD5?}F>MKyxPoSv3K+yn!qJaWMdkPc{ z5=x3%m*-y2fE4FsvwVk8bZ|N`?Nwe#zLKKB<@q0agrXsi4@LXgp=hWbiuSid(E)ZS z8fJ&01MN_BkR6JK+o5QLP0>h!qEP}x2MZL97AP7cP;`hu(O7|^Lj{Ts6DT@dpy&vJ zq9X;0#t9US7buz_P;`_)(a{1$69tNn5h$7@P;{(7(Q!ga(LUw5M!RK-&MVL0>>G-T zRTpgKh2$$Knp~c5*E1ANaeOE`*$zdg*r8~u9g3#eq3BdQ6iv57(P?%lI^7OMGi-{^ z5GXoRpy(`tqO%2x&Jid&SD@%TfuflLMY9BoW(yR}5hyxeplGf@(FFoU7YYBfuaWliXIdwdPtz?VS%DY1d1LNC|V*= z^q5dmbY*#NK?bBaCY_5GgrdvSqwB}Z3&~ef^mKXtu|A>b8OMjBXYEk*oE?guw?okj zb|`w$4n;57q3C5h6un}HqE~H-UK1#KU7+X*&@U9NaC|8G&JIQ2+o9+OI~1+7L(wWb6#Zz2qMz(gwAv0u zKid@jB2ctOplGc?(XRqUzX=rmE>QG`K+&H9MSlqt{Vh;bEgzTd6jc`}DibKm2^5tJ z6y*hqY6uh+1d1vIifRfJ)ebI6f4uV~3)Kb|`9OhoW`uP_&*Miq^M7QDZw4ZD5C@4Q+}x5-8eOplB0;qD=*g zHWMgnB2d&+plEY}qGkd`%>|0K5GdMGplB=Ey3)TSotSpW7m}}}s9iokch6AN-tnQRgB^-?vO`fv zI~46~hoW8VP}Io|MZ4OesIwi4y4VzT6)5T^P}E(ZsE0t&ZURNS3l#MfDB44ysFy%d zZ-Jsd0!5VqMSTT|`Uw>E7bqGaP&81WXitHnK>|g42^8%uP_&OwQnX_}w>Se*Jf|Xq z(>4^mvl zqJwRUMhg^;5hyxDplGZ>(V+rGhY1uNE>LuYK+%x`MdJjD#tRfp5GXoIpy+6UqKN`U z#|RWn5-2)Wpy)V(qT>aMP7o+MQ79=IlF$8>0V&o^4~6y%MP=zq|D=2&`AUjT$>%rQ zHxx~Ed?=b`hoV#MP&C~RMW@-J=yW?2&9Fn!8FnZ-(+)*v*%X~EP;`z!(YXRe=Lr+MieG?{;d3|d?EQtik{2oZyFkko_BmGdch7wFWRB#B|8+oY=@#(>`?To9g1GFL(%JY zD0;)D=uLs5w*-pb7ASg0py*wJqNM^w?+FyWFHrP>K+%T+MIQ+iEfXkOE>QHbK+z`x zMV|^3eI`)!xj@ku0!3d66n!O7^tDh@^h`eYY6hgZaXJ@08;WKoQs3kY$yZYJeLlbH zfKc><<3rI(I~1+5L(z|RDEi3`MXT*l^s^m`ez8N*8aouNwJG{lpy)S&qTdCI{tzho zQ=sTCfug?!imKI!%XW&Y3lxo<3xT4R0!6I^inbFd+FqcjwLsAh0!3{EigpxAiW=0&9gqPju9qHN zuT!IRrGHks>~CA6kbEUYJJrZf84-#)IzANbY=@#<>`>In4n@1#p{TPRin`dLsH+`{ zy4j(qyG>CKfuh|6igp($>M2mPhd@y;fui05MSTQ{Dg}!A3KaDdDC#dzG(ezepg_@{ z0!4!aiuMvH+FPJ#AAzEM1&Rg>6b%tdirUx6U7Z0bZj$cAI)tJ=>E)39Y7~;Mq-a=; z{1c->(SeQ+MF-iTXt*7UM%bZfq#cSz*`erQI~0w!L(v#J6dhtyG*+PKP=TVu1d0w9 zC^|x*=tzO0aRNo-1&SsJ6dff{bhJRxM1i7X1d1jJ6dfy2beurZ@d8CB2o#+tP;`<& z(PV+5DMCrn{xx!6Wk8Dc(&^`bP_!aFk$rNFLh_XqomwMbb4)0j?)Xr2njMNxw?okk zI~1K^hoUp>P;{0Ziq5t}(K&V~I@hM?Jb|K_0!6a~ie?KG%@HU%U!Z8NK+y#PMHdPb zT_jL+u|Ux!0!8x#iY^r>x=f(xa)F{N1d8Sh6kRD$v_PQfDuJS_g_5GFHFDc!K#DWc zxoBD_x*?s57S<>vUrEvRHSz<-hN2rBABq;)q3A|C6y0QpqMPkdbc-E|ZnZqWcAk9uO#cP@w1`fue^6iXIUtdQ_lj zi9pd~0!5Dt6g?qO^rS%1QvyX#3lu#gloVZCBX>*&q&PM`puR2?eUi>a&(ik1o# zy(dugzCh6j0!1GR6n!L6v`nCAxj@m!0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2R(bob+ z-v|_aD^RpTC@FfrM(%+ONU?LeM|&X@t<7cQyBdY$D=Au4Bme#pq3B1)hoYbCP_)_( zML*l2=odQ_t+7MVT00c|YKNlV>`?T(P0=3$MSltu{UuQJw?I*~LR_{}R9&E`OrR(y zP*g5Zlou$>Up{R*XQB#4U%>{~@2^2LKDB41xXiI^jtptj;7AV?AplDlxq80*0Ed`2N z2^4K7P_(^3QEP#s9R!Nn2o&uoP}EkSsGUGjd!eMLQ6bke15&)aRt9I?Lg`BXxO8Ib zP$(o{NzpEa{2@n$qE3zvMZ4OesIwi4y4azps~w8E*`cVr9g2F`p=dWd6zy(P)Kj2n z4}qdy0!6(Aiuwo?RSFdK6)5T_P}EkPAw4XrHP=TWTg_5FHl@tvx`*k;4n>FBq3AH1qQeD>ju0q1QlMy@K+$-Cq6q>;M+p=i zEl@O3py(KZqDcZp#|ji3Cs1^}K+y>TMJEarog`2+S)gc&K+(wpMW+Z9O%+Ot4lLwe z&wvykNN^4cMKjW)>uH5T@|6^wUdaD6DHP3cd?-4@4n=3$q3A3-6rF8{qI2v}bgmtW z&a*?&Ogj|KvMHJ^P&7xN=zM{qxdKHO2ozl?P;`+%(ZvEqmk1Qi6DYb=py)DzqRRz} zt`I1iFHm%)K+yt$qN@aot`;a-C{T2bK+&~ANzwE|uJN&%qT8}rep)DMn(ooAD-@Ei zr0B*%zT@$s=qAU9qMPkdbc-E|ZnZum+ zK7pde0!8-=6g?nN^q@e|Ljpw)3lu#fQ1qxk(Gr28#{`NV7bto{py)|~qNfCko)##2 zMxf|ffuiRGik=rrif$<64$OcQN2JTLMWN`qbS`?KP)NR#qE`y}Q%(#;uR1;yy=I4^ z*X>aBh8>FDv_sKbb|`w=4n^|vq_)zqV9g5c2p=hlgihi|2(QkGr z`rQsif7qeuPdgO-WmELGKvA`dxS*z}x$tw2!=fufcIMXdyiwi77YUZAM8K+z5YMQsF%b`&UTD^S!< zps2k-Q3rvdodk+H3MEDBSL9k}K#ISmS3nw9l&XLju$98L7?bF zfufTHiY5ybO%W(MS)k|?fugAbMbiX|P8BGcE|e6FsK`B(0V$45KVLL56dj#NomNpu zzLKIdEAk(n9*WL#d?-5G4n^nKq3B#Y6rE>>qM3Fmnq`Ng*>)(JV~3*iZHnd!6kQ-t zbfG}eMFK?^3lv=?6g?wQ^sGS9a{@)r3lzN|Q1qfe(Mv)}(M=V( zUKx;L|7@1u9E#?pN7pY`6q2u`==F;Hp=XDpHyj^|-n2u}TXraV+YUwV*rDiMI}|Oo zL(zM7D0<%xMIYD{eJD`$kwDQhfuiLCMIQ?keIiiwsX)lS1WQeGa%WeeFo>XP&6Pt)c&cW zkbEUYYbx@$og0eQIzANrYKNlV>`?T(9g6<2L(!jhDEi9|MSt6&s9MdqZVyG(ZHmeS zigE%)h1d3V;6txm4 z+D@Qodx4_X0!2Fr6txj3+EJjWtw2#bfui;TMI8i+b`mJ+C{VPsK+!G&MV*9_q77^2 zHk_3ydap(XXQP^>EB(4v7i={P$yZX;t!93gIiaY#<3mvoI~46^hoar>P}I{7MSIwx zsFxjzdfTC>j~$9CZHoE|6!jA*>Mu|~a(H55&(x?rnW zNWPMyF*Wnk=7yp}93P6t+M(!BI}{yehoZynP;`VHijK5H(KtI4jkiP51e>Cx1d5Ip zD4Hlxbc{gJB!Qx11&WRnC^}xC=mdeH69tM+5-6H1P&7rL=wyMSQv`~p3KUHfC^}W3 zXu3erX#z#33lz-|N{SAynY%6nQk;~|MWaK}xb(wDXVfetUrEt9HS^D07>dqyd?-54 z4n;HVP&CU9MYHWtG{+7_=i8xZt{sXlutU*>HboZ+6kRM(bcsOGJb|K11&S^cD7svr z=n8?N`2s~(3KT66D7s3Z=xTwYg#ty_2ozl_P;{L@(e(mFHwY9h5-7S+py(!{r0A@g zxfL0Z;_lfjKRXm%o$k?Yu31RFlA_yd=IdM%itccHD7w=QMR(bu=x#d{-D8KMd+ktk zpB;)8+o9-wI}|-&Q}m!f(L(}74+|7MB2e_GK+zI`qQ?Y^9v3KjLZIkLfug4bik=oI zdPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl7ASf}py*Yhr0CX~xi%S);$I2QZK3GsbdB~} z%|h~(6unh5zt^Rq=xxV`qIc|2^sXI>mfE4{Jv$V=Z-=4}>`?Tf9g04(L(wvuqU8cb z9}5(HB2e_HK+$IcMV|{4eIZcvr9jbF0!3d76n!I5^sPYA3W1{U1d6^FDEdL5Xr(~W zDuJRO1&V$WC|WI0^s`V>^hV9x@fncfvUH91W+-ZxerL!pH4DjCQuJHR{JhIU(eI8A zMSs|#=ubNo{bh%uzwJ;|tyWyQhob6sC@Ql#TY;i> z0!8fwiaH1s?IcjtQJ`pNfudamiaH4t?J7{zS)izkP*Su>tz7w)nW8@F^s{NL(v|+U zX>_esNWPMy-D>5xxGEIw?)XsD(+)*@*rBMG9g2F}p{S1?iYo0;)YlG0{p?WG-==7Q zK+!;fqCEwQ1_>1HB~Y}tK+!$|Mf(aA4HhUGB2cuSK+#ZvqWuMm4iG3BCQx*sK+!=0 zMZ*P(MhFy*6et=cP;{_RQq;Xxu1^M}n0`}Hd5=(ZUmBxp6_T%{=+IjE!xx64!yF%q z4!1+m5q2m#(hf!A>`*k`4n-5}P;`_XijKBJ(L|e~V+4vO2^1YGP;{I?(eVOBCkPas zC{T2gK+$A@qA3DJCkqsvB2Y9{plF&v(WwGO(*=r76DT@eplF6b(HR0oX9^UZC6p8$ zQY$w*15#|7PCsKq(IM#`?d)2G#davV#HMJTK+&ZFMVAQ_T`o{`g+S4Kfubt~iWUeIT_sR-wLsBAfud^! zimnwXx=x_zdV!)F1d0|36x}FLbdx~Q%>qTY2o&8aloXv?EBAH=q?^m-b% z)hZ-kNzq-k@@uXSMRz+s6y0NoqI>O7be|oH7TcldemfLBV27dy?NIcP9f}^dDSAYp z=uv^9B?3i{2^2jpQ1paA(USs2PYDz~El~7~K+&@TMb8NoJugu7f$AaiFZYLUG-TmELPLh_Xqy<024>y4pk zspCV@dv+*#-ws6|*rDh{I~09nhoWV6C|YiZqL1xR^odQ;rvgQv2^4)UQ1pdB(U$^6 zUkMa_El~80K+(4XMJoh~z7r_=UZCg)fufZHMXLmgeiSJBNuX%8K+(?vMZX9Xtq~|% zE0h$yT`M;-15&&x-HE*uik_&*#;>&s$yZYJXRZA7n?uoGjt@nD+o7mh?YMFeMb+(4 zRAz^woE?hF?NF4rLs1Po6cucWDg=sZ3KZ26D5@<`R1_$xBT!UVps1ceQGJ1;1_DLv z2oyCGC~727w5~wWdICl33ludLDB3`vXhVUbjRcA|7AV?8C@K2AR_=xjNOAvkF8U)B zU6cJ;`KGlC$yZXedF}jjw}zr-jt@o6?NGFZ9g4QJL(x`tDB9W%Mcde+Xj?lJwXj1` zOPiur0!7;i6m2h1)LNiu2Z5qC0!2Ft6txv7Y9~n2vq6u~= zI?4`3N86!jq8*Bku|v@$I}{yjQ*@j_(eVOBCkPasC{T2gK+$A@qA3DJCkqsvB2Y9{ zplF&v(WwGO(*=r76DT@eplF6b(HR0oX9^UZB~Wy>K+!n@Mdu17MTgbSotObBK9OF= zKRguukxoqK)h;AoNzt6z`OEGJMdv#{6wS3m(FJxWy3h_q7ulicVmlOFVuzx6b||{k z4n>#Q6kRS*bcI0Ce1W1X1&S636kR1ybhSXyLV==d1d6T|D7sFd=z4*o8w83L2^8HZ zP;`?((ai!yw+Iy7Do}KrK+)|2MRy1#MYC$>mSjMRP1Ct(b|_k$9$nvAyO4Y(MfcXu zf1EuNS@qw>-skvGwAc`?Tu9f}^YL(!vlC|Y7u^q4@=;{rub z2oyajQ1p~Q(bED&&j=JfD^T>DK+*F8MK1^xy(m!hl0ebR0!6O~6ul}?^qN4?>jFh@ z2o$|3Q1q5S(c3~v(cQIkH5O-zPEBy`2}SLzF4$@plCPxb{o47h9tcGrI6f48XosSY z>`=7K4n@oDQ1r1KiaxPJ(WiDO`pgbRpW76DAyD+CK+#tMMPCaPeIroxtw7NVfuipO zioO>p`az&*r9jatfubJ;ihdF(S}joYvp~@=0!3>Ciq;Ag{VGuOn?TX;LP^om+PS_N zkm7*!6w!O3=$1t4kJ^RgD=Dg0%pdtsD5_qJEBR1VW{0Aj9g52BP?WbrQ4Kp373@${ zVTYocb||W4Q&d}^s3=fWN1&*#Kv6w`qWS_w4FrnT5h!XXP}E4EXkCG#^#qF67bt2h zP_%(S(S`y=8wnI`EKszGK+&cGMVko}H4#dR{;HijKLb)cIsL@!-=U~Y_Gjfyi-qJX zDcYi#zw41uw58)i(N=aS+S(39+t{IKTRRlButQNxI~29DL(z72DB9kpsI@@R4gy7O z1d4VPC~7NE)J~wNy+Bb1fufxRiaH7u?JQ8Vi$GB)fudaniaHAvbrC4)Dp1r-ps2e* zQ4fKl-2{qu7fOnn6?5-qK#D!nxu|)ubfte;8a<1J`=6~P0>CAMf(aA4HhUGB2cuSK+#ZvqWuMm4iG3B zCQx*sK+!=0MZ*P(MhFy*6et=cP;{_B(P)99F#<)02o#MKC^}T2=rEzAs8=z!>0_Cq zhSf7Ty+cv@j~UAkFBX!oq-cCG-{px=G{Nzq=qNiB9c_oAiFPPD#tuc3>`-*99g2># zL(%beC_2HW=tO~{lLU$;3lvQeC^}i7=oEpXsRBjQ1d2`-D4H%%becfX=>kPF1d7fO zC^}Q1=q!PvvjvLI5hyxWpy)h-qL~6kvxJhOBa69%Ga$vc)5ZO`Q1n$Avx|k~D=E65 zm_PlgP;{Z=L(xTcD7x4VMVHv2Xr3L4F116^Wp*gK+zv%o*r8~?P0^JCMGFLqt`aD^ zTA*m5K+!bB5`?Tm9g3FNq3AI?6g_T-q9<&Mo)jp0N}%Xzfud&wik=lHdQPC|d4ZxA1d3i1 zD0)et=w*STR|JY)6)1X5py+jhqBjJJ-V`W$OQ7g&fueT=iry6{S}K$j-B--5%zzXh zPp6;7p=i_W&&uB`7Lu=|=%Zr3!SkVLnd3vzayt}#Y=@#x>`?Tn9g04)L(%7UDEh(< zMPJ&X=qsC|uLX*}5h(grplF3a(RTtx-wPD|AW*bYplFpq(T@T}KM54A7AX2zpy(HY zqBR0VYXypa6)5^mpy+pjqCW(R{uC(sODHM&pqOi)0Vy7se(w6iP;_-V7yVrx6P*hK#sJ=i^ z1A(G-1d1986g3hkT34WGJ%OV21&SIA6m1|-w4p%JMgm0}3lwc4P_(H)(PjcgO$3UX z3KVTFP}EE)DXLy4H#q}RY@A+zEvr+yMr)Y;S$Xq1h2$$K+PY5uikCytHja;T(YAId zYGH?>mUbv=Wrw2e>`=759g14pp=bv?6t%G_+EJjWtw2#bfui;TMI8i+b`mJ+C{VPs zK+!G&MV$nSb`>b*OBK zfE2e$aJC9XSEReQ-gOGeS5nlkPX5zZLs5UnhoS*?C>m&oqCM?UG{_D`d)c9AZ#xw2 zV~3)B?NBt>rf7&j(S8C&Lj{WV7brSFplFyt(SZU*2MH7n7bqGbP&87YXp}(F!2(62 z1&YQ96dfW^G*+PKP=TVu1d0w9C^|x*=t!ZYsIpG3;#Sq38-b6wS9o(Uo>6T40Bwt89v{7ARUMP;`wz(X|3a*9jC|FHm%YK+z(B zq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pKQhdj*Q_6H1CMtdqMS z15zB6e%A4#P_$h-F)glBNWPMyhw9|-c_$P-?D$ahh#iU^wL{SoI}|-;hoZ;rQ1pZy zik`GX(NlIPdfKMw8G)i_1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+X< zfuc7Birx|^dRw6A9f6{E1&Wpm6ul=<^u9pR2SQ2F19fumWk8Bk(#!Y{hN2_VD(Z_Z2zb_3%pEy1geQJlI&+Jh2xgCnWutU+8b}0JF4n<$vq39bs6n$$`v_hch zJAtC_1&V$UC|W5{v`V1pM}eZB1d3J*6#Xnv^ou~z8iAs<0!6x z3Kab%Q1rJzQMI~pVNOwXp`>V8om`XmGDRP!S3s7BqEpj7T3Ovf@|6_TsGINhK`1IX zJ``2hp{S-EifY-RsJ0!7igqZfV~3);b||W6hobs6MGXXs))6RbC{WZ$plDrzqV)ud z))y#hEKsz8K+%Q*MH>keZ7fi zgB^<6*r8}gI~29GLs2`MqV@ts9R!MY5-92@P_(l^(Jlf-odk+@6)5T~P}D`BsH;Fx zH-Vz=0!2Lpigpty+FhWir$Esj0!6(9ih2ta^${ql6iSM=shhhw15#|9UIE!Q6djjH z^{rb-zLKJWb@MMR4@G-AJ`@eIL(yJ#DB9Z&Mf=#HXkR-N4Yotk5IYp@XNRJpHbwgj z6dfQ?G)$oAK!Kuz1d4_W6paul8YxgTN}%Xqfuhj@MPmet4iP9CD^PT(K+$0WMTZL% z9U)M3q(IR)fuivOMH7UQqW*PrKW0FRXVuE!3&rV12I6DT@WplG^4(P;ujrwbI# z5GXoBpy*72qO$~w&K4*-N1*6jfui#Sie?HF%@Qb@El@N^py+&oqPYS^7YGzxD3laU ztee{@15*4Xy#jJfC>oI-U0+nUkbEUYm)6bi_jxF~%<-Y zP;`|YimtXp(Ly^EU1L*ptw7Or0!7yg6x|?Dv`C=nMuDQ61d47JD7rEeD~C~B6* zgLMnZS5ow7-TakbhN2~o4@HmJq3Cft6g^>wq9^T8^pqWnp0-2LGj=F?)(%C_*%Uo5 zQ1pU8(Tf5_F9{UAEKu}{K+&rLMXw1Iy)IDnhCtDq0!42L6um7_^o~H$y8=Z^1&ZDi zD0*L@=mUYG4+V-o5-3_GloUN&H}_-)qc0YG_l`NT6t4fui*Uiq;n>YAjH+fk4rQ0!14M6m2X}w245`rUFHq z2^2LEC~7KDw7Ec0Gl8P!0!3R06m2O`w3R^7)&fP_2qi^@dbxoakYaidhw_Sgr7Qid z6RB``V#supNqq*r8}YI}{DIL(%?rC_2CnMZ;{04iqRlNT6uAK+y<+qLBhcqXdc$ z7AP7mP&7uM=n#RTu>wVh3KShCP;|IJ(GdbgM+y{;6DS%lP&7fH=qQ1rqXmj43MEB* z*2{g60V&Q+&s`4+MT^plYRA+oBwtC<@%8e5{uqi*aC|5_(GEo?*`a8%9g3#dq3C2g z6rEy+qN#Q$nr4ThQ*DZ-3lyCuP;|OL(F}p2GX#px6ev1Npy+IYqH_d_&J`#+PoQX~ zK+!CLqS*pPa|DXc7bu!5P;`Mn(S-s<7YP(yEKqcbP*QYkz1-$MWs0^)ucI9oiuOvE z{qyP-lCPxbihB7TKZm0Ejt@mw+M#HH9g429L($cCC|YQTqHF9>bgdnVuCqhY^)^K} z2ox<6D7sOg=q7=pn+1w)5h%Jum+K7pde z0!8-=6g?nN^q@e|Ljpw)3nfLD)ys{|fE1UeCmJsgMen4iARnn$NWPMy$Lr_fudgpihdI)`dy&t z4}qdT1&aO>DEeEVs9OEFY^SKYKv9`MQBI(!T%af~P*g*ps34RSeO@oOIs;N%mG05L z2t_ZZb5TY8Lh_Xq73=5M{Ua3BaeOGMYlotGb||WEhoS~{C|bu3MGfsx)W{A+>)N4c zJ)5HS1&SIA6m1|-w4p%JMgm0}3lwc4P_(H)(PjcgO$3UX3KVTFP}EGIsJTGV76L_E z3KVT6P_(r`(KZ4_+X@u55GZOXloZvfpW8VDQf!yt)UIE;(*Gts)NWP3kbEUYJJiqb z|5qq#dtqaBLc+M%eO9g5o9p{Ro$igvO?QAaxz?QDmlU2KXv2^8%rP}EtVsEa^R zSAn8#0!7^gih2kX?IuvPyFgJ-fucPGih2nY^%f}VBT!T+P}EnTsGmSle}SR_0!0G_ ziuM#ringzxo0`m~4G(w+b33KU%?loXv%KUd6UiXKi+G@clWc1`D^%j*}CucT-} z{d}u@D7wn=q3CKm6fLwv(KU7`y4DUw*V&=ydOH-|V27ebb||{hrsyVtqMHSZZV@QD zRiNlLfuh?5itZ37x>KO&E`g%E1&ZzwD7sgm=stm>#R5h53lu#dQ1qZc(L(}74+|7M zB2e_GK+zJRq-cKq+@K6daX~u$Tp5aT>9YT^`i0~xDSE1YeqtdMJ?;2V^o$*fp0z{K zb9N|t-VQ}C*rDh}I~2WShoYD5Q1psT(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH17 z0!2#&iry0_dS9UE1A(Fs1&TfrC|V{^v|OO*V}YVi1d2WtDEdsG=yRc@=!yEdOEMtE zGt#-}$x!ridUX9o{X+7U6n#@ae}BzT^sVDV(F!{heP@TF@9j|ZgB^-i+M#Hb9g2Rm zL(xxmC|Ye(^s_+GF9Jnt1d7%Q6#Xht^qWA@?*c`C2o(J(Q1q8T(cc0^)f&WQJ4Mw6 zipm6vasox=0!4X&q8b841%aXpfufoMMYV*IqOa=bKFWX;r)0DI>rk|~>VmC7A^A#* z>NUv!T{{%jcYG*nV27f0>`>Iu4n>XZP_(Wciq^A3(fW2MYHWw14Qz@w6e!wAplD-( zqD=&fHWet^OrWTVKv7eHqRj=0nh6v&7bx07plC~hqOAmqwiYPbMxbb0fua@yMJ)x2 zS_u?wCs4G#P*PN(z&R0gF^C^6t!)T-@R@qYUlV+)ZPw7 z9qdrFlO2jW+M#G?I~46=hoVk)DB9HyMV)Pmx(F0?6)5T^P}E(ZsE0t&ZURNS3l#Mf zDB44ysFy%dZ-Jsd0!5VqMSTT|`Uw>E7bqGaP&81WXitHnK>|g42^8%uloYjTkUJ~` zQXHBd3hfw*o==zk`!pydUrEt^4f5yI4@E;AABy(3L(u_tC>mymq66(vbdVj2hTEZN zgdK`T+M#HaP0_&uMWY3Z#t0N0B2Y9|py*J6qQeA=4i_joLZIkKfueB&MdJmECI}QA zB~Wy`-*N9g1eyq38@d6rE{Pbe2HT*#br9 z2o#+wP;{O^(M*A&Spr3~1&Zbf6rC?nG*_VL0)e6n1&S^bD7sjn=n{dVc>+b33KU%? zP;|LK(G>zk^M#V4$qjP9WI&20jBPkbEUY3mfFuUpEw8c?tsRQ4 zvqRDKb||{R4n>RXP;{dmif*z)(am-!y2YmGR)M111d47KD7r(S=uUy6y9A2v7AU$$ zpy*zKqW_P*H-Xb?e*gc^J@=gZu4zj5JuTBd(?aVkZAzs*)kv#kZJid{)IE){;;Xp-8f23t6%x%3Ane*Lh#hd!|10i4VW;_xJmM=JBZOem&25pYuNFJkL7! z-1iCq7Oeze(PIECS_QzO#{pQh8h}Ml0I=vu02Vz3z@jw(ELsb|qNf2^v<~1bx-}MV zDT1Wlpidnan?=X!vFMptRQ*zmHpKkX%bP{d)7~t4fovANNH&W$lFgz`WV7fcvRU*p z*(};jHj7>%n?+m5SoA6Yi?#x==rsTqy$-;lHvm}lCIE}x0$|ZL02aLsz@m2mSoAIc zi{1lZ(fa@_+77^?4**#7Apna$0$|Y&02X}=z@kq8SoA3Xi#`K5i=K^zr-&e_{q!BP z&zVKVM4sfGv8ei`7JU`-Z>wMy?V`O|^flQm+D$f#z9E}M-;&LuJ!G?JFWD^mj%*fv zPd1BwAY;*w04(|mfJHw8uxK9ui}nMs=obJM{R+UM-vC(T#qG8oi$VY_N&;X}7=T5| z04(wWSQG(ZQ51kh#Q<1T9DqeB04yp2z@k(D7L^1zi@u13H;5pq=jpNNOS9-HJ-wBR zN7XO2C?5BBRx*pyXm1vkA)7^I$!1YGvRPD~Y!;=H&7ulqv#283EUH8{iz<_`s0sj! zssga68UTwj09cd>z@q8^EUE#(qM86Kss+HJBLP@+6ab5A1F)zL0E_AZu&5pYi|PZg zr~v?rvH)0=4Zxxt02bu}u&5!xSyVb6E>&49+NUS6Slr#|FV|yHqj*&PQj3m```J~^ zqGq%=i<*w= zn?(c2X3;>hSu}`j77ZqwMMKDDQ9ju$8cN2ZVE`-|4#1)j04zEafJJ8kuxKOzi$(#k zXfyze#sIKrEC7qn24K-R02Yl0U{L`8izWcD=o|nRoeRLCi2y7*4}eAI1F+}<02WOG zIEzk+hZl$-seANJ|5UT+M?Jk=7>}x7YSATe|MBW((G=R7MN`RU(KNDIbSc>^x{PcV zT~0QOrjyO08Dz8Q3bI*rB^irm0R02W;hz@lpaSTqZOMY91|bS(gj<^Zs0E&z+J z17OiS02a*$VA1seEV==JMGF8}bRz(Z76P#7CIA-Q48WpW09dpLfJL_goJAMM!`nrW z)V&guC!0mTXjmMNs$X7dFDbc3@p?ywyx0o)m8}!lc z?CAcUcYEx@fu6TCwr;TJ-5V=D)bp0dx)1lfhhx{B>3J(-Z;$l6)v?Smp0_48>}=0_ zCU)O=&)X2&Gr{vV#+py`yv?zT&-c8ovGtQY@6A|=i#_k1SkFs5Z+mS1RL|QHd-qb$ z`z%&ty61fv8*zo_?T+0))ARPmzPsAKuye_X-^!ivP4m zwn-?i-|W#R6xXk2=ogCXXX~F9itC4?4+zEe)2)Yu;`;H#!$WcXeA$tqxPCzB*ic+Q z;jthT*N^C%7>es>tW65V^+U2IhvNDvN7F*_P1|J)h2r`-BQryB{h)|hp}78~|J+bq z|5W?>P+b4kc3~*4e=NBu6xY9YyFC=wKUZ2BitFE-+#8DP9}FxH#q}NE4~OFVmfe-1 zxW4CdbttZHnp+c!>${$w3B~noD;q*_ec!>xP+Wg;yg3xt-~4S2#r0P=Z-(Of?ERfk zTpylp55@KA*N#wJA76YHitGL7m!Y`cKJ8<=lP9ei)5RY6>+>!BiW^7d&y1^T6lw89F%)iMh`V9b&cY3VxbpmYT+y$aKjkYcYZlwbr*W+ zE2YggY15ktJtGr}$bnWTG@S|U|NMjJT$et7W8<|!mtyO0*m-);r78E_vSgx{K2kQ7 zHhPRkuP(b}tE@X&pL4c6c-KUkebNNkIx_2CyKn68rGF?5bOU@vgU_y+|BmbKuHA2! z4Z3^Jl2=x^^}npcl@VE);+nR}tYaH`SdDdqgLz#3*o_-?oB64or=L?H=-5kB*WY=b zmp;?l^r21O!*gT=St~8_ju;Wl=CU2@pOg+t*Pi*ZL~}2_jqjFa22Fm>>l6)Uv*?UQa^2sP)4t+Qo5DPp^>fK{$hB=*LPtFF@(;HP$_Fc|-ZukNoOjDO97ySBQSY}|Rt2H9Q(vgc`=8g+ve5Q*Kf z@QSr7sEX{7`-VibRoCVwGGm> z9X6Sg^-cEco@!Gun9R8kmre^N)3o0-(O)*e!%zMEnj9CtlqR}})m@WtN-^I{ACTg@ zd$hqeU2DqjYOt$=A=%^;4V_+yrWqPrh-Mj@T8I`JnpcRH8oH|xJ#1)oA^Kd9uBhD( zMPk>lcM)#O`_R_33)ph{P5=eZv~p>ho(C zTrS(>G-;(Zneb0nWSp7^mSfV!;jp!dt=iYVmE_I#T@WuKWvPg5K zjc(`?S;1Ner)-r8EwTw6>!8f^vWIF06RQ37i*lM0@B06`yi%}go_uA^Zbm@i6d*qg4oq{$)Pdn*kFMYSodNlJHwEZmE`acQ|R!s5{Zkl&9 z{KDaH%8^veo!xZL$-xvq8}*?a^<`<^xoqc;a)vA;O?2Zw<(h<3ddN1*u<7ifZ_^fk z^rUoN`Zia#bCYc{c76=w|+l)e)dDM^{Mj$N6CEhL@b1*RK6&rYz^9(n_7VlkVwqZn0TC$*kOE&^BiEiOp&s!_ObOTKtjK z@a&YOPs*B=)$sLQBQt{)dgJZOK9EDf_co)_xwankDyXSkUFtF&<)EMHcH3hG2g`JV zywKitq>=7|1p?KO3mlZ=!Z(lE5#ozqcYUHpM`9mudGTv^GJbK__G@JI&9zp`Y*w*r zSM1VN9*MoX?U%()>AuIN9vf`B3m1MJkyD{G(cY!kPIDgbV2<+_&G}H8^h`QeE|PjB zofljx#b&PkNX~&RZRGTZCjIyd6NUscTD9n@4+DQ=t8chOPAy{F?mbhs$jTWYZFG@N zaBU*7YwvsZCnwgg*L<*8UdbZeuwv(OnW?n;@#hz|${sgeT513CnUgbOmSAUuywJ5b z)eUzJZ?IWCLZb)HSkq9t=cis!uvgWS)7&eI^Mln;>8;+Qz4RyL)?D}EPZKS=#Pp== zr(Uuw?Wmx|lu3h&1uZ_E_D-gker8#>IF%a(s~{44;n}TQT$Ah-{VE4b^W9rlJ>*Q> z^5MsOWoa&xM!GbOTq8gA^L?XbC%#&6urv#7qGvOFX8MtJg7y0Ni?gqBdcX0`%x~OQ zzwN!9i)E|dEsbz z&Xdwa_u`kB&havx7i>DA#@D|PkpIifm~CF96Oe7eMMKN z+&*+%)7Pt5I$fR!NSpNO@dU$&~D6cJo%+INOdF9CUM# zywGkwMK@KP^KC|ZXmnTeBW0yaFBd)Vqh1KhjDBo?M3Z1f*FLiBO1a8gW;2R34VE{Q zE8ZBY=ulGe-{c0%SOXhP&YnLC(k(a0p-AkpFJ4{XX7}@gpJ(dXCK9`E$HRK1FWdc+ zUagY6^eGkHx|mO+Zl}2T*Kf0>ip<1ICTq8gB%BNTM z4*c3P{>_fTd>(%MzLhdZX)<-|V}s<5ys}$=A6OH+tR5gZSbt;Xg|5Hf-0*OUUW-f; zs7uuF=wMy=sq@3_^}OMymb`JDT>QxDJK^o7ql48q`?q)XJiNu`)6q52)wj#g$qogp zFCvc#b#soi(PZ^i7Nj#<#LNbCe7I~r$aK!TJ7b|K_*kT-;%swGK=?4 z`_@h7_HS3eDU)eg)y?}d=KbE1#UHpG=fRg=Un?74*6Gd94oM2;ed+$Uo|iknUe(;n zx``RN>&R0C2ixvUd7<0xaW~v;yS^E2b$(5wUlxD&Kk)sx>Te|W;j)F-oaa@1Q`!Va$Ud2F zhG)3Oa!y?S-LG!Zu6ttfEVlta`*7ctx?4=L47ISE^|K?X#NPlGiyl>{)Z_0Qw z!$lu#3s#|@+V;bhUA^?HtJEKnNVaEFLAvx+jxjGT-#qtm?T(-N)u*+NmMQa$W&4xWdV1;i%J?d5 zFUDW@^;h3Xr)B)>S~ol;=*jyZ>|5wo*UGgI{UidcvPPG>Mt*9>=1)rnZT!ipRi%wQ z0(dg@`=a!Q*Yy7$tfn4dafd4IVT+FHXc z-HWb?E^w+mhSzoQo*`M_W`cBqOSiBE{(AErPf2fO{eSl8W9q-G%O~cnzeZ23!BdrG z(n1%x6D@9@cbPs7krr3Zzw<3=D=mJRw{DN_q+-CV9ZO^ZR$HqJXf@-vg{r!&sK%Kc z-0^Dv{JFQQ7;-9kY{e&X2LH?&-A|)MD>p53jW+%K#A(4&Kiz$Am7vYE4`xo0OOn0P zCM5Tf&$u?>lv#4#@@lz0|HOo@yXsecb|HOUF>T{Z?p(F{hm^ha(`ktr%{G@QC z^2zc-|M_7FW#!4A{_|^vQz}P=>ObF;A-zMMr~mx&5(df({pY7k=qNArpI=Ub+zxvB z&o3ikjJ(i)euZ$v3&ldUN~M(um#S3i#PYFFX}Qcvs_B&|ajYQE3zzf4rH(1lqD1o& zUF4cI*@nnN6TgY4BoYdBNejt~Xr|LHc1<+v^4Sy`w=TC{nI(egBP;?(rnpm zCS@8I=|bxYE#<^tHY?P+0{uFwLM#-Iv`L@eu7Y-=T+z`h%XG^Z1xe*sw39WNK4VHq zR&Z{xhALb!CFCWg&u%9dUlnD5rvp5%661&gS)R^#bg5vT(l2>RUo3Rck1)?WLu5$u za&FP8k9d>3+*`Enm*rBfRiAt+*IHW+H_El@(Mq}2y0UXA*Q$H8a;^GH4dubif zas9^+&hI~V+?ay=!3Ft4vImblZ*0LB1%va4Oc<9xzQ`~gU&d~pJ$BrPQ6maQoRjZm z4<9osKYQTF{E69FBgYILI5Kh&dyI{V@BsU$R9XpM1$O%tVRuVaFz@{ zU{Lmm(St`$7?PhoYT)4EBS!y^cVql{wJ86@38~Noz-c==>C0VS%&o(IbnSNUTvFpYw~w&rgH`s&F`Qx*Ot6{RahKv|pAVK!0-t9Z~mu?PjKW5aZ zF{6cvdoknhEz3loDvLogEc;(NEts~H6UqzTsxo1BDV6=Y*DL9EtcUI zkF@j4MbaAhHEa0gsz}U~7?Ns>afDlpnzk50)K(33v~0g-^*`UrubJbQt9qET_%kE_ z#ia-q;(t+pGXL?lDl4kEY&c!!%t)GFu7$kF_Whh;fgSN|{{X>rblWF{&MYdl%Gl5^ zE5f9;RNu0P+1^pzkE@%yvjqD__OQGIy+_DH>@7M)-CNRfD>tgIdt-K_ydSR=y!d0~ z6LYi|zhiuOx7SkiEt6ffTCm_wc#%0$_Rrfa%|z$_BYV#OM!%D~|Alq-Pa9rQ4vFRJ z`W0*XCFO8dNi|RNONIQBWyJQ1UHp=IK&+&%tI6wD@=}J$9&n`8(iwg%63)u<^#B=* z9P8vSujL58zR4d%9kHQ}X8Xv$8|^TrCL1{>U2$`_z2lIR&8#L3GXF$_!&@rtM|Hny zRh_u3sj4lsTj6^zF19L|Rs9?{>~MPM*S85B-pGePW$9!68h+I(e{uz61|9mdt^7Z= z$T8U>y2>(J`K7`=FB~{x9$Y!b9^yz^ zc-@hmnC5v3X?yTA$qYZdX$KcIdL=?LCUc199OTR7RL*Yr-=q9rzZU!d+f~eekMaNJ zlysQqnxtdP{LWGS-v1utgNxono_YO0I>`T{*U`Zxc7x!=aM(AH+;%38{(svUB`3Rj zcBLAAhTM{dCl)`AI)>2KU(zyB1Wez0Eku8PGzxE{t9O0&(QYmv3UWDcWwC^x%`T>+-dY)^SMbD$6Ip-Ix9G6!6?{r;`+$=p55ZL!>Zx@SlK;cGuG53Mpp zvp>0lTgvtbZlN>fZd|S;14|EhI@CZnJnQ%O?v+dGt#atkJcf~r-E6;Hm&7v#c?8fZ zcnD?JzW-K;G`Zi1SF5i3m2C$eTDhkQf7AXI97u!1mphJTMA8wE6>@Mz$bY*C($Q?0 z^#8_#maap6`lt^G4`(_4-yZpIIE0JVx|jdUBQN1)s^-=Y4gm6G>Cii0nyBV>5?oI_ zpbbA4Jg)ka`{3XIkTrM)oZ$zLfU{)pt{EH{*w^JC;+~_m^2>{1`arR|)YJ@lvJ$S= z(ytf^<@l8{{fbrnIyL=@m4XK@0;LMH>K?=-^|#|}n!CiUqeaFDVwN;$=vR?gG0(50 z&u_954|RM$S9fZC;&?bW*m^|$M|J~wE}{4BfA;e1zx_G%Z%zK8_4EJ6=_c1t)6163 zn!#z)U5j(NI=FIL%S`+>=x;o+y5AxELs!LmOx4Hsg_oIfoyWnI#XQ7WjSC_<7U?17m|N@fqwU%;xDe--C-L zhMRzF`N?gVT`#-Np&z}nAN_7UDjeLa9z3j-ouCfpMRVB(!EbL9WBwV#arB?M$orqT zU~<3aF8p1#J7UX0;P-A=TC^N?;8RpCOl-&gII*Wl8nqF%v-{IXeo#p-^^ zaP5|naKGRhMy@yP_QNhtY8SmY(Tkmib~SUDquFD+LrqOCC-k>d?jp&S;!xv<Ud|<1bt;AI@Fu@10dDX3OOA%ob~Ra@I5yP>6~nd5#5pLpL;l{_c{O3l~Ce5kz-FOiar8lG1%D-c}?_t zYxsZk`YOFz-3B?~)U3?h@VKmM4a4W@+f;Os!YQHfIfP(4{?X<;3|{8IbM!&m|Bw?n z_~!7y2U@}Ul#|baZyEb*SAU1xaC*7(pPbI)t?jwD>GFF|Ktk1nleesnGC7&q*_G@0 z8R63U-n+5Eu6D@PROBLGpIIJo6_A~Dh8}G7-Fycf{SVv_hh?z4?kks_n=MCx+}zCY z`C0bXx<5E9L@LM<{O;u)d(I!$R`MRH|74}x8?9u~|LCDp;VLgDYrIlsJwG#CN>}-~ z|8SKT>AF4EcI)~;eSiO{xL>5-hkJ%SV1vu~{!o{F$I4SDc_*73%WBElwQ_JyK#1eWw%JY&-c&#_D65N^#Zr( zlF*04nV0N+(zU8Jbbl)6Rxiz|*@-92zqfk+V9ze!Qdg}mwH&+j-LLf}GetSLxVL6y zXJ*%{sVdU-7HSKhS$&%IGher2nF58zI|2Oj1QXC?dt z9s50X(i+LrJ-N;cm&lNVyB_0oONC2@vcuyue(y-1XGdXh}9{JHGVlANeba|7zv-CG7dTwUT#0>2c(* z?6%<>E=X#0@PUth{@Z>251zNSlLxNVGvtA*JG&nC16P~hA)k!OIrY#FI)lfz|F=GH z&HpP8T*HrCFeNy`{i(g3U;Af=U!K%en*YU<(O)?6>0Mp9?7w)sb*$Xi%hhRlJ$&LR zRrf2s+WxoR%4os-5Ajz&e{c~hx0kY(4{>|>JJ;Wb^+xC5GE{y=;2!*Q(V6&r7WtD3 zS+xKDHOqm2&C+I={B1^_Z1Qk3QA!lf$*!kf@MmE9ca*^?O&{}@3oZ@9Z%s-%*^T^{ zF24Tj`@h}0{_Fd{dDA&(utSX|hvR?!>#e`y`^_m`^TIO=rpP&YS9Hq%o4313UFE|G zdUZUmf2W+zp4QxEIi33taxa@UPP}Z=KJl_?GaIvUGgw<1=QMW1I<~iQa%JQZ$B!8^ zHrMOcwqO7DC-iCP_3E#G*=~Oe@8;Bj2{cK}{b*35!d^5?^rC%{8CZ84(x7Q#tmZ)v zCyX9HV%X^XAsO#w}mt!rqE`ZuG?Bp?FT=(lt*kNv`ZmUS7wO`?u}TD`+Q1*+R;$WUo3L(9+W` zWd#5Ii{QD19cgC{qq;Z}%mBBY48akA&E@tQMID3boT>Y7&?v_yCOeSzsa>LXdf*5~ zYFpUN4k*{ih9w-N8@bIAlgcgB9CHvSx6pf89-B3~B*c(oRM3IkLeFwVG{0N#A;(R<+ig`!$xYJ7)4gUt>eN&DO<2fVSk(* z!D=WJBDaVUMNDWa9Vrx+1F@_v*FPPs6Ow9k&J~9P#8#D~oDFJ}ScS487`@O7HaS~7 zv6Y+2`WusQS@f~CoV4^1V@TRCVG-1=LYZywLe>Ps3MUbCNl$BiYF32#9Xv z;9MxD2i>_6tz`??6bpO6HkLKS+@zoOGO<}@Yq*&eY9hxO87r8N8`ReNE!*3g3$a&; zg%cOu*mA_xL*F>JrgB|z9nLK@B)3qJgq4M6$mM`cfBf(<;|dbzTsEg#7l@E>AaSiA z`%=&c-A=vbLwLHm9?5!gFN(-fC_`?c4Y`Fnu&uPqL1Vdy2rAnmSIl-(EwZT#x2$x* z)=;io1i2Aq&$Snc6`3oJ*?2{c<+;{Ews+xbmRHA}aAHRL=FKzola;b^GxW2Sa+)=4 zoKbsR{>c1+WxeH3Y%r=(BLM}&CyW{-b?C@30}C3+2Q#&jjWa}n zj5&1dIZYajAKPF^Zc`xx#|<9dN0da5^M{MdR!$7VDbmeHVl!;A*< z;X%P4MygV9#$~CRgNHcjnqK5y(B%A7mOG)y1{t)kR++{czEcL zfdvB-*{upWd$<>cGUpcBtakp<3CdYo6z<%4~{}| z7`JW}ZXxG-;tUz6-M{~Vr*E!(3om`qMz6rScj}!uE$4EjTX>yXczIfQbt+fA=;QVU z+uvR9xUwz0=qz&0$%U<4&Dtc`EpoZQMcu;VL9SlW+C^@#gu&`?lW@CXVg<0;`+15K2^A96kg!5*$Xf45}VUqBYMZR zZ+}ciZQYC7jvJNHanzvvAw%S~LLBe!-Ic{qGa!z---?o>j#7t z`3c*{&w;}F`CvtU!t&W*u_9SNs7^kp+neP+wN75S;k6UZ-0&SmvbIl8e7>C1@5smfxgR(E>Dnmxal`w`XCIP-{>eukl6BN%`C2iu4&PiP>+m)5*@5oIOi!Xz z@kLs5^}EVkepqWm&r6bhUZ*o$_HC{2X_e_s62-Jmx7t!Znp1~IL^ZA7Yn9<+Wgia4 zw>n*`48L8g^y6Nw(vOwKH)xf9Y_D$^aHRr)c~_#~~;kLi|Y zX_bB~w0yptEVSJettyUS{Fz$vQqg94? z)hc|fRvB-W)qAzdbZVwam3}v~dYV=lZ<IhpQ2UTU7=Ol%`?74t1S0}mRD(Q=y}gt{#?HPK-=xrD(#Zwz@zi)rB$Y%D#!4Y zCekmhlJz?cG|$y4^Ifi0+OO0q?KfzZ_T}V*baj0FdI25(NUbt{8?7>aXRR{+8Cqrh zb8PtCHvCzu?^)feRi<~5d|tjzXOY!D@@cU;z0X}y0wtBJEX;x=heaPzCBscv{RzFI1`D?4b90!AbTRlpy zi8ME|+C`2tnoqQPR!Nu7wYvNWm!Giuy{rHoKP>yL)|R^eN$p~FitIOapU84$reXO*WL~*;ZeWV}s^5tdHU7llgV^^2ovKsH^ay6^{y1Sfj_2!-~ z-(z)0Z#XiS&E?{!yV|b5tKF?mAL#ORR$mg)b$z^T zwaieLGp(L7+~r|b7s(ExT?!|G|5xIDt@;;Am*Z}qcFUH;B$)^wL!SS`51UPqI2|y~{UQef>F? zKeAf+1()ks9kkKqF;K`37d~?{QWqXSjTo)n}`_{HoRZ@(t%YesilGtsbw{ z_qJ+QjSY2rKE~^h~m2>P$t4|o;V0oj}SB$@B^$V*%TJ`1YiM1cit&X;O ztJRfO*INDFY6N2bAto~p%RUQUvyVh3wTJ3MO!0J+~?^@k$wPvV|9(yy;h6oxOT0q_OW`p)j3v|T7Amu2CMt6#^ieswg0uP=34D!b&}Qlt**5C zvDFIl&4Jp!yVapq$5@?a^--&zS*;@9wx{hHTWw`^oYl*%uCn^F)g<}uIc-;$F1NbF>OQNBBrPq2ED)hn$owtA1%HCFdpjmnpyX}>C2&9XY!>h)G% zwECgdFRXgaA8^w^~BJvrF4mwc5+-t_#==*-;ZC*piNR#08z(Iq?<)2e@sC>&#(Kv9NJ|ed1x;FnxM(TIu z*c7E>Ue;jwLYI7bFIthg4jngel#JB2SGTNz1qI_q44P0NlRfMo{k26%{^>f@AGuXN z;73+n@RKS3>v&-o|7AQKrawo?zhd(5-;I|e;~YHSqF;oh+fIM#%fI6CuZ{fEp8+f7 zyVGP}Rrhrq{ipNmEdS_(y!3h;DUVBKf8mE$9Rw7e-oz(D-kYV|^mH9Cy*~1qHad;| zgG1h;B7m1e4;t^cAt6sLcN0I1H%Lg)`S#c-UvMV_bvcwX-wE=XHuBQjmml&n^o9K} z>}<(Jr#E1eOi!3jPaX#)rZ-()(?(u;m4>?U^tJvlY?{0-I=!()rdLvi(LdeCX(KPa zdNRHH+vqFz!!SK26rJ8=nVxPZ?cWjdkLfLu*V;yX(4TEf zGB2&{D>}H1j5k&qmY3J+uuf06kIs{QLtc8zSA@J}`oeygUQBY)@vfKtz0F8c8L#Nq zLp8}7lPzyyYuYTQp}sprevh4#Tjc+yO@%dU)sV&>Ctk>oH&F!al?LDaXnKvZu-`f7$`r*l)dk<=V=8cjr%Db>j`$2hU zUN5iPet&D)d0q2tyyL#z96qN@ZyBcJb^dm3cw8_{$4tsRJ8w+qo`ZENI?Z<9*AJf+ zOlN_l5qZOdF}0meb4V~1ZP!7jGB7a*Y1RJpV3@W#E$@^ATAh?=rStBcXjLqucV3S! zJ!IZ_XKK6dd%dwe^76WN9;`jrc^1pa%RA1-(7Eauo%7n;7~0>Y%#L}jt^e9W``;q5 z9-8MhOUzCC-#D=ry6?>x+bl1~rlixJoY^F=evvhyOISOxCUgmFC6=m2UiHK>>2#|m z=5m6xs+3q0x`oOoT9wNyb3m(DqE#npRWi{^=Oyo9w{@V)d_-R4fVGe@ws>AB=zH3B zuXMRK4^;3|(UK8^sw@vXT_bl#B-h8|_`PK^FA8n;mbpB{7-9kMQYgE_u@rgCsEw4*red?S$CDx}d zMY}{R9o9P0N|s?j>%104oNV)Lm$ai3ZMD~p5^cNhtvom<(N?D0yMAJx+P6B1c4}p< zM7tyNswZ0M{HrBeP0q;3t5js2PR^*3SH8#^)v2Z>+Nvj|6KzZ9l}yY}r&>HQKkaoS z(Mo%rB*RK=_nul))|;&UJl#gzi3gsPR$rbT;7xY>q%Kvd1E!mjm~NYIJEld8OxGKb zoENs<>h>9XoKAb~B5(56BSW4ZgXKsZ+AAlb)Q)ntZ&&n)ErXImk>2{dlu)rTDN>UB zolz~({sO}_} zC5Ng>%=MCMTdXRvp_g38Vik#vyyUtTD@$zbCD*f9Nn#T(xxU4U5}SI-4J=lWc(j+C zWief1GcP&YVtI+pz2qE=#~@&G7TG{fl3%{?sa?0u*m8W+WdMy;EMRA$k7uqH1NRkIl-bC z(%qsN(!-(|($k_D(#xV5(%YgL(#N71a-u~H>1!E7PO^+4{VZe1$(AwX6w4TLs$~p0 z%`%3ZZW%+)u#6%7En~<4%NR1yGKLJYj3I+9W5^K87?N)pLxx($kYScFWVmGv8DSYi z&a{jnXIXZJbP0bU+rRi?If5m3b%wN&BUJLpsG6gOjP<{efq@}sTT?S+oJBKayhSsl zz@iy4!J-**jzu%%T#IJNM2lv~c^1u(^DSb?1(q>nl4T6J&@zTxWEn#)wu~W@En~xAy-(&kSi@?$V|%^a+PHax!N*@ zTw@tSW?6QIj1HHSLq_pZa>7X-;|zI6)JUEkRddvk>->^(x(W=LXHCtJ`4-KP>n)lg zH&`@77FaYxZnS8IEVO8b++@)Vx!Ix_a*IU_S!5YQZncadi!EcwZI&_QcFP!Yhh+>| zVi`m3w2UE3En~=CmNDdR%NTNxWemC3GKSn|8AFy?#*q6hW5{yL81jH+40+HphCE~$ zLmsw_A&*#ghRg|P%l0o`S&t!eogp9V>qnz%jvBJc*Y83P40+s|njxz#njueEG((=W zXofsx(F|E*(F|E@(F}Roq8YNzq8ajxMGRSQ8AG16j3Lii#*ht`G30s681jN;40+Kq zhHSKqA)72?$V-+n@m-74EfSBhJ0liLv~rlkgqLc$ZpFR z@{MH-`PMRq?6Hg?do5$gca|~ad&?N|gJlf)(K3eoWEn$#wu~YBEMv%i%NX*DWeoY% zGKTzS*%|U~xIngl@%!}JPG#!vCK<{uW07@v3o>l~;D3G330u)yuJ*^BVra*dH1rSvrJ*^6eD3G33 z1NaK0rx}1`1=7<@Kv;qFv^pS3fZprW0E84sPiq21kdn#CNuls65hUe)y*vqroJHI8 zx}{bqs(PtKbwd8z@<24Os4nfzqIzVrs6N>&YCtxNvdCspHrXu7A)7_HWV5It*(_>A z#-hdmENTM4qNV^WIvRjQ%>Y=`9Dqf~0I;Y90E=1zu&5OPi;e|gQELDewEI}f5E&ylIQK7K>Wr>$^z8;Edn?*0EQe8t)^-C=} zA>?P4F^js>-Yn`tHj8?a&7xjpv#2-OEb2oxi%uk)MSaO;(Me>ps2>@NP6lAnDF7@w z6@W#j0kG(F02ZAAz@q*DEE)j7qJaP`8U(Gkt02U1eV9_uD77Yhr(Fgz* zoe99AvjA8$5`aac09Z5{;4C^m6z(K~q&zJ#xtm#3MU@&8imG2~(fE)*On!+K9E%EQ zZx&4;n?>i4&7yP3X3<2lS#%!REIOZT7F|F#izboHq6^7bbP)iHE(T!HWB?Xj0>Gjv z04$mcz@ljYEV>kcMVA4v=yCuSO$T7n3;-5g0l=aw0a!E>fJIjUu;^+47F`3tqFDee znhn6BYXMj^2jDC^I~1NNf}~WEJMH9gW>JgaJ}VSeztp1ZL;ij8HiW>U8)$D9Eg+jk zHl|7A*l_(VYM+S_;6T zy8u{pHvo(70btR+04%x>fJMsySad%Cior@0KlRb0a&yVfJK`CSo9JAi(Up` z(PjV^y#m0ZEdVTf6@W!s0a)}J0E=D+V9^@@EP4}wMQ;JHXd3{F-UeXNI{++t7vL;< zJQPlsclf0IsyFVd&7#eEb^Tr_s(z_OABOzqRm`G~Xm1wnAe%)Wlg*+}$Y#-}WV7fq zvRSl~Y!-b^HjBO>n?+xevFIxR7VQFH(boVh+6};>Zva^IEdY!50I+B;0E@l@VA1yg zEcyX}MLzPDV3C)UxXX9|j8+e6_q zM39s-_3-n7S@epY(ZWel^-C>^CixdvGmDDR-YhCkHj7foW>E>US(HjPi%OEsqEckD z=m@e|RGMrS#mHC`2VhYe0E@~1u&68mi^>78s5}6R(g9dh0f0pn0a#QCfJK!7SX2do zMO6V)QD^rH71)yO~__Z zQ!*AE4Zxyi04!<_z@lRSSkwZ5MJ)kX)Czz_#{#gZH2{m+0I;Yn0E^lIu&6x%i#hlnBM7kONy#r zYEjQ5zeG*5s2AGkt02U1eV9_uD77Yhr(Fgz*oe99AvjA8$ z5`aac09Z5{fJI{fSTq)ZMP~z?MctFaIU-2Psd_BxVHSO-r?+uQQT0nLIw#5Rd8Ao% zF73^tiDa|rJhEAIKG`g~fNT~`BAZ1QlFg!v$Y#;SWV2{88H+9fV9^u+7EJ|U(KG-S zT?)XW%K%t(IRJ~M1F&cY0E?~wV9}KTESd?xqN@N{bTt5rt^r`tEC3eG24K;(04$mV zz@oVTEV>SWMe_j8qJpIGIU-2PQTm8zf?2dek45v7qUx7gbYqe~zqVPlkoIQLO=Pp^ zX0lmy3)w7ML^g|VC7VTy$!5`QWV7gYvRQNo8H<(xu;@+z7A*x}(Om#6x*LE+_W-cy zUH}%|2f(6b04%y6fJMszSo8n@iyj1E(L(?%dKiF3j{vafQ2-XL0ASHd02Vz4z@k+E zEP5Q^EV>~nyjlcFxj7`_EHI0{&|}f+q^SC(7OhG0->qvFt);zL^fcKlT1PgEo*|n> z>&a%(vt+aAIkH)_fov8%Pd1BQAY;*s04&-Fz@kk6EP4rmMK1%eXfptdUIAdy762B# z3c#YR04#b9fJLtZu;>i{7QG3;qPGB8v<-koZv(LC9RL=+3&5iH09f=s0E@N*oJCJ2 zg_G)uMKkoN<5Ol)3%$DjAStSTsYM?r`867tMW4{#Ec%pe7JWuGi*}ODqR+`@(HCU1 z=u5I$^cC4G+C?^tz9wVQZU7d21Hhth0a&yLfJJ)&So9qLi@pb7(GLJD`VoLdKLN1l zX8;!M17Oj902ciMz@lFPSo9kJi@dPiwqsEUfJI3FED8g#C>el7KEPS@QBt_G2$C{d zk3~DoqF*&c!cp~0ElLUdBeKn+60|pqQpsjfNwQf~ifk4gK{ks@lg*+S*({2a&7w52 zSyYCMMP&h4R1Sbec&$Kqjkr@vZ{MfJi_ z^-C?v4*U1#nngLZH;Zz~W>G`3S=5MZ7BwcDMNP)5>2f(7^0a(-xfJG+&u&6u0S=1mL-YSBml+g!`S!U5*Jr?x{N7XO2s887cu8~=E zBJIthzGSoLB(ho5k8Bp5Og4*7A)7^~lFg#i$Y#;$WV7fDG8Xj*V9@{o77YYo(I5a8 z4F+J*5C9hC1F&c)0E>nJuxK~{i$(yj=u7|>odv+6kpL_j1;C=w04y2{C zB(hm_A=xath-?;JOg4)qlg*+_$Y#+LvRO2hj78G`Sac}>i!K9T(d7UvnhwCC82~K0 z0)RzV04OMY8}{G#h|L*8;F;4gibh0h02a*yV9|U47F`d( zq8k9tqI1LH0U}7sM=H)lvnW^3XbZwo^-C?fIqY8|e`*~3PX89#n?;MrX3?!=vuH8d zEV_+s7Tr!Zi|!zsMN7zL(Vb+oXek+s?gC)Z-2g1Q2Y^NQ0l02VC+VA1^mELsl0 zq6Yw2^dJC>9s*#|!vHLL1b{`40GXRTT0btP<02aLpz@n`HEP4%qMXv*}=nViC zy$Qggw*XkQ4S+>&1F+~F02aLqz@qm6SoA&si?#!>=mP*2eF(s!j{wf1wc+rWB1pH)B*J^+gv0Gvf7lEV{4kd$V6EJ{swclrbLjFy!gRln4t zhROa7ZOx)av^R?ylg*+gWV5I#*(^GmY!)>mn?=pZX3;TZv#15xENV%{qE-MbIu?LM ztpQln27pCv0a(-yfJN;ASkwW4MI8ZH)Cqt^#{saYGXRUa0I;Yl0E_YfSadu9i@E`@ z=mY>3bq8Qk4*(YR1Yl7wfU_tkIsBvuk}_Lja;{nQxgLvpCr8yUwdkZ||NZu6Q9s(7 zMJJQZqEpCb(Wzv!=rpofbUN8AI)iK$^(UJ}1IT94Kr$8$0$|Z#02U1aU{O8*i-rQQ zXcz#Ch6Au@1OSW91Yprw04y2_z@kwAEE)~KqA>t08VkUpvjJE%4uD1D0a#Q3z@iBN zEIJ2(Mdt#XMJFbQlRJn--|JJyzGhM1;D#+Zs(z_Olal>foy?*OX>S%?L^g{qCYwc* z$!5_dWV2`r*({n$HjAc_&7w=mX3=G2EV>+kMbiOTGy{M|R{*f+N&ptk1Yprs04%y1 zfJN5;uxJ(li)I6`=vn|4%>iK1TmTkb2f(6v04$mhz@qB`SabsbixvQ|=tck*Ed)4= z&QA_^6+u!`^nKSCm__V zlWZ0(C7VTek2LV|05CDrF24K-6 z04#bGfJG|+ShNy=MUMfnXcYj99tU92Y5*2J0l=as0a)}D0E^ZDuxKs7S#(Qsc$Nr~ z^0FR_7MVpC>ly9ofy+}5THj>SvO=Pp^ zC9+xcGTAKJOva*D09dpIfJLtYuxKj)i(Ug@(dz&#dINw(ZvwFBEdUm617OkH04#b3 zfJN^Du;@Ji7QGL^qU``I`T&4M9|ExGBLEid0ASI_04(|h;4FG3IsCc^lF~>|V(ZPK z*?On{X>wHkQj5Mw_J26uEc%l6X35ZEC3c|1F$Fu;4CWThX;uuDL?9+{t>>r)BjN4Y?SLq)i1TEiSJMCX%;o5 zy;*cL*(_>CHjA2*&7xz-W>E{WS=5qj7PTUqMaPoOqSjKq)ER(9T>x0r6@W!~04zElfJNN^Sabpai@F1_s0RRxdIGSh7XXWT z1F)zM0Ex4lG&YNF)X>+Ds$Xi+DZc-FZ?ouB+M7kEk`r4FzD)FaQ<}2Vl_%02ZAIz@oDNSTquV zMWX;%G#Y?KV*pq*7Jx-(1F&cu0E@;0u&4llMH2v6bPfQE&IMr6L;x0@2f(890nVa+ zet4G%l5(S73Y}~g9j_Nj7x+>2OD($C_mAjn7EPwTS#$~6ESf?#i>8vzqG@Ea=u)y- zbQ#$!x}0nlO(&a0GsswU1pte#1Yprj02W;Zz@n=GSab~li)I0^Xf^?mMK=JjXaN9=ZUkV_LI4)s1i+%30a$bkz*%&mA8ssyq{s)D zd&w7>MVs_kw8)RDUux0qzJFprv*-@mn?*~=X3?EwvuG*VEV_$q7TrxYi|!$tMfZ}; zqWj2Z(K0d?-4DQ`I02VzAz@kS0SoA0Wi&g-zXe9uP9s^*}DgYKe z4#1+-04#a}fJILNu;?iO7Oeqb(OLi&Jq^I3bpR}S2H-4O?1#@6K~l!*rO<6=k$!PS z@_Ik2eyK&z`~Homm_;wp-Yj~NY!+=Kn?;+*X3qF2dS zv=x9wuK}>=bpRH<0l=a+0a)}F0E@N(u;^_77QF+&qIUsU^d10<-UndOb^sQA0KlRT z0a)}A0E>12u;^m|7JUN1qE7)>^cet)b^@G5&-vjsB1lSQJr->+i{4bFKKG;Qms+&T z_dhtzEc%-EX3=i4S@aFrEc%vg7VROMMSIC+(RXCC=zFqR^aI%}`jL!9KLN1lX8;!M z17Oj902ciMz@lFPSo9kJi@b>4wqsEUfJI3FED8g#C>el7J^+g%04$0Eu&5XSi;4rV zC-5I3c#Y004yp6a29>(ha;zpMf!W!^E z4FDF^1Yl7u02Unyz@no7SX3K;MRfpJR2P6n^#E8@AAm&-09cd-z@lsb7Ucl2C>MZ5 z4FOox2;eM=MZ(96ASt)$)pb1L?)3FLl#?4rqUx7g)GXqU8fX?Zr@dKp4B0GdK{kt8 zlFg!4WV7g4vRTxcY!Gsb7PSXpQ3n7Pbp&8hCjb^52f(7v04(YPz@n}I zEXo65(eVH*>IT4~698D$9e_nW09e!$fJMCkSkxPUMSTERbRqzY`U0@%Bmfrm12~JC zM#9&MASn~|BzCk}^pO5K8syqD#qU(Pd<_=yI}IG@Wb~%^;gaSCGx3 zE6HZjOfnW-1;C=K0a$bm0E=b;uxK^_i>?J=(HsC4%>`i5bpR}y2f(8F04%y5fJHX| zuxJ4Qi*5v9(Lw+g-2}j*n*msK3jm820kG&+02VC~D*#xu5`aaI0kCKl0E-?6V9{y-7CiyLq9*}Z^b`P#)&Q_* zEdYz224K-T02Vz1z@qg4EP57zMb818MR!EPLqw32eR}v=Virx%uptsvztp0Q5&zON z&7w`TH;Y~(n?)~^&7#d@v*;DFS+s?07QIR~i?))@qSwe~(d%R^dINw(ZvwFBEdUm6 z17OkH04#b3fJN^Du;@Ji7QGL^qU``I`T&4M9|ExGBLEid0ASI_04(|hfJL7Iu;?=Y z7VQLJ(dPgx`T~GOUjm#(FGRw3iy$eF=o#%rvnWq*`@f1r)i1T^n~4A7NVDi$+M7jt z$Y#-AvRU*U*(~~=Y!>}MHj92Fn?*m7&7z;lX3;(}7VQUM(Jufj`W1jhzX7nwi`s2F z7KH#qI9xZRDo<3RV155 zmB?mMWwKdRg=`j8C7VUn$YxOn8H+LjSX3Q=MKu6eR1<(jwE$RjBmj$!0$@>X02b8& zU{PHF7S#h_QGEawH2`2y766N~0a%m+z@l6L7BvK5Q6m5rH3nc&695)91vrb!M8i!* zkd!)lr(ZVe?(}!*f$8XIRQ*zmT15Sm&Nho$(%vj;MK+6$C7VU9$!1X-vRTxYY!!(W>E*SS=5n?MV$axbQ}PSIs>q%3jm9{0Z02cKDV9|*HEb0ruqLTnv)DM6~Cj+qP6aW^T3UC%RkA^3SASqu;Og_de zny1I2)1p!JOD!4@^=}$)77e7mSu}`j77ZqwMMKDDQ9ju$8cH^chLO#p;bgOD1lcS) zlZ-`Y0kCK!0EHXRA z1%O4109bS@0E-p_u;?}b7TpfOqB{W2qN&kvv2(dO=ki3EP51xMJoVU zv=V?tj{&e~6#$DK2Vl`^02Vy~z@jGsSo9PCi`D?JXe|JXo(5piIsg_u1Hhv704#bI zfJM&%uxJASi=GEy(F*`)(b8!61Q8@R?gKiia_{^8o=k>GCS@j}_mI#bB%$}-GD9!Y z2_b|Ifh1Jvy$VS0y(5B(pn?<;5kXODA_`JPIszii_qt~PzezZ*d%d@3-RF7lXT7ZD z+4+5wJ(*-aOeW<7QFN9qiq5e`(GP4CohP8^M*@m25K#0J0YyI(P;`-iqDur6{X#&| zWde$>5KwfLfTC*z6kR8v=mr5rzYXA0>)%alRdBG@P@NI+2` z0*VR~P*j9~qM`&86(gXiH~~c^2q-E^Kv5(CMWqNRiXxyWnt-Ah0*Xo#P*jG1qOt@O zl_Q|2JOM=&2q>yZKv5-vsVKXjHEgs}R9F9yYz{y3GyMqt5v{VHUHj6Cs{7e$jTJ>T zIA0XiWQ(F&Y*AF3EsE-}MNwV0D5}R6MfKUDr~z9PHDseGmVhER0Yx4HiW(76)R=&x zCIl2UC7`Go0Y%LTC~84KQA+}fS`kpxnt-A=2qJ6!m6{qCRX<)R!%a`ms^epMaty0*VF@P&AN$qGSS!QV1wYC7@^!0Y!reC>laQ z(NF@4h7nLSoPeS?2`CytK+#A7ibfGoG@5{-F$5HiC7@^=0Y&2prlNR1>ox_%aZi8M zv8yP`sYy-nvuj^k(G)-1iHV|UD(8!$X>3t6oh^!Hutm{KwkUdwEsAEbMbT`wD4N3- zMQ^iFG?##)c?1;AC!lBn0YwW5C|X27(P9FMmJm?1lz^gT1QabNplAgFMJov?T17z7 zY66PZ5Ky$1fTDE-6s;$qXafO78wn`dL@*Ui^0PivKpcDZx6USuB8Pr-z1h#MeQ8DS z_}MZ~5k=cMUlhH|7DYSQqG%^u6urk5Menmk(Fbf%w2Li@K4goc-E0)?A)x3Z0*XE+ zpy(3NkGwW1QgvOpy)OMMRy1&x=TROJpzjE6HxSkfTD*4 zQ_)F3>nH_8eLPcez7<8w^cS*!_p@tXTG1bVwv{tP(NoSBMSrqI(KEIvdd?O_FW92! zC0i7|VvC}`*rLerm(SZpk%f&S9|DT31QhuaP-G*ZC=&rib^?n02q^L=pvXZ$Q2+r& zfdmu<5l|FNK#`MxA{PNgAp{hK5>S+xfTAn}6lEo#C>sGq*$Jki$9~qs3W%eRzWaG1 zihT6Q;cwTzw4yxzwrg*RqP(0hit@2VQGT{43S*0+0&Gzf&K5-xY*AE@Es6@UMNwfk zii!|WRFr_CVgwWwC!nYV0YxPVD2gPYs1yN3Q3Mo46HpXGKv8J|ipmgBRF;6Eas(8W zC!nYT0Yw!FD5^w2QDp*(st{0Am0&8$lgS(O?3Kh7eFRlz^gP z1QZP?py*8kibfDnG?IX#Q3Mo?CZK2x0Yzg8C>lpV(Rc!iCJ<0Gk$|E}1XEErf9nDT z#Iaw0)iF^NJ=ed8f3m+_`_hW0``dQU7ezBTUlh$`i=wyKqG%Rd6wPLfqB(3)^fp@* z&1H+Cd2CTMpN*mg1QabKplA^RMT-e2T0%h4QUZ#W5m2<8fT9%y6s;tnXcYlPs|hGt zLqO450*clVP_&+aq74KTZ6u&*69Gk=2`Jh^K+#r$sc5Rd^@0N8sHdjyG*Q%Af7-vz z->!XWMLYa$FBgiUot!U<-eZfR_t~Q81GXsI#TG>$vPIEuwkX=e7DXSiMbXD>6n#QK z(Ov?I_7PC@DFH?M2`D;1K+!=0iVhJ_^cev~hY2Y9oPeSu1QdNiK+#bGioPVE=okS- zUlCAroPeSe1QdNuK+!h@6rCiPinjY(!xt$#18Kd?p7dA2C}ku8cYutm{NY*F+xTNGVnqv#R=MZXYGbeVvnD+Cl> zC7|dU0Y%pdD7ryF(XRv)-6WvsHv)=o5m0oSfTBAD6x}7D=pF$@_X#L^KtRz$0*Zbo zpy&|+MUM%lqVN5!Jrxi~Lk;JYC_1FSHT%Thu6=1m&-`sumx-e1oG*%Autm{JwkUeV z7Da!tMUml<&)h|kg)NGF*rLeF7Dc{n6xj$U%0xhsoq!@g0*d?zC~^=`6hJ^xAOS@| z1QZ1mP~;?_$VEU=2mwW*1QcZ^pePFgMOg_b%0@s@b^?lW5KxqpfTCOkQ_)j@>vjdi zab7;x zin2vfF*b^d6HruwfTEHF6h#tHREmJ2C<2P22`Gvopr|wfMP&#mDoa37IRc8x6Hruv zfTD^76jdUis4@XXRR}1mNLI_%n) zR#ewv%eq<=)#H3oRG%%18n8uCL$)Z2Ws4#=TNHWNqNovD6g6gxq9$wh+>%7Uzqi*=$iXhb@ZUW{aY^Y*93iEsEx| zMbQGbC|bxCMT^)dT1-IE5(0{r5>T{^fTHCD6s;hjXe9wfs|YAsO+e8a0*clWP_&MK zqV)t6Z6Kg%BLPL52q@Z2K+zTginbC^w2gqGcL*rjPB0bCa9EEhAdV>gg~pkpsFeOp z|6PY&`_hWuci3)h6h$9!z9`zo7DXSjMbU1yDB8moMIW(6(Z_62^a)!O?PZIieQXqc zN97WFQi}ZaPw&4ciZ*yZVRP8EFRkdD!xp(k z6#c;YqUbzZ6#d8+MHkqj=qI))`k5_?F0w_@CAKK~g)NFMvr%+~fTF7e6kQ{r=sE#K zHwY;Dm4Kp~1Qh*7K+!D%if$87bccYVy95;7BcSL$0Ywi8D0)ah(eDHlJtCm!F#$zS z2q^l4fTE`aQ_&fRwS@xWc&y=^6-CYThqpf+cI`_mdg-vGY!gMVIA0X~#TG?IfPCgI ziY#nV9z3MQb)NkEZ{ zfT9orib4q}%1l5}76OX05>S+lfTHXK6y+eGC?^3$xdqw!SZ_ z6JXcAw4w$9w!e0WqK2F=ielNK$juf-9=0fI#1=)3*`lZkTNE{Ai=t+1QPiA`q80=c zwIraZ6#+%92`GAlfTA`86tyLws2u@C?FlIAKtNGP0*X2jP}G@#qBsJIx)4wlPe4&u z0*Vp{DC$N)Q6d3F-3ch_K`<573$Pa4sT4icKMYb|6fIWI^X(a6*S@r(z5%v+?~9^- zoG*&{vqe!7TNDjoi=u&SQIyOUMJa4il*$%GgV>^IFdIcf2q+p#K+!M)iiQ(V^dCJK+z-uiY60KG=+eosRR^FBcNzH z0Yx(irlQ^f*4_$;qnSg&=_85~^@F6D0e0<6E1DBvo4!jFz0LWeXf9h6&0~wA`D{_N zfGvs^vPID%wkTT67DY?gqG%}_Mau{%T24UG3Id8&5>T{?fTGm|6s;kkXe|Ln>j)@X zPe9QI0*W>gP_&7FqRj*pZ6Tm&D*;8@2q=1ofTHaL6unD8(GCKNb`nfQvjVI;6cEQz zeP1+N6xGuo(cTNNYhPN?hXJ;4cZ;IkoG*&@utm{FY*F+vTNHi57Dap6qG%sm6n)AT zMf=&J=l~l<2MH)TL_pDJ1QZ=6py+b~ijELa^aTM$M+qqUl7OOP1QdNmK+$mmicSzv z^fduR-w;rAl7OOb2`KuGfTHgSC^|(z(P;vT&JavR9|TyRC?Jlk8qO|JG{^f1TYz2r z(u#fzux0;P6kXtaQS=jA6#dK=MHktk=n`8L{lXSSm)WA|3R@IiWs9O~Y!qE5py&nx zMZXeIbd!Lh-v}tWML^MQ0*dYsP;{4oqI(1s-6x>v0Rcr12`KuVfTBkP6g?)O=m`Nu ze-Kdglz^f?2`G9-K+$u8spy9QYgGlraYTRB@w_OitVz8Huxnphkr8O?v{w{a0_8J# zQRKrGMOL;b@@0!68(S1*Vv8a>TNL@RMUg*S6gk)^3Lu~;kbt5f0*ZnOC~^`|o^6(@j!po@h?$ST0PIVK%iaw(uxWN+SYz5iVAbSC@R7hMMc@7s2E!m6=#d0 z5^Paak}ZlN*`lZvTNFjHQ4~!;Q49e^r3ol1LqJhk0*cBJP*k3Pq6!2QRV1LO5&=b( z2`H*UKv7i!imDM%RGomL8Uz&8B%r7k0Y$Y5D5^t1QC$Lx>Jdyu5rNjD3W#H$zAq{m zXnv+28mLD7K)d#(6}ba#HxGy+59f=bMr={km@SH$utiZ*wkT@G7Ddh3qNoL16t!fF zqE>7awI-nG4FZbV5Kz>XfTDH;6tyRyr~?5-9SJDvL_kqz0*c}YDC$B$Q9J=fT?r^k zAfTul0Y!-f6m=({s0RT>Jqal4ML^IFk2K2VT+=nY*93fjiTWM6un76(Fg*H zMiNjoih!cg1Qd-SplB=sMdJu48c#sc1OkdC5>PaWfTGC+6ip$ZXet3k(+DV+Cf0kP6CSFBcSMg0*XE$n2O#G zv@TIV9L@F5UC$Lor}WqrXxF~9qK^V?pL`*TKIVK;^a)!O?PZIieQZ(mDO(inXN#f( zY*BQOEs74YMbT$$6dfj@=yL*!ju24v1p!4z2`KuKfTCjr6n#ZN(QyKbP7qM^H33E6 z5KwfIfTC{+DEf|oqVEYPIz>RyX#$GQ5KwfMfTD8*6#YOj73~hRUQ$3DCG_3T9#ND} zJHigI*S@qOYmlwM zaZ%(O^!jJ|Hnu3r#1=(%wkYyriz0uvC~~kxQ2<*M1+qm^5F16o1Qa<5C~^@{6hc5z zC;>&82`I`!Kv7l#in0+Uq8egY4RuR#Y^|HuGyyRE+cGzNk1`6qR6$ zqLOS;6v-AvrP!hyZKv5+EiYgOO zRE2<|sst2OBcP}{0Yxa0ZH^viiPgZjfF3(ux)a+2T%%qD7o9 ziWaj)(Gs>OTFMqh%h;l5Ia?I1V2h%aY*Dm|Es9pNQM87DqO}ARts|glJpn}<2q@Y} zK+z@wiZ&Baw1t48tppTpBcSLV0*ba1Q1mVVMLP&6+DSmsdju4{Pe9QJ1QhKepy)#a zigpuBMe~EK6BH1~IsH|~1)}Jn{!D*QkX`%IiuMNC)}Iwc`#4_|eaaR^``M!C09zCt zWQ(FhY*F+XTNE8;i=xljqUZ=4MPCq5bd-RiF9|3*MnKV51QZ=7py&hvMPCz8^bG+; zCkZI}mVlz~2q^lVfTB|b6rCoZ=nMfxX9*}eM?ldJ1QeYopy)>eiY^dLMIQ%Qk0~II zFZA8dC!*+z{&vVuL3Zs+EBYnKcIyXGbeZ!-(G|8Ry2=(s*Vv-yI$IRoV2h$(*`nws zTNM4q7Dcz%D7sBR(H#Pc?h;URkAR~41Qb0Wpy(k1MZXhJ^oW3>#{?8TA)x3F0*amz zQ1mAOMb8K*dQL#m3j&H>5>WJtfTF($C^CZO6LS<<2&SToK~~p!rRcD}FS;a(Zs{MN z^$E6XUs_S7U|Y-uQDoS+jfTG+46y+hHC@%p;`3NY=Pe4%^0YwD} zC<-T_D1v~Zf&>&5BA}=+!BpfMY<)ukact3WY{BMd`s$Ik`h+dmu6=1mC4y~3eilU~ zIbRe-vPDrTwkV2Xi=t?@D2ic=qS9ycKv6vcis}VtO zpvXfo6%`A%E>l1p`}NN{78gaAG^s|xcI`_mY8GtUcS#gA=X_Drf-Q<#vPDrVwkT@N z7DaEcMNu2JC~C_VMeW$4s687+9SA7uNI+310*X2lP!vZ%Q5OP=;t43~NldR(O3eC#t~37o`9kW1QbmqplA{SMUx3AnnFO)R04{o5l}RpfT9@$6wM@{ z=q&<@W)V;{n}DJ@1QfkZK+#+RislheG@oE9N(r_WRX`ji^?gyQC_1MfT`vf>YhPN? zl3-ixHBq#b^F`4zwkTT87DX%AqG%;s6s=;5qSb6sw1zE;*0M#>IyQ>d6Hv5)fTE2A z6m24)XfpvtTL>uHNHu3U$8~dQMM@hl8vHc1QdNmK+$mmicSzv^fduR-w;rA zl7OOb2`KuGfTHgSC^|(z(P;vT&Ja*^mVlyj1Qh*1K+$;uihd-Z=mG&nKM_#$GXX^x z38tcb!PXBH5J#APDDWY6y0Qt zqTkq}=oVWP-DZoTJ8V&OmyM!(1QgvTpy&YsMGpxm`kjEHM+6i-CZOmE0Y!fhQ1q05 zqCW{JdPYFea{`K95K#1zfTC9f6#Yd&k>Qk2+fig8pvZ@SA}aw!z64Xz)2@AKMgC4(?%Sfs!TF*nfGvsw*`g?jEsBEKqR7b>MJ~1|3So<)P_`(_ z%tlcb0*bN{P?U{;qU;0|q#Su`{g@B@X0*bm4P?SJGQ8xmL5(y~k zPC!u)0*ZPPP}GZnqTU1)^&z0BF9AjU2q@}LKv5C_MFR*Z8c0Ah|h$vcaQ)98y zu6=1m%bm6|k44c6&KE^1*`jC_TNJHki=s7bQM8sViq^43(R#Kh+Q1e?8`&t@L_pDI z0*bZ}P_&hRqHP2ey+c6Jb^?mtC7@^r0Yy6rD0+{8qW1|X`hb9ZU)Ued@GpUs};2r)}6DqUbZu z7e$BJqUdwBC_2IxMPIN*(NVT2`jRb*jKM+uKo`9ks2`IWiK+#VG6#Yy<(M1A^E)h`l z3jsx!38tb0PU{K<#NpPTmK_vD{`yOhSDbe3ODnqJwC(>>6#dHiqUa`D6#d2)MYq_Z z=r&sv-C>KOyKGT(k1dMsvqjMZHi{k+Q1m+iMUMz5dQ3pk69S6_dR2q^lCfFi>spSGjOLO_uZ0Yz2GT2Y|OW_uxuf;e9k1+ztwlP!u|Y*7@#7Db_KQIwf2in6dp zQC7An%Em@fb^?lW5KxqpfTCOk6y+wMC=UTec?l@WM?g`20*b;2C@MfeQ8)ob5d;(! zB%r7e0Y!xgC@MlgQBeYliV;v$oPeSd1QeAdn2H=OYjFj{amZi632>R8>7URa-XdLg z?Mo|)aoIetL{VwZ7e!^*qNpre6qRF(qVjA}RDmsuDzZgUCAKK4%oase*eI$>Kv6XU zimDS(RD*z`ngkTpBA}=?0Y!BPD5^_9Q9S~R>Jw1ZfPkWg1Qf**P~;|{$U{I;BLa#V z6HwHIfTE@Z6g4BDs5!w@6y>rGP(U2F^`q-(QS`RHV`|~DYhPN?8!p=%Ltj9&;oFAu zMNwO}C~C(RMeW(5r~_LRb!3a8PHa)snJtRq*rKQl8%6O16m=z_D1m^YZUhu15>V8g zfTA7*6!j#as22f6y$LAlLqJhq0*d+(P}HA*q9g)}1`tp*kbt6O0*X=yC`u)uXb=HK zg9)ahRxay@3W#Hg{?=J*QIuPMra#1G*S@r(H(j=~KB8y@=Zm6|Y*93dEs937MbQ|x zC>qNaMdR3_XgpgKO<;?niEI>2BA{q80Yy^?D4I$@(KG^zrV~&!gMgx$1QfkRK+!A$ zie?i~G>3qqw+SekOF+>)0*dAnP_%%6qJ;z$Eh3<3F#$zO2q;=gFcl4RSzjn14!8c= z^>9%%S>G2ebJ?{ot!S0Yme(eVR&%~6TEiAaYuTb`9a|KwXN#f@Y*Dn4Es8d=MbT!q zDB8kC(N+SAwh>VD4gp2m2`GA(fTA4)6zwFS=sg08-Y1~w0|JV65m59Y0Y$qBDB43n z(MJRneM~^nCj=DjC7@^@0Y#q@P_&eiY^dP^b-L^KNC=Nk$|F01Qh*3 zK+$Caimnh)bd`XjYXno#XD;g$1;mj>-xnPgMLYGQ>+3GN_N5j5=CW<}7e%)?UliSD zi=sPhQFNCrite#R(S5ckdcYP%580yVceW^c#75C$0*amxQ1k}@MNbJR`jdd7X9N^I zC!pvB0YxtfD0)Re(O(1<86om%JBlm>6!{QPWF?@;mw+N00Y#YzD6$h!2C>H@mxd|xBLqJhp0*dkxP?Vp5qA&uA3J_2fPC!uv0YwD~ zC@MriQDFj#iV#p#lz^gQ1QZn~pr`}^MI{L+iX@<@6aht11XEE^h&4-~Qgl{-)iF54 z{7ip?zAuUnv1?yiQP~h%xnNOLj`KxPdA2C3z!pUn*`lZtTNG7hi=rxQQB;*JimI_i zQFS(oY7kIVlYpXH1QgXKpr{T3MRf@%sz*RkeFBOa5Kz>RfTCCeirfSgc?c+KL_kqv z0*aatP}G!wqGkjXH7B5`1p!4Z2`FksFcp;!v9?!092WgKS{YH4ML)W39b(tMw4!z) zwl`g(s6FS4q7H0P)R8TUIO(+LUjmBy5m3~hfTAPQMS}?_ z8bUzPPy&jE5llsGLaeJ45XU}!U({9I?Mo|K8)CC(6-DbfUlgrpi=qu|QM8dQiZ-!D(Pp+N+QJq^ zTiK#$8(S2;!$#3|0*c-xplAmHMLP*7dXIpj_X#NafPkW11QdNpK+$djiuMpt^br9? z9}`gY2?0fW2`Jh}K+&fJ6zwOV=l}sl2MH)TL_pDJ1XI!K5Nk;V#8FuP^!^%A^p(CZ zIvirxzOFN%(_MbTGmQFNRwicYXa(bsHI^bK1Son(umZ`q>gJ2r~G zC!pvQ0Y#??C^|zx(OCkD&Jj@b0|76(xZ-&^lFRkcKh;438 zQFNE{MbSOBD7w!UMGx4b=pkDa{mvFekJzHmCKf5vcErZi^y+{ShrV)UJJLMWLa#A99PL%$zTZvam%_R<1TNLGFi=td?QIwl4it?~gl$U^_d;}EbC!i>dfT98f6onH|6hS~yK>~^j z5l~c^fTAJ<6cr_)s2Bl7#R(`XK|oPS0*WFDC@MujQ4|41(F7F55KvT_U@CHjT3;z3 zjw$*}L?NN(XZmyXeNmZEyY{6ORS31^&nJp1a=s|4#1=)B*`lZlTNG7gi=t|5QB<8R zifXV$QBAfes>Mc8Z32qw5KvT?fTDT?6xAo7r~v^*4GAcUC7{SnK#_-lqDBN1H71~_ z2?0e-2`FktKv8o7idqm*)RKUrRs#}-9h*rF(&EsDCbMNtA<6m?^ZqC~bR>dr<{4+4sM z5>V8OfTG?66!jsXs4oFU{Rk-PPe4%;0Yw7{C>lsWQ8EEVDFhUy5>PaVfTFj*c2m2T?Rpe|Q@iYS+HBqOqa2t>L0*9OsLo z@oZ5vfh~$AvPID(wkVp+7DZFoqG&2x6is7`qUmfD%^;v?CILln5l}RXfTGz16wM)^ z=xqXu<`PgekAR~21QabGplBfhMT-b1T1-IE5(0{r5>T{^fTHCD6s;hjXe9wfs|YAs zO)wRW4z-?CKpcjIt`Zodw=7kNTrgLFY!>H^0skmV@bVfuPMk8mhD8p#xd^g50 zS~(w=F^sm(D&-BMqjPLU!|3AtqOxIha|Ts2jGoSxH4LM#b8#)h7~s5E$1qZzh3Xr| zP-mZphB3mq(`^`IoPRVjj0w(aO$}p;b9{5dnBn}grD4o=I^QsidCt~t4P%jWX?w$1 z=KQ6jVXSf%i8G9K&VKQRvB~*ISg5UM^I( zfW=j3iMk0auBpq^ZD4VIvqIen7FX8Q>Q=D0I;>SUgT=Lay}BJNF8#0B7qqzaKSy5F z;?n<~bV-X#|AWBM7MK1PUCUZr`k&;iXmRO(Q?aVWrT77-YG`rk ze^;oH#dY(5x=k!D{V#j8vbgj=&Cu53(!X23qs66vIeHh1OaFH3ZWfpR^~60bF8%vu z`&wN37laP5xb$y$OtrZ5ujm_Uap~W&Hp1f4za(pn#if7C(FBWY-z9YmSzP+}jLfjO z^e>8-ZE@-Ur~f>QOaEWB7g=2T|7*L<;?n5M87c4IQ#nVd`m;UP4Rf|i1`QlfLOMm`(+v3unK-{;u^drDW z7MK1I{?y{q_rWhLM#w$=V-D-gzjC1pi(x6Fin>bbuasq3<|Or{e@nUGSvqA_>I_SH z8KL?)6=Y1Ys!=g`y!XYXtG|1eO7fg?>e4KgWo**tRFUzn9#v&@v8Yi^#xwPo+EQJ{ zR)-ojWOUcppr$$0Qz4c@!I=ZB!MTH5XAe;-48y0O5fD&aCBv|0Gpxat1F8g63W&|D z-bi_lpJCX_8M7@$vxyK>>jQ71dkfm;JSu@>egF;ZhwkZRRTp zkc(7PUu2+Mr1!b$7a1fMDK8bQPO_z64`-0NcKS8DyieE+BShX3c_pExEH!d+C5q$> zv4m!-nPXw?oaz=To8ijkQ5Rw4QUB??NcHx6|5yKyzG*Z5$+*wB)H}{-u1@i>JP!^s zEb5PXS$*r2DixI+AJsi&KvYU{LR4~GN@#>5!1vZBTMz zN`~j@msc-cDQZA+uYSE!dks!BqIxFvON@%|n>aM8RNth8_`XpoJ>!!TqmmQ*C#J-w zL?xDvOGzEntyfZ1YEn|)gr4!e`lm$oNJxl_Pwp2L6CGD3u5@(in7Ei|9V1nY?4Q&> zF)}f}Yp=+d=u%}O^|MQ-gk-l9%+`G)LXsJQ=(c9h)?cQe^CFpR_bl((X8*Fl(-hP z$~P|eKXEe+j!#Y0?=8bHZ|LrW`X`i$E>|i+Q;6%9*gbww-_*F&VFMCVO7+yj)Xmkc zSN~Ks)LlW#I`!hz)l8_9)URJsf7P@&bzf%lQnZ$_*ld~qt3S5TOzPR08mW)*maMh_ zeQ?^s^g(s+3{%f8?R~MZXj^DLwZi{fFC6|)Uicqf@_*`u3)sTcmCmc)!UFPc`R~1@ z|LFSs-}i3uzE}SHxBEYOZ~TK7{`YR3sDJA={ont(Z2vp{GX9@@_x{5-`5(~wUn2Y; zzJdSu-IM%#TK;~PU;F>YN1%W2@9;mo4gLYL{{z?O-+L8*fB*gmKJ5L2chrCGCiuVe z@A*G^*Zu$HPT@a^PEaNl61@jK;Ov#?@)ks!_Rl&QR|Hc|moR&3B`^6!VD;SD^x@s&}6End%)Y=aoylFm-)+rKRQN z%cNhAI%#Lb)ZtaBD=uef4;j8@^*{BMn!1Ty2lX)D8uk8HuS&9px=jdgZCQubpZ1P3qqx%=p50sjMe)99v|NOeD%YfT+I7-@L%lClEB(sV<%TaK z&r6fQE03v|c2P0u*ua5}m~?&Wt&mrZh_u^Y-5GeVKukKN7-h+9(L6IYZu6j?%oc z^cz1W{nn4kaPzBM$UG(ehURvNsV#3iw?d_~>#N?sa&^=1l(>n?rC%TO=J&qU>9=@H zhMPRYO?UnY4GIdPnf$={G#LDK}}_%~(;r z|B}+MnzzaSRcd6dXBAee95@(%uk-+B{#~{Tk}a{K@9KJjOhjS1u-jNG~VgN)JJG_`6)e< zl2g+@3@XW73sY1YrnC>=>hGZUMf45s<*D8q<`WrwrF)7=2Njbpid#fqS?|f}Bf9s< zdpt({9th@0%F)h{SwB^_O3sNP8E?n76LJni=lpW8@5VtERt$)l&_c zv<|CNsZyB!j!3DPF#SD|=!&Jwh80at?3);$l2|M(vR}f0LDdq}dn|EiWWO?HR7mYP zs9#rg?A|viJ~dK(L#3L!S-R<N_lhD@OJ!)lYqo zrbM@t0VTQ*2#f3y7TL6PSfu)4RuUWty_F*eA+hO73zb&`9wO|m~^w6g8&s-$JJHw2z%$)NygIe_-cvjp>gS(;q6ThoJB={}$-0m*$v$l8nq?^KhnaoS?p1j-nf{0`{Q)1S({Ay!$CGIf6w@9P zX87Ba{&yh#5gj*h`s2B@8_s-CXf&u(r*c?P{r9C-a=);8{kkT0>!uz|x8j?R-oHY8 zQ?b~8{TIpzRNv|POZ~AJJ|lwF_kZ=~kN!q$tx9Ue>+e$9e$y{Su9yC*{wM&IW4&?xh;7t`Fz4HrS!L9|K(4{SjFH9s?y-8xe16poTR*>9+BcKU=l9L9_49XR*lMQz zu^Q?d+Zp~?4fW#y8U9!e^^N)rf2@Z3Ie-j*)Q=ZsSo)jR>RbL9{#Xt5o$L&MtcEkg z(k~xssGk?`zL)gv5~{yP`LEyWESPE(?Dj98%Bgeo4@mf^A1%_?z(>8)^!rU8v&vC@ zC*JT;udaYTs;f~{y1u>j%c-9f@*dUC2YHXR<=9M)t>vh``|5puZ#fQ><7hcfkmGDQ zu9f3XbsOo|vrmrSt2a&Wi*kId-T=Mz|F2UYv#TGO(#HrnR#HDXpm#kvc2IAt-aX{F zO1*7*zaz)%>S?`ymt#qF!|Pp1j>+oBt@Iu($35x?uk`+0j<0f=J0Q1ttgC()OFzH4 z9H-?s_d+?IRPR{*{Ga5Qt)RIhui=uDPem@z8v8eb$0ke6-9e7?mYI9C9M7wt;M2Fy z4LOFbHg}{PyRS8OiX6ACH}^+!e7Movf61}p7IW8=(f!kmH!o z%{^0&N4_xk_i_w8X6~GFY;oM&adKSrwYk^J@#mA~z9q+k-Uom%XIkviH?sz#axnb^&a=fH|)KPo5 zBgewG&0R*0eearkm>l1`Z|?nae5!sNQlD@8-8@!*Y#u#wobZRa=g9HcpXNR*N7oB; z=au6dugskw$7SlHy1x9)a=fg5no{q3axAKT6iM%La_p~uzEbZu<@ka6K})?4%JG@{ ziA%lh>Q^4s=m-^UPj+4~SVCp?rj>pvxW9t2b97EMlW$K+@j&0SCXX>3O#}(@5 zH1*yp$E)fGHuZiW$KvWIH}$R{#{psH9x2BU)z5P3=YJ;0JnAQ-^)4pIXnnM)k8iRY z%CWT^yUH<1jw9qaRgMefxK@rkhXRB50KAnv!Ca(xKGrUtKSyKAkPq zO@Ap>ef_$7l6rCP)A3!qCMOOyGCVgvIlh07M0FwQC;Ywi)jt?07oo0&Q7S?G6kDSD zs(OaAx+ll?Q!iAjMdMQOsj11mx(-TJ7yIA+qaNlcndak2eU5q<@!B8tZu0&qp#E3C zoYkCvdpZ3){ilff&rkjL|Mqev)yw?r>&^JXpZa#vf9k6LxNN=kZ~8o^Ze#xNR81As zLq<Ng)#d5yrLUj*>ydVObJf%OoM`o*{_~)k#mK8)K>q0G>Hk*9 zk(Ud0TMW0nj6U#kTjgn<)mFV+7(*TP+oAt#RR3kXej_rxz531J?cJlER;C81gZIx+ zb$OK;>Zo6@{-ckW)%yeWa$Qu^f6ue3|McbQ%hj(Fqv}Z`i}F%PKOuj(JayOg+RM#Q z*Y7AVq>j8?#!uHOluC+HU#c%(F}k$=3YYo}Jvt`C|CTSWTBS-cmCA?dKV2N7>ouxx z{%o^(!4~yd8keifywToeGyiTDHFBzZtH_&An|dA|7&JSg&Xat#n?5RAb4-D(jj}a4 z{PcD+^WXQ2npV8T;2Cul~~i)qIi?Uh_#z zgns$3LKmNwT&4b-t^ONhZ>m~!^Gk*+Tg{Zh>i_v*>^CkyY;pRP>)O;Ic^XyvEOS`p zPn#`_X_R?wiz7QWZ{O|N$5VWKoyhVxepw@;>7y||m*WpVJsESQR|g;C!L)Hc4;reMpB}!&vo&^WL!Za{ zyXu#``1HbOn?0M|TVl89x59h2rJ8a7*#ur+?I&S<*6G){W1U<5ZP`n9c1dtLf9 z84F(*VGrTP{VxoIWhI2>$?cDLNojWFW ztY@ryoVSHVjCD7Cbaw!+d6Z|gdvxp=@AH~IvJcSLbEIdKdsOUbZ)+Rg{co2(?6pfD z5PdAEiX9}EUd(&xDV`K}YHX@pdXv9hdeUo`-Z!?Nr=PpO zw}nTvP?vr@?b3UBdb@ka_K{1!?Y;D#o?h-=vAyNeEBx)!yS;YlU1Pg?65I)L>6O)` z`=woaoF~rRCAN!PdJgZUtG_Evn%*B9sB~QF;OXG*7~3(;l77#%_q2C+i0vS+J$u?~ z-+Afy;vBXmA3J8%Xu0>Hv44`W^1M-T@a(6>t6u41%W^m7+gHVUBve|p(fP%XPrfSG zHEdgf%>yUq3YwJVw?9vJZo6P=j<56IJMnzX&FVirI3IsI>R@Et@@FN&49l2LCoZ$h z99!^KmlwUxSW8=s)yMi+iVV&7^-qZv*KM@_^?b&mu_5(FZ?N3_^V!-PKiY=wsadem zqT(A%TGa=xtS>*gK4N}IyV@IGmS~o*eW}2oa!+~IIyPmvZ}_qJ;MNuAe7(}LCb2}4 z|HAL)E$a17mb#%y?(%sTG#}-xlhc0YyRpmjl-f~n-o`^E4%gVwdEVM?JFnlYd7@K( z%Nt+J9#{S8_7QzHv_9-x`+3)TzwFpvEN@Wl-|p4&IpSaP=*^yoyR^(zH`j_ApSFJ< z*YS3>W!EglG8dRpIJ(!lbv-NWDLidK=KM`djVt!-YWt)<34ZmbY;d(5{pfh3cV+~g zSy*}Lh+&u8S!x71KI`;H>C0zwZyn#PcH?>d$6EMXSM;^pxNvM?PZ4(!ZwrekoZ)X> zK~Eufq1eK53s3Ui!V#W=?t-y}S|Euj$)u-Jaiz_Z}Acw9|n;BQ8CEaY)}L!`zn_SFLls93cEaL^?MujZLV+QtKa2c^Y%MWUhP~qaAK2t#os+Ksr{sp zSF_i)?Z1CvSBs#z?~fevOSxK~92%DNwk2urtKPdjAG$w`-R*ttZNoqO+uQY?_c`2C z?eOey?~L8)ZLWwN8Qy1Y!#Doz+|93@8yc}L!~0>aXPtXp?0R{?J=f=+SsQX`U3y+xe+I`7v z&m8xh*tfmUYx>B%FPY_;?VcSwM=rhB-!6UnYnMLNGu1sUcAB@jA`;wnGu%VB|J%7^ zUpqH6qK(@~d-*p#BitimN6PE<{O#N!ubr#zUp<4}gS{;*qM3TD((iwhJ<0Br*c9*c znm#h`e+PO7x|3s*<Q!b{Yc~WkC?94Uc0(4^>lQ1^tP~woEaT@+PT}szJICb z{d&V%mi_YT#m3>EW%kSB&wb+DPqUp`ban8`O*x*AZu?`wg4{Q*9Q59)^P@jpKl|nf zzYT0Q?2*22to!6xPOU8&;dS zblU!;q%G@qyybr;PT$Y%YSU`nyV;*qYQJ%nim}V z%k-bGbQw1!PT%hy8QA2TT&*S^OMYA_KHkso+{3Ze2DuL3nOY-T%>9#Bw!OJG-#ak} zZ++Xj!P^H*K2F}UMBj%-l^p1^`RJ;9ZOZTO@vyefw%YOc{3lf_lVeMk3pWyLCR%4z zZak^tBKP!;v)gZJb|UkhdYd!NTi@fWvSG`LwWxHs_pi2U$J&hzY*J%x=TnW&+`7N# zUi^R$0=Dj$**xayEAu|C=_B)AGOs7ETiy40Z&H9-H0!9P?hX@xv}9vv{()v&Lr2;HJPQHIHv=5Iyoj!Ee6bbkB%wHF;oU z?^oOx?kiW`y1$73JkPN3)E2+jDWY$`7mZh3oOg3g(SeIzZe4V4&=(i;eEi`%XP1uM zJ*m@x;VqAjZF)Z}SUv6wZ2Bli_BEchjnzl==r#IL-=#I`t+{kyb?lA!)eW!3>wE6D z;j28W)T3il>KS=#x7>TJkH}-YCF2jcey2JtH*AQK38Xdp5bxjRPWi`TThCe?3wJI;%#9O zlV7{noZy-0o)|mH`#kP7$9pEYC&W(lwzlEDJiXLgZ@z6@JM*z0*G}CRc}BWNd0##} zBFTHd$@LrN8SWk)`=(sJdA~W-Gc0zPd$_bqDa~X1boKOJRzV3yxrpqsYieHqh7lQY~^X?ZXMfN-cs`( zu%)M^yH#u}t+$K%ubCF4KiksB*S;KFVAlYiT_qx*Pl!2#|_(N)H*(D$BL?xI%MtL<%eRWxNj>n zZ1tVThc4e){&eo5g2&3w)Awz=E=}3Kf33Y;`GtpGrhM{K5B+x|OD$vG$c^Vext{CU z97p)*WjF2~%l_iW5ANC)#zt*D-!iMdZ#(OEs9#NcyCub!d=&Q4*Pr$o-8-p`>f>8uSREW-fXA4TJ7!q&Yr&WR&wvh z53ct-v?2Sm3q1-Zj~pD)x8m-(EwZOJ`!3toKRQj&_gS~Ad|c^eiRY(_J-o8!$d#_K zo@s?%jvRk){pU>@HX3rk(S4KWTJ?bKAI*%rJ+{o)&eI)6SQn#m6^ncgz}M1OeKH={ zRefgOH{)mS>JwidOQx^%_x&t>H`LcYe0*&2>Pr_sKK8RJ>UWso(>RCvK9c%zVcVPP zIo8MerJCmK;!XB=z5Hyc>Pvw>e)jI_vwdG*oBm+{A7A?&^&-|$>IJMNGuP5jUs12x z8l9z;dfGNipKr+&sxC52V<{jbLqk>3cGU(Fc9x2Vi~YL+&9i^6EW>>S4`n}0Av#A-Q zu2zifta_{KRa$lyz10;fBRjL+>YA069jdpwYUN~y=&i0>dD$+#)s?Ft+o`v@b`@m@ z>#eR{CD}oGtLs-;cA(m&)%B|)J3w!B{i@1#=&i0_HQD}ptLs-?wx8bW`qhwa*IQk` znzA$Lt*&1!**3k^^{Xx0S8sLw>d02#*RNe#UB9}rebg?au3tUb7QNN=t1nwI@bmR8 zX#G;%{{E-6pF-Z>Y30A(uAXjS*I&ERLOeG8OFz6q8p)|5q_Ip9(nO{RX)05MG?OVp zn#&X+Eo6$2mNG?1E14pswM>M(AsZoWWFw@lY=pFvjga=T5z;|6LORMuNGI6{=`0%| zak3H8MK(g>Wh11kY=k7pMo2f=2uYNUknXY((nB^vddfyfFWCs`EgKKe`}D!;Xg@z!0}Bo zh2+%tCv)stjutZCrhi$GSI7c6RfH^*DMA*>6d{XcijXBTMaWW_B4n9N5wcvS2w5Rh zgshZ_kX5n~vRXDm*2qT4TGU5wck}Lbk|8$X3}1*(Mty z@5n~TcG(DdS2jX+$VSLc*$8=0HbUN)jgSvyBV?CsQ^;Ivl)C->FRHr<-+87GkG?K`9w|?A$w(tkbN>m$fq(z$bOk3AsZn_Wh3NE*$6o%8zEoGM#yp52st4eAz#Zz$TzYPa#A)zzLkxT?_?w7 zd)Wv%B^x29Wh3N_Y=oSZjgWJ)5%PmLT;5QzI5%`UV1ql4c!*Bw> z@i2nGZ#*nWP(XrweSIv}j};KdZS~02*J?2pwa|}d3t8-%msV8FV$;9E(5t98=Zm5e zY*AE_Es7%9qNo&G6h*N`Q8Zf=#jr(DX|^aT!$whA0*cBJP*k3Pq6!2QRV1LO5&=b( z2`H*UKv7i!imDM%RGomL8Uz&8B%r7k0Y$Y5D5^t1QC$Lx>Jd;>pMatU1QazSpeUAL zDk@^pKhthF9%?v6MUh>9v~pYQ+Lu<;#A4IG0@JIgDd&r#W^7T^oGpr4utiZzwkT@F z7DcVuqUa5_C~CtNMQzzAYDYj(djg6&5Kz>SfTB(W6m=$`D2{-lE(8?C6HwHZfT9Ef zinUfTCUm6!j*cs1E@}eF-S)M?g`3f~lyH#adqhahz1sx3MUi zuSq4T|GR+lr4^-EZ2DKIdKIN|z9<^R7Da>EqG$+P6b)sIqG4=NG@LDp-eilS5o}R3 zl8vHK1Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTBqR6ip_eXbJ&EQwb=VMnKVY0*Yo3 zP&AW(qPGYrnngg-Yyyhr5K#0s0Y!5OrlNrs>kI|Nv0r_r?VBu$UU@&yve>mRt!R)RT{*fTEoQ6un14(fb4xeLz6b zE&_@^B%o+F0Y!TVrlJKF>vsx>W4V4ny-*Y#(uzK^*tIXMXrINVe}%JG(Wjg*iuSWb z(E+w7I>;79huEU%Gqxx?%oatTvqjMnwkZ07jiRFj6n#lR(J=ywz9OLLH~~c`2q^lR zfTC{*C^|_%(YFK?eMdmi_XHH3BB1Cr0YzsBC^}0((K!N&ejuReJOM>N5>Rx3fTEuW zrlLbsv`L{SBO$7J=fYhPNC-N&YXg}hghALolAf3_%cutiY-TNDMdMNtr26a}+I zk&`WoTx?Mk!bVXj0Y#Y!D9S=WQC0$qvJp^}oq(bo1Qg{YpePpsMY#zm%0oa=UIL2p z5m1z$fTA!0iV6@=6iz@<1OY__2`DN=;J&CZ0Yya!rXrhQl$fTGF-6jdRhs44+P)d(o6PC!u&0*Y!9P*jV6qS^!$)ghp$E&)aL2q>yg zKv4q%iW(A76iYynn}8w@0Y!}nrlR6L*54Em$4vc2#}cBbivHqJV;{Trr4=>zvFU%p z!mFqS=Zm72Y*EyTEs9#RMbR5vT@#SnTlu+Yw@@@Oe|kH; zT{Zj4iq39V$v*<6P0=~dhoYW#C_2{;Md#U}=zKdA^|C|J1$HR9&<;fx*`erSo1)$V zMVAN^^${q#RG{cGfuhR=imnhS>MKyxPoSv3K+%-~MOO(FT`f>_jX=@00!0G^imnqV z8YoaSNT6u2K+zC^qU(i1(V6YaXD1-FTkmpjqT6hW#tIbOE>LubK+&B7MRy4l-7Qcw zPN3)>fuef_ipC2R-6v3Vzd+Fg0!0rB6g?zRG(n)~VS%DY1d1jK6g?_X^q4@=<3ge6 zhIZvA5|G-Ix&-IOP;_s8E_$L}HT%knCbg^NAHmf2Tr}DFQ1px)ik`JY(Q|evdfpC2 zFW8~zMLQHtu|v^Ib|{)^Q}nVx(KLagR|JY)6)1X5py+jhqBjJJ-V`W$OQ7g&fueT= ziry6{dQYI}eSxA61d2WsDEdgCXu3er#{xy42o!xPP&7j*6g}0h+-}vRXyf#kkL#Zf zMGxlh|M{$4HT%knzHC>?KfgzO_TqcXlZH-VQ}S*rDi0I~4t7 zhoV_FML!D^{UT8Gt3c6j0!6> z(HhFt>?>l1&THk zDB4`0XbXX&Ed`3U5-92}P_(r`(KZ4_+X@u@PoQW!fuijNigpkv+EJirCxN1!1&VeN zDB4vh6s=w^zny^8-pgMKtr3cr$j?Q)m8;oTR0!1eX6rCtgbdo^P$pS^E2o#+vP}D=9=rn<%(*=so5GXoRC=~5cE-$ifQnY{m zQfSXmlz%W|{aNK|_LUW#Tdw3EVcMqXJm*8v`F1GkWrv~*>`-)}9f~fpL(#={DC%v8 zqD$;h)W@diQh}n&1d1*fD7r$RsINd#KY^nD0!3E}6kR1ybhSXyH3CJ~3KR_xD7sFd zXrMsRAc3O60!2dvimn$Z8Y)mUOrYonp-^;AxqMgxQX8A$^bAFJW>PnntJzmpG@@L| zKLWQ+(Jju0qLFqe8fAx~TkTLZ+73ly>`-)@9g4=?dS3lxnL zD7r_W=w5-M@d8En2^8HgQ1pO6(Srg-4+#`a5GZx z6DWFLpy&gEq7Ma%J`yOJE>QHbK+z`xMV|^3%@8R1OrYpY6e#*jpy+RbqB#OZ{|FS#6)5^wplF^z(SHI(rTTc; zPEnmeQ9FU6vOrP2Kv6}Ys6n8pDp1s3C=`8FF0Y+{)Q-wuP=6hY9?UQMJJeURudJw3 zeI@@0_cleHoexD#b|`ALLs5$zin`dLXg)g>&2NXIRy!0eV27dwZHg8WC|X#cXc2*; zMFol$6DV3-plAt!q9p~2mJ%phTA*kdfudyvik1^7T3(=N1%aX!1&US@C|X&dXcd8? zRRxMx6DV3;C=_+9FZWD9YWL;mqQ?5-mHx8%Guj&U)$A)PTD!h-!FO$CZJ6DZnTplAz$qAdlAwh}1nE>N_! zK+!e=McWD#{ZF81JAtC@1&VeMDB4k=XeWW9odt?^5h&VKplCONqTL0G_7Dn1UF*wF zB_Oq1(yU)A6y<+>zkbj9YW9^C?OR{@w0kJp&-qZaza5GWutU*-b|^Z?4n+ssq394h z6dh`ZqQmS^bhu5?5duX=3KShBP;|6F(J=x=#|ji3Cs1^}K+y>TMJEarog`3nvOv)( z0!60^6!j1&I!&PHbb+EX1d7fSC^}1^=xl+abA&?C-u31Bt&^fn>l2)PLeau)FWBm< z*;iK7tG=@QwxQ?(=R?tjb||{Y4n-H+p{TbViY~E3Q6D=LU22D-%j{5exlPd(0!4iV ziuwr@^%p3*QlRK6fugGgimnkTx>lfQfI!i80!0G_iUtW34HhUGB2aX_K+#ZvqG19> zHwYBnC{T2hK+$laP;_2>d4~j~)+2v=u;{FW?xy+sQSu@+l8WAoexE$ z?NBtv4n?=wp=hifif*?<(H(Xuy3-CtciExnZkwWU0!8--6x}OOG+vljS61{wedYcgLeY!PhoUKVD0;~bMN{oi^s*g_rrDwB z6+0BYYKNlN>`?T&P0kFtf;wC*>u-X)Z%<7 z>SBkY`Rq_Mza5HN?NGFU9f}sTL(xKZC|cMKMT^)JEhG6s;*x)Kw@H zb*_|;NI+`m=kL32suZvEZ_7_iYgMY*S5~xMrP62jP_(}Dp=bj;6m_#h(S~*?+Q<$? z8{4616FU@bYKNlD>`=71P0kP(2o#+u zP;{0+(b)n;=Li(_6ev1Zpy)iIP_$pA{8Iu_n=gMUw0|gS%CGd#uT-l~ zbg}cHsJ9)8F0n&VA3GFXYKNlB>`-*M9g427Ls4Hl6!o(y>Mu}qr9jbD0!3E~6kQ`w zbge+q0D+?G1d0X<6b%w68Z1yWM4;$;fuf-TMZ*M&ZV)KCQK0B1fui98MK=o+jSwih zMJN*rDi6I~2WT zQ}nh#(K`Y~?+O&XCs6dhK+y*RMIQ)tK{dRDWT}5OzOKzHT%kneyUVHJ17** zay}IOY=@#>>`?Tp9g2RlL(%VcD4K1DqCf0V^rsz){<10hTcBu;K+!(}MRNs;{uL;i zCs6dCKvAh7Uba(ICs5Q*pr|ZRR4-6e5h!X9D5?q+wHGMrAW&2jDC#Is)F@EYNua2+ zP$>GLQf@dnDawEDTK{7x+Bbix-PBOczOthE8Y(Lu8j9w3J`}aup=bd+6fJ0nqJ`{G zw6GnD7O_LoqIM`+%nn71+Y~J!P_(2#(NY3MOA8b&BT%%gK+$pnMav5mtsqdeqCn9~ z0!1qe6s;mqw5mYSY63;83lyy(P_(8%QCESYwFHXR7ARUrC=|6cly^!%YK!KtuDdi8 zuk`!mm;LKDRI{(Fs9Qtj>Wp=b*`6m4mT zqOEL-x(gI-El{+LK+(1WMgJ2h+D@Qodx4@I1d4VPDB4M&XlH?9pZc_I@AtDhuNX%a61$oVTYn4?ND@-9g2>&L(wsIC_2`r=s1C*;{}RN5GXoP zpy(ulqLT%RP7x?NRiLPcK+$OeMW+iCogq+kra;kI0!3#F6rCeb)Kj47T!EtV1d7fV zDC#9pbb(MPIIEFU22D-%j{5e zxgCnGutQN_I~4V^Ls5S_6kTbDqN{9*t`;b|Mxf|gfuaEdMb`-w4HPIEBv3S1plFCd z(e(mFLj{V42^8HRP;{d}(M`}6DTSR z6x9n9RRoF}1d6HxMePNOItUci1d2Ke6g3JIbrLA*EKt-WP}D3?)FKp$W;K+5PC#lK z=jWoIL($h+QI~2p`^t(Is8(7|4Mht&ABq;TL(#%^C|bl0MT^>@XfZn!EpCURCG1eN zq#cTuvME|xplBI^qGbh&mJ=viUZ7|Nfua=!idGURT3MiI6@j8v1&US^C|X^hXbpj) zH3f>g3KXp+P_(u{(K-S}>k1UDCs4G$P$-(eT3$Z^sg0^7IIY#a1gy+YA!=R?sSb}0JO4n=?2q3CZr6wR?i(LZ)5nrnxm zf9+5-&!*@MWCobpr|TP)Lx*dgFsPDps1rjQKLXn zCxN2Q0!2*%Ma=?5EdoVd1d8SpD4Jg=6#ZH)f0%&Oe#o!%e+xx>W>T%~tJzmpv~c^% zKNp6gMVt>si`t=RF*_73Zik{J>`=6%9g3E+L($T9C|br2Ma$Y0EhkX4yg<Y}8mn!ibQq4vcq{eJl~+D7fG*;iJyS^LVCy+hIF&WEBc>`=6& z9g4QHLs54-6m4yXqHXL@w5=VA{%41x?QDv+7bx06plC;dqMZbab`~hwMWAR`fuh|6 zigp($+C!jdPl2Mn1d8?+DB4G$XkUS%{RE2k7brSFpy)t>qJspA4i+dnL?{$((!P95 z0#X~F;cOa;p3l!khqkX~Us=(S?JHOG2}MUaABv8)L(wsIC_2^-MaS8p=y*F6onVKe z6YWrRk{yapwkbMApy*VAq8LuaK+%~3MP~^Voh?vwjzCdQfueH-ip~=# zI$xlumq5`40!0@J6kQ}xbg@8DZ-Jsq1d93yg`&gTm&YX_wPW-57ab9bF3O}XZC}m4 zvZB82E3aG@iuySpiu&83=t?^jU1f)&tL;#9jU9@vwL{SWI}}}KhoXTtMS}#21`8Ao z5h%J|plGN-(J+Cc8w84O6ezk$plG;2(ai!yBLs?W5hxldP&7)Q=vINE(E>$d1d47G zC>kqJbh|*&9YUe#^7iFl6Oh_hbqUTDq3DuK>dyAn>?(L;79nqY^bhwV`Gh)vN%fuctRiXIavdR(CB34x*~1&W>$D0*6; zXp%tDWPze*1d5&&D0)ty=y`#n7X*r46eyY^Q1p^O(Nuw=mj#NZ2^75|6pHR{U+$KG z)OJa;eq1QpK7U4gwS6`F%8K4>U)jHZD0<8JQ1rGPir%q9(Ytmide06;@7tm113MIb zXosSY>`*k_rs!jVqE7^hJ{2gMAyD+0K+)#{MKcA8z7Qz-QlRK7fugSkioOvj`c|Om zJAtC_1&V$UDEd*L=qG`qSpr2r3l#k#Q1q)%D0;np`N9Mw{V7_4^F}B-D1WojZ|$qu zS61|A`^qg>g`&Tl4@H05p=gdBivF=f(Of$e{cDG!d3GrJ&kjYU4)MA@6xG=jwG${R z3l!B06jcO@8U%`}0!8fwiaH1s)dY$<3KTU86m=3P>MT&yBv8~WP}Cw&)J33ZK7pe7 z1&Ue)iWU$kT2Lqy&2C?QE&-`Mke`132t}Lcu~3I<_LUVa)}iv{HKAy6=R?sFb|_lX z4n<4Zp=fD46fI+iqGjz+w45D^mbXLE3N}S63KXp*P_(i@(JBH(s|pmYCQ!7xK+zfk zMQaKabrmRDOQ2|NfueN;iq;hC=+V+C2LpA%#ini=fS@pV5w3YLrsJk7CwzfmjHg+i5)(%DgvqRB# zb|~834n;fIp=d{&qMZbab`~hwMWAR`fuh|6igp($+C!jdPl2Mn1d8?+DB4G$XkUS% z{RE2k7brSFpy)t>qJspA4i+dnM4;$Ufuh3%iVhbFMVogh@0Nhn2IQxoEkaSxwij$2 zs@YdobWDfJX@f%1vCfC08utU*_b|^Z@4n-&1q39Gl6rE~^q8>IyrwJ6D zE>LuaK+%~3MP~^Voh?vwjzCdQfueH-ip~=#I$xlumq5`40!0@J6kQ}xbg@8DZ-Jsq z1d93y6kRG%beTZW_IfE|jivqRB9I}{DFL(yP66b-Q{x?Z4Ys6f#$fub7(if$Arx=EmD zxIod(0!1SPif$1o8YxgTN}%Xgfuhj@MPmetZWAaPD^PU1K+zonMRy7m-6c?Tw@@hR z*P%Q;0jX`1W_|xqbWwiUKdwVH`^t*$>rnZ3Xeheh`B3zL9f}^bL(xNaD4Jl0qKEBJ z^oSjbCfcFsQ9BepW>fUIK+zKdMNbM8Jta`|v_R1$fuhL*Mb8KnJu6W3oIug@0!1$f z6ul@=G)183C4r);0!1$i6ipK-dPShEx25A0C%p&g1ovP02yI~09vhoVpHQ1q!y(F}p2 z&jgA-7bu!3Q1pdB(U$^6UkMa_El~80K+(4XMc)Y&eJ@b-gFw-b0!2Rw6wMMS`dOgp z7lEQ*1&V$XDEeKXXtq!&daFbExCEs3L;fzcw?olJ`QHrrqeC_O%8KT6sPr2iivDpv z6wS3m(Z6;mnrDZi|Ljnd{z=K=hrorRIy)4#vqMqY4n_4gMHPXf27#igKv8>vq7DK@ zHG!gz0!57iMV$nSItvsv2^2L86txHxbrC3ntGqTM6fNa^C|cSMMa$TsXjwZHEoX%U7%93i`7PV^jl@)DWtF(>^McX(Zing^w(f{mFw4EJ_wzosk4t6No(GEpB*`a7>I~46= zQ?#o<(QX1oy9*TUAyBlZK+#?TMSBYr?ITdMuRzg$0!8}^6dfQ?bf7@dK>|ew3ltq9 zP;{t3(P08bhYJ)PAy9OrK+#b`p=hgGd7}iRmj9)q`tG6V`8MKyx zPbd@}TPt6jfYesVPd~?nqBHYnwEnef_LUV~Q>%=+Efihrd?*@VhobB3P&CjEMT6{6 zG}sPBL+ns=y&Z~%+M#HeP0zRw+R%D6)3u0py&>PqB{kO?h+`vTcBv1K+!z{MfVDYqN{4<7ZQ-#?fEwvuMS0< z_??{T)&Oborfl#!3{=VzCYt`&4D|)|HS^ch1 z^nvrC=tDacePoBC>2@gk*bYUX*rDiCI~2{ZL(yk;DEi!{Xr@5X7Xn3J3KV@MQ1rDx z(KiA`-wG6cCs6dgK+z8ZML!A@{UlH{OQ7gyfudgoihdO+`c0tdcY&hW0!4oa6#Xes z^p{X5dbd{IBLS&R%%8;G3q@1%Zyx(INsxiwYDiCQ!7vP$>GRRvwms)H>$pqPd~y zf%I$jOLVMeUs=&I9V?IC8;X{7J`^oyhoa@}P_%*_idM8k(MonGTGd7fK+zfkMQaKabrmRDOQ2|NfueN;iq;hl^AiVn%&46L(yq=C_3E^MQ7Nd=uA5lon?ojvu%pb5h&^@P;{<9(Rl(z=L;0|5-7Srpy)z@ zqKgEIE*2>2El_lcKv5roqDuveE)yuaT%hO*fugFSQv>?ID7smoXoNt~EdoU&1&T%q6x}LNG+Ll&j6l(C0!3p5if$JuxkeFbdNyMy#ht!1&ZzyD7s%L6kXe~d|v`mTO&Ug4G2X~=C7_F=vd9Z zvZ9AOR^E6d6g}d6D4J-8qDSpe^q3ur9=Ai$6Lu(i(hfyW*`erZI}}Z_DVi)$^o&5! zvjRoW2^2jqQ1pU8(Tf5_Qv`}$5-6G~Q1r4u(KLagR|JY)6)1X5py+jhqBjJJ-V`W$ zOQ7g&fueT=iry6pMGti>|B-;yuFh~Kgre?kFW5R(v#+e^qmGpY9}7j(oexDH+o9+a zI~09thoTvFDEiC}MW5TDXr>*CzOX~lmo`OT2^4)TQ1p#J(YFFc-w70bFHrP@K+%r^ zML!7?%@Qd3S)k|_fudgpihdI)`dy%Cwm{Jz0!4oc6#XSo^tV9K9D$;LghJ5=9m|^} zAhqrDZxMYMiXO(INsxiwYDiCQ!7vK+zHcMN0}4EhQ9+=5;Jzl7Q6K$lo#hUnp8T{aXFfjn(Wc zD_Xv>GWw}dw1V@YXhk~|tz?IymF-ZpiXDnpwL{Trb|_li4n=F&p=eE;qOJl(YY7ys zEl{+MK+(DaMe7L^tuIitfk06=fuaosiZ&7`+E}1y6M>>l1&THkDB4`0XbXX&Ed`3U z5-92}P_(r`(KbS%XxYZ{lmw)`t@R|ew3ltq9P;{t3(P08bhYJ)PAy9OrK+#bGMMn!19V1Y5tU%Fm0!7CQ6rCUxinePk zcb=RSEuH`9Z2M3&IQ?4viH+6lD=Rv+v9ji~p{R%Rq3AR_6rFB|qBHDJbfz7O&ay+% z*>)&8#|}k3?ND^CP0@J*Mdu3?^%5w$K%nSCfuf59iY^u?>Mc-oi9k^wfuc(ViY^l< zx?G^>3W1`&0!94l|a$e0!7yd6kRJ6icW4U@0EbmX6D~@JS7y(&SOAh zHT%kn1~*pDdOj2laXu7XZ-=6xb|@NVhoT$oP;{dmif*z)(QrEy-E4=V5jI7)2o#MJ zC>kYDbgMwoXn~?J0!6n86pa-qx?P~?4uPUO1&ZzxD7ssqXq-UNJpx7d3KWeOD7sIe z=zf8s2Ly^96exN~C=?BBEZ>-b)E>#N^aq8ao!VZoHCD5)tmx6k%HuDFqQ{&MMUUH| z=m|R%J!yxcr|eMlv>l2j*`a8%9g3c@L(#J~Mb8NoJugu7f#IeJfD(oj}p|0!2Rv6#Xbr^pil*EP}P@rfbfue;4iWU(lT2!EDF@d7R1&WpsC|XjW zXeoiBr3H$X5hz+#C=}IoDxZ{q)E3Ww0Nbup@fvNu^lSCYb*g4xSkAZZAW+mz zplCyZqKyQKHWnz_M4)I>fuhX>iZ&N0+CrdcOM#-T1d6%~6m2a~w2eT~wgN@}6DZnF zC={*Gsr*0!Qd>F0SuqstoIky7->I5?Wkox8s=W1jDB8vOP_(NZigvR@(e8FA+QSY- zd)lFBFFO?NZHJ`=6?P0@Y=Mf(dB9UxG2pg_?<0!0T46dfW^bf`elVFE>m3ltq8 zP;{g~(NO|LM++1kBT#g#K+$mmMaK&iogh$jqCn9}0!1eag`yohmH$dWYQN`CVmpPR z_cN(eI#si;tmyPkm4)95MQ1o4iq5n{(OGsVI@=CK=h&gBryYvUwL{T)b|^aE4n@6e ziY^c+x=^6#B7vfd1&VqL6kQ@v)JLG`Qh}n&1d1*fD7r$RsINd#KY^nD0!3E}6kR1y zbhSXyH3CJ~3KR_xD7sFdXrNFi>d~pZSprf!HGkjrX%yw>qCuUi*;iIHv{U8KcS6xH z=R?sAb||{h4n;TFp=h`rif*<;(Fi*f-C~ELk#;B=Wm9ykK+$M{qA>zRw+R%D6)3u0 zpy&>PqB{kO?h+`vTcBv1K+!z{MfVC6jTb1oPoU_2fuaWliXIdwdPtyXf^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+$xeQ1n=*^3(*R)<6F-{^OzO zn8q|d?o`dbvZBvARlffq6n*Y|D4J=9qA%=F^ran&zOqBn*LEoS#tuc_+M(z>I~09y zQ}lyC(T@T}KM54g5-9pvpy(HYqF)7yeiJDAU7%>TK+zupMSltu{UuQJw?NSxfuer| zislLw{VPy3PoU^Ofud69cwtUaolq$Hv{SkH!=&h^{3jqYLebj!Gg`aO)$A)PYUo^9 zYkDZEIv`rsEa_+d;&%D3ly~q z6fGc7w4gxILIOn#3luFPP_(E((P9EciwhJjAyBlWK+#eHMN115EhA90tU%Fn0!7OU z6s;f>it0O;_enr%zvMsDuXK*@yH3AWzhdWV_LUW_+PQMhC!uIH=R?uzb|_lI4n=F) zp{T1Jiq^72(b{$>TE`AW>)N4cJ)5HS1&THhDC#Cqw4p%JMgm0}3lwc4P_(H)(Pjcg zn+p_eAyBlXK+#qLMcoC8wiYPbMxbb0fujEj6m2I^w7o#l4gy6x3WcJTJC}ziAhqT5 zpMb0qidM|eMLTt_W?xy+Zk;Pn&Im=jJ0FVnutU+Fb|~7*4n=$0p=cjF6zyw=qW$bp zw7(sS4zMXYP@w1_fue&2iVhJdI#i(OFoB}O1&WRkC^}N0=qQ1rqXmkN5hyxVpy)V( zqT>aMP7o+MQK0A~fufTIicS$II#r;khfpZmrE~f71f+IN{=Vy7L(!y6>a@<)>?Sc$b3+zyIp&g1YvMIV)ps2S%(Io;! zeFTaw6)3t)py+aeqALW7`U({F6DaC0P;{k0(NzLPR|^zfBT#g$K+yn!qU!{T1_~4n z5-1uhP&7m+6rItzyix*Eo0b0rplG~6(R~6%_X`v~AW-z6K+!`2MH2*y9u_EiM4)J*K+&TDMUM%EqG6rOrz9Y? zkMfKA8$!|Yc|6{^ntf$OPj{|d`*kRq`?Tq9g3c_L(%hgD0;yTMK9W+ zXo?+*Ua~2gDp2&YK+!aTqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz z=zW2r4+M%n6e#*gplG^4(Z>Qsp9mCvDin&I>|A~*0jV9Fzq)=Z6fK*_jLy~UD=Ye< zbLE|HL(!MchoZ0SQ1rDOioUT!(YJOe`pynT-`k<+2Rjt~XosSoY>H+H6#Xnv^ou~z zuL4EC2^9S0jwo_Cm zP}EMKs4P%aFBFPC?_8dffYj#Y-*ucBiXO{~DoxewD=X^IR9W>`>HfhoTlc6m_vf(R?;V^9vNU3KT6MP_&>x(Lw@63kwu2B2cubK+$3X zMT-j*Eg?{}q(IS90!2#;6fGlAw5&kUasoxm3lyy&P_&{z(MkeED+`69YEyZO1f(`6 z{|QL@rs9?U`g+S4k0!3R16m=IU+FGD!8-b#2 z1&aPBP_&&u(e?sGI|vl*C{VPMK+(wWM2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMLh(H zP7^3PU7+X;p-{AYQ+ZkfQX83n?|P3=w10jsI$Xq2^3u|P;`wz(X|3a0|bh$6DS%eP&7!OXs|%h5P_oW1&W3W6b%y!MQ1mayZn|E ztzAiQ&Iv__<(K_8G*z>&tmx*Z$~v<{(Fo^5(Jgi;8fk~3QFbW0)ec3Y?NBtv4n?=w zp=hifif*?lxkeFbdNyMy#ht!1&ZzyD7s&u=mCME2L*~A5-6G= zQ1q}s(IWyy69tMM6)1X4py+Xdq9+83o)ij2H#L>_OF(KL<=2eJ&J=CN-5uBp|gb^2@Txp=eruE}Gd?&AzgtubV1Q{~e0HaXu7%Yloum z>`?T*9g2RiL(z|RDEi3`MYHTs^s^m`ez7U~RiNlMfui39ie?KG{UK2Fr$EtP0!4od z6wMJR`bVH>u0YYh0!8x#ivANQDmBN;c8cl*irNVjl?96G1&S&HMGXQ)RiRMyWmEZ! z1f(`Ee@6Q%6upt3i`q9=v#+eEvAI&28;UwPABsBLp{U6YMa_07YOzC67dsTqXNRKs z?NHQehoS{+iWU?oT1cR1VS%DW1d0|FC|XRQXmNp}B?O9=6ewCsplE40!1eX6rCtgbdo^P$pS^E2o#+vP}D=9=rn<%(*=so5GXoRpy(`tqO*lU z(O%8vhZB%mhx|updxxTJ@+ z>ja7h3KR_zC>ktKG(@22dV!*$0!70Fif#}nx>2C$CZSMtZgY8V0#bV>|3>3^p=gKv zTr|A7ntf$OBbzIWS3=P!=R?u0b|@NchoUidD7wuKMPuzybh{mj?yy7Aopva?%ckgV zfueB&MfV64-78QuUZChcfuj2biXIRsdQhO~A%UU^0!0rC6g?tPG*O`FQGuez1d1LP zD0)Jm=t+U1rv!?g7ATq|6pBVPm$ynlYP;p9pIbsvbAH)Bxw)EsWkt_7SB|WPq8FSG zMK9W+Xo?+*Ua~{cR67*CY=@$0b|`wq4n?opq3AW6qSpnA-Vi8yQ=sTAfugqsirx_@ zdRL(6J%OV41&TfpDEd&K=p%um=>kO`3lx1KQ1q!l(F}p2&jgA-7bu!3Q1pdB(U(G@ z=-K9S-vp#~RemmdE);!~zqRePu;WEtOdvLs7Hyp{T_UMP2MrG@l)c=C?yps~w6KutU*;b|_lN4n+&w6fGi9 zw5UMQVgf~r3luFOP_(2#(NY3MOA8b&BT%%gK+$pnMav5mtsqdeqCn9~0!1qe6s;mq zw5mYSY63;83lyy(P_(8{DC*Qwp1(0ES|Wd|b?27imHzAbxu|PPHT%kn)@`Y**Etle z=X@wy-ws6^*rBMK9f~%zL(xWdDB9Q#MVr{6Xj3~BZDv!nxj@kt0!3R26m2C?)Lo!x zYk{I|1d6s5DEgm3(RKnw+Y1!!AW*cUK+#SDMLP==?IKXLt3c6i0!6zE6zw5Uw5LGP zUP7U0?UwQZ2}teO{H4%3q3FH*vVZTEYW9^C?cY*4zc~~g;Cv`L&<;fh*`erQI}{ya zhoVF6P;{6biVn9!(GhkiI?|@-D1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%R zP7x?NRiLPcK+$OeMW+iCogq+kra;kI0!3#F6rCeb)Kj47T%l03Z%cV(0#Zx=kZh@b zzfiPG{)~2BOEvq-iY{!aOzskjE^`-*69f~fqL(%1SD7wN9 zMSX3G`Uw>E7bvF0t_w0VA|e@ja>`^t(&w^XXF zp=gZrq3AX{6pgh*(d~99y2B1dciN%oE;|(6ZHJ<9b||{Xrs!UQqVWPn_X!l;FHrP= zK+%H&MGpxSO%N!0SfJ<;fue~5MUM&;Jtk1}xIobp0!2>>6g?$S^t3?HB!QyI0!7aV z6g?{xibl1RS4%)@Bl7P$-WrO!=jWp5TB_MsRy3uhvh#wW=q2Yv(NsGWy=;e~X?7@j z#STTU+M(z*I~2WchoU#^Q1qrv(OUvVZwnN?BT)3NK+$^wMehp~eIQWup+M0`0!7mW ziar)7`b41UQ-Pux0!5z*6n!pGG*h7H3xT391&Y2BDEeBU=o_I>^g>Jd^aP}~NB+x0 zFNUH85}x{RTdLVtR`g>_WzfQ*=qKkx(JVU@{cMM#U+hrys~w7dvqRDEb|{){hoV31 zQ1quw(O&{Ze+v}N5h(gcplGf@(Z2#k^8||i6DTTmiI?pZ)d>`}6DTSR6x9n9RRoF} z1d6HxMePNOItUci1d2Ke6g3JIbrK3i-?x+}CLpy-^K;P;p=etE^wzmcHT%knx^$_0 zuxKcn&-qX^za5HN?NGFU9f}sTL(xKZC|cMKMT^*>Xi+;9EoM`+xIobo0!2#-6fGrC zw6s9cG6F@*3KT6TP_(>2(Fy`ZD+&~?Bv7=nK+!4!MXL%FttL>kxI6m=CS zT1%j4ZJ|)q+@(A(0jZVp?>e@0DPHM6nV*Z+=~B(UvZ4*TRF+&K6m@ex6m4jSqK)iO zw6PtEHnBs|rgkXW%nn7H+o5O+I}~kcQ?!*pQFno&tp$p<5h&VLpy+=BMcWA!Z7)!? zgFw-a0!2Fs6zwcfw2MH|t^!572^8%vP_&0Y(VhZDdkGZnEl{+NK+(QJp=iA><*gHt zTKD{1w0oS%#K>r&0WvZ8~!RE}OM6dmk*C_2OrMTgp<=rB7J9d3uBBkWLgq#cTm zvP03)b|^Z=rs!CKqT>XLju$98L7?bFfufTHicS_NIz^!9RDq%%0!60@6rCp!oDW5P>`-*69f~fqL(%1SD7wN9MSbm1)Xxq@{q0b6rA^UQ0!3E~6kQ`w zbge+q0D+?G1d0X<6b%w68Z1yWM4;$;fuf-TMZ*M&ZV)KCQK0B1fui98MK=o+jSwih zMWAS;K+!0nP;^n3^6LpmE&sV|{l%du{b@&f!PcdkeU&(?Ke8<~ zy_A1zspV}c)N#2|X_KbiS16UXXd1dw zskC*|$E%b|+chn_da1Ni)A4JTO1m|UU#nEwt7-N+rP6*)8?Rp~9n{pjTd8zd(~BFG zN=G$y+O$+Uu4&KBOQn;VZrHL^>e2LR_fqN1rscOSm3lUvxLv8#tLgq7N~MdN{@kfl zy0mH2T}!3DO?`GRm9A=fY0pw=KvUB`rPAQ0z4t4XhBe)EK&dpm>9d1MrIAf59$G4m zX*&7vQt6JS2ahb3#x?zYbg6V-)8@yON)I(%c0#E%vFYWLN~I^7T23vMCN=GQTB-D0 z)6Hj;N>iFeMMYg)Nysq}i&sppkSZ#PZoRVuyT^v{K*()6Y+dzVTxny%FhK*PQ=t{e$Y7^FNM$SY31e*R7AL zYtH{X@o{y{`QMj4sjfNy1ED?Yn)AQ#cxGL5{wMl+)-~sUW35+RbN)xNF0O0N|H{#& zb!t~tN{{GqNnzkv9;t~q}N_=*XBH5l2@u*KSs~|D;pGJ{@2QBbnDzF{Ri#yf13U` zU%4^04dcK5D_yv5qZkXO|E6x^7)#`_NsRt=X>1x}gM87=Vl10JsOvV5aZI{?-4?}Y zO&?LE{JyrXSXWx0ZnuV(d7}ou)^mZn-7AgfEVk2z3)Jn=(DM10FW+^+0(E;<8t;1N z`4dVD?vT#Blh2Hd!+R8mD~+Y6FHcw5y`kmlvA+ztsO|8Lv+w#VT`wJ;cEduIQfqQl z`aB)J+#4J`{l$Li>gf$`GV`!X+nH%E4VqKD!LtYawMwb=k9a$eIrHKpAAQ=Z?aYQF z(_i_?@8n;PU-wK(>Fvy0`Pd^%t+jM#e?)^6!ce&3c}sqN0FG=BWchljVF`RC$qH)}id>eElmD&EX~*Y{hf)Vfa` z+1ZgpZ=SPi+mRpEoV!#w@+nrO~moxsl{lRo^q}zCPpMf7-n6H+egIWis|GLA*b*1s~U$>uDY8@AE;RSDD z)YKExTX@J@m=tfJymH*YtDZ@JCXnv?mfNqLduZF+`1s||MxEDor`-PY-#_;%wZ0l} zXTjo3yY_uct>47kS;KXEomAjy%Dy4_oE-)zaH(X!-WH?{7($-=oqv zaf{`4N^hsq`1MDXo~72t^!aFkbaO5$j+ATD(>=0KiunO~z;$+8;(#^U?%l1%{+sUR zbeUd5TJ~>ycZbZGHQ~Zi>r&~+vgtZ6y3S(lO0BEKb^dXk!#nTYt?m7p)3@&%>G4b# znzQ%zXS7}Ds>fzcO7GCN=}dmKx~vlS)pf7ll5XQJDYrdZ2gEgZ@#|Z6IdzA&_wClB zS3R}ulEaR_CrL}b`rSKq?75}Z6Vj1<8;>lGlxs(&_wDSs&d?$@wA}pY#NOw(y>nNL zd-<9KG`({dHg#XP?ao?%@#}XlwO*Lc2jZo82a5+UpE_6W=8(Ll%bl>E3Dt*|0 zH*3pwZ8vh|#XD`)c6UAh%(Ju8hvW2gCf~||F7$r7&^K|R=UwQZr+@i8eNdzejrjVh z1KKXM=OSA#(splsd)#w}m0H`Sr^5V5PA`sB8aEyOWxA2Il-q9P0_p!`Ws9s9H*$sk z*U#5>Bkvr0>1V}_9P`G~_DL~6dEMm94Xft(=A*nt~1TMGy9pTPo^7|?w@&g z^u8`>NGyjAy|{O3=~7qpnK&xl(_5ue`9{w4){7^{9a3()k^96|mtG@oAn&yGFfLMOP;gxe+zOAlIl_b!|F z%-8w3ywZ5V7Yi2HU%C3b2hw|Yb~==A=!GscrPO*!YMH?UMN5jFn0G?k{dMlC1MAw} zp9z=zI3(Zg4J{A;^YNAG`LC3|R>=49SI*4We*O+^Z~N1m`rVNJ({v-=`ew}7{CT9( zc-+t1q&s<$bSB?3|2k7V{L7@=cF(L4*W75$_yF1Oqve)sdq3`2=%3=#{IHik`X}AQ z^nMKb_rsCt<71O_CVzU`r8v{}`0o>M=V;d{9)Ux=os;6sCC;QzH9b?yw`XF}8d`oC z`Q_;JHq)Is;H|gbDIV(&|NG#c;<3Kv` zZJ)MxZrF&&9x3ka8TVcPUE96gGUm~KXO~*1rZf4GKHi1$XQ+4MLN~k6H67kfpODk7 zob~p=%hEGXB6Cy!r_<+^bQez_F#Fp?=I3-KKWq;7NZs}t*9m+Sex>nmgQ#^Yw6<6B0h?U0iYj2T0 zS*G`H+PKH27hjzG@z5tzvw%wDZp&kL`4?J|uw+_-nCb(eG^-^d%B*zxVP)06i;DYxCoBjSqh`t@TL`C)~& zcWvr`-Z$mjSZUm0@8|L*)5pjs^FB`>BR$fYZ1cO~OuP15r_Y}8cIwjA(-*>(#`9L| zp5D$tZ)aqjS-kl5x~}P~t(5ZpySpQYU2;zGn0+>M&WJ+h+|k$dORmzrvdp1hFIj4R zA>Pb!&JGs@s$B?(v zXWZ}7q5POVUK}dEuJ|LaG|O9hedf60%ZjJRJ=go9bfNSS)c2A6#eRD4e(k;KS*6x_ z=}dmi>eq<}KYv|OORq8V&D@}f4K1_3yz`yRsM7eqfs@m-b$X8`fB(iIZP$5XiF?*6 zwJw*AIyw?p|@Bx4faFw>Y}oc5mHv=g&{&hoI7U`KIeE)b_q@b@;3frPhPe zk$fA!ah?1Lw`Yp^nRbbFHt*6_w)bN$}XnQwqJND&u+YUef=8YrMlkTnQOumm!FV0jN ziznT?Qf|AC9*%3?>zePr_w0-LU8*!zHl4bE+cgIr@^<*T&3@%fB%(p4H-u6*~IAB)>H>)FYp&rhEz)0uo1bzCnP z3q7%L;!O?+~__0!{+9=#pUUFOWTyY1=M#^k%Le>#$Hk_CF=xM~zR9uI^uI{UII6 z5B0#}Nbwo>uei>XA~v-2e{Sx~;ywOq!Z+6z@A1E{e)mcGP)YCc;7fXEHKp|1Dfz+v z*roF4+{P611J~TG?Z#Ic@BVPl*0u+`GIaYj+iv>YN8XxUfd2ZYsSBo0YUxOR*j99; z_>|i<<+g`ylepxOe*Mu`pE|MalJB*DCVe%L9=26(d~~U{cWu%&U%Z*#wVl$Dd@Fkv zM~Y9l`^9zcj_b6H8vSW;od-|c_29O5?W=!&9hh%prSYN@8aF7l9+r;en>fjJ-cKL2 zC&hJsD`G>-RTJ-?SUk~AU2mE6@sQr3e}CFGJwv7IZ2ofpjnYfPbR^%z+JA-YJN@}Dy0*P-OFEGnsiZ$s{1X zi=in>NkRufdP%5K6j6Zyp-D3V1VoCxAfi|hQL$skf?Wgzd+%KoyQqkW*!O+UbA6Ne zzW@K)d$04Zbn(#H@G1}04Hgw9CGw^W+0OE@7bH{L8Mk|R z+thY0_~47w9eI$wVc_RSMQSgyCI0vnsWaJLN%&_Fi>24;Z;gKjH7yLW)<1(Z3p?z^ zwSNZ9V#zxGYRx}`h#fP^PVb*VEejLvfPV(HEu3rz{4=Oy;WYbBoqq<^W9gA-)o8QI z)w5!i>sKCCyQ+QfITA^08p+B!%Bn~tRx1*#+$HPCtj<{l)$LoUI>sKtg7y(_(yK?a zvceNYEhZ{OVi}x1E2~mgc2+05FUY9r^i5`Klc{6NH(5!W z)Tt`lqM&>~4yt5(=jU7{b-*s5s`^TFCe>O;yVqqW4y#)=S}natohy3P^>eJ=uEOp$ zu#MEHSftf{u$Ns(HP1UeYL{Jpbzf2I{L`b6v^p2}suPLSwj&~bgk7VpBi-wEtvjo7 z>Wu81{X)0z>)I8O`tUdIPK)GS>oaL(dL$!fUZlabe%Kz(JvZ{~hilkkjt^JcPa0C| zJ=sftefW2_D}GeW2l+J`nPhg-qQ6(JWIK}D72A5Wb?e-cqTI=)b8<^dCgzrmE1g(8 zZcfSUxy2Lb7Ej8ZSh8@=+}U1CES@y4q`0)gaejI`b?4kUCDUe3n>%fOaU^%@?3u;6 zMKg*Q=HYSFY=rMXik zP8?TMGBYVvXzysX3d^e+^V=}!n9WTd9B;F@}pbZ(f>FqciOCp zGv-Yy&Yf8_aq6^L|F7>x>B7>Am&BB*xjjoJ&6_rBcJJ9G#jVONiv@E_QWr^hi3}^5 zJ>4$z(%cbqib_uEH*eOsk@mGr88%~H>A2xNI}C3BpSYUl7tJm9ODhryujtA1W=(9H z*Rl0P`|(U<+@#{kMe}CN9XEI3oZ`~fQ%z{ZuC7VbX3e!=-?kdjyYD#L&56Bd&zw1X zmUV^?Fw=a~VHL5T?gX~h$hD0ILG}OcBZ#KQrbL5kvAV5u8|CHJw>z&&ITlNEf*?IN zsFrSvQ?vRZ6^cgbHG*m-UZhtKs-=$UmO626tFlwsJH_P0l7+Ud$z4-rjc8CQmX%Q$ zWX8^nP7Z3NSI=!3WHt$E9UNrZhH3=0CZ!Hk4{EjY1GzzM+j^}->~J?b81*h_Y%@D2 zsFZ$GkZC`uO^aO{y(6gQhx`OSbHi8=CR>t|I^DCUwGL|dA^U>Dll#9pw$VJ>l^VG% zg3LBStpmaZs_Ib*{ z|L6tsf6vDKTD4n?UEzkjUP0=bx2yiY!jrZs>T>@d`}q%F7yraLrCY3WTKDLG{T2Lw zga3bbyZVpr^Z&U*|9O4>mlFSXuE+oTF75w~o9zG21@+(F-={qqt^S|A`~2rsJf)j| zML{KdkV@VE1VLKM+V+rNJvX;S(*~(W_gX=<@IcL=+QF&D9{3yDfkr&=+rv_I+eo!W zL8Hb&_0(zftU;GSR`{6LNRN4`*xI(xCaCETfvM*PcE@LDYtJJZYwOy?|5+Pv>6c5{ zp8LJ+fA*63_wD=Bvz)x}GHV<@MCju7Cq4cYBNhF*T$|L6{V$*R|KIawha8^r_^+3` zKlL487iig&V?R(m2wJ6@>Wy-9Q@0p7C_B|Za`>dJh@dCNg}S zzk1N?jen%h;raGqbM4Far6X0_@_lMkwokn)oSk;Q4GTJyovL$cf9K6Aoi=4w@uVDk zEt5LC-rDE&dX;aaBTMaqO&w_$y4JNX+nDVSXWB-mZ(F{J-eoKDdvjK{<67ZzDtueuKlNg` zPw|9#QzG^qgjrLH#}&_-G_7dXxEZr&O$on1ySnV`?Im}G>r1=Vu6%FJMtJhFFAs!y z_-OnJ#JjjKEqS%`js7J^!4TT`NztL?@~_cpMN8mU%n%~qzsI9HKxu0 zedX7eou$6Qvh(Si+Rk*py`_%I)5eUr_NiCd-uVqZb)ueS%k%r7qOFcAW5RCacPiUd zez`>C04KkkrhPqj*8j=xEa@9l<=?OHyDco1sk1w*@X{$qoNtQ5E{`M2UFY{hfH;@k znDaX2rB*@2F0XJa9B>P%yH0s3TbZ91uGFowLT`5ueqWnker;4>)=}GoLMYf5bSl59 z?1~Jx(S~y`CzxMuFuwvq)1k918F zIrYG3j}5k;ealwcHJ~k)?*Z4bT|zpp?7Fn8AUub18+OlSr%G)+JgTR5)~;kNw?>D` zz9It{p4#ri{m!%`ym<1%5$)3cH@mFKIi}f5@nu-km$=__wfI=jZr0vGY2$ zX_wQyq!RF){vy0}ovhRR*v+HM) z7k0|YbLO{iRXV5Dr2G!n6qQVz+ReTtKEG3|nXPBqH`QBADxK3}@|>JjQ*v4jZIjc= zzKh#!qU}Jd$uo;fON*uyx0+ErYs%cI-SVsopBlCDtKX8}#m=2JdseGb`);(&QtKua z%`Ga+;YDE&N#TKV#QsR4FWZ6scaM4@)C!NxWe81kYMbRxL7ipl7G1XG^5>uVA^DUP zyZhE|m0v?4_p*oGlEu5O3R;=+EZU$ z1inBA%N+BBw*0wfg{PW4pVjk9yMN#Y;ZHTg3q}yb=Z&ea+@Hwmxozqz3~zO1Up2R~ zGRsi*C$uM(-4$|YQU3g~{OMzU`TZom%dY&gC#q%7K+B$NR=6RR-yF)HDso+yKT#~Z z4#Q`gk^a4Vcgbn)H=Uj(GjsaRoKQSzl0AbT$q$ZFw+CF@nW`5DPGGtbI6J8@3>xxsny^J5pJt&B!`cD551`468W(Of$i zbZRxY_28ZbLn7%_6N58j$&7088qu23+Oay(y3u;k`q2i_hG~tX_IsND_EE8lM}GXf z;t68@)0YY#G5^U+g^!s3@TI~>%zp4vwL1+A>KWDfa^ z`ESKm_=uJLp-ouEBKEg$6+UAAN8uGdVv({9r`lNLpbE$O_WyZl#Ul12+6o`BNVN*d zPhT@)Kj=+eEAFG3UB1mKoT7>yZu>8}=fC8k|B@&COP=#DdC9-z75|d$PtVFe{QUpz z2Y5~AMw(8l_#!i}V}+ET_swfl~Ldm&Z!)HU^FxGc5J|DU|FEk9*m=SVNx z)ujCqVn3e^?Qh7GpYeG}Bw~L-mO4J&ZUTNf`#rc+KU{N$&m8{?Hk*wi_D5^s@pki! zBpdsmpM}S7^x4S&)+{{!IiGg?XFhHHZl8_p5Bz-E`DUcqY+^rM_i4F-PrGAiuH4I~ ztt<3t>yA-B*{7{5QC{TJ)}5`q-lwhG;M3OKuYS8vTlb2xzY(FY`%Ky2>(bYy+ild> zRr6{4)!3)4YpvYDr>z_A(=IRnTZE+HoS@@Bja#iWjA48-_WP6KfGF@!Ngc@h|wapH0);M3NPR6fC{t(&U6-lwhG;M3OKuYS8vTlb3cJ3ejQXUYxiA;s4<^=a$! zeA<5W^J(jbE06JM>t^}1%W1w(yPk|=B+VXXY;*SeLH1innl&}+`m{gSwoOOU?7^nF zdVikbr?pH7&6f6r!E@Xj$IpO3m&(_>f8s<%!-_Hy4@0#rv zgt@2YqD5goM{~>KFu$mozBJ6$H3uyZ^KqJ&oDt@0HQzZa%%5vEJU7fOG$)-O=94vV zTM_05HTSFx^Pid>E)H{V&Bd$3e4ggE%fkG!X2zN@*VG)cHq6IsUb-&K*J-|YO_;yb z%(*Vitu!a!5av?NJ8lZ|!%pH!@N-Q-aTP{Li2#VF!1%kPvJc3=Wq_xJoA?@U#$6@{jU>#`nNT!{1N7ZHIMl# z%o8=&*{eH0{jHjx+W$=9`3KGB_DhVO+iT8Bg!xp>`!mD5Rr9y3FemI+c70us%HbTW zd3KdBuhx8_TA1I}tX4D3hiHzj9p+-qYwCvicFoV~hxtd%BkX^{@bm4cIVUH~r)fUW zILuFKHaIlQhim5f3?h;4%7ZkI)10h%vQK-=o~OA;{W+SKYF?*#m*%6I&uG4>`KeDk z-&%)-^AODun&)Ufs`-OvxOS7ToaLs9&C7QQrKBl=xGqAsR^zC%g9I825bA{%0 znr~=+t$B!j%mzsMt_i6sA8MQwk^6exwD{I!)tgqQrv$6fo(d-2P5Bdtpp&YW9hzb#NYwC6)Ywcz03cqz@-{ws9ll&J#>^F2K&$cD0!$lJ&loZde zc&zM~MKkS0J%DTA~>~wi{ zntwgtihnia*PVZ~v`>54AL(JA{;_7d{a0IdWGy@Fr}0lezXA5iKG?y?zRLFfC-cPz zhx%AiaeJ#~M|o@3+g^?z&|mtw zpzw5l*grV#Ogmh0d#fsJuaX_d{@F{gvNd)v($Kb7-7Y^q*xuzN(4*MGS;2-&8?C<#fjzAxNoPXL&tACvC)ydIFp-$t2({0vaj%qL^8u9xHKKy+B z!(M9rWB)c(_v61>1Y1`{Uu<7UPA3nLQcwS|v8*fEzJKVrNeS3cW z_+`Rv!wyFFOp8V~_yK*ey{eWgp6(&rzxO$jO-@(wZ>c)9o}HWDF|R|Xyf&TMw9m00 zOXlTQ__srcb~!nn^V)Z8lj9%blS}&!>KFboUbx|?eJ7CZded%fDh1(vLUa3CYDHRo zePHOLg^vwV2~Z^y8XcJ zyx#jaceJ^_*Zvbb*vuK{p*=NK)t870IZ?yfu&b&7c#PcI9et++()Lv~r5Q+NU zU0HDDz_o>IQ(faGJ@$7#a`4{M7TNwT9J(i-aarNeeM{#w9=~gXpLX@Y)rFT9T$(y< zkG)-ccz4ObOA1#PtWI^dvSaW4N3}V9pnXLhdhPF)H@?xw2QK~8_G07EJ)^U2uD4IV zlAU%qZ&?%jmwnd$?#@|OID4=kYx};{_C4oK?fa>z^Vy+&Us$kk;G)7ssV=9!|7ZAHB& z44i(gt?O<7SxA*8lL{vdS}|d(?Q4(1jPcJ;s6O?Y@bshn_-akY4(d|yW|42Lift`x z>ebOFf9f&*H{aq&-;=h5FBCm9VW92HI@{)ey@|Y>M#BfS8W^s4bwa(Vt89DA8V%jo zedOT1OXk?R<9qD?sLS}nEOi*VZ|CBsgFimd@?!g3{^WrM8$UkK{F5h5fPJpF&sFw0 z%szYAXBGQgM(#4GMxnZ$HvRaBea^AZ@%Cw_ZMr4Add>s)atS5{Ya-AyT!MCrzm<|qc1kCyrRm} ze+_={sPAuGab2uQG%`1`sqy=RE{^Y8_wyIK2EKXl#W%I8bVI|1wSV4qOyjK$Hjc}Q zM3=q&YWL{3v8s1X+j7Y>{SWT*-8IMD_j$+5C*9od(dWM(S2B3o@23vx_WLcz#%}6Y|EXVFGwl4D@Q9cnl)%I=i`;olU z>~o8Kj+lN`>TB9r`p|%f3RX?%Yp4ws(Od+&RtL-)1oc|~Kt)=uj1@qx&$s|VR}JMD9eea^AZ z@%9<9&%CP!tQ%;v%2fsSZ_ZVPF4#X)x7UL3Ry?}#N;^%w(T)nY@5@sA!|l69lktbz zd7X0hKW@nv4qVpEZ(nvyUhlo{ruJ%$-P_FBX6+Vkkwf<#nr?^vRypkS0rqd+a=*u^ zvb@0lwc99rw6t)k_c>`lF6(vu&kv-XR&bh~dgrj~_fF{bMUkJ%w4_Cvd|I^qz$^K? zrr9kbt@^%Y2Myh`DmJ%Z?tt|Z?9^2nj~`R8YeJ7b>C3aGt_^QH!-no#IbvktGev$4 z_%#&InLcn>!LW&3KW=i+fPoWwr>>uZK@$g_IbmYqq=HGQ%fN0QZTy~gS+l`=OS<}H zUNXPuK)ap0?wmSJ?N*kbV_)@RyT$BY_VIxQscDCI+9lz)9=}Cwu}^Ld!wLppJ;8Eh z@BsU_$CC$kM(U1#&u*KSmF@4&lI8{P6pb-I;q7>9tZB;68ryrnhiT9(b*@di4Qlvb z+{aw0`;5VRr2tEZ9+W=7cS_zkYw?x4iIvs#=p)gIW)$RJhf|*yk|2=jjpN z@92K&7(3m(rcLcpCo**3fu2nVzGe45yN3Hhup$?YpF`6I zYWdyH$16R(@AH|v4{Uq-_L32`mgTJJTIjc9zr9?Pzx%`6hShCet46c#GYW6-u*7al zUo;xC@cSG%52)1nzKC2gby-zIz{p0zU8)V`p!!FBBC zGxqm2L14>cANZ+;)*YX!5(7MC1POZzotBaCUkr%H1OElEw0PoUJ4vkAP7rHZy{8|3 z-Of6eSHquT2N(JJX!=cdX6fsag*iRUWTw%FO;+flKW#eCbX zeC3*+ZNJ(m*YIpR)>gT?XWO%O%GEsEuC-UL>e=?KgK`zmwsReo5Atk#*GajuXWPBb z%9T9Z{&i8#w%o?{??~k=&$fSEm6M)r|GFt>dba&LN;$)`?O%80glF5o9?I#SZU1^I z2cB*JdMU>}+y3=dj(N8I>!X}zxvlMAUuFAm z2^pn`kYkh)a;!2!Mk^!aIAw&4QAWt|$_P0@86hVsBV?>HLdGd0WV|v$ij)yDK^Y+v zl@T&Y86m~W2$`&mkSWRtnW~JCY03zhu8feAltUo}v2X4A&%Da+XyS#TkZbK8Dn29O za$Lxq!2i?wl#r9PR6}nXf1zrzlFu0!0Z~s3;+e6cKW&GC~$B zBjhw?ge*};$Wmp5EK^3va%F^^u8fc~lo4{KGD6N$M#$O92suX?A?GS1 zPZ8l@W4_GD0>eBji?Pgxsc#klU3Ja)&ZP?o>v|UCIc#TNxo6l@W4}GD7ZE zM#z222)SPwA)Ay#A**A#cKv6T_LLSvp33*IWLLOI? zkj;t`@`R#GD2QaM#!tm2zgBzA+IYV}b3GGk^By9uJ2?X8L`|`w5rhLOu@sjZjiTc511Fe4;2JpDIeoE=39XOi@BU zSCo)16eZ+KMG5&zQ9`~}M94SF2>DhSA-k0k@|`k5zE?)b56TGHql}Orl@YR686iI@ zBV?a4LVi|8$bMyn{GyDI1Ih^bRT&|_DI?@}WrX~pjF3N-5%QNZLjG0`g?t#BYuA5f zWBXQh{G*hR!BL$|mbwnJSU>u1uB5yerc|6uc`_6$;*!sVW8U%2bVlcV((h!Mifm zpx|AZYEtm7OtmO@SEkw&yem^33f`5eE(Pz(RF8spWvWlXyD~MP;9Z#xrr=$f8dC7C zOoveLu1q-;yem^93f`5eF$M3+)P#a}Wok-cKq|%U|Ky52VnC7~*fZC7EE+2EUv7;z zizb|xD>^(H_}eU{6dl2ODQZEMqLySSYDJc!)?_KlB}-8rS&H(>Qq+blMQzC_YDa;h z_7o`UK!Ku;6e#LMfuhb7DC$Ciq9Z9#)Rh87-6&9W6a|X9Q=q5^1&Vr7pr{uGih5I^ zs1F5-`cj~%9|el~Q=n)71&RtNLPdu~Q-4F0{LJArm!e;sRADsXzFg6eXwayJ6b)s) z6b&Ow(a~fn8cvp?5o9SENtU8fWGOm^EJeqXrD!x6MaNN~Xbc64j;BD;2^1(gkpe|y zDNr8u;71rS6O7vR;bjk)>!pS&B{} zOVI+d6fGo6(IT=Gol2IX#bhZujf|ot6ewCsfudy;C|XW|qSGl*bOr^A&ZI!mSrjNb zn*v4WP@w2s3KX43fui#%P;>zWidImd=t2q(Yq8VdXEA{?^B@Y0}2#@ApNINs)hBC;m}1 z;l5nar_sRQrZlB!7we_yGqMzYPL`rC$WrtrS&F_QOVQV4Df)&iMcilQh5iqa@TMLVOhu?8f$#eRP@{)rU%`!vO4X$kk` ziV|sozs+q*Q3mU!D3dHjNwO4Wk)P3N~-V`Y6LxG~c6e#LPfujBtC>lV4q5=vO z6;hyRAO(sBQG|+)NQ-@AK$1)Sn~p7{sD;1MADotOU#{rrw7}nHJEdqi>!oM}S&BxI zrDzmcijE;m(XnJH8cmj>|N8s z8$hUNXj&}KfFw`!`=Vh|G|(T>O41VU%N5N}3;b=`Q;JSuy%a4VOVL8I6fGi4(Wzu9 zT1=Lr)5ub^ge*l%$x^h8jH2ZfC_0@2MQ2c;=u8R}okfA7vnfz?4h4$Nr9jbn6ev2M z0!0^4plAgJiY}x;(Mk#wT||MRRTL$Y#QK0B{3KZQzfucJpP;?gsiteUB(MAds-9v$* zdnr(K9|el;r$Esr3KTs+fuaW~Q1lQ5iXNsw(IXTndXyqmbY)uXF$0o(C~9!lN>NY0 zFM2F3;l5nambBo*Bcy06>!oNLS&E({OVM_+6zw2O(Nkn8dYUXn&yc0)S+W#8M@G@} z6exOu0!1%Upy(wE6unG=qE{$T^eP34UZX(K>l7$@g91fwQlRK93KYFffueUPQ1mVZ zir%9@(fbrA`hWsOA5x&`BMKCKOo5`E6rrNcX|c2xrsySqrT>H!t@Ypk`6MmjzFg7g zX+e`#QuGDurRYnt6n#aOqOZwP^bJ{xz9mc1Zn6}8N0y@R$x`$K8AW?2Q1l}OiuO{V z=qCyk?V~`^&lD)yPl2LeC{T2O0!6=4py)RW6#Y(tqCY55^d|+1{-Qw9-xMgaw}cCy z!k{Qhfub}D6vZe|6sJH@KoKh1l@=RdK$7SBebHx9RL39D(qjqt<%*KAU|OyeWwBn0 zvdL0Zi7Z8x$x?I>S&FKVrKl=dimH*Ns5)7SYLHP>lLAGxC{R?J0!4KwP*j%!MfE69 zRG$Jx4Jc4_Fa?SlQlRJ%3KZo~pr{cAiW*a(s0js%no^*s83l?Cr9jbP6ewy=fuh4H zP;>-Es3;>ATWLU&tNho6GGpN@{rdhSsYNW|zFbjmEVw&git<=5MfqeYYD1Qywqz-4 zN0y@YWGS*Y%MEWjQq++wMV-h})R~N;E)*y_k^)6tDNxjn0!2qrpr|_qih59>s3!%A zdQqULHwB9NP@t$U1&aDnpr}6uiUv@isDJ`Rg%l_nNP(h36et=@fubQ4C>lx;Dryyr zymP;@0lsOXefY`g(UcJ}+C1yZ!iNv(|~+?Ol5CKfEW zKeJDLzvx=lOVN6=6kSJ_qU*_0bOTw6ZX`?5O=Ky$nJh)Okfmq?8AZ2Jpy)OV6x~jN zqB|&1bSDLh?xH}^-4rO=NP(hzC{T1S1&Z#YK+*jaDB47Uq6a8Y^dJR_9-=_e!xSib zgaSp6QlRKD3KTs~fuhY6p`vxM*v$qc+0YeTEk%cVcp{c?U#{rMSn#y{=L#uB+gUF~ zJIGS>6j_R%CQH#XWGQ-FH@lC6$%u+N`a!+C{Xk| z1&ZFFK+&5ND0+(mMQ>A}=p70ay-R_j_b5>GJ_U+Cpg_@w6e#+L0!1HFplBxriaw!0 z(WewB+C>p6+8T@PHXz9l{0a3oDO%$9MW4kI?#mT@6$>ia|6H0<^fl|H=o_*WeM^?2 z-DD~Hjx0srlcnefvJ~whOVN*HDcVa$(N7d8+DCz+pD9qZp8`d{P@w1l1&V&9K+$g$ zDEgfOMSoDB=uZk1{Y8PIzbQ}@iR-loilP)KN~1tgi~>b*3KRttC`zY5QGx*s7eYv7a@nA%EDXPqRDLRNOMODaBRFy16)yPs*oh(H) z$Wm03EJd}*QdFCaqB;~Ps!M^QdK4(CPl2Ka6ev2F0!0leP;>|digGAW)QAE_jVVyn zgaSoPDNxjm0!4>Xpy)6P6g8(n(cu&*I)Va4Ehtdbk^)7oC_+V9@z??blDxw2i?ZY4 zEBy!j*>&r9!hN}-Hu2!fo>J77^-|Q1EJf|fQq+MgMIFgf)QK!boyk(vg)Bu!lBK9C z8AaVFP;?Xpin>#vs0Rg#dQzaM7X^xXQ=q611&aDopr{`OiuzNaXaEI@3Mf!iNP(h( z6et=*fug|_C>lb6qM;Nh8b*PlqbX1{oFY_|7msZ=Ajyj@#`C2p?srTh;tBWVijIv3 zANQ7`(X5xE3(0dUW%^tXV=@}3HRlSo{9(e6iU(4te2u^$WrtyS&E(`OVRUWDSCk{MK6-2=q0ig zy-b#(SI8)Ol>$YtQK0B`3KYFTfuc7lQ1liBir%I`(K{3j4dHbocsBic7oRN#+j*+Ig6xuPmT z&~2y`Rb{;tRU=DLb+Q!IAWKnAvJ}-KOHpmI6xAV1QC+eW)gz;*J_U*zP@w2w3KTV@ zK+z!-D9WKgQ6mZzHKssO6ABbHr9e?L3KShmfuh4GP}H0PMTb+M=m-iFwV*&zO9~XV zqCin=3KZp1peTLO)wzInf`m%2L<6P{Z4+zlpiGAmn&)?1ZNyAMIBf#MIFgf z)QK!boyk(vg)Bu!lBK9CS&F)mrRXTK6m=(~s0Rg#dQzaM7X^xXQ=q611&aDopr{`O ziuzNaXaEI@3Mf!iNP(h(6et=*fug|_C>lb6qM;Nh8b*PlqbX1{oB~B7C{Q$#0!5=J zLPc$Z*aicV%*ik~?WE{8561)v_vMPl1i`Z-r096oOVJ5rDLRoXMPtcQG>$Aq;1my)F9!$T+z}XIOrHDTE==QT27Xt)5%hF23d;EBumj*WGOnEEJf##rRZF;6rD## z(fJf8x_|;jD=1KOAq9$7QlRJ}3KXrPK+(k%D7u6KMXM=LbSVXjE~7xvEpy(!s*svJ~AymZA-0DY}&`MYoZq=ytLc-9eV3JIPXX7a2u&Q=n)g1&Z#W zK+(MvD7udVMfX#nXcGmB9-u(cgA^!whyq0qQ=sS(3KTs`fuhGKQ1mzjiZ)ZA=m`oG zZJ|KXRtgktqd?J<6e!wG5h}Vqh%GW8$xZ%B{{|^~(~gVp2omng6+IgSSB;UP=U6XA z&y%I-1+o;qNS30P$Wrt&S&CjEOVO)jDSC}8MX!@l^acfr-lRa$TNEgIn*v4eP@w2t z3KYFZfui>*Q1k%>iaw-3(MJ?0`j`SmJ1J1~2?dHir9jax3KV@tfuheTQ1k@_ioT>k z(N`2G`kEqC^mGv0VnC7&{J!WJDQfMHXx{`0_vMPd4}wolkfI-0FGYLEQuHHPiuRJF z=qIui?ITOk&txguPnM!z$WnBGjG|vDQ1lxGihid+(H|5j`jY}he^H?5ZweGe()F?( zMNtYArBR?LMuDO@1&RU+6s1$3C_#au3luv=8HWVmoOA#unnjRZuK$2PhPq;5vbYgmN z-$W@I%X%pqN0y@TWGN~lOVI?f6ip;c(Im1I6_cfCGFghIkWn<10!7m(P&AzaMJG|9 zXa)s}W>TPN76poCQ=n)L1&U6lKv4+=ib^R^G?xNJ^C(a>p8`dvP@rf51&S6@plA^V zicY0K(P9b|okkHVIzB!2jsZ#j?)OC}NYQeCL|c-ca9^(I^z`7@VktU<^-^>uS&Ggg zOVQb6DLRKNMdy;G=sdC%ollmc3&>Kmf{daIDNwYM0!0^5plB5ZiY}%=(IpfpT1|nX zODRxv83l?ir$Esa6ewClfubuZP_&i;MORUvXdMNLuBJfIH54eimI6iVDNuAB1&Xex z2o)_$k2RcZiVpQB)XSx4Kop8`c6P@w2T3KV@rfufHoP_&Z*MW0Zh=u-+5?V>=@ zXA~&{1&U%6D2h{{D4;-5It7Xn6e!A|Kv5`YC?gcrW7b@MuDP3 zDNuA61&W$epy+T46dgfqnC8MYx1&aDpplAREiV7%DR7ioMffOhjM1i8g6et=( zfuf-lC>lnAqN6ELG@JrOBPdWbk^)7eC{T0^1&WTPK+$Ll6dgx_qA?UGI-Vj_)HxAb zY(SE`EylY@(TjdxbV4HGzFg7xL~wPf6cw>viYAbyXd+pPCXuD6m@Gw;$x<|hEJahv zQZ$V$MbpVBI*9^BGbm6rlLAGvC{Q$;0!4EuP;@c{ib^O@R7!!OxfCdxM}eaG6ev1{ z0!0fbP_&Q&MT;mtHWGOnIEJYWPrDz3NiY_Ee(MqxuT|`FF zDhd=`Oo5_HC{VPT0!5cnpy)CR6kSe%qAMs+w1xsjS5ly8Ed`3MqCn9)3KU&Ufud_D zP;@N?iq=!0=sF4%T~C3c8z@k8BL#|Xq6ih8k%(o?H$`__jGrk*mHZLy=0w7MxuV+= z!Ql&}=yuji(H&$dx|1wLcaf#&Zn6|@BumjfWGT9rEJgQ`rRaV#iZ)T8=m828JxGC~ zhbU0=Fa?Spp+M226exO(0!5EgplCA%ik_fA(H066ZKXibHVPCyNr9s66e!w3fug4< zQ1mnfik_iB(X$jNdX6Ggv>_22VnCAirZSQEtx`1B?~9&KB;1!PdN~oyUL-}YuwIH@ zB}>t3WGQ-`EJbgSrRYtv6um{3qPNLX^bT2y-X){xJqi@PPl2KjC{Xkv1&ThRK+(q( zDB4MZqE9GL^eF|3c2S_{GYS-aPJyB?C{Xkz1&Y3+K+)F}DEfv1Mc-1OXg39lzN0|V z_Y^4lfg)7&Vj^~_0ZE?gie8eUnBN!eNhI8tE83R`HZ7K-pII+O`^i%D3t5T|kfrEX zvK0MBmZIOuQuGH|ivA=^(O+Z~{Y``zkE+ey{TNVqRoR5v5|eTfv+W4#pBCreQSvJ@RmmZFAaDLRBKMLA?CYDAWz z#$+jKLPk+j3KTV?K+&NTC_0P+Ma?NtbT|cyj-WtM3knpqq(D(C3KX@bKv6CQit;E> zluv=8HWVmoOM#+x6ewy>fuar+DC$UoqD~Yj>P!(Ts+|$bS!#;b`cFXWWQ4Eu8~7ty zmyCq_az#gF1U;8aQFqo$Q4g{d^(0GCFR~Q%CQDHtvJ~|tOHn_v6!j-d(Eu`v3Mf!i zNP(h(6et=*fug|_C>lb6qM;Nh8b*PlqbX1{oB~B7C{Q$#0!5=JP;?9hijJi~(P#=3 z9Y=wpF%&2|o&rTDP@w2U3KWf{2o-hBh)p&i$zBepn-p#G`=W6f3HRlSCT0ZZoFPS% zST9AzWGR|VmZB+SDVj=_qG@C)nogFYlgLsugDgce$tapdfuh+ID4IioqLV35R6>EG zQVJB!r9ja<3KY$!K+!1_C|W>)qJ$ZEC{Xky z1&X#)plAmLik_lC(bE(tdWHf;&r+c1ISLd#Pl2KrC{XkwMX2cZj94cFk{n_&euorw z_D8grG7|2~6}^@b9CyAHz0P_mdV?%QZ<3|xEwU87O_ri}$Wrt!S&H5xOVRseDf)nn zq7Nxh^brM$KBhp?P6`x#LV==BDNwYF0!5!upy+c76n#N~qAw{>^c4k)zNSFYHxwxP zmI6h)DNyts1&Y3>K+z8rDB44Tq8}+xw3i}O^h!o-i2<>nq8Xf5rRWF$M)pq`3HRlS ze#r=~T_HsWST9AtlBMW3vK0MJmZCq%QuHTTivA)?(cfe#ie&0_yA(yqC`zM1QH%mb zaS9X#6evokKv9AMMHv(*%A`P1k^)6p6e!B3Kv5+M6ji1`(Lod_szQOHsuU=yMuDR0 z6ey}efufoeD5^z)qS_RpqMtKj+YLzadcXVGFGaZ?>SQL|mn&+J8GOD{iVkMI6g4DE z(II3h${|ZpBeE1VCQDHhvJ^EXOHnhj6dg)N(P0!QYEFTo!zoa71O86et=-fuf@+P&AwZMI$IsG?D^EqbN{x z3jio@*I0_Vvr$A8=MX0EIW^9-NNiOrd zpB_>)F7<*fGvU5m(d5kFoTyWD^zYx>q(ISH3KU&MfueO3D7u;gMb}WE=voRCt*1cIbrdMNo&rTTP@w2W3KZQ$fufr! zP;?6giZ)Q7=vE38-9~|;+bKdt=Vit|Fd)gk7USnj(QJR&e@AA*eYv8InZch|NYOp4 zm!f;gQgk0#itZ;%(I&DKJwTSC2gy?O5Lt>ICQH#HWE4G0fuhGKQ1mzjiZ)ZA=m`oG zZJ|KXRtgktqd?J<6e!wGfubE0D0+$lMNdx-fN}kE!IoX+hi$vhb%?! zlBMW9vJ|~fmZA^HQuHBNiasJs(Z^&I?W91_Clo09lmbP&C{Xkn1&ThWK+zWzDEg8D zMPE^%=xYiTeM5nwZz)i;n*v4OQK0C13Kac7fucPWDEg5CMSCew^b-Y&_EDhdXNpkK z>zT2s1|+%EU);YTMUDLb4B4NVa9^(Ix6I(YbyD;@>!s)qvK0MEmZHDNQuH@jiXut9 za+jhgS&GugQWPUgQJjpTfC5G76evnipeTa^MVS;RN>ZRGivmU26ey}hfuhP3C_0D& zMO7$JRFwin)hJL@odQKQC{R?B0!6hbP*j@&MRh1pRF?up^(aC`2Qp)K8IWY2KQH=K zikA3&QT=4XeYv7TlEKT@NKp>!rKk~EiW-xps0mq$nv$ic8Ci-BB}>s^WGQM+mZHPS zC^~`yMJ*^$)RF>4tte2`ngT_+6e!B0Kv6ygirP@1s4WGG+EJjWJq3z7P@t$I1&TUR zpr|tiin>ss=tv3_b)`U2HwqLTMS-I36rrMnld*jUB-z35ei|mjSNgR)^hhS$mn-U% z3~F8{MSWQ>Mg7Q9)SoOx1ISWTK$fCHvJ?#@OVJ>*6b&Xz(GW6S#I+g-OqbX2y90iKTP@w2|3KX3{fua*BP&AeTMdK(?G@b%Q zMHDESK!Ku(6eyZR5i07HjCC;}N&laU;=QHlK@Y{rg!^(u(~`mQH%QTR)=SYzWGR|K zmZF(tDVjx=qS<6AnnRYNlgUz4LYAUZGK%I>plBWiisnsMN27Aw2T5p%PCNFIt7Z(pg_@?6ev220!3$2py(V56rD?fqVp(1 zMN^WoWdRce(aujM+?Oj_nGCMGNs2CFy%en?OVPz-DY}F#MXSkDbSYVi zE+b3PnP;?aqiq=t}=xPcST|6N<_Mafc>MwX%&S&HIhDGJC^lunkS1Q|sc6e!B1Kv9wcMOhRm%BDb3 zB?=T(ra;j_6ey}ffugDuD5^$*qUsbVszHIGniMFiMS-H)6ey}gfugz;D5^(+qWTml zYCwUagDFBqzb9jB3`p{K|915sQgovo7jKxAa9^&daaQo~T~gG9^-|Q7EJe-8QgkR; ziVh=7QFF2s9Zr^_Bgj(Jf-FTX$tY??fuhzFD9WWkQ62?~@+nZ%h5|)xDNxjo0!8g9 zP}G3}MI9+n)QJK`oheY%g#txKQlO|S1&X>+py((H6m_RSQ4b0f^`t;iFN#o6PFCzA z1CspHe;V5;D}1H@gWnhR&Pup1SJXc%_j}oN0U)BoB~B7C{Q$#0!5=JP;?9hijJi~(P#=39Y=wpF%&2|o&rTDP@w2U z3KWf{K+!k~6pg1qQ4s}-CQzVgA_a;jQJ|=p0!5Q4P&9=iRMa;s*7P1z^rL^*v7Z!O zX~)HmJLB=7bg-@(d7iJ~gmn*tB zE4W~j6kWo4DOydIqD#qAbQxKSE+-AaL?+bB?UI|YjFpg_@` z6ezlj0!4RIplBlniteEZ6U1D|$aGsQri(eZYDt`j9L|ACaZ# zW3m+OBumjJWGVWTEJeG>QuG;FiasZ!=nD!IeMy0$uP9LTH3f>kp+M2M6e!wFfuipy zQ1m?oihiI#(H;sE{YZhLy%Z?=i2_CYC{Xk>1&a1lpy(G06dj;I(XSLJ`i%lbzf**Y z-pz`2H6Y0&{aZxuNl{lP^+#61eYv7Yc5vcjQWVYBD|snOBTG??EJbm$6a{1{N+(NE zf-FTDWGTudOHq=HqAUs&WmBN25(SDXQ=sS|3KUhLKv7i+6jh@@QFRIw)u2F8O$rp% zqCin?3KZ3$Kv7)^6xE|ZQGE&&HK0Jz!4xQJNP(h5C{UC`5i0sCD|Wg8NjCJ?Xn#vl z8#^xEC_CZ4Tv4;^;D*gobSUek=rFPrH785a;bbW~f-FTX$WqjjEJdxzQq-C(MY&`Y z-pr{)KijJZ{ zQFjUy^`JmePYM+EqCin^3KaFBKv7?cP*IcY*fRzs*~agSnr4Tu^w06oFFWDBTv1_m z@bwlc8pwJn8bp?&!DJ~KLYAVTWGNa(mZGD{QZ$?_MI*>kG?I*>Q4}aTh5|*$QlMxw z1&WTNK+zZq6dg~2q7x`kbRq?c#!{eY90iKTQ=q7b0!0%jP&APOMUyB{R7`=Q$rLD> zLV=>G6eyZTfuiXYp`roVvC3ObQFZ^WV}TT%ZO6q=%1*d1S2R02$bC|Z=CEFhP9{rH z30aCt$x<|zEJgFkQZ%0|MW>LZXaQM@7Lrl4hyq2YQlMxt1&U6iK+zHk6fLDd(J~4Y zEvG=y=@ckBg91foQlRK83KX49fueILP;@Q@iq4}z(fJf8x_|;jD=1KOAq9$7QlRJ} zicrza?AS;HlAP~PsAoyhxgJ(!C)}4Sx->hOw?m39W4#nzPL`r8$WpY1EJat6rD!c# zimoC{(K@meT}_svYse_NmI6iVDNuAB1&XexK+z2pD7ujXMK@8P=w=EO-9mw)4HPK4 zl>$Y#QK0B{3KZQzfucJpP;?gsiteUB(MAds-9v$*dnr(K9|el;rwA2Yk{w%XK$3<2 zd)KR_=q(SMvJ>vh6+N6CJo>a0J;Hh^dXy|hkCCP5ak3O`CQH#1WGUK0mZGg>DcVMs zq9@5H+D?I@9TX^fiULJXQ=sS>3KTs{fuiRqQ1mFH@lC6$%u+ zN`a!+C{Xk|1&ZFFK+&5ND0+(mMQ>A}=p70ay-N`)dN4b-(|{x=_}$M#Qq<6ni@%qh za9^(IqwFC1oD_Y`dMVmTmZDF{QuHZViguBu=rghueNL95FUV5#C0UBTBBSVQ3KV@q zfue6IP_&x@Mc+}N=z9tj{Xl`DJrpSVkpe|~DNyti1&a1jpy+1`6z!)#(JvGzIzWM< zUnx-Z8wHAfr$Esk6e#+W0!4pOgo-}MjvZ=1l7IQn^gooMe1E0?cXq;kxuRI5p#KX} z6tDEpSNZ{2iqgqalpsq{23d+S$x@UgOHmeCin7U4REdnD$`mL%hyq1bC{R?D0!7s* zP*j})MKvf;RFeWlwJ1q8d9L>5DFCKP@t$0 z1&SI|pr{E&s3=+~Hp74<OHnJb6tyNxQ7&1E^2kz@PnM!KWE8cfKv6pi6t$;7Q3nbXb)-O1CkhmGra(~_ z3KShlfugPyDC$OmqN6BK)SUuFJt$DrlLAG(C{Wa!0!4i&P}G+KMg1sH)Sm)H11Lg8 zhgOQ+Ye15RJDkI$sGC2$6;w*NFIP0UQtlKqnqZ9utXn{^W2K2=1Ekms*4TURCAL(P zXkvjkzqsUQNUq*m6X=kRhkC7xTpwQ`wk$Rw!DF_(IV-XrX95v{1AGS}58GEfj5n7K%1Q3q@O?g`%y{ zLeVy8P_!KeDB1x76g>+A6zzloigv*OMY~~uqCGG`(Owv!=s6gm=y@2R=mi*{=tUTy z=p`7S=w%q7Xdetv^a>16^ePNc^coCMv>yg2IsgL{y$%Buy#Yg`XjNtXECR&)Cf{{j zEfgK$mHxrXUd$I$^iE~t&T~T1A;cGo{sk=*y$dZAl|TzchoOa{_n?KMBhW(8QD~v) zeQ2TR187im3(ZD7py)6y1UWif+RIMZd!UMR#C; zqPs9aQ5g(S^al)3bPon7`V$5yx(@>sJ%9m<9>M@cf58AnimxopL6HuIM$v`Jdh>ar z=sWIUrHxeM;2l-vc zMnX|F?u!z9y_heiDB0I|s8lHGj`%`R4``vNC$v!13tA}Z4J{P)ffkDTLJLJH&_Yo^ zXrZV-G$-4MPm_PC>jSX6pe=#iY7n{MH8WgqDjy~(PU_$XbQAYG!ctjCJazC3kE2f4FeR-fdPu1fdPubQD@BdLLRS`T$xeItDEi9fuZ* zK7)ga~PoLGz?I51_mfP3j-8= z0Rt4Bg8_=ZgaL}af&q%o!vIBJ!vIC!zyL+x!T?3z!2m@UU}zK_^40GrK)e%qcKt7* zD1b$&uNU*h6#eLHJo}4KbP4f=qRY@i(NEAq(a+FA(J#g8_>E zgaL}~!vIAOV1S~BFhJ2?FhG%Fl4Uz6(!l^l9xyBe0P()cf9>I- zQ1l#AWHfm(UrbR&ld()egaa#q^uUg`$?w zpr{oLP}CX*D0&(OC~5-(6t#r`irT>dMeSjLqBt0!C>{nV>Hq^2b%X(mI>7)%one5Y zE-*k*R~Vqk3Ii0`V1Ob!3{d2N0g4h}fTBbgpr{)RjiM$d{Tu?s+n*^47m7NvNHTdb zUrbR?lX3TTp{N()3q`%5g`z&tLQ!96p(q7fDC!3-6!nJ|iUvRnMFXLQqCwE0XfO;= zlnMhBrNID2=`cW11`JS?2?G=jfdPuLV1S~bFhJ2T7@#N{1}GX10~C#b0g6V#07au< zfTGbbKv511P?QS;6y?DHMPp!qqI?*jr~rmWQFoL61Oei`l=aLD5VYplB8h zP&69`D4GKU6g>k26wQSJisr!pMe|{Rq6IKO(LxxYXb}uhv={~`S^@(UErkJ!mcal; z%VB_`6)-^2N*JJM6%0_c8U`p@0|OMTg`rV2)};5pMHIcyHyXzYMYoJ3)|tGRFQ#ad z$r$syP_!BGg`zFcLeW-ep=cYlP_!LdDB1xn6g>+q6zzl-igrN@MZ2Lv(HhhS(FZ7}Im2oUcaUfgdKijMFt$bXrzXC@O^kioS;dihh8hQB-2mZze#z$MLf4uuzoBw;(T?yqGVh z=qHo$-9Ln)pAlau`UP4j`W0Fz`VCqrx&kc}{To^+x(Y26U4s^iu0sn&H=se$O&Fl) z77S2y8wM!)9R?`60|OM@g#n7nV1S}OV1S}~FhJ3tFhJ3L7@+6@3{dnC1}ORq1}IX@ zvTO%MIvAkH0|qG4!vIAF7@)`q0~C3}07YIfG>R^n^gj|H-phCpyDStPq46xD*);A(Ryn`8>N@i`P{}WHO!_8jI7gH2% zHaZ>(MNJW3D2jm=iejOKqGr%SQFCaas0Fl8)Dl`KY6UG6wT2doo`wcRZD4?+wlF|Z zI~bs-Jq%D32Llwv!vIAcV1S~IFhEf!7@(*#3{cbs1}N$Z0~A?dfFc_VP-KSziX1RN zQ34E5ln4V9b%Ozll3;+MWEh~RI}DAYNV7hV0P*g?eNmK9^fQYdW-sQ8De7Z3E>k#x zD8yf zGz11H%7OukhQa_v!(f1-Y#5+uI1ErU0tP4=2?G?3f&q#~!vIA&FhEf*3{aE@0~C#c z0gCcrfT98zpr{ZAC@O*hipIjwDC%X_zfOR7Z{*o^Z=t9euk^>6y_heiXp-4@&O<1g zjQB#)6lkGnDzs2E4O%EFh8BvZLkmSSpoOBD&_dBHXrX8}G$@(_0~9?20~F1L0gC3q z07dg*fT9I3K+!@NplA^cP_!5ZC|Uvo6fK1Tik86uMayA;q7^Ve(MlMgXcY`lv>FB| zS_1tTSR4KOr{CYbg22@vnSe4}xqQ1mVLMH|gt%okI%)oiS76pFSX zzEHFsS}589EfhTqEfnp97K(O33q`x3g`z#sLeXAmq3AhiQ1mMTcO3qJO~vMeo7@MI|saiZ+||9S9KbIPQM72t_-1jds}V#e6YE@0*R8UP93a zh%Xc!gBFU8LkmS8LJLJ7K?_A6LkmSGpoOAOpoOB7&_dCt(4goP3{dnL3{dnr3{Z3$ z1}HiM0~DQw0gAqW0gBGS07YNI07YNH07d6vfTFKqfTC|;fTC|>(D~c4QQe0CbUp=3tA|;4GoHZhXIQ2zyL*eVSu7C z7@+767@+7L3{dnZ3{Z3*1}J&}0~9@k0gC>D0g4nqS+;{B9Sl(90Rt52VSpk73{Yf* z0g60ffFds#pr`^2P*f2HDDsA(QS`G}f06+4o_i%|5ex?uD3V!oInlb`WgC85ZS z_(G8%v{2*^EffVn3q^s@LQxfHp{OdfP*e?CD5?%E6xDzRMNh#1MKxi7qFOLOQEeEY zs16KJR2K#)3W5QOf?0~9ra0g4*K z07Xq;fTD01peOJaALv6A`SKGGUq5Z7U&4J+l%E&##T3Q*8JqbEMa>Xj zC~6KZ6t#dBidsSoMXjKPqSnwt(bLdEQ5$HXs4cWm)D9XHwTA(U;$VQHco?9l0}N2q z5e6vg1OpUxh5?GYzyL*EVSpkl3{Yf)0gCJ}K#>CmC`y0NUNAI@n)>Pc6CmFAcq$Yl6pi57b#Ff}=8Gxn=VzQ`7K-{KzECs( zS|}O_Effuc7K#Q#3q`5WLQxvDP?QcW6lFjQMVZi`Xb22Ylm!D64TS-UhQR0~F=M07V5bKv5wKP*em16pe)e zipIeJMdM+Bq6siGiu(HLw-O-UxA_T3icr*yN3@B4Ud$I$G}X^|*k34`hWJ8JF|<%L z9a<=w0WB2GgcgcsK?_B*p@pJ3&_dBO&_dB%Xizi{1}K^j0~9TQ0g4vF07Z*nfTG1P zK+zHyplB%!P_zsNC|V8!6s>>(idMn^MXO+dqSY`!(Ha<_Xe|s-vP_z?TDB1-r z6zzr^4bN~h@dL0HRdIJV1ItT+4y$J&py#)gly$u5ty#oUj9fARh{sjXRy$b^rmB0W+ zhhc!C_h5jcBQP|Iw)yFs5Fp+S`0f4eLQx~`i;ntvF<(s4aX({XHKFK3#21P_f)Rf86aszVD!HK2u}r=W$Rn$SW~Eoe|w8wMz<0|OM*g#n6!V1S}v7@#Nw z1}L(?07aoNKv5VBP*e{FD5?(w6g7YWiWlQ4<)TC>#bTihu!%B4L1{ zC>Wq98U`q83PYpF?5}@FfO!AJgP5Pcw$gu*`=S_sFXoFWYT<9JTSq8riTFZMD`=sp zHMCIlG_+9E23ja;3oR72gBFU~LkmT5&_Yo>G$`r-0~B?H0g5`o07ac)fTAuiKv7p1 zpvVdX6xm>aB0CIFQo`8w^mC1OpT$!vICyVSu6@FhEgH7@(*Z3{cb? z1}N$S0~Gazp;6S#U*CxU@ovN5G#83`abJ|;@5OvEMFahfSwTY4AjB7n215%)sn9}E z8njT94lNXAKnq2g&_dA=XrU+zS|}O{4T^@r07cm_K+$j*plAdPP&5(-C>jL=6pe-f zigI9pqFflDC=UiG8Uq6q<--6)1u#HSAq-Gd1OpU}g#n7j!2m_$VSu6uFhJ2n7@%kp z3{W%~hDK3;fBk#{#CrwbbsQiR{m8@H6n`(~iz%A!Z+t#PD4K!zLeWfUp=cJgP&6A_ zD4GK;6g>ki6wQSeisnHJMf0JBq6N^PXdw(xvu~p6wN7lxbbOqU4z_bX1f=Q&<;8 z8E+bCRg}r5SL}*XY`UAED6>p$lN4pHX=ZmtS!nvOr=l!1nffToN>lF?MOkaw&|gtD zn!X>XC|gbSQx)Y|)97?X*<*SwQ&C}RqP%1B%T<&T zQ{OR)a@4e`Kv9mHE*2@u2~)%IigL=7J5f>2m<~)!vLW73H?+(qcs^Gc{hODEG}{R#5rt%x|os3ecG!tf3mv znLDnhD$tqdZKOKTnLpi3m7p_M*+#XXGY{B7)u1zP+e!7HGxLA557n9Z-;p=anfd=o zH_@5-9|A||%={l+V|8Z!mz*tiX8xawZFFY-r+9HXGyhk!PC7IHTPmy0%>P#?L1+G@ zgz7|R=Kt)`OK0YP&5)uq^WWAVs5A2)M^Dq4`LA0K(V6+r6KCtp{P$%?>CF5GLi2QH z{tJ(VIy3)?zVSLU|BbcDIy3)~tYV#+|H{!Uo%v8H)sW82e`jQ&&dh%(VyVu|zv;hH zXXankUaK?n@7iwEnfaF`x9ZIN+iuV5%>3(0dvs?0eUle-X8whNeL6G0@x5PX=2vzP z>dgGk`cY@*+ZR9U%)I`*qBHXX;=0bvGr-$AGY{cqIy3jd_jQWj&wOwHS*^+W z6D*1@h8)Tny_coixTuj%3CQNJ&3u=z9YEwMy5=G(@tzhU-qn+6={r+B?00H^x>mAh z0i~#GE#f(j^R$RpShNu_QAeV!i29sbI}zTTT6+;gIR|l?2sD%6O#0T>DOGgIo_;5< ze=}oJ6x5+nO33I_s2m7U0*M>tFr`z1blMn{z8u3HCAk(mW$En+-L3S8b^?=UgKE$ z!sTYw_Ivtme({qRDMNIPzddvGI$doKPrqYtE&Y`|D!E^ZKR!wqIfr8LMGn$p>AmA9 zbIT>EWjNKJlM-5}nM=)29Ihtx!JU`xXbHXX!t&Q9DuL@M4qxRiBvecZ?UIDPLY{uP z^7RqUlhJ2L=6f;fWnSyoeVlrkSF7{?ZesHpSqD$RY_E4&(QJkMCPT(l|!Ub21 z$U$q{*wx54cYRenUX5Hfd&_rJf>ds|KYrulR4O-$#MxYfNE&gA$yT%ZEPdf@9zZr3 zo~vYXHh_g$N!7Dv^wUu_np zUw(R4L-^|NM;B2lgmA5MJGHXB9Nd3`5;&jY@c9NH&WH2w?4G7x+Od;gEaW(ze&1fc zJ725Gl_wV*9IsScO)Z#Xsb_iSa{>_9&?!ioK#-KA2Yve@)`$t4R4aE>MLNnYRd10-?Ie{XNs^qT zk0hz?btPF@l9Z!-DU#8Z4^w5z9iQ2(exW+^lPi&v_($m4*FYxf*YMN%d&X5?)1d~R zF(B40d$lN$zGJrtmx=N$I_;Yh=|Njj~rT%7g>;> z8JVA2keQX5m!Dghm06fIBr-F9LSA7m8<|-{it@7x-1hPDbabo8y!_##hZhbXo25i% z=Z?;bOdpjsJ~CodZf5$Z$b#(j{H)0QtemWZ^n%E&rl|#mMMH+?Mi%Dgj>^nVAD&YX zIV>|XH9dcHWOP(&Ols4prqQXIK}0qaM%6WBcupY+>fL*G?3_y3%LK zqe`bfMrSkz{N2Z>^VAQc1N1c_Jck+mJp;m{q9UX86C(89LHe-~Mx$pWxq5Hi-;3Z# zV?eOcUtbVJM?2_fN=}XSXc$oU2|LO zfcC4BFQBQh3dw*re1=H%8p9$ZBlY8GUx?Aa3E7l;HNoJ>VGcf^deep>k&!hUsd)QF=rUH3%x{;n!ea{pD5|0fvWl5@>?xaXS7#Au`*N-bfW-^9KZ>h>4iq({3 zM;b$;j8$us43@+Mt^XK{P89OL$5KyKhfek1oWfX z{P_K71wE=k_kRk@;e-SKhdz#5`v1Yu_20KxDv!tz>4*RCjdM|vO&%L;aMdV<|EA~p ze`5%agJlvUv{x@D9# zHADN_Jl6TOSx4vB<}KyO*p~3(5jiSW+t<0H91~3k4^PO=&5KqN<5N;QcI(wt>51nnG>r&weuUW^vbtWm)ulT=&sH5S*>$yH2LII@>6Mmrs)qJ8P$N~8s%Qn9K# zsmLW>GiPFyADpzQ93SIKqN6iLbVru;kVG6C%bB1N5X5|bS zo}QCBDmQ1Cc7aq`bb4CWN^Pl3Yu6X+$}N$h9qzn5AQn9Bi6+(+N9TU2@tu08 z@uOt|YY<2<_F|yBz39=F0(wS7Wi$stEaH3sk()Gxxfr}Fi>O<5F zM7ubPCeSo53OilsMR!3Z331LA7S&Q~c&J6XBrO$u;p$R*GpTZC%;+dBrZgZoKU#|r z?J6)g5?V-ls4WdLK0`}aX;N8hX*9*zU6e$-Fo|~Kgep)@>nt`@Q*;L@8dOp%=OI-5 zQpT>X4mH@!l^=}`wHRDLM7t5;MnZGShznSBlvG+;{&+VhM4_BHniy6s)GBpEvMa_} zgj5hX+{Fc|95wE&<(5=_xlWb|ABl@Wg}WHBC=L=PK(!*I)2d&nB(TqwgqkHDc6!lG zBsm@tsXkPPD_I?@sQc!|<%~@=ASt?XfI6lUl6}s)q$<$P;9`S17dlE!T-y~dnWajW z=;X*Z=M@ov+R@a_a(|bv6;HGlXt|7bVG-@(!ik~_2O6U({etY={6gnIh&p7{)Y^Ae zymJ7j2BhYJD@R3%ibeb4#)7Nvqg|CB?W%oL4QE#Qzji{_}vC%C)m_N)HGc)O-7w7(KX?8O*5mlW~5?BLxN<> zRYO`6a*noYi%Cr_KNY|{*EP*$COJu-a3yu==^WytF{^dWNnKM>*G!aVxWGqiVw{$< zkzf|{TYT>J_S{mW0;2odtl_?8F*W^MrP! zv!_L0x!MDLo z?^zXRSD54VjOSeAJi~nb0*}QyCB79Mn9fgl6kQ~JHMR^-j7W^PbyGb3yb>$wy({<| z0(Dh%)%4YMHFQtuYU*m~>Uf0c_>tqIA9u^3-1y6Vzn&j)xPA2U01cL&pK!Q+^z?MY z&rS2AHhPaqxvf2Sqi@>&{my9G{;l-hh4#_*w{bp})Ap}*(>Rhtz2c0h+Ioc^i@JUE z3cX|H_R%Z+Akg*EEA))d?W0#rZi>?{e>HlAU*m9n^h$t2Pixgu;`;KZ>kD)3R*#N( zM0a^a_j*KUJfia+(NiDM3m?&sJ*5gQR6>WiukxZ=x+$J>QcHbowc?z7s?%Agig|p& z=(f*&X&D_wlUBEVQIt>S-J4!%+s+{s9KB7Yc+*4N*Tw&W!y1b6gXmv5d`eO7h#pKh za=f7&QoMW)DLr}wtj43Jq3YEfQoQY=ZxU}D?;eK~&zl~?dDo=Zt~jLU!u+CzH@#Sw z%^|19Ass)TLppvdhjjd}9MbXp#seR3rl;C`{2UI+Urr2g$W(d|T7118gb-82VHFAK z5)}_ZEto?>s)6|2mif5m64HBls_r0RvV^@Q%#?71gkvO}CgCgzmrA%p!dE=BbPq{* zny!b>dqKkA=>k~m=z2J;M$L#ri-i0$9wy;dx;EA?N_d&Rv%V!^6Y3OL zw~{cQ%8>Om2@g`4vwmN~hg6rWD^VSA*on%X!|oE!udC@b5}u-h<^A7EST$7B76}K| z)AVo&w^If1@h?mGb0bavE@4Etrk|FukSdCgpDy8B(V9Lcp%Sa<$`W>=3gzQ_O1QA4 zrq@aMd23Bykgz&cJRct>;o$a~9x36o@tS@`!e2XT`mTggT{PWR!m(CO&y?^TyQV*s z&?8aPCJC)cn(i&(;_jN>AmN#wn*LtGr}}8RzJzHhnjS6TuKt>SO~NY!HT{Q#O;a`9 zUc&L|nw~A;zX)_LkB=oZ4Ar!sg!XJr_myzz2u*L2@QYEJz9?a>TunEWFk_6Sb0yqU zpy>k=UM_HGN6K zI&(GMSi&LmH9bbc=N4-E4GFI=*7O4jn=jLJM+qmd(DXbB-&>{WPbI9dR?}4^?6zLh z10-CzQPbNbJil4fKS>z0P1E5L4&9;Y0tsK(sp&T*yt!M`e@WQ#IZbz#aOw-1ULfJo zmo)vEgx;@cx|)Q^uW5RagsTr|dWVGHyrJn|Bn){=(~%NpzoY3Q319k`rr(zEc8R8S zhqbWv5iRU0Ve$K#UL@fM$25IfLZ6Q`T|>eiCp4WZ;o6g$-YMaCr!@VWgrTQ39WCLA zvzi_!;l6X4J|y9tuQaVcuZ3;C(L$SqGrrUG5($r&YWl2%z85uJQ^H=CG@UNt`kyqt zTf$O$#hBacza^}9Mbj}7j=HMp2@<|~UDNMMSVpfQbA011Eo}F@7CI!Hbyw5NB>d

kgyTGG0nP#gn2=lo+9DvA(}oSVXbZP`LYstxC0s7y zZVAszctgT_5}N3ZRZgd)gb5N(mvF6w+a!El!e1o3DPcW&uawgnDB)rbsXmrVxIw}# z67G@k1qlyG_@;#KN%(<;pGtUI!fzxjmGBn{|1F^>&+~j}e##-`i$5IF^iB;6c-}{v zreBJOKfNv~z7kO|VRT`728D(BT9}P*bSJ1#iQro=N<>CMff7MCiz3*JaGT}R(n9rz z@KX?aC^a;fqNv}~GcxkC#=7rK&*xQ#B%~emxHF1hO_U@kCrU&ny+@ZtkILLmGc-Sa zG#wP*BQYYqurPmkMo}Rp``>eE(% zwtqSQSc6~|5 zwS=IM&&!|ZX>-qCire*4SL4jzJM^8{%cDU3n3Hr$YX}PYoc!SsY_m?F<4Vb_Lf?7g z^K!ZKIl(f0Rhkfg>-md(kRIp3{kUw(-w7N98 zvMW)v71LIFw5&l1g?Y54(Z+rGsvUkhF^#yf5+Q#Br2^v4$Wz>zI^~)sB^klp@YRDPJ*D>cNzH)LBV= zrJ9nt-usgN5=YYQ8hMS=uBs_6t)Fx|HX-rmq^S!W?^B-V+v#V?eA|30g?W5V-sU>y z+UMEksVQ~5^RE_M3Q50v#R2F*%lePoq$IpRV zcFABqy1IJwQp<(1;=_Xy2PZsjd#|ik>3dY0?@>(J(pF`>M={N5r!y*Luh(MsO1fPu zvzI-}dLn&(h9jfnhz)e^?v5t*ju|~iY@zQ7HxKI@+Imv1Hj_%ay|`x=YnXj59ouun zCUOixT^zx- zxKQ?UF>R%^m8{6{b5IVK(pF3x<@$=5HfPT1dz@DS{Y-wZ%%G#Ih#F9OD(m%!Z}0jr zMCm(fPS9A}hl;ssT#%wG?mTUmZtVPD{e3UBZDc>09k4ws&8VloeA&q@^cG#{-r-fg z9MJUCbN#1&Tw-sM^U9u#3Mco@da*dNVwF8v6%St5T|S@lrN61hY~Lu|_9T;hyQu7U?|y`u>Dr`EU2T{}xuzVXr89k-Omphi)I#LaCjd!9NUufsr(`vl5;2GOot9C5c_*}2eC zl;BQ|ILfoZkI6)S6U*h-;c(a!YzeC8Z*fq5D>(C;5)$i(q8_n)57<#X7X4qmE#A?= z-a+*OEl*SY8hMS@p1O6k?Z!*G&I_MQUy(P!G;LSVpVL3T zRt4?%;r_X+DokIpBejWb^Yk70?WR*3n@(-ay?u2Yu};W*LFIHkDQ+PKuJNcK%kG3- z+?S@&mh9?DH%L!PV~RRfZ4C>dp0w<}O$nQ<>mTb$wVnul=@u<+a!SYw$C8BO>4&K% zDP<=KOUjY3(6PwA$hKHWSVT2>!i|KPj;W84FuNQHftF&5bG2OUkFk%G_BzRtqt-WS zf27I+*M5bdqJ$#HFx$!ut+(d-_X)~(WJq7lrIvJCNy~8zmj0aj?&J*~_tes(vWsnC zNlEOBvQy{^lYP`tNUnb{#`&#bW-7aP4iB;pvN@<-lplqp>=Zv5hb-Bf)v}B2vMh|o zvA#VVJ?%Yhy{tc_qyNHKp6p1rceiy{OM+{Y>!-Q3xjlwQPG?WYGmc8xo1{K?lx=K3 zp3Z$4mq1EzV@LhR+G*Qzwc~GTK&9*IdyDJQ*`_94_wh-(UC$VkL}x3FanR3_rrc-b zHMLR?n-*=ml+HO-EJ?SEJ$|6vpNhUXJjKJ~Mz3dR4EHcws#+V`DkN^rprg&4%f=YH z`-CQ3O%HX1+3lq?XiyuX@uRqoQc|p+sZ+QOeKM%7&VOLd$~lP<=eJ!~0!n*CEaLXS z;~ewP?XSd7Ddu*-V-3Zfu5YPR8hu}R%Aj4ZtejV=W@+HP{52c05*qhGx} z?(nw8+}?+Nt+dRzXuthyd_aElN^AQZ=yqiU#;-Y5%z+#dmvmbjYbQ7+*eBX1Iex)D0 zlz46Q!&j=kvBJA^gDx@aFEqD(zx&V0%e1k_HTS}}!0m@Qzj4&`?ZZL4r*tjxKQQj2 z?5jMkjjsFBr0mbyRT*{h)sQ|5`!$(0c528+Npo%|ELeT@%PgPYq#deliN`T+b7QEz zGz^=&vCb#6a=*D$wM*vSYj0nzIKREQ#UEE1{84r>ZQf@Uat`d?)@xnVSigHQdv{LD zdAFxJV=x50?s!88<~ais{F-{ro1JsyM`uni(9EgVOxiB;Ds4r^-hZ4qZD#tNb7ag! zHkPAjoo&5iy?uk~g;>^?BWaCet$nR+ow_gSwl;HG?O0=9V_WO2Y0R8f+E)?%GoC>I zCLN6&>G!DaN(R$vvkmbvj#hqSQ^IK7WGzxhgcTVpxE)}I&$E4M6Nc_IgL2N0%eUG| z)M_V7tMyk~t!v!G$b%K;V8_6JTw!YSNzAX@=aXj35Gs`l&Jk8^#i2o#ENhmn3$HYJ zjTlGkL!}|jzyh*2YGn7OxdZh>?Hz3s&Zg7#Jk|^KEmseLG*-lRSsrGib2W0#0FoR@ z_GDW!jVjuxhVd`ak!bH`>*lNl9{=L4@%E4>jDKt0#=oaz{Nt9D5?tL;H4%LyR@$xA zG*J%zmN3dsg8Q|P^Wl{xjbYWTQ8rIrGxJ(GZBGW3fSKo@gGzbq!Tb;NzN1qUZv2=# zuWg41;~P9MC!Xdu_spQ!r>3lXtK z-sktLh0ed6x9i0(zG(d7b<-Yhe>^u#v*kZmwfovv>VCCs<(z8Yr(vwzd-_dX>z6Y| z4qf&AjJNJz`D}56;Um9)dwNX0;!hTi`~1d=z{o|-xi8@H&3(RT$tGH}Ht2}g>(zaW z>CQq)f2#5EG~Rn&D9bxSGnwT_%W7@iMLlYRrMsB-;+H1_K+ z^4Q<~;&AR)GiGwREwya4ZnSNBV!yhU`qj0Lb#`i#(yy)~wVo8$JJ0Kv*n86Kg=cfC z9Sg0zUgMbz_mOke*)8{;+(*u|&XVzxYuXUB&`~VC4X^0Ax0x)X?cc4)i>SAmOY5|` zv`(8#>$J)L*xO`3vA4-BNBL;mXh)7cNA*H1qgA$WUuYz);6~ZBc8IZdgkyw#q)l7b zal6A<>#z@_-p28S-bTi#-YLPItx1lK)b^HA&r*IZ)~{Ti{4ISbAFlC}XLfWhn&k!h z6xT~u$IoPS{7h2E&m?vH?DoX*a}d?@b2GH|5n>IoS<2P3^bCFKP(8PI#M$F)@lwxm zq~b}To~x+!%(dCp;jh*+#zJ4`Dn=U%y``SHUJXGpjvSgd{*d?FFzct;i@s~#sK&om z{&im3(R8%QgZ9js%Ok5Cs#*PPOjDoD{yj2V-tOnOs?x4gm&aD&v(}dzy~S;}-T1cSy3Dz@BEIz9Pn$e{+<0}q}J?5X}= z@A)uq_E#9Q>0U}p_x4%x$f)_wKa83Oh~rT-YL22&a}ZcTYRVx^zdnJ;Rp4y(sPlCu6)D>=2F-r@p(SqbzL0aX zF}7lTchofqBnd9-H*RitVzBkHa z=eY)djk|EFPS}^POu0DkCF2VBwwf*XLAeb#mbHCJpRLsUp*?6T$*t64wmDl&t<0^? zQErQ4Q@K%YeYsI?t#x&|QEruE`6Hv;;zvfgJh>a0CwC*KQ17sxM!Eeo%I&97Zq7gU z4ilc(JCuJSFqWPOjFTqMUOlYD4-_-h4Msz={C#V$Ta&H>Kz6>p?7eN zatYRcj$Th3&%DOt*-VgH&pf8_ zC|Ac?OX``|N`~OJj_T@N%8u$iX`amls>k!ZNb4N}EuQvf3C*nYGb-Z_mGkc2uu{G+ zIq<_*R&RLydi~R$)t-y|XwI=4t;|VZ4C#DR$w*l|{N+`hxsBm|3eRV`tugbR7Ctl3eu@0@?&X3vM`rwR_}ucjOZ%UA zKkn1wl((ntPP&RQ8ST}*ojKPWe1}1v6D_suN!*jLSG~ue_5S6b_((1F;(FL>-{O4Y z!!@wUu|a*}!{yJlu|{2gbJ=rkEVr(Z+TbSwh9J7jDXosnpKD`*+UhnsSF(>j?U_Zb zZY#CAt<>taQmdQ!kF9Rp6I-43Tn*103vFuKQmGHI6qchs-;r-GuobBLFt;4z7-P@3 z<*Oc3gSlmYnxAgZ=>LRPCuK%+%U;$#jvh~Jb!m^ZxF z>!Y^1-cM|G{XBFxQf6y&%V=w~t!cSdCr|MDgj1{Q;^<0uW31BZx{|Vz!rU@cZFOqh zI)c?!$2H6KTw85Lc(PaBT0`oY>(vm{+EGR7nb#a#&wgq><5>?s(ergA-W=0zMF!0& ze5gzdNR2D5r_OfhS@wmpJ;lT#&s2(g(LD9hc`4?6n0E$V92=c&_6|>t+cbN`uV)5w zTU&kU*N^LEf4l4KiQ22*U(jXUwa$w7kJ$yGfhS`pd}kT`)1&jwvhTjW=uv$6{Uaae zp1&O!zw)n<72Zufz38)5)kp7reRqd_Z~9&RaYXw+x6SQ(Z}P(lgNxA4+}qcMvV}7_ z&$OBMQ;U+HrSz?YHkw&oNn6JEFQQ&%l9Oqs74@PcFzr-EjqJm>;xgvZYLZH049~b| zRZ)@VS1oytwUg#cwf6BH(ko`#Ft_6GL0f3n#dE1EL7VM-KZC!~vr>9iJh2(g(^@B8 zH~7-CyUFC|(S|u#&=QWfl{QYLlr~Buv_yM)8+UVh&u5(XRk;RdsWs^8H-juQ6J}Yb z@-?Q(mBdM}1iLiFHMV4!oawoS>V``Q0j(B?qTL)>CbbYkKtWIMu zkHjGfZPl~3Rr`WAYG2Ss?F*iMVqcI-XZ4o*34Zh}!Sy5o&rnMG_$FRX4|jyyBWw}Y zo$4L?a7P5GNM}!Apq`*VwL^XmjrkzvmUM4ZeTI$s9=A!pr@~`ca_M)Y_MLe9Vocok zm3KY(VeFoprz5joT>Y_U>ndwDcHj6To+Ui!?HTjKjKv?!?ww{`b;!1s$GLaHI=2Y# zayR&w1>V0+2zYlJ&kbLkl)lP)XUt{a!|lgTf90F|TG^@9gr&;D#)(ToLG zZ#TbjarfY~0U;Md&h#0<&(5{GAcq`>%FPeoDmOoT!}@x;`Qd)YtI~t-k?- zkE{R7)nkS27s@Iu@AqG?9vx3yJ(h2|+UjwYx_achHm=oUPe(6%FI(>?t{#&e-RWsz z4`=yp4GXd)S(B+P&|33vo)#wDIi;^x?rC9tN62ISibYKm_3CelE?1Z3`;}&D3y)P> zc&ysOV<@+!X)%BEv`}}W@^o#qH(DDzSAYYlz4ADzwbNpS=cYWL#h5v5?yTb%4ZQ|m z-2PxkUcXj-dCdG|!Iszo*Yd9B{JikWjzzBo_1&`d$eTs$uI`<9CH~f&ZTor5#Jm#g zz^FZA5Bcr=wdIRR7ao4&|4sGpDyBa@w`k^onitQ%Huv1NX6P4qK6}7_-v`D}XQ zdyl?QS_v!3u2X_sSn!tN(NMRI?l zxRUOxx<66eNKY^LSubWctDGaBHj7WpEsI%62iKOdPfs2~J=J3cEE~`d*t~kii{Rz(% zQy!t2-=lH8%Z3%Bxn6O7nh_o5d*0oc=Cnknxg?RttGt9Kj#q;`lpE`L#i)<9HM2KO z+{RD7gDh#6>B%?Ni~Qufoui$-y{-Kd$H=gR)@loCt+t?6Y71(mj*%^&c+P%w&ZX)q zb*ZJAwOY9`60>D58Y3Gy8rd7$8p{~T>mhF%7yGF5(|48NZ|=XU?>a2_!m-dBKmB^R z#@BNjZhGa^iRvR(uL&5Ye4CAS$joEz$m6Mdn?hT`8j{D*-{#c1^Px|J%Wo$9`+37t zJ9n)*E)P_ntnctml{ecmLr%DXR3c zA+A%y!=Isz<Ev2KaYqK2PrF5{aO;mG@buF!TS|{F|+9s_& z{Ty2yX0rxasI&@~s{H{yHCaa6bZUiLFO<#toq52y3Hn|#G7!Lg3okKO-_QrkT4 ze@4&@F;ZrTftCnr|BamYLQ_IQ9hK=0s3Dl1^f}*Vs#mVhFk7_wY>+xOTd56kn?M`k z_aAwzI({>!cV@M|shxM!Jl{O~Cw^8io!?cN|NObN>kG%}7Y!ITqSb44{J#p{W~f}U z*Vppa(&#V8mQ2F>(7kP8Uiy~qVLM{2K+owIDcN5}(iV?37e_=I-C?GjI$HrY2b z!9kmBn~CSrv`tU!LsF>^88Nfdox?S_cTKv!wF0f-dat1Oq?f)*+xDYnp-VGI@N6=~ zvV_|O&nAi~y?uNhOE&lAm*^QFAH|$KxeweLs%kr$uAb^f^^m&ipMS++#}moUrG43AbNA9 zzil`5-D(Vla;v_*WKrK<$_u7rVtTkzq_?=ak3U-0q}ZZT8ANY<^Ak|J&5?8|eRsyT z3_E6EZfR-bUul7Mb}lu}3vyxzX-8cYE56D$>h*H@C*3yGN~ZKJ^kh257L~LuqdBEr ztK>lZ_mKF>6!NvN^%{~wTIn1Q`1q?UdvWXIC4Jy z9dmJbf1;@N^a_;M$kM6AW4CVxOgMD&;I*pN)_m8rU|t}%4}QOk+X}y{MeW3so{rNP zGPju5W!z@CjqrP2w9kY5>384!Y~;hYYaG85zb9qmv$3anjNv(4rrOs3GjTzdneNvi ztTJ(~T4&}^>*JFqJh9ffl(bqO^Eb85eOFL$+|9oJ$(G?s!>Md`XYg88<%jq%1YgX+ zdnvjgzC*=?B;B4{kV>_u=*kn8Y`K)~I$lwa=kbA$UXBrQUzO=|yyRrgMU5E)DS1($-pdZTC04f~MyGk){TZ(A3zy7NlMBJN)$=_3ia- z4TPiN^_P8`v7Ey{?tkDD`a)8dv$s`3_#FIzsVvQ-4*|Ae4T~LrJ<_7GGEH zOR1xa!eh|s^g}`TArz&gq?v4byU(dgFz;(s51go9LE*_051a(QUJ32XI@Q6$vJvG;Uvw-IT z+(SpvlM_o+XmET&E52g4`R`}++;b_FEgi-8;rh|sMtz=|bUlH717!2KD0-{KVh9Y1 zNo>q3R=yXopIFoCoed&6Wz7J6zoNTF+7;1eg;fwTD8QOaX zryt=v>Gtsge|j59(Ot~IJ2y$!|BB+eO}6;Z_^RlBbH>paH+HGmjbe27rT5}YHnVk? zdN=2yF1y?kAQR6@&B>RBv;sPnbKM`;cE|#y;1%_xX_rEOjTo_|c3= zE-hXy?6K1N3mhgB|ML3*n19jO7qHECDxKeT*XCcP1)F3ZbpK4;&1F5;tLrN5%@c!} zk6-0>KTbQ3zhzm%a_bVF-?-I@+i#xqT#&dhVPUtA(;IgQ?y|tXQ01HYP@O`f<7c#% zITd|+ct4N08zZLAaqv4Z%nYAvqI14G-7(I2_lNfss<~w1C=Yb6ZL3d^WpvVLYmVFO zt2D3Nnk$+6grSmqrcjHS?88(ASuT_voSvODnBq4mrYk9>t>itL`D$s%JS|0wlc&bn zY8jZ+gI8|Fv~DYMyzVDnw_ho3l$meMw=h5CE zJDqV(ekaP=U+TEOyinHQa0~k}qUTsyX-TWJKZ#6jBrWNlY>7_#EZr5;)pIshV@#s* zPg;mhp53;t=%<1o1^wtn%9WtkXS!4>paHs7`ft|ot=Ah zSiN)4x$`qV>2v?=@p#>4nIC#G_uL-%-U#|GZX?`2Sgu%A{RD;gg>f7y4W2HN=X_vl^zP1$W zF`A!nyPtKrkE4&huT6U+koMVAXfN-ne2MB-{f(90bVMIH;;*~;2jSzs7a#rb?%;Q+ ze^HO`?&x9fVe6@;^6;+5AsnAXZ_X#noAVFvzVi-_PjqynHwu%~kwCwx zqP->Y;I8pa9B-p1yEKnekAHCYc}hpiXIF=no;KOUzeUGuKHeAB@_FDb_#GXc?44|# zC7)O6yjuR%-*2&LzxDFq?p3-jEgif!#pyh_n|X-)H?0rkIg-Xk-%VjP4}38zZ2pGf zSK~Kz{G)#QimF#Oep{#K!?qEPx_rI3`ZE>wpV~d)^zwU6Ygopt%xvTMc=6f&y36-J zKaujy^nT<1XtJSy?cz%xo!Qp#wLi8@`D#U3-(!)?XyX~uO-@f$bQftqNPX~Ux;6VSjt#0Masy)I|ecO&KQ~XQK zj^%W}i(fp9c6J`{?EMJwG3Kt#DlEtG0$`U){aWaP(5Y2BErXBRb9g zYKZPogZ=H=Ox(59GJ9O#!nyap_w?GH6m0A{r^xf2;jP!!DC~9g*f(8tw7}wzK{t_p zS=Hx5ouZs||IJp~<)QQZivL!TuEOv1tIi%C#$5Wc{`++v2CqNq5dA_rK;I-Fp1&v1Zhcf> zFZym=!tr&U4Jk=agQ1?0{|Tg5hbYBRU;cY|U6Rp?p@GOcB%3ORh9YZ|j8P1YMAjl1 zs~8%KtVyz&VrU}rDU!_6JRhKU9t*`h(naM2)SglG^lQnW^hP5&F!f5kwi!mbhW0rf_A z6Ow1-e;%t6GDe~bA^9SOkOGlHNTEm}q)4O?GFGGzGESrrGG3$*GC`yeGEpQ5nIsy7 zOco77ricb1Q$>T2X`(?$v1kx7T{H-pAsU3t6b(XVi3TCFMT3wzqCv`AGzeKB8iXtq4MG-)1|f?@gODYnLC8|k8X-CQ$^=Knl{DZOay3F`@OZS$i^*X^ zRvGyp3#){zmZ(C=8j(WCT9HD?I*~%idXYlN29ZL@Mv+3uCXqtOW|2b37Lg!it7s6i zO*9DEE*gaF5Dh|}6%9gmiUuLOM1zpsqCv|Tx91{&fj*A8%ABqMcABhGbABzSdCq#pgPeg-|lcGV$r=mf~DbXP0GtnUAbI~B= zv}h1=Ml=XHD;k7+AsU376AePX6b(YY5)DGmi`ED^sP9hoUvUD>N)2yngk0u6hHrg^=$>3L!s;6hbbF6heL!DTG`SDTG`WDTMqaQV983q!99pND%U? zXb|$7Xb^HmGzj^(Xb^H$GzhsS8iZUI4MJ{+1|c^^gOFRILC9^Zl?ss1arqd#k8_)aCnJCXYk z`h&2Hj#9~BFzAf@@9KScHDlCC?7F0B+Up5jhcr#gy`XE8rfGQv=vt&{T3!*lCTW_M zdqY1(nx^HIplgt(X}J${b<#8~uMAy{G)>EWp{tVSb&Ux|6*ee`W*C8NP!|1Q1h7GQ z^oQZk24yk;h94W0%Rm@rHYl4_V3^pTd{%|w%LZk%8jQ+pP)@7E@F9a&I5l8YVuNz} z6bx@RD5o`HRAhs4S_?)6HYlgHVR*4YIjsZ3lMTvgT^L3-D5pU%3~W$NgJI~|pqz%l z@F0WNIu;l@HYlf|FbI&!27`xA{}ut_-J81>y-uSjjc2oAIxohHDQc)Qe(fg|H9~x$ zs4=uq)C5{63WpYoBA|t$NNAxb3R)I4H6b%p_o zy1)QMU15MCD-2L%gP~DWU#F+Ps;*GB37iH(Q63{@*Lg8tOi?$TF_`{Lo7xv8A-+(Q z3@sFOhZc%@Knq1Zp@pJe&_YpfXrZVNv{2L+S}00^21Wf~fTI5Y4^{Ua-gMdjeK;Xa z1EDl2h^V-?xED@vEAG8Dh0aQd@zdBL#}O3ltqCP;|6F(J=x=#|ji3Cs1^}K+y>TMJEar zog`3nvOv)(0!2LpicS?MI!&PHbb+EX1d7fSC^}21DcUPv*fj%E{w$kydxxSi=~{Gl z_9M4qY6e#*jpy+Rb zq9p=F{|FTQD^T>GKvAy6|2@mEJx9w66txg)ist4EM`u9FTcyj-7oljUbYUvAC?#J> zQK?1o%9TPRU z7bsd%L)`NCs5Q;plEr4q7?*+Rum{&NuX$DfudCeidGdUT1}v6b%CNa z1lOW91&Y=ZYKn?23S%=M<;Cd>iuEmO&-C|7*P^vsl#;KcXuTH2msbfz>pLHcHn2m{ zhIT00$PPst+o5O^I}~kdhoa5wP_(%niaOgAZ6Q#!r9jbE0!3R36m26=w5>o<7lER# z0!7;i6m2h1w1Ys=jsitH2^8%tP_&Cc(XIkTy9pF^6DZnUplA<)qCEwQ_7ZA}I<+W# zmjNl?nV#vd8;Zte|Lj?}cZ*W;l@#sYqS$)%P;`Lvq3A$66dh!TqJ!;Fbch{_4z)wk zVRk4w+zv%Y*rDi1o1*RlMMnt~9W79Fj6l(`0!7CO6df;6bb>(9i2_9@2^5_yP;`nw zQ4fKlQw54n6DT@epy&*NqB8}G&Jrj(TcGG1fueJTnxcJM6gJ9$l)p&VqWwbAOXSc$b%k5Bfg&m5nv_nyEo1#7f zMOO(FT`f@5SD@$`fud^#imnqVx?Z5DpFmN6fuaEdMFRzjZV)KCQK0B1fucbIMK=o+ z4HhW6MWEjYq(v$DN{a4mQ5>>%C>rj3 zD7woIMI-D`G|~=5qwG+0w;hT`+o5QT9g4=(X>R0!5z+6n!R8^tnLMT%o3DYKuaPbu&e~6*D-`g`(%v z_y2s+qLh3kMPIfkuC{(C`pWrG^tBy|zOh5mw{|G{&JIQ2+o5Qo9g2RiL(z|RDEi5! zXpunC&jLk@1&V$VDEd{P=r@6){|OZRE>QG`K+&H9MSlqt{VhNQ#8Ltp<4!|JT{-fSrCeDP8X*7LMi!5ipquJsT+o( z*3O5b20IkBu|rX#9f~S;D5~0_sL2jRZS7Fh&JIOO*%Y-GC|X*esDnV!G6F@*3KT6T zP}EVNXnBF66$FY_6ewCrplD@*qE!TnRuw2(O`vFXfuc18iq;e;T1%j4ZGob71d2Kd zHAO88g&Q*<{qP_%^|ing>v(N;D^TMHCzBT%%hKv5TgqOJl(+X)nHFHp3DK+%o@MLP); z?JQ8Vi$Kw?0!6zC6m=6Q+FhV%4}qdR1&a0(DB4?~Xdi*1eTAB$^$UgfG9cyo=~JN% zLeX{UTC`uGlzb&c2NjCHZ5oOWc0LpxVuzwb?ND@>9f}UOL(vg-C_2&(McwUCbd(*6 zj(x*ZPhN2x3sS69Goi4n@7}P;|K+imtFj(Uo>6>TQRjK6WU&$__ja9f z7bxl{P}EqS(1&VGFD7sak=r)0(+Xae-2owz! zC>kcz6kS{>9Gd|tKa${F5{jNor0yt`lCPv_M4{Lx`<0B%|Bg1&`A{^<4n=p{p=h)n zipJQXXsjKI#@V50yd8?}u|v@Wo1%LKitZCAx?iAZqCn9D0!0rB6g?zR^sqqDB!Qww z1d1LND0)nw=y8FfCj^R~6eyZ3Q1p~Q(bED&Qv`~h5h!|AplGU4Q#8C#7@q+t4@rvd z3PmH+c&<=NzLKIB3&mHnU&Pt0=q2Yv(aUxydc_V!uiByLH9Hi&Zik{b>`*k_4n;HU zQ1qrv(M*A&w*-pb7ATq}Q1p&K(Ypdg?+FyWFHrP>K+%T+MY9EpJ`yPUSfJ<=fucDA zMV|^3eI`)!xj@lefub)2islIv%@=Blo-Y&@W_8 z1&Zngib?`SErpt*uL^}tG9cwQ(PpF1Qq-odc;I%SsL}aQRIx)* z)ec2Xb|`9VhoW|NC|b%6MeXfSw6qj@OCFVqyZt}9%U z0Vz*S*P@2H+B5wP(?_%o>PpF1QnX23ao7%_XjA7y(Pnli+T0FBo$XMxg&m5vv_sKW zb|~7~4n^D8p=ev1qAmhOT?LA^6DZnVplAnyq8$Z_b`mJsS)gbafudanigpty>LyUM zyFk$%0!4cY6zwHYw6{RfJ_1Gi3KZ=pP_(~5(E&nD(MENJsTq*+1KF(GI22u;E=&j3 zm6ETd=+L_2=R1X>!<-LAhufj(2s;!VX@{cjb|^Z^4n;@Xq39Sp6dh}aqT_6eju$98 zL7?bFfufTHicS_NIz^zUhd|M(0!60@6rC11EKoF9py(EXqFV)uZWAcFU7%=)K+#ZvqG19>cL)^SDNr`*k`4n_Ca zp=g2~ite>T(S3F(y5FW~qCn9D0!0rB6g?zR^sqqDB!Qww1d1LND0)nw=y8FfCj^R~ z6eyZ3Q1p~Q(bED&Qv`~h5h!|AplGT<(Q^Vt(*%m17ix+|))fY2K+0F9Ytg7s^mzL0 z`h~hu@|6_5QdgX`M<{yL`B3zl9g1GJL(v;{D4K4Eq8WB5deaU?Gwo3HmK}=Twket= zQ1p&K(Ypdg?+FyWFHrP>K+%T+MY9EpJ`yPUSfJ<=fucDAMV|^3eI`)!xj@lefub)2 zislIv%@-(IAW-zBK+#u1P0>qrg%2_y$+0%l@xtnSNwgiP_)qb zQ1pWxihi_1(NA_LT4aZ!pY2ez*bYU%*rDiGI~4t9Q}jQ9qTdCI{tzhoQ=sTCfug?! zik1iz{UcEHuRzg%0!6uEJZ+~aFHqD%pr{~FR3}hW6ey|}C@KjQwG=37B~VlrC~7U# z6n$G)SbpzJQKe-D=etmJPWp(}P%I^1Nl~>}?6PktYH~glwY5W0J3ACDWrw2nb|_lf z4n-a8P_&F4ik7uQ(Q-CL9R-S(7bsdmplC&bqLl=SRu(8)MWAR^fuhv}idGjWT0@{{ zO@X4d1d7%cC|XCLsFOg^x&lS(2^6g_P_%(S(S`y=8woW6kS;?Rt^b8y`2w5ee6(ll^u$%wnI^0 zI}}}GhoWokP;{LgimtaqQ9qla{sKh<1d0X<6x|?DbfZAgO#(%O1d47JC>ktKbc;aI ztpY{22^8HfP&7oKXsAHZFoB{w1d8qyC>kzMbeBNU2!W!JLQT=-#lmJ8kn-^KwCsvd zbYQv`jVhLsucT;fv3T%dp=g}*p=i7vite#P(F8jb-D`)U`|MD3za5Gu+M(zHI}|-= zQ}mEP(Zd2olLU$$5h!|8py)AyqQ?b_o)9Q{QlMzEK+#hIMNbP9O%W)1Mxf|ffugAb zMb8NoO%o`3UZCg&fua`$ie3_GibfX;Ju@KX4brDVV?xo-+27T@Tr4GDNzv=Y;+;o? zqBoomMbqt2G{X)>Z`z?~rX7mjvP03^b|{)2eJ)TmSD@$%fueZ=Me_xU76=r5DNyv4K+)F%Mc)V% zeJj)yy;>|x%Yc-#AK0F&do2{*lSqA6EG1t_(T~OA7u`eAPtJ#;MRq9q*$zdE?NIcK z9g2RnL(y+`DEglrihj34(H}NNe+m@+B~bLYK+zI`qJIR6{uL zicU(OYFFw@$yZX;uD-a|F`;NF=R;9@I}|N#hoTO4C|br2Ma$ZuXgNC+b+kj#@^&a% z!KP?MfufZJidGgVT1B8}Re_?_1d3J{C|X0HXib5lwFHXR7ARUrps15T(YgXf>j@OC zFHp3BK+%Q*MH>keZ7fi&6c+B5x|)6@RV>PyL2QnY1# z@yz2w(N@lfqOI*vw2d8#wzWf17dsSnwL{T%b|~834n;fIp=d{&qMZbab`~hwMWAR` zfuh|6in<9D?JiKXhd|Mu0!4cX6zwfgw2wg1z5+%22^8%wP;`Jm(SZU*2MH7%EKqca zK+&NBMTZGBMV;#lgEJuI&gp~L7NO{b^v@xO*O!v7r0A&n;-e>oqNAM;MaS5o=vX@x z9cPE4TU3r$EtV0!6(9iY^ywijJ%=%+7$6 zJEY4`_fS+!AJML;FC|||(N*=uKTirpS34hy`r4uB8aotSYloui>`-*Q9g6zdp{Tzd ziU!!BXrN8e4FW|s3KZQWP&7!O=w^YU!2(6M2o&8aP;{F>(d`07Lj;P33KR_!D7r(S z=uUy6;Q~c>2^5VGC>kkHG)kc8Zh@lFLQPTc`ofAQXNpFqYf+z2^nAJ&jj1msUrEtD z^~LRagrW(~hoXD!P;{Riite{V(L_5GJz$5T2klVwkR6I1wnNb*o1#YqiXIgxdQ70` zae<;I1d5&%D4Hx#^prr+(*i|P1d5&!D0)_)XsSTba{@)v1d5&)D0)Gl=tY5|mjsGl z7ASf}py*Yhrf6J!;lvC`xlg+Mj1NVBr*9K^t-h3eB}Fspi`SeMir#cS6wS0l(OY&X zdfN^~v+Pjxjvb2LwL{T+b|`w^4n-f>6n!XAG+UtPBY~oi1&TfqD4HWs^r=A6X97i^ z3lz;2DEdO6Xr4gPe1W0`0!3d66n!O7^tC|IHv&c93KV@OQ1rb((L$l7=#BcqeHoDQ zuIVG%^ib54u0=o8my)lf=;!+4^fN-yV&_BAFLo&U)ec3!*`ervb}0JY4n=?1q3BOL z6#Zp~qQ7m5mIxI6BT)3OK+%5!MY&QuZKo(NP}D-8s31^OCs0%rD5@7IDhU*|6ewyX zP*fHuYAsOIAW+mspr}!xs3K5Q6)0*FYKnfUFD%M{ln+SPqD7%-zoe*bsg!&rMN5~8 zO=pLq4$g<7W$aM2tR0G$vqMowI}|N%hoTkiP_&{QidM2i(aJVOs|XaWDp0hVK+);~ zMQaEYttn8nmO#`=6`9g23bDcV(_Xg7hPZURNS3l!}kP_(B&(Ov>YdkYlp zBT%%jK+%2zMf(dB9UxG2pg_?<0!0T46dfW^bf`elVFE>m3ltq8P;{hFQ?ym7&?^H{ zZkfJzy>%$sHC>CkmrBW3Qgm#oc-Q%%=s4#?(eZXDI>8P_C)%OtBs&zHY=@##>`>Ih z4n?Qhq3AT5qSFP6&JZX%Q=sT9fugeoip~)zI#;0RJb|L~1&S^ZD7sLf=puoliv@}< z5h%J;ps1%n(PaWfy#$Ib7bvlzb&c z*OZF$FAPQ3IvmggqJefOy1@=bH`<}-CYz!`0!23q6b%+A zx<#PqR)M111d47KC>kPAG*qBym_X4T0!4QU6b%Q*?Ey(DI^8(e!NA^$kVqq>pIhOQqy1DY~yzT<4NdbiebVXrdj89&lzb&cZ*`eqiI~2WZhoblFQ1reXiaxMI(T8>@ znr(-ok8FxQ7AX2eplFUj(We4Mp9vIwE>JXApy&&MqIm*E^970)2o!xOQ1q2R(bob+ z-v|_aD^T>EK+*RCMGFOreh?`7QK0B2p{D4~QsLGNNI9QAqRk9NE2V4EqEadON{W6h z6(8>vihgrG6#dT*MZepj=np#-{b`4yzwA)-w;hU>*rDhjI~4tEQ}mxeQLbe?ZKo(N zP}D-8s31^OCs0%rD5@7IDhU*|6ewyXP*fHuYAsOIAW+mspr}!xs3K5Q6)0*FC~7NE z)J~viDWRrlajEce2BiE~dZzzND0(JcnA*22C0|L=vMq~$UlEFyb3PPxv_sMIb|_lG z4n-^4p=c#L6s>HBqE+lrw5lD7R6>JiX<2)we_Q&9wsp%=@|6^IZCTu*Pbk{X`B1dI9g23aL(z_QDB8&mMLXM}Xcs#a z?P`aj-Rw}*&8BE~fucPGiuM#J+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bf=6ev1Kpy*(M zqC*6V4izXmOrYp+fubV>ijEX0>Ml@plt9tZLQT=OEej`SK+3NqI9)=~2F*{{T9%Tp zr09f}#p|vPMJGBRicYda(aClwI>in}J?v0)svU|>vqRD8b|^Z-4n=3$6rCkdbhbdz zIRZuJ3KX3uP;|aP(FFoU7YYaQH^|wRO z06P>7v_sJib||{h4n;TFp=gjDif*<;(O{dRTLg-36)3t*py+miq9FoBLj{V42^8HS zP;{q2(QtvHy9A0x2o#MJC>kYDbhkj!Xn~?J0!3p5ipB{PjTb1oN1$keP*Zem%fjLe zNO|A%V?wSAMS~Klds~*0ucYXKmc@40hoT3a4@D2zq3B^d6iu>2(Ia*!deja@kJ+K< zaXS<}VTYn8ZHguf6g?$S^t3?H6oH~=1d5&&D4Hrz^qfG^G=ZY$1&Uq}D0)$#=p})o zmj#Mm5h!|9py)M$qSpnA-Vi97E>JW>py*AZrs)2bg)K86<$bbQH!&1Fl0Lhh*|L;; zB}MPFEFRuJ6us+wD0))U$PPsx+o9+aI~2{aDf(2P=re($ z&jpI+3KV@IP&7}VXud$v0)e701&Y2BDEeBU=o^8eZv~3J6Day#plG2$(GLPeKMEB6 zBv7`;_z70=s4QQoGgg+Nh3pr}rus3=fWFHlqxC~7HC z)JmYJEKt;1pr}EhsEt5Tqd-wbpr|TP)Fe>UR-mYzK+#eHMePNOmKG@LAk-B7*0S(Y z2Bh3EeM0@eP&6T3ikkqEnm? zMLq0LbgCVSPP0SN>2@eO!wyAf+M(zyI~1L5hoWPXRNuj7u_Gwbxb*)OtS5h>fRq@H&LeW6yL(vU(D7w)OMK{@@XpkL> zZni_wU^^7uVuzwz?ND@^P0{TFMMDINh6)r76DYbvpy*D4qTvEXcL@}Y5GWccP&7)Q z=x%|c(E>$d1d7HA6pa%o8ZS_Ek3i7`fuef_itZCAx?iX%>es3;Cj(O6C7X5qL(!D< z5p80tQu37)J>07J&yY|w$@x(9h#iU^wL{Tkb|`w>4n0!1$f6ul@=^pZf)%K}BO2o$|4Q1qHW(dz<5ZwM4k z7buz`Q1qri(M*A&w*-pb7HWzfY*kowXr`z``ggR4LeYTq9Bo#sQu37)z2B<1(;cDc z1Ls50hju8MZHJ`?Tv9g04&L(v>N6n$!kqR;G5^tnyZT!Er51d8Sf6wMbXS|CvL zr9jbF0!3d76n!I5^sPYAcLGJ<3luFBDEdL5=tqH~p9G2)2^9S-P_$T}=of*aUj>SO z6KaayZB^)z0V)5Ho};}Nin^tr8S=kYrQ|Cq`m0s3-|$fMxAUQBi5-gmu|v_nb}0JK z4n?_gJaZ34c{>!futQP74n=h~MMZ(4dV!*nKv7G9qE-S$Wr3pB0!0l1MQsF%8U>0f z0!3AUq9%c&wgN@%1d5gtC~7ZIw6s7`2Z5qx1d5gwC|XXaDf**T;lT_@`QG$-(VwB{ z_jE1lSS}@BNzqE>;#(s^(aO$;qE+lrw5lD7RUJnv!wyAj+M#GII~1*LhoW_C ziaH4ttt(Kpo$LBL#}O3ltqCP;|6F(J=x=#|ji3Cs1^}K+y>T zMJEb1MLU)YTW3JZ=_eJ{?G%dMP2;3;Dfvo@PAwOY921I8b3PQEZik{X>`-*39g5Df zL($oGC_2XuMd#X~=sY_Voo`cgfk4rP0!0@I6kRM(bcsOGr2<7g1&S^cDC#9pbh$v$ z6#_+93KaDgDC#3nbd^BS)dEF*1&Xc_D7sdl=sJO->jjGX2{lEhlncExAmz={<)=p| z>YYBK^)Hu_ucYY4a`EnQq39;(L(w2R6y0oxqQQ13y2TDfx7wlTHaisEZik{Fb|@NZ zQ#4GV=njFRI|Yh{3l!ZYP&7iIXrw^VD1oB81&T%s6paxm8Y@sVPM~PKK+!z{MH2*y z?iDDyPoU_2fue~5MGpuRJt))^4J;R4$$*p}PhV)fAr$SA&&EULQu37)Jz6e)eNQNQ z%=u9CxE+d~utU+4b|{)`hoYzKQ1rANil*41=ovc{J!?}mRiNlOfud;wMb8Tqy&zEZ zqCnA00!1$i6ulx)^r}G7YXU{D3lzN}P&8ejXof)1n*v2M1&ZDhD0*9cZNI?iZ)H(cl}Z-@~D(oAaS)cRLjAVTYnU z?NGFr9g6n0L(x8VDB9N!Mf=&IXn&ic0|bf=6ev1Kpy*(MqC*6V4izXmOrYp+fubV> zijEX0>Ml@plt9tZ0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(a8curwBDgyRJ}Fal zTKcE6T|?31+27UmXkALalA<$O7k7Cy6rJgOC_2jyMQ7Wg=o~u~ook1p^XyP`z8#7# zutU*>b||{Yrs!gUqDusdE)^*1DNuBoKv6G&qRRz}t`I1?QlO}}Kv5roqN@aot`;cj zD^PTeK+&}VMb`-wT`y47PoSv3K+yn!qJct9(P^ymymqC4zRbf-eSfFT%zkskn+~)S~MsWO;4X)KhnCCd?iIsv@XtiG88@Od?=c1 zhoYzKQ1rANil*41=ovc{J!^-esdgxO&JIP>Y>J*2D0)Gl=tY5|mjsGl7ASf}py*YB zqSpk9UKc2OL!fB7K+z0=qBjMKW(pL&B~bLXK+!CLqIU#}-W4c%PoU_1fuawDnxe;A z7yg$4Dc_mkJRXYnZGOVmx|Dn+MW3`Tc6d4z&2c^yeQJlI&+Jh2xgCn;+M(zRI~2{c zL(zOY6fLkr(U&$wUkMa_El~80K+(4XMc)Y&eJ@b7P@w1sfubJ;ihdF(S|m{Pvp~^e zfudgoihdO+`c0tde*#6n3l#k!Q1quj(O&{Ze+xB5AGI!Qn*k{wn!ZHzaVVOWNG)ky zO1_e!Tto4wXF^fFA)d*Hq84^2D%hc@&JIOII~3L1p{QhsqLy|jYGsF_vQ1HIfuaV1 zqBa6WjRHj#fugEFQIkMXTY;i>0!2#+6tx#9T3Vo}gFw+T0!7OT6fGxE)KQ>ld4Zx8 z1d3J^C|XINXl0?M=-<|bt1=+vA?Z72{|iN%WPew;N<%66N{ZHKD2|yLiq>>K6s={4 zqP6W%w2mE$I@zIUT{{%5XNRKo?NGFV9f~%zDcVS&Xk&q*O$3TI6)4(FplEY}qRs+E zTL=_wDNwYPK+)C$McW7zZ7WdJMWCpwK+$#rMcWG$?I2LJqd?J40!2Fu6zw9^6s^`! zcr61`-X~p)R&S_1(;t(@t_`K+D=FHeq4@2zP_(D>p=d8V6zy$?qJ8X8w67hC_OnCL z{&pxjzz#(R+M(zmo1%jSiVhJdI#i(OFoB}O1&WRkC^}N0sJlSXQ36Fr3ltqAP;{(7 z(QyJr#|splAW(FoK+#D8MJEdsogz@wL!jtXfuhrdnxbwEg~sPIMH{AnI@>)Ijn4kA z?(~LI@|6^w-B8@{#ZYvP^P%WmI~1K~hobZCP;`MEiY~N6(M5JBy4Vgym)N1`Qk$Zl z0!5bz6!j7)x?G^>3W1_41&VqL6!j4(x=NtvYJsA@0!7yd6kRJ&be%xa^#Vox1d93# z6b%q48Yob7gFw-Z0!23oHAQDO6b{OOlz&QJbv!E+<Xiaro1`cR-~wm{KGLQT<=4TZTGkn$(#S~NKnt(g5? z-Ny~3K`W zDEdyI=zD>pg#txC2o(J&Q1p{P(ISDOp9P8*3l#k#Q1q)n(Qg7p{}U+sU7+X>fucVJ zivAKP`dgrAi9pdm0!9A{HAQn83TtLS$`_~ayZ$s3J)W*b|2347ucWBZrnuXTP*m6E z|9_@mv_nz79g0eJC~9ekqE>b&D%+u`wH=BY>`>Ikrl?V%s3K5Q6)0*FC~7NE)J~vi zDS@K)0!2#;6m<|NT1KE~S%ISE1d2Ke6fG}Mw1Pm`=76 z9f~%vL(ztIDB8#lMH}0pXcL>FO$CZJ6DZnTps2Gz(G~(lTM86yB~Y}rK+!e=McWD# zbrC4)Dp0hYK+*OBMLP%-?I=*RlR(kV0!6zB6zwWdw3|RtH=(9z%{GNcG9cx35}dU{ z(G%&z+wN^j$yZXecbnq7Z-=6NoDW6&+M#GaI~472hoS@QP;{UjiVm_v(ZO~oI>Zh| zhuRb!CQx*^K+zEbMMnx0br&c)N}%XyfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMS zQv`~72o#+vP;{C=(dhz3X9yIXDby70*{1ME2Bh2~U5oY#MPDUSXSFFMUrEtvKcVf^;pqrA;aMN{WWGDIW8FC>rW~C>mymqC4zRbf+DP zhTEa&E;|&ButU*EI~0wwL($zfMWY3Z#t0OR6(|}fP&8hk=pKQh2?9m;3KZQZP;|dQ z(L{lw2Ly^96exN~py*+NqDcZpj|db!Dp2&8K+)p@MNbG6Jt@=_-PWeiHv>{WJ$QG_K+$x8q8S23ZweI66exO2py+LZqFDk(?+6sVD^T>FK+*dG zMIQ(heJD^gTcGG8fufHEiarr2nj_Q{J>918Mh2vOd-_7-lu&d*LpDBbQ%b&)qA%JM zzyBx{&2v5!&9_6*0y`9aX@{b(>`?Tz9g4oOL(#W(DEiJ0Mc>;LEfgsFL7?bIfuf%T ziWUhJ{VY(lSfJ<^fudgpihdI)`kz42?*c`C2o(J(Q1q8T(cc0^O9YDk5h(gspy)q= zqFiGy$7R?PscczbMEgDP7S5j2pSloC{C@MK0idx#CsFfXx z%62GfZHJ-;I~29CLs6q0iYj&}s@fDa2^6&zC~7BAw3I+mdx4^*1&TTd6fGlAw5&kU zasovi1&WpzC|W_FXhngdl>~}b7ARUpplDTrqSXY7Ru?E*L!f9)p{A&=v2aKRq>Tp=eV( z6m4dQqRnlJItvtSAyBlXK+#qLMOzCLZ6i>$tw2#1fugPgMcWA!Z7)!?gFw-a0!2Fs z6zwcfw2MH|t^!572^4h`DB4}1Xb*v+J%yU0bs7u9Ga%)S)4zap3Ppnwsl6IY$yZXe zUt{svxuIx(=R?r}b|^Z~4n+sqq3B>c6dhuRqC@RabeJ8A4!1+m5jI6f3KVr0C^|}@ z=xBkWV+4wh6(~ARpy+skq7wv)P829QNucOtfud6cih2kXohndtnn2O%0!3#C6rCwh zbe2HT*#br92sK6fG#2J%K+40@_g(KBiat!F&TT9uUrEu0jm5(JP;`;=q3B{e6kTG6 zqD$>i)YA?{m)W7HmmP{Ow?oktb||{irl_|-Q6GV#s|1R!7AWc~P;`wz(X|3a*9jC| zFHqD^ps2q<(Ex#>fdWN02o&8YP;`?((IA1Mn+1vn3l!ZVP;{$6(QQIa(fN&qwKE{) zztg{fTo8&*O`l!g-dIY$lA=2ri@Sdritcni6b-jS(Oq^Z8exZ`k#;B=Wrw1>?NBt@ z4nw<&rz%=GImXfceXhCD~{cl6jm(GWxuk29twH=DS zu|v_fb}0JJ4n^PFp=hBUihi&|(T_GoKM52q5-9pvplGo`(Jul;zX}xnCQ$T0fui39 zivAEN`ct6jFM*=J1&Wpk6#XMm^shkCe*#6hN<3|+C@)adLZGN1P*f+>6wPZa{FMPI zpOWCr4@IjrKVhqslCPwwRi)T*VJIp)ABtMrp{T(QMQ!X*)M$sIiXDoob|`AHLs45h z6t%M{T1ud(y+F~@0!1AJik1;5T2`QFIf0^%0!7OU6s;gow4y-KN&-bI3lyy)P_(K* z(P{!ks|ysZAyBlYK+#$PMQaNbts~SFl`4hpGa%)b=~JPWmD)4?9TKTdl~VGR6m3u` z9`|D?+R*t>w2>W(Hnv02CUz*=)DA_P*`a82I}~-cL(vv?DB9AdXe)uDtp$p<5h&VL zps0&LQCESY?F5Rp7bx06plC;dqMZbab`~hwMWAR`fuh|6in<9D?JiKXhd|Mu0!4cX z6zwfgw2x3zv|gofZ3d*gRr+_d^+VBVY3y4mC0|L=ftBJti$c*s&WECd?ND@x9f}UM zL(yS&C_3B@MMv17=tw&hb+<#&Q8qlg*I)S3=1&aC!6!jM<8X!r5>C>m*pqEU7zy4wy#qwP>M#tube?NBt%4n^bbP;`$?(FB2_dj*Q_6DYc0 zplG5%(E|cS4+<1LBvACQK+zX ziaro1`cR-~wm{KG0!1GS6n!F4G)JK5Q-Pw-1d2WvD4Hu!^o2mtJfWs&TBR@|15#d; zKB0a-6wOZ8qWP6l@|6^QT`4~IXDIr{`B3z&9g4oQL(%tkC|YQTq95!~^rIb$ezHT+ zB0CiQY*VyYpy(HYqF)7yeiJDApFq*?0!4oa6#Xes^p`-<-vUKT1d9FC@KmR)e97rgqor+D}@Caka9V}`6?8Bo~}hLtEJ>CDQc(| zi%UXL8|On&qaBJWb||Xap{U6YMQ!a+)Xok?OWC2Qy&Z~{wkhf$P_&Fd(Xs+X%Lx>9 z6ewC=plAhwq7?;-RuU*$S)gbYfudCfidGXST3w)M4S}LH1&Y=ZC|X;fXdQu~P69>i z3KXp;)D)Ggg-#iea<>Ghb+z_P|Jd}|_4?IP@|6^ATrKYTZz$Tt`B1c}9f~%yL(%4T zDC%s7qAl!Dw51)2wz5Of)^;e`#-?anfub$~MO_7owi77YUZ7|PfubD+igpqx+F77z z7lEQ(1&VePDC#Cqw7Wpj9s)&s3KZ=nP_(x|(LMr2`wA58Cs4G%P*b#FwQx=bq&y{k zcD+$3Ixbz94ycxrucYXZYVqb=x`B;yb%#11iVm|w(cyL|I>HV`N7|vNyB&&-vP03) zb|^Z=4n@b>6dfl}bi6>(2?9kY3KX3rP;|0D(J2B&Jp_tQ6(~AQpy+ggqB8`F&J-v* zOQ7g%fueH+ip~`%I!~bJe1W111d1*cD7r|fDLSZHcp?K*UOD~K*}fdWN02o&8YP;`?((IA1Mn+1vn3l!ZVP;{$6(QN`nw+j>v5hxle zP&7=S=njFRJB6B}ORI$?8IbbZ=?jfLL(w7WS~R>`O1_e!QPtuK#ZYv&^Py<89g4=- zp=hifipJTYXuKVY?y*DB1UnSnYlouyY>Ms|D4Hlx^ngIog91el2^2jnP&7%P=n;XU zM+J%=6DWFIpy&yKq9+B4CJPijB~bLVK+zO|qGtq(o)svXDp2&CK+!azrf5X9uww?K z{8YO9j0{D~r>FhTS4+uPQuK1QctR-@z2bZ*desg^ui2sKbvqQjVTYpWb|{)*hoU#_ zP&CsHMQ_;@y)95QOQ7f-fueT>iry0_dS9UE1A(Fs1&U@16n!L6^szwECjv!t1d2Wt zDEdsG=yQRhxdKIB2o%i|D4H)&v_PQfOQELd#cJXD3`qHobS-)*6z!ZyeN`>`?TpP0?=xMgJ2h`dy&t z4}qdT1&aO>DEeEVXo*14KLSPn3Kab(P?T$mr|lHw1&Ue-6cq%D>I9040!8%#MJ0iv zmI6hs1d7T+P0=^i!psavc~~~`>I!4n^(k zP_&dCirU+uXlXkXb+ALxGIl6h)~0AVfufEAMav5mtsqdeqCn9~0!1qe6s;mqw5mYS zY63;83lyy(P_(8%(OLpUYYP;uBT&>yplDrzqV)ud))y$+K%i(tp{A%!Q(>uwOwo1e zn?V|zYR~kyO4p)|no7x6QnXo9ar4Gdw7K)4sIwi4wy;CdmUbxG$__K+zonMRy7m4Hqc7OQ2|kP*c>asqj?> zr2J#L{9GQ2_Ds+8M>ds`ucT;9Q?b-O6peL06pgb((Re!)-D8KM33e#D*A7MZ*`eru zI}}Z{L(u~^MGp!TJtR={ut3oyfuctQiXIgxdQ70`ae<;I1d5&%D4Hx#^prr+(*i|P z1d5&!D0)_)XsSTba{@)v1d5&)D0)Gl=tZHX=2@fZVTYnO?NBt+4n=R-q3CTp6wR_j(K|Lp?+O&XCs6dh zK+y*RMIQkyy3`qId^c}OWhN9IoJaykTm6ETd=!d4_Ez5?YADs_HKiQ#Z zksXSDwnNckI~4t5hoWEYQ1qJ}ivDMZqTg+b{tzhoQ=sTCfug?!ik1iz{UcEHuRzg% z0!6vD@wAo$57PH`B1c!9g5o9p=fD46m_se(K2=@TGkFl z%h{o*qaBKtw<%gdplC&bqLl=SRu(8)MWAR^fuhv}idGjWT0@{{O@X4d1d7%cC|XCL zsFOg^x&lS(2^6g_P_%(S(S`y=8wnI`EKszGP*YTGTlhBvQf^FNb!=)|d#1l;dZxc= z+fwqC6m8MAxYCNDXiMiq(N=aS+S(39+t{IKTRRkWu|rW;I}~kahobH6P_%5-2)Ypy&{RqCrt~$J(LjI6D*_Z-=52>`-)~9g0q}L($1LMW+Z9^$;jJRiNlJfuhp|ip~%y zI#ZzNEPv z5hxleP&7=S=njFRI|Yh{3l!ZYP&7iIXrw^VD1oB8g_@!(+ZNu=fRxj7`nuksD19KS z8{M{)eB~N*E$UWl)p5;yu5wTIkuFzxJ$-4Z@_qKzfR>dunYV_@hS`V1YGwa6x!h8f z+bX%-GL=u7a=GOzt1Okvtz0=}>0EC0$^*;fa%)$9SuU4bud>w&x!gvTD_6?pHmkh6 zN-no$rS72`Tuk_h6mpiud>ejj3iIp~8a=9Lr1GmfN&ZrFAA(uO+^7&4=+y#|2cFpB3 zshr*|m+MuTv_~%2yYl;9xm@2$mwj`&>nm69pUVxbynbLVH>grMB$vCja`0if+|bIM zN91zDD_?Za&>-=2qwaWYpbGaFnbuP)}-maY8Gnad>@_4UYZg%DGD{{Fx zl^y!za&s%!U7gDfPhAw?n>~ew+R3`D*%gGw&mm#?N@2)t3gntr3}X8CIRm7H7VtLb+tZkw;B zUy8SVzM6ik+0OZD`n6Qu^40Wvh4#u`N7SJSU%I4oaHKU=?hzM6hG z`myy@vjAClEO zUrj&dsBgad?A+`vl&_|rGcqt=O+P4NP`;Y}OaEK*)%2fg56xH8e``BDUrqn9O=F<(vp!N9}$YWj}v$MV(mExVKR)$~1=&*ZD=o93qFtLeL* zUdmU~x2?REucq%in31ohe>i?SUrqn=_g=o5{^@3RzM8)FJ||yIUp$?gucohlEy!2X zmoL7_SJU&)h52fF0^KDTs!zxt+83&*|DYw7&{^-aAWob>1=OXm+LHoZOlqYIbLA6RUdGXC{d zbM4Q{&YYH=S+91c*s#l$NwZJy%qN1t?TF}ulP!$tkSYnyJdVUL+T z+BM%|nOlZk77F}Jvxn`e&9Ud#tx%z`*H$)OWlDe-ZR&soE;gFUhk!|KcvTE zm9?86i(*5o_7hHOKHK+!-Wz6T>zn2cnmn^-^WlkeUVgb}uKf|&nezn?%^RwZ#$M>tpr@VN1^J~<&Q9gU1v)5?why@ca$+f>CJ9K|` zqXTM(3grt5x%U0zmZrI-8U0?Hb4Bx8s?WeBH)VgyUcYN!c>mjUQ^khOUi*0c?19Y= zP0nuVeYf;jc1t7TmRhY7Z}Y+9Ctq`E^DXtC_{fyn>(qOl9Zzn)p(Xo&zecY8gBhoE zKUc1uDK-pPEqib3@I;oI@8=8IAJSuYjN4rN;QSfcYmzzo`u=Z!tG#wZfBN!5zhC{PPr9SUhO<9xkwMDt=l$0We5m$z z_-?@b_p^uWtL#v^qf_0|IoT~Oj$2ynmfm`7&h^=`?3Qjippd<3Gl^StTG+AqRr+JZ zyrJ2v^jY@KnC@t+PJ!U9LBq2<`c;;j@95&}59yBX=I^_ny8gz^_w(6dKfI9MU+SBt z-M8eg>`~0#pu=Vj9iH82i(>75cCQ^OlqYAeU1Jv0Ee&!@hpf^yajS27_v%68vR5;E z?biEZ$r{Z!w0Q0dA77CX&CaB|InE9Jk=@X$aYG-~Vy0l!TlXYm#fE8D&Dy^ChFZOU zdiMUEy+%*m{^8S^+Z(ep>25Ca!n+LrGP|4U2WU3m&Czk2>#iFQL!Wnk%HBctFE;%* z3w+n+KEDWdolCk#oXra z`;0lSYx869@3*5TW+t;o^Yhtb7iWLUUia&-nmRmt-51A8y3b2W@AyNrOJ%x4&%32J zk6J0aL!+|Xe1|4xe@Kt^zqP-wZ<;&qsr0UrJxF&i%4HX$>?Qqp$5XS?+pXBpwtL4m zx%SUwXVP72w_fvuP$&=0t`f831$C-LSHHPl(4sih&7pKHdndb2r_0jiwOHSD>#x(N z)ZXR#4O!T`_U`fNj912`J6de$^hKM?vnyS8sQJP)FZ)A!-JkX%FMj^+b(T~ToXP?cb$77Z=wRhOAS#Ewj_R0Q`?%PjZ&GfF|;^7XNNd)=D(9VG{0`I zeEP&+wLA94)&I`QJZ5+7+V<6@a_vvf&ZHMJpmwId>7L(z8BlvPKL25C|JtDm1K*rg zdo-TBrMye7{c_pIuylt;dqK53v}%@{@6ZO>AJUD^b)&!EI_8(`rn2{^pZh)cO}eVp zH@(_>`h@K9%3hOykGkjbT>Gxsp>zTIt#+t(0oo&OX{`<7Q8;Aa;p;U&3TMoJWYy+J zp~tMQ*?U8FGiR>!;AOe?2V^JGyXCgE6NPfR`WziMb8aoxH_e_tX?E=unsNKbzs5r| za@g2(Nh~(>z37VUW9!G+p>!{=_p)o3pLtnszL$%$KcqL?crPhkNmkB2XGnMbV=rm` zJ5xW;?q+6t&X-H?+WZ=?_-5a;vzJrfbnhFZ7F?RW4YD)o?bew6zPIcHf3e}%ezRIO zKUxzO&mUQP*BtNz>N+MgFMXQ$ek`lfOJJ@t2bIrU99|N7SJwM*7P z!#298`33#>-H02q_ts?^Yxn2~FQ|5pR?c$sJz6jOLwepQ-Avb? zhp*6lGn+4S47hvn^yZk^v;qFt2f`| z10Q^ly-#Ovp#E>Z_-OXH{hFOgZ|Om`GqsD)29??iy2lHuUA8-Cx%ma{nEfF=m|yz) zYdd^#Z1ZC|ckt`)rZ-T1)5u3&9h=^<>YHvK{l&nfH#?MG(qCRux^j<-m(;XzJP7x` z`&4#4o!})+jYAvO{=QJ2kR5s_iwV^U4&Au+si!x;_^1DT^rqUo;8*uuJEV4@+WMj6 zPtUG$*_oHKGwtVPe@L(UD2JEY@P^LKhkqaY>d5Rh&R+NNy`T81cKC}aeKyUma@psv z>4AUJnYhYjx%u(fC;LOXYwvq4(^al#Q|$${+NAle)i+JO_umhbxMIU+ojWbt{DNK^ zG3NW)3z~P%eW&EwPtDGxd)B3Prr5AaL-vF{9qG8t`i_@WJ9o~# zgKHTx_HAq>nbj`)mL;^Pv@#f5)|nw~LI_DjlC)@%N~KasDn;5PNht|wQ)w64_`l!h z^M1|@E#J{k-{1H9`!_xGzOUywpL0Ivoab5Zow++U@77~WIDW+q*WN7GB(Ky4zPeu9Y+CohA~~E+DeV?$D)Vs*G*hs@KnvuBuB3HLbLIN` z-*A#&_3Va6+!mht_RrH~d1Sxs^kPiQK$-ibk?t<};6eCt*{l!W6q+`DU{telDoZb3&edv{os{CNpgr^ENyhl?WfHJ%erUy%Q<=X=X%zWM!&AS zZI!G#Syjdc8yI~v#0fPFC4#Z>&s8;5_!>b=ZsGF*TSCf-+5BKl194awlgI?&|Pm+ zN@!?{x$K2)4~q3NrGqbye?=G5i$0k&`6PczU)}l053)X|mUW9+*ERB@FRqc3XSrE| z{l&abUg(DF8Z@=u{pOccc+`5Hm}>NTS2al_I)+$ zvOu|Y(#pR8+9WS@)jh>L10$Y3+h21rnex4tx(O#wc=nKPjd1)ObMAdmj-SVsbN$>z znMBjEF50*y$`$M{(Rg{G)BM1O$G+bE>~Y%Qil|OU@#9Nh39^wQCeAs<)cUY)Ux}deMsWlj8jiw`IX~o&B|$ zwEu!0{&Z$s|LJ~NGl7b3DW}uK9RcG6`%76~Ug&mP!hH0Q-cg_~`Zfo{@oya5b3oR- z`1S0pTW{B8_oA&f^}4{{ZgXBplUv#u(nhyi=_a<6U#y*Wo!f5vUwi#kIf%$Mc=*j{ zpL1I6{^)_}qW^rG)5)|twBecW#0#0z>l1cu)mC2g-1RTC_LphP-FHlqW!hEQEz^ar z5qHm@3-*_3pS;lSFJSnP&o`g%ucpKg$H?8KbY#c)AC|feH>gxmxw8+;b64GP54k4p zm|j|-PUmAf_ri?}UUB-qb<_T3dT5Yy=*Ax&ce~lVSMT3(xg3h6m2SD8n3P_<9%qwE zZfa|1`-{t;(&hA`i5nW|l)UIigL35BMRtU*I|Pab%8ZdFdNOYBns5LdC)i)gnesxn zTwgcb9nDtReC9Ksz4uPK!*zMhjnBR*>t4D%ar}aZWXs6Tect43P4G%AWRrfhrWs9Gf;kMnOEsG9_q9vr2uAZ1?{xZo;z$F*TgDqL4sVD!W zj)dbsKe*>Qw{o7mbHzO}r!h%xp(@bET?dU5>@U<@d7%r{*bR5rK}!UxT0>~G_}5)> zzLy!*Z~Z}We@4r0`uY}GowD*y-MM{epxjbv;$H@>kQds?C9Z8ae&Lwali(bFK6;NUnKb+3>Kg4Y@MjKly&yW1=&*z zZ_Ignj`%Md_}8Dm){~UXr|mAUncwKk)%UN_TMcQX3-kdqs!`x?Dtl?lCe z&20?=W!6d?-7)7dA>A=I+Js(mFdYB=wNvg^^}Xo5m+oofPw2@nKGyq7S)E&+nRtur z;_GU;#oWQ%-AQ|cV1F@p%M116SLUQA?Lcj}4bocJvTrNBt-Q`C{(;+mb(gR4_kP~Q zpU<+5TfdMqcC0k<&)B8pg|4@uw4J(TQA2-mZ(jGst?no}b@Wx|`AfUKNajg_GX15A z9zL$3iQ5!I1^a!xTwZ7&7rEhXwccm*dCS3Y{G(sIsuwP@HhSD5zmuw(cy;Hr_dEI6 z-K*s-n=(t~ttoZ5NK0F;Pd|UIg5S3t*Ug#c&TgTT2dcv1_(dzezfleyE2NDsPjlJ~ z47@+cpUseYH|oklTP3Y@iQZ#Y_ix;BlD|an z?AiUY9x~)X=iFaqA*FlszI|kioXGaroQk({Ya#xviRA1)KNh_#&7aGg%iericFB=--SUj4 z&Ep$yxlwJEEA@3>ZPdfN7k%lw;b;2u=~wRT-tv4;+UU|Ov7SYnK3dh?Yh8QZK=%}C zLGHyNe>T&%Y+onq`k>8bD^1=Rvs&lkMQg5{r6*7?T70$q#co}gcas;z%K5FH+dALU z!X4LB1p8a3nY_>qk=)u=&w|NQ^&vnwe!*w+XSh|`?A|q1{7J419!v<7=^{;ZgSK@| z+^JxI&F37Oj$JMfXFlcST~TdxF^zQ3OB1Lwzn?}KInxsTnLqvUhrham#k>c%?UmIh z3)Fqvd9n(|rn)veTpKxWyu9fqw{`ZlS<*|^fn3$^|75j0n(u$|jf><+mF8B$cdkt^ zJy2$+A+L?U+`%-tcu#lRqp3q)^zCv@WNXW+xa#qF-NQQbX$;iYanPj-$rjwb5jmwhB_mqHXOM@W3k*Q+;6` zt65F=GI_3h=2p3SmL2A^t2ezN9bDDGt>9*^NjUzct0sRVBAgbJ8}NJg+5_J{q+29r zbU@Z)L)W!#Zfsq(6&pF!$B=a6uEwq#vzX@eCl>n;ExqVtZ%>lDjMHPr$i!u}o_$Mg zS*?%Q_|LoXz33SSTcr5i-m~!is(!bR&zw_MTf{%Na%LB~Ww#dlX>t8e8FCzujkodj zPi~g(%4(fI^N!nf}+iP3J+T^W-N_-6^Y9rgP0>=jwFiy~KSR^|`i8=*d}~&Ipw0WfNM%gtSBbZ9@AT z^rFL0?iA;*?B}+<{iIvji|))S=})K1kecP?pl#DB)}g@WzuczN(m{E%a_0R9^~@yO zy3y7VqbM|JOvK%m08ULc_VyqHk9LP{tQ z(0^X-P|*rWLiL{)kRcZa0|EW#m6eb!RR4J)30DLH0sZHdmM~OC(SKe!375(X{pXdJ zFhWMre_lxmQ-$h3uR^jP>E*6 zPAb;4Smy-!u!9YWlg14LO2P@jV#VADL5Y##flwUd7b{l0ShQFZdAlO6++kxCk+BL) zwWvkU&7_!3Qld^WYLoPb=1;P?P143HA&tEJev~XOz0*0D@?Xf>ink@PnUqcmwyHoU zj;|0OEFErL{>HWybdCuP3UsfsOeC=&h$;6(TUkkErcDgWx=T;c7G@bdO>6AdL3e77FFX7KqIw2cF)?(2Ak=L?)<%Ay-NV`p|o;qU!>9=WJ zCg&XGTJ_kkT&sS_M7iHs{wL25BgBC z8M|rf$n3$x2ImeQlNCrEG-6m*YUa?av8gFTNA$}anwm2xGdn9aJ8O7WPG(MORz~lf z+|m69k4ViOF=A-HL79Vx=cEqo*ROYG_OR6SwBGf5XQXAM_fAh!m@F`P_=w?I$yu3w zclmf3I6;Nk!4-N?Blr{J0xI4HGEcK^|XhmUAC zB0DQNZ(WSd&GuJ`TO+4tj~F8BJSX*xk(t>SbsRmscTZWCfu{}~ozwgDHjTP9JQka2 zOlEGDt}QvJ_#1k_=;8h9r!`IKrz-UBpEV$J^w8YixtEO0%1IfdhRNpYKX`bq1UXin z(XK;p>1MxnBZdtdFZ` za#~tyT6HfWRSs|$C)I2i8k6LCVM$>b>wi!a4r`w#ABqf?@rr3F=~dSv!~K{dv&rzv zNK9z1b4>NSRn7Bic%|zJsBT@U?)ND*)%CTyS6zmOF8TA${)JAIZsjFZ@%!QC`+L1e ztd{I~>0W7nyl|pdx~et^CwQfW%M$pDkXSD@!(Xk|)rG7p{zO9GvA~C%a5A*de z9%S53l8{;>wNg#D?vldgWjQYWv)%V-HcQ(7EzAA}>;H3{Iwq&B|9qngdnnQ!uC#wT zbEilo0;&rLN=>y&w#)UBdi7Y+t7W%2e$?q?=;*1{bOJKBvN5N|`_uB$ z^kz!$e=60euB$L_d)Zl$odr%V%-zBNv1`P?b}TrW<6we+;IC>|?0Q>fB*Gd zYRyVDZC@W-@QjH=yA11s$78o<{7j;bM92|n&bbYYsA0&$T_CZpB&n_mnf4~DJ`SkiT-o^ z0?+-z<-F3mSyS_#KIUDQ+T|X5j(eLzM*a6)k{)&jlR2Mq*mKZ7dNA;x{(z%U7cqr; zrt^CT%Kx2b)c+mVpI(C870T_uzQb1VSoS}8n(`;th-K@hrd9jTzUlivvWLZtlJmw< z-R|q7h=2Amy&yYQ?*jea!6>m_x_l6$W@vO$s7Q+4_+=No@#ExjtSXm(g*e8BiUj4c zZMwXvU7btIF-fVRqA8)=W81@Ha?`GdnVP9pPyD@WCV7yg&)0sl4*&nUcB&_S9m{v? z|FbTf@@`)X`84nU$bnr>)c+jThwh}h zZTydc(5q=&An^71_W4^sSG)>%_nBvt<9y z53m>Jc_oL}f8GVqk31c5sQ$f^=RZ#<dPAz^1el=n7mivzfqxA&7tDKBQN>6i2Wa3@F)5g z0>8ODKAH>uypyo}(%awv;XnCQKA(W`e}nR0-BK|8PwrUq7U19W!9sb{xJEVo_0Zq> zM8;vik?CI|7UGk_^1jHi{h%<{VE;W=izaa1dnoqXx<_0d*h9tte=Zi2+y&ARzvP&h zoL>Een({`Yd@THrKOB^&qOIFM{&Y~;G%v26oRLBw2U5IR(ynY(NrgEtd9~6CJ#u1d zRlUpLBk-v*r!rpIDo1-J^k?}OTGcrEd3i6uFqE5;>K{49$ucT1=fHxsod0Pzv$o)X!yga1r)7G2`0qOh{;&M< ziyHjBl4)oFSu?tyV=|rCNg{ zYjxvxy!*2W>HHYI5c4f$_X;`M|JG9cZ_T%mtEG^m9kZnJ>eMqd4th)#;j+_#i;e~L&tn{*4wF1+mtyVc;ACvv@Xjh%O z($d{B{^@RByJ6kwUAtJo2SU+GURz` z(5u=~u0`b-_1lfW9^UA8XQICY{6};7{RT3+ z9q9hdoS+=&{*LMD@07>OZ=pCPk78}wStGwswACtSjr_I7mZmadA=ailJm$}XNgP>^ zW|DGv%%9*c}1sT0;3$J#XS5BWD(cQwe>+036 z@z>gw^PhO>-)`_9$%YmLFzKOgS}O%&J$@tE$I`V{*EbEvbuE@baz@i#;-E3SFWWN{wTG@bTj10HN2msjcdIcsdr!ZvQdM)mkrzHy=>IP#%$08)`rGu4cxE}?QEQM z8F}z2BSwr&4|HqOt9QHZJu?EQ_tw9r?Ee08gTqpj!%|b%i}p;sVP4M~gX-t^Fe9&r z?F!7?7A1oQjq=87>i2&1@SMQ|hiCOqlE3uq&#s*)&s#kFPRn1qrg=+}E<0JEYlm}sw`qU6 z-%gCOg_M2FUbR20Wk9=>_6<+A(@^=*5gUTC|j^$et(=D{%Xhu*G!%c769#A35%d^70PV=7qTW8 zmOlxw$OJHuEXj1hNR~!l4oVU8FHN< z)6W?+B0D$lgv;hs>wFRN9LT$fkbTMTgKj6^Dp^DBMFB1HHAv6*AU$6Mwvu+%Z!Fgi zeq}49i_>nZ1vYa2HkFy%x=EMoA~&M!v-Toy6{d?_HeP|Fc)GQaEuFuD<<-gE&rE99 zv}uxl!ADAZl77WUT9b?hNp-TbhGu2vWSx+dJgncy(JlJP8p|4+Jgk0w0l9-l59=#+ zz|awyxykbVAT4CG^j9Eb4j4J6VRFvM}mhZS|(N8*%JYZN>PEO{)tmL6t!w2RLYLO<$T^c3pR+pq#0=a`n z3{TFH@9K~$zqB==e`aoGUUsWO&KvGUzQ*bK9;=ssbZT;b7C3$8xhE3))6BmhRU1`> z{Oi*EtI>34x^Idcz^z;PTgX|ScW(5h?%n(F6E~N``B%eeqt{+NI-ZetLQd!6H~;c9 z|Ee_qqEs$~(Z}rtwx_$^aY37Zty$nwlk3_1>q>SAz0`Co#zf3N5~S;etXtHNVg)PqH(2T6N6=fmNS6e1rU~!`I5UF}fc&{qpj)T4cYye4QJaS6V}XJTZJ6(y#I=@DmE;iDAR_ z>%Q`TLV-LHd>9Ip%pWMPLPyvd3gn4kh0YkH{mB$m5R4Gmgj$j>t=n$iMlvsam;#TKx;&_@~Kpjsmv>X}^1enKy!e z2a=cSANE8cJx%T<@`t4z_BiFwo;IW%`RqZyj!u@NsD81hR`DlWt9Ya9L-|at;>}Ao ze3K2|X*@APVXe(%TWOVcXK9t`>DT<}^oAJMukb5+QXnwJvK(duMVki#3oPF! z$1H94h*oL$j8>W62CdR=tL0r(7^>|TYL)g&w90%|XqEPxZTL1DzQ_0m z*~N6dZPF_1ZM#-!mm#~FPOq6(nO+yIGM%wnW%yZgOxAXNwMs54yP}R?RjZ6&SF7-5 zT4lLATJEk@mit`GZ)=ry+qFu&ue8d1DvJ=>zOPo9&v46$^6iN_er2sPejTkcUK6b{ zpZ1nd(JJ%lWqG|;X}4LcwA*R?8?7?Gx^k${;Tc+GcuTD^-R@dt_(B_gmknQOe1le9 ze_C6}a%h!y8M3qM^qOgv>2=X6(-|WNY#qK*tF&8Zd7>P8bo}XBW&C+sWxT~&Ww{=) zyi%(y*E-8(6brQKq!GM{I(%JiStD*kNH+At8PQBGy~qwbb%2TBTiVMXAy*QLD_StyXD2Rcq5g zV6Nrul_ksgpJfZ1_Q~GM}Py z?$`F&Nm6xutup>Btup>yT4lT?T3ZAH%eBh*an+^D_@%VU_(@u2{O($1_*|{hZms1w zxn|Ius8xnfttnO7&(bRG7ity0RI4o43d^gt%5tr@{Cq9R((VYa%tBjvgN2-k9NUMzBQLBuft5t@t&?@8a zwp{N7mxtDM!@trh!+)||qn>1$UR|v+y+&GPIvusjbo<)yAvQcwu6>l((<ey_N&gXKf$VD&v>8T+6bYZ2jTQEqAiq({dlnLoJWBJjwDb%L^?p zvAo>!YRl^_zhhai&|*$>=j#|*ck!B~ma$qvYf2y>ng(KIUCUOna!>G;Je zx!PWiBbraMI$iD^G~Z}-qpVoX?^`V^`>E!dR?nCHPV-=^cgP0N{E*e%vL9*w!D@=^ z7n)D9s{4oL307C8yZoZnfcUP%i(Bm|8&vZdR%eJOns2hYNsb+wcUUbi8(wp5s~5I% z`68=#wQ>1jtDm=XdB4@PjxM*bI;NA$S6N-v#pRc+#&mPJq}5J6Tt3t4%+p-H+3Myq zT>ijn#j{*K-fEv-E)TQ1_*|DCwYukgmw&XH(c9%#R>x+#JlX0qBD$`RSFOela5>&; zmq9L{ZFSZVmv6E9_E48Uv|4$D%O_avJIdt|R+r?s{Fv3RM!Wp8)dpi-Ze#V*OI^O& z>gvl~e$8t5N|zI?o-)DZbF5x}mCLtTeP^=EA6u9T^B!~gPOICV zaQQQmmq%ND@EMn%vbuM*%faVdZMMeMldX<_!R2eMu6xntH?2lrak+xk z)7QJ)+v@xcF5hi+`$m_)uv+U)m(#5ddCTRCtuEW*^3zuLz3XyltEF27~9#D^|dvfA@wmou#{_|)ZltnU2GD&@+DRu`NrjEtseN! zW$$}eTmIl`SF4luyFA2g< z)$vxZwK`vGJ-ME?y2$v0R-dx^lGV4Y?$RprEqlDH$yOU#9c1+it8=a1V)YTLA6xy( zYK=N>dQGjiwR*AD8CIXO`nJ`gC%AUit=6^L$LeUS_gQ_`>i1TQ)^+U@tah?`fz{bo z7hBzG^;@eyS*>@Xn@$_6y{u+hooDratIu0~)#@RuiS^ucPPE#OQM=UmcC zTb*z90jnQa-DkBbF*FH*(WE*Xm5GcUyhX>MpDMt=4Po z+O@HoYxNqdbFJQM^?j=eO(R?}O!=`^!C%<3eo*IK>9>f2U}wsh@USnX-`0;}0pmss6qwL~k|uC3KE zR`0d?p4IQH{%kd+wQJYT>bX|?SsiP2snwlUzqcB0W6NoEsMXu8K5F$vt6QxWZ|mBf zWVO51Osli4uCaQ+YVmfiT^p-sS)Fe6Hmh%0{oHER_O4xhs{^cFX7wSfYpw3L8tvfP zwX)jN>eW^kT7BK>M^?*sbnTL@UZ_>BSNdAL$m$5IW366pb+XlIRN2ZOT7BB;I;*c(ebed|t3~y>hMZqYSS@R{qE&hP=MO*5YKqkitIe#ov>Mi0*S!~| z)72lX@_59rIr`j0vOK;B#H7n}C*y&XoJ)q~X3A$ib8@p?9mFg7s7P)gML(MnNa>rC z6G)LylcXq2DfsSCQ^))3hZ^MrtOG_!6aRH)-@e&dV+sx(I-*~}n3=7gfVAnlHoql9 z2M^C;iqf$_O1}}qhGog8Z2jK2Rs*s#hsj87PVbhInVXwExbNs(nQWndW@4EIqXMPo&Qr^{;%VOT>Q;=I!u3#mw$2c?_Z54dj4j<`hFxoy6yBwE>rz?NLy== zpIYAp{r7>?868Le>HIp$Kl&gq1BoKZPVtQ&UbPn>kHrG5ZNU2d!NACPxu%t@>wxL? zl-IP;QTL7y1}-ZAcsbyR@kUGx2D)nl`(eDkk_*nad6AgFsls%=%9-zIc}*L68F*Tz zm!vQ3hhd{67o6SFNENdgK^Z()Jy6_;W3Z-Km~ zjZWiBnO@EF^p*Qz*gS~^r?*t5r`t*US5p2ly~Xlc+o%uvQ)+uK@L<%v*8l4;{U?tK z4jb>8&x3(3!uVmlX9VbLe&W6e>SO1;ADyrMtdxHR`?tKn@+QbI`uD257MDj#@qb#& z^z`_{5A)K>zM{h}m+`)lhUMh7?o&EFUGF+i_6>O%82WWE@VLIPAEqZt9yZ=u>EC;d zB$e^9d*}4aa=!>5AAlQ?Dxc47)FdsVNk+pY`P5EYdV&8pYSbVpsY#=T^4U23=~MK| z4ySYs2APshvrgW0bykVp{b8OvCe#U3kRxaEX9s$;-gl_^_~Ux)J z#a-q9Bgb@EdthguF`dVB`Z)8@{)2}CHGAwGAG0fS?SYNy9}eyvGivjwuA{nSch2sl zLtB3r={HJSB=zglZ_ovSU*6h$AQ03cL%XN-3Djx5F;Kh5-pUtUc*>3gzbuk}vj=vS z|4$ewbF8(j?~qwBzigIQxAz?~TVA#Q?zx!0efti%US9XuJM;7lJ1>&x#)_@cx1WqT z%Z=Hoz?g0K?Y#WVE=@b$(YI%(wjFgzbp9EGf(`F$drH?=-Z{1Fsa;O%e45|i@zR^} zi9PlnXw$T7_b%N#tvRqKse6|-2X>yiE%TjBNu{=CKE3Qp9V^mZGF*ufhOl|YWv(*i8Yfh8#l2^|8M86?qB-KwmSniGfwSs~1;?c8#^;3H7o%+u1p3AG#bhh>zCc@$8Wj%gQwbE z_9fTDd5$i>e*0 zyRs@Gr>of5gDNo*L1t!J^K#72SGWQ!FfHV(w5SS&BGNgy`WVmXOT1F>lq%Sud_Zlzl;qgncu zVL4H=bgaJR1kKX329`@}maa9l9IsjW*2r=x&C0d|7vaO58#?}hGE8D-=_v%yaL=~V|FEJzb zIv3_0I2hFoA7LoT$8A-yeQNFU1>l4%)3`dY@2 zewHz$zhw-`vWy`EEMv$(%NR1qGKLJcj3GlTW5`98ogtk=Kg;$n_LLlWV!Jp)ddm?j zc4$P+QA0+0Kg&ShkWtpu49T`=hU8c@Lvk&eA)_stA!96>As1UTL&jP(LoTsshFoe9 zLoTz7A(vamkSi=>$T-Uwa;0Sq8E+XwCRoOhiIy?sD$5u$$ufpawu~WDEMv&kmN8_i zWek~S8AGO9#*k|)W5^847;>#;44G*eL$0%oA+szyLxzW{$RVRxvYdcoM>s=15;bCH zN7NiOA&V?y$Q_n3Na+hTcx!W>^EVhgx_gKb|C6+PdUdtGApJfcW-!g_QwTvMT zSjLbCEn~<-mN8_RWej=PGKM^28ABemj3LV{W5{Ecogs5Vtz`QbyIzkWbDbdv_4VTs zHAf9u>9vxBif_nM*3=AHWzh_I+M*fqj72l#S&L@KYKvyba~92z=PjBcYb=@}Yb|2P z3zjiton;Jp(K3d-WEn$Vwu~XKSjLc7En~=f%NX*SWenM18AD#Tj3FB>W5^qpF=Ufv z40+QshHSQsA#Yj6khd*k$QH{O@{VN;dDk+AY_;qRSrN*V?O!Y^7rwDiIz#T(Ym)aO zYK|JR!^@Q0f8UUu*3=C7z@izl%c2?bp+z&~Ba3Fp#}>_yPb``tpIS6Sc3U(v?EMv&`mN8_nWeoYjGKTE4j3N6i zW5@x^81kcK4Ef12hWu<9Lw>Q0A-`J2kb{;n5j+O%yS0Ftt4~PoTJDduDVhW_E6#+#R zNKY#PiYSntRtCf=ke*fnL=;F*s{+Cbq^H#Yo&xD<5+GKA^t3u4q(FLF0}vxX?{#Vd zf(oRkwE!YW$=KMKVCWSQB&zqkv7w-|=tsS7sU3`{UTV<^LGKHB=;d2fm-c4SiDa{= z9@#8PCYwbmWV0xhY!;=F&7yR&S(HIGi|UiHr~v?r8UnDW5de!C1F)zG0E?Oeu&5aT zi%tSyQF8zmwE$pIO8^$N0$@>V02Z|YU{PBD7PSLlQF{OubpT*dM*tR`48WpJ04(YZ za26dO43#P^7Tu+XqB>^LCRM6SFrt2`Mcsp5dZJm>gZ5_8sbsV0G_qNAI@v5bgKQS{ zB%4KNlFg#C$Y#;mWV5Ij8H>&VV9~h%EIJQ>Mdt&s=mG#1T?oLU-T*A>1Hht802cKH zU{OB+7WD^UQ5FD;1^}>VAOMR70kCK=0E>nIu;?NH77Ybp(J%lO4F@=jP6>w25<#NN zCB}9$i<+xaBZ3k2OD)O?dKb$Z75=d(m-c4SXtG%}hHMsHOg4+glFgz^$Y#-{WV7fp zvRQOF*(|z(j78%BSac--i^c=6XaWF>CIYbNDgYKu0$|Z(02WOFVA0h8ESd_yqG0X%wHKj=LzZ#DZC-9&q{XaU(Qx|wViEhL*ow~)=ETghh8ZDh0PcCuNth-?&_W`izegGCN1z^zw04#bCfJF}huxJ?o ziyj7G(IWsXdK7>~%K=#Q7yyeN2Vl_?04!Poa2CxAhIWY{(Np!&?~P{BXtn6cU_|{= zi=Ga8p-N`aGqg90o+X<_tI1~3b7ZsVd9qowhHMtCC7VSrkjfOS@Z?jEZRfHqAvkh^c4V$z6M~? zHvla97JxFmN z&7vY?v#2Q9EGkAei=t$+s5sdyDnT}jN|Mc@Qe?9zo{UAM0a%m(z@kI|7L@^DQCR>M zl>=Z=c>oqw0ANu?02WmOU{PfN7F7XYQB?pIRRdsA5&(;;1F)zD0E=n@u&5RQi)sTn z799t`qT>P1A}=PiTm*?;qYo6rG44+PV?7qtiHWFRYEiuy@2%=)Q8Mk#q7<@Olu9;> z(#U2}I@v7BAe%+?$!1XlvRTxSY!)>lV^L!O7BvB2QBwdGH3MMLNdPQr4#1)o04!<= zz@k)5h3cy)Z zHzxFx2oh~2p970M(JTtB+7F`IyqTT>3>I1-{OaK=31z=G>02cKJU{MwT ziv|F&XdnQK1_7{WFaV2&0I=vH02U1eV9_uD77Yhr(Fgz*jRauPD1fu5M@*=-2ok+i zk42}NMHlHAEjuQneyK%cV!X`b%%Y2FZx)Run?;w9&7w=mX3=G2v*>cNS#$;2EE-2P zi>@S_MdQg>Gy#A`69HIs6#$DS0kCK?0E?you;^+47EJ|U(KG-SO$T7nH2^G{0l=bb z0a!E>fJN5iK1TmTl`0KlSo0B2EdOlXP-64k%;5oRS+t037TrNMi|!1Rz_W-bH2>^@k1z^#A04%y6fJI9ISo8n@iyj1E(L(?%S_Z(PhXGjh2mp&71z^!~ z02Vz4z@o(OXjM!^{Zflo z$9P}XHH)63y;<};*(_Q^HjCDh&7v2`X3;vbS@a^=EP9D-7QIY1i(VmP(W?L~S`WaY z*8o_w0f0rX1F&c#0E^xLV9_Q37QG3;qRjv-dJBL>Zv(Js3jmAW0btR)04&-Hz@qm6 zShNj*MehT!XgdIlb^x$wC%{?sOiZZsiDHrd{jJz%&7yPl>iUD2i29`#eH`P}Pd1A_ zp}kr3DcLOAO*V@@Bb!B^lg*+p$Y#+VvRU*c*(~~sY!-b@#-eWkSoAFbi@pP3(f0r> z+6%y<9{^ai4}eAc0a$bZfJHw7u;?cM7X1vsqF(@5^eX_14g#>~5CDth6Uq8vPt~(1%O3W0a#QGfJI3FEUFH`q8b1!stLfNS^zAn4Zxz~09bT90E_AX zu;>H;7S#nfi{e6|TSbuQOZsu4A|ZFD|DGO;P7FoVFSRH&&YCtxN8j{VTMr5<7G1)9?LN<$X%y7Gvw*7AosW0a(-rfJK=AEb0ruqJ97@>JPx8EC3b_0ASHT02U1b zV9{Uz77YPl(M13(8VbOoVE`-|4#1)j04y2_z@kwAEXoF8Q4Ro$askew(?g-UB1kl# zho3XdqTTu+dvqwGeyK&5guJee%%V$aZx&rfHj6GNn?+ZU&7yH+v*=2)Su~z(7EK_V zMH9(p(N$zDngqb2$p9>x0>GlH0a!E@fJM^)STr4gMb`kZXa)d_t_5JxOaK;L2f(6P z04$mfz@qB`STqNKMRNgIbOQj3<^iziMgSJg2Vl`n0B6y~q0mSXBzle>i^iHo`e(Xh z7lb0}ms)gd$eZ27EV_;MX3_0rvuF|7EV_ei7TrlUi|!(uMR$|UqQzvh=pM3Jw1kXB z_X4o!J^&Wo55S_O04#a{fJF}iu;?KG7A*r{(Zc{NdIW$)j{>l0IRJ|u17OkP04#a} zfJG|+So9|(VCFA zMSh9cKclUsy;<}E*(_Q|Hj7>)n?)~?&7zmdX3;BTv*=Z_S+t&P7QIHsq748ndL4j8 z8v$7K1^|mT0kG&z02XZqV9{FuEP5M&MOy$^^bP=v-UVRMRsa^g2f(6j04#bRfJNH@ zShNFxMLPjl^Z@{ib^);HLx8jBxlrgA5hS`$pE^Eo7PZu4(MO?(`lS}_4tZ7NFHZUv zeMWn;=yS4J^aa^0+Cw&rz9gGPUy;qCugPZ7H)ONuTe4a79T|(h2Vl`&02ciKz@mKs zEZPsiq5}Xd`VoLdKLN1lX8;!c0>GkQ0a$bpfJKJ@SR|kCcDLHl04$0H zV37yFqA&o9A^Yt8G)}Lsi^N9MFSV$6tkHD9 zSyYN_7R8gzqS9ouD1mGiC6djeGGw!;EZHn7N5-P^04%Biz@mx(EUE;+qRId)ssg~G zssJpi2Ed{u02WmTU{MVK7S#k`Q7r%#)dpbEaR4kj9)Lx409bSa0E_AZu;@ep7S#h_ zQ8K_;R4g_$RRoEit;eEhth>{HTd%HDVk7F8T9gs%-P^`2s!w~fr~%n5YDhMV8j;PS z#$>ao3E3=aN;Zp{khqD}xT>I}f5E&wd*3c#XM09e!wfJNN_Skwc6MW+I==rjNpoepporNxFe zh#=9cB*vzjMLYCZbVh7M{Zfn0j`hB7XBPFMy;*b)*(^GjY!;nIHjBIglS=5JY7G;vLs4oDE`T?-0KLCre09Z5tfJFlVSTqQLMS}rYGz5S}7Xh$nC;*Fw z0kCK|0Ewx9IRGrm1z^!=02Yk_V9~_@XVIClp~UuL(Rum~$XRC5 zdOa46jg6>ZYSHDfUc-)N(G|2ei^h@7qAST}(Ri|1G=XduO(dH|SCP%4No2EVGTAJe zLdK%20a!E@fJM^)STr4gMb`kZXa)d_t_5JxOaK;L2f(6P04$mfz@qB`STqNKMRNgI zbOQj3<^iziMgSJg2Vl`n04!Pnz@nQ0ShNt}EV?u{bgl>zt*M{8zRWB-q#qNxB{rgd zsYQ!oy~{e8MR(BNEV`3y7TrZQi|!_yMT^O1(LH3dXbIUYx|eJg-A6Wy?k8i>QUDe` z0KlRL0a)}90E?CZu;^g`7Ci#MqDKK(v>bp%j{&ggaR3%Q0l=aa04#bEfJG|-So9PC zi&g=!=xG2JJp;g^X8~BW8h}O50h~p*#fEMdL81-xSaiEtl&fd7=VK%4ms+$g)_bmt zS@a_9&7zmcX3@)Jv*;DFS@bH|ELu-Ci(Vs}MH|Rw(d%ThXd@Ym-T+|HCIA+_3BaPw z04#b7fJJWuuxJYai{1fX(YpXF+6us;_W)S54S+@O1F&d20E>12uxKX$i#`Bg(JlZM zeF(s!j{sQoF#wA`0XU1+#)du-L8ABSN$dr)Xqn#We;ON6zto~HV!cQ=vuF?P&7v>K zX3HGS@aFrEc%vg7JWxHi@qnDMSIC+(GO%S+6Ta*{QxXF0KlRj0a)}C0E>PG zV9_rCEcz9IMF#;`bO?Y&0ncvRu_y?@q8I=cg#cI-3&0`|fJI>d7DWJ96bHbfA^v7ve*Nc0XpqkV1`6_G#T5F7O(>X%wn%JaJQFpJ`8Zx)p%n?(s^vnY{l z7L_5JMP3)dgVDi2y9B2f(6a02ZYHuqYLPMQH$MQ3)@U zErLXo^>f!HJ$I+yOAk!xUPS#;iyC^~oYTyrMzlAJ8k5bUCSI%T3Qvg`h4S+@60a(-nfJLVQu;?@Z7M%{jqB8(k)DwV3X9Ao>^}Wyv5hU7JFQ^-s zMJqL&Wd-n{p=sen+Mdy>vq6^4o(S>BQs5jXx>O(e*GRbC9U$R-$k8Bq8 zCu30-0E-3yuxKCviv|I(XfObah5)eWA^;W*1z^!I02U1gV9^Kw7L5d8(I@~GWdpD% z2Y^Mn04y2}z@jk#EV>wgMPmV2bO`{9E(JJ?dU>IPB1m+lUJ9LK7Co=WqRYI9`lS|K z>3P-8GKDRMGF8} zbTa^p76P#7762CA3c#Y<0M4Q-yij`)Bzm6SmW?xu_UN(bb}yoSsYQ2rURE!&=x*AZ zMT^O1(LH3dXbIUYx|eJg-A6Wy?kAf?OUY)@17x%4K{6IS1i+$Y04#bKfJKi0u;@_$ z7A*&0(PIECdK`d7PXMrJ1ptel1Yprh02Vz3z@k+EEP5J%Mb7}R=ve?3tp;Gxa{w%Q z9)Lw_09dpZ;4Hes3r!b6qHpP){+(vgi!vsAMX%7_EP9n}7Of|n zMX!;~q77uT=ykGLw2^EUy+JmMHj&MuH_2GE8GuD^0kG(802XZlV9`4OEP5A!MOy(_ z^d10O02ciWz@lFOSoA9Ziw**?=nw#l0%5yt$D$wr zi(&v+6arvTEC7o<02YM-SQG(ZQ5*n^iU6>vC;*F!0k9|vz@p*+EGhwT7VYsuWiJqm z^nKUZFU_I@dfQ(z98tg2qJ*&5xVKr9NPDxW4B0FyOE!zjkd;!s2Tu^k^op#9e_nO09aHLfJL>jr z3&5fi0a#QIfJMmwEJ^`jQ7Qn7(g0YL4#1)e02b8;IE&)Lq4PzM=<|AYT{`UU^c(7J ze}iyD{ZfmXguN>=&7!8XH;bB)&7zaYW>IspS=54T7PTasMXktYQEReU)P`&pwIyRw zI{+572VhYL02XxwVA06{Eb0WnqRs#;>H@%`t^h1L1%O4}09e!=fJHq3Sad1?i%tVz z(dhszIs<@3JpovBCIE}h0$|bE04(YSa27QRhwczTqVMZ1P&QNPDxWH`y%eLpF;t$!1YsvRTxRY!>w=n?+eEE-70qCo&G8VtaqApk78 z2!KUH0a!E)fJMUrSTq8FMI!-NGzx%4*#Ioc0bo%s0E`+O zO95DP832ne2Vl_^0B6y8;m~doB>I$ozUX|jXuh7&#)Tv5ms&J2>=hYc7F|VqvuG08 zESgL8pxqN~Yf(NwZoG>vQ)O(&a0*O1Mk8DuQF7Jx-F0a$b$0E=b;uxK^_i>?P? z(HsC4%>`i54FD{f2f(5m0a!F2fJHX}uxJ4Qi*5#B(Lw+g-2%X(TLD;f8vu)L2Vl`6 z02bW=a2AaZhf+k4Xh*%Eo?sS@@o(6|5%o(gx+m=Q7-SYLp}kpjFWD@*k8Bp*Pd1B| zlFgzA$Y#-lWV7fYvRSl@Y!*FC#-c|6SoA0WiMIQjL zXcqvBJ_KOVM*uAP7=T5e0I=v&02b{AV9{p)EczUPMPC50Xb-?y^h!9iQUr;9u4lAY z&7#(N+y7-aqJF7G--f;ShMGm+(cUcjo@^HFC7VS*kj}f>DF7D51Dr))heLs3V$sKX`1!^x^7M>W zIucR8)S|KxulfkHs2uIhqVi<3r~=t6sz^4ADv`~i%4D;s3fU~GN;ZqCkS&_Ae%)k$!1Y2vRTxcY!Gt`S=63v7Ih$FQAYq4oeaRDP5>Gk60a$by0E;dMV9^x-EE)&EqALMd zG#=nAx-b&jB!Wbz>Pf7(S=3QaZxbRB^-C?99Pz%FFG2Qyt8ohL&7!NxX3HP5>6&1;C=a0nVbU zBBAnQ#G*wKV<(wKuj!@s;z&gOQj6}3cumKeMfcO*ELuu7iyk1GMGunAqKC+4(K51G z^f1{hdW38iJxVr6A zEC7pE1F+~h02VzDz@jw(ELsb|q89*Iv<`qpF9NXWB>)z^48WpS0M4Q%k zqIbw<(Ys_U+6us;_W)S54S+@O1F&d20E>12uxKX$i#`Bg(JlZMeF(s!j{sQoF#wA` z0btRm04&-Kz@pCpSoApni@pG0(H;O6eF?y#uK-x|HNaW)S|oIr2ohbbmqHuNqBVLf z`X&-lztp0=5$^^00%-q?_5r#09X`=vm0tG3Iebw27pB&02ajpu*d^oQ5b+l5dap&0kEhD0E>zOu&5XSi=qH5 zDh|M+5&$eJ3BaOK04$0JU{PrR79{|%C=uW+`YsasTm*^E(Wj2zn?;wYQf1;I>X%wn zAGb=S(HRJi>i~&q8engs3sYUY5}mQHUNu` z17Okd04%Blz@ifXSX38)MJEEVs2%`|k^xwh0>GkF02ZYIuqYjXMHv7rst>@T1^_H- z2*9F704!<@z@jDqENTjH7L|(&rHLTXmHG}y`8ao{-(1gV&Eg{Jms->^&O2>_S=5U5 zW>IUhS=5GX7PTdtMeWFDQG2pk)PZakbtIcbCzH*hPGl_V48Wo;04(YXz@k$CSkw)G zMcn~d)B}J;rvk9(GyoQz4#1)_09e!$fJJ8lu;?rR7M%^iqFw+jItPG7=K`?kJOCD* z55S@e09bS(z**EhE;L32iS|`-T9`#2>anPITtxj+i~7ZRH(q5H^{2gAltng+29V97 zfn>925ZNpmOg4*#kj`+OO95DP832ne2Vl_^04y2@z@jSwSTr7hMH2v6G!cMBR{@+w znQ@_2B1p7^UJCU!i!xNHNpTVNOD&oj=edE&%_f^g*ORem4gibh0uq zJx(@@o*-k<3IG;83BaP204#b6fJLhSSoAaii=F{s(X#+7S`EOW=KxsrJOGQ<0I+B+ z0E=D#V9`1N7QG0-qL%ifU{_0Txg~UB5$0DIB%FmCG}GK`?!eur55dv z^B$UE79F6yS@a{>Ec%IT7X3^%i+&-SMZc2GqJw0!=n&Z~3KX&XcC#o*#-bPi7KH#< z6bry24}e8s02W06SQH1qq9On+Dhj}&VgM|P0+#(=4h&d$Xu2 z*(|C?Hj9$TW>IyrSyY2;7S$x1MYYIgQEjqWbQ~Frjt5{-9RL=c0KlTU04zEYfJOBH zSd+_vR4U@`^fzc|Q6!>%sYPvycqh#^i`vrOENVwKi`tXTq7G!U zs3X}dI+<)1bt0QZoylfV7qVH@m5fEF0I;YV0E@ZV7XYy6LI4)^24GPi02XBeoJFmQ zg!+ge(G`05X>Ar&^KaOSMAR>}Xh0Ef!W^?`AnnbfL1eRNFxe~`LN<#oBAZ1+$!5_o zvRO2oY!;0mn?)nZSTqWNMcDu>$^l?eE&z*01F&ce0E;dLV9{6r7F`0sqDui-bQu7P zE(c)I6#y(62f(5$0a!F1fJGAkSTqrUMOOi^Xc7R6CIhf&3cy*^zes4Y2oi0mho3C7 zsG@$@=;|U7^-C?fril0A4Q9~{+M7k!lFg!-WV7fxvRO2XY!=NXn?=`?&7wJEvuG~a zEV_Y=Me_hybRz(Z<^!*1P}Nti^rh zdt_!ZnfYWgDK`>Ow1j}7r34f$BcSLl0*aOsP_%-8qLl;`ts`{dY>(dK46QY?QBuBgDr}7vPID@wkZ0LEs8#3i=vO&DB4Xx(I*5HeM&&l9s-I! zBcNz60Y&==DB4dz(E$RA4iZpwh=8KQ1QZ=1py((8MV}K;bc}$a;{+6)AfV_Z0YzUB zQ1m4MMW+asqOF0pI0eMHS%0JPT~QRLzef8i(4l>4MPCQnJ1h}J-*A3W^etNyonwol z@7SW~JX;if&lW`&*rMnMwkZ0MEs8F(QFMubqRRvnT_K?8Dgi~;2q^lAfTHUJ6x|@8 z=q3S0KNC=Ni-4kE2q?NuK+&%R6x|`9=r;n2?h;V+I{`)a2q^l4fTH^Z6#YrC6rBmQ zjZ{FK@95uBJ1dGV>mSWN2y|#)TG8Ku_QlIY(PPdpik`4V(Nnf4dd3z-|FA`o5hP!^ ziz1UPiu~B3$i@~${%jQ42`CC6pvXZ$Q7!_C0tqMzBA_UkfFdUWMIi(fg%VH{MnF+G z0YxqXirfSgL$s$pjQlA)sg~0Y%dYD0-QIqUi(_%^;v?Cc#qFH^??u0dbzx z4?q1xQ91n?ZB~#&`_hVD3$kxpCyM59eo-`+EsEx`MbYbQQ8b?|iWaa%(L%N;dV?*B z-eilSMQju;CZK2u0Yys*C|X89(OU!*EhnI81p!4X2`E}cK+$Rfiq;TNw3dLPbp#Zx zC!lBp0Yw`LDB46o(PjdQ-X@@E3jsy%5Ky$0U@4j%Wcx+|akkOlXna)^jo0JdAcyv) z6@3t7|7(LN+Rph!(GIpK+Q}A0yV#=WL$)aTh%JgfW{aZTY*F+HTNHiDM$sMuiasNt zXfFXp`v@r7Pe9QD0*Ve2P;`iZqQe9f9U-9TC;>&E6Hs)FfTH6B6rCWT=p+F}Ul36A zB>_dJ2q^lBfTGg`6rCYhinayWifmMhp6YKAy)TNs)r!srIkYdW=vp@d$uULz!pV6utm|2Y*BQPEs8F&MbTxpD7wN%(NzM9t`Si569Gln2`IWjK+#PC zihd@b=oSG*zYtJ#n}DKU2`IWlK+$gm6x}7D=yw8&?h#P*2LVO*2`KuLfT9Nk6#Yd& z(L;iz=$jy0vI629s6UB)D~i(er?*Ez4(&@TdKzS(vPBd<y04fQ(zV!;mWODifFZ2x?#C@RJIMNw(CC@RAiMP=Eds2p1qm1m2h3T#nSku8cU zu|-j3Hi{w%D2gJWD4Kwx7y^o72`Gvqpr{G~MO6tXszyLjbpncN5KvT;fTCIi6xAl6 zs15-|bqOe{M?g`10*V?CP}GosqDBN1H6~b!B7$vq6cA@6{awcr!PZy$@9M{*CczHv zODk#-Y!BNeidu4hQ54S>MIN>&^0GxyE4CPkRSHv)>f6HwHHfTErR6eSW+)Qf&=NCmo z*rF(nEsBP+MbR*}C`xCGq71eu%4Cb8;cQVff{mh=2q+p!K+z}yibfMqG=_kpu>=&2 zBcNzJ0YwuCD4Iw>(If(jCKFIJg@B@|1Qbmppy*`+il!4#G=qSmnFJKgBB1CM0*Yo6 zEJXu?ZKD+sXPW*o{y$`(a?*rMn& zwkX=mM$tY3iuMywbbx@Og9H>EBB1Cn0Yyg$C^||&(dPsd9V4LVH~~c`2q-#9K+zWj z6n#lR(J2Coz9OLLGyz3t2q-#BK+)F(6n#Um6m1W-1$?L!MQJ!YM9~BNSoCeML;KQ- zz7MvS`&blR;QXTK2ev5sku8cYvPID)wkW#H7DZRsqUb7H6kTJBqMz6(x=ujR4FZa8 z5>WIr0Y$e6DEftfqT2)%{YpU59RiAeBcSLm0Y$$PP;`%gqCW^Ix=%pSp9B;=AfV_k z0*W3IQ1pm^qQ40!dQ7kseHUzNrGPje>u(XA7ey~>Qcr>%+Lu;jIPHT!5k;m`zLFP3 zer!=>V~ZkxwkWc*MNt4-6gk+UC>L841+qm^5F16o1Qa<5C<-B3=iiA5j#iUguxJ>CnEkqB2hV2YWqG&dXVhAXTC7>vdfTAh{6jddls2Tx9)d?u7K|oPW0*Y!8P*j_M zqB;Z=)g_>)9sx!52`FknKv6>iiW(76)R=&xCIl2UC7`Go!BSMpX*;KYIPdAlqS8+5 zEBzKuHJUpe+Lu=3aoQj46-8doFN#{RMNwp^QMK7^M(MYx^8pTG@Xab7H5KuIhfTD2( z6pbgKXaWI66A37qL_pDG0*a;(P&Ac*qG<#ay-YySbOMTI5KuIefTCFh6um+~(QE>W zUL~ODH3Ev}5G+N5ownWzh;yxeLOnzj?bKtg)1iH7MGKtvX@^A7Le4LW-e8NOH`$_S z5nB{3W{aXFY*Dn7EsB=0MbTSqQM86P z$Uo%yuk`I~Q53)yMGm$o%EcB%foxF}#1=)tY*FN7i=q%Vib4q}3L~H>oPZ)10Yz>C zigFWBl!t(#yaW{GBcLch0YwD}C@M%mQ6U0~3KLLNgn*)=1QZn`pr|+jMG*uPl^~#~ zBmqUG2$mu<#5Ps|aURrg{6eg+(Q>QT`IioHXkS`U`4IbCUx=a#oL?S`DzZgUCAKK4 z%oatFY*7@&7Ddr)Q53@#MX_vA6vswU6#|N?5>Ql)fTHRI6xAT0s3rkLwFoGxO+Zl{ z0*dMqP*jhAqWT0BH6WmHXD*;8_2q@}KKv53@ih2@Ilt@5PF9M2^2q;P>peTiaqTU1) zr4mrohk&BK1Qhinpr}6qMFR*Z8c0CVAOea86D&pE5L>RVl%l2jv8a_O(%&ZX9}?ow zzOqWdMI+dv=q0u&8p#$#qu8QoG+PvnVT+=%Y!rie?i~^eO>G zuMto*hk&BF1Qg99py+jirD$k~t&IZW%%{KWI7}2R){jN=Lmb+dR`h0wJ?(2zw21SI zqQz`cw1h2+ma;|BGPWpsi!F+lvqjMgwkTT37DcPrC|XTG(Ha7Z))G*(j)0=|1Qcx` zplBljMVkmH+Dt&v+XNJCA)x3T0*ba0Q1mVVMeh+%w2gqG_X#NafPkXy1QhKcplBxn zMY{-=qJ<&01qz7sr2eks8=~mE{!0JD5Qp}q6@3z7-|?*|`jqpFqCIR;^ch*?RS-Ytp>=%0Z65aQ6jw4%!)_Q&6eqAQ$V6kTPDqHAnX^b=bYU1y7;8*EW@lP!vV zW{aX*Y*F+J8%4JXDEgIvqB{f>{YF61T>^@JC!pva0Y!fhP;{SwqCW{JdO$$YUj!6A zB%tUK0Y!fkQ1qC9q9+6tJtd&%839HA5Kv@<$`|G+G6|NViy^j%^GeZ2`myMeC~B)e zqxpq8v@fkFAk^OIf+%uueo>T*Es6r!q9}+hih|jq$jKH(A#70;$`(aoY*7@>Mv;qv zA~yj=xd|xBLqJhp0*dkxP?Vp5q5=dI6(pdj5CKJn2`DN;Kv7Wwii#0XRGfgK2m*>q z5KvT-fTB_a6qP2Rs0;x`WeJud|4>^W1;iPq;n+j1uk_V3ZS@6Ps6+eGiYkTLr~fF5 zDsz5O6v-AvQEX8Z%@##5Y*7@;7DaJvQB;L3imI|jQ8hM-suNIDgMgx%1QgXGpr|$h zMRf=$s!KpoJpzjA6HwHEfTD&36g48Cs4)RWO$aDzN8E zA)v@huoP7YwQW&Aoagj+9V?2WW|~y1P>1%V6}1hupS&cB+HrnS)SfMhIpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&YzXb1sCX#^AvC0L5ugxc;YAkJz* z3QmG3%FxfQhlM({FRf^Js6F>pQ8a?{i=vmFvT&*9AGDT5{es=vvs6+eG zik5`hU;IfFE#>^8Xc=1+y~P$q%h{r61zQxYWQ(FzY*DnDEsEB#MbTO|iq;WOw4Q*X z4FnWzB%o*$0Y#e$D0-WKqAdgzy+c6JRsxFNC7|d%0*bZ~Q1m_lMIR7Qw4H#W9Rw8Z zB%o*)0Yx7YQ1lT2MIRF^MT;>QC!pv80YyI$Q1l}K zMHdN{qEAC@2Ne+KG@F96M-<)Bzdm~@)S-Q8Mb|>@Km9CTS4(&@T3JkMXx-E)=IKLB)YC%9zO9G1G2`KUq zP~;_`s1*T4tqCYwm9s3YeWMV;89 z=moYY>dY2JUD%@NMYbsF$`(c4*rKRATNL$Rqo^kVMTrCy^&+4siGZSH0*X=yDC$i> zQ7QpNeF!M(OF&US0*d+*P&9ymqJaby4I-duFabqF2q;P;plB!oMZ*XvN++NwgJ3CY z7iPPlfH(*0?_IYSMWyv)QD&G!`_hU=hS{Iq6GfvqzbG2b7DZ#&qG&8z6pdqxqVa4| zG=VLOCbC7*B(^A;%tp}^0*a;*P&AEzqL&FMnodB`3<8Q~5>PaYfTC9jD4I<`(W?X$ zy+%OM90H2w5>PacfTGt4D4I_|(ET{=U@00AW-IxJQuLGlM&nDO zD7XHye{q;Y`_hWu3bQx)Qxq-d{Gw)E1c z0~#6unPC(FX(+Z6}~;2LVMp z2`Jh{K+%T;6n#WM(Z>W7?Ixh;69S4pC0L49;(S+sS+-9UP0)`;SHm3ImsWHm%>LygQFN2@i=v;| zqUaV|6#c>$MYq|a=vTHVy2BPlzp+KpUA8FtosFV<1Qh*2K+$~yivA>^=m7yme-Tjh zkbt5`1Qh*EK+$6Yik=Wq^pt?2X9N`eLqL%cE?>5z$Rwc1kANZ@0Y&}<6xj(V3Lv1! zL9i746lS}xfH=45-we4fibm?kqFmt)?Mo|ihTHQ#5k(=KUlfJ1MNt@A6os=zk&7*g z+-y;ln=Oj+utiZ`wkXQSMp1qOiV6@=RFHt8LIe~QCZMPY0Yya#C@MxkQE>u_A_yod zK|oPS0*XozP*j?LqA~;&l_j94905h;2`H*SKv6{kiYgIMRGDBY3JSN?RzRGW0~MU$ zaO*4m{rb~eWVl27(u!ik?cJVT*Y)!Cw`23r)>WQ(F&Y*AF3 zEsE-}QB;?JqIv`r)hD2+0Rcq~2`FkrKv81?ikc8m)RcgtW&{*9C!nYW0YxndD2gYb z$U{Jpmw=*H1QfLdF>H-Poe2J6ja>V2h%jY*CcR7Dc_-C`uxrD4Bqw z6atER6Ht^&Kv5q8iuw{z)Q^Co{sa^aAfRX<0Y!rdC>l&a(GUWP(g-LTNd?uR|qJY zO+eAB1QfkSK+zlmislkfG>?Fy*9j<^Pe9QE0*V$AQ1k`?MQ;*Nw1|MB#RL>BA)sg} z!BR9T+~%|?Mg8?R8b^zwr}}|uS-3;{(u!7w+auLK2jP1xTE+QA(Q39RTEiAaYuTb` z9a|KwXN#f@Y*Dn4Es8d=MbTz9iryxmXbS;F?+{S5m4Kpm2`GAxfTC>#6unPC(FX(+ zZ6}~;2LVMp2`Jh{K+%T;6n#WM(Z>W7?Ixh;69S4pC7@^z0Y#q?P_&m|DOw(GYp;Mf z3+soU6{6^X{*1OS+@XDGMTf%e84gi&nDdLGBWzK0lr4%rXN#g^Y*BQaEs9RCMbSyN zDEfjeioRr{=oA4(UlCArnt-A+1QeYmpy+D?ioPMB=vxAc&Jj@b9RWq>2`KuWfT9Zo z6#YOz(T@ZaT_m9B5&=b*2`IWkK+#nKimnk*^b^5SbRgWeNC9zH(T_z3MbUcw?D~4R zL;KQ-ZiU-F3KT`ZaDGvAn=OidWs9OaY*F+ZTNK@8i=yAzqUau56#c;#Mfce#`jdd7 z2Lu%TML^L*0*W3HQ1mweMUM$6dO|?aQv!;f5m59G0Y!#OzHCR4NkEYw0Yx?fiu?&E zvJ+4gKtPd$fTCOk6a^Ac6hyET-3+(=sDL=r)b#&Z6!q3$=?A+U+Lu-o=Cc12EQ-Q8 zzbJCCMUk5=igL3>Q69D^%F7l-`PiZ;KU)+PV2h%HY!nqDpr|kbMMVfGDoQ|6F#?K; z6HpXEKv4+-ib@htREmJ2(gYNhA)u%%0Y&8qC@N1tQ3V2uDiTmsiGZTY1QbOQP!vT# zQ8d9)6yma#b}B`6^-n-TUDj9nOZ8(>jLV^YX+>3C_GY1?s2b-NMb+7&s0LdU)ntpJ zT5M5Nn=Oj!utiZ_wkWE{7De^hC~81JQ9}ZX8WB*`n1G@t1QazTpr{!EMa>B)YC%9z zO9G1G2`KUqP~;_`s1*T4tqCYkw2XkFw+JX&POub>b=e*$AkKyQ;b)vEx~InqmqYu~iq^R7`SXgRwVYoRtz(O# z^=whJfh~$QvPID*wkX=n7DaEfMbQ?vD0+vDqOAlJy-PsRdju41BcSMg0*XE$plCY* zMLP&6+DSmsE&_@^B%tUc0*XE+plCM%MV}B*^eF*Fdk84{jDVuO1QhKfplCk{l*qWciE!oceW_H#}-9@utm{*wkZ0OEs7qn zMbTeu6g?!M=n(-$e-lvjn1G@u1Qb0bpy(L^MgI^`WVq$ab`+Te6!{TQWFw%+pMWAe z0Yw1>6gdbe%0)m?AOS@|1QZ1mP~;?_D1=}s`o(2Cs(?7l=*OblqG*Etj27y4XkS{9 z+im~3uqevS`9)D4wkXQW7Df5kq9{LG6cu2LqJnHuRERB#3bRE~5jKj75>Ql(fTH3A z6h#nFRDyt_k^~f$BA}==0Yzm9C@M=pQ8@yN$`epjfqtg%WZw7KSSa1ui|!SUs_QOw>`R;D5}Z%MNuub zD5}jCMRnMss4iO+)nkjI`fO3ufGvs|vPDrNHi{Y(P}GEgqNW5CH6x&?IRQm22q0Yz;HC`urps4W3S?FcApPe4%z0*X2kP}GTlq8A7#>P)Z{ zRdd@qDj?1%4X3&&%G8fVUEB`sODpQ`whxaGMLjsbDC)@;MTu-t)Qc^OlGvgsnJtP^ z*rKR6TNI_TMNuC%iuw{z)Q^Co{sa^aAfRX<0Y!rdC>l&a(GUWP(g-LTNvF`_hUgx$V14ilWJ!UldJYi=wG)Q8bM$ie6@mqUmf=G=nXQX0k=mEVd|mg^i-w z1QfkWK+$Ui6wM)^Xf6Ro^9U$T{?U@4m5wp~&{oY&R#pD2oc(_^*Up?w+QhM#|_z)EFJ z!?jEO$kuRur@^@%tDo5Bauroy%{g5S)DPjpT}dH^k;kH>@Dr*=GT^q_9MpM_X z6%C`Mt4gF{v~rD#HjK8e&teUuqsv~^FuJ(B)eWP&YhF#m=;ivhwqf*k6|H9&{ah&x z3}cXMQzOF|>iVsTVPv|hH8+frt}!hQW2|eR$1o;uGmO2izQYXTpzECs!#L{tW4K|QaMe=(NsLpj38M|;tn1KN z!#L*(o?sXkTxXHEann_5hGE=x^`B)JcU|w!HjMkOKVLJ9hpsyF z4C9G=(tLIMo9-hE)g55ELl&ufz;t(5qV59Iy?B|r4@~#P;Il~Wz((ygTOJSTmKhbtD0{8pX97*y7hlkv99UX z|53b#rd$74&6=8S{hy_3X}a})SE!ZgezaHJC#GBfmpwX~ZvCHT=wiC{zpdZhbnAZ{ zy_f0M|GIT=)2;t`;(n%E|NF9oOt=0ALWi1e{VzObnr{71^o=y#`rlX^Yr6G6k~PtE z>wo2Fs_8y?N!>%HTmL&FvrV`Dha%>hZvFrCUtqfR|5baD>DK>W+hwL(|DPpSnr{97 zc3W$@_5WRIqv_WFf0HeyTmK&h-ZS0$H@>%#);~BtWxDlG{?3|i{iB<6rdxmS{etP%-#oo!y7hOzu9DHgZADV9c82rREa_7?D+h1#a$mMB}%P{O!T`Sdnnpd67 zFsrB!DfPap4>EIE*Yc*3Z-zR#SuJ#q&iRx=!>lf&l73AM8Nb@ps2MuNcd{MoW6`W7 zuX$TtqFGzUK7F1#*2sTUkGj60u7>YVzE1i|)RR;D=?kqd<5-Xy4P+?%hS|^>1uCnd zuWM{M(eT7ed^gknNuU2X-uEtF-rc09zI4}#Nk8sUw}QHz z_HO(A$awvcYgf0l`fK;I1r(X9TJ^55g<%xt zH0nN!GV~iB66$-K>Ut@P>T_h)pQ-94KO<&^KB`A8^#IgKJvOL^LM!XzkLs_=oTZ5G z9D4bae2)=XL%pCMGx+nS`k1#Fy;bouAFJEhRDaa#^o2%6MW-i4_sJLeRKOho<)*+&{Dbh*TrGU)tc* z=%hiZBcr1RrKKbdiq7bll%5)$o;oBoBPk;~H7+qDb9nFmY0;T!X@gSwCG{VY5#2W> zB{3;|aCB@;VwJ?Wn7G))*ccrnRg4^xHY7DNH7U7&WNb`Sl}P>SDD~>+UKQPcNXnq$ zy;GwHC#Cf3Kji=T)yNo?k@J@5+b_CNdhg-=hom)0OHYl=x-CX#ru%LZ>lSI7o;E<; z<{8l)h9;#CY(9KQVn_A9^ldw6ct&FTM%7za`=7X*MkHmX>RZb&tUJ2T@F6Kx)D4@W zDJ1qz?UOWoP-bH0sG+GDQT>!jL)~4y`wz)fLp}6&XwocEUCopxX@du+4N*R3`eOEvS_ z!}KA{URobi_f374IC~y7-5&K~w7rl%gK5tjWiM2+u`N%OJ;W9o6=3V)u@_P~Bp}AR ztlZXRm6yx%%?S1Cxc_e_tN-6$ntD${^!4(+b$L(zySL8C|2MDf|NFI2SJ6+uU%sP$ z%YNz_=|f4Y6|+`A3F`z_l#{3{9;vhKg(!QV@Aam7j;=z4T%Nl9tsG#hT-R>zXLkqW zE)i2P)_32lk*|pF?scp8UfuO7#RNz zwQtrUv3X2OLmy*n#Xp(h~*e1Lwb;acz8bOX{ z8vj$DUz?^T5ASQJCnZDrrY5Ei>D@nRNaCQhA$_fPP~9u)&8yGia<}-nTJK-g>}#tC zSSQbV_pla|{od8edQV~%W5e6*#l%KU+Z+Fr&&1@3T=wU8--lV&+f^STa$7ci?rItO z{f+Sb&%YSQX1|w>MJk|`5#M`_;4GllM}&Uc&3xw`pg$UYCykMdP#+v}O&VuiC;c$s zJ5i(TE7ufgRpfP9@_6I1HM1@%HXAn>u^5}JUA-6brV*HBO+DgRcVjl)SY_90F}yNc zb8K_&_iV&aQ166wK3>rGx$n_V++=-#$Hv6?ULhZaIeM&hhS=ejU`BaXMO?j(8lW3xHL=J25IGI_IEHxzeFY-71GxLayvokZQ>a)heV@y$Phrin&aLhNxy0;izn&v4P>)dRRK5%M zy-MA;axV4xMPAB!N0dA3{OTcEKUSt&w@R#akk7B#8e+3KWC_expgwi0%g^YSmY$jQ z*^;|X3-jISS@(C==XLdQ+ZynSr`wSgXEiz+hWbfGOswAbS^sA@7f*w&ba&XjO z^)+~<-WfwH^%)uw**79GAub|PebHAhMO}f&K7&&;GLrhHMh;3H(l@hTy%?3OXE%}h zzE?|shRN)oHY74beetS}8LIV8%1p}I)=i%V2~>i8 zmzn)cQJd6{1ldm*v!5o$TFiZqIO;)Ku2%LvWLeMptmmVhnE3qXd!DCeKTU;=epZ#x zyo2xaxbIEytTg)>X7&@y?B|v087h3Nj|F|+EXO=2&3?L=GVr=%qB-FDU zWIZ3vdZL;2oHED9RQ5+k_A^56_Uz|_S$C)Pq|#{7q)F|F^7^BwQTpJBW`mPcd-qn) z$2;;ZC*KDa-%6_RUw@dXpP{I4lKrFpsBiF%4OQR0EX_C6)KPzbt#N4iDM3>Mr{#Lt zF+E_0eWw2`+be#rnMR{p>I6yp+g66DeokfBYeu$?YTYQljS--J)D&n7%H{UYW9BvU z+X|Qk%|d2jvxr&DucWDe`v0GQawdP{_kVJ}-lo5AljDy~f6pezADjNRO^!b{^(`A$ zj;+6csD2)&envse{(hn^HpBPh2VSW*KNzr*?YZw`>eK7*ZD#+m8S3YMIsVv;upCRD z{`qTTGt_rZbNsOx?i@>>KChv^|LS|M_3iIg*S}1TQ-rIRtNh1q{vW&Jf9!vKE39;; zQM&hke%+Ph$ym()mSr}R<1{<<6ssQ1-R{m4|`8-Du7tNN(EkFRe%eN-p)9o09t4L|kD68fladj0nG z>$O3BR6im09o5f8eaFUfY%53o4Q72h^$kMbaey3$$x;1;($}ZTajqOckmEjmJ=OV7 z%JHh=r1x)fw5y*m>FttZIrYBiT}6)ZijUr%tOBQu!nVQoM;^rJwfo9( zrTT!-r+-I|*9Teq4>?v&vvw^xrVq3B1UY_~VeLb5d^X(L!6U3=(~;J(og8P4w)UHH zJT=zZKgcoP1Z$U)WA{nc?k~sHQ>^{29B)pu_MdW$nqloaa?G4%?MZU{c(%2V$kCW% z?GQOOpJ(k3a-2Qi+Kc6QdZD#1%CW#AYnPE@&n4C#D95$Sti4T+x0YM`FFD4nvUWW= zj#y*uDRTT|owYxgqu)krhsm+!W@~qn<7->2y;P28w_5wM91Cr;b~!or`oP+Q<+y%_ zwLg&K?OoP>B*(aqt=&M5BR{eBG&%0sW9{Q|^xtP~mmEC@tle3Ta}QbjEjfO3#M)Qo zSmcpxn1g&faavi47MEOyn}mE_p_Cu{y<_c} za@>E{+F!~s*B{o-E5|l}TDzMZ7yM=IRdPJ9enUimyx)*x#1m^r%CXNgYiG!Di+X0F zPydk|@A+B#A34@kKN{1oZzjj_4r{+6$Ajt@O!Vu&l4Fqizj*4MUyg0nubk-JLym8# z-#yWLjT|qiUqaFQXE~Nszm1}Iv>f}XUrW(@xE!~t-%rtdw;b=QUsTasJstHOYpdT_ z(Yu8lCq`KNRXHA3Kd08OKO@J=>Nmplt|iB2a%`oKcEji7#nT66M%Wj)UYlT#lpUm`gt&Qs;NdQ9T{;?E-QvF2_=GR8I$duaA~vfIg}V374%7 zzSpa#QNCk_etxAc-*>rT>K76?T~x-X!I??PMpQ;-x^?WwOX^z%nMRcU+T4gr&d4yL z)OQo2bc}lbM-0B+TYoQH{S2Z{nmUW`<)q}~^wbg7xvZjoz@Kv_rR#5;%jH_9_;(qk ze>^XjsIHh1m7;!@oT`3MlH;xRNlzNAPSmJ<>!_s6%=G@r!!y;z{%`+LPvz7{pY>c> zpGiGcdhU<9>3n}msQ=Zcvsv?Br_-;~f6A%9`u_ayP8Xw2^Pg`w=kH+X`%eFSfNOUNjn4GSx50>6ffOyr`b~Ja@V)l})2QC(7}3g5_+tr=7 zJ3PmE)Qd($q-jLx7vv9bcbM8aFVARg`uyw5Q(q2bUEU1!GUrh*8V%Lu>5mis@Vcog z+;sCm-TtH z2mR-lDyGq1KM=?t{W|?uJ*9Z=boCmVhDT1L51ej~yv(a+sMFPCsH1*A^dI#UQy5mYSpS$BQ8S!=@m4gS*zyOuQpj1Y^tw-xm;bAP4+GQ`@-r^d843uA|oyf0*(W2vuo@wW4{O!2DItWdj4iG-FNy{%i#P2T^|-?jhYrI@o1{bP+vkI%RD zUB8154O3sw*4{RrHt`9*mZwx3Ps06*LreC$nyg>frDRiY-PQ*m`jr5dU8)EQc_*Dt>F==V0-Gf>{Uy57q1yic{g6+HUd>G!9mx2&%(QZF~WH>pD@ z-)r>ymT=!c_r-@7CdMShwuxgX~iM;PYBO=mtb zzv^7^j^|e8rKvBJIz7v~_`EI7G>#mIH0Kpm|Jqo*5ui@%w`iOO-JYwwtK(OD*7#o5@6W3E6lFo*lPkT; zeYcL*vfR5g>-JpcU6gfub}6ygyRg-N-qQGp?4JNftNgn9CC13Tv=6NlCj_>tdN>1>OZgohRIF!TG%;(*ifEsgS=$a+gty;D8Y;-~pulW_m#p}eg=o)od&@IiZh{|>+Su;Xg=_jUDm^5}$~ ztwy&|A2%@_ntPfzYF^Xl;3eO^s_*mRS@-!1S@-#{towXu*6F&GZ0kic9}WGVyXJXH z^?B|iAmM(k?p2y6ds5<4l$YB+FJ`^nUnO~yJjwCN@_tMlF|ka-{Q}{M-d^$QR55M6 zaUON-r9NufUP`*0q~AAv@4cAgqoGockA~(sJ{sD2vp*KPlql^j-kN)rkH31px5~#~ zb8ibzi};qlmZww=-?issu}jH3-mrh&SM{^r;)v*7aXk^WVdrY79Iyy<$CLF!}3Ki)L_Po44|{q)D2{ut}} zEd8Irl@G?$@jupPeAgWfuSB;$;h8!qxQ@rUtl=#6DJ`O*u}WQE_1AC9(3gh)ekZm1 zw4D}EU{bp%>AI5*={mApN?=~q}>LYdgoydCp+v(lq z*%kkx?{x|HZ~L_F@b2{NjNj#JT}tls?)=x|;|IRiasRv*zsTp|lQVpeW}Cd5Je%V;%UfIGUE1of`p7$+<0Ega?{$2PtH%)U z8hI2cS!$YkYj?8Vn-$&_o|W+{<*hkUC|8Kdc<1Z_n4g^F8z9tw))J`xSg|MSo2DmrJ-` z)iY2%p5Ip=)AuL$ZF5|Gq$J#(=JYh5>75lnOMiT=m93 zyis*U2?iN-IEcYA(w2ur^CF%Jn8Z2|HUN_e(sX>bAmzMLB3W} zUFQ>7m)y_W-_t*SfLyZWuCKSBr(eAFXw~Ikw?@9_F1eQ{DL%<-Jvtp$ALCVeW&U~n z=KkO6w!CoXTF3NY{joZ*!p&xL*1f#3+^2;`ZQ2`NsMDcJKb zy$a=fQhejqt-)YK0nxEOSGdysN*`tE%@`pX# zf!7|bPkos3TU2cIKR>8C>}*2)Pw(Dce7e<*2j|c0$BjBSO1ba9RBZCM&FU|y^W^kb z-40DX&^bYS1^=PtF?rG~0K!48p!25w`d;Iq7&p8by-0#0N;jVvZ z!rh5Z^|>bhR`0uQ^yiwb`ZLX?t?KjIrM>UO-$;6=<@F@}(bJ{m7VnmSJvMFfy(J!- z*2iz~Zt!gMwTMz1e2*4_%Xi6KyBXdYo|*C1GZ%NM$sQx?SxT3ZJ-j{s^|q}?7v8pd zO!1EQOz>S|M5!+7eJhytxIWrD#xo{U*x(%jHCaDeY^J@ zKVVk5@*zCt=*N%IN&OD)nNsvorx%N_PC5|RSwCiN`@MU!s-DQ?avzQB@k-S1!_WVi z{?6zNTRJ@*@>coxtL)mKKTbP$_3N-<*^$e?G~QULQ~zFjQ$}7nzhFnrz}17lI$mwV zl{!rV9yH&OYubTpXM1+(96o!l_iUUwdG@JV`C1LGFnQh0%3TWN?yR3@jIP|ooKenU zmb*Ir-r11kN_kK2ovI(BHh$Uc^L`0a#*KXX>F;X}H;5c}>(jjJ!#-KM=!;u72fp*R zQDph46A4r8>E1n!ikOr?$S#?IdEh4iC5oy_1f-)(Z|ak z{(e@IS|LrInWKUxPOFmQZMNg%{Uf`S+vQpRxLdBJ^$S)#*?;(?LSb(gy6&2DzVXvS z)qbh_(O26Z2HWe-T=QArkQ(3roj9`T=GVt9*mZpUyb_b%*x6$21oidJzjPIRPFMc; z{N4hd0-`H_4*Pk%`8@gJ^ZQ=Y(0Bj(zLJelU&)#Y_a8QPsYjaIZPi~x{S8-tBd#WW zdh_8N?mKIt6jYiNJ7r}_qfbFBJ?Nza_$El{uYGXp+V-?;HJbA6}2W$Wi>@1VY2;^*i1Tt!=H z^@X@!>jLWMg6j9p?Ss{8Y&Z0&5(@V6B}WIna;abO*9S)z^_>HMf4lyr6hD8*MRgL} zP;~-Z<=l<*%U`QEZHvjHzr|%&Kbq2S+FxB{fWLoP`v&zohyJf1l#_qirns81hJSgP z#ng;5{42;Ts%91SU*42iM9r#(eW{hG+O>8-9`Q`vrMS5eomnQT*U zb^V&lRt$3a`Qe-2fw`_!@%0@^Z*$C+?8zKE)grv(9AsI47NTy5? zGF+wz86i`Iyd+bEjFc%tM#&T*qh%swjBJFAm5q>bvJo;~HbN%IM#x0j2$>`sA(Lez zWQuHrOqGq0X|fUWvTTG*myM7avJo;9?WQvfb zGDXNTnIhyZnIdGlOcAm|CPG%qM#w7J2w5!~A!}qKWUXw3tdot9^|BGNK{i4*%0|d0 z*$CMz8zFDYM#vV~2zf^~Lbl3A$h)!;@}6vjY?FgmriI~`h%7V@!O|DWi6LUzkpMaU;IMaZWzMaUkRBIGlfB4n>j5wcIF z2-z=FgdC75LJrDA$RXJXIV>9?M`R=9sBDCME*l}oWFzFbY=oSUjgXVF5%Ps>gnTI* zA*W;`J;+Nt|Lu!nk9 z>i>}?BuzhteDBb5w2+JTcIwBHJ|UOntRm#HOc8QLrUwot-((}?u55(-E*l~DWFzDc*$BBW8zFzn zM#ux%2>DAkLLSOS$RpVZ`CB$Z9?M3^6WIuPDjOlsWFzDs*_MzWY?<BvWmD!>wk}Zm&*rF(!EsA2;q9~RvisIO!s0tfJ zRS77nMnF+@0*Y!7P*jtEqFMwL)h3{*4gp1V2`H*ZKv8`HiW(45)R2IpMg$Z!CZMPZ z0Yyy-C~8JPQF8){S`bjwl7OOkf~BaO>HGg(1YOf`%8Q~$nv}V8KfTF$x6!jyZs6PQk0|+P@NI=mb0*VF` zP&9;KDQacfnkyhd`_=SsEsCaVQfa2c_Zvh?QHE*ntA2sX_gIw4`9;xiwkR6G7DX?y zMbSvMC>q5UMWflGXbf8vjb)3XacmTgC!lBo0YwuDD4Ik-(PRROrVvmxm4KpY1QfkY zK+$vpie?Z{G?Rd$Sp*clLO{`M0*YQGpy)LMisledG?##)c?1-_PC(Iof~9DfX`8Kp z1a(wjY5S*(qPxDYvrLEfr5}qHnf7sEoF>3j&J1B%tUN0YzUCP;{DrqB8^(oh6{?YXXYCA)x46 z0*cNNQ1l%EMdt}9`ksKI3j`GXK(G|;Hf;seZLqO4Q1QgvR zpy+o3itZ6m^alY&_X#NalYpWJ1Qh*6K+!`2iXIVA^fv)Tj|nJxLO{_|0*amyQ1lN0 zMe6^TyHwrt{w9h{0*d?ymZD3ht)~JKv|s)IH~cS)q6+$f$>!(KzO*8TpM8S*KZ*E0 zqvhiKq9~9pih|gpD3~pZoNQ4P!WKoLY*7@(7DeG~QRHHy$W1^|ZUTz(5KxqtfTDZ^ z6y+zNr~m;)1qmoBL_kqt0*ZcqS&G+nk|ZA z*rF(wEsEmUqNoa66jf!5qH1hWRGp2Y8Uz&8B%r7k0Y$Y5D5^t1QC$Lx>Jd;>pMatU z1QazSpr{c6MU4q4YC=F!Qv!;b5m3~efT9)z6tyIvD4u{K4*^A90*YD@EJYRlY_}AU zpb7e$j+I1Fr2b03wVy-#(u&&o*@H`qqV}9$6m?*WqK<4))QK&MUSNx&&TLWCg)NF+ zWQ(G%Y*EyWjiT-Z6!jpWs3!qMi3Ak&BA_UVfTCmqic$zD>PvTVd z_N5h#@UyooD~ev?{GwCN zK+zNeil!1!G>w3wmkB7EPC(HN0*Yo5P&A8xqE`qgnoU5_s{|CiMnKUV0*dAmP&AK# zqSpy1nomH{0s@K_5>WI8!BUjzXB(k_1kKZ*#D-w?iO+SbBr4=ppv%gth6fNWY zqUbHQC|b@IMJw2%XeC<|tzwI!)of9;hAoQLvPIE4Hj360P_%)7qKyO;Z6cs(GXX_! z6Hv5;fTDK@DB4Ou(Ypi`y+=UNHUf&?C!pv90*ba1P_%=9qMZa3?INJ)LjsCEBB1DF z0*ZDMEJcg`Y@a9~K_8n6&Jt17L_ZdN;^)x5w4%L!_8%&WqJ5lS6zyk=q62JEbdW8I z4zWeiVYVnb!WKnG*`nxkwkSHrM$vHsicSzvbdrFgF9<05l7OO91QdNmK+$Oeip~&F zbe4dkuL&snhJd1P2`D;8K+$&u6rCra=z9W+E)Y=k0|7-p5>RxJfTBwTOVJ)bn_nfR z=#>6S|1(jvPW{5E|7Aai_N5j5qT6gy z^ebBw-C>KO-`FU+OF+@@1QgvPpy&?*itZCo^d|vD4+tpwi-4ks1Qb0Ypy+P`iXIbC z^n`$-rvwx|BcSLX0*cgs0>k>U9YrPqMScVn*$61|C!okquoPYOv$a$}f@bN*qHCh4 zkp7GoU~_0+T2YYA-alFt1#^B;P|s`%2bI%P*bogaHDI(h*RUo?t5qGR^S{ zhQ69D^%F9MkJ_3sJ6HruufTDr~6cr+%s4xLVMF=P=NP$dU7Xpg95^P1)Ofx|arKr4qDpXw*ozmaP?q<5QFRiGTY30u)ih6Ur zDC)x&MSa<#s2^Jt^=FHs0c=q;kS&S^u|?5fwkR6HM$u3LiiQzTG@O8<5d;*CB%o*% z0Y#$;C>ldR(O3eC#t~37o`9kW1QbmqplA{SMUx3AnnFO)R04{o5l}RpfT9@$6wM@{ zXcoa%)Wb9zDT0*cNPP;`NSqKgC+{YgO4B?5{r6HxRQ0Yz5`D7s2O(KP~!t`ksngMgx& z1QgvOpy)OMMSl}ebccYVy95;7BcSL$0Ywi8wxWZk`BDLK-_lR04~e2t`myMt>C(Qm zqNk=6R!|f@<9Jc@oGpr8utm{JwkZ0CEs9>TMbT@vD0;&dMQ_=n=p7qH?+GaSKtRz) z0*XEnQ1mYWMV|>M`a(d_R|1N@5m5Ai2isFWXV%AfPCKfFhHC zqCf(QECPz01QfXlC<-FjiXNM0HU-38OFyB0B8ryjm;J$kF6~Pz3JbKV7Zyd~950GI zY*FN8iy|Le6h*K_Q7pD7ip>^9k!(>Ehb@ZYvQZR|fTH*W6eS>_C?Nqwi3li4Oh8c* z0*aCnP?U^-qT~b=r68avB>_dL2q^lEfTGj{6r~}cC@ld+=?ExFPe4%y0*W#cP?U*a zD+&oTdnzFA#rm-*G|+yfze7K}&K&5{zOvpfTCsu6vYrw)SQ5#76cTvB%r7j0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7 zpr{i8MV$#K>Ow$KR|1N<5m3~ffTA7*TT#tGGq8kG6s3OxQcD!A(~m_x16|seR@67p z`mK~G>c{b-s6Sg24Pc9+foxGUh%Jf+vqjMmwkR6P7DdC@qG&i9MI#6(8c9IWC<2N` z6HqjUfTFPk6pbUGXgmQ$69_1pNI=mf0*WRRP&9>rqNxNFO(URaIsrv92q>CKK+!A$ zie?i~G>3qqxddBL??AJh0^)9}e|uveQB+R-2d{zi0$tjdRuHNv0Rcr12`G9*K+$7@t>{Rgc|`$nkI`Smj*6mh z`j!5ZK$rHV6}{dYqltQ!xlwv*`nwjTNJ%#i=q!~QS_0G zqE7@A{Yya6X99}85K#1$fTC{%6n!V4=m!BsKM5%MML>~Z$;);WIS42UAfU)3peT@l zB8z|`Cjmt+0*ZnNC<-Q^$W1^|2*FnLEYM6;Q7L+^zoI=CMK$zSv{1{XeQ8Br%PLq| z6!|z_6h*K_Q7pD7ip>^9k!(>Ehb@ZYvPDrmwkV3v7DWlzC`w2`Q6d705))9Agn*)? z1QaDBpeQ*3MJWgHC7`Gq0Y%*jDC$8#QBMMjdJ$06n_w%dZJDnW5Vxhj>sUt=E!B@jeJq#u zr4=&2BcNzJ0YwuCD4Iw>(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&>ECPyV6HqjV zfTFns6wM=`Xg&c&3kbHNewLX-0decUU?s4>D9WuLixyfg?Mo|KYFRaFi=t&5FN&74 zMbQejC|b!DMXT7NXf<0DtznCzwQN!J2U`@aW20z20Yw`KDB4Is(Ix_lHWN^^g@B^1 z1Qcx}plCY*MLP&6+DSmsE&_^n6Hv5=fTFzw6zwCRXg>i(2M8!SNI=mc0*Ve3P;`V~ zD_U%sy%iAmcKu3!i6~Nk_n>;gX1TO4t>~m>&8aJjPI0^_I?WbEXV{|XEL#+vV~e8m zY*BQ9Es8F(MbV#ZQFMuoqRRvn{Y6006#|N`5>RxFfTHUJ6x|@8=q3S0w+JY@O+eA# z1QgvNpy)0EMfV6Ox=%pS0|JU35>WJrfTG6)6g?rJ=qUk3&j_}nVj`j;(= zKC@Bug@B^31QdNEpy)dRML!5A`bj|1F9M1Tr@U-Ok%NGu00N3k0*V3&D6$ABauQJF zBA_UUfTCamirfSgg%D5_NOTNK4-i=qTj;xin2vfF*b^d6HruwfTEHF6qO>Ns5AjZWe6xLOF&UM z0*cBLP*j0{qKX6*RU)9MG66+Z2q>ybKv6XUimDS(RD*z`ngkTpBB1DZ0*Y!AY(=@8 z=41uLyi;05j?<-mX+;g3*5+tY)R5yvQ6sh}YRnczP1vHSDO(gpvqe!e zwkV2Wi=yUiQPhHsqLu^{wIZOXH33C!2qPtXTKZ32Op3}UhfVjWu$D;b8=&t@o zc7LZ!`_hUAJFPD_J^@7w2q;=eK+z%siWU=WMFX8?lIBWLTK$B2kSHqWf5GN-Xi=w1#QIw30qT~b=r68avB>_dL z2q^lEfTGj{6r~}cC@ld+=?ExFPe4%y0*W#cP?U*)qRa#oMG;Vxg@B^01QcZ>peQ>5 zML7s4%1J;`E`qHnw#&?=fVii)6`V+y{YpPtKQQHXxwJ2>D8I}4y^|;^!11D}AX^j_ zVvC}}Y*AE%EsBb=MNu)fC@RhtMJ3pxs3aRjr3ff0O+Zl@0*cBKP*je9qVfb3RUn|K zA^}B}2q>ydKv5L}imDP&RE>b5>I4+kAfTuw0Y$Y4DEgg%qS^!$)ghp$E&)aL2)3fU zF0-!!;(n=SU_McFUOyJqce%7Lt*Eifn%6}XHQ{(s)RZlXqS>OT8Cw*^utiaGwkT@B z7DX-DqNo*H6t!lfs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9bta&w3jsx42`K7DKv8!B zih2-G)RTasUIY~NCZMPf0Y!ZYDC$Q*QGWu81`tp*kYFon=rRu}AnyA5WmzLpG)zCc z9^`UqUs};Hm-V2VC>qZ3qG$wL6pdtyqET#7G@31n#;`@vShgq{#}-B7*`jCy8$}Zd zD4Ik-(PRROrVvmxm4KpY1QbmtplAjGMKcK~nngg-Yyyhr5KuIifTDQ>6wN1~XaNC5 z3kfJ%L_pDE0*aOpP_&eQqGbeI(GZsz)LkiBuV&y-Q52@XqAhp1v@fk_waZG^QxvV? zcu};LEsFkNi=uUGQM8^diZ-xC(MGl?+Qb$`o7tjh3mZjS2`Jh|K+$#rigplCw3C3M zT?7>ECZK2!0Y!TWDB4Fr(S8Do4iHdukbt5?1QZ=6py&tzMMnuJIz~XzaRQ1?5KwfI zfTB|bThU6FSxEtLoBE5`Dp9moKNg*KxwJ2>=)BA7&|4H;;CNAVku8e;WQ(FpY*BQX zEsFkPi=r!RQFN6pimtIm(RDV8ZV*s(lYpXI1QgvSpy+P`itZ3lbeDjldju5SC!pv7 z0Ywi9D0)Od(PILNo)A#lYpW?0*WjGikt)#xdo1BDaJ(o=$QDJ3*rF&gTNEW>i=w1#QIw1=ijuQMQ3|#wO36l1DgugrBcLcX0YzyD zC`wB}Q91&O(i2dWfq2q?-e?`j|t{;mU1-Y~@ttdLk8Zkr^HRE_u6vGxp&Do-;1zQxgWQ(F!Y*Eyj zEsEN(MNwO}C~C(>QF{W4IuKCQk$|F31Qc~9pr{K0MO_If>PA3OcLIuf5Kz>UfTCUm z6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2*Fm=B*qTcMPt~aXe?V4jbn?V@oZ5vfh~$AvPID(wkVp+M$r@k zil!1!G>w3w=>!zbAfRX_0Y$S2D4I<`(HsJb<`PgekAR~21QabGplBfhMT-b1T1-IE z5(0{r5>T{^fTHCD6s;hjXeGf`G(5+0*dw%P;`KRqJsn!9U`FUFabqJ2q-#AK+!P*ijEUdbb^4QlLQolg3SI3i25m- zf^$(6z182yejnu0zO(O{ol$hg1Q4+Q&O3D^R$=ISOIa?H^V2h%ZY*CboEsB0)i=xzQ6r~}cC@ld+=?ExF zPe4%y0*W#cP?U*)qRa#oMG;Vxg@B^01QcZ>peQ>5ML7s4%1J;`E&_^j6Ht_gfTFwv z6y+nJC_e#31qimH1i_|zf>Lzdso*3GwqNOo`CqUFyRyaKv69Mihd`cs5SvbbqFY`OF&UQ0*dMrP}G2cqJ{(%H6oy>F#$zQ2)3fa z!DbZ@I){1g#It^F_9f?e8|R@6M$>NG_ZwcvPB)RHZVTCqh@YqltA!xlwt*`lZ& zTNJfti=qx}QPh!*qD}-9bta&w3jsx42`K7DKv8!Bih2-G)RTasUIY~NCZMPf0Y!ZY zDC$Q*QGWu81`tp*kbt5=1QZP>plApIMMDWF8b(0TaDuI0ddFGk3}(}C`LU^ z3LFva(!R8!F~QdMX`*N>$BUwIY*93xEs7?vMbSjID4N6;MU&a0XbM{tO=XLsX>1ft zC!lBs0Yx(jD4In;(QE>W<`7Ucmw=*q1Qg9DplAUBMGFZiT0}t6Vgibm5Ky#~fTCpt z6fGy9Xaxa9D+wrCML^MN0*clUY(=Aj&07kHyQG?dqeW3C{jz^;uuJ>WiZ%pWKW2!c zjT|qEHnBy~X0|BW!WKna*`jD0TNG_)i=rKDQM8jSigvM4w3~pUJp>f(C7@^@0Y&=> zC^|qu(Ln-=4iQjvn1G@q1QZ=5py(I@MaKy!Izd3uNdk&a5m0oRfTA-56rClY=o|q> z=LsmfK(H093pP{CREpl|r$XyRQEW?%i@`4KODp;-*eX6-6kXwXQFN6pimtIm(RH>c zy1^DjH`$`-7F!hEW{aY~*`nwU8%1{sD7r^L(R~7n9uQFUkbt5`1Qb0cpy&w!MNbJR zdPYFea{`K95K#1zfTDj0D0)Re(Q5*V-VjjqmVlyn1Qfj|py&euMIQ;aqD#SMO9jL| zNWZwhEQ&JfKQrW0uuJ>WioOP0qvndDZyYa*zOzNq54I@!$reSw*rLdA%PV(L&ZeIieGx?i^ya zKv69Mihd`cs5SvbbqFY`OF&UQ0*dMrP}G2cqJ{(%H6oy>F#$zQ2qAd zqGE0{p9136e^OCkaZ$8gj~KU0`_hV9xvhFjL{V#w7e#H@qNpuf6t!cEqV{Z2)PXIE zIT{=fTG0&6fGg3Xej|j%Lpi1PC(HL0*Y1= zP_&AGqSXWxts$UjEdfP;5Ky#^U@IEyHjgPF?pgX9jpIa7X8lTkz1yXIX+@je){_;Y zXbZ=SqOELEw2du_wzEai4z?)T$reSs*rI4RTNLeKi=w@36zwCRXg>i(2M8!SNI=mc z0*Ve3P;`WVqN4;99V4LVH~~c`2q-#9K+!1zicS+ybcTSUvjh~KBcSL!0Yw)GD7r{M z(VqkqT_V_uHoDEwl}b@6{TIk=5=C+K@4LS2c4=Q)(KWY~X|*W2&het?23r)}WQ(F( zY*BQZEsFkTi=sPhQFNCrite#R(S0_G9uQFUkbt5`1Qb0cpy&w!MNbJRdPYFea{`K9 z5K#1zfTDj0D0)Re(Q5*V-VjjqmVlyn1Qfj|py&euMIQ+$`b0p{zXTM0CfJIuxXo$` zh`XZxB6d|2?Fv%ki`%7rX+=NWR+qJ+=qJaEqF-!LWQ52ocTwbEi=qIwC^FfiD3C3R zEVd|evPF@LjiMj|ih>C!auZM#LO@X{0Yza16onH|u90Y%vfD9S-VQBDGiauHCJn}DJ`1Qg{ZpeP>!MfnLRDnLL{K>~^j z5l~c^fTAJ<6cr_)s2IUklq|&jTLE$Z(m#z&9%8@J|EeF0iifzgFRiF_i1llOC@RD8 zqNpre6qRF(qVjA}RDmsuDzZgUCAKK4%oase*rKQ^8%5O!D5_3CQ4Io$Y7$UXi-4lv z2`H*fKv5k6is}+jRF8n7`UDg;AfTur0Y!}nC~8bVQ4<1+ni5bHO+ZmI0*Yb?C~8hX zQ44~tsAPzlYNJwAMgIh(lqi~|-WJ$0#HD>{MQuZ@lAA?QJB}Ac?b)KJ16vezWQ(Fs zY*EyiEsDCZMNwC_DC))*Mcvsb>OnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt=T{? zfTGm|6s;kkXe|Lne-Kc#j)0=|1Qcx`plBn(Rx}~R+@OHClj+BziK1w|{))CK#HD>{ zMcYEGi|RX({=W%*JI9Nn9c)pwlP!vNu|?5twkX=e7Dap6qG%sm6zyk=q62Ic9VDRW z5CKJp2`D;3K+#bGijEObbew>q69g2UB%tUN0Y#??C^|zx(OCkD&Jj>_o`9kY1QcB) zpy*EmiY^gQbeVvnzX&M0La-HW2{At@AnpMg&Q?)$O+OZ04RL8-TG7oAEAB2)bc^Ff z(QURU`kO6^?yyDCUA8E?#}-BR*`nwHTNFKHi=szt6g?)O=m`NuPYEb`MnKVX0*YP` zQ1p_3qJIb|dPP9dYXXYi5K#1%fTDK<6ul>)=mP;o9|L_pEM1QdNHpy&$$MPCUh z`bMx7T@Nt}C?M|q`ddUdMA1@B>U)Sw`_hVxP^-ZnQRE1fSMs7LfGvtlwkQf@iz16H zikxgw8$}@m6onE{6h=T%H~~c-0*br@6!{1!iXfmU76C=E2`Gvr zpePOjMR5rzibp_Ed;*FR5KxqmfTBbM6eT90CQ)6Gf>xUKFKai=wn_QIw7?iqf-1Q3kds%E%T)nb@KzGg}lz zu~C$TfTFAf6lEizC_4c~IS44qNkCC90*Z1IP?U#&qPzqYTLS5RIR#Yz3 zdUik*mFIX-RDmsuDzZgUCAKK4%oase*rKQ^TNG7ei=ygmQB;GCqM8I0)gqwicLIuP z6Hru#fTFqt6xAc3s6GKj4G1V|NI+2|0*V?FP}GEgqNW5CMH5iejDVsT0*aawP}G8e zqLu^{wIZOXHNjR?Ce#c+s1(K0-*qf2iiWGV1-1!wX zi=r-UQPhcJL8J=vnD7aK*r2`K7AKv7=;iuw^y)SrN&0R$8cB%o*z z0Y!reC>laQ(NF@4h7nLSoPeSc1Qd-VplB2UMWYEQ8bd(QSOSX15l}RqfT9TmTT#1E zvxWlV?x~+pw--gD^_Upy(!R8!si9W4qoQaU$BUxrY*93WEsAEcMbRv_D4NX{MRVAq zXf9h6&0~wA`D_#|AfRX=0Y!@lC|XQF(GmiRmJ(33jDVu$1Qe|xplBrlMXLxXT1`OF z8Ul*e5>WI90Y&QwC|XZI(FOvFHWE;@iGZTb1Qcx{*or2HnzI!U_bUBLe~Kt7e9ZnqMf1E?&G3p7srdD-E2{`hb@ZsvPIE8wkX=q7DWfxqUa!76dhuVqQh(y9U-9T zC;>&s2q-#EK+y>TicS(xbc%qY(*zWqA)x3i0Y&EsC^}C-(FFpEE)r1mCjmv52q?Nt zK+#_W6kQ>p=qdq4*9a)OPOuei4>j*9Ans=R;b(^^N}}Etcq7!MeQ8C1hgyzPqUa9C zi=w-1QFMe9ZnA~Vb?eMS@ohW*c1`W9OhIoYDf#TG?D zY*7@<7DaBhC<+qTB=&&)h3{*4gp1V z2`H*ZKv8`HiW(45)R2IpMg$Z!CZMPZ0Yyy-D2gVas2Kr8F$5GfC!nYW0YxndC~8GO zQELK<+7M9GmVlym1Y1%0F!Qql;(n~Zh*c0p`XMN=eV9x8(uz8VS@AE4qAnaSin_8z zQ8%_I>dqELJ=mhCCtDQtVvC~QY*EyQEsFZGQPhusqW%OF4IrRsAOS^#2q+p%K+zBa ziiQ$UG>m|v;RFl*b(HH`X#u898j)0=^1QbmmplBiiMUx09noO`2 zbqq5LDIo49`uAOT5=HIwW6_i_m-eL<%?Ps^{UwTKa=a*-#TG@g*`jC;TNKS@i=ugK zQ8b?|iWaa%(L%N;TEs@tVgibm5Ky#~fTCpt6fGy9Xaxa9D+wrCML^MN0*clUP_&kS zqCW^IT1P<9dIE|z5Ky#{fTB$V6m2G;XbS;FTL~!IMnKVaf~{y;m^oAdaevU?b(}7W zQs@V!9bqo*ODozFW-YraiuQ86DB8ysMf=&J=m1+39b}85Lu^rWm@SHqutm{PwkSHr zM$vHsicSzvbdrFgQv?*9CZOmH0YzsCC^|<#(Rl)jE)Y<3k$|E<2`IWmK+$CaivA*? z=n4TvR|zP(MnKVZ0*Y=BP;`@kqFV%8(XKG_lmg;Ts(;`0Zc$V_RE^tVF6~Pzx))}> zxGswBbG#^ez!pUh*`nwXTNFKJi=roNQS_88ik`7W(Q~#adcj7~O9G1iA)x3L0Y$F~ zD0)Lc(OUwF-Vspro`9kc1QdNFpy(3;MgI~|^qGL7F9Z~QC7|dV0Y%>lDEdJ_(N6-3 zei2Y)gv$$a6gddCqB~)x_l8n*S3efr6-BA^SG0g|m-eL6lG$IqRebj6vY-rS=gc|D_az0 zV~e8fY*CbhEsAooQIv~-qTB=&kcSTWEju%DM*rKR9TNKq`i=vurQB;d9ihgH{qS|axREI5!>atN( zkAR~31QazOpr|1MMU4n3YD_>;69S5w5>OOPKv6RSied;TYED2=3j&H-5>V8NfTGp} z6ty9ss4W3S?FcApPe4%z0*X2kY(plApIMMDWF z8b(0TZ~}@(5KuIdfTB?Z6pbdJXbb^GV+kl4M?led0*WROP&AQ%qDcf4O(vjd3IRn^ z2`HLIuoZO)H`6L0?tA(tAYDaKMg8o0dbmsb(u!t>TV)@KqB$HdisrIK(LA;&n$H$R z3)rG)AzKtJVvC~1Y*Dm?EsB=1QM8PJqU8h>tstOiB>_dN2q;=jK+zfkiq;ZP^alY& z>j)@XPe9QI0*W>gP_&7FqRj*pZ6Tm&D*;8@2q@Z4K+z5YigprEw2NRXni+1kS3uln z^^5yiqA0E&yTe`DmsYet+?w!26dmArQFM?kiVm?w(P6eII>Hu3N7K(RBifZV*s(lYpXI1QgvSpy+P`itZ3>MSH`|EeeRcvVL~GPZUM!aW~wheQ8Ax z!>zxbiK0gwFNz+sMbQ(sD0<2kMbFrx=s8;yy4wtti-IC44E0+#D~8LfE1x zlr4(F*rF($Es8vBQRHQdA|G26MX*ItEH;W_6HpXMKv5h5isBMb6pw(S_yiOsAfPBA z0Y!-jC`wE~Q4#`*k`hpqjDVu#1QewppeQ8)MX3lV`i+31)C3fzA)qKN0Y&Kuwj!6u zETVw8U+SNL1bOUN`lmFh^d6V?r4?oNSWRAuq9~3RMOoOQC@WhOWn+t?>}*k#gDr}3 zvPDrYwkXQY7Daj3D9TGfQ9c5S@)J;0fPkWc1QZn_pr|kbMMVfGDoQ|6F#?K;6Hruw zfTEHF6qO>Ns5AjZWe6xLOF&UM0*cBLP*j0{qKX6*RU+7mGJ4G63Wz(gR+LE;Rnnuf z$EAH~Mb$mliZ`OD2FHt{nru;2i!F+NXN#iRY*AE)EsE;0MNvJrD5}pEMGe>}YDhp) zBLa#V6HwHIfTE@Z6h#wI)Qo_l7y^o#6HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxb zP}G5dqK*U;-0L(cU?^smDi6&T|F-CODpQ>vHp1{ih6Op zDC*4?MSa+!s4rU-^<#^o{%lb+fGvs!vPID#wkR6RM$r%giiQ$UG>m|v;RFl*b(HH`X#u898j)0=^1QbmmplBiiMUx09noK~^6atE-5>PaafTHOH6wM%@ zXePl{)ZJr7yjO~j>u)sn5Jev?HD-BS+Lu-|&tql(D2nEDyeL}07DWr$qG%CY6fI_p zq9trmw3IE1ma#?Aa<(X1!A8+a0*Y1Z?_4-#79p-pZbc8L6jEsCDAMbQhkD0;~jMgOox(JQtndd(I^Z`h*fEgMDe2q=0_K+y*R ziaruh^of9?e+el1OhC~W0*by8Q1p#}qVEJ0{UD&|Cjmvj2q-eV^0FO84g!h-2q-cM zC<-K?$ReP~NkEZ{U@Lm$F&`=*?kW0<*ke(2SU(m8d0pCIjN?U7I9n8X z*rLeG7DYa`D2iZv-l7OOA1Qh*7Kv8M}iqa5Jl$L;^bOaQoC!i<;0Yw=Jwj#IJ zOs{~rGio>?Ui+2)GyPOMlh>tvX+>GRR{5WzC>zI%qU>x@l!GmbaK; zCIl2UC7>vpfTCsu6vYrw)SQ5#76cTvB%r7j0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7 zpr{i8MV$#K>Ow$KR|1N<5m3~fU@NNOHMc1s?r-|pbxl!}Tffrp;dNHS`m;sR0JbO^$QDI|*rI4KTNDjpi=v@yQ8bK=qTvJ-jUb?CBmqUE2q+p& zK+zZiipCO9G>(9x@dOl2AfRX>0Y#GtD4I+_(G&uTrV>yzjew%*1Qg96plBumMY9Mf znoU5_9D=Q=m)HERfVj8lZ#4E6MR)XL(Oj=f`_hUQdacBkC|bnvqG&N&6fI$kqNQw6 zw2Uo^ma|3C3brU($reSc*rI4P8%1jfC|XNE(H{g9ts|glJpn}<2q@Y}K+z@wiZ&Ba zw1t48tppTpBcNzI0Yy6qDB4Lt(Jlgtb`wyvhk&BJ1QhKfplCk|?ynzk`muyk=4_g$yVvC~JY*F-vEsEZ9z3MQb)O|TU`^_u4t5O+T{1D}ba_5K%ZK9}~T6?uHt>kv`o<#67I8K=^xUMMOl0sE*I-;}u19IbIaiV~e8tY*EyJEs7elMNuQRC~C|WMNQbEs3}_%MYB=V zjDVsT0*aawP}G8eqLu^{wIZOXH33C!2qtKW^ z8o=?QXdqh@4PuL;!E8}9ge{7OvPID_wkR6T7DXf2qG%)=MWYBP8cjga7y^pM5>Pab zfTHmP6ipzYXd(eclL#o9OhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q>COK+zlmislkf zG>?Fy`2<^0U!VC{0de=x4?q1x(Pcdr_*~kTRT{{fTH~b6dfR-=pX?_hX^P-Ot2L#@|hVG5cfp= z8}=8AqMZ7%=!nmyeQ8A}d{)J{qUa>Yi=tC(QFNLuiq5b_(OI@AI>#18=h>p@0$UVa zWQ(Fd*(kb1K+$CaivA*?=n4TvR|zP(MnKVZ0*Y=BP;`@kqFV$M-6o*uZvu+$5KwfN zfTDW@6x}DF=m7ym4+$uGL_pDF0*amxQ1p~wD>~*gJ1ZdW68b+LIxdQW6rR9mK9}~T z75(G0rolYpW?0*WjGikt)#xdUl5O;U|SoBg9HPK(u!XsSTmsS)JVO>usiehoRD2mM% zMUiY#6o)N};<80iJhmu`&lW`q*rF&QTNEW?qbM-}MM(%KN=iUcG6IT{6Ht_bfTENH z6s01d=r;n2QWH>=hJd291QewspeQ{7MHvVv%1A&_CIX5w6HpXIKv5O~in0<=l#O63 z@Ql%fTGd_6qO;Ms4M|RyfKv4|>ifR&2REvP3-wC#&oDpUT1;m|GKNjT@ zMYZ%}QSAtq_N5iokFa8riJ}G^FNzwnMNuQRC~C|WMNQbEs3}_%MYBawGqxy-VT+>X zY!tO1pr|DQMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}Gfp zqV5C~^&p_ACjmvh2q@}JKv5q8iuw|4MRg<0(F%xrn*Oe1JyG;plj;}Y(!R8!K@rxP z6ryM_$BUvNY*93nEsBP*MbU7!C>p^QMI+gwXcSu%jb@9YF>Dl#C7@^=0Y&2pD4IY( z(L@4@CJ|6HnSi1x1QbmrplBKaMbil=nn6I(Oah8#5l}RnfTB4B6wM`|XdVGY^9d+g zKtRz#0*V$9Y()bi%nJ&L`-7T+14YpfJr+l}v@avv2nb9WoG`V+@T^cjvNb#>H8{@; z^}A|=JYm7=H?Mi3)DPjjo~mJn5!*A(V;J!~H+_bY$df#_VI=dkh+`P3Jb%P9jI^Hj z2@E5nCvRfI$l@80)G%^*jwUyZJf4tLhEc#%HML0>Qr>9LB!|3bTSk5p8dj73o7(+b;D;vg0&ycEyG1hakx?xQ8cxoBOR8P&? zhB4DKr>D22bIZhOxynthHh6@SJXI z7<)Xv4u)~S^Lr=5IO3Vt#V}5I9&|H|GoExk4da5RLvO>l?AhAaFs^yN^*4-Lo}z;c zn&?I-?Eajc37F!}#ENG~O^idooNijPKq~Q`GJ6@NS=` z?f{4P#|(83IK0JYtGmGA9W__o2M+J~`RYz^cq137d%@wYw?y3y4)3C6>V9x|_1|Wn z%Hh?29eG-ZSO0y|8695z7XoK-c=g}tn#1AMehuad`FLYF5JG z)qgEj8HZQ@y+Rcn-e(8Yed6%yzuBXP!>j*lhT0CV{ObAOnZv99 zc;c20um1C8+d91Z4+!n(@ajL|v8%(Y|A@Yx4zK<**7`cU`VYw(=O;>K`0maCr4k{w_Pb`bRg{9A5ps_gfCH{^sdjhgX01>!HJ|zkTu4;nlA{Upl<{ z1;iVNS3d*%;PC1%;h!B|{TTe+Vfaex@9i(OKjk9wI@Fz+U40tqPXqPKxnJ@)j9ACj zyEt-&Pf*pX-=zK*TLCm2x%|zD-CDmxZW#wnHS&ZH@xR+g^=atHD{pzOPVC5Mk66J$ zYUKBi>FQl4>XUkPDU3Qh8RjOYgr@^X5Gm(O(^7`7TTy*3^ispbpWOq>p`w)Awo1*9GcYt6Spc zf&JsvuhcE^?%w=W_AT-J>f6ofTeEZH8+G%k zOOwg-J;;BWFQ>Nl_MfKNi&^S4fr_TSf?fE?`-aU`S1?p%{}qgKW}!~ zr%c^#zdohYw{g>;q57Oo-<>0GXDgMd)j|3y9_6x~F(R|ciN0{6&m+%hb?WxNv}*XB zKK=`rGwF{O{tMUiNR{SBWIlC_zK-GP{Wpv0RzI|h>?|kBVMjlss)~_1fvqG!eOZXy zr`}6nuk!YLS)ukP#xa%s*XxSEk2%jZb)FA$p7u@}m0i>Y5iQwy(MWn!iqZKz*948?)w7 zXJRALs~(c|jhV$h#0o7q_mR4i@l^KTn5on+^p)(uDX-rexmewO>RKNAzH+!axw>!% zj~;)f?^364^~M=H`xucq)KU6c4z-Um-N_VD%6}P1DHCU^ z#}ReT@0FjIF(MbMWAv45Wgla@Z>hUrot$Vs7w-J}pZ-TPr|;UD1&{5=p=1#oyZW!@ zmF>gM^)w>4se|;@+{~F0sjGQN&h&_jR3&V2693J$a-I4+i1p)Hf;ivRq>Xgjg7 zVx*4HSMobYOggtfUCE~^`>*5&Ib+_;{u|B;y-+k~UH_H5I%3pveOFqci4%YA?7wIm zR}8rIeh_70s-#-}D+lX6D9Z*9Z z5ZO>Jf+NblF1}&oHmk4iisgf$wUn~?BnNxMXaH7d(;w{-}61IrrHl^L)JbmZA7kBhv=JT6X(%){|-6NBhGW^;kEq! z^ZXdRv6KJuOw3lLiU0Bp8@%k2x;z)uA^!WHL+tzin#%s`_)t!nCyU(wjt1#`{@ZND z*t3t-ql>zZZNGnOr_O1GZu17KPvm#%5PcOZ+K1S8|4%v3U^_Z}>+WA$rEYR{<3D;c z;hTo!^o=_4WV`)w zsykI(&-_o+cail;ua5b0Q9T{1pbpYkG?#sl>7J>O)s{20=1jXr{L)`$6^f>@&Q|tc zyjwFD-?Hz_db92{Ga?(SWAybLz=^J@6Sb8SZRSKtkKU~AS9N>c zKK9_H`gAU*4$@b%IcL(3%neo4pU$)Y>mu!*qOP2};rEXG@m1Y$>LLw0viQCI$o#xs zeD$SwqI~o-95XsiTJ>3`K6w3x{adR;tk4I2{?U&~>NC-p*+PA~s3ZLMKS$V))Fn7=mtnCRE(+c)BqdMv-7j?s62PWu@9Q~8#h zs0Ak)llg5o|3yo)vtI-MMaxkxQ&ay%+xWJ=`l|d;9ieZPzMMvXCclx>Y_Ox#x9Q2P zz4q<T#pT_N~vj18Rlyg4i?X}~@()Xkl zI(XUBjQ-0Or$W1Q{xc39dm*n8IbI#1pU8c;j|d1VVMMN$j}j}Vc<7z6xcVrY_$d42 zqg1iq?(|KYJ!HB4(0@6ssk#aEB|o-cs(ui%LPw@?scU;iK2EfKj3bMBMkXJoHy_4+ z^nJsJ`7R%3J8xfdtZ*j(ExmHVj8itt&tLx?XMdQMm4~QXIyBV2%g)%x*bl$)RMhvq zkxQ;mn?Kg5Cqn8jn>laIar@DC`GPmM?N9uE&-X?ek;&9C`YwyKk1^f)(Kn-OdX={u|^zXKV7V%vi}~dFQ=SqzuoCu zy6xROb=}lC!v`KvUGIsen3oAx8XqIXXUs#hcG80~T+mrXxe>@O#J#0NTdb98b4 zc`Ello!Wn%4Ra>z2V?b^^kmkiSL*BEaCMBnl3zKIeoUIJqJB)uoLfFqjy``r&Avp# zvPYNqpJ~v$RRh%>u3qTwoISR)5qG{i#{Vp1wOoqU_Q6(YjoT= z)$?D7&l~3Hr@qJ3A^H{?#38onb1M69p&N3_{al`{SKgmgS3})>gSPIurXCm6XWWfq zKN9#)I{VD=&+3{zRR`&t=#qVqpY;bhkyBCdf2-r>*G9J5{lV>X`>)rq&r9d}ALT+X zZu}ggUTvvE^bM52J|rM$sQS9BzC)@tRpK<;O82$DmQOl7bc-^i?y;$_*KM=UQ)2aG z#d3MLeH~*s#{P_2r?US#?oz+d=UigH-RV2G<@-DZQ(ebN&+lEvHDUdC*k z{aszh6Y3y+9kJIQ@?mU^?S(S1<1MKh|%iJN_zF^*@%O-cnk9I_ZC`IBI-TRsUm| zYSdI!|6|2fBU=4J|6|2dLw#e_(EnJmOsC=SIerU|6=H@b46hm2r@lXF7y+q_kdQ(u z8HO3hFvIhO`F(%i#%Amrj3Vum2b7 z<)u%qiF}ZV%#OnGxe#gM`y3I@BJpMvi?2UotQ`Mw@dDy*FQ#sj*#FrQsS`(z8thQF zUDjCoh&ZDMJB)yMlZwSNjJWCzhJJ(krZMlM?$69d;rIpOw-5J!Om!jD?H>>j;86F8 z;gEl;UmDHT_Z0$+EDQ9%^|vHkhTCv-GZHP(}s6L7#bLObdO`@82=@`|e zb97YaMqQ#~8g=a4p=(TZ*O+Ee(VcsB?Ak$x=$K~RI>&VRkGJXfSMQxSs$=I??OJth z)jh_DYT2P(OjMJ$F+HO)x9t$!q-|7}mQ6axM0Jj7AJe5tm#CO*jkBsIDD4 zw2f}rq*ePaQ7xjQ8#U?NE-Gu5M%f!>%aSc?qpVqU%%ozb_8r>CWQu9hv{k08Su$tO zq~Dxbz4?Es^8 z|GF)DcJ1uHN$gvsO6Lx()otD-s(QyJo!gY^*1k~p@*K015WteK+?MWIo%nC4Bowe8xdYp;$mT{5@S!qnZ>tX2E2YAE&9 ziW2bfm+)OIq|k030+PBXj1vSR(e{m*hZ%@*n%%=np|EvyKq zBPw~8^eGctmNQDP|A&7km!3lXG|v%fh3J2ItYrFM>izvQnK~?+dbe1aQdr4SSP_ZT z<}m*Kzj3%Dx<=VgA1yWhKjEMI=!N{cn7TSV{knU&2_C1B`D+$RbJ3A0a`em=z;@MxX6{D}$ zeD2Zn)NwzpRLS0Ad9L(*_oT{ado2~OE>!Y$p4P|52XS3h=; zAMqyH4L}+9)Bi8NW&Z)`+1`zeDK|F7D-EjqAH7Nj{S)tY|Nez({U5zB(ML{f>*t@~ zCwk>faR<9yuH@$n5a*A|mA@PT(~@EuooNoXdnfpR@uS&0U;g5L0ee@h^uK&bug?Ap zs^}-W8Rvdcg`#JyU%<{f%9U)mClh^`y+g*ir)x)vpq1C-71yJ1?It?&Iz>I1 zmON?SJ{HA!9V`0z>?iL1EqbZD-yDidi}%vgqHpy|#mkknkCpbJH-Ge2)0-T;%`X2? zoC!4gHvS)dp!=`huKrhU-v8P6>wo&gW8BQxJpcZ~@1WNI^i9F#FaMzb?55zq{lZ-K z^vemb-FN&??rvne-Lqe8=H1Uq`o-q2?fY1cJH7jO5Znm5j|cAU`v2Fb8ofdK-`+IZ zW5m4`>+btRAJ@Is?bOZT|Nhp|9&wQUul40Op8s+?X`e^Lc`r=+H#d}T##D5-d3h>T z(ha4%nT&pRQ7Jy3pF4U-H$HE0U$c1hZnlH;&)gaQo6gKz;3$dz=1tW$f4gIb%X7MI-~xm%Wh_6>gd8)Q&jJ^i@7 z?p^Kw&L?o$%>MmZ*d2#T#Vb|f-p2px6aC;8IJS6PQTJO_9h)}q)hxY5jGY-Z(_8fF z8~n6-)y$t(Yn=Jh>NWM4Rcq23a&daq;9*T0>v1yNBM)gaYSieAn6?eO^=jO%bLE(h zz3lfnqQ5heUMqM`O?U#;GM{@5QkATiqH^X-(Ky>P(2HA{3#w;6R;}nuIAP?tA%jK^ z=%40(pC$V28tbLZXvR}|s@dU$c8%xhK(o!iW*K1kXh;RaIW7h6*(@UpV)w=f!kyFa5MCznUgl zuPFEG(L>!YCwO-5sRTc1l=VbvaH)I6Mjz;2>AJ33<`Z)-56`r+9=}S~lW3fIMMh(u zm3zT;g;~k=TbBRSZ`3sz(09V1827uIBL@xWHDF}_A$>;n8a`^|px_ti-dyh4yWbAX z_V&_?RyFITbvA-W&-~?qFg@#6S1a>ZlHs(+v~JqHSHmV9qt`Xde2~MgUv87ju8gr4 zDJ}ZHe<7HW^@22#GBCO~WAquIFYE2)o~3?;na`(b^yv(>_ps=L()Gj~alK59GG97- z*N#3?!_3PwnxLYJ9+t_37bBx)=99|El87AOWMt8FzaBknxMad`w<5tWAj?^XgBG-O z9+*WhqZw}`iOYO{ORt$8y^6P@`y~ZWg`e1)D|&mTH+klj8R@~5dI!qZ-FvXz0A^&p z!m>%Ip{K`ND?nx!)XaKqy4Q8^G%EAlvy^0HG0Dj0#JvIaY%^bNyqPi@=~crUsaEEr zxL3bk$5}UayalUey*z=A=&vdZL`F6d*(6kVFGv@6}ndhkDld%H@UsV|H(fc(I2j4{hqtMz?p<S9+veaqQ74IsMgv2&b}U>3*8$#T1-&%L!tZF;9jn#nOD0v zubyJoO8_AE>es_Ep}4ni@Eo$>xmzyxSkWgQJgA{wSSLuAyP}_E{)(LL;IZ9pxZRkJ z4PHGN!4bTa8Cm8sve0EZ&%8y-Lg(%axMwtO@TjrlGe6)W#Xv`mW%A0rqu}06qc4oT zm7-wX>nHe0HgQ?PGO~zeWEtaaWG{8}Vt3ymdh#~NaPKa`Q_c1!&U%ZwXRcRLhP&?* zJfgcf&`&a7ml+PO9xvMmhzwof-p*OCY4@|{?Yg8ju2n0|{&=loMwA`nq%A@KJrnS8#tiSJ%CL`de_1 zIdJsEY8A$fuFyZDx+{Ig_8VN+{c+vIniWP=9O3@JuU!9eqst8(omOE`T7~wN(<-<> zVXE8Dy#N&kjuq_aQ0xNfu)JNTOf10sVI$^#Z8bJ~C$_bef}2GwV*Lu`~)<_dT=jab^VM zqf*?*2EABWZ=ryD=7-&=?q0nvzfZtj-mH7Pu(5ky?VEMV{8*pC9o($Dr&;$(v+k6- zJG*)n*aiA&rep5VX5H7!c2|@8v$|jDe$~7~*j>%w6(fkj{l@68-0sNgzHRhZ7`)eI z{;GK|%d`w-yF)uH^QMp+i>&*PS$7{ZvTi5wo%zPkyrY_V4>a@6X0~^vtapd3yNbN6 zv+gKnz72zWn=#EBH?Eyl#@=-rjvbNKbVT0){rkIn@SXWX?dW?Ge^_1i-@k9gxUa8? zx#WJh-;JG;>b~NlWVS!Sw?Dvdlv-w1WOm}5gt_5)@$>!LLkqk+;ugimG_2(wv5)<^ zcuZ_1_fx-Sg|-#jHf-50CO%iVZK4-R$Q{ZXn=iJ2S1`6vY~k1ID~r zhi}XLI)>okTisWV1V4g@uXJDe!nUVh#(fn9+n&CA)n#sb_(JzJG{KMH`k2fwj>vpQ z(Fc1m?n~UW{qSNkpOGH!{%&ZtA6|@o0ZG;mFDCODN28bZjI=L*ZFn*6%Tu!b@M7Fo zW@P)}#pH`|U-c4wt=ro_w|o6uo$cZF*VU^0Z8!Vd?)Rj5{ z!cNzh+3BuZZKu0#gZef*)7)Q?)wXYb87c1m3aqxhTiA68cDn2G+UcHN2|L|&6}79| z>8=~8z1>cC-5xvLb%*VAFXxwbx|hrTMLc^t!yRLLyzzFr$D3}a>r3o(kN>0|Ztq9- z@LhJghaa-jJ^$m{r|fjk|D1NRdv~y>o7YZvU7DTlx^z3;b#=6x*y*mjNqe%L?z)+F zy6YCHueQ@&w?TW0o$k7w+Q;p5*PXJ{U3X4B0 z#Khd7hmW<>J)OyRx~DT&{T@5r(|J&Py`ApqY}Gzsr@QW5JKc3B)xWdTUH6-IoV!`D z>r(A>FHb2u-E|f1bl25ZZ(*mquCw-ycDm~ZYfrb+T{quOcilbemEG-`U02Ue_w<|D z>8`uMPWS6wsJ`A#cl{fzh<@Hh1EQ+oJWJ=}d!Y4rIdxOd!$ zd%k(?bkDb_o$mRT(YAjl%bsr=JKgi`rasb6cim*|nRdGCmf7iEPxi&T=3<>5zQ<1Y zboSZlp3Zyfr|fi3=bZM>cDkn%=WfpJ<$2hB{IKgb*y*l&&Q8}~vD005Nc%lI-F1#_ zOq{!^cTXlJF2DP#N1gd}7P8ZQpmL8I6X#+Xb^F+Dk6&G9U7d||UZ=B*&VD+F>KvnU zn$Foem*{*%=Vo`iWY6a%ok!g5gY8drUU0tv+p*5Oodw*7Jv*<`XHN~Y0&M@Nv%LGY+peW^toym`X*##LFW|KOs?NU(2Rq5V&aF3bZv#6! z=v?65*0%4{dC1;&Zhx#Zf5~89rSry8!5*UXVfO~G$A4PqSJwplg3gK+f_<&d@$L;} zk3U1__KaY^t}~`;uv2t4s~+r5Iv3Uq_We2!*ADh4It#itygmJ^b>37z*u!)_+A!Fg zb$;DA*uUsZZx-yjIw!UW_AH${S_S(}opEi0okM4f_QCF=b5Vz2KcMs7PQm_EXW_2F zF0He7w_uOZx$cHwKcn;Pjlup^XXReOuCH@apJ30?xzjilj(uz%NCbyBb!>YO||*zOA4@xSIcObe234>$nGT29TrhXpmB04*N5$rxXSDX&^V>(Z|f6ByO-fwl5IveaNI){H3>|1nhIT!4g zbzVFlZ2!mLtal+eTkD+tOR(?Kx$oCtzppdrAHlvtXV<@i-B0IA_ZgMFe2?q=%>8RA zw!ha|#(mAQ?P@wly1%n!`&OM>6N9~5=Wj{D4krg^gVf+`t8;G7U@z5qAa}4o)R{Y9 zu&>nFtw68`=v-YW*iYy@<^DkydwG7)d5!y*S!~zPIXW%ax9NPYM6mbjELtkqWp$?8 z>Bq#>*KTE}`&6`@&Q9vRb&k+ES?4^R_vl<>r@Q_Uo$J+~)wxIK+d7ZyJY%POIf|AJ z&MG?V=p3tap3c=eAJe%*=VvXBVAAb>6S@pw3e|ztx#mPESW?8=YNrF3`C~=V6_v zbryF2?t#4=89Hn09IbPX&TTpm>Wp>&0)SmtP-k(SU33oBxkl$!onPwwQ)j&U4JLa! zwRN`FIZNkqop0(qtTWF24RpJ%kj@f1yXqXKbG6QAbbhJxPo44ZuXx+jsim`>&RIH_ z>pZCQl+JH;mT-S}+ODsmbC}NQI=AZFuk&4<3GT0<+I3gx?5J~)&IfcJ)Okwhw>pcv zzqV`FSJydM=WRMS>wH7!J34*$*H-Pi!aCdO?5FcSof~yNuk(z~KXvAWp=NgVJ7({5o6e?5%T%&Q&_M==@UW?>Z~FzprRdr>4$fI%n#MW?UxX!C}R@7Np z=e0WP>ujO3jm|DQyX(wppQpK(-+g)%J&Wp0)9F49iS`Vg^>ju*PjuJ0yY113chcEI zr@MO{?L&2r)Om}}+jK6|>F(}DAOB&U>vV3^xkYEZo$iI^<#scAo%?h$dXBTtGx_xt zaJMV!F%`$%GGct6zU~}9HaG|KGxx_!<6|n?pXbC>>^p8;Ohxx6P!%m!y!;DUqP@R; zjfMN7mw}_)CDEVv>DzbgfQi9XL2-WrE&J><)_zk`Pd9jse=Wo9?~myzx)&^_Vn6qn zod&qC%*pm#2afGC!aY*Mj%_RU89#pPkiHYfyC?fU{^35Qb@xJo-!rg_+^39}{cx|k z=#S#=|MqxZF#qN8>|yq!wEHi?{r7+NciNUr{{iKB=hObcR%ME_tTit?&;b42|sw) zY!|XWz2(`SUW$7dFQ2_na*aKW8t&=6_io3j0S^SFoc>)r2u?ktaXNAyR+u-KT|40rOp?BspL9^Aw|Ub+kJ<|d}F`_G=9 zz25D0!uy8%Y0UT$?jIbnpXdiqFPGcdA8(g?`99*2+{xo*|ErUgD~_s^Q6s&2&GgDO zD_2W%f6|wpk?sH0t5;1+t68;1waRJsqjzLl(>Bfc%f9xcW8Lor@^o#NX&zmEaGOvj zrjWbkOyAo6r_p^H|J-+cg|-!1Rc!5Fm_B9C#ZbfKZ>A^jxp*k&o{O)f``=8DJ$x~g z5mWB>V@ZQ^X6(5blhNT~a-BX+gP$eT3C>XTJo8SGmPvzG#QyPa`=54oF5J3cs{?&@ zyQjiaXmmc$RWUy_i0yK*xO?jEH#2`|nC<6{qCan(ZV%~lF|9#Ti-eZ$=MCM<5tFBP z(%=W&(@o#uo^q%CeMUErdD(tlF*)-$czNErMlXe98Z=Fw9+T|uuLmwdu}dA&aPYIW81_$32R-);)q(K2JmY`6~CUz4W|x6XY+p z>to{^xhEMP3YGHhAB+v#ccm_^?=*0wn;9{oGMdHQtQ-?6t9gZ+RboQdXcl#|YD}n{ zW)U~5#e~Xh7Iw3``)2Bzh1{$W6RN0L(9N1Lp-P$s+^prkADd==H#6Lem7$%_wtKlM zYv;A?Ua%_Kd2G9vtg3cy+wMiHrk%^Sd)caM=d|r!xEk6yY`d4Prgo}r_u|#kPO}HMy?k}G6K%Vfuby^-ZTIrk*ACluFJA-gc-!vfYpCtp zb}wHe?T~Hv@-^1>Y`d4QiFTaZRou(hR6EwTd-Q2iYD!2uO$lkQDIwQsN=OGy3F)XQA)PcOq_d`k zbkRgeS8aq`uZ@sy+6d{cjgT9(5z<2&AvbCxq^CAQZqi0bFKvYM)<#GlZG`mIMo2$x zg!I=&$N+7G4Ae%*AZ>&U)<(z>ZG;TfM#wPjKuAmP8~654tZ6D*1wy`ew?v`gVUuG* zM*H>;O-F@{(WMeHR#QU8X-dd=O$nKxDIpUzCFEvJ37MoRA-8Bs$Yf1~+^UU`DcT6R zO&cLowGlE+8zIxR5i&y?Av3iRGD{mFv$YX2M;jq?wGlE;8zJ+x5pugWLKbKvYfp+6Y;q9S9lerMM3!iBGu?IH6I2kRy&p=&rEIF(LQ*_K%Q9g)Gyh z5^|rWge=#Tkoz?yWQC@LJfJBdD>Wr#m8OKO)|8Mnnh1GN8zB#ABjjOiggl~+kVmx< zvQ`@*>$DN_m^MPzYa`@wZG>#lM#vM|2zgQ)Ax~)|WTQ4hp4LXlCT)al)<(z{ZG=3d zjgYO{2zgdJ5VF*(?IqWv%o94ZG`-&jgX(T z5pqErAwO#)eNl(evG1f3iuLVVTO`|OGk&bD)^}2gXX`tugxUH|DhX_TCzV9DzLQFX zt?#6g#MXCGNoMOisid&=om5iUd?%G01iq6>P6FRaB^QD3q>`J!cT&ki;5(`0CGee8 z@)7t>D)|X~CzS#OzLQEp0^doc5P|QcQkcMZQYk{HCZK2t0YyUzC>lmU(QpEaMi5Xmk`O3r z6YDi|Kq6b+47HV_y>?qP%6*xl{RX&GG%nV+Z_N}{G@k3FXaZY`CbFgIX0{YfVoT92 zY$=+|mZDqPQZ$7vMYpk0G?jp&X#^BaC!lBs0Yx(jD4In;(QE>W<`7Ucmw=*q1Qg9D zpy+l2iWU%1bO!-N3kfK?lYpW{1QabMplAsJMRyTUbTdG|*Pp%-Gq=F1el z6zki!hKnlN$@Nn7GFysvv88A?TZ;CurD!i(ie6z$(W`7JdW|hbud`9~1_4EH5>T{{ zfTH~b6dfR-=pX?_ZxK-RHUUM42q=1ofTF_$6dfU;=v@MejuKGx9sxz~6HxR40Yx7Y zP;`udqK^nDI!-{*$Am!9i?Loo_ox4nAM6wN9a1#PKBAq74Vy1h^jWNL-&!!L=yR@@ zqEl=s`hqP*U$Uj>G+Teihd%X=mG&nKNC>&3jswJ2`KuNfTG_BDEgg%qCW^I`jdd7zX&M0L_m@II->{N zTRs$vqF4fo;s}AFld;}S4oIY@-TZtiMT6{y$%_k{FH;nb^X*$xMinJ+y%Z&~r6|Id zq9nEyC9|a{g)K#?Y$?jYmZF?&Dayr0QEmc?@(@szmw=*t1Qg{bpr`-=MFj~cDnvk0 zVFHSZ5KvTVQO&+@HRO;^TtP^at2&QJJ`~`7%Z2<9z$prcp%|xL%4XvZbgJTZ+=zQk21#qRMP3 zs=}6{s%$B$#+IV$Y!uZXpr|GRMYRYhs!c%AwFDH^A)u%(0Y&u)D5_6DQ3C>s8WK>{ zh=8KT1QazPpr|PUMa>8(YED2=3j&H-5>V8NfTGp}6ty7)imr+CzIH$&`Q6tKg~~}$ zf_dKa)>)BG&jV(pp*-~@^TZ($H zQFJ2#MLh{9x`}|IUIY~NCZMPf0Y!ZYDC$Q*QGWu81`tp*kbt5=1QZP>plApIMMDWF z8b(0TZ~}@(5KuIdfTB?Z6pbdJXbd4x)IQEjcR(Wcw{1h$Ns)cS!qC{bu=z4Y6XSgQ z*2+;uH*>udO=3&YEo>>8%$A~C*-|uxEk(DnrD!T!il(upXgV83GYBY}NkGvo0*Yo6 zP&9{tqPYYV%_E>_J^@9y6Hv5(fTBAHC|XEB(VYYoEh3<3F#$zO2q?OXfTFtzC|XKD z(LDqd-Ah2xGD4tee4IDY0f`*64`LIf$i7)@=)SnH`7%Wh#QFD?k)oAcFGZ`^QnZ>a zMQhkn^dMV`9%4(;!)z&fge^snvZZJ(8%65~D0+;5qV)t6Jx)N;1_FwnAfV_;0*am@ zplBljMNbn@w26SC%>)!}A)x3P0*ba0Q1mPTMb8mX^gIDY+XyInfqQuGyDiq5d5=xeqVeZ!Wbvur8)mMul!v8CvH zHj2&>Q1k-Iry|4MX>}F#Su{C5l|E&pvWf#iaw9?S~wt)0d`w-N{TMni1)(g%M?XC ze@G=MO5%DcN@hz@3R{X&*;15)Ek!xmQk07=MY-8hl!q-vdD$q+M?g`20*VR{P*jkB zqCx}|6(*pl2mwV!2`IXPfTCgq6kSO`Q5pe7#R(`XK|s+}1QeAdpy+A>ib@esRGNUI zG6WQrC7|dULZB$Y^A+t4YHTU0&X%GYY$>YAmZDm06xAl6=vo4b>JU&=mw=*r1QgXLpr`=>MGXlk zYD7R$V*-kr5Kz>VfTCsu6g4NHs09H9MDtO+z z4oDXs2f{~y0fL|2DTLSU`x@B zY$@u=mZF>3DC$K(QEvi@`Vdgmmw=*v1QhirplARAMFR;a8bmJU5KuIffTCdp z6b&b!XaoU8BMB%PML^ML0*b~EP&Af+qHzQijVA<(I(lB=s!q{#yDQX5iU!!d>j_@i ze3_zKJpbD2QZ$+CrRY|+6is1E(QRxgn#z`2K)&X%GXY$=+_mZDi~6wM}}Xbu5I za|tM#M?leh0*Y=YplAUBMRyQTw2*+JI|(RSL_pDE0*aOpP;?goMRyZWw3L9Ndk84H zmw=*W1QgvzK+$pnitZ-_if;D2-VR9QJ%ckziVhj66<*kUnWEL6Kg0bs#OUW}Yq(yD z9%M_=Lu@H}m@P$*u%+lxwiK;pOVK*E6g|e4qV;SPJx)N;1_FwnAfV_;0*am@plBlj zMNbn@w26SC%>)!}A)x3P0*ba0Q1mPTMb8mX^gIDY+XyInfq(95m59#0Yx7W zQ1l@IMaKvz`iOv{;{+6aOhC~I0*XE%py(t4MV}H-^cev~pA!N_yFKr$0}?52U+cI> zigwy<(J3!%zD&_qo}W@ziq3Go6n)K>qHowzbe1he-?F9XJGK;k&z7QdY$^JIEk)ex ziY1^Zj({SMfT9oqMLq#V@dOlw2`EY+1d6`&yvhzpB*T8Y`m_{Hw|m!#p|JTfMJXY_ zQ++8)<$5W~!Iq+&Y$?jcmZIEjDayl^qP%P=%Ey+X{A?*Iz(!F)0*VR|P*j+Jq9Ozo z6(ykP3Id9X5m0m`0Yzy96cs0+s00B;R}oNDl7OPC2`DN>Kv8J|ipmgBRF;6EYX~SR zM?g_|0*WdS0!2w7Z;}HNIc=ZZCx?R1^gG!{w2Gmy`7%Y7L;n2@rKk$mOHoy}6jftO zQFXQy)nH3eO|}%(VoOnNwiI2QMS}?_8bUzPPy&jE5l}RofT9ru6pbXH zXcPfOqX{S)LqO430*b~FP&A%^q6q{PO(dY`WcssqL$H5*g|3R zWs0VR{HvQu(QRBWMN`>QG>t7q)7erqgDpif*-|u%Ek(20QZ$DxMRVCGnnysWIM0Yw`LD0-TJqD=%8Z6=^- z3jsyX5Ky$0fTCv!D0+^7qUQ-H+D1Up3j`ExC!pv>0*ZDJQ1lW3MLP*7dYOQtT?7>E zCIpJsguEpVNW{LYLg+y$nrI)<_JqRb%M`s9@;A4VqSv`zir!#L(VJ{3+Q*in{cI^Z zz?PzeY$&GXjb}C!pvQ0YzUBQ1m4sQ1nX3d(Q!hl(G+E zuS!w6-PJxF3Y#xe^i9bBrHvGw<$5XlmMul!v8CvHwiKOXOVJN(DLT)Vq955(^b=c( zF0fJbGXX`v5KwfHfTCXsDEf_nqTdN9`h$R?KM5%Mi-4j_1Qf;i`m`NIu>=&w5m4k2 zP!uAd$S0sEo`9k-0YwP}6eSW+6d|A}i4Z6{6Y`3-b&AT^*E)VJMYr2Wv}8YQzD!Y0 z->=(VigIzi6y;`1k^7$5!51P(QC_wbl}XYnf_7xVxtT{Y`#oU zHQ%4rL5iw#y%g18OHoa>6xCu&QEj#qUCWlDI&3Mb%a)>gY$>YGMo|L-iW(A7)QEth z#sm~KA)u%!0Y%LSC~8hXQ40c!S`tvyihv^bjpc*44T{SfTB(W6m=$`s0$%bRK@q!J0KDFuQIxS7Ep@pTN#DA`eE~Bif-`zH{Cxg9Q|{& z9$YU)H?pOuCtHecVoOmkwiNYdOHm)T6!m3GQ9rg6^=G4K00Bh<2`CywK+#|ViiQwS zG?aj%VFVNnC!lBq0YxJTC>ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}qx|x8YNdy$# zLO{`ELZGOd?|tWhL~7ezq3%*t-|i&c>W9sjDVpZ{Il4;Gbgq}88Eh$<$(Ev7Y$=+} zmZCXqDVoccqIqm7n$MP^+u0~uKtRzQ1QabKpy*BliWU)2w3vXRB?J`RML^Nr1QabL zpy(a~itZ(#Xc+-T_YqLEoPeVH2`E}YK+yvP6s;tnXcYlPs|hGtLkJYz=6h8gkcj)o zh+{%irD(X_7Cq>P&6g>9)c3n|lcKd;FGcIvQuG*Giq^BG=yA3bZD32$6KpAZk}X9~ zv88Au8%0kOP_&7FqRj*pZ6ToO83Ky75>WIk0Y%RdQ1mWIP0Y#Sx zD2j>KJ!2Hb5>OOJK#@m4QHX#dpMaux0*b-}6eSQ)lt@5Pgn*(X0*aCeC`uuqD3uT> zI_rD!J)I)^bJx(fQZ&`>YUhX#n=ez8C*CjJON#Pxy%gnROHqEd6cu1gQ9-s86=F+K zVYU<%VM|d_wiI2#Mo}>WimoJ}D2;%k;sg|xAfV_f0*Xo!P;@l`MWqNRDosF983KyR z5>Rvv0Y&8qC@N1tQ3V2uDiTmsiGZSX0*W#SD5^|AQ58a;69S5w5>V8PfTHFE6ty6rs3ieKtq3S;O+Zl_0*cxaP}GiqqV@z7T}MDs2Lg&Z z5>V8MfTGR>6m=n>s4D?Q*Ar0GjSwiR9`D`lfJBDb2eBGbw88#3qdTg*erze~&z7PAY$+PZmZCvy6b&YzXb1sCLkTDvMnKVU z0*XcuP&AT&qEQ4CjV7RI3;{)B2`CyzK+$*tiY5?HG?9R!n+YhIL_pCk1Qbmspy*Zt zilz`ybQ>X1)Fa;ezyXP@vafZ#QHqM$N3^N&Ve@5*X2$!!4v?Z*TrWkl*-|uzEk$$L zQZ$b(Mf2HGbURy$7O zplBHZMfVXkL_pEQgh0{sc(2$% zr)aO;7R`{NQ1lbF_^|mhMUTb%^#@DQdajqE$JtV}fh|Q(u%+lpwiG?ZmZFVpDSDbM zMVr`Cw3&^fEd&%jLqO410*am`py)XQik>H+Xd3}VFAz|)oq(bj2`Jh@K+#JC6zwFS z=w$+mb`emtn}DJ{1QhKhpy(9>ie4q4=rsb0UMB>K*2a7N9gxThyZKosMR{$!5g#^R zrszPtKWC^E9pri`dW$VZZ?mQ75L=4gVN20rwiF#ipU z1Qf*)P~;I%6e6I=C!i>vfTAz~MF|8HB@$2+A)qLUfTCmqic$zDN+qBu2LVMn2`I`% z2o!xE@11i%BE#(F=bRMXXZNmihr{N}6y*>5xkgD*0j`&#f@~=&#FnDMY$+yf2o&WFd(|C~$Q$;Thw_Dk z&-8z@8>SlJu=z4Y*M|M;$4F5fu9u>^Y$>Y8mZJJ>DQdu$qK0fKYQ&bJ#%w8S!j__@ zY!o#kpr|PkS-^#l}kBcP}|0Yx_uP}GAED5@3qrZ^yx6K;lTOVOQnTXbVMY`#oU@36mW zoD}updMWD5mZE-aDeBLbq5*6v8pxKSL2M}+%$A}dY$+PbM$s?=iiQ(VG=hMlkpvWt zBA{qA0Yzg7C>l#Z(KrH%#uHF9fqCL zK+!Y;il!3+MK^`LJq}1DzkOQPON#c|7h%r`hs~EMniKXvci%iW`jsJbxn7Fqv88A} zTZ(RHOVI+h6y3p=qJ?ZJx|1zMi`Y`Mn2n+(1QgvxK+)X<6fGs7=pF)!?j@jT839H2 z5m2<8fTH^eC|W^4(E|h&tt6mm6#+%72`E}aK+%H)6g@;h(Zd83JwiayqXZPKB?O9Q zg}sD{PSHbdhGt9A)AkWB*iv+uEk#GzQuHocijK0S=smU+z0a1S57<)lAsa=< z2q^l9fTH6B6n#uU(Fp>IJ|Up!BmqUA5>WIR0Y#q^P;`obqAv(2`jUX6(*zWKML^LR z0*bySpy(R{ip~;H^eq8J-w{ysJt0tZFznsqfJ8dlU7@$6Xsz8AoePJ}mnr%w>_0n2 ziY{=y6#dMWqF>ljbdfDZzp|z1H?|c0&X%G-*i!T-TZ;Z-qv#R=MKKBbv>ipU1Qf*) zP~;I%6e6I=C!i>vfTAz~MF|8HB@$2+A)qLUfTCmqic$zDN+qBu2LVMn2`I`%Kv8Z2 zit-Rpl$Q`FIv@6qIUtcd_JwIbN>PfD%9ju}U#6%~g8%zeDJsnMQdER3MMc?CbOl?A zim|2WO12cGv8AXuTZ&4srRXX)ib@htbTt7*r3ff0O+Zl@0*cBKP;?CeMdb)6Do;RB z1pQl$fTDB)iZTc&s!Tvp6#|N?5>Ql)fTHRI6xAT0s3rkLwFrTt0tsH)G^ePB zeUWUzgy1v%7wjWi?S!!TGDY(9x@dOl2AfRX>0Yx_xP&A2vqFV?knoK~^tppTJA)x3s0*a;*P&AEz zqUi(_%^;v?CILmW2!WzL3Eqf( zC7|dP0*YQGpy)LMie4w6=nVpj-Xx%C9|1-C2`D;1K+!=$py-JNuciYMY3F9>Nh$K| zBidUDVe@5*4k!5C7f8_&u9u>B*-~_rEk*CKrRaUO6n(&!q7T_pbc`)UAF-wAI2%PD z6Hs)5fTB+bC^|_%(We9yeMUgh=L8g;BB1CC0*byQpy)IKMPCt6bcTSUuL&snhJd28 z1QdNsK+$&u6n#%X(K!N&ejuReJRwkYD8ZZRfVdkU2j?9rT5P|O{bNGde3_zO68tp_ zrRXBpOVO`vDf*2qMZdG9=nu9O{mGW1zt~cAi7iDjiTb=Q4#?~$pjRo5Kxp#Kv50?igFTAl#76(+yoTmA)qKP0Y&); zD9TSjQ2|1r=t6?`iUShqYd1eXOVO|PTaX14!{*Br6;1TNSR_SPaJ>{2V@uJMY$-}( zOHpyQ6qR60(N%0ID#@0jtJzXiijAVu1QeAapr|YXMb{8eRE~h6@&puBAfTus0Y#Mv zC`u=wD1(5a$^;ZuA)u%#0Y%jaD5_3CQ4Io$Y7$UXi-4lq1QcCMKv5k+pr~-77g_8S z6|g(hMG}M0^jk+iVM`2~FH_Vo(JyzG6gA>{DQe7?q9$x9YRZL+^FIUtc%c3adyiq^OfaG}15 zVe@5*1}6GrmP*keu9u?0Y$+PTmZG6-DH_I>qTy^Q8o`#Lk!&d%#g?McY!rRwA0Y#GtD7uA!qR9jl-AX{w6atEFBcNz10Y%dYD4I?{(F_8L zW)e^|i-4lp1Qg97plB{3P}D!sTjqd7w%G4F4v?Z1_Qgi?62s=p6y1^NKYyE8dMVn%mZE3aQnZyVMbEOO z=sC6&J}?-boCbFH>|h(Qmv$ir(XTDSDqRMIW%G=tH&?9b-$;M{FrN&X%H&*-~_Z zEk&QOQFM}kqE87Z`iy|0&j~0xML^LP1QdNqK+$OeioPPC=nMfxUlUOD4FN@G2`KuO zfTHgRDEgj&qH_ck{Xjs`c>;=lB%tUg0*WpW0!2p>y}=GhJm} z(Qk?V?JK3|cdnPBKiE?ACtHgCVoT8_wiLN9kPH6hCn<_$OHmwKiafRyh1e+a2`Gvu zpeRg0Q33%)i3Aiy2q;P-peUJuq7(v(QVA%^K|oPX0*Z1GP?Vd1qC5l?RG1Jbx|rx~bU-2p?S9d(QdGo7kx1BlnW8Hr{@bgiD2?l-s5o1S zO0cEqDz+4rWJ}T2Y$+V8MfTGR>6m=n>s4D?Q*Ar0Gjew%=1Qgvs zKv53@if$yJs3!qMHxW?Oi-4lu1Qhilpr|haMg0gU>Q4w1HHvt(9gv9qOGTl^QuMfu z0gCLK+!Y;il!4#G=qSmnFJKgBA{qC z0Y!5ND4I(^(L4f*<`YnKJ0VasDB?|bKq77J=4Y@JJ!*H77DU44%M>k&_z$g>qQzV< zMN8OHbQfES?q*BTQnnP`!w1R-52M8!yNkGvm0*Y1> zP_%}Cq6Y~mdWe9chY2Wpgn*()2`E}iK+!q^iXJ1NXgvW%j}uU|fqY0|XQuB%tUm0*c-ypy&_*Meh($beMpmBZNTF=7^WP-YL3d zaJER%{n1a@B4P7oiav<=6*frGhg>g3$JkQz5nGCmv!&=`wiKOUOVKB6DLToPqEFdU z^cfpPpA%4Yih!ao2q^lJfTGg`6n#ZN(HR1Yz9yjP8v=^X5>WIl0Y%>tQ1m?kMdt`8 z`hkF=^8^(ANI=m~1QcB$py+1;ihd!W=prFd^j^g4=zv7NGC1!`(f9V7N54kG=F1fQ z8S%$GDMf#Ay%b$yOHoXcK696%Shf_!v8BjkOHqg|MLt`K;@MIZW}_&9fTBbKiXsFQ zB@s}ROh8cz0Y#|<6y+eGC?^3$xdQ$fu9u>cY$>{$ zEk&i+QdF8PMP=AhRF*A8*RZ9i99xRYvr$xmfTD^76jdUiD4l?!3<8QO6HruzfTF4d z6jdXjs5${fH3%rGNkCC80*Y!AP;@N;MRf=$s!KpoJpzjA6HwHEfTD&36g46Qiqew2 z6Ann^sNF9ro)mnhU&-!jH%z zwiLBzOVM>~DeAyRQAYxbIuTIRnSi1$1Qc~8py+x6inlUO(Le%<1`z^9O_RKmo1LOX_QfF0r05R! zu+ZS7u=z4Y!;}1`&q&b-u9u>bY$+PWmZH&YDH_9;qOoi#8poER@oXuYz?PzkY!uy0 zK+z-uif$pGXfgpsw-Qh^g@B^l2q>CLK+!Y;il!4#G=qSmnFJKgBA{qC0Y!5ND4I(^ z(L4f*<`YnKI{`%t2q?OPfTD$jK+(`7Z>R$j`QH8*f0z_?vpY$5CWXzHDY`4kzvEdc zx|{2zXenEY?qN&Oy=*C3#+IV{*iy8dEk*aUrDz3PiXLF2Xe9wfs|YAsO+e8a0*W3a zpy(k2iXJAQ=n(>n9wne?EdfRA2q=1tfTHyT6g^Hr(FOvFo*~cfBPkY`#pGuMtr6Isrv*5K#0c z0Y&==DB4dz(E$RA4iZrG76C(95duY9lf0iD zkjPep^Q;ujj()I z^dkX9KM_!LfqQl)fTHRI z6xAT0s3rkLwFoGxO+eAL1QgXFpr|eZMfC_Ms!u>s0|JT~5>V8LfTG3(6g45Bs3{>( zbXBtVh656L({77OCI_GC7fW`dS#sEXnW9$7{+V4;)SBz1s0~|++Onmn9b1apv!&=d zwiI<>OHoI*6m?=tQD-)ax)4y*m4Kq_2`K7DKv8!Bif$mFs0RT>Hxf|PlYpX|2q@}B zKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRln^Ltk?f`Jc8YxaUB{ME zWdGnyXjpRCe3_zA$$q81QZ$1m zZYQ8<0RcsK5Ky#`fTBAIC|X27(PBcNXhgEt*#U`EwmZ}#rKpLGCCOp)Ws2@e_9wh5 zMfY;O6fI**(S2+wTF#cD``J>of-OZ4u%&1vTZ&e(rD!!9MQaEsdXRvkhX^Qon1G^3 z2q=1#fTFbo6s;qm=rIC{))P?lH~~c)2q=1jfTAY}D0+&3qKyO;JxxH-CIX5!6Hv5; zfTCvzDB4O06y2Tdt#Cjhr|mQSrBXC5`UzWd*nF9y7n1!KUzeioTrWj0vZZJTTZ&#{ zOVLiY6ur!rqFrn$+Rc`tJ!~o3%SO>F1QfkWK+$Ui6unMB(HjI5y-7gPJ_3sN6Hs)3 zfTDv06um`2(c1(R9U`FU9Ri9D6Hs)7fTDK^C^||&(R&0Gy-z^V2Lu#-NC*@?pX{A< zKqAHL=4TuCi`>IP$CAV5%M_hR_G9-+(I;FlMJL%(^eJ14K4VMK=WHoD#g?Kk*i!T* zTZ&GzrRXa*ip~&F^fduR-w;rAmVlyf2`KuGfTHgSC^|<#(GLU^ohP8^M*@m|BB1C3 z0YyI(Q1lA{MHdMu`jvp9-v}uBoq(c02q^lKfTF($fuiHdUMUA8@__H)d@Mz8*=^CK zE{D2gNQZD~Y-)BovJX?ywY$-}$OHm?QiXv<&N@7bxj zl>`)}5l~c|fT9uv6kSCK6vd`^!yS-F6Z-?$xRl^?v^?%%p^_(%Dj!!Iq-RY!p=?pr|SVMb!u>s!l*r4FZa4 z5>Ql&fTG$26kSU|Q5^z`>Jm^?kAR~31QazOpr|1MMU4n3YD_>;69S5w5>V8PfTHFE z6ty4(ib|z;TO5!`S%XtrihlLnXqgf=U#6&Sihtyg6t&}eDQeG_qU+dF)PXHU9obUU zi7iE)*;3SnEk#|~Qgl5VMcoJ}>P|q>4FnYRAfV_*0*ZPPP;?UkMZE|p>PV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*ZzbP&AByqTvJ-jUWVyTBmpy9gs*7yDe%X zMfTf7p^+(J^JR+0ruc=9NYOa1m!k1(DVo5RqKRxNx|uCSlh{&p3tNgNv!&=(wiHca zqv$pQil!1!G>w3w=>!zbAfRX_0Y$S2D4I<`(HsJb<`PgekAR~21Qgv)K+ysMitZqw zXdwYbcM?#vh=8KS1QabHpy)0FitZ)^ibkh+^&F7MGW+_XF;Z08?rJYh37aodbYF_! z>!=hh=Xxo+pDjfz*i!TWTZ&e)rDzpfidM6wXboG69%M_=Lu?d1OhC~i1Qb0=K+#$P ziq;WO^cVp}>j@}&oPeSY1Qb0%K+%%~6g@>i(MAG_o+hAZ69Gk=2`Jh^K+!V<6m2D- z=ve}ao+F^>c|xG*-V|@P0}^@Le%EoC6!o@y*V|IU=F1fANb%RcFGVkLy%gG+T(H{g9{YgO4Uj!6gBA_THRiBunD3%Z?`Xt56dCVz#(Qb=Q zO3?|scO91+HeaSFKGn}SE=6Ikm!br=6eY5yD8iPaB(@YKv!y77Ek&tpDayf?qMU3L z&5BA}=+0Yya!C@M-o(G>&~6(gYNN&tHj1hfP*j6}qM8I0)gqv% zHUUM~5>Ql!fTFqt6xAc3s6GKj4G1V|NI+2|0*V?FP}GEgqNW5CH6x&?IRQm22qP;?^!MLh{9x`}|IUIY~NCZMPf0Y!ZYDC$Q* zQGWu81`tp*kbt5=1QZP>plApIMMDWF8b(0TZ~}@(5KuIdfTB?Z6pbbXirS@mpE)3r zXYK2*+e^_oBQ+*9Y`#pCMK+!w`islngbUOh>3kWE>gMgxi1Qgv# zK+z%siWU=4w1j}7y9g+{n}DLF1QgvvK+(N~K+(8VuZ#l{xzgZ_m!ea4?|NBk*nF9y z6{&v9FQn)Ju9u>fY$;mBmZH^cDO$spq6gVh^blK$9%f6?BWx*pl#Qab1Qe|!py)9I ziq;cQ^f&=U8wegF*YSQS>SCYiznB^}U#95gRDbblDcZ&LQnZ^b zMSIv%w3jVKudt=)Rkjqp#+IVj*;4cdTZ-Ofqi7!iMf(XTIzT|tK>~{2BB1DP0*Ve1 zQ1lJ~MTZF}Izm9vy95*+C7|d%0*c-zpy&eviasQu=okS-9}!S=oPeT_2`D;2K+z|J zK+#L7-c|=BQo!yC?UbUA?aOCRriRUzDLR$vA3Y;QUvRw?eaV)h(`+gFiY-NF*i!U0 zTZ+D6OVL@j6n)E~O9T|fD2gSZD2{+4kAR{OAyD*Ls`r}%64_>O zK9{1QM#|3-HeaSFF^6B|tQ1AKUW$^~Qk2Y=q7=3irLv_c2V07AvZW{&TZ(eCr6>;@ zMR^G*%11y^egcXL5KvT*fTBVK6cr|*s0aZ?MF}Xnf`Fo81QcCKKv5b2Ma2myDnUTe zRRk23B%tVO0*XozP*j?LqA~;&l_dm_u%)OnTZ*c%rKl=fimI`ts5)DUYOtlKCL2Yy2q>yeK+&}X6xAW1 zs4f9T^#~}cPe4%v0*V?EP}GQkqQ(RiH6fs=DFH>z2qgS_LVZWutwLu=z4YopSh(os*)@TrWjk*izJ$Ek)O} zrKlTQin_C<=mxeF^PtXTKLU#S6HqjOfTDo} z6b&MvXfOdqLkK7uN1mZYQ8<0RcsK5Ky#`fTBAIC|X27(P9FM zmJm>M7Xd|g6Hv62fTDW{D7u$`qGbdW-A6#tazdbJVh%6&k517z`*XCLrD%!o#{D_M z=F1eV%HdbJAVsVH5901SI;uK;_x+yi*_mVl%p~+CK|q=iLa)-R^rEO}2oO31NI*ao z5U?N?Y*{Sv!8bof9IZc?;mHao3(W3c_%v=GA|}G z2?5TRqD^cmx`8c4o7qxyBU_4YVoTA@Y$@8pmZDqOQgkaDMOz6dx{ZLM+X*PTgMgxK z1Qgv#K+#4--)I2mwWp z5>T|0fTG6;p`vRO{&)u@o@Ed2H%gIjpV4+DV&=;fJ(&oW{4PaLalRDoVN21|Y$9Kcwhu&X=NZ*i!T@TZ+D8OVRgiDf)peML)8o z=qI)m9bik*&ukR^LO{{41QZ=4py&_*MZXbH^g97XhY2Y9gMgwx2`KuDfTAM=6#Y#= z(LV$f{YyZRm(;^{6h#OqN+Y1iC!i=wKv6(IQ91!dF+!;5i-iBV0}^j-aK4nH!}jfv zjAYDwnW9R`AUGmLl{sIEs<5Rf!Iq*VTZ*#TQk27%qN;2us>YV0>TD^h!A4O{0*Y!8 zP*j_MqB;Z=)g_>)9sx!52`D;>fT9Kj6y*|7)R2IpqX{T#L_kqv0*aatP;?9dMNJ7P zYDPd&a{`K55Kz>TfTCjwp`v)wZ{dK%3k^lUO(Le%<1`$v+n1G@o1QZ=lK+#YFiiQzTG@O8<5d;*CB%o*% zAykx?^yfJs@sI7^bsH&KV>e8rlQHvUicUxd>pgn|ZM^7-oG(S=*-~^8TZ&F*OVKH8 zDVo5RqEp#YbQ)WV3fNLKk&U840*WRPP&AoMi`}~( zCq+5-NdNR?%zT-mGm^pEX;QR|^QGuawiKPkmZIfsDO$mnqLpkZI-4y;tJqSsnk_|Z z*eE)OfTD8=C_0aTqVowTT1!CD1q2kWBcSL)0*Wpopy*-(iY_6bXgvW%ml9BP839F? z6Hs&o0Yz65P_%)7qN@lfx|)EZYX~U1mJljhlJt)_An`x!VcAkCT57jN8)XxGCMoJ=e@x_wWXyb-qNkI=InVLOT<1QewaP~;O(6eXZ2AfPCnfT9=yMHvJXWfD*nCxnW=PWrDnAn{^1 zqu)r;=cxy5*)j8FiW1quPgzow;69S5kA)u%!0Y%LS zC~8hXQ40c!S`tunECEHW2q8JwiF%5Mo~`!ih2=H)SG~! zJ_Ho?C7`Gu0Y&`@C>lUO(Le%<1`$v+n1G@o1QZ=lK+#YFiiQzTG@O8<5d;*CB%o*% z0Y#$;C>ldR(O5#LsBN}?vI7#|V0VSuNm0!1U60F-nJ-gxQg(1gQi@LId?`AGEkzU9 zQgkX?icVuoQ2|?uCbFfdkS#@%*itl^jiM<86crIrG?jp&X#^BaC!lBs0Yx(jD4In; z(QE>W<`7Ucmw=*T0*dAlP&A)_q6GvLl@L%=NimoA`=vo4bHWE;D9RWqx6GBDHvi&a|ka&*W{G2I8#Wpr& z$IO>0x+yz|RhOchIbVvlu%+l0wiMmUmZGg}DY}gKLJG#5K#0W0YwiHQ1mbXMUN0r^e6#EI|(RyjDVtD z1Qb0^K+$djik={#=t%;Ko+5;bHfQ_CIw0|MAO3_TaE!vYEGhe3Yx$IzAO(}Yw z^QGtowiLa{mZF!~QuH!gie6z$(W`7J+RK)r*Vt0@IvYj%2q=1kfTA}ED0+*4qPGbs zdWV3bcL^wZkAR~02`Ku2fT9lxDEf$iqK^qE+D|~yCj=CIN~FN=PY9W!61=!fj!vf5JgBj-!ePi!eVz?Pz) z*;4ciTZ(>VOVL5L6dhtq(Qj-i`kjrU!vqxlK|s-;1Qh*6K+zEbivA{`=pO=#{w1Ku z%hAJj6h#OqN+Y1iC!i=wKv6(IQ91!dF#?J*2q?-VpeRm2Q5FG3l?W)ROb8Wym+e2~ zfW+^x+oJEK=!kt&tx8VJe3_!0oZ#KMQdE`mrKlQPimJ1vs0Le#YOV8TfTE)bC~8DNQDXv%nh;QQ3;{(=2`FktKv8o7 zidqm*)RKUrV+kl~MLojG5My0E3FD_e@Xv8AXxTZ($HrRX@e6!m0FQ7^U>^=6}}4*^Ae z2`K7EKv91JiUtr+G?0LzK?D>HCZK2t0Y%3XP&AZ)qG1FS4JV*z1OY`O2`CyxK+$Ld zipCI7G?sv(aRd~dKtR!ngiuk39KW9f5^rg6I!e*cc3U()CuY7((S)3!$o-4Nsqdqm z%K1`s8e57A*itl+Ek%WFDVoHVqRDJ2n!=W%BDNGwWus^s0Y%dZD4Ib)(M$r0W)V;{ zn}DJ@1Qg9Bps1LDqIm=q%_pE}0RcrN1QeALP_&SMqD2H0olZc}Vgibm5Ky#~fTA-9 zC|X7c6`h>puXRA;BMi^0*bC9py+x6iZ&5YbOQlJn+c(!Fh}63-jB#CPt?lo^T2?$KPOM4r2Ao=l9Y z?0MA^S0p^IR^t6^&#RYcSk3ct6VqyVUgN}_wLGs`;@3K!cWk0dea~x?Sl+<%+9#fF z=y{zJS&cofdt%fvp4Tg}p_%9POMKYE^9Cgvweq~7i5YpGH!^W|zUPfi9BSuz;}hLF zdftS@%FdoQG4X6y&zq8{+{5#xC&u*jyxEDXdwbrz#K(O-uQbtQfafhv%o^l*%M#m% zc;1S{??XLrb)v@z&pR)%YLw@#OFTcu^DapwPVl_T6XV8v-c^ZfPxicxiBBeY-VKSS z1)g_vVosswZB5)a+4Hs~{wVUidlEgTd)|)3nwg&WP~yeep0_iRUF>`#9ZAl=%zgYL$p^1+S3o5B_Xc+jM3Q~4 zaaTbkdHzOs9Ym6^Uhl4iNV587cP&Jcr`+VOhDdVr7I!^FlJ>9JH;yFjpCfM;N!q_B zeQYFY{~&OiNYegA*Y=U5{ga%XBT4%=6}v~0_K)KAiX`n{HR~5i+CNJ*D3Y{)S7>M? z`OR*3okWuMFMEuQB<-JO7#~U6->p9(lC-}ZePSeOf4lXRNYeg#;^~p3{r$4DBT4%U zLgz)2_BTA1Mw0ed^ev7g?eADy7D?J)lC>g|w7=zObtL)Nes>K;lJ@tEtcxV=FN(M% zlC+=nzdVw(AJx7plC+<--55#Q4@=$TcN&6IjIFhv6 z;3E+)dyV@|6TLb7Ethk#yE41D-&R$Zxo18OylS__Jum2x-ORP>?IZ4*Zs%UznQ{L` zHr9B|w^HBEN@aJf8MsF?kq%X?c{LqVFVZm_wYIv~iF8VhPOf*bS6FUup>vg0?s>1~ z2KRe5(nY5>v)AsbG0@&?lc|@Mzsbsa zlX|Tx?xdjnawICdOK0ynnR+JhylnkS^iFajk-=5%%~x&cUNg_VLbdi4E>zFj-D`VZ z_12M|wYj8CYiCDt(tFj~(8s-`Mo{6E(`r80$9>ppR(u2X-21LoG3b@-%GJ|V?ile# z+Tlj`U(}oT*z!&GoQaBhzeYxGa?hlm+)cWBYUch+^V*cvdZ}$M314o{*|`;;D(-yu zYQ8tc!AOhzRi&~QaZm1bO-<|8c?$~jrk2dhD_Jl(Z$UxH1jQsHIx`tG&64gi5@)i`$Eh;H2$t!AGP*S>Z%8cT?(&FOTlcyKXm|K!JZSv%T!Uc2k^4k=&D`?xM zZGJ(18;h-6Y&ExdZc(eE!bvk)<+o|wu9dyGwR`b@UX(Xu?&R4ErxfMQDV#ig#@zqk zFGk6dl8PURY18w1FPO4$#@yn*#S4mBm3=H0mo7+sNWzcE$OXkS-N(EnZ_K>H1+xY$ zoLex~{aU7toV~E5V07<}!#e!mxSAFfmKNDZ%k#o3dg{WtliTIDZ9Um26ig|aTDWj_ zX+i0dc||3yr#o?;ySk>#m|N#rBNAk~`#O>KLBbA+ zpotyQBjIeFdSP06+n|BVX)XtL^q1rYHSL+EdU@Xec=_Vi;me!-Z!b@s#+xlaO}TOE zz4(h-2Q}srMa8Zxm#?m$^%tYX|qT)O0U(mog_kk{2{QI>@Q-W<#6q z*v4M3I%hSkc$R%E?5vtW-R42nA#UXbb=^tj&mJFCZBUkT@`Bt(LDhPx5WaEyh}t_j z`akdF|KXxV(yInJ4T4CIv`X$KVs!t31q0d)^6Z%3xy_)0N#U~{+m}7tp>Nr<9Xsna z+jpk*=Hxc*!f~1$~E)Z5zJrew@;w?EQ5jwJU$WZOh(o z-wJP17qBfSbS!(VE~(43aBj(rX>*IFvwzvIBi~(^)a!R~ zuU1gt&TiMXAbbn??wxVM0DEf%_M1e%ty1UoDStEW!{A^-&TV)rZmh`5h~UeR6d)LYMYZzX)D!bRxBsqQ0~dZGL1>bwqRZ_HgD z-f3ICe!KF^(YNf3{Jy*^cfoarF{toa;Q!WbU%#SB3#Wy@8h0hQ_vLO*D_je@9PP_5 zn!CosS1X6 zH(2@Q7o?BuK+Iidsds>>lp6aT78b9r+YIQe9x+wYXvhZwv*{>qM!j;=er*j2_ZtM+q zF8@%u4`ld0+ValIulW4(Yd*iiRqw8y@Raf^nd>0GkACfT4cL3?Qg(UW$5$7({8p)* z-cpD1%M)Jpsb6*ZwVhw#>aK7#cXX$h8{{@EA1(G`dqeJ6_JQIZ>f*T@61}Kh*@w`5 zAb9oiE1v6=tF-KD?CjoBaT(O|>x5f;yNS@7bLa4eoxt!z=-zGW8TXOkWn~x1y)W17 z=5(yPKcd&?M0b6pie1U6PbA^zkN#z6yK6vivHTKn9lMW^URHKpx~m|359K!8?S*@- z)Ef_9)LR$UUCBD#6+Kt>D{=tC*LF9Pp1Xs)ApG#;hX;L@D`$~k?xKuhIS2O%)V=+Z z>BS35%RXm0b*Xn?)Kb@e*%e>*+134iNxh0)IVno+!xBDI!9w|UpI?6E=a*mmTs8Ub z!lq7kpMFzEKJ@txa`;v&T(jj@q7<~>_eCzUd^fBEafp@XSl1k z`~&Qs8#sJiZr?6la_zA|>-=1MG|;AV+xEH578K1cDl92#p4)29GXwjCb{F(*~NvWt=vP29`0(HV!^%U)Om|Kv?`g`YD#`bR|*$Qp5DVfwpi4; z)tuII+@q70Q%dHwoH{SJ)wJAJBiiP+a(9P&Om-Kb)zmpfB_)N^idxMsnmes@dXF|P zh4(I6*|qML-3ch2Q9QR*iMw0xjwP;5DJ(54+u?`8eR2+;DYu(nj@MlNpFYKeJ}Z10 zEVJhjr`~4yJvGy4ALH^nY~^>;@!|Wa@HPxYNcx z!}5D*{JzNNhS%=Bg&!!v4DX?(J`#4{PDcJkAE+}Ehw?&AJeXkQ=jB6;rFpmVEXt%vm8YLV)ZntrWF?MR(S-AKL2QE5jM|r6!m`ox8jR^dw^Ww$+ri`6`p*1 zd|ctlcaM#;D{T8hO*OZ7m$mXQ+*tCw?*RSrmFKnfL)%J1EahJbIh1W>h^Z)Z}2#rg< z##8>sLm>U$-0faH&Am(aeqvJ>&$LZ+4!jXFUOdaRzxLn88I$omVO*(FOSF63B$8_B1t|r^| zQ{HwwnfBC)`QL zUVn^^>pF+~Y8_wi8t#vEtmUqFd;KOlp4Kzmvvj<n>r$FyPLPUtvjM7YQ4c+seEU#sIAW5WH3j&)85cT*iFjt}=79d9`~-1q7D z{e*D;p<~;EaQD=4abdXE=(x*4w~xn*I!334J6p#g)5CqDj+e{~_jNkHH9Op&=~%Bg z+|6~IG(X(MI&Liq_x(ElxG>y*>DYd8xO?lkbZNNH)p7T-aKEf$`topB)p6*`aG#{( zrK`fdNym5Ag!>B}k2){hEp?o-Hr(@dynS7`AJp-{MdAKi$Byg6-B-tDmxcR$9iO}+ z+^_1GaaFjh>p1+HaG#>%cm3@8`AWy!&EamPXmSB(eb0b;r>p?#{0sZuj9-&!+pAr_q-kM$8`Md-EjNwg~#q6gvY@;p8Zj{FV^w7 z{o#I7$10zNyRMF7zX*4sj@Nt@?pt--|4q1m(D9h>!`)8D**}JRiH`Rk2>0VU9(LbC zHBZ5>;qkab;qiDKSN|UF^*X-rN4VeCF?l51^>sYqpKwpsaijZ;Z*TuL9Y1y7fwldU zj?LWH_HB32ajyHGtnD*&+~K}CYx@Zu|8(D_wH3F^S-mdLCbo|_Xlh^joI<|1%?X}%W$9cKoK2ygB z-1mR&*ZJIc#Zn4I_}W% z2_0Y2@qHb?*71;zX-&h+mu~l0+~si>A$82wvAT{8bZn$!Cmp-#m^weheUnt%9a3+{ z-OWiIOYHuSd;9Kgh?kad-_TU|T9+)DQ(8F59ZMI4$LT!h9&wj?t?ePM*LqS(iPzda zC~s}C^?$!Ap6XNV3%c%0=~Ii{DXHfRCrw&Vv?x3)Ebcpq6=&gs!nxCm^mfD7_}|NH z`~IKaqPt*T>&fn$RYmUW{T1Hp)CGle+$;4SJ*;(MY3YI)lNOe`H~atj$=%g*zdOpm z+3)Vk{O8Gi=u%G&-T&?N{BYV`pZ`4B%j~JC`_Ek!|F5st#=Xw}e7|qF#*h0HX&)e(RfA;@!anE|Snnm0nD6!|lC!Te8P5$$G=QWRb$MZ@RUN*@+U-A9E(La*M z&ih?h;T-p@x6i%3Tzf`Oyx;k5SA2Wb21HW+?d{p4Dc;_B?s?8}&w9VQw`adkc;aQN zU8wl>8drFGmEFsDd+x5mf8L(oBI0$h7wU<(cct4E-(Gw7_UwAH%jbRzmc6}O-1Byh zd9bI>?!j#HO5yYNe|wqz=RW2C=k*G^M!X@e@x<%xa>1VGX`6dJ-nKO^s=EvDpUc<1 z!mqcgUe7M?i|#*Xex5s|o<4AIuPehHd0%$q_lmu^RyTM3x>(aaZ;wXp{o2RfJ|_Gg za?g6>oj)_q6K~IM11rAXP=at-%*Q@xjwO#AtJon9uj-A`I?cBCQuKUtNoBRs@ z@7S?@Zf@uH?K`%~wWo>k<^A1TjqsN2Z8j@=yY{Z4?tQwaApE`F%&YBgIp^&dad6($ zUcaO@sWG_5keWjyhgOt4d3f){$agCuPafXW%l~eLH*VsX=@YyoZ@zxm%TMO_KAh}s z&#mm!`*5YybG;8|=osz(&1=Dss?)EH9C>5j&JhQ9kJ(o^Z=k(XFIl7451dVxJgjbzMnpF`5pf-horh|O}*ui<_XX~Sx{$2{&k z#=*btCH@k7tr4{+rc&$+cb%kV1abG z8{ND1+f=ighu~s6Ka#%5y~*@w^q9c@;9|`FcC@DYiI)a$=6lg*nn$_W){8dRtnX$! z_c!uu)^oGH7j3Co*Ub)I^jOV0ZgzBksh?(TH#>RJ)|$24?CeGJG;6xq#r?einl;?a zcNZ&PySi<6x!P)1v+XWeJMF5r-6d@OxY+wSu9)Q;J9m#>$0 zx@~v)dTR%^-R0|}9kuN)UtewCw!3`&wA0*f=PqA=?TBr6`37h^1{u+4WB++~{byce zeww6yW+StklMx*lyVbpd2{}HnKh&BMGE}EZ$S_R_8LlZIBQzysq^5+7(v*h9){B6f)G^ zLPclCOpXbe7uX+oP6?T>Qzc}9ri7GeN=T`uge=sQkVTpja=NC3EY_5eC7KelR1+a* zXd`5qHbTzSM#x#(2wAR;kQLepS*eYXv$YYjN*f`owGpyL8zJXtBjj9dgq)|1kn^<> zvQ`@*7ic47oi;)))JDif+6cK=8zGlyheGE1mEBE7X54+ki57=KUUxL2>tiOzgj^BW zABIl}xl*S}$OcUbxk^()uGW;0YcwU~T1^Srs3{@WX-dfTni8@}6CpQfBV@BSLT=PX z$W7V^xmg<_TeJ~!i#9@T)kerxZG_yWjgZ^55pst%LbhomyR{K=k2XTK zYa`@dZG_yXjgTGM2)SQ76mprL=dSUHbVAkBjgQjguJPZkhioE^0qcY-qA+L zyV?kOPdgOykUz>@|CvA8eUFDjAsy{L$@?*rV?sU-?1yMlLiX!a3Hd}*LO#`$kk2$F zWM#%5l2sx~ckUz8$@~1XJ{?bOs5p9J0t&Na>v=Q>Jb|~aS zztmm-nGf52kB?G9;&0n+i2FvM(XpTCi$((b5v$bCg$5Cwt)J*iXX_{WVr>0HUj|!0 z(U-~APxQsv`iZ_Qwtk|o5?epfSDCG!=&Qo!C;Acuexff);3xXB3H(G~4uPNOt4iP} z`l=E5iN5Ltexk1ifuHEBN#G~?Y7zK}zS;zSqOT5tpXjSg;3xX(5%`I|`UHNW?`z=i( zG2>;5nnwcr5xtb67Mw3dE!k3ZEL)0Nv8AXrTZ;17Qq+bmMfq$gYRi_Qc5D>2C!nYU z0Yx1NDC$H&QD*{*x)4y*m4Kpd1Qc~Apr{7{MaL0P)RTasUIY~NCZMPf0Y!ZYDC$Q* zQGWu81`tp*kbt5=1QZP>go>I*Qh!z>evaJ~HIt&CM z2o(*D_yZh}_zpLt!=xzJNEN$3+G1aQb&5(Nf&GYZN>M52OVL8M6fI&)(dld{TFjQB zC2T2L%9f%t*iy8NEk$RtQFImoMau~&T0ub3N&z3NX&ehqN^f-{fK!=(bb$UMc1&U=vuZEZDdQ)b!;iRo-IY2*iv)@TZ%Tb zrRYXBif$sH=wT|2fTG(7D7u}1qB{sE+D1Upodgu!ML^Nr1Qgvv zK+$#ritZ(#=sp69b`Vf>KLJG#5K#0W0YwiHLPb|b{MQ|jcsqOewLyx;o1%v!G4o}L z9*YF_R}`ca?c#hXdYmmqyV+9o1Y3%pWJ}RgY$@8qmZGQGQuGX4ik@Yo=s5z4o+qH_ z1pie4q4XfFXpuMtr6Isrxd2q=1kfTA}ED0+*4qPGbsdWV3b zcL^wZkAR~02`Ku2fT9lxp`u44el7Q%`S_pqzUKZ?Z6mnr%*64+mHky7*- z=S$J&Y$^JJEk$3lrRXcR6n)K>qHowz^etP8zGF+#_iPmXKtR!t1Qh*5K+ypLihd@b z=obQtekGvjAOS^(2q^lEfTG_CC^}3)(H{g9{YgO4Uj!5#A)x4Q0*d}2py*!$ioCS4 zNBNaf-;atAP?Sap7447sr#T?;r`(@?iGCtQFWYUApB6J;rYM#c*k6&7Qk22@Qk2P- zqBvWMve;5oi7iEy*-})6Eky~o6eZbGl+8v_4gp0~2`H*YKv8u9ifRy0RFi{HAo1z$yYJETwD6JslXhFwEG=ffOwqAvf&CRbDMhU~Uy53@r6`XrMQzwpl+Tu; zwrnYC$Cje@Y$@u%mZFYq6m=q?s51dYT?i=ZNiC>PbLRF9M2s z6HwHLfTF$x6!jyZs6PQk0|+P@NI=mb0*VF`P&9;qqT>lD8cGNiwMg^7bwJ`Z+@I}< zwv?inJ<=bR7BgR_XjEEYe??PD(P++>qA_eK8q1cVacn6%fh|QRvZZJ|TZ&F%OVP<} zDLRFXq6q{Pok~E_X#^A%5KuIcfTBVIiY5_IG?{>+DFhT15l}RhfTC#x6ip|fXa)gA zGYKe~ML^MP0*dAkP&Ai-qGAGy<`GadpAaeRv=0Y&E%P_&kSq6-KpT1P<9g#;8`L_pES1QcCDK+$>viY_If z=rRI|E+?Sq3Id9*B!r4e)BHsaNW6u8iD;n|-D$T)8`5It%M@Lk7HnuHMH@L^imqcz z(e-R8+QgQk8`x5`nJq;(vZd%IwiMmWmZB|e6x~8V(X9j&Z6%=SHUf%nC!pvK0*bZ~ zP;@5&MRyTUbTQ?xrRu)kt3bzAfV=S$I(Y$ie4q4XfFXpuMtr6Isrxd2q=1k zfTA}ED0+*4qPGbsdWV3bcL^wZkAR~02`Ku2fT9lxDEf$iqK^qE+D`}-?Mn00S~^9a z+E*PPm!eK~@A{LpnE5hAU!(>0S5&4HeaZP!^c7o*zGh3&H*6{TmMul!v8CvHwiNxq zmZBfoQuGrWMF$8d`k8>DUkE7rm4Kpy1QZ=2py)ROihd`c=r93Ae-KdgCjmu&5m0o5 zfTF(%DEfzhqJIe}a(@E(T6ZDzl}i3R{X2Y$-~zr6`*%MLBFKs>+t4 zYHSo$C!nYX0Yx>JU&=mw=*r1QgXLpy((9iW(45luJNSLjsD9CZMPh z0Y!}oC~87L(J=%RH6@^^839Gj2`Fko2o+`c{zVQ*{3QFTW2PTI(tpTqi(2|I^JR+i z{J{Q-+?1j=oG(TBY$d2O&PHZXa%$A}qY!r1Rpr{)GMcoM~ z>Onx!aRe0gB%r7l0Y$wDDC$E%QC|Xz`VmmnpMatP1QZPQMS}?_8bUzP@dOkN zC7@^+0Y$?JC>lWs6}9sHHyn`o9J?#jT8h54+oF+v%zT-mv3_8G#d1o~IL?=%6WCI8 zB3p{av!&=HwiKPrmZDSGQZ#`rMW?c*=rlHp3J55gNI+2`0Y#GtD4I+_(G&uTiU=s0 zNCMKv6LPMe_(KnomH{0s@Lk2q-Eggo;M{ zex3GC(TDEOEJnvj(Tnzl?1g^Je3_ypeqet^cS_Mx&X=My*iy8NEk$RtrRXfS6fI{< z(F(Q{tz=8l*=#9V#YWL;0*clUP;?FfMduPwbRGdk=Mzx0mVlxQ2q;=dK+%N+6kS9> z(ZvK5T|z+7dIE|rC7|ds0*Wptpy&z$imoJ}XafO7R}oNjH6c`Vy6;bPK;qr)wrH^w zwX)A>*Z48>Ws0u%1N$r9Q;Ifmz7*ZSmZHsUDY}s@MK`gf=w`MQZDC8%Eo>>el`TbE z*(kb=fTG(8D7u4yqHP2e-AO>vT?7=}O+e8-1Qcy2py*x#itZzzXa@mB_Y+X`00Bi0 z5>WII0YwiJQ1l1^MUN6tw3C3M#|S9eMFLDtf~Azjr|5XW3UBpOm7yc3bqhA2VO3=xaZ)e_|q~=o`+LqHoz! z^c`D@zGq9(4{Ry=ku60(v8Ct$TZ(>WOVKZE6#Ys-(Ln-=4iQlF8v#YX6Hs)RfTBML zDEgCtqQ3|zIzm9v-vku>LqO5L1QdBuJ#0r&gn*(n0*ZVBilPJ*1q2kO6HpW*peTb7 zD*Dp*+d3feHumM}ucT|%~svHgMpD0Nws>1nFlweCyk}XBqY$?iNOHoy} z6jftOQFXQy)nH3eO*V>Z5l~c{fTB7C6xAi5s2%}D^$93Cih!a91Qg{GP}GosqN52Y zYD7R$V*-kr5Kwds0Yyy-C~8JPQF8){S`bjwl7OOP2`Fks2o+^T{lyMQyr10`Rf>j> z^dGi+*R7*5^JR+KMuV$+OHn({m!kG;DeAzMqK<4S>cp0!&TJ{_!j_`0Y$@u-mZI)# z6!jpW=r{t3dJ<67i-4lu1Qhilpr|haMg0gU>Q6w?00N2z5>PaVfTF9FX`bH>3GdwBK%v#zbT0%M_g$4eXyt zO5GNX=X@zTi7iDZv!&=1wiHcZOVO!pDLRcUMFngrn#h)-LNW<`7Ucmw=*T0*dAlP&A)_q6GvLl@L%=Ntk^7Tq94 z3+*%7lhK&@GDXis1N$fbQi`7Cd?|X4Ek)0>rRW8=6uronqL_1QfkaK+!$|iryfg=uHBO-XfsrZ32qkA)x480*c-vpy+)9iasEq=tBaEJ|dv# zV*-ly6HxRC0Y#q@Q1lrAMV}K;^aTM$UlKw^d!qhZ4oG~ReG+?GiY~NA`d>w3=F1d) z7Y*#6h)gN^p7W*X2euUb$d;m?*iv+WEk!@GrRW#76#dGUqJwNHI>biNZv+(mPC(IN z0*d}1py*EmivA*?=m-Hte-lvj4*^C05>Vs?df1Ml2mwWD1QhuM6h#Rr3J54lC!i=s zKv4z(MVSN?#R(|NB7};*iTd@1IYn#iGupRO^rd}9s}#h{mnljHf&CMsDMi_wFGV?Q zDXPkrqH1g@s?L_88f+=5$(Ev8Y$>YEmZCar6xAi5s2%}D^$93Cih!a91Qg{GP}Gos zqN52YYD7R$V*-kr5Kwds0Yyy-C~8JPQF8){S`bjwl7OOP2`FksK#}`*+QL6ff+F`1 z%7p<%Z3v;FDuF-A0f|TL&s`^i@R5EuyJ5-?V&=;fbqE6cCu&oQI&!`gbz)0VXSNh| zVM|e0wiI<^OHp^W6!ld8h?F9M2s6HwHLfTF$x6!jyZs6PQk0|+P@NI=mb z0*VF`P&9;qqT>lD8cIOXFanB(6HqjQfTEEE6pbRFXfy#uV+bf3OF+>$La3-+;BR$6 z;&trir@a(yuyH~VGhe3YDQpxK5l}RhfTC#x6ip|fXa)gAGYKe~ML^MP0*dAkP&Ai-qGAGy<`GadpMatT z1QeAJP*h4l(Lw@>77i-4>k@#LSl| zS{?-UPh_VQt>AnqTFI88v)NL#iY-N}*;2HIEk)|qPy5Ax|@Kadk84nPC(JU1QgvzK+z5Y zitZ<%=m7$X9weaXAp(jXCZOmM0*W3bplBxnMUN3sw2OeE#|bFfO+e8T1Qb0DEfqeqE87Z`iy|0&j~2{f`Fng2`KuCfTFJnDEfvFDtb2XcRL_) z_YXjL(dVQn-#(*#8^p|)Df%%8KA9jzKXJYk9bik*&ul6Bg)K$DvZd%CTZ#^`rRX=d z6#dSYqQh(y{Xsy{p9B>BML^LJ0*d}7py(e0ivA^_$V=D57!*YaC`u!s$S0sEN)hV*?yGDPIqWA4#ezn3T5Kt*&6c7%Y$>YCmZExWDXPy#(NP2xH6WlU zmw=*%1QZ=jKv5$CiW(D8)P#VdV+bf}NlyY(J%svh7(XUf`Fot1Qd-TplCD!MPmpk8cRUYI0A}JAfV_(0*b~H zLPZ_Z{YxE?_-l5*sFM`kXWtGvDLrPsOwp<7!F`jZ=rqokq5`%QO=L?^AzO+jv88A- zTZ*QzrKpH4MN`>QG>wg-=>!zbAfRX_0Y$S2D4I<`(HsJb<`Pg;OhC~*0*dAnP_%%6 zq7nj%N(m@hNI=md0*X#2plC4xMN0@MT1r6C83Yt9BcSL^La6AJbpIU(Bz~R!`JxF@ zbcTIKJ1aeAzD&{C>A@dGQnZTmrD!!Rv*0Y#S+P;>{vEk$>+rRZ+96y3v?qU~%H-Ah2xeFPNkAfV`e z0*W3Wpy)vYiXI}M=wSki9wDIUQ38r~5>WIQ0Y$qAD0-ZLqTK`(JwZUxlLQn!ML^LW z0*am{py(L_ik>BeingTtQyh@^?{@QZixkbb@mzY$e3_z`(t|ZKrRZhOm!enLQuHcY ziuSUl=ry(!z0Q`ReQYUugDpjGvZd%PHj3URpy(X}iryul=sg08-Y1~w0|JUZB%tUc z0*XE+plCkIRQmq5K#0b0YzUCQ1mqcMc)um^eq8J-w{ysJt0)| zLb`vu0}_A2KBK)TMTK_1=!f)}`7%X6rw1?2mZD!cUy6QZOVL5L6dhtq(Qj-i`kgIB zhuKo}2V08%WJ}RsY!n?Kpy+P`ivA&>=wAYgyqF%gqbNc^Q5pe7J^@8h0*V3xiqZ)v ziV;whK|oO^0Yz~Fin0hOszg9hWde$-5KxpLpeRW|Q8pn|^i#TjzyXOrXE#3wr051y zloN}YFH=+_7GxJoQBBU5qFQVzs?C<7I&3Mb%a)>gY$>YGmZGEBQq+JgMY(JgH6)CMKv6LPMe_(KnomH{0s@Lk2q-Eg zplBfhMT-b1I-P)`#RL>BA)sg}0YzsJP_&GIqB997I*Wj!{s zEkzfxrRZWdiY_6bXgvW%ml9BP839F?6Hs&o0Yz65P_%)7qN@lfx|)EZYX~U1mVly- z1QcCIK+*LC6m24)=mr9cHWN^EBLPJ>5m0n90YzH~p`ukWKVy+owAsz*YAL$gKBL_d ziXDcWMUMF(Or^JR(-#)A8oNzozBm!jX;QuI4piVm}- z=nu9O{mGW1zt~cAge^sXv!&=CHj4fwpvcS6!*&!!2q;P;pvWhnC`v$4KtNGC0Yxza ziZTc&$|RsDPC!u>0Y#MvD5^|AQ56D;5(E?_2`I`YpeTocqN)TGRU?Foeu??-IUwUs(MDue3_!!8Npv?Nl_inm!i6CDXPboqWWwpI*Kht4cJnY%a)>sY$-aL zEk%vkC~8bVQ4<1+jv=6^DFH>z2qqbs>a`YG(Mk%blX@>^mT}GQvmt4eT>o*Nm9? zGDXK_1ie>EQBTg7qF!t%>dls-K5QxK%a)>kY$@u`mZAY{DH_O@qCspF4JM#y2mwXM z6HqjifTCdp6b&b!XaoU8BMB%PML^ML0*b~EP&Af+qHzQioj^d*i3AjlC!pvg0*X#1 zpy(6=iY5?HbSeQwrx8L$-81~D4oJMe!RaAIXW4C0K}O7cnWD)V!MUrXXbR^`Q4w2; zrn04I8e58{v!!STTZ(3~rDzsgie|H=Xbu}ia|tLaCZK2@0Y&o(C|W>3Q3(M>r34f$ zB%o*!0Y#@1P_&qUq9p_rEhV7n3<8Rl5m0m{0YzsKP_&$Yq7?)btt6o6Yyyf_5kf_U z8U8j0B>tU!)p3#(RX0+rGh*h;6rGn5yu3z=&gXn7TFaKA3)oV$jx9wOvZd%EwiI2= zmZD48Qna2eMVGQsbQu9fmlIHQ1p!4@5>T{(fTF7iD7u<}qH72!x|V>VjRX{3M?lf_ z1Qcx|py&nyiZ&BabRz*pHxW>DGXX_g2q?ORfTCLoDB4O06`hme|Kfne?~OP(=Sop! zyLWwCM$CMfqB}E!s^>}3U7RmPceADF9<~&1XG_t&Y$>{rEk!%nQglCCiXLD~(SvLh zJw!m!!vqvPLO{`@1QhKgpy)9IigpoD^f&=Uy9p?If`FnY2`GAsfTBGF6g^Eq(K7@T zJxf5*a|9GUPe9QN1QfkUK+#JC6unFc72T2HcXmMH!`+N-lcF^HjP^=K%zT-m*E52X z)=JSn&X=M$*i!T+TZ-OdOVQhGDSC%3Menku=smU+z0a1S57;RBkbt6(2q^lPfTH~b z6n#QK(We9yeMUgh=L8geK|s-$1QdNmK+)F(6n#TL(YFK?eMdmi_XHIEKtR!t1Qh*5 zK+ypLihd@b=odn$Xm5spmILBGpE)?MNzozuLiVp2G4o}Le$NOtt&^g|oG(Rxu%+lv zwiNxvmZBqUDf*i&MgOp+=wG%Jd6|0LE=3VGiqZ%u@(C!45>ONnP?SzUQH+413<8QW z2`GvaP?SYLQ6&P3Dicstg@B?20Yymyin0kP$|0brDgi~+2q>yfKv4|>ifR%hK-`81QazRpr|=&gBA}=>0Y!NP6ty9sD4&3$wgeQl zBcP}~0Yx1MDC$T+Q6~b5IulUTg@B^21Qc~6pr|_`R8%L^k6-K*otf_7)XfYZ>2J5u zBQs{cOi}O5pyhfg>cja`)R!$q{n%2}pDjfL*itl*Ek%RaQZ$$?MMKz9bUYhHLkTDv zMnKVU0*XcuP&AT&qEQ4CjV7RI3;{)B2`CyzK+y>V6rD&w(Rc!iP9mV_WCDs#A)sgi z0Y#@0P;?prMFj*DO(dYGkPs^Bndy&oK;nb#wy2jB9dV!FqLVUX=F1dK%?##WCPmXY zUy7!)rDz6Qie|EtstOiB>_ce6Hv5@fTGm|6s;kk z=o~_*XiBDkr2`VLWj8-XQuMq1Mf~Sx#>|%~x*#)n@Cqqf$N5rpAzO+rVoTA*Y$>{g zEk*0uQgkU>iY{YI(dBF@x`K_OD+wstKtRz|1QcCOK+!b>6kSU|(MAG_t|Or6dIE|z z5m0mk0Y#e$D7uk=qMHaPx|x8YEd&(ZLO{{21Qcy0py)ONif$*M=ng`t==@Co0|zAD z-_7V+DLURB_HWCKnJ-gxPiFA<1}WOk`BHQ*TZ-;uOVJLt6y493q6gSg^dMV`9%4(; z!)z&fgpHy{2`Ji0K+$6a6zw9Q=y3vyb`wza1OY`)5>WIM0Y!TVD0-TJqGt#wdX|8q z=Ljfzo`9kk2q=1yfTEWOD0-QIqE`qgdX<2py@XKFU77yTS2;x&+7}w{mZIu`8?R-? z%$F&8Gc)LWjTF7b`BL;YTZ-OcOVPV*DSD4BMennv=mWMCeaM!gkJwW5F&jnu2`Ku6 zfTB+cDEf?mqR$B^`htL>F9|66ih!c82`Ku8fTC{+DEf|oqVEYP`hkF=9|iGZR5 z1Qh*DK+!J*6#Ys-(Ln-=4iQ2{`!fCM4oG~nJ-B~EigwwzW`E0!nJ-iHXJ&BzMk)G> z^QGtrTZ;Z>OVK}UDf*W!MeZLy4*!}iDT=VAD2**eK3j^SY!n3q6r~eT6eFN0gMgw; z0*c}U6lD=mREdD1$^;ZuA)qKhKv9x_qHF?+atJ7@N_dp5>V8NfTGp}6y*_6)P{hfd;*Hv5>V8R zfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}GfpqV5C~^&p_=I0A}#5<*4wzE$**yK;pOC&ChfxirZ(jwegtwGDR1~gUwr{=wi;7qD$CPw4NWIS0Y$G9P_&N_D%u|RD{Xa({xLZBO3}Zm z2W;_}`7%ZC#DiA1OVPWWFGcUMrRaUO6n(&!q7T_p^buQ%K4weNezp{S!j_^>*(myq zfTGU{DEfkcqAv+3`ig*}uL&snhJd1P2`KuGfTHgSDEfhbq8|w;`iX#|0|XTPOhC~u z1Qh*BK+!=0iVhJ_^cw+1zY|b&m=G#@EAEeWK;pygli1r*G}J!5{Sl9uFH`h)JSf>F zMgMTV6#dJVA}>pi+@&bOmZCJa6!~l^in66BU`tUtTZ&?A6lD-llu1BQoPeS%0*WdT zP*jS*)Kv50>MO6tXszyLjbpncN5KvT;fTCIi6xAl6s15-|bqOe{ zM?g`1La6AkxPO%c5`Wuni;hUqmF{KHqq1V=%M=}*6+C>G6gA>}DQe7?q9$x9I)*Jp zP1#b^j4egY*;3SkEk!NaQgkdEMXd-ZYE3{<9sxyd2q?-Ypr|bYMePVEYEM8>2Lg&Z z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)0*a0!pr|JSMZE|p>PNr4(E^sf4PS1*& zFHB zA)sg}0YzsJP_&GIqB997I*Wj!L9@A|^5nE5hA>$8Fj?w6uVIbVt{ zV@uKHY$>{eEk#$drDy|NimqZy(ba4zx`r)9*RoNxk$|G>2q?OqfTB$V6x~2T(PjdQ zZX}@SCIX6XCZK2w0Y$eEP;@H+MOz6dx{ZLM+X*PTgMgxK1Qgv#K+#uYHyM9lKIvS}XSuyiv zio8m}sXL`8Qb~{Gr6`RpMLt`KqHHM&*iw|vmZBJ2iZa+zl*yK&I2%P-1Qb;wpr|qd zMO6qWN)S+#B%mmpfTA1%imDP&RE>b5>I4+kAfTuw0Y$Y4D5_0BQ5^z`>Jm^?kAR~3 z1QZ=bKv4q%igF2|qJOgdvmKE5SM~??|COS)?q$)2m15@06g8<7+_X!Ij^TVMYRZ

EOs%SO>S0*X!`py)&bipCRAbP@qYClgR~3IRnE2q-$0fTGg~C@LVJ zXd(ecg#;8$BA{q80Yy^?C@LbLXet3k(+DV)$PMnKW+1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?lg21Qb0$K+%H)6m21d ziY~3@U+sXzhuQaCUnWJnZEUR;Ghe3Y(Q3ityQJtbPA^4|v!!SoTZ*=`rRWK^6g|n7 zq8)50dWtPYPqU@y88(V`5>WIk0Y%RdP_&DHqUQ-HdVzqV7YQhOiGZS)2`GAnfTC9k zD0+>6qTK`(y-q;U8w3=+NkGva0*dw$Q1li7MQ;;O^bP?7{5NTZ%qmOVOunDf)~pMW3^!=nJ+KeaV)huh>%b zH5*0W5K#0j0Y%>tQ1m?kML!Tw^dkX9KM_#0pMavD2`Ku7fT9Bg6#Ys-(QgD4{Z2s9 z9|RN~B%tU|0*d}3py+P`iVhJ_^bY|=hY6vg532c19guj$KI{0Q6t%QR`u|ponJ-i1 zX9fdbmZE6pe?HO=*iw|vmZBJ2iZa+zRD~@?akdmyWlK>twiIQuQIthMQG$S?BmqU) z1Qg{EP*k0Oq8bDg)g+*(76C=I2`H*VKv7)+ijE+ls2%}D^$93Cl7OP42qjwiLByOHm$MirTQHD4#7wZP_SlM?g_~0*X2iP}GrtqD}-9bta&w3jsx4 z2`K7DKv8!Bih2-GbQ}RiJqal4MLCK2o)Wl=^u1J;`8mcXs8s~r-`Do zGGpe;6qRHKb>EbtQcf>LWo#*$%a)>fY$-a6Ek*O$QnY|AMQ5|6=p42bEo7tUTmp&~ z5m2<4fTHsVC|W{5(fI@vEhV66839Gh2`IXNfT9ZtC|W^4(M1Fltt6o6Vgia*5m0mq z0Y$3`C|W~6(OLqE))7#2DIrueJJUbT0f`^5uj$W`qD$rbPEARw-Qja znSi3(2q?OpfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C2q?OrfT9NoD0+~9qAdgzZ6%=S zAp(jXCWMNv$n=*vAn{l2vyN9v(RO>J|43%ce3_zcnZYe@OVM^tFGWwVrRYhv6zyP3 z(NkY!vMxpy+u5ie4a~=tTmGULv6AWde#`A)x400*YQE zplCM%MXwW3^acS%ZxT?nhk&BJ1QfkRK+)R-6um=0(Ypi`y+=UN`veqyKnN8*mg&Ff zfW&j{`>r3CqMz)`As=SO%$F(pBs2K#T`BsM(@W83Y$^JjEk$3jrRYnx6n({(qOaLf z^bK2zzGX|%cWe}WPe9QR1Qh*9K+#VG6zwOV=w||oej%Xf00Bk65>WIT0Y$$PQ1k}@ zMF$Be`jdd7zX&M$n}DK21Qh*4K+$0WivA^_$jj0La}-4gp`wp7{p5R2(PMU7v`>n@ z^4&Y3mZCUYimI}us2W>}GTBm;#g?K3TZ)ow6lD`o zltVyKbpncN5KvT;fTCIi6xAl6s15-|bqOdsf`FoW1QgXLpy)^fijE?nr~v^*xdaq7 zB%tVM0*V?DP}G=!q9z0sH6?_KqFMe}2PA%n!3na$NBZubwtK*q6*FI^sAX1g)<;rw zET@;ER%|J1&6c7(wiLBtOHn>sirTWJs2y91+Owso0~HCZK2t z0Y%3XLPagI{EZGs{BirN<1te7fsq=T6*FI^Xhc@9eV-Ja$mykMBwLC`v88A0Y#Gt zC@LbLXfgpsQwS)UNECPy(2`HLP2o;@><$vmc#B=O1 z+HffvYxl0_WW~&vDVm!V_@7D9JWek~XR)PdK3j?wu%+m1wiKPimZF7hDLR)eMT^){ zw3v;e^9U$fLO{{^1QabLplBHZMau~&x`2S93kfJ%K|s+(1Qe|#py*-(idGR&bO`}P zs|hGtLqO450*clVP;@B)MVAp!bU6VtwiIQur6`LnMG3YPCD~Gx&6c7ZwiH!o zqo@V}MKuX1szpFiZ32qw5KvT?fTAM^D5^(5QGEi6jwGPyC<2Na5Kxp$Kv6>iijF3r zs1X50jR`1fLO@Yd0*aauP}H1&q85ZuQ7qy2azNs%?XFNpB7CI3&PW}Th?y@_)H)Fq z{wPIxoL-9Bu%#%UEk$kFQq+zuMeW&A)PXHU9obUUi7iE)*(mBlKv7o$in$zRCH{@zrX>B-)oQ2T1nBq)C0Ce%zT-mQHfylekmHw>7{54TZ+cArRXHK z6pdp`(aCHnI)yDor?RE!G`19-&PLH01QZnzP&A%^qCx_SCJ<0Gk$|E}1QZn!P&Ao< zqA3IvO(mdc8UaPq2`D;~fT9@$6wM@{XchrQ#RL@1CZK2z0YxPQ6qOP}MJFcwmmQG! z4Ex;mNGWP!w?$=%nE5hA^Ao`jzev#nPA^4gv!&=9wiGR7OVPP(DO$vqqQz_}I*%&~T}eREdIE|z5JE-s5`NABr|4b#GX7ao^n2jORf(AS zGDX)Wf_A@2(RG|&imqo%(G6@V+QgQk8`)BH6I+UIW=qj6Y$>{xEk&EzD7uY+qT2~5 zx`TkCI|(Sdi-4lL2`IXUfTDW|D7ue;qWcLbdVqkU2MH+JLO{`00*W3Ypy*)&iXI`L z=urZS9wVUWaRQ3A5m2<95GuMR;g54b;_dCWXrmO3w~uH~Bx2^v6g`~?7W^Sa&v1Gv z+R2upXW3Hp99xQZv8CvFwiLa=P_p*m&Pf5`P`xNA7iJ18^MPDU?C;yb9uQ|OGeZ!WbZ`o4x9b1aN zXG_r!Y$^JYEk!@ErD#7}ihgFJ=obQt4iHfED*;8n5m59y0Y!fhP;`)hqCW{J`ip>~ zzX>QhL_pC$1QZ=6py*!$ioB#AwxcLQKv5b2MLq#VQ38qr0*cZJD2fq6MPDTR&mEBX z<@Q1BODP&-w?!GrnE5hA)sjJQNQyE!y%c4!r6|Fcq9j|2ve{CU!Y2mZF+$ zDXPUrQEdW>>JU&=mw=)p2q>yYKv8`HijE|p=qLh;8W2#FOF&UW0*a0%pr{c6MU4q4 zYC=F!Qv!;b5m3~efT9)z6dglAQA+}fjwOVO;z|D)2PFPP6$htkGJK@}jD2`(m5iA$ zQ1-)FgDph`Y$+PgMo}RFMH2`pnn*y=Bm#CNK+zNe zil!1!G>w3w=>!y=NkGvI0*Yo5P&A8xqGAGyW)n~}hk&9I0*XorC@LeMXf6Ro^9Z4$ z(MkUy2PA%_ed%nB6lL2Z{j-uW^JR+8Nd|AHNzp=1FGc6FrDzdbiWak_=sdO*En!R1 z`D`g#%9f&KY$;mKM$rWX6kSL_(Fy{JE+U|4B>_bj6Hv5@fTBwXC|XTG(Ha7Z))G*( zj)0;|2`IXZfTGI@D7u1xqALj~T2DaH1_Fw%BB1DM0*bC7go+j<{X-5&e5`%$`fMrM zXSYQglQHvUif%{-N4kFwB6VA|iPKBbjch5pi7iDpv!&=3wiMmUmZHsUDY}gpy)mVitZ<%=m7$X9weY>3jsx22`GAqfTD*9D0+l| zqDKiRdW?Xg#|bFfMnKVa0*am>py){gigpk}Mb{<$J`PB{zTNy>FGaW7W3;D|G4o}L zo=pZ5V^Z`Sro1cr^JR*@O$N7Dk)rQ7y%c@V zmZBfnQuHHRihg2C(SEiR{mho4U)WM~fGtJ8vQhLK0Y$$PQ1k}@MF$Be`jdd7zX&M$ zn}DK21Qh*4K+$0WivA^_$jjElb`(VjC`u!s$S0sENA&iL#EadGej`P_?U8=f?3np7MTzX-r>atvV8TfTE)bC~8DNQDXv% znh;Rblz^gU1QazVpr{1_MaK|O)RKUrV+kl~ML8JwiF%5 zMo~`!ih2=H)SG~!J_Ho?C7`Gu0Y&`@C>lUO(Le%<1`$v+n1G@o1QZ=lK+#YFiiQzT zbOHfI!wD!FK|s-o1Qd-VplB2UMWYF!qPE%oDGo^dAG<5mPKsvQz3VaAG4o}LPRyzjew%*1QeY~K+y~Wie?f}G>d?uVgib06HqjVfT9utib@G6DkGq1E&)aJ2q-#> zfTH;X6fGcxicZS*Z*V~3+wHb!oD{ubpMpF)J7&I2(W30&sT?U<%;}}*Jhl`qVN22Z zY$;mGmZD{BDO%2!q6^qkbRk=cR&~T}eREdIE|z5Kwd#0Yz66P;?CeMH>kyx|V>V>j z4oG~y-Ta&@MSE>rpB*z_rs$^ZAXZa~Zszn-bPHRGZe>f+X0{aF#+IVn*-~@|TZ-;v zOVM3yDY~1DqI(D^x|e{W`v@qypMatV2q=1xfTAq~6m2D-=ph1%9wwmZ5dw-HC7|dr z0*W3dplBNbMcWA|dV+wWCkZIpK|s+{1Qb0@K+!XVP|>Dr|5yhkezbk}{*6+!%WjKy zX2;BzDSAFT7*<<~Uf}dn^deh|USdnp%WNrng)K#|vZd%XwiNAVOVR6WDSCsAqBjXB z+CxCmUIL2VBB1DP0*c-tpy*u!iryoj=zRi;J|LjzLjsCEBB1DF0*dw#Q1l4_MV}H- z^cev~pA%5@1p!505>WIN0YzUELPgJI`y~!Y{C#_*ze|e#axaU1lN~c(rs#+4;Ig_> z^dqO2qMz7Ow4W_SKeMIi7q%1~U`x@jY$^JUEk(bxrRWbfiVhM`^d|vDe-TjhHvvV5 z2q^l8fTF_$6#Yv;k(Z-~?I?;6P?SbMkxxKTlz^gufTDB)iedy5We`wQg@B?s0Yy~_ zD5^$4Q6?c&^j)_9hyxPOu-l^VrD%eEM9a#FnJ-h6lM}pKPl~E@dMT>GmZF+$DXPVm zqS|aJs>7C|x@;*rf-Ob$*iuxVjiMt7C_0LOq6P#MPaXfTGa^6pbOEXek*qBGc1RKS*^@oXt7WJ}QmwiHcdOVK2@6cw?hXfhi`QwS)U zNECPy(2`HLPK+zlmib@D5DkY$(jDVuK1Qg99py(_D zislngw19x3vk53Vhk&Amgiz5bIsQrqB)-+Y@A_0JT4EpG&drILFH^K6C%E%yDLS9i zOVLuc6fI**(Q>vFUBH&23)xb%f-OZCv88AwTZ%4bqi7WYMVAmzw3>jTH3Sr`C7@^> z0Y#S*P;?mqMVAv$bOixLR}xUPo`9ka1QcCGK+)9%6kS6=(MAG_t|g%8Is%HWC!pvC z0*W>fLPd*n{M`;n{7W~Z=Sk5|Hg3#`nJ+KPON%zDQm<*mOKf&uvh@-#7`ViD?$eYR ziA?usu393`-8D}pPR#VY8i^|so>wRFezxb;Pc*FIdAW%xwLGtJ;_f=0*F16H2+un< z(d9_bYm->q!1LNCo^9xPofB0XdtUd%iA_DPS7Lp0&+C`?@EFeGCC2VV@!6iYC$V**=e?8ody(gTkm$X{ z^Y$e!T{*NRd zzQSDrk>o$?-8B$N_PyF&1(D=M8{KsfNxpWSyAmSFnw#9U5J{eTle-!s$xXMo>mib~ z-)7%9lC)n(-aL}D-zR-+Bx%18xJ@K!ztOdQBx%2rvvVYAzf-Y$Bx%1CuU8~#ztyZ? zBx%2vYEUF;zgK8zB>Bw_cb!C%_M1IMN0Rod8OBAD_HXN-7D?Jajy^t;w13@tQY2~r zJn_^>(*Awf8Ih#@1EI4cN&6Qb%OXkpC;H|`lJ;+`EsP}XAIUl|lC*#2Xjvq=eV@CA zB1!vqMpi|V_76p@jU??S{V$Is?MJmYM3VNiwi_c!`(eo&B1!vcx0@qL`*Ee)B1!vs zle;2G`+?=6v}ear46k)(ak<+e!DzG-epBx&FEv@?>lZ(DgjlC5u(#<=Oqw9kHh9!c7#FTRc>?eXXLk)%C<*dIyS zJ-}ZhN&66fFp{*};6o8F+y2r-Zw~*;<*ad6W*7I@s`^6r%*TOOBi;Qq3OZyrcdcfR zh`XlSxmS1ZE%#q!W3A_WD@WR?++V=dQ|&X|_j5%$WLfiSJEmTwV>s$$*-JX5Ml;u& z*ek5CbLgD4)IIOjUhm#mq>E0v+P$GjSB;zPq}?>`w9#E-tX-%c8vEUiLF71%&2cw+ zYD{+LAL$hi_gr?QNmli$epbD#F}1UuCeKT2>{YFLoJ*eP*Yf{j*;jAqUNg_V zLXGy7E>zFD-RpW@&DN2gb-AR?>SjlB(tFie-^abAR#54c(`rB5$GzKXS3ZOK?rqnp z9P~K%xTxIXm~TXswCHFf``d2PyT{nWOXAS^ts6`t(8cv|N` z`Q9XVUTKlPvogJidvY%`C9PZMl@#VpE}flMS~4-Oq@Z+SQNiqz;6Sr zEGfz>DVkMOT3DJ_)V83sZ0@9K#d&4L#WN;OEu1#1G;hkpi3NovGxPG>6tpX7+oo-P zL4F&Htz2w1t9VvXtD?dQ(^}=XY2B`sy|}e|@qfH1Z`!PhGv-bz%9~j@aq6^L|G!_1 z(gmfJ-xE`&=JhU_GUSV00y|+9syrL)1oi(vte!JEajY7esqREAGXOtC` zEtp+Y+Ip%J=eetE(zID+Za6`s`t~ny7jt6Y;+ZpxXSwF^0cM(=b(lPN^Bknu`t2e? zQ2l><3L@$Llt_@{*UfFywPCj)NY4v$(py(LHVkS-f-3HAO{7kcutOqfY=`tnICE1k zOiOPYG<7-6<-m^qg4RJpd#0IQp7&obpRboU{~s?;ovii$mhFwFrTg<*2es@uy*c-0 zbN$TR)Z31vHwvn{m$^%tYX|qT)O0U(mok!GJ;-SgM0%vf++V?w{Rb8dXfw#OV}9p0 zg9;{u&vtBI{%nW7<Sy+rT#?D zte)%lAE)$Y6wjKHoBH4XaFt(iLHdXe!rXP1dIONExN^$*gjnrwUH{biOt-%%sS~x) znK`$*Onu5Po&60>y;ARri`maz%e_Yq%un@l4_t)&&gEy5UqKEc2+0o({$G9=)<^M* z8+ZG&x_6ZROrR_0Zs_!qf4LUGu41xC%Y) zMo$+d-(41-&98V@S2EN|C+B(&dD#jUq+=|=2b~>jH6_+P;mHJaxP|B}lsgj|N?&KBJx#i4Dg7qu&Y7rJ)@uU>J*bDeUPmS2sX-8mJP|1GGvPWZTDw?sNScN)&v z@ebdG?#-s2aqkIUR(_G(+j7lrt4F(g6?%P6=&p}cu`4|i$gki~F0ev@`{?Y>zjSJGNm=;^M2C$_5nk!#*LV4cZui$D^(uCqqy)M5M)*u6 z0u@(ze#Ld3UvZ^#jpVxvn>w-k*q%D_9?y4v!*i{4g;rdD?v3kxlke`0gs zcVT{b?WX>YRK$Fp!d1&z{$zRq5ifplP)CamBsCiu-{1A@GzGcWbPRRdHp6%F923 zrcf6Y{O5;v?u1s{2ZfE@V;VkSRQZSPeC~2q+fd`r>T*}QN66jIio1XOy~yYG*6tdH?+69ZFfM=EWaU4-OqHFyyAXf#oa)VmkTJrmsx)IvHYH5rN2!Te@TEf2DYA+~R-#3+6tB;vV(?>z*QB z+QKaN`4sy^0#Eh{gWg%ymif!mE{M#0?%AF0vp&7MxL9b9zr9GFdp79YYFO)Gy$7G* zrDw;6Rq^8)Inf%CnvvRmok-ot5s`Y4`jMm3j*hgpPcQt}Q{@!(e*U-ei+y_lTItER z2cMOme0%&^>B)DGJ+muq`$UNQ9JV*9yj6T+#FFo&K0{ajQr~l*xT^Hzd+zh&m7aXh zeb%PZlkd6DnOA!9y+oyD=l`FV#`oMOlqx;>UQVTDuV2%1pD0TGsqOuq<1W8_>W`(Hoa}jVJxrBOm?su|Id3dz1F3OtVk*+tFQrcB$-GQ%Cm+D=*Exu%R8@AE~*z zUAOjn?z8o&qx&3v>exre5ju|1(R~IX_44UD&e3tPj>~jhtK&^N-tVqfdpp~8eA8V` zwm;VKH}?my9dVz{v}0}eXR%`=9lN-z#dd!kPj!C=+f#JB!Cfu3@7D24_YSaqK*wVp z65CyLEOB4*u)SEvN8A@bY(J~x;UmIbwO)Aa=e{6fFF#Sol?}qZUdP?;9cwTDP{&%0 z!`(>7)7)qB?B&yRywP0&w(r&P>tn+Gn~tqpg}a-MW$ucy*I%OJWBK9UrK8tA+?hHK za960k{wN(+bq@DcI=<00+#l;$$6fLE`b~5^qi49!)bZxt;l5wTZ~KP(4;|YK2zL)1 z=M4(?QXRJq3HJ*+rVR^sLdQYF!#zgF)hCAg8XfnH3il^E9x*oD&2$_;F5EM9y!DiD zKd9sPr-l1Z9orU!yQhxx3&Xu!$0r$M*BX-CM`A&kpy6I__8)?pJh7UmWi0Iu2bD z?vr)AbZNM+*YTa@;r>F$qgI5wrH+$UhI@{VcdQEc!#eI?9qxa0?6@x6eRW)TS-3CK z@#!nV{hE#$8^T>v#}lp&_o+HwzA@aJbbQZ!70s@nuXN1a6z*0!PQEGJr8?eqOSm7^ z@t4iv{#VD&cZ9pYj*IRJ_r*HyyeHhR>lnX3+_iNa@nE=5*YV1&;l4@74;~KpH##2u zSh(|aoVqRCb9KDuiEuxzp?#&3o@U&rZt!+n;H_q`qN?K=McZn*vT!ejRj!sB2a&;Kag zYjk{mU%2<`nDtq>>*+Z9i*Og}c=cD|-mK%kZ^He9j!nN0cRL+t{21;9IzF&J+)wIw z(0xhLJOu~B<8i-*$K!Qe_D8ta>G!7wT z)A42Z1yS4Y>X_rcGHSblj^o^yNNpGCc%A!NsqH&;{M>!f)b`Ih9^<}xYP*w;vvb3J zu8t46ucz9}pV6_t`;w{ct~w6TahM$g_oZp=iFS;;kLxEc~0Y= z^|rY4nq4XIth+1nAFtQAMa1i7C(skGH^J@7Z+Az(h-dEud%MNz3j^WI=`elKf9jn^4Z^K&hJ+Dyj=!+U)WRQRuQj7weWfSzrD=< zb06aWJGFG6_65%-9c^R=>eKxzfyZ9;ReuDj*zymjQ!y?$TTHyBWF=+1-DhC2`L zY_sQJG~a9a_j_LMzkeM5x6d!t8`T_AeelkMUc|jLx6$~jQ?HI3+B5vu9V2?Vmt_ul zzVP_*qo$tf9oqYbd!4GsPpjYeU=z=t?|ZOe>Ug^=splH{9o)-uJ8$=rwR*i$CA=AE z;{Gm%*JCu|yLV`{qnxZhmEZgB!ly;jOYCuKBx8~LP?nY!TobcHY>|t8E%ygY8&=0X z?r~oy4z{|N_^a%-hSwdRO0k3PY|}D=9qyw>T1Kq9yC$O1z&>-87LC2`Ud6BJUfn;o zdT)FFQTL|(HZ|-fBUodnkED-rXPF+2HVy2X0b_mKzc|)RKSk2O&3rG~T=OV5+j`L! znn$|X&iyO*n)Tgm??qc`)^oFi7d=+<2sb;re<)A0uA7~_Xlu~Oa8n)d9Yo}e^w!38QwR3E{i`GFq+qS!G9kr9T-G%F?4Rom|Jb=QvDc9*Y*b`{(1@*St0VcT84p4u_n z?(+50PPgqYUvKTew!3_Nw4=7&pbZS23` zuKy~V%ukcl&p}lA*?p9W4vcMfuV6xs59}L7Q$mL7q!KbrQ$kMAl#tZG^1RM#x(2P{=Gl(|s_ha-{o!6D9E+6dXAjgYO{p^(e`Ja_$9X=%41mxn^u+w%{_OpXb8EU+IwNC|md zCzX(Gni8^IQ$n85l#nMiC1i)Dggm7wAx~>c$TOM}vQrZw&uSy&IcAHbVAjBV?~OLf+Cw$lKZo zc}E)|?`k9DJ?&7)BmRl*`mb_};}Cr`6f(;0le`}@IVR-ezXM#xXv2-&ZV zke{^?@{2Y?4rn9fS8as+rj3x_wGr}%HbM?+BjitQg#4wAkiWGNa!4B?|7auRur@;e z)eePx=$E)=$aB+4?EDs%-s~Ts5|SN-mSFpOVXB^HXvO0zV~}B=A#m*#v${E{DKR z$yF!tQ*t#3{FGcx0zV~Ji@;CG)h6&$a&-v&lw4f`KP7hrfuEAAN8qRA>J#`Wxg!bu zl-yASeoC$ZfuEAgCGb;n4GH{|+|dMnO0E%spOR}#a6mGn?t8NR#~hIO({}g7kA#Z8 zvHLAeA~EA-idsYh`?0r_qGLF{6t!ea(XnhPYQ>hK)@&)tV@pvRwiM;FrKl}iirTSJ z)SiH%4g?f+B%r7h0Y#k&DC$B$QC9+rx)D&+oq(bq1QZ=dKv7Quih2=H)SG~!J_Ho? zC7`Gu0Y&`@C>lUO(Le%<1`$v+m=G#z7D;`-M*J$fDQYf79~!A4k(l{1MJGf8`?1NC zqT!rgibk-d=tQ;@jbuyFD7F-hW=qi+wiJzJOVLSeDH_K{(a8i9okBp-sRR_AMnKW& z1QeY?Kv4k!MdJx5DkPw20s%!62`HLGKv59^MUx3AnnFO)R04{o5l}RpfTA-AD4Ib) z(M$r0W)VU~LnHnG2PD45&FC;GYGcXJnnC(nw%GcAHXE#_6SKE?bJ`v8CuN zwiL~0OVI+h6rIhMqI1|%w2&=D=dw|>h=8KS1QeY|K+zHciq0pXXej|j%Lpi1PC(HG z1QcCJK+y^UiY_9cXe9wf7ZXslih!a^2q;=jK+zfkiq;ZPw2pwHO9?2tj1VfC6Y*C$ zAn{||BkgF36b(r|&Wgm$mnqs13GBzVQ;M$Q^ip&+TZ*n>OVLKQ6kW@fqU+dFbUj;& zZeUB%Cbksa$VSmk1Qgv&K+!D(6x~Wd(PjdQZX=-Rb^?m-AfV_@0*dY;py+M_itZtx z=w1Sf?jxY+egcXfAfV_$0*bZ}P_&hRqK615dYFKsM+l*!D=uZNQ{vx30Zvu)A5m59G0Y!%iDEgOx zA}_7{QGT`5*P|i?6r~YDMf)QD84gH%f&0p4^b;vsYPUsxTFiWzqF7pB|LjOgQ3j`% zqAF}DinFDtDqD)Gv85=JEk#*uDN3-VD9M(hY&ME=2q>yfKv4|>ifR&2REvP3+5{BU zA)u%(0Yyg;P*jhAqWT0B9Z5jZQ3Mnp{s0~|+ z^4U_*-|uyEk$G5QgjkqipH^}=w!AO zox+x)Q`smwjew%l2`D;)fT98dipCRAR7gP41OkdC5>PaWfTAJ-iY60KG=+eosRR^F zBcNzH0YzsLP&9*pqL~B~%_5+vn1G_$1Qg97go=iz`E4AKc&6PJjgX?KeMBosiN+n=qyezMf2HGw16!|XS1c~9JUlKWJ}SxY$;mAmZHUMDLRjhq9p_rolii~ zQUZ#W5m2<8fT9ZsD7uh5CZK2)0Y#S(P_&wWqBR5*ttFsn9RWp` z5>Rv*0Y#S+P;> zEnAANV@uKXY$>{dEk&EyQgkC*if&>{(amfrx`mCRTL~!IOhD0X1Qgv)K+zop6x~Tc z(Om=--AzEzJp>fpOF+?m1Qgv*K+yvP6g@~l(G~)Vwh~bE5CKIG6HxRB0Y#4zQ1lo9 zMUN9gMOUTy+Z>SibrA>WYAO25?rLvKiXa(XGM#+IT?wiIQtr6|Fcq9j|2ve{CU!Y2Mo~=yifR#1RGWaJIs_EeC7|dC0*dMpP*k6Qq9X|?I*Ndz1_Tu45>V8TfTE)b zC~8DNQDXv%nh;Rblz^gU1QazVpr{1_MaK|AMH#-o+5w5rvu_uw;)jp)U$WbxmVV59 znW8*Duzz+orKk<3m!f>O6t!hbQ9HI2wP#CF2euS-WJ^&ewiI<{OHmg#inCwr!2}cyA)x4Z z0*ZzbP&AByq7w)x8cqlmwetNv4oJL_JuGW2MZel@(Fi|gzD&_*Kd^tcIHhO|rCNK+zNeil!1!G>w3w=>!y=NkGvI0*Yo5P&A8xqGAGyW)n~}hk&9I0*XorC@Ld_ zibneW5$&C#{qB1fqobr~iQT)N>&MKODO%tM_Rn6Y6rIiKrRW^C6fI;+(Yb6XTEv#3 z#cU}$k1a(@*iv*pTZ)#lQM8PJqU8h>T|hw5g#;9>AfV_X0*Y1=P;@Z?MXLxXx`cqD z)dUo+A)sh20Y&QwD7ut@qRR*sOT);AMb#~e=#`o zrKp#EM7!FLnJ-gxogdggo1Rj1J*StV8`x5`i7iDpvZd%IwiMmWmZDqOQgka@iZ-*Q z=r%TrZYQAV4g!kqB%tUn0*dY?py(a~itZ(#=sp69?kAw=0RoC1B%o*u0YzI0D0+y1 zqK646dW3+YM+qo;jDVuY2`Jh|K+$#rik={ZiZ=TGtqw^1ZBulu6uEz%+&y6PW9G{g zJ>v)V&+exb?d0@Q^ekJ7o?}bVF18ds&z7PW*i!T&TZ&#{OVP`0DSCyCqE`thdX0dh z-2@c9PC(Hc1QfkVK+zroiuMvv^cDd{Zxc}T4gp2)5>WIW0Y&cRqv!wuMZXeI^cw+1zY|dO2LVL~ z2`KuLfTF($DEga#qC*4}{X;;}VFHT&C7{TQ>R~&IA_Nqr5m4k4P!uJgC?KFHoq(bk z0Yw>vP|=sZ-_`+%cePJfeqM-foefPkW00*V?E zP;@i_MU4n3YD_>;69S5w5>V8PfTHFE6ty6r=okWuS`tunECEHW2%(~?QGdPz5gJ#NBYI~5v_GJX1+{O+h}lAZz*cW>7}SWTZ%fcrKlrYiaN2Ss54uNy0E3FD_e@X zv8AXx8$~?`C_0XSqMig4^&+6CHvvU`2q@}HKv6#eiuw~!G=PAjfdmu{BA{q60YyUy zC_0{iqM-y74I`lF1OkeN6HqjQfT9x#C>lu!6}5@_PdFg)rEW&^rRZC`EgBV#nJ-gx zQZ%q%JCwRD8pr9S=w!AOox+x)Q`u5<8e57^XG_r;Y$+;WOVN0?6cw^jG=YGki3Ai) zBA}>AY-MdDD{9X8Z%#}Xkj$4Ut5(@bS|ftqD5>e zTFjQB^Vm|fge^tqv!!S$TZ)#krD!=@iY{QI=t2UDRuE8h5dlRj2`IXlfTC3d6kS3< z(P{#U)(}v%mVlyl1QcCLK+$Cc6kSe0(G>&~T}eREdIE|z5Kwd#0Yz66P;?CeMH>mB zqO+s^5CQ1mGQMV}E+^f>`VUl36AB_UL_GwQ$PfW-UQ2eD_R=mvYF|5Y?* zzD&_~(ZGJ~VoK5XoL-84U`x@DY$^JQEk*m;QuH%hihf~B(E+v;{mPc2-`FVnoq(c0 z2q-#8K+&HB6#Yd&(cc6V9U`FU9|DRF6HxRo0YzS*hwUhe5KxpxK#@;CQIvq9fPkWO z0*Yb;6lD-lRE2<|H~~df38A8IqJI5hPEj}ehaA3@qCf2;TD2f%zD!Xv2<+E(rW9p! zdMV0bOHp;U6xCo$QBAfK)nZFgZMGEEVM|e6wiF$~Mo~Qiis}qM-foefPkW0 z0*c)4G7G=o0!2p?P}GQkqQ(RiH6fs=DFH>z2q+q9E$P?C~89p6=enf1P3Hu+rIBQ5rmKQf3~~Y`9aKlnW7FsV88Y?rKlsPm!eK= zDeBCYqAqMH>dKa)Zfq&)&X%GcY$-a9Ek!-qDC$K(QEvi@`Vdgmmw=*v1QhirplARA zMFR;a8bmJU5KweH0YyUzC>lmU(Fp_;4JV*z1OY`S5>PaffTB?Z6pbdJXbd4# z)GqLEb3o#|?Y5}B6y0IBMPq}Q`7%YP1cCk9;FO|MIlUB}#+IVf*-~@{TZ#(UQZ$|| zMTKlBn!uK#iEJsF#70pO0Y#GuD4Ie*(NqG8rV&syoq(b<2`HLDK+#MBie?c|R7^n8 zYyyhr5KvS?Kv5|HMP&pO%_X2{9sxyX5l}RrfT9Hi6rD{76^#r0A03eR9d=jfWGOn; z?j)TP#LSl|S{wxSYo}9+&g1k_w1h21=d-0~DO-w`v88A^TZ%4VOVNdFDO$mnqKnul zT1i0B#RL?sBB1CJ0*Y1>P_%}CqO}ARts|i5QUZ!DBcSMV0*bC6py)~hiq;cQw1I%4 zs|YB%nt-Bf2q@Y}K+&}X6kSI^(e;E-(Yb-&-T{eEwufblr04^?ExI9ynJ-gxa}e0C zEl(-Bh0{yXt!ydU%$B0t*iv*mTZ-;rOVOQdDY}a-MR&8M=pHtT?j@k;J_3sFC!pv7 z0*W3aplAyLMOz6ddWe9chY2Wpgn*()2`GAufTG6ONnP?SzUQH+413<8R(5Kt5+pr|SVMb!u>$|RsDix4XMKJe2|cZ%%muF)T) zXr0~FPNc`omno{A9yBYEq8glDifXc@s1{p_YO|%N4qJ-qvZd$^=3;^A2y2m5>V8SfTI2c6b&Gt zXdnSag9s=ZOhC~P0*a0&plB!oMZ*XvI)Q+q;RF}lkWr|Ku4<4K-MQ3n&DJoz~(Rj8L z6|$vh0$YkEvZZJeTZ)Rtzb*hMQkZr z$(Evv*;2HMjiO5kC|XTG(Ha7Z))G*(j)0;|2`IXZfTGI@D7u1xqALj~T2DaH1_Fw% zBB1DM0*bC7plBljMb{EgbR7Xj*Aq~50|7;w2q?Od5Gpz^-9KuwQ)IuhG`d8Ja#Ii3 z(qrb!6m3oqdQO$1+c>=x-OiSxJJ?cmCtHf{VoTB8Y$>{jEk*aTrRYAk6y488(E|h& zJxD;&76OX45>WII0YwiJQ1l1^MUN6t^cVp}j}uU|jew%<1Qb0%K+%%~6zw3O=qUn< zo+hB^83KxS5>WIk0Y%RdP_&B>D!L`zpX7kV@3xztTcxO(jpx&2=F1eloE|KnE=8|! zdMSF9Ek&=frD!)>ie6_+(Hm?jdXp_hd)QL6mn}tau~GCk0Y&c+Q1mVVMeh+%^gaPa z9}rOVApu1n5m59o0Y&==DEfqeqE87Z`iy|0&j~2{f`Fng2`KuCfTFJnDEfwgqHhT( z`i_92?+Kxz7t{Sa9FX`P`-t|E6!ox&{Xe9~%$F(pIX!r3h7|q6>80oZTZ(>VOVMv^ zDf*o)MSrlR=pb8){$xwhUu-G*n~kDF1Qh*4K+$0WivA^_$cyP=JBlI%6r~YRuEpeUVyq8I^183YtnA)qKuKv7i!imDM%lu1BQ76C;G0*aCZ6lD`aML(tc`yG(@ zBD?w7FGUa9z3ZG<%zT-mTCpIzSc+ImZG|BDLR5JMfKQHRG%$HN3x~pD7F+e zU`tUh8$}HXC_0*eqDBN1H71~_2?0e-2`FktKv8o7idqm*bPNGSEeR+(mVlyG1QfL< zpeT=kqBaB+)J7#==MXnf6G(Q!Hk_ zOi{O3aMBzp>dxtplApIMaL6RG?aj%VFVPNKtR!O0*XcuP;?>zMI#9)8bv_SXab7H5KuIhfTEKK zC>lpV(a8i9okBp-sf18bmzclM0g1a`202>g#A1aC#}akS#?k*iv*6TZ&e) zrRZX|6s=-Q(IsptTFsWCHEa~EC7@^>0Y#S*P;?mqMVAv$bOixLR}xUPo`9ka1QcCG zK+)9%6kS6=(MAG_t|g%8Is%HWC!pvC0*W>fP;?^!MK=*pbTa`(w-7=_OJjbt8CZ0zk)RNL-qzZ8p^ zFH`hdEGRx(igt5)DSDkPMQ^aB=uNg1?O{vNUbYmy#g?MC*;4clTZ-Ogqv$;Xiry!n z=mP?ZJ|v*%BLa#(CZK2^0Y#q>Q1mGQMV}E+^f>`VUl36AB>_cW5m59s0Y%>sQ1mSU zMc)xn^gRJZKM+v#BLPJ}5kf_;#Qe)0koYXSEA*-qJz}>-`(rWlWr}`{1zQ(N(Qlky zihgHH(I0FnI>?ryKiN|B7h8({W=qi_wiNxtmZHOK6#Yv;k(Z%|?I?;6P?SbMkxxKT zlz^gufTDB)iedy5We`wQg@B?s0Yy~_D5^$4Q6>RJSp*a%2q;PtP?SwTQ4Rq`)d?u7 zK?oK767%14K;ld78`BO*Q41qgGb3icOi|s8;O|9JbOfiDqIzs8s?V09BiT}P6kCcK zu%#%MEkzC4Qgk$1iW;#|)R=&xCIl2UC7`Go0Y%LTC~84K(J=%RwIrbESOSV#5m3~c zfTBDCirNrRlutlWTLOyO5m3~gfT9ir6m=w^s1pH2oe3!FLI@Sr&hT>=J4K`Hn`G-` zgpc(1+P&+p88P!^ijK<&dM}Zpo}6BadayuDVmrO zT)0$5~WVRGdVN20ewiHccOVM<;6rIVIq8V%{n#o4dECPy(2`HLPK+zlm zib@D5DkY$(jDVuK1Qg99py(_Dislngw19x3vk53Vhk&Am1QeZ1K+z%siWU=4bRGdk zO9&`BpMavJgiujohJTj>5JaC#}amn}v2v8CvKwiG?UmZAsQQnZCF zMO)cY^blK$9%iHH5dw-HC7|dr0*W3dplBNbMcWA|dV+wWCkZIpK|s+{1Qb0@K+!V< z6zwFS=ve}ao+F@W7Xd}j6HxR50YxtoQ1lW3MK2Rj^a>$VbZ3U&*#U{4;AZqLDQaLJ z(O%7nnJ-iHMn-V*N-27i(@W7FwiNAUOVL|wDSDeNMenes=v}rHy~mcK_t{eP0UJdh z5>WIJ0Yx7ZP_&PLqE84Y`jmj8&j={`oPeS)2q^lJfTFJmDEgX!qHhQ&`j&vA?+7UR zo`9ks2q^lIfTEuWDB4dz(a!`F{Xz&8?auHQIUw%inS=AX6y0f`$Ucw}Ghe3YkBs2@ zRZ?`2(@W8xY$^JSEk%E`rRWe_ivD3s(P6d}{mYgjuZkYGOHqW4qBH`Ed;*H11QZ1X z6r~eT6eFN0gMgwc1Qf*yD5^?8Q8faJG6^WkBA_TiKv9x_qHF?+atJ7@PC!u&0*Y!9 zP*jV6qS}N|(Qg_4P6s5u$Zmdqm!g_B>QsrDFH=;%O7O*MDLRtVOVLqmDQdu$qFlBV zHDpWC(QGMd#FnDQY$eEeI$&hJd1$1QZ=hKv63Kidqv;lt(~O z8v=^*2`FkyKv6pairN!U)PaDajsz5SBA}=<0YzO1DC$Z;Q8xmLx)VZ0M^y3SYn-BX zc89uNmGF`Nl+**ZDlzkAih5TGTCS6#KAc{P`m&{{A6tt0v!!SNTZ#s&o2q-#%fTH096pbLD=tKgFMiNjoih!cg1Qd-SplB=sMJEwZG>(9x zlL;s~g@B?{3I7jq_Z=No9k=a%PxfqvOv+3`uZE(6ln{EAj)0&@QB*Vp2)!l&K~X@k zAy!mSuprp5q9|5G#fk;QE-DsO6csyG&hI<>zLNMn>s{yk@ve1POLy)o*^?pjVVFq> zplA#MMQ0FDbS42sg#;9hC7`H?5Gv}K?hkW7;uG!erAyhOW-M`KOiN9{2bu5;mxOA{w3rDz4`OVMR)DY~33MOUz; z=t{N}UB#B7tJzYtk}XBou%+l)Hj1tzplB5VMXL!Yx}Jcd8we;`LqO450*Y=Vpy(z7 zif$&L=oSKs))7#2D*;982`Jh?K+$ak6x~ih(H#U7-AO>vT?7dXOze53!|aGh2!tW=qi{Y$@8pmZC@5 zQuG*GiXLa9=m`Rfo+O~?DFTYN5>WIs0Y%#gD0+r~qGt&xdX9ji?F1A(Pe9QN1QfkU zK+#JC6unG9(JKTL?I57&RRW4$BcSMY0*c-splBx{RCHgu-*~lC)Yra@f4>y%u;*yI z(qrb!6uq4u^u0lf-r;;HdY3Il@3E!meYO;Rz?Py9*;2HJEkz%(rRZa}6n(-*(Ov?I zJ|&>&GXjb}C!pvH0*dw#Q1m4MMPCt6^fduR`w1xehJd1P2`D;1K+$&u6n#%X(GLU^ z9VDRWM*@m|BB1DJ0*Zbipy*dZsAzY(KiL6^pJH&{lA>MqrP<%oW9G{g{h1zIvQ~=z z;(RIkn=M8Eu%+lorKmX@MaK|O)PjJbmIM^FBA}=>0Y&))6ty9ssDOZ?wgeQlBcP}~ z0Yx1MDC$T+Q6~b5IulUTg@B^21Qc~6pr|_mMLh^8I+lQrRX@e6b)oc(IB=I4Q5Nx@oXs?!j__;Y$-Z{ zjiM6?C>lmU(Mbdp4JV*z1OY`O2`CyxK+(wr6rDmq(P#pSP9>n|Gy;lFC!lBy0YzsJ zP;@2%MTG0Yw)P zP;@Z?MVAmlMU&$GVh1Gtl->PImZEL;AZd9#X1+|({mEk#$e zrD!EvimqWx(Y0(Tx{fVHtJqSsnvJ6C2`IXOfTA@76s;wo=tcsHZX%%QW&(HyMcjYE z0g0brpJ=>Hit_B4{{8Wo`7%Wh#e=WzkfP0;FGUZtrRWj16m4Nk(W7iBdW_cW5m59s0Y&=>DEfwgqHhT(IzT|tcLWrDPe9QR1QZ=4py)>eihd%X z=w||oej%XfR|1NDBcSMa0*Ve1LPhVy{oxKsJZewN-j$*>`|a(Ic+7m6qJQE+={-{P zFXv0qVYU=`8G7a}MG>|XrLm>RXG>9(EkyxaimI@sD8@!nRRW6A2`GvaP?SMHQ6>RJ zSp*bi6Ht^OpeRW|Q4Rq`xdaqdBcP}{0YxP$dU7Xpg95>V8QfTHdM6!jpW=vV@ZdJ<67i-4lu1Qhilgo^Sq{Er=wcz=6b z)F>l-rhl{D7xm4EnJ-gxTt;yC0Vx{D`BF59Ek%RbQgl39iiWVIXee8XPGC#XiEJqv z#+IU!*eDuKK+y;SibfJpG>U+tlL;s~g@B^b1QeZ0K+$Og6rD~$(HH`X&LE)ZOah7u z2`Cy%Kv59^MdJu48c#sc1OkeR2`HLKK+z;ZsHlI2-*l5xw9)=B$N(w2)V(e`IU{Di zOwsg=p#MWsG=uY{XeL{VX0fGcHd~73u%)PkEk&hlDJo-2(Ok9^&10kJECPz=6Hv5( zfTFVrC_0CLqJ;z$ol8K`c?1+KBA{q70Yys)C_0~jqNM~BEhC`l0s@LIB%tUb0*Wps zpy(0;ik1^lbSVKvD+r;YsTuxM2P9r-U&fy%MP>Hr`m&6e`7%XUWdxT#EJasyz7(xw zOVKrKDY}*|Mc1*VXcb$ERT|BfT9fq6x~KZ(d`5j-9bRnodgu!ML^L;0*dY?py(a~itZ(#=sp69?kAw=0RoCP z5kf^*WcUv_An~*9zUWFR`rW=X`(Q@Qe3_z0GJ;)Oq-YE0OVOijDSC`8MUS(k=n1wI zJ;|1$r`S@ol`Tb2v!!So8%56$Q1mPTMb8mXw4H#W=Lsl!fqAG4+C6SfrXWlPbgY$^JTEk&QRrRWQ` z6zyZ9=t}~Mz9OLLYXXY)6HxRG0Y%>uP;`KRqVEVO`ksKI9|$NqNI=n#1Qh*5K+(?x z6#YU#(XRv){YF61?*tSbBB1CG0*d}5py)3`sObF+zqdqKz_R=F1cvnHj9#Dn&PbLRF9M2s6HwHLfTF$x6!jyZs6Qc8)Fjh? z$pMM)vHPN?nc*}2f=o9CWX8;wDH@y^?B6Cu$8)|E4Pi^sP_`7Ez?PyD*-|u&Ek!4> zrD!-?ibk-dXe1j&qX;NEnSi2G2q+p&K+&lL6rDyu(dh&fjUk}u3<8SIB%r8}fTFPk z6crIrG>(9x@dOl2AfTw2fTD>66ip(aXfgpsQwS)UN(dDV%=ELLaf$-_tm7alvcGU9 zIxRD1zD&`q%pm_cDVojsQZ$DxMI~%0DrHMi8C#0xvZZJqTZ+zNOVNC`6fIz*=xhRt z&LN;^Apu3_5>Rv=0Y!@lC|XQF(GmiR&L^N~DFH>x2q?OMfT9ZtD7uJ%qKgSAx`cqD z_^HWE;DHvvWW5Kwe40Y&!_P;@^5MGp{Aw26SC2MH*8 zh=8Kagiz7dnf?t9NZhvv)GMXv!qgMC%$WHyMUQ0$PrN8ak8{2hJ;9cuC)rZ;6kCe6 zvZd&0wiIn+OVKlIDSDPIMbEKOw4H#W=Lsl!fq|%~^0R{DUX`L~)_(MRB$iWw50vlPyJAY!qb^P?R8` zC`mw34gp2E1Qb;xpr|?lMKuU0s!2dmEdq*a6Hru#fTFqt6xAc3s6GKj4G1V|NI=mM z1Qg{FP}GQkqQ(RiH6etGB3b@)2PD4Pz5tt+6+TC+=3WPkRSHv)>f6HwHHfTCjwDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*ZI*x#% zfrL=eQCa?j4oJMY!8uxrYS?dYgR)}g%M=aG3U=?5q7yh@icVxp(J;0Yoy3-+;cO`y z!Iq+tY$+PWmZFo{QgjL%MWYEQI+cK;(+DU!oq(b-1QeY?K+%~56crLsG?sv(A_9uW z5l}RqfT9Tm6crOtG?9R!Ndy#4CZK2v0Yy^@D4Iq<(R2ceW)MO}$7lJ69FX{>c3(6^ zitN)w(V1B>^JR)kvVuChrKptirKpT8MRVCwG>z(Rlx{QFL%LypDf`Fnc2`IXXfTF7jp`zJY{;>{7yo!C+agG%Awfmx#SuyividJO> zg>OsIYR;FU>)BFt16zvLu%&1%TZ(REOVLeiDY}_0MYph}XdN3xw-Qjao`9ka1Qgvy zK+)|46x~5U(VYYo-9py)mVitZ<%=m7$XHW5(tAOS@W5m2<5 zfTD*9D0+l|qAi3_(Y0CrG6y97o_*HwIw>l(N7s*L#mtu}dNM1x?OiE)iu0vtD_e@5 zW=qjFwiG?XmZE3bQuG{King<*=y|pjy}(A%iv$$CL_pEY1QfkOK+z5Yie4q4=rsb0 zUMHaF4FZaG5>T{@fTA}EDB4Xx(OU!*y-h&TI|LNHOF+?k1QfkbK+y*T6n#iQ(H=sm z={|VTQ-Ug5K#0T0Y%>vQ1k-BML^Nt1Qh*4K+(Sh6dfj@$jjCfa}-4gp`uT+{Nx8t(RRBp z+ABqW+Lvb2vSa4U6jjL%3ie1*jPs?aDqD)u*-{i|OHl?}iZa^^g5l~d0fT9Kj6g4EE=m-Le z@(3tuL_kqv0*aatP}G!wq9X|?I*Je~ie~#KJ0S6=3{H?8KGS!PwA~Z7?3np7MJ=*} zvp$xhmYgp|t=Ll3nk_~7Y$V8MfTGR>6m=n> zs4D?Q-3Tb^PC!u)0*a0$pr|JSMZE|p>PV8SfTI2c6b&Gt=r{t31`<#- zh=8KO1QZ=l2o*KY_SZTf@j3Qq9gmTsAB@zH?3np7MZ>a#r}j$GNt`c5!`V_af-OZO z*-|u$Ek!4@rRWs46pdy}(Wz`HI*pB@(+MaVLqO3P1QeY~Kv5w9MPmslDk7k0905h+ z2`HLCKv6LPMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gAGYKe~ML^MPLa6A3Z2vO{ zBz~m*x$6_9DAOKY&&iINFH&~T}eRERRk1WO+e8~0*bC7py*mcsHimCZ{~o+yV-qFnH2qQPy4US zj+rl0bVGJ9XrC0V;e07t%a)=W*-~^9TZ(RGOVKTCDO$&tqFdQgw4NfpOF+?m1Qgv*K+yvP6m24)=s^OC9wMM(YI_VI>45q@7PlGJsU+o5KwfGfTAA>DEf(jqMr#U`h|d^UkNDsjew%x z2`D;5K+zur6#Yp+(O(1<{Y^m8KLiy0OF+?K0*btZp0=YXLO@X(0YyFmMNvYi=(BA9 zPX{FamcjX4iY_!#K_X_pOi_9wsCPh$;+!u<8Eh%aWJ^&NTZ*#TQj}mzQIai1IczD) zWlK>tHj1hfP*j6}qM8I0)gqv%HUUL-2q>ycKv6vcis}2o<$V_!l}L@n`KhS}Q5~IrW4s5i?(=Xhb5oaPJzR?N?Y^ii5i?(=XnrF2?k6c)!1+>iHd~6$VN20MwiKPqmZJ06QnZLI zMT^-|w1h21=d)3?lz^gT1QcCBK+%N+6kS9>(ZvK5T|z+7asrAjC7@^p0Y#S)P;@x~ zMOP3|bR_{rR}oNjH33B{2`IXTfTC*&D7ub-qE!SGttNzu<|X{xpPiyB?CWS}Nzpxl z8`mdd=F1e_m=`MlZJ&btJP|Wrrs%6g@bn*2^fl*8(SEiReZ!Wb zZ`o3GfGtJev8CvHwiNxqmZF1fDf*F(qMryT`k8>DUkE7rm4Kq(2q^lUfTBYL6#YR! z(Vqkq{Y600-vku>LqO5L1QZ=6pvX(=X*-G{1QewaP~;O(6eXZ2AfTuU0Yx!FsAylp z|H1)@54PXLzLcWLc3)IA88cs|C^H!Ze@jso=SxvGTZ$5FDN3@XD2FXYxojz_#+IV$ zY$>Y2mZF+$6xAZ2s5SvbbqFY`OF&UQ0*dMrP}G2cqJ{(%9YH`*9sxy-2qqM-fnTGyz4;2qc&PHCZOne0*ZzZ zP&AZ)q7w)xI+1{)VFVPNL#h=8JT1Qd-YplAXCMa2XZ zO(dXb5&=b%2`HLEK+#kJilz}zG@XE=83Yu~B%o*(0Y$S3D4Ih+Q3(M>r34g}5l}Rj zfTDSXP|?Vw|A+$;A7WoR8zn{c?3w;q$(Z>vMdu`gchjV3A?Hicxojyqk1a)u*iy8Z zEk#S%Qgl9Bik7maXc=3IE?}eRLIR2|BB1DE0*WpnplCS(MVAs#w1R-5%LpjCoPeS$ z2q?OefTF7iD7u<}qLl;`T|+?8wFDGhM?ldk0*Y1>P;@;3MK=&ow1yBWT9EYrc0l4& z>~q&=OVM?9U$izEGhe3YmSoVt{dEwj`=WK6FGaVqrD#1{iZ-yN=r*<#-OiSxJJ?cm zCtHf{VoT9RHj3^hpy(a~itZ(#=sp69?kAw=0RoCP5m59X0YwiHP_&tVqK646dW3+Y zEd&%jN2VR{2040+Ac+#?9ug?$(Z>vMc*WYyV9lT zTh5oF18gb!jx9ysv!&<mML)Bp=odDMekGvjHv)=&C!pvM0Y!fh zQ1mAOMSl@c^fv)T{}530F9Ah|2`KV%^t2sC5dwGv*qLKDYKO-k*zD!XfC-@;lijtf!MLBFK%4JJYHMSI0 zXG>8HwiMN5OHnPh6xC)+Q5`ml>Jm^?kAR~31QazOpr|1MMMn@<(~OBLa#V6HwHI zfTE@Z6dg%G(NP2x9Zf({GXjd56Hs&v0YxncC~8SSQ7Zz9S`$!|PY4xd<@nVzouV)8 zvyRz0;WPc)?Y^i@PRx9nqV_pKhiob8!1+?tku61?*izJ)Ek#|}Qq+|#Mcvp^)SWFw zJ=juoEE`2V2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Y%3VP&AN$qCo@{4JM%Icmj%s z5KuIffT9x!C_0gVqG1FSokT#PULhYoei9Na=l@l{x zrs&k1;GCosoyPf6bUIs##;~R647L=V$(Eu*wiJzJOHmP9ipH^}XgnK569_0OCZK2{ z0Y#GtD4I+_(G&uTrV>yzjew%*1Qg96plBumMY9MfnoU5_90H0;2q-Egps0+1qPYYV z%_E@bECPz=6Hv5(5Gpz)$G^n^iSM-gqR~>c&pritc23NEnWFP@f@gB2Xc6a2(PFj~ zEn!R1`D`g#%9f&KY$>{cEkzfyrRXBI6kW_l(Io^FEhnJpQUZ!r5Kwd(0Y#S+P;>E*Xd3}V&k#`bECEH&5kf`la{QJKNc=tftmCax z^nu+MZO@6BFH`hVPB65V6ur#(QuGR2igvK2=vB59y~dWJ*V$6^23v}DvZZJjTZ-Of zqi8n)MQ;&M^fm!S?+{S*E&)aF5m59#0Yx7WQ1l@IMSBP+`iOv{j|nLHgn**G1QdNr zK+$Ie6n#!W(H8_1?IWP*O9G0%BB1DNLa6A49KXZ?iGOd;^k0;sKi%u1`*ULE%M^W= z6RfNwMc;G26#c-KqJwNH`jIU~Ke46gXSNjm!j__6*;4cyTZ(>Xqv#L;MSl=b^d|vD ze-TjhHvvWe5K#0l0Y!%iDDrakv>ine0*cZIDDnv?iV{#15KvTwfT9=yMO6tXN++Nw zPC!ux0Y#Yv6lD=YMc?N5k2)ant#)5@K#FSH?`YY%G4o}La&v?C>q${H&X=OY2 zmZF+$DXPVmqS|aJs>7C|x@;+`$Cje{Y!o#hpr|1MMMn@<(~OBLa#V6HwHIfTE@Z z6dg%G(NP2x9Zf({GXjd56Hs&v0YxncC~8SSQ7Zz9S`$!|Pe4%{0*VRG}U#6&2Zg50HDeBDmQq+YlMP1oa)Qv4g-PuyqgDpkJ zvZbgeTZ($IrKmR>MSTb;>PtXTKLU#S6HqjOfTH6FC>lsW(I5hf1`|+pJOM>R2q+p# zK+y>V6rD&w(J%svP9mUaH~~c?2q+p!K+z}yicTh==oCVzs6(#b&jE?IFgP8hD9i4P zM(4)Nmnj;P8x*^LkvR2rv@AqKRx2 zO(LLZG66+X2q>CLK+!Y;il!4#G=qSmnFJKgBA{qC0Y!5NC@LYKsFZ-BG6IU`5>Pac zfTFVqD4I_|(EoSijhQbm+e?c!Nw0TQ#7o@azGUkqUN&%v zZ{4RUt0uDCv$@PfzI$k%Oq`VEdDRowCOofp;=>%ztDk68-ShGilWKZi)5N{CJ+E2f z=enNPGSQ`h=e0>JI>PhXC!TNQd7Tp(O+BxB;-sTIuUBGKGtcXn_~;nV8<=R)%JYUK zrsR9xu*CfZo;Nb_Ydg;yo#@ul^Ts5WboRWli5I(i-h@O}56_#N7}3-7rYElN?Rm2k zpY-*-vc!=CJa2wt+Ca}+nAkMf^A;z5AL4n-5Qn&+)ed^*PSZb=+n=y@9wGm1R#&cs9GJ@1~xAH|;cK%(bl&)b~1V5;Xm zn%FVj^PWuP%<{Z#iBsly-uA?erJnav;`6zl_iCcK`zJAWCT5-Od2b~iUg&x6CH^|k z^Y$cqFY&y+iHnwc-WQ42F7Ujs6V)#EyaS0-mwVp9#LX)_@0Y~B%RTQo;BJCQ@{+agHi#tOxXIlJkz|c^?pBB-PhanDhDdVV zZSHo6B<)|bZyHJ3KS$mylC*zMx@9D3{~&OiNYegA*Y=U5{ga%XBT4%=6}v~0_K)KA ziX`n{HR~5i+CNJ*Fp{)?S7=Bixqq9xO(IGAmpw*ClJ-wCjE*Gj@75m^N!nkIJ~ooH zzukI5Bx!#=@#IL-{(jl%k)-_vp|c}N`x_q1B1!uz`sPQH_IIo;j3n(Z$yyvq+TU`t zERuX`ue*gJN&9<7Rz#Ba7e!ndN!oY%UlU2%w`#ABB<*``*G7`|&62l7lJ?zh8zM>j zcBMNbN&9}2dm>5uhJgnnN&6Gun?fK_{ zNYb7_9E>FG5#TS8r2Q6tD3Y}M;J+hY&N}ytCb}W~C6{}JyD_`CUslx?x)(kPyy|t_ zFQcGCPBYhP92ar7bUXLv?nB}Ji>$48bi}LqzHhaGomtgh<$ly^1S`&RpT_fv~C(jHo9w!wQJNvBg-!BSdGWy zZuHccXxE@uIBGX`!>)Lp$goHo&#Sw}-GSJD!I6I4i{wO(%&wN5$P?x!7e@T^p+7Rks6-yq^cd+)U`IX~h)zynuM%;-%HTs*k$|uG`wPcQ7+M zb=mG38HY+g8oHMw-Y`3qq+T3l2Y2`7`QF@fZ?+eVqwmc*?`C&Q{iyH$Z@)3P8!7dF z`=7m0 zD;{4~JRyI4$%5Hsvn-4+o-nthxU|yi?CsrKcgde!GG)e;vMKY5z5L0uW)$ZaO)s9G z-+KD2@kP_~OD7kV6z7)|&nzx2D$Or$TUc5)cfyoe`DL?aO&>qGXv)me{7K`-7Z#Pw z$S-J9*sic`o3;go1#K+0avpZ|)vevD|MRN+DKp1UpF5#A ze@4;x$x~+j|9&+}7nD~1NKBfX-@9bO+$l3>^_^8x+^YOzF~6)N^&tsABEw2%O?4mh z()v|X3Us1(=~?=FjMTJ z!{oU;^&q9wZx;!IYX7GnL8OX5DH2rk>*NKwje>|jv2{3tDm{YSD(=)OZQKK)NR1%F z4vCr9S~|8og>l`kPLbqVerYBSEFX@Mn|OHV>tf%VviuKc|jyUFRhCE6*s*9afJig4D{?+(7DaP!g1k? z9ov_`*r9Lviyb@bE!%gd_2%R@?Zemg@2j^daBnu2;bTF2%jT zPqTmd&!fOynbg~Nac@>w=+17}wlKVe0{6~1VE~ubTbI@+yo5qyD7fLz(tSMKNfYMI zn6V(dT%FmTtI=DbQ~A|#AKvo!Q~oa7^B((Ed}!PUL~rPR0^z%JmlD39D`dB4Cr))A z%G4{}hgs)!D8DdweR!vB_4e&5u1DYUGYb0huG|&Z8RntVz3cz2`;>mggI$}7pIw*opGkoe z?H%9$)WY8VhNsSRH?)3|4zynC_n$L8yGnVf|NSp?1r=AMk6gje-HfSsfVXl{ps-6W~|rHY%? z-BszT6u9fciv<-QjY>CeC!Nj>5W2Ao>|F7oav#X>eYEABRow6e6}NmrrJLT}I^ii5 zH!`E^CA0hso!M6-&^{ZpY3h| zU1G&G;5K$2A-%5rwsbc^_#P^3xcdwDR;de5y~^FTI?LVn>!tFah;tX7@9r?|o~tDM zs1$?;{l-_J!S0%M5#<6a6u940-78Bc&nhV^|82}+<649_dim{L{u{3QWs-UmyG>Gp z+(#pPp%Q_Lo4lanHZQ2S(YZwm+?DnIZ$1pyqxgykcXk!sZ}+Kd$jw>cesP3XxssL& z9PVePk6M9yfD*o;`^B#p%0Hw9Asu@MmG0pSbcQ2SaqGF4jyqvgUf(WV^6a5}>w-Lc zFyE$g+xB_QN{Xi!7nK$_&ucYf{Oq|s#=D!Ncz&xH?b^9eHhJ!haqc*A`mCa|R_>WV z4|khSu;AWu;_P`HT9wXjHKCxRD@7&aC--nq4d!)jHKX+m_vE6*gwok9CeF@lH7T#v ziEZ;*xks}-#=9%fYT}II($bjEBy zRy?AtcpzEvIMO{Lg-`fP%r2|^7YUC+!-t0>3J3P@JuLO!Dm_T#k!ZyuLVnQ|aA$6h z7E`A|IeZ|P`bgMgQ9V3O{fxt3;^iL&eo2?xhPFK>omPG?%R|qK2ZR-m2SHvgp#0%x z`Qym)hm4heHC6nYsCdA~4PNnZul$A#A2WK#_3hg=ubKV&>0L4-um6m3#SfX!S^qNG-p1q)w!6q+X}O!d8aleqhexre zVLFb|(S5EV_4=tg&e3s^j`s7n%ezv?^*U~{Pgc49l#aXIO=|lS9e;H{0oxJx2~#`P zaz7V4Hqp^O&t|*7j;FhygY8K=-r{aT+xP1DrTYNb{#nPC?qg)Ti;gAkODeV(>G-Jo zg=7199sjKx?u>fjv7h^bi@p9N9hV;w?o~SObRSrI{YN_1Y#Qz+I*vIi+*5SC)!hL0 z_V?@f^)cc8Rmaw?!re{BGIvAS+b_}a@q%!_sH4|D+*vvfa5t#E{RkabIDodV*YVA+ z;r>L&+U|z8*B`0lnLWcjO~(zr!@WtzZ~BJ&cOBad2zL)1=M4<^QXQWh9PXEOOdA^R zgpLDG4EHDDYdLxO?k(_SxaSNXKpNOCWZAU(>P5qHtH!ambQzpQ_{4OT&G$j_+L% z?tMBoyg1w~beym}+;eo?xFXzJbUb)@xc||y<5l7AtK-6z;l4!2XRi(S8#-299qt-B zo^V6BPuKC9wc%c;;|Di|`zsyu)`h#3juY31yHv+}ZVUHgI{tJ=xDV^td1JWy>v-Nh z;l5PI?e~RymyYpG;jX3Qu!q8ZhK|=g9Pafx?%5LV{W>;&Jly#@PJS}nb9KCLYq+1# z@t1Akjyw|{yFM2lkJEAS^WnZs#}{4<_ii0CUkP^|9f!Xf?m`_`zaH+}bo_W{xWCo0 z>F#hB=s5N5aG#~)1Mi0WDII@%KivKY;j#Ok@Hj}v^FI#v6*|7OH{5UQnEiRU>*+Xh zU$~2Oyy2^G-=X8){o(#j$DO%)n5OMj(@tZs@jgZZ)>t+FZbnDI}X+HLicr6+beZ^)qTO$_WL^Ky05(2K0?RQ z?n|(?i*>xoeJ$4Z-8z2Zz9?(^M;(uGU!AqxNypiF;XYT#N8HzI?e)*;Sl@j~)^=AN z2k1D|j)D7{xAr7E#yxMEjbOJ4_jKH+<4-ys)-lt4ZPng? zeLK4Am#1S@d)(rBrjFHgtfgZ^9UJS|LdSd^tJu+9NK)G!QkUl*?xc>T_BhC0zI!<0 zr6t@~8`Ztmr3+@16^(PpvXbyPnU~y?=rXUhJ!|z^k1H+pTD#}jtu40x@59DapJ1N~ zcAt%(ILn=qdbw!axRT;|;aOpEU(>5Ri%RU_rY<*pi~n7w+gIdtiSCMdt;f4B9~HYV z8B}_&6HAI_xHsxOd}!;Uva*sXW#w04qvNb{c`?n9UQ(a8PZ z-p&u_|9U%no&7l4{b#r5|J&QOac}cK-|sTl_+hu5{b=d_a}P_sUhY5pv8P)kbvxH| zFWcMLfA;=_uBcd>h!bKHyG%kJ{*?fAj#mbp;*@>W#3ye#)RF3&wg_|N6N?=Ei{ zH+H4hUH3mOZ>_sLyPfR%xnF|imv_5+*{*|mupei%ig?}ajzB-`b@re8t^Yr7cYT+L zH&}0D2i|V0UglL_xVJMy{IH*g{csNj{`2$QQ0eDu_doo6cet0`Pj9w6q<$p3M!c>J zceM9wKkUe_728AH+YNKk?!)XEtX-ac-0fpr>BHr%b^dy~#t$wp$A!vox7l644|yYZ zhjy*>=*fCb1#AiguTu zg7Kd$pr-qT*PX0M31*gfxFvLxcB{h6Hbc8f-Q_W{hD=C0Q@l|S0<%BDrC zOta^!k*epp-_p|3fncDXn4Yq&S}TUP6BFK4({`)#V*T|{t&ogb<4pnGRkqS2!Q z`$LB@`>$=&| z{e^s*b=>UaMO$mucC)h=&DX5uW*7H8{hBr1EO1w=K)Z%*cfHzbSGVo1SUc@%w%s*r zubpe#U9}F{Ikw$(>!_Wy?XFxW?SyT2?K*2`+jdv4i*}Z6cm29*XS&_iUB7PH8MfW^ z>#iNQ?XF)B?R4Aj`W>rX)wa8SJ+))D-Sz9GUB$M$e!aB=+wS`H(T>`7*RQX(Z`)nJ ze%fhnw{zF8zjnm7yM6<-9fPXTXjA`Xcl)RRY<`YReZNI|Une7aTgBji+V zgq)_0kkhphGDaIAXJ{kjOl^b|Y9nN*|XGC><5#o7p&sEv?G+6bAf zjgTqY2$`ylkZIbXkU{>p?)Fc=-QCed2ZusNyL+hU^q9#pA+rPf!^$Zkb9AbNlxRvw zsiuUKX-ddkO$nK&DIsTRO2~Xo30a^iA!lnMM#!bw2w9s3a+9Wn+^mU^TeK0fP8%V&Y9nO5HbORNBjh%1gxs!;kUO*ya;G*z z?$SocMs0-Lt&Na-v=MTzHbU;xM#%lz2zfvoA)B-j@}M?C9@0k0W^IH#tQ`tj>F2xK zKmA<054k23vfo~QBxZ6<$m4;1lS4|#6FOBwp460(r!*yGtEPlJttlbfG$rI2O$m8c zQ$n88l#uP32zg!`AunhnLcZ3Nko}qn z`9>Qd-)bY|fHp$D(?-bm+6ehU8zBd^5%QxpLVnUl$j{mc`9&KcziK1oH*JLcu8ojG z+6ehW8zFycBjhh_g#4|Ikbkrh@~<{R4r_-(KJv@l?VtX-^uyYaHv z`fj{zHs6hxAn@IINdn)EmqXyY@p1`#H(oUY-;GzDz<1--An@IIH3@t-UM&LOjaQq% zcjMI|@ZETI34AwRJp$j2SD(Ol<24}g-FOWNd^g?^1il+DkHB~1H6rlcc#R2sH(nD0 z-;LLl;DBUBqiGTUaR($`-R@faNT_JPJ#INN5;I<=sCgu?Z?8)!I)?M5s0CY!TC%06 z6SfTB(W6m=$`s0#r_T?r`aMnF+_ z0*ZPNP;@K-MLh{9>P0|NZvu+?5Kz>YfTDf`6!j;dXaE64#}QC8kbt5=giz7Zk<_2@ zh+l1YMa`rr-$)IP#LSl|Iw2C+w`Zmloyhr8G>k1pC$XhyI9rNFu%&1uTZ%@prRZd~ z6rIABqS0&=ok~E_X#^CVPC(HZ0*cNcpy*5jiV6uR8cRS?5dlTx2q+p)K+yyOii!y+ znn*y=Bm#;i6HqjTfTF1c6ip+bXgUE!GYBY}NeC4UiTDE?koaadqeG>rrIDKD{+Nq> z2G%JmjRf}Xy(vXyoG(Rl*-|u*Ek$RsrD#4|iWab?=xnwWox_%*g={H0myM$H2q;=a zK+$3Xik1*ibUpz^O9?1iMnKU81QcCJK+#166kSX}(Io^FEhnJpQUZ!r5Kwd(0Y#S+ zP;>%M`7S1orLWDMiOZe~l-Eo>=T$Cjd7*(h31K+y&Qif$vI=yn2%?jWG( zP6CSVBA{p^0Y!HcP;?IgMfVa=bRPjl_Y+X`00Bjt2q=1xfTD*8DB4Uw(Zd83Jwiay z76OVMC4`Eui}-IkAn|VYsozynG}aV77KxcJQ}k3Mu)kg)rD!YXOVQJ8DcZ)CqG#Ar z^ekJ7o?}bVcD58f&z7PW*i!T&8$~Y>Q1mhZMXwN0w1a@6R|zP3jew%p2`GAlfTEoQ z6zw9Q=uHBOb`wza76CyINb^JR)Yiv;%9Q=}Aq&iPXG1zU>tv8CuswiJEEmZGoOQna5f zMc=Tc=v%fF9blvAI|7QnC!pvD0*Ve2Q1l}KML!Wx^fLiPzYtLLD*;8n5m59y0Y!%h zDEfndqCW{J`ip>~zX>S%hk&Ag2`D;DK#`YL{wzN;_4TL-0YzzqP|@Cqf2IQx-{JoJ zOY~DIdfV=c{Ir<)GDWep!2WuZl%lGfFGcBWDT=eDD1$9UnQSS_VoOmrTZ$5FDN3@X zD2I)rTmp)!5l~c}fT9`%6xAf4s1^Z5wFxMyLqJho0*dMpP*k6Qq6P#MH6))HX)*I< zidv=x_SfU26t&`fDQeA@qI|X#wP8z90b7dNvZbgUTZ-DVrKkg2iaN4U)QNzi&IA;7 zA)u%$0Y%*iDC$l?Q4a!&jwPU|Cjmvh2q@}JKv5q8iuw{z)Q^Co{sa^aAfV_t0*VF_ zP&9~uqQL|d9Zx{f5JITvm^A+z2PEFu{rR3~3n?1!zU&ztniex(rs$-!!2Wurl%nCB zFGVBRQZ$k+MWfhKbTV6tPGL*YXtorc%9f(j*iv*l8%1LXC_00HqB997DkPw2ECEGD z1Qd-UplCb+MH2`pDkh+4A^}B{2q>CNK+zNeil!1!G>w3w=>!zbAfRX_0Y$S2D4I<` z(Hugk=)^R?jRO*&YWGFMr08V(9jzoSX1+|(ytKgndajhBvp8Rh=Ch?}0b7dBW=qjI zY$;mEmZEdnQgj|$iWae@XfYc_O9&`BpMavJ1QabJpy&buiY_Fe=pq7&E+(Mp5(0{r z6Hs(10YxhaD7uV*qRR;=x`KeBD+wsNih!c42`E}gK+!b>6kSU|(RGASQCXTl&jE>d zv`-Pum7@CgS;tjrG4o}L)}#finn}@G&X=Ma*-~^9TZ(RGOVKTCDO$&tqFdQgw4Nkyx|@Kadk84Hmw=-C2q?OrfT9NoDB46o(SrmO zJw!m!W&(;HCZOmM0*bZ}Q1mDPMUN3s^f&=UPY^;y*QfbUIw0|b5eMf6DH>w;MNg*1 z%$F(JmKNAw516_ydWQ3*=vlTDJ;#=!?QAJ}o-IW$u%+llwiLa@mZF#0QuGQNMLP&6 zdX<2p*9a(joq(b@2q@Y~K+!G&iryrkXg2{xZxK-RHUUNN5K#0k0Y&c-Q1m_lMIR7Q z^dSL7dk84{h=8Jx2`Ku6fTF#GP|?;jKdpsR^o>2!e_DzL+oS7G(_-e!6zxk3?5~$h zDf*K0rRXcR6n)K>qWx?s`i3n<-?F9X09%T_V@uKZY$^JIjiQ4D6#Ym*(N6>v{Y*g7 zF9a0*Ns@Ghe1C?g#eQlcp49 zaK02}vZW}CEk)UEDN3-VD9M(h9JUnYvZbgRTZ*c)QB;F~qM8I0)gqv%HUUL-2q>yc zKv6vcis}(9x@dOl2AfTw2fTD>66ip(aXfgpsQwS)UNVf2;!%x4$?#I$w%<+3#pK_%ZWkif-})`|H_Lif-n7 zDY}I%MeEp7bSqnm*0ZH(16zu2V@uKPY$>{fEk$>-QFIppMH>kyx|@Kadk84Hmw=-C z2q?OrfT9NoDB46o(SrmOJw!m!W&(;HCZOmM0*bZ}Q1mDPMUN3s^f&=UPY_V_BmqTF z5m2<15Gq>h`?otF@#d!JMky+=@w6W^U#93eKd`^vKc#3p=S$J^Y$BML^Nt1Qh*4K+(Sh6dfj@ z$cyS}JBlI%6r~YRuEpr{G~MKJ=3suDs)U;2Jq2PD429#DTJMIYMJ{`6?f ze3_!GXkh=mNJ>#Q=Sxw7Ek#MT6y>m`D3>io)!0&0oh?N**iuxJEk(81D5_0BQ5^z` z>Jm^?kAR~31QazOpr|1MMMn@<(~OBLa#V6HwHIfTE@Z6dg%G(NP2x9Zf({GXjd5 z6Hs&v0YxncC~8SSQ7b~IC?o36cR=F9?7k>78a~s1#vWa_j>gQFDQX)HuJ0{H?KoeG z+Owso16ztZvZbgKTZ%ffrKk&Ain_9;s2f{~y0cN#gMgxA2`K7GKv6FOih2`J)Q5ng zz62EYBcP~10Yw7{C_0XSqJaby4I-duFabr!6HqjSfTE!U6rDgo(TM~U4I`lFBm#zd0(U|!%MW;jq`{#{P_eG;QUy4p;OVMd;DLS1kMPt}f zbOu|B&SXnbAzO;ZvZbhqjiPY`6pbgKXaWI6#RL>hB%o*#0Y#GuD4Ie*(NqG8rV&sy zoq(bl1Qg9AplB8WMY9PgnnOTQ2?0f=1QeAKP&Ai-qIm=qoka*0jf(oweooOT_7#wm zrD%)Y7tN2x%$F%z7!B;7$4V(Wm-D6QJhl`qVoT9twiGR4OVRmkDO$>wqGfC;x_~W3 z7qU@w5dlRP6Hs&s0Y%FRD7ut@q7?)bT}D9Br-OBk=w4N{vEk$>+rD!8titc8k=pF)!?j@k; zJ_3sFC!pv70*W>fQ1l=HMGp~Bw3&dShY2Wpgn*(g1Qb0=K+$6a6g^Hr(Gvs|JxM^( zQv?)kC7|eO0*bZ~Q1lETRCIIHztRDTx3T-8Tcl{0J-U828Z%#}=!Ixt|2$tx(Tkif zMK7_X=w-GPy~38F9c(Fjl`TcDv8CvBwiLa=mZF_(6zw9Q=uHBOb`wza76ChO3?w%m!j|3QuIArihf{A z(LuHp{m7Q0pV(6LGh2#&VN21kY!v-QK+*366dfX<=nn#l{v@F2F9M4GCZOma0*d}6 zpy)6GMP8t%?I?2p;8ghKcNC=&P~;O(6eXZ2AfTuU0YxzaimDP&lukfVoPeSXLa1ne z)UQ9(DOzp6qkSVqf7tJ6nL*5anWAJ6*gp@NQk28_Qk2VYEmZCarDXPmxQ9S~R>Jw1ZfPkWg1QZ=XKv5n6MU4n3YD_>;69S5w5>Rv`0Yyg< zP;@i_Ma>8(YED4WF$5H~AfTuv0Y$9{C~8eWQ9c1hZ3v;F?7$!AfW(vb=dKe$_)NdA z-7yseG4o}LIs}3J^Rg*L9XVf$IlD8bUzPPy&ihAfV_( z0*ZzaP;?RjMZ*aw8bLtONCJvR5kf`n0{>12B;LyIe%edXMjIywG4o}LP74D2=ZRB_ zPUn0n8pD>NGuTpeCR>UM*-|u?Ek#9aDH_L?qVa4gn!rX;F#$yr2`HLGK+$9Zilz`y zG?jp&X#^BaC!lBs0Yx(jD4In;(QE>W<`7U+LO@X|0Yzm56wM`|XdVGYXAw{|pMatT z1QeZ32o;SE{O=u*_(ppubgC5HYxhOx1TphviWUWd{qxo-MT~^%BA{q90YwiJQ1l1^MOz3cdX#{o#|S8ToPeSy z2q=1zfTE`eDB4Ou(bEJJZ6l!Q83Kx)C7|dz0*ba1LPfU*{@D&le3w1bUoS;3y4OXY z4`Sxa6ule-Yfh7*S2$macCe-BRkjqp#+IVj*;4cdTZ(qFrDzvhir!>P(QY=1-Xfsr zZ32qkA)x480*c-vpy+)9iasEq=tBaE_7G6?5dlRX6HxRC0Y!TWDEgFuqR$8@`ka8G zF9;~wM?le+1QdNmK+)F(6zwO3ie3!-Z4OA>{bLYb^d%|kV!xw(6U5AyDf&JLJ{==P zKXASj9b`+`rK2c9Kv5b2MLq#VQ38qr0*a~-P!uDes44+P=>!zT2`I`SpeU1o zqAUW6vI(K01A$-V45!Gx?i&40ioUm}{fR0u^JR*vRSAwRl%ndKFGV%jQdE;IMYY&c zRGTeDb=Xo=mn}v0*iuxVEkzC3C~8PR(Gdg`iod2A`lXG>85TZ#(VQZ$+^MPt|~8cRUYI0A~s6HqjPfTD>66ip(a zXfgpsQwS)UNj@~jlYpYT2q?OnfT9fq6x~BW(Y*u|Z6u&*69Gk=2`IXc;3}FI>8&-|C`z+W zsOL-3^zavKk$&sTDtai=*LkcIJjV_NK|s+S0*c-wpy(}vtLTA9Z-D_42-t5CJt#$s>|@c}k$&sT zD%uFwiI1pOVJ-}Df*KwMHks9x+t4YHTU0&X%GY zY$>YAmZDm0DXPtuq9ito>JU&=mw=+n2q>yYKv8`HiW(45)R2IpMg$Z!CZMPZ0Yyy- zC~8JPQ8EEV%?T(duy;9&9P< z$wpBx0*ZPQP?SMHQ6>RJSp*bi6HwHLfTF$x6!jyZs6PQk0|+P@NI=mb0*VF`P&9;q zqM-y74I`lF3Id9T6HqjQfTAl2D7uQ^Dr)EV&NV;+Uz-`xUWzVy%^2zTTVGbuD8KKX zA}Pw{{8E(1mZE&N6cwf+3bqujWTR*m0Y$3`D7uY+qBR5*-A+K!9Rw7uC7@^> z0Y&QxD7uq?qPqwvx|@Ka4FnY3LqO5J1Qcx~plA~TMVkpIx{rXOEd&(ZPe9QF1Xs~Q zzc*^8QMB32h(%KLqJ66UpxH(W9JSing((=rOhwZD&i-<7_E^ZTtYtLQ_&Z^|4g+Q<2&=p(iieax1kPuNnlpDjfP*i!TC1K$c?c*f zM?jI6fT9QjihKkVMG{ctC!i>bfTCyuiUI@_#Sl;wOF&T^0Y&iy6a@(=3K3A0KtNF< z0Y&8rD5^kk6`l5bzc4@o3+;Cu&q&dAmQ=+kzx8DmRgLmpyg`bpaegVP&X%GYY$>YA zmZDm0DXPtuq9nEy)nQ9fUA7cm#zs*+0*dMrP}G2cqJ{(%H6oy>F#$zQ2qV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*Zzb zP&AByqALg}8csmb2m*?(B%tUj0*XcwP;@l`Mb{8qMIEEOqYaS2a0{oC6dkdTMLAJ^ z>&q(2kMiBTP>KpTzZ4a+rD!x;ipH>|Xe?Wb#<8VnJX?w;u%&1sTZ$&JQ8bx=qA3Iv zO(mdc8UaPq2`DNeps1LDq8S7f%_N}cS^|n@5l}RnfTB4B6kSI^(Od$Gt|y@A1_Fw1 zB%o*>0Y&o(C|W>3(L#c&C^yQx%>W7fZNKZ7Cq*?asYOwK>&q%y66Je;u@o)k{8F@x zEk(DmrD!=@if&~~(F(Q{tz=8lDz+4@W=qj+Y!s~_py+l2itZqwXe|Ln>j)@XPe9R~ z1QgvxK+)X<6m1}&=pF)!?j@jTBLPL52q@Z2K+$~!6m21(=zao<9w4CTK>~^%BB1DD zf~)AJDDP z^b}i)o@PtYGi)h(mMuj)*(iFBfTHIKD0+c_q8AA$dWnFdmkB6(g@B@02`Jh{K+$dj zie4k2=yd{$-XNf84*^AQ5>WIO0Yz^UQ1lJ~Meh<&^d134dkH9dpWrHbG|Jo7015On zGh&+*O|zfTK8W&LUsln_QN9t&r05gQFGc&=QgnbVMW3>z=rgty9b`+<=WHqZf-OZ~ zvZd${8%19cQ1mqcMc)umbeMpmZwV;+j)0;g1QdNwK+#bGihdxV=okS-KN3*%69Gj( z6Hs)VfT9xw6#YU#(XRv){YF61Ndk&a5m0oR;40b|<-NfGF`v&2oR6gFFZ+$`Gf{r) z%PRUk%C~X36kXu_QuGH~ivDCv(M7ftU1CeoUu-G*n=M8Eu%*a}*4OP)10=A|KKz`QqA_+{h=8KT1QazPpr|PUMa>8(N+zJF zIRQl}1QewbP?SbMQ91!dEeI%TNkCC60*YD_P}GKiqP7GSwIiUYJpn}>2q@}Ea1~XH z_6AlOMT;X1oa)i;SNhM}(J9(*eOX0aqkT%3^c^<@=}j`mGkBSm94zZ8vSOVK#C6pd#~(FC>>O=L^aB(@YyW=qi&wiHceqi7ld zMbil=Dk7k$n1G@g1Qg9Apy*lxie?c|G@F2;IRq44M?leB0*bCDpy&nyif$yJXdVGY z^9d+gKtRz#0*V$9P_&qUqMHb=qJn7eS_34IWFLMCr6^#YCPmyF?YF+HqFbVUJMWO9 z<(yxNZe>f+3bqujWJ}R1wiK;qOVMp?DO$spqTAV0bO#$nYY8Y?M?lef0*dY=py)0F zitZ+$XafO7_YhEYF9Agx2`Jh`K+$FbitZzzXbS;F_Y+X`00Bi05>WII0YwiJP_&hR zqDKfQdX(TQS{m&=WPk*Eni;W7iu&5`7j297TVGbu6VblE)=AM0&M!qzvZd%LwiG?h zmZE3aQuHiaigvQ4=sC6&JP}5bfP=fCM_&=S6==(NgLK$ zm!djsDXPnsqRZG)RF5r1_1RL?fGtH0*;3SqEk%vlC~87LQBwknnh{WxOh8d{0*X=y zC`u)uD2;%kbOMT65Kz>TfTC6e6tyOxs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9T~0tz zXM(G!X25&a015nHAAV{D+^_WCw4+PFZ+%%sJp#Up<_|-L|HN!h&M!s1*izJ+Ekzk@ zDavF^Q5IW@ve{D9hb={Y*;3SxjiUYp6b&GtXdnSag9s=ZOhC~P0*ZzbP&AByqALg} z8csmb2m*?(B%tUj0*XcwP;@l`Mb{8eltVz#C<2Od2`I`VpeUb!q5^`es9V6>-T(>M zzo{sqyA*A;qcGsNzO15g0pC?yq-Z?nm!b)5DVoTZqDgEin#`7>DQqd4%9f&OY$=+~ zmZBmyii!y+nn6I(Oah9oC7@^)0Y$S3D4Ih+(RBnA%_X4ddIE}WAfV_*0*dAlP&A)_ zq6GvLEhM055dlSu2`IXWfTEiTC|W{5(Ncn|XiUI6&j1O$Y#)BcN>QTyjJ7P`x4x{R z6#?Jo2c&2v=a-^YY$;mJmZIC(QnZFGMYpr1=nl3Ntz}EmI<^$8XQSv&0*dY;py+M_ ziZ&2XbPoYV_YzRFk$|F21Qcy1py)mVinb6?bUy(_4-ioFAOS@W5m59n0YzI0D0+l| zqDKiR+D1UpV+0g!C%B512fS|@Ac5ZY8;!S0QIf}u#{+)r%PM**;5+t^6g|!PrRW*9 z6g|t9qMd9hdX6nc&$FfI1-2Bu$d;m)*i!T|8%3`WQ1mJRMY{+n+D$;wYXlU%PC(Hc z1QhKdpy*8kiryli=xqXu-XWmqT>^^UBcNz60Y&cUiX)&Xo`9kt0YxDKiV_GYN+h7DJOM=&2q>yZKv5+E ziYgOORE2<|sst2OBcP}{0YxanG$K3j?!u%)OWTZ$U7rKmAmikh&cs3}{Dnz2!oOh8d{0*X=yC`u)u zD2;%kbOMT65Kz>TfTC6e6tyOxs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9T~0tzX99}4 z5Kz>WfTC^$S5Z=o_iF`KU<0hu%&1q8%2W%C>l&a(GUWPh7wRTjDVsm2q+p(K+y;S zimoJ}=qdt=MiNkTH33D}5KxpuK+z}yigF1k$|ImCpMatQ0*VR=C>l*b(HMfOsAr6~ z-VUSalKrk@FDbgkye?vFjNkgQiYCVRdOjsZlQ_Q=O=e5c6t)yiWlPaCwiHcgOHmP9 zii+7%G=nWgGubG*mVlyJ1Qg9CplA*OMb{BfG?##)>j@~jfq&q%y9pk&@87aDr^GnehwiMmYmZCe@QnZ#WMeEp7w4N)$PM?ldQ0*dY@py&YtiXJ4O=ph1%9wwk@D*;815K#0e z0Y%#gD0+;5qU{6}Jx)N;69g3PAh?QF#(1AFKmvR1W6>%p8e%`AJsIP-zO15WV|*X& zl%k!SUy7b%OVRUeDSCk|MK7|Y=q0ukz08)PSJ+bYDqD(nu~D>}fTGt3D0-cMqBjUA z+CxCmn*Y0|XR(N^liD9pgQ3fCTDUIL}DYY5Q38S&ZNMvWmWp@l}37iVkspDf)^nMPIX} z=o_{a9cD|>w`?i;jx9w;*i!U8TZ)ddQS<`=MaKvz`jLR5p9m=WnSi3>1QeYhpy(F@ zihd=a=r;n2P7+Xbih!ci1QeYipy(_CMdt`8I!{2+?*tTGAfV_E0*d}5py(pORrGm` zx1#|P_}V_Z{z8f}EvZW}e(TFBa$yaKv69MifR*3ltge9{T<_7V1NXM**`J+j})bw*G1Hc z^;=(7QTx0q2*ZhHNQn#FnDQY$2Lg&Z5>V8MfTGI@DC$f=Q5OP= zx)M;-jew%=1Qhikpr|LoRdiXb_iY0taKJtm)r)n%(r*%LMz2`E^<@=h#rl5QB}Lhs zUyAy$rKm4kiu$pos6ShZ2C$`QAX|zCv88A*TZ)FTQ8bi*qG1FST|q$6Z~}@(5Kwd_ z0Yz64P&AT&qN@ogx`u$F90H0)5m1y%Kv5n6Mfn626%bHVNI=nO0*b~EP&Af+qHzQi zjVHK@GGe{)yNx2B{n1&b6xqLUCSpRY-}A zq8V%{n#q=;YuQpXi!DX7*(jPrK+$ys6wM`|=z0Q*ZXlrOMgofF5l}RrfT9Hi6fGp6 zXb}NLiwP*YiGZS;2`E}ZK+#eHik1;jbPEAR%LypDm4KoZ1Qe|#xQZsldWRSwflc-a z^<*h}(vDTJe(TFBx;@r6V~-Tw!TF_VEnAA#v88A|TZ-;vOVM3yDY~02MH|>sbPrpK z?q#EBBLPL52q@Z2K+$~!6m21(=zao<9w4CTK>~^%BB1DD0*ba0Q1l1^MUN6tw2gqG z#|S9ePC(J)1Qb0%K+z5Yik>8(=qUnsX)XT`Bs8^GnfT zwiJEKmZI<2QgnnZMc=cf=qOu?eqc+{F}4)_$VSmm1Qh*DK+$mmicSzv^a}w+zY-d!vU2eb9|0mXOeOX1`IA8C*QWO#Q@2~WIY$=LlOOc-~MNw=i zie^hufGtHaY$=LmOHmvfMezg_1qmn$5m1ysKv5zAMdb-7sz5+dMFNT{5l~c_fTAh{ z6jddls2Tx9)d?u7K|oPW0*Y!8P*j_Mq9g)}>JU&=mw=+n2(BVeoOhxD5_sCeDHrE{ zjaJ^gE}~wX-}qr6`3hMX78lN@Gh= zIvYhT2qRObPj8uVe(TFB>Ko_# zWSldR(O3eC#t~37o`9kW z1QbmqplA}oRg@j)y$gDpif z*-~^ZTZ(3}rD!%=isrDT=sLC(&1IwLdIE}WAfV_*0*dAlP&A)_q6GvLEhM055dlSu z2`IXWfTEiTC|W{5(NY46mJv{N3jsyT2`IXifT9%y6s;tnXcYlPs|hH&jo>Pp8t1*- z00~6e?>bJCqC4zk(V95F^<@>Ui}U3ikfQaRUyANzOVM3yDY~02MH|>sbPrpK?qy5S zMz$1fVoT9xHj3^eplAyLMfVd>^Z)@x4-!!H5CKIG6Hv63fTBkTD0-BDqHP2eJw`y$ zb^?kXC!pvF0*ZDJQ1m1LMNbh>^fUoQ&k#`bECEG339h0$;=GFtkU$grXC2o{(LVc? z{&R7D>&q&7DbDx6XHxVs=a-^a*i!T=TZ(qErD!)>ie6(&(d%p}dV?)Rd)QL+CL2X> z5m59t0Y&c+Q1mVVMeh+%w3mRQ_X#NafPkV82`Jh}K+#786n#uU(I*5H?I)n<00Bjx z5>WIR0YwK1DEgd$qAv(2`jUX6Lj+gR3vu3e4Uj-1`{%A-l%k9Ff$6I_zx8DmeH-UH z{<#!=$N8n`2wRH2XG_shwiNxqmZD>9Df*EuML)5n=x4SR9cQEH1OY|A5K#0h0Y$$N zP;`=jqEiGEohG2@3;{)F2`D;8K+$;uihd`c=mG&ne-KdgCjmtl2`IWmK+#_W6#Y#= z(LV$fIq~|!97P_2tLU3JZ|Do7sFHmwIxIzf>}Rxc@qX*eDvFHvr5%zYKj)XCD7F+u zv!y7&mZBK86veWoD2^>f@oXsyvZW}*Mo|I*MTrCyl_#L60s%!82`H*WKv87^imDJ$ zRF#0DY6KKjC!nYX0Yxk_afOLqJho0*Wpppr{@JMfC|NYCv!mMZ|lD z86bh6h2x8NztT6)w9OZ6@qX*eDry?( zMJ?D;)RHYlt=K4PO+Zl_0*cxaP}GiqqV@z7bs(UqBLPL72q?OofTGR>6m=n>s4D?Q z-3Tb^PC!u)0*ZPPP}GZnqTU1)We`x5NkCB+0Y%vaS5f15?*;=T@Vfo3V-qRrYDx8p z_gi09(SUg0%ZH_CAm^8&L2M}+%$A}dY$+PbmZD*7DY}9!MZ?)rG=eQfSF%xb6#+#f z2`IXnfTC*%D9RzAXcPfOxdasD5m1y*Kv4k!MTGMKz;k?uKP>TIQ#5+TD;%-vWjNJ`@Bb_XeQ^E zqHEbwG>a`ov)NKKhb=|dv88A(TZ*n{OVJH%DY}u3qIm=q%_pE}0Rcq|2`E}bK+$3X zif$sH=w>epN*mi2q=1xfTD*8D0-NHqOAlJJwiayqXZOfBcSLp0*ba1 zQ1mzfMNbe=w1a@6CkZHeih!c02`GAofTCv!DB4Lt(Q^b8Jx@T<3j|lu`greT10*or ze%J9%DcWNni(ZWPTVGbutMR^-$E0W%=a-`0Y$RyX#$GQ5KwfMfTD8*6rCra=yw8&E)Y=k2LVNY5>RxJfTBwT6#Yd&(cc6V{X;;J z6V#XODDn_cRE~fmF9Agn1Xs~_@!mfTkU#?q=ZF*?w8IzlTVGaDbkJA*gcJohzZAu= zr6`syMR9B?if2nvkS#?awiG3>r6`dtMdjHjsz5+dMFNT{5l~c_fTAh{6jddls2Tx9 z)d?u7K|oPW0*Y!8P*j_Mq9g)}>JU&=mw=+n2q>yYKv8`HiW(45)R2IpMg$Z!Cb)|H zL2nlWByg8~DijrTztVTCq9#GV^<@<`5BhR{m7)~RFGZ2Lg&Z5>V8MfTGI@DC$f=Q5OP=x)M;-jew%=1Qhik zpr|JSMZE|p>PS*!Kv6ycMFj*D6%tT1nt-A)1Qd-WplBQcMdJx5nm|C&L;{K?5l}Rl zfTAe`6ip?dXc_@U(+MalBDjhM2EBU?kigsaPwx+sqWSh4*~LM>^<@>!3i^IIEk(0A zzZA`3OVM>~DVoccqU+gGbOT$8Ze&Z*Jhl|gXG_rnHi{M!P_&4EqQwLh-9$jq%>)!J zA)sg}0Y%FQD7uA!qU8h>-AX{w3Id8&5>T{?fTGm|6x~KZ(Ha7ZZYQAV4g!kS5>T{` zfTHyTSJBL%H}Q;7^sW6y`Eo7hscnJq>4 zv88AWTZ-;yOVI;tDSD7CMGvu2^e_QMTL~z7gn*()2`Jh|K+$6a6m2J<=y3vyo*WIM0Yy&}Q1lD|Mb8pYw3C3M=Ljfzo`9kk2q=1yfTEWOD0-RTD!M!99d3XG zTH42=4N_EOKcl@8^jlw6(Q859?BAv6bi(2M8$olz^ho2q-#8K+)#} z6n#NJ(U$}i9U`FUD*}qXCZOmW0*Ve3Q1mSUMc)xzMZ1FDdkv7lp zekqD)OHq(5MIp8nC9tI^ku62#*-})2EkzaCQdEhJqRIpmRUx3LDgi~+2q>yfKv4|> zifR&2REvP3+5{9O5l~czfTFqt6kSF@Q9S~R>Jw1ZfPkWg1QazQpr|ncMNJ4OYDz#+ zGlHuq5b`!LKms2{8#pl`_bdI{_StoE$ZvgFMQI^l_TN&J&iSRN1zU<*vZbgMTZ&q< zrKk;CirTWJs2y91+Owso0~DoP1?ry3xEzV@*w zRf^8oF(~A>zO15QA>V4pUO=i7aRuj>qTy^Q8o`#LE7?+X6L$s$pjQl zA)sg~0Y%dYD4I?{Q4s+}#RL@1AfRX_!BsRQRjXj8~n)BJT1;m4xQoL`FW zV@uH%wiMmZmZAsPQuH8OiXLK1(Zg&h+RB!qN7yKOlz^gb1Qb0+K+$#riXJDR=m`Rf zb`VhXBmqTF5m59r0Y%RcQ1mPTMLP*7dX9ji=Lsl!fq$VSmV0*XE&py*=)iasHrXg>i(2M8$olz^ho2q-#8K+)#} z6n#NJ(U$}i9U`FUD*}qXCZOmW0*Ve3Q1mSUMc)xnbcBGS?+GY6N^lju9`Y_RKmwQ9 z$D%i+$ZJXc5b|4JR?*KP-_~d;I?nl}=mcAeeql?|uWTv$jV(nd*-~_hEk&o;=lC!pv80Y!fhQ1mAOMHdMux|OHm?QipsO4r~+GxDzc@h5?hKYv!$pCTZ*c(QB;k9qUr<`)gYj# zCILmY2q>yeKv5C_MRf=$s!Kr8Wdsz}BcP~00Ywc6C~8PRQ6mD18WT{|gn*)^1QazR zpeUJuqUHn?r4U?2aS7fEu|`o_`xB7(1otcb3kFX_YJ%VTvWi+J_*%tFQ7g_bMXlLV z)P^lZZP`-Pjx9y)*;3SjEkzyKQq+kpMVGTt)R};yE(8>HC7`Gq0Y%*jDC$8#QBMMj zdJ$06n}DJW0*W#TD9R$BD4T$yJ_Ho?C7`Gu0Y&`@C>lUO(Le%<1`$v+n1G@o1Xodd zg7-=TB;d1OqqUHt8TQ%r&;-BrWfhG`@Ld;@qANMS6kWxZqLFMVx|%IT*RZ81hb={; z*iw|smZChi6y>u~R6sycApu3B2`CyvK+#wNipCL8G@gK>2?P{PB%o*#0Y#GuD4Ie* z(NqG8rV&syoq(bu0*Z(?AVy#x4x{REeSqEkzHprRZU{6m4Zo(IadrdXz0i+t^a{7#l^~2`GA;fTAY|DB3|l(USxe zJw-s#(*zVfLqO591QhKgpy)XQik>H+=mi3bUL>ICB?5|GCZOmQ0*YQGplBBXMY{Xy_w*h zZh!=i*{}59lA=G&>mq(i@LOM2(Ju+UHC3hPSI#d*zpvRfFd6OMUey)`3WeBBA_UmfT92aMKJ^v#S%~yM{pG#Pw+lxfCQ@B$D$KbG~Rwj zi%;}hUsh3KqVMzSQdFMvOHl>36jfwPQ6;t%Rc1?36}A*rWlK>twiH!oOHmCrifR&2 zREvP3+5{9O5l~czfTFqt6kSF@Q9S~R>Jw1ZfPkWg1QazQpr|ncMNJ4OYDz#+GXjc| z2`Fk#Kv4<-MX3Z7r4dk+PH+{461{&LAc1xETSN(o?pOLp4W5V=iGJ(LDr%GHt6fWq z+H!s=YR8tM_G~HYz?PzpY$@u*mZHnqQq-9(MP1lZ)Rm2*ZUhu{C!nYY0YyCtDC$K( zQEvi@G6*QjB%mmZfTC;yiuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP z1QcCCa22&m^!6}70!=NP)>4#XAB%=3`mHakXk?j&H1J18nzVWu%&1e zTZ(eoQk2J*qI|X#6|kkKkS#@{*(e%AK+#wNipCL8G@gK>2?P{PB%o*#0Y#GuD4Ie* z(NqG8rV&syoq(bu0*Z zDO$#sqFdM~T24UGtppUUAfRX^0Y$3_C|XTG(QO12ts$W3b^?m-AfRY10Y&QwC|XZI z(VYYo-9plBljMVkmH+Dvd2-I(azXMhBLFf(GF6#Zt$eTjbS z%ZYc&MO+qLy@AIGK4gBr<^jB}g{!8?MEQziIi zg5%T()~Vn)Nx?Cd9H(CJu_}(!D0rrt<1`DltLZqY!5eEkPRrn)I*!ve7*o%2ItB+e zaGWl|b&VXSNARmAj*}6*EZK4T1jnT~&Vb%x3=ei_?KmTY^V>SksNh@e z9j71|*U53l1_yU`oQc6ZyE@L);5XeJr#M)@m*dO|PRMYaxxpP-jx#U#dmqPH6ztUB zah3!Z4s@L5!FL8b&Z=N=nB&|Y96H=_)(7vt(s4Efza8l~n}Q8<9OwSvq+G{&IQUe) z<7^B5QRp~N1Urv)oTr0}$2-n*!S^OQ&P&0BDUP!%c*Qiwc_VmFk>k7_JTk*^_68f9 ze-dL~aLOFV*&lpnuHzgGUcA9^4h6f;cbvn)n-@CH_rdoUJI;^6@=F}&L~z71$2l3? zxZH8h29K_AoD0FGs~zW3XxbWc`+Gt=?=W|OC-m1ka}Rhz-S0AYfhV+dgSihpp%3ph zcY-HWakIG>JfW+$n7hFf+WdgIA3P!Zui4l0gzP^@-pCWO|DJR+Pssj*z^R^){TE$Z zdP4S}_5#g+!L~YxBf^^$o}Q%qdXz|w_6u@LiVpG9_tC&zh8EuCuIME(5aq~{Tm*OJt6y7 z^v&{w?BB6A*AudTN!C11$o?%yi#(y151V_)6S9BL$Z}7}{zVb1JR$pk`rqye+5c60 zy(eV2YWps`-9_so{;^?-+oWX{^;hQCuG0( ze#jHD-#k6+3EA&{eeVg`Z(scA3E8hdPk2K13y71RkbMSt))TUy!Y_D2_A&U9$4NM2 zK4>EDcR%D3dwa~C*}@caOPJrD4G9fBPWh(hqs!Bx=1Nn-uQJC9H<%v@cv{8V=2S2m z9ZzeGO7=BvG=A}#(Kdcz_+(qm$E2s7UbEI*l&8JMPJ5mX8n4*VQDdmRMx8Wr?4@0< z@j}3i&KjfbHR$4wisl2?u~*z~CLvZ@}>+cHm0q4$D=C$>r~O^RAnwTpy_kpNQ^GhOnZ^By2$WrOD{4`7pYUl zn=|=JuSYP>Ts!-gL*W;E<_6GvqBoM*+|#)#SE6Cn1W#gQmn!SJRkd%iysymFD_41E zH*=d*Xj!J!Fc(~L=>m_r?b6EIb5vTkz~hvwvbtLp$EnOK%q`vA>0GsA)yeVUH)P(j zl~D34$-Lxo2G~Ph_{E|2VCh9TXFLNonis;qYMB3;d&~SX6!puVs_d__`&t9V>lB!? zl=EDSk8?ccmpQGq)Vz7h^xTxuMN?CXrstXi>KI- zUsy0>dSOwS*V)sXQ@2Z*I(^)vamC|i7CI?or%WnL$(>j@E2a6wDfzh*Q;NpsPA^QE zUO2h1D7Pr3Fg>TJct*jvDJjKMrcBHqn>%iDQOcP7{G8nBlTy-Bb6Vu2r>3Xnq@~)J zY+~}{DU%D63v=_vC8wn}Z;@R$3<>$W;&%eJ(xoH@0n z`?{Xpb(%DD;&FYZOqrVI^zAx4r+dF4>F#Cs;4H05-d-D0i_*87Uh;Okm$^t?!F0~h zy5v;t!q;iW0gWqKqm{QwEye_i#~+LXM5 z<_;^l<|Xe$OWubbr8l;@iFHDAlel-2xfJ&Wy^B^z8_sI(obW5n9jEiPD!DN8&hkdn zb@~>i*Q0yMInuiGrpy)BIjpcU57Yl!4^BM_^Ja{3%p>~bF@-sWlMBY>PR^M)W%3yJ z9W-~jdGqEWu*`j~tJbpg+8ST($xGfnAg7kTckN2vlQi=&;$-(6k<+!upz!$&9lew0 zLqsq2_}4iddzF&H|M@SB(@L*MH%SGwxf{c80Kp|j-H!-Mqi6Wstx^f_bzF zzmc?3S!srr+fsRDDYmp;+%2WXxTnlJ;GT~c>|GN6NGZKr&4Zt=N}9PYyqH#cYm~Wj z+vx1v0j?W+fo)4~Dsw}+ZzG*IR(i*$mEQAdW$t=&@3?0vy_2~Q(z@w=xA%a3OYKUo zuep77bxR)uTj-Knm0lnBt`EQ0rT2DPnY+8p-Q3!oz0@F&plN8aueKLtjwLq~Z%|jy zJhtdnElO@eb3<_Q(mS5}l)JR#Zft8VX-Wyy())zZFZNMG7iZ4H1sj3xO=#Y1_yu!I z@Vb(#WZsr(_K|vsc@Ck|b4GK2gp0kC!=JX?&sIH4&TZ}iU1I4q;666D5O2*~PrX=j zx0-vyePg9e%tMDcRru|MUuEuQoy&Y;(Mu)olOgDy-#m8O2eIky4V2~{^jWnOhJBRQ zMU-GH1z|p6n^zW%oie?+Z?hzXy>-aTPV=7w=!D5IhD-cKvN z`_oGAf9{+#b7jM4HlOapM{fKyL)pF5GWTuiU1{F9-mx_E1jRj}`B2phCGT~bdq;;q zTuNh_&SCE0(i_;k)Vtr%r0(t7CD~{2&C`o=VPb{1~ zrg&_pRFm9iGs*T|H_Lv)FCI5#a&nP*GH#AVrWNEC=ay{urZAte-4{yrrj_!w9RH_J zGA_$9p9o9r8N1=jEPZBZHQL*_^a*0=)50_tcvy;gVAjD|41`=mzp1E=fsNl85? z~CSTLfL>LklAo zc^8*k;c>dQGa=W0we5IP%!|IZ$$gvm?V8!oiA?bKjrInj5+f>jDtan=t9Ytm1aVjZNKeN!R&&P zR{Cuao4h68mvc|xb$jWtP4Ce_tD~W4_^2 z=9kw=EVJzCD>~*IM&b9`-sXws`qwXWijaNzKffZcSM1a)a0dPB>mEbUXuo4-cTXL!GVg=kV|3hP?kc+<)A0v$1K52=$7TkO-R*RoZhrJ(_l-I}XFfpe z-lOB+)!ZFZ-97d&KNzvEAE@K9+U{Pb<34l4+Sh-jW2JiTzD&oF4ct9W$NS73U{C+J zjz2bW_cYDVvZtS~;|po-eoIHErMu&F>}Bpyd-}mTE^q7ZJ9YfHy}Q5B zv5L9l?dj|5cui+_PtfuHuI}EU+S zzq^O(xMHBY@78huV0VA3W3^%KZm8p^;qIQKNE$%MTaoYp#eqP7Z54rmv9os(Q?w&f{u+81K==jEV zcYmZ~V28Ua>p0*kcVDgJ+GpIoMaM%s-Tjk}bzg9IijHGna`y}!x4+`<7j-#r?ypW)AJFmZeeOQ4W4%w@ou=dX z1Ma?7$0t5>_scq-H$OMD_mB4r_t^1}d(6~v!Po9yspH#+-F-mE_#^JFuH%rS?#|Wm zu4C?gNXNrJx%(F#8=P==3mqr^>h9S(K6%pJuj+Wg{Aki%U*8$`c=m>+}MV_zL_GCvQsdyS5J%@0QH{#?gI^Al3LYwI}N z{HWCKLLKilKQp!aQ60ZGKRmVjl#WfzPf_h|qvO;hcVDmLv*zcj_VuspSi}4&1-l#T zm}-wc$LXw{Wsd>J>8Imh^-(%b(s7QCH|u!2j+=GduH%b3zOCZ{9lz7@H+wX1znuBu zs68gyqq%;Sbd0pmTTC}sDSS-Ov7(MObWGAQeEKN!Q$}rb2%pb9y$K(S?DHOTdFJVd zQ!Z$JAgJy%FPc56I5*E6i>JHCvAkryDlT@K+b=_%=6OX$PIL2xb8{P;|NH4-xEI*( z#F}rfkDg-A5`H;1FK>F`O!r)FF+ZCtJ9DSorAdc=PkH|J%f8P3YG{6&yW;R$T|9rc}rt!<(clK8^^V>WPb-I|}_E&KSPxyYW zWL~zXvA^xx%P_yW4(3JYVe`AT@x(7)>S03J%UfhFZ-5E*@~k5+Z-{xB^OzT%x6EZt zEfaXrJSF+p>Dn~*IO+Bb`o-z;%r5(O_xJEP_BOC@*LL3S4D&MQF)upf%;hE77xatQ zO*6afi>1R z%yu3p%QSv*x>roFFZ1hmb2@8?U-td5zs#rpf4#rW%Dlhj&Fgr7-!m_pcW*iBZ%#Rpaw@poNo8BtPe2XGAt;~O0w{Dq~)UHLVcIip>*QmgaJ^S=> z|5So|!5;IKDVJ-@6XU|m=YFg=a;lm~&g|2>rpDGy{^>&h?&n{bac6el)3b|Tzi`6I zIPFg}$E0m_@5nI60qgTNo!b>MFLha;x7w7$PSsIgkG<1v1N)uc=Uvq2qujxH`Qu+d(`D%0<^J41uVMeQRVvNPo}aZPZ+`ZI%r`Ea zNZoR3XwjB)*R*)!!r`e~&dn^kKI4bne}4b_pZ;g(d5`42abe%UBja+)Ij6cU%07K~ zZjFZ7r#H3{d4u!1kH6QHF6WzhduDbwr@qImLD}8Hr`=#)?s|T6 z`OcYx&1=@1)yrI;4&m3?YuEp5mr)sgGP2ub-kvug-=4-^%l>DbydK%<8Cm(+=F;t3 z?|pt>_vTsMdFy61316ap%jQ<^-Y|TL_AT4%(K_=oT{HXkQ?hG^ua|x6_PW$4dF%GJ zsS>^%_pPoNTrvDQ`xcYxbveDXqB(u2UUsd_HF@#bSLaFCIHgoiJ zJoS;eBu`}42wlI_r1F`SvsdSNG6&>0JM6sbgesX2rH$qT!ZYuq?ZZyg{?cjNtoNYQ zKF4-;d8+N)s^?Dq@nV~gS3djGW#fLn?ncj{TYKG-w8H<`o3E^?_T-ML=Fk5*H#_@I zIP>*;~z7iTQUTxIS%_x858!wn_xdDru+%U{=buo1JdoKZaNPjmSZm1k$q$(oaSUB+)E zQjh2Exv($y__%9~)NdBp%b1ikL2sk~*~3NS%iOXD^CxAD)^)JAZehmw>^xlq>#6JM z)#a}VUjzI86l51>6=sgkuoCU%UXeA}T&}%$?d1+B^S&L-zanG6zuvd`<@;r3_q8r3 z*pIu*2OriHJ6r||XX?X>^b+v$|iy3E^YmC-&s zz056WuYdEBTd-qxr>stymzP}shJ7cLy){qHi|v25fxk_5n=JG3mf9w>P4=D(hj+F4 zA8y-^=l3FvzZZ=V1#im+WS4OR~Ba6Z|&_~?Lr z|I@}kYR=DGknyH@gt8X8oc8D6m^G*Gn->lz6^)uOcDQrtz<~>n$G*w8Z{JzcnUf@4JtM{G@^)|VWqTS9Po_bX;bJbCrG6PO|?!?0lR1U9Nq6F8ev6 zLFCZvq4qSXL(S)i!&8T35B+aHEA%{IKL*-m<(qrbeymt|t-?~RTl==s!v^dlU;nc; z@{==~%W3%W&z!nR`1SUYpockigYbFn$7K8L_E{Y=JA|*f`7Ajjwx0P6ncDk&&8{_# zRQoy6el|3}9rHW%MefT#URar)ou1Vqvqktk-yb`&!#s9WPc*mO_w&r}P3HHi$M*M82Zl@Y6JV(r;$64fW$D7Tkro@KSFoLxDqN@f-NtVPdQ zR=vpQ#+%LOH2ZmNqqD1~Gq2yl2JJfTENn6_b6cyL@pXSMe&gQni#I&KV{MOx^=j4l z>*UN;2h&HEYq#j)@m^iO-CH!uem>m4Y0a#ce2@NfX68@*>Q~&Ic#rwtu-xa$5uRq| zNo#CP^VLyS*=M*0Q8`cKE%s*uo~Vb+*XrfU`RxBkTCSXbor&H`=E-BZzE#Zkn9ZN~ z^V$E~-TRC^RsX7^!pUF9t|;FTpFQ|{m}k2Y5kC7qMkz zRyMPp6OpP}$;>o!wbHaJ+HI~^x^@M-%@u2*UEXeU&01E{ zjgV`!5t5^gkWtzQ$<;Xzw1_NM$Sm`S6*19ouY)uK7qlu8~v=K5_8zI+gBjg5cgxsi&ka^k&nXiqI1=^8KrunQG7P3}nm5_Cs60%-XLhjU*kh?S`y%J#F& zvwkbb3VFfT**vI(g}kVzWesh9*Mx zXd~oJZG^m~jgYss5%P{ULf+Lz$a~rd*{h9^_q7r7fi^-u)JDiYZG?QJjgXJE5%P&P zLiTGTEc(MHIx+6ehg8zCpP5pqf!A*Zzwaz+~=XSES>P8%WTwGr~WHbO3FBjgWlg#4+E zkc-*~xulJdzqAqZw>Col(RPJ=Y zOXBTUGd_>bUE6H)v^SDn%WU(s+|RCQws~3}#jattd0HOLu5Pw@S{`6mGuu2Zk6~9e z+dM6gWmhrVJS~r7S2o)`EstkcGTVM#6C_l$!Cb=-p@I$ODkc!h+hDF^A|cTRb0y0Y z5^ONnvH~GwgSna&2|*jo^{hmQx4~S|%7i!@%r&h-h&91}g;SLfV}rS-)d&F_%r&h} zh_=C8(;9>*8_YGWN$}fXu4yeoqz&ep)+YFDFxNDR5MhJ4rgaEj8_YGWODJc8{aWWT zg2x7PP3sX1kYGeaIgj^U10?oc`}D-?aTO)nXS4M^e#^@$YV7eHH$PAcD{8{|rKl-e zikh*dD48uq&Dm0v!j_^`wiKnYr6`>(MJ?DUYDqv*D*}pI6HwHKfTFep6#XCK{xdqt zvXB3@XEK=#kRdRG3WyDRquWJMLF@&vprVL?fYPK1ioK!O5DO}H?7f1$_uji=@4feZ zotfXU_x)ebdfx4|wrg?Ud_TzvAvw5`D~$~WiZ&7`+E}2dw?NS*0!5n&6!j4(+DxEm zbAh5Q1d93!6!jA*+ESpXzd+Ge0!3R36m28a6s?vow9P(BS-vH~Sv?eel1OcvFC||| z(T@3Ik0nCUPR@s-o$XLGzz#(N?NBtx4n@1zp=eh-6zyh*qTTIKG}xwS4}qdR1&a0( zC>kPAw6{RfJ_1EU1&a0+C>kbEw4XrHaDk!`0!1SQiuM;M8YNIPTA*l*K+ypLMF$EL zjTI;wCr~tAs43b$U)U`JQob#l^*e;3T@$GZ`BL(g6iv<-56(Ubp!r%f#raS))ec3| z>`-*D9g3#gp=gF3iVm?u(V=!InrVlk!)%HU7brSHpy)_}qN4s zkaF+rPP=|mD0-^-J}X~JzLKJO`Qp9Vr*SnaI@kG7beXpvA;bauY*VFsi;CcQy@PAEDxDY`RX zO1_e!d-KIY_6cy!itckh6y0x!q6h3y^q?Jz9NzsS-;x^e=rZg-1 z$oWw8u^oy&u|v_Pb}0JH4n?2aq38=c6n$xjqOa^w^tDaVHv&c93KV@OQ1rb((GLPe zKMEB6BvACTK+!J(MZXFZ{U%WKyFk$&0!4oc6#XSo^tV9KKLSPn3Kab(P?W3tzwh#E z_h@;6qB^0bXmP$UJ_Ay2{+Dw<2t|c-VJg&>lCPwwR98H0`B2ot`B2o-4n?i(P}FFL zqOu)|THB$h$qq$r>`>I!4n-B4qN+eqJAtAl1d5gvC|XLOsJ%c@2Z5rF0!2#;6m=3P zT1KE~S%ISE1d5gyC|W_FsIx%PiULI|2^6g?P_&BRTC}P_(P~0XQL(OYTLz@OAiYDe zp{{nP|8M#T#p-pX(Kvyk@d8B? z1d1jK6dfeg6zx=3*enB5o|~>kJBOlU(_7b*>PpF1QZ%iuIBeBWbg=WGXu2JWX4s+V z5IYndYKNkkb|^Z`4n>FCq38%Z6dh?(bd*5R(E>%s2oxPFP;{I?(eVOBCkPbH5-2)R zpy(ulqS*pPCkqsvB2aXyK+$OeMW+iC%@HU%L!fA`K+%~3MP~^Voh{T9O{ps!p8+Xn zpKF+_pBjo@O4p)u>PpF1QgnV@@ygXh(R}Aa(FJxWy3h_q7ulicVmlOFVuzwj?ND@? z9f}s%q3Cj(qALW7t`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-3 z6)3t*py+miqB{hN777$C5-7S;py)1vqPvBfqI2sC&tyQ#SL8D|=Y^s}(zWQGx>E9$ z6g^N^{ASHi^q}*h=pj24J#2@fN9<7as2z$PvqRD2b|`wn4nXiWUnsMfcSes%vG6u1R8PpF1QuIk(u~(N+^r`cq=rcPM zeQt-MFYHkCr5%dCvP03=b}0JB4n^PEq3AoCqVENYeh?`7QK0B2fuf%UihdC&`cN=r4hyzXgi^5h(gspy)q=qUI8}k z0!8%#MMa^e=%c#A;0#E4TDlf}9Euv!YqW+!Dfvo@S`~^jx`m=f=R;B14n?i)P}F3H zqBeFYYHNq0iXDoob|`9RhoU8Hik1{8T1ud(y+Bb1fufEAMN115brL9AMxba}fuiLE zik25BT0x+wvp~^`0!1qc6s;^!w2DB{sscr;2^6g^P_%|X(V9X{QHw(1!VF0H@bu|I zEeo|f{h!mdXstpi`AUkq6^i%w2u0nU4@EufP}I{7MZN4$w2mE$*0n>?dUhyU-ws6^ z*r8}co1%>biZ&J~>Mc;Ti9pe&0!4iUiZ&A{+FYP$3xT4(0!94Mu~Vl|a$f z0!7;h6m2U|w4FfF_5wva2o&uoP_&a!Q`DtU_&5VnzAU{d)HM`k-)=vZcY;$yZV|qfp##y-;+B^P%WaI~2{d zL(yS&C_3B@MMv17=tw&h9c722qwP?1j7`z80!7CO6df;6bb>(9EPMbkskm_+KlLMi!5iY_b^=Vadsq4`>Lk@KPGVmlOFVuzwj?ND@?9f}s%q3Ciu z6kTD5qATrCbd^of)dEG=2ozl_P;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+ z0!4QS6fG1eS|m_(r$EtN0!4QV6x}0Gbgw|seL_vq{6gW53`qIUbosd;6xAhC_ZLdZ zS5owFq4;|C4LX_?J>q;Qdeja@kJ+KAW&2i zC~6_p6n$DKY>@#eZ;@{9KMO^3(p%Rp>r2U3Qq;P>IJ{3NYH~glwXs7{TRRk0>`+v- zLs2_B6fI$gq9yH6w3Ho++S?R$5Gd*>P_(o_Q73_-Wdw?r6)0LxplEr4q7?*+Itvu7 zC{VPLK+(zqMXLxDttwEonn2O&0!3>G6s;*xw3a~8+5$yggqotp`ogRXNO@wq7M1I3 zclu|fS8rYGOUYMK)U&>L_2!|dm-C@$9Xk}QYlous>`=769f~%vL(ztIDB8#lMH}0p zsJBhgCIUs93KaDbDB4V*Xmf$0Ed+}C3KaDdDB4n>sJ}qbRsuy^3lwc5P_(T;(RKnw z+Y1!!AW*cUK+#SDMLP==4G<_ADAW{nuP;280VyAo&H5gp=*M&|8dP6OzLKKd>x(Kvyk@d8B?1d1jK6dfc`G)bUnvOv)kfugAbMbiX| z4i;*PcC9Zg(JxcfK79maw@@@IU5lpImy)lfXlC}EJo<;C!<-LAhufj(2s;!VX@{bt z>`-*H9g2>zL(#EzC_2s#MaSC|ogh#&OQ7gPfufTHie?KGoh(pvia^n+0!60@6rCC+nz z4MiQYFL%;o=NP`TO({kc&gn3F$T3L-nQPD=B)c zzWCs_q3ChvL(vmB~bLXK+!t_Mehm}y(dugzCh7pfuautiar!5`bePY zV}YVi1d2WtYKk7IFMOH-DUVFA#2yVrPo_Kl&+1FbS5ov`b#WQU@k?NIcKP0_CcMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N% zzXC=72^8guaobK&UZAK>pr{~FR4-6e6ewyCC@KjQwGb$3DNxi(pr}!(Df*(muyzKd ze0O?{_GKtqF}+4B7fZ=kQq;Cs++n9sRB=8ORqasJ&JIOO*r8}iI}|Nthobg&DC%H` zqKp35a*0)2^26iag&<;f#*`a7-I~4V{L(wL7DB9ExMSX0FHWMh?T%c$R zfug;69tM65-6G^P&8SfXo^75RDq&t0!0T46ipW>njuhhh)`2BxLEi%15$oD zy(zRuC^|e{iw-T8lCPxbh+=X1-9pik&WEC->`-*H9g2>zL(#EzC_2s#MaSEr=ma|y z&9Xz$i8e(i2^7s1C^}i7=oEpXQw54n6DT@eplFUj(HR0oa|Mdd6ev1Npy+IYqH_d_ z<_Q#?D^PTvK+*XEMe_xUE)XcXP@w1{p{D4tVxeCKq&z;|mK`37is|j5i;Jb?D=At~ zERGx;iY|9P6kTD5qATrCbd?>7uC_zbHFhYv)(%D2*`erqI~3huQ*@(1(M#ua8d@OJSV-^@v>0#c=oXRM~kK8D=B)iSiE-6Q1q1Zq3CHl6g^{y zqG#<;^qd`vp0`8M3w9`a(GEo~*`erVo1#|)ie42cdQG6{b%CNc1d84iD0)kv=xu?b zcLa*w6)1X7py+*pqQwG59|#nEC{Xl~K+(qnMV|;1eJW7&nLyF!0!3d4HARmX3om3q z%Gp1_m8*Xu6tzmP(Y`E}lCPxb+hXyDA))9y=R?u=b}0J64n;rOq39<&6#Z<6qF?M# z^s60;ezQZ-?>0q$2o(J(Q1q8T(cc0^{|FTQD^T>GKvAwCZrdr!3l!A}6cq%D>II65 z0!0l1MJ0iv76L^r1&Ue;6g3JIl?94g3lud8HAP<+3rp>tDM}xAt^XzzRnlA6Z5m3+ zS5nljp}79gP_%^ep=e1v6fI?kqV{$u>R^YWj&>+o+73mX>`=6f9g3EP4%ps1%nQ7@sUsM1gvk^w2do!+{xHq`F)`=;Cebs9>^S5mY=L-DX-p=d+rL(xWd zDB9Q#MZN7%w22*xHnl@hA3GFnW{0B9?NGFZO;KNgqJ9EJTM88Q7bx0FplEA>qHP3< zwiPJaPM~OefubD*igpwz+DV{jXMv&t0!0G_iUtW3?IKXLt3c6i0!6zE6b%+?iq>l= zT$%wXpPSw;T0ay$mp&Y_M?)$3N{aSwC_X$q6z$`DC>m;qqJ8a9G|Ub~``MvrxE+c{ z*r8~o9g6n1L(wRkqR|3HV+4v05GXoOplGZ>(Kvyk@d8B?1d1jK6dfc`G)bUnvOv)k zfugAbMbiX|4i+eyE>JW>py&{RqC*9WW(pJ?Ce#$|)lm3615$o6eSXo9P;_&8NA}?j zrQ|CqI=Z3Qa{o|tjPs%BSUVIQXNRKW?ND@r9g1ezq3A?A6rE&;qSGg`AUkeY$)zDIuu>yd?>ow z4n^14q3BvW6kTVBqU-HYbb}p=ZnQ(uO?D`{*{0|gfudUlif$7qx?P~?4uPVD0!51i zitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^96exN~py*+NqDKUZ9u+8hOrYp-p{D5a zhQgE#NV!XTgZhe4bY;30J<(7~zLKJ68j5Ef5Q?64J`_D?hoa~0Q1pTwie9us(MxtH zdf5&|uh^mJRXY^DW>fUKK+zilMQ;iey(Liewm{K40!8l%6ul=<^u9pRVu7L$1d2Ws zDEdgC=wpGRPXvlS6)5^lpy+dfqAvuBz7#0>N}%X#p{D4mhQeJLkn->8HQLjmXp?l? z|4l8o=K+40?o&J)g+MRxnbf>?5sg!&rMH`ojqYes1y`2w5o7kafQ#%y(u|v^j zb|~814nbvO`vFZfug|zMSBPo?I}>Smrzr*VX1I(2BiF6HtRPE zMK`Bw(U4Lp`AUlREfuey9EyfHABy&~L(yMMnq}9Vyfl?NchelmRLCOSff1L($Om>g}jfDfvo@jw=;^ni`6Z zcRm!IV27evb|^a04n-%~p=h=picYpe(J6K)I@JzEr`Z&pE>JW_py&*NqPYS^X9^UZ zB~Wy>K+!n@Me_uT&J`#+PoU_0fui{WMHdJZT_{j=kwDSK0!5by6kRG%beTZW0)e8- zg_@#cN`(&7GDVkUv;Npn^mckv`-)O2`AUkeDHS)I9*VAYJ``PNhobB4P;`SGif*(+ z(M@(Jy4emzx7eZRRy!2kW>a*#K+zonMGFOr76}yHDNuBmK+)X-MfV64-78RZpFq+5 z0!0r96g?`koLO6oRiLPwKv8#rq8kAZZAW*cSP*c>tMWK5Jq&zKs z1f)ZY+MWKc={4F$ElSB(QnYD{;(((m{tqA_+TI=~J^2il=%tR0HR*%XZzD4HNpG*O`F zAc3Mu0!5Prilzt@O%*7bCQx*+K+$x8q8S23hX@oMDo`|2py)7xqQeD>ju0q1QlRK4 zfuf@YijEO#iiWi)+>-$*ua@2v+AkDsmq;DkqLh3kMYCEI-#soAo#=chI>`=2v+YoH zvK@*}u|v_Rb|^Z{4n?Qip=gdBiq5bpnk!Irra;kI0!3#F6rCebG*6)DT!EtV1d7fV zD4H)&bb&z8g#twv2^3u{P;`kv(WL@KmkAUt5GcA_py&#LqALZ8t`cgBj&D(@J3dqN zNIrveLMYlIk-EA?Dfvo@u5VFXX;vt@!TC^hqaBKFvP03$b||{V4n?=xq3AX{6y0uz zqC4zRw9uw#kwDR%0!4QT6x}UQbdNyMy#ht|2^8HgQ1pO6(Srg-4+#`KEKu}_K+&TD zMUM#-JuXo6gh0`g0!2>=6g@3a^o&5!vqDYLwJi!;XF$q3X0!gfP_$ZljrLrNQu37) zz0{&O=A=;cvh$(n6+0BYYKNlN>`?T&9g5ztL(!XdD0<5dMQ_`o=pCD)cLj>x6DWFL zplGo`(FX!W9|{zGBvACRK+z`xMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&c93KV@O zQ1rb((GLPeKMFNPFSIC}ngPi^aF)S&F%&(W-jV%Ni&FBH6#dqsc;m^T=y&Hs(I0jw z`qK_Yf7zkvZ#xwIV~3)D?NIce9g1=-i=7JoT46fNs~C|b@AMa$cvXazeIb+$v%igqYk$qq#; z+o5O`I~1*IQ?!~u(dq(4YX}srDNwYQK+)O)MO_4nx(XC^6DaB~P}D=9sHZ?tFM*KuQDB3}w zXh(sfodk+@7AP7ZP&81WXplhBE&@fn3KZ=oP_(;1(O`k1Jp_vO6e!wDplFCd(cS_@ z`v?>b6)4(QplFy-Q`DzrVc!f$d3?J3Y!-?(Xue@n2vq6u~=nrKsWkU-HSfuhL*MNLQT<#mW3-a zAmty@dmTrHqF(8fjZSD;O1_e!*)5BYpB0Kuc0LrHVuzwr?ND@@9g0r3L(v>N6rEv* zqPcb`I@1nCXW0~;El_lhK+!ybqH_g`&J!p)U!Z8dK+y#PMHdPbT_jL+u|Ux!0!5b! z6kR4zv_PQfa)F{N1d6T{D7s3Z=xTwYYXpj}6>5r3Y+3j^15(~HoAoD!qOH#0!8-- z6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2oj|db!Dp2&8K+)p@MNbG6JtO1_e!S6dbbofnE;b3PQk zZik{b>`?Tk9g5zvL($uID0;^ZMeo|7=si0Wy>C;rSfJ>n z1&TfsDEeHW=nH|OF9nLe5-9pwpy(TcqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7on!; z<(7r%8Ibar1m~4d^k@3e?5{0L$yZYJXUpQb^Fz^J&WEDE?NIcO9g6<7L(zYBD9W{p zJNHnOw?k2#9f}HeD5|$9Dhd=e2o#kBidqO1wG=37B~a8TP*fHuYAsOIBv8~wps1}t zQAMDrDp1r;plAt!q9p~2mJ%pxFHqD$ps1rj(b7Uq(eEt__hmrJ<#b#2M=07ey^++Z zRVn#Oik5FxeE-5ww1V@YsIwi4RkJ8G*F;ukU-Hc z0!6zD6zwKZw7WpjV1c4N1d8?)DB4S)Xox`3-U3DY2owz!DB4$`XqZ6JegZ|q1&T%p zHAP#rDr}npDW~sLRNprgU7g0rR;A=CDH_wNc;IEB=m6(K(Sdd-8f%B5ads#gZ-=4@ zb|{)?hoXb*P&CO7MU!ocrU(>G6)2h}P;{_B(R6{L83ILz2oxPEP&8AZ=rDnz!v%_t z5GXoQpy()pqN4?hju9w2R-ouOfuiFDicSzHnk7(lqEJ&bs#W3i3`qIYbom(_iattj zB%Rc%lzb&cr?x8Ie0eB3&G}Gtx*dw<*rDhQI~2{eL(!RbC_2jyMQ7Wg=o~u~&9f;w zSD@%Tfui#TislOxT_8|&p+M0^0!0@K6kQ@vbg4kmWdcPD1d1*fD7r$R=t_a2s|1R! z7AU$#py*nGqU!{Tt`{h}L8vJ@xmDq{3`luYdPn0ap=gD4r+;IsQu37)-P)@7+m)f{ zHs?dp?RF@-!wy9Y?NGGH4n=p`q3A9<6y0ryqI>L6bgxa(eF8=I3lu#dQ1qZc(L(}7 z4+|7MB2e_GK+$6YMUM*?6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkF zFAFtAH@7M*b5*9OZTjr}TSCz%iPS5tO37DJ^hT@VCf9_bH=PefZ`q;fZ95dbV~3)5 z?NIcd9g5z!L(yV86n$Waq7Q9~J`yPUSfJ<=fuc_Ziarx4`dpys3xT391&Y2BDEeBU z=o^8eZv~3J6Day#py&sIq8|l{eiA79S)k|_fudgpihdI)`dz3gdaYGqzYIuuwRBtd zdMKKeUcLR%s+4>sMgO!a9&=qN`q%kT^q(Dya*c849*XjID5|qVQNa#H^>!#K+M%ey z4n-xKq80*0Ed`2N2^2L76qN;vS_>342^6&vC~7NER1qku3KX>yC|W|GXi0&hr38xF z3lwz_DC#Isw6s7`CxN161d5gwYKs19Rk$hxQvM>n68k$8ot-_be!0d{@|6^=*jRk> zhETMU^Py;EI~1*AhoV*OP_&vIidMHn(HeFrTGI|iYuTY_ZJVMl0!3W~in<9Dbr&e= zAyCv)ps1HX(K-S}>k1UDCs4G$K+y&QMH>nfZ6r{%u|QF8fucLXCJnLyFz z0!3R0HAO2l7QW4Zls`)!jqTi6yVHLnU5olQmXfceXsgCzo0~(?*3O5bZR}9AtsRQC zvqRDLb|~7x4n;fKp=c*N6zyz>q5(EV0|kl(2^8%jP_(N+(QX1oy9*Qz7AV?7plDBl zqP+x)h6ohxEl{+NK+#ZvqJ0I5h6xnyCr~t8plF0Z(MW-!{RN6f2{lDqHWt>&fRxuv z9|7qfie_gIs~_E1O1_e!v5m!DZw*D`oDW6g?NBtq4n-5~P;`(TiYD2iXtEuOrr4oq zsvU}^*%TctP&8ejXof)1Ap%8*3KY#0C^}4_=x~9eBLs?$6ev1Mpy+6UqGJS#juj|6 zPN3*`fua)xie?EEohVRrl0eaHfufUznxX?53x{Mt%Cpjk@ed3|$EQ2}QyNRjS5h>m zv3UONq38_fL(yD26rE{@qO`-*RP0@UTq6-9yE)*!b zNTBFqfuc(UiY^r>x=f&Gfk4sa0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mFHwYBn zC{T2hK+(-YP0?wMg$FVq=+N&kjZR+o9+Io1zB=iXIXudRU<75rLvd1&SUMD0*C==m~+M zCk2Y05-56Fpy(NaqGtt)o)ai~UZCg&fua`$ie3^ZdRd_86@j8x1&Ur1YKm@aEHo_2 z6m6B@+#ZT1VmlOlV27d)?NIcQ z9g04-L(wNTMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&c93KV@OQ1rb((GLPeKMEB6 zBvACTK+!J(MZXFZ{U%WKyFk$&0!4oc6#XUC6usG4*ggYNZduOYycLQjB~pJkmXfce zC|53yyC)Ro%W)?kit6l8RIo!)y&Z~*b|`AFLs7{NMJ?=5)Y1+`t!#=K1&Yc7MXd#j zngoj42o$vyD5?k)RRxOL2^1|MP_(2#(NY3M?FEWD2o!Y`C|X*esFOg^G6F@*3KT6T zP_(>2(F#IM(Z7v_Gcq9Ma=J(RFBJ969#-GETuQ!@qE*VpTki`+t2!TwRUJnv z!wyAj+M#GII~1*LhoUZaDC%m5qHZ=t-35wz2o&`cDC#9pw2na0x&lS(2^6g_P_%(S z(S`y=8wnI`EKt;2plB0;qD=*g`Un(lCQ!7wK+zTgMSTT|`Uw`w0{c z7bqGbP&87YXn%pCQ36Gy1&YQ96dfSc6m4BDEcalhsF>dCxJ@XUo;|Goz;Y@1N{S|w zi+vsrMH8J5MF-iTXp$X@CflKCiXDok+M#Hg9f}UNL(z0Q6wRGOVhN82a4@GC&q39et6wR|k z(YbagI?oP8=i8xZz8#7#utU*>HboZ+6kRM(bcsOGr2<8l2^1|5D7svr=n8?ND+P+K z5-7S_py(QbqH6_;t`jJ_UZCg(fub7)if$4px>=y;7J;H$1&VGHYKqP%7p}>Gl#fa8 zb(|ZD8k%p|%BAEhDY~;MO`zy?fuc7Airy4ziWZg&-)BI|+o#LVqENJ4_OSZ5%BAEhDSEG5 ztUMKp-giC}Ew)3^2X-j>&<;f(*`erTI~09lhoVpIQ1qD{iaxg~`a+=SOM#-V1d6^E zDEdaA=v#rJ?*xjz7byBcpy)?|qMrnceikVDMWE*0!2#*6fG%Gw3I+m zdx4@30!1AKik22A>LgIKj6l({0!7OS6fG}Mw1PlUXMv&>1&US@YKro$3o|ny<#!XD zy4JOOw07CU>Q`=EO1_e!)ms-YcrFyJ;e1?+*0e*>T6QQ}+YUut>`>Iz4n^JUP}JQH zMLq0L)YGP@mq5`v0!8Zz6s;#vw7x*m1_DJJ3KVT5P_(f?QE!2wO$3TI6)5T>P_&sq z(dGh0TL={O6)5T_P_(5$QGbD=tptj;7HW!CZC!XM15#ci!C5U7t(IQBZPU7xd?iIY zv@U-1LMYnN`B1cz9g23gL(u>`6b-aP(I7h%?P7kwLG)AE40D+m?d^;4)w?okdb||{g4n-H) zq3B{e6kTFdbg4kmWdcPD1d1*fD7r$R=t_a2s|1R!7AU$#py*nGqU!{Tt`{h}L7?bH zfufrPif$Gtx<#PqR)M111d47KD7r(SXrWM3bXM!anHiAs;`Cm}vqRBO>9&7S>r(QS z6y4Lhc>C+2=w9bT(S3F(y59~(57?pTK|2&ZWQU@M?NIcH9f}^cL(yY4MUM*?6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_IK+$UgMXw7Ky&+Ka zra;kK0!42N6ul$V6y4Rj@Ky$-{71U{+#QNmO& z-fvx4;jK*3GwE8iI24r=sk)|8@|6@dG!-|0Clr;O4@E8PP}I^6MXl^m)M$sIvK@+A z+o7n*4n=M3P}J6@s3K5Q6)0*aP_%?V(UJm1O9>RU7bxl=P}EVNXla3>P69>C2ox^lZ)s;Y zY)z%)D=Av5sd&PBp=fRALs1ty6m_*jQ8zmjb+sJ}qb zRsuy^3lwc5P_(T;(RM;j(Hc#K>oOqaAJXSKt{IB*=~}dXQz`jMigs=)KD#&+4RAgb z4YWhiAUhQ8Vuzw#?NGFv9g23hL(yP66zyS$qCIVj_7W%>B2cuqK+!$|MMDLO_7x}^ zCQ!7WK+$l4q7ec`BL#}~7bqGfP&8VgXpBJ70Rlw_3KWeMC>keFG+v-+fjir}WnK z*-fS7D=9j!skp}{q3C?)L(zOY6kTA4q6_U%bdep3F1AC_C3Yyf)DA_L*`a8GP0{57 zMOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2 zMRy1kEfgqPBv5pxK+#=7P0_rj!r>W^^7-k#j^~D=&(pQ&?xs@ml@#6IRJ`c3Q1pQF zq3A(76g^~zqKEBJ^oSjb9<@W!V|FNd+zv%g*rDi2o1&)#ik=oIdPbn=S%ISG1d5&) zD0)Gl=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84l zYKrb{Dm;<_DQ}$Ky1vibMQJQ_81d8f~nxYSz3a!4(6upza+rvkp z=+vaB*rt?xB}FaU6xaGX6t!|b6gAqRsBDL#)^;drvO`fDI~29GLs7*JMO8Z#wX-Q& zLZE0#fuf}ZirNblbr2}(C{VPtKv5@wqGbe%mK7*kPM~Ocfua=ziaHAvtte2ml0ebQ z0!6C`6s;;yw3H)@?KXw8Ga%)!(mh(2P_#@UwNsl?@|6?~YExYJeJI++`B1d09g23dL(%SbC>m^s zqCMkSBbbvt7fdWNi1&YQA6pa@snjla#QK0A`fuczQMU#b^q5*9R?_@yAho|>l4-7@? zr)$xaHl^e%DVpA<_|K1_XomBl=ny*;9cqW7nRX~T%nn6|+o9+PI}{yhhoYnGP;|6S z(J=x=#|ji3Cs1^}K+y>TMY9BoP829QNuX%9K+(wpMW+Z9ohndtnn2O%0!4EKip~%y znk!Irra;kI0!3#F6rCebG*750n%1VU;!l~POVT?U4-Q4or%!x5w@oSeN{TLMQ|$Xo zD7w)3P;`+UiY~T8(Is{$y3`Ium)W6cfgOr2w?oktb||{irsyhxqN@dpt`R7@R-ouQ zfuidLif#}nx>2C$CV`@x1&VGFD7sak=r)0(+Xag55GYzGP_#&(=uUy6y9A2v7AU$$ zpy*zqrs(`Oh0z(1@;d2SG(Qy0Pp{tYYg0US5ov@o8t3-grd)#4@FgzO_TqcXlZH z-VQ}S*cAOJQ1p{P(a!=!zX%llDp2&BK+*34MSlns{V7oNmq5|q0!9A_6#Xku^q)Xc zu5H}5QQ(VTQGYSFfod?iKY zw#6m?4n?h<4@FIOC~9MeqPBJ@s@S2ZYKNkBb|_lH4n<4ap=c?aqV@ts9R!Lx3KT6Z zP}E7FXc>W`Wd(|s6DV3kxI z6s;vtw6;)F)T(V^qYOy-&-7i>8{5|I^j}S{-nz6cC0|KVkG93V{tZPvoexF5>`=6h z9g5bqL(zJ6C|chRMH|?mXhS;`ZDfa{jctm03lwc4P_(H)Q6GV#%>;@z7bx07ps24v zQ9psAEd`4D3lwc7P_(r`(KZ4_+X@tICs4G#K+z5YMLP-m;qqJ3?Oh6xnyCr~t8plF0Z(MW-!{RN6f2^5VMC>kSBbbvt7fdWNi1&YQA z6pa@snjla#QK0A`fuczQMUw@JrU(>G6)2h})D-Q~w(wX6r2I_!(Aln`Xr*+ge{kDU z@|6@F+P3&vT_~FAd?-514n>FCq38%Z6dh@YqND6kbhI6cj`-*I9g428DY{mm=sJO->jjE#5GcA)py(!n zqMHSZZV@QDRiNlLfuh?5itZ37S}0JoNTBFWfug$vitZLDx<{bsUV)ihi~! z`bD7VSAnA61d4taDEdR7=ud&7zXXc@7AX2hpy*$LqW=Vna+SDkrzkH_R3}hW5Gbk_ zC@KmRH3$@y1d3V+6txs6Y9-VZecrb4UIwH*A)EDIgrdXJoql7blzb&cZ7Rk88beWA z=R;A&4nMT&SqCn9~0!1qe6s;mqw5mYSY63;83lyy(P_(8%(OLpUYYP;05h&^^P}EJR zDQaCQtX$3%{hr?I*i@EDp9Mcpf<m~4 zG(wQhc!*ijHtT z6dh@YqND6kbhI6cjTtsRQ4vqRDKHbplG6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07cL)?M6ewCGP;{q2 z(Om*XcMBBVBT#g&K+$~yMfVF7Js?o@pg_?>0!0rCHAR`?Tg9g1GEDSBC; z=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2fueT>iry0_dS9Suu|UxW0!1GR6n!L6 z^szwECjv#E3KV@NQ1rP_Q}kG+aC8QwTuom*^mr)xGkaM57nM@-l@xtbDPGnw6n*P_ zDEiJ0Mc><@=m$F#{b+}xpX^ZdvmJ_lu|v_Xb}0JIrs#KpqCW(R{uC(sOQ7g)fuer| zivATS`cI%JSB=|tit++Qbpk~NfueeWqM|@igFsP9ps0mFQA>fMRsuzh0!3wkqSiu9 z(N~qi6B&^5rs-Prbtu|6y+&)QmXfces9G(4(J2(Qb3PO;VTYn6?NGFo9g5o9p{Ro$ ziaOe%XlXkXb+SXzGB!oa3KT6TP_(>2(Fy`Zodt?k6ewCrplD@*qE!TnRuw2(O`vFX zfuc18iq;e;T1%j4ZGoaL0!3W~in<9Dbr&e=AyCv)s3~e&Ei^5YDS9Bi601~eclzgN zc>Tp=eV(6!oz~(Pnli+T5mS z3xT4(0!94Mu~Vl|a$f0!7;h6m2U|w4FfF_5wva2o&uoP_&ak(ar)z0|bf& z3KR_zDB4A!Xjg%v-2{qu7ix;utrm94fRxutaMlY&-P5&baJ7_tB}GH3#i=WVqP?9D zMf=#HXs8{E_O(ONFgq0OXNRKUb|@NQhoX^oDB9nqXp}(FXn~?J0!0T16dfo~G*+N! zoIufdfuaclMH2;z4iYGuBv3S2plFIf(Nuw=X#zzD3lvQkD4HQqbcjIFp#nuSg_@#0 ztA+D2Amzi-=Uwj=itbIX-VUpllCPxbsA}=<6+_X{&WEC7>`-*99g2>#L(%beC_2Fo zMYHTsbfO)KPO?MMY@4E!1&U4)C^}W3=rn<%(*=s=2o#+mP&8Md=uCm4vjmFH7AQJL zplF^z(YXRe=Lr;@FHkgJpy&dDq6-CzE)poZSfJ<yHdY-=%SB zwUm72+UDx&S8BP|s`*@HVfG>0T;d*!s{bGdaYuXfJm zHmG!3IhX5Q8MbOJw^`-N)pNOim2cL}<+iT$>XOTCUzyP@m)p5=e~(;lmr8M+TyAh> zyY+IpA(c5Brh-W-(6onBdfw_NVb%E-aF+`P)Qd**WU zD?bd$%$CY=F%jG_=tTZc^`?@mbq+IU%%8e)Iaz9soIW?F2y|VF~T<-7cQFF8B zf4=(oS=kF9Uu``vdkN&LgU-ud1o`T@^Rt&hzWV-!*$W|GUFDMOrI4>4cv<#h$X9Q^ zJbO9htLa~}UpZe*{~Y=1`D*(2q}R?@(?1B@Jzq`#qU$>OYWgQRH^^7hzp2c9=qhL>7Qm8oUf+utv@7RP2U`S z-+VQFck2=PYWnuXqx04D{bk4ItLYnrPRv)+cX*tVucmL&H$7iX-(ziNzM8&C){*&Y z`YuPu=Bv*x&R#%M829n@8FqyHGSatg?u%A~Qqa&h)D zU2y=*^z1RS-|>|GvsY+7eClbp-99rr+)(-J-{Te^mRoww z>`?RR{@I@@J-Ht^ecIEPTzW|J>3%CrAKQHTtMC3?l%C#($^{o)_0aTOhnuoP=?PwP z_2xfgL*<7%@A)@N+~g^nzj*Nz)0+={`1T!lWq*q7`TyDvcl?vJ?9lkd zEtk)A_&I)~j~tqJ?ydLDXnxuT^?Q6&^V9a-LHq2Hj#M5!|MER^9quXC{xnOi5ijLc zXO7>f`L{Xlfsanlo}%nIaK-YiYQM`5w-0WWTl$Uc$lUCY)1fXin4S~6*3LFmKAC;r z!|7SxP&xmyM`ve0%bv#DAGzq=>}T2Y{EXjDSUe-wVQ_Y;`MFU$Rd;ZvYe3!f?0*N= z&B*?DP~D-~6>e-i)(w8`bKbq``#Axx0bu*I@}UZ z&WDa%ee<~=)t+TnoPWlR+0U{w8!mbv-+X5D^h<|i=CZ#m%>Xh-8S;k8g17#hT?0^^ zJ7&%1BRidQMw{j%3wxFa;kgdoju~>`%YUy_wzgqgYpHSmxF2C+SDAkd1w_zvAgfu~RlK%id5)KZ>hl?{3al z@~bqpYb-Q%YTC7ZCEvDvE?2j5uCZ~`Eah^ArE-O)jT$#@+^}(*cG=ZA9+Ixj>*i8v z$mh3dm(PAu>YVNLor_zv%QrUGj-=kQb*|9Duh7`oy0P52LH1a!+W#Mq)tEij|NK7X zn8n&}+d6*9Y^GnbDSpZ3hyFjmWSjUUBt(@|-iJ$>nSt~UQ9`}@}}{%rA^ zEV0i2JPCa|_U@Ry;^~_2)6vtlTE|Mh+OS!NbGGQ1o`|LX_tDcAm$(1lP}hFp7TI&M z!-+@dvuALR=I2nyla9{k>N?EXqC+mXboPK;dO$AM$>U@%z^=LU8;@^l{ynp&E4!?x z*LT?q?*He%jj|VDU9S5@>Hi02KN@l^R+y4o=A!iTU23~?+Ue&@XMd|bJpFv5>__w2 z?Em-8e&lnz49WiDOv-+woc@1a_9M&bwQ$euNpL#-JiQ7|kLF2QCi_YDn`HlG+Ty?T zIRE?K|L(n(%v|M0WJl`qe`PPreD+`VxY>_<*RI_r4ePf55cK(QWvo855^WNMZQM5mP6PocuozOOKyD_J-XiP8u_A%#<)|z@8`wz zDU+I?CAH_s&XXn_kUh^QcN;Wu*rWsdPaQvWm+a3nYUi<2Cl4LC`FcC7`~Sv^Y1*(U zBhzy$gV+3m-hb-&;k|mS*L8TJFm%Mo{fA8*J7wsU852iN?m9XN%U)a~#*CkmjqFX1 zL4CIznmw7r`%V})Zo>GiW%z&@lYZ%1%4Ki17MpbzdgY77cK`qWD^?rw-HQ3b{wox# zg-%`9UU|)8v7uX5I}{G-`hT%^-{Dc!{k!jztXY|4(&!*HbdVZ42-17+ARxW>UZe^N zic(Y%5m5xCh$xC(5fCic1uH5jDx#gL3y%JF+Js8Q+#pv%-og!DcCa_*z3{@*s+BB5-~QfpJazLKiv-Q`O%r~o?R_? z)9F?HTt)tyXVur+%2T|8@0ap(70!BNC4)CzB|eXztCh=D;&c1CuCnLbH4wZ{xueG_ zeo=Q!u*>bG*Nn^6dNPp)REmp$rV~YFf+=0baad(0LtqWy@-Cc zOAkKT*{4zWdBUz#_qm|8UEh3mXyE_TrE|or zUUl)mL9@7Ds>I(v%m2$4%pW0k?HuO+=~2VqBK{wJYWjPUc!&|)!uDXPcyGNs|Nku< ziVf}t|Jp75?>=yHS8D|f#eC+8K4`ViM$t#%_AGZdnVVbrUq6nj`Uyq-g7IF?%I-#r^$V8p zQ)>DJy_s$Nl(O;O%o#}pxn{n<_biwG+y|^8#1hbf) zTg9(r)tlbSPt=Rmuw%N;a=L>Y?CS-1#vK1QR~mOI zxr_gk{eQlOf=|}}diBJ+&mZm`{mXa2|IHV6UjCEMIsc^#?~k#Y!+p(Ep_Dy}NASNt z#uj(FyqT4qtgZ8=WJ+u5+LZrSgn7TtjT>N(LI2im`=8wc|Jhmp-@Rb&uKe#mi1}|{ z3Es`l)!(@}y&Zq|ge7zBE&ONi$p6i={+1l~wO18CUu*XvStTyReKWO7^OpTvRBaVw z$Ba5vTlF6lJXxzo=94v>W{fu395_Uh}4UnGE;BBioH1KOrNgedAvJ zn|A0{EqL9{IHhLh+pA5gp7nOCWxm~}*I8L)~N_yJoDXy zU)8Mlu5RXglHp{>v~AwIf8%CdqUX6AT<@fVt*4s(!eOkf~$G&W!GiW{9Y+ zm&hc-MaZa=`3f_#6ru(+8Cfjd`=Sc~l}r@w-XeIjS;jIPvY=JvnOW>IT5tnpY2!9? z?@DkUPuPtUy{FO*ocW=aQMGFH8SbvkE?Bmn5uA{bbwy>n-D~UhaoYr>>@C#Ex{2L& z9K4Qdy!9*-8CfVYvZ-)4oZf8a6~)by(L`4UH%r~j7jaj(uGOqNHEy$-S(hhJ5xp9+ zAY^2d5D19AKrMGcvUqZr=&r5c^4YWP<=jzkIm3yKCc7Q~PyT>SKcCC`v5mc5cb}%W zTRrpkan~}JC5st?0F;TQj=PxSGe1C_MxD!NBfGa!a_8`ho%i7Oac?&Igu9w~Ue>FK zUL?CS@8*80q?hMJcVkD335tG_3qH3s&pg}Ryn2mUmjFQS>eur!p}5;OcnewZ-2Ie$ zspu<@KFh(;S?+U>p2~bj9O~eFcSmjan3IBQB_lZK6K@u^j4W%Jyt9b8&*|>QBj$gGC$$F56b9eu-l}o`^jJX;1ap(BzPj5vaB0EBkPvW$hzsdT{7H7 zj-Kou7etR-?-}kxBzUdaZq}?@(Om>xLmBRoOz?v4E{r+^Hd;cnZk ztJyu(vP1XurgiJ4+mCZAXQbN?bgR~>RwKRKq@iPm4xBu+e0rs^gC|UFFxXvhLuXVP zTfMpqQ$|c3JIEb}jTt|1N+tKx;0Er-8Dhb`2Xf_z^E8Wjeua%aw(8iTYvyP33?8m#J@m|a#F_Pg(>-+6RbVIR$xO#QSj~DIneAaDk5#iC zGxA|!4n3heO)=MvEA3BXEjZJSp zcF@ovL)@eDZu}BO^rMMijwt`X{@991cE9y;+5K@px0#*le&wfBw%-`BUl?hgT5e%v zQQ{2=H-;C-FY#{*-Rv!mTNWGBxUPG_f%bbCF|qD=EBQ( z_In7~{&?!VXLPYa&^Mz(Fw&*Od>DfkmSe?_)!&)?#H7bpAk?U!=c z_WTu@zii`v2O`@a&;8m?_CH=s=84hl*)JDm`{TvfFC1n4@nYQXtY`b<#iV6hc76Qg zd+WuxUuVkp$BW68ZQ0A`jd8ye6}?vN_RZz4pVHZ0B8Pjr`akW)|Fk>)(;oCs`(J*S zq|}s{QbV#messTKl5IsFW&Y!1%gj|hqxQf1N+tL_xW>KRi2D_>!*(p_erer~?$`I- zuQErs{UWaICXR@`+;%&dbbGz_Y3--oZ6AHTc67g4bxFIMyD9DEN9ef2 zj_&o8a5k*>(9!-^l(z5FalbppxxY|w&fWCZbGYl>jumyhQAd*!=Wbs6n2d9%?3T5o z`(3T*(Y>jdICpavx1+n6%c8wb&&`+Ek_V-p=a>DXPz!8(r8aiWg%bX=t4 z3LPKUaj*NBvA6T4j>p~gW&0-`eS1IM&Z%Qr_kP)~u48LQ+je&yM?2cKr|bBrd*5xp zpyPRW1=#l7`)tSh?jJk0*717x*EVb~*YQ>NOMSNA*D=-I_O=V@*v;Jrwg>9Cwpg$? z>v+svvG)8QbSzUU*wu9$QzqCmb$ra-0QT}P>UiPGVEYw<|#3h>KN>yI!Cs}~TMoKiA4hb|Gc4G}b-ZRo zu!rk-pZkEYmw#BtZ^i`std14O2fMD0lO_gxo{mpX4)y^ZFHH@0(zM{%Y({YGtmDnI zf_iOM-osj#F+9_5vNBy(QSM z=oqs+*eN=;SQ+fDI^J@7ubT-S zullgf@$1`!kzN}*%_j|7P{N_5&4F`Lvj{6gX{jQD?_n%C&m(QY~ zwfnnVwm0hdsryS^womFX^^{wIX}@Ryxks zai@-7>6qXB1sr?1bRB!>I9ta@bUdzOKKGYb?B!eQI9|t%I)0#IlKaai_HtM2IM$Bt zdY!1_EFI_SxLC)fI^Ln<8XeuK(brc%$8;Ut!B~vt>a`Jr|URZ$Ln=mrsHio#@jK~{+@2|_S_-*c0)Q&w#Sq1`iQb$ zo;h~Pz(FyUCr_Ca97ph!`&Q7Dn9BCOmzc_fCQpv3?7mx6*<$6aZ&TZs8PPt(e&XSN z_%v+1J0<$`z(Ip14V{+#x$bW#WS;{k*^fu`dV_QRwT!X9TcFqIE?7+E!R{B~hq|AT zWqYf`CJh|xUZ`=G_LT=tnKEhQps7>btNqJ=+(TD)Z)1P?Blu&tVfH`ns*C<9?*45r z=LIw7pI^?NXMf7Ne-hk3|I^EvnSXw}+5ZBG-FEh;qWi}^ypL(*{;@yj`ntcA>W=x` zKlU>AkG;KC?jJ6LdoreQBqnBq^UEKeYUV=r*SEi4Y)l>ZviADyI^gx0RnBow#=KB7 z*8K%rdn)+DlkTD3KfGMO+OaYB^FrC4H^@Dm{q0^H?p~j3_I9oFcBi_hdEM^Gn9J_< zrP~ww!}BJ(o&EK#8xb4zZ?DgN`IGtjmbj-m$2}QStWNN9_O$)sd5hfB*%>wDh4KD(Xl@};?dczqALr|lf`V1JgikBu3S z96W9Rw&&SD?jh7ayxfnyV`JL5#vfj8w+r?(f9hQ0ZeNBw+S|21?jhAbT)zF;-rwBr zd0f8N-P6wU1b2x3nc!YuJ%&5-w(Q8qiamR~d%0sS=66rq{f)i89PS^xPWaexPsZHh zJddy^^oQ4%)9vgpci3INBfOA1@^ab#T21ZB3)oOLB)l7Ham8+VO?ccR( z)ksgTQ>$*(I_dUjKxAI?b}fRxmleF?Soak_uh+^Q9iz+sdjsxIxfu7?ZDT5(ywEX6 zdfPL5rZzpldrG78bu&7iJ2vUTwl7^c)ye%6v#FK)ccV3f+`n^NGw7O8tKu#mZgi$t z)sn^UZF6tCb*>*vU)!d@fR6{|9_}I#}`!Af@v!c!Z3&$p`XuYDv*p4;6|rc&%eISg4XvB8a$}&s5R~qG(NvF_nbCu2X!5Fms`!w?Db~0 z?&_X*w_DTO9ldaD!O;st9&`WP@BX>XUEXRXOHOIMVUT-U^GggkKB(k~dxOi`#V+fY z153I~x<1<_J$hl?-mx9*QqC{C|3bMv?vf6$%RaL0$X0fFN46Q+`d=?^uef~COE!4W z;8AOJx$J4XR87vOPwms9bBk6j`nvb{R4031A3M?b{DRzV+YcTzI{JPzKQnJi_qILS z^l06)l|8>l+n#NDw(iyHfV%~3+pUzNl)Ig(wme^?af7y9+UQnlWVe*vLZ1wL;oA$# zYqze|W`nz~f@`O`yFP}jbpP0OvLU!GGTe1hrL}ucas=1L+JCt=>{h!w_V>efo9*cn z+-^&b9lda$yDkbpTGQQj<&L#!VYgso_wQp9GXBl&*FP@b`}Q8%b+A6$^>L4`kIpSh zw<_JXOy>3R=m~cX)GXPyWSdg0OGU4NQf*7MDc!oXyUv4aY|e?89Qhi>#%zq)S}^d?=$P~YF<<0;>8EDX8ejeC`WJE) z{G(EXImPeKpMLG+j3eVxYUU{OQ)13p5B^-G@*TTZe>Hwpscs(~N-NW?Q@i!!XD1(= z|I@Zpt@cjZS!`*ZT~%8hc(K*=UFBkR-xP}7;_fJuFS$=j^|RljxDUa&*!Ust&OI(R zp`?3mT%3PT*bdulhP_nBD+WYU_#SuP6PMucbB~1L z62c|jy-O(M+s`QCLg9Dai+Inv7w{_PZfsBA=ianeHIIE7^xc>1_NIHfR~a7)mGL*b z=Y{S6v{Y9A^}J$kX2gWbX%=;}T1=?CW)U~5yZ^hlW??sL#Dpqn7IL#@OsJw}K{so; z|3R4M6>ip!302lC;AWkeP!-MmZq{}Gjd9IcB*Z6@#<=)*mjq%o_4a^)!gN~N;}E6 zyL|PvBevb;YoMKI+g-k^wG(W+%hymlY};MFM%wYV-Q{bn?b~*juZecZw!3^ywLRPJ z@-@?rbGy2`e9g6EZM)0YLfbJ&2!%>{uesYlaf$gU9sTdWC7yMUoI)+bo81eTkhcD7 z?$cdVNIRV>A?-CKq=Tk}bkvlPPMQ+ZSyMu~Xi7*|O$q6yDIwi85z<2&Aw9Jb(n}j5 zy|oc?jW$C1Xd|SrHbVMoBjj3bg!I=&$N+7G4Ae%*AZ>&U)<(z>ZG;TfM#wO2gbde4 z$OvtOjMPTRC~bs{)((WU_P%$we_{_)(Iyab&fOD*#)M6d37O!3@17YIGEt{W$Rte( znXD-xQ#2)Hs-}cY)0B|uni4WYQ$l8HO2{ltgj}bMklES@nWK%6x!MSsr;U*L+6Y;o zjgafL5wcJlA&ayTa)UNPZq!D|Vr_&h(MHHk+6cK>8zD=z5ps(*LT=SY$TDq&EZ0WJ z3hhA1I4{M0GD+O$KH-GM2SPq@G(s!GCdY)V@>AS1qe52eR0+9LQ$p5gO2}QB60%lP zLhja-kae08a*w8jtk;x~do>YqpEg1^Xd~o)ZG>#pM#v^@ggl^)kO#F9vRNA;TeK0f zRU0AOv=Q=(^riAR(l#qRz z67rI!gzVQu$N_DHysV9oSF{oGsy0Gi(?-ZaZG^n8jgU9A5%Q)sLf+Cw$lKZoc}E)| z?`k9DJ#B;>(niQ(ZG^n9jgSwt5%QrnLO#+)$j90U`9wPq^0e34-TsN29f!~}fslIk znB+*<Q!eI#oix(3FrbH6`S@ri6T@DIs5LO2{{w5^_RQLcZ0MkdvAS z`A!=l-)ke}lr}9Q+6ehc8zHB)5%RM(Le6L-LjKT3$VF|0{HcwQOWFvztQ`pX%$wqF|HRiElhEf;A(7>F9}*KAHaam$ zp-?E+U**0Xm26+l_^~>>nA`4QZ#=uG+wNg`m|ete_pm&HUD$2+uso4n$ZhwqJi;#M zwtHBf#J<99_pm&fUBGSkusnsG-);A>Je8f#ZTq?=jgZ%ZyM#Fic`Ue#n3Is(g1d~l z2)Qh{3z?gc(}KH{c?dZyxQm&WkY>SM&U}Pa3+{sEC!|<#m$U#O*#-Lw=L$lS1$Rjc z5+WAdB`riqwBRmjVM2lhcS(y7!WP^mElP;D;4Wz~f^WfH(sV+|g1e-}37!RaNlOso zT(GZoN)p_E0W|u>PAP%|;{Nloak1XB4oGCHJv{MZ14Ya1(QN71u< zmZENKDeBIaq8@B1>dBU(UThTgCZOmV0*d+&P}G-zqJ9JvT}wbwe*%gI5KuIbfTBSJ z6b&YzXb1sCLkTDvMnKVU0*XcuP&AT&qEQ4CjV7RI3;{)B2`Cyz2o$x8^;$R}kzH}HI$Mfnu%&1wTZ(3}rRX}g z6wPK!(Hu64<`PgekAR~21QabGpy+x6iWU-3w1|MB8we=6k$|Gb1QabHpy(z7if$&L zXej|jw-8WtD*;8z2q;=kK+y^UidGU(bQ=Lhw-W+I6Jxzw9FRyM_my^Nk`%Rzew`H? zHeYsMv?kVn*!|cls^~7xm!h?7DY~02MeEp7bPrpK*0ZJPUbYn7$CjcEY$>{*jiQYN z6m24)=m7$X9weY>GXX_g2q@Z0K+!e=iXI}MXgdK#4--(dgMgw(2q=1#fTEoQ6g@^j z(c=UZ?INJ)2?C0qB%tUi0*am{1d3M2dha2C>H@mxd|xBLqJhp0*dkxP?Vp5q5=dIT|q!mK>~^j5l~c^ zfTAJ<6cr_)s2Bl7=>!xNC!nYV0YxPVC@MujQE3AAMP&#mDoY3yx&NT{CI=*v?tc0n zijNDv(w}AbMdjkc=F1dSjPnl^m!e9XFGZEvQdEU4MOE2Sl);vwYHTU0&X%GYY$>YA zmZDm06xAl6s15-|bqOe{M?le41QgXLpr`=>MOPD0)R2IpMg$Z!CZMPZ0Yyy-C~8JP zQF8){S`bjwl7OOC1QfL zqRw%CQYk6w!ue9vl`Tcx*izJ;Ek!-pQq+?zMedi3?sjiA6e~r&*-~^3TZ;OyQPh`! zqJ9JvT}wcb`$eAMZK7xZ0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)8bv_S zXab7H5KuIhfTD2(6pbgKXaWI66A6K$j&WX92PBea_eGtgDBeD!O^OSfFHqApu2;2q?ON zfT9}-C|XQF(GmiRZX%%QW&(Rvt0Y$eGP_&GIqU8h>tstOiB>_dZ5m0nH0Y!HZ zP_&AGqSb^z(UdrEngbF!VxPpOO3_ZcFS;`>Y`#p<-Esb%<)mmG=S$H&Y$;mLmZE#v zQgk0%iZ-yN=zg{oZDdQ)Cbkqkz(&!71Qcy1plAyLMOz6d+D1UpLj)9UC!pwI0*ZDJ zQ1l1^MUN6tw3C3M#|S8ToPeTT1Qb0%K+%%~6g@>i(bEJJJwrgzvjh}9M+g+%73V$g zfJD~BIyh^k=%PK;em*X2zD&`cIRCRNrD!kbOVK{I6urcjqWx?sI>45qm)TPE3R{X^ zWlPa(Y$-a(M$zj86um(}(VGMmy+uIL+XNK7LqO5H1QfkTK+z!riVhP{^gaPa9}rOV zApu1n5m59o0Y#q>P;`WVqE87Z`iy|0&j~0xN-eG+{baxY z^F>_Pe3_!JazG;PFGIwHzLKH~HsZao`7%Wj&mUPu zijp{AijvtBi!DX9*-})8Ek$+ND5^(5(NzQ#)hD2+0Rcr<6HwHUfTBhO6g4KGs0jf@ zO$jJ!MnF+>0*YD?P}GuuqE-YHwI-mb4FN@M2`FkuKv8=FiaHQb)R7P0ukbJ*;2HCEk)O}rD!1=MT-b1x`BYA8wn^{ zOhC~R0*Y=Tpy*}-ik1>kbPEARw-QjajDVu$1Qe|xplBrlMYj=9bUOh>cMwptih!ck z1Qgv#K+zfkitZu=il%$s00$&;&fv_DqOXnAS}$zAOwoGJUrWIU0Y%RfQ1k);MY{=sqII74 zpaT;5*c9C(MPJx>(F>a|Q}mMOzvBJ^bo8gO`#E2V4zQ)@WwsQ(!j_^}*;4cxTZ#^{ zrRa6G6urTgqBq$ndW(Rfw+SeEhk&AY2`GAxfTBYL6dfj@=zRi;J|LjzLjsCEBB1DF z0*XE%py&tzMV}H-^cev~pA%4Ylz^gR1QdNiK+%^36dfl7iuQWmDF-C7(0Ns5AjZWe6xLOF&UM0*cBLP;?~$MHL7r zsz^XlB|@MmDdf#?Kq9B?i~HnI@Rj~V`;1mO6gFR`s9MOstFaVS=X@!u!Iq+$Y$>Y6 zmZI8hDXPPkqPlD;s>hb1tJqRhpN*mh1QcCOKv6>iiW(76)R=&xCIl2UC7`Go0Y%LT zC~84KQA+}fS`kpxnt-A<1QfL;pr{=IMePYF>OeqIM*@mE5m3~bfTAvhKvC6@x7z`U zEOaxJAw^%=eNop?*nF9yo+1BeQz`1j`BK!IEk)O`rKk^Eiu$sps2^L3u4PM6f3_42 zU`x?JHi`xjP&Al;q9Ftn4JDvx7y(7Y2`CytK+#A7ibfGoG@5{-F$5HiC7@^=0Y&2p zD4IY((L@4@CJ|6HnSi1x1QbmrplBKaMbim^qV6Ft)XXV5Z{Kz7Aw|QZU$BM3=F1e# z4*8{9NYNb5m!i3BDVoQYqWNqoTELc~>)BGYkS#@v*iv)@TZ(REqi8V!MN0@Mx`}|I zn+YgdN`*sMnKW+1QgvtK+!4!idGX)bSD8tYX~U1 zi-4lF1Qgv(K+!rvplDXeYvX`KcH4IyualxX?AJu@35Cs*{q-dsnM%xz(n=e!Ja>(D=Mv7kHd?|XBEk&=frRX4Aie6_+(Hm?j zdXp_hZ?UE5ZMGD>!$#4&1QfkTK+z!riVhP{^gaPa9}rOVApu1n5m59o0Y#q>P;`WV zqE87Z`iy|0&j~0xNON&peTtDC^{MP3b%KP8rXlx;X5f>Z=cbU{jm8m zMLB%GK}RXd$@x;0i!DXD*;15;Ek*8sa2#AyQk0J^MfurMRDdl-SFok1AR9%62q-E{ zKv59_ii#3YRE&V4bOMUp|Is{nH&EpMcb`E(k^5ht2LVN;2q-E|Kv5Y2ipmmDRE~h6 z@&puJNkCBr0*WdUP*jP4qRIpmx&QrT@V=nP{V#um5GYFZy+IC0B#-^xb($Z1rGM6b z*(k#gn=eyT)Atv4mZDmmFGaQ4QdEa6MRnOyRF5r1SFxqY{lB<_%O^z**iv*gTZ$U8 zQPhZlqQ(RiH6fs=DFH>z2qP`q0RrkFu4oKuZyDzFCMIG(FsD~dmU#939-+!&E z6!qbJDeB9XqJC^Cx|S_P{n=79fGtG>*-|u!Ek%RbQZ$5(qM-y74I`jvH~~c?2q+p! zK+z}yibfMqG=_kpu>=&2BcNzJ0YwuCD4Iw>(If(jCKFKP{$IesMPaafTHOH z6wM%@XeI$gvj~BrUcUFE0}|P;@5&MQaEsx{H9KwFDI1O+e8)0*dY-plCe-MfVZ{MRR`A_^g3IL-e617n`|k1i!DWOv!&=AwiLa~mZJCAQgn!oqQe9f zy-z^V2Lu#-NI=m?1QdNtK+z`z6dfU;=u-lUJ|m#$a{`Kv5>RxEfTAx5DEg9sqT>V< zeMLag*8~)OLqO390*byRpy(taQ1puL?QuXN?tdH;6M9vOP8zB2{IK~lML+uf7w&)U z5&g}OpEzHNPP3)xXSNibVN20jwiKOXOVKZEDLT)VqF>okbb*bc-v}uBoq(c02q?Np zK+&HB6kQ^q=rRFCG4Xmlf}&UgisA?;@(3sj5m4k4P!vxzY$+fTD5)6qP5S=t=^LDiBaqk$|E~1Qb;!pr{G~MO6tX${?Vq8UaPs34x-V@m@Oz zB+}C!UFV7qzS1vjU-s9C51TJjR43jaJ5Y-1a=sMRV@uIhY$>YGmZAo1DY}|1MGe_f z)QBxbjoDJvgpH!61QazRpr||>_T!M= z@nQ32iu%R-j}MljYdK$v`m?2I09%R%vZZJcTZ#s=rDzCSiiWbKXc$|HhO<#Lf`Fot z1Qd-TplCD!MPmpk8cRUYI0A~s6HqjPfTD>66ip(aXfgpsQwS)UN{#Ek#S&QgjO&MYj@Aw2XkF>U)X)o0x8NF{emq%Y`#p<=6Jv12r1ga`BJo%Ek)bdQuGj8ing<* z=wY@L?O;pMBWx*plr2R&*(iF9fTG6K+$sq z6g^Ks(F+6=?Ixh;MFNWU5Ky$2fTDc_6um@1(S8Do4iHfEG66-e5CTOH#Ct;=kjNu; z_w%3>mACO~eAs-MqBr9G8%9ado18C2Z?UE5ZMGD>!tQ1m?kMW+aXqJ#0?HU}i~u6;&(U5Xmmm;FD)hs~EM z`Z?ZzeT)>H;e07N%a)>ZY$^JMEk)3K3A`6HpXSKv9^0q67kp5(y}Z5KxpvKv6OQMJWUn zr4mq-MnF*x0*Z1H0!2T?d#4?c$b7r|IW0wN?a_6vaM*mAqI_XL=Xfc~&-qeRfGtH= zu%)OVTZ#&?rKm7lii)tMs3=>Cim|0AosFX61QeAZpr|APMWqNRDosF983KyR5>Ql* zfTHpQ6kSO`Q3V2uDiTmsiGZTY1Qb;vpr|SVMHvJXRU@FNIsrvB2q>yaKv6A1peRq+ ztL1=1KC{0(ls6oFr5~}c^lOL1=F1da74~~hl%o2aFGUU5Qgk(2iW;(|s1aL=8ndOS z30sPqvZbgQTZ)>qQPhHfqLu^{wIZOXH33C!2qD{#+IVtY$+PSmZFhtDH_E_(P#pS z#t=|6mVlyh1Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gAGYKe~ML^MY z1Qg9CplA*OMRN%#nnysZv~|G+u= z6ObD@Uy2s9rDzFTif&>{(amfrTFRE9Ti8-`D_e?|v88A^8$~M!C|XHC(QO12-A+K! z9Rw7uBA{qB0Y!HbP_%}CqPqwvT1!CD-2@b^BcSLW0*clXP;@T=MfVXie4q4=rsb04iW-ITf$xk z2PE>A{oUBDQgnqq)P6l2HeaUb?XW+7mK43i`BL;QTZ-OeOVJ^=6dh(u(fe#E`hYD( zAF`$BBeoQM%tp~C1QZ=1py*QqiasNt=yL*!juKFGjDVsq2q^lJfTH6B6n#ZN(bohN zeM3Oe2?C0~C7|de0Y%>tQ1m?kMW+ZT`hkF=9|i4Z7yGwj{rfJD06L!q~%Xq(*^ zoeqc1mnk|I_Mez7MZa*q6rE>F(XVVNy1ydKv5L}imDP<DmIH3EvN6HruxfTEfN6xAZ2s5SvbbqFY` zO9&L@Pw>*`*?p1yl5By5;4A$P?a_6;gs}NCMOP>IjTcB!L(Z3?MrPA3OcLIuf5Kz>UfTCUm6!j*c=o$iw`Vdgmmw=*v1QcCM2o%*%@P;`ckv|Pi z11Xwe_eK2^!sg2q4NmYEFO;GooG(Q~*-|u&Ek(oGQZ#}sMI+f#G>R=nquEk4hAl;7 z*(e%EK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@D4Iq<(R2ceW)M&`lYpXG1QcCIK+$Xh zisledG?##)c?1;AC!lBn0Y%pnP_&Q`C>ogHZFfK-8}0Xt21(JIMru()*nF9yB?C^|qu(aQuBy+T0Is{|CiMnKU)0*YQIpy&+(irypyiXKYv z>Np^g4sM3FOHsUiMtdtEY`#pZMX_uY z#Su{C5l|E&pvWhnD4u|#Fabpg1QaC_P!u7cD2afgWCDs(2q;P=peT)iq8tPiTOS?(0ov8F zwiLBwOHnJf6t!kcQ5&`twPmBI9RWq{2`K77Kv72miaHTc)R};yE(8>HC7`Gq0Y%*j zDC$8#QBMMjdJ$06n}DKg2q@}9Kv7=;iuw^ybS(iz{Rt=x|qDSE_y*=TWM*nF9y zrHTGitEA`_&X=NF*;2HOEk(=OQnZ3CMJw4-bQ@cWZf8r;9c(FD#YWL;0*dY=plA&N zMRyTUw3dLPy9p>-M?ld%1Qe|&py*x#itZzzXafO7_Y+XGk$|F21Qb0$K+%H)6m2G; zXbS;FTL~!IMnKU+gh0_viQcCUNTj)&p_`?srG44IJuz&)Owpr>{-1YB(N4~nqQ}@$ z^f+6JcCn@C3APkH$(Ew0*i!T~TZ*1xOVP7z6g@{k(enfpy+A0^$=~^lJfb*s3L$(xs#FnCu*;4cgTZ)db zrRY<(6n(~)qR-h0Yy0oD9TAdQ7!_CauZOL zhk&BI1Qg{XpeR29MFj{bx`KeBf`mZPg+y6|Y`#o1C+f-OZQ*-})BEk&i-QdEX5MP=DiRE{l0<=H5@l7ONL1Qb;ypr{f7MU@FC zszN|fRRW4K2q>yXKv8u9ifRy0RFism)PgNVE!k4kiY-O0 z*;3SoEk$kFQq+zuMeW&A)Paqnjsz5SBA}=<0YzO1DC$Z;Q8xmLx)V^;gMgx*1Qhim zpr|(iMb{8e)Q5ngz62EYBcSM70*d+*P&9ymqJaby4I-duFabqF2!Wy|5wD&D60!eM zQK+dDZM88p5;k9^Xk^6ivr&phalRCdW=qi+wiJzJOVK#C6pd#~(FC>>O=L^aB(@Yy zW}|2d0Yy^@D4Iq<(R2ceW)M&`lYpXG1QcCIK+$XhisledG?##)c?1;AC!lBn0Y%pn zP_&SMqD2H0-9SLmjRX`eCZK2u0Yx_v0!70k-h2lnGRW?JMo7^GXX_g2q@Z0K+!e=iXI}M zXgdK#4--(dgAgdXCE~s8fJBblHyUr1qICO8|B*=8e3_!hBmRlaQnZWnrRWK^6g|n7 zqNmtW^fX(Fo?%PTvur7Pjx9ycv!&<-Hi~u=Q1l`JMSBP++DkyuJ_3qfBA{qL0YwK0 zD0-QIqE`qgdX<2p*9a&&NI=o+1QfkNK+&576um`2(c1(Ry+c6Jy95-yM?ldbLZE18 z#7o}d6vf$(&K{GZ-S&Ieha+M0Wr{wE_?5Ov(Z`%GMW3*x=m=YiK4nYMXKX3@oGnF1 z*-~_jEk$3jrRYmGijEUd^c4X`UlUOD4FN?b2q^lNfTEKG6n#fP(f0%tog$#<2Lg(I zB%tUg0*X!(Q1mkaMP~>oI!i#&IRc7)A)x3y0Y$$OP;`M1DEc7cb#Xu<@%Clehf)-> zPjA0P!sg2q{TcBmZ5>Ql#fTF?#6cr%^ivEarYaEcs5&I-|QHoZ(=Y@(Uh0T{KDv{(rvqOqX za=sLmVoOnJwiK0NOHo<26qRF3QF*o$UCEZB3T!E=$VO2m0*WdVP*jD0qN)TGWe`wQ zjew%+1QgXEpr|GRMYRYhs!c#q9RiB#5>Ql+fTF7iD5_6DQ3C>st|p+UApu2=2qEuIv7rQgi%i<%~d&6g=^ndD!7REk=0z7(})OHmuP6t!hb zQ9HI2wP#CF2euS-WJ^&ewiI<{qo@l3MO_If>PA3OcLIuf5Kz>UfTCUm6!j*c=o$iw z`Vdgmmw=*v1QcCMKv91JiUtr+G?0LzK?D>HCZK2t0YyUzC>lmU(QrbbsCklCYNu1Q z-F_LQg%mAy&kK!63Y#xeG$zS!{6wN1~XaNC5*Aq~*kbt5^ z1QgvsK+%l^6fGv8XbAyDHxW>DGXX_Q2`IXS5GWdzds)B%aiw)>(LQuLesX!fzBu=z4YPbT^AJ|#s@alRBi z&6c8P*i!T?TZ*1zOVRUeDSCk|MZ4Kj^deh|_OMa3mw=*u1QfkQK+%2ziVhG^^fCcO zuMkl5Dgi~W5m0oHfTGt4D0+i{qBjXBdW(Rfw+SeEhk&AY2`GAxfTBYL6dfj@=zRi; zJ|F~&b|rb|9gxUt2ImPWT50!1A0~y(mnk}uMzYf95!F3sC2Tw zakmte;e077%a)>YY$+yeKv5k6is}+jRF8n7s|YBnPe4%v0*bCCpr|1MMU4n3YD_>;69S5w z5>V8PfTHGvKvBtL?^OpR^0D0)l}Zl2(yyHCMvLUI`7%XqlKqo=q^K?DOHn(v6t!nd zQ3tjZb!1CXC$qQZ$(@MN`;PG?gty)7Vlp zoh?N(*itl;jiOlu6kSI^(QE>W<`7Ucmw=*q1Qg9DplAUBMb{Hhw2*+JMFbSxKtR!r z1QabMplAsJMK=*pbTa`(O9?2tg@B@42`E}dK+$qSplEEe*UbTmG_(iQXG_rwY$@8!mZBHgQnZIHMSIy&w2v)CFR@XypMatR1QfkYK+!7%6unA7(Q5=0 z9VDRWbpndsAfV_?0*c-upy+J^iryih=v@Me-Xoys5CKJp2`GA>fT9lwDEg3qqK^nD z`j`+XdMepF=72;h*xk?5QdHDEFZ4-r*nF9y&y)SwgHm*q^QGt*TZ+D5OVO8XDLT%U zqOaIe^fgj0*byPpy+!7icS$w^aBA!KN3*%69Gl12`KuRfTA-5 z6rClY=o|q>zYtJ#o`9lX2`IWiK+$gm6#Y&>(H{g9T_m9BPXdZA5duY@CVOQZkjOLk zGyTt`=(yb%T}}?0FH_{D_$}X%qEN~|ex>iTr6`^)MParSC9tI^ku60LwiG3?r6`## zMJa3)r4mq-MnF*x0*Z1HP?U>+qTB=&QdE^KMHy@Vi9bpncN5KvT; zfTCIi6xAl6s15-|bqOe{M?le41QgXLpr`=>MOPD0)R2IpMg$Z!CZMPZ0Yyy-C~8JP zQF8){S`bjwl7OOCgg{Z56z?$yBvRhsl$D}*`}Ed2C2YP-QTr7C&^uDpf%B!PBU_3( zv8AXpTZ+1{rKl@gin_6-s5@JVda$LaCmTh*2q@}JK+!b>6!jsXs4oFU{Rk+!mVl!E z1QZP*plBcgMS}<^8caaZ5CV#Z5>PaZfTH096pbLDXe0qeqX;M(O+e8Y0*b~G0!3|8 zybBIUq^jK)wUZ+IHc@C?O4xjvqDd+K6^Eo~GUrRt6t)yiWlPaCwiHcgOVJFr6wPEy z(JZzUUB{N9*=!WeA)sh30Y&o&D4I_|(EqApu2;2q?ONfT9}-C|XQF(GmiR zZX%%QW&(Rvt0Y$eGP_&GIqU8h>tstOiB>_dZ5duXMQoO4jkjO*!GyREDRKxCz zZchoDFH>}9ir@czDO$t%Qgjzviq^8F=x(+Ytz%2kJ!~mj&z7Ql*-~^LTZ%TYQFK26 zMH>ky+C)In0|XR3NI=nM0*bZ}P_&hRqHP2eJw!m!b^?kXCZK2s0Y#4xQ1mDPMLP*7 zdW?Xg#|bFfML^LL1Qb0oI!i#& zIRc7)A)x3y0Y$$OP;`NSqTdK8`kjEHKL{wgNI=n_1QcB&py)CIMKP)R!W>1hgh0{J z6fegoPSI|=FFGbg-`lUx#-)bMmnn)*^)o(|qA=%6Q36|v64_D|VM|dGTZ)p|Qk24$ zqExmNrLm2`I`%Kv8Z2it-Rpl$U^_d;}EbC!nYR0Yz63P*jkBqCx}|6(*pl z2mwV!2`DN?Kv6mYMa2myDnUR|Ndk&W5l~c`fTA*lKv5{w>*0VzHW?g0HTX*3J<@hx zu%(90mno`{>QDb%iYjux6jfqNQDwFiRbfj}Rkjpmu%)OPTZ*c)rKkp5ifXb^REvP3 z+5{BUA)u%(0Y&u)D7uP(qWT0BH6WnqY66NH5>V8LfTG3(6g45Bs3`$O%?K!JPC!u$ z0*YD^P}GWmqSgcywIQIWEg?`;KGj?2fJ7$S?>b&7MaPU(yVS7xGDV$I{TGf&QD@GV zqAqMH>dKa)Zfq&)&X%GcY$@u=mZDy4DeBFZqHEYF>O(+LUjmBy5m0n30Y&`@C>lUO z(Le%<1`$v+n1G@o1QZP=plBEYMZ*aw8bLtONCJvR5l}RmfTA%36pbaIXdD4W;|VC5 zKnN6dNcFySKq3e2KcCi7ic;;-^~BV$`7%XQQ+@Ba6iwrNDVolfq8V%{n#q=;S!^k~ zjx9yA*-|uzEk$$LQZ$c^qWJ_AEg+!idIE|T5>T{=fT9}+D7uk=qQwLhEg_)jCIX6X zCZK330Y$eEP;@H+Mau{%T24UG3Id8&5>Rv-0Y$eHP;>_YMXLybqRFXVIR_-t!0wBt zNYOcabiFz?Y`#p<+El;w*HUyh=S$H#wiMmNmZJ4+DY};}Mfb6#Xaie{?q^HUMz$1f zVx#B*0*W3aplCAzMOz3c+DbstHUf$sBA{qH0YwiJP_%=9qDKfQdX#{oodgs;MnKWy z1QhKepy&w#ik>8(=qUng{qsA_eWC&~6?V*{{zYOAVVZQ}k7;|NcoS`kM2l=o_{a zonTARw`?go$(Ew;*i!U8TZ&GxrRWE?6#d9X(N6>vohG2@X99}O5KwfMfTD8*6#YU# z(Rl)jekGvj0s%$85m59y0Y!fhP;`-iqCW{JxUiX))NBcLcm z2o!yp>izD3M4mG^$E9ejk@C~R=F1c%rul_VNl}FJr6`FlMagU_N?}V;DqD)u*iw{( zEk!xmQk07=MY-81%0oa=UIL2p5m1z$fT98f6kS0;Q9%NV3K39Ln1G@p1QZn|pr{xD zMd<_-6(^vm1OY`Q2`DN>Kv8J|ipmgBRF;6Eas(8WCj^SZXz2qBt>g%bW97IFH_Vt&EI@lin?*W z6m@4yQ4h8h^<+y?FSZo*W=qjEY$@u)mZH9FDeA{Y(X|8=^(UZc00Bh<2`CywK+#|V ziiQwSG?aj%VFVNnC!lBq0YxJTC>ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}qnnXa+ zWI~{*bDH;t0}`2F-@EQ2Mdj_jXi8exe3_ydY5osqq-ZAROVKR06kW%bqS?gRpa5^6exmV^{~ z3%z%w_ud2)5JeFb5Cjz!1Q7)U5fqRnMG)Te%z5rDgzxqL{{GkRz23bpID6kSXXcza zpHpWxLlmtv8SDMc6s8#mv)oP^7{DMJ_NvkpTuMa)kkkj4(iv8w^n74ntD(o5^rp0OAoxo!AYgs3f&T z#mw%+7g1EgY&5=Lib^6rQ&b9?DKbGbMP_KG$P1b&@`h%Le4v@4($GwiFEmqB1{xHV zg#n7n!2m_&VSu6vFhEg77@(*U3{X@V1}Lfm0~A$-0gC)!fFgewpeO(aC<=rDimJf? zMQ_0XMb%+|q8czjQB4@2s1^)RR2v2;ssjTQ)rBD`@-Q1}3qU-E(0w#dvz+OFLET%B z*`4?zio(oB?Ilwbj`&PbJ!qz=J~UI*0GcUk2+b5Vf@X>$pqZjbXr`z!G*k38G$?8U z0~9rd0g9Tz07cDVfTAcEpr{25P!tUV6ve;*MJ-`~qE;|KQEM2Ws0|EI6bl0sSzv%7 zD-2Mi!2m^ZFhEgT7@(*f3{Vsg0~ED~0g5`nkQ9ZO4LJf3kAG=&9m*7~r-rGc*`4?z zin^GM^AtKjsN&ic@tLATXr`zeG*i?ankni5%@p;7W{P@2Gey0jnW7|UrYIR26s5ob zMX4}AQ5p)7XaNjRv=9a; zS_A_Wy#oUjErtP#mcRf-OJRVbWiUX|au|}L;by}N0f6fL2)XocCG_#%qd zn2nXipM%ibqP2+66s?11iq=CjMH`@*qK(i@(I#l7XfrfZv;~?e+6v7SZG#3y+hKsB z9WX%AP8gu*T^OKf7YtCe8wM!a0|OMj2Llwn4+9kKg#n88!2m`3VSu6!V1S|nFhJ3V zFhJ2qFhJ2k7@+857@+7A7@+773{dnb3{Z3!hNNhf*$^!N@$jSOXEjsQo91Xo%;J%Is=p27e{&tQO}e_(*3=P*Fg3mBm2Ul^e1B@9sX3I-@rym;CUic}b&$OQ%{ zGQa>ut}sB65e6u7g8_=%VSu7yFhEgp7@)`lhNS4G+3>Xh#3Nfs*IP`{GkwD5tj07VsH zfTBt;Kv88Fpr{HAP*fELDDr~=iu_@Kq5v46C=doHss;lTy#)glRfhqJYQO+RHDQ3F zS};ISZ5W`a4h&FK7X~N_f&q$xVSu6#7?PrrUWU>o1V!g*)v=V9oawKjwkXugo%kY( z>U$X*lwyh+AU;#n5Sl4!1kDshKr=;=&`eQdXr}0GXr`zMG*i?Rnki}q4T_q>07X$S zKv4@ApePy!D2jmridw<|MXg|fqSi1#Q5zVbC>91NvcLdERv4g2g8_=-V1S~wFhEf| z7@#N~1}JI|0~B?D0g5`p07VHfKv5?clA>@gLw5m)$37Yg)nkg@qS19{FL&aLDC*{A z9BF2Xx+6YQ)B~C+>Iuyh^@3)KdP6fsNzhDDGBi_^0?ibqLNi5a(4Z(C1}Msa0gC#- z07ZRafTBzopr{`VP}Cm=C>j6*6b*y{iUz>|MOiRFQ8o-vlmi144Tb@Va$$g?JQ$!T z9|kBYfB}kzzyL)ctj zCJazC3kE2f4FeR-fdPu%@l2gW{S2!Gez5>nW7!gOwmqgQ1mVgP_zpMDB2AJ6zzcl zir#|(ir$9-iuS?)Mf+fYqWv&H(FZU<(E%8s=tCHw=pz`Q=pYPG^f3%j^a%`5bO;70 z`V@K8GPGTI*$~D**AhNUM(Pn4+=N79I6+C%%ZH6JEx)WtpOr zh|dC$Fpf@X?NLo-ERK{G{PLo-F+Kr=;WpqZj?p_!uZph401FhJ2+7@+7J3{dm~ z3{Z3)1}M4!0~GxT0~B3^0g8Tt0g5ic07XB;07bvR07aK!fTAlfK+#ngpy*c^py(P5 zP;?yzDEbWsD7pay6#WhZ6y1a&DLU?D$Q6Ki{7I{hUob`gh;6R7yxfT|qUes7aY1>e z=q}FhEf; z7@(*)3{d0&0~C3}07WHWfTEHxBt?IE84d_QJPuP^bek!vKs{P1Z+GI0DDw6;{#cPI z@1}F-E0g3`)fTC(JK+#(;Kv8uVpr{56P*f8JD5?bm6xD_Sit4}sMRj3-q97Qc zC>RDP3V{KNLScZSFc_dH9EPOG>}_}{0P$!-tBzjYa;85^z~fra+nx9#iW+$vt5#u( zA`qV`iiBp08bdQhZ$mRhO`w^grqE1LGiau$IW$ug1IoD6+x;MH&oH6bAzowS@tS+Q9%t@i0J9dl;ao0}N2q5e6tq zfB}j+!2m^_VSu78FhEgP7?Pp}-iDR}5RW$Ag6!r8rX818hy%3)% z>J7~lB|$Sq$jI<6lK8xMcFVwQ4S1HG#Cab%7p=n@?e0Xd>Ejp00t-;0s|Bcg#n6&!2m_W zVSu6$FhJ2r7@%kr3`tRUZ^Lu}h(}L)GNcDn6iGjn9qsK-d=W*3-p1_#OwoA6XNo33 zGer}jnW9P1OwnX$rf3Q@Q#2KtDVhe&6itU_ie^BAqM0y2(JUCCXf_N`GzSJKnhOII z&4U4o=EDF*3t)hvg)l(TA{e0P9T=c!F$_?&1O_Nt3Ih}^g8_<`!vIAqV1S~PFhJ2N z7@%l13{bQN1}It!LsB%>+i*qz;&DSr*KthIUnJIfyAxkZDaFM#uz1Dls$$wKZrLiP zlLVaUPq9o{%v4g$=1Q1C#L(Pq>QGWqN}Cp$6s4T$Coe^*Wb!YqD1N5CWfY~FX=gb_ zscCvxK~d_OA}cFOsA+6fMX7H(=C3FbCeLb$(!|uEx}rpx7S~jimZqO;D@v>>Fi272 zO#MO>rM+oan4)wt{asH{5>0P6RFs~k!U#o4Hhs}pQPNE%n<`4CDWSQd3^Xlmp(r_~ z%Q1?QZ+fe>q6{+)h*gwPrae|g8E1MDrzjImP2&}1s%b(8MVV^3#eRFu7@N&OY&fa%mg zMfup|m8~d;Olelr%koQD>2TPvPUS&S<}8zigLm9e2k)8GPNjF zlq;qw6BOmT>8nYKa?|89RZ(u6x=mMuZwGrdo`u4<+i0*9(*dZTN7)l9GCj8M(=PQ@mwnO=$)rJCujW-V1Sy_PCgHPd^A z;#Bjk!=g-7GrifPlWL|{GbE~J`rG5pWMQ_b{OjwY(+Pp*g(QqA;tMrNvJ`a=DJ8!)l6&emsB$? zo?cPSwEA^jHPiCNP1Q{E&)ce*CJ^^jGmQWrsb=cJpQ>hRgI}nM*LqQDTsO!n=iN~i zg;`HH;?fz!*A**ks)|pbn4qW)O3fkLN06te4Otu)yQ+;?jHeh8r6%aRtq}E3jpQw@ zX}88wlLarFQayJ^ZNJ9raPm{s0qdr0|u@vsrW{TyiydajN;~X z`0(y?V?-P`uf-dFI5K~>wuxBzGM3A5ak>sJBgFsW z6o)@pv}&x_+hwGp_^#kRx8V3!HvaqNFg;CsV^ccn5#F2eXbv6TSYpo2wKWyr9USKp zvQe1w{Qx~l8+I;VBa<}s+1;Bm&id$Uaf)wyafK)!#l=58>n(@0Xhw+|Mv2lBD3X75 z`^=YP6yKR*XG(qqcD}Ug6K`7%j3q|-hF`F-OX#>qouP%4#jmf zSO2THIKHvOPgx}!=u!N7=Y=U{-{mNJQcTr5wU^1?a&?us_~IJ9bMn*e!^Qq?Ub`-x zc_c1WxfP=Erhi5kgIl@1;tTyV8VqiV>ZQI_%E!}Cs$!|mWxYhLR}`0Oil=8YVJV8C zjAAI&*z;}ANKcE8fS9)w6OkJz=eilG?x_w+33S;8|yP+F|4(_Y2J zUJgg~U}=;m@#I4aNrx=Kht#*)4_T5A$$OO&k&O0qm`aM&(V5Nq7o(zhaZdOo-oa|~ z@<>FD@?NU9TU5El(dFrkKJ^`vS4kYCw4>ot_Je3~k$k6(SH-mp^Pw1JrjJ(@mvZx> zMQ>LY8^mP~R+^V@Qa-Dcej;&ZQG>*#Qw4$aPkgS6e=bVsY6=Nv7bR>ph4=LDp{pq* zK**<%S`6Bs;?k#*_$O@f5#`Ar+Q;$Zs27Vyz@Vhl5!L6VN{VFY2@z*egM&kIQ$qUW z<%HzrriJ7t<)vjL<>Y4PXQbt4q=%&C4$sNYCL=8)y&yLu&tV(wFZPZM$;s_Es9%1+ zAsI?YX7-?rkd%QL!$N`wW~ZeL49Uw($;}AK&B)5gOUVn#2v5q(FG%l~9g?4&JuodZ zrC(NFNZ+)yq?Fu2Az`6O^^(Fv!^4uoLdgsgW>8jkRz^@pN@~BLu+ZRoL9{toY z+5N>e&kIS&Ny#11x*#j5lgLZo_5%y@k~+3%*tWs{MllUZ$XeX8;oGW;Dj zkPZ;TRMpq$NrB1eM}df_OFywWTAGaLX3WHzDDoL4hQ=$4x)-^q5p$edP@9c zLW0Gqs!_T_{p$va?;$vUh+Ao+cNN|7F?!P`f66fBtEth4FF+L$7V|Tf2{RU}V=V4w zIIIL4%LuPpps`G4VfgE+IIe_AUWsaaC3NX0b__$ImOjQX!bLDxfx0Z8>s}m+?r8B zeT`*hvg>lPbxAvh|BrSHF;=mNNFj#ICVITOp~fmzgu&P5KcA$Go55G4#xNk*t*^0^ zp_ghbZfK;6oRqPMVhu4G1*GEg`G?f0R*Ar3oZcL&{vwXyuQC5WfU3~ISkmAtGH&p; zQqgx6*S=`cH{~M#uS)WNSoBRq5fUrDmBZ_V$nq>>tWZfWSYKlWoj_5)D(C=EQCAh4 zME#ObzM-f^5&YjP=qOSB${4+B>!sF_N-fM@YA#(xN8GVho21sEu?mG@5uve3sq$;X z`nInPVr*XC-I9_-?0Vrz@(5w#WQfojM{B`Hi?$y@TmjlGi8?Co+T;;APJJYx1sjcQ2@x08 zb_UzY>f>B3?H5H{3f@s9U0zOc6#2y=DUA?STtt1NxWF8*f$d--JveDN?_bZJju=~v zuo#?5B%EUq2@b=p|E)nr%Z${5zA`tW9K^ZAxW%C$I34xvNfU)GcemvQbcNcp5@}0z zm;hJNT6Ifm(Xyi+Pn0L;NN~&FS~|s424-jV_0#_=!d93)A<>KvC=+F-p8#0dz>%0z zeQTx1?oU-j-!+sEA&BLaMBCCtbyMG|g`T+dfpH9@ioYK3VdDWw2#c^CFwBk| z5CI`!b_PXWI04|oMu2Dxh7!d}GU8p~sZ7&iG zp9uNPVS-rQLOF^yhBwu-T|#jou)CcE6f(-#R<04^`eoY~7Qk>^^as>>uqEQ)zye8m z3B_skFXBpIoBa@alBhZDB<2LXKO&0q&>bpdy_=D}ODkJ!Q38BKdkRp-;tKILTUm-C zkY}*7A(|4gmws@4lPFt`C0c*}X3L1+PR17vry}N-x$>%n$$+~)I}KrW9Bc&IDGM?GlCwl6XId_Bo7Wh*Gs*VDYU@yUu)KifR3jh@e5igT%r>o%Fn%I(>5d zg8KRe#fSR^iJ55AG?9RyK7%sy@>2R{1P#o{>YJb0G*nn}$Pq-PE)@0s`Ter9g7Uc_MX--t#+!9I$!kKMu~ z;5sRydFEu-BV~laidfWDFkdV@F^^qn!BG3AU~_3`0fxu+Ki)vk&&fu#qnT zMc}VCjxkWQkKr7Ka2O}r$7`q%G=!5EhC!5Lwg1i4Ctkd=uW9I)l}4XDAk{CQtkSki ziYjcYD5xhi3LRi;RWaDK4+QPwz%YB0i^^jo%QoV)4JB=(Mu%EzuWR-(A3(B?_-ug4 zVWZL}CZ@4pO{$kIatHaf8kCxmo-T&nov^Z|S5>T-)%wpBS1BQu4PS|mSj!w$O02t9 zb67^CRmA90H79sXEIz5&WcMjlw>s;^qsP);qcR!}RdmDDOO0cx;VY~$2F2u{==jd5F(_i~*x_SPyd4zn@2iNVW7du?95>rhy6Jm z%;8uLCvr%4u;{q!Iou=CN%|8GzZW==zRcm@A_JsVv1(3XS&>=_% zx-W-oMDdf}$>9xg0Z2dOu&%gfq$4@Z6}QYukLB=yxSc@y7>6$_NbOlshAqVnb=uy6 z!|7F}Ud-Vcabaou&m5MiCUqc(J*!LIkHdAM0BHYR9Nw%g_1_!@2TA=lhxwwQX#YYE zKMIrj3l5d~QkUegwJ1>9KY_!U5mGPZ@VmxRU*@o!D0tfcEe?A(mwEt)8(K)chr>T& zq<+F-XltpPayTSb>IocvY?b;Xhc0cUHgOmmFLh@QXLpc#IfrKxq`t~wg)UOp;4nE+ z>OmZC>Mr&B9Nz9J^)n8`lca9W;jk2`CvkX4fKJ!r6o;;Tr1s*_nkjWx4(IlldL@TH z43zpBhn2FWuEk;MV5ze?+>$5tJ`V2|Nd26{`opAd!QqGzQcvOV@F=Oj;?QlZ)IJ=> z6-wQW!}$}WUd`c!NmBpDVU?*;*WoaIy3~U?+%{9{4>-IxTk3x~Y&cKq7!F4*ka`-2 zpDmL58xD&tk=mETcFUyh!QsLcQm^IkqIe2}%I9|u{nkny#9^QHQs;5FW24j`a`<4g z)UP;<*d}!=4#(_}dIpC_-$wg!!{g_J0|rk4v&8!_4gc>_)_Zf9Ckb{brOe5zLt6; zhrgVW`cDq4eJ^zwhyBkbMNPUjO zQrD!e$YH17q)y>*+3!+s=J3ibsqb)D{kGKgI2?Fa>fs!|cTeh1IeaP}X`%EQAIh-V z-!jxVocKiQc^rNzo_3-A&vR&gA$4UAyS$V-jl&gUWI_9HzaPJT*hwUHoj7!YJ|h425kuoGhNBA-#aZ)8c^|(m!(OEuO3) zU6sQ`@rVuS3=UU`XKhGt=kU6C=!W!t4r`02Z%8-dFvm~o(H!m<&*RYc&pE6lo^B&u zi^EU~jf&EobsUG?IPAk=9*5&NoWoQ7H1Wj>GL7?&44+O^+vb(ZezvR^Tvz!|EIca~RHH zV-A~f=tf~N@sI^;5$MMi!zVq=qj8l;rx@NSE++9j1p7*G-ta;BDXAjN&y`^&zKJ!1 zd?lDB=}K^FUY-&xmKB1@47M*e(hyen(`k`f+#%?bEu!e(Q&LlNGln>B6^|b{%9Pxc ztiBn1Tp6dRGmsu0;3JBJDZy#tPIrd5jp1EUtOp(w7f;W8dt)(y=kGDn~Z>})tcytYL zyiVdf;)t(G%ety~aFD*q55D#h65nad-XK+JCwI~R$F@|V9M2otPF30qkIqXz&RZb9 zBaZm0xQNNAAAR8uwhb2A@p$9J@rZvq9?b@Eys6?l;)t(GfH)rQhYz+*6o%vR<~kg& zq}YbzEfe1nhmH|0j06hZ+MQ^oP9{lN$4q7Ze3wjCAwwHIbt@!ebeqvO$ar*onXiLXj&!Cwpd!XF&ZOK8Xa z4v6&qgq=i){T!d0i3rXP32PMEFd{TOBD|5GSYZhbbNIhu!}>ziZx|U7>L)(Q9%Ea@ zwU!TF$pfom=8NN!)1-w9Edxh9esK`=YaKq zMTE%*V#WXMUp;yGDluTcWxuvI_2^Sq|D#W@gr0rs8m82Fe(}9n+IsY_tVo7 z$7va@jj@igjMcZsKkA%AM;@h(wvM)p(Y?fg?pi{Tv<}m^A*}_LA=(h@P}>;-^t5*2 zwB~BL);vodpCL&d#xUyiHWi{wyaA{OV#?XaCvdo^7xFQp;b#w=)Xj$ zME^*wUfa)}x_W))aJ|#@xVYY_TBM4zRx5srI_{73;_9G>rC+prb^XBhDetblxn=8^lc_t@zu z{F1!xy1aTfRIS)H;rB}S=l(Pzee~LqKYadEpx1r%>#gsmJy`ljmp%n4Zd;DM+^dQe zp~N+F)DMU3>YBgzRLH5StA2M=zl}YnCHB}nF8#Oj$N#+R((F`rV0zt%{jpPzoE-Sn z!}scZ#nYFCw&|*NIk)H3{EuH9SiLM~+8+mp ze0C^0Rz39VR}bFyJalO1_L85dtIBoTC2H+%uC-AQT%(A?ceP#CU6$SYl}rrSrR^$G zhCB3aD8sGVHtROacHN74upmIznK&-P_(zq}R$J2qRZ9g`Egls5EVm>G;+6>&`{0OS ziB8;dow$YC!Z;9zR%V{lx#n9IXbY?hbx)QuwK6!@9Bqzuu0_^p)GEC`TV#zU=4V?+ zGV`m&If?n9dJ0zQDah0Ei!d+iFqj{wjkAin&AFv^&bf_A)6$AuFIh)%z49#uT7h+l z?Ff>2=QbwW(n0I+2Il+gv5=NbOQzP(+Rx!?P+GE>`E)JAnqldqZ;gL6RBr*&v~+8_ zB}4ZT10uADB56(1w;`=PwO-aZPe4L{t4wO?jmTpQu**dHQFOlNS8Z;7L+k!RE#{^Y$EAuWhhyux!+?3=zKG zvcbAmwCb|P5#ej}Qu+L0RQu&F|D0|4*u${gdO|eb3H_-Kw0>~Luq1Y|Wo|0fOR5J} z;VjV0j>iydtc~o(x<%)*)i0np5BB*w4j3l6_x}mSY`k8LX!+F`&2B zqb)`w=)VW(+fcXqS^8=Ht+KwA4y63VKN^-(J6Vn;C^uHi0B*-9H*IX~7}bLqJ#Tb% zDQ{5@EliZwq)6V{I$g(hmUu1R+FtkUc|$$WG|d`kiPN{D9#}=sr&(lwm>5t)t5zg$ zt(@{E>XFvcDr+C|7Uz^VA3bkW`caPyeaw3LsoYvTnCDZ%soaX|+hn;F*OEm)duwuI zgIlYStG_z>^~oObKWJ2Ms1B;i6fq`UulKjq&ux7kesb5Q3u(<}1stg~(wLLdtJNnJ zJDut|Fu7ClW_5~BpYh?fPlo=xy=(ug-4}-pIU2HSoZs+@QOi2?De=``Ljpq=P+j@9 z-Y|3F{VuOcSL(8H(x12MtlYTltE)}A_8!@&_l7;w$NV5n@l+RYD^4VnBtZlY# zd98fV2d&rEi`uwB--z)f!l0M4i>!9MLZJjt#R;)!RYI zZxb!3$kpoNl!^pPC#{pUv+miiRx+oez1H5^!O}tB8vm%D-s9?Z*&=ImVnCqgTcqse zm=$FoYl+n?R*QZN)XgqVb<@?>?odmkiqal^1$|t{fRvC`Ll-|!I}}o{+T(L&Te&>Q zH+fdR^HH;wO+Qa<)^(eI|6jJh*Q8{_b@M$gSI;<4{Uh~LbMKB`onK?^3;*8lrGJ)F zc6502Vh#}__dfM87qu;CR zmrblbtA_XV6B(|?FULF^^sIFHe(T|r>+1bdtJTwemVPnkA2i?B-*w^fp=mAua2@|r zA0IDhUKl>HaDPApQ|yVDZk1&{pf-4yQ$5)3P!G0hTZ)vd>@mTYsGro2zE-m6y;f^$ ztZOW5xnyOJvPxTRU2R#Tdx-(_#O(C-9!1VXQL>9IOSC1{rA{U5-0F^XXm#iLjMUSQ zR(F_FtDCQHlho#FgNx)%)->d8v_+q9zLqz%SdMiQE!Hq?xOKQ?1m~^0mRKZj`T92G zZLpYa=JIUQ-eO_)MJ-mWQ;XHosiayslvH!AX_4GG&l$U0dT2eYJzvWW`bT{}X^}HZ z^p9P%F4nG=uAG}Lmg=I1EINOe^%gmDthY3`Ev=99Yuj2ZU(KgTi`7~`1FpK>$6931 zOGoh5$0(<{tw;=T)eN?)I*jM1R3C})pL+H^cCps2dszuteanshwMVP6%?s+!Yt%5& zoH;CD!rsqLztiB*kON1}+vD0jZ}#}cztoTIomji6f9-{xW4g3BzI(xxyDdvki@DRT z>bi#qER(8w{#5$g(B;dQ^?LbYOPhbLSq6OHEPVa$p02&O{CRvuu`z!th1IA(?K7xO z%#aopcVFIfZbKuVYBz4(K6CWcp_2XIKH<6i#rJy~Z)kt+#NJ0Ye%ade&wBTco~&@9 z^Ysl|o8K7|bz|GOqc?x_p?2W1d7=7F<8GfPS~oPEcxlAMmh-C?(i}DL_p>$s`0!f) z340Iqf3mh=EXG|sok*f9W!A5CF}~K+l5ezbirbbtAT_N&we8x2HAC-JUnhE6G1jGZ zsvKIeqPZ*mTcfSDuC=V=(q3y>t1W&*Y0KUfrM*mBZe4C!p~tcFi`5$9ce2he#;)U? zYU5ak+BjJoS%hENSAvTPmWkR#>m>bL_C5r)(Q$r>+BjAlYaM49$2l6LrP;W_HIy|K zxf!Mn6Sa5vYq`O^kaE+}RvT%27w=RXHHX^RQHw2-8|N8fiX}y?0;Rr|8;l=%X}ztz zEiwki4~}!n#DKseJ~_D}dd{WO`I8^UVBAafbVRy`DK*$D()E7BZJ%zce&@J{$B~0a z=M6UAeUP=Wea|(|>n5AuYxtmPc&}PxtYHaHv#k7n2Tmcz1iNW5W_W8hW&BezE+~ z@}v9w)cnTa=fhXZ)k6g3tDQ6#mNVfIaf7TgQ{`-!C^7i=j~k+8 z#x6|lAW|NquUbVtc8Si_(k#(wGs#t;4Xh1x z@6BUd58K$5+9h|9{?1pvn_ZCh+l}7~?>)IS@j%=jF^`<1oXJu2bsegIXYMKE&O8!- z??cQjssEuqG_J&Kwd&nNpGqPWo{2uf}Fm%4Ch&T-xx%>B*Rr75Z#)YE#$gB_Y=s*J!JYl!WYg zz_Pf9LH*HdC4sT%JKAEa7)$C~vAVHHd&l~YWwGuh229l^7b%H(`ZkorY>U2Ds(UC2 z=dtJzr?F_Ro_;wNE%eEDqHKTzW&O0wB6*Yd8<4krOTJkBEYQzfwD-#qcPIw)9SZb* z*<$4;$F_3QL5nYvH|LcbeNEINS8nWmxnqCP+}8Wi?D=h{l8SIBsfJqpBDs+>Ipn5; zrK8r-n($g~&|kFE+F9c*@%mP@o^7?Z)^?V5y658GHnyEs(bjfS%MkxaO|iyVwKBFA zh^~74qv+IDnisb~)J}!^MQbIw{gLy4=CK}Hu{X3RjrDUO#o78?5#!7nRZgb{-x}o~ z+3=%7eJ?i8PcHq9&!{Z}x|gkZ^ez9y64g3BpOeumWcAI)@x`YZyS5oX{nw1y>t@we zzB*ZWWWoy5@SQ17ADw9a;EH*->+}u-vN!iX@S^UhmHX0Po&WmYsc&A)iXPMAy|$%} zH`w*_$=ru4_h0*MH}yRo?@smo=F@q81B*Xfu>ahZhE)zXtlYGq=FrSd+w$irhgTHu z@A9%lrTslGx(@G`_vNu>^Lr$WYW8By_p9r!-MBVzXoB7b#8I6W^}na6)1&D7YGp&7 ziz>#1VkReNclMs3oFLE3)j*Bf6W5%LA!6>J48zELuM%q?T z-n6>fU+)QIPh05I*NN&h2dXo);Z$6Rg!LlDD^= z@+SH)t(jH!eD=Iy^c|@+7WYJD475KHTBJ47B5P4%KpAl_^7VOseW$#IY2nszOFi97 z7xTKOo-UOy4X)j?bjB2qU%!nJPh80{qho)B@gemoQEf`^UpaYp{DHu)jtp5DaI#U8 zz2*m7ey+N0<-5^)y++*YJgvHmf5z~TgA1$gT~g3E%5&{Iwfg7$Q~#VtN{3$utUFJ2 z^ybp;o{i_m*GZp|vf#`QLG!=-{Hp)D3f>!vG)@4F8@IB?~MrCQXeT<(`u zzsI#dS+CA}jYj*0Cw%$u;-o)2NyezUKz34t?1@&0{cK&~a>jrRiwIpuGFHo!X2GEn!Z<#S%Mh!w3+l&!Q9{nKKbiF*-6 z+nq=~K2lDl?j1-o?)%kg?1}Q|taTQ%vMxnt-w9fRwUecjevHHbtK}^%@C~!?Ag6RY z-oLO@=GbF<>*vyTVo$`}m>;H)H4(g0Kr*5@e z-Dz2as~60VJ$)XPK6TyftM;k7?ZU&z!@n3d)=Bh^ja}PeWLiS)TAebf?^*}rno_|erOR^7~1$nbr`F7fA8)t66I8i^cb8rVPQ1C!fGfv31FjtF49(t_ z#4Zs}&0zK>#~Ovni{jqV7T9KQG~S@u+dT1XjGVpEh=XQtv$W|vd!tzq&EBTRPU6`c z^+bvOQ(~uRg>RtD`7Xpb@w7}KKP_YLvmIw|gRR-N`}X!eJ1efgtpx;w{)#5_t}&?>a!E{KAUnzeRjOgnaox9*p8a^ zhFr-z1E@QWbwP4XH3EHR*pR<=m%Df=+=*`ZpPHO!KBrSaA!Ke|>sH1*}On%C#9 z>UQ<->c4b)G`ZQeAL9JG$Bc>mc=Oz+>(1S}(6QNqrf1a|hC}~(zP8zEzLx#)hwZpppd&iUu`vDMnW_^*Ou{i$F4cDLXDEt~3ho!ocp zI=KR9Z*Lq|`xfi%4Y5KqgoREm|6GTbf3`NONV!aRYHy}mrfSoy({#^XE*NjaCL_;-y<)>_$8DMzL* z(LJ>&PNn2tRT9OznoK9vVXBJ>S|hHDlya(z_4K+(B|>#EL@xuXxrzRk*dVRW8*)|C zDOWAD7S?D>wC>sKBFcg4Vga2S~ZNYYJhjoWVuF8YSZQ6G0 zc8h%OD=}cZw!KJOA@7Hyt=On-vWolU4p*D*U_18c%k>&Y;(m9Lv6bWaE-@fg zJn?9GL%K8cb0FQ~c{K6Fmz>MJxvh)P(=E9#^l9M4eV7CHL0WK;l92bV(cg*ZQpD;; zTmAg@l0Y5P?`vCR3~<#(i?zmDjkJl4)k@o1JJ}i(Cbx`hshMn}5u$`fBh57r z(Q1sovaxpmgzx*ezo$IE(PLb{xa7hLKaKyiu4}CNa9>Q_8iBp3o>6_HvD>U}*6lls zr(NC}*U+U=_YYgSxr?fPpO@3@RF9-cq;a{VtaFC~_ViCj7A zUzgZ9Xj7d%mDP%Il9uzw95DmiY7Di-BjW z-uc<}lj^PAA`QKNTv2)SjqOjrSG1V)?6KJRiZ>iLehM#Y|9P}P*2+Bx2L^}^!spfAO`C#|GYJ)yCf zxbMYdF=CL$Vyj|TI6dF6Ja)OZGDYn$FbO4>*P1ApNx+y zw6*`#ZW{b2$4%Bo+1h{E+Pg%L*M>UuQZyDDBkmsC`zdPwhl}1#uB21$sQvHnw0_b@ z=aQIB^v{m%^TxU+R{)W#OfAzYp6TLTVf_TF+tmJda9BT?=hIHF2b5-Nk;L;=;z|>b ziQ=KgHbv@zT;s#J#4{jbRj}i0^#JE;D^>-?GhX^utfcGphF1j>1H!f7BJFFezCUVp zEAgacYm0nV(q5~(@EudiO%=UXQ(d9+n?9sNZp1i+|p>;$biE+Iu$ze%r@4e3Iyw#JU}? z#p`PyVm*G}$G3hO`7Cf*iKXuuS5K?mDD=a|zAa)NXANKcVZS}@Hw=F3-@S79*RxNj z=g#@q#iQ}Q@Gc2TP4`+6j~D&)N6izf`qLOOa^P;4T|IraW*)zMXYc)+J*IkU38_18 zMc$e?J3W+|gQTYlVn18gng;Tc$0x z(M+=f8gnhu<}=O2e5l`i+Z;)b7Usmx(Wbwl&dJ^f*LbRBniwU@k>i`kTqCT*xX!I| zShE}xmuIVURMrOnoVXDVBSR{2n*R*3jSQ*Osm|q!6+T(#Wd6pbh&dA1Im!vuxt@BR zqkPbqE7742q{VjEI=vxR&iz|Yt*3Z;xR=g`ear=Nh|(Cn&dC;io==pG(w2hKCJvM~ z(;|ydDr*F;p#JQzQ;ndx7Wy7KmwZy0a!WPhEvJ4?KB+8AEKsXb}Sg z=c=RC6*WS}KtCs*!i_0zDW*S{OJl&c=L5fM^z+-JJ4URqzWl2Gd5q~~-Em&irv8i8 zwHMb}6?Dw>WJ#R){FI9xU2W@3P&D2?4I)VcrDFx1}=+RYB`r;kFi8< z?MN}^$9*Yc1ZFN(#r!?vA39RvxEk?~s=Hl&`th%qpI-Rv=+jE$W{6)Q)x0v@DxT;# zJYD<}=}OMD*c&M{E*1TP;abYkr)N4`>(|{yxqoVc7%_-49+xs+8%g^s_B+sH#1j)^ z`H6|K;)#8+zQ7c|Y8CUquVwtB4(($eB)5ov)Uo40?Q`)hc^s&k19D@wQr2K3UbwmA;*-`auyuCa+)^c(7%yz_)Q@Or=F{EHyx zen&pT=GgDJin~#fS}mt`Py7l>a+OEnI?9R2R2w$+#0ENW32Y2JE{ z=xR{@O2s9J=Xvzjtn)u-B?)y!PqRK%^f&Yyw9t^)5JAJ09DDh97j@@~L5}ARi?Hvb zYq`7gmQP=Ke#G6-TI<)G8K;bkTUgn>Z(f;yV%1|U<~0s#6S{2bm5K62;gh2ukv z&%`hHixr-kEAAQXmiLSby~Il}#P|*O#8!T^{p;sVXL={~2+#h?ZC9O^7vh_I^iOjC zYNNW=+FrQM?TZn={_dUhWW~PU!+ZFiF83YvWpqDT9LJ^JsN?3#KPeG^T*|n;uW5Ll z)BnER_m$A#wwK_xjg4D+j@ZsEjV_#j1NX8BtIPijRu{j4)kO}h&b3Upu`2rq*QgoV zB!{u1tKU?y8t2$MR7#r^JBoiHKxIi!o(^*=&4RWGsRQ&8(nxKTb(Cea&PQUvC@rhV zb8>PW9PAW`U$Kexaa%7T$D3$P;~&jV=xysI68$r^?nPQ>IjY0)`dIpEeXW_V9naqD zypteiPW%fA%73DNg4U|YuYO*;UnTBVC0gYDs-i3Fi2>1CgCe<<_jr-2I4#cFR@8TD z$><33_mNmtp)p_4r}kwX!=~CbG5bg?L|GKxl!t-S<8o9-MV7b0K=!>H&{G?`ln|#3)6cw?>h39(x>*F zUOy*cKDA=jTc^_RUotfrvGcP}KAHP2^>=p{>^bn>{2vZned0bdc1mhGJ=39&87u3?MxI|G;D;ExK zH@I!Cwm!9wXs75pwS0WUCrx~(7EC;aC%(~W3NBr3aV5h81N+AIwX6}pm%U;RNWPXD zn7Pa$oxi38iat>EfPI&%q7S?`u9WBjONhR(+vTT63q=n&w@z!3x^an=x-0bTkMIsV z^?!q}^-FSbJKIs*X%Ww(>qKq;Jytx45XDqeOG2q?qK|Q?Z;2E4Ffmu8EpnDmsc)mT z5i@W(mWmb6#D`cKSf`7{3;CQAwbQlrn3R9IT&halG+4IfF{gyub45SH&yDF3SCB z2etQc?b^0&%j6IjV1(*ltWM7BJV|n*V`H4iaU4HMa`e$tUyxI-k|d|D13C3{a_WgY z&~GBAyGzX3U@h1x#;{C|V|mqaDlcjsYiiZ?@*-BKyx!6RoO%W&*gZ4dG_`4LRDaO_y%3`<=-w7f12S_g|0oy>8DQ1x3z7U z{E6qMoia0q&s-dNHFrzGxtU!u&RtfheR{n-_C45hb?_&*XAXL+$wxkGhE4xt{=~BW zZH}$*`+cjSe$&sEQTenoBVN;9!E&k4l zi;FQ^{MiE+7x&+UX(*$L?`_M8zw0IbZohGw*kUly&hh1wb;~`Q;uJFu6@QAtrI>r3 z_zM88u15NskS?z7--=xfGsO;ux;`!F`#o`LLulzv;=6GU#aG>Gi9@=%x>h%C7TesT zLlxH={FdFSLWU`>HCa{>GF)-3#j>)H^%U3IEGr3FUvaI&vZ9a;6xX^eD+t+8aSdWw zUdTp@YcR`lLPjXAAuP)Z8L7C2vMeKHm`GL_YhThLUE!=tlNJf9$J&RqNLhW>-lRp+ z8nE^vEz;JIwVAX?TqD*d(js*ctV@v=$%|xNlC(%)W7Z{v4j1Wro3$rtk-jFZJxGi6 zHDz6#v`Akw*2PGR^fhPgPFkcdinSYQk-iqJjig2TqFK9=7U_#&Z6Gbu*OIl1(Dg+6 zTCrA1i}bZ-EifqN>RQckQj~x33&hV``g>xFe=Pn;hie=6&0+^4L^INh^mIbvI4Tp; zmL(I?jwKTk&yopg&yor0z>*2+$dU<3V9A7ZV#$PbW(h*Num&MrS%Z*7)*z%CYY@_% zH3;d!8ie#@4MKXc1|hv!gODWFAS9VJ2uWcLLQ+|SkTljHB%L(~$zTma`mhEeeOZH$ zOx7TzA8QcOpEU>>z*-VwG5jgYzql_^VU>g&7cG(NKzAaC2+1+hOBQuP26I#$!E!g6tHAMhOlHphO%TrhOuNqhO=ZsMz91SBUyuxQLI78Xx1QP3~LZFmNf_& z#~OqbvIZgJS%Z)XtU<^`)*xgOYY;M-H3*r)8iY(`4ML`|1|ic~gOC}lLC8$jAY>M6 z5Hg!J2${nggv@0v3CS{)6mS$@C^{V1Y)MFUYES056FEf4A|t(kQzzsdj>?2AX32ys zVabFnWyyprW66XpXUT-DV9A86WXXiAV#$Q8W(h*pum&M(S%Z*utU<_n)*xg9YY?)L zH3-?n8iZ_S4MMiC1|eHngOF{kLCAL2AY=z?5VDgs2zi$^2-(FNgzRPwLiVr*A@8vU zA@8#WA$wVakbSHrAqxy4qWp{B7R`j~LPwI}=Ci5w#2BO|?>RVU;iM`c1jX32zn z!jcI&#F7d5lqC~#m?aZ(ge4R58A~SQbCyiVQI;U&7;6x6oHYpff;9*^!5V~|WDP>T zWDP=2u?8WhS%Z+TSc8zSS%Z*oSc8x=tU<`PtU<_ktU<{4tU<_G)*$2@YY_4SYY=jt zH3+%D8if4F8iZVAEeSbb=pf3!_;4{Qb^TBhGM(CxpWKNYBIL4>Ufin_a)qNZAy-*4 zA-}R@Lawo7Lawu9LVjb(gxp}sg#6Bu3AxFV3Ax1*g#5u8g#5`GgxqEgLhi5zA$M7W zkiS@ikbA5_$bHrzbJif_ z1#1xUFKZC;k~Ii<#aa^bvmsxUfAMDGPrkYSq7&lLj@l6M$F2z-dW*QLYNXdXm!R2< zQRUeD7I8Odev7y}G`~f>7&N~{yf`$!Mcf0L-y-e_&2JGe0nKj_FA2?W5ibRew}_iy z;4R{27_< zSAc=Hh*yMxw}@AQfwzcPhJm+;SAl`Ih*yPyw}|_}z+1%qVc;#|0Wk0u@jw`Oi+D8{ z0+5oft}d$KBLRrVGcj^?HK>xJWE#!BrMeSdL{Tl(NUsIgDXNY5Oi>+Zrl>A7QxpWv z6a_;wMIq2kQ7AN16b8){g+nt%^`JpfeHfsq0Sr*o5C$k}1OpUBzyL*&FhEgb7@+8F z7@(*L3{cb*1}JI<0~9rf0g9qvfT9*KKv6UdP!t0L6t#o_idw+{MXh0gqBbxguTRo#g%qNtr}q}R&p6vZPxQ`8=sDe3^t6m^7ViV~oi zqE66EQD-Gp6s@PWC|kU~f&LPxpeRo@_7#5!Ri`K)@tL9mXr^cgG*dJbnkgCv z%@hrXW{O5YGeskznW9n9Ownj)P&5VxC>jd`6pe!ciV9(XqVX_5(F7QvXd(ctjCJazC3kE2f4FeR-fdPu?zKEhFs&S|IQ`R~~OA((bS_aJ&Er(``RzNdF zE1{X9RnSb)YG|ft4K!1<7Mdwq2MvnW!vIAaV1S~HFhJ2J7@%k~3{bQM1}NGJ0~Bq8 z0gAT607W}sfTEo+K+(G}K+!H3plCM?P_zdID0&YDD0&|TDB24H6zziniuS_*MIXQb zMF(I=ir!HT-w8lG_7XUYnWArKw*H~&PJ9tXpQy%%6_}z!h|de6N9hGvS6Kr=<3 zK{G|4Lo-E3p_!s%&`i;BXr|~3Xi#(l1}HiS0~CD;0~DQt0g6t;07YNH07YNJ07c)x z07YkDfTC|zXDEbiwD7pv(6#WDP6kUP= zihhP6DLSYc%89=c@3E2EqK}!PF4Uv_qPi1bMA5IRF;cw!M{kR+AwE-d9hxcn4Vo#s z0nHTs4$TzZgl39vK{G{vKr=;uLNi6Tp+V6d7@+7b3{dnJ3{Z3r1}M4@0~9@g0g4{N z07Z{rfTF))fTG7RK+zKzpy(+KQ1lE2DEbEmD0&V96up1}ivEQGieAD1MXz9hBE`iv z%P*ndk5XZPA{Q8vqARMQw*bT=l$xKbOi@c}m<%rN#1~QI?qVEUl_@HQ_)Jl8Xr{;m znkn*xW{OHcGesq#nW9qAOpytiDKbMdMPAUL$QuSI@__-0O2Ys}zA!*h85p3bEDTUo z4hASH4+9icfB}js!T?2;V1S~^FhEfi7@(*s3{d0;0~Gng07U^XKv5tJP*e>DD0&M9 z+M?<(Kv4}Ck|LvvVS@m~;{h!wy1B@iejK$$HC^0^FQTZfi}9F0Qxt^wOi?g2QxpQt z6oo=FMPblPQ8+YHR1cadst?T+HGpP{8bX7jMle881Po9V2?G>0h5?G+h5?G2zyL)} zVSu7$FhEgr7@#N$1}JI)0~AHW07Wq{Kv7E=pr{oLP}CX*C~5-(6ve^-MHU#K$O;1# zX)r)h91KZOZ5P8I0uYboG}Euc6wRiFsjZ7U@kJDMa4~vTV~RQ=K2wwc%@lQlW{NsP zGeupXnWC=HOi>~W{So@Geu*enWAyfpr{ZAC>jp~6it8uiYCGUMU!BFqRB8o(G(b zrf4lRQ?w46DOwNB6m5WJiZ()nqD?SB(PkK+XbTKbv=s&@+6Ds@ZHEDhcEA8dJ7IvL zcVU2{T`)k=ZWy3w4-8QB9t=?QJ`7N_7X~QW2LlxChXIN{fB}jQzyL)b!T?1d!2m@E zVMvOWx)?qdfOveQ3UHP&MF*)Z`q;&t_#%o9yBL42%@iF$e5U9#Xr}0MXr|~WG*fg8 znkhOC%@lnB%@m!0W{OTiGeuuQgQ8O~K+$O!py(?Ypy+EDpy(SIpy&(?Q1mSfQ1l%P zQ1m?vP;?dsC^`oN6#W1L6rG0wiY~waML)s-MHgX!qMu-ZqDwG9(a$hI(JwGS(PbE* z=n4!;(IFRuOC3Q`Got|KQ>N$$J^ypn#hv&fihgr31_m)jHxQpG`W>1nx(Uq`-GXL{ z{(xqR{)A?VZbLIgcc7V~yUn5s01`q zR1%sgDh16HnV^{>Gc;4=1M%f24H%%P zCJazi3kE2v4MS2?%wU);0P)yKL!sgZIn$4(K~f!qJMl#ng&2&x!kD5^#Ak}apqZj@ zXr`zhG*eU`nki}k%@j3+W{Mg?Ger^5Oi?5>C~6D?6uk`t6g7bXikiXzMa^Jp_!sy&`eQpXi$^{0~96007WS3~D-Oj9Ev3b2i(7%>#Y%B^cXxLw?(XjH?(XmJ$vpRUo%j63 z_uexzN%phZWT8Mn(EtL91`<#-h=8KO1QZP+plB!oMZ*Xv8csmb2m*>m5>PaXfTGa^ z6pbOEXep9gO>x`Z%|BNg`hB#i9IuL| zu~pG@wkn#zRz)+}s%REl70qU=qB(3;G?%T4=CM&UpMatT1QabKplA^RMT-e2T0%h4 zQUZ#W5m2<8fT9%y6s;tnXcYlPs|hIjkAR{z1Qe|$plBTdMe7MD+CV_jMgod95m2<5 z;3%5pcF!?DyyHaCWK}dx#um3ne2JnRZhMdUM~Xv=c5=Kb+Qn8yyVRyX#$GQ5KwfM zfTD8*6rCra=mG&n7YQi3L_pDH0*bB>P;`}mqH6>cT_>RE2EkFZ&Fy|@fOy}^3+nBv zXtq2T-E@1zmngdHwxbKFqI(>#ite*j(F3+BddOBqkJzf{FK+!t_iry1Y^nrk)j|3EbBB1Cq0YzU3D6+!zZ99rw z1Qf*~pvX-?Q5XS5HUUN91QdA)D2gCBif+5zISdeQD|tbE2SxI>KQhcCzC=-Um|d}m zDvIHFRpe)@q5xYJ1=*@7E?X7FW2>V0Y*iG?Rz(Teswg2FMTrO~N=!ge5(0{n5>S+k zfTH9C6r~`b=qmz>QW8*Tc`ovWIq&q-$#=A@VIJ`%igJY6UPY*mzxt%~xqRZ#)9Dk{iEQ6U0~3KLLNgn*)=1QdNwKv6LQii#6ZRDyt_ zk^~f$BB1C80*Xo#P*jG1q8|w;`iX#|vIG?UOh8dN0*Zbipy*cuipmpERDs|q${yz4 zY=C%sni=-3Dhih;rix)6@g<6?hS^t&tDr$$yGsmlGTqCRXC^(COF z9|1-E2`CysK+!+~iUtu-G?;**Ap{f+C7@^+0Y$?JC>lXP(MSS{MiEdnnt-A)1Qd-W zplBQcMdJx5nm|C&L;{K?5gbJw!`wd_Al}aMn;!qFqK4)_cnzBz<`G|_XnL6aS7}u= zgX2}vOtvbT#a2bL*{Wy`TNTY^tD<>qRWzTiiWaa{(Ly$g77j5m2<6fTI5hC|W~6(OLqE))7#&o`9ka1Qcx~plA~TMVkpI+Co6l zRsxE)5gbKR!`#CR5N~36E}Eu_Cd#Yp?O`7AC5m>3*~@=aMSD12742oKqJ3;tw4bet z4zN|xLAEM7#8yRz*{bLWTNNE;qv#j`MaKy!Izd3uNdk&a5m0oRfTA-56rClY=o|q> z=LsmfKtRz&0*WpXP;{AqqALUxT_vFC8UaPu2`IWjK+#PCif$25berHP+8O3PZGd>+ z$?xg!Qbh^nrS_dLkN6Tr55nv>WmVBbj#ovG*sAC;TNOQFtD>iDRrHLlik`Do(F?XJ zddXHruh=MhO+e8b0*c-eQ1p&~qW1(8eITIdBLPL92q^kYK+zWhiY!~-wxh^JKv5h5 zirfSgg%MC>6HpXRK#_-lq6h+tA_*w+5>OOHa1`AOb0_=RDDp=bIQLaiOZkrGvpwQV z6a{R%&@ZYe$nmNuE?X7FW2>V0Y*iG?Rz(Teswg2_6(wS;qQq=fl!T3;Pswh8O6%}BsqJnHyREVvL3bR#F5jKj75>WI#0Y$|KC@M}sQ3(QyN)k|1 zih!aY2q-E|Kv5Y2ihd-Z=qCb-$`VlYGXX{A2q^l6fTCXsC@N1tQ3V2uDiTmsiGZTY z1V>R$+dar~v^*4GAdvlYpW|1QazUpr{D}MSl@c)RcgtW&{*9C!nYW z0YxndC~8GOQELK<{wAQP4FN@M2`FkuKv8=FiaHQb^bY|=9SM%2YPS2a0pd+1FNJCwr!2}cyA)sg|0Y$?IC>l;c(Fg*HMiNjoih!cg1Qd-SplB=sMdJu4 z8c#sc1OkdC5>PaWfTGC+6ip$ZXez-`)Y*3DGC;gNBEg@g<68*>>e> zs%SRHtD-qj5m2<6fTI5hC|W~6(OLqE))7#&o`9ka1Qcx~plA~TMVkpI+Co6lRsxE)5m2<9 zfTA4)6zwE9ie}jEjs}SLYk4U&Qx)wo9}C-Md&HM0+GpDne^*8OIbIbVV5_2oY*loK zt%?q_RnZZ)DmuzmMaS5x=r~&yonWKrBmqUI2q-#DK+zcjip~;HbdG?c^8^%KAfV_X z0Y#SxD7s8Q(G>!Ut`bmmjew%-1QgvMpy(z6MYjkjx=ldQ9RiB(5>RxH;3(Q-ySEx3 z-WYi<+N+AD2&wzFM|_E*$F_Z~x+;3Y@v7)4TNOQHtD@&@RrG?bie9o+(JQtpdd*fv zZ`i8nEgMDe2q=0_K+y*Riaruh^of9?&jb{GA)v?#*SGB`auHAzhkznC0Yza16xjq6 zg%eQZA)qLNfTBnOio66AMG;WsBcLdnfT9?Jqv)aS4zFPp$?v;{JyJytbn_8+UKF6z~Shgxkz*a>G*{UcJTNNc{tD+=qRg{#iijuKaQF1nlQV>w|6#+#l z2`EZMKv8M}iqa5Jl$L;^uL&qhM?ldx1QewwpeO?YMHvYw%0xg>W&(<`5KxqrfTC;! z6lEu%=vxAcau86Ili(-{hP%reAl?k}>N;+?^G<)byzS2w?h#+2C~vsktd1(m$MLEt zKU)RZ$VPDk{oWMc=bkQ86}(iW5*&f`Fou1QeAbpy&qzib@ku zREB_}9|iGZTA1Qh*DKv6jYihd!W=vM-Y$`epjfqC7CBfdmYjc|KqJyleb<5f{DwkoR4Rz-E#s;Dko z71d*_qWWxA)PSvu8nRWPSG*zXTL@BA}=cv(?z1ga$4_g)WWviloY*o~st%?S)Rnb7U zDjLK_(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)8bv_SXab7H5KuIhfTD2(6pbgKXaWI6 z6A37qL_pDG0*a;(P&Ac*qG<#aO(&pe2EkF(E!>@=p;0tOo{PGxqP6l{vopgz;!70G z4Y!LlQbqGPUKPz}tD*&LRkV<;iWad|(PFkLTEbREOWCSu8Cw-CXQOBZ0YxhbC|X58 z(P{#U{v)7h4FN@K2`E}eK+$>viZ&2Xw2^?KO#~EeCZK2w0YzI0DB4Cq(RKogb`Vgs zlYpXK1QhKiplA=lQ8YW;UEculc9*B0IjZP`{4tTe;U4iNiVlX`y_=|_LmaP)4zpF! z5wU~Y*qAujiQeP6n!F~=raLDUkE6&Jo>gBMJ@u0;t){eCZH&cfFhfKqHqF= zJOmU)5Kt6JK#`Y#q9_82d;}Cl6HpXGK#`w-q5uI!L4u>`Nx1u|0phJ7&qYsF(S3P! z9oOR#U!o|1#}2koMF}}x6(wS;qQq=fl!UE{lCo7%GPWv8&Q?V!*sAC&wkk@=Mo}sP zic%9$l!kz!v;-7=O+ZmP0*byNpeQ{7MHvVv%1A&_CIX5w6Ht_efTFAf6lEizC_4c~ z-x5%igMgx(1Qg{WpeQ#1MR^F0qWB(n9s|U?)NA0xdYpIqUFC`CJC8?viJ}4?yJ{;{ zRFLCUQ6aV}D$G_zMcAsSC|ebM&sIgn*s7>FTNRaHtD=%@6qO>N=m!FdN)u32hJd0U z2`KuBfTFSl6#Yy5foeU7~Wi!L_tD>v&TvXlT5nrOHw#T0Qw<@Z`@v5jUTNTw~tD^dB zRn&m3iW;(2(VuKp)QGK$8nabV6E=$eBA}=#0Y%LSC~8hXQ40c!S`tvyih!cl1Qh*E zKv5e4irNxT)Q*6n_5>7lAfV_U0*X2kQ1mYWMV$yJ>P$dU7Xpg95>V8Q;3%r;ac?(3 zy!+*CSuIsGO&%jU}LH905h+2`HLCK+!}3iY5_I zG?{>+DFhTvC7@^;0Y%dZD4Ib)(M$r0W)V;{o8Tzw>2XK2Gm5608P-b`WsvV^b37jL zC5je!>)!}A)sh00Y%#gDB4ay(GCKNb`nsui-4lt z1QhKdplB}vMf(US+D~v4&GWd+86e&i@=a{MD!MMuMF%_{@g<6mcWJrfTG6)6g?q0 ziVk_)qYM!5Y*BPr6@4YoMNd5*@g<60dhFGmRM9JrS4FScs^|?{6}@GvqIYan^q#GX zKCo5MN46^Z#8yS0*(mx#K#>)pZ`)DiBA_S^0Yz>CioysevI!^(C!okfKv4t%MUey) zc?l?rBB01eKv6USMKJ^v`3Wcr5Kt5(peQZ@MeztIicfG9J@>fJ8zA2I@=pJSDyl7{ zVk11_OB5xJus?KBMM*eb6(wb>qGW7Ul$@=KQm|FgS8P?3lC6qTu~kuOwkk@)Mp0S< zioPbGC>;Ss-w;rgo`9kZ1QcZ?pePdoMVSdG%0fUI4+kAfTuw!BJE&!rjmS@$MElg;ddAc`m9I;Spb=s9uEKx2Gzq&+)3L0b3O{WUHb- z*{Y}!TNO2CtD+`sRrD8I6*Xn6qGoIqH7B5`1p!4Z2`FksKv8P~ivA{`s0{%{Z3!r9 zM?g_~0*X2iQ1lN0MI8w!`j>#BP6QNnCZMPb0YzO2DC$N)QFj80dJs_5li(<-6X9ND zfOy-=pD(JbiUtX(UJ)MgC5rk**oS(nqW&DOiUzP%(LlB;8pKvbgW0NR2wN2mWvilL zY*jRzt%^plQ8bc(qEQ4CjV7RI3;{)B2`CyzK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@ zD4Iq<(R2ceW)M&`lYpXG1Qg9CplA*OMRN%#nn!RH^@(slH$c2+T?S5HRWwXU&5!Vi zFHy8O!j9KZ6)oX-RkW0?ik7ie(Q>vbTESLDE7_`O6k$|F21Qcy1plAyLMOz6d+D1Upb^?la5Ky#}fTCRl6zwLUXb%BJdkHAo zM?lej0*Ve0P;`)hqC*5n(ZUFKUIWBi&djhys;G*5M>`zh5nrO{c!d4i09AB?<5kf~ zwkkTsRz;`Ts^|<`6`f_PqH}Cjbe^q>F0fV6MK+2q5m0oQfTAk|6kR2t=o$e<*9j=P zK|s+>0*Y=CP;{GsqB{f>-6f#t9sx!72`G9%K+!`2iXIVA^q7F6Cj=BdC7|dT0Y%RV zj-sOx?k)z1`CT*v=a?$0C4boHMTAFuiJ~_V_S8YD=q<;qqIYan^q#GXKCo5MN46^Z z#8yS0*{bLZTNPQ6`o3Kix!5R*LqL(6fTA!0ifjUk!U-ty5Kt6BKv5(CMP34mq6jGR z5l|FOKv4_5*$UZBHTL-5btVv`gyI2 z%F0L-=@DO|C|RU^YltdJ&he@!1zQz;#a2Zr*{UcNTNR~dtD-b)Rg{*kioRy6qI7H& zeM3M|dIE|v5KxqnfTBzU6lEr$C<_5aSqUi0MnF+^0*byRpeP3cML7v5%0)m?ZUTz( z5K#0T0Y!NUD9T4bQGNo73J_3Kkl-jv66y91HHu!!JN=}Q&O80|p*L)i9`PlLzK^ss z4Od0QI9?SMXRD$TY*kc}t%^#qRnZS@RaBa-ipsE6(T{9Z^b;FJWeF(ynSi2l1Qh*3 zK+&%R6qP5Sr~&~+6$vP+L_kqx0*a~-P*jzGqG|*b{YF61?*tV6K|oP;0*Y!7P*jtE zqFMwL)h3{*4#81WB+~t>0pgu3Pd`OfQJ>Hown&fo5=9Lo?N%dI(VrZziW;$1QDe3$ zYQk1Uf3a0jQ?@E<##Tkm*{Y}oTNSlrqo@@DMXd=a`kR2FHUt#4C7`Gs0Y&WzDC$5! z(LV$fbtItZUjm9c5m3~bfTAu06m=z_s2c%A-3ch_K|oPY0*ZPOP}G}%qCNyiQT<5w z7z4!HTb_#=sG{!XWl~t*NRRjuMFS)4HKSG0AdXi>gW0NR2wN2mWvilLY*jRzt%^pl zRnbVcDjLOBMWfj$8bd(QSOSX15l}RqfT9Tm6ipAl{N@h7C|fmE~>! zqDYVU5=F}*?N4J>(Q=MgMJw2I8s^|h+6qR(tq z^o6a8EU&(ES4A$iDvHBaMQ*k#3S*vZfFd6OMbQKl z#Sl>BC!i=mKv9r@qPPSU#Ur37J^@9s1QaD8peP{$MTrO~N=!ge5`v@XZKQjN0peXC zuZ!NPqQ~-Fl+^1HU!v$MuYF{SDoV-mswfp(6{TjYqBLw(l$NcEzGkbUbZk}h4OLSs;Dem75&UsMdjEi`h|d^UkNBG zPe4%x0*WdUP*jP4qRIpmRUx3LDgi~+2q^lEfTG_CDEfndqUr<`)gYj#CILmY2q>ye zKv5k6is}+jRF8n7`UFQ&F|Rwn0pgXvsVJ(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&> zECPyV6HqjVfTFns6wM=`Xg&c&3kWD$NI=md0*V$BP_%^LC>rE-?>0cZtK|ocgH=&V zd8fbB>k(g~XrSyY*nY0|XQuB%tUJ z0Y!%iC^|ww(NO}5juB9FoPeSe1V_9Il;<&-~nebVa@U!v%&*Uqv) z6`kXFRdk-MiY~BK(M7f@y2MsRm)WZ53R@LjWvilVY*lofjiMU_6x}4C=oSG*w+Se^ zLqO480*dYtP;{Swq6Y*NJtUy$5dlSy2`G9(K+#hIik=Zr^qhdA7X%c&B%tUO0Y$F~ zD0)Lc(OZI}=(N{e!2t1YkZ)pVRMBbq;n6#Tm%&5CZH$}0Y%>tP?VQ|qI?7t z2`DN=Kv7`=ii!|WRFr_C?+GX>MsO6RjB;N#K)eC@sbi`r=be56d8u7I z$|Jr+(GOAfmu0G`G{>u=GHg}!BU=^y#8yRR*{bMgwkj&eRz<(CRnf0(RaBmhq6!2Q zRV1LO5&=b(2`H*UKv7i!imDM%^cw+1zY|dO2LVOZ2`H*TKv7KsifR#1RGWaJIs_Ee zC7`Gt0Y&u*C~81JQ9}ZX{v2q^l8fTE5B6#Yv; zQ6~b5IulUTg@B^21Qc~6pr|_mMLh^8>PbLRF9M2s6HwHLfTF$x6!jyZs6PQk0|+P@ zNI=mbf}^NOl)H%m;yo?DjsKS_^2v*&!BHOZC5nbe*#lRrq7fXgibk?k(I~bm8qHQk zW7w)_EL#U^Y*jRYt%@eHQ8bBwqR9jlO(CFYDgi~)2q>CPK+y~Wie?f}G>d?u z*#s2LA)sh30Y&o&D4I_|(E`?Ue$ohWcttD;h&H*8TJ@g<5b zMA-?~tD=h>uZk|QRncX(D!Rf}MOWFX=o(uUU1zJJ8*Ei{ldXzwu~BrJfTBAD6x}7D z=pF$@_X#L^KtRz$0*W3HQ1qC9q9+6tJtd&%839Gl2`G9&K+#JAie3>=^qPR8Hv|;D zC7|dX0Y&c#DEdHf6rGE57c@Y;Rpm!S=T*^GA@woJBfdnD<+E#SR7EbIzLQr)aoDQJ z%~nNWY*l2lRZ%!w6?xdID1xnuBH60Q%SKTY0YyFnilPZ9iXouLPe4(CfTAD)MR5rz zibp_Ed;*GM2`EZHKv6;hiV_h}l$d~`Bm@*CC7>u70Y%9PC`v&<(N_c%r6f3tK1aEG z7$DvP@+W4$sG=O^V_~U$9`PlLzV_KOH>;v_9IuMLVXLC_Y*mzjt%@?TRZ%9kD$2}O zMOoOYC@WhPWn-f#I{`)C5>S+bfTElP6y+kIC^rE`c?c-_j)0=P1Qg{XpeR29MFj{b zDo8+4Ap(jD6HruyfTE%V6n#%XQ85CFiW5*&f`Fou1V>RCpL?$X;w>l7MQMG`JN=n5 zO8GqEOBDU+v+r$HML%)8Dk{rXML)AuQ8~6M`h~5Eer2no@@!R9fvt)vvQ<$fHi{|} zP*jD0qN)TGRU@G2Hv)=&C!pvL0*a~=P*j6}qM8I0)gqv%HUUL-2q>ycKv6vcis}x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3K zh7eFRl;9|8=5tpvK)ko*r;g24(OVhAd>-*7ibnbDw!2i(XpUD!W7w)_EL#U^ zY*jRYt%@eHRna82Dw@nzMN`-)no2;?Gy;mI6HqjRfTEcM6wM-_Xf^>wa|kG!OF+>) z0*dAnP_%%6qJ;z$Eh3<3F#$zO2q;=gK+!S+ik1^lw1R-5l>`*6A~=dh_}mi=5bt4m zr$15^{T_P5=JSXzQMAryZ`h-X)^ofn+Q3#t8`-L86I&H+W~-ttY*nRnc~~ zD%!zD(M|%2b`emtn}DJ{1QhKhplBZfMf(XTIzT|tK>~^n5m0oPfTAM=6dfg?=okS- z#|bDpK|s+-0*X!%P;{DrqB8^(oh6{?9Klhv#^=6jfOwC~)6ZH}l)`*0?7Yt-zC_Vw zpY7VOimq_HD!R&6Mc3G>=sH^!-C(Ptn`~8di>-=ovsKX@wko>IM$tV2itZCo^nie( zhXfQoBB1Co0Yy&;D0)gj(K7;yo)b{?f`Foz1Qfj@py)LLMQ;cwdP_jjI|7Q{6HxSl zfTE8C6n!F~=rh4lbkXNdXMlK{%b&Zxq>5I{bI}){M|_DQceMS(K~)qM{r}(T+iX=7 z&Q?VpwknEXtD;D@D)O>bQ50Jh`Pix`nvJ3u0*d?u6a@$<3KCEhmw=*p1Qf+5peUAr zq67pKB_yCI5dlSs2`EZJKv7Zxijomfl$?N~6a*A~MLe`TNPzutD?+oRg{ITin6j* zQ8uS+jfTG+46y+hH=sN<6@)A&#kAR~51QZn@pr{}LMTH0` zDoj985dw;e5>WI#0Y$|KC@M}sQ3(QyN)k|1ih!aY2q-E|a1^DBcCRo%ycq<}H>zl{ ze0wVs?Gaz1=;vtr#8FjLj^kC)FKkuxD_a$nXRD$LY*kc|t%@qKRZ(TODyqU(MOE1- zszyN3Zv+(mPC(Hg1Qb;#pr{4`MKuX1szpFiZ32qw5KvT?fTDT?6xAo7r~v^*4GAdv zlYpW|1QazUpr{D}MSl@c)RcgtW&}skPtoqT28cI~JQtN!Me<{!u;$So@g<5{N85={ zsG`3)UKO=rtD?4SRn(5HirTYPQ3tjv`iHHGIP|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9QC0*VF_P&9~uqQL|d4I!XtC;>&o z2q+p(K+y<-qo`%HyRZS`?JR%px|J%rAkRf3qdnqF6pf9xYn@U><2YUwjc2Q(32ap~ zk*$g*u~pGzwkn#!Rz*|Us%RQp6-{TOXa)gAGYKe~ML^MP0*dAkP&Ai-qIm=q%_pE} z0Rcq|2`E}bK+$3Xik1*iw3L9NWdsy0C!lBr0YxhbC|X58(P{#U{v)7h4Z%?~I@;aK z0P((*pE{0FML)=^>$TAy@g<5jM%%N`sG?0AuZlLaRnZo~- zoorRKi>-=wvr)8%fTFzw6zwCRXg>i(2M8!SNI=mc0*Ve3P;`WVqN4;99V4LVH~~c` z2q-#9K+!1zicS+ybcTSUvjh~KBcSL!0Yw)GD7r{+6s?bT?>9iagXOpJH>jdEJ~J*w zd&HM0x)yCeIH!uPbG$0L!B#~#*{bLkTNT}AtD-w>RdkoFite#h(S5cmdca1}LjsB( z5m5A)fTAY^6g?%N=otY;&j~1cK|s+<0*YP{Q1qIBqBjH-y(OUN9RWq}2`KtNK+#76 ziarrg^qGL7F9Z}>G5W?FMJ|G)=t{IZaNa1oD$hk%RnZ9fjut1zBfdmYc#Qq+MOEbC zcvTd^Rz;C)Rpe!>qA0d1^08G>G+PzLuvL+tt%?F{6a@(=ic3IIJOYa16HpXOKv4n$ ziV_k~l!$<$!~_&2A)qKJ0Y%9OC`wL1Q3?Wzz9OI~B>_dL2q;QTKv5b3iqaBL^fduR z=?IRZuo!n01H}7MeoxRG5IG zA_No_C7|eg0*ZS*{Y}#TNPDitD-7wRaBL&imI_y z(Qj;3^gA0xe-Kbqoq(bm1QgXIpr{rBMYRbiszX3gT>^^g5l~d0fT9Kj6g4EE=uZNQ z8WB*`n1G@t1Qh*6Kv7cyikcBn)SQ5#76cTvBshx7#kj8cCb-|FBh2N46^Zm#vCAu~kuLwkqnvRz+ReDC$N)QFj80 zdJs_5lYpXL1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&YzXb1sCLkTDvMnKVU z0*XcuP&AT&qEQ4CjV3sX{*G~{H$c1}<##~ZsG`R5>UvC!M|_E*2{Cq=TdHUx$E%`A zY*jRwt%|0wRnb(oDw@VtMbp`;Xa-vq&19>hS!@)|CZK2z0Y!5OD4It=(R>1m77$Rh zkbt5^1QabMplAsJMN0`NT1G(8asrB05Ky#|fTC3d6s;zp=syCA)(}v%mVlyl1Qe|& zIEu!_xSJaw-h1-qe!MCwC}Ts6M|_E*Eiv}cJE~|a$E%`kY*nRyX#$GQ5KwfMfTD8*6rCra=mG&n7YQi3L_pDH0*bB>97UUA+^Y-_ZxeZSy;&7y zmvJ@5Bfdn@%^3UCJympz<5kgZwko>ARz-K&s^}hD72Rj6q6chM^pLHJ9XJO z5K#1#fTCvv6g?-P=mh~qF9|4mML^MO0*c-cQ1q67qIU!oy(ggP0|7-J2`KtRK+$Ic zioOs~Wcl@NJBnNc6vZK+$W1^|7{O6=J;wds0P#i%oExfWlMLJM5nrMx(r+hysEWKC zuZp7Bs>sJyMbT_k6vI|UezqzKuvJlzt%~BZRZ%=PisBPc6iYx+0s@K>5>S+gfTF|% z6eS^`C@BF&$p|P)PC!u#0*byOpeQ8)MX3lVN=-mf8Ul*a5>WIt0Y&KuDEfwgqVxn5 zWgs|;Jbrgk1H>C4FNGrf&O7~Eam>i*_lPf1l+|z7d8~@Eal9(Z&Q?X=vQ<$IwkpcW zRz8qVL$MC@&jD`3NY=Pe4%t0*VR}P*jM3qQV3e6(OLgC;>&^6Hru) zfTH3A6qO*Ls3ZYJr3fhcfqeihd%Xs4M|RKNC zs;CAVMKuX1szpFiZ32qw5KvT?fTDT?6xAo7r~v^*4GAdvlYpW|1QazUpr{D}MSl@c z)RcgtW&{*9C!nYW0YxndC~8GOQELK<{w6qz%KP014G`}L`Pp>^Rn$lXP(MSS{MiEdn znt-A)1Qd-WplBSyQPj@wj{CwW%557s?Nw1ddD}nU?-5_3XtLkV`AQW{;doUvm92`V zu~pG@wkn#zRz)+}s%REl70qU=qB(3;G?$H{c?1;AC!lBn0YwW5C|X27(P9FMmJm?1 zlz^gT1QabNplAgFMJov?T17z7Y66P>BcNyv0Yz&GC|XBA(Ru=kHV{y>k$|F21V_{(`MUzy~efbgOX1_;#iK6X(`=2+eXa~ouqMdA2w2Q5ZcC%H{9=0ml%T`7E z*s5qhTNNE(tD=K!6dfX<=r93AM+hi7NIbb)}Piv$#1BB1Cp0Yz5`D7s2O(KP~!t`i(ZTm9}S28ef*ye-?Niq6S% z(G9;xe2JnvetXM1Rdko*Rna}RD!R{BMGx4j=pkDbJz}e($81&fgsqC6vQ^PDHj17T zQ1pU;qL%~|y&|CKH33C$2q=0>K+!t_iry1Y^nrk)j|3EbBB1Cq0YzU3D6#_jwjD(- z0*c}gP~;|{D2#w2n}DKl0*X8YN6{_6`=$ZnbqSo?s_2S57exd-;!70y0=E586-9Hr zDvDvNB0pOd1=y-6$W}#h*{UcWTNTA;tD;!8DoVgcQ9=TW5)n|8n1G@r1QaDDpePvu zMac;$NQCb3uz9yh39RWq(5Kxq!fT9cp6lEl!C=&ri znF)>}Z@`_=0P&UJU&=mw=*r1QgXLpr`=>MGXlk`jdd7Mg$Z!CZMPZ0Y!fiP}G!wqGkjX zH7B5`1p!4Z2`FksKv8P~ivA{`s0{%{Z3!r9M{pEX3b_9>K)fmCx6Uf7q6+d(zkR?X zzC_W#0sBlGRn&>&RZ(ZQD(b>kMP1pds2f`qb!V%h9&AljT(P#pS#t=|6 zmVlyh1Qd-YplAXCMH2~*qJIMJj|PbMsQjR@qbmAYo{J_0JmO0fO$*q`&0hx*dM=vI z@v3MBTNTY@tD;$KRWzHeisrCY(OkAFn#Wc}^VzCs0UJdN2`E}bK+$3Xik1*iw3L9N zWdsy0C!lBr0YxhbC|X58(P{#U{v)7h4FN@K2`E}eK+$>viZ&2Xw2^?KO#~EeCZK2w z0YzI0j-n|6cQFIRTSK0HrmCXk^5=`T1w7(Q6zvMw^*pL*H^-}@J#1C9m#vESu~pH2 zwkkTnRz(Nds^}0~6&+@)q9be+9VMXX7y(7c2`D;2K+#D8icS$wbee#oGXxZ!C7|dW z0Y&EtD7rvE(M1A^E)h_4nSi1z1QcB*py(O_Mb`-^xWJxfTH&V6n!9|=pz9|p9m=WOhC~W0*b7lzHLX5i-4jy z1QfXmC<-H>$R?mDoPZ(^0Ywo66h#tHV0Y*iG?Rz(Teswg2_6(wS;qQqv2q;QU zKv4<;ioPPCC?x?!sR$@aO+Zl^0*cZSQ1mqcMd=7A`i6j_^aK=TAfPBC0Y#YzD9TJg zQ5FJJX4!Yy}jG`{`N3COm&O80>@?4ZX=n-F{C|A(V9ixhJbG$0b!&XJ# zu~kuCwkpcURz>;Qs;B^46%}NwqC#v{RG5vTA_No_C7|eg0*Zvl_j9)X99}K5m59C0Y$$OP*k3Pq6!2QRV1LO62VcF zBk2C!0P(hwmqIyJ(Rq2>UpeRzU!v%@p#5(^75&cfs^|~4Dyq&_MK#!}s3uz#)ncon z+H6%+hpme0vQ<$%Hj3&KP}G2cqJ{(%{YgMkBLa#V6HwHIfTF($C~8VTQ8NOHniEje zf`Foy1QfL*pr|zgMSl}e)P{hfwgeQlBcP}~0Yx1MDEf!sD5@HCPcuNg9(gXRri!Y| zceIW{kN6TrU4r(uxT>ft$E%`lY*o~qt%`cERZ&m2D(b~nMZMXos1I8e^<}G~ery!= zC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)8bv_SXab7H5KuIhfTD2( z6pbgKXaWI66A37qL_pDG0*a;(97Uai?%M{4_m({UbXG;hT{^fTHCD6s;hj zXe9wfs|YAsO+e9q1Qe|yplB@tMe7JCT2DaH1_FvU5>T{>fTGO=6m21(Xe$9l+XyJy zPC(HPf}?19(4E-;@h*~|I?hl<<>k3(XV4?QMA6=${c}Q9w2$Le(SEinI>1&%2idCV z5L*=;W~-tjY*loWt%{DZRnc)aicSzvbdrFgQv?*9CZOmH0YzsCC^|<#(Rl)jE)Y<3 zk$|F01QcB+py&z#MOO(Zx<)|JbpncR5KwfJfTCLj6x}AE=nerzcL|Q7-9dM21H@Zf z{>1DaRrKC`EbLy;Bfdn@qo6%9u_}7Z@v7(vTNOQJtDqGW6oB`2UL1p!50 z5m1zpfTC0c6s0DhC=CHcX$dI$nt-Bo1QdNkKv8-EiZT#Tl#zgh!) zl#i{7^0QS@0k$eC$W}##*s7>7TNM>ytD>T8RrEa@Ma2jxDo#LA2?B~r5>Ql%fTAA= zC@M`rQ5gb?ek7piCjyGf5>WIr0Y&8qDEftfqF)IpDo;RB1pQl$fTGF-6jdRh zs4Brxlsm4wgaP8sByjSmqMhakT(eYPrUz*a>K*(myxfTBhO6g4KGs0jf@e-TjBlz^gU1QazVpr{1_MJ)*^ zYDGX%YXXY?CZMPd0Yz;IC~8MQQF{W4IuKCw4*^9T2`KuPfTB(WN73(b-2)5|uUp{! zp^Bp9ujlI=*CW0}QTMp^!qlp$2gj?To@`ari>-=!vsF~Ts;EC(6%Amk zqJeA_4I-duFabqF2q+p#K+!M)iiQ(VG=hMlkpvWtBA{qA0Yzg7C>l#Z(KrH%#uHF9 zfqk(g8j1?y= zO=Qw^F3UgH{Fbfd-zPs>@;@*?4T$hZ8*e^;HuLQ;;4dF-S@Hd&{g#!;e<5gD$^5C} zTUJW{p9w50t$%SM%S!Kmk;Jkx`|~BYtnB`-Us+Zz|E^S)mDeAY*0Kuv%crxfqW-bz zEvtn8Qbx-v?N5`%vda1!XS1wd{Y$^KtV;e@IW4Q2zd#<#s_yTe*RpE+_vE*%`u^xb zmet5#v4~|g^^gDFvReAD6t}E4{;x|}RtNuIr7f$IfBBD=)y@B=tY!7`7y8Ar`uTg7 zx2!?_eHAThnBQN;vPStUSF@~f{)xX^)+GP6>XtRl|4l8+n&od+$Fk=6SJtzvMgDgU zENhv+NF&Qy`%CdI)C;x3(d;K@sTGl~-2J=s19QC*8 zXjv!yt2c>hIgrvTphh^|q|L{&@W?>!JU*0haaDKXs60z4YH2 zVp(tfnTA`|$3Ux*=J9t0){Hiv09WACSo0Zh1&U8Fp8{8)|0MG{a0QM`F`ooiAa=U> zEVu%H%ru_{S77>V^LcOuk7y}N1omlkbh4)vnwF~AaHh9K>kJ7T&{rplbm^7 z0r@u-3%UaGkKz?|1>|2fE8z;rKTB2G6_9^dsH`h+Z>#y7xB~JodsK1-m8-My`PT{jyD60r?9;Te<@BH$1j+1>~>j>);B=-?7%o z6_CFqtD7qzf6GxXS76gs^BHmll0XNv?qW z$CA@r0r{`pX1N0LpDWFC1?0asS>y`He=xAj6_7viy~-7kKeD^l6_7u3xzQDnKQy=1 z6_7vmw9^%kKen>h6_7u7aL^Ty-#9+%3dryLopc4{w{Fh50`jx>i>`qD@bs!HAV2-O z=?ch?FYdYm^8WLoDXAm75@x&rbX{Ly6v>&nmeXE|STaof1eCo`w{ zGBTgq!seHg_SSJ(@gAE0iz|1`P|5L(Jj<0wM{oJacRG%{&BzY^5^~bQI=(eu)UF~r8kz%LMV%3w-VC{| zvER6?1g>9g-_qBvzZ1C1hX=>J8aB3L0#^mwcQXF35eZxs!-Fes@9EpoiZx$_)+uvL zW{$aE-#owx%b9##PW8KKz&86lI{4m!%Qszz_p1-7C=o8YgZJls=?0nD1->+iD<}ioI zW4E5`l!#*`%wyt5`D|1%zmN-_=YrLy4K)|6X>#a-P0TMuK!OY^Al!AVbm)5P+AXab zx@QNryxnL%f#!m3RvpM@#db1>MAmg#nVdu1Uh@|)#P-wk)Z#pG3Lj_@dWg;pUi!uy zZXTk!-A62RPPFT%YJXUbQ$KTFD|W3pMDF8e4yhOY#N5ZNCWr3hK|SR=K3@D-#~%b02T4 zAGXE0ZOwjY|Bn^>+#DqLu^MOUWX|+i&oq!TjX1FNk@Hzj?0-@@bc?EPyY^M+7QHAo ztAZ7q-+aTC`#8fn#P+>=o5bA5VkU>~V>$B+`8;0Zlut$sJ7K=q%#Az0=;0~n%kIUj zWmB9lhe>Pho$74G);33po!8vDafVDMy;QV$R}*?t$o@lBbE#fjYM5TCtn=~k;Qcq} zN1FR=E_Hgro=fIe=5d(1di#M6=JtmNN4)#I=U*#!hF+?UbClbg(lDK4VuZv5e0qu0yVvhAyR#gp8MO=OOd zPhxWC7`NB_f@+t-i!vO{jW?OQp2L^&%~{uvc{ zFjF~)IA8Ub^*oiG7#{3X%ATT?7_o%$2azh5d3L2T`Kbwk(LcyaN$PFCy~y-stkBhT3r zObmT7tT(?9B||u2-8x^)7sGawL-*{k`GwrG{d_#}$287oFYDg4xk49Q9JV4!=z@=r z-P~^O*j00geD~Yyt;wN#nO#r1l9LXfJbj4yN;fxe=ZZxm%#(|Gni=wZ-W^dI9^CVO z*d_BdFTb@ZUk-b@eeyNmPcL=l|6ghtmzt!PN@~9Cho13vHvLdP^ch_EaB+pu<520y zhPo#=k&?L0{x>c8Qz^CZ=0z@rc5Y2AE1 z-0PFyT)eb-F({AcPL6TD3;t?y=<%#>ej(>{eXDme*}t~=DliY{<_QD(J720x=bSaK zG0csd|K`9x&_*t_S1;7W`M5d%=~+k3r^{UF+WOJ= z<@==VYg)TfWa!2xt#qKe6?@(sBM)cS|Gm&{J<&=ol&#%Pc`0DN<7|JhUcRN-zV@FM znpY|277u(ea+6_AZgJF0_L`b2S=?v zyFhT-!R|LM81V(oA@XR}cMfsP4AblU%XysZjN>}9^g8RDkB0}BkA5$&qRefdeBk~= z$HIrlZ$sZ`Y~QtlRcl(Y|Cxj2;XM4mSK6*;a^=)}w5`L`=Ajeay>MZ!d_CE|xr3w1 zh8~0thc=`(uZ+zh@@OV-4spKmo!0aG=tT3RKXLw2`NFh)J=-7oHgwk?zU{d(bk}{g z8kB8fp5M(e@@UrK+Ritm_a=uP&2X>tXinkd{r7!eD0JJ79qGMKKGosDJM%W5H+R>7 zKiauKG4oy793v0sN^YEd=gV&1>&S)nb0X(Lc})&osD$~2eA;aDpQndDt!ZDMN*KEB z6;jtRxXfcvZ*#WL_p9KPCzlM(D&`1zER#4#IN$i{>S=!FG&|}RHV(~0u)c5!bHmNe z9XjUaUFX$q$vDs3Sh4b#y2xW$m-EQ?y>@z@F-{B*UO6;sgL%F*C(1KpguL9feG69< zj5c@Myvp1$?}d5l8DWl*ySSKZJKrAU&rgT$;v7BaJwCp@WkTnascNn;PiqzI;LF3k zoEH(pF1`6+u&*_T$V2&=+a}*0KI?U2bL&IpTqoSTMGajiuK9⋘xd|hX;2}TQJ9b zg3Rmc6`#k|3|;8>><0})pR#{;Mb|a2nam;bST=MHaeL)D+4Vf*^g6*QXZOpKo$YJ1 zKGxh!^AP;GH&M~hX?DD>-qwoEYmShIaxtfoZ$c&XG*|UBzT7jaWeA<7^|UJ0LZ|6j z)ca%Tkz9X%<`?r8t-d)#9?3Tx;=Gk@YI5ivcFOTmp)r)9?1db5P1br+Bw8|Cp$;4Q;YLB?_`&7o%MR1NqoHBnTplTb;5%u z22C2{Jki}MamD!tH0Jfm%SORLz0h(lB=2N1n;+cC9oox@QtmuqUOD74Idq4LnqSDL zEbKeIL;JhDYZkggGbi*)7rH}x8-$tH66OvKKC<_ydF4>S93r2x#LgjZZ#VN;*VOa; z%z56fF4H)4o}8C6lr-lF5AN?acZ~C$`Q7|sE6p==Lvu{XKPQ@HPSjdYG+Iv-yx+fH zo6w1Nx35QoZ>V|oL=&7C z9-PtV_~_6VlCN5zk#mc44gW4r=s_r%u!#8zC~6Lo2XiUsk#BQl^*q=01_d`ioEUmX z5?nZb-S45>({Alf^S#O3@q>#`KQni{kvT*j%y)W-&w09RX>#a3cG6Sk$rpMI!h_4^ zPI+mb)y$W`s$Lljg+4($7WH0XZmszQrOG&}viSs=W8}g7$vMV(!o02*s_R5sFLa*^ zz19m&<>OyPU5FpLPKo&a<(*G>@Wrz^3(SLIZv3OkpN5(5rx5|?!Cdvf7m9D9d{*vq zqB4J-C>;8%%o}=ds=4Xr>2Jb@cg|8-^`C>wIAy*c@%XN1rywh)s8a&>eOzbX`yMofB=} z)1CX0gdT@$9wk!A$3*)qb31oSKu4d3AGwxpf82LGlcJpIbN2JaJajE4d2lC)@e) zN^P#xRIgN!kH49o$N4c?&sCe7n1{jk-CuXZ{K9wF6e{ z0&|2Q4i?t026;~SPft_QiFUA0zZLTBDm=JvbdL+p{cd}+ocRf!@%Ciz#2e=XgGTDNpLw=A5=Kb-@kJPhhVdo4wWf3Y$0h%~NyEx8@jm zFqd%S%Gej%SVR}uZJ&O6%Lc{}y_@uK(6jgQQJ_3O}s zuxsmT^H|n5hsa}@z&XTuz1C9CQ-<^8@s=nOy1~0TRCHdlmS3{ayb3Un!JE}zdYG@d z4(1SfFl%xidBN68&oi9!l((zPyKeKQ>_-3d&h6>k@PawD`J|jryfd*CJIx#-cX1wv zI8U(iOb*?}ReH+X&d1FUA0O=P>%biHW$R$`7@ALX(%DI!FO_l6HZM1?0(YB(r*lk*$)3&f^|3IW}~jA@deL4xK01Yy9{c=GCwH zU08WA7jhnXdM#n1+@33(XKmT#=7p(wFrPk|8+vmW9=vsE>QMOxYWt24XeA@Q3Pn$Ay(^Wk5&^WJ5MaMwRwkGn zy3ic+3wb;%@$o;;7ja&`f0N>%`H83TvF_pBSD}Z~m-Sw!ROYRwIYb`L#{YXA^R*p1 z&qU6Xs+!Mvt@VHGoe7+kWB>op%$YN%rfJ_7H6=-^Y1)g@CP|yhzO+vJrp5MHl8|Jl zvQ!F@B}s*3i%51QWJ@SQ2uYIv_j_NT_ssD4{eD8v|9O5t^Lo|id_LE?mixNj=f1D| zK4<2Xul%$fkZcalxpVl5(Qx~gdAYP*{#Xs4%SANf3*a}^%tthnIPQqy(Pl57efw&g z02|M{@9lotCcw74=Z{zB+6_&s<8%2Vb;7xBx5d#W7OE76)}n(B1jWy~w_nueWwWM! z5!$@q!Ye=W^JjX=dnPV<$(X5Rm3%V0g-YRMH_AfqDVLT)Pp4ZP^)yL6%?ssr0(t4K zr)=sB&Yj<`w!@&!LfX`$ZG)_%?N2^6(bn(RSskCv2Mcy|iyHczj&@((E*u13`ry7j z0nVk*{q%S^rR;v|tIrJ1JFSvWXv*Q*|9-w(qL!M5FumlmXJ=gEL$VXz$1i?q+iWxX z%x5dU@TL-(Z5MYf7AyOTRr2lZ8Y(3+!=dv{i=*xQNR3`f`LfqH+O>_f`S~>;&G9x9 znJ+(nb$GG&+%~1GEgr3k&*y9g=ZEM+D~EoT(oX27gT+xlJ?w$Q`E@8yFM0I^6MdOu z^I7$Yru#+x44HqI@oGbFHKFzyv9kTGice>HM@@qFGfM3=4`Cv6+?rLbqh>awon=?O zHr&iA%TD%YN?y9|(lK^d$7=XocBL6VLQhgN7tqYy{mEqv#+ zIvs2#t%e_-KVfJu*x`A;eTv7s`I%CBcf@sYn0_v{m^E+?4f6u zT;W6|GG|?UMR)5cz2p;Dyt>HHe8DRDKI<7Og#${ds-dT$A>@Ek$>OM|TK2$ux}Bbu z-1^Cde#%K?Hapb*l!kY7*Q|xMbh9nme&@T@>~v^Ve4i~Z*iQ$w^9B9PoX|3y4j)-? z_lhDPg_)bf;Hy-U~PdvkqD95XvCLv5Ox#^8dAGJMX<9R)! zpWQFE@eCWYt8vs$k-5_kij^I2ReUnLgeqL=o?~&eiBr_%r8N19nP6N^L~ zd^G*yn=G=iwY;kP!LhP8TAhf0#^$#=x2dD0zwBrS9i>(abNLnJ9~IvikA}YHsTb`i zVnhG(hudtaY294hrfREL*)mqcr!sM*rog+&QZvm%n80Q!I@5|7Ay4SsZnAvptCT?;OobBJ<4>J8VZ8{;y8DXLmRUtXs1FQa`WQ z*?#S{yX=6v&?@<4_6(K6+IhKJx+H{lQ{$V7JDew5^gedyDtlzp@KK4f_8zRYbnPc= zeFd`8D*1HYOiR9cen~C8%$VvN)O$#@?MMG(fE`!tXmZU}bEk#{X#DnrkGJb`tKyrv znJVFcx!vMuGxw;;nn&qne%qF}F9;`&Yrmgiom;cH z-B`6MKAm$5_A_1WydFaP6wdaa{jDq`;D);o4cFx(sxPvYna$?v2j1OdaL%?mKAT%< z$PdnUsiFP4Xb;CXPO_JX?Ur|TT=bY7fNZyHdwT5=(ST;wy1_1J*H{(b#>P|$Hz!`R zINHYd)Z}TD@Av5u^`j>5xa`Us{19Y|qh(jUYWv(a@`KZku#eV!Wp$$K|4=8M;rAx0 z)(9QVqM`6IsAX}~QEPkP2Zu+fmx7PFl=U~ z-uBS?b7SR?wK~x~gZ}owchA9H1;WcOFIZ_i-KMqs_AB>`W@A~;CU)+#k+-h6#QK|L zReUzug(~dvsTN0roUSI%r^)rpKUfv^RK5M|H)eb`-g@h)t^N{9WPWkbG~4BOS{>i8 z>q4D?);4u?_b)rzK}WCbAI83wj;?xi^V9(G^4B)K;IFXsl6#iUn;TxNlUMItWp}wZ zSuLmQ=U;TCrW$qAG(5HY;}3lGlgM1(rMj&~t)*`--*rP6^LMr0>uu*(tK)Qa3U$Ie zW~nv9n9il43#MQ3l{aK({P{cPhFAUTpT5~M+8cMw-892)eoeMYKBL!#O7=O5=;~~m z#nFt;RHLs_{&lf;ZINhge!2PW>EWRCz%`#w3@_FbKfmM%!`$jPUz-`7U!0wIK0IgZ_to3auz4O>ZPuL-AqSf(T*FDq; zC;w;E(V!4=@_&hrHmIZ9=;(*7-_H(=bQ*tay=cB~yYof=5Qp`&bH~?HZJIu}O1|eF zF4)sfwe$r&bv0Gt3vG}_?FoHP?P@1KtK$2u3su50zk$WkbfzB| zn!J?qvTHing_!NPi(kI|dS3_H2N>r!J}w&Ds~=3d-;P-otWI?PXKa3AKGj0+XekYa zjs{sAbu?BTeNFkQ*2Bj}ld$5(B_~AvJT*J>lNyRi@=^1`c516%Z^U8 zING2=_P{r2zRF83eq%~*v_VgSEwQ=&V(E;fw$m!q2|MkPg8kIA(A(KY zKNE*`=^M2Z`*E|)kb%4Q^(QCUna$?<_Bz9Q*?Ut~#rIjfmv+AIv*v22X$TXUbr0PC z)To`5Z!yV_(=J&0`E)y$_O>d%iCw7@mKi5o9BtwdH93{?j~;517B#t` zOVhCaz4zK_KZaNN2W2Wi%8zT1`jm)X{dzYgeAp**dbL z?zYEo4kz^ipMNkSnuC*O-D`IzHd_^c0VI2C4!oc3YUhv;+6s8jJI6=uym8r&bDUe_ zVa=@BVKR@~RIZeLX;2mTK~?P;QI9i=KYekC}F@e$&RqVQ`ncygK>>Z+gky zOSi7G>Fi>){57zR(fK;#Y;~15Mz4V|os;P5Mtk7Ns2jL!HpkIcjJI4SjgQ7ygkpo514be>^stz^2#k zAFg-@eGnUNM`^3#Y~4dU{zAPafJ9U~#mOHSK|KWaHz)B$T}VqwB%}`^THUm}rz)oAdX7bx_#3x7|6{ zPE}2Sz|_b1tpZESiJN8y5TRU;E7c_A6iYrA&Is zr9aGn-_F;W*;1{i;hMO?!!5%k zoi*d(u&{00e#a<#>%waIPOBJdgxkN9)l9b#rk9*_-6so-F5CN4KYsKh=PXh3iB)Sm zMgzX(ndKMRiD#Ns^4&Iomi+ebOtmzf0o7hT+pb%zp&fT`TW^@!6xU83)Z7}fcbSjv z6|imRUaExk+6s%KZCtG;w^F|3>rd>6Z%uwO?dNUYWO~W_9)5APL1t~X7_rD+ z`x~r|zqWs7Z2kd=tOlW@awllALPxbNjyh^=4}3Cvh4S>07hSnxrnPVAPAPI!xCZ_7 z(hU!U<6{4NKW$;ZJz{lyI){WhVPV))4c$mbV`tBcmTQ^CKV4WUnuAV5>e#8l#yjiE zm+INh&k1vRAI*7`z22?ORde2X){fbCSsi}~ zbP09h8NR|ev0>u(~I;Jj*&0X(+2gFagsJ^*5I%G{A-7WO*h?a?HeC&UK!39 ziOdhr>1OM&&(%@2P$wL^8a4`>)RcxoM=dRmHmRdM@J$*|`MMzw+X2lwditX4H-v-n z{13m6eqX}iyy&*&cKkTrDmfsR7VK%DT6!#mc6VUrH<$at%|7?Jalwn>Wzy`aa(+KA zz2vqBSIo6tJHjgY>uoJ9`C)QV<1nT|Cr2A^A82`P+C_f2wU1NY_t`h$)v;*H7wdeF z+6T|R{cvoo>?c;qPjW3or9|e{E$i9o+Bol&vZ}3fRdUPbw|Yc1x?E>}0k`b8>Shex z?3ntI-*2~WzIgS+Wq#;PFS%mD_x={Pjd;WSk-b?!I7NdbB+? z&pGa(=ykGuS6@2}*$i}ev%B5pNoyMBvRbGSE{;lA=)>t9!t|2Y&;0PJ@OoRirJ)^i zY#Xn6?AnV|0W%1Xk(ME0=lb#t>IrYV9 zBkbMo=3#qkoT_Q*z5H=I=-576_|Ws;L2>;-65d}~@zCAUQY+G&ZPC)Xgb}9cM4J9qMK~-T1MiW{a>r zh5Kjka;OyUY7J6P?4gB+wT|lC zH-C-ai?Tg1GjTz9TkE@5m)ZMKuc*py`nmq&FE;yLv-=r^E7|pi4Q$$n-%qp3M&Xz- zBkf(ht*ycY)UzEIefG7; zPxE!G-R@lZeDpg-_ECiG_ph)sN}0h-XwRZ>j%F#H^%}rT#Bb)r|c{PR#!$s+*~85By)Eni+dbDdztY70fiX z)c+;2%nY@b{9ht&#^&07b=pj&czP_QWXb`>N*9S2t6c1u@+IvTv12j2DOjXPYl~vB zc)3`-Sj!@Z6lqc9$kO(E#VRRem7ByoNiUsJq)2!|irHk*SiBI=FH)pvk<23g0rx`X zfAOrs_N)S}X2>Q&Cq>kxS#L5^O-7~pO%_#?dR8&3l*k`P@uD_5@3}@Qd52`R@8m}_bF;_hj>;X^Z(Me6!#?B2PZ&6KboThsqel!F(r@UfaoK|h4CvEu?8xk# z27Ma!Y1p7)PM@3x9@ew4-l)-|a_i;x>p!$!PJ{Z5>UnW}EB-}M_RvuSMobu(n?17M zfFVOi{eK_ExU(jGs)2>bairsX2zwx;~Td`Q!(Ss(88qg@GdHn$~L!r;W z+(G>&j2Pc%{8?ji$JHO=gxT&IICRu_Gx1ogSNp^J*f0mQA3bv9=uws#d;l}ln+{Pd zVejikbjBN{Bod|ntDi(ldVFw7qEx(M{p{*>6N&v3rS?lC(zDacBubgJ2c;9Gs`-QL zMCs^pjjHCVo3UoovlFEvZD446Fj3ZQ=|iJ-278@sZ?n2L zSkE7L<2H)wiRv{HrK17--)%T=qJ1(-Rq^Tht7m)gQG@r{gnQei(o5G%WQnEf+Lbka z!AMp?MzU-p8%9sdYLF=9fc=k8{*U8j-|yDcD^g1D%RReyJID_Vzk6@))sy$tuK%0d z?B6^#?|X8y|Hk%@pE?JpUShBNeS6IHGq)e0OGhthKSA%sQT<;CsmcItpKfAIytUpU?Wv@8Ez zxZby@?(2i=z8byno$CLVC#*kqeYCIU=`VbR{KW^P)QKr&{?e<)y*jo0-<$9M@v3{T z=5Mc_{2wsce;@v%MV;@d|KvM=sptIinDXD>t@M+~Ki#bSW5;iADUq;Mai;?Fmz`}F z-MX{-_XW%!y?y)_p2B`>Z||!+S$`iP^(Mg|xB>icF?Xrwm)7m>8i}mDyY)V_{LA0p zaZ)W^?@v{?!-{vlm$zm9Sgk*DGv{A%c-z}?Mejdk<-bK$(+>1y>L#*G!&@$UzZ2~a z)SqDBkL`|sX{~*BKYw3eVeZwjV&6UaKVXgfS6{##|I4-3pMBSFulCLVz3KiPr<#4W zl=%;s?EjN1JG)f*bLXZ1KWh`aZ@0HAn!j+BkvcAVL+!VK`Fowg+d9AJVDrZorhl(9 z3VeR*4_q4k2ONw4;&sOFVR4^Pm9kGhxb_#_(nuX)i|gOKg|)9%0)Ma3{@kl~ujX&B zp1g053;$LZaev`rAo}z|c8%=lwm|+TR{ayQf8WUc;~&>e9s1jAEI;n~{q;X}Gv!ZK z|5x5s+1mxBe-P`hr298N@)zxaz54|3-#66u{toOuTax@+9gFws9JNTKfSI? z9sYlI?e+I z=+?&HmuA2C6ve(=6#W}rnAvATqt%st(&G2r{rf|AqW``&`>)O-fAUSGf8_=CAMESz zYqLLh8*^VChW1t4emdDl`+cuk-dEd~+D9K(`}-~7=p%Z6{?8WteQmZ^A9VctSj<}f zf5Ej`^?#e+>)cnz%fUze_Kon=qkqT8+Dd0v&HFehH-q-_vlI4_p8PiE>pe$#!pAU8*a9;{MBG#S=C4w?!iB4Kz$7hJ^Py?AI;oShuaB zGky3ima+%?I4sC}!0)$|&8`}avA~ll+RG1k``G{WpAG&4AEMg(^I6_sZn4j6{jR^< zvX?8NeSGgiZ#Vv#1<_xAL*v(f8|mL^r~K9ny-am`3H|be^Z)dBr1Tofdzsr(bRWIY zy(fE_|NT18`+Ho!xz_k2_cr$GrMovz-gkeFD&p>U{~e-zwUDq;{E_+IXT$k-Za8}V z{_`PluP)60lRp3P-z*bTd;N}ere9O-%|h|Fj^KaAQmxVfi9(g_&!0XMJ2X)=UNOD4Y17o~BFq|LJMJqqQ>G z`&F-I1E~J1@#25axU=gOXyCu8U^5hLXqoJTqbj~IuC$+pzA&y-HF{7wQOR4gm1CHY zR*A}*$6BT(vJxfJ<5~6N{l_P4pX^yN{Z5TbRZi9p^ zaewcVt%u+LhOyczhtRu?fsr7hYOtj_U6LIuZyBS_O@1{ zrft>l9a#0f@1jzA{O8ovF80d*`&dwvz5m;XspuG(6%KXv?ImB+Uh#kO$j~HFIKJ-O z@qYvC7ytGe`2zr#jPFSq?}w+OQc|1QUu*7p_z`_NHs};{&1v4CQ=k6fVbjKW51X{l zd)TzOp4qrLSz9VMXdKE8Z?EU%*pr8L89jPTPONL&mFljtXrTs9uv_ zkGx@nf@5x&^9yG?HGdoJ>r^6=+UGTv)1Fb-HmL*0sK6ie{;U3sb%)&k69&iZZ-0*( zoZBaN)WD(rM)esndeq=BB-^jnz5TK50y|biYn(q?gGgJzV4<}^{tjr7wl=-uVzkzP}2^tKFk8Sy@0&Wocz5}0Ip_g4*&wUUZHvZuCg5&+Gt4c`QYW) z5m@t*Qvf}qL*3?08w}*M)6_sfi@c}U^sBA>11)$o$sbQZFWRbn+HwluRsgf6Hjw<+ z0EcOttuQ|A0NY-FqBm*E_Sg#~irBw)08~+t?w|{N7gue25v16D$E9xc`@q)1(uj+O_)1$m?GbqEe?P%_Y)v;ls za)Rh&o{x&3Qq)8qp81H_I>8FZ4H-RleBP;2BqT4Z9?OU|S@^7E0pOfX^KhdCh!^T;)$L5a6?Kdv>psac$2aK7} zYJkmH?wR#QHfm(S_#qQU_BS0gVsyXp_3XAt zU`Q+bHjC4n*Be=XqUD3JRnNYFq16BzK)pdDbH|PAH#oQ6 zh}=IvDNRLRd1Br%}zlQ?ldFR~->OOsbxhP;c zoWB|d8()=m@7OEvWS_(0H-90UzkbbMzS=?cE6)hamJ!tkog+iG5Ac`SpnFMWsS9Sd3E=C3XDmzFvC2TJ(P+xdBm z*u2$g-a@p%3n~BQkiS-BU+1qB^Y&pl^2Ls5-@av5ZGY*s9Xm4X@R9v<2M)Bges8|> zC3-dST`mXx*RQQurhTE!&-PDTP(d~vTNaZMxjz^Wm3wfl#f?PshCnJ zrE*G@l&YyUQtIogdkS>n--?p=lNS5>=R9K%;=d?$AHI=?=fwRhQwsdV?dwuX7V!Sv zJ!Q<>cYx_9l-t+$=6NrFIz8We{ng2Q@8!p5kD4Or1`t~(Y;U|<| zl{cu+|HM+iEN@db-}_S=l*{+t|DE<7N#Q5d?_Dw9d-=}F`QGcl>0e$H{e=F9RLl2K z`&s!us$V1Dd->D$z4zfK)NgKIcaHb+n0@zm_zC4_+V@=Jy}XQlUozg?Uu|D!i;vo` zm+!s2w|!-3_|g8!$@gAa_g?;xeWPIb3H3+V*9GFeJga5C_xev1@Ls;o zzAq~Lg!(7jcShm8{Hna~eaZtTDvrnUz>&A_rz-Fhj}>IKQ{KR8deXDfQu_-nV6@qa*p=a;a@c~fbR-FN&|dGBBO{=f2L ze&x^mm7n%2f8($Goxk$`^fgH}$H!_8EO3=zU!GLJ`L%={%Kz!YHt(V$x=hJ)jed2- zZdc_6%6@VEo@2Kw3X~PRn$KzQ%V#=nHSJ%9an{b&zJ0N?s~s1QRX)VkIGe0;pBFEm zsq(v2{*20BQuzjzf3EUEc7XKuOSoG7Dz4VAA4|RchOYMAXZF?b(evzkVx#8`a<%83 z>1upWmY?Qoe9x3$;%e=$aJBYVE8pO1^)}0IbG3TAh)0G-__W^ zQ{{_PzCz_Mxmvp$^Z4-5v6!>=5Ve zR&up=Yq?sx&0VeCX)3=?<+rGOv8%QFnEW%Y*6wTa+gz>P9j?}Hs-1(q-7>D$Ze2T+ zdU<14D{td!+*Do@P}<;7gB-7HsYx2}9+ zS8KP8d|y{-R+Y{;t;V zDEX&OtF>EGzKyH3+sW11?X7%}tF?QN%9p7836;O*YVE!! zzuDE=-7a6sPL=maFyO+|}m4x5`ge`4E+#t@5dMD)su;xLW<&T&>~+w$atv^;5AwzmTgvzl^KpwOnmGMyPze$|tJ)8duwn+4A#UZ95jrzvOD|u6MO| zH!1(t)!J=o3lcAH=W6BMT&>@}uGa1d`SGsS?nL>UU9H}2u2yf6@|CXEZXsKPdU**~ zE3e{e?bdg-c3a9fwza9Z+s4((SGrogHLg}~z4A|7ZT@DK59PPGTKPS$R_`%a>o=`J zD9?1Y@(Qk2UdPq?Z7Sc|)%xu$KghMYy$)Qh-r35hxmvqdR1D?QU9EhctF^nt)!KbR zezmK$yH5TqS8I2tYYQ7+B~zTOiM-PPJ{ZfkfiZ{up^U0ki-Q(djyVe(^Lt=;qFx4K%r?XKQ#6;rFX-L<7{_kN-L zE>|mG=4$1uU9I0@RYQ3>S1YgKYUPbxt=~5Com^Yl>qvf#tMz-PtJRyVe7bAvSZu4S zkIU7{_qbZSCG1+n+pXeizNV|S+d#gHtJUl6YW4amZ=Ge{+MVob<;)<)6FS{8y?G%4@hQR+Vp8 z`3rWf=JnolwQ+8h-|lMT+#^4+rg>|3imSDIovYQG?`q>b_JB}+s;iX`bG7nwT&>@g zDqo}W^(z0w)%yKbez&XjTc}p3U(?n4t?O#-rrNcmw_C>5+C9-PuC_g!RK8W^J5*liAS?IzceQ?xb+!8aU42}2Os(H6 zSM#-9t>4D-JzTBc@vc^Hpz_mQt=$zWe_G|QsC<*FwYyDzhpV-lda$YWQ^VETt>bF# zHdWrq)wbt!m7k~b>8{q_U9QH_LRaHxxvRCe!PVN^+Wjo>soz)!MDnAe7g1wQ{>ojM{DIYVCHDFO*~6+AZU1 z{Z4eXcBi;nz3Y_EclFmr!%%*ztCbIPwR-2cTE8n*zDDKiRsM;}>o*GZo4Q*4cCJ>x zx2uh-ulx{K8`nLJL-|LpwqL)Jf2N6f8|O=|*3Jf3Yv*%UYiFl?tf_fxC)3r++qhc2 zPOet(L{}U4Ju1K1p5y)WwdX|Jb>A<|JJ!$`9@c3W4o)BXIbXu zwO#FBV^=Hh=xX!X-_^>8x!S+eU9EhItCip8YUTI1+P}w?`!$t6?;h!DR~vUR+jiF% zq?>Kq{duW27SGR-PL{{beQxs>G{&h(yOGmO7Bk%?LI19n-={0((h~oeB3F?pydk(-CycolkVk* zOHZ=v0QZBXw-gWlUg>6=05AVWTG!Tt?psL5mJ9xT=|dHQUnSjBDfl9lgLc?2=+V-t z)qirSohDxW7;Oi5)lHeFX=R6&;1S3*NjQ`?@KG#j(2~6^i*Ta{c!1RZG*pGy0v}q z-%A^G48E20^iIKFC|%Jx_~)dlU4t(!?bJQ^W29Fc9sEtwb-jZBKw9b8;187cJwEu6 z()lL_|A6%KlY{?3+OSXXhe^-u7yL!i#|(7e{^zA>gMu$9?K~v-wTD<1>SAD?R({;4hIraZd0rO4H8|zO=N<1;L*n zz2?H;=SbhYDEN=1Ri^}huyo+m;7^m@H7)oDrC(hU{7=%RR|nr-dd{`MUn*UBeef?! z3(X9^thC#W!Jj0(?&jd&|Ee_O{@}|?dpr>QDbndngTGb!&V#{!Dy^|R_-yHr6~RxCE_^KbN2K3A z5q!#%L0di*^a$z1Rl#2_edgKV*Ge5W^0zeBq5 z)8N05*7`j7M$!@6f8u$(o$uEuO>adeDJx_*%gDoTl!Ju;J=pEsTzDU>6onG&y_B#5&ToqDz$1D72CXM;Djg<0 zUpienN4i$}iS%b_q1vIn*3w?mVbXEZ`O-(EPfOpHek3h_P-w5Nw6Ao6^iJvH($&&k z(&BYO{SML-q|>CgO7D?wl725Oc5tX)UfNaKUpibmNqU*|3F+(7!gWJCRi!Wj@bh|WZZ!GzKuPQxIdZKi+^i1iM(wWldr5mMX zvO{|ZNl%qdke(-9B7IJ}QTnO0N`uf&jx<+#wsfI%mGmWPYEGzEURqz;OgdaTQMyF> zob)GY8GED6=Vd=>4{5IS9O*^U<sf{!a=~2@D(&5rM(k0U8rR${WjYB(?rQM_h zq%))or4LHCN`ID?YZBV2ChaL5EWJUxQ2K#%r!=K$sNYz6q_nSesC1TevGh6VYtlrs z&`u?3H|YTBbm_g)WzwzEpQYuRYkQ=!qJbQx6UGi%45ZdrF5& z$4W1eu8^*h{va*UDzsNo+EvC8>Qb%V{JqICeqH*e$rvmS<=PQ z=cKPm)7yo1DocAvbEP*(7fBzMej!b5AL>_>){q_}9VWe5dcX8z>27JFLujX^w7YbW zbhPwV=|j>lq^XC8`pu->q{m68O6N$INgtPPmnJ)gc3McgNhe8fkj|5?lYT0V9TDmm zmbRAmk`9xOlg^huBHbp9cM9z^m3EaLE1fExBV8taT>7;%{YY((w3~FIbcXa6={o7B z(pYD0kF>S4mvoABmh=_r7U@^g1C9#qw3Hq#JyCkObe?p*^fPJIE}?!CX=~|N=_S(H z(mSLpq+dyYkk;)Q+G{WEBAqC`UV4vosq`~xtXrtxSbC)NJn8k)+0xgfTcmrW$?l<@ zL!>>VgQa7nw@a5xw@KqYLj9)FuF_+rQ>AmH%cPG>w@Z^pYaG%Z(hH?GN^g~}mwqNq z?HTG9ksc=PEgdc$FTF#$Li(jNtygHLnY5eqIO%25Tci(4pOAhdEz~=-bEx!a>163m z(%YmPq+d$Yj|ugQOKVDxm-drhE4@qlfOLy=x3u)Jp}i{79@1RtOzFMS52QP#DaVES zO{ATr{iMUBv!xG6*GSh&6UT>kDoMLb2TEs17fK(LekP5b5bBqgW=VTXhe~gfE|PvE z{ZX2BVrZwiw5xQWbfk2i^g-!M(l?|c*QNPk-q$8vgq*JAjO23lse`=`TQrcd6hIE?rR_Q&`_oUxQGx~&fN=rLQ zPmzw7o-17}eOCIObc=Miv_ap{Za?XC>2uPbr1krS=k=G)ls@Nb_cLCUu9t3*ekk1{ z{Yv_+^e1Ub|Iki`w3xKKw6e6Ow6-)y+Cus`j-Gd-G~KnXeeOWsBr3PJQz9Mb@3UAt_I5`swUK@PM0u?K zxU)u%@7LdS{MevFcx1nZGCo${fA1q!zyG*#vHJF#D)l|AU*Hp@_OaC{ALze~X}?B0 zXtY&{9{20te{AmQ1xrVa9#GKs8|xo%RlA|iKPMxGj>@G)8(6IVfYBpI=GyQ27U*@* z*nT7JNo{*}t>16___0I#PZ)2_{_Y=pODC3M|9lSp$KEpe#g9#0^i$pb_vgif{io-7 zng1MU{|ec^|LJ)R>^Z;g*FVq9kMBGGvE3Sd!n%zc`6`|D)? z7=t~GH8?C5JIZ+EhesVOu(#1-ZB)>_T54>fy&>rB`5e$*Z+lD~f9gNxro{eHAmHJk zUp;Tfyp-55ub>~E*WY}>ejjR{8XIGo_v<}|ok_UtW-U$i&T+Vj^5KeRX5f`aWeFVJ35D`R{&+GFZ?8&_F-Pn_V7!VhKB z%@%C0leOpj$;W5AFR#7%_Sow<5B}5Rr`_aZ~%}?fJZWpS(8gVQh7=)YvkApdZ>RX};j|`r7#3=1HbJZ)~4&19J7t_$}&> z&bD6yZrZ#-!{!Z}WZ7>7HOMLOf77Oov$C2uZrrp%mjCq4IREf29aBK=eH)cim zZ=dM3w%?c|ywg~Ta%~>JWMjL`15={8v(cn{WdLQaO4Jt;LcIo!f{IopWTt`+RPRr?D%iFsBMKg*xhy<*=eN`7qnB(+fDUOPji7D^su zv!0fg@ZTFtO-sINPl@~IlH+wtxAn*Kt?PJ$GJbeST1k=T5_ecx(msrm zc3`=itSBv|n%SIKT5Z{?W*f%R4wBu^Y@=9O9oZ^o8^_WPmaS~INi40dY$dZzV`=qd zE1GQq2R1HRI3O{x5um^K(EM2cYnKc1B4%B6){Bc0!IyJZFc2h>$L-Dnh!- zijZ!yBBZ;l2T_%R|T=@(^;T zJcKNehmgDEA>?j(2)RcdLhhA^kcILPa-TeeERu(i`{f~Iu{?x4AP*r+Rq_z>j68%qD-R*7=1{2-zbKAwSCpLf(y!xBXxEVPAW^ z7ZH+iwjV?61ILa|tVmi~T1w)2yG+mYtC>WKYF9IF%ieT+Rr9tiPvZA8Z_DyR_$uaY zSzZ`l*}N^wGw_wn+p@d}zM^?smS^HCn73tlQG9vxwk$7(FK6DbYl;(;^}t40f}o5C zHpG$yr9H4QmLe$Sfeo@WK}ip6lw}A?cwoaUOHkYc8)rF!VjkE)%M%p!z(!huAkzZB z!l_75!~+{?C4vkOY^0S53VUE9twK=90~_gn1W6BUq*V#hJ+P5hBS?5)Bh4a6^T0-0 zognUkjkE?qss(wVpFKuXf_a*7U0 zNxW@0G9rrVP+t@sj2A_9@uH|6UKG{Gi=u42C~ANgMLBp;)DSO<8sVX+F#!}cA%LQ$ z1W?qB0E(IuKv4?5Vcu~|7FN%8MMNx0OC^`l&ijKvLqT}$Q=y*I7oj?FZClWx>Nd!=IG658w zLI6dl5pr}6q6b&GNqJacZluH0bg9xB#FaZ<|A%LQx1W+`L0E&ha zK+y;SC>lusMWYA;MO{+j9Sx9-C1%sQilQt>YP9_djlTbQu8@O(TG!%L$<93IZs)k^qXXB7mZ+ z383g20w}tcAW(E#N_?6Dl2P8SwA03lqGr)`R!Y+Oa*AfAB<{7h4WnK>$T}5bp%lKIsp`|CxD_i2%zXq0w{Wm0E#vcK+)R-Q1lJ~6unCj zD0(C%UZJv4w97BtSBRn)e0BX^O49jqiZ-PrTG(%3M#rKLsV|B?!i%Dh@uFxmUKDM? zi=t2PqUck+DB6k_MW5kC(dT$5`hoz8wh=(lmjqDs6#*1|O#nsP383g30x0^H0E)gN zfTA4)Q1m?k6zwE{q8|vLXcqw#{YU^sy9uD^CjuziLjXlT6F^ZcHSa1vT%)BBKv60| zplD-C{8R%ZV~`(yJ`hD?{J<1XO*&srQ8G1gel<~4i29#Dv5`pQUp*`ngEK*5I|8`0w^j+07c~qpr`@?6jdaEqDll%RG9#Z zst`cYegsfdl>myW5kOHE0TfjyfT9`%P_#b*6xAevq5}vx7S$qvq5}y6MTyk-Z3alj z5PSDMEj=|{>96!-QSH>E^W_xPO--z-E{f_=Uli5Hi=u42C~ANgMLBp;)DSO<8sSAz zW4tJ8f)_lfnMS}^TXb1rm z4JCl0VFXY#oB)bO5J1sL0w@|q07at-plA#M6rDy8DC(XXZ(x9A9OuWP9-`=LKfR4j zO*&sr(dns)qiczxGpH|$&cutNv+$zmY`iG?2VNANgBL~T;ziMUcu{mdUKCBlL(v5U zP&A1EiY_F8qR9kMbP)j*T}%K)mk>bF6apx^lmLpR5&nI@u~6C4UmjFev4>=D0d;%!Cg8+)| zB!Hp?1W}!>C4i!3 z1W@!K0Tew%07VZIK+$pnD0+k-P;^6Te1!p$F+0V;xlt5t@ng}7)THy}6g`oec(;xy zdXoC0XeC}0J%txVPvb?=D!eFq1}}=9#fzfVcv18mUKFjtL(%gDQ1k);6un3QMK2LR z(aQu-^a=qKy-EN@uMt4eS^_9qM*u~y6F|{=0w{We0E*rufTFhuplAaD6unIVMeh(m z(Ypjt^d12ey-xr|8wmnMkEO<=KM!}2-*tRk6gBhJ^#`d*=gTSjI5n|eTj#nuLz*%YXT_RP5?#U5J1tl1W@!H z0Tk^ZfTHgSplBxn6#YN|MY{-~=tlx5+D!mOKM_FD9s(%(nE;CH6UgDyz)+Mz07a<; zP!uPCqBH_1N)QB!K1_{wGC(p$`LXCDQMAWRdOYcTIYk-q#L#R}RD}AXC=)M=isD64 zF}x@$ju%BG@S>PFt^`ojjR1p5{%PHy|Pkd*;i5K0wK8E_D=vcfcIu0+2j>n6l6Y!$wM7$_E z2``FH#*3m;@S^BcJQVdIfTF$xP}GkAiuw~k(EtJ{8b|;|xdc!&hyaQP6F|`r0w@|v z07b(HplCP&6pbK&qLBnpG>QO9djR1 zGzl+?F2qC8WCAF(xbR_{4 zT}1#zR}(#fzeOcu{mKUKHJi7e%+@MbUh`D7phLitfZi z(Eqik1>U(J}%k zdXNB$9wLCEhY6r)IRO+sLI6c82%zXu0w{WnAW(F3JU-t5$#~i+nk9-}aPxRP>3lgw zPsJ0@+AoGiXSAoOFN#*-MbR^OQS>Zc6s^XKqUZ3UXboNzJ&zYfFW^Pdi+Ct{i2#aT zCV-+>2%zXy0w{Wo0E*TUK+!q^D0-a$iq;cA(HjI%^de-0E&JffTCRlQ1l}K6zwK}qMrz$Xb%At{Y(Hw_WAB`*$zc11W=Sp z07Y>EC`u!Mq67gHr4v9=k^qVd5d?}h$KwqRkc^goyLyW#y3|+Kh0~JGms3de0TfjwfTC&yP?SXgMb!zQs0INP?N0zjH3^{T00JngMF2$y5QB%AqYK9j@&GDkB1zr@j#EYUs@S^BYJQTGefTGp}P;?jp6ty9MqP7H3 z)Q$j(+7m!g2LdQMoB)bC5P;?Xl6m=nhqOJr`)Qtd&x)VTA z4+1DUngEJ=5(J7Gq{SaIKr${go0cPrw)(NCS6b5fa*B>iOT6D+6dg}}QFH=c6rG3{ zMJM4!(aCsGbP8S+or)Jleej~FFJ2V&!$VPj0w@|l07U}{peUCBiUtut(O?278bSa? zLkXa07y%RwCxD_61W+`R0E$KtK+$LdC>lcmMW+!!(O3c~8b<&{;|ZW>0s$1AP5?z` z5Cn>jNsFg-Fp9SOUB_cZQP1dtEiLJMIYsBBB@XB)iq56JC^`=>iq6N2qKSA>bOBxz zO~Q+!3-O|8GF}v2gcn5@A6{4^i}ve@tXnTGIJ)isq&zhIbN0^QbS1ZpDkD+wh|3cDyK>j~7LE;6>4$ zcu}+fFN*HMi=w;nP;?Ig6x~YzMGFa_=sp4{T0{Uv_Y*+TVge|7fB=e?5J1sV0w`KW z07VZHK+!`4Q1mbX6fGx!qDKgzXaxZjJxTyYj}bu8;{;Ij1OXI1Nf0QSlNP_q0LggX zk43kLqVxTXwlXd0d^ttWq$Td}EQ+3`z9?Fa7e&wEMbR3(D0&_*ieA8rq8IU^=q0=; zdKoW@Ucp1rs{~N=8UYloC4i!J1W@!k0Tit#fTA}Dpy*8kD0+(kiZ&2H(c1)2^bP?O zy-NT^?-4-J`vg$5kpPN5Ab_Gx1W@!L0Tg{i07V}YK+$G`K+)4_@%08sMz){CR*9m^ z{YrmJTGIJ)iatwAeBVVBeNKH*^aWlNZNrPAFY%)2E4(QB8ZU~r<3-Uocv18%UKD+Y zhoT(>Q1m?k6zwE{q8|vLXcqw#{YU^sy9uD^CjuziLjXlT6F^Zcq04qCN+E!vR01f9 z6F^ZK0Td+&peUUHijo9SREPkI3KKw41_2ZmAqW(Gnij9p)hMd%f5>60DBA32w9G`( z`ErU%BoeKfCF1=Jkc>3{+;#CpxYB>mKWvnfNIG9mQIkaC z!lOk|Q|gPNW_VH5950Gm;6+hOyeK*ZFNzMui=tL|QPdhQiVnj=Q5ym%YD)k`?FgW# zJpmMTAb_I7381JW0TdlU07ab$py)^fDC$fAMMn`pQ5OOz>Pi4b-3XwlI{_5+Ab_Hy z381Ja0TlHjfTG?6P;?AIpr}zIey0JF@u(k*8jGSCek?jRk#xSCq7xH|=X!~vlc+C> zPR5I(Q}CkbRJ8C-1`|Nh5CSL~N&rQ} z2%u;<0ThiOfTEEEP&A4FibfMa(HH_KI*kB|#u7l$I07gdPXI*|2%zY60w_9z0E*5e zfTFVqpy+IZK+*Au_%;J1V}>tMP&AbQiY_C7qG<$BbU6VOT|odvR}w(cRRmCU zH31Y|LjXnB5-HR7R3-M5N9|06CB7ma%37}{(0Tewz07Xj(plB%p6fGlwq6Z0} z=ph0qdYAx;mJ>kHBLq;if&hvhC4i#G2%zY30w{Wd0E(U@fTEQIQ1lc56g^E4D4Lgu zpKX9-jPRwplCM%6#Ya1MSBRK=w|{bilyta9g0#2peU69isA%NltutW z2?8ieCxD_P0TdM?fTF?#P?SLcMMVgpD3bt+iV{FkF@iwR=ZSdwDMpdM@0#|7C_2xV z+Qrk8&X-eEIz4e`l6^TUKEwXi=y&)QB(mhiYnqoQ6;=6s*D#!Rq&!{KRgsw zC4i!81W=Sk07caapr{4`6zxv{MKuYa=l}vJszm@r2NFP0Z2~AdhyaS}5J1tv1W;6$ z0E+4nKv8`HD9R>)q6P#|ltTbT4GEyA5ka7+WO}@d0g^GtSJ$P|!$Ua2%zXl0x0TC07XX;Kv5S0DC$Z8McoLXs5=1^^&o(vqY0p>Cjk`o zB7maa1WW3Fa{qdq`0A3Ug#EYU_yeJxk7e#~dP&9-9iiQ$E(J%ri8cqO3 zBM6{qBmoqSB7maN1W+`F0E$i{fTFPkP&AGJipCQ_(F6i0I-LND&LDuIGYO#RECMJx zn*fUbK>$VP5J1tn1c9QH(&KL$AQ`j#^F=3%qN;vIJ1;%yd^tsv(i1=AilPgtFN!AP zMbSlgQFJk06kUQBMN{yi=u*5Wnu-@im*GXxG&~etP5?z$5J1tD1WA{0@S^B$ zyePT{FN*HPi=u^iQFI?(6fMGwqWkesw3q;j9w30CB?M5klmLpB5kS#{1W@!40Tew< z07c6Qpy&|-C|W@PMUN6d(PIQq^f&<&JwX6PPZB`UN&+Z)iU5k9CV-+<1W@!00Tew; z5GcAmJwDI?$+*!EKl4RV88@rblg^h@^g?>#qG6)wMe2*9m++$KWxObQ1uu$T#fzfX z@S05I|880w~HPfTE%VP*jWnii#6JQ3(PlDoGG1`Z7KKl>w45+z&rr ziK1J4bzLf%biSOTa>+!=(W0n4^+izyyeO)O7e$ruqNp-n6ji~CqW$oqs489*Rl|#- zEIbrdCxD_F1W>d;0Tk6FfT9Bkpr{rB6dgzaMYRc_=pX_pszU%p2NOV1T>>boM*v0j z37{yO0E!wAKv50>6g4D(qDBNz)R+K@nh-!yQ-VNInPj}F0g`cmU+I@khAaJDeqd^r zOgdjq(ILsiai@u*L#Z!{TH!@eYrH5r3@?h>;6+heyeMji7e(#yqNoF26djI-qK*Vm zbOZqubs~VGBMG3WGXWGGMF2%z2%xAd0Tgv3fTHdMP}G9}ijF3LqMig$)QbR$dJ{m= zF$7R_ECCc9M*u~~6F|`k1Wl=yMH2|1=yU=oI)ea;&Ln`Mvk0K*Yyv3y2LTkF zLjXnR5NB~7Q5kS$+1W+`K0E%W4K+zlmD7u9JislkP z(L4eux|INmZX+WchF`ErWxN+u3EQxx4zeNl7| zUKHJn7ex#4qUb)nC|ZOUMfc-H(PF$PdH^qqmf)diDFGBMBY>g@383g90w{Wz0E(6q zK+z)vP_%*oiXJ6^qQ?lJ=y3uldV&Coo+N;xl>|`q6af@HO#nr!2%zX00w{Wx0E$)< zK+$sqP_%|1P;_T9-pv5XSm(bRyFe7B`BMA&WYYO^ie648MxQN;UZK7ydKE8@lUkbe>if;E~(O1c&^W_wMn@lV{M-+WWeNnUnFN(g$i=v%)QS<{| z6z#%`q95_1Xg6LI{e%}qd+<>7GXWIE3hA;Pic$!mD3t(;;sj8XMgT<#0w_u+fTAP; z6cr+XqQV4FltBPRMF^lMlK_f}5v^^Q$ zV1Q(d@eihbBZ|s7Qe_JzoiC@TVxh#3=ZT_9)E7mS@uH{-UKH(z7e!U^qNo~P6lLK> zQFXj1s(}|p`{SXgCIJ*3KmbLx2%zXd0w}6Y07VB8Kv5k6C_0z`is}+TQ9S}Es!sq# z*#uD3fB=ee2%xAT0TeYNfTG3(P}GC~ikcEYQ8NN4YEA$}EeHZdN|6dgu=QPc)6irV5uQ9HaSYL6F19q^*)aJ(q$h!;gi z;6+gf`}r5VpkLu6%iCWDvDiH z>;(&0QBlwDJNv$pJkPt{bw3w=>!zbAfRX_ z0Y$S2C@LkOsEmN3*#s2LA)x3y0*dAmP&AK#qVowTx`2S9`2-YQNI=m=1QabGplBfh zMHdrLbO`}PiwJ?D;#B`02PAgTzUnwyinbZ4#i>#AWr~)hMqas8imu>%DY}v^MOU$< zXenEYu4YToGPV>gXG_rvwiK;oOVKrK6s;nl=vo4bt|Or6dIE}86Hv5hP;>_&P;^Z6l!QF#?JnC!pvF0*ba1Q1m1LMLP&6dWwLeodgu^BB1DL0*am? zplCM%Mb8pY^c(?2&l6De0s%!Y5>WIK0YxtpP_&1DqE`rkqPtW5b`D7FR5!!-NKuA; zMte0iYQ9X-8>x{qu9TvEoG(RhvZd%PwiLb1mZEpqQuHocir!;O(fe#E`hYD(``IY^ zkbt6(2q^lPfT9Bg6n#QK(We9yeMUgh=L8geK|s-$1QdNmK+)F(6n#TL(YFK?9VDRW zI|7QnC!pvD0*Zblpy&_*MTZF}`iT%I+MDWMio z_1RK%JX?wyu%)OWTZ&F#OHm^>iW(D8)P#VdrUVq7NI+3D0*X!|peT=kqUHn?PSFQCqkg8PMRNE?iA(P z9qPJi!6W_Q$p>s{QS)Vrx}`;$t(2nfoG(Q^*izJ!Ek(W9Qq-F*MSa*()R!$q{n%2} zpDjhFuu(LCfTDo}6rD;y(I5hf1`|*;gn*)<1QZP;plCP&MI#6(I*ov$(+MaVNkGvV z1QeY~K+#zQ6rD{#(K!SZol8Jb5dlS`2q-Eh1d6((`GXyh*f6{K=_*A>-6y#4=(MQ$ zGDYLkA~RP>(Rj|6q6us%n#h)-No*;a%$A}lY$=+`mZE8FDVolfq8V%y%_N{`76C=2 z1QeAKP&Au>qB#TJD!6#Z_05&z|BQS)Vru1bqMdYu$4<$Ni+ znk_}k*iy8dEk!HXQnZpSMc1&UXcb$Eu4PNnb!-$}Pe9RX0*clUP;>(UMQaHtx{-jQ zbp#aML_pEa1Qe|&py(C?iZ&2XbSnWx8wn`dL_pDP1Qgv)K+$FbitZqw=uQHP?joS* zZbG2wiZp+}0}|`yX81}e>SGW4?@5cAFH`hDTIBE5QnZEhrRYJn6g|Y2qOEKxdYCOm zkFcfaQMMFqV@uIvY$T{@fTE`fD0+r~qTK`( zJxf5*a|9GUPe9QN1QfkUK+#JC6unG9(H;VdULm09RRW4$BcNz6Ay9N*nt%Knr>MZb zjeoxsZL`N{uct-LmnnKHEz)DH6ur&)QuGd6ir!^Q(R*wudY>&tAF!opKU<1EWJ}RU zY$^JfjiLht6n#QK(We9yeMUgh=L8geK|s-$1QdNmK+)F(6n#TL(YFK?9VDRWI|7Qn zC!pvD0*Zblpy&_*MTZF}`iX#|p9v`Xg@B@834x-0Y5oKUB-Yd5yeUOH>|3+HrA5t` zDf%-la>Y6+`it|W=qOu?{$@+jKWr)bmn}u^A3hHLHhC!uv85=5Ek!|}Eb`jTQk2X2QdFNU zMaQ$Hr~zAw8nUJ61hy14VoOnDwiGpCOHorcicTb;s2Kr8ClOGTM?g_?0*dkpC@LVJ zsE~l776cTvB%r7j0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7pr{i8MV$#KI+=i?E`&hQ zF){xa2PC%7Zhnr91&{O}ve7jbHD9KvXDm{EgB11Rd@1V9mZCmvDeB9XqJC^C>d%&< zQ`k~8fGtG>*-~^W8%2W%C>l&a(GUWPh7wRTjDVuy1Qd-Rpy)ILicTk>Xe0qeXAn?y zCILlf5m0nC0Y&E!P;@Q1P}DuQG>t7q)7erqgDpif*-|u%Ek&hl6qONB zG@F2;IRq4)M?leB0*dAlP;@>4MHdiIG@pQ?3kfK?h=8I61QabKpy*-(iY_6bXb}NL ziwP*Ylz^hk2q?OofTAS?6kS0G6pfGh3muTyU3T*`L5l9RJ4si@qUOsKEsI4q+$KfK zIbVuau%&1vTZ*n>OVKK}6kW@fqU+dFbUj;&Rv!&=sHi~u-Q1lc5MLP*7+C@Oo(*zVfLqO4P0*am`py)XQ zik>H+=mi3bUL>ICB?5|GCZK2!0Y$G6Q1mJRMXwQ1w3mRQ*9jneZZEY{cI`vkS#?Yv8Cu^wiF#; zOVKB6Df*O+qR$8@`ka8GF9<05l7OPG2q^lRfTC{*DEgLwqJsn!eMdmi_XHIEKtR!t z1QZ=2py)6GML!Wx^fLiPzYtLLD*;8n5m59y0Yyg$fugr#{!j-bcG%#&BSi!3)7u}h zsQEHQf5#%F_ejw{oG(THvZcsN*CTf+3bCaqg)K!sTZ+PLDT=VAs0v$(qHGkU5>S*z zKv9fX9BbU#6%}dgR{+q^K|FOHn_z6!m9I(J5>x8o-vK zfov%{l`Tbs*itl@Ek#4vC>lyY(J%svh7(XUf`Fpa2q-$8fTEEE6rDjp(U}Akokc*= z*#s1wLqO5F1QZn!P&A5wqGAGyMiWpphJd261QeAJP&AH!qVa@4QLl8r;TET8wf$j` z-codxds%owdenTGqABT-UJpspRL+;8X>2K)&X%GXY$=+_mZDi~DJo@4Q5jo`X0xSe z4jV=15l}RjfTDQ>6rE2%(FFt)%_pGfLIR2|BA{pi0YwW5D7u({qDu%UT0}t6VgiaT zC7|ds0*WptplAsJMOP3|bR_{rR}oOOln^MIl5;1*mZEDoUy4?-rRZ9=6kW%bqU+gGw3;nNYuHkB16zvLvZd%oHj35}P;?UkMK=>r zw4Q*XTL>uHKtR#01Qcx~plA~TMYj=9bUOh>n+YhogMgwt2`IXYfTFtzD7uG$qI(G_ zx{rXO`w1v|fPkVcgh0{qbpHVdBsSh|i&jWcH~WnCV0zSinW9J1BdWIU0Y%Rf zQ1k);MK2Oi^b!F@FB4F-hk&A22q=1$fTGt3DB4Rv(dz^hy+J_HJ_3r~B%tUm0*c-y z1d6t%`@cCLv90z!{fDLK>f{5q^r-nVMIWR`YCbMS`#E2VK4eSLM{Ftjm@P#I*i!Tf zTZ%qqOVMX+Df*l(MPIN{^d$jBUlCCBH33E65K#0j0YwK1DEf|oqVEYP`hkF=9| z>JU&=mw=*r1QZ=ZK+&-T6dgxEQ7$1+^iR5fi31WlY+rT!SBhG=mxb$RM9r5eIw2#n zafcK&;(RG;%$A}iY$s4D?Q-3Tb^PC!u) z0*ZPPP}GYMC~A=5zu(Ii5ksBea! zwaY1r*jF9fY!sbOK+y#R6wN1~=t2UDE+U|40Rcq|2`IXlfTBwXC|X27(P9FME+wGo zG6IS&C!lBv0Yz63P;?~$MOP6}w3L9Ns|hGtMnKVWLZE1BhCkc^iFLF))YGJBpp6w7 zQS)VruFZ(depZUE<9sQ)o-IYI*;2HIEk!r5rD!c%if&{}(K@yi-Ncrno7pH@Pe9Qv z1Qcx`py*ZtiZ&8Zw26SC+XyJSoq(dv1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?lg2 z1Qb0$K+zTgiXJ4O=ph1%wh{tG*JSu>9gx@|d!)Zgib|6Y*fOH#%M?A95qaWyDSDjq zrRWK^6m4fq(UWW`+QF8hr`S@olPyKN*i!T~TZ*1xqi8n)Mb8pY^c(?2&l6De0s%!Y z5>WIK0YxtpP_&1DqE`qgdX<2p*9a)uOF+@<1QfkNK+!$|iryrk=q&<@-X@^v9RiBp zC7|d%LZIl;4F7-w5^HQXKijxpWIv0Y(210!8~X{6-E) zY*WO+`A~|Q*(3dbGot3p6#1EvK6|7nocW)R^doF3s=}6{C|inB*;16omZBJ2iqhFq zl);vwOg4(L2q=mZP?R8`D4T$y90H1}5>Ql)fTHRI6xAT0s3rkLwFoGxO+Zl{0*dMq zP*jhAqGJdsI+lQ<;|M6qC7`H20Y%3XP}G1BC<RuLZm>D%+ zrl?6~OeqIM*@mE5m3~bfTEKLDC$B$QC9+rx)D&+oq(bq1Qhio zpr{uCMZF0q>O(+LUqYa$QKtW(0}^X$a2iWdihX+Pml-u*rf6VhWZzyXI+gRKXb@Y9 z2D7DT2wRGVvZZJkTZ)FWrDz0OicVuo(dldyjU=Gx3<8SIB%tUl0*cNipy(U|iq0jV zsEB}~Q3Mnf6HqjofTA%36pbaIsDyx`aRd~NC!lBo0YwuDD4Ik-(PRROrVvmxl@KU8 zCDT9RfW+q7ZP5TJvM&>br)5UXmnoW+8L7Qbib^?OiptnhG@C6&bJ$XJ9$Sj$vZZJq zTZ+zSOVI^vDVonl(S-yQT|_|90s@K_5>Rw80Y#S(P_&4EqQwLhT}nXFWdsymPC(HT z0*bC6py)~himoD{Xej|jR})aQjDVu$1Qe|xplBrlMb{7lMKdz}lO2%Q&-Ok2nNn0> zw?(Tmqvp#LtC^|$y(P09Lej=dg zX99|TA)x420*Zbkpy+o3ijELa^alY&e-cpi7Xd{_2`KuTfTDj0DEgOxA}>o1%uy5~ z1d2Y+^b_wpMZ4{`=ztV`<-3uR6*XU`s7h9(aK98qIbVuW*;16omZBJ2iqhFql);vw zOtutdv85=^mZAh3McD)tE&)aL2`DQM0Vbc^^s9Nt`c5d2A_a&X%HlwiFexrKpfCMJ?D;)RHYlt=Ll3nvJ41 z1QfL;pr{=IMePYF>OeqIM*@mE5m3~bfTEKLDC$B$QC9+rx)D&+oq(bq1Qhiopr{uC zMZF0q>O(+LUjmBy5m3~hfTB|ffug2a{yGOFcCLK~U+tVgiar6HqjUfTFPk6qOKAG>(9x@dOl2AfRX>0Y#GtD4I+_(G&uTrV>yzjew%* z1Qg961d2}0@;`MzVmbC0ZIBfGVWeheMa`Efnw=H#Ka-+4oG(S^v88A(TZ-nfrRaRN z6kWiUqWNqox{xhJ7qO*i0UJdN2`IXlfTBwXC|X27(P9FME+wGoG6IS&C!lBv0Yz63 zP;?~$MOP6}w3L9Ns|hGtMnKVW0*Y1;P_&YOqH72!T17z7wFDGhM+g*^X8BDVkXRFg zQzk{9+r8`Sv!dq96s^sQ^!q}JZsdF^TE~{6o7hrxGh2$*v!&=3wiIn(OVO=tDcZ=E zqD^cR-9|vs?F1BUCZOmJ0*dY=py)0FitZ+$=pF)!?j@k;J_3sFC!pv70*bZ}Q1l=H zMGp~Bw3UFOhY2Wpgn*()2`Jh|K+$6a6g^G|6s^hfr#T?8BKxZ24N^419_c@k6*XU` z=&7v8@~@<5C+ADiF18ds&6c8P*iy8cEk)0=rRX`f6g|(Dq8Hdw^dcKYFA-4mG66+< z2q=1mfTC9kD0+>6qP+wZy-q;U8w3>XBcSL_0*c-upy+J^iryih=v@Me-XoyseFBO; zAfRYJ0Yx7YQ1lT2MIRFaMNek=TOE*CuH6;dAw^%>AD=yt6*XU`=<}?|Ti;007o0Ce zU$Uj>E4CDU&6c8X*i!T@TZ#^{rRY1h6n)Q@q952O`jLR5Lj)8ZCZOmi0*Zbnpy(F@ zihd=a=r;n2ekY*l2mwWZ5K#0d0Y!fiP;``lqQ40!`iFp`e+ek^;(FMQq7VT^DFhVx z1Qdk{fuc{d{68I#*e-+fnG}^8sYpC(zD!YCJW}^NDT;Bv6s5DJD1$9UnQSS_VoOn+ zEky~o6lJreD2FXYRoN)2MnF+@0*Y!7P*jtEqFMwL)h3{*4gp1V2`H*ZK+!P-6dg-I z(QyP6iicTP)s1X50jR`1fLO@YdLZB!b_q#eEv1N8wC^a5D z(!bG2ofwarFH_V!9x47oit;&MiVE0LRLGX17HlbM$(Ev4Y$qIPT) zwI`sc0|7-H2`K7BKv8D`icTh=s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae z2`K7EKv91JicTS*XaE640|_WPl@KU8Dehn9fW+>%$7p#{bRhYFEgm&rrf66^viXn{ z4d;9*8o`#L)7VmUI$MfHvZd$@wiKPomZG!RQgk+3iq2u9=v)GdiU=qgMLldR(O3eCN(d+#M?led0*WROP&AQ%qDcf4O(vjd3IRn^2`HLIK+$vpie?Z{G?Rd$ zSp*c75&}g-;{F~7BsRysc0E*z^6j>$EFLvqrf6`M8=zO*mUBH&2`D`h= zkS#?Qv88AMTZ$I4rRZX|6kWnb(INth786i(DFH>75m0nF0Yys)D7u1xqALj~x{83J zr34gRO+e8y0*aOsP_%-8qLl;`T|+?8DguhGC7|d!0*bCDplCG#MQaFwqB(It=VzyA zzI`9Hc}sQEHQH^n0@f0d$}IbVv_v!&=3wiIn(OVO=tDcZ=EqD^cmx{WPG zx3i^aGaE&B5Kwd{0Y!HaP;@r|MfVU;bT0u#_YqKZKLJG#5Ky#*fT9NpD0+y1qOAlJ zJxoB+BLoyZNW79U!3S69S4pB?O9g#{HWekXV0vShh=wBK9T7&*D+@Ws1IvN1pmaioWK2 zDf)&jMc=Ze=pb8)zGF+#_iQQpfh|QpvZd${TZ#^|QS=i5ML!cz^a}w+zYLqO5L1QdA*J#0r&h=8IL0*ZVBioygGMF=RW zLO@ZJ5GeX0?tkup#M;^?u`i`)gxwaUCZguc6lEkLk)u+S$@x;0#g?KtTZ$5FDavL` zQ4U**s>JU&=mw=*r1QZ=ZK+&-T6dgxEQ7!>R z^$93Co`9kT1QazSpy&hwiW(76)R=&xCIl2UC7|d;0*aauP;?R@P!vn}CpsXp9cd0u zdLnqF|B8Kj%S%MfmnkYtL{9lfidt~K6t!eaQ7g6-wPs6E8@3d+WlK>zwiLBzOHl{5 z6m?{ys1pH2oe3y9nSi1$1Qc~8pr{)GMcoM~>OnwJPXda15m3~dfTBJG6!j&bs2>4E z{Rt>Kg@B>~1QZP6|Y`BiT}P23v~GWJ}RmY$-aMEk)VXsvG(?@vk_8M*BVU*fv#(vBFGY*&wrE`EkzsIQnZOJMYpk~ z=ytXgZDvc+9c(GOlPyJeu~Bq40Y&!^P;@T=MfVXplCY*MNbk?w1a@6rwAz8NeC3(obbClAhAYv z^Rr%x`q^W&U5TjqGDXiOB4eUb^c?3)(erF6dVwuPFS4cRCAJj3%$A}(Y$dXIpj_X#NafPkX?1QdNp zK+#786n#uU(E$RAJ|Up!Qv!-UBcSMW0*byM1d5(X_)8p+SWUYv+AT#}?B4a4iKzK9 zMc*bOccw|vLC%+=@7PlGJzI)?U`x@DY$-a#mZHOKDf)>mML)Bp=odDMekGvjHv)=& zC!pvE0Y!fhQ1mAOMSl@cbd-RizX>S%hk&Ag2`KWi^{^d9Ap(k02q^LiC<+r$6d|Cf z3IRn?0*X=zC`u!sC`JereVy=MbwFa%-3)&tMcwR?etLG)e3_zncI3x&DN1m@6lJre zD2FXYRoPNhjV(ph*-})4Ek!liQdEmAMYY)|szX3gT>^^g5m0mt0Y%3WP;?vtMY#kN z)hD3ncmj$V5Kz>RfT9x!C~8DNQDXv%nh;Rblz^fW2`FktK+#DA6y*_6)SQ5#d_tfo zGuyA0;S}w&uR3OB2aoh`x7(tE?5O!NMXjzwiLBzOHl{5 z6m?`vQ75((b!JP^$!rvLA)u%$0Y%*iDC$l?Q4a!&dJ<67i-4lu1Qhilpr|haMg0gU z>Q6w?DFhS^AfRX<0Y#@0P&9~uqQL|d4I!XtC;>&o2q+p(2o$x*_Rn-cVz<~`p_WpV zuzS}dvZLn96rGVBxga4$XL7z2oyC@-v)NK~4qJ-OWlK>JTZ%@prKp%KMWfkLG=`0$ zu>=&A5KuIZfTHmP6ipzYXd(eclL#o9OhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q-Eg zps0+1qS*u#%^{%ZJOYa55>Pac5GXo5+rPyDi9KnzMI)u?4f_)0`PotPWr{A!j_k^j zq6M5UMGM(dbTM0sE@4a2BDNGQW=qkfY$>{oEk&2JrDzEoMOP3|bR_{rR}oOOlz^hE z2`E}dK+$pnidGO%w32|LYX~S>ML^ND1QcCIK+*LC6s;zpXbk~HHxN*?mVlxg2`E}e zK+#PE6x~b+6wS}}zjQ!ib?xToLMfVSV|{kie3_z+*^y{{zjiUPqD7v43q6Y{l+Co6lg9H>kL_pD20*W3cpy&|- ziXJ7PXd3}Vj}cJxH~~dZ5Ky$8fTAY}DB3|l(NhEz?IfUR7Xd|26HxRFAyBj-+ds(x zi5+i$djD1_dfsk}c4tS;mnnK7J2J4Q6urp#QuGpAie6?*(H^!Gy~38FSJ_hZ8e59? zvZd&CwiLa=M$tY3iryrk=q&<@-X@^v9RiBpC7|d%0*c-zpy&eviuMyw^dSL79}!UW zF#$yf2q^l5fTB+cDEf?mqR$B^`htL>F9|66ih!c834x;Lvi(^ONbCc9r2o7W{pns7 z{w6zWzD&{g*^yPXrRWFFm!copQgnzdMTgl^^b=c(er8M2FKj9Ll`TcTv8CvDHj0iA zQ1k}@MSl`d^cMj|M+qqUn}DK!2q^lOfFdtP58F``BA_URfFhrOqA&qP5dw;;5Kt5) zpeU7qqBH`EVgwYW6Ht^vKv5kBy>Z2q-$1fTH6FD9RKv5$CiW(D8)P#VdrUVq7NI+3D0*X!|peT=kqUHn?92Bl!Yy;6=F1ed&50a$tQ585d?{+rmZA=9DeB0U zqE2in>dcm+li5<#g)K#0*;3SvjiT-Z6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqW%OF zokBp-00N2z5>Rw10Y!rdC>l&a(GUWPh7wRTjDVuy1Qd-Rpy)ILicTj4idyIRJspr( zGlSDcivF~3@Q=)inlDpyc218qJoXF>EOs z%a)=NwiJzHqi8$wa|kFpkAR}N1Qg99py+%8iY_3aXg(oObY_l!r2`ThX>iVxqKoaW_Jui7 z^JR)I&WYT8ycAu+`BJoqEk%pjQgkU>iY{YI(dBF@TEdp1E7($WC0mNFVxwp&0Yz66 zP_&GIqU8h>tstOiB>_d(5Ky#=fTC*&D7ub-qU#ALT1`OF8Ul)LAfRY10Yx_wP_&MK zqMHaPx|x8Y^#l~%LO{_5LZE0tj=$FdiGAs2c%c;iXyewLsQL1;yp(W*w7QK#UVO9r zmaP|m(ZIzIx-V0v#xvccxr}(eyKA0^56SerYVqsho>wdWLAK}Bi`TE_dAafNH9W6j z{N7rg*ChUP9nU){-u@WRD~K;R&huKupRMnC?c(VTJ+D)INF&ed8eiSS^LoZVJkj&| z#v9~$-hlYTe9s#kzrWD)hR1(x>3JjL9ou-`+3}0pdETh_^Bp{IY&^5G=S_$Y>*9G+ z;x}~jyczM2dw5=1{Dj_~H#a`HujkE=Z|U!O3*)~J@Vv$G&VxK}Nqo@|&s!RQahT_= zh{sR!yldklMta_w_>E_J-n#fFXM5f)@y11-w<$ig*z@j)KQzYk?uq|V;&~6myG-!B zt?^4IdEU18%TqjWdpvu(=k1K2KGXAd$8Re2ycgo1&Gx)K@uu#d#Mm33e!l0u8Gm@b z=e-;M>mtwFAMbXt=N*V&zR2@FkH2!M=Y1Woy2SIoi=T0&=N*c#U+Q_k#J^bPc}L>S zR(jsi#LQLh;~z>qdY!uhLW#duyK5kn=&{ya1);)dq^O1yTnyAnc)>Koj(5K5f2 z(OnIp#D?44^$<$fzh>Vsl(2t}yh$iw|DNR4Kg}>Ql(4^B|Ljo0 z{&MtDp@jYI)?-5n`|F7(gcA1m%T5U;>@NtN5lYzK@K_c~*k92%H1 z!cfBgmZQa?#FGcyH55wN-!rl_l(4@jVnrxnKk0vMC}BUUy(W~fpS4{VO4tue-V#dK zPrGdjCG5wQ?g%C9=S}VjCF}U{Ui z#}Thu75CdH(mK0|Yt=`F+%?_Oy}J8ox&K1zYCPv#ImXU%zX6j^HM88KnNaI2YhF#q z)C;uUX13Ghc_|IO^z@Tm@;twW z=Vx_D@0i{`yFJs28R_lZuOzkRf4o+j zd#y^B8q84#|hAuMs(u#}B)J5vGvfN3LiuWU)>E1hg%ZcPO5zoukuS9Po zClu;e)h@njefOIA?iH%Fs`O5Esoklz=T&bW>QbBcv~lh1P)?PuwN`g`FR2l!^vWqU zAMNfwY&9!iKt1=iYgG<$Pe2Fc)CHES+|5Chy@>(ys z?Ij2c&b7jmT^3I(9Vp)$>nDS5zxkBuV~VHbmrf|2RgyoeWLimSacO=@i=xu9*<&Y8&o7%keae^##S^EM=8qpU zrl@$<)cnGNqLxK13R)Bv6&6^`b1`q)^l2q|CB>sB<`ot+Z<%K=Zth`l(M3-c{55%n@@1!Ja=`Coj9$`4JT+=k6uOY-5k?n`qZh@r@7|v z0cN6IbdWrE^BhUC^;?D_k*fdOQzTTyA0LY3__cEjI@IqNiB!pt#(H`Ff4zLJUf$$?ygYeY z^ZzZ|8&9d?&uJd1VbAH!xi_2ZXXYl~cBo2&NVYNgFzXgZ(>QmIaps#1g!gd9Hi$({}wrN%VZ0jE7&$el&*KE~}){T=3S_Lob)kCjS z=w5l^fa%j`6nX=@jV$VM>hKo9W%uNi*5z-nEvaS2+ig+)c6(I1NWFtCIH67XYqd|l zPqU|$P8>h2WNfYzlYDbM^nMlg=2F}<{4#r$|2hiYJCl6<_U_e+irm>PTNDMCQ0U$m zC-mmhy6MuoS6qVo2)I`pJA3NXdEU?>gDTp=4m~~$3@(XkC4{x-EUcY6<`_ZHPjKUtg zDff=+4D(Rw=Jx;UMy6-U=-K0gUyZvq+}m=uTa~U3y&tVA-ZgjC2d`fKYr$AS#V@6O z`MX`{_9BOs}|@YoLjvo-OJx6`yHBmrEV4PTu*o1b{pEKFxkr$@P-T9 zm0wI@1vFsbqOd}q`xWTTqM`hHcQ*vdH&R%^sL(kIS^+PtkX6{5tEB=I*OdDO1n2RL zT_wpIp^B^3-7e`}DRl1(&lXmEG%8)WZFM?VK;XtMuwBK6%6%Y%x6y((R&m7_R$TLi zm9Bbs?F6S(T*+Jqh28aQw`;)OQv34v*L{5T?pEA9wbUiGu6Tcft3LUwuDG@fD_z}{ zuI4uG^a_LAxD}$sUThcSj^!UH-k{z+cSE8VwJiS-x(@`eUU9{9opP0yUybeDB~34f zT5+9l({DEsx;S?Z7wiNEA42zLlh3%11TQOpm)zTO&2BS?yHEUjeNJ@ON3z(JocxRu zd?M*pezv;?bcq%30oSqn2E+jV`Da)6 z+a&oacAflR-hI}+?}|HRNuKUQ9sG(b`Ks_#SOKcALKIhbq5DWAPj;W%lSi)3Lid{^ zxYSBoDsZ@8nLhA^?%qi7itabRo+-b63IjUH-+&ddP-i$Y71y47uFt6>a(lFIpKEvI zn-}KVUHO7`En4L^nN>2Sq`0)CX>Q)sF*9a&9^AM`^GavrjV)~BO7W~Q6FR#G26NiwO>I8aJ+x>xwsc0baWiuB z#^>e@YLT1g?#p%_qmRIWT zle=T7Yh#PcipzKKp>Ut@gJ&v!KNME{hA`{@+o!F-e5FsV<*?mvjO1lj+zmA9_A#!w zH&}5WurT=Dla%6a>h*3_Tp7V{q4Lk0$=@+WMgRFpojaiw_d#J}_mc+o9#;Ozx{$k^ z6?Y#i?lo52X>@l#;S>B8vv;rDF?TqF`+~!Y`u6HJIQf28x<|;}&WgK#{H819#@y~2 z1|KNF4DJIaKN5DwQ};!azvAGxc=<20SCzs#KazC@;-e1L?KaiITD8Fx6 zey6eg{$ZuxO%=ZBJg;(6SE59OxJBVJN9z8nbHnHD7-DXYA?KO3D$=I>(ZuW2< zLnnVr@z}WO|Na}yeF?=q>i^e0g}jvcS?=p8_JstV>{MS?E6!s4PTlvMlJpirr9E${;c%myT_i{m9~8$#C;9h8(ZEgzA$3R z_uLoGDn0q0`@&VFC*N~lAFuS}d+w_?m7aXhea*bmlkdeVExY{xd~bZueL<(AaRJ66}xeZk60aWAZINB2u=qHfo%y`KAOee&qOMxQ)(*Kx3pBXo3MK}f!Ql8!TV zT%hA(9areMQO7OrYPGlXq>lUC)nxl)9e;Jd0NWw=)l56qbiWomHqf!XyIO4b((x?! zYp^|D$6MUhV*6elzjPk}+du1gl0#y)ew&~cml=7;TPb^NDJu+!@X$DZyR zBKGnjI$n8PuvhE2*L`5^z^E5P>sI(~g(uz%IDd0wzP z>R9HkD0}^jb$q-q*w5?ewF-8oj=kL#YOg;`$EEFpeS?l~bO`pxI@WSmyuJPjI-c7l z*pqeK)GgRsbo{nQuz%OFpm(r4>o})xuovmLy??M@)G=jXu;V)R9Te;lIxZU$>>G7_ zb6BuH(Xq~H!EUVMsFA^*s^jfv2Kyl$zdJkFf9TkvDA-+eoLe01OLg4gpxejeWgWxg zf}O2n{|Ui9UB?xZf_;;YZ%+yKXFArK9_*$%j-DCp={nv~8tjL4{9$&m|I)G5++cUp z@%;0HeYuW1=Lh>09jhz|c2yk*Tpa8(bi8I!u-EJO?xn&0LdRp51iP7zW3LSMOdao9 z8tg}PJhUv>f9u$0Ww3kbIDb{Juh8-7>w^87j;U*cU0ugh*9QA69j{#%> z*Uwiv=57dfo{r--2D?bU>WV1J|I@s9^PU&jgCgFRcv`*sBT2_1jg8SK!m;Mn1r;MhmU zh0g~2Y8{_@KG^$o%y=o-wRIf2C)h?;G1B7 zuVbU{g56TbDL({zo{kS53ieYv9&z82G*6MAgX77+2FFu$T>N{mSL*oEAHjY{$HdWK zAEV=G{{(xCj_cfKe7pQRb^O$QN7MF?IyP}%JGb3h$7$|+oVG8}ajW}gr|n%j{^`E! zX*=qE?8uH?-M2sOI8evS-1k9kuhMak`-Z6P_jJs0-x;-ioQ@;iw@7W5=yp0Mk5%;ZW?J;(Y zxzFo5PEnty<7GOo)XT5aajp7h9k=SZOUGAr{6NRAb^KMwl*YmP=kAUq-=9<+<2qK= zv9XTLbgW`W_sR)vcSxSk<&@g}9rx>VcRRckcVV@7z2>F!rj`|t_L`TL%?geac+Nct zF7uk(qfW2+=+aWJxqF=4++y?p{0eunkF~Gcx-XrNo9<3YK3_a~^sJIO!C66Z-;t|4 zi)R&28(*T!4PN7amMQlAG+m;5$Gqla+&6zp+}HOjz14BEil@3)>Na#>^Ww6ySrbRk zE^`mwc-4{%^162lIctp1sVT?7Fe*?f>od3f$}b z_uHM}8c%lJ+0#kxKX>=j>+1fqrx_hX$;+?dp10Sr|LpDcb^q}`xM#gh?!Scd#1qf; zbfNO)&2^X8*9E&gbHwEhch7TlL}n%e80p#LH&7UHS43xyv*Ec6s*biOXB!p649*thc~j zp1mGVylk-xl`qfhRdIQl?qyt_yDRV?m$%$q-gR8rm0ouJe_dX}U7lS}_Ws%LXD;t{ z_q@Fi_OY<1hIt{cX-4q8{oh_@|G7``|M7YQ+lRdVuJOd{?Qp@K=V^_5Jucgtyi8@&%0mV40lLAz2Gjd1H&D8TXy94ioH18A>{s0kb4Z}p0`Jz zc6s)3w~uk950}@|`7`4@ae3J;RDQiC?*03KS8_*QuhPTR76r|x=ezGwv}sq+qFsyD zx$a951%;LV-=KD;pF=_BDG83*mSH}Uk5-38%;3qx-l2^V_J{(3)s zLZa~LBVOTb_$N+-I~Zur_q`%|XBH98u?#TK!)s-sLWZOX&Vn z)dt?-+|ckN_1&er2i1q`S9<>V?OmG_- z^01eSXY}!&O8!a{HM%}^`JwJlM!l}RG8TFn?)P@!A{;v8kY>CWb$`CA^0n#CN(ogd zvd6ul)XDBsV@gV7iF>7#l;~s^{Tl8Al`^oFdmQDy?;N?+y~LkquQjOlsAP(M;jZ_T z)W}BnStunndYrpv!{La1B`hTzecio^Z=Y}dld5*J=hwM6?H5$Do1n;YJ3myVySvCL z;c%mf{o%rBclS4#HP%n19Oq`C7jB|?teY*oa8u1=+-&Lo)_l!+ZnpBm%{1$}+1d-A zq*=$!HtsLp)2!`gTQA&PvzD9fyl}o|O*h-SpWWB2;bx(Gw+gkZ+jj3)3+-yQ-8vF+Zq*4o*&-TT%?J7L?sb8WTbw%vQzPCLuCd-vLFXWDk}UkB|Bw_CXP zucLOlZTJ3l(vI17?_X!_G~4d|J6Su`wtN4&Xh&_k_phsV72EFp>!uyC?cTrc+F{%7 z{p+Fa+jj3?Pwf=9Te|nJmv+dud;fZCI|ixYa6|t^cm1a=Ha{mMf370!BllS=+$Xx( zy@CljC1QW@G$~|&PL+^>ni6uVri2XAl#s!i5;80M#va#gpAcjNQpK= z#%UvDyf#86Xd`5zHbN$8BV@96Af%sv&|Uv&ZB0f0K*#`h3l*LcH900^M#TP5a#F}l zohl)-G$o`|Q$or#C1kdygv`;Dkn=PpWUi)!%+r*R^EDB2fi^E;jgSS} z2wA9&kc+hua)~xV7HK17u{J_3)ker=+6cK^8zD=y5psn#Lax+C$W_`1S*neYtF;lb zOdBD~wGpyHI}kF>&vc(m(qirtPI!7Cz02ec8gMH?XxY9r(!ZG>#qM##h3 zfsj>xzPtX@vg|hG+Ca$p_WUDJlVd_2kJt}0B!xVoQzc}(ri47HDIq&FCFChh3E8PB zA-gmsA$znD@`^S>Ue!j( zYuX6etBsJ?wGr}$HbVAkBjinOguJDVkhirF@{Tq_-ql9Pd)f$jUpo-8%^%{f|Fmly zhwx*8kT!Oo<3+vLJsIu3Hd}*LO#`$kk2$FC%9AwOy(FHbQ>W zM#%5l2sxsSkUz8$@~1XJ{?bOsQEi0$t&Na>v=Q>Jb|Bzo=-5x)g+mehF{tFvZbm{nTR(MIg{_~ui?a1ocd2as)Lj}|KXn&l>!jIDF$8|@Kbm73H;RE z@dSSAt^t9cx@$;qKr+Mb&v^TfJ0P*!?Cyyl3KYF<_ghW~MU9s!Y8r~zkI^L+oyhr8 z)Ql}fC$Xg{k1a*b*;16xmZAc-6cw_is0CY!TC!2pih!cl1QfL)pr|bYMePVEYEM8> z2Lg&Z5>V8MfTGR>6rD^!Q5OP=x)M;-jew%=1Qhikpr|JSMZE|p>PV8S z5GZOKO8)te*kyK8)I^GQ8ma!FsQEHQr-mZ-W0*-rgE(J`2D7DT2wRGVvZZJkTZ)FW zrDz0OicVuo(dld{8p%e{83YuaNkGwA1QeZ3K+!n_6rD>zQ4s+}qX;M}CZK3E0Yzg7 zC>l#ZQ3(M>;|M4kPe9QG0*WRQP&A2vqR9jlO(CFYDgi~)2!WyjA-}f+65Hx#c%T&J z8mZ~-kIUFsc%7osP{e+WH>s$M^QCAuTZ-nerRY4i6wPHz(LA;kozIq{3)oULpDjff zvQcyq0YwW4C|XEB(ZvK5T|z+7A_9sQ6Hs(10Y#S)P;@x~MN0@Mx`KeBD+wsNih!b} z1QcCOK+!S+ik1^lw1R-5l>`)BLqO3gLZE17$Y1J!#4_C@?eHuq%1b`Z3PsJADOwYX z*pGoH72Ux3QnZ#WMK`jgXdPRMZemN(&1@-J&z7QF*iy8CEk(DoQM8eOqD=%8-9|vs z?F1BUCZOmJ0*dY=py)0FitZ+$=pF)!?j@k;J_3sFC!pv70*bZ}Q1l=HMGp~Bw3UFO zhY2Wpgn*()2`Jh|2ozl(^51YkVs9Iq)lziWeQP27SSV_~Owp5}i2XGJNkuz2Uy7b$ zOVLiY6zyV5(bH@xdWJ1UyV+9oEL)16V@uKVY!tmfK+%f?6um@1(aQuB?IED(6#|N0 zC7|dv0*dw$Q1m(hMQ;#Lw2y$IHwh?ui-4lH2`GApfTDK^D0+{8qW1|X`hb9<{R9+! zNC*@?5%O!f@BYUQ*#r0OQnbhJU4ImcnlDrIX((cU4MkGXXPhrZpR=Xt3$_$}$(Ew8 z*i!U0TZ+D6OVPJ%DLTlOqVL!!`ksKI9|$P=k$|E@1QZ=6py($8ihd@b=obQtekGvj zHv)=&C!pvE0Y!fhQ1mAOMSl@cbd-RizX>S%hk&Ag2`KVX${*!tB)=aOBA_UR5GXnj z^3QcZVrSdU&nHqe&Tg3el&JYKMbVUq{WT^@MX8)GMQLm)im|0Aoh?NfY$?iQOHmeE zisEc3O0cCUn~kCz0*a~yeKv5k6is}+jRF8n7V+bfZ zmVlz;2q?-Wpr}3pMaL6R)PR7Zh6EIyK;X8h5dlSw34x+WioeMLiA`|deGgYj2_ES` zZMQ{DQljR|6rGe3vA+fqolHPc7Xpg95>V8QfTHdM6!jpWs3!qMy$C4k zO+Zl}0*d+)P}GlrqW%OFokBp-079VX#1#Kq2P9U*{rRDAGbxJNBmIFXQS)VrhNML7 zuTe@W8p`=nG>k1p!`V_af-Oa-v8CvAwiJzIOVJr@DLRuaMQ5>5bT$D+=MYeIE&)YF z1Qd-Tps1LDqR|8tjUk|DECEF&1Qd-UplCb+MH2`pnn*y=Bm#;i6HqjTfTF1c6ip+b zXgUE!GYBY}NeC1TO7ROEkl5*VTQpdTzOqkmvr?kw%M{H?iP&Gml~i;d=S$ICwiL}{ zOVRmkDY}3yMf2HGbRk=cE@Dg30=5(_WTWU}0*WpnplA^RMT-e2x|D#T%LpjCoPeSw z1QcCCK+%;16kSC?(NY46t|p*p839Gh2`E}YK+#G9imoA`XcYlP*Ah^49RWqx69PqL zDgGP>BzB^GiD(y6y3y@qMO-Lw4NWII0YzI0D0-NHqDKfQdX#{oZ3GlOMnKWy1Qb0%2o&9r;%|3AVk<%p&RQw@ z&~A&ir$o({DcYG5vA+f|d0VuL^QGu%wiG?XmZIHkDSDPIMbELN=y|pjy}*{D7uizu z5*tM?6Hv5=fTC9jD0-EEqSpv0+Dkyu>jV_NK|s+y0*c-wpy(|Eiryxm=p6!z-X);u zJpzi}C!pv90*dw%Q1l@IMIRAR^f3WN2MB?p9VvcFGpFbR`>NwpQq=wAYg+@CKVv_EzlBA_URfFhrOqA&qP5kjEovlPFt0}>l$w?&^z(H?uGU&W7_FH;or zBlg#jCKaV~z7%D!r6`jvMOkbqinFCC!Iq+IwiM;CrKl=fimI_uRGomL8Uz&8B%r7k z0Y$Y5D5^t1QC$Lx>JdRv;0Y$k46xAo7=y(E(8W2#_kbt5S2qVuY^{^d9Ap(k02q^LiC<+r$6d|Cf3IRn?0*X=zfub*czl8%5E3hwDe zplApIMMDXJqJpr$!vTpcax+{gMf>fxXjnLEzD&{S;fVb+M#rqNxNFO(URaIsrv92q>CKK+!A$ib@G6DkGq1HUUL*2q-#_5GWcE_QO4$ zqOa|%j;Bdc-{b?faMXO6qWR&7{WDleMHh0u6kWuYq6KUzTF927i`i0i30sO5v88A+ zTZ%4aOVMR)6kSe0(GmiRt{|Z3N&tstOiB>_d(5Ky#= zfTC*&D7ub-qU#ALT1`OF8Ul)LAfRY10Yx_wP_&K^C^|pv_jf>I>+P$K7jRo-e@x`2 zaMXO6q7C7Q{WEGwMYnRk6m4Wn(I&PO-Nu%p+u2gInJqqw##mdZjqvy_8INzaMXO6qUXX9`)Bx) zik|0uDSCk|MK7|Y=q0ukz08)PJ!~m@g)K#|vZd%XwiNAUqv&-4iryfgXdeMZZxT@S z76CZCL5<9^@i9IVtSKA}~ufkFDWr_}lBlgcYCKY|h`BL;fTZ(>Q zOVN*PDLTZKqQh({`iU(?KeMIi7q%4r%0|&|1Qh*FK+zEbivA#==uZNQ{vx30C;>%( z6HxRI0Y(23P~=7QupLDq0*X=yDDnv?3KLKiA)u%V0Yy;)ic$$EN+X~sMnF+IAyD*9 z*snLxDQaSWk;AuA^rd}9%ZNnHmnlj_BKFUKCKY9Kz7*xKrKl=fimI`ts5)DUYOtlK zCR>VXv8AXsTZ-ziQB;?JqIv`r9Ya9Tu>=$yM?g_70Y&cLMhpJD1&WR*pr`=>MGXlk zI)Q+qMg$Z!CZMPZ0Yyy-C_0gVqGkjXokT!U9sxz}A6N^1aVW|sps0WlD9VcXqaBb~ z*#6vgJQ6(8f7AZ3QDG!%zD!Z;NW}gb*`%U2oG(TH4{`q;9aSB-ZQpw`*_mWgW)iv} z1O)*VLg*k!uhNU6q9H)&5J&<7qJV%RB1IGsQA9*6h$7e8BwiKPlmZFYqDeAHC7`Gq0Y%*jDC$8#QBMMjdJ$06n}DJ|1Qhippr{`KMQ0FD)SrN&0R$8c zB%o*z0Y!reC>laQ(NF@4h7nLSoPeScgg{YCKYXhL5_Nwoqx)+CrD(m~7M$b2Y$-b3?j&94N6eQgTHyQk&sZlEE#!PDTEv#3 zOW0Dhm@P$1*iy8VEk&2IrRXxY6fI**(dBFuEhnJp3Id8&5Kwd_0YxhbC|X58(P{#U z)(}v16#+$S2`IXnfTC*%C|XBA(Ru=kHV{yBEdfOv2`IXbfTB$V6kSh1(G3I?Z6*YY zF7m^z9FVB}`_jo5OVJBWEo>>;&X%HE*-~^HTZ(RH zOVJ%{DcZr7qC44Aw3CgZy9g+{n}DKS1QgvvK+$djiuMptbT0u#_YqKZKLJG#5K#0W z0YwiHQ1mbXMUN0r^e6#Ej}cJxH~~d_2`GAkfTAY}D0+&3qNfRgqMQ8iJO?B?#_kGj zm7?d|%aWh*Bj(E#z2N)Tog+p2IA4lhWJ}S0wiLa@mZF#0QuGR2iVm=)=vB59y~dWJ zgKQMNPC(Hc1QfkVK+#(S6unJA(K`eby-PsRdju36BB1Df0*XE$py)#aiVhP{^br9? z9}`gY2?0f)5>WIR0Y#q^Q1k@>MPCw7^c5jc^qe2w>wrYvKPurRKQBf5jMUeD#C(~e z?|uKHQBw2+=S$HMwiNxymZG27QuH%hihf~B(XVVN`i(6`zq6(2C>uq85K#0d0Y!fi zP;`udqQ40!`iFp`e+ek^QuMe6MIi!;k_adY6Ht^)K#@;CQ3?S?5dw-*2`EYS*y2o!zmhf~gTitPKY$=^xQ#dcRamJ%^vrl?Aa->5)}s&c**Rbxw0 zb+#1MU`tU=wiMN3OVM#`DXPtuqB?9TI-ZT9x&#!}BcLdkfTH>Y6rDgo(TM~UH6Wm< zApu1v5m3~KfTG3(6g45B=wt$lP9dP^R04{c5>V8PfTBDCikcHplutlW3j&H-5&}ip zDdGMONOZH^yUs}o9_eS;!~Rw&5%Xn=+NJo@3Zm|v;RF0*cNeplBo^P}C+Re3b(doov5}wUwgV z?Asw{r$o$`DLOC3-#u1}&gXn7Dqu^|Xtop;vZZJYTZ+cArDz;mii+4$G@dO*6WA!4 zNI=mf0*WRRP&9>rqNxNFO(URaIsrw+1Qg96plBumMI{6jl@d@?MnKUl0*Yo6P;>zS zMRN!!noB^@JOYX?B%o+M0Yw)P0!8Phgx_{RqSxD>FB&C9b?tYwi&G-z%M@Lb;{Q=3 zMTQU2G}3n=M7V*eJS(fTG<56zw6P=w1Sf?jxY+egcXfAfV_$0*W3Y zpy*)&iXI`L=urZS9wVUWaRQ3=5>WI60Yy&|Q1lc5MNbn@^b7$-&k|7d93fD&EhRk8 z0f}z3o1a^xsH%*`h@+C_M#MZvWNZO zr9{k^Df%(Re{rf5{lxiF^fOzEeql?|uWTv$jV(pLv!&=LTZ;Z*OVOWfDf)|zqGJRU z{Y^m8KLiy0OF)qq(ZhBWg$O80BA_TtKv6OQMLq#VDFhTn2q;P=peT)iq9_4H=>!yI z5Kxp!Kv5O}MKJ=3;sg|B69Pp)q=b(+Akisy^K(Rs*4e%5oJhocnWE|uKf73pYH+?3 z)nrRiEw&UL$CjenY$>Y4mZIa?QdE~MMfKQHl*>j@eFBP3AfV_(0*V?CP}GosqLTPaZfTH096pbLD=u85N&LW^_BmqTd6Hs&x0Y&E$0!8g3;rR|o)cpg~ z?w{h5q7`;qG%6A?U#4hu#J|2&iV8VjipH>|Xe?Wb#<8WSh%H6q*-|utEkzUAQZ$Jz zMU&YmnnFO)R04{o5l}RpfTCgoie?Z{G?Rd$5(0`!2`DNfplB8WMY9Pgx`2S9IRq5V zC7@^?0Yw)QP&A)_qKgP9x|o2X1q2i=Bm|1ikA$CeK%&*`VOfC`J!yXkdr>4}zD&{5 zi2sTE$8!_kjlGofrRXxY6fI**(dBF@TF#cDE7(%Bf-OZ?vZZJxTZ&e(QM8(XqBR5* zT}43AS^|o$CZOmV0*clVP_&+aq74KTT}wdGMgoeiBcNy#0Y%pnP;>(UMVkpIx{-jQ zEd&(ZL_pD20*Y=XplBN*P_#G_PMz%(ZE-Vsi4@&szoXp}iI^`_bbG{aGDnK;;Cw0C z!Iq*s*;2HVEk$>+rRZ+96zyV5(LHP_+Rc`tJ!}-+OF+?m1Qgv*K+yvP6g@~l(L)3j zJxoB+BLoyZNWIW0Y!%hD0-iOq7Mit`jCL4!vqw4L_pEU1QdNj zK+&fJ6n#cO(dPsdeL+Ccmjo1jML^Nl1QdNkK+(4Z6n#fP(f0%t{Xhs5y%Y&w?SMpw z*j=HQrD&Vo79EL1%$F(pCF0*ZUy6R^d@1^kEk(bxrRXSIivD0r(VuK7`im_^$JkQz zH(QGSVWa3@0*bs;J#0r&h=8Ib0*b-}6eSZ-F#$zQ2q-$4fTB|fC_0sZqNW5CH6x%XkAR})1Qg{HP}G8eqLu^{wIZOXH33C! z2q-6kfJ2}9qr}Ri1{)_uci8DFPEZ&oG(SMv!&<_wiLa| zmZG=VQuH=kir!&M(YtIZdXFtdhuA23pMatd2q^lHfTF_$6n#WM(Z>W7eL_Idrvwyz zMnKW$1QdNiK+%^36n#ZN(bohNeM3Oew*(Y@M?lf{1Qh*1K+zEbihd-Z=qEy;=s;@t zVh6p3)w%XM$DHf`aRX(yh4hOa=sM(!Iq*w*;4cuTZ)dcrRZ?6G66+C0YxbU6h#OqN+qBujew#k0Y&Kq6lD-llu1BQ z76C;u0*c}U6lD`oltVyK6#|N?5>Ql)fTHRI6xAREihfNEKka}-3+?9THz_)5UxKWe z7BOF@s7{*y*-9xop7W)sE?bJ~v85=NEk*U&Qgi}aicVxpQ3JLVHDpWCNo*7~BA}=- z0Yyy+C_0&dqEiScI+cK;rUVo0Yz;HC~8YU zQ9A;P+7nRJfqe^|+BmI7f2W)8(^JR*Qk^Kv5|HMP&pO%_5*^HUUK!5KuISfTFns6wM=` z=t2UD<`YnK5dlRP6Hv5(fTD#26fGj4=n?{o786jkgn*)@1QcCL2o#M=3$JrPqPy&? zjzv=RyZuG{m!(C_mnpg;&A zmZEFeC|XBA(Ru=kHV{yBEdfOv2`IXbfTB$V6kSh1(G3I?Z6=`TMgoeq5Kwdz0YzI0 zD7u+|qHP2e-9kXob^?lSC7|dw0*Y=Ypy&=lpy=|n@F52z+SASCH+=mi3b_7PC@A^}DF z2`GArfTEWPD0+o}q636L(ayB+2^*ZE=Jsv;yQFBRJw|&qEn>b*(Hm)g_l;8YCg)4h zTWl$Mn=M7}u%+l-wiLa`mZC#!DSDqRMIW%G=tDM&4iixH5dlRX6HxRC0Y#q@Q1lrA zMV}K;^aTM$UlLIC6#+$G6HxRG0Y%>uQ1l%EMc)%p^aBA!M+hkTk$|F~2q^lQfTCXr zDEgHUC_0!Hp6Gx?I~bhTrRXvH*6eR-5%Xn={!H^P-y}tUalRBCV@uKBY$^JOEk*yb zrO4f}5B}aRDGITrD2XjaVYU<{vr*&|P?SPIQG|e^R04|92q=mYP?SzUQ3e4;nFJJN z5l|E(peRm2Q8ocZIRq3{A)u%#0Y%jaD5_3CQ4Io$Y7$UXi-4lz2!W!bY2lp?NOZs5 zFZx4@j8($|IntIRQoa1QfL(pr|DQMXd-ZYE3{<8v=^j5>V8R zfTH#U6m=k==rjU~IucOSiGZTh2`K7J2oxP34gcbRL=W1{Pu*znNPoADF42hjGDSV2 zezh%9)RXh2s25v`db6dd4_k`*vZbgWTZ+zLOHqHe6b)cY(Lgqe1`$v+n1G@o1QZP= zplBEYMZ*aw8bLtOnFJJ_ML^L=0*cNipy(U|iq0jVXcPfO=MhkJJ^@7q1Qd-Xps0|5 zqA>&%jU}LH93fEDEgJ6NfJE(YDoXAyMYq`~ibl+rDVh}Z&)q6TlR00Crm&@GDqD)C zv88A_TZ)R=QZ$1tMKjq_RKk{`QZ|ap2q>CGK+$XhiY_3aXbu5Ia|tM#M?leq1Qg9D zpy(n3iY_LgXaNC53kfJ%L_pCc1QabMplAsJMN0`Nx|D#T%Lpi1MnKW!gh0`RXn3Im z620ASekMxMR=bn5JQ^`yrf6l<-?B}LR&l-*t!7Kn8nzT&#g?MAY$>{$Ek)O`rDz>n ziq^BGXagHX*Ah^)k$|G>2q@Y_K+*LC6x~2T(PjdQZX}>+3jswp5m2<1fTEiTDB4Cq z(JcfNZ6~1URsxD{BcSMZ0*dY+plAmHMRyWVw384hS`iID>wrX0vv1>HDMh*VNdK;A z#C(~e-BJIG?NYRd^QGuswiMmRmZJOFQuF{@iXLQ3(L-!0dYCOmkFcfaQ8tPmBcSMU z0*dw$Q1k==MNbk?^b`R_PZLn|3;{*Y5>WIU0Y%RfQ1k);Mf(USdXa#l{R9-fL_pEY z1QfkOK+ypLie4q4=rsb04iW-IyQ1NYTb-hR49-1Lv?1|;EgCUjrs(ac-}H7VdWZ9+ z=v}rHy~mcKLu@H}pDjfnu%+ljwiF#^OVLMcDf*a=qE84Y`jmj8&j={`oPeS)2q^lJ zfTFJmDEgX!qHhQ&`j&vA?+7URo`9ks2q-#2K+%r`6#Ya%(a!`F{X#&|uLKnRMnKW; z1QZ=51d85_hKD*J(Ju_nTT;~DetY{P8Zlp{=ybKv6XUimDS(RD*z`ngkTpBB1Cv0*Y!AP*jJ2qT>mHqQ9cy4Gu{3pxqW7 zlcII*Wyy8ZBj(E#osjN7xKoNw=&2 zBcP~=fTHmP6ipxmih8Dp8|-q5uCzZ4(o2f2a4$=qm>w}-rf6!q-*dMVP2+qin$DJ@ zVzv~`U`x?VwiK1HrKprGMP+O$n#Go)*=!VDKtRzP0*dAmP&AK#q6-NqnomH{MFbRG zOhC~B0*V$AP_&4EqDu%UT1-IE5(0{r5>Rw00Y#S)P_&GIqRR;=T24UG6$BKmAOwmg zr-vsyAkqHzhe4)D(OGsU>B{to`7%Xo()}y$m7=RSUy9bUrRZw56kWrXqIGO3TF;iE z4Qwg8mMuja*-~^J8%3K4D7v12q8kV(+Dt&vjRX{JA)x3c0*ba0P;@f^McW7{x`lwE z?F1CvNMNbk?^b`R_PZLn|3;{*Y5>WIU0Y%RfQ1k);Mf(USdXa#l{R9-fL_pEY1QfkO zK+ypLie4q4=rsb04iZrGIsrv*5K#0cAyBj@J^Y&k65V6p)4x}W7AGFCrAN${DS9v6 zuknx+9pZc`dY>&tAF!q9L$(whW=qjWY$^JfEk&QOrRY<(6n(}<(dPsdeL+Ccmjo1j zML^Nl1QdNkK+(4Z6n#fP(f0%t{Xjs`5dw;SB%tUg0*Zbnpy(F@ihd=a=r;n2ekY*l zC;>%(5K#0d0Y!fi0!8nnhdVkT(bw$W^}ABk#%_y_rAN${De^M>^B$3+P=+4KOHmSA zio$FuN@h!u&z7PTwiHF!Qk2S;qBOP?McF7yC!i>UfTBzSin0hOiV;v0C!i>sfTA1% zimDJ$RF#0DY6KKjC!nYX0YxP|pW4+4sM5&}ghW`v)2K%y_$ZBc`a;E{ga z3^#gZM9h~d>X+evwO5MH;Cw0S&z7PAY$+PZmZCvyDH_a{q9JT48p@WUVQeWH&PLG) z0*cNgpy(_DibfJpbT$D+=MYeIE&)ZO2q-#_fTHsWC@LVJXfy#ug#;9hA)sh10Y&2o zC@LbLXgmQ$69_1pNI=mf0*WRR0!4i?!dXu^MZSI2v9A=_UpSLIB_m?KOi^)$pZAm$ z&ER|~n#q=;61EhTvZbhuEk(1~QZ$<_MHjH8XbxM7=CV;VkAR{J2`HLRK+#166kSX} z(EkbSVKvml063jDVuc2`E}lK+zQh6s;hj=t=^L zRuWLOiV!H8mJuHAfJF1{4)t^?>TY9oM#OxXqN_9fS)2AXo-IWi*iv*Y zTZ%TarRX}g6m4Ql(e-R8x`B)$PNI=mR0*Y=TplB-rMK=>rw2gqGTL>uHPC(JE z1QgvyK+)|46x~5U(GCKN?j)dSCjmuw5m0nD0Y$qAD7uG$qTK`(?I8q;uF42+bU>m< z?2-OjDJo4oV9SV@FH`hjhX3$$QuGk#OVPt@DSCu0MUS$j=rOhwJB)=s5z4o+qH_1pD0+#2qL&FMdWC?Z0|XSk zN^=r00_juBAwHvvWe5CTPqGQuZ0AkmG!gY&)=y==Ed|7JwYmnjNo`n~r{QF7*g zAL;vSDN12WQG_i;scb1qV@pw#Ek)^UDav3=Q6?KjSp*ct2q=mZP?SwTQ4Rq`RR}1m zNfD4#7wE!Ze(NkCC60*YD_P}GKiqP7GSwIiUYJpn}>2q-#@fTE5B z6m=q?=yU>#IulUTg@B^21Qc~6pr|_mMLh^8>PbLRF9M2s6HwHL5GXn+GklK&5^Z8| z8cEU7up50dBj(E#4aoEl9+0AeoG(R#*itl@Ek#4vQZ$q;MZ?%qG@LC(BiK@OCR>Wm zVxwpz0YzsMP;?FfMduPwG>U+t^9U$9pMatQ0*XcxP*g}j(HH`X#u898j)0;f0*b~H zP&9#nqKO0)O(LLZG66+X2q>CLK+!Zppy-Uu@KFaOI>&B{`b&|0nJ9UBX2g7%qLNI% z)p8iZJI?3*8ug#2@FH^KW(=T{KiZ*b*6kW@fqK#}R zx{fVHo7hrxJzI)yU`x?vwiMmSmZB|e6x~EX(N+SAZYH2;8v#YP5Ky$8fTCLoD7uY+ zqT2~5x`TkC9Rw8JNkGv~0*dY;py+M_igpoDbPoYVy9p@TLqO5J1QgvzK+*k#K+!ds z;Ux}8bf10Iah(*6wtLqPWJb)FDS9N+-}aUiJ<9n~^cY);9%oC@UbYlH!Iq*Y*;4cr zTZ*1$OVKlIDSDQTqUQ)GdY*uy7YHcYM?lew1QhKjpy(w6ie4t5=oJEr4iHfEDgi~W z5m0oHfTGt4D0+i{qBjXBdW(Rfw+SeEhk&AY2`GAxfTBZ$K+!{);e8HB^g+A%d02{m zuy2RFpBXV_u%#%IEk#*uDT=YBD9%PvHUULB1Qb;vpr|SV zMb!u>s!l*r4FZa45>Ql&fTH6FD5_0BQ5^z`jwhg~E&)aL2q?-Wpr}3pMJEtYbRq#o z4G1V|NI=m^gg{YpR`^T@BzmL4@w0+Q`tF{#d%%_zF<++Wlq~;(52WZ+&X=O5Y$s51dYT?i=ZNuu*g_0Y#$-C_0aTqVowTDj=X}Gyz401Qd-SplB=sMdJu4Dk7k0JOM=$ z2q>CJK+z-uiY60KG=+eosRR^FBcNzH0Y$|G6wM$6iUwwdKXyQ(IrbQBkQDu4q-JJC z%$F&emF0&&k)qk0FGUxyrDzUYisrJVXdYXNE@Vs5e6|!_#FnCq*;2HCjiQAF6fGj4 z=n?{o786jkgn*)@1QcCLK+$Cc6fGm5=yC#zmJ?8P1p!4X2q?OefTEQI6s;nlXf**v zYX~U1ih!cE1QcCOK+!dXKv8K{xUmBgt!r?~r07$-cfBqvV!lk##w@?@XHs+>=S$Hh zwiI2@mZBTjQnZ;ZMK`jgXbW44ZemN(R<;z~%tp~R0*Y=SplCY*MYj@AbQ=Lhw-Zow z2LVMp2q?OffTEoQ6x~HY(cJ_T?INJ)9s-JX6Hv5=fTDW|D7ue;qWcLbdVqkU2MH*8 zh!7~+kQJWpfJ6)ItB%)7(Fl8_|8Q2se3_!hv;0+GNYP%-m!c=wQuHKSik@Oi(bH@x zdWJ1U&$6ZHIkpr%&z7PW*eKdZK+%f?6zwOV=p_P*UM8UE6#|M55K#0g0Y$G7P;`)h zqSpy1dV_$XHwh?ui-4lH2`GApfTDK^D0+{8qC*4}y-z^V2Lu#-NC*@?nibyTfJCd? zU7^RM=#c&K*~3{8^JR)Y&GO&)N{T+?d@1^zEk$3jrRYnx6n({(qOaLf^bK2zzGX|% zcWf#8o{gd(2q-#2K+%r`6#Ya%(a!`F{X#&|uLKnRMnKW;1QZ=5py&?*ivA>^=r00_ zjuBAwHvvWe5K#0l0YzR+58F``BA_UVfTAz~MahIf(Z^ZgKOKKv6XUimDS( zRD*z`ngkTpBB1Cv0*Y!AP*jJ2qT>lDs!KpoJpzhy2`H*hK+y>V6rD&wQ3C>s8WK=+ z5&=bx2q2C!nYU0Y#?~P}GrtqD}-9olZbeX99}4 z5Kz>WfTC^$6m=({s0RT>Jqal4MLL$s z$pjQlA)sg~0Y%dYD4I?{Q858UGYBY}NkCBv0Y#;RK+%v`c)tS@ooHXX9x6o*?Y5{a z7BOF@Xim)k?k6dl%lT3?k1a(PvZZJ~TZ%4XOVPz_DO$jmqJ?ZJTEv#3OV}t{OhC~R z0*aOrP;@B)MVAp!w2XkF%Lyo2PC(HW1Qe|xpy)~hidGU(w2FYD)dUo+A)x3g0*clW zP;@l`Mb{8ew2pwH^#l}cAOwnL$HF;3J4Ge-eY6XtXqE5AwXul#GDX+N{Fc8;(G8q0 zMVr}DbR%1ewy>q>Cbkr9WlPb`Y$@8tmZDqOQna0oqFV_lx{ZLM+X*PTgMgwP1Qgv# zK+#SDitZwy=xzdvb`el?4*^BH2`Jh_K+(Mf6x~Na(ftGzJwQOwg9H>kL_pEQ1Qb0& zK+&UwK+$!v@JI(F+RAQ=Hc8QF`yK7ESj2ppq9DbAOor`b~U3|oqxWlPa> zY$BML^Lp0*d}7py(e0 zivA^_$cyV?JBmUC6eST*6egf3nSdgnfT9!viXwzS(Py#nrw&N8sloYNibmLNQEEJ5 zzD!X@-1m=3Q6}e0Q5IW@Vr(gjv!y7TEk!wODXPMjqN;2us>YV0>TDF%AfTuw0Y$Y4 zC_0XSqS^!$)ghqhcmj&*5>Ql+fTCOiis}P0|NZvu+?5Kz>YfTDf`6rDjpQGWu81`tp*kbt5=1QZP>plApo zP?Q%B&u~DZAK1O?=2Eo8ZkUF~Bj(E#of-Gnc=iUGd&y^Uz7&mQOVQbEDLRKOMdz}m zXcSwD&SOi_`D`gFU`x?xHi`-fC>ldR(O3eC#t~3dL_pDa0*WROP&AQ%qDcf4O(vjd z3IRn^2`HLIK+$vpii!y+nn6I(Oah8Z2q-Egps0+1qFDqK%_anjhR4JAIUv#Y_N}uK zQj~3v^e>1<%$F&;Fz&yVBt`Q%Uy3ebOVPz_DO$jmqJ?ZJTEv#3OW0Dhm@P$1*iy8V zjiO5lD7uV*qGbdWT~0vJasrC3AfRXk0Yz65P_&YOqE!SGttOyo4FN@05m2<2fTF7j zD7uD#qIComttX&p0|7T{}fTHUNfugzb@G%D@dZvBtdY%-`wcDai@rd~{MK{L% zf(CZK2!0Y&!`P;?&wMfVd>^Z)@x4-!!H5CKIG6HxRB z0Y#4zQ1lo9MUN9uw3iSlx*;C!=72=&*v-#oDe7#0Oyr4p#C(~eXX5_Yh!j1``BL;8 zTZ*1%OVJB#DcZ-Dq8Hgxw4W_SFR`WQWwsQ(!bZ^n0*YQGpy)LMiVhM`^g01WZxB%Q zCILln5m59t0Y&c+Q1mVVMeh+%bcleW_X#NafPkV82`D;DK+#786n#uU(I*5HeM&&l zXM{k}Q}OUJ2P9gQdE^KMb+3+RGlqFHP}*AlPyKH z*eE)VfTG$26xAW1=y(E(>Jm^?kAR|F0*dMrP;>$TMJEza)PR7Zh6EIyL_kp^0*V?F zP}GEgqLT?II)#9uQwb<)NHCZK2t z0YyUzC>lmU(Qrbbs6}@890w%2&h84el%f>7cReCIV!lk#+1dVuaVa{7^QGuqwiJzG zOVN33DLS7mMFngr8qJoXLbeo*VN20iHj2g(P*g-f(Rc!iCJ<0Gk$|E}1QbmsplAvK zMNi1{)_7iarVgW25MD0*aOsP;>x{`pRl>`*6BA{qB0Yz&FD7uP(qO}ART}?pI zH3Sr`BcNzK0Yw`KD7uz_qKyO;T}MFCCIX7CC!pvCLZE1VcKCA#B${nEKNm^SbQ_zq zBj(E#ZO!&0)uiZV&X=NXY$>{hEk)beQgka@if&^|(d}$0x`Qo6JJ?cmCmTgO2`IXY zfTFtzDB49p(LDqd?IxgT4*^B@5>Rv>0Y&!{Q1k!+MGq2C^bi3>4--)I2mwWp5>WIQ z0Y#4!P_&nTq9+I_dXj*mrwDU zOVLkkDf*c$MZd76=vTHB{l=D}-`OZSN)9sxzU1QgXLpy&hwicTb;r~v^*4GAbZiGZR;1QazUpr{D} zMJE$bbP54QrxH-qlz^gU1Qg{FP}H1&qI?31S`Y$7@tp8K4oGx~eTgVLCwQd4)Zs~P znG-Qzrl@U>U$3qdwc~s#YR{IU4s0npjV(nT*;3SrEk&oZrKmGoin_3+s4E*q-3Tb^ zPC!u)0*ZPPP}GZnqTU1)^&z0BF9AjU2q-#(fTI2c6b&GtXdnSag9s=ZOhC~P0*Zzb zP&AByqTvJ-jUb@tOah9|A_R(B=Y)GWAkk9{P8%sYVz)&jb0X%;6phO9i`>6RocKQ4 zd7Ljr=d-1#fGtI%*-})5~cs7bA5KuIcfTBqR6ip_eXbJ&E zQwb=VMnKVY0*Z3NM~KOg6Lr^ebJ?|IE*3+j1ZtJpL3 zJ+ECXy@BU-j14)-^SZ>=H}riP3hx#^JBaE zdEUa<@BKY*NvzW#&s!E-JjC->#9kQYd8=cwGd=I>*ocvyw;^`jIi9yE_R%QMyD`?N z!1Hd7O)K=gTVuP&dftxMA4Q&bcdYY7&)XAQI@$9ch`l(~^B#$17kl2`*jY0@@9Eg} zrJnbE?2}oZw?Edz{gW66V#V`3@AcTd^F8nF*k2cW-l166MV@y!cG+Uj`!x2_QqTJ` zR%MyzeH%M_x#t~;ZC>Gdzr;RU>3K(Er>yb3WAT}5-N!!^zyBI{1%%>%uXoo#DBgXe zy9z?_%Qv~}AQXS)26rWd;?=geYatXrcdNS^Lh&uz-1QKO+rMVtAQZQMj=XUwZvUS2 zsiC<2gTT#0ar+ltTZQ8GPja>k#qHlz>==sMKZ@5S6t{oXtVbwr|14FXP~84qq5h%x zS9{%c5{lcu>@hqPw||;pWGHTbxBjS5-2QU((V@8g?bhQ$ar^6uCx+to_sdQV#qBQ$ zoe_%L-|$!#irZh&HzyRgzhiBFC~kjA*1}NS{+6R9q4=YR-8B@7+ut*?A{4j3C}MRe zZa?XNbtrB>s=Xl;x1Y7$6pGsqOWqiY+fTdQ9E#hIE8QB3+s~Wq2*vFO2JQ~U?N5B~ z3B~P?>^=~R+n>37BowzlG`BYtw?FmtbSQ3rY~}e--2U9b{!rY$aeN>Yx9|MD9*Wzy zZr%>X?Q8FcLUH@z>ETe^zWViPC~jZA_%al?$DiMZ;`RXINGNXi0DlR^?YHowp}5@! z9}9WeOWY?-^3B1gT+S+YWwv*pR#oP^XFl}3swwW%$Zwt9*tKd$LhhPw>0aHLasP!j zRevOG<#;p*F#&x!t`^sBL1nPZh6~y~4%z7TRSkcF%h? z*1LBWYOhlp*=u*u=xuNGG>w5aI%*8H3)M;Eh`TWeovyJx>PBac@$T)1x&*^LmmO-D zRV6)~RXb}$jcljM^O72P>FKAt^z`5r zLT*Mfy>Ke8pPrtXo{`?p{Yp}6{O7gO+-p^Ot5Hoqcqi$4lWy9Z%+Q-mytLv?X6jAq zwX)nve#Pa8Wx7je?>U}$#`nBz{YvysazdfLRqV}IsqbDh&%Hv`R+TPP=UN?Wd0w?< zq0Y6qq>XB2hjLQ7)Lh@qy`;Kd>6Mde+~3W8*lJXM19jZ{u30(gmF&vZ(*}18d4uh6 zllw31%{XtfJ!7Dfy`MvaH@jyNPwp1oJvDa!C3(%uYn{Zlmjo}j=j`0dPnEa*`z>K_ zoO6*B`YS8b3%Muvx`w7%v%HeRyz!+o@=8m_=9Ltbjx8#fQBqu1G`6g0T;AA{xiiX& zEsQN1H>;$mw9?D$_1$Z?&zn&)Y1*W+NwbT*yotrrit-Al7R||PHnn(c;ncj+iG?La zc_l^Di%JVi^NLy&l$OmJH>o(UthjjU*olRcrkCbT7(2G0uw+_Ze)EEs1udGl$S=rm zZn3G0O{W)6FKSv;IA&7Q{N~MCHnkTwb1(kSi}EH-A3Jr{xT3sig<~g9n*RU!#VDOy zTKOX}VPam_l5w*pO)u_VTvF7u{9`evtR(Rv2|gl&ONuAEk9ld{uo;CVQ+mysUNGGK zS|$vhI;*r`XxBCaTL0g;nr0W471>A2^MWgS{H*C?TefK4Y^+fz7*{mDaMskag0i_Y zib|VJbmBaBb&Z=ez03`F3pK2J&jNQb$96BCHm!KNYfcqlCfS<~lIL!%eRr-S*D~b$ zRsK&;ekdh8A>`+TkIVI|H1%`(`&ByleoCI7lhRB_ce>lvLw=gOs}pMF$LtXE8`>cy z6wGFc7bc~&@awsp z|HnlOrBv~A>iMBgNg3`YVrb9a1-+X0@$8u2u6dt=F~PHKT9rTBx_kMvZQAKITeYKg z<>cnAf|vE|uGh(TuRN)Laq*0NZ$Q_P1>FY@ZxOuh9-Pv;{Qb2hwXAr*Ey~|-_eyV4 z7qA5vuF9QBi~(^#Ot?ruU1gt z&TiSFAb1P;?wxT$FWy>Ly|r!?Z^3;8+^db7HEr75;4SHOTk(#&Dzq)X0PX`?{+7$% zNh{t*kBSe5`w-|A-9-*QjP9)j&s4eyZ8_C_@DeX{A6T8&I(TCR_6e?=gy8fRI;UmD zW$9jiR(^NhoxAXQOQxXGZvy|fZu)u@jhQtexJd3gaPQ0AnpV0JbU9j8Tr_uu2d`fK zu|ZbzieF0m@{67C(0XU|JiDN4kD-b4+;z#vwBjxN=S**E@$?C~iU0jCSNRneq?_m< z%w2DZcL1q!GyzfjTGTG;4;+48qT(})n0&C*DbZ1*LpvDQL}kp>)};NH4CI3Q$~A z?iUc8$1`@7ByM^tu2y$zq>Ga8E(_1*S9~-oUAb*_I#)p8#@=ANiVv0hKnCxl1@Ell ziqChqR=kTI6{omsCpe|zO6EGq@1|e7T?6)>+LvEm_wm)+s<=^VskhYnKX06OS#fRW zSGu|@UCnLW=@kaKNy|rzz1S{;JMt#oB~B!+Hg{v97qu+^rMeFUuU>J*bDeUPmS2tS z+%L4a9BRdN!VSLNMCi@Ab9lo}VDKSy?>6y_`$+Jz@{8o&muq&5G~C@C(d%=fyFL=d zuH?k;Bf)PUJ6TobPTYJ$DDUB>4E`2M7HwSK%VR0!F#T3J>l#Q1|vrCl;5KmH(c_m1x!y zSAY36U;ewR`-Dkc2D^3=pF!^95kNmd;@Wf1 z^&U7Pw|o2cx%NP#S$?iP)M(zWMXTJ#B}G$<3QLQccIQ7~W3N@2;^iJja7m)Y%_PHQ&J zJ@h$cTxYOwFe!?gC6tjz0{z<|e&fvb_u!254yADoV?n?Iv zx!YNB_m5Ayd~Vk5u3_+j63pN}VB#ZTcRY1pH1R7AKE=yF3VceJ+lIE?0i9BQd&~XI ziu-~UcLhOSE};CLX8B#n@_UPwKAS2&Co1meafMgh%PYSkgPT;ZclYicavR&{PuG%Z zxjm1yKrbabG9WD+P0dNJ8mbnm5w01k z6*?|dJ5(oBH|c~>GyD3-|9GmLlD!}Qt^DG!JwmSZ6t+jlm7c=(0J+jr*gZJTuC(nd zHC5f-TizU+F3Axvw%+dJ22)Yy6d-!d|S>vbX== zOB43o7r-h#g}t0g%U-{l=f1F&_*L7-J;z=ChLv6;ZqNVEFCsK3^BRovhW_Vqgg$@v zx>rwf@6vra(@U~%P1w<0gLbLxSWQRw1vbw;`t<7C(fyJVU-@z`x9iqk&%R`8NB2F2 z#Ic)>gLNFCqx%v^;^mWdoT=ji9hd01TF0$A?s8YFz5PdZJm{__+aK!qtNR7m4!N(s z+OdZFwb=1Q9oxIB#dc2}&vm~B+Y@xW(OoUJ@6_>g_W`i|vyP`aB(~e@SW-RM3v_&- zX0V^p@t@;@onAXQ_Hf_8vGa%MxV&Dl*Xww|ePHe7@9S8-L9kEManwn{o}}YV?h3Hi zze~q2PY(94IyP$>?9+5Cb61qT{vsV8$`AH)I@;H}?d6#|_HtLK?O{5uXcz2jb$qQu zus_tXrn}lv5t@Q3-${-CJhL7 zOvgThf;~dVl|zDkosO>$3-(7k9(QK28|gTDWU!~{c*{A#-mT-eqk{d1jx7p;-C4&u zg~48`<6{oGeLP;&F?oEjvvuq@G1zD6xO#H1uh;R-slon4$2!HqZldFunZYjB@z&B{ z->c*Ivx5DXj;-bdyQ_}#<^}sQ9rw-;_DedZEC_ZL9s4f|_SrgKwK&+Db$okius_qW z?y_K?qT{&b!Jet(?JI(Pzm7*%2K#Rv+pGz8cOB=i4ff?aK6y>BU(qpjL$IsqIB;XI z&(-njO~KxxbPTDupiX%r|rT1SI2g@2fL?^7w-u6 z6*@k>GuW@{7~K`@8afW%9qjXTTz7A??JA_PJmm)G=dUuxsf!bbqi5blmWAu(#>>!GU0Zqho`E z!Oqul@*BavK*zh^3ihKq{`O9=!|w*ij)#I{UmY*`AlR#PeEx8--_SAZlVI1@arkG! zF4S@37s1}Hq2r(KyR^0=?#HC;*u{Oj){X;oywrW)*7jN*_q%W4+I~mJ9QU1E+x2uD z>At0FyGX|y-1l~E-=X8D?wh=}f7J10_uXFGZFQWH8|;g8yw83A*IxdVj&X_6h zxO^#gf5lxMcM%fDY#poVSXajrbacPHCSI?Dj*0VA-8V_K-68REcQ+?-EVcVT?(Ms~ zAzo6hN;M~k&v;W>DO!RT~ zC0+Nm^zp^+l*IFeW5$#e%?{2Aiu)E~}B@U$o=Q8ivPc_*WA6%|9ro%yT+4UclLCu`_J7S^}4wK>}g5I zP~z=ZchB4F*njr^`ndnN4DMO?M^>B%=Zhzv>)}G>x3|K*y*@73+cQVJz2WY8&T-Fr zH5-TAA1JZsf+wDJcTN8Dddr%Gyneh=rI(Fy&sToGulEckeogj%t@D0oRXWE#>%HdQ zUamc(C*JQ&w=2KBs=Y!9|MvFm(G+iQnR}jd+_ThJt?h++;$`dHuKe~|xwmK6lU+XdDOmpYZgJ1sIp)Eh+PVj`O)`S# z?f>>N`_KKB|DV?z-QjIqjE~>i=@Sn@qvC^-%ieAqy?~Cp~ zXMTn|B%Thrw`aFIJlXrSCp+@FV!P&P?)r7HhI`%~joSOQkGp+L_#AT2dLx}bGtLul z&u#-Nzg~ZL`QGD|+>zI-{IE5@S#h5G_C=d^&0Dl<(K^?CZK8R8rT@2S(<(Q&U8`1Y zn&;Zn=;(r;?yZJ+OZGM!m%m+mSIO>ux+g!lO=#@Za<`l__6+*P8{g%ps~S}ATfJY6 z0ihpPho3xpV07r4g`p>pK0P@6%|dVZ=wTB_dB@&(?WmU@&+mFP-qD_0)UE5$jKp(Y zkEZIF-0`bd{eD#@UKcv{`iw^g{jzu1!NM86?VWn@>Rlec>~OaX_c?h476 z>i*ZQ@<-aeZc-?vz#gN9Qm44zLz0sGWf40>rnnfc?tT$T18Ta*Jnmb@{!Q*B;kou& zgKCXVq{wIPI!Q|P?{vRIB&9~0xQ}{rvTt9uN=lBr>Ru&mzc+?YtqW^FfHd&#G29_MBo_m}!<)^fA0m)uOVrkm}&_ zAtN*qa;7#y&eBH6NNt3it&Na#v=MTyHbO>eBjh}7gq*L9kOFOljMhd-p*BLsXd`5- zHbTZ}Bcw*|XGC><56SWaCNgE-PwGlE!I}p-0{EfT*)4H09eu0qw?iMO}YQ*H2 zkQu)Hf#-yfnL1TMN;D;;R8vCAG$mw~ri9Gal#mNFC1j4Kgv`~Hka?O2xlkJ+^R*Fj zkv2ju)<(zzZGI&R2w0eX(MErHbO4fM#yq)gj}JG zkQLepxl$V;E42}_N*f`owF4p3!A+Km7D4HAwO#) z{Hq-Zc|Tm{uK%*U z`Sv4v2}LJ!z7(CpmZDSHQq+_!Ma|e!l*g8$=4>g-XG>8FwiLBwqo@@DMXd=aYC}L# zTLOyO5m3~gfT9ir6rDyuQAYxbIuTHGIsrwU2`K79Kv7o$in>6rDpr(YXW^jUu4vJOYZ&C!nZ+fTGa^ z6crLsG=_kpu>=&2BcP~=fTHmP6ipzYXd(eclL#o9OhC~T0*a;*P&AEzqUnS{QU6f5 zmje>r<7V;zDatic#qN)`*jHbjqSBCWKO&q^RL1#IG>a`ov)NK~0b7dZu%&1&TZ-nf zrRYMo6wPN#(M4<&T}(jH0s@K_5>T{=fTBwXC|XQF(GmiRmJ(2ODFH>75m2;@fTGI@ zC|XWH(G>&~tstQ2N&<>j5>T{?fTGm|6s;kk=qdt=))E3mGehAO4oI|yd!(IQB1LTz zkF!D%^JR)QgnauE^Ms;nIbVu4vZd%cwiIn*OVRagDY}6zMVr}DbR%1ewy>q>CN_$; z5>RwA0Y%#gD7uA!qU{6}-AX{wZ3GnEPC(He1QhKcpy*BligprEbQb|dcN0*wi-4kg z2q@Z3K+zroitZ(#=sp69?kAw=0Yac?T`2sT0}_4H;H;OT#J>&pU?^g~Owpqu-~Nh% zgrdhdUy2@QOVM7o6g|O~q9@r>^b}i)o@PtYGi)h(mMulku~GCq0YxtmP_&PLq8AA$ z+D|~yO9T|XOhC~q1QZ=0py*Wsie4k2=pX?_uM<%81_4EH5>WIO0Yz^UQ1lJ~Meh<& z^d134hX^QopAaZ|I25kwzB3>F(;m1#B1QY{-t`Bei1{)_ABTMVD=rd>KH+>R`jjn2 zpRuLrbG8(H!Iq*g*;4csTZ+DBOVKxMDf*U;qVEVO`ksKI9|$NqLO{`v1Qh*5K+(?x z6#YU#(XRv){YF61?*tSbC7|dJ0*d}5py)3GijEOb^fv)T{}530F9AhfQu(9&jKue& zLIe~g5duYrL*erskmz{#oz3Krq-ciSFolyM=F1dCl6?CsQWA<%IbVwYAL8yZI;y+x z`}RyG!@vZX0ou}*3T$=zd z?q2I*t@GS`Kgmu)=E!7bk|yo!P*k-;QIj2t+S{S1gB^-G+M%dshoZV2iaOa8brvY< zB2YA!K+)U+Me_(0brmR@SD|pg_?=0!0f86m=IUT122|QGuex z1d4hH6fG{eE?PpMXh|VgRBk9;oB^peWnXx2Y}1h6(|<5s7xiqYBwtCThF>TQRjK6WVTYlos{I~4V^Ls5S_6b-OL(Q&Zm{(lD#=$;v{6Gj{fMR(MH@Rm6m4RMqD}2kw3!`> zHn&637IrAw(hfyi*`a7_I}~kWQ?#u>(RKnw+Y1zp6e!w3plFmp(T)N|qXmk_2o#MK zC>keFG+v-+fwWM z2^1YKP;`Po(TM^@CkYgtEKqccK+&l}u4raMY1a%$b?NjF(X3E(TYA*-w1!IZl@y)T zP(H0^C_3Buq39et6rF2_qVw!fbiN&mF0ezq$PPsp+o9+Zo1#kviY^l z3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~? z4uPUO1&Zzxaz$q}l>@9<)Qz zLv|>7*bYUH*rDiAI}|-;hoZ;rQ1pZyik`G7dP<<^X@R0=1d5&&D0)ty=y`#n7X*r4 z6exO0py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zSqqbZDKiJ4VC08Df* zDEeEV=pTWie+7#E6DZ2Q1Np4%V$8mxo?U?H+fIuDMGXQ)C4r(wfugdIEBdIRG$I31 z-635UeH@CuPoqt#l6)ma)lxbAh|?BDP0kNR?d?$1!45?o?NC&+Ls8uhMV;(W)Y%S2 zUF=Xamrc>!0!8x(6m=CSnpdD`K7pe71&X=}6fGc7w4gxILIOn#3lw!1C|X3IXi!M{!mEQgGGACcRlsIT)wQL`P2`q`nVza5GO*r8}SI}{DHL(%efC>mskqQN#rD+m;=C{VPL zK+(zqMXLxDttwEonn2MIfuhv~iiQdl4HGCDE>N_FK+&24MI!`?))FXMTcBtifueN< ziq;b-T3?`O10h$`t5kY915&N02O4{aqEFLx(T1f;@|6^AS}La>vD~6)Gv|k*&FxUM zg&m5vv_sKWb|~7~4n^D8p=et>6m4gRqU~*pMhX<|AW$?)plC;dqR|3HV+4xE3KWeK zC>k$NG(n(fqCnA30!2Fu6ipH+nk-N>MWAS^K+!aTqFn@vrVA9!5Ga}{`=77 z9f}UHL(zeDC_2cd=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VI zc!8o51d2`+C^|`?=wyMSQv`}m6(~AQpy+ggqBDeC(Qc*E4jGVY_H(Zbjk|}UUg2C$CV`@x1&VGFD7sak=r)0(+Xag5 z5GcA+py)1vqPqo(?hz=uSI8BeT`FCg0jWNm6rB@_o=)SwQYHCHiXJMJ)2|3gfDXRI@`--3~>a>`>I%4nS|LouRzg!0!8x+6m=6QT0o#^L4l%$1d0|GDC#ayw1_~_q5?&W2^94ZC|X>gXbFL$ zB?XFl3KT6RP_(o_(J}%>%L)|r5^_aNjiuc)Ak|^%x~P3)eouef^ck&pV3QP_%*_idM8k(MmQ&D+?5@B2cudK+$Rf zMMDINRu?E5Do`{`plG;2(Ha6pYYG&N5GYzpplEG@qICp{))gpPPoQXhfuaoriZ&D| z+DM>iVJW>plGH*(JX}NRK-1<+><+%i1}OmE`-*29g429DY{yq=o*2d zYXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pKQh zdj*Q_6DYc0py&Z1S9D%u>G%vt^{I4Sbbct>C4EMFu(6VSB}I=mmea5JYfN(Z>Qsp9mCvD&&eD zZY;f;0jZ{6$JY2rC^{zH)Bmiol6)maUp1D~uZV0>^tJOt(KmJ|`qmCb-`Sz)dpi{U zV27d~?NIcS9g2RoL(wlbMZXFZ{U%WKyFk$&0!4oc6#XSo^tV9KKLSPn3Kab(P*f<# z-FAwK0!0l1MJ0ivMuDQTKv5fkqKZIKTY;i>0!3AUq9!3%^hIN7f%P&)J=6C(ei@2B zO`p-)mn+FvQdBRO)2|q9QPj!#p{TPRin`dLXf8Vx&25LGdF)Ws)ec4T+M#GZI~2`t zQ`AkMXaRwu1qF&05-3_&ps2e*(INsxiwYDiCQ#HvplES{q9p{1mJ}%JDNwYOK+)0y zMau{jEh|veOQ0zGMQ!;vlTeiXM!7st)K|zAbu5>5%z#uI)AwE1%K1J0chff;HJ2;N zS5mZGxtxAQZHuCT&JRV)+o5QX9f}6qp=bp=6s>57qLu7Ww6YzFRG6s;*xG(wkP(2o#+uP;{0+(b)n;=Li&?D^PTvkSp4!TpEx8scxC>mhBsgo=De4 z=a(zVS5kCwxtxB*dW)hHJXilpTtmwnNb~b|`w*4n@z|q3C%#6un@Fq8IH@^pZ`{%K}BO2o$|4Q1qHW(dz<5 zZwM5`ko|BT!TkC~7NE)J~wNDp1rUP}E+asDnUJMr$EtC0!2#;6fGlAw5&i; zFM*=o0!4iUiuwu^H47B=6DaC0C>mmiqSbARh6)r76DS%kP_%|X z(V7B9BLs@p5-3_*plBU|qICs|))OdNU!Z6MfuaosiZ&7`+E}1y6M>>l1&THkDB4`0 zXbXX&Erndsz&525Ga%KO>66&m>rqH%U88gElHL7-@&K+#SDMLP==O%f=YEKoE>plGT<(KLag zT?C4z3lz-|D4HoyG)tgpSAnA41d4VSDB44yXitHny#$K(7AV?B$Q5nVru2FSq`-*29g429L($cCD7wZDMc3M)=sG(TU2lh?8*GYh6ezk$py+0S zqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^96exN~py*+N zqDKUZ9u+8hOvn{o(xx;f15!ORUHx1disnk=@ivv@D=B)qP5F?WLeVqM4@J+~q3Ag~ z6g_W;q8IE?^r9V#Ua~{c%XTPw#STTU+7!JeQ1rS$(HjCqZweH>B~bLXK+!t_Mehm} zy(dugzCh6j0!1GR6n!L6^szwECjv#E3KV@NQ1rP#(H8H1U)F4n)5-4gEC@KpSwGk+)2o$vy zC~7BAR23*{5-4gfP}D)7sG~qpO`xbQP}E7t6@AyH^nC`Tx^uev`92h#pKe`uu2hn* zq-dT>xzp58)YbW+XkI%M&1Z+A`R!2D%??Ei*r8}aI}|NshoXh;P}JR~Xc2*;MFol$ z6DaB-P_(!}(GmhhO9~YA6ewCsplE4yR<%RXYIZ0ZVuzyD?NBt-4n@Q4P&C}8Xbpj)H3f=B2o$X)P_(u{(K-S}>k1UD zCs4G$K+y&QMH>nfZ6r{%u|Ux#0!5n&6m2F@w7Edh76L_E3KVT6P_(r`(KbS^XmF*p zcLt>TZZ;cN2t}u+>!NKdmEGVz52UIG_ zS5kCHrTkI$i)~xJ8hfboL(yS&C_3B@MMv17=tw&h9c722qwP?1j2()OwL{TyHbut^ z6rCVYbfQ4fNdiSD3lyCqP;{z5(P;ujrwbIFAy9OtK+#zOMP~~Xog+|mu0YXw0!8Nw z6kQ-tbfG}eMFK?^3lv=<(XbmODmP+D=E6NQeJBJP;`~^ zL($cCD7wZDMc3M)=sG(TU2lh?8|+YYqaBKFvP03$Hbu7x6x}LNbellY?E*!22o&8Z zP;{3-(cJ|py(}uqPGQ#-VrEzSD@%Ufui>Xiaro1`cR`=6@9g4c!p=c316fJ6pqQz{AdI%IPE>N_DK+%!{MLh+I zmJ%phTA*kdfudyvih2nY^%f}VBT&>=pr~1(sGmSle}SR_0!7OS6b%$8T3(=NkU-I3 zAy?G3ZK?ZynWELwH_6W1HovF;V7hg^LfcC6l@zVgwmjs3P_(M^L(yt>C>mmiqSftC zG}I17!|YHr+zv%+*r8}mI~0wuDOyXQXl;R_bp(pm6)0LyplE%8q74L!HWVn@NT6tA zfucw(zpyr_45R0 z5^_bO+Lo@)fKxcif&J&4sKgXzLKKD+m@d> zBorOt{7`hH9g2>!L($Q8C_2UtMaSBq=r}tR9dC!C6YNlQqD|3B0!1ea6rCbabgDqn zX#z#33lyCpP;{n1(OCjTXA2aaBT#g%K+$;uMdu3?T_8|&p+M0^0!0@K6kQ@vbg4km zWdcQ)3%R00+m?RJfK;z7W^fJ*MIF+u>nqw;lCPxbnzrRGhliqToga#>vqRDKb||{R z4n;TGq39+%6y0oxqFd}xbgLbTZnG)6U7+X=fucJFitZ99x?7;=9)Y5J1&ZzyD7s&u z=mCME2L*~A5-56Dpy&~SqDKXa9up{fT%hO)fubh`ik=cEdRn0986j76Rol{_3`lkT zY&KpUirS~oXwSB-BwtCb~9)Y5+LaykSwxx$NAl04I)z7b?s3DDc+f|aUq-cS5E7bqGaP_&#t(LjNsm;qqG5I@8g7T8HSAEdrX7k#*r8}G zI~1*LhoW_Ciq;hKNL-{L(xP#6zyb(qMhwfG|3J{lkHG6#STSN?NBt$rf3&|qUi!f zGX#oe3KY!}DB4w^Xg7hP-35yF5GdMHplC0FqP+!*_7N!BSDNHI5rghmVOZbVeKl(S5kCTyYg+PgrcLJABv8# zL(#EzC_2s#MaSEr=ma|yooI)mlk8A*vK@*}u_-!Lpy)J#qSFP6&JZX%Q=sT9fugeo zip~)zI#;0RJb|L~1&S^ZD7sLf=puoliv@}<5h%J;py)DzqRRz}t`I1?QlRK6Ay;%n zyVBbkkm~SkHXa#@)=YQ%uWnaKzLKKr+m-)0Efn40{7`hG9g1$UL($E4D7wWCMYr0a z=r%hP-EN1XJM2(&r%lma0!4QV6x}0Gbgw|seF8=I3lu#dQ1qZc(L(}74+|7MB2e_G zK+$6YMUM*?6g?wQ^sGS9a{@)r3%R0e+m#kQJyX;-eHs6{P;`5` zkM=^lO7fKyz0$5c^vqE7s`Eq9Yj!Al-3~=>*rDi6I~2WThoZObQ1p%+ir%$D(R(&U z?+X-tAW-z7K+#76MIQ?keIiiwsX);plDu!qWJ`h z<`;5Bzqc!0n*pi5nr;{U5sG@G(XCoZzLKJatL5j;4Mp9ZABq;SL(!skC|b-8MLq0L zw74CLmas$7l6ENSX@{bvY>Ji^C|X9KXjy@xUIInE1&aCz6!jG-Y8EK!Cs5R1plERJog2mXt?u3(HeFrTGI|iBkWMLmK}=LwnNc6b|_lc4n^zPp=f=Z zq74L!HWVn@NT6tAfucU!zwXF@2tCf!InvRX;LlA>d);bfO)KPO?MM z$#y6@#STTM+M(z)I~1L6Q*?$v(U}58X9*OYEl_lhK+(AZMdt|=oi9*yfk4rP0!0@I z6kRM(bcsOGr2<8l2^3u}P;`Yr(Uk&4R|yndEl_lgK+&~AuIT7$>Cp^Gb;a~${9{5< z_jFJHx@sl)N{Vi(mOr~J6y5CnP;`qOif*+-(QS4py4?;%ci5rmPCFFcWrw1>?ND@& zP0_sqMfV95-7iq|fI!iM0!0rA6g@0Z^oT&wqXI>b2^2jpQ1paA(USs2PYDz~El~7~ zK+&@TMb8NoJugu7fN}%X#fue5&ioO*n`c9zedx4@K1d4tXDEdjD=x2eVUj&MN6)5^m zpy+oYSM+MNv~dQc`a^>AS}6K1J$Up-wUT@#MgLUGGp-Ir|2jVu{bz@wLQ~vx4@E^g z6gAkPsAPwtMmrRh?NHRl4n-B4qP7A>?F5Rd0!2*%MePNOItUbX6ey|*6x9WaItdhY z7AWc>P&Ai7(cA(>^9U4m6)2ilplCjUqWJ}ix(O65AW*cRkSqGDS~@)gQhh0X68k$8 zotizZaiOM4@|6@V+El*d+EBEZ^FvV&I}|N$hoU9yP_(2SihA0iXem1sEp3OQW$aM2 ztW8lbfui05MSTQ{`U(^^3l#MeDC#dzG(ezeIf0^q0!7OU6b%w68Z1z>fm7HP`w>Gw%DwTCuUlCPv_&8G5y z*N37J&JRUv*`a7{I~1*BhoW`uP_&*Miq^M7(FS%X+RzR~8`%_XEKszGK+&cGMVko} zZ7xu>g+S4k0!3R16m2a~w2eT~wgN@l2^4KFP&87YXa|9!Q36Ff3KWeNC>kSBG*+N! zoIufdAy+iKsnp|!OwnoSn?cqHMMq^%Yn;$jNxqVzNloS9H-)0f&JRUX>`*k-4n@=K zP_&C3il*D4Xoek%X4;`>mK}=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyAy>3hQ)#CRNOj%x z%^*96qEYEa(lJey`-*F9g0q|L(!>rC_2p!MW@@L=nOj) zooR=nvuuja7AQJLpy*tIqVoib&KD@UK%nSCfuf59iY^u?xO7be|oH?zbs=K%nSBfue^5 ziXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!?g7ASf~py*kFqUQvPo);*3L7?bGfuffL zie45ddPShaz$@6l~&4t zR9{TDuHOtrZzNKGH&v3aq^QuoyxrZQsMtR4$%mo_I~0}dP}FFLqOu)|+Ss9}Vuzx( zb|`9RhoY)YQIkMXdx4@30!1AKifRHyb%CNz0!5t#in<6C%_UGYw?NT60!3W~islt4 znopo;eu1KH0!0f56fG!Fw2(m2!U9FzgkPAw7Nji zP=TUh0!71xT+w3fOOIzjs!ycrq8{z@d-@Bt&&C?? zdUhyU-ws6^*r8}cI}~kXhoX(`P_&61iZ-<=+DxEmbAh5Q1d6s4DB4P(XlsF@Z3K$8 z6)4(HplEx6qLBhcI|vkw5-8eHplGx}(HMcEu>wWo1d7HB6ipB)nkZ1TlaMPK(Z1C2 zflN_3J?gktC`vzYrg7)?mEju0q1QlRK4fuf@YijEN|I#!_QI3ZUwxqWHV3`ljwbc1?IC|WO#x=f(xa)F{N1d6T{D7s3Z=xTwYYXpj}6)3t+py+ym zq8kK?ZWJiGNucOvAy;%_`_h>ikm~p8p8iRpXhzE&w)U0eD=E68efh4(LeZVh4@Gy` zq3CWq6y0NoqI>O7be|oH?zcnH19m8S&<;fp*%Uo2Q1pmE(W3%Ij|mh#E>QG@K+%%| zMNbJ7JuOi5j6l(|0!7aW6g@9c^nyUqivmS22^767Q1psG(W?SQuL%^rE>QG_kSn^a zed+xSNOj3{^>e%1McLCD-)vt=zLKJM+n0+^hNAbJABx_$L(vCzDEiP2MIYIr=wmw+ zePV~APwi0jnH`Egw<-EUpy*41qOSysz7{C@Mxf|hfuipOioO>p`az)RM}eZB1d4tZ zDEdX9=vRTF-vo+&7byBepy*G5qQ3-+{uU_uN1*6mAy@Qv`_d8_km|+d49+{D=-G5# z^k4f*@|6^oI+WLZIutc__@DRm%XTPgV~3)O9g5o8p{Si5imG-fYO+I7dpi_$uqo;& zP*f8rstXi#5-92{P}D`BXfA=Gxdn>m5h&^^P&BVV(R>0$^9vMp6DV3hplCsXqJ;#C z78WS#E>N_HK+&QCMT-f!qGE^Aqzp)PSo#8NLx=o6T9@o;jXgS4lCPwwXNU4J&xWF< zoFCUkOWUDn89Nj$YlosEKszHK+&oKMXL!E4G}0>U7%>FK+!OPqTvEXYX}srDNr;* z$Q3Qop>$&gq`Fjsvt%f0NT1%;>QG6(lA`rGlwW#26s_<4P_%&^iZ--E(MEPC+Sm?7 zo7kafQ#%xGW{0B9?NGFZP0^MDMOz6JZ7oo=jX=@10!7;i6m2h1G*X~w2Z5qd0!2Ft z6pa=r8Y56NR-kB{K+$-Cq6q>;69tNP5-8ePplFgn(PSZ4v`&Z8?-`J4w{%^!ZYW9* z6E#lhP)WX$qUjyV^Su;`W;j0-&9p<&EISnKYKNlT>`=739g6m_L(!ggDB8;oMSI&6 z?ITdMuRzg$0!8}^6dfQ?bf7@dK>|ew3ltq9P;{t3(P08bhYJ)PAy9OrK+#bGMMn!1 z9V1Y5tU%Fm0!7CQ6rCVYbfS3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUl zif$8fMW=Kq9h?EFKA9eMJT(;UkZxVy-l39wB}I34C|~kgD7we_q3B*a6y0ZsqWkSo z^ne|T9<)QzLv|>7*bYUH*rDiAo1(`AiXImzdP1P+Nr9rL1d5&(D0)Vq=vjfH=LCwL z7bto`py)+`qL&1UUKS{NMWER?0?0$4c^* z6t(GCZhkuyRh%D++S;M0ogIp*b|`AHLs5G>6m_seQAaxz)$CAIw<+o*P}EtVsEa_+ zTmnUN3lz;GP}EhRXkLM$`2>pQ7bxl`P_%$R(Sia+3kei0EKt;4plA_+qD2LY785Ay zAyBlqK+zIHuBfqNY4Z$7^~waN+%dnWpWV{V?yz;NBwtCdXHzs#plEr4qCo;hg9VCK5GYzvplBt5qLl@T zRuL##RiJ1!fubP-MXL)G4HYOFCQvk7plA(&qBRAIMhFzGB~Y}sK+!rvu4t)_rL!|2 z)$P+)K$Z?gZzodgcB~{{NzsNK%lEt=iZ*h7DB9Q#MVr{6Xj3~BZDxm}&FxUMg&m5v zv_sKWb|~7~rf3_1qHP6=wi77YUZ7~CK+z5YMWY0Yb`&TYEl@N@plGZ>(Kvyk@d8B? z1d1jK6zwEXw6j3bB!QyI0!32vt@Dm;tGFPWRC^2t|J+QoD4lBwtC< ztd8Z`=739g6m_L(!ggDB8;oMSI(!XdgQi?Q4gk{cMW%7brSFpy)t> zqJspA4i+dnM4;$Ufuh3%iVhbjIzpi6NP(iG1d5IpC^|-<=vaZG;{=M17brSGpy)(_ zqLT!QP8KLSMaUJ+=veBR0jc&(aAt<0kJGK|Q#)3YucYYAj^(vJ2}Nf)KNOv9hoW=r zP;{;xiq5k`(fM{Ly1))a7uuodB0CgaY*TcJK+&ZFMVAQ_T`o{`g+S4j0!3E|6kRP) zbd5mKwE{)g2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xNMYjnQ-7Zjchd|MtLaylaj-@FX zkZMDE)bWf^v{|~Re^`?Te9f}^ZL(#)_D0;*WMUUE{ z=rKDKJ#L4hCv1wI6exO1py+9VqGtq(o)sv1PN3*{fua`#ie3~bdP$(@Wr3ns1d3i2 zD0)qx=yidjHw22_6exO2py+LZqIU#}-W4c%PskPB)3J1O2Bg|O-4wbv6n&b$efIs1 zmE`?Tj9g4oPL($iEDEh_@Mc>*KeJ4=# zy+F|q0!2Rx6#XPn^s_+GF9Jos3Kab&Q1rV%(H{aue+m@+B~bLYK+!(}MgIyE{U=aV zsKwoOii!e74FW|afucqsSM*`W(w`ZS>H`VRN1rhm6ekf|P zLs5G>6m_seQAaxz)$CAIw?k1UI}~-cLs1u-qPYZ$<`yWLN1&*yK+(JcMe_+1%`Z^Y zO`vE2fuaQkiWU+mT3Dc{yFk$*0!51o6fGuD)I*?Xae<;G1d5gvDC#Ltw3Lu5s?vl6MLYn9|HDe7G-kNP$g^>KbE>T8FhW;+!1vqMpTI}{DDL(y_} zC>m&oqUG&SG{~lCut3oY0!1qd6s;ssw6Z|aDgs5T3KXp-P&7oKXmx?2p#nw21d4_W z6s;jpw5CAO2!W!t1d7%cC|XCLXkCG#^#qF67ji|*)=GzFK&scJ`)IvF(fciT*lLyJ zD=FHfR=(`}P_(J@L(yh-DB9c(MO)aRXiGa3ZDog|t?f{>jU9@%wL{T%HbvVD6pa)p z+CiXblt9sr0!5<*ipB^OjTI;wCr~tAplE_X(L{lwodk+@7ATq|P&8SfXo^75RDq&t z0!6zB6ipW>njz$hHma4L&VW=Wq{pr|4n=*^b|ew3ltq9P;{t3(P08bhYJ)PAy9Or zK+#bGMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD3lyCqP;{z5(P;ujrwh5FU2CPz zKV^#cPG3jcEfk$m&c+$FO7fKyol`6K|0NWi>-ibeT=jAL9bP_#q(jCOCW zl6)ma57x?i{1%EHa(*a!*bYUH*rDiAI}|-;hoZ;rQ1pZyik`GX(NlIPdfKMw8G)i_ z1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+X2BErp{Sf5g8ZmfNxqVz&uZoS{s={%J3kbC zVTYnG?NIcU9g4oTL(w;ODEih8Mc>(>=zBX9{a{n{qd?J50!2Ry6#XJl^s7M8ZvsWX z3l#k!Q1quj(O&{Ze+v}-BT)3OK+%5!MTL6YZKtRxP}Cq$R1zp^6eubS6txj3stCEF zPim!)Ga%LF(`6fI|mqJefOTHX#tgX~Z=*bYT2*r8}eo1&Ej zidGgVT1B8}Re_?_1d4_T6s;~$G*qBym_X5Rfuc18iq;e;8X-`$mO#z zw4OlG`T|882o!B7P_&VdE9z4(P0N5(KTo%=`-Y-p(-qUk^-A)U6m4EFpHN6Ipl_jZ z3+IQTE$vXWl^u$wWM2^1YK zP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoi0#xhCtDo0!3#DxuQMlrN1*E)y>mm*L#Md zgVJ@;+4V~Dl@y&{FE5z=IEa?(q6?fKiY~N6(M5JBy4Vgym)N1`Qacn~W{0B7?ND@u z9g42BDY{Ca=xTwYYXpj}6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$Dsx=oYdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1| zfufHEiarr?MGw_Whi5>lUDI{Z!=dP+bnE)ldL{WvioUFuuV@#FzH)vj`q~af-`Jt( zTRRkeXNRKi?NIcC9g2RmL(xxmDEir^=of*aUj>SO6Day!py&^QqCW+S{t_tqTcGG4 zfuer}ivANQDs+mw?GzOSiW&rpN&-cV0!3wkqBa6W6@j9*0!8fvimF1c=<|B%*$hZ^ zYBn3c2t`BEJ^iLmmE`>I%4nS~9g zdF@a%pH0#H0!7^fiWU$kT2P>9A%UWW1&X>06fGi9w5UMQVgf}y1d0|HC|W|GXi0&h zo&rTn2^1|YP_&Fd(Xs+Xy#$JS3l#Mcaz!0FmF8-nDS9bA>e#VUeoz1ObY0Z9QziLI ziUxElFV`^?E$94DG|&!3%iE!7kR6H!+o5O$I~1*GhoY72P_(igidL~HT2-KEHG!fb z0!6C}6b%(98YWOQT%c$Tfuc19ibe<&ttC*jwm{K30!8Zz6s;#vw7x*m1_DJJ3KVT5 zP_(f?(Ix^#n+mz2ew|8NXF#gwr<+3kLs325y56i)CHYE z+M#GWI}~kihoX^oDB8geMWgIcw4)u0M%xsP5hxlfP&7`UXuLqt1c9Q70!2Fs6zwcf zG)bUnvOv)kfugAbMbiX|b`dC=E>JW>plGH*(JXOJYYXvaMP7o+MQK0A~fufTIicS$I zI#r< zDY~drxiWVsy4d-l=n^{=U22D-%j{5exgCnGutU+6b||{a4n=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1w zU!dp#fuaWmiXIYjMHh4`Et>(UK9U}Fyf73!madB)?o>&>lA^~umDlSUik@(OD0`=6TP0@k^ zMGFZOEi6#fU7%LF0HxIobo0!2#-6!jD+T1ud3X@R0;1d5gwDC#9p z)LWpak3dmhfud%CqJBcIsNT8sZw91#aC(TSQ|J7i{vjEj#{Qiv$yZXeeCP7Q3x%RV z&JRU{?NGFW9g0@8L(xihC|cPLMXT7MXjMBDt!9U!AvQ&;3lt3%C>kbEG+dx)4S}LH z1&T%p6s;vtw6;LeIs!%O3KXp;P_({4(FOuV8wwO{Bv7=mK+z@wMVkr~Z6;8(xj@kt zLau1J&ZS`)km@oC&cIOgXZiyFmYplfS5mZX=knO>Hxjpe9c?@3hobH6P&CpGMLXD` zXp|j_cCMWAS^K+!aT zqFn@vrVA9!5Ga}{P&7-RXjg%v-2{qu7bx08plDBlqP+x)_7-wQTX!xUnE|P8nc!>_ zih88~P9f}UOL(vg-C_2&( zMMv2b9W79Fj6l(`0!7CO6df;6bb>(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaK+%~3 zMP~^Voh?vwjzH150!8Nu6rC?nbb*j7+OKoz`3y+)(`+{GABw(9$QzK6bf_IPN@|N^VZ(#R46P^ zTV$?6p?huoJcUA!+BNeQ3O#E-&0i=iTN}J!q0qOs-@=8$fZ8LA6bgfCO+5;Qm1-L; zQ7EidJFRD-Fs$~@(uKl^+G4#5g>`Ea`xFWr)~;(V6gI8>(!WsHvbN&DLSft50fP#K z9cquQP$-P4by&Gjm{8kf)k0xX?TjIX!nE3ZLkoqOwZ+#c6n3xeJfcw8yLQ9cg~I-| z-_|V@4z8`dL7{MX?Vybcg`;avY*Hv3U#o3iD4bl|Y|BF7^x9cl7Yb+BKG?QUIKQ^! z$U@=b+T>A%!sWG_Mi&ZK*Zvq=C|qA#bwZ(VbM26w3WeKiPfaQm?yhy3S}5FK+hUhO z;o;gjGYW;rYah)j6rQdvmHkSL=WA2=G!}hn|^T1jYIhXJ?l|vHsk-*@aN7&wW95DHQA5T$Ei5#rg%8WS2v+o_?Es zk77OjI`W>ydis6R%NFbD7XtS!*3)lv9Z;;NU&%SBSWmxGaiwBC{ZhQuiuLqc&4v~0 z>DN+?DAv>O6>>S zPduSmPd{IFQn8+XK*;5#?Om*=ACk3yv7Ua)(ZR*~J@03i zP_dqV&dAZldip^T#~17Azw|%3SWo|{_UXlX`fqK|F4oh3EO~yhp8jjMi;MO2pDSHn ztf&9p*?WQJ$>8C4kmXGXjor;Th?9x=~*sbGcT{~r(3WbIqg{G!e zvQ#LP<|&jquF$k%)8MAHx@7;dcuL#!o+zZ!rc1G@DSw7yHY*(prM8~Gsi{L#`=&wJ zzoc!~|M6VyvgexPrB-8>^H;m| z*IWKlE)+V&za(Bs=VEcKF6qU0StNVTKG`$OHDHc6YSsBxny*lpyLWNb`Mjk|&ey5f zxy@?xp0;}SlzGZ?Jaa?W+g8usZC&Sl0SjcWd)_%iJX5-GTmEF%s2T4K(;*3JEc{g5 z@Vu6%q?NA83rl4GYbf-cT^DHC=_!Qe=ceLMdRhLQkbx={#$+$6q4-zF4uxX&Cwp2_ z(z|z`>7)9Ln=!4=jOnBMOdmO8^w^Qprca$YcJ$1#WBQDqzQ?qgQ&Si{cFe5lV`t3q zwDkPha}Vw_ZTiH?6K77`b!?%}gsGFq_8B#4?CyPfPntS<)TBN$CXAXsw$JpjQ^w91 zHKWhiej{hhoHb_R)IKw(PMtJ*!l;Q;X7m|9di2Oq(~1WAmWCBS!9+|8?Mi*?(Pb=*|UwAHF@$L`AdrD9pDuYiLm_aHz0e5&VI?WU&#QkV_54u zBYPLbGiGmc{%*`(O8%EQ-h}0yn!WQ{o|wI3No{2MP>K(}`~~%kv-`Kc zRYPZ=-#pYS&i)zkGLwfnu5SNdUC9g^yW_0!`J0qo8rkd0uD9m6IO6RX(E6rj7k&Qh zv)@aM^=kQv&fymS-B$`o;~* zF6ki~ui4zvXPfYfn+MH)G0m;)FrlQm)nWE8h*wL)?8`m7B4~Lf&8?`KGgW!(>xr$- zn%8i#w1RR;W&eQuJby_SNz0W`>&2Q~FU6bEoV_jn+T8lynB&4-K2CQ5*(i|wO;Vet(ScB92b3d>Ex%hUdS$k=GEiho-Tp(ng-8)d$ad%yt%DcPyOR1 zE!X#Ty~BZoC(a|h1siZ`Ahbm@U+=)QueyC zmadUD%|7wR^E)xSJX%V+kXt^Z^&4un|)bk7eW3ST5V+4 z7uj>QyzrJMWtVN7m0i)t-)8?qGI#m;*|lRKy8$^pf3Gy>hxjbls-d}+!)$@A3bIe2 z*~_0XVe0gmvp;8L*t`|_g+BZ8p8eT1`!H#FmUNl42+H0Y`CsNB(0Y+Kw_fJWtrxmW zq&a(ITTaeC{k9yv$D1?1`AePS0&TtgvR5AOo965WL;j4}$7lRy_Pek-zjXg!-pY?V z39YvsTRs3=Ut@E;IT@MOOE3G|n(J@Yedyr9-O~;E-p$?9P5Hiq`VHvbbNbjxV@J&x zyHxjHlSfaRweslf;uyPougU%UXJO`qS(A6nj^idx9W}F8c0XX{>@pvdLiU{FrtP|1 zuNl*NjcFd3l~L12Pgps-W3cO>UXy!I&hA<)GiJuLWyVeG-fMjKUK{l5-YdH;yYlGl z4d^v)^4J+OMvWiaYtq;$<7ZA-xo?*8n=ZW)scfZx+{}qnr}UbU-6qeDGqN^j)XY({ zcm96PKK|2_%Z$i$# zwK&IzYU{^D>#aK%c&$m7}Bx*!KFhQ4lPc8^pS_NM}3A2 z&f=(a|GQA^ll`?ksMmVE*Bi3d`h_-~D(kf?RoixMoU1r@v1@7G;(W#Vi`|L~6c=h( zwAed6yzsyN%$XVsKm0f6lS}Ci=p27a>CWdIe@f~8=Nx}Z*?rGWbL{j$NcI?ZVa)8- z`oKs^r9$?=*&KgLh3tW=IsTLi+2iAL{3#W(M{VZ#Qz~SSna}a3RH)6d(#!v!Z%wI? zJ)ktlpHiXo94kHl+=c9cqLzPkdcSwh-v0E^pFj2Vm;Zeqy~oT#k1_x2&O?0oqG`rp>syZ5WArV@)#JEf z95;(&_6S1D(|3yFE^*v1jt9r__&8n^#~ZSXHNBpD;`mZ_F{S-p9Dm9F0cjVrM>Es0 zYxZwR$Hn3}IJ;QV9v;VSvVTL`X0>FMvpah@LeUM!B=W{>2h zr%#OIh1ms=_H}XmeCd4u635=X^1WglXJ!{vdj13AcxQ9IAB$sQK)yS~agFQ(P0znc z9FHE9?=#}~;tKhGFOKtO7kqmD#pAgBs`=hIju#Kf_YHCUa%jGPi(}t4^1X5#cO8-M zgW`Di+WCGWjt%SOyB5b08{~VlI3BxEzR!x|%bVo;gE-E=dA^s7;|^QqdvY8v-8$bl z#qsNH^ZiF0`;E-^s&U+XRK5?1mt{ekP7>_RDvd zIIep@zPF0wi3jETyg0soNWMRb<3fk$dzmrru775}w~6D)XXpEZIKG*E6)jyppT)8J1^Mn3$8rB3 zV|N`M<-LG^I$<&l41oYO>eQVAbyw={-a?JKK;7Nl-QC^Y-QC^YsPFsDJoj$TZ~xfM zb@jY?KFK?z{OeVRgwa4Um^(C!+M~**U*4qE(IPaCMJtD__uWs$5a(wvO)_x(! z<_)bqQI4zJ)Y=>7c!eNm2Y-`3h+9hc5=|3_N;m>eH{thHatvGd8+o;b(Vo^I`pb3Fao*1jaicb{+VuX3FBrPdyn z||5|I`ljE;%w07;y)^WkNTgPQ{Jn-GtJ}$?{-*4?#a_sj}YfqZv8lSZG z$Q;l7thF!8@%=Aa`iKeBbsG@m*b4p*UrnHE644t z$2iO0E61Cw2RqAtAjdzdM?K4KR8Ko9$3?4$Kg)5&91pD?2QB-g9G|Wp5H0(S90yj9 zjFvrRj_Xtpk(RxAj^|d7m6m-~jvrSKnwI@Tjx$$}o|ZjNjyn!+?R|2*wR$|Yy#1jZ zC#xPZEqnePm&$R)a;#SmO=oXfj?L=xdXC$s?~&u7Ii8TWpOWL5>6hhrbB+(>_-u}E z<@kAyzvS3shStYd-5lxuczWg7mE(9h&XD6QIrc2a>Ye*%SBLKNUCx+td#C#Mt8R9* z^{6gvkoOxhW{>U0jvUoCWX#x|TgTB}tL_AkZ5vYVb+!!|HD*lPkm`Q&kP?Ud@7IsJ z`)1|qw$+!;x7eXNrTg`fqekt#`L3plM8W!v(2S}w8r zz}kjvT0Qu)dG+=E|NN<2>^yS2>YWx_ZN(uY$Bx~3t5Lg*tuFTe_e*uts``IJ>$Yn- zsk-U%KQGmPy6%^$s{bwTS8L7x*ZY;Xm6!5&Q~uumzus?X^*;aSpSxq#yp+GY@-l1n zPj&ONZPDtV^0MOs?cJ9@VfA`>pYl)n^OmXp@iA1dwq0EP)4%fM#cNAe;lG!+dv$rs zRH0m6apdyWs9twY^=jMA)n)DYpWxN%rpW)i-?THew=Gak$cy(IRqg-&x%V&G-d6q_ zls~t0f9@{T>&~fOZQHoIyusy_ym;GA)&B40eP3N(@n0^l+TNEsx+(BKmv>xsd8hcx{?FS^{XZ_Re|34~@2Pxz<^Rtv z@6zh^@-dYE7UgBy+1lG?>TJDU{R)fi>d^i2cy)R68`aUDRgV6@Qr_G#e|z;! zLDhYz>h*H(vs_;J?_T~J|K~qf+me;PV%&?%8&HM+zTb@1$M=?Zs*c|8zjsrI57}Y% z>M@GB=N&qH-r;i%uD%p8bl89Xcka3896Wg5Ip>*c_~7!gNprsuD=gLeUWC>Kw^#Q_ zU2Z8eF5SKAt?Pst+a|8AIfvf7^3QD}7yoh8T(hk(+j2ve@A%>P&IiYJtlIh2{?+mM z{tu3OcxcC0`?tS1u47o+EPuY)XLSEz4~}aaw(7Xf1xJo(z1C~N*0H1e_{9s8F574H zneBhQyzVf0*t+uTS6o`V2$M zThnKBLd7E_dkN)g`a~)W{u|Zo9Ah-?aaPi{5wG_lw`t zXj^nd=l*S-)&I9!E;`!3uaI`$ReiFU@4tVW)mc5-dv09r_qO-irux*_qeuOdMmaRL zsbX!y>OWME6$e%KqpHW9>;G17sqInTYvqYI=}wJLs=xOhz3LZN7u=&)V{r91+tE=k zUkU5c(RiVHmsN%ewvL%HC$Hul)lbdOoUEF2wsp*sIcYWLYU`LabCPP#UH#y_ z%!#WxPg}>3%t6(hx2Gc)9>47B1Dhjzyt1p0 zY|iX~Wmg~CT-gK4u0FQ8v-_7_eQ@(+ca>dzbn|BSE4%ve=F9F|cJ=YipWRvQ;nl~t zKz5(9tB-HN>}J{3$G1>+@3O0pZ{h4-Wmg~HBH4|ytB-Hd?4D&;AKzlx^|GsvZ}IGo zva648iR@b0)yKDFc8_Y$QGI+PvfIn9KE9>0D+awfI;O2XQT_e*KBV}WuKRfvy@yva zI+ku+R=q@5Xte6=gD`iH=%9#GCG@(t+EN(I-8JfvRguyt$kJf{r5hlx-HYOTuaCb)iqSdwv8gE z2-&e-zA3p|$WA#mLUzuKkTIDNGBz_pcFBy8T{9zOx6BCHJu^b~$c&IZGYQ!%n~=S; z3E3x`kbScW*)N-r{j&)`IH zIW?z7$Z44oa(ZTjoRJwJXJ$soS(y=Xc4mZ}lNllBW=6<)nS`95O~?h=gj|?S$VJ(N zT%1kFCE0{rnoY=M*@Rr4O~@75gj|_T$W_^dT%AqGHQ9t*n@z}d*@Rr5O~?(|gxr`- z$W7UV+?-9wE!iz0C)H-J{{DM!TdqS+ZV7q4ynbt=$SFeZtd}PZkBDMH?>mnXV(3wb}MM#u-55%OVXgnX14As=T( z$S0W*@@Zy-e3ls@pJztM7ny{7nN7%7*@S$ZO~^OdgnXM#$amRt*LzcfIXA z>#k|%S$BQxJnOF0&a>|N+IiMpKijkJx&+U<>o0iL-2lO}?gk2;bvK^iS$E?Lo^>~Y z;8}MQ3Z8X0k>FW(g9OjIn^^FyyGaDkx|>w+th>ns&$^pj@T|Kj1kbvgQt+(1!GdSq zO(l5N-PD3--AyBS*4?y11*C6B^*!FTJ1Zc~OUuoZT6;^;tL1jfbnT78t0|pg_?=0!0f86fGi9w5UMQVgf~r3luFOP_(2#(FlQ}r38wW7ARUq zplDg4rD%rs?(hF-9$K!7W{jflUr)JQd!zU&idJf`m#1NND_Yt4QM8I3MXTCTw3;17 ztJ_huh8;y~+EKKY9Yt%~QM8Ut(YgXf>j@OCFHp3BK+%Q*MH>keZ7fiph3TPYgTUN2AM?N&6_`BAis9Ywp^QM8*KMZ4Qkw1*u7*UOI)=vH*E^P}iKJBseN zqv!!UiXOD1=pj3b9=4#D0)_)=sAI+ z=LL#h5GZ<4py(xmqL&4VUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgT8i#!uMMgm z{crwI?zrC_MNgMo*YCDBim#&R!}falF%;d3K5~8(eQZb3Cw3HlYDdv$b`*VXN6{B{ z6n$w&(N}g9eQi_pjX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqUzX=qL6Day! zpy&^QqCW+S{t_tqTcGG4fuer}irRYo-}mx6yC08g7bxl>v=qJHUfZYw(%i6mWV7Rg zD0;YD7u9++im#%m(W72|j7hhmUe1rA-gXoSsq$mmNj@?I;>x zQ#4SZXgq?oSsrf434qIm_1<`XEI zU!Z6KfuaQkiWU+mT3DcH5rLvb1&S6EC|X>gXbFL$B?XE`2ox%L)`N zCs4G!K+y_9OVP|dYF}1BniE#vKh!Zx6!j`!JX*0wqxdR{R_#$QKSrrr(Q3|*qSfsv zTEmW_HSH)`%Z{S8?I>Euj-qw#C|b{sqV;WxHV`PiZ&N0+CrdcOM#-%0!3R16m2a~w2eT~wgN@l2^4KFP_%KlqfvYnMfdlpmmdSzeO>f` z^P}iNJBl8%qv&BfiXO3}=utb09U4f$a1d84l zT8i%NQR^{FrD*T+Rmc0HXr6NG`hy;g;;Sh7q({B{7|Cu$pE^H^KC`3fb32N@u%qZp zJBq%tqv&fpioUU<=vzCAzOyO%UZCg)fubJ;ihdF(`dOgp7lEQ*1&V$XC>keF^t(XO z9|A>x3Kab%Q1rJz(LVx3{|XdU-+_Eq_19QEqF((4mTx<47bxl>P*f8r>JTWZ3oS(- z^{6dV0cmbhu8Tg7qVLP-S!)zuMNzX>FF%H~TTvh9M^UF8MSblk>Ssq$mmNj@?I;>x zN6|n#ipH~}XndQZ2?UBJ6eyZVplFal(Zm8plL!<|Do`|;K+)s^MN6_Dn7<*SapYpr|wx0map zS!#{qt0j-s{gC|bvkqIK;kTF;K6_3bFyz>cB~?I_yFrf6e$tw7Os0!7;k6zw2Tw4*@LP69krY z6s=aPO)_Vt=$-0&7CTmtqRq<}vUjO9im#$*k6OL_80~IFdpbXg_OhdBZ##b zV+D$i6DT@fpy&jFq7wy*P7)|OS)k|?fud6dicS+KI$faX456iHw_0tJ3P`j380wDQ zqiDAB8STtkqxdR{&aKtUk74gtbe{90=zKehF0iBMLOY5svZLr?JBlu`qv%pQiY~LG z=yIE)D+G$J6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCc z=yrjkI|PdE6ezk&py+OaqI(32?iE^!&aTxit$;KK6-DPn(cm)ft2K(RqUfPoz5E#e zZbc6}KZ+i)qv%mPiXOA0=y5xWp0K0nNjr+3vZLr}JBpsMDSB3*=sAI+=LL#h5GZ<4 zpy(xmqL&4VUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_XUbR5GeXk zpy(r^rRafL?du9ibKmk+#|NWm(sEt&ajj8&6-A%d>gCr!bSwJ8`BC(x9YtT+QS`MP zMc>#_^sOC5-`P?0y&XkA*irPOP0>#RML!D^{UT8Gt3c6j0!8BlihdU;`a_`TPl2Mp z1d9F^DEddB=wE@NwvOCwr>I?^sE0sNO`xblpr|fT)Kj3SAyCvyXes)%RvTUcX$~u2 zuKp~F_A0lodv`R7ucD}LN4@+Sk#0r(oF7G9b`cB` z?I@barf85r(Zm8plL!<|Do`|;K+)s^MNk`QG69e z!#nC{EEYv`I6sQ!w4-P)JBsGEqi7yGisrSWXg)iN=C`A00XvEov?*FhplD%%qD2IX z78NL3OrU6Sfubb@ik1{88X-`$lt9ta0!7OR6fG-Iw46ZE@&ZLG2o$X-P_&Xj(aHiv zs|XaWDp0hV&{8zCqjqlvq(2?9kY3KX3r zP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49ow$M_vXGd+h3P|(sa<^YdR3t4 zHG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiarr2`c!Bs zdbp$ZY6YY@efcEzNE97Y?&*Kl(I~!(qOUsY<<~fNEBe~`QS^-+Mc>*{^qn0=-`i32 zgB?Xb+EMhA9YsIeQS^&V(XRqUzX=qL6Day!py&^QqCW+S{t_tqTcGG4fuer}irVVA z+fGrtKv55YqMATahd@zXps1%nQA41pmq1Z(fug2BQ6HhD=!=fpWGhyR4k^zh`Z9_> zEuYak>y6^8DC%FYmtO?q%N-BoYh(|@IWv(d16 zqxdR{=Bn4ruaWImG`I7kXdXL?=Cz|}K0Au$x1(qQJBk*xqi7*JiWat`Xc3#DMFol$ z6DV3-plAt!q9p~2MhFxwB~Y}qK+!S+Mav2lEhkX4yg<S3sJRl&haPqv*6U)~Yv(ucBzZdcFJ_;%-IjJ3opx zu%l>0JBl{4qiAD0iZ-#MXrvuQqwFZ!)Q+OfY>GA)DB41xXiI^j(E>$V2^4KDP_&Ie z(Y69b+X)nHFHp3DK+%o@MLP);?JQ6VRjT9Zb#7(HbqAY6dff{bhJRxF#<)$3KShDP;|UN(Fp=YCkhmuBv5p+K+!1z zMW+fBohDFpxG&X1x??I^m;j-t!$D7wOqqATqvy2_5CtL-Sd#*U(EZHlfF zD7s#t=mvqJ8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&Zzy zD7s&u=mCME2L*~A5-56DXeqj|UfZ(*(%iJ%6uKyi9;@Eg@kqT5Rqv&Znik`8f=vh08p0lIqc{_?;u%qZjJBnViDSBC;=oNvYR|Se*6DWFJpy&;O zqBjMK-V!K!TcGG2fueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzpy&&s zrRcGG?fwc#v-+hHZ5@wC(Nl%gm-R;RRTO<&uYa&X6n*FXDEi)xq95!i`q7S}pX@05 z*^Z)L>?r!xj-ub}C>m!|^t(XO9|A>x3Kab%Q1rJz(LVx3{|Xef_00VmirNK=dI%KN z1d2KYis}MIJq3yy0!6(9ih2taH3f?L2o!Y+6!jG->L;`meO<5h+^|wq9(V2dCW_uF zcl*0~Hj1yJXuO{F88(ih@tq$<6WCESp&dmN*-knIG)$mqxIobyLQBzrp0yP!AkFj2t?Pk3Tle%k%iaDtdp3%%qG;Zp_3cJR z(R|L2qWSG8TELE?1??zW$d00g?I>Erj-o~FC|b;pqQz~BmJldfQlMyrK+#eHMN115 zEhA90tU%Fn0!7OU6s;gow4y-KN&-bI3lyy)P_(K*(P{!ks|ysZAyBlYK+#$PMQaNb zts}G)&E2zhVg;nRP5C4?PZV8Q9u8TzXQTKkiZ<+7ziHDb+Q|7)w6PsUo7hn_(vG50 zb`))DN6}_>6m4!t(H3?TZD~_9TA*kvfugMiinb9b+E$=wJAtC@1&VeMDB4k=XeWW9 zodt@<2o#MKDB4A!Xjg%v-2{qu7bx08plDBlqP+x)_7*7GM`$Tpzh~|B3P|&u^8G~{ zMA2U5GupmA8^u>qbYRc=@0&-_LC%k&gY76f#Ezmv?I=3Tj-tcuC_2K9q9g4nI?9fs zqiu?g5hyxVpy)V(qT>aMP7o+MQK0A~fufTIicS$II#r z0!6n86x}XRbcaCEodQL72^8HeP;`$#(Y*pi_X!l;FHrP=K+%H&MGpxSJuFc4h(OV! z0!5DrEk&2~tZh~SY5rEOelCrooyvH;XQTKkik|LSKV<7DddB%t^sF64&)HG*yd6a^ z*irPN9YrtMQS`DMMX%UV^r}tKYXU{D3lzN}Q1qri(OUvVZwnN?BT)3NK+$^wMehp~ zeIQWup+M0`0!1GS6n!F4^r=A6X97i^3lx1JQ1qoh(N_XRUkfcoPxh=`SpjK2P(GtQ z6-5h`yZztvY!qKb(GNZAPi-4TKRQ2(ezK$JXFH01v7_i$JBog@qiCERMZeoo^oJcq zf7%rNB~bLYK+!(}MgIyEwKa0LouYPuq8m^2G?hTn)B;7*2oy~#P&A!D z(ewgEGYAyTC{Q$$K+((sMY9ML%_>kdn?TVJfuh+3iiQdl4HGCDE>JXwK+&86MRN%h z%`LPPjo+xvT>)uMSMKRg&}iM$|D#+n&C_TUUq#UZjr!UW9p>?m5&j-nAZMN0`3EiF*Aj6l({0!7OS6fG}Mw1PmN_FK+&24MQaHZtu0WrjzH160!8Zy6s<3`6wTMD?Og$BR=;4n z`c-^UbWFJ}+Mv-WzKWtv8ufF=MA1m+N6{!diZ->QXfr#CHn*c_3pe(I~!(qC*<> zkE&mu+x=+lq0Wz@!|W(J+>W9n>?k_Yj-sRNC_37XqGRkRI@XS&<7|qK7brSGpy)(_ zqLT!QP8KLSMWE+Yo+LdYIYnPMc0+jXqPq`#aB^uWurdR?oo7=^P}i$JBqHc zqv%>YimtPx=z2SfZm^^1MmvgbvZLr`o1$9;if$Dsx=oiry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT z6Dayzpy&&MqAvxCz7i<kPAG`m32P=TUh0!70Gisld~np2=?E`g%C1&ZboD4JKGXg;B(Xrf-V!TVK; z<|*GKJE&Ldp8ka8Gur&U8pT&pv~aKbVh2RgBF>MZMeQhB%#NbP?I>Epj-n;)C>mi$ z(NcC4Ep129GB!oa3KT6TP_(>2(Fy`ZD+&~?Bv7=nK+!4!MXL%FttL>kxI z6s;vtw6;LeIs!%O3KXp;P_({4(FOuV8wwO{B(xMQ*sHch1*ExPfwNE)?NY9bHty9Z zzKWtvd({s+D2g_7eiUtPN6{8`6m4lo(P%r0wz8vWYdeazv7=~PJBqfmDcWA3Xa|9! z9R-SZ5-8ePplFOh(O7|^T?C4D6)4(GplEl2qCEtP_7o`EOQ2|Pfuel`iuM&K+E1Wp ze}SR{1d0w6C^|@JDH_?Uc69}$`BnL<kP(2o#+u zP;{0+(b)n;=Li&?D^PTvK+*XEMHdJZT_{j=kwDSK0!5by6kRG%beTZW+C4H-j1Rh>?pd?j-s3FD7x8> zqFd}Jy48-N+iZ$%7bvN(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1%l|a$g0!7~l6n!gD z^qoM__X0&f2o(J&v=lwxtF~_ir22eT!FeHyjw@ft{;5}^_$rEi>s3GR=qMWJ{3!a} zj-o&8DEiZmqQC4Y`rD48f9xpw*N&pL-nri%MeR04Jp_ts0!1AHMRkFqo&rS;fuddl zMZE=zngT_A1d2KZiuwu^^%E%S5-92~P&7cGXrMsRcmhS^3lvQtP&A=H(L_Q^(J#Gf z4_82%qsrCKuTk`S`4Z%y-i_j`D4MKy{gY#(XmaOA(G+$RO=(BbU^|MYvZH8fJBp^U zqi9+?il(!pXnLEX83c-E6eyZWplD`+qFDrrW)&!!O`vFqK+)_1MMDLOh6xl67bu!T zplD8kqPYZ$<`yWLN1$k4fui{Yislz6T0o#^L7}B+lHRrEah0O6<>wbo+Pig6|MD^x z>fI>5ilW7O*Jn8)iWYZ%6fI##(UNu)jj*F=DLaamwxehnJBpUIqi8uhik7!2T0x*_ zMS-G~1d3J`C|X6JXjOrt)dY%G7bsdoplD5jqO}By))pvQN1$k3fui*Uiq;n>+CZRa zLxG}=1d28mDB47zXr$0mv`FvTDix6Ca^<>c(J1<>`UKZ8s&}LKDvGw~UEk@XDB9Bb zQ8e0)qOI&G+S-nyZR{x8){dg>>?qpaj-nmxDB97cXeWW9odt@<2o#MKDB4A!Xjg%v z-2{qu7bx08plDBlqP+x)_7*7GN1$k5fuj8ciuM;MIzXW4K!Kuz1d0w8C^|%-=un}h zXtUn6Q!60N8_QQ6H;LuaK+%~3MP~^Voh?vwjzH150!8Nu6rC?n zbb&z8g#twv2^3u{P;`kv(WL@KmkAVIE>LuZK+%-~MOO(eMMw0my*v7_i#JBn_zqv&=!itezZ=uVrW zy9A2v7AU$$py*zKqWc7j?iVO}K%nSBfue^5iXIjydPJb;QGuez1d1LPD0)Jm=t+U1 zrv!?g7ASf~py*kFqUQvPo)=n*uI*i$`t(ZCG35)5*G18FQS?gh`VwbG z(W}mnqSx#wdfkqqH|!{S(~hFI>?nHMj-q$$D0>KmmNia+fnq79Yz1z zQB-|{TL51Oi193KUHwP&7!OXkvk)NraZ7alLETRzR9Fm%C-Z zN71C^M$)9sM)6e?P1&qJcWx97c77C1Wk=D}b`(uxN71x)6isJG(e!o{&0t5-jCK^w zWK%S=K+!A$MY9SN%_dMZM4)JPfuf-TMZ*M&h6@zUAy71@K+#+RMRN-j%_C4WuRzg! z0!8x+6fGc7w4gxILIOn#3luFPv=mL=to>X8X}(mhex_))?&;rD#-hze@l_Np*{n}+ zK@^Q}eiSWbN72%D6fI*%(Xw_FEoVp3@^%!hU`Nr4b`-5-Q?#-`(JBH(s|pmYCQ!7x zK+zfkMQaKattC*jwm{K30!8Zz6s;#vw7x*m1_DJJ3KVT5P_(f?(Ix^#BL#{^2^4KA zP_&uQQnYxpHh%@AS$qv{kdd{zXx=wezEB8#{`&wWDY|JBqfq zqi6>^igvW4XeT?0cDAEvj7`y4fudamigpz!+D)KncY&fk1d8?)DB4S)Xm5d{eFTd3 z6)4(IplE-Aq5}kq4iqRlNTBFofuchMiVhVhI!vJGaDk#DgqET$o3;HbAk8bw)z9cC zy13j(I?pd^j-tElD7xE@qI+zL?iDDyPoU_2fuaWliXIdw zdPtz?VS%DY1d1LND0)nw=y8FfCj^R~6exO1py+9VqGtq(o)sv1PN3*{fua`#ie3~b zdP!(0x}jO?yu4C0y4=&hF^bOUzQfjR6kkQr>&^OXS4Pnr&X1xu?I?Q7j-t2iD0;_^ zqIc~mde4rc_w6Y9z>cC1ZHhh;DEe5S=o5jWPX&rT6Dayzpy&&MqAvxCz7i<SO6DS%dv=qJCtgTi7X?|YdycR_( zluvKJHyg!QQS^7SKIZBu`p5ZE^sgO7ZGCdjJ&M}xDC%KHQO%B`4m*nKb`OS>5u8pE; zoF7Hg+EFx}9YxdIQ8a@cMKjt_G?N`gGuu%#iycL?+7!(uP&7oKXm)|3p#nw21d4_W z6wM(}G^aq(TmnUN3lz;GP&BVV(R>0$^9vL$AW*cRK+!@1MGFfQEh12~s6f$T0!51p zEk%R-)ZVRtG>4blMN{=@-P1q1To*0Tr%`+rMN9Xo|9gEDE#v$sTGo!D?m5%j-r+9C|cQ$qE+lDTGgg#HG!hl1&Y=XC|XmXXf1)FwFQdS5hz+$plCgTqV)xe zHV`PiZ&N0+CrdcOQEG`M4#HUH&lwgDqnS6 zDvFM(-qta?PowxMini@jA8}I@ZRh+b+TM<$9qcID(T<{>>?qpVj-oMk6pgi`Xcs$* zcC{(mO`vFZfucPGiuM#J+Do8lZ-JtH1d8?*DB4e;Xn%pC0|bf=6ev1Kpy*(MqC*6V z4izXmOrYp+fubV>ijEX0I!d7EXrZNO>pr!uDwTcGG1fueH-ip~=# zI$xmZ0)e6n1&S^bD7sjn=n{dVO9hH96DYb|py&#LqALZ8t`aD^TA=6}fud^#imnqV zx?Z5@2BD?sxIVS(DoAaaSb~}phu%qZs zJBseIqv&osite$a=w3UD?z5xlew(5P1d1LMD0)bs=wX4PM+Ax<6)1X4py+Xdq9+83 zo)jp0N}%Xzfud&wik=lHdQPC|d4ZxA1d3i1D0)et=w*STR|JY)6(eN{ilVpr)F-+#ir#j96uo0d(YtmOy=ODC!g_>MKyxPoStv zps2q<(Ex#>fdWP22^5VlP&9!+(S!m;6A2Uz5-6HjplA|-qDcjcCKD){T%c$Qfubn| ziUtcUMgR1v9asTreqO#||KBJYUcIejs?J97RTNFvS-iZ&N0+CrdcOM#-%0!3R16m2cE6fM(P>-RvVs9wJ6xNH=aA2`#oO=qL{DvEaK ztk3>X6z%BzDB8)6qMhw18e>P%SUZY#v7=~LJBoI*qiA~S#aB^ua%X*)N22Hy=SR`0b`+gvN73na z6rEv5(V2D>on=SS*>)72V@J`sHbv(N6rC?nbb&z8g#twv2^3u{P;`kv(WL@KmkAVI zE>LuZK+%-~MOO(FT`f>_jX=@00!7ye6kRV+bb~?r!sj-rq3DEiorqEGB7`qYl1&+I7r+@|OYfub)3ioOyk`dXmq z8-b#41&Y2CDEeNY=m&wK9|ekj5-9pvpy(HYqF)7yeiJAfCs6deK+zupMSltu{UuQJ zw?NT9LQB!xoweyJAkDMt6`XgXXqIwM|KH9=@l_Pn`qr0zI*K~_{_j2gx*bJ5?I>#4 zQPj(hqTY5CHSH+sV@FY^9YuX@iuwr@bqN&p7bqGaP&81WXgq`Av zv!iIZP0<_zMRN)i%_UGYw?NT60!8x*6wN14G`~R60s=(~3KT6QP_(c>(INsxiwYDi zCQ!7vK+zHcMN0}4jSwhWN}yk`Z=?7sidO7f zf9d%sTFLoQw6YyVtJqPrsvSkE*-^B*9Yt%{QM9HVMQhnnw6;yrIs!%O3KXp;P_({4 z(FOuV8wwO{Bv7=mK+z@wMI!}@MhO&cDp0hUK+)y`MOz3IZ7EPRTA*kvfugMiinb9b z+E$=wJE5g$`M$Mr6_Doc<+^BvC@Nnj>e#+-qxdR{cJ5oB_@yWsK$<_5 z$MkoKq8Z9f?UVX8im#&Rw7&I?Ux}jAogYPK*im$*9Ytr^QFOK)Md#R2bgmsm=h;zo zz8ysu*c4qTP;`+%(ZvEqmk1PHDo}KpK+)v_MOO$ET`5p>l|a$e0!7yd6kRJ&be%xa z^#VmV2o&8YP;`?((ai!yw+Iy7Do}Kr&{A|t-`c?ykmi%+tB$8e(LLp!{_TAm#aB^u zci;LYuSL;4&X1yd?I^m>j-vbRD0;w-q6h6LddQBVhwUhO#EzmzZHgWfD0*C==m~+M zCk2Y05-56Fpy(NaqGtt)o)ai~UZCg&fua`$ie3^ZdRd_86@j8x1&Ur1D0*F>=na9Q zHwB8`5-56GXeqk0Z|%tnNb}Be^>bGgeODe1d8coq_$rD%=v)8ljVSui`BC(d9Yr78 zQS^x&MW5PH^qCz+pW9LNg&jp-+EMhCP0`l^Mc)V%eJfD(oj}p|0!2Rv6#Xbr^pil* z&jLli2o(J)Q1qKX(Kvyk-vx^P5GeXnpy)4wqQ3=-{t+npSD>h^U+$Pw)Go9Xz1O$a z|IJF#t>wDt{V003+`8`3uTgvzMLqk~hrJy|4d+KuFFT5Q+fmfCqo|J^MV)pO^|hm@ zpB+VAb`|e+3lvQvP&BDP(PRQelM570 zAy71>K+#} zWdw?r6)0LxplErarD&#pwX-WA%^S=2I?fzLFBMWN^lKDfMbRq#>i4`KMXNeLidM6u zXmvY^*07^!O*@L#vZH8iJBrq^qi9__iq^9!T3?`O1A(Fq1&THjDB4({XcK{=kpe}d z1d28lDB4V*Xmf$0Ed+|T6et=kP_&gm(bfV*+XxhGD^RqZK+*OBMLP%-?I^Sqt<?qpPj-tKnDB9bO zqJ8Wr+SiVv{cMW%7brSFpy)t>qJspA4i+dnM4;$Ufuh3%iVhbjIzpi6NP(iG1d5Ip zC^|-<=vaZG;{=M17brSGpy)(_qLT!QP8KLSMQAA+)2}vT1*Exmxh@(TMIV=2*QfSt z6kkQrnf>a^eiB7zIX{Zdwxj4AJBrS=qv$+4iq5yA=mI;6F0`ZQB0GvMwkf(qpy*P8 zqRRw|E*B`eLZIkMfugGfimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n*@q(7AU$!py*bC zqT2+DZWk!JL!jtRp{3~bezol@AkB@-R~^rYq8rO~(Ovx-#aB^uU%&cspGDFA&X1x8 z>?nHBj-rR`D0W9rY>J)~D0)hu=xKqXX9S9#6)1X6py+vl zq89{;UKA*LNucOufudIgie42cdQG6{b%CNc1d84iD0)kv=xu?bcLa*w6)1X7Xeqj< zU+v}!NOPicQ|R6(dZ&E*?EC#1#aB`EaliU2UqsO-&X1x`?I`-pj-t=)DEh*VqA%?z z`pS-?uk9%M#*U(IZHm4VDEeNY=m&wK9|ekj5-9pvpy(HYqF)7yeiJAfCs6deK+zup zMSltu{UuQJw?NT90!9A{6t#8bZaYQo0!2LpifRHy9YRadhy7}QR6v@y7dRh9(bk1j zy{l1t6-B+f>XUvQMNQ{NQ6D>sI_)UxYe!K(JBqsODC%!V(EvM&2HH_Ho=wsC0!0%D z6ip~lG?75jAc3NZ1&SsSD4JBDXflDK$pwn05Ga~bplGl_(NqFOQwtPLBTzK0K+$vp zMbiru%^*-Tqd?J2LQ7GjtF~wbqX&^VMQb=eiq^EFXe~R6*0!T)9XpEFwWDY~ zJBrq~qi6#=iZ-+<+DM>iV}YVg1d2uq6pa!n+Ek!uGl8Pb1&X#1DB4n>XtY4lRsuy^ z3lwc5P_(T;(RKnw+Y1!!AW*cUK+#SDMLP==jS*UkR_&@iT>)v1E?>J|EsCZu*F|Hy z8pT&pw0l?mn;)ZS59deGo^}-NWk=E8b`LuYK+%x`MMnt~9W79Fj6l(`0!7CO6df;6bb>(9i2_9@2^5_y zP;`nw(WwGOrwJ6DF0>Tw+Ep9)Q>AE3c^qxGC_27gjWfC$#aB^uPFH=7U!v$-=SR_b zb`+g&N6`g#6kTXX(M5I?U2I3uC3X~DYDdv!Hbs{U6kQ=ubfrMiRRTp<3lv==P;{+8 z(RBhv*9#QgAW(FpK+#PCMK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZWv=p7y zRa>V5(wwtg7o8nNo0QLJ_jWakucGL|uKFIoMbSgfkD`a|D0;+>qDSp0dd!ZZ$L%P3 z!j7UR?I?Q6j-sb+ik=ZDdRCz5If0_*1&Uq}D0)$#=p})omj#Mm5h!|9py)M$qSpnA z-Vi8yQ=sTAfugqsirx_@dRL(6J%OV41&TfpDEd%nDZ0O_c5VfvxmdYd_COS^TfPMO zQCFk*DvCbqs^9l}6n*aeDEh*VqA%?z`pS-?uk9%M#*U(I?I`-rj-v1FDEh&s=tqH~ zp9G427AX2fpy*eDqTd9H#t9VtE>QG`K+&H9MSlqt{Vh=Rk3iAC0!3~8bGMzMc7dWE z0!1}}q7H$gxg)U{ z>Ssq$mmNj@?I;>xN6|n#ipH~}XnZ@0Ca|MuLYtzA1d0X;6iqBpG>Jgbqyj~g2^38( zP&9==(Uby3g9VDF5-6HlplBL_qG<(+rV}WdUZ7|Ofub1&ie?fhnpvP|7J;H!g_fdb z|JuwIkmkL;D>!}nx9;iRS3bSX*1u7F6-C4P*O&h%iiSHsisrDRXihtd=CY$`Zaa$R zv7=~SJBsGBqiB9RiWaabT2P>9A%UWW1&S6CC|XpYXfc7J#RZC%5GYzwplF0Z(NY3M zOA8b&BT%%gK+$pnMav5mtsqdeqCn9~0!1qe6s;mqw5rfjG<*NrjunvRd*#;k&?q{j zTrsWIzfpV@MQio1pU_q=U}#&%+Rl%nb?hiw*N&p~>?m5_j-n0hDB94DqK)h*+Srbw zO>Bxr3KWeJDB4t@XfuJL%>|0K5GdMGplGx}(N+RQTMHCzBT%%hK+$#rMcWG$?I2LJ zqd?J40!2Fu6paxm8Y@t=i$Kw?LQBya{cE>YK$@qPhtAfFqJia}{%-vn#aB_ZSO5BJ zJ)&rD=SR^#b`TMJEarog`3nvOv)(0!60^6rCnebh<#%83ILT z3KX3sv=r^pzxG!Jq`6l4+V!4Mv}d_4I=g?P_$rFd?_Zz1`f(85*F_gNKZ-82qv#?# ziY~UJ=n^}MF14fRGCPVcx1;C^JBqHfDY{Ca=xTwYYXpj}6)3t+py+ymq8kK?ZWJiG zNucOvfudUkif$Dsx=otSZRTMqazrJZBiXL@-6g_4~(c^X$Jz+=DlXet6Wk=D|b`(8h zN71u(6g_8C^t?dP3j#$i3KYF0Q1r4u(JKN)uL=~sCQ$UcK+zilMQ;iey(Liewm{K4 z0!8l%6ul=<^u9pR2LeSO3KV@LQ1r1t(I-Mn(L?=fhgU$F6P4?thok7Ca_joj{*B_R zDEhL0{fgdE^p*3Y=xaNQzOkd|TRV!rv!m#HJBog=qv%IFihi=A=x3XvUj&MN6)5^m zplF;x(eDC9e+U%)DNyv6K+)dLE~66DaBsD5?t-^%N*- z2o&`aDC#Xx)D&8ZKJQ<9wgS@Jp_(0EMA2g9o_?PJjpC~)>Kai0u1^&8cYYKNu%l?8 z9Yy2WQ8d0CMHARjG@%_u6WLKT$d00kZHgulD4JBDXflDK$pwn05Ga~bplGl_(NqFO zQwtPLBTzK0K+$vpMbiru%^*-Tqd?J20!1?m6wM+~G^;?-Yyw3?1d3)CT8jD(sEyxQ zDSEPe)v@1z);;~x%XQJv0gd9TD4KIXeXf2{G?(+EXl^@-=CPw_UOS5Bv!iH!JBk*t zqi8`piWah?XknY8MFff#6)0LvplES{q9p{1mJ}!&AyBlGK+)0yMau{jEh|v8oIug? z0!1qb6s;&ww30y4$^u2J2o$X=3P0(2?9kY3KX3rP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owm{K20!8NvEk%0| zsC`-iX$~w`Kl?<{4rQD-piz7kMHdaIHztUpi=7`um)KEssU1a^*->=49Yt5zQFNsp zMOWETbhRBt*Vq(YD^PTuK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellY?E*!22o&8Z zP;{3-(cJdclsO7j24O5-56E zpy(BWqE`iqUK1#KU7+X!UDEgy%TgMjz8pT&p^v!_!NfSrWx6Y5E z@9Zf0-j1Rl>?r!tj-sFJDEirsqF?MN`qhr2-)xG;2^9S!Pot=&$miTEBsf;;SecII#Z4q){}U^P^~dJBlW-qi8}qiYBt7XpkL6 z6WdWVi5*3g+EFx_P0{26MN(SU)id-{h| zcsk}7*eJe=qIm|^r<@{+=5>A)&1Xl^{B{&AU`Nq{b`&jSN72G|6fI&$(V}(~EoM`+ zxIobo0!2#-6paulT1ud3X@R0;1d5gwC|XXSXnBF66$FY_6ewCrplD@*qE!TnRuw2( zO`vFXfuc18iq;e;T1%j4ZK0)Tu7R~BD%s2oxPFP;{I?(eVOBCkPasC{T2gK+(wpMW+Z9 zohndtnn2O%0!3#C6rCwhbe2HT*#br92o#+wP;{O^(fI;J7YHpy`wgr;Ujb=;TFs9A zqv*RbE*#h>zS{b=_2`(U_oUOew{=}sJ!IR~^+W;JRerf+udcq;y}8b=*{hr8{kvA} z+txOI*C}0XZG*br8qn4@S=UtKx3vxK+H%6SwrRVr8PwJ`W7kiUw6)FJHQ(fIZ9}{E zoAUo6?!Kd=s{6L>@5!E>NhW264uTXx0TDvzAiY?J^9CoT<$2z)#GUz`H!AUSYtI{#IKG|d zjY}-+;CbT{&vo*=Nr{{;o;NiyvYY44NL0tVV9#5T=rYvvRwb4X_q^4K7e;#CnnYr>=UtvSag67!Ph5Sn=WR@UGS2g^Pc$y@ zyc-iU3q9}V#Jv+eZ(HKGBG0=k(QT^dZBMM6?s*R;UYg-~I}(+OJ#S~?q&c4VbmE#4 z&wD=j~0Lx7_nSOT4nu^S(+{ zS><{A6Jsy%yaS2rR(sx|#OD`#-r+>EwVwB9a?WM${U1p_aD}@8BFVqjxmzHT?6tw& z1d-(V8{KUXNxpWiyAdMEYMb1x5J{f0+1(70_HQb7jwJ0L#p@nP+P`YnJCd}2ma2awY5%U!;7Ic8 zo$fY?B<)}J7!^s{Kg}>ElC-~De_SMKe>wX2NYegx>q(KM{q@9CBT4)FWoJZ^_7{ZC zjwJ1Gcr1-1?XT!t5J}qKv9>spw7(>4X(VZX%h8HR^3lES7K$Y8?-^MgN!ni&u_ltV zpY*>xlC&SyULQ%?&)RN`B<+VKua6|{r`>LhB<;tQZjL1F=S{XnlJ)}wcSVx+9pBp{ zN&A-F2O~-Qp35DPq*?u8(!Oow`AE{f@8IP~(!OxKE0VOY{Oyh;?MpZB zMw0fq_dSuMee!f~Bx#@h`Ye*PPhWf$N!sJj{gI?SfH)9I+C9KSk)-_*emIh}kHLRN zyh@+C-!#!1!{2h1FL5_!NB7&R%3}A-$AMQh-TgKS+E!}fTD9LJ?v`%tUfr2-|3x-d zf7G{fq@9(@?pR}j`+lxS+gxj24ad}rvt&ONb4C8x>r(i(YLSzTT7Jiof<=XT0EKC5HafGX~tqnBjZd&0AlUL}&16~02m z%~+1-XYl%2SvgtRSsmQ3B%{W^UMthRR)tHAYX;#P$~Mqo z&-Z4Jz0RI7P*Lxv$gu0&GpQ%{5#2pCasQ=xEz4@1)V7y|FSqCH+=@>XcfNZy-<#xI zq(%P7&G91c$-S`dE*>k7OoK`w*evy|qwRmPxUg3i?FaFny@}|w2IAh+VqP&@f6Q@p__5b{8lq@W% z_@0*Q9B)O5JcDp+@%VQ{b-V#9qZSXBN+L&8Y&+G`r|9dG4ci;LdgAT1SGQ z%K!8fMAH2!k)X1FME#&j^PuwJph~A8NY4u@r?=42o$hw^NRa97>O|TE2|FZ$qwSC$ z31^Gc3)9kD1@&A`b2+f1zp#E#!=7oZm*@S*%NMi=U*6=uUY2>nmD^D9-Ts%A98`5J;L9Y`=wF)o0H>b2MdwcCkt;^qTtFpJ-tHMR< z3bx{ec4e>CF?F5h%_^BTWmeIo`c8D}&Gpjt%J0jixM%of_9^>y>)d~vS z*{xd@gqM)--WVtJ<ORv@g2??j2fo$z^Y( z4R51&`8&hC3-pTaDu?ezcPZgB6|O>iPId3R)C=7^R_C=XyD)cstQFXAb$xJ1y>9FB zE7Pm&wESMYJ$LPOQO2Ocp923|ANzV2O_(<&{3W>?!M!c_;k3f7pzG15{HnQIJbd-C zcMh~#mj6;ZmR;?9r`8+PXKX=_-Xl`yxf@fzB8OJb_5RnH-i+c|Q|hPw_g}E`%dbdJ z*@2k5;Zkn^Q)OyGqxPGvPwMRH_WL9Csx5U9j;pRo&$8=ezcEv<)T8{$^>#OKj}iUy zQ@xA=Z#ch0*~R3SYeNS(^2_;gNKzpLCkGJG4Y zcw^-^e17>YpI_mocehS>O8Je@9UHyT0!ItE*f7QK_{qscrf732*w; zue$u!&aZHDSGbwmxzo!H@-Z#nwES=0sndPJ^1BLl?d)yqSavJ$tI@CBeW=olT9@5E z?!C;bm#YE{UdoJgaFQi>MyLokq<<|f}?%l7Kl|ga0Z}=9<;kge+?zK`E z9=?d*T27EocYliLxw2o8(;dFH`xxxGd(U&jcTawJ&>x}Y=JLzYl{qiB=KgecmtQiq zcy4LgABc{0>J6CV6sBqo}Z?sA>J?GbhfT*JYx6j}oQ9C(kG@EN$){r*v^Q%Onf#H7C!W-?n+l?BN~^_x$r-+XAR`pw;a?Jg7D6=*(rW>HB=;gq80Gm2(SDV^G- zrAy&mm*#e>yJf!{OQ#jjYF^?VGq_`kYm*8~3(I!+u5f?+htHJT%`eAmF8`-Lze1lC z{){cN=MbkZv;1zLX|(ro`MtsN`+)hO^pq6$F<)1!{1yt8m;C{nLS0bs??2tS6Iy;B z6gGCRX=vY(Wq)etbC_9!0Xr+!QE*uClh{2RKQ^geZe*CB6i+y{9T;a*LN5>VOe0zXg;mLOojw@Bz z_L-WhZtpB><)68+J!wUsFgO zd+In$#}jpQpW;Zpe7cTvbX=n23LV$zxLL=$-OXy3|EP{{x|_+i{gk&Ie|EnBJ4W1R zU+q}K{aWnUP{)q$X0hEz$5Y&|!S)m#uXi_#?b~(y!o34*|D@w_4vFoKI?k;g?j<@t zSTo$u==k>$;m)cZ9(%hl;Mn=Yb-bWnxYy~p%e`amNxJ0a8J|m26qG4 z>))y4SI36?XB}HK5BKppmbx3tUVoX659f#bIUViu-S+Yv9s9Z))b>anS9b{aRXV=W zDcm3HSkv9`_WDQbcv`n`pRVJLJ;Hsrj^FeO_pds(>>KVbI?nGO?&Uh}7#QvsbW9r( z?u3s0hlcw^9WNdp?yGg&Ju=*%=y=5Fa5vU*{Frdh)bXa1!+o!g`^Sa*Hyv9Qgu9!L z3kt)%Qpd*}bbEiiq+@h)xGU*6aB8?u(s9l7a9^Y2+cUzwPscjN;clwqggN0Z*74?& zaNnon_w&O2hmLI)gu921ix!3ZJRNr~4)-fMrY{M16&(jJ3-?$ZFI^t)>vVi~Ww<}r zvF@sHH`8&_1>v5f-gjq;eJiWjP>EJrsD}4 z!hMR4mv0RBCLP~*U-h%w=Sv;yZwhyF9Vc%NcZrVMwuJj39S?2|_dhyzxHa5;bUb@o zxG&W4={v&xx{mR?!(BtiVfTjnR2{FpFWj4T-19)Vzt-`nhr^wx>~ zMsJ2YU&rZhh5HO0?|LWPkLvi#d*Sxq509PqgvS9op7T+-FVXS&z2SaK$J~A4uC3#! z&%<4)iFVs;eJQQpNUH4)sh7LEIjLib-T!fy z@9u_pX$kiQO?9tD$-pqu0x!9eOdcJVNgt&Zdp$p#sW0{G+0?;aW>1aXf9|IE|9!od?sfk2?e2DsC%f(J={WbFyF2Q2cmLVb ziq4VL>N`_KK6|F72@-|4^K&-Qwc>Gj+p^|Z~s9+z!_tLp9o{OkI4uJG%vqSv$Q`;z<5 znV;zI-_^`Egi{d=@)r)o=TDI!Ys%?Guxrvtf75?9@U7Py#JGAN0 z(jDB>`1q1O?ouOMl3iw#vdgtMwYy*HWkL8cp^3Zgs(C{XeLu4Qz~uIk6Gl$onD*!H zz6W>tefswvux7%@34^AucV+0ImL=T>4stKQ%B}9dEUVIWKE~|3vfX2E+yNv$s5*wy2 zabwz3KXo7W`|jSq#QlbY>keE!;rZ0%+BNYT)E-=KP_6!#PZ&Ot>(c#~w4SvGRUOcC zBG;$;FA=Z$pya^*6S+P^4=o*Ec~I7XVeYK(SJ>y^u3oXS>tok9I>26L*X7j1(LuBO zd5?R^>h9)0&%Hl4yZ^3p|84blP4$-U>hCSxeN03SqmgwES@ur%Ctrt(dfYodEs{Rc z9(PAF?4QU=OAA)V><}w((XZ}qn6x1^-Qzg-W$@r8_Y%Lpz1GlL<5MZN+Br+h2)4RE z_0lq8^_-+=G_X&_rA1?}yI1jVaj)PXSEYwNztO#EzhzbXkQZEH=SR}}x{FMYMvn>X zn=xbdH@-F2Pw~`qGvA9g(X8ucD=*qq^GG*ayMJXsvyPi>yl6Ac+HSV>qQ_|-;buGc z7ZqyOahyAIm9w%yh1sGVcmUB6D+*>1OT*Y9}kEZgq- zb=HpCcGs_qcBXB2{km#r*ml>in|92$yMEoZ(`~!!*F!t7?XF)>?Wk>c{d#Hpw%zsX zt)1p}Yj^$nXh&?j>(^J?G02EU8~HD|+dp%K`8hiEb10dqZ!YW?+v;AygbWJo8+B7c z2J2J_8KNm6CumB@P)!LLrYRxAH6>((ri6^tl#o%H5^|y@LPl#N-nW~MD zY1#;xu8ok>wL>8T{BPaupV`OVcZv=Sg>-ixp`tTlCdY)#4(yw_Q$ptGR0)}@DIq1A z5>l!uA@ejPWWJ_^oS`Wp3p6EUp{9f^(nQFa+6Y;!jgYgn5puRRLY8PFWT`enmT4p8 z9BqUw*G9++ZG^1UM##C^2suw1A*-|za=tb~F3?8Eh1v*Nt&Nb2v=MT#HbO4ZM#viN zP{=Gl$NgcFdAIumCt4f|dBf3&u8o--6LLjh-{7ATa-~j{kae08vR+d{uF{l{4Vn^i zwWfq@)Rd5GG$rI(O$oV96Cu}YBV>~{LT=DT$YyPX+^CI^E!qgVNgE+swGnc&HbQRE zM#!z&2)RugA=|VOa=SJ{?$Acao!SVwOB*3~Ya`?yZG_ybjgaly2)R!?6mprL=WhSZ zI`%Q-@=(Ysd;b2I$uS`h2lm4sDIt&OR0-LkDIt$)O2}iH67smFgzVImkS8=Hmo`FP z*G9-2+6Z}58zH;35%QKcLf+O!$UE8yc~=`D?`b3CeeF=lgZ^-L`)8*9V%dj6A?@rw z$p<5EVLiXxZ3Hd}*LO#`$kbRmG@|mWDe6A@WUua6mmzomtm8OJzt%;Ct zv=Q>HHbVAmBjh`6gnX}!kRP-WazGm)KWZc7pf*B&(niQ3ZG`-+jgVio5%Q}xLJn&q zg`dQ3QTUu_1w< zQfx$UKysq)```VC9gz4IyL;kCLPck}$JNoJBQfJ;ike0O`?156qGLHOnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt=CJK+z-uii!v* znoK~^6atE-5>PaafTHOH6rD~$(F_8LW)e^|ix4Ur9P#@)Ao1;PMu$kzkw&W6eY=i* zM%gJUi3Ijz&nZQvoG(T5*itl~Ek$RrrDy?LiWah^Xc1eA&SXo`Vzv~W#YWND1QabH zplB%pMau{%I){Lwkbt7q1QcCFK+(kn z6kS3<(Ha7Z))G*3DFH>75kf_CBK~RzBwooq(vHrRqT^GKvm!C`Ws25E0{gM~l%lIR zUy3%crRZw56m4Wn(KT!-x|S_P*RiGOdbSj8VoT8tY!q!Kpy);dinb6?bQ1wZTL~z- znSi2O2q?OhfTG(7DB4Cq(d`5j-9bRnodgu!ML^Nr1QgvvK+(Mf6m2J<=sp69?kAw= z0RoC1B!r5tjQDRjAo2GN&N?aj$9-ub`cNchzD&`hk-+}ig_NSlIA4k$XG_sewiG?V zmZB%wQuGvCik@am(KBo*dX_Ck&#_VTJOM>75K#0Y0YxtnQ1mhZMXwN0^eO>GuMtqR zi-4ln2`GAlfTA}EDB4Xx(OU!*y-h&TI|LNHOF+?k1QfkbK+y*T6zw6P=tDxN=#hwD z(|xx={E$6x-yuaMcJKP5NX&ehqE91%{k0t_Mf*5kiaujY(dTR_`hqP*U$Uj>E4CDU z&6c8X*i!T@TZ;CxQS==FMc)%p^aBA!2M8$ok$|Fu1Qh*5K+z!rihd@b=obQtekGvj zFabrs5m59y0Y!fhQ1mAOMSl@c^fv)T{}52*rIkI(&rW?kDndX}8X;7)H{ze>fW*h! zho4WRsMJ0%`DropWr|{Hf&H~FDMcBaFGZPbDT=eDD2pvc*=#AwVM|diTZ$5FDN3@X zs1h4Rl?f=SLO@Yf0*a~;P*k0Oq8bDg)g+*(76C;^5KvT`fTB7C6dg%GQC$Lx>Jd;> zpMatU1QZ=bKv6>iiW(76bTomFMaK|O)R+(|3ex-=9guj!ef2$>o)$jRpJpG6nxw_d zmnk|fEwH~fD5a=5=SxuwwiM;DrKlxait^b~)QT-dt=Ur4hAl;H*;3SwjiUAh6m=k= zs3QSIod_s8o`9mx1Qc~4pr|VWMcoJ}>P|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk-P zPe9QC0*VF_P&9~uqQQhv(Xna%Hx5WV?!I3s+DwWbvky!|(qiVz6b(-c?5~|lDH_4~ zQZ$k+MWfhKbRt`dMzf{pB(@ZdVN20iwiKPrmZDSGC>lpV(WwL!okl=W0Rcth2`DNg zplAXCMH2}qnnXZR5dlS$2`HLEK+#kJilz}zG@XE=(+Mb=K|s+=0*Yo4P*hAn(QE>W z<`64EoGx<839G-5Ky$7fT9%y6s;tn=v)Gd&Lf~`6#+%(6Hs&k z0Yw)QP_&wWqKgP9x|o2XO9&`hLqO450*Wprpy)CJiY_Oh=n4Xgt|WwtO4I!L4oJMQ zeTrzF6y0v0bzGMgGhe3Y>a<{86Diur`BHQZTZ*n_OVM>~DY~95MVr`CbOT$8HnXMZ zMz$1fVWa3K0*ba0P;@f^MYj-8bSnWxw-HdZjew%t2`IXQfTBAID7uS)qPqzwx`%+G zdkHAoPC(Ip1Qgv*K+yvP6g@~l(L)3jJxoB+BZN@VRcZbX2PD2G;^1tMqHpbE(T=p3 z`7%X2(*pZz6H_0Hp5S~bdXgs|D8ZJZBwLCqv8AXoTZ*c%rKls!l*r4FZa45>Ql&fTAM^ zD5_0BQ5^z`jwGO{E&)aL2q>ygKv4q%ijE?ns38GGjR+_@nt-BX2qhK)@&(i z!UC;Al=F1c< z^aJ~A$5VqIComttX)9Dnh8}4BsE`fW-G1oCQ*}+emHjW9G{gUF!$-*Vd;LUB~%SbUj;& zHnFAX2DTJ!W=qkHY$@8pmZF>3QnZyVMK`libPEARw-Qiv8v#Yz2q?OpfTBAHD7uq? zqPqwvx|@Kadk84Hmw=+}1QgvzK+*jK6g@yd(SrmOJw!m!!vqvPLO{_D0*W3bpy)9| zsA!|_-{gSApEpIWIJ0Yx7ZP_&nTqE84Y`jmj8eS}ca6TZLS0g2DG&pJLS zMNittqR;%8`7%Xc`GNhj87W0ybG{UP!$cyS> zJBlI%6r~YRuEpeUVyq8I^18H7;L7rx)h0g1P?Pgj2_MQ7T*>&$4(e3_!0 zXkh>BN=i{K=Sxw7Ek#MT6jfqNQDwFiRbfj}RkjpWV@pwWwiMN1qo^hUMYRYhI)Z?r z+5{BUA)x3;0*dMqP*jhAqWT0BH6WnqC<2Na5>V8LfTE)bC_09KqQ(RiH6fs=DFH>t z5>V8PfTH6FC~8g!6=g;J1rA8u{<(~3b~JpXKid98YY~l^FH_Vi8eG*widu8N6t!VX zQCqeYwPQPV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*X!`plB!oMZ*Xv8csmb2tuf+ zWz>Jn0f{enGny|&d+cM;$Y{)bnWB@Tf&H^jsgFftIA4m!vZd%`wiKPhmZEWNDLR!c zMW?Z)sDLd+PacfTH;X6rDi`6`dIMqrIJ?{q|YM(NZ)x z^?)rJGhe1?aWt@hHY}y+EY6prv)NL#ge^r&*;2HOEk)U&Sj(M zJOYYV5m0nK0Yw)OP;?;yMXL!Yx`=?HiwP*Ygn*(o1Qe|$py*NpiY_Cd=yC#zt{|Z3 zN&<@35m27DfGm4oLiV`>f-cQncK@W$l`1%zT-mP0_&q z*}0UW8#rHzHnXMZMz$1fVN20XY$@8xmZF>4QgjPjif&~~(QRxLZ6l!Qb^?m-AfV_@ z0*dY;py+M_itZtx=w1Sfwi8fv9|1-86HxR30YwiIQ1lQ1MGq5D^aue(I|wLxlz^hg z2q=1-fTEoQ6g@!*6AO(Q}+HMbERP z=moYEy~viLm)KJDGFysXVN21gY$n-2@c9ML^Np1QfkP zK+(Gd6un14(fb4xeLz6b9s-I!B%tUc0*XE+plB}vMV}B*^eF*F`v@rdjDVug2`Ku4 z5Gr~)>c8!P#GBe5V$VoX8~Zxim(iH{GDY7;1N&z$Q;PO;z7&1OmZI<3QuG5`iVm=) z=ts5`9b`+@ zj^9YpMfN9Jb`UdPrYIQ%_RprK6jkDUDXPqtqAF}Ds>+t4YHTU0&X%GYY$>YAmZDm0 zDLR6UqS^!$)ghqhNCJxL5>Ql+fTH>Y6g42A=qLh;8WK>{h=8J_2`D;-fTG3(6g45B zs3`$O#}ZJ~jDVu!2qQ6B<|`VvsokAR~71QZP*plBcgMS}<^8caaZ5CV!$AfRX{ z0Y$?IC>l;c(Fg*HMiNjoih!aM38A9afq%0D5`V%z7PXP0uJ*BLbPzLNrs(7#uz$8W zrRWsSm!ffODLR!cMW?Z)sDLd++DFhTvC7@^; z0Y%dZC_0^hq8S7f%_N{`76C=Y1Qg9CplA*OMRN%#Dj}e#lz^gn1Qg9Dpy&(&iWU%1 zw2*+JMTAh%n85$u0f~3DyFz27sHfdYIx~owFH^K62<)HzPAOW-`BJouEk)U&Sgu{d2A_K#g?M;*(kbzfT9ZtC|XTG(M1FlT}(jHB?J_$A)sh20Y#S* zP;?mqMVAv$bOixLR}xUPj)0=|1QcCGK+y&QimoQ0Xd?kd*AP&2EdfQ>5kf_01%4X` zBtFI-mYpp{v+ZNi^+C*hnW7tm!2a3zl%g%1FGV-8rD!W#if(30(JgE#x|JWIQ0Y#4!P_&bPq9+I_dXj*mrwAx|nh+|wA@CPDAo0m|S7@^oJ?CB) zeI|&RFH`hF5L|t-6urp#QuGpAie6?*(JO2zdX+6jud$_Q7h8&6XG_r=Y$`OF9AiL5K#0f0Y&== zDEf?mqR$B^`htL>F9|66ih!c838A9r0)M9i5_kWog%^EZie5ER-vlx9Ws1HJf=|Xt z(GQ$2MF-eY^dnn}4zi`_C$cfTC;y zigE}j$|Zz~_6L6YsZNo7-8K516rE#twG-(v^JR*vqz8=)q^K(AOHnnp6jf(SQ4O{f z)nrRiEw&UL!Iq-hY$>Y4mZBrsD5^_9Q9S~R>Jw1ZfPkW-2qeEeI&eBcP}y0Y&))6tyCts5K!}R4Lsb?104k z+P&+_>ER=N`}g*uZPH`r%M^7;4`vohQAf^~qE2inI-V^>o!L^P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_V^L_pDC0*ZzZP;>$TMMDWF z8b(0TZ~}@(5KuIdfTB?Z6rD&w(P#pSP9mUa3?Wq1F5SP>0g2DDKg8Ng(Jl7nkg@48 z^JR)oO%Lv!C`G4nz7!R(rD!}`iVE3MG=VKe6WLNUi7iD%Y$=+|mZB+a6ip?dXc_@U z(+Ma#oq(bl1Qg9AplB8WMa2XZ%_g8|4gp1T2`DNdps199qIm=q%_pGf3<8Q45Ky#` zfTBeN6rD*x(P9FM&LV`0PD%IQbwJ{4?X!;Kr06L76YcEunE5hA=cEU}6-m)@&X=MU zY$;mFmZEdnQgj|$idM0u=zO*mUBH&23)xb%nvJ512q?OkfTBwXC|W~6(OLqEE+wGo zG6IS&C!pvG0*bCAplBTdMe7MDx{83J4FnWjO+e8`0*bC7py*lximoG|=z0Q*HW5&C z10htjG~KT|*(rL~J{B#LqFCwyTYAiVnWC-fLAR+=bTj8m(JgE#x|J{vEk$>+rRZ)pitZtx=w1Sfwi8fv9|1-86HxR30YwiIQ1lQ1MGq5D^aue( zI|wLxlz^hg2q=1-fTEoQ6g@#e(USxeJw-s#(*zVfLqO591Qb0-2o-Hf_a`|Z@oVkF z&rMQP)5i1ZG4o}LUQQ2IPM4xrIA4lhWlPa(Y$@8smZI0$QuGE}ir!>P(QdXBy~UQI zx7jFqhk&AY2`GAxfTH&aDEfeaqCEr@eMmsjM+6joOhD0I0*XE%py*QqiuMsu^cev~ zpA%5@1p!505>WIN0YzUEQ1lG}Mc)!ow4V?vdNJL<)d7j$XMdu-Bt>29VgGmOG4o}L zeoPNunju98IbVu?VoT8>wiNx$mZD$SQuHfZiVm}-=r^_${mz!6KiDYxlYpYX2q^lS zfTDj0DDq-@*p8wI0Yzy96!`=cMF}Vh2q;P?peRN_Q3e4;nFJKY2`I`UpeUPwq8tK> zatSC(5KxpPpr{fdRP;l-f4~8W7u$!Q15$LQ-Mg+Fi6pXQQYA0Yyga{`K55KxpyKv7Eqit-64YDGX%YXXYe5Kz>XfTDJUP*K&G z-_8MvzidA|R4o=h(*NE*Ftv}x%$F%TJ{FubM~XUgz7%y~OHo(06m?@uQFpc!^Q6w?00N2z5>PaVfTF5~WVRGdVN20ewiHccOVM;TicTk> zXa)gAGYKe~MLT|5fTFVqC_0;fq9p_rEhU7CPK)_ZIw0{{_OPr#igwvIVK0lt%$F%z84LEgf2=q4 z)!1`6Uy9CSOVKK}6rInOq6^qkbRk=cRWII0YwiJQ1l1^MLP&6 zdX#{o#|S8ToPeU81Qb0%K+%%~6g@>i(bEJJJwrgzvjh}9M?lf@1QfkMK+%hYP|?jX z{{#ml{-XVC>@8B1VRyA(ip9*ADS9my6fcsZU7RmPud}7-4Ym}$$(EwsY$2`GvZP!teQlukfVjDVsH0*W#TD2fwMltn;MHUULB1Qg{G zP?R8`C`mw3B?5{n6HruzfTF5|P|?Ad|GonfuVLSq_LCH48>wm;G4o}LYGnj}oGnF1 zaK04PW=l~WwiF%7mZG|BDXPboqWWwpYQUDFqu5f^kd2~71QZ=jK+!P-6g4KGs0jf@ zO$jJEmVlyW1QZ=dKv8o7idqm*lt(~OO9G1W2`FksKv8P~irNrR)Rusvb_5i)C!nYU z0Yx1Np`scYe*Gm*Q78K**_s*QBmHOX-gT#pnE5hAT{D6n%cQ6q=Sxv{wiNYXOHog@ z6!l_DQE#>s^Qk^Kv5|HMe_(KnomH{83Yt9AfRX=0Y!@lC_0mX zqQwLhokc*=*#s0VA)sg}0Y%FQC_0CLqUD58QDKI^%>jvDYTsWpL5g-5sTCP9^JR)w zWdyIRl%n%FUy3eZOVNdFDO$~zqKnv4bTM0sE@4a28nzUzWlPbeY!qEaK+)v{6kS0; z(Uk-gts|glJpn~m5m2;&fTF7jDB4Is(KQ4VT}wdGbp#Y$Pe9Qo0*Y=RplCAzMK=;q zw1t48n+Pb{NyuDY`u)sIp3m?%;eWx|1zM zcd@1DZnhNN!WIN0YzUEQ1lG}Mc)!ow4Z>Y?+7URo`9ks2q-#0K+%r`6dfdligsoAXFDM7gO7vr zx)fb%pUD0xBWAu#(XSc7b*rW5Fy~9rZ)_?0oh?Owu%+lvwiNxvmZHDeQuGg7io8rc zZkM768%1dZ6!`=cMF}Vh2q;P?peRN_Q3e4;nFJKY2`I`UpeUPwq8tK>atSC(5KxpP zpr{f7MU@FCszN|fRRW5t5l~c}fT9|NP|?pB{?iUfywE=U{31n%?Ng97Gh^n<6xGQL zKEGIsj^unPs>_z5dTc4G&z7PFY$-a5EkzC4Qq+hoMMtxx=omJN8WT{|gn*)^1QZ=h zKv6RSijE_os5t>eEeI&eBcP}y0Y&))6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*U< zbt0hXcmj$#6GBBtWcu+-oT5f{hq`uV_(*?D>H%A3%zT-m9+^S2wNliR^QEX4TZ($K zrKk^Eiu$sps2^L3`m?2I09%R%vZZJc8%2W&C>laQ(Fp_;4JDvx7y(7Y2`CytK+#A7 zibfGobRq#oqX{TFiGZRp1Qd-Wpy*@*icTS*XdD4WrxH+f8UaNG1Qd-Yps0`#D(aT$ z4|71`1MFi_cPZNJ{(y^4$c&jUQ#3g2K)&X%In*-|uvEk!fg zQZ$P#Ma66>n$1Sh90H2w5>Qk^Kv5|HMe_(KnomH{83Yt9AfRX=0Y!@lC_0mXqQwLh zokc*=*#s0VA)sg}0Y%FQC_0CLqU8h>tstOiB>_d}5<*3jGW{zZkobM}S;rzNy4Jqg z=)BCB`7%WpW(E&jAw{b>Uy3ebOVPz_DY}F$MQhknw3aPJm$IekGPV?5&X%Gp*eJS^ zfTDE-6s;$q=qdt=HV{yBH33B%2`IXTfTC*&D7ub-qU#AL+C)In4FnWzCZOm>0*bZ} zP;?UkMOz6dx|x8YTL>t+m4Kq#2%)0$GyOddNW71m(F>%gpFQl~mKif&rs%HB;IDO3 zbT{Wq(LHP_x|c0Q+u2fdA6tsEkzHprRZTciXI`LXa@mBj}lPy7y(6( z6Hv61fTAY|D0-5BqNfNbdYXWuX9y^ImVlz?2q=1Ft=^wS;DQaV1#=ldF?y<*cuV=>0mnnKHGw8KJir(gYDSC%3Menku z=smU+z0a1S57<()hb=`PvZd%FwiJELM$ujZiasHr=u-lU_7PC@839F~6HxR80YzUD zQ1lf6MPCz8^bG+;-x5%?pMaw82q^lVfTAA=C^|qu(T@Za9VDRWCjyEN5m59qAyo8c zra#pIiFY+PyQQeezBKzwX3Tt!zT2q?-RpeU1oqBsFXSp*bi6Ht^xKv6CMMF|3mk^~f0 zBA}=;0Yy~^D5^?8Q8faJsuNIDgMgx%1QgXGpy&ufsOWH}e}@ASf8XvG{U$|qZPbp( z%$F&u7Y|;$R*LF#z7#cJOVLqmDQd`;qDE{fI+`s-$FQZSFiCYED2=3j&Jr2qV8RfTH#U6m=k=s3QSIod_s8 zo`9mx1Qc~4pr|VWMcoLYq9fz}AqOPB$Ugkkjfao)PqxuL9y4F2sCPW5wn>WmaK04v zWlK>%wiNYeOVI$f6b)oc(IB=I4Q5Nx5VjPZz(&zf0*ZzaP&Ax?q7eiXjU=FG6ahsi z5>PanfTEKKC>ldR(O3eCP9~t}6atFI5m0n00Y#?~P*gxb(Rc!i3JEBhKtRz%0*WRP zLPb5}ekTVcZhuozw3ig!VxuS?Ghe1?T0A&qvlLC|d?`AeEk!ffQZ$n-MYGsaRLqv5 z*=#AA!oG(Rd*iy8XEk&2IrRXxY6kX1iqAS=^bR}Dg*0H5%JsU+= z5m2;&fTF7jDB4Is(KQ4VT}wdGbp#Y$Pe9Qo0*Y=RplCAzMK=;qw1t48n+Pb{NH+=mi3bUL>ICB?5|GCZOmQ0*YQGpy)LMigpoD z^g01WZxB%QCLvUGcihju*(v(n;M^lc8&eP1;xY4Oir$R}&2N>W_c&jQ-e*hE2W%;megcZVBcSMe0*Zbhpy&VrML!ZybdZ3ep9m;AL_pEc1Qh*3K+&%R6dfjnir$X< zBOH+Uw+81ODf-DidGuR6X1+|(U-6)1n-u-c`BL-`TZ+6aJ#v?#2wRHM*iz)Pr6|gl zqJS+$>1-*Au~C#kKv53CZH&XfTCOiiV_4AB?&01L_kqx0*a~-P*jzG zqG|*bRVSdR1_4Di2`H*XK+zEd6xAl6s15-|M-oCsf5iRu4oLh>`&jg+6kX|F7Ok5V zGhe3YsI1_jJEW)~=Sxu|wiF%BmZD?WQq-6&MNQaJ)RZkn$FilU8C!~uW22}!0Yxnc zD9R(Cs3ieK`2-ZTBA}=>0Yz;HC~8YUQ9A;P+7nRJfqpqLBm?jUu4vL;{LN6Hs&# z0Yzg7C>l#Z(a8i9okBp-I0A}JC7|du0*VRl>dQ6T|E69_1pNI=mf0*Zkbt7qgiz7+EPuKK6937* zjDNZmonm*AF3O6TFH^KOE4c7JDY}&NrRXxY6kX1iqAS=^bR}Dg*0H5%JzI*dVoT8m zwiI2>M$twBimoA`=vo4bt|Or6dIE|z5m0mk0Y#e$D7uk=qAdgz-9$jqRsxD{CZOmR z0*Y=Wpy)ONinb9@bUOh>cMwo?Cjmuw5m0nDAyjlpmVcK658( z=qUn z(I13R(R*2bX9pzytbNw;eJT3TNd1`=Ghe32%MMQ6Aw`jFJ(8EAG`1A^Y$=Mer6^!a zQ94_SVr(hOU`tUZTZ-ar6lD=mlubZU4gp2E1QaC*C`uAgREdD1$^;ZuA)u%#0Y%ja zD5_3CQ4Io$Y7$UXi-4jd2q>yeKv5k6ijE|ps4f9T^#~}cPY4zLo#mh7fW*JFZ`l7w zidwmsMH^(t%$F%TIy>0>m=qnu`BK!FEk#Y(Qq+_!MaQzGs2N*|j$=zvbG8((9xQwbr zqNxNFO(URaIw4flKikiJ!YK;uvyKC#$o|5a=;_%p^JR*PvxB^+q-ZwhOVJ#*6wPHz zQ3+d$O4(90k1a*>*-~@{TZ$I2rD!1=MT-b1I+K8+#RL?cML^Nn1QabHplB%pMau{% zI){Lwkbt7q1QcCFK+(kn6kS3H70t}{ zM>!zzwswblmK61~u_ilazD&{O*}=SLr05FHm!d1#QnZdOMeEs8bQN2QHn64WYPJ+@ zWJ}RCY$>{yjiT!aD7v12qD=%8-9SLmW&(fpOF+?fLa6A{Y=46T5a5Gg1%O zvSa4U6g`w3Jo20rJ|@bC*)j8Fiu|0Q-^)@I&H48u{eUe+>1-*A zv85=3Ek&7ZDT=eDD2pvc*=#AwVWTLQfT9EeMM(mRDiKgrnSi1y1Qb;zpr{%FMb!x? zszE?eO#+H)5m0ml0Y$Y5D5^t1(UAlc)g_>)9sx!52`FknK+#bI6g4D-iXu7w3cktKwc3ZIlx;U#6%@PH@qyQq+|5^|9z!wiGpEOVM#`DQeD^q84l^%417W zOSTl{v!$pN8%3=NC~8AMQCk9v+7VFHo`9kb1Qc~7pr{i8MaL6R)R};yE(8>HC7`Gq z0Y%*jDC$8#QBMMjdJ$06n}DJ|1Qhippr{`KMg0k(qGNLWdmNB>Q-jl3ivF}O@DIp| znJ-f`Bqw-tmlU1A`BF5LEk(oFQZ$?`MI+c!G?Fbvqu5e(B3p_^v!&=HHj2g&P&Af+ zqLT?II)#9uaRd~dNe^MA2C}G4o}L=H>*o-jt#e&X=N6 zwiL}{OVNC`6rI7Aq6KUzTF927MQkZLlPyJy*(f@TfTFVrC|W{5(NY46mJv{N4gp2W z2`E}YK+#G9iq0jV=sW_7RuNEiJ^@7+5Kwd>0Y$3`D7uJ%qKgSAx`cqDH3Sr`C7|e1 zLa1nVj^EV*iEoHIICG@vSi7rzSx(G+nWA+$LBU&6w4U>&=qk1pZD32$)odx+$d;mO z*iv*YTZ*n@OVRagDcZzF(G3I?Z6=`TMgoeq5Kwdz0YzI0D7u+|qFV?kx|M*U+XyJy zMnKW+1QgvtK+&B96x~HY(cJ_T-9tdpy#y3(C!pv)0*dY@py&ZYsOX9ue}w}Qf6+ec zc%>9gvU}GL=ETgGDcX?}Y8(Wjg*Mf=!N^ch=DUkE7rm4Kqd1Qh*7K+*366#YR!(Vqkq z{Y600-vku>LqL(2s|V&NiV#9YALsbV_no5q?PJkiDf-0jU8m*7%$F%j&kgeTNKuUQ zr6_|fMVV|VinFCCi!DXjY$?iNOHnRciV|!oO0rQ@iGZTY1Qb;vpr|SVMb!u>s!l*r z4FZa45>Ql&fTAM^D5_0BQ5^z`jwGO{E&)aL2q>ygKv4q%ijE?ns38GGjR+_@nt-BX z2%(~Au0PrViC=GUg52OeqIM*@mE5m0nI0Y#k&DC$B$QC9+rx)D&+ zoq(bq1Qhiopr{uCMZF0q>O(+LUjmBy5m3~hfT95e6b&SxXb>S()HK)M=zzp0*jGS~ zm7=$e)ZpBh`7%Yra)U?rO3`r6m!c7DDH_R^qET!qI*~0!quEk)5?hMKu%&1$TZ&F* zqv#X@ipCL8bSeQwrx8$8KtR!W0*VR=D4IY((L@4@CJ|6nL_pDG0*a;(P&Ac*qG<#a zO(&q}bOMTI5KuIefTCFh6crOtG@B4AIw9Bp)B%Y~DY~95MVr`CbOT$8HnXMZMmCDJ5Kwdz0YzI0D7u+|qFV?kx|M*U+XyJyMnKW+ z1QgvtK+&B96x~HY(cJ_T-9tdpy#y3(C!pv)0*dY@py&YtiXJ4O=ph1%9wvl}*5~@O z9FTareb(_RDH>~!^dHHMnJ-iHcy4gXmr}Ho^QGtswiG?dmZGQFQuH)iik@Lh(X(tR zdX6nc&$FfI1vZLaB%tUe0*YQHpy(9>ie4q4=rsb0b`enYIsrv*5K#0c0Y$qBD0+*4 zqPGbsdWV3bcL^wZkAR~02`Ku2fTBGF6n#iQ(MJRneM|@yJ(}xpcR=FR?XJ*cQnbgu zeRgkd%zT-m&vJvezLuiTIbVvtU`x@LY$^JREk$3mrRW>B6n)EJU5KwdiAyjl+!avsmiI29g zqcxYJ^K1-F#LSl|8kq>T9+09@oG(QuvZZJ=TZ&F%OVJp%6pdv|(aCHnI)yDoK+$*tiV6uRnm|C&L;{K?5l~b_K+$9Zilz`yG?jp&X#^BaC!pwb0*Yo3 zP&AW(qFDqK6%$Z2n}DJ@1Qg9Bps0ipDjJ^fUv@y^|A)H!0B@@P`~QE^Bn_02w15m5 zrGU&X_K;at5}-^eLrPl;Wt5fSi+Dw6>Hz`oGg#txeDNwYH0!7;?P_%;r zMLQ`_w2J~oyD3n#hXO@=DNwYJ0!8~NP;`I-MF%NR^cDq*-ljm&I}|87M1i7rDNIF6 zoz@ryB%r3=7cCP-4*iOD*y+%|w4x83_7V3*(T7YgijI;+(J`_p`iLxwJ|>HzPspO^ zI9U{(Ad8|;$)e~a8AYE_py+c76rG|#(P;`4ouNR{7ZfNuOM#+u6e#+V0!3d@py)gW zioT{m(FF<=eM5nwZz)i8kpe~EQK0A&1&S_Hpy&z(impP-LS(k(~lX{uC&3P?(B-bXtExH zzOL>5Jb$fBq)Srio^i=yYqC@M;UqGA*% zDo%l-5)>$Uo&rTBDNt030!5`MP*jEjMZpv(DocT)5DFBPqd-x43KUhKK+y{nD5^+- zqDmAfs!V~RDikQHN`azk6sDp8m$ixl5|F6jq6g8qiQDX`eHK9OJ zQwkI{qd-v<1&W$epr{1}ids^js1*f@T2r9NO@Sg01&X{BC~8B2qP7$$YDa;hXbKdy zr$A8$3R6+I%bKcy1bnZLt|LUzWW8hR=yGUZTG2}``y4~hAi}V9WqMH*Ll#Bd$fBq_ zSrqjki=v)nQS>rd6!jvDqFAyh>P<#b90iKvDNvL^fucSXC`zP2QC|ua^`k&h5(SF- zQ=n)71&RhzplA>UijpZ%G?)TKDHJG5r9jaT3KXSLpeUUJMHv(*%A`QiPzqB~XP0%q z0uslc+MPtdLXdGD- zjVFtu31m?;k&L3(DNrrm9(-yB^C?iYfC5EtP@rfb1&S6?plC4#ik48IXeouMXoSo9SOE#}==ZKiilSHb zzG#`tp?zsZt6cU{>gynU`=ZrMFN)TXMbTQaC|XArMeE6;XaiXkZ6u4LO=MBDnJkLl zB%^2x1&X#(plBNfinddrXa@y~c2b~d7X^xTQ=n)M1&a1kplBZjiuO~W=l}(Z4pN}# zEeaI9O@X3!C{T2W0!8mqpy)6Kir%9@(Gdz$(F&KfnF10}Qty6NilVmq9PNFVL;KQ- zj=Ag!4pHqUckyC^|_NMW2yH(dT4Qbc&3k(-bH=LxG|% zC{T2k0!8O2Q1m4QioT*i(Rm6KeNBO)3lu2&h5|+3QlRJ}1&Y3-K+z=%6kVo3(G?05 zU8O+L_Y^3)MuDOqC{Xkxg{kO6mvyoN5^zAjMRZgYt<^`@*If?nODp=-W#61v6#d5Z zqUZ)$6#Y&XMSqY*(M_@_x=yWTQZlodQMv6ew~~pePRo zitN*nqR7Scq9~9oih{_Zs1R8c z6()4MKuHMwF-)&T1+pBYLi7#9kM8@OBO}-$fBq|Srj!O zi=r3FqNpKR6g48Fs4)eKnoyvqDFup}QJ^S_0!7U!P}G6~MJ*{%)QSQ{ttn9Cra+O0 z0!3a56t$s1QCkWWwWB~$GzE&-3>e4N(-J zkFL7}IN+6@C z4+V-6DNxjx0!95OP?SW0qW%;p8bE=fffOhjM1i7Y3KR{dKv4<>ic%?1G=u_0X%r|* zr$A8#1&T5$P&AYRMZ+jiG@JrOBPdKoT?4JF6p(;DdS4VHibm*Hw2^@h?Mo|qEztgc zkSH3>^rC1CSrm;Wi=uI4Q8b<`iYAan(L}N+dYvqaCXq$aWHO4TP@rfk1&XFoplCV; zie^xtXeI@UW>KJMHU*02P@rfo1&ZcTplCh?iWX3y=nV=KEu=uvA_^2Ora;jW3KT7+ zK+!S^6fLJf(FzJv(WpS{bp<4#h~E9YDvHu{SQ+ThzO z3KZ?9K+ypT6dj~M(OVQKdYb}8?@*xV5Cw|fr9jbP3KYFZfubW6D0-g)MITV0=tBxq z(ds~JH3cN#xPI4hjVKzd_eDno9om;x^huz-ZBbEloasf;39=~qlq`x)l10&HWKr}v zSrnZji=xwHQFMkZioPJD=qv?_&QYM~O9~WyMS-I86e#+d0!0@nQ1lH2ioT^l(M1Xr zeMfHv;7k2(7v>y-vjOQii@H@m|hg!B#WY3WKndREQ;=sMbTZdD9R#>qI+af z^e0&q-6x~y0R@U4QlRKB3KTt}K+$6g6#Y$sq9+t6dP;#JBS=o$QDmV&ksk$$tQ07+ zQJ~09fg*nj6genRl!pREc_~m7K!Kus6e!A1fuaHwrlQ{htp^p5fE{{YbVC$9)gP)A z4032+T2WAt{lfF2s1VbOqQYcRRD>*wo+FE*qGVB2j4X@ zC<>)OQ5Xe^!YNP`L4l%33KUhRFcrCitWOk>fU5dk$G{--On;)nW2+J5(7v>yIzjd_ zrA1L)rWZx^$fBq|Srj!Oi=r3FqNpKR6g47?qQ+!V)PyXGnvzk}i~>bb6ewy=fua@^ zC~8T8qE-|rYE6M6HwB736e#jipr{Q6irP}3s2v50qA5_+o&rT3C{Waq0!5uDP}G?M zMO`RR^b!S%x>A^mY6V%FD$eyTvBeCyuw3nG)6!jvD zqFAyh>P;3!ab!^xPZmW9WKqBDLCIyOSQJ`ox1&ZcSplB`yisn(EXg&ps7Eqw* z4GI)3q(IRk3KT7-K+zHk6fLDd(J~4YEvG=y3JMghq(IRs3KXrTFcpmsvYu8z0aZrrp?w(z4L@7CywAU2F`OIKN4AFZxCZC^O}$N-$5}v~&E&#c)FkW85I2TqjjONbosu)IVXSq+Y#4)_i<=ros`GM`VPrTfv^0$2&Vj8BW0Z53$1uh? z@3%3G3C@PmhB4VWzJp;*cOLI#7_*(umkeXRvrCL&EOIXGZWzm)S9==9Drd!5!&v7` zjx&r+&OHf+vDNu7(J*#88z&jYUgyLChH=pO=^(>6?}0dFm5=z zO*M>L&Xv;*Bg^^YOv8BKtUAXq9=nFjQ|sU2I4`Rsnm;cPhSUap_-**Tmw|ztya{#if5ORcnh&|6ZXs7S}IF)HboW^l$d) zY;oyd%@AX8>F?I>X>sW2J60V{z%PCr+}s^!LjSvbgjYgr-_t`WqfIEH3>O zeZws-{T*wgEH3>eSz|0N{VhimEUtI2s4Zl1>F*htZgJ@^ikNM2>Hq0J-{R8$ReO=e zrT?$(GK)+9XUSC-m;T>w>ntw)-<395T>Af;Y_+)be;C+lap`~Yz1QN>|77=|#ijqv z5VtHYeFT_gap{-v2Nsv!2S2tLfpgW9#FDnEkXWGiY;tbTy3G6xfZUZnuSqP{n5Kf z_4s{%>%a7-&Ha-*KUQ~VH9DwC{49?O7BDR8N8MI$ov^U*w7BrT>8auAX$j$JvFQnk zv8ib(8HouQiG9Ko(nh3ar060cu}@}NVtTIY^zGHH>xHML^-u1f(SK;75uTKioERQA zC~7Npwk&-efAt|o^;Pmi*2??=r zY02S{5wSI5t4CCijE#)YWvD7c2d4~93{8xS?;jc&5mqBqUmd2de&(w1{(}<+W%fx7 zPmW7S>Oc7Z_r*vbk)C@^^h*kFn${~%3bBh9x;%r(+JEoFdO=jq{{ zQsdGFw#*zH+gUx9e(eWkrpI<{TDxtn|BcNwG%h1iuPwtcH+0|3!3j00*9c3{6k_`% z_KnLNlo6XTA~i8REJ+Jfo2yU%!5J#3T|uX)7O`qE6QWX*lT!w(PUBPiGP{qWwT8uR zFZ5si*n|8nc8j&&i}oOE@nE~%Kg95}S&G>6>A`6a)`Pl*FY2qSs|gB)+Jnp4gG#Ab z);IlsYbuL9IKm!O`v3B~_`m(J`!;B>xjnwQFWytQD1g zv36a#WzD*DO_?~Nrg>e9D7j6fx^e$DDJiLuM%$(_u~F?hS2yR~oJneB-(MZ78aek{ zJ^Oy6a?Mf}usRde&c0PW-!f$mPVe7uaAKcewR7^_U6d?WWJ~6vF7Pm0WIv8bwJ^Th z*Hbr(ja5_Es2*$1AyVBL6SQP*O=WJ)a^|4cfVx?q%;e+|=A7iVHM!%aQq;*_0JTE1 z=bU{fHMx)GIV(f00=c1DWOFsDxtJGnEkYe8RV&YTrCPBvU9Ieyspa8LtLxjx>fN{O z@Xa|!Wlt3u#oeiem#MUZT(9TO$0n@(*@c|^*rTx$Nzl*XWx!To}LfBnl-8mIUB!*T$inZJCCfJ zJ*&tZZ~(zaWR5`fDCDkvD%3(|Z+o>1@GU@O4yQ=v$?PJyGDlcsOEyi7>_uj4sRvv&HpN@>p|i>e^~S zavZW-i$qM$8rC<|vs5FqQOoYD*nn!+B3ISOzAv>(xOol%wk{htdxO?hYceI9ZO+zV z_pf&tGCMU5GgcPOm8tI5cR{TauFGB|bziE}JEP9(I8$!Vglfz98ojxFuPWw?NsH{M z)wYm1<}3kQTdga(E_t@$>8_Lk3ng;h@&-!kZJ;>F9*kxH^T*IXMkXZxu;mvs}V4jRlGs%NTP z$X~_1V`1Y7pzb1!Xkt9$z4R<>NSHar6mqZj7v|f z92}aQkeb;rL9MaG;i1VjYN#S3DKj}chiT0&Aob*ebDZfJ5?vO3wU+9y4=YTwl0(0;+8(ba=P)!9wM1hoL6eUlT@)8qOj zh7L*`+%F@kVT7v8BaBeJ)m753oEiO728X7rvotlPtFBL6MqG9_SA}|&HZSCmjm$Bt zIsR9#GbYPiuZ7w6lwIFEbB@-uM!k-64%%`K)gn#cJ}GLiA&Zr>g-qqyFLXZCv9Zs- z3UjQObEpU#eQ*=qvQze}Ya~a8IY)Up2X{HgcIqe*KIXGPFJ87|jtg@R*>WAR>BGYR z%{M9JJ&v4HU%een)t(VIG^|MvI8<1c9d8&RahTo`y>U}cxUVQeCenYBx zLE8k2-^`=xjXa}iJ@r?des9OHgsY48x}j~u+BS8!GyDS`ZSz_K@&wrmTZ&kUT8mkV zTS{1-x0JM$_6xCu>9?-_@sqo<8MmM2zS^qa+{pD~mAB5Qtopr;Tt8OzzD8iKtlwl) zpD(DlvMF=kbkmL1Q17ng`mq}7Ezn#)Rztlxnd`@DsP{f|{iu&rawR=Ky>@bbtcEKm zs7qGE`HviAsP{;Hk5aGWApO3~Ki}UepJ9~m^N*7NHI05#*iV17qDS?yihkUBEFzLs#qqGk%~w^N^v_(t`ah;M8rV|y99$f(|N@?AebM)k>sFOQaSf{e3e zTr1-){g$P=pLb zV;PN_W-cIOOSM7u?K{ahy{?%T%lJioGhddmnA-6A_7!C8)!57fWn94v#bQL>Uh&=z4v8DxIZjI#%rdAW>V z4KnjJ8B3;^xw4G$L(H5av}W4 zCF7lqW_~JT-8aqLLdMs&nt7UxN4J~#jEn)h%v@B)_Iu3yvW#!+GxJ&*FCH-SFEWO_ zZRT(plMb0VQ^xIw&HRpxSx3xldEXrCe`t=aWE^wM%rj*C=wmaVl`;PbGZ&Y!<4H5e z%DCurGq0EN(rGjQCS&=tW{#9`z?WtoCgaZYW`0-3KQEZs`i(ihc+ni)GLE}s=2dMF%2@E4nV*-j^N(hZlX1yUX5J{{74`A1_VBxmFWfM54H*ahVdfDs?!IN__hfva zJ_6R$+wYoVqkHD)m2tv-GtZIn#6vTmm(lgu%%x;}>4}*WWL&0R)%E;0%lN(e1X<^s zGFDO_zvx^`#=+_{Wu0Ggmv5NY%TIV`4rUsk&RT=lI z&#(3MAIex#{c8}NE6W(6N4sG(klb3vE;7c;m?GmS8K=njhKy@v+$rO`GMZ(W5%-@QuCo@rcUmu)y#usQw9r^hQ|vh~$j8cr|9EnPU={)G2I+5vI=> zjj;IibR$d`Vb8uV8>Y^D!}{pANY#7OeN)uUeV60n zgY<`?G7Gg7Mp%OSPAgFwhfER$VlrSpP8X%```UhhdD~7c^s*y zQHK%F{HWFB`zfpb*0-~o@n5&o*Xf^%>W^CO|Btt;rf&1k`_271B>C2+vtJYZIR1dmH$PHp|?3d`hNA#M)fE6@;%P=c=h^W`3|bf%3i7( zd_Q&7{OS|bsP9+*=n=CzXQx}oa~N_`F2EPuD@&7uBlVKdg_fb_0v0Gbc;4E z&415f&e)>P(wMJqMs4;byZPL#WE59>tI%H_M0@WX8D@JS>d(WOX>HQHM<3isP4lF= z)z~|&wfejL)B8`JMrR#NNO7lnR>!Z2Pl!(#u*mQ6xt4d{w${tm7_)_N3$#?5xGKcow4xSF~ zj@ff4Qm%@cLygqmd~@)qC93ZksFrAjZ;2XtYyWGBnm@BddMRAKrFc=6LO;eZPbIfr z2i^h8)qLuDEBGGeGIhDOH^le&^}4C)E#vFWHDfDu`N5Sj5z&$DBHI>kbNRv6*=OUT zTGnqF*|Jhg{pgHx(OF~szK=Wl;B@4*{yqG9oNNB)`-Sv+*6Z@hfk5<2~hJ zr4ejc#$0yIw{(4VVdXmyHiSOvdu8{l)jAmK()}zGGkR5;6!X@m&o-aUcj;(&NSpjK zEpv*iZ_05S{&NBiza3AKhIQ-s!uNUeoZ7MWyWMBvkB|IuU%qP(2c29H@~P8VeZ6;s zXM=mAZ#{1CZgg+-Z1P>!k7t8huQlyqy?3o|?dUDB*1O8L*7Vw3?OmR|He<@JXuZzdseUp+)^^~u5JHecXf;CaLShVQyf!FtWiSIq)x zVnQZ)$F@19OdZRma<=c*sGQ-R>7D7Bl|A=z%EQ)R)8tg|G|x2mbl-I+eRH4covNB? zzD7UdsqX&j8Ka*e+C)s*0j&pk6WioGBAy9jpSjQ1+@rmtJ!7)(Geq6zX}Ql=yrVp$ z+^_nsyXCu2eLt!0Xt^J4qsgBg%Z;gU`9Y;M>d#zvo3`yPKPW$LNc0B}ZbWoy>1nB+ z$G+)Pe1^2J!M;m+85?H{8;~t5Df@OYzP0;KK@Nj;&q^}dLe7J>U?BdT&#=ZRhWn+#R-l#cv@E{XZG3o|87W#ju?| z?Hm2{b2|9!yzlq?wW-XDx5iED^4+7U`Z-;v<{vXWC1*r7nQGKEf}0pK>h%2aYVUco zjx2v=U9YA?i$1NgW!82_^2&KD>mJ(b+n?*_~kTy~Ko!@lJP-Y`Z#sZTx6u;n`P=*PmII3GNBriJpnRj(taT)=62GG2XGB zvF>rcYooI+rfN&0y<hv@`0gRYo8ifHXZpIBkaphI|9aI+@m8b)Z7*md_o9?H9V~=Y(Ie zkhjCaV|uLfJ~YO6->uGa-!mRQC}H{eYLNqdruAu_cjKqFdVh{AIpmKT1t*SA`laYQ zj^aZ{Ppy0L{LPRphh{G-7r1+F;DAQqPq#-{?p}UeYThS#yx)Jc_Q8pzQC}`x5P#s} z<=wTme-JYI#f~cz+LcV``EXr{!!L*S>yTBxaj}S2T`jF|oH}1^r@L#`2>0U&b15zVO$TGotQx9(|_xTi-A9Z}YTQ>+sX%0&iQ6Y+Nz5O`fc2K^@Qa zOa0(+KEEwHDy13WFHH4p{$SsvlXcSsm+i|zxK&%X_hr$(ihK- zy5Q)sWqRh8AM<^fZ^oQquYVXC({t+Z1G3Ew-!|Ll-RIfw-tX&TLiTwtKX|;GXV15C zytT`B?Wc0QwcWGBy~DfH*QxDOD?}Z|lt@+Aw*T}&wFv!edDHu*XN!A_+)s$_e)OwT z^et;1@10d6V=As!M?*K}Eot|u+J8six|QG4a*cP5d#&EfuVPQH=d@DoX;!&c`{uOD zyH>vj4axl)w9I!6a+Y|OxR-jD`Z~Q-CsQlP>(4^(BF`eXd9=WD`VH?w&qDVinZvX5 zeRj_?$1}%0*K6*1%BlHY%AW5`?<~(Ow|VRkon=0gXQ(5GnQrsg;h)Pp^_k_J?3wJI z;+^8_g4KL)WzTn__jS+f?n%CDqO;5`<=bbu%{|#a=lkrD#AwfG_ZY8vB%#+sp6vOK z^1kYM)%}{x*W54UKDPMhe1|`?yhGJqYnXSKuhZ)xFnhk~YVVaHd#~s$b8nF5P4}d` zGh`0WuHTZ+%y*DyklLFi`#QZIN@UOX+5MO)DLSiO&wkz{Pm;TT_EEvX+m<||v%cAW zQtcOxJ?*mie!Y|5&FuF2t-%?M`v-11(Oe(<9*^H@`Rk5zk^lJQu&Sl^R`1`qg7?PN zX4e`$9%UJo)VX2X={uV0eM;1(iG$Z{E#EfjZkeSET@8+$dV9j+=d=2y-`#OxtUf-_ z`-|em`aCRua`e2Si5v2C>U^w)-DSU*ujSw&t-AN`aQW(?zw7MV@W!-;14h&tF*h}} zq~n<0Uwk~Y?3$(R^WUh{X6>1u3%oqOSC8$fv z(|7m%UhR{q#aA}a`_)d-f_Hytb9z$E20)dvnsc>C=L{Z+z6U+>UK$e_y)1Z%x0i67vrHKKe|< z!lKdjf@@^jH2-j8eX*`aR3O9z)6n(W`M@4nxwPI+XV8`X2?PmTSCy!BGSLnZ&t ze`^2OS(d%FMYjvSUN)iPAAk1l@^;zEQ=@Nf3!Y=+pmw{ z#_ZEaa98%JGtiPp_O|{>ofX~at^Tyv`vLuDr+1fUmwUHQNleHt_b%`5cB}Os!FO)> zmF%mw`>y{;_ElTlTfJL7+kBn*T2fuTmYhtz>pM5xen`bXE zA?h5X?MLb!KFW3WxyE;UUWZq?S9w=^%srI8hjPBx;Y;#5yiA?hEO(nnLhK)wsw1Ig zawMdWTE_hAb$Frg9@wkRcl*v~vL8cmIkg6d-KmiKRdJSgwnrTw$s;lM7wntVI!w*I z9;bU}c+~lg@3t`^>NVWk`#-ElbKk>yoZz0Qj+o4SPtJOrEbDQsI$|1^eZ;iLx4&19 zOC3dV#MIK;>R;>8JYr%!j!;KTBcC~9(#JDPWIbkjefu7Hd~f>hAwwNSWy(=hOh}kF z>|g8AJl|nGCc6i#BPR1GNj+h2!A2A*B-9vwM#55rLh^erHWZdK^O{GSdOn77Q61$D=# zw=dY`eyV+s-mly{96Q@DVA$U9%F%!IzFGIi#pWA3yc#m(w;NkJ|1>4`wdAoe(_h|o zFLc@PZjs&6Zl0*C_bZ`$8-%=a_}s~i6ONBVQ}>+db$w{tx1%O)3LDxdv0Io?^_Fwg zUw-|HE^K}xxx}{oky~b5xc=dZe6us^PTACCa+!UvOlon~@=L|8+oSrrM%634t>~|{ z|7`h3(az)lFfL4J>Yf?C;eMO)nJzF|FXi9Z;u4ho-K~j%BL(&wHun<%;UxeGGcy zSyXrPWB=aG+n+bWtKKX==3t#WD~nWKyJBt4y|I*{2=Plos$??kbey?}0XPIE8OF}Odr00#F^__H91GP^ka{o0H;q0o z3sU$9+Q|`TJIP0$g?{4F-UZldAy?@lX{;sUDi@P zZ@qslp?M_25~}kk??BHW-|h81m|Hqf_Dub}{nU|2lJ8oMeENF(diuHh$vp&n%l_*z z#QCmc9s2gc9`n5ubI+vr@OOQC_!9C+x_i5OdboSY{g_8WyRJ-I;Oz8M@4x1MobDR* zaj)~6!UD_ezT`L-cqKTl%w`yyHjDw#C;3reRlivTl2E!j4JgoJ^6mbgKCHJ-(Go0?=KdgUbW?$$o_I!~q*6t|$L#yB)mRkmFncD1^%R4%+ zJAGhR)0&Q+`Z#9!pfhuhS6p$Ye#EkmMt}2{|J{v?rdBQb_WYI$M=tC7YuN4n-HROj z=74AA$%3o;wfo_%Q~Efj=ZfnmTU^RW`t$Z(Z||~OvxZL#J~sWG9w~b+%r0O*cWR6? zc-ZX=t!-ETe4|KsVPoSYeN4D*W8$K%R|5B)T=iDTnWx5NO&;0ueA~laJFMx_q0m>O zwR_J7^6C)nZtrdH>EN4&{gM%E z9*wk7XSQwK?R?h-``+Vg<87mwwsH>*y^a30Pip164yi5NExhWDzU;YcspaLl)Xdw= z6XlNbUDw<<_ok|8CQVGp3*Hz0rL>{%)+nv-Zs2X;c`e%r}pUAZR$^@LI&3Ue#hkEMUU?+*u`@+ zdei7en~%LTz5B>vt7jU)y^SKR)thj>k6dh)Ug`s({0@~;bANiIuJp6`zpMZ4nI+E! z_4%8hpS_d%_{`7Gaa@(w=hO!?er=1j)wi?RlhrlWpY*Mwi}&_bj!rt|u@6=sNBiY* z3{amW*=%L%^Yqdg6_2r+`U0WjxcUG6}v-I>9{{m{3{x;hScKwA4 z4*gqOD#|x;l~FO$uvL;+TE*&yt+K>YD%McHDOh4j6>A!{suG`9v6f-0Cb5Kywbd^h zl2}~DI)*JwVlfr#8n$qWMOCb)zOPu~b1Fuv#fp?%L}#^J)g>3!SuI!%$%S-QOIA~I zkj`q+YDo^%SuI;_$u6DM!qt)N)LAWEUC9M?R*P3pasi#y^3|7|U*+m*`5H*hr?XnV z7bOSitd_5#xg*I6xJGs!lc)$&D2R{yrN zS#`C1%_aM(Tth8i3&|Fp)$+BJtQh36*~(jwtL>lnl=f4>_gzwXH#^kjRu297sTSh3 z>o42z327sfijcMvMMyh|A|zU(2x%`-gmjQ7LOMzmA)O?Okj@fCNEe9+c}X%tx=Kb! zjAVp#lZ=q=k`dBFGD3PvM##&O5z*#7Ra-ykvwVNJdB>$p}f5jF7&P z5zHprpnXd$U~{Y5N3Awy(R z5t1fRgrrLpAsG@yNTx&)GE|}n875JL43{WEMo1JPBPAl_70C!0B^e>FN=C?Qk`Xdm zGD5~kM#xyn2pK0CA>$<@WP)UbOq7g}*Ciull4OKTmW+@ok`XdhGD4-n zAu}Z-WR_%v%$95l8Eh?}aO54XUT|zFrjSy4e=^6R~PTd?-TWW0Dc_kz|B?EEyr6NJhwU$p|?i86lraM#xFY z2>DDhLOz#_kW-Qoa#}J%&PYbc7m^WjRx(1)Nk+(*k`eNiWQ3fTjF7J-Bjkc)gnT2} z6mrnoL2duMFRP!CSKB_rf7$q0EQ86l4)Bjj(%2zeqIAx|ZnLcX(R zsO_IOME%o2+a;fnfChRWqW*)ArlY@U&}OmguYU7=U!~n5Q_D9E`jh3G1|4MirolX9 z`KH0VWcjAS0J413U_P>Z(_ntGeA8e7vV7BEK{DSo=%nDA23-_<(_kP4-!vFR!8Z*S zqTrhb3sdk-gGDI#rorbZ_@=?46nxWQF$%tEus8+ZG+2UyZyJ1_f^QluNx?S_mZIRB z21`@$O@n19_@=>N3chKuECt^*7(&4}4VI(en+D5MC?ExFHb0B?Z3QGif8UtRYB3cx z*GIDzEDp^}E2?a<>#q*QPhzviaL=+QD?F!>OvMpFOfx2SF$LIA)}}p1&X>;pr{80 zih5F@=w%8N^`bygECq^sQ=ll00!8r@C`zC}Q6CBvB~qZMF9nMFQJ^S^0!95PP&9x7 zMFS~NG>8I4$rLCWOkpZ&W3jeWKmzuvXlpBqCTUVB>c6ZiUs_SR#jd}))Tbze=|xc{ zSriQ=i=tslqBqVW_c znm~b~i4-V$odQLZC{Q$+0!33OP&AbSMbjuyG@SxPGbm6rlLAGvC{Q$;0!4EuP&AhU zMe`_3MMEss=?X}|Tk1^PmL`fG_|CH|4(&@TT4b^7ufFvuTFmsKXbD*qEhUShWn@vb zoGgk~kVVl-vM5?b7DcPcqG$~nMQbTgw2lHr>nTvQfdWMvDNwYD0!5oCQ1m7RindUo zXe$MZwo#yHI|Yh%P@rfh1&Vf2plCM*iuO>TXfFkd_EDf{KLv^oP@w1_g{kNbi}ecy zBw)2Zpk6474rxViSsdDzR`jmLuD?3jr|2-#i=y|)qUZ=&6unOtMIVqw(T8MFbd)TL zj*&&tM`Tg-F&RalP@w2I1&U5kpy*Qy6rH3%(PtDW`kVqqrzlW#ngT^k(N`2GI!}S3uPIP;fdWO}P@w2r3KU(WK+$&;rlNN&)?(^^{RJ%3`=Udl zsJ?zhyJT@_Us}=k7Q6oHZJ(lROfQOlAd8|O$)e~wSrq+57DYdkMbR&0QS>WW6#YgP zMK{PO`kewre^8+4CIyOaQK0BH1&Z!apy)0Iin1tBbdLf>e^Q|6J_U*%P@w1`1&aQn zK+z)#6g{Ru(ccs(dP0GsrxYkM{IbvT^ZP!JvQVJNkHS=R#bWKHfCN<3yPvC~C{pj3 ztbPvdODl5t+4Wbq`xND2dQp^@EQ$iiq9`9(6y+z2q5@=5RFEu+oMchtB8#FxGKzvI zP*jKlMTIF)RD=RW&rzVLC4tte2`ngT^` z3KV%LP~@dRQ5yQCG4kiXn@lZe&r^oh*uakWti=0!1%Vpr{uGief2H)SCiDaTF+u zr$A8x1&aDmpeT_7MSUqy)Q$XW zC`?7se%1&DB;c6d7qu5fyYHO5lPOR%g#txW zDNrZa7vnfzChXO@&DNr1;iZcAHLluyK zIr>E`QxrYW`=W(@4(&@TTIy$CSVPAu7CBBZ(sC2(~F`H$fD>&vM4%A7DdO%qUa;CDEgQziasHWqT^&ybb^ec zPbpAzk^)7aQK0B^3KX59K+$Om6rG_!(H9gbI!l3~a}+50k^)6vQK0BN1&Y3=K+y#X z6n#U1qHifsbddr@-%+6G5(SDbQ=sSyg{kPUpVhCbQdCQQ0gmlGQM6wF`=6_R4(&@T z`q9r`E>sj@1&Z!bpy*Eu6y2vl(E|z;J)}U*1NxtxS}0KDM}Z+2T`<8pXvKs9om;x z6kxUMU%lqr7v*DmQIwx7iVBcLQ9-gOa*{=ni!6!)$)YHTEQ$(|MNwfgii%L6=s5}$ z6{SE?F$xqFr$A8&3KTt0fufQWC@MvPqS6#7Dno&yU#1&Yd1pr||riYic` z=miQCRir>sB?=T(ra(~@3R6)Yt97OV60lBx0Gropp6S1!50a`{9om;x6mGTaU)|?Z z6v6bOD3UCSs*^=g4YDYzNft%5$fBq=SrpYFi=w(@QB;qNqWTmlYCwUa7b#HGkOD=G zC{Wax0!2+IP}GzHMa?Ks6h(oe<`gJuL4l%{6ewy%fuhzFC~{Mv$U}i5F9nL)P@t$S z1&Z2HpeUNcR1|8po>M>q&ges-Fj3^vN7wDG4(&@T>TI>^U;XG))P?Cq(Mx1e)RioX zV#uPX8(9=}CySyUWKqH2k|N})heDg}y$P@pJ{0!8T*D9WHP6?L>) zOVm_~y!ue6lPC(;q%y4z?Mo{fVYTaD9qLmwlIca!D`ZhLiY$s=C5xih$f9U8Srm;S zi=we)Q8bP$ipG;sG=Ty|6Dd&iIt7X*QJ`ot1&XFnplB)uil$MZXgURoW>BDLCIyOS zQJ`ox1&ZcSplB`yisn(EXg&ps7Eqw*4GI)3q(IRk3KT7-Fcl56T6-%X0jo5e;i71% zCbh)s(7v>y6;`|c)w4cDE16ytts;w})nrk$hAfKKl10%vvM5?l7DXG#qG%&o6m24- zXfp+h-lRa$777$?r9ja(3KVUpK+z5g6z!xy(Jl%U?WRD{9tsrgr9ja>3KZ?9K+ypT z6dj~M(OVQKdYb}8?@*xV5Cw|fr9jbP3RBTCt963{5-?FKS}uxa=|vM4%97Db~nzc9Th z`jsq-ej|&b8)Q-RJ6RO{K^8?f$)e~MSrpwSi=sPZ6y2pjQ5FS??opuVPYM*>r$EsI z3KTu0K+#_mD0)PJqQ?{{`kMkpPbg6IlmbPDO-|cUWT8Nj9|el66ezM$pvX>vB7X`L zIVez+hr(2J-D<6_fCMDz1L~hd(RzK_pV#KlzOce?C{R?K0!1Y#Q1miYy3RO249o*&N!JR#e?)U))p_)nIy2RFf=4iMGYxX)QAE_jVVyngaSoPDNxjm0!2|2C~8iDq81b=YDs~jRum{| zO@Sge1&TZrDDqOEs0{^*+ESpX9R-S_DNxj&0!1AtP}GsaR1{&e9#%jC#;a(H6h;1e z$JEK@(7v>yt~UGSC{Yx{^rEO6Srm0Ai=rN6QPh(xie4s*qF!WC6iXIGy~&~|j*Oys z3KS(!pr{W8iV`VM)RzK9{U}hBM1i9I6et=%fueyFC>lh8qGSpb4W>X*3I&Q%DNrpQM7?9iZ+r((I&De+DsNjZ<0mP7BY&qQlMxX1&X#)plAmLigr?|vM4%9 z7DbP-LS(k(~lX{uC&3P@pIe1&Z=gpeTR>MfoU9MZegrCEF@Rcl9gUucD~4enrb~ zcW7T)k;`sx7%hqdnO+nHkwsA=QQ3QplsG!{%uYd$3>wkCcw3}!8EA@^k((cf{w4z#e`}hu` zs5aA!qB>+zRF^D@>XAiJeX=NOKo&(Wl0{KNvM6dq7DbK8C~881qNWrmYDR&gC<+uc zr$A8)3KX@ZKv63S6t$*6k(&ZV9tsqBDNxjg0!3{pP}GhBMbQ)}YEOZp4iqTrNP(hG z6e#LUfub%HrlJ~l>m~&xU~(P>r=}>f>wVEnc8B(*6?M1Uk9QJ9J(yk;^(2d;m&u~2 z7g-d=l0{K(vM7opi=ue4C`urUqCR94B~qZMF9nMFQJ^S^0!95PP&9x7MFS~NG>8I4 z$rLCWOo5^l3KXSMplApMiqa@hlum)73vtWyiK4vvO#c?G?^@lrjSuIl>$Z6C{Q$=0!1?@P&AVQMYAYSG@AlNb0|T2?dIlQlMxV1&WqaplAgJidIsXie9x_YbqcCwPl10%bvMAb27DaE8MbQ?rDB4OEMcc@tXge82 zJ19`JlLAG%C{VPU0!4c$P_&lZJeF_wPK!KtUDNuBj!c?@zZXKzB1eDZ=LTg3Q$Lc!UF}p+i(u$7T z?Mu6hq7zIniasTaqLXA%^ch(ceNGldr^uq{G+7j#A&a6f$fD>h8AazPQ1m4QioT*i z(Rm6KeNBO)3lu2&h5|+3QlRJ}1&Y3-K+z=%6kVo3(G?05U8O+L_Y^3)MuDOqC{Xkx z1&Xdypy($G6#YzrqF*RXMIYO(M--3%^^2Vi+b5!EfhP5<-JyMHMSs}sS9^-0n@lf? zZjnXNZL%o3Ll#AM$)YHWEQ;=tMbV#RQFNayiXMVU3RBSyyVd_?rAUA7YWrOjx%Hv8)8C=sB_|DoPeb z#mJ(lI9U{xAd8~s$)czvSrnBbqo_0mipo%+D3}68Whqb;LV==k6eucBfuaf&D0+bc zMHMMfREYvbl_^kEg#txYDNt060!5(|C<>!MQ8)#PA}CN4Nr9s36ey}eVJZsrx3*D0 z0t)D(>mYygOg~ef_Sf`xXkS`UU4MIWoG7Zt^rEOfSrj!Oi=r3FqNpKR6g47?qQ+!V z)PyXGnvz9PGct;zC{Wa#0!1w-P}GtFMXe}M)S3cCZVD86C{X03Kv5eC6t$&5Q9BA0 zMN^=tJq3z7P@t$I1&TURpr|tiin>ss=p_mib)`U2427wvw!d|*0uoSOzlhZlMOpek zgmm+FXkS{<%l`H~38JVM(~F{5vMB0J7DaJnQ4~)WMG0h4)Q2pJ63L>dFIg1zBcmvZ z0!95PP&9x7MFS~NG>8I4$rLCWOo5^l3KXSMplApMiqa@hlum)73Mno1T$)5xM|IvGVXC{Q$$0!6bZP&AtY zMRO=nG?xNJ^C(a>p8`b-C{XkU1&S6@plA^ViWXC#XbA<1mQtW-83l@#Q=n)C1&UTu zplB5ZidIvgXbpv_XpFzLbYG=thTa#A6-7JrN3(1F9om;xw9((*I7t+3VtP@unJkLl zB#WXgWKp!0EQ+>~MbUP$DB3|5MLWr&XcrkpyD3n#hXO@=DNwYJ0!8~NP;`I-MF%NR z^cDq*-ljm&I}|87M1i7rDNuBn0!8mppy&t%ir%L{(FYVL`j7%eM=4Nri~>a;QK0B! z3RBT~e`_BFBp^{AP;U@Lm-W8r6Mu*Hr4^m@w@(}(iauj{QS>=k6rCcAqSItibcQU7 zz95UDvt&_pjx374B#WZ2$S68bfugS|P;`L;Mc+`M=vxXDU8F$KcN8ePM1i8q6ezkv zfugGvDEgiPMb{`$^aBNoexyLrbqW;yM1i88DNyta1&V&9K+$g$D7rymDmvkBeNzDm zsG<+3KNUp{^=bd_{toR+E4uA(|8$Tjy2JFM=q_0lWsybEJ+dhJlPrqvlSR=3vM72; z7Da!NMbRTNiXKy-=x+)XJ)uC+QwkIr4moW{k%a<9eiSIOQlQ92fg(Eviu@^1t1&Z=fpeR2DiV9Gms2~N3oD?W>QJ^T0!c=tA-+D^{38=02MYlxJRef|F zIJXsW#B#WX_WKmR_EQ-pIMNu#rMP(^a z6heWbaug^kPl2Ke6exOu0!0-mP*jNmMU^Q~RD}XXRVh$ZjRHlX6etR#Kv6gaiXtdb z6iI=i>J%udL4l&06ey}ifuhiir9e>|3KX@aKv6pi6h%{@s67RWI#8gfBL#{&QJ|*py(wE6m_LQQ49r& zx>2C0I|Yh*P?(D9Ijo};kbp}n+Ukp<^Lk&@)8Wv*w4&Y)`|@;A6vy`&CgD6mxOo5`o6evoeKv60MiiS|2D2)O| z=@cl+pg>V31&W4JplBEciiT65Xaog{MpB^Y6$%uMqCnBB6exO)0!5=KP&9_ZRMg91 z{XhW;cwe8E#fqXC`sjMB!=Zg?MH3zNYnh_xb*2|ZlgOfIGFcQ&A&a7^WKlGYEQ+R+ zMbQkhD4IzYMYG5#noWVCITR?GOM#+!6eyZcfuaQzD0+heMGGlVw1@&liz!gFgaSoN zDNwYG0!7OyP_%*qMJp*#w2A^nt0_>lh5|)vDNwYI0!8a7Ohw}z);vR%qSY$eCWxW} z`W0=1!=Zg?MQ=Lnm4}O>Ele+pwvt8BHnJ$%P8LNw$f9T`SrqLei=y3RQM89FiuRIG zw2uNs`zcU#fC5DaDNytl1&ZFLK+!uCC^|%eqIW4!beIA~?@^%W2nCAXr$EsM6e#+T z0!2qDP;`s}MITY1=wk{LeL{hv;}j@5L18M|m6kVr4(N7d8`k4Ynzfhp)R|*vU zMuDOm6e#+g0!4pNpy(!rspvC@b-n@;uuLoZTohULzUY?2p?zsZSq}TYQKIM`(~F`% z$)e~!Srk1Wi=u~QQS=vC6g?t~qQ_)W^fy@)Jt3p$DFup*JaXEOA`1nI{3uXlr9hF5 z0!4NT6!}x2$U%XkJQOI(OM#*Q3KZp|Kv8}Q6cwOAQ9%k6IVn)&qCim~1&V?wP*jKl zMTIF$MRy$5ZxoP#OZrUzt|;oNNfpWC(7v>y;(6?kUK2$nm|he;PZmWb$)czfSrnBf zi=r}QQ4~xTMP0% zDNqzffue8<6h%;=D3St2)hSR^g91f0DNt040!6hcP*jHkMRh4qRFA?`R5Xt@c(hVv z(f>%cSRV6Cf4qK0tDncAeQ8CF^4Ob>6-AAiUKBMUi=w7vQPhkqilWG(s5w~_wIGY4 zmSj=XiY$s+lTqZRK#}MFu=gh5QB>X9c6BGfiQ_05ET^&VG@*i5=9UY5fNn! zlT0!wD2mK8A~J(af})HH2m&GsDj<_M;DCsTh>C)Wiiq&9ReRkDujicaI{*3J_k92P zuaE1}-OpXUcGa%BYgcur(*a;nBLEiN4#1+u04!<(z@j?7PMXdo?bT0sl+5oWVJ^&Wo4{#P$OA2-tLBeZPoa$!L z>pB;;O-fY1)S`|_q0z(5qE6JCMLA@%s599t>OwY)x{}SJZe+8lJJ~FHfNU1^Ae%)! z$yn42fJMClSkwoAMGpe7s4oDE`T?-0KLCpc0I=vG02VzAz@mWwEE)vBqDKH&^e6y} z1_Q9@F#r}l4#1)z04#a}fJH+ASTqcPMZ*EkqV`F_DsJ|-pLQ6|0$|a* z04&-Kz@j|>XVJ2xU=$%x_o+9FJ|LS#ACk?Y zkH}`xL9$u&G1)BoglralN;Zo=Bb!Bs$XN6_0E-R-u;>c_799a#(U$-$Itsv|uK-wd z41h&n1F+~g0E@l>V9^Nx7JUoAqVE7$^gRHJP6Dv#2LKlR2*9FK04zEUz@nc3SoAZ% zS+qYX__zonKSdL9-ZP6@>W7VfNlH||)S};$Lh~n>MQ5oui~b;+Md!$7(Vt|q=sejh z`ipE9T_Br97s+Okmu#=w&7uGqi{b!S6a-*VJOGPA04z!XU{N9fi;@6XlnlV4FaV2E z09cd?z@mHrEJ_1lQ3QZRQ2-Xj09cd`z@q#BEGhuNq6`2Q6$D^WA%L^!*QDTf5hT1^ zr=Q=@G>MOTu|qD-<`RGe%Ul^~l%SCP%4l4P^! zYO+~$4H=8B1z=Gr02W;bz@qB`Sabsbi%J8qs0;v$$^x(`3xGxC09cd_z@qX1EUEy& zqKW`4sszBI$^b075r9Qi09aHNfJHX}u;^w07F7c{i;5-(!%vDuU+OFU%aYwI{S5yF zTXLfMr54pr4&CsSSyYF5v#2iFEUHH~i|Uijq6TEM=oYeB)R1fz-AXo#ZX=sTjmTJZ zI{=Fs1F)zG0E_MbU{O;57BvH4QF8zm-3h>=762@|3xGu}0a$c50E=1yu;?BD7PSUo z(Y*jHY6HNc`v6#UKLCr`0iRzbH)Hyly z;L~PN7wXNTu4J>Q8`&)CPBx1kAe%)!$YxPbvRTxNY!>w1} z`U9|N004^~0$|a@04y2^z@k9_EP4chMUMioXfOba9s^*};{Yrg0>Gjt09Z5>fJMUq zSTr1fMI!)MG!lSCqX5pLPRYUPB1m|!&P6$9QI6au#g9%-RKL`s@yVg})6Aj?)SE>U z$!5_cvRU*b*({n&HjADjn?+N|X3^7RvuG;WESg5fqUiuEngPI~nE))B1;C=&04$mV zz@oVTEP4ijMe_hyG#`LP3jkQO5P(IC09f=a0E-p_uxJSYi=G2u(enT-S_;6T7XVoF zA^?k)0h~o+lY@sukZ^s8@#D;*yYyxM^5jJIOD$TR9Qtd9S@aV1X3@)JvuF+3ELux8 zi`J3NqF2af(R#93w1I3Ey-GHVHj=Su699`g1F+~d02XZlVA1OUEZPddqBj6o^dMY{l4^ezC4b_1|z4*-ky0 zgC%B)MStq8&?>WNkiJHHFF8^DQj0!J4%MA)7JWp$S#*$W7JW=Mi#{QnMW2$*qR+@? z(IK)~^f}oqI!rc;z93`K5dao_3BaPG04(|nfJMguSoAdji;e@Z=oPAV9}2NEII|iqSF8@`U!wVKLfDn7XTKW0btRu0B6zr$-%B7NcgyZ zO6>!)sI-1($ZyGs>X%w{E;%%Iu37Xa^=8p|vRU*O*(|z1Hj6Hj%_1*suiVX|0NE^x zBb!A*vRM>Q#-b1aixL1>lnB70BmfpA1F$Fzz@iiY7Nr8PC?5ce(g0W#0bo%SfJHF? z7NrBQC_ey;3IMPu1As*Z0a#QBfJKD?SX2anMMVM5qO-}tl_E%ZhTa$bVHSO@bJ1nt zMDuN;SpXJg0kEhX0E@B#SX3T>MHK*8R1tthl>k^&8GuDM0J0W&7uZmv*;GGS=5kh7TroVi*6&EMUBX2(d}fjs4>|rYC^`MI{;YJ6o5s|09e!< zfJJu#u&4z9i|ztoQA+?8-3`E^Rsbxz2Y^Mb0a$b|0E^lHu;@Mj7TpiPqP74mY6rlg z_5dvE0KlS-04(YRa2C}G2X7KV!um}`@pa9j7c}IA6V)%Zs9QL6@3Ur6ck0ce2gqho z53*U*lWZ3CBAZ3M$!1X>vRU*X*(~ZyHjDa^v8X=)iv|F&=pg_WJq*C2fdDKT1i+$4 z09f=W0E-3#u;?)W7CjEYq9Fh*dIEq&LjhPc41h($0a!EwfJGw#STqWNMWX>&GzNf0 zV*$>hF5%!4B1pKfPCs4EqF#DM8y8Mgzto~h;n2b*X3>+>n?;k!X3Sj$djMFp7l1|k09dpifJN^Cu;>5)i{1w~i(U!`Q- zwdk*KsNZt4=mPa-(M7UZJuA7R8gzq7d0EN+6p>iDWEF0$@=x z0E@x^EJ^`jQ7Qn7@&T|Y4S+=v02W07SQGSX3B* zMMVHuR1|d*zs5$_PY5=gPCIE|S z0kEhx0E_AXoJE-_!NVd*xRbu?SUknO(m$tjQQee8^-C?fB_(umwOQ1Vdb8+OvRQN+ z*(_>AHj8d2n?;SuW>FKeS#$^4ENV(Ni<*(Ks5tFuqS@a;; zEb2=(i~5nxqW)yFXaLzPdWeig4+F4hAOMR70kG&102Vz8z@otbEP4!pMUMlpXb1p{ zo&aFcPyiMU17Oi`02Yk^V9`hb7L5X6(P#h`jR9cMSO6A{17Oj302WOEIE%Wc1iOnM z;f?xZ{0GdUpxz`+Oi5I~)S{%7Jx;I0a&yIfJM&%u;_UJ z7A*x}(F*`9dJ%v{%K%uk9DqeD09dpVfJLhSShN~|MK1xIMNg&#SBoIwQaTq+Hj7s2 z747AeMDiWJ@sbM2C`Z7D%mXBNH&W$ky+77^?w*Xl5HUNv>0btP%02b{8V9_oB7QG9=qTK*2+5^C%y#OrQ z2f(8J04#bBfJFxYSoA&si#`Bg(T4ym`Uv1GTALF5O#}%KQE}FpMb-TmY$=KAms<2$ zN~q9Av*-}@X3^(lv*<9{Ec$|M79Am*MPHK5qN8N9=qs{Wbc}2keND!q;{YuB27pB; z09f=b0E@l@VA1ygEIJ9mq8|WQ^dkU^P64p!Gysc!0$|b404(|ifJJ8jSoA9Zi+%%O z(eD5(It##}KLA*C4uC~}0-Qykqy(#pAmN+!Euv4&qQ$Dz`IJQUOD*zJL-%bqivp?k zO5QArBb!A*vRM>QHj6@JvnYXV7A2C+q9n3eluR~@!elH;0bo%o0E_YguqX|HMG*iN zMFCh817J})0E_Yiu&4k4i!uOMR1kngg#cJo7=T4Z09aHMfJK)9u&5XSi!KLX(G>tJ zx)OjznE+?eg_Phh5hPq*KQVjJEGjR{;)|yys$Xi+)v2Lpx0prOP;VApOE!y2kFRyi^>78C>wx9d&ys44)9ZUSJ@%>XQ_2Ed}~04%Bjz@nM}EUE>-qS^o~ssq5Hx&SPy2f(8G0B6xv zslgp0NVvStMI}?+EB(FKeS#$^4ENV(N zi<*(mqUL0?=uWa()PjsfcLA`dB>;==24GPu02bW?z@pXwEV>tfMQs3BbRPhV?gwB| zTL2cd17J~m02XxsU{OZ^7Igw(Q4Ro$Is>q%3jm9{0&gK2MwMIn9H z@m8})zi=l0fz(9xOD*c18p_&c7WJXtEP9Y^7WE~YMg7QTQGc>oG=OXtJw!H(9wwVb z1IcF5ATky`0>Gk20a!E`fJKi1u;_6B77YPl(GvhH8VbOoVE`-|4#1)j04y2_z@kwA zEE)~KqA>t08VkUpaR4kD55S@c04$maz@kY2EP4{)Eb5sWY$1Y#Ki791dznS2G)zuS zRKL`ssi~m>Z<$5Ys5gtIlg*+TWV2`{*({nxHj8GH&7wJEvuG~aEP94)7R@7L(R=_F zEdXHALI4&m0$|az04!Pzz@jApEP4)rMb87UXej`TUI1XxivTQI2Ed}_04!Poz@n7^ zELsJ?qSXK_dI^94FHSQ0-QxtQiHQaknkpbrT?^9RKtJ4mYS%3sYS1*hBm!p z7Hy>7EZRgii#C(ZqSwe~(H62<^g7ur+DbNy-XNPrZ<5WTZDcIk4#1+f09f=k0E^xM zV9^c$7VQLJ(JlZMy$isi-2g1w1Hhua04&-Ez@q&CEP4-sMF#*_^gaNKJ^*0RhX5@4 z2!KTg0a)}g0E<2WIE&V&29Jm!;hj4DY%q(ikY(|orY5RiYSH1;P+*r?^ab^1(Gjv) z^d;FWI!ZQ+z9O4N$H->U*JQKkIN2=vhHMs{AY;+D04(|rfJNT}u;?TJi+%uL(T@Nu zIt9R@(*P{`34ldE1F+~902ZAAV9~DtEcy+AMZW{E=qvz>{s3UnIRF;@3BaQB04(|o zfJGMo&Z0x9!D~d2aE^ZN`g5~rmd-^NQxnxMwJ4Y`bjxnDC_djmzS0ko&7uUdS(HdN zi;~D@Q8L*q3X{#E6tY>AN;Zq~k+CQZfJG4i7DWMA6a!#UIsl9E1F)z70E;pJSX2;z zMTG!ZR2YCoMF3b-6o5sS0kEhT0E;dMV9^x-EV>eaMVSCBDh|M+5&$f^3g9dXFhFH!wci%R7SP26i1T}QpmMc0$fq8rF&QE9SSREBI8l_i@+ zS!A=Q9N8?&CYwd&$yihYfJGGnSX2psMU??qbRz(ZssOO4DgcXa0$|b204%Boz@q8^ zEUE#(qM86Kss+HJ+5jx71HhuX04%Bpz@qv9ENTG2qFVr1)DYk-x+Y)nWf3HNor-g< zS+rO$Z@1=4RKL`s#`!|;?>CE@P;VC9K{kt;lFg!KWV5I_*(|z~Y!Oz7PSIk(LDexY7M}mdjVL~27pEP0kG(P02Z|cU{N~&7PSXpQ3n7Pbp&8hCjb`Z z0I;Yt0E@Z+u&65li@E`@s5=0Q9spob4*(YR1UQQt3oUmms&I zqSwi0(N?lq^aj~1dXsDxZ6ljS+sS6pTV%87Z88?U1Hhsk04&-Gz@l9MEP5A!MY{o5 zv~V*nO?0>GkA0a)}I z0E-R*oJAY+1$T)c;Su^{{7q(2t5gY}=Sx(-)S@r*g}(p9EILZPS@adzEILLui@qkC zMaRiz(KlqX=mgm;`j%`KeMdHnz9(bRNdOl80KlRj0a$bjfJLVPSo9MBi+%=R(Jufj zIs?F>UjbP38vu)b2Vl`z02ciLz@l>iEcz3GMdtxn^cMh&E&#CTA^?lLG<#u=MFD`b z=!<;8=%-@Q5uJ;Um_=jtiWZlasD7zM32CA1LuOGT^=45L*(^#Xn?+%=S(HLHi&DvE zQ9iO+ltwm-B4o2DO2(oX0E^NASd<@tMFjv@lmWn^f&eTk1i+%g04yp3z@nl6EV>MU zMa2MEbU6Tvt^i=sl>jWt1Yl8d02Y-1V9`|oEGh}WqN@Q|bPd2+6rUDsDT0K**PrQ! z(%dV3xuD4lwzNd`OD(z~E%fkVv#2!nW>FckSyYy67G;smqH<)jD4T2+l_#4;706~$ zMY35`iHt>+0a$b+0E?;su&62ki*5p7(aiuXss_NK>HsXN0l=b~04%Bnz@pj!EUE** zqPhSqst3TL`T#6y0KlSK09e!zfJL_gu;?}b7BvDmi>^xx&J{tzSL#ndt~ZMw*SYBS zv_$nwEozz;dhLi=)Qozws5#jzx|3`cwIG{CcahDamSnT&Zn9a_ifk6$LpF_nMQs6C)DD0}?EzTS0f0pv0a(-tfJHd~Eb0uvqAma|>I%T3ZU8Lm z4#1)Z09e!mfJHq4Skw!EMZE!7)Cb@!YLXT_DuRTc(9d1pVHRyyr5;R6RKL`s0coM& zS7y;e)SE>Qlg*-mWV2`x*(`d5Y!*FAHj4(6&7#N1X3^thvuFqzi=F^r(NF*u4Fh1& zZ~zvK0ASHb02Yk`V9{s*7L5U5(O3W$jRRoOcmNhn0ASHX02WOGV9}ERESe0!qNe~@ zGzEY~PXn-MDgcY70h~qs(t@Q#knp$q6OjI9QDeQko}QMdeyK&X(?Yj?Z5GX;-Yl9+ zHjADin?>`;X3>1IS+sy`7A+*3MT^L0(X(W;XfYX!mH@EmIRF+t55S_O04#a|fJH9? zuxJ?oij7A_0f0rX z0E-7JUf7qK^PrbP#|=9|N%H695){3c#Yz09bSgfJL7Ju;?%Vi@pFji(X3$ zt`$MT?e*?@i&=E7h9hZ->X%w{EG_imw`S4T)SE@e$!5_vWV7f5*(~~&Y!-b-HjBO| zn?)zdX3-C1v*<@M7M%iM(P;n{{RF_Gp8;6(3jmAG0I=v+02ciQz@py)SacSEMSlRW z=o|ox{sdsrc>osu1;C;U04%x)z#=bVFWa#w0KlR+02T!SSQHO%79C9so)baBaVpMN zX3<&=p-7_or4}VeLYJL1i^9~KMJZ&nD3xp$J1J z78L+sQ3e2u3IedG5CDq`1F)zF0E>zOu;?-X78L_v(d7Uvx&nYjR|2po6M#j<0a#Q5 zfJIjUu&5*ei>?M>(KP@px)y*%r2trT9l%+X7zx%ALBc2XCm=}?_e%eeeu2pKkwo=N zEh-xcwg1s9%A(#ZDn~YpvdLyqd9qnlfov94B%4K*$YxPxvRQN^*(|C;#-geKEV>DR zMK=Sms2Tu^sspg71^|m{0I1N-0RW3`0bo%>02bW} zz@pm#SkwrBMYjX6s4)PGngEIlH1P5>;*0bo&Q02XxtU{O~97Igz)QFj0qJpjO>9sn%r3BaOW04(Yaz@k0?EP4=t zMSTHS)DPe+Y8DCZ7D2*O^u6omX3>2*7xj-Ms$Xi+z)0wapUt8{)SE?*kjCIYZ%5&(;y1Ypr*02Vz3z@jMtEP5J%MNkNdY+6$O95E)0sxC%1YprJ02VC=V9^Qy7Oeze(JBBItp;GxO8_i- z8GuD=09dpZfJN&7So8`2i`E0MXafL?UIk#$MgSIV0$|Z*02aLla2Cyp1Y3z9;fgvJ z%{7bm>RXUoB8lpkTJ&ZlH0XD;XdCrr(RQ*~^cLAHdYfz(y+byOc96}Yon*6U7uhU& zmuwd8CS%ba02b{9V9`DR7VQUM(R%s<6z zBvJiRi@u43UjM@^Izhcz^ex#e`i^WCeNQ%vPLj={AIN6Wk7Tpx6xl2~O*V^uB4g3d z04(|ifJJ8jSoA9Zi+%%O(eD5(It##}KLA*C4uC~}0j0E_+tV9^Bt7F`5jkr%a> z?N}55U{M?Zi-G_wiU(j(2!KTi04z!bIE%iH1doXz;j?;0J8l+j)43=qny7xMMXAwH z=)75!k9xBxjcgW0$YxQLY!=1HW>GrXEXq$diwcmtJx)OjznE)&*4#1)k04%x+fJG$%SadZ2i>?7+(X{|9Dh0rz z>i}4EJphYt0ANvRfU_tZ4PGyTgiEV9DN*-I|69Ghm5C;*UuscyG}P#VSyY~Sv#0{u zEUHL0iz<=LqRM2m=tiTQ6B&nJqW;}z5p!h2f(8K04y2+z@mo$&Y~94 z;430XI9`8rc9&UntG?2IIGU(_sYQ=QLkHu`qQTUgMURoqqQ}W*(Gap(^aR-~8cH^c zhLO#p;bgOD1lcSaNyeg404y2}z@jk#EE)^IqHzE$8V|st2>>jb2*9FA04#bEfJKu5 zSo9PCi>3gu=xG2JO$A`lGyoP&2Vl_*02a*zV9_i97R?4=(HwxYXizkGUIYoR)i)X+ zF^lTyTr@YDsD7zM3!fy-3EQWdJN%4#1)n04!Pwz@k+EELsh~qL%XQV4S+>k09f=o0E@N)oJI4Z!8#&HxP?wX^Ub2Le!l39 zXrlV17QGb>bxbsi-lpCxdWUQl?I4>)JIQ9zF0xtlF4-*FO*V`6kjP0E@l?V9_xE7JUtH7Hx|L$A}=|$8|2+ZWis)yX)i8MD{s3UnIRF;@3BaQB04(|ofJGMoSacD9MPAHawqsEMfJJctED8d!C?0@CApjO7 z0I(<#fJI3FEJ_AoQ5fJXIuQ--6+yziCB}bi7OnDMu*DM9FSRHV3!O?ai=xz-$ND*;%P z3BaP_04yp2z@n=FSX2^#MOOo`=o$bPT?@dXQUENv4uD111F+}@02Y-7U{M(W7L^5H zQ5L{ilrI)6kSZ1p(2rWD#oR0XH+3#57fV#X)S`;9P^C1ps1o&NQDw4ObR*d;szNr4 zs*=s3o5*I-&1AEv8rdwWPBx2bkg=#H0E=n?u&6cwi|PQds4f7D>H)B*J^+gv0I=v5 z02Va_V9~7rEV>PVMU4PhbUOfx8UwJX2>^@k0ANv502Va^U{P}b7TpQJq80#WQTbS~ zwFnY!ueU-K%%b=7W&d5VMDNmuwcbA)7__kH5n7Igw(Q4Ro$Is>q%3jm9{08*7WDvNQBMFC^#Wi~ zZvYnc0btRC04(YYz@mNtEb0%yq5%LbdI*3;4+F4hAOMR70h~p5$ASw)knjcl2}mom zsFq&Q9*HHYUux0gvCtdoX3-Gp&7vpBX3&(MYmcG>U8%jV7B# zW5`%E7JxdO|C!0k}$!5_DWV7f+vRSl@Y!)pin?)Jd#F9ERVWdIhf0btQu02ZwSV9_f8ELso1q748ndKG|08v$6f34leL0a)}J0E@N& zu;_IF7HtJ!(Hj6PdJ}*}+W^j@g|T315hOfW-*sGM7FE)@XnQPC{Zfl|#6pb=nMFIP zH;Zm z#{pRM4FHQy0Gvf{$AW!DkZ?Wy<)L@XqI0q={@Ylh`lS~A5DPtB#4P%edb8*h*(^Fu zHj92Dn?*m9&7xn(X3-h4S@bK}Ec%UX7X41fqO$-j`U8MP=KxsrCjg7i1F+~X02W;U zV9`YY7J2FRvK@;804$0FU{Mf&MezVE3IVVv0f0q`04z!ZU{Nvvi^2dbN&#R|DgcY} z0h~qO$ATL~knlq~7o9YV-qy=oT6&`Tr52^9hd#N?EXq&4SyX^*7G;plqJm_zs1VsK zDoi$uijd8sqGYq^GO}4zjEqH>1F+}{02W;dz@kh578M6zQ3(JRT?N3Rk^n5a8h}OD z0I=v<02Y-3V9|8|EV>?mMK=Jjs5AhJ$^fvaEC7qL09aHGfJNB=EGiFh7Ddy87etWo z&w3GyrMp-9t3;mo3h9aJms)gVdg#h4%%UpPn?+U0X32BSyYW|7F8#kMK#D~ zQBAU0REumD)h1(69RL>91z=G<02b8;U{M1A7Tp5CqJ{u0x)p#$w*j!I5de#B2VhZS z02Va?V9^}_ENTkCqGkXrY7W4nI{{eK0)Rz#0kEhg0E_MhIEyN!2kVI-;Tu$(%4X3f zor_wfC#qj+QJeHoPNrFOAN6L@{baMKE!iw;M>dPvlg*+IWV5Iv*(~ZrHj8q|W>IG{ z7Igt&QC9#Kbpv2gcK{YW0KlRi04(YWz@lCNEb0xwqCNmDdJup`eF0e14}eAe0a!Eu zfJF}hu;^g`77YYo(I5a8Jp#a@M*&zg7~m{wogN$~f`rfMyN>soMW^)g_E>tN`lS{P zO%E+AVHORe-YgnUHj74(&7zTHvuG6AEE-KVi^h=6qOoMNXdKxr8c)We2>>jb2*9FA z04#bEfJKu5So9PCi>3gu=xG2JO$A`lGyoP&2Vl_*02a*zV9_i97R?4=(HsC4%>`i5 zGXN}_2f(8F04!Pnz@mi!XVH-K;C>M#d|YDu6Ii5SQF@~K<)wLX@mD2Zc1^&GJTE`8 z^&1GNY8|)r)+7z2`NI zTvf*NZjW@!^1P;zRoR}`BJyhm&ubOAxw7ZAi43jcdF>+a+~j$kBKfL&Uf0N-H9fCK zWL9m@>l68+uIKfST;0I)21Xue=y`)9FWu&OPegvd-Sb97s^8&xVZ+Xz2_~Btm)`^%Oii}c;4zr&90ue zHZroi=WU3*+r#rVM`H4Gq^*&=AN0KKk!SjO-j2vu13YhcB#&Eo_8kl^(4$ z(S=LoI0T~l*X&CMqWb5^O9i6(_oPb)qWTAc%LStP7hNj`qWUK}s|2F@Hx;V|qWVYi zY6YVDSIz1LqWWj48U~{JcZF^bM8DlC$0QKdzwFT>5Y<1;&?*qs@78YX&3a5s2!y9E}J> zUppd4C=k`}8JQ4>>K8>!4n*}g{ig<^`m5SA15y25+qr?L{<7qPKvaL*ZE+x~zpk`2 z5Y^u|SssY$FAS^>MD-KjYXedJ$nJ(fR6ldMIS|zk&20@t^;1vV15y3h%8o!(KX&jzA82cHjku{-p={l)H-OTSspra%Qbjb!f@k%x0v-xBcheRc*=7(sAG>7xJekNx0b$s?bF3 zw1~25_Uv{63Dqs!tew`dkfEK{w9r{Mq?QXAr6lMk7rQp#6$~^DrB3Vzu_! zo8^y{ZYG^epMUNdI^$8l&!5jeS4R2_rQZG6jO)CNrBZTGN=CSnV0dYqm$BW}GlzZ_ z_mhKMNQ89j`PkNTkmZNBXO)okgi`msAb&0}&^#eF`lYYml0nFNM)tqIl$Y_Ht>+}` z*)8iSAp1?n6D(!>;P%u>vYujs{qdBQ2fA^^-SS}gv=ogJsDr%4!MFiB!nlXz|IOnb zmjB-wC-X(dNAj#=@~lVcy2tKm{wBuO&6se9zlleue822*fA>DS>D`Hsc^Pd)DXm#W z&DC|6)be-V?;E%L?heU?3oFX`H3z0menM)xN{w#KQED0t9MILTnYw1-w#WQko)i2r zM|VZ+k2y;ldKnv~L`VGxCB?E%$*A8H?2me{by?{;+bgl-?JN3SPJHU+VMF{bht*sw zvdG@8Q|Yq;UdCZ5`ANFG)s@60jgdWW-3+FihD(y#_}vWul|lfTXt zoxBX$z1{`sW-{F@^)k*|H`^Uch@C$8@kXhZgFUG0^d^2cflizH`8(yz(HGts>}3>| zQ$R=f8LK{?AcwM0reJ@BrR9O{w1U^$2#ZFa%ksN?rO~MxewTkvd`lk409V&N(A>+Y zCKWos>s>`$(sD1Oq4m<%v4q$QQ$HLw&>!L9a|=FF-4kMCM~s^9JgnQRVlywJi4^G& z`_a*EFQc_}^n7kd)5gvo>~GKaqvGYzNk11ZezHRPmJO?;zp3}0|R!fPFF->0C$czw| zwBO6vY~9p#EFrdZ&AQjbDmkTBy*lTD8{_vc>>VvfM7FI~lgB%H8E;CFj`40fIxUCM zIvVa+D7AXRj$Z!uESdMcoEXjH2KncXTxBzElY3$v+iaferkUn~{juFI5A^VT%tn2< z@zg=L<2N4}e@Gt5+_mQ1(kuPZEqHFBndFoKA>MJazg-HxYdK#-8(1)LmwO-2rnbayy`}V1EZZE)TTRgDfu)`s5yeXSQ9o zH_;z{`P1vK_P1m72WQtm>Saup5*_|YSK@}h+}0B;^AE#c%X+rjdTO$Kcx(CaqkoN9 zJ?1?(pD%9ohYmQDS~jcIyq&n8-FSaJoyK>n=VcU=5|wo`>zOInAN@1I+RrKad1%PED*k>cv?)<0 z8rjz)M=yF;_jM@s!5=H6c^T!TL|u)S2|}a~hBrt*)vTW?4u(==-D~LlkPv%z(T-`N zx^%Sck2kkF=?@(|Rl>{AKbNk@><(%!t}G{GY$w=1W<9LW@osrSY}fipFY1{jm)S4Q zU#r<9b4dD`XZ>83Wyk(Z$(n`ze(o#NrI|m(KX!h1T6Vtdt0u)d zwh{5AM2A?Ol5)4)Ekk@$us_7T)@3i2k0@FHc7M0+`1tiL{4Z{CufFwe zFXM=m=n#jyl3+MfPOy{K&jtr&93Ngh>CW#9@9+Og&+mlT_fKyd<2G)|hmCIXGR{bm z4ss7Y)smh(xl2+Z0&*zi=qAJtPkwEvztdxLC$4s9-+OD0O>;)n{iVeaF-vN6l!aYQ zDD|q?Pcq7qg8fmJvp(-)d7n4W%RPt4v31|M4|L-~sp-u>=;9xN-IMo!At!VlsnKC} zcQwIqJ=wS>*3mpRZrzi=O>n~;H*Lu@xd2E{eZ8z}{QVWTY?a)`w3HehKr!#wNRK(TSZ4ba#okzs{H^^Wjt}(qUet=(|qIGR(Px{b4S( zPOE2|9|M-jpCQ&^zIkHVCU*=*zp~E*{(^r;eE4s?9jJ!yX>BP45a5V%uh{oiNDD2uqEQa}FJOGR}h5(LOdQwscoL zzn@!&;YG@h_Z?ww_fgS)n< z?jOn;=LZM;O*^@5{A@V_eWgUlID~%2NI#1O`uBhiCd5u0zxc7+S&NpJY%CqQ3uP#^ z?$VLHyh2Om`6&%$FR!%?_<_P-zBoQfZ3?AccBYHm9*G3|ex0&gMpi<35IoIK5zYuv3_D-Z2P6Bziqd)?xvGXC^e-)uLu228@XWWQaKId<&}%>ooDDr zC+4U?J)hrmP;Le{%w6j4lx`d}rH|jy`0Cx=7}tL{d!49sjnwEEPuRLs-Nam0us_C| ztj}xZm)HF{;>4UYvvtQM#O5q~>4-ah-uYqVQ+gXGH$XEd>b-hHsnTIqb5+5x&dn{X zt3GtKZTzMk?ieiIo?qv9d3AMg<`|iQWPja%@5(-M(=RnT&XIJalXF+=Xd@l{_2e_# z(8lf>z@C7$CHnUpHijc>`7O8MsKyQ7P3j>ip;;+-}UQ0Tl0qN>G)HB zozj^rlsbP zT>RlzB1WoI={WDAE4>aCwywrH7)mXf`RpzJHg)RI=6=7U(=*n7?hKnaZL?l8%1Vun za{)E(I#gM(Kh8SV=V3PQ?YB4oAU(+DjecQ`e-|v0Y?%3{e{qW~So_RGq!Db<29M2H%pO@vZN~thINwOFHk4xyB!Rr{`gxv_u^_) z@s8I@N1@dCnerWeI>@2(M=g+hu+?dNGuCC%sx}#{JT$td-{p?{`P^CZ>G3J2RqasfkuM5g?qwuI+)mAMC2nR< z7pR-o$-#u!ijQ9USgORGkz*$f)myAksyC=^bARJr-@f~K*|?%oq&syGJ#COV?;7iA z1wH-#<+PdZ@bqh%Cc9S-&xK`2XSw;Q`vb{W%6*m8=qR_lnvl)yw+Z$~+0y!qyU7mu zk;7kose3&k_Um64hPeyasso$d)(x9_=vg^bU8P9nDddXW)ZX8EYUH5o`L>Vi6)Yik z^5B7u?iBfJ`}WV&>`>~Vde6&i{lQYB!)!-KI<=3nj-IBYzNdCo@pt^dd$Q$Jkx{<% z{rWFu)1;rFttQAxyI4welrK`^Cidlm{ZVePE>F1Satw~_nJDL~_)%u<&HCaxA$Df! z{0(|AWu7{J;JBQ1`=v-n`4=0fw`zy1r*b!&759|&Zty!Q`%owMM#RR^&urIuO0HkW zA8ITwaHT{CS>Kfe!#b~@6{si3AO~fOW^MmO=cZ6fLCHe$?`>zoHw#xAWTwV~8qDUkM{>iR(aSoT?V#Kf zpV+6{xuVS5@`6w{ZpWg<{)?uB*sRfCpVeteYIKyr>i&)i>NoggY_^W7I2cOZnRBz; zK+4|wdi-C{x$EB3Zy$bAwpWI^{+A=uWun|JMLNvJ^wdIn+HXA#p{InWTk2bhq0|A* zuPp74vS_o~@|J?^_I}H|-zcyBq(TQdor*86Eh>XNBiJ9L7jtsF$MS<-mNWFS9v5!& zdrW9oPwr;q?arA$Eza>W(xpO&c$^JuB^!2ybyKv42~lxv*&6;3UwHf6TqnehKhMwb zM|f(@6We89T_ZI*!Yo%43=fo!%3DVr=%`HncW&}W_~OxI?I$62@!j`+aFf>8-^fqC zGMY#^|L zd%cVcQlo=>mu;IV+ZN96I=aY;4kx}9^ZQx3==@|krDWsYdF}JJ^*Dx7-{}|aA$v<| zbdUvVnh-iQUtt|JbTA>d^3`wj%?~+_s~fG$^gDWX)i2NJl~b-3neB^t88=CdjvImvr=)%*S1{>v|3~t-&~@AP{Po-neK8kGZS-j0>%EM2Qlf)g&9-fp zZR=tE9B12pdS=^vx3|`<+Iv#wJn8A@cTX&LC*{X4EI1)|Y5k>2hxsR69g?n|u&&D0 z^2eSKn{f2vF`ao5VyjQD`O@vMKfYPF$!*k`rv}Saajq2UIB#)9+;uM&?2mJ`bvm5o zn?eWWb*1zg?${$VSEwLWdMZ%c+)sR=ja&d_&v&iIrxK}E> zSj|VanguK$^69w*e>Km1^426h&l6%BkDOlXuG>5Jot-MLi%&?A%CXKBxtA(utf%iC zl>PC+rme;zI^@+K!xsHCDp5ZR#pFH){ z7&SH__T<(><7MBEk|G^u1y>{&M*q#ENrL@h&bCe;q|-_Bhc9-+T(NKZHa!fo7ZjcB)Nk-KTSA>~W?0bU=e&>hr*3O7*< z6zuPy5!T~mHfPL}FVAszs;AEXUcvA3_`u3egIgC4?kVq6N{Q~CXI+U-6AP@DgYq_aP$??<0d!Q}irk-hb1IX|UF_s;jOCN3#c_Pq6TWdqwepFDd&-|&{5 zb8g{$`6;R#tviRj6ZH4;=2yR2C9it-N{x=Nva1QDx+&@-!Tt!3TA%$`{@s-RW&AFa z)7#0oWPcAGH~u%Bq~&dd?L$w>k^5O{bcmx}jXy<_Y*b$U0;3+7s`14~M>t?=V39)lOj{Maf$G2KeXzlN;r5FF$DH|zcyz92@ zcX)+6NR1vx8B1JJSI;ZbFeIOAk^e$*!Gt0^<%h-kU+C&!xJa5%{V(LnlA=QOzt9yD z+6mSFLO}`rWdhXyLYGUBo<039R9Hf1d7%G=iUkwAKrC=|TK<$^+GS~X6^hBnYCJEl zq?eLXLy+eM3wpt{n^JC0shV=DTwddCiM$;is^lq2$R9{aaZdylo>7DH|&Db}S#?K0K6^q1y!na{ekXQfF|C~rF=`DE*K%~Ah> z?30*{#8#4CHc+z&8*y!sSRg&2R^b_Sis%~iSG;8N;tH*=Bm1PlrL35AoH2G-K=xgB zeyu1tZdkyJEBsU)If{j3fu{@Pvrarmj%Qh~W|3+|dZqd6l#P(jZN$aJ1>`Vz0c+)< zcUpd)9OsprudV(-Ho;4JVt`j{zCPaU@=(qCcAy>Jd07_pfEnSR=>U-v--B}*DeypIr<|;w z?K^hu*6aWHX7n4>@6tWdrE6C0zMTei>(#q%@4h)@a`(l+{(b#j;`T_>zP-E4KJS-x zXP@?cA80V3SKAgcmM%?u4CvRkdF{%LEB!ML(?jk1=jh(@Ja?cw59rmgLivhiJ9?r* z+fF&1+Yji`zit0PeRBGh?W%^!;p)__SAPj|Qrua$ep}hhj&*zY?Ag1QFp&>ox@p%A zd7*$zovLE6LLd~%{~!Ge1rmZ?0-^L^k+NCEONT;Nh0-q%g%Yw73WU-n%7gr&^egp2 zRwzB8Kd3Aix{$=|=^FP~jet)(pp=W4%F+EKFnI-4l z|NfckpR!q9s(1MpoUD0$|JP2H|At}94*aj4#K|>71ser3GegP2qIv?=@n^zNhC6=> z`X`O4A8}_$NjpRQD0Om%{D1jrxl=$^?iBFvZSK{Vj;gFbsvg#0p( zlnWIsEugrKSS}83TB-i;?t;JfDXWN+y;a0-rEhJee?MmF|Fc2`-7-Ju|74v$(d$;6 zPG;JcxfD{P6BA2HxaVDQ>GLSQnH7d~l8+14EgQ5%ySPnnC|D7rNISIou#^ZWj<&D8(GYlz#Waf<`_|M7_3 z@V{k4C?rz(FEQ-mE^}xj|6#$#p+Xfy1%r>sr9xHtAn_K_w6_eLi-0u2P|I1J8|1tA$$t<@A{rd^#dA(pYyksK!zx(We z^-hI5*7}ytKj%eO+|Gb>_HW-2`5)ud-`>gjXYZfCy}Szy>&0?(l)R>1(kE3Rn_070loTl>(VQy zQ>MJ7@2{?|ZC7>!dXWbVvwrS4vSnlZ=U0`dwQVca70S1DJ!H$uC}==$wXL^0u7|ez zg9HCZ4cQglC}n?0QKtbtdk*rNU$VH$KcuQ|oz`nbHnFyW8*?{Rc75(Pw&bkosZJX-kZj+wk{*!9wZCpJO;Gg*u zQu_gG-p}3qxut@wIM+o+mR%)xJG1k2M^Eg`&huY(k&O!@U{~57YpEU}jP7*^*t(Rm!ZYn|TS(b_LmaN8=K?ZnXXo zz#&wf&M^FRw)Gu+`@7HXO*VW4lHT&^1-feTwXU>nm@5 z&bCTDp|e!bcocneA**h1{Xaj^OEe zUU0}c;<-n;iVU=O?ujD$SS{BsowW=}4IPW1ZWqdG{RgrqSeDm?ze#!(XdypZw&znQ z$HOOjko`-dyAsyVt(GHTJ?3qJTnvnHv}Ioz$vvuaFx-JB!YwUuZ=Y?K2tczS1^L&td0a@6uYwy1Ob1%OfM0L$S{JBRy z_eMd^Ab%V5==i6U>=*ao5*hLiesa|rpDiZ4UN1Scc}G%K zZUf7fdmr~iIaBRH?x?fHDSO@}mxFApkmG9$-K2I)le;qOR;`+;pX(@_ovEMfC|9L? z#mrKDb9&^o@0W93W|^KH`wXbwQTABQz%o56R1na=>wumer0v|Jcl-WjQ(DZ8?e_I*2ctuCJvd8kU6o@IN=CrxhX)UVGCo%>{#>5^IIj`Eph z>D)7?U%&QUa?13`>D8rw*Xrd2xf`W2dekN9eBHlW?_Op4$wxG#?I)~L z`~K~7v)dJN3*jE*$(x;Luj=?8UE`dVmt2Q)-4l2HKJ#um)kakz@7^=-jx*Z{?wcah zwry745ptI2USxf#+qV73I{yOZ#b-APFEX#EnmG$=a zf!ryOyV$(@$GqFe?7aCAzjF_M?u}~h9cb>&<|QXm-szBcW5}`2yDiK;hHk?1ZmC=M zrp!`$>eTMrGqZlr4mq7V$^Co_K27DHO?*n~y8rmx(og5ehta%?@=t!IHaJZ_>Q_>s z{nHPR)k!NgJUk+KWYVa_(FtQhW8=pK$Hz?yc(tp_liKTNvb;c+JPcJS)3|Ko+P60G z5@LyslY`-;^!NgSj6k7a;Xsi<(ZFSaVu35-N(AJqBL2<4OHsV{)5S}l5Y!JPUGgtz zA9(`>^)pGA{0qwGk>nR%F8LSl$;Z*apYM`?K~H{N?vj7OzwOPSC!edl zAJhspLE&3S6}jc`F$&|!ryX(zvUKx%N_of`}{3G{PX}`SL(*W%&o%O5Jg7Wx4zop})Ma zwz6Elp2_F(Sy=yh2eiFPzK&14*H%9Us`amEEB$WKR_b;c|5RJqxZ{>jYAXlwtmOi7 z+G$-eZKbZ1w$fh}ZKbZB<=eECx|Wv5Xe)J-wUxTL#+Pd=bsH>i(N@=Ixk0?EYoe{x zwboYF*F)P9@`+koKEamHGyaOUSIHMDYAet0oFJ{Nzn8Ys&m-CjpP;Suv(%Qaw&j~` z`CePDU!bS;=WKa`d_9cT7uL3<98b%owUzC!V!4I3QrAXXS#MY4k7z4(qbyI-R_bP3 zennfU+oG-1?J|ByTd6x?`LwoDciwVgnFh2jQ(LJkt*vZl4Q-|FHp|VmmAd;a>tAKi zx|!Na-D2afXe)IWWIEA)667<^T9>Y^OJK`)X)FC4&{q06Z2Y9Q($87TUW#PtCskWne+g}+?s{#duCnoZ+Dcth%dNDP zx=xlK(N^k)X)AS;jL+3p>Xuqwt*z8;wtPTasryu0sXK1`jJ8sz7gpV_ByFXxfaUA8 zmAdlUN?i@(w`(hPtt_|GR_c0K9;U6-jnh`@rW;?Zt<0(pJAG zK=<=zZDqR-X)FC5(^mRBZ9GnPA>zpsmy`)mG}(8sDw0)O~FEh_+I9MqAl#{f%$k?s&Oy==PMQ2aIQlEEDTd7Ns%c$lwZKbZL<;vPhT@7ue?l$9Xw3WK9miuTc zb%QO>)K=;iXe)Kgjc?Ib>ULQ^psmy$wtPWbsY{TX46RGoR>z~Q%!f6!mE{d=d2?Id z!InR6%SYMrDYkr(E#G3x-?rrkZ22*5WxGyWKC7*4SG?Q@>H0IZmGzd=R<^66@dnyT zU31H=wUxTgmWOF8b>p;^y6MJOYAbacEx)O))K!z474=Mip-nxzU0Ydy4{fEN{@O}E zPZ*!9t@Jb3@*-`epOuz(X)ARHw3WKU#(&gS>dsmAm|Ps<9X7R7bl^V@hofQo09$K$@e4s zZ5?ZyT6>qZ9j)zd?Ss}1v37*DldXN$+Lz*7zpq*Qe!Rbw1I&!rJ4q12q3)ZE5jIb5(2m7Ib-twHsvL=<>I$y&#V@ zr(EXRdh%t|nwwcWPL7f08P@KX9jp0sYYWOT(tMS*ZNw$b-KD9%mm}6Tyu;(T3fWG%hy`lu9eF@t$nVw%WJGX*~aBRtS#Tx<(k$GZ13_&YqyB#x7z@>hj&zPVVmVGuD38!{x86E!NxR>#XhYpv%3jUE0s(b=Lkkz~w)!m0uO} zx2LwXk38b?Xlu6)c6pDr2}4}YZ|&_vUB1WKDZ^c!Z|%n;UH;nIE5^8dgSDN;x%{BD zFHUfIy|t$&x%`*4m7j9CuC;@oc6qF|Z%%W0pS4LdUCyw!$!wSJwRY-Umls<5={%Re zu{Lv|%Vn(X{H)9UtX;mum_;Q!WTf6=LVeBrzq$~qA-tX?r z?Cj14-QC@dbk7c5(%sz+(%ncmNJ$FPA*l$G(gLE0NC*gsAc*IA_Pzgp@bO*e9Igu= z?*H-*Bm9`zS#aIt>~lJOUpPC7&YIht-BjnC?ap4Q^ZHI_-_x0XkF)dW?6A+-eRXa+ z;OxCRpC5E~@FC|ce#AK|>l}W}*;90W{f)D~*BN=j*~xU){?6IWb{U8%o^|#E zof*G(c0Qe*E;_rv&MlXny^bIuaiozt&#9buKa=0kMxK>vaAc;_Sydvzq@t&c3~n&Td|357zmm`J|cl z?T2*!9pP+mq;r;ucFt-#$C?iS*zZ3}=Xdd)eN|`tM9xm5vq2JPx7E2MnX}jH{3V66 z|InE|wX=)p?2*>lLv`**@9ZNwQ)YH{Hl2Cx=?MxdtsP^}#6dyTb=FaDp|h*bK|06j z{8Z;sdz$N4>RhY7UFTt)XLMfIdC#8aex%CcoCS53)Y(Jl7@doBuF`o$=kGe*=98V< z+l$hfUS}1ZLv(J@d0Xe-I$h>diQDT7>x|JkRObwx$8=uTc}Hgw^MM|FeGZ*1boSA? zR_9kbkL!G`GfocY`U*N5=p3zcq0Y~AUe)&&3Drp_@s7wKH3^NP;j zb-K-`R*wC7)LBMnJ)K>2_SLyo=YE|}bb8DOnC#VP{v(BYDztnk8XOQ`nTlV^Jouzcv(K$}% zBAsV--qra;X9n|WTJ7x=)!A9+aGhIp?$-H8r^kF2Q+r*s&ayh|>ztr-iO%yn@9BK1 zGpqSTU-ouN>g=g=tj@hU&+Gg_XSDgOn)bR3IveWjrgMeP-8v8Je4#VKeBw!aeOaCL zbxzc|T<7OHf7JP0XLj=$9qsj{b@tXdQRgh3U+erqXWXLBb(wTF&^cM>Y@Nq-{;2ae zohi&`7_>ibUY%`q4$`?v=P{k9b-K)_*R$6p)mc?%OP!zUT(9#>o%eLU)tS$HW;=U3 zm2?i$IZEdaou_nO(iv_(8JxW?wa(f)+v{AYbF0q1Iv?wFo6nkNuP>&vy3XM`=jvRh z^SsWxI#Za>J!Y@ZtFyJvK{`k2+^O?Bok8XkbJ^<>>GbPtp|hjTMLNIGc~|Efo%zZ* zw^K!DEuEuv&ewTb=WU&d$~xEO)LBSpC!IreeyVe^&T~5N=zOEoQ_i`)qB^VUY^}44 z&gD9H=zOR%*nILL`}0v)XEmMmbxzc|ROk0Pf76-Dd{!WPeLC^Vvz>oh^IW zKlIb>I@f$yy4cSxqFXd~EGTzt^NBFpn!if>&X3xzSIe&EJC&_nEqBX4eR_3l)whqi z+5g{P%uh#9u=#3#4(%87A)fcXn4h}XFX_xb?e}vz^Mmha-)6sLF<-;X*Z;5YXYKs& zANSo)AY*^+>=$dze3&k%jQMK6OrH`QRMh+c=G}4gr@hWs`{PwHU%3zFn?VE2$03s$ z&wSxq6-;>d_Kwds|Ff)k&h6Qs1ACkH_Uf9iTw}f&G^3^Y{~)~+_@?=g&3oT3vUPCK zSM~yZ;rq2R``sUR*BbLVAWgIX9=7x2_BG$;8uLx_F{0q0wDueN!rOY9{qF5`SQ{Mc z-`<}2Fy?=^H{N`kYs@!;9+=y+zfbtW+eVx4?(GeD=k}t^+qi!V%(uD5-o|Tldxg!< zHD7q!924HXz47Mu?9Z#ce{sxLZf~{uw!OxBuwU{G4Gx+a>3rM%)4t7qH6IFj@B1B@ z5F8X^8ejN+2TZWv=1bg(#tXxo_Q$nf_L#5l-oNSZ{QD*_Z{z-*G~YIsdzd5kOBHi_ z#Tn-0$Fe8CSL~ZdoA1}dge2zMsm)h=d-mtu{+RsUFy9P%KH2;~g6uc+h1)YE-}`>c z%>Da;?_^HC-@Bhyr%>+hdCXt7EnGBj{-XH{r!{{WCvU!Y{#m$iLAwg&FPt~6`O?Do zNyVy__(V|lri0B#?zvsNE6j~u9_KM3Yfv)t$eHWj%Nl{F2m1zPDF5O>ufWq~J)WdX zQ1!=`U6vhv`LL$>nm1m+{4?#!R&itE+HVELtz!NeH;(_`zux|9zm|E?JAIiK`7+q= zl{V9lFAGjLUx$a)2(NBR-k4kFw@=)}W$f>w8I8RMH@+#~KW>E|gEw?fn(1wdBJuOI zoi@F9=Afd_YA){jHv7goy90Y-_W1W!vA0~~$?)hJ&of8virF1|A9ne7#~gim>((xF z4^keq-yt%0pE+x**NZ{f$6Z;r6dy@|ahxMa|i zD&x5Aaxc<$4pcI4+fvT{b6GL-&s(?hntwV!g1!Bq4EzX>tw&!51>1YMD6lwYv42TyEB|y<`uG{rw-}%H zb}Rd~2I*&+f4BFq{`9@8X9i}*%<|9r@9G5R>J9&0J?ew2C%$*}xWM?B@%{<_T^-k4 zefGbr`+RWqC+}T7)IT&ZEM{12EBAC%{`BVR8qdG$;oSFufk82Y{DWiPTI2ck9`@g7 zKwx0ZK>wiF)*yY84{pEDd$-@q-z(5NruTohpCR`4Z|e5D1-i#{_xI54KZ?Emu7Peb z-Td8k`xQR8{f_V5etUoWK!=zP|J{Dt*xP@i+ix9c6Vt}uR<|D%d;6^dtz%mI+vxUl zesKHE-n;!K{w9H@F-`xwedp&VOt;@4&@iTC|z;h=e0jARDbixbyqHTO+~% zs^l8kDcSL_1DR5_u>ZHY+nEzZ7hMr|#-n-5j}E@RbEy5_v(k5xY2DZbbrb)&w`b$?KaD+jEB*Zh z=gU4mk$lJ9U1O^J-tCV4bn(8o_XqZRl>XdrZP#rY+a%@g&@CJGFRxfI)5XH&TLm>8 z(x6z4^8H({J2P%>v+d1FMOWO>KmN?CCJm3W=%Zmm4vkoW92HM{;Yvq7pS zE0Zn0>`Pa9^5RD48|{C6uTk{8PrHo>c04yoKkS2FNyja}M+f)^8o7>JE8US8Prs6V z1ASxq`TOZtGFj}eWS>Bvn7;nLv8_S+b|2inhEUcI&SUlI}(%Y_B#bS#dP*} z*6pW{y?ygoJgml(Cz0k+=~lZyyBK5HKJvyshS}d~Z3As%+WFh*$8YPe^nW}KwTyi$ z_o11;d7ybri`d5RW*&zc2b#n*@jH^&rnR@1${N8QX_16p3i>d$L zZQGwe9;IppYRA;}*NJ`Gcd@r!D^San+Pdu|AKZ4e_ij7J9|#0us{VJ|_UDeru*!id zF;)Ej*tb22z3s|@%BEC_EjNCN`?EK${XJp-M=od47*` zTV_6t`sVv(&+PBl>ceja-CQ_yVD@;`&uvcfIP#B>RP|C%%#yBi!~I3-##^%}o~y*? z>jt)Lk$>j1nssaTyl;O$_xWjOlZdowW@N}eHu{H`<5rj6Q}B6`XLCDNX|TCP?Y&E; zckI9N&xh-J6-rjWWWI7w4^`X~*c-Fgzc2P@t3mp`{=NT)qMfmCMbY-a_Lv?19kK1h zXS4Mm{90~&@9NJ3>tojYH~e??`_E>JKDc_tdsiNXR~pE zapswLeC%6mJa?YW#sR|HMB$Fg#|&f4Besv)PcqkQnoPt=o5= z%?1Ys#|-fg(d~cuY}x<4+wWr@<@)MTj$hfJ|K3+9^uf<=m-nuI_c6>~ZGUAm{&#hz z53X+Y-qp@C;hK-NcJ7#Mp}L!R`Mq$Nt#o>)3nq;d5=zK+hQSerN1kYdnAVx%Q9P=i07;uI4?= zZtp$Ub_sNe>FV#Qf4?sNYX8Thr1M@TkCJWuvCrB6-3Kd@=h}DQ$8?@+TLoH~_c~ka z_CNfc_WpaFjm>+VP2PF0^WEp#ci-o9o@*PJ_c$B+8|t=GfADixH});u?^^!a=GoeL zuIA^C=i2Il8ZkBeHDkZO^ITi)X^WiI0@Y%w`>Vh6^HpJY&{tc}xpV&%(k#m)|DQR( zy>v5Azlr-w@H`ydDAC5VVTpej6FGfVtF&b{Z|Faz_tM1)g72;<5kF|*>BWQNth||U zL-Xx{c4uAVr&d^LpNBi%>GEpxhNgu-YVX?h@Wk3i%N~6*`P7M*H(bB|k|}yr(}72$)6;D+&X#9agAsEn>v4%PIHdOG(4ZHM4=G_%g*js^m5YY`N!-Z*Q!j7CuyV2 zYtqOX&yyzE68IwaweuG9YWLx-E#_D3*1^sGyDc|Y`L(6N`ZVU{Kah@~nkB}il zcJuo7W)J5+zWZ91XYBrg0Ws#af_?;J|AT)A=hZB~pL+OXA8%s6Kfj-9Jm(cCk2UsJ zwZ?PjIs4tmni|h<_3jc=(7&Qp>sEnI^FrQSsPgoXD{oAoRh>@r&1#S?N0pp`oK>f{ zI{eZd@9;anlFeg(MD9gXf73v-80S&sf9?gZJ{krZ#WeCaj=h3M#CIP@$~+xWCnhF= z?!^N0<5n>DB2MhRSQvXRd{umbh-&|HFXrD$JJEcYE^V2hOX+6!d-X;9x5Xz9JC%NY z@CcrB?Z<@d`^DK;m(JLH_~3rQ`?5S*aDH?=`}^%ouKhDdcFI#TdAu{(4;=dKqW%4J zxI(wzMmFqFal`a@v#&4eoz6b*cKM{ok+B`utjXf>rrNvu$7MC!+^gE>TK$8sd-iQM zyG8S#@(;o&wi|jSHM{V*TzYUZ*W-^~hV?Gu?OSiYeGaj9?CZHa3rcQi-)%#qJa;d& zKQ%kbpSRtx=d{13-9lbTsH$el+s ziJ8TM+<7$^Ao+zji{q%^fSCoxpB$&kAbCx7*ycLfY}{HutTtc3iv7 zohzap$8K})ifTvOZSGz%?I^p={VT2=X}0+f>)an{N7!xdUkPoW-RAz4)DE}X+`m%V zVRoDQS6bU^x4D01v_tJS_phwB$8K}~%4xgpHutZ*w##mF|0-yQm|ei!zlz$ycANWG zN!$Edhq>JuUH1PP5`M$_$&}Cn2ybL$xGQ_tm~UGl0nfLFa;%W5x>Q1{X-Y_SO$n)? zDIqmAC8U<7gw)oQkUE+YQdd(#>S-dRzBWQW)<#GJZG<$`Mo1%Vgf!MhNE2;@G}T5( zGi`)4*G5PSZG^PcMo24dgtXR1NE>a0wADsPJ8gut*G5POZG?2xMo1@Zgml(+g!o+# z%&)(BZZRri93i{RBb2*~*UGU%dUzg~H^vI-sY@lKm!^dD)|8MwniA4iQ$qS_N=ScA z2^pX%Ap~OwvZkWNm~@(MHHrZG=qIM#yw+M@TnUlzGSqA8Vd)+}#}^ zIqc)f46l`Ah0OLunP(;ri3ij zM94C2ge=!a$O>(Qtkg!xXW9r^rHzo)+6Y;rjgYn42wA6%kk7RdvR)e@8?+I!Q5zwf zv=Opd8zEb?5%PsLLbhrnWScfZzSKs@c5O$mNSRK8Aei2zg<@y~AteSRs2n zdCY@KtdPCBR6_P?O2~dq2|1uCAzx`q$U#jBIix8ehczYSh^B-b)kMfKZG?QSjgW7& z5prA`A>V2vZG@cBM#x!hgq+hx$a!sqe6Nj=3)%>|sEv?I z+6cLD{X}Qt&Nb^+6Z~0jgWt| z5%N|WA^&PSLTj3-!E zr!m{S+Z)PGZMJ#0+{;d7wt2TajGfYK^KN-KJB8Wi-Etp0x!LC3@(6Y^v(3BZk?f>q zn|I5j*h$Pb@0Lfi6Ps;c*Tf+tvccTLxP*i@n7bH{kiZ6WALA3^+hFcw0zy0+%)LxV zh--tnn~4Z} z2?j`%+x!nYTzd=<-&^yZtJ@XqD5`DWo6QvLwY;pNY{8x%%wMF6Rg|6Ur6>nmigL20 zC>L9ba;56YRCVtfK0{o^%PNs0POw$KR|1N<5gbKTgI%$ovf@iK-PNRMwk6fwe9D3N zj-uYdp7!Q1zs5cm_2GIc>dTg*erze~&z7PAY$+PZmZCvyDH_a{q9JT48p=k|FanA` zA)shD0YxJSC>lvX(I^6nMiWpphJd261Qd-UplCb+MH2`pnn*y=Bm#;i6HqjTfTF1c z6ip+bXgUE!GYBY}NkGvof}^Nsuxqjb;_GByX}fz#(Yn~zS;1cG%RUy(3-)X@|M^0! zqWN4eMGM$cw2&=Di`Y`Mm@P$1*iy8VEk(=NQnZ{cMJw1ST1i0BX9N_jBA{qB0Yz&F zC|XNE(K-T(J}01PJpn}<2q@Y}K+z@wiZ&Baw1t48F9;~wN}wyMw*fmsPYs*z+v86dmAtDf)^nMF-hZbciiQ zhuKnege^r!*-~_jEk$3mrRWoI!i#& zIRc8#6HxR$0Yw)GD7r{M(Ionv*k`nx!CvdjD*8FtQ_OtEn%Kvp+gvY2zp$m~4qJ+TWlParwiNxwmZE!X zDZ0;=q6cg#ddNo6?*tS*BB1Co0Yy&;DEfndqNfBDJtLs#IRQm~5>WJlfTF($D0)di z(JKOq{wAR4H33C$2q^l8fTFhq6#Yv;k@*}5&L1nHD42kv5Q3xVRalI6Uv!%$#mZAu@6h*S7D2gpb(QGM-!v-l7OOA1QewvpePLiMQI5r zN=HCZdIE|v5KxqnfTBzU6lEr$C=0<+PgDQEs*rwoI_8j~eD;G!)k3`1msM0N#1oNGifVJc6xCr%QC+qa z)niLheYO;R%$A}CY$V8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}GfpqV5C~^&p_AC&5uvBgB>0 z0P%fqAB$>AQEU5*)+@woeOX2QLOiuHOHqHWm!bh|DH_O@qCspa8qAiWA#5oc%9f&G zY$^JLEk(oGC>lXP(MSS{MiEdnnt-A)1Qd-WplBQcMdJx5nm|C&L;{K?5l}RlfTAe` z6ip?dXc_@U(+Mb=K|s+=0*Yo4Q1mGQMY9PgnnQ3D^$BtHGeCSx?UPtvDGIe8b(|aG zwZ5#Pg(04~S*2(Z*Gti2wiGR4OVLuc6fI**(Q>vFtzb*hO12bz#+IU0Y!s~~plA&N zMQaHtT1P<9=L8h3C!lBp0Yw`LDB46o(PjdQwh&PC1p!4{2`Jh|K+%^36m2JR^3#6!_eJt7+;OVQVCDf)&jMaS7v^etP8POwpQl7OP`2q-#5K+$Oeip~&Fbe4dk za|9HfC!pwi0*WpWP;`-iqDur6T_&LD3IRn|2`IWoK+z8b6kR8v=mr5rHwh^Ek$|FG z1V_<<5LZYJqv%)rO8+Y<+GhX$&rcy<>&q&-6XMB`ONxHwdMUcgmZIO-Qgn|kMfcfK z^nfiz57|=mJ6nn#v8CuS8%0kDDEfndqNfBDJtLs#IRQm~5>WJlfTF($D0)di(JKOq z{wAR4H33C$2q^l8fTFhq6#Yv;k@*|Q&dYWb1rtydLO_v=fFd^mMIM5q=yr&!iUHy? zpY$Tg{fiV;u^)mAb$P8XtH|f_bj%|~5nL}tk!&f7VoOmpTZ-bar6?|2isG@QC_YS+lfTHXKM^Tu|HPry|ZME+Tg}a&q(2u%)OdTZ)RYQB<6OqK^nD zDnUR|Ndk&W5l~c`fTA)46qO~Qs2l-B+b$R|QAVu}KUW)3o zrRZa}6g6N=QA4&AHDXIqW407EVM|d{wiGpEqo_FnMJ)&@YDqv*D*}pI6HwHKfTFep z6tyFus67Ei9SA7uNI+310*X2lP}GHhqOJrKbt9mtI{`&K2q@}FKv6FOih2`J)Q8|G zs_k+mFK84swC@Vlk)m7n1KE9DUhB&$8tC$TR9K1zalI4`W=qi!wiFFzOVKd46n(;$ zqTy^Q8o`#Lk!&d%#YWL+0*b~EP&Af+qHzQijVGXJ0s%!62`HLGK+$9Zilz`yG?jp& zX#^BaC!lBs0Yx(jD4In;(We9y%_g8|4gp1T2`HLJK+$}Hqo}{j)xrSr)v}L81Egr3 zCAGliwZ5#PB`(j1qEfV!>!oNJTZ)#mrDz3PidM3v=rgtytzt{jYPJ-uVN20kHj35} zQ1m$gMe7MD+CV_jMgod95m2<5fTAq~6n#NJ(N+SAwh>VDB>_d-2`Jh@K+#SDigpoD zw3~pUJp>f(C7@^@0Y&=>C^|rJ6fJVORvRF`!dB5@DJo^hS1zyhWfdK9dA>29m@f8D zV~=vZ6dhwr(bsG#`i3n<$JtW!EnA9Cu%+lETZ+D8OVKGdicS+ybcTSUvjh~KBcSL! z0Y%>vP;`NSqKgC+T_T|9G66+b2q?NrK+!bJOVLBN z6#dSYqDO2gdd!xhCu}MDgDpi**(iEOK+$soivA>^=mh~qe-Tjhl7OOD1Qh*EK+$Ug zirx@V^bY|=ZwV;+mw+Pk_q&~!?I;Q+peTfZA{PNgZUTxt1Qdl5P~;_`D2(7J`qkyi zZ-Dsv*>|Y#O3^C&vOnDIwZ5#PD7U9hX(@{4dMS#-mZG?9DT>FIqWEknO2C$)gls8F z#FnDOY$-~@Mp04%ijomfl$?N~6a*BdB%ml20Y#|^C`v;>QCb3u(h*RUo`9kZ1QcZ? zpePdoMVSdG%0fUOy|6ybIaFhG3v|8(e%bUUx~Puusd zbGyCPmsOPC?U`RziVASO6cuDkQ6aVz6=q9O5w;W+WlK>pwiFd-OVLMcDJsE6QAq-d zN)b?0nt-A*1QeAepr{-HMdb-7sz5+dMFNT{5l~c_fTAh{6!{4#iXosVKtNGd0*a~; zP*k0Oq8bDg)g+*(76C=I367$?Zr1?=#5c-JcRnc!wGT{n++OR;D*D*%`LVndHQ;(F zYRHzNMr6wN1~XaNC53kfJ%L~s-ha=T&-5MK)WhaQ8a zsDb$pUfqk`UhB&$TJH9At|CP%xL%4@vZd%VwiK;mOVMh!6s=)P(OR|?tz%2k=WHoj z&qmP(0*W>gP_&7FqRj*pZ6ToO3j&I^5>T{_fTAx6DB4ay(GCKNb`nsui-4lt1QhKd zplB}vMf(US+D|~y0RoD?BB1CX0Y!%hj-sV**K`BKm)brSEt8^!_Py)FZm;!a6@BgY zd=Vo>-*CMY9cN3?w`?go!Iq+vY$^JVEk&o;QgoUvMQ7Mjbe4^xa|9HfC!pwi0*WpW zP;`-iqDur6T_&LD3IRn|2`IWoK+z8b6kR8v=mr5rHwh^Ek$|FG1Qh*5K+(?x6x}AE z=obQt?hsJ)E5T88)a|-tfcTc%C$VEv6mH+uzU%f{Usllrx96{_QuL7PrRaCI6g^@~ z(POq0Jz-1HA8aXl%9f&MY$_wiW0M>C<$AN zlCq^J8C!~yvr&|SfTENH6s01dC^Z2^X$UAvOF&UN0*cZTP?UjyqKpI-Wg?&`GXX_e z2q?-*Kv6aVin0?>l!JhxoCFl*BA_TY0Y!NTD9TH46h(Vntqc&~VEgy3<9M7``ZetX zQ$CN^`m%}&c|4)9>Gymz~fqLfcWNw88`){D1m(}s_*eyUsh2gkLTMuQq-91 zrKky8ikh;es2N*|nzN;-1zU<*vZbgMTZ&qSfTB(W z6m=$`s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+G?0Lz zK?Fxp1CQ&G0pd$w-xX>oMSJXH(O{3)`m%~X@p$6Ym!jcZFGVBRQZ$k+MWfhKG@30% zW7twOmMul&*itl}EkzU9D4Iw>(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&>ECPx? zC7@_F0Y!5ND4I(^(L4f*<`Yn~fPkWf1QabIplC4xMN0@MT1s#f4fVJR8X&%r_GQ^H zDXM56i)BGYfh|QF*;2HL zjiSv26m21(=nDdhwh~aZjew#r2`Ji5K+z5YigprEw2OeE-2@cvA)sh40Y&==DB4dz z(E$RAz9OLLAOS^(2q-#CK+zEbijEQ-MJqh6K?aELlzpYYQi{GYZ*w2>c&#t1=v$9x zVIwIz!Szyfk}XBwv8Ct~TZ&GzrRWS>iq5j7=p0*$&a;Ss=?N&xKtNGO0*W#bP?VW~qAUayWhI~} z8v#Yx2`I`zKv7NtigFQ9l$(H}JOmWwC7>uD0Y&)&q%C8tUoVQi_Uky%ZH^OVLMcDJsF1qLOSWD#ezf(rhUz!sg+pC44G`Z&`+iXoDGITpVW`*ovWl99dbYKe zqGnt#Ma|h#)PgNVE!k4kiY-O0*;3SoEk$kFQq+zuMeW%r>OeqIM*@mE5m3~bfTAu0 z6m=z_s2c%A-3ch_K|oPY0*ZPOP}G}%qCNx^^(COF9|1-E2`CysK+!+~iUtu-G?;** zAp{f+B{+&2hq|s9Aii+>@Y6(!7T9OBVWD2@%PJZf>Uq^xibiq06pdy}(HOQAjb%&G zIJOjxXG_rpwiHcdOVK2@6isHMXbJ&EQwb=VMnKVY0*Yo3P&AW(qFDqKeM&&lYyyhr z5KuIifTDQ>6wN1~XaNC53kfJ%L_pDE0*aOpP_&eQqGbdWEhnI81;J4?Jk*uCol#WE zzC%4iidw|JU<>tHUslnYP*3R&QnZ%qrDz>niauvc(R#KNZD32$Mz$1fVoT9xwiIn) zOVJl>6m2D-Xd3}VUlLHXoq(bp1QhKgplBBXMY{alI6sW=qi-wiKOZOVK&D6rE>F(f4dAy1P;`}m zqH6>c{Xjs`bpncR5KwfJfTAA>D7r;J(N6>v{Y*g7Z32pZA)x3E0Y$$OP;{4oqTdK8 zx<^3KeFBOe5K#1x;3zr~>iXOO@fEetXeXtpqwCtC#I43MQZ^ zgn%L!0Yz>CiaZ1qg%VKYC7>vbfTC~$ihKkVMG#OFNkCB)0Y%XS6vZK+C@uj-@d%Eh z$Dyt#28i#jefW7IMUP!(#P@owFRLiA*AuV16eZz$DN4$gqGW6-O3s#|6l^I<$(Ev2 zY$;03mZCIlDN4&mQ91&O(i2dWfq=aqg> z`@mGh>$SeDqK~|uk9$f{39gr-l58m|#g?MdY$+Zkp*XE=70jV^I^Y*ZQ)GT6jH+drMJE zu9u=#Y$qIPU4YR{IU4s0pv$d;l`Y!r1Spr{K0MO_If>PA3OcLIuf z5Kz>UfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwVy2`CyyK+z`z z6b&ahikf*{hYb*4FZ;5rxfGSMPj4fY$@8vmZD8;Dca1IqAhGG`hqP*TiH^yjV(oA zvQf01fTA4)6zwFSXcqxRy9p@TLqO490*dw#P_&~^n5m0oPfTAM= z6dfg?=okS-UlUOD4FN^R2`KuOfT9xwN6}iZtGWT=%V3|x)=AND`&e|+>$SeDqBCAk z_d!y0mg}YH99xRcv!&>JwiI1pOVLHP6kTFV(Pg$2U13YnRW^#Q5m5940Y%pdD7ryF z(M{YpU5T>^@JBcSLW0Y&!-D0)CZ(L(}? zekY*l5dlSy367#uUe~7vi0^Z&=(H5YvyVkjyk6_eDthkqY#$;;e{#JPy5*$TOy{>Bp zi0`5OsN*v!YHLX)3iDcDR#CDr&+B1Ql$`6OCSlFjv}7jH0dfPe77}Ij{5!+Gn)l zVP5OYDk>G`DLX=nN^`vwm0?R!S+*3FV@pwawiH!hOHoC(6jfqNQDwFiRbivZPe4%& z0Yw1b5>I4+kAfTuw0Y$Y4D5_0BQ5^z`>Jm^?kAR~31QdNtKv4q%iW(A7 z)QEth#sm~KA)u%!0Y%LSj-nD_u6729uZ@LMQi@L5$D-z8UhB&$Y8~boH%f}yaJ>|@ zWlK>zwiLBzOHl{56m?`vQ75((b!JOZ7q%32WuvGY0Y%*jDC$8#QBMMjdJ$06n}DJ| z1Qhippr{`KMg0jV8bCnNKmv*e5l}RkfTAG;6b&VyXcz%SpAb+qoPeSc1Qd-VplB4q zQPeWbwZQ=KwYPu2sFf6Dx1>ggd95$2XndIG)EFt6!1Yozku61&*itl^Ek#q&s2q^lRfTC{* zC^}9+(YFK?ogkp-BmqU=5m0oB;3!%j<|=A{_^O-f-XKMd?K9fxFt7Dx6`c?BG@K|! z-*debU0_SmMYa@OVoT9wwiI1qOVL%f6kTIW(GP4Xy3R(?4FZa85>WIb0Y$e6DEf(j zqMr#Ux=ldQF9a0bA)x420*dYuQ1lxCMfV6Ox=%pS0|JU35>WIz0Y#4pD0)ml(GvoS z{ve>}DZx>6Hq15505N}xX5gHYBCmZ{`&pRR`m&1t3iB+TEJZK5UW#6^rRZ;d{Yt@d+qOKtNGK0*Vq5P?VT}q9g=I(Vt8JHi~)@P}GZnqTU1)^&z0BF9AjU2q@}LK+ymK ziUtx;G>Cwr!2}cyA)sg|0Y$?IDEfqeqTvJ-jUb?CBmqUE2q+p&K+zZiipCNgMQy@e za|{q)F8lD)R*HI?caz-X!oAj)RWvEwvval-P3C$jn!=W%scb2l#+IV#Y$=+-mZF(# zDVoKWqEFdUG@Fg0IRq5VC7@^?0Y&o(C|W>3(Lw@>77LBcNy%0Y$3`C|W~6(OLqE))7$jIRQoM367!(;jZfjh_9lV?uk-V&%W&6 z5bm|UtfDR9o`2>_(HC4VMO)cYw2duAU$UiWJ6no&u%&1xTZ(qErD!)>iuSNkw3mRQ zeFPNkC!pv60YzUCP;`)hqC*4}9VVdY2mwV$2`D;7K+)F(6n#TL(QyKbz9pdO1OY`S z2`KuGfTB|b6rCoZ=nMfxX9|JmZGa{DZ0j%q952&be%0lH`r2ilPyI*vQc!4fTEuWDEgUzqT2)%{X#&| z9RiAeC7|do0Y$$NP;`%gqWc6CJs_ayApu3d6HxSsfTG6)6g?rJ=nn#lo)S>>jDVu& z1Qh*Aa1?zX?&@HG_~zQbrFKDzirdc_@*>=8eOX0+hkGV0lA_mKFGX+IQuGg7ir%uN z=wG%Jng9I6`E2r16wH>Q5VjP#*iz(XqsT)*Q78dLUIL232q+3CpvXr+Q3L@+kpvV) z5l|FOKv5h5isBMb6pw(S_yiOsAfPBA0Y!-jC`wE~Q4#`*k`hpqjDVu#1V_=!aMvaS z#8<_>U-U|f=Ge!g6h5!@Wfi6IdCn}6qO@EuMd{d5l%6d`8Q4;kku61;*iw|4Ek#+_ zQk0b~McLRW%1%I04g!jD5>S+jfTG+46y+hHC@%p;`3NY=Pe4%t0*VR}P*jM3qQV3e z6(OLgC;>&q2q-E}K+#786qO*Ls3ZYJr3ff0O>h*Y^0}THAif&*;U~4vd8MDnjxs*4 z^<@=R@Ocs~m!gVXFGZEuQdF5OMOD~RYBmZEBGDXPv!Q4Io$Y7$UX zi-4lq1QgXFpr|eZMfC_Ms!u@C#{?8LAfTur0Y!}nC~8bVQ4<1+ni5ddjDVu%1QfL( zpr|DQMXd-ZYE3{<8-k;#oX=I<0P)$+ROBu%MeFQn>+@P)R#8Wvr}0WD>csU@)R`?s zUD#68l`Tcx*izJ;Ek!-pQq+?zMZMTk)SHc>J_Ho?C7`Gu0Y&`@C>lUO(Le%<1`$v+ zn1G@o1QZP=plBEYMV}B*G@O8<5d;*CB%o*%0Y#$;C>ldR(O3eC#t~37o`9kW1V>SO zpKG`Q;>&CwemY1|8vBek(dV_ktfHwt&+=7LG>z+}XgXVpX0WAbCR>VTv8Cu!wiL}~ zOVJ#*6wPHz(L6Sa<`Yn~fPkWf1QabIplC4xMN0@MT1r6CG6IU06Hv5*fTEQI6n#cO z(JBIpRufRPhJd2A1Qe|!py+b~iq;cQw1I%4jRX{JA~=dB`&?feAig#B1C3LpD6M^^ zzuD)tzO15cKF{4XQuHO)OVM_=6zyP3(N4A$?P5#OZnhNdVN20owiNASOVNHdiVhG^ z^c4X`2MH)TL_pDD0*a0hP;``lqGJRUeN8~oHv|+NC!pwC0*X!$P;`=jqVEVOIz>Ry zX#$GQ5KwfMfTD8*6rCra=zD^r=nJ1Ka;;I6)&37;wn|YZ`}eLd_`KGaRdmJY$@RGu zUFCWyy2h5GAJ|fKoh?N-*iv+pEk!@FrRWx0ihg2C(a&rY-6o*u7Xpgz5K#0h0Y!HS zDEf_nqI(1s-6x>v0Rcr12`KuVfTBkP6g?)O=m`Nue-Kdglz^gV1Qb0dpy*Emie3;< z^cMj|FA0vKOFma^1H{+bK8anHqT^v^yz+UiFRSPupQrZ*DSFHGQuHrdih?5a%3X?r z*-{k3mLeBhirj1|^01{Slr2SGHj2UsC<-T_$VWg?1OY{n1QbOPP!vr-Q5*t_;u264 zkAR~11QaD8peP{$MTrO~N=!ge5(0{n5>S+kfTH9C6r~`bC?x?!sR)ju*FM)g1H|`_ zeG+>kMRUyC+^HkH)|XY3KEktmlN4p(dMV1tmZD5-Day>2qAYAF%F33aY-}mY&X%Ga zY$?jgMo}&TigFWBl!t(#yaW{GBcLch0YwD}C@M%mQ6U0~3KLLNgn*)=1QZn`pr|+j zMIRARRDyt_k^~f$BA}==0Yzm9C@M=pQ8|L6C~bu6rUBwhWIyVdF2Z@GA76xCv*s5SvbbqFY` zOF&UQ0*dMrQ1meYMGXijYDhp)BLa#V6HwHIfTE@Z6g4BDs5t>eEeI%TNkCC60*YD_ zP}GKiqP7GSwIiUYJ;6~_F~XJc3!^C9{s~AWDVk*7=I#*TwZ5#PE)kxJ+oY%~*Go}1 zwiI<|OHmKD6!m0FQ7^U>^=3;^AGQ?rWlK>%Hj4TaP&9ymqJaby4I-duFabqF2q+p# zK+!M)iasHrXgC2yBM2xONkGvk0*XcxP&9^sqOk-NjU%9FJOM=$2q>CJK+z-uiY5~r zMV%sCoeU7)ar?*kou%kY`@l3M!fSn5MKdBileSCIOsky+C)InW&(<~5K#05!BI3V!nMT!@m;ll0y15S z_S^Taw?=raFRN%rgy-B&DcZ^PQnZULMZ4Kjw1+K4d)ZR7k1a*}*-~_XEk$3krRX3V zMTZC|I!r*(5dw;i5>RxEfTFJnDEfwgqT>V;m2?B~v5>WIV0Y#?>C^}6*(HR1Y z&Js{`j)0=`1QdNwK+y#PiY^jRbcx_7`ZB`x!T|A2v2eCa(IfjQCfnd=xu~+qyge9 zWBuD0Y&)A81MiUM3OMOE2SRE;e~)!9;1gDpih*-})CEk(82QdEa6MRnOIsz*RkeFBO; zCZMPR0Ywc7C~8DNQDXv%nh;Rblz^gU1QazVpr{1_MJ)*^YDGX%YXXYe5Kz>XfTDH; z6tyRyr~?5-9SJDvL~s;UiF8FDGKxI*qmF(lvY&9q-8s^0eOX1_BRzSJNKp^2m!h6* zDeA?RqTXyN>cf_zzHBM#$Cjf0Y$+PRmZE`d6b&MvXfOdqLkK7uNrqNxNFO(Qsp zx<5*RR%PRUb($n{t6wT&(DVoEUqPc7-n#Y!+`D`g#z?Pzg zY$;mAmZHUMDO$ot(NY46mJv|2oPeSg1Qe|#py)FKidGR&w3>jTH3Sr`C7@^>0Y#q^ zP_&+aq74KTZ6u&*69Gk=2`Jh^K+zWj6m2D-Xd3}VUlJTeGb3FK3=m%z`%%YPQuNr4 z?U7#V%PQI(>Dl{@6z$=9DcZ}HqJ3;B+Rv7v18gb!iY-M4*-~_fEk%dfQgnokqN4;9 z9V4LVYXXYCA)x3u0Y%>uP;`QTqLTy^eMdmiDFTX46Hs)9fTFVm6rCfW=sW>M-xE-D zfqa1>pSbY(U`e2MKx9dAg{8v9EB-$<|ZWfi%iJe9wbB6rmLuk<}^DGFsvk(Vt+ zVQeW1XG@WfEkzM*DT-uEQ4||R(F7F5A)qKO0Y&i$D2h)&Q33*r5)x39h=8KR1QaD9 zpeQK;Mac*#N=`sg3Id8!5>S+ifTGj{6r~}cC@ld+=?ExFPe4%yf}nJyhcl4-sa92<+Z-7qO4J#DW|0<8`tZxC_7tNs5AjZ zWe6xLOF&UM0*cBLP*j0{qKX6*RU)9MG66+Z2#%u6QLe29h%cLklSPW^*{3&ul-K&Q zimF9VXv8AXsTZ-zirKm1jit4eYs6JbYK4zn+0Rcq~2`Fkr zKv81?ikc8m)RcgtW&{*9C!nYW0YxndC~8GOQELK<+7M9GmVlym1QfL=pr``@MI8w! z>O??MX99}45Kz>W;3x`2xn3F|zUTHytf~~*4->h&MR~0+tEg9$C)xK>)SK(2s1I9; z`m&{{A6tt0v!!SNTZ#szO16TQJ&@(rDz`4OVNC`6fIy&(L%NqEn-X2Vzv}5 zVN20cwiGR6OVM&RidGO%w32|L&j=`5ML^MN0*clUP_&kSqIComeNI5pdIE|z5Ky#{ zfTB$V6m2G;XbS;FUl35Vm4Kpc1QdNqK+$#rigplCw3FZ{njPgDZGiZm+mAZVk)rGN zmHw_Muk~dW?ThlPx-3Qexn7D6u%+lLwiF#?OVJ^=6dh(u(Gj*39c4?=F}4(a%|_8T z1QZ=7py*oyicSzvbdrFg?+7S5ML^MM0*cNMP;{1nqH_ckohP8^djg6s5KwfHfTBwT z6kR5u=n4TvR|zP(MnKUI1QcB-IEwZ}xlR}$zC!lzUGJ5mc9CY>i1J!rR?$yUo(ET@ z=x45%qT6gK`h_h;ci2+&D_e^0vZd%ZwiMlCOVNF{6g^<0=pg|`zY|dOh=8KU1Qb0X zpy&?*ik=cs^o)R_=L8h}NkGvH0*d}3py(w5MXv}b`kR2F*8~*3A)x3V0*c-eQ1mYW zMM2SeVUD6;f}`liC|BHTM$s+%SaeH@irZ(jkZ7;85 zwiFd)OHm;B%FGaQ4QdEa6MRnOyRF5r1_1RMNFOpW6RgZT4Y=HQt+P`;QLyG#^_pW<6b)ue(Ga#24P{HwFt!wZ!bZ_>0*XcuP&AT&qEQ4CjV7RI3;{)B z2`CyzK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@D4Iq<(R2ceW)M&`lYpXG1QdNrK+$Z1 zqo{YZE2{zGTVNlH`bbe@``-1OXs`8U6)lMVf7p8yFdOUt|NlO7=AOeC&KZm?G?q|d zW^5t*mWo0um9ouP$`(VEO7?6aTe4**MN**>+9gRyDk%~YT9j1!zh3wI^_ZE@=W~6p z-|v52pU?mQ|6ITSxh`Jk`MA&PeQ%F*pZhFxj(`2PX3^91n?>`^i`D?J=ve?3tp#Awa{w%Q z9)Lyb09dphfJH9=uxJASi(Uj^(MA9ky#&CbmjPJx3IK~X0kCK@0E@N&oJDgBh5L&j ziJ$AMj!&6IAM3H`)j|>VOD%e%kpIMYX3;kK&7$pOvuFp|EP9h{7QIC_i{2)iMemT! zqIbz=(R*aG=zTI4?F3-a2LLSE1;C;Y0a&yffJGkxuxJkei#`Tm(Ov)+eFDIueE=-l z55S@W04(|xfJFxZSo9eHiw*&>=yL!TeF4CtF9BF|7=T4z0h~pz7Yc6_K@tb(+4WYl zsJ4b9g(B*gT6C8x&*+YzX4d}MeS)j7KH#<6bHbfFaV3<0nVat3WYCF!sSrjFkMKQ8jluR~@3X{#EB4jKo3c#Wi02UPk zU{P@Z7L@>CQAq$6l>%VVWdJNH4Zxx@04ypCz@p0mSdaRR!7ImcGEV`9!7TrcRi*6^I zMV-iI(H&&7=uWa(bQjqy>P$9^?j~c=Jpe4~0>GlK04(YTz@qK|Eb0NkqD%l5WdX3L zCjg6j0kEhy0E_wnu;^X@7TpKHqP_qu>IcB0{s1f*0KlSw04%y6fJK7mENUMO z?-D^0XXtC!9n7Np^jMS~ji_I0(Xgoh!%t?>aQe-n2gzp9Lu9jP1lcTlm~0k3LN<#Y zC7VSf$!5`GWV2`#8H+{(uxJbbi^c-5XdD2G#sjcu0sxC12Vl`e02WOGV9{g%7EJ+Q z(Nq8yJpsU?X#gym4#1)r04#bEfJHL_STqZOMY91|GzWl1a{$&7x&wvuHWlELuS} zi&m1cXcYj9Rs*nT4FHRt1z^!y02Vz5z@p~?ShNm+Me6}r^a22jHUO~bMF19U1Ypri z04#bLfJLtWuxJwii#7wWXbS*~UIk#$YXB^I9pEf_IvVaIf+W_`W6^xG=nH)ba%(iA zeyK$}qW%WS#+9g7X3gri_VbEqO)YP=p5NB`jL!9KLN1lX8;!c0>Gm4 z04(|yfJMInu;>B+i+%@S(M13j{Q78s5}6RDgdykA^?l70ANui02WmSU{MtS7F`LzqN@N{bTt5r zssfxv@mf4ZjwqH)x_OaK;T0kEhi0E>D7u&6fxi~0bt=w1L8-3P#; zz5p!h2f(8K04y2+z@mWwEV>_nMS}oXG#G$I*#ImW0>Gl70B2FhSomcTB=IGE>+Dvu z=yrXk|3ECFeyK$d#r#j>%%TzWn?( zG?t7-;{aGR9)Lv?09f=m0E;F9uxJthizWlGXbJ#}rUJ0&2>=#N17Oi~02a*vV9}ER zESd?xqFDeenhn6BIRGr03&5hM09Z5+fJILOoJGT9;Xg%?#2xxVorz17Oj502aLfz@iNREP4@uMH>NF^b!DzUIt*%D*!Co1i+%r04&-9 zz@k?HSo9hIi(Us{(N+K!y#c_YZ2)J{!dSSO2$I-c4?l~{qF411ZF?-DeyK%o$NU}< zv*;cA&7yb7X3=|Ov*>-YS+tXE7JWcAi*}LCq7TVt(QdL?^br}0_5iTxV*nQI1z^!9 z04&-Ez@q&CEII(dqE7)>bP#|=p8>Gw5CDrl2Vl_`04(|vfJKJ^So9SDi;e)W=xYEL zeFMOvqW~;A2Ed|k0nVZ~W8n!RNaAEY7QJN_eW+*G$72!oOD#GT^H=9Li@vAdEILg# zi+&)RMQ6xn(OI%tbdGEm{YW;8ej=MiKae02W;UVA1aYEV>B5 zqCWsw^d|s|{sLgpB>)!v4ZtEV*`BszQ3!xVaR4j|1F$F_fJHt4ixL1>6aipSJ^&Ww z2VhYmz*%%67Tzs_Bo2@mf6^>^J$S;F98tg2qG+;zwt!g_qu(q_CYwct$!1XzvRPD= zY!;=E&7xvtv#2=PEGj`Zi%OEQs1yK;E(2guX#f_L0bo&C02W;iz@k(D7L@~FQF#Cs zRRCa7MF19E0l=b404%Buz@jPuEV>eaMOOi^=xP8KRRv&CH2@Y>2VhYez*$r$Y#+sWV5I)*(|C@HjC<$&7y0` zW>EvOS=5kh7BwPcQDXoWH348zQven<17J~e02Z|XU{Ol|7PSIk(RBbUY7M}m>j7AF z0|1L|1Yl7c02Z|cV9`wgEV>zhMeP7s)EQJS#%HCEb2lwi@K7{qHbifs5{v# z>Osb$OaK;T0kEhi0E>D7u&6fxi~0bt=w1L8-3P#;z5p!h2f(8K04y2+z@mWwEV>_n zMS}oXG#G$I*#ImW0>Gl704#a{fJMUqSTr2qEV?~8yjTQDOwwafC$s1#eMEaOIih~4 zMUN!=+Y6gTkJ4`zjU<~zkCDxyQDn1dG}$Z~LpF=XlFg!VWV2{I*({ns#-hgoSTqrU zMUwznG#P+JQvg^r6@W!g0I+Bp0E?yruxJJVi=G5v(M$jq%>rQ2YycL`0btQw02Vz3 zz@m8oEP5J%Me_kzv;crb3jxle5y|1>B1qyCJ^Vau7M;?tC^@2jsYOeZ{YZ*gw2XeU zXgS#|T0u68R+7!4Rb;bhHQ6j$LpF<^C7VTS$!5`WWGs3ffJN&7ShOC1MK1ubXafL? zUIbv#MgSJQ1i+$~0a)}30E;#OuxK*?i?#r;=v4p~y#~Od*8y0x6@W!=0I+Bq0E@N* zuxJMWi{1n{i=IgiR~11L7wV_?mzYJ(^;q;)azy=7i{4B2+ZH#A-lyLz+DSHxJ|LS# zyU1qIhh(#8H`y%uh-?<^A)7@Xlg*;NWGwmwfJOTNShOF2MF#*_^eF&~4g#>~GXNGH z0$|bS04(|ffJI*du;?%Vi@pM2(GdU^eGR~(Zva?y6o5s?09f=b0E>gijf_PX09f=p0E;dHu;>o}7X1mpqQ3xGbP0e(e*>_{D{N2O zu_y$Xe&_}dFg(K>hT2#2O|Jh|`Q4#vhqM~H8D1~em6(gHP#mQz-39?yKl57^0 zBAZ2*k+kMX3NRDhI%#@&GKV0KlS(04%x!fJK!6SX3E+MO6S; zbR__bt^#1u)c`E23c#Xj04%Bwz@jt&7NrBQChT69fe|MIeCQC<4YqIzVrs6N>&x|VDfH6WWs4asIvBeGf4m~0j`A)7@_ z$yn43fJMy#SkwZ5MJ)kX)Czz_*8#AoH2{mQ2Vl_+04%x@fJJQpSkxAPMK=Mk=w<*G zwF6*LdjJ-70ASHA04(YVz@l3LSacfzi*5%vi)t4Rw-7-RuU2vDm_>c{Sk$R-MEz2W zIv4h{Qq7{f={Jk+A)7^A$YxPjvRTxPY!-DVn?*gyW>F^DEXpFAMLo$_)C+(`y#ZL% z2Y^NQ0l02cKHU{OB+7WD^U(EtDz4Fq7({QxW)1i+%f04&M|V9^i&77Ybp(E|W1 z8V10k;Q%ap5P(Gw0kCKUz*%%>;qXKeB=K2&rhk`N^p`%oJzO}VeyK%|751MkZx)TB z-z*wUHjBoP&7!envuGUIEE-QXizblGqQ}W*(L}OYG>MEwlL1&X1%O3U0a)||0E?yp zuxL5}i)H|@=t%$;%>-c4EC3eG24K+~02a*!V9`?mESd+vqNf2^G#`LP3jkQO5P(IC z09dpbfJM&$oJEfo4(|~`5|2xaA88hy)v%;+ME&v#d2#U-@?TadGeHAYH zy}VUkxipC@}>>1es4o|hW!Rm}4$MxQI;c~zo6 zm-4)-(RyV(FFpF`<(^k7`gS?bs~as)(eoNa+gI|uCeb-nJg-Ic%d0%Eb+ke?&ubIy zljeEtqU$m|uVeIlP0#BTy|#|$b&ft(*YmnY->vU?nbCp`J+F84md2jfH~Lgl&l?#1 zs=4Q7N3Uq*dBdXjwf4Lb(HCy;yphr0+IZfWXv3R5Z$fl*d(WF3eg78En--1U=6N%t zw|4TpxzVTZ^t}1euRD9*;%MbAp0_O8ubbzsioV#x^VUXx&+@$W(Z;KBqTf#SybIB*r+eO?vHPEt z?H`K0GD~(qDE8MJ*#n_i^LerhLb1o^%RUIjK3XU{Arwn_M)pD|cGptb4WZaG%Vj@= zV)|?L6+U?`^F@R%Kn=~wg(3&r$1)<%S4`XyN-Loxl9qcNe_>qle{g<|?W zBa=fh{i29zp_u-q|IAQK|5ST!D5igFJ3kcDKbBk^is@gwEepl;&y`k%V*2+cYeO;p zgMsy-n114WV<@H{+1(V1>1Qrq3&r$9bK62O{nXQ2p_qPb<-Jf$KXem@?_Y#s`r_%4P)uL_Iu?rQ%NHj?F@64dIuz3<5a&WMJp=qD6w`4SoEwZ~5yKK)qPpe6LmxY}NdcoVdoX4%$sm{~iR&B04EcMK0&?moKb@}Q+p z{YQ&deBShEIqHuO5bfgNu|@yhP>jLg5TE-Inc&@n&~%QQKoA! z=BW*fUzY7BdtvnSm!|7BNl0FNV#ZstB}Yor0qI_6i<@tPmom?0^bP|ZPpB?4TEdK; zw;6@6w7vb%7q2`V%;?MuRRA-#8 zpY>!uN0`rPo6o&WZ}-X^+0?R=pIi9dSF*chhmE`MTwE}l_P>wl>ZQnCDp;LIn9Uw9 zrI_5Sbi2)BnBOmylG&6M9Bj9%jEa|$!iC@T2uh~#HG1Pm9UVYXL_3}qYpA%DMMVp@8St=N5$-a-KJ?y0% zkS1NxEZ5{GoyyEFD|%RPu%i06^SVEmGU&L?KfdR7L*k`VZbeUgu>8EPXhQN&Urc&j z2K`f-bWJz0cw%8nJ~{g7NZ&Ij@9q(ug8jL_PV?@;!adWnmK@(?oN-4s{P2*MqTdCf zt0@npx^cpZUYwUw+QzBnU_$cN*~ioZ5o69hFWnPtu%mmoZgoeidN<4QF{O_5=vvu#5|Y$P~X%NuOW#~E|O6JJjfGh{EU+pulB+jIw$@9h{Y-I2|E-WSXL>nL1ALGpCo|;ic4<7G1^n7$;N4X=UU5#q#`c;JcM>n{WDi z!V(=QA$jJGZ+?@tm5o)m@_4xqb(JRFkwxVg8ay_>-+isDWN*R2N@m-j?V0}jBh4!Z zoBw=j_TXU1$@}+Bb9bgcKK$@^xigKE9$m|xt|y$>Tb6Ey4fGTPU0pCDZi!^`Pj{;l z47B{Ob!X-NDa)34?7n;CNG~nAmd`WJ1R3XLf%;&6)WL-0bLVHQl64caR<4}zPOvAF zRy?^vc7%98=ZD$n9`cHBk*2?-DdinoiqteaI$YR$;sdvh{`}$mGS_`Yp~BY(8++dP zKg5G$(xaQ`8rS37Bim`g!6v$3V`ekv_^C5?>6m`feaF+>Hrl!Ci52e9HU8*JiE`hS zvmM<;6I@T6KCl%PrarySd>X91LwaPzCcgXZLAfTo@0HKDKc<@~A$ik*zrT@fT}qmC z8-2_`tHd%J$d@B*a0q;N<>&>nhh%})&yX+O)qy^JamOULt;gPjomg4!;9|j#ab@JeY^b#88otOdyS$W9Hq3W9!z_OL z6FoBfNi}Bt+%6bq_3&<8gDo|E+_{hC1ZBST=o(&fJ${mVJYOa_Si|);=Cv8N)jt1m z(MH|=ep2?=uXGN^tWZO~HBYzxq-}prkX76!J-UiFyPmjw@_@d}#u?2xdw;z+#;s!O zPU~cmWEG45Jf}}E&Ktk%eMTM~_ezhh;~d60Cnto$RP>#W`AN-w+TJo)oRYUS%m{`# zy?T(G@5$nvJTv7v874_it<|8vX!-S(I`TjuYmmNSl^7{=ZZz@xtAm!`K7V5OBVNi? z(h}VNYuNqYown5w9Bh?FHe@@d-#C6&MIAEv^YJgpy+ro=logW?2W}_N`SK5Wu)0ZF z^rS7*wFGYWw%I(yFix+5%w~kmW{aDikUU|>w3F_k_KzJKzLh((%xK&XE4~pX>-+p? z$9|H{KiTHAn>op8+X|c0x6H}y=I5Ey7MoM~nzq8tI>_&S>o&R=YbB2eGN0p5kKg0& zWM|LLyfDH`*=h5s<9dSKe9Y$4mT}y9+iB)=!R9lO>0|$Vr@72W9wxRdxu6FcxnIwj z`MSHuth=M=m0n7sygH#eEpk2Xysel(-KqN=Oi2D<>8roGo&VX)~P9})q^eb z*u=x{i|l2kNrgJeNP6COm5o$J{%Aco*4LfX^v+7p&O#<;`!)(xlDiD{2Wldk1QjHG96 z6K$lp+P0Q$J0#{02C81ZvOILjO0L^9esW-J(!x3)UhSnUlNMdclC-#UwzYzTmE2@Q z-p2Hwv%AXKt?bK%Pp)~~?ScM1hv_4|JlQ+DceLCWcS?`0<$bOvtlzkua=-?9#=(T- z-w#bVq^ArC$xrT?F~#kINu#%YC=X~d)ZUrLM#@>+Vd>J8elb=L zzcSR+(MP7Z(}o8YtiCGP@-;iGyxU8OPju@Us$-jGdhC)s*e3}N*0Y3MQPmnTeOCHM z?lHRC$}8>Hv$=uU z+-9>`&h!u8pQWdC3CW8_p8wTt&enf*k)0;9**@vQvvODOX|vhvdgAg`lxK%FpFNC| zdTfErX9Dw?Y4a&~jje9S?Y^##Z1&gYoN@D+HFd#V!F=|NTf13SXPM2Xoa>3p*IJ$( z+I;FVjyu_XhxzQa`3zgQ5BoBo7k0g`XJDe-=O=&o&bhn$nJEY5f%}*=sUMSE zQ#esib{oknBDw?KV5AKn$IJa%Mp}AkYw(;hA^G&uX{+^g%TFrNWRRRCwUQpSV;=+Q z>8^hGKnF^wYpXtV;%g0LAV2B-1BcUOiTtEV*PpK%4D)r|J(azbzS5!hfiiTsv)ydL zfg2-j#LjMdLh?7;MqU&XWZ9-}+<(HUJNBt~Bm#?cer4K~gh#+k5S#ynjl zKk3Gvd&0qXpLy`o8n@m5SUCB-EYU7$()IM~*_Lr9y!!+P>v_ZmZOZi1J6GMQVFD{Y?MA7TbrBA%8 z4~=qi+RUrt6|W>s!3l2-xuPNzt{<$foVgtNXqW5Wzy0(xa=?)8aicdL*CURf)cWbC zi^;QoY0_%>nsDwixanOl@|g;sbl+}{8e_~IO)-i^d{rT z8Se}m=U2x0aLUMqvOQ#+%@rHo5R7wMolbhPBri=oT3Swg)=G=6W5H|919wKUQE;%1 z+ib`i+;ln3`Q*1z?j-u{>9>>$hD^FL>YiRdHsQt3~1WhLIEA4#HIQ*BIvY@!gvQ8*1)}4_4~~T0-)yAHLq~&X{UH zHoU2qvN7sb;hgJ9NM3Sa+yu9Ex6Hlxz1zA6%FP<8nYci3YW7XGOBH$SP%$cKUt1CS^ zpEsC~obYzE`5a(AZZCIcKD})|MdVf8;H>Y9`Geh~?b>JFS>+xDN8Qm|o?6I!c09iM zO}TRnv-wnZJ;7d{Y4d5sIPQdZKJ!^+^BLi$%gb#aUK*zd1$oH2wEbzfD=PbuGQo_- zeX`(nIZxdpO{&v$*W}K4-?5S2W~5o$|C;FT&41iKA- z(xXBhVxUcOx^>6~N^0y@J$d??KipHOwbeepJlMjMZ(bCy!z6FG@Pa(q{8c*CjSAM0 z&fN2UXVM5?B5rc?EFxUp`D~jS2MARIpI!ty9y3gv#$-> zis?0r&y%N(vUG2Ly z&mQG<*U?Yx(Sue(@`;O|%@PY`Pc|*^<=t{DmmXcqWelWey9;fg&m2rhp8dj}?^G^% z4`;|*?s@3W@uT07O(<)*WzOuavb_#Vldk1C=I$Qqj|&dg@+TX#dedMl$m8JLaqiJ4 zdH1rTnZeSXTf1_uJAW8E@#Ho!HomZ1&*rYlJ=n(t>V0`ABRxCy`Q7>`>nFA8FtlW_ zy`~?H-Wjas+ues`dMPEOMOSkYNaz$73BGW&dRZzr`gN_eV_bb`z%U_;+uUEX2wCHJ@S0Y(nRMdZdIGj-8 zT6y_j|M}%5{4TF#>pwqE!ly#@pMOO-vBVof^`Gy_lu|2QJ6ln5+en@a6WEdpg_R_Nd@Z4d$jqA|HG~F%dPT^nrP8? zGbvz0O4K2fY{+10?vMp-NV`=bY4UTIBU(_FPUjp8uIPrfHL;l#t{!S!l7*;TGC5Q@ zp-G83%}VMVi`2@qc%@~KqIp4F@mHG3MoM{nR7kd6MiK2OHgQzQiz_j`nS6kxxJ>YL zg6z@iUgMGtO7<@l%t+=eZ{EtHgk;+Xmud2UoR_{x>re78!ONFA#4Ei>um9q5In8?g zH96g2y2Rj8TK<>aEf+DsF8Vfo-b>z`Du0lm!VEMHVMiy?WZ9ZfQLS z4@?_8s7KnME`xhybs0ElKz3G-?5xbR9)pGt%pRbiM^@&LL0N@ zpX@$Ev%Iw41Nvp9b?cioEUkLq0X@3)O&i?1+n}tpL0SE?26r2rmQ|z6;OrrpeFmgu z4;aw5NAGTZ`VUU))uTt3ZiD)zWu$kh*`-E$jf^fC=?bd}tk!=(|Ey|R-MaUwmXTh) zW;LB$T_*p-q_jT$d-NTWnU&VBTaVs-`v1Sa7=woo&buXg^-gO#D04`k{sWp17?f2l zXIl)*9u#a6w?*0w8gQ>{^TBDi4D2@OzE(r}cj+kW(yLwHA%nYgXj-Rj?SIE^8rm&8 zOShKixgFheNdF!+Yt*jZ!xI&{WM=j3Hl%NMm+avKvj$i1t%k|&%IwoWTY|jLc1!b? zU1TwPG#}8f-+=zYL_UP+qeDC7$wyWEz|L^Zknb1ypDunVA>1qE7Y>)Ko>neB?J~bu zxL~Tp!PR{~ANqfOVqzoi|`;;mz&k_%SgPefp(qgze zA^+dF5&nAzj(as!-CD-{-36AJxj zx68lV9k)^bJ4XHQz1RPTT>kIaZT}g?oD6Z#g^K(aKD_+@2h{(KGpAk+-8qlRe$K|K6?f|IFB8Ry9Ahf-|X{?Zfh_LyB*5=ra?20uaR1Kn{Jbm74CX`(NJp zKd55vHv0d-ddNLhpStC4xc^)Cs@zrix2bf+d1o9A4uQ`c@;t1hf5 z&FQt=w3f~7HW_l`K5YgJ7?|O;ZQ7|z^P4)>aAUWirFPEzt^w7|oo|ht`8Llpq%B|# z8tUZSs$Q^6L;4Ty)2n}0W~#h^5zMZ+EmuY>Mv*J5X3L!Q$dH8zZeLGs)}@Pd*R0XS zjgTQTqoEa}HMP;2xe>bP%Ot@ID;c%iTFUm2rpzJz`VIFwm;$yTJNtyTNjoxkkEc zuVFnk|9PEj$U5h_d2M&|<~bu~G-pv{#cVF>Ql3{1|6Q+_waDr|q?aczGWPG4)g`Nc zW}j~TyYwB?jg%hW7qne+}H+^A{p!nMGanl>#*9%i0VH)p7fTtD#%oicKTm9?;0BT$YGa%>3} zAS2hl4AIZAbS9dRs%B9i8KAM!M^i!=Nr^9-iSE zGIBRqp8bD~jmJK6YUv#6=59^d)^3a%%stnQ3^`KTcFD+NhwMO`ZO&$6H)S-lO~X#A zmva-@{5DqZ0g*jeJ9l}U9l>VE6(S>#5qV6gBMXwNDTh~i*a&R(u7+iyUQ%c76<@?fI}7DLj*z#^#IgfiRUifjp{1bC*Dl-p1J5vaO8d>{ZzrZeF>T$iYQ! z70f1>BzxJq2rBch6u2b=L<#HoCi#$Fy9tGIG_*$aRYypCMZ! zXqNMept55#bqL$b!*g0tuiR9Z&tU#Sy!f3>(^u8kcK^EcVrE#)~{ww0olEW z^y@CQXWs$cva88kVhv@VXDX0e_8d60cD2C+t7T@?5z=i?kKPUCJ+h&7tM#kiPu^v_ zI&<*At9uSit=22G+RZgmtI69s4SUD}RO{IY3+` zlzVr`Juzfo=bjek>_c}n^{#8)ynbpGz3Vg`)GxJVzwTL?nR0gDk#~}VdlT;vU->`Z zxAaYN`Mj?8w_N1S`w@lYg9a7zymPK^oHr{}Wpv`0{A2Tti;Pd0;6ENeF+3@5s(cc% zp4_mTz8~#{(&VaNw_4lkZJSds~a}BxbZv5M@h&!eS&`{RmWiu+GKQs~wEr`+_P^3DI0yZ=)j z_)qzff69~pDa%)Hot`Mm(dA#B zSmoS2I0w&3HT7v@Zpx6Sx_Qz+JY&qL>(!S+O}}8% z3(IF4bbS55m5yIYYdLXWtL*d^mfL8pB#v7iq_w=~J*ZXs#u=ZhRr;1$UaM95Hd)@Q zwY;piR_Qx#{DM~Liw{ec`6p?Wz7m#eXqCSDS}S;7E90HCN?)eszFMX48@Y?=IDcxD zzIb111^FbER^jEfN?&!$b+k%fGs~T|N?)c{=^JQVzb0J!rdpn@Rr)q)mHn)L>t`IvVe( zRr&^5eo(9QjkCO1tMskXDt#M`zoS+9_F6uqRr-!wmTw*m`toU&zM@)XxhiUv?a;`k zx3cLSYAP+E5v{UZ_2scg=hsZDEZ0qzdux^T8K_m3 zYlQKsTBUEEh1PumHvZTrT>`mU$n}8jLCzEPA{QVrdQM|eYLd8 z^maDAlTFXG>De}YnoXZ;)0f%wm$l0B?XbL4t1RCE%RgzA`Cim2^G%Qw2AyvStB^n`o6GyL96uXiJSH%X_dZ;TBR@Da$T*`*G8-C zw~kuHw*+a8OL6D6ai!#gubQO_3TjEM@;Ox*(uUmiKUEYv<1(ep}a$M0`!K!|WR&z_M zcZu(sds$s9erkTss($oe^UqeR%68IR&*~ug>Nm}gTHPeuM)TWNFUfVy1uk>7g?urb z=Jr-6%C^@$$Lb#0u$sTLT1@T>nk!iCEc;AzAFE4b2WVbr^~6;!pSN1Qn#1Bt3zA6Jlg7OH@N)1)ws4UN3FKL+2vcUPHpe<(^mK0;_}y4OWo#j zWvg8~x!lj{iaT9?(dy~WF8^+|Mi-YGTOHQT<*`<`is-sMKCl|!)8%BVH}rP-cB|9w zb$Nl+1ASdSYPIwLm#?(i{eG7RSY0*P<(I6U8RGIER%;D&xvA9$A9Q)V)omkO{?KZ| zqb?V*+U7Br@31;!w9AXE9vtiPw^qweaQSMhnG;>U-|CvlF27>++*FtUvRY@l%gwEh zc+%y^t?roR@<&$l&2>4&>P_=pzRT*&`7S?W_0U3>zq6Y9jLX%m_FU@nV5@7FyS&-z zPb*#i+iKl4F1NJ$$Xb^tS$*qymp`_e_=3yDt+sp7<-4uUe#zyfR=;?~<&##+Z*e)z zYVX%v9%A+RtuDW6^_Oifhqk*~|4mn~vpVu^m#0{L=UtaSv6{5g<&suA>~gt_)w#P} zUT*d99+$tjTJaN?Gpydb-{l9auK(2K*RB5gnaklrt~U6>)$6T}I_&ZjR^L0~@_ws@ zj=FrA)sEk~+|BB|?_6GK^~gz=f3RBVw97TE_C4eBaH|{6x%`IJ3qQH+|Lkg`^RC`# zbVTODV0i`9>;`d7QY zQdV!a+SBR)tIMozwtCuXNWN-K=Udxq8>_ckooIED)sL+nw^~xZvP}Eat=6;J*XmLsfw@?xs?m$ll#YA>tvtgf?q%<2zT%gMKAX@6a-O|1^G`nc7tR`*&>knfVx zzA{!TS-rz*KdXzaZnS#B>fcuL$rm>1I1Q|}vpUA=T&o{gy<{~-zT_xaZ>#OCW?3C! zb*$A_t$t+nxYe^(E6CRc>3G*zy~*nBRwr3qY<0iYQ&!8$7x8F+ZL5u}-fwlB)mN?V zu^N^yvC+O#Rx4P&-D+Q}ORTn-ETD_-$Wx;rSbfs!N~?#g{%G~0 z)#?r0IL)jMvHG~x*RB3&HJ^Nkfi8El)fQGeSsh??nANpbw^{wv>Jh6&<=X&syed{3 zTWxLiVXHH&zGL-ss|Dqc>b1Y3)oNC|S{-6_jny}-{$jO26W3qV>UCB-Tb*Wgxz$5f zf3$khYMT6Mw=PEus}ES6Y<0WUgI2$`TCADtyV`0OtJzjpS$)ImdshFj8k4_84(4n1 z4y%)`&ekgDAM>m(wYt*kdaE0)zHW89)ty#%Tm97P=T?tdJz@1ntLLp=vKrUIEk{0m zT|u@}l2v(HALJ5N67Wp@fSP>1u;&12 z39fhR-hEKk(7aRSuW0keZiDnq7aQ00{443Je*1gLO|Z}ys`346C#d|r`v$>I?8o=n-&<2A`MUO}10c=Ph~$W`w$8Bf3ef(zr#7La$mb~2vsCtbd% z{A0Woa$S4W2fZ}z7xEVCfxs?0P5;SL^MAPASHnZz4R#wX+-|E~XHwM%#TSB9ov&WD z$iKYH*D25X7LjQz-v@GCTplPTxMa$B^$AjSzIxHheMR$Px!p(s#pQZg`KRNFX2CqU zZ%Fh~#phLe#V(AOEIIG(ddu>C&W)sUJNvWk^z`Zj(o*FjpSrA5H@!yP8nxwmdU{5l z|LfGLm6}?&W}Vt~^oFTj6CZ8arj`5t05@<*UP)$LCHlP>a`D|Up^EG~xl@(*Z+!DY z-EwbU*pu^b;C0>`UaVM?ee!(FZQuCN@3OO#mP@)Z?^cn~;z9|X^mX4*zU)LPasC;( zH^;?AG6ja^iGdf_wuHQnD4*B&^?kYUD81FqCA$VFaz^%9Tt4}u4lNOVV>CYA*N?)) z#YaxaO~M7_=HaSEn(Fm+GV5@9QN1hsPiTKAVU^4*AwIs6uRk&pX_oHASGHfLyIf+1 z7hlC&9Z2t7AE)Sr+aZ%Tdj;bagEk(kzQt&vHS{vV8R|CrOqM0mNTxxqxO_z6O>PHOulf zw47hFEMFtb`83P&HMShlEX&u#a)M@AzNVIa&9Z#WEXQk>9s47uGhhIF!wA$M5D zkUK47$X%8(q_brVx!W>^++!I-x>&}Lu9h*Rn`I2?ZW%**SjLb{%NUYn8AEzn#*ki? zF{HO;4C!MTL+-VVA@^B!hFl;1UiN?fm2#kozrh)zZ&$_lji@vaEMv$h%NR1+GKP$?j3Hw!W5_tm7&6{6hD@-GA&*tMEMv$n%NX*ZWenME8ACp@j3Ik0W5~yrF=Vf04Ee+|hU~M9A^R<3$N|e3@~LGE zIcOO}KC_G=hb%ioHig^E{?C6w&pkFfL-g0N;y;h5IcmsPzW(4{V8{_`HAB9(Xoh@a z(F{3i(F{3e(G2<4q8W1Bq8aj?MKk1tMKk22MGQG*8AHCej3K8jW5^GdG31P83^{8V zL(W;okRL5$$WN9rR2XET1ty6x9D z6Ug@Kn-Q}8`er_|{rYBpvifu zZzcoy_07TnetlEEW86KJ;@3Be0{HdK6ac@zSq#9hZx#pe>zgG2{Q71|0KdLj3c#;# zUIyUTH%kNf_02K>etoknfM4Id9Kf${rULl&&2j*KeX~4(U*D_%;MX@R0z{C4@$#Kz z;VmLaqJ9oJJ{)oueWm9uSA-&}ms)gX$k(6K3@o~eezWLmvRPD>Y!+1`n?=>hW>Fg1 zEJ`PvMHytXs0P_As!7J8S^zAn4Zxy004%x&fJJoySX2*yMfCw#bS(gj8UV1UApnaS z0kEhs0E?Ocu&5~ji<$wjs5t;CQ9H6()She>bs(EXw~)=Ej%2gwRH@%`t^h3R2Ed~304(YOz@kh57G(jj zs3!o6dI7MgHvo(J0I=v@02bW`z@okYEb0fqqW%D9QJYY>l?amffyDT>W>I-nYJhxP zR9{FIiw1{${W;&jqHOxjq9J6nXeik%dVp*e4I`UH!^vjRgJiSlA+lLCf@~H&Ova)| z09f=W0E|(cF-) zKL;IH^c4MO(LAzQ^fcKlnol;17Ld)Ng=Dj65!ozSOg4+2A)7@@$XK)#fJMsyShO5~ zMJoVUv=V?ts{mNE8h}M>09f=a0E^ZFu;@7e7CjHZqICc)S`WaY7XVna0f0p>0MFUJ)d*fj<43V-|H&i#CTM>X%ydddSzG6AvufO21k3 z2H7myMmCGKlg*+XWV7f^vRU*N*(`dSY!_MV|n$XdeKJ_5-l!004_V1z^!Z02X})z@kF{EczUP zMPC50=u3dJ=+#iTguIKM7|~}il|>|(KjJqe~vz|=qUYW(J``F^ex#e zI!-o=z9XAOC&*^eNwQgVifk5rPd1BAldGkT04ypFz@icWEGh}WqEY}X zx(t9tr2$w}27pCn0a$c70EbII1OoS^yR`0ANu=02Va@U{PZL7BvB2QBwdG zH3MK#a{v~#0ANu|02Z|ZV9|8|ENTtFqU!-zbOQj3ZUkUa8-TOus<`ke5hO7xpTmj2 z+APvPl8f%jcgX(PBx1=k7PMO^?`)D?h5-2hnB9e_nW09cd>z@jVw7WD*RQ7-@%^#)*3 z9{?8J3&5iL09e!)fJOZPSkxbYMFRj>G!TGA_XC_oH^+t3MUcdX%wHG|q2d$t-$+ezRy8*(@4PHj5r4n?(3pxXa)d_o&;dgOaKfU_t&E<98ONvx_b5e+emw&}5GPFzI&Qj4CB^XF7C zi{{gB7A+u~MGMJh(IT>0w3uubJwrB&mXOV&rDU^c8QCmaPR61Y04!Pwz@k+EELsh~ zqBQ_4dKQ31YXMmF8~}@+2Vl`U02ZwWV9^TzEZP9Tq89;Jv=M+sF9ERVWdIhv0>Gk8 z04&-Jz@jYxEP55-EP5&~{F(@oxH2T-%rlGH>apmxxQP0t7Hy03zr4yU+D^Y&w1aFG zy-7BU-XfbtZX0E@l? zV9^nPvuJBvIPPk(Xof!1f5R+lqG#7%$3@gHwdmV8zd|*$=s5jm(RXCC=mgm;I!QK* zPLa)`@5yG-X|h@L1KBJ(LpF=flCkI<0E>PEV9`$iEczLMMZW;B=sW<6eg$CBZvZU1 z0KlT(0a$bqfJJ`*u;@J#mHt+ zGTAIDOg4*(kj}f>DF7B-2Ed}y04yp4z@oAMEV>+k zMX3NRDhI%#@&GKV0KlS(04%x!fJK!6SX3E+MO6S;bR__bt^zoV@`b}wMUX`O&ae3V zVfRdbyB>?K4oB24wJ0s@ugfrt(&;ygGRS684YFBOlWZ2%BAZ3E$!1X?J=Q3C)LH3VQ$BLEgP24GPW02Va`U{Nyw7BvT8Q40VTwFF>MD*zT< z2f(7%04%y5fJHX|u;@kr7PSFjQCk2O-2}j*n*q+EYT@uc5hQV_o(feri~iCBQ@e0P z{ZflMhW+z3&7xcBH;Zl~n?<*i&7w|Zv*-@8S#&4aEV_$q7Ih|@MR$|UqI<|#)CGV= zT>)6s4S+@60a(-nfJK=AEXo34QBMFC^#Wi~ZvYnc0btR+04%x>fJJ=)Skw=IMg0L- zGys4_0|8icKLCpc0kCK=0E@B#&Y}+CaH(2ik$!(%{4HkDK7Ap3NI0T?sYS!X{&(Zgi3=n=A6^eEXZ8c8;b9wVDYqsV5_XfhU!0btQs02Yk{V9|I0 z7EJ(P(c=Itnh3z6NdPRG48Wo(04$mcz@jGrSTqfQMbiOTGy{M|PXe%LCIE|O0kCK` z0E^}TuxKs-i=F~FiyjDvyNV!*E%jJ5%q*&-k7)D45%o(gS{U{plRxJR-bY(Rzge`H zY!*F3Hj9>!&7!4bvuGLFELu)Bi&l`$qLpN`XcZZYRs*nT4FHRt1z^!y02Vz5z@p~? zShNm+Me6}r^a22jHUO~bMF19U1Ypri04#bLfJLtWuxJwii#7wWXbS*~UIk#$YXB^I z9e_n!0nVcN;qVF(B=IV>Xn|Q&L&F>4i29`#y&3l3l|SMPEP9K6v*>NIS@aIsEP9u0 z7QII{i{2-jMLWr6(FbI+XcyTm`jCu8y8&4A5de$!0I=v|02b{9V9_T4EZPUaqWu6Y zIsm|;PXSnT5P(IW0kG&00E<2cV9^%bS!!(yu>_KNgOtUuw~buwPKVVK1=gB>iU5DY9AgJ=rWeO*V^uAe%*J z$Y#-5vRQPFY!>}UHj92DW6{q5Ecyk2Mdtxn^eX_1egk091ppTP4#1*|04(|gfJJ`- zu;?!U7F_~h(cb_p^5X4jI~IiiSQH1qqA&o9;sIFX1F$FofJG4i7Ucsti;joGHAIla z=KAFRJF{qpo?YjUkEma2QNeismd0jLA^OdtDA_EEkE^+ zEGkAei;9!6s009uN&>K`6ab4Z17J~U02Y-2U{P5B7F`a&qErADl>=Z=c>oqw0ANu? z02W;Vz@kb3EUFB^qACC^x)OjzR{^l-Y5*2h1z=G%fU~GTe0Z1$lGsp>MM?4Qnf?wv zyRIG|QNPrp8u9*9P0ga3^qWPs$YxP(vRPDzY!+QZHjC<#&7yi_v#37VEV`C#7BwJa zQ9}S0H3DE!V*nO40bo&602Va^U{P}b7PSCiQA+?8wE|$#bpR}C4Zx!70a$bc0E=z} zU{Mx*32)?EqNR9)Lw10M4TH`0!Q{Bypa^_zbh?XFV3(5+6~&)S}zt z{jZvvMV;t3i|!zsMR$_TqPxguQD?GQbT`>7x`%8Qbs?KYUCCxqH!>D=2VhYT02XBe zuqX?FMLhvn)C+(`y#ZL%2Y^NQ0l02cKHU{OB+7WD^U(EtDz4Fq7({QxW)1i+%f z04&M|V9^i&77Ybp(E|Wy(XH{}_!eT(-}3pxXa)d_o&;dgOaK02a*wV9{Iv7Ci;PqIm!; zdK!R5^8wDH2jjyxh#-kk{oM6KX3@9$F_8uF5%o(gdM4h#ueDjUgnqMVDcLMqMmCF< zlg*+PWV2``*(_Q`Hj7r1&7w7Av*=ke7Oe$f(Q^PSdLDp9>i}4^9)LwJ0I+BS0E=D( zV9`bZ7QF<(qL%?!^a=orHUY3`GXRUW0I=v)02aLlz@payShN*@MQ;GGXd3{Fwga3+ zi{iu6M3BUTdMsLO7ERDcv>ovg^-C>!C*FVI2D9j0`pu&E$Y#;|WV2`|*(~~iY!>Yz zn?)az&7$38v*;tTS+s|YMIQsOXfFVZJ^^6SJ^&W&2Vl_w02X};z@mcyEcy(9MTY=b z^f>^Fz5rm+mjEm}48WqV09bScfJI*eu;?2A799m((J=rPeG9;%;{a#TTk+uoB1qya zeGq%wESjy)^uLRbs9$Q)_woL3@}+LUGyT)_n?*m6&7w18v*;|@EILOvi+&`VML&_v zqMylT(Jy4P=sX#Veg$CBZvZU10KlT(0a$bqfJJ`*u;@ zI;)RpNq$8AQj21~-|%L$D4Bk47s4M`BE(c&yDgcYh0kEh%0E;RBu&5#ci>?4*Q6&HtRR&;D6#y1p z3BaPO09bT20E?;uu&5dUi>d>#C=Gx`=>TU@AwS$*1WEi$pXo<^_e{Tq9+)!xi29`# z)%N|-?aiV(^qWQ3kjG`3S=5MZ7BwbgQ4;_bH3eW% zGXNGf2VhYP02Z|bU{Nao7F`FxqSgQ`x*mWl02cKHU{OB+7WD^U(EtDz4Fq7({QxW)1i+%f04&M|V9^i&77Ybp(E|W18V10k z;Q%ap5a2B83hROk+~=y^RBJ>*B!FSY1V-;dsA7LBCeEP9M=7L6jCMWe}P z(HOE>G?r`@jU$^y3mw=m`K8O#@)jbO093 z0ASIR04$mbz@k|IESe3#qB#I8nhU_9rvO+q4}e8a1F&d50E-p?uxKFwixvT#MGyPo zS|Ui|0DW5ah*`8(k4209i29`#E%W_bJDEkx={Jj3kjt#(F95J;0|1L&1pHsb-3N43^}n|LJxq4?WKw2AF*K2; zf|L+CDAJMMQB)KHgx(Vn5ETSP5DOxTiUqM(EGQ}}A_^)h3W{CqfDI8572)~*vhOR& z|D5-%cRg#JwI0^eJ@=K&WHR$%GLs;p=xG9q))P?l3;{*Y5>T{(fTHIJD0-fNq8A7# z+DJgriv$$CL_pEY1Qcx|py(9>iZ&Ba^eO>GTL__|yZz`~0}`L({@nFiDf+_Rmhze( zIA2cD8@_+rc~bNy=a-_l*iy8eEk$p$rRW{D6urxqq8)50dXFtd@3W<7CmTh(2q^l1 zfT9lxDB4Xx(MJRneM~^nCj=CIN!QDf*T3 zOVI(g6#d4QqJwNH`kgIBhuBi|2V05`v!&=ywiF#ONnP!uDeD2;%kH~~fJ1QcZuP?SkP zQ5GRo^phV=y}%T?pSz~~EJfeCm;H&RfTBhO6g4KGD3^euCIl4a5m3~WfTCuEP*HYjw6_6?Kj5BS zmro5}>HF?Kw{D&qIA2at>r{Voz7)0L{8H4GEk&oZrRWT{6t!bZ(V1*1YR{IU4s0pv z$d;l`Y!r1Spr{K0MO_If>PA4(Sp*byC!nYY0YyCtDC$K(QEvi@`Vdgmmw=*v1Qhir zplARAMFR;a8bmJU5KweB0Y&E!P&AYfDr%V;y}^LQ7r5s|t)yt9`*Fy*se$w5 z6kU+&KQ&5+DFhTvC7@^;0Y%dZD4Ib)Q6T|EMFbShB%o*(0Yw)PP&Au>qB#T< z%_X4dVgich5m0mqAyjmJYV;!m62HlP*KwE>EplJcE=>)bFQ@48RR6C6DO$++rDzdb zimqTw(Uoi|TFjQBtJqSsge^r&*-~^hTZ)#kQFILfMb{EgbR7Xj*Aq~*oPeSm2q;=X zK+%l^6s;tn=q3V+ZYH2;6#+%J5Kwe00Y$eFP_&wWqT2~5x`TkCI|(Sdi-4jv1Qgv( z2o=pwjn)`rikiA7)C;7jYVixU)WG?2itbPK+mDl?2ROeJJ;;`#huBi|Fk6ZqVN21Y zY$nik@Jj=t%;Ko+6;=X#$GY6HxRF0Y%ReP_%)7qUQ)GdY*uy7YHcY zNI=nx1QfkQK+($t6m24)=oJErHWN_vDgi}X2q=1ufTGt4DB4O072TT}9c@73?tc}P za-S5`B@=y$dh9b!w-A8aW)%$A}**-~_bEk%E^rRZS#R(`%C!i>UfTBzS zin0hON)S+#B%mmp5GwjLHG05+#NTrdKL@1fLHF#sd=NNaPSFX0pFLHIayY*fRc1?3 z6}A*rWlK>twiH!oOVNpJDXPJiqLbKCRFjROS_Bl;CZMPe0Y!BQC_0&dqEiScI+cK; zdIS{JC!pvw0*V?CP}GosqDBN1H71}amw=)s1Qg{FP}G!wqGkjXH7B5`1p!4Z38A8j zLA0d-i8pqy^eYA7EB)Wy15>LYaK4Jqal4MLX38Qddcb`}yDtcwFQ@3Cz^^}BiXP_tQuGL0iXLT4 z(PL~WdYmmq>)2BC1Y3%pWJ}RgY$g zQ1l`JMK2Lh^fCcOn+Pa+g@B^X1QfkWK+zTgie4k2=yd{$wh~aZjew#z2q=1!5Gr~g zi1sxg@z33V8~dOXO>mDzZv}z#n?PN>QF18eXz?Py9 z*;2HdEkz%(rRZZeiasHr=u-lUJ|m#$a{`LKAfV_=0*dw!Q1lf6MPCz8^bG+;-x5&t z9RWq(6HxR60Y!TWDB4Fr(S8Doek7piCjyFoCZOmS0*Zbmgo@q{qBk0l_-OZ3=p8A# z!#x%q2m*q<)ADmx`4zs1`Pqq{tVN20pY$^JiEk*yZrRXSIivDFw(J?lP zjuTMi#q_crMG*pu$`Mc$C7>vUfFhrOqErHk0s@L+1QewaP!uPiD4l?!3<8QW2`I`U zpeR8=QIde7YyyhP6HruvfTD_oP|?94`iTLF&vD;%{9TGpa-=H70_V#qsuJ`6xm1d( za(*eQ#+IV$Y$-aCEk!lhQgjkqifXc@s1{p_YO|%N4jV;v2`D<5fTB|fC_0sZqIv`r z)hD3nGy;km5Kz>RfTBhO6g4KGD3^euCIl4a5m3~WfTCsu6g4NHs09HdKa)Zfq$!i!DXn*(mBkKv7Quih2=H)SG~!J_Ho?C7`Gu0Y&`@C>lUO z(Le%<1`$v+n1G@o1QeZ3K+!n_6b&Vy=v)Gd&Lg1cd;*Gw5m0mi0Yw)QLPcl9qGJq5 zysv}PPKp-0$D-k}!1;2DM#cQa3#Di@=a-@awiJzFOVL=i6pdp`(Rj8LO<+sWM79)7 zVoT9vHj1VYP&Ac*qG<#aO(&pe1_4Ed1QZn!P&AW(qFDqKT|_|9Yyyhr5KuIifTD{D zD4It=(Io^FT}nXFWdsz>C!lBn0Y#S+P_&Q`D$0*VA2A^DL+-ndBc-T@Bef_NIA2cD zRWbkVE2L-%=a-_TY$>{$Ek(=NQgjVlimqi#(RFMox}GgX%h^(N0~P;@&1MRyQTbSD8tcM(vuhJd2G2`E}iK+!z} z6x~Ze(R~CI-A_Q#1B6h~m9gkS0}_AD{pf756eZlV>jz_j^W_vh8uKe$B}I>MekppK zEk*0tQuG8{ik@Uk(Nk)BHD3|oqxWus^V0Y%RdQ1m#6um(}(VGMmy+uILb^?mt zCWML}jzwD=ka%C4DUV1|CHEEWomk*}IYsZs{BxH|(N4}UMZ4Hi^Z{FnK4eSLZnhMC z#FnCu*;4cgTZ%qqOVMX+6n#!W(H8_1eMvyk9s-KKBB1DN0*byNpy*oyioPSD=z9W+ zejuP|F9AjS2q@Z5K+%r`6#Ya%(a!`F{X#&|uLKkwAfV_s0*Ve2LPa}b(Mt`8eLXWc z?@7@y_l@k|V}bMK6#W_V?_4HDM>xL}{l%7|zu8js4_k_kvZd%>wiF#>OVM$*6nSZS z-7ZBDHj2s-P!uJgD20F`pMauN0*V3xiedy5r4djRC!i>ufT9cniZTf($|9gBK|oQG zfTC;yipmpERDpn^iUbr@BB1C50*Z17p`t%x(JclfUgREr4ogwG86xCu&QEj#q)nQ9fUA7dR%$A~4*eE)cfTDT?6xAo7=rjU~ z8W2#_kbt5_1QazUpeUDsq9z0sX zfTGh0C^~}>Dyo_mjbCSqu1qyJ)zZRO`p>)3E-i4roT83teuL#w)QR&;QD?Rkbzw_U zSGE*&V@uIlY$@u_mZBbPDeB3VqF!ti^(LUG4*^Ae2`K7EKv91JiUtr+G?0LzK?D>H zCZK2t0YzsMP;?FfMMDWFI+uW=^9U$9pMaua1QcCBK+%N+6b&b!XaoU8`GinW`?P3( z0}>zR9)3DVk?)>ek4y`kFQ;fsnm>Jo6piKlQZ$Y&MdR60G=VKe6WLNUi7iEw*-|ux zEk#q=QZ$W?qUi(_%^;wtkbt5h0*Yo5P&A8xqKgP9noU5_90H2w5>Rw80Y&o&D7u7z zqDu)Vx{QFL`2-X#AfV`S0*V$AP_&4EqALg}x{?qo8l4us$$-Rbxrd(uDRNJfQWmEL z&X-ekb(;U|N-0{#`K9O@wiI2iaugX(Z_5l z`h+b-pR%RsGqx0c&X%Gt*i!T*8%28vDEf+kqOS=k`i6j_ZwV;+j)0=?2`Ku3fTFzw z6zwCRXg>i(KN3*%69Gj(6HxRE0Y$$OP;`KRqTdK8I!Hj#?*tSbBB1CGLa1nGT6CNN zi4Slu?srMiR`;XX!)bx@yZKv5+EicTP)D2ITe$^;ZuA)u%#AyjlEE&7-NiJ#$~7yTtgOWk8pwRqrs zIYlSM{dez>qMDpvifXZ?s5V=Q>aeA#E?bIDW=qj2Y$-aGEk*U%QdFOfqSFW{YCu3y zLjsB#5m3~afTCOiikc8mlt(~OQv!;b5m3~efT9)z6tyIvs1*T4tqCYqQZ$(@MN`;PG?gty z)7Vlpoh?N(*iux;Mo|#~MKcK~nngg-MFbShCZK2z0Y!5OD7u({qIm=qT|z+7r34gR zMnKVg0*V$8P;@x~MGFZiT0}t66$BJrNkGwJ0*bC8plAuffMlkmjEzU<8<6-@?%`*g z6jg9v(U!&o=gTR&Htw&vSBkFV{8Ds1TZ)#mrRWB>6s=%O(T!{=TFI88o7hrxGh2#Q zu~Bpj0Y$eGP;?ssMXL!Yx}AWcI|wMclYpYT2q;=ZK+)X<6s;wo=pF)!?j@k;J_3sF zC!pv70*W3apy(k2iXJAQ=n(>n9wngYF+!+lSv>l>0f{$v-)Ou>idwl>`j5v0=gTR2 zD(?SqzZ5;q`K4$*TZ*1xOVP7zDcZo6qUYFB^gLUNUSLbnMz$2a$VSmi1QfkYK+z@w zie4e0XfpvtuM$wSg@B^h2q=1;fTFDg6m27*=nVpj-Xx&tEdq+R6HxRv0Y&c+Q1mVV zMLP&6dXIpj_X#N4NeC4^5szj(V2ZNcpWc5`iem1uXjeRNzMP_u;(nutr08SLFGZiQ zrRY<(6n(~)qR-h<^aWdrzGO?$9<~&H#g?M4*(mykfTC{+DEf|oqVEYP`hkF=y#y5P zBcNzM0YyI&Q1lZ4ML!cz^a}w+zYYREk&tpDGJyqiV;whMnF-VfTDB)iZTc&$|RsDi-4j80Yymyin0kPDo;RB z1pQl$fT9x!D9RzAs4@XXRR}1mNOeqIM*@mE5kf^Z)1zM)koddqr?Iut!&mw%-D6Sb^uYOYiq1;+ zkFS%W?wntWda$LaCtHeov8AXtTZ;OyrKm4kiu$pos6ShZ2Cz{ykbt5=1QZP>plApI zMQ0OGbPfSULkTE4mw=-42q-$AfTCdp6kR|-(S-yQ4JV*z1OY|)1Qd-VplB2UMWYEQ zDj=X}3;{)B38A8{>Cw7Rn4*8(cOAP)(cSj8lyT{S^W_vxO82`yB}J1tzZ6YjOVL!e z6is7G(R8*H&0tGWAzO-y*itl;Ek(1~D7uJ%qS*u#%^{#@E&)Xs6HqjdfTBwXD7ut@ zqRR*cU zonS!XL)?$?CrZ&2_v4Uj(gWwqDO#THU%g(6Zs7bRv(0Yz&FD7u?~qO}AR-9tdpy#y59M?lg2 z1Qb0$K+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qe|!py&xgsOY-%=sE)uf7?A4T`xsF z-B+|H(*x(rDS9T|fA3i-dY1D`(FV2@J;#=!=h;&90$YkUvZd%nwiLa@mZF#0QnZPU zqE`qg+Dt&vs{|BnA)x3r0*YQIplB-rMcW7{dV_$XHwh?ui-4l-1QfkZK+!t{6unD8 z(GCKN-XoyseFBPh5>T{@fT9lwDEg2PDtbCSdf0%(t2#LArRY}oShPDmaK4S%i4d^ts4hJV3EDT-w1mAn*{V@pw# zEk!A8De~D;l**Q(fGtHawiKnYr6|ruQ91!d83Yt%5>S*yKv9B#q9g%D*#s1oC!nYT z0Yw!FD5^w2(Fp_;0*YD?P}GuuqE-YHwI-mb4FN@M2`D<9fTA-9 zC~8MQ(U}AkwI`sc0|7-H2`K7BKv8D`inz(Rl5~OtuuwVoT9QY$=+}mZCXq6wM`|=wbqj<`GbI2?0fy5>Rv* z0Y&o(C|W>3(d7gbEhM055dlS45Kwd_0Y!@mD7uP(q9p_rEhV7nY66Ou5m0mu0Y%pm zP;?z3R5UpwI@o~3ySpdUQ>5rTH?GeJoG+*7#teVvYf`k5^Gnf9Y$>{#Ek&!?QgjPj zif&~~(QRxgTFsWC+u2fd2OC9q5>Rv(0Yz&FD7u?~qO}AR-9tdpy#y59M?lg21Qb0$ zK+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qe|!py&w#ik>8(=qUnVD1_4EH5>WIO0Y%#hD0-WKqIU==dY6Er9Rw7; zM?lg01QhKgplBBXMIR7Q^dSL7y9p@zh=8Jx38A8AGopJ8NW8gw_}L&uHSBFEpJW8i zms9jbh97xTioWFhQnZIHMPIR{=xeqVeZ!WbZ`o4x9b1aNXG_r!Y$@8yM$tY3iuMyw z^dkX9KM_#$GXX`v5K#0h0YwK0DEf_nqJsn!{Z2s9Ap(m2AfV_l0Y!fjP;`WVqQ3|z z`kR2Fe+Vc#NO3D1s zSNc9%ic;B96tJZz#+ITqwiLzLQk2e?q71eaWwKF}MLV6y*?5RGEOHDg+c&C7`Gp0Y%jbC_0gVq8bDgokT!UO#+H)5l~c{fTB8t zP*Ef^I>~^ShMcms30Yz;HC~8YU(dh&fok2iR zI|7Q%B%r800Yx1MDC$T+Q6~b5IulUTg@B^21Qc~6py(_Din5~OtuuwVoT9QY$=+}mZCXqDVoccqKny5G>?sCQ zK+ysMiY_OhXdwYbiwG#Xf`Fnc2`E}jK+#nM6fGg3Xej|jR})aQjDVtR2q?OifTHUN zD7v12qU8h>-9QKxP0Ng)X+Yvf-Ou!=OHn)bShONDaK4~^%BB1DD0*W3Xpy*KoiXJ1N=y3vy))7$j1OY`)5>WIM0Yy&}P_&+aqGt#wdX^9> zTA3MLWI*Cyx$ipOBt@^gSNa<=1Lw;r+L-CzyIYE0mZHsU zDSDMHMO)ZX^cq`=UT33dD*;8@2q=1kfTA}ED0+*4qU{6}y-h&TI|LNHOF+>M0*c-v zpy+)9igprEw2OeE4+tpwkbt7y1QdNlK+(qp6n#QK(We9yeMSfsJ)aqU(}2Y5yFYjR zf)wp_KMwgkGjP6~qOUUjA3v6&uQ|UIeZ!WbZ`o4x9b1aNXG_r!Y$@8ymZE)ZDcaAL zq955P`iX#|p9v`Xg@B@82`D;1K+$gm6dfd>=yw8&4iQlF2LVNg2`KuLfTAM=6#Yd& z(cc6V{X;;}Q38toC7|dS0Y%3NDDtxO!W=~rLa6A=%xLlxQ}nibEZQSQhuj~ZEteHI zUrteKmY?^T6a}1LiehXjN@Gh=oGnG^Y$?iMOHn3Uin7>JlweCyl8vHl0*cBLP*j0{ zqKX6*RU)A11Oke32q>ydKv5L}imDP&RE>b5>I4*>NI+2y0*X!|pr|GRMYRYhs!c#q z9RiB#5>Rw90Y#?}LPaTA(X$Om{3!>=&kA4Z+cRx@!Il*`UrtejEdQb}q^Ke1m!d{& zDQe7?qFlBVHDOCp9$SiqrKklPMJ)*^YDGX%YXXYe5Kz>XfTGh0C_00H zqILunok>7Zdjg6&5Kz>SfTB(W6m=$`s0#r_T?r`aMnKV71Qc~Apr{7{MLh{9>O}|@ z)z6BqHX!jW?z@hsNzpz>s&`i4d^tt^v-}tLNYMb!FGT~{QZ$GyMT6N=G=wchXS1c~ z9JUklmU(FFt)T}VLDZ~}@(5Kxp)K+#A7ibfGoG@5{-0s@N0 z5KuIhfTD2(6pbgKXaWI66A37qL_pDG0*a;(P&Ac*qG^OsQQxfS*9IhB&AmqJCq={E zv+LCc&M!q5v88A>TZ-nerD!f&iY{hL(LA;kUBZ^4OW9I%85>3O z2`E}XK+)v{6fGp6Xb}NLR}fHiB>_c?2`IXXfTAS?6fGs7=xPFrmJv{N4FN^h5>Rv< z0Y%pnP_&$Yq8kV(T0ub3jRX{}B!r3zv!eA3Nc>v&SX3lMpSx$*H)RFRms50Wmfzz$ zDY}jGOVMh!6y462qC419bSGPi?qW;P8nzVO&6c9IY$>{jjiP%AD7ue;qWcLbdVqkU z2MH*8h=8Jp2`GAmfTBkUD0+;5qQ?m+T1P<969g1JNkGw41Qb0@K+$>vik=~$=ve}a zHV{zs905ho6GBC+vZ7NANPL|8uH!9I^n!aVdLb)tzMP_$v;6CRkfKeTUy5E~OVMVw z6urupqAhGGdW|hbud}6SD_e@Tv8Ct@Hj3UPpy(|EinbF_^fm!S?+{S*E&)Y52q=1w zfTH&aDB4Lt(JlgtJ|LjzLjsC+6HxRK0Yx7ZQ1l4_MV}H-^cev~pA%5@1p!505<*2U zW<{SiAo2R{snAPO^sD>hvwN}v=gTSjHp~BDpA>z^`K9Q4wiNxqmZH6EDcZ-DqWx?s z`jIU~Ke46gXSNjm!bZ`r1QZ=0py)ROiVhM`^g97XhX^S8gMgyL1Qh*AK+zEbivA*? z=x+jw{vn{~C;>(P5>RxEfTH6B6nP1~Y)4UqfTD5)6h#RrN+E=bzRrsNZ9w90Iym1* z(L6`WPXx}FQ1-*=U`tUZTZ*#SQj}mzQIai1*=#8)&z7PJY!p=_ zpr{f7MJEtYltVyKWde$-5KvT=fTC&y6jdjn=tKgFY7kI#5&=au2`H*XKv8W1is}$h zRF{CFlL;s~g@B?{2`H*ZKv8`{s3=H8I~b7oV)s-imIzJql&;Lb= zayh>gHDOCp9$SiqrKkm4idwRzs1;j^TC-8qhJd2B1QeZ4K+zcl6tyFu z=u85N+7nRJfqPkRSHv)>zBA}={0YyCsDC$W-Q7;0DdJ|C8 zhk&BKgiuk#MD$7n65rrnqcxJEeZ?=>5`pvO6b(xF_aBg=!JJ=;hOnjRY_=4g!qPc7-x|l6R^Vm{!30sOTWlPazY$=-0mZAl0 zDY~4EqJ;z$Eh3=k3Id9*B%o+90Yz64P_%@AqNM~BT}?pIG6IUOA)x450*bC9py+x6 zik1^lbOQlJD+nmMk$|F=1QgvwK+(+v6s;nJie@FE<$pItOWcp~FOs6;zKvTFf%D}Q z-JbB9{UJqnaDFMelPyJev88AYTZ-;xOVL`k6y3v?qI=m=bRS!a?q{Ru0RoC1B%tUa z0*W3cpy&|-iXJ7P=rIC{9w(q^9RWp85K#0a0Yy&{Q1mnbMe7MDdWL|aX9+0UKtR!R z1Qb0_K+y{X6m2A+=tV-P=(a?3r~!%ha*su;rD(kSiuO_>aK4zPUY5NgMHAh(Aiqfj&X-g4L&AUgFDcr~`K4$dTZ;CxrRYbt6#c}O zqMzAP^b1>xeq~G10k#zV#zxUW0*Zbopy&_*MSl=bbeMpmKM5#0LO{`91Qh*EK+!)0 z6dfg?=wAYgjuB9FoPZ)Psh902iV#p#j)0;l0YxbU6!`=cr4mpS5JE-YC8FONkofKH zi`e&4bfJ4JiX{W*%PGo8`uhK)@&(i!mG}mNYNoT1||dN%PBfL=`Z)(1vK$e&f)x0G?Xnx z=dz{fJhl{_&z7QLY$>{cEkzfyrD!-?ibk+elutm>NCJvR5l}RmfT98dipCI7G?sv( zaRd~NC!lBo0YwuDD4Ik-(PRROrVvmxm4KpY1QbmtplAjGMTGc^ms50c(%)T9iso^CDY}F$MVGRr=rXnx&1Xx|0=5)g z&X%HuY$;mAmZB@zD7un>qQwLhT}43A5(0{r5>RwC0Y%FQD7uD#qH75#x{iRN>j@}Y zPC(HO1Qe|xpy);didGU(bQ1wZHxp2_ih!b92q?OhfTG(7p`tm-=ura_@8`aEJy(kM zxyPc_$-wz?itbAKC;C#fhVx6&-E1jZ%a)>h*iv*aTZ-;uOVRyoDSCh{MGvy2=piLqO3{ z0*d}6py(I@MaKy!^0M`^9YqlWipmjC6eXZ2g@7WTfTC0aiUI95oL`Ev*-})VEkzaBQdE&GMU~i6bOKw7 za@bN-nJqKv6XUimDS(bRq#oH3%p=iGZS-1QgXGpr|$hMRf=$s!Kr8$pjRg zLO{`}1QgXHpr}3pMW+!^)PR7Zh6EHfBA}=-0Y$llP*G-fv|@%S+T*_Kn3WyA(tq4N z7B$HZoG+)SdA8poONv@>ekp3nmZDZ{DQeA@qBd+PYRi_Q)7esV23v~Sv8CutHj3I4 zP}G5dqK*UTZ%4ZOVMz)6pdg@Q9fIWMzW=76dOgO2`DNcplA#MMPmsl8b?6U zcmj$h5KuIcfTBqR6ip_eXbJ&EQwb=VMnKVY0*Yo3P*g}jQ4s+}GYKe~ML^L-1Qg9C zplA*uRCG>u^ezJuf89M64V9u#-M1j;W(UrfQ*>#z|4Ml&x{UKn(R{WPEnrL0{eEk#$drD!o*imqa#XbAyDO9?2tnt-BZ1QcCEK+&}X6kSI^(e(rrEhnJp z1_Fv!5Kwd@0YxhbD7uM&qMHdQT17z7Ed&(ZNbFGcsVrRYAk6y493q6gSg^dMV`9%4(;!)z&f zge^snvQhLH0Y#4!P_&MKq9+I_dXj*mrwAx|nt-D91Qb0(K+&@V6m1}&=s5z4o+qH_ z1pWIa0YxtnQ1mhZMVkmHdWC?Z%>)#^N(dFL$&NNOAn^w7Pw(F?MLXPM(U$DM z`ErW3W&3?{r05OKFGX*%rRXiT6m4fq(c5e(dWS7V@3N(62V08XV@uKdY!vMzplBBX zMIR7Q^dSL7y9p@zh=8Jx2`Ku6fTB+cDEf?mqR$B^`htL>F9|5xLqO421QdNuK+!h@ z6n#rT(RTzCeNRBq4+IqLC4`Dz&yLP8An{%9mHt*K$~HVH`?3S)%PIOf+h0*dihkkz zQuHfZiVm=)=r^_$9b`+mfTDnaq8I^1X#^C-2`EY@peTcY zqD(@l=*R5n1_Kh$c8^6rNzp|26)mfL;Cwkn<;(jYSCgU&oL`D6vZbgJTZ&F#OHmG6 ziYl|Es0v$(sycK+(wr6rDmq z(WwL!)gz#&J^@9i5m3~CfTD&36g48Cs4)RWxdaq7A)qLafTE^^P*Jjc^q2vOU*o<- zlwCf2rN7!e7Bwp$IA2attMdLyHKeFD=a-^3Y$lUO(Le%<1`$v+n1G@o1QeZ3K+!pbP*IEW(Jlrg-pRpfDMcgPW6{v^f%D}Q z4J+>#)RdwNIKLEK$d;nvY$+PSmZE&N6pds{(I~bQjb=+x0b7d3uu(LYfTD2(6pbgK zXaWI66A37qL_pDG0*a;(P&Ac*qG<#aO(&pe1_4Ed1QZn!P&AW(qFDqKT|_|9Yyyhr z5KuIifTD{DD4ItI6`fZ;y3~Ng3*4W(K3|HKx-V~+ln(U zMJos>x{-jQl>`*sL_pEa1Qe|zpy(C?if$#K=r#h1RufQkI{`&^5Kwd{0Y!HaP_%{+ zD!QzEbcX?n|7$a4z7(ap2d2Br2hNw5<&{gRlUD7Nh?ltEeq`$<-f-X&KiW@hV~I?A zHJ6ddwWsFE#DGlCtC(1s@Vv^2PqRI*dZJcE&#RdjdxGcHO*~rJ^Xesjuj+XX6KziP zye5guPV&6wiPvg*Uh719UC%osG2j%>>yWs)p67K*e14kebx+i3`J=> zBFTSmwtFCw?0l=;1(D>E)pj35lJDMOcS0mtX^q_rk>vSn?QV!9*W7FOLnP_`Z}xQ~ zN%y}auNO(W|DSZjNYecefty5M;{SMy1(6ebR_Bi zdg5`Br2G42Cq`Z`ws@zMUw7Md_NsYx<9hJA(C`|=5k{s>Hg5%rbyELsi!TGr2Atl+agK# z=MJ_UMvi++D~;t*8?Cbz7Qfr|_IoeVMsK;(>0!U;|z`Q5gY9^ zqVCep)L0j{(OzSWy9OP?VW+YqCudbik7iZN8j_Q3Dm<@TT`xWTOiP{@J;94+wM{=g zy-j+L3ie6rEiupYTX?RdR*0mhhwl)v8Dx6V81J8+o|&GJ-r7EsSk8aESDL+7nM;jp z`r!vj*G1ZN7nz}pEPiY0MP}+E^Cyy^0KdZpY9XEAyL2mw}g4wx^CrurdKPk6xT>gxL+!+N^ z3JUWJa|@adFD#lldi>PfqN!6SjT)CfeoA5P*ioZ~=g*j&o7ZG`v*AsfG|d~H*Tls} z78^~OI;EgdLH@|`jq;i_Zq~@Xxv{z(=M;DCApE;>$c+s3`1%-{rc}B(V zs?p=86xp!fxPv-(9d1`~ROhLaCr_PX&B3$BF~68$v{}UWEBsHt{0gb|=G0y~=KjYq zl3OmtJPz!7*6?mkx_j=J*Sbmf;UmM7Et{8|Y|**oWXsli&*rUZ9XWH8=Hc7AcGmmk z**lN#J$34|Jg-m3p~E}(9o#g$>@Mys!`){#XzG}viwx?(g2IBLK{NHSTa;XlR$O?q z(yP<7l!DPU?UpUR7M*o<^SW^()%{&19wzt zRdNOFb}qT(k`L0HkI|*{#;}_}?`T&!ymjqT!V_h#LMzT{H(v1@?S|F)T9jOvT^~MZ zQ@ww)((BQ=5heG%Jt`DmfxJ>md1fhWO?YFeuDovC zHKnMyx9pP$&&LUOw-i4jg?H`$=GRKT)D}Mi>(Ni2W1fAIoXjh|smsV|rR&AL8=`cV z(z^71uzM-I@=f_HN>$~RvdSyt%I^B`ETw|DgY!D+M&<5pQ*xi!9jB{X`e?^}-=g&T zgszHj&QeNwWh|93)Y7g@LWTB{!539_&#{Z)#R@6WR^IyO)Xr3sy>e zw6@!CYRT_{())xjFz)e37iZ_;f{k`~6WWI@K4G^6Z!5V<_OYzFuRMe8>#g3OGur)8 zT-=>p{B5=*ZE_p#kVdRxhTX?H>R5lU^?gOR;g@r4(^$?jX7%f4>t zRLLh|?!xoiL$7Dg*=B^dN?v%-*V0lAd8Hgm1ePkWFVlAUh2y5qC@T39XxO+G;hkP` zf0uj>x8Hxo@8a&0VnKFmgeS@nD80+`O7HW$(mS1dB+ssF@tN(bdGV23JkR`wms;iy zExrHjgX^}*v!^BDJKFD0ohZ2p^TK=AUClC&@Oe6i-K(WHu$?-q?~t0E+q9|ap58Xj ztLdKLHfi0odCht=3MLig7Z%j7*=X{pX*1i6vRkZRcB9G7npr3sH*@kxJC2z&HNU8l zJv(k^cgtuO>^;X!o7JLG;j~7h^IBTTpD}7&JA1l3t97HvjVId^?gpa^r!^Qet!AUK zH5>J7TCTzW1+Rt`9=99JG?3E3x0T_lx$w9S;z5z`mzv zmOdHG3xO9)v4?qGtOP?^7 zK2I!tnrP2M;S>HYa96LyF;6i|pZ%42^2amG(r0@7hHy{*!W%{q!)JNLpSgQ#sb`zT zpJDjBuH>`kcUg&LD7&Ya6H6ZWcqUo;Y_Igm9;i$1@sj6~B~KDdo)4D!-BbE|p!C@s zcW~)*xsp3Bd_w4*)wy%qn)Tf8myR%O?_OE>Ry3>o~+DX54qdtxMbnMaBOU(}Yq($Sg@+lP~ zl_ELO%8@FOs*!4u>X91dYDXHom(~B}SJ{-}{dT>CYbenma|_Dq>yQO~|{Qs!6Gv+v84`DNekEwkL^ z*|%WI{E8NT^wJRZ5~agVMZNN#eaEEuvvjv>dH1@p>}$`uMPA*}|I@25`(}=vr=0uN zuRGc&o~>gg9qqd#UOD@YNG*4?cdDoE?lbrP_TAg!qkYe|_}EFu{yGlP(OwZ3zkPy^ z_MO$@eVLAnbi7{2wK_gwcbEG(FY36{K0UX;)bS7d1l*3;&F+pl_PMxY9Ua@)b$7d~ zj_2EHx5w&um))FhKdR&Rb_2NmyN(U*8{clX(Q$@-3*7C?blhMt+bo^;pxc}0z>F{v3*Ku}!xUbOhC4=s6kGFJ8 z858bo9ea)o_c=OVKOx+=>-gcMaDSs?^{L^muj9z+;hw7F1BKyUuj4N>!~Ktr&1Z+Z zqmFauhI_G&o92c4Z5>lD3wH$_doKw0xjNpkFx+?Q_|X;N{!YglSB1NQj-!``d%BJf zEerRvIv%(--2dv>a(TEr>o{*kxR>a-d1biY)iJgz+?90fduzDQ*YU>H;a;QTC-zen zcmMpLW6d?;ZlvRwwc#$*@sWGO{hW>m?+^EJ9a}#X?yfps`bfC1)^W>Y;eJoY_!HsI z(Xszi;l4n}o7RVWt&X4B4{qG`-KS&i=fj<=~^cjT4u*!I=% zc$SXyUkmp&I=;R&+&gv5cr)BpbR4)n+{1NT^-j3&)$xlR;r>y_x;w+2r{jbV!hMmB z>vo6xMI8@+9Pa2R;qi>m!eb8|FaILk*Xg)zPq;tOG3%RfSJQFucj3<0@zx*0eZP)- z?8i^;_WfDMQ+^6}GaV=W67D%VK6xPAFY9>3enjQY@Bbbi&-^1i_R?|DpW$AvwCt2$P=qT@&%r|LLQ$0a)6q~ls0*Xj78j&JIi>YjhZ?1xG2Xdlo0az}gGQG6Wco{!kJ zrv+ZQtnm3^@%uF{oHMy7f27yAuxLhj9LFhpd0FH&cCY8W#v=<0y~Zvy{vWEA zHXiN1Eo$G39y8U>SA05u@c;XM4efpY>&LBbjbH9QbHDo7KU}uk{q3KR?EdB#r+Qeh zr;lC-y`g!Vh*#M{1>25-yF7Qj&b5CykDc`Dof`4#lnI=i_+Q?ySG|Z=)15)Tc)zi> z%YNM6og&5l+{bkvkB@t)o#s4t(wk_P=bZA3x6QRs_VR|6xxBc&jmx{E$wuZCV6H4-Lhr#nl;v>h|m2IPa2Rh!|d)JYT11cRj$?tHW&VmjH%UyJ1uN!-= z?6Kv@qG_q!wj7BKSke9XpT~~7e+JfG-fPQ|lv-PkY-zIVNJ^g9;Ga*tn(i+eFv z?zza$ zcjs?D@{_muNJ{qRBYR3NH7LH+pxf+TvwP0zF{is-?sTq2FFUVaYiR9hy}mqh*Mco} zZu=)0Uavh(KGO9HFCnGd#9otnPU8M`N$Ugy!Rw4j5wX!YFPhX z{d*4RF`)Zadmr~vI~*LCXXozJ{qSoQ8o7_0z4geBn*aTyN4t47?IY*8^Ze)ONJ;N- zuy&p5#n*4th(Y7dwa@Z>J4a6M!V&KHRPn!mFaCEk`)U7q_V!(NE9CZ?k?)R;dpucu zY}EZ=@v-U1hQ+r_hdO~>=El4g<3CL~x~pEd7xx}m(CX+mr`7%EA3NWIDaXcizi-K?i=Sw`=b4AMH89;N^Vcu_ z)_%*TEEsXD-v`yM|9561Kh~n{Bd@IgcyGbdZ}YaDo8BSwip2+VBYNCOiS)9^ zri?WE>h;tK?zc$kuX2&pi|hfeTqIUxzsJj!^KY)?4#ApQ_8Yl!Z9CnkviqV^F2%pn zo-jn;C~v3xRT)v7f@D=&G5<>!W5G2021H7V@4hEkE+xpY3yQkGLN3~{LPvY|=y^5m zUrj0ww$uJ~_OI0L344;3GS5z?^vbFb*x2MAi-OhmXd4MWv&Wrs7VS(yZ+kpS37)nq z>IXaR@g+4lY^Q_ZO1t=2u+UDY1rOQ#$Ah7E3F*Q7%J%679cp@BX0Xw|4rB$3YuFzK z3{JCuCxfl_p4mafzFkp1=vB)e+=CnKeJTbo*pskI!7uhcCj=Ypw#o@I>)6wtV6ArjO zb%V3)>C?%<)plv4gR|^LEeI;qwLftebhNMGZv;Qsb$&CbWM6mR3MSek==R`5`+VOH z9|wjPRz_m4*}5qbyU*_An?-e##(LS6 z*cXkt|5w2NXl#{T=8w^sZ|;7I#vZiW<>zRux7`@OL}PR8*7()lW}n!BXe??U;kRh4 zlYPA2DX}x{O7uyIwX$p7Hzjtd-TVDgVh!!W`lrNF>{14##NM!vH!vmkgB=E?#46jz z8*Kk`0z1Qylvp=2dUi^zs@((Uq{Pw;*wB<%%PRInCMEW$UD$aku{w6YoSzaKYIobP zlvqWxvo0l8WLKi1A8TYcT_r#ExLt|aeyoq(N^|_!47;$oer&bH&-|GCZrbO5tg79R zU-+>%4BD4|tghW1d;Hip_Bnjz#}?SF^tB%wZP#T-5Zi6<`Cbrv*UtWa5NmB8c4rVf zYH|2T*(w5z)zJ+{kky64hkOYOp* zPmjG}AK``c*eGLrS0eVOnOu{IO|>h3cOv$sU8S{&*c$t!?@7dJ*k#_Ei0w3J_a$P} zZCzC%*4FOLB^6@#*x8e(#%8+T4yVS(+h;p1Csy08%k-Ss>2}R#eoVhioloRt%M**?NWIk6M%ewdvTyUA|BIXSU?cJ{eBv3Kk)zBnf~+^*-m zoY<}QIb4zx`^dapniG57&VE@=?0mZ+=jX(V>?175i7l}!(P4FLw0+o)t79M9g>_mT zd&F+mE~{f7*Yv!ut78efLAtGu*{eJ6tktnDc1!esHFntEHsICRC_9YU9~)*LA%B0Y zmtEbF`(p)WV$}Xv6}v%3+uQ6a73`0-vd>}6{@5}5cw_gcoo{cOX8(O&TA}Hk?oJ%G z%bnp)++ufop*yk3u3?co;r_CNneN23b~Da$C(f|XeZJkLX~*oH7q}C(?Q$-6Cnni% z#)a<0;@b8HMBRz)cE4WXPTX!c|CR2o(;(q(Q%DEG@?W4ON5Txy} z4`F{u%1isgZbsjoxX?_bx)Z0m$6?N?5Hq5SkId@`*-Ky@#8fnAqcTtKvVYh*O7IxxV`=F`r z#9j7zx%WzQf3!Q|PIR{$yqr7nj9pcCKKs81*mX^r5{cer+rIQYYab~+x^365t#*d(rgr^K*G_lauHPBj zakuUIwbM>>+pgc4+A+87`nA^%+_vl2K|9rLyM7(DeYfrUb<(zrYA^wpG*ewq@}UsFN`XiCUHO$iyKDItS3C1i*uLeADk$T`{w8LEwt zbF~q2o;E_x*G9-NZG>E)jgSkq5i(pGAtSUAlCO=Bk=h6urHzo$+6XDoM#va#gpAcj z$T)3;jMqlU1Z{*&)DDI8h)%crKhfJBvHYH)khATv+@BOUIZntl-|;CHGF@ktkQtg1 zQm82*MVb;aQ&U1_X-ddNni4WwQ$prwO2}MIgj}qRka^k&xkMWwmue&AGHry+*G9+! zZG>E|jgW=f2w9|!kSnwia-}vx7HcEqDs6-;(MHHpZG>E{jgV#92)RZZA=hdnNvr={ zC}fsBo%cTtoE#_QOMkaLn=cl!M`x9guQVm(YfTCHMpHt*)s&F$G$rJFO$qryQ$qG? zO2|GLJnyoRHbVZD}Ty3_Vu zGe^hEPVrMBel`1kKza9S#*gUSC)u{Ay{YUPw(V(oz&_EoJuQ#1tJ}7xcKds?2wKEbwoU6c4f#NBsv)Mfwg>zNGS43H2e zV1g781ne{sMMXiei;7~wiUMSMHH6b%t58Y)n@C=R?sM zb|^a24n=3#q3CQo6rE#-qI2y~beV_V`kK`XDEdaA=v#rJ?*xjz7byBcpy)?|qMrnceikVDMWE$%d?iKY znk-v76t#3d6t%KLQENLC)!Ct_-VQ}=>`>HThoZK2D5}_@sL`gVoj_50fuh9(ikbw9 zngxnF2oxn?O-_fuf}Zih2kX^%N-TC3su3 zv_R1^LRC>#Q(8U;QW=mx0G`#>RB!2@nm@lFTeha0d?iII)?}M38;W{6ABy_ep{TDN ziu&21sJ|VGRN_FK+#}hdZ75K*kwDSL0!5n$6b%=uik7b_P0N8) z9?ze%lC2PmPD_tmY+6%JzLKIXYO?vuhoUW=4@D#GP_&gDing{x(KdD{+SU$5qwG+$ zogIp{w?okmHbpxM6zwEXw6j3bXn~?#1d7H86zwWdG*+N!oIufdfuh|6iY5pYO%y1a zBv7=wK+zroMUw@J_7o_ZB2Y9{plF&v(OyDT(dIR!TXGLuYK+%x`MMnt~9W79Fj6l(`0!8x#ijET~I$ogY1c9Ox1&Zbi6rChc zbh1FvDFQ{O3KX3tR29vvDgBiLshp7Rb(|H7dZ#x`3u?;AS5kClO}0eeP;{2_q3CQo z6rE#-qI2y~bex=f(xa)F{N1d6T{D7s3Z z=xTwYYXpj}6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$Dsx=o37euP1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq89~x6RL{tsVNHx#X$ ze^i~lUsF!LlA@1mvdagAqEDO;MW5QC=rcPMeQt-MFYHkCr5%dCvP03=b}0JB4n^PE z6n!U9^u0jQ4+2F$3Kab$Q1r7v(Jul;zX}xnCQ$UdK+zupMSltu{UuQJw?NT90!9A{ z6y;wo_RRdRF@HoozpExa8e0@7su3tE2^6&uD9VJYq7Q3I&*VTV+vJaMWFLj1U(={9 zm6NZesC6m(c3>!~b3PQ++o7n99f}(4P}J5AMHM>~HQJ%5ogIqW+o5PNo1!LxqGo}j z4gy7s3lwz}DC#6o)LEdYi$Kv50!3W~ik1{8>LyUsU7%`=6-9f}6op=dRmqSXb8)(|KfEKszjK+#$PMMDINh6)s| zEl{+MK+!OPqICs|))OdNU!Z6MfuaosiZ&7`+E}1y6M>@P0!5n&6m2F@w7F1K)VoyL zJ_l0io8J8N2}Qk2`4~|uCtpd?R;BEK)kD$N&WECH>`=6=9g0TTp=dih6m4&Zq8;o| zw4)u0cCtg!&NfA(1&VeNC>kSBw5veTSb?H(0!8Bmigptynjla#QJ`p&K+*03MSBPo zO%^EHQ=n*yK+#lzqGF9q3BRM6wS3MI!vJGaDk#D z1d5InC^|}@=xBkWV+4wh6)2h~P;{I?(eVOBCkPasC{Q$Cpy(ulqLT%RP7x?NRiNlJ zfuaQhMGFOrP8X_*_9>M<$$?a|^a1t0p=h(D=!{Z1`AUk;DP`p$q3B%aL(zG5C_3K` zMHkqi=t4UbU1W!%i|tT!i5-eAwL{TmHbs{U6kQ=ubfrMiRRTp<3lv==P;{+8(RBhv z*9#QgAW(FpK+#PCMK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZWR27|7Dy^6U zsa%pCjXgUQ?Ug?Yo84O~Ctpd?gQaZKwL{TE&WECh?NIcH9f}^cL(yY)D0YdR3t4HG!hn1&ZDf zD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDSP^c=pzf_u@1F7^%Pm+Bg6t&HtotAx6 zDkon_(PyRXMT&yMWAR2fugPg zMN0}4brUG+E>N_TKv55YqMiapy#$Ju7ARUqplDfvqU8jNmKP{mL7-?wfui0*RZ(4w z(my$n%8B`BCTI06s<-rKrq4_5)1sVwB}FT>$d=qN6b*1b6s>HBqJefOTEz}UtJ1)iq;e;T1%j4h(OU$fugkqiq;V*8YWP*u0YXx0!8Z!6m1|- zw4p%JMgm0}3lwc4P&8biXj6fr%>;@z7bqGbP_%_W(UwA0QNI?Yb#owC1sn@}`Ak=nOKIr&P8X1B<$93F}e zbUqXvWQU@I?NBtw4n>F9q3BRM6wS3m(P4HdI@}ILN7xh{DNuBjK+(|xMaKvf9V<{Y zPoU^HfuiFDicSzHI#Hl#zCh7Q0!1ea6rCbabgDqnX#zzH1d0|46rC0!6n86x}XRbcaCEodQL72^8HeP;`$#(Y*pi_X!l;FH{ws+oIIGd9LV}^z_E_ zLQ%)`aL5BK%E?z!^hk?r)h$BNqt1t-$Lvt_xE+d~utU+4b|`wv4niR{AUlQW>0{ znASF{-qL?Q-I3itD<@w`(ZDQgH7XRX;(RDt)ec32>`=6t9g0@BL(v*`C>m^sqBZSM zw3Z!;hS(Gh6)0L;plBU|qG19>>k1UDCs4G$K+y&QMH>nfZ6r{%u|Ux#0!70GiZ&G} z+DxEmbAh4}0!3R06m2O`G*X~wD}kb|g{qqS1CJ+Qkk`-*M9g427L(!FXD7wlH zMOWLQ=o*`%YXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&Zzx zD7ssq=pKQhdj*Q_6DYc0py&aCq6Yx3Kab%Q1rJz(LVx3{|XcpYU5@* zMMZ(48iAscKv4^UqD-KuR-mXXP}EYOsFgrbYk{IVfueeWqBa6W4MJ7XS6OLZ4y3Y7 zQuK8wx-)%r-L|%zd?iKgYqP7zhoZ%t4@FIOC~CGtQ3pE|EpCURj&>;OWQU^8b|~s% zhoU8Hinj@OC zFHp3BK+%Q*MH>keZ7fikYH6|GWRT6|)z=$Z6RY}HWoMY;=eyV`Q{l@#q%o2|BcDB9WiP&C>OMZ4Ic zXp9|-cC|y%SUVJrvqRB%I~46^hoT8KMH2;zCJ7YnE>N_GK+$A@qCEwQrU(>G6)2h} zP_&mo(R6{L83IK!1&U?~6zwfgw2wg1z5+%22^8%wP;`Jm(QJXD1BI%h9coKE=RhiV zwaww|7>XvQr>q@RTTZ@`qC;!5gC~cgxz2~8!|YIWxE+d)utU+2b|^Z^4n;@Xq39Sp z6dh}aqIot&#|ac2FHm%XK+%Z;Me_xUP7)|OS)k|?fud6dicS+KS|CugP@w2^fub`6 zip~@$I!mDFY=NS41d7fTC^}D|=zM{q3xukoIklyWav+r-($_CKBoxg~Zca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>py)n^p-%;+X6-J z2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&nLyF!0!3d46n!aB^p#Lm^h9l` zUk;>lXnGv&$xw7yDIZ_gmXoif==<7iiy5Kl2j@f4k9H{f$qq$7+o9+eI~4tDhoax? zQ1rVUivF-e(VsR&e+d-*El~82K+(SfMTK(QY^SIwP*fvOR1zr4pAu1h#Gax|pr}@$ zs4P&_QlO}nKv8RfqB?=1dV!)g0!0l1MQsI&Dgs4~LRHbXwWYmtAeD9VFKwND7m9XI zpW@iATu#1{qULh8U{)yV;Cv`r+zv$@?NHRo4n>{qP}Ic^MN8PBsH+`{mb61rH=CmF z0!2#+6!j1&>M2mvOQ2|Jfudyuik1~9T27#7d4Zx81d3J^DC#Xx)JLGGuRu{hfujBb zMJovu4G<_=S)gd3K+!5fRncPQ(p@=_%G7ihQB%2kOTSlokG5*LoO~rkYm~FM_X$OV zoexE8+M#GII}{DEL(xz>6s>KCqIK+0G|Ub~>)N4cJ)5HS1&THhDB4h}0!0T36dfc`bg)3t9HFXc=W=Po97yGY^f=n+Q1nQ* zd>m3PCtpd?;pJ@7>`-)s^P%WSI}{ydhoYnHP;`tPijK8I(L6g89cPE4q9@Dcb%cV|-ZYcWM`B3zW9g2RnL(y+`DEi$FMSs|#=ubNo{bh%uzwJ=; zk4@3P0!4+Eag&>(qCioNKv7AcsD(gLCQwu>P*fHuYAI0EN}#B8-bz* zfugnoMHPXfMuDPs0!8fwiWU>9ihd}UcFBQM%8Tc4ehft~r_X9^YFSRclA?|+vqKIK zMV*`vMV;+X)Wr@(OW2{Ps~w7#v_nxhI}~-dL(x)pDC%KT)Kj3Smq5|d0!7OR6fG-I zw46ZE@&ZLG2o$X-P}EzXsE$tw7NzfuijMinbRh+CiXbM}eZ91d4VRs)`1;EPa&&shpo~ z>8}}zI;JtYWjXmuipI9g+8h&##yKB~#@nH2H#-zfutU*AI}}Z_L(%SbDB8mgMU(AN zw5Ltc6oI0t0!7mViuMvHnl4Z@L!fA;K+!CLqP+!*_7N!BSD*zLKJ=TV|&pABwJVJ``PRhobB3P;|W= zif*t&(T#Q}y2%bjH`}4;7CRK(YEyKZK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c z{Q^Y~2oyaiQ1p;M(Zd2oj|db!Dp2&8K+)p@MNbG6Jt`?To9g1GFL(%JYD0;&V zMQ_@n=q;O~w*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiarr2`c$CkGl8Pd1&Y29 zDEd;M=qrJuuLX*}5h(grpy)e+qVENYeh{jPo@-fZF+W#yWP0B9^P%Xy^pv$9Tb7fr zr0Ca{S+A2r(QnR&qTlUM^oJda{qRogsP&STb4G?fm9ZD%i;VIiuOnkhb-QzoO~rkU0P*(oEnOja6S}uwL{U8 zb|~s*hobIwC|b%6MLq0L)YA?{z3fo5v`x`60!7OT6fGxEw7fvk3Iatd3KaDgDC#3n z)K{RWpFmN6fufZJiUtT2tt?P9P@rfPfudCfiUtW3ttL>kxo^~ZhS{NLT{{%5XNRKo?NGFV9f~%z zL(xWdDB9Q#MVr_Z4HqcdRG?@xfuhX?ibe<&Z6Q#!r9jb0fugMhinbOg+D4#gTY;ic z0!7;i6m2h1w1Ys=jsitH2^8%tP&8VgXcvK^F+x?*kXEHvav+sw(>t-Dp=kU3*Row( zm6NZeXt!3`ucwEi3C@S2iFPQOWQU^N?NGFb9f~H~p=eJ#6iu;1(NsGWO|vQ5OQ2}F zK+z0=qL~6kvjmFv7AV?BplDx#qWuJl_7^BRK%i*0K+%B$MF$BK9V}2ZN1*5sfuchN zislLw9VSq8xIobnLRHbYR;4ay+b}3lv=-P;{X{(M1A97Yh_!B2aXxK+$CaMVAW{T_I3(rBGFL zbgR;?IgrYF>63?!2}N0YO#iA@<>V_Vx~^3=_nc64z4M{y20IkpXosSk>`-*G9g1$T zL(#2vD7wuKMYr3b=nk8rI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaWmiXIXudRU<7 z5rLvd1&SUMD0*C==m~+MCk2Y05-56Fpy(NaqGtt)o)fByu4z@eEC*64r{`T?8;W*L zik@#(PQH?&ms@3zpBIW=aXu8iYKNlN>`?T&9g5ztL(!XdD0<5dMQ_`o=p8#0y=znS zo*rExwE{<1^S-*zba#|}mR+M%e>I&Qg#qM{v&YV1%{vO`e|o1#phs8*n;EKt-^ps1BV zQEP#sI)S2kfuc47MGXQ)Z3T)d0!57iMePKN+6xpdCQ#HQP}D3?)Ip$Vae<=ho%qD=AvCb++}zp{Selp{TnZik7lNQ4c#5^|V7# zFFO=1ZHJ;|>`=6<9g3E-DOz5jXa#|y6$OfV3l#McDC#Rv)K8$Ozd+GS0!0G^idGgV z8Yob-ia^n-0!4!aidGXST3w)M4S}M;0!3>I6s;vtG(@N>TB3Dn{~SoAoW6ch*Vffr z`uC?Xv~@Z8N{ZHPot=4UC|b|?P_(`siZ-xA(S~*?+Q<$?8{4616FU?Qw?omUb|~7+ zrf744q7ec`TL=_wDNr<0plB`*k-4n@=KP_&mFil*D4XogMEOo5_V0!4cZ6zwBWw68$X zegZ}N3ltq7P&8Yh=s3P@3 zg`!^RgQRO)my@rg=*HIBp4Wt;o170tH`}4;7CRK(YKNlR>`-*O9g6O-L(!dfD7woI zMR(g2-6K$RuRzg#0!8-=6g?nN^q@e|Ljpw)3lu#fQ1qxk(PIKdj|&t%AyD+BK+#hI zMNbP9JtI)`tU%Fo0!7aY6ulr&^rBEzbbag6NjZ?pLFvZ*4Wa0Or0AvA<>V_VdaZSK z<8`6vb>~CT8+Isq(+)*%*`erdI~2WRhoX1wQ1qT1ir%+F(FZm~9|{zGBvACRK+z`x zMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&c93KV@OQ1rb((GLPeKMEB6BvACTK+!J( zMZXFZ{U%fuz0$h$S`MW0aQd{5S3^`+u|hoZ7gQA>fMRsuz>1&Znfis}W5+6WXi2o$vyD5?k) zH3}596DVpgP_&ppQIkMXvp`V?fuh9)iaH7ubrLA*EKt-%plAu9s_4(wrLH&Tik9k; z!}%)|%}sY6b*(EWUrEtYb=i=cLs1XsLs3sV6!o%0(b9G(TE-4V%i5u6IXe_BZ-=54 z>`=6#O;K-wqCNseeFcj82^94gC|XINXn;V`$^u0L1&US?C|XsZXplhBY63;83lyy( zP&8PeXib5lwFHWW2owz!C|X;fXdR)ds9RlWTn?miUbh@h_qysW{XfzdGa6P`PQH?& z4eGMPZw*BoIvD#+M#Hc9g6n0DcVP%XkUS%{RE2k7brSFplG&0(SZU*2MH7% zEKoE@py&{RqC*9W<_Z)YCQx*^K+zEbMMnx09VJk7v_R1@0!7CP6wMQ=igvFneU}5N zyp}%0dXG@_LjG&nadqY7D=C^^mo?rMicWGq6rF5`qEqZpbgCVSPP0SN0y`8fv_sM9 zb|^Z-4n=3$6rCkdbhbdzIRZuJ3KX3uP;|aP(FFoU7YY5GZ<5py(-qqNfFlo)IW|R-ouPfuiRHie3;X zdQqV0C4r)s1&Uq~s)}x^E6vV2eJ)V+g+S4l0!3d5 z6n!mF^o>B#w*p1q2^4)VQ1pX9(T@T}KM555EKu}|K+&%PMZXCY{Vq`Shd|MvLRHc0 zb)^S#Ae9@_-PLb|qFuV?a!0Y2t~#ExFsKoYV1%{vO`e|I}~MhD5|wX zQP~bfE$vX$$__=XZHnpyis}W5+6WXi2o$vyD5?k)H3}596DVpgP_&ppQIkMXvp`V? zfuh9)iaH7ubrLA*EKt-%plAt!qOJl(O9~Wq6RL{-sVlX7Fjv$i-Cy)?D5@k<-RsNA zS5nlgK3neLP_(r3p=cR96fJ9qqUG#Rw7eaPRkhGw2DB{sscrW1d3J@C|X^hXbpj)!2(5V3KXp+P&7oKXsAHZ+5$!E z2owzyC|XybXg#5-s7HNivm8ieNP0?9&-&^u{a)#z+4bwo$yZXeaeX%R(NMIB^PyplElYs%XRd z(kVHR%0cNaqK!h){Pel8d(@YcucT;deRlKXp=g@(p=d8V6iv57(F{8j&9p<&EISnK zZHJ`=6?9g6m|DcWD4=m3GD*#boe3KShAP;{_B(Hw!ILj;Nr6)2i3P;{6;(cuC` zM+g)hDNuBjK+(|xMaKvf9V<{YPoU^HfuiFDicS!!iuSB8y^#Z{?2(>#JtY)%N_QTe zSYJ-QlA=@Uvp=5XZEwn??>2@eO!wyAf+M(zyI~1L5hoWb2^2jp zQ1paA(USs2PYDz~El~7~K+&@TMb8NoJugu7f0!3d46n!aB^p!x-*8)Y~2o!xQQ1qQZ(f0yHKL`~4 zC{Xm1K+(?vMZX9X{VGuOn?TX;0!4oa6#Xes^p`-<-vUMd2vtRI)t9cyfmHrZPX>8A z6m8Z%AOF^uldq(x)Fyj6zdyU(I{gY+i#GrBmVRc3qFOr?mF-Z}(hfzf>`>I&4n=i# zD5|$ZQ5&1027#is0!0;pqDFzDb^=B11&S6EC~6WYY8EK!AW*cpKv745qD}%uodt@z z2oxV_V zTDDEr{^d}#ob&OvXn8vntzd_u741;e+YUv2>`>I#4n_U!P}JWJMJw494G<_=S)gd3 zK+!4!MXL%F4H76?O`vFXfuc18iUtc5ttn8nmO#-Efuf-TMQaNbts_u0OrU68fui*U ziq;n>+CZRaL!qi@={BW7IgrY(>Bjvsq3Fz{XrngekwL zw2MH|7=fZ)1&YQB6pa%o8ZS_^n?TV7fue~5MUw=Ib{8nxL!fA~K+&E;RnaDGN(bdY zDp#iGT@MdM52X*1rnD(1UrEvQHrctahoTwIhoYHwD4J!5qP^`7g7*Wl(zavsWnkxlKM!Zc|Ra zlA;A|vX9>kMGKt|MW@@L=nOj)ooR=nv+PiGwjGMju|v_hb|^Z}4n^nN6kQ-tbfG}e zMFK?^3lv=T(S3F(y59~(57?pTK|2&ZWQU@M?NIcHP0^zQMUM#-JuXo6gh0`g0!2>=6g@3a z^o&5!vjRoW2^2jqQ1pU8(Tf5_F9{UAEKu}{K+&rLMXw1Iy)IDnhCtDq0!42LRYiBS zDUHa1R8HuS!?`mQU7sEfdAm(H`AUl3ZMW5QC z=rcPMeQt-MFYHkCrA^US0!3d76n!I5^sPYAcLGJ<3l#kzQ1qif(N6+JKMNH7B2e_J zK+$gkMZXIa{UK2Fr$EtP0!4od6#XMm^shisp&@RVQ&beHir#HgIxPoMIW#@J@x4&g zCOsTd(@;*nlA_v%?A8xLQQ7%W)Y1+`t?W?L+73l^b||X1Ls1($6gAkPsI47}DmF!p z0!8fvirNblEhbRZBv8~WP}D)7XmNp}jsiuU1d2Kf6m=0OT0)?xt3c6`0!7^finN_F zK+#}hdZ75K*kwDSL0!5n$ zRYl7+l$QE9SF|uabhdmb>YpAC8QxG%zLKI54cV|yL(vw_hoUX*P&CpGMO)dSXlpwZ zZDWU`ZS7Dr$__=_*`a8Ao1z^Aigpwz+DV{jXMv*80!6zB6paxm+Et)vtU%E?fuivO zMY{plEl2qCEtPCJPkpDNr;;plGT<(KMl|XtRdW#2iSabJrZs=Ao#4 zdIV&zhH~``V#sKRXodZ-=4->`*k@4n+srq39qx6di0+ zG)JK55P_mY1&Zbh6dfi|bhtp#5duX=3KShBP;|6F(J=x=#|jk96DT@Ppy+skq7wv) zP82AbFHm%nK+(wpMW+Z9ohnon&1fiHlLM*LrFUX8L(#^IZm>0!ldq)cjE3ylFGJCp z&WED2>`-*J9g5DeL(#c*C_2v$Md#b0=mI+wU1*1*i)@N67AU$zpy*P8qRRw|E*B`e zLZIkMfugGfimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n*@q(7AU$!py*bCqT2+DZWk!J zL#QfR*iiZ@2U7VaJ@5MTP_%AMKJIKNCtpd?y$xB@H=*c0=R?u`b|`wl4n+^zq39ty z6g_N*qDSmd^r#(*9DK+*F8MK1^xy(m!h zl0ebR0!6O~6ul}?^qN4?>jFh@2o$|3Q1q5S(c1z=?+6sVD^wNT-B4OR2U7VnJxTVS zP_%t1AMZ7kldq)cqlRpU??TbX&WEB;>`?Tn9g04)L(%7UDEh(3d ze*}vD6(}mSjhpQh6$OfF1d2)mMJP4_ps15TQD=doE&@eM2o!Y{C|XjWsGC4hcY&g%1d4hH6!jD+>LpOLv_R1^0!7OT z6fGxI6_wkT9?5}Jj!SnmwrpFyrN35s#_aNK%gI+#)TeFs=})1kuk)d(pB;+&+o5PB zI}{DDL($51C>m&oqE+lrw5lD72H6y?CQ!7xK+zfkMS}&3))XjOOQ2|oK+#ZvqO}Ez z))6QgCQ!7lK+$>vMe7R`Z6Hvzp+M0_0!14O6m23zRy9yMI6(|}fP&8hkXg7hP2?9kE1&SsK6zwihw1+^^ zWPzeR1&XE!6ipQ(2?9kY3KY#3C^|`?=wyMSQv`}m6(~AQ zplE?W(L$lBXz#YAg*lMQ!1PXRpHMVA-Fb9++j8=i6rJ5RyZz5lbdK|(=v+G#oo9!l z^X*V{fgOr2v_sKFb||{o4n>#Pq3BYZqRRw|E*B`eLZIkMfugGfimnzYx<;VrT7jbL z1d6T~D7rzQ=thB}n*@q(7AU$!py*bCqT2+DZWk!JL!jtRfug$vitZMwiq33XdM5`` zSt*~{S)u5m^g+@+ZOh45QuILE?BBmb(Sy#1qKE8I^spU@9hoYx!ik=oIdPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl7ASf}py*YBqSpk9UKc2O zL!jtQfugqriry9|dPkt>U4f$a1d84lDEdICD!Q+2spmhrqRZ3cX!nPrR_TMJ58IZL zucYYHw%K}xbOHJEu0L}=6n$=oqA%=F^ran&zOqBn*LEoS#tuc_+M(z>I~09yQ}lyC z(T@T}KM555EKu}|K+&%PMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N%zXC=1cau6Z|4V97 zq^KxRR3lJS5-4gRP?QN2)e01qg{q>D+m?3EfmC)+-#7M?P;^#$_tvsfPQH?&`bu_e zO(<&Pd?;$LLs45h6jkg{)M$sIc6KOgZ-=7A>`>HXhoWYiq7DK@iwhKW6e#K>P}EtV zsEa_+5&}hC1&WpwDC#Cq)Lo!xDS@IM0!2Lqih2nYEiF*Aj6l({0!7OS6fG}Mw1Pm< zib7RU>q_am97ttG`cSB@QoW_Wb9!jDccq+sB}M%!+4C(z(MryTq5*a&TG ziXDnpwL{S$I~1*EhoaT(P_%|k(O`k1H3f>+5-1uXP&8DaXl;R_bp(or2^6g>P_&*v z(fR^K8weC_C{VPKK+(nmMVkl|4HqcdRG?@xfuhX?ibe<&Z6Q<@^{teC$$?bHrpM9x zg`%P9(bz33<>V_V+NP3qD2JkLoexE$>`=6w9g4QML(vX)DB95uMLXG{XlFYVjkZJ4 zE;dDD1d4VQC>kqJG)|ysyg<=z0!0%9iY5vaO%f>DU7%`-*59g61Kq3AF>6di6;bc8_Bkpe|W2^1YIP;`ty z(Xj$W^8|{H6DT@fpy&jFq7wy*<_i>^Bv5p+K+!1zMW+fBohDGUK%i)$K+)*}MP~>U zoheim?N=!snggjk*DZ&$e<(UA-Fb9YrJQ^vMdwwr3+qDB`Ob%;3+zyIp&g1YvP03u zb||{U4n>#Rq3AL@6kTqIqAP5Qt`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y z=w^YUTLg-36)3t*py+miqB{hN?i47xOQ7g(fuef^itZICx=*MoI;T>4EC*8AJUxtm zZYWwieL~3nm2&cx6g^zYK5r9>9&tVtJ!*%d$Lvt_xE+d~utU+4b|`wv4nN(Z@nn(SwyzLqo3U)pQrpL!s!{^l0oSm2&cx6n#<2 z`c^{Gm(GWxuk29twH=DSu|v_fb}0JJ4n^PFq38!Y6#Zz2qMvMveikVDMWEH1UR3lJS5-4gRP?QN2)e01q1&Ue< z6txm4YAsY1eO4)Ll>@1)ke;xeLh-UV>$UsirO}2v)YBCiu0kU(GErJ>`>I+ z4n>REp{U6YMa_07>R^YW#qChk(Wa=AKv8FbqAmhOO9&Ko6)0L#ps1TbQFno&r38w4 z2o&`cDC#9pw6s9cG6F@*3KT6TP_(>2(Fy`ZD+(0#7AWc?P}EnbDr(bMIwJ>Cxirh+ zG&ELk>Gw(ZI`(TUCtpd?%8l8bi-n?r&WEB^>`=6-9f}6op=dQb6s>NDqBZPLG}sPB zYuce`Et{et0!2dwiq;k=T1TL0m_X6G0!8Zy6s<2%w1Gg;h5|(!2^4KCP_&6a(QtvH zO$CZJ6DZnTplF0Z(G~(lTM8776e!wCs47~ivGiUJq_S$daX%mw{gV`J-B?b(lA`Sz zvtox(w7v78Xa_qK?P!Oho$OGwvmJ^?+o5O|I~0wvL(#5wC>m>1G)|ysyg<=z0!0%9 ziY5vaO%f>DU7%z^Py;t9f}UIL(!pj zD4J`BqQmS^bhsUgj<7?~k#;CL%BJXOfudssijEa1nkP_noIug>0!1eX6rCtgG+&_T zB!Qxn1&U4)C^}W3=rn<%1p-A21&U4=C^|!+=uCm4vjmFH7AQJLs4AM>Sel#zseDn+ z;T#x>-c94&#&YtN6kXVu9oIP&UF3Wyy4Vgym)N1`Qacn~W{0B7?ND@u9g42BL(x@s zD7xCF=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&Zzx zD7ssq=pKQhdj*Q_6DYc0py&aCq6dYlqVpR|H{?Jnz3X#07lfk8>5lA&8q3L7QuJ73 z_Tmzu=yB&m(GzwkdeRO>PuZd9X*(1>V~3(=?NIcb9g3c}L(vO1MK1~zy(CcdvOv)* z0!6P16ul-;^twRN8v;dd3KYF1Q1rGy(K`Y~?+O&XCs6dhK+y*RMIQER^Tu-Wl@xv5n04$HioS6^6n$%lqVMcb z^t~O5ey~H)k9H{f$qq$7+o9+eI~4tDQ}mla(eDC9e+U%)DNyv6K+)d4_2^7@}6txkmioR?tt(60* zT-un!`6?7GOb>@Nv@0iHNm09Y+32N0QG4e@(PDNeYO+I7vmJ^$*r8}~I}~-aLs2I? z6m_;kQ5Tz{B?OAP3KT6VP}EJJsJlSXQUXOi1d4hJ6!j7)T3VoJ8G)i@1&WpvC|X{i zXa#|y6$OfV3l#McDC#Rv)K8$Ozd+GSLRC?vUFonKNM*}(uVZ7o>Mi|qay;39cID(N zDO$B%c5%;8G|2f-w3;1?R<}dZ8g?ieY=@#X?NGFq9g2q7p=hWbiq^I%T1TL0m_X6G z0!8Zy6s<2%w1Gg;h5|(!2^4KCP_&6a(QtvHO$CZJ6DZnTplF0Z(G~(lTM8776e!wC zplEA>qHP3?5Ga}`P&7%PXm^34Jp_s-3l!}sP&7rL zXsSTbG=ZYM1d65$6wMGQnki5;OQ2|Pfuel`iuM&K+E1Wpe}SR{1d3)0RYlvkD^-?B zZ;R3s({>0&kEPFQJg{9k`AUioX_xh1E)*T=d?=c0hoZymP;|H*ijJ^D(UEp2I?4`3 zN86$37&{alYg05&py)V(qT>aMP7o+MQJ`qPK+#D8MJEdsogz?lszA|c0!0f1iWUkK zoi0#xhCtDo0!3#D6rC+lbdEsLxdKJ!2^5_#R23cEuCz@Kq;gR{vpJ#Y>hvYCE@)Ry zz6y&KYO)@!&R?-uXzHDR)Lm%WJpXdEEt>YqA0=tobaMWVu)gW${DZ1W)2sQLv&EV^ zHx~+vH;u_rc4@ja|B$^~)7SY&Sv{KuDQDkT_~*Fw8^rC z!l0)4%NGiRn_gY9P#D^@MBhST-KMeq3xy4vE+0@R3~%~&V4*OgY2ctjVXLMCRxcDr zHQhhBP}s4lJfu+ArD@Z(3x#n_Cl4zWCN{mkUZF6#X~_)>g=tOWH!c)rHeETqP}sNW z`^^f4*-fi%Q7Fu5I&fs6a9GoWTNesPHMJU5D9mfxeEUM-#HLesEEG;@dUNMOVPRAE zF@?feO%uiz3g!edR7W)})iHC=m9q3~SO&vOcemzvg?TPVENbjaa_ z!dp#`9$6^7*VN{iLgAyPk@E_L&zep@zEJq8>D?0xh3}erom?pV)U?N`g~D%5*Doj( z{%Zd9^!)W-Y+m!M^c30Vx##461I6aY&&&S`ip^~=%>NFG&0Alb|0NWg&%8AMTPQZa ze|i4bP;6f2s{HSv*qpwbea~WZ`gY{Y7Ms)elU}jdoW3D&zhZOxj;<>go71=C98_#h z-&1jLu{nKHyrISBv+v9QLW<4l+fr>+~r*F+Ls@R;q zw*HRA=JdtUcPTcfuWmiA*qpvR@x)?t`uehyi_Pf^gib3qr?2ohv)G)zMBl!}=JYkz zW*3{&7s;AaY))V0=&)jQ`Z6^~6`Rx78JSmXPG2bE#A0*$O#f4g&FNFM7Z#h-=h~iC zY)+pnd0w$OeYV?0#pd+sN|zOz)90I9Rcub5FmPS5IX&b1rebq?%I#6zY);QRc&gZ(9york*qk2ud#Tu*9=dt0*qrWrf2-J>?mT_3 z*qrYD`l#5P?!Ne}*qm;EepPHvHz2+%Hm8pOe=0Vocj3Pko73Cizlw#{0~+&xSQl0Q z$#t02G5^aPP}jbk|E1>t{gi(IP&{j4-(q3$+4;Y!;(#@l$$urkw`9?O9Y5=ww}A~O zq}6e?hJ36NV`v(y#u$_T^D7Q&$dTp0ZG8UXimS!1^z53C)nnA;|1yhf#Aubq;21;m zFIiq(GsYK7^&INDDXQKY6rzw%D)G>AXm9 zL|V1bDYsg-r{ILAuY8&r8_nt#%FS@)QAN*Y@ zbonhm^Lo0xoX(;@?83Mzjo&@?)#&_eZR023fB15KB>&U?(Q(}1MQ3M@cwyN>r~GZ_ zq9adwdDp)^=hg!jy}V0~9-IFpKXT<`E99@c{OV8nXSWUW*H3u-EgomqYV$F{3m^oRfK$;&UwUxoQ=?!Gflxoh7= zFZ`;xuReWXq0qHwxBLxH{-d_0RNM9HoNM|~o8{x7{5?wgQQNE3y6Z~$Z%IFDOZl%{ zoWGYzKWaa%sqK1W{*&~h_OpDPn;%X;YFm_Q3&qA_uZH$@rH0N8TX$$IRyq_4H9ZS; zb!+9RP$)GQN)4;mtx>mH-A3*6H=6M)=`P5Dg;Z)=6iW?j)z#&{T>WjuJeHTuPj$&( zT+2m2$qI#5i++;-%V-@Jm{l*Zu5JFJ(&f~*FV@xl=MvhqDU@1zxpj4I>gwwT<(Jpc z;eY(Dw)yY+uWMI{8JFD{7n#p=rP{?sF8bB~Tx9#W$oO50<%hEWT#u$U`JXbq` z$^RrB`V@zB^ir4UxKaDYV!PU*i!WHGV|pQrXa9ALYC7DyPX6lbxblCs^jhh3^r6N4 z)!x5-I??%bvdJ9w7CjD>cML!*p{+He`wkZ5q9C5CLUGksgG5;@r!cY8{e%F8h_usod ze?wX-ypaEnn&O`gZ3@Nwzx?;+KZLWTVH8-)+pS$umdK+;7_W8GR-uyE%k$lcvnfN2yTA`Hdbs zb5My?31+|oVD95%lc*QR?o89!R@p5wfWK7zO~(I`}SQl+I7#`FPT!-ZqYCG zE7Y_oHf43`e{Hkw>3?}&H2dVgZKbR!pY7J_optMxweRv@2VKBY|KkF>{r3fQTXX^W z%juhS%dgTB`RpDq_W#?d_W29xo^@X;YuEX|&Q|{*|3Ci-*(O>0jndW6Uk{6}QTzO= zR4;qEl;e8+?_TzVMVFJmt`_}iUFz`vhqw0*kD~nBw|BFd%qBrunt%mEQ9%V0Ix0#k z1X3V{CK@`Z^rj$E1jOD^QB>@`ixnGU#V%sU-mqiC{(kP6>)dSk`hA|~kKgg;IN&qa zxl`{sr`)rf?EltAZQQ;%$ZLIw+swYnJ!MxnAow$=AXq+2*))upRGSY1kM$9bD0FULy9- zqC>rCY-zMhPTC;5`ju1z%sbipsj`+JfrBs!}&vNo8$CQ7~Gs-UEW#r@?Ag6;}_gv^5Op z)ZNCRE!?^nSLIiytU2vgUfsX0pthvM=3iYpvN$=(e{5N4xogc}9M_Tsxv48!T2WWa zg8OLY@=6+vQdl)&a80Fca#>m3;L6g9nqqBoSB;-<)h;L9y4KAJwxFoNLgd%}P=>ytrln?OQi^z=%5A*X6dC3-fDAD=Wfw>XV!> zuP|lG(yAeK1?E^$X?3_T+A^G_n^~~i>dHzh1|?fIBD(yd@rovjZuDZCU#vRKnx}>mdP_Vk)x`#(jk6?+x!gE2v!4x1>#*UxlEI1n6NyVLh z+^H+&=qxH8T52~>1+~>-E8DS=dOivdB`32rvOBn4d!$TWHQWyAy2_!&RV8JW!**V1 zRYm{gY16#QFHeq8I@nHT+QozIbdq{L4K}ITOh}$2yCxf~Af<8K4ys>t=zGe`wj-=b z>WYUK78e(#tg;%!&agH4c7_;KJff~7ztkP&>_d&=ZYpinDr>83z>cw!veLr(vwmQy zJDDY$F0X6y0JlRuJOJ(Z8$WmI)cMJI2Zuv(Wog61h9%o+xV*B;?GAUI3}?|bI6$UM zpEfDSPFex$&g}DSfN8A_t1Ig-Q|`2%d`;)ws^YTZ;N0vQtGJ;@;huKeY&)~GBy5y$ z4SJ?5B{=W6o#W1M!PQJ_*}xkP`nvqW!rH3*LY=~r>odTvbHnm&Lu*RQi)}9j^XQ%2 z%Y`Wm9Blijx~kAT$}g-b9U5M9dZt|JI4JGn+`l5YFb67hvr*hYeuI;H>Y1VbjFnfM z+;eU)xtbEe_PrhBwYuEdYSxcn3oWS1w@bPda!a(mlX?hQQ*pX2tE|>R+&j5I+YMn0 z7BEm8?C{w~PntGie2(>dXC)Wse6B39*_kBur|9}qKw)8J-2gi^B`2V5$}5Y)wYRH& z^2Ng9va;H;{3?^Ye`&S(>@HPo2v%{-hwGSYlLwpF;G|t!T@YNZ>#7IXy-7Hxoz6J1 zr7W_%*iKctX<2IeKPwGvCoeF|OIB1^ak&)M(#8@ zo3f(H;6$3dcxWGoyTnd1+Ld{Ex=7hYJK2C7>$!DBLu%@Z287q`h8OvsDdX!rRc>dZ z+N$7k6r2l7tU;;=*jYF@(*^$}EpX>OHW8)E@<+HkNnL(z$j)37=S~}!+r3*PHFeiU zG%z-){!Tjp8B*?r%k0po*MX(?&o3{}uV1E(>$4#F#XTtHFr*`XRV9w;ZQ^#7J zIA!{nIi2n4R$n_MjCa7soH%1%kIu7abRM7A)5w@v<0kjD$6fP!cb?j1sy#3}VEpVE z2TYui(|J-(=gO`*o$WbF-*L7AohMG6FnjixNfSCxnJ{hAoXLH24TXnXXD5y&*OqgR zo<6PfY8T&>^bdnRbX3+ATmq zzV(uHPIb$)8~ku}d)13?m-dh~?2Wj-g1a*)wa!3z4-sx>AluPp)2GkKiv*?Xf2>P` z>vMzK-g28$LFMrOn4+-EPXBg6b*HDGZNgJ*()_&Kt|{i{<=SyzTa(u-c_y~zPtLTy z&D_mfof=o?g`cB$T_ue`YHoR_hw>eFyb5HIj%$gO>)B0@x zvNGXWyQ;X*t<{J~<=i<%=3L#N3G+**jh}FQIH`3;gMo%!Sa%hwzZbKPs}4uk5f2)| z283KsIY4$V9SnpW$N=Rg#|noy@1)!m2Dh@-#3o z`mSKI58G37343oWH9Vmgmk&-Nt#!HW#w@jq?QW)Mx=^M5)?EqjY?3bo{<^!@$_jU`2rk!o|KqE6 zT)893`fn1bzT4KYH|88nn$L<<4=$}!uiDLqUSNK5Zgvr1#_mQ)%dmS~4dq!EAh~`i zEikyMazLr|3vE|a*uAkmXJCYsY#*rk+1)(XkB<~BK1`k>(pgQj8~ z+`8>_-OjIekIRxzTI?7~&NSIi%P$BXoF!jKX~?SLnt#2Y4o;19sNI@`eX(Gj?3Tv1 zfpxOpq;=U!3rmBm&)|H!_yl9wB_tfMXJDSY53> z%(BMR3^hM{ltl~Li9>^~pQg2}pObantKE6A-b**izuvsEa~nLKYj7Xk;Ev4AC+s-U z3To1ZM<)9!Xb-z33fsfFXDRLBu79qNQdd2!w8maZxtP+A%d39~kY{J+$n42>la%Zc zyIxzc0J}a11Fn}AtYH07mU2MZU37g5xrejC6BKttVowd~`sbI1kL=95hC?A?%cklJVK~{aMP6sH?Dt2LoqXV`w=-NIQO}gb=@mQN$m^R1JTk#JBQdgy(Va< z-S5Zdo0b8^lT%%Mg|Uq&(z&u>Z9qPC%4mi zqyC1nsQAC!Qo0>HqB!i;(w%E~>^phwj-}WhPS~T;@ZK$05BHoo7zm%9m*)?!E3Bx| z#U%CNajbZKZP4^(rJvC)fsasG|T4wiWsSgI~?@+3%3-umNgJ!{H z+_Wd1x^b8u-pB`~Yk0wIa3W*{l4tE?`=y-6T&Iu`Sw!f4@;VwcUg{Ihz>9yo42LJ> zG=ZN;F9%3)#i(s6Q+@ZEgFP6%sRU=OVA?YQ8rlHg_6E8@kJyO9PDYl79w z)5Xm7nF8P*kOl+cLtHmVrzkJ=*{J5~p2L^ep~tf+78-6F=Pn)WDUVqjc4)YP3KncT zAi3_rF>cqzn*1tv$7u(i-QE1RV?E_5ueK^Ld_?PJ8+OrHJ$sWtH%P(F3-1#I%TKug z=qL&AsFF`Q?G(Xnku2uzzr64PZ7>`6JTw>x@5WiOJLxyPo+Xd%)Wb1c6PrbFYDl(6 zVOf6p;FOzzu$kQ(d2YV-?`YNcC-S-{PpBModG3j4xM~efQ~87Kwtu*FzZ*!NvU*`V zga;4X!!h6lw)c*Ae#jZzdX?m--q$b%qq;Ro>899)RjnIdeca1oe}Y904sX)!5nr-h z0#EE@lmvz4MGbnY<~jQ;x%W~f~OW5@Zdjbuv$iX(&KamaJj9|s;Z~7W^blmLiK&Z9NV%^+q!j4KX#7Q@N z=vh}sZ<-mWoWloH4YHjT9*U*5I|Til>g9Fn+wfiC4o1Sc513d@!}se}5mqKB3si{{3S=_JQGryEfV-;y%X9 zkNdc8!LF^AXRPo}PG1>2CGD(eB)^ZnI>vqaH4?So35s~VJC}E{?np%>qlsUh8Ow?{ zO>Z7;5p5Z36>S~eJ-SD9&uE*pc2WDJ{D1tUqV&iQ|D=u(b05-7`HAVn#h{q`jAqJD z%s!uKzx|Z*lO9P}8XtTP)8YD$CA$=h*eAzReqzbr>Ih*hVxNFd`H4juenvXB)6!xQ z`~8rVpIF3x&m-k07O_uYr~KG2hovO9J}rVV+*Z4GZ))r7nwlTCE&T~rU9R0JPu?ld z+bJ*KDWA7f=CiE9-ExOHkq+Z^jrm_YODS&-G`uc#i~P%bqN$g$yp+q>zr3fGGUKih z_i^+rYex60Em`)*NlRR9VZUvpdYh~EyEg6@Q?l$+^7ea7!Rz0PyI(QMvd_djwcLC< zs=8kVaq}DCs?E>+^0<5bDdksHx2kSa?PvQb%YI?VnUrR_xML~Je#61-c~@;#LA6mL zY4&1US4~p49qx5^{J7dvwXbS{>R?s3pWS%&DdwQs@4E$crs`rpsBmmhb-Ru&eei)Wn<9n;_ zqk4d9o@y`EzN&?)rK**xwW>#`j!~VYI#qSH>U`D3sw-4aS3OttBGt=OuU5TL^>)>D zst>6?uKKjj}yzN`ANs`JRT#}BGIRPAIO@C@@SXh+rNs(YxmQ|+XhtJ+KTFx6t! zGSzC;k*Z@T=c7RnJpht-4nAdez%h*Qu^oeM0p))mK#CRDECdGu3ZY z-FeZq#~-R`b_sAfQ#GO5QniihKB@<*c2hlAHD7grYNhH>)gx8Ms~)R5OLe~L64jNe zXQ{4IU88!n>P@P5s@|{qsOnRyFQ{%-eMj{p)h|`QSN&D>Z&lAOeXgAvsWwyHUA3)h zN7aK=d#d(TEm9q%TBSNdb+qav)oH48RTru*Q$0=fT-A$JuTZ^C^;Xq;R3B2^p!%%p z%c^gvZdLtM^=s81Rex8F+OKiA_KB-DR^3f?FVzmJomG3P9e&U$ZSStCEmd<=JE?Y6Jw&xg zwOnK57?ump7??X!i;(f1|pu-GjK? zO?8UhbGSTT^)CC}UY8$L-C;M~E_-{0^{~CeI!JYS+c2N2`ds@kzoDAgH_Usf4z(K$ zH@|VJYxWQGjjA8n4U~KRJJpVMBjR!o)oFQQK0)=KZef00_4giO_U*>SP1mn?Sj$yU zJ~+(ht3H2dnBP)udU%-kRvn%n<_W5o7l!#})lZ7U{DbQL1H#-(b%y=EvRjW6Rqrhe z^AoCnR)jgTGOPtd!dj_%N_Ci5slI48TyB2vs5T!S=C-OMM}~Ql>e^9ZzE$Vadz+(&iRxG*nPy?;WOpH%&OQkb(RhqdUKunti@ZAzFgQhj+^nBP;~ZDyF;tB#r- z=A%`wnj7ZZRlhhc%s;DkSrFz!ROc)V^HS9Z7lrw0)yUE?@1k0=EX>uaXRHYGYSmX) zhWUNfR;Pt|AJwDI2=lS3*PIpRJ5{&Y4X)cizpCb*ALhQQ^Hzm_*?U&&R5Jt`Bo3)v=F+dAjNikA-=i z>bD!h{D*4yC&Qety5Q+BuT*{P*)YGLn(=&?o2iz)80HbG=e-=}D^%ZnHO!x?ws}3w z2dIvJBg`{ZZ+a`t_o;qwf49PI?_a7tw}!b;b>RnLK2>$YM`3pd1FGAtBkI=oAJyK!hPhaE(QjcsU3H^% zu-y2ssAl~g=9a31twZZxKT`F=v@l<-`mX(X1o!%vs_m?U=JG+RlQY9SSM@ggqZ{t^ zhg5&Ej-1QUUBh~?{TU9I`>QUozsKS7nW|6OALelRHPuG;7dl*Sty*OrL6_@PFSftg z;qtYrTkVf`xcrrBhnz6ysUFiV%*UzT(ILzatNvnt;KNNH+b^t#b_#2$>Q&a^cdy^B z`k<>`B=W5CW>>T9Pr|6aC%#SfSJia;TNrLWO;p>c9-!J=wOF-EwN7=4>U>vi`M0R9 zQ+-DD9o1dzA(|U+H`Pw6N2*R#U9I}O>g%dssP18ZD8kLBi)y}Vjp`)T)vnt1U8Z`S z>P@P5tKO&jnCeE=7gS$SeOq;_>gTFosm3GbwXIhp)n=+KRokexQ|+YMS=Da;B55|0 zgtC=jes-H5)DP3bYL9v%X?8EyN<7kK_WY@H#@JiWv**kT>tu%P1JZLMUEC*x`!qCzcp#_)7JiXu3Mm&zy15$i-Ie);oCO>&A1-8*Tqs2OErZv=#WtyyJ(VQ3g`y*Jyk+GN4H~Ki3A# zZ;A~wjhn}w-J+3uQvidDb{g;1?$LYGzk6(cZa=y8vqLjEzejA?P2+rUKSK_UMh@r@4!i%| zYwq8(s*JaAbTl&17(a}+#ef^;=NTK1X&iIy?0)Q4q`~^FPuX5~USfZIY{RC~3@gFU z4x8V>1gk8|)f9ar-R)uJT7&M~*3|yF`6cY1YZIGa@@Ml{8!wsa=VwYb81H#ozaRf) zJpSxO?=I61%CVokUb#Jc=XUMgwWkf|=H{jR-?L};oSZ(ry7kU=Bj$|GT3lRK68=?| zaK=%4a?SQQvhesIdEq&sW2Cj6QFpAny=?Q2^+Q^Gzqi-#`|73reo6Ch9(2pVTS_p*b6s9?_MmeHo>O}60GsdQti>Rk)^9t!-O52rDmU7+_Ae2x z)d#t6Xswuj*`VbEmzS;>@N~-bCkbP z?})TrG-z?@;sISpFCNHJtJ)nsXuK^i+Xac?}&j z8EgM<4F3NhC+&yB3(|fb)2_X>^BPUpZ+lg4<@ZbS2mJD6v+hA#r$;yJcsa4*KlWg( zB$8vToag4>a5yc=`)%*qzJ0Kd$BiB|dAPOJD>g-&fwM=udUx>ukHP=l##B!pVXwbx ze7CaMV_dyE`2WY?|88UJ+q&DJSz}$BcP+gusCfgnhk0CX(E9z_XV_M*&pZFi(9V|Cl@X`77+q8TFsE^ITeRNr?G9Y+mX9J+`8r|C*imGW=g` z*!NGi*~k55Hk|37Z{uhA?hjC9`)AudTO``6o;9sFFoJ>JJZ-R3sl z?{AGd!Ea_4r)PZkmjR#kKeu&$&TnD2w43}IJ7YiZXV~_>;NN6pz8GI?t#M#9ev++L z=V<&~cS9bHx3d;MC>p=t)+{#~Kf}s7(f9{8)w$95Keh+YkH(L)w!0u2zuB5=RW$yj zr3<6+>ue`q6pi0ubGg_iXd8*Fj>gOEwM(M$-);3SjmEdwf_}1O<>zR8U%TS`5{-|u z^lLQ!hHc-DX#9CwvEga)FKj{U)8eabmA{C^2iZz|8H>-b+lFni_{BEQuVV3UEqxt} z54P#PiN%kw#`rcCA8W1goxNt;@O>;EvnBixi+^cLC`*qYW-C#i9`9vqU6CGN6p2JC z)8hx)%m$~&Z?^Uxk{-XymRFS?f7wcPdc2h_p(Z`v*e0k=kC&LEL(}7r+rAx^9^Y;Y z8lE06HZMn{$8WWnjZBZ*rxzkeq{oNbZX1;zZ*K0~kshC8E79Ekx{~e17GC^zTZ!Yn zc)7LGd@tVGcIN^wzQ*9YUi?&(_B}7YyEWuiFaD;9_P!V2#Wv*wFMgV>;D=tkqc!VC zUVOZ*%gcWJ4IA?nKmL+U{;D7EZHs-)kN;x3e6t^a&sOPmKR(EI@fJV+yumm8_zSj0 zZ~F1|Hu+nAe2T5^{n_!4t?3@fj-O^TdoVlxtS#Z8?D#m-c5UPMc;UaZKJPg9B*UuytZ+Cfi=i=jpH*dozg7+p>5Hr&EnVCcZ8))I{BiSTQOo#Ln|yK0c#$>a5_`>- zu(V}-maRm;HSzJb*!(r|EjF`)HStx}tVL_$OL8KS;x+Nc)*vNo;`X#5(tl07$Xa6X z6YYJDqczBQd(Bp9!nSxX+lGnT;-A~{ zCT+_+#$KDzBpS(_ZT8M|1HagOXSsoX)=0D6z)QAqE|ahV%f+0OnXsvB5m`*npIC^FSgb_1{2x~y~qv#iz5t+RnG zw#DbUfxoQD&UXX%*_K`42EMTEUgZWpuy&ts{g=%4wqgt1z>l_K?w&8xy_FMn1NYi? zrMZE2wsiL)nal@l5$SGVt2LwN20U}Z{t9CxGvUs|Zs0x>DeeYtv}I)m#CAlM8#vJB zob3jVu&LaIE_0)8p#43*NM@!@wW}NW+}gXb8+gV>PPl?5Xl^6E1%{DUba?sAMME;Wk*rE8?ZL8t*`<2 z?rDY_SZmwm#>za{nl9=F23Uiqxq&NeRo!%vtbJ`=)2BsaYc1QQ?><{ncKX>C8l`*t zdhU-T?^2K(@%GcVYwT??FXDAnY-6!&#OtKEm&I-oZ-2!-Eq0H12Pp1gu}8!^P;qyQ zJtJOc#nu*kMZ7MGtt|GAcn2xAwAd%&jPq~H5wq9M8o4af))=jyY%eH3S zm7BV3tJXugiOaTbJ(UwK+sgG)ZtSwHU2o-GUAEQhqr8jDwtfdIH?rK-*6$GIY?p2Q z4pq)_+19VGa;D3+eupW?UAFZ*T-kTo)~}y(hRe2o`O2QlwtfZ5_L;7NuC{)K%J!+N zg08lHMapTGyV?2`D@R?n^(#@f{l9Cv*CAGE`@iu>)5qH<_G2|TO(2!}d^KJh(o@cjW-t^FrTkUG^o$EVuoFS_`_lNfbLoU>$GUOsf z8FI0r3|XxxLoQL2A(tx3kTr@j`)+%GjmC6`$l`@80t&AbpC}YUA z${2E;GKO5Qj3GBDW5|ul7;=*`hTN=-A-5=F$gRp4a+@-S+^&ovcPL}Xoyr(;mokRj zt&Ab}C}YSv<3|X%zLmpO? zA&)4^kVh3|$YY8!p6#sSNp0QHFe^C__G0 zlp&ue%8*YLWyoiWGURhb8S;gq4Ea(KL$)bn$XCi3^0hLCe4~sZ-zsCscgh&@y)uUU zpo}5gl`-T;WeoXA8AEG2~Ze4B4TKA-^eO$nVM+@`o~p{Hcr~e<@?g-^v*B zk8)_pd$Heb|2J-Fogi;(U`S$bH*8PMoI38?gVLj(`#P7Vt~cXFHMPDyD1)qT5Aw`k@f9C*<^itP$ROwJ!luQzCCDHGT$E57{Ip&B>;STP!j;(9@G@T zw+A%?@a;j(0epK<3jp69v>SkL4{8bE+k;vG`1YXI0KPqFcL3iWvgY^2oBND_ItG zBV$o_02cKCU{Oy17WD#PQEvbi^#Nef!2m2e1b{_{0`r z6#%fP5P(HR04yp7U{MJGi~0kwXaE3jU{1%O4T0b02ZANz@jq%Sac=;i_QXI(b)hjItPG7 z=K`?kJOCD*4+t%q8I3iyi&^3#cjG)u7X9EXx*+O1znn!EM?Lp-c7a8!nO+uMLY76B zl4a2vvMjocEQ>BD%c3jDvS=+?7F|h}MOTrr=xP8KT?4?PYXMkv9RQ222Vl_+04%x@ zfJHX}u;^w07Tp5CqFVu2bQ=JRZUtfMfU-) z=zc(G(S_02a1$gk#oZTOB#RaVeX*$T{BjmO9QEe6l|_#*y)1f^EQ=l^%c950vSb`8UTwn1F-0I02XZlV9^@@EP4}wMQ;JH=xqQNy#v6acL7-R9w4;np=j)K z6C_dY#97aMk-aVEZH@ZQFK5w5QO|vyW^gY0nCWHFCuCXlDOnbMMwUgNlV#BtWLfkj zSr%<0%c8Hyvgm6v7JUQ2qHh6M^c?_;z6W5@4*)FM4#1)x0a)}C0E>PGV9_rCEcz9I zMLPgk^cw(+eg|OD9{?=+6M#j30kG(A02ciNz@kW6vX|d9ct0u%z@jujXwe7J*e51P z!gCJ`Ka@pd-TPCqG~fBEb2~{MLo!} zs3#eVdI7MgHvo(J0I=v_02Unrz@kF|SkxDQMTY^f=x_iQ^#fp0J^+gf09aHAz@j1m z78L`qs04sT{Q+1s0DwiM04y2^z@k9_EGh$p7VV!Fn_+?^p0&@ccn8R$#qOPp@-*N1 z8Uw(hu>dR@2f(8704$mSz@mu&ESdzsqR9X(IvRjQ#{jVCSO6AH z0btQo02WOHV9|5{7R>-)(M&*SQDs`}UK1oS-aZ)Q4VFcJ*p|8 z^8r|N0RW3u0kG&oKxomNwAh~}NaAew)N!sX>g-NT7p3{mFK5xEX`cH!`oN+!OfQQr zBg>-8$+GAQvMgFlmPJ>RWzkh+S#&j77F|P@Mc0zC=sExvT@S#b8vs~zBLItT0$|b2 z04%x%fJL_gu;?}b7TpfOqB{UsbSD6d?gC)Z-2g1Q2Y^NE09bS{0E_MeVA1^mEP4Qd zMGpe7=pjI8(dx8VfeDiM$vv*VL>49NgFN2)G~fB8Jj zjbvH$Bv}?cMV3WRlV#B}WLfkqSr$D<#-dFCEP5V*MK1ub=tTe)y#&CbmjPJx3IK~< z1z^!@04&-Jz@payShNLzMQ;GG=uH3?y#>Icw*gr64gibZ1z^#804&-Hz@qm7So8rP zwCItv*eNDR;%WOZuJ@=c>TY+{-iK+v^UGQEX_|LqH(B%<)61gI$+GARvMl_rnK@t1oCF6pzK4 z_cV*PxJN{pv9PD#D9yqFG2i*+EIKIW_2?~&a+zKh<&kAkSF$YXMwUh0$+D;iSr+vq z%c5RnS=5^>i~5kU=wJXA9Rk3jLjhRS7l1{F0kG(B02cKFU{O8*iwXc(R0zPLA^;W@ z1F)zBfJOZQSTq2DMWp~N8VJCmK>#c&17J}(0E;RBSX2oJE$SSLjWj_LTim&*i!ACK zvoJX3JHMPoH8JmmgJn@I)61fvWLY$fEQ^MdWzh(-EE-9cMMscj(I~PkI+84ljv`}G z9RQ0)1F&ce0E@-~uxK0ri^c=6XaWF>CIYZ%5&(-P1F-0502Unsz@lRTSTqHIMN;;~0btRo04zEUfJLVRu;>f`7M%&eqO$;4bT$Bs&H-T2xd1FW4}eAI1F+}<02ZwR zV9|vDEV>AQMHd6GXf+_T=(t$yGZQ4?xf|-^Wl@E*=#rT4{Bjmu9`pReWziK(FN@Za zWzm&nS#%Xy7F|u2Mc0sJ(Y0h*bRAh1T~C%pH;}RDMgSJw1i+%30a$bk0E=z~V9{*= zEV>?E%1|Jpov>7XXXe0I+Cp02bu{u&6Bni`oIOs67CS zIsmX}9{?8Z3&5iN09e!!fJL1EShPO?iw*!_(SZOg>I?`i%1)2{ZGt4uvENMg8l{Il z{UhD)rFKd8onOwPuIb+117uM*rk6$C$+D;iSr+vq%c5RnS=5^>i~5jd(ZOU{bO>1% z9ZJTcz5pyb41h(41F)zc0E_YgSX2POqCx-`6#=lQ7=T4304(Ycz@h;FEGh+H(Lewe z4FX_M832pQ0a#Q4z@kb377Yeq(GUO@RRKbaa?@i)CP-qA>*?poqOa|fvR-w%@BDHW z4NLbX43tH~nO+u+Aj_hWWLb0sSr&~V%c3L6vgjzXEUF{RqS0hoG=_{tV*yw+4uD1D z0a!EvfJGAlSTqTMMUw$obTj~qjsalNu>dTZ0>GlF04$mYz@q5@ESdqpqL~0Jngzh3 z*#In>1HhuW04$mZz@p;-p+&XnvC~YDL_2pwJyaI;c1j(e?mNGnMGMoto6BU;iA*nx z7LjGqVzMk+LY75K$+GAqvMgFgmPO0SvSJ02W;gz@pUvEV=}M zMVA7wXbm8=XhC}HWfLUvn?>&gS+vzzbXmIZ{BjmuneP2iA&ahJdRcTeSr%PGmPOZ+ zWzltHS#&*F7TrLWMK_XV(M@DobTb)?ZUJD?tpF^#4S+?r1F+~002bW|z@obVSadf4 zi|zqn(K-MY-3!2?`v6#UKLCp!0ASIB04#b4fJN&8SoAOeiyi@B(W3w?dJKR?j{`!B zu1JsVR%sT!?>^qRRu;K0Q}Q;X`_3!*lV#D5 zWLfkRSr+|F#-d*USoA9Zi*^98=r;fs{SLsQKLA+tCjg870$|bK04(|kfJG5c-F7UB z0M2mqoqEvZyy%7WE;^qJzn@=n%3jI+QGn`jTbQVPsi!I2nuj0k9|^fJFrW zEGh(GQ4s)(iUC+u0>GmF04y2+z@kzB77YYo(I5a8l>xA*9Dqd?04%BmV9{Uz77YPl zQ567-ssUJ31HhtMKxk1nFV@8bNnGkacimkUO>hs7hI+p9%ULwi^D0Nmq9d4I7L6jy zq9e(&=qR!*sw2yy(PUXPhAfN5l4a32vMd@;#-a%TESdIc z1z^z>02WOJV9_)H7EK3W(F_0<%>-c4EC3eG24K+~02a*!V9`7P799t`qT>NrG#`LP z3jm=-!@bxX6C{!AK6gDr7WJ_|?dhH1`OYtA(PGbAHA)sOVR~7#lq`!*BFmy>WLdPF zEQ?ljSaco$ zi_QmN(FFi3S_QzO3jtVk5de!W24K-@02W;Wz@ke5ShNO!MVA4v=yCuST>%I!I?;;!GQBLijx39=C(EK6$g=20vMjoZEQ@X? z%c5JzvglT_EV_-1MYjX6=neoD-3h>=y8u{pHvo(70btQO02bW~z@qyASad%Ciyi=A z(SraidI*3;>j7BwFaV1l0btRi04#b8fJKi3uxJASi=F^r(MCXM(N$h7QfC$wI&rR+ zMZYz%@TBKEznn$SdS2TxvgkRcmqnY%vgmoTEP8<~i(VwlqL;|B=w-4jdW9^DUM0(- z*T`738GuEv1F&cd0E^xLV9}cZEP4xoMQ;PJ=p6tSy$isi_W)S56@W$W1F+}=02X}+ zz@m=;SoARfi#`Eh(Wd|``V4?Yp98Sy3jh{<2?#BE+KZK#Ac=u{nmEtMqG;5@HqUo{ zIg7sayh-C^(RWNQi@qnzq94ezXggUJ{YaKYKapk8&tzHj3t1NZN|r@C$XN6n0E>PH zV9_4{Ecz3GMSlUX=x+cP{R6nwIIu)-N>@2C0Q1=BFm!IWLdO3Sr+X)6s4G>z?BqR2!36l8Dy^q#3Bkbw-b?@nS&+wgJ&Z6EK-j9=HQ6Hw4MF*2* z(II46bSPOC^(D)q!^pDeaI!4wN0vqTWLZ=|#-c(178L=os2G4nB>*hy55S@U04yp6 zV9`JT77YSmQ5gV>$^lqZ0l=b402U1fV9^i&7F7YTs2YGpH2^HC1z^!o02U1cV9{_u zXi?9MSgXnIT;widy=2ig_Xu)ChVT4x79E-4^*Kfs9mVvrsE#a)Mw4aH7_uxHOO{3B z$g*fWSr$zo%c6;7Su}}^MUw$obTj~qjsalNu>dTZ0>GlF04$mYz@q5@ESdqpqL~0J zngzh3*#In>1HhuW04$mZz@p;-Sadu9i{=BcXaN9=P5@xhLI4(>2na1YA|rN`36i+B zv57NE7BzMsSzDChJHMPoCuMkxr^upZOfQR;lV#BgvMf58EQ?l>Wzi{QS#&B{7M(_x zMW>Tx(HUecIun3JX92M2YycLW1Hhtl0a$b%0E^BCV9^BtELsJ?q6-07bP)iHE(T!H zY5*2p0>Gk60a&yKfJK)9u;_9C7F_|rqO|}lx)OjzR{=tcmSn`PF+mdB-QO=-DvK7n z6VufhzVpjjbbW^R~ zj{&ggaR3%=0ASG*04&-Fz@jGsSo9PCi=GCA7G0YW+h&3!PW4Qj>txXe_pJ)gWcbc6 zXVLQ+UiM5`^a9h%q8G`s=q0i&dYLSXULnh(SIM&IHL@()OqNBjlV#BsG8Vl7z@j$+ zSo9VEi{1uc(K`SvdKZ92?*XuAD*%h$2Vl_$04(|tfJGkxu;^m|7JUN1qE7)>^cet) zJ_lgY7XU2!5`ab909f=D0E@l`gcd!Q5z93}5+}L$(KgAV+>?0AETJxnxvB(2pQ3e2ud;k{30a%m?z@jVw7G(pls1X2* zb^&0~t^h1*48WoU0E?OcLW{o3h|M!W64mynt-bGM(R}wSj!k{v`Qb?M;?NIbfJbp&8hCjb`h55S@W09bS&0E;>Uu&4_Fiw*){Q7!MY7Jk^%f8JfudilQd%UN`Y@4a`NEIO3wWl>+UEIN!V ziw-BtqJCsqluwpL1!P%NNR~xKWLZ>9#-b7c7WD^U(EtDzl>)G6AOMR70kEhHfJNm1 zEUExtQ6&J21_Q8Y2mp(!09aHFz@i!e7S#fH~@=A0I+Bz0E>RO60l=b}04$mXz@pgzESdwrqPYMp zng_t5;{aH6JOGR41F&cT0ENv(dlGabOu=#ok^BOXOU&m z*<>s_2Y^NA0j02ZAOz@iHPShNa&MHd3F=pq0XT@1jY)c`EI1b{`C0i*6^&qC3d4=uWaMx{EA}?k3Bkd&pR{4uD1X z0l02bX3z@i5LSo9zOiyi`C(Ru(DJq*C2M*vv#C;*Ed17OkP04&-7z@jGrShNv< zMNa~-=qUgeJq^I3X8>6AEC7q11B4dc;Kw$bAc@=Er}uA^MO)qTqD{W<{Bjn(3|7QIfEMO(k z02XZpVA1;kEcyU|MIQpN=pz6YeGI^&PXJi-DFBN;17OkT04(|ffJI*duxJ|qi@pM2 z(boVh`UZeS-vY4cJ3wgB3w~_(rDoAV%}ksZWzj#oTln7honOwPpM39-WwPjJrk6#( zkY&-YWLdO>EQ@|4%c9@Ovgi-8Ec%lyi~b_ZqQA*l^bY`wB5`%Ou_y|_qBH;&#Q<28 z4!|N0fJGSqEb;+Z6bE2YCIE}F09cd_z@kO~EZPNtMY{s9s4)PG5&$e}0>GlC04!<- zz@p}W(4y^rY_tiI*sYa`^P?yPAIs&k$699|$2Vl_w04zEX zfJL1FSkwi8MF#<}C>MZ5c>pZx3c#Xn04(Ybz@i=iEb0lsqFw+j>J7l6K7i1omhsqi zCP<=v2NS1NJnZQ=YGmQyxbOUO79AG%o?a=74rh8<)Q>ES^2xHOfGmp&$+D=3EQ^ZC zvZ#bCi~5sg(Eu_Ql>)G6AOMR70kEhHfJNm1EUExtQ6&J21_Q8Y2mp(!09aHFz@i!e z7S#fH~@=A0I+Bz0E>?Uz;F_(_Bx#uPjP) zp)T$_znn$m;@&Q&$)fR0FN-FSWzj^kESf}?MU%<0=xDMmI)*HZjwQ>YDP&nRm5fEx z09Z5~fJHL^STqxWMY8}{G#h|La{yR07l1|c09bS!0E>qVvdDbUpx!E&yQBDgYK; z2*9F?09bS}0E<=wu;>y17F`O!qBQ_4x(t9tmjkfq3IG~9 z7F`R#qU!)ybUgrzZUBT9og9xHZ-OM6y2sTkWzmc7Ch5kw@BDHW-5U2+pCyZKV|rP1 zJ6RUpL6${#l4a3dWLb1KSr*+xmPPBxvgls2EV_@3MfU@+=m7v0JqW;}hX7c#9)Lv; z1F+~302Vz8z@oShNX% zMb87U=mkJ%(arJLBPK}Vh`5P!i!9pgey!-mxbOUO7QGtx-akhcy~gyiXfs(By-t=z zTgbBL4YDkHlPrtgBFmz;$+GAjvMhR+j79GOuxKj)i{1xd(FXu5`VfFc9|5rFV*nO? z0>GkA0a)}I0E<2cV9^%)vGjAzqAu>K<14c0S@)5(ALG9B%USem+}r1TS+s-cWzlbBS@b(u7X3k%MSqfI z(O+a)^fy@+{X>>Tkxcd5Wl@xjMQH#miUF`F9e_n10E;pJSmXn+C=S4)OaK;T0k9|= zfJKb}ShNcOi*^NIQDXoWB>-5|1b{_N0a(-wfJMy#SkwZ5MY{p8s3jn@=;wHBpb3&V zJjcZOMHbb#w?kTG`pz$B(Vm&!v8!a!UQ92G+K^?@-eg&nLzYEt$+D;&Sr)Y?%c2fs zS+oyX7VS&MqWu6^)DeJ1od8(0KLCpk0ASI904(YZz@jbyEIJ5)MY#Yh$^&3gR{$1u z17J~i02cKCU{Oy17WD#PQEvbi^#Nef!2m2e1b{_{0z!*+&y1a8f+Tixe{O$|%&@0l z)WkyHOyBwCEXvRH?z~7A6)?RlDkRIIBC;$hCd;A{vMlOPmPG@|vZ$0Siw2Tq(I7Gw zl>xA*9Dqd?04%BmV9{Uz77YPlQ567-ssUJ31HhtM02U1eV9_uD77Yhr(Fgz*jRauP z5dbV21;C;s0a$bt0E_AXSTq`dMPmS=MTcj`wwNG^``tyXpDY?_uX$rLedm|6Xkw=K z>uOmviRoq0WU?$enks0ASI{fY74xnXx@DF^kT2f2nwaEV|ZR(N<>q&M#-t>6u>NHL~aork6!$ zl4a3ZWLb1JSr(l`mPO~1Wzl(LS#&;G7F|G=MXShIbRhtXE&^cD#Q-c?4ZxyH09bS> z0E^ZDu;?-X7F`a&qALJcv=)FxR|2r;DgYK;4Zxyn09bS_0E?~zVA1seEV==JMK=Pl z=q3Ob-3$mVIyEyk)&xluyI&qUO%{FYu4uPp`pz$B(H)uIvdd-BolGx_?jp;gyUDWX z9mhF#r}l4#1)f z04#a}fJGYtSo9i{2p1qBqI1=q<7=dYdeZ z-XY7PcgeEoJ+ds?N|r_MldGkO0a(-+fJF%a z7BvB2QBwdGH3MK#a{v~#0ASH>04!<=z@kmPPxLWzl|QS=5m%i#n09 zXnz0}9RR?h0|8jn8GuDy09bSo0E=<~Sd<6AqOJfe>IT4~?f@+60l=c304(YSz@pv& zEb0TmqJsfgbO->84h3LQUjP;z2Ed}j0ii{EWyKblAPL|7{h~HmVNd@i7y4!S&M#+C zQI>b<^|Gj#>19y~Sr+vt%c22fSyW1vMFYvQXb@Qzm62spIawA}kg=!|fJK7=STqEH zMO6SSss>eR@>ge>3r?mMK=Jj=tck*-2}j*n*msK3jm951z^!_fY72d zvSMW>Na9QPhtkiKMfmhF#r}l4#1)f04#a}fJGYtSo9qE`S|^eO<0UIT;{-I*0T&jd+K za-I9TWYG!EqRm;p^UGQEW|nvN9kS>xrk6!;lV#C6WLfksSr)xVmPK31vgm!XEc$>f zi#{aFqL0W}^f3U7J^^6SrvNPa41h(S1F+}|02X}-z@lvcEcyz7MPCE3=o3;3w4O!II zxA0q*@BDHW{gvhYc9$&ro9SiIKV(@H$yU!@7DdUjD2*(OVq{sAPL@R;Sr%oGWsy(D zqBsDHG67hW1;C}E7s<2v#4Er6X#D^G{rqUYLo3dznn$w zvc1FC$)fg5FN->mWzjxlS+p-%7VSrtMIFhqs1sQh?N63P2asjafn+S|48Wo;04zEP zfJM0gEXo65QC9#Kbpv2gcK{ak0ANv102cKEU{P-X7WDyO(ZK*LIs|}4hXSyuF93@U z17OkN04(YUz@mHr78L+Oi*mAK<4ur6{~QyiZFbnx|K0sDqrz<8`Q04y2-z@m`=EII;!MWX;%bR+ zCIYZ%5+JmwI6HQe36eO}y&GF1i@tLwrpej9^UGN@CEMHdfGnEI^s;CgSr$zv%c2=% zSu~R@i)N8!(QL9TnnRXFbIG!39vO>{17Okd04$mhz@h~JEII*zMGFB~bRqzY76Gtm zF#wB}0I+B&0EjU{1%O4T0b02ZANz@jq%p+(1J z$G$f~5{um*;X76qy=t#{XJ-4(FK5xY*S+t5Qi!LO~qKn9~ z=wh-gT1}Qkmyl)ArDQBx1Hhuo09bT60E?~wV9{Ct7F`LzqN@N{bTt5rt^r`twE!%- z4uD111F+}@02bW{z@nP~SadT0i*5m6(X9Y1x($Fuw*#=~4geP22?#AZJ3H3X1WDZG zZm7?ZMF+e4qPwzv=a;kS-fVB!BeLi|rk6$clV#BZWLfkeSr$D+mPPByvgl#5EP8}2 ziykG*qQ}Ts^f&;EHUO~b2>=#t1YpsV04#b6fJILOu;>{87Cj5VqUQiuvxN%c4)o zSo9eHi#`Wn(H8(L`VxRe+W=Vf6#$FA24K-Q04(|zfJNT{u;_aL7X1LgqU``I`VoLd zKLN1lX8;!c0>GkQ0a&yHfJMInu;_OH7X1MTEqW_Ew!s8RjC7By-8~M&JXVE^5yiQNbqJ5cO z7VSrtMIFhqs1sQh?N63P2asjafn-_KnJkOCkY&+9WGu=BU{M|bi@E}^s2c!_x&yGN z2LOwD0D9u&56Jiw*{0(IEgVIuw9KeF0c>7yye72VhY@02bu~u&4llMTGz? zDgt0pF(9<4eWO@~36kjOK2p@7QP|Vp)x9-a(#UsyIg181@}@s6iv}^hEGi?*qH?k< zsvygvO0p~(OqNAM$g-%4EQ_kivZ#iPMYRAd8VbOoVE`-|4#1)j04y2_z@j4nSTqWN zMMna#=qLad)d8?*Gysdn0I+B*0E@-}uxLC0izWcDXd(cMCIPT$G60K?24K-KfY71= zjbay=Ac;lp5mBiuTI+r{_SiSy?oL>1EMOvMicKmPND4vSBC%c9j}S#-(&N8DS$M{&3P z`ZL)KyGW8vU=yq~NEHGJu7xNBVnm8mmH&o%O!Ss|N6=aJ2#^<=Z?e6m?|0U3)f1Ypqy02W;Y zz@m!*Sab;hi!KFV(PaQEx*UK-R{*f+N&psJ1;C=K0a$bm0E?~#V9|8|EV>?mMK=Jj zXd?iNZUkV_O#m#q8GuE%00N6n>lDg;N-UbC@4H@S7S-yb*;_k>)i1T^&Q4z8GiK3U z3~v_QO*V@*k+7Cj8WqDKH&^e6y} z9s^*};{Ysr0)RzN0Q02VzBz@ldWSoACai=G2u(enT-dI5k%F9NXWB>)z^48WpS z09f=Y0E=D&VA1Po} z7X1mpqQ3xvMQ?QqT`Ph_|I{~wylobZ=q%yyPGR*+EefT1Ps{!6tfG9!OHFIr()Y+_ zQ9H6(6egQR5wcm-o@^F%Ae%)U$!1X}vRRZy#-elp7G(giCD6u&5^hi?#z`Q7-@%Z4bbrTmTmJ24GPi02cKH z1Qxkzq3=bI=y-jrbxK;$M*CeY>X#N)ztp0g)4a|vn?<`Yyd8^nC7VV4$!5_2vRRZz zHj4(5&7whMvnZcz78Q`qqQPV=8Unzgp#Urz2Ed}>04y2-z@m`=EE)yCqR{{>8Uw(h zu>dR@2f(7;09Z60fJGAkSX2nWq9Onm6$7xS1b{`Q04yp4V9`VX7EJ;K7VVf88YzNA zr)cATC$nfx7YXHQVf9Nbs!a1{ylNIzF}zt+O*V^a$Y#-0vRPD1HjC=WW>G!aENUQ| zMZ1&DqG@C-nhwCC82~Jr3BaN~09dpq0E_klVA0+HEQ$lLXchpA8Ua`|8-PV~09Z5^ zfJIFJESd+vqWJ(US^&VJg#awt2Y^NU0k6~zI=x6* zk``9K)S~7z@50y3q85fXi&l`$qLpN`XcgHk+K+4&?N2s~R+G)51IT94fn>AjATkym z48Wp809bS=0E-R-VA0_KEII;!MMna#Xbk|1jsjrO(Eu!33&5gd09bS^0E>qeMb`na=z0Ja-2lL%jQ}jV5r9QE z0kG(102bW>z@l3LSacfzi*5%57M+n6>hP9WbcY^`&NPcIO_y*-T3G#3i#DZs{ogT* z?qPVd=w7l}bRXF)x}R(oJwP^#9weJZ50TBH&1AFaVX|5D2pNkW1z^!*04#bOfJILL zu;@tu7Ci;PqNf2^^b7!to&{jha{w%Q9)LwJ0I=vq02aLjz@nD{So8`2i(Um_(Q5!K zdL4j8Zve39O#l|X1qdvW6_rYEcyz7MPCE3=o>67HtJ!(XRk3`VD|ZzXP!74*(YZ3BaPi09f=l z0E?V-YnWq^3kWQFH!XCg2ogO)-`@D1S(K)aLsHVi>X%y7F5SER1G6a1@MckjY!H77S=5Pa7NwERqI9xZltDI&qGT+}1Yl7X0E;>Uu&4_Fi(&vQ$_8Lj4gia~ z0~ zl$suTO9Y7)=moWx9<=mp^s7R5N)M}FYEl1m@6V6Sq5%wV7Uhx6qJd@M7G60LF00N74Ne}h;SS&hQ zAD!)L78U5@kc#xM`lS}tq@+Q6m70W&^Nj4gibh0(|l+MjF|ttOjA2awI81IcF5L1eS&V6s_s2-z$;l#E4( z0kG(B02Unqz@j4oShNO!MMnX!=x6{Itp#AwF#s$&7Jx;^0kG(J02ZA9z@ifYSacEq zi%te$(J25dIu(FLrvb2N9RQ0?2Vl_|fWV@b^w9MpNVKD##8#L^-}w!;^sxG+7M+{! zJ^O`ObRNT-MeE6C(fMSv=mN4?bRpR++CVmoE+U&n7n9AROUP!?rDQC+41h(K1F+}{ z02W;dz@n=FSadZ2i>?7+(X{|9x(;57TpTK zqT2vibUOfx?f_uXod7Jl3lLazc6#VX5hQwszVG@Rv#2CR!rkd%^-C?fFWrlMZ5G|n z@Mh5iWV7f&vRU*H*(};jHj5r6n?;Y1&7w!iX3=A0v*>X$7CiyLq9*}Z^b`P#o(5pi zGXN}l7Jx<10kG(K02aLfz@ircSo9JAi(Up`(JKHfdKG|0uK}>=bpRH<0l=a+0a)}F z0E^xRV9`4OEP59ZSaeT%XtW3ty;$FOeXm(GGbG`?^sxG+7JZcN?eVQy^fAMmMW2w( zqEE?Y(Pw0{=yS4Jw1sRIeL*&hz9gGPUy;qCugO^S4FHS21z^#404(|*fJHw5u;@ns z7X1XkqMrd+^a}uswgRx|R{$3M2Ed}<0a)}00E_+vV9{RyEczROMNWn_+p)+6U{MMH zi$VY_N(BTKeUKhHOazIZq3^r?&@7s+Z&~v)!s?e=)IP(z=zFuM1H+p|9m!@nq5&D9PCto7ujoUM zJhLd(Z?I*A)i1TEF2l?F#Vo34c(bU1Y!>ZKHjAc_&7$dKvuFm{ESgC+i}oO!MSGIX zqP@siv^M~Y;s7j~1;C<402a*#V9^`^7R?1qQw9#S^~hLr2s5i2Ed}_04!<-U{MPouxM&Vs8$4t7U^4xYR#f!)S?v`Vf9Nb z+CRf<`PD31&G2T?0c5l2K(bkM5ZNp`m~0juLN<#IC7VTukIcw*gr64gibZ1z^#8 z04#bRfJGkw0*mg?2=)6*EILh}qdj02eXs8?`Y>6 z7HtJ!(XRk3`VD|ZzXP!74*(YZ3BaPi09f=l0E^_;q|TF#l9RQ1Z z0kCL$02bu}u&6fxi~0bts4oDE`T?+L2LKlB2*9G909dp$0E>13V9~AsEb0%yq5*)w zq7Ko}MiC_1T`z??MuV3AVtq857Y(alYEePddp^}H8qDx!(Gap(G?Z)>4I`UH!^vjR z2(no;l57@@BAZ2{$!5_QG8T;mV9_`L7VQSWqVWJMngGC}LI4&O0kEhTfJG$$EGh+H zQ5gV>CIYZ%5&(D4gD;FMCa&p zw0yH@fh0CuEINqc&7yIc1z^!}04zElfJG+&u;@ep7M%pZqLTqwbP52AP6c4mX#gx*2f(7!0a$bf z0E^B9V9{9sEIJ#2Mdtvp=v)96od*akS{)4?A%aBr%N21BFpK8v&7<|vu==GIZHRi8 zbTo@DVtBLYVzOCu3E3>Vlx!AVMmCEsC!0lAkj?P?(G37B+6cg+8v$5!699{D24K-G04%x{fJL_fu;_LG7Tp2BqB{XtbQb`N?gn7d zCIA-Q1Hhtt0a$b&0E_Mi1QuNo4Lv4;M62~N{)J}IuKIzH2clv1OD%dh>V2MO7Cpl7 zX3?W$v*qG!lv(X(VMdJcd^&jYaN1ppSk2*9G3 z09f=g0E=D$V9~1pEP4%qMXv*}=nViCy$Qggw*Xl5HUNv>0btR)04#bBfJN^Eu;>E- z7JUf7qK^Pr^f4f?=%HvRJzXriUvCj@Hj9qer?Hv?b~dikd}VFuYmxCD|W02ciXz#=Epn(bKR0yOtM*&MK+5%lg*+o zWV0wnHjA>!W>F5=Eb2-&i@K4qs5=0QdH}GfCjg7K17J}v02XZzz@l6L7WD>TQ6B&n z^#x#2KL8f(0KlRh0a&yX0E>18V9_oBEZP--Mg0L-Gys4_c>pXL2*9F2fWV@(%+R?a zNc0L%#7WN#TKYNqXf{7HtbVCQLo>a*yO>487~U)zPBx21kj1NR$y(Juw8CJj4qC+yh ziQUYiLmA#II*e=<9Zoijjv$*wN0QB=HDt5sD6&~}G}$a#OE!y+A!E_804zEVfJMgx zu;>H;7M%#dqLTnvbTR;oP61%isQ@fG4S+@K09bT70E^B5V9}WXEIJE-MP~!B=o|nR zoeRLC^8i@19)LyX1F+}tfMfU-)=zahe zJpjO>2LV|05FoJVqRh}uB1km5lZbP%S+q!RWN*$4t6yr-W0~HI+nGg=GrU>!1lcTl zl57?|MK+6`CYwdikjGvH;cX@n?>J}&7$wf zX3_U#v*-u1S@a{>Ec%IT7X3^%i+&+v(N+K!{R+UM-vC(jI{=IR0ASId04(|ofJJ`; zu*k`>W;+(S04z!YU{MHwMX3NR@&H)W4uC~r02W06SkxYXMI8WG)DeJ1od8&r1_&(r zA~Up`2ogOdQ^fhwEE=zmL(;Rt>X%xSmF30zm_?l#-Yn`uHj83pvnZQv7Uhu5qON4K zs2kZV>P|L`dXUYco@6ZA4uD0y09dp=0E=<~SkxPUMSTER)E9t7{Qy|B0|1M51Yprl z04&-WfJM6iuxM8R7WD^U(EtDzLi^h`8qH$!iXg9K1G@fi0 zO(2^^g=8!$0$@=w0E^?h0bKl>jVS1;C>H z09dp?0E<=wu;>5)799w{qJsc|MKiNP(VfJiMtx)29%j*F`l-f)v%>0^T6B1pSFnp& zbOghjMMsj&qBUf*=qR#TbTrv4T1z&Ijv<>x$CAyWL02ZAL zz@k$CSad1?i%tVz(K-MYoesdFGXPk0CIE}h0$|bE04zEOfJNs5u;@Gh7Oe+h(fI%@ zx&VMh7Xq+o0|1LI0t6Nvnibkz1c_cM(L2m6+N58Jb#Yc${c^fEDPG_97Y%ToSe{&U zJF#l{I@;9Oa(PM;iLH|pVW-%wa#0nHy()*ZF0mfjj?*=!Qud5pA(!mAv9IJRt6yx0 zeE4?f*y`SnGaz=KJZ{O4c{@7J(Abon9cN_h)Lk8CZ0ywmjx!;)-5|#)iOnf+oJp~( zhB!_|?3-bZQxh9D(sAlz2aa}}>9GgKI?kT4@Oa0W6{{?CoVl@e#g4Ne_Ijz~EQ)PE z$#Is&nkGBWir6(3j5t+5-= za-2W1e>q3izneX7y}m^@`^XDq3%J>jZ;(ykW@lU?+rZ6kxJ)*Jn|sR#c?`G?FtR3WL>z8C5=4R`+9IbJ) z^=oR5akKS%Mow_E^@}1-akKT4{-?Xy`cdt(-E94=?Rqy`KP8(m8=Z>;ho|F%ExuY$l z$e!trvCv+_SPK*6E6d$+7Pj<}u$zTcxk7QrTbM38xH};T-DT%>bjGjAbDbV;jn`@B zGi&?xaHo2m`jovsvWHvib-Me?LFql*x^|gczWM&NL!6!iWsqNGknXapI_>gZ=h0wT zH{ahKaJ7ZN9`ih@H%D8 z|8%+2^A;Hj``!;H5k~H@rgeE_+~M_8y|i2>;wGqJ$U4c@96m2W!`$nQCkl5 zXZrga&wf^BS~PR=bc`aCzrg1QgL|1zKD}v`KlEW+UOWF#e{LSz^WX*kz{g$u@tX%Z z-NgidnCESnPKUj6(Gq`{2R=FKGnuwb@#rru`1W9b5pL*qQ;E}aR~g1%OJ&lbYw0Un z1X)YXHoiWx7Getydy{xZdn|FX#++Z*4%yvpg`L5$G3In*@n(+ zMSToi)rtlh+GJ?3v)!eFM$5STMS17+w;qsfAOiKyJ+#uF^z@Iq9^y}Wa<4ApTdybO ze4_u_rG(n`I#YH5{nyTuuvyMh`mfy%p$@%XmtOQ=yO6wclAO8pU%O9J+Vxs59r~}` zXA+K)f%RXz)KELe&2)E2@7ytz-XpysC)17QI8I7Gr(?(61UXJ9+X1MT?(DkgMZaR^!UeX+;{v3vf2we>kvJTJHmBRx}I937ZLJ;qc1qlcJw1#f1oqI+t_YP(*3E* ze9DfQ{3llyvWwPexlO!so!zx;@;hs^=)pGC`N6HZkimLNhrA$v@+Knt)4r1blJm=Q za1J>y$RH{1@9AldD}U0j{Bs8m9Ms%6XkN>*K`qU51~tc9<}}5ZH7{M!G-pNA+(C1i zS1((!RKc94xhtEST9RJV{-y6xgO)WfT)c3_!c|Sqpan}8Hw|iB)U^Mgfs2;TXBu`%+C@;5pY0$zYa~7?f+cao#EvT%hiX2y+)MSs_8Z75(CKmM&hrbVofkb9>ZAhX zc&>bXsfr&O;(A`^fA{CP?LzZiFBa;S>qW+TSyi5w?`4hlymn(dd!5_KpzQ{=%WXGk zkRP&od!4seUgw@k12Td>ZAOrr zJc3+*1TvjLUarj2b`pErWdF0FI?F_Qd%gR3Sv``54Ho3Txd`4AuXDN1zN`m-jylV% zw2qsl`9B@^e1G|5UHMDPSa z!D{;dFeBr1v$q-UKiTYw>G#&fj`f%2A7|FI*4%boysSy`(tk8Y^+>jRZ;>z%$#x4H z?SE(WiblciBm2d;f72}!`|mHgDv&$G>lVzQrf#|e_V)f&=YP4>|MO$>27BFf|L^T> zud)_+-GlwvPx)T=UWwPb`|~X;N0&$p)>qn^yUkI;9pXhpA0IN%b3^C319MaAUJ@^?o!C%WT2=4xLS<=PUE##icztzsyrQ~lqElNsFE%IRNzfh{27l#avuke?kq|M+(6>?InE%P@+X;q=b5~sSXE?!s?jAoeM zx6WBv(t?-PPh$PXYbMQz%eJnRtz2AKUtV1mtfx_l0Sk(ghAgk08ZQ#ZO3LekiLow& zQR>M2%@(gHubPrrYtzch%HxGK{#+JUS5=i3t1Z5HWkYp^`JE-EL|sF1u~?cI8fB+8 zls1&c%VbR@UaBdqEw7)Eh$?kuVbu)VbgiTCH(OnGoj(U9Vs&B$hWXQHDXhP;0@**} zb=75M@isjdjB3+&abZ=wzP7NcuClz|A9HPKVaW`CVT#%aTU%EsBl0)3tY8zHX;#-2 z$Ls2=Wu2CajYCE3#A~QrR9ilAQhk-I(Rf{HeZB6> zOuDSNVv0YzLxu)>&M<$9{>1Y^{?6nhQP{TCNPDqBR$pRl<>j?yh4Iqj;&?$(x$Wk~ zZFWWf&{9%fI5A$`P+!wfAK$&YqF(l?VTm1yO+yVU{OO|u$E=t zNIo6~yOPQ*D_M7LT^~t<*G`vRI$phdX>D0W^|Wm#T3arikIor_s(5qvawd#gi>5zS_tfIWQ^{DS#st2>gsw)_r*uiC24|YJ=|K_e- zym)nD-2U!RT3z0Dw_(b17_O|Y)y<*D$zT+N{T*b{(k1hA<)G!Wp^UyjIv7^gVO@3W zX-W_KiP!A7TU%OD>K~hRWtFz|DA>}v%(5}d%Yu~>%)#)asrbho-8g!L^Ur2Bmu!JU6XS7PP*+vQ)N`KaP=!tz4Wm!5Y~{b+yIfQDJd?`R>6v zXL!=7j-66Y&J(Nr6SJ?v5a~rb3fmmqlaCCoN34R<#Fo>}#B7=fvh8IbZ?Myy%w}s3 zGSQ;iLOG?ILOMm+I?20`tSSz-71edN6OT+xP&Pxb28-w@^*4CS!ud;@=H^NRzBw^D z^|`uCMkkWA9->a84)u>Y;9D`Vsv);{)Tms&p*FA}S8u81j~qNScjxA&MNN$@O}pggEuOP% z<+wRZn^!dLpSO6(5CJO|tXw=>>bylu8&~AX{kU69YFJ*&vb?zk!-X_9 z&si`|ZqTh7nYVc0V!6fFe{RdN{_~dQ=FQK|s~()2CwG3v&5;?%o42^BrKNFxQ{JMc zCG%G-7?&?7*thc35J|c&S1eq*B(Fv8jY(}0Hn(v_VIOOV_`bHiqE4Kdlq>mQc1N@tF6Z!owQY82qd+eK%H^s*xL635 z)0b^w#nPqA3LL)-{>QwuIT5$HzO9ro6;)6F#}LI8a-5elryhs=brT#*6XqA>4^A?_ zAYb+aS(<_oi9@ce{=`UI*O^|W#cjm}L&&+&?~sif06AVI9j5%P+}ax3<|5mUcx_J* zLuE`&alO~r)Z845QyORgVrGKFb8Ts{&eaU3dgY1|aV|ckX?6LMxlQ{AgG#H@?`Ydr z)zeMuMVGWtZFkfbx4$B!!;m(KeIysnen-$!^ih7Iub_)#Xwuc6f6XdQ8@m#deLEPN zEM?MaN*X{fCgn)wJL31++U83%R)^bIf@T_14UXKUl{HCiuVTF$kbIud`A%*+PMRh+ z9EzvNK{HsQHv16!f?l2^HUKcWUHrdkft8h)Rkv*(w(3+;SnS_Gu9q9miSZ|nxBuK( zq_r$7ZC~A261@jY-B4AyyX*?u`c1r&v{DNjq-`x%V99N1y=r3B1u9LHc1dsvlX$`R zS1(hmtMpjmpO*{%x39{6rF)Vz)J&k(_F3CzmpYg*pBbsEDUVz8Sw};2uP`w-ISDXg zz2dQH$i=L6709)IV*ZlWKuvA+q;hEh%BHB2i(t8-z$AS|bVgK@a=99vDKf<4@+747 z_C|qRPRj)R7DS>M!3gxgmaG^YQOXKSo$5q!J#m%N+WaZ8^J0Ot99T42 z3yHbrdN^5nf5jL3tBQHhdE4f^U0A30#S*tvWFJb5G|?a{Eb{M=C0Crq9M-7~GMmfRF-aS}PLGSNUTQD@@+y^$ z+vYx8n+xW|1vpL4poPR*uvOZ2&tzNq>q9Pyg7qQou%z{&=Ra+X#OtP&*UKwOCsP`1 z1+A_90y#1}Eeqr#Dbe)R=9xbMIY0Xy+8k35w3_^vl6EM$Ty9-MdKcEeRiYOpa(f^? zv9LV2Hz(dDdSm5CGoYcO_1Z&q=ki4lxc=FAqC9kMmgi)JO)Z0m4XPGNN` zldMVH#~I9h9BuBgI+>(iq&WNdM@U@|ZEev@a??QWkCqq9kw%XE_5RvS^i?NqTDb>c z?R?g5(j(*lsRyMcO|w_d_t(3&+?Yw-VGD}_1A}|WyuuQeNrOz>$M9E=KRH5BMwQ^uV<%Vp&i za@m%AW1#iIrLL~np3$^f56Fv*a;MX-Czb}+_kI~1oJZTt5;KrEm?u_P(&0_piuA}N z0?`wvSAT6K-{JH{_*ZA=;8>lwCB}IDCok;vK;5jh4Z(3vkIHa6hRZf>dlNOOF(fx* z{7oq5^M5MELdZc;&RKTJZ%W7XT`WwJ|f3yFya%f>OqcEY5)p>3NZ zT>khImJN`YcYoiLvs!&&tzIw6{vp>U|85^lx*2OrRS?`s)zJnGEM`yc<=f?rf9b*P ze1G~$2WFEwxE@N}kd!@{iyD)Sr*s9ueN=xmdfU?P2(G1>vL1}vo@WxfVDerQ%!!P` z--8qDqqw55vL@+&(>~mR?wG&)&P^N2`;ha zPF!NW_@2lyBLRvlOWL$E#dEeMmZaW|+~)B^>+M20gS5GY(%LMPC*SrkOJ`48Es4ey)7LY+ zf9m>I4OewX<)bmCV=1#`ERefgiM7hQ2<~qtJ;)DQ5dO+ZzAp8fdeh|LtUjKuw&$(P zQgCBkAI@!i_}9~#KF;QF#p6(hEUGB1nj$-JsoWde=5k0EW!v6cH%vvfJbshIiQG0V ztV+5Er(37(jgz3^5?sf(IdS^S*m^%TcxLcF`EE(xZ0WyCjwNor%4^g9(fO7=tU=Zn z3$61Pv|s!#j^@F=(0H6iHX}|tIZUdZA{GSuc)1wWdXsNjp|s;UMsG8u-agXvaj@cB zZ>Q>w%0#a`weeew6Kl17zRh-P(?(TM{T)o(QjCOID=sXSO;{H9uO}RxJnwR#d8NwQ z&Ys+s3Or1@ywO%$a2(W|kGi^oV-HjG4=Q#4?zyL}Ic6(y=@qnYd`i>iXog)H;q}>rAVzonoid#HB}pT(ZhS)2kf8crwzqxm6~Qv}vj6 zTP>W4#l@p@chnmbn>;??s`T>pUp@37tF-#;FZH+##wE&rB3dE@gz z>7CLXeLFIL`nKc3^sYy?TjL#-dUR-Q%1N$MI7(h^)OYbZu6$m~@kZuV4wU9cmD4UW zT-iRx4YZJ?dkSP>Ep`h2mbMwj8dKN{!Z>8q;ED&`U}~cq(LEl zuW8a>NZw~EpA1X-OLd}>?hoEuEnTf|uhyPIj=Tdt=`WP{#7h7}j=YmU=`ZB8eXnJ9C;^s(w}^AE-C5!#QZ*Vsdc?)$^7c7=1-SpB0;L=hHdhK zZStyZ@|tb(Y1?Gplj|SF`mJ#K&HWE=Km7ai-4N$rJQ7Xry&&oI_%EKcwRskyZ>#Sh zt5HAp(?PztwM1*oan7|WpElDEH8>l!%DesFF#e_SZ?(#M`~T1?m zD&t#XTtDfeT(tN3O~%`aQ`%pa)m~P2wYouTH~Bz@OeaM&(tRvNKEa_zXq7?zD!n)< z@?vkTBJa+|b-&X7hFcwHwa99X)ds6`tnOoVxz$6h>UP)honrMOt2bM{)9QUz<%4#9 z|4&+d-s-DX-?sXp)z7VdWA!Ji@hV@jwR)D-^Q~TD^(w13SiRNi z-Bus4`l!`stiEjZEvp||-D34St6QzgLE2wW>Yu+Jt#+~6!>WGpNnhW^YQEJGR(G>n zYPG^@ozJwIiX1<6dhM-7t>#$mWpxLu1FR0QI@)TX)k#*Xt?q7hFROaI*6HnQ zwb|-wtA|-#YxN|nXINct^%ARBTfNch9aitN`iRx1t-fUSO{*VR{oLxeR)4YjmsL+r zi8|k%tai5A-D+>EJ6j!Ob-2}WR!gi-v07_&hSgbC=UZK3b*0sVtR89gIIE{xJ=^Mq zRxh`Doz+{c-fi_ktB+fK&g!dH-?93!)i167VD&evu6#^I*H6T1hShAV+ga^rHP7mB ztK+RsvO3l3OsjLOF0#7P>LFIwT0O<;IaV*WdX3dvtlnew5v$Kyea-6oR<~IF!RjAY zJvm|N@}^tOv6^dj7psGQ<}r>rVdib+FpSYG11(PH9yE57X-Cr zpP){)dfcKQpJnyAB|(1MYWDIV_qDobOOO{@y?AAiZ?O8=enI}p>c9hnJjUvZgMxgx z)w>P}@}pLr!-Je=wd}|s*I7N`s34zX^@X)Te%ET()hO1hTx|8A_kw(^)dxQa^0QVW9|t*Rwd&I#?_u@y&x3rC)i=Hf@~2jFzYcPq z)p_3rxy9@-s)y)U}^u)TkY^ykaMio$UPK& zeJ`tLrUdyCt8dA-k?8B6TkRtaG|hvoE@&U*l~%8pFDlX3@3#7*G~_h9=|LSG4eCUz zhh+u%M5~X;mzik)FIw#+-)f?{o7Gxr2x^X7JzKu#MDt}<-;pmo(fozgez`#|u)2>l z==JsetZwWV8|SH2ZPr#Harc&p2;uCaQS)vK-EWA!VovfSTU{mtrMR>Sf&8~S=j zt6i*iwc6Y24ps+R9c*=s)$vv%j`%L~+sSHYt2tJCS?yzW7pr+z<+9L8k#OYz4i zm;Zi!KP9Mg3&=^4YrL+;oq;W@7q4iXEpaAwSKsv_xBcfWl~MWKjk9MrH?0cB77+PPhUD1Tte-rv=>>iKlPuD2RIoA1 z3_An$gZfSKVV|U_&TDR5EIk$0Rt{`jv7&k5?3F8IwEyv659!mDf4Xk++FvM$|L9L&)4!eMpKj;>s=s{cXWQu}e{F_tQ~ett|JuvH3G&bXYjXYjg>p&m z-yzoibb7PoAM+rc&e<{plf*mz=-N|2^7uB&_-19wmy`(Cb-?%*NjJktr}N$r*U>M& z;g8Nk1kkOoojJ^PyA6TU1&m#s6C);~Pzo%CxkyujtG7 zOMe>#>ai_L{^|Il@=w=^j4$ywYp(Q{NUh@&CEN6OjLhE;|Dr$pT8_c_1D6iUmA`@! z`NK!%4<0#qxOC^|7bN{ZeE87Z+)+bE=I3jVxwASPT3S&Sd>c(LVpr~Hvph-`Eb)^U z920hSy2%lB>#aLiytH*wWA?Y(w<~+T==&6JhbcQu-m!f1)-^TZvdvo~jr}J5{mWl} z>%ZDQeWq;Qn%aBw*3J1ZZA~q3`v3lhldG?+DeF09yUE*?_nNeMtMh=83Ey|_n^`$$ z*1ij7I)A+U@>ZvJ*D0fCY0W7=z^~bp?(*wzv${<7hv@4~et7Gqf^`euO#S1f{Iae0 zRLl3NX_ar1pRi^B8Ch#49&z|?tD2(b($^a=jawp`b%-!T`VG}xRDEGTc)IV zzsIzM_w6kk>;w5PrLt?K^q-RIt&;;vC{JuksqQw*N8zUKk|JKQ!bte(ZX!mir|+dr zNewTP5rtlnRUR79xlno!^~;t2^1IYaw|BDq*X|zKbHb?yNoVSmbp1ZK@crssSiXDF zal;eDnG}Cl423reNe#a%GwOw36yMr~d&}I0!$-^LBjM|Xw-2XF{~f~9Wegp|AIZ70 zQ@BH}-0Tm3Dwj;@;kcZQGr}qIe>B`*`pgW!-cwW#$7B&Zhwqbqx`gxP;vg1&MEc1N z-y&y{obaoC!DofcdyixY`?%}h9_XwXRYq4i|rQ8VV72ZMSVf*l}@@j5)vP`je zc(dFv=@XtPW9u9KL;CC&-Xz^Sgd6(G!?kdxjI$~Hwsb!h9w+ngc=%J9=O@B3xs-S^ z{H)B|Q{ls9d7loikUpP@^pNfWZscZ}tvok!s`NF`jhrt#;UG7XCUcYTM&6ehJjIRd zA#40pH*$c?$~rf4v8=n(-N-evy3TMT-%2{ujXW=_?JPI4QO0t%8@XB*{v0OUxp$rGTc|8$VOQiUxy-J%i8!R6j>e{{ zWD4JfBHd+r6{(Sk%tU2sWQ5FhRchoA$8oAtBco(wHK~!eq?f6wkvy4RZE9qSl)BVN zu}rT%HIg9%G^9rA#L?YTBj3w-x?M`~ocY_>fm zi8~upBP(Pkx_FUOWr<>5WVOu1{$8X~*3xP(GFdj~0bXRDz_+|esvP#-_9CUSBH!^M zc{1vEy~r^#FYkGgyJZI7_aakdwSM45^nT-W;fP+cKOc^qBZI#Xj*OJaz8H@DESvnL za6}(vy&R4_B5UH6aO5e0uZAOfLHSxZ^0*BCdN{IGX7`Sck&$BbogE{$%4F~A7+EJ% zxVvNIBpLOFjK~jS!9^L77iH!z&WIGtEM1Zj`B}=P84-Orcv(i|PFYKrXGE4uI;L|Z zOSa~*og>f6;L)8Tugel;?i5)lOS>#5a2pO+WV5WS zl{t|;WHDFeM7qcZ-!CU}xEQ;CPUK8kgR65Qm164wIgw&n^9SZcc9Ho!C?}F38~os$ z$XJ=dLvkV)$l!@oxLT}Bu>oP z5;<6wVeXd5^D+}nTOzY%8Rkimxt_nJ{eAMT08!bd0DF+dW-hdxO7aFj?=W`See^(+VO@g+3DKxnJo7i+A&Nfv3ibl>@TbC z0PW}{@rA5LPdjGHP9op>=d@q1$6@X0 zBqX98SIM;6Ysc-fAv$Qs02y;f?bs;&$jQfPKVH_geE*x%es9q)T{}LN^_`&|k4eu_ z?N}@QWNOFhvU#(#<8xVKowZ|*kS^Nsh3q>q?f6lqrE}fBTsDC;)tvS_%BoAzjvZtY z`WB4#JIY>^svWX?vJ}#xPqW%-$91w?+E@EWWRG#RqeWJDigt9D+0fyf4hPDJQkS@) z4U*;5_km2QW9rEgI;DC$diq7bX+`;tx0C%s#P$*k9B*ffy(A8Hyj?7ACvk}5?P{^7 z#G#JY-(nAm!yIpb#qJV^J6@i}ZW2d0-aw08C608wK^Ai)j&i(wi`fzjWVQ+{$27}) z4Yu4xv&`5K%bhjLoDH>{rCDZenB`2(GH=5zM>WgLjj)`dS>|q}<#f$5d!sC;X_omL zZMl==!7_hiEO*o_^EcLV2hB2n<1Dw=Ec3UU<%njPzwwsCnq~ebSZ=3T=C9DQr&;E& z$g;fmrf9ItU$JF*cTCY>nZFXtDUyfC{FPdEHOu^!S(fdep6c}rRm=9z_(b&acJP1W zAme!1t-XoiJlXNpkSU&i3AArWg$-(kR9ZAcsw|oz)fUZ=8jEJgREuUvtwl4W&Y~Go zZ_x~Cu!teMTgH%SmN8_yWek~N8AE1T#*jTMW5}MCF=Q{x7_zrz42fIDkXe>7q|q{l z%(jdnb1Y-XT+0~JWEn%|S;mn0mN8_3Weizp8AJB5j3N744h$&|Etl<|u~Cj#-sHfL zfpRSO7KPOuHDsBmUl8savfKtWLz*p`AuSfokQElqkd+qAkX07Vko_#0A^Tf2LsnZf zLk_TrAqQHv$EMv&=mNDc6%NTN^WehpVGKQRN8ADF792l}Bv`)5v#*=cT<1Gyg zc}ER7HLT{SA!m5{x7_z}KhFoMBLoT+AA(vRjkV`FN$Yqu>UiZkRL2#$d8sW zXCrq|qz=@FU7jW8>?H6!5 zknI<6I+E=da5|Cg7jV+Z_6s=aWPSlB1HdofL;?H)P9}g~z{vve3pkwt`~prF0Kb3} z1Mmwt*#Le4CkMbU;B*D>3pm{X`~psQ0Kb6K1Hdof^aSt=INJgE1)N?0egS8D0Kb5f z3*Z-UdIR_coIU`40jDp3U%=@H5J5VpdMR#bf(Q~_s7;)Z8(7p|ZY_8_xM9^xE!xHP z^e1h6i*{vrv#3AWEE+&Ii}J{3(Ll0UG>B{#<&({#0EE*5Mq6q*jDgdP<$!1Xl*(}W6>c1EIJf`MTY^f=x_iQ9Ra|iBLP^n27pCJ z0kG(302ZwUV9_xEEIJl|MaKcK=y(7YodCe169HIs5&(-%24K-C04zEcfJLVPuxK41 zuxPm(%94{=G)wOGdd+6hBE5<}-3_Z>YSG!Qr$5Q&TXYV?n?>i6&7$+jX3=`GS#&4O zMb`qb=sExvT@S#b8vt0e5r9QE0N02bX0z@l3KSad4@i*5s8(d_^%x&shcbfz1c zE`mhQ*XyFQ%%Y$CwwN1Mztp08TyM2JSn(~om*LH#`^aX|{baM~0kT>2AlWQ>h-?;Z zCYwbMlg*+>$Y#-_WGs3NfJKi3u;>W@7Ci~TqNe~@^fUmAo&jLdvj8l54uD0^1F+}? z02aLnz@nD`SoAUgi(Ua>(W?L~dJTX@uLH2?4FDFs3BaPa09f=kAh76eH*|pr5`9d? z*<=lZpA_{iiZHxc)She>bs(EX9m!@)7G(jjs51bIx&W{!2Ed|h02bu{u&65li@E`@s5=0QdH}GfCjg7K17J}v02XZz zz@l6L7WD>TQ6B&n^#x#2KL8f(0N_}(BLItb0t6O$DWP3OkmwM30PeL*30nFc0sHzD0QqZx#(Cn?-}jW>G%bEGi(IMT5y^(Gap(G?Z)>4I`UH!^v1Q z0)Ry$0a!E&fJLJLSTqKJMPmV2G!B48y8*ChJOGO(0I;YKfJH?BEGhb02ZwSVA1IS zEII>#MP~v6i&mtB{t!W;>-DbVO0#IX9+=Kb39Daf(RnGJ{-nBZ(RzkAi_RyTMHi6G zq6^7p(FU?vbP?Gsx|nPhT|zdCE+v~qmyxmPasU=x0l=aw0a$bu0E?~$V9_-IEV>qe zMb`na=z0Ja-2lL%jQ}jV5r9QE0kG(102bW>z@l3LSacfzi*5&C(H#IRx)Xp!cLA{I zZa`qsIVqtc5hS|3yfec)*DM+%Z{+bdrG(Wlwdnp7Z%%<(^Z>(~MGunAqKC+4(Ppw) z^f1{hdW38iJxVr<9wVDYkCV-!C&*azBmj$^0$|b804#b2fJM&&u;@7e7CjHZq89*I z^dbO@UIJjz%K$8T1%O4b0c02aLtz@j$*So9_Ui{1iY(c1tldIx|-?*g#sJwRa5 zy(yt%M387teMEnsS@f5_yW{PHV9_4{Ecz3GMSlUX=x+cP$xol3C!0~8sLRPj-*)N(uqXw9MIitdr2??X z0|XX*m=bzM1c}zl6Ateqv*=k3?LuMoOD*aU^1c~n7IkEJv#1l$!1X(G8V-ESdEiHvkrO2VhYT02cKGV9|B}Eb0Zo zqU`}#lncP3-T*A>1Hhub04(YUz@i-hShOPmi*^EF(ar!Y+690`y8;4>BB4;1;bPHj z`S5_(J`}X{JEchI9}25qYSEyOH*BO?l+W;HQ32U38ca5ehLFvop=7gY7}+cuPBx21 zkjzMSX2zaq7ncWl>)G+ z41h%w0a!E%fJNm1ESe0!qA36@ssLb7B>;=609aHF2rSAAg=UH%(f)e)8E6*e$;T|b znowB%Qj6+C-hrddq6UUHi*_fQMbpS;(R8v|G=ppw%_N&edyvhdJ;`R#USzXqZ!#9e z0a!E(fJKb}ESe3#qB#I8nhU_9CIA-A17Oj702VC(V9`PV7VQJTqJ05avAjAhKC>Fxf0RglrZaN;ZoQBb!Bslg*+d$Y#-zWGq?(z@no7SadW1 zi`D|L=okPN9Sgvs;{aH6JOGPM0ASIH04zEQfJG+*u;>&37M%*fqSF9av<`qprvtF) z3;-6L3BaPW09bT30E^B61QzWV3VkAiM4#0Q>ix~4Dz)g`P+0v^i!KOx;qhkCg$!>N zZ6KRP7m>}Pi^*ouC1kVcQnFce8QCnloNN|dK{ku7BxBK404%y1fJN5;u;^L<7F`Fx zqU!-zbOQj3HUhBdMgSJw1i+%30a$bk0E=z~V9{*=EV>*47QG64N39srBl0k9|xz@i8su;`Oe z=nfGidWOEg=u@+(QJ;XcPYtVIYEfFM_j;*Wl+N&GQ3ly8ijvKuOtM*&MK+5%lg*+o zWV0wnHjA>!W>F3qi@E}^s2c!_x&yGN2LOwD0M17Oh(04&-OfJHk2uxMuh7VQGSqFn)4)E|IF0{~c*2M8?cm>T*^1c}})pG@{T zr3Nki*YtC#15?B5ms&J9)!TlOSu}*<&7z@XvuGIEEE-NWi$;*mqLE~?XcXBj8cjBf z#*odTv1BY72f(7;09Z60fJGAkSX2nWq9Onm6$7xS1b{`Q04yp4V9`VX7EJpY$55S@Y04!Pvz@mKsShOzyixvT}XfXhbmH@D5DFBO>0kCK}0E?Od zSkwZ*q7?uvS_#0SRRAp74-ihqEi4^bSeOgP6J@kIsg`(4#1)_09bS;0E^B7VA0tCEIJ2( zMdt#r=sW-xtp@}a9grG&P6UbmD$zU8EE=M>AkR+?t6yr-MXBC*Rc6t}3~v@)LN<#o zC7VT;kvRQN$*(|!6Y!+QZ#-eKhSacl#i>?P?(G37B+6cg+8v$5! z699{D24K-G04%x{fJL_fu;_LG7Tp2BqB{XtbQb`N?gn7dCIA-Q1Hhtt0a$b&0E_Mi zV9^7Bz@iINL)q10(Y_fX&IYq+n7(87!PKz&r4~Js>W!Fc7Cp-FX3=A0v*>ZMS@Z}^xnFJ^^U zBcNy>0Y&cWIR0Y#q^JVlQ;^-nQCg6-^+*b`Dz znQVqHng*;dtLU4i?nzZr^ex*<(Ra*J^gXi_{lF|mKQc?vPs~#EGqV)!XO^O0n5F0d zGm3sCpy)ROihd`c=nn#l{v@F2F9M1V5>WIv0Y(21Q1mYWMUJc8b`<#tC~87Lk)ME~ zrUVqZ1Qf*)P!u4bD4u|#1Okc@2`EY;c#6Ji>c7eW2~M+ztG||_Gwq&!vKz3ztfHXn zK2{?|>1;1W8O&1Dj9H4BGfPp3S&A~5rKkn76t!fQqE^gO)S4MZZ3rl8OF&UO0*cxb zP;?jpMOg$Cbs(UqBLPL72q@}IKv5S0iVi2Bs4D?Q-3Tb^PC(HS1QZ=fKv53@ih2@I z)QffTGa^ z6pbOEsF;AFqX;M(OF&Tx0Y#+*6qONBR8Bxq1p!6l2q>x~ps0#~qG|$)Y6za9zOKKQ z0TRqKzmo6vlcG)b;L&(DV0~FdlU=ubvJ@T7_EI#3S&EKfmZD>sr6|lSMaMBqQ7y9+ zO=Xs%Y0OeIof$=S1Qg96plBumMY9MfnoU5_90H2w5>PacfTH;X6fGd2XdwYbiwG!M zOhC~R0*dMhC|XKD(J}&xmJ?8PJOM>32q;=fK+y>VPtiozztjK;X4}tQPm-eD_HVB` z(G6H%R?*3>yJdT|2fTD{CDB4Cq z(ZvK5T|z+7b^?knC7|ds0*Wptc#2MP{r4Im!J+nZ*Q=#yV!9cwa0AwtRdluMzI&_` zUBmWLbS<+K?PQjs>zJkJdS)rQfmw=fWR{{`%u;j{vlQLTjG|izD7uw^qT2{4x}AWc zI|wM+O+e8e0*dY=py)0FitZ+$=pF)!?j@k;J_3sFC!pv70*W3apy(k2iXJAQ=n(>n z9wngYF#?JnCwPjka{W%&D0WIW0Y&==D0-iOq7Mit`jCL4j|eFGn1G^B2q^lLfTGU`DEgd$qAv(2`jUX6uLz!^ zy{^B=00~}h4>Ud{MLwSyzIFrFmsRw=>&~1eML)2;6#d97ML#i1(a+3Mw4YgueqolP z1I$wNE3*{+#wQ8ocZIRq5-A)u%)!BdnT=YPcj3AW8La5Cb&J^j1wGg`m6fc0e+4T^L3 z&y=FUY%fJan5AeavlIlpVQ6&LIRRk1O6Hrt`K+$*t ziY5?HG?Cyb8W87iIm;+|!9Ix%l%lWgA;?K_0qe^uIwsB?JV%O-WqT?Nn!zkZGnr8|i-4lp1Qg97plB`uMe_(KnomH{0s@K_5>T{= zfTG0&6fGg3sGfkLr34f$BcNzG0Y%3XP_%-8qLl;`oj^d*i3Aj_BB1Cbf~V-{IRCK* zNHEL3x}G9MqwGi4R>uXbFRSR(IQQgvQnZ%srDz?q6rIK_MW-`M(RyYnI)hn?&SaLN zvzVpmY-TCiz>K1E2q@Y}K+(Ab6m24)Xfpvt=MhkJJ^@7+5Ky#*fT9ZtDB4Ou(M1Fl zZ6l!QVgiaTA)shG0Y#S*P;?mqMVAv$bOixLR}xTk6~R-qCeDAg0TR65etQ2DDOzP8 zn0CYktS_r*XPo=Q0x7zV?WO2?W+}RXS&D9CmZDwEQgjou6y3}$MYk|Z(XGr!fI6&J9+tfJ@Q z+@!@)^gP>3(F@E{^dhqqy~HdW7eL_IdrvwyzMnKW$1QdNiK+%^3 z6n#ZN(bohNeM3Oew**hoGjaZG10;BpeIM;vDO%?@!*_83>&q(oDb5{NFGWAIy%gvc zfTAD)Md<`j(GPL{{bS&G^+OHn&!DQeFwMTapP0|NZvu+42`I`Tpr{W4MSTe<>PJ9Pe*%gI5IjZA1OEFB zkl@Ak5K$=L?dkt*pV0;e0@jyRG&JDuJ6?*0vAq-xXO^N7%u+OxS&Bw6OHnSf6y-5X zQ9iR26);OtAv21K2q+p&K+zZiii!y+I*Ndzu>=&A5KvS~Kv5Y1Mdbt(RS-}#j)0;{ z0*a~#D5@r)sD^-|@dOl2AfRX>0Y#GtD4I+_(a{7?(cpl;$qJ+BX!}?+M2ar3AHtpz z2v}cM(QyH{(+N^k%l1+9Zx{f3Id8&5>Rvk0YxVg zP_&AGqLTRv*0Y#S+P;>MK>`^(ap?K zbPKZ--O4OQw=ql6?aWei2eTCIW=7E-0*dY=py)0FitZ+$=pF)!?j@k;J_3sFC!pv7 z0*W3apy(k2iXJAQ=n(>n9wngYF#?JnC!pvF0*am_plB}vMNbh>^fUoQ&k#IC*9H8q z86d%-_S5^S1qmohC!i>UfTCsu6g4M!ihd6Gk264mb6XlX`=#h*t0)v7u)eIKR`KpB zr%6$3wwIzd%u>{rS&G^*OHq4fDLRZP|q>5d;(+NkCB#0*ZPPP}GZnqTU1)WfM@8LqJg<0*d+)P}GlrqW%OF4IrRs zAOS^#2q+p%@D#O(_g`y(1i$NK;IxeQ_Vh>E-y|9mAF#fxq7m`#-t|&6lI^8v6tfiN zGD}e&vlQhsOHl!{6csW{Q4zBgjb@gjG0Z3`CZOmj0*b~GP*g%dQ7HjMWdszJ6Hrt^ zK+!k?iYf^xsv@AMnt-Aj0*b~HP&9#nqKO0)O(LLZG66+L6HqjTfTCjvC_0wlDH;~< z|JDErx^_>0xD=ffGDA2%V0~Fd)8gHfv!rM`+e=X$vlPu>mZF)=QZ$QMie@uQ(Hv$e zn#(Lj^O&V*J~N6I5Ky#`fTBeN6fGv8XbAyD^#l|xC7@^-0Y%FRC_0{iq7?)btt6o6 z1OkdqB%o*&0YxVfP_&wWqLT?IT0=n5DFhUqN*E8~msNCAyt{3q z6y41BQgjQm6y3@!MYl0a(e2DqbO*B(?PivuJn2Bt86btuQ5x} z>&#O02D22s$t*>0F-y_g%u@6YvlP9{EJg1zqi7!iMeh?(^Z@}y9}-aX5dlRX6HxRC z0Y#q@Q1lrAMV}K;^aTM$UlLIC6#+$G6HxRG0Y%>uQ1l%EMc)%p^aBA!KN3*%69Gj( z6FfyP#rvCXHj38T&t1PPMFsXFYy0B^)|XZETfE!ld@1^!?WO1sW-0oUS&IH*mZF2q zQuH^o6#c_2MgKBOk&~ePb}8~Pqo@f1MScQ`ni5dt5>OOJKv95zqId#|5(p?tB%mmX zfTCmqic$zDN+qBujew#c0Y&Kq6lD-l)Qo_l<^&Xl2q?-Vpr{4GQ*PbLRF9M2s6Ht^*Kv50>MSTb;>PtXTKLU#S z6HqjOfTDo}6b&MvXfOdqLkK7uN9Zx{f z3Id8&5>Rvk0YxVgP_&AGqLT#6kSX}(Io^FZ6~1UQUZ!DBcSMV0*bC6 zpy)~himoD{Xa@mBR})Zl4FN^h5>T|0fTHUND7v12q8kV(x{=^1Iy1pP)c^?=+Fu?z zONwUO_w;uq1gtNs=+*>x?PXGQ8{13K?aWei2eTCIW|pEo%u;kGvlQLMEJb%SOVK^d zQgkmfitZzz=zao<9w4CTK>~^%BB1DD0*W3Xpy*KoiXJ1N=y3vyo*WIM z0Yy&}Q1lD|Mb8pY^c(?2&l6De0s%!Y5>WIK!Bcc|g8w=LB-qD(?)nxfdekaY^bWHWy~`{`?=ef!K4vL;pIM4NU`El01QdNl zK+(qp6n#QK(We9yeMUgh=L8geK|s-$1QdNmK+)F(6n#TL(YFK?eMdmi_XHIEKtR!t z1Qh*5K+(?x6zwOV=obQt4iG#=uO|4vH$Z|v+c!O4lcF;FBI(zJfc0e+{h8pV?U16s z*j|bbGE33l%u@6ZvlRWyEJaSD_S~h&$1Funn5D?iEJaP3QREU(6h}Z&fPkWS0*Vp{ zC`u%tD2afgWCDs(2q;P=peT)iq96f9=>!yI5Kz>NfTHFE6om*V$|Rtu1p!4Z2`Fks zKv8Rgr|9s3Wr!bz+vH z&dgHOg;|OYXO^O_%u>{iS&F(dqv!|%ijE|ps0RT>Jqal4ML@X@ZV0~Fd1&Qt@JEf?Q?WL%QS&Bw8OVJo+DJo``qNA9lXe_f7l`uy^-?s4?WJfgvlPu^mZJI0QnY|siWV|U(IRFkTFfj(OPHmoo*6|;2`E}dK+$pn zijF6sXaxa9D+wq%fqT|3fTDE-6rDyu z(dh&fttX)93<8SIBzTHuCi>%UFp5sF?|{sbq7n9YK+Z}GSYKAr#zeR4E-5;f?WJfF zvlMM+mZI~RrRaQSDY}4JincII(S^)Xw3S(kE@DQ}HUf$+CZOmN0*ba1P;@B)MVAp! zbU6V_cO5m2;)fTF7jD7uD#qH75#+DSmsbp#Y$Pe9QP1Qgv!K+!G&if$sH z=w^baXhWjE!~h8{OEqxLk)kg4Mba&a0qe^ux+Bq@f3pK+$sq6g^Ks(F+6=y+}aOO9T|XOhC~q1QfkW@D$ya=s(W@ z34UyM?r)c(GpwT55(CzkRrFS(d&jL(^fuc|(L2mi^e(d$y~iv?`7JKtNF<0Yym!6eSZ-ltMsJDgi}l1QZ1cC`u=wD1(5aW&{*9C!i=qKv5svWhw;xg+;T zQ75*SqRz}x)P-4!4ri94uFO)@jaiDiGfUAC%u;kDvlR7UMo~`!ih2=H)SG~!YyygM z2q@}9Kv7=;iuw^y)SrN&0R$8cB%o*z0Y!reC>laQ(NF@4h7nLSoPeSc1Qd-VplB2U zMY#kN**q3RquO(dZ=iw7aBe4BJalF|!mM#Vkc* znWd12jkNdfE2Dw>z%K6{T8&1ZWlTEHwt3z?;85wjF6W|pEQ%u-a(EJaJ1 zrDz$m6fI{)(eVTntstOiB>_bz5Kwd?0Y$3_C_0INqSXWxolHQ{8Ul(=A)x3~0*clW zP_&MKqSFW{I-P)`^#l~1K|s-&1QeY`K+)L*6m1}QismHwe>6aXx7y#Zo-0MKn6J6# zBn7N5t7vnQn|{9(oyYc4bUw2bUBE0wTbQNjLS`x2$}B|}F-y@lW+}RuS&A-UM$vWx ziY_If=rRI|E+?Sq3Id9*B%tUj0*ZDJP;@l`Mb{8ebS(izI|(Sdj)0=;2`IXOfT9}- zDB49p(M<#t-Aq8yEd&(ZNIIJ;*FY4>3#8!^|jpgn*()2`GAufTG6< zD0+f`q9+L`+DkyuQv?(}O+e8z1Qb0>K+$sq6g^Ks(F+6=y+}aOO9T|XOhC~q1QfkW zK+$Ui6unMB(HjI$(e5PwDgz|=uKjh`JyLXyePDVsDPVnBMeioLmp&{-@3FlU?PHdr z_nD>W17<1ukXed8VwR$hnWg9xW-0oVS&BYmM$zX46n#NJ(U$}ieMLag*8~)OLqO5D z1QdNoK+*RE6#YOz(T@Za{X{^~&jb|hC!pvT0*Ve0Q1mMSMZXbH^g97Xe-KdgCjmu& z5j;h2C;1;WK!Ru6!`1Id(V+HbIG7Z$zN{iA+5O~EDe@(2PhN_eFiVl2S&Eu6OOeYg zMRCkh6kwL3cxEX|V3wjpW)vk6P?StSQ3?S?sRR_I5l|E)peUVyq6`9xnh{XcoPeSb z0Y#Yv6ty6rs3ieKtq3S;O+Zl_0*cxaP}GiqqV@z79Y#P=7Qs{WPm(|WF{7xhJzn&$ z6n$wGbx00aUsh3MSTb;>PtXTKLU#S6HqjOfTDo}6b&MvXfOdqLkK7uNXhs+GeCm7?cY4pIoaFOKhwT7Ta+BIzO167 zlHG-SrD!bMOHm246qPbdQ5mxol`~6G1+x^5W0s;yW+|#-mZEBA6x9$=G@gK>2?P{P zB%o*#0Y#GuC_0*eqA3Iv9Ya9Tu>=%_2`D;_fTCIgil!1!G>w3w=>!zj5l}RPfTEcM z6wM-_Xf^>wa|oWIG0FZ543OX$dx)r5iVoPnKxA%m!1}U^7ACuUo|d9TY%fKNnWbn6 zvlP`cOVLthDO$!XMa!9`=y+x+TEQ$uE16Mr0s%!Q5>T{?fTEKKC|XTG(a8i9ts$W3 z6atD)C7@_60Y&QwC_0URqSFZ|T2DaH83YuaNkGwA1QeZ3K+y&Qiq0XRXd?kd=Mp?c z^OODW7$Cv9_H)+@q-eE0c(f@wV0~Fd7bLrXJu5|9*j|b*WR{|>%u;j_vlMM(mZFQ9 zrRWl7Dca5~MVB&5(Phjix}1QbD+nmMl7OPC2q@Y?K+)9%6kS6=(X|8=?IfV+Is%HW zC!pvC0*Y=VplBBXMK=*pbTa`(w-8WtD*;8f5m0nH0Y!HZP_&!iDLOCNpY@zkbhiE6 z_4!itynSnSPjbNevWo6Wc5`2lqI=n1itb~UqWhVp=mBOadXQO)9%7cFhnc155oRfR zlv#=%V@A>A1Qb0%K+%%~6zwIT=qUnH#4JT0GfUAY%u@6zvlM;CEJdF)OVJn1QuHM=ioPPC z=xYLsz9FFKTLOx{BcSMe0*Zbhpy)>eihd%X=w||o_7hO_3jsw32q^lMfTG_BDEgg% zqCW^I`jdd7zX&KgNI=ow1Qh*4@D#n5?B8X81QYF1$9+V8FfTETJ6tyCts5JpaZ3rl8OF&UO0*cxbP;?jpMOg$C zbs(UqBLPL72%aKeivMQ=Bsj-@)VfKEw~w~GxfwdA1gtNss9TEL>~$&X&h~mNI)Yh> zj%1di9?VkIlUa&-F-uWzW+}>MmZBVHDeA+FqP_$a^&_CDKLJGp2q+pzK+zxqiUt!< zG=zYnp#&5SBcNzF0YxJSC>lvX(I^6natSEPBcLdsfT98diV6uRDk7k0Gyz3p2%e(D zQ~ZMrkl>Sc=f0~H{c9B!rv$7otEe=^o%E&@m9f1Pl`~6G1+x^5W0s;yW+|#-mZEBA zDXL+XqVdd9G=UjK6A37qL_pDG0*a0%plAvKMaK|ObSwcyVFHSdBcQ03fTF1c6ip+b zXgUE!bp#a6AfRX_0Y$S2D4I<`(HsJb<`PgekAR~21W(b}6#r@iB)HRl?z%*Zy4e>= z3sM5smsPYR#l8G(DXM3CDO$=bMa!6_XgRYK9nUO9E10EdC9@Qrz$`^4GE31aW)z)7 zK+$RficTh=Xbk~Hrw~wdDgi}n2`E}eK+$Og6rD~$(Ru=k&LE)ZOah9|BB1DO0*W>e zP;?FfMH>kyI+uW=O#~EeCZOm%f~ROvivMu~B)Hu^{4AEDIjLqiKP6y&Sw&k@+|S;X zqKnvGincLJ(Z$SCbP2N*ZD*FEOPQtUGG-~doLP#lV3wjQnNf5V0Yy6qD7u<}qH72! zx|V>VodgtJM?lf_1QgvsK+%l^6zw9Q=q3V+ZYH4U76OWHC7|dw0*Y=Ypy&<)igpuF zw1&q&-KgB)reJOf??WO2JW+{4z zS&ANJmZC?PrRY&+DSC`qiXLZ{q9>T8=t*W2?Iob-DFTX~CZOmU0*am`py)XQik>H+ z=mi3bUL>ICB?5|GCZOmQ0*YQGpy)LMie4w6=nVpj-Xx&tEdq+(CZOmY0*c-xpy)k< zr|8}ke}w@O+~2~$xlf8h_C?aZlz{bR6@8TAF8)x8K4yC<`h;1EK4q4o&zPm?b7m>} zf?0~bWR{|@n5F1zW-0oH8Aaa`Q1l%EMc)%p^aBA!KN3*%69Gj(6Hv6DfTCXrC^|qu z(XRv){YF61?*tV6K|s-;1Qh*6K+!=0ivA{`=pO=#{w1KuN!5-yihKl5(FZC13k{H9 ziT!xvhf?%r2QxHD4Om}RQCzBf*T+&6V0$TwXO^M_W+_T!mZBtPDN1IRq7-H+N@bR! zG-fFZGNUM+fT9cnikcBn)SQ5#5CKJ*1QfL(pr|DQMXd-ZYE3{<8v=^j5>V8RfTH#U z6dguDQ5FG39SA7uNI+310*X2lP}GHhqQeQEqNb_-_Y9EWF8jeWH`UwIKhgeGpQMS}?_8bUzPPy&jE5l}RofT9ru6pbXHXcPfOxdasD5m1y*Kv4k!MTGiC zswJRkDgi~)2q>CPKv5k5MKcH}nn^&>ECPyV6HqjVfTFns6wM=`Xg&c&3kWD$NI=md zf~Tk~)j!Js3GTNaZ!DLh5%wLB#i;@7%PLxy>Yn+P6fI|aDLS56idHa7(Mo11I)Pb= zPGpv%Rm@U!60;PoW|pFpnNhTcfTB|fC_0sZqO}ARts|i5Gy;lFC!lCO0YzsJP;@2% zMQ0IEbT$D+8we;mhk&Au1QeZ1K+z@wiZ&BabRGdk=MzwL0Rcr@2%e()RR7HeNN|9C z5?d-o9WAK~Qv=qQRdjKx`{FlJbP3x_(ROAjx|CUpE@PIW%bBI<3T7#~l39wbVwR#E z%u;kUGm5Supy*lxigprEbR7Xj*Aq~50|7-h5>T{@fTEiSD7u+|qFV?kx|M*U+XyJS zoq(b{2q@Z3K+zroitZ$!=q>_^?k1q<9s-K)C3uQ1O7;I@fCRs`pS#{BMFmaFa9?V` z`m%~1N_9iuOVPt@FGY_qOVOjuQuG+J6g|!?MNcqG(UZ(lw3k_mo?@1wrWIU0Y%RfQ1k);MK2Oi^b!F@FB4Go3IRp05>WIS0Y$G9Q1k`?MQ;*N^cDd{Zxc}T z4gp2)5>WIW0Y&==D0-iOq7Mk3q6bp_Lky7MtM+r(4@%KwzZpJE4Om}R(Wj~I(LYMj zXKXJ;pEFC*7tB)hC9@QL#Vkc%GfUAo%u@6%vlM;DEJfclqv!_$ihd-Z=qCb-ekP!3 zKLJI*5Kwf0fTCXsDEf_nqTdN9`h$R?KM5%Mi-4ko1Qh*EK+!)06#Yv;k&~v~b`<#t zC~87Lk)ME~rUXyX$Ep4`21sy={oM5@QZ&(iWX(+rSYK9ALYjN!&r+1g_EMC@EJex8 zQk23hMXAhEl*TMYL1rmRXO^N2W+`gMjH2cQ6om*V$|Rtu1p!4Z2`FksKv8P~irNrR z)Rusvb_5i)C!pvs0*bN-DC$5!QAYxbIuTIRnSi1$1QZ=kKv7o$infTFPk6qOKAR7yZm8NpN3Bh8HY5qzBB=~^+U|OXV-D4FkO$%6GR?&(yxBd?)TFLfO zbON&!oyaUjtC*$eBxWgE%`8PHGfUALW+^&_S&B|&M$uXViq;WObQ%FgrxQ@Lo`9k= z2q-#}fTFVqC_0;fq74KTokKv;Mgoe?C7@^%0Y#e$C_0aTqVowTx`2S9Ed&%@NI=n6 z0*Wpoc#4*%`7bg+g4^tq*zr&q&7G|m0@Zz+0=?WO2(W+{4tS&E)ymZH7PQuGwF6g|x> zMb9ux(X-4_^c*vao+qH_1pie4q4=rsb0UMHaF4FZbZB%tUm z0*c-ypy(X}iryul=sg08_7PC@J^@7^5K#0X0Yx7XQ1mguQ}l3}zwKWfgsq<`z2k49w@QzhrwU`ifbKzGjx9Zy)eMLq(Gnh;RrC!nY)0YxqWMR5ca1qhy^&(i#J43OYM_TP>DT#6j~ zrdoV3V0~Fd$wBw*CQ_8b_EMC}EJbO|QWRvCqI6~{%3zkFX3SF5oLP!O%usr6|lSMaMCtsFr}DsRR^FBcNzH0Y!BL6wM%@XeI$gvj`}fO+e8c z0*dAmP&AK#qWJ_AEg+z1Apu2;2q;=iK+zHcis}g{T1r6CG6IU06Ff!LLH{rVBzU&{ z#B7Ze4YIra#|Hz}msNCP&^;zWidM0`6rIE@MXQ;m=wxOoTEi?wr!Y&=smxNemRX9{ zF-y^D%qTjYfTHyT6rDjp(U}Akokc*=*#s1AAfV_R0*W>gP;@QDt zR?!tfcSn*GUCH)RbQQA{?O>LotC^+f8fGcFmRX8+GE32Q%u;kcvlQLHjG`L}DB49p z(M<#t-Aq8yEd&(ZN^Z)@x4-!!H5CKIG6Ffzi1^rJMAi;9`HvZ*ObdCLmkVk?6>&q&7BItgVB1KQK zy%g=V8HsaioOoIy@OKp4ckl6x6D%X9kUdD z&n!hhFiX*o%u@6dvlRWzEJgd7rRW!C6dfR-=vM-Yej}jhcLIw3AfV_^0*d}3py(h0 zMSl}e^bY|={}NE-q-(bwMLq(Gnh;RrC!nY)0YxqWMR5ca1qdjLC!i>SfTBc#r|8R| zzuEu^9_VP`d?iKqrI;ZpJz#xVMQQ2ovJ5E-vb_|gGfPnhvlKOBmZIj&QWRpAqD*Ef zYQZc;Et#dL6*G!j6HwHKfTFep6tyFus67EihY?VeMLqbs?bW zZ~}_D5>V8QfTHdM6dgf8(UAlc^&p_ACjmvh2q@}J@D!z_`!6;?f;(LUCpF#M)8Ao_ zI%cN_tS_smU%Go=b1CZ2_EI!}S&9ZSOVJ=^DH_ZyMMIdSXehH34P%y~;mlGrf*D04 z2`CyxKv6CMMR^1i}_ z(Jp2wx``P@Hxp2F3jsy95>Rv-0Y$eHP;>_YMY{kL_pEQ1Qb0&K+&TF6g@`p6kVC_zuf={7AG4xS4q)UtLX9c zfc0e+J(cdh+D?j|W_u}mhFOZ9WtO7nn5F1>W+{4sS&Cj{mZF!KrRZg5DSCw&MXwT2 z^cn$0uM<%81_4EH5>WIO0Yz^UQ1lJ~Meh<&^d134`v@p{pMatd2q^lHfTE8GDEgRy zqE84Y`jmj8&j={`oPeS)2q^lJ;3;}C-T%7*5**vcz}YKB7uerw{3<=x+jw{vn{~UjmAp4DGg~$VWg?69S6-1QazTpvWblD2{-l00Bku1QaC@P?ShO zQ4#?~$pjRo5IjZSr29u0Ai<;z1Ls>5*|$SdGXmC^Rg{t8hC518Gq#ta=FCzQVwR#z zW+`gHEJZDurKlCN6t!lSqBhJ@)Rq}V?FcApPe9RO1QcZvP}G5dqK*UYw3%#sCRs*f%`}NYSpy4qHaR z`m&0qWVqiPE=9+%y%ZhGEJa~vDLRf>ifWmqXezT5O=Fg#>C948$1FuNm{By7fTCFh z6wM}}Xbu5Ia|tM#M?leh0*V$8P_&SMqD2H0EheC72?0g*1QabLplBHZMau~&I-Y={ z6$BKmB%tU70*X!~plB7rQ#3ilAM9!r-Dy8}eY6xkWq+&jq>O;|Wfh&0;pTLgqEp#k ziq)^~_Rq2D22M$t*=@F-y_e%qZGGK+!n_6m2A+=v)GdHW5&? znSi462q-$AfT9ZsDB40m(S-yQZ6%=SA_9uG5m0n70Y#S(P_&(ZqDu)Vx{QFL%LypD zf`Fnc37(>pGyLNXkl@v3bk|5xx+Qg0M!@=VnmbM0P6=1`@HwHL=2f>7DmQ-}ZPUk-ZZa#AxdeeLopn0f``RHxSP^~$KwxONo1C&{z@64;L&Y`~Mmv6g; zR(5cl9-)WKUzU^|au0W$exb459A{8y^AV0SEc9j%#~BrB*V}OlLep{_XH4k&zK&B8 z`k}w$RD}8ua-8bWi9;M`V(5`!jx!|`80k32g-UZBXL{)Te8-s;db`kZ=7kO$<2Z{# zbw@eQ($I}1jwe3Jo0RIBP;DRXNVO&|@`@b4Dm(qT_4`l}~n@O`$DQ9Or`2 zyT>}tMWGJ0j9bDHB^5xS|)ajp*SpXoT)g$B=YoL!-l=Q+-;p(hqN&hAjsV#m2V zG_Kxp?hkEU<~R?B_8spykB2&);5bi(X0LLb=R&uvcAS?&2i7>wYoVcQ9p|mkDW^Hk zd!fDS9p}SP%2|%{X{c(0<9r#~w$X9E4Slf5aefSSIp1-93C-Q&IKPK(+v+$6Gk@D= zu76+V@a^^^vYBfyGq->*^XV(hP2kH++hJ}4UuMlU=0@;kUb55N3ck#bt~WP>FSF|| zb36Dl?Z0N<*_UbmIr474O#AOi_wZ%fe-Jp^mude+*M7cC`%iKX@@3k8Q*oFt)BdA) zqkNf{K5T9fU#9(MsmAy+?Y}Ej;>)!EFieFn)BejI)xJ#oPcuyPW!k@6e~K^D{^jV$ z`7-U_Zav+XY5#iSS-wpB_sh=nW!k?WbdfL9{tb^yeVO*J=v(2-w13CiDqp7kOS0DZ zGVR}Tw9c1l|C*XJe3|y|8QI{=w0}{=CSRugP5%pgnf6z;FY;yD-?iQD%e22Nd4(_2 z{kmO#7*) z$9{6|_DyPL z7W?0O=6}BJJ$w0_mV?Z{A@A$kx2ySzIa(6=uhpk!_t)1y^;|o(x;fPh12pWh!$1vB zn7f~EP^v*@PWH6WZ2?J!J3sr}x=HSF$ah7lT?npY^k zks59?cW~b*Z)k1q!j8S*H}&*6ZG07R>DO)E{`{&ozHxEsZ(VcFjuYGXD&x}EoqOhn z6>WS~Zt~YFCS^Endzg)en2lN&nLms+e|Xy4+L!ILHuuWN86M;e58So)k(10By2%3% zJJ`vbpPQWY#lBgQv)g%V_c=~Gb0>1D&AFKG??te;#@QQU>@e||Khs%6Wcd8)&4K8sXxx~ zrTe<1HcRrSwn?pNk?sq&aGWNcous4@COM8j)A6ScNgA3oIH|aqxr^#6<|cIeJGR6% z_4!jrBqfI_})43pB#x3cGx+{~Ah)Nl?d zDULs$@0*mAl9Ze@$edqli$=td#I@RYiX}LMi=xb}f;MgxXPCHIxZq{DT$X3HzEl7=gS93WH zi`f4ri@h5*b@uxzE;oOO{MXj}zoBpbYa01~`+xRSvH!)+ zN#wD;F(YXv4I+>C2YX)yI6zp5B~#aPLJ+X3w9!boTN(r}wOd^Xq!o&Z}F|yVtyh z(`x7SuAf!Aq^|dpx&?Lhwe`L0`h@G3E}K4kVeh327tWhDt9JH+`rb3AO$*m9ncq7n zJKQ(iC%aEhI49f2o+kEOuy8?L&$`;FvwP-b_v+izez}+Va-%Qxp1ok&yk*ntde5(& zHf#2R|K}H@er0{^H8FEm@7yKRm(5(mH!vIF1oIL zbDPDPP2+mUWySUG9T_q@xXli;$<2s-Dcfn%)E9D-?2_hou#4%Dv6nenA2(!AHr8!c zY&Y_@$};EQ-i#d^ZJQOlZB}I4)^=NS7H!Sc!HrBgZm38F^m|*>Bikc;sSc zb#$BAuQa}RhkOfPUpMFv_i}yy4!yFPv@>`9qN<8;VP$2wxNLlGNpV3qw{mn%X<=El z!xu^mtEzHG7ly0L%flt*Wuu+S!qMTJ-25@oQ{-1y)tK$`%S$Ut3aia2Ys!jsx}y9s z;i(NL%&ja4mz7tW6IT^hRu>jTzj9QCIn$c5s+x+5a{GmFMe)SKl5kOZWod4;_Z`hy zH9mP>NqPR*a6xW$Zn&(bG_SDI{v73%-l_Wziv7lA<>9KDysG@lVtcZp@|v=O$jJr{ z8WULuH@cXWg;f>h<`R16)X$uT>%w04!phvLm`l#}R$4VWoL5s+WX`{;cyeKMlmGb1 zic9Ua899x;CiAjmFKBUDxQ1^$SQjp*sL@ICD<@S{mzy8Cq$FHXUR+jPs2{nHPM>R5 zb8qU~C%iQB6BIPsJg>yul`4xOH$!1rt{DrQ@}jD6Zh?0;{UfKgm#iq}2QRE1!}S}k z7&9qsZtGHWE9d7{7nhfL*VEwWhB^5$TNYQ23+EYQ1;tg~H{-hW&eEP)&tMz@CSxSGP6!f=tfrlMb} z$gM1{o)jG|>eAe@NxJD8&LVQNRh3soEUrG53#fRe4cSxY3Do z1~)o&er{Q~x-z${s*gSXS)l_-cvbk@> zJ|1~@C5zcy$@b1|uaB6`D<_(}bhvzcVP#QC`GiBiX=T~y=)i>xceJi=Dz znn#GSg_FWXxyANg&TXhu*ymJp(aLKo%^%Ettf-_ozu{3oqSQW^MX$P?KG8e4xvM+n z%a#_@F0Bn$*RAj#W^&A(ar(0P^H)Z{QRKc+SYF)tKE%Z^kIALwmG-u=51QT`x=-ZZ zGH>C6nOWu$EYkX!?-lvsbIc#u)?A@gH9ZJd7M2u79;ofcg^f{pH@m$8 z%q?47h0JP`XJ((vGxQy9IG?H{8*gv=Nw z=HZ}5&y40`Hk`nG)4a-D^XxBe_B)!}F81DLu1Fr4OUkQse;*Y6hUP}{uHQWVP#ED* zKYQkay6IVF4`E64+gbYMMds`bp@v8EhDVG1{POS^^C%YGfa|8TyuiEk<^@9Zi}{5m zB{e0vmFE61y12^Fx6f+)AeiIf!MlvvX7k98*y!=SrYbM;%pR^9V_wF1r!-H+K6%C5$~l7? z-5*3{j5(*6*JB0zSmwq(#6+=uq&(y?D)#k;d7y~g!6R2s^q!H^ztI_S=i=6idFpQj z=f6JjHMl7$D33hmMxSSN8+$j2c?i-?nUkaEGxPi&y#je8$PO2bs}2{8@t)!vzaAJ6 zb9z0Bm72$?n##yCSLBhh$Xp>+V`3h#v0IWm$-cTgMi z_8Q0fA=fy!e$4CS5_4Z@xc#{lqjO73bEB8SUO(n#7*~tA$40KIhI@5RPDID(vYM>? z!Gp8xo_nvHEW7WXJ*ZE=tZqx{=GE2K*LBb8Ie*%sWy7Z}T(Y!oMbG(t`x_8|YnS#kJO0DXW59G9%qeFqTHe2B{i2@Ja|W1FyJXs|;pRxd@>G-t2^%wcfPp=D999M}EYCjr>J!d+({ozO;|rkcDOCHRd7c|Kw2>4$4IK zrXzQV#;@+9PmJaTVs2h>N%7={SLoU1@!W3Gx6z|=!$XL@A4V-V+$GGDnt5=kHZN}N zD~0F@;1JmhYfxhDtoi13M_#VkHPfTB{hns8BJ#a+1~%M<%%kcgbLVRtjSpFBY4;_V^wUA4&=7f^&-vee)!dEDRh(n?5e2AW*Rb&(pEVeT&IPHeC=P4S-JT75 znz_+)GfyU*v3&)l?_pjX>rXjm&mwyHVy=OT%JMPAX5Z7?6lLZq(;Um-TSkc33u2iR zn^(7!4Tf;o9J*~dvXWz7o||tF*$YwnLu(bF1tjx#-axb03PHX>?yO zH!pHOU~cf2xxjM_|t?E_#0{nh>rr2h7ZssWa61nZspVgXV!l zf3&-Qx|9v)WDXBh*~i5Om-Zz8^;Iu7Zlgnhjb4C9U(mCI>+NxIE$Aw3e9z>zid-M& zrImMmnEkq#>%%_X*`1qk)r8_|^OczAPIdru8V)q%m`7%(ewKN$72VOcyL*vuV4jX6 zf3UlEHh6nskuSyEq0GzghHJ>72;ChRB_v-)Ddo~4iQe?B#Odu;ri(F1vrvurrhonwx>#om<~jt|)%*1Holdhm(v=i76PUX8KdqC3jE zZX*YwBj1)s@P_9u?})PfqTM@;oX8$tLKu z{Lit6Vma^Fi(FJ(VqTEN9ztk%Nm5mnuQz@gT@T;|qd9!4R|*Tg7wVCvkM|7O=pu0e zq7T#2D=g-L%kE8bLcWCuJ^I8Mxwc{tn?@k~x945&Q8;?=jPs4Wox{DJXm8fa8t)Oz zKHk#x=xlD&#z$sj_G-*wo5)RQo~i$n6hDM{xHHd2dhM>aY1kba*l0txFfT}r?gH~t zB<3{=UyQz)#B-&$bK!9_7eBJQr2A3KPZN9NH+uI)KW0tY*s}5o-nGE~i#>dA&)3^I z;Cjh32dm9nagn!4B44&UCwwvHRYIeqFOiF9j~d%Q*j<-Mutz*2fAEgk+CQ?hk`sHd zQ|D@r!55jkMC`$)#yb(bXo;MuxpJeID{{Xw&qdX_mG)Jhv2R{c{7?6=H|Xs7HoQ~S@ESg+U-Ur? z_Brh}G+Lm$lTlazhOn+G4>F=flV zlH9Vf<}O=k4p|-Y;>P|chn~FQrYI>l@6eeC5ObI`w=Cw+n7ut3AK>tIFud2>jh+T0 zKV!r3Q}4Y3E?C1$t46yM_UsM)8uMdu+3eYPy91Fw@et}Aq6~-GXXT7z9+AgXjx{%y zcjqfMH+;h(vI)6nx0nadL$W9*Zlcl|_;az=gUY|T) zG@OTb>r5!G9IF?T(dYXd^E%P|(45pfwD877<9(bW^X4?W2lhh~&glI7Az9t*LHXPz z^Ro)gn~&3{oA=nN`6OQCI6a@R>;69A*u+}EGBB`0dBdV*c~%W0EAl{j^!ke}3~xGxJ*m zG5$OA#>>=^KpmFe9A8JenaP_ zPUq?WUvFQ>96HZF-kr_=63vfkKeC-@e*Y}bt|9Z$Y4y|XYCc15 zulXkC>b3Ton9nxbYs#+Xq>;6iUCkFe*wx&q_WbPEtv9<4&^lbJ{XVu=Xsyv|KED|0 z=JzTh>td}ZYh9;xlh!M>-l6p#tq*B6znl;`pJ%nctkwMTL8R}~`ia)BwEm#=fL8O% z1Ci6)kM7#bZU1&lyP97Ph^)=D+P}rX_QSMx(R!rT9IXSj4%eEmwODJp)*7uxYpvBf zQ|o-K^;%bIJz48%TF=(HS?gAv-K+Hlt*>i+PwOXIzt;Mb z*59?72d~KW6lXp?8o3^|HrLulYe%i!wPtG_sC9(aLailQtF%tmTB~)I)`eP^YduNp zI<04GJx}X4tygH>sr6>9d$iuK^)ao_Xnk4hTUtNR`nlHcwEm*?FRe|?L#Dlc60`=j zw$R#MYZt9OwD#3HL~E|rFsMNT)cTv&f3&*hslr}Q$y%FfZLPI~)^1vRYaO6swks()zX5{aO!db z616th+DYp`^IUB&f4$IL|o}=x&UhAdirI4Mk*ZPoog17UtT0b(c5$yb( z*2B$f0z3EBI?wzDj-6L(z1{o{nVs#wnPJ!8&5KmKy5_ge>^kBwZyl?3T?cR8to4~r z-u$N4;NjlfPV0E{0>hrqG_Bi@@aF5aer$f7%zpg`t=-HE5j*$Sx**4!Pt>}*uQxxU z_0Rs^9563j>~^CDd26ZG(}#HT`C6YF=FM+w%^2y;hiRRd>&TA zJz|VE57fHoC~rPV>zyUu{Fv5*W!{`n?yY&_ytQ2G8CBlAMe7UZ1(*G~-qqTCqBnQY zI(f1;&(wOw6mPys>*vRM^M0*8YQ1@|)+N)t`DCqk*Lm|3TK}2p%}KMowP237j?;S9 zJa68r^`!;gyiaT9VsGxGbxOTA&(?a?GH<>`>zBuS^8u~BPVnZTT9>Z!=2NuZyV{%g zYIRQW<`k_(YrVNj>xR?3d7IW()_d~@T3epw&0Vw}yTP01YQ1`+H{Yi9Yx4rv-afx+ z%|73ohihHF#hce^y??7WKdrUN#onBzb_>uXnd^G8}+@9^fXT93QN zo9Ao2cBePrq4nGAz4;HVeRg^CNUbYw_U6;HK6tA)KdZIr9p0R-^{74GJVEQGyS({Q zt#6nY`u6(yL~Gmoz4?DJb{9}m*MI!)cX#&7cNP|QD8WL)4n#%71{D*<4r~;$m9V?J zTd}*lySuT$Rul`duU*y^UiVmi z-yO&ApQ!IY<2dl?`W_m`1D~z$<2XHieRMwm?>G+nu)bG~brX!*PB}3TgLJ1uj~8rIKKZ)eNT;J@9*n-u{iEDy}rlC@unH|eSaKhq%XnF zxA)&T4*spahsE*G-|PFNI6jr$!OBnndK}yTQ{O$}xPJQBLjL`&<9KfR!tK1TjN|0= z72J7$9ml@u9kjd`kK@iQ^}SCVZ%JR=oqzwqIR2d8k;}WWQ~kJH`f~5Q*NEfc>Fd7p zJ|&LNq%Q!^`^`AErmqCgd-gbPnBEc0d)qjkpT0Ic@2lhZVfrHRyuXR#yuIsti8$`s zx4!p_<8AZS_rr1gHGLs@KEJX+{kXzH_2XJ`ydr&nhWz`t#_@rCEE*b~k3A_L+ox|m z5XULer^WHNI5wxRxX#zpIgY*JxJVoa$8lI3H;m)9aojzQ2jpXV{>9@&aqJbxzHwYAj*G=Hy?NEp zl&+)}I~`_SUwSio*71|3`Z0Z|q@gLjt<*DmL;vvy>@i{cQRz5gT>ZGSOX>c#6B_#G zJG3_RA2oh_L;rLa-2OTC|9}6=gjr9wW4;qZ`hfCId!?(Gb$R`7Y=2eCki}|17)buhorfOgFTlfBq8C(dlbI{_|XS8n^u(>4}DJxNiULCrlW( z%cy-Oq^te^{bSDbl#S_UewpSU1M7$X{hD5svwrkRzvic_)aU=>>GJR89}A?P`Stt% z^>hQ$)BK;$cXDce{2aG5vH-y4Wyo@y3RG{u5l>_y2gh z1=9zQ(wme2`{C)vrSjkB+q_5PtUptJzPWq8$E3^7Nf#T&r0eUQFT@YOcSPF%y}s4b z_2s`0`TEkk5C6Nq^V4PLq>By5rR&R2=ZD`rJB9yV-^TyBzVzdN!#(qb_~H6Gr~Tij zJ2>6G^xypdet0@xNWMh>y%z7Cex&=74;nmR$-zqwN|y%=SmHmw4jMGDckgAF9-O{3 zAph8|{b9p~uU`K?2lcDXf3sX~F58WpwTk+`2@9r2Q|#F=^X~PBx4U%G%!fAUK7F2I z$n52XF+=-(HfF@nhi|k)`gM!(N3Z_W%;qH~rJoIp z{Q3Tf>CK%|-Fx!Ph5=8_Y*=FQ%;q>&(}S=ubsCWlb-tVk8ZE6K4N-9>jG=NKC`(`!@_^QU)i}f;PG_E`ZHTsX#KId zwSKv}!kA(8OU*0f}&n|+duzS`wp4W zb)zmLMvd8FyMuNf+3?p}@62rI({-ICx68*aYmJ+A?7Ze3vyL;iYg;>?HKbp$_Omk| zTH>r-K4|`H(t@kce0aq4#_svpP@8SYM^8Q2tIJl`o>sZM+XKs-zuCY6Z+$fC;sv+9 zZerh4?m1}trUC1uf4k~dn;Tb7|53Is+bz8zlK=Mn=SNdxyHnC%s;0*3iOE${Q}J~7 zd??rJlkhy9erZ~_=ep_Xo0^Mb(?4#NOOnK<5wmYME0xR6kyf?1E5~Yi`Roa4bCK_W z+0Ha^(Y_coBr!BUrK+<*~k%6ZG>)0;Z;mFx6N|0$F|_emd~Dc?+& zpDPzgx8eD6YP!uYl-<*tGcT4y(%;&b${Fb;@N&6XdhV}OPfnK?ZLD6LZq{Or)icsl z^>3_pN-y!n8>^qBTQ;DvdUraU-dLS4y~NLGtge=B%2|!oQ_{=s?8fSi>BV(UWA%fy z&TXtdlwNG-HCAs+*K&S(l5|rpXsnJ*zjt9{^?`JgE^4g)n4Zzkjn!AvGykQrI)4)M zYh(4$6n|^1PDy{hnT^#0((i5FR9!4RqlcQR$E2J5Ri!#1-H5L%)$!@Sj%k(ZE$KSH zsZ@VY>)T3o({$cMy6SbC ztIMQYyTzxb>$p+2UOVab(u(|qBI&9Qjoija$jhm}&>4Z(1 ztE(rYn>JS`rV$M7x)s$e)1Rn&QQa%OB=#?=>!z2|0Y!CSdUYOHRJTfTa#7tUp`B7x2c#F|hefq9 zUG+yr_4jmJJ}#=4q#O82QSF~zte+Ou9n)=jt*pMEp7QmwdRjXDjj}p8J=-_S>aR`d zn}U_qDd{G?RaTctuj04M>PsoUQ&!(if1-EG>O<-D_sZ&i>E_4mjVk81v)-o8DmU!~`;UytgHbo%~1s^_Mc-~m0VkEB1!fjz2srI-9c zJ*utgb{^cLdTRPJ9MYrOF5SRGdsL4|rytg%IyAi?5ARXEDVaE;M|GQYEkh<&cTCTA z=)~&V>B?4_SUn=$menR!kL}&iFl=JAExkZipIA-r$u+Dou{tunB-VejdS&{(4W6vl z(qX%4)f3a-fbFMM*Go5d)U@j8WMYSD)eX|0VaI9J_0vrnJ*~QK`ZMe_t@>tqeq*M! zoRxlW@6L@4EfbU8vH8O9>3YZI3tOfa()fH~X1awF@`e1t*M0JZQ`3ua-+ZBSdc7Z> zUZpLMr6)cjUsxwy&yo4Uh3TKHqw(S^2`l=}&fczVKE0bDxthw4`Tozz*rc@N~lt%okeH_2joB zTJnd<8}o&a(x0m-UwAdW2J$EDTdq#eqB&pqFufRyd||cpmn3~}tA>`2`QPDu;nxJI znlD_Ro>xo0aBq4=w9gk7P1oEZU$`)x)tWD~q?dL2E=LV5Yo@b00&mz6( zn(~F;(;qqC&7ftj^tY%vUr6@SpCVnzpP6cxFI<-XT=}V5h9zx{`NBHs1>Te|e4btx z`Mieqqtk6|-m|fCS=#Bpz6a8C>d<^z8m-O6{6+pohaL0dgD()@A$y)QmuM&!jM*#A zB^!!`V$PlBQVqqzG3QEiU_-G;%sJCsx}jJ!<{W7bN)G}YbM`csX(;-~?3w1^hGOxU zJDCR7-6`*M^OlX>G4FKymW$n*_LAxLEg!o>-s$$O5W9We>GrJ{yCv^* z`&Now%{$$`m1CEAr`tCqcDuaO?Hd}q$UEJ>Rbr?6m#ng6x_zt0PWJ#=Wyy5=R*T(~ z_EPEg4U65Fce;J6$4;;RPR+%EUF<70-92{A*+J~2bczA;0{elbJH{xL(y0Wm|!fiVd=C^jJn$0p>E*n}J! zn~=j|6LNTLLXL<{$dR!LIVv_GN5>}QnAn6I8=H{hViR(FY(h?mO~{F{2{|b?At%Qs zu(_#~HdhEK8Ju7FW*MHlk=`EdNuey-uvXC>%EGG*&r^w$tcb1TIyY(j31O~@^=3Ar^kA-BaQDDpQ}o+aeLI5mVk6f=Z8 z95aMG5;KH68Z(4E7BhrA9y5eI5i^8588d`D6_b#sV-xaBY(k!mO~`Yx33)y?Auq%x z?T z3HdQLAv0nV@>6U=evVDZFR=;vH8vr?#U^BCY(jpIO~@ay3HdWNA%Ddt|OGEGeu*Z9ghIe&W=X_ zDD8LzfT|sj0MKH`BLK9w;}HNl*zpJet#&*DKu0?s0icuZ5dhi*j{r~;JOV&x!6N{4 z5j+AwSHU9ybQ3%RKzG3-0L&(M1b`lbM*!$4cm#mi1&;tQhu{$a<`g^vz+8ey0GM0w z2mrkVj{q=_;1K|N3myTWkKhpi`U)Napr7Co0Ol1Ekgm-|Q)6XF0#e&3zl&38tSkCA zE1Ivd%)GLqg&K?eE&XRHTG;uaXc0RUEoz6N#q3bj-ws8K+o5QH9g3E)L(!6UC|b&< zXrMsR(gH<;1d5gsC>ktKw5&kUasoxm3lyy&P_&{z(MkeED+?425hxleP_&9b(W(MP zs|geh6DV3;plA(&qBRAI))MN97HF&-n}F2vx2`W13`Iw#kE#@FHllF+Q$w>``V#s zKRXodZ-=4->`-)|9f}UJL(#!@C_2QZ=um;8!vu;B7brSHpy)_}qN4vXO^r#(*9{pP}F9JqM99wI@=U=5h&^^P}EJJsJlSXYyw3+1d4hJ6wNMBG>1UZ zoB~C22^7sOP}EDHXdZ#0-U3B^1d93!6!jA*npdD`KEc05^9vL$Ak-BVO_hZcklIq| z6W~R=ruuvOC#3rq6bm+$*;iJyXj73Nl5dux#hf3C`rDysaXSkYDw1Ys=jsiua1&VeOC>kSBw6j3bE&@fn3KZ=oP_(;1 z(H;UtdkPfoB~Y}tK+#yCu4qJ4<(>qjc73{IP_cd}x-S3sHm<46zOtfyn~MC9ptBV1 z=loE#za5GWutU*-b|^Z?4n+ssq394h6dh`ZqQmS^bhu5?5duX=3KShBP;|6F(J=x= z#|ji3Cs1^}K+y>TMJEarog`3nvOv)(0!60^6rCnebh<#%83ILT3KX3sP;|CH(K!M| z=L&U26PhZ2B_Ora@<$!_2}P^sf0)i|DzmSw=%S_~Kcws|MH8JLiY~T8(Is{$y3`Iu zm)W7{ayt}VVTYnC?ND@;9g42DDY{0W=vslI>ja9f7bvI*~B{OOK7#Y0VH_LUVq)>Pz&B%Y<{ap#AkC+tx4q#cT$vP03+b|`wr4n@z}q3Ag~ z6g_W;q8Dt6UKA*LNucOufudIgie42cdQG6{b%CNc1d84iD4HZt^p-%;+X6-J2o$|5 zQ1qTa(fa~L9|#mp7ATq`Q1qcd(MJMB9}9Iwk2F<|Pe5wZ)17gPM?=xi`Q9C$G?m#` zR`f+vkss1}mZC46ABv{hq3A0+6n$-nqG@(0`o<1L-`b(*J3AD8Z-=5EY>K7}6#Xbr zG(({1CxN1$1&V$VDEd{P=r@6)nF2+>3l#k!Q1quj(O&{Ze+v}-BT)3OKv8;t-;2_# zF?~ioy#n*yP8$V^ngog}0!7UNMTJmT^jTBol?0@=Li!9x@p&k^KaX~mGW*Jk+E`aCvO`gu9g1ppDC%s7qAqqQ>S~9gZZ<{T1&U@9DC!|l)Kj2n zc7dWf1d8SqD4I*4Xl{X`UIIn)2o&`eDC#3n)K{RWpFq*P0!8x)6wNPCw17a-f&xVg z2^1|X)D=}Lm2QKQqEGUNh*~Q3_w-wv(paQYW?xy+;+10Q!J%k?^Fz@Rb|_lX4n<4Z zp=h8Tik7xR(I7h%En|nG!FDKG)~0AVfuiLFidGOPT2Y{AC4r)q1&W3U6b%(9T1B8} zRe_?_1d4_U6s;~$w1z;@ngT^@2^6g@P_&Lf(QtvHbp?vn6DS%X)D+b}3lv=-)D`VlseGA$)b7Y{Q12g#*2{`6td!YTR&+_FC|3?empVTbU1o=(%k5Bf zg&m5nv_sKVb||{q4n^14q3BvW6kTUibiF{)4FW|s3KZQWP;|3E(JcZ+w+a;9CQx*{ zK+zonMRy7m-6c?Tw?NT70!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IY}#(Zot+(FCM6 zDStNh;!w0``YeC(Xr;`)vZ5y|#kxa7(NoS3MNiwI=ovc{J!^-e=j>4Qyd8>OutU*{ zb|`wu4n;596ulx)^r}G7YXU{D3lzN}Q1qri(IkPQw*-pb7ASg0py*wJqW1)f-WMqP zK%i){K+zO|q7Ma%J`yPUSfJ<=fuc_ZiarzSiXN|2#w8%Nt@E8^p9n>3qNioUT!(YJOe`pynT-`k<+2Rjr^w?om7b|{)*Q}mNS(a!=! zzX%llDp2&BK+#NrqTdCI{tzhoQ=sTCfug?!ivAHO`d6T+p*h}dr>Ie&s7auxB2d&U zP*eyMwG${R1&XRdUD217%6$n)?XZ0RqN$;1wfq^7mgX}1%8EKR7w-)VMV*`IyJq3zp7bu!TplD8kqPYZ$<`yXGB~Ubv zKv8djqCNseeFcj82^7sMP&A)F(fk5M3kVb~C{VPJK+(biMT-a&EhLp}F!; z0#dssePwdd+FXB6f35s=sr{SF>?I z6s;vtw6;LeIs!$*1&Y=cC|XaTXoNt~`T|882o!B7)D;bAuB?`T)b7mpyIvv`bq#L(zU&(f-Y4_LUVK++5r^JQN+`{7`hL z9f}UKL($=OC_2IpMMv79=qNiB9c_oAW9(3LtWD8z0!7CQ6rCVYbfQ4fNdiSD3lyCq zP;{z5(P;ujrwbIFAy9OtK+#zOMP~~Xog+|mu0YXw0!8Nw6kQ-tbfG}eMFK?=g}R~x zn=7v+AhqAqEDj1qbLS61Uff(}Us=)R&Bc%Fg`z8*ABwKDL(x@sD7xAXMc3G&=vq4z zU1x`)>+Mi`?T)9g1GCL(z+ND0;~bMK9Z-=oLE@y=sS|*KCSj z7bto|py*A3qDcZpZwVB=El~81K+(GbMehj|y)RJofk4q@fubn_MIQokHVQ@G zIzJSBXNRKi?NIcC9g3#gq3B0D6wRUezt|N0Dp2&BK+#NrqTdCI{tzho zQ=sTCfug?!ivAHO`d6T+p@?_eDQXlbY7!`_2oyC76cqwR?F5QSfugEFQHwxPdx4@3 zLS50<&6O(>klGIU!`0J5(eC*@{nnz)zOtfPQ9QXxDC+F|P}Ic^MP2Ps)Xfe>-R)2` zn;nXJ*rBMW9g1eRL(v>IMRN)i%_UGYw?I)ZfueZ?ih2ta^${rQD^S!=plDu!qWJ`h z<`*bhK%i(rfue;3iWU|qT122|QGuex1d93#6fG`LG(e~;>Qq#|NN_FK+&24MQaHZtu0WrjzH0HfueNw6Q?ZCPH1&QbnbI0#f@p-|u>0C^{&A@MzPb%)YXskwr0LWGLFw z`JrelI}~kghoWulP_(Tbing;u(e`#I8fAx~9qdrFqfOChfufxRipB^O?JQ8Vi$Kw? z0!6zC6zwihw1+^^o&rUC2^8%uP&8JcXq-UNc!8n`0!8}>6zwZew4XrH{sKh@2oxPC z)D>-BR3;=KwE_8l*IR_5`O>%cEDkEl>?$L(x%oC_35> zMaS5o=vX@x9cPE4%s-5`m&ig}S0cipm2CNUdx7j(EkP zq3HRn=(3{BzOtgLisFN9LebUE4@KA5q3BvW6kTVBqU-HYbb}p=ZnQ(uO?D`{*$zdw z*c9C=P;{F>(d`07cL)^SDNuBmK+)X-MfV64-78RZpFq+50!0r96g?fuKHG<) z7n~o8UbI8eOLi!F*$zdo*rDiEI~2WUhoaZ*Q1pf!ir%y-nj}#4mO#A33lx1KQ1q!l(Psihp9>UyAyD+CK+#lzqOSys zz830=o-Hb?Cm^*G@&_893q_5MX-q51>?qS*Kv6q^qEetJeUth6o%Jbd5h!XeP}D)7s8yh-qd-w7p|0rLqH=NqQtOx% zeHV&e&u?9~wJWo)tf*_d;^xtzsGIXcQFl8O&1Q$99(E||X@{cO?NBs_9g60(L(yDz zD4N@*sFy&|JOV|%1&aCz6!jG->L*Y%uRzg!0!8x+6fGc7w4gxILIOn#3luFPP_(E( z(P9Ec{RN5^7bqGaP_%?V(UJm1O9^#Fo!eF3NI+`;=Fg*bX;*(wf1&(2{ekVu>?`-*#inRgfuhv}iiQak ztu9cshCtDp0!3>H6s;{#w2na0aDk$A1&Y=aC>kM9w7x*m1_DJJ3KVT5P_(f?(Ix^# zn+gobXyJU9wL{yL*;iI{WV_<9-9yn)&JRUL+o9+fI}{yjhoa-`P;|T`=2C)*UAB2aXyK+$OeMW+iCogq+kra;kI0!3#F6rCebbgn?rc>+b}3lv=- zP;{X{(M1A969tMc7AU$zpy*P8qRRw|E*B`eLZ~Y`yj|t01f+IpzW4qSq3GcJ57U+H z%IqsEy0%^M^q!&UI_HO?>+Mium+K7pe91&SUJD0)z!=plikhXslr5h!|8py)AyqQ?b_o)9Q{ zQlRK5fug4cik=ZDdRC|_y1HFuS^`o#p-6D92}M)#qbfYtuFSr&qL>bt9B@Q%??Gc+o9+UI~2WXhoVV#D0<5dMQ_^_y(3Wcu0YXy0!8l&6n!92G+Cf% zia^na0!1GQ6n!jE^oc;xrvgQv2^4)UQ1pdB(U$^6Qw55?5-9pwplF&v(KiA`-wJg_ zFSM%+NI+`m=g*_P7>bUrr14$5GW*Jker#84Fg_H`aDFKI$qq$7+o9+eI~4tDhoax? zP&CsHMZepj=np#-{b^J5mq5|q0!9A_6#Xku)KJE|%M>*V6g3GHRRoICT_Wo5a#K_Y z6txp5Dg}zF0!1wXMePNOItUcC3KVq|DC#6o)Fx0=6DaB|)D`{EuCi|eQX7}PwRJH) z6kUSc$bdF)Ws z+oq_GKv7?TqJ9EJ^9mHrCr~uMK+ysMMGFcPEhJF1ut3ow0!51o6fGuD)L)=zae<-% z0!2#*6fG%Gw3I;6K!KvA1&RgkeZ7fi(Kvyk@d8B? z1d8?%DB4$`Xg`6X{RN5+5GXoOpy(ihqJssB4iP9iRG{cEfuh5Ox}t5$%9;sCZNL0^ zv~5Gt_}*z8QI^?PR&-2R>~e4@I@bB2=r}tR9dC!C6YNlQq8*A(vP03yb|^Z<4n?Qh zq3AT5qSFP6&JZX%Q=sT9fugeoip~)zI#;0RJb|L~1&S^ZD7sLf=puoli2_9z3lv=< zP;{w4(PaWfmkShKAy9OsK+#nKMOO=TMMssDQxlL{kNhE`qeIaT`LnUtlx6mn72Qx4 zw;mdbZghSqy2%bjH`}4;7CRK(YKNlR>`-*O9g6O-L(!dfD7wq0=x%|cdjyK^6)3t- zpy+;qq6Y+u9uz2gNTBFpfuctQiXIgxdQ70`ae<;I1d5&%D0)hu=xKqXX9S9#6)1X6 zpy+vlq8Eg^qU*}aqy(gPQ@;29^`Yp){PCg}%QE}Qie4>?Uk(pNuQ@*yy>5r1H|$XK zrX7kV*`eqyI~2WbhoX1vQ1q@Hir%v+dS9UE1A(H+0!32WXHRmF*Ic+R8l>oS#C`gIQ7cYMFgyMYC6n zBaR70b2vW~&1r|Cx$IChw;hUl*`a72I~4V{Ls1_)6!o=3Q9qlac?F8*6DXQrplAVs zq6Gzt77{30SfFSTfucnPiWUMu~VxIobWfubb@ik1{8T1ud3pg_^m0!4!aik1;5 z8Z1z>tWa0fqguHp0jYh~FTv?qt-q(=BY!2)a@8{X%8FL17SA3RidJ@hC>mmiqM>#u zTEz}UtJTU(GJ&GY1&Xc^D7sRh=qiDts|AX# z5h%J=py)cGuISimW&Z@Ewpjjf^>Lx-xBN!Z_0=-_%8G8T78jfvif(a!D7w`SMYq|Z z=yp34-C>8KJMB<(mmP}kwnNc9b||{nrszI_qWcAk9uO#cP@w1`fue^6iXIUtdQ_n3 zF@d7T1&W>!D0)($=qZ7srv-|h5h!|Apy)Y)qUQyQUJxjHQK0B0fufg%x}qDal}8eg z+SqD>b5kgql)tR#m1>!NWkqjPi;qqZMQ=Jk6iu>2(OY&XdfN^~@7ST}T{{%LXNRKq z?NIcA9f~H~6ipE*`cR`?Tt9f}%S;{Ene)M!)GBv4cl zC~6icDg=t!2^5tAMOA^K7J;Jn0!1AJidqGVItmnZ5-4gDD5?n*brvY&kjZN+Y~JzP_&>x(Lw@63kwu2B2cubK+$3XMg0Ye z78fWQAW*b~K+%!{MN0`34HPI^TA*l|vASaD(~I@$T5 z=oC8?ooa`o)9g@mx*dwnutU+Ab|^Z_4n=3%q39f&qH_g`&J!p)U!dp$fuaiqiY^i; znkZ0ou|Ux!0!5b!6kR4zbh$v$6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z2XMK=m{ zMJKdWMkOG%Vfl-PP7Fow=l{`eYALg?tmw9u;;2hP(e2I;MR(Yt=uSHn-DQWOyX{bP zj~$BcwL{T;b||{v4n+^x6g?PeyK(fmfzuPtTvl@2{cDG!hW7EEdnjtOLs63*iYj&}YPKmV1d7@T6qN!+Re_=w zfui;TMI8i+S_O(a3KVq`C~6ZZstFWz7AWc>P}EhRsGC4hcY&hW1d4hH6!jD+nq8o1 z4xz4SW=myY0#Z9Kf1vUAQ1oy6H0EqyW?xy+Jnf53t`0@Loga$&*rBMe9g6zdp=e$^ z6wPOcqWSGmw16Fo7PLdrLN-MU3luFPP_(E((P9Ec{RN5^7bqGaP_%?V(UJm1O9>PW z6ewC+plFal(J}%>g9VC~6)0LxplEr4q7?*+Rum{&NuX$Dp{{7|_LTz@kXrlv{fm0F zufL~%cOFC9m)TcVv|9V(qH9CZFz1J&)$LHUh8>F5v_sKab|_lg4n^zOp=h`riq^G5 z(RwyTBLs@p7bx05plCyZqKyQKHWnz_M4)I>fuhX>iZ&N0+Crdcq(IS@0!3R16m2a~ zw2eT~wgN@l2^4KFP&7)QXa|9!9fi80RoYh`OF(Kr=KsW24MhW6(-_^p%)YXsUD_9) zTpx;db$%$?%??Go+o5O=I~46{hoZggP_(xlipJWZXq+92#@iH45GdM5plDx#qWuJl z_7^BRK%nSAfue&1iVhYiIz*u8P=TVu1d0w9C^|x*=tzO0qXdeM7AQJKpy*hEqT>XL zju$98L8vPl)4tN~hNNi6{27p)Ls6gnH6SOpFSD<#=+ySb0yl-C)0`iQPPaqR8FnZ- z(+)*v*`ercI~1K`hoW=sP;{Ohiq5wwxL0QqH_GR{! z6}{WOxbwD9^q%uW(ff8N`oIoFlkHG6#STRu+M(zpI~09vhoVpHQ1q!y(Psihp9>Uy zAyD+CK+#lzqOSysz7{B&CQ$T^K+(4XMc)Y&eJ@b-gFw-AfubJ;ie?BD{UlKIvp~@= z0!6~HQS-6utQNhI~0{RMOA^K7J;Jn0!1AJidqGVItmnZ5-4gD zD5?n*brvYhI}an@O$O zq0GLrqBS}c$J`r=)^vU-TFVYaYulk{9Xk{aw?omob|_lU4n-sEP_(`siZ-w*+EAcq zBY~og1&THiDB4t@XfuJL%>|0K5GWccP_(5$(N+RQTMHCzBT%%hK+$#rMcWG$jS?u@ zL7-?yfuhj@MLP);jS=dKhIOdikbu-i=g-Ej9*S=5m&VQ=%IqsE+Py>Z;{Bm$59f!X zJ?&7mmmP}swnNcaI~0wxL(zCU6iu*0(LQ!4+SjINKY^nC1&R(3C^}G}=pccjg9VBX z5hyxTpy)7xqQeD>ju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlZCpX zT{~2!Cm^*8^H*5!7K+|TzgL{nq0GLrqBA-aogWHCXF5L=on?ojv+YoHjvb25wL{T) zb|^aE4n-H(q3A+86kTLfG*O`FVu7Md1d1*dD7s9b=yHLgD+G$J6ezk%py+CWqH6?- zt`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCc=ysv5=(G-%K?z9hx%>w8>7nSb z{C3eD9m?!0E4rscvDqV`=w9cCqWkPnbiW;n93l#k! zQ1quzSM*+o$`c7lZO{DS>i0uY-(G3_)uGJ3vZ998;`+v(Ls7FG ziV8avwX;J}X@{b!9g14)P}JV0sDnUJt3Xjlfuc?VMQs8_HG!he0!3W}inJX^Kv55YqMiapvkMf>Ay71@K+#+RMRN-j^%5wWN1&*;P*?O%hf4Lyq-d`E@uGjd zU6d8|X)Uv_tZ2U0Vxgx)(frO2MGM%WXhAy^Eo6tHh3!zZh#iU+wL{Tjb|~s^hoZ%8 ziUtT2Eg?{}q(IS90!0G_ik22A8YED(j6l&~fudyvik1^7T3(=N1%aX!1&US@C|X&d zXox`3P=TUV1d3J_C|XURXqZq})UUO&UIJ2^FMl?6-q!ki`hVoHdTW_|WkqYZ7JEG# ziq>&{C>m~uqIK<1w4NP`M%bZfeLECwV27d&?NGFl9f~%#DcVG!Xj6fr%>;@z7bx07 zplGB((Ut;5TL~0xEl{+LK+(1WMcWA!Z7)zXN}y;5fubD+ibe|*?Ich%MxbbCfudam zigp$1iq>qcoSlHw7RetXS}PPipT9PCx7ITI%8K@CE$)6k6z%Q&P&C#KMdR#HG~NzH z6YNm5j~$BkwL{T0!1eX6rCtgbdo^P$pS^E2o#+vP;{D5SF}fK<^2Stwp+g6 z^`4<3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WE zS)k|^fudUlif$7qx?P~?4uPUO1&Zzx>Wa>6t@M5=DcU#R@A|Azv{L@m?A@(p_LUXg z-&zcPB@{j2{803u9f}^ZL(#)_D0;*WMUUE{=rKDKJ#L4hC+tx4q)pLN0!2>?6g?wQ z^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_IK+$UgMXw7Ky&+Kara;jofugqriry9| zdPkt>U4f$agu0@8TPr&yAho~qhluVAMJMNb%)Z}RW?xy+hpokNuZ5zIoF9rlwnNb; zb}0JP4n?2Yq3Clv6n$ZbqA%@GG}R78U)dCWEl@N~py(TcqHhI?z7r_=UZCg)fuiXG zML!A@%@8R1NucOwfudgoihdO+`c0r{ra;l}0!4oa6#Xes^p`-<-vUMd2z5o1TPrsu zAho~qok6CAqJCY|__wvpzOtf9$KvJm@$4?E3}`5tJO1C_(=Y5$)Xok?r5%c@b|`AG zLs5G>6m_seQL7z_I@%O<5-4gDD5?n*brvY{H+8JPk2WkPAG*qBy6@j8v z1&US^C>kbEw7Nji8UjUY3Ux*EcdQIfKx)g>5}XA>(evHXSgT{1ePu=Kb}Y7dClsyc z{7^K)4n^zRp=bj;6m4jSqK)iOw6PtEHnBs|rgkXW%%*5_fub!0ibe_)Z7EQ+l|a$f z0!7;h6m2U|w4FfF_5wwt1d4VLDB4k=XtY4lP69<^1d4VRDB4A!Xjg%v-2{qu7bx08 zs4H5hW985Uq;^KW-}UfNG$X%}v}eaM`^t*Obu2D@FBFY;ekht?hoXJ#P_(ZdiuSWZ z(f)QQI=~J^2il?NAUhNtY*TcIK+&NBMTZF#9WGFGgh0`e0!2p&6df&4bc{gJu>wWM z2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoi0#xhCtDoLS50`9V<^IAhnM9pP#Xz z=<9qZ?6W$S*;iI{UdQ5#4?@xT&JRTw*rDh`I}}}HhoXsgD7x4VMVHv2=u$frU1o=( z%WaCT5GcA*py(=rqN@dpt`R7@R-ouQfuidLif#}nx>2C$CV`@x1&VGFD7sak=r)0( z+Xag55GcA+py)1vqPqo(?hz=uSEwsGr(>o4D!zc77; J|+M(z%I}|-`hoUF!Q1ql7ik`AV(bIM)dd8;cS%ISG1d5&)D0)Gl z=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQfuczQMQ;fdy)97mjzH170!8l$6umD{ z^npOpWTCF;fsU2+6Oh`oJrbM;L(#GMGayqsmf2TU^hw8J?8l+#Q|E`G&+Jh2xgCnW zutU+8b|{)^hoZ0SQ1rDOil*72=o_1&Zv~3J6Day#py&sIqUi!fKMEAh5GeXdpy+3T zqF)4xeibPCO`vF|K+*34MSlns{V7oNmq5|q0!9A_6#Xku)X*v3F{h|es4M!YW98fg zq_#@Fd*jEU=z%_IG<7PoudJwDr{dmELs9AcP*k-;QHvdl+S{S1gB^-m?NHRw4n>{p zP}F9JqMA)nXMv(F0!3W~in<9Dbr&d_O`xcUKv7SDqS*zC<`5{FQ=n)rfugwuih2nY z%_C6MTcD_qKv7?TqJ9EJ^9mHrCr~uMP*>F4sWLeMsqLHJpe{Pq-_zeIf2+_1I+fX1 zRdVTYn6?NGFo9f}6pp=fEFqCo;h%Lo(= z7ARU)plCUPqU8mORuCv!QJ`ogfufZKiiQXj4HYO_MWAR^fuhv}iiQaktu9cshCtDp z0!3>H6s;{#w2n|$v{0u?-!GD)$MdJo77j&gVIc!8o51d2`+C^|`? z=wyMSQv`}m6(~AQpy+ggqB8`F&J-v*OQ7g%fueJSx}x!&Dz_vcwLbYju?eB5HIq8G zQ<;5bMHhA|Ui~H%UF7^wG|>)47u%ue5<3)KYKNlB>`-*M9g427L(!FXD7wm~=xTwY zYXpj}6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$Dsx=oiXQD$bpJjSJ?8vS z^tc_0p0GpFlXfV2$__QHNK+z0=qMrnceikVDMWEincQQ%8FXripyt&qV~=YMIG!=)M|&Kj&>;OWQU?QI~3LIP}JEDMP2Mr)YYb_ zn?O-_fuh+2ih2kX^%N+YU7%c#mq5`x0!6(Aiuwo?^%W@UCr~u6 zK+${xMe_?3Eg(>|pg_?=LS0eWR(U1?sg24XXsou?-_zeW-(z;+wle$5iu$(|Q-2Oc zi#tCQ4X{Je5_TwB(hfyS*`a8l9g3E=L(w2R6fI+iqQN#r%L)`NCs4G!K+y^UMJoyv ztt3#ivOv)gfuf-TMXLxDttwEonn2Mofuhv~iq;S)T2r8CErFu71&Y=YC>kzMw5~wW zdO}^%qHUGdUy`CX^CvwP3q|wHdWWs8%)YXsjoOOEehWn#J3ka{Vuzwl?NGFt9f~%$ zL(vv?C>m*pqAl%Ew3Qu-wzetSMxbb0fuijMinbRh8YNJ)gFw-a0!5<*igpqx8Y57& zvp~@<0!6zD6zwKZw7Wpj9s)&s3KZ=nP_(x|(O7|^aRNo-g}R~*+A13+AhrJaE=3!L zqARna32kNel@;yZR*e5W6dmCFP;{UjiVm_v(ZO~oI>Zh|huWd&Fgp|-Zik{H>`-*1 zP0>*TMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD3lyCqP;{z5(P;ujrwbIFAy9Ot zK+#zOMP~~Xog+|mu0YXw0!8Nwbw&HORnAX9YJ24W#P$nCE9I|8yP&PizOtf=+lu@D z3`LhXKNMYRhoZ~uP;|K+imtFj(Uo>6y2=hkSKFcJ8aotSYg2TcK+*LAMK=f(-6&9W zlR(kU0!6n76x}LNbellY?E*!22o&8ZP;{3-(cJo}eQSrJ@9a?Yy&Z~v zutU*wI~4tBQ#3=M=qG`qp9PA35h(gqpy)S&qL~6kzY7%oAyD+EK+#_UMSlwv{UcEH zuRu|HG^vZyE2+7WqDFzDCV`@gKvAWaQ-tL&P9)XvI}8~bG_nw0;0 ztJccwD=TWP6(==?qK?iFMV;(W)MkgGnjMNd+o7n79g4czp{Sc3in`mOXf~Uo9s)%@ z1&U@DD4Ii{XikBmxde*l7AWc^P&AJ~QE!2wJ_1F31&aC!6wND8G@n4x`~pP_2oxhI~Fn?E(XSgp*yvZ5tw#p}(XXi4XX zqNVImG|&!3OWUDnkR6Jau|v^dI}|Nzhoa@|P_(>F(Fy`ZD+&~?Bv7=nK+zC^qM-ss zs|XaWDp0hVK+!OPqSXb8)(|LKQ=n)qfugkqiq;V*8ZJ<@u0YXx0!1SPiq;n>+CZo) zTD(^IH36v|kUx($AQY{dKO4JYt<1i%qD^Z>k1`Z(=KN5!xgCnOutU*EI}~kchoY_Q zP_(rjing&s(YAId+RmnEdx4@+0!2Fr6zwQbG+Ll&CxN0d0!2Fu6zw8Vw5veTZURNS z3l!}kP_(B&(Ov>YdkYke6(|}fP&8hkXo5h|J_1Gi3Ux&r*D5O{Ahmt+J!UrvMb~#p zW4~INePu-l)rzfKLeas_4@HOAq3BRM6dh)VqQmV_bc7v>j*c2Tr zP;{I?(eVOBCkPasC{T2gK+(wpMW+Z9ohndtnn2O%0!3#C6rCwhbe2HT*#br92o#+w zP;{O^(fI;J7YGzxC{T2fP*-$7t#V`nQahw~f^%Rf+9-eUXkx9*zOtgrYQ>cuLeb^U z4@Fnlq3B9G6kTP9qO0vtbd4Q~uC+tab#^Ga-VQ}K*c9C;P;`?((ai!yw+Iy7Do}Kr zK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2oj|db!Dp2&8 zP*-$Gt@2y~QX7#!jelty!wyA1*`erX zo1$L?ihdO+`c0r{ra;l}0!4oa6#Xes^p`-<-vUMd2o(J*P}I;l-fgF-QJ|6m_;kQ5QQDb+toLH#-z{w?olvb|~s$hoYW#D4N}-Xbyp*IR%R55-6Hmps1HX z(L4f0y#d;&%D3luFNP_&>x(Lw@63kwu2B2cubK+$3XMg0Ye z78mM@I(DvHn1Ix-EfSngo$K%E_syT09niVVzOtf$or?#%g`%aMABqOqp=cR96b-gR z(Xw_ZTFwqd%iE!71v?b2XosSeY>HMEC>kPAG*tM%h@o zMM0&74uTR=Ad*H3O*94wMQIX1u%ckE*b6H5-h1!8cm3IW?+yF&y=OkxW`n=~^PKm* z&wJiI2fp*Uc4qdTnQO{DTY^R70a#Q7z@lOR7L@?7s1$%j698B=5r9Qy04&-KfJKu4 zSX2(cq6z>ORRXZ63V=n`04$mez@i!e7S#f^v&gb&HW`cN0I;YD zfJJiwSTqlSMe_kzv;crbdjqg&9{?6D1Ypr302VC799=1qGJG9bSwaijssxP z@c=A30f0p(0L02ZwWVA06{EII{%MW+I==rjNpoesdFGXPk0CIE}h0$|bE04zEO zfJGYsSadD`i_QZ?79E%yTWErG@Z4R;gJjXqaSP|?#+_fzqKk5a)T|$;c zmy%`CWn@`&IawB6L6${Vl4a3VWLb1ISr%PG#-eKhSacl#i>?P?(G37Bx)FdyHvzEd zW&jr50>GkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO-2=d)djVK<9{`K)2Vl_y04#bC zfJF}hB8x7_jooO1bm-O2#JNxw9p;pJI5+P6auz+F8@#lYEP8_JWzmylS@aZH7ClXt zMbD6B(X(V(^c-0hJx`WJFOX%?i)1W%34lc}1F+~702aLpz@paxSoAsoi{1cW(SHC~ z^dk02aLuz@iTTSo9$Pi#`Hi(Z>KR`UHSQp8~MxGeBg~ zqq(t7CP;^!x|=wU$)ZEtw;DgsjXS@bMPKIz-STD8H%u>!z9q||@5r*~d$KJ0fh>!D zB+H_o$g=2XvMlr67X1dmqTc~n^alWo{sdsrUjQun8-PXs0IcsT2s54m>CCRcVk1UJ2kY!OqU`}#)CYh?eF0ds z0|1M51Yprl04(YUz@q*DEE)j7qJaP`8U(`4=(!&>*&*>G8Ob=YC+7IEle;bM!y8d>zQ`$?<|JI0+~US}^O*f#rue!iFNZ&%%3vdVsr zHZ!@ey-Sivo?<7$cF9}pqN+pkH9MSjPIk}pyspVcld?zhGW!5!e)4O(%IcjQVqd=P zn_S(?^ZF(4vmZ+ulnl1_yrIcSeLZhva{Z2;HzxU7KhGPN+-jib6(?sGc;3Y16+=9) zJo)V~&#O)j8|is<$pc1v-n8TcV?1wWGQO+l?Uk%3^t?IAQ;Ixqe)5eH&s&(>dZOno zO*ZZ3dCQYmm3!W*c^i}0GlRK~Vyw{V5 z9`1Q>B_BJ|^WIBtag67El&n3@^FB+Sb%N)8m3;Rk&-*U9-6@{;Q*xivJa1F-hBG|x z&%9sHvi0xhjosirBAd7NJlg_(-V+;b6Zm;K7uh!O^Xf0Ljo{~^ccJohI#NBVj0Zz_)Q^V}cB z8|UYpd%tZEKhOPHs)>G{`@2HrexCcoFx7sZ`^z46exCc&4AcBP_uKk2{XF;M=zIBj z?$@p7_<8Q-UKPT`yUJa-KK)A!mWa&5=DINIg9Y;7G{e@NR-aoec&m~Z=MUVZGDHqnz_*P-Fq!yT(PR%QRXCT*YchfH$pNXv&hmSw>oGRv{MEZ^i< zbIA5T(S|qKKU-;Dw`bk_hP8KWM|)*=zSy#Vdt<{x=50CDg%Jv8xfYFVZ|>S?qiret zQF`VR`@WbzT45*K;r*Qz2D>muVVwOEx<6LojBPCJqL679KK`x>huU$&9~Xu0wpBg1 zK4SK-hhLqQyY|5spFg07KRIYO;>@W-d-ye3xhLO#?q92V__aa1cOSm1r?-_`mO{qg z@W{! zOh49sm$q%~>1Z_HV7#wQ)x!>;iEtqByzFqm)=nGEFo1CIjb!UT9L**BsEr7p5gz| zehbgHhmC9h`~d?7E^8b(w|VKn=4G=7E^BC>-PEvj*^=c=vzIr`88~~{>ZQwZ1uL7pf%BIvY8u$MuxZu60SlMRZd^F9d4A)vrh&_v z7B@9FHVi z`y1@Pc*)|X{!NXu7W6L|G+;=7_w)dJy46zy7c8E=aK)Uafr}bv&tI_k|MzAzuWn9X z6Z7T|EL=8c#e&64ik2*E>YrK{tClYdS4p%+s+TR<+tzvWz}lsa%l0W*i_*-o;CIZbmLS1erKuzdB>rse_j z&1KI-n6qHN5_r3;Li*0n_?4YpEd7lquIIgFkQ+)G8s3w-;L zPbYqCh#v%<{-;OaXT|3EK{D1YKk#Go@}r@|fFQ`48Fb9@-M~N_=oEC?T7x#btX}T9 zv^+NG6y_OTMy8((+Pabx^m4^`7~Px(+hln`r-4Dw9fD5LtfT2BY5JDR{G;aw1-;z- z!})Fdf0})-9qgrOQLCDt*5qD#$$>%AEr}m=7!Yh%5M=8$a-v1pPKyx60pYV5wivw) zXQ)LPvDNuO7YF+2`GKkD`#T(4H6VI^_`jZaOOz4YPtV7)^ZzwQIO739pYR1^D+dHg zHx#W4*Mj`m7PeHz{H)Z9$q%E}dwvkc{FbfI+ilJMZdFWjo3U4rKPc$9m1VZ-Hg5XV zR@`iEZYy?oi#|BW>k&>Arh*_Znnjof1$jMF&*ix--7DG<`P&4Y+%tpzcQ4@&2|C2? zK4gFy`LH)2KR=_R9hysPs~bvcY8uKarxcc#6*m;tOsKCYsjTyOqN1d>ws1m8LtRx> zLwQx@1h1xKLPJ4e(ZtjkMRm3HHhoc5MRj>eosC&vS*GzyizYVAY8kPxrnsT9s?J8P zEvcz1DNa4JTeZ!!zOuHyy1L3e(NJABt)#r6w5q0}ur7K7EtSfA& ztgjefQsb7RswNtH$jI~;uB>XPtsh@oR8!_gE3K-pEDlE-F>+#9N408ZO-XHam9;RM z(@-0Sb>Z4xQd3x))^gTcMeT%!@%5#pHvihP86~Mn{e>Y1GygwubVu%1NoUHnps@tf8YBU%Ic=4qLaF!uyVRKUCS)O%~o4g z8@8a>tWGsxSor!Zg~lr_u>GTMjL8N>gwFS%uAORl}`$rJ7j3I=L`#9F?{hspm1jjktwWgHBwI& z*y>Bot*or3w6LM1sHmY}e3^FhqE@?NcxWjuE1b|!RbN+KU)M0Ds=UtjpVTba8{9#~ z9e&)QD{b#AE}2qhXZG>+wb5F(eIxyN6zxh*W?RW_=XUEOZStCFwo5luO)04uC~KT`tdYeq*^l}b&wpKT4CeUR*u_1EiWDUp7ykD z2wNo$CDV#ZN{Z8(tQBHM*t$YHLQE=|-cVXt=Js;7p~i4mJl3?T`WhRseXO*+tf=Lv zA6n`TW~o(IFgUe?+pZq%fVTh5S+Qu*>eRf$-Jztato3fgE8AhXqN>Ji4tJc4W-&P2 zK^87qJTKo4S|JA?WR<)d_++jcUoQ}ISCFLdIvDvMxlGYwYTiPwNZOpRL zXr)9g7;djpwPJa3*prNp+sJ^DKNC&i3>n7S+ zZ)%|}c3oLTiET5lqHtP6k)2^(Ge@SjeNo!NR@;`Vttm3Q3XAH>rbK6=;b|v8c2zrN zPpAw}*P$RoY!o+8*y@mo>m+E+Y#G5`bbL*ro#-W& zdqvx3={uIKG7iG!Rkhl+N2XrTHcqrA$1_k8YS6r3-r}Y?`PNlimU=m7c~z;+&eUl+ zaJL*7ii)ZlCfWfjH393UqN+G*y5JhT4gC#S)Ea2RRORX)jq(Vh1o?%J52Veg$^yjHW9IeOj?NeevBG zc1}n&ym)Z2PLwqzmBr?8+EF>Rfs4XRB00m-l$Dp4OeieZUS}uzV%zOo&UB&VsgqLL zCM_7*N^^NJ(dLwPomI>-*p}Q(fHHRk-0awsejQ;)gK#en*F|bKC>YjiM(i^zOxh{E zl_mf6gw`TSd2v;EEKQw1v_YfwZ^s#Jw}Jwlr|i6)TJ`MUgBpq_*EJMRj85IH&-266 z#@C^$!VX6DHQ^a4JRFwV3aOo#b|6O7^1|uvs&TVZZM3RtN{UMC0Fc^vEr$cw)buru z*qg0!wtm|6Z@G!zvi)hrgu;r7!c;5V`mxI^R*UVP;i_ucg$oKoJ0?`t=NF9{mGADC z3@FHVcT5J296U6?@3N+aO^wY>JLLCYG<)fav9p&fTi&#)|Dqv73@o3&V$m$Ca~CdY zT;AVqw~VzNevSh+=G>(#hxKn>+J8>La3hV&X3rmM_g_|y?7wKhBD;gL)12m|JI!61 z-+x|y|Ej_H{jFm^cD6O3|J+4Q&CQMTn))wnT0C$0{IP=!MLSe~XNsk{D;CdQzF^7X z{>^sl!)mj!Id;HLmG>fAGoW5GV1_D*A3BfhO#XvU$SIrffts+|7uICb8@Ro z-3pu2_^N6Dnxd%O4(@i^bjPD`-9!h_26vuzTdQEuV6{7SWVIEZnoY}Ea+hcgT2;{$ zb_xs!Y;#7yj#O#8OSoNIx?-DMVe44e`aCey=G4^SZXPu)TNcgJdS?HnG0{=j_FUJh z=(@AOdYIuPt^1|!B+_z$WxY}DZ?1P8u67#`a^2q$*#&Yq5cLW}G$=JzG{nI&?Mg4a zKDBO)uDWdJjpk+xm9|#WCU6&yc1Q{(2uE${-=#XH!!?(vOUA24hv<@u>a>1Vk?Z-V zpAcNT)4Pcir`pYhqDgjijFza?PJ-<2q9e7wf$4qV|4nbJw5+tMbyu*(p5nry@CIO= z-7rkeKXs+>@4dl###nDpdM0h97S>xo+ODh8`_1lJh*cMv zGr{^G(S=FsiBMN}5n5I04hG=~xZr>Ltacphlu4kLzF6xnmUA#AIt{6_A*-@SuyXzRehFzj+sKBo4Q|(Jz1JyNE6U(f#XPctZ&SiG^%7V#TMMaHbCsJeeQ0n|xT2#P*@oOjDh&!tvqVu+$T2 zE3&4f?!R6Rhetws$*v_)2Pa_T& zC3YSCT6e&05#EjRU$1kqrq#{7R@c|5>vj6AQHP4vt8LYKmq&tdMcc(xw4$xsmbRkZ znbY-M8fvGO)!8#?r(ybc1ueG>3ha>YHP5%pt5pBl_2$ACurqr&;CgQkM4hbgskA-S zF1TCPkh_%|-fwZ2GIo!lVM1Y9bc4@?PL0OOv5rK2dCOIc+mE>LNx#lb-R2q0Z64R} zV?{ADcj4ldEe`wP6Q_84hlf|!Sl0n#b)7jH>Gt-*@sVZG&1RlqSxc>tX5HC_((=OEmg#u5zS=qN z?iX+$eY4(GYAY3$7PV}l0(U!`SJFL^=rkN|^5|Z?8%)2Y9d`dVJ2bUilopr#50|BG zQ%^66`n~i4TOVGW#`Ipe{tMgT?oWpU(Oq}l4bk~3{ibu+w11y{quv_JnYuX_&a&n1 zb%EVWOW&zlZUDK3jdq7t$G236-pw(!8qwr^0pQ6CsUS;0tO)f1fw`;!idj&05J+-w( zdNZfhdO%)ev|FOO7+Dfs{fA|6bP{gWBpQ&qa!ReRv_qKdNirfY5s98UH-~F0{Z?ow z!hbupN5|vTT{7kyzD2`c4|JQgran5Bxg#%J$7$Q9t?#y~s}%M{Cd_Yao*!*RyH~?O zs%%P#>=NPMqOoXpIJC2sIt_Y5hMw1mRueLXT?w1>#dZypc5%d$skew=b$8oKZAVGJ{nWbm!qrkZQ(L*I zc7=PJovZ2!Yux3f?Gbh<^FQr%X?JAR;)3XQs+(=pA7gp#HovZh!V3!S^oOsXb|{v< z(dAR>uB7d|T&n1R$QyVC(aqFwHtybKI1pWW^UCh<+xpCs+Ue5wlc*&&i*TP!t&gJe z!iws&6Lh49dn?Y(x8*&lmd-=L(A1&L?Ev9?-QCHkX|0YQh1GVAKh3(9i9GO5$%kYH(Xz~F2lLD?jp3z!rsp0!i&bz zNvo}|wRfo0N&eS8N_Ts5vo|5^zGCWL%AnMO+WX&nOUpIL^=DGuEMC!_zQgm$pYPeDs!0QC?+l!r76-?wA%L-Ll96O`Cl?@H_ zl9_SZp?G4=B->cgURP!tzU4OD)I#fsbJW~yN_YRqofD(=({jVp-AYW2+Nx(Zp~iKv zH(R}}I+@O=(0tctVJ0-KsIbV^bZJ9)PWRl)^N|F)G0rUQh3S2kNSDoCx2U4H)eR-< zFhzT^yMO4`V03_>5#gR+`#-&Jsg+4fQ&&V$rz70J?lvPc3(qi>g)JXCaGP_p_SvZ; z^}e86#hg1@<`HeMsZ}+Tbh(*2_ZQfeq^$==wWAGhYqahKmD*dz%NFIAESl9cXO6wyR>!9!!@Kx=>T!qv`JTS}{98Nw_m4g7leq`BZ?{GGAyLQO z!+jXEuzlCHS?hwsGmnTJnQ?;e6^^ne8r^3rJ>S0T;RPf6R}8RzL8X_K8?VTYwMlf$ z?CdA~F0rnDH-AgNyWhj_nX!#;AM5_tBOPUW-~W?7LM-*^)`-U3$N$nEG4~0;v`5T7 z{b%25Nqc14PhfbS`{Zo&X!+2q%Q4SBww?Bfxu45Od&E5VeVLX=%xnF*2kYRXs#?o$5)d7pUH(dWY(Ls*k8X zrTT)ZePJb>|J$k`s@fM)LjJAl&#Hf@x{o-!cDi3gb=AI564p+t?w2nd-&%D$)tyue zR7a?eRV`92Q>{|1SKVE;QFWf`BGqQq)vAZ69Uz~PRL@ntNc9TU>r`)1y-W20 z)yGtyReeSEE!7WIzfk>Nb(5+cP{Q?;WxH*-9#uQ5c30g-bqCc!sv}f)Q7us|SFKf@ zq1vcAUv-Jda~+SsvA`=Q@vL87S+2|A5wi%^##?}Ro_+pMD=UcpH%-) z&9K9mTR+*V9aOuh_EgS?MQ zR4-D!QuPMa+g0yVeN^=s)t6P@RQ*8pbJg!ue^vckHL%0CTTks&JE?A|+Do;s>Oj@u zs$*4)RVS&|s7_biOLd;=V$~I@2db`BJw|oC>Y1wNt6r*ljq1&+cd0(8`h@E9s;{ZO zqx!MxSE@g%{;ulV2i@KJNvP(i=BaL_+FP~1>TuOvRVS)WR-K_bTXmu83e|&Ek5oNL z^(@s3Rj*RLS@j;(M^&FweO>i^)h|?kRQ*#muoISB-u9|pRP$ALP#vtgvud$wh3XX5 z2G#kh`>O7*x>of#)zehZQ@u>}deu8rA5?ux^<~w!RXjz9 z-1M_mH|!YYD^x$|7v*nN``U$w8-JMU;({n2pnCI=C_kY3`>-g-?ZU-PH*RE9D^!md z9pzJ0pB@wCH&i?B8s)83rxixIN%g#g`QYenj=}c~NdVKdQxhM|HC5F$<%7hU)W+qx`mN-o8=ZR&{1`lozO8 zxFX8eseZO!lz&zouz!?yR$YEzln+(C^WZ2yrs^FU8mrH$^#Db+=ohJXQ6i+oF7~>Z^94@7B+Usy*(G@(!xA?v3&i)ywaX@-3?0 zJQ(FaREItigz8?`D4|duS9t# z)j6+4d0*8l--z;Us^7gC<-b&izZ2ym)dSy)^3kdfeh}s7R1+UZIjLItX_R+YJ@xY_ zU!eM*FQfdaYW_D-?yoxcyC^rSUj0Lq?@;~0zToY)&p)aoe~og9>cPK7`B>G5t%K#p ze?hg)-%;+OT5bJ(_xv8Jr)Na@BGtDtqx`w*Hr7FN;}2AwpB?2Ds@K{N0=VbzQvJy~ zaxVMrqdMAtBEaPds%z}G0$e^`^-=rL0GD40^DOI%bEcmZ@H7zvO!+I-@5TRA_WDQD1+LosJ1BQn?Izw^xvy$}@sY}7R13u`Rd-jN zuew6@Fx3-PH>h5rdaLR~s?WP>%bRI8mRud?sUh;sRa+I|cs5E{ld9cR^HqDR z4p1GeI!ZOXzhSReuRL9KFV#7!i&dAY9;te)>dC67t8P@iSoJQ|`&1uQeNy!WRXe0R;_wwC<9z3_ia{Bzr z_ib4(*6m8o?+6=a8aIorheYGKVfWyDAWdtYuF4ZHu{bMD`Ds*Ly8OyAqh7!Ss? zOR`iO+;g4x@Kf`4*{x^yxZVDxw{Lmc@^-T4*d9;VusOffO86+Y`Hd!6b+79luClMV zyvD|J+qa7iceHwRrm^1S|^Z>rj+{N+t|PfmWfbujvc@jv+cjQho3*|X~5P3x|IcvE7s)usN3 zhc}IBtomuw!7feu;k^T0p7g{0tE#^9w;cCF#tucl{JrwwO<%3aon-&Nm%E$&e}9KE z`@g!wMEid)n{J~`v;Lo7|Ndv(whwQ*yWpY)Z)X1aa^KQ>KHGGn%_SKPc^&e`xnCct z8@u?h>mOUcUB5otFPnbnf-z^>IXT+anf?y#?6|S8v**3->`QxO_*wgzlo@_vxw(*$ z5jfS8esh`gJO_(PJOky@%MK&UH2%oM``Lb+x@9o_U}RW=?AFe!D4t zzw;-)$n5ju*O)6A25qAFR@U;&_|4YPApVj$krn^NhU4)gZ1#!xS{u%eA7JCRiBGdR zw2fbB=eKt8C+!8dh+kpX8tvo#d)iJHf8K6~bcmm6W9G)s?_pZTU&;5pPVqx+oX+vH zY%fp7Pqi`g;``fKp-bHTx>DEpy|$Fy;wx>o$mZWO?%s0PI)0x$ zn;&mubL$m9*%o#@#MDlBVO?rdf9EE__;Rxcsyopcq0C( zwfV_-(hea{#mAWSPshKpHSkP)sJ;5LiKA?|pPx9?n$_P=thccS_=z^Q#s~U|m#k%j z{Dk{)xRd-uFI(g5{lqwH$|-(gKU;UF`iZM-b)DuX9^OdYj9ceqwKH z%2|G*+@3qzPpq>ho#Q87u^0NuPyA-(XFsvM8T5;vm}Ti#KXIom-zGmX#Tqs(Be8?M z(A^n{L#@f5#S(L^5ue8rd)T4(i&)}Jo9CCY#D|u?iY12FbYI63D{WdeHIw!SB4CeF6k ztI15mRln_2Z^b+M9CmA%GSiHAW>m!X?2k3YMXQaAhEr{w}M22 zN&9w?*wR+yJ3-<{6Ybp~@w2t%y&!S4HSql)(biV$2SH+vwdMJE;$a)}g?M7RP5xp$ zVaImwrFh~O+vG3D6K`9SUWq4$*d~58o_N~eYw^T`wnVST6L;I>Z^RRg*4*3MCjPcn zcSqaAF*dV1+a_x574B-As5Wgk<|OVgCojlJxE~g~Fej01OM6jH;%+M!=OlXCJTJ*f z9ANXjG$*mIrK36}-m@h-x>I7kP2QnTVyN34`Xm7xBOX5yjl>NIT&a*Xt zK$pbl`SxRUT@tHo84l`_$gl<;+$FKlCO@Q0VkcXXYivwgutU2fCfZ!aZAi?qmo40o zc-3Y$ena9QYfJHl#B7^O$%aIZt&q|U3F|?66E-A@ZB0}^lvrcWO@1ixwas&{FA_)C z9?9))$E;b7J-vi6UEuIbS43Ta%i;NQ|&$nEOTIIeWc%Ut}L{&n?aMz3dar z-hJJ`hc@43ZeUkiNzHEH3v1zWH{gB`ZiO2-!B*o+H?W0m_cgXjvoE%h4|M}$Z9a#E z19r$->jrYSv7g{`16SHMINS{snd(QlffuYTN4kL-w$|3$WmxvTw!|m9fgfy@o#F=0 zwgo)Z4SZ(HeVQBi!`A!i**36?HEe%3@S`=%oe#6!?Rnn~ykN`a&I#F9nJGL4FH;`{TiTyO2m;I})nYbHx(L_qPfh+8_vfaRKwjtWMfqpjUwr*ghP1Vi~ z*l)Yoo9;Hy+oo#o20pd*o#O@`w~;%zfeITZ*A0AY8{2*t#mk;zYpjzSxYtN$H!#f> zIq3#|ve$C0&Tea)&$^FZ_9xc(3^(wltyTAtgX~XiWoEhoTL-ojHsIb7%W?x7ZMoc7 z*#m9W*)QFB*~4swXSjj)Y+JbLyf%f_*389zY@=m6^<8YQ)HXBNKImgxy`B3j_I>m_ z?ps?d@PfXIJuMFQf*lmMvN*&Gc2w+Pai|yUq}bi!FfZt*xTVG6_NS^9yICCJ1p^ej zS{&&G0~Nbi9A$s)N-@u3fim#tw#lsma>EgP!b(PeAeFy&mAt!=}V zJGg9(8=;)zvbAoca(kDpd83rKaM{{7TDhI&!PdT=mD{>(?Hi-q#${{YSmkV&t$n*F zCtSAn?W!Di+1fWwIm=~hU!ii~vbAr#a;D4Hz9QwA%htYP6O}RKB<0AE#j)dU`?p_j z*EqqF$dIe;JRhu&J9C^Nrv=B`IWIKibWJKl&QO#gXDZ5&vlL~>*@`mc97P$jK~aXB zt0+UxQwvD`UtL${6ybGKM^*j3G}eW5_eg81k$#hCHW?Ax4D`UtT${6w=<;alRV=vhDZ$HB>SA#nu zLpIuleDG%6nd1z3H+aFW<3mH<)1)%weMK4afuaogP*H|_q$oo^R+J&1D9Vse6=le0 ziZbMLMGW~u8AHBQ#*nX+G30Ay4EaVGL%vnUknfZ+&epJSgpOi7=XJrie zMHxeWRmPA_${6ySGKT!Fj3Iw0W5}P%81k1ghWxFJA^#{xhP)m7$+my{!Pfl=-U$uK z8SRGcewkCp>yQ~_+7G1KNhsI#W&&SRZ*AEwd$Y(rE!$;zoV=A~yDU$Tdsw#1@@#T< z%XV4bhP6jU0__5I@NX`g%0UPrpi@tXjZRf|GUe2N&{9t!G^n@1e z$n>&kC$cQ+N0vqX$+BnwSr!c>%c4PKSyVulMT5z*Xb2gLh61o?7yyfg1F&cW0EGkO0a!E+fJKD>EE*5Mq9Onm6$7xS1b{`Q04$mS zz@mu&EGh#;7WMICYfO-wk?wX0{ z7S)htQ7u^()sbaUJy{k_A0kCL30E-p?uxM`p7VQJTqJ;n~S_HtN#em47 zazFN{36e9(?#l%gvSSz@kF{ShNO!MTY{g=r8~ltp#AwIsg_O4#1)#09bS+ z0E>1EN`WLb0$Sr%;|%c671vgkarEIOYo zi#C#F(FJ5#bRijwE&^cD#Q-e21b{`C0Z02W;iz@jSvSac--i>?A-(bWJfx(0wn z*8;HUIsg`355S@u09bS*0E=z{VA0J0EV>1NMYjU5=r#Zr-42K>I^B=em>@a(xa*=b zWYMg!FXqRcU(TX?{Gi$1l?W}mm+58EePmg5KUo$%K$b-hl4a3DWLfkuSr$D)mPL<} zWzl0~EP5P(MNa^*=t%$;Jq5s`rvX^>3;>Is1z^#004#bQfJH9=u;@hq7QF<(qL%?! z^a=orUIk#$YXB^I9e_n|0I=vk04#bFfJJWsu;^_-WYJxI>`W6RXP6V`Zdr7Qy&)F7 z27JW&UMPHGz z=xYELeFMOvZvj~J9RQ2I2Vl_;04(|ufJHw6u;^z17X1RiqF(`6v*pBF^kq>tSr)Y+%c8bqS=5d!i?$%kqV{B2ltY$99mujMmyAUn z0a(-tfJL1FSd;`{Q62z`x&W}KD*%hS0kCLG02XxzU{MbM7HtKD9uxL8~$D-{4Skwm)SrlZ%dT(zQ4Y9YrgRG3Gr{8Sv_6L14;?6H; zQNN6!q^~UM&-Air09h6dB+H^fWLZ=|mPLcfvS15V9_K17L@}ci+0S2?QMeOJYk$+Bn$Sr+Y1#-f=3EZPHrMSB9Ur~!aQdjYVh z5r9Rr09Z5|fJJivSkwf-qPYMpng_t5`2Z|h0KlTX0a&yT0E-p^uxJqgixva0XbAv| zmIAP7UqED0RYvT36C~#n`$$kwEsG9!r?+Jpap#w_Xk|w5f_>aQye`_0>1EL>vMgFn zmPPxMWzhj-S#%&-79B*EMF*2*(II46w1$jDhXSzZFaQ><1z^!S02Un%z@j4nSac)+ zi;ehqEi4^bSeOgP6J@k z>43B6%c2X(vgjhREV`I1i!LE!(WL+^x(t9tmjkfq3IG;e3BaPO09bT20E?~xV9~Vz zEV>SWMb`tc=mr25-3Y*l|7TpQJqPqZ*MQ3Hi z#+V>E@4MU8XUn1v_CcQD?u@we%UN`PMzBYLEP8SoAyqi(UX=(Te~qdI^9|?mWeX{6Y_vw!JGvdxKXVJ$Q!9_!4(I-qVi#{dGqR+^(=yS3x`hqNrz9h?{ugJ3K zYqBi*hAfM|C1cTd04(|*fJHw5u;@ns7X1XkqMrd+^a}useg$CBCIA-w2Ed}<0a)}0 z0E_+vV9{RyEczROMgIV>$o?{Q)TzcIAAm&}04$0DuqYFNMFAkP=);WI<0eQ>S9^ye z_(&F==0a91?)-8VwTT6v50gc0nO+vPBg>*K$g-$CSr+AxWl;yREXpOzqK;%))QK#M zI+L*|3BaN}02XxtU{O~97Igz)(Ut%#>JGr79sn%b3V=mD0a&y(0E_YgSkw!EMcV+d zXj=dl^#)+kb^t8e9)LxC09e!)fJHk1uxLj>WKkj(Yd_p9ddl4*%8o@n{dO4^c8bNF zU(TX|v0&gxSu}|0Wl;fH77ZrLq9J5iG?XlhhLL5_aI!2KL6$`$$+Bn^8H+{(uxMuh z7L5U5(O3W$?E=7}T>)4$4uD0404y30z@j1m78L`qs04sTr2s6N0KlS&04yp4V9{;> zESdzsqH+KhRRFN45`aZjfXJf$u~?l6lJmWLH+Fz5>Th4L2&!Xo=a;jnE*7j9EsN@z zUKULu%c7}dSu~9-i>8xh(G0RI+MO(mW|C#m9%NaxCmD+x09dpa0E-#{STqZOMY91| zGzWl1O#m#K3&5gz04$mhz@h~JEZQ4@Mf(7-XdwWL76GtmF#wB}0I+B&0E_koV9_!F z7BvH~XgMIVs3sOW+XTrO?yie!Wzo*=7UYUp-1+4!S{)1S8Y7GLXL?z509h6tNR~wh zk!8`rWLb0wSr)A!%c4Wcvgk0fELuy(qICc)IvjvSM*y(sNB|Zc1;C=C0a$bl0E>9uCnNSrk6z<$+GAIvMjogEQ>B8%c6_P zvgi`BEV`5|i!LL}qRYuxbOiv5t^{DwRRAoy8h}OD0I=v<02W;bz@qB`Sabsbi*5v9 z(M

x*32)w*au{Rsa^=2Ed}*0a$bg0E_MfV9{LwEV>(jMfU)(=w3i%(S}%TdlMw* zdG~JYxw5E>y$c)M7mGW;oJ9}Cf(eDP=wYUpMURkW(W7Kp^cYzdJx-QIPmpENlVn-+ z6j>HMO_oK^kg@1l02Vz5z@p~?So8t_i(Uj^(MtdD9uxL8~7Hto}qCNmD z>I=Z49ROIgBLItb0$@=;02cKJL>9HpjBPSOa!#^uCI{^@qn>_=`(EmR%((N*Su{8^ z=r&On4Pkm&G?XlhhLL5_aI!2KL6$`$$+Bn^Sr&~Z%c7mhvS15V9_K17L^0Ar~-gRl>jWN z0$@=!0E;FAu&4$QSu`j!wu=dpbE50%7s#Tx3$>YX=a;i+YG%-|n=G2f^s;C=Sr*M8 z%c9-MvS=n*7VSZnMSGHEQ3F{P?M0SFjbtpE1;C=&04$mVz@jDq7R?1<(L4Ya%?Du7 z0st264Zxy(09dpTfJKV{ShN^`MN0r!v=o3v`vS0N832o#0a&ygfJG|+ShNy=Mf(9F zi|R9D>r9ZGUhaZ=iY%&i7Ol#RJHMPo2WAGBl*^)nm|hkgOqNB5kY&*tvMf53EQ<~! z%c8YpS+tHUiw-Btq9e#ybR+f02Un&z@ifXSac!)i%tSy z(Ru(DoeaRDQvg_WDgcX417OkV04zEKfJJ8lu;?rR7M%^iqH_RPv;h!Vw0~yoNfRXJ zH;cgmvgkKw(Ycv%=a;kSg3RE{N?CLv)61fZ$g=2SvMjoUEQ>BB%c9H3vgmTMEV_a$ zi>@TgqN~VQbTt5rt^r`twE!%-4uD111F+}@02bW{z@nP~SadT0i*5m6(X9Y1x($Fu zw*#=~4geP23BaPe09bT40E_McV9~t*EV>VXMfU@+=m9`v(fOIN4pnB+qweF48)eb2 z?JPW)8Fzj;iyqAk3MR{<$CzFgJx-QIPmpENlVn-+6j>HMO_oK^kY&-cWLfkaSr$D{ z#-bMhSo9(Qi(Ud?(aQiVdIf+*uL7{>H2@a94#1)}09f=N02aLoz@oPRSoAgki{1fX z(YpXFdJlj_?*p*t0{|9%2*9F`09f=f0E<2WL>4`q8Jl8)PHV9_4{Ecz3GMSlUX=x+cP{R6-v`&#xnwt_Q#Eb;+ZlmWn^7yyeh z0az3OuqX?FMR5QYB>-5I4Zxx{04!O_`BoyoE&NtQ)EZUNcMcn~d)B}J;TLG}B zCjg7K24GP>0E>D7uxJ|q7Htc_qTT>3+75t4+XJwu4*-k$0GA56;$qMrUA?nZV&5O;n#i-rY3Y?>?@&h)Zq z1X&i1B+H^vWLY$tEQ@v~%c3!4Su~a`i*_N)qFu>YG!B48g#auX55S@#02UPku&4xp zMWp~NngGC}i2y7r17Oi^04$mWz@l;h7F7VSs1krhRRAoi24K--02b8%u&5S*MRfoy zss}_C4GCg>O^}?o+~=-`%AzKB^Jq#CcYZmGW&}am3|X{0)61fnWLdNaSr+X{mPHL@ zS+o~f7B!M((JZnonoX8PbI4fK1i+%X04$mZz@qs8ELs4-qP+oFv=0D_76Pzn5de!8 z1F&cb0E?CauxMWZ7A*r{Q8NIGmIJV81ptdy0ehm&Q|5oB3( zBv}?6MV3WJldj7AFG60KC0btRo04zEU zfJLVRu;>f`7M%&eqO$;4bT$Bs&H-T21^^bF3&5iD09bTBAhPJ7Aa=6}lJl4Q-1Wh- z=n-ep#vtzeau!`21h4EVi!Nb$S#&8`7F|Y`MVFIh(G_G_bR}69T}75fSCeJYHDpV02bX1 zz@mEqSadG{i|zwp(ft4{dH{e$4+600ApjOV42UecFo^wbg5-2_;#?$)-p{r0NDy~^ zIg6eMg6@s7=t-uRMNg4s(bHsE^bA=RJxi8F&yi)(^JH1{0$CQlNR~w}k+JAy02aLh zz@k?HSo9hIi(Us{(Hj6P`VRn$-UMLLTL3J28-PXc0I=v?02aLmz@qm7So8q^i#`Nk z(MJF*`WS#kp8&AvQveoy2Ed}v0g*+I1+j4^NKR7^6X$VR@PEb2~{MLo!}Xe%-n^#owi)&MNZ2VhYz02XZnz@lvdSkxPU zMcVE0KlRh0a&yX0E_wou&6%(iv|F&XdnQK1_7|B0Dwh<0a!Ey z5LuL)6?@tQ$$87YkJd3O>gjLi-qRnN6?c9)i$-PzU(b_8qnKV6jV8;YoyoFj3|SV9 zCCj2+$g*fxvMd@$mPLhRSu~!EMMVHCDh6Ot2>^>q0a!EvfJGAlSX2hUqTK*kGzox3 z~P-GZE+6?c9)i}uJ0hU_hi_GEfl)IgR+dy!>PBUu*BBFm!LWLY$aEQ^}R zvS=<@7R@7L(R=_FEdXHA-T*Ax2Y^Kj0a&yMfJKV|ShNIyMN0u#v@ZaQmI1J+8GuF0 z0a&yGfJG|-ShODii&g=!Xf*(f_6K0m0RSvI5P(Go0V0cb&x%bmL2?erF>z+fqW111 zYX@h=onOwP!?J?a3uVz-rk6$Q$g=2gvMf4+EQ^jL%c7&mvgl~CEINiPi;gABqT|R| zbUXlyP5@xhi2y7*34lfG0a$c00E=nMcBoe99AvjA9hHUNvx z0btPv02ZAKz@qa2Sad!Bi#7tV=mG#1T?mLQT9Xw!&jiUi(0zLUP+4@KJ1||86?c9) zi!RFw?prL2E@ygKbOl)!T}hTjSCM7W)nr+84OtdlOO{2~k!8{KWLb0r8H;WNV9`wg zEV>zhMYjO3=vDw0-3Gv-+W}Z~2LOxi1Ypr!04%y2fJOHJu;^X@7TpKHqWb|@^Z)>h z9t2>~LjWv#7=T5O0I=v$02Vz4h%CA!EB28Il5=!m;#?|=9&mqE;qk1v^UGQEbXE}T zD~q0CdRg==Sr$D{S@a@V7QIB4MK6i{fz1As;U z0btRa04#b7fJJWuu;?8C7QG9=qW1t;^gaNKJ^*0RhX5@42!KT&1F+~502X};z@pCp zSoApni@pG0(U$-$`U((P^ki0SM-wFHF!w&%Q?h7X%)-}Map#w_==-c-QnM`jf$3$@ zk7QZ&6ImAhOqNBzkY&-YWLdO{EQ@|4%c9@Ovgi*o7X1mpqQ3xG^fv&D{sCZ-7gx6( zi+lhUWdN`!2Ed|B02T!REXo34Q5=9p2>=#l1F)zK0E^lJu&5mXi?#q@QF{Ou%qUWYMYaD~=uGap#w_C@&tYUm=USFug45N|r_4$g*fl zvMlOOmPI|tvS=%^Eb2*?MO%|)Q9c=qdI7L#8vqt<3&5h@04&-LfJNH_u&56Ji~0hv zXa@im?Fhi4od8(W4}eAe0a!EufJFlVSTqQLMFjvX8VtaqApk5I3c#Xa04y2~h%D+H zkKJm5@M-0)R!804%BkU{N&y zizWlGs0M&VwE!%t17J}-0E?youxKg(i>3jvXgUCkW&p5gcR*y(sCev86C|gXI~I+W zMYG(^qnYuz^UGPZS3KBie_7PX^s;CcSr*ME%c41CS=2<9MRUorXdYP>%_qyE1!P&Y zHyMle0btQW02VC*V9{a#7A*l_(NX{w?F+!7WdJN{24K;002ZwPV9`nd7VQVXqE!Ga zS`EOW{Q+2X004^)1YprY04zEffJKJ@uxJe+vS`nEY`h7Qv*(s3PJ=9}&bM%AJnsB* z79AcBW*;bvj$nFObR=089YvN!N0VjIF=SbEELj#EN0vp$lV#BfWLb0~8H-K=V9|O2 z7M%>hqEi4^bSeOgP6J@k=>RM`1As+m0T02ZAMz@l>iShN9vMdt#r=sW-xoe#jG zjQ}jV0Dwgo0J02W;gz@ke4kwt6cv7=0ooFCo$XzOIrm$?=$jmMo|&Y~;h!4(I~ zqN|u*7F|u2Mc0sJ(Y0h*bRAh1T~C%pH;`q~jbvGL6ImABOva*H09bS@0E=z|VA1UW zEV=`LMRx+Q=q>;j-3`E^djME;F93_~17Okp04#a{fJF}iu;?KG7Cj8WqDKH&^e6y} z9s^*};{Ysr0)RzN0wRkpkH?-hL2^!apWeSh7QN%{7d;h^JHMPo&&7jp*T|yhnO+vX zK$b->l4a3LWLfkwSr)xQmPN0UWzlP7S@b$t7QI2nqW=J}=uH3?y#>Icw*gr64gibZ z1z^#804#bRfJGkwu;@bo7JUT3qK^Ss^a%iqJ_TUWX8bw1QA>e9)?c~%x}>E4?CE*^J&Ig5UZ2gBCNqMw;w7X3n&MZc0| z(I&Di`i(4$ekaSKKghD^PqHlfi!6)&CS%b*04(wn>b7H%55S@f02ajnSd@X??gt)zltpJai;{`B^UGP(EfE}WxGdU|>19!OvMlOBmPK2UWl>MEEZUkZ zi}J~`s25olZ9|qt+mf-UHvo&a17Oki04(YQz@okYEZPBpMLPnpXeR&`^#fp0e*hK@ z0ASHT02U1bU{L`8iv|O*Xb1p{h61o?7yyfg1F&cW0EHF@RM57aN=a;i+mqhTuk+Nu4rk6$I$g-%AEQ`jIWl<4X78R3aQ3+WVm6B!A z1hOoeNXDWv02b{Az@kY2EGh?JQ3U{tDgjtj1;C-)(e3~&nhC(7Jpfp=Cm^zDOd|G)36k?v(!?1ni;7%mNW`6A z&Z60gAbyN2n#1(6sEI6#=8|R6JhCjBPnJas$g*f}vMkz%EQ=PBWzixs7A*!~(Gma_ zEd^lFz5py*2Ed|b02VC=V9^Qy7Oeze(S86dS_QzO)c`EoAAm&%0I=vl02Untz@mcz zSab*gi`D?J=uiL_9R|RnwSdT?#zd^236k@N>!Zz*MISkf)+OT3FK5wFiJ;;*S#&hh z%c5h*vglZ{EIN)Xi;gGDq7%rn=tQzCI*BZc){|w?$z&`#1%O4T0b02ZANz@jq% zSac=;i_QXI(b)hjItPG78vs~zE&z+p17Okl04&-Fz@iHPSacx(i!K6S(Zv8Px&(kl zmjbZpG5{7`4u~u|A`x3=g5>17+to+PqR-t$(iMrg^UGOuO(Hnu1X*+~)61gk$g=2q zvMjoREQ@X=%c7gevgl^AEV_j(i*6;$qT9$=bUOfx?f_uXod7Jl3xGv;1F+~G02bW~ zz@qyASad%Ciyi=A(SraidI*3;4+F615daoF3c#Yr09f=m0E?agV9}EREP4unMNb2; z=ovs{(N&4q?IuXh?gGkA0a)}I0E<2cV9^%+G67f=0I(R02UDms3%z#ZB3R%`D9tti!6(_Av8WFKi~0hvXa@im?Fhi4od8(W4}eAe0a!EufJFlVSTqQLMFjvX8VtaqApk5I z3c#Xa04y2~z@iZVEE);GqEP@W8V$grodH-h1`t`aWp?Zs6C@|k{oH={?5L;T&%FaO zHaqV8auyY42UndTi^em(EGi<)qGGZvDk00FQnD-)(e3~& znhC(7Jpfp=Cjg5Y09dpa0E-#{kwv>^$DTJqa!zn3v2n6!hCLU|%8om~oJDi9gYVCh zMe~?m7R@Kiq6K7Gv^QB6?L(GD3(2x*5m^>3Cd;BFWLdP7j79qbuxJ?oi<$vgv>bp% zD*#xu5`abf0kCKl0E<=wuxNh(799Y3*L9h+%_?mUUg@*tFzn$IXZHeq8M3>k)m~-;)4uG>U2NR_?r}ckz=7(PSSn3q78ErwUWGR|LmZEC16ip>dQ4JYIwG=3-qd?I#3KZ2-ps0ZYMU50FYN9~Vb`&U@PJyBs z6eyZWfudOyDB7L^MLSTSXh#YZ?L>j1W(pMTOo5^n3KY$zK+zlu6wRfG6iv*D-)TTn zZ~2>8nH2T*Z-%tyB;A)QT9}h~>k28_h3TbeSF#i>B1_R?vJ@>LOVLuY6fGl5(QafZ zT27Xt6=W2xq(IRs3KZ>5fucPqP_!onidIvgXfFyB?M;EAeJD`0F9nMBqd?LA6ev1? z0!0T>py(h96dg=~qC+T9bSMRi4x>QP;S?x3f&xWHQbda8=fs06P0!FU#{r5oJ8NNrRaF3m!cEMQgk9&icTU+(aB^fI)yAnr;?@UG_n+(PL`rG$S69K z0!3$0py+H06s@5^(K!?-I+p@P=TV^OdD7usaMVC>a z=yD1aT|t4OD=AQP6$Of}ra;j(6ezluB2sirPQ229q~7&^H}+U5+QfH~uFFZfFIRL^ zPGbJGQgk!ZOVKT4DY}&`MYoZq=ytLc-9eV3JIPXX7g>t#CQH#hWE9;?fuj2;P;@^9 ziXNaq(SsBydWZr=4^yD%5egJNN`a!sC{Xk`1&W@aK+%&FD0+$lMNdn-Gc%u~k&Gb_A4_S(WTphVf zQH(4_S!5}Slcgw|EJX>j6m=j=QId?Jjua^BM1i6l3KZp1peT<5MV%>7luv=86a|V3 zC{R>Lfub%HDC$aqq9O_u6;q(78wHBGQ=q5^1&Vr7plCe`6!oG&(fSl9+JGWb^hZv- z$4#c_YX8eKe@f9ce)6byZqj|ZqK$GBV{Vb6jhSAG`jMq*6S5R-N|vI{$WqjwEJd4> zrDzMX6m3bCq5)(S4WvNPAPN)>ra;jU3KW%4plB!siiT03XgCFmMo^$=Bn65_QJ`ov z1&YQ{plB-!6m3m`qOlYx8b^VmZ75JQo&rS^C{R>Nfue~Nk)l4i@tq7vYKuMwr*Cd_ zq<@H$D$7l}FIO}vH?jY1QZ$+ArKpN5Mcb04XbM@1s>xC`l`KUyWGSj8OHmzJil&iK zR8N7T1_~54QlO}b0!7KJMdkPfoK!KtiDNwW%1&W#}P_#1z zidra8G@AlNb0|sVvJ~w`mZIfkDOy36qLpMRT1A$k-N`80g91f+QlMxx1&a2f zK+)b5DB6btMf*~qXg>-R?N5QC11L~*AO(sJqCnBX6ev1`0!4>Xpy)6P6dg{1q9Z6! zbR-3ej-o)((G(~;h9Xk5OK$v21CrX${|Mi%QuLx-mpC>z>AqaiiMff~yQSzPrkA3V z$x?I*S&B|2OVMd$DLS1jMQ4zu=uEN{okf<=x(wU-9wh5d&yFCA6bg-C!^>A3KTs^fue^fQ1mbbiXNdr(W4Y7dW-@^k5i!N z2?`WFNr9rLC{Xk?1&W@bK+&@lD0+?pMbA^9=miQCy-0zgmncy5G6jlWp+M2A6p^Bv zbK|=kkkkeK>#(;-(F)%%y_TDFU#{q_+{EekOVQg*FGcT=rRZI<6un25qW8&C^Z{9l zJ|s)gM`S7bm@Gw~kWut01&ThSK+)$EDEfi|MPE{&=qm~oeNBO)ZzxdoEd`3cqd?JG z3KV@$fubKMQ1l}OihiO%(a#hp`h@~Tzfz!R9R-Shqd?K`6e#+GB2x55Zv1WolA7tK ztKXEO4!te>nVWQ9t|-V$yz`(G#qx9{FGX2oDT?#vs0Rg# zdQzZhJqi@{qCnC56e!w&0!6(kP_!WhiuzDQivG@xXFX(!*7x&8|47lTuBdNb(tWw2 zP4W^OKO#k&GQAXSMwX)fWGUL5EJa(8rD#jC6b&Ft(Lk~k4I)d?U^0q^P@t%U0!2e9 zP&AAJMZ+mjG=c&}BPmcciULKWDNrg@f0YUK!KuC z3KUJGKv5Y5ipnWaR6!9b+Bh#h*?^={{%LH#yy!^(V-J;iN%!T7w#`c{d`ya_FufF2 zlci`XS&C}NQdCQpqB^n^O(RQDJz0tx$WqiuMo|+5ingOb(R2zF&7eThObQguqCnC1 z6e!w(0!2GgplBxw6g5+zXlDu(wNRjFHU*02P@rfo1&UfJP&AJMMe`|8w15Id3n@^v z3q_=8a$fv61Cr|Kr--Vg=q~@=*j@9I?#mS|%}ZSOgcL1fdMVnCEJe%7QnZ3BMJvft zw2CZ6yOX7853&^PNtUA3WEAa1fug-BP_z#PiuR>I(S8&t+MfbN2T-8sKnfHcM1i7% zDNu9>1&R)(K+$0oC_0=1MMqGe=tv3_9YuknqbX2y3Uc=nS$Hok^CWv&d3(Hd%_+ zkfrDxvJ{<5M$vf`C_0}4MHf(@=t2qKO22L+0HQlMx(3KaFCK+*aXDB6GmMZGCdv>^qG z`cR;#F9nJ=qCnBc6p^A>=lItKBsIXlYMs?NI!61*74_?!bYHHhf9FK!SEOijrq{M; z3$he#NtU7kWGNa*mZCvqDH=?cq9J4{Dj`eJP%?^!QJ`oz1&T&cplBooibheOXfy?i z#!#SWD+&~CO@X4Z6et=;fue0FP&A$bMH47cR7!!Oi4-U*qd-wP1&S&tP*h2QqDd4e znoJQX+O%_gr~yg!EigEnNzo%k7OFZY-Iptx+BwniniSPAy%g1wrKpZ9MbpSqR8N+o z2C@`2lBKALEJfRqrD!@CMKdT+G?M~FvnWusJq3z(pg_@%6e!w>0!7UfDB76+}kAgRUv zz3XZz`qp=nmUK?KFITj@bK=Z5q-X`xOVLWQ6s;ml(e7j^+Jh`bdy=JSHCc-GB1_TU zWGUK*jG}!hP_!QfiuR{K(E$`FI*h2biRe#J15W=OP=PoH)=AVGP(>dwBT+s)e6T7}IMISP~ z6n#XNqL0Z^^a)vtJ|#=hXJje*oGe9OkfrELvJ`zqM$y+4DEfv1Mc-1O=sOA&t))QG z_Y^4lfdWN8QlRK33KacJfudh1Q1mMWiq=t}=r;-!{Z4_RKPXW2Ck2ZBqCnB#6e#+K z0!2Z-4$M&$qlgr}*ExQI0ZHZg*BjrLqSO0Y$jVQ;FIUtdKXJo{Qj}zRDe6d;qE2Kf z${|ZpE?J85$WqjqEJgWbDN2#0sDO;3LJAahp+Her3KSJlps1JvMcpV+)SUuFJt$Dr zlLAHSQJ|<71&Y?EK+y&iDC$jtq75lf)Q18^eJN115e14ira)0Y3KVTZfuc<*B1PHx z@mCE7{5OS&9acrD!l&iiVJ-sDvy< zL&;J!j4VaN$x<|ejG~bgC>lk9qR|v68bg7itte2mH3f>sQlMxY1&X$zK+$*#6iuK& zQ7HwACQ_iNi~>dF6ey~oKv5+HiY8H@Xfg$gswhyjEd`3EP(+G0&yTPFi7C3tKRVk& zic0+Bkm~%T`*KBf`H69#NzpW>m!f*I6g7~gsF5s1O=KzBjx0sf$x<|fEJZWPQZ$Q< zqU|YAv;zf-cBDYjP829=ra;lo6ewz;K+$Xp6wRSP(Oe1?wNjvH9tDc#Q=n)81&S6@ zplBBg6zxiZqD2%aT1AqaiS^0@4zLKJ|nO=(4 zkfrDxvJ{<5mZI~>Qgl99iY_2a(S>9wx`-@A7n4zR2?dHSr9jbT6ezl!0!3F)py)~p z6kSDuqN^!TbPWZHuBAZHbrdMNo&rTTP@w2W3KZQ$fufr!P;?6gif*Mq(QOncx}5?= zcTk|{PKrp;8Ts*V4M^&G|K9bPQdFL0;ja9o`*KD18=s5}$Jx_t67bsBl zA_a zq)zqkU4JA+GyE%SiB!^kxuQ;~#MwVcQ4Z5fQ7&1E^2k!unJh*5WGPCKrKo@`MTKN3 z>Oz*Hu4EJyQJ|=p0!7^@P}H3QMLj4`)RO{5>rtSn7X^yer$EsL6e#LVfuap5P}GM4 zMSUqyv=If0Hl{#PKME9WLV==9DNwW-1&aDpplEZ7NKrBszu$nQs{KS`$5eErzrepS zyG1JLzFg6uRN{l5q-ZeHOVJRr6qS&rXee2VhLNRcI9ZBDkfmrOS&BxHrD!x6MPn#X zv=s%4wx&SQSPB%4qd?I%6et=`fuac%C@Q5u(L@Rql~JImoB~A^6ey~sK+z-$6iuc; zQ56M>wxvMP6bckoQ=n)n1&V4YB1HpI@eV(mqI>*9kAYGY4-eQ|diVmef(P0!QI-CMUM^K>XND34kMS-HD zDNu9_1&WTPK+$m&C_0`3MJG_8=tK$>okW46lPOSi3I&Qzr9jbX6ev2K0!3#~M2dD# z#ZNLIsb+r@+e3;r^4~{0GnI5-uIQXp;-){O=v=0kqVvd7bUs;%E+9+Mg=8tZh%7}H zlcneqvJ_oPmZHnZD7u^iMORRu=t>F{T}6SSt0_=)4F!s>r9jbj6ezl$0!24apy);l z6x~FDqMIpDbPENFZlyrcZ4@ZFodQL7P@w2e3KZQ%fug%9P;?JPr0DEa{B;A88fr1I zMv4yhouqqHN%!T79!w>E`%8)*VtOfhm@Gw)kfrERvJ^c=mZHbWQuG8_ik>7((Nkn8 zdYX))XDCqgECq_5qd?K~6exOu0!1%Upy(wE6unG=qE{$T^eP34UZX(K>l7$@g91fw zQlRK93KYFffueUPQ1mVZir%9@(fbrA`hWsOA5uh$?oY*g|80t1^3Ty8kfP80`$Zq6 zlJ3hDeU?g$5Bv`7d)J>cy%c>xmZC4oQuGyBioPaG(Klo%`j#w3-;t$gEm?}bC!^>G z3KacFfuf%%Q1mkeihiL$(XSLJT1SDR-zZS@I|YjVpg_@|6e#+O0!4pQpy(e86a@u3 zY)4Uy0!3LAD2h{{D4POB2?`W-pg>WQB2x58Dn8eMqz+xr;Cw1YkNVqN$AYB$az%Ls zi9@rbs58?`Q9fCUQe-JAAWKmpS&F)lrKl@eii*fmR7{qlZe$d7r$A8;3KaFEK+$>> zDC$LlqV*|Iv;hT*dQ+fiLkbl2p+Hez3KVTbfufBmP}GkCMVnBdXj2LlZAO8j{uC(M zoB~B#P@rf_3KR{Xh!o`%#IH0Ush++olv@xT=^x=A%?>O`x-VB$QjmBmTZ)DlqBqHQQpG@b%Q6DUwrN`az@ z6eudAKv6jbiYh2jR7ruNNfaoWOo5^*3KVTifuboCD5|DF(Nqc))li_QmI6g}6eyZT z5h)s65MOIRQgi%sv>{S7&_9i>FG#vCSF~M0qA)2%)0tk1W{{<5CRvJRk)>#RvJ~w= zmZBZWQnV9Uikit%v@;n+Efgr4O@X306eyZYfudFl6wRYR(R>ONEucWrLJAb^LV==P zDNwYC0!51{P_%>sMN27Aw2T5pyHTKMIR%PVP@rff1&UTtplElBNKs=!e53(MP4f?6 zo22NHE*ADENV+dqw0A*bdM7E`hv}tgU$PYKN0y@f$x?IxS&9xMOVL4ODLR-eMTd~3 z=uk3>4x>QP;S?x3f&xWHQlRK43KShpfudt5P;@K>ijJc|(eV^0I)MU3CsLs3BnlLr zOo5_PC{T1N1&U6iK+)+GC^~}zMQ2i==qw5polOxbT3ry|$AF|}^)WbmNl~qzJX%wb zbYHIM{DQ80o~vJ^c|mZB%fQuHKQik>1%(bHrpdWI}T&yuC+IWmf#r$EsQ6exO;0!1%T zpy*`^6um-$qE{(U^cn?O@X3+C{Pp>>aZO}F$xrAQJ^SJfud{*6eTE7)PVv;NeUEoq(D(8 z3KZo~M2bEyh}Rg9)GZqsoG+xPpPw(vElj#ESClGDEbSsi1xznRg=8t}LYAVgWGN~l zOHnadin@`ds5@DTdXS~4CmBWSQJ|<71&Y?EK+y&iDC$jtq75lf)Q18^eJN115e14i zra)0Y3KVTZfuc<*P_!8ZiuzNaXmbh_Z9##eEh$hmfC5DWDNrF4=JvqK7#?#mSoFHGE0Bt;{bUW!JNrDzmcibj*AXbf43wjxW>)?_If zOO~Q>WGUK)jH2-rD4IZlqEZSJO{73k83l^UDNs~Ffuc$Z6iuQ)(PRn~RZ*a5TM86S zp+HeJ1&XFpps0odMYR+ts-r;BGzt{eQ=q7U0!57!k)ol6@iz@fs-GX+50j#2T~SkE z(tWw2nT3fzx=GP2rkA4a$x^ffS&DWfOVLhbDQYH5(avNkY9UL}Y_b&1A){z61&UfJ zP&AJMMe`|8w15Id3n@^v3k8aHr9jal3KT7-K+zHk6fLDd(J~4Y?M8v35mm*TMPhotX0ZDzCG&uW8(R&`wD@?jCS9DQf;_zNlbTQLQ(IsRlx|A$M zmyxCDa1%vK!Ktp1&TUSpr{iCigGAWluLo4JPH(bric`MRTv*_KvH`a8l11CXqJB* zlHVoizFbk4E{T~NNl{m(m!cxF6cv-Ds2f>|x|5}-2U&`GlBH-pvJ~|qOVRpd6m39( zqTUoJ+K>W8eJD`WmjXo_QJ`pJ3KaFDK+z@?DB6?)MVnEes6PdYHm5+*78EGjk^)5o zC{Q$z0!4!;P&AkVMMEf1R6>EGp%js#f-dp>3`lAtKkHc7B|6eS*YG5UbxFD}S2U_i z;=F!RG@9w9Xbf43wjxW>)?_IfOO~Q>WGUK)EJfqVQZ#`qMWtjEO{73k83l^UDNs~F zfuc$Z6iuQ)(PRn~RZ*a5TM86Sp+HeJ1&XFpps0odMYR+ts-r;BGzt{eQ=q7U0!57! zC~BfW(RLIlnobcZ8qp>GumMT!?;o9wl%lJ{1GX+n_vMOq=#uzkQz_b!>7{5VvJ^Fw zrD$ie6t$40Xf|1j=8&amE?J6N$x<|rjH3AzC|W>)qJHU)~-P@w1>3KX47fui#$P;@>8iY}mt6z$(7US~j3 z7h6mmAVsfrw{T&Xr27iG23d)XJDois78Gq}d)+}%mHj!|?4n)mQ<9EF$J!fVUeR^7 zQ&mv(f^E)WT)B4uZy_ zRa*tYjH0{72Eh(RvGGB$bJ3*IAedWpY*`R2D0-rMa7xiDI|acRMZH>r zU``9W}b(Xd^D;Oe5)i-O?#qWhKv!Oca9-GbouqA4qa;O?Rm zR|UcSMX&7<1P>Q&uvZW~UNmQ)Ab7gyiv5D%`J(R*2!fZ3MjRXjuNUooXb`+z^uXak z@P1M9s37>bXzDRR@Ojb6#|6RHMQ@xC1Z#^nJUIw{Dr!A72-X!{b$Sr|S^WK(w)|to zqt^IuwifSuuC0Ms@k8g^Du@+#y2#c+thn|PTM4n^Q!lf%5G#J`3R?}a;=WhgdWaSK zzh>VrR_y;AdH-0k|9jE{V#WRs0uPB5`@iTqJXY-gB;6`y{; ztμ|Fcw+W5xdO3RTC7{U3&@ixvC7?9mu2_J5jTMy%NXw*C&WV*lglJI9LsuUpTJ z75kqjUJxtxzc0HeR_uQubXly}|H9+SSh4?!zCB~byS{I$Csyo#BAIVM)@e<zf*$BO;8-7bz5`>!iq z9xL|WH@P}i?7uK@eXQ8O@qKfw*uS!Sd#u>Mb9r~H*uOM)f2`QQ_4IJ8*uS>&c&ymJ zckpzq*grUaK343X{Jk72_K$8}j}`m5_qSuke)9DFSh1h|`Z!kXr!PK_75nk$*Rf(h zfLI$V_C3I#V#WRzzAjem+u%QAK~8p|y|6BhUUJ=93T$N#%k7%9m1;ki+kde&#|?}H z-LJGm-PnlySAeh29=UDI9GtwbuMj_kwMq=X?R@jRx+L>5v_Z=WmmnYgb1%i&>fM zZ&R&r+oX=+g+vf^3NP4m%h4SsqC3p(8q3XXn=r3)5bwyt<>q$I&C4Bachk9hyIbYk ztukgRrKr0s&|O;ec`4LghS#>;Wf$G0Zq?N$O0>;KQD=K{{>a7Q1$zSB2F1qr4 zS=F^L)}_OQ9;Z+2=?~IX zUbu4M?ybS#1xpvV4sKc0y650QiVsPuw<`pYf&0V;3 z@XDo27tLAFvT(_Y!SmM7*cyP&(=3&i4hYT%gE*awGKr06>S-PZkU~9|lg#$~5 z3>r4juO4Jqx4UZa!XIhboJ=y;c z@BRM?g56tIw)(mV0x=poa?l({);za$UdyUQE1OrYUe>x|&;qw>5aupiveJUtG=9x< zmM&hrbV+l|vW3xQz5W?Lw8%EI0{dqu%>p+8hq1&Nsbkw%9f9~Mg_y8f@9M65%6 zek@TO?>Q*Zacm;dVM3xyhghO(NutZZ-WCTZx?1$n>uBtn=(?dU7H`RgL{~1xh9$b% z%?E7ZS9R!-=n~(nPk6C=qD!yvLbpVh^}`Fri7p%Xh4h{4!Fbedf~@RVaU$1;RHBa$ zHWy*+ld#7rh%X$Qh{d}P%1YUbx3ZzGxuU+lxvFNn((0=6=F<8}O;ams8UwDFTG7x@ zI;o<$v9`9ky0&IgP+u{rxumpga{3l!jSWpUeOc|)y6TEXyJb^Nm2OvAHo19r+YL+W z%bROz8|}so74?l3<>_m-t+P9As%dDdtE=@Zn(L}&R8%)t*49rgZHyk#?yCLGCsx;% zO=&JKZ7glBX_`8*qTZiJZGCj>VWTr2xTdzbp=n}6S$&n?tg^PLraZjasL_+daZJ0} ztgmROtF<|d?rFH)hGpUNUQu7#kTK^hx2X-2nkP0@R@(hHRL!bLPx2qntZJ$+&G0t9 zBqt8ZoYAV9<|ZC^jApK+vfWL}>Sxw9*4k69u5PZYt*U9P&{H0&+n3sCuZCemn^%U< zpuFAW6RYi|P+u9YhKia}i{(LWWkYjmd2}};!dv^CRc1W#ipI$--{!i>Gn;K)PqnpN zR@zuqTN5p(G3g0Q$}*;`s-M<8(TtT>HAD}_vW)K1?<`zx&DB*kQ_@RqdR1jrb7@^T zmu0mzH5Fy9C6re=+!t7Qv0Nk?n##&dX?kkNPHU=Ys%WmXC6&IauC%_Yab`L?>ZzqQ zGqvj4?jl@m4Ydv79F&{t^bCv$AD?HT+f|m>>!Z1$wz9Ih-Hl7ew7Yd#X-#uueQ8a@ z)T+ktp6e@0%V&m9W@0 zVd*KY4j;L>wyvTkeI1l1)>loM+*o5vw7H?8vC&`4JalDQ^^|aShYgQjIU~YH3?F<5 zRrq2GDTF}CRa|GAlg#aD_>>wyS&^qw;^%stMni zLkh#}CVru`-Nrq0%h0yPDyc}XIlq{mO+m1AZ?Ewtz1`Vtw%x!UbYgv}y`_tgKccOj z%$JZYDmJ&(wGDa^k4`_Jt%hg`PUJ#GxWZQ~oWG=XZXeriU!HzA_gq_PcV|f2HqmXH zfU>gM=E=5cN>9MDnOa*O&Aq+rr>`ulsIG3RF0D7@ld2lbv%gjGL{PK-`4$WE0ej$V6Xe|^%^dV^vj@RM7ulUwZfChc=K+j z30gP&}jMF7Del=q(tvX_70t1^t`Z#G?!0nY%ZT1y-Bx!M<1DS zdu^1a+GeMzK78*9H++@0KpG}zY;u8GT{_eE5C8S18ZD~&in0pZ0Hjx5+vdP$HFJpr z`(I0(wV$!4TW#>$)<1JGsdVbp()3*T^06H$7K^<+!$sBh5-uqTbxf*h>QgpmOdmgX z9#qoDkDiB&9y+{F|K+WVT3c4MZr*3$;yKG!jhnM{`O4Nk2QD5q%!-u@RxO@wuv25Vnl9AT5ET6MroE?krK6>EdL5uBZe#^NlmTft2 zS)YOP`wXld+Gn60la8hFBH7pa!}WOY>GOnX_`? z(j@~|*kQ1ZE3BK_va%(e!>2f^oxgD1NAD!Qa~`h9ikjLc+unq3+wVrF-;QigtaM^k zb=9o4UEv|NjrB=}wcAp*y{!G^k|x(C*WOC(1>b0Uk^YvPz5#13Jlttpnf970vp4vO zrFIOYEv7%F?Y>8|JE~2(y>Ulf`(q7167cu^D%;hM_7I}y8Dd*ly>#iak{}$0{>Qwu zd-rX(Q#;k}X=3e+|Cpkz+BWX?cIn%raM?r~&}M%}_O(?qWT@sly=Aopp1zy5rQ|zf z&018^6!sPvUa-{}6}F|yc)5h@we6tmU;EP9*0p~h7;g8}+UzG1T9+@6?$eIJ{>#in zTVZ?U`dmeOm?d^B8BWsv2-M$1+IFSvxKpn;KaLI;yIoM_2fATpyTajx==d+JhNN#5 zU1DRIu}>H7iP`~+_OI;48{L~dsf?wPF@f(Q+9oMP5Z<)yNG^Q{I#Tx%9enYq(I&cL zYF)+=Rhb{-XTBlW_RiLE)PE#CDtQ0m37N z^x*<`;M=lHbo4-}EG@TlF8_Mp4H5XGPBQ)J9hA1ioN~Ptme>&jPtBG>dal{;&3qX| zFWhiZF%Ld(|9Yz~ZSeD7=~E~6s!HE!`oODnVt6JjeMQECtgmSNuRF-$wvi)bpOfg| zDx4?VZL#OTJlWx)9fMVsRfTUjb*1)x6W+?+HKGf43a8!8qmzSWlkKpzqB^{Z9kr(K zF8z9`oZj4IXQymo>JD{(c5cep-y^0pJ9mr)YXn!yDqnYN0=~az(O~xBD zM|>r1rwdB#O(0mYz;?LO$IgCy7e0W!*M}GUc+QLHuq(VOPveH?T72im z&M!1iDy@o6?v-UMNEVJAS~OL+?Z^1*h+Uz~J>T>xo}rxL@gqSN6nEykGQlq4M%8E0 z55%}h=7EHrI;|?Rjg!4uG=|G5eX9mL+_lpKIt9RT%lHiG|E*6>%3EiznjbDvKd56S z{WV@XF|rk%UgjE}VWl0b*rPobaWm(&LDe)87 zJd)0WL~qC8ijK~{`^C(Y*x_N|zcxs1JE!Fp|6}*mSMbb===hgo!S)*!$IDR+`+?zn z_!;T&LUf*eYUzyTvYJM{OJ$yB4rlE@-*cm*HlAntbX<6sZRe{??Ce?QOR4RYk3ZSy zMbK`mmOiledrU9JOmFFfWi8wARC4&R_JYu84;jr!`u)+55W~t(k}}ufySS};b6aLF zv;Y37MRXFl?Je#E%*ZT{^Wc&?&i3VJ*g|9y5c-0i6>&D^J8 z3U2Cil5y-|Z)#e)(U#w@jt&xd$hv6H+s@6UmrLlywhQT^Y-)MC!%wr!I!mv;OmJG(3D)l@{?3`A5$?<%nvzi&7)kg;p z;R49qa}1C2rrYPQ{t0xgK2l|tqI2i|`P;uYmeypPaq~6M{w#{UdTsSZd)n>Z0K@0lcJ?&-Sb!O8 z+o@`IAmMj!*qiKWF>ii1(SbmCiH&D;g0i`p!(i?>V_Q7Aeu}NE=;c;rE57Z_+w@X9 z(q^;yuPObMkH7sz%ct!er=LAc-!y%i*^lWa)%y|jzZP%1qe%A@TK9tz?u1z@D=o7n zUD+JIeFy&VeBXfM6qlvfUFJba#3f^I!ViCLK3|@^L$uvTw05S~)=$xHWcr=H#P$#~ zwhOi~;bV*TM>m!B;W7sX{-uXtQd!wnefs+;`O@W!`&2BR-8y%!eVo?FH{rsw^nAl@ z^Z$L$-o7Vn-*)=Pe(XDf`{djAAN%>&pY-Ej`&#``qdSIfiOJ*DvljrP^?uzyG6M;h&`;bH%s#-BCXSHHvFzpUzy>wlZj zNBe4bICjYjhig1eBhpvEUOKCkgLjqhswMB~>Qf7JN9#+ZF& z*_Tg8jVX=YG;W}=pT>b2M`|3eak9o~8fR&oqj8bORT}rxc(}$BG@hyPLXB5xyjkNt z8Xwj8oW|ERexUJ7jX!GqQ)9y3u>ASvYwWJEkH*b44%N7|#&V5QHEyS|S>pnYyJ_4@ zRU;HGZdYoyM5`j*maT9F0X9H`eI?NVi`< zPGf_;H+yc@xXLbjK2YQ7w%g(PB8_+08@%U7G`?j!8J<7W*vEcT$n!vr^X%6{Jo|6< z_;|JbR*;W(X#Bx`PsH;-8b@y!id7dupsNjdHWbGs>cTiN<#;qWqP{ev_kIqH&jPqr8X4>#L)DkH%kWq8zV{ z#oud4W#!XwIJWS)F zIZQz%N0h(Q*nh7mkI=YepD6FG@#g)a{D8*a4~TN|z-XLsa5PTUc-Wy)K3U__he!Dh zja`n4@`f5`924bMjprU0<*PJ)Y&*EVe!kbZ#mP|~rE%G*QQlYMt*1x%A&q~Y8RbrA zMdQRZ(O9eTh;yTSs>Wx}kMdg@i!O?CUyZXaiSm4n=U*1(Yczg(MU;QkIN<6ikI}gN z+9>a@@%HPZ{D{WC?RQ80`R3jfjpesQ<1~#&-4^B3H9l`U`hNR&G$ej~~^X#CQCyVa-vRpXF%qdZRI?(awWV2yWw809B4 zW_=Rnl*Y-QMY&1iabHCFY>h8}73B{!uJ>(}H`BQD+9)s9c`wF5cNe`p+TzpU%IRO4RuTf3eQ*Lc7E`mX0^GRUeHU6qGdtfwup~l`Cx70XVV}-_g zjmrcFO>Ue*ZYr;wtE_mA7n*ik>`B-4OI2PpcShZuWYd|f2>%! zJQ^2p$-XDLG8p7v%nSz2Ua=w=WM3s6NCh%VN7xY5mkeEh|?pUpRZ! zO1sRe*=qQ|yxkDH&A%V_ za_ji<_2xeV?7vR--vs;5e_o#%3-908qu<8=^T%tn|Ck567`$!&tuY(?aH-CU%=>%a z?r(yj@%!^-!2RuPmzl;c27B6x!2>f2E-wGq?S2~^3;Os3`r&pSat#&!0#-|qe< z*!}r(_4%`xdHVkB?K+$XUw{6yZdfe1W#j0w|KI1&|GQQrx4UL~EZEjMez@ITR`_Lp z*4gcB7dZXn%f)|gv;Q)m@8pc$0aMwoO!Zm^|d}e}4V@zTm!~pxcD`W9CmAbivK<^x$2TjJT-3ICE?R(A3QyGeYA z-5@@oYpGwp#2z|6q^Qv@Cyw{&V;!DJ`rl;mkj&2BG;xjHqNDw*irJg#?+R{cu_Vau zuh`q-&>(wr#SJVD3$nLRT;JmGAbU&2UKU3L*#i{Uvp6!y9;n#U;;0~dkYW#uql4_h zirp=a39^SMcC%PwvsI#8?AhjPsB)2Ko3UZaT|L{J4Oi~s*=B8oa-nCNw~@*Po^9qv zDW^Q!+>KVw_iVE_M!B7;^DGaw`P*7K*R##vSmhkgHh<%kJ9)PG+eW#gXPdwA z%1O^Qe-o5Dc((Z~RZe)e`J1Sm?b+t9OxZpanK;zuuUt9H@-Umf3T4}tO&n(PSE+34 zzf*R0zxZ>u{&W1)V)iECU&hN>Xg;zhC9km?xR5D{=WN3g3aQql5;9d$LTVHxq*hTv z>J%kpnxcf%D@sU%qJ%UmN=TC;Lbg*z$aH0d%uq(iOl5@3Qbx%3$_Uv(86i6=BV;FK zgfuH7WM^fBv?wEFwlYHIC?jO9GD2FF5i(C1A@h|HvOpOj3zZSFi!wrXRgQ#I#lN@p zpEJ|8W7*qALUyt3RQ95z%W)yg65rdEp^)7)se~+7l#msQ60%ZJLRKkC$nJ^~vWKFC z?5QXrs}&_=FGYmxt&EU;lo7J8GD7xKM#%ok2suC*AqOfWF zguG=mvQJF992atGqN}|ZhC)u$q!MzvqJ*5GC?RJmO2}D?5^}bpgsf4NkaH9zpy3RZ$nOrgxunnZ%u}O zN6UoVnHXUkl~BlCnp8sWR+Nx?6eZ+dMG3i2Q9|xll#mA$CFDUx33*6SLLOE`$Ro-K zc~lu8k0~SMab<)&p^T6xl@aokGD4nKM#wYD2zgc+AY3ZrOIr^U2*T`*BT*qSyRv zDDc8&vzQ{~h0SL-ihM6@M!QpV_QK}02SuJ0euUGLBG(I>)AcBFys$a#MbXI%o743v zI(lJqx&cMf3!Bs46dk;$~5$MMKC^R6>@bp=2ojIbjV0ZeE2@blHnS6lp`u!*m!dkd6ip*bQ9W6T8pu-ANS2}|vJ`Dc zmZIroDVjk>(M$>y&7wfj_7o`EfdWN4QlMxj3KTU{plD|b6tz&GXf_3k=1`z$E(MBO zDNrWc1&CEb@Rx+j+SZ9OTvm+7VG zKC%?uPnMzw$WrtmS&AMaOVPt*DSCt~MURrD=rJ;i9;ZOj6BH4{ z=xquVy+aWxx+@m%ZJ(v*`uBvh@0Oz9{jA`-v84NQMIXizC{Xk}1&aQlK+&HRDEf;6MSoME=pPCc1zG8%{OA}h zMuDO%ib&D>vG`mAlDpCm?mv*CBYayF&q}&4SCq_39BSWc4Hb1{dMWBemZBW86y=ho zD32^foyk&^PnMz-S&9nCQdCGrQ5Omnb)`U25e15hDNxjn0!7^^P}GA0MLj7{v>pYD zdQqTgeF_w9K!Kv(6e!w|0!4i&P}G+KMH^9|Xk!W#^`k)1CKPOoHl;w(W)zX4L{|Jt z1Co21pHS?O6&>lX^=(oAtfc#LMFX-DPxY0eflMz&gUC`em@Gv@$Wl~7mZG6#DH=wW zqTysI8bOw#kz^E&qCnAT3KWf@K+#qdDB79=MPn&YG>!sA+fblrJOzp-P@t%k0!0%k zP*g^NqH+opRZyU)k^)7OC{Q$+0!396DB6|+MN=qHR80{n+9E5y)_~-W&oek%N>SX8 z^rvPe-IptxmX#>%Cq?y4FGUSxDQYB3Q4?8;wj)c?bg~r9AWP9qvJ}lCOVRdZ6zxEP zq8%wvv=ar2nki7UGX;uTC{Q$;0!4EuP&AhUMXeMlnn!`6`4lKxK!Ku#6e!w-0!6!0 zplA^ViWXC#XbA<1mQtW-83l@VqlgsMX2nMuklaIkTT~}So%|hbc~;VWxuV^(64N)8 zqCJ>iiuNQ+(Q2|3?M0TNy~$Fv4_S)#B}>tMWGUL8EJX*9QFI^$iVmVc(ZLibI)nm6 zhf<*EFbWhMPJyB$C{T1H1&WTMK+(|@C_07$MaNR0=r{@#9Z!Lx6DUx0A_a<0qCnBf z6ev1{0!61%py)J;NYToy_&x?CcbcCfS|vrd`nKrwtfc#LMQ3Lv&gm~jYnWb&&LK_citeO9 z(OndgqBFDN4;ql%6JiGEEGhcOceU@%O1dvsbbnUjqb;Q90j8It2gy?O5Lt>ICQH#H zWGQ--EJcrzrRZ_86g@$fq9@5HdWr%?Pg9`i8446VOM#;2C{Xk~1&UsvK+%g7D0+zk zMK4pJ=oJbSy-IK+z8rDEg5CML$uX=w}KP{X&7FUnx+ujsiu$QK0B|3Kac8 zfucVtQ1llCivFfR(LWR@vhN|EZL85fQMZF^|1>s6fubx56vZh}lud!61VyCiqpWz1 z0m_%M}fdCvGW`q9IH#MI~e@8cLR;VPq*9PL`q(WGNa+mZDK)DH=_dqA_F?ZAF2i zttn76mI6iNC{VNw1&YQ~plAXGib^R^G?4;DWfUkXr$A8!1&S&uP&A1GMUyE|R7HWJ zZ7EPRg#ty@6eyZXfub4;6xC8hiU!8xZyJ!?{(e|C2t~dvs*5Mxmn&+FC;k{FMNLdE zMca|3XgXPnW{{<5CRvJRk)>#RvJ~w=mZBZWQnV8pMa>i_+L;1HEfgr4O@X306eyZY zfudFl6wRYR(R>ONEucWrLJAb^LV==PDNwYC0!51{P_%>sMN27Aw2T5pyHTKMIR%PV zP@rffMWm=c9`7^U6y^Hnr$LJL@xAL+@ud55MXTe9Qu~Vs;koO*m|lwZCQH#iWGUL0 zEJgc~rD%V$6dgd8q65iNbP!pJ4kn}M5DF9>N`a!oC{T1b1&WTKK+%yDC_0J)MMqPh z=oktV9ZP|t<0w#cJOzqQpg_@y6ev200!1fNpy(6|6rDv0s1|;`ahqI>?ZSSPciYMKdD>^rxIDE7eoyYW2bUs;%E+9+Mg=8tZh%7}Hlcneq zvJ_oPmZHnZQgk^PMORRu=t>F{T}6SSt0_=)4F!s>r9jbj6ezl$0!24apy);l6x~FD zqMIpDbPENFZlyrcZ4@ZFodQL7P@w2e3KZQ%fug%9P;?IkiteR|6s?KJuQnjLZ@Z#% zr08Q0_r;U$%N0EoPdsD48X9hk9%gzedW0-RkCLV6F|rgrPL`r4$WrtqS&E(_OVQJ0 zDSC#CqGu^k^c)3>o~J<33lu1Nkpe|8QK0B$3KYFUfudI_Q1luFie9Hc(Hj&fdXoZ0 zZ&9G=Z3+~O@X3+C{SeI?~V@JQ52&< zQ5FS?;uI*#ra)1G0!1AtP?V%VQAdhM(WmkFXakZv#!pv&CPjPu-gT$!r2BG3owE}& z?Jqfn+oF7?m!cF|iVDb5R7jShE@Ua{N|vG`vJ@4QrKlTOin^0g)Pn*=Jtcb;!%Ps)6lOcI2v2q>yUKv7)+is}(iRG)yN z1_TtP5Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq0*d+(P}HB`DawfU?=V1u zbIpv-lp_0Aszwip4p?7S(V%GeXa^}8%=uC@ge^rw*-~^JTZ)FUrRaLL6y3m(9x@dOl2AfTv# zfTD>66ip(asE~l7A_9tv2`HLOK+zNeil!1gMb||8<2xEf|Jd(3UMoezBVVvZ2dpov zXlArqzq1tG%=uDu3tNh2v88A>TZ-nerRY|+6wPHz(LA;k&1Xx|ZEO_XPC(He1Qgv# zK+ysMitZwyXdwYbcN0)_4*^As2q;=iK+zHcitZ(#Xej|j_YqKZKLJG#5K#0W0Y%FQ zD0+y1qU8h>JxoB+3WBF-Mzp`L0TOI%|J?OWQWS6ghu7#wq65~KRkSABozzu|9_4%~ zTFaKAb!;hmj4efvv!&<>wiG?dmZGQFQuH)iik@MkXgvW%&k|7d905ho6Hv5)fT9-& zDB4Is(TfBWy+lCKCIX6HCZOmQ0*YQGpy)LMie4w6XfpvtTL>t6gMgwp2`GAtfTFDg z6unLG6s?N(KVX0aKeP8mtEFg?{fxFPI$(WSMejtruXLB9cR62*cCn@CJ+>6R&z7PO z*i!T%TZ%qnOVP({Df)yhMZ4K3+CxCmrvw!3C7@^@0Y&=>DEf?mqR$B^`htL>0|XQu zB%tU^0*Ve1Q1lf6MPCz8^bG+;hY2Y9mVlz~2q-#2K+*RE6dfg?=m&zQXh*dFkO2~G zV?T-Ql%mb{EBzm%1J;*S^lP;HPfsa2#`#k88(WHgXG_r^Y$-aPf~V-`X#W+xjG`CqXS83WsDk~Bmf!}g zFRLizx*hsRQJC|ks2p30%Cn`Y0$YkIvZbgJTZ$^PrKk#9imI}u=n^)HE+wF-8UaO@ z5l~c}fTGI@C`uuqs0IN=R}fHClYpXH1QgXKpy)~himoD{s15-|bqOe{M?g`10*V?C zP?SnQQ5pe7=>!yI5IjXmu0P)Z38vaVcb)8dU+LSwc0W4P4Om}RQ4`m_v!4_-<$Nh> z#+IVyY$K$Zf6f32c8xV~8cWemJFayD)|XW@)O9}@AVt@4z7!2(OVRagDY}6zMcHgA8qSuY z9JUmVU`tUhTZ%@qQItnO(I^6nMiWq!Pe9Qa0*b~GP;?^!MdJu48c#sc1Okc*2q>CJ zK+z-uiV6uRDk7k$n1G_m1QbmnplB)qMbiifQ1mhZMXwN0^eO>GuMtr6IsrwS2`Jh^K+zin6un76(OU!*Z6%=SZ32q6 z5m2<9fTA4)Ptl{Uf3^VpRK444HhiobO zh%H4Qv!&=0wiNAVOVJ*-6n)B;qP=Vs?IWOQKLJIb5m59w0YzUBP;`KRqJsn!eMvyk zAp(lNBB1DN0*byNpy)6GMc)!o^c?|3M+hkTo`9mG1Qh*1K+%r`6#Ya%(a!`=(Yvny z9RnnoWbcc1Nzr$f)Guzp`m&0CcikU{NzosiFGa`MQgnhXMJL%(bc!uSr`b~UCtHfn zu%+lMTZ+!HQS=u9MSl}ebe@2s3j`GXLqO5L1QcB)pvZ~Qm+dI>5l|FGK#`w-qG$q& zTmp(>2q+2=P!vl*Q5*q9@dOkF2`EY+peT`mq9lT+=$PwIxZWtTKX;A(O^V{|XSC#) zfc0e+m5*^#v!$p4=SxvVwiH!jOHpOE6jfnMQB}4SUBZ^4OW9IXjV(o&u~Af=fTGI@ zC`uuqs0IN=R}fHClYpXH1QgXKpy)~himoD{s15-|bqOe{M?g`10*V?CP?SnQQ5pe7 z=>!yI5Kxp!Kv6>iiW(6-Md28Ke*+}=k$rSsF2?&xzlr^_zi~{!`m&0e$GAl~Qq+R; zrKlxaidwOys5M)P+OVbQYPJ-$WlK>zwiIQtrKmj{MI8tz>PSFQCjyE(6HwHJfTFGh z6m=t@s5=2gJqRf3NkCCA0*ZPQP}GNjqP_$a^&_CDKLJGp2q+pzK+!b>6kSU|(I5hf z1`|9*O=JAa43OX~`$?>s6uoYL95N&(V0~Fd*T=Z8 zJxoB+3Id8AA)sg_0Y$3_C|XTG(Ha7Z9wm5+X2pY!q!Ipy)*cie4h1 zXcGZNFB4Go3IRp05>WIS0Y$G9P_&tVqAdgzy+J_Hn*Xc%PRUX#=UE-6n(_`QuHxf ziaudW(QdXB?O{vNr)(+O%a)>jY$@8$mZHztDEgd$qAv(2IzT|tK>~`tB%tUJ0YzUC zQ1mqcMc)umbeMpmZwV;+j)0;g1QdNwK+#bGihdxV=tlyIej=dgX99|TA)x420*a0i zJVo!v_%|3J!C&lWv=5}Hjs3F!x0rzSWfh%>arcaqqLZ92MW@(Obeb(if3l_M3|orM zvZd%8TZ;Z-OVQtKDLT(a(FFpE{vn{~Ujm9Q5>Vs>^kqAWd;}Cl5m4kOpeUMvBA0-o z7y^m{1Qf**P!vZ%Q9J=fK>~^r2q;PqRN~vMOD~RRFy47m$0SiQnnOTV@uIxY$>YFmZHnqQk23* zQ4Io$t{|YOCILmY2q>yeK+%;16kSC?Q5^z`>Jm^?kAR~31QazOpeU7qqBH`E(g`Ta zAfPCdfTD&36g48Cs4)RWO$aDzO7Ij_2>4qYAi)9lEB%TA?<@V9_AC8nfq?a86}1Yu z*H4n7)|@XzZP-$DHCu|>vZbgUTZ*#SQq-O;MIG2u)R8Sko!BVqOh8c=0*bm4P}Gfp zqV5C~^&p_ACjmvh2q@}JKv5q8iuw{z)Q^Co{sa^aAfRX<0Y%pkP;@N;MS}<^8caaZ z5CV#Z5>Rv1Qg9Apy*}-if$pGXchrQvk9J}8v_1a z21u};{jw}uiU!$FZ*u|x>&q&dA8>!3EJe3*z7*ZgmZCe@QgkOJxoB+ z3Id8AA)sg_0Y$3_C|XTG(Ha7Z9wne?EdfRA2q=1t;3=9L@Fz_%iq@DJJx_{0vJbT% z4+N|)tLW)~n?6m7p5c5cTF;iEXW3Hp99xQ>XG_rrwiLa1KJK>~`tB%tUJ0YzUCQ1mqc zMc)umbeMpmZwV;+j)0;g1QdNwK+#bGihdxV=tlyIej=dgX99|TA)x420*a0iQ1lxC zMZXhJ^asIH^ijaS+yDsKx zwBL0+B}El2sfw`y>&q&t8teLINzo;oFGZKKrKlQPiY{YIQFXQyUCx%G6t)!AU`x>z zY$>YAMo}#SifR*3bR_{rR}oNDhk&BG1QgXHpr}3pMGXijN+qBujew$b0*W#SD9R+D zs38GGjR+`eOh8c+0*aavP}GcoqUHn?wIFzkD#!Y-G(dvA?H`h@66<}X-^+eRYZ)7` zzO16FW8E%uq^K?DOHn(v6lJlcs6AVXIP|pW z4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9QC0*VF_P;?CeMb{EgG>Cwr!2}cyA)sg| z0Y%plP&AByqU#ALx`E&+Y8~qzXMhBYESxq{G~eDAWyc1rFRLgw*1dbK6piG3DavC@ z(I~bQjb=+xK3j^$u%&1$TZ(REOVK#C6pd%2XaWI61q2jLB%o*#0Y!xb6crIrR7^n8 zWCDt&5KuIgfTC#x6ip|fXa)gAHxW=YlYpX|2`IXSfTCFh6wM}}Xbu5Iw-Qh^m*6SN ziS=(ZK!R26L!l8;)WMRP7aOp?tfD(&-M#ar=uXa;q6KUzx{EDE3)xb1H(QGCVN1~> zwiGR9OVJXx6y3{4(NY46?jxY+egcXfAfV_$0*aOqQ1lQ1Mau~&dYFKs6$BJLLO{_< z0*Y1#6m2J} zH~~c`2q-#9@D%Ni_0Kav%$<*cvqy^7+HYi^iVav_R?*p5_pyaibdK|-=r6Vu{mqu5 z^K2=)z?Pza*i!T_TZ%5SrO1iX*X>f|W1}dFfFeHuMbQKlxdar&5Kt5#peUArqBsJI z;t41U5>S*tKv5zAMM(q{B@<8-BA_TtKv6jYipmpERDpn^iUbr@BA}=;!Bg~Stp9xj zBskXI{hW~^pB+`=0@jyRR4vZ^^&Tm@jPs?aI$Me^XG>8ETZ(G1rRWN_6xC!)Q7yI< z)n-f4m24DUMLb2FDnQG3ppq7G~+>d2O&PHZXa%$A}qY$@u>mZENKDeBIaq8@A%^(3IE7Xd}R z2`K7AKv7=;iuw^y)SrN&0R$8cB%tUT0*bCBplA>QMS}?_8bUzPPy&jsBcNy)0Y%pn zP;>(UMcD)t4JV)|hu|q{8|S~)015WDcR%fNv1}>2ku62z*itl}EkzU9QdGc}qKRx2O(LMEkbt5h0*Zyz zjew%*1Qg96py(z7ie?f}bTa`(w-8V?i-4lp1Qg97py*ZtislkfG>?Fy`2-Z*M(`Ak zjPtKBK!SVicOCPjsJ8vXMz_ZWtS_tRt~mFN`=w|h=S$JuY$>{jEk%piQnZ*YMN8OH zbT3&0*W3Zpy+V|ik={#=t%;Ko+6;=X#$F#A$W@JjPrkIfCM|48NEP? zy4WxK*T)5{FRN%noa45qgKR1Kk}XAt*i!TrTZ+DBOVKxM6dfj@=vxAcz9XRM z2mwXk6Hs)NfTAA=DEg6rqMryT`k8>DUkE7rm4KpS1Qh*7K+*366#YR!(QyKbP7qLZ zl7OO91QeYnpy*G6r)Y1Se}VxL>|^2VlcHm>W}Jx&SYKAr-*N7u6;gDb^QGtlTZ;Z+ zOVPhP0*Vp{ zC`u%tD2afgWCDsp1Qdk{C@M!lQF#K2DiBaqk$|E~1Qb;!pr{G~MO6tXx`f~K{uOHmEB6kWlVqMB?es>PO~+H5Jhk}XA7 zv8AXETZ-zkQB;qBqWT0BH6WlUm4Ko&0*cZJD9Rw9D3gGqh6EHfBA}=-0Yyy+C~8VT zQ8NOHniEjef`Foy1QfL*pr|zgMQsQux|)EZwggYnW%2&M4UnME{#B0EdKa)Zfq&)&X%GcY$@u=mZDy4DeBEeQ6B<| z`VvsokAR~71QZP*plBcgMb{8ebS(izg9s=ZOhC~P0*ZzbP;?yuMZ*Xvx}Jcd8we=M zCZK3I0Yy0k6pbLDD3^eukpxds`*?pl10-nwrlRN$QuLG^dGP`3%PJZZ@8+zPqOqJW zMK`jgXdGLL#qQdG#6q9QhmiU}y1OhC~T0*a;*P&AEzqUi(_ z%^;xYCIX6P5>RwA0Y$eEP&A8xqS*u#%^{%ZRsxFV5>PacfTH;X6x~KZ(d`5j-9bRn zodi$O=y?Ba21xJ=d-szsMVsw|qy_N->&q&-C*FPHF)3Qa`BJo)Ek#S%Qgkm{ik7ma z=sva--OrYy2iQ{dAX|!-u~GC80Y%FRD0-NHq7?)bJwiayN&<>j5m2<6fTA@76g^5n z(OLqE))7$j7y(6(6HxR70Yy&|Q1lc5MNbn@^b7$->j@}&mVlz?2%e&a@%|4Dkl+ye zjmEpBD8+uI|9pJF`m%~%jCX%~LW*AEd@0(*mZF#0QuGR2ie6<)(Q9ledYvsro7qyd zg)K#Iuu=3T0Yz^SP_&hRqPGbs+D1Upb^?la5Ky#}fTDK@D0-KGqFn?Oy+=UN`veqy zKtR!l1QdNlK+(qp6n#QK(QX2Y_7G6?DFH=$37(=C;{D~GG>ZPVa5hTO=a$sI_<;3g z6@3x!HhNl$4sgB{9b`+>6ahu2 z2`KuLfTA-56rClY=p4aQ^jW-rumKXhXg`U4E=4o!r??6IRc8x6HruvfTD^76jdUis4@XXRR}1mNRP0p91T5Kt*&6c7o*-~^BTZ-zi zrKm1jit4eYs6JbY8n986N0Y&Kq6lD-llu1BQLjsB#5m3~afTAV@6g4HFs2Kr8 z%?T)KK|oPU0*YD@P}G`$qBaB+T}?nyTLOyO5m1yxKv8>wrzj=p|K0!zeq?_dTO;Uw zrT@CUFX|8sSYK9Am!RvuAVpm{Uy8c1rKmewih8i6s3%*BdalaQ(NF@4t|Opm7y(7s6Hs&m0Y%va6b&b! zD2ITe5d;+F5>PaffTBDCibfGoG@9Tk>J;?XGeCm7>>mc{EJb&jmqq6X1J;*SG%o1& zcu|VRbG{T!U`tT}TZ$&KrDzgciVE3MRK%8|Vzv}bW=qi&Hj1VaP&AEzqUi(_%^;xY zCIX6P5>RwA0Y$eEP&A8xqS*u#%^{%ZRsxFV5>PacfTH;X6x~KZ(d`5j-9bRnodgsu zAfV_j0*V$AJVj%J{)q-iaEARc{*6*J&OS)GI~cIOtfD1BcgZFxx|j2%XenEY?qf^Q z{cI_EfGtH2vZZJlTZ$fHOVM(+6g|vF(Fy{J9wDG;B>_dN2q;=jK+zfkiXJ7PXe|Ln z>j)@%jDVuY2`GAkfTAY}D0+&3qNfQcdWL|a^#l|>OF+?c1Qb0_K+y&Qie4aiiWUX^ zFB>4iS@ynYu@n{9&uANi0qe^udO7HR{)!a6!ueA4DqD(PV@uKNY$@8zmZB|eDSCq~ zMQ^gD=qY&j_BPmxBHa21u~2g|kVDmPNi` z3kIw&tLV$1d)ez!bcpk%=qt7qea)7lZ`e|Fm@P%$vZd%dwiF#}H~~c`2q-#9K+!1zicS+y^d|vD zX9y@dOF+>%0*d}3py+P`ip~=}MF)cZ_6A7sy!{r@K`9z(NnHpAtS_s`NpN$wNRcl= zU&%{R6kCe?Y$=LnOOeZ#q8PRm1=vy)%a)=zwiLy)Q4}PgD1m^YL;{ME2q;P>peRH@ zQJ8?Das(8WC!nYT0Yw!FD5^w2QDp*(st{0Am4Kp42q?OgfTC&y6kSF@QFQ`}E+?QU zh2SarH|W2^00|zqe`m-=DQak57F{DDV0~FdwG-T@-jt#%IbVvdVoOmSwiMN6OHnP?SkPQ9}ZX8WB*`n1G@t1QazTpr{!EMa>B)YC%9z zO9F~o5m3~cfTA`86kSa~QCk9v+7VEcML^=3;^AGQ?rWlK>%wiNYeOVI$f z6b)pf=o$iwt|g#o5CKJl2`CyuK+#YFimoG|Xcz%S*Aq~50|7csqBKsH4MBkVYu)eIK zf&{n8b}5?3`BF5AEk%WFDJo)1Q88PJCbOkz3R{Y%vZZJmTZ*Q$Q8a^qqMHaPnn^&> z%>)$PLO{_h0*Yo6P&9{tqFV_lnoB^@JOYa56Hs&;0Y$eHP;>_YMRyWVw19x3y9g*+ zNI=ou1QgvvK+z(Cr)YeFf2aWx>}(%UPmrR)b}UW^SYKAreF^SOJEiD;&X=MG*i!T$ zTZ)#krRX8H6fI{<(Zg&hTEUj0N7z!dl8vHO1Qe|%plA&NMUN6tw3dLPbp#YWMnKWy z1Qb0%K+%%~6g@>i(bEJJJwrgzdIE}`C7|dz0*am|plAaDMK2Igw2^?K7YQhOiQp-^ zH^IN!014h?|J?ObDf-urO$h<(%PM*;!F~H(DSDmrrD!u-ing$&=nb|My~&oMx7bp& zl`TbYv!!SoTZ*=`QM7}AqMZa3y+c6Jy95;NBB1C!0*c-zpy&eviasQu=pzD(J|>{( z69S5M6Hv5=fTB+cDB4Rv(LMr-_7hO_839F~6HxR80YwK0o}yP0{682V!G`wk=T#}H zZeA9BFd<-lSw&x)f6w}TDf))MHs@7Ypxlr2R+u%+lnwiNxu zM$yj%6#YU#(XRv)9V4LVHv)=&C!pvL0*a0kP;`QTqLTy^og$#Rx8fTFVm z6rCfW=r00_{wAR4JOM=)2q^l8fTDj1o}xnu{ssm}aHDJBd?iIg>{t3169U$kRpd`} zdwnQH(TV^0mA=cCq8PRm1=vy)%a)=zwiLy)r6|ajq6D@SC9+YJL_kq80YxDKioygG zl_Q|2JOM=&2q>yZKv5+EiYgOORE2<|sst2WLO{`_1Qb;xpy)CJimDS(bU6Vq{KUeEO7y-)D{o#FT`MtQeOX0y65XXAOHp0U*L_hvwiMN8 zOHl*16s5AID2**e>1-*=U`tUZTZ$U8QPhZlqQ(RiH6fs=DFH>z2qPqkwU76^A z)c^_BwQ#PIqD1@Yty^Ni`m&08CAtT8OHpsmm!dvwDeB9XqJC^C>d%&<0crQZ$7vMN`>QG>t7q)7erqgDpijv88Ax8$~x0P;?6c zMY9MfnoU5_90H1NC7@_70Y&o&D4I_|(QO12-A+K!9Rw8JNkGv80*dY;plBfhMRyZW zbPoYViwG!MOhC~R0*dY>c#0+_`a2pR!5a3vj+3OQmAx-oni#OYtfB`K-Msx$w2bqm z=pnWgEoV#7!)z&9!Iq*&*iy8TEk&!?QnZ>aMQhk7dX#{owFDHcBcSLp0*W3dpy&w# zik>8(=qUnhxdVzqVjRX|ENI=m`1Qcx|py*`+ zie4djitbPJFEBuY@7wP>J|IQE+OPCqO$=CHR?(J3_nFV7=nc-7qBq%6^cGu+wz8$@ zZMGC`V@uI?wiNAPOVLiY6urYn(Ypi`?INJ)Jpzi}C!pv90*XE)py(q4iasWw=o12p zb`wyvhk&9_2`Ji2K+!$|iuMyw^cev~pA%5@1p!3|2q-#8K+%^36dfXXie69j?>0b! zd+goMW+|#-e**GVV!-;cioQ*BPaKeJwIjo4Iz~XzZv+(mPC(Hg1QZ=7py&hvMJEX;Iz>RyX#$G=B%tUF0YzsCC^|<# z(O(1<{Y^m8c>;iUOQ3MX_utiepPrJX?x_Y$-}$OHm?Qijvq;l+2c*5F15d0*cBJ zP*k3Pq6!2QRV1LO5&=b(2`H*UKv7i!iY_6b=u!fTsu56h839Gr2`IXpfT9!vifRy0 zbOixLH3=xHML&q(Yo8)dkEJgh|UyAy(rDyZ zUCWlDL2M}+%$A}dY$+PbM$vTy6b&Pw=z0Q*ZXlp2n}DL>1Qg{EP&9&oqFe%sMiNkz zM?ldi0*XcxP?S$V(HH`X#u89;BLPL@2q+p)K+yyOiV6rQnn>^z^-l8tWPk+Q**|yP zM~ddzN7s{*0@jyRG&#wQJ0e9>IA4mUvZZJmTZ*Q$rDz6Qif&>{(M+}!-OQGvTi8-G zi;be$1Qg97py*ZtislkfG>?Fy`2-Z*MnKW+1QgvtK+&B96fGd2=q>_^77|c&HvvWW z5Ky#;fTG0&6fGg3=w1SfmJ(2O9|1-86FfylN&YkgB-qa07ZpoUqJ4DzKvKZ^vWk`` zxqXgG(ZifCMJw1+^axvuRU=rIC{9w(sa2?C0q zB%tUi0*am{py(L_iq;cQ^eh2I&k<1cJOM=;2q=1ifTE2A6un45(MtprZ6cuPWde#` zA)x400*YQEpy+jir)XJ{zt{i?-fh3@_>dGGw)aJwlLFS4RrFSpd;gD8w3YLv=xw$X zZDUK(cD5AlU`x?XwiLa?mZEprQnZULMengu^gaPa9}rOVApu1n5m59o0Y#q>P_&zX zqCEr@eM&&lUIL2t5m2~`tB%tUJ0YzUCQ1mqcMc)uS zMQoI!i#&IRc9Q zBB1DR0*cNPP;`NSqJIb|`j>#Biv$!o$@;P#MLq(Gq6jGR6HpXQ@DzQQydKv5L}imDP&bO`}Pml9A^jew%d2q>yfK+)v{6r~VQRD*z`D+nm6 zNkCC80*Y!AP;?~$MOP6}REL0~x&%*AAlcv9012+QKLLqN_P)|zZb{Wk4p?7SQChM) z`gbWx=X@#3U`tUZTZ$U8rKk~GiW;+}s0mw&nzE&+8C!~)vr*K7fTETJ6tyCts5Jpa zZ3rm3nt-CV1QfL+peT!gqV@z7bs(UqBLPL72q@}IKv5S0in=S$HwY$>{yEk%Ra zQZ$$?MMKz9G?Xnx*RiE&7+Z?2XQSu_0*bN;C>l;cQ4Rq`BM2zUC7@^|0Y!NP6pbRF zXfy#u`2-Y=A)sh10Yx_wP&AH!qVWV2O(3ACfPkWj1Qbmops0|5q9TH)s9&=GQv)QJ zZ@+ilUy5qj`=a9Hfc0e+O-pu9os^>KoG(Q)*iv*8TZ(3~rRZk16y3s>qFHPyn$4D? zIczDqm5rjg1Qg99plCh;MYj=9bUOh>cMwo?CjmtZ2q?OXfTD#26x~fg(LDqdEh3<3 zF#$zO2q?OjfTE=Y6x~Na(ftGzJwQOwg9H>UBY29YB>StJGKy}uKS!G?MNim2`1nwA z!1}U^9!Yjv{3%5%IbVuav88A=TZ-1OrRY(%6s=`T(K@yiJ;s)z$JtW!1RF(95>WIM z0Yy&}Q1lD|Me7MDdX|8q=Ljfzo`9ka1QfkMK+#45ie4n3=p_P*HW5(tG66-e5K#0g z0Y$G7Q1m(hMVkpI+Co6l8w5|$!^!>|43J=BdtbCdite$W-rh_OSYKArwq$qKSt;7i z`BJolEk!%oQuGd6ir!^Q(Jr+0*dw%Q1lrAMV}K;^aTM$2M8!SNI=n-1QZ=2py(?CioPbG=o z6rCra=mG&n{}530F9Agt2`F+x`m!BGJ_3rO2q^LsP!vr-kxM{P3;{&}f~V+cvi}zY zB-qJ*68k}l=GyzB*igXwvWgNyZt#K>C33zLC9$O_nJq;jwiJcgQdEvDMdjI2RDmr; z71>f$iH)Ml1Qb;vpr|SVMVAmzbSVKv)d(oMjDVu*1QcCPKv4<-MKuU0x`KeBngkTp zBA}=?0Yz65P;?amMRf=$s!KpoJpzjA6HwHE;3QB$@QHDgOrbG8(&q&-Hsn6&*el3zq6cxl z6b)ue(Ga#24P{Hwb!;gb#+IV%*-~@^TZ*#TQZ$^6q8tK>Mi5YxOF+>`0*dkoC>ljT z(P#pS@(Cy!LqO430*Y=VplBQcMdJx5nm|BN0Rcr52`HLGKv5w9MMVS@6%$Z2nSi1x z1W(bxkbjE-65L^bbasstCEBm_r-lO7msNCA$o(oxie_@Y6y400qFdNfG>a`ov)NKK zhb=|7vZZJ)TZ-nfrD#4IMYj=9bUOh>cMwo?CjmtZ2q?OXfTD#26x~fg(LDqdEh3<3 zF#$zO2q?OjfTE=Y6x~Na(ftGzJwQOwg9H>UBcSLZ0*aOsQ1mdtQ#3u~kMbKu#r7MG zGo)yVy)Rl33RquO(dv*})BJT1k^7=GoG(R>vZZJ(TZ-1PrRXuX6g|$Cq9@o=^dwt~ zo?=VU(`*zyLqO4b0*am`py)XQik>H+XafO7FAz|)k$|EX2`GArfTB$V6unG9(JKTL zy-GmQYXlU%PC(IS0*bZ}Q1k`?MQ;*N^cDd{TM3?`l_7su10-0*-uMF$8dI!Hj#mjo0YBB1Ci0*bySpy(R{iVhP{ z^eq8J-w{xBgn**&2`D;B@Dyzi`R_46f>+!7q8(DS);_xaAr!E_tfF5+?(=a{^eg8} z(J{6Z{l=D}-`P_12V07cv!&<+TZ&GyrRWq}icYgp^d|vDX9y@dOF+>%0*d}3py+P` zip~>Ibb)}Pe+Vf0mw=*+1Qa=8ec6s89|1*C1QhuRD2gVa$R(gChJc~~0Y$L{6vYux z6i@IJ{S@-=GeCj`W=8)kMFsXN{a`p?eOX1xVfW9V6ooinio$FuD#wY5mZHjRDXPMjqN;2ZT|z+7r34gJBcSLq0*a~=P;@x~MJWUn)gYkg3Id915>Ql& zfTG$26kSO`(NzQ#)ghp$E&)aL2q>ygKv4q%ic$$EN+X~so!}`-4ErxhFp9pm-*rq1 zdtd1x)R%ywegqWtC!lBm0Yw7|o}z|f|8N5&Sl@n))<}w~+eg>egag)>RWu~* z&Iw7;P|la4>)28>j4egiv!&<;wiIQvrD!-?igMUeG=eQfxoi}TB%mmdfTB?Z6pbdJ zD4&3$F$5HiC7|d=0*b~FP&A%^q6q{P6%bG~k$|E}1QZn#P*g-fQ858UlL;uALO{_} z0*a;)P&A$3DH;^^KW=~oci8))!BXVd&uBBk0qe^ux+UzsTTY5*alRDIW=qi=wiMmU zmZG_ADVoQYqWNqox{WPGx3i__4mOJJB%o*k0Y!HaP_&SMqPqzwx`%+GMFbQrCZK2u z0Y&!`P_&eQqWcIax}Sie2M8#7kbt6P1Qb0)K+$pniXJAQXaxa9j}TC_lHe(t8TKDD zK!SDc-OtTZbekQk!U5~cDq0(M6Dvy5I?k7($JkQzI9rOIU`x@HY$1V(X(t6Jx4&%^8^%aAfV_40*W>gQ1l`JMK2Lhw26SCmkB6(g@B@02`GAvfTGt4 zDB4Uw(G~)V-XNgpO#+JEBA{q10Yz^UP_&JJqU{7v(VDQop#c)?Yyb5Aqf+#z{c*^S zaKQSqigtzF0hOibJiuSOj=u_c;2q^lBfTFJnDEfwgqQe9feM>;mcLWq2 zA)x4c0*a0jQ1k-W5T+y8m!T`Bt8ye#_XaKQSqihc{b4^@?- z-#K53{$NYdakdnlU`x?SwiKOWOVMez6#dDTqBCqMI?G1UIRc9QBB1DR0*cNPP;`NS zqJIb|`j>#Biv$!o<@9AcihKkVMG;WsC!i>rfFhTGq8I{-0t6Jr5>OOJKv6saML`0J z5(p?tBzTH`4g23TK!Q!}ebF%~DsMldC6xmN>O>vm!b-6DXPepqDpKj zs?3(6Dr_mL%9f%_*iv*UTZ*c&QFIvrMb!x?x}1Qb6atEB5Kwdl0Yx zt|Xx7Dguh?5KvT?fTDT?6xAo7r~v^*sRR_I5m1y)Kv4z(MVSN?H6(b7LgoC?)r_Kz z_5pRcocERfe1j*tQMrKiWfe6m=hm(+Ma?;1idwLxs3lv9TCt_5HCu|>u%+l~wiLBx zOHn(v6lJkd)SiH%4g?f+B%r7h0Y#k&DC$B$QC9+rx)D&+oq(bq1Qhiopr{uCMZF0q z>O(+LUjmBy5m3~hfT95e6b&Sx=o$iwt|g#o5W!Q_q@2II0TQfl;WU+^SbJYIxLm;c zvWkY4b8j^NB5~yBXxDST6y3m2?P`s5KuIcfTBqR6crLsR75~gF#$!B2`HLEK+#kJ zilz}zG@XE=83YvFL_pC@f~RO`Isak!Dd)a$g%sV& z`BF5OEk*O#QZ%0}MYpk~=ytXg-NBZkJK0jSfGtILu~D>;fTFtzD7uG$qD2H0EheC7 z2?0g-5>T|1fTH^dD7v43q6Y{ldXRvkWdsyGL_pDU0*W3cplAgFMUN0rw32|LRRk2R zCZK2y!BaG=oc}WeB>01w(X*xK4?7+$7qGsZWG5=RW?YRceNO0E^CMd)^oa!*I$?fd z8yhNbzM4x2H8DSg3xx(HI!=Yq!^w_QCG>6BajJ!`s^B;&q4AX*r&j32Dvnbp^w%Yh z(;(FLGRMgX&A;4n8izip;W*7h;aZNkfs3>~TGI9)?^Qyr&gs36^O z`i3@TI?lk*`9_X2IF!}YafXF%Z|*q5Lm#ztoROjOZ5$^*G^DNLj0>&Ga-4~wqa7Tl zI8?v0<4g-p>gqT%L$7pqoY|p&dOFU$P=`K_b4TdTevY#+^vM9nSsbc(t>fGmx^A%J zEDNm}>NqPxKMr%8)uGgE$5|ID%5j`0L$BpJ&ic^BJjdA(>Xh#|FNN+J>o~85_Kb6! zEuqQphNhE|j^%aV~_XE;S#2U-*st z%?;oS`b_uQWG;FMR15b1V45Icv?$;0r(Tn7JK%Vf(My z*Ybt!KSy527qgo&Ie^;odFZ{<=bDQ|W_FwiG=nLC_nqjanZ2xZkVZN~a%h8AX!uD^s9_b6) zzn(bX7q)-D>^NW8{so~EePR1IJQn-H_OIxh<_p`uV{N7{Z2yw1*}ky-TaM=W!rKp< zTgVr-f6vH5U)cUd5sQ6c`+xf1=L_5aRePB)Z2w=|6~3_jpCwoO!uJ1mTjvYg|6S=x zU)cWtChL7+`#%h9@P+N4_C`GTYX{sr=E8B!uF4??DB=} zpF8-_7q&k*-t7z9pZx9fh3$`SzVLzDAAAP34&1XOX80g?`(*FEXpH`BmHes`yaAv?fWm^)|n{n_ra-RL9pe(ws`I z?FE`?EV9?oJZY}EfKzFc`R(d!p_g>CZ$(RuPwhFaG!EF&TBEY)d=ie7q#n(S3{M@!r|GBw}Z-ARH zy2WVo8?oxM<~_E*T)#iY@r8Z0lgbDENtY&FQ#tGlRd$@HT29dX#NVIfIQ~kGKdEJ~ zRj@^{TY2-L(o15^$xR$vVv@~e?K6S$zF^S1q|eOQM8_Y?iNRoEFd^97d_3YR|Hq}` z&85m*eNfZ&UR#2$(oB1miMq$C7YAn(zhd&Xx>cwn!}N2T*oP=cS*0L ze44LqRo;lJs)l{#V%k-Cuzgkg8Y{SE-n^*Fue3KGoQjSAYpYbYRWq-w@}0N(%m?=V z_Ej^@)l^wu8QG1p8)h`j z%+AcPG1bJ>2?Z1KQuA^~j7iPRNNbd8Uz}!M{2wn$A2T6$+~kpY>Em;9^T$m1|Ndqa zO)o0@kre$<@|Xz)9SREbQcFG-(~1it9}@2)(zmc+tofK1r4N{xQ+Q+N$rG{% zn)hXN-*J?bYOe<7S$YQ=Df%T8^U|x?zi)v|Q^Tdt~0IoXO*gvx}!s%qvRE zx4g`4HFC^^Vlxb%0UbJJo3}ByL&5m*1rtm&_dRGCW3Sgsj`_skMrisQ`CPaBfA{2; zkMX%a|L8QgyuWIS>&B$J70u;M45hen=3$gCrm<@uPWh7E+L7t=W?JN>Q85i8Im(>i zniog;r>D4;?K4;D<>@6aZxDI;v^4MKP5;Zwz4NE)<^DMD^+%bv$i8Cx8X{Mm=3W_@ z{wZm0Mf;pybBr&>pO6xHf82Dp{N?t2iAi&PHC*@dDEnKjf2S_loin;R_L$i`qigmE z@7bn}OP+1gq2$@7&2`Df&1qSjoYB~OS*H%VOs2W;n4Sd%6EmG&S%b4X^d8vIyY7yh z(xl||H6t}DeZ37!UT=poSE)C!Aty8~xm1hD+cbGX(U{Q_@w zY-3(=mO`_VH^6*AORl-(l{DscbS(W~m=A$2Xx?P+!)UI>d#22r(2P^f2QTtM^MTcQ zO-ioJygj_qhPr&C(zl~S$r+g)cva>NH)nL4&@rbtC)@rfD{|$QLz#Qk|E>Fyj(H;{ zkM`a*b7PoSZ0?@Q+!}hL8kfGE=9c#^Uhl+dKMElPBb6 zW@LI7$t?Y#l)0^&=^D5_JVy39o0opX%*WHaj)uIxQU{r(5Hib1FgKE3ZOMm*nm70{kJ)VHbJ6?LDXO_9u%iP*cc|#&sU5b-Cy-fIUL37mG zkZHU|-U)6)b9bW`H7faFnhyyVFIB(|%IHe$$}EO28+(+Q-ZxCQ8MRn#fGEz z!8ETn@{IYI*q23aVv3^Wf4 zbVcSG|2H2p@`%%WAQHJ{42H<-vce*t+`P|eol4$kbMxyREPbZ|W^NR{tOSy|{k^xn z6sEcFGM9>6dE`X~md-MtbM#!v$IhVl&Np}4j(N;l=-m*R-a(&mODSfSS}fsTO3-{R zH`ia3Ur<dO zMkW;JPaZ$Q97l~S$SF=WUmdhDH_J#H%q2%noYEw+XN~(E~+a}k%0jZXpOCLLyK4Q%DfJda5&jxz4N^c=gdC8~Q2n65W0pR|G!ItwA+RUt*%HS*JS~0XSmuEvk4{S;CGs1>K5+Ct zFoNhkLX5oU_F<_WsYc#I?{{6vd(H2%63bAw4^M9_xv%9>Xz3%x(g%u}rFX>mF1hhb z9+H+k)+~8gS>`uV>2HV92Zh|$-a|tBu9Vz{-s4KAONS0EQ|j2?I$4F|Q#y?wkvDRr zc|1OlFRCNIoA_e6?tlM#%X~M~d>i1Rc{1PIn3^T)@Qi>~0S=&S6n;;ZVr#CNH$ny-4) z6}~j@`xzzIYo95bqMZ{L%f8V6A1}4vx$wT%!DamR>(Me#e)F}c`8HRXr)Vc^*5H!D zcL%-TcOu_NEP1KlG2aR+^W=BTck0VL`JJ-g;IVIy`R;w0C%^f=f7vI0VyD)~|Iw%M|9CiOuBN~F zRo%Qf_9GBw-c5V^N0|?v{dn19MIEc!qj_Nsdo=HE9d&!V+sm1sDMXIuCkc^bdma1g zc#V$cTMdzykJWLKjpUg!0x|vY-nx}yW8qGt&+Fr>-eVmjbdN^ zfsWCadONIRck^Q#`|?3LF23B`kLdWB`M}zjAJMT|EpOM=am1D0F3|Bwa|77RZ_@Gi zdfq;-W8+kBXX!Y@+)(!Nx9hky)7u~E7}MC><#p_7ZcuyqAv)gM+}o>k{Gz3|kLp<6 z-0=4D^>rNC*4vYGd^*e9ujqKZgSY?Dv1w;-chGTWS8v~`CRyWB)nc&en0+TyH<7id#a8b7JB;)9nak3ZT}+g*m{X~?55+bOTE2F$6fb(d%uoJ%e;N5jsur_ zJ4eUmE4=-Lj)zxz`!^l0T;uIVI*wcG?ddvhe9YT#>3Hr5Z@W)=$E%Ml#buM;_W|ltn<3Jo9H-Ui??sm@ufGt{kD#O zZ}oQIZSUA_yLarR<83>=y;R2!-}UwZ9m~D%?aOr>{Gqq=bX@tdx1Z7R``z9?p<}(h z-fpJj#QomBS;v<@_x5%jFPNWdTK{ney<_`B-m#C4cYN*b`*r;Iu(!X|vBD8=*U)k3 zQE!jdarKYhepbgHe)je$9UC0;b_*Q~fA{t*9bY}}?VURQYkqKQ-`?OU@7VEA@7Pbr z1!ukeppLuE&s6Q@ztXYN1#j2XaoE4!9;4%<=Fxz?{PQ~gWPa{y_n$hNZ!kx8D;>b&OI(9Zcq_r;}pyNXG(^|V9((zOCV_Unw(Xop8`K{fx zb-cm+AlL32bzEnDqHFgHI{spQv}^ZS9W%_&cxn#{Gh#$x-W2buykdS%Sa#+V z=1dr!r&s1(;=h)0_NRQhM)TG>X}RX7QhDa55oKQMsKT7_=0aKhd!^+R7Z;8hF}c`W z?f>-2Jd88H^SsB&_8fbAlzlQE&d5^@^Iv;8zc>HOt^LiJU=Q+nb>wImlFU3BiCth}&*=4WqxVb+2d%|9y{VI;@d&E4?Ip$gCUvqu- zay;>}hfFAYeNN}n>q|5*$4v0(_N`Pr+*Sj$H1m7QV=zZ!tOY#O2JV;s1F1>a_Gl4C!K# z*K42u#QZAz_EjnK{@VL0-oC@;dGqc~G>6F3Ky!U98RlqTuYIydey`ZQ*j%oiiIvUs z_N!ofefHySUuT&Qm$SQ-&*@|uPh4NvgtC{bW8S{wT*w@`T*=S3N2L{{r=+B0Hp^(* zJfmUrhE2`$85x;n{@b)^*Or9ok>z^# z33Z&R=H4{*=W~7foPMczPUqy#8+$G5ys=08%AMz;vv!_4oUz{=od)L*md{_`bLTlH zbKkk>eopH7g9GyWoURhuVM>pavj^-rcPwL8P5a*-Cs#*S!SRd!KF4PV`<$K~@6@(0 zS=nP{cY9oW;#h8tR`$7vyRGQ4~L~_aixrdi>`#42~+?*XQ)cqFcIe zI~Se#srlv9KYy^(nV`Q#{Ycv}9vZszFQcJ6R!a<}rsgZYp6E|@d64k+yYLC%1J zVgBu>W@r6v%7#H%XUhAh_nOi5#-5+&^c%hH+`7KzET{bNn)%DTbFL}wQQUoUx5-_P z=GeC)rFPeon1#@)H z?zy_h)!o~6Ya6*G+nt&3n%C=eG#|Ov-7hn@(mL}oIOdpJE2XCSSTFZJ3VrQIp;Gr< zIX#9C$iL2f6h1YcGP~_M=a{$N$xQFM>s)l?xn1XC?XgCK9=pyZq}11sbRPN-5l#}_sGsk%-=!-Xk3*ZuTRg-NY$I$AaP(_zj+ zC-%<=W*q+dt%K?P+wMC1Ueq<;n#;~{W22qfPV}7jP7geC(`AFcOIY%7bl=0#C(?E- z4NeL#@0Nc1)Pe6z?lQ~g%$t3nES_sspcM~ zlD&5+^AzQa37R{YC|_)>dB_+Q<^EmK9s-kUm^+iR=08!rs+jL9m_O9vCIn1sVD9On z`cxerNr91R)b}{IH$9QHoIm}YyOhO%^t|43`E(tg zDZfb9`PuTc^dsnV<@9vjo-dC`@9zuciRn*Hug;k+4{E61ny%L1hH6XtiDQw5>eTcN zV$p_bTe>zw8mb?rD|kjjbyWI@pV?3ypRUTJhH7j2-g$OI_1W~{n%q#`GOZ~M)n(Hs z`J9I8g6VHLx1st_dgsqe$J0mo{D$hRboDN1sCG{8)z1yphO~ZZsIH#O{Mt~Rl-~Mp z4b@KR!0!#!>(Uh)*;w5%y`lRXtKHLe`La@-mafECmFf@aLpifj9hBbQ*OltHX=~{2l zR6Q(x_D3{TA5K?r!=~zM>5pvGR2`Jw-o{PUb<+QB(o{V!y}eD-e*z^P*sQ7ge0s+= zZ>s)~KCW9dRVOB3Bhw#AF1Ku|-jM#XQBBp!>1UIznyMqyr)}$|>ecCb-rQ9ECS8dh zMfHsI9`!7$m!vCka8Z3SeMZI?)wR>7b3#!)EyZ_>Y9)P3ey^zBn9RLjR0pNM`h%i+ ze7Y_l7S-F*75u2EZj?Ss9~ae`>AJjBR!61}`O9VXk#zi(vbuD7v#*xbU(=`jwX*tN zx=OE?)hE(N;*GNUe2O#5>gMTV_GVcfp5E!V%4(55Sa-KpmrA1VX|2wk{<3>pt5>JD za9?Zn)3h#bul|@6T+&{BC0+ST+pELVRl2Ob`b+x1%iF7Sr@!-x_G)|jJFjf7j!El; z?$wU;**vj(b-whWs|~Eanckz0fz^-Gd%It+>app%jOkTfE?u+zdsR0~Z+2|2>c;6$ z9?+{gIK9&c_Ns1@-pzx0RlBE8__$uxBa+yIdsW->2dh_gy`*(Quj=shkw2tYbdB)8Cn{;9Z>)fvgek-e(3(v?_wYIW!IW>=Y79g+UB z;Zv*a>AI{owR%n8PMubtT0J3sJlB|7O<(^ytvR*&X1XpLK307){j-f8s}4*5xBblO zL+Rgu9cEUaPal^ZXI76%CU%-xJv6-!JI}1XpRU9%Gpo;~Px!7gt2?A?z1z&@d|&l` z9SxnDpGxn{n0#SeI=g?quwVMLkIfh6O@HQqeBu1`896XtI4yk`56Ty&rN8Bf^eJtA zJ^kS$^M!-b-*Z&H@M8Kv9Gx%h+CM!FJzrQceGZPz7Y;}t{^Rn6UDEq-e7-O%y`yJt zmo99WE}WGwOi9;vQoitEde6?z7rspI_vCzG@$@Ff@02c#OCP!k`NHw(eab)IHSd%@ zL=E{uOZx2R?*YvX>8(i7k?3~_a zAiatFP*?K?>EEKJd?CGm>Agr7Zb+Zx&iTUp>HW%os`=IQFL*<~@Jv$Mm@mwcu0}rB zsbxa?i<qCb#{h^sjZXW;r<1N;aViPhtHX*ymCS;G;gzOo+E@bV>nDqH?zbSpiD%PnB8JxbB7kiaiP8PCXF(&c( zpO7(eG=%IQGlYzd8A1+-8A1+>8A1+<8A8Uz3?T={3?buVhL8y{2{|M-A&15$WMXVW z4vS65;jsxhA~qpM#wO&b*n}J%n~-B-6LM^9LXL|~$nmiWIUzP7C&nh^q}YU<9Gj3+ zViR&|Y(h?pO~~o72{|KnUC2I_N$K<7{%rb5r`WeH_iCA>^W%A!J%iLN1O?$R)7}ximH*m&GRJ z^4Nr25u1=JV-s>!Y(lP%O~^H|3Ar{lA=kwwWj`aC&zbyS|Q=DBFGBW)rRNPr+Ia$cP#U1H~r2h%IFOG(g z`(uWX2V#bh2V;hihhm11hhv72M`DJMM`MPN$6|(%$72%mL~KHyj7`W>u?cxPHX+Z% zCgj=Jggh6Ukmq9)@A#cPcWJYX4 z-i%GiTd@gwJ9b^j-IW>X^WQ!z{lH$_Qy219x(QOeQ)W3?$OpxYbUWdHLOzV6A>^Z& zA>`wjA>@;oA>`ATA>^}|A>{LzA>@mgA>_-LA>^x=gv^Xh$k(w6nH8ImZ(2&I7Dw-OK-sziAw|r}+Xo%DE zq`g?D^h&bWbEiEt-KA#tNqbnQqH52T_Trt2X1jOVOLQt)>^ak3vQyD&&yn_0or*Sl z_OzGoRCKX>rM*n2qN_by+KZ(t*e>+UAzj0o&?AR*6+49PIi%~@P3V?Gx{}?6jvUgp z>><>0NLRC`(4IrOp0f#Eb4XXTm(V4LbWLX$+EN&ruIU^?YYyp}&MCCykgjQOp*e?i zP3ID-IizdaM<{bh*K}^7a}Md6&Lb2#q-)w&Xv!g7(|$sF!sPIw>6-Qz8dDgSuIao& zdcFAYVd@!G>ao^rh#2iWYJ{ z6fJCrqCs{j8f=H6MeIC|XgVXeEK7l?94c5hxliP_(K*(P{!ks|ysZAyBlYK+#$PMQaOn zMFSfu$0Z=O2h%-1#R8!yKbl;u(@ju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlLd-S z5hyxUpy)J#qSFP6&JZX%Q=sT9fuc!5UD23^O1JdQtk#k4?Jf2XMSJF-qR(z9v#+e^ z+=gOUdi>#kiq3OB6rFE}q6_R$G}R787uuodB0CgKvqRCvb||{U4n>#R6kR4zbh$v$ z6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z2XMK=l*-6T+Svp~@;0!6n96x}9Jbh|*& z9Rfvn3KZQXP;|FYS2U%eGBN?FP0c?SofC?F{@-n}hBEugiXLbv#`g});9%D0*I?=mmkI=>kPB z3KYF0Q1r4u(JKN)uL=~sCQ$UcK+zilMKc77-V`W$OQ7g&fueT=iry6{dQYe;y04*f zQ36tXD#N)y6#bqa;40p4D6_Au=;Masq4apx|GpM|;(RFj)DA_T*`erjI~09khoUd- zQ1q1@ie}oO=xaL^&9W)_Mxf|hfuipOioO>p`az)RM}eZB1d4tZDEdX9=vRTF-vo+& z7byBepy*G5qQ3-+{uU_uN1*6mfujEeiaIsM?QV)11d1Akx}pyoDxW4GwNDeJ;-gUX zSAKk|(pY9+Sy9MS5$RA6gAtSsKpLNt#&ACvqMoAI}~-bLs7dOifVQ!>aZ#5 zCQ#H}ps0sHQBQ%Q*#wGu2^7sPP&9`?(VPNBy#WYfS%0dZ9ZR7L+c+t7BeoMbsx+}3*ps~!pvZ6ta#kvcG zqQTCGqDAabw5T15hS;HKF*_6uwL{S`I}|N$hoU9yP_(2?(NY3MOA8b&BT%%gK+$pn zMav5mtsqdeqCn9~0!1qe6s;mqG+dx)Re_?_1d3J{C|X0HXib5lwFHXR7ARUrplDrz zqV`*k)4neG`-`@6bEVHky=%B`8#-LC%&iPPuupNrV+o5QJ9f}UIL(!pjD4J-8qQmS^bhsUg zj<6{@QlRK4fuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlLd-S5hyxUpy)J#qSFP6 z&JZX%Q=sT9fuczQMP~~XO%^DcBGeTf&{+990jc%OPh~qW6g`rj1XrBXSY}^Y(FKh~ zpG8B_ROds{g?1>q$PPu*>`-*E9f~foL(!#nD7wrJMVH&5=n9*nD+P+K5-7S_py(Qb zqH6_;t`jJ_UZCg(fub7)if$4px>=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cf zqI(63?i1>Y&TFg;Pe5u1=DVxU4@H;fZ*TWEmf2TU^l)Rb(_*3M5$8kEqjo5I%nn75 z+o9+QI}|->hoYzKQ1rANik`7U(X%#1&j}PgFHrP?K+$x8q89~nd#NI+`6 z^F#Cxg`)Y>Pu0aojb-+g6@AuNTr(^beeQfH`oa!HU)rJQD?1d;v_sL?b|{)SO6Day!py&^QqCW+S{t_tqTcGG4 zfuer}ivANQO1~ufg7j%jkEo{`+4<4f27#hRfuf2)QIkMXA=DLp(pZ_EfYdfhk8l*9 zhN9_tbgq=yS60+gDZX1G6ty}ZirVZ@)Wr@(UF}fRZik|p9f~^aP}I#1McwUC)WfEz zr$Etc0!6(9ie?umnnR#yPJyD{0!4EP6!j4(np>b~9)Y610!94|pg_?=LS0d{Qt7c|QnYV+@j%gBso&CXYfNL|N|}9SMT=I7C6*3F zL!1vqi`k)Qs2z%i*`a80I}|NphoU9zP_&dCik7xR(K0qg%L)`NCs4G!K+y^UMJoyv ztt3#ivOv))0!70GidGdUT1}v6b%CNa1d7%aC|XOPXl;R_bp(pm6)0LyplE%8q74L! zMhJC9gDaI$2}o_B{N-nnP&Bxb#)g$L`^t(otrUkW8;Uk_J``+7xXkP_(^3(GCJdI|>x-Bv7=oK+!G&MY{?V?Iut(TA*lm zfucPGiuM#J+Do8lZ-JtH1d8?*DB4e;XpBJ7{sKi~1&R(3>WVh5R4z_HYWt=aDHWT9 zqEY!S$O9{7_LUWluN03gABrY8ABqmKL(!pjD4J-8qQmS^bhsUgj<7?~k#;CL$__WaoyDxW7HwNLZYr4J58duK)GSIX=wE4rvslq-dz zY0ihDi|tT!i5-eAwL{Tmb||{s4n2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj2biXIRs zdQhkKLM$oke_P( zXeio0-|YXiQf6OS(U+BC(yF28E9XPeOgj{PZHJ;+b}0JB4n^PEq3An16n$@pq95!~ z^rKDDPXa|h3l#k#Q1q)n(Qg7pzY7%oAyD+EK+#_UMSlwv{UcEHuRzg%0!5vg;$}NV z4FW}t0!0;pq9%c&LZGO#Kv5}BR2AxqKCe{nPC#mB=jRuF5sG%pkAO5cmDyKT)TOC- zYxPjn)%j4=Zik|p9f~^aP}I#1McwUC)WZ%%J?&65n;nXJ*%Zw#P&9`?(VPNBy#P6fJFsqGjw*w5%P9ma{|A@-{^)2o$X-P_&Xj(aHivs|XYg7bsd)plCILqSXb8 z)(|LKQ=n)qfugkqiq;V*T34WGJ%OV21&THhC>kM9w4p%JMgm0}3w1?9nkuU$AhoCS z^R5>QMJwmANmH49Wkp*w6}zkxibgsging>v(I`6jU9@%wL{T%b|~83 z4n;fI6zwQbw39&5&H_cd2o&uqP_&ys(P)99-35yF5GdMHplC0FqP+!*_7N!BSD*gP*HxEUpWJL!zmDyKTbZAp? z-Fl&DqVu8XFgp|-Zik{H>`-*19g2>!L($Q8C_2UtMaSBq=s26A;{}RN5GXoPpy(ul zqLT%RP7x?NRiNlJfuhp|ip~%yI#ZzNEPoi4n>#Sq38-b z6kTbDqO0ssbhRCduCYVWwRR}F&Zg*kfub7(if$Arx=EnuW`Uwx1d47ID7sCc=yrjk zI|PdE6ezk&py+OaqI(32?iDDyPoU_2fuaWliXIdwdPtz?VS%DYgu0?>O_kY3Bt?6) zCpZ^}qLcG8W*==Tv#+e^$);kdjY82=&WEC>?NIcL9g3c{L(y|~D03lzN~Q1q%m(Q5)luL~5tAy70!py*A3qPGN!-WDi&N1*6kfui>WiryC} z`aq!QLxG}?1d2WuDEdU8=u?5B&jgA-7wU>0Z>nsafYj#7-^88>MOU|_@kLXaePu;o zHx&~%2}QG<4@KYDq3ByX6n$rhqVMfc^n)FWezZf;Pj)E!*$zd&*cAOLQ1qKX(eDC9 ze+U%)DNyv6K+)dh$Kv92z zqIm_11_%_*Cr~uMK+!;fq6Gws78EF2NT6t8fucbIMS}&377-{~RG?^xP*>EosC=1# z)LzO@OlvRdxAYg!cVsVCl-XBSv_w%fj|@diIvkxI6s;vtw6;LeIs!%O3KXp; zP_({4(FOuVBLs>z6e!wAplD-(qD=&fHWet^OsFdwR#X;AKx#eHOY)1wL(w1k>9d;` zW%iX7jVg)}qe9VE&WEC{?NGFh9g4QKL(z72DB9i*MLXD`Xh%B~?PQ0doo$MC5h&VK zplCONqR|3Hy9*TUAyBlZK+#?TMSBYr?ITdMuRzg$0!3p4iuM;M8Y@tAfI!iK0!0T2 z6pa%oI#{4+yg<?WU^7 zm3tGA+L`%z*N26oEjrS;xG1x)tmyKhcxT&CbcOSw=t?^jU1f)&tL;#9jU9@vwL{T$ zb||{u4n;TEq3A}NqMHPYZWbuIMWEE9u_EiM4;$VfuhF*iXIp0iY_fGowiGg9>`yQE(=9t^CKWn z6lM066+KfF{dNdN&pIE9p0h*I^L8kD!45^!?NIch9g1GEL($82D0;;XMX%Zvy(Uof zx`*kj9g60#L(!ae zDC%v8qPgr))W@c1Zh@kC1d93!6!jA*>Mu|`=6_9g0@5L(y=XqE!Wo zRud>%U7% ztvXk>O+ae%q^;xy-(@qN6$&hwl}Nj&?p29b<>0W9?9MoE?gew?okh zb|^a04n-%~q3C2g6rEyIbgDqnX#z#33lyCpP;{n1(OCjTlLU&+7ATr5P&7rL=p2Ef za|Mdd6DT@gpy&dDqNxH!7YYpy*`zIy)3yZ-=5A>`-*09g1$UL($E4D7wX_ z=vINE+XRYk7bvN(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1%l|a!rfua_HqE>;THi4op0!3W~irNK=Y63+aLS4~!oht_=AhoOV z<7nT9q8IW@9J`fe_LUXQRu<as1ABtwTL(v>|D4Np_MZN7%G?yKU`q-gpZaWms zV~3)?Hbwmeiuwx_%_~qeK%i(ofui{ZiUtZ4Eg(>|pg_?=0!0f86b%w68Z1z>h(OVz z0!2dviWUw6Q?ZCIUs93KVT7P_(%~(G~(lBL#}K z6et=cP_&g$SF}u7X*@V78kN5mEgOnX$xp)Gx-7G=tZ4hPn0G=b+QIoyw4)u0cCtg! z&UPr;#STTg+M#GSI~0w!L(%SbDB8oOXitHny#$K(7AV?BplDx#qWuJl#t0PcFHkgA zpy&XBq5}nr4iYFDCs1^-K+$-Cq6q>;hX@oMDo`|0py)7xqQeD>ju7gKwk<1bB_OpT zKLER3D4NnYjU&r4`^t)rEsNa`4MoQ}ABv8*L(vI#C_2#&MJL&z=wv$-onnWgQ|(Z6 znjMNxw<$V9py*72qO$~wCJ7XsEl@OBplFIf(K!M|=L!^^Cs1_0K+y#PMNKO&E`g%E z1&ZzwD7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRG{cFfuhF+ik=WCdQzb1DS@J= z1&W>#D0)_?E4sR@yq18}md(%Jza|vDpYJbvt}L^!tmwtE_~nRD^pf+T=w&+;y<&%= zSM5;rnjMN>w?okzb|{)*hoU#_Q1q5f(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$kwDSM z0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2R(M*A&uLX)`2^4)JQ1q=p(RV^!(Fm(?iiF`KkQhmu2>q75!Wm%N-qxesMk&{c4Az-|SHIyB&)DutU+Gb}0JG4n=?4 zq39nw6#Z*c^q)Xcr)u2frl>)ns8OJ(B2d&MP*eyMbrvWp1&XQyMa=?5EdoWY0!3{C zMO_4nx(XDv3l!A^iaG>}x(O6@7bxl>)D`_$R<=(-YJ1F{;QSPdUdoDkR?F-wE1IKP z9C>Ugn$!7E)Y}e4bJ?M&j~$BUwnNc8b|~s=hoXLVDC%#AqIqqK1_%_*Cr~uMK+!;f zq6Gws78EF2NT6t8fucbIMS}&377-{~RG?^xK+$3XMMDLOh6xlcE>N_DK+%!{MN0`3 zEiF*Aj8Iq9t6I4-0jc#Ikl@T-t>4n0oL@<_Y_-h3vZ58M#Z$+JqLrKvMJwB(XcapY z4Yxzls&*(^%??GY+o5O;I~1*HhoZG?iq;k=T1TL0U4f$Y1d7%dDB3`vXoNt~h5|(! z2^4KCP_&6a(WU}Ln+X(cE>N_EK+#BnqAdlAMhO&cB~Y}rK+!e=McWE>Max$!vl5V6 zQ@*9YLMS@4XByj8%j_#F+NoM}IVlwF?0hKN#STTg+M#GSI~0w!L(%SbDB8mgMSI$z zXfHby?QK)Ek3iAB0!8}?6paxm+Fzh(tU%EL0!0T36dfc`G)|!CV1c6X0!0%9iVhJd zI#i%&qCnAM0!4=l6dfT@bfiGhQ36Fr3w1?1R4YRhklHzOCOA8WqCT0_G1W5r%8E{? z7Mq+BicWMs6rE&;qLb}Vbc!8{PPIePX?7?&-3~=(*rDi5I~1K|Q#47S=xl+a$pS@F z1d7fPC^}c5=sba<^97175Ga}|P;{X{(M1A9(*%kx7AU$zpy*P8qRRw|E*B`eLZIkM zfugGfimn#wijJ#R4o*O7!}HzM$A_Z+`B!3HQ!TTvtmuYnao%a6=tk#5(M@(Jy4emz zx7eZRRy!2kW{0BN?ND@w9g6O>L(yF}MRyAn-6K$RuRzg#0!8-=6g?nN^q@e|Ljpw) z3lu#fQ1qxk(PIKdj|&t%AyD+BK+#hIMNbP9JtI)`tU%Fo0!7aY6ultS6`*kr4n=R;q3A6;6uoVS zqIc|2^sY_Odjdu83lx1IQ1qcd(MJMB9}5(HB2e_HK+$IcMV|{4eIZcvr9jbF0!1?g zioO;onk7*5jX=@20!7~m6n!sH^n*ark3wD1OVvu#nMu)6`FYnbhoV*UQ`UZ}mf2TU z^jo!$tw7Os0!7;k6zw3?6|K}MMnq}9Vt+Blt9tZ z0!7CN6dfy2bevFEv~zQ1uJezkR|*teB~Wy=K+!b`vr;~5GZ<3py(liqK5^F9uX*dRG{cFfuhF+ik=WCdQzb1 zDS@J=1&W>#D0)_)=sAI+=LL#h5Ga~1Q1qfe(Mv*I(T&ZOs}qpg1^M?E-4u!*$%m-C_M zZ#xwIV~3)D?NIce9f~@Yzw)L@6AMmrQ$>`>HXQ&b2PbrvWp1&XQyMa=?5EdoWY z0!3{CMO_4nx(XDv3l!A^iaG>}x(O6@7bxl>P}EbPXf}bOUIIn43lz;EP&B7dSM+;x zW$^^0)+gW5_(v$3n12mT@0K$A%8KS`DK@(z6!mpJ6!o)1QGYuW&1;9E0d^>w&kjZN z+o5Qn9f}sPL(zgZMGFZOEi6zpNT6u2K+z%sMT-g)4G}0>OrU6}K+!OPqQwP@mJldf zQlMxlfuf}aik1;5T2`QFIf0_(1&US>C|XgVXeFVps835}LIP4dA;X!wrG86)SX&w^ zx0KmeRhoXJ$P_&;NipJQXXn#8tjkPH{K%nSAfue&1ipB{P9V}2ZUZ7}# zK+z!rMTZI$O%y0POrYp+fubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vm69kG*6zYn0 zYpHa;HYpmP9|0L1ik8f;0XeCq%)YXs(^`sw*N39hoexE4*rDi5I~1K|hoVV#C_38? zMU(ANG{p`@=h&g>T$`fv1d7fVD7rwPXsSTbg#twv2^38eD7sjn=n{dVO9hH96DYb| zpy&#LqALZ8t`aD^TA=6}fud^#imnqVx?Z5@27#g*g}S0sS}N-$Ahn~qCOD^tqKop& zt#4{6v#+e^ww7Y=8$;3U&WEBq>`-*49g6O5d+OM^g*;iKdW=nC~&7tTm z=R?ukb|`ws4n^qM zyFgJ7fuf!QMY9PM^%5wWU7%fc(dbVn$f*ZEL1zz#+8*`a8DI}{DHL(u|uC|b}CMGM)XXkj}P4YDa3 zEKszFK+&QCMMDIN7858MDo`{`plES{q9p{1mJ}#jN}y$mjZ%D>EL)z&im%8J%(Esnh_ z6s_faC|cVNMeEq1Xk9xLt!Ia#_3co!fgOrQ*r8}cI}~kXQ?#)_(Ix^#n+g zijEX0I!d7EXn~?*1d5IoC^}A{=y-vm69kG*6ev1Lpy*_QqEm#rqCHwG-zOlooAN8H z_Y6g^q<>bN+FE8`S<#uTMaTW2=q%?$(Ih(*oo$Dr$#y83Vuzx0>`-*B9g5DgL(%zm zD7wI=XsSTbg#twv2^38eD7sjn=n{dVO9hH96DYb|py&#LqALZ8t`aD^TA=6}fud^# zimnqVx?Z5@27#g*1&VGGD7smo=oX=_==9dgk_kv{jr_dpGeXhr`RAfrTg&V#E4s6_ z*y6!ZbeHp?=x#d{-D8KMd+ktkpB;+sw?okbb|`w#4n+^yq3B_oqDKUZ9u+8hOrYp- zfubh_ik=iGdP<<^X@R0=1d5&&D0)ty=y`#n7X*r?3lzO5Q1p^O(aQowuLu;qDp2&A zK+)?0MQ;doMYp$B4oyI6Z|9f8-Vur}&tI5kw3gXdR`gD5apA+E=w0VS(R+3%dfyI3 zAK0PjLpv0GWQU@U?NIcI9g04+L(yk8MV|{4eIZcvr9jbF0!1?gioO;onk7*5jX=@2 z0!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqUzX=rmE>QG`K+&H9MSlr(MQ^oM9!)@M zN9Vh%-ws7f&7H>It!4I=6?JMWK6x}0HMGSo`B2nohoXudikj?DRM?@YvmJ^`I}}yz zP}FRPq86K?R)L~6fub$~MO_7o+69Vg0!1AHMco97x(gKb5Gd*?P&AuBQ7?g_*#(N` z5Ga~cps2S%(Od#WeFTc;7ATrWps24G*`aA=)X|(MOM_Wt<1i%qWRj2 z1)m5-^E)4k2HK%$0Xq~eXosSO>`=6@9f}6op=hujiWad$(V{j*Lj;Nz6DS%gP&7=S zXmNp}B?O9=6ewCsplE4Ox)7yls^Y5|G+$`8UrDXsh4SKOsLfyGC1?ePu=Kv=#e46^hn%J`}BIhobfE zP_%&^ibmL>XhS;`ZDfa{jqOmhi5-eIwJF+6plEY}qAdi9MhX;dDNr;@plB%g3l!}k)D^AORyjKX zscn<*B3e5X{hWV+$ewLw_LUXw+g9B1OeosV`A{^*4n_Ohp=hifiVm-)1 zWa>4tMq+7Df&4-?|M=wdOklidq-QDePu=Wv=ysN4@LJnAByg? zL(%6exO2s4Kdw zt+HzZQX86oO~~D$s3kw~@$I%U`^t*mZ!3;}DHMI+d?@p`az)RM}eZB1d4tZ zDEdX9=vRTF-vo+&7byBepy*G5qQ3-+{uU_uN1*6mp|0rNw#xMhNbTtSF#da?=$7tj z{MS}yUs+M5OYuUwKfBxTA)Sh*F8}|Qeqo2A&UPp&?NC&;Ls7FGidyVY)M|&KHaiq` zu_@{*P}D9^R1+xb5Gd*1UZoB~C?1&ZbpDC#3n zG`B#}JOV|11&aC!6!jM3PP&C*MMT^*>Xi+;94Y5PfVs`=719g4QFDH`?T$9g3c?L(!8qMNbJ7JuOi5j6l(|0!7aW6g@9c^nyUqbb+E5 z1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;Oq8S23ZweH>B~bLXK+!t_MehoAMfY~8Y?y%5 ze(aUt+!u;^r!T4SZuxpupWkm~jE&lm56b*7d6b-gR z(IR#zTGS3jL+ntrm>r6S+M#He9f}sWL(vj8MN0}4EhSL2v_R1^0!7OT6fGxEw7fvk z3Iatd3KXp*P_(i@(JBH(!v%^~6)0LwplEf0qBR7H))XjOOQ2|NfueN;iq;kCiWclz z>Hk?$G%G)JwooW~B0n6mUe_}F%8EAZTCDm-DB8&RP_(ffiZ-!B(WZ7N+RP3`o7dKq38)a z6g_E&qNnUo^t2s{p0O!1f=#{e%|$ip=f+1 zjSst)*;iKdY1d+_??cgN&WEDU?NIcE9g4oRL(x}uD4J=9qOa{xG|LV}-`Jt(TbrWq z1d6^FDEdL5=tqH~p9G427AX2fpy*eDqTd9HeitbEL!jtSfug?zivAWT`bVJXUxA|k z1d2Mf$IW(%8U%_O1&S&HMNL9o(Z^jYMj*ikjPtOMVPR zEzXCcRy!26*`cV59g4czp{U&sMKwDVb=aY(n;nX}+Z6Q>DC#LtG@C$CFM*=j1&Zbn zD4J8CsJB4TTmnUX1d8SsD4Iv0sINd#KY^nD0!8x*6b%q4nopo;eu1Ka0!0f56fG#! z6_xFkClip`_xbMXYJ2^b{w4VtvkSGC*;iJyNPF?c&!K2h=R?sDI}|NuhoYf&C>mym zqQ&h{w1gdsmb63BQg$d>+NNk3fudyvik1^7T3(=N1%aX!1&US@C|X&dXcd8?;Q~dg z3KXp-P_(*0(Ha6pYYG&tB~Y}sK+!q^Me7O_ttU{lzCh6iLS50I_Db6?Nzo2j(cnF3e|}=x#-Zr$tmuIDGW*Jk4sI{T{t=4C zJ0FTB*rDhUI}{yihoXsgC_2mzMTgs==mXLju$98 zL7?bFfufTHicS_NIz^!9RDq(?1d2`(;*;iI{VS91UU!mwC=R?snI}}}PhoVdDP;{vs ziY~K5(dBk1y21`cSK6WIDx0FK1&Xc_D7sdl=sJO->jjE#5GcA)py(!nqMHSZZV@QD zRiNlLfuh?5itZ37x>KO&E`g%E1&ZzwD7sgm=stm>`vr;~5bBC9Xs^7VfYgSjSxgN@ z1M{P?54M-tS61|Bd-2~tq3AK^L($`QD0;#UMNitH=qWoCJ#B}gXY5e)tR0G;vqRDI zHbpN86ipW>dQqV0C4r)s1&Uq~D0)?(=rw_&*9D5+5Ga}6t(3iracmhPR`FS`lP+gzOte(+KbgY z<-Z_3@A^yUL(x}uD4J=9qOa{xG|LV}-`Jt(TRRkeXNRKi?NIcCP0^16ML!7?{VY)Q zi$Kw@0!666ryeu-kY;X{|` zR5S<_H3}3}1d5sjiVA_E&H_cHP*?O>du5LVr1oI`@5X)}ivG*r-m0}S`^t*iYQ@Qo zp{R@Vp{T1JirVc^RI@`-haHN#*`cVr9g2F`p{S=Fie|GZ>LpM#yFk$#0!4EQ6!jJ; znoFRlk3iAf0!8x(6!jG->L*atU!Z7SfuaEdMe_+1%`Z?iP@rf5fuaQkiWU+mT3DcH zkWg3DQmfpYfYjE>KMJ+h>bLYC$q&sAu9ewWR%^ePu+M#GWI}~ki zQ?!FX(T)N|I|&r+EKszIK+&!OMY{kSBw7)>nSb?Gg1d0w6C^|@}E84VHSv~=&os^$3yICk&D&OoMS1Yrxtmu$hu}yO* zI@I}4G|>)4huNX%a61$oVTYn4?ND@-9g2>&L(wsIC_2`r=s1C*;{}RN5GXoPpy(ul zqLT%RP7x?NRiNlJfuhp|ip~%yI#ZzNEP?=&8j3D)J``PQhoZ~uP;|K+imtFj z(Uo>6y2=hkSKFcJ8aotSYg2TcK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellY?E*!2 z2o&8ZP;{3-(cJB~bLXK+!t_Mehm}y(dugzCh6j z0!1GR6n!L6^szwECjv#E3KV@N)D=Bet90#}6fK+YB6>U&rQe>GZm`wL>?`b#WQU@kZHj&oDEd{P=r@6)-vx^P z5GeXnpy)4wqQ3=-{t+npSD@%Wfuc?wakHJG27#hRfuf2)QIkMXAyCv=pr{lmstOb} z3ly~obwyv+Dw`%CwLbaT`(K5kySt>(+EHd-Sy6jOabUMlRC7KQb=aY(n;nX}+o7n3 z9g2F|p=dTc6!o%0(d>38n!~1OPJyD{0!4EP6!j4(np>b~9)Y610!94|pg_?=0!0f86b%w68Z1z>h(OVzLS0dpj>`E7NUd-F56E=w zsNd4RIp6Czq@&EfvZBR1iu-zmq9vRUMN8VDXem1sEp3OQW$aM2tR0G$vqRDHb|_lG z4n-^46s;ssw6Z|aDgs5r1&US`C|XURXmx?2H3W**6ewCtplEG@qICp{))gpPPoQXh zfuaoribe<&Z75K*kwDSL0!5n$6m2Th6%FmEe3*dL?#?&vhlQg3^8@^wb(GmxRjU9@%wL{T%b|~834n;fIp=d`t6zybFw6j3bE&@fn3KZ=o zP&8VgXm^34Jp_vO6e!wDplEM_qJ0F4_7y1FPoQXwK+*mJMPmhu4iG3hP@w1_fueB& zMF$HMjTh>Qw&>S<%xS z#jAZn(KF76qG#<;^qd`vp0`8M3w9`)Zik{5?NIcR9g1GIL(wZXMXw4Jy(Uofxh$Kv92zqIm_11_%_*Cr~uMK+!;fq6Gws78EF2NT6t8 zfucbIMS}&377-{~RG?^xK+$3XMMH(UqFT4gF$qZR$$Yb{qg(x!{zVB-F|1peePu;U zbt|qI5Q>&|J`^ouhoWWeP_&#Kik7!S(F%4bTG0+gE7_rFWjhqDVpB9+plDTrqSXY7 zRu?E*L!f9)fugkpiq;k=T1TL0U4f$Y1d7%dDB3`vXoNt~h5|(!2^4KCP_&6a(WU}L zn+X(cE>N_EP*=1>x5~2#NUbA3=&@udy8eGR*t(V3S5~xjx8m#hL(w+QhoWumP_&&L zing~y(GGSf+R+Y0JK3RVXFC+_Vuzw#ZHjgiC>kwLw7Wpj9s)&s3KZ=nP_(x|(LMr2 z`wA58Cr~s-plE-AqOk%+2M81$C{T2eK+!mXqJssB#tRfp5GXoCpy*Jcu4q)ZN^M|L zbVq(-+E$_Hi~Op_iQUTVD=Rv(Td~-Jq39^*L($Q8C_2UtMaSBq=r}tR9dC!C6YNlQ zq8*A(vP03yHbtih6rCzibecfX=>kP(2o#+uP;{0+(IkPQvjvJK3lvQeC^|===>Ld& z59lcB_J4aOo5^nI1d`ARML~rWItofE2?avVA1g@p@||$yQ?L7E6t*Is??P!VfD-D=p=Z3lCK!x zI;jKYs@qAekguanOkFJRl0;J1$%(L4>Rs*SGq`iQ*UlAY@9?KneHOZz*{h}3iTb(~SDZwzppF{$0N z9H$_4MvmhYr*0bTIAy8d4t1Q$)S)9BrzZ92{T*j=>Z79^=aAI!L5?#mb$qVl%uHRE z?>KW(-zs#Rd8s{%9cNK${W!;2l6pg#<19=4zT9z+NgY1HaaN`tTkSY&Qn%DP&MB$M zlO5-b)QYK&vo`hoLmcP4)OQYZob{=_>Ktc7>g*YgvoZCiddIms^~c$cbA9T_!yV_w z)Z^zl&aJ6WEO4AVQ(G=}oO@FzG&;_MsTVGFoXx549pyNWr}kOlI8UX{J;rgKO}*tf z$9XaJr^R#~Tc74QpQKiw;W%HUUUZh@>`eV&t>b)` zy4O0#*_C?4`Hr(Y^|lKg=Z~~sE|UIt(?)O5kI1I2zD%}&o3?GEYyvl}?Nzc3+_c(j zWFxp~ms}@X!A<*clWYbzt>2BZ9o#hi-|YLkY5L!h_jl9u|C1izrs;nOob9IR|L8iz zP1FC9bA+3w|EJ<8H%!#^vE+2H$^h0x- z-8B8w)8lTMer)9_H%&ix@T{ArZydkqrs+F>uexda*3Fx4nm&7f*G2K#v`R)9%+)leg+ng=K`c$}u{C0Vujj&-pbGkgH zVYr3IWv_Nev=Mh@w5Mb(+>!Rm@ACIz?*0}g$`0=yVBt^=qbzLIW{tM6t+#{&EhNf? zk9&}X8|Ap+jtN57Q)FSG^wUaPCWxTs?{w<@Xq?dwn2bWAt5 zI;s8lKkvNZIH&8=HqD4&nxytW-Lzx%asEW_Kk{~#Khev7ZG8B6f1+(CzIvKWR4FU3 z3!2YFFK%9Uii{ykYIV*fiT*^t-~aBpG9Ovewl80~SSGq&Cd!wIE~j-_Cm&VgPqTID zSedxWYqhxj#U(O{*DCYzbuFE)RkEhKn3tL2V{chYnIftExlg}$q0C$+8C!Z&Pk)l+ zw|-4>y5235RLUet@~d6Y{*R~bo#RjP;HEpyU*@;$&UKI6w_Uot*4Js-@<2h36H0SJZT4?@K+BOWOFGEm$zIV% z#zP$?Nr`T#&4Ddj%FDrMuE21AnW~$dPa^(+=Qzp!fXLFqX6OYoY}r;8rSoak!EM>H zX%4MhJD~{6ZP~JQ%T_H%$o$%*Hyf+1j1||qb{1{k?QND4wNWWHOaIlTS$42l+E^WB zBCn|(sjX!#b;)V|fUHS+rh8ClmfEj#Nr(1sO46847v^==g>>@bT9lA}Po8vV=OO=O zUE-PcRM%5aaAi~EbkMnUJM9G5N$7M=p6oW=c|kU5rgKo|QJojG@fR-*mYt&MXMY)V zok}fl>b~bp(V~Z+MCV7h^75uJK`M?R`5rw))LHia{O$o|78koL4tFR-zFVbhnXh9IaX#A{OC*mdizli zh6zr#-~M6#RN0qn9U;G-Gp5n$cDWAvUpnI)r14&f+H#%BX6bbE=b}lz5W;?RocN#k zTq!$7$azKPl;Hl}rnTeBkBlq7Zf0gyLtWOa#zk3;4KuPDqKz}^ql+3AE~%ffq<&`B zjE3clmMl~-qkiVnhWf_1*K~Xtdt}z4hPm_SE}45|y^}R(;r#lnx_R}>vNGo_oKZI~ zt8q?ULw#05{et?&y2h;fLD9w~OJ~kqn6+f#!g(|1)XiPcm^FLGjA&iM{H&bp=-}v} z>_IuvoNR>y1rA)Wa6$dR`nu_J2j*mF4j!m4XUfaXUdo!gV8*8 zmM^Mr%$y@KJ7U7jxeJy^5OKx7=!}K)=Pz6kty?r#n0Q^CUl^5MnUU{vVRDqi&$+s+ z0Lfo%$+w@X`JutC=XLmRKc1Tun(cZWLY*@`H#9plHk9F|gt}x1o0Xv~!}F4|yp$xF zS5mfJIKf>{bd=;bYhlKYRejJ)z3LO zUI!T=v^=ggeZ7=!annsn>L@MO1v95!%p%LvMd=GYq((BlE9 z(%^J`#k{vo*{t(NdF~LebyDc;<1@XkGD&L@s*7Jo`*k0G=B=4Uhrot?Z2S2!Qznw; zC8cG1{X;7@L8Bj8yUrrmRl94S2ZOD%yzV{ylpMP6 z_;IuUw;MjgYd1&^k}KVe%!Eq0f+(u4j22c^MN7&j=9ZNdM02ag){ZYMuW@)`d|`EU z?%2X;O+`httfG9ZQ&l)Nnv|)wPwC75YN7vSe~$S+uC4YJ6@@utb?v^U?FlD)LLC z1-Ui3(em2yd4*NF9u-x=*n>yJFSxuST3wr0onKX=qZL)umKXS=4IfeL*OASdSyfnF zSs^V9<}^gcp)a)Ug;lxLaV@9c##fJx=G7Jz$^5HJrWVE~`Nx`-jMv`u$I+h5%Z_ho zNqMxE1&_4Gwa#>llvZAECrqEV-kd2=!RnEwR2Su0oYf#W^^1L!R z9ak0ko1w5gS7L!vQB)nxEeK{a)E`@0Rus45g*CsM>c-hMNxiuvfGDFc)i!a^b^Oqd0s4Ogxy@u&|RV8DKYs#g=qt%5qHM*;_=%W0x zQop%_hXgy;P=AU3!m~mCzV?6feudke;5yY`nCv?y$p~9)j%>GBJ4;HcigKfc`T5bD zyb?RU6eun+5AB%4o!gp>xN_MkuM2 zqo~PKDaWz+1G&FS)#6y}=sd_@W$m!MxX#f{-?V7II}74omQ5^O5-psZUszZW*JSGu zIkea0%Au*Wa7wf&w?q#w*kNPnjw4O0sI8I#*}03#O7fddH@^RR6peLV&Y;+lMUF8} z#nL4ObxZ1^HTBDa<6Dj#1!gXtKYw{_LH=G>SW(h^=cO5PG8kV`rQ1f2*1?fvkiQ?! zTex6$h8#M5Hbj=?uY8USFs*cGbw$(3Qcpgy*X-zDRajQ&pCNSO!sb#1n_W9VwrojJ z&_lsehQ+O#u3uA+_{T!sZhF-9&#>0!W=e6SiRR|#*H-1`+hH}zk9$B38!`Ee^*DVwjlDqj@K&95n$7@P-(#hrdR637L^*mD13!SATSGKvo5Hap?O zAC8)iqB(`JjjDsOW|||Sg&bIF?G!A{Y#Kopnpc%8mlX5s{N5#9#VMeyqT2TF z5wQizMhSW_kAXse^Eb|&y`X+(hCI(`h%HW4uPBn)i84*6ji#eRett!?SdNFW3Fw>g z6$L@-Vt!#+S#4QvmH0olq*_$h(SDQG z3dWQp9ml-5MUF3&qnKStu_T>ejvShU=?Z<1mM(~2eH}wiIkAQp3@WhGbX8$_fw&uY z(2s54eE)*XoMCNB%E}7I=9bysCYKonvhO#YXMMS2=e)R0nlqxA-sVNI%qi|FuYh%s zExCsPC3+a#;{X(Y6(dIhfA97CBDNdk3~e?e_7zqp?t-G3CI5Q9Y?7p`pu#_(#!e!( zL4*F6)ElhqXiRcq6Njll|l2%h+%Q#+aYSa9E57C{L_+u7%Y+w zsVm^fUP)QW)TYbzY&quY zECx3_ayISey8Fat)MT=pTI2vwBbTyz_KuCfR`hSlnl`TNWBGC|ke4g>X?6tFWy&o^ z(EQ;|=F2%gV9oD`^ln8j5lZBCB)FIe*4vkFZrQ?xi*g*l4Eje~nw^`QU0IKpIptMM z{>K#gWpc2W)2AMv{JseesQ#6{ZoQoBLDufrkybW9Y&K23q}Odx>#AT1IVJi7vUvj_ zN3OWt$KTFPH->v$(A%-E`FUZ8%&9)A4_xaT8iIMsed50~CO9g~o~*43E=F_Ye%GI* z`CYP}RGO~3CL#0p2<}mRlpPx@7~C^Wl7X-+;w|!Cz%_Yn;i9- zv0m5MGUSrghH~WkKGwdt9;mFUC@zsZK-m=Ka&D7H87$IQL>r=-l*l#bRFNSXmA8MI z9<1cZMYAlxziWuyIxqu0a>XkKN0g%60(lCw$642xK$kjJT#sFzG~NH`eVA{g+%2$b z(hIRxbJZI!y+3}w-&M3h+qTDvI=5P%$i*J!$UYRCY3z4!g{1X54Qkg4f7k?}{M+5`1f66Me3Up(BvE0uVmieQ| z?QHDz*#1&9DOxMf%cL`HhBiNWT1F4bfx`y%Cd^vdG$*-9uh!#Ylb1Tmzh0iws%B3B zn_U*iF0;AK4DN$iE$h{K3i?Ctw&MCjPjGt65v`t7QX{X#oh`X7%W1mZ z&ygdu(>O=2iek6BdK2a^Ku*B^fZlW|2=0yim*RFPxlV5CA$|VqKP%BI4tYKh9h+Mc zJQWo0Vx!SHa{XUh)^u^9x^sOJe|Z{vL^Fs-G+KzHkorkA2!iy<1|G_^W++ z=30_3#}GND*ZBPu8>?FGN#%~-?%L_MxOc$+Z@uqZP(OX?Y`;hK&WlFsu9%w_xD`B? z<`vekNN%X)-ZNTMmRsF49k13_s@Zx|&m;FeZiQmoCch}ZX}jd;lW&$}4=#dpq`#qq z$M!lH|Mc6xSKH&b(R9UFQ21Z28Fd3sDGY8>xnYwVmObR~Weu%cck2Ir8)?zBNrxX>?_SouJvlCwBL(bBuLk zyl=5PTI*Z?8MMDxj^O?xgNDQg^)}8&`uLPq`zKr3_Tp{6>}LP|c1Q4dxamyvkHbt3 z7yLQ;K$LmMH@T>!OfJacZ|s{cNvf;!?R}qS{eZm4C=W61N?~DeY3`Rn!5OkylW0Kf zFdgf#xC58o_Aw%h2t<#aIQ`y=e|YJO@Nehc;3yn>q{V#wcXQb5fx20%YJ($~9&h1x zbe3(}{P}3yeT+Oz@i(EIssE`IDv^ap|`r#i^ZN>2PENSmuZ2``deBL1mR z^P31RTKt(x=f>LQ?^kjzs>!X=t2}XE-T?h?`&Zn9QfqNe@RU<$8{8JLzVZm(E=v3h z2A;zE%a1$gnyA5>uCa%OvX_cBIxcrJysMWJJmd6dqmLB*f#3?5CF_B<`8g!Ed&Tb& zK}%#7{@xkukNmRS@s)8W;6M+3e@^Gy^iEXMHGIyH*pUnEbM&EM(6nYpirh-M)SfJN zxXlEPYhKU~!H&WD;J3;tZwc@D=+M91Dawt%mS74-)t1EF8pz4adN(-Y>&wA4Jd3Oh zE{x^DS*%}tPvm&u*khKa_Z>uDHdbu2#T(Xi{M4t!@$ci%&R~80{*u1*JFfYadebcA zJx(sHXe{?i)wR{~?vdTA{^QZ1J~iCqJpp;#CvQOnk2JEK_|$Y4CvTD4n@`$2y~&8( z`>=ey=Jd};|8}3L(x`RZJLz1CY#nptsZ*?f>5JewWZXOc!3DqHIq{c~{+-z*c^6mT z$F8t9W@%FJv|Hay+w+*N=PG^Qn`01fj51|jS#Ei$?74;VtZI*I99@+?M{n9NWfk&v znH)#tv1V?0+%qxVI?bPR1os)iWp}f)VVqg|{LWwHrpKSbbA8&`bivi^CPSAdJ4CIl zB~8`Y1UCu(5C_)a31c+Moh&nsJ5Co@mCCjYcF7X)py^TBq+GdK=8(F_l=_TDPmMu$ zH9e%%$9=I;W6z28wrp&b-URQ_+s$qSRWH9k^oE6*(6s#AeChb2sDEmAbn$$MfqNJg z&34iF8e$7e>Lohd*0=6v)i{ z(@%MB)5jEabMDbTIj_Xt!_zM2#L_g6V1rGns4BIq&e(-Pj$BYmKQO8sig+uc`OQ#~ zyqC;??W3>=>+cM0WAQv2}ue$A3yOZ(fR)G z_z^<-3D>xvkbb%~?kA)laE<#3$%k9zPZ;8U5*_&y7yrZK0c`qEx8_jnuX2J{Lyml! zJMJf>-*FQ66LOk=06*l&-}1!$gdF*Ui@2YVzw{;$a^$1_aX<3MesM|LlPZ6u=YM+K z|6qEGtk2-MG1|#+?jE^fkIV;ogHK-cUE=heX{VF_`pKC1vrY4JkKES9otJWSQETM4 zg{;O_t7Wo@G+(V%8ecA(Nb~JlQ{~U-vJ?V+uzH`>N31?!^%<)# zS(QJ6^XK!P)sL;pAG!JbTdO}=l|N$hx&C>8E?>W8S*!e!nqNCu)o;^L-qY${R`;`- zV|BRI(N^=VmRPN@T5I)St94dqTb*yU(du%m$6Gzo>giU`v3jA^ORZjIb(7Uwtlnky z0jrN%ebValR$sIFuGNpN?y&m3)!kO*pyl^dlKAEKqt%X9yISpSbswwQR)+ilt4CTr*6JFor&~SO>P1#JTD{Kd%~tQS`k>VP)LgSZ%PX z|4py9W2M!Tt)6A|e5)I*US;(^R&TR)WA!7eUt0an>MvIRvg*mH zLEG2LY6q)btoE|n-)ffCVOB?5EwEZ@waV%gtJAE`wz|OTQme;UU2XL=tLIoF>YY{}u=<$QZB}2j`i9l_t$u2Cr_~>={$|yczY)>?iCArGHO*>wt9`8wv^vb{ zK~{^cPOv)F>I|#%tS+^BoYj-9uC;oR)hn&uVD(O`4_V!6^#!YMTK&-K4y!*}{lls! zCoEmxHdfQEW?0?F>L9BJSS_$R-s(iFQLA&TF1EVD>T0WJSUunBWmd1VdaKp@tUhM- z8LO{aeb4G=R=>5n+p7G}O#b?{u-egTAFIRVT&?S$Z*_`X`e?4VdbFIQHJ@ztQn~ce zyvgb#a)Q_VjMWe2nn3f{R`-@aMAkgm>OA?&N6pKv-rgn1k67I;f0?JR%O42%^}wD% zEw!qDLanc#WA*7iL4Lz(yS;Cp;^Q}HF7hKxj zcdT}t9OPbBr%ny>Y^xg&3Gz)=KRYbQKUy777vzyv8)gLgc&qo;2l)xBf6WeZ%Q-kngejoqSJ+ zuJ4~#hrJ)Ly+&Y`h$EGh_?4{t0R61a-r4Zehu>JRv(ueEFJ$Pt1bQta=KOd!z%yv zL#FZfm=OhPtsnwh1OGfnd2dwUr8#&Exo1pG5Upu0C ztksqB{Ue&sw7ONktV8oFR$Iw8l4$O1wMuRTHAk(km+vUie2vxj<;zMme`U3AMv!x? z9^O01M_IkKZ;&6d`m=nYiB2Et7t~Sv1hvHKmGV77`uZ(a@7L-%&Nj=hYHcCUR;<2f z{0qxFt$uI(56jNLU^-8$%)g!Gj#fJx?`yfg)q%!GSRQ3H*LbsG7x zSbe~%9RB>*w_26MiJ#@L;ny8jzp?tW)!(e@ch+dXb+Rh@`dKvft7zlbY^w)YJ;>@f ztL0Yx{)~uMHh(Gp^l}^H*N+l{DvzX`gtoF=<4$Jd^7%{Zrb}JY5Y#yg$p@8}IGOs% zU?+2WW22KPpJmQem>E1C`>#*d{1IpBr%dG8{;Y*E4}Z9B`t*kSBZJulM847?KGrqV zEtp+z3kt^gCz+>T$Y67nmO7dGXa4o_r!sL%oz+k`Uq;HU8lPFWWJ$x^=}VW$Z2z}E zU1db+*4R_hA$v?HUFrYyl7Dr)P!OFx$J5vJr=R@FrujdPmo4M$x!m|K-Oz2RKLg}9 zS$@aJul^L*yN+C5J90}QPfmkhUEUP=r42IZ+$aq_O!hy17^)QzKfjeSzfQ74>ipCz zou|&PUVfQI2AvjzUFVTFz~E7PjJIuw>m0_5aj)qXiC^yeBjsydWISE2a+Z5i+%z)i z^c&_n89HD;%=!e$@$>uQDEVSIVLHE-^2_`#l3}KiL1(PYPsihj*UlFZKfm2^^V28b z%%aP% z{yt`v@t&IQI^%@#!+0+U&|!W$&Io)V>w4(VGx8hXzIM_+`mck$#`?Z1!=ln6DgIBH z%x`~!RFZR0r&b`RO?#e!L86-%du7 z%6PFa3z?g_Fe@V?BWHN_uo2mVMhqGz!`az6asLh*HpEXOv$JKyjA<>7FDxqxzRM<< zu`5sHnXi&jC;7<>_VxZwXE~A%{Bn22Bc-qGesDtScRjr^-~D~U+M>Ll6H;0gZP~ph z`+5LFNE4veWIs5+p_MCoqkGs1hZT^)3~j>ot*1SHx+N)y)*mz68U%g^`%>P zZ{Pe&-QU0b^|#ZfV%N%qAL_R5elh3Axswx|?;l-Nv1{t$jindJl!@(S%&Y!z-nywr|N~7bVCDV#^c+3ye zv!%tkhn9}j-gBi_+il(bc&rC=f9TMs*IezRI{)7*{C_|6|D90s*zT*_jV$Rft>v7{ z-9KKf*tL0*%x{>?Z%k?F;Bhb1Ju2;bboYzSqj7UA);S*T&(Z()3jf~^{eKUVIc{&) z*Pr8Md(5%;hr1ek{Fiy=={%3{=js1@h5zsNBLxlJ@cYBd{y6?4!EJ#jlU&P7%NEUNv^R(=KgH>n?3FbRUsDapm^2 z?rh_n;*8i-{Lp6~uH8Mf=FU%Fmpy*v_S2makGglVzlAv(fho(;K0)wc1&NgaoBYqy|!8A?`Guon$Ua9&ujW@pZ($N$7RoZeD~Ga zubStMzx4}$=+IvFmFnBaJuZFFYub$29p+pT^gv}|FLA8##!z%|2CY^N9Q_YcK@P>zSw>CoZc6guCEY-dg=c6hP5Nut2?FjnX_)(lQO?`rRz$b zl)ZXg@w(C{Wsm+VZjb)0?n&wK-~AqcWo7;kV<$}ReR}EYav8tflQLf!KYLHR*Oaaq zcVfwj&Fn7yVSCvL(vqEUXo%pTC}X!z#tNOr$H#%bk@DU~Cpd(gNsC1d=4nEja?uTz7qKDl@A(xmTK7U}l6 z_NU|b{4Kf$nbuep|Zz^pm%R z=Nv!z#Ee^=^GY`t?Yn5$(b2q$3oaZ|mAU?^l6&|0;^to#&wcE~*HUIh4jVjd*_JbY znf&3I3(g(#PVq^bcJ)6ggMCu>McpUcBqd%tZsFMdkDhwM$jSH3Dj2`&oik^)ICo7| zuThuIYSCiK9alU*e8PKcwhj7V)`goNJoM3#b=P0A;N7j4=QKRDzT;QV-;*L|*k|Pp zUcDZWV}yHPD|tU^ZfD22Pp^#PeiGcIqvX0O!Hq1DYlegb?^3y4Oh^cC?IjlmqkGHn z_)gG6slrJ3d6|D=qNjiSkdPQokr{ zS9O$e!goqTz3?k?y^<9ES%$-5y>f_zSIcm6_*NOeMOaSGPRsD=axc~@JT^lfl7_d+ z{cxM`Sv}-}Fq|X*whKQeW3~@RxJuTuL-;%yr(^h8xdKfM|0Lt2g&&bSmh|wT zK5|phtKwX+zKOCGu)U_+(jPukepD=icFu zWo~`Km&urY!;|GUey{MYGPjxGdD5x%;Sqi1yMV*Ra!2Rvtx;_(LELUXD zhWp6+J{NvL#(X~Vko3j?H}a7*YoHrBN5;x@BL_*3XStC!(wb~}O&Yk?jr=K7o#RHj zNmJIjk)x#V&T}I-NOzs@MxKy#fg8D2Hu8mTdN<<90xohRW%Am^ZltF)=@K_G zOx9|b8<{HQCpWUU81%Cn*&<8-#f=P?-rDU(zL)7H%XXIqJ(v)=TbleuC~}1~;>%EE zh1?eG2u0S*JiiJ>c1zkBirgyw@^vUuC7tn&ye7TzZ79-GR_wb_BqU4tJ`^dD<&`By zW=J26PmJgn;g%;xj+3olkr){uGpkIDw3N9_NQ}H7%d1L^d@ZFqG16O>P?H#GD-+Zv zMvBDIiHVV3vIQn3M!JY#lM^Gk;^maY$W1b{sfiK!Hcsc@#K>gXY= zBRYB!eG4hoi@Yk0Sms5>OD`?=BFklFE4;{~0^ju_*UCKK^CDfOBj1-XMYIpR$iA{U zwtJBsvJM~0DAG$Gd6AjYmKVd3H)PD0!jWAv`OD$R2wCha;mFUj$zKge-jgQ17LLr3 zo_IYRc~;;XGJ&koo8icVGWlEK$a&J-ds{}{mae<6W#lxO+5Ige-^dakXc?Iy+HPzc z`AaOgqHScUH2%uAksZ>ctJ+3>k(Iu>ZKQ|H^P0Aiw?(vT+eQ{kI;BG-SGMM<9U@oD zp(kqe{;m#0U*mC0A6M?R2Ed~|wbjkNQa^vDge4#%cP-j^f7ap{rg zWb)(FBlDyqSEff+$P!kiN6wZ;jM)&GDT~eB5P4l@mbW2tyL4;8hRF5|$0^(pX)7I4 zv>_r-Nu9A9A_dYDm0Kcz%4-w0L=KlSZAWCfETL{kq*R(aeMh8ToS3mA(pNfU=8njG zX;S@;$Z%PQSvw+$((2hel4r?li`u(R@-|tS#X9h_%(p=YHp*si)Pb$i!X-M8BpNQ& zfwQC=kJN!YnafJqq{;GSWX>ubSSIs1K?fRSXI!lVH};l~I_bb8vRzNqfvaWYlXT!E zY0JqvaJKZ?IZ+w-QP%ie9oS1+yG{qvr3=r~fiGme&)0!rvWVq!-I5_RBx=|)cn>ct894qqpEgdT@=AYDjA2R6yF zl6Bx7*$^#sV1UfIr4BqGOgmlz_Gi8-ibzqk)OIw}XLpGm0`gD?4N#hfAU~gH3eq=9smFz`{ zIv{q-TF8KY>LW=9Hp+VGSjkmln|wpG3`mD3=)i;0RGrRgagxj^ae*7!D7od?@=vyO zU8`ecpr@PzlUhr+wN6ytCehp58!axh&C7PYe)hj2^^}<7c>OK*kT}Tk_OaMq;$X+y z*J3w`LmY2Ei(MrSb-V!3G=|(@yNXxA? zOZ)b>+)DBwY2N{sTWXf}jk4TAv$Sut-~KE5G~ZBjF&!J-+`XweK=V$lp)YS9ci(xMr1ltnXSnME^XxkWQ% zg+&ZG+A@Y5V;Mt^wTvOhS;mm#En~<^%NVlCGKQRB8ADcE#*j6ZG2}$c7;=(j3^~~{ zhMZynF0e_>kP9uEA?q!gAs1ORLoT*xhFoIN4B24O47t>z8FHCL zGvsoM7_!kahFoD8L$0)pAy-+(kgF|Y$TgNR z4EbGvcXwFLQA6(co{)tkEn~=2mN8_TWej=RGKM^38AG16j3Lii#*pVNW5^4ZG2}(d z81j;340+iyhP+}KLteFvA+K4+kk>6^$Qzb1M~AwOEikX@EB z^b%dU5s^DCy_@k|o4TiDx$I3M_mC`?Z$#PlVhMXo@?`zruK9RTeWNGm%6+9{A`rUKe3kang4+9;5QrUP0lkd}4=v=X3q zIGq746-Zxp0klvcE$s?ORv<0y28bw-mUah(6-Y~a0Fo3)OM3!51=7+CK%xR^X)i!X zfwZ(YAVGlM>+}J*3Z$id0U}6hqL<)?Dn*c#^?HjFas!J7$fE{tFE^}usYUy^-eNiQ z_!jNU^k&h1WV2`h*(@4JHj6UJW>FT|EXpREMLA@%Xb{;f8cfEbApk5I3c#Xa04y2~ zz@iZVEE);GqWu9_bN~R0Mgg#BGysbZ1YprY04y2W6=}<7EJ|U(ZK*LIs|}4hXSzZFaQ=s z0a!E*fJJoxESe6$q8R`znhC(7dH@#90$|Z>02a*wV9{Iv799@2q9XuUG!KA9^8r}2 z01#MI=7!!CK~mPr(>iawS(GQ2INm}xtbVCQjjs2nJd5-#TEg^Z(NeNmbR^j1F+~602ZAJz@pOtSado7i_QRG(U|}&ItzeBX9KWkEdYzo0btR&04!Pu2rOFc zhI-4%EagtUaBeV*+Gse>4Xa;j(R$a*mm6~5qKlZ`EV`I%7F|L%i#CwWqD#qU(Pd<_ z=yI}Iw2^EUT|qXBt|Vj8RRAoy8h}OD0I=v<02W;bz@qB`ShNX%MgIX{(G37Bx)Fdy zHvzEdW&jr50>GkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO-2=d)djWw(7r3E0B1p=! zdR=s(S#+UVbe|hmztp0KT<=tQpT@W7VWu~W9wD1Wo5^O;qhzz_F|t{-g=`i*PBx34 zAe%*7$!5`$WGs3LfJNH?SoAaii=F{s(X#+7dJcd^&jYaN1ppSk2*9G309f=g0E=D$ zV9~1pEP4%qMXv*}=nViCy$Qggw*Xl5HUNv>0btR)04#bB5Lonp8@gEpNjY4_d64TO zd7I38-wmr@YSBlo_kz5?Yxn?+xd z&7z%TEczONMc)9h=vx35eFwmz?*Ul!0|1MD1YprF02ciOz@nc4So8}3i*^IB=vM$1 z{RY6I-vL@GjJM{@yKlmG}U+U|z*V+1Mt>cheh&7#xv z{i#qwSp8Cq!UCK{KvRTxEY!IUhS=5GX7PTdtMeWFDQF}5L zr2w#~0|1LU0MZ5c>pZR2VhYF0E-F%SX2bSqOkxh zDh6Ot2>^@60kEhPfJJ41z@mKbZ=mLG`Vthha{Zfl2BzRZsYZg^8 zy;)REHj8S=W>GEKESg9*izboHqRC{lXbRaZno2f{4klyKApk5o6o5sC0k9|vz@ljY zEUE)w(R2V7%>ZE0OaKpY$55S@Y04!Pv zz@kL}ELsc*EUHKdZ52UMR>=p2yh^huLr-rF31Rh1Ejlv6`&|A&%fBu@G>MOTu|qN~Ve(bZ(L=o&H>T?@dX>i}4EJphX~0kG&l04%xzfJHX~u;?ZL z7TpZMqFVr1bSnUhZUbP^?Eoyg1As+$0V02bX1z@mEqSadG{i|zwp(ft4{dH@hu zbWuX6N(4#yOCMKXY!MV}^k_YF3SK4W^b=yS4J^aa^0`jTuG?I4>)Uy;qC zon*7H{Q|(E-2g256@W#* z0kG(I02ciLz@k3^So9YFi~a^+krT4pb}VuMSd;+3q7VR!5&>A`0RoFYP6)j(f}|WO z?{IjZm_>hSND773FSV#e$oqS!S=5s0&7xLhv#2%MENVkGi`tUSqIP7ns6E*%N+Fv? z9mr-;M=}H@%`t^h3R2Ed~304(YOz@nZ2EXn|2Q7-@% z^#)*39{?8h1z^!$04&-YfJOZPSkxbYMf(7-XkS2JQ6v=VJ50}L`iLkw6x`{zN|3N$ zD6D>|MOh)QaD-Wu&Gcqb4%sXkL^g{Clg*+bWV2`}*(@4HHj9Rn&7u)xvuGq4i}nX# z(E$J~8U?_j(Euzu5P(Go0kCKc0E=<~Sd<6AqI>`r6#%fP5P(HR04y2{z@lOR7L@?7 zXdD2GN@2Ed~604yp8U{M7iuxMZ?bhrqTGE5IYnP$@+(QE(~%>iK1TmTjw4#1)#09Z5+fJO5GShN6uMGFB~v9ZxokR+7!4Rb;d11hQGQnv6wj09bS)0EiSadD`i`D_K=sW-xoe#jG3jkPjApnck1F+~K zKw!~Pq0rAFNXou?LA}f@Dp!jx4u#b(wdk^tmwu30bUD+TMH|Ux(G_H~=t{C#bQRew zx|(bjT|+jDt|gmA*OASl>&aNO34lfa0btP$04%x@fJHX}u;^w07Tp5CqFVu2bQ=JR zZUvh4mf@h1D;$XiLaDG}kP8oaxP?C&*^eRH2@a94#1)}09f=U z0E^xNVA0zEEP4lkMehQz=sf@yy$`^m4**!S9e_n20K02X}=2rPOu6goi!Ny*la zT0dqMb&*e}d7p&B>X%ydMaa7<-z@r)>CK`YWV7fivRSl~Y!-b@HjBO?n?>J}&7$wf zX3_U#v*-sh7X1joqFn$i`U!wVKLfDn7XTLR24K;z04(|qfJMIpu;>o}7X1mpqQ3xG z^fv&DoJ6~A$08SiMF{{b3IVVv5r9P=0E?0USQG|eQ3McJ^jRqMln9dYxPHFqbF=6{ zc`x5fP7JGGYEkP%@5@57s14JbMQzDuQ9H6()She>rI5{{4rH^aBiSrUC7VTQWV0xp zj76OQSkxJSMO^?`)D?h5-2hnB9e_nW09e!$fJGSqEb0ZoqTT>3>I1-{z5p!R3xGv? z1F)zc0E_wquxK9u7VQhbqWu6^Gys4_0|9|WEfYg+io~L|@|Ve8tHj_=e}(>CYGz_s z{Zfkt$<2PTSu~jG&7vV>vuG&UEE+~Oi-wcUq7h`XXe8Mz+MjF|9Y8jVMv<{-GysbZ z1YprY04y21HhuW04zEjfJH|DuxK6ti{=BcXaN9=76Pzn5de!81F)z8fJKb}ELsAi}4E9srBZ2Vl_!04%x?fJN&8SacBpi!KIW(Io&Z+5iYF zT9FvqE`p@|D$zUIEILphL0*~|R=?DuD-u1o!YsOy>CK|6$Y#;iWV7fRvRQO3*(|z_ zY!+QlHj6fq&7%L1&7vE~Sac%*i*5p7(aiuXx&?qmw*s)}HUJjg4#1*209bS<0E_Md zVA0(GEV>7PMfU=*=so}z-4DQ`2LM>~AOMRV0$|a@04#b0fJK`DSoA0$u;}u{(B2|Q zO1Q0vv(YS)|DRB9*b>9)ms+$n(HlF#EP9gZ&7!BsX3;jXS@bm7EP94)7ClQgi=HE! zMbDGXq8G?!(Tij(dI^9>67VQRL(XRk3`VD|ZzXP!74*(YZ3BaPi09f=l0E^_$vM-SiPIR%z z1z=GE0ER{$1u17J~i02cKCU{Oy17G(gis22c>dIPYi4*-k$0qx6GmZN1=5{|$YRo#Tbo zFSTf>=XIWJ77b&1vuHTkEE+*Ji$;>oqW#Hc(E(($XcXBj8cjBf4kVjJ2a&O83;>IA z0a%m=z@mHr78L-ns1SffMF1=s3&5gc02Y-1uxK0ri%J1lR0hDJ@c=9;2VhYJ0E;RC zSTq5EMO6SSss>z0iRoNXotXx$7ZjQN2Dqn&^eqFSTf@=S8QQMF%sz zS#${5EIO2I79B=5i=t$+Xd2lpsw104)5&Jh46<1?lZ-|604$mXz@pgzESdwrqPYMp zIvjvSM*y&B9srBx1F&cT0E-p^uxJqgixva0r~!aQjQ}iK0>GlB04zEZfJH|EuxJ?o zi*ubgm_-xii#@%gy|DVF79H<-*BoLNtz>$$XcgHkI)Q8! zttOjAYshBNiDa|rB(hm_GTAITg=`j`O2(qo09bT70E^B5V9}WXEIJE-MP~!BXe|JX z&H-T2xd1F$2f(8909bTB0E;dFV9|vDELso1qKg1nbTI&nE&*WC1^^aa3c#Yv09bT6 zAh76IFZ8qslF~)K5zjl$Ec#6?+USMVFSY1u&->~yv*;S8H;b+%n?=`=&7$kcX3-|H zS@a*WS#$&0EV_|w7TrWPi*6=k(JcThx)p#$w*j!|b^sRL0l=a=0a$bw0E_MhV9`AQ zEV>tfMfU-)=zaheJpjO>2LV|05CDrF24K-604&-Jz@kS1So9bGi?#r;=y5<`(Uo4P zT~sWZrs7;>7NzMsAWwK<^-C?<=6N}FX3^73Zx%g6HjADmn?=u&&7$YYX3+~|v*<;# zS@aUwEP9!27QI5oqE`V}^cnz*UI$>&8vrbN6M#i;0kG(802aLiz@m2nSo9tMi{1xd z(FXu5+77^?4*^*85de!m24K-A04(|xfJL7Hu;_CD7JUK0qAvk~MNfL6i6ThKfAm4) zQ)ZFtO4#9r)i1T^8_zpxhFSD2)0;)#k}QHj92Hn?=8n z&7$38Ecz9IMZW>C=yw1X{QCa0I(<-fJH3;Skw}LMXdl>)Ea3>I1-{z5p!R3xGv?1F)zc0E_wquxK9u7VQhbqWu6^Gys4_0|8i+ z3BaN(02XBfuqX$BMS}oXG#C(A)IKTnkqDA9B}2qXNeb@tr|KDPNK#n+Qj10;d7(LG z(MYB@i}oj*MF)`0qETeCXf)X@I*@D@9Yi*Z#*odTT(Vh|N5-Oj02UPhu&5A#MMVHC z8VkUpVgMGE0I+Br0EW(;Qi~2v@=6Xjiw8sy zqB^o!G@Wb~%^;gaGs$LAJ=rXpMK+6Old)(H0E^}Vu;_3A799b=qIm!;nh(ID1pq8s z2*9F604!Pzz@i2K7BvE}XbAv|mIAQoNB|Zc1;CW~r;*K~)5&Jh8DuOv6M#i$0kG(702ZwUV9_}MEIJo}Me6`qbRGbU&Ie%8 z1pq9%5P(JN0a$bq0E;dLV9_N2EZP9TqDui-bQu7PE(c)IMgSIF0l=aw0f9v;lR|fj zASvm6M4VM-(J^{px+*EGeyK&*C3&wcFpI8ddb4N~*(~}G*(|z&Y!=-}Hj8c|n?*O1 z&7xb#X3?!=v*l02bX3z@i5LSo9zO ziyi`C(Zc{NdIW$)n*mt#C;*Ed17Oh>02VzCz@jGrShN*@MNa|(i>^ru{U(B>oa%`< z*P2DW^}|L_C56>5wdmO-uj^v7=sBi0i=HQ&MK6%eq8G_#(Mx2r=w-55^a|N5dX;Pz zy+$^RUMFMG8vrbN6M#i;0kG(802aLiz@m2nSo9tMi{1xd(FXu5+77^?4*^*85de!m z24K-A04(|xfJL7Hu;_CD7JUK0qAvkhv;%-eUjeXaCm^us>7>vY5hUdVeIM-^vuI67 z!q-V*^-C@KKFOd*}QHj92Hn?=8n&7$38v*=f{S@av(Ec%^{ zMSlRW=uZF^{RP0HzX4d}gzdH+i(CK}B>=D}1i+$102X-wEJ^}kQ5b+l5dan?1F)zC z0E=1zu&5OPi&_J)s0{#%+5)hs9RQ2k0|JY_O$wbPf~1U-ueSESGm94KpE#z3!|In> zlos}`TWS`iGrd{ViEI{iCYwcF$YxPjvRTxPY!-DVn?*gyW>HVFS(HJ>qFw+j>J7l6 zJ^(E03&5hi09dp)0E_wou&6%(i}nFv(Y^pI+7Ez50{~bw5P(IQ04&M^U{N*zi*f*1 zGzfr2g8^7H1b{_D0a!E)5LnbP9C}s+Nm;0mh*HDBo&EqlqYan;<5c`oiw+2TUms-_ zjbeJUXf)X@I*@D@9Yi*Z#*odTT(Vh|M>dP{$!1Xj*(@p~V^I+Ri^c-5s2G4nB>*fM z2f(6I02Y-2uxLC0i^>65Q~|)EN&ps30ANuS0E?;tSX2YRqFMkJO$1=kBmfpo24K+? z02WOJV9~*Vz@m}iP|7l~=udr5e}A)Ri&}I@IIMoDMbpCG;1y<39n+gd)5&Jh46<1? zlWZ2%lg*-8WV2{C*({nvHjCzx&7#A}Sabvci{=5aXg&ao767nlApnaO0kCK>0E-#` zSkwr>q9p(AQ zMHd6G=n?=HZ2(}=r2s6t41h(K1F&c#0E?~wV9}KTEV>GSMOOo`=o&y^(duyMG7%)@ z5Pd|n#w^OvXV=$;!|In>^q;Wz$Z=-T4NPwq-AFczZX%mSHVXMfU@+=m7v0JqW;}hX7dgFaV1l0btQ) z02Vz8z@o{Zflw2z%Ztv*<;pH;Y~(n?)~^&7xPxX3?u;v*U2yjc|0kMe&P z4y#{k(XOypy4o!IiRsOvpUGy?FJ!Z5H`y%um24LMMmCFnC!0lokjE1;C=c0a(-z zfJOZQShNoSi}nRz(S86d8UVnefdDMZ1Yl7X0E@B#Sd;_6qCo&G8VtaqApk5I3c#Xa z04y2~z@iZVEE)+2EJ}}r?iN8(iu;Nf02Un&z@n7^ELsJ?q7wjEv>FgtR2K>5i6AK# zbrErV7XYy6LI4)62Vl`f04%x~fJK)8uxJASi!KFV(PaQE zx*UK-8v$5!1pte#1Yprs04%y1fJN5;u;^L<7F`FxqU!;HMJGid^MK?vfO=p=!H#5CibPL%mx|M7e-9|QxZYP^XcaY7ZJIQ9zU1YQ9Zn9Z) z4;hQ@1z^#A04%y6fJF}gu;@Vm7Ci*OqK5%k^aucpHUqHeQ2-V_2Ed{%04#bOfJILL zuxKj)i=G5v(Nh2{+6KU)rvX^>3;>Is1z^#0fWV>~BBAF+kd%WXBF>Fw(X0ArMbAgV z>X%yda>V;~ty%O6)0;)FlFg#m$Y#;&WV7fEvRU*d*(`dCY!)EvFJSj z7QGL^q7MLAv>kv&9|ExGBLEhC48WpK09f=X0E<2YVA1CQEcya~MPCB2Xa@j`z5-y; zP5>5t4Zxyr09f=b0E@l@VA1ygEcyWuSoC5f)bSj#=q&x*^-E^aXZn$~A0uJ)OD*~( z;tgGA7VTzwv*=f{S@av(Ec%^n7X3jsi~b~=MSqdaqQA*zk&|rq?Pifn#-aoO7KH#< zlnB5g4}e8U04xdvuqXn+qGSLTwE$pIO8^$N0$@>V02Z|YU{PBD7PSLlQF{Our2w#~ z0|1LU0F3%8gem091>)RonlEdnkTGTDsJNkUHs5{e} zMLo!7QBSg2ltDI&dXded-ej|=57{j0OE!!4BAZ2fld-5D0E_wquxK9u7VQhbqWu6^ zGys4_0|8i+3BaN(02XBfuqX$BMS}oXG#G$ILjYJb6o5s;09Z5}fJGw!STquVMf(G= z=l}o~jRFJ~bx96w6hTtb^y~J!CI@%=b?qgLP7bSIYEf>o_vnRYQ6AHqMfqg2sDNx1 z6_U-OBC=UDmTVRklg*+MvRO2aY!;Q0v8W7yMdJZjR1UzR3IG;W019V9_1`ELsV`qCEjvv=;!2_6A_lJ^(D*7l1|k0kCL) z02Unpz@h^IShNa&MF#<}=wJXA9Ri3fn%yzJkqJ`xk^fS0t1MdWN3=sbCfzT$=*W(V zDQC%|qZnTn9Zi-+$B<>wv1D0v99b3}PnJa|kY&+{WLb0)Sr(m4#-dXISad1?i%tVz z(dhszIs<@3X9BS3EC3dr4Zxyv09bS`0E^B8VA1&iEV=-IMHd3F=pq0XT@1jYO8{7O zDFBNu17OkR04%x!fJIjVB8v|17+-3F6ju3{hmMd%Iet(7s*Xwb%PqRDW8%bfWYP7E zFNW@7Ci~TqNe~@ z^fUmAo&jLdvw+B=YdXenGeHWI{<-UGWzlT6=(&zb_scDMsbk``^JLM>j4z8`AQ>7X1jo zqMrbfMK5%W|7C&{p5&LSUzA1P`bpBy9h2^tTl8DUM86AV(eI2ei~bnIuxKa%i%J1lGz@@6WdJN14#1)j04y2_z@kwA zEE)~KqA>t08VkUpaR4mZ7=T5a0I+CN02Yl0V9{m(EZQ6pS=1*xeuN29Sm5IH&5nBd zH+k41JL!J8MU~l!D=(ErRg5o-s>!lwB3TwqBFmy0vMkz?EQ=?E%1|l>jW-6M#i~0kCLq02b{7z@mKtShODii}nX#(E$J~IuL+Gs{mMZ5CDq~ z24K-404zEbfJKJ^u;_3=WYOI0c=s#JqJw*zIP+xDLjMlP5!p%i%Pl%4J2B=eS#&Jp z%cA4RvgmlSEINTKi%ulVqLaw7=wz}iI)yBYP9@8t)5utKIsl8#0ASIX04zESfJJ8m zu;?5B7M%;gqVoV)bUpx!E&yQBg#awN2!KTw1F+~402W;ez@p0lSadl6i>?4*(Ukx! zx(a|rR|Bx<8bD;xQQ7hBO_0I@|J?P_vS^^6Bwd@Gbidr98?zJpTqBEaVtiS2Gg%hh zLY76hl4a3tWLb1OSr*+vmPL1xWzk(^S#&oUi|zqn(Y*jHx(|Rw_XDtKH2{kq0ASIB z04#b4fJF}ju;>v07Cj2UqQ?MO^f&;Eo&aFclK?Dw3V=mV1F+~B02Vz9z@p~>SoAyq zi(UXk7G0kmzrX}3JjgruH^`#B+@cq=lkS&W^lEnEf$L<^Ym6_8UMI_zMSX2zaq8IuN2UH~lW4Zxy4fXJfXv*SZekiv=UnmB*R zqQm{-QQw@T`{fp`lar{wSr)C!__AmKSr!c>%cAwjvS@v>EE+_XMT5z*Xalk=+K?=Z zHX>uu5C9ep1z=Gr0E>nJu&4}xMZ*DDGy;G{BLP@63V=nU0a!E!fJI{gSTqiRMH>UK zXcGVyZ3@7m@c=B^41h(O1F&cd02Y-4uxJ7xvZy2{zT5;UytKr`>7Ntz^!vF|6*)=w z%PpFilQ{WSSu~09Wl;@T7HvtEMU%<0sFo~?rjTV(9a$FDlV#CVvMicL#-auQ7BvE} zs0n~Y%>XRg3V=mh1F&d10E@N(V9~Y!EZPo$McV_gXa@im?Fhi4762CQ1i+#h04$mb zz@k|IESe3#qE-MF%>iK1TtH+|RZjd46Qppg-;J%7MP2<1A@g#Q?w4D%ASdz0?XqYg zjZT0xdYyOFVIcK{ac0l=b_04&-QfJJ)& zuxM`p7VQJTqJ05av>yPA_6K0m0RSvI5P(Ii09bSo0E-R=V9_A}EIJf`MTY^f=x_iQ z9Ra|iBLP@+6d3+FI$LA#a-zAGqV0>A0B3Txl zM3zM-lV#B;=A0$|bA04%x&fJN5=u;@Af z7F`dBEIKwPUTuOD-ry(H$H}6t{k-UgoTU5Z7TuDQn0t>bx|Q)|(QRZ|bURrV-9eT` zcamk%U1V8wH(3_lLzYGNl4a3-WGuQLfJLhTSo8n@iyj1E(L(?%dKiF3j{vafQ2-V_ z2Ed}n0a)||0E?akV9`?mEP5J%Mb7}R=ve?3JqN&|=K)ys0sxC%1Ypri04#bL5Lt9n zPW&hnr0`?^I_%A|=tXasUdc(iUvAMGIf<+9lSOYbzASo+EQ{VI%c6J4vglp1EP9VD zi{2;8q7TTj=tHtB`iP809|N%H695){3c#Yz09f=n0E@l=V9}QVEcyz7MPCE3=o>67Oeqb(XRk3`VD|ZzXKwRUdxF;Z-Nxw z;g_plmql~?TKFR;>3+FIL2lxQ)v_p-tDd|p${@?4I9V2Dl4VhXEQ_+pvM5QGMIFep zs3TbxWs|We2Y^Mn04&M_U{O8*i#h?Ys51bI3IJGC2*9E)04(YXz@lydEb0!xq9Onm z6$7xS2LOwD0D9u&56Ji~0hvs2>1}N&t~Xf91rBA25r0`}Lx~Wl@nU)jv1s zez`>ha}(npl11w=zARdwEQQZg0|17J}Z z0E>nLuxJDTi$(&lXcPd8Mgy>D3;>J905=4HV0tQ z762?N2Vl_z02WmMu&5G%MOA>vqIGlQJDMPcQ~e`F19GFD{)T>QwmLWIez`?k<|g)g zL>5hEd|6aWmPJ#@vZ#(Mi|Wa;XewD2O(V;q2C^(_B+H^EG8Q!huxKj)7Hti{qUiuE z+6I6{+XAp?I{+4K55S@w09dpm0E=1xShN!Wi)H|@XeI!QW&yBhHUNuS0a!E#fJJiw zSTqlSMe_kzv@;;GXi{$cA`_(W!gWlX8d-Ffe>ZlQ+@$;E7A?+AJoK0>TEh6UXjif< zT1u8h%gC~5IawC1Aj_iN$g*g6vMkzzEQ?l>v1m^K7VQPVqP+oFv=0D__61e=uiL_9R|Rn!vR=y1OSVU1Ypro04zEhfJMgu zu;^GoWYNOh_~#}_;V%BU>qW9?pkF*XE;s3ZxkV@CCUTyXMJF@9EINfOi%uoWqSMH- z=yb9yI)f~W&LqpCv&gdOY_cpmhm1w%0j02ZAOz@iHPSacx(i!K6S(Zv8Px&(kl zmjbZpG5{7`4#1)-09bS-0E?~yVA0h8EV>4OMb`qb=sExvT@S#b8vs~zBLItT0z?*_ zkQ*Onf)wuLpSwO$7A^K$vp44^-7mN3_T0p@r)AL{j4zAsB+H_^$g=2evMjoXEQ{_X z%cA?pvgm%YELu&LMGug%=s^G$Jp{m_hXGjh2mp&71z^!*04#bOfJILLu;@tu7Ci;P zqNf2^^b7!to&{jha{w%Q9)LwJ0I=vq02aLjz@nD{So8`2i(Um_(QAOnqFZz0yO|(` zFZm^++hoz<*%n^UO}bxh(c8I+Q=gSZ?=ZeBdY3GV-XqJR_sO#81F|gokSvQnBFmzW z$+GAZvMl%Jt51~b0eq7BHhXhX6r+K4QRhLB~^P_is4CCj2=WLZ>3mPNzKSTq8F zMI!-NGzx%4qXAen27pCl0a!E+fJGYvuxJwi7HtZ^qVWJM+6;h2n**?D3jh|C1F&cU z0E;RBSX2qXqACCuRRgeSA^?jf0V0dm%ZpDkK?>)2=YD-zbiP|ulb3YA+@dLYiTSU{ zqB_QxMfGG^G?grirjcb)16dX|l4Vg7Sr#>uWzkk-S+q47i>3pxXd3_)Z41Dn?EqM` zJphY#0ASIM04!<&V9`zhESdqpqL~0Jngzh3*#InR1z^z}02a*!V9`7P7R?7>(ar!Y z+690`3jkQO5D-~3IWK;U2~v22f9|?g7Cr7KNsIE5?w4D%G%s=OYqDq=^7799(~qT>KqbUXly zP5?v}Ey;_&Xo3`O=FQKpvM4Lx!ijlF_scChH81hg8?xv$#+OB>lV#BvWLb13Sr(l| zmPKciWzjigS#&O07M(|yMdy>T=mG#1T?oLUivU=3F#wA$0btRk04%x;fJK)Bu;>Z^ z7F`LzqN@N{bTt5rt^r`twE!%-4uD111F+}@02bW{z@nP~SadT0i*5m6(XD{UqLcID zJ>N8oiv0%cDYEEEx9GOKr2FL--IbTvc02aLtz@j$*So9_!vgnSy_)aEB;mJiN z&YiO8R=*wcR$kKma*N)}OC0d7EP9{uWzh#@S@a=U7JWpPMIV!8(I;eC^eI^ueMXi= zpOaGj* z04(|yfJMInu;_OH7X1OhqCWvx^cMh&{sv%Ckgtw87R3OOMepRrFEK$1FZB<}zAKA{ z`|Xg7{G|Kk7G>op9(i9DB^h59bs)>4j$~PsO_oJDWLcC;mPL7FS(HzfMV-j9s52Rh z3IJGC2*9E)04(YXz@lydEb0!xq9Onm6$7xS2LOwD0D9u&56Ji~0hvs2>1} zN&r~YAAm*c0I+CX02U1ZV9`JT7Oe+}EXvG}e`$gg*7*r_B0uWsPxYS)T|YnRez`>( z<|pz#l0_RazAPF-mPJF!vZ$0Si-wV9Q5jhl4JXT@5oB33k}Qixk+Enr0E@-|uxKm* zi^c)4Xk!2tZ34ieO#xUm9)Lxg0kCLu02XZlz@l;h7EJ(PQ3U{tDgjtj1;C9<|o}Rw`fIv;`GmC(Qb?{i*_f=qCLp6XeC(| z?MaqJdy!?)-eg&{4_OxNOO{3Zk+Eoh02Unpz@h^IShNa&MF#<}=wJXA9Rk3jLjhQH z7yye72Vl_=04zEZfJH|Eu;^$2799h?qGJJAbQ}PSjt5}T2>>iQ5r9P}0kG&~KxEOf z{P;a4NMVj2#FopVX<>&gKk0tCMQ7wE-uXfnoyqvJ=q$1i!K9T(d7Uvx&nYjR|2r;DgYK;4Zxyn09bS_ z0E?~zVA1seEV==JMK=Pl=q3Ob-3-8@TL4&eD*%gb17OkZ04%x#5Lt9uemwI_v*;)P z-1X_Qs4~OCo%u=k%PqP$KQZuYS#%%c%cA?qvS>9~7Ck_gMGul?(L-ce^e|Z#Jwld6 zkCJ84V`MCP9Dqen0I=vu02Vz3z@n!CSo914i=G8w(Q^PSdLDp9F95LUMF1AP1i+$~ z0a)}30E=D)V9{#;EP5S)MQ;GG=uH3?y#>Icw*gr64j{7V?)>xP%c9T8vgix4Ec%ixi@qYuqOZwV z^bG)uz6D^>cK|H<9)LwZ0I=vs02ciOz@nc4So8}3i`D?J=vM$1{RY6I-vLM17J}J0E_wquxK3s7Oe}wq5%Lb z8VJCm^#EA3J^+gb0kCK=AhIagDgLqvQh2mqXzb7_>gm_`CuTS3lytw`qM@AEc(lDdJK_8v;FM4zEjfua*G-}CC2|Ei<%f;7B!P)(N<(x zv^7~4O()BuZOF1{Te2+Ljx39|C(EK8$XK)^0E=1xShN!Wi)H|@XeI!QW&yBhHUNuS z0a!E#fJJiwSTqlSMe_kzv@-yUb^&0~0ss~*1Ypr302VCmPPxL zWzl|QS+qY{79BvAMF*0xXcYj94gz4&!2m2e1b{_{0X02Un%z@j4nSac)+i;eMQ3+PJodXRI*0LP(Ya(p zOqNBLkY&-OWGuQ2fJK)Bu;>Z^7F`LzqN@N{bTt5rt^r`twE!%-4uD111F+}@02bW{ zz@nP~SadT0i*5m6(X9Y1x($Fuw*#=~4geP23BaPe09bT4AhPJpPVuizkiy{>6KBby z$NePfo=!>k%Pm^nDbeXKS@Zzo%c2L#vgjeQEP9wMiyk4%qDRTH=rOV^dYmkao*>Jj zC&^g!6ab5!24K-M04#bIfJM&%u;_UJ7QFz#q89;J^b!DzUIt*%D*!Bd6@W#r0kG(G z02aLgz@j$+So9VEi{1uc(K`SvdKZ92?*XvreL!T3+FIpL9wz2R;G&-1Vo7FN;1S%c9T8vgix4Ec%ixi@qYuqOZxa=o_*u`j#wO02ciWz@lFOShNO!MZW^D=r;fs{SLsQKLA+tCjg870$|bK04xeR ztJ{u6F#r~20I(`{fpubxypODT{_P zzAPF+mPI4UvS<`p7L6v$qA_GyG?pxj#*t;w#$;Kv2^otv1z^#502XZqz@p6oShNKI zi^>65Gy#A`6#y)%1Yl7W0E?;tSTqrUMUwznR0F`GEdf|G8GuE#04$mUz@j<;7S#i= zXet1UrU4?0N;}815@yjXzmGOd7H#2oV;edr-7mLjtImn_ld@=Q#+OCY$+Bo0vMkz` zEQ_`y%cAYcvSZE0OaK02Z|ZuxJhdi{=8bXdVEI z<^!;3X8;!M0>GjL04!Pvz@kL}ELse}q9p(<+7*CBO95E441h(;0a&yGfJM6jB8!?j z$7@ZH!c+Xy`^~cG^+F4~cTT!rZqZ(y6AL@aqP-bk7VSfpMf;Lv(SBrEv_DxE9YB^v z2a;vcDzYp(h%Ac^CS%bd04zEbfJKJ^u;_3A799b=q9XxVbQA!Kjs{@SF#s$&7Jx;^ z0kG(J02ZA9z@ifYSacEqi%te$(J25dIu(FLrvb3&bO08e0l=a&0g**3JI7BjK?+|f zF>&^kMF;uCqq90E-7mN3yv~Umb7ax^j4z8WAj_f)$+GAovMjooEQ>B7%c4ukvgk6h zEV`U5i>@GJ(Ukx!x(a|rR|Bx<8UPku3&5i509bTA0E=z_V9|{LEV>DRMK=Sm=oSDL z-3q{>+W=T}I{=IB0ASIb04%x-fJJu$u;?BD7TpWLqWb`mMdx&mziNUM*86Szb7j#) z|3b+9os;gDTl7%p#IJd>=wZf}MURkW(W7Kp^cYzdJx-QIPmpENlVn-+6j>HMO_oK^ zkg@1l02Vz5z@p~?So8t_i(Uj^(Mtd-Cwn?-N=C87sq(UE>P_T$b; z_scE%ymMmn&a&tW#+OB3l4a3XWLfkzSr&ammPOx^WzlzJS@be02ciYz@k3@So9|Vi~a&&(cb_p3JTP1$D$Yji!uOM6bE2Y zCIE{P04&M^U{Ml)MI8WG)DeJ1*?`ERPdmqFn;?Z#{nPuO(H7-d$SFv=Uv5#Sg2cgv zvZyoT%c26ZEGi_+qAp}v)RioYx{+m3cd{%hBFmy;vMlOB#-g48Eb0ZoqTT>3>I1-{ zz5p!h2f(5d02cKJV9`1NELsG!TGA>jAK6eE=2>0$|Z#02XZkz@iNSShNuU zi-rKOXea=SN&%5Yc?Iz+OpwA$6DCf6LDbXV+^;$gD@eLuZqdks#1ma*(J023MWe~G zXbf2vjU~&Xab#JvFDgani3BaN% z02WmPuxKIxizWfEs0M&VTLQ3XG60Ke0a!EzfJJoxEUE`!(Nq8yO#@(20|1K}0a(-o zh%6dj5dYQ$DIDXS`w_CJlONui3zF`aTeM913V9^2q7A*u| z(INmAEe2rG5&#zM3c#YJ04!Ptz@p^04zEkfJJ8ju;@$x7M%saqO$>5bPgc0Xzzmf-X=)l=SdT1A6fK{ zhjR;(?w4D1VL{^TUb5&S#+OAGlV#B*WLb16Sr%PJmPMD7WziL6S#%{?7F|V_MOTxt z=o$bPT?@dX>i}4EJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2vibUOfx?f_uXod7Jl z3xGv;1F+~G02bW~z@qyASad%Ci&g`$=m9`v(fI}O)h0+`Nv?@=fh=0!7qTBLNV;Ec z(W3>45BkWW#~5E0Jx-QIPmpENlVn-+6j>HMO_oK^kY&-cWLfkaSr$D{#-bMhSo9(Q zi(Ud?(aQiVdIf+*uL7{>H2@a94#1)}09f=U0E^xNVA0zEEP4lkMehQz=sf@yy$`^m z4**#7Apna$0$|a{04(|hfJL7IB8wg_he02ciY zz@k3@So9|Vi~a&&(cb_p3JTS2$D$Yji!uOM6bE2YCIE{P04&M^U{Ml)MI8WG)DeJ1 z*#Ioc0bo%s0E_Yfkwsq=#Oq9u!mA5RoG)e3xqdq&zcA^3xkZJAiN)*4qArXti@K6! zQ8%(I>Q0tLMPyl2OqNAG$g-#>Sr+vo%c9<7Eb0TmqP_qu>IcB05&#zU2Vl`U04!P; zfJFlUSTqoTMe6~uXng<{4FX`%U;q|v0KlRR0a&yV0E>nIuxKa%i%J1lGz@@6WdJN1 z4u~x3To^ye1Sy>5-LithsHcC9$&(mSm~_9~qA`Vun+M3Ev5YT^#*t;w#$;Kv30W3x zN|r_A$+BoOvMk!1EQ_`v%c62J7EJ(PQ3U{tDgjtj1;C46?WJPlkS&Ww0&XX_w{7a4va60b|lN97P2hbi7bm|kY&+KvMicKmPND4 zvZ$3Ti{_BAXf6PY<^iy1J^+h$24K-H04!Pnz@mi!ELsG>qQw9#S^~hLT>)6M6o5s` z09dpffJG|+ShO1ei*^TK(H;OSS_#0SJpov>7XXX)21FKZTNp1{-z?g}KbW?iEPB+x z)woY#(*1Ia4k%2N50*s-GQKQYMV3Vek!8`rWLb0wSr#2imPLn=WzpeeS#$(h79B~( zqN4ydSO4uD0+1F+}>02ZAHz@n1?SadP~i%tPx(Ww9|It_qDrvtF) z3;-6L3BaPW09bT30E^B6V9~h%EIJQ>Mdt$|i}ovw&oMy?FS3}}Ul!fyKZ$igVbc8y zx(6AFbvs_aQ7kALZ)e>>QH%W?ZD!E{c9*0>(S>#(%q@DzPO3T=ePYd7*P;!(2SIVs zt|n#gqFe0)lqE%f+F90sq6+&9HG_%{?;ivk6+L6OTZR>NTQ3Mk7Hu~u2*wtjzd;ae zTJ*_AL9j*9kkTNiELv6;1e1zx9}xt#MSqV9f~iGSV}qcn=*W$OV0zJWn+C!5MMawj z!A?axln24=q6;g6U|!K@RY92i{zXSO z2Ejo^FEj_iVMRTr2fheflF3W86I zE8@MFL&ZG~9zcbD5{h!u~y%C>_3jaQ>@s3-FkMc*nggQUaZ)EUv@#P*nc2& zNvzm^;c{bR-cD@O;#iv4G54vQ80?~EK3EA}6XI4)M~ z-}FBzR_tHZJ}p-4-?cp}R_tGvJTF%4-*&qwR_tF_x-3@g-#57`R_tFGxGq-gpZLBh zR_q_yy)9PkpSip%R_q^|yDwJkpL%*QR_q^Jc{En+pF4OmR_r&9pN$p!oxc}j#eVDN z)mX7#dw(-l>=#epjTQUVuMcCze);0lSh4p%zl;@o2jbgUv7Z6{7%TQe_?lR;x50nJ zg6wg&qa-ehcDWws*}juCvY;dx1U={2ei0jy)5V_qqta^Zthr^epx3S0{>q3kM(oN- z_~^B#?R&8iQ=ByznPC5VHCy*MHe#ML+a$rA_OJIh&PL@QYtMt;TjpCBtuW2Q7=^jE z%f`m$o0vA(F1CoVae8ILz7{rCnBLRECJHScHdWZde&#$jUZK;v7B*AJw6mJn<_b;L zD8#miLZ4%7X8s1h9TE%r#-?T!Tz>pdH}BgwHZ76+-f?S2^^G+oa^F4Xru@FK#;k%D zKRxBveS$uB#7r6+Cv#{xPDY2pL7yj$9bjy1#1grgKaE~#lgTQ$Cj-&<#P3;I24;~Zn-^m)^s_(Cja(_yJ)i`Y%2CvFZ%tW1MIEd7LVTQ*U?C^VL_kog<_@QyLa@L zP}eq;ZJ&Ygb+mpP>Mpc#8`{Z`FVo@(WfiP>>Wm|871`R~>$7e54&V99Fa2?@Eu1aW z58uCVgFIxYf{`KA!Hc5MPM;`iEGMvy=KfbbR z-=N<$Hqx0kQlCdP_D|8+iQEfoZW|n~nVT-U{eGK_ZM@azymps8vyHc8^jol34narH*>}|qXKfn6h&!YGL;Yp8P z}}t8 z{?lWEl09vt)r@e`%Xi*ma@z>kfB4fw(FkAPcIIF9%;tCd>hs@P83g?|EC~Ytmz5FE z>i=LzJG$Awtby_D{^N}LzpS{uGR|5h|CjY$MppkLtby@=S-)7g#LgJ}U)HAJ@7g6QcqrS(&kT{$@Ej_Hr~>%wTemjn&&`*CBjjo4RB8#MVN#CYXpOm=lZD zbn#Jg``hG7ZIrxDHglhHewSEIPTMp)}JAER)>iQghV9d5nS-5uk9&unS$S6L3 zf;Hy-?1jKzu+s~MF<*uTKI=vK;aqLegZ7U-EXIPVUOL-m$P9jnO+DA2b+>=^f)_sk zMlZABQ!3%Sn7S63_IJaqD7KKlnyfEWw z=eD0!da`$JlWg!}2YY)u-3zmA2xsf_vKPEWGiqp?(e(5gHKbq|6rXz9`!rE``oDP6X7R_W4~WwTmamMmSoymi*{ z*4d@Amabf~e6fRBt+Q7wZC#f3nh$S7k1JiWbpFEm%jfUb8kEjkys))&#)8&8N{233 zJZr{+(q;2zENv}a+PbK9*^FhSt;1WEEnhKv{^HW*ix)4LHE+iJMaxR(&YIOSW9h=u zvSBSFT80lBUe;1J%;6A&Ll!Mw)Hm($~b?d8Oq`XRnyQXmQ2jrL99!>tc`POT$$Xt&yoq7w>HAd|7GZ zk{L^Psa~!(w=7?|q;=WQc`mP+Fnj)@Dp$?Bfy**j4?XO%(QR zdp)avsV!ocM4`W_@%Gf;RB58G)ea?zj#=>oW1A+5EOjqU3|uEs)W=w9qPu~Py!TGg zdmpIx9>$^e^6*A@w=v;3>!HtzT6j=ch#=O zb4&i=)p*X(_=@y#=4y>l+f8GwX`4Q4&1~HbMY@%4u=Z>JMV=haw8-Yg6zy$BPY2po z?*1RG^&Y+@Cnt((d`6|EbG5Cbjoten<}Ts?{YLMeRg@?iY-5fOr}a-Y(r0{P0E@Yf zyVEV9i4I6N$t4_~dZ*^NInuqC!Ty^3+UxrN{{jyC-(A4&{SyP$O%(mp#`%xdV@F$K zzPbA+62s=U?fjGfVdu}wsI@&mD`xAuf1-PT_ta{*^RK=7|J&8>rga}*niw#w{jxK` z|76)qeK`i&`t>)@h%Cu}vIJ&&w1?Qzn4kan+?zVR!ds1*sMZ#~ypP&KTZsQ@TiD$i z=)@pfg9F;V{dE)F!zR`D1llBTTdi3xvSusXwb_wM6YJPI%q>aeWyK3OP54oyS81YW z|HR;R{1B68O;|5uUj4N^8t5)j13g%~RTzib%fl0We6Y!hUNt_F?OQflX+M8%v+fzf zL`U0PHq_eds}kWj)}pxo_cO%PxU7MQ>D%5u8F+9>=DBfJ^P~fCgFrT#y^N{ z8XfgIX8o70bRM43V*R1&#;Gk;4Gk?dbz7C!)>O8XH%x4vQdQR!@WPa;#>VoARV_{R z^)0pabrXYzs);RS&2=>zuDW7U%gnX`%Nr_N>gt

e?=Q4Wt(jg`+frTMFr~aHnxjps{ooU7>nkR=RF*fD zx70OHnNZc>@1wpU8hXUo^cmOHw=_0SXsl?c@xiL=o9imW!N!c86xMO=7PFzMacaFS zVKk+YHVo^+m%XZ?yfJObS#MJsC$>yzuCBJ}H`Z)hl^W$=-dW8QUz_1Dz9uIOOJC5M zx|U{UJWdN&R^4upiiT~bHr3l(uB~mET3=JwRHe5(T*H@Jwf@D3;VsL-_1iLa(l#x&t*6*lt|)J+sjrLH z)40@#Wff^-)-+6OnP84p)-*;lV_im*^ofO=t);f6ZgOg^ZCz7c(^5V)T*`|2y1J?g zwMdZe$g@M)!#Xl$;iFiTToqwKWis^+SeYFksOm!_6C)HH3AiZ1n(^15xb>Dnd{ zZnnny#&8KL&Fa(wj0)$^yU=jeWww8`G}c#Fx3n9$Y+SpcE6VFyni|UM8mH7Wg;Q>* zDzDrod@~c;3ER+EZW9VOwXI-@%{=QHD_RTR7?nU30q(Yk3jk+l6O^@e3nd2Kl7 zminnxb*a}-c|t?Y#7RwcwnkeTtD2g8UuM?T6}6MY#T_v++H*#Qa|~xb3>5B6Au@%v zt;XubGFyGAsnygpRF}6@RaCT;O{mdsUeRt>44an9n(~P)_03IFo10p;s;_Ob{U6*s`$l?u6zxhbv#n&`xqW@4jovWbcIlS-t*RQT zYwNdOd!`L_6I0Emc~w3oH9*Z&Ys|EXr&@E8-kyeUsnJYGHIlEH|?lx4_R)uY|udJ%}9z|Q)-?MGZ zn(An!L`yI_Z7yNE;~U3YxbSGErEKR7JAF%eMMZN%d4-y=)bdQS2j}4Nl-mRk*>I&7Zrdb#{qe30<0+o%>v0ZId%e+M4LLCZM9CzGad%O{o!BH&f~> zqouc_e(J@Fs@mG-+VTdId}2+b`Rs=(-UwE)&qvER%tjC2V!KAWxp6{xxNd2jWalQ) zkk*{hu%*p%N|iNLI%#1}KD{z)C8P1GLXTD~N`L!4gth*u1+N@lsY7BzRb8don%4fN zHgH9F@*`(#EiRhd+S0mc_WT)(T6|whO{}K2wrXN|t#&y(%2(Px-*%V_eNP>c(zbHh z*mlNCl}R?Gw3Dn#-j;3LwVbH&=5MWrC;cSCnu2f_4p&cV&nO$!ZbIxnY^}88dCj8A z8Ovw1Om1D-WLH*GZ}%UMYi$PAR@R42YU(hetsQL~Yi_hr%gS`Pvcq?3+U)hiS}LbC zwNy@uj^OPN_oLH>SBo{p+N9=&@W2$diq*Di8YiW-$5>ojzKx$e>WFL4tg)K2V$rN& zBS!@3X{466ounz-*IMUn|FqNJTH71i3}EgP%co2!Z=1V0X=hig4%=tLnYQiMWo4ls z6YH8wD#nc~@p}|Q%S!w%#jvr%N0tm)+Pa{1#vH-0#fye4v)c_;ml>OF5~XtZ7RR(RFx=+R;lKbAk!w)@@QF>;Bsrf3)~x+Wfa;eZ<;#PrUQsrwTRJJBUsy z!u_{0RB?Xo;>AnKg0Kw#mt|>pz;1UQJjJFop?-S$3LQQ6U&gPfwWEU_Z@u;Mnc4}c z+nL%+%7zWsyGS+7wmDLhX)v zGSa5h+T!en@TH1QQOm3|8jccmVH@oxSlfxEAB)<~$gKOS zJ=DA7;ij-BLf&5vk)2V8Poi#Qh=!$xik{KHrkxswC$!e@(P^6P?$Oljt);D-v=RJF z(;BZ(jBwDl4q>V%J6cnT`f$uOYSyc!Oik;URrsZX^n-{mcY42a($;o0qGGbOqtQER zx8tw___<4Jtpn3L&HqLBth%PUzJ1@Z&7sQjitsL7yJJtP3I5kT#JbY9(suD3B(*rv zyKb&4-^%>=u5s#>w3S-kY#nbqJxlLs`zaNxF7juhby}kHo74-Tw0;g-U*`=(c+f8U zFJIN}W4$;D)Yf@x-zReiQ@XPtjZky4AiUQI9NKCOe(6 z_rNk)pVB&RH5E1CA!lm29dW{;?6?sYjt*Q+Nv94}va;g2Ldh3>E zyQF0+Qxnwm?1C0+&>9Xs_1>D6vTaJ%fp7G7vCT^#!hWv4?pO6Po<@C>zXEeCG7}GZ?3HEQb3ut%)zpGcHWfg z7kl3=oPiyb!zbQXa}af@!k5x^C_9&KTSI<{HoT7FXC-#+pk-otO?2VTyh{zn%CSB| zb8XuRhwIKcO!|py>hjHSF5h@Bj}^tl{G21$Ic)oU5xtYeAn825V;jyI_4GLVYT(ctjpR` zU0dGRHXg4wPj$2XS^!tY*Xk~%woOHKMcZ~M^NZ8WNmn?cV`R9YqbuwFH2nf~*q>Xg z-Do?DtgQMs=aIgFx2b9h!tS_Flb&7s2EYxrbCoK)PGMI~b=GD>m-!{4=hk9XVXSe?2}%JulvD>Uvu^$+ip9Wp;TieSd1ZrsMB8+7sHfK&hU)PcgMF z)1^yweYJwaYsKMgX~x?QV9|wNf6;q+;Xr;Bl%)=jxF&$fTVea!zucDifBAVcKCTvh z&L~`z==yQnf$m>gu`=&-goFCESe80{WmMPH+WB7k<%YI1p2o%s-T7&^hS@i8-L9YN zL}YQ)8wktr=m6YqkywD#Q6RM`(%MDucQPQei1wq@aXEVPX~Ttz{nKGRYUEQF+L&&5 zKZiyI=)yEKM-8Mm=WsRtW=s1^vuRx?yTn7+u4b!ng-6|^wI;#av3AuCd+I9ajt#x9 zG3|V33_J6+J*d*odD2dXcrkTfiGy;~mkHOBUsnx#XORYe6_d!}_$0cP z>rd$$m8D-I)l~g*e6{U%T%uy8(R-ua(vF^XwY7bZhBK&e#bG<*`Bjx%R(_1hoNQafY%{u3>UO(NWvQ|qImwtULew6lR|HT(TM zpKjZYt+ozD*~nC5>N`m|UBB=dEn2&FrF^QL_fNM@cRR_`7B5;4(ayvBVIOdT?H2Od z*E+*M37E`KWw9<93a)@5bG$4;EJuxe5G`SO}Y^OrZSXzO6LZMNEa zyZL90ja{lOuS>hK=i9FRm6@n#6m=BZ9bm&X&~^j(MdZ8vGQH=SB? z+W=8N#wX}oAe?Y?nY5*a&NdTHYvCs~OtwuK?Wi@T#q`v++q&HP^E9+;jp>(>{O}sB zz357-&A803Ql&~^tD!gyS}R17B05;sh9|hR#9GIYr486JUs|}_IwnA zZkBteJvO~h70Hx#w&K0FXzlowM_)}*1Hv4`mZ9*=99vi*=CyTw!(<&7Q|Aw5(FIlpwPuK$Cha?C)pmK3evN+~ zBbZoGv2n>DzcEn0bYV%=!kMkJXWN~=CcgI&-Yeky41@puodf%lk$qF+Z+qBxY4*;~ z%?k#keapkY>BG9D~cD#dc=Chdc}Ij`ev*Xv#$~U%Of3S2H*XiK0w?* z;h*-1>#HfCxPQPu?Gd*R_uH4W(jJ+CeUmiEObr&jeo|WY*N?I<$V88}FTHq<2dNjr zm*c5#zeYpH1N#nI+9Mvc|C&)euy4ntJ>r3V+cxbH50|bD!~^>hQ`#dQ*k4CTd&C3# zQ3A`pR($&u+WQ@z_IhV~zQtO(ajiUKt-N@xY~LPFJ$!nrQpvu%WY3RZE2q9WWZYlp zixg4MX~6Pez-%4K{$1nT{;2m4w_4K&C`&sm4zt@r(bfC5A%@wVjkGkB?oAyNz=bw7DoNEqc*jL+b zvg+e~t@@j4mZ{{tP<4B+Hr`3fmw2`5`FB^d?R(4*D!;4OzgPBem1f&ls59(4Dn5R; zDe2>l^=i}KQhBOZ`}Wp6<=wp6pV71uWSEw|uV>f>a^Jn$q{3=%A;_?uroUIybC9_2 z*FM~6)$ytmRHv#otIks0S#?*{{ZtQ9Jx=v})f-iBSG`yDA=M{TpHqEB^)1y8R6kSw zM)fDv-&Orm(;pugTvb)f2os`hQw@bxjO<5eqEYgFr1n^m_{ zouN8cb)o7q)s?FIsUEC)r0Vgir>dT>KN6{RI5~LRU1{eRh^+aPj#{CZmRpJ z9;AAt>Itf+tDdKNsp>VVH>=*I`he==s?Vvus``%V$Eshc{;2x9YKFA~zJ5BYc2+G? z?W;OabtBagsvE18t4>m_SKUf=2i4iCyQnTzU8%ai>Y=K~sGh8Pmgc0ix z@8@3ChgF|aeNpud)%R6DQ~g%;7ghh&0H0pM+BdJcs$Eojs`ghMq*|&vT6Mf?rRrqW z2Gwm;cT%0Jx=3|}>fWlWRF6Yb{qRUcD*R`nItw^ct< z{ZjP@RsUrGpMK2ReXkuGzQdYtO% zsu!qUsd|&@-Kr0(KBM}o>U*l6tNx(+hibwOSpI(VRf|+hR0pdLSKUOlQgw>zR;n$k zeq8kF?y9<{>MB(~2lUrZRy{}cQq}8JZ&zKd`h@C>s&A=&ton`W8r7JcxA}asRlBN= zP@QO}l>U07>U=wPdtRY>q@7ZFK2`N< z8$|hb)$cco^53ds?L@?fuTtH&EXqf!J~$%EkH35yS3q&jtMly^`)W#cGcsQTun zQT|MIoz0_MsyeSc$}3c_sfhBOsy|jmIaVFjjje~~^S2K$g?0Zeqk6RJ!?jUMx+)K4-=P1umJ!3(XFI9baQIx+@U2oSYk5FB(EXwxH_V9h( zup+AWs;=2R%85Oqy4jvloveD$-cdeY_3?e9{EBMl1ESnVb*oiTo~3%$!BM_k_5DMm z{Eh0MBceP?bTkzIIeC0kw>UAXQ&bN*Im#!hK6z@CUsEkSBg*|$ zr=Jz&R@HOPiSm`IAD$QG?^HLqFv??8ms}j>eN=C`G|CUC{&9JfJ6;jh30Fn6UiGkR zqI|OI)7M4$4b`qUM!CQ0wl_z4uIhQWM)_*hkL^U?{ry38qr0L!PIc)$QQlAWw)>*| zkm_Hnqnz_VR4X5f>NM3O9*Od)s?Rlz&nk z`cjlPQCRsPQ`7zaupQ7AJb9c~>o&zr06VZV#!`C!$1><7|3 zKcSkLALRnoEjvefYt`fIx6^$1vsGWVA5ruCfokufC=XVhX&pg-eX;6g_WNp{Z&v-< zerV0}@2Vq9qFk=Jr~M3zzkaCdefAq{o}W_9T0hENRBH!Ec^lOm>^Ba5_8Nvh4NGgTL>?yY*b>M5!h zs$Qphw^v)vMtX3e}aW2dW;TdaUY+s%NR5r+T^S z)vC9s-l6({>LaQh0^7fAd2ADhwTo(zYJb&%svD^eQ*BV)N_7X-8LD&+itt$P*L_r1Sv*{`c+6xeT!a^dnBGp#OP z8r69`vrpPD4~F_j+k>Gqmn{p1+K2InIvg5ZZ2WguI>X^+`)8o+w$7ZzHi_{0jF~f+ zw(b^9B_j3&B2ZL+vy<&Q^?K$Jv(_qp#`=P}&z*FCsc<#fkyGhJ`3)P=R51uZym_FZ6 zSHC-E=i;LETh3~_KU&(|N1+rRYX z+am4#di%@ry2l#Q|5CBue~9X{Hg4;xmN_W$V7 zBTGugjU-=IqGUHu z9TH`>n`d-LUT#|xK4*i(huZ-0jk=Wk^Y!fI_^__tTqMHdVJzzzYf`c@ zGuKP__2%S+VL|5l`a386ES3eCgB1H(93Es2R_tSOM3A|GVsDEhgUk&Tds!S6WNxI` z)8gnLbBJOOi(~9}X%&ktjtw$P6^ks63o?f(cDGn&i&duF&9g1naOJL^ZNWw;ckygX zHd49Jvn|>vyvXwH1Y^{tT)0Ht~8)XdH zRvAOKQ^t_(l`&)oWenL-8ADo>F=QuY44I*fAv2XRWR^09%vQ#bR%HyCql_VQl`&+V zGKS1o#*m$rF=Q9z$dH=&7qj-SFYLw8kX<#Z3|Xou zLzXGZkmZUpWQC#(*-cS~?5-$7_E3}|D-~tPo{AWHIaC=#4pYXE!<8}Q2xSa8QW-;zQpS*@l`-TP zWeho18AFa!jtp58&$A|@|hFq69m%~c+i7_=xu<12EzcqMuxzL0x#VKYc3PfCF0yQ=<@x09mc3uo z3DC`fEn#OsR|mF;1%NINY#9pyg$`^Xy8sFt*iv={bar5i*$vRifh}iuK)wT8&>}#d z16$H!K&}Dr;q(CHIItz{3CMO}OWF(2(Sa>#Z$JkJwxoRkNe8y1eF0exY)Sh85)N!h zO8}V;Y)ShA;tp&{*8yZ0@V?HvfS3bY(g6SyBrh{FBNo5I1j#P-rX?PWEXs1D2F8-E zms>PAmhjIegcfbU__An2vMkz&EQ^MaWzkTwEGi|-qG4oNR7RFX!^yH}1R0A)0$!wsbpC+jVy~A$g-%BEQ^}RvZ$FXi?$-mqOHlYXgV2-wgF(#wg4>J4uD151F&cZ z02b{Cz@ioa7VQMUq8R`znhC(7SpY1W4ZxyS02a*wV9{Iv7R>`-(R=_F?F_)8T>x0L z0Dwgc0a&yM5Lr|ki&vW<**96toFa>AT&czO5v;<X02Un%z@j4nSac)+i;ePOifVWf@-5K_?VoCSQ+oIEAiL33lVQA6mj4zAMAj_gN$+GAyvMf5A zEQ`(|%c671vgkarEIOYoi!LBz(S-mkx(I+p7Xz^95&#xm3c#Yv09bT60E?~wV9}KT zEV>GSMOOo`=o$bPT?@dX>i}4EJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2wGMW@8# z&zm6G+j^(`R9Up2TXcIY>3+FIcgGSx^pr*SFup9hmn@6!Bg>-u$+BoQSr$D&mPHSe zWzj=qS@bYj7Cl17qDKK(^cVn(9tU92696oF5`aZd0kG(402Vz1z@ldXSo9nKi=GEy z(F*`9dJ%v{F9ERVWdIhv0>GkI0a)}J0E=D+V9^@@EP4}wMQ;Hji|&lYi|r14_P*X0 z-6f0u@T-Dv$CB=sTl9V`G0r}z8@5FsFupAMkSvQnBFmzW$+GAZvMlxP%c9T8 zvgix4Ec%j+MPC81=xYELeFMOvZvj~J9RQ2I2Vl_;04(|ufJHw6u;^z17X1RiqBQ_4 z`W1jhzX7o5cK{as0l=a^0a)}G0E_+xU{R2f>g7j$v={)3G60c9@5bUgnjqQ!`TNZG zWYLe_7R57??w4DX%t-9lPZo7xd|A|yEQ_+qvM7fvi*m`bD32_Q^2xHO6Im8@Cd;A% zG8Ps7AL9Np%Bj1L`?eD@A&>zQpwy_)mU@u^N}(;K6e)F~Zj|CJE_HWzcXxMpcXxMp z*JuCPzk}htpLM;s*SglaS?fGE-_Oh*Nsh@R843bL9R-T!6DaB=P&B_l(E7?rTeip_>HnB+iplB_D zqQL@1Lj;P33KR_!C|X;fXt+SpIs!%O3KXp;P_({~D_WsN>B|gAwQu%^85>p%MVnmhX@oM zDo}KoK+)j>MMnq}9Vt+Blt9tZ0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(a8curwA0C zD&&f0wJ7bH0jZ8iPZ7-yMXRJ|9ZzdfNxqVzvs#o-TP_rx?fg)5jvb25wL{T)b|^aE z4n-H(q3A+86kTM8qKoZNbcs#Tr2<8l2^3u}P;`Yr(Uk&4R|yndEl_lgK+&}VMb`-w zT`y2{gFw-Z0!23o6x}RPbc;aItpY{22^8HfP;`et(VYTCcL}+oGg_4H&VW=uC}wcZ z3`M)7+oHQ$RFbcx=>8VvcUA~R4>&&*J!prbhwM=FupNpXu|v_Lb|`wx4n>dKq38)a z6g_EE^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0K+($rMXv}Hy(&=jnn2O(0!42K z6ul`>^p-%;+X6-J2o$|5Q1qTa(fdNK=-w8k7At0oTBpZo_l2VI>E87REh@=ZQuIlS z@>1PG(WlN2MW5NB=yN+1ePM^9FYQqDl^u${wnNc3b}0JR4n^PD6n!sH^n*arj{-$M z2^9S-Q1pvH(XRqUzX=rmE>QG`K+&H9MSlqt{Vh=Rk3iAC0!9A`6lH$``K;_}%zmPt zJynx_8e0@7Y9UZm5-4gAC@KrNqK{gXhG#&kH>BI5k3-R*bnm)lsgispMb%PyVvkVN z==@OB#tubo?NHRt4n;LP6xHoe)ZPw79qdrl(GErP*%WmWD4JiOXaRwu1qF&05-3_& zps2Gz(INsxiwYDiCQ!7vKv5Tgq9p{1mJ}#jN}#B#K+)0yMau{jEh|v8oIug?0!1qb zxuRC3(yPP9WQ0r3uNdNP6TeM=Sl6)maJxb;4nnF=e=ZB&uI~4V@Ls4%#6!oz~ z(aLrx>T8FhRqRmI&kjZXZHiVEC|XURXmx?20Rly92owzzC|XmXXplhBS^`Cb1&W3U z6b%(98YWP*wm{KvfueN;iq;hUe172PfmA*x`(3l zR{=F_T&g5rNzrDd@-MwZ(dNz%MO)aRXiGa3ZDog|t?f{>jU9@%wL{T%b|~834n;fI z6pa)p+EJirlt9r=0!5<*ipB^OjTI;wCr~tAplE_X(L{lwodt?^5h$7@P&8SfXo^75 zRDq&t0!7mWie?BD%@in_CFF`WEtMATlPPMOZhl6Dq94kP( z2)Ux&N~Ik$Al1?7wrKZIw0$CVW~q{VB}M0!$_HfsDd3!+qn+pcP;|Z>iY~B2(S>#> zy2uVi7u%ue5<3)KYKNlB>`-*MP01C5#RCl`6?sQuI)%{8;uMfX-3$u=7LFBX%fy)DA_D*`erhI}|-(hoUF#Q1p}? zik`MZ(K9wh&k7VhCs6dfK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1 zQ1rGy(K`Y~?+O&XCs6dhK+y*RMIQd?Qw?!Y9D#=$; z^m(b=c0efl!ug@-OFI;OWrw1#?NIcM9g4oSL(zA3DEi(GML*b~=trBPp9G427AX2f zpy*eDqTd9HeitbEL!jtSfug?zivAWT`bVJXUxA|k1d6gh-<>~fr>H1U)Iy-BBv8~K zP*fHuYAH}u5h!XU0YHTR& zo&l+jNw-C98uCZ_@27j$-5V;&S5nlgp?t=mP}JM`p{S1?idMEmQC~Y0tzw6wes(D8 zZ-=5)?NGFu9g0@BDH+CZRaLxG}=1d28mDB47zXj36q)U%;ju0q1QlRK4fuf@YijEN| zI#!_QIDw+$1&U4(C^}J~=p=!nlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugg8T+yBl zrFAnP)o$s}UGEi&+GPL1Yr{DWmEWiryC} z`aq!QLxG}?1d2WuDEdU8=u;tA^l(Gz)eK1Wru0qhkx+C`dZhnZLnZl2ioR+n|F(W8 z`r7%S=o>o}eQSrJ@9a?Yy&Z~vutU+0b}0JE4n;rPq39QzqF)7yeiJDAU7+X>fucVJ zivAKP`dgsrAAzEO1&aO?C@PfWVLL@dfua@yMJ0iv27#ioKv7G9qKZIKD}kcc0!3AU zqDCQC^hHBykqt6Mx1{fAUxuRj(|5EsuzITEz}U{p?WG-ws8q+M#GQI~1*MhoS*?C|bh~ zMFVY$))XijBv7=LK+#}SfFSVfucc z6dhuRqC@RabeJ8A4!1+m5jI6f3KShBP;|6F(J=x=#|ji3Cs1^}K+y>TMJEarog`3n zvOv)(0!60^6rCnebh<#%83ILT3KX3sP;|CH(K!M|=L!^^C*+FuDVO?WK&n@yhh_VQ zqCe7Y(fQ>{@|6@_TrO|ERVcc|`Jw1iI}}}JhoZ~vP;`YIimtRn(N%URy4ns!*Vv)x zTAQNl1d6T~D7rzQ=thB}n*@q(7AU$!py*bCqT2+DZWk!JL!jtRfug$vitZLDx<{bs zUV)nPK&s!TNBS4}j+VWw;gNDB`AUkOD3{OL zCKNsC{803i9g3c|L(wyKD0jFh@2o$|3Q1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$kwDSM0!5z)6n!dC^qD}> z=K@7v2)Uxi%BA}=Ak}v1w&?Ltv{m|!_GP(}d?iKSmdhV(7mB`fekl6h4n;rMq3B0D z6#Zm}qMz+h^ot#eezilHKy-qwU(9SD=F&Ovb^lbP&A+OLs2I?6wPmkq6O?ww4fb|7P3Rp!geU?Y=@#n z>`=6*P0?ZkMT-j*brC39LZE0#fuf}ZinAUhPTWm7a*plFCd(NKY+ zVFE>K3lt3(C|XCLXkCG#^#qF67bx05plCyZqKyQKHWnz_M4)I>fua!tMVko}Z7xu> zg+S4k0!3R1xuU);ODASPs=ufEMXQ9O-f3*zvXXoyMccP5-!wWD?cn@SG|~=5JKCXW zlpTt8vP02mI~0wvL(y0}6pgb((RiDp2?9kE1&VeSDB4A!Xp%tDWPze70!32=ilzw^ zO&2JdAy70^plFsr(QJXDT?LAE6DZnUplA<)qCEwQ_7W)CTcBtkAy>3*%hKx^km^0@ z&lhbMimpmeWbfOul6)ma2evH#F*Xz(FCq38%Z6dh@Y zqND6kbhJ&;F#<)$3KShDP;|UN(Fp=YCkhmuBv5p+K+!1zMW+fBohDFpxAQYv4q`BdumX+iy zDY~p>dEkUlbh-0G(G_+my3!6sSJ|QHYC9BNV~3(^?ND@`9g42EL(vU3MK=l*-6T+S zvp~@;0!6n96x}9Jbh|*&9Rfvn3KZQXP;|FI(LDl1_X-rLfuc47MQsI&+6ffZ1d8ecMeT)L(RVFN-)BIozo(m@??X|S^c}53 zrILIlMe|q6?WcyK1)Lv>7PLdrLUt%x*bYUV?NGFc9f}sUL(yV(C|cYOMO|!)mJldf zQlMxlfugPgMN115EhA90tU%Fn0!7OU6s;gow4y-KN&-dQ1d6%~6!j1&>M2mvBv8~# zps2S%Q6GV#l?96W3b~^BDy6;|km}~?k$$I2{z!k}^hke|N+tP9idL(Xx11h|R(F0V z8eoT_HSAC{&<;gw+M#HW9g5bnL(yP66b-RM(NLSBVFE>K3lt3(C|XCLXkCG#^#qF6 z7bx05plCyZqKyQKHWnz_M4)I>fua!tMVko}Z7xu>g+S4k0!3R16m2a~w2eT~wnDC` zf2Fi{2Bi9KHXBwAMf0cIqU|b`$L(x%oC_35>MaS5o=vX@x9cNQ?yg<K+!n@Mdu0>ohMLqzCh6h z0!0@J6kQ}xbg@9uB|@&~ph~ILu9>0>ve|HOD0(j4)xNY+NxqVzD=X#YcMnBZIX@I# zZHJ<3>`-*A9g42AL(%niD7wK8MK{`^=q5W9-E32Ii$Kw>0!6n86x}XRbcaCEodQL7 z2^8HeP;`$#(Y*pi_X!l;FHrP=K+%H&MGpxSJuFc4h(OV!0!5Dr6g@6b^n^gslR~cO z@=9sL3`ljeQU>RWP;_{@Eqba_NxqVz=PKo?dxoOtoga!`utU*{b|`wu4n;59q39Jm z6uoMPqSx$D^tv62-mocpQ=sTAfugqsirx_@dRL(6J%OV41&TfpDEd&K=p%umj|GZ8 z5h(gppy)G!qR$12z7Qz-QlRK7fugSkioOvj`c|OmJ0Vx}Or>;k2Bi8{QuJ&ndL-Qz zeP5|0UrEu=mGUinhoWDcABujpL(y+`DEi$FMSs|#=ubNo{bh%uzwJ=;j~$BswJG{f zps3I)9=20d6ewyTP*f5qY7i(Y3ly~!D5?k)wGt?5El^YyC~6caY9mn8R-mYzKv7Mg zs4h^{UZALhKv745qWOee(T|nVn;DSm`RQ55pF+{8iBzXnmE{ik7rP(NZ==T?LAk7ARUqplDfvqU8jNmKP{m zL7-?wfufZJin<9Dbr&e=AyCv)pr}cpsFy%dZ-Jsd0!1qe6!jG-T1B9!pFmN6Ay>3O zt5TQ!GDQ!kpMWgbDu1LuEPY2?wN)kgN{ZHKRUULeC>rSeP_(8UiU!%CXe~Pw4Yotk z5IYnNwL{S`I~1*Lhoa#&Me7I@tt(Kpo|0K5GdMGplB9f~H{p=hEVigva`(Jpon( z1d65#6ipK-nl4Z@L!fA;K+!CLqS*pPy9yNTCQ!7yK+zroMSBVq?IlpOw?NT80!8}@ z6zwNaw7)>n0Rlw_3KShAt0z(ix2hyxNzvi0%Fi4UijHu8 zC_2&(MMv48=x93>9b<>0W9?9MoE?gew?okhb|^a0rsyPrqLT%RP7x?NRiNlJfuhp| zip~%yI#ZzNEPv6%(Y4MGMc3J(=z2R8-C&2J8|_eZ zlO2j~wnNb^b||{l4n?=w6x}XRbcaCEodQL72^8HeP;`$#(Y*pi_X!l;FHrP=K+%H& zMGpxSJuFc4h(OV!0!5Dr6g@6b^n^gslLAFg2^2joQ1pzDE4r#xsb2=9x?wgOt`0>< zr|)RbwyGpwNzsd~%3B{9ie7SlD0aBh8>FDv_sKbb|`w= zrsy4kqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>n1&TfsDEeHW=nH|OF9nLe5-9pw zpy(TcqHhI?z7r_=UZCg)fubLUT+#EbO8aI&vY(=5a9#*Si=?~SKeehPUrEt#t;**e z9g2Q;ekl6G4n=?3q3AC=6#Z?7qJQjA^sgO?{;fN4@E_rq80*0C4r&_fugcN zQA>fMia=2-fuhy|MOA^KMuDO>0!3{FirNVj)dY&_0!8fwiaH1sbrdL?PoSuiK+*gH zMGFYIqF-8-9?pPNze+bhzlNd%(^#-|CHYE<7HM7n`=6X z9g3E;L(x)pDC%m5qNVLnw2V#BvI0fR2^1|aP_%+T(TV~^D+v^J6DaB~P}D=9sHZ?t zlR!}~fui05MSTQ{Ru(AgD^RqGKv6$|qW%I!s|pmYCQ!7xkSkiab*Xw>rs(398Jy0o z^GEuxr!k;)CHYE<2DL7)ctR*z%lV;bupNqq*r8~s9g2q8p=fP86b-jS(K>c0TGtLm z>)8~oFHp3BK+%Q*MH>keZ7fiwy5^_ZYTbDM@fK*>fH$Q8JqLt=6U~64TzLKJGt;^F- z3Pt0cABrZ}p=hEVigva`(Jpo~2!SVXZ64S5kCT>+)@(bj9km}HE zHXIp>PEQZ}uWnsQzLKKrTbKViEfn40{7`hG9g1$UL($E4D7wWCMYr0a=r%hP-EN1X zJM2(&r%lma0!4QV6x}0Gbgw|seF8=I3lu#dQ1qZc(L(}74+|7MB2e_GK+$6YMUM*< zJt0u^q(ISA0!2>?6g?wQ^sGS9a{@)r3%R0eTbGtRJyUc~dZO{VP_%k_jP^q7O7fKy zz0$fo_{>oBs`Eq9Yj!Al-3~=>*rDi6I~2WThoZObQ1p%+ir%$D(R(&U?+X-tAW-z7 zK+#76MIQ?keIiiwsX)0!8fvifRHyb%CPx0!1AJiaH7u%_mUQNuX$cfuaQjiWU?oT1cR1VIf!ad+XA* z8IbBW>3-24q3H5-ThzH)NxqVz#jEA#&J9IfoF9soutU+3b|_lP4nE{ecwUquU$Hl7oBmIxkZPA+5 zO7fKy4XKtpT@Z?fIzJQ*vqRC^b|@NdhoW`tP_(Wciq^A3(fW2M+Q1G)8`>0YBv7=m zK+z@wMVkr~jSwi>OrU6Ufub!0inbIe+Df2kYk{I|1d6s5DB4b-XnTR89R!L-3KZ=q zP&7)QXeWW9(E>$dgj~^D)zYdNkZSsyiW&xoqASuETdgEtNzue=dE1LZ(az2fMZ4Ic zXp$X@CflKCiXDok+M#Hg9g3#gp=gF3ie}mr%@Qb@El{+pK+$djMY{_W?IBRKr$EtO z0!4cZ6zwBWw68$XegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXwK+$0WMTZL%9U`-)~9g0q}L($20C_2Rs zMW@=K=rlVNoo-WfhCtDo0!3#D6rC+lbdEsLxdKJ!2^5_#P;`Mn(S-s<7YP(yEKqcb zK+&ZFMVAQ_T`o{`g+S4j0!3E|6kRP)bd5mKwL-4w=xXWF3`lj`^hDz^p{PrGq<>wt zl6)maH&x4@T^5RNc77|P;{pqite&Q(cN|^y2qyIUV)z7;6?PN3*}fubJ-ihdL*`bnVZXMv($1d4tYDEdvH=yxGk z^lG)VX$GV^JHdG^6z!e9z5P+GBwtCHuitlA4}qed0!2*%MZE-ydJ7cw5hz+&ps24v(JBH({RE2o3lyy?P_&vr(dq(40|biJ z5GWcbP_(8%(IA1MwS-(zm&Ve&8IbC*^sM6&jrk+}yVGsa;KoYwl@zVrSpM(&P&C~6 zp=cdD6s>EAqV?=hw7wmRHn2m{hIT00$PPst+o5O^o1#qxibe<&Z6;8(xj@kt0!3R2 z6m2C?w6#FdHUdT43KVT8P_(^3(GCJdBL#|f6et=cP_&ak(P)99F#<(n1&YQA6pa^h zMME1)U2n(~bxuD485W9;%3jtmp|O&DB}J1O%R_GpMU$N$il*41XsR8GrrDurx*dvU z*r8~q9g1ezp=h=pigvXr+D)KncY&fk1d8?)DB4S)Xm5d{eFTd36)4(IplE-Aq5}kq z4iqRlNTBFofuchMiVhVhI!vJGaDk#D1d5InC^|}@=x8BVv~y!==L|@7@APB*T|&_( z>4xc;#!B*)6rIpmKI)cGbfWV^(MfhFI@u0Ir`VzBR67)%W{0BF?ND@v9g5DhL(y3_ zMP~~Xog+|mu0YXw0!8Nw6kQ-tbfG}eMFK?^3lv=E1%P-s( zif(g$D7xJaMR(Yt=uSHn-DQWOyX{bPj~$BcwL{T;b||{vrsx5Iq6YeSfJ<; zfuctRiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq89~p9|Vei6e#*hpy+3TqF)4xeibPCO`zy^fucVIivAQR`b)?az0p`&Jp)qxF+J<} zW+)n$Nd4VdNxqVzLYwmTcZZ^4n|LH2idxvAsAPwt20Ij$?NHRx4n-9^6t%KLQENLC zRc(qI1&Z1T6txv7Y9~-s6DX<+6tx#9>L5_mQJ`o(fuc?VMe_?3Eg(>|pg_?=0!0f8 z6m=FTT122|QGuex1d0|HDC#2QivDdZ9hd>BPEUVg_PL(y_}C|ceQMJw2$Xhk~|tz?IyZgwc@Zik{CHbp%Jikbw9dI=Qu7AWc? zP_(i@QD1?gRRoIq2^94gC|XsZXf=VN)dh+M2o$X$P&81WXib5lK>|f<2^0+$C>kPA zG*rkHE!C#$d1d7HA6pa%o8ZS^ZL7-@&K+(=Zu4s6hQo9E-MdkFP zvvopI`U__oc4<>dzLKJ;ZOT0!3PsbLABv{ip=gF3ie}oOXqFv{X4|1?S34B#W{0BP z?NGFbP0^kLMSBSp?JZEWk3iAB0!8}?6zwlibbvt7fdWMb2^1YHP;`hu(V+rGhY1uN zE>LuYK+%x`MMnt~9W79Fj6l(`0!7COxuVH!N}FXss`sS__ftaA3uzqRrjmRmMJKl@ z&weBno#OmZbgCVSPP0SN>2@eO!wyAf+M(zyI~1L5hoW=rP;{}3sawy7jvNzuD)%Ec!`(RUzL^e&pFmM3fui{ZiWU$kT2P>9A%UWW1&TTg6fGi9w5UMQVgf~r3lwz` zC|W|GXi0&hrG#8jv2AHm2Bi8zg43dH{ur%e_OgbqZ7a!FQnXy#@-febqUD_*w?!-1 zp=d=r6s=^3qHcC5>TZXk9(E||X@{aFI~4V@De5gy)JLFbWr3o;0!6C`6!jA*>Mu~V zszA|d0!6C}6b%q4T0@{{pg_@@0!4!aiq;Y+8Z1yWM4)J>K+!OPqO}Ezh6}l(W!jc* z%z#vvPjHqEMTe$uZ|k(JBwtC<25rkPJs*lTbbct>$PPst+o5O^I}~kdhoTX7DB8>p zMVs59XbU?OZD~`ql|a$f0!7;h6m2U|w4FfF_5wva2o#MJDB4k=Xp}(FP69=v1&YQ9 z6pa-q8YfURUZ7}#K+!~jqMZebb`dC=Bv3S2$Q7;Ew)A@jqo`3W-JEWVPHJ08zLKKT+LlMY5{gcDekeM_ z4n=3$q3A3-6rF8{qI2v}bgmtW&a*?&`F1F}z^3Rzfuf59iY^u?x(dm$N8b?UON=sXNRKu?NIc99f}^b zL(xNaD0fucVJivAKP z`dgsrAAzEO1&aO?C@Qpz2j&zNgP&A)FQ73_- z`2~s=5GYzuplBh1qJ;&DItvsnB2cubK+$3XMT-j*brC39LZE0#fuf}Zin`>Ip4n@7~P}Ii`MJwAB^%W>uMWCpkKv92zqE!WoRud>%U7%=yK+zfkMFRzj z))XijBv7=LK+#}3Pad?iI2w=3WCekj_+`Jrf2I~0wuL(yh-DB9c(MO)aRXiGa3ZDog|t?f{> zjZM+E0!7;i6m2h1w1Ys=NP(gq1&T%q6zwEXG+Ll&j6l&?fueB&MdJmECI}Qw6e!wR zplBC?qDcZplLd;V2oy~fD4HhZiZ*Ol`Y;1hT`T>$>y1LuKIz`|^mdixD=C`Yu3Y*k z6z%H#P_&yJigvd{(H?dv+S3k2d)c9AZ#xw2V~3)B?NGFzP0{`WMF$8J9Vk$AkU-JF z0!4=i6dfv1beKTV;Q~cR2oxPDP;`_)(a{1$#|RW1D^PTtK+*96MJEUpohVRrl0ebP z0!60?xuTivO3P(Hs#mAmqFJG+A>F$^wOu9oN{Y^GS6=6nP;{2_L($oGC_2XuMd#X~ z=sY_Voo|Pt3+zyIp&g1YvP03uHbs{R6kRG%beTZW!eVA^G?rK*_zLKK*+Le#{EEL`E{803O9f}^bL(xNaD0=6g@3a^o&5!vjRoW2^2jqQ1pU8(Tf5_F9{UAEKu}{K+&rLMXw1I zy)IDnhCtDq0!42L6um7_^o~H$y8=b;3Av(s+Ldn3fK<;fWpM5dMdQ+Vzg;EyN{T*i zSAOM-Q1prOL(!*pDEiC}MW5TD=nFd(eQAfHuk29twH=DSu|v_fHbvhF6n!sH^n*ar zj{-$M2^9S-Q1pvH(XRqUzX=rmE>QG`K+&H9MSlqt{Vh=Rk3iAC0!9A`6cuXmu$`i! zKv4^UqLM&SgODrwuwCiT3`liQg7Z-*`YDZat&)5tMXhV)&R>V3s`EopqaBLc*rBMc z9g5o7p{QnuqPiW5+S{S1gB^-G+7!(vP}E7FXnujB1q6x~6ewCqplD%%qRs+EiwG1g zDp0hTK+)m?MO_4nmJldfQlMxlfugPgMN115EhA90tU%Fn0!7OUxuQy~v}OjRdTsg% zNUK`@NWXJZv_h?td?iKQYvobjhN2$M4@EugP}F3HqF#0=>TQRjK6WTt*$zd0?NGFe z9g6zd6!jMH6b%+A8X{0MRG?^>K+)O) zMZ*P())6RLSDs$=?qBqj`XMZHw{HI(i7RUYL(`=779f}UHL(zdYMF$BK9V}3Eh(OVy0!4=j6df*5bc8_Bkpe|W2^1YI zP;`ty(Xj$W#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@6rC>QigvA)I{cI=DwH!g zyM>}f)5HEVYL(#R zq3AN3qRRz}t`I1?QlRK6fugGgimnkTx>lg*I)S3=1&VGED7sOg=q7=pn+1w)5h%J< zpy)P%qT26(^XNRKW)3>*KYn9|HDSEJ0 z-s87W^pNvI(ZhBqdc+PzkJ_Q=F*_7JZik{L>`?Ti9g3c^L($VVMb8KnJu6W3oIug@ z0!1$f6ul@=^pZf)%K}BO2o$|4Q1qHW(dz<5ZwM5`koSpGx z3Kab%Q1rJz(LVx3{|XfSCs0(V$HR7tiULI~1d2)mMGXQ)Wr3oW0!0-eSM*7(^l=8H zdRO|6_Gu_OB;6LZs#lV)q^M23T>d*0wRL_dYG;R{njMPjb|`9ZhoTO4DC%g3qWSDl z)X5G-^V<|HAW*cRK+!@1MGFfQbrvXEM4)ILO6Igh0`f0!2#+6m=CS zT3VoJ8G)i@1&WpvC|X{iXa#|y6$Oe`5^_b=dTE6WNcG#+8Jxy?{z$)`?p=4QSCX%! zsHt9F@83|=%lVJW;plA(& zqJaWMYYG$%5-3_rplGl_(GY>6p#nw21d7%cC>kzMw2na0x&lS(2^6g_P_%(S(S`y= z8wnI`EKszGkSpp@FHOsUR41j|qMo6sL;8-kX}ywsB}H4*%O@1l8|YbR*wXo-Xe&Du zZEc65ZR}9AtsRQCvqRDLb|~7x4n-sFP_&~>(I|nUodk+T3lxnJC>kqJG)|ysyg<gCs3grdEjABy&|L(#r=DB8~sMf=;K=m0wu9cYK5 zgX~arupNpHu_-!Kpy)7xqQeD>ju0q1QlRK4fuf@YijEN|I#!_QIDw+$1&U4(C^}J~ z=p=!nlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9Ay>3Vz4Uhmq`GT*qH)hqR7tl*XV)vq zS5kC-y}W4l*Fns=ExN$@q3A+86kTM8qKoZNbcr2`F116^Wp*gK+zv%o*rDi3o1&`( zimnzYx<;VrT7jbL1d6T~D7rzQ=thB}n*@q(7AU$!py*bCqT2+DZWk!JL!jtRfug$v zitZLDx<{bsUV)`?T* z9g2RiL(z|RDEi3`ML*jV{UT8Gt3c6j0!6|Kv7wssHH$rMWCpaKv8RfqN zC|XgVXeEK7ZURN!1&VqIxuUl1OY^nK6m6OQsCB#c`6K-=(rr=C_Lbx-DeBX{ymGrx zw6gO`6s=)XG*F;uO@X380!3>H6b%+A z8X{0MRG?^>K+)O)MZ*P())6RLSDHG{xbwIi;+A0*a zNZ--+Y+p&flA?Xvmmla5iuQAUDB9l+MF-fS=s-IZ9b|{1gY8gsh#iU!wL{Tib|^aB zrsxQPq9X;0juI$3TA=6{fudstijET~I$ogY1c9Ox1&U4*C^}i7=oEpXQw54n6DT@e zpy&*NqB8}G&Jrj(TcGG1fueJTT+!a`OP^*ys^_JfpM65n-)WrJzLI<;MHjU%S2~5F zi=7{eF0n(=rFJN~%nn7D+o9+RI}}}MhoYlg*I)S3=1&VGED7sOg z=q7=pn+1w)5h%Jum+K7pe91&SUJD0)z! z=pi9jbV2*lN*R#qrs+@bUl@vhOFs^IxP2x0N{SwDU*2GWQ1pcJL(!9VD0<2cMNiwI z=ovc{J!^-e=j>4Qyd8>OutU*{HbpN96um4^^ol^ys{%!@2^769Q1pgC(VGHAZwVB= zEl~81K+(GbMehj|y)RJofk4rR0!1GQ6n!jE^oc;xrvgQv2^4)U)z1@J0Jd@|6^Q)4qJtLZRqe=ZB*2>`?T*9g2RiL(z|RDEi3`ML*l2=odQ_ z{c4Az-)xG07byBepy*G5qQ3-+{uU_uN1*6mfujEeiV7X#VLL@dfua@yMJ0iv27#io zKv7G9qKZIKD}kcc0!3AUqDFzDHUdR$gq)r2lG$r=fR;O7fKyt)Vd zYKNlL>`=729f}6np=b>|6b-aP(VBKB8e~(nmO#;9fubP-MMDLOh6xm{El@OEplBU| zqICs|))OdNU!Z6MfuaosiZ&7`+E}1y6M>>l1&T%p6m2F@w7Edh76L_E3b~?{JCufG zK&mSyIDJFWzUj7Ts}7aqD=FHpLwRiWFA~rBIokHl4@EoJp=hKXigvU^(I`6kP(2o#+uP;{0+(b)n; z=Li&?D^PTvK+*XEMHdLUqWwCQp3i_(Kh0*t{-Nl*G%oB=Nxlm03N0FzYTbF6Vxe|f z_9NRu?TG}gmi|GtR<*X-qq#P<9@$;a|UlDHPVMowi(| zFr@a*3WdV(+EU#Lh4pI_dlU*A*RE?S6gI2<(z{UDsOsI_*SSU=YoiV6Tm{xmlaG@}(w)C(aB^+)tqO(HYiDg!D4bpUV7o%${Mxc33x$holSdT_ zm)C9@T_{{#`(tdOaD8pyghJuw+95j^3b)sunp7y*?QAT)kLN|0v#?#d`Wz&4v`~>7S(!esu|FXws#d`Xu8MZ3c)8DPXU9q12a`YXG_4Kz}k15vEUr#)tSWkby z?4)8n{RN@ZiuLq2JkBcC(_hiId$FGWj;{9--**KQXV>*+sNy1ZCV|Gml8 z#d`V=2CgsG)1UahxmZtsWcT)BJ^h)>yNmVohvx1t*3+MQdbn6me{ALPVmH)i}m!Azn6>k^rM^Ci}m!}``g8Odh+!BVm&?k^>MMDp1%0JSWk~Xzb@9(1Bma7 z^>h#L=VCp53;(@XPq)E;7Ypq>r04c8&cEb3?2~;p6?Jk6!u+kW)6)OSOP8vJ zV*BFK?K(D=+I4QX`2y`THHAWpu7$?NHL_GFl;$s#+O68ST4VplbvkAjLcF9^cJj)F zR9bc{Ha6z3P|RkfZK2f4>o+#GZEVxnFZ(Q8E$~0D)jE5vdERO@W;uT+jqxV4ncifZ zc$0Hp+WaQl#+!`SYL}f<&TAiEa^F0}eWQ`*gW zJJ}n~F6TwE|D~JT?6R8k|LOk{lX-v5yI07rhf-lwc1nxlU+vl!irKI1b+IjzUc8KZm57&&wF*pbs_Or14$^sKRCdW@d2$Fx~fQy4vV%B}JXHDF7Y@x@5sguX{7&U3^?mfCsnmT&aq#iRTjG8gF$BeO4#?Blyv&Yz8 zBWKQ&CiiISIkNZ2UOjs?jcn?fVz(@In=*CE z*luG-?KH7lQ_t?byQLR*&tCjLFX}OI%IHb6$BgYUdDQ3$6Q}%t{$b4AW9Gb<#P|t4 z2F(~Vd*YO-gQw0I+imV;vHPqUb1stn64`jh)Sa`-d}fak(?-qMW!UT~BR9)Fm+>1< znmu#mri1!!u=4+nt7+F!v&N=Nt5Aq5x>x^M-A5+}Bgc##H){5zStDodF>UP3?h_KP z?7A8=amuW0WPC;p9y&7n7)KADI(hQcDOtbt+sX1Anx)>wa=GLG=~ubf zvNXO}?ojI7Wu+dAm&+}ClsmM{PMCXKGP`F{>{M<{hg!KyI%F@OGrMH3)@#nIcg)UO zVu|t+JktRF7{|q$-Xu=9lG|&VLgWz z(y^&u&*39?%75Fp&)naxJb3PJ`}T|1?9)#hzmlOKVeXag;KBn1IW=AH8Ot-P1!qh!m#YE{olM9 zaVwPLOxMC%%^y;Bk!J6A%tP4MQ^#$;b&o6Q)NU6ZpWPMtDhc5X7^o99ON|JF^- zkg+?>9$(0ApQnr;J96xlF%w5k898a{l=1mRk!i?2(Ch|n9uDzI^lARQGJ5%|&%GcR z@7a7g^q+fqHDzBuh4qGRJ#x^HP3N4Ksfr6Q`|63`4f&rl3+Y4ZGUxyP|AaR+e;{iG zV%D=Oe9k+7JMo?KrJjGWq~8vmbN0^Z3w6$mdd8c`zHZ_pS!?dclx`vBywafN4{iuG zz2jwb8F}YT{pP-@re>*Rfz{MZH~TE&UE?$tPIhCIe*(=8n=*)b>*njpr{K6d!DM zCCBMmiQmorj52`vYiGB!>1J$3e(^NrhxnG;%%Z8;#axQb9J24`+1sBvVd{)obH9OR z>gK$IL~YKsKlh5C`>j6vdYSVo>B^ZyDZ5zm-^^p7`MPgvzVfqMexH%6rYZYi=bW6~ z7npN&(Kls~^S3(BHQRheX74;Mo2KmEOa6-47i#=w?nT&?U(M;moaYv~DbC2Q-sTH9 z``y|bZr){Z|NdRlJ@W2NUDAE>p8b0D>9X96v6IG*nmKm)F5M=No;G{H=?vt~}2rG`6Ic>#p)4FsU-=*6|y}ESE?w1Z2oqYh^#!VhObLOb=W4lcnJ7xT= z2?Kg&DZi`JEnVx`8aI2&==2S<+sy3Fb#|PYwd`BzsJT18D6;SF`EQ!-HZ|i-F8@#8 zW^$kNd@G!5FGD=%Z8qO+Od8W=+}EMWtmbPdS3dXq+#J*+NB-|O zVRu@a@3Uf)?i6h_Y{cAeu1)TuHs9TBzL(j2Co{XdickJkkUqS*j@?0RzVA5CT}Ss% zo9`$3f=G8A^9v>*=6C7leCFwnY1~(x^BLw}b#p&!UuAPGqnz%b?lSil&}~HXUAyLc zc2Li~#^>H~oO_RO?w!ARzIvL!2Ac1>xq{=4TXxaRz2fqFe}%ON4_>v)a_Q@3(2U7l zhECpT?3gjx-SEvk_?`15{)@m+hxyHWX}uC{goc*4{BFG zsNvw!AuWzA76$dt!l?9^xlrtp{kGh%+Xme?7_`oYg_i9r8?-J}TXkrduh^-$Kxx6^ zLdAuPor{YU7i+O(v3q(-;Q#S!-qcX|;lFubTuP4{=lNBNrzE6Ode}J6uTu7qF?+IS zo?i`x_Sss0ZfSlpBc)Pd&eLCWUs_84Ugtc&N`>tC<#~RU3hAkl=3k{k_MG!Pze>zMx+_uw<) z|Ia(v+1p<$`(L#~_M}&KY>}QqPsi+2Ngr)Gc8cRd>6m@WOQd7=O3Ou0*Lixq>{;+R z$LzW9Imh&NQ{Om_o5wMGHegQQIgZogxL+I(j^puhyeN)0WDoPx+q)-@FJ)I>+V92j zm+TWryO=$*n2rl%pG!I}702{UR@y`3xNY|Pw8zKs{OsyV`$#>g0 z4$H34^!g*>cyzyfpAp9wSIzf(aa=IF;?wId9mgF8=6jboUOXt@H^lMF!TJ6zjy;Fv zdq5m_9iH!l;&}JE`F zavU$+Cf_&3@$2pK{YM;ojm-DJIPN|w--pEU-VA!WJf4bU!?=96kK?)%^1WpokKZ}p z=fv^VN%{ULj*Cpq_wsSvX?nh=#_{r*`MxEN-_FkWUvccSd%g$7anC*TeOMgt-#g#W z#Ifam`R*9U^$*DR)^R-XpnRVf$JY6x5e@MWApt_ z9Q&S-@4<20`=opy5yuBl$@g<{Y;}6RJH>IsGxNP|98W$w-xtL3&2#hpSsc4ukne7B z9CuN^XU6gBOY(h39Dlql-~Yw2-U@9pDw z>Mi-cD2{JuKLAUfzKG+Jcjmjt|Btb|j+3(f|NXzaGs7%9%d(V&q+*~*i`axBjbdRE zieiFbK>r>@jIk$Y=XkPiaRUD6fw!F`b<8$-Ndtn@FUo7v|aUAnAITEh-;3SzJC2jpM8j z%X@YlpZ~bL--=`1XXU+W9Jl+TyeGu*(yz+ZU(8+wOdtPF9P5{tce^<5u%f*8h~wqi zBZKtux5V+&?3Kc_e~RPU*;CLGv7ss~Qi+yQ#iDQp+EL2o%9(zO_cZ%a)ahx8< zW8-*c950RIO>w+0j&tMqY8>BB$L!bnF7{7xY>*z8RA(>7rDOK<=`9_zha)SGQ`6&= zY-bM_Dyr(Tm%yV}ben$I0W&5{%#Jgrm5-CXmtDWksOXk17%RF>oIbsxTXu=tEyZsC z@6Xe&JZI1JjB54_`d(AAPq*^@2@@wyn{;sbGe*gt-rajr{37M_f0zB!3taIjvRhfv zZIA2)nMv96`v3W5_L?@~fb4??j2YQ&!i*Wy_L(?yM)qm{U*EEaN15pI zd&~Yau6*m1{WE=Bt~~#*k4rz7-qy-~WWO!{zaQ5l`-ogWDg-L z`e#4V+g%$~uKfJz_ceV?`jLLUJ+mKfL-uaP8QG6znH6u|8=r;$e!hpY&(|Xh>GLI1 zKHt>redlEFR-CX_WyR?K1ni@Zx8j%V^Cjcn{9N{B`G5O-%l`BE(v^|VcT@JhbJFL?b*ZfA<~Q*_KX+aB{(o;@ z^%no%f9LFf_W$$w?u~QO?_YZB*|oA_Xl?oZ^w0Ebr5{hk(Z?O$ud-rT*1Y++m$LBR z+xJZNaq0KmTl)7%Z}YPs|Gj%YmV7+#NhI4 z`Q=YsnOz0?ys7jUv2qpqto-SoV?wUGp+4U9kmOWFy^Z13!@|`Ny z`Fqi7lk@A%TUOC&;^g$tYghjB)0O|+<-O|%KQK7ox%cqwW3!v|_oBti>N}>7TD+`z z99zY)?aJfW$pb2uzqK&?h`Ocqb)%NmcTMl-`;1yvyYjso298=*z4E=1zRNXhF?87EG1+HZkbQA z{Lihoow7@A`J3tA`th%q3@8n+9acNE(U5FE*?Vwp$Lh}cH5PwW@#H&AI$pD=(ZQRp z-gdp#C@{u_l6V;4O2%Gvjie;~UbD4Wbz)@3+q-^{+q zZ1!JC*?;`1$_BI2b#7(#1vS~Bs*ua>qN=KjXJs+BO7@#nHL}&n^l|w@yXX?}6IWFi*T_`m^M&+eSXI8bAp4M9*X#pwU7HO^?_Zn!(zzbZx69ry z%ueT5Hh8?4-Ie9jDCYBP7VgMCqB{M3U~9#n@#v7vo)!7EW46y`uZnz^nC-IJJNrB6 zW46s^pNjmtF;~sz`W5-EG23LbZ}!*N#cZ9;4Jz{8Vz$a=zlwbKm@TupVfH8CW3H0T zp4rXn8M{T=+3o5TyLsB#4eK4dS=!kx>l3?a+SyH8KX#L}v)k4;c758}joTo0;saJ;f2>S&?|+Eh*Lwz$e1By zRLl@EI%WvjI%WvjCT0j36ElQt8#9D#7c+!xACr(BViU4sY(mDyCS<4BgzOxfkX>RE zvTJNYc8g8O?y(6O7n_jru?d+Fn~;gI3E3kyA$!IqWKwKG_KHo&-mwXp9Gj4RViU4& zY(n;nT^2Glw>10xuemLI^phV}7BVHfpUUrFOmdQtsfDH4Pp%YlP@EbzY(kEXO~^5^2{|@4A;-lg zWL9iKj*m^q39$(|F*YG5#U|wB*o2%Cn~+mu6LMN?LQaoO$QiK-IWsmPXT>IDc5Fh< zj$IaVV6Itqmr>Iv`?8atQWo-VMk9YtG090nE+{n1z80<&a$%erLN1CKLN1OOLN19J zLN1LNLN1FLLN1RPLavAzLavM%LavHQ$knk4xh6It*TyE~y4ZwVADfUHViR&>Y(j2| zO~}o$3ArUUA-BdR#wO&h*o532n~-~A6LN2CLhg%A$o;X) zLe9&rpZ)&V%u4qm=a+^2nBIS&nB*iOj}+F=?o?I^c{EN9A&*;{UXM-4g4l$-5u1>Ou?cxIHX(1tCgkndguD}*kauGf@?LC07R4?Lc__DI z_WNJcD0{e@f4D4Ulk}M6{bG`ngnU%kF}u)QDdgigHH3T;GlYB^GlYB=GlYB|GlYB* zGlYB@GlYBcuyJ7hb1*xSHvpY7~ndC_i{ z?d)NBwcR$`*~9XN_Nv*=9+ubGZL*y`EHBxuvz|uGGy-K#z zbxmWTMGDz1tQVT6kln;4LbDXI+t^fSnnHFXn+Z))$ZlnGp+1G|X0{L-r;y#wRfM_} zvK!h`Xp};BOIr!GSx8qnt%Xtw*)44&)TEHz(p80qDP*^_tx%mpc1zm{#T2qz+Fodo zLUv0#2!#}~TiQ{`r;y#!PD1u#{>n?8)r6`nq-&kkg~}ANTiRL3fYjylRh7A?G9abf z(!-NnWm!@BPJ#RymBqv>De6*L_#}I}W~HKaoF9tTwL?)?I~1*FhoWwFDC%y9q8@fA z>S>3fUUn$zZBx`oplE%8qP_w}8weEj6DZnHplBn3qKyTLHW4V=RG?@xfuhX?iuwx_ z4G<_AC{Q#=plAz$qAdlA1`8BzB~Ua(plGO2RyQMLP== z?IKXLt3c6i0!6zE6pa%o8ZS^ZL7-@&K+zroMSBVqO%f>DOQ2|PfuhL*Mf(U8?JH2U zpFq+60!0T16dfp(6^*FOjmUtM?#pI=WGEVuNKL6MCSOU>^vc2ktAwH%&JRU1?ND^E z9f}UIL(!pjC_2mzMTgs==mXLW(gD>FHm%XK+%Z; zMJEXqoh(pvia^n+0!60@6rC;=x1_eGaDKNMYRhoZ~uP;|K+imtFj(Uo>6 zy2=hkSKFcJ8aotSYg2TcK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellY?E*!22o%i` zD7sUi=q`bxy9J8w5h%J>py)nm^pj4IaiyjL_zo%yfKddY!UrEuYm4(f-@3CBY zU-X&tL(%7UDEh(T^%2gGUucWA0RXDLjD5`dTC~9bjq8d9C zmF!SdYlosnb||W|Ls4Tp6xG|IsEJKcQ-Pvp0!7UQidqO1ts+p=QlO}nKv8RfqBa6W zs|pmg6)0*aP}E+asDnUJM}eYF0!6C{6s;~$)LEct4Z(fUngT^@31vlvs@$y^kkU!% z3B?9gDOQ2|PfuhL*Mf(U8?JH2UpFq+60!0T16dfo~ zG)16jszA{}LRr!1s$Aa;NNHxeFWNd3?UKHtO{*#aMP7o+MQK0A~fufTIicS$I zI#rbgdnV zuCqhY^>!$_!KUa&fufrPif$Gtx<#PqR)M111d47KD7r(SXpTV9odQL72^8HeP;`$# z(Y*pi_X!l;FHrP=K+%H&MGpxSJuFc4h(OV!LRrxzRk^1#Af-zyGdP!qqHWTB(PLG` zhoWcfQ1q-Fik`DW(R@1;J#UAi7wk~g+S520!7*PAzzmLHfFD=XHV6nS7R#$imC*P zasowpfue#?R`gj_Zd3-OG(O!IeIAPbN~1xpn0zHgHMzo+?xCpU{7_VDhoVMyD5|qV zQDZw4)!U({i5-fX+M%eK9g3RU6txg2T1B9!r9e?Dfuhy|MQsF%Ruw2}D^S!Rj&p3`l8Q`gWm) zx$>3%r|G_E-CQyGN{YJY3itO6MLnD!ihA0isFxjzdfTC>j~$BEw?k21I}~kThoXLV zDB94bXd{85jRlG}5h&VJplCCJqRj=0`U?~d5GWcbP&7!OXbXX&Ed`1O3lwc7P&7oK zXsAHZFoB}s0!1SPibe_)jS?stEtD0lm&+~6fRqkT4~4pgq9y6RXzN@t`AUkm%N73a z9g4Phekj_(4n;fKp=hifigvO?(av@#+QkkH#-#VZc{W)plG~6(FB2_i2_A? z2o&upP&7%PXfJ`Hy#51%_xnlB_6djf;4Cot*4tIViI>HV`N7|w2C_5A# zZHJ;`>`-*99g2>#L(wcd6di9(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaK+%~3 zMP~^V%@!y+TcGG1fueH-ip~=#I$xmZ0)e6n1&S^bD7sjn=n|o<=#X4)uM9|OXu2;t zG!*TaNL`vMCSOU>mAS&n{X)@I&JRUb+o9+hI}}}OhobB3P;|W=if*t&(T#Q}y2%bj zH`^55B2aXzK+$aiMYjtS-62pkN1*6Vfug$vitZLDx<{bsUV)b%l=-Wm5RP`ekl6Z4n^PD zq3C-%6#Za_q95&0^phQmme`?asU3=bwki5Wpy*eDqTd9HeitbEL!fAxK+&H9MSlqt z{VhZC zG9abC>FMgPLeYuo(RIUoG5Jc08s!T+Z61p1oF9rB+o7o54n`=6^9f~%wDcV$^XfuJL z%>|133lt3yC>khGG)SOm3xT371&Rg>6m2C?G(@0is6f#$fui98MI!`?MhX;-5-1ui zP_(r`(KZ4_V}!Dz9{Joe8IaQP+06G0MPH`-qHXiVjljk811csmqLuqm1-P_&0Y(VhZDlLU(P5-8eRplGr{(LMr2 z`wA58Cs4G%K+ypLMF$ELO%W)XDo}KgK+!aTqUi!fGX#oe3KShIP;`h;R`-)~9g0q}DLPr8=oEpXQw54n6DT@epy&*NqB8}G&Jrk^El_l}K+!n@Mdu0>ohMLq zzCh6h0!0@J6kQ}xbg@9uB?3j43KU%?P;|LaR&;niw{-@jl>QWS{)kZYSNb-QEAqwU zD=E4rUpQz;D7x19q3Ak06kTtJq8sc`bfX=LZn8ts&2}id#STTc+M(z+o1)tVitZ37 znj=tjr$EtN0!4QV6x}0Gbgw|seF8=I3lu#dQ1qZc(L(}74+|7MB2e_GK+$6YMUM*< zJt0u^q(ISA0!4F$vZAZik`Pa z(F=AcdeII=FWI5!WjhqTVuzwv?NIcZ9g1GJDOw;<^oBsuLV=<;1&ZDhD0*9<=pBKg zcLj>x6DV3FQ1re)(PDw34+M%n6e#*gpy*?PqE7^hJ{2hXOrYpx`dy&t4}qd(0!4oc6#XSo^tV9Ka)F|M1d3J&6#XkuR8fe_c8V$m zimC*Pasowpfue#yQ3HXZqCio#Kv6@1q8fpsl2BIkO+L5U$V|}%=_}f|p(vmI6%P5@ zLNWPDis}o6L8C)a6X%DbrgkW5W{0BYb|`9LhoV*NP}I^6MXl^m)Y=Y3ZET8G6)0*e zP}EMKsJ%c@2Z5rF0!5t!idGXST3w*1vp~@r0!3>I6s;vtw6;J|7lER61d7%bDC#Ou zw4OjwH-Vz=0!2N9vZA^|ZgK{sG$wuDb>l+$O8<}a%|<;7#pEj~TE9>@b(>Js*ZHAn z13MJ;vqRB_b|~7&4n-T=p=c936m4pUqRs43w7E@De}SR_0!0G_iUtW3Z6Q#!r9jbO zfugMhiiQXj4HYOFCQvk7plF0Z(MW-!Q36Gy1&X#7DB4D#XpBJ7wgN@l2^4KFlojOP_9{xo(d6qB!{Xy-!VwQWPuF3t}{yV{{>H#-#VZik|Ab|@NehoT8~ zD4J-8qCMm3uQ%P3%Or2Af>tKq0mmDXhM3BbVQ+; zd?iK46bdbN2t~&_KNKBjhoV__C_3H_MJL#y=tMgdon(iilkHG+iXDnhwJADHpy+gg zqB8`F&J-v*OQ2}BK+)L(Mdt_3`e)eZWzz#)k*r8~lP0^bIMQ;fdy)97mjzH170!8l$6fF`cdS9Suu|UxW0!1GR6n!L6 z^szwECjv#E3KV@NQ1rP#(H8YsK`Gbihf9> zzAY4!ucYY5LgA}jL(xyp4@FDtP_)zzML*l2=odQ_{c4Az-|SHIyB&)DutU)@o1#Aj zivAKP`dgrAxj@lB0!1qXivATSs%Q|G?G#lC6jccn2 zMKuCNC4r(^fucqNMRh`1(f5U1?QWT(^tx;Qhfwrqy6kV!%)*Ba!nma!f zwXj3cDt0JpX@{a#b|`9XhoUxiC|cDHMQ!a+)Xt`;y+Bb1fufEAMV$nSRud>%U7)D5 zK+zfkMQaKattC*jwm?xAfueN;iq;h<>MBsQomggqJcI=g9M7U5GdMGplGl_(N+RQLj;P33KR_!C>kzMG(w6zwZew4XrH{sKh@2oxPCP&7rLXsSTbK>|h71d65$6wMGQnki6put3ov0!4=k z6dfi|bhtp#5duX=3KShBlojpLAopPgr1Vt!{-Rw&(d3mEYz>OZS5h>qLE+y?q3C$$ zhoTegP;{alicYda(aClwI>in}r`nZXZik{XY>LhlC^}1^XtqGn*#br92o#+w zP;{O^(fI;J7YGzxC{T2fK+(klMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)dEG=2ozl_ zlocJ@AlG@XOwkwVzUa76)MDiYTZ3Zql@#67ps?lSP;|5NL(wgED7w`SMYq|Z=yp34 z-C>8KId&+z(+)*<*`ereo1%LJitZICx=*0!eu1I~1d1LMD0)bs=wX4PM+Ax<6)1X4 zpy+Xdq9+83o)jp0N}y=2K+)3zMe_uTo)IW|R-ouPfui|BS9|;tFEKu}`K+&fHMV|>2eJ)V+g+S4l z0!3d56n!mF^o>B#w*p1q2^4)Vloh?$Aa_>=q|`V)pnfS7ZJNHK{m`J8d?iIo8x$7o zABuiqE(88mQzAeOXr88R(2?AZHJ;Zb|_la z4n=M4P}I&2MeXfS)WHr#9c_v_2^6g+P_(*0QD=doH3W**6ewCtplEG@qAmhO>j)IB zD^S!`plCgTqHY33-35wz2o&`cDC#9p)LWpak3iA-0!4j=vZCh2+$I^2(&%)h-=bK) z(jSuUm^LUDldq&`<6>dAgF?|J&JRVK+M#GOI}~khhob&=C>mggqJefO8f1r}E$mRV zrA^UbfugMhiiQXj4HYOFCQvk7plF0Z(MW-!Q36Gy1&X#7DB4D#XpBJ7wgN@l2^4KF zP_%`=6q9g6n0L(ybA6zyY&qJ3?O_7f=DU!dp!fuaKiilzt@ zO%*6QNT6t%K+$x8q8S23GX;tc7AQJIpy*J6qQeA=4i_joLZIkKfuf@XijEd2I!2)A zSfQ+F_hRn(3`l9MbXhho6!lGC-i|94ldq)c#A4x_nW5+;=ZB(`?ND@z9g0r1L(yq= zC_3E^MQ7Nd=uA5lon?oj*)~OI3lyCrP;{<9(Rl(z=L-~FAW(FnK+#14MHdScT_R9) zsX)qZ^CGLF0nQ=q7qKv8dj zqCNse>kAb16)4(3ps1ff(S|}@ z3KWeJC>kwLw6#FdHUdRs1d6s5DB4b-XnTR89R!MY6et=iP_&ak(ar)zy9gBRDp0hW zK+*0(SijEX0I!d7EXn~?*1d5IoC^}A{XqG_H@j_YAgzDTq8IV$o^iXJG zC|WI%I-$Cld?iJvR2LSW7>Z7HekeN44n?Qiq38@d6rE{@qO>lrBT_;-yVvp(^s@ttBc83QuIc3Vccn`=7G4n^RVrA<+lKv7PhC@)Y{5GZOOP*fBssun0}C{R=*P*f5qsud_|Bv4c*P}EqUs9vC` zi9k_Pfud#tMa>0@S_l-aB2d&)C@cD{I`?7*q_lUs`}sW-tw>KnwrW^RzLKK04GZ6$ z6^hz9KNPjMLs17i6m_&iQ71bTt!9U!)$LH!*$zc(*r8}mo1(P@iq;k=>LO6IjzH16 z0!3W~iq;b->LyUsU7)CkKv7SDqFw?;y#wWM2^7r|C^}xC=mdeH69tM+63UA9Y?!+|15#?2;7kfdozgcOo!qdPd?iJvH!M7U zK`1)I`Jw1cI~1K|hoaebC_38?Md#R|=v+G#oo9!l^X*V{flbkc0!0@I6kRM(bcsOG zr2<8l2^3u}P;`Yr(Uk&4R|yndEl_lgK+&}VMb`-wT`y2{gFw-Z0!23o6x}RPbc;aI ztpY{231vm6Hq3pR0V!>n&HQPhXsdMDe|y7X@|6_b)v%DeI27IO{7`g{9g6O?L(zS9 zD7xPcMGx4a=s`OaJ!FTXhwV`Gh)vO>0!5Dr6g@6b^n^gslLAFg2^7s0D0*6;Xr4gP zGXh1=3KTsjP&8kl=y`#n7X*r46exO0py*|RqE`fpUKJ>MO`zy?p{!_5!`#{#kkS?D ziN-ra(Smf1wxD4#`AUl3YFHS0X()Qz`Jw0?I~2WZhoblFP_)PnMep08Xt5oNKCna4 zhju9X$foFHfuc_Yiar%6`b?ncbAh5S1d6^CDEdmE=xc$ZZv=|I6)5^npy+#nq8|i` zeiSJBNuX$nK+#fxqMrqdei118RiNlMp{!_O!`y)xkkW_*=gm;GxH=oZH!LP!Nzq>o z3$rf|MSnX#6fL(y(LZ)5T49Hxf9+6IQ4?40p{UXhMOAhv%GsePZ&OqdC~6>3R1_$x z7AR^cP*fvOR1zqv6)0*XP*f*S)L5XXUZALnKv7eHqGkd`%>{~D2o$X%P}EYOsFgrb zYk{IRLRrzWhPnGPAf^84vh2@Lv}qw5tJV~gucW9$P2sI8Ls3WPhoVk)C|b=9MXTGP zsIwi4*04j-nsz8!%ML|r+o7n7P0>06Me7O_brmRDPoSuqKv8#rq8`*k^4n-sEP&CpG zMWbwrMhg^eEl{+LK+zb1qHP6=wi77YUZ7|PfubD+ipB~Q?IcjNvp~@<0!6zD6zwKZ zw7WpjIDw+^0!0%9iY5va?IBRKr%+ZjuqM|(15!$VQ&E0UD7qz$Nj1gfD=FHirZC~U zP_(b}L(zVADB9l+MF-fS=s-IZO|e7KR67(MWQU?@b|{)|Q#3=MXr@5X!2(5x2oxPE zP;{6;(cuC`M+g)hDNuBjK+(|xMaKvf9V<|DoIuemfuiFDicSzHI#HnLB!Qxn1&U4) zC^}UrE84pzcTxtV^nAMenH-9qOAnGxt0^X5Nzqv~g_~{&MYEkBiq5t}(K&V~I@bm?d^;3fV27d$?ND@)9f~ftDY`_U=u&~A%LIxp7bv`?T$P0AUg?>RpdEwV$=`*tW=Y=@!`>`?Tf9g04(L(#`}DEh<>MW5OfeI`)!xj@ku0!3d6 z6n!O7^tC|IHv&c93KV@OQ1rb((GLPeKMEB6Bv7TI78shv=G}I17!|YHr+zv$}>`*k)4n?EvP&C>OMO)jUXd9cNF#<)~3KVT8P_(^3 z(GCJdI|>wy6)4(CplD}-qFn@vb`>bvO`vFZfueB&MdJmECI}Qw6e!w5plDBlqDcZp zdkGZnEtC~)S<0=G0V!3cS3m}bqSLdV%TF#9ldq&`|59Q2y`ks;=ZB&L?NBtu4n(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaP*${WDK|9(QaU)j zjK5zf+9zGPqB#OZcM25UB~Wy?P*ya%lzSipQd*E+0XaJqjZ0tA?kN?MucYXK zQsJEkL(zlI4@D2zq3B^d6g^^xqDSpe^q3ur9=Ai$6Lu(i(hfyW*%ZwcD0*6;Xr4gP zGXh1=3KTsjP&8kl=y`#n7X*r46exO0py*|RqE`fpUKJ>MO`zy?fuaQhMQ;ccEfgqv zQ=sTAfugsCvZDJ+x#byW`AUi^Y72Wj7K$os<4QghRoS5^XNRJ^9f}HeC~9DbqM{v&s_jtJ z&<;g4Hbo_YqFRBXMgm230!57lis}W5ng|p%6)0*ZP}E$YsD(h$Dgs3<1&Ue;6txy8 zY9mmzsz6a&fueQ-MePNOItUbX6v~QLlyawJKuSNPXC40yMZL10%Xg|RCSOU>8nuO6 zo(M&2IzJSxWrw1*?NHRk4n^zOp=ez@6m_*j(Ry|$>Sl+c?lwg|1d4hJ6!j7)>Mc;z zN1$kZfughd^%E%CP@rfdfufBCiZ&4_+Ek!uGl8Pb1&aC$6b%q48YoaSNT6s7 zfub#ivZB>%bFXGVN-fiUQRmw7mHz%|46ZFEUrEuh+QLsyg`(lk4@D#FP&CpGMWgIc zG};bDTic;%8#@$@u|v_eb|~7;rf7SCq8$W^b`&TYD^RqPK+(QPIG}ZZ`=pZ{3O|wJMbUPHyutU*II}{ykhoVF5P;{sr ziVm|WI$WUW2!Wy_1&WRmC^}l8=oo>bV+D$i6DXP`P;|UN(Fp=YCkhmuBv5p+K+!1z zMW+fBohDFpx=y;7J;H$1&VGHD7sys=njFRIRZs@3KZQXP;|FI(LDl1 z_X-rGQ1poNL(!vlD0<8eMUUH| z=m|R%J!yxcr|eKP*A7Kb+o5QlP0=#~Mb8QpJtt5!U!drDfua`#ie3~bdP$(@Wr3ns z1d3i2D0)qx=yidj1p-BH2ox<8D0)+%=q-Vww*`vc5h!|Bpy)lJtmwho+?N@UQulQC z^H3;ipZ#2ZQEf5#N{T+r{{O6B3`HL~KNNjzhoVpHQ1q!CiaxVL(dTw3`oa!HU)rJQ zD?1c@ZBz7(K+(4XMc)Y&eJ@b-gFw-b0!2Rw6fF@bS}IWVvp~@=0!63d`+u|hoVL{MRfv2jRlJ81&W#o z6g3qnY9>(BT%f3hK+!4!MJ)x2S_u@j7AR^XP_(K*QCoqcb^=B11&TTd6m=9R>LgIK znn2O&LRnE|qujI%Na@K0r>ar;8m(FObNSAVipf_}w05Jyd9Q||F3ykpqIK+0w5}bB zy4s;=Jv$V2vqMpLI~4V>Ls3sV6!o$x>Mc;zN1$kZfughd^%E%CP@rfdfufBC ziZ&4_+Ek!uGl8Pb1&aC$6b%q48YoaSNT6s7fub!1iUtc5Z6#1NL?|m-vr+D$3`nU< zg0ogAs!3nohBhiDUrEu(MuqoY4@IM#ABslXp=fJ66m4UNqA_+T+SU$5+u5OLdpi{E zV27d|ZHmSU6zwEXw6j3bE&@fn3KZ=oP_(;1(Kvyk@d8B?1d1jK6zw5Uw5LGPB!Qy6 z1d8?+D4Hx#w2wg1z5+%22^8%wP;`J$Ry4d(Zbb&9bYZ$L8WD=p(?t0L8x@nUq-a{B zLWhN+Xu9)5(F{8j&9p<&!FDJ*#12J=+M(z$I}{ymhoU3wP;{hC(NO|LM++1kBT#g# zK+$mmMY9Boju$98L7?bFfufTHicS_NIz^!9RDq(?1d2``-*I9g428DY{mm=sJO->jjE#5GcA)py(!nqMHSZZV@QD zRiNlLfuh?5itZ37nj=tjr$EtN0!4QV6x}0Gbgw|seF8=I3lu#dQ1qZsR&+t5+-Vt* z(wpg7#|uNz`{_#mp+?2zD=B)cQQ@|CLeb;S4@FPdq3B6F6g_2!qPcb`dfE;}^XyRc zj2()ewL{T!HbwIVik=rJdO@J*MS-H11d3i3D0)Sp=v9HD*93}Q7bsdFQ1pgC(L#Zu zHwB8`5-56Gpy(ZeqIU&~-V-QVBvACeK+$5Mtmu(Oxz{rwrN!y)=h0BKX?g|ZgGR;V zD=GSK`YDEdL5 z=tqH~p9G4Q2ox<9DEe8T=of*aUj>SO6Day!py&^QqGbX_e+m@+B~bLYK+$r6qJIR6 zRtOaRD^OHX7Z>IfRSIQAA2rIYvM5vZRJt$vI28SqzJ0c;u9$o!MGfi-8!Qe*Mdyd2 zYC9A)v_nyi9g0eJD5|wXQ6oDP)!Ct_u^o!)ZHk%*6g3qnY9>(BT%f3hK+!4!MJ)x2 zS_u@j7AR^XP_(K*QCoqcb^=B11&TTd6m=9R>LgIKnn2O&0!5t#iq;S)T2m-1%Gc#~ z&485VBshh-@|Aw}NISb=t1Bj7NzuA>g`++UMO~dAiq^A3Q8zmjb+Pl)K{Qr1A(G`0!14N6m29>w6Q?ZCIUs93KVT7P_(%~QGbD=0Rlw> z1&Rg<6m20;w534NV1c5o1d4_T6b%(98YWOQTqrB*QkT0n15$cEeXrv>q3H8OYD8Tz z`AUkmt}D#@I23K;{7^K;4n^DAp=dih6m4&Zq8;o|w4)u0#@eB1Cp#4FY*Vz0K+&!O zMY{PM~PKK+yz&qKN`Udk7TmDNr;?plC0FqP+!*CJPkpBT%%jK+%2zMf(dB z9UxG2pg_?SfugBGS<$Gv+}9b9(kAKqu1ANWJ<_A=gX)UOS5h>yuF&waP;{{KL(w62 zC_2;*MTgm;=x{p}9bt!}BkfRhlpTtWwnNb|Hbut@6dfl}G)ti9c!8o51d2`+C^|`? z=wyMSQv`}m6(~AQpy+ggqB8`F&J-v*OQ2}BK+)L(Mdt_*>De z(Yj*tl@vW$SGeG-Q1q1ZL(yD26g_Q+qIq^Gdd3b#&)T8rIXe{1w?onMb|`wmrsze1 zqL&1UUKS{NMWE? z^u9pRVu7L$1d2WsDEde!D|);x_ech$)HXd7dLk5kn!bJZo}eQSrJ@9a?Yy&Z~vutU+0Hbp-P6fF@bS}IWVvp~@=0!63d z6m29>w6Q?ZCIUs93KVT7P_(%~QGbD=0Rlw>1&Rg<6m20;w534NV1c5o1d4_T6b%(9 z8YWOQT%c%#K+#BnqESLwQP;+~Gcq8h_tG`mdZDN$ks95&n0zHg+cqxTu_P32=loE# zy&Z~nutU*~b|@NahoYVAP_(lhigvL>(XMtV+RdhDcY&gD0!8BmiY5pYO%y2FL!f9+ zfuczQMSBSp?JZC=S)gbifuel{iuMyI+FzjP0D+Yz<7n84~=!(XL4Sx$oS2{lwU1f)&tL;#9jU9@vwL{T$b||{u4n;TEq3A|C6y0P~ zbhALwEdoWi3KZQYP;|RM(H#Osa|DX+6ezk&py+OaqI(32?iDDyPoU_2fuaWliXIdw zdPtz?VS%DY1d1LND0)nw=y9Q}=(5JS-7_GiKIy*b@=$bI`ttTf<6`oa6g}OzaLgZ} zXrA*!(KB`^de#m_&)K19z8#95w?okjb|`w$4n;57q3C6sqE`fpUKJ>MO`zy?fuaQh zMQ;ccEfgqvQ=sTAfugqsirx_@dRL(6J%OS{0!8l&6fG7g`aq!QLxG}?1d2WuDEdU8 z=u@Gr=&8oJ>oXvw!RfMWZYY|Po`U?WaWVNyioR-Gc=pdw^tJOt(KmJ|`qmCb-`Sz) zdpi{UV27d~?NIcS9g3FNp=ha1(a!=!zX%llDp2&BK+*34MSlnsEfXmEQ=sTCfug?! zik1r${UcDcLZIkhfuf4~xNN7WQlO|xpeQF$lou!}2oyCCC@KnNMPD?|eVYL(ZJoY| zeHn_5N%uw7^~K~XDXOh6l$M90M$QjKb#^FfY=@$HI}|msLs3&Z6g9I$QFA*KwXj3c zDmFze1&Ue;6txy8Y9mmzsz6a&fueQ-MePNOItUbX6e#K>P_&vr(dq(4odt^45GYzx zplB_DqO}Ezx(F1lBT%%iKv7qrtf;0w*CPW`THG*$Q>rgt>A#S^yscMXOumw$p7n)o zR)nHn&JRVs?NHRm4n^zRp{TDNiZ-xAQ9nBrZD@z0jqFggu}#q?0!5n&6m2F@w7Ec0 ze}SR_0!0G_iUtW3Z6Q#!r9jbOfugMhiiQXj4HYOFCQvk7plF0Z(MW-!Q36Gy1&X#7 zDB4CSE9zdKJ2(SUs!aDqJwnk4)ukLD$*zDQIX%#`Jrg69g23cL($H5 zDB8siMZ4OeXg50)?QVynads#gZ&NfuplG5%(H;UtdkPdy5-8eBplEM_qR9e9`v?^6 zD^RqbK+*mJMF$8J9Vk#VMWAS^K+!=0MbiX|rVA9!5Ga}{P;{_RRAv*R z+4iBRWxCQoq`sJZB}GTn7e1&8MMpY66dh%UqND9lbc`K}jt}2%)IxIcWcz7tfJlz*vUSCYUlA^2Y z3#(^;9mLA}qHCNVimtUo(RFqxy50^&H`t-*MmrSUWQU@g?ND@!9g1$XDY{Ld=yrjk zI|Pd62o&8ZP;{3-(cJWiWUhJy)RI-SfJ>n1&TfsDEeHW=nJ8&XkLBp ztPDtLP`WRACKTO~9$kM~UrfG|qHpU9cQy<~-#I@NeQ$@NAM8-{qaBKVvP01lI}|Oo zL($K6DEh??MZek<{U%WKyFk$&0!7ONivAQR`b(hbZ-Jua0!9A_6s-^_`d6T+qDfq~ zQ&cHXR3%W96DZ0H6cq%D8VD2>1&XQ#iW&+O)d*!pU)Sf}%z%`pWHbLwDB3Sw>6e-m zldq(xag)MtrBGDw{7}@y4nB)Tl|WO>L&={q(G3U6b;a{d7eKv92zq5%R$0|kl(2^4K1P_(5$ z(O`k1tptjO2owz!C>kbEG+dx)gh0_qfud0YMWY3ZwiYPbMxbbnK+(1WMcWBwMZKEj z#%DlEHR&3ycPQ$T9$jzWq?mjqMLRVq99JKTc6NR!+QkkH#-#VZik|Ab|@Ne zhoT8~D4J-8qCISi_7o_ZBv7=MK+)a;MUw@J_7N!BSD`*kz4n@b?q38rV6rE^?qLb`Ubg~_aPO&LERiNlJ zfuhp|ip~%yI#ZzNEP+b}3lv=-P;{X{(M1A97Yh_!B2aXx zK+$CaMVAW{T_I3(rBGIMWRu+Y8IV$+boX;qC^{#NtC|#(ucYX@CWS^VLecfk4@EcF zq3A|C6y0QpqMPkdbc-E|ZnZpy)n< zqWcAk9uO#cP@w1`fue^6iXIUtdQ_n3F@d7T1&W>!D0)($=qZ7sxdKH`3lz;0%8IUO zlIxWLDfLg^y?<>eTAJ>Qo@r7{zLKKnn-sQf8H!$Tekgj;4n;57q3C5h6un}HqF3!u z^qL)tUbjQh0y`AFVNWiWUhJy)RI-SfJ>n1&TfsDEeHW=nH|OF9nLe5-9pwC@XrdN$$`LNU2Nu!$b2!(O=om z<-ciCOumw$ADR>{X&s7wbbcuM$qq$J>`=7S4n;rPq39Po6#Z(4qTlRL^t&C3{;(-p zCQ$UJK+#_UMSlwvEf*;IN1$khK+(SfMHNlsvYnzzfubsbqMSfcUZAKTP}D%6s3=fW zEl|`@pr}Tms3cHSD^S!(C@cD|N$!aZNNLSI6s;vtw6;J|7lER61d7%bDC#Ouw4OjwH-Vz=0!2Lpih2qZ^%Ba8 z>YL{BZ8Jr4(o;lDnwGEhXJ>fwy_*)3ucT;$riC@yhoXMY4@Dc=p=cvJ6m4vWqD|~j zw5c76HnT&~=5{FRZ-=4*HbnykiUtW3Z6Q#!r9jbOfugMhiiQXj4HYOFCQvk7plF0Z z(MW-!Q36Gy1&X#7DB4D#XpBJ7wgN@l2^4KFP_%9f~H{p=hEViuSNW(VliFnq-Hfy=;p1 z7ATr5P_&Og(Y^vj`w0~7FHm%VK+%B$MNplG^4(F}p2nF2)z3ltq9 zP;{t3(P08bhYJ)PAy9OrP*${a)7;q^kka_{eb>8$qN~!Ex1*XCldq)cxTb}>R|`e6 zoF9sgw?okhb|^a04n-%~q3C2g6rEy+qEqcqbebKCPPZvKL!jtPfugenie?KGoh|$? z;@$*0ilS}%@1B{?41{GS0m3GP1duHxL)aI|0wFU)2oQFV>_FH8Bw-UJ>>&HT?;xm% zC?Y5zyP%?gtgZwQ5JZK5Aqwhu-`)3>3_d>ZcfRv~&-u?`xa+#QySlpSS6$ULlLQnk zgaL{c!2m^zVSu6~FhJ2#7@%kw3{bQj1}Itq0~D=<0g6_^07a`|fTA@pK+#$lplBTo zP_!NfDB1u66m5iIP&Coce2D<@y+zWJD-`|8Vw0bh`BKU%CQERM8nso${uX^?tJu#l zaP|lEiLK4`mxHIJ>=PX+^JHuO02zZh@y0~ zXND?DXZs$fqI9!A30IU}_QZT18EuI_9sTHc%ZG*HI&=jw&0e6;wy^W@-l2v2820gX-YFW?xfv@Sh{E zqdNHSNjFd({0D)*T$-Y|0HK~)xm#Lv9;>pKZ+NjI{2@ewNoAZXQ^UU2mf86 zj;iC=!_+3Kga5KeH`T#^nxU8K;NPv^Pj&DwM^926{M)V5R0sch;z6o|f4}Td)xp0Y zbcE{Q-|(2NI`~)gja41|JJu$s4*n%sxvGPI%h6QTaV(EoNOkb<8JVLx_!mViP#ye} z{!3H`|ETr~)xke&yGC{J4@+)P9sJX7TT}=CxYBmj!9Q=ZLv`>E4D3=J{EhGTR0n@$ zcc1Fu?_3^G9sH%a!>WV7^>kcy@YhyOsSf_$!D-dO9~_@m9sJ4P1=YbH-CR)}y!QUB z>fpuGJk`OgUq7f0UcUHIb@21&J=MVv5cgFF&j25(4j#e_RR`aLpQ?&qA$1zd7Ng7g z|4O|^4JU^yl9Fo{J+CU|Zc>j@!^5bllv2EjUgc(5+3Ubw8om3mmuY6N|9nbQ>nf}1 zU4AU@*Q5-4R0sM`lU5*j6}74EDHW>l4$VZ&;T)QmnL;}#6+Yy`w2&>UsZeT55l8u$ zRw6!O(ON`TE_E9b1$1vvUl4JwB#E{n25<=?3=u&00)?-$7riU0owZV5mmb}wqT0pB zv3XzN+pknqyZSh$UA#1fQVBke%bRm&jaMr1hacC%@G61E0QgY{M&xQe^|(tN5*%%sy3Kqr&rB^C7X1Tz+e2vyY-W)LLcyea&U6 zl<6MeQ0)PVVydb5`o2JxqL?cv<}xjPTlu!|b@@{R$`%_P+(co=r!4Ku39G;A>uc<( zlC+gp%r+e8>s#8lly7sY=Mn+W>{XKX^2**RXGmEF)RUUS;VZ zt+*Wa(o{@7vqMj4isC1iBq#B2sJ5+yLOfr|q5AnmR9qfaiO*P0^D3SxU~d#vPWi_F z=~eLds?x~G^FL#1t{)|G~r z(ThT5V>JKq;!dF|ojDBFlifHB)sy`=Fe4V_q1t&pr>Nu6?%g zaG*|3$sQb#SrmE{AjF4A>?|e^sUbd3@%J#EbXwetGM!Xg9NxOoy1% zCuK@2D!pi5daDf^hK@=O9gsC5G;369=%~c3)bzv=qcXG8Q?t|4LQ_YL8^w9lE3s>2)3_%8 z8_hI2IXj(eOHrhu8@0%3n93X^rlk)^&Ka7Wm_2SpdRD_hj2E?4TE_5f5;S@wM7K|* zGNwjn4jYy^oIFAbv}AC;hNaNJs_AH&!&Oc5|8Fl%^)U~m9n6&)YN~l)pq>gWN(Kh{ zglc|1s^(82MALj~kn*n)8mjr%BV}y+?=gtxv1)nEmjnHl4i1!;E*sL}jkG|LT20Nr zs-BrYE1x#nKVx~eRn6X7s}-!3&~pjac#ce&){;zh*-$G%nbxFz12`G_e@lk(!R3)v zP4BD%^%I#WyExMUp7BN}SKdcsa;(6@vZ?a@HrkcmAU$fI}Ni~Dp1WX+z<{kl_Zc_gEp!@!Kmy&T}owBvr4^G=X$T9*Gpg{tvc7c zp}aQe$!DAHKXVHua{M(d#N2N{>p)Wlx|MZp-ytz3ELP#@Y#tVym|`TGHZDpwi7rYu zZ7zE@ZVoRJ2ZuE_wzZFzeVnv&M#s#|5l$s8vR7hsr*4gmyxZZBCPn9K1}nVyyp4*^ z8|{^)6tEEvXj-&a3%yJ^!?Q954o^=Dq|T?GE?Uavj6p7xz-6{Cx(+85M&G{$?UtBG zM~62`G;(m#$#6gna*LGQqKb2%8lc_Ma)u2XXXGUNHkMuK5M&c6o0=6_RJGVh?IFp= zI9t2oYN5)ItyFlULMay`;Z>MsIFzbU-$+#~$2BR+j7o-+Hj@3ri^~yRbc8b+r=o(( z5zKfXMHU_IYzF|sWm^#uD1@_lQC7}k=l}^AaTZfZS0kqe z8AS}x4Z*m8Vx*kJl;MS8V=-mU7&K8aTxd1A2;(>;xOw!Oku-54kDUW@hNn8i!t@Q& zJG^|Sae%Y9io9CBndFDoF`(izG%v0{s$C|Tr(r~x!Zpfslj$t>y)M4%jtL56QgV$m_km>4(Ogifm` zsA{pTI19ZPZTGKQ@7MMqPUN{+=P05sHVWm^#()TYK6ieaO> z6YZsEu5Th(NXO@7w@c1WPVAOG));h(u7y}ux)#yiNP2;jZq5ol1B^1N$!P=`V2gQk z76Vtrcrj-*cGIb|24#-QE*dV;mdvn@6~ZcsWoPDOJSV@J9JNTR5{oP?I_=QRd6dQHM)7ou!h6v z0j_>p)`r+ zd{4~I$Q&M$MNd8yv&c&$go?CL6*MJKT*IGb%UR4b4;@kk%<6v|H?~Q3XmykKp1JF^#dYIz&ge46MWb zEppVb!1lvZ($mst(%ua#8+sSSibdW3-XZn1-@oZai)Itblq#*%@mj{=Rh+0Y6{q@4 z)23Tym}i>isix^Azc_XB;}gfrC^5c~EokRtULaA_P)cgeL*g37MY=jEJ`QVK33ExC zpQW5yUJWo;R4b{K)hcRLwVEkNZOH3C|9E*@7UjX;-kZ%u%TW9Bsiua}wD z2Y7w0_+?QXBSW`&kqymEvJZzJEf!kp*#OWV|~P!c+|{RYNp9B z_&?BFG)(G~#UiB-nnlVP=A?6RiA&OD*rTQ#L*Fb+XUb$FaLaT1L_}FUqn%QsP93Qzb5txLM*} zS|8&5k4fa!N!B+dKA{U>ZKd^lj?dAxaI7n_Ej2xBkHloU2G+wQzD7;Ydbh-TQ~|7i zm)MBvigjCwW9fqm*3%?@MC;b9Ka*&wVrYj%H+`hZ+j~k}P~FgLC0?S6KXcp#Ks|pj+8i_8jAOyA@Q)&(4R~6Ay9d{zr>EzpsagK zT-4mq>m^=kY3Q30t5L)A{`DoMwKeoeiEl(2dauO$(T4t0V$&EyM@yU#Yv@@LkGc(g zMxrgw(B&m|iZ^s$iA%Z|dZWaz6AXP@VqgzLhe#aI%g|X8cl0sz2NLt?Lp8p>za=(L zG<183uOu6Kw#4HEI`4l@V#xu94v^S+kfC3cxNNYYH%t7MR`vP#I}(F34IL_R&`3k) zNZgra==~BOeJx1cLIfgzcv0$E|&GU`edZ7_r5+^S<^n8h@mKyq^#4;-kT}5KI zRfbNMxN41|w@J)fXXu|L*4}97aEU`V8+x3?cj-e^ZjVC}3%40s+it`c-Y}v^;?y06 zUMTU?orbQ|Ys7eoGru?VQi)&W8TuQE55TH;MF#h`zm*#B8gfCrSK}zOKN>pOi>n z3DI?Fi81sA2Hu_^agN>4D4ZmC9yw!$$|9{iCgH~4y@mic$dER z!1}SoF#7%j>oyWc2O4^c!~^t+EN}lrVi0}5h;^vMrW`dzX)n4n$CC726N$aWPZK>z z;xO^Yik={GlK68(FOaxY{7n+ymUuwoClW77ydm+v#6KmLq;Dl~`2!@@f7BC(hitCG{?$b0_7JVs-CLQu0<~-v&r$kjw>#ezLsa4mwlXf z2BmQfXJTrgDuJAk7q(3y?VX>^L*L&dkFSHDl9AskO5+$xDnXPV?}rz*EhED_zlvV@ zm8NaTZwIAu4Cm2^^81cA$_v}JllIQ94&}$~#O0%IS(M*CO7k(y1HZ~TRb>p{6y?R+ z_b>absH3rB_nPiS0Ya7+(r9GFE9- z0Qs_0r-Xh*nsHC4qg0}v7jox*{HGmf?7C2Rz^N_rzhB+-`5lvLSrm0YdrDM+DfqbS zMC|dxsbR-G#|v#Wj=TSU{MX<7KI%EOc8f3FIvi z1y0(gsK*QMg_%|>_0{_ia+TotM~8d7)lpp>ogZ!T3*O_}m=ct9BPDpydiCjrsDhqZ zw~{$OB7kzwDKM$tyk1D?P?5o#U0x z@=A~NN@sedhk2!kc%?JE(gVHH>0aqnuXM6kI?*frqF1`FSGu=Xx~EsVyH`5FE8V3i z9Z~SH8j&B}C^L ziYBrxHJI)xd5XP4MB5UdolCI1I`4YJdCdYNe4>1sy!6tEiP61&%!-JaT6_JvsikbH zsvJ`2iNX}WLtE7g_fl)6eSTBED4v{70q9h7J#UU4bCl>{YSNmhm^18Mzj zm@-9~sLWPoDa)0m%4TJ)@|Lnq*`w@Mj!>Q_l@rQU<-BrJxuN{3+)|)pyjl)&1&T z^%M1odPe*$Cf8}Sf&Y{ca!sZ?(BG@Xxoc5g-;K@s{L>UxUzJ!+cVqox+IXO5ZdmCp4_ zzv7ji;FbRW(jNzS<&)->PVq`7d8Lc{UHqeY30$A4DXD{3nx0;W%wL$m=~bp<4x%x z*xPzbQ<=;+yvoobx3#CWyN#=jUIuEV{GQ>@wvj=qIYtRA9!I>>ROZgu5}hAz24#F_ z;99wroSG7sM( zWnZ;D`>IX*iT-t=fBWcPHTpNL47~@xkyACT>bAq}3NC->v+~o)Uk~>mGWe~M)+)-! ze{CyQ$}jL$rTG_Q->q6NGh|8GouiMs%U<3y>C%&aga2N#;rf$P7Y_Y(_sE)WnpdAw z!E)&LvE4&HIZ|+qTd=6r0@iufx!1ea|4V)KF)0rg&sgPIj=iZ9!t;z=({*OVc_ZURy5_(cOgqXIlYhjFa=~Ba zRmRnnj+K4ZQ<`eQR4%x91nC+4>^y}^W#^v3SC1ZLTz|i!>qmZk9@Gn;2lcYvtNo%q z(Xs8^?OgxKdoQ|{9n<6T&w7>r3;nwOS$?-y`D63XM)UQq)z7V@gnCl+av5dZS5(G` z{8`fXim#u`SkqI}UCUKVZv{(G{G&v3ym^UqjkP&(3XG9sw4CL z{g=q7wMC!3tWv4$=~VLjx!f}X=6P-<&(nLxT)jMVxn~@n^Dp;;zH~M3Pm2t`F|a-5 z8k}SaP913U;>n)L?kTP*GO|wgOd&N@YNNOpbu8*dRD!O5T!<*BYxm?Ij^-M8T8sV< zi!Sg9pm#$2qtdR-`)Wz!itq82FQE4Z-Y25K<{y7Q&^Nl^md#yoxJ>+gOR2%G!SO@l zc&2$TERe?hd%5(^qxWI875#6gcObnvAEY}|TKV&2!QDuAXjc8FOGnzE5f& zS6{9V-do?xI4UnNH7RvaU*+k=3p56D?~TsCJBr!3S~zIZsY3d}KspQe8uZM--4XfI z0qS3I1%=tP-jjsx$#@7t}!!?o9b&t0|grHrVTYovdB zdf;iAsy4S~OmYNL|5pYK+jQ-t-oc?k z_ty`04>Kv>RQPOosnP4ND)hS0ZPOPSU%a+quBrr%Z2WzRg*s`dtK~&?HODj8eIt3U zYp!RWz6b7b`dzeupG5D4;ZDbQ?P(sbdtPd4>SSGW+r;Es^!p*-4Ppw6v~mCRNgZEQ z-`;F+UDG4={ehFN78Y)#_d;n<#6L3b>U@vE2*D*s`q>e+*yp-HzvMb-FCzu#gSz2-UeN2p zxEm@|H?4Hdbr36eH_pkGZ!;S`p!lw7lxR}XSQ?RUq&cr=$2j8(^wyDmxJ20hf650} zz~#Xea6Y&K&Zo>jTGzLzb&V^ipI7(e(8bJOhs^x9{Kl1U(KY?AJ|F&m_ONY%NjY*@ z$xR|oA5`}5bMEsJKkyu`?b+O@-=5nXdav0Bj~(SAzByCr$G^&z54^G9;k{1={dQ%* zjT$w#mJIpkMPoh_|Hv5Ixs2`PPRM1n1aD4`f7CAZ-^Ry(9i9Ad(Ei0^F!JJjF;eMu zC?gf_Ml?J3f0O#do31xKJA|3yc`?sUz!dn!XqJD_^=x_HEy` zVC_yCHA>K^QISSDt5R#dXFcC{!q&Uj^Qf_a*GQ`7GLM+^_og|2_GIt*qq^F(N)2BX zr7nKuQMtEsYnz^re^gsr+Hsj@nSSPFoa2b4oL|z?f1RK8r##0_p6{9OUf^1wmyt%1 zE;Og|<6b~V>-RzC5Ix`(cWO$4KC2|+)bXA!DSZYn((CJ&E@RxiX&cvA{39jlWmlG` zb1H9NPEKIpcz33&S8AUW&){{Wxi<}QduV^Ak!oHYsOPnW)YZZtCyj8&Kgt^(l|Q9v zO&Uoi*I1R(Atoy3YT?-Hj+q$?@CX*B6&+@YQJMp1?K)-*}Xpt#QxbQJ?P`9XdYy)EkxWAC%yVr26BvwBs~W zs61#P-9Kn0t?Spx5&3>WeUe&w`V8ty=l0~EHJvY1948BN?M9p`ai+vM_DI*tls+jT zo<4(@(N%UVIBV*YQjZj0b0=NZb|>gH9h>jt8{CoVVFSGv(5SKt0=s=I9O@;XK(KQZU^`8!+lddEL{ z*S&n?eje+1Z6o90{t^)nmaOG5=n##8tv;+zC9i#&_mi(QL#4|#xJW|{Nz?&}znI6sU@#{JSK zbxP5g^x`vffIC@A9qzBE3N1>{?-c5J#`6}R2XkQK9&gd_GG6WWpYvY-!E`qn96Q7_ zM4zj8&wF1qC0=Y-P)Z*&Iq%qlQu?@H+WM-uC(0e| zik5l6-;ZNIoc7JVTHQ94>C!9wi@0s?Z>`iOx6CwGy%%d%H|KmeprBjXKpMA(Cda<{ zxbr*BZ}$xUy|7B=oa9fVr$>IUr*QkA8jfG^g9&Bqf@eO7Jug$>QJ zR)pEUsC+xgS*~hqXp^(Q_X{lJx4xI<=+FT*uidH{@LZ)+hv!dN*LF(nR)t+MKi%GL zasS;u9-G@fPbr*km7Q>EAUw`kZ$dGePQwkTom0mry+D{t{^b-?AuG#t>c%+mlqF|w4pOj&w_;F5NG%}MN#B-AYN5WZNz^fVLg8^zkB|1zeZ4PjjmBy>>HweRxGTiwPodTH&NQ0qpXnq~ zAC;%pb;cFWIl}^L(8w7a6%*5mR$~s+2$mF>bS;ISy^2T6qlLNj zoXex-QTn`zQ%4JDN}LmR=Uj7oN^0S1p_9;6e?I>Aa?)5C?4&-fkCgh;F+WlBNJ-;l zFs%U4S^Ll(l-C>SEY#A9THAHCkrdGQ)6Sw$-=5N_#Vx5#}rl5*GpcYF>Ipg z^pP`J6KW3Hx+d@4wQHyIcvNzQG0v#U4CSz*=FaFp%+@D+>6bT$mAnz(wDb3iFFbCu zWX-XfanBzT*EzI2FY4jVFV7ubQQ2`UX2UY=g_UF5_ws!>I=?!tOU)|!6iu$S3$Mvdb6=zNFJncX zSKO%7-v}R;M z$^;^FKy?0;8h%7&2RfhS2$4xVAE#B#8z~_F%fba=_C~~#^Gjm#jVL2EGt7u{^!Ves z;6Xxv*QOp`Z!CW5yL_jeAM;52JLp~G@|_qzr1_ctxXvf94>6xSau=^qVeIBHHL~EE z{;cIars{Lo0=GT7U<$QorGK=73Z4hAR@?Mvk<#OMr{(*Dk7CUfFuveIsSVg9!CY`Fz-Ske&Ls;_N~* zy$Na+St^7CVA4quBJ=--~zo&F4@X=ReW_fNT&mtbTgqeTa z&CHlL^ap;GV3*R<~DcbR6@6KI4`9G45H+Ko6<;v7A`Vp=VWfp#H?dGYJo=H2n#L#{yGehk}yMBsV=<$P)_9*42JRPbl0s z)7-t{deigF5Pim;;_24$P5sl$u0ctj6IAvSUPR*aI%{wrms{?VdG_EWf0UMbb=ey2 zJZF;~^o+5{AhSEIAw~46(aHTn$M2G9oKa|mbkKN5cTD5c{(AbS{XQ`rXyy}3Gaq7H zUxVk-#gm_>*K0}Y1^2>w(f<}_Yft?+>g!<_|8aaPPb+t8SL@glUdOlev~;&}wbI*& zSH)Vot9Cp==N>}$@kDvnGOudl@=t0K+tkxk|As=>pe7!Fy1y9X*d;lOaqTo7HIKhv zvkZ?&=CxM~-#c7C-sb+8Mu7$~^nY$$`oBS5XS&aGA2>AQepCcK8}L2;$;qIvDvryl z(C^}NCSFrGXf^u8&Ds?#AAV73Twd67)0$^zD!FG*8-0h@6zJO>xf{%CZq~eu z7usD(S^e|fz~qQ0>iHHQmg(Q1h=CjV>}NYbvXKG)x4|AUY+w5|Kx%? zX^8nr-7+`k?0bIu-M_PMKHtG&vnVrW=9%bY<%rxSAJb_1apCb1SxE_l`cqweN&Uc+ z#Q)FM|Nl(?KeEu?c5c+q=icoUu7A$WyZ~1om|NqI3)D)DRwh?Y3Zni_ zEfqA6devDw|9{-xCn?vRFo;(|`AY4L`THrH+DiB5nR@DY;T(wzXy%Yjy#L?tg5Gu76v*KJxN91tLYllzi9r2-cj6Vd$}Urd9c{-XYrkffArZ1-x|Gw+IVVFZSd&M>o44!iu3lX=`H8yx07d3FTzeq6~);&lY>k7)^6yOSOLuA4PAtG)lO z3sYz2(XWS7Cw=6TG3T|f+CAFZcItwAJY{qF-M+7n`SRR1eJ-ATFDBv4 z3qM}0_RD)^tNlLw&0W<8$0T|8)s9{J51Y0v$y2j!+1;J4j<-K5cfG~sPP%1y0XE zj;}|}*5haT|3_#}eec{z%AcPyx!>ndzt3@v_KZfIQ~p7c|4_>JY#{%CJTOhqooDBI z?$pN~={;%(^|3u1At5*`4f4Dehz3zoNKr#S={ynhBi^{D0|V z6`$#2FBJ7Lp2hQAU0WIJp?i=%Z;y$kyO5qbQaDHAf*MioD1AL6BDf)qc?X<}GrqCV zD(wpEu7f|`pHELu{+7j1;F($e>+#5gQ3ZjiJaUM|e*JD}y_U$^J zy6(EJda`%7gUozJm94k>R|*?G!nJB(72iXjg6$Q{b{^?vT6ga8uO092ER%4#)rS>6 zD7F1y|I-KkcBVhsy=(mF$H#Uxi@WBo^xT%n9kaULpZ#ROj-P7e{L-ad%MFbmWb=C3 z8@;oCca*MO>e8X}-+mTTeTt*;tv7s!t@V6$tUMAIN6MY%e zq}mE;tI4EQrmvBjOxEKy=u49MoQ|s)NBf&B+Uq`Kb@Zone5EAavd*ha%BH2TX|ono zqOW6EH2xW7lf^o}JnepoMqG0P|47>1JTZ{|3oF-+(%O9b&*u_-Th(frKuL?IjK7t{ zVg6R6wR$<~!q!Cko~DURI>>s49ENtF+ed=-b-?)>gsvHFs+bN>{R;p~|RiJxu8;*8NnARjo&9&uZ3MREFx- zAaVk&Tj`87tPVO$5dFmqSb}vVK6hrCD==6eZmnS(ARpsdYeA`Y{gc zZ7TDp*7Ee#`p>MtP}xpfH_-KdZoNW#eqn1#=?1EezOtr-s5bsfG7VMR0s7)=sA_9U zr3q7QB`GXWZR4rN7pk_ERM5q$Z4=eq64mx5Ro7D0cAwNT)mD#w4rIA%`;)GBg=#a? z30A7MOxm_ewbh{_tyXQ_=tPfH+gJ*}skYh{MJZ5i*XWWStF{EHtwPoI2OZbTWSdMU zI$*MeQ(1mA+dd%{?wD=miL|?B+cC=XC$nuase5MIX{wi>&9<+ol72DUtkmwmnr$u9kJr8a<qzJ8YOxKb zkYKTGrAz5%v6ZC*x?5}+#ApwTjekpSPm66iov4?^c8qA~ZLz&Ynf0;Q-YKmpeJ!?L z)NK7|Phw}6#gE&UbB5l=C_(H*iPSE)@twAyY`OUZn+ig-C%G#JjAm9-6}B5f{ft4__arL3(Q<+-)2t&nzkt*mV%shR$^ zL~6}h{*%Z=WQ8uwIc#-Td6D~18l9RWTOIXj z0bdEQ{X~aP46xmyU2+3#DxG0cfUOke60ydXMyHKjW4lC|MXj-gQd!!qu|1_~ZNJ7= zjVdH&jm?*8u)`YLDQbYu$84483|)@dX3{Q6cWqax2PEIMouPV3xob-&CQ|R(UZXRl z-L>7NLZsidrO-7DxNDn4=Novp#E-OXghN$IJfMpi$%*lF>?lrrM9rSXi8$IPn-g^j z!yHb`qiP(@i9?i2E;VV1V5-qcoY+A5OyCJ1;;DAAeD&cAG+L;{_{!U>hGLgT~~VuF5uE0vI1!peyzVQ#{4*8 zqn_f=iOJ-Y;{^Z6eR)niqH}SnOKhShpdSHKO1w&iH*um9oq~TwLWx(Y7g;z#*GE@D ziFtHVA5I)2Jb14XSE+-moVZBTnmEydiowSzCAUyUmf@;-18Lv+^j{d&MyUyus7_;` zPdhrIw1xdL7Ol3{h8Qaw6{cv<%U^q`PSUApbwpMp*+|jqihPb_xT4h)S(RjCMXN8e z3dtsl)<9%sl1&vYL}VqB%@nPn$ciMJD_W??0Fo^fElgwul1?g?Q*?RORIWy%%dw_{ zg^TuQO(knA+K)9At%+y{Ybsk)(RS8UxMrfuvZm5C7hQ%m6|aTp(yXa`Ek&0i-H6K9 zO0+L)Dqm~SC0SGX+K4W}n#%WrXd7!PUt7^u)>OU-(LSuHe37Cx)>OVI(H7QJzG%_( z+bg0PQTf`5Hjxge^0gPOvZnIIh^F?pTeO--MG^OaFT%jw^Ie&^lP#5Hw7P zM@uANbV54Hp+ZQUNFk(?NFgL%q!7|sq!7|Yq!7|oq!5xIQV8iLQV8iT5`^>+4MKW~ z1|hvfgOJ{$K}a9bAf&Ho5YkUH2zgO722V1X`(?$ zx@ZtGKr{#$C>n$e5)DE!M1zpQqCvNm%m+0QE4Ye{kOvngr z65*p0GExo|LPm)cLb5~(A=x5@kQ|Xh$Y_y5$QY4A$XJm=$T*Qg$as+;GEp=L$rTMkCW!_ilSPA&DWXBhRM8-0nrIL*T{H-pAsU3t6b(XVi3TCB ziUuLGMT3wzqCv=9(I8}=Xb>`AGzeKB+8|`Oc{8=Y<1Wp7v`mAL`ZWE~7FwAcCS<9$ znTB7TkY#eH5VBmP5VAs~5VBIF5VA_75VBgN5VA(35VBUJ5VB6B5VBq*2-zSSglrTI zLN=X?` z-WCl)c8LZd?}!E=?}`Q?yG4VL_e6t`J)#Xl7Mo8{`#bV!s-rD22pLOLBkg@Flf#63 zsGXo`rcTIyIaCNaAW{f9C{hUdNTd*QNTd*QSfmhgM5GXMRHP7cOr#KUTqFoNAsU2y zEEg#0K{2)QE?gxnPk zLVgkrLhgwMAwP=-A-{+QA-{?SA@@atkO!hcNWN$g@=!Dgc_bQy{3aTN6o>{Pk41x! zLeU`PchMl^578jxiD(e=R5S?rQ#1(qOEd`iTeLyQcV_;5Wsapx#rHZPerq{Rt7wdl z;&0I`Dm{qM6Bj?tXsR4toit5*eW0t6rfInq`Z>}xEw@2eB~8=v63|sh)3m%KbY;>s zE%$}4M4G1MrJyU4rfGR;=m63*EiVIIfiyqYl!ZaRG){l8vBN0G1{Ki(!=DW*qaO@E zHmH#PFdS@9Da*mIvq8ly52Gv_RL%-8%CJEN4S-Ra4Jv6x7^TSIC!9(!eA%G7tPG#s-!2IT%(psHD|k_^?4GtqwzDgGw3*!@>rYv<3__8&uLD7$!3K zStl3<{h=KFVW%bx0;Ie}GpXjz1c=}J{D@;#4T`$aQiE1YwK85zQC(FVNvk0`MfGsJ zP*fjUC~5#L6oo(wMGc{aqEKj|C=6OCazYD5ji801aA;7}7zQY60s|B^g#n71!2m_g zVSu6*FhEgD7@(*X3{cb>1}JI+0~Eag0~ED|0g57EfTBnkpePCkD2j#wirT>dMeSjL zq8J#Ur~?d86bl0sxnLL+J+GRV5g>kjX)#8tBNUlws;jwGEAzz^byBsx1eQ)wJdPKN zIztOZU7&@cuFyhJ0<=)n4O%Gb4lNY*fEJ2+LJLK`pg~b@7@(*R3{cb;1}N$W0~Eao z0~Ga#0g4h~fTAQApePvzC`y3=ic(>KqBIzwC>;hU8UOKli z2n0a_?}85$J50s|CHgaL|jVSu7ZFhJ2{ z7@%kh3{W%`1}K^a0~Ae%0g7h807WxlfTCG2K+&r(K+$X%plA*ZP&5|?D4GWY6wQYL ziWa~CMGIkoqD3%3(P9_|MI%*n5DjL2PM$cA5{hQiNTw}Ot;`owv_jRQ>499QXeEvp zidI1jMXRBOqBYP$(OPJsXdSdrv>sY0+5jySZG;wzHbH};%`iaG78sytD-2Nd8Vpdh z4F)LM4g(au4g(au0Rt4h2?G@EfB}l$f&q$l!T?2Y!vICQV1S}`V1S}`VSu9DFhJ3J zFhJ2B7@+8V7@%k`3{bQWhC$IX)jWs*@w?0OqUAzSIsI8owK88!(Lq(4MW55?6n%u_ zg`z{yLeXJpq38&-P;?YpC^`l$6di{aicUZaMIS>8MJJ&_(J2_9=o1*A=u;S==rb6g z=rjya^f?Sr^aTu1bOr_}Itv37or3|2zJvja&cgsj7hr&*i!eaZB^aRSG7M031qLYk z3I-_p8U`r(1_mhl76vH#4u(O|e$~8_0P(xcx1R$-(M0-~O#5E7GG9#5byYhg1pJ9NaUtoZuUtxfv z`!GP!0~nwv9|kCT2m=&7f&q$tg8_;PV1S~>FhEfu3{dnt3{dn33{dn01}J(80~GxU z0~GxQ0~GxY0~9HyqNjZ08BK)&icByJit<$RBLc*)4lfp76N;?#NwH=&S(z`U$ZFEc z*A|LwI9@0!0WB1jgcgc?p@pJS&_YpZXrZVKv`|zQS}3wZ3q=lSP~-;#6#2sdMde_C zqVh06Q3V*FC;$d1st5xVRe}MED#HLpRbYUksxUy&b1*2_%07cKkFesuw=-QG1@e8L9#5Et2@uVM2 zONm+?la={miW-=-zIBA65F9TQHG~$5LZOACFleF32`v;gf)jPR zY6k-pwTA(UVqk!x4lqDbEDTWOf&q%$FhG$91}N$X!=R|1$(&1o_&uWUo@n)jB7gqm zBFZPG$Qg`zb$UMN}%EflST7K+wG3q>2Cg`$nnLeVB@p=dL-P_zYFDB21Qie7^O zinhT3McZM3qSs-7qBmfGqBmiHq8%_m(OWP;(M}kk=xrFFXcr7n^bQPA^ezlgv>OH} zdJhID+5-a=y$=Hv?S%n~_Q3!}AHV=bAHo1d`(YRqtu&dt5+Hv3%?xdoP_%@;$fF%F zS(z`U=&(u4atcL9aJ*1-6j~@c1}zjFhZc%XKnq15LkmSGp@pJT&_dBC&_dCt(4gou z7@+7h3{dnr3{dn13{Z3i1}HiU0~DQu0gAqa0gBGU07VyIfTD{qK+z=_py)CTP;>M@ck6?hJ-(Y~E0vMp^F$_>t2m=)T4g(bZ0Rt30fdPu1!T?2o z!T?2o!2m^n!vIB!S)SrRkqQG8nP7k-GYn891Na=`#aZWy4*0|OLwgaL};V1S}dFhEf}41=N&vw1K9;@6GuMGb|b5HpF+W-If> z6m>Ievs(&9-Eq87)B{>5>Ip3r^@0|PdP56EeV~P+zR*HZKWL%oMQEX@KQt&xgaL|@ zV1S}z7@#Nx1}I8}0gBRKfTDC5plARLP&5z*C>jI<6lK5wMT230q9HIq(NGwmXc!Do zG#myf%7g)mM!*0?BVmA|Q7}MJ77S374a1iZ(zCMH``oqD|03(Pn6&XbZGZv=v$?dJS4A+6FBYZHER$ufqUEZ@>UW zZ^8gYJ79pKw_t#xoiISr+b}@UE*PNb9T=eKT^OKfHw;kp9t=>l2L>p59|kDe3j-AG zg8_;@fB}j=gaL~7!vIAGV1S~7FhJ2qFbs;;n9Z#T5Wl*->bO=YT1KD3YKP2L=8Gvh zX4YPe6pD`Hc%kS7v{3Xhv`};sS|~aNEfjqMEfjqUEfjqQEfk%G7K%QH21Q@M07YkD zfTFW7K+!oEpy*2&py)gdP;>zXD7pv(6kUP=iY~(dMOR>eqOV|pqOW0qqHkb;qHke< zqVHgUqVHjVqN^}KQ63CXbPWb5x()*r-GE_Gbi{0)On~^k%U`uVDip2Z$NnG8R_2Q- z`q8XyjuwjU;CP|vF0@ee6SPot4_YYt8Cod%1zITj6>8P zVSpkN3{Yf-0g5azK#>Lm6#2jaMOGM~$Oglp=$6@hiU9Gu&JXvug`yAXvwW?D#mam! zMWrp;o%TXe85}PZm4z0H?9f7y16nBZgBFVXp@pJy&_YppXrZVAv``cP4T>tl07aEx zfTGGUKv5MKpr|SgQ1l!OP*e>DD5?$v6a~TnMKxf6q97QcC>RDPstE%W)q(+vYQq3U z&%*#kbzp#^x-dXdJs6;UD0&+P zDB1-B6ukoj6uk=r6zzrqir#|(iuS+&MeoA^MSEd@qJ1zx(FZU<(T6ZV(S8`9=l~2* zbPxt8`UnOnIs^k09fkplj=(S|T5mDeCP4hAmL+gD2u0iI2kW(?7Ay0`6n$*bI&=|= zPU3i>=oGY2^a-?3^eMDZ^cl2JbQ)SH`W#v)`T|-gIs+{forMNP=U{-MFJXY9^Dscs z1sI^{A`DP;2?i*-3_{H!bc0wpRUW&wRiaq7pDbQArq}$QOn|(H)EVT>``}m6xmU3PsoXNxzh4WxkjqyQZD* zE)+R%yinu^Efo1f3q|Fig`)D%LQw^1p(p@aD5?l86jg#2iYh~cqAD;zQB@eA=s6gm zs2U7VR2>E=3WNcQYQO+RK`=m3Fbq&s69y=%1p^e-h5?G6hXIP}zyL*cVSu7~FhEg# z7@(*D3{VsT0~9rc0g6IlfTA!M21R8wb0GoZcbLDJR#uar)8~b3r)Fion4%_{R;iaz z)D*`HMa`gvqUO*-Q446Hs3o*e)CyWCY7H$EwSg9jUVs*g+Cqb(2pFI!5(X%Wf&q%6 zVSu7`FhEgz7@#Ny1}N$P0~E!=07WhspvVma6nS8PqK+^?Q5+0V)CmSCiiZJ;I>P`( zU0{Hst}sAR0t`^p4F)Lc4#S`*Trg=(Eu2rXdnzwGzbPL z%76ii2EzbFLtucSp)f$vFc_d{I1Esf2?G?3fB}j|!T?31V1S}57@#N{1}Msb0g6V$ z07YY9fTFQ5K+!lDplCb{gQ8xVc`5pb3j-9* zg8_=>!vIAKV1S~9FhJ2F7@%k|3{bQL1}Itz0~9TT0g9Hx07WZcfTEQ!K+!4~plCG= zP_zaHC|U~x6s>~+iq^w0D0*2le@cM(t>y1szakWkagf-cS(z`UXp5%()L$stisOZ% z*Pw->ZO}r|c4(pKb!egJ4QQe0O=zKL2eeT17PL^b6B-n~4FeSIf&q%&fdPu%g#n6o z!vIC^!2m^jV1T0cVSu8&FhJ2h7@+6_7@+7w7@%lB3{Z3c1}HiR0~CD(0~8&C0g4X8 z07XY&fTE)?K+!Q6py)UZgQ88E*`7!geaE+-%|g*){siQNW@WyZqE9rmY7tlh{8EB#CEVNK`4q7Ps5?Uxa4-JYgzyL)TVSu7bFhJ2|7@+71 z3{dnH3{dnn3{dn93{dnf3{dnP3{dnv3{Z3x1}Msd0gA4{07chffT9~PK+z8{K+#PY zpy(D1P;?sxDEbiwD7pi~py;G#?m>X~o#KVYQ$mrdlDMl`nJ=d37flg`&sMLQx?!DEb`+DEb2iD0%_|6g`CjivENF zivEHDivETHiWDDtYzIXu3{Yf(0gB8pK#>IoDAHhnA|Du_$O;1#*nfNf@BW z7X~OQ1p^e7h5?Goz%VGfrtkiUm?D24?O?i4R1U`rMdhJ| zq6*MLQ2?}1R1sPzsst?*RfZOdsz3`xRiTBV=b%ARH5j0%It)-02m=(=fB}kvV1S}v z7@(*o3{X@H1}Lfx0~9?E0~FPP0gCFv07dm+fTH>^Kv4r2peO_eC~61;6otY7MPV>N zkrM_eY6Jrmg~Ko?a`>396Ci$L0tp;HALB{?GLLADeXPtEQ`Fo?GY=AqTHtu0s3o*e z)CyWCY7H$EwSg9jUVs*g+CmFO5zsP`(U0{Hst}sAR0t`^p4F)Lc4g(bR zfB}kn!T?3RU>FoN^)c5WK>WVoL9CfjbeESPd;3_KFQ({4AI&vbDC&>ng`z}gp(qJj zC`yJFic+A3qEu+1C=FUDN{1GT20#l%1EE3DAQ+%10|qD>3jj|6peuaipIhKMdM(AqVX_5(MvEu z(F7Qv=w%oNMSXqD!wC?-wmiG;Clt-)udKb|V`aXWqRBqm{Gme86dW%UO@$VUra=ou z)1if;8PGz}OlYBK7PL_GDzs2E8(Juu0}YDi!T?3{V1T0eFhJ1)7@%k&3{bQP1}It# z0~9TR0g9Hw07c7SfTHCvK+y^qplBrwP_zmLC|V5z6s>^)iq^saMeAUIqV+I9(FPcx zXd?_zv$Y zDEb%%C^`wlplGX)`40lbZjye1Sy@RyBF`B<4Rrs%YfR%N76^f`_fioSpriq1d_ zMQ5RfqI1wf(U;Id(Rpa0=mNA*bP-x8x&#f1F2evtS73mmuV8?puVH|qZ(x9;Z()F< z?_hwU?_q$Vt1v)O9t==)4F)K>4g(b3fB}krfB}kb!T?3LV1T0AFhJ3dFhJ2A7@+7b z3{dnF3{Z3rhC$J%KIRAl#LuTBf%BPAG}TPvXCEu`#S}g8(UP--qI?`L6g`9%iXK4= zMZZA{MFr48(PL<#s1RBx`W;#*`U6@hdIAlKp27e{f5HGof58Anf5QMpid7!lL6Hgr z6q#UvA~Ot7WPt&SG#H@B2L>pz!T?1!7@(*G3{X@O1}O4{0g6h&07a!?fTA)mKv7v3 zpvVpb6gglR6#eRBo=$-Ho#fBa?h8ea`9~c6tXAfWDXL)Aw&e�XSYLst7F1P!s|K6g7kaib7$4qA(bs$O!`!HG%<(!eM}-#xOup z6BwYVDGY<6a#r(c0>p0>FAmP=Q?ZUKhr-)@6l??zi}$QRMFXC_lx1Cs1EB*QC((JRFByd)n_(E4VX<) zLuOOdh}jf1W;R7lm`zbrW)w9epr|0Y&E$P;?#vMQsQu zYD+*-I|7Q@6HwHFfTE5B6rE2%(FFt)T}VJtCjyEtBA}=<0Yw)Rd_}dx!RQE4G)nhH zXPKf8RnaBku=-L(mxbMGqfAjZ)|;ZsnN3l5W>eII*%b9;Hbqx3o1$LKrl>cwDeA*) zimqfv(NzQ#^(COF9|1-E2`CysK+!+~imoQ0Xb=HKg9#`aLO{__0*ZzaP&Ax?q7eiX zjU=FG6ahuo5KuIlfTC*&D7ub-qU#AL8bk0EbqNPM36N-6eFL_uDf%p1h8x0R^`(l& zhux8*P0<9_o1%%#rf3qgDY}W-6isF}MK?2>qAAR#=oV&EG?m#D-O7xjX#^DAMnKW+ z1QbmtplAjGMRyQTG?Rd$I|(S7ML^MA1Qgv(K+$XhisledbPoYVa|tM#M?leh0*dY> zplAUBMGFZiT0}t6eFR_8jp5*20TLahFA5rf3DTDSCw26g|ppidHh4qE*Z&T1`OF8Ul*e5>T{`fTG6;C|XZI z(FOvF9w(q^BLPKE5K#0a0Y#e#D0+&3qNfQcdWL|a%>)!ZOF+?c1Qb0_K+zTgie4a~ z=tY9BXlXdOM}R~->ZkYbH%0I1>qT3`VfCeowuN2y22-@1^`_`mW>fSUvnhI=*%a+y zHbrkRo1!PPtxhQsPh6@3?WTis}izGuBDI>c;>eqc65hnY>$kIbg%CuUQ0gxM7R z%xsE&VKzm-GNb4>0*ah?d)kho00BjD1QZ1cC@MfekxM{Ph=8In0Y&iy6eSQ)lt@5P z5&=cY1QewZP?SnQQ5pe7=>!x-2q=mYP?SMHQ9**Q=$mkGpa6-^$P_r=nxdanQK9&- z`cg$j;@#WEo1&tuH$}ymO;K@XQ&fW46qRH)MOn zfTD5)6rDyu(dh&fl_#L60s%#55KvT+fTBtS6y*|7lt(~OWde$-5KvT=fTC&y6jdjn zs0IN=XA)3UlYpXH1QgXK_=;lj!8HOT+OCYi$&B}(=|7@>lIX1Xu=-L(_2S*PCYqx9 ztT#msm`zbbW>eIN*%UQqHbqUCO;J;3Q`C&v6g6iyMJD%b*%b9)y(#L+Y>KX6HbuRd zO;K-VQ`Cpq6kW+|imqZdMSYn~Q9ouB^(UZc00Bh<2`IXnfTBSJ6b&YzXb1sCLkTDv zMnKVU0*XcuP&AT&qEQ4CT|+?8Xab6^C7|d!0*bCDplA#MMK=&oG?sv(8wtLmZt=lJ z0wnrWQGs*0DXOca#>I!#mnxbR?{=SJif&@PDVoe|if(2$MN^nf(JjoTXezTQx|P`! zO=C7iw=tWd+nG@`oq(bl1QgvtK+#MBitZ$!XchrQcM(u@HvvVn2`HLFK+!z}6wM`| zXdVGY^9d-rmw=)L1QabKplA^RMfVXnbQ?!cN6s=}9MQfN%(OPB{ zts|i5F#?L#6Hv5)fTG64iZrGH33E65PU`3UwQu9Y>Pr><5bxHQZi)`G-W2`F zY>IwjHbqC6P0`QHrsx-DQ}ipdDf*4s6gdg@yxkN9m{Al*Kv9r@q5=dIxdar22q+2@ zP!vxl&a(GUWPh7wRTjDVuy1Qd-RplBokMWYBPx`u$F(F7D-OF+?e1QcCQK+zZiif$mF zXe%M4WLRfvNqMH-kbLW_%DXcd| zw=kQcsm!M6R%TN)joB34#%zjiXEsICnN86QW>a(rGm2&sP;@5&MY9Mfx{H9Ky9p?o zO+e8c0*dY-plB`uMe_(KnomH{y#y33AfRX=0Y!@lD7ue;qQwLhEg_(2DFH?I6Hv5_ zfT9NozM`8Ff`bG|w5k5#p~U(WnNhTXfTG6hnMIWl7R};eOOBKD5;J!WI6urrMQ}hWIt0Y%>sQ1mSUMc)xn^gY2>^m;<@R{;`@=*!hROi@35 zkaQ>^tiDvyPYG_;LQ`~v^`_`&W>fSFvnl$O*%bZ8Y>J#jd**J60?ei;j@c9inN3jv zW)!&u6om*V3KLKiPe4%u0Y!-f6eST*luSTT3IRo_1QewaP?SzUQG|e^C;>$o1QZn{ zpr{Z5MTH3{iV;whNkCB%0*ZOeqIM*@n@C!pv8 z0*Wpqpr{i8MHdlJ)R};yiwP*Ygn*(;2`K79Kv7o$iY_Cds2c%AmlIIboq(bq1Yc33 z#Nc)T5}l`aVvSAFE2^kxVpx5tqCSc4*Y}&ED_L)fu3|PteVI*BKW0V>j)^i zo`9k;1QgvsK+#wNif$yJXdD4W;|VC5KtRz%0*WRPP;?W)SJW#pSa_KzT3B4*^fpB| z>z@IcoETPLs%UDWTXVT7x|Q{&Xd1IAx{cWs-Og-^rZbzO8O)~W4rWs{li3vA$!v;d zF{9`%0*dY?plCJ$MRN!!x`%+Gxdar=BcNzL0Y&!`P_%%6qJ;z$Eh3=kJ_3ps6Hv5- zfTE=Y6x~li(J}&x9w4A-IRQlv5>WII!B;dTF?fjpiB3%wIJcOh>iQt*;l!}|Qbj8h z-D@8*MXOkEidHk5qBYE>Xf3lTTE}dP9%D8|>zPf_24++AII}6*$c&;V2q=1zfTB$V z6g@>i(bEJJJwrgzW&(# z6m2J<=v4xWUL&CBb%L+xk;LEv0TK=9=dK?$MRQfrj>NF~Qbjux-Dg&qqPJOZir!&1 zMZ1_y(Qal_^e(e0dXL!@z0YilK43OQA2OSwkC;*PF#$z;2q^l5fTB+cDB4Rv(LMr- zJ|m#$a{`L?6Hs)3fTAx5DEg9sqOS-jI!Hj#*8~)OLqO5D1QdNoK+*RE6dfX<=m!Fd z4ikJuZzcx!36SWs`o})rGDS_oGW?hrR$r>e%O*)w-j6ks+* zam=PD$ZU!VFq~^j5l~c^fT9=yMVSN?6(OLgC;>&q2q-E}Kv4;Tujoi(Fjs&?+m;qM zKbxYEzIaqJDXhL!QK=-i&1zFrn)Rlr46`XJ%WR6uF`J^(m`%~?%%-S3vni^;Y>Lic zHboVgQB;Y5qFe%s@(3uZOh8c;0*a~Ql&fTG$26rDvt z(b)tP)ghp$E&)aL2q>ygKv4q%iW(A7)QI3K%1#On5g^gC^_hN7lK)KqbS2d|DXhL! zQS&7CjwOJ-Aa4znq0#cYaNGn=AwnN87o%%-RfvnguJY>L`3qo_RrMI8tz z>PSG*`2-YQKtR!j1Qc~5py(n3iaHZebTI)%mk>~NDFH=Y2q@}GK+$Cc6m=t@=yC#z zx)V^;gMgx*1QcCCKv6G(uc&EKaJ>MDuGbIAHZw&f^bdseP713pRn#}h-SwC$>c@Ih z)SuZD4PZ7!1DQ?H)y$@75VI*7%xsE=Fq@*G%%*4=&|NI=mz0*b~HP&9#nqKO0)O(LM^CIX5k6Hs(B z0Yy^?zM?CWg3fwT^o#xp>#I!BYw|nymZY%yQbo5VxjB!UqT5+-il#H0q8ZGl=niI6 zG?UpB-N|fSU-OQ$FHZzLm5Kwdv0Y!5OD4It=(R>1m?j@jT0Rcq|2`E}b zK+$~!6fGv8XbAyDO9?2tpMaue1Qb0$K+$pniXJ4O=ph1%9wwk@1p!5m5PU_qCIy=b zkm$SmfO?uK+EGY`N0Y+pOBJn2a(g{tiq^8;6s==6MUOF?qV>$CXaln;dYsu5ZDck@ zPcWOJCz(yrCT0{pML^Nh1Qb0(K+$Fbik>B)=s5z4o+qGa3jswh5K#0Y0YzI0D0+#2 zqL&FMdWC?ZZ3Gl;C!pw60*YQEpy+i1igplC^acS%ZxVb(tCE6K1W2@izUsKz6n&#R zrni#9>Pr>vN^&3EWQumP-W0vdY>M7vHbw6C^|qu(H8_1eMvykR|FItB%tVP0*byNpy*oyioPSD z=z9W+4iQlF0|7;c2`KuJfTEuWC^|y$6}_Dld`*Bvck0X4@0gs0|JT~5>V8LfTG3(6g45Bs42l$R604> zMSw(K*1vhCOtSw>f2qDT+blV(zEsgU$?o;fo1#{%H$|~NDFH=Y2q@}G zK+$Cc6m=t@=yC#zx)V^;gMgx*1QcCCKv6FOih2`J)Q5ngD+#`$7RkXy0wlV;l)!0e zic0F!{;QJ1>Pr<3NOqrn!4wT-y(zky*%S?8HbsM(P06b)lGMZ=j*(FkT! zG?E!bqX;OvhJd2c1QcCMK+$ys6kSh1(HH`XZXlp&ECEF~5>PabfTHmP6ipzYXd(ec zlL#ofiGZTX1Qgv&K+zNeif$pGXet3kw-S6s{gQ*93y|nl`nl`=rf7*OnwA_^U#e(E zvYYghDY}F8rf4R!DY}!{6wP8bMRzfqqPv+*(QIZ@G>6#~-NS5(<}#yb9sx!32`IXk zfT9Hi6fGp6Xb}NL_YqLEn1G@s1QabLpy+-Aik1;j^Z)@x%LyoYkbt6x2q=1(fT9%y z6g@&f(W3+utt6mm6~R|@dvdU{0EzC=&s|S9MF;eA*Q=Am>PrFOdHbonmP0tvBW6?d zF|#S!!)%H^VKzmdGMl2k%%*4`Gm1VVpy+b~iuMywbbx@OF9<05l7OPG2q-#8K+)F( z6n#TL(YFK?eMdmi_XHFjBB1C80*Ve3Q1l}KML!WxbcBGSp9v`Xg@B@83BID;$-&13 zNHkktb$r(py{aD*`7JrDzEn{##eG*^&o0=gvf~y=Iq{jk%WR55%%&*JY>MKUO;G}~ zDN1BEMM=!2D4E$5r7)u?m4Ko&0*cZJD2fnJ6eXZ2gMgxf1QZn_pr|kbMKJ=3G6^Uu zLO@Yb0*ZR zfTBhO6g4KGs0jf@O$jJ!MnF+>0*YD?d`0C_f-M9{^b>t@f0`*OsqcWaObM$mRdjBO z+vhD)bRO$XQ5$Ac)Rx&4wPQ9#?U_wc2WC^$k=YcT&uoe=U^Yb;GNY&y0Yw)PP}G@# zqKgSAx`cqDO9?3ILO@Yh0*Wpppr{)GMVAv$)SZB$9t0HiB%tUD0*ZPOP}G}%qCNx^ zT}eRERRk3EC7`Gu!B^BOB{)@pM7QfZAgxVNbA6E1KP9ZbRMDUm_u;oq(O}k_q9M$t zXehHO8pdpjhBKR@5zMA&B(o_R#cYbMVKzmhnNf5t0Y%plP;@;3MPmpkx`BYAu>=&| zNI=mz0*b~HP&9#nqKO0)O(LM^CIX5k6Hs(B0Yy^?D7uA!qNxNF-AX{wGy;llBcSMZ zg0E;`N^pk&iEhw4v8zqdjj1wBPYJ6pRdi>H`~5CcG>i47=q_ecbT_jpn$2vA<}jP0 zdzekpTxL@=kJ%K>XEsImGNWh#0YwW5C|X27(R~CIEheC72?0e*2`IXsfTCpt6g@yd z(Q*Qc9weaXAp(jXCZK2q0Y#4xQ1mDPMJov?T17z7Y66PZ5Ky$1;48W#C0KN~C^}Q$ zfSqZITIvhg>r%q%OBFqy;-3AUDcZ<-Q}hJ0DSDFG6m4QQMNcuCqNkZn(KF1ZXfv}Z zdY0J~J;#iq=Lsm)&_1!4y^32TAXy zgw>ZS`Y^@4;R93j5$jFS$IPZ^53?!ygxM5*%4~}EGMl1(%%fSzvnkrojG_Ys z6n#NJ(U$}ieMLagK>~`tCZOmW0*byRpy)dSioPeH=nw%#KM+uKn1G@m2`KuBfTAM= z6#Yy<(JurP{YpU5Zv+%MsrJMiMFE1Z=>3%7VgV9ep&yd{z!X*1w?pDm!|F>Fg;L$; zKQcvO)|;YuW>b{FY>E<@O;HlFDN1HGMJddtD3#e1r7@eLbY>Jq2q=mYP?SMHQ9%NV z3K39Ln1G@f0Y#Yv6cr($s3-wN#Rw=WPC!u!0*Xo!P?SYLQ8ocZIRq4yBA}==0Yzm9 zC@M=pQ8|LIs6cA)fB=bZ)u&}{s{c&?8vUz6PfHD}FI99#s+;nODXPeNQ&frB6y-9T zqC93(RGHZnRbe(oRhdmuHD*&(o!J!CU`ElI1QgXIpr{rBMYRbiI*Wj!vk54wLqJho z0*dMpP*k6Qq6P#MH6);@5dlSw2`FkpKv7cyikcBn)SQ5#76cTvB%tUV0*YD@d`0C` zgH;7cw6OjySQSjsYJEGTb!u3BsiL;2Zil_5s2%G~QF~@n)PdO)b!0Y0=QEq43z$vO zh0La?6SFD0h}jf%W=7G)1QcCDK+&ZH6m=n>s4D?Qml06Zjew%d2`K7LKv53@ih2@I zbOixLy$C4kO+Zl}0*bCApy(HNIyJ1mRMF5>_pZ-O(J(+Mb=K|s+R1YgnM)Zh~WBzmUai48GD1H30}sbTe{itbKz z-`{VFX0zTD&0#i0_b{8Hxy+_$9d6?8AbOIP_&qUq9p_r zEhV7negcY?5m5910Y%FRD0+~9qK615dYFKs6$BJLLO{`@1Qe|#plB5VMXL!YT0=n5 zS^|pJ5m59P0Y&QxzM@&F!2$Wxq5f%AkZ>Kv5egVeD4Qbl`G-K!3oqEA?FiaupFMSGb|(LQEV^ck}$ z`kdJm?PoSc2bfLK7tE&UOJ)>(ML^L(0*bySpy(R{ioPYF=sN<6z9*pQ5CKI$5KwfO zfTAA>DEf(jq9X(p{Y*g7F9a0*N!MAn<4BxX~T%xsEMm`zbCvnfhrHbv>orYOQ} zilWS>D1#YA1qmoBL_kqt0*Yb;6lD@nRD^({q68EbBcP}_0YxPUC@M)nQ5FG3*#s2j z5KvT#fTGd_6qO;Ms4M|RKKdo1&`Brl=aTDXPwFifS;MqBEIIQB7u3RErr!wFxLX zi-4lD2`H*VKv7)+is}(iRG)yN1_Tr}B%r7f0Y!}oC~87LQBwknnh{XcoPeSh1QfL- zpy(U|idqp+)S7^za|tLqkKik+m=-Mly(qdy-}Io#d&^`(kBq`7r}Fhw0% zZ;H-mHboaOo1zPuO;IOiQ*;rtDeBB@iY{h0MVBy}qDz@k)P;bet^^caMnF+F0*Wpt zpr|_mMLh^8>PbM+6$BLZBA}=@0Y!ZXD7un>qN@lf>PtXTKLU#S6HqjOfTDo}6kSa~ z(I5hf1`~Wm?b3pm3y|n;{a{*qQxwvt{X^2i>Pr=kNON!e(G-njy(t>SY>KX7HbtYE zP0_W?rsz6mQ*=GEDH_9Uif&*wMPr#!bRz*p;|M4kPe9QG0*WRQP&A2vqMHaPnoK~^ z%>)!pA)x3M0*a;*P;@H+MbiihOX8kQDZ zDnO!7>z&weQ*^H?x+^WLzEsgYY3>V0OwnA{o1%Hlrf5F1DY}>06fIyjMGKit(IRG3 zbRV-RTFh*UmN27eDFH?I6Hv5_fT9NoC|XWH(SrmOJw!m!!vqwqAfV_G0*W3bplBrl zMXLxXT1`OF8Ul*e5>T{`fTG6;C|XZI(FOvF9w(q^Bf(cRJ1zL70Et$W(Vb(8n(Kq4 zC(^>|OBFqx=BE8>ik@M;Dca0zik@XQMb9ytqUV`S(H3S?^a8UfdXd=_ZDlq^FEOL& zWde#`A)sg*0Y%#hD0-EEqSpv0dYyox9Rw7;K|s-)1QfkRK+#SDiryxm=p6!zb`emt zn}DKs2`GAxfTH&aDEfeaq7Mlu`iS5w+LRWoEGZ-HbwiHP0;~nQ}hM1Df*Jx6n({PiViZHqOX}z^bG+;-x5&t z9RWq(6Hs)BfTAA=C^}3)(T@Za{X{^~5dw;SCZOmS0*Zbmpy)ROikx(N+K!?C0Yz~H z6a@(=DnLMyOF&VGfTA$LSM*6*aFhUv?$h_tJ~c(ycKv6vcis}a(-Gm5$qP;@x~McoM~>OnwJPXdarAfTuh0Y$wDDC$E%(Uk-gT}41qUjmBy5m3~h zfT95e6b&Sx=xPFr1`$v+n1G@o1QZP=plBGuSJW{**jj)@SLyp`=bNGn^=bd`^sxF; zMc1Ue{Sr*kXx5veYne^abYkt8ATHaD4Iw> z(If(jZX%#)G66+56HqjTfTCLnD4I$@(X9j&O(US_HUf%nC!lCL0Yx(iD7u4yqL~B~ z-AO>vECPz|BB1DQ0*Yo6d_^PEgSQKi=(pJdXOt-l=tueIq=(g)Dw?0}u1qpT_p;s; zEnqf93z<#PB4$%`AG0Z1%xsF5Fq@*K%%d6`8AT5eP_&$Yq6Y~mdWe9chY2WJ zK|s+X1Qb0=K+#G9idGR&w3>jTH3Sr`C7@^>0Y#4yP_&+aq74KTJx)N;MgoeSAfV_; z0*W>fd_{B9gF6LCw2i)vKaYDfRrFMPSbeFYXVcvuQ%uowtT#o^Gn=9<%%fSc zvnkrjY>HlDHbpNpo1#~kP0==H6m2J<=v4xWUL&CBbpncZ5K#060Yz^TQ1li7MLP*7 zdYgcvcL*rjML^MR0*c-xpy)jUiry!n=mP?ZJ|v*%BLa#(CZK2!0Y#q>d_~Ws2TP`k zqR#pf(PmS0v%VYqX?j?FsiM!*-TLXKXg}*s(E(;t^aZmi`jXiceZ_2w4l-0@LUl+Jon6k#?+^6&M{mZL5ZFhv>6rl=sZDJsNliV8EEq8PI&%49Z0 zMVL`klz^gQ1QZn~pr`}^MI{L+$|9gBn}DJm0*XozP*j?LqA~;&l_j94905hA5m0nG z0Y&8rD5^j}(HR63RV1LO5&=cI1Qg{Fd_^gd;4%RcUE&Iy)QJB~|8afQv2rA=zEn~5 zh`Y6*DXPJGQ*NqT0-+=qzSabT+dos>5uG>N1<6ddw)QPe4%v0*V?E zP}GQkqQ(RiH6fs=DFH>z2q7lAfTut!BU(Im`%~;%%-S2Gm3f;P}GxvqALg}>P0|NZvu+?5Kwd_ z0Yz64P}G-zqJ9Jv^(UZc00Bh<2`IXnfTBSJ6b&YzXb1sCLkTDvMnKVU0*XcuP&AU@ zE4nZeJX3%~*XpC|PNwLs92rJM!s<&ET^DgLEMkhTXT2#J!)%IfU^Yc#nN87+%%*4@ zvnd+SY>Fl@o1%%#rf3o~if$sHXfgpsHxp1ag@B@42q>CLK+&xP6ip+b=r#h1ZYQ8< zIsrv92q?OPfTEcM6x~Tc(JTUr?joS*ZUTyC6HqjVfTDW{D4I*~6^)JrM+=Z>A$`^H zT2qv$!@NjXeW{{_5%->Arf3oCP0@YKrf4yIdTFz{W z9%M$*Lj)8(OhC~J0*W3Xpy*KoidGU(w2FYD)dUo+A)sh20Y&QwD0+;5qV)t6Z6KiN zaRQ1q5>WI60Yy&|P_&7FqNfNbdYXWuX9&Kcdn3W81xR#5vcOqjitbcJnc9`q8C_iie6+kMO&Fo(M!yx=w)V8^a`^n+Qw{(wlkZeSD8)GYs@Hmoq(bp1QfkN zK+&576um`2(M|%2-X@^v9RiAW5m2<7fTDK^D0+{8qW1|X`hb9<4+$vxh=8Jx2`Jh_ zK+z`z6n#oS(Ov?I_7QwV&qadqB}LJYVgl!RQ}l)Ysm9MDVfCeozKFQxvrW;LtT#np zF`J@;%%fSHvnl$P*%W=pY>K{THbsY+P0 zX;~!dKhvKpc-(5yu=-L(HKXq8GNz~&>rGK@W>a()vne{8*%Z}bHbr%rO;J5&Q&gYX z6g6NrMGcuz)QEth#sm~KA)u%!0Y%LSC~8hXQ40c!S`tun4gp222q< zmnym>>K-X)iY{fnDeA&(in=nJqRW^~Q8#8&bUCvr>dtJ6dN7-!p3J7`3T71bBA}=@ z0Y!ZXD7un>qN@lf>PtXTKLU#S6HqjOfTDo}6kSa~(I5hf1`|*;gn*)<1QZP;plCP& zMI#6(8c9IWC<2PEA)sh9!B^Bd8q7XT6uqyXyS~^IZP7o~cx^PSzEsf-QMX}vQ#6+K zrszgyQ#6j*6pd##MH84!(L`obG>O?1-NbB)CNrC&o0(BGg@B@42q>CLK+&xP6ip+b z=r#h1ZYQ8!_9n$u%9 zN`H#+uf0oQ|=Z&vKkju~+Lj&Ly!}eaE>hc4j9IH0Uakj)pj&_`vVozS@INM|H4UV%T*6K#b*%`ZSyyNVS zy*1HsK8Tf=>^OU3-KRLtzS#X!9p^yot7(pNFjix_<9rvp<_^a>9DC|c$N4!ke79`> zK<2q~^c|+m>2u{82xPuJU#@~cX4XQv4g#4y?~^Mbkomw8xfTMMU*9iRLm;!}a=9J? znfkBUmkDI*KSzFgAXEQ6>573&{Re?72Qu|vbgdr9)PIt*Rv=UVO~pEaO#Mgk8U!*Q z+$2{>AXEQYsuqDv{da|02Qu{^hG`qf)PLEdV<1!iX@*XLO#Qp{F9~GoUygoRAXEQ# z>mGqj{p*Q)2Qu~Vm+c$K)W0BfU?5ZfhQ}d+O#LhRMg%hT?^qih$ke|iYfKTB=21DX2b=?8&Kef4WkAX8ty*cZsu=br}x znfe6cU?5W;0e%8{~T}<*T@aUUF6^7ij+uqoKW?M{vF{-x5^c}OKxIC z#f$U4>lAr5TYgz1@}jh2D_ptOt0iT~0rkJOa*GMfsoFf?6rUt1Q0;789q;{4uI}dY z56}myomW$S)l6DF`6_;PDQ*3p-nk!Ru_1M=C4itHeIJG=bXQ0mcU%XSjToY*|v;S#}I#ipp@d4HI>!V?%d6 zlXY##EGQcD@(cCr^d41B-??z+?+Jz!d-oAY5 zwb_C8ZgO^mP^0WX2RHen+^IF49NA?!^<_;~6I^gFxvsPK2M^18NOJ{AeyoMZcWT%-W zHx=)AUna+#49Pn!?;&S7@&`Jz_EKiw{coZ7RX-iPrk_MAXzASc|5tN(@kTgxw!Z*;Dge2L``$u~PUN$zd=F!@eLc86I*ET>hr3%}60NAeiU<;V{@OC(RR zT$jAskzHTbEXy6qPdQIYUS#Gsy`9q5+TT``ol+?B=3}osaEeEtQ>eC+kVoy$cSoLDb8tJ=?bd&w+o|rho?63h1pcY+vs}*4p@^O8ch>82aQ{>txeL}Ud_D)C z>R;Ac($&yp`h-W9&GhePHy?QaO|d8{_pF;UezbRAdF8U9#htA7vPi8w&S@+um>gBe zk=bKr4fF0@uY533skq7S^v}3Tt^qrluUYZRh)0Wix?Y^S`yu~Smc6(7Ub&AJ`?v0X zXZmQlE!v`TXWF&@4rCtT;gQCY3Hpoi(a^K z*R663kh}gLN1R{DTQlXsX@~Vz<|fbCRVz#GUS*ALoPPcqy>0z$Y0R+{FZc3#sOiU2 zVM|N>6l~ClT-28*PhaF;4F@`$(?)LpvdFvrv*`Poi+#d^za@C9+|!M zIo&jF@>RFY@93TWb!YS|=WWdgFW4A%vdYPGRz00dS@QgiJKps-%*=zYs{uE;NsG`0 z-jY5)eOXo>)X5UPatHcLl)!g(EQ|c)CfB;4uPP5kzI}d$UO93sUuAvL)4SjwZ=3v# zY^~Fi{p;~Df(@J7w<@ z?!If@$FgDN5;nRvM~+|C+sGP?B;sTcg}D=qbr_;jB$^Xg#G5IrRE(pPAra zrs&8*wdKH}$n)>L@Re*vIjQzNf9>q#R7|tW)K-4b#j&$&gS$$bAd{B_Zc&U#8C zIi;MAa$xUHt-md==C9JLP(M(m=eZY0blcJ~@5nio4RqkEJsb5d(oO!p#6sByaxUs` zAJfRmnqwzE+h5}*_x^t872c9*dsl8#@1e+yWn=F0Hd18U%K5|PaezEG(lfk`H9yT9 z-pN~YXtlWT);zmvoo*yKoeOW@)7!~9By04%1<&>_q?>&C&daL%XYJ$3tNfkY+b@1~ zNZiVr@|WF`BoE5v{VYA58myUexJnCI<0emd?9F)Z(v&^ed8oJI;UA-MPF6Enp{LTD z6=zT1E)O+iSAAshi#@zEw*S4iXZTk`Z1dNbJ6WUbL}s&O%!V&yUoP8h`?!gE)0AyC zcgNSV@#K8%8Jb$h$-3K?Z1jZ=H6n-2KY) zAiXdJ>e#jX;zQ5vlB1UsdVB7xclsxE&)QET-U&4r79HSZEtWOPKIX5{>$tbPuC7PZ z#7}N=pN$(5LYCG=~ z$L~5IJBBM|g&zGfR$OtYW14p+=S|qLU#})Nxn+e*%XpV;<8A)P-iKdq>0}L)HF}K|t81I(t2Z{Skpswi zT-rNFHb#3l^3*qPHuX;M!x^_eDtnN{b~t;`xB=;ci*rLZ+biqv( zvb{x99=`8$IjAg}GIiMpdVxg2+b`}N5(&u$$xw*PpEcZrJby{w9NI-7;>io;SIc3q0M|JDK@&wj7rIbxB(@(O(may!h(vcZ(L;a%UfIH^5snxBiX( zoy(R@x5}fEine3}OYZ;Vn|I~d<#fib`tf#upHi&yX;*n?t;@=vJ2_cr*_wl_`FY`n zJN*67r;87KEn7>r+sEr>&hT&SyVf?U?_^zOi^|luO)zhJ1vyeVokeq>-ll8ZC+w+}$Z_My-VH3Ob zliizlCzew{7I-`SbX(cPUnzHWS>MQOJ91fP%y~vmTDH&h9Y56dw$HW$o4yhB6=aFt zGB5O(=>DUN9m@oc<@zg6JKZ~$!1}Lsi@C`!ZMjb#P5FC}HFogz9Neu}=4$VfKXc0s ztA&mne$%X?ayyl4<=d@Wr^>0mW~ch{u~VHZugB@7j%#R_dfb|+_v#fDiahnxJCErW z3`KUm_le$l=v~GO>$^KyU&>2Fy4h>^i^OQ+8zsFpi=Vq;r+?am4}2lFEm_jNb%a9i?1NtT$)}Gr%^!e z$K}PnO@}7VlJg)Z@x|xa`p7jD*}UTBU3wa_73aLU_*y6Da#?hREXtZ<$5_H&?H%J> zJI1ztbCZjI)a6X?2>b19*4jJ5<=-9tP%o#OTzh?L7bjFGZktdkv)|aZ!?TMw-KX0j6!~z$!P|WWdltVuTaH=IchC(C zme<2L^uD4GS%grY1%4U~&=lREX9~^&;lQT`0c&e7!(WS`CjP}}x zQ^r4QIevxZ`VY$G4E&ka zx@Jq|VVP|02`{gGOG%0Oxoduty|`@cmY?ROIa!l!O~Iz#rF4@QjDAJexXGV=y+-ef zLXppI{c5tHkgN5DH@~?@_AGPD`lr)^H3M7T-OF3krATFYElAg_nX%emGkfOGZ^(Z5 zS6g$Pza|uU=$@C>`{;I#J3PgwFzdnfx9FW~DDuPmE60l7%ggzvw31by9NIQs!OIIo zM_xSW-yJ0{-PpxjwBfsVw#dVU$+AevKj$w}Kr=19eJm}obl_Ne$kK0?TFA~%(il0e z>dox7vf`^%x-n$?G+cgDd+)No_~>`@b(4l7KOJ~?o?ObDluOnXk!34i6*{s--~8>BPxWRJifp~* zmsxV-8fB-ljkC6H_6oakjoUwSlD}h4>Nm^v7TvaQ)?4xjXR<8P%M+9@LG30VS~JFf z{PouK+kR86p~&pV_N~+F&P~3ue$lp0sik&8-r@Td9X-gqD7)T2RLi?40~buJt%r{6 zcsP33FtPN7auEFr1?4x@xHTLtp#p(mYQ3Z+`L%zrfW+|WvZ}Z|>yGz+kQcHNydOf2lW0fi z`bU@)2(--5CCNE*ba}EQB~4CTk2y6Xkd$=nIMY&`U_9p}DJdl>IjNQ$JUw>8p(1jq zM3V>KgeY(QvJBotY4&# zJUS}sT^jjavD`rYBAlbsinPp#1frn^nRhlSqGzDEybpEs+{VS$Hj<5B;`n2;R`U3! z+coQ^u>rZ_s(70&d-7O$_>p;ABY7;BBfoI;7mibk!-$_;N6%OPRPWT}aycjdC;KZW z;I!3m1q5cCb6X4jo-ALI^_#wVsrkfp{v>xuaTmOEwJlT|$ z?e&`-q$3B3a{_U3@_vf<|9UW;?3eo8`- z7t0MzzjUpB-yvVJHv1Ymtp2>ypL2B9pDW8NGyGnEt|wo*R=kCMO5fZ|}($m+VXV zxqu*)UtK2;b@eOg#Fv>@SRSwHmpAm4_lgI~mmd2n`M$>cxxu_GIr1j6d}&`J8rI2| zx8Sm}j-y}tizno}e#tMg=M|TG0{xPq!92|9p%hIi&(FnN#jX;Nb7l~ZUBhw!uH;p+ zG4;zkXYzfGeCdWAEE`&Xeoekyr;UzHWNYb{9#p^U3ruXH^m#f>J+2g-r_%zz1k_By zd9TQ3d`-Ue81(xXZ(SrG1Wkw;NCsj=i}2;NJ?ww*9AvIsU)n=LehX_3)Z3i3=P_O_2@l-QMJO z7Rb%b8`LfDiopZ(1`q0m62?mfE>95i4^&+bEd_Q>l#Xym{l12lB+*<KM zuV>Y+gNF?5(Pu#3kO2ewcJJM-PyfMry}Ebr+HFw3yegHuR_j`|a@8tbt5nulNn)k` z1N!%@)U(^=eJWL{oLjAu{yJBFeZsHu`t9y$2hW6<{pz(k~Ju4mE79)lX@-~UTMcNJ;aHVYX!Fe49b{lk6v!VUFc9hG~t8L$* zgS)nGc;>k^xSHg`{s)i!-$5{}+mN1mT{w<0s@g5LyXS9FxGHD6 z(ULOeg)-cXEd8NwUN1L8e-*0hA0$-Ii7OB&_Z<6P%0Hbn|8&aO>3Czd z9IUDvlQUVklD8t}t*m^)in7PA$n{nf2?biYu`KyH&y}C+{_p4iZHIgqa0}<<<+-sE zo*N(O-^N-vRIrl5LpMk8m&)bl;U>tc7RN2l(X%7u3+Hg|{c{yJQT`q*@78Iznv>rK z+`{!Low)GtoSVvdCH3a|`wPNR(DQM@0&Ys_U?f*|2z~Vyo#SRoDcCE|Ehd+(XpUPf z%T1A6YEhX|LU!ZM(94(RmbV+XH|EN(tGXq0QC+uKrQ;UanXpBtAHOKuO_4D!RMq?c z47aF$Z)q{dEv;j)U#^>}KgfQ`JDBWI3)PV`c(RS3pS{n&x#cUJYQyJagJ-xgxq2!d zckKxv*=z}H-BYsp|KqMxZn|zv?<3%ukFBKJ!|voxe&^%e7iGKNFZGV4jNW5ab`vVO zg8|Vo6~Wb(=kLW zz32MlW&95uUiZ4ERHJ*{e;b$FTKwbqBQ9^3+r-tITU_wmD}J{t)|wp(o|&z;r^>o( z{OjA3NcJ8z>TOFN{RvaOuI$#C5NfDbrleEe`t_mb|M7$69sfwI{N0nu z-N8S-WBspe+LP|h-2}M_>&{%n_*eEHxTJ&{oJIj3RNdBoEL;f#w zFWu5P$M4fmc{WeBM?di%q0uSt5%Pb=^nB&z`+WVq<3086SMGM%{mLHHy9O`%vps2w z?Ah|MqqZZ=E2WR{|NO4%@7zV@<;c^8;>Yn~Z~tfC^L^ySfP1L!?~i~hSam_9flM6<9%Hym{!Lv zDfd1RxkK{5*R}6Nh!@H|is>s&eclTgnePZc1hEh9YO;KX$+EVb_Zx zFAw=dGOARR2eW_9h0E-JFL|!q;g_mXsk}m&movW}8n8di!o2Gb$_My1(15%%|MG$F3cHJ@WXgR%Gj@j^%n= zyGAHDk{kJ{Z`9t!&ELfy9(U1Efq#0zlm2+YPq@d(=k5Y^`8@cEJ7Q0vYz*&7nBMSt z^1wFE=fU%N;`un3_mF^7&(}3v_#E%*wX3yIL)l+7w_8PBZ$G84UX_*$Sx6-5(~3gu ziHpfqDtqrL`c1kw=E|?Dx@Bc7Ro5+DNhbffNFn+7l^m>)f2cIq+b}GWm+^fa-v4KK zJ3o2d%8xnT-GleKmF}`+-=w>&xRAGRk|#@rvU}OtwaxQaxAp%WOs)v;Ue>nTsc*M( zb^g8k?*CmIzk4wAzYTKo4f3CH7gyPy2mQa@5AfLTlzSKNfo`_{I5$^zv}J^b?6LK6 zu74ZL=fjm#o`^hrwqxVbc0LdO|L|ZZ+Yqv2myIY7fkHVK9lZcqavz~jA1cWAf^t6* zs^{Ma$-PRJcjw|iP`dHDKY64i@1ywl7NOvc!8-bwD6g_xOdhxvlQ(LPdrqSdK=mDB z?>WuU*Y9}Q_xKlwOVx4pEvUHQQ^T%s&+w1jb@h9;KW6`KQjT%*kj*)lq%BT3)TmkTd4}EblFEQrxYPgedoRl?``*Ei zEwij2f`|(Rhsgsv{mG6_`6kN)t`k2#(b~$cq%&rQHlqy_5)VHM_TfLLSJr`n|4a@++4RraD8a3zt!ZSSC(wUyo=;F`$lB<3Vx%{9fR**H>8)8 zmmIk>hy=%8pKXuW{-MW^!H43;_6pYGSb1>G1KPiO=5XB0$H8CSxJiLPFV_tg33&H6 z`FgnH-Hl`)`v_neSt_?h|BhYv^rimsJ^f#vBo7rT=li7fQ;2_j$np2iy8oCnr<9wa z$7NgoFFq;RN*Q{Pb=o(|;*A&Heo=!?vUM zKKCJeVDCY0@_3 z=y&`l9rCxa|Ba7W>O0EEK457(fs=m}&40WZbF<6KRanI>=6#+l!@B_%^FN5B5Budq zaPnTKeAGogR;C-2*OyOqoPiTQL=xA~UMM={5;6`b%Q>(7uYQD9p79_5 z(Mc@kW7GaCr+Ly(lvI`-^|33JbHMj}os&Fy!RPqTmigD^-#Lo>!#e3@sFGJ9=OkyL z^vOQH=-p!2ubkw=Gr?-!D@Ft=Rx~F;H?LEHZc7y)!^M3dHW4poM|K9d@f0E02 zr=l-m{NYV)c_c0GX`k|0=Ls9x_K&upyj?19^gpRxT3J}@nuOlA)NU2u)nCFR~ z=g9Xvbo#dYf910{$G@BTm(RZCT+010pPtY+i1}#1-_tLvybtHPiNTky)qQB<$J#Gv8HyTcjH*<5`N_=!B$1NeBF$hIGdx205pJJMuKbhIwLI0kZ zcZaPXqp&;Z-~ay9G8K@22VFvcI`(Gw>A@8Ly?uQl?UX!aD}ada@+>JJ7rc;N)Y5r$>PA@M=tV90?_AUe<@wuJj{gMCm5+*?_#$1s<6eL~_Y^NcMnf^ZiDuVu zGlC=iS7r5fnc=@Oc=8|pQ{s7q-Km}W1$9@RHnfx{AM*5DR{v`+Z2!kzq7Hb^&Ac}o zjy|Q5Yv$M=e>>?bsDJNWf`9QM=ahA$#r*B2FEB@Q><{eOwVl7`p8w|S%W~G`?GSwe z`ggXDyhkI~b&e}fll@C@6ew@l_>A&(5!_a8hVs!rq2({bJMaJa8ui5T{ha)`Bh~kd z);&M}w`+4t;sf)a~0sKpyar{&Ed|k?D-MlJi$y1lIa$6kE zJ0yHBq(>LmQQr2_H_l{#?{5db%T?n)NBYY*OY*$kPr&tdL%i9M2^S@}PW#EW4~* zLT`Eg>xB~j?8g(Y+7m9EE~@Ii7wN73d*>tnhtBuQWQygaTU2%{0k@3YPwKO9y{i7? znVmQO7+wX6?TJxj;lZ^M%RdwEFU{r=edZT$WOf_X=e*0T3Nz(b{X`^VmIQ&e&j z$Tupx-|=@l>^J=HIrcv9iPxdN(Wej5y}LB;I+WLm<^;guesPDW`_K0Bv{A96XdK9~1rGox;&O1=$#~6Fhc@ z!=BOKNXPb=`MIv$-`zLJef{t58te(cpFir+Khjo8nC7`9j_uX*s#MI;{rk~(z)OVE z+-ParJIE)a{j+)e4nFQe+2!YR*RB^WPEPj>{eEoM{%_@fYS-?)Q^2i{J-NR_k{1V# zT|ISWKUCQN2#B{=^7cr7^#K4b;n5wEw*}ZC<#?a1)D3fVhvfa99n!JipL)anQ#+(% z9^`VLxG9bc|A7sW_ZJ)D*zZr+5P!)3)P^{2&m5IUcCt4<>4zZlbBq0t?Va^q!jf_) zARkQg_s$w*?<{}LQ_=Ek`LT@rBFlT6AZJE?mJjcoj8J!(8uPe*bx9?+TFatH1fN1TU!5 zE3Tvb^*qfwwC&ooefzF0&%2;u>y}NrHf-Pg{BxV0*U{k@=Qi!op<(l;T|2gE)3tS* z^O`&Dn>O!SrD5Y1M-S1sV~6u)edGU+wetXvs_NeTnZ`^YKuEyQgph!A$b=3enM@Kg zGf5_-&>@B1d$AHah#*BeNLN%uR8$aDx`+)F8y`vl0YOv{3L*)P$Zl$}?)qbof=JJp{_J7*-MXC}l4ws_O% zq*6wt6o#;D2(y7Ys9+&KQ`?BL*nXc^AtdzKfbiNONy4t%{ zd*g*u{n;5=aT)G(5AT-f&q|HgcWc)^N!Jc#vYDQck>;lysx!5weNYyh_k?s;h9T!D zx0H;o*>PEkiFE!9Pw#}lA^*5DPYRc&z7LmVT(mKxp499tT)2Z|&Y4(d7k7HEv`jzU za&mHZn%|R}nIN|uBm28Z>GN({#bi&^?;yU+;c?0IVK?cC`eR5)bx|0v`4cm;UGeHP zZS=i4XNiUzPsmI{`DUjj^~$DaokCC9?aK7{Q&l;22ps5i8;S8EM zbxJ;&{@AjUJ*mDxsrB$Ada_+>73N^_-qGJ6F=hC0QS+Djf?=_&Nbmf_FPa}ZBd2Qtt`zdr6l_Dgh9{m9Pn zCnjc>+1c5l%-(KSYIbJ2D>WmDFxM88km8@Sm+n<(@8rTMu3yY-gNDs=2#NRn(i7 zc#o@Vwm&N~Eh{s-yFWRT>QCSls14kxaPz}Wm!WpXCv^AFr#r=EWvEi7x?yaOR8?Y_ zsgSvHb9opJPwz=pI@{kpAw4nK-{by^rl)odG@HbgD*y#Q5Bax!Gxx@{kQxN2!VqoHT0Gqk-$`H73FDDOU|&@N=V-0rM&ms?u7Kz@>_E9~K-8_o2jBoNzL zimPX~o4Q@jSo;7FZo`Gs==o)&y9qg$JJUm7g~GeGHS~(8ztoR+P1XBwy@*=TE}U?c z=?9FBNNMBdOb9$xP6o0okPsKt9Art)NZBmifi4=C?xNmb@Zu}dQ!>^zDl)Xp$^Hzf z@9hH@q{pF3G7gCZ{lQNdHe~dmff4i>e&Yj|qY}&ZC(`K%meSU|w6$=%{n<&>iUkfp z*`)a6Rqknk5ZLHWNKVd5cBNAV=<3NJ*11>1jessR4=Rt*bol?z4>ZK*A?hDwrX`K!6;#J^&LK>G6ynGAMh{=z+s>M`v?o4V=uAoSe|rl`M6dMjG+d z(3EzydW8z~iUxd~?aNdtVK9l#WEkkhqO;?> zWoE}GsX;{95l36Y{?a0*P@9*PuJ?_4tD8tAlaXZX1Co7QqY`?$6B6PLK59*}s~3-J zWiX(+puv+y4~TBvN;)JJwN`{t){Tz>wd=k|0W1t7^JJ=hrC{LdU0o?DuF|VhdC|ZR z#YAm{e$mo)#Oc(r>6)4q;qK5OfH1(cB*s(VRYZvhx7SK=Z+)22GfdJ7iGv zk%LALnK-m_G+Crnu~Qj)1(qsAeVM!h^{ z2<(8TrccjGA0|~cH;q8zTr_8sW}B}`(+!o~cBSOg$U=E#=SDnp;em;VrY33#qwZ6O zZCLV{F=L&YE;0YeOPQfSnL&68ohi=W^B+gJlc_#X-^~q`UN)++)dyevv}n|2Am15H z^?>fi*)Gr~Q}G8*T3Tj2l+2cbQ%6v*tS9K}z*e!My-%^?3JGphYgPjGXt)cDv*GhzJ@HGj^a4}>ip)p93PI{u@%v(!Oe z3(&7j39)#xu3I#m*Ar?Et6R~5y;KSOls#i=|xhF8?}q#ltPLLRe-P9T=8lrmH4oCXh{a&;Hm@ zlQeykp+eChy0nCNeOO<_;ZX>!AZ2%TdDN;QaTnMPg+r5rtmM)G2jh-0i*aZgSUZZr z+7ZtiQBXJ;k2$pAdfUfYtgl z-eO)?wiRHEX~2>|%OA9EtA=iRK6uevPpGAQSxu2{#ki8KXYHSzq?&l)J_9R$`YB77 z#GSN2XRK7EOGbRNsydWuh63|;K4YL5jl2aWzEZaOYPEh@wB@C}m|A+~jXcTIcj9$e zDd#vZmMwq{=$e_XD;oN{?Xt#F&%L7nk~+4%yOb9nTBS@C4thxNk)cSULh(| z4uBUh(r8u23}e*5U6&ZuSC+{VG7xC60|jPi!gvyh9dQW-dY}u{OUt;vs)O)vJ+Nwz z1FLK}ul~9ZYCTMTtm#>*E#sCKzO>WyOv^6e8fH1P45L3n>a+ie6mEhVKI)fbEHAI; zV0xtH8n_~kprI+z9Z!Q2!)OH?1Ft%v*Hn`Yg&SpGpFT-FGTe>v;g@-tMs71J)tBn; zp-KVs8D8h-^QvhAav4Xf+Vq;8{(6eOnI|jQXc#Y)SwzvZ=alY-r!u<1OQU*1E#q<$ zlNYCPRaDN(i}i_AC9rsei>iA=n}~BXp{z zS^YG;5~?TEco|pb#<*-h6R3j5TBCA8r_gI~pgi2ku9P%Gcdd$oLsLco%?v(g4b4lVH&n)otjG&b^wYJ{@mcDbq06SMXH zU*pT;JrS7lIMoU%7lmze<7r02VQXG@H&1Cn^N3WfTorptkfppM)LPY4%@l5_ZmMCb zX{u$aZK`9AG_|0wmb(APXj!$J_l(;u{9ROrAB%j48Y~Nc6_w$~LSI8gU&m+ov1%a{ zMF)0M+uK{Qi)^=-#(exIhM14fq_6Z;KkE3?hM2b(1um+#ucGe*#Qwa!fdA+}a{Vf$ zF>e}MwKV2aRi|&6Q$H$ytLRGr5%YHb20FxieCt}JF>l{xh({kU_ zv}p95e}*567AQ#FwP^G;i-sSIM&H_J__1i!^gWm=<~@{n>1f!__ewP`@WXNUKtx|} zO6g(u#Z&H!pS&-gbzi*nzIfw(ahb1Tt3OezKk)zdy(<5GiYR5 z3K;;DZu*y3Cd<5bLv@StU%oLh$l65HVkPd)+EmlFitZBKFM3?`v}l3obc7qODR zl$HD);-6q`rfFwodx32KQ?@73xBBt%nW8zOBSoi*&JtZLx=wVv=x)&iqMwLt+y;*7h{;VxEZJzjR#DAWZ8o`%Y={#SE{>n<{ zsb5c(r#Vt>A1nH&Xk?VyuZ3tw(L~XCtaRRISSf!mh<{hKQho9%f1#|DzlT}rx~bx) zvr_*0v(kCyh^}d%;y*?EKP1~(>G-9h&x^h+dX3dd#ZP@cUpJAJ&O2G+IjppOtHk9r zx_>IuU{<;|;i)U(q$@p6jmw6LNi)+uH4>k0Mc>|5w6kcOXqsr2=m62-qT@uTiOv#T zEV@bbP0_ugABY|m{aEyr=r^L@i(VAHD*Bt~@1l1^`TKkM{_Ua_MZ-jEh}IQtAlg*a zDcVl7v#49tBkC8;673_JD>_7Ul;{M}M@6TJ&K6xDxKGB1s zABuh^`jsg6t6V-8MX!n86fF^@$&0>UIkVD=qE$s}iAIVx7Ulkz&)-h;5zz$EWYG-K z-lDmpLq*4kP8NMql>2Eu{{qpaqN_zWioPhiQ}iv-{i26OPl%op<^G({e@^tW=r5v0 zqIX2i7PWtnXozUID31sDd<{gKiMA5$DC!bT67`FA7wsoHP;`Xoc+p2i^F`;1E)rcX zx=wV9=*yz7i|!HqK=hdCr=q7t|08-q^s49$(c7Ybi`uNJ9D+r|L~DxH6Ky2gQnamT zXVG|3pJ=*hFVP&)A)=#2Cy72GI#cv%(Iuj*L^p`OAo{B4Zqa?BheSUTJt_K)=ntZo zM6Zk966Nt8^I@WK7pp_GvgiY%4~o_oZ7$kYw2LT@8~HrlM0<-45asbBZ=WRkl;~Vh z9!K)_)uNk4UlHZ;ByWFD^qA=9qCBqT?dL_WiQW?B@g;A!QHRA^Ni`Kdv zRuyd}+BHaR&k!9}LB*3q7tpws&$CkW)ygW~EBZNg@Vxy$qBm)L$?;#JZD~Bnv0L;B z8sBj|U-S@-*Es%M)IsAlj;o2L(pZAyKBCXnQ}HIzGf^tOA{z0KikpiLrU3>YKS6W{ zjj1@^D_Tfn8jkOYwx@vz#|ffOIaRzs^hhfepAs!k0~X#tTr{n{iu;MK=&0f?qGumg z@m0~tE-G#*I@G1&NuoR5D&8krl%Qf$qSB5@O6mQpdOq^KN*9VAOIGohqQQO@*APwb zrs8bTRT(PYCi(*nxcL5l7Ome?#ZJ-Ty;VF#bXQ*$zb9JUU&WSer4Q#S^@z?GpyFpm zj}KDuSE7}Ms<@VD=5Q6~imn-{;ul2=MyvQ2(TB#VxRvP02`YY6^o>a>{y?;3ii&Mh zl|J&AQlIFoCse#d^u$vt{zf!px{4nZ?LJe*14P%&R`E-s7v`$?H_=8? zxajUhDn2OsCk=4<`Pi2zja{ZRMRd+`6)zM0WTlF~6AfLX;<}&uiXp=1}ZYMf+n~I+lefvcf9~Qm)l8S>~RvNcMsb6&7P8BZ~{cM+t|07!UO%>M@ z?fsUDhlp-`N5!v-UZ#OQm(MNHX8Tp#L3I54DxM~~=YWcjivE2_#T5=KjX$cio9NRY zs(7X7$&Xb0z32mGFEi@y7via!+9 z&Z@YgXyOkl&Jca3K*g&?zqp{{bE4HRsknh?|0^mUA-eUdieDGK_Ops_i$?#d;?AOz zZ>V^t=>9?#eK)p;9=J|dbWI#P6|=o-=2MURV~ z6D=04NDB^p|Mf*XiKdGV6U`T0DY{eisOVYITcYJ-)OqWPwioq_4i(Zix8qD|YY{riiK z6Wu0yMzm4~wO_bsyyz6se9@hv7es#+t=>@`Ur)5P=upvhq9;YIoz(tqMTd#56Fntr zdsyvPT{J;-is&n%yG4HztxXGQ%z2vVY|(c`e-*9wh}thpbe`yb(VLMHh)4 z6g@2(L<@~vPLGIA5S=5sT6Bl#2cm_dcSI}2tMf#PW{LI}9WT07^i|RGqSX@A@gC7> zqPs;u6g?yQi>Q{Uj%y=2M0Bm_Nl|N8wO=b%>WABj#)`&^rigYE?Je40bcpB((TSo{ zMW>6-7IkRUr&9R_i-w7Yi_&yg-yS8}M6`t{P5<=mUQwF9>2a25KT(=y={`-LbR8+0 zFFH$ff#|cM7e#56T`9U&bc^VVqB}+35PetlebJ+$ABmn4{Yvz#Xn`od zKFrVay6B&xe~a39otCx-iB=P>AsQjduOIV%%|)G}9YytZY}%eEu~#%*w7Y13(LB)+ zqWXF^9Y00l$3^w^Z1U$xyhL=l=z7sjqQ^z~^=HoSX;FRMn&JY9e-ynTs;^tq_Inar zEb90QqLoD-6s;%PQdD2BrsMT>YSIMpQ$)Lo_7v?aIzV)Y=xovXqDw^e^=UfqdWkoQ zZWrAlx?5CVr>6Z6NPI-}6Va2R<+z^IQST|?^5P#>tLS+t4|-WvGdH031c|S;nDFSR ziMe^C6UQqZiWL0^?1@?n{vXd;i@XUFv=;P#v|F&*LcOEofBm=<{eXe||7Pev_Y59G z=hD-;d3oapO;)E<&d4zXjA8D0etU^rQ0?(gXXLQagK$R5vDRY1m{Fq!(I=4@t~z*p z?kL*Hm7dZfcjCnH!}2Cgq|^T2{?wu!sd@$8b=3O41F1;$pL+C{_oGLl|J=VHZ{wea z^vmt?|F&N=?Q{Qi`Ta%s;b+P}&FD9Xeq-sEe~w%>X}qpXOQHI6=l%G4x%7)XP*R&k z=UPPl1b&d>Hr;r>AE~k7*VXxa%ool#iqbfSl3M6klU8Cdkeqhke&xrTv;y3`VcX-B zHeNT_YS#Gm6}~R}xb7muF_hGLvz6$h<^KGIuj-jMh zezHm5kJJ2vZR;srCV!67^U<<(;C!@X6gY;GT1`6N>s>jeesI3mC^Vk0Hl2^36X&lo z{UU!KP@0cn9{A_u_e@%^`YO$Tc^m(p5XFA=FPJp$xABAhz9ECt_!&$4B_SZ?>+;W+ z^lQvteZ&2R(Kh7oM@rLU8cU-8?4k2@L_msbv7)Z<<|5iJf)3=d2%)H-FNBn@X~09P zN<8l*4?j3x6*7$bwWj3CW2j6VAlvY!o;zUus8X{f_7h@c5^ZR)bp9=2vg{PbAOX zb-HA~)4DY5MqTr#SLx$;m&V;#G%K#y-0FzuXws3AS`(Sh!- zCYzSI3*F|>sJA?u@*;CC=0y!%Yr13xXSF20Vo1Ma zNWW-EZ!@H~7}A>z=?#YTdP91xA-&p=UTH`#H>8&t(n}2KXAS9vhV%kMdcGk&*N~oV zNY6B+ryJ7K4CyBg>BkM}M-AyIhV&#udV(Q6&X68sNRKk4M;Ow>4Cx_;^dLiefFYf0 zNM{?;{S4_ohIB7Ox`!d1Wk_cj(%k~-*y3ZR*g|(qBp3`)oNXY^k_r#E>gr|E3L>I% zqK2*~FFqx~m*AxjOh~$%yDg7N)9H?M6WP{!O!v$JE#!gN+oy*A^5)sMx78eEihFX( zhWfv}w>f0lUmI4eC>gx)&)4=YoE7Y#TKIuxqZ(g9v(x*1DpI=^ zt+Uoi>#Dgmzvj_;X&Kre>hVTsL$q|X|N3Go@?V|RZc2&Eh-K6)^m`s&T73qEE)l3cOo#yRKtxTOw9ZcO!K2twaAJY(1 zu4$5KjA@$bannN6Y}0Df64N%*7Srpd*G&6N@0dO^9W;Gz`qXsJ^rh)%(-qTg(=BR5 z{xX%*cIBJ24O;oTwHAJs)b;J_$M(JbX#M!5vw}4fYNx8_Nrhoi2feDMtMXh$<(Wcn zBy$&snM0!XdAOvnYgF3u3|7vBkxZC@d=PkXat1^ExQ08T?uRdeA)N1_Z50#e4MHCcc)(RZSrpRY&M*0<9|69=XzP0TyqPQQkY|+Tw50D zbX*SsAxuq`NSEF|UC1-GPz$AndL}@gCGlxPdY&OY$B>?7NdLdo-qD8hj5MT&8`47! z>A{Bd|4R)_Gn^;YkWMzFy@qs>A?-4xyBN})4e3sXbO%GaT_Ei*T9m;w49FWWe7*VZ zX;V!uOZQKJ^CRJ{mp-fC@Lsu@Q-u!HpkvPG}mABD_yyB z0gVju>390%PMi0BUu)wr>#@-HihEZ)%XOx|@BD+`?H_9{zweRS?M4m%vD=T|D1Dg>&_z!ta;B*+BWCKPrvQ`<)MVV7r%979{PIh{){J_ zgCd^R+G}rhU)1ukNAvPVov9NNG+@?%;cHbHgmD>cC@q8Vt-h_^ZJupOSM*v!C1SZK zCD4ybVCCG6zKz~Zo=tiQREdl&?9r+$;i{Hf619lZKG>M15=+Atci{w!v4-+9xtz;6 z;%BnftUs0TxxOp8bG`FC^HixDa+FOu>NIzzZD1}l#Ug84Ee0>P8^&x*gJ#>P~;fPt|#Sm@0?s;t~bwI1N%rCUpi(ebjZ*y^w~IZZ%8sHaS0PM3-#uy!U&mk6SHFM04$jBdLAmgCaLv^Q zqMG@rK6zUF3sLm0!J8>_QVLJ%`B&HYOusL_hB{Y5L8Zvb;ct1Xev|vs&>^uuUx}|A zyrNg=@rc2rHr^Ro{>?7Y6Uy!Gc&_3k^7z^B-bvcf^hoZp!6wT)eXs3ZHHG%lkeDHv_~%$F4@?^`Fed~ zLQq0{S37(=ysvs*)t|dH(qA;)y*YQwfGxwaZHI5=M>6Gm25iX-btuayF2T=*!$PcD^5I)j(Id`O96GrO!8NoH-z=(fgrw_3+aJDPz;*bP7YgCRk zYQPXxhjXZwkLwtn?+*|^88_?fqcX7FJ`pxhc zRrHLxVJffg_&VSDV*1_4`@|MI!u&TPD!7X;JG{jQD*10%gOfZSzbA!zv+L0jGy=Jv zPrn89d%)C*{)W(R1pV@PkWQnt_S>m_H%%2TopKj?dU)x{SR!Hz%MIw@>A>Z|d+U3t zqY5Gh#@{b3u?Z3YWVV! zrt_3EnUz0R!s`FZUPb_+cZ>4vo=VI>4q*XpHjksb@ zD3{)HrbsX4=cp7_sr4*dY7?ZiqL06>(J1qY8T7k!zW+!`{d`q2oP&;f4rY6NiK?GL z4t@^gV6tzT_hRlePrff-&m-ChRZn@|dp$a_(CQAf+QllZTDo!rCI<4?&yYXP8%@7& zxTc>gxjucQKP1Z0;9{OTakzJcXM}zozFRe`9!hoP{#mtg49vB;Q(}%c$CGOq17}mu zljF&e)R6R#2GLgX zb^S#u59+#Vpa1FD*g~}rAB#Mw>#E+0kByhQ&eyd@ZOQc)#Sh^2x930FUp@}K`m-cgFze!na$9FzLyx6KQG-S&5< z%}50-Os&?$nU+0O^uTN8hWQWqiypEqPhR0$ppq09~HI@dAbGyN%FUS99vi>Z8wGSg$;UU?ZZn)|ie6kj*mwv@}R za7nib`Zg(H(^!4mO4>HXJJs(m8auQ;wa4aqYw|iKo+~LjPrnC;Bp)t0nQ#9+f70QS zBL#;`v;*Jf^`dsUzpBB`keIlVkcX*-cD@`JR}!qJ;z}H%)`zd2%JU8I4)6@r??lyN z?mxL6rzMx2&BhgmMfUM{scd+S>7>c+&XiP`jT2i!vBC1!k zttmy%QIx7jjl3Cp|B+N!u0n(4b0t4*q~FEVYVN{l*)UEi9WD2iQGM+UT0Eh-RA7!2 z7%fk~IIO=pjryP_XL1)dUsmI#=8x@4`?yy6RrjD(!@f%!bgNg|%U}4)Ywag24M}hD zT<`ANo7F#1?ZaV{p1Sk*yN@33I{$@XzkbyB@&tYTh5M%8Voq!=e`i+p!LOYBqxG~O zt5=@$$o_hHNd>hRr(M0W=fZcq{=z>4R~~<%)~E-D$2=cZssB3oA!yOKC0b5&ukftYpYiA`%=$`+ zaI|XQRC~+ZqP^m?qR-&7CQ6^7+QxDN<_7wVvLk`36SPKLlTVabwO-%*Z)j9+)!c>8 zuG%-%`=fPH&x)^sR%A`-2tI5y^{k`4qkUuadk8!!nicmk=YADm9IW?heD0*;V7=w% zoa65FvkC#6bKD)@bst|}PhW38{k&&NtkFR?O+mhd7td-9FthIA>!G&|J@oNlcWxUB zy8n|J%1b|L8`7qy`O>`IJl*s&K7T2tFt(bXoHTN%MAEo@x_8^XH`V9&`aNm-UiWVQ zxQAQ66#Y6Wo)llI?(e^n;!E+;7bfV@#!KW=O z==h|~g=h6O!8wbrIQMBnWjryH(mR_BFSsvl2PKR;so_NGgJDLM3@_e#45 z-kR~+=ui3`zdP^LjM&qwyI<+>VZy9SV<$bZcgs9azn5+_IU4$D`MT%3zGC^X#&747 z2R`}c-3oVaUtHDa(+B%L^W@h09~YEQs++K8rMY-&`=g7xO?mdEPKyhsPXFe;@{X6* z&McffIPbkC=Yq~}7_n|PMazynpw0GVpinx`gxE5aVzaFY7=*u<^bF`>RPmiTJ%1&Rr*3YPfscdrjh0hOXzn~W^z(u z4{r}oPkju{Wtx%L-P_&MLoeU-NUnWqbsJ@X*KWMEBcrH3Q4P{x!8t&+RAz;|PD*`L zU$4*W^?7`TnmcxML_O+JqqskfKbS~cPSPyt$bpEQ^LaeGDeXlMQ4gwm(L?&HJ(}}S zi9>e|l>|Glo@(!F@1=Q?{Jrnc>j>7 z^SPz#L%K_QKW5mQYERx;6R%txNb?tIxf6W_xfk+s2XJ|)tCmZPEvy^UENTq5+cX;m z4=8b>ztx4@C|YS-&1(Qd^)&!}EtSsMCoh#ole_YWx9d5%+%D(m(s>FBat!>)2$seR zJc2!$?=RY!(aXCz4|%|BfcqkM;Y@QCS@Xi3CKXq*q|!a9Bls!0i}RkMk>1EqV$ws? zc%uD0QAso(p*6ybd7%D_k`Nl(5$nz`h{u=XRLbF08m#M2r_`&IbT{ekeY|>CIyY;_``1MP#AH{vYxp5phy6^{wQ`5JLN-9qnwT^si8)9=lk_}q_?Ef&=n z)Bk06aqc)O-Mp$%uP1HHqq3!Y-WBnh_cbc#t)!7TuX!)#af$M)!WD*wP%YP--DuqW zQk+UT9#(4A_3EiD$$>J?*hI5$T9@{zS97`+m($k;Hux^)^893LwB`3*VU}XI1k#x^e*x&O1hZ4NN**d z@|`QO&e)>&_X~Uryw7-^QSA`T_^r;T>Dou4zmvu5IlejGxt_U6$4j(>+{#j^ z42X<8UUD*;+rt^2QOUaJGJx*gI)izPvL+t%;E#d^No5P43Gt zwHuL1p8AqsZdHtZbZlYe$eKA1QlDCS543)x_k=wox%ckqtwz0gK?Le@Q~lisvl83* z+IZV~+EQIm&xG^gD=g3{3Z`dyJ-Vm`0K z;pxY^_W0&9_W^e{WPbI0g|0R4HhOr-^f}W!+@^E;Uo?J|ebewpqdzds>Ui&R;yiBu z^S6)sa`3XFML$@6JyI?xcfZuhyS&Cg@94PM*7W_*X(A z?s}K+b?@t*HpDBUhW46wSMpIRu@MFeENgan!g6*b?eM*-KWp{G zUh!?CvN;lstH^6X&--uG58}CV>%vwOa-wWqTemu0sN7pr#`#pau>Bgfa%@!Y} zF~Ct80}RXQH8h2KVxGHp%i+IE^uMR{zcj0^yEx&OQ%|Qf)nBJkwesiOg`S1JMS8wz z_TZ*-MaNOU^|Y7H7{PxFBAVtrS!PV9=FL-S-kh$kR?o6}V#-0{gsxfdAia-8X)vqv zAhr8nl^l=mU+&K7DLz^k@J!XOW{r9!H=fq^M&u3htr?bOqj6fXmBv?j6s6e?-O8`` z=jqkCkv!Uo9FhdgstMOdofA!F9Vew;P<=m_YBN(Njlgl*7&u zy8hKu$<*rc>o$DXeW}&!>*?oHGpN|Y^j3T{-#ztP(MiQe!(9LNMCjEyDsg#-j4>S& z@OeZOL(g3^@pG5?rPHz|o@&3U^Kn%BOKUy12Zu@`Vjl555_sp2qN0;tkL&(RJ#Oo% zQKlZ3j*V444y9+cJkS=Et;dbL<@I{(FBlm$?5W*995@j<>70p zI-S>-R4(^^^M~)9>hS(MXNo6$Vyu62=M~VnQT1ql=`D>d@eSXb-ZwqFxuxmGt&Fjy zsc2|vc2Ljq?F?>f(0`~iSQB6Lz3AQU+0Olk3umA;JMW907X!8S1@8+f$BB6EIYtca zOLSYG|B9Z`W_riNmZVlWTlC(mKD~l#j%uCgOx&2%DCb(<2C5||Blz!;h!x%uIaD_% zWenvNbLP*N!+#g(e?Qj$x=KR2ER6f*)VY#oGrpzO!nLM5I+w>wYDaImnVPZX_YcFK z@lw4^+EP5D73Y;l08V|}KcDljQU0nNr*Xhs>f^RXOryUiBWBazBYMs!`OsfaPqMB) zSrSt3Ml|)(_2P!}-x>PfL;Bwlfjz$|iKxe0zbUCN+DNpSuDyqLm%1K8HM%H*Yj{Yz zgC!+;YERt3lDm59Ao-_HWyzYF7D@Y6v93B$QY0&AC8BplHJWEx>v_twFA0>Z;}Pl9 zUZi_z91-CP7M8~9)DC7tu9(y*8~}Vv>M850$k@^-Z;;#+_C5~H@D%6_rxb0*FxAQ3lsm`a1uch?*Jb!%KndRcNecb1iyES2c z+PNpQW_GY0-nqEa>XOI9uZ4fp`0k*d{cbnC(Q-WMm=XL{Dv9evazL~*)(67>ms>R?H* zXh>9RZ)*>;9UIkxM%w$G%ZB~OdiS(#m3`NHKizniX5eAAWr&*kntGdgn(6iQ@7r1X zdX9=T6#hjAN-~+3(yk><7wOEuU@KYgcOeYI$jHAbYpp&u!#a&F-E4yY-RV<-Fzh zHo7$T!!>Q1jU6>;@DG<}*hj8kH@6nAr}mf}ePUPB;_*uy^DkUZ{;B2Bu)X>JY1#4G zfRCD0eEjYHnT>``S$?na^?PexJ>M$D^g}l@4M)1S{$%kAkaNv#m0{h1hJiAE`$Jt}C2Qsh&dn zo2|Ar^agH=i{8C!_SeYKE&I%x6gg}?*mT%`u0e0LvD)|xPRv&OtZKCT*VLq2nuWP& zcgwU0`V(C>lhU?l=});Q>7B}U>l2i;`YMIlDL7!Jz+SZ~;cL&N_vo6*q=W27$g$c_ zQbuj|FD-PaJ(O~5x6h%|JM0_C53)zn{^jlTCJ?QH-Ap+NwhxNXw2Jog<>{kS>^tZ` zHdMCz`M)>VyU?Ch?6v6QJ3{TF=|02kyJ(-P_8at0>}vL~y7V?``xo@i{cwAyDEe;> z_6I0k!+wMcqo(~WO4qXQqEf7FKSX=hu{WSR)U}6`6Jg&*SFC5RLRX2j+bd~Wl)WbX zFNym0Cn(*(zL(B6&^{?r(+1gH^{H95_o=OEAK9-^o=@1T(SNo0*nW}n_KAHt-S4ON zZ)wlZ94#r`%;ccAD{9S6jwQ5L3zOsZQ2u{Pj;55GXp`d}J%+_5#~3Q{B__ur%IGqa zV;Pm*b0)_tR9wqVj`I|)FgXrUv8^;YcF|c@nH(0nz-p5thqkRTIT}%x)|wodbfF@X zV=Bq-CdWfoO)I9u>6UJr92rzvB__w8bX-rfV+vhpzuD1<^750#@jhkZs>QLK-X4F= z;@C~+{Mq6NBkrzS9G_6R{9gY*Nxep0Fw!T(JG_kYG>X=BGsA_X;qdTf* zb9_&km}+yRP$@lXbF8G3J!W&9AoDBpI7PJPbiSVws&usIx*!Sgo9 zRw|_nHV1zW>pDjcl|Px&^-*k=9o;^ z8*(k^d)hX(ib)H)OgA%*6QOkMcuu@ek9`6s;%J|VoTy0{PU6HOD#pp2*iC22r$-tT zMI}0&6U*s5GdS@h6~s(VycJ3RU4|29=(*13#39;w4kv!0yv*fGuCAwA+C*Gk4QJxdc=*$&3@fq#Ili#2W zD(i}zc!C!6PG2Ct6T8_&BZnYC4g1w8^rO;tJ2wpJ;lf!B0@4F7<)s&eD}DTG_8;wLN6(OpH~I zi`HxnA6QGC)l`>4r)Fy;VI2x%G+Sc{AEdCAW@{p0Z3ey|0*vKPPPVB8GtI^Qk!7wYVSbkZg%TNRGrHBv)b(k|!|;86YtT87MIb z86+_X87wgf86q(V87eUd8746Z87?sh86mME#ABIG&%eqMYQbz?MabjSw%bP9nH(l$ ztZh2sqZ2Yt4i!SiODKd)kWdJjD4`HCNkSoHvV=m&6bXfpsS*kyk4h+nJSHIsd0b); z@`S`7DoI5b}w{AmmetLC9wkgOJZ9 z1|cUU1|g>;1|eTa3_`w?7=)ab7=(N!F$nouVi59;#31Bbi9yJB5`&O45-URXSgz3X zuVSJ>tZlC%q=cp#iC6iEz1ewP@86iW<3Zc7Y8N+bp$e@F~M{*)Mm+>scB+?5!F{3S66`CDQTa!+DK z$oH1=G`p+vG);qA@yJnAK)A(L{u1Ts)hxndIoY6w|P`9O60@)3Dr* z_(6(kSnfbvn_?Q42O+LSF%8ShBd$p?4a+Mau0b&k%YzYDrI0j0$W}PHVy_&j#hR7K|V^D5teyIM|?^J_y6k2IaI4jB;#H zPV2(3u|YYFfMI2Wa#|0Dg$>GSBn&edJlBbWVPb=FS|0`hQq5{Jn=HIO6Z$q!aV#c9 zk%yKVYz<6y#)~OxY_g4`rbnl!362+vnj#j8njsd7nj;p9S|ApRS|S#Tq7e&4PQ*e{ z3}T_E6=G1-8U`q80|OMbg#n7%!2m_=VSu6zFhEg97@(*V3{dni3{cb=1}J(21}N$R z0~E!=07WhspePOoD00I9Me#5|Q34E5ln4V9b%g=7@(*(3{cbu1}N$a0~Gax0gC#=07cm_Kv511P?QS;6y?DHMFU`fqJc0# z(I6P0XfO;=Gz11H8VUmx4TAxShQk0wBVd4{kuX5fC>Wq*ivdMCm014eft97;% zp=dV^acpBucIJyInqad1MQf2dMH6wnP&5g#P&65_P&5UxP&5^>Q1mEbq3AKhLeb-h zg`y`A3q?;N21QT707cVafTDaDplCV_P&5MuD4Gca6wQJGie|$AMRQ<)qPZ|Y(L5NS zXg&;3^fU}mv;YPudIkn4S_lIaErJ1xo`nI57Q+BVOJIPar7%FzG8l@YaVAS7b!MRt z@xXb!P?S$Sne91~o%v#lR+(&Wnvm-ht;X>}(Hg`;(OSep(K^IJ(R#!}(esFfq78_J zqK$}!qD_c}qRogw(H0n>Xe$g*v<(I*dI1I~dJzUF+71I0y#xaky$k~sy#fOi?SKJ_ zUWEaQcESKfufYICyI_E#*I|I7H(-FGH(`LH-7rAWTQES;+b}@UJ1{`e9vF(E6(-A2 z0wk2brOUQbC<@Z&VkSHD#T30~vdyR0X>^L-$MHhZ2Z)8D1Biv9gNTKqLx_c)ga~PoLBn(h= z3I-_p0tP7h5(X$b4FeQ?1p^d)4FeQ?0|OL&3j-8=2LlwHfdPvC0|OMDg#n7bhoLCi zXR_=hKtj)Q^Rr(lnno{^*?utDnJ=d3g30zdy}qSWbP>l3ML!}IiY_4*iY_A-imo6Q zihe>Y6kSCu6kS6s6#a}?D7uaq6#W7N6#WVV6#WJR6y1OUif+OHMTIax(JdIDs0aoq z`W*%+Duw}yZo>dYB``qIA22}CpD;kt9T=eKE(}og7YtDJHw;j84+bdG%z;_HnxmOu zfFd&tMNxstQbd4+HsZy?^Fq;1etpVfwliN$k=<;o_K;BI!0|#+5MrUIJYu1!0%D;k z7_m@P5wTEI39(RA8L?0lf>R~Vou2?i+gzyL*F7@)`p z0~960P!u&WTk;8z&`b2*6I)ZE=v`WnwxyWu%okJC&1~D$L?}wf@j_7sVxcG#u~3wS zSSad_SSad&SSad=SSad+SSad^SSad)7!>t|0gC#;07d;_fTC;|peP3hD9VKait=E9 zq5&{K(LflWXb=ogG#Cab8Uh0p4TS-UhQRnhpaL&42-lX2JkPvtWRt*)TxS92lTz zE(}mK4+bcj4+9iE4FeP{fB}l0fdPsZ!T?2!V1S}$VSu8=FhJ1~7@%k=3{bQT1}J(C z1}It%0~D=*p(vVYwgfjPinj2o<0PTT!wu6)vz_^3iq@KK&07jZ>u|hKv>vfg^gLpr zXai!QXd_~wXcJgU0dI<(7dKm^NdIbh3 z+5rO;y$S;q?Suh}UV{OOcEJEeufqUEZ@>UWZ^8gYyJ3K$w_t#xw_$*ycVK{`JupDg zUKpV0T^OKf9}Gp&YO^Js012%@@652R5sI488+mN|&35LCDLP=bO>hcD2XVYmbO^Cf zbQrNvbOfF9eFXy)eGLN?eFFm&eG3B=eFp;+oq++0{sRLPorM94 zzJ~#det-dr&cOgh1uzsv@0%^F2$0Z@{1W{KLQx)#s%_`ZcIJyIx@5NPZ6y?4#_>YY z6~sc(Pl$!0tB8f7YlwxSpAid1*AWXvzaSQhenl)4{e~D6-GBj#Zo&XXg)l(TEf}Dv z2nHzn9R?^Wh5?Fh!vIAkFhJ2CFhJ3tFhJ2A7@+7b3{dnJ3{dnp3{Z3r1}M@jGHnM% zCK#Z|3WrqJ`7OQ00t;} z2nHx>2m=%~f&q#e!vIB1U?_?l7EArML{TJ9?t?69rXOskpsB^qd@)5WEw+UALQyo1 z7mA#Sg`yb5LQyNkLQ!kPLQxyULQz}9LQy-!LQ#9fLQx0Apr|7ZP}B(qD0&zMDC!IY z6g>h16m@|Cieh1aA{Pu$6bAzoxnY2!co?840R|{agaL}W!T?1{FhG$91}O5v07X6+ zpePvzC`y3=ic(>KB0mg8QFDuBH~|vs;kKxSP}JN)L7K(Rd@)6t7Tbc3LQxiu7mB(g z7K(Zx7K(Zz7K(Zy7K(Z!7K-{H7K-{J7K-{I7K-{K21VI0Kv511P?QS;6y?DHMFU`f zqJc0#(I6P0XfO;=Gz11H8VUmx4TAxShQk0wBVd4{kuX5fC>WqVS!LP|icBy-kr@Uk zvcLdERv4hj1_Kn8g8_={FhG$5hN9@Q#d4eg3BACR`zu1xyYyPVEy!wTzL=tlR@>DC zp{Np$7m6w)7K%a;3q@5B3q_%bg`zOTLQz%3LQyruLeT?=g`#l8pr|?wP*ej3D5?nq z6xD(OifY3EMGwLNMRj0+qPj3ZQ3MQ7R1XFyii81*qF{ic`Y=FI0~ny_AsC>jAq-H| z2nHx>3fNM9~iVpUJjhtD5Ow=l_@5!fI!}n4%b( z>?a9Dt#G_h)Eco+)CRFo)E2Q&)DE#w)E===)B&+j)Df{z)CsXr^e|#j)ENdSdISb2 z>H-54#liqZE*PLF4hAT4!vIC`FhEfP3{aE^0~B?I0g94ffFchJP~?RHihM9YQ8Elr zlmY`3rNRJ3ei)!A4F)Lc1_KnO!%!4OTP>LcNaz)Q-?dXH%H|-$YG=Nfq8?V;B(G4^ z6UPfhy$}mUy%7sVeGm&peGv;q{SXU9{SgaA*@%Ur9K=FVE@DuW2LluhfB}jI!T?2s zV1S~*FhJ1|7@%k<3{W%-1}GX10~C#b0g6V#07aujp~ z6it8uiYCGUMU!BFqRB8o(G(bpqAaUr4FM9mkq6Y>g`!uOqN!Fp^TiZBVYTf`7K)z4 z@j}s4h=rnQh=rnj#6r<@#6r;w#6r>(idMn^ zMXO+dqSY`!(Ha<_Xe|s-v<`-%=rOCMfB*^ogF@TmLQywff?RL4Gha;6CacZl7m7CH zc%f(uVxed&VxedoVxi~-#6r=Fh=roh5?Fh!vIAk zFhJ2CFhJ3tFhJ2A7@+7b3{dnJ3{dnp3{Z3r1}LKcmc5n=*lGerCK#Z|30lZv&O(?p+GyPzjo%v#l zLTt7#vxK55I9@0UMJyDBAr^|NA{L6OAr^`rKr9r6BNmFPBNmEkAQp;hA_hgZV1T09 zFhJ3RFhEfq7@(*w3{VsS0~FPR0g57FfTAcEpr}3!P}BehD0&D6C~61;6g7eYiWoklvdhy(qm&hv)ibU*DtmS?4+L{j6ub z>wW(?-fQle>pS^nCp(|)B-1EQKv4w(iYgLNREdD1_X#NafPkV82`H*eKv5L}imDP& zRE>b5>I4+kAUKK&*zV#2B=DO2O1@oC74}dR0`LSrvW8 ztcvO|tD?Hhs_1iORaB2z71d`}MGcr$QA1`FH6ozs3j&H76HwHIfTE@Z6g4BD=t}~M zniEjef`Foy1QfL*pr|zgMQsQuYD+*-I|7Q@6HwHFfTE5B6m=q?s51dYT?i=ZN^lg_ zwB3CLNFcBIx$93<(GK(1tGd}<H)S4F*;RZ(wdRn&)B74>CSMg5pn zQGaGtG=NzZ4P;hDgP2h?n1G@o1QZP=plBEYMZ*aw`i6j_5d;*CB%o*%0Y#$;C>ldR z(O3eC#t~37o`9kW1QbmqplA{SMUx3AnnFO)R04{o5l}Rp;3)dacJCA*fkNizuD@1A z&HXaWu)W5YQ8dT4uhmgSb6Ky7<}s_H`OK ztEY-~vR)PKVpc`FnN`sqW>vJ8SrzSLRz>@nRnY-vRdkS96&+$m(P09Lju23Elz^gR z1QZ=7py&hvMJEX;`i+31Qv?*9CZOnd0*cNMP;{1nqH_ckohP8^0s%!A2`IWmK+$Ca zimnh)bd`XjKM0PZ?Y8?P0TS3`zR5>RA$ z^kqAWTm%$F5K!bMpeO|aMK%FN9s-KI1QbOQP!vT#Q8WQXF$5I(2q=mrpeT;uD7tRD zrwEY1J4VqBRdmceyN>sGjW44prN`dXNEM}Gy(&u0tcubwtD+#YDhe^HqO{DaC>^sZ zO3$o{GBB&6jLay?L_kp@0Yym!6lEr$C<_5aSqUi0MnF+^0*YQCpeP3cML7v5dX<2p z*9a(joq(cT1Qg{apePRkMacvdKWBJ+`}vDte3cs;CIFDten)6%}PxMa7s^QE_HfRDxL*m1I^$?=Y*PQp_lN zmw=+u1QfkTKv5Y2ipmmDRE~h6@&puBAfTus0Y#MvD0-iOq7Mit`jCL4$^;ZuA)u%# z0Y%jaD5_3CQ4Io$J|dv#V*-k55*$Tuc-%P!NMNsd5PMS<{b{}g`H9DCd>KWbdF=Ad zR8bw)tD?Hhs_1iORaB2z71d`}MGcr$QA1``)QDLXeZj1X8Z)D)2?0e-2`FktK+%^3 z6g4NHs09HIUMFW^s(LiQZG>BOh4Q5tFLzq?3P-YYjBcNzF0Y%>sP&9&oqLBm?jUu3EGyz3p z2q+p$K+!k?ipCRAG=YGki3Ai)BA{q80Yy^?D4I$@(KG^zrV~&!gMgx$1Qg98IEs3D z+$#l0AStWB>7|Ogn*-BqkJtDzispOlBP~_Y0@kadh0LmG5wj{<%&dx*Fsq_(nN`tJ zW>xeZvnpD~tcsR1qi6*IMc)%pw32|LRRk2RCZK2y0Yz&GC|XBA(Ru=kHV{y>k$|F2 z1Qcy1py&qzinb6?^dkX9TL~!oiGZS?2`Jh|K+!J*6m2IsispLUPXtI{kS%cLsiKnR zhmCf4yvCPNwA*8+Z=;I#uwE7IWmZM|m{rk!W>s{6Srr{*Rz-)HRncK)Rdj?|6&+

%0*cNPP;`NSqKgC+T_T|9 zG66+b2q?NrK+zur6#Yp+(KP~!t`i(ZJ3a1_0wgfad>?I>D(dT&;fBX+d>KV|Ja)Zy zs^~83Rna|WRdku7lSrsKRtD+=k6lEr$C<_5aSqUi0MnF+^0*YQCpeP3c zML7v5dX<2p*9a(joq(cT1Qg{apePRkMacvd^ajCE zl*;SgEkFW8%$JB#d!1MM70e^roAPg*iZ7$+ZLfW!lPW68dR0`6Srrv$Rz)S4RZ&T1 zRrC(CDk{aSir!^bMWvZl(R<7&Dnmd~Sptg65l~c~fT9Wn6jdaks1gB1?-Nk;0RcrH z5>Ql`fTAh{6jddls2Tx9)d?u7K|s+*1QdNtKv7KsiasHrs1^Z5pAsBJZ+YE;&Z4N5 zITjUBMdys7+Fq~mWfXnxwF`7rMfF&(it00~q6W;Ws3Ef|YQ(IHzF<~GjhR(Z6J}M^ zlvx!uV@A=J1QazVpr{1_MJ)*^YDGX%YXXYe5Kz>XfTDH;6tyRyr~?5-9SJDvL_kqz z0*bm2P}G%xqHY8fbtjpqLBm? zjUu3EGyz3p2q+p$K+!k?ipCRAG=YGki3Ai)BA{q80Yy^?D4I$@(KG^zrV~&!gMgx$ z1Qg98plCJ$MRN!!noDpL_3^r=36MZn^ChCbs%Vt?+VwoI*Z4Au7J2O-zE(wxS+9zg zFsq_(nN`tJW>xeZvnpD~tcsR1tD+Ums_1)WRkV^BMXLxXT1`OF8Ul*e5>T{`fTHyT z6m1}&Xd?kdn+Pb{OhC~O1Qcx{py)>einbC^^b-L^KNC>2jew$G2q@Z4K+z5Yihd=a zXeYr@w7~1WC_n;F&EGFtsEU3!UoYC_^%`GB(LS$j_fkdsS+9x?Fsq`2%&O=Rvno2w ztcs2>tD>XKs^}QADmu=ricT=2=p+F}zY$P$ih!ci1Qh*FK+zcjip~;HbdG?c^8^%K zAfV_X0Y#SxD7s8Q(G>!Ut`bo62LVNY5>RxFfTHUJ6x|@8=q3S0w+N1+Jzn=~0wl0G zrNG&%irShV<-hIq8ec}yeXm`yk1Be=dR6onvnqPXtco5ntD?uus^|%`DtgMSik>m6 zqUX%2=mj&1UJ_7bMe3_a6uAf}iXfoKO+Zl!0*Y(`iaZ1qc?l?rB%mmYfTCyuied;T z@)1xJOF&T^0Y&iy6eSQ)o$RGOMC;%qS{PKv4w(iYgLNREdD1_X#Na zfPkV82`H*eKv5L}imDP&RE>b5>I4+kAfV_Y0*XE+pr|GRMV}B*REvP3PYEchO+e9S z1QgXFIEso!x}OP}dy z39~9{%B+f-F{`34nN?A9W>wUJ8AUA#C~8GOQELK<+7M9GmVlym1QfL=pr``@MI8w! z>O??MX99}45Kz>WfTC^$6m=({=qmz>z9yik2LVMr2`K7CKv8c3iuw>7MfD=xr36S| zbvl7lUlrvyr20mBjW45UV5Hq(s45!7dQ~)-SrrXoRz*XZRnahJRWzJg6@A03ibgQ2 zqLIw1XcRMwMiWpphJd261Qd-UplCb+MH2`pnn*y=Bm#;i6HqjTfTF1c6ip+bXgUE! zGYBY}NkGvo0*Yo6P&9{tqPYYV%_E>_J^@7w2#%uuk?w&4BrqbAz!{*5-Z6g?Yhk3< z_%e#VjkFgIS4B%%uZq57Rz=I0Rnc;0RkVUx6@AaFidHhKqE*bQXf?AcTEmQ@wFDHc zBcNzK0Yw`KDB4Is(Ix_lHWN_v0|7-_2q^lIfTFDg6#Ya%(a!`FZ6l!Q7Xpg56Hv5+ zfTCXsDB4Lt(Jlgtb`wyvhu|n$9O>RGKmwg21vN6Hw$KpvX%=Q6vFHQ3Mo4 z6HpXGK#`AtqF4fo;s_{;C!i>SfFeHuMF9eeQW8*y~2#590U~QB%tV30*YQEpy+i1igFQ9l$(H}JOmUa6Ht_wfTDZ^6y+zNr~m;) z1qmoBL_pCS1QfkVKv7`=irylis0aZ?Zxc{dl;9{z7v-KIKmuvZpW9C#<-F2AWWK3Z zEXr$q8Ab0z**}g~MWtA;ir!^bMWvZl(R<9Qs0_0zD$A^j$}y{=^31BJ0<$Wr$c&;& z1QfkbK+y*T6n#iQQDp*(st{0Am4KpZ1Qb;#pr{4`MIRAR^f3WNH3=yCgn*)21QdNr zKv8W1iasNts15-|bqOf?oPeTw1V>ScDEDOn5_oKW?z*HZswJPZ>qmKwFQe#-DBC+p z6*XqPDr&;4ikdR3qGrsh=u2i*)SOurwP037EtyqOD`r*Hni)lH2qd{2K#l-Kw&ik3y$qo=8&<*ZjlE0|T$_sptjC9^78#jJ`}GpnLC z%&KTDvnpE0tcun%qi6#GMH>ky+C)InW&(DZ3Gnk zLO{`W0*ZDJQ1mMSMLP*7+C@OoZUTz-5Ky$2fTDc_6zwNCik3#X*9wq8R`YY$->IUb zM$v&NukmFR9f`6}%uq!~S+9zYF{`5E%&O=Fvno2ttcrePRz;_nRnci?RrEWvDmufA zqO$}Pog<*=JOM=)2q?NpK+z=viY^mSbcKMTs{|DNK|s-;1QcB(py)aQMK=g2x=BFM zEdq*e6Hs)AfTFtu6x}1B=sp2O4+xH;Ls9M*0wmxuU#>o^ic*=^Xn#d{jW46w^7Rz)e8QDhTPqrJwLQIr^MH=3)8l31^bGBc~9EX=AX zE3+!f#;l66GpnLkm{m~@W>u7vSrxs?jH1^FD0-cMqFe+N! zMfnLRDnLL{K>~^j5m5970Yz^TP*j+JqPGYrDndZf+XNI9C7`Gn0Y$|LC@Mj46lIKd z4;CPSTn0|2Xy=vwJ~Nbz_8MPCQR!%V@qAVE9_v+68D>>fmRS{*V^&4wnN?8*W>r*? zSrt`cRz>eKtD+B>QS>1JMU@FCszN|fRRW5t5l~c}fT9`%6n#WM(Z>W7)g++k69S5A z5m59g0Y$Y5DEf?mqB;Z=)g_?la{`L$5l~d0fT9Kj6g4C`ib_Sh_Y06f8S^0at}5za zelny{wAc7Dike2-cNVImW~^65Uoxwr=FF<71+yw@$*hW6F{`51%&Mpjvnp!Ktcuz( zqo_RrMI8tz>PSFQCjyE(6HwHJfTFGh6m=t@s5=2gUlCCBH33CE2q@}FKv6FOih2`J z)Q5ngz62EYBcP~10Yw7{C>lsW(IA4OsByGA%_31WA%nnaqKbx?-vJpM?KQrPqT$i@ zn@d#DH>_7hBbZguNM=!UGm{rkOW>qwfSrv_ERz(w-Q8bZ&qDcf4O(vjd z3IRn^2`HLIK+$vpie?Z{G?Rd$Sp*c#CZK2z0Y!5OD4It=(R>1m77$Rhkbt5^1QabM zplAsJMc)!ow3Of|8XE1cEkFW=%+Fm9Q$^X$lcevWy~dYO^nJAb)lyZolJ%-+6|*W@ z&8&*nFsq`q%&KS|vnpE8tco@;tD=p}s%R54iZ&Ba^aBA!TL>unk$|GD1Qh*5K+(?x z6m27*=obQtwi8gagMgx62`Ji0K+!G&igpuFw1RxHfTH^Z6g?oI=r00_9uiRWh~OwX8tuL+Kmyy$uYDX- zMTNXFJdXAnUq;dMXglhARrG@Os^}%NDzakqmAfi(F{`2oW>w^7Rz)e8RgulCiagA! z$jgkPNCJwY2q=mspeTlbA|C-ou>=&w5l|FQKv4n#MScQ`0t6JLB%ml20Y#|^C`v;> zQILS55CKJL2`EZOKv8-EiZT#Tl#$>ldK&G{BR~R`vkIJNs_3ctiP=msUgOIs$`WIL zxJngeWxXoO#;l66GpnLkm{m~@W>u7vSrxs?tcqS^RzC@IF>UVsD+MGKtFG0rRfoQBl9F<#@#C@LFck6ojR%CTM*m1kB( z6_`~~MP^l0iCGoB&#a0*U{*yRGOMD>%&MpgGm5GbP*jb8qUr<`)gYkgBLa#(CZMP$ z0Y#q>P*jV6qE87Zs!c%AX9N`0A)u%(0Y#q^P*jhAqWT0BH6WmPA3OcLIvOBB1DN0*ZPNP}Gxv zqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+G?0LzK?D>HCZK2t0YyUzj-qBUZfm_LdTxHh z`b$-GP(Ei5i}4y?M$yO^JM%_WG>Y}AXf(4b8pEuL#xkp-am=b{JhLjAz^sZUGOMCV z%&KTIGm54VP&Ac*qG<#aO(&pe1_4Dg2`HLHK+$XhisledG?##)c?1;AC!lBn0YwW5 zC|X27(P9FMmJm?%EdfPK2`KuGfTCpt6fGw>ioS_)mk}U=z2*t^2vzi}d0w<4#%p{T zMXO`%#+y~q8rG|#walt$9kVK0&#a0zFsq`C%&KS;vntxmtcreMRz+KwQS>7LMOz6d z`iX#|p9v`1MnKUo1Qcy2plAmHMZXeIw3C3MT?7>ECZK2!0Y!TWDB4Fr(S8Do4iHdu zkbt5?1QZ=6py&tzMMnvaqLnf3p#miE*!()|DphpX9GH&9c#SWk=(iaA+byc-6zf&d zX=YXQJF_Y}!>o$VGOMC<%&O=-vnsm4tcor&tD;NHD7s8Q(G>!Ut`bo62LVNY5>RxF zfTHUJ6x|@8=q3S0w+JY@O+e8d0*dYuP;`%gqWc6CJs_ayF9M1l5>WJrfTG6)6g?rJ z=qbTbbRx!mP=ExEn=e`bu6EMKG%(H?t~A!K{jG zW>w^2Rz+TBRTRmrilUfRQ8Y7(VhAYm5l|FMKv5h4Mezg_B@j^LC!i=mKv7Bpic%3! zl$wB|Gz1g{2`CB?P?VN{qI3ilr6-^$0|7-D2`I`$Kv5zAMM(rl(Tf;&=qFK>!F;{w zr79|9NM-hUjW44pyU%`Wn<{#R^{OZbvntBTtcqS`RzampYuw;pm{_qpg(REb#?z0a(QK44ZwA2O?=%FL>$3bQJz%B+g2F{`5L%qXfsK+#78 z6n#uUQB4AhJ|Uo}76C<{5>Ql|fTGU`D5^t1QC$LxJ}0249sx!52`FknKv6>iiW(76 z^aTM$jR`1fLO@Yd0*aau97W}P?l}S^uq2DXDX)rBnwR}w`n<-MQPj$3Z~IjhwPw94 zYQwCG+A^!6cFd}%J+mt6z^sZoGOMCa%&Mp}vnuMsjH0dt6m=t@s5=2gUlCCBH33CE z2q@}FKv6FOih2`J)Q5ngz62EYBcP~10Yw7{C>lsW(I5hf1`|*;gn*)<1QZP;plCP& zMc)t{MJ;^pKLtqOOY?KrEmhGJqiBTBYkV0+V|;eZZdEjv^{Qwbvnm?TtcoTutD=d_ zs%R3kDw@o!il#8DqN&WPXc{w$rV~&!gMgx$1Qg98plCJ$MRN!!noB^@JOYa56Hv5( zfTD#26fGj4XfXjrO9&|XmVlzA1QdNoK+!S+ik1^lw1R-5?+GYcNpKX6^11U0kU)3y zbJwF)(K++2*;PKT@nsaP^VwDQs-pF*S4A6`RnbOfRkVp&6>Vl#ML#gBqAkp-=tpK% zw3S&E{ltu-p9v`1MnKUo1Qcy2plAmHMZXeIw3C3MT?7>ECZK2!0Y!TWDB4Fr(S8Do z4iHdukbt5?1QZ=6py&tzMMnuJIz~XzaRQ1?5FABoeD00{Bv97;-1S;jG}nAPKW*`|R=iRnZyNtD>{as^}cEDmu@siY_p#qKnL`=n}Iky3DMKt}v^jtIR0+gMgwx z2`IWoK+$yqif#~4bd!LhTLcu{CZOmJ0Y!HSD7r^L(R~7n9uQFU7Xd{N2`G9*K+$6Y zik=Wq^pt?2X9N^IC!pvB!BKR|=iVql0)F#V$J46lmy|NR^m&ahqsSd=pO&v@rz(}# zvQxzV>nnYmSrvJhRgsrj6-6?uq9|rn6wR!PVwhEtk69JPGNUMtfTDN;iV_GY@)J-L zAfPBE0Y#|@C`wI0Q5ph@f&>(W2q;QRKv6mZiqaEMl!1Vvj06;ABA_UdfTAP%2xAoJxjlv0mfLD9RaYXFZ~dUS+)=i(X?^MXxif zqFl_XC^xez%EPRRl9^ReUS?I4k69JvXGT#00*VR}P*jM3qBjUAdXs>n!UPn(MLWIG0Y#+Ql*;3#?} z)?H431WqOhoE)ksrTGp>`B<;ZfTAV@6g4HFs2Kr8UlLH%oPeSh1V>TDSod%N64+*b?z)mH zDr%l2wT$%|Uq(^eSo^yZs;C|7RZ)9pRn&o56?J4*MV**cQDPV8SfTI2c6b&GtXdnSag9s=ZOhC~P z0*ZzbP&AByqTvJ-eM3Oe2m*>m5>PaX;3#Sx>pm<%0?W*USQ}OJTAU1{W4*?gQ8Yf* ze(;+rn!tKhG?7^qO=4C>lbKb~6lPU4m01-{V^&4enN`sYW>qwk8AY=QD4I<`(HsJb z<`PgekAR~21QabGplBfhMT-b1T1-IE5(0|8C7@_20Y%>tP_&GIqU8h>tstQ2djg79 z5>T{?fTGm|6s;jRipIve)14AUubVGdk5fgrjiR-&UgOIs+8ArU{ktmK#ClbxePvnu+TSru(#Rz<%sqi8z;MLP&6`jvp9odgu^BA{qD0Y!TV zDB4Rv(LMr-_7hNafPkWd1QZ=2py)6GMMnrII!Zv%F#?K?6Hs)5fTEKG6#Yg((J6wX zXnm~va{&_Yo4_dL2q;QTKv5b3ih=|bg$O80OF&UN0*cZTP?UjyqKpI-Wg?&` zk$|Ek0*W#dP?Uv$qO1fIWh0;{I{`(n5FAA*;@sB-NMMV3S!TyMuk@RnKNXrI&TD)b zMX$%%v6oa)F4n7}+{~&d53?#tW>!UcnN?9fW>u7*SrrvvRz(GwRZ$^k6um(}(VGMm z6(*qQEdq*)5K#0s0Yya#C@MxkQE>u_N)S*~l7OOj2q-E=K+(Gd6qP2R=sg08$`DXg zmVlyi1QeAgpr`@?MHLB-qF3YG`2|QI#{3nm*HqE_=G!5a;=IO}QB*n3u69KgRbjm< zs>-a2sxhmg>ddOB2D2*qh*=eV%&dxPGOMCbm{n0NW)yu&Kv8W1iasNts15-|bqOf? zoPeTw1QgXLpr`=>MGXlkYD7TM7X%bFCZMPZ0Yyy-C~8JP(U$}iH7B5`1p!4Z2`Fks zKv8Rgqv(S;cV__-D49v%e5i_&&38cB#CeS`qo_liJ@F4!)RFb7s1vg)>ddT)x-hGv zuFR^a8?!3v&a8^QVpc_8GpnK=%qZ$fKv6FOih2`J)Q5ngz62EYBcP~10Yw7{C>lsW z(I5hf1`|*;gn*)<1QZP;plCP&Mc)umG=hMlkpvWtBA{qA0Yzg7C>l#}6t#YpQ56>s8SdW>qwmSrtuVRz=g9RnZJ)RWy@X70qH+ zMYEYz(Hv$J%_X2{9sx!32`E}XK+!@1iWU)2w3vXRB?J_GOF+?50*byPplBHZMau~& zT0ub3_XHHJB%o*&0Y$3`C|W~6(OLqE))7#&p5Q2&5a&*DT@*!{uR2atMWrKT*bwJ6 zzKo(D;_U1VcyMZYksqV3G8Xa}<@`jr_)I|(S- zML^MR0*dw!P_&nTqJ0Du?I)n<00Bh@2`D;5K+$0WijELabd-RiV+0f(C!pvA0YxVX zDEf_nqEiGEohG2@cLIve5FACD;@lMkNFXUm;A~b!wcIkCjq@5`M$yGM`^(#^=o0Hy z(Pd^;bcI?8_XsGu zPe9QF0*d}3py(k1MUMz5dQ3pk69S5!5>WJvfTHIF6ulsz=p_L~R=mD!N0Ezwq6h+t z+yoS*AUKN7$GJxckib~;bJrJCQBCtBYj(WX_%e#3;_c;kRZ%qSRZ$GHD)KR_qF82C z6vwQJ;+a)Z0<$XeGpnKivnoo-jG|No6s0DhC=CHcK>~_G1QewupeP*yMd=AB%0NI- zMgod55m1y!Kv5C_MVSdG%0fUl%H7@6<}6H1({V*A!b$d z2D2)9lUWrNW=7Fl1QZn^py+J^ii#3YRE&V4;sg|xAfTuu0Y&c+P*jS5qIU@>DosGq zdju4fA)u%%0Y&8qC@N1tQ3V2uDiTmsiGZT_2`Ku2;3&!!@6PZ*6lF1ra;u`==Gpa! z@m}N0D5@537kj9RsMU4q4YC=F!Qv!;b5m59c0Y%LTC~84K zQA+}fS`kpxnt-A<1QfL;pr{?eQB)<~U0;9%4wxTItE!4T=4F5Tc(3tg6m^cb`#e@f zU0AP*x-zSxZp^BvJF_bKidhwX&8&)gFsq`T%&MptvnuM%jG{gS6!j&bs2>4E{Rt=< zKtRzz0*VF^P&Al;q9Ftn4JDvx7y(7Y2`Ku8fT9ru6pbXHXcPfOqX{S)LqO430*b~F zP&A%^q6q{?QO9`q0s#_OV;;mhsiK)i(ZqPK@nsZEjkkY&s*0wuUKLGeRz)+IRnbgl zRWyrP70qT=MRS-{(OhO#G>=&o&1Xi@0s@K_5>T{=fTG0&6fGg3=vxAcmJ(3(9RWql z2q;=kK+y^UioPeHXe9wfs|YAsO+e8a0*clWP_&MKqV)t6Z6Kg%BLPL52#%u3@$Q=f zB#>W5dx|Q$X&&A-$9s)0qiAcq9sfcV{lt1z^fR+6+QzJkeqmNc+nH6-4rW#KE3+!v z$*hWYF{`58%qZGJK+#?TiuMsuw4Z>Y0|XQuB%tUJ0Y!%iC^|ww(NO}5juB9FoPeSe z1QeYlpy)ROicS$wbee#o-w7x>LqO440*cNNP;{Q)DB2S5E+{|(navNT{iuqHo1YB1 z5brg>jDVu&1Qfj>py(w5MOK2o zY)6rcfT9QjirfSgr68clCZNbeK#`Z=D7qBy?kYe6r_J}#E~}zUX=R8^@ETu6kuSlX z9HEM0S+9!Xm{n0cvnonpRz-ehRTN-WMJbt8Q7UFtl$u!;rC~-)vJg;|m4Kpb1QcZ_py(9>igFN8l#_s>R|zP3 zjew%p2`I`%a1=!+xVH$9zy$MDC?>&qrGM5a%AMdfzKo)L3HG@Zswh9}RZ#(ERaB5! z6%}GuMQ<>xqBogUQDJ6P^cJ%!D#EOa-eyKoQ38sJ5l~c|fT9uv6qO{P=p6!zN)b@> zE&)ZQ2`GAxfTA)46qO~Qs2l-B`g3K4(TzJpzjA6HwHEfTD&36g48C=nDdh8WT{|gn*)^1QazRpy*2i zikcHp)PjJbmIM^FBA}=>0Yz;HC~8YUQ9A;P+7nRJfqTz1a~C?5?E-yk5)q! zRWdL8J0*CHFQceig54rY6?JF5D*B396@AUDih3}sqMppEs28&;>dmZ*`Y@}azRaqq zA2W*j6HqjOfTDo}6b&MvXfOdqLkK7uN8gtUGK!`oc#SWkXhwql zeT*ua$$C{Zi&+)TW>!UWm{rkSW>qwgSryG^Rz(Y#RnbCbRkVm1MT-e2T0%h4w*(X| zC7|d#0*aOqP_&$Yq7?)beNRBqN&<>j5m2<6fTA@76s;woXdMAX>j@~@KtRz(0*W>f zP_&tVq8|t-+Cp#?O-pbe7a)NT&A0KVtD<%07eana@ETu6(Y6HpajYu(h4rdvJF_a< z!K{jYWmZKynN`s)W>vJCSrzSJRz-W6Rnb0X6zwOV=l}sl2MH)TL_pDD0*a0hP;``l zqGJRU9VejZ1OY`S2`KuFfTB|b6rCoZ=yw8&&Ja*^mVlyj1QeYopy&btMHdMuxMuRz*Y1cVjOnc#SWk=+6YZM1m^1#(GtBommy#U{*ypnN`s(W>s{X zSry%3Rz-K2Rna|WRdk;jMGpul`ip>~hXfQoBB1Co0Yy&;D0)gj(K7;yo)b{?f`Foz z1Qc0*ec6s87Xd{P1QfXmC`v&S4DniRTN-WMJbt8Q7UFtl$u!;rD0Y@L1tAHVpc_I znNgIEfTHvS6lEZwC?f$ynFuIKB%mmXfTGL<6lEcxC@TR)*$61gPC(Hs1Qg{UpeQE+ zMXwT2^cn$0uM<#|i-4ls1Qg{VpeUK(D2nyF7YUHSd|Tke`JGq#4a`>^^ZLEUmr+#E zZ|_Q_iVCq_6}`c%ir!>aMTMDF(Ob-_s0gzvdYf4l6=haM#h6u5ab^^iAfTuu0Y&c+ zP*jS5qIU@>DosGqdju4fA)u%%0Y&8qC@N1tQ3V2uDiTmsiGZT_2`Ku2fT9lxD5^|A zQ56D;suECCjew%+1V>SRzx%cT2~;yL?hB}*0_Hm)HT+)V%P9K9Z~KF)s21y0(WlI+ zs5Y}I`ixl>)nQgeb(vMs=gg|89z z2q^lJfTHFE6ty6rs3ieKtq3S;O+Zl_0*cxaP}GiqqV@z7bs(UqBLPL72q@}IKv5Th zqv&J5`wamSSYw`D*HlHvGRx4_?=`-RqObk-$7xkj57w)qp3JJK7qcqr&8&+0Fsq`z z%&Mp#vnuM(tcnIOtD=F-C>lgS(O?3Kh7eFRlz^gP1QZP?py(R{ibfDnG?IX#Q3Mo? zCZK2x0Yzg8C>lpV(Rc!iCJ<0Gk$|E}1QbmsplAvKMNqwwSrsi{Rz(Y$Rna15RkWB{6)j;_ zMc*=`Xej|j-w{x>jDVu$1Qe|xpy+!7idGU(w2FYD)dUo+A)sh20Y&QwC|XZI(FOvF zHWE;@iGZTb1Qh*1K+zTgihd-ZXe$9lKM@>7GyU$Z0whr1Cvaw|qJf6g&wj7*Wfbl3 z+ZQsbqF-6Bigq%qqFv0YXg9Me+QY1h_A;xYeaxz8KeH-2z^sZ6GNb4a0Y!%iC^|ww z(NO}5juB9FoPeSe1QeYlpy)ROicS$wbee#o-w7x>LqO440*cNNP;{Pvq6-8RT_m9B z5&=b*2`IWkK+#o#qv#jEJ2I0fYMNf)Y*$77%x^XR;rAL}M$rww{c4gby2*M~bc}& z(KWyO0|6393<#X-s%VAzc1T>nYkV0+fq>mAiz-UVdR3H)Srw&bRz+!;RZ);x6@{2p zQCenIl#W>yrDs+}8JJO&k$|F11QaC_P?SVKQDy>)vJg;|m4Kpb1QcZ_py(9>igFN8 zl#_s>R|zP3jew%p2`I`%Kv8Z2it-RpluSTTUIL2p5m1z$;3!H6xW@>PzyR~I%pY)G z=}!|pc7cG`_%e##4A`r(siMNHS4D3ztD+*zs_1QIRaBH&6%}JvMa7v_Q3+;MRFYX0 zy~B*6QUnyeOF&U+0*c-vpr{N1MP&&nDn~$3c>;PaZfTH096n#TL(Fg*HMiNjo zih!cg1Qd-SplB=sMdJu48c#sc1OkdC5>PaWfTGC+6ip$ZXet3k(+DV?k@yLV2+G-PgRs`NX-g(jV~*W6=7$MTAs^g1&hhEZYx+<{v2(JU@!SDNn~)g zJP`VV+x(W55WFHk36LuIy8P&EDA-2MAwzJD`~YQA@VPw8$`*WA{)L*H!9kfVD_3xz ze7hxYF!d{zRWSHzPRlABocWq%6%Ag=WmzSIxsxrcbg*4M%PJRKSHQ9=1z#4jtjfXn z3R_n7;E*DgRWo>?sAbg-21{7h=fTh3v8;x{+3#9bli(lkSyuC4ayiRt9qdrSvf2kX zRI;qjLDz?t)je3Yie>c-4y$HaeS?Q;Sk}N`+M1R%G+4KmWsL~Vt!-Ijg4gO;)`Vcb zdX_aM*r|bK%?NI4WLa~9?k1MCAXvVcWi1JQ)7-L_1&_3}td+s^Z7geTuwFaM+8CVQ z!LqglZ*;P(pMwRuTGozWm+qFeJNU!bmbE`<_p+?R!HRt>>v(WvKg&85JT}0x&IU6M zwycZ62170DYH;Cj%eo%CHNvuP2Mdk1toy-kV=e1Z@W=6%^(^F_B>UeLdVh-C0ItyJ zX>tp=LMLX(P2dV8&X(K26>2nBZUk3o@qD=zT%kJ)Ve3YmWpIIk;Y{zcbI#{E6tAQ!Wd2pN(yoyCXQ|4$ zLgwEUs^kipe;B5+D`fs(_RL%pXVp+!Zo^-MXPGWd1yH6IaOm zec9%&kog0ltz9AW7arTYLgr8Ob#{f!-&pJJ3YkBW)zcL+f90sJD`fsm%|KVk{GE}Z zu8{dd5hGk7^PB!-Tp{zT+7nzM^SicFTp{zzk~3T(^V@E7Tp{!8N()>e^ZO=CTp{xd z1It_?^Aq1IT_N)$yK7w`^D~zlT_N*Bb6Z>?^HWbhyF%v2R(7~T=I0J}yF%t0$NOC& z^PRuLu8{fG&2d-AeC_>|D`dWSde#*(U;Vo13YjloTy=%a>(A@1ka+=d+Z8g;0Pnj( z<{|u%D`bwr&s*8RH*&-NCU>!P;>9{+TWPl?$tMf> zcS=j2&nLHfftZwXLi1lGxv#jUEGzG_GIWvTD)6>hEnij%|Cgb#`~&o^0w267pDH7z zxV&X}JBw*8OzSDL*+|BS4AKh4nY9<>ZMwW=Y8fZ(jc~Ivbuh!5&XDnh+^t=O;{>nu zt2|R#E^ir6%e8U66+S_Kx7?2MmZ^LuX+=1PbTYiHLw7S2)uFn%ki~QeWtE}04k_fE zT_tqbC5I7LNoPnbDBCvII!hjxXs+z>f4}axZ@VVBs(AblXD`0?b&{*9?fa_J^lVA4 zYPK(3BUdRavm7$4O|mAjv@ZUf#ZS&$zR@|nc-)=I*W{zB9{=d4FIRR6ufDNqR)UpS zM;7gr)$N=`uDn*_0!@RRWczGOu6E)|%`?d{mh9`qEt=Po{gxay6XnhlKHq)hpp{bc zam|;>iI)6IXW~W8&&jV^*(J+8AbcjNlEb^h_9a`dOMa&Lb#gK5ZOM@?=hUUhWvzE5 zn{No1YxoKIL#w=Gp&ZVw$)8x&Bn!rH9zbqn)stLU^EC38R%6MfHLoJKv06y3ta&%N zkJUqRZOs?RL##oPn`nMQ9&gD3F|oa7e_p-vv#qI;duq-}{??i=d8p!TXM)tT&B4%`HXc)@*$(PLCDRGD9735o%9LEw5YyOq|)Vd@2 ztmd<1ugfK9uWNotj(5qyDe;l!xO{r$)4EbiHuoHJTV^L`cgX=NF+p=t@|&&#k~3(o zMlR-hOL9)l&B#?;6(twc+>88~>r=@kHBTTncGZ(yN%ME)4z5;`Yij<5+{4vPazo9h z$-`XzB)8UlpFGhuQgV0AG5Ph%&vng~JWz8M@^aUAlE-L%i@d?LM)C~JmC3)lew1up zgPA?pn7q%mNAgb8H7_AQblsDDO7l--%X%(3lN>$FLG7`V zJ^sf#MvRhUkQ~&m54*LhTll!NcjVL+@=-O9fAFJQS36sov&gFOVXaIG=Mtxun^ca8 z<_I-Pk~zn+PV)HwTD9uzSK)K)J9O7o=NwP3>A9-AoMS|1%gQ`XR)o)OnVwsNzt3&2 zq+@b!qnu>>qBj)JAZHfQNwz1)+Y=jGM}&`=ctFktemDpc%OHOXK+F5q2_WpF;>NM?BIU8rIi!`s|+IMquXRBK^ zU*zPv)xFxE(RHgQwWlnk_XB6Emo>lcWRG9BdRKcXPVQ{=h2~nET(=r6kI&|w(3Y-S zO{0AfXX9)&i{_b}T(_D>`&v%!Y_*8y{hVC4T1NX-x^A_q_LrQEv(-A9gKsDU-D)%K zd7N(hoUL}$T!xeDR(or&L)Wbi*WQ7%ake^1^Ds`XTb-wU4kvfEx7Zi_s6d${}8!YnVG} zQPx!Jp082(9>4Y5pDvhtyzRSi{GICIHHZ3*-zoTu$QrYq*3KG_f5fPvv&|DCc_PuZ zi?gAgf1bQ+He~ziw>T;HjQhG~HrpwA?MmtJl6ni9G!9?3RbvmVm4l5eiOUinv=RgI zywqH@BP@yjzC_;ek`^cIZ!Ykr^<35om8M4CAyXvekhqS_)p8lOmYl@R6 zA9~=cswu0J+$GCplRL9Sb2UG9qQ`%9+K&UxlSbQD_(BDF&Mr^;wobqHz#I&1Upvpr zBJu=4)|ksYlr?wfURhy|pti60S9R_1nxFcO*k{&w{EIft8!ER!-Y927n^`n{)Yi4~ zoKz0vJ2o$!DW{b!JzaZcvpJBP!*1dSvchcUuCqdzPOaNCyp@(eyb=hXe$dTp=jA+P zE9ZvJUfRVf|_qz<1|s?K`#6tkONLJR!90JreRW#B zmNUHRGkvxXmTSIR7MVR-OlA*d*g-koWI)QG$pOXt-7HB&Kldd zap%-d;k{C$=OA;puzeGzRmd0K%<^rAc6@DRo+i)f&BaX|EU%c%_BOKii`bmyWv$%Y z;e`{&mQ61UBf7}$Um~Y9SLi0E-F0BYo8jGZ{qVvM!zW+X=0!|+ucW*a%57ynEGxpB z@yQEEvzhE~>%RE*;)d_c)$;gnP1&EE@-}=4q;^4M|4a18^@7=viHt9T- zm?WnUKb2Ui=djdSXl}xTlFY?E%f+6#Z0-zW*W*8R>6gXMJ*3yQz9Y;(vSh`^CX zzMXe@hwLR;vuNc2^NLT_WT=rNyOnrX)|gB7727#6W8qkX%l5t7XoB1)WzDWNJ9avE z#S=5fP8M7_M!)sD+Z`wiD*uFetYJDV|@%R^<7}2Y{xRxbmJD1tc zsonefILC;2ht`?niEQX`|LHrO8{@@aPmjrwx}$C=ZL#oPuzdx4TnvRb6#cZXd?0IX zU0N_tu39zQfBEQExdV;UB_BFVJpL06{}7QRLom(E%(ckZuciGecKSz>PHI;os<`H5}! z|9RdDb6gSj;qAWMdH%4uuo3bVvc%GPYMbMk?K^sV z_@`E4Ras&7dye9|I~w{IJGWKKFB4sgr>$cnJ$Nckd$S=!K9 z>ha(HW9(zu*K!RDTyG{~&Bn84(uqgQ%$?2l&6(Q1 zVt9KGZy(MPUedVgz1s4kLpQUNOIYE`n`vZ)I5@C$q#SI7#@C^9Uxt_5c(hfXH?PpG zJZCG1zdyO&$gq6_5A-f+miTvXnCU!DuIl|=OL>Kg z9}(UIXQRs{T8X}(v!7ih_3HGw+flBrEEzmv&S|sLJpM<$f4^xSCp`Xz54ZG{C;aJj zQ6UyB&Cxj+UNmLE1I!R{O6x6di<4@m|xd4WzE#SQ{%(er_Eb0orm2y z=g%*f#jtGE;a%Ge^fe$IcPAmaTEHl^r90jv{fmF7dn*-U%N6kRyK_G}z?cy7}5k=L&6z zIw8zuJN+k)=`DMEM#$N7Z#j$PHQDu7<>rtz-)vZL(BYPNuW%(S|*phSECs zh{`N+S>`FhZOP{T(aXuLiN`;8_qRReD#+?>7iWw!w8D4%bh5(SDfc-m%#q^*J(Gx1E=!)= z*uK)U%b15mc`1B<)D!25+^@2skaGdj##XWt=joC{ENR?kv)mO0=kq-~M1pMf;PY!e zdxV!9ne8ed5AeF-a?TR7;o;^{|MUH$9OCP*&N?TD z^7HbQIdfQ8?kw^6C;t9eZ>fvh*4}YQY#MNIwp?tvsV2`qdsJ?!CGyo#v+5G7<}aPT z-Q2#m|Kx#5EyI`h?w$>^3_f{Aw@$uNpO_}mxp1L(!+XW!pYe3>k8&f(b+pG-s%fb$d?CXN%&^TqibuhcKg!PtDVEj++pS*Ec>VD*53}uEhXE_u`m>A zCCZ&Ke8V(x)|mZMOV4JqlWbqF{yog|8r%0QXHoOK-}X(5DVr{QO`ra7aFN{0*6NbI zZ29G$$y?=W$(kQreT#(G%xsoZuCi?Se%lFNEAgmq_}t$c&YR?1_n>?&G5mD*^1N~L zdJrAs&EO#Bb0{utzHLr1GFaJJZ?fmXm=4P@geD(Xw2gXg6KrM7)pei>kHF^_-cranuZz1}=)Q+W<~Ro2`wXLw&eFc!V< z=~aIEvfnRZBEIewmzv{~?c3I-V5{(sn{no~Sou<37H7%Z&Jx@AO6DYattXpHGxUr+ zn9AmEPMo~K+zCAXU)MfAAh%CpSz~t12hJL^Ys^35ZnoT;vuSbpS^Dt49=_$OdDd_Hx|ym(K0;ZO-vx8yc>D+MJ=!GChx5yt zu&58@19L(8{k@4Y*_|}eNfD9HSF24^*hYv_W1kU8#6)9NN%3WXTCB|d}Mo< z_wACe6Hb#wVO5Ld19RKfaaP;D*Ka4c4KKd5?7@1GA&0o}OXmv~S^VhX>HYHfby(Mo zVvD^7jOpuKiP1Oj&vUl;Wcas*!#7lmtsT|RaNhS$vfb@DHAsFUk6^Vp3M!fta;=Z1R6S!BfQ)KvZNbW~I0 zztee5-JBE=DJ!$QYFRI2hc0)TyoUN?#Ab6JmnV5Ur*AYnM{b2N3wJp3kDPcmU+#5P zWtDMp(OG5trcN1E zxntLVGzV^3GjimdG3Kh;zRQ)aCR>S1bu*P%(`|Jf=YY`Q*Iec)vd911nX3n!y|Zop z#eVY8v{|oE57xZz`n^i{qD}htTme~Q`(GYf<{U#796Y_aifBXeCB)k@_~8tT#4{x{ZT$JZ=S0%nAgMR&6C3Iv0Q#v_PCTW?zr@EHG+Ou zf;^Fm$Y#aF6qjUK?lhJ=u1L(=F>l3`mscz)^fQt2-Pl5wDV`KAcUP<_2(Bq5J3r$;&rMsVe>SsU69@Hn$qkn;yz7z%_jXwkp^>HJ>1<~Cgk?Tq zSy?!Z_{n3L%hfV2yfwLA*1!HI$7XpNTiLuTEHopmk>$+$lJX|myffcAH~C-JIg>p4 z$;qmice=Wgd0!^Hx{7(Ht1JEI)$(FnR#r9d^dyxzNrdH!h;X^&^ZK4Sd;;mRP~IY( z)4L-6}z8&9`SFtqxYyvrJh-)6KO1A0@+dGwl$savGO8 zO@`^41-*GQ=V0EOuR?mP$j>`j8K#?$D?4*NGn&u(0P3k76 zH6MTB%$dz>KHmI~&zq0;%9~kh-j9*HrOT>uR^Hu|HG`BY1Jwr}3tR%Gev5%Q$nyoHA^~eATi(k~g`G&Mhnl93wyqF8<>tmJ@WBH?ypi>>u;S$ED?Cv!C0^el;I|E^oH= zp&19u&M|N1q~^W(A{!u*rkm;TKT5XgX7VNc4IpiG6=bk}6 zaQ2Z<*8j|D{`ucO=LETPyRCz=B*OJHE>?E5x%NRcIF1c}o26gMTZIPTWZ`}fQ^XJW8pGt1pvO)6>4I3r5sMnxL)0Y3AUyOEL+Wm7+G;WgoPTPhZnzn59ZmYJ9a{tG^ z=-j?-c$YYPq;lI<&19dqORm`7^-Of(-9OKxnZ zG@tSmb57zZZbhVUrM6?tyLdaZc_*I_kLH~6+o@#?6th$2HtTg!vYpDDhs%zyV5f0M zC%HT4vEwt@QJySz8c)h(^HH*Vh|Z61446ikIrm|q@-$`Y^Rs&mM*iMKGBYqdulqFVm*52PHC=R zy#1=)xx-@~`E-6eqghnUPM`Z9i}XV1qMZL+lw`-s7~#nu{{NJAI`h7~#>}=k-bA=t zVqg?;E2}P0Y zyC`9ce>qb$l#9CegPjLpgP=%o+wl%abF6`0WR>!IPGhKy!baMPE zuIe%Ur}KMdu~JG>r)p)hH9w<{kKGaBI{fjB#&tuv>WqnVR$OO{D2VTwUaNG^7^`vf z*6$x{rW%NTb#w>j<&^m4vuLGvxVMr2%V#T0Zxa1wsg^n;lu4^r+gg+VpDsNAkDS^S zme^6A-Lzg{8!_Qx{{fd)Ii(`^e|}qVQ~FJoHU6I{vsdYEOyBH3bP#j>ob+17^0gpZ zQPuKyOR`lhnF?2Vul~uC*Sy4Ac^%TqN}yG!kF|S+y}iru=atCcsXPjMS^r}VTNw*c zD*u@>-%4uFKvy?wuXOD-FkUt7gK&(i(gKLOTA!*}hlL$l>4sN?RmZ}0;P@SzaV2a`tFG~h^j(eTVIzO6lX4QPjf#3$Ez#C0j-aEZI-br}ZCO`ppo`5HTW<>u zv9k`Vmt9q+;uBD*vuGqKMWgh3W&5X9%v2AKgWe*4%%a)Rm{DMd-t&m zomlLbvM^f1j=F;#Y=<6cN6%R(v^Te-j&{(A4pCc|oHmhPqeSnJdOaJ*n(H6*eyS5W zKK51MpKLF+AwM%&Io+Z)T&X%}>K0PuEJh^EPc|E$ z+aXbpaE{|kkY#MR?HQb1@xg8rv!`(>qG28k4i_lLC<{yHB)SjQiPH%*3ggn-ZTlj} zc=U2-7QfOn+;n|>h%^1-8ry!dI~PPfdPi-C=OlLKHedN|9q;g}9rliYec1VbJnUvQ z#wr#UP`8S+ufl9`o&2{>ai{U|`PF&tSmGm6)*-YZDN0Q*FML?4kDd39c0Iir-jNcq zo1IuIMT=c5kL_TaJS1AvZ12%gpF!qA+r49sF1i+quNVv2_Dg`@g^v)T2EYrFqHicbpTg6ILEYt_8ssEa&_(Wm)AM&y!&!{y zkDBXGGYbm`#uMTPrZz)Rv81P>UPh;$iu%H~bz4tCQP|}FUuP~X?$zH8wwE1jr|yMO z-(gX^#7=(rewO^@=|;$IY&gyUx)X{iDu)`bS4=*fQ}) z>m;r4<8oB5@<#kBZuo!I+?|F+d5QL;Y`+uRj*s%}sfC@8PM({S@9E)e{w)542!f#)XuR})4}S1guPomH`EHtwSJdx$l8Ie zsFD2NGn=&onp*O@^Zuk!ZpY$}iF!|nI>vQj-?%;BKI-e8fXt|8fjuTHif37!v(nQF z4eJwlpV5o3*!pZ?O{+ZH=znmn@xByf4^?>}io7=Q#eWTuMc>BlN4ZXX^A38+6d&D2Cj}|wL=-gRf&rX_m_6D1F@he_t zLn3GGvNW`^tTExkYId8qN=zIabx*t+?Gw(LHM@G+IV_xRQ*PR|AaVE}OXu2>Pi5Hs z)++I6M#1Ig_Susz=|9xKOuU@6kJ^7UsAyBR~H!7Gv8|9B-5SBeEqZ>aVC&o}9Bsx`G@XubTsT@FplUcICC zzAl~Uzj&K&LN7m`&6*9Vjr)z5dL3_t4S)`Xaf4Uw4c_BRt>AB+aF+gib-gbYU*%L| z=WlKF?``bAXYL6)<>)`ZXL-YlqRxfJQ8#PB%(Ztl|MQoUMi=+6=c+4u$&DwAf9usQ zo=b*CO>wXFn!V(?{3=;>cn8dp?h;<(SS>txvjQb<@G$Z^M1^+fHDq~5z-w9S2!vj! zbw1qMVsQ)Khuq`o{r)gLj_JHMEvDG3x6l!2{vKH92yn8~A1~{MUg=9z|D!j+{E11^ z>vw9qtoR+D(7@~*74-L>ctL@`e`4-H9NYJ6m6JK-~`+FIFc|KY2^w!cOH>Fbr&p-+FK4iZ=8;Q#hEQ*HhtE0UWoBHKh) zY1@T8;)|tj%knqWs;pwwL0ZwP2OSFs#IJ7@+H=ZPeg$j=J)1<&c(f?}DTj9cpXlP) zE;cLiJq_v0b3FJzzMYEHv0#FO|*HOhbyr}Dq z|)jA~2&u0AS*g7%k&lLypxZk_x0Ui4pC~<_ zj1r$^gdR#{551cYcWsz9ls9oDLwW6TI!E35M+Iv~-4Z+7y%B~s{T#3KW7rriXkFoz zj~GYRVBWx*cfG<=z1Ff3)m?mZz5cV`%ZVmL?W=5YYn9pF6w@#0xK7k}ZCkY+OjGxU z9i`1a+JA?~n^XTKgS0U=@gQwH@c-X8NV^JM;P7mKq1e7r=P)wtK~(Imalaf)ZuZgH z{U3CxxTve%C9#d!&~^OmB-M3v7*^8v^am>5r-!8U`|H1Qs62gV?M_MCdF!vozZthm z{q?51jMGd>!*eCw&RS{K=1y?ane@jG-V}(-2EW_GFV&^3)}KVBT@W_&mt~4Ss#wF; zXzh>qk=OM9{2<#^7grWphiPckKCvU^MkooJm#XX>YV@pPIZ|ln!TWFnTzOd2EBYVB zar-7NHQM=FQ>8{!kZ5IlAD{UYn=2enu|@1qbo#=f`sMB5j|Cwe{kua$VRfr|Q~DUY zy?|7(X4Jh~Tv90TLSscAo5S1e;9|<+=bQ10{@#A9`rIoTi}Rb#OO*C~2BdA9GKMpW z_KMnPMtyBGHm-@R=KquKWQ@*`6f5yFVQ)UiEHynZgrzXun$Pj{rssuBZ-!uDYPE`c z#9Q;`v$sQWx#^vK$WYBQephmV~y?G3^|6mx6F zWr<#k@E+fg_{|-ArtiNXF#s=dvurEP=UBuXZU1bJ zh0M|Jk8_BLFk0)sZ)@K()w}@hWM?Km=#|yV?TyNTYeZ}N#T^|Dw9^oOEc}y?p+GA7 zhaWriYt!!XRqgaOr^0I5_|i7jw9ThmO&d>ds%e?ttdwYi zP4S;~`n>tJDxk#0n%&gi365X*%Cw5GFtXaU+0!*{`>c&urJ(;`R^RqDkbB1UZO>3D zdtmi#&rsho+3v}vkDSEl`fdoL$` z@50|WT;-QW@)GU#36Hw|;-Nwt?>Hr;Yiq`4)K!daEG{VUsgMDQgy{-o3o*& zO7m5gjceShX~vSe^2VCl$u@I+Mcw3z^3;^^lWe68HT4aXCe`|c#z|GvDykbRYwISK zOb%PLRW+Zzw7RxzLSuQ!!&57GQ3 zruHXwh7M_58XrMRBF)>dU6-zD74c=OudR>wpxmfV?ZEJO`y7Slt1Pzrqp`lWva+$+%*E?9 zo4c%}rg3szNlpF4s>$)1>ncjhr^g3V+6>sb`Vw1Fe5vgO3v9MoTVK{#Ke^V9YwV0R)>llP?DsO8t}Lsb5by5L zVd2gh9&a(;co9*2GsTf1tZOw=6N~NirPfweRaaTkSW#BiSX^4A+q|sVtr!^HZckF>?>rr9msSUaVnuClsz>hc?{s~MXrHjS&2iK!W?CRt&oOFYSnll1a5KBRgh zAyr5YNu99Lw3Fi(sA;wxP~G*gaNRT~*dp>c^CNVU{{|#Y0jzxZUa*wab>4&saL6aniD_Cd}Ts zYT>NeJB6Fl?#Wrp7A)8~wY~Tjsi>`Lek-vzRy0qnt@BIdWoKB$kocyVzi8py0xQVk zY?y5_J_p72fo1Ky*4H*wU0xNWrl~BhtEjGs%WGe_qB&dP>ic=H3tUwhPE^>+h_tQ5 zWszSnFZJRYPJ7vmB?^MZlCrXfx{@*#YpMMiXLaAy5 z6{)N0A5*(4NQ?`+{~J^l+HN+@U>hy1E3xWcc=;CXDy83EcFHJ-SBJ*&X}F5u$S=A8A~N?V=5(o}pm6%S=)wTT&_?`Z(vxF5Z}u2=}Fxg#lxGeh}(#(l~&is%MCS{n-R3a zDz6Ek>hjvSv`y78zLsIsT2|`lnidx;vzk41Cb{{G8p}7H+*m#?RPN1N0wdDqSHU&W zil&CTxXy|T$4Wah_2bftY9OvIneOdMRmS$o%B(rd7S1dhHZ&vM4GSdME~cMyU|;T( zbNSO+#?^K+Gy%ZY$CgZ-ShC#K$J(FrTx@@Rv2MwXAw|PR*3DQrYtaHKg8F5lfoAP9 z&YIoX@xC?P{l&#GMPq9k3d+`7ufYGV=iuT3|I405BZmwt=(l+G{Mj>>%Xu-_w zmW`gdXz|k7I}KVebf^VO=Pg^XmFb-Mi)JhxWPcWPw3QXJJg_Et+@#*`@<4t)mAT9jqBxBd~QP7o4P@Y zi-x4#AjL&?yV%hbubV2O?ewQs+H}sm#n-447nZQPH2z>0Hw0F`rCo*iDmV4)mTR!9 zglt}+46`-OZuCESI(zZruukjftzc(Dab8zZ=6e;IvBlP5jTZ^s+n=(WC)nr(JNXZ(|YN0>iD z9RK~;6>Q$ywpJ#_n8kbF)CEoTokyq|3cW^F5-N*|iIdX0f@MB9kzO_VSxE26j+<)Z zA7vA)cn;^M*=@+}$rmv(!SXotB+q}2hL}YnMS^TGPC)=OSO|3uGjQQjJ zW}SDt#@qVsmYO{rbwf?b6uX!m+8l*t{3$M5k^ZcBFn%Rik?Iz8ZR;C8@PpJ;I8; zk)>@|`&plgt(%eBzqB(jsjhZhmGwvMQq)+x+r~H8WQ>UKh+|S^4d6`-hQ>zwo6b$6 zEydP?w++OdmsAgi6?oa0ju<(hRF;(6(9m*y?id2!>R4kv)i7%6jg_lvEw)Yzhh}FX zwbwMk)1i+~d|7;|*azRYYPS;Lu0!3u-T$)?`Bl^!(&twkc`#F@411roo3| zE9Wzo%(He@s@Ls3!gvE##m67K2k1fQsKt}gZYXP^H=Q9L6plx3yiH@H6^&y{s=`pA zahIBnlVd%PhU%u~i{nlUD7`(L8Za8dfRXndIZ>?4TQC{h#AToFqIcaI8@WlDIlaeW zL$Xz6R+?DpJ~=*Psa4inSJ{RbG>pI*O#1`(|J0v#FQ2{DvbpiO^$sCB={IFbX`n0& zTQh}Yt+algb%`4*t4r#emSbweBxl^m92k*bt~-{xN@bO0O;@Pc2gccwMp8m;8DH`+ zs_!4u2gl?7;<OQ|q+6;!oPAeyOKdguXMK#^$AfV{FZz3L65k!P?LejQ7Jwy5kRF z{9Yp}s#em6uj5_&VQpsjmo9pR87N1ez4(oXjTlR1_gYLsneLw zTdG&Ba~ls)$D5@rZ>q(@c(YIR9%MX|55BV3akXpL-ncEZ8*ari1?)!Q}r-QvLwV`Z#P!~T$i6?v4 zhly$Jg=Ql(@$MC?y77)t9Qg2P{2>hG`bWA##pxrXTC0!HSK2MX$P^n5$3~f=n=oyV z)pjuL^3cSIH*6Om>_PK+;@i+FvB@QM-aNEh#hN02b~~mG_v!$P!&t3vA@t7JQ+tx2 z)=b>e;9)|%D`{o4xDL&q)R3p$)OHv?FWn%X5f+D$+ITfSFdBadO=q_3<#O{XCv`Wb z-#}qcY!&g%+;my1OD0ZAtGUA&_oscn-loT1O^yFz8*J0wa+ehQ&}Z1SW(7;hBx|Ej zv+i~?-qUt3oQH59aXj1(&aypVUVgMQZYNciq&GrXf?0h}()tuu_i2Aa1>uuJuf4@eaJigsT8{#4m&<=j9)fy={K#y z9-PuJWBv5C>Kp3qS(y5|e;DiZVb0|qbTo}aT4mB~(50ytXwTjCD9v}zJ1MEY6WjO7 zKCZ=9)K7JG96tJ9zLrW`OMTe-%sy!I?N8`16 z*2@lsfqQ>2xO_d}^_xFRr`+OEEK8PFm()zK+qc5T(w1u%`GG7yd(&m9uC+&hR+!jm zY)MVpn4Mpn=3_3Qml7K7&1%s27@Njl!!rqXtf^JjtWV;rx7(n>4vT&B)r3Ap{E5;x z3~{C&0WRKp2ZnxA*C4H2A6GZQu3ES!tBioAVZ5m&*3G7PW$(14kM4L?8ctQyfT<5f zre;kIZF`4qY@K(XmpjwVx{wZ5T%dSYhn28vWhG^H(kmO|ra*>oo_8YX{S=3xS3ec$ zU7bKqTFb;cRiWJS;YFW4lof0-E(GfT?1`w3pWRBennK6K*H-MKkgP1OY-&oHUUBft zxco_&)R=ny=;xDaq-h=D>P)Szo1oe-)oLiV)~1z6%xWbLk4T#Llqziul1_%dn2|BI ztZe;)em=fmvUov3#e%J7&zfbA^(OO`U-6JXU**;R&mRC}w6t$^`rUpqGqQGT-Lh52 zF#nn-{rK0LmA3A?U*7(?2P6;7IVd_f`;f$;Sx01+wjPr>p+k$-eM|Ez;{P);O4hT5 zX85;=Wn>oG$7tlBiG!^}QInC=HaRgb(IU59c8AQ4nVl0|GFQ*+n%OOLjm#cdy)y^< zm!vKClOAPfeEEC&+2nosN7KA7zf+6m)3Z}w3K^FFB(>47{_X5L2E$L7{)Mk3{?YWdP2MMM*P+S# zs@mAs*oB|4{89E@mw2D>CO3KD|w^ChyDN zo92D`Nqw77A8FrD7=FV3b?DdRefg`>yf6QzedS*GNuBuEChQ9b(|_!%4b!b%-Mr;| z>cq!+V!5lG$gnRSO#4Y>q)xQvx36_f`$_mWKBoO7GCF4X98R6z5ABSn_0y*NvDp2X z`f)!cj8tI>=a+UM0O% z`k?e#>6_9|q(4Zr?PB?Q+DO-s_LB~ij*(VNr%7i?x0CKBJxF?-^epLR(i^4sN}rUz zD*dtsvzMn0nU8H@bMbc5yani}sEv56NJ4yGG9wj|ZdXe-x>7CL?r7udmTG{B= zr-!RupHjO;eLs(Iwfq=Y%P&*@uD zZx_&ntIQ8D_30P6+Wb$t+WK>? zX!U%6tL59dT7HcD39bXJ>{tG{tIhwqrax#!u`lFvsovO3$3 z>k#`cTA%*9)!Dw@0{`}4%P%r@-_E{4*r)e!we=5>FL$-|Pm#Y)`n2+a1!1{4uD0Ah zt~URR(vMti{hzrO+gEn?3fq0$)aQHC)uzAeI>e68)%K%H@1Vn6ZN7`-JM{_q8PfY* zZTi#F*QFmx2lNf|4|cWv8}DlKm#!Ifva4->nyc;Ke#%c!eu}H@*9ES&Ur$O)*9!ia zwS#^m-LGFbzMD;bJNHYUmcB0S(ch*IHO^dZ`@6W>`Y(~cS<_#Xx7$A>%g#+pSKGGX z9;-L$+#3%5rSTayOGcLMqirV63#B8Zqot+NNzw-COzAe#?WKE4_mdtaJzILM^d{*Y z()*;3NS~6vAbm~xj`Tz6=hAPbKTG`!k^Oj+(pJ*;($%FsrE5ypkrqqWm5!E{Nvou_ z(gx|K(izgZ(go5b(w(JyO81u@Dm_|yqV#m>xzdZJS4yv!-XgtA`hfIt>2p$VC;0h! zNBWWUOX&|%>#W7|uYX4DNCq{mB7lb$QRM0&OKM(G{W z`=yUbpOwBMeOvmW^b6_t(%+;}b~q0$rR}9%rM;y6q=nKE($Ug#=>%z=bh>m)>0IeT z=`!hV(tV|eNRO7DBt27lf%J0eb<$g;cS|3VJ}G@c>g`m&{_jaYk$x@xNtzjj`EsSJ zNjpiqOZ!R(Nk>RGl8%#ZEZsypQ#xO|OuC2kKF3fPq?y+4_Uqn4+Ce&0IyNs%ua|C}AN(@up{;^HQF^(xXMKG)NuRI^ z-u)}mFRi`m{#WS;Ygf82lkR5iMfV3w@3!`z`zNHi*6wrPQCef|H}{)LkLwlu+0vK$ z1pk4wz~=S&2TA8x1H=6i>18&q;r=G+SJu{Y|GRXgHALK3NcSiX{!r7zeV~@Mev!GLDwG_)LsLQ z_hYZ|K@XSSUmg52(w4QsuP&|IIQT~CN%g^>FMZt_Tz-5XOZ!d>zF4}=Cc*D0y=t@I zZq1Dt-5?;J=g(I5+rprQ4k!{O-~lE)4!2=`R-tpLa>n(#wL@ zN)Ngs_~WIIUlsf-(hk=K-%Gm5^})}Tp7pQbFPFY=4Shd9UrPtx8vJ_F#kU8)r}V}< zgTGJu+ugzE-xIX_zMvaR4|yQ?6Qxf+6#Q$_PLBrPN4nYL!EY@+=gHu&l>Yna;J=j) zelGY8q)T52esAf`F9rXAG~?CaTS+Tl558V{*qgzhEPeXz;NOsTc`x`irCWRu{I=5b zJ`Db9=|>+2|Gl*6v*1TdclaXseWka475qcetZ#!~O*-!T;2Wez{22VH(r2xM<=68q zY1iL^Ut79mhCSV}=?kP6WCee%^b;E}_31xKhgb*A{YKKA@`B%AdV7BGk4Upy2j5mY z-UeQM`Ki*Q+68~Q^!X0Kzaw3vbMXD8TUkfYmtQ2ks9W&YOF!!#{Lj*11;Lj{cj+Dc zfzmts2LG5eXYJtIORM__KV5pwz~JwYzAF8<^lR71&helyUn|$%)~}a#Qr=5`P3ZvT z!{yhLZm7IUexkHad82f`bVp6!Rl1k*L*66kAq`yf!7HWOcGU+DL?WG4v&y?OEeN6hU^k-?iqOjin(lOGh z(uLCfrKd@+l|C$eOZtO!H5+j7<6lcUS~^*}t#lvh$08o{qr!4k(mkYCOFxiywE;N4KPE}{ zm7XBISNff_--coSV(Dz@NzzB8ze$TX3iHpFo-BP#nl&a&A0gdFdZzSgX|g2Dx4v{^ z=|0j!rMF3+lqO2Gerc6-H|aIf_ob`bK%}3K-qI=3t)-_)pOC&S?NT0=>m?l~9VgvY zx}WqU>7&x;q`4JgJ)@+x(tV{jNBs0M0$Yq6zP-Fm!zLcdyft4 zTSwX`Jy!aF^e1WIxG;aIv_U#gx|{SG>3h=EtHN>4(yvqQTH%K>^ zTK6!{t=kvteCb}&{iKIVkCeV6wdQKP+~?A-rSbT@?f>uctun)WZKXY>eWX^6#p|(R zI99v8W3}5R)``-MrJGAe2$KKgV}221$#h>r3PDcbi@*KVBM-zgs?4 zzEL_;>d*Uqz1vB5lI|wmUwW`K9*4L2Pmn)DdXDrV>0{F8q%TR|lD;SXQu?jbU%B%A z$(FX1#^ddl$K&j#y_NgBS3dtRX{oeQS|hEKPM5~x?6zDy&TcwS`2o^Hq{m24ke(qu zM|!dJa_RNbo1}M1?~}&k>$bh8_pzh9a$*nimShaJU(p}z;o$IQ&0oIC6E85!f6>W)8*9!Y zTUY#f##UP`p1ng@T}b9Hnwf5AEcVxYw81dPACvi8FPzO9ZI3es&s?-%!EF2UF=<aIem6foc^z~h3h0U8*Vfgx-FJGsxZ-M<|8T*)V*wW05AJPIo?z!B2 z`|XgK@fHW4Hf>k?oW9+oT4ZJTb0OcZ=WO?gv}NpL#_U}(GYb5Je%S6I=F``=SL>|! zoi|@!zWrl;XWM6%v5y)1+xpu02mLVZbo1%!J1T8`Hr$?CpAB_2Ti@}vz7FHGvb1Se z+UNB3on`Cu^XmJzn*C${?y%3k56*-CTzq$C#`M17v;XhY{NKY;=F755W4vYjFy9Ln z_-B5qZN9YKi?{33p0R)F`*%^=@wT^V?BBcg*)G#|Ch^a4w!ZZ-rfkcVd&MU|Y4eS- z1-&g|D8}pa^X}VB!y}`O@qC44{II^Z7NpO2qwU`}%w)=ZiyN2BoZYzH&>=GhFDfi3 zC@5aHXvD~(AtQ&3u+K$B#cBVK7%{A%VC1lMhuS3j*|No+71foQnXJjz*)O$T-&B{e z@ihB-OaJL-?@M&axUNsf@kQ6&{X=%~Ls!>+kqV|Sa zR#x(03lp8}0J0`_ndtLnM}uri;zFORcJ(deDB0d!uKhtvm*hTn#vTK+fmXW=VY&WyRGqMNDb~QU9BYTkS>Sou?$Q~@) z#q7w8>_XYjX4lKeE|TqJw%B&7SiYls+pi(=9o*ZF4V7>2-u7&md^`8HYs2N+y0?8B zA>YQm?cBQZtGTzm8!6w~z3tw5@~zz4{;eh#`T;9sA(xJA074n(x zZT~9e?ONw$XZKA!Vb{OK=T6a@9UOobTN@wQW0RNLXD4Jr^n?{GF(K7jRD?{F6(KdU zBBWMUgiMkZAsfqzkUCirQZFk)Cd-PD23ZK1A`c-`? zLN=F&kS*jPq){G1wv>mE8S)Ual{|#Zl!uU6@(?mx9zy2GL&#it2$?4jAzRBs$Tsp2 zvaNg|q$=^HUH=x3T5*#-J`l2vl~dXClTMBkvR(A0O^gZIUWF2WJSo1vLa+BSrM|ctO(gf7D9HFhmhUmA!K)X2-!m(LiUu0kiFy~WN�*+(8i z_LYZ_{p2BJe|ZQwKpsL4l!uUmc?dZ~9zqV4hmgbMA>?p*2suI?LXMP&kfY=S zAqx}jt;lFG(yE>8MS+mvUY;DCbaI@KRg7siB~phZQMOK8I zDl0-xlNBMS%ZiXQWJSoCvJi5XJcOJr4pQO;&{5E-OOrkQE_!%8HP? zWJSo`vLfUjSrKxtEQH)A4!9q&$Q?B@ZD_%R|UB@(}W@JcK+a4!a zyES*SZwiE*>}AL+Nhik%c_W%?ow}HiH?^n;c}rG=ye%t2-jNj{@5+jh_hd!L`?4bB z16dLBZ&?xYp)7=aBo84U%R|T~@(}W=JcN8E4|)oy#oONY zcs(X0Kk_mpBQxpfWVFoA&d!WZwT^l#@6AM+TDqrsYxd^gdziOoc@p2n@oSj3 zW_cdIn|W)Nx4?HbZ_V<2{OabdS>6)g#k@7kTj4vKw`O^3d?)kXuUU5w!NecC<4=D-Uc>yAZUr zzBkzD^&4Ob={N`w|!+t+VaBTM~B~Ao;mov?MYEMgHr!*=uGd z9WSS-e`fTS4Q0d>4Pbduv<_Yr4aAG0L3mL#7%z$n@uH{*FN%usqG$+S6b;2g(J%ri z8cqO3BM6{qT>>Z?NdQIb5kS%U1W>dA0ThiQfTGa^P_!Wd6m3KRMPmq{sDuEDN(rE- zi~x$t381Kg0E#LJplB=s6pbT*qAG$w(b}1boOVXhc@9oLQPjtg8lRbTzMP^O`<9;$ zqNtYTMbRX@DB2h=it6y9s2(qhCgVj>16~wO!Hc4)cu_PB4@J`nplA~UDB6?&iZ&yF zqRk1QXbS=;Y9xT7EeW7#1_2apMF2%J37}{e0Tj(9fTB4BP&AhSislhO(bfb|v<(3i zZA$<}^9i760Ra>(BnT8$XC|r*ko@b+W=|AFV;!kQnMvo%DO!>lEwJI|xGY-A@}g)N zUKH(s7ezbbMbS=pQM5B&6zzf+MZ4lf(QbHAv^yS(_8@?wJqe&_F9Imqn*fUTA%LQN z37}{{0w~&_0E!MEfT9Blpy(h1C_0z`iVh)wqC*Lw=r95(I-CHCjv#=dBMG4BC;})t zngEK9A%LP|2?9miXC{s@K=Svuo_6+PQRKhukbPWc()n_VPRfj~wFiqaMJKboC^`i% zicZCgqSNrA=ybd&Is-3?&cutNv+$zmY`iEs2MbO&A(-H8`P zci~0R-FQ)S4_*}Aix)-r;YHE?cv18K9*Q0$fTD*8py*)&D0+kdiXJ6^qQ?lJ=y3ul zdV&Coo+N;xrwE|vX#yyEh5(A5C4i#m2%zYB0w{Wc0E%8DfTEWOpy*`+D0+neie4pv zqSpulMYm)odf2o1{CQp$-71QH@=?LpGn3AjQ}lLbw2}R8Qd}0j!}6l&UA!oI4=;+| z$BUv5@S^D7cv18rUKD+V7eycAMbRgCDEgEDiasNNqR$DS=nDcU`jP;Oz9N94uL+>& z8v-c$mH>*rBY>js383f)0x0^C0E&JhfTEuXpy(F@DEgHEihd)2qTdOiC?hM?%MX3D zOads%A_x?{nVFbnfaJemZ_8xAC5nFbvM7<2biSOTWLC7ly($+|l*{s>C=V}+THr-d zK3){H#EYUMePWns67D`bs&JEjs#HDi2#Z^6F^ZH0w`LY z0E)U2Kv6dWC|ZL6inPY}a1q4vkivWsx6F^ZP0x0TB07YvOP!_F407YvP z1d5`p#3cqu{s}&yn3ENH`d@fi)GsUPd^tq}v!X|OiK0O)FNy}^MNuJM6cyn`Q88W= z4Z(||p?Fa=3@?g?<3-U3JQS@<07WASplCe;C|aKYiZ&pCqEQ4;G@1a4HY9+ejR>G< z3;`6C5I|8W0Th)HKv6jX6jcyFQ6&KsjU|AhaRg9QMF2(P37}{K0Tfje1d0Y^CB85~ z@;9>Ab+gwIMG1TCnLRNp>3lgw8)rpr`--AEmKR0!cu_PNFNzxQqG$?U6ivm8qG@9%^`rI zxdc!&j{u6cCV--C2%u9V{sd5T009&oNB~6#5kS$w1W+V6dg$bMMn`p(a{7@bPNF$9ZLX3#}Po$@dQwG0zsf?X;xx410;WAA0k>Niu|?d z>=Uz+&X-ekYF2c5KT&iV%ZsAZ@uKJqyeK*oFN)5>i=wmfqUapFC^{D}iq6A}qVw@k zbO8YrT}S{$7ZE_w#RO1v2>}#cN&rQd5kS%91Wg&QRIKDF8kK3 zr1Rwz-I*1=Ge8vG#qy%)ZoDYE2QP~5#fzf*@S^B`yeN7AFNz+-i=v0{qUd2f6g@%! zMUN6d(PIQq^f&<&JwX6PPZB`UQv^`-GyxPnLjXn35fdGnrB!Hry2%zX^0x0^00E&JkfTG_Bpy+o3 zD6;pE!`r}6lt}MNwP`SfJqVzvCjk@{5I|8c0x0TD07ZQWpr|ha6s<`BMQag2 z(b@!1)Q5`UFt40Ra?^B7maN1W>dg0TgXS z07YX6ps0iZib@HfsEh!L$_b#Tf&hvt37}{!0ThiRfTAh_C>l=yMH2|1sG0zZCK5nV z4FMF@5(J6{B@!QM5T;6m5ZrqDBHJ+L8c@W)MKpRs>KqlK_fl5kS#w0w|h807Y{N zplBWe6m3laMcWWS(Y6FoG@k&977#$uLINmSL;ywG5kS%Q1W>e?0E(6nK+#fyKv7*H zQ83IX%J<@@UKG9I1KGg=zP2=x&SYV zF2swXi||l%F#!}^LI6dV53lgw_avgn>{mnM=VeDEf&2ihd@5qF)H0=vM+L`i%gJekXt;d%rt$ z+o33v0E)5*peR8AMcD*U6cIpC4gnM;37{yKAW-yvA~Dhc$v@T~oqZsRcJyeR67hoUY7P_#M$ z6m=zlqHY9Gv<3kbbtizL9t2R-lK_ee2%xAJ0TlHnfTBJGP}G+Iiq<56qO}O1Xl(*0 z>PG-Y{RyCG009)OLjXks37}{YL7*rYgin_uMeE^3(fW8%v;kfejlx6GXaXqOkN}D{B7mYX z1W;5$07az)P*g?$MdbugR6zhml>|^UmH>*z5kOHD0ThiVfT9TmP*hC-MH302sD=QF zY6+ld5&;x#OaMi71c9QW?8LnWNdCTNvx`O1t6mn>XD6L6r)X++^j?`Ln#S^?XgXdL zZGsm?o8m>$W_VGwIbIZPffq%Mcu}+^UKGv1L(x_QP&AVOie?c&(QE=JnnM6Za|xhm z9sv|>O#nsP5J1tk1W+`e0E!k6K+!@1C|X1SMcWZT(e?yTw3q;jmJmSEQUWMiMgT=S z5J1t61c9Q4>_m%lqi9Qi0y0Gu-Q#7^PT5K4%PHC|J6fkw6z$IPqG%7iDB2S*iuS^b zqP_8=Xdk>N+7~a1_QQ*!{qdsc06Y{ONB~6#5kS$w1W+V z6dg$bMMn`p(a{7@bPNF$9ZLX3#}Po$@dQwG0s$1ANB~7A5kS$&1W_qUbBU zDEb;NioU^%qHpm~^c?{deNO;IKM+9Cj|5Qk69E+cOaMi{5J1td1W@!F0TlgC07V&* zy6sSuNdQGz1W=S9fTC;yD2fQ6D2D)wk_1qcO8`ZA1W?q10E+Sn0!1HYCwfmbimvq< z?ITgt!E3aZQPTNxirPd`S*<8)%krYA9bOc*$BUv4cu~|5FN!+hMNwzGDC&Y2MXTdQ zQCB<^bt8bHH3*=nI{_5+Ab_Ht1W;5!07bnBpr|(i6!js1qP_%Bv?c)*twjJuYZE|G zKLRM~PXI*&2%u;k0w@|t07ZicplC1w6crLcQ4v9)sCAT>XMp4n^7pP+i$YJo)(fWM zDCvATMZ=@$;EhGm2$mN`>*7VxNW3Uo4=;+=$BUv3@SUhAb_HU1W>ey0E)IFfTHaQplC4x6fGfuqNM~-w2T0Xb|8SF z9SNXlCjuzinE;A*AqW&rixS@$Ao=%sQ)s#1I(Y|<5v>#p+?T;5l2jE4~fp}4L5MC4=jEAB_2%zXt0w_9+0E!MLfTAM^py)^f zC_0J&ijF3LqGJf4=vV?MI*tH}jwgVk69}N_L;@%}i2#aDCV-+-2%zXx0w_9-0E$j0 zfTA-9py*73K+*0|VtoT7f0}p8_7Fwids%c=lyttFqVu9?(`lmUe3lnQ7vM$Fg?LeP z5ndEsj2A_h;6>4;cu{m2UKCx97e!a#q3B8iD7uOOimoPrqH74C=vo3Ox{d&ft|x$^ z8wjB2Uj$HeBLNiML;yuM6F|`|1WBaqUQ*p=y?JtdVv6nUL=5`mk6NfWdbOAg#e0P zC4i#W2%zY70w{We0E*rufTFhupy+J^D0+tgiryuFqW1`(=zRhx`hWn6{!IWy9})zL z9*7e68zA|uy)1fA6jgYQ_ED5{zMP`ZqUeLoMA7FgFN(gvi=r>_qUbBUDEb;NioU^% zqHpn{=sUb9`W`Qee!xS~j|5Qk69E+cOaMi{5J1td1W@!F0TlgC07V%&>b65sCIJ*> z5kOIb0E)5+peQ1Mq8tJ!N)kX(E&&wf5kOH30w~HSfTETJP}GV5idqu{iav=FEjKrc z{JCrPr=lp&YqZsJlFpY?)IKK~)F_HNu)HYhh!;hj@S>qNpog6m`Rk zqBZcMs5>5tdJsTSPXZ_^Ab_G?1W?qQ0E+q$Kv7=;C|Z*Miq;~4qO}R2s2>3o^(TO$ z0R&LA4gnMmB!Hqp1W+`X0E!9;ps0udii!!KXb1rm4J8N^warP?86f$OdF#4ePUz_m z_iq2NoTT&R6phS@mdp@E>#@8jS|2ZpHo%LbQFu`_8ZU}A#EYVh@S3~JQU3%fTFDlplBNc zDB6|)islnQ(EI07g-o&btYAb_G1383gC0w_9}0E$i_fTB|gpy)ILC_0@0iq0T_ zqB9Ag=qv&#I-3BB&LIdC?Uj@0JIC8a-k{!F6zv*!*m9E2ms50MPE;{Z6kWvfqUd70 zD7pkMiY~>AqRa52=yJR$x&kkXuEdL?tMH=eYCIHOLjXnB5-o6g`0# zMNi^I(NlO)^fX=+J%blT&*DYVb9hnoJRXW(Ab_G5383gD0w{W!0E%8AfTC9kpy)LM zD0-a$iryfAqBjYk=q&;$dYb@>-XVaZcL|{AJpw3tp8$$JAb_HO6F||21W@!50Tg{q z07ah=1d1NcNnB-sEAAMm2+N4zNd2``F%#zWCB1W@!V0Tlg407btOKv70g-F7I-B!HqU0w_ul zKv6aU6h#D3ltTbTNdhR!C4izl0w`)h07dx(P}GtDidqpsQELJyT8#jT+7LidTY^B* z=Q)Y*43PZqy!iP-6lHpi)-IWJzMP^?$*A)pQPi2`MNt>LC|Vsain`)OQ8&COS_3bN zy5mJr54_37}{ML7=EZGBL^k$*=dG ze#d0!>G$!T{<_Je^W_w6kc>9pUKEXDc~LYPFN!wAi=vJ2qG$|W6qVpbQ7K*&mElEE zIbIZ1;Gw9J0E)&EK+!k?D5@fWqVWV!G=Tt$stKTIA^{ZD5I|8a0TfLlfTE2Fps0=j zis}iVXfgp5H4s426apxkN&rRE2%u;>0TgXQ07aV;1d7&6CiXEv@?STby}l^=K4E6F zWYYO^indHf=PnUNGgw{}ZG{&_Gx4Hm7G4z1#*3mkcu_PLFN)^jMbXxHQM3&ninb+y zqWJ_+w15DL77{?wA_6GdjsS|bCxD{G1W>eu0E(6pK+!S+DB6JligqM`qMZn!XlDW_ z+Jyj$b|rwK-3Xv)cLFHdg8+*5B!Hs52m(c0BohxBAo+)TCDtg4rh4_ZcQWaGIYs*? zqYsyfq61i76di~cMF-(U(ZP68bO>G)9f}u4hv7xh;doJW1YQ&!iHD-22%zX_0w_9$ z0E&(!fTH6Fpy+r4C^~@vicTbeqLT=q=wt#YI)wm=P9=b%(+HsGbOIx3U?Ak zm$JMlx(qLhF2{?aEAXP|O1vn#3NMPT#*3nB@S^BiyePU34@K7#K+z2ZQ1mYXD7ujV zif$r+qMHez=oSJfx|INmZXqK63rMHeL#lMRskL0*YnEQ*fwvgnay()n_Vo=8T^b`eESvb-pI z3NMPD#*3n7@S^BhyeN7OFN&VWi=r3sqUc4uD0&GGMK2RT(JKT{^eO=qy+!~8T6#ax3ML*+3(Jy#W^ebKz{f394-wB{7BUjyaD9R*&qAUU^N)SL%HUShx z1W=Si07XdxD9R;(qC5g9YC!-+`2wV3?Fs;S`;mEq&ns%oiC?o_1q|PPf^sBlTjMe7hi(Le$y z8bkm^g9)IhkN}E`2%xB#0E&hXK+#YFC>llpMZ*c8XaoTitxEt!BMG2rJ%T_{=iJ0v z21x$Z{sg2;Zs_Sx^crpb+@$m66m6Irjon)mZN&1TXbfHymEc8DDP9zn;YCq7UKCZ} zMNuVQ6ph7;qH%aAsv>}*@dQvbfdGoC37}{q0Tk5`Kv69L6ip(4qKyflsEz=N>ItA| zG657d5J1rs0w|hF07cUXplCV)6m3EPMVk^p(Pjitv^fD3Z9xzy8kL)vZ-C@4ad1Y9 zqBp!OYRpYKUry1?-01LqMbRvl7e%x2qG%3Y6wSqpqIq~xv^8E7ZG#s@+u}vhe7q=H zfQO=m1W>ey0E)IFfTHaQplC4x6fGfuqNM~-w2T0Xb|8SF9SNXlCjuzinE;A*A%LP? z37}{<0w~&@0E+e?fTBGKplB}wDB7CNd!=IG658wLI6dl5j37{SX>MXe10=u3Z1!cMXtvjAkLMG=Kn#)**nRfdo)AhyaQP z6F^ZR0TdMxKv6LP6b&JOqM-y(G>ia>h7&;12m&ZtmjH@J5d-0TgXO07at+ z0!3Z(5^at&iZ0DDaJuD%p8gwdM&~7+FQ=#^FDgD-6qT~PC@RB?qH??_s=$k)O1vl< zix)-X@S>;+FN((FMbQL26jc*I(L@3$sv&@)S^_AVL;yt_6F^ZN0Tk5}K+$9ZC~6>p zqA3JWG?f5~rV&8VbOI>agaC>*C4i#M2%uQM3RriWcHU z(IUJk+71sz+Y><1Vge{yLI6ce37}{h0Tk^(07W|zK+#SFP_#1v6zxI)MY|F}(QX7# zv^xP5?Lh!VdlEp=UIb9IHvtswLjXnl5d;0TdlT5Gb0JmpIJ;$sg#&&ume& zroU`-U|!Psa*7Vki*7q!6dlI$qUdnEC^`Z!ijKsKqNDJl=xDqsItDL_j>U_jV6KmbJ-5|Tq16~yU3onXp#EYVv@S^BuJQUqR z07bVFK+$akP;@&16x~4pMRyWF(Om>kbT8s z$kRm8&nz#Be!+{PU-6>oH@qnN9WRP9TBzqPiZbz{C<`x&5_nORjfbL$0E%)5peRWI zMY#k}lt%zXEeN0}p8$$l5lTjMe7hi(Le$y8bkm^g9)Ih zkN}E`2%xB#0E&hXK+#YFC>llpMZ*c8XaoTitxEt!BMG2rJpw3Np8$$BAb_G#1W+`Z z0E#vwfTE2E0!7_hBz`hL@-zKUIreA~dirm9Sv00a()n_V%3DO;&K5-#EH8>G@uFxf zUKEYPi=ryLC>oC!MHBF%s2VSdCgMd=4IYYW37}{a0TgXa07Z2KP*hIv_)c!0g~^3sVKWl6kY6Qc8jF*e0kWALKrSiC4Y4ljz1 z$BUv9@S^BMyeK*e4@D;vK+!1#P;@E*6rDx@MW+)$(HR6#bS425okajeXA?ltIRsF2 zE&&vsM*v0V6F|`g1W)NqW_P$`;LyP zZu_>sclK=dz@*G1KvsBt(~2aP|t2&?xhT#@kd; ziup|c=?b3lWfVPM!Ts$~RrCUvS4CUds^~?wD%!?YMcdh`=q0u)dYP??USX@ESJ|rQ zH8zS~C!pvJ0*ZDJP_&bPqFn?O?IxgT4*^AQ5>WIO0Yz^UQ1lJ~Meh<&^d134?-Nk8 zmw=)V2q^lHfTE8GDB4Fr(Z>W7eL_IdrvzWovlX1g&7$aU1LrwabkLC6U%@lJjH1sg zxGf%6MTfY&Dmu(oMPIO0(U)vh^c7nbea%)y->_BD5we zihd%X=w||oej%XfC;>&s2q^lMfTH6B6#Yg((eDHlogkp-BmqUI2q-#DK+zcjip~;H z^alY&=LjhJlYpXPg0JX61!trH35_!!#15*Wx#q*$Ully#%P9J%f;;C)RrD{HS49`u zs>llIXYQ)VW~-tYwkmSiswlu#MJ`(vm1CybKv6XUimDS(RD*z`ngn0b z`3lYk0TTMuyf3<-itd(|1!{#n_cO5m1y(K+#wN zigE}j8b?6Ucmj$h5Kxp$K+!}3iY5_!MLk1K69E#cYrX^0OBLNJFAL;_JmbqKni6vR zKd*|Wa(PuWjjf9E*{Z03t%|0zRnZK#Dk@~Fq9V2`n#op0v)CxQmVlz!1Qg97plB`u zMb{BfG>?Fy>j@~jfqBA)sg}0Yx_vP_&GIqMHdQ zx`lwETL~yyPVg079dZf;NNBG4HvToL=p*xv>9&w(d>KWnLhh=qs^|_buZmW)RneVn zRdg3y72VBNMfb2((HgcYTFX{N_p(*dIyQ>d6Hs&?0Yw`KD7v43qKyO;JwQOwg9H?9 zBB1CY0*W3cpy&|-iXJ7PXfpvtj}cJxH~~dZ5K#0a0YzH~D0+&3qNfQcdWL|aX9>Qd z6(Q$E0TMcG{$*js^}ZGDmubeMc=Yj(RXZB^gUY@{lHd5 zKeAEu69Gj(6HxRE0Yyg%C^|+!(XRv)9VejZHv)=&C!pvA0YxVXC^|(z(P;vT&Ja*^ zmVlx^2q-#7K+&HB6crOt^cMj|e-lu2p5QAw6mq%=kkEPaC8EQsXo4YiA>C6s;B}RMIi!;VhJdUBcLdr zfT9EfioygGMF=QLB%mmXfTD^76jdUis4@XX$pjQtA)u%#0Y%jaD5_3CQ4Io$Y7$UX zi-4lq1QewZd`16;oMi$e)X)5j*^8>Exx6e;C)P8*jG_jy?qjd3qJ~^v6P$dU7Xpg12q@}GKv6dWin@~Mg3yk6FXE&@~UV$TNTYff@u4SvD*=$ubhmE4S z1QcCIK+!w`imoT1=mr9c<`Yn~fPkWf1Qgv!K+z%siWU=4w1j}7r34h+L_pCp0*Y=X zpy(C?if$#KXgL8zw-HcuI{`&22)?4JvCe1#5_-%$p`NCSUNK{3tY>@~MR&%!*S)EV z?&9*Q=x(+ux`(Zb*05F4TDB^>m#vD{u~pG}wko=ht%^3VQFK26MH>kydVqkU2MH+J zL_pC)1Qb0?K+z)v6g^5n(PjdQ9wVUWaRQ2-AfV_;0*bZ}Q1lc5MNbn@^b7$-&k|7d z905ho6HxR5!B=!gtg}&ogswARbzH5A{xxH3tY>@~MK8s=JKt7CFLQZS^a@)Qy~ugo@23r;FV5_2?Y*n<2t%`QDQM8AEqBjXBdW(Rfw+SeEhk&AY2`GAxfTH&a zDB4Rv(FX(+eMmsjM+6k@BcSMG0*XE%py*QqiuMyw^cev~2M8!SNI=o&1QZ=2_=>j0 zIzI`J&|T);&vsQ*OI{W@9P1fhM$y;u|FeEi6@A0yRnZZ)D*BeKioRp3qVL(N=m)kc z`jM@QeqyVlpV_MD7dDEH5>RxEfTCXsC^}9+(QgD4{Z2s92?B~v5>RxCfTGg`6rCZU z=qv$6e-Kb~j)0;+2`DNipy)3GivA{`=sW>M7YHc&hk&Ag3BIB)W1VIKBvi?K)$uD; zG|GIYe=*iGzKkL#&KVf`Foy1QfL*pr|zg zMQsQuYD+*-I|7Q@6HwHFfTE5B6m=q?s51dYT?i=3BA}=%0Y%*iDC$l?Q4a!&dJ<67 zi-4lu1Qhil_=+0FIokzDsIh@_i7F~EAKv=LdB&GfG%(IRv`-Zc;_|9!Fk2N3VXLB{ zY*jRjt%`=TRnZ8xD!P=diY{ZTqRZJR8c9IWC<2N`6Hs&o0Yzg7D7un>qN@lf$|j&_ zECEG11Qd-UplCb+MH2`p$|ay^A^}B{2q?-UplC7yMOPD0bPWMTQwS)UO7Io+k8}PN zAfZRh`=SA=$b6Y7FfGnAzKo(7ac=ETRZ$_AS4Bl^RWy^Wie|A@(Y0(j5m0mo!B8AbQRxw)UIqBUGz6|H5fqI=n@XdPP>t!JyE``D^z16vi{&sIen*{bLPHi{l3 zplA~TMGp~B^e_QMj}TDwC;>&A2`GAufTG6 zK+$sq6g^Ks(F+6=Z6%=SMFNVp5qw2=#W}YKkkEVPtB!Z8qF>Et`rG3?Q1mGQMf(XT`iy|00|XQuB%tVX0*Ve1 zP;{7pqAv(2`jX%)dO6P7CqP0i&A+>TMHN*s-vRk5&NIG@qHp8eQ-@U1cU)c-ea}`! zKd@ENk8D-+6I&Ji%vMFeuvO7fwkkTtRz<(EQFNSuqTdK8`kjEH69g2UB%tUN0Y#?? zC^|zx(OCkD{ve>}905gt5>Ql3K+#_W6#Y#=(Rl)jE)Y=k4*^C05>RxJfFdhiKQTv< zP4E?c6X#SuEQ($yUKv7)+is}(iRG)yN1_Tr}B>0K~@y-|l5(*hOZoL1Q zzC6>GPuSu;P0|NZvu+?5Kz>YfTDf`6!j6ip$ZXet3k z(+DWaC!nZ+;42yw@BAV_LRseDT@O}8i_Np^>G7WNWfaYfcgugTie_rbPEARw-QjaoPeU+2q?OpfT9%y6s;tnXcYlPcMwptnt-A^2`IXY;43PO zchUq%=y~(Ls7MvXnP=B`$9u+?QFL#-JNQRcw2sTGqV;T5bRSz4ZD6aS``M~!BU=?c zz*a>MvQ^P0wkmpvjiQGMD0+l|qDKiR+Dt&vV+0gEPC(HU1Qb02%=xG9q zo*|&z9yjP8-lOswRq=c0TPOw$K76CR6A37qL_kp<0Y#GuD7u<}qH72!nnFO)R04{o z5m1y*Kv4k!Mbil=nn6HOA;DKPG{N~qfQ0hQ*RF@DqB`b%QBi_td>KWv6WlYWRnZ(S zuZrffRnc{9RWy&Simqp?q8r$%Xg*sNEnusng=|%HBO67F2q;=iK+zHcik1>kbQ1wZ z%LpjCnSi2O2q?OhfTHCD6x~KZ(d`5jtstOiB>_dN2q?OPfTGm|6x~Tc(Om=--AzEz zJp>f3A^3`BB{)^ih@xZW3ys&Rq6+5I{)!ZMnKWy1Qb0%K+%%~6m21(=qUn(YgfZ zDghE|Y2FvDS4Fp*4{xt0c*d7ev@5}#|EDV2&E-|m9=0laldX#0VymLJ*{bLrwkmp; zt%}}btD^VWs%S48MIR7Q^dSL79}!TrkAR|&2`Ku6fTB+cDB4dz(Psn{9U!3SAOS_6 z6Hs)BfTF_$6n#NJ(U$}ieMLag*8~)OLqO3H0*byRpy)e-uV_bt^N;`uZ8D#h?Nmi8 z&HJM76FlR~DEc|Uee*9>^b40)MMv4H=oniS{mNEF$JwgrH?}JJovn&auvO7XwkkTs zM$u^kip~&Fbe4dkKL{u~M?le^1QZn$Q1ll8MSl}ebe@2s3j`GXLqO5L1QcB)pvVgA zr|l@R2`GvopvWPhC_q4wOF&UM0*X9>ujt1F=a>KqZ8rZhs3KbxRbs26%4`%R6HruzfTF4d6jdXj zs5${fH3%rGNkCC80*Y!AP?SPIQ5^z`>Jm^?kAR~31QazOpr|1MMVAmz)QEth#sm~K zA)u%!0Y%LSzM=|YCqsaQj+YlWp|Jm%{u}1QTWZ)dzKo*Gusif$Rn(lztD+WcRn(HL zidwN%QERp;YQt7VZP}`*9a|N(XRD$PY!r1Qpr{i8MV$#K>Ow$K76CplApIMMDX`qV%vc zOMrw%nfFB*s_3E_!@{2NWfWZ&cJHyw6=Ya}%elNN8p&2gqu8owG+Py2!B$0M*sADC zwko=ct%|bQs%R`5ML7f%jU%9FJOM=$2q?-WplBiiMUx09$|Im?G66+b6Hs&w0Yy^? zD4I$@(KG^z@(Cy^AfRYE0Yx(iC@LhNsEB}~nFJKgBKV3%gq>FfNNA7w*4d@1D9(JQ ze{I+^zKo*l!tPfws%RdUS4G#eRnZM>RWzTiiWaa{(L%N=x{)Vzw$;!bZ_j z0*Y=TplBHZMK=>rbPEARw-QjaoPeU+2q?OpfT9%y6s;tnXcYlPcMwptnt-A^2`IXY zfTFtzD7uG$qBR5*ttFu7UIL2N5qw2+!cL4Mii*q^8t1B_v*vx#`mkqw8AThzZaw+W zK}6pdJ;3Ev(SvMNw27^X9%8GahuNy=5w-fTE8HDEfqeqE87Z+D|~yX9N@- zAfV_V0Y#q^P;`iZqQe9feL+Ccmjo1jML^Nl1QdNkK+zEbioPYF=sN<6z9*pQ2Lg(I zB>0MUhn?F6NT{=UU$jRRZ8FcUe+qlXmr-;q>^@yy75&QPRnc*_D*BDBihgISq7!UY zbds%#PO(+dX|^gl!&XIS*(myhfTD8*6#Yp+Q858Ue-TjhHvvWG2`IWiK+!)06#Yv; z(M1A^tcZTvjv||Yq8I{-90H001QfXh6qO^O$RnUANI+3}0*WdSd_}*6o&5qNlrJ-I zR2Ai$&-6nP&-gNm5+d#&AypLS@~SApRz-Q384=I;GKyM8 z+z#=os1=u2MXlMYs0~{cwPmZKc5GGDo~?>HuvJkHCZK2t0YyUz zC>lmU(QpEaMi6{O%_GiO0TOCzK1XYziWZt@*Ox{-%4aRncfJuZpfdG6IIcCF0YCfuvO7Qwko=jt%?@0RncO$Dq6x; zMN8SL=q9!*TE<4v%>)$PLO{{21QabNpy)ONif$*MXaxa9D+wrCML^LV1Qe|%py*Bl zitZwy=xzdv?jfLP4FN@K2`IXkfTDE-6s;$q=sp69HV}M8^CHf10TNnn-u+y!ijJCb zf5bDsjG|2uH?EQ@dWg%bqKDb4=n=LmdX%k-HnUaHV{BFQI9nAx!B$02vQ^O*Hj17i zpy+7=ik=~$=ve}ao+F^>c>;=FAfRX~0YxtoP_&JJqU{6}y+lCK%LEj?LO{{01QfkS zK+)?26um(}(GCKNb`nsui-4lt1Ygku5vRET2@Ns-djCOH^oRL&$exI2d>KXWMBL%Y zs_0!VuZrGdtD^VWs%S4;6@9=~MIW+N(MN1mw2!TdK4z<;PuM8>lz^iB1QdNnK+ypL ziVhM`^f>`VhX^P-OhC~W1QdNqK+#tO6n#xV(KiGX9U-9TTLOx{BcSMe0*Zbhpy)>e zihd%X=w||oej)gZ-ikQ01xP4het76@RrI&KEO0d98DB=xZxMHGRaNvmmsdq6*sACx zTNRyRtD@6vRdj}}iq5iC(I0G8bdIfx{$!)5n1G_c2q^lSfTHsR6kQ;o=pO=#{w1L3 zA^}BKqJG+rBAbAs7y^nM0*V3z6uATxl_Q|YBcLcqKv8)DiYgFL6e6G~mVlx-g0JY; zi1WGt3AHxwi;k_{Je4=N38AXYS?l;v{Q4*I|MHShqs1jQhRc5QAWVR}*!d699 z*{Y}-TNPDjtD+ig6xAf4s1^Z5wFxLnA)u%Z0Y!BQD5^(5QGEi68W2#_kbt5~2qS*zKv6mYMHvJXWfD--oZu@8Cpv)|qUbsEggTPwf2O}g z@B~^Udd8Pg)F#nwP)ilHkMOkcB)Rm2* zZUhu{C!nYY0YyCtDC$K(QEvi@`Vdgmmw=*v1QhirplARAMFR;a8bmJU5KuIf zfTCdp6b&b!XaoU8ml9BP839F?6MRLj5}kemB-GTvX|0N`G4G2;CVIw~Q8Xsey+;0z z#L@4gUCHHD(N%0!l+9K}W7(=Ghpmdnu~pG{wkn#yRzG^MI?-7vKtgYs&-AZQMNgX#Z`UV!#+OmFFwuRst}42b%d4VAY*nw2^?K2ME5R z`H9W}0TTL2W?+FTI$_3xiJtLgC0H?mdgbdhw5{+K`IfB}j{ZOR!l&drw!v_cd^Q&w zZYAG@3x_X{v#g5YbqSVLCH!r~vTB4csc2a#;i;7^tA6v+hP$@5tTEx6+FI7w@CWTJYeG1wlV#; z_pz*b;cfjaYeD#*0hYBm+mV2vK|T-=2+I|@Jr(@>&fuNT+4bU+%wOzUI^cMwPkG&e>}yqUJWPbTh@;7 zmD4S2Pk2+IWxW$VI@7ZDhSTMLiLoy{bFO9W55F?cvOW*n^DXPkaPNhdbtHV-BFp+A z{OJ`32xoX-CX|TYrolG5>M&v3A7#*R3bm5%ZrX&a)%tzb`w* zj+p;IXn`Fu|AogQJ7WG5eY5R|`ERVvvm@p|lC{8&nE%SrVmq??h&)1e#Qb+gmfI2Y zABtFMN6b(9-)Tq8k7}>6Bj#sq*V_^E!;%~Ai1}%^hwO;?aiz_6#QeO;lXk@Xz`!$h z#Qclz7wm}nC%fD2i1{~{ui6pwkLGsR5%aH}_Sg~g&sN^CBj(>7?6o828^`NcNTUJbc`7dO3mSkB@Wy^_gALL&JnNlu6&TCG1 zNp>jYpVO8ZjI*2|7Yv2sLb0K?a(9$Z{*QB2kaLx}`jAf7e{HdPl`_p$#_3f?Us`&V z@p_edt^~P|TY5XfadI=wYmP)u$XlJLZ<4-}q%^xrRc^#3RU>v{xvVPpbgOD!V@0>j z&5KFi)=lo5N-h7pRW93V$SX^}`9@pr*t@z_&6KODa?6dj6;owZw<>byr&(R9cC0!r zKKd%>>B-%SsLgp=}K{2hKFKWPcO>P zpE5o#XY#bd^hx8#XXnhAnx2`F-6FerM)S<<%nTD#C8kcxpO%}Nn=@{5YGy`Si&XRC zGEqjE#Et7^!nOT@UtZVCmt^PM2rdc^fx#r%o zEPbF`G|x#JZyaP#$eoxob4pQm(VT+Z!n8cYOCGBUlcyEQ5I)1Z_so{tIKF%S)T#N? zq{%y6v`jYF>nBS-F1S&eP7B+0lm4e)Zc;hhwVg?6Zjw_q#dXW2yOrep62mEOd3hFP zmuu;oXH#~9+aNk^f2KuW8dI)$G{?vVTzPSfGbhDOHYYC8m#3G!yjk?+v(x;SxBjn} z` z9oMZLWB#fQ>)AWIS4JPp95dTy^vNFQpKRT-)Bn; zlPPDOJRm>6Ak!Myb!2w;K_i;`*WH7Qv?_UhZAdLjUvKl0*W10!Rq73F&IMYRoU2{* zHqD$?IC;{v+zBayBl_yP>+Qa}$%y#~1lSTJk!2l-?O~7w8$~ zCi{1zT#J9A%uQ&+Mdi+mzEJL1yvb_7OLYWZuSr+WOyC9Ns>(H9+- zrBlb6yf@86k9o1VA~}}aZC!HVJ$`DB+~{+& zOA98*$KI}8dkmlHe^}u$mG^LZb6b?$xpEh2%PdvF1J2`J@))<3dp5s>wBXUp@=?gV z@6sff;fjT)f9J}pjh>MEh?kXKMf4^a1|#I@hMu1b$|Dsm=HZWiaPvQ=^(?uxJT`ib zrMG}bU+z17S;?a;503vDO4Z1F7&%w;%A+rmM_n%^A9M6n$r~af{maX{ZA+fB&hYP* zO#h%Ca7&$JmO?49S?WVRmdo`Q=H<^QD*5oqUwUIN%ArI;$p?D*I~2VQ<}r!dl6%8H zp*YNQi_(WYv-B|+ExbiMBAIeyqZgKE0?{M)c&5nqueHnrTKf3OE7$ubQ=Yr{XOzFW zdZOem%oIs_zB2E&GxZYksFvQra;o>BOH;bHYnNi4-lt`zm?!udZJW1DX*45uN^VYJ zZsU~HspAV~b{a4DSnll9sV!PaD9W2Tb(|b0PRY+HN|nzJI?2N_!2~(y#DZC^QVR=G zCuFvkk~3p`UMKl7Wpj8e7r2NCw8OPS^A{WXfzZ`pF5U5W6bn{N2SQSYQ0&dkC3mt@M&EMtv{av|M&CmJZ(Ye-&EK*T%TP8?Pp>I?$H%kK z(r1dLPZTpt-z(y~ zX=MKDbe%CZrRUUfxf3SH^YIaUQXT!<#3##*|L4D3@-={1`F&A-$rm@~#mB~3^5u<^ zU*<~)-Q$CcW0u$x-`o>#b!{gh$9y(!+39l9ZJRnUZD7~FgRF89Z(w<+LNGB<(XM1C zJ5}teb~U@YUBj*wQ`b)Ozo1caz2-#O6tGTREc-&|KVE9Sbm4!ogY!7%6Vfuj9QkBa zzRp$VSHOzM8d*~K>YyJSEBb}Rl9xJ`d@ZcZFUOLv)R+0?SY^M$V{VUp^}ft6N51Y~ z_LmcV?WM)BU)Bay7%`cP+U&<{pTVH`6@+F>>db`^y|F>9MLg$_wk5qrAC|w42A>oKL=| z5IxFw5~9a$dK{w1OZ6yUYly!5YCTTZ<9t0X*5gV&Zqnm6dC1M{*{#Pz@(`N+qaM%8 z8(_94UwAdgn)0@oV`Dvbk%!Fe{(8)jx54bGdVEA4GP9r8<8iqI%>GM{&E)|xyNe!Y zSN8W3J-#k~QOwKV*JGf%zax6=C*QU)FTY%mD{K4vK0O|gJJ!7Xdp*{u@9)NX9M{m_ z`Fh+e4}dxURz3dS#NX%j*fQ1MUG+Fu9w>AEoAkIN)88NHv0O`kC+Ts3JfP=9)~UT zceWnaEb{lmdi;8czkk(Z{bl~n)Z^8+`1@KtKC|54uj%pJ?f!OF_{WZ`{9|7|-niP| zEA;rzUH<+|kMV2#U0shO?)7($9`9Z6???4`WP`td(__O2{M|y2Q#Sc~jvk+T*xzsH zvG`GcyPN%E=g0kHe?2aK(%-A}_})|gKB&j=v;MBB$IG7g_jo<7-|Fwj^!VL2f1l7} zqnG{NN{`cC_4jppeBpI}@6_YpJN)hK^p9D){o_DAE`8JAtM$0|ZGRuqW8!=MuC2$B zd;OiO#|c%M{iDAp>2c%F{@$X;pN{(bj2@dE_jfxz&iLKm^Yys> zq`%+PK%CzwgoGKKY)iIsaFBtbD=W_4GLAUw=>5~Hi~MZSM)b^|?LCEv(3`x-qyB;V0B`&m66lW*;s{ihx?v5ePH|ue$9(U>SBRzhp$D?{Yr$z=rKu; zjrAxWzN6=p56jVGTRjfaqj~;ju79*1uhL^VbCfF&>y|_Ge7xQQ^E^r}Cr@Xr7G2={#E%!zEN0q=FG^MHYrzMnSYM|E>q06`Scp))>>)f<=axZ z^6iK+uXW;#oT+lAuEPeVZTzs%!lel?Td<>hyl{5HR;bhM+_Us+C@ z^O)b}^<62yxeapC+9%B!za~U~leI?hIVovBUUba+r+3Pzg z*Ju7tnCmm2#c_T2$!RVlC#`?v`po(G#mm-8D0_WYuhQ#_lb3OQPs?d8W3D5viEUla zgI(rjPsr)A*B6%SGmn$Gedc`v*Y}E?HrHo7m|wS~+SagG|Frqjyv+Q5OOKrI%XW73 z-?vDP{^ES{Vfa68U!(SR)R3Mn`g+ajkK}jR+gGK`+iTuear=(QX?gPspJSBde;sH%&cSJb3Wg7iK*^;E92IiUT=buRX;_hE(nq z*K2=qppMn#{NZYOdy1_(5BB?{I1sTKpFey>-hz}}#a3qj(+h_0Dn6buzn=NC|LKj< zm4EW0Gx%(kh-rEC?inD*tcOk=pHQcxIkl_!i1l&KuHr!Es{Xgj%Z_BoYss{lo%J*oysLWN(tdI)GMDyW+INp!v;1Blw{zu@ z969xj{5~STclgCR^+c9)>hA8=AKOwkoxY;Gb$ZK?i+}!maZhoLjeCmsE&P7+6*1PS zrxtcUUB0_qDr4~3(Jd0{`llK?`F#ue$my{BPMIdJ>&VJ!{l3qc*8e}RVWeC`@q)o; zpDP^G&%8Bq-$dVvp65bNW}e(Tk%GK&edTD6=p%1sIBBetx52)!fAHBI!-w?Uozp*m zjI;a9f~>!#Jac)sb4kwSgGLVM+wY^CK9hD9?-{$Z_()c0Y*OA@|1y`SH0*PFYf-n; zNkfA5vicsBdvM>_UB!E{!efU|3gzAFpKC>_? z(Y&oYE^pAkVV@H@4f{3h`=-2|=3bRY+4(i+&EkDIzfLyy>%Ijk{p<9r)38vh4*GSMTngb+gs>?Yif-Sj(+o zhx?8n|Ni{w54!zrJ@f6AnJ>$E7rMcKwZIB2w5`Ppjy1J9cIjv(xF_6wV`3;z`Z}X<$i6qX2ij>pB)GuYnswB>vT>F`8$%Cb#93> zSUf(I!Tpj_Uml<7y-z14wKeyKJv;j6_UNC*(Ld!86a9NcLf3vJk88;z)~RoY!TaS= z}3 z*FY5SDKO^}%_;T9hR`r1ORUuF_fAg#vBUGStqY%hB7eg|YwPw2jWwtGNB_Ll{8^_~ z|M$k$>Q}3;c|;cdRI|T1U0WZYIDLE$$>URffd2?p>tC&3^}f|h9>G1)NAOEIN3x#7 zJcj16IHHe5#cBmBW*+|d&)-H>*|nlm%u4f^ymi}}b@SgiaokO~vfc8#H~n#RbH^)Q zazwUia^h>s1_QHwf)2Eq#g|<1}){hGTJ6AsT#6Dr3 zIGXp|Wq!rj9337Y9z&tq_=pUct$=G2&)_8VB`9R=xm5&uM66HePvr+=yPPw73_o;mRDCaqH zYdvqNTz$}6DZRXxAm^{($zL5SgJEPsZ*W^&Gm z_j3*T5auDxBIl{-{V2}}DtY_mJe9p&@(eQBJ1=)Y6|bC}uIfE2ALFZe56kK5 z-fFoQYk2c&%NJw4267u}dwjdi?FYFbuZ?}A)gJ?|emXMJzFd}`6aTV7B8 zk+9cFt~1xGSYQ6lwAWv5!@J(ka+}}tD#_FP_q}~`+xB`l%G>*aw?@wSVX%grZe|B} z%FRl(gRA6RX?AdfeDF=TgVp8MWZ1zI@-VElgJa|#Uu6fclbf>I4x0au;hlEy3AwxO zvV-QIyWVXFpO?Gs9y|DqT+13e_@TVo@Vwl-b#}0lyj5rIU|7~4cCcZ< zvd-DT2j#W@X$KSJ0>yUlWw~J^V}cXp6}=i0tR%PP7bp0X+=!!2aIHK|JLUu*mh1f0 z3Dy>O$DQCZxnF*Bg3rpG@w*e;B=^P%CwR4}Iq3u)c@3wWU?X|80|LP=@@fYLf^Fnh z4+;ctkVk)TAlOc>Y)ByZy_{ueAebhvZ&)BWKn}wL!LIW9M#%qOMlNt^AUIr%UKR*i z@(5fW2sRL4BLl(B;&N0VxJ9mPbRgJC9+xWu!IAQ?jR^$nh@EEw!6La472V(+@)lKc zgU`r~nC%7!%Dptl4UUv6o9hPellY~)uau`dU%A0c4R(;L{>Ba7EVt!|8{8!~ z@LM-HR_>+m+~9P%E&IIS$8ye(z2H8%_$OYlt-RV#z2G@{$oG4}ujD3u<^|uDd*Xl> z+$-^*7yMV=qR+kHyK?bEUT}-t-0h)YFA@DxD0q)t*~_8eHhB%Ngo5*g?Z$+lEs7pU z2=12~|6oFJsNAGY3BiCo91kS~Ysqy!oDke5*ZD|7aJsBzNx>9(G;dA{z9ttBUlKel zZ&Bou;ADAg3zCC3$!(dQ9PA*sY({c0TV8Epa`10CXHjzS5xKKwCI`pKn>i~vSXW-d zwaLL7MeOY4;N5Z$&Pfgq60LKSgU93{zAib~S#IaN5)%uPgTKp-$XXwqAg{LT`rrY%vTo~x5xFfr)(5wzSXR&V!34QOdaV!2 zzf!k)uMZBDdt%7$;Air(p}T|KuldZujRJfWKR4pZ|JIQIWbI5++j|1mRq~poH!wG*`4OZFY&$%&jh8MIJu+GK^Ke zpWOHubE1X33iEBm@>j~=qJTLeZ=bvsa^iM*rRB_tE%J7mbCthNwAtpwbh*Q0%!%r9 zGtA|z3OCCY1*X}~M%nVAZ=bxTP+*0O*nr#6O_j&q{1l>liT<>>|KnqBBc1+FkGYL? z`aeA8Hqq(-?3mkBr~jj4ZZn-2wY%+1iLKQ-oN>ee3` zbDQhdpBZyo=+++@b6e`xpBQsn>DC_@b6e}ypBHo6=+++>bKC0HpB8i5>DC_>bKC3I zpA~aE=+++UD>DC_r*b?Xm_x!rW@&xpC* zb?c9axjl62Pl&lab?Xm^xxIAD;~yVz>pO$x@lRMMeB1`npLb4JD}Sxs-d?Kw#WzCw zyMu*PRLB6ms0taVQ-uuDsX_+pR3Srjs*s^NRmd=%DrC4$6*5An3b|A#LN3#dkjr%= zWTb9{jM9ye(Yg_Gg>Hn5(T$KRbtB{|-3ZCnjgYar5t5@DA>(u-WV~*KOwf&xT-^wn zs2d@ZbR#5BH$o=sM#$B=5ps=gUr1layh}-VR^DT|{d^%E<$bw3#WQk@kOFtQ@QDhU zt`}7yGjytuLY*q4NT&*!sZ)i_(y2nO)u}>e>r^3gbgGcKIuUZ6ZiLL!jgaegBjg6% z2$`=NAq#XPWT9?^+^8ENi*zGov2KJc(T$L$x)E}dZiFn;jgXslBjgs{2)R`^LYC`B z$Zfh2a=UJXtk8{+mAZW))11}v_$Ta@XF6`aFXXrpvdS}ZjF7wB)$-vsD&%gxs0z79 zrwUo4Q-!S6sY346sY2H2R3Ynis*wA1s*nvjRmlB15wcM?LLShKkOy@mWRq@$Jfs^T z59>zABf1gtsBVO8){T(IbR*<(-3WO?H$tA&jgT$65%QF7ggmVqAqf{sx)JiOZiKw2 z8zJxOM#x^>2>C!aLO#@ukdJgDWS?$?e5@NGpXf%&r@9fcUpGQN(~Xb=x)E|vH$pzw zjgUjS5pr0!FJ!xOP#*t;-{lFr`;sr@7x@&#{lYVHjF4~KgYtPoRLBv%s0#U3rwaK_ zrwaLArwaK&rwaK|rwaK=rwaL5rwaK+rwTc$6CuZRBji`z2sy4BA;0NH$nUxlazZyk zPU=R;DcuM;ts5a{bR*=fZiM`y8zJX(Bjiur2r1T$kiT>zh^_v<@_y=f5Ke(B*^_bDkOZPIW1o`Gjyy-zzx`Lb@?EaXg-^9ZM}4D*_oF7 zn4a!hvYX47)Yvs;x3JtGyN2wRmRp`(U3M$Wt-!7(yS3$p*i~h>vD{d871?bqH;$bw zyPf66vn$KalpB~psAPiN!Z4wt333x7gd`K>HYO4hO^_RzM2MImx3VH3Y=Yd(N`wRx zDG?@@*g51(7gjfm9<(5_@giMfIT8&V_1i7Wv3FS?YTUvt1Hwa!czHVkESXTUw7GKa1b3h1}Bm1Obv1 zaARyIOMry0HJ{=*wy&t2d}+aLV0(s_QPkLWbL3r5R8bQyuZo(oRZ%mxDoSOmqBOQD zN@uI047MuDWUHd)Y*o~PjiQzW6tyCts5JpaZ3rl8OF&UO0*cxbP}G5dqK*UP|pW4+4sM5>V8OfTG?66!jsXs4u}+bcyXO6(HfB=8H;= zRM8sws*2ms_KYv1XprqbDzKu826K5;G=!~+hO$-BFt#ch&Q?Vu*sADKwko=et%@#Z ztD=!?6pbRFXfy#uR}fG%hJd0g2`IXXfTC;yipCO9ltVz#I0A~s6HqjPfTCOiiY5|J zG>L$sJOYX)6Hs(D0Y%pkP&9>rqNxNFO(Xb<2H4JC0TNy4bJ(hAE?X5{$5uu2*sADyHi~W_plCh; zMGFWhT1Y_AjRX`eBA{q70Yys)C|XKD(M<#tEhC`lW&(`*6BB1CF0*Y1>d_~i3Cs96_g_Go~z3vQEG}SzdzSH)MFQaIU?Y5BbKSUL+ z%-RnbPaDtdseiXLR6XcGZN4-ruGFabr65K#0e z0Y#e$D0+;5qQ?m+dV+wWCkZIpLO{_|1Qb0@K+!V<6g^8o(Q^b8Jx@T<3j`ExC7|d< z0*bZ~P_&)kE4tfuMhcMd6Xto*J*wzj^m8%WGro+X*KBu=d}}MJ=yfiyir!$Wq8)5i zw3DrhcCl5_Zni4g!&XIavQ^PrY*q9&8%6IBQ1mVVMeh+%^gaPadkHA|fPkV82`KuA zfTDc_6n#uU(I*5HeM&&legcX+vQ^PfY*q9#TNVAn zRz*kIs^}P775&OqMaS7F`i+31-w7x>K|s+-0*X!%P;{DrqB8^(oh6{?4+4tL5m59e z0Y$|G6#Yd&(cc6VohP8^0s%$;5K#0l0Yw)HD6(So^KKN`1Qf*(d__lW=LZ22J|mRe zZ&lGI^Zh9&#xuT*A}_|3|F(^yZKv5+EiYgOOluSTT6#|N?5>Ql)fTHRI6xAT0s3rkLwFoGxO+Zl! z0Y!BPD5^_9Q9S~R>Jw1ZfPkWg1QcCD@D;f+P7?tVZXw?Qcgw~2pXt9L|GvO&6yq6R zMp3gEw|^s5l*;8*Q5stnrL$F023r+nvQ<%Ywkm4DRz)q@s;CuP6}4ugs0{%{Z3!r9 zM?g_~0*X2iP}GrtqD}-9bta&w3jsx01Qc~8pr{)GMcoM~>OnwJPXda15m3~dfTBJG z6!j&bs2>4E{Rt=QG(S2-Hw1KUP?q{o_jcir)09zG3$W}$0 z*sACuwkmpE*=otcvo+Y5@ zIRc8FC!pvB0*ba0Q1l`JMcW7{+D<^xO9T|XOhC~q1YgnG7^j;63D=Z=nc?26ip+nA z!hJQyGro+X9Wn0sOjWd#%d4VYY*nW7eL_Idrvw!3C!pvv0*Ve0P;`)hqR$B^Iz&Lx zVFHT2AfV_=0*byOpy+D?ioPMB=m^1A^m>f5On`)Ins3p+p^93`vugL-7|-}Jihhi7 zA8VnCe&X_~=x4Sn`h~5Ej) z83KyV5>WI90Y&EsDEgCtqGAGy{vx30Zvu+W6Hs)4fTDj0DEgOxqKgC+$$x=+oji>4 z9d&t1V!j(|6HpXGK#@a0QGkFVm*6Y^^g5l~d0fT9Kj6g4EE=n?{o8WB*` zn1G@t1Yc3maVoYJMakxq`|^(enSN}HjHZrfd>KXQj@zoOD$3yUswk7Kikh=kQ46*z zYROhbt=OulHCq+6VXLCHY*o~bjiUAh6m=k=s3QSIod_uEOh8c=0*bN-DC$Z;Q8xmL zx)V^;gMgx*1Qhimpr|(iMSTb;>PtXTKLU#S6HqjOfTDo}6b&MvXfVN7l#t~37o`9kW1Qg{GP&AQ%qDcf4rDq6@^MK`il(IPgA786jkgn*)@ z1QgvwK+!S+if$&L=oSKsZY7{-IRQnt5m0nH0YxhaC|XHC(JBIp?jWFOH33C;5>Rv( z0Y!HcP;?IgMQaEsT1)U1UF$eM36Ss^^UtMctD-?h(Y=mmd>KU>9M|ijitgv~s%Rry z6+OUKMGvx7(I&PkdWfxx9%ieeN7$<9QMM}D%tp~;1Qb0^K+zKf6g^2m(G~)Vo+6;= zX#$F#A)x440*am^py+u5ie4a~Xe$9lFA`9+jew%<1QfkQK+($t6um+~(W?X$y+%OM z>jYoXddF!dK*AyORmb~O(GdAAtow%J8DB=xZpR(iRTb^w@~Y@fwkmpyt%}}etD<+< zs_0#|DteEtir#0dqP=WY^Z^@19}-aX5dlT}2q^lPfTB+bDEgFuqWuIEeMUgh0RoB+ z5>WIx0Y!%hC^}3)(H8_1eMvykR|FJ&O+e8%1QZ=1py*oyioPSD=zD^%Xs6@M5Fp`u z%s;i>rHU4sPy2sxJmbqK`o(cqcUMJ6xx6Ym##TkYvQ^P>wkrCKt%`nUtD+NZRdkZA zicYar(P=h{&Ja*^mVlx^2q-#7K+&HB6crOt^cMj|e-lu2o`9kY1Qh*4K+(Sh6kQ~s z$O`DE?I^MdD2gGV$RVI8KtPd8Kv6jYiaY{}f&^dDPmZ%)fP^=he_!;oDw<`!15!TV z8DB*{Ud+jiM?96jddl zs2Tx9)d?u7K|oPW0*Y!8P*j_Mq7(v(>JU&=mw=*r1QgXLpr`=>MGXlkx`cqDMg$Z! zCZMPZ0Yyy-C~8JPQ7XY#6bd;13Xt%9@{`GKY{36a|B(5))U<$Sd>KW}18(g;s;C8* zS4Az^s;CuP6}4uoqBd+*)RwJ^+Obtpd$ua-z*a>a*(mBnKv8D`in~8Qxy$1V|c(bzKo*F18#0VRWy>ztD;eCRWzEdimqU*qA_e$ zbR}CAUBy;K*=$ubmaU3%*eDuDK+$*tiY5?HluJO-L;{K?5m1yzK+$9ZimoQ0=o$iw zrVvmxm4KpY1Qg{HP*gxb(R2ceW)M(RNI+2$0Yx(jD4In;(X|9$(WL?B76B3-ZJtnH zri#`XMY98*@nsav3%E}VP({~sc~x`+TNTY`tD*&LRkV<;if&}9qD5>~w3w}mmatXP zQZ|ZiBA{p)0Yx_xP;?6cMYj@Aw48vV+XyJSoq(bh1Qe|#plB5VMRyQTw3>jTI|(Sd zi-4lL2`IXUfTA@76s;wo=w1Sf))7#&p5QB*8*ugsknmqJ-Ro3QSMw#v`vRWvWfVOS za8C_VMGta$RkVq%iXLLCqKDb4=n=LmdX%k-HnUaHV{BFQI9nAx!A8-O1Qcx{py(+A zik>E*=otcvo+Y5@IRc8FC!pvB0*ba0Q1l`JMcW7{+D<^xO9T|XOhC~q1QfkWK+$Ui z6unMB(HjI5?I56NC&5>Af553cSQI5D2%L?osD=3#v%3PG@nsaf6>!@ORYh-ec~$fd zTNS;_Rz>fzRnhxwRkW9_iaubgq7T`s=p(i&+Q&xG#{?98LO{`{1QhKjpy)FKiVhG^ zbdZ3e&j~0xL_pDD0*byMpy*2iioPPC=xYLsz9FFK2mwXk5>WIV0Y%>vQ1k-4u8NLxc~$fqTNVAzRz)Y+s^}zJ z6`f+MqSI_ubcU^p&azd}A8ZtzBcSL{0*Z;w3nQQ51IF-IuDO2$xqyiELGr#8yQW*{Y}#TNV93#N7vY6m|Qk z|5=vFre_n_r9)@}3Z&2xgiV7;8YwiO??MX99|jA)u%W0YzO2DC$N)(Xj*+ z9Y;V>cLIuf5Kz>UfT9cniZThVqGa3qg#qF(lpjn>vE4oWzH%Tt%l3&cQPjt_ zzO1i``Z24b{>-Xq0JAC@$gGNvXI4dnm{rkWW>s_ovnm?GjH00g6om*V$|0aAmw=)? z0*dkpC@LVJXcz%S!wD!VB%tU-0*XcuP*g-fQ858UB?J_e5>Qk|K+#A7ipmKnsvw}K zl7ONrf~%;P?d@rR_?wwu$+vr}qIq)gXq4>}U!rK7ZI_NyMJKVoDjLtMicV%$MW-;U zqA;^6I+a-!RWqxi3CyZ!BC{%*#EhaE0*WRRP&9>rqNxNFO(URaIsrv92q>CKK+!A$ zifRccnoU5_90H2w5>PacfTB7Aislngw19x3g#;9xMnKUb0*V$BP_%^LDjH*Z=NlmY zO!>L%v8rgN{Owhz+dlCnik92<#__6X1?#J#mCUN>OlDQIidhw{W>!UKF{`4pnN`s_ z%&O>IW>s_^Gm6#_P;@>4MQaHtx`2S93kfK?h=8JX1Qe|&py*-(iZ&2XbO`}P8wn`7 zlz^hk2q@Y_K+$FbiY_OhXbS;FTL~z-f`Fnc2`Jh|a21_ldml7F`~&3Yu9vBzv8iUb z%JzvbQFNVczkP}-x}Nn_(GAS1=tgE$bQ7~Gx|vxO-NLMjZe>jV_NK|s-d z0*Ve0Q1m7NMQ;&M^fm!S?+{S*E&)aF5m59#0Yx7WQ1l@IMIRAR^f3WNpAb;=DFH>F z5m59w0YzUBQ1m6iRkYXk78oG@?Q)>;X;tL$nBgniC%#0{ceXucqAL2H^;OY9W>xe9 zvnu+LSrz@ntcngXtD>KoRnafZs^~DYD*BZfMZXbH^g97XM+hkTgMgwx2`KuDfTF(% zD6(R7w;e?u0*V?DP~;_`s4)RWHUUL31QhuQD2gSZD2{-lcmj$N2q;PPkRS zHv)=|C7|dy0*bm5P}GBfqMig4We`x5NkCB+0Y%va6!jvwic({|uNWZytaJk>Eymr` ze?VT*ddK+0mniBVWB)Wo6%Am0RWy)U6&=s4iUu*OqQT6n=mcg}G=y0d4P{nEA!b#S z!;GR_0*dkoD9R_GsDOZ?VFVNnC!na1fT9x#C>lXPQ4s+}#RL?U5KvS~Kv5Y1MI#9) zDkq?*f`Fn*0*a~#C>ljT(P#pS#t>XZePg`Mry4~s%8OV(RrHk{f*c#;6JMg}#L$Lvno23Srt_?tD*_as%Rp!Dw@QsifWiu(PU;-G=&*OQwb=VMnKVY0*Yo3 zP&AW(qFDqK)e=xNn}DJ@1Qg9BplBWeMRf!e%_pE}0Rcq|2`D;^fTBeN6fGv8XbAyD zrxQ@Llz^f$2(F@&V!WpqApZ99?s~i`Dv=*qTNdLJU!v&D7<>6lRkVurRncl@Rdg1! zDmt546`jMZiq2(LMdvZAqBYE_=zL~Xw3Zn~7Z6Z%Apu1f5m2;_fTHyT6kSX}(FOvF zE+L?3BLPL15>Rv*0Y#e#DB4Uw(d7gbZ6Tm&D*;7U5Kwd_0Y%#gD7uP(qN@ogx`yB? zS`p*D&H(X$AV0moQWY(g4b!zTKJg`rZj7<_)T*MJSYH+0%&dxTVOB-AGOME7m{rks zW>s`MvnslSSry&MtcvbpM$z2_6x~BW(GCKNb`nr@F9AjO5m0nL0YwiGQ1l=HMY{+n zdWe9chY2Wpgn*()2`Ji4K+$6a6g^Hr(Gvs|JxM^(9s-JjW>s{A8AX2( zQ1mAOMSl@c^fv)TmQQ!vQRE?@s1X50UIL2Dk3_hi*rUiMpeTlbA|C-ou>=&w5l|FQ zKv4n#MTrCyB@s}ROh8cz0Y!cSic$%#qVHq83k?we&GI?gK~?mU{EB0m&nLb_QP5{! zwm=m%V|`WBoLLpMU{*yfnN?9MW>wUhSrxTmRz+=@RZ%-;Rg}(*qV@z7bs(UqBLPL7 z2q@}IK+!P-6m=n>s4D?Q-3TZ;mVlz;2q@}KKv53@ih2@IltDmICILlR1QcZxP}GZn zqTU1)^&z0BFTqvR)aQN30P!!CLqq|eyQiNZuW0>zKJg`rj`!K`o~DWhvA!xA%&dw| zU{*y#m{rkGW>pkoRz*3?swkIP73DFjqI_l)6%bG~jDVuy1QZn#P;?>zMI#6(Dk7k$ zn1G@Z0*XorC@LeMXe0qePabfTEKKuA%`x zZ=*#<(RkSw4OB&2MA3MkPkf1@Q+;;FC90^J^;OXXW>qwiSrtuURz)?;s%SE^Dw@Kq zil#EFqG`;kXgV{BW)M&`lYpXG1QgX0P&Au>qB#T<%_X2{9sxyl1Qg9DplAUBMGFZi zI*ov$MFbQrCZK2u0Y#@1P_&eQqB966T1G(8asrB05L`v4_`Jgn5Wi18fDNmn>(kA! z(&rOjqUbE2J#DEfI-B)X(K*bj=v-!1bRM%RTEnc0&SzFdYnfHi1Lw3C3MdkHAIkAR~4 z2`GAifT9NpDB49p(L)3jJxoB+BLoyZNxejvnu+F8AX2+P-MmGE;oui1QazQpvX%=QDXv%Yyyg62q^Lq zP!vl*Q5*q9@dOkl5KxpzKv5C_Macvdr4Uf$C!i>mfTA=4ikc8m)Rf>V`qAe-)d2A? zZf@ZGq>A1bMS)nK_!31eV(pb@siKywuZmhRtD@G-s;CXKDr(EDirO)&qI70e)Sg)t zbzoLS9hp(oiGZTc1QZ=ZKv5S0in1Qhikpr|JSMHvJXWfD-7 zMLQ6B<|`VvsokAR~71QZP*xQd#^dT%g5{GB=(IL%|-J^jJ*n?wU+ zed0?Loe*p9Jx3J{VSQCJlvx#pm{m~@vntAERz-QtswkgX6%{b6qG8OcXgD*93JEAW zk$|ER1QZn!P*hAnQ3(M>r34g}5l}RefTD5&iYf>wswAMOih!a~1Qd-XplA#MMPmsl z8b?6UNdy#)C!pwL0*X!{xQYhFdcQG1{4uhpKUftl3z#7s>l0t1Xkx6Lv_=(8VtrLq z!>o!XGpnL0%&KTAvnra#tcs>HtD+gqs%R#&Dw@TNqFMrqW)n~}hk&BF1Qg99ps0?3 zqWJ_AEg+z1Apu3F5m2;#mJ(2O1_4FO2q;=kK+y^UidGU(bS42s zs|c>5>R4~K0ph=*rGYa+6}1ymt7CoQOB9_OYgepQMdz`;Dq6#=iq2ybP=;ETF0!4)-$W3io#SFsq`S z%&O>KW>s__Gm7pfpy&YtiXJ4OXcqxR4-ruGFabr65K#0e0Y$qBD0+;5qQ?m+dV+wW zCkZIpLqO3}1QhKhpy+7=ik=~$=ve}ao+F^>c>;=FAh?QdjrBfafcU4z8aTJ9q7UWQ zie8NMi7!#~O050#L&Im{rm1%&O=OW>vJGSrr{%Rz+_ztD?7~_?AfV_+f~#m>the!cqiDVS-1W<mfTA=4ikc8m z)Rcgt00Bio0*aauTtz>}dQUV!{HLWGIKQZ(eWIv&oKJj-qSkTtjE$wUYSrv6+Rz;neRnalbDC$B$QC9+rx)D%xECEHw5m3~ffTA7* z6!j#aD1(5aOah9s2q?-Xpr{uCMZF0q>O(+LUjmBy5m3~hfT95e6b&Sx=y(E(1`%9E zE#tiF3=n@%{<{5Eaqgb}ZuwAcaGXzkiK0-Peb;5GD2Me`Q7*G8%41eV`OK=QfLRp{ zV^&4OnN?9Cvno1~Srv_7Mo|#~Ma2XZl@L%=Ncgk)iSH1+03eF z4l|185>PacfTB7Aislngw19x3g#;9xMnKUb0*V$BP_%@AqSFZ|T1r6C83Yt9BcNzG z0YxhaC|XHC(U}Akts@A(OTA5MHeuuq6?W-(M8OvXdSaETFf zP_&tVqRR;=+Co6lRsxEyAfV_<0*bZ~P;?amMOPD0bPWMT*Ah^49RWqx6Hs&m0Yx_w zP;?UkMK=>rbPEARw-Q`M=f!y^7$E+9`Q@QCs%W}=rhi+UPkf1@JLBwCSE{1BSYH+0 z&8&*s`AvnsleSry&Stco6BRz(joqi7caMGp~B^e_QMj}TDwC;>&g z2`GAufTG65&=y?K)ULc_8MFNUm zBA{p=!Bup7ocAUJ#NSkY?)nZ@^n@sSInF1(MA7SU_A^(hqBmGy742tMMF*Hw(VNVw z=q+Yd^ft39dWTsRz00hM-eXop?=z$50|JUZB%tUc0*XE+py(3SfTBbKijoK@N+zHvg@7VI z0Y#|<6r~YR)P#VdrUVoP2q+2?P}GcoqUHn?wIHCVCBaqnYn->Y0ph<-4mAFziaN_* zL(?kWC%!~cyLh|mdR3Ip`l_fsvnuMqtcp4^tD;WKs;D!wDmsQ)6?I`&MO~RyQ8#83 z9ZNvbaRd}~C!nYY0YyCtD9Rw9D3gGqECPzM2`K7CKv8c3iuw>x)R%ywegqWtC!lBm z0Yw7|C_0{iqCo@{4JM%I1OkeN5L`uV;=M}@5Pzn?X&dkE>Ax+*(0HHt5=D9O_Ldt} zQ9kRdq5@`BG>lml4QEzGh0LnxL}pbqf>{+6F{`3tW>r+ejG|HkipmHm8c9G=IRQl# z1Qb;gP*g=g(I^6nMiWpphJd261Qd-Upy(t5ipCRAbTR=&rw~vSCZOn40*a~$D4IY( z(L@4@CJ|gkIq}}z28e&9yolwhqH&34sEPN9FHtlt-v01rRWzOTRnZJ)RWy@X70qH+ zMYYVTXg0Gdn!~J$<}$0IdCaP)ju}Ps2`E}XK+!@1icTY-Xb}NLiwP)NLO{{!1QabL zpy&(&ik1;jw48vV6$BKmB%tU_0*Y1TXRnf)Fs%QhVD!PPO6>Vfz zMVB(GqRW_7(I#dTZ6=`TasrCB5Ky$0fTAl1D7un>qHP2eT}43A)dUn>LqO5B1QcCI zK+*LC6x~2T(TxNY-9$jq%>)$PLO{{21QgvyK+$#rif$*kiq^(^iwqF|vGQ}*7pS7n z@+Rqyc%S$ZMfb$pvu;;KJ6K;8?POL(_cE)Z`F5m59w0YzUBQ1m4MMPCt6^fduR-w;srEdfQ}5m59!0YwK1DEfhbq8|w;`iX#| zLj)B4OhC~u1QZ=6py*eEtLTk*?*RkEzej%UW4|iu=`+J`@jme-ivEnZf4f^1{l)sK z=x=6KWF_dHyDIW9tD;8Cs>sW%iW)PkBAZzi#W1TPA2W(#2`GvqpeUYzq67kp5(y|u zBA_UlfT9!viu?o=r4mq-MnF*$0*aavP!u4bC`dq2GXjd56HwHGfTETJ6tyCts5Jpa zZ3wQSBk|t0_ZUSTI~q8DsG=|A;8EKIpZF3*9TMyzJ5^Cf)>lQHm{n0{W>s_yvnuMs ztctoatDlaQ(NF@4LIf1$5L`v+3EoKth<|yy zfzv+0-P8X<{xYN71fTd4MZ*&8v+h$x!&zSy6*8-$6PZ=f2xe7O#H@;nnN?8&%jU}LH905fq5l}RqfTEKLC_06J zqA&qPrxH+9O+e8E0*WRQP&A2vq8b8=&o)iJB0`OKtD;MoRnbOfRdgw{D!PnW6>VZxMVpyb(dEplXbUrnwh~Zu1p!4@5>T{_fTF7i zD7u<}qH72!x|V>V>j)^io`9ko2q?OdfTEiSD7u+|qFV?kx|M*U+XyJyPC(J^1Qgvt zK+&B96x~H|6r~Ob^1kTq1fTd4MfWDyqaRU4_p!bzx}RAUJ;1Dr z9%NQUyO>qcL(Hn^VP;kI2(v1Blvx$+W=7Ft1Qb0^K+zKf6g^2m(H;Vdo+6-VF9AhQ z6HxRF0Y%ReQ1l!DMb8sZ^a24zFA`An5&=c~2q=1)fTC9jD0-EEqSpv0dYyoxHwdnx z9SPp028jPl`E}Txs^}isFzrw9i7!#~c7lDyZdLRS>#L%7nN`ty%&O>pW>xe7vnu+K zSrvW6tcpHnRz;sMtD;YtQS=!BMV}K;^aTM$UlLIC6#+$G6HxRG0Y%>uQ1l%EMc)%p zbdZ3e9|$P=k$|F~2q-#4K+(?x6#YU#(P09LekGvjHv)=&C!pvE!BzBTg7`{Tz|ktb32w^6Rz;1ORgulCiei{mk&jsw#WJg+ zIA&E8&y1o30*Vp|C`uxrD4Bqw6atF;1QewbP?SbMQ4<1+ni5bHAfPBnKv6RSikcHp z)PjJbmIM^FBA}=>0Yz;HC~8YUQ9A;P(h07jzY@H$PZ&k5<#^HGs^}L{)IQNCzC=;y zM7!G_RdfvNtD-KdCB%GMG`6NkCB+0Y%va z6!jvYs5b#ceF!M(OF&US0*d+*P&9ymqJaby9Zx{fAOea86Hs&l0YyUyC>lyYQHX$| z90H1R2`I`VpeUcKG0~pAR~3z5eN|M% ztcr@6RZ$7EDk^1GMPnInt-AS1QbmqplA{SMKuHzO(vjd3IRn^2`HLIK+$x9 zt7v$l_YwodKT{476{;ey?Do${^ocJ~G&|AW`HU)>!}_XdF0(3{$E=F#m{rkyW>vI+ zSrsj0Rz;^VtD;5Bs%SAYik1*ibUFb=O9?1CgMgxC1QabNplAgFMJov?I+K8+RRk2R zCZOmn0*cNipy(U|iq0jV=sW_7)(}v1J^@8*2`IXNfT9ZtD7uK?Dw>t(eaisx&yb(H zu2n^AMbWxMpZF3*mn7Opo>N5|Szi@h%B+emV^&3*m{rkcW>s`KvntxctctcWtD-BI zRne8qDB4Cq(NzQ#T}?pIH3Sr0OF+?e1QcCQK+z2Z6x~Qb(M<#t-Aq8yEd&(ZNWIK0Y&==D0-QIqE`qgdX<2p z*9a(joq(b@2q@Z5K+ypLiryr+itbDFPBuXNz2&b7xnC7s6K{sM5`E%J6up;dpR-RD zz0dlp=mTa|^dYk<`iNN-eax(iK4DfxpE9eW&zM!w=gg|;3uY93NkGw81QdNuK+!h@ z6n#rT(RTzCeNRBqK>~_?AfV_+0*Zbjpy&_*ML!cz^a}w+hY2Y9m4Kq(2q^lUfTAM= z6#YR!(Vqkq{Y7vUy_4v@%>ePo%TdR7Rna|7%n z+svvchFKN)m{n0Mvnq;XRz>m5swjb36(usOq9kS%B@P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_WPo`9l3 z1QZP>py&hwiiQwSG?aj%5CKIw1Qg{GP?SeNQ9c1h1q2igBcNzF!BuojlDEGB;@>Mf z_gz$xC7*y4Ci%pdC@M~}$L?1}C9JQCN|{wr8M7)H$*hXXnN?8*vnr}&Rz+3Js%R9m zDjLm&%jU}LH905fq5l}RqfTEKLC_06JqA&qPrxH+9O+e8E0*WRQP&A2vq8b8< zCKFIJg@B@|1QbmpplCV)MKcH}nn^&>EP|_OM3Q%z0pi~&KX+ZEin__0q}n8(_!33) zlI(47s-im9S4H!gRnY=wRkV;<6`jVciWV`eqQ%UrXbH0_I-OY+EoDa083Yt9BcNzG z0YxhaC|XHC(U}AktsD1QcCJ zK+#166s;qmXgvW%7ZY4XbCSGI8X*2F#Us^|)4Rdgk@D%!@ZimqZ-MOQPU=o$iwt|g%8Is%HWC!pvC0*Y=V zpy(z7if$&L=oSKsZY7}THUf&a6Hs(J0Y!HZP;@5&MRyTUbTxeQGm7>SQ1mnbMb8jW^eh2I&k<1cJOM>75K#0Y0Yxtn zP_&PLqL&FMdWC?ZR|zP3jew%p2`GAlfTH~b6dfR-=uHBO-XfsrZ32qkA-IYjO!Af) zApS$m44hr6C@61|-c9m}FH!Vil0EkWRrC?-tD=vYRnaHRs_0W@RrDFND*BvR6@9_1 zioRr4MPD(iqOX}z^bG+;-x5&t9RWq(6Hs)JfTAA=DEg6rqMryTIz&Lx&jb|xLO{`B z0*Zbmpy)ROihd`c=m-Hte-KdgCjmu&5m59u0Yz4_?wF&0Yz;HC~8YUQ9A;P z(g`SPPe4%z0*X2kP}GTlqRs>q9Yb&xHBR=vV}SU#%Wj#S?C$BGEPqvKmt>##5=F-) z+kbwdin_DDD(b$TMMDTE8cIM>h=8IT0*Z18D9R(CD4&3$0s@ML5l}Ro zfTBVIicTb;XavDk)GgWD;ZvjNh6)j>`MT?nL(Gq4=bUL#t zTFR`7&R|wW%a~Qsa%L2*AfRX^0YzsLP_&AGqSXWxokc*=*#s1wLqO5F1QeY|K+zfk ziq0pXXe|Ln7Z6Z%Apu1f5m2;_fTHyT6kSX}(FOvFE+L?3Bf(Wvm+ZaW0P#1M7qR)O zC{uo7_R?gZ_!32zC)+Q5t%|m=zAD&>btuaOycCHuse zD0(#64t%GIcC)@JdW=~WJdXIpj_X)0|hm*Yn4G{lZ@^jaZsG@ORGklQj6JMg}lVtm(gR1CL z)>lQJF{`4_nN`sj%&O>1W>xeRvnu+USrvW5tct#6Rz=@2qv(4AiVhM`^aBA!KN3*% z69Gks2q^lQfTCXrC^}3)(XRv){YF61?*tSbA)x3F0*d}5py)3GivA{`$V$=Ob`*IC zC~8DNk(Yp?#spWP!uGfs2Kr8%?T)KK|oPU0*YD@ zP}G`$qBaB+wI!ga9RWq@1QfL=pr``@MI8w!>O??MX99|jA)u%W0YzO2DC$OV75P%U zPZ=QoP4aWsu_^AJ{+;qq?j4)r6JMgJXNvv#Ayt&Y`l=|CSruh5tDFT zMSYl6QD0_N)Q?#e^=C%W00N2z5>RwJ0Y!rdC>l&a(Fp_;4I!XtC;>$w0*Z17D9RRz;(jRncf>RWycK6^&(9MdO%N(MimzXgsqjI++vI;Srx5hRz+trqi7WYMXL!YI*Wj!vk53V zhk&AU2`D;`fTA@76rE2%(OLqEE+C-jLIR2|BA{p;0Y&QxD7u({q74KTT|z+7Mgod1 zC7|ds0*W>fTty30yqgRV|Bdn@cA6@hAP0{&r})H|D7qrWe&C2Ix{~!((KcpPbQQBI zx|&%PUBj%3u4Pt5*DzP&24a}ApWuPRw%*m?& zK+zBaiiQ$U6e6G~hk&A70*dkoD9R_GsDOZ?VFVNnC!na1fT9x#C>lXPQ4s+}#RL?U z5KvS~Kv5Y1MI#BWq71+H7X!pUM?Oc(R7C^j)7WyqPkf1@QGUCbPZf=3eN{AuSrv_C zRz>5ORnbYzs%Sj3Dms~26`jJYio(pQ=u~DDRTEG&fqCPK+y~Wie?f}G>d?uS^|n@6HqjVfTFns6wM=`sE&Z5`2-X#AfRX=!Btf0 z_YN{Z{F~(`W~)@u0NL$7&F>RmqUdzLeR7;CTFUyW=nQ66w2WC5EoW9mE0|T$N@i7b zCbKG9#jJ`}GpnMrm{D{#0Y&E!P;@QD1QcCJK+#166s;qm zXgvW%7ZXslfq=W?Pkf1@ zJ%0PkBvtej>#L%@%&O>VW>xeIvnqO)Srt9UtcspzRz)u`tD+Z~Rnbe#DB4Fr(aQuB zy+T0Is{|CiMnKW)1QfkNK+%2ziVhG^^d@YweqdHbKQgPLpO{tAA!Zc)OhC~u1QZ=6py*cuihd)Y z=yw8&ju24v2LVNY5>WIP0Y!fkP-La*Zaa!R1QazQpvX%=QDXv%Yyyg62q^LqP!vl* zQ5*q9@dQ`V7k+Q00pjm2KfV8@DmpdE3<;?|@g<5sj!swkCN6{Rt&q9)9$ zs42553NWjpAhRlJ#;l5(GpnK&%qVI}Kv63Kidqv;)P{hfwgeQlBcLdqfTH#U6m=k= zs3QSIod_uEOhC~w1Qc~4pr|VWMcoJ}I+lQ<;|M6~PC!u)0*ZPPP?SM%6(yy5FE>E^ zH`)eHa;m$hKSqu^W~TbYmniC;YVT^Qiu$m=D(cIuiuy6DqW;XPXaKV+8py1Qj%QXy zgP2v(U}jZx0yBz+5KuIffT9oqML7f%!V#Fsq_-nNf5e0Yz&FC_0~jqO}ART|hw5 zg#;8`L_pCx0*clXP;@Z?MH>hxx`cqDjRX{3N>*Wz^sa1WL8Bl zF{`3|%&O>RW>xeGGm2g%py)LMie4w6=nVpj_7hNafPkVm2`GAtfTFhvD0+v0qIU@> zdXIpj_X#NafPkV82`KuAfTE8HDEfqeqE87Z`iy|0&j~2{g5WB8D%Ja|0pcIq%D~yH ziWbUmHGY}u6JMg}+f=(nx+?mP^;OaL%&O=hvnu+5Srz@rtcreORz-)HRngDPs^}MH zRdkpcMZXeI^cw+1zY|b&gn*(y2q^lKfTF($DEga#A}dXI+fn2ppr{c6MP34m8WT`t z6HpXGK#`AtqF4fo;s_{;C!i>SfTBbKijoMfqOViECm109#54ov8{QYm$05mSKJg`r z($eg32UXOB^;J<*W>pkmRz*Q(Rn&}G6*Xs8MJV8R zfTDB)irN!U)PaDajsz5SBA}=<0Y%3UP}GHhqOJrKbt9nYSOSWUBcP}|0YyCsDC$W- zQ3e4;nFJJN5m1y(a25H}ysHfmf3576rKY)i`d1n}cCR#__!33^((LOysiOX@uZjjR ztD=F-s_1xTRWyiM6%A%qMJF(;q9M$xXehHP3NfQ7hk&A70*dkoD9R_GsDOZ?VFVNn zC!na1fT9x#C>lXPQ4s+}#RL?U5KvS~Kv5Y1MI#9)Dkq?*f`Fn*0*a~#C>ljT(P)CJ zs85>rSp&r1L_YNBtBP)OcG%K<;!6~bPqV*1MirgR`l{#@W>pksRz;^WtDuHNy=waSf(%r&2q#0EB)7sABA&Q$X=w}JiUCjpuUTA3fcZ62sL z=g>NEqxk{K^uV{~T~?<+FZ0W{T?32TTUPhLqvqq5%z%B2W%Uk>=xSO01M82qtU-bO z-7RZqpiPEl>2Fz;fzt9?*#UqV_6>rlGa$(CxME!mi0wo^M#i6P2l}?mUS@D zd4pvg3e4DOS-%GEy3Dfv2p-;S?tf2k@K*T|+2E=x%_HCmK690M2t2`*Yt3We307Ti z9t2Nt%Z=ty@B}}+**pxMV3*s>Xb6O@0BysIZD|DJSrPf-3r;7m_Y{zcc` zo}m1boc%pP`8O2@d4lqf;tll#uh?xK5KmD4S*qclp!~Z+MV_Gi!!Tu@p!~}om7bvd z(+p!gLHWD&$9sbEm!qHR3CiDYJ;@W4zn*xiCn$fv>`YHk{({gso}l~pVgEP5(;+wD3}P<~zMCQnd)-{dw=P<~z0m;t9&(i!VGu+5h~;6OpJ%-*X-nY z^I-N$XyP*us`>Mp`S9Aab#;cvYCga`S3JFXcQM~dcE4$wc}979jgV$!Sw^7Me1>@r zdU{Qi_L-RvNZVkZVV+*gqz(7T<7V3H&LwS;rhU{*rjB)m3Jl^=6%WS?AE}Z^Sz5JaFeL51!$y^U3*}4wwr!SMP>v4!p70 zYW14ey`XQndKVozcZE5BbDO@s=fidG)%$tJ-ba=@YhAKq_YrfWvJICj%|*30|Cu`? zCiST;AHCzQwRZc3+s$dsJz=MuJiuA$@4p`Te3{j1s98y_UxmApo%m+2P=&c9JMo5| zH;s2zdB8hnhI5O)ylK!$R+|aBhI3zkzjkh|bG>dn_|`S%&N7!U>`3lh=Mp~ue9zaX zTUJ|dx@F0KF^#-2ZJ#k-+=9)B~-YShU} zNI1bHa|S`nn>;Y#_=Euog-y)HPQN3E4*OVAVj6qA$tNTvm~Xo$^O)%CYSwCPUY%l{ zFKo+-bG|Ul;`Iz|_Y4zK%tguhBsTFRB-EcnQj+D3<#H1ek`fXV`kV7hZr0#bDdtpB z*Uqn_o_DIAr5WW)rRiBZ->pB(CVG~7s-|WoyZ(9vlFY4?OAb0;m|J4J4{5=rc4<-A zB-N7^Gqm|-IW6Qun%hy=s8O@~a?IV?qW3>r%jhQeRIBsO^q7YttBIUT>osS3tVYe( z=a?s48@^#4(w^3k7K2*UCOa2zuCVoQfBKr}vC3pI$UNUX)@WIDH?|vFKY7Zw$yaO4 zf94yq7-d|!-;l2sng7f;WFebD_Z$CqDQ-K~xvY`0C^FADk5wfLE^DN7S-qXJtda$n zHF8`1WmQFA*2ry9m*p{6JL-?wV3`Xjm&H`)c8!t+msK8hS)-yat32wmMnzv%dGuvD zm($z1gbG=3<17AgB01#_b0ZsB>z$=sfkxID&J~ffm(ImV|F=K7eq&kc`i*6&>o<;C z-<+fSr;+7p z`JnmFoU+b*OTK){8HdOykC5C8a-Lj=*5(UyUgl5aYB{HIlKxND;m;QHa_6;PHLEo8 z97#^HJm!!2o;-RzduGh5&X`;`C!=oO#Eg02x`{R6IrC=EubDW%W>Ut)d5h=FpDkfx z&7=kMYU-lCC#N^39*{9--n3cM=1*H#V`WU8J*y_8dS=a{jGi-RPpqDqQ8%@EUQNcl zn%bJW>bi`Y>~P)u1(T-D&X_-Y_RNV>tEbi0WlWhkFujs-8G?TJ8Vyt5LVOF8ZFB zGBqPKZ_7KeT)0>Fqs?sfAQS^{~%acJ-hO6gHGtJr_8oH#+dVRS88v*bXV#4Ush;hPLfHNE5lBcwPHr-a&YvV zeXMheCNV)ft+n}*Z;sUyv2uG`&XhB2-@#66Yo<)OvVs3{P10h5-7~U!^tL;B7nu8^ zi&-u8&2HrRohU~3)a1Q{_+?V$7hm?n0xohj`H>$(|sGv_=q><(s` z=$!H3K^n)o_eqNTaCX**(;0i3Gs%`qv%4N=Hx#TgWe@_ZteB@?@G~w=(xk*A8~8wssPmgC^#lFk7;&vM}Fu#&p}$XOKCG_w8kk26>#dlFW0k zrTKohOuOYj*X|a*c2BcrwmEUIeTLoDyQHVxD&3R}J)6P*SjyST_Zu!d*j=SNXWY@f zTK~9~?&Wwg47siy?Ut>~*|b0EY&csb_wTos^Re3sIp=&>FT-x*u~W^pFyvfQe!H!V z9o%ZJw=YOTSmODkrwUH$v4Y?_D6{D|n{be0>7nl{z2K#?=ox7Sxq)pT<|KHwH z*$lQZ4^k()O>1X8g1PgK`ZCGf{C090?|y5{{|7!zvu(52>1=BEEHmyzquIr{SPLW$#QDxT8EiEo9%C9u1tSTwg(-q_n4^OB+VW>PWTvA$T zPF#^+UYVa4`Ob-D=1i+fDyquLO642jvcfU>Md5AGfTqSnf^dG;&YoWJX`n z!jf7J#Wne(uPiwa9dMDDfGg$0G-P?>Wrb4yD~ z@^eLtBd?&h++og_c}k+9DmT|CjjRpXkyZIs`QZX{Per~}7Ah~S92*%0b#bUUSVihxU{OWtg13RsJO;^;jGcSKsq1lzmsj6`AW%JyK-X6J6CBba&WO;JS{Smc#`55z* z4wsI~FE1!69ewnLmX{2RY&MOnP;ul0g=J=ArVnwM*_=dgPo0}oVI)L0lG%|vEGO#D zkq4;$qFwJ%-!>0~xl6+NV{-HJ^P;Y@-XUfSTNyH2h!Oc?!vd6x4S>M3Lw&s??A zs&ey%d5#qn73S7&^&O?MF^k-FS=o^%xOu8ur3>cgRnM;uSJo_YH#1r0$vA1jtXYdA z7vwxQ@=FUFK8Ls(W}94GS}u=`Y&6{`bhh(snK`?5O1jyCIjy(3Ea%2&nJ-w^+@Tev z^{-j-8W8!OZiLJ8i}IZfwXB@q5S9C|%N<}I*}?+%9&#_GZ`7qY8zFh5WOL`dwCS~M zfQT(XIFy@PRUXRK?OEjd3^y-&qeJF~Ru&fLn}^IfkN%N|JU8kB%gh5-QJ!m1g>owk zN4YOReWPCYc!ru+>R~0$tF&|1^fD)rFG3Br^wFD%`ps8Xe&k`4FC$k|RTv27316kJ zedcP`pTJybPI<_@zN;s>MDyrGKcCE9#kRMov_hZJ{UaA>9tQUw%;AfC=K-&qHl?;^ zQo1=NH7{~;g1fZ9oSi{ZzrC*C9^~ehhKHN&RAdG2o8r9-3X6*J zhlPst`DI?;^USlo{sqp#9eFK^dPuYSH{h)X{V_>faYezq>G-1?TDP+*OfhNmic*m%~$u+Zy#k?;t9y zb+%3NzsjPT+Q_~6uP=M`ri$`Poh@$URYo6w_u(=dAbps#vh>x=yt+ruo9#emIB#TS zIB&T70^ji6K;Nj->o%;|Y^AEoo!2dAJ6T}vzlz~en`>Mbg~rNz%cEY9-Mg+lKR4fO zFCve1{nkUSYV-rd^Wdo01h7QCOD;0clX@;(i(#SS;!xyT$o*s9gmJf+XR~ux)j#92 zvK&mqN~+Rx2MkD;0Rg5%&e)dtLc{BW7fnu3kFY|J#T)^q8_t) z^)g}p)CIF9nC0Y|v#aO#Fo&TBo9)9S3FefO=Pc~gqi#-*Nm+eOsh&4+>R@wRdSU+_ zvwF@lN4AffR5$0i$#c?sOiAxinw{Rm9Pb=F(OiKZlV{b`)m2Za=`pjWcFO#zgELKX zpMO0>j+rJesGT@}+U(jMb>@(;S=O00$v}$C&Q0vsz@zinyDvQQ#@=}#^Giyr%;w2) z?7jt$QW=U?8F@7`@9IK1g++zq>fcspnoYEvMXv@M+WM`6Jli4!>m{34BD1}yH19~| zCFOuU@`+6X3Rn`z^9pA@3my&2EGH zZo|FZ4!&tcvuDrAvYbWsKdwuI7w-mdkc-VZ<&=*3#~Qgs=C#4R+REn4xo_OgnS=&h2KbbbPh+L}s;*eil7Pa4(D@P(4yiytO(Yvj~ zN1KBkxg*SW*u6y!o_;)ycoZ#Yi`c~@LoBAXfKok7-r{jNSG%}$~Ms^2$kxXUL7BTpf&NJUv;Sa;p!@nBao z6gfBZdcqmY8!WvH^WIs%$}+nak?R+A50sUc4lgu2pXQ+`F|V5DUl5Xv*hfsT4TcM!;>4l~vxZ-nZ1 zz4G)WHp}d&aMR4a5V_X8{f&Z7|N1`N*~YThF4x4}$8)Zec{^lo1J}vyvYK7N!rVgVg{v%NUbmc6nO7h8 z3-kPJaB}y6W$tjZE1h5DoW$%&N6s$td?^?mt};i=%$=!csOM*nmvIl84TpXy`+s^Z z>(9v?AE=P+V!cZ_$-ll&=D}@n46wob^T_*s_Hf-DGVTSvOB+5jd90lK!@Rq4?+>%v z7j=KgOQ-DngeyiDR+{fby$-W~m{otIA3otM3&KI)xC&ArG zbG{Yzgfj2Q>+c~s0_+^7k@qs@&_sAxsL(wwm>cDYJICyZR29{~Z4vIg^ND`r8#y|Z z&Cwy*Z{&{R%;cSmHQm|v$yJoyHck?~Utx~A7Ur65h}ouBI`>oLR263D*c?pI0|wl0 zQ9n-cf9i(_@@gh5nBv@{vJ1$Sl&4}S$F=1indUp(!UD5rXLf?a1x2BX`t|s3Rhh_^ zqYE5#KWd*W^4R1Sf-_A~>!ist~TmMkjzcJ0r z{||3X<!X(+~Gxa{bHFKejnp>{n#TfmzNw`YIO` z7MXWv(T5xA-=9=eV$fyg#Ha)(82#boc2 z6LJx*`pB!Ob8kf-M0Fti+l#QfNsb(7<9wYDci03FNkw*N_r8)3G6=A}t@5%fbF_OtpmSdlf%yHle(&%7^*dc(puBOfjC!s+hA zxZKRuclN{dc@%YPq96PQpT+3StST8%Qaakb7uZdbgZXm4?w$hoOO82oZ9bTDJ~VN@ zE&D)xGwLlvgQGFd)sth$@`danIYEw&I$yX)aOF$(iL#;(jOw|{5%~i1l!!i7)o_o3 zcQDSGnmadgy`1Njd10yymCIW`W8b{J_)pKTsKd8Y_fe$*CNp}KErB8M=|vy}HG3W*Q-vfLxD&e_O;PUj2v?J$=t8`_31D3PaE^fSV} zCgv=hXJ_R8$Sn#LmqooAyFBFMIyv9^&#mg;&}a3IY{X!nC5JNItJYvk5h^q9yT_Ov z=>~wKuAX~8xK9jj555Jb`GolB1DeizpMp^I8w=Lpq;gH7_7lu2o8G(b7GJ*YzMSpD`>j$KE8p2YQZZ?AKInfubYuZOGp8t2GQvD_^UWbKeGTGU za#M~zdHrKsRBAr9Gush!^fXiwb?8kVorVWJ+?@{hJ$Qpx!zfvDn9#Y&^+#FVPaC*0 z^>4Tu>~YAYnI}Y*xs_a1IU9G6!TE{}t9u|b9A>wcGmhF$4=*2K9y|9bS!f*8ACVg! zGJDQ!Qjc0w4%o;`qkDJN9}AVEijk8>4oAyA+OTrjBR=ZhZm?Gu3By= z*WB?1VdtgYl8fhO8rY!`X!;b5-g|NN9Cf+5#d!^m0LiYU`$*_L=Wac?63%9!;y-=X zsdpyVH1fvC-4SulR*pDwX3on`NvQs(7UbbP>iU`2mB=THau@T$Qhy%q12(#}e1yL1 zjJz?(GH)oOwkl>*#3vpN_lye6XWHyk$j@3>!*X*6rgxR2`Js8U((`9csF^g$d~jFE z50pCx`1wKcZvXjkzx>2-qWSM{^T+&>$I|4)B&(A|{Ubj=pOf5mRs8C>vtrNoofC7e zeO}`=-t!w>=&?cr%!#Vy$I>m2`Q1#*?%$)hr`b&?v0_qv#c|&F*tEt?JpoTMZ*xxz zPfJfLPis%xMjbrn_nH3jCptB@e)v231YY^!>8L+m{i%PFSAKRn>W|m_+_d>+p{PHN zE%R$=&hJOK(fz*s_5rheUw+SlnXhE&wajk{Mg8$w<`<5l{&+3<{nz?GUaR4+!gww7 z`*=}*yq5Xx*r-2V=i1c=uVsGeChCv*CEln>u1~=H_O0`a3(oI5q?y~>E9w+}^L6N` zx%8-+pCNaTI(M3Hb(*BFH~;Z7!swTyhA&QLzc1>AD@!iwGxJ}3z%sv3>Moa=pG}u} zt1Qhg2<|iYz05t$eI9RqD`}7{O+Q7Ka*sDMcca*BWNwf=KC(2cILj8YG!JrnS(>}E zt9EfHr<30|lI37s=IF9amsPr)sLScPoU6;_x?HWxb-KJ-m-p!M0bM?-OY=*x&gDL* z%a?VzUzhLd@?%|^Ut)Dm|Gh4M)}{F+Rj12usL1V*zeQb^=9f^NWfNV>-9U_L2kSCdmxa14)n%0~Pts+zE~n^nmM-gbxmcIWb$OO9&)4O8U0$ZkD|C6S zF6H-2<@(>D%bmL1rOU^3xmTAj>hg76zN5>Jb@`Ppf6(Qxx-=U%=W?9iOOpH1IF!qk zUq+H;D_wTbWj9@B>aw3MPtaw)F69@@Wc>2i%O*XweVF1P9O23>B~ zILR@YfiXLFrxb#~R+N9Th&N9vrY zbC%8pI+yEwUgtWUZ|U5obFa=rI=|5Qt&I; zW1a5byu0gn(%D1j0G&g1j@3C$=UknObv~o>C7l~}zN>Sm&X08-(|J|G$YXX#vNZ?oNAtMdbU1Ml|7I={7d zf!zLCX9;`X!0jqJAGCjq?Diu%->`p(>-GmaZ`eN$b=&?uLe_a#;o!{FIlV}*pU}C# zSg?=l%w8hcx9RL;?_jvw>!Wjp{Uc+y*Xle|F4({7EM@PAxIeF^^WjRt9;fpydxy>a z`3{|bRtvUo@3^>Lzh-c@(mAtMuovn)P$$?YbVln1yRgpA4T9ZI=QE9hy-w%%O@e({ zXPM@~uAy^CMzAO7e7j|^cj>&@I@k$qg0o@U;B2Gw(e}Y!tn;9~!{z>7U+K)%IoL&X zcI_JM{yJB63-+rzf9xLY-*lGi73@284(k)_Njl%@7wkPc|LGs>qyfR%_<`VTt8>nS z!CtEK@Wa7AsWZ>eU>DQbZFsN;>U@4=uwT>p)97Gd(^+9`uxslaF+SK+bZ(g#?0q_8 zrUW}hXVYoHZm)Chj9@R<`RS}+f1@++oM7Lsv-{j&57POpBv5$ujS=RFhbr*$4%73^mKe5bPN`-`^PQk9Eeq8SET7Gd2bL9-Rv|2YaQ?&+Q$3=l46E z1-Ayfw9ek|2Yay2m$wIdlg?ju2Kz6aRrdtDfzGk}f;~&;_K$-7iO%=~!Op3(<-uTg z(fQ=zU_Yz#3;P*6?*9Iuv(RV3E~~Te@n8?t`O1l4Z`OI~t6=}Fv-+uEH_|!&bg*aZ z+<7M0hjd1M2zG9rt1iQS>`!5B1xX$(V6Mo#^?_Hf& zt_J&Goi%?Cb`zZw{|NSDI(OR#Snm2qbSC~2>@=Ns+vgnIpWml*iT!{ew^!@@Ixg7f zbQZM_(A=Njp>se&ut)0LU_V62{rP)3ui6K4ZiiBXvzGl>A-9|9oNPZ|$nD2}L?U{i4oO_QQzWzM!*sdax_$e4uEsN9){JJlNZG zUbi1ua=YCnO;JzNK!Gu&x^@7X$^)VW0GvpQGnOpP(e zcKxW%d^+vjpsZe8r@b4KwJYn)`h1C9FYEIqb~aGY)M;<#vmU;a&aOJ`%~@8TsB?zS z**X{KT%_|EozLrBtMgTzn{~dY(_UR>-Tq#kKk7WM^RmusI&bQ<7u&4sCF)GonOkSp z=S}SISxnnlXFa?<8?w&II^EC8a!=2eI@{~KN9RzTBXv&DIYsAeosa8WtaG`}*L7~v zxlL!*=RNH4ex&`0&d+q7(D{eXzjeBw0pad%g3cT|bL&jkSzPBGI;-fct+Sra44tiY zcF}pC&Up9qPPCUxp6)vB!@#WjaYhg4K3^G|!(I+}xC+A`d1yqh-Z2%1j~Eu51Gr@0 zcs?Sgg8NSIm(v&~ii+ZF9ene|^0``tZUIG8d2{o&l7x&KPq zuZaEn|9ZHJ_Avkb@!tA#bKLXN{a4O@CD^a}_RIY@{((@|W&4oK{iKqtU+(dBv0vN= zyO{Mkfc5tJiT}9N(Za2_x7BX1rWtX!=Ulnlbhp>fesLYU81q)uP|OFn1TK#LZx1)T zdMM^0o@lrHnR|}h`gpI73&jkvhjWkDbsq1`TdrdlV@}r$#iY9n`j5vu)%LBo*LR}* z;7n`o_Uyyo|J>ekyUca$Voc1P!NX-;w%_=(#di7D+Z%Dq?YXZcaR1ibavi%ElihCb zS$kRJKW^_O3%B0hbh|zGbanSHoBiVU-0NO<9p}OQ_nLi@xLonzvisfrnftXYZHU8t_4q0%Q`LC4yge?1T_CNo*$Ls$4*nZu5|K{HE_swa4#{K)+E}P{cc4Yn6 z({8U8!%iNTJ8yZm$E>i2n`|-7x_dq3ZqGe`+~eeB!!E`YG=KNG3;K`SGm`)1;a1rF zyT}9C$;18U=lu+rr7KhO zG;MSxwrEPzT{otuZ_3zpBl7yL8@tnw-iRv_Q|7NP2b6q05 z{^>(&TUsl!>qgwrT{li=KXxOoQcT&uzHD=8a-_}GylLS9Z7#(o@4gXJX?13stCJIV z-?&(D_l?t&&-Pl?rp=|81lvR0!`ZogMdr#D?$1_atZaU^*T292^Y88(1y}99arlYv z26l<9e|g)K0Y#T)`j;m++imyirE8N)+Cx`7{(m21vfWayvIFL4?6b!=D|23pefHSq zHJ_Kc@5brvH?wZh?n7)$u|Iq5yK%VEUjywk?w22%+UQENww;U4%pBFy9zOd%yKQ^; ziu_F~r@MRNH=UF@DPwYr$<6KWGSn6KEAz_fmJ`~z`#wH%LdJv^6YWng4sn0dxoDr3 zLo?m|bocSU-`2>?kr|^}jQTIPRsTxwiuP1%Ff6k}hFvdYfA8$OZ|tu4ss4V02DEOm z)BaxT2DslZWc^-tpu2p3=1zMY&9CGvma}KlfTu$@kF~kF{T{o$s&;$zn_t;9yne=^ zUOR5YHP~_EaLkTdZ*ySh;5M^v=R(%+4efSHJz%#R+IeGl_DU_>Z9W^^W`{OcyAElU zSuW#%yS2~`d#v2MDg#Pp-O>@=+u;L>W$du~#-G1ApzweB^GgHjWZIvHYG>4GQKz|k ziq*-ilTo*M-4^b0OfmO-inct{%bp6Az8l!to=Fx!=Ug{>> z7YA#`JQ`E;<4c8$evy*%(arZKJf2wR=_;q~&(2k^xnX^;VwYEj`hDLyPt{LWg+r5b z-rl9lba+jh?#6>|I;6B_-%Tf^7Y;uw0B^UiTR&Md~?@@Piju?((S3l z;sf3+bbRrs3F|wY9`;MGi-iwP9K7GIJH?AcV!rJkINDwDGd*=+Gvgdp7 z()GEXD#7*Rnhwt#kujph$mV@~Z4?WJq)EiVb~rDvdfnaZ&? z>-Te6zn69|5jpyr+|$|H-ujZziI=YKnVA^}|DP{gS+|&V{k2)YpUe8aw0p_Q(Jt#2 z>tx;HGg8Yfx|i4L|I2NRB%tf9BZ>~>0H+Dr3T$)w-~&{=CqfDmBDRxtd&_S zqjrnh&40*x-Ph{JHkU#LIyZIC&s$%X>f7^lYo*l#PsH6k_RWo}8-s`FT(m%D+~vuQ z-Rr{_u1zZb|9YKRCbLXN*%oF0^LorH>7Lf^wPHzo-FI<&$&8XMO8w_`;)oxDmqYh* z_v_D@4Hk{w*YwoDL$l_dI+0L66q@W_&f2aScXr3RIV-3A(mwZ>jeE9EoAqjF^RV~3RHTw(K?>M;mp59+BoB7a`eN~fw zy>?{jqJmTBpFXmn(AjqB4f+?zcez>jwD(h-Q@upuUu)Bb=fx8USOBgd%8N=UFwn1=4uJwU9#5zof=)~)y^)TwztjOzv*R{ zdb&SpbY-fmcCK#MxwyO3&aNNVpq0HXKb_9YWAK(QzG=(MRvGpkMDDqq<>=Ozrxuy@ z-P7xTytQ)rgO{FxS?+Ir8K|74zjBuTW&cfob$jdbzrQ>MFFgaZ%-`z2Ox7*lmUWA~ z6}a`~DeZr`P51ItdQi5km#2Y)vRC0Gk+Vfky*$16 zy?M6R>+WsK>BnMf?mQZkeY>5`akEM<|5;+n$s=RB?M@pp=-NeR_ExX=Hv9efvTv&$ z={+O7;A;Gm2e;dGpS4dMxc4vZHbcwo^Ige%?H%$;?mf?2{)-L8kG6NfV?&V<_C9EA zte4x~6_1Ve_ZG2tH0u_%%dPUZvWJh2^JdxyLg8liUT|!id_A+0KRv&#hN(`+PXE%x?2SIMUACT?|JK+SBFd zaAdzdk$wqBuGmxK*KlN-sks!6gzYh04oCXi<7*ig>0?i$R&kLUcCTBlPQuWp*~&L)x9l_?8e)+1ezU((j*^jq z_O~697FlKYWoTNYw%xN~X^}zpXosgos@W5HL|SCIJ+VfnMP9aN)u^;c6?+V$(;`os z*fD95CH542BrVe4w2n=S+-XnwacL3vrS0))5zn6C6Vf7`><&&$i(Ig)PfCmIwFjA; z7P(?3rlduDyOsJYB7N=AHdqn)+-|Jlibxr|FO643{;?-(lNFI{_5^9VB4S^)h-tPW z(%7C7ckhZ6u*cALSL9K9ke=rwU)oDRuk(>i`-}BHAL(Z%`karfu)jm!^O1daC;FX_ z)Udz9{pTa&?eX;Vyfa5$-~~F&ybG z%(ExsD0g9t-O6NpmL?Rlr|1-SVTs+&RCnRLJt3yK3+s#8&(3!j^4arshP$xS9(bm^ zaK!G*EO)`T2Y#Z5T^MA4<0svPNp^1+x(n6pFSy8E_{sj>i`|6|_9!0dV;7#ZC*4?g z;WxWu_A1jJsXY%v?m`(uU_Tc-CZU-#JLNn?8)f43)9Sm{givV9eYmr z?m{&y5qDv&J+1_IVY59W65WMzcFRfb!U=nrWOt#9J+18rSH~pGve!PT?!sAndS`PN zKC}nU?k+rM50k@PSYXE7`$P$0dr8UZF7&XH%U!S^vuNK+X&0{A<8t>pp^!cM>`M(X z2~+IO$GQuR?NPXIwN02}FGX?gg8lvMZ($eQcVWf53#;t!$=r8EoKtQ_N&*1XMTl^Cy#WLE3cW)W{nuH zf@WTuHDkOxG}CO}Y5%Ww%{(?M+1;w7o!f1@UzN3Uxovl>igr%7?VeTDj=F7kt(tZY zx9z@F*Us*?-MJdt+1$2!S5rIHZM%DSYNxnu_pg?AvhB)t|7vR|xo!8aj&`EkcK_;X zC%A3*?=J0#+jjrzY5Q*5{j0AX@3!5)2HKw6cK;e`$GL6yuaUNWmvh6)cK;e{$J(x9 z_pga|$ZflSO||X$pFPfg2y+j6{^vMgoV?q!{y%y-zOdH`UNgV0dwDY(>ri47ADIsGu5i(92A>*|XGC><56SWaCNgE-PwGlE!8zED* z5i(61A=9-HGD907Gqn*iOB*4NY9nN}HbUlTBjhn{gv`}O$m7}wnWv4A`Pv9spdAQ# zIK0}P|2clJ_k6s;fsnHH?vM9`@8mcki@nwM<~K{o5?xh7mTF4KGEE6tt|=i;X-de` zni8@?Q$kj1O2{*s67sAjLRM)b$MT`sy0G4Xd~n`ZG>#pM#$^h2zf&rA#Z9Ux_MIFjWQ(`Q-p$Ms@}90LAzL*iWSgdhyss%CA81O*c1;P{p(!Cd zH6>)1riAR)M93a(gzVKu$Ubd^e5j3(kF*i8UmGDGYa`@JgdEaF$YE`S z9MML|r`iZPs*R9i+6ehf8zG--BjmU?LcY*O$O&zPe5oA>c_)0kn7qA`CS_! zH?$G*hc-g~)JDi(+6cL+jgY^!5%P~VLjKhbgq#c~+DCUe9Dq;D+q=E->_WEf-EyCOn{9iyJi;z$+ukitU>C4$@0KUB z^V_y}%ahpoY}>o#$?Uwg?cMSecA9N_w>*`d$F}>pCL6*2abea6HrWZeT(G;CgOJk& zyN^*q)CIefISDyjuzQ({klh8lo4ECU3lI`quzOmN5OKlo>1_nx1-qw(2=Ol1JuOV|T(EnZPKa~C?r9N1*af?% zMG3JM+{Ze_2q72jo)#wD5^?8Q8faJsuNIDgMgx% z1Qgv#Kv69MifR*3REL0~x&##6MLF#$zQ2qJqal4 zMLlgS(SrmOJw!m!!-POl%TV}h z0}|a}pRMy+NzoR27sneM@|`cIXn4r`+ddbWrDz1#m!gquDH_F=qS0(A8pD>NN7zy{ zmMul&*itl}EkzU9D4Iw>(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&>ECPxiC7@_F z0Y!5ND0+;5qPYYVJx)N;JOYa56Hv5(fTAY|D0-5BqJ@M&(a=!1sJ$_ZmUHho50j#q z_Lj_B6!M)fr)XKoYh)jgXDM3F^`+=3wiG?hmZBAGDO$;vqG#Ar^ekJ7Rvie4q4XafO7uMtqRk$|Gt z2`GAlfTA}ED0+*4qD=%8y-h&TW&(=dAq0w+gu(+1Nc6mWzi6oxWy|_lEaW?1PSLiI zH`~5Wlcnf=t}jI&u%&1_TZ(qDrD!KxigvN3Xg6Dm_OPXBFI$TCu~GCP0Yx7XP_&Y|edo(5Di`bBTS|(`bA2hQz?Pyr*iuxHEk%{sQdF5OMOD~R zRFy47)!0&0osFUz1QgXIpy*BlifR#1RGWaJIs_EeC7|do0*dMpP*k6Qq6P#MH6);@ z5dlSw2`FkpKv7cyikcBn)SQ5#76cS!5Kxp!Kv7FVpr}l2c(MVBeq`Un;+2)6OHNU% zSl{__irU6{&y|s)c3fYI+Owso16ztZvZbgKTZ-;sOHpUG6m?-sQCGGU-OEN%Hv)?8 zBcP}|0YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpy+-Aiuw~!G=PAjfdmviKtRzT0*W3a zpy(k2iXJAQXfOdqLkK7uN(dCSi4E^HAkjbEJJfeeQM!BcHZ0b6zMP^_vEJEoQZ$_4|Qi{sES4>OoJDJUwQ}lGKSN;wuTEX?DXeC>Uo?%PTvur6^ z#g?My*i!U7TZ&e*rRW8=6urns(Ha7ZULv6AWde%U5>WIC0Y&QwC|XZI(W?X$Z6KiN zH3Et@5>WIy0Yz^RQ1m7NMQ;&Mw26SCw+SfPOhC~)1QfkXK+zTgirymxik8QQ+Zm8( zXZy|!?h4SQA4pLbd#~F2 zHr98(oT49My?3if(T`kTiq5j7=qI)monuSUdA1Z?U`x?OwiNx$mZD$SQuHeuMVAOD zx=cXP6#|NWBcSLi0Y%pcD7sES(eDHl-5{Xo4+4t*B%tUo0*Y=DQ1mweMgI^`^e+KL zF=2h!j-n6&MX>}Fg$XE%BcRA51d6_k4WBX~(Q)<_4)1#@D(F5186WnYFQ+Im?EPC! zijug#6eY8zD1|LWscb3A#+IV&Y$?jYmZB(IigL20C>I+=xd|xBLqJg)0Y!NUD9T4b zQGNo73J_3Kkbt7w2q-EY3 zmZGX`DXPYnqUvlZs==0`nrtb$lZ~QU1QgXKpr{T3MRf@%x{H9KdIS{JC!nYS0Ywc7 zC~8DNQDXv%nh;Rblz^gU1QazVpr{1_MHvJXWfD--l7OOC1QfL zeQYV}&PGuW0*ZPPP}GZnqTU1)^&z0BF9AjU2q?OrfTI2c6b&GtXdnSa4-il^h=8I8 z2`GAqfTD*9C>l&a(GUWPh7wRTjDVuy1Qd-R1d7^)!y64qbdLR_C9k~{)pnnP92xeV zFQ@2{uy>@66piKjQZ$Y&MdR60G=VKe6WLNUi7iEw*-|uxEk#q=QZ$W?qUi(_%^;v? zCILmW2q=1#fTGz16wM)^=rIC{<`Pi!H~~fT2q>CQK+ysMik={#=t%;K77|djh=8KS z1QabHplB%pMau{%T22TQjSh#e8<1!j_YUT{_fTH&a zfua@Ra2*2@E$%++xKfIi*jHh_55m6l_A}uHv)>T5>RxFfTHUJ6#Y&>(G3EM{ve>}PXdbmBB1Cd0Y!fkQ1lN0MgI~|6ceWp z+ffuEpeUArqA&qPaRd~31Qf*+P~;O(6d?qPehh~{G$7G4?t}ZYQnb~+mhUCR`OcS9 zloIEiYa&IdTwjW^v85lyY(J%svh7(XUf`Fot1Qd-TplCE9P}DIl{FDKSu5#~CcaoyF zouV;uzVqc2jgRx*Ybiw&xV{ukWJ}Q`wiHcfOVJdz6isDI(KNOcO=nBd47L=_WTR*n z0Y#4zP&Au>qB#T3(Gvs|JxM^(LIR2w5m2<4fTAS? z6fGs7Xc+-T%LyoYih!c02`E}Y2o#Nt3!gS1(LZc@XdN3x>j@}&m4KoR1QfkSK+#45 zie4w6=nVpj-Xx&tEdq)*5m59t0Y#e$D0+v0qIU@>+Co6ldju41C7@^<0Y&cuP;`cXqVEVO`ksKI9|$P=kq{`_9T$Gk zfJE!KH)4CFXj-z3vvI!jlj^ebD6F0rNPGFytSu%+lX zwiI1uOVKqpimnq-^g97XHwY;DgMgwx2`KuDfTEiO6#Y#=(LV$f{YyZR{j=<+?Fk$g zLQ#l-qF4fo!UPn>5m4k2P!vxu_ZYQ9q1OY`Q2`DN>Kv8J|ipmgB zRF;6Eas(8WC!nYT0Y!HZP*jl+C`$FhHw;L$j{C;6Y+mq@ejE3R>`I>Rd^ttcJTG5o zDXPx(rKkp5ifXc@=uWm2)nZFgZMGEEVM|e6wiMmPmZExW6xAo7r~v^*4GAb}L_kqv z0*aatP}G!wqGkjXH7B5`1p!4F1QcZwP}GuuqE-YHwI-mb4FN@W6HwHafTDH;6tyRy zr~?5-9SMP=Dqi?50}`!h|0Lh5Dn&o2q+p(K+y;SibfJpG>U+t(F7EYA)x3H0*b~G0!5v@@N@$b zt?0h*x{DMYbU(dnoaZ}VPSGUKd$F4oP3HPiG=(iiQ`u59jV(pf*-|uvEk!fgQZ$P# zMUS$jXf_)~a|kGUjDVuK1Qb0^K+!w`islngw19x3CkQBdl7OOx1QabIplC4xMN0@M zT1r6CG6IU06HxRN0Yy&}P_%-8qLl;`JwrgzvxGp=1TVbbfJ8^Q@4KETMZfQ1mtdMVkpIdWV3bcL^xkLO{`b1Qcy0plBNbMeh?(^Z@}y z+X*PzK|s+?0*ZDKP_&y6D0I zz9gXND*}qXCZOmf0Y#?>DEfwgqSFKveM>;m83KyFBcSMe0*Zbhpy)>eip~;H^b-L^ z=LmtKeO|be0f~O-KGFE06oo=I&U?P|B?u@gNkCC40*Xo#P*jG1qOt@Ol_Q|2 zJOM=&2q?OPfTD^76jdUis4@XXRS1Ei9P!~Z1|&K<-QYyygOBt-b#KwC#{15fQ&cnF z3lET@JGs6T)nZFgZMGEEVM|e6wiMmPmZExWDXPzwq6Ta!YRE=WBLa#V6HwHIfTE@Z z6g4BDs5t>eEeI&eAfPCdfTETJ6tyCts5JpaZ3rm3n}DLW1QfL+pr}0oMI8tz>PSFQ zCjyG@A)u%;Ay8C3K3vLxL=U<*Vl|}by!#Ynmw4a#a*FPY_gXw4Mcui+6!l&o2q+p(K+y;SibfJpG>U+t(F7EYA)x3H0*b~GP&AH!qVWV2O&|n{?u`#W zY(Sy~-Fw&Fr08+?Eo&3wedo(5ni}uTe^831aeXP8&X%GXY$=+_mZDi~DSDJGMYGvb zG>0ukkFlj_E*nLU6HqjdfTH;X6fGd2=m`Rfo+O}XApu2;2q;=iK+zHcik1>kw2XkF zgO8Y!ypzS-!*c;ESQiVnnk1%^t| zCtP2O4zi`_5L=24v!&<=TZ%qqOVLrb6dhwr(PwNa`kalT;{+6aK|s+70*byQpy(?C zioPbG=p+F}rwAzehJd2e1QdNsK+zcjioPSD=z9W+ejuReM*@n@5>WIL0Y&EsC^}C- z(FFpEE)oJo`{Tp)4M=pV`#RdkQZzkmDEga#qJIb|`j>#B7+)W@qbNi`Q7i#PVFHTc z2q^LhD2gYb$S0sELO@Xh0Y!-f6eST*luSTT3IRo_1QcZ>peQ>5ML7t8qF>{~GYv>| zr~5kEB`NyJ{S(Ki?>k>kQ6ArWX`~dTaeXPu%a)>iY$?jmmZAb|DJsa8qTAR~RERA_ zh1pV+&PGuY0*ZawNiF18faV@pwewiGpBOHo6%6g6T?QDe3gHDRNu zDFH>z2q_dP2qP$dU7Xpg95>Rw6Ay9OuAC8VOMI+toqFPe)ty9#^_nj}NsHg8$87oD- zxV{wiW=l~YwiNYcOHn_z6y493qW)|t8o-vKfov&yfQ_O-1Qb0;K+!`46g^Bp(O?3K zh7eFRlz^gP1QZP?plAdEMI#9)8bv_SXab7H5K#080Yzg8C>lpV(Rc!iCJ<0Gk$|E} z1Qbms1d6)*;m!smn(n>;+e3;jq}!O{`_7kBG{g5E881aMxxN(5VoTAZY$=+}mZCXq zDSC`8MRVCw^f+6J=CP${J{v^~2q=1jfTAY}C|XEB(INth786jkgn*)@1QabJplCS( zMNbh>^fUoQD+nlBNkGvv1Qb0>K+!4!ik>5&=y?K)RufS40s%!Y5&}ij{O~gdBs$i8 zifFnNEpwl{UgP`Dms9kL?|m>)iq>&`DO%5#qF32cw1F)}ud$_QBU_4IXG_r=Y$U0*c-vplB-rMcW7{dY^!z4+tpQPC(HP0*ZDL zP_&DHqTK`(?IECOF9AjS2q^lHfTE8GDB4d56us<+zc(P!O76S&*GkbT_xYlaec$*-~_rEk(!JQuG;Hiauvc(Q&pEeZiKZ6KoWHNkGw81QdNu zK+#D8icS$w^bG+;rwJ(fmVlx&1QdNoK+*RE6#YOz(T@Zaoh6{?CjyGj5m0oVfT9Zo z6kQ~s=w||oej%XfS3;oZ6F*$WfJAraG&l#PXoCAz{!6~^d^tr|eJ^vG6kX%`Qgody zMZdG9=muMg{$NYdpKK}mi!DVr*;4d3TZ;Z+qv&4(iee)AkPJm30*Yb@C<+r$6h}aj zM?g_L0YyFmMG*pu5(p?tB%mmXfTCmqic$zDN+qBu8v#Yx2`I`zKv9%{qMQU2k)Es6JbY8nC6PAzO+Xv8AXnTZ)>nrKl-eikh*ds5u)& zEeI&eAfPCdfTETJ6tyCts5JpaZ3rm3n}DLW1QfL+pr}0oMI8tz>PSFQCjyG@A)u%; z0YzO1DC$Z;(Y*u|bt9nYJ_3rm69PqbBH^0`BwE;gq+eHxmgct6BjP(>PEntTciS8( z>dW<|s2^L3?q^F;f3_42U`x?JwiG?UmZCvyDSD7CMGvu2^e_QMg9#`aLO{__0*Zza zP&Ax?q7eiXjU=FG6aht}2`CyvK+z)v6pbaIXdD4W;|VC5KtRz%0*WRPP&Ao^oZ|#IYo~~ygqZKXg1fEqB(3SdW77aD6FyjV(nR*;4d6TZ-ObOVOKbDSC@7MVr`C z^fp_HHnUOm4gp2)5>T{-fTH&ZDB4Ou(KZ5#-Y1~w0|JV+6Hv5+fTEoQ6zw9QXg2{x zdk84nOF+>+0*XE)py(q4iuMyw^f3WN2M8$ogb*lN7YQFUAkljx24}q#9drMz=wQTm zzMP^@Bi^qIr06Kum!e~ADf)~pMW3^!=r~)7zFvQ1k-L_pDH0*bB>0!4=-;apFcqV?|ku8&AjefKSEzeRlK%PIOj;#FHHMK`#< z6#c=LqCeSE^cP!-ZnCB5Z?+Wu!iYK7R zC!i=oKv4n#MTrCyB@s}ROh8cz0Y#|<6lEizC_4c~IS43<5>S+rfTCOk6y+wMC=UTe zX@o%0wMe+D0f}x)H#pa&=$uoOH^FzloT7pW-nhk5bQ{-~qC#vbD$JImbhZ=~VM|d_ zwiFd(OHpyQ6y462q7rNrl_a336ahu02`DNrwiGpIOHm896lJib zD3gt%mIM^FBA}=>0Yz;HD7u?~qP7GSwIiUYJpn}>2q@}EKv5?GitZtxs51dYT?i=Z zNz&{`Ury2e z37-Fy6!qu&QZ#@qMFZJV^Z;9m2C=2+LADe<#FnCm*-|u^Ek#4vC>lyY(J%svh7(XU zf`Fot1Qd-TplCD!MPmpkdW3+Yu>=&2BcNzJ0YwuCD4Iw>(If(jCKFIJg@B@|1Qbmp zplCV)MKcH}nn?&0^-TzuGa%8h`$)f^6xDLCi)JPG&X-g4Sc2DTg%r)@`cm{bTZ-nf zrD#4|iWab?=n1wIJ;|1$g={HW#FnDPY!odaplB%pMau{%T24UGQv?(}O+e8K0*Y1= zQ1lD|Mb8pYw2FYD=Ljfzo`9m&1QfkMK+%f?6s;kk=p_P*UM8SuEdfQZ5Ky#^5Gb0R z5FTbgqD|aC9-1RX)7;ne*C+VSms7Mc!CUx@6ur*%rRWW|6urroqPN&mw23W6Z?mOn zGh2$@VN21wY$@8pM$vl&6m2D-Xd3}V?-Nk;0RctZ2`Jh@K+#SDigpoDw3~pUJp>f( zC7@^@0Yx7YQ1lT2Mf(XT`j~*C0|XR(LO{_$0*Ve1P;{6ODB6$^e#d}BefNFWuSwC@ zPSKGB-}!QiK1=XUtdgS7xxN$~XG_r+Y$-aymZC4&QuGyDioRw`(Mh%xonlMTH*6H0 zCZOnB0*cNMQ1l%EMc)%p^aBA!KN3)MmVlz42q-#7K+$;uiY^dPbdi9fp9v`Xg@B@8 z2`IWmK+$Caimnh)^cw+1R|zP(MhFxgO$h&EK%&X+)78hMD8s#zbUnd$zMP^z6THH! zrRXoNFGV-mQuH@livD3s(Z6gdib>Q*?ot$DOHnLaio$Fuiesb5BcLdrfFhrOq6h&+ z2?P`+5>S*xKv6OQMJWUnr4mq-jew%;1Qg{UpeRZ}QBDGiauHCJn}DJ`1QewaP?VQ| zqI?7to8<6Ny_ld?oq^PI+F*F4dedo(5DxB!`dr^wgxxN$?VM|d_wiFd( zOHpyQ6y462q7rN=D#@0jQfw(I%|=lf0*cBKP*je9qVfb3RUn|~4g!iQ5>Ql$fTGF- z6jdRhs44+P)d(o6PC!u&0*Y!9P;@5&MYRYhs!c#q9RiB#5>Rv(0Y&u)fuh?I!*dKs zbdZBnC^7g*Kh=FrzkZ_cd^tsp6TNjWNl_E7FGWq+Qq+tsMa|h#)PgNV8Eh%aWJ^&? zwiLBuOHpe!irNrRbTWfTDW| zDC$N)(R~CIbtj;x2LVMr2`K7CKv8c3iuw>x)Rzz_YM2;4Y(S#p-5aq+QuMe})GyI@ zzMP_giQeV4QuF}Vm!d&zDSD7CMGvv1=wY@L4Q5Nx5VjNzWlPa8wiFF#qi6&HMI#9) z8bv_SXab7H5K#080Yzg8C>lpV(Rc!iCJ<0Gk$|E}1QbmsplAvKMNAbwPtOK#Cr7{|01EqVIe;Me`E98tbKKKG&C` z1#BsLf-OZ)vZZJtTZ$I3rD!o*ik7gYXenEYma$Q^oPeUI2q=1*fT9%y6s;tn=otcv zo+Y4Y6#+%h5m59z0Y$3`D0+c_q8AA$T0=n5O9T|XOhD0E0*YQCplBTdMe7MDdX<2p z4TM0^+{AD<0}>sSYH%KxqTAg&Nv|dP&X-g4W}-J?gA~2R^`&SNTZ-OhOVMVw6urZi zqIcO+w1q82@3Ez5D_e@Tu~GCs0Yx7WP_&(Zq8$Vj?IfUR7Xd}P2`Jh_K+#?TiuMsu z^dSL79}!TrpMau|2`D;1K+z`z6dfd>=nw%#hY2V;LO{`{1QZ=51d3iy3_ou`qBq?K z_isqiIH%}XqVIe;MPDR(yEaPE39c_iU$Uj>E4CDU&6c8*Y$-a$mZERiQgoUvMc=Ze z=nNZ0-w{ysJpn~O5K#0Z0YzsCDEf(jqH_ckohP8^0s%!A2`KuRfTCXrDEgIvqDur6 zT_&LD3IRpG5m0oMfTC*z6kR8v=yw8&ZV&=RpC^WYG9b}C?w@@em!cxRjXx57=gTSj zJJCycQ;PoK`cm{STZ&?m^pU$1h1gOQ%a)=rTZ-b?Qsl9vD4s1vJ{v_50*Vp{C`u%t zD2afgWCDs(2q;P=peP#wMcD}`%0WO;lz^g~1Qg{WpeQ#1MR^D)N+X~sF9AjQ2q?-= zKv4k#iV6}?bQ>X1^jBiIf&qy(D`s$RN>Rvt@~BXf?|eB$MU%WXo1~~1*O#K=Y$>{( zEkz~RQdE*HMWxtMRGKYCW!O?wmMul)*eEJbKv4w(itZqws3HMHl?W)ROh8c;0*a~< zP*jb8qUr<`)gYj#CILlv5>Ql&fTG$26xAW1s4f9TcM(ujkAR~31QazOpr|1sP?Vk& z9$`SDd(sU~k)+@w{lbn^qa@$?a*CQId5bqoQFE>@MJ?D;l);vwOtuuYWJ^&iwiLBy zOHmuP6y431qPA=lwIiUYJpn}>2q@}EKv5?GitZtxs51dYT?i=ZNVxwp@ z0Yzg7D0+l|qOk-NjU%9FJOM=$2q>CJK+z-uiY60KG=+eosRR^FBcNzH0Yx(iD4Iz? z(JTUr9wne?HUUL*2q=1tfTFpCK+yw9;g~I^=x_HgtOrTar}k&w<4L~reTFjQBC2T2L%9f&KY$;mKmZGQFQuH(%MJos>T1i0BGXxYpOF+>o z0*am^py+u5idGX)^a24zFA`9+hJd1%2q=1)fTFbo6um+~(K-T())P?lDgi|s2q=1u zfTE2A6unLe6wOZxH#H#9H{3ha3#8~!ZX0hT`OcS9^mdZh|9vUi%=M+{9kvv`%a)=o zY$9OVQU{Uy4q$rRWq}ioRh>(P_36ean`jGi)jP zjx9ysv!&<2`IXafTBVK6cr|*D4h@}`X?!zcb6$D=ssWcuM|~tq>3c_&X-ekd$M=u z9w{op^`)pJTZ&4trKmJpipsF1s4QEG%CV)WJX?w?u%+k@Hi{||P*jP4qRIpmRUx3L zDgi~+2q>yfKv4|>ifR&2bSD8twFoGxO+Zl{0*dMqP;?goMfC_Ms!u>s0|JT~5>V8L zfTG3(6g43Pii#zNyBm<`EAA)H6i*I5(x2hJG}|=UcfOpWjAU=pJ}JuN`cl-AEk&)^ zQq-C)MQzwpbT?ay+Onmn9b1apv!$p58$}%nDC$H&(LDqdbta&w3jsx42`IXkfTC^$ z6x~NaQFj80dJs_5lYpXL1Qhiqpr{W4MSTe<>PJA){R9;CC!lBm0Yw7|D0+YpC~BS@ ze!+l5R~I!nEu<)y`>=mdvhRF3MT3*QJs(NY5UwvpL)lU^j4egO*-|uuEkz^QQZ$M! zMWfkLG=?ojkFZfRmVlyh1Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gA zGYKe~ML^M`1Qg9CplA*OMUN3sG?##)#|bE!M?lehLZIlOAvrJp%k5UUz**N>^omh(YwiB+k;ZH zh3iYvdu%D%%9f&SY$q zF9;|)K?oFWP7aSUAkkLtOK0y$(dSqv#v~Mdt}9xBML^L_0*d}7py(e$py=!5@Kys7 z{o8#r$Vn+WkkiJ$$-eXD6opf~llJ-STn#J6cyTHJ^&@?cEk*HcDe~D;6k$tI0$Yj_ z*;16mmZD^~6s53HluAHRHUf&W6Ht_cfTAb?ML7v5%0)m?ZUTz(5KxpxKv7--it-Uq zl%Ig20t6HlB%tUv0*VR|P*j+JqI3d^iV#p#lz^gQgg{X!B^-Oy6s>mOcO9D&e2lgr zmyO~nzVqc2l}ho7eI`YvxxQW(m0?R!S+*3FV@pwawiH!hOVJ%{DXPepqDpKjs?0`F z6#|N?5>Ql)fTHRI6xAT0s3rkLcM?!ki-4lq1QgXFpr|eZMRyTURF8n7`UDg;AfTur z0Y!}nC~8bVQ4<1+ni5ddjDVu%gg{Y=lyGwc5Ow$KR|1OeC7`Gq z0Y&!_P}H4(q8Q zMGq2C^bjFXl$jEqXF#Hd-B&M}iPSV3EzVqc24NLJ}J0V5GxxN&QU`x?RwiJzG zOVMby6pdj^(Iadr8q1cVacn6X&qmP%0*WRQP&A2vqR9jlO(CFYDgi~)2q>CPK+y~W zie?f}G>d?uM+qpJO+e8c0*W3ZplB`uMUN9uG>?Fy`2-X#AfV_80*am_1d4{FgpV1J z=-cj%*ib3znQCKUitl_mMN3n>YhOvxGOjO0%h^)&6kCd(W=qiuwiK;oOVKlIDSDPI zMXT6S^c)*S&l6Cznt-Ag2q=1yfTA@76um@1(aQuBttFu76#|OZ5m2eYO;Rz?P!zY$@8omZF_(DcZ%BqTOsM+QXKjy=)ZiBcSL* z0*XE&plCkMJEU-`jUX6uLvmmnh+@3k`nG|K%yz`=Uu-iMLFC%Nhec$=gTSjHpQEAT8hqa zeJT2mEk)n6rRWE?6#dASqO)u%`iU(?=h#woo-IWe*eJS4K+(?x6#YU#(XRv)T_T|9 zG66+b2q^lEfTF7e6kQ{r=sE#KzY|b&gMgwx2q^lKfTF($D7r~N(cc6V{X;;}zXTM; zr0N566om+ZqHj{dYYa&ACHGCTr=_T}`*KKZs_%R`Me(WLzB5wfbA2g_u%#%0Ek%iJ zDN15XQ8HVKQrJ?I%9f&RY$?jlMo|s|ilPJ*ZSZ3Mdi4@6qRR7Q3bXX-NBZkifk#W#FnDUY$>Y3 zmZGX`DXPXsQFQ`}Y7kIVlYpW-2`H*XKv8W1is}$hRF{CFy9g+%M?g`10*V?CP}Gos zqDBN1H71~_2?0e-2`FktKv8o7idqm*ltDmICLvH%IyGF`fJBqsPr)i9MU~u_Lt3W# z&X-ekcdFO^tQ587`cl-6Ek*6wQq+MhMIG5v)QK%c_pqg?Gh2$fu%)Og8%6gLP}Gfp zqWcIa>P|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk+!pMawN1QZP*plBcgMGp{AG>Cwr z2MH*8h=8Jp2`Cy&K+zCFps00fc#Hvw)-Pmm+DK7O_Z5(#slM~&6pc*vmYHG66+X2q>CLK+!Y;il!4#G=qSm znFJKgBB1C|0*Yo6P&9{tqQ?j*noB^@;{+7VBcNzL0YwW4D0+f`q9+L`T1Y_AA_9sQ z69PrUQ^W5YkZ6*7BQ`>c24{W1mg+lSPSI1T-ZvMd=xMGmMJw1+w301F&#G8we=nw%#hY2V;LO{`{1QZ=5py(I@MV}E+^f>`V#|bF< zf`FnE1QdNqK+#tO6n#xV(MbY|P7zS_4IxmpEj65BK%(jC2IqY#>Ke9jI@Nc+oTBej zy+N0x=m)MZML)8o=qy``equ|}Ikps?XG_rqwiI1tOVQ74Df)$tqF)Ipx z5K#0R0Yz5{D7r>K(RBifekY*l1_4EX5K#0d0Y!fiP;`^&sej@87lOnR)iiHP4ity@N%+1F+~102ciTz@ngwF59sv0l=ax02Uvv_*4F8q2uuIDQa*Nt`39tP|7Uj}j7Ih%YqK;%))QK#M zI+JBl7qTqsN|r@=WLcC?mPOsjSkxVWMQZ`Ds0RRx3IJGC2*9GA04(YSz@pv&Eb0Tm zqP_qu>IcB0{s1g00$|Yq02Zwcz@l{kSTqoTMS}oXv@QUP1_Q8Y2mp)L1H=}kx+GsP zLGnNJ+tuy5#8>+F_$|owyQJJNw`h2m@W=0DQ8DdhQ3+WVm6B!A2(m01NtQ*U$g*fd zvMd@+mPKR8vS=(Bi#7sa(Z&EQ+5~__;{aGR9)Lxg0i>d)wv^fBarU0<027pCV0a#QEh%Fl0CE4eDvuK7}G)xxl z?`PL_T~h9sTh!1c9RH&%YNWj^Y9h;`Ey%KHOR_AQL6${Zk!8`=WLdNgSr%-c4EC3eG24K+~02Z|XuxLjB7R?1<(L4Ya%?Du7P5><08GuC# z09dpTfJKV{ShN^`MN0r!vmIAP786dW3dY9xZ6D0pd|HZU=S(M|K{mZ+g+%LCi zWtVXE&$4KD+RLIn$g*fpvMgFfmPLD!WzpVbS+oyX7VS%xMf;Iu(f(vCS`EOW0{~cb zAOMRF0$|a>04zELfJKJ_u;?%V799@2q9XuUbR+f02Un& zz@ifXSac!)i%tSy(a8WTIt370v}>2-B_>Gz&3+KuO%|Q&7MSWMb`tc=mr25-3Y*Fj*EoLY763l4a3jWGs3dfJILLu;@tu7Ci;PqNf2^^b7!t zo&{jha{w%Q9)LwJ0I=vq02aLjz@nD{So8`2i(Um_(Q5!KdL4j8Zve39O#l|X1;C=W z0a)}7Ahzi4F3C|QNd92|#k6~5(Q^O&qIbKb+%LE2!!BV{;4`q_yZ(swvgl*7Ec%2j zi#{dGqR+^(=yS3x`hqNrz9h?{ugJ3KYcdvn1Hhth0a)}M0E@l{V9^f%Ecy|EMLz+s z=w|>H{Q|(EUjbP38vu)b2Vl`304(|wfJH%9UAALU0)RzX04z!ZuqYdVMIiu-asXJA z0>l=*-zB++36lSYzmN8TEb8CWLc6Xh_scEn*fl&oOBQvay)5cXmPK92vZyOr7Uhv; zQ9fA~btB87?qpfC7FibcAY)Mh0E-F%Skx1MMZEx6)Ej_BeE?Y07l1|m09e!?fJH?B zEE)j7qO}27vLHXec1ID7S0!ZWAQ` z6h9T}&^5l&f7>k@)-~mRxkaU2!?&|#(FoehqLE}-G>R;XHYCfU(PUXPhAfN5l4a3G zWLdN^Sr%5=4CIGOg41h%w0a#QHz@iEO7F7bUs0x5ZlK@yW z8GuFA04&-ZfJIXPSX2YRqNxBZss&(C9RQ1_0kCK~AhxKuYceM^i)Q=#XeF{}g1;ME z-!MGF8}v=D$rivU=(7=T4f z09dpO0E?CauxJ?oi~H#`1@#0vZ&rK`*-V_a=+Z7J-dbr z+smR=w3kJDk!8`|WLdNiSr+X}mPPxKWzqg*S+trgiw+>mq65iTbPxcG4hCS+Apk5o z6o5sC0kG(B02Unqz@j4oSacKsi;f0h(J=rlIu?LM#{sbDcmNii0KlRX0a$br0E z=aFU6`D9si0a+GZNR~wxk!8`vWLb0xSr%PNmPMD5vFLID7F_|rqALMdbQJ)Lt_EPy zH2^HS7Jx<90kG(L02bWK< z7QG0-qL%PiZfUJ|oMb&&jgr3$iTw zk}Qk9BFmz$$+GAhvMl02Z|aU{QMj7UcqBi$3a_ zoMVFIPxIg2|5z5C+sQ(Qyp;Rp7In!B56qWEU1=|i^2o9%pDc^Ik!4YLvMgGQEQ@-O zWl;fH78R0ZQBN`!^#Wi~ZvYnc0bo&I02cKFU{QYn78L=oXaE3<)&^kFIshyh2*9F2 z04!P;fJK7=STqEHMe6~uXng<{Z2-Wcp#Urz2Ed}>04yp7#1?hROI~JzZG%c70RvS<^sEE-3aMdQh` zXj3v4Z3e)i2>>iA17Oia02Y-4u&4rnMU?<7ssdoqBmfpo24GP&0E;#UV9^u+7S#Z- zXet1UY5`bO2f(6f04$mgz@mBp7Bv8{s1XobG$Jqgl?jqR#xL$i%A)!H27gmt%KdVS zw#p0h3S`mNw3kKOkY&-fWLdNwSr%0>Gjj z0a!E_fJO5FSTrAiMLPkoXlDQxEdXHALI4&m0$|Z%02VC)V9_oBELsY{qGbRqS`NUX z6#y*S6@W#%0kCK#0E>19#1?ItmmF<^_IvRjQ#{jVCSO69s2f(7^0a$bb0EALbP-t= zT}+lmmyl)ArDR!j8Ce!xPL@SikY&-8WGuQ0fJIjWu;>~97F`R#qU!)ybUgrzZUA7> zjQ}kA2LOw10$|b204%x%fJL_gu;?}b7TpfOqB{UsbSD6d?gC)Z-2g1Q2Y^NQ0l zKy1;udC7ZCko-M5nmFglq6K~<`~JL?`{forlo!6+R~9`?ds*}dSr$D?mPL<|Wzpkg zS@Z;17ClLpMNg4s(bHsE^b8q`o&{jha{w%Q9)LwJ0I=vq02aLjz@nD{So8`2i(Um_ z(Q5!KdL4j8Zve39O#l|X1;C=W0a)}70E^xQV9|R3EP5Y+MIQjL=tBS&eFTUt`e$CU zT|cvEr`{&cgPa%nry4)bOSxZe(dT*LdPTD63);(~FUhj#E3z#5nk zvMl#`k-5&$g9 z0$@=RfJNB=ED8Zwlmoz`6ab6b0kEh&0E=<~SkwW4MI8ZH)Cmw<^l4tQ)&$8PlyBmE zCX4Ryw?jJTr`#{MC_g`3ytXXrMtfP*oh*yiBFmy4WLZ=|mPLhRS=5s(i+Yh|QE##= z>O;n&z5p!h2f(8K04yp3V9@{o7Of4yqICdRG!TGAg8*2xE&z)L1F&ca0E^ZGVA1*j zEZP8oMMD8tGz@@6!vR=S48Woi02Y-3uxJDzwy0}<@&pqk{|>(_%gc|i^v^PR!jbtY z_scCBlONtVP!^4)y)4>@EQ>ZK%c4!lvS=Jx7L6y%qD{%NXfv`bnn0FCWn?Ux2*9Fp z02WmMu&5G%MO6SSngqb2$p9>>24KHt_Y4S+?{0a#QI zz@i2K7BvE}s0n~YTL7?VOF(SVhWW`?OpyGc{-(!hS#(8o!IqzLzucm2^TS`)l||dp zUKVXnmPO5ES+oOL7R@BfqFH2FG@C4o=8$Dk3t1NJNXDYM04$mZz@qs8EZPZxMLPqq zXaN9=76Pzn5de!81F&cb0E>13V9`&Z{gdGbW$P0q51s~dP0(39fz<%|%uwWOPL!W}1>=!7D3VyeYfb6s)yw5R59=W=If>EjV}mAQ)Hh;m{zMP%x}G2r3Gel?K7&f?GxgK~2G* z8wSC&g37T$&{%Nz#z8Qn;OTKeux&xXWMZwVvg5a8h=NARR4F$b- z34)soW-beY+Y2sU5d?P^e7;){++Q$qk05xcVE0u)@L0iJdk4W&1>t@{@La)^)j{x5 z!LbJh!D|IC9vlR374$tU2;M80eMAs^RB-80LGW3@m&XLbR|Oj$9|YeO?0I4k{8Vty z$wBa2Vd^wn|B1q>XZYVfDm?xy+X9Kgm(Q_HkSOebzHNg2ZMb}Y@LjRMTV-tn`Hxp6#Ac~nw%)~zbjOeDD*!JGc8f*f7zokQRsh~VMe0RzgvIXM4^8< z`VNUg|90y+i9-K+;(3We|9;s8i9-K^&?SjN|Axoqi9-L1zLkkW|Bkg)i9-L9tbG%O z{w+rbBntg&Y7R*h`uB_+ktp;piZ~`w=%4gIAyMcb)jlOr=%2McBT?udmOLj>=%04G zAW`TaSGpuo=$|*aB2nlc7`P@;=)duOL!!`sW%uSpq5sb1?TJGFrMbHkh5lPl_a_Sd z*H#`%6#DNSJeDZ*H;$i56#6@V&m{`|t(%t;g?{h-wM3!cJbf!s=y$)~OBDL;i;oh8 ze*O7bqR=lOzDgAO8Q^z`LO+E6lqmEu__sumd#&v#;RW$7*Yg+KcXCGM6{Uip*EL;j z!;b9G%^v&D3AUpp&e(WFBItcnu0Jz!j6Gv_PNJXQ&)L407&+BhqmhaBulF*$JWh<9 z=j?UMkJ`UJo%$Htu=COOIOuahXA7ehF844-;Z56R6JtA@m^RtF*2Tm|dZxOcg^d+< z?PXyTg}pqCQ z<@jhuN8kGBFTV7!NFHMc#+wY`uE_hZk$@%^$FLuc-fb{czRwtD?r=9x!fL)cC`@FaBYV zpzm4M#@F~P+HAG$X}Qtz2F|;_U)1kUPk(nmU*S1<$Da7unYQlkR+|&!HaU4u{C>x? zHhX)qU(Echf3%z{8sAzPz19~`+;y*@@BPVmbzc%UNt6VA{}8&Z73JEmYWPNZq80TJ zdb<^^E%aS0syF1XVz6yi^ClZI$^g5tD+u#`T3Nxs7FV<@pAj1?`fLL z#&MIxhC$ye4Eg$76r-@?D-}D`Ml)IcMZ;Rry13`X%RbvZS{F}0_Qh>`2mPi3w zi(BX9J^#kJm&I%OqDT5qh*}@?@R^T!>#$?_O|$n7`gXK^Zclp!rKMUACtv!_G4Ub~ zf8)iY_lj1;!u=i`6}^OaZg}^Gl|kPMYvgOaGHw*@3R@WSRk1rW`ugafuZuk_o7=l* zG@pJS))z(dIr^Rl4>Aw8wKj)Xo4(7{_$C_P`qO7WTQ}{6-|*TmU)XHw!@Tc~`F&y3 z`jE>$y2hkh-v%=8#iJR$7-!6T@h3C-?uF++^j$mbxN_V33!+tU(f&UiWv{Ct%zN;i zbDDzw6RgdN)~2Y!hD&c8jU(UXoU|b7z&nQ>wXb!>*8C~=y?CfM%*lK8sMqh>D+mTu z7X^X;%gIXS47lH#`@ft)$=m^38ufoUNqgo!8z%i<&W~9+1A>l$9ce9mWTDUoZ~vE* zZIgXtXGH!l=R{j z$khzPc!nJkiRy0Nq~idaU9mOk)WsI=bMD+N(V;`@JiBxXlI`e8hYp=ObnGzJChuC% zW~w}!Dx<&oidtGX&C;STv%6*)J=;3VwKPjj)x#Qvt^FwIWF7S-7e){4we=j8vCPeS zj%33qOnlY#J#_zsZJW|) z?esfr|3r{gcQr&-fW_j}yUkFFwjAf+jB|Hdc7+>1X?+*P_`rd0~0e zqvZuAfi?EBw*8A+_@mLbbeokIIx_w2jHUjIhqgAXNxhf2BU@y4q(17%_STt1u!R>o zQlHV0`pk~hpY0v#ZYL<#!V4X#Pj|%5R|0#n_G2^Dk585PlbLU`)23wbtTo9>{Mxxw zkgy+{*8U}i4=-Livv|j4ONy5*on5@NdD-li<|RuPFK?N>yk$=D?4`ReS-#l8?3Otz zmbNU*c+RJ{sW&QKvUL8!`OD|;+7cAcTfDHPc;ZxX3m;Fth8kK$YK8UaC^GVQ^oTa&0er#PD}B^nX~83U-bWaHoNbDXD?p3aPgw%nM>vyGp`%UE1PYt%r1|(G24srbG|PtMuB}S zBaC*2^VGaH!ciwwhi-h62tAmcze(-?AG5N7CWhyAR!D+=4^Y#J8W!yW^|L2HKv8yF}K2iXjI47G<^EnVW(GDxc>io@;c5n&JS z?+|M>Ff8a3we4XuYrjs|qpv6CQ*09&_I~(-0xSJJMvL|(u5GkqQP?RbnLjS{_1e2Q z>@^@|^cf5s92O*Z_stQ{u)Rs@ zJhR5DaJ*LKrv9SW3bknlW^Njvjc=NGMSIsu!XCX1wyy7ZUVr;FN3SuxiT~QM?qPxJ zLf?wRfxhMY8Cv^qchgs34_|?6_VPb&5tql;zAx`TPVAlk-XM9y0Am@~k} z{qD9NlJD;|JYE3<<4&+%UD9sDYziL>;$dit))f05<54sq{T>XDMxS^%>fP5zk-s|( z^|nO}?H{f;Fzg)`oaBCcjSCaW z+mpk6@JLP>K3B(`|MK|Kb%eDU?uXjs539yy?j9RNU0%;O?ofNEJ^k+!6=WhE<|6|X5A^$rQM}xqyu$T43*O6~K zJ8#p2l2Ike<-TUwq-|=lW6{5OHrZi#az$pFxf)%lZRWAYyzM-AjfL6yXH3>AUVqK! zEDzAk*PQ8;i2I2fb4-tQkq>`st*<%U#hd#7AChdn|34iw|35V(Wvy>FE2{s%>bRHm%N| zXr5L*qq3&Cs;+)&S!29Jn^oJ%C)U)JPid|wYb%#k9Szp$W(R0?@)P_mT z6Pv24Z2k?^TUVx={Ne?ykwYFt-RdsXOw5XTmb+xsX8GZZ)mJxem5wg;)Uw*GwCP%B5pA}Hx`wC+6=rq10~s+!wOT)I)4smsf1n;YxPY8$3jH%4==uPm$BDta*!+X!3VP-ZiVHnpu_iOn+W z8p@j+8tZJGR+^65hVi;-Gn0({DgATP#NF|E6dB9OD9%q zH!p9qD@H?0MRnPv=DMcFX-$pITh!Gw+WwQC1$%=JDn9)9(3P=wR#a|LZMV86HZ{a+ z+4hah@hIMvTxMIzzH|Hf$Y@?a!*=QBx-BZ}t7_`DTyvrIwUg4rrg>F1H9bM~G#kvc ziKp3ck~yA6FR8&yNDq=D(kpCY#>(*x)Vk={_l&1)L)a>5uAEU`Sy_?MWvvh!VH?YA zgqTvfRdZEYweRI@Lrvkg0Ih3vP4)J`_OYs(>hji6KeE&Zv-GMf9g*I_ZC8(XK->T3 ztXQ~k_w>A@-J!Csy6tYml5H5CT37Fz!^g>Z79*k^WWnM^bBk=yir6S-Uuq9%YwNI~ zuJthG!+!cXjl1=gHI>oW>?^CXtw-^e_SbA1v$`r?DRB=*XDlTecYNdc2p1jA)XO&B zu+uk}m6tcwmz8S>OZR889p|8)IzvA}7zjT-99&7-pN#_BEN zW6tP|LmfM%9h@iCMhE6dg^@OiKPYQ6xMz+Gts_=xWqQl`!*n+#f^B=-$D4Gxvu?Id zU<;jCUuK7NDdbDEt&_P6*{Wi=t*L9!PCPcfK-&!Q8l1?3%4mZxn?H9^%bX&6n__8t zaqe?nmCep1X&s_lhk)|(y5`9?G^HD`Zl=~%#J#tpe)`Gs%9@&{nzDM6d{T9T`Rs=( zUI^6`|m(o%l2<^lmy^$DCN}4OCH#S#Hj?WF+o=A+&m|kPy zR2%J@>Z3zmG~QO(N^h8)G19Yt)Rb-Ir=>cU+antWcU-Y(cFCxbL1r4I-nP*{y&tWy zH8CsW#Ja}zvsSlQ`lPa{Q_EVHZnoQb8>_=cgJ_|xBSvXyWZtCOrlRtVHY)PBCWn_6 z`J0m^V@HfC8nU!yLCef#E$bBxTR3~kit)1-FJ0cUa@fL=BMmH{w_@Qet2-`OJahRl zduMaJjW2T?*pxdi*>%HV%a#nAQ##tn%%!vEjkmWtcO5%y;qZm_X6XiVmMz&}$0bF> z<`xaB8&NdO-a;Ec+d438$AvA+md%{oGHgN1qPffGjW012@4v%*__E~da{2tli-s+; zcNwiNGd9QcOy}q&j%nj|w9VrKmtPA+8?dsruE~bCj7_rPM)4+Tdk&vI7TRfG*~IFa z>aAPP!%J*{Z{0bn7tLu|8O>s3n_;_kjPV^cEn=(Bc3iX3r_oMn{rn(30oydX_G;bK zwl|mC*~Y{&yCBo>?f%=fMBM!`t^V6tM9kV=`1oaspM+G~bw_-<5{(QMk&5$c7B5~> z8boEpU;5JKRG`fn_EekG#JU-oD|GbOzqBu}vEz;%$$eb(h1#jD+nL@=N=ruQRip=f z+Z^fHw5~HhPi)qTi(A;yIeK85J_a^oW(<^(1FhGCYn%@>i94 zJv(_zy9-i2#YWlq^|slq*ggE5DZNdAnHTH-#bsetbyZ#4Yt~l7D$2^Ex9+239xo$3 zK>v0Bu}gScr91oXlkQIZs+(%dwy?d!FUix-WUTVCCcEIb)56RPd_R>-FEcv*m}D1A z@p)DHiAZTbcdo1T;UhX(DE%*=)y`#CkJ794qOt9@pc|Ur8R$sEwCZME)BE<|8ni4u zH#=%DV?PbkGVBank4o(VB;CJ^H88EdZgRCWHzG8-vl zBkgjAmu71r-D^(LGo_CVE{|3feek}maiA}2@SAn%`#iP}rDvMHN-Ucg-L^|Vk+CA{ zD;xji*?crwayjokiLV5sKH15Ry$1SZ*RpoOSY2Kn9gwD#+3_fv%8n}W1KU5_Odj9K zET3%G*p)TWBzB3No?Uu>soJu+$!?|D%G3-sKf95}8nl5!5B(}py=qF*63H*8tm zXwPIEU%84bZM_9iYU6gWY@VG}rLV{RnlV~{9kQbbevRlLzLble%Gjao9KLl8`K{sT z{*9lr*gcEpNoCdX4MX!TJsB&CQ@gjEpvPd`I6OX5JW&t|QkNH(JjzD=PoZS*CB`ttuOX=r(}QlPk)$1ArTB zXEK#`f5h(A>YUD|F7;d8QLo|~_*2VfG?&*l>WGqg|2pd5UyqORbr~-8+wmp6Hj9yXZUDZg0 ze|7MUhvM{YIOZF@+rzF8^vzn|6c1xQ=)yHb+cs@`<2K{+$8G>|c~-qew8G;{oHb^_ z%dyeV4o*7V*ZVnKL5*o+B`xgy)I6`SGn0%{7M@JM>%^fmz8;CzlHYZWuCQVa{2niz z%G99E+cbK?O|?^M>$Z&72bVm4pWo*jUr8{hiFQ}p-m{C|Pl=xP>lvQRIB95ewkIiilJL#PxIpGrAYA zhj{1V^{@}P!1f07ns-8@Go-4r%+n8AFsb(><7&c=e_Ffo@xh;tPy1QqwD?@w?$M>! zOXP`-9%)cMwW7@hrFqUaOK-hQ(OL&xza5_Wt`yykUv{+GY?VgqukAU0>n!YzQ%=d~ zGgny+O%3*5n67gFa_BMym=ry+9X^r2ppkuA)W^JxVeD<~@G}+6dZ$6v&dLnwnpc~)J zY;NYFml2O z^AW#_iiaz|Kj^C~9wJy`wC^|kyEjL*=IB=XTq(XLiMFQSMr3BuF{ZYx^*0-Q+pW10 zrZuPEiuCo#(W7-9@z&Y0u6~M+eCacU()czgliEPTTN`aJlB(<`BG(uG`xwEb^74&~ zhWPFKvZV`)Di_XbnKQ@U>1*UeNzomBK5Vq!zrVj9ea=X>l_z0GN z0&8ODA**u_Xn$b4gHi|Q91Gtn#2JJBc6FKg|DeF*w5Kba^y`1;Sx36lQtn~a~NJ~swR z`loL)eve0Uuhp%i+|$h{c~$%Z$CNx>9p2Q ztoidv|KwZ7Pcr@K{TL>Lbi)WFgSMY3Oa}H5(u|*EU>`Qk_(?{+Zw1M~KCzhblML*O z&N6vf4K1df#SR*&Ak!P-v7q5}+gSF`&pWo_qvQLuQ<73yz z>5u&x_viT(RQ%@Oz~#ZfIsfUFbH*D5C4MEl=3B9u2gcHj17nH37t#7$$*565d`G^O zMejVMXTQd~b@tYf{hVk2a_!Tl_U#is{K@Jy;}Q|lrQmW^YstA zdp}+f|47_FwC>CQ%07VR)3q~YbM22vPw;BV`LSN@dH?Ko zZhvcMUU|03f-KY5KQEnS8v1_XbuCq!B*?N2KESIzIYivY3!lzE`s#JO>O|FPs!gi1 zRqZ=jqUm>0-ADBR)nio8RlQ#I7S+2{A5eW%^=Z`?RbN+qSM_7nFIB%+wJ#ot`s1HP z_19tFG7?q$Vv(qJQ}u5^_2>Jm4pQAf)jkRzJwHZuylS~>wQ8Melj=6AGgarRE>vBn zy1VK=st2kbu6nHM$*O0np09eT>eZ?@s@|r0kLrV}PpCex`kLyys-LKSt@@Ly9fYFw zkmLJd#N6vdbp~8Jlgwr zs_Hqa7pq>SdZViE=RW;?s*k8Xt@@Jco2nnEey;kR>aVI z>PXd%Rm)T-tJbM*p}L*w9Mzpwm#Xfry07ZNsz<4wsCtI#`Kp(xUaNYu>Rqb;RDE3a zIn`HH-%HyUts>Q0KRmZDVs7_J!uO{*NZl$_| z>Ri=Dsw-4isjgN%O!ZjRQ&i7Zy-4*+)f-fAQ@vO9Vb!NpUsQcV^?g+z|GmH8s{W#y zu;YRAcB)-ed#LtR9jH1?b+qbcs*_cxt8T42TXliz3e~+;4^}-!^;FgKR4-S(LG=#R zf2uyI`jYC~s-LKStLop%;IA{Z1D4m$ss*Y=s_UtaP~Ak;zfHy4O;z=8Qt{lZI!|>M z)jd>Ks~(|xqUu?y7pq>QdW-74s*kEZr~10;2dZDH{-m0)b5`$HuBxBIdLF4d$&TBe z8&v1psi@}_s)yUL-1Et*SK6tl=UY^tv}3sES5?2ZQ&G>qtB&pw=W^9mcJAQMAF6t< zott=mQnj6(gLqy`wbsrpJa40V!hkrRtNO}1asE)XXx%suQ{B-{FueUT)hpJI^DV01 z42|=js$=a$#HX)R-Mci-hpXN{GR{w{=GqC1PhX%qZET#kQ$1th)AQ zaV}P!R~F|Ls#lfA`8L(>D&w4}itEOc<7&UY6!l}@&EtBc>OX7Z{H$unx;Xb#t)Cv} zX4O*~;(Vd%8+O9wukTaUfivP^L8- z`cO-ppI7ZXFV4MH8+VHHOx4pC#Q9>?w-&|ubJcZsiStO+1k9p@KSyY3g~zN%ZSj`M8QGY*XNrK;~79Oo}pha48? z4OJH%5$8QsZ#XK>_o)72C%C?SQpd)1!trsPs(R3gaXw!4v6JKcvTFWmaqh1=@0>V)t-AjCaUP?(&tO|P&Ifh&Ye`N-iUL9>Je|n`Bc?s-ih;@s)g^zd64S%AI5oS)eAn3 z^R=pZE;RZG5z^LW)=zl!r})!V;`^TVoH-^aO&>f|5e+@yNc&v8Co^*Ou1^6mMy zYOg=yJXm!HyUXFvFI2rKE6&%eerDhP=+FPGI>Ii{Ja4AD(!LMU^MR^&+80B5epEHP zbDZ;3H}4wfEme=nkMo(TFW8qydi!@(``EWgdR|X;mR$&XUaWeFeXpeF8&$usFPQZF ztLmttIG3sJv38sfR=wN4d(x+WTs3EKoV%&ktQY64RIjre7e4)6s*kF^;57___m#i$ z+S%@RsQxUTZC~N&yq#(%uQtCzc%Np+U$V%1fuhpL{WdcNv4s&{y` z{(h}GczB#QQC+0Eo9bn%cdCA)`m1WOee0mlZ?@`5s+X$XuKJ|vJF4HS4zaKE^Y)vl zE>>NsdbsM{st>FFt~$bQ0C@W<)jd>KtKO{om}+2Of#=h=SKY*`ZHLWNC#%+|HmPo< zI!kp&)y1mIR9C6)t9q#Fk*X)Do~GI^u>I2d(^0jXYJuti)j_I5RZCR;yG^~lon}PU zP9LH=Th$K#QC_5KhwCV>QeCZju&Ny%qvualJwx>zRXZF-&tIi_qv|cH(fuFm&)do$ zseY#Vt*Q-M(R`x&KQ_JpeeGyHsCHHDrRslu!k>@s|5&x%GRh-W$Ef;!MW1e>s-4~k zS+;V!YI#RuOra4+igW>*_S}pd8wTz|ixOC=1o2aaQ>hPJ%moJ?^YsGS#?ce^f z+n{!|i0@r`qf!1}#*eMa=x2ca@6#pY_?PMYIsX}K|J?uoG@ZM?=5jN?;m)_E|M{c1Y-$SeYyVgi2cj#-&Yy0*T-x6_o_WMmzP+H zezvvwZA`Grvb?gd_|vD@bPjyX_t)(6^VQ_bWZ$rd!6~~Xf-C)jewbgL<;>}VBNKt0 zW~P6bF8$4X%ZD#6E-ET29b<3tl#CcVVzfOjDJjkPfAr{4MMYyr*=HDRx}u^Ta`&mM zsfxciGM;V1-jQIwPTEyQDU8R2A@*8&1Y>WU_(Qj3-sX9e^Q-Uu>Hgr}pWf=)ZHI32 zPEY*yT-|qfH`Nyv4Ve7RsAcVHo}YQ|PuYoke|oB`O;_^VPuZox2EV=%6#e<*AAjEe zQ;-;YN6@v$gs@$9uy2sP-*@(f;qkVyZ#}b>)NyUIWmM)GwGL$^a`rK~vl8u&$+eOd z-j?!`I^1Bghjlh+eYQw^$lv z4^ixAaYT^4o?>5%BZKVq75i8m6=ZLq*xTZULH1C^UKU3O*~1ijS{xH(4_7R-I5x;G zRxGf%QIK7t*u!F}b*of)Ezj1k5z5^?TgOH!ck^sL8>O7@*}Ar&a-L`F+i2yko~?6Z zl)HGg-i=l6?Af}vk#Z-`*1wIFJ6axL{o6#jgJ}#yZ-R1;XX{^?a_HImH&Hp;v-PiBIqBK@SD~C`d8GBPQaRz-`d6iF8nnyK9+-UC zwtxHM-Je0xUqWi1XJ%wiN?mLdxFJ(QzY`r9Qlq9aWU8VJsa2FAb&4`%nxYJut|&w5 z6=g_+q6}$Nlp#%u7_x;jhHR;fAv2UQWGiJ1*;*Mxwo%5AZIv-(J7o;nUKvB0l`&)o zWel0Aj3Kj>F=VzfhRjjMkQQYO*-;ro<|<>zJY@`-uZ$r(DPzda%CRBU$xm(jxA*S| z&)z&XWPy!P*$Yx`jvKNh{M4R|4B16ZWyn%R8L~`KhAdZjWXMTsDnm|Ilp&`m%8*kPWyooYGURkc8FGfA3^`L#hMc7+ zL(W#jkaLtVqJ^lriK|WemAY8AC2t#*izN zG2}{R47o}fL#|fFkZY7NXv8**#tUu+*4a+{jUklPhy$Q_C@GDPzdP${6y9GKM^=j3JLHW60ym81jTNhCHc^Ax|k|$kWOg@{BTu zJgbZ$&naWb^U4_Vf-;7@sEi>mDPzdX${6yBa%{-W$?3NJ+dtsv9=F7XRQfr|t0_0f z4S6%1ZkKM6A#bUv40&5ohP5koOg3$OnotUn@{ytp`B)J{K2gSy zPn9v`Gi40F~J?skT?!da32k7R&`j`*McVM0D z2FP<@z3dL?>cG0W7NCm*>t_!@X9w2N0zfAR*3&{jM+1I^(-Y9af%UW(AlHHQv^Su= z1M6uYKsyK4)4qU|1M6u&K#l|JX@5ZIzmG z0VYVN?Ch*W@>UZh_Xa;bNhV^8a@?pviInT*7Oj^E{dXWDi`J*TEZTr9i-wYA(J-~xv1k+ki#7yc(P#h`jR9cMSO6An1i+$=0a&yN0E@-} zuxLC0i#7#d(PjWFngGC}G5{7$1Yl7)0E;RBSX2qXqACCuO#)!iWB?Xb17eE?C!*iW z&b`RR86u0Gbfq>=q}(sJs5TJ}=q`)uXfKPVk!8_zvMj16%c2IdENUdnq9(E|+JY>L zwj|4<8DuQl3V=mh1F&ct02XZvz@qH{ShPI=i<$vgv;zQ(W&*Hi766N81F&cg0E=1x zShOPmi{=8bXdVEI<^!;3Cjb`h48WoV04!Pvz@kNf*rJ+5vdRR>y}@GkR9RH*N-efu z^|G7zZqc$tIM;5tMq|-(+RLI9WLdN;Sr+X^mPIScvS@d*EZT!Ci}obTqE%#Bv=AQMHd6G=n?=HT?)XW%K%t(IRJ~U0ASIT04%x+fJIjWu;>~97F`R#qU!)y zbUgrzZUA7>jQ}kA2LOw10$|b2fY_pw63J&wklglu`E{}^8txX|l1RB>67X1pqqTc{m^g95H{s3Unp8zZh zveH-i@ikfkfJIq=*rK-*$?Z*$T>rd4_S>@Pd>@OFSt<9+ElOpD`}CJZ?PxEH+LL8b zE?E|JAj_hTWLeaSEQ>mmWlG78L@p zs3!o6dI7MgHvo(J0I;Yp0E_wou&6%(i;4hPGys4_YXh)o9RL;$1Ypr10Ata*04y2| zh%E}Uk{6gDxkuU?@7Xz7@s<9EJ{AqhO1WQd(a@~$fdR5;80}@zaI!2aCd;A{vMeek z%c2ovSu~O?i$;-U(S~GMG@6V>V*pq*7Jx+?0kCLe02XZmz@l*gEE*5MqD=u5=4 zCIGOg41h%w0a#QHz@iEO7F7bUs0x5ZlK@yW8GuFA04&-ZfJIXPSX2XuEm}V-`H2aV zJKBCfFM9)7l=Lh8saYxa%PpFo6?PaXi|T1FiyFwXsF5s-n#i(f3$iTQk}Qj6kY&+U zWLdN|Sr%02a*wU{MPIi*^KH(Odu) z%>!W3d;k{h1i+%50a&yEfJF-dShNU$MT-Ggv;=@fy8vQ~>avn0CP?loAB(2RqJe%y zTbh+}zucl-v%=}?%A(z9FN;=^Wzp_rS+oaP7VSxvMXSiNXfLuX+M6tk_94rneaTp~ z9{`K?2Vl`^02Unpz@h^ISac8oiw*{0(IEgVIuw9KhXJtYZ~zt^0l=ao0a$bt0E>9zx(I+p7Xz^9 z5&#xm3c#Yv09bT60E?~wV9}KTEV>GSMOOo`=o$bPT?@dX>i}4EJphYt0ASIL04(|k z0E=z{VA0J0EV>1NMYjU5=r%xX(WzO<+f9(%V-hCLX|kx7k43jK<7QG0-qL%&$a*N*23fCDXi$0*eEc%cv zi#{UDqL0b4=o7Lm`jjk-J|oMb&&jgr3$iTwl8i-P0kG(602X}%z@l#fSo9qLi@pb7 z(GLJD`VoLdKLN1lX8;!c0>GkQ0a)}K0E>PHV9_4{Ecz3GMfMxWr`u+q705@sOdG&|Vgml4a2dvMd@&mPMn; zvS>rHEE-LgMPtaaXe?P4ZA8YRjR9D+2>^@60kCL10E;#SV9{m(ESdnoqA~y$O$1<3 zIRJ|)09aHBz@jPu7EJYNLkcGds(yvSr%%>XRg0f0p_0a!E(fJL(bSTqNKMJ)g<+7W<7a{*X14}eAU0a&yX0E>18 zV9^2q7A*u|(INmAEe2rG5&#zM0>GlB04!Ptz@p`V*rNJmveziHD9eYR23d5j-^gB( zOu1if(eBA`lhLwh58BJ3J;}0Y6ALbP-t=T}+lmmyogOQUDfR2Ed}r z0a$be0E?~!V9`|oEV>$iMb`kZ=vn|4T?fFT>j7AF0|1L|1YprW09bSr0E=!0V9_lA zEV>ndMYjR4=ym`W-2uR&I{~ppXC#vsnIO48`tWn6Ec(;KUCEUD=bpRH<0l=a+0a)}F z0E^xRV9`4OEP59ZTXat{`I!lldzRmIyjK=Y@UiHo}7X1mpBK!UB__7^~5&$g90$@=RfJNB=ED8Zwlmoz` z6ab6b0b+|jNG3;^Ah|>RcJ+s{Xiq=8Zl9fUzuclu*@2J6RU3MV3W9$g-$_j75b2Eb0lsqFw+j>J7l6J^(E03&5g&04(Ycz@j1m z77YMk(b@nkS_gnd0|8hx2!KWF0

0E>nIuxLF17OfA!q7498G!%eE!vL{G9kP=v zO_1CZK%c4!lvS=I`i^c=6Xj1?dZ3e)i2>>iA17Oia02Y-4u&4rnMU?<7ssdoqBmfpo z24GP&0E;#UV9^u+7S#Z-Xet1UY5`bO2f(6f04$mgz@mCUY*9&e@=g;ZceTarQd#6* zVw~NOopQh2qAjz-H_K(w4BE@0t;n)yYqBibhAfM=CCj4i$g*gAvMg#Q%c32~vS=n5 zi)I0^Xf^bp%D*#xuD*%gj1H=|JWhb*M%%WfYuHzQ6=s+KfR%WN%FSlq_ zb~va?7VSlQS+qA<7VSfpMf;Lv(SBrEv_DxEttQK&1IV)IK(Z`4h>S%C1F+~202Unz zz@ozdSadi5i;e(b(UAZwItqYAM+30v7yuR>3&5h|09bT90EIsl8#0K^vUk)7P!1j&8Puk`nnMG5=BYxbGhDfi1QIyXDqd9o}z zkM^?Ye6lRMfGmqHB+H_U$g=2SvMjoUEQ>BB%c9H3vgmR$7F_|rqALMdbQJ)Lt_EPy zH2^HS7Jx<90kG(L02bW7eAuio1JpM+@gPGhu3Z{iyoxCEP9A6 ziykJ+qDRQG=uxsPdWSoAyqi(UX= z(Te~qdI^94+3Sd;)@Q5FD;k^n5q24GPLz@i)g7Nr1K)DD0}?EzSn3&5fdfY_ps zvy*+Mnnm0ACy73hMIHQz)-g=EUv5#?FdSbei}GkMi}J~`s2f=pbtlWBwaBul2U!*s zkY!OJSr+vq%c5RnEb0xwqCNmD>I=Z4egG`$55S@#02U1ZVA0wDELsPEMFRm?Gzfr2 z>jJQ7FaV2&0I+C102Zwez@iNRSTq!XMZ*ACG#r3M#Q-cS0mK${4wJJ?klca(d)Hk; z{r0~9vQcT6a=+Z74a0EtbXhc-_OfUUSr&~Y%c70QvS?$nEZT%Di^h><(Ri{f+LSDd zHX~!v1OOJ50kCKy0E@~2SX2SPqDlZ3RROSQ5&(-P1F)zXfJK`FuxJVZi)sK^G!=kF zwE!%t17OiK02WOLU{O5)iy8n})Cj<$CO~Y_$S`?{36lGjk42+o(e3RlY!Rm1FSlsx zFnqW{7Hva&S+p%#7HvnCMcb2QQ8QT6lt?GuJwwva{p(q0zr zN0vqVlV#CrvMf4)EQ<~#%c6tGvgly4EINcNiw-4Y(P02AIvjvSM*y(sNB|Zc1;C=C z0a$bl0E>04zEkfJJ8ju;@$x z7M%saqO$?9MSF$GQ6@<448JVfTNZucW6?Qb%KdVSE(pV>8M5d?+RLJg$g=2SvMjoU zEQ>BB%c9H3vgmTMEV_a$i>@TgqN~VQbTt5rt^r`twE!%-4uD111F+}@02bW{z@mQu zu;?ZL7TpZMqFVr1bSnUhZUbP^?Eoyg1As+$0V02bX1z@mEqSadG{i|zwp(fxqf zqVvM!9wtbx|Lw8t^JUS4_FVP@Vaok-iyjWc)3=sIkI-HgJxZ2EkCA23<78R%1X&h6 zNtQ)Vk!8`-WLfkKSr$D@#-ir{SoAyqi(UX=(Te~qdI^9P?nKeaNz?FByya z0kEh)0E>zMSTq2DMQa1FXdM6+4Fq7(AOIGv3&5hm04y2;z@qg4ShPL>i#7mY(NF*u z4Fh1&Z~zt+1F)zBfJLPMEE)m8qLF~uqP(1BjR}%_zn@*_=fqd~L;bRUR8GqMa*M|1 zgbQcNqK#-Ti#8_9qD{!MXdGDPXLY754l4a3cG8WAPV9|U47VQMUqMZR)v;crb3jtWP z2!KV40a&yIfJM6iuxKd&iXRA1%O4j0d02bX2 zz@j?CppIi$$i|1 zpNnMCBo7beq}(sJ=&_vez@22#HMO_oK^kY&-cWLfkaSr$D{ zmPId+vFJqr7QF<(qL%?!^a=orUIk#$YXB^I9e_n|0I=vy02aLkz@oPSSo976i{1rb z(R%rl9!nvxo`Us?NM1Y-Y@$< z&q=voZqe5{;iC&=(Koc0McLY76plCkJF z02ciYz@k3@So9|Vi-MFc+p#DCz@jVw79{~#lnub55P(HF04z!Yu&5mXi`oOQC>MZ5 z9ROI=5r9RV09e!+fJI#ZSkx7OMR|bOqAzojUzs4eXZi5+l`Oi@&#v=RDfi1Q>X8cb z7R#an+RLIsvMlOJmPNhDvZyy%7WE;^qP}EV)Q>ES`jcf*5gCgH0I+Cn02ZwSz@mWw zEE)vBqICgSG#G$ILjYK`9srBh2Vl_#04y2`z@lLQEE*2LqGA9Rl>o4)6o5q|09Z5< zfJLJKShOJki$()ti@K+hqfL<9&HYM$tyFxa-^;J`$D~s3ms_++D%^4xSu~FJvS>V6 z7HvwFMVpaj(FC$ADkICHiDX$+PL@R#WLZ>6#-b_!7EJ45)3+?|KnTtEK*f1P>Fac0ge=giob7)91GGj_7?`@U0S zjIlG!3?YROi6ki@5z->1q`inX6s1K{DG5=bl%jl}&v`xWGxPp@uFv)R{PDT2pX;jE zJnnN|Gsm2pGv~}$P}GNjqP_$a^&_CDKLJGp2q+pzK+zxqiUt!L$sYyyfV6HqjTfTA1%igF1k$|Im?Dgi~)2q?Oh zfTHOH6wM%@XeI$gw-Hb@i-4lr2`IXQfTGz16wM)cif#$GZyO-N>h@__x)fcrzX^M8 zAYgr2MGFG{6H}$=F3y*tg={HW#FnDF*;2HaEk*aRrDzFTik7ma=w7xIEn}nTJ_3rC z6Hs(N0YxhaD0+Z^qLl;`JxD;&Lj)A9BB1DD0*Y1>P_%}CqO}ARJwiayIs%FwC7@_M z0Yw`KD0+;5qKyO;Z6cs(Gr?0dFW^Q^Gm18t8985y4%&y>j|T$QmsRvsz+Yp!6g|!P zQnZyVMbEIMXd7FKo@GnXb8IQv&X%I**;4cZTZ(qDQS>4KMLP*7dWnFdmkB6(g@B@0 z2`GAvfTGt4D0+i{qBjXBdW(RfT?7>ECZOnT0*dw!P_&nTqIU==dY6Er_XsF@pMatd z2q@Y|@Dx1}aC;aa!7uHfjeSyz8rg^1`vU>%%PKk;@Mq7IqC=c7MIW=J=o7XS9cD|> zr)(+uj4efjuBAwH33E65K#0j0Y%3NDEf|oqVEYP zIzd3u4+IpQB%tU=0*X!%P;{DrqB8^({X{^~SptgA5m59q0Y$$MQ1mOoQ}kiLeZT+- z4z~}5K9Zt$?0wPsK*0L4ihd9HUz{aHmpEUF{$NYdpKK|*%$B0R*i!U2TZ*o*rRXYK zivD3s(Z6gIT_d2#iPF<{6!{1!iXfoKC7>vhfFeHuMa2jx3J_2fMLRv_ z0Y%jaD5_3CQ4Io$Y7$UXi-4lq1QaC`P*jJ2q7(v(QVA$ZBcP}*0Y&u)D5_6DQ3C>s z8WK>{h=8KT1QazPc#29#xkcEzwj%+FF#70qP0*bm2P}G%xqHY8fbtj;x2LVMr z2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1Qgv&K+!D( zPf@cdca#AVEN>qQHJ74!_P!`RDqwwCMVV3lh4Z9nBRv-0Y$S2D7u}1qB{sEnoU5_90H2w5>Rv}0Y&o&o}!E>cdG#sEN>qQjgTVy z&(%lHj|x~{R?(s;|Az~t=x)xJqQz_}x`!=AOW0Dhlr2T~vZZJlTZ-;uOVM(+6y488 z(Fy{J9w4A-B>_bb5>WII0Y$3_D0-NHqSXWxts$UjEdfQ35Ky#^fTBkUC|XZI(FOvF z9wVS=BLPL52q@Z2K+)p_6m21(=m~N>M{g>dB~p^<@=36Xh?y zNQ$;`z7##nmZIm_QnZ~dMbERP=moYE?O;pMi)<;{$(Ev**eH6LfTC9jD0-EEqSpv0 zdYyoxHwY+tlYpYP2q@Y`K+$djiryxmXb%BJdkH9dhk&AY2`GAxfTH&aDEfeaqJ0Du z?I)n<00BiG596n#xV(KiGXeM>;maRQ3IBcSMe0*X!$Q1k-< zMJEX;`jLR5Qv?*9CZOmH0YyI%P;{1nqH_ck{Y*g7F9a0*N)B5Kt6LKv5h4 zMezg_g$O7L6Ht^uKv5zAMa2myDnUR|Ndk&W5l~c`;3>KkMGXlkYD7R$ zV*-kr5Kz>VfTEiSC~8LV6qSp1gUgJfzV-oi`DpK%{z5yNM+dAgtEhFfzt(aoYQyJU5KuIffTCdp6x~cf(JcfNr4vvzoPeSX zf~TluwA;%72@bM%Kdq#wcK#E#=z#TQ6^)AaPgx;Fqd8xS#;~PmEL)1kv88A{TZ$&I zrD!5siYBq8D4Q)sli4VmLO@Xt0Y$k46y*_6G?jp&X#^DANX;=( z70kn=$c51X>&q&-C))qgN-0{x`BJo$Ek*aTrDz#jitb}e(Q>vF-OrYy6>KSbfGtHU z*(iFDfTD*8C|X58(Zd83ttOyo4FN@K2`GAmfTDE-6g^5n(Ru=kHV{zs7y(5a2`Jh` zK+$FbiXJDRXbS;FPY_V_BmqTF5m59r!Bcd1w0q0|3AQ&gaY0|XR( zNI=m?1QZ=4py&|6Q?xDGy?&KZlxe?q{j3!2w$IT%jt*E~R?%nC{7=yT4OqA%D| zbc8KMU$Uj>C|ioYVoT96wiJEMmZERiQuHkwMaKy!`i_92?+GY6K|s+D1QeYlpy)>e zicS$wbee#oGXxaV0~Fde@FZ8UModcIA4mcvZd%BwiNx#mZEEHDRP2( z<}O7(wiHFMrO0JVQ6w8hegcY$5l|E$peTxfqG$q&f&>)B5Kt6LKv5h4Mezg_g$O7L z6Ht^uKv5zAMa2myDnUR|Ndk&W5l~c`fTA)46qO~Qs2sslbUE7HW`G2v?bEWqq$t@w zNGcx;SYK9ArJ(=dIw?xxd?~8TmZIy~Qgj1bimI@ss482EZe&YQHMSI0XG>8HHi~Kz zP*jV6qS^!$B@<9ohk&9K0*X=zC`u!ss4f9T^#~}cPe4%v0*V?EP}GQkqQ(RiH6fs= zDFH<{5m3~OfTHFE6ty6rs3pNubY0N>-2e$*ws$`jgWfa!BX+b32COfus9n%sa)T7L z=X@#Zz?PzpY$@u*mZHvVDeA(OqONQy>c*C$?rbUQ!A4O}0*ZPOP}G}%qCNx^^(COF z9|1-E2`CysK+!+~iUtu-G?;**Ap{f+C7@^+0Yx_xP;?6cMd<_-4JV)|gMgwD1QcZw zP&AU@DQXjRn;IZN`!^Luww0nM?Z^rStS_r*Y|uY+qZEzfd?^~wmZAx4DVoTZqDgEi z%4SQ^WVRGdVM|dCTZ(eoD9R(CXet3k(+DWKm4Kq@1Qg96plBumMYj=9G>d?u+X*PT zgMgyh1Qg97plB`uMRyWVG>?Fy`2-X#AfV_j0*V$AP_&4EqPq#6qR~NjjsX%pXzzZ; zNYPIFAZc+hV0~Fd_XhnNHcQbm&X=P5*iy8dEk*aUrDz3PiXLD~(Mq-yJ;;`#huBiI zijAU&2`E}kK+zfkiq;ZP^aue(>j)@%lz^i31Qcx`py)9IiZ&8Zw26SC%>)!ZPC(HX z0*am>py){gik>2%=xG9qwh~bE3;{*k2%e%PLHAt)BskQ5p>e4cCD~{C&jth5msRva z(0^)+6z$-ADSDADMLXG2^b%W&US>%qHoz!bet_k-?63Wdp3$r5K#030YxVXDEg6rqEiGEohG2@3;{(y z5m0oNfTD8*6#Yy<(JurP{YpU5c>;i zk!&gQv!$pQTZ#f~6h#qG6iq-;kbt5X0*Yb@D2gMXD4u|#5CKJD0*Vp{C`u%ts5k*d zB?u@gNkCC40*Xo#P*jG1qOt@Ol_Q|2JOM=&2q?Oa;3>KibXOT5!Nc~x=&BSwXkHgt zF(zPrSw+{!_+Qy3MK^H16jfnMQB}4S-N=@rYHTU0&X%GYY$>YAmZDm0DXPszQ8EEV zbqFX*A)qLgfTA=4is}+jRF8n7`UDg;AfTur0Y!}nC~8bVQ4<1+ni5cS69Gld2qGkl=p%-Pp=8-ZTB}_Mvv$n1JvwiI<|OHmKD6!m0FQ7^U>^=6}}4*^Ae2`K7EKv91JiUtr+ zG?0LzK?D>HCZK2t0YyUzC>lmU(ai)D-9kW7Isrw)2`I`SplAdEMVSN?jU=Ebi-4k0 z1Qd-Xc#7J`xK*|rMf>bm9Xm+TJ?3?hV`2i zDQqdqVM|diTZ;17QZ$t!zbAfRX_0Y$eFP&A8xqT2~5x`TkC*#s2L zA)sh30Y!HbP&AK#qWJ_AEg+!iE&_@c5>T{=fTFtzC|XQF(LDqdEg^V{#>Kef43OXy z`%q}S6pgbFl9t8fP_&tVqQ?m++Co6l69g1J zNkGw41Qb0@K+#qLik=~$Xd3}V&k|7d905h!37(>5G468)NN}~iFS<{PO54w9&&LF; zFRN&0jQ``8r06Bim!g;1QuGR2ie6<)(Q9ledYvsrZ?L84O|}%h#g?L7Y!vM#py+J^ ziuMptw3mRQcL*qYmw=-82q=1=fT9lwDB4Fr(S8Do4iHfEApu1n5m0oHfTBYL6n#uU z(I*5H9VVdYQv!-UBcSMWf~ROljQfWH5(Io}PXdZA6HxRQ0Y!fk zP;`ahDf%+TZDxQ3FWRp<9+je4dtY=lCSZM8MNX{$=GUdj7prITQWU|KB9|>ik!&gQ zv!$pQTZ#f~DT-oCQ8ZhMf@~DU5Kt6LKv5h4Mezg_g$O7L6Ht^uKv5zAMa2myDnUR| zNdk&W5l~c`fTA)46qO~Qs2l-B*kV*}QgRa7pxs2W>}sKx)_vaq37)a{MO9+GXZkH-&FBytu)eIK zF0uYIyQHWq=SxvHwiI<|OHmKD6!m0FQ7^U>^=3;^AGQ?rWlK>%Hj4TaP&9ymqJaby z4I-duFabqF2q+p#K+!M)if$&L=oSKs(g`RUPC!ux0YxJSD9R+DXe0qeSp*b~BA{qA z0Yzg7C>l#Z(Kv#qs8g&PzuPGC+pjuymLmHX&P0xn4Om}RQFg39Wsek1=6ord!j_^O zwiM;Er6`XrMN`>QG>t7qx3Z;ZI$Mfnuu(LVfTG(7D4In;(d`5j-9bRnYyyhr5KuIi zfTBAID4It=(R>1m77$Q$7Xd{J2`E}bK+)X<6fGv8=pF)!mJm?1lz^gp2`E}d@Dxpq zb^940!FKim^&}}8V8?y20qe^udLY(6^&Kf%$@x)0rIlz^i31Qcx`py)9IiZ&8Zw26SC%>)!ZPC(HX0*am>py){gik>2% z=xG9qwh~bE3;{*k2q=1%fTHIJDB4ay(enfpy+ApLB$#UNeqNTMisp5ZM`HulmsRvltlzg! zioWH1DLT%UqVL#J^gUaOPOzou2euTQWJ}SHY$-a$mZH;a6rCZU=qCb-&Js{`j)0<{ z2`Ku7fTCXsC^}C-(FFpEE)r1m8v#YX6Hs)CfTBMLDEgCtqRRvn{Y600-vkt0A)x3g z0Y(21Q1masQ*Jw1ZfPkWg1QazQpr|ncMNJ4OYDz%SO#~D*BcP}`0YxncC~8SS zQ7Zz9S`$#zhJd2B1QfL+pr}0oMI8tz>PSFQCxWNw#yIzR10-0(!l@=jG4|72=eU6N zWfgUg^B+DWMLjrQih8o8s25v`db6dd4_k`*vZbgWTZ;O#rDyCwr!2}cy zA)sg|0Y$?ID7u+|qFV?kN++ObH~~c&1Qd-RpeU1oqLBm?Wf4#`ih!cg1Qd-SplB=s zMdJu48c#sc1OkdC5p{ zXewKZrm>~yR<;yPXG_rxwiL}|OVMp?DVoJb(d`5j-9bRnYyyhr5KuIifTBAID4It= z(R>1m77$Q$7Xd{J2`E}bK+)X<6fGv8=pF)!mJm?1lz^gp2`E}dK+$~!6fGy9=zfBy zXmXs}!T<^0V87}(MT(l(`=S+b0qe^udMM7H{+Sf5;(RH3m@P%C*;2HIEk$eDQuGL0 ziq^5E=ux&5t!GQo1~!TwBcNy_0Y#e#DB4Uw(c=UZZ6ToO2?C0qB%tUi0*am{plB-r zMb8jWw2gqGX9*~Jj)0==1Qb0_K+y{X6zw3O=tTmGb`ntZ62VinGR~cEfCTs1uR1;` zMJwzx{g>kc)|XZEdYpgr7gF>F=S$I>Y$i(2M8$okbt6(2q-#8K+z!riasWw=o12p4iixHDFH>F z5m59w0YzUBP;`WVqAv+3I!Zv%R|FItBY28ljdS-IAi)Fn?&mcr3dNf7bzH#uvWmWo z^Pl}vioWN3DLTQHq952&bdoJaKeDCh6kCc;v!&<^TZ(>SOVL?2ip~*G^fLiPzYtLL zD*;942`IWiK+#14ihd)Y=yw8&E)h`l2LVNY5>RxRfTF($DEga#qALUxT_vFC9|DU0 zC7|dU0Yy%{o|vP^NAMJV8|Q|P8bv$pebI3#I&XjbY(#v(`m&0O#rxBaNl}3Fr6`Im zMbT_23bLgrhAl<0Y$=LkOHn*qib8BD3bRp^KtNF<0Y$|LC@MifQAq-dN)b?0nt-A* z1QeAepr{-HMdb-7sz5-|bp#YuB%r7g0Yym!6jdgm=z0Q*ZXlqj3IRn`2`IXe;3&q(Y74LuJxD@r~d@1U~mZH9FDeA|TqW)|t8o-vKfov%n#FnDLY$+PTM$u3L ziiQzTbTa`(w-8X2PC(Ic0*W#SC>lXPQ6>RJBMB(VBA{p#0Y#$;C>ldR(O3eC#t~37 zo`9kW1QbmqplA{SMcD)tO(uAXdc?cm8z8|(_V-=)l%m@9(e;%0fc0e+O^x@vC!}Z^ z=S$J8Y$=+~mZBMKDVoWaqTAR~G>a`ox3i__4z?7{W}|2h0Y!5OD7uq?qIm=q%_pE} z0RcsK5m2;{fTBeN6x~fg(P9FM?jfLP2?0e*2`IXkfTCpt6x~Na(Q*Qc?kAvV1p!45 z5Ky#|;3>+DcdHv9!J+oPC{Kza?W5}l;{(>0RkS+Z-}$5zt>JtrTFaKAN7z!djx9xx zvZZJ}TZ%TYrRXuX6m4Wn(Iz&EHWN_vH~~dl2q=1jfTAY}D0+&3qNfQc+DbstGXxZE zBcSM60*am^plCY*Mb8sZ^a24zI|wLxk$|F|1QfkQK+($t6um+~(W?Yc(W-cNk^vH& zZ@=pJuoNw__eHP82dpov=&gAFvQtvDi}R&uH(QF{W=qi?wiNAUOVK-QDSDSJMenht z=zX>neZWT1J_3sN6Hs)3fT9lxDEf$iqJsn!9U`FUV*-jkA)x3m0Y#q@Q1lrAMV}K; z^aTM$M+hkTl7OP41QdNmK+!P*ioPbG=oK1$@x!Ut`bo64*^C05>RxF zfFdWPr|l^65l|FCK#@y8Q6#}r^nJYhw*eA-*TOj=Mbj-Qe<)ymSw+zyfBAD#6y$s< zieXDpEL)1=*isbFmZA__io$FuN?=P-B3p`zvr$xnfTEHF6qO>Ns5AjZWe6xLOF&UM z0*cBLP*j0{qU#7Ksz^XlB?5|)2q>ydK+*LC6x~2TQ56D;suECiBLPL#2q>yfKv4~X zrzj9|TNxn1ZT34LQ6cY{{(4KQW+-5NSw(e1{)}IwD24N-D3vWmX>2K~%a)>gY$>YG zmZAo1DQd`;qDE{fYRpDa69S5w5>Rv#0Y%LSC~8hXQ40c!S`tvyih!cl1QfL)pr|bY zMePVEYEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)f~Tl<$i2$|34Usyqa{mG z*pliQ3RquOQQwe%%Xum4$N5s!pDjfL*itl*Ek%RaQZ$$?MMKz9G?Xnx!`M=EGaE&> z5Kxp(K+$jliZTc&8bLr&CILkw2`I`UplB2UMWYEQ8bd(QSOSX15l}RqfT9Tm6ipaA zIA4lpvZd%YwiL}`OVRCYDY}C#MYGvbG>0ukbJCQK+ysMitZwyXdwYb ziwG#Xn}DLl1QgvvK+zHcik1>kbT0u#%LpjCkAR}(1Qgv*K+y^UiXI@KXe9wf4-!!H z5CKK22%e&8Avf_iqiBKsKH9BPbii-M!=ZrnWfeUV^4Gg0Me8_UiXLT4(R#KNZD32$ zV{9qf$d;l_Y$@8zmZHbmQnZDQq9+I_dXj*mrwAx|nt-CM1Qb0(K+!e=ik>B)=s5z4 zwi8hFJOM>75Ky#(fT9-(DB4Lt(Mtpry-YySD+Cn1N&GXjb}C!pvH0*a0hQ1m4M zMMnuJ`ig*}V+0g^O+e8%1QdNsK+$mmioPSD=zD^vXjjNxXMhBI+NWi^rKqv}66A?c z!1}U^PKEq${Ut@GIbVv-u%+lHwiKOZOVK&D6#dMWqF>lj^ebD6&aP;`}mqJIb|`j>#BYXlTIVLfd}k&l3) z2m*>+0*WFDDDo3fRE&V40KrpqGUWbXfCR_cPhvkx(M)?^6cr9wUsh3U*zdn8MRA-j zMe%GY3bCaq%$A}AwiG3@rKmVtib}Ahs3cp8O0iK?nt-A*1QeAepr{-HMdb-7sz5-| zbp#YuB%r7g0Yym!6jdgm=z0Q*ZXlqj3IRn`2`IXefTC&y6jdjns0IN=H3=xHML z2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU2gQA*gIY=8tW*hkl? zQncING4%-ttS_r*K-jXlYpX;1QcZvP&A5wqR|8tjUk|DECEI12q+p)K+yyOiY5|JG>L$s zYyyfV6HqjTfTA1%igF1k$|Im?Dgi~)2%e&TVRxqi5}aVab=F^s;_Ng1Tf+hC%PP7p z?EfM{ie_=X6y462qC419G@C6&bJ$Wemn}tivZZJqTZ-nhrDy>gMRyTUw2*+JMFbSx zO+e9N0*dY-plAsJMN0`Nx|e{WWds!6M?leX0*dY@plAgFMGp{Aw32|L2MH*8h=8J1 z1Qb0?K+$Rfiq;T3MKi+gRRbhA&3>VArWEb8_eE>N0qe^uS|9dbXZ|{f{QIH}oG(R> zv88AuTZ%TZrD!u-iXLZ6(H6E8J;9cuC)rZ;6dOfP6Hv63fTCvzDB4Cq(X#{;Jx4&% zb^?l?C!pvB0*ZDJQ1l`JMLP*7dWnFdmkB6(g@B@02`GAvfTGt4D0+i{qBjXBdW(Rf zT?9|jy0F{E011|{cR!Cx(JcEMZFe|eeOX2Cg#DQTDSDUlrRY7j6ur-uq7T?ow2v)C z``J=-fGtHIvZd%FwiF#?qv#L;MIRGT^a%k)hY2Y9lz^ho2q^lTfTAx5C^|ww(U$}i z9VMXXD*}p+5m59s0Y%>sQ1mSUMaKy!`i_92?+GY6K|s+D1QeYlc#8If-9-jSu$8?p z+ABpH?W5}-!vX8dD*7qxe==H%&T_sKonuSU&ul6Bg)K$DvZd%eTZ%5QrRXACihg5D z(eG>&T_T|94+4t*B%tUr0Y!fiQ1mweMOO$Yx=KLNKLiy0OF+>z0*agjJ#9ykkAR{G z0*YJ$iXsUp@)J;0jDVs50Yy;+6h#wI6eM_xPKVu(43J>9nUQCtXq0`XACnNUzO159 zg8$bTDGGDG6eX~wD3L8i#o1C+f-OZQ*-})BEk&i-QdEX5MP=D2Dn~$3c>;yTKv7i!if$yJs2Tx9)d?u7K|oPW0*Y!8P*j_M zqGSS!>JU(rLhuyDCAcMGjiO`rtB&yr-ZTAG_P!`JAz*!3MfDT>4dSJ!0q09mL$(w( zVoOnDwiGpCOHos{6y3y@qGoIOw$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq0*d+(JVkXA z+#v=?@UVR-R8NY^+DF&@69U$kRWvxke_L3JhH$&%jU}LH905h+2`HLCK+!}3iY5_Iluba< zWCDt&5KxpuKv6CMMR^1iO(mdc8UaPO5>PaqfT9@$Ptm{xcfA1;eB0g^4U(ci?Ux{D zCIqZ6tLTmd|L#O7n$7uAG>0ukbJLAz*!3ML#F_SCo~aUpQZieq~G1dA1Z?U`x?OwiNxwmZIO;Qgn$e zMSrlR=ub9^E)!7n7Xd|o6Hs)8fTF7e6#YX$(Z2)~T_d2#Nz~JJ6!{1!iXfoKC7>vh zfFeHuMa2jx3J_2fML_eJNVDBgZXi%$$# zUsh3KqW{bCQdFGtrKkj3ib}Gjs1#d@O0%V?3|orIvZbgTTZ+oFrKkcMMb{BfRFQz9 zN(2-o5l~c_fTHUOD7t}wqACOwRVAS4Mgoee5l~c}fT9`%6xAf4s1^Z5wFxLnCZMPe z0YxbU6r~bSltw^NU4o}5oap{*fCQhkUm{9K^q%Q2FnA*CB?hc7tEf?;zfwghYRvgk z)PyZXP1#a(6I+U!v8AXvTZ&q+rKlxaidwOys5Ki!Z3rl8OF&UO0*cxbP}G5dqK*U< zbt0gsGXX_i2q@}GKv6dWin=DXG_s=wiIQs zrDz0OiZa{(qB}WXisrGUXg*tt7O(agv>QuM1Gk0l1IFDKrK zh`b@X{Ea>*w8ebO)(L%J!G+G6FH=T^;>@$T*iedjXdVvrj&qz6p_L)WDHHlC!Eq{t zDwlAaq|oS6j#DM{Oc}?i9{R1ERK9cM!5;nt2bIrME?$H@y-?cg}mL*qL+&aBY(E{-!N^k+B6nICH2({UDs z=Jj@*C7}=cI?jEe&;ZAIAk=@55j80G%>?*o(R2=={Q?M ze`Pt&bD@@F9A`&p!8pfxIkbO*o~_l3+Fk`51|hiIL_%%@kNevE;M+tDuf+WErvpQY;L3)_EJsGBc*W|z55d|~@9d-U^#?LW;h z$QQPMxBf6+*#70{!+l}D((=KI2L95=U+FKqvwktM#c{fi>*^M&o7^nbt?wtrN6l`m}n ztnFG~*#2S3^}ewE({7u5Vf)9Gp74e3pEud+3)??1@SHDff5-O@U)cVZ-Isk~`+F{5 z_l50mn%m_I+u!xH*B7?GZRLGm*#5qQ1HQ2R#_=Iv*na2lQ(xGA>*k0rY`^w?%ony_ zJU#9U+pm88;0xO?U!3-Z?eoubzOa1)ao!iUj{tx7h3%*C%f7I^55DSi5_X$kG?AOU zUvi19{N~22XNvjIng4uie=@(uinlgTP<##Im)Tt0$a8!RHGVJ`^)=F1>YC9weqR2? zUNXP_d`TPe4+G$4AjNYV~_D#m>P3FJ0@J+_)P3ltd<|KdN^$5k8YiHkcIR6E6lO^b9qIZ&5$Jeqf zSE5?k1YcsYR%IS)Q`Wx6;`NJMy$a@yl(_p&pZPeYnb(zEe5cQeD6_mx8S{ax ztn8%t{I_G?u=zMwF#p-RTl2BX|G)j8Wm5D<(OuJkaGeZuN`&u9e4OJmKg?zAtz4&0 zN=`<~sNBgZxjC6BIqA8XS?QB=vh%Vs^Rh;!WaiA6oR@7wX4c55Ia#?yUS}_FF5M($ za?aR^WAnyN%W_i2WKYaW$(WEeJ*Ccs?97Y_DY;`ZauoA zc1m7$_Jqta8Dl5qri{+aOwY)fn39&7UN60FYTdN-v{W0DO-!DYJt-?WD`UjizG&n$E#AtPRg7xb!1k`#Ei@_V<-Lpel>DufC#Cl@KbO(HCQQvu@6)4)D}%pL9XC%Wa6YNu54`-`Rc6N{M> z3Xa#CM;5-4{up}*`IGFyygq*>nTyrUzj$$TR^`h6%BlXu@+MaH7ypm9!P`vzkGEC1 z=-aB3|F%k+(~39q`%)qT=GR7__8rqZq;_)bF|BcGr}Potiw)}+yx5>^!HW$W>yq^w z(^_+KYJKl@?c3@yY39OXyJcrjPIJ1q9+cj;N58t>+iu4x4GP|0BT~J>_glB%{kARg zCUphtazev`OEt;APE#l4jvYNIYh;qSHS^zHTV1cT4!jlf0zb|61wW58b7k@`-^5%j zJ>8sLuWq{c7ShZ+9X~C$E_6_6#E8Yu5u0kVDH6OhESDFv3&TCNc#?1BMoz~Um>lI#) zwgqRTwdGxzE3PxFfFk#N|5v}>+hvWII@&RJl9NVfrDshVIW}Wb`h@IBqrIP?xk=2s zH}@(?&>vpll2!=P{4DgYK~liM+#}>)fwV$hX@-~A zQh8+|xU>%3G=xJ1AY1G;>{eF|F_;Qsf41q|><(JUjLc zHZJ^dnGdG-KI-z$3UB$I<|-G8<^C`YTlUrV4Vh!Xhg69h*xVE8RrLx!*ycmV#S4jW>vQ85+~AGPM>@NJ zb>XeYXA65Dqc>;H;SC$B-Ur*f+x!>IM}pTCTqX0qOtT;Ue&+MIF3*YPmdh`eL;fcr z?{iQ4g0synpto3f4bWgdLV8`nt!{1t?>!VMGWRa#Qu%K@|5fI;)mi3qgI+55i5Q{Y z`R4A`-p}QDAC)xkpihj28qx|m6j&`(U_R%Xx1T#EJ14K;)0|<+weW8Ag4?^`6SDaQ zm46X?o8${J9}Vw?A_NL=@-*)@|G#|D%wulvp_si6+`wt(=bnFE%maY@BR620`Q_kU z$s#@qIhdb|KGbREA&YlGbH|_;3T}}!4~u<|MLq+h=?sIU@b)qc^-TFz@bFwC6W#nenNJ^fVIeBXHOmhQdO;4U!ubv5cW2R0VVUD9FWM||h zn@91@&88Dfqma|7#>Y{XakH^GLPufhuh5L#v)0`WAdLPvdcE z;bY9ghn9tpEX}<(H@$hdiX`vXm%XM1ze0F`TKL$p$U{dSpB6q&R#=;(cnWYT+# znEyer4@~t~HUB5;{dz9=0PyR#fHkV^1Jv;acd0xMEqtt4_)rnw1vh@dBhi9~m<5j} zi~K?={N+&iSdiPg@R4A_ZRkCmbUL|*Vv4lYPXg3&@7+Jzs(pTCo<16bc=PU24;HwyMy|0e_lE8oYQ8Yz5 z7p@h3wQHX@7Wv`oOA;j4K5Z=W!!=JC%@=!${D^cC%<5K93cr|Plk1o-Ru%c-I_3*P zMSi%B`TBB^AFgA+G*bA(bpZUt7J(e~<7kj)xNBfm5yW8tH)Vyr>XdTy^ zo6GKJbo|kL0POxv$J*w`vAc3GO|VD0O_*0EF-Z{MKfup7NSR>#N84PY<-td6H^di#=&b&|b(la6`jhO(ER ztK+L_-hNLUc{_Z;#h;Q)_Q; z*YT&e-u_d^)DGTmuH&>$-kzu9>s`G4fsPT~y&clAQ%`UA*YV!o-d>~Qr+vNsosQ)O zc)Oa8!v}eLqK=Ob@%9Tko*U-vzjUmd?(LR3PS5c60v+Ep(Cx=#zmAckyq%z9moeTR zsN;R(y#0udpHJ}i2^}kBd%K2?Bc^yeTgNAIz5Sw&zfAS^6&>qO_jYR?XU_EYLLGO_ z^7e;17Mtzu;yQMl>+Qih-apUVkLq}2fwxcUSaFfJYw0+0vA3t__|y__zog^&d%gXS zjt!T4yRDA1R(Shv9p7H*?Snc-t@3tB9eb?y_D~%kSnKT#Iv!o;?Nd4?ZSZ!oj-xhu zJ6Ff8o4x&tju*Fh`lobb?b15-dcoT_>-gY{-rlI= zG4l;D>*U*p0^L{ z7`xBgWp(Uxz}x9MuKLK^n|1u=khjn3Smm&{({vp7nYVA%@wqR&{f3TznD4{cpRaq= zJ2pG!9XsoI=QrM7rsMm^z5SVv@h7}pUdMhXy`7=s>Qmm{qT}&1-u_v~8_#*Wo{kfK z@%9WIpFi*Iw{*O0zSU>1um3mi*y56R?5gAZKfS$N$9?9zfcElV=or50?dxt39sf4pO|&~;{y2|4 zwld#Vw8!o`-etbOX!i;o514N>+Wn=DiRL?wc30AIkonf5-B~)WGv9->`)M72FyD-{ z`+|-&&37g3ZlvSnByZoY<4*H^O8fdfI#w{>?6bRuj;Z$Ocbt~m-EikbM026meY)4l$ji$aJ7Q{{d9(l9ALika5$!$xwC9+IAOG>gd>He8R5t&&mvg=O z-!5lgXMa>P|CyWR|MPOG<}&~F{SGpXANF>%KWdx*%tJ`0mHE&9c&@20|Lxn`)n3N_ zXW!pQ^B>p2yyz@3|6Mj#_`yrVO(^>IUN&zp)dc(YtSR2!Wb-oTm=~S-)qGCRB7qn0 z{4bX~T;1m+*%S1G%iUpi(f510tuNoMeZRKzepi~8Imf){{AS*sHO>!SXFe_e$J@JH z zVE*Ihd&InKetMJ5A^*pD^Y)rD%#rtHkJz@auHD2qFtMb0nYU-(zI~rXK3vW)rP!GJH&VB z)TvYFk{vpAx%TJ3*E)6W)TQV7?Xl&CxBBC*KvGhti#wdCz61@`y3^|BvPW|NH#^5B+jehn*cFtJLdiE^DsR zm7~Wlhm-83j$JOHV;LPQJub)QzqGkckIPZ{ zFU4L6$M(1!S^MK7<14L+D(Cani?~q2A90~fWWZkT+{l@9@tz){zc8TpA*U9X+>UD@simDP>_1G!rt<2&T zTXY?G^W3P3iJ5~(J$088F4fAJ;>_89t3TtWdh3r@8B%}Y$&}1fJI(!oXEM_Fjk)8A z9b`V{Rqe01B0nO0#U8WIbA3@+L34=k9}d_fW=1FNP#<59`XG$*pUW<@jWI*~OruQRir`8((} zE0|f|iL9kr-pmG0WNpoIW;Qf`jh$v$GaEUPbu`PE+1QCp(JXCd6Z0qGHA|V9X0BG6 zc1gR<^{T5~!ftcL>S-6Z+g!8y+KG0XtJXj}!ESTi8fu5_Hdn5ZcF1mX?HX&x+ik91 z6YV&=&Gl=l9cy-7bNz18jG&yUq1$t{rW+xqdCQqwF@K?6EpNH?7-A>B14q=%-2^wgA)UYZipTT?>% zXi7+5O$q6zDIxte5i&pnPPwGlE*8zDDqBjgrsgrsXDWVkj$ zGPDsgLK`8O+6Wn`jgTyDgpATg$Y^bZjL}BOSZ#!i(?-a6ZBIyN*Zz%y!Q0HEpU5tr zkY(n6Dsn==%CSNw`!ASR<_npkQzaxvQ$lhzB_vN%LZ)g;$TUp}xm8m_rfW*b3{44{ zsfm!=v=K5(8zHxABjgTkgv{1P$Q*5i%+*H7o!SVQr;U*L+6Y;ojgY&v5wcJlA&ayT za;~hWVR>df}s()JYeNm zAuIjG&F7?iArIlOkG&6hz!UPOeR*fV%CSOT^*1ngD)~ZQ z)2R~jx~7D@p(!D6YD&mkni8^0Q$luYO32%q60%2ALiTDR8UZG`OCM#uqegnX!tkdL$xa!?x~hqMv$u{J_J(MHH&ZG?QPjgZf@5%ReYM#y<> zgj~=@$VF|0{HBeN-?b5PNgE-5Xd~oLZG>FbM#x{<2>DwZAy>2!a#b54|7auRUu}e3 z)AodX?anl}e=uOam=O6*zL1z5_CCaXOVQGCVk09Xef~8e$BDDgX8b;#UCC_ou(uey zqS@wQd4PSL+2&z+6uW}i=3#j>yS&-vVR?{U&TR9rJceD?Z1b=@mR-hd^RPUQUD|B( zusoh!%53|*CPXM{gSm!bLJ1qpRZJihx4~S;L_(qs=1LYPB-miCWeGyq26Ht_5<)hZ z>sg8rZ-cp_r3rC1m}^>w5Nm>chEtXhV}rS-Dic;88 zl**Q(G`1AgWlK>#Hj3&KP}G2cqJ{(%H6oy>F#$zQ2qeEeI%T zNkCC60*YD_P}GKiqP7GSwIiUYJpn}>2q@}EKv5?GiaHZKMb&(6G4oq8Vm`1>gQ`o> zx0X~FU%>jZihB6`)yx+k^A+{vd@1V1mZIKlDeA+PqP}b?>c^I%{%k24z?PzcY$+PV zM$upbiiQwSG?aj%VFVQ2OhC~s1QewcP&Ax?q6`9xMi5YxNkGv^0*bN-C>ljT(P#pS z#t=|6mVlyh1Qd-YplAXCMH2}qnndsvb@RF143L-|W=3|GqT-fRwl83PSw*=%|HM*K zl*jo}G?gty)7VmUD_e@Dv!!STTZ(3~rRX-c6wP8w(d}#$-9bRnYyyhr5KuIifTBAI zD4It=(R>1m77$Q$7Xd{J2`E}bK+)X<6fGv8=pF)!mJm?1lz^gp2`E}dK+$~!6fGy9 z=zaoWIU0Y%#hD0-fNq8A7#+Cf0kiv$$yB%tUe0*YQHc#0nM zxkn6;n6Q2N^^g=bu!>&s1*|Wt=nbF$uX0lKCg)4hTWl%X#g?MoY$EBB1DF0*XE%py)6G zMV}H-^cev~pA%5@1p!4z2q^lJfTE)W6n#ZN(J=ywz9x8zUh}yX&F>e8DR1wKUYDYG z?W5~&d;#mrD*E2%Z)tvyW&VB93C@?IAJ|fKk}X9)vZd%0TZ&GzrRWS>ihg2C(OI?> zonxcuX99|TA)x420*cNPP;`NSqKgC+{YF61?*tTGBB1CG0*d}5py)CIMSl@c^fv)T zR|qJ&N#)5d=@sai2TV0Et;|f49zeQuLI)FLEOS z)|XWji106{Bt=o2FGbO8DGIWsD26RXv1}=dV@pvyTZ%$#DGIZtD1nWlL;{M66Hruw zfTEHF6qO>Ns5AjZWe6xLOF&UM0*cBLP*j0{qU#7Ksz^XlB?5|)2q>ydK+*LC6x~2T zQ56D;suH*_x{-jQY6MS_Kf-;=0Ero3z6T#!EW&%H|GK>|svZ%rzO16!5&r#^r6`&6 zrKk>Dic;88l**Q(G`1AgWlK>#wiMN8OHl*16g6a{s1X50jR`1fLO@Yd0*Y=Tpr{!E zMa>B)YC%9zO9F~o5m3~cfTA`86tyLws2u@C?FlIAKtNGP0*X2jP}G@#qAmm!btRyv z8^KdlGr~P@fW(ZnUv#V`Md|jLe)oug^<@?Hj_@Z`k)l4FFGYRXQq+$vMg7@QG=MEd z1KCnEh%H5f*-|uwEk#4wC>lmU(ai)D-9kW7Isrw)2`I`SplAdEMVSN?jU=Ebi-4k0 z1Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTBqR6lD`oG?{>+DFjbZ&j`1n0TR>R-WTt6f`FnY z2`GAsfTE`fDB4Ou(K7@TZ6l!QSptflBcNzI0Y%RfQ1k);MLP&6dXa#lodguUL_pEY z1QfkOK+&rN6un096g?c_zHNZSobwqttEH&2y)Sw_B4B-4MY|&WCu&O3ZqApYx7kv( zhb={W*;4clTZ-OgOVN95DSDqRMIW%GXdfFz`w1vIKtR!l1QdNlK+!=0iVhJ_^f3WN zpAb-Vn1G^B2`KuEfTGU{DEfkcq9X(peMvykQ38s-BB1CP0YzUEQ1lG}Mc)!obe!NR zdNaa}s$~>CZlCGDB}HlW(e-x`0qe^uIvL@wkt{_&a=sLuVoT9!wiKOVOVLkkDLTuR zqH}C1`k5_7zp$m~S2l{y6Hs)4fTD{86#Yg((eDHlT_T|94+4t*B%tUr0Y!fiQ1mwe zMOO$Yx=KLNKLiy0OF+>z0*cJVtPc#2L$ zxIGMznCI<%(GOD8&3;BJ<_4@Ut0?IDvs0ufhV!K;mMukbY$=LoOHqg|MParSC9tI^ zku62V*-})3jiQnS6qO>Ns5AjZWe6xLOF&UM0*cBLP*j0{qU#7Ksz^XlB?5|)2q>yd zK+*LC6x~2TQ56D;suECiBLPL#2q>yfKv4|>ifR%(MNzK%fB_OS-Tro=XxDqD|Gd2~ zs^tc(FRLiU^}m=VMX8)GMQLm)s>_z5dTc4G&z7PFY$ti+^o997i;;b$=n4CU?5S?R`m%~MGFWhx{H9Kg#;8WBB1DQ0*V$BP;?IgMN0@MT1r6C zy#y33BcSL$0*aOsP;@^5MJos>dVqkUl>`($NI=m;1Qe|zpy*+Or|4GK9c6&Tl(qLo z)1|1I{fxHS4Om}R(K^?^u(1?9%K1{Xo-IWi*i!TuTZ%TarDzjdiZ-*Q=yA3bZDC8% z6KoVcNkGw41Qb0@K+#qLik=~$Xd3}V&k|7d905h!2`GA=fT9-&DB3|l(TfBW?IfV+ zB?5|GCZOmQ0*YQGpy)LMie4w6=nVpj-XwU6*1GOi10?2Od-wB*6cw|i-f{!hmsPaK z^?zvo_-p=mWA}2t6urZiqIcO+^d4J^-e*hE2W%s{+)E#0}V%uI&NCzF{ZVu*mE6atFE1QbOGDDnv?N+qBuNAyD*L zINa3%iLJH=)SpYyoA$InJrXrvrYI}oAKP1svN^vL<*=nF&X%GCTZ(eoQdEO2MK#${ zREsS|wb@cshmE4T1QgXHpr}3pMGXijYDhrQVFVO4BA}=-0Y!NP6g45Bs3`$O%?K!J zPC(J&1QfL(py&t!idqs-)QW(j)&vx_A)u%&0Y&WyfudL>e3}CiJIC&eG9$q={Y&l3 zTYe;JzD!a3h`*(;6m{VIQq++xMV;7E)R`?sUD#68l`Tcx*izJ;Ek#GNrKkrRMLh{9 z>P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_V^L_pDC0*ZzZP&AZ)qG1FS4JV*z1OY`O z2`D;>fTB?Z6pbdJXbb^GV+nzx!btcj2PC$_%}9|Hb+tRDagnI`GDXKk{QdosA zqGQ=oG>I)m$FZeoGFys{XG_ruY$+;cOVNpJDJo&3XbJ&EQwb=VMnF+10Y%dZD4Ib) z(M$r0W)V;{n}DK|2q>CEK+#+RislheR7OD2d;*FV5Ky#`fTD5&iYf>wT0}t6Vgiaz zCIpHmM8X*ZoT3``6Of~&Xsz8BEr~?Umnm8v@!JfNqEk7)6rIMFqSM(@bOu|B&SXo` zS!^jzSMe7JCT2DaH zg#;8`L_pES1QcCDK+y&QiY_If=rRI|HWE;@iGZTZ2`IXPfTGQWK+&>Dc(el&`^27> zogzig+pmdS8Ht)NQ?xbWFBl?4*KmF*x|S_P*RiE&8(WI5XG_ryY$>{tEk!r6rRZk1 z6y3r`(RKogZY7}THUf%nC!pvK0*dY=py)0FitZ+$Xa@mB_YhEYF9Ah62`IXcfTH^e zD0+Z^q6Y~mdWe9chY2Wpgn*()2`GAufTG6>K+D$kkHxqCL8PA`&%U zrs$c7zjK%r?c)4W^ekJ7o?}bV^K2=4fh|S5*;4c(TZ&#{OVP`0DcZwE(Ov?IULm09 zRRW4$BcSMY0*c-spy*8kiryli=xqXu_7PC@4gp2)5>WIW0Y&cT|CfTGU`fug4(;ddR7*ev@Z_Ouk8W6$(Ik3`LvDf&9%|2;yAzTx~* z^etP8zGF+#_iQQpfh|QpvZd%JwiNx$mZD$SQuHeuMZXbH^g97X2M8$ogMgwx2`KuD zfTDv06#Y#=(LV$f9U`E}^YyeHMIi!;QV1vt6HpW(pvWhnD3ySsC;>%j1QewcP?SMH zQH&5M`Z5x3I?^dBwf~anD=B)-zM^INQS)Vr;=bR1loTa6zZB)NrKkp5ifXc@s1{p_ zYO|%N4qJ-qvZbgVTZ-zlQPhBdqJ{(%9Y#P=BLa#V6Ht^#Kv5F{ikcEo)Qo_l<^&WS zPC!u$0*a0xpr|DQMXd-ZYE3{<8v=^j5>V8RfTDZ?iV6rQDkKDovidBU(UTi7q z%|=ll0*d+)P}GlrqW%OF4IrRsAOS^#2q+p%K+zBaiiQ$UG>m|v;RFzD&_1-+y_W z6dlL;rD!r+ijHSX(FtrRDrQU3iEJqPaY zfTGz16rDss(HsJb<`PgekAR{w0*dAnP_%%6qJ;z$l@m}@K|s+W0*V$BP;@c@MN0@M zT1r6CGD4teq96Xn0f}8`4~34EqOHd~6$VN20!wiKPqM$sAqiq0dTXe|Ln=MzwL0Rctp2q;=lK+%N+6kS9> z(ZvK5T|z+71_FvMC7|ds0*W>gP_&7FqRR;=x`KeB%>)!(NkGw61Qcx{1d2}e!`&T_ zSU-bvniTD{`=YD;sQEHQ*ZKZ&6QyVy=a-`E*-~@^TZ(REOVLeiDY}_0MYph}Xggbq zZe>f+ZEO_XPC(He1Qgv#K+#Rv>0Y&!{Q1k!+MGq2C z^bi3>4--)I2mwWp5>WIQ0Y#4!Q1k==MNbk?^b{dbbd4WA!vTq%Z{KyiR*H7Hw?&@z zqvp#LJ?HydCrQ!soL`DwU`x?%wiLa{mZF!~QuH!giuSOjXfIoeUSUhot85g#MnKW) z1QfkNK+&576um`2(c1(R?IWP*9RiBpC7|d%0*c-zpy&eviasQu=pzD(J|>{(69S4p zC7@_O0Y#q?Q1m$gMPCq5^d%usw95}aROVO`vDf*2qMZdG9=l~lRJ zSp*bi69Prw_~Fdsog(|WYvfxgdd{Bq=cGo>mno`|>bEPFqMDpvifXZ?s5V=Q>aeA# zE?bJ~v8AX!TZ$U6rKllWiVkC=s1X50jR`2qBcP}W0Yyy-C~8JPQF8){4kw_f1p!4z z5Kz>TfTC6e6tyOxs0{%{Z3!r9M?g_N0YwD_6crLsR75~gdjg6&5CTPs)bLmbB(}*O zUFW6-&-5qR)BcXBQS)Vrx~BT&B~sLl^Gi{8wiF%7mZBbPDeB3VqF!t%>dls-K5QxK z%a)>kY!vk;plARAMFR;a8bmJU5KuIffTCdp6b&b!XaoU8BMB%vih!a~1Qd-X zplA#MMPmsl8b?6Ucmj$h5Kwe90Y%3UP&APcDC(RV-sphDHrV5$E>g6|ejIXaYSet0 zqT^Hj`=?6L37lVwirG?hB3p_|*itlwEk#q=QZ$V%MWt*hn$DJ@8Eh2IB%o*(0Y$S3 zC_0INqB#T<%_X2{9sxyV1Qg9DplAUBMGFZiDkq?*f`Fn$1QabMpy*@*ik1*iw3L9N zWdszRLO{`S0*X#01d5JJ4ZrVz#6Gm&FPbbx57>jG(^8}6%M_iJ>K`hVq7|H9idM3v zXcb$E&Sp!|IczCf&6c8b*;2HIEk)j)@XPe9Ry1QcCFK+(kn z6kS3<(FOvFE+wGoG6IS=5>T{>fTGI@D7u1xqRj*pT}eRERRk1mA)x4L0*ba0P;?C; zP;^FWxcPLa=pVZ;I#Y`BlTX-Eqvp#L-H_@JoGC>&a(*egi7iDpv!&=3wiIn=OVO=t zDY}gWII z0YwiJQ1l1^MUN6t^cVp}j}uVz1OY`)5>WIM0Yy&}Q1lD|MY{-rqHU?+*$zl-zdfM7 zUW$&g@oZ|;e3_!%ss4GhrRYV@FGVl0rRZh06zyS4(O$L`y~38FSJ_hZ8e589XG_r= zY!tmoK+#(S6unJA(LMr--XWmqT>^^UBcSMg0*XE$py)#aiasKs=wkwkJ|Up!Qv!MPCw7^c4X`UlUOD4IxnUd}{a(2PBqb52#;|qMr5@?c3C-`7%X6 zruuv5NYPK6Uy6QaOVKZEDf*QyMZdA7=y$dh9bik*A8aZ5lPyJmu~Br8fTF(%DEfzh zqC*4}c~L!WM^T7?q7(v(!UPmW2q^LiC`u)uC`v$48UaP=1QcZuP!uDeD3gGqECPzM z2`I`TpeRm2QGyUC`aU)Mn*$QN*Y19PkfMj}(RFS#YQ9WS?WkX;Op5AoekrQUmZExW zDXPzwq6Ta!YRHzN!`M>Ph%H5p*;16pMo|+2ikcEo)Qo_l<^&WSPC!u$0*a0xpr|DQ zMXd-ZYE3{<8v=^j5>V8RfTDZ?iV6rQDkPw&h=8K@1Qc~3pr|7OMV$yJ>P!d})r^LF zI3Tgc_DsK4Gz#O|27M5E@*6df7$k6$1~JvhG<^<+y?FSZo*W=l~YwiNYcOHn_z z6!m9I(Ezp-4P>Ke5CKJl2`CyuK+#YFiiQzTG@O8<5d;*CB%tUh0*XcvP&Ar=qA>&% zjU}LH905h+2`HLCK+(|z6dglA(L@4@jwPUI5&=cW5duZsqT#a~kl6cfM!HMU-F9Cz zIT|%zrs%||e{H!Gm2iG3n!=W%scb2l#+IT|wiHcgOVJFr6wPEy(JZzU&1R$MBm#=& z5KuIifTDQ>6qONBG@pQ?1q2i=B%r9AfT9WliWU)2w3vXRlL;tVLO{_{0*aOqP;?3b zMau~&I+cK;(+DU!oq(b<2!Wy#qTy#9kXRpkT2?GYsrKdV%xKhnnW9xu|I0;EbT;Rg zqI1|%w3;nN=dz_}4O@!NV@uImwiKPumZA&TQnZeZqV)t6T}VLDMFbRGOhC~k1Qcx` zpy*NpiY_CdXd?kdn+PbnoPeS$2q@Z2K+%;16kSC?(G~)Vt|p*pD*;8<5Kwe20Y%pl zP_&H@C|VH>XD@b&wz?TvDMdfoH;=B5M$MNgx;g3>ERmvHIKLEaXG_toY$>{pEk(Dp zrRWZ}6y3>|qPy5qbT?aycCb-&4*^B@5>T|0fTH^dD7v43q6Y{ldXRvkhX^Qon1G^3 z2q=1#fTG6;D0-ZLq9+I_dXj*mrwAx|nt-Bb2q@Y`K+&@V6g@{k(es2r(T&mYcn2i* zrTr&pH%U=1yDxen8Z}?0=;f%tXqgo4;rvpxmn}uFu%+l#wiLa_mZI0$QuGE}ir!>P z(OYaOdYg@+eFPM}LqO5H1QfkTK+*dI6n#KI(T4;SeMCUf#{?98LO{`{1QhKjpy)FK ziasZx=nDdhz9gXND*}qXCZOmW0*byRpy)dSioPcVie8L{FLyv<^X;L~OH%ZO-5323 zjhZi0^h?x#aJdxy%K4?}H?|c0&X%GBY$^JKEk%E_rRXoV6dhzs(cf$-`iG68Lj)9g zX?og@q7VT^DFhUS2`GvXP~;O(luAHRlz^f%0*cZJD9Rw9C`Le0CILlR1QcZxP?SSJ zQJjFH1OY|41QgXEpr|GxQ1nwY{GkI9JHdW2?Pn=!W29=OMa`Efs+Z=6PM4zkoL`C> zu%)OWTZ#^2OHm`X6g6f`Q65{0ny{s)DO-w~u~F2VfTF_*C~84K(Gdg`wIraZ6#+%9 z2`FkqKv7!)irNuSlutlW0RcsY1QZn!P}H7)q7DQUbtIsu69Gk?2`K79Kv7o$in8GW(UHx@o~P{e$+OICf8qnlDq-E6pE#rWEz&{8H41Ek%9VQq+$vMg7@Q zG=MEd1KCnEh%H5f*-|uwjiR9h6b&PwXgC2yBM2xONkGw21Qd-TplCD!MPmpk8cRUY zI0A~s6HqjPfTE)bC_09KqKO0)9ZNvbBm#<#BcNz90Y%3XP;>$zP}CzWJjVfvHMNIA zJ*DUhyDutEi<&P}G&RjXe}xoHgP_&7FqRR;=x`KeB%>)!(NkGw61Qcx{py+A>inbC^bPWMT*Ah^49RWq# z2q?OqfT9}+D7ujlC^|bWe82&TW!Q7HbEL?#N7px{Ma`Efx;4$Ow_1vB{nEk$>;rDz9Ritb@c(YRJSp*bi6Ht^xKvA54 zq67g&xdar|AfTuw0Y$Y4D5_0BQ5`~{=-0IH^A1St47>aJO^WK+sGA-&U#6&Gy8rbB zQgj&Sm!d{&DQe7?qCB<~HDOCpQ??W}V@pwUwiF%CmZBDH6dgf8QA+}fS`kpxnt-A< z1QfL;pr{=IMfn626%bHVNI+2$0Y&WzDC$5!QAYxbIuTIRnSi1$1Qc~8pr{)GMcoM~ zI+B2*9)v(q{q%5rol`W)9#A((51#2?V54Vx)O?wuzUh9^g;Lay^Gi{GwiFFuOVL2K z6b)ia(O|X|4Pi^sP_`5eV@uI+Hi||NP&AT&qN4~X8bv_SXab7H5KuIhfTD2(6pbgK zXaWI6M-xzV3;{(G2`D<2fTBqR6dgxE(PRROjwhh#1OkeR2`D;|fT9vYps06x_-F?t zHq-8Y`bg1l$tP^-QS)Vrrl}0y8rM7DO$_abM1TAw@cAi_8e_*denTGqSw>?p_fb18=PN?-egPBTWl$Mn=M8A z*i!TkTZ-OgOVN95DSDqRMIW$H^dSL79}!UWF#$!N5K#0f0Y&=>DEf?mqR$B^`htL> zF9|66ih!c82`Ku8fTC{+DEf|oqVEYP`hkF=9|iGZS?2`Ku7fTCXsfudK_!}A=F zSgFBzO^UXsx$#?i)O?wuKhynno2BS4&M!p=*;4d3TZ;Z+OVJ^=6nPnX<}O7cwiKnX zr6|mnq6iyBJ^@9k1QbOHC`u!sD4l?!3<8Q`1QcZwP?SYLQ8ocZIRq5N2`EYsP?SqR zQ4Io$Y7$UXi-4lq1QgXFpr|eZMfC_Ms!s?M9Y_!Fa6n>lds_B~6rErXk{V=0&6g=^ zoZ-KIl@#T1ekp3gmZGL?DQd=+qULNVI-D&(9x@dOl2AfV`I z0*a0yplBiiMaL3QG>L$s;|M64OhD1`1QeY>Kv6LPMJEzaR6;<}6atE-5>Paa5Gd-G z5$@xF#O!Y>iu9MFn{1S3M9r5enw8;~Tq{MhIlmO0#FnBtY$=+{mZEuVDJo-2(R{WP zEnrL0Lbeo@vr$w*K+z%siWU=4bTR=&O9&`hNRv&0YxhaC|XHC(JBIp&L*Jf90H0~6Hs(6Ay70UBYd_465D8ZKQpE11ACCP zCL?OTOwk1y{tertXdUO5qV;Skx{xhJ7qO-2Vzv}r!j_^9Y$>{wEk&2HrD!7?MVkmH zx}1QbD+nmsOhD0<1QcCGK+zTgimoQ0Xe$9l*AP&2EdfQ>5m2;^fTHUOD7t}wq8kY) zx`}|In+Yhog@B^%1Qgv$K+$c4K+)Qa@NNercAEVd|9mORvuFCZXGG1HDY`qu|Mmtc z+QIpy=pMEd-OHAuoop$(k1a*_v!&<(wiG?cmZFE)QuHtzMUN0r^e6#Ej}cJxH~~dZ z5K#0a0Yy&{Q1mnbMb8jWw2OeEX9*~Jj)0=)2`GAjfTG<56un45(Mtpry-YyS9s-K? z5>WIC0Y$G80!4RbgmZ7SuW0t0A$Lj9K_m5AM$~+nqPH^q4mV5D+nisD_OYet9kvv` z%a)?|*i!U9TZ%qlOVNjHDf);lMIWDUkE7rm4Kq(2q^lUfT9D0K+zi+ z;fW4NteHJ6dsB+K+n2XLGNR_o6#bpyFWoLh|8RaOI>eSDFQ#YiQWRoKQ3_j%!fYvu zu%*anOHnFYilS^3r4dk+PC!ux0YxzaiZTf($|9gBn}DJm0*c}U6eS2K$|azv1_4Di z2`H*XKv8W1is}$hRF{CFdIS{JC!nYS0Ywc7C_0P~DEccSe3b(dE3o^bgHm*SfTB(W6m=$`s0#r_T?r`aMnF+_0*a0#pr{7{MLh{9 z>P0|NZvu+?5Kz>YfTDhcKv7;S{HX&H`^0`4+awk|(_d!yMg3z@^JR(#$9(@zDH_80 zrD!NyiiWYJXgFJnMzE!5BwLD(VoT8|wiJzKOVJoMipCO9G>(9x@dOl2AfV`I0*a0y zplBiiMaL3QG>L$s;|M64OhD1`1QeY>Kv6LPMJEzaR6;<}6atE-5>PaafTB_Yil!4# zG=mT*8W;<=c0gi#?YoYHr06{Nw#dv_)O?wuIWd3u-BL7{^Gne@wiK1IrD#4|iWab? zXdzpQ%Gpv>!Iq*$Y$;mIM$yRx6fGg3Xej|j%Lphsg@B^v1QeZ0K+$Og6rD~$(HR63 zok>8^Sp*cVAfRX^0Y$3_C_0;fqH_o+T1`OFxdargA)x3y0*clW0!6c9;rR|oY>@pj z$VpOkmOaxyKNdA#rs%?$f8jk+bP?y5qKny5bO~FEHn64WQnnOb#+IUuY$@8rmZHnq zQgj6yMVkpIx{`pRs|YCCLO{{g1Qcy0py(O`imoM~=sE(5wh>TtJpn~G5Kwd@0Yx_v zP;@f^MYj-8w4H#WTL~z-jew%t2`IXQfTBAIfueP>@VyR5Y^&WDt(T$#`-*l~ENZ?? z(Y-PM&7D%Tlk-c_eQYVZpDjfXu%+lhwiG?YmZFE*QuGL0iXLT4(PL~BJx)N;69g1J zNkGw41Qb0@K+!V<6zw9Q=ve}ao+F^>c>;=FAfRYB0YxtoQ1lW3MK2Rjw1};RL-sTMd!*<#yDxe(7Byd{=$)8<*aK4ZF6Wn` z_t;YOK3j@DU`x@5Y$^JPEkz%*rRWp36n)B;qWx?XeMUgh=L8geK|s-$1QdNmK+)F( z6n#TL(YFK?eMdmi_XHIEKtR!t1Qh*5K+(?x6#YU#(XRv){YF61?*tSbAfV_E0*d}5 zpy)3`py=&bxSsRH3%rGNkCC8 z0*Y!AP*jJ2qPheW)gz#&J^@7y2qV6crOtbRq#oB?J^rA)sg~0Y%dYC@LkOXgUE!GYBY} zNkGvo0*Yo60!2eI!!;jwihTRg*-$C6zi=jUQfAbAnWC~xztfXaG@tWJ(E_#-%Lphsg@B^v1QeZ0K+$Og6rD~$(HR63ok>8^ zSp*cVAfRX^0Y$3_C_0;fqH_o+T1`OFxdargA)x3y0*clWP;@>4MHdiIw2lxcnwuG( z`Eo7hrxIa`XZU`x?v zwiI2-mZGcJDB40m(bWVLZ6%=S8Ul*0C7|d!0*bZ~P;@;3MK=&obRz*pHxW>DGXX`n z5Ky$8fTCLoD7uY+qT2~5x`TkCI|(Sdi-4lL2`Jh@2oznE8NS*9iM6)pXctS-BgrRh znNjm)itf+!AKxWK4{&}ddXOze53!}_VYU=K!j_^(*;4cvTZ$fMOVJZ-DSDEPqNfNb zdYXWuX9y_TML^NB1Qb0-K+*FA6um$|(QX2YUL>ICB?5|GCZK2!0Y!TWD0+o}qE`th zdX0dh*9jxlf83xwl33Wk$`HDSF@i|E!;v zq7OK~6n)5+qL0{8^f6nCK4DAIr)(+O&z7Rk*i!U4TZ+D5qv%TlioPPC=xYLsz9FFK zTLOx{BcSMe0*Zbhpy)>eihd%X=w||oej%XfR|1NDBcSMa0*Ve0Q1k}@MSl`d^cMj| z2MH+pn}DK!2!Wz^GsA5ikl6e7GyV6ZsGdF3Ka?3YU#2LW<&WGgMUkw3KhyWwQk2S; zq9|L6(%4dz&X%GKwiLzKQk2P-qAWIwvI!{4A)qKuKv9B#qFe%sY7kIVlYpXH1QgXK zpr{T3MRf@%sz*RkeFBOa5Kz>RfTF_)C~8DNQDXv%@(3tuLO@Yd0*aau0!5*$@InV9 zw$9+BWChRBYPh#WnrB7LmnmwQqIPU4%4bVa0b7a+ z*-})*mZJ7-6m=k=s3QSIod_uEOh8c=0*bm4P}GfpqV5C~9Z5h@4+4sM5>V8OfTG?6 z6!jsXs4oFU{Rk-PPe9QC0*VF_P&9~uqQL|d4Iu=IT4aUqb3kIP49*c!)XcuT4b6(0 zFH16dlF+rDzmeibk`gXbfA5#2`D6fI^;(aCHnTEdp1rEDo$#+IT}*iy8djiOTtC_0URqSFZ|I)i|sGYKdV>j)^?MnKW^1QgvsK+%l^6x~EX(ai)D-9kXo zb^?lSC7|dw0*Y=Ypy&<)itZ$!=q>_^?k1pU2LVO*5Kwe40Yy6rfuapr;WZ9OtcCrq zAOeT?g?9V)O?wuHrf8E?@Liz&M!sn*iw|wmZAc-6cw_i zsE92^?b%Y)fh|QH*;3SrjiSy36m=n>s4D?Q-3Tb^PC(I-1Qhikpr|JSMZE|p>PV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*ZzbP&AByqTz%CKK+!A$ zie?i~bP@qYa|kG!OF+>)0*cBAD4I_Q6djcv{=xx?W!iJJQBu^w9$hcUj+!r1v?$w8 z|3r!wbABm0nJq<2*iy8VEk(=NQgjMiik7pb=v1~8oyL};)7dCGgMgwl2`D;?fT9%y z6s;tnXcYlPXA@9#4gp202`D<3fTA@76rD#v(OLqE&L^Pg0s@NG5m2}Rwm)jW6kWmjrD!u-imqf! z(N%0I+QOEitJzYtl`Tcru%+l)wiI2*M$t9`imoT1=mr9cZX}@SCIX6XCZOmR0*ba1 zP;@H+MYj=9bUOh>cMwo?Cjmuw5m0nD0Yy6qD7uG$qI(G_+DSmseFPNUPe9QFgh0{8 z>~Mtx5*umXb=)LHSKEEjgV|B@Wr`ln_BVVkMUQcQDSDhOMNhD$=t;H|J;j!yr`b~U z3|oqJv8Cu)wiG?bM$z*G6um$|(QX2YUL>ICB?5|GCZK2!0Y!TWD0+o}qE`thdX0dh z*9jsDD;RF z{gr&emK`-;rs&gb|D7+TXg}wdqR-e;^f_CKzFBML^L(0*d}7 zpy(e0iVhJ_s8WK=+7y(6%2qplApIMMDWF8b(0TZ~}@(5KuIdfTE)afugoK;k6D( z>?V7T)=rA{C7-b6M9r5e8kghW`hygW=loJMfh|Qxv!&=5wiHcdOVP1xDVoHVqT|?7 zG?^_$$Fos%0s%$E1QeY}Kv4++MNd?u*#s1w zL_pCT0*dAmP&AK#qA~)C<`Yn~fPkWf1QeAM0!3qT!ml_Wv8U{}_s2@nsdisfkrOpv zrf5ly|MO2$w3PEp(K5Caox+x)T1i0B zDguhmCZOmX0*Y1>P;@QYQOlnDJN>aOwpA&ez#wx=qk=H zMO)ZXbTwOwwz8$@8nzT&%a)?+*iy8OEk)O}rRWAWif$yJ=q3V+ZYH4U76OX46Hs(3 z0Y$eFP;@&1MRyQTbSD8tcM(u@HvvUE2q?OTfTDW|DB4Lt(R~CI-A_Q#0|XR3NI=m; z1Qb0?2oznB6F$KKiFLI5qRmn?$-bgJk`pywrs#WIC0Y$G8Q1luBMXwW3 z^acS%ZxT@S76CuEcRLIf105Kt5*peRB>kxxKTDgi}NLZE1WPWUSaB(}i5hBi!DX9*(j<*Kv7)+ zis}(iRG)yN1_Tr}B%tUp0*V?DP}G=!qC5hMnh;Rblz^gU1QazVpy+S{idqm*bOZrK zEeR-UMLd2O&PHZXa%$A}qY$@u>mZENKDeBIaq9fTT>OnwJPXda15m3~dfTBJG6!j&b zs2>4E{Rt=6qONBG@pQ?1q2i=B%r9AfT9WliWU)2w3rYm8XpfoZUCWlD>)2AXjV(pjv!&<;wiMmSmZF>3QgkyLMYj-8w4H#W zTL~z-jew%t2`IXQfTBAID7uS)qPqzw+Cf0kJp>fpOF+?10*dY^a)w@u>MSMNh~5Sy3r^hVx6& zF18ds%a)?&*i!U7TZ&#_OVMt&6uronqLp1QfkWK+$Ui6unMB z(HjI5y-7gPTLcunO+e8;0*c-tpy*u!iryoj=zRi;J|LjzLjsCEBB1DF0*XE%py*Qq ziuMx%MNh`V7dRlX47)FSN{SBIH;+DxN6nWh`YP_lweCyE?bIfu%)ObTZ(G2rKmPrit4bXs4iQI z>akH&pMatU1QazSpy)6HiW(76)R=&xJOYZE5Kz>VfTCsu6g4NH=x_pxS`bil1OY`Y z2`FksKv8P~irNrR)Rusvb_5jV6Hrt@2oz-{!u2zqqF?O0j@gOenf@x)R%yw zegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)I*NdzQ3Mo?CZK2x z0Yzg8C>lpV(Rf0jsC^=Qq5~4!XAgxsNYOBRbUh&vHD9La*o1#(T#6=feknSREk%>r zQgl39icVllQ88PJPGn0_30sP$u%&1!8%5IyC@LkOXgUE!GYBY}NkGvo0*Yo6P;?Rj zMRN!!noB^@JOYZ!2q>CQK+ysMiWU-3R8Bxq1p!5i2q;=iK+(wr6fGg3Xel93bW9?A zy#o^4XZJ-DrD(T(3vyW^YQ9X-X$gN75m2;|fTB$V6kSe0(G>&~Z6=`TN&{tEk!r6rRZk16y3s>qU~%cx|NNh+XyJS zoq(b{2q?OffTFtyD7u?~q8$Vj-9tdpy#y5PB%tU%0*dY@py&YtiXJ4O=ph1%9wwmZ z5dw-HC7|dr0*W3dpy&w#ik>6{inb=g?H!O<+TZ&#}OVLYgDSDYLMSIv%w3jVKudq?{Dgi~W5m59x0Yz^RQ1m7N zMQ;&M^fm!S`v@p{hk&AY2`GAxfTH&aDEfeaq7Mlu`iOv{j|nLHgn*(?2`Ji6K+$Ie z6n#!W(HDe3(KCtg5(gyK%Kqb_T~hR?dt2noMAUqlqHh!arg~EJ9p{&#@7YrH16zuI zWJ}RcY$^JgEk(burRZ0-6#d4QqTkslIzT|t9|RQrNkGwG1QZ=4py+P`ivA&>=nw%# zUap?DqbNi`Q3?S?VFHRG1QhuM6r~bS6eXZ2jew$b0*W#SD2fqKlu1BQ79mjdbt3$T z0}}hqegg816m_w$XxX_@^JR*1bNvq*NKp;WFGV%kQdEmAMYY*dREI4^b=gu>k1a*@ z*;3SiEkzC4C_0RQqDBN1H71}akAR{k1QazTpr{!EMa>B)I-G!_76cR>K|oPU0*YD@ zP}G`$qBaB+wI!ga9RWr81QZnzP*g}jQ4s+}?FoURcy2h-&?!32zD1PC4W8+Lc*C$?rbSKk}X9&*izJ!Ek(W9Qq-F*MSa*()R&E-egqWt zC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)I*NdzQ3Mo?CZK2x0Yzg8 zC>lpV(Rc!iCJ<0`Gyz4&5CTP=a>K(MkXRdo(^-nz+I`W)+^G37MU!*=lidH2IQet5 z<2k<+oxql&Vzv~W$d;lKwiHcaOVL!e6is7GQ7K!Brn6BrgMgx$1Qg98plCJ$MJEwZ zG>3qqxdar=BcP~^fTH;X6fGd2XdwYbUR75m2;|fTB$V6kSe0(G>&~Z6=`TN&=jFxc*7m&S@w@AKUd#9&^*yg`y!TfBa;CU0{ zeLH*J-VgC@Yd!Cm_}3SB-hp`0g`RgXaq`9P;~z>qyusZ7p+tD2y9Gjt zp_jXxAe30Q+1&=A#OqhN8zGcvu+`lPp+w2G?q&!jZrJ8-hfu=)Z}!bY3H#rXw+toh z|0mrxl(7FHaA7E6|3}x3p@jV}IlG1u_WxAu5lYzq6t7PxVgFaN0ilHbZ>ffa688TU z8WBo-|CqZ?LJ9jndyEey?0?NLF_f^sTYqvWVShRLiJ^r3?bg#m3H$4bXND5?_sh-+ zCG0N^~T| zBb2b;_}&pp*stu~7fRUgTs{;^*e}gJ7E0J}Jv|jl*srZT8%o&k9qbMz><7ntLJ9lH z-)o_S{pjYcP{O|V{%$B?-#q;=l(6r9eHu#Gw=cd3CG7dFI&AHPb?$X{>v~tXe`*b}({;+W<~|0=|C+S6!|R1QC!1IMYxmwl zT{O1YC3MYR;ZESy-se7rL*4Y2lk8;OH7>FXJyK(njUF0f?OONL$gxZ7rLi@`joup5 z?Hcq6Mjdxw;Mt$^823-z(CE~}3%C8cW=Y-97(X*@Ztm2&p|Ponw|C!kk4xkH%&9dR z_44Z3&px)e)7Q6$M%y{#{twnZc$zz7YT~*bd+&FrcjtWYvolt?=Fa)T$$p9FHMrm1 zSJ^*)N;tK_Vt3{3A3xQNy{_6nemI=!g%Y8|vunh{*$uKM)JcTmbv!SnxfhG|a>?_; zwY_k5_t=rKZn2>?+zqI=q`5P9@~ouhxYODz(HfyxEI4Jz&9p2poW>brv8-5TtgHJt zr`P${sWRNDs$G0c(+}QTrY_P=yT~kEWb&<57n!Y#)TwgZnf$8j5zlg0)82C;`HJs( zx%wmNoz%z=^{&U2IHF!6l$+Y8?q&Vz*?X+%SG#&Cb$0f1ADmhp|7WXRy)|_2tj@V- zh1>_WsD@oi-8E;0yp*~Z_N(i8_1qggdxPiI4^Fe8Up-q5^1a^mdeobjoxCdUx*5&? zc(G54kT=>6vy-omx5J#|tCQ_uNFv_Pq0w9HHTQ|}rLI zEtykLKC@(DX~DwMd8OqgO!BRl0ivAd2_`~e$Txi74Kl4iI= z$oFgfw--N@8lK@!5U!W+hr%=RlCR}ezM7YpTHxoVhWr}t(9ZW$o48e@ph%Je4=Nnu*|Df=;gI4f!K^rfz|54-H2bVp7vvjI_e_co&s@`w= z%Jfp;1Y`5JL3$4xU{~yw0>2W;64KGWYZSSox9Zg-~7tJ7nb1u#%`&O zdgty+aK-xSigl?>?#AMc?iSXo9l8Dksy@)}!>hNt4@Ynlxl0LNsrJX~!dcx7lYFDQ z(R98}l^5o&8Sk{cPT!&Gdi1Y6M^S&?mAm3PM^aa@-BFgs|38ls%zA(^1T;1)86ob#}@Y;FgAHU zcT?+%InsJWcJ}EC9L>eexY3&P?euB)GzXWV@jUCNE{S zeHJC(RH%z`sCA9{RbDsy^i7_qZ`G9?!0p&UZ>zjvxe`TPD=(_3$_}?RH+4}JCikb& zyXFS2yeZv1Meqlxl2PPn1g(%aR$(a`#7$IXgj>!1A%gSqirqZPdnw(-Nhs47&6`?O zSeSf+kXP$P!5NCGK19`S`7XLVZk+&?y@#$cUUec<)ct-535w(C@Ny#g1>4@VV+qG}eZ8R+b;NEKA>7TrfJ zxPJC#yC8SedoFTzlZo5Y-D&7e9V$PR?gPTft3+^Pb6Z#5zFpnNv8+u^T)2wJ7)!G_dmA?iSD` zR$T*bYxfb-+bVBMcM}Bfp~{H6Q*ozCUU>3N?zVM%)S`+3B^4#b<4czWUqmYZERLWz zwi0Q3;Vp7^jh=fq=HHS zm0zgcCsgv9+l`bYr?}(vIb|gk?cB4c zp6+IuX2G3u`uxS6+Lh05H?63%D?NwQ{5G4H+^ntd3ni<(spx7=gp{?*|X54;DJgzyVc#YyRwQ|W%JsVyJs@) zSnitps#j9EgAaxKg6s{Q_itN8Ri2BgK%3S7_O&T6TkY#-Ql+~WC~~lq@2Khlpvg2A zRgVL!9{m*s`jcwheYmb-)vXmgK&kxVm;_#2{O_;aJp8PB^a&w*OfzcGxXQ1{MLgK7 zdf-^~c(Ll?qI=*8rQkEdu3n{S9%@!S3as`ZkVl$TkNE79quMj`|E=ev14^eXnh|`s zcqq%~NANH*`60E(u6j6|{LlrT+La$pK9ws!VfcKp$FL_=-re$0wdx^X)g!*5s{3L- ziA-4Xz4IuusPaK$<>SL@pRHA&b5)P-KvebEt`bM^0MQ%Vzkm0uzGKnqzkdQJzxR8{y|{0hEzi!(@>*8=HjaH4r(bs6m8q-zvm@t( zSEpPMN;x~@rDu0N^Yl~M-k@0DZtlb-_6-s*RN!9qyS5vdKeF%8qrB8abYyxsBP};l zGgK>7CtNpFFH}F&Ak;9_D5YsA-@gCzA1~EY#QX73^*4trzg-p7u)hDqX~OnBf@&{e z_x%C;{#w;b#7nr*vhtl&edo$f6ZYKqp{u=wJ@+lwYA<2WeXqRQOW6DOHw@hm#j3s4 zE-&Xlw!QbNm$2u)2U+bU?AbT-s$RlgEzkW#EBU9k+aTBdc{*0T*^9f^`~Alr{U4j} zj|5M8npb$ur|HY)|I3qu$}g+Q$ApzD`9-#J6%`h__hr{O!~HSR-1Wm zMeTZu`*7L!O;g;BV1IHux;G_{_3Y^0*u;+R!)D&>?dHdh?&odEqx&ga@@Rif>-Oif z;{+Yuw~>ePWSyGJN=V7+IJ^y@7M7!_Xn^Yb>F|Y<6-X4 zV#iiG_I5YD?cq9>xIcsKxjJ6&ZhG5y>-dfP0NDOR$M)`HWxKbIOWY4CY_HPs5%+y- z+b`%CX%Os$j>FuKH0|xj=(xUdu&>nd4flbyw|}Bz!{)(mrQ?(q!7kJBMt1|)>F?3; zyVk+}OUI7wg56igW$uQu)1RZ`V@1J!QO8sV)!tr1#}V!ZwSBCP7j+Hx79HQ}9_;-( zHgY$-oxY8Z(|QMcfsQx#4fakQf9N0Vzjf?9DA@gVTs|b&=j!;xuwcKeW7^1I*V6H* zQNcb=$4kZpd#jH7#s&Lx9rKP3b~_!XPYiasj@u^%`+gmNaz9kFKi?r8yA}s~ppK`N z1p7Q4pK{Rc^m}#8m>%ppI*y(h?BjL3bat?>)$v{TU41+MmpV2r3wD8yGZzGVk&d^O z2m3)Ce_0gl(Bk0OeMxW}tm7HWf_=V@&nyr2t2$<$9_)HLjy*Hj#X4?W5$tU`zP~Ei zU+dU>b+C(coV_O4C+m2}+F(Dd<8K!PJG?G9_P8)O4%P9ji-WyR$7eSL`*j_&HwL?b zj^i&6c8QLcZw~eiI)3PW4sIXcZ*^?3HP{_=oO5lkm+E+z`yr~G{!twd+z@R4#^BiN z=HNJ7$CcZIeW8xe-xlmQb&TH`?89_C`tD#))p7GZ!M;hyk9P+9dmURo5bRDm&U+}> zr|7ujkzhZr{1=CdMVhq z==kZLVE?FN>sN!_MaTKC2m4eV?|n1aPwIHk{lwos-s$^-W50KU<0u_hzaQ)kI==K_ zu;06 zKL^JFzXr!KI2J#V1)Xgg-O-!;+kSoLYzGj*J+zC?Suj%TW`)n2dT2K8%nyj{nK zbbL<7H+1|&#~*b3TgMFdYYBG!>*(0rj_&$T)Uiazi}m))bi7)}>vX(T$2)b*w8uy8 za^gDH(a}BZNcN^Ww$RZ%97y&e9gozpw~p@1Z}RQKbeyK6`!bd6?#oZ|SgzwT9Z%EI z-Q6eOzE;O=I^Lw?9XjsN@j)FQ)$utUU)1q69pBQ?eVQdN|2G}or$=(TPlMz!Lr2Fr zxgF2s(SG;ZK2E82`n0N#mz&A%9!4gQ^X>7aJ6%oNIqvbXx|d(RbZ$k-6nCsx7#wHv zn)@C~g_m#NwD9t$l$U$??%OQ+7W0E|c>VWB?#WY5v**O_Coj{>+=V1xFPSoBVd>)F za)RQ1FkXF@EG(Hfqg3xHIK}@gbL_|3x-2>sbKQyhjvbj_ zQc&1OIlP^u&zwLD4VE*fQktKVZy&U2GaW~KZ z^>l^qH2?X2?Ku}Oc6-`OTlY`8`=^il$6nI42Z*t29V z?{fD#=W(xkP2J_$>3HF7m%32>^6FN*ye#)NE^oVgo%7gbw0D>Hp1n~oyzNG}t6yGA zcX@U@+4XaumX()xpL^ZTV;<}!rzqr|Y^_bcPPfMed!3g( z?sPpE?#NZ$?Ov~b{R*r7d28r&c75M-|2XsW-68ps*(>CAXSgHp%Z_}m*qevA)1By| z-JjcYc6+~Z_m90#K8M_^-i^IO-U;@KUbwu3+tp9k$6dc~IgvYZI)104V@ZBlL0(>7 zQJ2EbT?^ZHZQsScURYRE?cbd{cg)M{+ObQA&hB)1c_(I^K5)dK;Fp4e3l6#O3UIkr z>JCmWKe$h5>D6x_Tf#TksYca1F`1$@Y^C|N+^2p@TC}D6h({v6eSb0~ z65Z=g5-xNn2)C`#*IwV|-gUUJ=6LtI@1Ew^yM8h1?lvMeqLD}o-+qBQ&Hk3gBlKV1 zHFmSei?q~i(n|9%H#@lhGl*tGH#>TfHku9G?Bqq-YSwqNv-`_MHS4+A#f#)? z)^)S17b(!J<7PMa_mgPWcC*M`ts?DOw%zq=uU*r&yJ8)*YuI+ztfO|WZFki=X(w#E z>(*I2ZrfeCF4{S^-L>ngoo(A)y>8lBw%zsXuAS+2dw2bg)Q;J9*RO|mhHZEKdTOWJ zcGs_$cA9N>{d#LhZM*B&M?2NFyMBGOecSH(_0x{ncGs`Jw);+GzxM9>4bV<;yMw!a z1GU|KS-%eM`VG={w|{yh(medKyZtjZn4-gz|Ls`DEaxLKIC`r)fe9J@e~7yaH!17? z@82`b4g)*vGDBl`Q-X?$f-NSPs3;gV}b-slHTuia~RXQr6GxxPur4skSu>=-kI>=ZME>>M+M42T&*2F45_ zyTlA3yT%M5yTuG4yT>GCkJyCl8Jmznu?g8LHX(b*CS;%3gba>N$iA@&*)KLBLt+!M ze{4dA#wO%|*n|v=O~~-rgp7zy$bqp5IVd(EBV!XXDmEdbV-s?4?3$4Ng&(uu|N7^% z%T3*OH6f$3>r~yCQj(K|Oei)z@FHD94vC{7WMa$^GAU*VnH)2OOo+*n}Jvn~JZGACvTxgcf;xiDr3xhQ4`nHw{NTpTlm zToN;c%!^6LrLhT_ADfWNViR(CY(lPxO~{q83ArjZAy>yHtYjfeQZK* zh)u|iu?e{;HX%31CghgbgxngNklSJta(iq-?ubpuov~{|&MvH%{r=Zqo~|M1)P!WO zES9UgtCZv#21Gbuk+#g3n$OAD$$b&IM$U`wh$ip#1$RjaB$fGes$YU`>$m20X z$by)JJQ16aCu0-xRBS??j!noju?cxLHX+Z&Cgl0pguD=&kQZYU@=|O+Y=y>6<<# zd9Re@Bq1La(}Ve%ge;7sA>`wjA>@;oA>`ATA>^}|A>{LzA>@mgA>_-LA>^x=A>`|r zgnSd5kZ)rXvM4qo-^C{6``Cp15Sx(2u?hJxHX%!56Y^7RLVk`-$S<)8`875nzr`lx z_t=E|5u1=dV-xaMY(oByO~^m73HdiRA^*j$3HhKfE&Khi|0I3v@nMsYaxq;)a`{rC zlO9=ImoKJ=dNw^iy_k>F@yO!lc097UWXB_mTiEf);+A$ivbf%kM;4ducw})aJ04lw zV8uXytLqv#mfjDS-h;^k;Tgi9$CD+;E}~E2p(CyqTrFmD+wN1yt3et#j6Mz zkjA>~!2yLwG9cxf(uXI7d`(eZ618f+lz1gYYvzmTp~6jy)^a`+t!;;*b?i{o#STSX z?NHRs4n^JVP}IW?MeEw3sHaU)FM*=<1d7%dDB3`vsJB4Th5|(!2^4KCP}E1DXcK{= zO$Cbj3KaDdDB4V*Xmf$0Ed+|T6e!wCplEA>qHP3@4UrEtU`C@vgd6S}@oexC=>`*k&4n@1zp=eh-6zyh*qTTIKw1*vv_OwIM zAe*AS1d8?+DB4G$Xs|%hz5+%22^0+xDB543XsAHZ0RlzC1d4_W6paulI#8hKAc3Nh z0!5<)ibe|*9V}2ZMxbb{K+!m%rf7$JVTTMz`HpPX?HG!-NuTsst9 zY=@#t>`*k%4n>#Rp=iDxiY~J$x?G^>3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pH zq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pLb_=)8R4?F>kHX!?Nq z{7`gaQgm;=lzb&c59W*MsZyF0J>+~Sde{y{kJzE;Q9BepW{0B3?NGG94n zEfy&HQJ`pvK+#VEML!D^{UT8Gt3c6j0!6vq7DK@9R-Ry z2^4h}C|XLOXla3>Wdw?r6)0LxplEr4qU^!$7iGUmb$N%U8pI_o?Pd;3`qIB^a;i0&1!f0i_^7ejb^3fD=Av1Sus7;SCgVH&WEC|b|~s* zhobIwDC%K{qIK<1)YA?{z3fo5o*jzTw<+2{ps2S%(S`y=8wnI`EKt-(plB0;qD=*g z`U({F6DZnDplEY}qAdi9wiGDZN}yMu~Voj}p{0!2FrHAQPRD=f}{ zl>27i-BY)AC@Q2o{T-W?lCPv_V6$R+s<2*r8}oI}{DF zL(yJ#DB9Z&Mf=zk4HhWcSDkeFG+v-+f9b;2;tU%Fm z0!1?fijEg3Izgc5M1i7{1d2`;C^|);=v0BC(*%lU3KX3#P;`bs(JX#Qq3Ciu6kTD5qAP8Rt`aD^TA=6}fud^#imnqVx?Z5@ z27#g*1&VGGD7smo=oW#ZTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCAx?iX% zx}aI%u?$Fgc0Pl1VJMoIu0;8Vbe6g}#ED0<8eMUUH|Xn`Gyp0GpF zlXfV2$__^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+!^>rs$z&g%)dPioQvA`VWVq z5$U7rkDHZ}ucYYnX2tYWxlM|`a6S}$X@{b(>`?Tz9g4oOL(#W(C|YEPqVMcb^t~O5 zey}N8EKu~LK+zI`qMrnceikVDMWE8ZM#6m@q#6!ow}(Ykgh z>S>3fUUn#2&kjZF+o5O!I~4V{L(zsdMH>keZ7fjKN1$jEfuc>7&ROrOY}QYa-~Nzvhj z;%4iIqG`^Dq9g23G~EtGN7|w2C_5A#ZHJ;`>`-*99g2>#L(vSIqT>aMP7o+MQK0A~ zfufTIicS$II#r`-*29g429L($cCD7wa`=vslI>ja9f7bv`?Ti9g3c^L($WAD0;>YMbFxy=s7zS zJ#UAi7i@}N6exO0py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz z=zW2r4+M%n6e#*gplG2$(Z>Qsp9mCvD%2D`S|}{ZfRyK^&pJL9iu$K((PxEH@|6^Q zRVb#Hx@l7Mwez9q8#@$zYlosmb}0JJ4n^PFq38!Y6fL$x(T{d0T4Gc5lR(kW0!6GKvAwPZrdr!3ludIC@KgP)d>_8 z1&W#r6qN*uS_m~oUlaHj)He5o(Icb%moc zAmsznwWw8H?M{C|`sliAT`BoWiq@?wrkC1kQqnP zO37DJv}av0y;NJ1qCw7wqP^@;w6`6K_OV0JU^^7;Ylou!>`*ks4n_Ohp=hX0(E$QQ z!vu zplGr{(G-EALj{Ts6KaZfuPfAVnJM}web#Z0P;_6q7EP@yC0|L=^txhtslO&gM>-#h zj`?Tq9g3c_L(%hgD0;yTMK9W+=p{Q8 zy=+tTia^n;0!6P06umA`^oBsun*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ+i zEfgsFSfJ<=fuc_Ziarx4`dpys3!$cHL0#ef3`qI>^iJ%FP;`H~)Bm!rlzb&c-_{k= zOVu_hTI75v`pynT-`k<+2RjrkwnNd6b|_k6hoYbCQ1r7Mihi*v`cN=r4hyzXgi^5h(gspy)q=qFga<+bPNm6g3klDhL$S2^19tikb@)l>~}f2o$vx zD5@7IDhoA5U)L2@+A&jfdwP%dO(<%Y-lMfDmXfces8TGZmpX1zRCPWSwXs7{TRRlB zvqMpPI}~-WLs3UN6m_ygQD-|8EoD=*v_R1^0!7OT6fGxEw7fvk3Iatd3KXp*P_(i@ z(JBH(s|pmYCQ!7xK+zfkMQaKattC*jwm{K30!3W}intCTYj^rvrwdb$Vk!Abiq#|}lC z*r8}sI~4V`De5Osw3$HB<^n}q2o!B8P_&gm(bfV*+XxhGD^S#5plCaRqU{BWb`U7q zQJ`oifufxSiUtT24HPKaMWAR`fuh|6igp)jih33cH)TM|+qTHy^a@2!q_Ib_lzb&c zdl!r8rPiAi?c;nX8f=H6eeF=RpB;*Z*r8~DI}{DIL(u_tC>mymqTx10BLs>L6ev1K zplGB((I|nU(E>#W3lxnJC>kqJG)|ysyg<py*J6qQeA= zrV11tE>JX0s3{s$Ec~1SDL;`u6xu5k-IA_FM-)rRS5kCzvDki(P;`v*q3BpU6dh-W zq8WB5I^GUNC)lCrL^~9nWQU@Y?ND@zP0^_WMW+cA%@im)U7+X;fudOgMY9Ep&J-v* zOQ7g%fueH+ip~`%I!~bJe1W1l0!0@H6kRA#bdf;OT!EsC1&S^aD4HkK6dhSCY?J{h z4@$RXM}?x_(zWQ)Vk!AbimoUY_Zbw5u5>;WU1f)&tL;#9jU9@vwL{T$b||{u4n;TE zq3A|C6y0P~bhALwEdoWi3KZQYP;|RM(H#OscM25UB~Wy?K+!z{MfVC6-6v3Vzd+Fg z0!0rB6g?zR^sqqDBLYQ_3KTsiQ1rM!(E_2S=(1wrm<&kymGphrmxrRKvbWVeQ7k22 zNzpUK;{3fs(X-BnqUY>T^t>I4Ua&*ai*_h_$qq#?+o9+cI~2WYhoaYPie48edPAV- zO@X4f1d84kD0)Yr=v{%L_XLXG7byBbpy)$^qK^cM777%7EKu}`K+&fHMV|>2eJ)V+ zg+S4l0!3d56n!n!6g^ceJedJ0r`Ic}dpZ>LN$=6VDVCD2r0Dx%@yo%X=m+OR(PBFk z{b+}xC3YzK$qq$7+o9+eI~4tDhoax?Q1rV^(H{aue+m@+B~bLYK+!(}MgIyE{U=bA zYaX}l6y*hqnh6vY1d8eeii!e7%>{}|0!1wZidqU3)e97r1&Ue;6g3DGH3~IFi;9I- z`(}#L*Inzr3q>u{d$iWgOUYMK)V6uC%aBmi&iPQ(-VQ|_>`>Iv4n>{pP}JEDMN8SC zXlXkXEn|nGWo?R<6DV3LF0Hu0T;wp{A(Xys%3Kr2Inq=(9)UD z^HTDa6!mUioHR5PZRmU`+Q<$?8{46%j~$9Ou|v_Ob|~s=hoXLVDB8>pMVs3cZ6Q#! zr9jbE0!3R36m26=w5>oo+gV$$*s8D>T+^5Q^?gUk=%;c`5lyiuP?@ymweA+Ryn= zG{g=?``e*ts2z$9utU)>I}{DKL(vF36dh=XqJwOTMhX;-5-1uiP;{_B(HMcEu>wWo z1d7HB6ipB)Iz*soqCn9kfuhL*MNMbiX|ju0rCE>Lu&P*b!| z^TLN2kn;WM`-=vLqHEJ9vX5$BO1_e!LuaK+!CLqS*pPX9^UZB~Wy>K+!n@Mdu0>ohMLqzCh6& zfuaipiY^o=x=5gCu0YYn0!5by6wMPTx>TTOzCh7sLQT;z%?qm>m?`R&KA=7}6m@F4 zVQXGWzLKJ=n-{kl8H%oPJ``PRhobB3P;|W=if*t&(T#Q}y2%bjH`}4;7CRK(YEyKZ zK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2oj|db!Dp2&8 zK+)p@MGFLqo)9Q{QlRK5p{D4{=7rH2kn*bO1L~_n(Y$mmdb)Wj`AUkOZ(clYbSQek z`B3zt9g1GEL($82D0;;XMX%bS=rubOy>5r1H|$XKrcKdX0!42N6ul!*^sYeBdjdu8 z3lx1IQ1qcd(MJMB3k8Zk7AX2epy*S9qR#}1J{KtZLZIkNfugSjioO;o`bMDWTY;iQ zLQT=L%?r0=K+4~w_h`?BqU_bhvKzMMrQ|Cq`muTOl`)}ciSwc8Cp#4VY=@#>>`?Tp z9g2RlL(%VcDEh+=MSt3%=r5b1zXgi^5h(gspy)q=qFgC%+bPNm6g3klDhL$S2^19t zikb@)l>~}f2o$vxD5@7IDhm{~5-4gAC~6caYAsMy5h$t(HAO!(FZ`MTDgT--KZ`@r z)#;<_HlL(vL0 zMJoyvtt3#ivOv))0!6C|6s;yuw7Nji8UjUY3KXp+P_(u{(K-S}T?C4{3KVq{DC#ay z)I*?XU4f#W0!6(9iq;b-T3@IsYF8@s$$*r1O?Ue3OSL=wmD8R62BlK+l@x7UD(-to zDC*;UDB8phMVs28sIMK0`q`mqGdmP*Zik{R>`=6&9g4QHDcV|~Xd8i|Z3T+@3lwc9 zP_(^3(GCJdI|>x-Bv7=oK+yn!qJaWMy9gBRDp0hWK+*03MSBPo?I}<+NT6shfug+y ziuMs|iZ(12j>~|QKg?#`Mxp59bS)ZODkWb@(f+04<uQ0GI@0d^=FW{0BTb|@NQ zhoS@RP;`(TibmR@Xp|j_M%xq}EKoE?plGZ>(Kvyk@d8B?1d0w3D4HlxG)bUnvOv)k zfuchNiVhPfnkrCqxIob~fubV>ilz$`9Vt+Blt9tZ0!7CNHAVZC3QuQ1%EzbMvLT^p z&-Cu?*itF^N{UV>6~CSmicWMs6rE&;qLb}Vbc!8{PPIePX?7@@X@{cI?ND@v9g1ez z6wMYWI#ZzNEPKGeRdR7$>*qU%bZ779|;sK6e#*wpy(5UqE7{i zJ`*VVT%hO+fub)3ioOyk`dXmq8-b#41&S646n!U9^u0jQ4?<1R3#Gz^8Ibbc=|iCx zL(${uTC})SO1_e!pG(F2r-!0noDW66+M(z-I~4tHhoV31Q1quAivF@g(cg9``o|7M z|JoG&Cs34Y5x4CW#D5?k)RRxOL2o$vyC~7Cv6fG$g7G^-om!!`+{uGMZCsOTOl#;KcsB?>A{^(G& zl=GozX*(1xV~3(;?NGFw9g3E>L(vL$C|c1DMJw5%Xl0wCRRoGw6)0LwplEf0qBR7H z))XjOOQ2|NfueN;in<6CbrmS;CQ#H}ps0sH(YgXfJq3z-2^6g-P_({4(FOuVy##zMeR<1$Mha;qZXy)D=FHvMRA*BLs4JnLs36F6m4dQqRs74 zw1pjtwzNahR(2@b+73nA*r8}!o1*>#McWA!Z7)!?gFw-a0!2Fs6zwcfG(ezepg_?s z0!6zD6zwKZw7Wpj9s)&s3KR_zDB4S)Xm5d{eFTaI3l!}uP_&;=Q`DzLVN3?3JSoB1 zBov*Hu0=yyl#;KcXjqHl=`%vnaOXqO2s;!VXosSM>`*k)4n?EvP&C>OMF-oVXp9|- z#@ZB(6DS%lP&7fH=n#RTi2_BF1d1jL6ipE*I#i(OFoB|}0!4=l6ipK-IzpgmxwWM2^7r`YKn%oDBP9-DR)jE3LOxNwn(IoZ&6CVlA@Da6kj_b z6rJLHC_2>+MW@-JXr>*CPPaqR8Fna|Wrw2Kb|^a24n=3#6rC+lbdEsLxdKJ!2^5_# zP&7xN=mLSF3k8ZU5-6H0P;{|C(Io;!^8|`66)2i7P;{9<(d7a~R|phcDNuBkK+)9# zMb`*5MJKi>{GI_R-;~eboD_(Ty#Nolg!$H#r}QZni_wEp{ln)ec3s z*`ermI~3hvhoU>}P;{3aite^4x<{bsUV)>`?T!9g5zuL(#i-D0q8|l{mIyUPFSjThp8?4(J{g=>LeW3z6WKqtC?#J>(Qhq^ zSI!JYzdIj_{;)&QpLQtv%ML|<+o9+mI~4tEhob-NP?T#K_wAu5Z&TDvpr{~FR3}hW z6ewygP*f5qY9Ub6QlO|_pr|ZR)JmYJL7=Enps2M#QAMDrDp1r$ps1}tQ9FU6_5wv6 z1d2KeHATO)C_I}1DUVK!XV27d= z?NGFm9g0@AL(wXBC|cDHMXT8qtu9cshCtDp0!3>H6s;{#w2nYg7lER#0!7^finh;Kv6G&qV)ud))y$+K%l6%K+%Q*MH>keZ7fjKN2n=Us%4=vD^qlR^9;_? zEo*oBAEmKL%Tn@{6m8bB*yGGlw7K)4XbU?OZE1(1t?W>=wH=DKu|v_eb|~s^hobH5 zP_(^G(GCJdI|>x-Bv7=oK+yn!qJaWMy9gBRDp0hWK+*03MSBPo?I}<+NT6shfug+y ziuMsG8Z1z>uRzg$0!2dviuM;M8Yc6pgV%(O5eajk811csmqLuqir3plG5%(IkPQ$pS@F z1d0w7C^}4_XsSTb;Q~d|1d5IjD4H%%bfiGhQ36Fr3ltqAP;{(7(QyJrGX#o`7brSG zpy))Qrf7J}!rTl}&<8iAr~1&Xc{D7s##DLSQP;gbwVd8=&J zof?X^Nw@tsv@9iGNzpAWi-kF%=vL=L(QS4py4?;%ci5rmPCFFcWrw1>?ND@&9g6O? zL(zRUMfVF7Js?o@pg_?>0!0rC6g?tP^r%45V**8w3luF7D0)Jm=t+U1rv!?g7ASf~ zpy*kFqUQvPo);*3L7?bGfuffLie46Kif(FISR(^czCV4U@#avpLNOb!v@9iGNzofE zi~TPQMQ=JEir%tA(c5+?ddCh$@7kg0Jv$V=Z-=4}>`?Tf9g04(DOxB{^szwECjv#E z3KV@NQ1rP#(H8Mc)b(EfOgDPN3*}fubJ-iWUnL{U}hhM4;#= zfuf%UihdDlie7737?%MlUz=|3Uk^o#T4dwbmZjt?Df+Wzan{^W^q2FY=x;j|{bPrs zf9+88pB;*F^>ODOit=_SYG#L`f*p$LY>J8kMa>0@N&-bK1d3V;6x9n9l?94g2^2L5 z6g3JIwH7F<2ozNXirNSiwG}98Cs5R0ps0gDQAdHIP69=p1&WpuYKneuS-2wuQXZN< zF8U)B%}m##rRz({S5mZmeesP;LeUD&hoTkjP_&XAidMEm(JFQ*TGb9ktJ$GwbvqQT zVTYnMZHm?sC|X;fXdQu~E&@ee1&X=}6m=IU>LF0Hu0T;wfuddlMe7L^tuIitfk07j zfuaosiZ&7`+E}2dk3i8T0!5n&6!jHqik7V}{FwnM=hIU;E>~Z>)BiYKi~7}khG zw2MH|t^!572^8%vP_&0Y(VhZDg9M895-8eRplBa~qQL@1`wA58Cr~s*plE-AqM-ss z2M81m6DS%k)D&%AU+9+sDW_*Ds@ozIU7N;;`cm?h6pgAc4!t}Sjdng19c+i9F?J{# zYlot7b|@NehoT8~C_2OrMHB5%G|8rDvOv)kfuchNiVhPfnkrCqxIob~fubV>ilz$` z9Vt+Blt9tZ0!7CN6dfy2beurZ41uEK1&U4(C^}J~=p=!nlLd-S5o(GKsxO?F0V%(o zEop4n=p_q3CWq6y0NoqI>O7be|oH?zcnH19m8S(5C1ifue^6iXIUt zdQ_n3F@d7T1&S636g?qO^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22! zy&_QbszA|eLQT=F^@TRqWQzVwaBd4lZzWQ%*O!v7r0DJXV$bVB(L2tEqId03^qw7x z-nT>12X-j>&<;f(*`a8m9g04-L(wNTMV|^3eI`)!xj@ku0!3d66n!O7^tC|IHv&c9 z3KT68DEdyI=zD>p9|VdP3l#k*P_#s#=qG`qp9PA35h(gqpy)S&qThv@qBrXcgEAoH zz0y0ew?fgh^zQAC`cm?h6#Y|QJp6`G^sn=w=s!CY<;rpA9*XjIC~9VhqJkZY>g-Td zv_nyII~0{{idqO1wG=3-7bq$V6txm4Y7i)D6ewyfP*f2pstOdf5h!XaP}EMKsJ%c@ z2Z5rF0!5t!iaHAvEhSL2v_R1^0!7OTHAR2b7cR+wlwV8NqQ67YdD+|QmMfQ%ucTK)F6m=CS>LyUs zU7)CkK+(DaMLh+IdI=P*Cs4G$K+y&QMZE=zHWVn@NT6tAfucSFMVkl|Z7NXISD>h$ zK+$FbMVkvXMJtpGpJhPGFQl)=u2`ED;GMO&0h$yZXeO}SXSH56^@d?@N~hobH5 zP_(@rigvI=(T;W~+Q|+@JKLdXfE|hk+7#^~P_(N+(QX1oy9*TUAyBlZK+zz9qP+x) z_7*7GN1$l1K+(PeMf(X94G}2XU!Z8HK+ypLMZ*M&h6@yp5GXoOpy(i>rf92jVXX{E zd8PCfkgY?}Y1!NAMwUy-S5h>lT-^TlP&C&0P&CdCMdR&IG{FuJX0py&vJqUi!fM+y`jB~Wy8!oo$DrbL>!bt{sZbvqRDOb|{)-hoTGYP;{XkiY~G#nk!Iru|Ux! z0!8x#iY^r>nlDgvnLyFy0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mFHwYBnC{T2h zK+(+tMYjkP-73@+%_+Vo=xAURs9y=7> zYlouy>`-*S9f}^XL(zkFD0;{aMGxDd=nYKq<|7dFp;l>bVfB6>Fz4Ns*0E|-$8 zq$t;_IP8H?ly4Px@}a1i9f}HeD5|qVQPB=X&FxTBvO`e|I~29FLs7j=QCXmLgIqS)gbsfuf}aik1;5T2`QF zIf0_(1&US>YKs0X7f#NAlozMx4EZk%jheFY6&WEDa?NGFa z9g5bpL(y7xC|cVNMeEq1sEZwny4shd z^%f}FP@rfdfufBCiuwo?Z6Z*#sX$R*fueo_MVko}Z7xu>g+S4k0!3R1HAO48D!iBh zDKAOaqE%Ye?)0~5m5r@im6ETdXuDR$A07!s+dChMcCbUyj&>;8$qq$3+o5QH9f}6p zp=cL76zytpgP&CC3MTgp<=rB7JO|?VO;WkCn1d5Ij zD4H%%bfiGhQ36Fr3ltqAP;{(7(QyJrGX#o`7brSGpy)(_qLT!QP8KLSMWE> zqVw%gG{+7_7uccbLOT>)WQU@;b||{o4n>#P6wMPTx>TTOzCh7s0!5b#6kQ=ubfrMi zRRTp<3lv==P;{+8(RBhv*9#QgAW(FpK+#PCMK=o+-6BwQt3c6h0!6nA6x|`z6rI(o zaA^jld_?-JB#w*p0r1d6^BDEeNY=m&wK#R5e?3KT67DEdjD=x2eVUj&MN6)5^mpy+pjqCW(R z{uC(sOQ7g)fuer|ivAU9ir#NkSSJHgZk0ak_(3SzE8Xe;*Q%6!B}IjX;*QUUqPm9v z_fEfPhoa_oC@R^ZsD&MhTH2wg-VQ}&I~29DLs5fGQKLXnYk{JQKv7kosEt5TTY;i> z0!8fwiaH1sbrdM-Bv8~@plB(9qNN3jmJujgR-kA(fuiLFidGOPT2Y{AC4r)qg_@## zLt$bDr2JBX)2yL(kJdJOTiq%RrQ|CqTBD(O_KTrtP3PlUw3Z!;*0w{@I(8`PVuzxx zb|~s*hobIwDC%K{qIGSGdI}Wv5-3_vplE%8q74L!dJ7b7C{VPKK+(nmMSTQ{HW4V= zRG_G@Kv6$|qRj+~HWw(`LZE0%fugMhinbOg+D4#gTcM_CwT8ky8Ibat3C`-Fs3E<3 z>)%jHzLKIH8;b9|9Ex^wJ{0Y2hoS*?C>m&oqFwAzw5uJ8cC$m#?sh2J!wyAz+7t~E zDB4S)Xm5d{eFTaI3l!}uP_&;w(GY>6{RN7K3KSh6P&7=SXt+Sp2!Wyl1&R(5C>kkH zG)kaov_R3p0!3p4ipB~xMcX$N{>^}tuS(aV9YRt1G*R8ShEnpC6isX>F8^96n&f;a znrw%nDRwA2)DA_5*`a8v9f}UOL(w!l6dhrQqUkn8M+y`jB~WykP(2o%i{D4H!$bf!SjSwc9dZ9gralPwdm}IQu37)o!?L#@kS_`<9sN(zz#(h+M(zoI~2{eL(#={ zD7wTBMf2=Xbg3PR=GzoqCQx*_K+zQfMOO+GT_sR-wLsA|0!7yf6kR7!biF{)4FW|s z3KZQWP;|3E(JcZ+w+a;9CQx*{K+zonMRy7m-6c?Tw@_1bZbRYJ3`qIe^jXLALeaPB zPXC^UQu37)JVAv+X3Y=@#p>`?Tm9f}^aL($`QC|Y2Lq9^Q7^rTJE zQvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3 zTLMLI3lzO0Q1q@q(R%_#?+Z0W_cat=&VZEHPTzNZe<fucVJivAKP`dgsrAAzEO1&aO?D9Sa) zjX6bmp{D4ghC+vTGevi$Yth0`v?P7|Y_rBv@|6@dZ!B)`ekdwAABtMop{S)Dit6o9 zRJKD=D?1c5*rBM=4n?i)P*kxgstOdf5h!XaP}EMKsJ%c@2Z5rF0!5t!iaHAvEhSL2 zv_R1^0!7OT6fGxEw7fvk3Iatd3KXp*P_(i@(JBH(s|pmYCe#$wH5LYEK+3l!IK{@= zoqqO_c6P(oSW3QL(#f+DC%j4qF#0= zTF<6veSxA41d4hK6m2L_w2?s3#sWos1d28hDB4t@sINd#KY^mn1d28nDB41xXiI^j ztptj;7AV?AplDlxqW%I!+X)nHFVqyR*;u$N15*Aveb#ZUQ1oRYwL@bm`AUigG!`FU z7>WiuABuLdL(#5wDB8^qMZ4RfXb(FS?P-UiL3SwG%ML|*+Z631P&8PeXkUS%{RE1J z2o&uvP&8Da=m3GDVFE?N1&T%p6dfo~bdW&NNP(hJ0!5<*iVhYi8Y56NR-kB{K+$-C zq6tDx(N2wpuQDLze(C$JcMe6zr;n}=X)GmQNzs(XV#`lM(V@`*k%4n>#Rp=iDxiY~K5(dBk1 zy27UDN`a!Q1d6T}D7r?V=vslI>ja9f7bv9dX(grbG%T6BM7Dfvo@9&Rk2 z`(-G4#Q9M4s2z$PvqRD2b|_k4hoUF!Q1ql7ik`AV(bIM)dd8;cS%ISG1d5&)D0)Gl z=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84lDEdI4 z=tF^`kA#|{2OA6bWkAZyrw@f53Pqo%Z=YS*SW3QRXQ1qQ0ioUlg`az&*u|Uy}0!2#%ihdF(`dOgp7lEQ*1&V$X zDEeKX=nsLSKLv{Z5-9pxpy(fgqJIU7{u3z5wT|0%it++Q%>;@H0!4K~P0=Tfh1@rp zqDK;(PeakPM5@@jlzb&cEn62?Toj7xoexE2I~29DLs5eriW==u)Y=Y36+0AF?NHRl z4n=KkirNVjwHGMrAW+m%ps15TQD=dor38wW7ARUqplDfvqU8jNmKP{mL7-?wfufZJ zidGgVT1B8}Re_?_1d3J{C|X0HXicG}sMNZ!bq1t-L;4Cxi`KO}{R*7J*hoWxIhobIwDC%K{qIK<1)YA?{z3fo5o*jzTw?okeb|~s?Q?#K#(MAGA8w(Wm z5h&V3plDNpqP_w}{RE0O6DZnTplAz$qAdlAwh}1XTA*kffud~%iuwx_Z6{E)y+F|p z0!2Ft6zwF`6s^;`Ff#*E{vh3>bqPg{iPX-mOUYMKv}^0)jf+FkZqA3I-R)4chaHOc zv_sJ#I~46@hoZghP_&O7iU!-EXkVM6{RE1J2o&uvP&8Da=m3GDVFE?N1&T%p6dfo~ zbdW&NNP(hJ0!5<*iVhYi8Y56NR-kB{K+$-Cq6q>;hX@o+6eyY`)D#VDU3fJEQXZK; zcfCs}S}|RVCbupnUrEu_*2SNegrdWp4@J}LP;`VHil*D4=tw&h9c722qwP?1j2()O zwL{TyHbpZ8ijEg3Izgc5M1i7{1d2`;C^|);=v0BC(*%lU3KX3#P;`bs(JX0+<*9vLgrZBF4@L9rP;{vsissv)=rTJLU2cb>E9_8or5%c{vP03;HbvJ66kRJ&be%xa z^#VmV2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c z{Q^Y~2oyai)D&IRy0Bjcq}(fAi{^%+Gt#@ahgz4CucYX)*2SZL3q_ARABq;(q38)a z6g_E&qNnUo^t2s{p0PvGvvw$Y&JIP-+Z4SZQ1qfe(MtkFFAEgCB2e_IK+$UgMXw7K zy&+Kara;kK0!42N6ul!*^sYeBdjdu83lx1IQ1qcd(MJMB3k8Zk7AX2es404+b>WH( zNV$KyEqgQ+%}&>%Pg|FgucYY9*2O3O2t{8xABw)VL(w;ODEih8MT_iE^qn1wzPCfs z4|XV8Y=@#BZHkr%6#XPn^s_+GF9Jos3Kab&Q1rV%(H{aue+m@+B~bLYK+!(}MgIyE z{U=bAtHf%un~kn+6rogrU@q8aI0)S^;K zzLKI=m16ntP}JajC~CArQENLCRqRkywL?)GI~29GLs2_B6t%ZQQ3so%jsiuU1d2Kf z6fGrCw6s9cG6F@*3KT6TP_(>2(Fy`ZD+&~?Bv7=nK+!4!MXL%FttL>kxI z6s;vtw6;LeIzmlReWlPn15#epGJ{jD)b8{jPVe5jR7%NLQq-eT9Qbc2TG#nd)YA?{ zz3fo5o*jzTw?okeb|~s?hoTMbP_&U9iZ-?>>LXCJi9pe&0!4iViuwr@Z6;8(xj@kt z0!3R26m2C?w6#FdHUdT43KaDhDB4b-XnTR89R!MY6e!wBplD}-q5%R$1BIHRZk58J z8IbaTbS>&0ihfOFmr5!5N{aTV6wlA4pP+lLZcpb!(I7h%?PZ6ez3ou6j~$8z+o5P* zI~46_hoT{NDB9nqXsAHZ0RlzC1d4_W6paulI#8hKAc3Nh0!5<)ibe|*9V}2ZMxbb{ zK+!mXqVWPn69kG55h$7{P&7%PXtF@j6oH~cg_@$>Duo9!Ams(=OJ}=>qK0&*e^{lI zd?iIkREi%o3q{kN4@F1Xq39?(6di4cqGRk(bgUhUjG}4C^|`? z=wyMSQv`}m6(~AQplGH*(dhz3X9yI{5-6H2P;{n1(OCjTXA2aaBT#g%K+$;uMdu3? z%@HWNK%nSCfuf6qnxexig=U3J(d6`r#%ZDG+jK3OTPY=9NztX1;>y|6K{Q>9<~tvX zF0(_?<#s5#!VX1O+M(zwI}}}QhoWojP;{*wimtOMx?Z5@27#g*1&VGGD7smo=oW#Z zTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=nx z6DWFLpy&gEq7Ma%J`yNeC{XmVK+z`xMV|^3eI`)!xlmK|c%^Vg2Bf@cx)v=6MVF_K zuD__1lCPxbn@aKKmZ9id=R?sVI~09qhobN8Q1pWxiWb|U=tnygEwMwDEeEV=pTWie+7#E6DZ16%I;})X5G-oo$Mi5-3_)plBI^qGbh&mJ=viUZ7|N zfua=!idGURT3MiI6@j8v1&US^C|X^hXbpj)H3f>+5-3_*plBU|qAmhOT?LA|2{lCx z)xuJ(GDRPz&pI|%Yj^r{(zU32wUm4%MZK!UjT=MJdd`QU_3co!fgOr^+o5PfI}~kX zhoX(`P}Ii`MVr{6Xj7Y_z5+%41d28jDB4`0XbXX&Ed`3U5-8eQplBO`qHP6=`U@0o zCs4G#K+z5YMLP-fE|j4*%S>I zC>kM9bf7@dK>|f11&T%q6pa=rI#{4+j6l&?fueB&MdJmECI}QAB2Y9@plFgn(PV+5 zDFQ`@3KShCP&8Gb=y0K?XwPclstibZLAn+V3Pri}9&K8+lzb&cM^%eYwFyN>J0FUU zu|v_Zb|^Z|4n;HUP;|T`=2C)*UAB2aXyK+$OeMKcA8P8TRTL!fAu zK+$Z0qB8}G&Jrj(TcGG1fueH-ip~=#I$xk@jzG}`0!0@J6kQ}xG*_VLVu7Mdgqou1 z)xx3-NO?xO{2UpI7N#+;T1vi>qRXqrhW4T83g<)7m3An)$__qNl6HT|0)NXPgg3&)T8rIXe_RZ-=56>`?Tg9g1GEL($82D0;;XMX%Zvy(Uof zx2BD_t z+iKyV3`lwXbS+vGipHk*XpL=3$yZX;rcLpqr9)9$=R;9DI~29ILs17i6m_&iQ71bT zb+$v%Qg$d>+73m_*c2@*P_&#t(eeUCD+m;=C{VPLK+(zqMXLxDttwEonn2O&0!3>G z6s;*xw3a~8+5$!E2o!Y@DC#Ou)J>qMyFgJ7fuePVnxaaZLftZ%qTA93)YUe%JN*+f zJas+Wl#;KcXoEJzRhJ7zy`2w58``00BRdprY=@#gb|~7!4n>>Vp{TDNiu&21XfvCl z%>|0K5GdMGplBD}9rZA!^kQgm#a;;k!%qT`$oMKkPBbi5skPOwAK ziFPPD$qq#)+o9+bI~1L2hoaMLie?HFoi0#xhCtCQfuh+0MP~{Woh49owm{K20!8Nv z6rCqfbiP2*9D$+>1d1*cD7r|XXs$rf#R5f_2o%i|D7sXjXueQWbab1-n;DSu7ul>k zCKUaU#$|0v$ycs*u36p6EmvGEpR3%MeaSXgc`1Rb{Fr^kwne3Fb~o3mvR?K@xJqTu zhFq>)<)YTPT&K#%)m(0w%IfWMxfLp7JLGb!RBrE-%dJuQW2szjol4(jbGh!76PC~A zdR3lVF_-IIsjiaC^{MQ+S}xbGa`76u+?JJ3*UII#t*qH4m)oH-zFRIgpmJxATyD3@ zUp;fVL6yzc&*cVJPU@Y@?O%Ceqg-xyrR^rU+{nsaeRH`nm3f=xauX__Z;{JQuB^Rv zE;qGu$hNuM^vd1a<#NYV{@EdyJHE2T&bi#ll~V@hax*J0?V8KYuC(7HmpiAj&!Ajx zPG$byx!l~!mxFV;ODkQ5Nd^No+)wcO+dR?I%^3@+6$$n4r)%409yXC9tr5Oh0tLeG*2j{El z$%Wk6NFC4SJN{*PR>`;Q}j*ESJQK>P0v@;lVlx} zucl`?IzC^0d|~!Gl&_}e8JU@{rYDM+ov)@x`k#}priW_J$yd{3ZRh5z>A{kh=Bw$^ zZdc^1>ETM(Y?`uEv0 zn!au2>3lVP-@)_wYWl+Q%lT^h%HQkxYWmX6+xcqx-240aYWn2q!hAJ-_Up5JHGTTx zt9&)xe=f>b(+$Mpd^LRp_;bFR-i803ucmA8-}zjd&gpaeSJeKKYr9VNUr@eh_LuC} zCHpf!x8LgdT)TC$|Hkq?duG2?x$M8Qra#(EETp#GtZc2B{kdxPXZs7XpDMpzV`@8P ze{Prk*&&0P%dg+mavl1lAFx4;S?Oo!-8dur0l5x$X8*b7H;lJDkp3+;it%bXvvG`f z(&!UomwYxhiSbAJcic3_8}-@f8{@$AZ_uwcI%fYp<G_RgF|FcEe|Jt?KYWI;hEuG7CE){dR^k=b9Xr9Yg^Q$(tEf*S>Zrr_N zHDBqN%QagiSI)lTUuewb3LSEV#*NAwmp3f;Z=3y6#amirhu6!c(!6!{W7GdAwau5y zwI7+!W{ZYgp@oCxaznXQxp(&K(X!+J^P}psAN9X}`f|)-?Vr{ve#&g7pRyr-%BHve z-=DHEe#-b!t+PYL|NHMzX~_OH(?7Y|^gpuy*KOkeQv5^OcFp(g>|bK_&eeRI=KVUI zzj^2MPi$BGU;lc|I^Ml`_KVZL*Z;S5_}^`r>>t+gl;iT*FYLLSckYq>G@VX8E}v`G z>CDYLWxx1cbA3Da={&Bn=^vT>J0vRcMEe@jy9azEt<%!{}E&)<^5d~RU+ zn;$gre|}K2>`m#9^iwp;b)UCs_V<3-pZVP2?5|CKER+2;y?^}|F!zPay z-fh^#!zWB0pTe*a!>3FfG3kH3E&cfHM{n3|!o*QyM@=4e=!jgmk>kgX=r(lBh^gJW zju}5}=$LMkMh=}gqT9p~<3>yxI;q=;b%#uvJZ1Q(@!ckmA3tW;$f2XgP3m^guwg@n zP8{2q5kn6c)ul)Gu06Y?H+Rk6{QtbE+o*BF z#!MMLqTAS^!$yu8_y7C9#-zh1{qJ9igGP4SY~t`KqsEQjV*JDrUH<3SV(R3HO}`|y zUy%V5$B)i_%_nu+b;8hz|A)2v43Db**EK$qm6bIqgrS2Vgd)-*bOfaLUQ|E@LPvTp zQUxrC(nLiOQ4q1Ch+;*W9Yh5YY^c}}6_BPNp6@T~xfA|-U;CW%Vsl-(=D9O7naq4h zCQV1Qo;12&PkUR2b{#osLci|K>UOI0zwt0l&YC#b-CL1}9_U)Nv#Jer4*CrmJS1z< z$cgzc-ie>nIQgy$Oo!??S!%w!SQPHH@zI!?q&Ff#0J)_~Q zmi^L%q?*||!7kw2ixa$Q8GaFW;!3@|dd|zMWWRiBweaP2|J%#M%TLkEz2xxqC)h1= zuh_kY>?^M3m(QNwWQyRhxdT zYqX8HV`lvtZTk%fPu8uSbFxm0oRf9y>zuXg)0%PN8nwfhwQ8aBWZIdBcN{ZjY-XfW zvtIpLbnaO*yzZ7!o_h^; z57^lTO&T?7T6j%5Z*5+2GlhCNH^A=DoNLZ`CAE1SEpzV-y9;ziyUF3*Xx9>+xa20( z`| zRquYyT6WLAoIR+zLkzD@wfv7uMn;YqJv1ZxU;hnQX6_AXE<;eW2Qd2;V9V*z-vzyW zIj^Nv_O;yP{=Q_tsD`e}`05rl&$(^xFKYIgn&n(Pvn3j8>18=QxDlE4bFL~gS0G{l zlbK7>-Wq$=|C=9!`4AqyXLs*&0GLC~-rIzCO|INbqZ_swyf7DYW@{e&T*G*=6dsah#Tab#U4E2$bC1+<6kHD_Jp>w-|$>cnU{FF z#8F+lA-ULjCz_efG5bzxHh4nKI(6F&9Mx)c_7kvc#tyO%u+5sa>@g|)*x|0hy)HZI z#%0=Hk?h2SYwzLoqFOokvfWplJ%s13gGZhRKIg%%Z+G#SoWCrlNSEcKkbB>yWS8NJ z?QcMMFWallK4EtjFU!4(?3?5~^t7iNIzJb*hb+4|2iYIo!jEaKaxQHTlCClL7Qn#n zM7=EM;kHL9d=0sL?0uJ=EBnf`Ut|xzE@dBcbSmc!F`D7!?cH|7p0kb*@0HB(pbxmY zU@~*Xw3y}#4EF@TM*W(#Gb)T9JaTZ>guxXvs*V~s zc2eVkc8?97T6I*dS{5b_n>1>G9fyn@lQprbeRj~;9+p8a*g1!com{8tgt1izW!ANl zHGbf*#`fvLNVQl3gV>7A_&8XU?W=2(elG}Ko-GHh?Mh%`YA#3R1 zsv`%F9y)PY;~JL2CpuN#qi)N+^O`t(%;>5U?3ub9Cs?z;nOQkIyesU>o8P^diT!)!L{ ze*OOQIRH;tbDy!o#y!XC(z-{^$M#H~pyoc=%zciT`xMijtm-as7tqNZ$2>jFedc({ z6Gxt%<~~d0FNAyI7~V007(PSHe#_m{Qaw}6ehb6DbvbV}f6H<#L)kq&9g*{nk7uE| z&lGc?C}!rqSHySDgP-%1H0QZy&eO_E{vzf6b;x~E$YUKoC3J5}&SMxpuZ*;5(c-F% z3hu8?v+<)cT8$boc+enwKHig0s0>DRB?samII?K(%2@&%oey_8t~#DdX6 z(IQ^aXtC&J(c;k((UJ*eqSeB$XXIS3J8@}BjGXxQ(ieLF@lyAdi|}h5oX2yYk6!Y} zv(H8C%UqZINsQ#P)hnm))xj`$k?b!d=DgI4*q6dC`Qt_GEA^NB@gkRgfydn*`|ABA ze?0rT|D}Jt?AM-Kyoi1M=#oEPB>yGLU0|=8syXtt2j`pR7?3dr9<2W5>>o{M>B|5Iv@nw6+-Rs$*<3W1} z-Tpzx^Y#X~9oQFM-SKjJTimgtj!o<#bGw6%S@t%#Jxa&*_K>-~NylS$2e|#0jy3H8 zal46*QwxWCfsSw5UljN94|GhlugSWdPsjH5Z5y|*({V|ua6hEuXLiTBmw&HgiE`nt zsN;b0;U1&o273V9`8VtMd!=xn*Rgiha5vL&x;;?t{I}`&R%W<&>zGtK+y!*(Xb-46 ze{UU^)erZ>I(~jtxPQ>Gq&@KN{FQYa)Fj;FbbPW|xL?-sc#ClVqhsCH;clVhjJDyv zL&xpy!~Kztu}-Y8yD_LIzBrg+^^|)YErnPlf&axQ^R8$9p_9B_gy-^JtN$o>XjmNdRmXC-hdWcpn-+$9ijEr>h5HR1&)gkuZ*h2Rv@|@n)A5$& z;a;rcyDP%IU&r+O!(Cj*o)3gOOUDORh5Ka#`EXyZ*+Xlf4FDr_|k!J@6hpreOJ@@Pd*eLn|~P|yXbiP z*Wq5F(?&WiJeAT`s>-IZ3+PA&4cOD&E+c#<5%X{d!$i7?a z_DUT;v2WYD{f&-A?fbWGU!h}P`$n$YBXnG6-_dpZc^!}1w|3n=t78rO9qoZ>iCO}XLR)Jd$;cP#@*3wXEW_qI@;5g>>krGuZ{(Dtf-@X_|86` zeOS&u*4MGKj_&!JyZ$~p_SG@T9qr2F+IGl3AFp?;dmd$%v!^qW1bgL0IbXF2(?(6q zvadl-m^eN>4&#)4zCAHg&3%F!sWxE3gh(~}l)RdY)xxjk{a>GXW}kVG`!chAp?}C2 zyPoXRSpx=)A3Qm{s<7Di2``;l7Xjl9H`^TQf+26eId9u5Vdps`vV|QovpVIbkcRnwi z|LuJ4W$w?F_K$n)|6k{;Vdwd;uXm(1{1-zX!>QgDF1@}CyS}j&-1RwIT;Fgz&1LLl*e>mS1+n2uHC9R^7{?^>voQtL;m#@3>u` z`#a&T&wUoh^*v;#xs08RT(s+R=i?7ATWR6a>x;C`y}ms5GOq7AJI!U>b);8{MrQJ0 zU-Gi2?DVDA7q{zkkCVH7?tKE+_nMt{*XKOAKX+D*M!Khkr`^BZ%iKS2>&W@OY7ou- z`4-FBe>k6g82*pjSK+E?wjrG@`}MlhAK5>b-oB!jyuI#y6}RuOowhe`tR1rd^t9`{ zieX3hdfgv)e~4-GWw^? zZq>1M_yZE*6-Vu}U#{1cD$}x;AHGkh5GiKwO{@NLu1l9wFHW4>I&bSOo$hbFr9;Z< zUFQ;;?K*e3#(q0Ss+>PmVAu;Ccb$u5?mL&*EmHOTp&rA!oGKdMX{E!-IX!lsJ62k}d;3eRnEGP#AjM3+;2YUM2xo+|Gx zZ+A~yJ8ie(SjMt;?%I~M|2}J3hyT2WUI~--bvgCIgj?EgKbM&KiTx9)eEv|YGpSyK zVcX9|@=YCfYdbqex1T#4pVqEG|I}d*MK9PT-s&-_{Rde+#@yiT_;XIPzpZS%uGyIa z-i%H&+K%aXAgkNZ?dR5YwM#_`^e;Q?{_rx_OztqH{gif7+y0Q{ZbjRZo5wagS)g02 z>_mIpH)bT9-k5*qxpk3*)3XMY?muv7fnh7d%XMpdvOs~}9Y4>(I+J0R2aY)?H)QD zFVMd-x3_Q8GygV>mM=qnR-R}>C_eEECUleZtZdQl>J%(Lx_r)is zEVJFa=OQ)SsTytHJ(rk$>fLiOcPw3{!@K9wGODz9uOs=V${i}VuhOnc_!`S5>K^(s z@xs0eZQcD7*&2x#ZW@Uu%z2_>B<-%nD~=>&Z79CAPw#}tqDZXgkrL0|KQM2H-EV%@ zsPfx8?8nm*=K8V3$ec*x+%A7FyP@sAqxU~Fr2YANd+N=~un%E9TEG6*ns#f}yi~N< z(rsJTXGSCQ=NzsaY1E`qB>$kafs-nZ9~Uh*<(4ltoZo5BKIhMUd{zG!CvE<8L*H`0 zFO2;1%Ad2!<;_>BZfe@jny;={(DD7D?gyx@uO8L=w8Usjd%u~s&EC77b?;>_`I8V$ zT4wKj6QZ%j_Wma!!T+L=I|SoO+dG-F_OFCaMeXYi_QM|ja{D0Y<+1mG30;cy&rZRh z%WTE`vM$Dg4~yA5vqay0Q8^(o=xSHweP-__yeb8n+1b5H8TPLl1$)|Qf3f{5sfFF1 zAaRDBOze>5&oo%Y-=Er@5>58DMh?J074(6^+0a0#OJ?|6`E*PJi-yo9~` z4T{^FSRhzs=P4NMw2x+mf?al=!oenc_ERJ{R>q!I1ZVB7EEX)Wd+xH}UhBn!@%FyE zL@=t9eIYTp!fr#U;Gn%UBj{?cv2?KG@<^mi@P%Dl+2Bh%XStxOJuSW>m|50-z%?ju z*Eu-w%h}KS294}CychgrxB2~`kUcg1Ab8Gh+lN7xy}i4GJM5f$V(0DNs1l96U^lC3 zG`7^vRV^BuX&*SMM`LMrYidMehwTO~iN+e*J-##=>ti=%c{H}n?z?-Uv8U|rT486g zb#FAb&F;4QqOpy3E%!%bTkVZs8I29Kmpu@T9kZMFU^JFwZ`G-2ENbg?G*;d|I-QBe zmfLGT8;wQm0_W^H?S}PAh_$d+^m;<Q|&3nQ7^X1uJczfcG1=` zFE-8Ym*2eD61y{g_hPr$z43<^b3bi)+>3ek8cukzV)kk~CdO*mtL>B+t7o^mb7E|k zJ^Eb|V{Popx+cc<*;%?J#`4(P-aRo^*$zDtV;S}udfNXQ#V&A7VyuT5y*4p+!tU4W z5@U%5tXE=erMc{#7<8RAH=>{)8)t7(AwTwr z-H54vtdreK)BIRFdpM{2vAZpP>Bkn@b$;c?>ewCmwI8cuSN)A28)moVupirGH}G3O z*3Isv@9fI#w(JdJ-`F`n4r1Hv;-3Vu`u1u+4Ps~PA>S9ozOtLNKZvcjd*ZVo_MycC z7VRziJczw#7e5%p7TL|+k{T;&qF+gkJ!V(-YHDnQy@uCPVk7tjilKY1jE!-q^i%o$K?)#@V{PKrEj<{kyureJH1HkJ$s06E)uJ5w{u33*jjrVW)_K+up2nb&S@8)T_kp` z-H~&O#I~4;xkX~T?M5_R6&qx)w%MxKXLe=HSH+Io-P&?h?1_v>q}8feUb{nDuZr1E zSV!8diuJR5qU(;>+xD_(+G7}XCsORucOL_iqxRa}H!x z=D0gC)XtO7otS73Z+>^;J-f#WxDzd`6m%y(um`!2J8{Zhm%G);uT$Fo&0**`c)^tzP5hT$#0;oUv%=X($?=e`3<%8 zYfgS6ZT*&$-&k9}1C-n`rA-ocyNR`VA+)nYMnx$#1T$-*56;XzSOT{Fd7K z?IypKwtl(EZ>?>Qe|n-{&g){2f8OcF$G;-`cXjhFw7=GVo1m)w#dktF_+5-twvdjx zsDyOVl#tGv64FIeLb_^7NH8>duJv1exr>2Blqlu7fwGnciHbQ!7Bc!)BLi%VU z_z_W0*rV(+p1_Mwof_P*R788|sk$XI`z@yQl4P8XGs@tP7cK~q8| zYD&l?O$nK-DIrrdC1k3mgiOyR{LrSQ{Zrv_m1I zz2)}!=Y7ha>G)$pAzwKmO9Lmz30dJUw-2}3LhjW?CFDL$3AtZWLRM-@$OD=Z@}Q=K ztkRT_hcqQ*wWfqTtcj2{+6Z|>8zGNsBV?^MLe^;`ppB3xv=Q>8 zHbS1#M#$6J2zf>uA6HbORQheDQno9*$>yVjoC z`1gcD8rV}I|E0jmaYA18H`|k>Y$31dq7w4Dri8qqDIsraO2}4C33*FXLbhp2$aYN$ z*`X;RJ2erqOB*3?Ya`?xZG^n5jga@W5%Rt^LO#$&$cNep*{zL`J=zHQNE;!0wGr~M zHbOqpM#!hy2-&BNkp0>S`Ai!j2ec9Lxi&%$Y9r*3b|_?vcfcP1yu0m5tN%(U6= z#Q!32a-5KF`~&uRLbi~@x~PPFt0^JhX-dfVni6tEQ$l{wl#m}aCFCbf3He!5LVnRi z$Wd*C{Hl$RW7-J$O&cMIi-z|)7l6*qm7WW+6XzP zjgY^z5%RY-Le6U=*mkDfz`TS)F4!%M6AHRuH!&ZffD3jT z^AqyBU^lV=A)gC&D+?0hF4)a1M9Axc-Oj>`M#&716-)a*8TO z{VaReldY%{mzSc-Y$>Y3mZGX`DXPYnqUvlZs==0`Otuu&WJ^&kHi~K!P*jJ2qPheW z)gz#&J^@7y2q?OWfTD&36g48Cs4)RWR})awgn*)^1QazRpr|Jw(f81bYE9%1KrKl@g zin_6-s5@JVda$LaCtHfHVN21qY$>{qEk(W9DC$i>Q6B<|t|y@A1_Fw1B%r7-0Y&`? zDC$o@Q5FG30|+P@NI=mb0*VF`P&9;qqM-y74I`jvH~~dB5l}ROfTEEE6pbRFXfz>I z)G_LPXh7og?W=QsCn=g^?}Pj?(ZKm~iY7$;-|TCT*@`A|c`2I2mZHgQDVoBTqN!{t zn#Pu*>1-*wnJq;#*itl;jiOlu6wM}}Xbu5Ia|tNAg@B@Y1Qg9DplAUBMYj@AbQ=Lh zw-Zow2LVM32`IXgfTBeN6x~HY(cJ_TEheC72?0e*2`E}dK+$qSsAyc&%Wogd;wRk` z=kZe1(T#hef%D}Q-5>R9+4mo^6|Lm*QuF{@iXLQ3(JHnSJ;aux)odwxm@P$X*i!Te zTZ$fKqi8JwMe7JCdW?Xg^#l|>PC(HH0*am>py){gik>2%=xG9qo*|&)#^L_pEY1Qcx{go^Hsdc6!te3g4%be|OM&;DF28aQ80 z(Hl{JT4^bIlgmrdR<;zq#g?LNY$@8#mZBYODcZ@FqFrn$dYdgp@32wyE&)aF5m59# z0Yx7WQ1l@IMY{Y&j=_wKtR#w1QZ=4 zpy&_*MPCq5^d$jBUlBq@uSLDp1|+`0!FgSZX4|*L{I8>d^W_wM7xlN=_p`F!7k$s= zrRWG-ihf{A(T{8?`iU(?KeMIi7q%1~WlPboY$-a%M$vBs6#Y&>(H{g99VejZ1OY`S z2`KuLfTB|b6rCoZ=nMfxX9*}eM?leE1Qh*EK+$;uiY^dP^bY|=7YQi(mw=*3f1QZn}pr{A|MMViHDn>xjWdsxz zC!nYV0Y#S+P*jqDqEZADWe`wQnt-A*1QeAepr{-HMOP3|RGxsMD+!?@Kf$YHK;pIR z8{mFYLim~fYWw*Dzd}Obd^tr`68sJoq^K&Fm!fKHDXPwvq8e-|%4ADXO|}%(VoOnN zwiMN2OHo}mis}(iRG)yN1_TscML{qEk(W9Qq-F*MSa*(bUhnIHxN*C zBLPKy2`K7EKv91Jin0hO8bCnNKmv*e5l}RkfTAG;6b&VyXcz%S!wD$5iGZRJ1Qd-V zplB2UMWYEQ8bd(QSOSX15kf^>61j@}&oPeSY1Qb0%K+%%~6g@>i(bEJJJwrgz zvjh}9M?ld=0*am|py&kxiZ&5Y^dbR8n+Yg-iGZS)2`Jh^K+!7%6unA7(QAZI(aHp` zxdDk^a9^%|K#D5c5Ayi0Cj`!yQ}kAXKQL2@wsCnW+Rm1u9c(Gu$(EvBY$xj>PXdZg5m0oRfTA-56rClY=o|q>e-TjhHvvWG2`IWiK+!)06kQ~s z=wAYg>^~m;pgoNC9d&z3;=UUjC7>vQfFh58qC^6Ud_t(``vh-~0f~3B?{N4>q-c*D zNnYT5IYlX+|3@7uO6BrWl*X2#JZvdSXG>9DwiLzLQk0J^MfurMRDdl-1=%PnL_kqt z0*ZzMP`!o?oZF6xHDJ zQk2P-qMB?es>PO~+H5JR!Y8mZJJ>DQdt*(NzQ#H6);@5dlSw2`IXnfTAV@ z6g4HFs2Kr8%?T)KK|oPU0*YD@P}G`$qBaB+wI!ga9RWq{2`K77Kv72miaHTc)R};y zE`(4~RnO~VK;o6$yPs-ORMoT5)eD?2r>Ljr-+Yx6UBl(2=vuZEUB{N9UTi7q&6c7* zY$>{)Ek!r5rRYYs6!m4Js2>4E{Rt?_BA{ph0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP? zpy(z7ibfDnG?IX#Q3Mo?CZK2x0Yzg8C>lpV(Rc!iCJ<0Gkq|2C?s;nrNW80iUerU1 z8oDn*PVxfh%PE@X`P&*v(R3~^MK`mhXa-w~X0oMd7F&vDv!!SbTZ-ngrRWy66wPC! zXg&c&3kWE>m4Kq#2q?OpfTBAHC|XEB(VYYoEh3=kE&__~CZK3B0Yys)C|XKD(J}&x zmJ?8P4*^9h2q?OjfTH^dD7v43qLqYD(G<`7(SXE{xF46EDn*^0q6fUd`ErU@dw$SF ziXP_jQnZFGMUSwh=ux&5tz}EmI<^!&#+IV>Y$bc~uNZ{HXhG>_bx2%)SfjZ}kG_%PHF7`JI|c(M~QeMZ4Hi^fp_H z-eF78yKE_Xk1a*-v!&<*wiJEHmZIHk6zw6P=pzD(_7YI^F#$!N5K#0f0Y&==DB4dz z(Psn{9U!3Sa{`JE5>RxAfTAx5DEg9sqOS-j`kH{EZwM$lOhD1M1QdNoK+*SvP|-He z8*f13x4R#;-Y!Kw?5ETGBVOQqIYmEv{_+-5^b41lqN8jn`jst3$JkQz8(WHgXG_r^ zY$-avH2F{mLlqbYCmZExWDXPzwq6Ta!x{57D4cSuEh>fDg1QcCOKv5F{ikcEo z)Qo_l<^&YAAfTuv0Y$9{C~8eWQ5yn^+7eLIj)0=}1Qc~3pr|7OMV$yJ>P$dU7Xpg9 z5>V8QfTHe%P*IIUucZNrzw3VPI#Y_8y3r#saK4

k|FJ?WL#}mzSd6Y$@u)mZIy~ zQgj1bif&{}QD3$c^f3_55u~9UDfTDo}6b&MvXfOdqLkK7uN_YMGFZix|4vSMFbSxML^Nr1QabMplAsJMN0`NT1G(8asrC( zA)sgl0Y&!`P;?&wMfVd>w32|L2M8#7kbt69giz7+L~pMFiT`EOzgdcEx-UUKlo&W) zPSGQY{)x^~^eC5?qP1)(TE~{6$JkP|o-IX>v!!SQTZ*1wOVN{TDSC>HqNfQcdWL|a zX9*~Jj)0<#1Qb0_K+y{X6m24)=tTmGHWN_v5&=ao6Hv5;fTC9jD0-EEqSpv0dYyox zHwY+tlYpYF1QfkRK+!frsOaHDuW%Prbi)03;~FW-@4g+fJuz^;oT9fA{d(P`=p8OE zMenku=smU+z0a1S57<)lAzO-ev!!ScTZ%qnOVM67iasWw=o12pJ|&=N9|1-C2`KuE zfT9Bg6n#!W(Ln-=4iQlF1p!505>WIN0YzUEQ1lG}MTZF}`j&vA?+7URo`9kw1Qh*1 zK+%tcP|?mr?*;=BFX29j?UJJEX*PaJ44f~g=+{JlW)CSk#^t5xH?|c0&X%G-*iv+y zEk!5TQgo6nMSrrT=oDLuPP0*ThJd281QeYkpy)3GivA{`=sW>M7YHc&hk&As1Qh*C zK#~1g_Jei@Cq_{eC7>vQfFh58qC^6Ud;*G+2q+2&D2fqKluSTT3IRo_giz5hiQc0I zBtFo6x%#LSxu4qi)BM2sa*E=Ql*fTAl1C@N1t(Uk-g zRUn|KA^}B}2q>ydKv5L}imDP&RE>b5>I4+kAcTt2eeY)j62H#3{7k=)`|;UK zKXAUBqB_2x+)Ik;a(OAL$Cje{Y$PA3OcLIuf5Kz>UfTC*%p`u#8SIvOL&p0@>rD%@(;?cE!;CwkneSE)5A1S(?%S+J> zY$>{tEk%9VQq+$vMg7@Ql*N{!0cljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6ip|D zihB9pL<179;ePJAw-nvu{_9mY`+@W26wUVi6*oxH94;?KbJ42 zEGep=&&C=*aK4aUnzQw%S+LEwiG?imZA-8DSCn}MNhJ&=qa`oJT|2fTFhuDB4Cq(RKogb`VgslMpI;)b}F&Ownrh?q{tO^>p6>+2se$ms9kf z@0ZS!qW8JH6n(&!q7T_pw3{tOd)QL+5nGD(vZd%_wiJEBmZDGDDB4Fr(S8DoJ|m#$ z00Bjx6Hs)JfTBYL6n#NJ(U$}ieMLag*8~)OLqO4C0*byRpy)dSioPeH=m-HtKM+v# zBLPJ}5m59q0Y$$MLPhWRUTXsqU+uoo_^uR1qc)EEf%D}Q{qFli2TIW&TwaQfv!&<+ zTZ&GyrRYz#6rEyA(P_36oncGSS+*3NW25LV0*d}7py)gSMHdJt`iFp`iv$$?OF&U1 zNuRc(C`v$40s%!H0Y!-f6!`=cB@s{*5Kt5&peUJuq7(v(QVA$ZBcLb`0Y&MAP|-2p zTVz1uWt^hlr06sE>^g5!;Cwkn1(N({21`*vE-yue*iuxOEk#AxQdE>JMa9@sbQxQU zinFDt1Y3$OXQQYj0Y#+lXP(MSS{ zMiEdnnt-A)1Qd-WplBQcMdJx5nm|C&L;{K?5l}RlfTAe`6ip?dXc_@U(+McLnSi1h z1Qg9Ago>_D^7{vEk%piD7uS)qPqzwT1-IE5(0{r5>T{^fTHCD6x~BW(Fy{J z?j@k;J_3sFC!lC00YwiGQ1l=HMXLxXdWe9c)dUnhOhC~Z0*W3Xpy*LTsAx`-x6XjX zKXyO8KUa!oxOYrzlLF_)diat#8Q^!fsZZ0oHd)QL+5nGD(vZd%_wiJEBmZDGDQnZgPMf=%O^cfpP2M8$o zoPeT(1QZ=2py&$%ioPVE=qmz>z9yjP8v=?B6HxRm0Y%>tQ1m?kMMnrI`hkF=9| ziGZS?2`Ku7fTE)W6#Ys-(J?}(==~(Gh5?B`onuSUUu-G*n=M7>*(ka|K+!)06kQ~s=wAYgB7r__ zM^Ti3q67kpJOYaBMoGnEq*iv*kTZ&4urKl8JiZa+JDosF983KyR5>Ql*fTAl1C@N1t(Uk-gRUn|K zA^}B}2q>ydKv5L}imDP&RE>b5>I4+kAfPCdfTEfN6xAZ2s5SvbbqFY`O9&Me47}G3 zNPMCD5>cTb{7nCX`-oOA2%ImcsA1rLHARXVad|0f%$B07*;3SmEk#Y)Qq+tsMa|h# z)PgNVE!k4kijAVy1QfL)pr|bYMePVEYEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?Q-3Tb^ zPC!u)0*ZPPP;?CeMb{EgbR7Xjy$C4kO+Zl}0*bCDgo+vjUcyvU)X=>zx=M-`xgWy5 zAqbo=r>KA6mz^#}SzKO<2C$`QAX|zCv88A*TZ)FTrD!NyiiWYJXgFJnZepWo1OY`O z2`CyxK+$LdipCI7G?sv(aRd~NC!lBo0YwuDD4Ik-(PRROrVvmxm4KpY1Qbmtpy*}- zie?Z{G?Rd$Sp*c#CZK2zAym{i@Y))X_>b=UX#J$<-V7UagTVQ6iWUU^@EKBcE0>p| z+t^ZcJ6nqGU`x?LwiMmTmZC*$DY}a-MR&8MXfYc_O9&`hN zx|e{W`v@qypMav31Qb0$K+%H)6s;nl=ph1%RufS4Fabqt2q=1lfTBkUC|XNE(K-T( z9wUT`<^|r}1|(j^eTitk6!mpqyIvmz&X-g4WZ*wHONyT2@>29PTZ*1xOVP7zDSD1A zMH|^t^gLUNUSLbnCbks4$VSm-0*YQDpy*`+inb6?^a=q*uM$x78UaPG6HxR90Yz^T zP_&hRqPGYr+D1Upb^?la5Ky#}fTCRl6unJA(K`eby-PsRdju4{PY4xl2)um;B)-l4 z^!^i4^tJnX(FZ}`d^trQ1^($dQnZ)LOVP({Df)yhMW3>zXdhdO_OqqvGqw~RU`x^G zY$-a(M$sVxioPJA=t}~Mz9OLLYXXYCA)x3m0Y%>uQ1l%EMc)%pbcBGS9|$P=k$|F~ z2q^lQfTCXrC^||&(XRv)9V4LVHv)=&C!pvLLa1nW;9WM?6fG=ZaP~-15BH<|$AiH6 za*9p`e#3cEbehXc(HXWBon=eWIkpu2#g?MK*-~_#EkzgDQuGg7iY~HI^e+KLk(fT^ zMp2Z2q67kpJOYXm2`KUjC`uxrC?KFHMnF+A0YxbU6r~bSltw^N9s-Ke2`I`-KvA54 zqI?7t38A8sf!E)F#5)uq6!2QRV1LO5&=b( z2`H*UKv7i!imDM%RGomL8Uz$&5>Ql=fTCIi6xAl6s15-|bqOe{M?g`10*V?CLPbSl z-g*NPFI3Lp6pe+S>6dW7Npw{#aK4Kd|c_|vqmZBkSDH_U_qG4<)8qSuYo7hq`f-OZO*-|u$jiS*6 z6pbOEXeCPK+(+v6wM%@XeI$g zvj`}fO+e8c0*dAmP;?6cMe_)uqO6!#(}2Y9yUgGWkfMuD(fnB8d^tt8$NV0Pr05PV zFGUO4QgkOeLPfX6yr~8x-rRk;`Zg&l8N8ku61=*;4cpTZ&$0qi72OMXwN0^eO>GuMtr6Isrv*5K#0c0YzI0D0+*4 zqHP2eZ6}~;2LVMp2`Jh{K+)R-6um=0(Ypi`y+=UN`veqyKtR!l1QhKigo>Vud2bq! z_~e+ud0L9Tb-z}$Cl)wgPSGbZ|C=RJ^eLB@qJ3;B+Rv7v&)8CQfGtIzv!&=DTZ#^` zrRWQ`6n)7?(N_c%eN8~oHv|+NCZOnB0*byPpy+!7ijELa^aBA!KN3*%69Gj(6HxRE z0Yyg%DEgIvqGJRU{YF61?*tV6K|s-Q0*X!$P;`IZd!HGQ_$%(` zuA53xAA6ZUAUSZpoT4Gg{@ImMG?dFr(J;0Y4QETyO>8L|!Iq+tY$+PWmZH&YDH_9; zqOoigjU%9FJOM=$2q>CJK+z-uiY60KG=+eosRR^FBcNzH0Yx_xP&9*pqL~B~%_5*^ zHUUL*2q>CMK+!D(6wM=`Xg&c&3kWE>l@KZ#l*u8CQK#tRqHowJI!r*(w*(Y@M?lf{1QZ=1py&qzihd-Z=qCb-ekP#k7Xpfo z5>WIj0Y%3MDEf_nqTdN9`h$R?;{+6)AfV_Z0Y!fjP;`obqSJ&>(WlAY?*=6PiTiT( zJ}Ii^K1Vx~95`Q2(cj5_-nCM6p36(o1-2CZ!lMLq#VNdy!H1Qf*xC`u-vD20HcR04|92q?-!Kv6mYMR^G*iW5+jkAR~51QZn@ zpr{}LMTH0`Doj985dw;e5>Ql(fTGI?p`vriUTp&sU+2Ei_?HwVy8jGK@sz;%a*9f& z_}4rpMHyUPib}Jks0>?*%Ce=X99xR6U`tVXwiI2-mZA!5DXPduQ6&P3Dicstg@B@} z1Qb;xpr|?lMKuU0$|RtuCILmY2q>yeKv5k6is}+jRF8n7`UDg;AfV_f0*V?EP}GQk zqQ(RiT}?ny6GEuy@)U2n0g2~za7w0xpXtBqM$?qQ`ErU{ruYv&E=8@lycD%&OHmuP z6t!hbQ9HI2wP#CF2euS-WJ^&ewiI<{qo@l3MO_If>PA3OcLIuf5Kz>UfTC*%D7uz_ zqU#7K>P0|NZvu+?5KweI0Yx_uP;?^!MSTe<>PJ9Pe*%iK2q+prK+!+~iUtuvMa@&Z zw+u+UzxyE8LW&xs*%+J>IA2cD@D%^sC#2{mE-ytR*itl-Ek&c)QZ$+^MPt}fG?pzz zCMK+!D(6wM=`Xg&c&3kWE>m4Kq#2q?OpfTBAHp`xKFUec4MXqx*D$S^6Y>wX7h zVM^e9IYoD;_*XtHMT@z-6fI#((NeY)En`d3a<&xR!{zEk*aSrRaV(idGU( z^Z)@x4-!zcih!br2q;=jK+(el6s;kk=n(>n9wne?EdfRA2q=1tfTHyT6g^Hr(FOvF zo*eihd%X=w||oej%XfC;>&k z5>RxEfTG_BDEgg%qCW^II!-{*2?B~v5>WIf0Y#?>C^}6*(HR1Y&Js{`ju0yPEXDiW zfW&vXU;8*9MU4U*f29P@ms9jlivQOOQgo5aOVPhP^C@1*O{S<|S%Y&yir#TwJSv$Q zIA2atnN+{YW+^Jm<)x?`TZ*n=OHp~Y6kW-dq6%y&s>qh2N^B{r%$A}mY!p=`pr{%F zMb!x?szE?eCILk?2`H*XKv8W1is}$hRF{CFdIS{JC!nYS0Yz64P}GosqDBN1H720w zY66Oy5Kz>VfTCsu6g4M=iZW8YK?Wo~HpAeQP7OcPKj{8rMlDhU=gTQ-lj<*cS&G_n zc`0hgmZJ7-DeAzMqK<4S>cp0!&TJ{_!j_`0Y$@u-Mp1VHih2-G)RTasYX~U1mVlz` z2q@}BKv8c3iuw>xbUgt@HxN*CBLPKy2`K7EKv91Jin0hO8bCnNKmv*e5l}RkfTAG; z6b&VWidv<5Pa2T;68GKM)>8DXd&e{^HE_P1qLHco2d_xcC@wEWquEk4hAl;7*-|u) zEk)zmQZ#`rMHAUlG>I)mli4VmLO{_}0*a;)P&A!@qMHdQnn6I(Oah8#5l}RnfTB4B z6wM`|=oSKs<`GadpMatT1Qgv$K+$ak6x~ih(H#U7EhM1mP6CP+5kf^brFzE=Nc=hX z8`dMF=o5RHe^+YYd^tr+Q~i9eOVKheFGb7QQgjbnidL|t=w7xI-N%-q``J>ok}X9K zu%+lhHi}jeQ1lQ1MXL!YdYFKsH3SqrLO{`@1Qe|$plBTdMUN3sw4Q*X#|bFfKtRzG z1Qb0uf1{gDpjGvZZJ%TZ-Odqi7oeMcWA| z+Cf0kP6CQ{5m59t0Y&c+Q1mVVMeh+%^gaPa9}rOVApu3Z2`Jh_K+#786zwIT=wkwk zJ|Up!Qv!}Dxi=iV_LNDZ7Xr|64R|Dm^}=u0jy zMPIR{=xeqVeZ!Wb!)z(~mMul!v8CvHwiF#v{Y*g7F9Z}FC7|e6 z0*a0iQ1lxCMZXhJ^alY&#|bDpK|s+-0*d}5py(6Ahoq=pNgEeZ1Lw;rilq79Zk>*$2B}L`AycAu@mZA!5DXPepqDpKjs?3(6Dr_mL%9f&PY$>YF zMo|p{iZTf(s!2dmEdq*a6Hru#fTFqt6xAc3s6GKj4G1W@ih!bq1QazQpr|ncMOPD0 z)P#VdrUVolsW(I5hf1`|*;gn*)< z1QZP;plCP&MK=*bMQzi(dkjeYM)xJ6c2cz8{Rc!wqy^5GQ#2;c-~65wjpg!EG>$Dr zrQZ$7vMN`>QG>wg-=>!zrOhC~L0*Yo5P&A8xqS*u#%^{#@ zE&)Zi5KuIafTH;X6fGd2=vD%XZX=-Rb^?m-AfRX=0Y!HbP_&4EqPqwvx|@Ka#e`7N zs5I}80f~=rKX*M^ie|bm9xX`=oG+*7o;3gb2U4_x%S+L{Y$>{rEk*aUrD!EviXLD~ z(SvL$TE&*4huBiInvJ4|2`E}aK+z)v6g^5n(OLqE))7$j7y(7=2`GA;fT9fq6g@#e z(USxeJw-s#(*zVfLqO591Qb0-K+#45ik>H+=mi3bHW5(tA|X_?EX~XK&=lS5e(rj? z6g}g6n)2*qVL&Kbc8KMKd`0fN46CG#FnC;*(myjfTE)W6#Ys- z(J=ywej}jhcLIw3AfV_t0YxVWC^|_%(Vqkqog$#0Ds4`oMs<5S~ zDqD)Gv8AXwTZ(G1r6`jvMK#$dszpFiZ32qw5KvT?fTDT?6xAo7r~v^*R}oOukbt5_ z1QazUpy+A>ikc8m)RcgtW&{*9C!nYW0YxndC~8GOQELK<+7M9GmJli`pU10jK;rA& zC-+xM(Kk*}yF7vOPQ6vX76C;A2q+pzK+zxqiUt!< zG=zYnp#&5SBcNzF0Yx_vP&9&oqLBm?jUt4KI^^+Y8IbsT_jA`Br6}f}B#q7!IA2cD z_&ol@2c>8NmzSc6Y$=+=mZHgQDVoBTqN!{tn#Pu*>1-*wnJq;#*eIGwK+!A$ie?i~ zG>3qqxdas5LO{_x0*dAnP_%%6qFV_lx{ZLM+X*PTgMgxi1Qgv#K+z%sitZwy=xzdv z786jkgn*)@1QabJgo?)I@pc-J_zd^%XPgvW%wuDDp1}EXitfwf|L}zr-OuHvXeC>U z9$-t+gKQ~U#g?Ln*iy8bEkzHrrDzRXiXLI3=urZS))G*(j)0=a2q;=lK+)p_6m1}& z=m`Rfo+O~?DFTX~CZOmU0*am`py)XQiZ&8Z^gIDYFAz|)iGZRP2`Ji3K+#JC6unFc z6|KnQrF?0Mes=GR?vWIp z0Y#q>Q1mGQMf(US+D|~yX9N@-AfV`T0*Ve2P;`iZqAv(2`jQYTdNq&N)quo5En;w9 zlcERRw?n?l6F6T^(YJa0afhYoJ1#Fp-?OFY2wRGNU`x@DY$^JQEk!@GrRW#76dh$t z(XVV29V4LVHv)=&C!pvL0*a0kP;`QTqLTy^{YgO4DFTX46Hs)9fTFVm6rCfW=r00_ z{wAR4JOM=)2q^l8fTD{86#Yv;Q6ycTn4>642o-&k$Gg{n#3#BRZ#*nT$4c8sNDrJZ zrzk1ifB8Ep3b?!!#n@7m%$A}QwiKnZr6`RpMS0j#l+Ko-ylg3ovr&|ffTH{a6cr$# zs2~AFg$O7rOh8c)0*Zs3<)SWFwJ=jvzlPyKpu%+l) zwiI2*mZDy4DeBFZqCRXCT~9#K4FnY3NI+3v0*d+(P}HA*qAUW61`tp*kbt5=1QZP> zplApIMMDWF8b(0TZ~}^MBA{pl0YxJTC>ljT(P#pS#t=|6mJllHobC-XAn}v##~Zsy zQE~Sjka6jO^W_vxO84*hMT#bKc`2I0mZGU_DVoNXqUmfYx|uCSGuTozlPyKF*itl` zjiNaO6wM`|=oSKs<`GadpMatT1Qgv$K+$ak6x~ih(H#U7EhM1mP6CP+5m0m&0Y!Hc zP_&qUq9p_rEhV66839Gh2`IXUfT9(IP|<{R?^y#9FYi8xO_ZY2j?}&Bf%D}QJ&^8y z^s5v-$mOMI6H+=mi3bHW5(tA^}C42`GArfTEWP zDB40m(JKTLy-Elb-JkBAG9d9^+|OOFl%kdiHeO2)oG+(nYr0?PcPV;{%S+KVwiIn= zOVJLt6zyb7(Jr?VDE~(VOMO34f}iFGxxRG;Pd?czjNOId)}NA?)h9hK<7QG0-qL%k z09f=o0E^xLV9}cZEP4xoMQ;PJ=p6tSy$isi_W)S*J^+h80ASIFfWV@M+J*KNLDHYo z&s{%k7EKLF*xD|veyK&Dw(}0yZWevU^k&iLWV7fCvRU*c*(~~sY!+=Jn?+xf&7yC} zX3@7~v*ANI{;YpBLItj0$|b404(|ifJMIouxKX$i+%%O(eD5( z`U8MPe*&=RF8~((4Zxy*09fRt*=;)(xd1Fm0$@=HfJMoGz@m@ag;t9o>F4X`u0Ju0 zChJGmytJ_Tr52^8c~|T(i&`wx99RXO>34leN0a(-pfJI#aSkw)GMcn~dv>O16asXJ=1As+6 z0a(-vfJMClShPC;i}nCu(VhS->I1-{y#Rql;k3|`B1rmS`k*nA7ToC{tDl(NJ1wk! zsYU(Myf1z-i*lLXEXpIBMfqg2XaLzP8b~&a29eF8!DO>&2-z$eN;Zpzk+Env0E_ko zV9|a6EE)m8qLBbB+8=;LqX1Ym8h}MH02Yk_U{L`8iwXf)R0P1HVgMG61z^!Q02Y-1 zuxLC0i%J1lR0hDJasU=p00N8priI%4EEavKZ+i4Iiw5~OY-wTjOD(EN^ZNa27S%Gn zSyV?hizbrIqDf@4XfoL>nnE^AjATkym48Wp#02WOHU{M1Ai>3px zXa)d_W&*IN5r9Rr09Z5|fJJivSTq-aMe_hybO->8<^!;30RW2@0CK|U$!5_JWV2`$ z*(^GeY!)3wHj9oXn?odv+6vjJFi4gibJ1z^#604zEmfJGMou;@Yn7F`4g zELxrxx<~{`U#Tat!_1-@{XW{oX<_wCExIhtyYCOPXdTm=MVFJ!qV;66=nAq~bS2p= zx{7QTT}?KNt|6O6*OJYm>&RGiJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2viv;lxc zw*#=~4geP23BaPe09bT40E_McV9~t*EZPXbqWb_?bUy%#9spp`g8(dg2oP9wXuun2f(8D0a)|_0E<2ZV9{0p7JUT3qK^TAMUSS1djBmJeXH-I zJ!TeV>P6BgX<_wCE&3wOD{^!O^116Tncgh=ifk5bBb!BElg*-U$Y#;EWV7fyvRU*! z*(};lHj92BW6=%(7X1joqMra*^fLg9egR<7uK+CC3BaP?09f=p0E_+rV9}odEcy$8 zMSlaZ=pO(U$^RyGscfWV7mHi~79|0&CYP zv7eho|LEy0k{(vS)S@=&-l<7uQCp@ri`tRRqBOEulukB_GRS68CfO`%Pd1A>kjq%3jm9{0Gm204yp6 zU{M(Wi^>65Q~|)EN&psB0kCKSAh0MmJ@ktRl75uFkCtZ^jnj8ytJA~kms&J2-OCP} zMU$A`ESgL8pxqN!xF=m4@=bRgL*I*4o*9ZWWh>d9u&G%^-70I+B}0E=b-uxKU# ziy8q~Gz)-5vjJE%2Y^L$0a!E-fJKJ@uxLI2ixvQ|XdwWL76GtmF#wAW1z^z<02Va? zuxKd&ibVRy$P^ww9is{XwBgtmb zQDn2|XtG(fnrs#wLpF!wM3jtVk5de!W24K-8 z04%x`5LmP_J#?%HlD@Y{ zMc0tcqHD=!(RF0A=z6kQbOYHex{-`UHvzEdW&jr50>GkM0a$b!0E;#Nu;_LG7Tp2B zqB{XtbQb`N?gn7dJpe4a7l1_@0a$b&0E_MiV9^5rEP4=tMGpb6=wSdBJp#a@M*)FF z>(WC{iy-Nh`ZoUMX3_Ebg^^hCP%Ra>*@Nv1c8o+6t?Pm|4}XUJyJvt+aA zIkH*wJlQOIfovANNH&XJB4g3Z04#b1fJLtYu;?`a7Ht7w(dz&#dINw(ZvwFBEdUn1 z4Zxyz09f=c0E^xOVA1;kEcyU|MIQpNXe$7VJ_2CT#{ew)1b{`K0aKw#0P^iaEY zVo?|UR^w)~=u~|-_Ve_x`lS|aOZRfq&7!ZF-YoitY!-b>HjBO^n?>J~&7$pOv*-u1 zS+s*}7X3&zi+&FT|EQ*rNqHMBR)RAl! zbs}R?X8;y;0bo&A02XxvU{QAf7VQSWq8tDg^#EW|PXHG60$@>Z02b{Iz@j|>ShObq zi~0btXfFU3?G3=9eE?Y07l1|m09e!?fJM20z@oMpp-V)N^y@qkr(H&Hr$1DmI_71B z)i1SZP=@zF2eW7})0;&@$Y#+{vRO2YY!(eCn??JQ&7%FtX3+?;Su~Pt7VS^QqEP@W z8V$gr7yygL0I;Y4fJKD>EGhzEQ856E#saWt8~}?-09Z60fJLPMEGh$FQ8@sMDgani z3BaN%02WOEU{N&yi)sK^R0{|!8jum%DuSes(wqB%X3=kIQC&t@{ZfmjWO#12Su~aD z&7uRyX3>FUv*;kQS#&VjEUG7)MbpS;Q3Kg5noc&0W{|OHCIE{X0a!E(fJL(bSTqNK zMRNgIG!KA9hXAl>J^+gr0I+Bw0E-p@uxK#=iw*@~(Gma_H36__DFBO>0kCK}0E-R- zV9^Qy7OeyX7EQ_s?ID7s->X;Glg*-Ydq_AuBdmU@MMq_LV>_8eM>D-yw3=)d9YZ#Y zjwPE#$C1sVHDt5sc(Pe^0@*A&k!%*7M8=|%0a$bj0E zodv+6vjJFi4gibJ1z^#604zEmfJGMou;@Yn7F`6uqKg4obO`{9E(KuGS^ySZ2Ed|q zfWV?v8KLHj8c~n?*N~&7zyhX3;HVEV>ndMYjR4XafL?ZU2LV|05CDrF24K-604#bGfJKi1u;_6B7Ht9q7G04M zx-=mF)bER2yqAImHBdmU@MNemVuXQtvo?&{k=vlH^^c>kNdY)_+y+AgLUL>1E zFOkinm&s<)D`d0iRWcU62Ed{%04#bPfJJWru;@(y7QF?)qPGE9^bP=v-UVRMdjKqY zAAm(40I=vo02XZpV9`eaEczILMV|n$=u-d|eFngy&jDEU1pte_1Oyg6nGxD4f~1e{ zBH}z{7Ol~5HGY*5R=?DuZ!^43IcCv!Om7x_Pd1CTlg*+Z$Y#+FvRU*a*(~~rY!>}Y zHj92Cn?=8pv1lg%i+%%O(eD5(`U8MPe*&=RF8~((4Zxy*09fQ?+HE@)xd1Fm0$@=H zfJMmwEb;(Ylmft_FaV1p04z!cU{Nao7PSUoQ5ygjwFLwgeVq~7Uj#}2Izz1Vv#2B4Eb2ryi#n6dqAp~!s4E$Z zx&g4LI{=Gz17J}O0E>D6u&5^hi+TaDs5bzMb_Zb59sn%b6M#j109dpa0E_kpV9`DR zEb0ruqJ97@>JPx8TmTm30k9|^fJFlUfko+=p*12%dbxfuEh96y(_bg@cmp%T>X%wH zG}F7Lw^=ld>CK|yWV2{rvRSkr*(@4CHj74*&7%FuX3;3JSu~n#7RAU|GzNf01pq86 z1Yl7S0E>zNSTq)ZMdJWiR06=F@c=9;1z=Gb0E@~2SX2SPqDlZ3RROSQ0sxDu0a#Q6 zz@l0J7S#c;Xd(cMCIJGA24{wz6+zN>=v!w)%%Yq98@9}_`lS{fnCX4JhgozG)0;&H zlg*-fvRO2ZY!)?;&7$dKvuFm{ESgC+iyFyh(JV3+%?4o68~_&01z^!U02Unrz@qs8 zELs4-qJ;n~S_HtN#Q-ci6o5rb09e!nz@nu9ELsM@qU8WAIt+kCD*#xu5`aaA1F+}_ z02ZwR1Qt!r45jZW7G0npOgq3VdRo8Lcw}Z+{ZfmL$@KE~GK-F7db8*_vRSl-Y!)3) zHj7Rmn?)y*&7zaYX3@!Hv*;AES#&BHi%tVz(dhszIs<@3X9BS3EC3dr4Zxyv09bS` z0E^B8VA1&iEV=-IMHd3F=pq0XT@1jYO8{7ODFBPs0Z02ZwSVA16OELso1qALJ_ zMMr0bCW;{GS4;F(n?*n9pTxQ{Gpv3&9h@YuSLzjgT_>xbTy;BHmGb9kld}$$cS#~y z=gNt&P1fCVQI($crX0>XWOb3h3E45LL8R=Ob)9^GGAHX>xytIDHBi2M+b3&f569`7 z^@zOPl9%P};W&e`O8Yp@u&lH9cAODeZ}xSZ(OKPc9j7pBM!w^W%erBp zY1U0;jCp z2REw!n|*ILs{b8%A2+K1pLAb0s{bKyo*UKw(RGj;)&G)nm>bpqQ*neF)&CT4v>Uzb zQQ07FRR3G5ac)%qU!gKLs{b)el^fOn*`wBt>VM5J*^TPo)<4jV>K{j+=0^3eThDZ( z`saz~xKaK4vh&@j{(;cNZdCum<5D-Of1+=N8`ZzDw#tp_AIVznM)j{8t#PCJXKGGz zqxyG7PIIIBha%2$qxwz%^W3O@Rr?}0s^7I;>qhmzJ(y55cI_f2kg zqxyw`4Q^CF@qL#Y)sO6Mbffy2%Lm=4erWDdH>#g{+U!R4V=GU)QT^P(^KMk%IDXlU z>N|g1+^D{F^OhUcXYcR1QGIy2)s5=YuTR~mKEC+Ujq3g9H*QpKAhx?vy#oBnjp`|U zryJE{@Sm>J>aYyiv91nwx$Ld7kGKO{w-3ukm7lXh64wsRb)AlT%f8|c9JHsrBLADb z|I=~2>~HSCQe`8A==UT#u93aT9XLyw_~aa;Y?w^p4qUBFwz_kzGF^l_@FHc>-_Bd| z+vyXzopuMeJ5z@Bscr4yNDI&Ol(4^rWV!HhM_D*s`($(wx||~m)BXtccg5nWl#El) z{OHpoySfv+Hjhl5lGN3$PRTg^@;9zNs;gV$wMlBYzKhdki%m0xX|_E5DN`#iZR#pyCtR$Uh}H<-k0GxWuwGRp~G#$_+uFx6km)7Rhh)JlJn z%HPj9(CM;KCMlFj*0Gd(ZvXTo89`e1*v4z~{b|;pd(82&;F^?-*G~K4_*G7qIkKX< zoL5-R^?z*6l4(*huKw=i_hh}KX?ra>)b*D$v(1cUPM7Cpk_j?NSbqH;_<7rlPwLvF zWL$UOu~!}8FKG3vUtD&yzn~AE-uUJUr`tO+m9|c%@Y)<-_Uvqbg3X_Od5bhr7P8xr z)@}TS9MwBbHf8spL^u6SNeZQOzg{-G{-z{LNXl^>{Y?plQXDtK-MwA=)}eM?+SO%e zxaryQT5qRy>-_~ePAKYx+U?tVzt+QBm$aATlf9x(`vyBoQj*o%>2$^6=7 zw-_r;#!6^ix<#9JhRsrA%`M%l0-)8>@p%Rhl2IpU*<18?ok?0=lwX}{!sR*?%x+TR>?Ztcc5(`psjIcH%<6xQBwN8Btwu{Q z+sTQut@#gAXbX~@v;8*dxH`-ujh-O)TyQCp^R@36#rX@3Sm((}SXslnnWYN;b8A}^y=FV8Ma`Dnd3T8CUT(+dKDd9C8 zU&bDuyLidm1#_3qUEb*A&RMjeF}GoU=`ra86wu(4lb z!}PiR^7Hx+?58jHmzP_-lsk9fjQPuEHs&s9m@#MW!vEi!(X_HDu_tEF$&D?Uxoqyj zMFoqNH1>=4#fqg%{4NQ4q-x2cdD7=ixiyO$mK;*NY+-$^tjp}G`OBK>t7AjT2eX-E zW&b~%`~MpWmNzVI)NSE7rqRGbv-;0a%j#z~&T3dTe`)>Fm5Upj`p*%W9Wi0%+=WXe zh`8ck{ftEm7A#s=->`VDF!8#kpr~GYWk!L|g~?G4Kj-SQ0_1qE{P|NgKQz$wy!QX? z$8%Fcvt6%!s8fH>4bAQ!AIkAEL!EPk&B{@h<9R8$US^8SD<#iKN_Mln)>_iM9$JL^ zvA?`L!0RQkM^CSP_y5hv?PcW5KC+AzIx)*AwPlU8>gW7?uf2>ATA9$A-d<+cgz2W( z_{^tA%B&RTmFwxUbQ#^HMsmE=lu+9dUQ|M=j3hO$yA0*ZP}V+PYHu&v)uN7&o6^CH z`md+7_oBNA=`qr#&GoYVdE|OMrMB^BJh;EXsX=e01--Sq^_Cy|%S;C7(!4(Vc-cBx zFsEn_FIyL&E%6ua^=9EcTg)p$X zh7Q-c^|0kro7)q#>wla-jY*ZMN_1vAb^F}hZZbSlRw(L4_m;t28O-vc(%8E-{7^*x^ZL+>z3`^)63RZOnlpv zEjoXM=MM7Pri9Ksy1&;&CTS}|bxvvDPXK?#6{@rbP=xX2eG~~ zVHbb?%%_{{Wyt8E4t_gBDd}E!jXeV@4e_Ha%pWTu>w1Jz_V&7I4c0Q0;->5|+h0~* zKd(=(U6;i&gZjT~b067E-K51m{!z~^_SbIO=fPmxT(8@1 zeo779cl7w#|J$vf4T7DXfoGkF6^&s;G5% zp}eT3CN{RHzP7TmzO1rhtW#Yywmv^rFfKkuL2XT)OkYr0UR739D`VDGl-PL11>@?c zH;)*rF08Mptd)^#imGdi3gfSguacS8Rn*i~RaNQ>^;IR4i^}SYE33<6wZRf)RxL*# zQ&w3}T3;Bejn!Awm5(W^*7c~Y4#plhEOEgVmGw1sV`>VjOLVm2%DRd|f3%^)#`$%4 zi)L0A)l^kV3xhcgl5yw@ZF^C5tR|u5^jmq&*!nSb#l*{WLs2VSYivlqJ;@>c@y>u?tmBq#NEk@2C-eT;6SVetpb*!SMyrkBj zb9GUyaEiY&V_FDXT@#ZT`I}lg*u-X;l{E$RHMNz}r$wTpZNs2%TFfM2e~PcL*%K@C zmt0?2Ra6mw4VA}Kmy8`(TOmDKUsF_DtNSvGE-ol5^_x3zP_X9=_Lt}{JP+jWOg<8Y zZCeeq7xSh2;&Ur0sVnrPOtLkd&Csvl#%Kj6d z1$%=YRP^wphpvRZv#@AliCl$_sjCTkS@w;@<593Hsm#*Jx^ruPBurjCS$66A%85nQ z#buR~c3o(7#n|{^Q@o0m$44lsl7pFT;wm|uBpy%wRjLsa;s?nA@eUi4&^fw+nin1T zp76442WgC~x|g#JZ4A9Sm!?(LRm*_vW5s19 z1r8#k($lKzs+6UEQf%wzRNeX+wQ&I2jS|X zvLgRLtrHiulq%Tl+5xgATIEtwdcj)o+h1=(Na zygjzUKWFtf{!7&UJ`J2CK?(Bt)GjrtO!jkynRQ1YYnVl%p zeDrQUIusOC){m2;R(t~bro6H+XuVtz#9u5ZDl4lii&cyNV@qm8bv=u*A~?q3AZTNr zOzy8@i{p7+%^3eoUSBg#E?a^zlv1$^UIe5XfR!o@6ob_iL0+; z$cZ7|@WKIwcDAf8swfn96AsPs4P4+~7nw7xO-Wf<(b!m-?QL?lFO+@1`E=*Y9X~TA zY|{K;E%Y`o#>t!#F189;2icOl2vDMj!CekOi5C-c6!7<6zc1puLH^(tGh$z1WfIQo zEiCzuXSHTY$_gv}18V#vVjDE*e>uL`cFWJVla-vj<6X~=omXEtp|-woTyXwwd9ojp zFuon4%H<$bSM8sc{KH_ebV$v(grhN{mc^#%rQzPohT7kOuUdwV<)7sbO|wzxj;|XD^*IGEY#jL-kWrB+Xj3aK_TPix&24 zl81Ftn}p4j1ARREt2nfUfBv=)&MSJ|?r+GVipn}U-uT`ISJ)*B{S%`86Dw<67&j+= zvXYCo*qD;ClBvyC&3SUn)maQ|apY{?&2{&QjCIkm_EpjIw8_3RxVfvxD@88vTQ z*~bdxT3}2}ZkOx`s>_rs{h;|no6VPVe85`Xmgr4`ULuspT|sa$5v;c_-`uiAix%fQ zei`tuwzN1mx48Z-mpP58ocymT3d-bQFQ-pEKKXqU98l}^e63qAKW~7wJAR~<4G^DA zb1&(2TfKEvFom2F{Q=p$0gxkC!tUd5=jQvfT`s%r*w^yBFi7UqSg%h%8<#8z<|(&p z|DiF#QCaq6ZB=kFnlHDV{v<7LR`sOPeAOklsJ8#9kBe>p67O?F);hl!x+(p?GtoiKr3r^><4*UKNZ`F1jX zA3Vh765Ii@)Zk=LR9=;ETUVeD8WK-E+U~@=(s7gISw=yr9EXE7YO(vV8|mdud`kio zZ@K@6o4ewY;>wnHp3Pns#tQsrwL88G(U6*|l6t!{*X_ZbWGp^6IiE0Ny<)Ou$i=V?<;$HzynP8hP*q(y zu0-xFWm8nhSyP@>ut;AKZHQ`8B3H9hMTYu%d6%d8$w|Ikj>`i4`;quf2{X`RVxnSj zL@ACH%442g&gZ@ay411adi=tt`Od1)POm{2zQF~4SJ4J-+b)*? zu^N5k7JphJ`%rwQ@q4}482{m0{Dp*$tS+kkj~CwlF_xQhZAowo=eJ2Nhh!aSliZQY zonA>niGSj%iphD)A4|?Y!GP?aEk+NXM;45eJLRG>e-ybzZ6fZuagI2(wR0x zo1Z)mqX*@{VS{>mXRU0WlidE-=n=QsOC9AuUih+cTRh@xalswGfaeA_xWl3stV>(& znQSY+Kji8v=nuJ%OXv?hb?VJbea)njT6rbmJj@MWe)EHbd^s{ZO>^XWD}E!bw|D*m z;I7MmDPf0_EAZwX(g(c$Qy9ILktYxJV`C-3V?XgOJ{p}PcNTSJ&6h2z zJ6Ar57rya_KLdF9qc?(d6f@H+7iXS-?9(RdeHf!8-bcto)sg}^hR89!*6*kIST%CD zE6)n-c>w*E@J9Flt+#gz8>cUu?f0nO)6q!X6=P!pw}J=Hyuun5%dMK+)z%l6#cGY@DJU*z-Y)t2XqzS3Baz@7>2K)Zxx5Z0KHm240(UuXG+&Dr z7X6p2QQg2(ih|o;ZUtNJ`zkLtFnN1ZokqSsiDll2O)f4elk2s_CkoA1EHyO+_P$Sxe!y*9m8Yk6A+ad9 zC-BRF-~`&DNi-mS6pwdU!f{RSHyM#d1p7h!yz2K>;!{)KlmB#D4i3`sXKBpWe>aDN z0#G+=bzN|P)59^`4&Jg&TRxagxPg+VIQ}M-6ZyZDVkP8gC?_ksX|Q)`xbqs?VnU{n z>s67zP_9%GE@5~v{$3KN(%`Np&`p}}-6{QuGlY(C0#z~*v z>wJT|68dF~Jgb&>;{10>{Fn8vh!+zsB3eA3@tda)jdeipnS7uRK>dN>k*yALmz1CQ z?9=9|kKl`Cmq>gZ)$$&LYZ`y1(z)?=`TLces%m4^dJ!n@%LT`O+rJW?&{~W0gU72n z+u(kT^_6G;cFp2nPw@EPUw*A&bRrEs^&}l{6X=97~1FS)5@S} zEshkiD!CG$EVtGz1WssP&=0|m!TR90$|-LN@A}NrzZxozC0=SU1*2+967C%2TxY!- z9P#z#;1ZujRt4A1^29FQFTN*oJaFv!PV*ZcA}<>&zS$BDYd(JJq1he$Pp})$_&s~Ez6liDj^;nC0 z5M7$=5OuPaG*xF4+(Y<799V-#oAveF=rZGkt4yn6L zsgH2<)EIPE^V3m%&KMsx{(xHV+QwGvJ@PKS-Qqq`_44~e?`N0^O)H2MNXHk~`=@qC z7teQWw{0Ag)N>5>CI-aC9LOyqX&)f4+}N_?afW=Oj;VhFbZx> z{MqU=NM`1rekx+kA5+lHxl8-xyb^!&P`j8DOY=N}4K}H=y40>Z;}-_`azQEmz^HO4 z;ysX-_e#a`CN{Sj`r!&^Y(c@kIeql`er(BtoT3HO8)wdx_vUK(@UQ>KpAYr!_21tB z&`)=^k>7vhM?QhRs$HA5PH%V#-P0$;qdLPE9()bz;M1 zqz3&6vE#~jy&P{?zw-Wa7g6D)WQ5C8L#-m2$sOD*H#^kP?c{cLyU14}x+nE?`|Bs9 zclk*~$<7b|B)%Nd54tA&g!DtM2|pqIoNK~QNIv5#-(*PmNp|G>5zhAbWX+%L){#Q- zZ|4M)gdF)$cfwD|(eKMO|Ad^DpTiG1@|~W9pO7Qprc3w<`AcsGAxA#(pYS7J`b$XK zo-Fycp8p|o|MTgYvOWV7#z>dp*e2}d7qxiLx zR(Y|9R_WG0#?>z!Z-~{AR>xSavRY?VJ}T{xuisA4=?=AewAD3M&$4=j)jO@;XY~=Q zPgs4<>MK^|%W(eu-?#dSRr#`;&%d|&vsL*ro6q%I0@^P9Ys*^Y%W8gYZ&m-Qj`H2C z?rwD-tNB)kS{-S%z-o!rN~?8N53t%`b+*+7R-3G@w0gAF-)Op_pE+mb(_^6tnRcb2Q9y!Qp7L6AFXz<+Qn*5t9x0^ zvpUr3{#J{u`rjat_S9I`uZ`&Z8?5S=z%(ziy4>oKR@YcP)#^D`FSfeg>UCCcwR*SJ z2d!?h`mEJgtiEOSL#v-#{nqMFR{yY?B!@_CZ>rUFtJzk&TixAiU#kPH?rSw>b)3~o zs}rprWOb(1L#!^by3*=ut0!7L!|M4~*IK>G>Wx-!x4O~lBUYcZ`hwLhR^PSyvDL4v zZnyfY)xWKJa%#|iYGbv%)y`IXSnXpq*Xj_fBdr!%Ewx&0b&Az#R%csXXmy#@RaTF) zdWzMvtzKmHa;w)`y~XNXRv)nXxYcK@zHIePs~=eX%<4B*f3*6$Rad?$qWu%Gnr1a> zwVT!6R{L2UVs(_&aaJc-ooaQ4)%jMJSv|_?iB`|Dda>0jt=?qyE~^h&ebVYnR^PJv zk=1Qhf3*6iRZmV>y1wnKW?Rj%x|h`fR`;`7XjQ*2tJ6=kT5olZ)kCcwZuK~;r&&GU z>N=~}S>0guKC6#gea`9@tM6O=-0JsMcUqPIp~-JwE2|x>_Od!u&ehuf0;^Nx(noWn z)g$B_t@%W&m&v7%<{PX&A}4sw&sqIQt_d`MYjqF#LbB$8R_DtXAT{g%La6l)`SP*W zN38CYFX(BOZwUBx|J{OGYE{2Vt*@VL_1RuQe$#6D9zpJAb)sBg==d|NuH8GxH(33+ zZ;-#Y+D9%#bo{|q7v=}~2&;Du4Dw@Ee;*v=uw1z4bfbp_wcP3n^6gFK=URPUz7($c zZL681g1np6$*~|eT3uHV}>M8Sse4*8s7Y6x#tIRy$u6zM%Xprx=`rYF} z{=@2^CxRTadiYa8KGEu<&jk4et0~V1xxLl07lS;->Nzh5`Esjoy&B}ttag7r$op8G z`DTz0wR+>*LB7}OcKLf9y1su|9r8ht3#_i%8sw9$KK^l#U$PqcEXY|_E4~Qw0anlZ zD#%w@edp^Se_=J}yCCJJ?gh0pK5ip++gYY zy<)Z1-$Bl{S|!gC^!0WIC9T4MD|`Flb7`fXP4 z*XlXWGnTh#Z6$w;#OnLTzqI^~)gO%iY1!!)Oy_Bp`KMd%V6~I+-j@4V?Pq+L1dZyL2R&TI+kJU|9U)Cz?n=B8lv<|g8&+6q?U$q*Mzt^GT4bv*? zHNt9<)e@`KRwr7O%Q1gC=}Nz5Sk1E9)oPB_5mrZA9c#7JYPHpgR;O8=Y4s4Ri>w}R z^<=AOSv}9H9De_h&7VdHBN( z)2A}*{z|sXu+?H&uQ|%dh^-X>=XAymsW4LjT%<|EtTJBEPgj2A$2)(0bYb z_+h9{K;rz?%ltaZ4yp4~uXLU|zef3G8X0tY4RoDH5&(mT?K0lSgIwoeUQBpRw@Bi0 zH!hdI?jqyqa+R~(6B4G8L1*+3*U8ZV`(f6{N=}?#WQF{JIAJ=!*7D2zE|y`YkwIsg z%umPThu6**kT}1N3G>q@;LPtP8D<)t$6}e^RP8YP;kD}|C(f^r%uh$t_Q@_8pPwFU zbQ<+Rf1cgnb-MKqhV@^4O@AM^%6MN)cb)OV_+h-41n4k7gJuN2kaa!u=Q;UJY+qi& z`nH$XSl{<#SX5dp#s8Tv^V^pom1SvVU(uJZm+__v%$DIy`PKPpzw0vDhh)%+h<^v^ zfc-E(Jx3&tH(J{F4I@cqy!hV?ncII+Zca{4{?NQ3!}10U8!%Lc^YZc&{v9%8P)^S9 z;R6Oqk)LU;jxH)I4*sM~Fk@Gq$TMFhoAm*)+>QtPdLO5g97+3qwX^c>(${uAI3a8M zZriQ zlQF^n_iX>)SM}c>n`FEz$~NuX`skLO$@$Jcf4oz<-EC93eRb=~pE`D~{AqP+<#s0$ znse#+%{!g^OG_^;*}U_cyi3Q)zmHy0x_Rf;4V!m%UH{LofBz%(tj#-LKIW6T2P8Q^ zc*mYsdY(US=m)PL^z(}L=g2f$H-vu4EjUZ&wd*uix zhnF5P{)m!Qe!KOx$vtP5Etd8t_s}KnI=80MrtwQlmbRGNlF}vPn@XC->C~flOkcdD zWJzg_w$+ujPT#z9bG*Gr%+a-v|e*AcK_T``O~8ZPA#2Ua=`clq&;09)#Xnu9VC4ljMr;g>p7R$c+##x zvh7BX+i`bO-|>&h*pJEfeQf8;&SQz~n^#)mw{TuBzZHM@OCBT39CnCs_wk*Z({<^a zejGjfQulYi1*1wwj~hKcCQA)kAZCOhI`P0-T`LoLGUh(@y zs|Fpi|GRfNtIr$r!$Xfg_`uck#_s>Yw*&L<$=iI@aW9?FXGPj^v-ke~=3%p@{w+J* z=zCAxp5#R$PR*xhy!=eK->r=cQx_g}%#O#rNUBrR<}Bxl%fs`oy!qngg_o9R_L+WA z_G%}2wHyUjUtIF?@vPa8b9CR)o{jA}AxE}DY}_wvdR0mvuX^;&*gox+hf{{+3n|C8f?+3ZNm?F}qLkLtpMZvv27>|8f7?-8W&6|GIzW$iCt{mNP!5q=&x;=n{4Rs@xuKqx)Ca z(r)9sm2{8qUlpHAUt|T#>{Qx$eCLub!JgBrwJiU^{B!5Nm;C3J?D9Lm$S%zu-?5~l zy&AGt-8M{CD+tqhI^;FKA zv**A0%&G*ROiK!}A+9Zam_^_osK6{ZOWEY*!=Bv-82;oiOEvOb(D z!=1wGqfduYx3kZ*$ij7krL_gv)#xXY09~7svz zBWFvOR3t~os=AzC4x;(j+`!DPDzf);}>UYa%8bwXC9CoxkJ){$&rQ9FB_60FG?dic#)%J zjk3JRlhTM4UPS*Bzm;C(WSQCFUgS=J?|G3OGSBzD$Wrm|1Nq}!GV2e$$Z~1RRxk3q ztiwlM>==NvON|{bEGtz9GGs%v z(t#6XptTM>C*!oyfqv50^2aKj)Rl4&YNrD+Q6NnRdP+0Wbzqr{lc590%I4K`QtF%1 zW9@Zdf{+e6@V0E^EFGwjMQE#2SI8!iM_*2AlQcd_2ZqQZ^dnoTO|lmy>wriuYas() z%0^Dnf!}4JI#%jBu}%I`u#K z&VeaYq}$piD{q(V?ct4-?UObp&++!O{~c#HiTRG#$6|Mh0~~KJi`^s+biBPSc9l5D z@%FLUMdDz`>ua&I#37E?&tfNuLmjWb#f}n(IbN>CY>C4iFVA9BV!kvh-*T2_Y1aVD z9W+bB23l^fSz0#8a;9c!+F;8Wnx$<+ET?Oh#tpTcrde7y%yK);(!Al8+iI5f?Q6M> z9V>wx~ zw6DOje41{|0BK*LEMv%I%NR1nGKNgGj3EbD#*hOoW5_|4G2~#&7*cN;L#A2AkOs>bGTkzU%&?3h zGc99Cqh$=4Wf?vmEMv&&mNDcE%NTN|WehpXa$v~9&{eYiGwzcsA8%1$NH@9s@y-sb zIcmuH-c@q?^$oeeCN)DYv}lH0WYG+{*rFM7iA6KyQj2EDT8n1LWfsklbr#K#%PnHa zddnDcg=Gx6(lUlzWf?=Rwu~XySjLcREn~=amNDdd%NTNlWemB|GKSn_8AEQij3KvJ z#*kYrW5{imF=T^f47uGhhTLHpL+-SUA$M8Ekh?7hhMXIELbiX#yK<@HofjA~RxXXa zd%|jt8gjq)gj_WFhCE=CnjsHbG(#S;Xofs&(F}RSq8ak2MKk0vi)P5<7R``N7R`{& z7BS=r%NX*cWej=BGKM^D8AG12j3Lij#*pVMW61NCG2{iy81kZJ40*{ihP-SULte3r zA+K7-kk>3@$QH{O^15XVdBZY>ylELj-m;7#Z(GKYcPs~nYz%!N+dt!7xq$cX3k-Qd zu2a2t!)lHi@}c*I+&B1!Y_&UiZknNT+C- zUo2zDua+@nr)3QJ%`%4kZW%-Vu#6#pTE>vSEMv&umNDcX%Yh;9hxB_98TE2g%Tvi+ zB+F%aD{^Paa#`M*+)1)rmbW2ylq{F!ZOPe^<+8jTIVxH2YtjJnB^Lk2CLPd0fiy7# z&|ZPGF%yufKpNQ|kfA_Y*#VHQK$@8aNK+u~i~`yzkcMUh+A5Hib_BE$pm#W(0Id~B zUv>txQXnnu0!URLE$s@3D3F$R1B4YwOS=P76i7>V19%Fgr8$6P1=7+UfRF-dX-`0s z0KM1g1#lHeOM3%EkgQ}c$qiMBAeq!JhEAoPd1ANkj#c|7=T6f04$mY zz@i2K7EK3W(F_0<%>-akBLItL0kCK`0E^}TuxKs-i{=5a=nw!F%?Du70ss~*1Oyh9 zxuN$&kj(Y+w9YFxi_VZs9B+{uR=?DuCfEB*o<;f=EoFMMXc^foT23~L4kMdIE68Ti zO0rpWIN2;Zf@~J8BAZ1=lCkJ002Un$z@pUvEII~&MaKfL=r{lttpQ-s@c=A30f0p( z0L02ZALz@k$CSad1?i%tVz(dhszIs<@3X9BS3EC3dr4Zxyv09bS`Ah76AH`G&3 zW|{iMP;ZG@G*z#n&vV1-ms)g@>lMfixo^?MOm7xlLN<#oC7VTS$!5`IWV2`;*(|!8 zY!?M>(KP@px)y*%*8#BTdH@#P0KlRf0a$bs0E=!0V9_lA zEV>ndMYjR4XafL?ZU(*P`b27pD+0g02VzDz@irbSo9(Qi(Ud?(aQiVdIf+*uL7{>H2@ZE z0btSV04#a~fJJWtu;?uS7QGF?qIUpT^ezC4-UDFK`+&fr2i(xDB1q;vD$avk7s(r5 z-Un`2{ZflQcDGkQ0a&yXfJMInu;_OH z7X1OhqCWvx^cMh&{sv&tKL9LplHzyy!9AJ_z@j8TV9{1L^pgmZ*;OAFeq15U{MYLi+TXC zs3!o6dI7MgHvo%v2XHLf1As+)0s@P?q|m-1NapGChPaoK6x`|Sr=`6c{kEQGc>oluI^?^2laUKG`f9KsJj8lFgz)WV2{6*(@4D#-gDBEE)#DqTv86 z+82OD`vI_M1OSUh0zNSTq)ZMdJWi zR06=F@c=9;1z=GbAh2lfq|j;+B(s;i)9LMF7JaN1l_!POFSTewl6S@4W>GcMn?*Hb zv#6GA7S)l>qKRa)XcE~hnoKr}rjX5|sbsV005TRG2*9F)09bS|0E_AYSTqfQMGXKf znhwCC82~Jr3BaO802a*xV9{&<7R>=*(Odu)%>!W3Apk6z55S@Y04!Pvz@kL}ELse} zqC)|JMU_dRCq<3bI+Wl57?oPBx2< zAe%+2$Y#-zWV7ffvRQOA*(_R3#-d{YSad7^i;e?e(Ha029S^{w698CrA^?j{0$|a} z04zEMfJLVQu;?@Z7M%{jqB8(kbS40c&H`Z3*#Im$2Y^NA0j02ZAOz@iHPfkjJ` zLT&nqMPKPt$7N>GiSnU1@4}?8`lS|Kn&kD%HH+3Vy;*b_*(_Q|Hj6GNn?>u%X3-U7 zv*=2)S#%ZIEV`O(7F|QeqH6(IbR7VTt_NVz4FD{<5r9QE0kG(102bW>z@l3LSacfz zi#7nT=ym`W-2uR&I{{d97XXXy24K-W04%x}fJGYtSacr%i|z+t(F1_MqKlJ4)gnmd zWcg%OOR`z?71=D>MmCGSCYwdykjPHV9_4{Ecz3G zMSlUX=x+cP{R6-vCuFznSmXk*C<%Z?ApjO71F*;g1Qvag6#75}$y^}saCo1ZMeXzv zWJ)NkeyK&RLf$`v&7#&!Zx*#7n?-HOW>Gt`S(HXLi_*zvQ3ly8$|Rdb?a5|Q2Qn6A z0k9|vz@lsb7Ig$*Q6~Tvbp~Kj7XTJ@1z=G(02XxzV9{;>EXo03Q4atX^#ov1F8~(x z24KEXpUFMFYrY(Ll0UG>B{#4JMmKL&#>)P_kJxjBFMSCu7mR04&-MfJGw! zSTquVMf(G=XcPd8Mgy=Y2Ed{*04yp1U{N6ei;4hPR1CnPu>dR@2f(5d02Yl0U{NUm zi^>34R1UzR3IG;W0s@Qrg+lX0kj!E|7WFra^p7rjRiUu@r54qOyi@lzi|Ux(ESg9* zizboHqRC{lXbRaZno2f{4j`LF2a?UAgUDvl!DK9|2Vl`O02Va>uxL5}i)H|@XeI!Q z8Ua`|3xGwl0a!E#fJJiwSTqlSMTY>eXg&ao767nlApnaO0kCK>0E-RV7XYy6LI4(B1i+$;0f9w_ zg+jlGAemkDf_jBnbiG=1Nhqv-sYUBTUiK)n=yIkvi`J9PqASQ|(UoMg=qj>VbT!#5 zx`u2PT}w8Lt|Oa8*ORg61^^b_2*9G709bT00E=z`V9~7rEV>PVMH>KEbUOfx?f_uX zod7Jl3xGv;1F+~G02bW~z@m)+EV>VXMfU@+=m7v0JqW;}hX7dgFd(pKZ74KC1j*c~ z@5Wwc7M&#T!g`N{!s?e=v?=5r6f=u9Grd{#1lcTll57?|MK+6`CYwdikj2mh$OT|g5&(-r04z!dV37yFq7(oYg#lO;0R$F(9tu4zf@E&doBJ=!B7HC4OHB@| zUusd?WbdmYv#1@@n?-44vnZWx7G;plqD-<`)She>bs(EXS!A;)N;ZqK$yn48fJL1E zSkxJSMO^?`)D?h5-2hnB9e_o<0k9|sfJHq3Skx1MMZEx6)Ej_By92Oj4*(YJ3BaO0 z04&-IfJJ))uxK9u7WD;SQ9nRnQS0PTyJE3un|`^!O>%Ij|D=8|wSRJ0{Zfkt$j$yZ zvuGgGn?-}jX3=1>Su})f77ZnvMZ?Hu(QvX^v@h8#+K+4&jUZ#uNB|b?55S^P04y2} zz@iuci^c%3r~rUPg#aun0$@=w0E@-~uxK0ri%I}kG#-FOr2s4{17J}(0E;RBSX2qX zqACCuO#om~H6XAkFF8~zf@FTGpS#XCi>fu$$Y0+Pzto~h$=RO60l=b}04!<*V9_i97R?4=(HsC4 z%>`i5JOCCQ0>GmA04!Pnz@mi!ELsG>qQw9#Iuw9KO8{8Z1i+%D04!Ptz@p^v?|$qpv){flIhK&qsV5_(PXn|HQ6jWhHMrc zOE!y+Bb!BQ$Y#;;WV7f5G8UZ(z@n1?SadP~i%tPx(Ww9|It_qDrvtF)3;-6L3BaPW z09bT30E^B6V9~h%EIJQ>Mdt&s=mG#1T?oLUivU=3F#wA$0btRk04!Py2rN20IkZ&- z$*gfjoFmMl3Vj55S#ntYQj4xg_S{Od=t`zHi>@M@MOTx}qHD-z(Y0i==sL1lbUoQD zx`AvK-AFczZX#pR%>XRA1%O4j0d02XZkVA1UWEV=`LMRx+Q=q>;j-3`E^djME; zF93@+0l02bX3z@i5LSo9zOiyi`C(Zc{NdIW$)j{>mhF+gC^<;kHvM3BsyG!bXL zSu{&OG5dIOSp8Cqo=o<}PB4p}VtTXaX|h@L4B0GtmTVS1M>dO|C!0ktkjGkA0a)}I0E<2c1Qu;h4$T)qGW+XE>o}7X1mpqQ3xG^fv&D{sCZ-d@cJ@>EL7+i(CK}B>}J~ z1i+$X02X-wEJ^`jQ5b+l5dapY0D8u&5URi+TgFXm?E%1|JpowM2Y^L;0kCLq02b{7 zz@okYEb0fqqW%CZ$^~Fi9w4x&ofq0Ef@EHxA52U0f;;_Q`tjL(FRXs4MT0%B(`2(~ z2-BNIL&;{*FtS-RoNN~DOE!!4Bb!Ad$Y#+o%$?}zaZ;)B^h(0`;=!MlUwP>p6)lW5x4q$q-=s>brbP(Ar zI+$!0)sxMlX=Jmgfov8{C!0kx$Y#+@G8Q!guxJ(li)I6`Xbu32<^r&29sr9D0btR5 z02VC(V9`PV7A*o`(P97=9SXprB>*gH0$|Zn02VC+V9{~_799q_q7?uvS_#0S!vTRs zlfBRy5hU{z{oM5wv*=3w>s3d1Vf9NbI@dLpFWV7gGG8UZzz@k$DSaccyi%th%(HQ_NIun3JX92M2YycLW1Hhtl z0a$b%0E^BCV9^BtEV>YYMHd0E=wbjCT>`+OO95E47Jx;U0kCKt0E;dM1Qs3Xg`O2b zGMDP-u8%T{iZdjv_rmIzT6DGNeSNT5bPdy+Mc0zeqU*?J(e-4r=mxS`bR*d;x`}KS z-Ap!%ZXugRx012wHUJiF0ASJW04%x#fJJu#u;?xT7TpcNqI&>XbT0slHUhBdJ^&Wo z55S@a09f=O0E-?1V9~<>EP4chMUMio=rI5mJr2O4O#m#~3_`^GfUAA%u@6tvlRWrEJZ&vOVKaPQuHgc6zyR~(QgD4{Z2s99|RQrNkGwG1Qh*E zK+!)06gdgnZAVdnfT9)z6a@(=YDqwmOF&Tq0YxDKiV_JZN+O^rnSi1c0*X=zC`u!s zD4pOd+T{i}8zA8Wt)g$FsIC2dv{nfr>&q%?o#5VEFGX$GUW(c>OHn&!DT**lQ5Lfl zwP%*14$M;2ky(m5F-uWrW)yWHpr|VWMcoJ}>P|pW4+4sM5>V8OfTG?66!jsXXdeQK z`VvsokAR|m2`Ji+fTI2c6b&GtXdnSa*#r~~BA_UTfTCOiiUt#WMVSe~j|`CT>~025 zIKki3ztTRV4M_-DUslnG1UEQKibk@%6z$I}MF%iT(I{pq8qF+42Qo|1LCjJ#hFOa8 zn58J68ASyI6crLsR75~gF#$zm2`CyzKv4++MF$g5G@gK>QUZ#~2q-Eips0d?qDlga zCJ<0mMLY1fz2D22+WJb{}0*Yo6P&9{t zqN4~XnoB^@JOYXu2q>CQK+ysMijF3rXdwYbjRX`eBA{q70Yys)C_09KqNM~BEhC_4 zIRQn-5>T{)fTEQIU(q26!3F~)oNixTA1X!1+aFmwE+J%nSw$x$xa;Oh(JHo=qSee& zbTYFPox&_dr!q^?Y0Oe|Ij@}2hk&9D z1QeZ1K+#45iq0dT=zIc-HW5&C0Rcr95>Rvz0Y#e$D7u({qAdgzT|z+7RsxDHC7|ds zg0JX=gy0SXB%IXKz&TNhUbC;Rw{2w7iN(K88d$D^g_S+?iMQ;#L^d{uS&F(aOHo&5DeA_IqV5C~^&p_ACjmvh2q@}J zKv5q8iuNI(s4oFU{Rk-9mw=-E2q@}LK+ymKiUtx;luba$t*?Fn5AesvlP`cOVJEwDVoVFMYEWt zXg0GH&0$8-Q3MptC7@^?0Ywc26wN1~XaNC5M-x!Akbt5_0*V$9P_&qUq9p_r9Ya9T zQUZ#W5m2<8fTCjwC|W^4(Mke}jw7Jxcmj$}Aoz+74+SS1AmN|vo_fP;>zSMHdoKbP)kXn+Yhon1G@!1QcCDK+#qL ziY_If=rRI|wh>TtIRQmi5PU_eLcuKtNO-P&i)ghJ&9(1cUl|HnUslmIA@}~{r080< zm!j*KrRaKQDY}7Kif&|u?NT(tzLEWOC}e$EMbC#^_e3drf$gQ}MP?~_iCKzX zW|pE?n5F1dW+{4&S&Cj~mZCS9rRYs&6um`2(c1(Ry+c6Jy95-yM?lg01QdNhK+%T; z6n#WM(Z>W7eL_IdrvwyzMnKW$1QdNiK+%^36n#ZN(bohN?INJ)8v=^HC7|d#g0JY= zP;g%ZB)qA$f%BXc&9^_w|9vQAeOX06h1~J0r08e1m!e;orRY~?DcZvIZ3J_4#f`FnR0YxndC~^rXN+6)f{3rGP&*q~j zk$|Ek0*aCeC`uuqD3ySsGy;m!2`FksKv4z(MVSN?g$XEXO+Zl_g0JX@P;h|(5c}ibotUMlGqV(RVV0t<%u>{iS&F(dOHmJI zDeB3LqFw|P^(LUG4*^B{5Kz>YfTDf`6zxku(S8IJ^(UZc00Bh<2`I`YplA>QML7f% z^!M}^*xw}DKQUx| zSw#mXy04!qMF+9H6pdk)qC93P%4e3M0%j>HWR{{LW+^IWmZGuDQZ$YkMI{6j9ZW#c zcmj$_2`DNfps1XHq6z|vDhVi>KtNFy0Y%jW6x9$=R7*h7L;{K?5l}RlfTAe`6ip?d z=nw*m4ke)IFanAWC-{m+B?kXAK*B$^HE>2t(NT7YCWfppt7uxH+j)%?O=o*4s%Ms> z8O%~NlUa&pF-y^GW+|G(EJa5#OVM0rDVoQOq6Pwr<`Yn~fPkW-2`E}fKv5$BMT-b1 zT1-IE5(0{jA)sg}0Y%FQC|XWH(Xj*+tstOiB>_dp5m0nI0YxVeP;?>zMJEwZw2I&> zs!I&!8zABB9Soc!r6|?Dd9*q)WPMphrzN`6)=JUoY%fJ?n5F0pW+__BEJbHBOVL@( zQnZd)iq2-1qV>#DbPh9$HV{yBE&)Xw2`D;`fTHsWDB46o(FFt)T}VLDMFbRWCZOnI z0*bZ}P;?0aMOz6dx|D#T%LpjiMnKW!1QcCCK+%;16kSC?(bWWB(J6_+(+rUCNnH$_ zQ>Cb#{U@=uCx)yqtLXYfcl%jVbOYN<(T&VfbQ7}_-OMaSw=hf5t;|xigIS7hW0s=Z znWg9sW)$5?K+#py){gik>2%=xG9qo*|&=$4tXvy zWPMphFD1I)oh?N#v%M6(!YoCvGE32G%u@6^vlP9-EJbfJOVL}*QuH>n6urZYqIU@> zdXIpj_X#NafPkV82`KuAfTE8HDEfqeqE87Z`iy|0&j~2{f`Fng2`KuCfTFJnDB49p z(KiGXeM>;mcLWrDPe9Rb0*Zbh_=;Xg47OQs6m98b;JheBx%Q3h9}`2?msRv@qC0eh z6zySqDf*3BihgI7qCc3W=uc)T`iohL{$`ebim7b&{eD#}UcuQYy_uz`4>OAPA)u%)0Y&`?DB72RqWuUc>Q6w?00N2z5>S*) zK+zxqigE}j$|ay^FabqF2q+p#K+!M)iiQ(VG=hMlkpvX&Pe9QD1Qd-T_=-9t1-BX? z;RW{X>W)eNp8oZjW*D6mvc9aMyd?L*^Q9=C?WL%IS&9morKpHmii(+~Xe_f7jboOg z5@snnm|2R(Goz@KfTA)2ipmKnsvw}Kl7ONK1Qb;fP*hDoQ4Ik_wFDGRB%o*#0Y#Gu zD4Ie*(NqG84k4iEPy&h$BcSMT0*ayp6dgf8Q60fobWl?8GXo^t-9G$`k)o;Qd+w1* zA?wR3nvvv&E|j8~Y%fK#n5AeovlPu?mZGDWrD!g*6wPCnq6TIun$Ijn3z$)KGyz2m z2`FkLplA^RMT-e2T0%h4F$5GXC7@^-0Y%FRC_0vaq7?)btt6o6I0A}}C!pvA0*X!~ zpy(t5idGR&w3>jTlL;s~h2Sfio)qkFfP{axyJhuKlx`o3PE86~Usll>Np9I@DO$_+ zQgkM>6rIH^MeCTQ=xk;wTF)#+=P*mr24*QbmsyH7GNb4`0*cNjplA~TMHdiIbRhvn z7ZFgjnSi2;2`Jh^K+z=x6m2D-=u!fTE+e358v#X^6Hs&o0Yz65P;?amMOPD0w4H#W zYX~U1mf$NoJt?@*0101W|NWvhQZ&harhi>h$ojI1Zc1`DY>}dy*nWbn4 zvlQLNEJe37OVJ(7QgkP?6y3!vMRzl!=pF)!b`nr@F9AjO5m0nL0YwiGQ1l=HMGp~B z^e_QMj}TDwC;>%}5m59v0Yy&`Q1m1LMNbh>^fUoQ&k#`bECEH&5m59z0Yxtmd_^}T z1@AOK!gcoNu5Xm0o2;T2lS0;)RrG3-`{q_DdX4R+=yhf(dV^Vt-ei`dx0t2qZDuKY zhgpi=WtO7%n5F1_W)yuuK+%T;6n#WM(Z>W7eL_IdrvwyzMnKW$1QdNiK+%^36n#ZN z(bohN?INJ)8v=^HC7|d#0*byTplCM%ML!Tw^dkX9KM_#$Gr?E%a#HYb10?)`{m|nT zDH>&8B>j>Uvc9aM-;>;~+ob3ZwwIzmnWgA2W-0ocS&IH)mLexvd+t&cV3wj5%u*C& zmZFx-C~^rXN+6&pL_kp@0Yym!6eSZ-ltMsJDgi}l1QewcP}GWmq6`9xG6^UO6HwHe zfTA`86tyLws2u@C5dw;`2q{k8AbaNP_!QbMg0jV z8bCnNKmv-g2`CywKv50>MY#kN4JM#y2mwVy2`CyyK+$jlibfDnG?IX#{Rt>KfPkV= z1Qd-Xpy)sXiVh<9iaI9;*BBt-qb!^*$^M>xy8TRlOmfKjvWg0m-D|Isq9V4JqGDz# z8p|w2KtNFy0Y%jW6x9$=R7*h7 zL;{K?5l}RlfTAe`6ip?d=nw*m4ke)IFanAWC!i=wK+zEd6x9(>bR+>q(+DVV6rD&w(Mbdpts zqv!$xiY_Fe=pq7&HWN^EF#$ze2q?OQfTFDg6kSR{(Pab_Z6l!QasrC3AfV_<0*bC8 zpy+A>inbF_bPWMT*Ah^49RWqx6Hs&m!B@04Ie4f655z&TTjj<+w8ZcGkYUslnr z$?nPi(bEJJJwrgzvjh}9M?lf@ z1QfkMK+%f?6um@1(aQv1(ap)h%M6h43wG!J7AbnwDtaY3WPMphZzQ`9-y}tEvb_|& z#Vkc{GfUAs%u@6&vlP9@EJg1#OVJ0+QuHCS6n(^uqK^qE`hm>Xs=7rvGylJeoGEnUslmy$!^lEQuH_5OVK~fQsks)&s~ZF z%u>{XS&D+pQq+=Jid<$XN??|v5HpGr2`EY;peUJuq7(v(QVA$ZBcLdqfTC6e6lD-l zlu1BQn1G_z1QfL)pr|bYMePVEiV#qgMLpcwJnE7Xvc9aM9w~0cZBo>e?WL#}vlR7amZCn)QnU}V6!m46qJGR$v@f$1 z?Z+%d{h3iTfPkWb1QcZxP&9~uq8tK>atSCJOhC~P0*ZzbP&AByqTvJ-jUb?CBmqVH z6Hs&j0Y#$-C>l*b(SZaM9YjFU7y^p&2q?-Y_=>uv1Q!_~;XAq+INekHJ^f5esvsp~ zeOX0gQ{0VrNYOa9m!cA8DLR;0ipDcbQ7N+&l`%_EIkOa1FiTM-vlLBWMo|?3Mb!ip z)eulrOF+>?0*WRPP&AoCPKv6vbMKcH}nn~~#6{Q64HbBCw?WeKDQj}nSA!Jrc$ojI1=BBuB-z7!!*j|bn zn5AewvlK00mZGDXrD!3u6g4tS(IRFkTFfj(OPEn~3;{(;2`E}dK+$pnijF0qXaxa9 zD+wq%j)0=$2`D;&fT9x#C_0INqE!SGttO!8WCDs#A)x3~0*X!}py+f0iq;TNbOr%M zYYD!hIVnNsZlmZs`y19rNl}0MZ>gP`60*LmqV*|m_nlI74%_cO5m0nB0Y%#hD7uD#qH75#x{iRN>j@~jfq zoN9mW`fMrMW?vWGk`l7MtfJdf+?n@D(H(3rMRzhw(Ot|^bT_jU-NP(JJDH{EUS=t} zk6DWDXO^M|m{If~0YwiHQ1mbXMUN0r^e6#Ej}cJxH~~dZ5K#0a0Yy&{Q1mnbMb8jW z^eh2I&k<1cJOM>75K#0Y0YxtnQ1mhZMXwN0^eO>GuMvDjJ5qvc4Uq6J_Sa!=lcG=T z1Jmm%A?wR3dOO9v{sAd^hwY{4U1lkIk6DV|XO^N5n5F1LW-0oJS&BYpmZDFXrRY;; z6n#cO(dPsdeL+Ccmjo1jML^Nl1QhKepy(R{ioPYF=sN<6z9*n)HvvUI5K#0Z0YyI% zQ1mkaMZXYG^eX{Hdk84{jew%x2`Ku5;46AFCHRs75`N0QUHz669n-}Of2M@2FRRE& zb$@(FiUO(Hlb50v%u*C&mZFx-QsgpAQ3A6Rg_xx%ky(n8n58J08AT}s6r~bSltw^N zIsrwk2q?-RpeU1oqA&qPtqCY7lAfTut0Y#k%DC$f= zQ5OP=x)M;-jo>T#J0+O)uu-(cz7+aLiuSRjx~GP$FRQ3`syp&gDeA-aQnU}V6!m46 zqJGR$v@f$1?Z+%d{h6g`0J9VgWR{|AW)uw~peTocqFe%s1`|*;gn*)<1QZP;plCP& zMI#6(8c9IW{sa^qKtRzb0*XcxP;?*xMF$a3G=_kpJOYaH2`DNcps0|5q9TH?sAp>M za04W~+5XEjy;A)>{bTG$v&E?)>&q%SIMqG=aVZ+l_EJ>JEJbC^QdG_?MHS3aRLLww z6PTr_idl-PnWd7=x_pxq68Ej zK|oO*0Yyg=P&AEzqUi(_)e}%OgMgx$1Qg98plCJ$MRN$gqH(Fg%MFn5#vTSvi4=Wd z{{fMsQbX34RWv`V6rD&w(Mbdptsjo)0+P-;oc52A_vWm`4 zbyJ>^qK#}XMdvX~(fQ0$w24`YE?}0T3z?TtIRQmi5Kwd_0Yz64P;@l`McWA|x`u$FYY8a2j)0=;2`IXOfT9}-D7uM& zqMHdQx`lwETL~!ILGTrwlNuakfQ0Y1KX<)Bite!=&EA$8vc9aMyHec=&q>kUY%fLk zFiX)+W+}RtS&HssmZJNarRV`>DSD7uiXLK?qKBDL^aue(j}lPy7y(6(6HxR70Yy&| zQ1lc5MNbn@^b7$-&k|7d905ho6HxR50YxtoQ1lW3MK2Rj^a=q*uM$x78UaPG6HxR9 z0Yz^Td_{Mp2A3Eh;qLaI3As~>K2A2nTd5)I%PM*=)jj_ODSDsnrRW1@Df*CEiauhN zqK}!S=o4ls`jlCUK4X@m&zYs@3uY93NkGw81QdNuK+!G&ioPMB=vxAcz9XRMdjg7f z6HxR60YyI&Q1lZ4ML!cz^a}w+zYM+y*JIJX%u=);vlR7bmZAa7QZ$fRin5udXb`g$%ko9F1m8H3}UzehC zwwIy`W+|#U(xuq;8_Mp_#yjq*QHX_&b~-$NDEnCR?)&V_r^D+sFCfZXc4m%EoPRYCCpNE z46_t1WtO64%u=+RS&EKjmZBBRC|XHC(QyP69Zx{f2?P|KNI=m^1Qe|zplCG#MJE$b zbP54QrxH+f8UaP86Hv56`h~v{`|HSZDM;Vx`0`VE@YOXi_cO5m0nB0Y%#hD7uD#qH75#x{iRN>j@~j zfq$8`m&04rnv{aCq?(Ny%gQYEJgP-OVI<&QuH9R6g|W&MGrGe(Id=K^eD3wJ;scp z#|bEUf`FnY2`GAsfTE`fD0+r~qGt&xdX9ji=Lsl!fq6@8fI zp7?f}MnKW;1Qh*2K+&HB6#Yd& z(cc6V{X;;Jldc_e6a@&rqW9B+R~jJU3+xZcejr7??8hN3(nHplRg{qKKK_vuh1gz- z5}BnaiCK!0nWZR&S&CAbr6`SAiqe^-s1>smWiX>ClYpWy0Y$9|C~8AMQCk9v+7VC` zA)qLWfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}GfpqV5C~^&p_ACjmvh2q@}JKv5rp zuc&2uaF+oRzR><)nw#$L>0e`iWNn}Hko9F1?U(MReJVx$*MmZCw- zQk26iMY+sUG?-b6hA>OfP-YYjBcNzF0YxJSC>lvX(f$M!9Y8?QC<2N`6Hs&@0YwK9 zP&9^sqC5hM@(Cy^AfTv_fTAJ-ii!y+8cRUYI0A}F2q-$3fTHmPUs1pGV6FiY{@Z?Z zwyzYOVLuKjO%GXLR#9cTTm88dO<;Q|s$!O+YGx^_VV0s=W+|G;EJc%;rD!s<6is24 zqN&U%I)s3tLkTE4jDVuU2`GvZP;>+VMRf!e9Z5jZGy;mI6Hru7K+y~Wie?f}G>d?u z*#s2LA)x3e0*dAmP&AK#q6Pwr<`Yn~fZ!`CPY*6NK*G6Q44eunnrA-&IXXRLeOX0| z)7=Zcl%geUFGa^NOVLthDO$!XMa!9`=vZbcTEQ$uE19L}IA$q2o*6|a5Kwd?0YxVf zP_&AGqSXWxolHQ{DFhUqN#^(014OIC$U9RROjumrH8C9tLVaX_x-P>=pwe4qRq@w zbTP9OZDE$8OPHl-E3*_`$}B~fF-y@lW+}Ry8AVqRP;?~$MOP6}bTt7*+X*PThJd1L z2`IXbfTHUOD7t}wq8kY)x`}|In+Yhog@B@42`Jh@K+$ak6x~ih(H#U7-AO>vT?7=} zP4E?MN)NW&WfZygUB?TgXiEz-+>;)%zO17A)7{?RO3?#sFGUYBOVLBjQuHvh6g|Q$ zMUOH|(PPX~^fH+=mi3bUL>ICB?5|G zCZOmQ0*YQGpy)LMie4w6=nVpj-Xx&tEdq+(CZOmY0*c-xpy)jUiry#qitbGh9&CVw z!`%#=`=n?`&hpaEF=#zB!sPCodQ?{3)&zPm?b7m>}f?0~bWR{|@n5F1zW+~dm zEJfciOVPK?DEf|oqVEYP+D$;w4+IqbNI=m~1Qh*DK+!J*6#Ys-(H;Vdej}jhcLIw3 zAfV_^0*d}3py+P`ivA&>$Z4hBb`%8&C~84KQILS5mIPnXN9n<{4Uq76_UEoYmZDqi zkF2?^Le`g6l+?<-`3EUVW_u}0VV0s)W+_TzmZEfKDQd+mMH$Rel*uebVP+|6&5WWp z1QfL;pr{=IMG*puvIr<@Pe4%z0*X2kP}GTlqRs>qbs?arD*;8_2q@}KKv53@ih2@I z)Qf@dOl= z5>Qk|Kv6ltSJb~%u+z^*(ZN>H04Z8zUtL$U3Rz!PQFSYK^siD>!}d~C%Pd6`nWbnF zvlLBcmZB-lQZ$uWiVk6xqC=Ub=rCp!9Zo<|lz^fm2q>x}py)^filz}zG@XE=dIE}O z5KuIefTCFh6wM}}Xbu5IM-fmomw=*q1Qaz8P&A)_q6GvL9Zf*dLIR2!3BIBUt%64y zAmMB652jT~(H^U4QLB*kWfd)L<*xcoik7jx6fI|#qGOq*Xa%zrtz?#>j)@1n}DMA1QeY^K+y&Qiq0jVXd?kd=MhkJJ^@9W2)?2vt%6q@AmO$4N$eOY+F;*2 zx}a6a`m%~HZsk7thZJpLdnvkvS&FtYOVOpwQgj)!6m4UcqRW}3=n7^jx{_Inu3|>f z)dUo6C!pvW0*bCBpy)aRimoT1=mr9cZX}@SCIX6XCZOmR0*Y=WplAmHMYj=9bUOh> zcMwo?Cjmuw5m0nD0Y&!^P_&bPqI(IxqKjGuzcoO@xn^`XOHn)fY3zNiLe`g6^iV6e z)!$O|FxyMfBg|6tD6{fS&A~4 zr6`kGio(oN)S6j}+AvE|TV^S0$Bd!~0YzB^6tyRyr~?5-9SJDvL_kqz0*bm2P}G%x zqHY8fbtj;x2LVMr2`K7CKv8c3iuw>xv=0GAeF-S)M?lfO1QhK@Kv92!uP8Yq_<#Wt zUSnShrDXVf`nTDSW(Q=1tS_r5C&T@)r4;3|y%Y^*mZBldQZ$rViiR;u(Qsxd8o?|@ zBblXWe`YBQIuJVj$lSn9RWp0 z5>PaafTHOH6x9<@G=qSmnFJKgBA{qC0Y!5NC_0LOqPYYV%_E?wfqj@}2hk&9D1QeZ1K+#45iq0dT=zIc-HW5&C0Rcr9 z5>Rvz!B?~_BY2Jh68^lKfwNqSUa*QbXN0UTt7vP6duxgmUCQ=SbQ!Z0ZDW?A%bBI< z3T7#~l39wbVwR$-nWbnuvlLy!jG}7^D7ub-qU#ALx`BYA8wn`7iGZS;2`IXSfTCLo zDB3|l(QO12-A+K!9Rw8JNkGwE1Qgv(K+!z}6zwFS=w1Sf?jxY+egcXfAoz;5WCY(Z zK*HPY$M}~>(FXeqArEGRtS_tR(G2&uG%0$F?WO2(W+{4tS&E)ymZGParRZs9DSC!k zik@YbqUV^U=y_%oy+AWIP0Y!fkQ1lN0MNX!6+ffuCpr{1_ zML`0JS`tv?5>S*tKv9T*qC^6Uk_aeDCisfJ$Ouk1K*IU z>7E>xq71f|qD*Ef3NuSlYi22G!z@K@nWd;5vlK;`r6`M8irO=yr~?5-9SJDvL_kqz z0*bm2P}G%xqHY8fbtj;x2LVMr2`K7CKv8c3iuw>xv=0GAeF-S)M?lfO1QhK@Kv91J ziUtr+G?0LzY=W;SEi-tH0TK?_|N0|6)8ErS!@lb{C^KYzSw%xK-KX0~(NMORqG8NZ zG@MzAMleg!NMPC!uw0Y#Mr6ipzYsEUB1Y66OC2)?4+ z%;5J1NO-;7xgRV=hu9DJYcoUEmsK<+)6I-X(NwmVqC=Ra=ul=UI*eJ04ri94D69QgjNl6rIW}MW->N z=yU>#)(}v11_4ED2`D;~fTFVqC|XBA(b)tPttX)990H0q5Kwe30Yw`LC_0aTqVowT z+C)In1q2jbNI=m=1Qcy1py*-(inb7ZMJqCcD-4iup?%kJr4)^{!zGy^>&q(Img!#H zQHm~SdnvktS&FV?mZGberRZvADca5~Mb|J((Y4G{bRDx4UC)f78we=6k$|F`2q?Ol zfTCLnD7uw^q8$Vj-9|vs?F1CvK|s-+1QgvxK+)X<6x~BW(M|%2?j@k;J_3sFC!pv7 z0*W3apy(k2iXJBTiZ0CzK4gG|m!}#ymr2oMR?#DwA?wR3dLq;PxU&>J$@Wt86tfgP z%`8RFFiX+1%u@6mvlKngEJZIcOVNwWQuGotie4t5=oJErUL~ODH3EuWC!pvJ0*c-w zpy(|Eiryxm=p6!z-X);uJpzi}C!pv90*XE)py(q4iasWw=o12pJ|&>&GXjb}C!pvH zg0JYY%wS>{qv+6%2F~MB^sxP{#xFBN)|XZEO{Uwgn-qP^_EPj6vlM;LEJeGSrRWD{ zDf*FFihg32qMwCe z6a@$&#%e0TTW# z)4&q$%hu!%-q^LF9OHmtUDQe3sMeUfSD8ej7S_`IFiTNK zW-02#jH1p26m=n>s4D?Q-3Tb^PC!u)0*ZPPP}GZnqTU1)^&y~W9|DT{5>V8SfTDc~ zDB6#JqW%OF4IrRsAOS_$1QZP-peTocqFjQnC?gy^*8mCMXm`sp!~UNB9)rgn91dAu zR?+aVds{Cl8o~BbG?H10_Ggx&1DK^~6tfhKW|pD@nWg9;W+@uOEJbK96Hru2Kv5Y1Mdbt(RS-~ANkGvA0*a~#D5@r) zsD^-|S^|nD5>PaW;42y$4!&i8n5)mg874&u-VR$hWPMphhlbrh`bg1XY%fKJGfPpF zS&EKemZCalDLRr_il#A3(R5}hs%Ms>8O$h}NkGvo0*Yo6P&9{tqN4~XnoB^@JOYXu z2q>CQK+ysMijF3rXdwYbjRX`eBA{q70Yys)C_09KqNM~BEhC_4IRQn-5>T{);47LM z4tCqeDB5m+Fzpa2>R~?tSs4ylUslnHVK=Xz6rIHOQnZR$idHjA(aFqGbPBT+oysgl zr!h;>>C95JhFOZvU`Eke0*cNgpy(_Diq;WObT$D+>j@}2hk&9D1QeZ1K+#45iq0dT z=zIc-HW5&C0Rcr95>Rvz0Y#e$D7u({qAdgzT|z+7RsxDHCHRVt4+m!$AYuDcjqV9j z^pE`~u`UaTtS_gX)57hUbhG)N_adXst8OO}HUAuK%gBl5Qdjx!>1>AsFLD)M=M#~BkDknK2yk;WXy85g;0u;Y|Q{u$~xm64(mj#CpkV}Hk) z9C>k+;~W}^9OO7hL=MYyoavEm1&%W-@@0|Z%#CD^bDRZ{#RogiqR2g^jToJqEj8`?8p^|I?lO~uMc;eO_7{B$Jrb?W}4${ zjoe%BIG0C)vmEE@NXZ<>xh}G9uH)Pkd9}fDc0@WJ?KpQv>KYwqXXL8Ij`Kj|n`0d3 zk;vfXj`Kuh*$T&bCUXCAj`KpqJ<)MqiHu+6IB!JOpX@mAL|#ADaXyH2UgJ2QM5e8E zoG&8V&vKkyk?+oSobMw;H#p8ukz+SH&YsAF=R3}yS)mKf^&iM8+iY%tK-PvW<`xKK zy}8xg1c9us+sthc$g01>+z5fJYp*i5LLh7Rc5^cXvW8!0ZihgY{om|+1+wgaN8UG( zW&c0v{(&s}9|8{wWZD1Gbx0t~{+FC10$KL|R2&t^vi~XGm_U~OU(E^wS@yrB8W+g2 z|F2MKAj|&8FqMHU`#*cs1hVXZ%`iETW&dscLjzg%A4fkTkY)dM>*;|k`_B{43S`-T zUv_RF%l-qQ3j$g8UwB*;$g=-L-_k&q{WsQD1hVWul668L%l<1zs{>i~pQ$-5kY)d! zk+p#=`wvB&9mul3>3?n@%l@kNra+ecUE9rpEc?rnTLW44x7{ueWZ7R=x;l_$f8XS~ zK$iW5ftvzZ_9wn~1hVXp?A{s3vOjaVGmvF}XzqbPmi?)xM*>;)$5x&QWZ9oPcqWi# zKRA9NkYzvldnJ%%Ke~A%kY(R{e?qS+tBoN=4+?ZdFf^trr}~c4A*e0xyuGdq#Ky#V0W0a7#OMV9MHuK`)ioh!3+mz zm~V$s8ZI;+d<8~p2=p|=ff^1sKjaZONW)h1pb!}251lP#djY>25OBH#D&5q-u1v4# z5}4qoE*-OHahE_rb6?Y1Ce_CFqNWj5(NPTOAXZ|kNyC!CvaHciO<`p;cg z9_wxU`=%8`yz_A3lOL{I?sT56^RP4SJlOxf%bthtIS)7QdgxOB!W{VCH-o+7x##jZ zW4+_q{l`h49qV*mZno)U&%`O_3wz}a%=WLm%sZd?a-nx7K7VEB=gYlo;_C13-DI!5 zgv@QH-go;_r*ne2E$l|q{EZSa|32xdb@mh!GM`+xW4GPPO|5T8YVbCC`H6d0uXH+} zrj0i0lu|Fd?gDd7o13Zck%vXRO$sk63!6>c)JHD~&2c)v67;X|?fw=mmO4)7bn~*r z-U#=`wGL`8#7(y+RB8mXLY%`fDDsH)=xWIolro z!QL_nnWyY{XQR(!*YhXebez+5t=X!dy-Kgv<|nfG=Wo3GoPX^+zHZfB=7`MZJAd48 zu{k1hSs#0RT5qTG17@RPX6xJhjoj36SFD`so#YD}?|<_+d-Y^KwRQ6x?;5>x&-q_1 zce=f&ZOr*j$o%N`&0m`%H0SZoUw41ypUAnJ9)8rGNJ8cV5B{*hJb`pSpqt~^zX>gZ z3EjISJC6OE&^wsiy~I@eHz8=g^P0I++rJ6Fwn*siq&nt#!3&%IJ13aFf64(VBU4IRnBA7w(4X~F46nKJeDPSUzkUUWF4XFA7M%$P}16N zlG@!IUAEaIt(7@(d(7#r11Tv@$Jr{)2_|w*Qc}`VQd35lgJ(pV9V*itD(?J-HR{w_ z>nP1=PqU4V()(`HQMT1l>QL>>MsCyjh@_b_YEL=K`@&qd_Cw-M^Pu*l%p-Y+fq{eC zb4K=QU(z}=5Kb7Ab$)((d%7LnxD8rF?#MUSd8hazu~%K^(@zSR+a|}mcDk%NDd4oo zTAyzoK)af6IQARnDV@U@A_EOAGs!Mvbd(b=v0vGvHQ%ty4)4nec6rIK zcHx93ToQN8u`kVKG@Do1#XqKrO~+JakI8#-bSAPvC-a3l59W{gp8nW_#Q%w(`#pX@ zY}?E_$Z63s(AG_{ODng#T}<~zyG5?sI-#B0p_3c#?Y8dM&D*fGx8Z2>9eV_$-414L z9sjLtw|hbxH{9iaa`fSZHrd&O+}7D{&)_n1isocGdZ*%@y@u&&B1crj%K6&UEO}Y z+>V{JU2C^v*Z-ZP=xokM+IY8PiQUMYPje+_53paGqwe5EH))V}uG^V2-_<+s-i77d zwerthZ=E}D9B2-f>$bNSb-WuX@vedFnL3v4Ztos$q*L56aqY;+e?CV4${VdKaqsm& zx3@h-?~L?x|NF7@+Q*Fqm)Tp7n`G}}8?Bp+^+0>PZ8_Rr@fX(~O|E}%b5Z<@>y5n- zq2u}=9Y@3*hq)no4|3aej5~i^Nv!{)E2~{Eu4#MK_3C3T^z!Bxx}Cuq>2FSl%gOQg z_|KPj)PK6X_E_S9r*<=v?A@cIIrR?N|NFrEnCS9Vm2g zd$8h)+VVp0V8cg@^VX5x6~LjZimEFs%sKRrX^1%t-?8Vts4A~I?woUrlvR(7=GPV% zo8zx8nOYRv?!4n;oQ}YD#5Ig}KP3rP0cY zlJc4&UF2LHKF_S?b==_G=pyeD6gJyDztp^lt19+xhNAL3GZs1(#nsWgLjP!ndWW{> ztT^t17uAg8`i)kOn-VpO%8Z|ayqc1Va{qc78QU;w6vsreC%4AR8m|L&8zgzWkE%Gc~ODY;+ZZUVy`go%R-T;t}Q4q{$pEnXP8i1 zR9h4+HrG__Ta|fLB{frGqrJP7<&{s-P1kf3-py8BQSF_BLUVtKoq?g=>2oP`xZ)gh z&x=-96c$J#l)NSZrH_eVD?*0_Jz|xaf>YZ}5qOzzw_B|-)SCxz%S5t1T(P(v1 zO^tn&;G~NSO2>O=ckmGZo-@=tMeoE1k-R&TmkeRuRwMMy9CP)>j;*AmsyHuNR8SDj z$uH5}yr9`#(R;WsySh2_UxIrau>I%(f~+_%jQVXl&B(d2@nqQbbd ztjlB`VQcctBgFWkDbeD*5_>P_Hq;^P-kdpW6}4673v(YUE-fi&dOq=#+6S}PRhN?+ zyMvp%x_<{W_rK|j=gnIdJ8tjpP*hRU{BFZ3n}^}DiYj|^*vCo#D000!$lUo2GrO4w zEw2sX=yS{$Y-_H=>WZc(K>M&C`<@`NuA4PZn)D&^9l-TtMUr;5EeT>4g!{VOmxKo;^{jufVQ@%%GusMkRBCpwld;B9q(<4?+ zQS6qpU&hX6jDNYgkJswy&YaDr1DF%dugWto7DULNqPcbA??UFP;^DTmqFQ(25wR0A zH-mo-=JQ37cY`<1p4m`8y_T%|^ ziGN7*aK-~$+)0)dnTIO9XyKIX@#UCDNq@T{&(Y$B_=|53VIKWsXS^`CP)~_fMdgJ? zYuw{+>;^9IUi`?6xfUB{)<^3brq8Zxh}!#7?8r(=ON++lmFg~Mp5+V8eZJ{w&hs97 zMvA+Yb4D~1FDm2AF~z;eD&%6B8+R`gCHCQOuLqv^7ZK*6z`F~3S5NGoku$W}5pnn7 z){1*RFKH;OTT~YvU%#xzyn_|Hxc~Nftw~U6VTJdQ8haYit?l19=HW&+YEF)xuFTVS z?6|qt4~iB}sEHPi^Pj<+KivsT%FJU@ZI$=LS5!GT4cqhUnZjLmJb**LBYAANTUN)Z81I1aRtO^UBKdnoixAG_S6> zI?R36JJF{5bxw}wV{CbCw}O!)yV>`G2j+CM?*+2fp`*j;IZ`y*z zqo>VZxTt>VfO&%lo3Los;(14!b;jKJb&Cd=w~|MjM}g@!m_yE3uw>|f#sveW=L|EY zZsD|9qs@EEOGXTsH*lVLcY43+jSKdhv7p<4ncW6dvGZT`3(aa&D*+WZ8UAVK@^+4i#WWQK<_s9pI+=M zcJBr(DzB(D4?>>Y=C7?|&r#;(SzdlgY01>4*T;j*18)=Bl7{K^OTD8Q-0b1B>Ar98 zKrwnvg3a@dc~qz|FE#D+cI*J$irzj^(~WEHWd-I{Kz^RtQPRVzJ=^9rzJKDZ1G!-!gMd`4yAnRSz5S zFWVQCn&$)a3~L{+?1`F}oYrIPevvaMSC=C8U~F!V*wHjyXZH15R9Bq8g?ZNWzA!ho zAIu|J+yj_*t2gbZ?e+3okA=;jI)<2Is*l=t&FdE~^pDf*w*8wk<3Dg$6&2WX<-aJ+ zF}t7MCjL%qwfT6V>7}H7_Gx+zW_DP0pR~L7-c4b?P_lc-UNWzty)XP7M=uSE9m@ZT zht#+igWgM6v!|mMX66p=ADg*oao0`U2KKe3dARamcn59T1&r;x4%4ytdu^Pm|3F?; zRvEV|=Dj%(|FmJxcl@5@xJl-nje_y!k<-6K&F(nd0qm=l*tJfK-%b86J7mQr#TCu> z7Mlze<`sCKe>8ixi9P84>pjHmJew=+D0>HqogM#D*Ouo^H2&?*aO^vAS886Z+0`~L z$l`ac?TaX`I^WM&vzy|-qKSROLu+5PR+QTZ2=8e+=f8eecOSFgCO}QQYt8q0l;XTX^VZB> z`@9|kd-2B_>#-LtO?yLydUDJ$I}%(pb1lTqH7}3j(R+dmysL`yV9(oLPu_Xe_HDA* zJ1pit6g$$`{#jnW_l8;Q8*x`;RZ-2qeI4yR9)eh&Xd`TG`ngg z1ts27PGz2X#_A?3!Ton93&xqf+oDqMAZF(_c671(OYx*=t$7p6T$wsT z9iMp%i)+w4aOg|Bf2MQUbWCQKz1lu5Ho3G1`L{1xxpAAlE!XVzbL{mvd!YUf6W4;S z(&qO}ZY%HlFt3aJ>%;7p#a$ovNzd+^M5`y2)R^zYJ%h6UmeaKJpJN`GoyJ+_l~Qa^ z*zT=)Ct#kGy)W$EnGOC0P6C7mYJ%?}~Z(zAgXFV!p#A zEH-;yW+ydTT$)$iv>o5At+cZ3-aqfK@3n&zyKM@J3z}}19Q$@Or=<5Z{O3sThW6j3 zw_nD;CGG9O?e)0P^eVEj=s&!Uv^VgSq8i8B0k_A=zFhMM04vzMRw**?Oqlmc^{UMr zI>)}r?42wBt@EI(MW9rjL^hw-K-F#oMy`%SxF=N-tt@5#CLo^cHT zgSWuk*Z%zn5&rwS{;Sr!`o`R$!^TdVSJdGB98XEZ>_yd!goc064dNk!Z%*cyPkS6G2eeh?=89hlW4QE#2JV^lE<#j zxW_iTx5xoG3IDzjdv5hEQT)4|9+Q9f)a*Y{$KD>}c)d?ycwivf8@;O5e~_~e$#gw{ zn_Im38>(@;Kjw`YcF#&CdRMr4TK`viTpaV*Xr8+Ca$ldbum?4~*@kRkUcH)oL7{ow z68D0JZ^k|i;)&JYAMvgw`);VWhvhS{@4a%l;u$pi_(T`DwtRef#U%gwV3)_f|89@h z-;>~&^3A)==Cd^Ka}Mv@c7KL%#=WFy_Wp`@_Hy)$WcPNwVBg*JzVP3HwO_J-lN0~O zrjFIViC%2(I=r#OiTam~#~$5T%N$7|oN^v_ze$CbQF^V)r~*>P@$JnroI*MooO;qq`Fuz<}6 zzk9z!>Aij`&WnF>!WJCVo|CwJ4fE`%YuA7Fu;2D~3OLD1|CP3RS1xwFcuvftM=TVS z6*k-5G|surVz*vAw5A7L`!;p_r$wAy|6+Sro4HE8>#zA9K+{o}4>Wnf#(8ERth%<^ zd`6{x;D330(!Mjf*M}1EZH#(li+??`x8PW;PLZ;x-1`N-COXkDRCVL40w+wJxv zyS<+X>=T^*kei1qJ|tz!{L;Mg@#YR(WZoCs>$Q`;D0?5g>4qt-Fdxd9hZFM_YF>HV z`)~HvY5x9+zyIRDoNx9N>RraB_g4K+5;$W`uiTpLt=OYCcZ6DVu{dw`X#Bkm?<*d3 z{kJcpQFe(r;<(4~aaH5Zjpg4JOUw;FIdIy>k+$;Yi`sT;f?QeDbWB!=m z2UwAwn&$M1`!RR>Q||fceOD!~PC7a9l+dXOr@5!MToXK_#aRI-Z=^Y3o&Di)Cy;Hv zbVm#*8)$Yb%AJJFP+3wiIWgR_O`vTc63hy;4|E8040H-~Y0)EKemm)3{=}!2&hCHW z4-m9J;vDxUsGrRz1?^8b$NdSKpKdn4XcG6QrDJ{r&3VWFk$&@)|NV1goB7}WKK8@@ zu`j&i2s-AsOyd3oW4|@$$Dm_>hqdWX&}sgw5<$oOZe84;pksbhChkwrJ9kYX=$K!` zi2D;Xzt$iBC+L`8W;VfIEB5vYo6BSWk0btMm@mdKnAOhJd(Cxw&GYw~SMD{h+G}3F z*UV3j`#&MpYmw7yx}Kc=(_T{ZC$fL@nP>a~a^jxp2AK~Rn!Yz^$PmYWi#@)@f5c`# zSa8lW=Qp{n<2;L{GyC^ zJS~hRdwi?4eqz=Z9n7!f8dLUolMNxew$o~ViQdiwwJy}U+OFpG?QfbTn_sQGT=P!5 znqNbCORE*w!mzUU)fVOkwVv&2&Vsj^v*xrg=)2q1@an5>@0a#)!?cdpny!n(6)q0oK`?Wr*^=YjyYJFYnyIMciYJM@-JHOv){aLH|#apl2 z->b2g$NZM9x0+w9_14x}?Y{tKzu#4BZ>{@jHNRNreSf&t(OL_%mT0ZeTC4RCt#w*w zYMrOGQR_0T$7?-V>ls?tYdv4<#ag#%-LCaUt+#2tN9%)HAJ_Vv)>pN@qxEC0UuoT~ z)&9dW_WCgo_TFlLfz!@uTH9#tsI`aIep&}<9j^62twmZ(wN`7Ls4(9t=qI- zqxEL3cWS*~>tkA<)oOp!)?VJXwSJ`aORe8){Z;GVT3z!vWw%S!+FGmqja=KiYwfEw zTk9~bqqP=l9j~=Y>lCd=Xq~CGLF;0zE3~fCx<>1It(&x7qV-Cx*K4)E3~0~qJz5{q z`lQwuw7#y@{^qScy!~h5?Yc|rk6M4%8Zgh(_WOxiTWM{lwX@bt|ZO)4E4%!2FvC_VOibZKHLt*0JU#q5Xcf*4gH{+s=!%o?%`R+WCB~*PG{TJKv@C zdGiEs=eM=)HZKY7{Fl~Y=Cy>K3$(5nyY=zs0a|C67Z~>V8ns@xuRq_V^@slc{EyZV=7oqoe391Ua{T!W zt&a@$=NGjmn-?th@DZ(*BmDU=t>>9v7q;KuruCgs{`{rZ9tZhzw$@pB{=8W04F&#u zkJg`x{5eqUult)_EPMRsCxg88goFL{Os$WV`t!?LQ!D(rz1FG;{v6f1soI~f(E6Tv z!DWyCYpuN|`*V)gIaB@l7_B!Q>d*IT{pE0f4o3ZTRGq(;Xgz6~Kd;mJM7=-1sx^I< zKX=qxGsmCnv|c#ZpRdyTL4!YkqqWb`{ybRg+(v&kznbe^u3HxS>-}2y9OKXKQhz;g zxxbFrx_X5_uh;t2asK?e){GPVxwF=ZtNeMI*3BpT^LDKto$AluY3;klpNDE~SnJQn zYTa>`KR>AT_p|*uwBBFGZ1C4It*31C=M7q)Ip3e()Ed6fpSx|zQtRzk`SZhC|J?4+N!R#m{&oIZq4l&I{CT6+=Wg=nx3#vp z)t|d-oqC%;&(ym04u8I0>u2VLzV-W~*8V&Fd8F2b_x&%%?gBchyJ7ovl9^$`;80hn zD}|O)>hA6?)Lp5&ySux)ySux)yStzLXYT7=eZOy=bxzje*|~qo4)c_&li8Dyw)eg{ z-gaMmKb+$~543l$2iwO*9&R63%<+gv+xyfUpL@K$-_CKor`mhU9M^fKy|>8mg6G=% z+8jT7p}l|3ap=qKJ$H^{UTyFFbG+mA_I@wVhZTjhAs=k0xcj$eG)-oNHJ?3?zUH^*JRYwrVdyz7VdemuvnpWC}% zj!XR7-mB(#%wVjMK#oiGZ|~J}Jg&N6FYkYLj;~ZdJgMvt zbDX65DN1EepW}wrg<#p+<#<{3bCt@zImd6RAFx#RpE-^g+};c3xW^RjeQ1vNRZkR@ z_kTLa9@Dn>pd6Q(zP;DX@rLS$`;_;;H^(P)e5D*4)#JtN@5-@v^+UOG{5`#1{RpGd zyL0SQj@8GTAbXM=hole9aqb+K$Z^#iH_UOn9QVrc@ElLc@xmOh%kl1VtZwgjIZjkz=iTBA~pznPdMP$H{Th9EapMLykjpoFm7%bL{S@ z{(Y%#SM^6W_BbfV@pBxK2&Pg zH^&2WtUk?+?Z@PJa*n6xSl!K!efzCB-jic>w>-92ce7)UPv`hjj<4m|qa0i9=N8NV z@A6WP)#c9E;|E>s<2YpxsNAM^4Bct>ZN`kQ{(9<8V|HvGH}_igE#+f6hL-Q)?ijk^ zPCIoBt-kAgXo*AHPwoA`J(D>0{WdP&`cr+KWYg`c4>9)j(Hm~K<0iYbKT5k)KQiUN zbM%ho?^)#cX}`z+UA8Vi@FX9xx}hCI%a766r24B(|M^`v-Es6b)jKV?(y~KGj~TP$ z78~w7ruwk|zh5S<-m|m%RsNZlml5s5|NL+Dk8`qUFQAI$2+Zh-8t2(9p_XZuYY+ZFWz=iwg3C^uKUl&D_=oy`>Ka{|Lfyj zQ+>Q))xV2ge7sAl@ZXPjU-j|IpHsPg{iKay|MTMg{^zIhj2XJ!EQ1FR9zI9)C5mCQj+%9j>h)p6hX3b( zM~)mZc<`tZ!)F~;z2D%$8?^RabeYB4KP;;KVLPj5?tR=+x)&Y08twap>8k%P<8_R> zdBI->)dnmzV2OcCKJeQ`9S{8WUjIQG4BGt6&c9w-{-^s^U2*W>Axr!)VyEt9ULO6x zZ}rXxe!H%J^?t)%`mH{^W5z$<=otL(umAk}&~McbXuP|l|9A^Dy6YYLb=3F&srtc^ z?LV7(XZcTR^uDD+HR8YjM5`Or)!Ad;3U^m$_kz`1ySf_3H_M@UWEE@URX4V4*$I{{ z?^kbJS-qvUe0i_sC){9cYTjA>v+wF|+)~{$bagj}R(}fhdZT=sZdbkeeDyB1*Q$4@ z%`|Ai^7@t4Z(SQUPPw~i99z!s?6Gw9A$!#8(=^KSzs-e)b=0TLe{W#&Y7XzHPnS7a zHD~RpPoFtyHD~Ln&yYDuHAi&RXUv?qnzMJ*XUd$Ynj<^vGiOd%%{e;iLo+9+=BSSP zESck1bIy+Xu*~tQIlQ`A!?VXNySiPoW{*>Lb;D-M9#nR9%SL1mEW5gCvu6(|ySi;7 zv-_7_-MBfj`;}eYx>4DE%dT$ToY{TKu5RC4*}bbhYjykP&hAxqb^GSYZk1i#zIn5I zmR;Sx`Lesqu5RD_+0C-6+qXb=kFu-Vw_tXo?CSO{lwB{ox_t|0*UGML-y+#v)t;@o zeT!yymR;Sx#j+~~-SzrZwa2SJ|DGonKU0tWiTOQ0tv++q7jIr#y+aYQbfY|DJ66at zIW5 zY(mz~CS;v#Le|YDWW8)c*3TwngKR=ZXA`nvHX$2j6S8qOA)90qvS~IUn`INSc{U+i zWD~MwHX&POw}mWO`?C7;@3~Y_u~b{g*3~^!ed}hCQ-o~a__BKASRp&))Ck!zGeUOC zjF2&z5wde;gzSxp4o)#l}*Ur*@WzqO~}64gzT41$o|=c z9FR@Of!Tx{lugLN*@PUDO~|3ygdCPl$l=+99Fa}Pk=cYCl}*Ue*@PUEO~|p?gdCUM z7P4)vPxZ;9=X=#BoceZcA@5f->c=;WoFe4pMxW}9V}+cOQzPWm%m_IxGeSNkaIF42a%WDBkh?M?%t@ zATvT9%#4tSG6{J&n~+Dc33)V|kjJtKc|4ntC$b57GMkX6vI%)Qn~-O+33)b~kms@q zc|Mzv7qSU?F`JN=vI%)Pn~+zs33)Y}kk_&ac|DtuH?rG8ZmX?W{rUGiv*J*{y)9(X z@|fh!W|32byxUl@x^x>WA7@6$Cz%oQX=a3cmKhep{rUHNy*&1KXRMG``BHVgqqAA) zbo8p%>z$30tIP4;}Yx)V}mQdZo{=zsVR5x*e zFsOv;HVza9mQdZuLBfC%s#`gZ(7%N0W{xZLE1|lb;|YCBsBY-^LZ1?6hc=O%C*jvLT3rpEuBiJfb^-?yEN_DK+%#yThX+gW518MbxFA^nl6f-Eu@y}Y!+Wd(Q=)QA=Oi5V-+p${3u$% zj-nOqC|b#mqLu9^TE&i{RqZHR&5okg?I>Eqrf5xpqO}By))pvQN1$k3fui*Uiq;n> z+CZRav_R2@0!14M6m2X}w245`rUFHq2^4KEP_%_W(Ut;5TL~0xEl{+LK+(2BThTI| zwZ$qRt(&S@Up9)CETp!pz9nj4ThUIPjm@ejna3&`?qpRj-uV{DB9hQ zqCM;=+S87rz3eF3+ootAfuel{iuMyI+FzjP0D+#WXZ@m21NPU~!3U47YbtfJGMA4O-_QFNvqMQ7PjbhaHu=h#tnt{p|^*->=99Yq(| z6kRA#bdf;O#R5f_2ozl^P;{9<(d7a~R|phcDNuBkK+)9#Mb`)vT`N#@oj}p`0!23n z6x}FLbdx~Q%>qTY2o&8aP;{HnR&+{d?S%?R>)it9)F`T#aeHU8_$rF-?ri)xQ54?nHFrsy$&qQ?b_o)9Q{QlRK5fug4c zik=ZDdRCz5If0_*1&Uq}D0)$#=p})omj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugsC zwxT;bYZFvofp68yebHS}bU}G^{Z41I_$rD%=xoecedp}h`=Sq>A4MP8QS`ALMW5JF z^r;<1pV?9LxgAAc*irPQ9YtT+6n!mF^o>B#w*p1q2^4)VQ1pX9(T@T}KM555EKu}| zK+&%PMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N%zXC-aUH@~H-@Zoc6e#Kv+KS%mtgTl8 zX>C`&2j=}K+P&Nt)w-I+S5egLYV13C6m>g4ih9~n)UuS{bZB#LHseiRM0qi7a8iiX)yG~AA&S?wsA&5oiGb`;HSN6|=|qB#VLMhO(n zDNr<*K+)U+Me_(0%_~qepFq+40!0f56fG!Fw2(m2!U9E$2ox?m5(j-s{fC|cX5XdQu~bp?vn6DV3=plAbuqR|3H8wwO{ zBv7=mK+z@wMVkr~Z6;8(xj@kt0!3R26m2C?w6#FdHUdT43KVT8P_(^3(GEge(ehoj zVHJ>8t=t!_5Ji8KPj5SRHH)vJXqT?Wiqk~VuFj95-RvmZ-HxI?>?qpPj-tKnDB9bO zqJ8Wr+SiVv{cMW%7brSFpy)t>qJspA4i+dnM4;$Ufuh3%iVhbjIzpi6NP(iG1d5Ip zC^|-<=vaZG;{=M17brSGpy)(_qLT!QP8KLSMQAG;(^cE00@7N!JVmr~6qUcETR*j{ zS$q{mXLdDCoi2*ba()z@ZAZ~Lb`+g!N6~q96rFEJ(FJxCU1&$qMRpWjY*TcJK+&ZF zMVAQ_T`o{`g+S4j0!3E|6kRP)bd5mKwE{)g2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xN zMYjnQ-7Zjchd|MtLR-=4UA4O^Ag$v%D>!FF(Rby(=&r72@l_Pv*VTA?hA6t<`BC(M z9Yqh?QS^`orr+fnp{P0^DAMNbJ7JuOi5j6l(|0!7aW6g@9c z^nyUqivmS22^767Q1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH170!8l$ZAJHV z)w*V^6dhBp^zV(LKIPH%`(4fAt0?-ot1;!wQS^!Pqv%sRiaxWW=yN-YzObX{OFN3b zvZLs0JBq%sqv%_kqVEKXz85I^L7?bIfuf%TihdR-`bD7VSAnA61d4taDEdR7=ud&7 zzXXc@7AX2hpy*$LqUt-4&#e9!tFNe6Pt}yK#&!x6bqN&J1d8ecMGc{?=))27Wt{p||*%YlWP_%(S(P)994F!re5-8eOplB0;qD=*gHWMh? zT%c$Rfub!1inbCc+FGD!8-b#21&X#4DB512Xa|9!9R-SZ5-1uYv=yyXt4%bbQgmba zR_K+ZXxH-SdgofR_$rEauQlc#8AW?IKZ^FWqi8QXiuSgnXdgR@_O+vEKRb%{x1;C) zJBkjpDLP1?=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o5 z1d2`+C^|`?=wyMSQv`}m6(~AQpy+g=t!UR;ZG#F(>$3u9woF7FG+fnq0 z9Yv4YQS_J{MUUH2^n@KnPufxRlpRG++Y~(`Q1q-o(Q^Vt&kGd2AW-z8K+#JAMK22! zy&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7&{lMRt@c#~ zq;*bt*71QT`o4U6`>56|zKWvHYK=bgM$zZakD@Q^DEiWlqOa^I`r3}7Z|o@g){dg@ z>?r!)j-nrIihdL*`bnVZXMv($1d4tYDEdvH=y!plKLm>Y6e#*jpy+RbqJIR6{uL;y zzQ4PD*-lZXKv9=KQB9zzE>P4EDC!|l)D$S{7TStFsnuq!fV5^RPgj2$MSGS<*FEda z;;Sg?Q*W$1e-!m~eiZeyqo}_fMFZ?88fZt+AUlf2v7=~QJBr4$qiB4aq6q|wCKM=| zNT6t9fuczSiY65(noOW*a)F}30!2dvilz`Kno^)>DuJS@1&XE-D4JHFXgYzS=>>{r z5Ga~aplBw6qM3!ZqF(jdZWWN$#^t`KcfEb3ze)LwHniR>zKWt*>y6VFjH20`A4MbV zD4N}lqLFqK&0$B;C_9Sgw4-P)JBsGEqi7zRqIm_1<`XEIU!Z6KfuaQkiWU+mT3DcH z5rLvb1&S6EC|X>gXbFL$B?XF>5-3_)plBI^qGbh&mJ=viUZ7|Nfua=!idGWZiiXu| z_f$Yy2UfE_Jc`N>`>n5BZx&xg(dzZay9-Cr8qSZRHSH)`%Z{S8?I>Euj-qw#C|b{s zqV?@4+Q5#Y(KbaJ3KVT5P_(f?(Ix^#n+gKa zucBzLdSmLvqG)gDN6|iZ6zywA(SCLm?QciX0d^D}Xh+dOb`%|KN6{fRMTZI$9VSq8 zxIobn0!2p(6dff{bhJRxF#<)$3KShDP;|UN(Fp=YCkhmuBv5p+K+!1zMW+fBohDFp zx4EmZ+&-B6x&+%t-9DBmV>cD-4A6-DRQ8(S?AMHe_fiY~OH z=ps9cF1DlS5<7}6wWH`VJBlv1qv#4dimtRNx=NtvYJs9_1d6T|D7sFd=z4*o8w84O z6ezk$py+0SqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zgKC=-hhk zxC%(C{KWD4c~P`O`Hc2Jy;*z}MUT`Q*Dn=Ck2*h!9UZCg&fua`$ie3^ZdRd_86@j8x1&Ur1D0*F>=na9QHwB8`5-56G zpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFao6QQl>p?d9=3P@{I`6Tvm6m3+Vb^Ns6 zEWV1OFYAq8mx-dUoF7GB+fnq59Yx>TQS_Z1Mc>;|^n)EmKiX0BlO07r+Z6pGQ1q)n z(Qg7pzY7%oAyD+EK+#_UMSlwv{UcEHuRu{pBbV(IbqW-92^7@?is}MI4S}K_0!2-M zqHckro&rTJfudeQThZtB+9bqaucD}bqcQLDQ8d8$Q8dtw zqCs{PjblgAxONncXGhWab`(uuN700K6isAPG_gR@BmzZ~3KUHyP&Bzf(O`k1Ap%8H z2oy~zP&Ac5(bNJ((+CtzD^N6@K+*I9MKcH#%_vYblR(kT0!2dwie?cg8YZ+A^=;HP ztbnwpD&KeAuhG8J|FnFw(eOsI_$rEKZ!`{EF^WbyKZ@qCqiB>JMRVFwG?yJkbK6lg zj~zwx+EFy09Yyoo6fGc7w4gxILIOn#3luFPP_(E((P9EciwhJjAyBlWK+#eHMN115 zEhA90tU%Fn0!7OU6s;gow4y-KN&-bI3lyy)P_(MhRy13qc3B0a^+>rd8WBa?l>4I9 z8qMOXC|ax0czoq3THE)KJYo*hN&+flTE9Yv$>l z1&THkDB4`0XbXX&Ed`3U5-8eQplBO`qHP6=wi77YUZ7|PfubD+igpqx8Y57&vp~@< z0!6zD6zwKZw7Wpj9zt8u8jadF6_D08<)P4;QB?k;G4(wg&El&l+PBf@w^|hK=lm$z z-;SaK>?k_Wj-rF?C_31VqC@N`I@FG$!|W(J+@|OVfubV?ijEQ}I$EIU7=fZ=1&WRn zC^}xC=mdeH69tM+5-2)Zpy(8VqEiKmP7^3PU7+X;fub`7ip~-!I$NOV9D$;9g|?!- z8?_M?kk%UIvTUCyI=9>xo!4j?pe0j-qR9imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*py+miqB{hN z?i47xOQ7g(fuef^itZICx=*0!eu1I~1d1LMD0)a}E4rXj+oJ-~D*uhH`h`*SX!W-G z!;NO~RTMqmXq>rL6g}bmD0?nHPj-nUrD0P4EDC!|l)D$S{7AWc|P}CAA>LpOrTcD_qKv7?zt>~*p zt;f2RqVjdu`qxo(XnCmJuSc`^DvAd6XiU3)6piEjC>qy}qVen~8sCnh3G67E(2k;s z>?oSpj-pBID4Nu!XflDK$pwlA3lt3zD4If`Xi9;isRW9q7ATrVplDiwqUi*RrWYuh zL7-?xfuflNie?rl8Y)mUi$KvZfui98MY9SN%_g)J4d_u@rUKI1xjeca*rR==KU2Bv zAJL;(d=*8bdNj5f9Yu3GKZ@qEqiAkBisrGSXkI&t=Ch+{emja5u%l=}JBk*vDOy;d zXc2*;MFol$6DV3-plAt!q9p~2mJ%phTA*kdfudyvik1^7T3(=N1%aX!1&US@C|X&d zXcd8?RRxMx6DV3;plA)Dt!QMA+6fhq*52il*c?$*{sXP`HG4FRucBz(9*r9}ilX(L zA4TiiQM7>_MWgK~+R%=ojqE7e*p8x2>?qpQj-t(MiZ&N0+CrdcOM#-T1d6s6DB4D# zXj_4z?F5Rp7bx06plC;dqMZba#t0PcEKszIK+&!OMY{9N6|rc6di0w(IIve9co9> zVRjT9Zb#7(b`%|HN6}F>MMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD3lyCqP;{z5 z(P;ujrwbIFAy9OtK+#zOMP~~Xog+|mu0YXw0!8Nw6kQ;+746rfHrb|?qL<5k(f(0X z{^Rxa3wtz+ucGME9*y}okD|+*A4QkjQFMhJMOWHUbd?=NSKCo^jU7eT+EH|!9YxpM z6x|?DbfZAgO#($X3l!ZVP;{$6(QN`nw+j^AAy9OuK+#fmI=&2r!gSU*L zr=1@~&)8A)tQ|$q*-`Yo9YrtLQS_o6MK9S=^s*gAuhN(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1% zmC#o7M334P6_D2ZCi06m<#|bqN&J1d8ecMGb+X z9s)&8fue4KqMiapErFt50!6(Aiuwo?^%W@UCs5R1plE>5R`hL;+IJO@)|hhl^Ia5O zTpnEyY&MIpqG-HkW59M%G`{nrXaYNmCbXkyB0GvEwxehgJBlW?qi8ZaiYB+CXs}Ju z5P_m81d65JY9K+$XhMI!`?W)~{aS zMe{g6isrSWXg)iN=C`A00XvEow4-PtJBk*zqi7L3iWapgT1=p5ae<;G1d5gvC|XLO zXla3>Wdw?r6)0LxplEr4q7?*+Rum{&NuX$DfudCeidGdUT1}v6b%CNa1d7%aC|XOP zXli*HwzTqB2aXzK+$aiMYjtS z-62qPr$EtN0!4QV6x}0Gbgw|seF8=I3lu#dQ1qZc(L(}74+|7MB2e_GK+$6YMUM*< zJt4FeUDm8ER{?3gUjAHKFW6D^q8&vq z*-`Ye9YwF$QS_=EMX%XW^tw&a8v;dd3KYF1Q1rGy(K`Y~?+O&XCs6dhK+y*RMIQkdn?TVBfuh+3ibe_)%^^@UN}y;? zp{;2A?%LpeD@99|Z<3v$yM3kqWO;NwS9i1cDvIXoZY;Qe6wUAaC|badq6O_JTF8!~ zh3zO>#Ezmx?I>Ezj-tiwC|bg%Xi0&hr38wW7ARUqplDfvqU8jNmKP{mL7-?wfufZJ zidGgVT1B8}Re_?_1d3J{C|X0HXib5lwFHXR7ARUrplDrzqV9_LpzdbzRTLf8-FW)o zC_3EvQFMeIMMv6Ebd()MN83?!j2%VC+EH|z9Yx36QFMY$(TM^@CkYgtEKqccK+&lJ zMW+cAoi0#xhCtDo0!3#D6rC+lbdEsLxdKJ!2^5_#P;`Mn(S-s<7YP(yEKqcbK+&ZF zMVAR}MTd0PeyD)7uIa4c92!L<3#rSyo5fdAbai)Q&|y(@jq{`ET04rav!m#GJBn_w zqv%FEif*!_=w>^LZn2~2R-2;R1d47KD7r(S=uUy6y9A2v7AU$$py*zKqWc7j?iVO} zK%nSBfue^5iXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!?g7TSug?5>TffV7sYX8o!t z8c;r?J=5JRzKWt3x*KaA5k)ULKZ;(mqv&Njie9m!=v6z4UbCax6DWFLpy&gEq7Ma%J`yPUSfJ<=fuc_Ziarx4`dpys3xT391&Y2B zDEeBU=o^8eZv~3J6Day#py&sot?0S#+CCMKR<%0n&qvYu<%#ScyPL&VQS@tfb$b+b+7xvO6x9TZ>HqFw?;y#RfgU^|M2*ikfv z9Ys^xQ8bkuMN`{RG>uKsv;sxb2^38)P&9);(ToB`GYJ&UEKoF5plB9>qG19>!v%_F z6)2ibplF0Z(d+_6BL#})5GWcYP&B7N(Od#Wa|;yBBeWGw)U(z)wo){Gc|bjJ&-Ru6 zx??ZcdNzx%qG-XMjTw)RqJ^9vMGMorn+flTH9YsspQM8mDMN8Wh zEhA90tU%Fn0!7OU6s;gow4y-KN&-bI3lyy)P_(K*(P{!ks|ysZAyBlYK+#$PMQaNb zts_vhu0YXx0!8Z!6m1|-G+JmYn!jglg$hV(jdJ(1Kore1_JXZvv-m2CHtpHi;lwD~ z%=uBYxgAAY*ip2l9YtH&QM9!kMcdd>w5=UQ+u2dHy-m>$0!2Ft6zwEXG)ACkXMv(! z1d4VQDB4Y+Xm^34Jp_vO6e!wDplEM_qJ0F4_7y1FPoQXjfuaKhiVhSgI!K`CV1c4T zgtnrMd)7{=fV3Ve&pK`rMNgM+HafItv-m2Cj_ldE_2eiz%K1@rv>ipq*im$>9Yx34 zQFOc=MJL!%bfO(aC)rVSvQ5z`0!60^6rCnebh<#%83ILT3KX3sP;|CH(K!M|=L!^^ zCs1_0K+y#PMHdPbT_jL+u|Ux!0!5b!6kR4zbh$v$6#_+93T;J)_pH5D0ckB-&H52h zw0ODfzp7`m_$rF7>)H7G)F`^%`B8L(9Yr_VQFN0XMK{|~bc-EDx7ty3n;k{B+fj6f zP0^hKMRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el2^2jnQ1pmE(W3%Ij|mh#E>QG@ zK+%%|MNbJ7JuOi5j6l(|0!7aWZAI7gtW9xRrD)FbW&CTS=>Bqz_I%G~@l_PP+_SOp z8Bz3#^P}ihJBnVjqv&-zir%oJ=uJC{-m;_UZ99tIv7_i+o1*swiryC}`aq!QLxG}? z1d2WuDEdU8=u?5B&jgA-7byBdpy*41qOSysz7{C@Mxf|hfuipOioO>p`az)RM}eZB z1d4tZ+KOK6S=+n<(pt8_c`1rcDqouYrDwDFDvJK-**N^HDEia+QS_G`MSt5-^p71y z|JqU1(aM#36m{BB)MZCe&5okFO;JOjsE0sNQ=q6@ps1%nQA?nxmq1Z(fucSFMSTT| z`Uw>E7bqGaP&81WXplhBI08lE3KWeeP&B?k(F6iT6ABbfB(xR%*0Xj^1*G+Ed0g~+ z6wO@5#I0uWRTNF$YCL;R6b*KM6b-SXXbL-urnIAIDm#j%wxehoJBp^Yqi8xiil(knIG>bsdFoB}s0!6b56wM}3G(wW9p>?m5&j-sXPC|cT%qGjwTTGo!DlUB3%DvGvfHP*f`inerq6m4Zk(bjepZDU8#wssV4 zXGhWYb`mgvCfa8?k_Xj-r$7C_34WqEqZBI@OM%(`<@P z7brSIpy*72qO$~w&K4*-N1*6jfui#Siq01(x7%vVIw>&}m&H|!{S(~hFI>?nHMj-q$$ zD0p9|Vei6e#*hpy+3TqF)4xeibPCO=v56rBz$00@C`Uz-*u%oDHQ`9X` z)Kj3SB~a8$ps2S%Q6GV#z5+%41d93#6b%q48YoaSNT6sOfueB*ipCQt8egDj0)e6l z1&SsTD4JNHXcB>?oSnj-u)8D4O1mq8aQcn$eD;nQV$?7AP7jP&A7`(J+Cc;Q~do3KY#I zP&7iIXm)|3kpe|?2o#MHD4J8CXfA=Gxdn>m5h$8hplCjUqWJ}i77!>}P@rfbp{;0e zui85mkk*sstFc3RwXgIyEDyC8?$s>5ilW7PHU7OWik5JG6fJ2-(NcC4Ep129GIkU# zYe&&?b`&jdN6`v)6s>4ew30y4$^u2J2o$XyKS7Xr|qi7rFN71%+6m4fm(e`!}?O;dIj&>C7WJl2$JBoI;qi7eK zqFn`wb`vPtU7%5-2)Ypy&{R zqC*9W4ihLkT%hO(fubV?ijET6ini=k+p+@Enxa*~*(!>*EDw^7?$s>5ilXCtHIBSF zicWBT6rE^C(Mfg`ooq+ZDRvZ{YDdv&b`+g%N6{H}6rE{Pbe2HT*#br92o#+wP;{O^ z(fI;J7YGzxC{T2fK+(klMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@ z(e*-G(XqX1*Hu7T+n4*I1b$la=J}9LA>eVd1ilUC*jdkye zqR!sAl8>S;JBn&{6xHo0YS>ZK!;Ye+9Yx)C6!o;DsAW^sOQ5K?Kv5roqP_w}{RE2o z3lt3yC>khGG)SOm9D$;71&YQKC>md&Xaa$v2?dHK5-6HjplA|-qDcjcCKD){T%c&M z&{p(Mui60>kk&8dXNLS6MYC3Ks}JejEWV1Ose3mryeEpLaefp{Ye&&^b`(u-N6`#+ z6wPQy(M)y}&1^@}P&B(` zzS5tscQqF4-7LO}qNRE_KEE%DmUey=En`Q~vUU_LXGhWUb`-5(N70IQ6s=@O(aLrd ztzuKOszA|d0!6C}6s;jpw5CAOS^`CD3lyy*P_(W<(RukAZZAW$?~plCyZqKyQK zHWnz_M4)I>fuhX>iZ&N0+CrdcOQEf3iQcuo_g9J<>?j&zN72r96zyV1(XMtB?Pf>O?lwhx2o&upP_&mo(cS_@ z`v?^6D^RqbK+*mJMF$8J9Vk$AkU-JF0!4=i6dfv1beKTV;Q~cR2oxPDP;`_)(a{1$ z#|RW1E3_4D)4R4x1*Ek|c|g5w6s=aqalM?k_hj-qpHip~`%I!~bJe1W111d1*cD7r|X=wgAQO9YB86)3t) zpy+aeqALW7t`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7r~#D>|Wf?TiXY>-Tb{ ze_|BvHTHt7ceD5^if-@Sxbx8{y2JTVbf+CfciB;Nw;e_I*im$^9Yy!qQFOl@MGx3f z^q@`ALjpw)3lu#fQ1qxk(PIKdj|&t%AyD+BK+#hIMNbP9JtI)`tU%Fo0!7aY6ulr& z^rAq~O9DkN3lzN~Q1q%m(Q5)luM2HOxAv~RR{?1aD|bJ)MbTu{+v;!hZWdof(L22x zoliv3yUvfI_v|Qo-;SaW>?r!sj-rq3DEiorqEGB7`qYl1&uof57byBdpy*41qOSys zz7{C@Mxf|hfuipOioO>p`az)RM}eZB1d4tZDEdX9=vRTF-vo+&7byBepy*G5qQ3-+ z{uU_uM`$a0t9Nah3P|hfMg`~XD0;Qr7yaA2S$q{mwLXo-pNgV-pZ|TO->{>ohaE*t zJBqsPDC%iPQOk~^UUn4qwxg(zO;KNgqJ9EJ{RN5!2owzzC>kVCG>$;gxB^Av2^5Vl zP&9!+(S!m;6A2VeEKoFwK+&WEMUx2>O)gM0SfFT#K+zNeMN*N6{>H6b-YZ zXt*6kv)UBRCQvj&plEi1qLBhca|jfT5-6HeplB|EqPYc%<`F2GSD9A%UWW1&S6CC|XpYXfc7J#RZC%5Za2S=~KI*0@9kkz?n9RdX-OaOZI6NUq#Wf zeHt%57e&iCKZ=&Oqi6*?idM9vXeB#}R<@&P6+4PnwWDY?JBn7fDOy9IXib5lwFHXR z7ARUrplDrzqV)ud))y$+K%i)}K+%Q*MH>keZ7fiP%bXqhM~PZQO*?b9s2ilQC+G$wp8igt2-6pgW?XlFZ$ zcCn*qS38P!v!iHtJBs$Oqi9b%iuST8+FPJ#AAzEM1&a0)DB543=m3GD0|kl>5-2)Y zpy&{RqC*9W4ihLkT%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mepyX!}03`6?i- zDa*5tJ4Df(<-X{|KF#8*C_1%IWBr$-=rrd?(dl*+onc4OnRXPNWk=E3b`+gsN71=< z6rE>B(fKw-7YGzxC{T2fK+(klMVAN^T`Ev?nLyFy0!3E{6kRD$bd^BS)dEG=2ozl_ zP;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-72&do!qB(Pz9v*M0wWnlqlMwJi5NEPqX+c zitg&uxcJp5y4(3tbdMcH_u5f(pB+W_+fnp@9Yqh?QS^`b2^2jp zQ1paA(USs2PYDz~El~7~K+&@TMb8NoJugu7fIkCD|)w2 zt^XU9qFc&+(R)$!UHSIeuD;FUt0?Nxw=w*!C~7)Cin{G6>S;$&%Z{R6b`Ssq$f19EK0!0G_iUtW3jU!Mru0YXv0!8Bs6ipydG@(GzL;^(<3lvQvP&BDP z(PRQelM56L7AP7bP&9==(Uby3QwbDJEl@O#&{kCMTU)IH(z>?5Y4mMh=~s`ms|&Wi z&El&lnz3(V*LR|5Cg(@d%ytwFwWDYjJBo(cQ8e6+qFL=In$3=)5q1>KZc{W;plA+( zqEP}xa|#sAB~UcCK+!w`Me_<2%_mSazd+Ff0!0f76fGoBw6H+YA_7H=3KT6SP_(!} z(GmhhO9~V%B~Y}q&{i~k-`ZIfkk)49D?m5(j-s_}iq;k=T1TL0U4f$Y1d7%dDB3`vXtY4l zh5|(!2^4KCP_&6a(WU}Ln+X(cE>N_EK+%>0MOz6JZ7oo=jX=@10!7;i6m2iG6)o4d z_CW=t^;!AxY0F1ZS9x^3L*HicRTS;qw^92rigs~+6zyt9(QbAW?QTcW9(EM%X-Cms zb`mhX@oMDo}KoK+)j>MMnq}9Vt+B zlt9tZ0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(aAzv(N2A9(^WuP!^?fqm?)~3N7twH zZ5Cfe(HVUkOMV3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WES)k|^ zfudUlif$7qx?P~?4xz2+w7#`%D zfucVJivAKP`dgsrAAzEO1&TWQ<+7ckPJyB>fufo~QC(;&`k-&^j|xcZkpkz#DB7)% zYV>OsUqw;RevOI0ilUbDqo|i1MZN7P>SISyUptEW*-_Nrj-ml}6b-baXpl|OI08lE z3KWeeP&B?k(F6iT6ABbfBv3T5K+z-uMUx5?O(sw@xj@lifubP-MN%vvtMn23P|gk@)eNoe(fv$^9rdM`ZbHMqG)Kp#^`UNXcp&3 z(J(uThTBmzs~ttN*-m);(HwRZjj}14Q=n)rfugwuislh0npdD`K7pe7 z1&S6BC|XdUXd!{3g$0Th5hz+zplC6HqQwP@mJldfQlMxlfuf}aik1;5T2`QFIiam+ zrhc_UDj=?d=*8z^=o|nLlo`q{3zPPj-oy7DB8=8qP^`X+Q*KfeeEdP&yJ$~?I=3HrszO{ zqJspA4i+dnM4;$Ufuh3%iVhbjIzpi6NP(iG1d5IpC^|-<=vaZG;{=M17brSGpy)(_ zqLT!QP8KLSMWE<{9YvSeQFN(I(PaWfmkShKAy9OsK+#nKMOOmD0-k@WA|U9=t1X4(L;6=J#0tOBX$%$YDdvy zb`(8sN6`~@6g_E2(Ni`>PYV=1BT)3LK+$soMb8Tqy&zEZqCnA00!1$i6ulx)^r}G7 zYXU{D3lzN}Q1qri(OUvVZwnN?BT)3NK+$^wMehp~eIT?I-Pf;nP6ed3e7P*UKZ^R6 zryxJ<*DSt@qEGuZ?)^QAK68E)eQrn57j_hVX-Cmlb`*VWN6|NS6n$$)(RX$feQ#6r zgFw-b0!2Rw6#Xnv^ou~zuL4EC2^9SP4EDC!|l)D+r^KJHihr~=YjpnMYhB#LG%_eI_Po5fdA)VqJ9@mCb} zaefr_wWFw?9Yy`^C>mf#(Lg(j2H8MAW$@;K+#M> zTT!cjZH5X+>!k8^v|jz&SNivsPj55#Zx&xg(eVC_rT>YdS)Ct6v)NHJ!j7WZ?I;>) zN6{R16pgZ@Xihtd=CY$`ZkwWc1d8SrD4I{8XnujB1q6x~6ewCqplD%%qD2IX78NL3 zOrU6Sfubb@ik1{8T1ud3X@R0;1d5gwC|XXSXnBF66$FY_6xxbr>0jHv0@C`vJh~nh zMW>cKrj`0Pi?5<+wf>FcJIV(b)=^*G`BAin9Yt%}QM8sFMQhtpw2mD`>)KJYo*hN& z+flTEP0?t9q74O#HWDb>SfFSVfuc;i}u%qZeJBkjnqv&9pqC*6V4izXmOrYp+ zfubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vm69kG*6ev1Lpy*_QqEiHlP8BFRO`zy> zfub`6ip~_;igxc``>O)d+NC_vxJMKnRql(<>fbEBilX!SHzuuq9K_iBqVt^}MHkpn zbfFzZ7uivCu^mO1*im$;9YvSfQFOT-MOWAqT`5p>l|a$e0!7yd6kRJ&be%xa^#VmV z2o&8YP;`?((ai!yw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObf3^xbWZ=; zLKTqK1m*7M+$dV9T%+CJzgc`0MGyCHY}AaRN1Pu;kJ?f6m>orr+fnp{9Ys&tQS_7@ zMNivN^o$)v&)O6{Cs6dfK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1 zQ1rGy(K`Y~?+O&XCs6dhK+y*RMIQHH}A%8sJ1?I`-jj-qevDEiKhqVMe}`oWH(AMGgm$)@OMfudgo zihdO+`c0tdcY&fm1d9F?DEdpF=x>3de*}vD6)5T$kjr+8It7Zl1d3_`MRkFqhCopd zfug2BQMW)*Pl2MA&{p(W|JpMZkk)q9tbZOwmu)(VTV^&1FZ? z+;$YrV@J`vb`;HLQ#8Lo(E2(Fy`ZD+&~?Bv7=nK+!5fThXioYHL+MT9=oHLbFBDgyqro zssozES5dU)fX1Hvqi8MXN734L6s==N(YkgNt!GEk`gRm;U`NqtJBl{6qi7?WqKyTL zHW4V=RG?@xfuhX?inb6a+ESosD}kb|1&X#2DB4z_Xgh(T?FEW<5GdMFplBz7qA>zR zI|~%;B2cueK+$djMY{`aMXL{}omT;AJy7n8)`+6Z%2SYg3}_Z#MbSP38ut&3qJ5no zMf=%Nw7(ri2iQ?`pdCdA*-><`9Yu%OQFN#sMTglG9WGFGgh0`e0!2p&6df&4bc{gJ zu>wWM2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoi0#xhCtDo0!3#D6rC+lbdJzg zwAX;zCl!#^RORkx?S!U2uuxKVVG^P}iuJBlu`qv%pQiY~LG=yE%X zuCSx%N;`_KvZLr~o1$w3imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*py+mi zqB{hN?i47xOQ7g(fuef^itZICx=*0!eu1I~1d1LM+KSE}P@Aa&(t4&m>v%yFon7vW z9vaXrzKWv91~ir(KZ+iAeiS`nN70jZ6g_1}(bIMmJ!41Fvvw3cXGhWVb`-r}Q}m)h z(MtkFFAEgCB2e_IK+$UgMXw7Ky&+Kara;kK0!42N6ul!*^sYeBdjdu83lx1IQ1qcd z(MJMB9}5(HB2e_HK+$JHThSu}YCBdyT7Q-+{YRtdkLqpp&j&P%ucGMd0gV$UjG}Lx zA4T8VQS_Z1Mc>;|^n)EmKiX0BlO07r+fnq39Yw#|6#XVp^t(XO9|A>x3Kab%Q1rJz z(LVx3{|Xd!49sOaMV$ggT>?clfug!VQA41phd@zNpr~7*sHZ?tOQ5KiKv8djqCP@f z(U${iw^cw|Ht&fv;sxb z2^38)P&9);(ToB`GYJ&UEKoF5plB9>qG19>!v%_F721mW53K!D0covOo+27BuzjU} zaD}Hn+rVb=RTRxJurc{$Q8dc=Q8cF=MRVCvG`Af^^Vm@|uN_76*-?j&-N706M6m4Wj(Z+TZZDL2!rZz>J2^4KEP_%_W(Ut;5 zTL~0xEl{+LK+(1WMcWA!Z7)!?gFw-a0!2Fs6paxm+F77z7lEQ(1&VePDB4}1Xb*v+ zJq3#P655K^8dy7`0@4~?zB6R)C|bSzMcKUvHjA&KX#atYE2oH}1Dqd42ij3|kR3$_ z+fj6g9Yu%QQFNFcMTgr_bc7v6N7@t}B~Wyq-yR1Y|jjpkdnPUKw+F7lK4GG$yO$vm4&jHH`~=Fv#sB*!Tk zSsHPivXL)}IZnk$m6DE=5*b_CajHe0DeE{jBfph*oVt-_S2#|+$Ssu}r(tAI6~}2B z30HHR7LmTy9j8rXSxv|35c#sU<8+BsO?8|ek@4w{(^Q?C zw>EX05s|&k9cOeTsiotLi}Y{pI1?iew{@H;k+0i3PG01yPL4A(a(x%anG@O4&2i>N z{_5d4^CK;LJI`6Tkf9LG5nxp1@N9F4TS)p3qR?wIE|-$g!H;5a8ECGK>b z(~%(y9p`N1(M68)d*u6j9p`+c&i#&aF*GII+AqU~3hn;;Oq zYn8bT0@06Fn;RhzEw$F%3W4ab_2y;>MAvRGw?iOm|26w+fvElG$ZH0o_TQ7P8;II} z5V&3-YX3#ohJmR4Cpnu2qW0fZY!Qgse-y7xAZq_rvkrl%{b#AV1fure73vX)p4wq< zlR(t|%N_#)QTtCb3=Tx?->pA95Ve0f`iMZ({_WPI15x|e6ORi-?cXmuF%Y$XLFkk~ z)cy^Rd4Z_?EBa;zqW14tn-hrIza(pJAZq`Xqxpg8>&MJ36o}ftXJk zC;cA`MC~8dULJ_rKWn=x5Ve0;a!nv=|Fqj2o$_RpJa3PkN67}y+$+TZcL zEfBT8Wp{fZYJbn=Yk{c!O>;W}QTw}|b_b&Nx2?Prh}z$GurCm`-#FeMh}!S`eG-V; zZ`~XUMD5q!j|QUli>Jo|QTx@e?*dW#<%^SnsD1u_vVEiP+&C^D4kv{Z!%fZ4 zGOo;jTq@pNs>oYS(DeLw64skE)4s_>y~+I77QV?Oy-8gv*_`ARUXMtUxpwwFNAq9s z9H*FmCVD5u(*mu_aV2V$D;6jo+otTYcIE7QEYYyY)vIXUNXffy3z&~nhIw77g|`Kq zn6me`D{DTGX-?~MEy_(!&VM`R4V#a1Mf0D%yEPxH{QukkStdn)6y3EA2-nFnr^Ey< zBquom^TS-$-pXld>C>{($K*~)&z&|ZeOhMjsO-!s({l2%N9ARYP9HUG)|9*)8%AZ1 zo<1!*x5(@4<;|s=rB9hQe$x27@iVfW^l>?pveUCBX3tDdo0u~yYhrrtxU6Z}>C>_& zXXj?+rf1jB%*~rVdVEfLUQW)$QRA}4PtHvrJ8D#B*0f3K8TB$7WY(`&KO-}vo{gy{ zrcTb8oSmATHFA7vM!mEKsrJ=r=GFi4s`T-bM@^hQIy-$*)~IpgC;vac8o9G_i+&`= zj!SPlZS?f z#Ob-2{n|F}+30`cW}1D%rJcVx9^x~uH&foIg=*kOg7EPL(6#kcKzg-`$;dKrrRLkc_sd*A6_8V9UJh9 zyA@LErdRg7*mSRWtU00Jc%^w{5h&$_?IGf&*n@d}{!B3!tDk@I66UNbRlF+oyy6v1 ztm2jUkGH|wtoI*pt4h(gm6rduN}1D2wD1Dy=C85}1p0OCoY|>f7snnmn%3)*InsZz zal?Wa8?`TZv2jyfvSCwNTTZUm(0^UW_PR`lx$yWNIXP1@oStn5XSVM(puYdMJ8(*) zg7?>i)S&SF)-QO!?TfrgUBUXC(751I&GN6)^vSv7$4<^3onmgy{CC%0*DIqFZ^gX8 zPqSme&m+TJnf%K)GZ)LuG-o%cpXtAa4D-%7p%ZVdt=?L@!na^P0_I|)r%#$R%YRF{ zY(w60TZJYCSHOHg3*K_UJ88)K=ur5z6Mh1a8f!5JCtc~|C&>kKQP$UWcx*01*t*(0Zqbsl$Jq>Da53lK;Q|#w?@oinNm?z?qvd{~aK#z>qK2{?hB1fA$3X zt0n)U_4FnTUR{%R1=q>`GR?nG+rlf?0SgWEx&j=$^NgkiZz`kEA70>+Q3%rfEcC8H zQozC7BjjI!j6z)*hL_*!@ybGQ8J)Ok3Y~FlnV*Dz9xvFNCI8;2@TN6)P`WA^=DP4= zM&U=K$PL^?r*k9tcI+E$TKM5IA58y!)aRWQ-uM}Xw|+*Eo8R0*{wakwG`B-WJN?|b z6`B=XU-R+R)h)cA;wEZTczyhvKmTW4c#CHgxyg&%)Q!y*DRjuaTn1w7tL+;y$AS-( z5;vQ}TKs=CiXd&xz*t$S?Lr&i~Zne@5w8aJIPx^cD-R0k^UF2OXa`u{8yRVR%e-ee7#ig6EW`m^Ua;6z4w~te^fI3gFf9AYRD+$ zP#~~Sf%!~o-hS@5oN0LlpS%nhvGA2JV|GTJ;O8Za%( zeCEv?pEJ4tbUlVBa?=;y(&lRFqnKeHWB6Cp{7Tjf1t07T-+}!J6}ijK&>80TFT5$t zOPzZSOljY&S&Dt!oR*PdA34`+TEAgR&1u;av$JxuYo(-48Z~8l%TeZIn>{miQiBF2 zgbHdresYUHLj(396qCI>ZG(u z=8=4z(YaIVjG2;>IyNP>cm0%9^XReVD02l;$4tu3&CME{ojNgl^4Pp_E$f-&KOjl9 zKFk_3eex*#VM@(44}r}w*EI71%qrOahr)bP_g^T)ol&UU!u_8<5BY$Le6B1|YLw@{ z&B6zF)~)>*7e2--d}Np5|5C^|W$w3iwF++`|JOsoC&GOGnVJ9jS(=BIg^w%&W*-an z?$p2Fvu_3uBnuxD7Csg%d?;uhRGQoSfAfhP&jbCZ2l+o+|5u`YvEbJd4^RsqI~IB9 z$m7$($BF!+v=1Hq54ni@j}i0Vi+y0K$Ex`sJO5XH!N-$d=>@+^_(ftLpk7~a=gZ^J z!pDk*4;A_4Qedgzk!Zm~%z{UgMSfit{^}}xEC`*#M}h?;{D+fH=l1QJr_{8+65CFj zl+tn1$n4Rh&BO2kJo(N4#mSS}TL1GeRVUFrTfc06n6C=VNj6`rFkcra_+g*uw@r@D z3(j{J#M~Qj+BP#G%RXmz0_o;OuW4$}w4QCd_Hts2g?h%j330`PB?F}bW!$oXa)I)J z3W17&N-zV|Dd?QLT=dnheco8)hpR71kX-w;vB(eCJY_Ur>?!gi=oB-n zM?oq4VunqwW4>5b;j{VX|;Sbj_Uvn<mVNv7y%+v) zooL}OFS$+$$9#=C|7U4G#>LI`Z&l%`ETv;Pdo(}gD)wkDR8!sF=Js;ttKj)Z^R@5%qkX%!_t9~n zj^?WY`F(Jy670T3$L;19iQRj2 zyj0%b;R^n-gZV~-eSKdY7gqN7G9CAu53GItmpYcN=I^RH4zKR-@j9+EH-NqTb2^@^ z?e9NyOiT6m)jH;x8_Hh(Rvll-@b_LForeBS(y^1dLG9)H>$s??zaQ4|r?9$uc z19iN&ufJF7_(^|%f1_jhYy4e9#}R}5JxRyMhx&V~j;DwF`)?iVXZpLfjx)3Ty+Fq| z40QYPcwfih7=IVjvD-L*57P0z3I2XW$ImAE`?!u3bNpRP$B|S0oulIux&D4Z$6u!V z`+|-QXZpLXjz4O?-DxpxYgf7bbMf*zaQ1{&;oyduVbY<{ar`L z(F^@ORmZ0m`THdu&))0re|2npzrWk-IA@8!@6z$DrT+d%$GGMGE~R6y75*Nkv+_B1I&6lrQ?;a_&Z(4aj*G%x{lAj;qO;<{C$VN13Ud= z^IiV2vyOB3`1>9m-`?x*gE}U@=kIbl_S@(0OdXeh=nl*9QBV~b-e8>e=pYYon!v~RLA7w{;r_ofbadCrQ?bd z{@$qLu~Yv3S;y+9{oO#viNE-JmX6P#_4k`Po;Tm>v)9-A%|EvK!#{S{asFTazF)`p z%y$9pdHn&wO4b~n;-viaVj-8bsE z&3qHl?wvaRW4@bccgXy49(!zKzO87FJ$1a@e1FmIB|7di-)OY^u#UyecO31mtm9zw ztw+1FbzE(}2Wj`yI(}!q8EN-99c!EKO4{8-$0;fPzDdUy&G#wo>v!o`(R{Pd?piw5 zvq#TyT5I>vafps%bj;Opu8#NUxI)K`I&RZ(r;Z=$_=P>1_w$qX869Koxb-M^4M0;lD){^W}oE*?K2_`tN0; z{RWrbgt?YZ+9>l4nQZfQ{UYyX%(SdY=0a`z^-Rmk%bPZSFmpRA24YyXnN#jN=^1Air<)YUwu0!F+ z+5ECEczauQj=lZtkBqtjr)#4Bvi-k(U-rK@bmVfgn+BY2rtyQzy>CL%>$lrn&fezy zus;v`W3TzI==F=5>t{bM_TyK~{KwDtka^ks^ro0Y{*SZf?KNkZBk#)|v29;nx0!KZ zVkz@7Z_mDc`#y_&xSZj}OJCFY!P~Rv6un%Exqc_PkU4U>f~Szv({j>NQc}!!5E?hF zSHEffCg$aO^)ib5zj5P+DJe}G*K24F=EsPHTRQgWY7eDbFY_r>TKIC-GiNyJ9X*OrE959UAkTV>(b>e-Me(_eRfM?`4L@yeQ`>gKW`88 z{=Hqh4!w7s5ANJ`e)E)F=O1%+o!=cDI^y8@U=^qKg(Fvv3#RTm?^GE%&i;R0{{O$t z|NpSVk9B&nQ?Oct?&h-QDqT2o^n5hMUh3%ik~)^vv10yl@VK_l#ZM2KOC+C*CiglY zt!rNnHtcmiG5@6v?RuS$%YP~HTr{!Q`C#1xhpw-@GOm0e&>-eqNiXJH*|IaAaEw`^dHt_%7r+>~c_u?n^XZ`xgvuzW*Cv{8en%u?g zHyd;$wH&?CtYWZ#EzQA`G3^Xx7633cbzEx38<_3rf#ICc?bpvs4B$z{tmuT*$Vq!w} zuX}e(n;R;oXW5?iazU@Ud5yczUaEJw5&0?9)UG%$#oQ&u#D((zxr(4?zaSP93>`2R zaR-_UxOGdkwJ)zT@7k?ba)5c+TWrq{#J(LecV|I6Lcw5l?-_H6IQw^k)zF{wsBC72 z6RfFO$;|pru$JZ(W;QT?54~nZGaEX=I+_*CY~%#%YL+*%vH7d)G|QRU#0jQpmNm1f z6HM1EV`ek+r{OhAo0(y*R)%&dyUq2guU*n^bHy5Hm$2JhvxeHm?KW4fk#;e=&2?+6 z9kttBxhC2XyUn$0s-0}Nxq8jClk7Ivueo-j+4ar!yIMPJx4C{Tv=i($*RQ2^yxr#d zwbG8W+g!ia+9A8m^=qRYYqz<6ZM8kS&Gl=i9kknAzxLYZt77fyo9ov>JI3q==K6Ki zHuu@>8kpF#}GK<5kTp;INK zr>2DT(v*&U)<(z>ZG;TfM#wO2 zgbde4$hF!CxlS7)nc4^$p^cC%ZG?=}M#v~_gpAfkNVYaY#%LpCtTsZ%X(MF3HbN$7 zBjkE*Ur1Ni{;h%u+sxffu$wPrvALfLP7GN&R>&0ZoOxxwkf}OVLZ)d-NUo-YY9r(}ZG_Cz zM#y|^ge=fT$nDw)xkDQvcWNW#E^UM?)JDkN+6Y;sjgWh^5pu6KLKbTy{WSurb)@vi=F>Qow&_>AP+6dXGjgTj_5%Q!qLY~q_ z$kW;g*`$q-XS5OWtTsZP(?-Z#mM#%Hp2-&KQkZsxsc|qG3vczpL zHbM?+BjgipgnX)vkk7Oc^0_ub4rwFgur@-DX!}C8yMxT_pHSL7+zr0$3u$2=lY9}f za;%WAy+P*5X1QX4~gA5ke^&%r%S>O4?wqVlhGq8_abqPAG1J zxsoLa#cVLwvLqpDgSnce2oW31^(;+Dw!vJ{GK3@>%rz}bNHoDd!zo7y+hDF~c|w8> z=9*R@#M@x5X+=Vu4d$9&K?vDku4yGgtPSRxRwj5hm}{Cs2-;w-X%&L`hJOB2ohu13 zCfMgXRS5wb%r&h>FhG)n!I*%%!vG0CZ6BVv0bfxq`)Ky6K*;j4ifRSCZ_Jl$@)gzQ zd?~8KmZG|BDN1EaQ5su{(%Di}k1a(RY$>YGmZAo16g4EEs1X50jR`1fLO@Yd0*aau zP}H1&qN@ogYC%9zO9F~o5m3~cfTA`86tyLws2u@C?FlIAKtNGP0*X2jP}G@#qAmm! zbtU+UY6RR^^V>4Q?^-xDr6~U&eC!qoSzlIBuYgy>d;v0FQE$$dqCRXX>dTg*erze~ z&z7PAY$+PZmZEFeQZ$GyMT6NW8bUzPPy&jE5l}RofTC*&D7ub-qD%scMi5YxML^L= z0*XcvP&Ar=qHF?+#t=|6mVlyh1Qd-YplAXCMb{HhG?9R!Ndy#4Cisea1l%45NO+r> z!Jbky(UQsugsd;CC^z6uDlJ8MoG(Sw*-|uvEk!r5rD!Hwie|B;Xf|7lZe&Z*9JUnQ z#75E01QgvuK+#+Rif$#K=r#h1<`GadpMatT1Qgv)K+zop6x~Tc(Om=-EhM1mZUTxH z5m0mw0Y&!`P_&qUqWcIax}Sie2M8!yLhuz$4Y&^&AmLf&nRalR6g`#yJSz~gzO16< z0dK4MCTISA(ZifCMJw1+w301FtJqTX2wRF)v!&=!wiK;lOVL`k6s=>UXgvW%j}cI` zfqjCfY@>28$=S$I> zY$@8omZF_(DSC@7MZ4Hiw3{tOd)QL+Hd~7JvQhL70Y&c;Q1l)FMeh?(w2y$I4+tpw zkbt6(2q@Z5K+ypLiasWw=pX?_pAb;=DFH>F5m59w0Y!%hC^}3)(GdcQz969JC;>%Z z5`0Ck2HZ;K_Y8!G+xw!|q^Pp}jP_L^WPMph-v+$a=J#3V-xnR{d@1^lEk)n6rRWE? z6rEs8(Mh%xonlMTk8COWi7iE^*(my%fTCXrC^|zx(OCkD&Jj@bD*;8n5m59y0Y!fh zQ1mAOMSl@cbe@2szX>S%hk&9B1QcB)py*!$iY^gQbeVu6C#K+8zW*F8KtNFp!B=!F z;Epyx!iVke*!f0^j@$bpHzs6#Sw*23Z$V`#isO7Kif2nv0$Ym0Y$-})OHmSAijvt< z6k$tIlr2TY*eEJaKv4+-ib@htREmJ2(gYNhA)u%%0Y&8qC@N1tQ3V2uDiTn11p!5s z2q>ydKv4<-MO6qWx{`pRsst2OBcSLi0{2DL2`H*T@D+J6?o$Rx_&NIp#n>4CnSQDK zCu}hx>&q&t8{@rSMT$~6Uy9P$Qk2e?qIzs8%3w=TeYO-eU`tU$wiGpDOHpGsikc8m z)RcgtW&{*9C!pwR0*YD?P}GuuqE-YHwI-mb4FN@M2`FkuKv8=FiaHQb)RBOqP6QNn zCZMPb0YzO2DC$N)QFj80dJud?wPW0~21t0c{i0(XDa!vBv3kaYtS_smZ;V&0niTcp zd@1VBmZAY{DH_O@qHEYvG>9!lgV|Cvge^rw*-|u&jiTWM6kSU|(RBnAWfD*{f`Fnd z0*XcwP&A5wqR|8tWfM>|hJd261Qd-UplCb+MH2`px}Jcdi3Ai)BA{q80Yy0k6ip$Z zXez;1)H}v)Y=DGU+xwzEQZ(9rMw=EBvc9aM88P0V>QZzA=S$H{wiL}`OVMn$6y3;{ zqB(3Sx`{1CH?yVa7Pb`4Wuxd;0*Y=UplBWeMe_+LT0lV2?F1CvK|s-+1QgvxK+!@1 zitZ+$Xb}NL_YhEYF9Ai12`IXcfTH^eD0+Z^q9p_rJxD;&QUZz|BKV5(V%#|fNI3uB zRhuqFTkRLJm&JsvFRN%}jQ2=QDO$z(QuGL0idM6w=ux&5tzk>iTDBCeV@uI`wiG?a zmZA-86g^Hr(MAG_o*fQ1lD|Mb8pY^c(?2n+Yh|LO{{;1Qcy0 zplBNbMK2Ig^dbR8FA-3*oq(d32`GAnfTC9kzM_X?+_wyn@QQ$evqFl7+WVr{VnWuJ zRkS0Cgc5=QHy~UQIU2G}Z&6c7)Y$SOVMez6#dMWqF>ljbcT(hvjh~KBcSM40*Zbkpy+o3ivA#= z=uZNQ{vx30JOM?26HxRI0Yw)GD7r{M(Z2)~T_T|9G66;A_aUz|H>3HEy7^L#{cdc4 zfT9=zid+JUf&>(K1Ygnd7`K-J5*}gii@uYhf9!~LL)Mp7l;C-!2sI`p@*k_L+ViH)MTTMd_~hLWUI8<9sQ~U`tVbwiGpBOHo6%6g6T?QDe3g zHDOCpQ??W}W22}!0Yz66P}G8eqLu^{wIZOXH33C!2q z$ojI12DsjZ22wPT^QGt-wiFFwOVMDq6b)fZ(NMM&4P#5uaJCd(%a)?+*eJ>*plAdE zMOg$CjU=FG6aht}2`I`YplA#MMPmsl8b?6Ucmj$h5KweI0YwuDD4Ik-(PRROatJ7z zLO{_}0*a;)P?SqRQ69lp)X#NO8X86Q>_egcQuK}eLiThwWPMphvs|xjV=0==`BHQv zTZ-nerRXNM6y400qFdNfG?y(!x3Z<^HntSaW20z30YwW4D7u}1qB{sEx|4vSy9g*+ zNI=ou1QabIpy(a~itZ(#XfXjr_YqKZKLJG#5Ky#)fT9NpC|XKD(L)3jEhC_4IRQlv z6MRKCxb7GOB%J@xUC)%Fxt7!lH)MTTMXO!!j;2!dDCbMj8nzUzWlPaIwiK;rOVML& zDcZo6qQ}`%w2>`EPq0z+BmqTF5m59r0Y#e#D0+r~qGt&xdX9ji%>)!}A)x4a0*ba0 zP_&JJq8A7#dXa#lmk21@PC(Ji1QfkOK+&rN6um}3(dz^hy+QC5t#aK>21vMx{fzdA z6t%YFO*dqHSw*{C?*sEkVDrBlyPNZ+Xb)S8-eybDUbYmy! zMMnuJ`jUX6uLvmmnt-BX1QdNkK+(4Z6dfn{igvp0uLekXr+q;EmK064_eI~iA?wR3 zI_Y{P%-=1Pujmx#OVN*PDf)>mMW@+P^fOzEeql?|8MYLiWlPaHwiNx!M$vBs6#Y&> z(H{g9{YgO4Uj!7LC!pwW0*d}2py&btMHdMu`j>#BO9T{MCZNdt{%-$iJBk7X6vYrw znOMGNes>-b>E`m&0Wg5HqUQk2a3 zQWRlJQIsu3#n@6*oGnEq*iuxIEk&i+QdF8PMP=A1Doa37IRc8x6HruvfTD^76kS0; zQ6&P3DictYLO@X!0*bCApr|SVMb!u>x{83J>I4+kAfTuw0Y$Y4D5_0BQ5^z`>Jm_t zO7InhgYL}+NcawWUz8a1pXq;OA6=&fL)Mp7R6poF+E$7haK02ZWJ^&awiGpHOHmWH z6g6c_Q8Ts_HD^oF)odwh!A4O_0*YD@P}G`$qBaB+wI!ga9RWq{2`K77Kv72miaHTc z)R};yE(8>HC7`Gq0Y%*jDC$8#QBMMjdJ$06n}DJ|1Qhippr{|gS5z|hJd261Qd-UplCb+MH2`px}Jcdi3Ai)BA{q80Yy0k6ip$Z zXet3k(+DWaC7>vefTHOH6wM%@=mvtXXkgGy=wK8Lu-^f>MvC^>`=Xh_ko9F1%?WyS zI!Vz@oG(Q;v!&=3wiL}}OVO=tDY}gfpOF+?L0*dYt=4BKy~(1|JEAtS_r*ZP1(AMT*vOz7(xzOVML& zDcZo6qQ}`%w2>`EPq3xvNwyR{#g?L{*(lmXK+!V<6g^8o(Q^b8Z6=^-3jsyX6Hv63 zfTC>#6um$|(TfBWy+lCKb^?lCCZOmQ0*YQGpy)LMie4w6=nVpj-Xx%C2LVMp3BIC7 zgYH8HNI2Er7p;+^8|`Pbw}K(-%PM+1=)KfUiuQ886urZiqIcO+^d4J^-e*hEKDHEn zz?Py9*;4coTZ;CxQFMTSqK^qEI!Hj#Cj=CIN@)on!I1T375x#BO9T{MCZNdi^t2sC0RoC*2qTT+&uBkNQL6onmgt47FRLi(dF^{k zQ8CV!qT*~RD#4bbl58m|#g?MdY$+PkRSHv)>f6HwHHfTErR6!jvYs5b#ceF!M(OF&US0*d+*P&9ymqJacoQ3KC?)&L2& zjWci>O3_z#T;qkTFRN&%=Y7;)iiUB%6b)xf(Y0(Tx{fVHnQSQ`*6 zBB1CI0*Y1>Q1mFlS9Fu-Ha9@RgYDC@o24jf9~Z6hLe`g6^qA)j8!SZ|IA4k$XG_sW zwiG?VmZB%wQuGvCik@am(I&POJ;RowXW1xvj)0=g1Qcx{py+u5inbC^w2gqG7YHbN zk$|F?2q@Z4K+($t6um+~(W?X$y+%OM>jV_NK|s-)1QhKcplBxnMQ;&Mw2OeE-2`9J zI?tVJfP_D^&-B+z(O&bq;2tkzeOX2CdfwWhQuH3@OVRsmDcZ-Dq7T?o^dVb{K4MGJ zezp`HU`x@*Y$-a(M$sn(6n#oS(Psn{eNI5pAp(jH6Hs)7fTAx5C^||&(U$}ieMLag z*8~(DBcSLT0*byRpy)UOMc)xn^gRJZKM+uKf`Fov1QeYj_=@&=?%M`P*!*)6PVgNm z>TExw{pf|PFRSPm&pR<(iq3Gp6rE*D(K)sh{mPc2-`G<0J6nqWU`x@TY$^JSEk)inO0*Yb?C~^rX3KCG{5l|FMKv9T* zqBsJI;t429AfPBrKv5zAMM(q{B@=u_r#(0ETBFE*-!=HN6xn}vBN&MdSzlIBiC8Z+ zQ;JG*z7&;WOHpaI6qR91QCYSWm19d$dA1Z)U`tU&wiI2#Mo}dKiYgOOltMsJ6#|N` zB%r7&0Y%jaD7uP(qUr<`)gYj#CILmY2q>yeKv5k6is}+jluAHR8UaP=1QgXHpeTcY zqWT0BH6Zwkip9G943O}z_R)3mSpS*+Q2VsMVQk3yvWl9PkRSHv)>f z6HwHHfTErR6!jvYs5b#ceF!M(OF&US0*d+*P&9ymqJabyT|+?8AOea86MRLDW8LKj zNcc1RxTuK~6|-YVY{>euimr|IULGYy*KxiSWwNDc1Y3%-*itl-Ek&c)QZ$+^McHgA z8pD>Nv1}BLBcNzJ0YwuCD7v12qKO0)O(LLZG66+71QbmnplB)qMbii<$|ayEkAR}- z1Qg96py&nyie?f}G>d?u*#s2bNI=mX0*Y=T_=<+bx?dR};bZpq7Y&!9arsZ!Vnf!K zRdiddcR5>%=5f9h&1Xx|0=5+0&X%G(*iv*STZ-;tOVL8M6y431qD5>J-9tdpy#y33 zCZOm(0*dY@py&Ytik1*i^dJF6O9?1?h=8JH1QabNpy*)&idGO%w32|LRRk10LO{`K z0*W3bplA&NMQaHtT1W5|&5d=djWLQ^+XvLQN>NV!6Smlp^<@=pjP*K>lcFa$Uy7b& zOVLwoDSDbMMVr`C^bA{yo@GnXb8IQv%$A}pY!p3DK+#qLinb9@^a24zFA`An5&=cq z2`GA*fTC9jD0-EEqSpv0dYyoxHwY+tlYpWf1QhKgpy(|EigpoDw3~pUJp>fJO+e9J zg0E;ptUJK~30JZYs2`W2JM1^r-iZxaUsln+Snuu$QuG1mOVNjHDf);lMf=%Obbu{I zAG4+CAX|z)VN21cY$^JTjiS#9C^|$y(P09Lju24v1p!4z2`KuKfTFJmDEgX!qGJRU zeM3Oew*(X&C!pv%0*byTpy&qzicSzvbdrFgQv?+KNI=m~1QeYn_=?_(bvGLz;fQ@e z{k{~nw4c#_jtyB~R?)dw@4!SU`jzvg=r^_${mz!6KiE?ACtHgCVoT9^wiNx%mZE>y zQgnfhqKgC+{Yya6B?5{r6Hw%Y^t2sC0RoC*2qK~Wm!g(zDQd-* zqSkCFYQvVIwrnYC$Cje@Y$@u%mZFYq6m=q?s51dYT?i=ZNrqNxNFO(UQvmw=)?0*a;+P&9*pq8kV( znn^&>ECPyV6Hs&`0Y!5ND7uM&qMHdQx`lwExddO)bs_g110;N_eOi_&MXl|pw_8IY z>&q%y5b{nDFHj)@XPe9RQ1Qcx`_=@I*+~gTX(ONTu^QGul`^BTjLm}(SDtap9rO%Y2r#WAW zHnFAX8MYKX%a)?&*iy8aEk#?{QuI7qing+)Xd4?vFAz}lA^}A&5m2<9fTEWPD0+o} zqE`thdX0dh*9jtQ1m?kML!Twbb^4QlLQoaE2q=mnpvWblC`dq&M?g_50YxDKisA?;iYK5bfqlyY(J%svh7(Y9EdfQ>5qw20 z;@pV_NO+iq(^86#+WVr+xRCW_6^)AX?wKb=qd8xSve{BJhAl;7*-|u)Ek)zmQZ#`r zMc1>XXd+vRCb3a8nSi1k0*a;(P&Ac*qG<#a(UMKcK~nngg- zYyygIB%o*x0Yx_vP;@f^MYj-8G?##)TL~z-jew$g1Yc2Bocp{15^iN53XPPaI+oP@ zxRCW_72O%<9b6zqcX7THEo4j4-E1jZ#FnCa*iv*aTZ$I5rRYAk6y493q6gS0T0%h4 zg9H>UC7|db0*aOqP_&$YqK646T0ub3N&<>j5m5990Y$3`D0-BDqBR5*ttFsn9RWq_ z2`GAufT9fq6g^Hr(MAG_o*?*&ZjW=%8zABB0R!g_DH>u)JsB6WzO15W;=FQqO3|~N zFGbI>rD!u-ing$&=y|pjZDmW*HntSKz?PyH*;4cp8%5g*D0-QIqE`qgdX<2p*9a(j zoq(b@2q=1!fTA4)6zwFS=q&<@b`emtn}DJ{1QfkZK+#?Tiryih=v@Me-XoyseFBR1 z5m592!B_NjoZHF(3HLHHxJioQ>}RwO<3iS#RrGP3m$^`i4syN}eZrQaPuWuR8C!}z zXG_r`wiF#^OVJUw6n(*#qN8jSeMvykR|FJ&O+e8x0*byNpy*oyijEUd^c?|3-xE;u z0|7-R2q-#9K+!1zihd-Z=qCb-P7_e{GXX`v5Kwf6fTFVm6rCfW=vRWTXn&kL-vBXp zJ_gPK6xoN`zr}^DFRSRUIB&xuDLT*jQuH@livD3s(FL{?U1UqqzicVG#FnDVY$MGXlkYD7R$V*-kr5Kz>VfTCsu z6g4NH=xPFrS`d6i<>TGxVxwqDtbtP@-hZaQ*N&F)A?wR3Y8&rm+%HA#IA4m|v!$p5 zTZ%ferKl5IiaN8Us0&+)y0WFH8(WIHvr*K8fTErR6!jvYs5b#ceF!M(OF&US0*d+* zP&9ymqJabyT|+?8AOea86HqjSfTE!U6b&PwXgC2y*Ah^49RWp|1Qd-RpeT#rD{39@ zUSoiSd)xb>Hd53({|Q@s$ojI1#>9I!ERmwIoG(S=*itl}EkzU9Qgl6AiYBt9XcAkB zCbOj|hb=`@*eIGxK+!Y;igF1k$|Im?Isrv92q?ONfTEcM6wM-_Xf^>wHxf`Zhk&A+ z2q?OlfTCLnD4I(^(X9j&-9|vsJOYa56Hv5(fTG(8zM|3b?kWQ$oM!KSvZbh-{mn*q z#D}aetLW}{@Aaipw21Si=pMEd-OHAu#cV0Mk1a*_v!&<(wiGR4OVNXDDO$=#(L)3j zEhC_4IRQlv6Hv5*fTEQI6s;nl=n(>nRufS4C;>%l2q;=hK+!q^iq;cQ^cVp}8wei(bEK9(OvQGw+2YKqnW{lQqn z9Rw8ZB%tUm0*ZDKP_&zXqCEr@y-h&TUIL2VA)x480*c-vpy+)9iuMsu^Z@}y9}-aX z5dlT}3BICdKv8J|ipmgBRF;6Eas(8WC-{oa$Gh7MkZ@P~xae;wT4wKyDkOxg zFRQ3>g7@iaDN5mdDXPMjqAS@_RFy47)!0&W6^?y2`EY6V@|#DGIQqD26RXE?bI% zY$@{CQWVRUq7WNJaRd~_6Ht^uKv9^0qC^6Uk_aeDCZH%nKv9%{qGALT6(^vm1OY`Q z2`DN>Kv8J|ipmgBRF;6Eas(8WC!nYT0Yw!FD7u2+E4q;2t~NlzU)oP%7p3SS^SWTA zaLD?yimnWMZ$2wURXJaZs8HwiMN5OHnPh6xC)+Q607v)n%h7m4Ko& z0*cZJD5^(5Q3e4;^$93yKtNGL0*V?DP}G=!q9z0sH6@^^839Gj2`IXnfT9)z6tyIv zs1*T4tqCYcN(xo@^=V#g?MpY$@u)mZH9F6!jyZs6PQk0|+P@NI=mw1QZP- zplC1wMMDTE8cIOXFanB(6Hs(50Y%plP?SkP(Fg*HvIr;|NkGvk0*XcxP?SwT(HH`X z#u9u*9m8&I10|cmn}tkY$=+~mZBMK6x~2T(M$r0W)V;{n}DJl2`HLFK+#PE6x~cf(JcfN%_X4d zRsxD{BcNy=0Y&o(C|W>3(d`5j-9bRnodgu!ML^L)0*dY?plA`nS2Q8)PBB2jkJ@kJ zUoS>blR;gI!Z72O~9?tejw9^iZ_TEdp12ia1zlr2RMv88AkTZ)#mrRZU{6s=%O z(MmRoRuNG22mwW_2`GA$fTA@76s;woXdMAX>j@}&jDVsI1Qb0^K+#45ik={#=t%;K zo+6;=X#$Ei5m59D0Y%ReQ1l!DMVkpI+CuOZEe^Xc8X(~#_B$Z=NztA5Gurdvko9F1 zy%_dBe@Tj7;(RIE&X%H=*;4chTZ&#~OVMj=DSDkPMQ^aB=uNg1?O>y5Cjmuo5m2;? zfTG<56zw6P=xqXu_7YI^4gp2)5>WIW0Y&cwk!g)c8&e;2+&%+_>%PRUJ>|ODS6dmP!Df*Hv zMPIR{=xeqV9b-$;H*6{TmMulc*;4c!TZ+DCqv!_$icSzvbdrFgQv?+KNI=m~1QeYn zpy+1;ihd!W=nMfxX9*}eM?lf91Qh*7K+*366#YR!(Vqkq{Y600c>;?5CZOma0*WpW zd_{-DZaV`coRVnZ9Fd}%EUAm(ko9F1If>q=*Q6+rsAuw06vLJxmn}s>wiJ16DT-xF zQHU)?acn7yXG>868%1FPiV_JZN+O^rnSi1Q0Yy;)ii#0XRGfgK5(E^LB%r7i0Y#+= zC@MohQCR|t$`Mdho`9kX1Qb;ypy&z$iYgIMRGEOH6oRklQrNxI015wWzv_5dit3x! z1*;^6tS_tRszmR}H>9XK=SxuywiMN5OHnPh6xC)+Q607v)n!XjDqD)u*iw|vMo~Qi ziZTc&s!u>s0|JT~5>V8LfTG3(6g45Bs3`$O%?K!JPC(Js1QfL(pr|DQMXd-ZYE3{< z8v=^j5>V8RfTH#U6m=k=s3XBwR5j84&;SXSvG+yQ68&fT6Yc1f7_z>sqHc-anH^Hp zo%5xr2V07IvZbgOTZ($KrKk^Eiu$sps2^L3`m?2I02@UE2`IXTfTBSJ6b&YzXb1sC zLkTDvMnKVU0*bCBpy)aRiZTf(8bLr&76C;g2`CyxK+$Ldin0kP8bd(QSOSX15l}Rq zfT9TmUs0Dtx8zQv$g^K{>?%d}FPsTppBS>ftfHJmuhA|kn!@=~G?gty)7Vm!%a)=% zwiHcgOVJFr6y3m)!}A)x4a0*ba0P_&KUD|#T&U1NZRN7=7BE|H?Y?06wDWPMph zFDH6C_e#+#oG(SMvZd%XwiLb2mZCSi(2M8$on1G^#1QdNjK+&fJ z6n#cO(dPsd9U`FUFu_;!Qlk5V0TRB;-u-NsqDtm&q(o%KUrQ?@7_uoG(Sk z*i!TjTZ+DAOVM$*6n)2*qVL&K^aERpPOzouBpXGi2q^lIfTEuWC^}6*(a!`F{X#&| z83KyV5>RxGfTCXsDEf_nqTdN9`h$R?KM5%Mi-4l@1Qh*EK+!)06kQ;o=pq3{{}NDi ziQp?bn&{RwK*DA0R~^5UqJH+7{^i7w^<@>gNnX!=QWQ-3&u97`TZ&@YQWRoKQ5;)} z;@MJ^z?PygTZ$6dQk29-Q8EEV5dw;$1QZn`pr|+jMI{I*DoH?5DFTX06Hru!fTFSl z6qO^Os5}8h6$mJ*NI=mQ1Qb;wpr|qdMJWUnRUx40N&YCmZDU)6s57HD4i`u_1IFB!Iq-> zY!o#hpr|1MMU4n3YD_>;69S5w5>V8PfTHFE6kSa~Q40c!S`tvyih!cl1QfL)pr|bY zMePVEYEM8>2Lg&Z5>V8MfTGR>6m=o^imE5M+YOL#EeofH6pgl@-nu4*tS_smXOee# zzZCW2d@1V9mZCmvDeB9XqJC^C>d%&<0c6b&JuXea?i!w4uE zPC(JM1QcCIKv5BmqUE2q+p&Kv6aUMPmpk8cRUYI0A~s6HqjPfTHUO zD4Iw>(IkSesC$xo$p8tzY43}ANRjvT?7;@B%tVS0*V$9P;?IgMfVa=w3vXR`v@qypMatV2)?2zNp1%N zB;3jVCfTV{^nkrDT9Op9zO15UNnZA+QnZ}&rRZU{6s=%O(Mq-ytzt{jBWx*J&6c7^ z*;2HIEk$eDC|XBA(Ru=k9wVS=0|7;k6Hv5~fTAY|D0-5BqNfNbdYXWuO#~D@LqO59 z1Qb0-K+$Fbinb6?^gIDYTL~!IMnKUE1QfkUK+#JCU(wPeccB3i{=|OO@gXVt&OX!M zo)ogatfJSFyr(~xqSrZJir!#L(VJ{3+QF8hoop$3i!DXF*iy8cEk%3SQuH<(MSBS- zdWV3bcL^wZkAR~02`Jh}K+y*T6n#iQ(MJRn?I)n<00BiG6Hs)JfTB+bDEgFuqR$8@ z`ka8GLj)8ZCZOmD0YzUBP;`{wD|#i#-EV+|8{6M^{i+nTwBG^wGAU$zSw-I@dFKvG z(YKs0MaS7v^c`D@zGq9(4{Rwq!Iq+vY$-a$mZBfoQuGrWMW+cU`k8>DUkE5VLqO44 z0*cNNQ1mMSMZXbH^g97Xe-KdgCjmu&5m0oVfTF(%DEfzhq6-8RT_m9BUjm9Q5m0oQ zfFdVZPs~viAoz;DPI5~hF^YEB`=Vn~)YX1Qi%AYyUsh3Uve)FO6ooinisIN(6wj8T z1hy1~*;16qmZBuK6eY8zD8iPaC>uq^2q-E}Kv4+-ib@htREmJ2(gYNhA)u%%0Y&8q zC@N1tQ3V2uDiTn11p!5s2q>ydKv4<-MO6qWx{`pRsst2OBcSLi0*a~=d_}=zcenu( zj5Ou%)OzTZ$U6 zrKllWiW;#|)R=&xCIl2UC7`Go0Y%LTD7u<}q80=cwIraZ6#+%92`FkqKv7!)irNuS z)SiH%4g?f+B%r7h0Y#k&DC$B$QC9+rx)D&+o!~2~mF%uFK*9&?R~>6hQ7cQTM{>ye zvWog7d%KQFQD4rNqJC^C>d%&<0clXPQ5FG3BMB%PML^ML0*bN;C>ldR(O3eC#t~37o`9kW1QcCQK+!}3 ziY5_IG?{>+90H1_5PU_wlHHRANI2X6zU$snG|@h~o|+u8zO16@$zJ?%DVo9gQgj1b zie|E{#Ek(DmQ8br;qFV_lx{ZLMc?1;AC!lBn0Y$eH zP;>_YMRyWVbQb|d3kfK?n}DK41QgvvK+(Mf6fGv8=sp69?kAw=0RoDa5K#0W0Yys* zzM|Y@H_ZSEueA3?c~Vs0KDvG=Ib?lVMJtlM-rq~nO3s&}RctAGge^s@*;4c zrRcD|FM2gOWPMphZzg+7Pe{=Y&X=N{Y$-T{fHnW7viYHwpi^_clGMPsT5Hyo6rv7BFu z#<8VnJX?w;u%&1sTZ)cjOVK2@6dli&qRDJ2I)RO%6A36PAfV_Z0*VR=D4Ie*(NqG8 zrV&t7L_pDW0*Yo3P&AW(qFDqK%_gAeWCDuj5KuIifTDQ>6crOtG@pQ?1q2k85KvS~ z2o;U0?!V-K#7pdJ*Q2GVwcQt$Rgal3Q?$5x@Z%3sw1o3Z(NeY)oywM?Wo#)rjV(o| zv!!S`TZ+zLOVJ9p6rIUN(Mke}RuNFNnt-A;1QeY`K+#$Piq0mWXdMAX=MYe|o`9lr z2`Jh?K+#45iZ&5Yw3&dS^9U$9pMatZ2q@Y@K+%N+6kS9>(N;pJXi;^)-j7bvyY_{~ zQ>3VhecFF<^_clGMVD3&y8bLhmvMe6+QF8h%h^)2lPyJ8u%&1hTZ*n^OVMt&6kWxZ zqN~{`x`u$FYY8a2j)0=;2`Jh_K+z2Z6x~Qb(M<#t-Aq8yEd&(ZND7u#rD!Qb)f1(2t?_l>u+ok9>`x4}R)nn$% z6g^ZuSpKUNJB)=s5z4 zo+qH_1pie4q4=rsb0UMHaF00BjB5K#0c0Yz^SQ1mtdMeh($ z^ezEK?-5Y+J^@7^5K#0XAyo80b^l5SBtF1CEqhRk7TbN%N7ZBI%M^W9J$UptDf*oA zOVJl>Df*HvMPIR{=xeqVeZ!WbZ`o4x9b1YHvZd&IHi~{Apy)>eihd%X=w||oej%Xf zR|1L-5m59S0Y$$PQ1k}@MSl`d^cMj|e-lvj4*^A9LZ7yyC_+F{8UaN<0Yy;)iUI

x*32)w*au{Rsa^=2Ed}*0a$bg0E_MfV9{LwEV>(jMfU)( z=w1L8-3P#;`vF+=004^~1jH7dA13!OLGqsQk^Tj;sFy4CP?&PR+@i*47QG6< zqSpXe^f~~G-T+|Hn*c0&3xGv$1F+~F02aLqz@qm6SoA&si#`Bg(T4ym`UrqU9|N%H z695){3c#Yz0I@}ngvonNki6|(oJVERSU;kD9;Vzcx9ICId~X|B^bPaNqHoEv=sU73 z`kpL{ejv-DAIY-lC$cR1nJkNbAPHV9_4{Ecz3GMSlUX=x+cP{R6Su&6Tti@E?} zi@pq#Iop~=%e^o9N*2B6!~V5$Qtp>q)Ga4muSFJhXMS1KgDi`Bl4VgLSr!$MWl=A( zEb2{`MSaM!s4rO-^&?|Ze*hK@0ANuu0E-3!uxM=n7OexoqCo&G8Vtaqbpcqk9srAm z0I+C%02XZkz@iNSSTq!XMZ*ACG#r3MB>*fM0l=bC02Yk|V9_W*Y*Btrvc?3-d&bYM z3v%L-{!kzGkIqTCUvAO3oN)1MSu~#cWzoiDS+ogR7EK__qKRZ#v?*B@ZAO+wo0DZx z8Ce!hB4bfG0E;RBSX2qXqACCuO$K1m6aW@g1F&cd02WOJU{MVKi>3jvs1|@lbpR}? z2Vl{302Va>u&5D$MNI%KY6f7@3;-6*1YprDKy1;NoaFH)NS^;+qS<3*QJ#k_b5ib? zTeNLXc*7i7v>o%yq873&+MXR)db1A%RgVVjV#*Vk7)bkq}(sJ=zyH?w^mtn zAoI(jgUGVzV6rSage;3zlV#DNWLb0=Sr#2mmPJR9WzmsjEIJB+MMnd$=okPN9Sgvs z;{aH6JOGPM0ASIH04zEQfJG+*u;>&37M%*fqSF9abUFZw&H!N1nE)(03xGvu1F+~E z02ZAKz@qa2Sad!hwrIbcWdC_)QHh^W?=OoML<6>*l>6ltU6K=Swm=qL%KWnEGO{eX zoGgp3Aj_gF$+GAwvMjoqEQ_uo%c5(^vgkT87F`d(q8k8MbRz(ZZUSJ@%>XRA1%O4j z0d02bX2z@j? zEP4bGTXa!Qa;^!I_m_7+7t5kuJv^F|a=+Z7Cv(Dsca%j>F~2N&nkC`f78jztLo7G(jjC<(x#YycL804&M@ zU{MNyMY#Yh>Hxr^JOCDT1Yl7o02XxyU{MzU7Oe%qqOJfe$_K<2eUp>?)&$9W+Pj}` zWzjE53k9i^`{fq(OojPNWlqHpDc?8kY!OZ z8H)x2uxM=n7OexoqCo&G8Vtaqbpcqk9srAm0I+C%02XZkz@iNSSTq!XMZ*ACG#r3M zB>*fM0l=bC02Yk|V9_W57L5jA(MA9)8Uu(e>YhrDF+uX0eWc$b6_50L`$&ImD&>B; zMVq9;nLEp(3Cu5xCX!{*res;P8Ce!>PL@SwWLY$cEQ`v?vZ#VAiz>-jR0Y7I$p9>x z0>Gkb02XZlz@n)DEUE!u(KG-S)dH}n4uD1V04$mgz@i2K7BvE}s0n~Y%>XQ#0l=b} z04$mXz@jYyShN)Yi?#;D7L89O_cB59>^~c}|B6o*edT@8HmQ{Rj72*EuxJqgixva0XbAv|mIAP7 z832oR24K;002ZwPV9`nd7Oetc(JlZi+7*CBy8*ChcK{ac0l=a?0a&yb0E_kpV9`DR zEZP@9m64)9@Fi!3Vf!`uF;l>6lt9h?e3SS5=NVSZV(nkj02ZAOz@iHPSacx(i!K7h z79E&M=I&w^{a`WsAX)T`pK4#6O1WQd(dDUd{oQ2I70fS-t|ZH%tH`qGYO*Z4hAfM& zCCj4g$g=2qvMjoREQ@X=W6@0jEV>zhMYjO3=vDw0-3Gv-+W}Z~2LOxi1Ypr!04%y2 zfJOHJu;^X@7TpKHqWb|@^Z)>h9t2>~LjWv#7=T5O0I=v$02Vz4z@osC z-iCei{7QG3;qPGB8^fmyC-T`3Iy8tYD4}eAQ1F+}=02X}+z@m=; zSoARfi#`Eh(Wd|``V4?Yp98Sy3jh{<3BaPS09f=j0E@l>#1=i3N}gzf02bu}u&4t7i}CIT4~?ts{$?^DUwO_01@{DWyf$fCurRFB-0`{fq( z$_@Y6M;7&Fep%FqEQ|V*Wl=w}Eb32|MFYsPsF*B^29jmb+GJU@4jGFE0kCK=0E^ZI zV9|O2EE)p9qV)k-v;hE%HUwbNPyiMU17Oi`02Y-1uxJDTi%J1lG!lSCqX1Ym8h}L` z0kCKc0E@-~uxK0ri^c5r zmqnYCWljOWqf?b02ZANz@jq%Sac=;i_QXI z(b)hjItPG7=K`?kJOCD*55S@e09bS(0E;dHV9~_@EV=}MMVA6%iw?<6es6;01^zQ3 zt7Xv`SL(9dl>6ltU6mVlJ5&~3&HS?H8nP_9mMn{|Bg>-e$+GAMvMjohEQ@X;%c7gf zvgj5v7TpTKqT2vibUOfx?f_uXod7Jl3xGv;1F+~G02bW~z@qyASad%Ciyi=A(Srai zdI*3;4+F615daoF3c#Yr09f=m0E?agV9}EREP4tMTXaQka-0d0cdo_kD`n9fKcYRI zn{vP0qUUqNEf1GPFEGC>dXX%PULwn)m&vl|6|yXPl`M;1Bg>-K$+GATvMhR&j74t& zu;^_77QF+&qIUsU^d10<-UndO2LLSk5P(G=0kG&}02X}$z@kq9So9eHi#`Wn(H8(L z`VxReUjeY_YXBB~1Hhth0a)}M0E@l{#1=i9o7~3)v3Jo-oabcGAATYGhuoC=>TK?jZ7Wl@5RMOgqWN&>Jb z8-PV20E=<}Sd;=_Q7!0KlSd z04(Ybz@i=iEb0lsqC!Ay(NDR_2ThQ?`@Q@5Sr%>Sp{PU3{c?-?b_hQ@S{C(Vep%F? zEQwgUPaJT{0G}2f(5s04!P`fJGYsuxLX777Ybp z(J%lO4F_OR2>^>m0I;YOfJGw#STqWNMWX>&v=IP{#sIKrEC7qf0kCL10E;#TV9_Q3 zESdm_E$ZDNnRkp?bYPB&)2Bl`(!a&S#11L<%PlJF5N>#!ESkjpvZ$Oaiz>*nsFEy; zs>rfvGFcW)A(EtL91`<$oEdfP? z2q+p%K+zBaiiQ$UG>m|v;RFlvXQ3k&q${Tg;ojLW;(5z7&mTOVI?j6isAH(ImDMO=e5c6t)yiWlK>OTZ*Q!Q8b-^ zqHF?+atJ8OC7@^q0Yx(jD7v12qFDqK%_g8|4gp0s5KuIifT9}-D7uM&qIm=q%_pGf zW&(;95Ky#`fTBeN6fGv8=oW&nXiPEpegh<2(cb-JN>MfQFe$jCSjhUaif$|B?Yd8j zmUF%o-OiSxJJ?cmCtHf{VoTB8Y$>{jEk!HXQgkm{itb~h=zao<9w4A-B>_bb5>T{? zfTD*8C|XTG(Zd83JwiayqXZPKA)sh20Y#4yP_&MKqV)t6Z6KiNaRQ1q5>WI60Yy&| zP_&7FqNfPHqNT;$69!250W*Wkr07BWn~gRX3t3-Q(bi(#Kjsbc{=VyNoG(SsvZZJ{ zTZ(qDrD!Kxik@Rj(Jr0Y&=>D0-cMqBjUAdXs>nw+JYDn}DKs2q=1&fT9Bg6un14(fb4x9VDRW5W!cp zrI=e~rBSrPexdOhDJpNj9dfu>$ojI1J}Tz5UnNB!bG{TEWlPa9wiJEBmZIZqDf*Nx zMJL!&^ch=)x=_sBVt|C3*~dkHNzoE}UsOIEvc9aMN@4Hd zBT|&Y`BGGwEk#w>QgkI-imI}u=qk1pUCoxFYHTU0&X%GYY!uZbpr{rBMYRbiszX3g zT>^?y2`H*ZKv5b2MfC|NYCu3yLjsB#5m3~afTAV@6g4HFs2Kr8%?T*FhJd0L1QfL- zpr{oAMXd?GqASAgZw5&C6MOelG3-Cnf8LHZ;gI!Z6?F)ECD%$(N6wd`PHZXa%$A}q zY$@u>mZENKDeBIaq8@B1>dBU(UThTgCZMPf0Y!ZYDC$Q*QGWu81`tp*kbt6V2`Cyw zK+#|ViiQwSG?aj%VFVNnC!lBq0Y%plP?SzU(MSS{G6*OdML^ML0*b~Ed`0cTZgT@9 z{Dhgo_EL1wj?8e#`m%~9guP+wq-Y}NOVK2@6isGJ(G<26O=U|_7F&v@v88A_TZ*#T zQk26+Q7!>RGYBY}NkGx{1Qg98plCJ$MRN!!x`BYAxdas5NI=m|1Qg99plCh;MK=>r zw19x3g#;8WBA{q70Y$eEP_%@AqFV_lT1xO0jSIW;4Uq6wd-pS5iemON+OlxS`m&1d z2zzTcNYR~~FGY8;rRZ+96y3v?q7`f@x|c0Q_pznuezp`nz?PzwY!p36K+!4!iXI}M zXf**v4--)I2mwWp5>T{;fTFbo6g@^j(K-T())P>)fqGdk84nOF+?U1QhKfplCk< zMXwW3^acS%ZxT@S76CEBB1Cn0Yx7WP;`Xg zE7}%zWIV0Y#??C^|zx(f0%t{Xjs`j|3F` zL_pEc1Qh*3K+#zOip~*Gbe@2sUkNDsjew%x2`Ku5fTBMMD7rxK6@46b`xzkN0T#|t zDe7lGz5NvqSzlJsKVdItvlRWy`BHS5Ek#a5&)lUbz?PyowiLN+DGIWs$YV=U5w;YC z*eEJWKv6LQioygGMF=R0C!i>SfTBbKilPJ*#Rw=$BA_UlfTH3A6qO*Ls3ZYJr3ff0 zO+Zl@0*cBKP*je9qVfb3RUn|~3WBfbV%S}2fP}BI_eGba=(KrVuwo=+eOX0SBHr^` zr07b{m!hg{DY}X+MOU+>s2W>}sF#$zQ2q21xh{`&Gxv5&xO~J@&q+eI#UkSw)>A-sP=Q)P?hPaZfTH096pbLD=sE(5(g`RUNkCBs0Y#$-C>l*b(HH`XG6^UeOF+>$g0HA!#I3r` zDEixe)v=QleP&)493Kf;UsloNh}Utu6iwlLDVoZbqAa!)O=C;ZbhZ>_v!y79Ek(I( zDVo8SqM2+IT~9#KECPyV6HqjVfT9}+D4I(^(TxNY-9$jqJOYa56Hs(B0YwW4C|XEB z(INth786i(3jsw-2q?OhfTE=Y6fGm5=r#h1mJ@tM6C>_K10+1xej9(16z#WnOt(iu z)|XXucf`AGrxe}8`BJokEk*aTrRYAk6y493q6gSgw301F53;3b6iGZS?2`Ku7 zfTFVm6rCfW=sW>MzYy%8@-Q6OH=}4scZ(bLy93Qg2tfH&p zy>+ih(bb$UMb+3+RGlqFHP}*AlPyKH*iuxREk$+MQdE~MMX78Q)gz!Njew&11QazO zpr|1MMU4n3YD_>;69S5w5>V8PfTHFE6kS6=Q40c!S`tvyih!cl1QfL)pr|bYMePVE zYEM8>2Lg&Z5`0Bh#=CDBAmKCizNl)v|4hGCycwP1L)Mp7)GgjSvqy@$bG{VyU`tU? zwiNYZOHpsO6!l?CQD3$c^f3_42V54Xt0Y%pmP&9~uqQL|d4I!XtC;>&o2q+p( zK+y;SimoG|D4l?!kpvWF5KuIVfTGa^6pbOED3gGqu>=&2BcNzJ0YwuCD4Iy{6?KVs z6ZaZLgY37?x=PVI=5@hI@geKWD$0uYQuj&GG|rcz>1-*=W=l~HTZ(eoQZ$1tMKjq_ zbUj;&X0fGcHXB8A2q?ONfTFns6x~Qb(M<#t%_E>_J^@8H6Hv5(fTD#26fGj4XfXjr zw-8XYgn*)32`E}hK+!S+if$vIXgL8zw-Zow2LVNQ5`0Bd;@trTNca)^fO@JFZMEaB z_>lEw72O-}&3Ijk?&EwZx}PmY53r?ZC0mLfWJ}R1wiG?YmZH^cDSDVKMUSvi^e6#E zYX~S>OF+?M1Qe|!plCe-MH>hxdYpiwjRX`uK|s-y1Qcx|py(+AiZ&Ba^fUoQTL>t6 zhJd221Qcx}py*iwinbF_w1eO)x+mUUWq^eH+uwJ+LW(}NV`qHG`m&0ikM~}DQ;J^T zd?|X7Ek!S}rRZh06urWhqF32cw1+K4d)ZR-8e59?u~D?2fTGt4D0+i{qBjXBdW(Rf zw+SeEhk&AY2`D;1K+$^y6unPC(Ln-=4iQjvn1G@W2q-#2K+%T;6n#WM(Z>W79VMXX z7y(6}5PU_u;@y)5NO+mO``Il;70v5{$KylRmsRw6ycaN^@)q#@geKWDsmIN&IhC@nDC#^^gXr|6=6$Jh%H4$*-})DEk$9r z6h+ul6wj8T1U8Bi2`GvZP!uDeD2afgWCDtc6HruwfTEHF6qO>Ns5AjZWe6xLOF&UM z0*cBLP*j0{qALg}sz^XlB?5|42q>ydKv5L}imoL1iUJAlWCJ9;(ZY#K@SmdaeA#E?bIH*-})GEk$W;DXPy#Q3C>s z8WK>{h=8KT1QazPpr|PUMa>8(YED4WH3Ss3AfTuv0Y$9{C~8eWQ5yn^+7eLIj)0=} z1Qc~3pr|7OMV$yJ>P$dU7lNIC;$10-C-!l@=jBkZTQt_dOQ%PQ)b;2k+6MZGv* zih8r9s1I9;`m&{{A6tt0v!!SNTZ#sL$s$pjQl zA^3{AC%6|3knm0RzNm*3CEBO`QxihgmsOOV;FUchMLC==MY(J#n!%Q$nQSS#o-IYQ z*itl`Ek$$KQgj1bisrIWbRz*pHxW=YkAR~21Qgv&K+ysMiWU-3w1|MB#RL@HLO{_H z0*Y=WplB%pMau{%x{ZLMrjI(tg!( zx)iOj_eCobLe`g6^gx1_{*e@|E*XbS;F&k#_w zm4Kpc1Qb0>K+$#rigplCw3C3M=Ljg;Mer5fm*6fkK*AO5?{&OiiuT!O`nwZC)|XZE zQi8YPs1&`-`BL->TZ&#~OVJ*-6zye8(Q9le+Q*in{cI_Eoh?Oguu=3T0Yz^SQ1mtd zMeh($^ezEK2M8#7kAR~02`D;9K+z!riVhP{^Z@}yM+hkTkbt6(2q^lPfTE)W6dfa= z=o12pjuTMyDFH<%2)?2h65MwTknq*^_g%jzMbUUOK1&E$UslnV3EmH%NYPiEFGZ)= zQuH-jioRh>(YI_V`i?C{r`b|;hAl(H{g9{YgO41p#B%LEiTiF#s= zq5#2H^hJUjJ8l#ewf99QrKp|#j24#|vc9aMB8gtw2`LJ3z7!Q@OHnbl6ouJR6k$tI zJX?wq*iw|pmZB(IiehXOB@s}ROh8d_0*XoyP*jqDqEZADl_sF53;{)D2`DN@Kv8)D ziYgFLbOixL6$vP+L_kpr0Y#MwD5^q0(Uk-gRVAS4DguhGCiseiiSD%qNH}2Oc!~Zq zee+1$JYh==SzlIBtwito&!wm~=Sxu?wiMN6OHnFYit4eYD2**e_1RL?fGtH0*;3Sq zjiSZ`6g45Bs3`$O%?K!JPC(H$1QfL(pr|DQMXd-ZYE3{<8v=^j5>V8RfTH#U6m=k= zs3QSIod_uEOh8c=0*bm4P}GfpqV5D=QH?}*wE+^|YrpDPQ;M2cQautw)|XY(C((QP zq!jh#d@1V3mZJV_DH_0*qJeBFx|S_PgV<6um@P#^*itlljT(P#pS#t=}HNkGw90*b~FP&A%^q6q{PO(dXb5&=b%2`HLEK+#kJ zin0hOnnv&y^-6TVGC;!Z!Uj%nDH?7cT~AL8SzlJsj6}~pB}FqiUy810OVKR06wPK! z(HyoE-N2Tjxoj!Aku60xv88Ap8%6U8D7u+|q6GvLEhM055dlSu2`IXSfTAS?6x~Wd z(NY46mJv{N8v#Yj2`IXqfTBAHD7uq?qPqwvx|@Kadk836K|s;H1Qgvz@D=4Gy44Mk z@NM?KC|8Pt_R;nIi6QIDDq5B3b^S()9^!l{TFsWChuKo}2wRFCWlPZ-wiK;pOVML& zDO$&tqV;SPZ6KiNaRQ1q5>WI60Yy&|P_&7FqNfNb+Dt&v(*zW4A)x3P0*ba0P_&JJ zqGt&x+D<^x4g!jH5>WIU0Y$qADB4Xx(enfpy+H64txR;M8X)0J`&GvWrD(UkFM2UC zWPMphuO@nTekVnHIA4nPvZd%XwiNASOVNI|6ur)tqBq!5^d?)1-eOD9+iVoQLqO5H z1QZ=0py)jUiry!n=pX?_hX^P-OhC~G1QZ=1py)#aiasKs=wkwkjuKFGjDVs~2q-#E zK+&fJ6rCWT=raO}J}02)3xcoc>$qLy}?Obl6HR?*jq-bZJo=o`+L zqHoz!^c`D@PP3)x3|or6XG_r!Y$^JYEk!@ErRZliihd!W=qv$6=Lje|Pe9SH1Qh*7 zK+*366#YR!(VqkqT_B+7F9M4GCZOmd0Y#SxDEfzhqJIe}x=cWk6V=mp6a@$us@D+WP=>Bbhgv(esr=;i|JG^Mf`m&0OMZNMrN>P~er6|IdqIk9xC9tI^ku610 zwiLzKQk2A&qGYxd6=$QU1OY`Q2`DN>Kv8J|ipmgBRF;6Eas(8WC!nYT0Yz63P*jnC zqDll5r4Ue5nSi1y1QcCKKv7i!imoD{=xPFrsu56Boq(bm1Yc1o>b5aJ!dvWjK#E5F zXZq*u7msR2L)Mp7R5$8n{47POoG(T7*iw|nmZJJ>DQdu$qK0fKYQ&bJ#%w8S!j__@ zY!o#kpr|0Yz;HC~8YUQ9A;P+7nRJfqPkRSHv)>f6HwHHfTErR6!jwbifTvQTMUr!7xp&q(YAN4k# zm7)QhFGT~{Qgkg_iUzTzXfRufhOnh*C|in#v88A@TZ%@oQFI*vMd<_-jU=EbgMgw@ z1Qd-XplA#MMVSN?jU}LH905h+2`HLCK+!}3iY5_IG?{>+DFhTvC7>vafTC#x6ip|f zD4T$y9D=W?Z`3_tfP`PL-^TAJMLG7qC^s6izO15IQSYboQZ$?MrDzUYif&*_(Ok9^ z-N=@ro7hq`k1a*>*-~^fTZ$I2QM8bNqD2H0EheDo76OWv5Kwe00Yys*C|X89(QO12 zEhnJpb^?m-AfV_@0*dY;py+M_itZtxXaxa9_YzQa9|1-86HxR30YxhbzM`2?H~Ck4 zUu3_~c)b)|^2~TJ8nV8uqKBhigWsj-5zd#QN7+)ehAl;F*;4cvTZ-1PrD#1{iZ-yN z=yA3bZDgb92?C0qB%o*$0Yy&{P_&tVqNfQc+Co6lGXxZEC7@^<0Y%ReP_&(Zq8$Vj z?IfV+IRc7y5m2<7fTHIKD0+c_q8AA$dWnFdmkGY2hobIa10;Nly)RlVMR(axZ?8l{ z)|XZETGX5Urxfkud@0(`mZI0$QuGE}ir!>P(OYaOdYdgp@35ulUA7b*V58_g0*c-z zpy(h0MTZC|I!r*(2Lu!yA)x3(0*XE&py*=)ijERcbc}$aPY5VFPC(J81QeYhpy)FK ziasZx=nDdhP7+Y`B>_cW5qw2^qV6LGNO-M%TDDh;#@jDJo{EO7FRSRgsQ2n$QgoX0 zrRWS>ioRz{(GP4X`jIU~Ke46gXSNjm!j_`5Y$-a&M$vf!ihd=a=r;n2ekY*l4+4t* zB%tU50Y!fiQ1mweMHdMux)Xx?dY0;Z^pN*tb%&*xnZvjfJc)t0+F^d6%Rpf%By(ku610wiLzKQk2A& zqGYxd6=zFP3APlKWJ^&gHi}9UP*jG1qOt@Ol_Q|2JOM=&2q?OOfTD^76jdUiD20Hc z$^;ZuA)x3=0*a~b5>I4+kAfTuw0Y$Y4D5_2H6@_DNO#>vnznFm& ziTTg;lkB7GIQGL#rq6Ta!YRHzNMrPajfTD2(6pbgKXaWI66A37qL_pDG0*a;(P&Ac*qAUW6rV&syoq(cj0*Z17 zD9R&q&-A?6*8lcKqtFGV-9rRXNM z6wPBx(R{WP-OQGv1#Br=$d;l-Y$;mIM$s(<6fGg3=vD%XmJ(33jDVus2q;=kK+)|4 z6x~5U(VYYo-9py)mVitZ<%=m7$XRuWM3AOS_I2q=1p;47LP zb1xYn;hFXejdP^vTYF!$Iu^3NtfDnB?+QWIK0YxtpQ1l7`MXwT2w1?m;dL-tyGeE)oIS1NQ&Ozd?|X9Ek$p!rRZ(86urZiqIcO+bbu{I@3E!meYO-GWTWU1 z0Y!%iDEfeaq9X(peMmsjM+6joOhD050*a0iQ1l4_MaKy!`jmj869g1}MnKW$1QdNi zK+#D8ioPVE=qmz>P7zS_H33E65PU`ZV(zU5NVtu?FWN6fzuPY!eH#l|UslogG4IJ@ zQuG7oOVN*PDf)>mML)Bp=ohvWon=eWIkps?XG_tqY$^JUjiTQPDEfndqCW{JxpXo=ELe`g66ixDeiAYh5^Q9<>Ek(&}DJssE zq7rN=D#@0jQfw(I&6c7vY$+O??MX99}45Kz>WfTC^$ z6m=({s0RT>Jqal4MLj@~DML^MPg0E;$lDozL374?6#+#L5m2<6fTD*9 zD0+n8E1H|+erte)Z?bnkH%if`c08ICvc9aMbxB^Rq!g{^d@0(%mZHbmQnZmRMNhD$ z=t;H|ZDLE&Q*0^P%$B03*(lmVK+!V<6m2D-Xd3}V&k|6yoq(bp1QhKgpy)XQigpoD zw3~pU=Lsl!fq!B@04$*paGgsa=% zz5kdLy=U)>_9um`FRSRSB(G;_DSDgprRW{D6urxqq62IxdXFtd@3W=oAX|zKv8CuR zTZ%qlqv!|$MIRDS^br9?9}`e?lz^gR1QdNjK+$mmiasTv=mY^ppAk^>IRQmq5KwfI zfTAx6DEf+kqEiGEeN8~oHv|-YOF+?g1QeYn_=?_0aRxBfTDj0DEgOxqRRvnImvq3j-mhoMR5caxdapi2`KUiC@MlgQHX$|q68Eb zBcLcuKv9H%qId#|5(vJcAClbN21q#3-WUBSMdR&fw8Z3)^<@<$Cwrfim!jgFFGVHT zQdE*HMWxtMRGKYCW!O?wmMul)*iuxUEkzaBD7u1xqKX6*RU)7$g@B^U1Qb;vpy)~h zimDP&bQJ+bR})ZFjew%+1QgXEpr|GRMYRYhs!c#q9RiB#5>S*%Kv6vciqZ%us!#A0 z#gg5B4Uq5-`z4~JWdE7|QF~w1AUR}xSw&5fy-F3Os43@5Q8Ts_HD^oFHEbzr!Iq+y zY$2q@}EKv5?GiaHZe)P;bet^^cyBcP}|0YyCs zDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVwFDFmBKV3LCA%FAknoKbPGcz= zVeg9uCx@&rt7v$#mzg3(BRF4*u47A4I$MfHvZW}4Ek&c)QZ$+^MPt}fl*yK&v1}BL zBcNzJ0YwuCD4Iw>(If(jCKFIJg@B@|1QcZvP&AEzqUi(_WfM@8LqJh30Yx(iD4Iz? z(e(rr%_5*^HUUL*2q?ONfTFnsU(wKHcbNeae$hVDA0|ah?5DRIlS9^*RdjQ*_f!=r zTEO{Iw2&=Di`Y`Mm@P%Ou%&1TTZ(RFOVLuc6fI**(QRxLEhnJpb^?m-AfV_@0*dY; zpy+M_itZtxXaxa9_YzQa9|1-86HxR30YxhbD0+~9qE!SGJw!m!Y66NLCZOmM0*W3b zplA&NMQaJZqIt>gAp<1b)ZQ1(m!h_IJeC}?zMMoSE_h|J@>d6(=tlD`TPOOq1sDCn ze8;wEG{HQZi;t$7hvu+{)z39A3j?*yudS%CH8jVzSoEFi(S36Fd=mXUqr$h9!nvT;YdSxBQ=@Fff z>NtI(&!jodfavcH9A|L!n#PVZJbH6e#~B%Yv$^Api6*pkobl2AtsQ4_^ue}{GcEc> zd&kL*Ue(EQW<@7;ah$o)ZQUGae)P{Cjh8eQ1eah6Bl?(aBvMWfd`&b`rr zgB@pO^r4}SvpV|aaK~8_t(NXM>!VXL9OsGX_R)^BIr>+o<7|z#9`86iqKhXw&hF^D zlO5-!Xi}Er?1>JV?l}9S59c_}ThUW99Opo^#w^D<6wR9BI3GrL&UKt)(Tg`Z&WUK- zn;qw5bjd=;`8xXEV#hfhEq<%x{1_dw%yG^}A6@P^zeT^f!*MP|Yu)WQmtxabn2&!T zw(CA~0|a9KJYa5tK&<^La}xw&OIMrQAP_tFh`A90v65@etq_O}TW4;DKy2*>b2|iL z_FuEF8i?6{j=XvxX8%3u+JTt;2Z8GaV)kEjZ5W8zf0DClAZGtf#TJ2>{YUZI1Y-7I zHR}+F*?*R*OCVMndlLImP7lcj=#O&Yjm>Y=MzoKteAZGuLwYhIt=9f6qrExWq|G5dQiUkb$RZ<^Z^h}qxuv_BBDzis8M zK+OKWg9Cw>{l@X3K+JyU@54aMe(UB~AZEYzej*UFUpze-h}o}xeI1C|FJGJv#O(9W z9|JM_1mbKUW*-6m7KqtT;THlidmnr$;3S>1zs+I2|4T0Ul=-z2Xkd!@(3$@NtG_qD z#)?ljU;Ym?O1#tN;@fO*tWm}a8}K43;mjlTBMT4@{&o6%Zhx4i~!{87UEQgZB-EE(t%sOLDPzA*O(_CN0`H|zwG z0#_v#kGP5D69<+~GHM(ruBsD>v@*$Y+)|F4*gSGgq*6qP%@1k`RfHG&MiVqNV@it%{kqDs-t~P0xQP5nZI2_9EkTk$JBzxX1)u zq~0pgoa7Z;k7$CqcJ@8T@?P*9CrLjOy_4j+f!1ZY64lBk1(J)jDf2+Pvi3a|Z&>K+ zRWKJ)V(Ef_`8cJS*OgqhAmGH6xw~B%^MS1Ev@YAC?9{}(%P|*hKF$@)fA;Rye5~^R zZ~teR6#h|o*EBbw>tvWy;sO^F6P$qgVcyo>%603eW@n_1&6$>(lRY{$J3VJ~X8N@3 ztlZ4extU{9M`zETmYZe6=*%%QvNLlEz0SV9dFy7W)3PT_nUFhSW~P%mK5I&5YR2Tu zS*dj=XN}I7oSHK}BRexSJ9BDgPDV~@X8rV>+!>1p+BtYc!GsaaDq>ttq(nouXLUfl+D?5pdVSO3SWQYTCuJ$c5M z%+x6vqsLE}`v3dY$eEo}_#-iHd}`b5F*7Di&1#>OomnUUV=*f?JMTl{e?`oFlDW@hAO+K-mw=!S04IJfR->mYqh z=GcrGlXKH^XHUz_sXN~CGPl*32~%^;Fns#A@0f0`J81HOmL~>=ply%iuEW{l{fhE__*a^De8TIjwjLFOV7+GQT$Z zb?ltpsa_Yy9@CoE>ykdof3b1H{1+Rw&wsITQ@v%wrndcG{(9nc^Ule;{^rW$y?rzDX6fnX><0DI z{YywQ?~D^VacOOJY3&Lw!F&YFn~j+dB<%Pn&e*ra}(uXa{fDM$ouF} z@WC)20==QR%KnGZT#Elfp{vk@Q_Tl2@0I2QtMeM=UzoW*ywm!6`vwKqqkaAvY3+Ge z=8EeKYpT$F>HpO|NQcZ(GsZdQZg=Xq%=FBuVzH@;MEk2H?@jCJA`D(#lXm&n$^OF6d!x1m zSFQsV8t8TTIC$r2P4h1*t-v2%;F4AV()=v+uG{J|!IICy+}Gq?k+cG3X@;5K>ha0~ zcxj!ui3+@NtC^pSe;zN`n@!Lfw`spQwnZyZjZEf`nhv!G|Ruf=HslZTX28HP1UI2`uGg; ze%1xId|IKKzR*qH*j$kUkKEg(A;-SjUXVHFf1s4O+06ZnUezG~Luft_ymM^go2=-R8YuJ`%hx|0c=6@11*tiz{ zjh=sd=YP62zfAJp#NH-(g3L$5f1wb8f}1?8;5JVyxY4;q(#)03JK20b&O7oEPcwe~ zOD%MR7TkX3o$F(hW*(FHZ)kpf>V^CdVVZyI+N)XU4mnL{m|L~r18iRE+-qP;`)18j z?BndZX({%RcD<(c8>Upx&YYZ?k&{^?rOuSm(`K|BZ9Za|v+7J~(7=S;@iV53GRLu# zvodn)n1|^t&CN2#2J@CrW$;ci(zNLBGKC@|^DRrlqNB*_OqI zc3MiEaVd3r*H5Wq9&NT9ZLUC_u~Ra0ax%tc)|s3+bzJWFmi0{XA8ypKx4KzlXG|TP zJ0WXoogDL!*&K6B8xk^&2(rJbFrp%)BQ$1E-k_ z$sCZKVIJMsi|s$df8=N3{!gEee87c1XXYz4%JbfP!NW%D*4`Qgj~@NUjCqj!UkZ6I zn)_}21PX3T|JOtQC&WDd>FNLZ*_sEf1&>()W*-yv?$kg3vv3-pZ3-S77Ca^_ct~g- zTmsGi^`{%=;PozdrMS z*8F zZld{Gh55Qb{tx>^zinb{VQ`VVIPQ*s)3%uj8TL7|6G$~LdQI!}tlP6~*IrJMq)^Xd zZn$W2utcC_ptM^iP&QC5P(Dy0P%*AbpsxLrz<>EsI0c<^mkYnzwa*(1{c!aq36g7{ zHWvEfnx~BBi#>&Y1f3+adgPaaFJ{=}I(c9I%73lvm@fzw`r$g}Yh;CfxQ_kONWl-+ zF<)~o^uu+cg_ga1``!zFxK6BKn3r6qxMRLXo%ge}ALC?m{aY1!i@dk~kLS@h?Cb zZ)d&=o_91~`_4Ps%eB3ajstZxUk%9X6Lp-f<2)S~>3Elp>vY^^p61)jds)XL=H|28 z{#`%z_`CTD*kizaWzil>o1cq4Ua6z~N|xOnbsT11wtJk8Ys}4M_tQFlYd!#W|Egnc zbK}_EOvh~VtpvO0>A2hcBC-2*9se!o??`$7*ui|G!M?t)j>{_f`vDyfnGdXe{bxFs zs_O46bsT=RzbEMUn7IM$+dre@>6-rjUB|k0{C$m%x#otlZ-29nFQobVO&y(v{!Y-b zlet0d+xORTc~gHssN)CC{r!cGWy}q4-~K8cuWRk^Njk1?>+fwke&62Tf9hDTlfPT) zIJ1kt7wY&@H-EpaV_Z*vM|JGd+us9qyrZwbAJXx|{{H?_$8y*DyPA$82m5=9j*k!Z z_jVnB9PaPGbgZB5@76lb%JBDM9bYlf?Z@L?9fM>2oup&8@%|p9<6RT|{jiQ7PxkjI z9V=w{yM~UVru#cf$0u_9y;H}ZXZZV~jtyt|yRD9M=JUeCizrWG3;;sI!rQ?`o{+_Pmrse+LrQ_K<{QZxPjqmn%dmZPl@b^+3 zU%SuW2X!pE(%&U@?6u0@!*slNwZGTuc>EE6f2U*0T7TEkaqK#O=jgb3gTJ5G@%%=A zU)HhdCVzL-@utoGzD>vdTl{@k$M80Pm)5b*c7Ko1@&29uUZ>*;^9?ZT>5Pt5UhsFS zj^khQ_Y57kyyEW{b^L9QzXN;yWAlCfv9pfzU-$RzI==CyzmMn`|Bk=Q>e%mqzteSG z`M$q5==k{|fB&Fk)g%5+({bWQ{=Qzvtw;U+vW|b4@59-juY24-wm9J*yXv^$bAR8d z<69^F{gIA|r~F-B#{u8?J444+-}!r^jwjFf`zIZ*{?XqJbe#ONzh~?C>{)-ms^bOo ztv-8wyF>LBe8+qj(7ydq9b=dLeT9zK{_F42I<7X44D8!KspD7X zJB4=tqGNUQrEt3&={VJV@6hfWblhRSiD>s;9sf4pO|&~?{y2|4wlUvUw8x%0-eSJL zX!i;o514N>+Wm=+$>uwbc30AIu=&=b-I+Q*V!j7y_ftB4ZN3?4_c5-9*P} zDgM4u$LGxVDedd`=~%&hv(N4tI@YsC&v9C7_t0^Oj$?Jq(Q&?xx9hk{$BjDf&~dMh z@9X%fJ(~CPgZ3{v7O{^@ikff6*`s;A{b7&h;Yi+bnthyNwt2YV#3h<e{E4PTf&CIZj>kWVo)4b^rH|^776ZW54ujzTQ1H%UoRE z%Ne6aWoORxFHyxj@f??_cjBl2UMAabaOonKmXg?+1J@0)y#k9 zX8HeoyL#qr{_Fc4Y#Kl8?P!10HvgH2kWL%(pZ&45c_8od?d@vc#{OsD-x%{B*TKB# zEI0pMFjn}%OCwDve0jUg<<&F6UY<3@`*5*RN=Yf{(NLWuJd}+jWk;{p^pl+5x9)y#KQOzkOf!zgKkR z?dF)@R@BWje(-khno#)q?Kf{{Z*zXwpNIYNrunb%^^2M7XFo3X~Dddd0S*a;0Ddy|^jhoi1-?V-c^K!jxoH^UJOZQ->#7~MQ>wtN!@b#+G7L% z|9$#r4RbGjXn)o(pFZ0*zI#HqgszEQ%zm{&r}&hjRfAWZ_|AFt_LZF%+YF$cJJKDQZlkoHBznVL7r@1fiT?PYH43PK>W_2p8 z$$a?Z0!41O&vgSupA4HroLAc1O~u899yHM{Wp1dro@IL4w+nh{<~8mv`&PZnj?7D; zEA1-k)iQTUaYaLojjUkMvtJO43x*DxH*wpTH*jkgZ);!PZr-(9ufzcJvUjIFKTzaw z$lRR;?Fa>fS9?#Jwxyu!=|=I^1`tYBtCCs<3f zyqS%hU~SEEW;Ql|m7Qi;Gn+WUx|(IoZ0ZD4HA|b>%=~G1%~EEjnX8qiUD9rIz3OY1 zu-ja*2HM5#HrK47cCy{(sx{J1vfEs@#@aEv&6R7S9kttByQbQScAKl$Ogq7DbN!lY z$D3W>T)%6yBX*nX*FrmNx4C{TwTszpu3szdqIR3>*IGMdx4C|8w2Rnnu3uYi&u(-5 z+Gz*vHrKDcw)v`9yZYw(b?508p3%(dgxRM>8U9py)-4Hx2A;j(Ug$BniA4aQ$qS{O2`0B z2^pw~kZZLOGDsUCgS8PdL>nPPwGlE*8zIBB5i&v>A=hamBwZUJBefBdp^cDH+6Wn~ zjgT?g2+7n&$XIQJjMGNQcx{AC&_>8aZG=qH_JwqH&zajl{HnRT33l^^%rW;(@CPHq|M#x-k zgxsi&kejp-GEW;J^R*Fjvo=B&Xd`5yHbNF@BV@5QLT=GU$P#UY+^UU`rP>Htrj3x> zv=Opg8zHxABjgTkgxsl(kh`>fAyeJr=2J?zi}|z@%<_etF*JgAhpZecf%d0HDGTeK1Kj5b2HY9nNuHbS1& zM#y$;gzV5p$WCov$O^ZSx&6cU+xw7veIe#I*g3)HLRO9y@`BgM+^OUVc~PfI$V-|M z^0KCcyrL-~uWCxj9!&|^t0^I`X-ddGO$phriICT|5%PvMLf+Iy$XnV7d0QJH?`R|B zU2TLM&_>96+6Z}H8zBd^5pqZyA&0dQ@_{x&j%Xv~Lv4h7q>Ye|wGnbu8zINE5%P&P zLXK$QRxq^JFtm$Vr_lAzx}r$XA*Ya!OM| zzSfkGZ!{(3TTKc1PE$foYf8u&O@w@}jgTL-5%QxpLVnUl$j{mc`9&KcXSES>P8%WT zwGr~GHbQ>WM#%5l2>C-BA%AKkp><|-x;irZkWV=^Jx26H8g6OwE&*Rlj5W`nt!B?(a*%=IiqNVLIR z(b9wj8_YE=Lx?xQKEo+Xh}dARX*ojJ26Iiz6N=eju4x5AQ5(!Py@C+3!Ccddgd#SW zYg&om*}?Y%tffD!~9r3Dit4hZD3vWm_1IFB#+IV` zY$&q(Y z74WK=FF@ug>dpC5)Q2raec4jfk1a+0*-|usEky&_Qgkg_iUzTzXfPW^LkK7uNL$s$pjQlA)sg~!B^BH;Px;;B0J0s_LL&~nJkzU2w7iNQBJ^{Qc8+)IbVuqu%&1w zTZ*n{OVKR06wPK!(HyoE-N2Tjxoj!Ak&U982q>CIK+${xif$&LXaNC53kfJ%L_pDE z0*Y=SplAsJMYj@Aw3L9NWds!6MnKVW0*Y=Ypy&<)itZ$!=q>_^?k1q<9s-J15PU_` z1MWQrNTi;5rX9?dqMdoqvjQRO%PLwK@V1+8a^~F^J;?b|w2Cc753!|aHCu`vW=qi{ zY$gQ1k==MNbk?w26SCrwAz8OhD1o z1Qcx{py(L_inbC^w2gqGX9+0UPC(HP0*ZDLQ1l!DMY{+n+D-5k-5+p|86c4X_DT5z zQZ(BtdOi@czO15`1KwZdr05mSm!enMQnZIHMSIy&^cq`=_OYdCKU<1kXG_r=Y$*D0-WKqIU==dY6Er0|XSkM?lg01QZ=4py&_*MTZF}`hb9Uqv$6Bihd@b z=obQt&Js{`j)0=`1Qh*BK+$gm6#Y&>(H{g9{YgO41p#B%LEiTarw{k{pV-_0*c}YzM_)>cZ>lN`P%-DoiC;6XM11d#)Yget0)xbEv_U* zMLA!Jim|0A%$A}ETZ-b@Qk1}!qC~b7McGmmV@pvI8%4DxaS5Ud^-vc9aM+Hu~ym8GZ-=SxvtwiKnZrKlcT ziqhCpRG%$H4cJoDkS#@x*izJ(jiM$56g4HFs2Kr8%?T*FhJd0L1QfL-pr{oAMXd=a zYC}L#TLOyO5m3~gfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(q8(9x@dOl2 zAfRX>0Y#GtD4I+_(G&uTrV>z;ML^Ls0*a;+d_}$E+{Ok-WU0L`>LW#2_A^>`T*&&e zie|=ngRYjM>p5SFX0fGcHd~73u%+k*wiL}}OVN#NDY}U*Mf2EFG@p&4n+YgdKtRz# z0*V$9P_&qUqFV?kT0%h4tppS;C7@^-0Y$eFP_&$YqT2~5x`TkCI|(Sdi-4lL2`IXU zfT9%y6x~Ze(R~CI-B0ip<;J;l4UkBN{UkO+iuT+4q6gwa)|XZEP@MO0btziS`BL;S zTZ$fGOVOijDO$spqP1)(dW)2AXo-IWi*eH6OfTE2A6g@#e(USxeZ6cuPDFTW% z6HxRt0YzH~D0+r~qOAlJZ6l!QSptf-6Hv5+fTEoQ6g@{k(Jlgtb`wzaJOM>75K#0Y z!B_NPoco#q5?K{6a8^lCroAtEDK2DvSw(x|yi+x$XfNkW(Q9le+Q*in{cI_Eoh?Og zu%+ltwiLa^mZG=WQuGcRMeh<&bbx@O_XsF@pMau+1QZ=2py)6GMIR7QbcBGS4+$vx zh=8Jx2`D;BK+!P*iasHr=r{pIpAt}Xf`FpW2q^lTfTAx5C^|{-6}=MY7OiCzt+CJa zUzMU6_V@pM85gp?tfFt?yc%_+=v&U0qVL#Jbeb(iXV_BoJzI)?U`x@DY$^JQEk!@G zrRWznip~;HbdG?c^8^(ANRxBfTDj0 zDEgOxqRRvnncs)}khvMncht?7YV3Do0|XSs5m4k3P!uGf$RqfQPQ|&s43Nl3dtdam z6vf%kXhqzR^<@=>T`wzDiXxmZMe%GYN?=P-B3p{0Y$=Mdr6`FlMagU_D$bUo5^NNe zB%r7i0Y#+=C@MohQCR|t$`Mdho`9kX1QcCCKv6{kiYgIMltMsJWde$-5Kwd_0Yy~_ zD7uP(qN@ogszyLjbpncN5KvT;;43QXy7w9&k!kj~3l($yXZnBG`=VNI$ojI1QeAIn zniSRJd?`v}OHqBc6g6N=QA4&AHDXIqW407EVM|d{wiGpEqo_FnMb{8e)PjJbmIM^F zBA}=>0Yz;HC~8YUQ9A;P+7nRJfqPkRSHv)>f6HwHHfTErR z6!jvYs5ik^RL6CX8z7N8>_eftQgp%IG4*jn)|XW@!1XRRkfMQ{FGbg~rDzaaiUzZ# zXb4-1hO(t-7+Z>lv!!SRTZ*n@qbQw#qLBm?We`v_ih!cg1Qd-SpeU1oqOk-NjU%9F zJOM=$2q>CJK+z-uiY60KG=+eosRR^d5l}RZfTHOH6lD`oltVyKF2PsS&vjE88b#&p z-A{ih`q6$NdxjgbzO16zuGhA)6wTp$DY}6zMRVCwbR%1eZemN(Jhl|gXG_t|Y$;m6 zmZF7h6fGj4XfXjrw-8XYgn*)32`E}hK+!S+if$vIXgL8zw-Zow2LVNQ5>Rv(0Y!Hc zP;?IgMJos>x|e{W`v@qypMatV2q;=fK+%H)U(xlhJJtY+jIj4bv!rN}CAG>8SzlJs zBd)iksT4iR`BJooEk$eDQuG*Giq^5EXgynsHn64Wakdm~WJ}Q#Y!p37K+z@wik>2% zXfpvtPZLnIg@B@G2q@Z0K+!e=ik>B)XgdK#I|wM+NkGwa1QhKeplCM%Mb8sZ^a24z zFA`An5&=ao6HxRD!B@1}bvGLzk#<(m!&21Ej#u4~^<@?9bG`S>AA!yLZtQ-}m!j9% zQuGE}ir!>P(OYaOdYdgp@35ulUA7b*U`x?^Y!tmuK+!=0iVhJ_beMpm4+tnaLO{`n z1QdNlK+(qp6dfg?=okS-pAb-VoPeTF2`D;2K+$Ie6n#!W(H8_1og|>>O9G0%BB1CL z!B@1`bS zOVQ74Df)#iMQ7PkbdD`W=h-Owm4Kq(2q^lUfTBMLDEgCtq6-8R{Y600-vkt0B%tUL z0Y(21Q1mYWMVAREGQYpuf7*_s00BjD1QfXh6a@(=@(3s@LO@Z7fTE%VU(vU&+tdJw zw6ag`zmuZH_R)2*V95HiiV}j}kk(R^$oWzfWlK?vEk#LeDN1HbQE|2um0(LzNwyS~ zVoOnJHj2s+P*j$HqH+Wjl_#L60s%!=5KvT+fTBtS6r~VQRGEOHDg+c=NkCCm0*bC8 zpy+A>imDM%RGomL8Uz&8B%r7k0Y$Y5D5^v76-9#XO$JCL+uj$&2mNRI$L*u*y1|h3 zWfj#AdXKi1q6VBVMGe_f)QBxbjoDJvge^r)*;3SuEk(`QQgjVlidwKy)RKUrRsPA3OcLIuf5Kz>UfTCUm z6!j*cs1E@}eF-S)NAMNZ3%dIakjO$agK1Lqv%N3s9}HPvR?(oK_f2~#8qE1pG=wch zL)lU^j4egO*-|uuEk)O{r6`>(MI+f#l)*;PC<2N`6HqjUfTBzSipCO9G>(9x@dOl2 zAfRX>0Y#GtD4I+_(G&uTrV>z;ML^Ls0*a;+P?SwTQ4Rq`xdar=AfRX_0Y%pnd_@C; zZn%R{6tUj{xmJn}+54hd!I1T370nHLwK_@Bjhrt-A+K!9Rw8JNkGwE1Qgv(K+!z} z6s;hj=w1Sf?jxY+egcXfAfRX^0YwiIP_&AGqK615T21g3%?Y}F43J1Q`}?kMkfKEM z2VR2@2Se7ERkSwfP46N_k8!>ftz%2kdbSj8U`x^CY$@8vmZB%vQuHKSiZ-#O=qWae zHWN_vGyz3h2q=1nfTFDg6m27*=ve}awi8gagMgx)1Qb0-K+!G&igpuF^gIDYFAz}l zA^}A&5m59p0Y$G6Q1mJRMSBP++Dq^iJsNcHH$Wm^+wXv^k)j*yXSCOXA?wR3dL!uV z>Lx{Ra=sM3#g?MC*;4clTZ-OgOVI(g6urlmqW9TSbdW7YhuA1OOhC~G1QZ=1py)#a ziasKs=wkwkjuKFGjDVs~2q-#EK+&fJ6rCWT=raO}J}02)3j&Hx5>WId0YzUCP;`ob zqOS=k`i6j_ZwbDl{XzGH0TOxIeiD0Kir%%)^uG&+tS_tRhoJXQ4=MVQ^QGt~wiNx$ zmZD$SQgoIrMd#R3be=6mzp|z1H?|c0&PLH61Qh*AK+y#PivA*?=x+jwE)r05iGZSi z2q^lOfTGI;6gi%rwxcLOKv5h4MJ@qFK>~_A0*Z?*%Ce=X92-UD2`H*SK+zQh6jdaks1gB1DFhT%CZMPa0Yz65P*jzGqN@lfx|)EZ zY6KKjC!nYX0Yx>JU&=mw=*F0*dMpd_{?#JKg|^jIh7&I_mk)^oQF! zrZg{PeOX0~Ja1`VDQe95Qq+VkMNQdK)Ql}f&Dm0P4O@y@u%)OaTZ&q-rKmLxHZ@t7xd_9qcbf!#H1x zhO?z;1Y3%(V@pvwTZ%@qr6_|fMWfhKG@30%W7sIlB%o+40Y&2oC>l>d(F6jDCK6CI ziGZTX1QbmnplB)qMOg$CO(URaIsrx51Qg{EP?SqR(F_8LW)e_zJpo0t2q>COK+zn6 zuV}F6{$_wgKC%ymhDgyH_P*!_FJygLMe{tb

XpYx^YX0{Y9U`x?LwiGR5OVMJs z6y3s>q9tr8x|J^Z)@xD+wrikbt691Qb0)K+$RfiXJAQ=n(>n9wqpSZuH#d21sPEeOh*t z6kW9UMQgl}^<@>U_q<_)rDy}^OVQ(ODcZ=Eq9@o=^dwt~HnFAXDYg`CW=ql2Y$@8p zM$t0_6m2D-Xd3}V&k|6yoq(bp1QhKgpy)XQigpoDw3~pU=Lsl!fq0Y&=>zM{uGcfJ7P7zS_H33E65K#0j z0Y%>tP;{DrqB8_v(VL$8h5-^W|D1#qd`pV@+0SU-dm-z~D*D;;z8fw@zi_@3on=eW zIkps?XG_tqY$^JUEk(bxrRWc~6#dDTq6=&k{Y600-vkt0B%tUL0Y(21Q1mYWMVARE za*F6_JBt1varXfoRoOQDe(y{sdnc1JlK=rh2)(A!L6BZUFM^7Mkc1`>NI^gpkRl>d z1QZoPKok`#Vnqc-MMXtHv7n-;6j6#a`*+>5uYVGs=e*}zXRUXwleO@k>p!#iv|pwr zf=xhC1OY`p0*WFDDDo3f6h%OhLqL&BKv6USMKJ^v1qdjLC7>vdfTDPUr|6{L7kiy3 zGCy~X{8<&nnP;?wD989Rijt!IsoAQi0^6&iip;9060<5wW>!U&nN?90W>s_RfTBhO z6g4KGs0jf@sRR_I5m1y)Kv4z(MVSN?H6@^^8NpK&it-H-Ac3#UtLwxl@11_WdE4JS z$}zr-qSjIVq8wG!hV4~RTV_>s1+yw@$E=FlGpnL2nN?8-W>wUYSrv6+Rz;neQPhQi zqOJrKbt9mtI{`&K2q@}FKv6FOih2`Jltn;M9|DT{5>V8SfTI2c6b&GtXdnSag9s=Z zOhC~P0*ZzbP;?amMZ*Xv8cy&OwT$wu5g>tO=5!U`m{m~@vnm?Rtcr4(RZ$+ZD#~Y8MPry%(O6~_jU%9FJOM=$2q?OqfTD>6 z6ip(aXfgps1q2jLA)sg~0Y!xb6crIrR7^lo2?0gZ2q?ONfTHOH6wM%@XeI$gHxf`Z zi-4k=2%e&AqkLZrkidK9_lriTqH*CjY*CK!Wfa{K<^LyN70qLNRWzSj6)j*^MGKi# z(XGs?Xc4n2x{X;CEoN3lw==7vCCn(ggMgx?1QabJplCS(MJos>x|4vSl>`*6BA{qB z0Y!HaP;@r|MQaEsx`%+GdkHAIkAR}J1Qgv*K+!q^iq;cQ^Z)@x8we=cNbnTRiSpGM zBZ@W}ICE7|z3>~hD989RiXM*gcN?dQwy?b_dW2aOJ<6<#9%EKTTbWhSGuMtqRlYpXK1QfkaK+zin6zwLU=uHBO-XfsrZGxw0bChp_00}fSFQ^|xeNvnu+SSrzSPRz(MxRnaHRs_0W@ z6dfd>=raO}J}02)3j&J1B%tUJ0YzUCQ1mqcMc)umbeMpmZwV;+j)0;g1QdNwK+z8b z6#Ym*(NO}5juB9FoPeSe1Qh*5K+#Epr|8`%-%|o4@Vj|NdruX$HxEodM>)oqQFJEC z|ItKMbe8Q^(XY&^=p3^uI?t?%E- z6#YX$k>%*yb`;qJ6h#nFSfTAD)MInNx=v0*Nf&dBpZXSM4tD^1Z)perd7+*$FCC8s!po)^&UKLelRz+2q zRncY4s;DZnDyqh;iY{kXMb(*AQ4MBQl){XnngkTpBA}=?0Y!BPD5^_9Q9S~R>Jw1Z zfPkWg1QazQpr|ncMNJ4ON+qBujew$b0*W#SD9R+Ds3`$O%?K!JPC!u$0*YD^JVg~8 zUpoO3$TjcuD>~jg{lVs)ek;c@zKo(P9RGDwRZ%;(S4HiaRne8qs;C3AD(c9riaIf? zqRz~!s0*_y>dLH&x-p}uI{`&K2q@}FKv6FOih2`Jltn;M9|DT{5>V8SfTI2c6b&Gt zXdnSag9s=ZOhC~P0*ZzbP;?amMZ*Xv8csmb)dUn>LqO5B1W!>L$9IbW34ASMWLs7A zn0YK3;W);ZQ8dc&Zz@tnIc%?rMl-9TTxM02$E=F-nN`skW>qwnSrv_ARz>5PRnY`y z6kSh1(L@4@CJ|6HnSi1K0*a;(P&Ac*qCx_SiU=qwCZMQW<`6tZBOTu!0TO6!-j-#nqTc4|ZLZ@OUq;aa$A7#; z6)j|YRdg$}Dq6&>if&_8MT?nL(e2EtXbH0_x`SC2EoD|k%a~ELoPeSg1Qgv#K+#G9 zidGR&w3>jTy9g+{n}DJ<1QgvvK+(Mf6x~Na(OLqE?kAvV9RWq_2`GAifT9fq6m2A+ zXcGZN4-!zcncyj!=lJ5MiJ}cMM$T77UzwNM4>^wUWfVQ?_|vDWqQ}@?6>Vi!MUOM9 zq9>SD(UZ)o=qYAZ^fa?7dWKmQZDUqN&oZNEI{`({5m59z0YxtmQ1l`JMK2Lh^fCcO zI|wLxg@B@02`GAvfTEoQ6zw9Q=yd{$-XNf8HvvU&5>WIO0Yz^UP_&1DqIU==dY9lS z+T!?z2#~1j)9*f>{9OKI<`q1&0%v44D*j^QV#H@-wW>!V}nN`sNW>xeF zvnu+OSrr{*Rz;sNtD?`DQS=1?MPCw7bcleWuLvmmnt-Bj2q-#CK+(4Z6n#fP(GdcQ zz9*pQ2Lg(IB%tUh0Y%3MC^}9+(Fp>Iej=dgBmqS~6HxRE0Y#?>o}%|1-@O7PFwVRb z`al)!H;+Z99mn`Giq1LymuIP>^K7q*E-qS}U3Mb|ODjG`*8 z-=3|CE@OLDRFzp3Rby5~mouxP>ddOB2D2(kVOB*onN?9OW>r+18AWvnD5^_9Q9S~R z>Jw1ZfPkWg1QazQpr|ncMNJ4ON+qBujew$b0*W#SD9R+Ds3`$O%?K!JPC!u$0*YD^ zP}GWmqSgcywIO(ll3iat0TOuC{7O+}*L$bm(LAHIbsgi&D7w=1_n51SId35$ zIx(xF&djQ)3$rTf%B+gIF{`5P%&MpdvnuMzjG|ry6!j*cD2sriJ_Ho?C7`Gu0Y&`@ zC>lUO(Le%<1`$v+n1G@o1QZP=py(idLG(qHNbOzKo(=*MG-6Rg}l}swkgX6^&t5MPr#&(Ku#RG@e-% zO<-0<*E6f4iOi~K5;KY>6Hrt@K+zNeil!1!R7gNk5dlTT1QeAJP&AEzq8kV(nodB` z3<8Q~5>Rv_0Y$S2D7uM&qMHdQnoU5_90H2w5>Rvt0Y&o&o}wJr_ly7uG&C=TMysNh zhSYr5F}{qVMXrDU0#$Sy+pD6*%&O>iW>vI=Sry&EtcsR0tDT|6fTD*8D0-NHqAdhZ(L&dENq_`)+5+cRRn*mxdc<{%FQe#j*I#9k zDtdzLRne2os^}?ZRrEBoDtd-l6>VcyMb9#;qV3G8=s9Lp^gJ_)ULc_8MFNUmBB1DH z0*ZDJQ1l7`MXwT2^cn$0I|(S-ML^N(1QfkNK+$djiryrk=q&<@-X@@E4*^B*5K#0k z0Y&c-P_&nTqW1}&qQ_j{l>#KtPsYfts;G*2M*F~Zj4z|;W7nU(SQYJOdsTFRSrvW4 ztcpHmRz(MyRnce6s_1iORrCe3D*BRH6&+$m(N_c%eN8~oHv|+NCZOnB0*byPpy&tz zMc)%p^aBA!KN3)Mlz^gR1QZ=7py&hvML!WxbdrFgp9v`Xg@B?{1QeYnpy&(%MP~_~ zqJ6G!z5tO2AA$3cD%xc}$o|!Jj4z|;qU+zhL=|0PdsXxsvnu+XSrz@ktcw0*Rz-g? ztD?V|Rnb4ps>q7g_wB04W=2s20YyFniXsUp@)J-LML>~5K#@y8Q8WQXF$5F^2q=mr zpeT-jqId#|5(p>?5>ON(peT`mq9g)}DiBaqk$|E~1QaC`JVobS-@5`NFx@=-Tu?;` zW~dzP7+*$FwP^oOOI6Y3Y_E!{GpnK+%&I7bSrye}RzT zfTC6e6tyOxs0{%{Z3!s4f`FoS1W(ar(Z1j^QM4{f;8czF-syjAhW62p@nsZsiuPx& zP(_{DUKMp=Rz+QzRZ%x)Rn(nX74=|NMLn5SQ7>jy)SFoqWig|u4*^Ae2`K7EKv91J ziUtr+G?0LzK?D>HCZK2t0YyUzD7uP(qG1FS4JV-JY66O`A)x450*XcuP;?yuMI#9) z$|j&_6ahs!1W!?iXx~)=BrwW6{B%@BZNqQaq8;PQC>j&(zhR{+8q4;oXdJUD8qchX zCNQg_>zP&2L}pbqiCGm*W>!T7%&KS#Gm54XP*g}jQ4s+}#RL?U5KuIYfT9}+D4I?{ z(F_8LW)e_zBLPLT2q?OVfTEiTD4I<`(HsJb<`PhJ3jsy*2q>CQK+ysMiWU+)MS0P_ zwE`s2#ytGwtD+X>myK?Xc8o8h==Ny;E2~w}61G=GcQC7>rOc{m8M7){&a8@7Fsq_F znN`tBW>vI`Srx5jM$uga6x~fg(Ha7Z?jfM)UIL2lBcNz40Y&!{P_&MKqV)t6JwQOw z1_FvU5>T{>fT9NpDB4Uw(L)3jJxoB+76OVMA)x3{0*W3Zc#3X|_I)Qn0^MYcT&#+E zn792~qaEYRD0(W|?^~mao@RSh^bE5q+QzJko@G`=+nH6-bIhvfd1h7g0<$W5ky#bJ z#Ehbs2`Jh@K+!7%6unA7(Q5=0?IfUR7Xd}D6HxR90Y$qBD0-8CqPGYrdYgcvJp>fJ zLqO5H1QfkTK+#?Tiry!n=mP?ZJ|v)MAHh@fM6|Dg00}&8K4^SW6@72sqkR1W>s{ESrvW7tct#7Rz=@1qv$XJMc)!o z^c?|3M+hkTo`9ks2q^lIfTE)W6dfa==r{pICkQC|iGZS$1Qh*DK+!J*6rCcV=rjRE zX9y@dOF+@D1QeYkpy)ioQ?x(YH(7uLt}}2BsG`%Z3>Tsuxezvnu+BSru6^`p#Vy+03daf>{;$m{n0EGm88K6h#qGOOPKv4_< zMF9eeVhJdUBcLdrfT9Efih=|bg$O80B%mmXfT9Wn6jdaks1gB1$pjQtCZMPa0Y#S) zJVlqHea{Mzz!3Ag=r>ig(Jw>Q7{~ZBifY98KUt@WQrKP<)nryhwU|{=ZDv(ehglWX zWmZM?m{n1IW>wUHSrs*8Mo}XIiW(D8)P#VdR04|92q;P?peTcYqD%scni5ddjDVu% z1QfL(pr|DQMXd-ZYE3{<8v=^j5>Rvn0Y&WyC~8kY(Uk-gbs%_(E|2m3EtE0mr>L;#$R=VD(c4es;E1&D(bSrtuTRz*{pRZ$_cDk@?|Q858UB?J^r zBcSL80*a;+P&9*pqL~B~-AF*uECPydBB1DI0*Yo6P&9{tqPYYV-9kXoJOYa56Hv5( zfTD#26x~Wd(INthZXV&-3Xs4d^YAlH6@6}ABrT3{j4z{TX^j8j&8lb_+pD7G z%&KSwvnsliSrx5hRz<6rRncl@Rdg4#D!Q9l6|G@L(LDqd-Ah2xeFPM(C7|ej0*clV zP_&+aq6Y{l+CV_jMgod95m59X0Y#e$D0+y1qK646+Co6lBLoyZN2`GAt zfTFhvDB43n(K`eby-PsRdju5iC7|ei0*XE$py)#aiuMsu^br9?9}`ftpWrEaI>wi{ zMHI!F-`;;l6&*FC4#YUdmr?XtjKA5Vs_1jJS4CeitD-NNRnZ}4RrD3JD*BpP6@A03 ziVicYqHmd1(Ra)!Izm9v_XHIEKtR!t1QZ=5py(I@MaKy!Izd3uPXrX5B%tVL0*Zbi zpy(67JKtNHDfT9oqMTrCyB@s|mfqQl)fTGI@o}xcueCq^A;0N<0_NOYkOOA`I9&n5=qo`KE|JoC( zs5aZHqB_i~s4lZAs>iH~>NBgN2F$9cA+suK#H@-MGpnK|%qU7FpeT)iqI3d^G6*Qj zB%r7%0Y%LSC~8hXQ40c!S`tvyih!cl1QfL)pr|bYMOP3|)Q*6n_5>7NNkCBt0*X2k zP}GTlqRs?QQA)t~y#NV(X?_}8GvK|`f7Lt|bqP4emr>Ls;P*eRih8oWD(c0oih47v zqAX@r)Q4FW^<`E?{g_oze`ZxQfLRp{WJb{-0*VF`P&9;qqM-y7T}43AFanB(6Hs(D z0Y%pkP;@N;MI#6(x{iRNkpvWF6HqjYfTA1%ibfMqluJNS9sx!91Qd-SplB??Q`9Zs zYa~Dd70pjTx~rnw<+#Xk0mt|GOMCOW>r+g ztcr@6RZ$7EDw@WOq8kV(nodB`3<8Q~5>Rv_0Y$S2D7uM&qMHdQnoU5_90H2w5>Rvt z0Y&o&D4I_|(EaW>vI?Sry&GtcvbsRz>$Q zqi8JwMfVd>w2pwH^#l|>KtRz30*W>gP_&7Fq6Y~m+Dt&vLj)8(OhC~V0*W3Xpy*Ko ziXJ1NXe$9lj}uVz1OY`)5>WIM0Yy&}JVna_zUKr;;0N;)kmahV$ULJx6L5?#qv*MS z|KRhg=y|qRMK3U`q8FJ}(M!y#=w)VAw1Zg{y~3=DUS(EAuQ98loy;iOML^N(1QfkN zK+$djiryrk=q&<@-X@@E4*^B*5K#0k0Y&c-P_&nTqW1|X`hb9<4+$vRM?ld>1QdNt zK+%2ziVhG^^a%k)pAtMp&jx&d3Xnh-182J`+F~Ay4h9_K%P9IX;J^GORdk5$Rnb?> zs_1KGRrC$BDmu)pioRu5Mc*;2q9e?z=zC^W^aC@Bek7piC;>&s2q-#EK+y>Tihd%X z=p+F}KNC>&3jsx^2q-#DK+zcjip~;H^eX{H=Lje|Pe9QH0*WpYP;`laqTdK8`kjEH zKM0!Tp%qR*FP!vl*Q5*q9@dOkl5Kt5(peRH@Q6d3FNdy#CAfTus z0Y#MvC`u-vs4@XXRR}1$jDVu51Qb;xpy+Y}imDS(RD*z`6oRMd?|^TS015nUK6U&@ z6*ZOPB5TGv#+Ol4H`f2itE#9T+pD7b%&MpXvnp!Htcn^jtD?rts;CLGDoSNmMQO~c zD4iKa83Yt%5>V8XfTCsu6g4NHs09HwUmSrrXnRz(AuRnZ`3RWz7c6%AoV(NF@4t|Fjl z7y(7Y2`IXnfTC*%D7uz_q7eiXT}MFCNCJwo2`CyxKv50>MWYEQ$|ayEkAR|l0*b~E zP&Af+qHzQijVGXJ0>M+%GuBsOmnia^PaS)yBJ&r{L|z~37+*$FL9D;U8>(mu+pD6f z%&Mr6SrrvAtD<6NRaC;Pil#BEq8pf1(R5~2G=mvMGYKfVk$|FE1QgvwK+(+v6wM}} zXbu5Ia|tNAg@B@Y1Qg9DplAUBMGFZix|M*UMFbSxMnKVG0*Y=YplAsJMRyQTw3L9N zWdu*rq*&iI0wgfRJp4>nMPtmcJk~M3jG|Ss{u|#^MXT9f72UzGlro`9kU2q@Y>K+#45iZ&5Y^dJF6n+Yg-h=8Jp2`Jh^ zK+z)v6g^5n(PIP@Z6%=SaRQ2-AfV_;0*am@py+7=ik=~$Xd3}V&k{UEcgFf25Fmlc z=2OR&swg7-hAq}HzKo(5WBt3{Rz)wdy()T{SrzSIRzpXg2{xZxT@S76Ci(2M8$ogn*(?2`D;9K+$Ie6n#$c6g?m7`%!=dI+}-{7gSMoIWF>x zSjYG>ioTYA&-z_e^bOmqqQlIp=v!u0^c}M*I>M}qzGqfNKQODJADLCrQD#+ij2T78 z2`D;2K+#VG6rCiX=w||oej%Xf6ahu22`D;4K+#zOihd=a=o|q>=LsmfKtRz&0*WpX zQ1lxCMZXhJ^alY&e-cpi7Xd|o6FfzSVtq{nNT8Pa)bT4-be(xD`X|;gzKkMYoWJj0 zRTLTb?|1rsW>pl$tco0FRpc_OqG)DS6vM2F0?eu?mRS|WF{3D+fT9Efih=|bg$O80 zB%mmXfT9Wn6jdaks1gB1$pjQtCZMPa0Y#S)P*jzGqG|*bT~0tzbpncN5KxptKv7Ks zifR#1RGZ)_vg3S(0wl2Cz=??S-lHYSaglZ69OKIt zO_)_tDzhp|V^&4!%&I7ZSruh6tD>gNC~8JPQF8){S`bjwl7OOC1QfLQq9M$x zXehHPx{6s94P!>pZ~}_1CZOmV0*bCBplAdEMb{BfG?IX#Yyyf#5m1yvK+$LdigF1k z$|ImCpMat<1Qd-WplBQcMdJx5nm|C&^#l}6B%o*#!BdnK=lffL1RgbyMSWC}`Isnj za-3s)8AXM0{u=vLQ4!m#qGD!MRKl!^rZKCc8<CQK+ysMiWU-3bSnWxiwG#Xjew%X1Qgv)K+zHc zitZqwXej|j%Lpi1PC(HL0*dY=c#5XP`ML^_K&JU6*{Q0imw7B&8Rr;ZM$z4I{`^l= z(Hgc_MfWhPqI;QD(S6LSXf3lUx}RAUtz%Y2>zP&21I(&u12c*?5>T{>fT9NpDB4Uw z(L)3jJxoB+76OVMA)x3{0*W3ZplB-rMUN9u^aKG#PZCh{6ahs~6HxRF0Y%#gD0-HF zqU{6}Jx4&%^8`=P>NwwG0TMW5K6SiH6`e9~`(KE2j4z{TN1Xq$gR1BiwpT^3GOME3 zm{rkEW>vI{Srxs`tcu=XRz^^UBcNz60Y&c< zQ1k%-MIRDSw2y$Ij|eFGn1G`F1QZ=0py(3IRQmq5K#0b0Y!%h zo}!oHeES4Q;FNjzd07?pG(QgcD$X&!jG}Mj{AWH_Mc=W#DmucfioR!7ML#gBq92)6 z(NShqbc|UQ9cNZWCzw^yPs}JfNkGxh1Qh*3K+!1zicS+ybcTSUvji0VNqwdSrrXuRz+7ctDCQK+ysMiWU-3bSnWxiwG#X zjew%X1Qgv)K+zHcitZqwXej|j%Lpi1PC(HL0*dY=plBrlMXLxXT21g26~+6~1W4c^ z^H@}@irSl3*LTG`#+OlaZ@j<%531-swpT@KnN`vK%&KS|vnpE8tco6BRz(|_RnbOf zRkVp&6+Os|qRj*pJw!m!!vqvs(Jp3H^g6RDdV^UN?PgX*Z!)W*x0qGY+svwH53?$IhZ#lh z5>WIW0Y!TWD0-iOq7Mit`jCL4eFPMJL_pEU1QhKjpy&VrMV}B*^eF*F2MH+pjDVug z2`Ku4fTAx6C^|$y(N_c%eN8~oHv~`7EAhUU1V|v&ycBv>75!>{efDs?V|*D!-^csE zJg$mRxGfTHsR6kQ;o=pq3{mk22Ojew%x2`Ku5fTBMMDEfDEh#_IiiXd8B+cP$M`aeq7(czPpYCAwpT>~W>pl+ ztcv28RZ%>%DoS8hML}j&6k=9IiOi}fi5W!|2q>yZKv5+EijoN^s!Tvp6#|MbBcP}% z0Y%jaD7u`0qUr<`)gYiKg@B@(1QgXGpr|$hMRf=$s!KpoJpzjA6HwHEfTD&3Pmz=0 z>n=b7JIqf&+yw8P{uV>3QG#Q98AWLc{;|KPqI9-bMH$ShD3e(gHDy*s&6rhDb7oc4 zf>{-{WL8D3m{n10W)!s{pr|bYMOP3|)Q*6n_5>7NNkCBt0*X2kP}GTlqRs>qbs?ar zD*;8_2q@}KKv53@ih2@I)QfqwdSrrXuRz+7ctDkw2XkFxe6 zvntxatco@=tD;TJs^~#xRkWE|6+OhPiXLW0(G~)V9wDIUQ38q{BcNz20Y#4!Q1k== zMNbk?^b`R_PZLn|3;{*k2q=1%fTHaL6g@{k(enfpy+Ah)~cd)=IQO#1jqO?ie69f&%UUN-e7xGw3}HKy~(VK-eOioZ!@c+ zJ`OKLJGt2q^l5fTB+c zC^|?$(Psn{eNI5p7X%c2NkGvd0*byOpy+D?ioPMB=r93A-x5&t9l=wyGr{+u00|5; zZ_9S6qIu@A=tzQNd>KVY6Z~)frizZSy(&7+tcp%BtD>KnRnbXiRrE8nD*A<46`f*M zMW>ln(HUkGoh6{?R|1O85m0oVfT9Zo6kQ~s=n?@%zY$RMI{`(15K#0d0Y!fiQ1mwe zMgI^`WCitYJBn-qiXsRo@)1xJNkEaGfTAb@iX4Kc=!XQ~2>}w=?iV;es-l(VvB(WN z#+OkP8}tYMR7G)YuZrTCRZ#-7Dhe{Iq7btxN@P|=NzAIK0<$Wr$gGMgF{3D%fTGF- z6jdRh=rRI|suECCjew%d2`H*gKv4|>ic$zDs!2dmEdq*a6Hru#fTFqt6xAc3s6GKj z4G1V|NI+2|0*V?FP}GFrDT)dDG6YEAbhN+;1ig3qADO4O)SzR08AX{v|G>XhQB$^8 zMa`I1QFCTh)Ph+RwPaRBt(a9&Yi3o{hFKN0WmZL3Fr%m)0Y&WzD7un>q7DQUbtIsu z69Gk?2`K79Kv7o$inDM}CerU{V181q<^p^9S7Guoh_V|*D!R|WldTV@9tR^%|YS4G2_RngVVs^}VK zRdg-0DjLD8imqc;MI)J2Q8u$G8pVvF90H0)6Ht^(Kv5n6Mfn62jUk|DECEI12q+p) zK+yyOimoT1Xd(eclL#o9Oh8cq0Yy^?D4I$@Q6T|EMFbQT6Hrt_K+!aUr)Wsfw?lvg z_Lv`?4OK-o%sc%Xf{yWJ6x|r~e-)vMX0g30x`|m8-OQ|tW;3gzIn1hPF0(4Sg;^EN zV^&4;nN`sOW)v+Xpy*ZtiWU)2bQ=LhiwP*Yoq(bx1QgvtK+#eHik1;jw48vV6$BLB zNkGv`0*Y1xesvntxctco6CRz;68 zqv$aLinbC^^f&=UPY_V_BmqTF5m59r0Y%RcP_&JJqGt&x+D<^xa|9GUPe9QN1QfkU zK+#JC6unG9(GCKNULm09RRW4$BcNy}!Bey@=<6v!0*%bW&w5q#wo$Yz=onu{(VId4 zct;hz#rCS`ZDv)phglW9!>o$lWmZM+F{`4z%&O>pW>xe7vnu+K8AbaDDEf$iqK^qE z+D|~y0RoCXA)x3}0*Ve2Q1lrAMV}K;^aTM$UlLGsh=8K62q^lRfTC{*C^}3)(YFK? zeMdmi5dw<7C!pvDf~V+>pl_)F3G_3MMY~necJu1`$Dm_;8AT_8{wJeV(NAozicT`C zqMw;n(J#!Z=oGUmI?b$#&M>Q@v&^dKS7udoju}Pg2`IWiK+#14iY^gQ^cw+1zY|dO z2LVNY5>WIP0Y!fkQ1lN0MOH}Pwxh@u8LtcofytD=g` zs;CmPDoSQnMU|OVQ59wsT}D7rRRW5t5m0nF0Y%jbD5^m~Q3?S?H3=xHMLo$t zGOMCnm{rj{W>qwwSrsi{Rz(Y$Rne`?s%Q~2if$vIXfXjrw-Zpbgn*(u2q;=gK+!S+ zik1^lw1R-5I|(RSNkGvm0*Y1>P;?goMRyZWw1$A9dk84Hmw=-C2q;=hK+*jK6s;q8 zie`m;Ck0609`o>XlPbDkhV>!G_%ez%h5T_9RndcNuZlJ^tD=XPRnf!Ds%Q(dDtd%j z6+OzViXLNDMO&Fw(c{c0dV+wWCkZHeih!c02`GAofTC>#6g^8o(RKogo+F^>c>;=F zAfV_)0*YQDpy*`+igplC^a=q*uM$x78UaN+2`Jh{K+)?26um+46m1CknhKD>5cAvn z8tJQnQ^ImVY!v?t^roUDr8VS82dF0(3nk69J%WmZM+GpnKxm{rk-%&KS~vnu+C zSrvWEjH3Mn6dfR-=o12pJ|&>&AOS_65m59w0YzUBQ1m4MMTZC|`ig*}uL&snhJd2O z1QdNsK+$&u6dfU;=z9W+ejuReM*@nD5>RxE;3;}5s0|JT~5>V8LfTG3(6g45BD3ySsGy;m!2`I`SpeU1o zqNW5-Q83XLSxpqZZl1(KiQYT?Wr8QNS)yZn8AYuU{dKFWqSkD$irO%%qPEPc=n7_4 z)Q(vdwP#jES2C-j4$P{kBeN>%#EhcO1Qc~4pr|VWMcoJ}>P|pW4+4sM5>V8OfTG?6 z6lD=m)Q5ngz62EYBcP~10Yw7{C>lsW(I5hf1`|*;gn*)<1QcCGK+!OQr>I4uueSgR zG&XQrs-o%Uv1oXrV|*D!BNF}B%fCn*{yExpY_Ez&GOMC&W>qwbSrz3ltD@1&swkIP z73DFjqI_mmG=>>PV+kl4M?led0*WROP;@;3MH2}qnnXa+WCDr`2q>CDK+#kJiV6uR zDk7k$n1G@Z0*a;)P;>(UMbil=nn6I(Oah8-B%o*(!BcciqHnnX39L6iN4r)PZ8J}A zHzhj8mr*n~(f@QURdfs6tD_dN2q;=jK+#hFU=#&{YCOXEKm0(3g){d@O z&$fb(3pFeFq4`Ds;2HUets6{|Uv7&HwvZpf1%t!lEUQBBz68sv9Q-z9S=EB|D_B-a za8f19suSE+*|Hi0f4j`GnglysZdn<@1vM$D|4J@l` z@JJ)e>KSa9YFT}P1?iSGAhehc1>?9Bka(vZe>8_Oz^7!RLEh)|}v9eJpE!uuFf-S`@r(pk*xy zemK~&mIo_dWm&6&*ABO=HNg$nSk~I$(GiyQKrl7ivK|Z;^9D_o(s;`srIvLm zn7P8T{tVr)Qf_}c^vY_v1MHA*jobrvsMo!67uca?Yvn$$L!YdZJHZZB-5~dZ9m?4x zcY_^zc(dFOcF6o|_I2!#`RB+R*dg=pNjI@W<{t#kutVlwbZu^j%sL zGXE%EM>}NxRkN;k$o#WZJ?)VBcZK@cp;J5MKCwgQU-lSchs;0CFx(EAzgvHV9WsA8 z`Y1bO{℘J7oTP;&FD!{Qa^M?U4BkLZ{dv^EW&e+adE;^i8)z=I>aWWrxgPk~PN; znZM;|z8x}uP0b=ZWd5F!C3eXCMG?#GkoiCTSJ@%+ziO|sL+1arU2BKT|19}{9Wwv7 z+kPrL1q z`L&fjcF6qR!CpILesH|c4w;|)9k4^@M>n6@A@kY$Avf7(`JtodyJLGN2GDG)1nW;6LVGPj@{T)U#a zZB_V9zN74B8FE)ya(wu!!dltPZq~!JJoz(1{#2ObGi~HDIV|_Cb)WpHxWt^UMZ9Tp z8-)LF(n^BYvRj6mRVm$^pp_2yn?1CSpC>1stdk8cGp~&v^S1QIp8amtgz$#jf7!C< z#_)y}>mTed8~S4(uU}uj59sLk&Mj7VDWlnCobEDwY}qd3b(eao z1lh=6b~%D^axu+0hr$Q^mX)YiNzWuH&F)Zz3sJvH$WDyvSo!YGRm?e7@Rz%I5y{VY zmK&#H^Z#y@%C~BAX34kRV#^JinPm1-dGRf_6;XLb=gO83 zn$@97yDF38!xu#^o00h+U*>zlwg#AGLipeivrG&h9AOqiB+~lT9D*P2;+p+`iYqTs8R>pd>nkyAyHDCXhte?prxjJUAW(Ouq34c|S z|C*;~b0zsQrz!tce*Roe=Cg8SlL-5d_&Cd!FFCFJvD4Dh3v<%P6irDlD$GqU%r45! z&z@3PP@JDzoS&DTTR3A%ae)cB`FSOU`9)JXk1QVetKd4oRu0#FC=yL7iImZSlWxH%-ea&NsJ~W$7K=tYt}Bu5pl^mp>+_ zWMXl4@r)_?MQP&H@h4T6 z$vf_UUTewASi7P>U>5mHI?N*b3Xf^Bc~gIijQ%?Qq-x=vC7CIzz5hSgiYD9sU^{=^ z+WzS9UTXWzOJvz;UEOJTO!G&}PV2~Nlg+{O|J%U~vvEasRj2%}Qo?5xA-iiJIl^2r zv-+l_`D=#{1mzsU$E25@qDlCO0!|TPA7!WT_A!}LB>qpQn8YcP(){(p=i-x8(HznX zA{VI6z?$jl{*X^DNlK&e#j~Sob7QB-X-jWxxm)#isbOySn&I0erK!J$x!t{~+!5h} z|Gw+~dvEC?C&}+m^^F+QE+wL}Jd_RU)+4)nMo-JEnXNN=W{>s`wrpN{utk^BgDqR@ zDVw*ZbzO-s+W zOSxU@1#HR&ElW?;CVZJnCKrt#J2^iuMZWpMXV*n9S7vwiA_usd-Ab=Vrd*it>D$Q3 zva@CDW=*rbJ!Hz6u|aqC)=Br)xoi(|3&_dxN+wO3;q6IJ+gwj7o3NWsdQ_{@BsVQb z%Kf1So9oFsb8Wkp-8^!m=&9sNcsH!<%{x%;Lbc)o%gq@+Qf_M9u0`q2N+UAo!rHG)r7Jh>iVxOt%(Jb$EJk;^IzOD%Pt7_ z8t~-K3!eefj3xcf@Gh_?*nBH?3-4uu`R)lHm7xFxvtFXkrI*co+lEinsq8{_MM5(@ zu9OBBBC~brt}@FMq6I9OWh~{|=vhOg6oWiMcvqmzR;J+cS_Vg!amy^{t;`wsn_LZV zOAeSjDE#=OcXGCQIvrCoIX5#SBYcE@!<6fp-UgXvH&VI#zLo6nfAf_aFZ{gM1Ll%? zP|cy%W%r5PW8S4|%JnIemRUwEvz#?ypjV{y#^=t??5sC1cXgZ6lgOQ@_f*+~BMw@W zT^`R^_=YWGm08YJIZrL+f|Q}>p;c~w@A8?W&5mT%bIz3SgK)xzJe28C%}VbSxgj`t znJ(bqru4hNwcLIMrQZ>PP`BlY$2>S`l5N3$dm_aOWqe0dN)(1x9F2@8IQ~|AEhMASjh9a zoORK-g2Lj`r%>)oLoTeK6hP^dy?kqiFS)ss!ldNp@eY(TQDz{s3_)g@0`8(rxv=4l z<<&rVFLTn4P@#TayRRd-Xmm> zenV5bv}u!K-a@5irkFQT8LgW(Piat?KQTY2D8FG!>ZIH$CGB(N7R#TWI;mMR3B}_| zCXJSL%*2A6;#7GD)?V(GJQL)UW2Q`NkycatVU_YIkSVak zXH@ng(#SL{%3e#By@Jg2^oP~Rvw>d3vU|&W*;M*O8wQ@8{qI)+yo4=#1q&hbN~?eO z!KKgcnY>^vd+}NJnzQUBr@VNDlJ^~9E?%i=UapqCk}UT^l2@x`uNwL0FfSy%8%9xj zuNcGE+`LTHSFYh}=zRy4UTePNN?pU+yj;D$^ih#lrDd-Z%U&jCmOW%*-9QMRd-x@4 z_yMI;eo@mFEqmln>Y5+^{9@=70hB+uMBf+iiZrwIMQ6Ehy0UMbvX_ilD0{(Z?qjP* zmo9Bn8kp~`PKA?Fx=k9LpO+^u+K2GTM)=!}Pb?b#&)PYEbTT z9P=?w=lII=qZarVM&9aM6tUEfSQzucp10q6b9cPeJ@VRzW^?XkUp`Adge>>vv&^S?WnVt4q9s4k3SVn;A0*24XV)&(D=@fp3ES)klGUdF?C61A+;mYNU zkqcW{*6J1IGivD(a&wsvP9x+_FxT9ya#VP&Vpch_rdj1?Gv3Vc#*bO$=WXFte##bJ z&Gj_hTtBl8)m1)63eVi$_-%V-*jy%x0RVY=sI0~P+{f; zy1ptOT$}klT_dY{b4b_T@*_=i{4iaY*YM{1b^TOsSabXlU8~jc=7zeCuIJ4Kx^9s> zz?^=&uD>+$=09|8p6bn=be$=8lsWyay6(*M=J$1t5~$|*BwhQ+9ct#Qb-lB-H?P+8L}`9odZ zzTR9>*M9xI`C4694fN&>x_&X(n~&<6a+Noy>N;k)Hy7!;^%`$}QP;EbLp5{#{?WB{ zwl{av_2wLJzFpVd0^OYcBVA+0cyqF@1IBstb-La)!J9YfdPqLjH`^cAwN`;Qr|UXy zsyCPD`b3d8zpU%I5^uJrd28G0-r7UgIWxWa4qe}x<<0wbjh*eyRdgLR*PF9-T{F*{ zH|zTK0&o6F*E);5IaAjOi@o^;Z$7AN@M&+pT-U3%d2_C=YqxvzBf5U~yf>fHwZTi? z+(OsMJG}WuU7vl`n|JB@`%Z6mc6n>ZH@vm4t_$Dv=9RkcecPKq*ER87Z?2*1@V(xg zuj{%Gy!kO*zu)K0XLN0}-|U6z2*mR9;@pEN4@!RU4K08&A;l}&<~*y|wFkZyl)X;)~vVx32r-_YKVT`%2eJe|mFmT}S-w&Es|5D6cBa>7Uf~ zScEs9*HwNb5w{CLyM_vreu z{7QqFztOd_{BDDp>*_jEe#ybi*X#PA{I-LcpVsw+{Mv(=FY1~hzyDz7_PS0>@#cBD z?vNkJn&aQmwU+#Tk(twVZE04&Wp&eefLUYY$DX=gtvyfYak@^@K3(Toy3WAGImO}cK? z^(kFr&FdrCPf*unUFBs*xYyFPp04t8Alx%`y+YRxy2{gU`1szs=IJU=Q{gU8KjF1V z*O|KBtgAfShmT*P>t7n9bMno^?eI3`MmL8?~6<_$C79 zy(r&fd~rx#F8*tOb!2}p$QhXZ8C&dcj2vbgIcRliXj}J{3mlyOAE!Ii$hPF9rC%H@ zmQwzD9O`AuujP5?YdYt9s~lz$y|Pav03u_o6^knFz=Gt-@S5} zZRDU;SN3O4#}~)lC87NOs+HScoE*pgw#s3)G5csC`}@iqsb3toMdtGRYa;tI_mjDN z@@-kVzZc}N*~WMpXDzkJQhUEd@YU$saL4MV9ba@Jici%OES~Wmdjd%+Y=1bfYAi$8+&+}dmRrIS15&lLG%$)BM7NjZ|!Y~1zR?8esVR&yidzgy?}Pwfmo& z6EVBbcR9N+?aMqe{^|(p%%Hi$Yc0;&eJQf0>^bAWrN~UH@gHAwOfjdA>OMbfLGJ~< z7WUkI$qJvBsr^q|ojRXQ%AG5hYhQ}_@9vZd^50{@+M|-jt+)R?(Er@dVf|0f>26Ln zv(L<)xxEhNynbolsMjy;?)dtpV^-3rz_@jKI=TJ2_dj>6xaZm0wWszR-uuIxU6)Rd zl0O}HT{>(9WRGjTQx2C?_UnJ{vsqm(*geeNd!F51Y|bICXI8J*FIAiK`lXYH<2&0do4v%R)r)5^l-WPLP_G;DhtxN4Xnfsz+?bzOLUD}bk za{QN(e;#Pi{gq><=k`BsSJXr2GNMwmQhTTMO6%!qxcH;>niZ_n(MlO**$q;f+s&;M z`5>+JbF&7WTd=Fqf(yQpiSu`#{rJ9~Rd)U|I&#It;l+!hANS4uZS`ACTGng*`vX3E z&P~hgnD6~LwzX)EJf6(y7CXmE>s({iw(iI0 zp1gMa1xHdx@g%J*`-Rt+AeYF3% z%&2-<^?KLuRbQ{~>>vA|YZ_HIt8VXlz3OQzk=87#PF9`Xb$iv-cD=ObQMI#b_pZ~c zjR7ewR+d;Ra;NlM_S9Ml&qS)Yxb(8t@Dq$IbXcjquIrY zfAsJ0N`%}x}y^f2_;-k@wcl==M@chu`xaeXoAW#?e0|{h2gGo@2b{fk=C}JlDi7muI-& z%`;QEuLwKp2D!r`Y`0h*vm+w>Usp7XGqI*TFdvcsMD(rPS56-h>0c->9DG4})`;j| zWmGshJuj2V_181eb)J$>Un3*^=BFVMklbqaFH%0!FQDKN2_RGg7 zR@4LX4CzG9l7o?1@kx#hJI!;8b3}G$JGJGxAwr^T&%nG(asrp-idLB%N_#G+w$5e)(ND@ZyGy0lu{NlTl zDErKJj?3XaPKsQHcbubgncsCP%FFrpoM+^+?RE0x`o8bXkyC!){w=pg6We`AE>^1T zu8>ou+3p;9vQ4+$({jl&YRqWsMvsSNvzd^H_8PY9^rPEGujd1UX+V`%;(ON3vt}%PLY>oCw%T2+2>C_H&NW3^tr{d-OoOE zrQ8_5_}p*g);Q&J`^XhL?Q?x{4rhFBoSa{uNVkGqh`y0-E4kGDBHf!U%jzHLHj$kT zh;%=clMIx*cZ>_PbBW1^m|U_K}9%kp4? zTV3|KIl)~k`+O+Dohs9!B=--wMzylI)I`%Q7|Dy+STo zVY1s?&bBDo{YXw(ob28sH&#iq+fT0Mv}E_9oWl*tZl2uz)05r1}H7EnaOTF zxs`5Ab{om%oR#dFAD7*f?ADMAcyqG5LN=eB?3y28%t>}%787%m-F8^JFh`T&J=D>BeQoflMngbunWx3TH*e5soiflR1Tn^l64$PEGyV4x^ zQm)x5bKsa<@73l&WjTu(xpLrIx#?z_1HZ}zGq07SPsn{}e*HfB7rD&lc_;d3xd+S- zIHQxzL#R3MwcLz;bD+I^lgR%xVnxrEd%`gXP6;H}9C$>|E7}}*Uhaq(bD)XrIbaT~ zl&xaTfm(7~%kSG;(Vb+gcyr*W+};W1z#chq&>WZ`rwN$@H^|+aXb$X^Tg<#_i0&?> zf;sSk+{qQqfpco_UPzW>8B%w9Xd zF1xefE(iu#7@!~`h#=U7qGDi+7^oQ7frx?uqN0e17}$l~je#AQ*xg;I+}3lQ&iDAe zUcdXV=kxYHWuAKvcBih{{72tC`JYr*b51_$YqFKHp83~4U8$UPk581SUSgW99J6|b zX|_tt>IJ6RsxhnAmu9QQtX^K4^@v%$x-{z;t+OgxB(yU+XxTG}eA3Lrn&DMz>7nEiL zV#oEQ*}Adga?)&I?6{gV8x%V(Ce7B19oLd(gJZ{~q}hU;l=hY=zRW{OjL1KIfCI_}^zDG#;7%wazvz_e_7k zav@u0!*Wvp2^ktkL&#P!L&(-KL&&h0A!M7FA!OT_A!NIlA!K;W5VC#D5VAu|LUxQz z$WE~d84;V1onsTSOKd`RjZMgIu?g8dHX(b&CS=dpgzOcYkdd(o**i8Nqhb@XPi#W= zjZMgYu?g8fHX);96LLUoLJo{g$U(8ILN+gr&AI*n~`sO~|C!gq#|ikkeula(Zk+&WKIOl(gj^Uigv^Q=LN1CKLT1MdAs5FCA(zAqA(zGsA(zD@WKL{CE{{#f6|o7q zGBzPs#U|wH*o0gYn~-Z`6LMW_LavWZ$PKXxxiK~&b7K>7Q*1(Rj!nodu?e{~HX*mg zCgk?mgxnFEkUL`&a#!rCkm;qn@~?m6MfqKu?EI>bf%#pb?Cx@slZ4!#-Id=-`cKFM zaWsTH7&C-C6f=Z895aMG5;KI%iy1;5jTu57iy1;5j~POqh)Kx&*n~V8n~9A-~2ZWKnEFev3`W@39H_BQ_z6V-xbf*o6EUn~=X^ z6Y_U#LjH+O$iK0xLf$L=FaP>C4$B_|W$*tdq_R``zw>9!5}iU*O;%IPy5v8E+NVb| zSusv8oA2KF2M5^8V|U4S-$K^b?ws$n3t64LWWM_q zvUQrArERDde}bv(Pq${FZhR z+N6-*(xrsfDde|wX`!4#eoL1TYE#H>>9RtWLVioT3NU=0#%??F9>`>Ix4n?cmp=b>|6!o%0QExjGt!am%J~l;b2^94eC|X;fsGmSl ze}STP1d0X-6s;>zG*F;ukU-IT0!4!biiQXjtuIitfk4rQ0!14M6m2X}w245`rUFHq z2^4KER26kEmQKroRQjhUl~xW#={HYgTNKO5S5mZfF}pU0^`D|)&WECH>`=6=9g4QI zL(yKWFD7s3Z z=xTwYYXpj}6)3t+py+ymq8kK?ZWJh*D^PTkK+(+tMYjkP-6~LYn?TX+0!4QS6x}IM zbeBNU-2z4T2o&8bR25xNERD#4R8C9xi)MzRH~)JqRxBr9Nzp^a?6~}emH!ky?0hJC z#12LC>`?Tm9f}^aL($`QD0;#UMf2@Y^rRh%p0X)=TA=6|fud&xik=fFdS0OD1%aX$ z1&Ur0C|V#;^s+$FD*{EY3KYF2Q1rS$(HjCq3k8ba6exO2py+LZqIU#}-W4c%PpB$- zpjf&z2U58)!FkaAqWopC?EPXn`AUjDE@qG9uV?+I=o9Bd(WiDO`pgbRpWC763p*5j zX@{b(>`?Tz9g4oOL(#W3Mc)Y&eJ@b-gFw-b0!2Rw6#Xnv^ou~zuL4Dj1d4tWDEeKX z=nsLS#R5hD6Dayqpy)4wqQ3=-{t+npSD>iS>i<2;uRcaA3KX>xs){}=mOjmaR2Jlv zvX4U1Y3cQ;QmbgjwaTHOvsYuKTvmmP|F+o5PpI~4V?L(y7xDC%p6qP1;``Uw>E7bsds zplEn#YN6=8{0Zr7t5)UYD=FHxRd(*Gp=dkjL(y`=6;P0?-wMY{_W?IBRKr$EtO0!1SQiuM*L z8YNJ)k3iAB0!8}?6zwliG+LnO0D+kSBbg)3tAp%8*3KShCP&8JkDjL?R zbaxJ<@>u@Hplq8^^kn++c6h6D@|6@F-6~tyBNQFud?-5B4n@b=q3C!!6rEs)qH%U8 zI?)bACP;`nw(L{lwNdiTu3KX3tP;|OL(HR0olLd;V2o#+uP&8Gb z=q!PvvjvLI5h$7_P;{<9(Rl(z(*=so7buz`P;`M%Rdi&l(qB1{$~oy-$D=|~&-9IH zW~*}Yl@!fxl`XwSD7x7BP;`kMiY~Q7(Pefhnq!Be%k5Bfg&m5nv_sKVb||{qrsx`h zqH6_;t`jJ_UZCg(fub7)islLw-6T+Svp~@;0!6n96x}9Jbh|*&9Rfvn3KZQXP;|FI z(LDl1_X-r#$dKq38)a6wS9o(UW#4dddz(PurpB89Nj`Yg6=`K+*F8MK1^xy(m!hl0eY{ zfuffMie3>YdR3t4HG!hn1&ZDfC|W2`^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7 zP*wDBtI`=ckjlULn{l&8LQ&iNUUl|St8(&{6n)kzyS`5-`rP?Y^o1RYzO+NpS9U1+ z+73nE*rDiKI~09qhobN8Q1pXM(T@T}KM555EKu}|K+&%PMT-QAeiJDAU7+X>fuh9% zMgJ2h`ct6jFM*=J1&aO=DEe2RDF5XA+4+|-e?>iikeyzQEeaI15-2JO6x9e6WkOZa zC#^~^=0GZa^H(^sPeak|Y1Ed=$yZX;wv_$QHx$)5AByVjP}I&2MGbZ+YP3U9#STSH zb|`9ZhoTO4C|bg%s9B(>MWCpoKv5@wq9p~2Itvta5hz+pplE4Q`>I-4n^zO6b%q4 zT34WGpg_?efui*UiUtc54G}0>U!Z6MfuaosiZ&7`+E}1y6M>>l1&THkDB4`0XbXX& zEd`2(3KVT6P_(r`(J-N^sAs9POAe&ckiPw_9*TOF^07^+oO~rk+n2Hv285y=oDW4i z+M#GCI~0wuL($H5DB8siMZ4OeXg50)?QVynJ#32h6e!wDplGB((cS_@qXdff5h&VM zplCmVqWuMmMhg@jAW(FmK+!=0MPmet4i+dnM4;$Ufuh3%ipB~Q9WGFGgh0`eLRHar zrP7=nNM(4sUo<=vt(%^LJgQVqzLKKjO4*|WL(%chhoTegP&CdCMJL*!XuKVYPO?MM z1UnR+Y=@##>`*k(rf8Bt(WwGOrwJ6DE>LuaK+$A@qA3DJX9^Te6(~AOpy+IYqH_d_ zrU?|CD^PTvK+$x8qVolcW(X8rAW$?@py)z@qFF*!(J`gc=Q)tdJL&Dx$A+SV_Vy0ny)2Zy4|oDW5F>`-*M9g427L(!FXD7wlHMOWLQ=o&i|U2BJ;>uidy7bvyiU#Jd!e)<@%E?z!^mr-TYW-03g!7?j zz8#95v_sKTb|`w<4n@z{q3BsV6g_8$qUY^U^ny*%ivmS22^1|5D0*3-=oNvYR|Se* z6DWFJpy&;OqJ;uQZweH>B~bLXK+!t_Mehm}y(dugzCh6j0!1GR6n!L6^szwECqh-x zqovZ}IgrYj^j7P~LeY--yVJ5yOXcJ%Df+UMP2VsSedT;8`q~af-`Jt(TRRkeXNRKi z?NIcC9g2RmL(xxmDEir^=of*aUj>R52^9S%Q1rV%(H{auiv^1QCs6dKK+#_UMSlwv z{UcEHuRu|uCLXp^R1_#`B~VlnD5?=C$^?pP1&Yc7MXiOZqR&gEdvhR_@#+0VUxcE) z(<>ltYRbu1Qq-;{du!uR)Zlz5YP3U9#STSHb|`9ZhoTO4C|be}Ma_07YOzC6N1LKf z0!2#-6m=FT>LO6Ilt9ta0!7OR6fG-I)K#FUn?TWW0!7OU6s;gow4y-KN&-dQ1&US{ zC|X6JXjOrt)dY%q2o&`cs*37rO8?|QD%0{Sle7Ao>LdLJ(sik;*OZg5q-f2WY}w61 zQ6J|+(OPyW>T8Fhwe3*U&kjZX?NGFi9f}6np=ez@6b-Z~8YED(okYDw2wg1z5+%22^8%wP&8Vg=m3GD0|kl>5-1uY zP;{_B(IEmwhYA!OCQvk1py+Ucq9X)~jua?5N}%XyfuduCs-higN>g$ml}*we>K#MT zVM)=kHRa?hDH>Ok-8eK9o#=ch8gGZ9lk8A5!45?y+o9+bI}}Z{L(wEV6rE~^qSI`O zP8TRTL!fA~K+zO|qB8}GrV13DB~Wy>K+!n@MbiX|&J`#+PoQYJK+*XEMKc77E)Xc1 zDNuBwK+!CLqKgEIW(yQuEL0U8UsGC;1F0;|XLdp;YDrH)UQ$y|zLKKLYqFoV4n+MiFXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M(Zd2oj|dda6DWFA zs4BXwrqnVlSG09w4rfj%S}DC__OY6B@|6@lS(EkKHWWSOd?COdI>DEij^vS;W21J@KODhd>}5-2JO z6x9e6WdcRD0!3wkqSgXMZ3K$i3KZ1|RYhObl&;8uR7RzztG^CKQ_>^-`mCIMB}J7i zdwhpb)Z~09YHx?44t6M7!VX2vb|`AGLs3UN6m_yg(UNv3>TFZgMWARYfuf}aik1;5 zT2`Q_t3XjVfuiLEik25BT0x*_MS-G~1d6%~6s;^!w2DB{sscr;2^94ZDC#Ltw7Nji z8UjVVgsP&3tn_6Lq%ttQF|9GHKGN@$-agwqD<@w`QQs_UGa?kN?R+TeXNRKxb|_lM z4n+g(P_(WciU!)DXpkL>*0V#=V4I>L0!8Z!6m1|-w4p%JMgm0}3lwc4P_(H)(Pjcg zn+p_eAyBlXK+#ZvqOAmqwiYNFCQ!7EK+(1WMcWA!4HqcdUZ7|Pp{l4)R$4s=Qdykf ztQCs(O-~-}n3a>Sq-d8c8@5X*+SU0`w3{7@cDF;(9(E|&(+)*@*`a8p9g6n0L(wQZ z6zyYEw68$XegZ}N3lxnOC^|r(=s*5D<@w`(Mef0 zW4BN=!TC^hvK@*}u|v^BI}}Z_L(!>rC_2p!MW@@L=nOj)O|~hTB2aXuK+#lzqO$~w z&K4*-N1$k$K+(AZMdt|=O&2ISU!Z7)K+y#PMKcA8E)*!5B~WycK+$Z0qKgHJE)giY zRG{cGp{nS_taN`4q*BR05ic7biq>t)$DFL3d?iI!W!XD>grcjR4@KA5q3BvW6kTVB zqU-HYbb}p=ZnQ(uTssuqWQU@gZHjIYD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=u zSD@%Vfuj2biXIRsdQhO~A%UWY1&SUKD4Hiw^r%45V**8w3lu#eR25y3l?r?2iY`yz zey$8fJEd1Z=4a*PD=B&=%esvWMbA1Pik`DW(erjFdch7wFWRB#B|8)?utU+yb|`wq z4n?op6ul-;^twRN8v;cO1&ZDjD0)kv=xu?bcLa*w6)1X7py+*pq7MX$J`^bWNTBFr zfuc_Yiar%6`b?ncbAh5S1d6^CDEdmMDtam_ZIT12oRXesd^!~6zm+0?z?PMhucYYv zEZcunDEh(qQ1qi6ihi;~(a&}$`o#`KzuKW_ksXSDvqRDEb}0J8rf9K1(fbpl28 z0!8fviW-EfqHnX()Er2qHYxfp6g`mcT{qU2ldq(xLv41`zM*Id=R;Am9g14)P}I>5 zMV;(Ww4@!1I@_VBiyexVvP03*Hbu(_6fG-I)K#FUn?TWW0!7OU6s;gow4y-KN&-dQ z1&US{C|X6JXjOrt)dY%q2o&`cC|X^hXbpj)UIInE1&Y=bDC#3r6*bkCUde$}mhPIv zX26qQQ138e)f{ z_3co!flbkd0!14M6m2X}w245`rUFHq2^4KEP_%_W(Ut;5Lj{Vq5-8eQplFyt(KZ4_ z+X@tICr~t8plEx6q8$W^b`&VuNuX$iP*t>cZK>1fT+xf^hgiQ*^mTd)a_8D|@|6_r zUYo6RU?|$d`B1c{9g6m{L(xb(6zy$?qEU7z+Q$w>``V#sKRXodZ&Nf{py&XBq5}nr z4iYFDBT#g(K+z!rMTZI$9VSpTR-ou`fubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vm z69kIJ2^5_uR2A)7TiPQBQYoc-*Sm$HRnlA5#@CjUucYXd+U%q;p=hG>p=gpFicYmd z(P?%lI^7OMXV{@=vK@-1*rDi5I}}Z|DLPA_=xl+aa|DW}2^5_xP;{O^(R6{L^971# z2ozl)P&8AZ=t6;_Spr2D2^7s1D7sjn=n{dVO9hH96DXP^P;|LK(G@~f(S+L4RXLE# z)9Ky&Cx@bO=^N9PwdLe1DY~{cn}0|sy3YAfbiEylZm>hqjdm!SYlotn>`-*G9g1$T zL(#2vD7ww2=yrjkI|PdE6ezk&py+OaqI(32?iDDyPoU_2fuaWliXIdwdPtz?VS%DY z1d8Sf6g?_X^q4@=;{rub2o%j1D0)($=qaJ9=<3?i*Ex{NW(Hnu6+ zM4)I>fuhX>iZ&N0+CrdcOM#-H0!3R16m2a~G)$mq8-b#21&X#4C>kzMw7o#l4gy6x z3KZ=mP&7iIXlH?giicU{&!rrZ1PQH?&y~^40$A_Yk z&WEDC?NBtz4n_Oep=e(_6zyk+qW$eqG};bD2iT$LK%1h21d7H86df#3bcjIFp#nvR z2^5VLC^}rA=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZCg%fueB&MJEarjTb07NuX$g zP*t=?xwKghr1DjIq`zk+PA->|ucYYIa(2MDP;{E}q3Cow6rEv*qRDnBnqr5d zGwo0`)ec2x*`ercI~1K`Q#4JW=v;xK^8|{f3lyC%P&7lJ=mLSFnF2)@3KY!}D7r|X zXtqGn#R5f_2ozl^P;{9<(Hw!I%LR(A5GcA*py(=rqN|0fqKW0w**TC(B|SwnDHM%N z&s|?rE+=0}(GBJ7mhqwJM(0D(TssuqWQU@g?ND@!9g1$XL(y$^D7xJaMR(Yt=uVrW zy9A2v7AU$$py*zKqWc7j?iVO}K%nSBfue^5iXIjydPJaTo$D0*6;=ox{cXN9Vw>&m6qav+su(!2Ms4@K{%=Zl^zmy@rg=%sSDXhJAj z;Cv{0*$zdo*rDiEI~2WUhoaZ*Q1pf!iWb_T=uJBmy=7DMwm{K40!8l%6ul=<^u9pR z2LeSO3KV@LQ1r1t(I)~$p9&OxCQ$UbK+zWhMPCXOeI-!zwLsA~0!7~n6n!U9^u0jQ z4?fF(xAOm3E+=0}(XZuf-HD-Sk@KPGH#-#lZik{j>`=7W z4n_a7L(!jhDEi9|MSt6&=pUP+e+7yPt>Ym#MMZ(4RsuyOfub6LqD-KuR-mXXP}EwW zsEt5TTY;iFfueeWqILpB4FW}t0!0;pq9%c&_5wv61d5grs)~Ltm-fnmRJQJv!}%o? z-I)|Mw=O4NNzsz6vy)E^MV*}wMP2Mrw3Ho+mbOFDGIl6h)(%Bo?NHRs4n@n^p=f!V zq7?*+Rum{&Nua2^K+(zqMXLxDttwEonm|zxfuf!QMXL)Gtszjj+gv9b1>K$$?ZBFQ3Ed)VlgezgN1FXh7?7@|6^=*E)OZ z^iVX|`A{^(4n^zRp=bj;6m4jSqK)iOw6PtEHnBs|rgkXW%%*5_fub!0inbIe8Y)n< zl|a$f0!70Finb9b+E$=wJAtC%0!7;k6zw2Tw4*@LP69qyr z?@&}sPaaKbT~5A|qBB}&!>5L#$Jobb+Gt1&U?}6kQ-tG*h7HLV==L0!0@I6wMYWx>%s-5`m&i1&S^cD4HWsbh$v$ z6#_+93KU%>P;|9G(KP}^*9sI}CsY-k*1B|T4y4i}JzafzD5^~#iFJMJa`KfF-PAgp zb#^Ga+4)d(iyew?wL{Tub||{t4n=p^q3BLK6y0TqqPy)-bdOEZy#ht|2^8HgQ1pO6 z(Srg-4+#`KEKu}_K+!ybqDKXa9up{fT%hO)fui{WMNbM8Jta`|v_R1_0!7aX6g?+U z^t?dP3qn=Vjjc-$=RhjEw$9vkx5 z!wy9Y?NIcl9g5zvL($uID0;^ZMeo`ay(dugzCh6j0!1GR6n!L6^szwECjv#E3KV@N zQ1rP#(H8Mc)b(eJ4=#y+F|q0!2Rx6#XPn^s`V^w4imV=GUUZALhK+zHcMa=?5EdoUyg{q=OtxH?vKq{lU=5T%sMYktKo!XR>ucTkzM zw7o#l4gy6x3KZ=mP&7iIXlH?Yj)py+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o51d7H96rCtg zG+vDJ^wTuIQ=sux#H@R7&5APH$6A zzLKId+hl_-4nlXx*dwnw?okko1zN@ie?HF zT_{jAOQ7f?fuh+0MHdScT_R9)sX)ja9f7bvYlouy>`-*SP0<4aMGp!TJtR={ut3ox0!8x#iXIgx zdQ70`ae<;I1d8Sh6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0K+yuBs_5o6 zrR#Dam2!ID^(~?3>ZIu9Hs$0iDSEw4_RO46^oH}HXrUd7-n2u}TXraV+YUwV*rDiM zI~2WVhoblGQ1pRK(T4&>9|;tFEKu}`K+&fHMV|>2eJ)V+g+S4l0!3d56n!mF^o>B# zw*p1q2^4)VQ1pX9(T@T}KM555EKu}|K+&%PMT>;0qF39LzR!VFUQaK2ycUXjr#nf% zwJ9fGNzwn>WQ|vbqCcGvMSt0$=x;j|{bPrsf9+6IXd92*Ls8KVMXl^mRI)=+jZIM| zP*f{WR2C>|El|`(ps1}tQJp|hy+BbrfuaV1qDFzDia=45Kv8>vq7DK@O9&J-3ly~o z6m=9R>LgIKq(D(;p{nSQHl?+4AeEWviN?jD=&!c<=+d^Fd?iK8w#|09IuvzvJ`{Dc zL(y_}C|ceQMJw2$Xhk~|tz?Iy?sh0z*$zdk*c7cQP_&vrQ4fKlo&rUy3lyy(P}EDH zsJB4TngT_A1d7%YDC#Rvw6;J|KY^nD0!8Zx6b%q4T34WGpg_?efui*UiUtc+MN79W z9iIcKl+))IEz`F8NPk`$L)w;;ucT6dh!TqA_+TI@k_HhuER$P&*VIW{0A&b|^aB4n;@U6dfs0 zbd*5R(E>%s2oxPFP;{I?(eVOBCkPac6DT@SplG~6(MbYD69kG*7AQJJplG5%(IkPQ zQw54n6DT@epy&*NqRB#4(f(~qwKwF7c2BQ>j1EP;(={Md+Ln{Ar0DFnS@*f2=p5%m z(KI_0ook1p^XyPG-3~?P+o5QN9f~fnL(xn-6kTXjG)ti9B7vgW0!0@K6kQ@vbg4km zWdcQW1d1*fD7r$R=t_a2s|1R!7AU$#py*nGqU!{Tt`{h}L7?bHfugwrMK=i)-7HiU zO>J8mngglq*O0?GD-^Am?j+sPww!z=MR&B#4!$`Q-RXQNy2}nlciW-p9y=7>Ylouy z>`-*S9f}^XL(zkFD0;}I=wX4PM+A!I2^2jlQ1qBU(c=O|PY4vv7btpCpy(-qqNfFl zo)IW|R-ouPfuiRHie3;XdQqV0C4r&^0!1$i6ulx)^r}!*bX(ifc{z~E{Pf`d_E2;} zQuJEea`KfFz1cRqN}%X#fue5&ioO*n`c9zedx4@K1d4tXDEdjD=x2eV zUj&MN6)0LHQ1qKX(eDC9e+X4YZ?rAFnFFcJPnUfx3`O0_`B>bxoO~rkf49vR-yVwo zaXu9NYlosjT|9CRMMXOlwX#D|$qq#|b|}j1P*iJ&qOwgII70 z2^2L56g3JIRRoHf1d7@V6m<|NT0)?xS)iyzps1rjQ73_-B?XE)3lwz`C|XLOXlbFU z=+CyLW$wro{gFO-=C4rnYDe5Uuw7Nji8UjVV1d4hK6s;*x)JLFbErFuG0!3>J6!jA* z>Mu~VjzG}>fueNYBspR#$zb zzaWv?u&$hZB}JRoWvAW~iZ*jT6m4#YqAl!Dw51)2hT5TMD?1czZHJ;^b|~7$4n^DA z6m2I^G+dx)dx4@I1d4VPDB4M&XoNt~&H_cd2o&uqP_&ys(e468dk7TmDNwYRK+#Bn zqP+!*MhO({BT%%jK+%2zMf(d?MH|-wMDH>CkJ$GLy zI@tM8bch{_4z)wkVRk4QYlou4?ND@t9g2>$L(x%oC_37v=oo>bV+D$i6DT@fpy&jF zqHzL6Ckhme7brSOplE_X(a8curw9~H6eyY`P;{z5(P;ujrwbIFAy70~plFIf(U}58 zQ-!Lc1M5mZ=0Ga5(iPSRg`!vTf0mt9S5Cf?qI2uArUygOdCrHT>2@eO-ws7H>`-)p z9g1e!q3A+86wR_j(M5JBnr%~bu|Ux!0!5b!6kR4zG)JK5a)F{N1d6T{D7s3Z=xTwY zYXpj}6)3t+py+ymq8kK?ZWJh*D^PTkK+(+tMYjkP-6~LYn^0ABPF-p397yH%bccFc zD7rA+FS@<1oO~rkch_Y*JsgVeaXu8?Ylouy>`-*S9f}^XL(zkFD0;{aMGxDd=n*>< z&9f?6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkF z3j~T@7ASf}py*YBqSpk9UKc2OL#Qgcv#vBQ2U2-BT@HI!C^|cRV_H~OPQH?&cj~fB z=7pknoexFt*`ertI~09jhoTSdQ1p=QG^K+%^1MPCUN zeJxP*jX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqUiv)^(6Day!py&^QqQwG5 z{}U+sQ>ZF>tFH7|4x}UJnv z!=|X0Kv8djqBRAI`Un)QB~a8?plEG@qJ9EJ{RN8F5hxlUP_(W<(LjNsK>|hV2^0+$ zC>kPAw7x*m1_DJJ3KVT5P_(g7RkVD4Y3m$FWoG*1nHB1*kMzf+mu5GqFDG9~(H8aD zp-+XPEu9ZVL+wzsl^u$vXnUKY9R!MY6e!wBplF0Z z(ar)zy9gBRDp0hWK+*03MSBPo?I}>Smq5`-fug+yibe?(?ITdMuRzg$0!8}^6pa=r zIzXW4K%uH=v-;BcIgrZc=_#VkL(!Y*14It0FDG9~(V_L(UC)G~!<-LAW9?9MxE+d) zutU+2b|^Z^4n;@Xq39Sp6dh}aqT_6eju$98L7-@yK+%Z;MdJmEP7)}ZAW(F&K+!1z zMH2;zCJ7XsDo}KqK+)*}MP~>UO%^DcB2aXuK+#lzqO$~w&K4*-N2n?~xW4pu4y1BW zdf)XSp=e}!@@QIpIr&P8&acn@d@dBta6S}WV27fab||{g4n?!zkR|*teB~Wy=K+!bdHp=h2RiXOE?(PMTfdfcYy34x;d0!2>> z6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBv7MO`zy?fuc7A ziWUkKy(v)imQYo6Pkm{>97v@leN4!`p=fe?$L!nn<>V_VdcQt9eL*Pt!1+-0p&g1o zvP03wb}0J94n?2Zq3AO^6n$=oqA%=F^rcPFR{}*}3lx1LQ1q=p(RTtx-wPD|AW-z9 zK+#VEML!D^{UT8Gt3c5rfui38ihdU;`a_^-u|U!P1d9F?DEdpF=x>3de}t-{ck4@Y zb0C$!)0;uw3q>}fud%Cq85RojsiuU1d5gv zDC#Uw)J33ZDS@J;1&WptC|XvasH;FxH-Vz%1d5gys)~y3Nj)GL5GYz#plF~#(IA1M^#qCr3lt3zC|X~jXaj+w z4F!re5-8eOplB0;qD=*gHWR9fR%%!3p985}pB~(I4@Dm*MVq%PCtpd?R_(H#7lxv( zoexFB>`=6g9g4QKL(z72C>m~uqV4Taw1XXrcC!L($Q8C_2Ut zMaSBq=r}tR9dC!C6YNkl&Zg)@fuivOMJEXqO%NzLS)k|?fue~5MUw=IP8BFRO`zy> zfub`6iY5ybO%W(MQ=n+7K+#zOMP~~Xog+{*O`zypfui$-s-nZ%m7d6fR8C6Ye#VBP zT^sT-y`*kv4n>#S z6kQ=ubfrMiRRTp<3lv==P;{+8(RBhv*9#QgAW(FpK+#-*qMHPYZWbuIMWE>VMNbP9JtI)`tU%Fo z0!7aY6ulr&^rAq~O9Dj;1d3i3D0)Sp=v9HD*93}Q7bto|plG2$(VGHAZwVB=El~81 zK+(HGRnh(JO55Z>DsObm;XDwE{z!`6YgbOblA@2=Wn(`KMISpKiaxPJ(WiDO`pgbR zpWC763p*5jX@{b(>`?Tz9g4oODf(8R=sSU;?*)o}5GeXlpy(%oqMrqdei118RiJ2* zK+$gkMZXIa{UK1aSfJ>C0!4oc6#XSo^tV9KKLSPn3KSI@;(<9uMWL$bgLb70av+rv z>FtdlhN3sS<)c+YIr&P8Y8$e9J`P1?=R;9zI~29CLs45h6xG?GsNN1m?d(w0V27ec zI}}xHikbw9+6xqQ5GYzgpr~1(s70Wtqd-w7fubb^iaHAvbrC39N}yMBswO`vEwfuiLFidGOPT2Y{AC84UQrlIt14y1BUdShDFP<^DoP5P+N?hWPSD=Av7 zA^ZE&P}IZuP}I{7MXTGPXbn3Q^|C`zZ#xvNX@{adb|_lQ4n=)!iq;k=>L*atU!Z6m zfuaEdMe7O_4HPIEBv7=TK+#}kAZZAW*cSK+#45MH>qgZ6Z*#sX)E)224dvu3DcYtX+whA}w5{`@XgfO;4Yxzl z_I4=R!45?`+M#GCI~0wuL($H5DB8uQXjg%v-2{qu7bx08plDBlqP+x)MhX<|El@N{ zplBa~qJ0I5_7f=DU!Z8TK+ypLMF$EL9VAdRMxf|mfuchMiVhVhI!vf4+Pa}MItNmD zH@&@aSSad{UI7`~P)@#*qN5tJ$zO${qn!^$$Jn9hSUVIQXNRKW?ND@r9g4=;q3A?A z6pgn-(MdK%69kG*7AQJJplG5%(IkPQQw54n6DT@epy&*NqR9e9Qv{066eyZ1P;{0+ z(b)n;=Li%{6DT@Ypy)h-qUi!f=L;0g5UPrfXeiyB1F6)dA7V#_qAZcRprM?6B}ErC zWG{Uaie@_>iY~T8(Is{$y3`Ium)W6cjvb0Fw?oktb||{i4n2|Es){~tC{4(LRA!|2U4IgaMx?i_WsT+J zD=BKzm|gyJC~E6`D5|qVQN10C+S#F~!45@@b||XYp{U6YMeXfS)WN1`34x+!fua_H zqK*PZodk-O6e#K}P}D`BXeoiBr3H$X5hz+#ps1@rQ8$62j@MM7AP7b zP_({4(FOuV8wwO{Bv7=mK+z@wMVkr~Z6;8(xj@kt0!3R26b%(9+Df2kYoV&BM`Nje zQLbp?q^M^o+HSdg3~MYWUrEvM#;oV>p=f*OL(vX)DB95uMLXG{XoMY#cD6&&E_Nu| z)ec3w*`a86o1#4giuM#J+Do8lq(IT$0!5<)iuMsG+E<`xKY^nC1&T%s6dfQ?bf7@d zK>|f%1d0w8C^|%-=um;8!vu=P3KShKP;`V)RkUqmX}cUqWlnly+IFGniu4%m$i{N= zl@uM@m>sb=6dmV$C_3H_MJL#yXq+92PP9YOcsmrGWQU>&b|^a84n?Qf6ipN;nj}zk zszA|c0!60_6rCYZG+Cf%ia^ns0!32=ip~-!I$NOV9D$-~0!8Nv6rCqfG+m(Re1W1F z0!0@H6wMSUx=^SpI=ZoRVGg7+F8vTYCKL@y*Q3p9EGJ({(It)9eSe0cOPvozm)W6c zjvb0Fw?oktb||{i4nY zMbFxy=s7zSJ#SO=f=na9Qg#txy3KYF1 zQ1rGy(K`Y~?+O&XCs6dhK+y*RMIQ`?Tr9g4oQL(%tkDEh$;ML*i1=qH<^ zp9PA35h(gqplFdm(Qg7pzY7%oAyBkfpy+=BMSltu{UuQJw?NT90!9A{6y?`l%+9|^ zHARYw0!6I^ib?`SH3CJMKvAtgQCX-e`mC{ZU=E~mMf$z5pNFDP(vP>+m2&cx6xCO< zGh2nCcFu>Q20Iir+M%dohoUAs6t%ZQQ3pE|En$bEW;+zM*c5dXDC#6ow4^{$XMv(F z0!2#+6fG@Kw2VN}vI0e21&X=}6fGxEw7fvk3Iatd3KXp*P}E(ZXk~$-RRoGw6)0Lw zps0sXRn)dpx-|z0g~*n(bLBCtpcX?@IP^O(|0K5GdMGplGN-(N+RQTMHBo6DZn7plDm6s%VW$>9-t6WmI|{ ztyd@-l3tD7u2N3ElA;|eS;ulH+R6D)G{O!=JKLdX7dsT~YKNlT>`=739g6m_L(!gg zDB8=WXrw^V-U3CV1d8?%DB4$`Xg`6X{RN6f3ltq7P;{U`(Ln-5V+4v07AQJIpy*J6 zqQeA=#tIZ2E>LuYK+%x`MMnt~9W7K9ZC@!3%z;!6N$;55Ary5<5Bra)l#{Qd=!8nP zdz(-+&iPPuq8*CH+o9+rI}}Z@L($20C_2RsMHB5%G|3J{r`i;qCQx*`K+zcjMUw@J zrU(?BDNr<3py(`tqO%2x&Jie@CQx*)K+$;uMbia}&KD?}Ay9OIK+#Nrq6-CzW(gEs zBv3S4s46ajJu=Fzi zWufSdbV10Ym2&cx6wR+>U$qNGPdXopp0Y#H({?C&#tuc#+M(zMBswO`vEwfuiLF zidGOPT2Y{AC4r*u0!1qe6s;mqw5mYSY63+)1d4hJ6s;~$w1!Ys)UK&?Q4XYXZI;7n zXsSNaKR-R|*sH0Wd?iI|HDwPh5sLacABxttLs36F6!o`5(K>c08eoT_b?s0z&<;g| z>`=6xP0?V1q9FoB>kAZZAW*cSK+#45MH>qgZ6Z*#sX)kbEw2eT~wgN@l2^0+%DB51ADq6Ft^kEL9(l0%@?-Po4OfT^7&{R&olA@iP zvSPXdi*1eFcj46DZnW zplGx}(E$QQ2MQD&Bv3R)py*(MqC*6V4izXmOrU72K+)j>MMnq}9Vt+Blt9tZ0!7CN z6dfy2bevFCv{O@Qr5s4*o^%s-5`m&ig{q=)O{Fn8kjmHP z9L|ZM=z}yaYbqySNzs)}*;!pe(N)feqO0vtbd4Q~uC+tab#^Ga-VQ}K*rDh~I~2{e zL(xq(MK=o+-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZWP;{?A(R~6%_X`v~AW-z6 zK+!`2MGp%UJt9yvPoU^gfuhF*iXIoLiY{*|-JS!f45-iHToH=Kq$jeUXeuXPNzv0y z*{e&3qGy~BMbFxy=s7zSJ#UAi7wk~^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&nLyF! z0!3d46n!aF6+PKh`XdKYS-ndR=c!P1K)R~&tEO`Dl@xu~lr7mc6n*b}DEh$;ML*i1 z=qEcA{cMM#U+hrys~w6K*`eq+I~4tHQ}l;G(PDw3{|OZRDNyv6K+)dQ2^7@`6lDTMwE{(Dfuhy|MQsF%+6ola2^7@}6txqoioR(ot(OC- zeBYGA`8E_ClU@#KXkSjglA`wQvpts!MID?EMN8PBsM!uhEp{mCXosRsb|_lX4n>{q zP}Ic^MN8QfEiF*Aj6l({0!3W~in<9DEhkX4yg<`*k=4n;%kP_({H(FOuV8wwO{ zBv7=mK+z@wMVkr~Z6;8(xj@kt0!3R26b%(9+Df2kYk{I+0!7;h6m2U|w4FfFaDk%j z1&VeMDB4k=XeXhnsBinyvpJB;qV&?)+M#Ife-GH&my@rgXt(y+H!Fpr-JK6bd)T39 zPdgOtWrw1Xb|~804n?EvP_&O7iuScb(S9~X`wJ9}7AQJEpy)t>qJspA#t0N0EKqca zK+&NBMTZF#jTI<5T%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeHaY9wmF6~Q| z?zy5_>5XZ-hN7p_RgEXMFDG9~(aG(z-m8S7Q=AV)6YWqm$qq%Q+M(z)I~1L6hoUp= zP&C;NMN{lhbf!(wRDq(i1d7fUC^|==XqrILxdKJ!2^38iC^}!DXof)11p-Ag1&S^d zD4Hcubdf;OY=NSS1&S^aD7sXj=rVz#IRZtO3sprYwJ+_M1F2k<&ul^{`Zawd))no` z$yZ^CLaS`~HkbD(7MgqJ_qq$s!}5=#t!W;cze>`&d3yeXu)g`O{7zM+d13zTY>DPB z`Da3QY95)RT&nrn{0)>{o4?ENWv$TMC%^c1<>uqM6$(9?AIV>C>D8RAR4A;~yyeP; zLjUG-S1l9_wB{MR6$*xYVPq3~(*@TrBum(8=zE)>3P{$N_6@MH6e(+h=Pn-7{%DE!fU+ss1Y zua@6u<^TH^TLxX6-XhyF@zVS&P;7Z-PW~k*wlrRue+`N)J6xTA5sEFdug$*-#g>n* z&%X@CmhN-&uS2mV{Wkj*iY@8ak*{2ANxx6JN3kXSLf~G-mh>B4*DAK8U&-0O*phyy z;=p1{`lWb7iY=GS%fBGSmh@|>HY>KI-zzk<*phxR%r?cA^qW1lFSev#%`l?al0I91 zw_;2BaP+;3E$P#(_bIldk0%~oY)PLlJEqu@J|Oh4VoUmj$0Lg^=_C4%Ew-f3SQ}St zNgt9mq1ci>xwPudXu@umUO|ut;Lq~j_*5*E$J=0_ZC~ydoCX=wxl=B%`3K~ zcRf8(Y)NlhdAit=-goePu_e85yr9^UUio{i*pgnld9&D(o_l|{*pi++{jk`Qp8fi? z*pi;U__ElN9)EsYY)KCwek``6dw{+;r;w|Ui;)&Ex7 zqkWg+wzW;CPQ3B@W4jc$t8Kb_@iSMP)TKB)t6yp1jN=NOpNun$s%L7OzMp^Y8OQy1 zX!g0EO&FIS%IcpTJ9vZqOl{Mo$=a~#RNu5+zt)pOOE%-nJM zRc8cqar5fGHrV2}vlZ&*VpGs4oE_@gU+8USV#K>uHu@srZB0W?6N+R7i`}yI@Lz4n zD-DmgaSjh~O52+sKjUMYXPc4Be|WCDzXrE7zTL`Siqp^DxMoGD>uc7=E%~90YU+&> zqt?VW(1yRyJ<4zM-NbVj_-%f^@TG@r-Y<^?)47!C{Bh}DUmf93XYAl#=lX3j4$mIq zxA}C_S05Z1>iW2~anpH)>AbLQO&`C>(#9Ew_)WZh2bB0tHa>RA*Vg1MHA%_VQocFr zojLxjJ^km?H?OcZDQ&NQ`}%KIS|hLJmK}}zgt~51n^8fVl(tWAdH+IN3R|AjpF3q^ z(CF4v-}}P4Y*RkJ`RDDXQOI^bH**V_(s?ITXZwwwdiIhhT_dmM%IC*5_-$^v=d3GN zhPrlAn=5Iv-}ReE`E71_=#y)0^IMw(D_*v>ZqxZ>%Qasf5$d|9+PqDhgD>nIOy}Y^ z)?Dw}q_q9wmtM=l z`_7lEabK`?hFdy@SER2BZC~RX3Yl%_$-=B9i>GHTu3Iv_p>E;g1&s~U8yjY1 zO<%lxVdDY^rZ>!3y0~FULO(aW4Lvez;o>>-<}}VZtRa*&d%?VhtopeP%d!T}T`;|V zZq}07^@|&_7B|dqSW>?vt6@;xlE$So<}Ao+T(Ds7^x5@u<}b;bHGO(r{o;99IoWlC z>jq^H%BjoAc5r~f0rMBkZy3-}KW)x{oa}*v2e{q?t#`9tS##!3pSyHML)N_d>9gm| z|9?IkOO`K5TobcqXXP%Qv2@P-1^EjWHw=ici)D?A{Z$gIk;=sj4zYExMv1OT6Id|!jx~kk^WkcCawy^&f$NqmJ!D01{4Q^Y6LegkR_Q2^*vbq@!GwYYm zZLDitzOZ4*z}e1S6Jf@j`HdEAXEFWirZ1Q`Z^8V!`h|0hnakDrg>|-4rswtp3 zbB>!-fI?o_KI7Jj9~m6>y!QXqj~7mf%nExQBV7i1u~D9vQtq`&u?8t6UVFc0S?=X| zJyKjpcu-dNp53jlAO3^d(;r(b(@RU~>$S2GrlsWmZ`IV4e6LeV`=0&1)EuuQ0ai{uQPWlPfDYqx8&h3a90*=(hzL|TpV zGAwlJ>1FKd#ukhrCEE^F;f{8awbI7x>xvEK$ALE3Ag_y?P>Gk}rks`Knsvz9%eqHv z1f#t^DIGPdLcN-evrpnU-K-39gJtFP@9FjF?RAQ*aIB}AGFv;>|7et1*#rK^M`?@9 zSPyqIy7P?vr};lw08OadzgZvuNps%^Uyxv?`u6fV^{{dMN1M3QXwQbv@Qu^9_`lvR z`+sYC+8!B!IRC5l{~xWmj4XfM*-n?z)Apf^0d7NQ`TI*BTPgp#5_fVsJj6?nJhpO_ z7mhp>9_a6Gudf^!tVWx`V5iMVIyiijKhD&YegC^XBz=%gK2o|<`!UT&_ut1zYySvg zd$8?T!Q_`V9W#8e(+HC6(L}hYy0WgYs;aKId_rz%aY0>f)!5py!t$CBJ<1BJt8>Q| z*40#0)Rk70j}287j;+hd%^w#ZBEP1(*4pP+lvS1%*4U7><;5DVD1Thtw59=bs|xDM zD{5@u>cXm;!h(38@s&2x+Vbk!%E}7Yqpq@eQekObQAJf*ZcQ*n8&&hc^GYl7OX>=8 zYjW$#Ys>NqtK4!_R0Ts19+5cV@`}3Z+Pv!gs$w@-QAKTefj`*r5##(ive|4_6;@YP z*c=998e+q+F5J8qR^?VF%sK0=ta@x+UTsm4jla5hN@2XozbsjCnOmFwFm6reWhc&P zad}-W6CSCV%PDF$NPgAi%9;vWU7Me8md0D7?EbZdwS{#>wx;5}Ds!ufYbM8|le#Roe6luO(VD!074thmM>b5&t( z!DN47@|p=-Rh?@i@;9}uV2RB%E2{JBs%t82ofevo+J?cpX*QCC{VBe{vM0CHpK@JA zWnp=|A1dcn6^|WPQ*LXtuDY4LxMeLs6R!2;@Kd7XY!FLtZg+y zJ#%dJ#m81$Tve1?SD2q)my=hl-8{e9uIL|H3W{^b)>YKjRMytiO{gfXvHd4L3ibwf zP;rMJcj!vkI|~XY6x&s0UTt--mTliiJRSwRl9Sn1vfH`c`bcPAHOY4Ax{3*fRYj#0 z6L+3yRr%QXVbi?IEsGCOTxkb0ZQ@EhoFpDk{Y9!a6XFNSLGcxqm#}i&25Opg;Cn)E z+Yq)&>Ix_27Zw&I%(7O99bs#7?Fdm)IJvGUx7h9FY(ov0Gj|JdwSR$+6Gf-UWq**0cz zQLs{iIT)5O75}*7HjX>O`DZiDWixNs>FaXy^J}Ye^K}S|&(AnJ&rQs=1+6JAE3~cT zk7Go9E9WOnu+p|sbydE3l$&2uJRvye3`;oGu~XW~d2G3VV)j)SY=gLt+-3*Mt~ z5i6%KzU5qJd^RP5ZF}3tYjwJ_*=!oXCYo23Yo~N6c-ijDc*o}Q&v$B z%)OoU<2~~WOG|4@bE{19vBlNqvpZF>AXvpdAIxL6HTM^>*+ILuI?q2{*Hw?RYm;C| zJDhP~OPFL?p&hDp(ZZD6_;Tzh8MG_(Jz6?Haq-;{cJzQ9uXXFfRHX?Q(wpPOVyqP%v z_H5SVO=&@ee;|#YJhY92O=1TbZOWV+ouurf9bbX$>)CY$``6SJj0?`&%}?^f5{B1t zs?3f=wN?J<$Uhbq*$Sy1mv9uu-O}92?vhdGS?jVx)Xb&xr)Lkzj?Y7|;;IVs3+)II z-;_0ofGu=bHfjOD(F<$nFK|?b8EpC|GP`{*MkIVt{rY~GNdisLJjSb5N z%o{w|K;!JC^QKvyId?&Q;{baGINFX6GaRrXXD&Q!=zt{)2h7MBW~6@c^x32Bq2OU7 z2Fx2c&mJr8HDk%by=E@V955?$K*gZU0rs?M^mLnn0W;?{ELl=Nt6{+0hWWD^XOGS{ z6zqQkoJE%0`fi-FVE%w5_B_t&5@R#!8|&lQU&P_f-1NN&PCV{f-rvZDl>JO*Ztqz-xU=XRW!f(Y_g{yH{XBUU1N{O^zl1eV zSyeHv*lsUvQo!dfPjc*H-6r7QpTuuc7=b%- zB`O9-l%m`Md(yMhEwnFzo9b9|J$?<;baPdpGir|Am#}EI7UFZw)pnxvzQOtas$w48 zyzO+x&#iV(-Qo{yY#)k`G=966o991&i}y%akyV8?|Ms%nKN50Z?&c)8rSs>>u8eFM zm?yg_wL8D!{9^y~QkiRK7k?-_M+6NLDcqExW&Tf_qOZ`FYUO7Ix`2JEfv98vh ziP_532sJ)?BE}lD1BW`@?VjecX-xJ6pxPZ5o4j;`{M&0_Hg2=0e9bP$?WhO zwCUo)>CS~u;x%ym`OhGp|G3*kRum(1*B7Bf{9~V+MR%9RAc?mW_FT0%-;N=6Ot10R zQ+%juyBD@+2YNohdP{ie`hV&L+k%E^OK16O)ZOthlWtec%?sQLo;}ltB`mTVIlJer zD=N*cZfZy0+Dd1(dzipu^_}jw;@c*_D8FgDBt~2oow|_&p z({ZEeim{;Zzqn>}8+dYIaC6LEVe@_8$;%xK7ia!_xX0CgNAM87EO$~}etC^fCW+6W z{aO3hQ)6)d#&X7=)%l}rdYGMKkJb`*rKaaWZefF+pxMDEe%J5D7+;NvzQu2wwQl|A z%>HCKf;XMJf``Vgr@L452XaqPnQQ-KYunzu&9|%YfB%w3@PxSOO!O~@nH=sUa@^Ba z#+^9JMa89dL6-PHq3M#Ox;kI4?KE2t$cv2jgj81w3xZ2?zYGe_kj-X^8HgXI<0~xT zz~$~A8IVZ?qQ_61{@O}>GU|))@6NlyQ8@l6jq&=g*s#|F-Da(-4US;$cnjCj*|ur( zhp!3uG4>G0--LFi{#T_~2s_-_*+|#!dL@P%pyACL(!wrC&F%ub6iK*7p=bQ{BF>e; z%|)P_&Axwwr2QyiX%aVnvlm#jn6>34JagZ!DE_PcE8zjHn`8fBO6h|78RM27TD>%Q#VNQsVyW#Z zzb;Mu%LX3w`*V?S=#{R)wM_g`rR}R+kVq$9zsm`pu==BM4>bLb;5wKoyTfhsGf8|W zOWZGlIk8dr`)GWv$7-AIgwF$33zPX06%rBDc~m zxF^|tZZnM&W-nL|!R}E!zrY@|)RpGP=MCSTtoAbS&d)3T%b%j$#A^#$FsPfSgj)qW zxoJHIX8_kbxTa@iRt6W!_OvcO7rr-ke29bmvVvxJi{><2FTNcU#cMjOx`)<@uN^VF z!3ywKpsiegO*X%PZyJTYyvg+z^UN(&b#1l1Vx?Qye|c=_o>=bm5=GN9LOWX|JTc74 zZo0X%SI6~&mzzCz?-9QxV*2iE?w_Xq-R-Bd$Z5zel^aWumNCbka>dsw>mqmtn($(O za3A2WoW!e3|AuX%y@2ap!miM3vdmKO@ZG(DxAURioxE zy6|dtv*AW>J3_537W3vt6WlELT^wM8N0xPU+|e@PgyZ$NsuJ5+!A@Ch8@}n0*~DDC zY39(nQ%m=(#+@RA_0#m!Gyd4G`Rh{g-QT}c8(Zb>i+5Vn&F&4ITK+EK?qQfTbD5u; zZ!5j1&Oh6S+??><1#WAcWZFFw?_mOS5-vX6-BNH2bImAK+hKlTkYVIT48z@3!^Yi!4?B|}>=PsU?SvYT6!;BgB(p(Mi*YzLa z^FG`?{_6+&_J+)s_WO_h*qg?WY~8X|$h~WsANTI$yw;spryTE{kbGj~q@*?BQ0_?U zTkqcN8w%V1-i5po1Ih;4-9dRMrERnqe-a0Xxc8(c{6zF#YEZ8|+b->FdHN&_;g)sKPI=5uxqPQwzf)eYQ|7I_{)-WP z8bf_%{F`g6X0Ko+o~v@2ovX4#|K=snror87XHCgH(zl;p_M6tx{!h9$f_fA?QmX-8{{2+*R1a3&;Hv#U+e@xm`%BCXmp8g< z`8Cxos(-4sv-R)#@20x9sxv0ZG;sS=l5G&Tg zR7b1ksaC4is!mruM0Jts(W15)zPZ?s>P}msiMb{t6rgco$4*Bcd0(0`l#xYsxPR%uKJ$pr>a|3 ze^7P)y7glRWxuAFpZs9LI8tvW@uUUjzW0@cG*k5XN& zdaCMKs_RtUe&y!(8r7Rs?^1nG^)c0FR9{wg$86XBL)9--zft{3^$*n~+b`YlsjBI! z8LB;0`>OU=9jv;yYOd-y)e6-Kst2jgP(4(2vFdWwV^mL6U88!g>Uz~HRIgXPP4!;Y zM^xSaIl1L~Uez6!Tz*&e6V03wLrB* zwMuoe>QvQPs`FKssvfC&oa!m6XR2PHda3HwsyC_LsrrEGCe^1^Us8Qj^#j$Yb_&sXn3lqUu|!AFFOv{ZaK#RnJaXZh2d)W~gSW?x8wJbsyCN)iTuys&%TfRTrtQ zP(4odG}UueFHyZl^;XsUR5z(UtNNPi`>J24ey6%a)xH_bU%oWe4ywIXhubBbTmF32 z$#(8`xk2>^yP$OWMAeJ!obB>;s*l(S-sNXiKekIam%mZn&8`t#9;`aou0>p4u6ny& zYqJGd3cGLvL>zCrb~!XW>ky63nc4_93{KFCL@-d!5x$5j8c3t%^&sTD!Z z+drrkswY(k`CQc(?1IY;|E_9>NkQ(ZI%P_bXQ^&DFvvHlesOS+e^l*XALNm$i>C+q zXw`cgg1lMv?^!`^F*~RQhXi$h)l=pM`Fz!v<_GzG)lQ3o+*|d)B|)B}dil~I-=ezZ z@F4%JI&ejh_fc&;GRUh`?_U|@CsjkMg4{~A=(r$PtDbgzkk_fca$=A_RPB69ko&40 zd|HqXRlRaekZ)7nx;Dtas%D=Z8Rej4op2N-W=c+wk5At5BGu{mHBGv2P z4)Q&!-`nTJxb}ak4*MX;`Km{L6y%dtH+>T17gb}Q2f3qa`IkXHK=qujf_$0kJ6{L+ zOV!M8gFHZW=J!EfqI%=@Am69D-9C!O&F?>|BYq8Xq3X)tf_$p#<937PhJRT#?e8FG zs8-rD6W9MB)${D5OI*G}^*#F}8<)RQ?PWJ;E@!FEP7U%>)tl`@Ze0HdRDZG?IhVt& zgSxlfc)L7S^%(p78<$U4eZp?YU4B)yrF|lf%Ux8f>_*V#I@Js8Gjd$MO7#Q#upF1a zR_&7+LS&vRNqlevm14{+^tnJ zRCiJBquNh3M|G&`zN&euC8`yw14HJw&F>)9k*fal5#t5QcKY{+t5ThydXTD}ZvFm; zsxDAHOw~?re*e{~C#jyHYNr#w|HZ18sa~sUhi||C-KzJiKB~G|^+nZJRo_vy!;{~B zi|RJjA64ye;P>~RtJreef7AQ9rE0orSJfV>{&N)@-gNheAFS#>S24b?a-OPPHiweZ z?0K4|XT@)4w?}^cI4P+1{ac}=w)QC*;-P^{md|UfpJugjaZqQ|W$zSk3=MQ|%?=Hm zwq!|YpuL%Vpo0U0$9)Me*ZRF?xcB4Os~deLU^K78ps&!r~P%qMS>XGc{tb4{p@bPG5h^r4VP`h>^$AXPZn|8&;9hb-&Fe@ zW54ca{p@h)R;!)t*A3%--SkTAmwB+x&<^V{$@WQp=o)JvaeSq7>_c753pYOJ662d_ z-L$dJQ01_2=;{f*(2?EGABO{R;aiChO^@>p0V0X5F;0&d`*R z;ZUaQ&=36@Ehmnz<&pLwhsNCaTG%h+JJq^rW1XQDHa<5TKlD4%K;rniC5+F#M#1>p z@q{*R9H-d$_HY|OKlEE?IdOdbZG3JpH-ByHm+@U^-L8%E!TsEk8xDp01l{hh>*s#& zRAsn38^WRS#`s~lM-8~{_|MF6eB6$?>AIhX>^E`#h9oR+d+W#iyAPqvM3 zZ-P~(pju<9Wr#jyccfVcS&u z{mAum+|5s@w=H4P*7~NUyL#1_?e#fhemQsgN*haZTenoNXsO2h(laz}d;7Ng%-*yk zlyijt_W}R!AO7E!C7X6^3vIHwUQp6@YS-E41xr_%zx|WEWfgDL=l`;M+G9JmWtME; zSZsA+#rK)9il17J&EK9>zNmcHzQ(57?*{u_Yrn_X???8#u;QoQ6RlRd?s30t9P4Vq z_7qorHg5Lt}ePfB=y?xWz)u#hVSnA!EB7xSQ?h?qc%*f^HX*px%pYIQ{iS`lWPHiE$97z4eLl(@I=;))_H4&W zx9$o{vddno-(>4f=SN-h$Y`uosUN+nP{b=@R+dB3!j=pWpx5lKT-meWW z88LoD@kqb#nBHBj<%2nA&v`fb&(}hk4{h0T#^8TzT~C%|L&tg z=^tI`UJ_ir%8Mn3yq0T2H|+b|Q|ll4@tyg5)||Cq&V`5cUsqYU{gm0e<;>o=_pIOd z_-A!mW$5^?vfteM(c@kkU;9aiM~2OQs@KDp{=IG2i^u%6<*_>(fB&_2d)u3*^~)TR zRg!H>nG-CNoE>O;R&rb0yPBM}J#OUeex+t?+vU#Ew)gpefAjxVPn|w{Qs~duU$Z?a zZC%<0X;ZDMZQ8}Tu79sTv%p`_#Zj>VnSH>&miq4odv%Z>+3`{ju)GY85Zw(NJc`Ek+uM;~l`$)p$mK4|>7 z114pMb^K2bPqBNXmMM1i^PoE;CHy3XQ;xS2RZ=*1tR1V9lDrKaU5T#jX$Rz=?N3r! z=Q0~UDcL*0E*K)Ow6pGtE>nFJ&FE?==528>7CpL)9r%+y_Xho>fWHahTU$yf|N;KK#HX1#_MjwlwX*@N0hYg<=on&KZ5k1eYds{}kXW9#!(Rb`} zxpnl=9(E#*wzj|N(U)w=HV9y)9*zXsxZeuF)%u?-Ctu=ecgt7531#N7P-y?;5?t`esHCvMKhAzSP}b7?1vL zW9uEg%!cd}UC=rd>Ki?ww|#(aw2zImA=(a0!?9a!EEj}h581-63&*BdzYD{$pKbOo z3dh>pQvDQ;rCItp9CI(A{}PUEu&MtVjcSVkg*o`6d#pwUzO0BzBptjqf6{*0x~ZM`971!Vi(y zZZ_G{5?0kdoc`^6O!uwvVpRLFbyx4~( z+J|0jfNhSCyx2yY!H>Pz!M2t@@nSPg<80k1@3cD)>WH5&WHHu-DO z*!wn1uSa8t+M0MH8hg&*o6*>hwnT45V-H&Mx1+HeY{cZp-t=`bMmq_v1K;%m$!-iY_oJlo7lCs&{wvJ^{{bX)h2eMjq~a@u|<|n zY9H%iTl3`hvD>YA`tGrnZgti!)vbpPHZ`jE4*2nI$)mpGV zc6VkdRJcCY##Ttt`j|cG3XNSKtFkpw`B>~#>$m@7u`yPrZjCkA6zaFeCfn>zvt&+8 z-x|xZWtg!ww%TT?VQZ|=mSN`BSk&fv*4ETT)^B0ka42`Pq7 z(>8~VuEV`JwbXU2vDJ8(>nOCb9Ald_^%EO-mFw8U#&fLeSZcfQajs)VFZ=vW*YU1x zgX3MtDqH<0xQ-8PUQTo!XW3div(7qxu_Zpsb&RsPJ==ABV@r09>)2w;eXi^H($@R( z>DJNRW^9G)uwCDNti!#GXg3t0)Q4=j+&LljAKL=%jasR1+a!`*#|O3=J=ZbQb`twE z*idS&I}W>!&PHOc<2svGs_VGNHbk21=x<|g;W{3)VOqM5&ujthBQQg$hnRk?UB{QU zzT3Etr)=PK*U{g$M_bo1(l&29*RjUdm^)FY#*B1u9cyioJGzdaY+7!vQ~TQ{u*X)` z%2r*H>v+@Fs(X7`>O|X%l3jbftQ{QHrQj6p>EVNAacJtf^;8kSR5Mi`YU#|I4tB1Q0!uHc*q;5*xBNUke8*HVR58=->hOM zi#ax1Im#Vfw)q;Q+`(m=vBApiUA8$JqTJ49o3)|JZC$o`8>XD@vd!FZKCf z?Xu0@Naa>8+x+dV+|u$Oo47;=Czh8(DjAqOdA$id1OQm2d| zQumC6`$v@(Vqql_V|lriL3Wehn^8ADbpW61H!7;=I# zhMcI3Atxzg$jQnWa*8sBoT`i=rzvB|>B<W9 zAzPgxXGWbl&X99G_a!U7A?K;73^`v>hFqX1L)IzEkP8)M$VG}WWWAycxmZz#T%ssL zE>*;k4ayjDnKFi4u8bj9C}YT#${2E$GKO5Oj3L)3W5~727;>F5hFq_VAvY*v$c@Sv za+5NK+^mctw#40%{lhCHGuLpCbPkVh3|$R8M z&KzgRho1X#Cf|^c)KrFitSCc1QIsK{D$0=06lKWgiZbL2MH%v?q72!hC_}zd#E`AZ z81l6;hHO*DkZ+VR$DPzdb${6yCGKT!Bj3GOe zG2}O84EbFdL;g_4kUy0%IZT~hs>?X+jz&9j)H`i@X&73;! zo8pqgp8M*qcJ6M*3#+xhDK3SqZ;FeO^-Xaxvc4%Um8@@yOC#%>;#!dPO>r&B`lh&6 zWPMXyYck&y*9O2h#iaxIrnt5MzA3I9fNzRx58#{PIso{lxQ+n6DXtTMZ;HzR@J(@@ z0en+j7XaTB*A>7w#q9#%o8r0w_@=n-0KO@%2Y_#i+ZDh!#bpBcrnsH}zA3I3fNzTH z4d9#N`T$Ij_Q_sSI5NfrNnh%2aU$WsqW7IeeZx_wm$PV(u;;$|&9`Vz+RLK7$g-$E zSr!c-%c6l~S(HVVMcHIoltY$9gUGUIFd2)60I+B%0E>nJuxK~{i$(yjXe0oO_6A_l zJ^(Bl1;C=w04&-UfJOTOuxJbbi*f;2ln20~d;k^|0I;YKfJH?BEE)^IqHzE$Dh31= z?H-PtV1lHNa1WLG$)eNksfsr~9Cdyrgank04%BlV9`_n7S#i=Xc_>E zrUS5O1^|m109Z5=fJL(aSTq}eMRNdHbO->84h3M*TmTl$17Oj7Kwwd6IP#ncl76N= zo%70MQK21!yanN?^UGPZB<#7bp7bqhq`fR!N|r^3k!8{0WLdO~EQ^+tWzh<f`7Oe$f(U|}&ItzeBX9EI@7KJ12>|~aHkGpVQEQ{K@ za85Yt{Bjmu5cb?xm--g1qrEJ;kSvQXBFm!nWLb1ESr%PFmPMD6Wzhz*EV_&=i!LW) z(G>tJx)OjzR{^l-Y5*2p1Hhtd0a$b$0E?~%V9^Z#EV>bZMK=Mk=w<*G-2%X(TLD;f z8vu)L2Vl`104%x_fJJu!u;^|87Tp8DqI&^>MdyVhlT48G>)dtG`LgIj|6VK{b$&UE z9twNQ?S&QJqK9cOiyk4%qK#x(^e9;tZ6eE}$H=niak4DhOqNAYkY&-6WGs3LfJILO zu;>{87Cj5VqUQiu^gIBIUI1XxivTQo34lc}1F+~702aLpz@paxSoAsoi{1cW(VGA) zdJBL>Zv(LC9RL=+3&5iH09f=sAh76xaO4sbBz>L}=RsL?w7o3meGra1znn#%guO@X z^(^0_PiZfUJ|oMb&&jgr3$iTwk}Qk1kY&+VWLdP8EQ`J-%c5;$Ecyn3Mc)Fj=sN%w zeGkB*9{^ai9e_nY0O02ciWz@lFOSoA9Zi*^98=r;fs{SLsQKLA+tCjg870$|bK z04(|kfJLFC_+5TG|MjRa0E?0UfkhvMBcGWd>7STN-p8`&GWYsaBq{3rau!9CJonYx zzC|(G%c4}WEJ`EGq84OX)RHWVT9IW@YqBhALzYG9WLeafj79ALSkxYXMI8WG)DeJ1 zod8&r0l=cp04(YPz@n}IEZPNtMcn{c)E$6DJpfp=D*%f!0a(-%fJMCkSkxPUMSTER z)EB_9Xg2^B?G6Ym@{%HZnjqfJjR9a$E&z-209cd{z@h>G78L@ps0e^XV*yw+4uD0)04y30z@icW z7L@`5i}p;4EHpvV-?aCdczemBOWi9MWl2%zm$PX9B=5{UWl(EtsPoHNbXb!2ru`#~e=Itj_OfUhSr#oP%c2!zS#$(h79B~J zMMsfk(Mqx`I+`qtjv-^wDgYK83&5h|09dpdfJMgxu;>H;7M%#dqLTnvbTR;oP61%i zsQ@fG4S+?b1F&cf0E^B5V9{Ct7M%&eqO$;4bT$Bs&H-T2xd1FW4-iBB%c2crS#%j$7F|x3MOTnz z(UoLbbQKwkt_EPyH2^HS7Jx<90kG(L02bWtfMfU-)=zaheJpc$ST9*{bGeOeZ**i153uRFc zdn1qcU{cii67HuNSqQ}Ux=y9?v+Dw*3PmpENlVn-+6j>HMO_oK^ zkg@1l02Vz5z@p~?So8t_i(Uj^(MtdjulBFK91|z9h?{Eo52r6?EczXQMSlRW=uZF^{RP0HzX4eE z4*-io5#6?9Q5b+lNdPR00I(<-fJGi4u;|mI$O|S&`oZ=JhxeH*de?=NNYwe|EJ}-b z-wl;TEod)`T9Rc^E3zzVO_oJ%$g(J%EQ{KbWl=k_ENV}dMIFdk)DeJ1od8&r0l=cp z04(YPz@n}IEZPNtMcn{c)E$6DJpfp=D*%f!0a(-%fJMCkSkxPUMSTER)E9t7y8*Ch zcK{ak17Oh}04&-Q5Lgt8L^=#Ji#ocS`_xEqr{B{4S;5;Y5_Nt#i?Sl#&=ImIoA$CO zhb)T*k!8_fvMd@xmPJF!vS=7t77ZuMq7h_SG?I)(djqg&9{?7O0$|Z-02b{Fz@q&C zSTqKJMY#Yh$^&3gJ^+gf09aHAz@j1m7L5g9(KrAW6$7wnJOGPI09aHCz@jn$7L^0A zr~(jJG$0b0VuGX(cZZ*WvS>iWLS-cC{Bjo6M7$&RmPNI+mqioEvS=b%7EL0{qRC`g zG=(gS4j{{-1Ie=JAhIkvn2ber04$mcz@mBp7EJ?S(R2V7%>ZCg0|1L=0pY$55S@Y04!Pvz@kL}ELse}q9p(!wMb%4O4!y}O|Opx?%+}ov>$)a*+ z(S?zy^UGOuNyLlpCyOqny)4>5mPMD5WzpqiS#$+i7F|h}MOTq!(bZ&GbPZV+T}#HI z>i}4EJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2vibUOfx?f_uXod7Jl3xGv;1F+~G z02bW~z@qyASad%Ciyi=A(SraidI*3;4+8>=)<+`!O_20k+^ew{W0AcI>pc>QI=`Gn zk43z)Tv_xu?PbwsvMhRnEQ_8b%c7^qvgm2DEP944i=HLRqUXr6=y@_0y#T4#1*609f=V0E_+tVA0el7 z9sr9{09X_SU{MSZSoB3Ca<2)JewllJ(U-EQ(Y*qanjCe0Ig45)dv6!YqSmyRMQzBk zD4i^e+LC2aJF+ZlPnJa;$g-#-Sr&C7%c2Z27Ig+-Q5OIfbp>G2E&wd*2Ed~304(YO zz@l9NSdIJ}}-T*A>1Hhub04&-KfJM6lu&5sZi}nCu(VhS-+6#b1{Q+1s z01#NzB02K636g$^{b#a$_D*o8f0X;b)Pc!S=a;i+P_nn{I9W89_OfUQSr!c?%c5aq zSu~t1i$;)T(MYl^+M6tk_94rnQDiI{4Zxy(0a&yj0E@-|uqYRRMR@=$$_HRk0RW2% z0a#Q7z@o7LEE)&EqGA9RjR#;+2>^>q0a#Q9z@l;h7F7VSs1krh`vb733J_S7og67J zLDFA$@4L>CML*g*WxeX;sPoHNG%?w07%z(^(Owo!Cd;BJWLb0oSr#2gmPH4VWzoT8 zSyV@sMN`SLsGf{P(*RgB9e_nM09e!jz@nJ|ESd$tqS*i}nghV1LjYKGC;*G*0^>40a&yYfJKJ^u;_3=U{P&yN8%kx-QM8vuE6K9xXtFFihAfL#k!8`bWLb0^Sr)A(%cA4Svgiad z7M%#dqLTnvbTR;oP61%isQ@fG4S+?b1F&cf0E^B5V9{Ct7M%&eqO$;4bT$Bs&H-T2 zxd1FW4}eAI1F+}<02ZwSV9|vDEV>AQMe6~9MJtjcFPR|ezghH-kVX5sN01jMN1b2J zqRW!KAIfFX<+PVYSCD1Vm1J3T6!v#1i+$)0a)}10E;#Pu;@`hV9}+?kxmt6QFGwa{v~70SGL5JUMcp36lPzyA;|iiwav>_%b=_{Bjn3o$MV|EsM6%UKV{r zmPOx^WzlzJS@bPHV9_4{ zEcz3GMSlUX=x+cP{R6i$7VQGSqHX{z>JGr79sn%b6@W#V04(YWz@lCNEb0xw zqCNmD>I=Z4-2hm$I{=IN0kCKf02b{Dz@ohXSkxbYMFRj>G!TGASpY1`1_Tzh_99zM zko58HjcIMX;7@M-0)R!804&-cfJIdREUE@zQ4Ii#Y5{>ogT2T=6D0is_rB{PvS^8W zcr?L_I=`GnQ#`L?iYz*S_Oj?evMf4?EQ<~%%c456ESgG|MfGG^G>t5arjupS3^Eoq z0I+B#0E=b;uxK^_i{=2Z=nw!F9SXprxd1Gh2f(8F04!Pnz@mi!ELsG>qQw9#S^~hL zMgSHq1z^!(04zEjfJMsyShO5~MJoV-MU%WpqY09p?cR4iSr$#U5AyVm@S@HyXVKA~ zckY3*=os3|qE%#BbSzmG9Y>Z$tI4wHc(N=yfh>zoB+H_c$g=2UG8UZzz@k$DSaccy zi%th%(Ha02odLk2wE!$S6M#i$0kG(702ZACz@l>jSaco$i_QmN(FFi3S_iPVMYjX6=neoD z-3h>=y8u{pHvo(70btR+04%x>fJOHMu;>8*7Ci{SqK5!j^e_O69syv{MgSH)3c#XG z04#b8fJKi30*fy9BB467Xu1>U3R%>}y#lh?i#orYMNfNP&w5$(4DDsnvt(KH99b4U zPnJb5kY&+}WLfkQSr)xamPN0SWznl-EP4%qMXv*}=nViCy$Qggw*Xl5HUNv>0btR) z04#bBfJN^Eu;>E-7JUf7qK^Pr^f3U7J^^6SrvNPa41h(S1F+}|02X}-z@jYxEcyx% zSoEY9DKbIQZ*UJ9pOQu4u!XH&)cNHs`quMiO_xRA(OwpPPnJbLkY&+!vMlMD*zU?1_Tyu^CG92An94o zqHko;)9&iJO-j`HEZQA_Mg0I+v*OWLcC;mPL7FEXoI9 zQ2_vp3ISMD1i+%P04y2@z@lOR7L5mBQ3(KxN@2Ed|n02WmMu&5G%Mf(G=s0x5Z z)c`E20bo%r0E;F7uxKIxizWdAi-x5{I?pzXUT`O|;j(C}djvT-CF=Zg79Eu0jXXpa z9ZY*!R7aLYQ^~TZo-B)|k!8_zvMicGmPHL@Su~R@i)N9rXf^Gk102VC;V9{X!EIJ&3MauwKv>bp%D*#w@ z1OSVU1YprofWV>yQX&VNAnBXk>u3kcqEh#kwUsGR=a;kS*c9*Rxw7au+RLKVWLb1P zSr(l@mPIF$Wzk7wS#&a47M((tMW>Qw(P?BXIvs#TYXDeu1^|oJ0z02ZAEz@oDO zSac2mi_QgL(RlzYIv;>V7XYwm9RQ0i1Yprc04!P$z@m!*Sab;hi!KFV(FOn(T?W9S z%K?E!$D~BAG(pl|bno6@C5!Bv9qooKCF=Zg7G0C#ZJsZSuBE*!x{fT1t|!Z)8_2Tg zMzSori7bn5Cd;B*$g=2GvMjodj77Htu;>l|7TpQJqPqZCbTC zB3n(6^piak=W1E>kNZ}Ir&6NMFK5wnDPD_3vgmo*%c2*^vgk#!EP9D7i(V$nqF2bW z=vA^TdW|fLUMI_a02X}?z@jezSo9?Ti?#r;=qmsgZ3SS_*8nWq1_&&ACMA+>f~2o? zucJLHi&jT0e3KG&emRSNNb&YxB8#@uUKagGmPJ32Wzo-MS@a887X3<=MLWo{=r^(~ z`kgF`{vcz~p8zcS3xGv`1F+~H02YO!x^2gzFaV2^09X_OV3EBg;v!pp$zd$=09cd) zz@jJsi(&vQN(Eq18UTx00I;Yf0E=1yu&6Zvi`oFNC>?-BZ2^Hr-=#zjGeOeJ?4zx{ z?`6>v_b-m^qEY9Uv#3+lJAbJx%Amb0>P(hJUC6SiD_IupLY76{$g-$ASr+vm%c5P$ zvM7^`MLhvn)C+(`y#ZL%2Y^L=0a&yf0E>19U{OB+7VQDRqCEjvv=;!2`U9|N004^y z0gD&h^S*UxYJK{Z=W3= zjXJ-aMf*g(_Yapvqi8RSMw4aHzGPXnA6XWSAxA*9Dqd?04%BmVA1{nEUE%vQ8fUIY5-VN3&5fY z04$maz@kY2ESe0!qA36@Isgz@G%^}VT4olxFPZoDmPPBFMF&Qs&M#-t)Tq~cg)FM4 zy)2qWmPOOavS?9$ z79AIjtT92-N4iHut7TDd_w4%WXw>=TEV@4G-Lg^^-9UR;bR$_7-9(l}H7PMfU=*=so}z-4DQ`2LM>~AOMRV0$|a@ z04#b0fJGYtSoA0Wi#7qU=rI5mJr2O4%>XQV0)RzN0Q02VzBz@ldWfkoFwBd?ht z=^wQ=ajug^AGqg5&qkxpFK5wilvR{S@`~IZhV+OnX`M3t1NZN|r@C$g=1+vMlC=}BzHx`8fSd;|7q6h$sk^xxc0k9|qfJIRN7R3NqlnTJ2GyoR00ANu| z02Z|ZU{PxT7PSFjQ91yN+5)hs9RQ2k1F)zAAh2kAG&0o$N$=j-#Q9Mcz3(jQ7>hc; zoJCz?-m2qeQCHf_qFuO16b_ZZlKL8f(0l=a?0a&yb0E_wquxJ1Piv|L)C<}l^*#Ioc0btP}02U1fV9^i& z77Ybp(J%lO4F_P+2mlt11Oygk#3EOlAn85&m^htd!JYmf_n$<2$D+gY^2o9%pDc?C$g-%AEQ^ZBvS=(>7L6lgQ856E#sjdZ1b{`Q04yp4 zU{N^$iz)zER0+VM{Q+211;Cz%Q)JN$+RLH_vMicOmPND3 zvS>D07R@2cqC?2C=uomOnoE{N^T=2~97F`PnEIJ_;S!RNySGX5o zPn1QkyNjgjVo~Rpv*@Onw{DFrx|#N}=oYdpx|J-8ZX?U0+sU%%4zet|lPrtwBFmz? z$+GAkG8Wwnz@qyASad%Ciyi=A(SraidI*3;4+F615dao#1Ypsl04&-Bz@oqWznm&mqo9UWzp+oS@Z^37QIQ9MQ@R1(c5HM^bT1Ty-Suw?~$?S zeE=4H0KlRT0a)}A0E<2bV9_T4Ecz6HMV|q%=yL!TeF4CtF9BGz1%O3g0kCK*0E@l` zV9_=J7JUQ2qHh6M^c?_;z6W5@4*)FM4hSrIDHcgS(=0l}z3=*ES@e~A%i52zsPoHN z^lQxPd$ugvL3>&B8(9|pPL@S~kY&-IWLfkVSr+|GmPP-NWl<JPx80RSu-2*9E&02XBfuqX$BMS}oXG#G$ILjYJb6o5s;09Z5}fJGw!STquVMSBCV zXdeI;jRFJ~bxn<|H9^ulxsTi5B{jIypV8LB=+vn5%UP70>fLs}EXt$3EXpU#q5`rk zDkRIIBC;$ROO{3B$g-%IEQ`jIWl;$ki%J1lR0hDJasU=p0I;YMfJOTQu&4@vMb!W- zssUh8EdYxq0I+Bx0E;F8uxK&>i>3gu=l}o~9SFdpg8*1`FaV3{09Z5?fJOCyz@q(9 zBX5`>>2JA{*ce$f#rk>EQlriMdt&s=mG#1tpi}ug#awN2!KWF0a$b~0E;dGV9})jEZP9TqRRkSbU6Tv zt^i=sl>jWd3V=md1F+~C02W;fz@qB_SadxAi*5h}7M+|LnP!5d7rK8QIz<+>cCYE* zm>P9{Ig4&h^^Utl7TrdBS#&#D7TrOXMR$^A(OqO&bT?TR-9wf|_mXANePmg5KN*W2 z0ASIB04#b4fJF}ju;>v07HtGz(W3w?+62I&#{gLLH~@<_1F+}`02Vz7z@n!BSoAai zi=F{s(X#+7dJcd^&jYaN1ppSk2*9G30D(m}r$(+dLDDc_7JUi8qAdU{`U-$WTLD<~H2{mY0kG&B02X}GW zgZ8rMPqHlfi!6)&Cd;CK$g(JuraO086ei1}B(f}ukY!Oa8H+ps7Nr2NC z0a%mF2u#jlapFuI^)Kc1epmznn$8rg^nj$)Zf!%c7oSS=5Ux zi+Yn~Q6I7_>PwbIyOCwl?qpfik1UJ!AY;*<04&-IfJOZQSTq2DMFRm?lm)<|YycMJ z0I+Bf0E-3#uxJPXi-rQQXcz#Ch6Au@1OSUh0za_ zsC!yug$a`0*NM|3Ex6Nv$%Qd#QRkPls36U|=o(p6NPAgSM3zNk$+Bo1Sr!$OWzl%D zEGi+(qEfOfDkICHaxxZG0I;YMfJOTQu&4@vMb!W-ssUh8EdYxq0I+Bx0E;F8uxK&> zi>3gu=l}o~9SFdpg8*1`FaV3{09Z5?fJOBHESd(uqUiuEngIwb%1euEG(pn)y4$jR zSya)|LPJ{A`Qb87A+vlqJ?Bxw1_N=7L#Ss z5;7Jw0bKBLG-*Bmj$!0$|Zf02Un$z@lRSShNa& zMaKfL=r{lttp;Gx@c=A30f0p(0L02ZAL2rQbF7D>6@EIPrx0y0|`<-7j@IVCOX z{BjnpN%MBUQ5Ky+ds(!WEQ`)0%c8T$vgmBGEINlQi_Rs>qVveI=zOv)x`2#D>i}4E zApnam0$|a402W;gz@ke4Sac}>i#7nT=rRBnT@JvaD*#w@B>;=A0$|bA04%x&fJN5= zu;@Af7F`d(q8k8MbRz(ZZUSJ@&49q7)6ycPCP;ce_rB}XWl>*uk#tL1)cNHsx+Be- zce5%c2L#vgjc)7Cj8WqDKH&^#2j} z9^g^bQQYoKHj`aQ+W<-EgrcAVN$4ObO9}+iNReWR0YXuFQ9x9z*n2@mLB-yCR}_2i zyq7TVt(MMz~`WS#kp8&AvQveoy2Ed}N04(|(fJI*bu;@zw7JUW4 zqOSp1^bG)uz6D^>cK|Hf2Ed~40a)|{0E@N*u;@ns7X1XkqMrd+^a}usb^rp4UT+Y5r>zto~0sovgqm_nLuxJDT zi}nOy(MSLmjRIiNUH~lG8-PWl0az3RV9^*rU{PLbXod(9Jv>ju>7E+&^gq%sGb&0A zt6yr-*i`ShyUe0-Om7yIk%_o~h3&>{CLb6%3h-?-uCYwb|$Y#+}vRSl@Y!)3t#-c+3ShO5~MJoVUv=V?t zhXJr?6#$D42Vl_=04zEZfJLhTSacKsi;f0h(J=rlIu?LM#{sbDcmNiy0btPy04zEY zfJG+(u;^p}7M%hJEIKGPv`qww-miaQeXv>dvb^S?mMK=Jj=tck*-2}j* zn*msK3m~xQ^wiK05hS`vZ>Y~Oi>B&*(XFXr^-C?fGu4~)pjmVm)0;(ilg*-g$Y#;K zWV7f#vRQOL*(`d1Y!*F8Hj5r2n?;+*SoAOeiyi@B(PjV^Jqp00#{gLLH~@>D0ASIR z04#b6fJILOu;>{87Cj5VqUQiu^gIBIUI1XxivTQo34lc}1F+~702aLpz@paxSoAs| zu;}*G&?*rmx>f%i_71b?7CkY&ks4ON)S`D%y^A-QMej1bS@a&+EP9`87JWcAi?)!> zq7TVt(MM#n=wq^3^aFFD*%f=2Vl_`04(|vfJI*cu;^<57JUQ2qHh6M z^c?_;wgIr{djJ;w0KlT{04(|ufJHw6u;^z17X1Riq8$J%`W1jhzX7o5cR*m#TdAQ( zM3Cqi`ndXSv#7YMgg;Wl>X%yNqvo zQTMd4`lS}_lIHF9m|3(d)0;)T$!1X>vRSkn*(}Z7HjDa_&7yu}v#3AWEXpTi zQ2_vp3ISL&0DwgU0a!E$fJK7=STqEHMMD8tGz@@6!vR<{0)Rz(0iUF`_3;>IY09aHEz@idBU{TMsP^AbGouVHp>XjDs^!w{uv!!Wa^-C=p zpXM!i!YrD=^kz{x*(|Ccn?;pmv#5$}7FCnYqKRa)sD^A7)soGkIx-g31F&cx02WOG zV9{g%7EJ+Q(Nq8y?F+!7{Qy|BKLCpk0ANuA0E-R;U{NCgi>3jvXgUCkW&p6L34ld2 z0a!E(fJL(bSTqNKMF#-_i^ipe&JjVP`|2a2GPCF^{oB}s)57YPTC^a|yW=UdXd%;^ zMT^L0(PFY$w1jLHEhU>p%gAQYA!M`YP_kLHoNN}YAY;)=02Unvz@k+EEIJ&3MMnUz z=tuw-tp;GxQ2;DD8h}N|0I=v-02Unwz@p;;ShNO!MJE8T=tKY(odm$5lL1(C3IK~v z1z^!>04zEk5Lh%XE%des5RYv*;qSS+tI97F|p>i!LE!(Ru(DZ2(}=r2s6t41h(K1F&c#0E?~w zV9}KTEV>GSMOOo`=o$bPT?@dX>i}4EJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2vi zbUPrh=&ZC*-m_xSeEr<@*=EsVeQWlPw6OZ67TuHP#hy2d?qzzj=svPpbU)cFdVp*e zJxDf-9wM7Xo5*I-!(_AQ5wcmdnT$n`0Y02VzCz@jGrSo9i@pG0(U$-$`U-$WUjwk{8vqu43&5i909dpQfJNT}u;>Q> z7HtP$(T@Nu`U!wVKLfDn7XTLR0ASIt04(|qfJMIpu;>o}7X1mpqQ3xvMenACt`|X~ zf9i)p-ZP6PwUzL9T3G#3i$dw%bMid9&6onmOHOau)Az_`Q3}~C3X{#E2-z%ZMK+6C zlg*-3vRRZyHjC29Sd;<4qD%l5MFCip1;C;<04!9)Lw1 z09e!!fJL1ESkxJSMO^?`)D?h5-2hmW2f(8404(YOz@najz#=z2^n(Zz-CsXyos=H* z(K_k>gx)JXtbVCQebT+QubD-=F}8`Yw+^sxG+ z7FDEsQ{FI(Dw*Casv?_3)nv11BH1jeA)7_DWV5J_Y!=m%&7ytCX3-=v7EK0V(G&m{ zO$A`lz5p!R4}eAc1F+}-02Va>u;@Sl7BvE}Xc_>ErUS5O1^|ni09Z5=fJL(aSTq}e zMRNdHbPxcG4hCS+TmTl$0|XXLNDmz$f<$lYEaH@#MbGI?(){$W`lS{vPWRToWfm=A zdb4OL*(_Q{Hj54+n?;9`&7$RGvuFj`ELur6iw+~3MXShIbT|NujsRfMkpL`O4ZxzK z09bT10E>1F+~602ZAJz@pOtSado7 zi_QRG(U|}&Itvh3v@kvNs0b2`>FH;YS=1#%!rAFz^-C=}Ki&KE9kXaH)0;&Xkj?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4fJJuzu;@+z z7TpC1EIKzm)cReq=qEiFoo5!krWW0u9#+59qWjamJ>EBq9$Icw*gr64gibZ1q2q| zn;xnbL85DOMV$N0qI>o2koVHV>X%ydVY;_yi&^v$)0;&flg*+}$Y#-}WV7fqvRSm1 zY!-b^HjBO>n?+xe&7!Z!SoAdji@pJ1(YF9B`VN3a+W=VfJphY-0ASH}02ciSz@nc3 zSoAXhi+%xM(GCC>{R+UM-vC(jI{=IR0ASId04(|ofJJ`;u*k`&fWV>;(nIHo zAkoA1J{w&7ug|ENVqIi&~S-qExb3ltwm-(#d8~ z2H7miB%4K1G8Sb4u&50Hi`oLPs2u={vH@6>1HhtO02Z|eU{MDE7Ig$*Q6~Tvbp~Kj z7XTJ@1z=G(02bu|u&6r#i+TXCs3!o6dI7L#7XTLR3J5Gp&Ir9Lfx`ZB#))Q@Zy^(UJ}`DC-GfNT~OlFgz4WV2`>*(@4FHj4(6 zv1kYYi-rQQXcz#Ch6Au@1OSWn1Yprf02Yk`V9{OxEZQ4@MWX>&6a!$<7yuR(0kEhT zfJG$$EGh+H(O3W$jRRm&832pM1F&cUAh2k+j8KnH#iI54*4gf6(cb!YNO?wB{Zfmn zGrXd$X3<2ZH;Zb>W>GEKEUF`$MfGH}Xdkj!G>L2$O(vT~Q^;n~R5BLr3&5iN09dp? z0E-R)U{M1Aiw*=}Q6m70rU9^MIsl7i0I;YDfJHL_STqZOMY91|GzWl12LZ6?U;q}) z1z^!U02a*$V9^2q7A*t>7FA}1W{V)vzxCsdRc29leFtPwMp*q)i^7799(~ zqT>KqbUXly)&Q{R1OOJD2*9F~09bS~0E=nMcBoe99AvjA9h zHUNvx0btR&fWV?98KE0RkZ1?Jh%GgX`m0jsWrWo)wdleO?}e|-qKlZ`ELul4i!LUc zMVFAxqV;66Xam_Sx|D1dT}C#GE+?Bs8_8I71pte#1Yprs04%y1fJN5;u;^L<7F`Fx zqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v*02bW_z@pm$Sab&fi|zzq(Om#6x*LE+_W-cy zUO-^c+KkYTB1rUS{oM5hW>ImHg!?kW>X%ydP==TNty#2*>CK{t$!5_bWV2{9*(`dL zY!*F6Hj5r7n?+BM&7vpCX3PAV9|B}7X1joqMra*^fLg9egR<74gePY z3c#Y@09f=p0E_+rV9}odEcy$8MSlaZ$jP*BI~KVBEJ^}kQ3!xV$$-G3k1|55MUd#Z z`nl_m&7#Trku@(ftbVCQtunn!e=v($Grd`qN;Zqq$YxPG*(}N+n?;#qvnWb7i?YaO zQ5&*Z)Rv4z?EqMm4Zxxt02bu}u&6x%i#hF#8EE+&Iiw2U-qCsS{XfW9<8bUUUhLX*qVPq^C z4#1)j04&-QfJGw#STqWNMSB6TXm0=(jRs&*41h&r09aH6z@lOR7L@?7s1$%jV*yw+ z4uC~v04y30z@iBNEGh?JQ3U{tDgl8-eKSL8KZ!+QwWyz26!SZ5nPK%yEvn7*`u$=S z)iJ$UR8KaG_92@^lgMV#WU^T_g=`j0C7VV2lFg$1$Y#<0WGp%WfJF@eEIJT?MU4O~ zng+n4=>RO60l=ar02a*zV9_i97R?4=(HsC49R$Flg8^7H7l1|c09Z61fJF-cShNs; zMT-Dfv>1RzO8|jI6Ej0KB1m+aelV@ZEP6~WTACSFztp1Tnck9L&7u`dZx*d2n?;9_ z&7xIgv*>WLS#$*1EIN{G7Of_mMMsg%qNB-JbPNECjs;-RaR4kj9)Lw_09bSa0E7M%ycqVoY* zv=$IpbVz1stq2mGpck=2&7uSK@6j&E469#i(Z!kGJ-?epmoU9qw4Q7hZ6KRPmy*q* z%gAQYXRA1%O4j0d02bX2z@j?qG!lv(X(VMdJcd^&jYaN1ppSk2*9G309f=g0E=D$V9~1pEP4%qMXv*} z=nViCy$Qggw*Xl5HUNv>0btR)04#bBfJN^Eu;>E-7Ht7w(T4ym`UntMv?(*x>o2kB zR(&7sVY8@EKN<3IW?21Fi?(KZC63NOK6m{&)0;(Kkj=tlq+{RF_Gp8;6(3jm9D0I=v+02ciQz@py)So8+~ zi~a;)(O&>8`Wt{n^1n%4Bs(eD#UdAgMM(fG3IVVv8GuC|0EHHjCPk z&7y3wS(HP@qFewLwFh8P2LKjz1Yl7o02XxyU{MzU7Ig(+Q8xe<D7uxJ+m7VQeaqTT>3>I1-{-2hm$I{=IJ0ANvHKwwepXy|4UBsxiNg;JwIPk*Vt zHQO&5R=?Du!l?IBvRO2M>CK{nWV2`x*(@4NHj9Rk&7z@XvuGIEEE-NWi$;*mqCLr2 zG!lSCqX1a67XXX)24K->02ajnSTqKJMMVHCDh6Ot2>^>q0a!E^fJNf~SX2hUqVWJM zngGC}asU=p0I;YMfJIdREUE@z(L_LCQGPV^vj`Ghr0=5@m_?QPZfs37tbVCQ`$WCm zuvs*T>CK|aWV2`r*({n$HjDNpn??JP&7%FuX3+s;v#5b=79B{&qDBA~O#@)jbO093 z0ANuQ0E=b*g13c#Xe04zEL5Li?f4UH5*qUY-;X6wzO_u5D}G#XaF)S|X%xyA?jV8Y8G9}^k&gzWV7gUvRSl| zY!+QXHjAz#n?+ZV&7!NxX3;fdv*=nf7F`FxqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v* z02bW_z@pm$Sab&fi|zzq(Om#6x*LE+_W-cyUH}%|2f(8H0a)|^0E-?3V9`SWEZPJJ zEV?8bdQt?5R_WXL>&>F^`UfEoN5kruTJ%`d`y$;edYtLaq9@2^(UWAe=qa*U^fcKl zdWLKkJxex=o+Fz@&y&rf7sy!jA^?kC0$|b004#b1fJLtYu;?`a7QGI@qBj6o^dk02aLuz@iTTShNLzMIQpN=pz6YeGI^&PXJi-DIlX%ydWz@@$nnhnRy;<}%*(~~oY!-b>HjBO^n?>8mX3_U# zv*-u1S+t#O7X3)ZqMra*^fLg9egR<74gePY3c#Y@09f=p0E_+rV9}odEcy$8MSlaZ z$jP#9I~KVBEJ^}kQ3!xV$p9?!09cd)z@jh!iy{ClY6ZZe)_}mG&!eF_5hS{+etQ24 zvuJ+0gw(9C`lS|SW_ionm_<>hH;b~!W>FimS=5$n7PTXrMcHJtD2Hqo<&w>!_GGiD z0~w1t0Uu&4_Fi@E}^s2c!_@&H)W9e_nW09e!$fJMCkShNcOi*^NIQEvbi z^#NefZU8LW9e_o90I;Yp0E_wou&6%(i}C@1Md?|g3q_FVRi22Gkrnjx_tB@01zBPB zOD!6d<=xlLEE>%8X3-F`Su~Vv77ZhtMZ?Kv(Fn3xv?tjt8c8;bMv={;y~tR!Hvo%9 z1F$Ftz@jk#EGhzEQ856EN&r|?3c#YV04y2@z@jn$7L5mB(F6b%l>@M-0)R!804%Bk zU{N&yizWiFs0M&VwE!%t0|XWg$O>%{L82wvxgTg2wb#pAeO6fgQj4Z!d2X&*G?nSi zqJ7C`(SBsJXn(RGlB04!Ptz@kF{Sac`= ziaR}mz7m)>1ZHjB>eE@5R>Sp8Cqj>z)Hb});MWO}n`HQ6jWifk4g zO*V^;A)7_VlFg#y$Y#;;WV2`u*(^GNj728`u;?TJ7M%>hqEi4^bSeOgP6J@k=>RM` z1As+m0T02ZAMz@l>iSadD`i_QaJ(fI%@S_{CU3jkPjApnam0$|ZP02W;gz@ke4 zfkmsbLUTos=#H?6bGTXbjfVAEVf9Nbx;)D}wUb%2k?GB%E68Tim1MK%DzaI0HQ6k> zhHMsHOE!zHBb!Cnlg*+V$XIkE0E=z{VA0J0EV>1NMYjU5=r#Zr-44K_I{;X8Cjg7? z0$|bI04%x(fJOHLu;@Mj7TpiPq6Yw2^dJC>9s*#|CIA*a48WpC09dpc5Lk3+R_Im{ zBswxp#JS8YTB#4RAI%D@Uuw~lS>7vM%%Z25-Yj~WY!*F3HjADmn?=u&&7$YYX3+~| zv*<;#S@aUwEP9!YMXvy`=v4p~y#~Od*8y1c1^|oR1Ypry04#bNfJN^Bu;^U?7QF|+ zqW1w<^Z@{iwg9l`LjV?i1i+$?0a)}20E<2aV9{p)EZPddqR#<=MUQ8Nc8DO+KlR<% zC(NQl^{*Pg$O@}pYSA}YUWYuh=v$^Yi@qb9Mcc?`(f4Gt=m)Y{w4H1g{YW;8ej=Mi zKae02ciYz@k3@So9|Vi~a&&(cb_pa@tt89gAE579|0&C17U{P-X7WDyO(QW`N+8uyJdjPPg zF93`B0kEh)0E_YgSX2POqCx-`4FCidMcagq6+xnNwOf|eCg|y3BJy|x+l19GwP65Q~|)EN&psB0kEhVfJGAlSX2YRqFMkJ z)d8@m9)Lyr0I+BhAh2j~o6yrDNc1j!>uiWwbiLnUYZF$#)S~^`cwg;m7VXdUX3+s; zv#5b=79B`7iyFyh(KNDIG@Wb~%^;gaO=PoZCK-!n0kCK`0E^}Tu;?HF799-0qPYMp zng_t5`2Z|h0KlS!04!Prz@o(fELsAX3;TZv*=i|S#%uP zEIOWS7Of$hMJJHWq7%tx(Me>p=wvb$odUq3Qvq0X8UTw<2Vl_|04zEafJJ8ku;^?6 z7M%mYqH_UQbRGbU&Ie%8S^ySZ0KlRP0a$bq0E^ZEu;^j{7F`0sqV)hQ+5o_!O96pJ zN45#=BZ5RXO7vEnMR)2~VqMlItbRG|oFuPjt4sU3PIf=J>vpoMb6|Ew%yDL9pIziQv$NkSah$o?-Nrf2!tAE;jobNb)@IUimlyTQ%reZA}l zH%I?B`(AF2{&(bk+#LP?r2D!#`X2%pxH?bb8g z9Q}IY*=~-0zwBH$N53F+p_`-M@VL~?(XZ%R?&j!stgUi$^h>frjzTM5ykL=#<=ICcG?{{cXPD=`L&y)9f)mij@|+O z=;r7pe21H(=ionFr}fAzIj}Ychg|LeIfC4QscpluQ|0G=dGp#`*So-V+P~35U+Ldl zUdaevblMM<m+P&#_2LmFS+&TsK1S}G9KQA(nZL|rRM-7#oK8Dzv4;gyq-6bZ_HFkcE|a8W9s9%scdn3W zQnEf-xAmqY{fWj;&633&FKeM~y_v-mY((GOR#q_2uHgHE zbOm?M_qS3?)KT|8PBopsqCe=T)7Z3+czcqWr9+IY-7f0D0G-o9hGKgr`AW*p$J z;JJ66c-xUqr`^SAUBSm_+sntF{nbi;qT@ea_l~qu_Tgoh_ukWA#qSrc+r#NpYSZjs zIa`OemAT7C$=k3j-=E_1*&j~v7jyKj-=DbL=`zD6@g>=R{J4E}^sGy6dEgL#^mPy4 zpW!dyj?C?Hw(jcYiDdGdk`zkm`m$Wp^fzUfQ0uOlLiIN#B(FRn2Y~*jB!^NQH_P26 zqit#^qf&~m%jAH1MLHF~agrfAXAcJP8s{%=37oNeVtK5Q$KOw=+%i0e$! z!ty32EN@cc@+PitUfv{Ko_^zmE^p#`9hxh@GAk`KWa4^V+<*OutTI83mRtR`tJ6X= zYW!w6vWBixr-jw7@tg5c@Pd{R){L6F3em!T< zBB%3u9qi-Bff{u=TjV#%DexN@%(Ecgrp_`qd0BpBVfLfrB>p7k3OWCToL6*??(Z4t zjw?Shu4>Z1fBxde{FzG@<}X=1J%4e-lIcwi3l}d~+BAJ>(~SJ-i&rdMx*bUoyLKaZ~={ruj`v z8kgiZ4QN=hblHqK3-XsPSTJ|`?8Z6sm*mfyKE0uF@x1)Pf`)+&0}2KdHWU^p>?g3_ z`~~xy`ZYC9o71nbp#Q*r`f`7Hxy4KQbLLNIK z#}?06HfR2Vq6Lea`o*`!@}-OYO%iO8>ctBVl5M^uzjk5c;)6?<&2Olab(vK?ciEDL zn%Izv!R#hk+5Zpc{{KdTLmHPh>Ar9r(`ZoP%>L8WvW6K=GaHx9UD~j8#lof~{b#GZ zV#16$^Os7H14;aAn7&}%yan?c8W+wHCNkF+l{Cm!nO@{`VRF{T&pEoR0O_5n=N}BA zfv)GZ{jVR-O$p6%`+Huf!}vV;Ny+!xq{sv*6TG&59p!bE8p-oorG(N)dTA0mm3wL9 zy!4cUwq8ex=_z|TNy%=u*H%lWx0@E>e(WzV5AeF^XcN3nWs>r}R-ugkUQSBeelpJq zGT=(>5zHbpm_;v}g&%d%18lTWego1|LOmyYon*p}-M!sqP5X|Yn8`D>( zE9~C4aCfg$H=D41Xr;C^Kc%DBF|>TVKiEMASLFGF?PbtL$n`pQ@>!18v9k`?Huy)) zmj=oP(j|=Y+p6R4D$9=Md0GCp>?WaWzSpn7>()h3zQ3ijQfvisgH6%THiaMi%V+~+ zw44I3uQsTg&MM#28D+^*cCKAh+ICBralY3#rJdKct03Flwv4`s%g|ZsGTi)p9kaU( zX76EhX&xx(xBIT4mBHdwkmlyI8vj;hm;ZCb39^L$d_m`|Be(^9nRL+qWVzj0Ks&F; zfSz90(4j#Sd!*!eT{|-ezjk*$pqZTw z=w9lsL$V@1a8vro>a^>pJ0>``bc_5S?HI3{Y+LcBN3crWZNIa@|Cj#s)BV-U>lSPe zUz(mM*g_$hv+s|Z)z<48G&vX}-`id0(k{=-7M1(Y@_I@t=;8J3D!>}hN!C|R2Y!-Q z{g~&q3mtW2f6on_;Oe0jdg6%w{}0b1*`W*Fk^ct^?mR%28qL$gJoL^HNmJcf!5Jjq z+pXaL@C?#XZ0fW7u3jfKQ4ec96*V8`9PXp+)L;jjoss(JW|8szsFM%yH(uBN-St$_ zJqY>D!|4Tj$nr|M>}CHoIh)E%`pC&oU$jmB?~9N#_q|8TrplEGT5+=e_cLu&H_|h* zYvc@d){(Mbb#M3W;dRqfK})e(o-~qr%k5KXZFNIQO-(~tilFB-V z7b;3>YhzbuwmsWtojvS~RX< zTJwmpn&O7asyZ3Dwxp)6q&WV{_-dJHePwNZb#;}#&`@1Axum?Iw5p~eRu?Q$X4P`^ zG38Z76B>$Rb+LxZ`ie0nHM$;EHNn^ehb1n!vZ|rBeoSpqO_`2XT2)_J?2k5d*f_rq zZ_&(}lG^GjX<;y@K{5{8Lfc+a6RS;VIoqwGc5K6#`qEOFe{I>+lK3S5ShKPU-J1S5 zx+TXHBsR3HvZ0;@54Xk@mbMtBsAfuaU6rhId3i&1Ras?SiLLSg8$TvhZbt?VXjtm6 zL2--8$CS&xNKL7~8%io;5{sRx(%ObtaWI>~{@B{G(u5T+sT;@kZKxhMr9t*}h3w^` zSY26FWw4!w$0sZ-N|>^&W@5t_ajdwkHdq+jGMJ^#%-?MdWst7`og6pPjI1`PI>&sx}crG;{QG}Km=mNv8)xo~)kv5R7r4RtlK%G!#u zI)BbJC9&cu{>qGLA#6=;OlIWoYT3XhHp{H4Eo!K(tCDS6B0AbW47N>+nIs%f@f9|E zV&(pl8>*^HD&w!A@|c>kvE%A0Ws5e{mekehvCN`Ni^?bX%^f%>IC2L2OY|3B0P+te zABn=YuZG!+g|hkLb1N&WDUCIh6csfTjw!Rlyr{*Y=$~4O%VJ|2s_N^i>+2f!sVc9N z<0n1~js`uc=;=pKT?t2LamhYqa`Qc=zBbs(a%?1?kAg!$B$~LU6YQ9YAX+Qp&op)=CmL3Ir zTGv^2W?5;lQGyl>k)>2ETUy+>w6Q_|Y2FC_Sx9%4p6~o?o3*)xMVtZ}Vns#uHL)T) zp~YJ_POf^BVzSzGWfdi|&-{4|i|_NIgq5t8Jyu&&Bv!?W>dN*Bu0TT)E_@uKa;Y9$ z>0hROF$T&gIuL7ds!u#mG@ri;OXB-c2jk5&EyM&l;_L0=C(UdgK^8iuCMFkn6H1pT z`zrB(l1;_Qx4f#>4(Va>1zZEiPWGl{})zr{5f5x1~`3-tx#b;JlUS2XbR&EEN zT=R?N4A6Yh^L>wBpAz+?|{#)05#&r=i4K3OOo+T}U)6xTe)3pu)O2Y;znSxzmMm$U)zoip z)BIUWXOAin6dZH?)Er4Om(8EPbk2hL{g%j+OQ}nQ&5&zBJo~FSG+65fy^O?~mJ|*c zRwNHHs9aFC6!h6a<1|PZ+Sx=zp%+YU2IHQdD+zFo9Y5N zKkFm|TbyN^PYHTl#a(PxS}sF!vZ#~$QN6gwM__mQ9jE5KEC*ka+$xNTNpH%|wz^E| z2n5X?+I$GeEkM9p_FA-0p?45v(rF0pHG=i@Eu2%nV8Oyd$1el^(Uun1@fNqo6*8wW zRg?cQMNzq2801o`CoX^61SemAr|51hEEr(zj-QofgU4snyp{B}uE91{Foj$`{Q=p} z0gzK#!g1v9*XHiqPIu*YQfzq*867#=9Siuly)r7l4|DIO5K6a-j zM|ChaS*e7rk}!eZY|6RHm%tyjxlb7H%nq@+1l>568l1~ZDykFuW<~n6Ao0qf?N01k zj+-P8B#I`;X){=(76%Ek>kUhMdjk{u&Hs}gT4`BnRm<*UvpvPJBLBI5oxBeapMU%= znmgXi0j%rj=z$yQDgPe_m+FI#J;xPN3rPwbH+-)CAg`H zzu@btH?CEcdNS~@)P?`kSM9)&j+_b9+<$A?EmH^MqSKJt>aqswUhDp#I~a@4O-}#J zSnq*s8FG7TLxs{8h_^3c3sl!sjVqH5qU?%FxyZ=_2Nvloq76|^%H;lZs>smLAn#B$ zKmI6`8*EvC-@}M^Gnj#%xe^tFBT8wkSf17Fbouoq(4~$Q*W>ps&E2D7yCN1!&w^Ex ztq^ZDcgTs-`vw>Jn~FAQ+jhEQ$7=PtS^SZU97FM$#yf1WG5!;@_zMXevZkc&UvH)T zGa)@|ZAs86^V=kMFR~7_NxGHNcPlF@^Di&eF}b?L~wu-^$Ky z@tm&3Ep+^roGxk5XJRYZCT)3SvakH@AvZ(8_K==g!uHS$oOVwdYA2P|$tww0OS*7{ z%})ag<;?6XnJu?R@vgCU*!%^^1=t_Z4w{0XALYN4a6riobn_O{r?mc~6usk+#|I5# zV`ag!JMk_)8XHGC2KD95Hy5fq_a}+>sqrT`19*a?T{|`uGt>JE=OF*wr%lwJ6{93} z1LVnQS&^JWRWJwbFl;-oN$m*=`AM(*NIjYr42;+Ok>x7S&!FjnqRiHYRW@ zczVn$tYN8izNDYpP+A_VZJv%->#NmleE`6N@tyie@qJTNTGYH>3ibIkOR|R?!8Ov~ z(ZR!Y9ZY;i?RVl#ti&!+d`8W;kHsbbaRaG)drC>ryQN##@_!4c8oOcd|7 z>m1{oB2m70zt=Xj|Jc}HET{A43t8|CSYOo6oj;O35T(`rl~+U%iHqcz`}cP!f(O3M zm!*H4a|*fpFVu&p%sa8krDf%Ecb51>p!xo!wzkOLs%fzuFc~xDfv4RzEC}w?{W2i9 zT()Qu4Tzt!;~OmDET)}7Mr09z_3^8yzqJw{bowIv+eJ7yCC8tIF<<`;7)}8|-K{nC z!Rbs-zHmEL%RX)SEH$B1BTr$R|C^s3;-g2wXGU~&<%Zy&va)&PtST2h>mt}&HuSTG zwwRD9;++`Vfc2FVDyt?1 z+m~*VKFZhm27M5=_!xO`EpN;DZ<+WnYafUg6K+OYJeKjBS7_HV?IHOT{MV72@a)!F zTo^of)!7EUFV{nwKVxzFDX9ZGP9PxvNk(D1Lg> z1InMTKF182*5Vu#tClwR4!Q~~vO2i`mIrn5?c#ePXBx+@taVMxmju)dFmi}B@b_kkhA#Zqc|3+i!lGWDN%6nMWCH}{wN_|SX)7upCcu^i_ z1y4>2oW#`JS(Nw7?JY2Ep7v$pT`ZQbHw6Bb?%%qzDver47ft6HZ8z=E@)$agKlDBmAP3#VW(0?4@B~#iMPi>QFlVPG6jcwt- z53fl%!8aRN`3!u*PsnNcXB#0$ z{#q{KC*;Uqo+kW+g4V@J$dNw~N%)aJkWEOs8rkxft-&Y%b^o-H_3f81hW@3(o;&5r zo$`J=Wj_8K+#~l|>hzN1^uOL$NxUW%IREnYX5t8iEiPdLWVzb**4grxC|c!@^JZw3 zzoPlk_|fu_Ykhr#R{8swC$-9WZ)=tDJ~w{9>^~iESJ?(S-WaO~TGhRlB)dZWPLhqH z`&g??;@1vZMU?JZWta3Zt}g3%L#&RnI>u_X)q1Pbt;*lm`qM44dZg83t)5}^QmeOF zy~pZ9R^^XW{rNm&^(CusSbfjx$5y|v`kmFEtjZse`t#90$k6rCZ#ma0er-PdZP)mc{OSzTgvh1Dai9%uDrt7lq0-|EFy zFSmM))tju|Vf8+%4_kf0>ho4#v-+;pkF9=b^?R#3tjY<}-%cswpT8Zg>R;Gs?qs!x z)!nQXSRHD0FRLY1%dOU0oocnw>TIhEtR7n>OiX_tj4U4vsz_! zAFKOYoniH0tBb9!u)5mn8mp&SJ=f|wtCw57*6J-*@3#7o)yJ(qXZ2O9?^xBpG1K+` z!s<4wzgYdtswd|u9WTvlTdN(dcDLHcYQEJWR!3PawmQM8{;`?PcZyX#A8MXub-vYQ zR##a)#_CB{&$PPM>UyhJTD`&Q?N;xz`iRx1tiEXV4Xf{4{nYB$R<~RI&8jPZm80#B zSk1JWW3`LbURL{A9b$EFtK+Orv^v%5bgOf%F0*=s)iqYnuzG>j%dB2!^>(WdSbf~; z3s&E>`k~b?t!}sahgDB5Sh~I$R&%Z9S>4U*0IPdiEw)-=bswt@R%csXWOb$0W2~NH z^<1l$SiQ>X%~tQR`iRwMtiEdXJ*%Ht{m$wRtMWgi`Rmu(YCEevtqzsjC|&;|t5f9K zt+~nSVR9R#d5zVJ<(jSe8mkY<1zz(rRzH;6D9ztk-Bs=(G!L{oSMC`!udsTn{L#PW zhpg_9zlGH7bqVTT-GVy7>apE}e5Tc>dj|OptI=J9+{NlXa)Y7sn{IX8?m@oB>PLNp z{GHW4awDSS54JkLFvy2ly?tPiAGZ42;2?+P#zm(aJuIjdR*xSM`S#7g- zkh@u(91C)j)k}(ke4W)#N`m~o)!oMhd8pNea#O19Y*iK1F%yGY zW%Y#GAfIdXdAZ@z@!zr9ZgP;jTb(*J$g`|&kegf`{|2j{9T4R0R{J&vdAQZZ(}R4Z z)w`R5{Fv3hW(7HQc2J8C3hG3wC(RA=`BqZleA8d8wX+gfl>X&B(`4_7NX9szd)kDq=@-bHLKR?J%Sxvey$eC8htqXF!)zdBs z@uZAitJMM52YGL+%Wn+waaJF^Impjg zO};J2Sysp25#&i$&$uhd7h8Q@ZuHg1kF9pTKghdTo%Udm7g)V|Q;_el`t2h@{@v=J z$ATQQy7Gx2ud%x6sUSaRHRahLx3yaSe2}MDJ?q6FuebW<%R&CsYS-6-yoc2pZv=Uf z)ob4h@?BQ9y%Xd=tqyrV$VFCHZ3*&;Rv-B&$S+upd>Z6ztCd@Wysy=Bz6kQAR^R?A z$Xl)EeH-L{R%dPt@)E1p{}AMRto|S!P~AU&TOIaGkV~u{@oSJzw)&`auyp*FthW9u z$hlUl<++8vzQ5J;UvBl?g&b9XZWz zMo>pYgF4pgYWe;jef?CckINSUX@13OntUUW<_=bCq$8-g!RlK1jv&ofSbblY(t)AmNW%*UD zY4R0RR^K!Jx#h2|esBB_%TB*wI!~+2KWe$1)egpcS?*)CpYdUqM_P>;ue7?a)!9~; zSv}h7=~mZSy~gUDRySLHQLC(Pk~|>Onr(Hg)m2t+vHG#qpRMj8-#Vky9bok=tB+g# z)oLI4RvX<8eXS0*I^60QtEE<}tkzo1aHNg0oHkZFSe4r(pZBsVw>f?uVAX$~BGdWL zQ>4a>Pp~St0si>=SeZ?}Y zwEBV7kFCnL0{HEe!_u!&tNK3_=ys9A#jpPJ6v?8upJn&@b&%CzR>xQ^wOV0yqSbw^ zHdxi~#?s}iwz|fu|GY%_S(eYUy20v3tJhh*$?82;AF%qU)hDffWc4$v-&*~_>Tg#6 zvg$t{k#@9B3fkGrY9Fiq^ALG`kmbFt7Fn&dT4U9J9wOr(U^zwiLu)yXZGTAdw}*5a z{rZuO*G_Ymd}EJsr~i@_^OiPFle%6ES>p7U&&2mv*#AGD zg8HM((2pm{n>RBT$khIDi`Pcm1(Y{cd$ZFKtU zS6DR3-(w{#b>`y6c`{P0rlNo2(xr>%Ok1{8X8XVY(@92^T^4`3J!q#%Wi$Fe-Q`~$ zFBC*)=kfG4{pl^g5&8XJjaMM!?7ZB>uawdKs6Tz>x0U>kmS6pOcaH1Gt+ylHH+kY6 z{Oa;*<(D?dptDV0+)vI`{4k{Fm&ExMALKfd#SfjII;Hc}`8CKd)5xGxKG=00N&pNl z+G)Jhp{_HZjh67*JQ+@0?z+QVXSIx{%T>;DSIaQ-mO*F5aM#Jx0sG;#Rgx3u*ZBzf z5=>z_Kj|vR=XbUYGmQ*77s&i{JbrlXbODL;>zgn?>1xO4cZCcyjn3m5ncqa6(0+LB zQpt()8!7YC?W*m|lwa0Y&&N8A`k+6*$%$~+Ucs>btFP&=+#a_WFK?FXj2Ffa<2@xn zhxwT+;|(K7)#d8XWAdBWzT$-SZ7Z+QzSm_~TwW-}|Jf+>8$poDva}}bc4v!>cZR@R z;d&0z`RR7oWpZrDptDeXK1c`bhxv(;Eyk;p_I<`kQW-D)RXB6{FUZf!%PSmOFl1Q4 zfMElM%5XtJVZy&dh78Kf8$NXSFe&nLVCy4G%1eW9Y6@oT%DW%TSIL_z{p1D5dLO5Q zoJDV+(C>?FV_(^E|HSNV-MrD;_B$%0wD^alteeJf-f?Vn^Nz^G%{v~=du2y*cW3wC z-=5w5+VSn?ZQkL;>imDt@&A2!-sR=Ox^I+elCw7N*pm0^j^sjTkKf;}+UBNJZCl;C z>c{pSs(xG@ae61sUN_-U8TX>HM|XT(aM5`AchiMJwrsd?+@m`>pYiuEfBh|W^`kpp zT=elAxk`M$>Zo%joa>K$&iHfvG0*vzF=uygka3?{ecFW8GSB2JnPb7r){4p92hLtu z{>Toe@PrAE$ZL?nEl z>xKHthfY{NetFr7aXR(rAEp(^R*4-lpq4D7z$+3rbyy!ffFwZeM&pE?&D`ef`&*^*r--3fC$s8T`ksXgl z+aB0+_66?d?W1S@=FfNHgqra+@+Wg!8@1K4|3V)(N?RL){qoT2i9ISN^r{TD!p4Hv zZEHLJ7JXdi*{Ae@&$q29nb7H9_ehSvM|%F}9vL=a*!baP!{b}g>&-qHEL;BTO@qe| zE*lcxBZIe!YuUjPooLSJ^o|*Mb`-33PLS`A{n;(PyzScT(RY7VcejwwCk?k5OP=VfA9mVF23^BcF_+r+bx{2J$1sS(%ox2x0|+p zK+Q)NPr7^jQ*W-nvfzPv9VbRcUBBwiH|I>9U+`Yq%#n{@ckFcwUfge&%7O>FynM%+ zZAo4v;*_MF;nZK0_sDfsQ|A_SuQ+w@SceYDkz{9!8nKdIX!NzMkB7FV9IcYgOag^yO8leI4E ziZ;U5%XKw4k0!f&Nnb2&xLhH+=$S6zC&^7YR8IIwZe*#P^OBN0S5Ey&N#U!z%ZaU9 z4;ij#Um@csC40xqg*P-%&bmoe9S-zScwt9L5l_D|GAR;%Q+gN4$)0}hKPfqUNVbgr zx}2IqecQ%l^iX4-{8P}bPKG_bj-@;xSD0|JULunxWa#(PhBxWCIh-PAVmDkW=hh^F zGEw+WA<5y}rJ-K<6*(`bgnyRdaQJwceI$I047Uomlkr=JC(9gC!{5n$WLkJ^p1gq? zeq3%pGs35Jl?z(9Q2vdE3uVl#a76k*ZNfFOo^8YD$T;o71=3r}4*w+MDhwz=UVLFB{li^O`wXzjEhc|YUZ-ET&B5mjv{##zn3$KwSb`NitIrj*U zmAUl{CrL|sh3}W)UBYL{+-8I;WurEQJNA+{%fsV3OP4vkRoeV?I9qO;p9#MvZF@Gn zM%MSa@GUat^O5c{+}DkKB+csQM$VM6`n!?Kr9+qRM%qhj3f#!ovK!8DBaO1f&vYZJ zr735-kwazMo#RHXlg)Lm8+lC9d2ZxN*~#a-k(*^MYu(6JS@{dxNV&Xrp&N0fNf)`1 zA+lCKx{;|;esUxFhW*cOWV0;&7dJ9gCfMOdUXg}PPKwNt1>K(%=_qaaJQTT38u3La zvQlnqz6?dy$~?acMRrK~IuyBCw#zr6h<@Ssx1q=%vNgU7MHYxP+d`3$EaCf5q)e7q zo*XHWZB&sQ87i%=OpY8Od%r3<(pP3yog7J(xlBxs43y>7BuDf+E^Ct`J!A=W$&pN% zpguWLDvs`x9O*85V3JHOf=y12Tp?agNsingGn<+mk?#(5_DzmVmff~ra-^NOb8~V; zKTp!mi<~cOl+qo$IYGA4M_y!xwB^NcC&U2z)~(kTrTU9Jya6e=8i>A4 zG9!P91(#+<-jc>&mKmv(CS9Hxabw z8|fxXI5ao1MvPsa8#zz5;ELQxt=PIUH&P^9{;=H0Oljw;+(@SE@WXQ>W2AvcpJl#_bzp<+_9Z&7yNt6`2lV@` zm+8Q1vKbH2fh%P$t7VtA@??u1r2|LHe2&(E*JVQ-qXVb)kgplnfrn(j9;X8vW#r>^ z;3a9x8Xed!D|)6pGiWtQ2F}uf6Q#9h>p-q-!gF-sb6M|mbzrnCV#RbBI6^kvN*&lP z4bywgR{D0Oe37-&Dn}&H>q4vDWa;{$tX3nWJ;^%ozHCNM2b#nQ`Nmp-rM zhz?vM%W93R&zwZ3?0}i+dESSo|KWJI&i9t zlcfU}%I?)`QmgM|i?!8(IYQd$!1r?OWb43>vMgGDs3Y`U~nGSE$~fhmh*SEnZ{&q(%m^+t&cnPUnZuebdVR^22PI$j@(T_p~1yxlBz zkvP!tcDLAB;vmP{!(u0igB`E0#f}n(I9@-C9V8BQy#5y3OC08S`4)2}4wwJu*J6&u zLTOf^ba-d}l zX|#+X(=21ibjuhr!!m|6S;ml=mN8_OWek~Z8AIk+#*l+7W5~gl14GI}N6G%rx>L?z z-uS?f{pH;5%?+zLYRE$GDAC6^WRXp3hAg&dhAgpYhAg#chAgvah8$wi3^~-I8M54> z8M4Bn8M4wMh8$)YLsnVFki#uw$Ptz?;$5_UYV=ZIIah5UU zc*_{F#xjPSU>QSBw2UDqS;ml)En~QR$wTvN`S;mmdEn~<=%NTNnWemB}GKO4b8AGnNj3L)p#*k|* zW5{)uG30v77;=MU47t%VhTLQsLvFT=A-7n@kXtQd$ZeJ}kh4RN$^OrJ zMs9Vya{@yerVnKGl0Ctmdd8A9!1(-{2dv#U?dFKD20td}PrK`PiZv@`*(=C zYAteP9V(q7?|t8pHb?5PJVjG=oVLkcvMU`C>2YaqMxOCqBsAIWCRuKKQ^;K<%WZj> z+(ok7mPg2)CChDjD{?2va$DY-+)=XJmZy?CNS533G;({%a$BBG&Xp{;C#KpO?p$hLqi1=7lPfT#j#W;P&GfwVIRkfA^tnhQu* zAT4bVNE4tvoDP6g1+pzW0$MAOmUaTPQXnnu42UR@mUaPz6-Z0F0#X!6OS=I)1=7+y zK(Yd9X?H+KfwZ&-AW4Asb$SBizpe5+JG}s+LUyv3EE-70qCo&G z8VtaqApk5I3c#Xa04y2~z@iZVEZP%*MI!-NGzx%4djYU$ZvYmJ24GPPfJI{fSX2bS zqGA9Rl>o4)6o5rz0a!E+fJJ41z@px6=sXdm%`kn))WrQ2YycL`0btQV04zEf zfJJiwSTqlSMe_lHMdfbjT@j?s8S=Ewt1yeMlv^Bcfg4u8)S@M>_oqCI^etM-^k&gA zvRQNp*(^GgY!)pin?)GkE0a$bz0EEIJc_ zMP~u9=xo6MVD2u!q^|$}U(f9D*#UN0*dcc55L?<70~Hk$#TG>b6chmoMaAy!#>DOx zySux)ySvWkz4N;NzwhsKT<1E6>*9jvWA{B~2-j9>r3>{GC~)Isfc$HZv5> zOdmy`S}Z4DNzs|bY_0qXd5fa6oDW53+o9+jI~2{gL(#c*C_2v$Md#b0=mI+wU1*1* zi)@M(2ozl`P;`kv(WL@KmkAVIE>LuZK+%-~MOO(FT`f>_jX=@00!7ye6kRV+bb~>`?Te9f}^ZL(#)_D0;*WMUUDPJtk1}xIobp0!2>> z6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(UofxV_V`kB`6@|6^oYqHLZg`(EZhoUxiC~9kmqB=Vi)!U({ogIoA z>`>I+4n-a8P}FEsR1qlZC{WZ%ps2GzQ5S)tCV`@6fugPgMco97x(gKb5Gd*?P}EDH zsJB2-AAzF20!94Mu~VsNnyi#RQ5L7pjV~n$pTSkjk+92Jx)6rg}}kIsa5* zwnR-i`AUkGsmZomA`}g9J`@eKL(w2R6b-gR(GWWn4YfnjFgp}2Ylouc>`=74P0A)OF=wH=DKu|v_eb|~7;rf94{(e?sGI|vkw6DZnIplG~6 z(M|$I69kGT3KUHeDB4+|XcvK^$pS@F1d4VQDB4Y+XsSTb?gB;A1d65$6wMGQ+C!)+ z+N7rRNDid(ak`E+IuzBUcW*Om%E?z!v}aBBY5oN!Egu){<$NfbYlot}?NGFj9g6m~ zL(x1t6zyk+qW$eqbbuX-4zwvcNTBFofuchMiVhVhI!vJGaDk#D1d5InC^|}@=xBkW zV+4wh6(~ARpy+skq7wv)P829QNucOtfud6cicS?MI!&PHbfKzfc1@{%K(6S7^jXI_ zp=dz*kLiq>a`KfFol}zy7!-=;J0FV9wL{T)b|^aE4n-H(q3A+86kTM8q6Ky+y4Vgy zm)I0tDo}KpK+)v_MOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?((ai!y zw+Iy7Do}KrK+!^hqT2ZFBtERMB4y5u=`gHZ#p{PTCN1p7insV}$6x~;o z%^DJl?sq;EJz$5T2klVwkR6I1wnNb)b|`w(4n>dIq3Cft6g^>6^rS%1QvyX#3lu#g zQ1q-o(Q^Vt&kGd2AW-z8K+#JAMK22!y&_QbszA|e0!6P26ulu(^rk@3TLMLI3lzO0 zQ1q@q(R)Hw(LFV#Gjkx7e(5IqdqdGG`A5~+`!(g{D=GT8CcAxDDEh?tQ1q!CiaxVL z(dTw3`oa!HU)rJQD?1c@ZHJ<7>`?TrP0@D(Mc)e){UA{Eqd?J50!2Ry6#XJl^s7M8 zZvsWX3l#k!Q1quj(O&{Ze+v}-BT)3OKvAI-SKBEn3KZ1{6qN*uS_u?oLRHa+HKliQ zAeHU&TR5_hLeW2I)RxN0S5nlrl>NJ0D5`Tl6xG|IsGS{(8thQi-VQ|_>`>HbhoXud ziaOe%sFO`mXMv(F0!2*%Ma=?5T?LA|2^4h~DC!|l)Kj3Smq1Z(fucSFMSTT|`Uw;* zB2d&{plDHnqQwM?78fX5LZE0#fuf~^s-o7VQvc<1MLXqROpvuHRj=vS*W_dAQaSlb ziUyUkkt>Fx!On-GA$BMlYKNj>b|_lb4n@n^p=fzK6s=%~q805>w31EH$^u2J2owz$ zC|XsZXf=VN)dh;y5GWcUP_(8%(OLpUYYP;O6ewCpplDrzqV)udMhO(HFHp3BK+%Q* zMH>keZ7fi@b4umpD=FH$ls!K@6z$`DDB9N!Mf2=Xw4WV{_P0aP0d^=l&<;fh z*`erQI}{yaQ*@|6(P08bhYJ)PAy9OrK+#bGMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4f zNdiSD3lyCqP;{z5(P;ujrwbIFAy9OtK+#!3RncCh(l0rXN`3l(dTuD%I4L^2R8GE< zqVq~w)9Rta1$HR9&<;fx*`a8G9f~ftL(wI6D7w@RMVHy3=yIE)D+G$J6ezk% zpy+CWqH6?-t`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCcXrVyS?E*!22o&8Z zP;{3-(cJ=!-9=1c# zBX%fy)DA_D*`erhI}|-(hoUF#Q1p}?ik`M9dPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl z7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84lDEdI4=tH5Z=>Aga z;2cQh)O1(t2SU;Q>1zK+rE>C>6n$387OWMDK6gG8ePM^9FYQqDl^u${wnNc3b}0JR z4n^PDq3C-%6#ZaR^rJx0PXa|h3l#k#Q1q)n(Qg7pzY7%oAyD+EK+#_UMSlwv{UcEH zuRu|uRa|YSs3=fWBT!TlC~758lnE5o3KW$EidqX*MW2*PkL5rr52gDTeHx0+%Wuoi z+O#SsUrABBR@vtxLs5hCp{TtbiaOY#sL>8Z6+0Alv_nxRI}~-cLs1ty6gAltH47AV z6)5T^P}E(ZsE0sNPl2Ld0!6(Aiuwo?^%W@UCs4GAKv92zqD2LY78591T%c$Pfubb^ zik1>6T3VoJ8G)h!LRC>+t5U-{xuO&EuT0MBTUD>=zmvW$bzrM<@|6?~&9CgQ7m9{C zABvW>L(y_}C|ceQMJw2$Xhk~|tz?IymF-ZpiXDoE+Z3%TP_&vr(dq(4YX}sL5GYzx zplB_DqO}EzMhXvMWY0Y))y$+K%i(tfufBBiZ&J~+C-pev_R3O0!5n% zRYikal{U|TR9;H=yB-pXHcVqot8(&{6m8Wio3nl>+S>V0w2d8#wzWgic6KNlYlouk z?NGFX9g4=;p=d`t6pgnj+DV{jf1K+$x8q8S23dk7TG6eyY{P&8YhXpTV9o&rUC2~|Z~v?`sQ1F0OGKA_$*6rGtA z&23dqzLKJOt+G2e3`P4nABy(3L(u_tC_2y%MF-iT=wLe(9b$)~L+wy>m>r4^w<$V8 zpy)_}qN4?P;{{!iY~E3(WQ1My37tmm)oJ}3Of{CX@{b#Y>KWHD7r?V=vslI>ja9f7bvV_VdZbmh?xvyWQRhR^V|FNd+zv%g*rDi2 zI}|--hoYzLQ1px)ik`JY(Q`IM&kGd2AW-z8K+#JAMK22!y&_QbszA|e0!6P26ulu( z^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keIis9J=Cf+H3w2zBE1uP zI20{epN~&lm6NZe=*w2wabrT!SI&o`ukBFujU9@Wcd?iK8Wm(s)L(%fihoTkiP_&{Q zidM2i(aLrxTEz}U!|hPCsvU|}vqRD9HbrX)6paulT2r8CErFu71&T%r6s;prw5~wW zdICkG1d7%dDB3`vXhVUbjRcA|7AV?8plGx}(WU}Ln+X(+5h&VRplA!Bs%ThNS}g}s z>5+d)ezt5Vnv_0yv}IOKzLKJCvuxb9p=dkjL(y0}6m4&Zq8;o|G|mo1JKCXWyd8>m zvP01XI}}Z{DViiuw6j3bE&@f91&XE!6zwWdw3|TDRDq)11&XE#6ipW>njuiMhd|Lx zfudOgMY9Ep<_Hw+DNwYRK+#-*qP+!*_7SRzw$4h2=0GZg)BUcu2}O6L?_RZUR!+W> zq64z*lCh!aK<7izL3SuQ*bYU9*rDi9I}{yehoZynP;`VHijK5H(NQ)qQ|pr$oNq7g!7^3NjnrhWrw1t?NIcL9g3c{L(y|~ zD0U4f$a z1d84lDEdI4=tF^`j|7T77AX2epy*S9qR#}1J{PKr9?eQy=0GY}rcX3J7K)0+e0-6W zldq)cn=IRFLMZyy`B3zo9g4oUL(va*DEiS3ML*f0=w~|={bGlrU+qxzn@!R00!4oa z6#Xes^p`-<-vUMd2o(J*P*kXmtL+pO1&V3}ib?`StptiPfudT0qOw3yYk{IR0!3{F zis}T4>II702^2L5RYhNArTICK%D|-P>rixO`sliSZ8`Z$iaOS2cTWmMotzIvo$XN6 z#STSHb|`ALLs3^d6m_#hQFl8O^{_)xPn)7%0!6(Aiuwo?^%W@UCs4GAKv92zqD2LY z78591T%c$Pfubb^ik1>6T3VoJ8G)h!0!0G_iUtW34HhUGB2Y9`plFy-Rn%Bp`XC2V z*``kpr&3$JrhiX*kG5=WIr&P8R;%1d7%cC>kkHw2na0x&lS(2^5VIC|X~jXaj+w4F!re5-8eOplB0; zqR|3Hn+gs*HE;B^Py;*9g23eL(zCU6zyb(q6u~=nrMfjNp>jO*$zd!*c43`D4HTr zw5veTZURM91&VeTD4HfvG+m%*hCtCC0!1?gie?EE%@!z{BT%%bK+#?TMRNs;_7*7G zN1$k5fueZ=Mf(X=McdVursY5?i=~gQ$A+Tm=`L&g*Ors7r0C$`-*H9g2>zL(#D|MaKyg9WPLHf7uC_zbHFhYv z)(%D2*`erqI~3huQ*@(1(MYMbFxy=s7zSJ#UAi7wk~U4f$a1d84lDEdI4=tF^`j|7T77AX2epy*S9 zqR#}1J{KtZLZIkNfugU3s-h=qOKapnDhH?A(Vh%NhnDj3b!|EMN{YU(&Bo6PML#$n zihi_1(NA_L`q>Uezu2MZS34B_W{0BR?NIcG9g6<6Df&yG=x>3de*}vD6(}l{<7zua zMS-FkfufQ?Q7eI>OrWS%pr|ZR)LNjZjX+UbfucHrqI!X%b^=8W0!8fwiaH1sH40Tl z-`186&w*5~O}C?c7m8j=U*cFPmy@rgs7pD!Y)&X@ay}F_+o7nd9g4cyp{TnZih9_g zsHYu@dfB0gXbFL$B?XF>5-3_)plBI^ zq5%R$0|kl(2^0+$C>kPAG*qBym_X680!7OS6fG}Q6?H0?p2~q#rl(I4buL%0=`WMs zqpgttjMLm#QnX4r`+BcXG~D@6w5lD7RUJnv!wy9w>`=6(9g5bnL($rHC>m)~ zw2na0x&lS(2^5VIC|X~jXaj+w4F!re5-8eOplB0;qR|3Hn+gzPyZLK9Eu)HipG}9$yZXeV>uhPPbeDi zd??z<4n-5}P&CmFMU(7Mw6h(GcCkazWIGg1u|v_WHbuJ$6ipQ<+FhV%nn2NXfub1# zMSBPo%@in_B~Ub5plFUj(VhZDdkGZH6)4(UplBa~qJ0I5<_Q$-Cs4G%K+ypLMF$F1 zMLU#BTjxM3_2~xKaiQqxKKVGPTu#1{qQlDB-t$7y;m(JmBkWLgq#cTmvP03)b|^Z= z4n@b>q3Ad}6diAeq7!V2P829QNucOtfud6cicS?MI!&PHbb+EX1d7fSC^}1^=xl+a za|DX!3lyCzP;{O^(fI;J7YGzxC{T2fK+yt$qKgHJE)lAV4k?$;%YjtJrcV(a8j220 zpS!-aTu#1{qASbUz59ovtDFx-SKFcJ8aotSYloui>`-*Q9g1$SL(z?PD7wiGMK{|N z-6BwQt3c6h0!0f2if$JuxE z9u_EiM4;$VfuhF*iXImzdP1lwy1ZQaCH1UR3lJS5-4gVP?QN2)e01q1&Ue= z6txj3YAaAwCs0%`P}EMKs6n8py+Bb1fucr%qKZIKM}eYFLRHZZ<Ql@xVtot<=8DC*{XDC%y9q8@fA>S>3fUUn$zZHJ;hb|~s=hoXLVC|bm( zsJ}qbq5?&W2^1|ZP_%?V(UJm1O9>P$El{+KK+yn!qJaWMg9M5O3lt3zC>knIG)$mq zS%ISE1d5gyC|W_FXhngdm4vFIrq-ofb0C$a`sZ+(TUW2?cd5_E%B{=ES5mZE>+IDd zLec8ZhoUv?P&C30MQhrjXe~Pwt!;;*k#;Cr#|}m7+M#GYo1#$yMe7R`Z6Hvzp+M0_ z0!14O6m23`=6;9g23dL(x<_6zy(PG)d@BZ1d2`-C^}7`=yZXiGX#px6ev1Npy+IYqH_d_<_i>^D^PTvK+*XEMHdJZT_{j= zkwDP`fuf5AiY^f-x>TU(GJ&GYg{q>%TbGW^fmCMp%HbRliUy`{iFHNma`KfFUDGt@EMiIy)3yZ-=5A>`-*09g1$UL($E4D7wWCMYr0a=r)_8g#tyl3l!ZUP;{q2 z(Om*XcMBBVBT#g&K+$~yMfVF7Js?o@pg_?>0!0rC6g?tP^r%45V**8w3lu#eQ1qlg z(Nh9NPYYE=SG6uZlLM)2*E)xDbtrl%eOb{nt;@+*QuIRW?AsGV(TmQ9qL=JY^s*g_ zUa>>bt9B@Q%??Gc+o9+UI~2WXhoZM^iry9|dPkt>U4f$a1d84lDEdI4=tF^`j|7T7 z7AX2epy*S9qR#}1J{KtZLZIkNfugSjioO;o`bMDWTY;kQ1d6^FDEdLDDtfMUsnbch zqT|#3uAdJ@>!-V{{n)ykd?iJ{w$7G2B^3SUd?@^p72i z{3k^aWrw2Pb|~s&hoZiADC%d2qDAab)ZY$8i`t=RF`J^r1&WpsC|XjW zXeoiBr3H$X5hxlUP&81WXplhBV1c3`0!2dwiiQakEh|v8oIug?0!1qb6s;&ww30y4 z$^u2J2owz$s*1X`DP52QsdP!-Zohk*>NWj`(~WAYwkaoHNzsTl+5KmPqBWflMQhoi zXl*+bjkH72I(8^p*A7MN*`a8Z9g5bsL(v8{MH>nfZ6r{%u|Ux#0!5<*iZ&G}+DxEm zj6l)m0!3R06m2O`w3R^7)&fP_2o!BAP_&&u(O7|^?FEW<5GWcaP_&~!(RiV%X!SOw zPjVoYmC}DdYlNb0^M_?SwJ9fGNzu-2vhvxXXcy;0(PTRmO|e7Ku68Ke%??FV?NGG4 z9g3#ep=i1tie}gp?IBP!Q=n*;K+$Z0qB#OZdkPfoB~Ub1plEM_qJ0F4_7y0aCs4GX zK+*mJMF$8J9Vk$AkU-JF0!4=i6dfv1beKTV;X+l>#5Sd6av+s&)77#`p=h!6f6)?dS3l!ZWP;{?A(R~6% z_X`v~AW-z6K+!`2MGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyX#3lu#gQ1q-o(Q`so z(Y0+#3v(cqa=PF3b)o37r0DrJ<>V_Vdbv&Z`URor73V|It9B@Q%??Gc+o9+UI~2WX zhoZOaQ1rGPir%q9(YrQ9?+FyWFHrP>K+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mt zmjXp!2^4)TQ1p#J(YFFc-w70bFHrP@K+%r^ML!7?{VY@!z1XJoPY$H=Te{KXrBJka z`XK3-Hs$0iDf**L)_XxH`qTMP^p_oq{{U3ly~zC~6QWYA;aKL7=Enpr|5H)KQ?QlR!~t zfub$~MNI-l%>qST1&X=}RYkwGDXpCYshp8M(fE5Ps!iX9rhD6R@|6_zZktWIBoy^= zJ{0w}Ls36F6fI(hqW*R$TGS3ji`k)QaXS<(VTYn6ZHkr>C|X*eXc>W`0Rlw>1&Rg< z6b%+A8X{0MRG?^>K+&=SMau~kEiX{CfXg50)O|?VO?sh1eW{0Bbb|{)*hoU{~P&CsHMYC** zW(yR}5h&VIplC0FqPYS^dkYlpBT%%jK+!ybqWuJl_7^BRK%nSAfue&1iVhYiIz*u8 zP=TVu1d0w9C^|x*=tzO0qlBuWUD}qqT$w96tVa%Kawyt8eGSObZOh45QgnRVY=x^s z(Fx9nq7&^+Ln{Ar0BJ_*@M@IqSu`dMQ_-l=uJBmy=8}@x9w2$jvb2LwL{T+b|`w^ z4n-f>6n!XA^pQZ(#{xy42o!xPQ1qEV(dPn1UkDU^DNyv4K+)F%Mc)V%eJfD(oj}p| z0!2Rv6#Xbr^pil*&jLli2o(J)Q1qKnRrE^R(q}o4%ERf)K3)w)eardyy=^)9N{aq& zo3*(q6#e6TDEik9MTNS!<{pZQb||W`Ls7{NMXl^ml-Z%E)(%Bwo1)eNMQsF%+6ola z2^7@}6txp5Y7i)DFHqD$pr}!xD8Ga0Ir%I2zrOc=M}eYF0!5t#in<6CH3<|o3lwz~ zDC#Cq)Lo#chd@zJp{nT5wxxkNkjj#aREp=fbC6fI$gq9yH6w3Ho+mbOFDGB!m61d0X<6b%w68Z1yWM4)J>K+!OP zqGbh&mJ=viUZ7|N!T&`o3KXp*P_(i@(JBH(!v%^~6)0LwplEf0qBR7HMhFzGDO45p zsVmLSfmAN*lf&s-SG}fROr+MTD<@w`(YkfnX}5)<^_&kyqwG+$z8#7-utU*?b|~7& z4n-T=p=c936pgk+(WW*mhX@oMDo}KoK+)j>MMnq} z9Vt+Blt9tZ0!7CN6dfy6742GAD%_DPdN+NA^=_f)h5TXJadqY7D=9juF6(<&C_35s zP;`nNicYmd(P?%lI^7OMXV{_WOgj{vWrw1(?ND@%P0@UTqH_g`&J!p)U!dp$fuaiq ziY^i;S|Ct#u|Ux!0!5b!6kR4zbh$v$6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z3C zRnZA`rFC*3l^fFs)F+0bJJZKSH`bMtucYYKx@?zwLeXu`hoXgcD7xJaMR(Yt=uSHn z-DQWOyX{bPj~$BcwL{T;HbwUf6g?nN^q@e|Ljpw)3lu#fQ1qxk(PIKdj|&t%AyD+B zK+#hIMNbP9JtI)`tU%Fo0!7aY6ulr&^rAq~O9DkN3lzN~R2AJ^S2{KaQu!o(IqWT= z=%w@@)2nsmlzEJd*^P%W%I~2WRhoX1wQ1qT1ir%+F(Fb-Y`p^zVAK9Vk zW1FH+1d2WtDEdsG=yQRhF9eFd6e#*ipy+FXqHhF>z7;6?PN3*}fubJ-ihdL*`bnVZ zXMv($1d4tYDEdvH=y!plKLm>Y6sn3|uPeQf1F77RK3)ArDB7i0KK`mJCtpcXp+5WZ zflySekE^GlsKyROB|8+gvO`g3hoV|L6qW5z)Y=Y3ZR}9g)~2XVpr~G;sGUGjgFsPx zfuarqMU4VQ6@j9T0!5t!iaHAvbrC3P5-4gGDC#Ou)J>qMyFgJ7fuf!QMZE-ydJ7cw z5vq#*sVg-{ik7rP(NcCO zTG|dp%h;i4fE|hk+M#HWP0?V1q9FoBLj{V42^1|WP_&#t(eeUCD+m;=C{VPLK+(zq zMXLxD4Hqa{RiJ1!fuhv~iq;S)8X-`$ra;kJ0!3>J6pa+BiWaFa?T`bh+?>AiO#k}o zHT@IPO|$FNmy@rgX#M)^fJZ~o2F{0~4ee00ksXRQwnNb-b|@NchoVjGP_&sHipJQX zXmgvQEd+|T6e!wCplEA>qHP3hed&uFNM*Nlzw2qC=%}RV#QJjbl@y&?pVd7TicWJr6rFB|qBHDJbfz7O z&ay+%*>)&8#|}mF?ND^C9g5DgDLP-E=mLSF3k8ZU5-3_AP;{|C(Io;!mkJbJCQx*_ zK+zQfMOO+GT_sR-wLsA|0!7yf6kR7!biF{)4FW|s3KZQWP;|3URdjNFX>bmtvSYg6 z^(mp~#dOo`E%oK(D=E6YKHKz}P;`g$q3BLK6y0TqqPy)-bdMd1?zKbFeRe3i-ws6& z*rDh_o1%vViXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!?g7ASf~py*kFqUQvPo);*3 zL7?bGfuffLie45ddPSh`sr;Sp4Dxm;TG%lk|JIk2ucWBdE_*xwe0HZb2N$wd?f&~U z{mc$UwRR{f+o7nn9g5o6p{T7Lit6l8RBwl(b~Z%~0!8fwiaH1sH3}3}1d2Ke6m=3P z>MT&yMWCojpr~1(sH;FxH-Vz=0!2Lpih2qZ^%5xREl|`)ps24vQ9psAMTDxNV!Kk! zi@Bmv>8{o_?W)(&=5@+P|90i%D=Au{UAD-}p=e3x`=6{9g3E*L(u>`6b-aP z(I7h%4Yotk5IYnNwJ91VP_(Q-(Q*Ps%L^2(AW*cTK+#G9MJo#wts+n~T%c%Gfuhv} zidGjWT0@{{gh0`n0!3>H6s;{#G*X~w9f6{C1&Y=as)`nCS6VLzQh6#}xnDdKW$6}> zQSHjfS5mZ5yKKsm{tqD}2kw3!`>#@L}~b2}7mVTYnE?NGFpP0`i@ zMcW7zZ7Wc;oj}o8fuijNigpkv8YfV+qd?JkfufxRiY5pYO%y1aBv7=oK+!G&MUw@J zrU(@6Dp0hWK+#lzqTPk6q7B-Wj?aNqZcO*P-Y^smOdljoYgbOblA@XIvg=+CMYEg_ zMYHWtG{+7_d)lFBFFO>?wL{U~b|~7%4n_Ogp=h2>(S8C&`wJ8uAW(FmK+!=0MF$HM z9U@S4s6f$S0!4=l6dfT@bfiGhQ36Fr3ltqAP;{(7(QyJr#|splAW(FoK+#D8MJEeY zMKju!Udn+~E=upj_6SA0Hss@!cID(NDLSKF_Vb&e=uGEB(OGsVI@=CK=h&fWz8#9r zwL{T)b|^aE4n-H(q3A-JqKgEI76=qwEKqcbK+&ZFMVAQ_T`o{`g+S4j0!3E|6kRP) zbd5mKwE{)g2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xNMYjo6MW?kZb$csU)SPaBJv|f+ zPM^qL*sh#>B}I3&%T{?O6y5E7D7wcEMfcjF=sr6X-EW7Y2kcPvpdE@HvP03sb|`wp zrsz?DqQ?Y^9v3KjLZIkLfug4bik=oIdPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl7ASf} zpy*YBqSpk9UKc2OL!jtQfugsBs-ipEm3GX5RDN&D;oKRDx~C74-fmY;zLKK%+hqs6 z7m7Y`J`{auhoX<{Q1r1KiaxPJ(WiDO`pgbRpWC763p*5jX;bu-K+)F%Mc)V%eJfD( zoj}p|0!2Rv6#Xbr^pil*&jLli2o(J)Q1qKX(eDC9e+U%)DNyv6K+)dMKyxPoQWKfujBbMT-g)EhbbIwQ4ARl>@2Vn68#( z4b^M3d?iIoH)QQT4n@m2ABqOpp=h8TiU!%CXs{iMhS;HKs2z%i*`a7z zI}|NvQ?$H5(Fy`ZD+&~?Bv7=nK+!4!MZ*P(Ruw2(O`vFXfuc18ibe<&ttn8nmO#6)o9N8kz&C{FZJyTPhR{NjHaV*icTslA_TK z*_cm5(WcIaqRs43G{z1^o7`=6|9g4QGL(#T2McWA!jTI=`UZ7|P zfueB&MLP-V_Vn$wV-^?4}T)A>-emmP}c+M#G~ zI~46>hoXJ$P&CgDMf=&IXn#8t9bi**pg_?<0!0T46dfW^bf`elVFE>m3ltq8P;{g~ z(NO|LM++1kBT#g#K+$mmMaK&iogh$jqCn9}0!1ea6rCbabgDqnX+l-etcKD(Igmo#4n+^xq3A(76g^~zqKEBJ^oSjb9<@W!V|FNd+@|OWfubh`ik=cE zdRn098G)i_1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+Xv8%pcvKq@tTaya*dqHRn0c(0+Hd?iI6HDtSe7m7Z1J`{aohoVpI zQ1qD{iaxhP(HC|o`qB!%(z!y31PDzMOm|MQz$=H~bKa+BzSK>g-TdZ-=6Gb|`AFLs5G>6m_se zQKKD-Dt0L9Xj9Zlps2GzQ5S)tCV`@6fugPgMco97x(gKb5Gd*?P}EDHsJB2-AAzF2 z0!94Mu~Vs6f$T0!51p6fGf8w4_i~RBm5-B?nUZK7G2nb^Gcy{cF;X+*_)B zIr&P82DZhdZ75K*kwDSLLRHZ+?Mpp=&K2#H6b%SP6Vpf6o3t+{UrEuJ_SvexhN8`#4@Fzp zp=e7x6m4aPqOI*vw2d8#wzWgic6KNlYloukZHjgfC>keFw4*@Lc!8pw1d1jI6ipN; znj}!Pvp~@<0!5Prilzt@?J7{Tn?TW2fuh|7ilzw^O&2JdAyBl3K+#NrqFF*!(WdQ7 zJLNzs52ib&Z5E0?ONwT@*GIz;`B~zuTXSI`sC4B z?aRqmQgm+n?D0QC(Rt2?qVw%gbb%d;F0@0@MRq7!V27fM?ND@y9f~fsL(ye6MVAW{ zT_I3(r9jbD0!3E~6kQ`wbge+qbpl1#3l!ZTP;{d}(M*ekdB4ZjHUCeL49`iXLd6wf`p+J?MNW zddLn%58I*W5jzw;YKNl7>`?T$9g3c?L(!9VD0<4K=xKqXX9S9#6)1X6py+vlq89{; zUKA*LNucOufudIgie42cdQG6{b%CNc1d84iD0)kv=xu?bcLa*w6)1X7py+*pq7Q_s zqWjvHmd$}wI;K0O-5-kfPxmkSuzflCN{T*hpKVb{7m(lY`ZMQ4(dTw3`oa!HU)rJQ zD?1c@ZHJ<7>`?Tr9g4oQL(%s(ML!4>{U}iMlR(kW0!6og6t#0c6gAkPsJ$JEI@qD8(GEowI}~-aLs2I?6m_;k zQ5Tz{CV`@6fugPgMco97x(gKb5Gd*?P}EDHsJB2-AAzF20!94Mu~Vs6f$T z0!51p6fGf8w4^}MQUXOw3luFQR28-DP`WP%QrRbcC{)*>dQJc7q-a2ga`KfF4e5}* z-zpRhbv_ggvqRCcb|_lT4n@n`p=bp=6s>57qLu7Ww6YzFRE>N_pK+$RfMXL)G ztszh}LZE0(fugkpiq;k=8Yxh;jzH160!8Zy6pa!nT3?`O1A(Fq1&THjDB4({XcK{= z(E>%A3ROjeI+SX&T+xJdJKEq-v_`r$cC!xUd??!54n^D8p=et> z6m4gRqOo=;+TIRDJJ_LUoE?gGv?&@dP_&ak(FB2_i2_BF1d4VRDB4A!XtF@j6oH~$ z1&VePD4Hrzw7WpjG=ZY&0!1?fiuMpFnki5;OQ2}BK+zn5qCJJGqRl&$Hq3!kPEYsV z-y#&Pmag{i)uEhxB}Myo$aZfNism^ViuSWZ(f)QQI=~J^2il?NAUhNtY=@#l>`-*5 z9f}UKDLP!B=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZCg%fua)yicS(JI$5CT6oH~s z1&U4+C^}uB=nR3PGX;vy5-2)bpy(W-s%Y;HrIT|Yl~?=ZaP|pBpCv`}JCu{Jr09YU z*-dq!=tAd1(M5JBT40Bwi|tT!i5-eAwL{Tmb||{s4nSQ1poNq3BUN6g_5# zqQ~t}^n@LXp0q>JQ+6nN+73m}*rDiIo1*6gik=rJdO@J*MS-H11d3i3D0)Sp=v9HD z*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>WiryC}`aq!QLxG}?1d2Wus)`=$Q0mo? zD;kkLMf6Z8Iwsv3`$>m#@|6^Q(IH#CLn!*v`B3zg9g4oTL(w;ODEih8Mc>(>=zBX9 z{a}ZpAMH@|lTFdj0!6@I+P~nKq^Diz4t#4MW?jOM_pq% z`AUk~H)e-bLQx0jLs6q0iYj&}>S%|ePIf5jY=@#Qb|`AHLs7FGin`hqbrUG+E>P4% zps1%nQ7?g_-U3B^1d93!6!jA*T123zzd+HV0!51n6fG`Lw1hy>k^)6b2^1|YP_&Fd z(Ex#>fdWN?gsP%;jioDdAeGCq98N=H^_u>I^jXKjjpgJkDO$EMd$Lm~TF&`Uw7eaP zR?Xmx?2H3W)A2o$X;P_&jn(b@tkAZZAW*cSK+#45MH>qgZ6Z)KTA*lCfuhX>ipB^OZ7x(54Q(ua zmjkJ+kgnVh3q`Zi4g6a)mXoifXq(2Yu_+X7>wGBM&JIOm?NGG69g23aL(w=p6zyn- zqVaYp+Q|+@6Kskm3KUHeDB4+|XcvK^$pS@F1d4VQDB4Y+XsSTb?gB;A1d65$6wMGQ z+C!jdra;jwfuh+0MRNp-_7o`EOQ2}3K+)bpRnbm>r4^w?okpb|^a1rsybvqN4?h zju9w2R-ouOfuiFDicSzHI#HnLB!Qxn1&U4)C^}W3=rn<%(*=so5GXoRpy(`tqO%2x z&Jie@FHm%@K+$`-*M9g427L(!FXD7wlHMOWLQ=o*`%YXyp~6DYb~py&pHq8kN@ZW1WES)k|^ zfudUlif$7qS}0I-yFk$$0!4QU6x}6Ibhkj!Jpx7d3KZQZP;|dQ(E|cS4+>R97dDn2 z$bnS))aP(63Pn@XC$b-EEGJ({(PNF-hdo2lv4f%k(uMkA|Wt>8lz) zZ!9NYNzvDh*^+%i(KpVAqHpa`^qn1wzPCfs4|XW}(GEpF*`erXI~4t5hoWC?ihdI) z`dy&t4}qdT1&aO>DEeEV=pTWie+7yPmAKkYQBk0%Mxdx9P}EAGC=)2E6(}kT6txy8 zY9mn8R-mX(pr~G;sGU$%^krjd;~Yq(v6932DioccZVqXvl#{Qds8Y$M_X|ZGoexEw z>`>I%4nY*pO@pwhE>YRS5mY>CA+16C|c3^P_&XAidMEm(JFQ*8g7T8Rqar; znjMN(w?okyb|@NQQ?#Z)(OLpUYYP;O6ewCpplDrzqV)udMhO(HFHp3BK+%Q*MH>ke zZ7fibFomgz4M`H2RjsvvqRC2b|@NehoYVAP&B~~MHB5%G|3J{JKGfPB2YA0 zplFIf(XIkTy9pFc6)4(WplF&v(R6{L83ILn2o%i}D4HcuG+Ur(jzH0#0!4cX6wMVV z+FPJ#AAzEM1&ZbgRYluYN_`g372TiicfDOGdMtfa<9?NL@|6@FRLMpx8Hx^eJ`^2d zhoVF6P;{6biVn9!(GhkiI?@hBN7IGLeseX+tIdaIw-%Dq;=DR z{2gI^)5DF0LWibL^LqkxYFawK>uqz>9{DBoXu2)G17)A4zw?i>`ZukW|Ad+)nvUvQ zC@jp>TQAs9g(%tD8=k zS}0uK^zyVq;pV39dlU)_o5s&76z*!eY)+wYU(?rn6$%eE4cn(sc&usfd4IoS&R_q<=8fj3A6eXd%6a))pxFHS1^Jtx*xY+T z{x&E!Pr4+3BNUsjx-5Sy6q~=lB7ZX!n^(9xe>)VL(@(SSUu;f4j(mw?bNYGG%M_c_ z4+I`uY)(JXb=hKb`jMO~7Ms)0R2*JxPCpcHjbd~9sb*^zo70b_TCdogey-4l#pd*b zVMZ65(@*x;yx5$6G{e@#=JdVw#}=E@H%H&G*qpw*^~7Rx`u4<=i_Pi#%T6ser*9BC zqu89j!{h8?bNUv2bBoRCd#ueXHm7frbzreMeV3y{i_PiV)ErrCPTyzb*kW_~MiD0# zo6}eNpIU5AU#fj(u{nLM?fhbM`eMloip}Y(-7YRRr!QB!yx5$+-sI|HbNYgT>x<3l z9^W??o6}u(7Z#h-eJ<}RHm5ty-B)Z*_j-D$*qrXR@>sDs-S6P3VspCT__<9b!S6`RwiFFq?ar|X|z6`Ru)i0_Kc=_A0Oip}X= z_;1DL^ndVQ#X{S2^M5GW#npduU0Zc16l#}k>{Bijx;>KrYbp+_>zMyN{c4rpkX@X= z?%-mf`)zI0Lk6snKP3OmNz1S9@3cJjx~YxM%bNM`9^d9ykBiGSoRA))$F&XlSU$!r zX{-?A$^4&Zam9ulVg6{(=Fd)XrFh8Fz4EbgjGemWW0e?F(ik3Njr?1h7gvq(eZPFH z7Nb>7K30#hF#ivrxJGsKJT-q}>4kZ7K(WxPIJ&m+!WXYOWNxqGrdfUQm*U#JikoHi z3p$?JxmR&aR=>u=PlgnF=JHyOGz^R*@0@#k($;c3O$?iHa>5gS6fy;W8#l>El;?^`|UfmT*|qZzLftZf5O}EcK5tO z@APA}rsXGkE+0ov@*F&V!@oE0({lFQtro7IpRH{?|KrC_-oNGWm>!*WD)iheo`p;P z<5`#(m-D*IdE>47Ki{wAa^~Io+LV^ddH%$o-p?;Oef~ zHGg`wjSoI>^B4K+Fn?`dwaK%k}GXSUAIq}Sc{)icGxg`Q_d+M}9UUY%Fw zExkGyxaePoO|EZwQLfx`<@^Jh?C0Tpuc3lg-ug^~$nV;zSSR8$?dbGCj z@0)M`WM0d&_4277&fmA?@NOq{Z`X3T^V~1T7J6P@Dilu34|mRgx48M}$`9{LXR`X6 zww{pO)HWV<*O!0n-SVQ`bkLj6?^EdWNE~W8aMHp@E>CZ>+Qu7>yzQd=@$%h=fb77Bfr?o%kF-?cTR+P)9v@8i<%+C@uk`>vGN^t-l{KjfSI-%7^;hAo;JiyfK@g_{0_ zy1Lc!R4A0X6iN*%*R4{wQr)PI`M>&jNdE6UTdt5wZL4CbVYRxt{K3^nE9SAhM1HDA z{^VM>{3R5Ue@4?&Zf^NY{<3vl_CKEH>RpHDccAY!u(*0x&&c9kM|Es0R%+L1K4ZFIXQ{^LMR(`{?!uk#-Nc_Hal*Yl`@i}~ATNXu)d*U<+T3pLFrt(pIy)jNMcAw3{} zkLhu8A_EKQNl$BNd8+xdUik07^7q~O`pyp&Twtm2Vt%Bi_-8}ALNWi9KW_fJIB?*g znd1lTJZr|FSu-aLnmKOPgh}IO%$z=Z(uCQQCJve~bMG0mr>8Js(!@D4C(Zhgho#5Q zAA6-iGiFZNeah@9drm40nmm2?NrT2uoiumQz^T(GjGsDa*5vUsCk>i8Y1*V&<7W+; zG<4jo*>fgNnLcRt^yyP4OddaF+N?plOqeik{LI}44H-Oc*tnsChYlGxWN?ZD@;G4H z^l6g@Od7w_lmSBq4;(fiJ$PXL;Q#iZK~ttpm^x?Tq(QrnpD=mKwExeajahro`p?(I zE|Uk1m^pFIlxfq~nm%*VfdBEjm^*uB%d4dN8W}xv`mXuweAb{bGse%{ZJjyO#%-Rz zEW3=JI%n3n%|J!|>LP#RXuvX1{-zp~D?#jIG`rBBwm)OBFidSI5-j?F5y#lgMu zzYWSd<_}JP<|Y4gaG|DEv2#|J{%D`|O@HLQWu}8e^GENJb?cFJOlwfqEq`FgKL2Zf z?b|==*rVkEmD-M3$KLVR|5Hz+Qrl_Jput(kLD?duz58U9zHvT((v_CWtnHjtdZtUP z?UYqoUX1){R9c>f7v#TQuwMD|*t$>Frnb~>c-AE!Z5GM8^vriU-DR1UzjVyH^iF>n zRDFc}C2LBLnE%-?|Fe6)tiD&)uC~-|c>WT1%$Dqzb?=$)>dW8GE3ISom9}KO(pu)g z{LzMH-Sb1s^v;&-pLOpM=Q?KHd;ed#i2S3%tlb7#_fhFk{(R=I`9UogkY9ASmYB5} z-11y^$)EX_7baeoc$2oTK6i`8bJsEl<}c#VtZRBvH^`bswY&xf?Gl$VC|k5&*3_fr zwb1fv%U|B=pZ|xK*rm29Yg#ftxoW%~|CfJOFKN}Re|jVI${)2~dd50u@oe`0&u25e z@rJfM?WX)$$Y1zH2WMTn=dthqcr*Rqdj|V2o;4+5=?z_dga7wuv`hX3{_|Do74X0N zytX{+eX1`=dIk5dzSi=y=@s19Wq3+eV)cFUw`&60J%3|#>-&G5Sn|<*c#EiF{?8-7 zutN{{|BKcfYp1MTFaKT!XWi1jra?*WDlN}(huYE|`Ey$=U0WR3@-OxK{cCnERw4G! z5hfr19o_%TM~9*5CH|o>aF>=>;1c;i(DWqYO#H)KB22Z+K3S)sHO=`)1nZ0$J#OS? zn~fW_@s=Yt9JThi5u2^M#YQ7H-n`%e8;u+@X2iN9$8EmJCgV2TWaD)UoBdC$-3N3O zbsP5oB)gkUvI!y}*hNJJ1tfG3gpdM}G*f7n(2LTfSg?y&u=lRmd+%MbVDG*6Ucic# z_rB+MeK#AP=Xw9S7wxnN0sS#wQoqg}Y6yuPu#Ed7<;>g-CJY8smA>T3N9&2^RI%Bz|y zYU`^@8pAExRkgnOh^pGs(amKgjU~-BP1PgH>;3zvtq+&(GcfapYigStnnpB~)>rz) zDr%c*%A$)67&t1LgIcX-eR)G&t*v3WroMI=?h9Y{^7@j7j5X(et8N(CJff+h!mhue zazc4}k^lJ4Dy#k8j4tE%wZ0;H7|Lr(ES6=}Rx~u1l!dG57hT%dtRmwZ zFK-;h{o7nOYJ9Uj*46eXmzFeE*4BjkX;6B>;?j&IE9-Y}9%07HDjUL$abJe3^ec-V zw&tqJn$hWdZER&lWphbgw3el{H8tg>t|gLJ(bw;==+iQhXlN=eHKpmLA-j81c~g0F zh22x>FV&UQS2m7MM@L;{i56FyU^t-itYK)+)!Il z(cJ37#e-U1y0oOGxv{>arlGpBF}mjZ@{+Rg(Kj=q71;WQ61$@4p|(3%u({3JhSKJS z##*~i%Z;NR!*JiUx{{3NQ~Dd0o|3BQmYZwq%4^bJgYt;_%8{cQYwR9vZYXbT^ye}+ zT~S&!I$GU6eZw=SUv!JnjrXF8o=j0?g!Nbr)EA5G?n_@=Wo3OuNppE=X>;+2N zTRjz{O-os2$;jr~rpCIa#^y1#RgL!iNnZue2H&Xo=EpZ(8PCqL@-daRKRKeQA>7OM z+{oM>g{P8ZwmaFM+=W6J9*s%posf1~v^Bh#Brb5&BEzCdN2ZOrr# z*V*PIb9)+nOARI=y^-vlzQaaj+&TULwcK>@p7CXSAnYz_E+1D~US5{5%DO{r3)@&? zTZqx+;%qt$w7`H)iR(uDEyl32smI@C3By z-_*r(<{Xs1?&#@IUR&AvX~QksX1Kbx-X9L%PKK-K9X&y2&zn1=vu(7Zt}j<#Y@e{K z-G>deEiY5P*-w8>+ui!|s`6;t>~~gqYe(Uc_V3vq%*u*zr-U`=pK&YEcE=wa-@-+& zW?IWuZg|o+mz0(^)t8iN6P8||QT94Fw#2^C#>(n)dz7N<7?^&POEYe;&K{$N`ciXL zQrcKKCcNhK&v>chNog<6BWt1;=7>TcyNG{M(rV+Lxn*eCVilLCA36Uty_$kxkG(y| zoAh#LtJ!h^yU`K#CH9goLVk<(=wv>H?5<*STUFbjC-K1a4cfyH?!gg!QXW0v3un!k zJ8f!bI~TAZeRJ-)w!*H?khE-~TQ&iurM1nYY}1rpfcvJpwk)i@z3QjGSXy3H)l^kd zZ^%bhHkfCBsp1ywj=gO0=v!>H(QaxO5xrbDH;l4 zdD`5mvnI`L_UBUi$||d>%14$|=_zNg@@4j%Z+V%Eyr*B0G9KmPfvv=g$|$?0jGe49 zzAbxj*E3P+o4@roJefNYwke37!qMH6er6Q+Yjs6DeR#AoUe7D%mQ7kTsd@CYgBtDJ zLi*eNudiz@f~v}DqfKi1Wkip5cyMfUqX)IPST9%h@}0hJp7p(&%XV*UE*lkI!CSxF z_s_Vzwpi7+O=_x-UYMe-Vujr`4Wlx)$0)8U8Sgufdd0QRY-2Tj@!ToB`u54nOntSs zt&pa*uXmsG_-E|?R@t+mMF6)xvZT7Yq~+Glr0rdCci3|_y3v;Bb#ZazV`NQJ=h8ug zI{R6=p2eO0JYBDWz590Vx?tMuX_FRC>(;r)oGJ4c51le^!J=sg_L$SBj}?n%E}k>l z=JeU~CN1h=C;5ijR$!_ZcFF1U_wUzZ;rt#`i~CzMX~C44L+z~J{sVi=={d*F8}2l9 z;ryMZ&+pu0M&};2y*u}?vq?jz*b4NRK4;p(g_CAX>oI%U+!>2z4((-Cc$W3>jf^F~ zFBi?4H@C+^JK<(?p>O#zR8GK#GiT9r zqV-;T`qj^N{7ObtR#i@D+4JsYoAltLWZJ^w-UCbRd}!s|S&JGLPtIz2npDo6I_<#d zJM7bH1KzT=@uzGWd&_giUg2yz)Mz`mzNe7B0B)kAuoh1Cye_rLhe>-+m z5#4t2fR^W&?N5ZR^&yZSp!n`cr5%BU9hY!_MBHap&6_vBI4c^x|6^TR?G&`y*RHl} z8c{ng^Lf;N;D0P%T4k?5_L}ZnNWW3r$@OPI`k7eVtGB+3^yc3lru5ac+-JVW*sMD) zEMc$H(I>_$6t?Zm*kne|T8<3Y+u_&NxAluvU%RGh&3*=T+JXh)I_*I5zpPAnsi-e6 z^|cDS!NqpK8!ZwJlN;<*bIZ=FzuvX%_1Ph^wgP_0A3YTIi7G!Pk1E@1k3I>9s!`P| zeW~yn8}W?Y&uFLFj;*vSXq%L9ZT78Y+&38u_};8-AR`#jMOzL!(?`qwbuHmIky{Nf z9p%+^83%u*emWxah051E^VoINSUclUI@-3?;X7*e#Ni3x`$y?}oig*l{Qq(YSW#I~ z+xqyl#ZXyEX>=~U)$3b&Gyk8@5IbDAJ8fTof}~d`eAi7iC1cFLAAYC5l5wY&G}*zu z?E+>V%=>N|cU|x^(hiKmK2-V(5nA6*uC4J6M6_d2{D1wbo<4S@C_pU-h^>$N++dnJ zE7DL`*{tJte>^zeEJGjLF2kPo;M^)Mps67-lwij+^ zG`Pu#h_8qZL>~z*jqWPe!PjlQ-G!0{KQWg+r(@5d z^p&QM2unspr|8mO$hafx%Nzgeo_n-Ctwr3_C2spcHC+Qhn1z3(MwKU ziM`@Pm$KK5@QFP?TU|VywJaTF$J6Ci(M9ZVI(>EN=S#)d<|aFBW_PBpP}gTC&A10` z!=X?8h)`?Ua!q!Upux9`EiU~c|8+N+2e;LUz*c+g=_3G+dBY(Z_k!-y*3V2HtLXl) zJ+W|q*nwci{oyZqel*nFFt)PMzLN0@$`NC6%jt$<+cIY@oN4=J>0@s{K8$X_UX-Ix z{CLodaM%`oDdP!c`|B#Q&eizdik+Wm9$8WuP7a#8^u@Sy>^P*Us%3}6xwCJR zxpSO8Mbw*9M1Ca69mSRTK1bF*(YDW5(GTRfNaj(8oqDY-wQY!P(;K7vDSfF1J6yKY z3p$0s{g&~@_W!H5bIYbpUOXeZNBy9XmGq}#$%tSpoSx<@e1{cwtY?SC%@tK84K2&@ z)uuX^?dKaf^S<68S^BXlttf4IT#Ee!IJcy;DB(3SdZ5GEd;c`^BzSbpxZZZ7WiPU< z{D166`U5<^yfG^}XLEIr8SLu zMaeu@9j)JgzCMPdJHFZUIlbsATTXfx+bOur=TpmhBma)WGojTMD1COouQ7dJW}-_U zUh58y&PPW#%Vxag1uUFg_AmO8WON}v)5=;$ueb)l@Rr(h?Z3bE5zZvHyd3? zy{%5)VHsO5KLX`~+(gixe)Wv*t;{p15rqHt;u|)_=~Hf8Z}iR%Pkl;%SnHd@X3RIb z^x8z*W7_&8ZN>qPo$QGoLVLOXPf~mnw#~DbB<;rQ9UG2}2DDm`C2X(MbeGxwNXCu| zUrfKR#0zFP&IsIW^`j#vJ&!WJo6HBl)f+MTHk)cj*VK*;_X3A9ekR|qHyj~wzl^Z+ z*7mMk^o~jNWj{{giy6BLtX78b6AO3O`R8eG<;)`llSX6lb0y)wTNR_zHVU zaEgi>4c{Bv6g>$u&bGEb+FSKn1} zI8*Ca8;+k?J$tV}doR(R1#cHbx1X_f7Urw5p`KF5{It+|B-eo?mav8(S?q`^A0J8#m z97EWvp6=c7s^DJ^JNw*ZUD$)R^Ly$0C30fhjC4_2UDoO_(wy^{r60XaXf2ysKjEGE zz7wk(zU}C4v%569|61?aw_Jt2HOh_{>&&rLLsNsj+ofaM|2Wa<=Q!7Udn5BiNUv6> zMOu#f?45PJS>~(f2PNraC2rqe;iH$X|8`vJb{rqaT7E4R`W}nz%vJhc<-Q1KO*4K_ zARHh>cTVPRXLKYt*53T}x4&!kelDvNPTc#Of9r4l{bkMHE@yMa+pR1)qN=23v^{~# z?R?jI`$Yb&tbg&A2d1jl-rlp#iJgossmVC6=8sP6^CIE6Bt1$a+6YUhnR0b)@K?qUV7h(QqZK zT4_nC-P0A#(aV08-#kC;z(J17(sMHNh$e8!*bDJvr?9#5^M1b8VH3eEM$i3*|Mm8# z?m1Q~y@wQzM56n^PY-fs(Q8aiNz2bJ_+z*Jolw`DezVcyqDaoJ2}Wvh5y7w*2vP*!JWJMssEA%b2^vLnLKUkRC_P4k)Q32 z-VNYqcDw!W_XhmOmJ99QI{UC6+&-jDVNq6RFZJO+%3Ru}^U-s8n>a3hd~A8n z$=O*YgX{v6{HKGnvUj#m69aox_q1b$nylOnlhygLg1mO|4%r)JcZzMCy-D__*_&l= zp1ozxHre)z8~^cksp zg`e5B&%)RJ=e)y5`1)HJnXmYaW!bL+WPHTZzd01jSeE^ML&iretM$*b$Fl7Ai!wf9 zS@!D;86UA|?OKXhmi@GR#z!p6{>VbcM=Z;Jq0_S8EB@HDv+t*S#@Frlpt1(9m#f#y zd#smdt(Om2FE3j!pRiu$M}xyVCtVh0b(#7<-wbK}`t@JlG|jv~amEW=FMF?` zL}mYtqXPRqiTOV5dbT%5J{x`7^_;1Bl~21q|JCyX`yH>xmEW_OW4}&zh50J5-yK+~ z>8f&!ia+;q>_Ky*KJBWbX*ZdbW01G@X=J*p_ve~luD|9`%@LY)noXKhH22ZmPxEli zqcu;}yj1gc&3iQ;)_g+qSqoTs_J=AoKLYo4Hay5@PBD>Sdxyh-y;%?C6e)AV1} z@$c_t&9^i^)civ8d(B@o|I*B{=bta1uh~|!ljfG1+i7;!?4vnYvqW>0X07HJ&Al|I zYVNDKK=UBYBQ%fIJX!NBO@E#8^}Ss4I?Y=(@6mi%(|=>nFaNyeYntzBexmuc=4#E~ zHUHI2*lUYlPoZXe%}q78*6gaevu1zIp_*lyqc!U_$7@d1oS`{abFtSfY4+CKMYBw^T62tMv*t|A{WOAxQC`CZL5wwveqAI<)@FX6dV^AOu7@qE1IO53OK{Gw)_{jWtmZ=_kXRmgj2p1F0% zmukMVZOC70cHTbZ9-7l_2g9##q2>)chJ3H)PqvfkUtgy=&~`*TmuntY9P$a8kM{}r zWz7QHVe!j%(ySX8@?M%}4-WZq&G&|c{I%vb!$RI!b7o1%i#2a54f%e}U&=$yt_X9m z9W(ju+Yb#z^N8KTJW2D(s*qpREUXQA6V3YFLvGeQw;|*!H9xQ&F2DY7HM@)pxma_b z2_YY#dCQ(5KdAZJ-XX`D!yGax%u3Cpri6To=2O!`eqFQ8%#b(JY}_a0Nt)-+4*6=$ zkLHH_z2^4&h1^GT_QH_u_bH?A>$b&VKCHRc4ifzPO&l2Ju1mrkt$FkzA=@v+N0)o% zurS}$Y!1khWw*u*X1Gi)0}%^$OmiQadOCyYW{g@$jQ^f z9DYWa)tbkg74jLH&z%$U+nVjp4|yxiaTkU>P4nW5L%v?~vlSt)(cJO!kOyeazcS=Q zHSfAQ%tsyLzuOi$K4e2S(-2067sv69c~YKYt0FFhCD-a#oZy_sQHEM z==9L<-W4*7k}j?aa> zt>&IDggi_0vX?@>S@SFVdnmrXziRe;J>*?97rhzsk(&3t9r7y8toK4L(yaI(JU^=$Zxix{n!B|Pd93EC_P1dC@)v2oVF%=%Kh@ma z{yL23Zkm(rK+y9%&1>xM#dy9`^9TFGF`oa@?Atly63r#sgnX>#BV9s%UNd)xklSlk zbqjgC=56*joBaA8)_hj;4WEgutk0EK`z*9SHl+E7`go7f=V=!CwCmeca|g}7nkAYw zntN!@)Lg82l;$a#7iwPX)7I-f%?)~nysc)F=H8m8YhI=Kj^?MDo$ODI`1Os}+*@;j z<`tSZYJRNQ(f-_sFE`4keZN(jO`791Cu>gEoTs@^^AOD=G>_LjN%L&Y^ELCb%)8yL zJrvPwuh~g+Yt8L6yKDB+tkZ1N+(Xk|o}=rVu4yl?QC_5JFNaY+Tyv?Wy-Y>@$(m@A1s^K9Yh^GTB@FPOG}SUxoN z7bY^}qy_%V54weLiT`Y7``?GqHQFj>_4L0wFwK77DC1VAFPJpPE>u!q-E-2SMGIz4 zUcAVz_W#GnW_HYt(Fb2U*mCCe-DB71&jr7}l>OuSPPfll#y-tD(yq@h z#|K~Y=UL|UJ(Y2Neny__yTU$a8NZIx?E1R+9i|Vyw!(7e^}S`+=NI$!+ra*DeSRPK zGQI4df804NJF9n>@VWojzvln$*W_|vPO(2SWgQ<}?kOw$b3Xb`&2DAYZ`VH_w||-I z_ff|8>)Sro&vuX8@_ZZ7$4tAv!33M!mQS85{^cv|axYow+fUyH`SrE6e}0=hH|*1_ zMbophe4EAx*JmVKU2e6l-{)M&CYMY9`I5yw=k46Nb7%Wyh5iG3^&Z%JfPLPpS8>LF z`}gnLx%0rj1MQbo{9|Il;pJ5o;jin2E6%pF=3K8gGe<@#5w;0kvo^7?dq(;SJuXhvv&IHo!HE_y;iQxDy~~wIHYh*yfA#8H)K+I z_$)re=a+A-`~BZ_4}R5lcx-fhw|He@l;wxB+IAd%?n$eb>xkp-+lbu&)F9|t0iQAGsk|$Xi>uBFZPW8tArcO>g z@tl1nR_~Xp-DF}^B_FcKBquNNw7pv7FOC8S9aA!C#gGFBNODBS;`36M;RgeDhDBzu{HMi7wqLKb_+u0 z+IA{FJLz&<$o#|_`(h+yKP@UD3lt?}p`wH=Qk0OziW0KFqJ$ivC?N+bO2|Qq60$@Q zAqOiXlO@zatn$Az4g zXm4MPgq*EKCFC4M2{~6$Le5i^kne_`ixnm05=DfpP)5k5$_Tkk z86lS|BjgHYgj}hNkgJpta_S$_RN%86i(A zBjg!nggmQ^kmr;U^1L!aUQkBJi^>RjNf{w8D{0kni4N3goAjIF2kH4FAIlc|~FfrB+>>?o_X;BIJSW!Yg zQIwER6(!^|MG5&_Q9`~@l#nkKCFCnb3He$PA>Sw?DqVA-^aieH)UMopd_(lML~AcH#m%STFLUnMAgh-paD=_U4ke zv~0WON%9t!ZMQs+yt!rDEzc)!X4!Vj3&@*Vw%zg+c@xXFTV6=s*s|@G7m+(zw%zhJ z3tPnvDcXBs>)4K>ofo!}?I||&!q&0_MO!ayH8-NzzzbW? zjudUYuodk@QRIcK>Bba=R`?OlCKM?zY)v<%DDcA8bTf*4FKkUWr^xfd)^rPsq!+fP zTTrm!Enj1G0Sp~$hqk9D@C$o9h4vOq#Go@6Q7nJh)U z$Wl~HmZIKdDe6N;QC|ua^`k&he+m>0pg_?;3KR{ZK+#|d6zxKRq9GJ08cKnpT`5pB zi~>c&DNs~Gfua!_l3msFvlWsE#Z}yOX7;o-9QTWGQMSOHmV9ipG$oXe?QZ#*tAp zo&rS^C{VNq1&a2hK+#?lDB7C>Ma>i_nn;17NfaoWOo5^)6eyZXfud;?D4I@zq8St@ znn{78SrjPRhXO_WQlMxy1&ZcSplB{dP*jy2t1=*|J1oYlrRXQ$7R}2}x-VC>Fgr2F zPC-YC7O}h(EhbCR{$wdSfGkA^lBMV%vJ@>LOVPn(DLRBKMTe46bQlGS4yQoT5fmso zk^)6XQJ`ok1&WTQK+!S^6dgl>qGKsgbQ}eWj;BD;ataikK!KtYDNuA01&U6lK+!1_ zC_0q_MW<1q=yVDcok0;4?Ux-p-GHPz+L3mAffO}F$647)_vMPt%}(5IZzx8J&SQBg zI-e{>7m%gsLb4QHM3$n9$x?I)S&CMWrRY+!6kSF}(d85opCTx_ zKRdRiy+5D&!w=jakfJO7743uUr2BG3pJXS7+0V2_+oDfdUWz^=OVQ_KDf)seMPHJo z=qs`meNC34Z^%;gEm?}bBcteh3Kac7fubKNP_&u?MQbQf^b-Y&ex^XtFBB;Hl>$Y- zQK0B|3KXrSK+zu*DEgBEMSoGC=x+)X{X>DGe<@J3jsitlIq9SPaEz8sfubCWpy;FQ z*i-|OI?CSPjDIXe{$t|tSWeP?xuRrFV%b(wl*jT?luwqT0cQQ=n)I z3KVTgfugM_P}G?MMO#y#Xd4O?ZA*coE)*!*j)HB`_7o`Efg&hM$Aqy&7wfjJ`^b0mjXqzDNr!!KRGSm)Z$MK1b7%27DJt?;v;{dy_vMQA&q<8kUWyK2c_})O zEJX*ArDzFRiVh}A(II3hI+QF$hmob|aIzE~K}OM$6ev210!2$HP;@i}ik4BJ=oktV z9ZP|t<0w#cJOzrDQ=sSs3KX44fufTrP;@c{icX1%(bHrpdWMXmXDLwh90iJ=r$EsQ6exO;0!1%Tpy*`^6um-$qE{(U^cn?2|5Q=n)K1&V&6K+(?>DEfs0MZZ#@=r;-!{Z4_RwG=4&g91f=QlRKB3KacKfuesX zQ1mYaiq=t}$bJs_0(%(k9d$cZssXgdlNZBK!s9Vk%Ll>$ZGC{VN`MNpI%i=AmeQvR1Y;`y;~q<@-ki*|}7-Ipuc zIhMGySc-bFyc89arKmSqiu#bHs4rQH`jMrmKUs1i4-V0i2_9@ zQ=sS+3KX46fuhqWP;@#4iq4=w(U}w|I*S5DXH%f)910YjOM#;ED1xE`VzKE4B=wiW zIZ%pn{T1!}SkisDqKjjRV+TsnB`hyRE67rGDOrjxBTLccWGT9WEJat6rRXZM6kSc0 zqHD+~x|RY(*HNJ8dI}WXK!KtgDNuA11&VH_K+!D}D7uvbMYmC)=ynPe-9dq(J1J0f z7X^y$ra;j>6ezlv0!8;xpy+-I6g@zJq6aBZ^bkc*bYU!Zg8@l>7|=q(Bqy-k6lcPLQwE(MC-qd?L7 z6e#+D0!1HEpy(qC6n#vAqE9GL^eIJ9^k^*hlL1Ms@Sk;DDMi2d%iCwMr2BG3U&Rvb zhf2}cEH6dhkfrEbvJ`zsmZI;;QuG5^ihd+Z(Q2|3tszU%Ph=GROo5_bC{Xk(1&V&7 zK+*3MC|XN_qCY55^d|+1{-Qw9-xMhNhXO_aQlMxZ1&ZwFyTf5Sin1wCltY1{7zK*r z6evnipeUCDMM(-2->1qeYv8dcw+o8DQd&=QnUeC zirSK;XhX6TwIfSWd$JUDAWP9kWGU)MmZDB%6m3j_qD?4Jv?&FOHlsk%<`gK}f&xWb zQlMxn3KVswK+)C|DB6YsMcY!Ks0#&(wxdAN_7o`EfdWNcDNxjn0!2GgplBxw6m_RS zQ4flsC>4(#WQfub4;6xC9osEz_fyHlX3o+2pf6^}h`KvGLB z#*3xM{|s-uA)a(!u4rsL@p-8fjbnK!8c&v@31lhSgDgdRlBH-bvJ~x2mZD~|6ip;c z(Ihg8CR3nj3I&R$QlMxW1&XFqplAjKie^%vXch&E_Mt%0z7!~$O@X306eyZYfuea7 zD4I`!qWvgPw15Id3n@^vhyq26DNwXO1&R)!2#T8Gv4S#Fw8qamj*+6d(E(dL>Aqai zA@Rgc6;gC4%S+K=WGOnFEJa6ihoQlRKK3KShr zfuiLUC^~@xMJH0A=p+gholJqEQz%e$Dg}y8qd?K=6ev1_0!3$1py(_L6rD|hqH`!v zbS?#o&Z9ul`4lL+fC5DqQUpay;;}jdl6u0=Ivy-V*ZPl%Tog~bFIRMFJh9&>DY}g1 zrRZ|96kS1tBWGQ-{EJZJnrRYVn6um@7(aRJldW8Z-uTr4sH3}5HPJyB~C{Xk!1&ZFH zK+)S2D0+tiMekCe=sgM)y-$In4=7OdAq9#)qCnBd6e#+H0!5!vpy)FS6n##CqAw_d zqQ~R0_Y6pCw7-ZwAw|>utmBvQr2BG3-^LUFR7ufyEH6dhlcnefvK0MDmZH^UDOy98 zqMyi8^fOtCej!WIuVfVcMuDQ=DNwYQ0!4pNpy*Eu6#YekqQ5Cn^bZA!{-r?CItmnJ zC3M)1qHGEjLDARo*f!OssLcP6 z!#7fNyT76pCX(*U6}3$yN^7NPLzb7Kc4R4PPnMz%WGUK+EJYp3Qq+koMH`c)XcMv& zZAwPbW)vveoB~B#P@rf_3KVTcfuhb7DB79=McYuIXj=*tb)i7fb`&Vuo&rTXP@t$Q z1&X>+plC-56zxQTqV5zZ>Op~`o)jqBnF2+X%3yzq=ImXL%_aK$fC`WGNa%mZHIADcXfBMMKC^G?XkwyOO177#T&wDNs~G zfua!OfucGJ z6zxudqIwDxHBg|akpe|c6hTp+MC>L5lKRrOMSZ1cs&9+NB$DpS6-`JaUTlz}Jy>3f z_9RQuUSuiSn=D1mWGR|RmZC{yDVj`{qA6r4no35|Gzt_=r$EsR3KY$xK+!A;6zxNS zqJ1e)G@AlNb0|Te+m>GK!KtIDNu9} z1&WqX1V!T#v0n^GYQFCZjYpC1BpsYcx-VCBcp|aU7%4h}<)!FIvJ@RfmZGI(DLR@g zMa#%ibPQRFjwMUcabzhvo{Xa96ev1@0!1fMpy(tD6rD_gqEjePbSedkPNP84=@ckB zg91foQlRK83KX49fueILP;@Q@iq4}z(fJf8x_|;j7gC_;A_^2;Oo5_HD1xFx6S2Vt zBsI#cyhUKN`S+W#8N0y@J$x`$JS&CjHOVLYYDSDYKMX!*h=v6X` zUZX(K>l7$@g91fwQlRK93KYFffueUPQ1mVZir%9@(fbrA`hWsOA5x&`BMKCKOo5_L zC{Xk%1&ThSK+)$EDEfi|MPE{&=qm~oeN7P*txCk6G$5%qzAbu6idH+RZxTuO<%)ht zB);5Jihg8yDOydIqBUeG`iU$>Ka-{C7qS%nN|vJE$Wrt>S&G(@QS=7|ivFZP(O(oO z`kMkp|4^XlUkVhhqd-wst`6H#lud!6910Z0C{PrqKv9AMMY$9xN>ZRGj{-&c6eud7 zKv9YUMTHb7DxyG98;YRlyF{#TFH_|2yT-qlqHBCtdxPAh`*KC?a}zz9rKkhTOVLJT zDe6d;qE2Kf+L$awn~J4SAV2Kyo11iBu4rIxV&Nny8pQHaG?*+!yO5=52w94T zlBH-@vJ?#?OVMz$6qS&rXapHWr4%SCqd-wP1&S&tP&ASPMWZNCR7ruN-6&8rngT^t z6ey~uKv4|^ifSoPR7ZiL-6>F1Pl2Ka3KTU`ps0xgMPn#XG?oHI<0yin{<*Pp4M^%F ze-RrXMK}4|A>(tC?#mVJm7BPCiWKe5@>0}HmZFJdDVju_1<$rxXqLSG2=& zlkUqE9hI9{H%*F`vb+=>O_ri%WGOm^EJeqXrRX@a6dg~NqUB^MI)N-jCz4Tg5(SD* zra;jt6ev2C0!61$py+f86rDkVqBAK_bQT4Q&Za=oITR>5mjXrSQK0C23KU&Hfuaj3 zP;?OmiY}%=(IpfpT0w!LODRxv8AVWZL~g9hbW`+|Z;OtUBLCkk$1l%Kx-VCBb#9`3 zrW9Sn@=|myS&FVBOVRaYDY}6yMK_YA=q9oh-AtCETgXy$D;Y(%QK0B{3KZQzfucJp zP;?gsiteUB(LEF>x|ae)_feqeehL&lK!KtMDNytf1&SV~K+z)XA~&^B3F zI?FddtEK1y-@9&?Ou8>u)G?XpG*5~;vAh&*OqQZe$WpW^S&B9zOVQ?JDcXW8MO%`k zXe+W5bta=|YYG%?LxG}gDNxjf0!7PCU09Vt+>69tO8Q=q5^ z1&Vr7plD|b6!oG&Q85LIdQ+gN4+V<)QlO|G1&aDp1VtT^u^|Q|^{@Z(&_>B{q`!k7 z=?_RI-IpucC7IZ3KPei*@=`REEJeGLrDzygiiVS=sDvy(UnoVB zSYC=Ilci`1S&F8TrDz&iil&pLXa-q|W|F077Fmk+A){zt3KY$zK+zlu6wReT(L4$i z&8I-oeiSHLK!Ku#6ewCmfuh9}DB7O_MF&uz=s*e-9YlemB@`$+m;yzIP@w2g3KShi zfuh4HP;>-EP_%b4_LKohZRv+)%~JH0{}A?($)x*oMaz(G?UZx{@L& zTAGZt+20ghYB7Ga6us=b+E*o$?#mTjmrU$@pcGxt@=|mIS&D8XOVLeaDY}^~MYoWp z=vJ~6-A0z8+sRUN2N^|oQlRKA3KZQqJPLz^e-7j>nKo^ zm8ZjY6lGJOD2D>~q`8tOlo_Ole_JE@KGlJ3hDZIYMBK3s}6 zWqB#uj4VZ)lci`2vJ`DemZGi5Qq-9&MO%}lXdAK=ZA(T`7YY<@M}ea4DNwWn1&X>- zpr{)Kigu(x(M}X7>P~^89uz3*Nr9rBDNxjl0!76XDC$jtqCONT>Pvy5eiSI`Pl2KV z6et=F2nrM(Nr9rHC{VPNA}E@a7rV`Xq#pO5FPbbx zulcs<=)9!+az)4GC0<=7MaQ$e6fGx9(FtTJI*}|zCy}M-WU>^ULYAUa$x?J0S&B|4 zqv#9@6rD+dqO&MabT$Qw&Y?ijxfCcmj{-&KQ=sSq3KU&Pfuf5jP;@Z`iY}o*(FzI_ zT}pwX%P3HEIR%QYpg_@;6ezli0!3F-py(Qkpy-&q*jfXUx+&Y>94kd1I;m^(lJ3hD z-I$ly<=x#EK?x8@@y%Z?A zj{-&aQ=sSp3KTs^fue^fQ1mbbiXNdr(W4Y7T1kPT$0$(rI0cHHpg_@+6ewCnfug4< zQ1mnfik_iB(X$jNdX54`&r<|N*XPA{H6W=Pi}4$zXq_MSzmS)7U#{qtyhQVIDSDOV zrRX)X6unNCqBqD=^d?z~-XcrU+hi$vhb%?!lBMW9GK$`(K+y*jDEg2BMITY1=wk{L zeL{hvPbpCJ83l?yr$Esc6e#+V0!3d@py+D~6n#U1qHifs^c@9?zNbLZ4-_c+kpe}l zDNwYA0!2Sj1Vu09#f~;0c4%*KUY4R;{Y3W9c}e%>ihj>aTzR4ttz~&B`hzS*f0Cu> zFR~QqIMK0YEOZp4iqTbhyq0&DNxjjA}IPb zFZPT9N$u@B)W1p5uf8qXI6vvWT+!zFiEmGqqAgfninb(6(N<(B>P(iRt;tff4Oxn| zB}-8kvJ`DcmZI&+DB6JnMO`US)Qti~J5r!%CkhmGr$A8;3KaFEK+(<=DC$LlqGAdZ z^`<~k9|{!pr9e?X3KaFHK+ymS6b+<6(I5&G4W>ZRE)*ylLJ<^gnjdR>iYXf6JJg%y zha>&@9){*8-IpsW$xjrYCPgDyUW!V|QdCBkqH?knRgk4_M|}3UKA+Wn*v466eyZVfucziLD8`M*cbzns_<>ma4CA-_pT@BC*7ATnx3CH z;0!66!SYfxlPpEE$WpWqS&H^0OVMny6wM(^(Oj|=%_B?Ed@_pmqd?ID3KT7*K+z%! z6fLGe(f$-DI)DO22U4KuAPN*Mp+M2W6ev1`0!4>Xpy)6P6dg{1q9Z6!bR-3ej-o)( zQVJ9uO@X3i6ev1|A}E@gAG^?iq~7$ij?<**CI4ZgWAl^l%N3oFpLp;rDLRqmrRXHG z6rD_#qEpCHbShbjP9sav>0~K7gDgd7lBMV@GK$WoK+!oAC_0w{MdwkV=zIzkT|j}N z3n@@^5e14ara;jp6ewCjfuc((P;?muiY})>(G?UZx{?A#S5ctoY6=uxLxG}eDNuAB z1&Xex2#Su+k9}f5Qsoxo%cW?fANJpnpLAcY=$8CM>|80jmF1=AHnJ4mPL`rO$WnAC zS&Hr=OVQnADY}O&MfZ}W=sq%v?x#S}0~9EFkOD;yQK0By3KTs;fuct#P_&W)MUPRS z=y3`ZJwbt@Cn-?0iULJXQK0B)3KTs1qIbzs^d4D? z-X}}Z2V^Pwkc^^_C{Xk<1&ThQK+&fZDEf>7MW0ik=nD!IeMy0$uP9LTH3f>kp+M2M z6e#+R0!80bpy&q*6#YnnqSX{AT0?=NpD0lDGX;u%p+M2E6hYCe`LVeMB(;~rc}Vu3KVTffueR4C~8lE zq7D=&+K2*09Vt-Mi2_9%Q=n)Q3KVTh5frV>kKJKFQa|~A(H~MY+{0!CN%!T7wkk-x zez6pFW_c;vnk+@zkfmr_vJ`b8OVM^@DcYVaMLUqCs4H2Dx{*<|BL#|fqCio13KaFA zKv7Q$6zxobqFxjzDyBeDZweIkp+Hez3KaFDKv91R6b+z2(Lf3m4WdBNUfudb0P&AApDB7YR_NM_!t?l?Jq6riz+Jgc`ds3iiFA5axO@X3j3KUJGK+z-$6iuc;(G&_4O{EBm zMij(`8<3R$rJ{JL6kY3KT0zo%xuRJGiAk4B(LO9MMf;MaXf|1j=8&amE?J7^k)>!p zS&H@}OVI+d6fGp9Xb}a97E_>Te+m>GK!KtIDNu9}1&WqXpy*%<6dgi=qC+WAbQlGS z4yQoT5fmsok^)6XQJ`ok1&WTQK+!S^6dgl>qGKsgbQ}eWj;9EUW)#GZF(9b}eDgC? zik|kJq~!%k_vMOCE=XK`r4*gQ@=|mvS&B|0OVR0MDLR8JMQ4(w=q$1nolTaabI4M3 zE*VAVQK0C23KU&Hfuaj3P;?OmiY}%=(IpfpT0w!LODRxv83l?ir$Esa6ezlq0!3F* zpy+A}6kS7sqH8HobR7kXuBSlJ4HPK4kpe|GQ3ORN7Q~)2AgR6lhh$HZqRxJ#e{(_7 zeYv9B3liU7Ek$>*ycFF@mZH1JQgk<2itZsx(Y<6Tx{oYH_midQ0kRZ5NJh~^6exO_ z0!5Edpy*Kw6s@E{(PI=SdYl49Pf(!fNeUFLqCnA86exO{0!7bIpy*i&6g@|QqUR}4 z^a2HnUZg^t2OwpeX=Qb&N*GaurkaS_ z^jAUbVgr(T)we}|OVQc(wfL5)r2BG3+oTc?-y}ubvb+>^AxqJAWGUL7EJZtzrKl@e zin@`dXh*UX?L?NM?qn48pg>Vi3KZ>3fudd%C@Q8vQEv(q^`SsfUkViUqd-xA3KR{X zK+!-76b+(4(O?P`?LvW~ArvSYN`azXDNrH?kCsCQDHjS&FL3QdC2hqFS;P)sdxW zcQT6VDNxivfucqV6g5$xXbc64#!{eY90iKTQ=n)91&a2dK+&EQDB6nxMSD}AsF?yq z6Dd$Mi2_BFDNrAqai z>{Md(?NT&{<)vsYS&HV7rD#4`iuNN*(E_p*EhJ0PBC-@MCQH%&WE34hfuaK`P;?Ll zik48I=wJ#I9YTSkLn%;n7zK(Br$EsW6ev290!2qrplB%tijJm0(J~4Y9YcYlV<}K{ z90iJwr$Eti3KX3{fua*Bf}(v=vH1ohwVnSk$i7mv#E^NeIPFd;I-TXE z=nS$Hok^CWv&d3(Hd%_!AxqJ@WGOn2EJf#&rRV}OiY}x;(M1#}x|jk*mr$T+1qF&O zr9jbT6ezl!0!3F)py)~p6kSDuqN^!TbPWZHuBAZHbrdMNo&rTTP@w2W3KZQ$fufr! zP;?6gif*L{icU$z?lK^$rM@jXRf^j9E81_Q#MOHmG4ieh9bij$=%L6)LivJ@rBQj|xQqI|Lx z6_8PsqCin01&WF&P}GJ3MH^6{s4WGGHl#pNI|>xFr$A8$3KVTbfufESDC$IkqKzp~ zvfudb0P&AAJMZ+mj zR6>EG5fmsYr9e>`1&Yckf}(8;V=owx)Nj5m>QWev^hXz3s3=UjFITi%VdBR}q-ZqD zOHmbBimJ&{R6~}cTCx#NvJ};mrKo`{MU7+>HBq2w3rm9(KmkSs-u z$WpYJEJgd1rRV^%6dg#GqJzjNT0()MgDFsS2nC7`r9jbP6ev2J0!2qqpy)^n6dgr@ zqNNllI+_AS%P3HE3$XicX|J(Mc32I++4Rr%(h%a|&Y< z3`nZccc|w|(R2@|7AD=7D>}0PnMz!$WnA6 zS&A+qOVPz-6kS4rq7@VO@X3+C{Xk-MNsr!VXV6WNj>84>Ax>UYkga^t}yAoTv4njQT?10#fw@W z=_kliluMSPBw32`$WoL~mZAc(6s5>gR7jShA~K5FP@rf73KX@aK+%R2C~8N6qV^Oh z>Og^_jVMsmkpe}XC{VO91&TJIK+&cYDB6qyMVnKgXbTDyZApQmtte2`nF2*yQ=n)Y z3KVTi5fo(?#TFQl)LcJBlv5Or(c0VB;$4c8?#mT*ElQm6f)sUQd2Ne!BumjwWGU)S zmZBbHDe6gra;jy z6et=(fuf-lDB6_*MZ+jiG@JrOB@`$cL4l%D3KW%5ps1VzMHLh%8cBhoQ4~SZ_C>LK z3`nY*!`VTKvi;?)vMA}kTv2sV;_a8DsD|aGsFo~6bz~{poh(K5WGQMOOHm_Pikiq$ zG=?liW63BQM}ea86eyZNfucPqP_!oniuR&F(cTm&YNkNZL<$s5qCnAP3KUJDK+#kR z6iuT*(R2zF&7eThObQguqCn9;6e!x40!6baP&9`kC>mW9``3V^%6(f@B}IOkC_c9+ z>Aqaif}+G$uS(HEmY1SMWGPxqmZJU1Qgi@WiVh@8(LrP>T0)khgUM2K2pL6(QlRKC z3KShqfubWQP;?{(ijJZ{(NYQ&9Zi9vWfUknh5|*$QlRKK3KShrfuiLUC^~@xMJH0A z=p+gholJqEQz%e$Dg}y8qd?K=6hYDaqF9*$Nj>N9>F*~+mA)-HqbTXVT+um2iD|D( z(YY)yMdy*F=zOviT|kzi3&~P+5m|~ZCQH#JWGPxfmZD3^D7uUSMVC{c=n4uHT}gqW zt0+)(H3f>Up+M2K6ezlm0!7zTpy&n)6x~RHqMImCbTb8tZlOTYtrRG_jRHltQ=sS$ z3KZQ*fug%8P;@s%P;^#NY`FnRJ>zE`&z7R)zIT03QPO?6q6dl+*S{%653;-zJw%qG zhsjd(2w93AB}>stvJ^c=mZHbWQuG8_ik>8+XcYyDo}xg}(-bIrh5|*;QlRKL3KTt0 zfua{EQ1l`Nie92X(aRJldW8Z-uTr4sH3}5HPJyB~C{Xk!1&ZFHK+)S2D0+tiMekCe z=sk*{=)R)ZO9mwMp>KZfm!i%69gz2nlJ3hDeO#1S^R^Uy!tzq|DOrj>BTLceWGVWB zEJa_ErRXcN6n#yWqHoAj^eq`h-%+6GdkPf&K!KtkDNwYU0!3>mQ1lZ8ihia*(JvGz z`jrAjzfqv*cM24(r9jai6e#+W0!4pOpy+Q36#YYiqJJq+w2lHrS#5M+j-qUepy@n;U~7|fU#@7UHi<(&kfQD^FGW4bQq+?yMLUzFs25p^ipf&cn=D0r$WqjoEJgju zDC$pvq5%{r8c2bnK@=z&Oo5_ZC{Q$n0!2e9P_!!riiT03XgCFmN+?h?f&xXQ6eudA zKv6jbiYh2jG?D^EqbN{RNr9r>C{Q$-A}H$CCU%(tNiFf8b=*;k-gQz{ZIbTG71gy# zJob?k?auO2R8N+o2C@`2lBKALEJb6;QZ$w4 zfud##6iuW+(Ig5KO{PH66bckgr9ja%3KUJJK+y~e6wRbS(JTrS?L&d0eJM~hn*v31 zC{Q$)0!8yEP&A(+D5_}_`^tc%zV$z!Rx3pt`QG(@ZIbTG6)kR)$p2J|_Gfu1I)E%i z2a=`eAhHxKAxqK0WGOm?EJcTsrRXs7{~_+a!=tL-{oSvXH7jdDAejjzG$HgNY4j?+ z_bQ?iLJ|l_O#%Xf^dcffilC?!qaupEgCbT$5kyo(Kvb0Td}cj&lJDMUpY!`; zU)PW8!Zq(ZnaO14m1NRT70qL#Xg&c&3kWD$NI=md0*V$BP_%@AqNM~BEhC_4IRQmC z5m2;(fTEiTC|XHC(JcfNtsT|0fTH^dD7v43q6Y{ldXRvkhX^Qon1G^32q=1#fTG6;DB49p(c=UZ zJwZUxlLQp)CZOmk0*am{py(L_ik>B)=s5z4o+ku~HpM%I0wk`n`Kse)RW#4MFM1)~ zGro+Xm*d?H$5qi@&aaAIVXLBjY*q9sTNS;=Rz>^Ss_1pLDtd#hir!?aqPN&6dYgcv zcL*qYmw=-82q=1=fT9lwDEg3qqK^nD`j~*C0|XQuB%tUM0*XE*py&_*MV}E+beMpm z&j~2{f`Fng2`KuCfTFJnDEfvFD0(s8d0v3Tl`{{8UQ$Je&5zF>iT8{zqv-p1_lqA@ z(J{`iihf|LqT_5;bb_sleq^hnlWbM=6I&IXVymK`*{bLlHi~{Fpy)IKMZXbHbcTSU z-w7x>OF+>%0*cNPQ1k}@MHdJt`jdd7zX&M$n}DK=1Qh*4K+(Sh6kQ^q$V$*p+fif_ zP!vNzkwZXHh!7|`8t+&qMbT~p=Q~w2*^qJ*JmbqKDwW{YJf(_CbADA6$5usU*s7>3 zTNTB#RZ#+46@}TVD8g1niELF=j*X)71Qb;upr|4NMM(q{RU)9MG66+Z2q>ybKv6XU ziY_Cds5${fH3%q5CZMP$0Y$Y4D5_0BQ5^z`>Jm^?kAR~31QazOpr|1sP~;^z-33V8 zF7tEOenRk>{whPNQG#cD8AYiH?zmr6Q5xr0Md@r+l)+X-P1vfaDO(jaW2>U(Y*o~P zt%_Q*RZ%N8idqv;)P{hfwgeQlBcP}~0Yz63P}G5dqK*UL$s$pjQl zA)sg~0Y%dYD9R_GsDKbC8kFFCEI{J&%-605tD>6beNkb8XM7n&GZWn3�nVoL?2q zW~-tb*s5p_TNTY^tD+m(s%Rct70qX>q6KVKw2+OWMFbQrCZK2u0Yys*C|X89(Q*Qc zZX%#)1p!4j6Hv60fTCLnC|X58(P{#U)(}v%mVlyL2`E}eK+$>viZ&2Xw2^?K+XyJy zLik>n*__#U2Gro+XI}_a2=Ty;MoL?2)%~nNQ*{Wz8TNT~I zRz=&{s%QsW72V5LMLXH5=sq@z?kAw=0RoC1B%tUa0*W3cpy&|-iXJ7P=rIC{b`enY zH~~dZ5K#0a0Y$qBD0+&3qNfQcdWL|aX9*~Jj)0=)2`GAjfTBGF6un3Y6y1^Fj1nMm z&CL6vEvl%s`H1#Xf@gdgMf(!md4H&)S2@2bdX24$_On&d>ugo@23r-q$yP;gu~pIA zY*q9QTNS;_M$vl&6unPC(FX(+eMmsjM+6joOhC~A0*Ve2Q1l4_MV}H-bcleW&j=_w zOhD1+1QdNiK+%^36n#ZN(bohNeM3Oe5dw<7C7|diAyBk8!Py}|;@X=}%UHWfUDxaQFYIicWBTRrDiU6`f?OqMz8R=oDKO{mfQHzpz!&uWVIxnyrd{W25K{ z0Y$$PP;{1nqH_ckohP8^4+4rV5K#0d0Y!fiQ1mweMHdMu`iFp`e+ekML_m=h)=%3} zWD`&nLqL&3Kv9T*BA0-oSOSVXLZIkaf^$-U#0@bY#C}jkspfr=ANGtdqo_>Sjk~Cd z%5r{H6wg*g32apqW~-tITNNd;RZ%&%Dk{%bMHSeps3IFhNdy#CBA}=;0Yy~^D5^?8 zQ8faJE+e3*IsrvB2q;P>pr|GRMYRYhs!c#q9RiB#5>Ql+fTH>Y6g42As38GGjR+{Z zoPeUngg{a0u#+x8;%+wIM~e#wpXtABKD?!bJ>$zL$_TrI{#8XyIKL`t%2q|q*s7>G zTNSlntD=@{Rn&^DidwT(Q5&`@YRg7ZI|7Q@6Hs&o0Yx1MDC$T+Q6~b5IulUTg@B^2 z1Qc~6pr|_mMLh^8>PbLRF9M2s6HwHLfTF$x6!jyZs6PQk0|+P@NI=mbLZB!u?931# zaUt`*C|wmjXvW~MXM7n&!^7@vmbrj*D|992S4AV(s^}`VDjLaFMOU*`(KT#UbS+yI zjbf{!OtvZ-%|=lc0Yzg7D9R?FD2ITeTmp*55>PabfTBDCipCRAG=YGk>j)^CNI=mf z0*WRRP&9>rqNxNFO(UQvpMatQ0*VR=D4I?{(F{VMXlU5kBS7M^&9}~msiLyxGyUts zp7CWA-4J%aicv*#IKL{I%T`4Rz(Zgs%Rlw6)j?`qQz`gw1kbKr34f$ zBcNzG0Yx_vP_%-8qMHdQT1i0BEd&&;BA{qB0Yz&FC|XNE(X9j&ts|glJpn}<2q@Y} zK+$ak6m24)Xfpvtw-Zow2O&^2E9}HLqG+c1+VyNzbhmk5v?c5rUq;c^uv=UHIf&@{ zqHUaC72U&DMcdh`Xa`#r-OE-*JK3t}KDH{lpRI}>V5_1B*(iF5fTD*9D0+l|qDKiR zdW?XgT?7<8PC(HU1Qb02%=xG9qo*|&KXi!|r%b6}`^+RnZ%4RrDrX z6}`n)MQ^iJ(K~Ea^e$T!y~kEX@3U3W2W%95NI=m?1QdNtK+ypLiVhM`^a%k)pAt}X zh=8Kc2q-#CK+)#}6n#NJ(U$}ieMLag*8~)OLqO3H0*byRpy((8Mc)xn^gRJZ#|VL< zSHsRK0TTD4`LygcRkYnay8a>T8DB=x$*}uaDOL0n=T}9i*sADfwkrCCt%`nStD@6v zRrDKM6`f(LqTku7=qwvW=Lje|Pe9Qh1QcB$py*EmivA*?=x+jwE)r1m4*^C05>RxB zfFdiRpSGjOCZH&WfFg&0q7VT^E&)Zc1QdA$6!`=cl_H?1G$BxQBJ3O#AaPSC6s;B~66;))bq9nE|s>D`BmDwn& zLO@Yf0*a~;P;?mqMb!x?szE?eG66+32`H*XKv8W1is}$hRF{CFdIS{JC!nYS0Ywc7 zC~8DN(d7gbH71}ag@B?|0*cZIfugbzr%D-7^s)J>V|*m|On;MkUz8s4j4z|8S;TD{ zuZo&;epS?ht%_Q*RZ%OpDr(JEMQzxss4ZI+wPUNI_H0#j1sg>j2q@}EKv5?GiaHZe z)P;bet^^cyBcP}|0YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVAOea8 z6HqjSfTE##Mvo8 z;+{3{i$8CXGc8a%P6`r;=Ylniso^CRWzTiiWaa{(L%N=TEtdGi`lAZ30oB{ zWvilPY*n%*Rnh%yRrCN`6+OsSMGvu6(Zg(2^avY8j}lPy z7y(7Q2q=1-fTAY|D0-5BqTK`(Jw-s#(*zVfLqO591Qb0-K+*FA6um$|(H;VdUL>IC zB?5|GCZK390Y$G6P_&PLqE`ulqHPhUi2#ZF)qK_Q9#yo}yf1n!;u&8?(VG!>NRldg zi}S0Zx7n)b9kwcZm#vE4W2>U~*{bLRwkrCNt%^QktD=wDC^|qu(Ln-=J|Up!Qv!+( z5m59Q0Y!%iDEgd$qAv(2`jUX6uLvmmnt-Bj2q-#2K+(4Z6dfg?=sN<6z9*pQ7y(5; z5KwfSfT9zGK+)?FXQlv&^UW_0y`hT!lBb1!jCjVEQS@`f-CS7}{lfWG(XVV(begS- zeq*bmGi+7#J6jcOONK#@m4kxxKTDFTX06HpXKKv5Y2ipmlKML$KH zmjp=MC+2<8DOFU{d_;>+^o%c~C^6Cfrm89`$N5!JdA2I5z*a>S*{Udst%@qKRZ(TO zDyqU(MOE3Vs2UqZml04@oq(bm1QaC`P*jtEqFMwL)h3{*4gp1V2`H*ZKv8`HiW(45 z)R2IpMg$aHPC!v(0*X=yC`u)uD2;%kbOMSp2qus;C`X6}4xpqAS>{r~_LSb!4lePHYr) zCZMPb0YzO2DC$N)QFj80dJs_5lYpXL1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ z6b&YzXb1sCLkTDvMnKVU0*bCA1d5s`I=ux*+~o#N3sqFnye}G&=ow!|(KU(gb@G2C zj(#8QTF$SEMzK{ z0Y&QxDB3_k(MAG_ZX=**69Gk=2`IXqfTBAHDB40m(VYYo-9#Qh*MG+!0{YQ{Z@p7CWRSTUj6rE1o*t?(oAEn6%6fdLo(O}7eRC;Vh3%W4q*vx;Rk4tKcBveLs# zYFJjY@H;gvt5rBs$FkamudHWT9m97vu&l1(?;2TF&v3&O%jz4Rl4e;0!%t;c*3j_Z zO)YCgxKj(ux+c7=m1T_%zt_gHa>C`>TUK89st%SlF?@F?%bFTK*2S_4!JgT;DZFi@Wo-!` zzs9n*hEp;vYe%>s%d+kdKbLJ;4~H-1TGp;`w>-<*9lm*jWj!1IXrg892`5dlti9oD zr&-o(;q3*M^=A0T>6Z0wI8FYS7$1hG&$g_C;TPsu)@NaRo@IR*?ytf{kb#nXLkry|}9biYCO>z&| zkzTjUU0_F6Z;|`Jj(l>L+zEE1>NdF->`2yjxf|@refP@!U`NdV&AyHuG5m+Y$4xTj$sj^Uo9K*%9;a%TBZ- z<{t>1YDdh!@K|U^%s=1F){dB;x!hw%%n!}&wIk-Io?f#f=Eqjvv?J!{4&JpR<{QT!+7a`ezk_zf zeCy^jJ7T`}{-qr;UpzfxN6c5hzPBUh%NHl?i23~UlpQgjK%BNC<`LjoJ7PYBU$7(Q zeegxwN_XhJ)JH@R|Y@^)l5l_EEY{I$3As&8B6*UMX!-L#S1RhB$G`ltL@$Fz>C zWi^z)b>(k`MxM0h@uu~czrE#eMS*JBEuzh;_?}#{-BQOQa|x~D7s)eN6`zwgSG%=7 zrJs4WHae!63vH`orWx&Y47O#o*YUHwAF!{`F~78o4m!q~YtS(mNquFQ*QwGqa$>lg zsB906jr_jymmhDeY!8Z!EL^zm>$#Qf!ETvSsXNcLCNJ9jb$utc z$_sKkn7^*$#9DU5t{Y!2&WW!YKP)L?hm$NTrj8XCcZDR&aw=L*e4DtoajoNem6ID# zpW@4zn_H&DCdl)e6J9wxE-rXZTc%&ua(vDh7gsi}Ok69ul}aW3$8(jI=PGgWaXQ`L zrIpc(lxZ%qtX^dFsl^u=uNSG$l^|zwi?2txtXxg=k|WU*u4N_atE4ZaT&mrnGFPI0 z<%pda+p*GZohzG{Sl%sh^-6$qP%mX`yXJ>jUqN?~qxVQx-ZcK)oXg;Pw( z&dr&gpIcDkY3BLmxm%}A%^yE$eBt;RxmH@r%aIBydZ7J)U5pLx=){+IaFSkaRVn# zFUTC+sYSo${~LGHjI6?3b8A_a-qFo6rl)2b2bnp!W3#4DEX*vNH8r;&HP7&p`zmMr zB0H0*QYzBf|nm7*NB%8z2H>0Ui1YzGg93O z=9IqVSb2@gB&W$MR?c-(V#4x9Hn>}l%ep#RW|#g$n*^8Lm9sQ2dU-8LO^aV{lcJZ~ zrNl+*6>P#8S`*#fwKDl80xXHOW$-*M~;=1Vd%IMCe$O&G}Zbh$0hFqEG^S72~ z%gmH>H*Jy`TtbGtFwW4OOY5YU*17l+N+@jKDi_HRT8jzs_TE8)0#MC^0?&afBqY)jN&WOS>3=(?zHF& zz>^W9{(~zVI5n?ox9FuzFmEH#C#CB}30b{Hor|uUdE<;eQ>Wr9*%bjz^=U;UxDpwy ziY_XnSRG10l2Oc1UK@SU&?rJ6?+2{GndY5rr`&>!Cat>2$FgBlbL9Q%km>qfqgY#p za0_1DbgpDEz>MzPdByIyKjqa6&c_LJ$35DD8(YTW`I_s;?UDUehS>(po zTe$dL7x!QD;_DOGh`!>*95PCHDB+-mT#;g|yyMG&lXw`XQD~Y!vzb^;3kw88$BVn1Wzlz zi0D-^@P^7qetmwUDie3?MS3+i!^ya~($$M2x9!%y3w^2rL(2s}3HZqEF6nQK* zAs=exr4{5&$uBJW=*AssyhRBV-TOr!hvn@idL7I?6!j#xO>m+Fh++U4#RBAwoY#;0 zCqu4m^vv>sI(p>x&k)VQrIxsRi|Lls$EN`)s+za%ZMY zYT8snVczsfW8^q?;*_ky6nWU*UhbA06XZF^PMy&_rC@4GPDTqUS^3#{?d5U&j8-X= zQYXo00+;6$Ouc;U)Z~s)& z2d4mRi4UMrmGX9;A*!PBU^$>IljB_8AP zK(hD&oq6LZ@hRc|)+a(;bH_{{7u;MtQswO4G=yqMMU9<)Swj z-d@Z@)a#1g*YZfT_|anVgT;*Ecf`CA8DY_vUi7fE=<#OJL(39xt;KJ1#SaWYRQ#~8 z2uJYP((2KrOPk~d=Iygn{-oq?lg8xcf z8*}2zl#PDPfiD`EFCcV^_ZP>kvd6vuTD;Y%wS+A5xwvJg$w{|WO25>8oqF}RVk2I^ zQch_f>?f%Q= zQ}5uBeVsz9PR{?=!^ffrbI}i(Maw+23%<5gTCU;^^$TlGnlPNqXEV zcchYA^0A~NG$0l+cncYE;Gv%8)W-rm>OY(&~v)|EUsA{kydh9LV@-a`pQjcqD z1p7`sekwPtdHQ#HtX3!34fQytUa+U=@qW1j%=15`$6p!+`)@rqO9^%-J#Rk9dDlhay{mB2=+8RKG-SP z&*<@Vmtg;+#}?g#-9?XcdItL@J?`rr><{$l_X~CfJ@y|E?5p*-eo(Nt>GAU+!9K3X z>v8acU}x%a)1qMCtH-aG1p6mF)>$6x3_VU*5$x;rxNBvw zU)1CIRl#;v2gi16gJUl}E?gJv)p~q$L$E*5WBjIISJmUt+k>5@$J@6A`#wD$k?#|l z`{!pp*4q~Brh1&XJ=nAK_{6=zep!zf?hCeie{j6w!Qj|OkBc7;_F6r@{b;Zc=`s9x zurJf&@F#`?|MJj59#sy4}<-i9vdA9c1t}@{Uq3P z_4xFmV85!zi}D>&bN`h3JUDj#GB^&<2bv$!M;t8 zAIkS*&GUby$BGw&U0aXW{2T1?db~#-DVXPfOphmGf_+Ypsq!Uw^YpfQER^r!n!P}e z&&#)S&3;3V@-6e|F004x@(o_|^dWj&Dc|Wed$S%tmT&o*{f!)Z^89l!r6X=lAuPpvQ80Y^X>1upWIr`EVUQw$fvNJr366 zNIj0yW2`yKg@<*^A$opZ?o{*mO0KUw%&}tRg;(PFQVV8HD$E*Vr4|(C2gf{4$yWjj ztyJ@=x0O1kpukF%FBYVlnEF3|aWncnIp%XZ`NqK5DRTDc>8vqh@^fbdmk<>Bj$+A~ zm7g_vT&}*1;5q(#nP|QrsFx^L(n`&i?_cH0cP~o3)Uo+lljNB?4epnkRalrme$4bj zx!C{XKk~3n-V%ey&E`zzekl1zZpP@Jn(|-sd`>X`+w+;HnLqXAues0v|DG>hp69>5 z+^N#|W9~=ur?LDkC4W20U-M^RJNfw~IaZXv=6TFt^YVtuU#^3kw06kf9I?nBP7Rb$ z^72N@+BF3*_a@L zH1l#z=jASt)0{_6T23R|N;W6-4^NvbyX58d>|T7kn9umQy!CRL^O%dMEth9*KmPEv zH4;i*-iQ*HS5}_J7Q@OnBxwA_=?H)N@^78WJ^345YUSIRRfXjPAPMgb1 zm%rxEgDJK(yi9P~{MS6q{C!c6JfGFZj{dBSw$Mx$g&u0wr$Glwg=XLp8 z^7>6J@%ozgQCvUyFm5bQl|%H;Ou4)^3^|&YYyOxcZ!2c+mggHNF-cA*%3pJNVfkxb zW{I223W>ko()h#WMI@AbzWH+fg4vE3i<^F;3_ zdOg{5{{<_{lul>Lm3y%NuHLU-*pb|Hbkn>$?TZHooZUO*_bhYS_T?SVY+8_4>w!Mo z`n`T3RP*%Nqx&zMN_T$yx6Af( z56Sg9wdRiA`!5_Bz5RT4x&0Ta?cLN%+Wbv&9Zrpwzemi|OgGoZsx7Z+%*m|c*YeQ? z9nWN?%WKxD=lKoU^W>63w!DsE^V)r^uU*IUHLad!%0=4d?Ym%Q+z|cm3(^1n9sTc( zefC{AW$lw|Kc!D(bd|h~!D~6N%bBB{XAbx*tIPTNrC+^pD!I>@y}jf(b-?Llf56!? zJ-VEU=|8Q1jk?lC%ipc?ca8j=FMp57->C!6*1l4X1I_84=lAw7$F65$%`w_~oT(XY zJcbEJfcxAsXXMX5wPRZ-zmQ60*T~6;EGC=-o zUi!d6{X6y<)X#1$r_FgRx*U^#|ESaXa(18IeR{rnVTU~BNOJSul}DH3{v0T`VMez; z>HR*;+IJxo*;hhFt-OxW`zeOmQy z)vI;%sU2%qk#p|JSU3KQ(8YsR@{1=ftZw@MsxPfiTJQ8;=|%cp{vlOLniO;2cdYH} zZGS8a#SOa@vtz^l8$&Nw22C z>r}#Sn!J^T?AOJvytNhEmAAmwc@6rC+{i4WHS%2azkf#mJ7jcr-U#dBCkN#%tMum5 zn@W$CQ<2hlb}~o1TA%x)$Ev+gjIP?Ns@{qfdcPLEH_WZr@_168q~4W!Rnn)K`{|+a zU&~V}L~q~neJb>>(5s?8)zjPm8+rOK$KM+B$J|Q&PS@D=_FoUIytngv=C&U&@AEyk zU(7t2Ja2UJJui3s_{)#Z-_o_oj{KkM&Yn2$nMcc*pHFKs>#nEHXRdDYBEm$rAy$DT6N!KQVUf68QiYWBUu`eRxca`)vht@NTRr@2Jno ze`5MolCR;&&(yd}<$;7#PCkmn45&Ohn!IUMWchAG6MgTnd=)Yja?MxqV?y3=xgh6L zc~|Q+F4sw(-D#OD|4A=z9@4n-WdtjByL`m-LUZI~s84)3PsU#JvBvvBF3$Gq$;XNq ziE<`yV|jTVZ=YOI*E=8|KVrR*TwBjuDi`m2Yo(X+&dSH3(%uNUggEbzJT5NdU6w3A z=IAw(#|`n`b=Bnqv==Y`4SNx}|HA_v8MOo zWtLUTYb%#l+dC@HS;yNYr|Wu4Ys-T-uZ~=1t`}cNe*W6)CD-9C@3>s&x4jDTu>KwI zDY)#`ZhO zExy+FN6S@NXZuU!wp(xe56R87!S)Zx+GzW`BwBQN1M z$FCei{u+6C zL*;)}BWD;E^1F-C;UWKDxm~Xe`8fh?M9AMMF0TstkI03M4EZbNao^P;e}vp^*M$69 zVrN&#FO(}$-u17S*QkQ)KPXpXrt9~UTWOZ-50|@hw(H*}@k`e~DVO<`>o<@a@@v;m zmW%$z^(V`9IpX?ze$1D=0g?(&14 z|CL;&Pdxu&xg|dJ{C6cD^89{sn|OLFiUoN7bi}N?hg*_kV@06GD zLY)7Ou-%&AUlIk|68z`n%HNaV50I<0J;9HWyJJU!UtKQq-UL5ZE^}vsKTX#1a(;EW zH*YHEmyw$;T;G3L-f$xI{qgeJPEGPB%5|BRl7H_9zIE6HyvT4yKu4dqt4A<1ti*K<-$5|@z2Z6+I5Tnbh2f2 z+u|q44bpv!FF)~a_1NMMmRn-rtNsCb+Mrkcj&c}%(%&g>0a+*gtK@bWbJEWh6WJ&I zsq#AHob>n0mB>Bmcazs)>`A|;T$1$8I3PFr+DtjoQcm1zPRx~SyUv{WSzfdC=EMnky*HQ>o#aK# z%9azOernk&H9`2r zn-j<7_D(P--jrvSpS83~O_Jw{m=m+*?oBi&K9F0?e84W%OG0}E0_~!b>0-=@40#deTaKl!l((XgIU&g9wU865)P-pOqXl^5&!SA8Dm+K6E4b5$=Gx#kuH$`XgOK5JY&fs^@+%%oRub{c< zI`ucu+zj3N3utZ=-TM1yZd2X*>t}8=-TK>SZgbuG%V%y2-TJ#{ZcE+zt7mR2-TIqn zZfo88i)U^d-THfHZd={@YiDjd-TGT+ZhPJOOK0vCy7hO?+zz_+SI*pyy7f2C+)ldn z7tY+yy7l+X+%CHH*Uj9ny7jls+-|z{m(ASny5;_l54m-m0doH*d@g+4y3yaAPPk3p ztlb`7ioD?)A${Bd0wyY?ubx$f^wX(A`s-9719Ym8fjU*lAe|~?uuc^+M5hWFs#Apw z(}|Gbx)E}vZiI}`jgYH!BV?p*gj}r~A=l_e$hEo=GDGIb+lv~GlC=|;#H-3ZCn zjgTDO2+7rrkg>WEGEO%_@^m9)yl#X{(2bDmbO%CuIn(6+PuM8$vE1H)kT&wZ+@0td zIY!7-cbf2t3Yn&7RU!F0RY-wO6;h~Eg-q9}LT2bxA=m3vAv1NVkXbra$ZVYmxj{EV z=IBPqT-^w{Q8z;7=|;$W-3VEr8zBpIBV>_oge=yLkR`eivQ#%hmgz>wa@`2INjE}P z=tjuRx)HKcH$raFjgVEk5wco0Le}UGgiLnU$^D=3xIEHvrvySy8X;>vBgY8Y;I5Mo zw^1P*^{gu7Hk~SDlTH<~S*HrQU8f4UL#GPaqEm(3sZ)jArBj96trHnegxsqeAv<*=9ahST{l*(T$KtbtB|4-3ZyG z8zGPDM#vMo5%Q#NgzVOhkf(G9Le@D?$^DjNPjC!aLO#@ukdJgDQo^|b*hl>bgGc=b*hkKI#tLII#tMVohsynP8IT_PK2D)jgX&oBjl8Bg#4@< zA;0KG$gjE)a#}Y+e$$PRGrAG-yKaP>)s2vIx)E|-H$wic&RW`>Rx3ArKLttuac63u5b zuC3>;Av?p8U*ywWU3L@sk{bIm*-hoQn%UK4H?!PQ?5eVxTW)D~71=E;H;!Fdc1!uX zF1wQKR+d|qog}-p<;Jrs%Fd80m_Vptf?UHep}Yxl6(fXlCdhS6BqW+3SF#)-VuD=D z@`SJnay2Uu5=@ZmS&lEVj!qHSzdbPpRv+X*PzK|s;H z1QhKgpy)mVitZ<%=m7$X9weaXAp(jXCZOmM0*W3bpy)9IigpoD^f&=UPY_V_BmqUc z2`GAsfTE`fD0+r~qGt(#qK&pQLV$!HFprCFQ$=4yKNqt-V5Y*q9+TNS;*M$wxD6um`2(c1(Ry+c6Jy95-y zM?lg01QdNhK+%T;6n#WM(Z>W79U!3SAOS_65K#0f0Y!%hDEf?mqQe9feNI5p7X%c2 zNkGw8gh0^?wsV&N2|sG!>`_JYybKv6XUiY_Cd zs5${fH3%q5CZMP$0Y$Y4D5_0BQ5^z`>Jm^?kAR~3gg}uS<1`W=;imEpa5pw4_)Py_ z`S}93L5yd78AXj_+&&FdQ3~f*MX796l*U#?>10TNO29tD@#?Rn&rw zqLu^{wIZOXH33C!2qvsKZRY*jRZt%|NyzjSwgr5aT>8K*Iaw2ZP*!s^~NG;VnPLGro+X88Pmm#;WLg&aaAQvQ^P6 zwkn#T{=fTG0&6fGg3Xej|j%Lpi1 zPC(I31Qe|xpy*}-idGU(bPEARs|YAsO+e8a0*clWP;@H+Me7JCT2DaH1_FvU5&}hq zG0sH+5?*b->Ns5$wKeaUZj14ZFQe#=827R?RkVfktD-yEs^~7ZD!QAking*<(Kfa! zx`(ZbwzE~y4z?<~myM#G1QgvzK+*jK6g@yd(SrmOJw!m!!vqvPLO{`@1Qb0+K+!G& ziXJDR=m`Rfo+O}XHvvUY5m59r0Y%RcQ1mPTMb8mX^gIDYFAxGnn`4~L0wg?9elo+o zT@_WAALMcO#CXP+QM5P4&CXCouW)`O&Q?WluvO8UY*q9Y zTNS;{M$tP26unD8(R&0Gy-z^V2Lu#-NI=m?1QdNtK+ypLiVhM`^a%k)pAt}Xh=8Kc z2q-#CK+)#}6n#NJ(U$}ieMLag*8~)OLqO3HLZIlS7-zWv3CEak(Z8&U(&SOK`)!P8 zd>KW@V%!Iss-hn_zbZP;Rz)Y+s^~|yDmuwlML)4s(J8hn`kAeYeqpPkU)d-+O+e9a z1QeYipy+o3ip~;HbdG?c^8^(AK|s+30*d}5py)3GivA{`=pq3{{}530F9AiD2q=<& zw)+mb8|6Fd@=3P&Zmdl}Q49e^4gp0W0*YKhpy<08=Y0VZ9wp!5aKBeYUzic=c*d7e zRN8TWZLW&qIKL_?!&XIQ*{Ud>t%?%Zswm7>MG>|tN@S~|a%@#po{gdk1Qb;ypeTue zqDll5RVJXQ3IRn`2`H*YK+$Cc6jdjns0IN=$pjSDB%r7k0Y$Y5D5^t1QC$Lx>Jd;> zpMatU1QazSpr{ccP~S zfTB(W6m=$`s0#r_T?r`aMnF+_0*ZPNP}GxvqFw|P^(LUG4*^Ae2`K7EKv91JiUtq@ zMJbLmQh66ip(aXfgpsQwS)UN09) zUxJ+Oc*d7eG|O>cX{U;2bADBH16vi%VXLCKY*ln4TNTY?tD^aARkVPuiWag}(IPgA z786jkgn*)@1QabJplCS(MK=*pw1R-5n+YgdNkGvp1Qe|zplCG#MQaEsT1!CDtppUU zBcNzK0Yw`KDB4Is(QO12Z6cs(Ga*oPz2p2KK*B$pAD5n~iuxNxw>zHkWfa}zxLyZU zbT{W$MO)dbXd7D<-NRNz+u5pU2U`{0%T`4@*{bM1wko=xjiLt#D0+~9qK615dYFKs zM+hi-lz^hg2q@Y`K+)p_6g@#e(USxe?Ixh;DFTX~CZOmU0*am`py)XQik>H+=mi3b z_7G6?A^}A&5duY99H+4W37WydqVjG|W^w_hh!^cv?^Mf=&R=ykR# zdV{Ts-ejwyx7e!aZMG_Uhpmd;mQ38s-BLs?G zah!Ys65e2b)Ow#P8f!l7|K9P8FQe#$P~;L&6iYynM?jHJ2o(L`IL``@@HX@FMaNZ9 zq4^F-sgP%U8AWA7?%{5#D4z4Hq6D@o3bR#FgsqAa*{Y})9sx!5 z2`FknKv6>iiW(76bU6VLt zP|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9QC z0*VF_P&9~uqQQhfQF_SfDnP=Yn4i1OP(}UB7!vY~FQe$nkel0E6^-Ehs^}`VDjLaF zMOU*`(KT#UbS+yIjbf{!OtvZ-%~nNOY!ratSCJOF+>$0*dkoC>l>d z(F6jDt|OpmA^}B{2q>CNK+zNeil!1!G>w3wd;*FJ2q-EfplCV)MKcH}x}Fdy8WwU^ z2#~P(u|{{eD%xxm%?x?Qmr*n))#!B%tUP0*Y1n9wngYF#?Kq5m59v0Yy&`Q1m1LMY{iFeYPt4fUSx?WTWUK0*XE+py&VrMF$Be z`huP;``lqVEVO z`ksKIV+0iaKnN7Q7ILl;AmN7QgV=smbaxpU$3vd+Wfc7sa_0_FMW;BwD*BnNihg0M zqF>pn=rmgu{l->BXV|LfceW}z%T`6_*eE(rK+zur6kQ;o=uZNQ{vx30Zvu)g5>WIH z0Y(23P;`laBKfuKJLCoq*(kCJD2gGV$RVI8L_m>CKv66KMIHe~J^@9g2q-E|Kv5ha zQ1oNSxkrG6v(1;QPpYCV<}>{=u4jB1MPb){b(kuOaDG*k$W}$=*s7>JTNPDctD=f* zRg}b5MU~j9s4`m>Rbiv3Dgi~+2q?OYfTHRI6xAT0D4BqwngkTpBA}=?0Y!BPD5^_9 zQ9S~R>Jw1ZfPkWg1QazQpy+Y}iW(D8ltMsJDgi}l1Qewc0!8tzb3%ZGdz&9jOK^kF z^sAa5pUrSRlUO(Le%<1`$v+n1G@o1QZP=plBE&P}J0QQUyr(qJh&)6&08-9u0RrAC|( zs-mkozbd+ht%|N?tD;eCRg}qAMWflOD2uI%#;{dUHd__tuu+stK+#wNipCL8lt)0( zcmj$h5Kwd-0YwuDD4Ik-(PRROrVvmxm4KpY1Qg{HP*gxbQ6T|E(+Mb=K|s;<1Qg9A zplB8WMY9Qkq7klBC_uvL=I5@jQbo6$f4%Ak*E7D1qIs^n;TlympYyAt1#DHckgbXq zu~pGxwkle}Rz*wMs%RNo6)k70qMO(#T0ub3%>)#!B%tUP0*Y1hbdT#;nWAWidH1tj6^%6C z0om_*#+Om_mh0BcQblibepU1iTNS;_Rz>fzRnhxwRrCQ{6@AE7MIW(M(Z_66bbyVb zg9H?PLO{`{1QZ=2py)FKiVhP{^f>`VUl36AB>_cW5m59s0Y%>sP;`WVqHhT(I!Zv% zcLWrDPe9Qz0*Zbhpy)UOMJEU-`jHSQdc$?P3y|fTDOppy-tAtP~*OG^6NeRrHp5be$0E8DBOD3h&7F!jKVXLBSwkpbDtD;=CDjLgHMdR2g$|Im? zJOM=$2q?OafTD>66ip(aXfgpsQwS)UN!zbAfV`a0*Yo5 zP&A8xqS*u#-9SLm90H2w5&}h6$2y|~NI2F!y1qsg^))}Tc4Mq(d>KUxW8HZZRna2O zuZkA4RnZc*Dq6}`Ma$T#XgOOI-NaT!E7+>&X0|F?$wtvF1Qe|zplCG#MQaEsT1!CD ztppUUBcNzK0Yw`KDB4Is(QO12Z6cs(GXX`n6Hs&q0YzH~D7uq?qPqwvx|@KatppTp zBcSLWLZE1Vtg}Oagg-Dpy}v*e%`xwow#RzLmr-E*=otcvo+Y5@IRc8F zC!pvB0*dw!Q1l`JMK2Lh^fCcOdkH9dg@B@c1QfkWK+$Ui6zwOV=yd{$-XH{u?u~U$ z3Xt$kuE5!;iY}S|tHPVHp7CWAy&LPsO;bhhaeh_wK3f%iz*a>cvQ^PXY*q9zTNNE( ztD=K!RrCp46@AJ^(IEngJ|m#$FabrM6HxR80YzUDQ1lf6MPCz8^bG+;M+hkTmVlz8 z1QdNoK+*RE6dfa==m!FdjuTLHf`FnQ2`D;AK+#VG6rCajir$WO(gjF(jrl&>JE~~0 zBje{-&-gNmev5Sn6{w;!oL?3F&Q?Wd*{bLqTNRyWtD-;Hs^|h+75&LpMSrnX(cf$o zT_m9B9|DU0C7|dM0Y#RlpSGjOCZH&WfFg&0BKeVs;5+sxatSDkC7{S7pvWhns1yN3 zr3omCBcP}Z0YzmAD2gYbD1m^YFabpoLZIl^SZ9U+39piW+S)y>igue{aZL0)Jm^?kAR~31QazOpr|1MMU4n3x}1Qb#sn0l5Kxp#Kv5b2Md<_-We`x*gn*)^ z1QazRpr|^ZRvT&mr>N#bHBP?6}991s;E6% z6lyY(J%svh7(Y9B>_bv2q?OWfTEEE6kSaS z6t(u8n3wDz++G%|_80 z0*clWP;@H+Me7JCT2DaH1_FvU5>Rv-0Y#e#DB4Uw(d`5j-9bRn76OXyB%tUn0*dY? zplB-rMcW7{x`%+G?F1CxPGwb-htHXB8C z2q>ycKv6vcis}YU6vxmr-Q6B<|`Vvso zkAR~71QZP*plBcgMS}<^8caaZ5CV#Z5>PaZfTH096kSO`(Fg*Ht|FjlBmqTN6Hs&w z0Y%pmP&A4VC~D_Brvym&rwRh6y(-E!Bh&YcFQX{icgwC&MLC>b73H#3(O9-B8pl>e zd2CfQo~?=|uvO7@Y*jRot%@eGQ8bx=qA3IvO(mdc8UaQ51QZnzP*g}j(R2ceW)M(x zJpn~C2`HLHK+$Xhif$mFXbu5Ia|tNAk$|Fk1Qg9DplAUBMGFZiT0{sGW%*7M0TSL( zMc|B4MIrOWqs6{wd>KW{eRs%8Rdf^QS4At>s_166Dq6`_MYph3(JHnoTFq8PYuKu2 zEn5}c%0|&T0*clXP_%)7qKyO;-9|vsCIX5!6Hs(J0Y!HZP_%`BqB{vFx{H9Ky9p@T zN!ty5>WIU z0Y%RfQ1k);MSBP+dXa#lmk20&nSi3b1QfkOK+!$|ie4q4=rsb0_7hO_Isrv*5K#0c z0Yz^SQ1mtdMeh($^ezEK?-2q;5BbhZ0wg@%7dQ{AqJ!qwir)7<@6j z!~mg54=5liRumfw78Df~d+!Z9_J)dL@4cd;V*k#WIqznJ`jvaX``mq=aQ64^)c?Fw z{de6#3RvRU*S*(~~}NHjDlwn?-+- z&7!}_W|5O<{dTj+N5-N!02cWHSQHPyq5uGk5&&2f1Yl7JfJKP_EJ^}kQ8ECFQUF+# z3c#W?02ZYKuqX_`q6`2QwE z)uQ%^LG?>5>YNxj{9LoB3*(zbUCCxqH?mojO*V_Vlg*+YWV5Iz*(~ZsHjDNmn?=3J zSkwoAMSTHSv^M~Y_5ongz5p!h2f(5n02cKJU{Njri}CHqG13m8VTkAmL2?x&2OwUQhqZ3<)C>gX))B zRFD|B^?b8vG~=5^g=Dj+h-?-Wlg*+MvRO2SY!;0rn?oQ8@sMDgani z3BaN%02WmPuxLC0i)sK^R13hOIsg{c1F&cU0E;F9uxJthizWlGXbJ#}4gz4&!2m2e z1b{_{0S#)5c|1}XL+(8dNqs*cy@>*bOVo?23i)JJSe%W9a&18JD zXcpNlnoTx~=8(;z!^vjRT(Vg-k8BprC!0kJ$Y#+(G8QcYV9{a#7BvH~XbAv|mIAQo z2mlrx3BaOd04!P#z@ilZEIJB+MJoYVbTj~qjsalNu>dSu1;C=?09bT90E4>~J6|Xk?bL2rlUbCY$D-AVLG?>5IxR6Ua-&&vI^&x~XOPXJGs$Mr zS!A+kMOOf@Xfptdt^{DwRRAoy8h}OD0I=v<02W;bz@qB` zo<*l7`lpH@;bQ&r&>FL-O5fAJAu*_asYSOW22QxdEV`BP&7#}LX3_0rv*-@8S#&4a zEV_$q7TrxYi|!$tMfZ};qWj2LbUy%#wg9l`0RR>~2*9F;09f=e0E-?0V9}!hEP4!p zMOy(_^f&;Eo&aFclK?Dw3V=mV1F+~B02Vz9z@p~>SoAyqi(UX=(Te~q+6M3}x+&3r zjR+Es=;y9)HjA!Ni(X0$s$Xi+tBHZ9HE-7JUf7qK^Pr^f3U7J^^6SrvNPa41h(S1F+}|02X}- zz@o1JSoAdji@pJ1(YF9B`VN3aI{{eqJphY-0ASIN04&-Cz@nc3o<*-D`o9%H!msO_ z9^1{LL3)w&b7D~aQj2~|45VLS7X8lnX3-yHv*=H;+W>GvDivj>FN&sL{5P(G?02UZ2?%+4uC}w02XBeuqX?FMePAt)B%7+9RZ$2yA%C`M3C_LdZY1IvuKI_3{9t` zp!%g2bxR7=UuhO)Grn2Woop8MAe%)!$!1Y6vRSkj*(~Z!HjDa@&7!_!vuJNJ7VQJT zqJ05a)DM6~IRGr`55S^a02bu|uqYpZMFRj>G!TGAg8*1G7=T4X09Z5>fJMUqSTr1f zMf(A;Xnz0}jR0WLNB|Zc0KlRH0iH!&lKd+~knpi8PS+%_r@v2%gi%RB^-C=(N(x+b zwOLfm_-0WF*(@4EHjBoR&7xAWSu~Dp7L}3BqH?lXR6#b2D#=(>1;C3jvXga{NXmpbQVG$%eLr-FbX3@23QBzV-{Zfl&Cj~yZ)-0OC_-4`JWV2{4 z*({nzHjCzy&7uWlvuGjNELuc1ix!j3qGmD{EdgNBQUDem0l=ao0a&yQfJMszShNCw zMMnX!Xe9uPjs{@SF#s$&7Jx;o09bS!0E>Z^7HtM#(Ukx!x(a|rR|Bx<8UPku3&5i509bTA0E=z_V9|{LEV>EcS#)}m zzgz?f&rTC@&M=Gi(u<^K<7QG0-qHO>ydI^9)F z&7u#;X3>XaEcyt5MIQsO=o0`IeG0&$&j48TIRJ~k0ASIV04(|nfJI*eu;?2A7JUoA zqVE7$v=e|u-vhAd2LKlR2*9FU04(|mfJHw8u;>>67VQRj7QL3_e_aF#KdxW<*kKms z1||HO6jZ;|qCb-YzusmR{l)lZ(cfgV$Vs-IyIJHTn?-SCv&c_2i{i;d7G(gis0{#%+5)hs9RQ0W04&M` zU{MwTi`oOQr~?3tIs&k$699`k1F)zIz_aN0B!Ac2#iA}fMVvp(qUZJIQPw)n?-%eX3^ecvuGc(S+p4 zE&z-209cd{z@h;FEE)*FqCo&G8VtaqApk5I3c#Xa04y2~z@q&CShPO?i$(yjXe0oO z4gg@$fdDKT1;C;L02Yk~cotFQ{EUG4(MdQg>R0F`GS^yT+0kEhZfJGAk zSTqrUMUwznG#P+JQvg_W5CDq~24K-404zEbfJF@eEIJH;MU4O~nhL<8X#gym4#1)& z02a*vV9`u~XHjvo|2h#Qe6hY8TVfV{sRyQ6$wBo?Et;Dgc=leiXddI6Mf1sK(E_qr zw2*8TEh3vmi^*nDGubR!LN<$*lFgzc$XIkF0E?CZuxL2|i&g-z=qLadtps4v(Euzu z27pD!0+kMOOf@Xfptd zt^{DwRRAoy8h}OD0I=v<02W;bz@qB`Sabsbi*5v9(M

x*32)w*au{R)A;GS;_t( zB1rgQy`Wxe7G0#*MYkmf)i1T^uH?YP2hF0p8Q(0rhin$zOE!z{Bb!C{lg*+nWV7f2 zvRU*X*(`d9Y!*FC#-c|6SoA0Wiyi}D(N+K!Jr2O4CjeOVBmj$^0$|b804#b2fJM&& zu;@7e7CjHZq89*I^dbO@wgIr{B>)z^48WpS09dpgfJLtYu;?{_XVD$W{*@v~_%r=F z?44%Ot$JYEksMUN)S|bN0~bGR7QM~*X3;xjv*=y2S@a&+EP9`87JWcAi#{ZqMIVvP zqL0aD(I;dq`V@dgp8>Gwa{v~70l=a!0a)}E0E@l`V9_@KEczCJMc)CiXeR)Rz6W5@ z4*)Fs5r9Rz09f=B0E>PGV9_rCEZPmgqF(`6^cw(+eg}9Ky^-vHR0IjH)!Wr?nnguj zCH#>bRKL_BCnfOFqh^sW#d`8)Q5@MU@{`S?c(Pd(Ae%)AWV0wpHj6@JvnY{l7A29f zC>el7DF7@=1z=Gc0E^NASQG|eQ3e2u+5oVqEdYz!0k9|nz@kh57G(jjs67CSIsmY! zBLIs!0kEhu0E@Z+u&65li@E`@C>!8e^jES!^q5%GS??G9Z5HiPi@K)-)i1SZuav;v zkDEok8Q(1GLpF>0lFg#M$!5_$WV2{rvRTxRY!>B^&7%HfvnZF0MR@=$$_HT4000&Z z1Ypr102U1fV9^i&77Ybp(J%lO4F_P+egG`mAAm(809Z5@5P(HR04yp7coy|c@mGo<;S2SbXL_Z0J^cmx)@(^iQ2kPi#-#)nJZTn{F}_(; zPBx1w$YxO`*(|Cen?==RvuHfoEUF=!MYUwJsE&+9^#ClI0KlS&04$mWz@o_jESdtq zqJscfbT9ym4gp}%p#Usu0ASH!04!<*V9`_n7EJ?S(R2V7H36__1^|m@0ko(=o)T2Q)S?9`fjgfzixx7zS+t037A+>5Ma^Wh zXbIUYT1qyHjv$*wN0QB=Wn{BxIT?#q0I=vN02ZwTVA0V4EII~&MaKfLXcYj9jssxP z@c=A30f0p(0L02ZALz@pUvEII{%MW+I=Xbk|1P6J@k=>RM`1As+m0TfM?OX z6#ttdNceF5-1U63XpP=HTALD7ztp1jDS_XgHH*$=e6#30vRQOK*(|z%Y!+=Gn?)Cr z&7zCQX3<8nS#&YkEV_h@MVA7wXcGX7E(2iE4O zMb`qb=sExvT@S#b8vs~zBLItT0$|b204%x%fJL_gu;?}b7TpfOqB{VdMdzgWv!4@- z=IiIK*O^7P>szyTrUcb5wdmfIK*0-U(S3|>7Tr%ai?)!>q6f%k(Su~O=pnLM^f1{h zdW38iJxVr<9wTGXRsa?~4#1)(09f=S0E?aiVA0b6EP4ijMb84T=s5ruJrBU57XVoF zA^?lF0kG&L02aLrz@k?GShO90MXv&|=rsTq?EqlW>i{fz1K?S7cZz?82omm~KNE6~ zS@eC9gf~-y>X%ydZc1SFHnZqG#y5-JC!0kdkj7?Ecz0FMPC81=xYELeFMOvZvj~J9RQ1V0H{Q|(E-2g256@W#*0kG(I02ciLz@k3^So9abv*_&<{|zEY_)q;X$UA1y1#Kn# zof1^P)FOXs;CZ>9-DY&26Npc3-O~?{&7uUdSrjCjMIo|Tlt?yi*fM1HhuO0MDY{ss3RiNcaZr-1jkyK2eKGQ-kW4T2zr5n7qR*s$_h# zsETYBRg=x4@no~8hHMtqlFgzzvRPD5Hj5^Z&7z59ESdzsqR9X(ngYP0g8*1`FaV1V z0btRg04!<%V9{X!ENTQ`(Nq8yO#@)jbO07L0kCKW0E=b$&7vd7 zX3>#kvuGLFELu)Bi&l`$qNB)W(MmEF9Sy*uV*prmEC7pE0kG&e02Un&z@ifXSac!) zi%tSy(a8WTS`EOWQvg_WDgcYt0I=vZ02ZANz@jq%Sac=;i_QXI(OLi&oejXEa{!)2 z3se1DMUe3EdiYsn79E-AX!R|2r;DgYK;4Zxyn09bS_0E?~zVA1se zEV==JMK=Pl=q3Ob-3-8@TL4&eD*%gb17OkZ04%x#fJJu#u;?xT7Tpc-EIK#UpY*m^ z^phTo&NGWL^+xtRsX_HiE!vVA*!Nwt=mEwziykDKMGuk9qKC<5(IaHD=uxs+^cdMJ z+DbNy9w(bcPmrJX3>{q zv*;@_7JUuCqHh3L^eq63z5`&5t55S@y09f=R0E>13u;?cM7X1vsqF(@5v>Sj$ zzXGu6Hvks>4#1*609f=V0E_+tVA0IuN2UH~lG3xGwv0iH$iY5uoGknlPB!L&e{*V8{#e=4+3T2TE`i}p!JhEAoPd1ANkjHqG13m z8V)G68~}^T0G>sAr}=w)A{PCsZ=LO979FT>hm@xU)i1TEIxSH6nOQWR@y((d zvRPD1HjC=WW>G!aESf+zizbrIqDf@4XfoL>nnK2+g8*1`FaV1V0btRg04!<%V9{X! zENTQ`(Nq8yO#@)jbO07L0kCKW0E=b8m*MHex?S+tRC7F|p>i!LFXMVFGzqD^G8 z=rXcdbUE29x`J#LZ6;&Ul>jWd3V=md1F+~C02W;fz@qB_SadxAi*5j5(TxBsx(R?q zHv_Qf762CA3c#Y<09bT80E_MbV9}ibEV>JTMRxf!7%%Y+=3HPT3)i1T^p|n8cTeIk4#y5)|A)7^ylFg#W$Y#-2vRU*v*(`d3Y!*F9 zHjADjn?+BPvFI597Cj5VqUQiu^gIBIUI1XxivTRz2Ed}109f=g0E=D$V9|B}7QG6< zqSpXev;%-euLH2?4FDFs3BaPa09f=k0E^xMV9~n(EP4;%S@b}fe?Ji<{JMVb`a!d3 zieJL}X+iZ%E&4buaL`V(=o7{_i#{crMW2z)qR+`@(HCU1=u5I$^cC4G`kHJOeM2^j zz9nPPcK|Hf3BaQ70a)|{0E>PEV9_oB7X1XkqMrd+^a}usb_1~JR{$3M2Ed}<0a)}0 z0E_+vV9{RyEczROMNYbP+p)+8z@j(+7Wn~K6c6w$`Y_GEN(2d?tDn36$Sj(qA6W~e z2h}gNC^0>7*$-w>662di$z-!Ag=`k3lFgztvRRZ)HjBb!vnYdX7PTRpMQzDg)DD0} z5daot0IuN2 zUH~lG3xGwv0a(-rfJJ=)ShP35vnZJEe?kNa@6a2Kp>(gOf3ALFcAxa1`lS~2PY-;y z%Ph)ee6uKzY!>B{&7uKhvuGgMEE+^Miw2X;q9J6nXeik%8b-#V;Q%b!4}eAc1F&cW z0E5)799w{qEP@WDga>7XaE)!0L2$O(vT~Q^;n~L1eS&V6s_s2pNkG1z=GF0E-R-U{NCgi>3mwXc_>ErUS63 z34ld209Z5=fJL(aSTq}eMRNdHbT|Nu<^r&29srBx1F&cT0E-p^uxJqgixva0s2Si{ zG(O#5BZ7pl&=027m_?7PMN86y>X%xyEIrWtt68+1@y((YWV7ffvRSl}Y!)3&Hj9oS zn?=Wx&7xIgv*Mdt&s=mLOe(GltX3q+9c z>3R}7(kwbmzmK*dJ*a-EMHibZMK=Mk=w<*G-2%X(TLD;f8vu)L z2Vl`104%x_fJJu!u;^|87Tp8DqI&^YbRPhV?gwDe762AK0PrljDBb_A2ofG3F|g4r zO4E<5J(wO;zto~f(*uA1X%;=k_-4^ovRU*v*(`d3Y!*F9HjADjn?+BP&7x<>X3?`` zv*)z^48WpS09dpgfJLtYu;?`a7VQ9F(dz&#dINw( zZvwFBEdUn14Zxyz09f=c0E^xOVA1;kEcyU|MIQn@iylt*_xejL`cdCUd&DeSte-FX zC_SitsYRcq2Z|k?fPC)ybH+D|z95@LUy{wDugGT6*JQKk8?ssSE!iykj%*g~B%4Lw zldHaw)NcdU(e`7y2i+Z z02cKDU{PNH7VQndqJ02Zv@ZaQ`T;zPlEVI5M3C@Ay%b6gdp-RZ^sU*Pa8UhHi}J&P zm*UN$0gP`J4J4aIgUDvlV6s^>glrZKC7VUV$Y#-SvRSkr*(} zCX>ygDP*(gAhKC>Fxf0RglrZaN;Zoc$Y#-DWGrd~V9`_n7EJ?S(R2V7H36__1^|m@ z0!W3d;k_L0ASHV02VC*V9{a#7BvH~XbAv|mIAQo z2!Ll%UD!WD1PPz7pO~#Ti@IvJ|HyDq{ZfmL3I`5JG>cX;zFBlM*(^GSY!)3$Hj7q~ z&7$MTX3_Cvv*-k}S#%=VEINsdMJEHWXf*(fP61%isQ@fm1Hhuw09bT70E^B5V9}WX zEIJE-MQZ_AbT$Bs&H-T2Isg`}2Vl{;04zEWfJNs6u;>B+7Ht4v(S-mkx(MJ|v^?xT zUIYo>m@VS0FpHj2i#CRX>X%xyDIB;W*(|z@@y(*k$!5_NWV2{9*(|z}Y!+QbHjAz% zn?=`<&7y0`X3=$IEV>?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4fJJuzu;@+z z7TpEFqPqcDbPoWF?ge1ceE=-FAAm($09f<@0E-?3V9`SWEP5E=S#(L*|C9(4uF|*h zFExu!(=UWP5)P_gYSH82z!#}z(G!es7ClKei=HBzMNgB>qG!lv(X(W;=sB`k^gP)t zdVy>fy-3EQZ2&BK34lc}1F+~702XZrV9~1pEP4%qMLPgk^f~~G-T+|Hn*c0&3xGv$ z1F+~F02aLqz@qm6SoA&si#`Bg(T4ym`UrqU9|N%H6M$#YV_|<H@%`t^h3R2Ed|h02XxzU{MbM7WD*RQ7-@%?FGQ1-T*A>1Hhub04&-YfJOTNuxMWZ z7WD&QQ4Ro$`U9{i7vNcxn&H1t1PNaq5OLBnyq^B~de<>8BdC6Dg>n!o}LTA7~a$);IX;GlJ@uS~NK$;L9?LrZB!)bP(ArI+$!09YQvX z4kepK4P>+EFtS-)(M$jq%>rQ2YycL`0btSL04$md zz@m8oESe9%q6GjfS_r_RMF1>X48Wph02VC)V9`V02bX1z@mEqSadG{i|zwp z(ft4{+5*6$2LM>~AOMRV0$|a@04#b0fJKi2u;?*>XVGOD{@X;5@OddB&gEv&3cZoN zH6y5gsYOp^1YYT47Cp`QX3;Zbv*=l}S@ay)EP9@77QH|=i(Vv~Mcc?`(Mx2r=w&h% zy#m0Z?Eox#6@W#r0kCKX0E=D+V9^@@EP4}wMQ;JH=xqQNy#v6acL7-R9srBp2Vl_$ z04(|tfJGkxu;^m|7JUN1qE7)>^cet)J_mRfJ(1zxErNt6b`o)(G>eYZZ#90A5mdj_ zqHi(+9kR`$ZyDb#`i^WC?IfE;-;>RvAIN6Wk7ToG7uhWOiEI}AOg4*tA!E^Q02ciU zz@py(SoAvpi~ay$(VqY;`U`+Xe*>_{X=B}XEb;-cC=P%{egGE51F$Fnz@h{I76k!V z6arvTA^?k$09cd^z@iiY7Nr6_i@wV6A0UE+zt0eHzBY?C>DwV`ZG!5TTGXaZprMCZ z)RythqIP7nC_*-iGRbC97TGLnPd1A>kjI=Z4y#ZLX4*-ky1z=G>02bu{u&6%(i*f;2 zln20~d;k^=0C*OK+xSluLBcm`w=AQL*VDg5a9SN1ZChB3ZbG@NV} z?MF6?_9vS~BgkgaNU~XU0NE@$kZcx>BAZ18WGosDz@kC`78L=os2G4nB>*fM1HhuO z04yp6V9_`L7L@_8s2qSr6#y)%1Yl7W0E?;tSTr7hMKu5{ss&(C9RQ2!0a!EvfJGAl zo<)P(_@5C$!n^gYvms{D4Q_|6O;G((iw*g13c#Wx09bS+0E?CZuxL2|i&g-z=qLadtps=$O=;r~_YsS( z)eoi}WEMT8-)cO%O;G((i;im($lu#6I-c>(q7%qw(TQZU=p?dPbTZj2T1_^KP9d8` zr;^R0HDt5sG%^;Q4#1)_09bS;0E^B7V9{Ct7M%^iqH_RPv<`qp>j7AFE&z+p17Okl z04%xyfJGYsSacx(i!K6S(MA9kT@1jYO8{7ODFBN$0kG&YfM?OMZTu5Nknm=SfmLSF zFZz>Mm$wP3UrswGF3>aavVJ}%k|S5$PNYhHjy68BNZut0Mb^oQFeP%QTvUZ4JLGWI zF49SU6S94zQKak~xmrFznH~8?uCjVX2FjOj`$m>`cbtBahve;+yhxz8;|z+F^>v(K zk+b)4oDq>7{Tydhq)V>j6h)@xJI>h1wF4ceJo4RO$El7C9_Bc8k)!r=oJo;KMmWyF zk>G)jb6BLJz;UKW))hL=tjHV1jx#sXZLH%gj5LjNoF$R#%N=J~n% zj;?i_6C;n+JI*PQ#7T~GdZcQKbYek65`<9r;cJ>79Wk8C*8 zalVecx7KlXM)q3gIJ+W;pX)fgBe$OKIDcgRvO(J4mpO8yend9&giB-#_%ff~B%8pO znSO?u)|0U-zU#9+_iX(iP`k&&B@?~E9uxt=trvA57V||(W{|c4+GW9=( zsrF^+|Ljrc%hdmxVUjOXe_Q`xU#9*z`eD9I{dMc;>2_hsr2MXdE@>Now@ z`!e;b+86jT^}DtkeVO`Y$xXgY{kGd?U#5Ot=^9_Ae&6H_pmQhKlQZLm#H6HdCHfmpF4QYm#J?YZ}Vm9JAd1Knflhv>%L6A z_x`poQ*WNW@5|J?UmyE2_4dW*zD(_Ze(lTD4#ZAhrd|Q=@@48Ne77%CkHLTVoTQ^O zWXIa^QxnA|of8&w|L<;`o~#(sG|r~Qr|`bz&k@=BWbqSJn;>_5JNMask` zM+|h@ca^=&H}D{30ohZ3Qr1iMPT#<0Wh;fvm%sK25_|*CRQ93dH|4LxPU%kj2B)1R zqs6hY(MsB86zR%&hyUs zaiu%wcOJOmyrY~>=gE5L(%#B!F8X%YGw05&MkK6x@_dNNz;VjRSyMFlf zhNB#(t1nwjlfQ&Ge?r%n<;13c348gIx~2=&zXZR$5|R^~{w2iw6C7WLZ?Ckr$^NuX zY4uqdzHpY~#PxELlMfK&IQ~q>pSEA}{>j6WOWVp3+FsH7or4`E3GqIE+5ySQ^0GIW zPhhaGjMZ6o+K~Gs;5doy6WL#qY=QxAg30MJE1gbCTVHZ=%M?;m9e;@VCMTyRrz8)P z>7`}08Y*3eidnj_MVoepO;VyRR2!S5`)bQ1+u9^;sCF_^pk+BCsj`+j=S=sBtVvdX z-+>*NYo89KZ8Lmr5=ON@e{=_(N&7&|62)cRJzAQx!=Qh%jeX8Aai31s@|5fv@y?IF z>Pz+6PWkgWleKJ>9l(1*pUu$&wli6a9=p94Wb}V~_~d{hk2dn>bH-~~BE;uR)WZD6 z$INeH?EJ=G+A_b1I=_WBzwwvqvlHb{CZ&Z18GotH?!O))tBg>ia?&JHSS`B zWet6fd~mpBwQJnP_|1DkON}i?&87OxJ%KrO|20#&JaK1Rt3|FaWa^W&Fx%RgwVxEb z_O&rGe5l5$7E3ZbV&FnBvOHvF_RwKsAF+9+9Dn@ID>_Br?`f%y zPaZO?YSO=d?&8MW8O;lGn-@>ZUEI(-t*K$*;sr~ZrY&ijo;z*v@`XzlD45nXed*$+ z=9t%Xco}+l?!v{h=gnR+`-mndch-V=O}UM8o0jGFpSxgMK?ciODR+4GxoXHJ{e(71SBZhl_Fz=i>N1M(a4^AzR?%$dJn zep60Ugi{<<6czZSKJ+QYH8ODwMWw-%>E)rAA0-Z`FHPzl32k#^ z+GX;@C$)z+iF9ugy=)S0)I}IzgN<|-BsIa`Yf_+-jM%YzVDBD*PF>vT>VnBqc~koD zh3Ti`<#+FwzfYi3Hyg3Ne}yh-ZbHXENB^>M?$ZwPba}S>w7opF0kQ%eJGm?~(6O^V zu{QWe&6Ndg8|bKW80jvn4%=Ji9nKD9xNX`^Lf72fKu%tuTW4XpZj-lETazrWO>(SF z+}K|RA0UHg<^}rcl6BK*<_2_%88W*)YuALf-CE6{UqZV;*RF!B-EAKIV&|cg)Oq-F zb9Kn>@-(uqO{L{YUd}$f{VTlLt1&H$zvt@2X4&@t9I#C0@SiW}lyv}KUOz@1^go$z zcV^Ho&|^T)Kv(~f-Xiu$$P9FC-PqlI0ij)c1|qWd{)8@p47Y{@+BW_khI73rYv>L3 zzn`^H{Rz62y6ZDp5f}Ip`pW9G%h3(v?QGg2|3@1p&`sJ@{ORGXQg_?#H1z+{pB&v@ zy^zn9re~m=G{BxJ$&_7x)U39FuHGVhlH~^Wk*T!H4n)N1{xbtTCFS)9^z16Y7NC=? zuN)WLB(J(LJJ8O*>e&7PpZ`>!?qmL~$MpYycsPmpH~L2WAI!M(0GVqzTlaVW8^^>= z@y+xOC9)^(ofqizZ#%WE$bTPGI*L|(_vszzq)O_Jt_P=<9iIchNIO{AUT4$mtL-Dh zyHQ6U;I?Ad{@wN9(cKHVEzeW)bl>HbRN36_YjS**iS(7jp}yF9k@uK|9MkVUR@y8} zMo8rF{qM)#u(sBVvW?`Jb@s8cfpxR@>k;Ut#{`?nzaBl}`pAV8%s%j{&svP6g6pv}hFDM)v9ip(VwqC|Btg5Ik zFRqgz>nlrbxRS!L4O3eNET}1JsI01!foqFv>WYh^uZ*jfiPl%v)>l_o=?e|jrIU)w z8%nBbDhlenIm)D34?eoQs<5n~sGzQ(p|ZYWba9QYM^%kC^uS@UGp?*^sI4DeTUb-7 zgOya(R~EU04IMVtt;1U_W=(Nzb(JikH>E)`3~iyyUR+a98?)rJTSe`dhSBvUB{Kcm z(kaE!QU0-Jr4`zm?l9Vtqw``Hw6wCJo*56fh08B#HArF2^KbhU%))%DQ4( z|fvCGKV@t}KvPamj>WLsCrRxT{4E3K;Z+G%)n#QegTF-vR4H;fj?ib`v}nbDTsBz0o$W@{)f ztt^YS+Qib5(uRU+cPR_2Dl3Z%)fU&hl0n*F?$aVuqPD)UP%Mp(jk4qGi|dOUN~EQt zFI5-Rl-5m-MwPmvpmMTpx|T_}o2|C0)?I=ku{yc{gWdVF7B*Z-zU&_jwN)i04Xp;w zAKq%{!h*_%x|)K@+KSRTcgi)z1x1tHl^NYi*qYh`nUK4wrGZUs=2=x+*ic(nC2d+P zI@&h$+NRY+V)m!#3Y$Fz*{o0X4WNzT z4jkm|IfLCfx--uMxjU1KL}A-j!|cU;X};*xN=s`>3L1(F3mfuBm)dS#*lJgF4=qKd z1!Eej>g%fO>l!9hmDkDs6P*NmgC11$@S}&Wn7y;8ctWXMmXEHl^;%i>jo9Onw=1d4 z(#X1VYkS0uUNcE{>4vHa#Wf}6RTKA|X-(yr=wVa5DyWDKP+BbqGuy<~ayW@Sp1P}4 zD<(t_k^`a*HaezpbOW`_+Vef;W!VtYBn`!r3X6-2ViwsNM2@g^1#*NaE1uj?Qc$XU zIor^N(C&&XT2+0GJdu5@q`b7S<*4skst2=Z)8!9{?%=Ykdpn@)f76%Fo3}hVZFhGl zt}1Q4+c0N23|Cau=;qMlq&JBH?hZ0{!Tg!oa?oJB?w{ZC)6&lGU=sYHJF`s)EA0 z(h1%fXh_V7k6lzw)nh8%)3htbKp8}z6tp_j#~vqIj$ir3(e0>Dql;-;hzYXC*W1ZY z7PDmlnd#`70y)8(P&!B1RzCV!O=V^b~k_X?3weMrf16y zmc`N8sohm2GC5JE<$&FCKqxG%Y8WdAs^|!`O+{6axAbxi5Ph+*xV*f+yr4#uA5&T@ zcI%0Y6~Qr%0Nyg@$>{DXwmO8@*N%2i-VL>5Q(2!~IDB}v-eT>a zpRG4p^M(x=l-+l6)7+-U=BB-~bLLH3xOC*S1&fz7Ez6lVaG-!CvzE@ADs{%(1&vE` zoNV#Qu#IT%s{pZO|-+iYyFWh&=!t9)x z**R4MvUB8C;K*sR068<}H8nRk&TPt=+cbaXl36431bKUNj+!HB#?txImdsu-Kc`vl zmP&0FHeJp#(d@3`&{jUW+ul2=X+Oc;kj0f%^>VOtJ#KwPA3Zb5MPb3{((=+NEm!4v za)8%S2DUm(w;WS+$BZi1Vy>LWtPix9RD+@UR|%Qb|@T6cT2Q=*q3rPAy0E>^ttbY+`ezF@(^e8(*V{;@2rE(BU#UsuSK zMpsSx#~6j>a%PcpwI2E0w(*YM4SI2)TPr_rfGv0Qur3WAolHwB>2+a)HI+ApoPXUX zvN=5<$HbW3#oewg{l7gf>+Pu8`Xn?+rqtA+x0{<5FZQM>-NAoZ81EDyd#)~(cd?r< z-CB2))}3KJgSA}MNf+4mH|^59%`Q(2X`kCga#ij=@w%ce%8L%=J>%dRb9w1r6ieU9 zF7;&R^`<5(71Js)Bk0wt9FklK+(BD9mC@et5SxnE4`i<1A-lMuI;L}1sJ9zpPd&Qa zv3=9A6XlLZVVN8qy)|mJlOVfZ@kHAj7~ApwpLFp`N=vF*_di?gDJm#*-!iC^w-}<+ zk6xzyb8nFDxHQ_~x-&!v_tv_;vS5O^uHEbCD>02)P%oW#xu}cntm}msP3M_2Mmj#; zRZ;W>S699At*X?6fqSaY|DV2UJC5`OO`w(zVC#OJIv5q51*xqrZLt2iZV&pC1<|R= zQJx9wMU>4$u8-|mzH}y{%NNrE)iqUPOQnY?o1#+AWpc-YS-Ohof~Y2?a)CQVWN2uR zH@{l$pXAFGy3D}sqD1>COhAuZv5LVFrKF%pZuabPmUSi2xsDOnqn9Tw{i`B7@#Ra` zgjJJPh%Pmk*s;>P1{bPBCyYw+kbJ$+iQ(?u&-leXS7*;a0Q$Tg4G9@4doX%9WYY5%67c4BFryb^P^ zqz{ZJCs}}x3rMn=5_DI=oN?D ze`pv}Q0m?M6Yrvf(Kynxs4s81xKQ1>K8d{?jotzpz%3x{8`4lrOs_ATIqtDf7g4)r z3=(^_FSk}p3*{Ih$Mib4ouWh4N(WeOAJ{Dd+AZe&|NmR>dKWcKT{_ckQSIijkh&`t zjP~5}Za?!1Ygi(^H|gj$l$00Lwv5NC_0?*&-a+8b`W~IE=(Z^=DQwv;`Few!IoVwj z?;PoFXz%X4K8?M}?e+pqtk|AUbV4nck444*aRI4YdvdYYJ*HpS`aqy2)6d{a&0Q$H zeeFK+Zpv2_Oll~stg|yq>^*6BIsbW{^!in-boAbxJIR)t+xc>v7(Apoc{t9uoZ-B? z%le{r?%aX&Rx7LHo|457vAa-q#(#hB!@HH-a=!Y9cu>jG7d9=Y|4sY5SWI$%&?GDk? ztJ_+!w@_U}{_X7S9jl{v*_f{T)(*!8plgI{N zc=>iJ(hiOb^wy~R#JicRPwCR+$KDmSsp|ds64@nU?@G1qYH(@ePE;B>@3yNu8NJKtKJl)TnX?{&Tc2s7yI1TU;Vp?w!reQg?NL}>P*ELon)dY2 zH|un|E$>>jTY69SAw)S?hYI0)5%L(r1>{-sQ90PK&mS>xmo>96K@AH7#4> zt)j@w#)@vXSi@S5pL*ju_T40w(_3G+y`(MOskXkJZ<&O=;mPF}3rmlxw!T*0!?GUj zKW-@My~I7-i?nuJF$7GrLQONm)l!lx_H_ZiT03~zn;(C^U=TcMpYWMjvkgy zrNq`TU+zss+n2WR?oP(M{qJ=P+{TH$*mV1E6Xh*keN(&2-lb)cyc_WPmfoJnbUjz; zo8TOScoUT|N0%2=mdT!5EO)f*9K=hyDtivzvSG@ryfu zY)zSLEN>qyl?~r=2W?`3^r1P1?lGp`y3uo?*FG)xD)la4bkOMSV(qPssnNdi9?jdT zf2cmW`+@djm^QL>dr*{KXn zwYn{&{Y`J9SR;Bz4wlC~B-H-bTb|agEOhju$m^ZBlhvDrOw2v?R2H;+UO~6)9?K`^ zl;~TE+S;5{TBhM`yNOjbWp>3Gy(q|+i^-Tv5jhO;=0xl6Qi;5qO;1BVW#Nn|EZi@< zuikhsSUfMgc;3{e>C@#MyE;A=?cR&$T)z_S`w52FQGM*^?rU zBj0S*?-9A*7fg~b*!*Gq9Qic1zJ7~V`RdH;T4lH|waRe2jXx*bPlr1|+CYb!Vs)8S z-D+{NDb(*cX%yYYT4fZs%6A-{I1#10R@o$djjPK#+z_iHt&X-@ZMEL&G^_IcTX(!g zR*$uMqSdulFSB~P)qAZzWL3Vz>Q3ibt1nsIVf7uWA6fmv>UUOuvMOIPb*H1>)zJ0P zUqRO@Um|sDTdVqOSIWCt-OK8}R`ab6wK~#jq195WRaWb*9%QxA>P)NitTtO+ZuMBJ zCs{qs>e*J$w|cSFE395?^=7MgTD{-uBUYcZ`hwM0t-fvbBdcFp{od+st8##J+bKc( zbKB8sJFA_ny5G@}_T1ZYp4FjN53pKnwcKj0)hSjRtYY}%SbfauGge=+s{5Z#?>(!ZTK&fAE~~#=jg$RShflQXe$z>EmgTNi z_p;j0>OiaeSuLK9gbTK&c9UseNhoYHnmvD(&ZN2}ef_O+U8b%@oGR*S5bS=BGR z>2xPsJtM^-d)auh#w^`j`^XR?*=yHXurd!Rl+Qn)wt2tJOSUu3{SgYf$PO&=8>RhW!tsY}_wbiv& zH(0&g>h)Idu=;@2C#=3`^>wQsSpCxKk5>P%8jur~u5X&vEUVd8_qIB~>i$-XtX5c^ zV70;OEUSyGuCRK7)zht>YxNSVS6jWs>b+JUwfd~p?N;Bh`l;3LtnRid|8ttVeo0o_ zS?y_cs9Z+r`WITAEaz^`O;(SR%P7sOtzInWY|YnNeMnC5nxD1$fm}vu{>Ex=xrWd@ z(CS>dX3)Ic>TU9)0Gc1Nx?8>`sX5Tas|R%RYMIp&yLMqQC9C5=;cSO{x;alLAh|z@kR~vYK7I4 z_w({PtIv(_@*7s$9O&h4RwosBxykA!gc_=i{@&_7W4%1o>cVkeKHBPCK}4Zs>_*J<<-&Sy;^1Ulv*#JYxM=W;L_pWvf6Hvm%Ce?GR4a?t!_Hl%Qss6RDOU# z$N$l4zeX<)x4L+mmyfl2Pm`A)xBAyiFDK9PYSA38j<>pIu9wfZx^2Ff-?5sx$jd#g z9^CBZ*;X%K>gAiQetx8vf3n(tg_rlYx@4u7kF$E;F~Vq;N@DYr=R5I z4OU-X?dA8ZwqN7ry{sO3x|a{Py7^2m-)i;CwO;X!4p{Iu1$ z3%#6fb?inj*IPaF5-(q5b^9hSe_*xa6<+RR^{^|wJkRP?S9|$(t6yL14)9Sa6dii&&gC6&Cfz=gHdU>_ghoAQH^Hvj{^Kx6OzMvhL`WQy7MhB|7mr|yIwA|y7GN5pKA5d554@N)zBwij##by z%*zK^UH^rbFSGjQS6=?iYWBBY&apaUrQ?Ds>GpidYSLd`&azr9_bv4GL#&=BKk%dZ3af9+Fa2o#!fFrcplQyvIxEr3ORe4{ zKLVt$-*0u7bmTPq(!9D~*sEi#u9Dve($~+h`h@&YkmgscrpPY_Y3^XPMmmC;8?0U+ zzagagN~`b6j|pl1%4)A{FXvmG)5FV0TD_&0mmjeDv;5$Yj_>c|)e(Dpwbbh6@;hGo z`ps7F(;9G`r!8;Snj-fDtiEIXbIV^_{oeQ=mYp1Lynt4je%Nw5s~wE@vfS5dj`3lZ zM_4T|UTO6ptFx>wwR*hOv#f5kdac#FtUhLSn^sxhc)3BQReqwxt>dg7WA!$xpIQCQ zYL5IQjgEJi)%8}Nw)%(F9Qn-~ZHIiT`&m7}>KLnKR_m-zvYO_I=Q5u*Ry$ag%Oscg zvMQH3ZXRIOy`LiEx%X3~78ozHDwhH7@Dr>~v3iWv{P$*05FCt=ufTi(B3MDYBlTx0_}2x^j%M| z{!^Qqo&NIC_5KR`|L0v$caZ7&@gjNmX2t>;+kM_Rb?V}#BfJTCM1IL6Ha0HS?}OMZ zydnNc=IZZ|*c4?Mo&Ngk7ESVnteCmZSll>I1}dnj=-;?x$>P~lmoAaX{_j6J$)K{y zqIb6k?J=q}qx(hDLHm}b;rn$WD3*iNmn^Ky>;@Oapb9UmrPHGMS35erE9E)k z=ro>?=^d^k+Jo0FlN>v}B{DtTPP%;Q^2hq>@mR-EAM}wgH`wbxKKVIFIe!b+V~|cy+g<0$z9CPYYi9eLIr_vNOiz?-HQed4e4jFqRECTG zO3v*53v#owv-5}M4H=dpYho4 z_p`U}j?Z`Y{r%0VoxYT+ovV_ncD3(NwQE(#=@U2W?6R#g?AozgcYmF?cAWhC@L59M z-*i^#*4>@g{{72ee@k7pb@#SKAI+W==X}56xKqp4$ZKEcojPufJLIV{?w&)=>VA+6 zJMOp>%9hGB<1=K6c`w^iOzJ*x)`Id!cRTq-oI7q_**ICNc%Q6k_SW57^Io#0ZJt#$?h#qm+h^&&Kf3=8oUPAU zpMoFS_FOc3e_f-DTW9OP-@E_j&(Y_TN*~?5Io$TJp0h6X{jt4j*TWO*%Ie3}mrfY_ zS)?!S45kCM4MzDIX&b?3an_t=l4X8h*PegCrk$Bif*VRIJ?{2w*SIyZha zTdo1VzjxL69z)7Pm0nwJ&U?*T!Ev|C6Ee-dB@cYQbF~xB9F^KJEn5Yay=9eiiZg82 zg9Qm!kNx$>XFq(k=79E7`pTPv!(RP)?7MBQzT~K^cdnW_?5UfpNBMlKHu-(4BFSSv zzo_lJrr+;hHg^4%RR4z3Z6`I>e7paa%6qqee^2+b-#&He&8u&_`@zt~&vaiuapufm zX7cA(UX*ujsQ<87wb24>wo$+=e*s0!Me*&%6cad zN_2`-);c%L`)f;8#>*F8zHVKQ1(zItNqi{Y*|)6UzdG65b+Y$=I+~`PNkhZ+j^$R+_&VfoBc-oAKSAkCVZAv z)_z?3(hl}&z+QbzUX4_Y`OJCfeQjT9Z*8{^Z{5*0W5v8n7R>CO=1=Z0q}QgbqP%J4 zZymSgxjEB*-g5PGsdejvzg}EZ(&fULpFWh)94C!5J^zNhQTLsCdBKJ&kNP!bzrr@c zw#&KOJ66a04v_v{%0*orM}Ort_7UexI8sh3alX(JIj+XV1QaiPEtg`waKN%8Rk{cb>9d@x=nLfBt@L z3uJJAW48R0*RD>U2lQN-P$p-wV7#7&+wIhUd|rA;C4CI#|e~?f<A^~A)TUs^Uh=bu!PjJJPX|AfWqu|Y3CJz?;50dFJr|6~ z`aU1LRfc>abhETZKVRq+S*#pi=xiCPzb}+8EuQNOT_sDF=L@Znvep;+PR2Uh7fO>w zS?3EKDQ&mj7rI`W>s(*xaY^UN2(ppS_l0hesa)U-eI_fv!51o**Dmyhe6mOv`9ecv zt#6Ul3-uO*e)ffC%iMqQg@(!qyM3WoWWgrIg?^DOyd^GljV$u#{?Kq)h%fx1 z6>{nHr9X6mO!F&$Xt$)V{h?c=UB2;$ili~V^@r9-YkcPq{VD6P(;xE79KQF5N@afK z@u6aAql);@P+98A_|P%3^{e7T{bXX*@u6gy%J}%uBQn35_|SV&YU4vaWDa%lp>!Fc zK0Z_;j!uXV-7MR7Vtgn?1e+8e8Yo^)jt|`^6PpqrlAkVh4vG&=lFfE-e5jqcb4z?^ zi7Z6BKxi*%x=0{&mn_7xK&V1mX?Y+Nl+C#!5V}I(+kwypGEF)3bd-jCHxPP4M0+m~ z>MX1BejxOvtiuO^&?(YN9|l6xWm&cbLpx;1mx7_!Wb~JVA?>Wb5)Az;n|ymP^o}gj ztHIC|*~G5}L(d7^AtT5dy&ep0khEA5ny(c;JoHX6N$)PnevHOxk+hh*+Cx@nq zwwuyJr;A0GrH5w9!e5>qdRrFhiuBM~veKK=LtSN>SEh$%NrPOK9$F;nl(wPIWQ|U3 z8`>%)>F&@cG+WkoVOFT4EX$&-(EhSyi?c$X$ZVUlLT|~COR_>6q_LJ}h1SSw z9+4HgQRZ-DRwyFdVOdt_JZZt@Ss{J1Xhl}&CE3JBWrb$Qa<0q@T`cQxbXI7a_;O5E z=y@6a*sRc@(vYjNLUUyf$7O|%lZ6V>X70q$R2!3;ijtjejgON6KMehU#PvjbDcT2UT|+CUx2WeRyVPzsxQy zu>-QJBBEj;C}E3=jf!1}C?a5DVvB)|qN3P|Vs|HYcXzj9x8Bz8x}4AX9LMv|ea!pi zeaWzUx;wSA>!+)`!GXF$B7I7m zXQco0lzgFE`u7}}FN{zBF&>pKoV;Lq`__En{`7f0CSO=D{l|1{zVKqYF305yQ_@H6 z)bzMS^QY-=d|JNHmagrL|1P8t;pzFp7wPYPM!xV|`nVr7E?sCzSM1YJMX95smr6d+EbiGRQ=FD#Zm-1&P_bAEgD?)k!R=@0FZFC3o!%5&ulKc_z{U+d=H>C=}US}Qe= zOIN-jU$`&*5&7k6&EwL4MUDAF`WU3YMY@n*h0q~in3?`w`Ty0tX4014QM}Z=Y5IUS zUGIwk$j!1SSOnVc@npS}ln_&0q-J2&RurLkC~SUFkf zy86IUv1t4jt@+a&R4NvW**nd_rDE}z^QAeYRP>A4E6t@##S$^+O>>!2(Ld%qX)aqT z2E?2@&E-nPk}=!UT)tE+6|*hP71Hk-j@dKKLFsA@ial4}>3R*0-6QXG#fHT0o_D%t zOUJI|ovzw4v0L*_*KOI@-SSRXZn@Z9^G?@p`Pg0ZPFHV**q!rE*KftxEol!<*KeiR zo$^lCZ)og}d8g~Qa_r{3)Ad^=c2nNz`mGwfns>T>!(w;HJ6*rkVi$R*>$iIB#=O(@ zTO)RQrQqs=)Ad_3c0<}j()C*_b~*2K{nn11KL6bsi@udH>GR(@K5;4*{_podwGL1J znHTF+SI+;vB_ZnL zxY&e@k4?yg*o5pDn~GR*ZX8H6*n~`pO~{e42{|e@AxFn1(l9`PH}o&$Tukzw^y^AEadLu z(R8EfKOy(T(GW5_W(c`AW(c`2W(c`IW(av8W(avOW(avGW(avWW(avCCLxc;Cgic$ zgghRbkSAgj@?>m6o{CM#)3FJ8CN?3@#wO&s*n~VEn~)b`6Y^qgLSBkZ$jh+_c_lU> zuf`_iwb+Eb9-ELiViWRaY(n0OT^Dj^<@5CUZ=I5E#1?neg-l8}?~AvqSxy%6e(`y_ zb^o7`58`MD`7mY(`6y-x`8Z|>`6Olt`7~w-`7CA#`8;L_`66Zr`7$OUb7B+nRcu1O zj!nonu?hJ$HX+}|Cgl6rg!~YjkRM|c@>6U=evVDZFR=;vH8vr?#U|wU*o6EMn~?v- zCgji9g!~nokiTOS@=t6+{*7H1@@}PL!jXPIa#Hc$e?n@V^X2p?TBcL#-dHr2(;bm? zk1OAsDavtr{1KJ8-7D>Mv%J}!H|=z@yrVr&+UaI_CwuO+ z)6Mc0yFKl6v%It2mUg;X-o@^jcD`TJRY*Ue^WPntZbFY7(p78~y62FtV@;^#kgjBR zp*4qeEqe&va!6NmE}?4<>3a4Qy5x|qXq(VEhjdNbg_acZJ)F6PPC2BHi9MUzN zS7^>5UDIAdQx55x&L>oJNY}Kt&>@F(P3ISi9MU!IBQ)lauIU0oC5LoP7Ze&&$oF*? z63RKGYuZ;xK;~*J8p@T86Oh^>`7TbSTvzl+Rv(N=aS8fjCswLsA*fud~$ibe|*Z7Wc;oj}nTfuijNipB~Q?I2JzPM~PK zK+yz&q8$Z_b`mJsS)gbafudanigptynkZ1TyFk$%LS4~_a^;-_q}DqwWM2^1YKP&8Gb=mdeH69tN<2^5_q zP;|0D(J2B&(*=r76(~AQplF6rSG0GzvS9jVR=YgkaNZ{r(GvniPYM)0B~bLVK+!V-Mb8QpJtt7~yg<B~bLXK+!t_MehoAMfa2|*C!yg z(HYKcw~Nx#WW{^sYW9^CeN--STwa7CRJmwnI@DI}~-bLs2(76t&tE)dY&V z3l#MbD4I*4sHZ?tn?O;!K+)U+Me_(0%_~sUOQ2{zfui05Me_?3^${pqK%i(rfue;3 ziuwu^EiCw2w1_~_qC#C!(NI}20jUj1Ply*C8tV7-FHf&GC>Cp|W?xxR|Au0l#X`{l z=R?twb|_lP4n+g)P&CL6MT6~7G{g=?OWUDn89Nj$Yg4qGK+*C7MJosttte2ml0eZ= zfufZKidGRQT2-KEm_X5L0!6C}6s;jpw5CAOS^`CD3lyy*P&8biXkCG#^#qF67bqGb z)D`t>s2q`i)SgVQVJVgfMaSo7E;eYWW?xy+CJn{K{X)^E&WEDS>`=719g4QFL(!IY zDB8*nMI-G{w6z_IM%kfg8=Ioh0!7;j6m2I^G)ACkdx4^{0!2Fr6pa%o8ZS^ZL7-?y zfufxRigp$#+C`vfSAnA41d1jK6zwihw1+^^o&rUC2^8%u)D>;iP0j zMGg7e+dd7|>?B~bLXK+!t_Mehm}y(dugzCh6jLS4~)4VAMK zklKyurKH9Ep=hOatGf8Gp_+YVMV~elcMS`?TT9g4oT zL(w;ODEih8Mc>&JeJ@b-gFw-b0!2Rw6#Xnv^ou~zuL4EC2^9SlQ4gDo6txQ!%`H$gk3iA90!6(9isln2>Mc+-zd%tRfuaQjiWU?oT1cR%uRzhl0!51m z6fG)Hw3tBA;sQnegu0@pN~Q0zNzwQDA)@9={hoeHLmEp|s@Ydov{a>7Yxz(#(D_g_ z$PPt=?NBtt4n<4bp=cR96fJ9qqUG#Rw7eaPRwUq2o#MIC>k$NG(n(fM}eZ91d4VRDB4A!Xjg%v z-2{pz3KZ=wP_&0Y(VhZDdkGZnEl{+NK+zLqStwd5KLoj7 zrJ8+ZMF&-i7l($TgPjjWhuEQLvK@*JwL{Tib|^aB4n;@Up=gR7ijK5H(NQ)2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=OEl_l?K+%0dUD5fK z%FqO)c42-t_JUA!V0sp|xW7`(zOtf+E5){}g`!8C4@HmKq3AI?6g_T-q9^Q7^rRh% zp0Y#H({?C&#tuc#+7vw}Q1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(Uofx`>HdhoYJtin`mOsD~Yj=CVUkPdgN~*%Y-46wNJAG><^hyaGkN1d8Sp zDC#XxG`~PmAAzC;1d0|EC|XFMsINfL!U9E$2ox9TfGG(G)fa?#RQzo$Pj|6J;ljn(WcD;k{c><`=749g0@4L(z(MC|b!5MMG_hRu(8)MWAR^fudmoMXL!Etu9cshCtDp0!3>H6s;{# zw2na0aDk$A1&Y=aC|X~jXoNt~1_DJJ3KVT5P_(f?(Ix^#n+kPB0~;%wCm^*Q@;&`Q zq3EsjO4(ww#%lJJ6>Zg6?6+Ph8tHr}+S(39qwG+$jU9?c+o5P%I}~kahoUidDB9i* zMPqG>b`U5UCr~tAplE_X(T)N|I|&r+EKszIK+&!OMY{n0YY8T7LAp26Oh`G`3Citp=gmz>cGZo_LUV)ZY=H@ z5sD6VJ`^2hhoZynP;`VHil*41=tw&h9c722qwP?1j2()OwJADIpy+skqNxH!CkPas zC{Q#_py(ulqLT%RP7x@YE>Lu;K+$OeMKc77P8TRTL!jtPfugenip~}&I!B=BT!EtV z1d7fV>WU6-tbCAw)c#1bI3yH3lNDXiSk1n&qKg}g@`-*M z9g427L(!FXD7wlHMOWLQ=o*`%YXyp~6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7q zx?P~?4uPUO1&ZzxD7ssq=pKQh*#brP3KZQZP;|dQ(E|cS4+?cf7d2KENkD3Ul3`u|v_bb|`wz4n@z~ zq38vhq89~x6DWFL zpy&gEq7Ma%J`yPUSfJ<=fuc_ZiarzSiXLgKOiVy(x96KekA|YfThjQvv6_8lMPD@* zCv6srzIHwoePf5BZ|zX@ogIq4w?oknb}0JM4n;rNq3CBj6#ZgT^s7M8ZvsWX3l#k! zQ1m~6qCW+S{t_tqTcGG4fuer}iqel|pO-$sjb)0;0!0l1MHPXfMuDP2ps0gDQB|O* zNua1%ps1rjQ756U=*z~+%?U_tTzMU;DC#9pG@n3GZ-Juu1&aCz6fGc7w4gxI zLIOp71&S6HC|X3IXi?b|~7x4n^baP&D4AXo5h|jsitH z2^8%tP_&Cc(XIkTy9pFc6e!wVplA<)qCEwQ_7W)CTcBtkfuczQMf(aA?I%#Qzd+Fe z0!0T36dfc`bg)oYG_t51oq*H^=GR?s9g2phxB4s&DXQ65R&;n#TsArs9pQW^nqr5d zBkfRhlpTtWwnNb|b|^a54n@b=q3C!!6iu}$Izgc5M1i7d0!1eY6rC(kbc#UHbb+E% z1&U4+D4HQqbh<#%83ILT3KX3sP;|CH(K!M|=L!^^Cs1_0K+y#PMHdPbT_n^M9a>bL zN`-*29g429L($cCD7wZD zMc3M)=sG(TU2ju#gFw-Z0!23o6x}RPbc;aItpY{22^8HfP;`et(VYTCcL@~TEl_li zK+$Z0qI(63?h`1wU!dp#fuaWmiXIXudRU<75uvW=lA_XWOj5LIhBGS^HRWeO9xbZb zS61|7Q4AUzik@;l6g_Q+qG#+-^sF6QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?(2^4)SQ1ppF(We4M zp9vIwE>QG^K+%^%UD4x3Wy=JlwtTMy=ZR2ME~hc4sAgYT(YHl$z_?KKo%5mSdpi{U zV27d~?NIcS9g2RoL(wmGDEie7MZejh=y#iYCs6dKK+#_UMSlwv{UcEHuRu|$ zL)>krs4P&_AW&2hC~6caDg=r;2ozNXikbw9ngxnF3KVq`C~6TX>MT&yMW`$Kx~QC= zfYfH^hpWE{Mfc=e*IheQv#+eEdxzrQ38AQm^Py-iI~4V_Ls6R@irVc^G`Ag!=CMQ3 zymlz+Wrw2qY>Ijd6wNPC)JLFb0fC|g1&S6DDC#Rvw6H+YA_7H=3KT6SP_(!}Q9psA zB?OB43lt3yC|XjWXeoiBfdWN?1d0X=6b%vTids8VK1x7pTlYzDY8~qL^hf0HXiImf zW?xy+@*RrG&Y@@p=R?tob|_lO4n;%lP_(igidL~h(W-VR8fJ&0)$CBTx=qm<0!3>I z6s;vtw6;LeIs!$*1&Y=cC|XaTXnldA5duXU2o!B7P_&Ui(Z&Krn+OzbDp0hUK+)y` zMOz3IZ7EQ+l|a!*p{{7z4wc0cklJ(ko7i%pXik0za_bJ&>?=wN}OLj;N@3ltqH)D>;h zp|VE;QoFTlf-^c4<+tA}4(m|OzOtetI~1o(3`IvdABv8)L(wsIC_2^-MaS8p=y*F6 zO|?VO33ezt(GEq^Y>G}2C^}i7=oEpX=>kQk3KX3tP&7lJ=yZXiGX#px6ev1Npy+IY zqH_d_&J`#+PoU_0fuaipiY^o=x=5gCra;lf0!5bybwx*XsN9->)c(kC@GvD5<=>E4 z%<53hzOte#Iux(&5sI#KJ``PLhoY?QEV$fYgr6&!asZijJD z+9CglW35`vzOtg8)#8f%LQ$LZp{U&sMRVJsXdXKh&1;9EUUn#&&kjYs?NBto9g6zc z6fGc7w4gxILIOp71&S6HC|X3IXipxTQ2>M)8s2FTB%xm zb3iB>>U=0#*$zdk*r8}uI}{DGL(yt>C|cbPMQhlhXiYm5tz}cRwm{K30!70Giq;h< zT2G*8eSxA80!14L6m2L_w2?s3#sWo~2o!B9P_&sq(dGh0TL=_wDNwYPK+#BnqOApr zMhO&cBh(eGP_5JsOp3nC&*`riiXP62MpvuZS5~xrwHR`6C>ra0DB8geMdR#HG~NzH z6YNm5qaBLUZ*;D|bSo6?Y=@#<>`=6;P0?-wMH2;zb{8nxL!f9+fug+xiuM*L+DD*h zl0ebE0!8}?6zwlibbvt7fdWMb2^1YHP;`hu(PV+5Lj{Ts6DT@dpy&vpu4ubzWn=+b}3lv=- zP;{X{(M1A9GX;t+7AU$zplFsr(WL@KmkD)6M^!5qCLpyr`5~gCLs2b1c71uZntf$O zS67Ss({FhG?|mJwaXu7XYloui>`-*Q9g1$SL(z?PD7wiGMK{}_=oUK^-D*>Gn?TX+ z0!4QS6x}IMbeBNU-2z4T2o%j0D7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRG{cF zfuhF+ik=WCdQzb1DWR_D%4+441f=$4e)axUq3FH*c+u0Iyn2^768Q1p&K(Ypdg?+FyWFHrP> zK+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mtmjXp|1d6^ADEeBU=o^8eZv~3J6Y7ed ztycOaAhlJxCpgcAqHpF&vEKt-%ps1@rQ8$62R)M0LKv8#rq8>tB(T~;2UI|F8u|2{0DHQFRpWvUX zshWLdMRPY5rydiE=5an0&1;9EUUn#&&kjYs?NBto9g6zcp=bd+6fJ0nqJ?aV`U(^+ zEKszFK+&QCMT-d(EiO>hPoQWCfujBbMFRwimJ}#jN}y<o+q>i6_}wxqFQQ#Jd_idJbVUOz4rt?GOz z8fJ&0)$CBTx*dwvutU+Bb|_lQ4n=F*p=cdD6b-j2T34WGJ%OV21&T%p6m1|-w4p%J zMgm0}3lwc4P_(H)(Pjcgn+p_eAyBlXK+#qLMI!}@wiYNFB~Y}DK+$M{qHP6=wiD`# zhBj6HN5GZ<5py(-qqNfFlo)IW|R;Vkw zrm6B=0#e(iDZ#lm6upvvtmwI>YW9^Cz0_2EH$4=+?0hJC#STTU+M(z*I~2WchoU#^ zQ1qr9ir%tA(c5+?ddH^dU4f$a1d84lDEdI4=tF^`j|7T77AX2epy*S9qR#}1J{KtZ zLZIkNfucDAMPCUNeJxP*jX=@20!7~m6n!sH^n*ark3wD13r&?CrzS`?T#9g6<3L(#u>C@M9_{q|5) zwkc{5D5?k)H3}3J0!1AJimC!dO#(&D0!1AKiaH4twFne-7AWc>P}EhRsGC4ht3Xjr zps2e*Q4fKlxde)O3KX>obw$54RYoNswTt>BIKPIXarx(6wT*+ zDC%v8qWSGm)W;4*3)rD(K|2&JWQU@@b|_ld4n>RD6fG)Hw3tBA;sQne1d5grDC#dz zG(ezeNr9rJ1d0X<6b%w68Z1yWM4)JCfudyuik1~9T27#7d4Zx81d3J^C|XINXsA$E zG*5G7W&%>{ncr@I-sbu}{moj_Sh=~HePuc08g7T8b?s2Jo*jzTw<#JSP_%(S(S`y=8wnI`EKszGK+&cGMVko}Z7xu>g+S4k z0!3R16pa)p+FGD!lt9ro0!5<*inbLf+D@Qoj6l)$0!3qmx}sH^E1xAGwa4=}v0qFwAzw5uJ8cC$m#L^~AiZik{h>`=6)9g6m{ zDcW10Xdi*1NdiUt3KZ=pP_(~5(E$QQ2MQD&Bv5p)K+z!rMUw@J4izXmOrYp+fubV> zilzt@9Vt+Blt9tZ0!7CN6dfzn6^(DM^iM!)hvs)Go)C&|&EL_EYp!NrS<#8j#Rlhx zqG`^DqLb`Ubg~_aPO(GLbUPHCYKNlJ>`*kr4n?Qiq38^oqB8}G&Jrj(TcGG1fueH- zip~=#I$xmZ0)e6n1&S^bD4Hoybg@9uB?3jW1d1*dD7s9b=yHLgD+G$J6ezk%py+CW zqHBb@qN&Z5eG-t`TKR{EP6$PR=kI9OHdnK+tmww(V#bA`=qBew(am-!y2TDfx7wlT zHaisEZik{f>`-*49g6O5GZ<5py(-qqNfFlo)IW|R-ouPfuiRHie3=vimq?2+?jyXs`+)- zH-w@s^D9GMY_4WsS<$P_#hWuj(QD3!qSx(E^oAXZ-n2u}TXraV+YUwV*rDiMI~2WV zhobjwiaro1`cRB?XF>5-1udP&7!OXs|%h z5P_nl1&WptC|XvaXgPtRD{q@Pyg0DhIOoFUs=(b9gAzO2t{i-ABxttL(w{RC>m~uqIK<1w4NP`*0)2^2s;#Q zV27d&ZHhJ$DB4({XcK{=O$CZJ6DZnTplAz$qAdlAwh|~BDNwYvK+!0HqHP3jl?O}(aJ?&7mmmP}swnNcAb|{);Q?#!@(S8C&`wJ8u zAW(FmK+!=0MF$HM9U@RPS)k}pfuh3%iVhbjIzpgmia^nk0!2p&6df&4bc{gJu>wWM z2^1YKP&8GjE83}JrRUX2QTJX6&d#A|_xv*;Cv>c4Us=(~9gF3z4MnFoABv{iq3BdQ z6rE;=q8WB5I^7OMXV{_WOgj{vWrw1(ZHmqjC^}c5=sba<^97175GcA(py(ojqL~6k z7Yh_!B2Y9-py*P8qRRw|E*B`eLZIkMfugGfimnzYx<;VrT7jbL1d6T~>WZdytc*@T zYL)!D>ytv!!udwh4IQi5S5|aO$KufIL(#3yhoal;P;|Q;iteyO(VccEy2}nlciW-p z9y=7xwnNdqHbwUd6x}aS^ngIog91el2^2jnQ1pmE(W3%Ij|mh#E>QG@K+%%|MNbJ7 zJuOi5j6l(|0!7aW6g@9c^nyUqivmS22^767)D_*-v2sZQQrkb@xxYCS9g-Ej(y^L- zWkqjvEFQiw6us$uD0<5dMQ_`o=p8#0y=#Y}_v}#gz8#7_utU*@b}0JDrs!jVqE7^h zJ{2hXOrYpLO6o zRiLPwKvAneQB9zzyFgJ7fugwtih2qZwFwlp3lz;QP&AJ~(Yyjhy#$Kp6Y7fo>{wYc z0jVv%P=fQ9uSNO6qu!mW*;iJyV5efE+d|Po&WEDDb|_ld4n>RDp=eP%6fI_lqQ&h{ z)Xxq@OW2{PzfI8qfubb^ik1>68YoaSNT6u2K+zC^qNN3jmJujgR-kA(fuiLFidGOP zT2Y{AC4r)$0!1qe6s;mqw5mYSFoB}g1d3J{>Wcbws_dJ9)UN20;4ILoeow!gNv+YT zntf$O>vSs4xFZw|cRm!YYlous>`=769g0TSp=bj;6m4jSqK)iOw6PtEHnAz%RG?@x zfuhX?inb6a+ESosD}kbs0!3R36pa!n+D4#gv_R3e0!7;i6paxm+Fqb&tU%EY0!8Bl zipC2RO%N#BQJ`oip{{7HPL;b8kXpa|Z0y>h=+~@h=T6n^D=V7Vsd)RYP_(=Ap=b{~ z6zyq;qP^@;w6`6K_OV0JBs&!CYlou!>`=77P0;}YMF$EL9VAe6ut3ov0!5PriVhVh zI!vJGaDk#D1d65z6dfs0bd*5R(E>%s2oxPFP;{I?(eVOBQw54n5GXoPplF&!bt{sZbvne`Xpy&dDq6-CzE)po3DNuB=K+z=vMY9BoE)^)cOrYp;fubt} zimntWx=NtvYJs9_1d6T|D7sFd=z4*o8w84O6ezk$s4F_9Q)TT0q;_+@K|MVbt($Kb z-Q1~~ePuop4n=p_q3CWq6y0NoqS^MLXm#Os{vUW?xy++ntK*9tcJ6 zI3J4MwL{T+b|`w^4n-f>q3A<96n$ieqL1xR^obpcKD8f@Xl^-wqHx#vH zQVX zqEP}x+Xxhm7AV?QplCaRqA>zR+Y1zp6)4(4plF;x(RhKP2?9ks3KZ=mP_(l^(Jlf- zy9#wh!&@qsCLpzA^7~z{8;VZOKO4JSOEvq-iuPiY~B2 z(Sgrc$esoC3Fs@YdobXQBU z$#bFTZs$YMJ$5LXZHJ5 zMV;(W)MAIC&Nf9|1d6%}6m=6QY85D|2^4h~DC!|lG?ze8Pl2K~fueSSqPYc%<`F2G zSD>huK+${xMZE=z<`*dHBT%$}K+%E%MGFaaMdi+whL@9~b@NND8#>qTqjk)`3B7OU zYW9^CE!MeM=+#iPxbyL~sGl8*mas!ne>)TnutU+3b|_lP4n+g)P&CL6MT2dMh6ofb zEl{+KK+&=SMau~kEiX{CfLu;K+$PJUC~~hE3YIVwSoD|&)%Wv_s(g| z=v>XdvZAv(7r(q6iq3XE6rE#-qI2y~beA#eQ}fFk zKL|xV^3x#=U8>nvR@9+O@%TrfsOo$uYO+I7vmJ^$+M%eE9g14)P}JEDMP2Mr)YT3} z-E4|l1&V3{McoC8dI%KFB~a8;pr}ots9m6FZh@kC1d8SrDC#9pG@n3GZ-Juu1&aCz z6fGc7w4gxILIOp71&S6HC|X3QD{Aag`8olq4a+yEi!Swh`WxrB3SG2IHT%knmgrJ+ z{xlTzcRmyiutU+3b|_lP4n+g)P&CL6MT6~7G{g=?OWUDn8JnVI1&WpvC|X{iXa#|y z6$Oe`5-1ufP_(i@(JBH(s|pki6DV3uplEf0qBR7H))XjOOQ2|NfueN;iiQgmtt(Kp zov(N=aS8fk~3t?f`W%BE-=fuhj@McWD#Z6{DPMxbbWfugYjMLP%-jT0yu zFHkf=plC;dqMZbab`~hwMWAR`fuh|6iY5va?JiKXhd|Mu0!4cXbwwL?sT`Pq)Naf# zZ`>#pbWU_Hsoa-<)H>yFV*7@o_y4=Y)}@+#Wku(9 zDc=7o6rJaMC_3K`MHkqi=t4UbU1W!%nRY0;*bYUP*r8~a9f~fsDY{Ic=yHLgD+G$J z6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCc=yrjkI|PdE z6ezk&py+O)uITJ8mBz1=qNDQbuFnZYYc`~DPnT-;l@;CJrC9jeQ1pQFq3A(76g^~z zqKEBJ^oSjb9<@W!V|FNd+zv%g*rDi2o1&)#ik=oIdPbn=S%ISG1d5&)D0)Gl=tY5| zmjsGl7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84l>Wc2|Qdutn zsWtRTaPA95qbg~9(50GvWksKKDR%ol6n*M^DEiC}MW5TD=nFd(eQAfHId&-e$__ohxvQ~7h zW?xxRbJyagA45?`=R;8^I~29pp{TPRin`dLsH+`{y4j(q)ec29I}~-dDe56mG?ze8 zPl2K~fueSSqPYc%<`F2GSD>huK+${xMZE=z<`*dHBT%$}K+%E%MGFZO^%W>uSfFST zfucnPiWU%U7%Wcbz zt@QdODf&J?=`kP_{g`iEZ`8G#ePuwUq2o#MIC>k$NG(n(fM}eZ91d4VRDB4A! zXjg%v-2{pz3KZ=wP_&0Y(VhZDdkGZnEl{+NK+zwWM2^1YKP&8Gb=mdeH69tN<2^5_qP;|0D(J2B&(*=r76(~AQplF6b z(dhz3X9yIXDNuBlK+)MkUD5tsD_15UwZZwD*a4wv@!n~i)3us?WknZsEuQ={6kX_i zD7wfFMKkSCbg>`-*M9g427DY{ai=qiDts|AX#5h%J=py)b* zqU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h$81P;{?Q zS9D(2%C`wfZE%{!`JrfbzL9ia*J}2a6+P6o==x76df53;^oSjb9<@W!V|FNd+zv%g z*rDi2I}|--hoYzLQ1pyV(X#?Y&j}PgFHrP?K+%f=MK1{yy)01lia^n;0!6P06umA` z^oBsun*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ-uMGthXES-SVF3!)RJs65w z@{OdAyH>NWtmyNu#TKRfFBn)VzHmMieQAfHId&-e$__L(vL$C|c1DMJw494HYO_S)gbYfudCfiiQakttL>kxI z6s;vtw6;LeIs!$*1&Y=cC|XaTXnldA5duXU2o!B7P_&Ui(Z&Krn+SD9OLePsD3YRa z`FXT~p=elsHg?l))$A)P+Ok`*Xf+gV<$Nd_X@{b%?NBtz4n^D8p=h)ning^w(ROwy z8e@l|?QM$23KZ=iP&7`UXuLqt1c9O*1&VeODB4+|XcvK^T?LAE6DXP}P_(;1(H;Ut zdkPfoB~Y}tK+!$|MUw=I_7y1FPoQXjp{{82Zj})UNUd*vh-iyY^h_;{1G-hSudL{h zZpH4+p=h%6q3BRM6dh)VqQmV_bc7v>rr4qANIMiAWrw1p?ND@#P0_IeMaKyg9WPKc zRiNkufua)yilzw^og`3nvOv)(0!7mWicS?MI!&NxhCtEj0!3#C6rCwhbe2HT*#br9 z2o#+wP;{P9S9DOf%4rEm?e#th&cUH*|NP+5`Q577S5`E$TX9RLP;{~Lq39Aj6wR_j z(WQ1My37tmm)oJ}3Of{CX@{b#>`-*IP0=+1Mb`=xT_;d=na9QHwB8`5-56Gpy(Ze zqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>ng}S1LyH$F3Ns6A&4-q{QicZYW#(vhV zntf$ObGj9)b_+#cIUkC?wnNc3b}0JR4n^PDq3C-%6#Za_q95&0^phQmezqz4MWES2eXx$IEX(+)*#b|`AML($weMe_(0%_~sUOQ2{zfui05Me_?3^${pq zK%i(rfue;3iuwu^Ei6#9h(OVz0!51n6fG`L)K8#j34x;i0!0G^ik1{8T1u!Z>fBnn zIsvI&Q6xBBTI=`p2jxc{2ewwTudHb4*5c_Np=cTBL(#H!C|b@AMa$cvXazeIt!Rg$ zmF!S7)DA@}+o5O`o1#?(iiQakttL>kxI6s;vtw6;LeIs!$*1&Y=cC|XaT zXnldA5duXU2o!B7P_&Ui(Z&Krn+OzbDp0hUK+)zxUD4py%J&IKZMl5sen==P=WlOY zv{tjPtZ3`jqO~m)jdDH|ZDWU`(RL`>)(%D6*`a8R9g4QML(y0}6zyP#qH#7w;{}Q) z2o&uoP_&ak(ar)zy9gBRDp0hWK+!~jqTL0G_7EuAQ=n)sfug+yiuMsGnj}!PuRzg$ z0!8}^6dfQ?bf7@dK|)>8R;`s~6Oh^+`PTKwP;}1%X&l^I&Azgt!&-~2<_<-NJ0FUU zutU)lI}{yhhoYnGP;|5%ijJ{E(XnK+zcjMP~{Woh49owm{K20!8Nv6rCqfbiP2*1p-AE3Ux)3 zTPu?jklLJTf^%pndOwegTC3StRy3=%xM1E;bgA>9=rTJLU2cb>E9_8or5%c{vP03; zb||{W4n^16q3AlBqU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bx zy9J8w5h$81P;{?A(R~6%_X`v~AW-z6K+!`2MGp&gMHjbL9!fxJeOeNnOG44a{6O|2 zt<~%+D|(`}_;|ih^rZ8l=qWoCJ#B}gXY5e)tR0G;vqRDIb|`wm4n;58q39)>qL&4V zUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_XUbR5GeXkpy(rkqK^fN zJ`pJTRG{cHfuhd^ioOu)iXLmNH1$r3KFQCkeZ7fimpjqV4TaG}aD9JJ_LUoE?hB+o5QJ9g23eDcVV(XlH?DSD{bUoN$+oNjfO+Qy`}qit-PlAa}LYMYh55w^5Fnr>8eYx_KX zIqT83M9)&Gy>0J=vRB(3=_Y%hw!hP@tiEk)q~B1pSliSEN~Qj7&!?wb2DZ($NU5}R z+ct}pO3Sxh+^QfXM*fTc>MHQOc)DwT$}-8H0C8qxOeGNsbSZEG!GDsA3& z;)!{-o0LjNw4JnBsdRMP%UhI6$G6QrvQ(PZHfB_*G`;Pz(WTPqZC`Cy zDxKXnXl$u;e%k@#N~M`?_f9C4E^VvqTq<4Jw(hQ_(zR`;Oe~ddY_s&$QitSgG_vTQQ|ndZlgsqe`VW z+D<*DRC=fF_2WvV58CECp;Y>$ZQQg{>5I0jPA-+cZu@R}sq}r@GBZl0pW6;Oqg496 z?ZLB3rN7#%=cbQ;xqXB4(s`P0nw=Z{X`aG1|^KY~7TW-(4j(o9ld;WdW{mbq77Xl9~x98vJx^%fc|4Po~ z%kBAhDh@5T=U<99tlXY|tJ#|6_WWz9hL_v(?-d$RZqL6MX5(^u{>>hnm)rBNW*Av+ z&+n~2y4;@M9DVz8dwzH8@#XgX_QX4v+w=R&PAs?QHwfLU+@9azao=)#ev7^X%kB9+ z)+U$R^P6NHQEt!ga&&aLJ-~z za(jOC>yvVOe)!^xa(ll2`E|KH-+}l)=H3Fjjk686l`M_rSPnBolQxAUb~tU)#xW#r zOfdvXZkjmIh8id{Gcz+YGo;MS%*@Q^eP^C6%jy3gSohp@uhvRmJzMk5jAr(HGv7#Z zzm50sE5IM)J^U2@YrKc|!GFeM`5W7T5?mA=ay?J5V<&fX#{sEWtk=EvtE>2^bZ2|+ zk45%DcKocp3gfZfx90mR!^YVwcIPB~^j>1eUVPM4XSGJA*uOq|_ck`B-LXDJpNZ`( zj8!P{Fiv5P9iH*=?My` zxk56>!WIhU)&ayPN1^XYwlIG)Zw!ma`o(L5f*S4;&r(lFFpRF zbNB5RuMY~Ic>krkSYISM;F`L*m}>c`+Boj-#V?t zrCBR6Uo(1x86A4nRrl=^uEj~S7A_3eBJb?S2Zn2L=tpn=v}dgUB5QM`SxNdH?!XI>-9oU`_6}CVd}Q+nyFop4^TfeEGxOz8ivq{qK5m$FT8r4`2U!v=;`S z*WGse`_|@ho4zt?6BK-WZ^u<(lk&c2L>oNy+u6}Jd-BX@FW5acAZCZ0HwpdxtzgrV zaPs2QFE+)@&-;G7`21h)FFCmbFR?SH|I7Wgv;(}{My+ckFY z81K+M7RwnNOQ$zC6pJOg#S-l{O>dT-kgn)#Cjz}6Pqf=Sowk>w$>Ii6 zL#9*;D^mv=RL-$rwb+oCn*0+4tW~r&VS)-t3J-WBG z74;?e2%p${>p41WnOpRnXdPIu;qfhcvLYMwtmxb^-YIu-k5i}g^yT&rvKr)czjcaj z^FG-#@lDtF@B`wuZ;HaL)9;7_;<20_$4{}2uD`ty^B3$i%QU9Q@R%=pS-Wtlw(7Cg z54%9HlTxjhC(YMn?1y;mx&G{V`)4nB@e@JxLRQ#z@_BQYj99g3?#kv7E1Q=! zubR7RMDxg|Rjb#`U%Y(8>gCIq%v&^f@v>DT7S5a3G!l4y(6u3WyOZSz$l>Q~HNxl{R?WlatCUKZ9a zS+lCCu6S(K7k{{KXRUFNQC_I(kHNu$xD7Z0E3mNm_9UNCpflGRPCcVE%G zYWO0T*G!ndc-d+TrnvdnG;jIRrOTH!&0VqBn8{pUQr2W!WnM|hjalb`pNoB25sKMY zKbl~8ibD!{qPPv_f&i(cDe`^_? za=VNeQ5bX{5v-TkeL&D@pxWD_JB9Pi?HY9I>vPQQ5_AgRhApF0xD4J%%Ny%w>zFqn zXp@_0J2B{Hq0M?hx4xFWb+=8zC!K?C{r$;^Xaaj@-F-r4~4qjiop+J@R_VH|FgjSPBQqfPn;8x9V7_ffmfLGS+mC$q3i$)N4@ zpm&8gvh}nrKO&rg&AL|zgEocXT6eRR58sU5i*{-IXzhk*?ZP-*`iY1l@awjiXIDNt=|qxvxmq;J>d{x7_YQ z_YH%=8wB0m0^b?`c}|nGTGTK7#(%l-{ zz8F#%bn~}5P%FrGqW&+p*Z<~Q?Pd$e-m}dAf4Z*W`yUW(XW!q0|NZvebaqQ*e8B+I z%#WAewkLZH{69C|b?rSd6g+N6tIh2DeRAg7y#9Z2_}FT63EKAK04@xA`Qbgn52ek* zb?%UxxMSam)@|MwA0Boc@9Z-?IxYs=G11SqSL=Pcj$|E1`a3=-Zf$%64z>Qm7oaxk zCx%MQFb)X1jLaEk7bxZRwM}Jpbxjr3Gm9%LN}G!7rZ!fURX4iHl)K&Oo71d3R zEO>%euBg1#BqeooY8z_oEmu}H)z(y0H(NtU;u4PG0b#+;Z+Y*{r zKH4`}__S0?)Hjxtn5CK4C_AIEtg)=A+_qHarP|`UiiSCv=u%e|SI^O|Ynes3+v;oT z!!;;1t1~MwCR{%6LerHO+40d-UsGP*)N10Q39Y6sDXwm6s4K3nuc~MW=Ui7-TskLw zGgDd#TUTFfGYWULZD5JbGHdEfn(7;BY@3#uj@pOOwrMq!tm7&3hGkE2Ww_*~n%c7J z%xkDTrLJP?w1#TiqD}Q>4Gn%Qv*_}Y%IV?ijv5^uIb*^lh6^tQg$GlJOkwS-@p`ey zHeY6L6%}>m#Z6@;B~3+BDs-5av^o^SuBEi1cxqEkV?%9YL(|Nf$_6`rGPB@l@J_|M zAMd)dj?U7unH6?#C<_x=r({xGFP2MXhya+Qqfjon-f?;ajRV6EdCT$jkfvZAD=*AFfA z&MdR(ibiG*a68na1JI7Y`D>Og-90n!@Ng)rsc3!Juw?6ot7__ecX&S;&0=JDfGkhQ!IsxZnX@h8QtI`{0Jp{2(vD$DFS zf0|iMiD3KQj`2pF?rb$%Ca{H0sVlZqx)kyy+TO`NgltpM-B#Ar>mVMVS)lEPXbVo^ zNm;nVS1n$+ta<(byEU;gvpDy;rrc&{lC*TuEnPrKNlnu<>zXnR*fv!)rP12kSwHh) zNm*rOV`XujNj|lr-hB2`6>kKqIOd~uEVSm~TWr;7H`Y%HPuETL)9l(Ln$o&6I<~Au zR+U*-rHdAp#!OU;}{w6~+3W8IB*YEh9+S9bc&%$uXWu&H!LLsRLr=nUTa zbU!w0di7XU)+aUAg(s%4S1h+pQ$H=MKgQz9;yHfts57oTv(9S4nq~6}M~{kSr_oy5 zR+46HUuT=M|FbTCEA41#F@U8{Ev~96ZdtlHX;)Wl4m)PUg|-~mMMa?>Q>z;XluVc~ zz;7B3FB;&t4GYJQ96ey@%H}1_b5}KQIAGY)c`MdTnzwxA>gL^sEgdz=!0JV7mhND6 z!II^3R}Zs$j+3kxnD4-*T(Dx7F~e4^7&gCXtdY4Z=PjCKHz9W!KWypnrFI*0uc-GIm#~2ilgP21@EyeYNcxKU)29Eyml~Jz}i~BtBg5i-QUq4@8#{(fbbNTU@z(`HG@g zSVsP9U0R)@TV459*_@`-%+9uY?D&7RFR8Tift_K!zw(9JC8ztCIWCF{N9tWf)K^zYm5puVii1 z;zk>4+XY$n(AqDe*mRLUQ*D?MUD0G-2&MI_)|zVXAi~ph(f{;S9X>X0lRz!Qwbr9B zcQB(nD^g!u(WKF|?+-?Q#hJO;nSdGl1(23u*S30AWS9P#^~>4&`}?BaAQlcA}}KJsa~+fig!*S3IgK#>_$Faz(+vK50PN_laq-I`fv z%o|GJOPy-2XD(V=Mnk1KITqPKg12T{A+y$89%oA*8e9@?D%Qc*ZJm>MalPLr%iLkH zV<b6{~>*vh%I3v(#z{FP2CT)FWvaiDJVb?{` z_OM}D*7op|o{vqM>St9n*eh9QP{waXErb6e>zQM#7TJ|jW+d#RwQvD;QVyT^=*&Sh zhzeiII-u<8xn&FaP1*3yiC>l2-GZj6#TC)5I`b|w85_q&1&x(07aXoT*D%?as+k)$ zBe`MY<2p7JGxKYX*p6Y}=d0+$DkjMu1K5qwiW2KXtWR$Uw^L@SdKn&~GVa>vDi~10amGncgcuM3}bhDUOc!%XS^0Gl{Q+Z`^eM>uDZLD>(ee}x3E-a6(*~2n2I!(4(B~~EQS7$a@R`2EGK_+Ao zk?onYXZVh??`MW0{HK#|)D>rLfHB|ja~2MLpzqeY#;6>)vPU z(FRvH;eu@kWY#@A_Uxq9P+aGigLZt_rN@6e2D5Ix>RlB@_f37a(fEngvpe^?dI_&A zxOpEgKdX0^%+cje=Jul<$y~EYHa?Rpitd_*v+Sc;+?OJ`d4U}8SpS9Z2_K6NE-Y3U~i)|nDu6su^yk06V_KT7Kn_rpZ z8+XxHrPf^+R>I$7)~LnKv)Z50dB|Umh8N7BHo9iF`+Kd;v|cI$N~%g*4P5QW!jg^N9b!8x+%v7m5-qc^k4CxlW1Shz)i>7Lr(GIN|LaDl-{V~8 zCOPa|Qs(sgHa=W{97dn~ehWtpwY zwutVUW_?j08j^$?C;LJ-96Qdk4}bmR?;3rc%PK`T?)}5Rbx$~cBK42U=^**Im6lT~ zi>s$wmr-VS*w(oU^S83@ic{-+T)xicZ8bJ^pTgt7$570K zRVyhju`ONR6kce=eDQqQfnk-KrDHOC3>E2;b=~8mwWuTXJB_}%qAr3ZhG(Vv|Mu~x zwj8UKxh9LoKH=W<8dSl9Eja4E0<8#VeN%C|kNi^ZfbtSzZHQH4Z-w z;48!%{`b!Y{9Duo_U|8i*!RfyYFE%UHo&1C{>|!=b^{K|J2-Vn?xDe9$-@&zygO(`YD2mnEl)$>ye1H{(5~PX1|fjdL&}@YpbkB zB3!!`kcior_p=^}nEiF^tVbedKT5UiTgCTHCwo7eWWCk&Ec-J$ z|75}*$JxL9uCdr1s`k4(|DlQfHqom6xWa#!m2W>;7^z&X*SA;p-%RD(&o)+gwfTIl zy2O0)e1=z>-*r}VdfBgw%q!2AdA0dp#*9QV>u@DK(D6GP;o!ze7do!lT@du)~YtD&Qsk{b!XLmRS!}~6>ei}rRTru*Rb8dJyXwBG2df^bdc5kXs%NWSsCv2TwW>F(-l=-O z>LaR8tG=ZArs@Z(pR0bS`m3sS;^B76bsv2@s&-NBtvX0`L)AjnajKiEmZ?^%)~jx% zI#+d(>T=axRQFarNcBk76I4%EJx}#g)oWC5R=rF00oBJWivxsQNDx{q@gOzg7K3^>5X{&M`h+fof;fUaA9C zhpLWH9jiJ?wN!PwYMtsF)$LUmsxDJqqq>*sfvQKS9ba_ys9vpllj@zSYgHdp zeOC1q)wfkYQvFi(2i4zIK3ZgRA;Der8-Y_iRv2F zeN+!sJx=v>)eBUwRJ}>{Zqs&A=&ton`Wuc~qTExW(J zeAO_dNflI@Yco zJeR2MW!EO24_94l*BG9kQO&bo%X{vsTHQa&TdSTlFv{nvzP?_RKT#d9ew2r)F0cy> zpWiCgt2T=A?W*6~#iqahkLq~45b<25x=&G*k5qkdRFt1n&9@5{pT4_l?f58ft9r_& zQNB?1&52R|Om)x}Q68bXs5r`NRIe$C@|~(bmPI*U9@R~4?BvV0FAs%vzb&JBwCcl^ zQGP+SpeD*aRqJL%xk>f3`Y2zl`nFwg`TW079XvbAMXEb)73E!3uiGZdcdP!qU6d0| zQJpw9suijS%!~4|s*g5D`6bnMi=y0HwPD97&s9BRNt7>DeRo-uzfxU)=O~X-U9u|5 z_A}4$eciAos`sk?YJ&xTzrk)%-F%OzPFFo>uP7g{`uILkenqvz{!#9$I`hCN&r?0? z;3!|N`u?F&{zi4^5m6qay6mVZ@2PszF;Tu>_4nhVoH{I~H*9*Od)s?R>svP~G0{B>3w~RWGptvgaFBzf4B?H`S3gK=aqPP~FY` zW{u~ARqwGsUgP-*)nvOUcU0Z7LzHK!9%p~o#-~49^<^8Fd;UPRkNu?^&l{@lU;{zV z%T+J4zkTERX4S9lkKlOzLv{3kC>N{lF(}H1s@^v^%1^20ZV=_ps+Ai?d5-E0_V=fJ z{`aarq587dAQt;b`CG3A_NNV0e-lp*i+G-DTdy|1UaA|Yj#e#JtybMyb&={C)dN(I zRXt1fa<8^tZ>qK*9_95^XR0=-o}_x2>YJ(`srIzLoZ|DVRy|Pl6xAzK-%|ZpwU_-# z6K_|gy0=$*-}|c`p?Zw!sj6qHUZi@N>h-EOtKOr!R`m(hXH@fI=DjW7c1c(}t9Dl% zs5(S-6V*c1TGa;CtyS$b9nNoos-0%Tyjs;xi(%eZ^*~iSU4{G@)st0ESIzaBZ-2x@ z*-ALQ4Lid6zK>(={rJ7WoQ`%MOFTAw)$U7I&)vc5>XlJl#54Q$_v+Yi|GIT-_ztU9 z#fIA##D_Z^9^FLy_a~U)6!ZQ2Irb66g5}mYd_H%F9ac8)619(r{Q->ZICrK07(z>k zrua8m;(xwEbF@{A4fj8a&}_dy%3A7zm2;QcM8$Pg!{@GEy>jsmYgXHA{|_F$ZQ8i~ z^X=)6(NW3#*EVDL@cr-8C8GGR>HIZ+Y+(P~rT^7*?#;T(&HgJTz90SJp0%-mlkJ~B z#@ioUI?t+I{@b11=$|jI&i=6u_B3{uz4)rR&4Xvv2D0b(s?Bea`Qh{PZQ%3t`E6(a zXk$-ftH;=%#mWLaU9rw|HRIy3E4_gpOt-{x_Hrlh5szJG%$Mt&<@#|z8+#i2-R3vI zpXkABds@z(-?uhDKNfs`Y5T|gPO#^+v8SPxj%T#kF)Ig#rABOpWmTpeivo6 zv8S<(Y<@TT2GfK2oo6|FejRLnKAEpyd;7=yd>eS1Li^{BwDo8PV_O>I!E}!r@aH_XvFWm%_T~EHLHn1zem%0@ulIedpIs)o%PXvekK=59n-Z+D zEUz3Z{_>MH-LnS0|MWh{=hwmh`7${+>}l+*h4Gm8X*`&pDcNeep|*Y>F_BfK%lvhf zHN%&W7%*T!(K!1cpm5~)k>l-oVPR3$f5(m;Jz&82(c?#3vB&oL`<7LfM}Pb$nsMCj zo-}_#OEV+qd zFN`QSRv3)@`hE2hX;0$kabo@ZOXEtFH9ZT%)I=X$pFD^?CX+xksWPI|WWD^a#jG^dQT z^($4*u{_GwuT0tcwJD=){mPYX|F=md2PdAf{hxoBTQns6`{Vh)+4&_oHFdR3;D$^O zo-v_ALn_r&hEyrakZMI4QlltCY87S33`H4Irzk_}6=g_+q6}$N#E_ZF7&1#4LuM;u z$Q)%1*-9BhwpPZFZIm%&TV)K{P8ma*lrdy`Wel0Cj3GNHW5_&Z44JQtAC)WXQ6F|DD${2EkGKSo! zj3GBEW5~_Qks&80#@PPPALV_>Ns%Gv`tw^-;a?~=L+%L1Sf>&ia;KWgkh>IR$lZ!E z@Ck}`(8tc)SAC}YU0${6yR zGKRda92s(3VwUay{5!29N!}hAGSaU}-blGQ-iN#s%(4MqXvn*2Dns5=lp*gc%8(Bf zWypt$GUOvg8S=5B4EaP+hJ30hLq1c)kk6GdJdfPRvR#(9A@{aym*x57UY6~$JWcLt*)Gcq$UQ9EWqDh2cguEJ-j3YO zvX5)p1G+k}HS7TB;=oq1BcQVbTgOg-P7Z7(I|Dj8u(j+0=-|Lsvn!yz16$8-fOZaS zMY{vqI6lt zRmX!3?1oxsQ4Q^7Q7u^(%^=I7I>iQ5fE9lb3Ac^36kz=Bkkl$SyUH}v*IcD%Pl%B9^7ajEQS`HPJ3B&23Z!J zNtQ)tk!8`@WLb0$Sr(m3mPO~0WzqR$S#$vzi!KCU(M13(x)^{(mjJNnQUDfR2Ed}r z0a$be0E?~!V9`|oEV>$iMb`kZ=vn|4T?fFT>j7AF0|1L|1Yprk04%y0fJL_eu;^9* z7TpGjEIK8gc+~_+`+dCRsj{e>huh;R_scE1J0ASjOBUTjds%cZSr*+#mPPlIWzkx) zEP8+}iykD)qKC+`=wY%fdW4Kcj{>mhF#r}l4#1)(09f=S0E?aiVA0b6EP4ijMb84T z=s5ruJrBU57XVoFA^?kC0$|b004#b1fJLtYu;?`a7QGI@qBj6o^d2%Gg?-00?2A62y)62WEQ>xO%c76Tvgi}CEc%oz zi#{XEqR+{)=nJwe`jU)AUjeY_YXBB~1Hhth0a)}M0E@l{V9^f%Ecy|EMLz+s=w|>H z{Q|(EUjbP38vu)b2Vl`304(|wfJJ`+u;_097X1UjqF7F5lpl@J;s7kl0YnzP8&AwP zLDKu%=bOp*WYLk{7bS91?w4DX$_WncFN^YMFN@lcWl=s^7NyCusDLbs+LC2aJF+Zl zPnJa;$g-#-8H+jru&6Tti@E@?s4D=Ax&g4LI{=G%0I;Yh0E>D7u&6fxi~0bts4oDE z`T?-0KLCpc0I+Bv0E-3zuxLF177Yeq(GUQA(fR-^+5iw)6yzkXFhSCz?KAjfZca4P zKg0W?p*bn{%Pra@CwO9@EE-08Su~t1i$;)TQ6X6t6_I7pNU|&%MV3XQ$+Bn+Sr&~Y zW6?MO7L5mB(F6b%Z3@7m%>Y<55r9RL09dp+0E@N&V9{g%78L`qXbJ#}N&r|?3c#W= z02Y-4uxKg(i>3jvr~-gRTLQ3XIsl6*0g*);Xl`{fqR z$O$?QmPK{6mqqntS=2z5MU7-xG?OfgW|3vlY_cqxLzYEbk!8`=WGvbSfJNH^uxL8~ z7BvB|XnOz_%>`i54gf5g2f(8F04!<-V9^2q7A*u|(INmAEe2rGjsPs$34ldQ09dpX zfJMsyShO5~MJoVUv@;;Gs3s>d)&xnf=Y3JFEGqCb+RB`i`{fqxk`v5YUl#33ds(y_ zSr+Y1mPLDzWzn8wS+o~f7VS-zMf;Ft(Y|C^v>zFZ_6K0m0RSvI5P(Go0kG&`02Unr zz@kF|SacWwiw*~1(GdVFIud|IM**F%LGaP;U}>*vgmT}i%!i+xnFM4nK{APLuJufw3kI^lV#C4WLb1B zSr(l~mPO~2Wzhv>S#%*;7F|S^MHiE?=n?=HT?)XW%K%t(IRJ~U0ASIT04%x+fJIjW zu;>~97F`R#qU!)ybUgrzZUA7>jQ}jV34ld61F+~802bW}z@pm#Sadr8i|znm(Vc+E zqSJE{YfX^!ad8vp3|W-pebHSxDfi1Qx-TdAU?W*{Kka4FTCyy9fGmq1B+H_Q$g=2R zvMhRpEQ=l`%c94~vgmO#7CiyLq9*}Z^b`P#o(5piGXN}l7Jx<10kG(K02aLfz@irc zSo9JAi(Up`(JKHfdKG|0uK}>=bpRH<0l=a+0a)}F0E^xRV9`4OEP59ZS#(cMB5z}} z$bZG1yjK>r_m1hkoRs_J7JZZxY&c97eN1~<^a)uOeM*)^pOIzJ=VV#*1z8q-NtQ)l zk!8`>WLfkL8H>IJV9|E~EczaRMLz(r=tlq+{RF_Gp8;6(3jm9L1z^!{04(|)fJJ`* zu;@Jb07Mpjkdvr3 zLDJiMU-Y3Y`qo2kBISO$Mfr(f`3PB*roAjGAj_h*WLeaXEQ{KcWl;yREb2&>MV-j9 zs54m>bs=L>R{$1u17J~i02cKCU{Oy17WD#PQEvbi^#Nc}UjP>M17J~q02U1ZV9`JT z77YSm(Ru(Z8VtaqApk5|AAm(00I+B%0E;#RV9`c^$fCSN;v^F!-RO56+a#iq{&C(H zZJbECUvANeL~wJFEGneEEGi<)qLE}-G>R;XMw4aH7_uxHOO{3B$g*fWSr$zoW6`Dn zEZPi!MH2y7Gzox3n**?D3jh{P24GP!0E?you&4xpMWp~NDg$6qIRJ~M03pxs1krhRRAoi24GPQAhKv!BJsKjlHS-ag@((bkG(IdO{Cl}x2Pcz{4q)v zHPT)d%_PgBS!7u>n=FgwkY&+UWLdN|Sr%N02bX0z@l3KSad4@i*5s8(d_^%x&wekcLK2JE&vwY4Zxy%0Fgy!B@$Pe zAnAA9qO)buCm!xiq}(sJ=z&D=l>JOJ{51AK+RLJc$g=2RvMhRpEQ=l`%c94~vgmQL zEP8@0i=HIQqNm7M^fUmAo&jLdvj8l54uD0^1F+}?02aLnz@nD`SoAUgi(Ua>(W?L~ zdJTX@uLH2?4FDFs3BaPa09f=k0E^xMV9~n(EP4-sMehT!=mS7x(fx_U_a;dCJpZoa zT3PgipWZ%9q}(sJ=+i{dd6F#pjP|nVbFwV@f-H-^B+H_&$g=2bvMljAK6FaV2&0I+C%02XZk zz@ni5EZPu&MH>OIXk!2tZ34ieVSvb@bTYAz36d`GzNjD>jr4c*GurTE%KdVSMka%E zi)GO$+RLKRWLY$ZEQ`jHWzjgYEE-RiMH9%fXj8H*+KeoVCX%se5&(-f2Vl__04$me zz@lOR7EJ+QQ3(KxN@2Ed|n02WOJV9_)H7F7VSXiESVO$T66B>;=609aHFz@i!e z7S#fHv{Ng~`N&CP?}~i^(EcjltuO7fGwGFzucm|lEKF1vS@GG%c6bAvS?qjEZUDOi}okWq65gX z=s>b8I*2Tb4kpW@L&#WkC;*EN17OkN04zEJfJH|Fu;?fN799=1qGJG9bSwaijssxP z@c=A30f0p(0L02ZALz@k$CSad1?i%tVz(dhszIs<@3X9BS3EI?$@9?3+l36g%$ z?>g=&i!Sr8iJYBGxnFM4`N?4CX|m`7+RLH~$+GAovMjooEQ>B7%c4ukvgk6hEV`U5 zi>@HcqAST*bQJ)Lt_EPyH2^HS7Jx<90kG(L02bWtfMfU-)=zc(C(YeXQDJDqzG4G4clSMoG z8EtJc<$k$E4=00Lx0FSX&|VfjN|r^Bk!8{2WLfkCSr$D>mPJpIWzo}QS@aB97ClSG zqUQiu^gIBIUI1XxivTQo34lc}1F+~702aLpz@paxSoAsoi{1cW(VGA)dJBL>Zv(LC z9RL=+3&5iH09f=s0E<2VV9|#FEcyt5MIQqqiyllS-ZVkdg?PnVH-N>@2J6RU>Aj_hjWLeaUj77ZxSkwoAMSTHS)DM6~{Q+1s z0DwgU0a!E$fJN&8uxKy- zK$bGkD02Y-2u&5k>MNd_1F&cT0E-p^uxJqgixva0Xh#4R?F7K0B>*g13c#Xe04!P#z@ilZ zEZP}>MJoYVvqv~Lh}ohggIc1z^!}04zElfJG+&u;@ep7M%pZqLTqwbP52AP6c4m zX#gxb9e_n=0I=vx02ZAEz@oDOSac2mi_Qf^7VRA*HZ?)gvwc{$k1RUb`=axLl>6lt zT@(ac&z40O(_R)`LY76Bl4a3lWLb1MSr%PEmPJ>RWzkh+S#&j77F|QeqH6(IbR7VT zt_NVz4FD{<5r9QE0kG(102bW>z@l3LSacfzi*5&C(H#IRx)Xp!cLA{IZU7eD1Hhtt z0a$b&0E_MiV9{Ct7CivKq6YzyMHd8#{Y;Sbj(#b0p)7jDUQ0d{q}(sJ=&>L;e=Aw^ zIPGQ86J%NRBv}?cMV3WRlV#B}WLfkqSr$D{EP4@uMK1xc=w$#Fy#m0Z zR{>b`8UTx42Vl_~04#bFfJJWsu;^_77QF+&qIUsU^d10<-UndO2LLSk5P(G=0kG&} z02X}$z@kq9So9envgnZ@@vsS!Zs&c`qq68FSL*X1<$k$EUkAY_+sLACXfKPtCCj4k z$g=2rvMl<6EQ@|5%c7sivgl{BEc%5ki+&|z(Qg1O`W=8pe*m!PPXHGE1;C=e0a)}8 z0E=R|8n$Cm9DqeR04z!XuqX+@q5yzJxd1Fm0k9|!fJJQpSd#dT4}e930a!EyfJN&AuxJAS z77Ybp(S`sl+6aI}8w0Rt695(s17Oi`02Yk^U{N6ei;4hPG!lSCqX3ab9di?PCP;c$ zzq;;}8;$fQ_^^L;Zp!^~i^k^$tLDn03AC3*o04VGW@K43kt~ZQk!8{5WLdNYSr$zu z%c5ekESf^bq7ncWl>)G+41h)D04$mcz@ljYEUExt(Ut%#nhwCCN&psB0kEhVfJHR` zEUE=y(F_0<)d8@m9)Lv+04!<*V9`tf7R>@+(QH6u(b(L?X(mW|rJuyc$)cbKodH<15`aak09dpdfJJKnShNcOi*^NI z(QW`N+8uyJdjPO#PXHF}1;C=c0g**p=O*4ZLDKj7_lvfnFY+_mKDjCP%Pl$}H~6Pn z79B`?S#%It79C8MMTd}O(V=8nbQoC{9Zr@-N04RFkz`qP6d8+-24K-K04zEdfJMgv zu;_RI7M%dVq7wmFbP@oIP6lAnDF7@w6@W#j0kG(F02ZAAz@jq&SacQui_QjM(K!Gt zIv0RN=K-+jd;k_*0EjHwFE=rGfm!sF_eJ~5qI5W5%T2joZqcQ=LD?c%bQ$es(dA@W zbOl)!T}hTjSCM7W)nr+84OtdlOO{2~k!8{KWGuP?fJHX~u;?ZL7TpZMqFVr1bSnUh zZUbP^?Eoyg1As+$0V02bX1z@mEqSadG{i|zwp(ft4{S_{CU2LM>~AOMRV0$|a@ z04#b05Lt9_Zem9hB>jMQKbOd&5gs1RO}Srg(UZBskvqzwr)V#Wo+itpXUMYXS+Xp8 zjx39wC(EK2$g=1~vMhRuEQ?+yW6>)BEP54yMXv#{=yd=Vy#c_YHvw4m766Oh24K-U z04#bJfJN^Cu;_gN7JUG~q7MOB^br7yJ_caXCjcz^6o5sa0kG(E02X}#z@je!kwuT^ zCayC<(qH=-?Fm^l$%p-4<)+*(x9Gdv;JGET=zH4Bq94ez=tr_F`iU%yekRMJU&ylP zSF$YnjVz0PC(EKg$XN6z0E_+tVA0Jb0ANur z0E3#-efn7EJ|U z(KG-SRRFMPO8^#42VhYp0E?;sSX2$bq8b1e)dH|+1^|od09aHHz@i2K7BvE}XeI!Q zW&yBhHUNv}0I+B)02XZxh%B0rN*rK09dp;0E_kjV9}lcEZPfzMSBCVXdeI; z?F+!7{Q!|g+ockZnjq=EJ}hgJMW6VWu=h`;+%LE2;8gJ08d-D*?PbxSWLb0=Sr#2m zmPJR9WzmsjS#%Ux79CBNMaPh3(XnJKIu3wE#{;nF1OOJD2*9F~09bS~0E=nMcBoe99AvjA9hHUNvx0btR&04zEWfJNs6u;>B+7F`IyqKg1nbTJ^Z z=)hE>-7aR)`4*E0$)e}{Qu~rr%KdVSu1EzVc9TU{(q0x_MV3WZlV#C0WLb1ASr%PK zmPOZ-Wzh{}S#%>=7TrX~qMHF&bPE8BZUtb`Z2&B~9e_o50I=vz02bW^z@obWSac5n zi|z$r(R~0cx*vc=YXMmF004^~1Ypra04#bKfJKi0u;@_$7Ci>QqQ?P|MVF-#4JJtX zVgGIH<+7;1Uur**O1WQd(KD%F%^tGoS=!5@=g6|?d9o~efh>z&B+H_g$g=2VvMhRq zEQ?+x%c9rFSoAsoi{1cW(VGA)dJBL>Zv(LC9RL=+3&5iH09f=s0E<2VV9|#FEcyt5 zMIQsO=o0`IeG0&$&j48TIRJ~k0ASIV04(|nfJI*eu;?2=WYJTp#2F??y2>wwo|Z+A zcwh8wD&>B;ML(v3JNJ@BKha(m{Y;iczmR3ouVh*D8(9|pPL@S~kY&-IWLfkVSr+|G z#-e`!SQN|CupNuy04&M@U{L~qMM(e_1pq9{1z=GMfJJ!#ENTP5qI>`rr2$w}0KlTQ z04!<;z@qj5Eb0KjqK*J8>IA@|&Hyax0*Ea7K9zXa1W8ZyFQ)wPwbI{m8PYKUo$HAj_hGWLY$bEQ{77W6@v$77YPl(fR-^ z+5mt>LjhQ{Apnau0$|a`04&-BfJMUqSTr1fMI!)MR0zPLA^;YR1Ypr902Yk~V9^)= z7L5g9(KrAWjR#=S1VCg__q@dVCP=#2za-luFB<8;NYge;3n$+D=7EQ`v?vS=z<7EL2#Q3U{twgh0&bO07r0qG%qhW`aoGUpZ2n-nJkMIkY&+AvMgFe zmPL!nvS>%LEZT`Iis0ASJ104!Pwz@k+EELsh~qBQ_4+690` zy8^IiHvksx4#1*409dpq0E_klVA0+HEZPTvMf(DfJ?GM1B0{~cbARw}6ZeHRB z6D0kBf4^u4S@eSUMF-`j+%LE2u)N@fgJsd-w3kIkkY&-4WLb0+Sr#2lmPN;qWzn%@ zS#%s(79CHPMJJH4=tKY(odm$5lL1(C3IK~v1z^!>04zEkfJJ8ju;@$x7M%saqO$>5 zbPfQE&IMr6c>pXrAAm&{0I=vn02W;Yz@m!*Sab;hi!KFV(Pe6ltU7Z*7JWLi{Lwi|tEm;;_N0vp`lV#BjWLb10Sr*+ymPI#{Wzj8U zS#&EIi*5s8(d_^%x&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^mELsb|q6Yw2^dJC> z9s*#|!vHLL1b{`40Y02VzCz@jGrSo9WLfkoSr)xUmPN0VWzidCS@b3ui{1iY z(c1tldIx|-?*g#sJpdNH55S@i09f=P0E<2XVA00_Ecyh1MV|t&=raHoeGb5)F92Bd zB>;=Q0$|bC04(|jfJNT|u;@Dg7JUzhEP6ICagYgOLwghFIazdy-^l(UFXeu@MZe?) z7at{yexEiHvkrO2SgVAl$Uti1W9k}7t}w?q9464>d_|Uez`?`+5}%5Ba8adUKaHu z%cA~dSu}twiw2Tq(IB!cT8}J?29ssc5V9;8Uw(hu>dR@2f(8704$mSz@kk7ShN`c zizWghi+Z(5bU4;5+RQJgd$);3`pZ2`YLjxm+@j((LDBKDXbSCRQ3+WVm6Byq8Ce#U zlV#CVvMicLmPHk0S+pft7ELE(Q6&J2ssLD24Zxxr02b8(uxJJVi|PPaR1d(S1^^Z{ z0lV#D1es#S=o0R+I7A15VA1XXEZPHrMSB9UXfFU3 z?G3=9eE?XrF93`717Okq04zEHfJFxau;?HF799-0qC)_YMf2Mv&N4yLFZ*4`W?A%% zf7$5JHYxYZEjqGIaQDfw=qTFDqNB;O=oqprI+iSpjw8#W0Eodv+6vjJFi4gibJ1z^#604zEmfJGMou;@Yn z7F`6uqKg4obO`{9E(KuGWdJO?9Dqev0I=vvKxEP3Z4&RBAn7uT$s=UZR3G+V)h6YB zxkcBt2@~2*9F;09f=e0E-?0V9}!hEP4!pMUMlp z=m`K8Jqf^~rvO;=Gysd90btRyfXJe2+9ZaWAnECT@A_IV9~b#EcyZBEE-If zMMKE4XnnFQ+JG#JhLUB`hGZ<-2!KT!1F&cl02U1cV9{^@7L5R4Q6T_}iU3$N5`aac z09Z5{fJI{fSTq)ZMdJWiG#-FO698DWDFBN$17Oia02WOGVA19PEZPDPS=2W_@w*9< zKG(aSe)-Wze_s!i^Hc7ZTU44K^gdq}mC;@nm6K)BRI)6ZMwUetWLdN&Sr$zv%c4rM zEUF^QqG~c0)c~-l7Jx-F09aH9z@mBp7Bv8{s1blgGXYpM3xGwl0a!E#fJIvYuxM)l z7HtE-qHO_Kv>gD8ngCd|Jpha50M37Of!5qMgaIXeC(|ts-O5Y5*3k z0btQC04&-SfJM6juxNJx7VQDRqCEjvv=;!2_6A_lJ^(D*7l1|k0kCL)02Unpz@h^I zSac8oiw*{0(IEgVIuw9KhXJtYa6n|y!u-S`CP;c0?|v4^qHFvj>4^N4`{foLlOJ4q zu`D{4_Oj?WvMf5DEQ?Mc%c2v>vgjnTEIOGii%ucSqEpGT=rl4GoesdFGXPk0CIE}h z0$|bE04zEOfJNs5u;@Gh7M%~kq6+|6bRhtXE&^cD#Q-e21b{`C0Z02W;iz@jSv zSac--i>?A-(bWJfx&{zgbX0!gNfRWU@Gr?8EsF;DNdMaWl>6lt-IyPIb*U`6iT1MS zX0j~0g)ED1CCj4Q$g=2mvMjoTEQ{_W%c8r;vgmFy7Tp8DqI&^YbRPhV?gwDeS^yS3 z0KlRL0a)}90E-?5V9_H0EP51xMUMfn=y3oRJpsU?CjnUW6ab5!24K-M04#bIfJM&% zu;_UJ7QFz7EV@2F(dja?=yw^>e1z^!<04(|( zfJI*bu;@zw7JUW4qOSp1^bG)uz6D^>cK|H<9)LwZ0I=vs02ciOz@nc4So8}3i+%+} z7QLLGm~DcjzxR{aE3&AEpWc4UPq|-i(O>z&?pMj8ziBUv{vpevSXv`@SrjMBq8zd; zN|0qyk}Qh?vMkCa%c2w+i}C`2Z|R1F)z7fJJQqSkw-HMePAt)B%7+9RXO> z34leN0a(-pfJI#aSkw)GMcn~d)B}J;JpowM3xGwv0a(-rfJJ=)kwt&xC(bcJ(l2;l z^rtL3#a>JHOQ+l~w`fp0xc3@av>xqc(O|MH8bX#u>yu^C24q<@lq`!jB+H_W$g*f- zvMkz!j77r$STr1fMI!)MR0zPLA^;YR1Ypr902Yk~V9^)=7L5g9(KrAWjR#=S1OOIo z3c#Yx09Z5;fJKu4ShP6+i?#q@(PRJ?6$7wn3Lvs*KsxcE36j3gKaCxjjz;>ky)P$OK8>;9mwQmqka~Ysp3Fl>6ltElCH{Z)6M8vu)T2Vl`204&-Q zfJJ)&uxM`p7VQJTqJ05av>yPA_6K0m0RSvI5P(Go0kG&`02Unrz@kF|SacWwiw*~1 z(GdVFIud|IM*$*>c1$N$m>}uF{$-GzWKok}BpsbjxnFM4@#*0Bn`O}nw3kIEl4a3J zWLb1FSr(l_mPMzMWzlJ5S#&yC7M($sMQ4(+=qvyhoejXEa{yR$E&z+p17Okl04%xy zfJGMqu;?NH7F`U$qDuf+bSVIfE(2iER02W;hz@lpaSadA_i>?D; z(e;4HqGQvETTGDj0p1rKCyUzp8SRF2%KdVSZb=8P+$xK1rM)b=jVz09C(EKc$g=28 zvMjobEQ{_Y%c6V8vgls2EV_@3MfU@+Xe|JX9spp`g8(dg2!KTo1F+~302Vz8z@oJEP4rmMK1#)i*8CM z{xm_-Z~15XH*-b{2W;t-`{fqBkq-LaA&cImy)1f*EQ{VI%c6J4vglp1EP9VDi{2;8 zq7TTj=tHtB`iP809|N%H695){3c#Yz09f=n0E@l=V9}QVEcyz7MPCE3=o>67X1pqqTc{m^g95H{s2T4y_QZ)F+tM*_${K> zWl@gzMSrGK?w4B>D+uP@C5z$(8p+F|9I`A*kY!PlEQfJFrWENTnDqILi*Y7fAo4gf6b2*9FF04(YZz@jbyEb0otqHX{z>JGr79sn%r z3BaOW04(Yaz@k0?Eb0ruqJ97@>JPx80f5M&ztf4sOpx>k{)PR2WYI`_Ejh3t<$k$E zLkfb+?~z68(_R*BK$b;A$+BoevMkz&EQ>ZK%c4!lvS=7t77ZuMq7h^)DgQ( zWl<$r7FCgDQ8if>)sSUTEm;=LAj_gUvMj16%c2G{7BvE}XeI!QW&yBhHUNv}0I+B) z02XZxz@lvcShOtwi?#z`Q4;`*wg+I*TmTmB0KlSo04$mhz@laV7A*i^(Lw+gEdpTC zVgMHH2#742R*>j&zgZOcUB?Pp?NcQO|30r(%p-FI|U^}n|Ny|c5k2SPG4p@b#|qzi%2 zL6F{iQBlzlAoL~)RTNO{4Ld4U?7dg)T~V?3UQoo|E5G+=_I)M!p7Wgbd;U0UJy{F) z+*dM_$;>Osq<|UBs56Eo>>em@P$@uu*g=0Y#S) zP;@x~MOP3|w3UFOD+wsNih!c42`IXTfTC*&D7ub-qU#ALx`BYA8wn`7iGZS;2`IXS zfTCLoD7uY+qT2~5x`TkCI|;F(v+4ww8Iasu_chwtQnV%W1zVlS`ErWxs}nx@v=rUX z`K9OqwiIn+OVNXDDSC)4MGv#3=n=LQJ<67%$JkQzI2%Pz5K#0a0Yy&{Q1mnbMb8jW z^eh2I&k<1cJOM@92`GAjfT9-(D0+#2q8$Vjy-YySD+Cn1N`XSeZ-cckJ(c6 z30sOjWlPa#Y$^JjEk$3jrD!KxioRr{=qmz>b`enYH33Dt2`Ku8fTC{+DEf|oqVEYP z`hkF=9|iGZS?2`Ku7fTCXsDEf_nqTdN9`h$R?KM5%Mi-4lP2`Ku9fTDj1v7-0t z1RV@W?!%$Md0&ctb03TL)QOxgrzpq^$8MLR?7aW{NMTGAqE2in>dcm+61Eg|VWX%k z0Y%*iDC$l?Q4a!&dJ<67i-4lu1QhilplCk=iuw{z)Q^Co{Rt@QPe9QC0*VF_P&9~u zqQL|d4I!XtC;>&o2q+p(K+y<7tf+NfaIXQ$ZRg;$ks{B1dK;M+IbTlE*u3!V9a1!o z^GnfqwiHcZOVLEO6is4F(PXw1O<_yX0cL-Hc|HCyvX@-ik9Vtd%r406`Ws+D%n!BoGnEw*iy8T zEk&!?QnZ>aMQhknbR=7f*0ND_6ahs?6Hv5{fTHyT6m1}&=okWujwPUIBLPLn5m0nI z0YxVeP;?>zMJEwZbTR=&rw~wdDgi~O5m0nG0YzsJP_&7FqB997I*Sl1TACLOF(A3m zyPxSFAw|XRW6{}pk@Mvgou3z$zb-|aIlmNLz?Py5*-~^7TZ*=@rRZX|6kWoWqD$FQ zbQxQUE@z|Y3Id9@5>Rv{0Yz64P;@l`Mb{8ebS(iz*AY;3Jpn~G5Kwd@0Yx_vP;@f^ zMYj-8bSnWxw-HcuI{`&^5Kwd{0Y!HaP;@r|MfVV5Md#)PCmWF5=iGN4&y%8)+@tGz z^CIWVDcY77-teXrJ;?c`=pnWgJE* z=otcvo+Y5@IRc8FC!lCM0YxtmQ1l`JMK2Lhw1a@6mkB6(g@B@02`GAvfTGt4D0+i{ zqBjXBdW(Rfw+SeEhk&AY2`GAx5G%SrFW6x~a-VP?ejbpbrtT*o@8?C%ms9j{Uiib? zQuGPum!ePEQuG;Hiauvc(HCqf+R2upFWFM`6WIL0YyI(Q1lA{MZXeI^cw+1zY|dO2LVNY5>WIP0Y!fkQ1lN0MgI~| zw18oXnQ?sgxGK9Zu(-LKDPDit^Y}l+Tu;BwLD7Y!sylC@LVJs4f9T^#~}cPe4%v0*VR=C~8PR zQ6mD18WT{|gn*)^1QhK>Kv6RSiuNX;sEB}~<^&YAAfRX;0*YD^P}GWmqSl01QFeYX z&4A=y>EML<@mKoxNZY<(%a5Edr)b~&@Td=@r~~JhqK<4SDrQSjC$PtXTKLU#OC!nZ50Yw7{C>lsW z(I5hf1`|*;gn*)<1QZP;plCP&MI#6(8c9IWC<2N`6JkZ}@`Ec3NbYL)yN>Op=p9FD zOn&5iIYkrl!^c08qKTYeiYBq8Xfj)hrm&^x0Janz$d;mm*itl=Eky^jrRWegiVh{9 zXc_@UhY?V8H~~ea1Qbmtps0+1q8S7f%_N{`76C=&1Qg9CplA*OMRN%#nnyse&l>PMW5w|?|vmkpL2dG`hqP*JK0k7C0mNVVoT93wiJEMmZIHkDf)&jMc=Yf z^c?|3-xE;u0|7-p5>WIL0YyI(Q1lA{MZXeI^cw+1zY|dO2LVNY5>WIP0Y!fkQ1lN0 zMgI~|w1Dit^Y}l+Tu;BwLD7Y$-~!rKo@{MRnOIsz*RkeFBOa5KvS|Kv6>i ziW(76)R=&xCIl2UC7@_80*aauP_#DzMMVS@H7B5`1p!6-5Kz>TfTC6e6tyOxs0{%{ zZ3!r9M~D?g$zYfP$-UM6-gP1wf2Dt#Bh@|`IbTjuaWb6qtrT_Q{8H4JEkz}4DeA(O zqONQy>c*C$?rbUQ!Iq+)Y$@u+Mp179iuw>xv>yRQeF-S)M?lg31QhirplARAMFR;a z8bmJU5KuIffTCdp6b&b!XaoU8BMB%PML^ML0*b~EP&Af+qH%;+QHNx3ssYJ8 z!TlVqqZHli#`t99d^tsvli^L@OVJe0FGUBirRYGm6dlBtqN!{tI+!g*hp?sSP_`6J zV@uItY!n?%Kv5|HMbil=DkGq11_4Dg2`HLHKv6jXMY9PgnnOU*Tmp*b5l}RrfT9Hi z6fGp6Xb}NLiwP)NLO{_{0*a0xplBHZMHPft(Zpo%iUG-;>%MnANs5}gk42Tq$oX=L zRwcuqew3osoL`F8u%+lowiK;pOVLqmDLR@hMeEp7w4N!tq5>T{}fTH6F zC_0{iq7w)xI+1{)lL#m}nSi2G2q-$0fTGg~C_0^hqB966+C)InnFJJ_ML^Nn1QeY^ zK+(Ab6rD#v(fI@vZ6?HuRwRRlKbfL6?&oMLrRYxgi;ov1Bj?L0x;Pp3{zZx|;rvo` zDO-vzV@uKHY$>{eEk#?|QgkI-imqZy(ba4zx`vISYY8a2j)0=;2`IXOfT9}-D7uM& zqMHdQx`lwETL~z-jew%t2`IXQfTBAID7uS)qPqzwx`%+GdkHAIkAR~42`GAifTC># z6g^0Y6ie4q4=rsb0UMHaF z4FZbZB%tUm0*c-ypy(X}iryul=sg08-Y1~w0|JUZB%tUc0*XE+py(4qtmu(saHRps z?d!fQdsK>w+_xY~zX>S%hk&Ag z2`Jh_K#`Zym+dI>2`I`UpeP`qD4T$ykbt5b0*WF+tmyM(u*-nt_Hv)ZzL27h?qg9R z6**r{QJqwn`?nP3aegVvXG>9%Ek!A|6s6fxRKS*^x@;+`$Cje{Y$VfTFz!C~8JP(cT0U6%kO>oPeSh1QhKzIn1FQ=#^6;AwDin?%q zDeB6WqHb&{>duy;9&9P<$(EvCY$@u^mZCmvDcX;XqP_$a^&_BYe*%j76HqjOfTDo} z6b&MvXfOdqLkK7uN9D z4rNQxG`18S#+IVP*-})>mZIrw6qONBG=qSmnFJKgBA}?8fTGz16wM)^Xf6Ro^9U%K zPe9QE0*V$AP_&4EqQwLhEg_(2DFH=C5Ky#?fT9WliYf^xT24UG3PP-CN-Ef9Kyqie zADtZ_MS1Qk{gtW6`ErVmOoi`fNzq!)FGWYOrRZq36s==R(R#KNZD32$F>EP1mMuja z*-~^I8%4(xP;>$TMJEzabP@qYClgR~3IRo@5>Rv+0Y#@1P;>?XMVkmHI+K8+vj`|U zn}DKo2q-$2fTHsVC_0~jqRj*pT|hw5g#;8`M2HowP6b(kDQf1vcfCf6E^!}=wxlBG z%PG1n74BpI97N`0(dC?9imqTw(N?w;UCEZBtJqR>HCu|VVN21qY$>{qEk)O}QFH?V zMK=;qbQ1wZHxp2F3jsy95>Rv-0Y$eHP;>_YMRyWVbQb|dcN0)_4*^B@5>Rv>0Y&!{ zQ1k!+McW7{dXRvkhX^Qon1G^32(h9|Qo#rVlH1UI__% zqHoz!^c`D@zGq9(4{Ry=ku60(v8Cu|Hi~{Bpy*cuihd)Y=yw8&{ve>}PXdbmBB1DR z0*d}2py*!$iuMptyeh!uUA z3SKiHxl3$jezZ9j}QdGc}qPlD;s>hb1`fMp`z?Pyy zwiGpFOHm^>iW(D8)P#VdrUVr2MLV8NfTGp} z6ty9ss4W3S?FcApPe9SW1Qc~3pr|7OMa2XZbt1%y^3p-$I;QAl_g%;Qbo`b6X7{nE zb2@UqoT6^&aKC&h>dyJ4s0Uk$da|Xc7h8&Yv!$pHTZ;B$OHp686!l|E(f(`{^(UZc z00Bh<2`CywK+#|ViiQwSG?aj%VFVNnC!lBq0YxJTC>ljT(P#pS#t=|6mVlyh1Qd-Y zplAXCMH2}qnnXa+WCDt&5Mo7L(!q2ClKX&rDAZMo((cjq0qMy3a*7U4hZ|B-bO`5{ zqC?qIG>t7qhq0yTaJCecvZZJ`TZ+oqQZ$1tMKjqbnngfSIRQnp2`HLFK+#+Rislhe zG@pQ?1q2i=B%o*!0Y!@mC|W{5(NY46jv%0D839EV1Qb;gP_&$Yq7?)btt6mm6#+%7 z39+Js(!tdRB=;Wov1qCkUGKgHxh5SsUry1{>G0_SDO$(*rD#1{iZ-yN=oq#X9m|%Y zjch48jx9yUv!&<+wiKPnM$t(G6rD^!(J2HJok~E_X#^CVPC(Ha1Qcx|py*5jiq0aS z=xhRt&LN=aTmp*DBcSMf0*W>hP;>zSMHdoKbP)kXTL>t+n1G^72(hBI>0q}3$!+RB z{2V1kXS;D}I&!|8qOIvLuf7yr$@!(|Dz+3|&6c8T*iv*YTZ*n@OVRagDY}6zMK`jg z=q5IbZYH4U76OWHC7|dw0*Y=Ypy&<)itZ$!=q>_^?k1q<9s-K)C7|d&0*dY@py&Yt zinb9@^dJF64-ruGFabr65K#0e0Y#4yQ1mz zQ}j$aoLneH&vJe#dX6nc&$FdyJ6nogU`x@9Y$TZ(>Tqv&@6ivA#==uZNQ{vx30Zvu+` zA)x4A0*dw!P~;Wp%XSp`1QcZvP!teQlubZUNI+2z0Ywo3MF|3mY7tOWn}DKR0*dMo zP?SfA6@8r!9x@=guepy!yQL_{eMZYKh@3B{sGuPHu!$7a<@{1qk1a*@*;3SiEk%WF zDQd`;qDE{fYRs0RCTuBc%0|&%1QazRplELbii!v*YED2=3j&JvA)u%w0Y$9{C~8eW zQ5yn^+7eLIj)0=}1QhK{Kv4$*iaHWdR7^loCjyE(6Hrt_Kv5S$tSD6wWH&WM)7-a+ z(gpEX`o|fb?5+io^W_xvEC^dQlcHXnUy6FOrKk^EiuPkmQD3$c^lvX(I^6nMiWpphJd261Qd-UplCb+ zMH2`pnn*y=Bm#;i6HqjTfT9BkC_0dUqJs#rqV5I3Cj z5m2<6fTA@76dg%G(ON>R=#YY7lL5&+(7`!WipILXD0@^vB?SyD_z=-1BZt4V~+GccxC6?|Jv8US8;V z+fs!~JnxazVMlo06RE8gp7%`ZtL2`zJ=Mwnml!)z%h!0`YpDm;dfr9VbMH~8smuCn{VPrLt{ zeM>*>{&(bU{j~f4Nq6wm?tci}*-yLwqiZ)m?f#dXz5KNMe=7F%)9!zYH^5K3|Et*$ zKkfdvR3rSf`~M1!@zdWuV)u!kcK>IODSq1huNkKLY4>mIPxI66A4i|=r`^A9J_R{7{(;b?e%k#DkClGf{S$qw{IvTw*4FxI_m5<)_tWlQIojx_AOFbi zAwTW@osm=hwEKr5Hu-7yH~r7?)9$ZoZ}!vf@7iwh)9x=zUgoFW-*&swPrJXabgiFu zf8XRrKkfd)z^#7T{l@p5e%k%Y?!A86{m$h!Kka^L?h!xje(UK8Kka^P)9yz%Z~1BWz4!P0wEO1iM}FFU_vY}Fy+`?7 z+uL2`{*B(uQ@!%QwE<_?YG;31*`NCDB5U3AT^nbAM%kYR2G#R>WSZAtyIr#1Q{xzS z3BB@j2VcH74Re}9d2wQcm*nC-5? zfOr&6vEkmPhO_L%6g$z#pAgpBI5&G)BY$F8=jyS~*KXub3hONEGCseNKRK-P(6;6F zF{JSnd&TZgmvgZw7>2Nb6LRH5f(wY2}`!~T{$FKFNe z`F(Qt%k7;zvaa2HdQQU5+}(2}CuuM1PDFM6+}!vjeVd6qFGz64+}ym}I=Q{mv11Njp{r-)(5^Wl#{eqkU4bLCc$i2pTVU4SoRd~-JyK(Aw`|qtm&DPXjS>Z{?_+HvC zvCC*^C+#*qcTgj@8l7y<$ZB}zpoVs*6np&}^=-5`Kl9q{>eyY%Q<0tUy$SB%AZL3& z`4cX+6aVov*_Q83bO&B&V$};}*|XeJk^RZ?I$!EUPq06}H_iT=d1`9^b)SB!-!0+` z$|U{AT`*4@Onl&#*;%suzw+}u-=6Gwj&X5ur)6cGW>+ljRIzMkr)8xTGs{btE?ZJr zKC`lXR;QWERxhnw;=;`GS<9D|SJZf(dwF~5-kp{%o406Q<-8T;UZ=TB7L|7@TUfrT zQ}MzjGs_lss+e20ti02*^2Oy9Wfh&uyOdT`E}u1TNvFysOBT+YTQ+ZTMW;D4XO@;N zThytfb7|MoE}grSl$LaMv7^O~i5lH!ZF%ub=b&^} z`Ruag3oA=2S1&EED4y$h*?l!@-r`Cd#%J>2p`~^mXAWMnXwj0z*6hO&TIRXSjgx1e zH^L0fpsOE-b^oWQ(9a3x_+dfNq$sT0AuMPf*6kREIsL+d96MW1r>bLpH~lbG6xOoG zUVcuu&^-q8lVPjO^y68ad2Uutm$0SfEO#017_2S|3*Ct}dVZ&>=Xc0Fe^qh({2u@9 z`SJNz>iI#f`1NPmHRCm8F1R>soq2`9isG=oJEhm0V{c!bqE7Z^)(yjsSt)y$n>2KI z>9EctJa;VV)pELlwy2O_~gtK(7dVM`fU8`Sjm#Wu0xW+~53U=WPJ*r-+cjh`RUtBS7&f@Y} zMTR8v>IUn2l?>xj>;!M-(5kni#I8){<$K$Um6qDMyLKs!FQLR<8D|*Ar47`j4XVBb zy9MmUW-VW|Xmxx^df9Hg;(-c1tFD0EpjDS#^-8+&I)+r=7+g@ZdjeKd)0;6_2HFv(aU$Oz8-_C&QUU$S7ldR=WqgQd_eu*`YNll#)zvOBu-@pQ2bT^UGAVODyC3xy znOB_}@*n5)7A{#lrzrEE|7NPB`icw^8+6%ymU#tma$v+?Z(r4G8JfA2`R-jL^Q_Lg zC=;t|G^pyjx%bV?3k|F~d&v+0bk*~!L~tcadR1LiNi{l^qJ zH=vqSiJ6L9XP#NDtYjE>Q8g~^HG3oC^Kru6J(&+d)pxOdRB~6P)P0Pfy?pV^lFlXZ zi6W%wE;EnBAW7Wpv^7RXZrDhEP&Ng561awN*C_cSXq{z4_b` zy{lftZsMvdKd`)_OZOgw?Qy^XOJ~{Vq{++UkFnJsxw!wjS6|cEM&>4|=1@|@Lk$N# z>?&4c<>OunoZPeB1=&&eZHf8KB<@rDh@)q9t-5jTCgR1bRd9!Me^=edz3i4^xks@r-X=d$pMpc1!TQ>Wj!+CC6ZjJq*yxb4I(TGR58fnNK$H=a`{Y z=eGMsmsoubxcBWA((|hBWxEUF*HEp-KCswJWiCAPEW6irF8dsyQ&n$>iL7C^OXu$K zrP&8n&mLJWi*KWn_@GaR)oMz_#_p^tsnsUzGp)V0in&XcRaSj+B{y#4l*?$2w7UgO->py0za8+0429>_PpCUL6+|FS0KS_MKI+bl=%ai#pCJ>NvhjQAc|y z+Ha;^fsV5ml~+`h%_;A=uzc~H%DMeITZ$isbaeN+E%yhv~*$0EN zsvX}H_Nm+(xp;^@qjXC7Dn0zD#_T@i>n3ne|EEt*G1wZPKr<>ckMP91`r)0E=~z@h z%By~CR}$0DsId>?x{B5JR_wp(vttH$Y3YA{>gK^^^VO5FtR3_4k5ng^2AkMU|e#N%;f_2W6-Iow0M%$o<}__18(Eq4zf^_VjA z7XEL3amv@W@s~XD`*zjs$@_BEdkpU|?jh=est>k260Lr;Sp8tJr1~QBa}m`K3#)X*k1f67g9rC1YU|!X2QFJwG<4C7@>#R& zG5Hj}z|OqS@`ZD||M@-Gz8_G>{_L?Q`$osw{5pA=??CV^1o!QPf%&P8*~bOPXPxdZ zc=4$xpRjK;c>{aff6Clf=$_xnPKLcYjx8QLaO5~ICmoHg71T}?WY_cS`-MS6zmebA zZ{j!gn`O1|i`_RM{>xL%l)EZBLeSzw(U-eVAm$u=) z{T4sj7qB&+0x$E;$Ep%|_N}rSPl0FOi>&b!cs0N4s|h6xh!SYCZ*-*Ir!$ z&%UWt<0+ytmfZx-NS58O?zVKt`Z_jpM|);-ceIHdUz5GEsZrVHE7whG-34bJm@IkB+@c<2_Wzqs!ubijGehbocTv>sWhsybE=lFgM3H7!cyHD5y@m1q zO2-yU;@wHdxkto%xsEqi#QOmqe_kGMe?@%kvnoCg*Kz%tc%P=@Q)}b>s*ZKm#k-M? zlQzV=RL9N7#``KAKR7PlU+dWN#CVtJIRE5$uhj9@Q{(-hj=!EB@8FF1*!Rr%I8w)B z&W`sPIzDr5ykFNbe{;N>=s4xVc$evT;g)z`qvJ>RvqN|Pe4}IQ%j4Zu$Aw$ty;{fH zuZs7>I{to5yu)kbiFEv@qSas)NS$JOUDE6i1$n#x7-!)>va6& zo_K$!W83@V-Cf7U+v0tsj(0v3??-j~^O1N*kH*IVkH^QcIv)RIywBEg`_u7$TgQUu z;=Q+yQ@6*vT*pgZjQ0&XezqgtKj_&0)p+;Rap~*vK1#>C-;DR;I{s}xC3W{tt#{(% zp!eeAcpXptAl~Qd_~J+LepknOpT@hnj)#06?>RbNwlm&0>G;K0@%~B24!h&sTgPSJ z#(SNP_kJJmCw2VSeh}-fZ|+a=amX+6aiWeV{}%7_b=+Y;qjfL;zK#w4j`uz~PWw0B z^K`tz9x1q&zeUF{v*P`Wj>YzkdH4MNbgZzLz?cHt>)J7mt!>s{&|U)lAw zhdExBz4C^nwzTuTMeYoG;^h|GuK9Yihxy)gYwq>B&gT4|Vjt1M9@6-GANl+@A+^ z$E0%h{*(|G0kB?d58kcCXhxJ!OAtUcXaoyuI#Y6xYu_jXTRr?T~po z$1blA!;bFtx+iz!eZ}n^_Hq*}7TW0o`{OPzWq;i3tZ{RBMdojmHJ-SJTx#&8@__SW^UIz3?B@Ez~Y3%*}B_>LdeFB!3;?dW!++Kp^KV$W~??(y~+|MU8+ea3uJ z_QdZyNXjIY2=9%X`v9rilbFBw$HMbRC%H4J;)t7n8 zPA}D9K+nZsz_uhpot6eAvXrTX&x~a`Nh?^S|xlek*25{oBsEaQ9uG26x=Q;Ho*Ne71dc zhZgPM9COY3m!4Vs@mZH$wWr}@r*%5I*4NEWIjiNW;<_Kcd~xg2?PuP0*K0#JJ-_^g zpEow`RM|vizJ2?Hwx1Pn>V2va-U}_1z(w*xcYeWB|zr z=umf{y?9W&$o|v0-V{3>+Ltw6&VKeD9A&Syli8#5>qa&narUF5?LEhj9x~@y7VS(? zv0YYn^rl_WFnZNI=R}R{+D6gwcJYbmYU{P4Q|;wzM^o(*a-$jcdAd&Y{oeM=SkZQS z7?dCNY-S%YqIdSPcc17wd&zWkTT^?NivB9{yt>hq_A>RNZT1nWesqbwWP_-S-ByLs zgDvb+ezc;oJz$B7?UrjC)wkXxa=(4nG#YD{-z;in*J1Byr9HPO>TH+RJlbNfrA73r zUD`g;8hgo>(Fl9!(<<6;ANz(}^jmY!D~}$x)6Ycp?K(Ug?X>IsTvXp4W;`E_wfETV z(H^@6UWg8{*ZyMS0z2KoPn=>`tD~Pd(_X6BPc*Sxypu({W}W>+sU0@?iMQ=mI@3@5 zZuj8Xe!~3@-#LEb2D`b=^%GCpI?qo$Yd72Ze&SZUl+Au(lU&& z`H2th75(fd0(;|r@e{4>BhIgWVxh&~{KQB0_WkZB*4h=Dnw9w2UeUI!#94NgzYG%1 z>`HtUB-Y!fja@-vvt8!bK_bW8?G6$L+xfl;62*37d>bUz*sbwhkl1N&!}mcVu-EWI zkoeJF!nrejFxB>}LHWOt^p8YDbjVX)pP5lvrnHeNHaq*UtmTD?uJ&fGC`_DXuVH0jVvn7DRbk>hy9HMlCZ4ymuPIDCYPbB6g^8qH z&$We#i|lPUsxWcCc{#c;vBJ*2t}rpqZpih8i39C5Y$!}DuuB=RB{9oh?Z7RGH|)X& zZAqMNH|vlsiIa*vZ|Igp(r%DpTN3tLx!&+Ci8*#lOn5wTwLNd*dx4eaKAe{b64UodkwR8B@VNzRK6?G)82;JyAmJS>zlKyRzJJ3mZp8L)-cn1 zggcRA=UwJbjI~%mN8uJPMmHx;|h18nHgMfcWJGg?S(hE6TjGva*R7M z&fXc1btihZuup;R#0z#G9Oq7qHR{K^6F=K^Il-M+V7Jjl z#NM)V+=(yk?LOC?xWit>>X~-pSG&X4xD!9w6?2arYVET7(03bd|)?Y=uUL8cM|)(TCY}P_i@;r_{<*s-%t(P=)7sM*Ka@VT(|A| z_0_KJwq3t|+O^!a>$ksl!fm^L{k0>v?fMPS&T-qW-$3oqZM%Mhw6oo|>o-_CaNDlm z5bZ46UG4e})%M-C>o-i>802M#ErXGE|K~3=IAN>I-|WnvY46bC@TiS@&oUvS!;yw5 zBV>%uDj{PvC1jkYgpAjekO`U+GEq}PCTU8@WK9W~qA4Ki5ZG;@8jgYC@2sv0A zA%|!q^oQ5zx0X(Qx#ZG@bljgS+y5pt3?LQd93$SK+gIaM1Wr)eYPbZvy3p^cDD z+Od$u!D)8?=a00{$>EY%$lXrJnURy@gq$0mW}oviLeA4!CFFcf3E8YEAs1*$$c35` za*?KlY|)gEi!~+W5={xYR1+bWX(QxvZG>E*jgYO{2)R-lAy;W5{RYJCDO2~tn67rCyggmS%A&+QE$fKGP z@|dQCJgzArPiP|KNo|BYrHzoMwGr}+HbS1&M#yv82zg!`A=|YP@`5%(Uerd&OWFw8 zp^cE2wGr})HbP$2M#yX02zgx_A#Z3S~M-r!}s|MM5v!`1M< zSjbd+ARoRPIXO+6ehk8zDbwBjjgog#4n7kYBYC z@|!k7e%D6GAKD1{QyU?FX(QxsZG`-zjgWt}5wb@+7V>`Zv)%vsyPS#-GD4C+y3_Xk zGDpWtWrx{*Sl>PgrQKIEp|5lAZQCC9=CGUDwuj{rdoSDeusp$TYTF)`*J3xZZ4b+9 zvm4vChvm8KMz-x?c^!5`+xD`K-pq+PIUS&xu%!LDX~Led4ho(%~3F4z?hZ*R&y_js^D>P9s9D3wBK# z6KcC)*R%I2v>74C1-qtu6G9j4nidi4_xUnk=`<(Uuh?b2 z)M-J;vf#ef*@s|%wKMa@PD_FTDaa19{Gg8kNe*;h;sk!I=sNp?I&9@fj+ax^&JPbY zSQ$m_IlmO`%a)=JY$@ul&a(GUWPh7wRTjDVuy z1Qd-RplBo^R@BB1)*FyyFZb=Fwo-J4eLp1}ECPzk2`HLPK+zlmislkfG>?Fy`2-X#AfRX=0Y!@lC|XR26^-$O zrwm9kueGCeh_>uGF6jk`)PW!H7Mo}f_m!jotDO$mnqLpkZTE&*4)odwR z!gP;?vtMaL6RbOHfIClXL} z5&=ag6Hs&t0Y#@0P;?prMW+)`bOr%Mn+Pa6lYpYL2q-$65Gy*u59-(_v*afCzW zhZXiCm5ic?IKLD<%$A}@*i!T;TZ$fIOVQ(ODSCn}MNhJ&=qa`oJ6#YX$(Z2)~?IEDZ%c}Y+ zKmHocC!i>c5G(q~4?Zv;$-9hF_^}kNaX+65vLffpDT=bfJ*}iD!TF`A7F&vHv!y7P zEk$+MQk2J*qI|X#CD~GxVoOn)jiLeqis}+jRF8n7`UDg;AfTv_fTD&36g48Cs4)RW zO$aDzN3mHv75n+0LptjPItiaKP4L)%JGN6s%r#cV0+#FnDYY$+;XOHmiL6m?}w zQ8%^}b!SUa4>pQ=5>V8OfTG?66!jsXXg>mq`VvsokAR~62`K7MK+ymKiUtx;G>Cwr z!2}cyA)sg|0Y$?IC>l;c(Fg*HMiNjoih!cg1Qd-S#ERNy1@jF^a<~1qO1Q5St#UuP z7@HM2Ury1)tniffQZ$M4OVMPu6is1E(E)5JI*=_z2eGASDqD&UW=qi_Y$-aFjiPA; z6dguD(cuIXl@d@ioq(b;0*Yo3P&AW(qFDqKl@m}jn}DJ@1Qg9BplBWeMe_+LT0lV2 zLIR2w5m2<4fTAS?6fGs7=m=Uutzt{jYPJ-uVN21GY$;mHmZGEBQgk$1iq^5EXgwQ68we;mhJd1D2`Jh~K+$mo z6dg}M(Fp_;ok&2@Ndy#~OhC~o1QeZ0K+$Og6rD~$(HR63Z6cuPOah9|BB1DO0*cNd zpy*rziq0d%iYl{$Ukym|4EJ5f_^?k1q<9s-K)C7|d&0*dY@py&ZYtmuNQ zpsxW*X4`LOgcnLtSNlbta9dX7d^tsrWQB*7NYSI5Uy2@MOVQ(ODSCn}MNhJ&=qa`o zJnw+JYDn}DKs2q=1&fTH&ZD0-iOq7Mit`jCL4j|j1%hq8iW3`p`q`~BeX zVJZ5|{dUL4S&{SQ6n&l*ZtW^XUvPdY+R2upFWFM`65PsENigG!>6xCr%Q65{0^4U_9WJ^(sEk$Xz6cwakH& zpMatU1QZn#P}GosqDBN1H71~_2?0e-2`Ji&fTCsu6zxqwQ4s+}%?T)KK|s+y1QfL- zpr{oAMXd=aYC}L#TLOyO5m3~g5GzUqL4FTY^sW0AQLP~UO21B)jeUd2`ErUn1!1RN zQq-CAOHm11in_3+s4H8Fy0N9GJ6no+u%)OcTZ($IrKmR>MSTb;+K+&uz62EYBcN!1 z0*d+*P&9ymqJaby4I-duFabqF2q+p#K+!M)iiQ(VG=hMlkpvWtBA{qA0Yzg7C>l#Z z(KrH%#uH*i9fM$s0Z9h#!%wjkb+o@=5l#pq=gTRY5`@e9NYMeDUy2T7OVL4WDVoZb zqJ!B|bO>9D4rNQxG`18S#+IVP*(fR{plCV)MP&pO%^;v?CILmW2q-EiplCJ$MRN!! znoB^@JOYa56Hv5(fTD#26fGj4XfXjrO9&`hN}*iv*fTZ-1PrD#1{iZ-yN z=oq#X9m_`1MgoeCBcSMb0*X!`py)&bicTV+=wt$lP9dP^R04`lBcSMX0*cNcplA~T zMQ0LFbQS?cXA@9#4gp2y5>Rv=0Y&E%P_&tVq6-MIqLo4LkpW5G`=(S{yjiT!aD7v12 zq8kV(x{-jQn+PbnnSi2O2q?OhfTG(7D7u}1qB{sEx|4vSy9g+{n}DKw2q?OjfTH^d zD7v43q6Y{l+D1Upg9H>kM2Hn_34+!JBzdCyY3#*P)ZBgw8$KLF&X-g4cn}UBC`C_j zekppAEk#eUrRZt46g|V1qG#Ds^c-7?o@YzZcD59~z(&!F1QfkQK+z5Yie4t5=oJEr zUL~ODH3EuWC!pvJ0*c-wpy(|Eiryxm=p6!z-X);uJpzi}C!pv90*XE)py(q4iasWw z=o12pJ|)D89u0zp1|%7|Uy^-Hihgik_J0;c&X-g4We}b=Sc<;l{8F@wEk$3mrD!)> zioRh>(YI_V`i?C{-?OFY2euUb$VSmm1Qh*DK+!J*6#Ys-(QgD4{Z2s99|RQrNkGwG z1Qh*EK+!)06#Yv;(H;Vdylj2hjv}9cqAUW60s@M%2`CB)D9RzAC?cRJL5LN75d^mz zkmMrw`$apYXt?_cNUiM1`ErWvZ==3CREqLBzZ50eQj}s#QJO791#Bs*%a)>gY$>YG zmZAo1DJo>6s38GGjR+`eOh8c+0*aavP_!2TMa>8(+M9r)A_9t<6HwHGfTDc}C~8SS zQ7Zz9S`$#zhJd2B1QfL+pr}0oMf(y^)PaDaj)YiIZg%jy0ZDGMznL7?$&SC$KhXWX z)Z*;O`ErW7WQUDLNKseLFGbzhQq-L-MLpP3)RQemz1ULJn=M6s*iy6~TZ;O!QPhus zqWuXd>Q6w?00N2z5>PaVfTFH%^>YN?yZ$Og6-S1tONYTUgo3i2L?8y0YiVn&SOGio3 zRL(C&2eYN<5VjN@%9f&OY$-a7Ek%d3rKprGMbp_*RK`Zp3<8Q~5>PaYfTD5&ie?i~ zG>3qqxdar=BcNzL0YwW4C|XEB(INth786jkgn*)@1QZ=XK+!S+iYf>wswALjIRQm0 z2q;=fh!q`>9c(lp$$i}e>I0=H*O6M49XVf4(c0|rsxeY@6z7+squElljx9y&*;2HD zEk(z$rRZ3;6m4Wn(Q#}kI-ZT969_0ek$|F;2q-$4fTB|fC_0sZqSFW{I-P)`GYBZ! zL_pD*1QeY`K+)L*6rDpr(YXW^oku{?`2-YgCZOm70*Wpqpy(n3inb79MQgHy=L|^l z51ZkUD01I|yf`~@zMP`Vv%{~)NzoOYUy8P}rRYkw6kWxZqN~|bbPZdIu4PNnb!;iR zo-IW;uu*g)0Yx_vP;@f^MYj-8bSnWxw-HcuI{`&^5Kwd{0Y!HaP;@r|MfVU;bT0u# z_YqKZKLJG#5Ky#@fT9NpD0+y1qK646dW3+YM+vc_OS6O2cvJM1`}M}lq^Pm`amZuY zk@MvgJ(V4nOq8OhIlmM=!MG*l-2?C00 z5l~c{fTCPNtmv!kV2c4s&UD|d-X%p#+*kT_!pQk@ic(?t-~m#U=KNArz?P!AY$>Y8 zmZJJ>DQdu$qC&P5HDpUsBeoPZW}~PH0Yyy-DB6pFqGkjX?M*;Y5dlTb2`FkoK+!$~ z6tyIvs1*T4tqCYOeqIM*@n92`K7BKv8ExtSCPWJ~1H4 zQum8#$uRy({|@(!?2<5YzMP`&VHix6q8^-Iih8o8s25v`db6dd4_k`%V@pwAwiNYa zOVR#pDeBKg(EtL91`<#-h=8KO1QZP+plB!oMZ*Xv8csmb2m*>m5>PaXfTGa^6pbOE zXeW z<`7Ucmw=*q1Qg9DplAUBMGFZiT0}t6Vgibm5Ky#~fTAM^C|X89Q3U}-l>`(mC!lBr z0YxhbC|X58(P{#U)(~PvQ^R1f0ZDdtzjuAG6m_wG)H6IXjGQm0Xk8edF-?lrbABn> zz?Pz8*iv*XTZ%TarRX@e6dli&q7&FsbRt`dPGY0zWCDs#A)x3~0*X!}py+f0iq0UQ zXcGZNXA)3!76Ckbt6#2q@Y@K+(kn6kS3< z(WQh~(NSS=rvXV8x!=1!T8iFqiY^Ny=gTR&G7MioT#ByZ{8Dr^TZ*n>OVPD#DY}j= zMc1>X=mxeF-N=@ro7hrxGaE&>5Kwe00Y$eFP;@&1MRyQTbSD8tcM(u@HvvWW5Kwe4 z0Y&!_P;@^5MGp{Aw2gqG2MH*8h=8Jp2`GAmfTBkUD0+;5qQ?m+dV&xux*`nzG$6^o z4$f97`Y~WIP z0Y!fkQ1lN0MgI~|w1VW)Cvzg_%PFdx6JAp;MfEtp6xC-- zQ3JLV6|$wMAzO+Xv8AXnTZ)>nrKl-eiuPios2Kr8dlOJpL_kq<0*YD?P_z#LMJ)*^ zYDGX%YXXYe5Kz>XfTDH;6tyRyXkP+~IuKCQk$|FN0*X2jP}G@#q7nj%x)4y*l@KdR z=LFjgNHVL);1uMkX{oAXOiAGQ?j$CjeLY$@u;mZJUH zQq-R|PtgV-n(9x@dOl2AfRX>0Y#GtD4I+_(G&uT4j`cDKmv*mBA{q0Ay(8QCn%U}ie7Y|#Cl56 zF83|SgL5M1%PBf6C+s?3iVo-eQdG*8qUmfYDq~C047L=_WJ}R3wiK1KrD!%=isrCU zG?##)c?1;AC!lBn0YwW5C|X27(P9FMmJm?1lz^fm2q;=cKv4w&MU?~;EhnI81p!4X z2`E}cK+$Rfiq;TNbR+>qYY8YiiV!P0G$)v9K$4dv4bC(vYUqAt?dY7y`ErVm$q834 zl%iufzZ7j`OVM#`DLS4lMJKSO=tQ;@oy3-+li5;q3R{X!Wuxdc0*X#2py&(&iZ&5Y zbS42sXAw|zHUUNF5Kwe30Y&E#P;@>4MVkpIx`2S93kfK?h=8Ik1QcCNK+z=x6kSR{ z(Pab_T~0vJ6@*yP`kder1CqSL{r3I_DO&43Fm26=oG+*7nw;?A#Zq)F=a-`E*iv*o zTZ(RAOVN#NDY}U*MK`mh=oYpV-O84t+t?_&oq(b{2q?OffTFtyD7u?~qI(D^x|e{W z`v@qypMatV2q@Y{K+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qb0%K+%%~6g@>i(bI%j z(N#IYX9gsBQfP3lmZIm~|5f3coXGidiniy3;So~w0_T^a7uizu5?hLPu%+l_wiLa> zmZDeLQuG>Iie6_+(Hm?Oy-7gPTLcunO+e8*1QfkXK+$^y6unPC(FX(+eMmsjM+6jo zOhC~m1QdNrK+$Ie6n#!W(H8_1?IfV+O9G0%BA{p&0YzUEP_&y6D|#*`Xm3E0SGk{~ zJugKY0~_DuM9!B}^g~WKxT{2`I`UpeP`qD4T$ykbt5b0*WF6iV_4A)gqv% zHUUMs1QgXFpeT=kqI?31k^~f`2q;PuVnyHO1WOG_vbFnLjo(Yr825KT3ZlsQa*7&6 z;hD>&sF3qZQA4&AHDXIqW407EVM|d{wiNBfmZD~CDcYMYMMZ2BH7B5`1p!6-5Kz>T zfTC6e6tyOxs0{%{Z3!r9M?g_~0*dw}pr``@MI8w!Dkh+)69Gk?2`DNdpr{K0MO_If z>PA3OcLIuf5Mo93qTp@=l3e1xMN~hEztVr*eMajUMb4K~v|kjyxl)Sya(*f5$Cje~ z*;3S>Eky&^QZ$e)MT6KwRMF$d4bPxeWQwbaIZB|RL1$GXa-w~X0oMd7F&wS*-|u{Ek$$K zQZ$z>Mf2EFG@p&41q2i=B%o*!0Y!@mC|W{5(NY46jv%0D839EV1Qb;gP_&$Yq7?)b ztt6mm6#+%72`E}aK+%x|6s;wo=qLh;jwYaJ9RWq_39+KXqhOE$Np5sMM=O=06-72S zM3M956df0ZGuKMd@tj|ZPGC#XiEJr4i7iF{A93#i9!1&yZO>-2Z2BgU(8W+xItd*W zVbjQxN(xP32@rad1Oyu(*bu2AqKGIWc0lD3JI&ruv7;a;c11*uiuhjl%yn)y=<|QS z_xRrL_;MWK+TXcz&&KE zbSD6d?gC)ZMgSJw4ZxyJ0LP+*UiWn(h|gng5iL@SPMUXP@9}z#U&f;Qy`KB7REr*< zy;}4jSuJ{qtQI{?R*SZf)uOFrwP+hzEqa8k7ClN{87Cj5VqUQiuv=e|uy8u|U8-PW709dpafJM&(u;>K<7QG0- zqL%otBEi{A8lew?os?W4U~^cGny zdYh~ky+c-u_LJ43cgbqedt|lfeX?5g0a-2jkc>qi0kG&}02UnpV9_T4Ecz6HMF#;` zbO?Y&p8>GwFaV2=0I=wD02X}#z@no7Ecz0FMPC81=xYELeFMOvZvj~J9RQ2I2Vl_; z04(|u;8^s!*PXmTENa_8#Cbz4db_EFV_vWE%UE>6>*=vjE&7G_YSFJ`wdgmpT2w<; zi+(4oMSqahqCd%M(Mhse^cPtzIz`5!zX4ceMd`2|i(CLKiU44d8-PWT04(wVu&5pY zi@X3ViUMF!GyscY09X_Yz@j(+7R3XwC;@;)J^&Ua0Su&6Tt zi@E@?C=Gx`=>RP13c#Xn04(Ybz@i=iEb0lsqFw+j>J7l6J^;s}Mp5n!B8cyu)*?>h zC}*VK#(b0L+$gW{%UEzNSTqQLMI`_%Dg|Is832pQ0a!E` zfJH+9STq!XMZ*ACG#r3M7Xq;8A^;YR0ASHbfMe15QSPH6h;N}8>GxHO{xshK2}XI1 zU&f*_Q6BGNwP-Bu)uKwWS~QNV7L6yXMH9$s(L}OZG>NPhO(v^FQ^;!3R5BJ#17Oi~ z02a*vV9~_@ESd?xqACCuRRgeS766N81F+~402a*wV9{Iv7F`O!qRRkSbU6Tvt^i=s zl>jW72f(8F04!Pnz@n=FShNt}SX2?^?kIxz8k(-qXtijaQEE|?*Z5^Dx-QC7utY7o zp7v_dVzOFv16eIvLRO1zB&$VB$!gIuvRbs9tQM^xt3@lxShNa&MK=MkXf*(fZU$h{ z8UPmE0>GlR04%x{fJL_fuxK3si*5&C(Ru(D-2uR&4FD{<6M#i`0kCKz0E_MhV9_Q3 z7Tp8DqRjv-x)F|W^Pwss}|kaSi*f#UgMXs=%Fajs-+;=BdbN*$!gJm$ZFB!WGvbNz@jGrSo9)z^48WpS09f=Y0E=D& zVA1OU$D#+K+&e@N-<44!&Vy>ve)F}WH=?}8FJsZ$QJxQ%t3~h7UM<>BR*T*xt3~gT z)uQ*wYS9N|wdg~#TJ#ZFE&7i*i6FiU&8PR@Qj2z*kF5P1t3@rzYEdh)TGX1X7PTR( zMQ4%KqO-|ZbPfQE+5)hs9RQ2k1F)zA0E;>Tu&5INi#h|as0#p#(g0YL4#1+W04(YT zz@qK|Eb0NkqMiUO>IJ}}-T*A>1Hhtl0a$b%0E^BCI2JXHb}tq|d=1T?+iw=_jP(1O zcR>0^dyQYlB7d~!fi-GT2JO|NOtM;(MOKTl$!bv!SuGksR*Q1UYEgi!77Zk;MR{Z_ z$_HRk0RW2%0a#Q7z@lOR77YSmQ3(KxN@2Ed|n02U1fV9^i&77Ybp(J%lO4F_P+ zg#awN2!KT+09Z5GS zMGFB~vJpe4)3&5i10a)|`0E=D(V9`qeEP5G$MXvy`=v4p~y#~Od*8y1c1^|oR1YprV zfMe0a(eArM5MO)qx$7-zQGfHT#dTJ17J}+0E-d;SmXm> zQ6d0~k^op#AAm&-09cd^z@iiY7BvK5Q6m5rH3nc&695)91vnPfM7ukSAig!`M&s{l zQJncRG|ghX#xG;hnK7QCO=?jp?bV`|WVNUjSuJW!R*Tw@)uOY=YSGzbwdfqOTGW=T z7PTW|QF{OubpT*dM*tRe0$@>R02XxtU{M+Xi_!sD)D?h5-2hnB9e_nW09e!$fJMCk zSkxPUMSTERbS?mk&I4f4`2Z~H3&5fa09e!y;8=78p(qN!xHXc}29nod@WW{}mQi^*!yOtM;3MaH6P02a*xV9{&<7F`0sqB#I8 znhU_9O95DP832ne2Vl_^04%x^fJO5FSTrAiMGF8}bQJ)L76Pzn5de#>24K-O04%x| zfJN5Q_TC|+37Ofzw zMJvf_(JHc9bQ4)ET1{4qZYHZmYshNREo3ZO3&5gV0a$b!0E^ZEu;_LG7Oe+h(H#IR z+5o_!I{{d97XXVk0~5P(Gw0kG&{ zfMd~;7AR*U{aR*N1dt3^A= zYS9y9wdhH*TJ#iIEqa=)7Cl48qGthE^c(<-b^@?y7XXWP1F&ch0E_klu;_UJ7QFz# zq89;J^b!DzUIt*%D*!Bd6@W#r0kG(G02aLgz@j$+ShNp-MQ;JH=xqQNy#sJ8+7{zp zB7*ovnZf-dYSCrJqWv*mEII(R(rOw?z=&^X6+G z@2f>Ey%K(p@fyF3MSsP3ettwPIz@Z6=x?%GWX0;pT`h8v)uITpTI43HMUiB+$U|0( z>XFqVFByxX09X_az@iuc7R3UvC=P%{@c=AJ0AP_1fJKP_EJ^}kQGEawH2`2yG60KG z09e!zfJKb}SkxGRMNI%$)D(b4%>Y=`9Dqe<033_{jBz)9R4jVi{NCaXo~kkz8LWVNUrSuJW$R*O22)uN7MEb0Wn zqRs#;>H@%`GyoQ*1F)zo0E@Z-u&6r#i+TXCs3!o6dI7MgHvo(J0I=v>02ZAGz@qa3 zSkxDQMHc|Ds2>1}`U9}Y55S@ffMZc=tb3#g;ww%SaazVYBmMi0Qkk({04%x?fJGMpuxJDTi$(&lC;v{#F!k=3H< zWVL7pSuMJltQO5At3_30wWyk`7R@57MYG9RbO`{9<^Zs0E&z)z1z^!-04%y3fJIjT zu;@wv7R>`-(R=_FEdXHARRAnn2*9F604%y1fJN5;u;^L<7F`FxqU!-zv>1RzHvq6` z3Ba*vQmp$M5yW?$`G)mmwdiem&U0g|*Z5^DS`q7seOfJANqe7PMVkRwbT0sl?gL=a{QxX_0Dwgg0I02VzAz@jYxEZPddqHO@jqGhq} zG!ex2i0M!-SBtute$gYbUgMXs=s&TZLC>m1kJDZ)+Cf%}o*=75Pmi z8M0dRELkmjj;t2#BxBJo02b{AV9_1`7VQOK(enT-dI5k%F9NXWB>)z^48WpS09f=Y z0E=D&VA1OUEP4ZgMQ;MIXdeKJ-U49J+W;(j2Y^NU0a)}d0E^xOI2Jt?>z*xw_=cIU z!){lLt}rL2_hY@rFJsZiv7R+M)uIEmSBpL&t3{uZ)uMxBwdfF8E&7bC79A$5MMubL z(dT5f=nFCy9R*;~mjEpK3V=ml1F+~D02X}0E>PBV9~DtEcy+AMKu5{`W=8pe*m!PPk>|5hq3ObMG)T@bG!N@wJ5QL zgp;veit~K3TPI%T3 zZU8Lm4#1)w04(YWz@lCNEb0xwqCNmDIv0RN=K-+jd;k{p1z^zy04(YUz@q*DEb;@e zCtQHlM)uKUUwWx%w7L}6KqB1fTl>@M7FaV2&0I+B%0E>nJuxK~{ zi!KCU(M13(8UetfkpL_T0jUn2f(8704$mSz@mu& zESdyxEXs{@FBL(2oy{$xfLc^#z8gC^&TITK7EO=yYwySCaXo4kkz6&WVL868H+9jV9{j&EV>+kMOOf@=t=+<%>!W3d;k_L0ASHo z04!Pvz@kL}EV>$iMb`kZ=vn|4T?fFT>j7A_7=T4L0I+BY0E=z}V9`R9JjYZ4jyv8qM(M@rlUtU#7SuHwBR*SwQt3_Xt zvFK|67JUQ2qHh6M^c?_;z6W5@4*)Fs5r9R<09f=B0E>MDn6B%E3r0*fCMfJ#Pk(aC%MUmB_XtG)qLspAo$!bv?SuKhuV^IPC zi+lhqN(5k05&(GlC04!<-z@p{=EII># zMJ)hWbS40cQUO@h5`aam09e!-;8^5}cYh~>_=?O&ts~-{G1>`ZQJZ+L@yl4$Hr^Be zu3FTN_IfUAPgaXMkkz7&WVNUhSuN^JR*Slj)uJ@AT9i&!i@K7rs2c!_x&yGN2LOwD z0D9u&56Ji_QgL(RlzYIv;>VeF0c>0RW5o0kEh)0E_$pEXn|2Q6>P3vH)0= z4Zxxt02U1ZU{Nl>vFPl0cUKX_mt_X`=cq+jn7^eKi1!-5j70_Up3?W#qC(oMMMY$_ zsFjW72f(8F04!Pnz@n=FShNs;MT-DfbTt5r zt^r`twE!%-4uD111F&c@0E=z_V9^o)7TpNIqNM;VS_Z(P&QqQkUTi;j@hqR+`{(HCU3=qOn&`jV^`eMMG_z9y?h-;mX!Z^>Bn z9RQ2I2Vl_;04(|ufJMguSo9MBi;e@Z=w|>Hod96bF90n16@W#*0kEhBfJMIpu;>o} z7X1mpqLTnD`U`+XrvO;=Hvo&Q1Ra=Tkqh8hbTHn%TmOsb$o&YTB1;C=-04(YQz@l>j zSaco$i_QmNQC|QST>!wMegG`$55OWn0E;pJSd7?ozl=q*5?D;(e(f< zS`5IV8vt0e1b{_10JQW6`Y%o|nH>i*BR6TC|R=7Tr!(i`J9XqC3cH(FU?wbSGIYx{It9 zZ6vEjcayPb699|u0btQ)02bW~z@qyASad%Ciyi=A(SraidI*3;4+F4h3jm9@0XibUM<>1R*QC%)uKIQwP-I{Eqb1;7QH}Li(VwFMK6)nqL;~7 z^a=orUIk#$YXB^I9e_n|0I=vy02b{7V9{FuEP5M&MehKxXg>gp-UVRMdjKqYAAm(4 z0I=vo02X}&z@m=E`s58H;`dV9_xE z7X1XkqT>K8`Wb*lCjeOV3jm9L1z^!{04%BjVA1aYEcye0MSlXY=p+D({sLgpDF7Dz z4ZtG#v(&fAevNctkqdxD5dbW51F$F(;8=7x!F{O+;#+M#cYQ=H8freW=J9!rU&f+n zpXavYYEcaB)uLFkS`l@{!e|M6z0xL{^LHlhvXIWGqSsU{MMHiy8v3 zs1X2*8UwJX2>^?l0f`7PSCi(U|}&N(Eq1O8^$N0$@>V02Z|YV9{9s zEIJ#2Mdtvps4W1C+5sGkygv6%5yUs$+-QvQIV1g4^I6CCKCki1Sk&3)`Rs&R)P?qH zQ5sn-N++vDUCC-uH?msPovar1Age_^$!bwAvRc%ej75C_SadD`i_QaJ(fI%@>I=Z4 z3jkQu4}eAe0a)Y*U{MADi!uRNlm)<|YycMJ0I+BP0E=<~SQG$Y(Leweq5VBe{ zl&lsFBdbNj$!gJsWVPrbvRX8Pj71{>SQG?c(I@~GRRFMPGysdn0I+B*0E;RCSTqiR zMdJZjGy#A`69HH>34leD0a!EzfJIXQSTqfQMbiOTGy{M|7Xz?pCIE}70FFh2eC~V^ z#CM+gNKuJew8B_a?eiMHj74*No~gg9MRRGd7F|kKi!LLpMVFJ+qASR1(UoMiXdYQD znom}X7Le7VtH@Zi5P(IC09bT20E?~xV9~VzEV>SWMb`tcXfXhbZUA7>5&#z62*9GH z04!Ptz@p^eTC|?_YSA5JwP*ubExMDe7TrZwi#C$gqPxjz(I&E5bPriA z+DyixdjVK<9{`K)2Vl_y04#bCfJF}hu;^g`7Ht7w(N+K!Z3AG@BLFOV6o5sK0kCL0 z0E_+uz@o48XDIHlO7R*Rk|t3@x6)uI>4YSBw%wdiHCTJ#E8Eqax#7QIHsqSpaf z^acQn-UMLLJ^&WI1;C=W0a)}70E_kmu;^U?7QF|+qW1w<^Z@{iJ_KOVM*uAP7=T3w z09f=10E<2aV9`MU799d$(PscGIt*|u+Uaw*I3*U{VBSaDr544QPSO#d*Z5^D`qJm= zXPFtu=dQn^y;}4&SuOg8tQLJsR*SwPt3}_F)uJEBYSE8mwdfdGE&7R!MaKbH^fLg9 zP5`jz7XTLh3c#Y@09aH5z@py)So8+~i~a;)(MbRn{RP0HQvfXb8-PVtq7K`!$OXWn z2mltj0az3Xz#szq0t%Ue{U*Z5^Dic9od9ibM* z(_Sq~Age__vRaf#R*RCzYEgZ%TGW877A2F_q7<@P)R2rtjR08G7=T4h09e!%fJMy! zSkxSVMP~r8s09Fv&IDjlDgcXG0XPU_CW82`G4G?LsYS)+-Pn>uukp)RG&s?d+=8k=3H%WVPr*vRZTz zSuGktR*OcG)uJF-EgD6}q6z>OjRs)R7yuTH1z=Gn0E@-}uxLC0izWcDXd(cMCIPT$ zG60LF0I+B(0E?ypuxL5}i)H|@=wbjC%>-ak6#$E>0a!E(fJL(bjzwjO?w%ruZ;W{Z zwp=axPkjlOBzlcs#-hs-Jwu|^qRVNo7F|JBi>@TAMf1pN(R{L6w1BJ@T}4)l7LwJX zMP#+;YBCmG1Hhtd0a$b$0E?~%V9{a#7To~Aq9p(GlR04%x{fJL_f9E;{Ax-S<&eDhO9oJ-ZBQRe2+ zx%UHA_(Q|vOT68Dv)uOw|YSBirT68yAE!sp@i|!$-MVrZL(Y<7~=svPqbUzu3 z9spp`g8(dg2!KTo1F&cd0E@N)uxJ|qiyi@B(W3w?dJKR?+W}bg9{?6T4#1)v04#a} zfJILNu;?iO7CjBXqGteD^eh02oPJm<4`b76`5yV$y-p0Q}EoyDP5V9-LYy2`6 zJ)h_~60a7$Kzp_5MY3A-5?L*JnXDGQLRO1jC96fRk=3Ht$!gIXWVPr`G8XLvV9{Fu zEP5M&MehKxXg>gp-UVRMdjKqYAAm(40I=vo02X}&z@m=An&>rt8H>J2^t4M< zi@v43TJ#-RE&86U7X3h0i+&`lMaRf$(NAQx=r~y|`kAa2ogib;F90n16@W#*0kEhB zfJMIpu;>o}7X1mpqLTnD`U`+XrvO;=Hvo&QBptS6kqdxD5dbW51F$F(fJGhv7S#h_ zkr#kPQ2;E824GPPz_IA7M0cSG;`_Lji1W2tG{AfxEjGz({4y5#l04Jvt3`>lSBsL! zYEgZ%TGW877A2F_q7<@P)R3$eH6p7;jmc_J6EYSx1z=G#02Va|V9^->ENTJ3qB8+l zlnTJ2mH;ej1;C=#04!<)z@oDNSadc3i_QUHQCk2OwF6*LdjJ-70ANu^02XxuU{PlP z7IgtQ7R4vIZxTU#n>`{0KlR`02UPiu&5Y-MS}oXR06=FQUDf}0UV3ECb>Tn zL3{(u;J%w$^pmluJjrYPG8PR>^8DFQEgDXHwdg{!T67UvEgC^qi$;>wq99o<8bwx% zD#&WlXtG)~hKxmH0a#QCz@l*gEE*5Mq6q*jnh3z6NdPRG48Wo(04$mcz@ljYESe6$ zq8R`zx)^{(GXYps1;CwZhF^4)uOR2 zC0v^1HGUb3u1xayo2W(eXs;H{C#yvZ$ZFA5WVL7^SuI*bR*SACt3}t4)uL<3YSDFM zEV>?mMT-GgbOQj3mH@EmMgSHq1z^!K02VC=V9^Qy7Oeze(JBBI-2}j*)c`EI8GuD= z09bSj0E^ZFu;^9*7TpHGqICc)x*dQ;>j92MmnXT$i6FjjydusOYSBRx?nv?)zl=p2 zlRVcpQ;Y7Vy;`)1tQOrvR*N>1)uMaJYSDdUwdj7bTJ!)}Eqaiw7Cl79qK5%kv;}}g zTLDJpsU?CjnUW6ab5!24K-M04#bI zfJM&%uxKX$i*^C9Xg2_h_5d7u0D% zFVkKvdWEbOy-HS#UL&hTuaniHH^^$yn`E_UA6YGWi>wyCO~#^k09dpifJN^Du;@Ji z7QGL^q7MLA^dSI?J_2CT#{euk0KlS809f=X0E-R+u;>r~i#`Kj(P01<9RXm`=Kw7F z0)RzF0a)}U0E@l?I2OH-e#=fW)EivC}{5r{N{4y4OpX6zfsuuk~d$s6C zvRZVEtQP%5R*R04)uNxtYS9U@TJ#H9E&7$L7X3!Xq8b1e{SLsQKLA+tCjg610W z02ZABVA0*}ZL44OIi8$Y>MN`b%Aqn-p#xG-0{ra9^t<<6hv{#Fg$!bvwSuJWv zR*M>u)uP5^wWtYMEow?ui<*(uqUK~QIs<@3EdW?_CIE|40a(-$fJLnUSkxMTMQs3B zbQS=M&IVx7IRGqb3&5gw04!<`z@iQSEb0irqD}xT>I}f5E&wb_17J})0E@Z;9E%d` zyRQ^MeA(u%V^V!*q`zL|@pP;2HGUb3de!&b(MB!mO?$Pd4_Pfbm#h|@M^=l@C#yw$ z$!gIBWVNUtSuN^MR*U>(EXn|2Q6>P3vH)0=4Zxxt02U1ZU{Njrivj>F8VJCmJOCEu z1F)z7fJKD>EGhzEQ856E1_7|B1b{`Q04yp4U{N^$iv|O*Xb8Zus7HPGUJ=B%+`M(x zQ!RSX9ZE0#Q-dt3BaN%02WmP zuxJ(li)I6`=n?=H%>iK1TmTkb3c#Yv09bT6z_Dm}eRs?`Vo`VV!L$q2qL<9K8n3AD zHGUb37S#82Xr~rkMSHbqAz3Y2L{^KgCaXo)kkz7V$!gJcWVPsevRbs5tQOrs#-b$v zEV>bZMN0u#v^i*5#B(Ha02-2%X(wE!%-6@W#z z0kCKt0E=!1V9|O27Tp2Bq748nx)b17G_St9SOoFiEzvVyEn3z{!d>;f#xJXZ72#!ss@@?DXs+N}3G5HDkV@YYrf1hPp-IKH1T2}Am8`@je`N?l}w5!-3MsjeVWmP9{%D1dJ$=?=Q*5%3RgDh))@+GB~wJ7ybERe7o&5cH%eptY+a$|+ zFnR72%i5a!+%(I2EZK9hW$j4LtFo-8lUK~Ltewg4Ut(E%lh3%+vR+CabGc=`mVDop zmbEYW$N84EKe@+3%laVsva2oYK=Q6@E$dLScd=!Co?NiRvc5`QwbZh{Oa5@VWgSaC zbCqSCNUmIMSvAQItg)<q;^IpL9o8iun(L(_AU$e{}8c zN-_T>XKz=E`9BrUccqyB6tBN4WzA06A+8kj-%{neQq2D=l5~2^A{egT`A^I z^v!XlOg<#L$CYCKNY;E;iuo%?i(Dz@&(vJ!N-=+DWQi-q{Go{Dt`zf4|C?MX=BwJb zxKhk_ZP&R{%$FrMxKhlw-R^d!n6E3{>q;@-H+j&NV!kl2)sTq$P!`JF4p3?PoVQcMr9ba7d`Y4J{n!5!@ux&6+mv|B81zP_7j5m)nchx4t**GP-{(&86djJcrR2)jkA zAKz{#E$Sux_SVKV^Xw*XJ>Rm8)%Ye|NLyJod$pQR`k|}cT)W9z2X6f0O1sJI z*l8oI#&Q_gOBvxbsh70r&4=!m3FM`?AANGN-R9O0-@o0osh70>{=KW`T8-t1up6zQ z(Px{kdgxNS(fl`Gy4-Gb|HF?yDM((F&4JfyuCUv*xM5`*yUmu9 zn?7(B^!K*wewbr5{YV?hi>a6N%dPKho+AxpHE!5-z*)*`8((qSa9EY$qgbGz$Vt|Zr42@PW13C$A98zs3C8(CIF8!I;U0zsDL zZfLm^&W$}Uwoh!Jft+Ua8Bx{K!!o2^q|2RfL2Rr%?M&tp=xr;ln#*+|%6{OntZ4gz z_!Xlw^f)t&ZQzQHt!)?=Z@HsbTx@K7Y+P(_nN577I#VUcRADRS)2Opd)LBY2>yo6i zw4be=WqqBcPSrpfd1}`qIbL3zS#pZ~Kwdz@&aQqgfiIsT@0NW@S~_b7p#(x=)uGGbc`+SUquerPXD^^r@9y zDyCG<>C$=1^f47vx>QZ5m|59nX63ZXs*0*Em0g2X)w9M4gTAYr+Gb>$K@WM>S^w7lIn>{^~BWc z?`bKpL#ijf^Z!Be)ayUq)1Y1hPyI7Jo_cxmP?lS-i>HNDnQe4EcYNpZo<@?Q>s??) zM7mNuK2v<2Hl_%-T@;MQCawO-J76-FS zN`isH!T$U}R?uHEpu8Zvu*~9#g6z^#|A6dZSy53izo>A4Rgyg*nC{Qa4NZ|*R$4CY zGm8p}^Rvrj%JRa1PM4FJ8ysCbp}!<6SXfjh6PIR}lx1gyo*7syGc7MHEiW!EGEW4H z14Fa(gE>Vd1^zN;i88CYlV{`?W#$F5{AK=NVR=DDc8Pf%MJ3ME-Fk;FxUeW#TAopw zSrRalYZ!XK6O^JB)hb@NY>DqQ+Jt$ZDH0uyTo4_w&rZNg38nY!c(!y6XP#7#{!F_b)(sSxel36mWxU5KCa(;fWxF}Fq zmaQ+jt4{BiDn~}QuEA>i6=cBMI&{Azi^oDy4qRTyREdS)Lw%uu{yK@J?!Q4Ds;M>bU8kPrA0Y8!8#MC z_o*{=roS*)R^l%#EeMp^b1upDXAQGoOhz4HOG^DRBYRiN23E0IW>INou(Yg5wrRHL zsQb{_Hg#qac07e%u-fC#x0f6&D$XtpJ%`E}C4m9CWreaugQeMJW#(9B(K(s+T#mJ?tgg3r_>t2a}CNVcl1~^~rSEe4)7o0wp>AV0LC^Fg+unhk0h5L(x99WCi>K zf<@(J#pPwe!A1FHa{Pp5!O>t&D(3WKPF-O~XIA#$fLsSM%1fQCEXPLp`N%nxjLfo; z&B1N9M_BWcp>jwEiw0+xCcAXBDK8=opCEt_>`_UZC~wz3UNi)t@Z=CmJrPS3j~ z+4O=QJ*R%Gt;n zJjk}4sG2x_TIJYO>E_Q2t&vf_C`Xnk9@U=3YtIsynMJ`|IeUc~u=xs#vYZzv9fQ!5 znc4aI<@x>+ISvK{N=12dHRH7+9;XFo9n++_y%p-5*UL*Y>??Y(G*`MW&XjV-C7Jo9%Zb!!mu;&yYg+irH&e(3BDCUJU9K-I~WIfZq)vUm-$Cr@)EU`~gp zoruCa6>@5@4{3W_gpQQ-9(88K;lzsxyS~@4V;-w#C`|VV&W85x;i-vlavV1qJ@lTA1x4 zeJwVN9G>>3(xcqin{L}Nps+kOvrnH?GuG~$o@z$hX}!C4Pi;H1a!O@IRb{)>PE*Is znALa8^qJL_b2?4!)=fb5gjrKZOC2|5dPQ|78LIb{1AeRlGUd1#vwL)^n$c-&dQTx0 zGsjHmD`WTBy*o|qJXJ>j9mZD8=rC?ZYNzq3or=1qc9Jn+-!ZZRoyJYAtg5OQU)gC& z<+SnD6Z)nJat^3Y#uQ28W=$JYJ#qT9PE|5&mRcojY(;fNDBCZwR~`TCeeYasO#j{9 zk=cbs<#N8Uy{+5R4qdUNv*ynT^)5>l?#T)EoF0beE^ zO>@-_O~78WM?|$dQ;w-j=>uf=WtgOAOtVbs;XA9_tJZY6wmYouaKsE2OxGYFqXDNA z;k-^;wu$-Er_V^Y?9%lg>r&?eU8mn$Aalwn8v2hGnfY>Zmn*6{AKBZ+If2?25wo|_ z)4J+& zwvqIf?FY^f(MD;ZshmfgEW^5ec4t+_G};A|gV&jxyr{6P64t=<{#=Q{PSp#VX|zr$>v}PP42wv@vdoxd9pZ z$*w4rYnj|hV3D>WW<`u90qKSg7a4*X240$Mh0t2l5e}E$HaOGXRIGzpx6>}n{!(*8 zEOakLj-k*@LnASNhJ9-+^hDT(EXgkW*Y2==CS=HL*2EcY+3O^o6nPD-lZ+Q-P!`Ax z*q4`Lzg%7HspJ~rJdoqF&g9PB!pvM5$7bi-lgKbOG`rC8k~1V&F1M>>W9kfbesZ&l zEhr}reP~8vx|X$blEHbYIWN|FX(svC?kGFA&JDOa-QZBSnz5!cG-500Cars9vajsz zA$=Zad&mGRYkQJYz#KGt@?vAQ z8Rv7y`?R4?Xy0V!WY+GNbaUgGCF$J@=Nf76Xy>lEc^H24*&dsncHXG%F=l1|mp-G} z!NanhK`8^Yy2rkem!SonGkZPEon-rgbAPK+P>Jzz87yZF}qU8==fQe3f$o`O+Z^AIR5s zNlHsI^=+3r+W~ozQEpypPhq;#HMdJw=L%V8l~{q$X*#sQ!cJUfn8$=H!Vx`m;k36_ z_)SY&gnzs4I%na~T`uNpznQ{O4>Y^Aq}(}!ne#1N&(5+>>)sa)8^_4a6MGlRmHMAb z@gn4OCs!lwyX%`I41jvoX-Es{kc!<|(iI8oqwr+ttsJhE&fvn)O;+C?AX)!6-zevO zcIORJdqL)wEZZqut2*zh=msn=%quJ!;%r|=M&`D>nUOQ>U``ow6I$M4v)}%(pEkoD zo($`M)VbkeuTQ#OzRaM=2Ii)x{lK{~YaTKTN)Nx^sdF{=)^p@w3%|cqcX&c~$eyX} zw$OUnN32}s%KRm!|0qY5^i}@bksEebR@XS)xut4m>kPPfy>e4uyE}GQg!}sT^21K& zdI&iEqtI8(z}OFj~r0x=JunrYIV**{$lCG50$ZVokJsR^_=bC z9CExKjvOPWyw`jBO-Q>VmE#ZZrO<*&&6&f#wmvAWL7wl|w>QhWQ=9SYRWLf*rq=f*lS z7%MF=mA9pIF#L~uk>)n!Y41bG{X@C&?%Xp;v%*vDFj3wD*LStd>X}hYXmG{yO~1gt z;QiY`*0^KjV{m5XlB2INU2bcIwkq4gxv?4cj=nRZus2S4Kh+-k4UucZ=^T_8K+-g=W=Vm#@ZXG&N~CFSZx=s&alPIUJitEd0DKRnT<2-upei7I;Www!(^{IlKIUTUY@gcOoaP2%XwuM~ zW;4(mP-2GFr)}OkLrde6eH@q}5Hn%bGX0sdrE`LIXTdUy=Tixcii}x$Ook7E99_ct zE@rUhoUY6*LbJJ?Qv^%2kNwjB_CBR9*so7IUSB@Pk@2HjW;W_(8Js*l|_up^Z%V)ji^HG1xk9@-L@&x((r2OTy z(2x0~U`9gJqKKs~%il+Eh55jp<&sa-Tb|yX3OdV}qR^_BMOh}3=((jd1bpCS$Waa;0X)UY47WxkbA`{TCE=PGM|+?IS(A?(L($#)jQe&nkY zVaY5n@wD8)-p1xtn(bR(*1uQS6lUt|({kx)nNPbpy~H-vR-3VUE%=|`lKrn24;lD{ zJ(q44mnFY3@+UpVnkpYcy~i~9bpw;}{ z0>jVLdY0A>TGO@m(%M&Rrq+PgBCX|GFVtG0b-dQ8TC23q)jCh>)mm@Rxo;0|(psZcPEhuCswbc5w6~+yWUbA#w$j>8 zYns+xS})L=tuerg9wMgq=ts}IK z)jC=0Os#XZ&ewXa)}>lkYh9;xqt^SiZqvF$>vLLP(E7U8{aQcPdRXh%T90Y{P3tMG z9=R--?G&fAf!3y4TWW2qwTsrCTKj6v(we8WMC&lEqqL6KI!)^=t(R+EsCBW{6(5&M(CU&8Rh#V-rPZgkq1H3Bw$a*2 zYfr8HwB~9Zq;uRm*wQknBRqGR4 zcWZrB>wc}DXg#X+N3AtlUGlv!^ZH`6CTnf2HC?XN=J~!_OXb>Za!~6md2I3mt!t#) zWAa9=Psjz{$xmoKE?;Fa&;PBpw|wEq z^PC&USJmt;N#8FzrWZy}7-UH)=i5(aB$HZ6zHMGkq7W6VjbL zOY6hkocxs56Fr>ll8%dMcW!T|4$wOPTqobC^@a1D{EpVReok(pwZ!k_pw?S5oxDlw zr`b;aR%@GFC#P$jG|ERUXub6!CvVnzXrzSS;5evh1OT5Ir)99i5ENh46TE!oIFPBx>-)XPwU}JocyEKwwF4&ht_GAJNYuLk6r2H zU0VN`?_}=+r}kgy)B>&7TGsC$-T7BSncF1wEky}llN#nxz@?iw>mXrol}dnUbo)KtF^wd!O0(MP2T9_mRg5z za`Jes8#X)nA+1O6bMntxJ3i>-K3Zo!?Bsb`cWia?^IA{I_l?c#jeXRqS=*gDNbBOq zoxDctKI!P2=|9oh@M$Nv)_T#iPM)asuANTaqV=oYPX0w}=jWY#p4RFYoxDKnlP^2@ zMXlCrPL9`_^M;d4wJzD`Vx-1LZz~d47o2 zZ+lW*7hUZj(cXl*V7H1m8rt)t~z+$K-gdarz)+vM$9e~^Kk$$x6?E?@9A*{}6d z`KGtY*J|Arqb*=T}&mNlGKx@7X1Wg{Mb)|e8+~hm7ejr~9H~9;#EmED_LF-ug zqPThfVy*YLaq{C@kI7fZ&GUb0?b*)BnOfJ$Ut}=P->3C4Q$3coNAo_dpJ@F?>u*{k zJ2~x>w6@UNL2GZV*;-4q22GXatkAkg>#thd$qgj){79`UwZ5qJcT>&l(ppcx=xuV0 z)&^P|X_fAf6%i$W+`v?sulX@my1jNi9N|=RA1oq4zKN^c>RdH zk=JUgv-ymv)p>MPmDO2372Das&dzO>|M9MjJ@Huc83wt}J8rtn$9`Nfdi2c7+0Lw# z%&eF;zEbDzpnsAn=4-Ax3t2s@v-$F5rF{J&Y%$|zR!o(N{3QjQE2^t!P8>a}T4wuy z@Y77Db;+;Umgc9sQ$qjBCbWNA%D-khw-f&{oq5juoFl)oOa8ahrO7m>FLx|6k>|`l zG(R2XH(GxC%dh!aev!+5Z1$;{#{8P)jga54=JF>XEGtz!;fF`V1cc9TpUm$T5y;HX zYy;*uQ6AGq9$GunT-MSsz{ATd>E*{){&TYc&Lv1?S*GH)dHR4%S1d3^9y33)-OVz?HkZ{= ze5nw|5A!o^!l&CH>-QNGNoBgwx27j{p57%jH8s6gTF>5TU3+)!EsxXE(!>7k*|WPz zUDJAXl?hWv#mvjj&vCxg@66b2Ddua)zQuO(bhn>wYc-KGUZ<~XieAazU-NWD!((U0 z_CMDDs#|lijz?6btd!QPGLVX79|~Rn&Cq-Wsdr zaQoj|?SDU>x?`ZQ^u0BQX6&trtaw{n#7=l5f4A_^9FDo-=AT`3qHz=VgspaqEqPmW z_tt!uwk06{?%X2FJTz)=P4ne{|90x{q7(C@tk#m|@2%OFeq`d%20dWKE-rj`{?`6&)6gT+O%Z<4oEfotzJ$bFEDUmV4!SgtHKcTo12$AFc1jjn#cW*k4`H(Hs3!W zuf5sIF4@0{#x%BUhly)ZgHL5Uvy&U zV3}WcnP30h)|qE{>%7(j+XUL=eqq0Yl0(*WR${~c@l6v_?L)|lnE!*fRfE*)tlojdL%CIV zZpst>>0wBGsAZi-{@6=4JQacVwdb*u2a~f0{qf zI`-@Wk~Oby=$ZcV%#P4A^QX6dtN-zeuD8kY8`*NN>>-T!sK!dYS*X?WqngOn)y4>U z6qV}KxWpCaEReJ!V61Q*DmvzBHZ(K#Q5pD8A^49dA;*n;Z3VgEQ!3~kwALaFW8G_f@@X}6q1*d81qdB+b8kXK$Y zu5f(b_<<7w6YMoITfv;C#^sG0I6g35mi*l)!-lr%mw%zY@_){2WL|J!Ffhuz^3c&X zB5<k%6G|I`wF~D6jLs9&M8+w6%{6=lu1peHQCrA8mu`9Bu3W86JA0xct&QJRZe9FG%8t8MJb&H3ksY6V>90?(+j+dpq~@nQ z(=T84b&p=F6W0z%=+wSbUccMgwX9!wPhnEuTefxC)caKT&5b_(qG8K8t9RE|>%DjQ zg714?n9=E_CWDXO*WcxuZ;sErojL7CyqNG%$;yqqU~JIeV*Tzu6%w()|->2ZXFjF-~8mZabI4M_GF7^e%RA2{1|@k+EFv_ z{ATrs7yBk2`O)*uSHh2KToHxn)sn@Wa_p#N4w>9AJ{$6!+!qa zqvipjT z*@tH={N?C-v5|A?H*R&L*P$uj9I~A4-(zoJz(r*ZZ}HwUW^`KjOU^vJs_Ex{P5AQI zfPLE+ZXTJvKSH+O+1*^)4~%qO5GU{ROqIc0gGSCNntvl)^)8VPYlJJRTKa4e5uV?q zD;E*reWj&z%>1q7aY5q(nK&ZSbB%QL-R&C4`Y~&r+R8o|upMg={H=0O?GSXwd zeh?Aqogy=GzbB`AcgF^PncTfFRsKm!E|bTeW%5rw^N;sYpZpVfxjc-_OK9wsVaZO@ z!Hha7^K?a>FC9cPR+W}f4@##xGU_o&o~U=E(^xO+S9$D>x<-}}6}34`_Z5F_tvL~U&$|CM=Esr;K5b&gD#6xCk-u3P=6YI(5@qHdCD zlA~UeZhJ~pBe}=kFzPcI<~54)x0W$*)bH|An?yY*_wJiU?G@fEYN>3>=20)mlr5sn zd)8urEt*!oDu%j=Wpts-pc|_pQg9AVAF5u zSN3ZfnLhjrH9eT#+SsOj(?@n((^~z~k2GxBy?3WhPd9y$uKAg!?&)#(vrW&YYkRKg zu=M+VzUkHUD_^MeOt+V;t2Cr{*1xVYHT|jqb(Lw=^yGY9r7c~}z`DvO=>n(JRklhW z_NjH11Jk9PSywqIeL&But6ZNxTxZu+9#89>y2@4QGktDdWoCLS=hamz=^ad~tE`{? z+xc~s0qK%1sH==j@95{c%B1xFeyOW0oE|33sjGaJeoMdBRkltat>5Y@zoc^`>no$v zJG!sF(j{HXm!(Sn0hO~#m5J%G)a+8_y!1A|Dph_<>+4eGmGp7>rc{}cJ{aGYDnF)= z#&@O4xb$iMzEmlt_wYlhvPXJ<>o-)!r;pJF4V5A3syA$?9G*V=8#PpxOmA%ChD!hR zRyJvs`e zMdgC@#wHe(mr{JMsN~0%?-!L`=>z#eQ5lfl^oK>|m~<^46_wU>fgcx@>(WQ*lcF*< zUCT@5%A4s|zFe-9(nt4|a%E_Gx388fbJC~$wQ}YCbV;w5E03g)#2e+xb1A-=4y51F zTjk1q>G<2_%30}h?`o;!pGGJlf1-c7%9LeI*y^uaoyXJtnER2|r}(mj2` z59(PtEQvk1XXTvq5j>=4Wu2sTV$aI3^pQWbXXS)+os)W2u1~**!+KVRrVBj0XXU$e zd~(mq6X};6(X;YeGI36JIq8yh~o(weSi#PmvidMj&8ue7HR z$ePnD=_$xgYfZ0=NFRxfAFa%n{@W&xR!&JD`5k6g?o0m**l~7cy>z)d&900~CdSOJ zuN!_^Fl_BZ(u=DK7sC3o4%x-=t{kMHP(od7j|02SE`No{|cE{%%kEBog z{`p4V^lK*M8;yzK0r|#h>BD$nzA-($l_S!pw0V*A5j`^BI5@qXqw>#_O96X_Qpmv6kBuI2cAV^;c&P92?YY>;l8k#8)NuJ+7)V_5nPo|SKW znSS4A=NrqVcX7y=bYnvL&`r!Yeo7aXA22uP*LUmkjn?$p&wmj#ub19?{;IO(f$4f0 z@{JGDhq1^vj!!1ik1*`id`A9rINunSN>jdZZF*moeB;jaiD=F@mP~KCCEs{I{hHQ% zV}EzHxN=H68iJl=SJ%f3Y`zmOf%#^NrD| zbjvrsNdMdEo^Sk|-dDcr=054um!8M$)O>8Z`1*Wf?es44*TOYVN&h2k$T!mOFa0jk zjr=7QjrqnU>Gzd?Rr97vTit&*(g(ag-{_GpBcJQka!qu1vf2^z?t0O&_|> zlhTd((qDv)yQEKbTSKvMv0_rtK73%OVv+b~9p+1OP^V(in0?Y*x>K=O%z4us+^JYR zX74nY=~OHcbDlJp?NlrovsaqSrGL3T=Gyor-}md!#ui zUDlx3-SbY@wRG%md8Z2-9J_1Y>B^RgUCldP+On}b@=n*bT|`?54ca^{o=SoOimu zRbw~iovv@S*hSvy`i94D$U9x%>ao)oC=OpbUEhe<^=S`I*SALO^wXM$4^G#&X6ytZ z{iN@HrBUhg-!VQxDi-?hA13H{Fa2pytW{ny|1T{GS+5wCaQ!D_{WuyzHi#KQHjEiU zHi{WSHjWuWHi;QRHjNoVHj5cTHjf!Xwuni{maz%hDmEb_V-vD>8Vp-C`56du&4X zh+Px1PU(pB`R|yK{_HB&tqGZ&{!}maEN3}c$iBr9iO+vR_KTw-WPHpJvVY7FG9hLN zIUr^TIWT4jIVffbIXGqrIV5HXnHZChLt_&%DK;U8#U|wN*n~`uO~?_k2{|%0AxFg~ z#)k4?x4u?aabHX$d)CgkMUgq#wakW*t5a$0OcPLEB$Yrq!xjZ%@SHvdd%GiWl6`PQ&V-s>s zY(lP$O~`ez3AsKtAv0nVazkuFZj4RHO|c1?8Jm!sV-s>qY(j30O~`Gr3AsIXO~{$0 z$I|D&33)s=Ay336 zCgjD~guE1+ke6c<@=9z%UX4x2Yq1G=JvJe4#3tm;*o3?ln~=9-6Y@^%nvlCnpQq1% z$E#koQZKgrj4x z^l+&7;6EYN1M=-ob>&Q_Q`d%~p)NfxNsqPiqnV;EPS2Niy4%}m_ene5Eic>irk(DV zH`%?@PIt>I_B?5)yXDPxue8(M@)mpUwA0=4R(r0r)7|pUcF(la-SRfON80&uO}o%N zhjfKqgl;*cOY9KRcM|>g(55O>b4VB2Rp`heU1c|+OAhHWy9@0(r0eVE2M(*OfL(K&toThd8CW znxZAslMKZ|b>++}D_X3s*f;&r^Pi%{oexDz*r8}iI~4V|L(u>`6fI?kqJefO8f1r} zrR`8O*rsS1fudyvik1^78X{0MRG?^>K+*C7MJosttte2ml0ebQ0!6C`6s;;yw3`=719g4QFL(!IYDB8*nMI&vBwiYPbMxbb0 zfuijMinbRh8YNIPTA*kLfubD+igpqx8Y56NR-kB{K+(3O`-*69f~fqDY{&s=n8?ND+P+K5-7S_py(QbqH6_;t`jJ_UZ7}(K+z2X zMK=l*-6T*nQ=sT(fudUkif$Dsx=oE=-g2B z!+(#(>dM(yR&;+|kzeHcPtgO;hoT4VQ1p-;iXOH@(Ia*!deja@kJ+Kx6DWFLs42R)u5?2JQhhALxzGKg^a5G&L0vif%8EXzD_%&i zZ2hO`Q|Cj`|LjoonH`Egw?okvb}0JN4n?!~HQS-6 z#STTSb|~s>hoUw+6t&x-sEZwnI&6xn0!3W~in<9Dbr&e=AyCv)plB|EqPYc%dI=QG zBT&>^plDu!qCNse^9dC76)2itplAVsq6Gzt`Uw;*Bv7=lK+z&XO;J%_8kT@m2d9_9 zi^lreBmK7YRARAceL4Heik7S|wplb3^>;oL4X{JeQg$dBXosRfb|_lf4n>3QP_&F4 zik7uQ(Q-CLLj;P33KR_!C|X{iXa#|y6$Oe`5-3_(plB6=qE!WoRud>1E>N_(K+y<+ zqBR7H))XjOOQ2|NfueN;iq;hU=2L%nn7H+o5O+I}~kchoY_QP&CpGMO)jUXd62eZEI7soj}p{0!5<) zibe|*?I2LJqd?J40!3p4ipB~QjT0!^S)gbafudanigpty+FhV%4}qdR1&a0(DB4?~ zXdi*1eFcj46KaY!sxLjBfK=bjkI^;`Mg8($Z{zFB*;iI{V14m<`hK?m?iU^8d?-5D z4n>F9p=hEViVn3y(Ih(*9cG83!|hNs*$zcV*c2TpP;`_)(a{1$#|RW1D^PTtK+*96 zMJEUpohVRrl0ebP0!60?6rCzibecfX=>kPl1d65#6rCYZbf!SjSpr383lyCr)D%sq zFSYbficZhZIvx;;`sY8G&aE$JUs=%w^~I7)g`(-shoTGZP;`+UiY~T8(Is{$y3`Iu zm)W7{ayt}VVTYnCZHlfED7spp=o*2dYXyp~6DYb~plF6b(G3DcHwqNpBv3R{py+0S zqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzYKo@Smo`a2s{iDttIrQbUD6lw z6!+Dav#+e^q55L{piuO%^P%VwI}|-?hoZ;qQ1rMRik`4T(UW#4dddz(PurpB8JnVK z1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+XLpM#k3dmx zfueZ@iuwo?%_mUQSDL*aNkU-JG0!51m6fG)Hw3tBA;zCVPQ>nDz za`|tx{1j28RC}b~TA#)erE>O_6)jaNMhp!_1Dy{=gX~bWv>l2D+o5O~I}|Nzhoa@| zP&C92MMLdSG|Z-Gd4Zx81d3J^C|XINXk~$-RRoGw6)0LwplG;2(dq(4BLs@p5GYzx zplB_DqO}Ez))6RLSD6dfy2beurZ@d8CB2o#+tP;`<& z(a8curwA0CDo}KqK+)*}MNacu=`ruHsVODg0shoXfMHiKd9;<|+i=7Wem)N1`Qacn~W{0B7?ND@u9g42B zL(x@sD7xAXMc3FAT`N#@oj}p`0!1?fif#}nx>2C$CV`@v0!23q6x||FbgMwoZ30EN z3l!ZUP;{q2(Om*XcMBBVBT#g&K+$~yMfVF7Js{K+O)r&JNIQG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOp zhXO?(2^4)SQ1ppF(WgR9(Zi+EkqJokr2M7UkA$KL`Cgw?k1EI}~-;p{QzyqONu* z>Sl+c?sh2ZVTYogHbrv@6wNJA)Jvdf9)Y6X0!8x*6!j4(nopppuRziK0!0f56fG!F z)K8#jA%UWW1&S6CC|XpYXfc7J#RZC%5GYzwps2r4Q`FK>>bz!BG$nm!a?#pQd!+wb z{=U=!4dv`BD_Xjt7_fFI8ti;1TE-4V%i5u6IXe^$u|v^NI}{DGL(%efC|bb|MJw7A ztt3#ivOv))0!6C|6s;yuG+dx)b%CN00!3>G6s;*xw3a~8+5$!E2o$X=P_&*v(fR^K z8weC_C{VPKK+(nmMVkl|Z7S3h4Qwc-e+ITwbx!`e>p`JtY#y66l(Vm_Xsd=|!n&bo zr1PO@YdaKeV~3(`?NGFx9g4QML(wQZ6pgk+(GGSf+R>(HCxN0d0!3p5ipB{P?JQ8V zi$Kw?0!6zC6zwihw1+^^o&rUC2^8%uP_&Og(Y^vj`w0|{7bx0aplE_X(E$QQ2MQD& zB-9jb(NLO}fK;!@cc`}vMfYSy2RD?nudHZN`o7lnL(yT*hoZynP&C;NMMv17=tw&h z9c722qwP?1j2()OwL{TyHbut^6rCVYbfQ4fNdiSD3lyCqP;{z5(P;ujrwbHK5h$7} zP;`bs(U}58X9*OYEl_lhK+(AZMdt|=O%o_OU!dp$fuiX`P0_@L(uWC1_4hQ3LqpLH z`6 zq8S23HwYBnC{T2hK+#NrqMHSZZV@QDRiNlLfuh?5itZ37x>KO&E`g%E1&ZzwD7sgm z=stm>`vr;~5GZ<3py(liqKAc=qKg|!3nd`c9orL}OF~ilC;rj{wuW-{l@&eFP^`I0 zD0!nV27d??NIcRP0`B&MXv}Hy(&=jnn2O( z0!42K6ul`>^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&KY^mp z1d2WvYKk6fDD9DeR9DS^i9H^Q7Hdu8i-vOcl@)!}P@J+^DEiv@Q1p!*ioUf&(RX$z z`rZyjKiHw@M>`b#WQU@k?NIcKP0<{IqF)7yeiJDAU7+X>fucVJivAKP`dgsrAAzEO z1&Y$QWnYj!zzua2)d>{U3lycNe``l5Y7i(Y1d193ipl~-O#(#~fud%Cq86d1XjVh% z<^-fVCO=(0I~0AHAL+LiQWT1Y!Qk&oDW4+I}~-bLs2(76m_>lQ4c#5^|V9L zTy`j$+YUv&Y>MU)DC#XxG_OEWAAzFz1d93!6wNPCw17a-f&xYT1d0|CC|X#cXc2*; zMFol$6DV3-plAt!q9p~2`U?~d5GYzoplF~_Q`Am;qqG5I@THX#tE7+lEMLQI&WQU@a?NGFeP0^|XMXL!E z4Hqa{U7%=$K+zfkMQaKattC*jwm{K30!8Zz6s;#vw7x*m1_DJJ3KVT5P_(f?(Ix^# zn+g5-2)Ypy&{RqKQIH(a557 zbOKTxn7{6N>rgZ^|MaRui*ojr6-_RRE4B+oM>rpfj*rDiHI}{yf zhoa-{P;`PFicYjCI!U1DWPzen1d2`-C^}7`=yZXiDFQ`P1&YoPC^}Q1=q!PvvjvLI z5hyxWpy)h-qG z0!0rC6g?tP^r%45V?s^QWksodbW(Ir{^RHJP_%D;1?2IfoPA|QPZ!0&9YfJG&WECB z?NIcb9g3c}L(vO%D0iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&tpCs6d6K+)#{MPCRMeJM~hOQeLvI!6~W}D5@7IDhU)d z2ox0pMU4VQWr3n5fuf2)QL{i%i$GDUKv8FbqBfzX=||UI4k-l6y2NeUAH%u zv#+eEYh!WWxKPy1`B2o|4n;leP}I{7MRVDqXl^?c^|C|JJa#DRZHJw^Xm)-Ia_h!&_LUWF-&m}@dng*^d?*@ihoT+qP_&~RigvO?(HJ`v zjkQD3I6D;WY=@#IXjDB4Y+Xm^34Jp_vO6e!wDplEM_qJ0F4_7y1FPoQYLK+*mJ zMH2*y4iG3hP@w1_fue&2iVhJdnkZ0os6f#qfuh5NnxbtROM4|C)!zBu^>(3XYW|Y7 z!yC)lS5|aXV{zJ^q3CGmL(wsIC_2^-MaS8p=y*F6onVKe6YWrRk{yapwnNb=Hbtij z6rCnebh<#%6oI0t0!3#C6rCwhbe2HT*#br92o#+wP;{O^(KLag^97175Ga~1P;{X{ z(M1A97Yh_!B2aXxK+$DFP0O2c3I7fz}N%;?^%NxttS5|a&WAWPFq39at zL(#Q%D7wxLMc3P*Xoek%Zm>hqjdm!y$qq#`?ND^HP0=j^MYjqR-6l|UyFk$$0!4QU z6x}6Ibhkj!Jpx7d3KZQZP;|dQ(E|cS4+<1LBvACQK+z)tMUM&;Jtk1}xIobp0!2>> zHAPo8mVQq_swWl+&Q+mkME+uq38uW6uoGNqL=JY^s*g_ zUa>>bt9B@Q%??Gc+o9+Uo1!-birx|^dRw6A9f6{E1&ZDiD0*L@=mUYG4+V-o5-9pu zpy(5UqE7{i{wGlMnLyF!0!3d46n!aBG)tgpwm{KW0!3d7HAT-fmR3nXsz>G5(Vh)O z$CT3erm>uTWko+U7CY=8ihguH6#Zm}qMz+h^ot#e=GdX=S34B_W{0BR?NIcG9g6<6 zDf&yG=x>3de*}vD6)5Udj)(0O)d>{U3lxr38uw3KR_zC|X*eXs|%hG6F@*3KT6T z)D(3qm!3^Ps{7=ph`N_+kMuXpf1?d4m$R>|XoYg|^+BO%Mdw4&N_Hq(*$zdk*r8}u zI~1*Ehoa$jC|cbPMI-D`w1!R5ngT^@2^6g@P_&Lf(YgXf>j@OCFHp3BK+%Q*MH>ke zZ7fi_LUXwP%f697>aguJ{0X_hoUidC>m>rqH%U8+Sv|8yV#*qJspA4i+dnM4)J* zK+&NBMUw=I4ihLkT%c&OK+zFGP0^@wX{!XJTAyEl9UY3k>zl@r<#P6w6&+hH4xSW> zj&nW~9dC!C6YNlQq8*A(vP03yb|^Z<4n?Qhq3AR_6rFBUG)16jszA{h0!3#E6rCkd zbhbdzIRZuJ3KX3uP&7@T=zM{q3j~U$3lv=_P;`+%(ZvEqmk1PHDo}KpK+)v_MOO$E zT`ANQ9bGP6n1ECd&rcB@6N)D0=dQ0Rm$R>|=(=+8z~Q0jdgnvY3_BFvV27d`?ND@+ z9g1e!q3C8i6y0KnqFe1ybem1l?E*!22o&8ZP;{3-(cJX|*OW`2CLq;8`K$M@ z4MiX1=Zl^#m$R>|=*4o;aAYWY$@x(9vK@+Eu|v_Tb|`wy4n?oqq38`e6uoJOqPOf& z^tMgWI|4=T3KYF3Q1re)(FX!W9|{zGBvACRK+z`xMV|^3{ZF9iGl8Pd1&Y29DEd;M zXqG_HY=NS$1d6^EDEdaA=v#rJ?}VD7=gXzV5|HXuT@#!aLeY`=OZmSqm$R>|=;v~= z?$M#>7w1FK96J>KYKNlV>`?T(9g6<2L(!jhDEi9|MSt6&=pUP+e+7yII5Q0!0l1MTJ07qd-wvpr}cps3K6*EKt-UP}C|=)LEdYO`xbj@OCFHp3BK+%Q*MH>keZ7fiCXhDT9+T`uM~<7>7K^urgHX`6^&^s zdY=@E#yTI0#@V50XFC+_Vuzw#?NGFv9g23hL(v{~DB9BwMSIy4?JZEWk3iAB0!8}? z6pa@s+Fzh(fX@c-_LUW#&{XVnN+>$f`A~F{9g0r2L(wUA zC_2>+MW@-J=yW?2O|e7KR67)%VN-ObK+#zOMP~~Xog+|mu0YXw0!7mViq01(xE9u_EiM4;$VfuhF*iXImz zdP1P+Nr9rL1d5&(D0)Vq=vjfH=LCwL7ix;GZz?^XfK<0_N^oX`qSx}b6}`|@&c3pu zSDK1%r-Y(coexE?*`erlI~2WPhoU#_Q1q4^ir%(E(K~i1de;s`@7WZ+FHrP>K+%T+ zMIQ+ieJoJ)i9pe(0!9B5DEdsG=yQRhF9eFd6eyY{P&8Yh=qrJuuLX*}5h(grpy)e+ zqVENYeh?`7QK%_;sj1X;YEm>af8F)Vp=j0oC2K!5m9wv`=+~xVnKMJtZ_bCJ-|bNJ zhaHOkv_sKfb}0JW4n_aiq3B;b6m_b^P}EbXDf*?Uv~>bf zeYkIeGba>1n-$GfDQ90Oiu&21 zXdyckEo@V?h(OVz0!51n6fG`Lw1hy>k^)8j1&Rg;6fGrCG*F;ukU-JW0!4!bik1;5 zT2`QFIf0@f0!2dwiiQakEiX{Cfmgs+6;@ ztZ21L@zA-UXt?vCXmvXjjj%(}8g?jJ(+)*z*`a7{I~1*BhoW`uP_&*+(fR^K8weC_ zC{VPKK+(nmMVkl|Z7NW-nLyFz0!3R06m2O`w3R^7NP(iQ1&X#2DB4z_Xgh(T?FEWP z2^5VMDB3}wXh)%@Xq8Iovjn8NRQ}^<)ljre`ftTfm2&o#742Lp8qW_!yEq?;cC|y% zZgwcz-3~>2*r8}oI~46@hoZghP_&O7iuScB+E1WpygV=JX4 z5|HX=`C-|(P}DpBS#*4*oPA|QCs&H~r-!0boDW5(+M(z)I~1L6hoUKVD4J@AqBHDJ zbfz7O&ay+%*)~Pz2o#+wP;{O^(KLag^97175Ga~1P;{X{(M1A97Yh_!B2aXxK+$Ca zMVAW{T_I3(r9jbD0!3E~6kQ`wbge+qbpl1#3pGV2R!aLNAk{VUHxHc@ipJ&F^k-Dc z*;iIHvr?RKQ7F3E`A~F=9g1$XL(y$^D7xJaMR(Yt=uSHn-DQWOyX{bPk4@3N0!8-; z6x}aS^ngIog91el2^2jnQ1pmE(W3%Ij|mh#E>QG@K+%%|MNbJ7JuOi5j6l(|0!7aW z6g@9c^nyUqivmS22{lDGR!Vm!Ak}jIy6c-l(F0l0%awBWl@+~SDc-sy6usemD0->ckNL0o*jzbw?okfb}0JLrsyMqqK^fNJ`pJTRG{d80!5z*6n!pG z^o2mtmjXqz1d3)06n!O7^tC|IHv&c93KV@OQ1rb((GLPeKMEB6BvACTK+!KkP0_2B z(%%V4_1pZS$7`Wz-Fzo$PNkfEWkr8fiawWzqCcGvMSt0$=x;j|{bPrsf9+7zsW~3G zhoU+=6xG|IsAPwt2AiTnpr}!xs4P&_Bv4clC~6icY7r=E6)5T~P}C++)GkoeMWCod zpr|TP)K#FUn?O-_fubG)MLh+I<`O8HTcD_yP*e0Oiu&21XdyckEo_IPMeIQEq7Cd&w4qJWMgm0}3lwc4P_(H)(Pjcgn+p_eAyBlX zK+#qLMI!}@wiYPbMxbb0fuijMinbRh8YNIPTA*kLfubD+igpqx8Y56NR;Vc&-duVy z0jW;Pe~GOgiU#Me3>nv4&c3pu-I|NqJspA4i+dnM4)J*K+&NBMUw=I4ihLkT%c&OK+zEb zMMnx09VJk7v_R1@0!7CP6dfl}bi6>(2?9kY3N=N$G?%(xmlR!{Ujf-Q6rG;G2jryY za`u%Koz`3|HzO3C?tCbkVuzxsb|^Z-4n=3$q3A3-6rF8{qI2v}bgmtW&a)|+CQx*~ zK+y#PMbia}E)*!bNTBFqfuc(UiY^r>x=f(xa)F{N1d6T{D7s3Z=xTwYYXpj}6)3t+ zpy+ymq8S23HwYBnDAW|4(p=g$0jYMhB{-*sqJ{FEq??+{*;iI{YjZK_#!z&d^P%W= zI~3hvhoU>}P;{3aite^U(LHu3y4Max_t~N7ew(5P1d1LMD0)bs=wX4PM+Ax<6)1X4 zpy+Xdq9+83o)jp0N}%Xzfud&wik=lHdQPC|d4ZxA1d3i1D0)et=w*STR|JY)6>5rZ zZZ2J#fK)%o5AJUXMTcfZuQivmudL{;=Hii=q3CVrL(w~SD0fudG{qRs+EZ30E@0!3W}iaG>}sscq_1&X=}6m=IU>LF0nQ=n)rfugwu zih2nY%_C6MTcBuOp{D51=2HIzq`KvT3C>@k=+pe%L)`NCr~s*plGN-(J+CcW(Hnv02CN@Qz3KVT7P_(%~(G~(lTM86yB~Ua{plEA>qHP3* zkX>8K*;iJyXG`(U-JxhN=R?unb|~7%4n_Ogp=dul6pgn-(f)QQnqY^b1MEbV+D$i6DT@f zpy&jFq7wy*P7)|OS)k|?p{8i}meRioNVP71-Sr-!=#})}ic?$4*;iIHwWa8LUnn}m z`A~GG9g5DfL($oGC_2XuMd#X~=sY_VO|wJM`F1F}z@})rK+%N)MHdMaT`W*^i9pe% z0!5bz6kRS*bcI0Cl>$Xq2^3u|P;`wz(X|3a*9jC|FHkf?py&pHq8kN@ZW1V(DNuB? zP*ZezOKFV+q!F-JI_i-O^IdzOte_T8fL($!KD7wcEMfcjF z=sr6X-EW7Y2kcPvpdE@HvMG94py&~SqDKXa9up{fT%hO)fubh`ik=cEdRn098G)i_ z1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+Xv(%8 znv;L@!<#MT>?eQJlI|JkAF zGn=B%1&Y29DEd;MXqG_HY=NS$1d6^EDEdaA=v#rJ?*xjz7byBcpy)?|qMrnceikVD zMWASoK+&%PMZXCY{Vq`Shd|MvLQT=zEv1(ekm`H+>FRev(TVx5x4&A-*;iK7skQj= zkx*3E8js{dQN10CN_Hq}utQN{hoVM16qW5z)MSUEiXDoYZHih1idqGVItvuF2^6&p z6m=0O>JTWZ3KVq}DC#Cq)Lo#chd@zJfugwtislw5>LpM#k3dmxfueZ@iuwo?%_mUQ zSEwoar=`^M(WIz%e!l46P&6!)n!mN2ePu-pwH8Ak4@C<*ABq;SL(!skC|b-8MT^^^ zXbC$MEoq0M{&pxDV27fmY>Ea76b%w6T3VoJut3o=0!7OT6fGxEG(@0is6f#$fuiLF zidGOPT2Y{AC4r)q1&US?C|XsZXf=VN;Q~dg3lxnIC|X0PDO#|#w0#0ny)OUcnSQOc zNBYO+muA;&EoWa@(Yme0;ZKI5^_&ky>)WAd13MILXosSW>`=6^9f~%wL(!&oDB8>p zMVs3cZ6Q#!r9jbE0!1SQinbOg+D4#gTY;kO1d6s7C>kYDG+Ll&2Z5p;1&VeOC>kSB zG*+N!oIuge0!6zB6zwWdw3|TD?m|t`+O4I_6OiiF3nVz}grYh52Z-#^TF$<*qJ3J6 z$DR&F`#K+r_OnCLcsmsBZ-=4@b|^Z)4n+srq39qx6di1bqC;$oCJGcCDo`{@py)7x zqQeD>CJPiDAy9OrK+#bGMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD3lyCqP;{z5 z(P;ujrwcVjd$pEkB_P#3^4DGO9f~IBCy%DImb0&{=&aVF`MFSZw)3Ir96J=9Ylouq z>`*k#4n^nNq38lT6iv57(S>#>y2z&JVu7Md1d1*dD7s9b=yHLgD+G$J6ezk%py+CW zqH6?-t`#V{PN3*|fub1#MK=f(-6&9WlR(i-fufrQif$1ox>ca)Hle2IjMmap2}pH^ z{B_r7hN7qQOS8APmb0&{=%D0*I?=mmkI7X^x55-56E zpy(BWqE`iqUK1#KU7+X}yF$^4&1t;TTF$<* zq7Pb&b6yHXA37h3KC(m6$95?C#12KD+M(!wb}0JH4n?2aq38=c6n$w^G)tgpwm{KW z0!3d76n!I5^sPYAcLGJ<3l#kzQ1qif(N6+JKMNH7B2Y9(py*eDqTd9HeitbEL!jtS zfug?zivAWT`bVfKdat!~Zvs;NJAX0A`=RK@u4(++TF$<*qEhGLz4Ux`x8Vaj6%C#L z|0Dgv4n>W2C@R~bsL2jR6+09)+o7n%4n?hYDC%re)Fx2WE>P4(pr}Kjs47s@RiLPw zKv8#rq8P&A)FQD1?g`2~s=5GYzus41%J zT&jCDDOx9gsdatl+GDiw-O}jSxtx7vMT>SW7I-}rE#`duS+uwvik7fL(UNv3>Tidl z0d^=_$__;X?NBtx4n<4b6b%+AT1KE~S%ISE1d4_T6b%(98YWP*yg<>Wp=b*`6m4mTqOEL- zMhX;dEl{+LK+(1WMcWA!Z7)zXN}y=8K+z5YMLP-`?Tu9f}^YL(!vlD0<8eMUUH| z=n0#mCk2Y05-56Fpy(NaqGtt)o)ai~UZCg&fua`$ie3^ZdRd_86@j8x1&Ur1D0*F> z=na9QHwB8`5-56Gpy(ZeqIU&~-VzUx(8;Uyeouv0Wm$R>|=;O}C z5g&!3Pn-`$pW315e|9MP%nn7L+o9+SI~09shoV__D4K1DqOWXp`az)RM}eZB1d4tZDEdX9XpTV9uL4EC2^9SfjLEWLQTJTWZ3KVq}DC#Cq)Lo#chd@zJfugwtislw5 z>LpM#k3dmxfueZ@iuwo?%_mUQSDL*aNkU-JGLQPRaTj{F=q3Q zP_&F4ik7u0T27#7h(OU$fudmoMav5mtsqdeqCn9~0!1qe6s;mqw5mYSY63;W1&US| zC>kM9w1z;@ngT^@2^6g@P_&Lf(YgXf>j^bQi?x*oB_P#r^Gj!ohoV9G<≧%Gp;| zv~gRp=@+4B6X!$GrgkXW%nn7H+o5O+I}~kchoY_QP&CpGMO)jUXd9cNZ3T+96DZnV zplFmp(P)999R!MY6e!wBplFOh(O7|^aRNm<3l!}lP_(N+(QX1oy9*TUAyBlZK+#?T zMSBYr?ITdMuTWF8VO!~-1f)8mPlB^iDC(MD0okvuoPA|Q2ecLE%?d>aIvnt2oxPDP;`_)(a{1$#|RW1D^PTtK+*96 zMJEUpohVRrl0ebP0!60?6rCzibecfX=>kPl1d65#6rCYZbf!SjSpr383pGXix0UWs zK&mbIFR=-sX#f8nu(g%5udL|&w&H`YLeT}zhob3rD7w%NMHktj=wdq*U1Eo#OYKl} znH`EQw?oktHbqwo6kR1ybhSXyH3CJ~3KU%@P;|XO(F}p28w84O6ezk$plGH*(ai!y zw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--HAUyOl}cYHMLqMgj?+TXi25|{Z7XMA zSIMqKEBJ^oSjb9<@W!V|FNd+zv%g*rDi2I}|--hoYx#ik=ZDdRCz5 zIf0_*1&Uq}D0)$#=p})omj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6 zJ%OV41&TfpDEd&SDZ0O{v`zw2?bkQKc_0*RQ%d8bwsQ8B75%TR*!}xZ^qKRa=yN+1 zePM^9FYQn?%ML}e?NIcU9g4oTL(w;ODEii>=sSU;?*)o}5GeXlpy(%oqMrqdei0~| zBT)3KK+$gkMZXIa{UK2Fr$EtP0!4od6#XMm^shisr}lW*PEnmeQN2J>Nua1fs44oS zt#o<|pg>VSfue;3iWU|qT122|QGuexgqosqd+GHAr20jEy1J>o_DKKo{1vl{ zx0kc8tY|=cG3Vz{w3PFqXrLX62HBx#X*(1RwnNb}b|_lb4n@n^p=gL5iiX-04HGC@ zUZ7|Nfua=!idGURT3MiI6@j8v1&US^C>kzMw7Nji2!WzC1d7%aC|XOPXl;R_bp(pm z6)0LyplE%8q74L!HWX@#mTWK0^Gi}RGArsIijK?ot~Y8gXJ1*-X6?m_zlNgCoexD@ z*r8}kI}~kYhoX^oDB9W%Mcde+Xj?lJZD)s~?QM!i2^5VMDB3}wXh(sfodk-;2o#MK zC>keFw6j3bE&@fn3KZ=oP_(;1(H;UtdkPfoB~Y}tK+!$|Mf(aA?I%z)UZ7}yp{8h) z_R@|CNcHagg=w3HqUQXte?ogX`^t(AZZD4dJro_{d?=b|hoVF6P&CO7MTgm;=x{p} zO}0bP5q2m#(hfyO*%TcuP;`ty(Xj$W#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@ z6rCLubK+&B7MRy4l z-7Qdbk3iAA0!8-;6x}b>6kX6>`X&LXE}dpEJrwoJuf{&mUe3O`?Tz z9g4oOL(#W(DEiJ0Mc><@=m(pk9|ekj5-9pvpy(HYqB#OZzX}xnCQ$UdK+zupMSltu z{UuQJw?NT90!9A{6m{wn58ElK6DX<|C@KjQH3$?H0!57iMP;F;=(G0HAqhzJpN_DK+%#yO;K}~(t`;|b$Y%l)Y7H)NdM8SsDGDo_LUV4>Qa2v z5Q>&|J`@eML(wvJC|cGIMa$WtXoww(hT5TMm>r6iw?okiHbpB66s;ssw6Z|aDgs5T z3KXp-P&8biXmx?25duYP2o$X;P_&jn(b@t<>j)IBD^RqaK+*aFMH>hdZ75K*kwDSL z0!5n$HAPExDHTOhG$y}}HZT;enqQ6Gv`abr%8It^QY>5!MO!%^ibmR@XlpwZZDWU` zZS7FBogIp{w?ok=I~0w!L(vX4MLP-EguF%*4}6;1C_&c3puOS+_= ztQLwcbv_hbW{0B7?ND@u9g42BL(x@sD7xAXMc3G&=vq4zU1w8ty+F|nfub7(if$Ar zx=EmDra;ln0!6n76x}LNbellY?E*!22o&8ZP;{3-(cJ`?Tq9g3c_L(%hgD0;yTMK9VEy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1 zQ1rGy(K`Y~?+O&XCs6dhK+y*RMIQ`?Th z9g2RkL($JRMZX9X%@HX2RiNlMfui39ivAEN`ct6jFM*=J1&aO=DEe2Rs8dHgY^SJB zpr~G;s3cI-AW&2Y6g3JIl?95L1d1vGMa@D@(U)CHV-k?+==|0DvqI5YozrOPC}&?; zQF}*mOf?jBaXu7v*rBLuhoY`_DC%a1qV9Gm>S2eXo^~jj%ML|z+Z6Q@D4Iv0sJB4T zyaGji1d8SpDC#RvG`~R60s=(~3KaDdC|XFMXkme(MFff#6)0LvplES{q9p{1mJ}%J zFHkfDmOOdUcWDv~|=T>93NXbsX4H&c3puWjcyyx`m=;oexFJ*`a8N z9g2q9p=g*Lik7!S(F%4bTG0+gE7_rFWt*Z^1d3J_C|XURXt+Sp>H;8$qq$hY>LJT6pa%o+F77z7lEQ(1&VePDB4}1Xb*v+Jq3#P5-8eRplBa~qJ0I5 z_7f-?FHp3ye@8{rS_F*ip{D zvZBK~iY@03MU$NmMMv17=tw&h9c722qwP?1j2()OwL{Tyb|^aD4n-%}6rCtgbdo^P z$pS^E2o#+vP;{C=(dhz3Qv`~p3KX3oP;{n1(OCjTXA2aaBT#g%K+$;uMbiX|&KD@U zK%i*4K+%N)MHdM*MUy&8hbAD^+2sW1uu$}29v63%v#+e^@{VHqJfY|c=R?tzb||{a z4ng;13KYF2Q1rS$(HjCqZweH>B~bLXK+!t_Mehm}y(dugzCh6j0!1GR z6n!L6^szwECjv#E3KacMpy)G!qR$12z7Qz-Qm83gs$b>Sl+c z?sh2ZVTYogb|{+54n=d@p{SP~isrFHQE!`~c?F942o%jHP}EnTXnujB1q6x~6e#K^ zP_&Rh(ZT{niwG1gDp0hTK+)m?MN0@2Eh$jcU!Z7!K+#eHMFRzj1_=}`Ez}fssg}-6 zK&toWhh-hr+9Umo5}smkwVZurMMJ8^ZT&*gQ0GI@Fgp}2Z-=54>`=6#9g0@6L($51 zC|bo1MXTDOXf>On;Q~dg3lxnIC|X0HXib5lwFHXR7ARUrplDrzqV)ud))y$+K%i(t zfufBBiZ&J~+C-peQ-Pw*1d28nDB41xXiI^jt%RDQWvivP6Od|Ke$ivOP&DJe2W-`H z_LUWFS1tZnI23K~d?*@ahoaGTDB8geMLXJ|XeT=qjj=<~SUVJrvqRC&HbuJ#6zwWd zw3|TD?gB-72o&upP_&mo(cS_@`v?^6D^RqbK+$-CqWuMmCI}QAAW(FmK+!=0MF$HM z9U@RPQK0Bhfuc!5P0=>h(tL{~MR(?}yWTbwJ(a(!@vv$+`^t)rtQM;-7K)B?J`^2o zhoWQbP;{&vijK2G(eZXDI>8P_C)%OtBs&zHY*TcKK+&lJMW+cAoi0!`MWAS^K+zcj zMP~{Woh49owm{K20!8Nv6rCqfG)`pd;rI#!{Q~^n)D+s9&NF#-!=+Z(_ znjs)!0V{|o_KIDx_ujF0MX`&D9Xoau%X^+P=dsyv-}m!8@8|vfe((Foo6jel`#pB9 znc10Ru9<5#yQp7IM<>bcoqF4#fRi>#uDYGHL*(mdLuqT|U6PcvE9FEONqe%5cWEecC|z)7xm;Qkg^7w0qhY5DR$)bvkV*VAzZrM)a~w`8Za@8>u} z(hltJI3v<7ALuxv(mo&LIAhZWWjRh^T78b=j8D67u;Y}b{XNuiD$@!_I8II4`u!Yd zYTDLOjx#;2;~2-8kv2Wgapt65S>QPH({>g)&cd|J@s6`Jtzm-WG^9OH>NqRYoC?P| zI<0t;M5S??4?1Vt{hHGUn1fsjHm)#JE4!cSALm;aEn|+@^RR25j z{(-3ef6{{jQT-2rvjb86A6@v_l#@^MD>dz zℑHlm6!fqWV$o3j$I7tnH>iR6i_vc_6BvcDp(d)sHJ(7l`WTO>PQA^#cR91)};F z-**L~`X{^h1)};lmk$M^`bTqH0#W^|rzZnZ{j-&415y3EgBJr)edBm*Agb^Dy&j0_ zTQ_e9qI&OrdmySePj>{OdiU$oKvZvE>q{v3$vDSUSzs(tXE z0jK%da-g_Z`-fboKjhd+9@3_7*l{{{m%(jdaPz1<)}JTkCP`q^gSi2x%e~F?nKAlU zp!d_IcW+@s3Y1L{k}tnqR>|=g80xVLB%i442%YONkLmfKv;1~#(^c4rmK)`Hr|X24 z5=L5>q+ve`kI7*i*uSO7Dw91Ws~s3+&y;nSFxtY@&Jqr=5YsTm!dUt0^T1dO?R16n zEQI7rCy;O97U?Jg1%Bvuxh(84c~ODPfYUut=|)Og?-<`bFv*Q9yW*PS?tv;d@?E%B zyY7K%H!^uh^Hxr`WO+&2Vwm3|xy>n$ZQgm5G)Zpr#KuRDJKAd#diLX~(k8jhjys<^ zai!C3s;t1vy6yZ%Nh#x;ZifncPuQ_6y2Zu~E4}%gv*)=#8dwaOQw+%F(%v-Vi0n!q-V>wGQGv@`0$&%j`i9UUH5c_*XF|yKiqMo z)9nmtquXMG-zK@u`d{AK;&0Tg58wW~Jd%xZxHZ!_BImMv{`BTV<( zB)7TnrVC$@3B-~+&b#v+bCuKMJZY6QSUkDGntw|3&DZa_PnIt0 z@x?d4U!;2@xy{B8*FWL!^!GR3E<62cTaVod>+!bDXi$!~5t7@y^2XgK=pJ$-XFYXr zp*NrFPu>2T?jSdEfBz$0r^j|_(@NK3r##TDG2d_OMjrm|i7sB-W3nIU?zR2%lZzhI zm*7U`Mp|@rx?Lm(v%c<2Sl;)iUiYXjFS*SRmtK9bzv5TC@z#s};qm6$8TF!(bY{Az zwz8Zym-RiwYqRm@dq43v`q=08Z|^PV)R$%~a=P6nO>{Xy`PB}f%{_OWD6d9d*7zCM zN?X}H&wh5#87hPuNqcGDVyD~B)?|b=iM-i7BrjXm?A|SRZu8gdtlQRID34^1TypZ8 z_sUT*NV-zpx21j~Z{HRQ(`Bz_M%hD-=;19pym|I4Z`s?gduNNk?4eJVjB|R7mnL0h zlcrC%wzAI2ZLWRz+$;T^`po5TUE&|ff4zFi+ST3~e0=R!mmljmJww{r^(squ9Q{pB z3MTh@QZBFbH@R=HS+9eH>ThyTo*5~fyZ$Eskd)jjD(4OTO%BO3pGv2#zsbMJGn?hg zOn;MiO1MBC=x_2DNy$#2O`vbfcFlt=yR@uLYZGXlCPwygnm0c{kmCe9I>DCvHQ&Ga z$mS*ORj% z{rN@$fs%IGq(x7eU6wRy*)Gt$dE=~FwQzzdtVi?aEt*G~kC3V4teZGh8<{F$ZQEM3 zg|xF-O4LQQw^@46HqNqx&C;goD2?34^+;!(YOdJp6!bsCbe%rTut$;UW4X9mV} zVnz1pRMM_Zpl$Nl==u4bbh%yJga%1z_vXtM@0vIh-D2HNIX)nJCdb<--Pa!ZZ@-lsN zp8U!aTJ#dbf1+tyKb`K)VUiZ+FezaUlM?4J>9T(_hk%@z<3Ib!qkvPTrMsNM0#2-IYE_r%qvQ2L!l~7Aq8#h~6Z+_C`IRTM{2G5kA9+_#PHlYgO&-YB zl~&bSbOi#=fsGrcT9>{_esv+$m+2#aUI#J@xp;EqWG_GRoc-t|i9dgHt4u0L{V!x9Cv z>*g%4uUnSzoK7!OkIY(HzhKdVh6O9?oUHjv7S(0VTv)dcbnX~6FSp5I`YAic)S>l$M zH$N+{e$Mg*i6d75GGz%7Zk;0tIRI&xG*^i@pFML%SVoUZp8Ht zhTyP(>$dw(KW-p7I4|IK2zJVJQ%1RN@^rUtav)P4jFt!O+;%1ae()rqua5o z_n?E@v77gxz1y+L?6TZ6*$*9i=#%o$Uqmmdk#x63a`1a+l-os8=PY+XFSkoKVOg$j z^A_x`cK+@fV7tqUneue5J4hz$qI1c12WSg#ir(&jZlDWlk$k}awy8V!${Lj8b{QxO z(HD`{J3BkrpzG?T0ro)Gf!FBOVCVGUTqgUMXWcHrXr|jaIA33BlXj9P+O~rKr@S|3 z`q6u}_xXTe%XC>{ec}?C@;_CU!1Lt9+P=H@68zo3D%er^pZA&!#N8GX-7Y2CI4f(O z`Qi)H_1|oi|8|bL0{!=q4SS^j3jGxt?ajD_^c-a0LtfDV>Q@K!>YwPN&L-E}lwIUy z$&oi8+wI&%U{9MDFP8d0TE)(N+%Ep>^H#W@tnjL)E8JNQ`YwZHIjke|@AW@f*A_Ch zZq%M`YSQHP^BND-iT~z6ZIL-oUtm^-G+-%>uda`5(bnnG&yMvDuEFVUhfGQ3O;WJc zsJ-%pgxp3BOzj!FXSqFkxNT%1+EKNk8%Wbv)XL4U&F;lac{gSWTa+3PmNh0f|imh`usd+38Kv5&`b5&Ovo>e0(> z-CbW}=TWki+qoIN*kJ#|ZQer~W%qD1`mot`F8}v-TTfY!?qzO|eZ3vkUCv`|x+TwJ zuj`BGUgAB~BHLScIYV^uUX^uO|Lr04|Mwf-cI*GYv)>5*b!^fR0qr^hZl7Lmnx6V? z$F%Yf*gkf^dNJK?ovYfdOBxky*YJPn@CyDS$NK-*El(OIZwgPMB9!7%Q)+k%_B|s%nY~V!3CyOmXsi{;lA7t8#sOAaiG zH~E)WR#K*0)0;-OWPWzyik6heYFY3|Te+O#CX*CYO{=V_ke6Iq8mp`*DX%HAmz-5camBCO|v9}wF%JU=^Iu*s$vAjZmHbcFsbc(!k> za{RQI?CUbw%LREgB^BlVb{ZLPm{X9@vZQKKEMFWeEUESv#MfsFVbc}o$ng=Yt|%^!HJLbPWRs~2 z^2%d1Re9yrWhFJViBX3vB1~#!-W<_;Dth%N`wrP>*X#3FL zHce)da6H9du-TJW>Mc1|QCUBQQki8V>%pzt zBcXZKR5_$$6_bmqic2e|?7h&c@^SHQQ@qM6i%(EeDV>?^;!5dG68lr{B~^1nhV#RqSdX%#dZ3?|B zBCA$WTO|+V7%MI!F4n-9uO%EHE zEZuNfMV0Oj?I-R$iA0jyw*;4vYL$($U^h0^5m3m3h5GM?<5{V zvZ?59ODn4FARZB4pzH>J3+D5n$lKw|7R*~*Hz!^0+}6hzr#@E{%j`sw#xAe%7Dc*o>Q&v&vuf3f0<4+b8m6q0)=2eO0<4UTTs-e1RTY3{wmCY^R| zb-s7Hj#ZDBYZHG;>CWib5*ArjBwdwVw6G+dUyk&We!C*iqveYeU%pNuy?=bg3v&zY zlvq_%UMRLE^uO^PT;N^&m@~2!7tgDU)h(X0VCLeO9!v3=m6Vnijms;wLr%`}g>uX{ zp5{E?<7cFVy__?miSee&c$rheMOGm%OLp#FPLyc(w^zrLco898fp-Xdnx zBMu+-R>JwbWO3olhMBR6bw}37o#6P({kP|}MuSQVE4(f>ej2g8?e84vZfvLKIu=H_xWo3DdOBW~Q>Wa-F z$E>%|#^X9C$Ma)cd2M>Z$dT##o=Rp;y1uKDJtB8VdjI;mg>^HR)eT6`STuX-^3k)G z)Hl?v%vdyduz-g7%NNa(I(OlcnGG58mdt4B1?DJ_Dd#R-F*IY@(u_Gd!-UMNpFMxH zyhpQQM8=}bMe;7szH^o>-FNQN^o)7w85Ozd8FKG`^lVvyjJb>ImMxn(uP$R@-Qsx- z^G9b3@{h6%?PMhBwrp6iWO2qad3!|aGGTK>qImXR;_xO0di&fzz33IYw*!mHD{7?^ zO4ubsNBX;@>6Lc;j3pOqdHE%!B?mTMEoVzN+^BHL;yHCIy;%%y(z!PF1bR5dMQrq0 z&OXvd)X0UWp2g!6uur`aQsb_cW3E813G(w~*kqlo`Y%`f{^}2J^k2^PK5IHW(ZPdW zDwN3Rz`v;Qj^9F0#Ra8HmMqP2ypsDb>*5{l|0~}kVGT-{#rl+VOGN-zjzROitU+>RThKK)VW&9IFRZ)Sim4ES@Bg0&; zi9a~5mbU{NFIn|0*LbZb17kb(b)fIcGU|_ep!VWZ~N%8*_z{1S)oda=f)^Zgko z!y*65DgJ~ftzI2hlxx@HT@K{@m(SYaBjZC8sBu`>bhM`q#&u^!sw+!kHfq=X!6-8? zJ~uhzFk`*YvSr9Mv^~m^Ax3=t61G5PRmJ!c8F$LAD3@z*xsSmjJwtoapHRX;;3=dCB3X~ zqzqViX|fgKYt3bNqV%4@1>UA&9dzCHx=6^Y*4uIMJ2`R;#b+8H2j=B_H|F9`By7m4 zqMCnuz3%mg4A^x|{IQ<5PI93nuYq-v(W(pyOA1Q7lUZe+oXfnaDp`m$t$}Lo7aP6Q zN&fA{F*~=(?Y}11>GA7+M!NpMjICgswCRz_zVfz*Tz~o7Lxz6|+e1%!ItGeWPbsO9 zXA;iMj1zMjZ!+Xa&+IIlFIQyo5x0&Cy#>hW-g}^rjuJ14<2QzKxiO^UM>Z5Q)2kWhP_OUP zRn*}dlO&EcNgs%PYa9w!xgIT;AurQjyKTPc`{~f+5xD+a;;J% zcR=KRtX;Lq)H!-H+gmID7JXUX)L21zjh#^v?@)W|_pj$ie@w@Vjo-=hX4!bFJ4bH3 zB_2Hu5xinsa%yM-fn2TE~&0Auy=l% zYzGX+NV$J%mkUe$(STQS{nKQVRbmC=eRX_;CG=i8?qot1;oBZRdwQ=Z@xG}i!oNHD z`dxASMjP|>-p}FC2kLIEs+Dfc8wKRmEz8LrQMB0mBgVoyuaqoa&``bHeWm;M% zE_=P{&D(^*mD~hk@K-X~+a>-0YOh)Ff~9|y)0bWH+j}~U&xSYgmKJgaD@Q`1T)QM( z)bM2dohMGN{+Ptuj(X?S8^8IY=zU&RDp8asZ`Ifft}UNfUNOb*_!;)-y?&jqKbl}p z`EqAl-naAKQ}LeGF%3^9Tvjx>m*cHoj-8cs#Nz?Ilj=S2@Am3L#yB~NH&Jb_dc(e0 z4j*n}u~7fD(f`;1n{Yq2>BxjDA#cI51LEuM9j9`FtI4a`KSG3gHa}Z}|y5xry&z8pUsk%2Chtjdi8GPnhH1$@ONVH%`3= z{$({w*5146i79@#CLUq_n#e4?qdmSo3QF_JDihA?{$|#9{B*vJZ+$fm4049VJ4HQ6 zy!q;_QGeB%^gMZ$a{WG42G30-Pgp&FJNO3=uZLqm1(r9N_r4qIT|*V;C0?M=f=P8v z62=>HhP18gpF#9#e_+5OEB&i&xdRyAE}kdSzr;a7Sz(hQr+Cgji|@Te(HgsDy(OOb z&J?Tbzie-_$tLx-U(-=Q<1FOOQ!d(AXU1XGwbk-|n2m$~Nfnki?rN*-dVt zG>#DEy?1*%O;=9`F!6B}%h#&`?=<)C#<1#+%E!1&=TdC1F-Pv7#kVTk!oRPY@TUa+ zV8YutiI=F}sBenAJ*;n#SJ*qgtdf6gU*8_w`&6N)Kz&1HYx6c4RjN{*STx7)i2R$hx+xL|LcTc(7cV;G@*C*wLY>_2Em*kM4OIW9 z_eyOevWD>sD}Ml^bIZ}YipKCOKEt*v~XO6t_SHs6P zytfYcIL3hg{6>O)A|)cf|HzMguIT8NkrqxLh4!PLQps=G|Ab~Irk<2?a(Hd>I`@>& z`rxTarw5$8kuuRt{qTnq$dZTdh>WsK8D^9_$!)@AsljF`ZA0w?9Rg{=XrNP|bD&G0 zYoL2lFa6l=zx*Vkkn_Voi4z3%BMJ#WLHleCD5#%MNcaiLrxWDkY6(9fM?RYDWXC7- zpMO0e>+_rBvqS!m|Ga*Bh^)`gh<}2o@l!qee9(zE^d=9+KZ5N=d0sxPm+%vGntl>1 z=*Y)^5`Kb?d~7e_C+MwxBM3V3;jVsHhK*H*U2u!QGZ%j3em z@|3-D-ClXwUirwq^4h(!d>ujjN0)b1Jjn<3^l_7qp!8{Q`baPE-;W9s-aW|H!SCMh z&nBKJa}v&!+45eJe`7vz3K{RlXP7N-VI-s>@^)b3bMjW9{K)qyIL-7Uk+Na6*2t$? zn#m``=4zFX`ss(mn{{@a6hkB|+L z57g-NE40dTPS+~a>&J_m$^YWJ+4AG|{OgwWW54?Uvwo^o+Mg$SYP${Mv(EP>t&(?H z?Jth#{Ksk)UZ_>RhhwT`wL3`^)qWyLRMTTYYX_^+#7UB!+Ec4M+26SK2|As+r**W| ze5;jK^&@!t{A{a-T0PwAYO5z&J;Ul|tM^%b#Ojk)pSQZz>YG-#Tm9JTPOINpm9L5L z*5?nadLZfg>9+`IjaY4KHELDA9!{UvFHz7s(5ieQ+snhOjb-dMbt2I^+v^vA; zT&oMM)>~a^^;oMXT3v7T46El^-DLGjtJhh*#p+#FAF#T`>eE(Vw7SjeyH-E4y3^|S zR)4knmsR~{2i-o+t+ut=$!faQeXM3$9cp!y)dH&%tWL73U)-Sck6G2@Q}ZIL4OWk` zdc4(Bte#=@e5;pQy~e732ba$8POA@Ceaz~!R$sCDrq%bYerok=t3O)(-Kw6>bpBzh zEv1*@-FeaGq!t6y0C&gw5#wg1%Z6O?{ZYcs2DtVXT&u-eaRhSecf z_qUpFwZv+r)hSjFv07(!q19zpS6MyI>N=|%t?I{xbv-Y!dbQOXt=?hveydxoK4bM| zt8ZA{ZuJwZUs?UZ>Taw5SWTAmfG)p<)%I59!{;9FWp#knT&w$AEwox@b+Xl%)%jKr zx2j)>q02kL>ISRlTD{b&{znKp-ECIyx2oqe1f& z&T3byeXV9%9d1>>gGSqxSgo>pkkvU>7g=3lb+y%XR?oDmUxT6ZyUOZKR`0g@h}CDT zZngT3)sL-yZS`lXe_2hI^R~{vmDNsGM_4VE%T0a0%IbW%+|=A)b-kR+HJ@koCb`_y ze4o{qT)gJx)JjiODTwrMXdaE}M^z(gIe;DNFzpW0J3lW{Z(CRTceqL|& z3Awt{=eJr-l?xWl9j#W3@bh%5=kDj{E3Lja%FjEk_8jBqOsn(q{M=ym<^n%IVD+aW zKRd;K9XZ~w#a35O@bd<%PnG)lHLJ}l{2aA9X_B80v3h>BpRcz1zFctW>-)-T@2P&y zwz}XzKd-QQ>vTUqWc8Or{G1f?>;5zSI^ODWv;BO!)o1Gb{JPZ^^Zne}YW1Oho?-RE zg?`>_^~1$}{>EzG!~L9V^{{1rUTO9A<$iv|>TgH*IkeKRqgVNLg4Gj__VXE5pOY_M z(e3l5)mF#(xvSOM6Z|~O>cuDd`8ul~t@ZPFR`*%&=OI=XZSeCdt9PF6=Pg!$mkV57 ze)5@q9dou{ORb)CuAk4c`oj5se%orBi~QW(>Xc1>o@4crOZ|L<)lV+>^De6cuJZFR zt4pr&^U+rCzShr=TitWLpHpt|Yu-(MEw{S%7C)b3^`+bV{I1n@cltTq>a@H4JlE=F z_xkxJtDoKP=O3-^`;ebUSUvm^KObxL-YtH9(&}H2`?=W@el2*)ua#C$dB)G@S$*X> zKX13%;YC09vUz+jdJiq%in8l={P@G-EBOW;q$Q7 zh*p_@n&mE5(~a+IIm_x0<9SxgtsZ1`zSZSckGHzf>L#n#TfN8X6IQosmDiD!>DS>_ zCt6)?b)D4*t?shgTfRq5+fT82n$;~f)W&1yE^%bkztZuiu!|In-zqR_S)jzDt$K$>E zg{`)>+TLn6t39ozII^wf^+c?;vzlhLr`5hz2U*RwI>BnW)mp35tj@MN&+1~U^;R#i zDyJ`RJ><0H)oZQZV)YKIavJcS-(vL{t1noUZr6KWx>v96u==Uh@2vi4Rk|r}y1%SS zx8h~#KD;W2rC0k~6@9!co6oEJSv|mNk<}8b)mEoiP1fbe#%^uPlj6-shI3y1ILWVi zk2gtnM%1{Ix$MYA4Krs+ZK(I_d>+Zi1R9)7{kwc8bJntDPNsa4AX8zcf1C5a`dbWd z+By2CR`QK8)U9A#ylO#Pan zI{C<2!cynf&s-!E{`%m*qF{^=?ggz1oMfejmzXae1i}@267cw;w?&%hJlRqEBy-=@jUBKwq=Y zPq(`+lVd|3IvW}S&h7fZewbey$%)hLkoEhXiKH@J{H>zpnM<Xe4I7f4K4Qf1;lpIQ^z<3cRu`2P`(LK#&p06OPB333J0^R{^^f)bPABP2 zGrruFcWFhac+Y~C#qD;juINzg?7DQ#o&~{Os|)V@Va;l1*9-CFNV+DT#!C7qp4KdJ zb_I{yFyXb`p&V!5J@59OAIf-qx05q_zW#fa_wOg(zd7$*U3^b*sLyc|x9LS}|2^++ z-`zU>iQP`m?YrAsjau#M)v5FIoj>2$CR4Qhp>@mh-K_`dx-I^S z$HyN#tLMfak6pbw{#ak@32PqSx$C%pe*60$sd*I>D<)KyRF0SY=-3};jUqp@JM@@N zb9>LRznh5xd|toVF}O&m61c**eie8`P!QTXfTwoTWf zb-Z=v#H7k~f4kj`$bPdH?0T$QzXk65d)8DOyY_)LA6>HL>^1Lh`e*rP zZT`F|_Ughe-LlTP_KW*BeY9cr$D!bjj|A`OH|^?zV=uZZ>yU!o>#r@IuusExA6HG8 zv2n<{b0=SP&gUi9H5@%4V0}y|u)iGak+oqNY$f&#a$qF|lJz@glL9G^HbO@q)_-( znIt$(CI}8{m#2@fltl-#+tgt9Gml$ax{m1DVsW?8RX%k4GGiVe2hPP44p5X)^f%c>2v+(xsk+c3+m zHOtBkx7> zuxN%m( z3^~lQZ%9e-SK0r~kCjX0&;;L*v!$~NEexwUYRFReS9#JiRsX2>NL&5%ninjx22#E{D^W5^YjG2}|i7;=?m47u7ehFoJALpEE+ zkZUbt$aR)66w(J{nc5px0|IKT)4>`v-HJ z&5%benju>(njw!_G(#S@Xofst(F}RgB8EI=8AG17j3Lih#*k+%W5{!sG30s681jN; z40+KqhP-4MLteIwA+K1*kgb+6UfYknb#G$oG~p zWS3C-Uo2zDua+_7H_I5Z+cJjyZW%-Vu#6#lEMv%@mNDcn z%NX*vWeoYpvTw-y!PT<=n>Uv`z@ZO3Ln8NTAL0bUs*ckl6bc30%Uj9+i=m?#H(;%M zNS4dqWO8@Oa#nKuxJ zO$db5FSV#V;0|hU7FE#REUF}%MU%*8Q5D%NswSI7HDt4>mTVSHCYwc5$Y#-0G8Rn( zV9|j9EIJ5)MbiOTbT9ym4gp|M41h&509Z5=fJL(aSTq}eMRNdHR0qJKxd1Gh2f(8F z04!Pnz@kF|SacWwixvW~Xb}L576W{XN&~@3B1q&eiJ>yHXsIf-BoJ1=)S_hpw_e^u z@cN<#+M7ko$!5_CvRQNl*(_Q~Hj9oVn?8DS#%5;i;e|g(P{t|tpQ-s zaR4kj9)LwB0I=vp02ZADz@n1@ShN;^Me6`qbP52A)&sEUQ~(xj0ASH+04zEkfJGYt zSab#ei_QdK(OCd2Ive0yba)_mz6cU2kdbz%-YjbH##w=|`lS|K5OD8{nnf4V-YmL^ zY!+QiHj6fq&7w=lX3?c&v*DRMK=Sm=oSDL-3q{>+W=T}I{=IB0ASIb04%x-fJJu$u;?BD z7TpWLqWb{8Mdt;A?~5Rjc6#gge6whTT6BLPtbVCQ4+q@8JDWw1(B3S1lx!AlA)7^y zkGlJ04#bHfJLtXuxJ|qi(Us{(Hj6PdJ}*}Zvn9AZ2%U%1Hhtp0a)}N0E@N*u;_h& zZ_$H+U~l=Ol8An=B=nG3)LYMJ9|Xecms<33z%7(Nc=yg|pU~bc`jl)IeMUBmJ|~++ zUy#kBon*7PHV9_4{EZPIWqCWvx^cMh&{sv&tKL9LplH#L$e~cCYU{Mml zw`fNoxIhGnTqSREhCVWjZq~jim=spO)S_^byS|56ltO#6D3xp$H6xov&BI%T3ZU8Lm4#1)w04z!eU{Oy17WD#PQEvbi^#Nc}UjThkKL8f(1Mn?!lY+O3Adx%u zhGKG(Khp2y4cL;x>X%wHD9PR0(=5uMy;+n=HjA>zW>GfTEXpC9MY&|NXfW9<8bUUU zhLX*qVPq^C4#1)j04y2_z@q&CShPO?i$(#kXfyze4gg@$7yuTH1z=Gg0E_YgSX2PO zqCx-`6#=lQ7=T6N09Z60fJG$$ESdnoqKN=3Dh2o!4NMCDB7#Kb>rKaf&7u}M(l1L2 zt6yr-q$IavAG4^6_GVEv*(|Cdn?8vzqG@Ea=s>brbPySfrUS6( zU;q{!0>Gje0E=b-uxKU#i)I0^Xf^HW;2 zBWQ0Htt6X8N0QB=Rb;d1D6&~}G}$aVhHMrcOE!yElg*+vWGp%kfJMgxu;>H;7M%#d zqLTnvbTR;o)&j6-9RQ0?0btR302ZAJz@iNREIJKXd?iN&H!N1nE)(03xGvu z1F+~E02ZAKz@qa2zC{g5!Q(`b$SOUFEjNqwv-Y9$lfvqkT6A%edu4yKXcO(tqD#nT z(WPXw=rXcdbUE29x`J#LT}d{Jt|FU7SCh@6Ysgr%8GuFC0h02W;jz@i%fSac%* zi*5p7(aiuXx&?qmw*s)}HUJjg4#1*209bS<0E_MdVA0(GEV>7PMfU=*=so}z-4DQ` z2LM>~Ai%fi!ld9cB1q(-fQWOES=2}SqKA^g>X%xyCCS}6&@6h4_GZ!JWV7fAvRU*b z*(`dBY!*FDHjADin?=u(&7$YXX3_IxEP4TeMK1!d=p_Iay$ryjR{&VF6@W#r0c z02XZnVA1OUEP4ZgMQ;MI=q&&iy$!&kcK}%QE&z+(17Oj102aLuz@iTTSo9$Pi*^8f ziylb|w%AuJx?M;5kD5iN>)-!;loVFK)S}Ol+{_HK=yTeeMPHE3qMc;3=u5I$^cC4G z`kHJOeM2^jz9pMQ-;vFt@5xxS3xGvG0I=vs02ciOz@nc4So8}3i+%-Q(Qg1O+6};> z-vLErLX5XkYZHS@eg7WCjb_824GPa02XxxU{N;!7Ig<; zQ4atXr30|2Cjg6j0kEhy0E_wnu&6Hpi~0euXdeI;^#@?l000&Z1o#%E1cMifAd#5< zxln4*AL+N!i==&nVf9Nb$_ly<zN zSTqiRMdJZjR06=F2>>jb2*9FJ02Y-2u&5k>MHK+wqKshhLlGoWrk6sQX3;L~izii`E0M=u`j}Z2(}=X#gxb9e_m}0a$bf0E^B9V9{9sEIJ#2Mdtvp=v)96 zod>|8^8r|N0RW3G1o##m5eyzCf<*KSxq7zlAi-KYGOD(!I=x&ftw|afiWwbYo zE+?BsSCGx3E6HZjRb;d1YO+~$4cRQ(Og4+IC7VUpk+JA{02bWtfMfU-)=zaheJpjO>2LV|0 z5CDrF24K-60NEp&-ll&ay;U|9W9i=GI&ugPbcJ&T^Cy;<}W*(`dR zY!*F3HjADmn?=u&&7$YYX3+~|v*<;#S@aSai(Up`(JKHf+6us;R{>b`8UTy70kG(G z02aLgz@j$+So9VEi{1uc(K`SvdKZ92?*XuAI{=H`2Vl_$04(|tfJHk1So9G9i#`Tm z(I)`kqQ`>4-$aneQ+h%DxLH)MebJ}Eu==GI?F_on(Pq(?v^R^sBAZ2Dlg*-U$Y#;E zWV7fyvRU*!*(};cHj92Bn?*m8vFIlN7X1vsqF(@5^eX_1egk09ZU7ej4#1*609dpK zfJJ`-u;?!U7X1ytqJIEbB!A!S58JUQ0KlRo02T!SSQG+akqf}0WB?Y00a%m*@Gbg0 z7#uBvM26|@>MzWqll1C3H569A)S?z4_mDAWQA^sJMXktYQEReU)P`&pwI!QH?Z{?P zd$L*7fov9aB%4KPWGspTu&5INi#h|as0#p#x&pAM8vu*C1F)zE0E^NASkx1MMZEx6 z)Ej_BeE?Y07l1|m09dpS0E_wquxJ1Piv|L)XkP#p4FX_M2Eezdc_?^-2ogC}`=Ut5 zAL(DHSJ#=Lu==GI<%Zm=^UR{bv^R@}kjIskx0V*pq*7Jx;004&M}U{L`8iwXf)R0P1HVgMG617Oj302Y-1uxJ7R zizWiFs1$%jWdJNH2VhYJ0E;RCSTqTMMO6UbqU=!cIT0jsg2YgcS@gN~Mb)9O`lS|4 z3AtYtm_<`*Zx&4>n?(nb&7y0b=P-5CYwbYwJ%y33aejg(a|9{yVxu`hW2LB zv1GGoHQ6j$LpF{=-S#%ZIEV`O( z7F|O&i#C(ZqHD=!(RF0A=z6kQbOYHex{-`UHvzEdW&jr50>GkM0a$b!0E=!1V9^}_ zEV>hbMRx(P=xzWO-2=d)djVK<9{`K)2Vl_y04#bCfJF}hu;^g`7Ci#MqDKK(v;}}g zj{$s(E(--O7C|Dv={q2on?*15u;_OH7X1OhqCEgC`V)Xfe*v)QZvYnk1HdB3 zwP8CJ1prtie`D$o?6D{az@iWUi(CK}B?GW148Wok02ZYJu&5aTi<$#`i@pp6_YpxN z^YxQNUztTYdPa-5Vf9NbYVEq?E6k!cv^R^|lFg!aWV5I}*(~ZnHj6rv&7w52SrjFk zMV-iIQD-t1bpc>eR{$1u17J~i02cKCU{N{%i+TdEs22c>dIPYi4*-k$0#eu0ANuj0E@B!SdqW#Hc(I~Q6G@5J{9Y8jV#*ndS zEC7r009cd{z@h>G78L@ps0e^X#Q-cC2f(8704yp2V9^8s7EJ_TQ7Hh6$^ckY4#1)c z02WmOuxJthi>d%vR1LtQ8UPm60(^@GyTLm}kVsvMh%>}2`dGtcH>`fCMF+a>>(yq_ zL9{oErjyO0gUM#mA!M^CMmCFPkjX02VC-V9_D~7A*!~(Gma_Ed^lF;Q%bE2Vl`M02Va>uxL2|i&g-z=m-E7 ztps4vkpL`O1@JAJ>IQ!oK_cJjrO-69=p^lnj&j55ms+&ibvsWsi`LNIEIN*C79CGE zi%uY$MJJNYqLavG(aB`9Xf4?+T1PgEP9bB_dH@!k3c#Wb04zEUfJLVRuxKLyi_QRG z(U|}&ItzeBX9KY48~_%b3&5iD09bTB0E;dFV9|vDEV>AQMHd6GXcGX7E&*WCr2s6t z4B%UIj2j#yf<&h3u+W=T}I{=IB0ASIb04%x-fJJu$u;?BD7TpWL zqWb_?bUy%#9spp`g8(dg2!KTo1F+~302Vz8z@jYxEP4!pMUMlp=m`K8JqhqFy3!4v zB!WaP(7TRTnMKdYbD^i)u==GIJ?FZc4>XIOr@dM90@*Bjk!%*dL^g|FCYwdCkjuun2f(8304#bRfJGkw zu;@bo7VQ9F(MJF*`WS#kp8&AvQveoy2Ed}v0a)|}0E>14u;@#GZ_zVu@C6Yh(o*}P zXU(EEdPe)o4Xa;j(RZ%o}7VQCG(VqY;`U`+Xe*>`S9{?6P$u=m*q5uGkk^oo~1Yl7J zfJH6;`>vsH&7yvK zb=@jCtbVCQ?ULQxm|4`G_GVEBvRTxTY!;=F&7vsTEb2ryi#n6dqAp~!s4Lkl>PE(* z?f@+60l=bk02cKGU{Nms7WD>TQ6B&n^#x#2KL8f(1HhvG04y2+z@mWwEZP@NOD;HQj10; zyDMj!MI&i%7VSqii}oj*MWe`O(P*++bO6~b8bdaV#*)pVJhEAoPsXAG02UPju&4-t zMa2Lt8VA6l@c=9;0btPt02WOIU{NUmi^>34R1UzR3IG;W01RzO8{836o5sC1F)zbfJMsySkwT(qU8WAS^>bKBLG;m5`aZV0YYMHd0E=wbjCZ31A?B>*hC6o5sS0kG(D02W;Vz@jSwzC~-2 zg9Aj6NUB~?A7>Vg^agCnVf9Nbx;ELJFyAb?j`n8J^<=Z?2C`XnBiSsviEI|#Og4*d zA)7_FlFg#q$Y#;)WGuP^fJJu#u;?xT7TpcNqI&>XbT0sl?gL=a{QxX_0Dwgg0I z02VzAz@kS0SoA0Wi?#r;=rI5mJr2O4CjeOVBmj$^0$|b804#b2;9GP}a&Udj`+Bz;ru+2pYLr53%I?4EI`S@aU^&7zmdX3;BTvuG>XEP9n}7QIF`i?)%?qSwi0 z(Hms5=uI*fy#>Icw*gr64gibZ1z^#804&-Lz@qm7So8q^i#`Nk(GCC>eFVUwj{#Wp z2>^>e1z^!<04(|(fJI*buxKX$i@pS4(N_R0`Wk>m-vE4zo=*_!*X3=Op zqkWqkR=?DuAClcS7n(&s(%vlkiEI}AOg4*tA)7_NlFg#u$Y#-QvRU*y*(~~lY!>Yy zW6_@gEcy$8MSlaZ=pO(UIbj>NV^IKrMM(fG3Iebw1i&H}fJMmwED8g#CJ)E7Ih+IcB0eE?Y0AAm&z09Z5-fJOTPuxJnfi!uOMlnKD1EC3c|1F$FufJM0g zEE){Jq9Fh*8VbOoVF2Hv_TgZj2ogD3NBSMY{z$)6JEq~`u==GI?H_h$9c~tlqPB{&7uObSyV_ii;BotR1CnPaR4kD55S@l02WOEV9`VX z7L@|9s0@HbnOQWG_GZy6vRO2nY!=NSn?-eG zvuG~aESg6)i{_Kfq6K8L=uk2i9R|Rng#avC1i+%j04!Ppz@nu9EIJ&3MfCtIS_Z(P z1^^Z<2Vl_(02Unqz@n7^EIJZ^MXLZ+E zG_qNAI@v7RNXDWw09bS;0E^B7VA0tCEIJ2(Mdt#r=sW-xoe#jG3jkPjApnam0$|a_ z04&-Bz@ke4Sac}>i!K9T(d7Uvx&nYjR|2r;DgYK;4Zxyn0KP>hgoEu?h(%XO44r5e z{i-*QHiyINms)f~*d4OcEV_~QX32BS#%58EV`9!7TrcRi*6^IMR$V*o6A z9Dqen0I=vu02Vz3z@n!CSo914i=G8w(Q^PSdLH0gbX_<&O$3Q-)z8LWZx-cgU-Uva ztbVCQuY}!ItIVRUv^R@hC7VUBk)CvFKd@ z7QF|+qU``IdLMvA9{{lELjV@-0ASHa04(|#fJL7Gu;^0&7JUZ5qR#H&JszXXx{ZflMrMStf&7#hfJMUqSTr1fMI!)M zG!o!jl$H|QR|JV1qwj!3Q~Z(sKgkmIO9`uAYS95HZs~Dm(HPpBMPtckQ6AYW$|sve z1!S|RkZcwekFMRjDeXfD|-nnyN^=9A5$1!S}6P_kKc z7}+dZNH&WWk+Eno0E?CYuxKd&iw*~1Q9S^QmI1J+0f0rz0a&yGfJH|DuxKR!i;e_f z(JBBI9RIc1z^!?02ZwQV9{{^EIJ;5MJE7!i)N+-?-fBJ`Fbfd%Pjgu z`=S$5!s?e=v@XSc`y{jI6xy3b>&a%(sbsTg1KBJ(jcgX3PBx1+lFgzs$Y#-*WV7fj zG8UZ;z@l>iSadD`i_QaJ(fI%@x&VMh7Xq;8A^;X$48WpI04%x$fJK)Au;?-X7F`a& zqALJcbR__bt^#1u)c`EI27pDI0a$b`0E?~z_!ga<68uX9iQE?uan_ne2dh%or-aon zwdm#)xBEJ?=oZ?WMYod8qT9%3(d}fj=nk@3bSK#?x{GWU-Ay)&?jf5+_mZ*bJ^&Wo z55S@a09f=O0E-?1V9~<>EP4chMUMioXbS*~9s^*};{Ysr0)RzN0Q02VzBz@ldW zSoACai=G2u(enT-dI5k%F9NXWC4g_yjVZwb5hPMBF?5qzl%i*}ms7&(ms<2%iaTe$ zS+tGzX3^_pv*-=7S@b5^EP9J<7QIb2i{2rdMemZ$qW8#V(RMNxy$`^m4**#7ApnbZ z0I=vI02X}=z@kq8SoA3Xi#`Kj(dPgx`T~GOI{{eqB>;=Q0$|bC04(|jfJNT|u;@Dg z7JU!EqFn$i`T>ANKLUJel7 zVE`7T0I(<(fJMy!SkxSVMG*iNwE$pIO8^$N0$@>V02Z|YU{PBD7PSLlQF{OubpT*d zM*tS30ep*oNeR9pf<)$N_w%b+^taxEjHZUwFSV#^s=MoSv#1;G&7$sPv#1BzEJ`Pv zMLo%8Q7^Jt)SGM;^&y)@eaU7~KQb2W1HhvG04y2+z@mWwEZP@`;4FO=$PyiMU17Oi`02Yk^V9`hb7VQVXqWu9_Gz#Eb)HyZS zVWU`duwGDiN%cqiXKEOo8dks5qP$dh*qLTgKJCq-0d%vR1LtQ8UPm603jv=s*A#9R$Fl=>RM`7=T5G0I(H%1^41h%q04!P#z@ilZEII;!MJoYVbR++kMOOf@=t=+Ypiu==GI-InU6TwoU6 zPJ6TH4zgKvC)q5zi)D0ASIR04#b6fJILOu;>{87Cj5VqUQiu^gIBIUI1XxivTQo z34lc}1F+~702XZp_!ixg8q5$uB1`q&^{r;nFFHnhH8re$sYP$3y5$#{MQ_sHEP9J< z7QIb2i{2rdMemZ$qW8#V(RQ*~^gh`v`haW}eMrWl9RMu)2!KT&1F+~502X};z@pCp zSoApni@pG0(M|vseF?y#uK-x|H2{mg0btR$04(|rfJNT}uxJ+mi+%uL(T@Nu`U!wV zKLfDn7l3ckw$$J<5hSuy#d+N}RHjDly zn??VS%_66njoi(m0NE@`BAZ1)vRM=&W04EMqGSLTg#lQU0>GkF02Va^U{P}b7DWJ9 z)B=D-Edf~63V=ne0a(-qfJJQqSkw-HMePAt)B%7+9RXOB2Ed{y0E;>Su&6V@w`g~2 z@O}{_(oTnEzneuf^&+WDv#|Q57WHW6zI&-zlumoIs3+Mh>P0q-dXvqfK4i0~FWD^W zM>dQ0A)7`0$!5_2G8PR4V9~w+EE)vBq6`2QWdg7$3xGx004&M@U{Njriv|O*Xb1p{ zh61o?7yyfg1F&cW0E0a#Q6z@l0J7EK0V(G&m{O$A`lGyoPI2*9F)09Z5~ zfJFxbu;>r~7R3NqGz0K|5qBTZQPge!|7S88c1bp6ml8Um7a@gSmEMt#s7MG9nm`~4 z2#SJILbK4wGDZ5$*~CLhA@!w--c9m5Y%@jgvAijIpKOXgAe*8O$)@NdvMKtQY>GZ1o1(*H zQ}ij>6n#cU(dQH>`ho&QUs9mxD+&~SO@X3sC{Xk*1&WSPpy)da6dk2N(f1T6I!1w_ zA1F|CoB~BBC{Xkx1&V&6K+#DG6#YzrqF*Rb^eY95PEiDk-cIt)6CjZ+eOdO7DY{7? z-hN98sV`OZSCW6py{71ImN!NJkWG=3Y_Hr+kxMp331m~`kxfw|*%bL?Q&fR$ib7-* zg(*-}kpe|Y6evojKv9GOMJW_0N~J(i8U>2dDNq!pKv9eWMU^N}RG9)rRVYwYl>$W> z6ey}jfuiaZD5^n$qM8&aszrgK+7yAJKa#x70wnU0K8XEkif)w466+*~)R!u%pX~3s z-xM`qc~jJoY>FC@O;KaADQZGCMNP@3s2SN5H7A>*)5xZ%1sO#xDNvL}fud{*6y;E$ zD3=07tte2`ngT^_C{Wav0!8g8P}H6RMI9(m)R6*3ohVS$nF2*!C{Wau0!61&py&(= z6m_FOQFjUy^`Hn8WhQ&y3XsS#{cdc%2 z8bCHh1Iean5ZM$BCYz!&$);!s*%S>Wo1$T46b+|9(Fh6@jif-)C<+vfra;kI6et=) zfugf1P;?Fjiq54#(O3!;okxM9aTF-Zqd?Jk3KZp2plAXGiY8K^Xc7gA3Mf!CnF2*q zC;~;jlf7&K5;>&rI`%O|SIK3GQ90x-sV`NuI@!PRQB!ms%bTL>$)@NAvME|aHbpm*P0>wcQ?!nTulD+P)+P@rfd1&TINpy)OV6x~jNqRkX2+CqV%J19_eCk2Y`qCnAB z3KZQwN%o!=AdxM4Uv#Z0TB(m{ z4<(1xmnwQJ+5hlyQ}j5?o1!PkrszqsDSC=*ik>E$q8(&Y^bFY)?IfF`XUV2$7a2v* zQK0B~3KZ?8K+zrw6um%!q8BMp^b!S%_EMneWeOC%LV==JDNwYJ0!6P;plCk@ie9Hc z(E$n+9i%|f8x$ydlLAGDC{Xkk1&ZFL2oyb%?72^fqOl6+QB(A!-WR=-98zDZ=!0ax z{!^ytLzXv1ACXPb$7ECV3E31KCYz#9$)@NtvMKtUY>K`ho1!ntDEf*5MPE~(=o<KkTrYM_?q8tho-py+f86rDkVqHYu@>P~^89uz3*Nr9qX6e#LV5h!X9@!k|5k(zp6 z)G!jf(x0uNPb8$iRMCKle{z>88p!gdXb{;H4JMnSGs&iC2-y@3C7YsQWK%SpY>GyZ zP0>g)ibheOXfy?i&Z0ok7zz}fO@X3wC{T1R1&YQ}py)gb6pf=mQ62?~##5jup8`b_ zC{Q$!0!5Q3P*gyHqRA8}nnHo1sT3%hMuDQ~6oI0C5wH4lqR7{G9s8T2`Eps}`H_(N zQbmOkzte70G@Ip3(HycVDk7VrVzMbJA)BJPWK%ScY>F-*o1*z-Q?!7Lq6;ZdbP)xL z7E++-VhR*pLV==16ewCufuc((P;?muik48IXekAXmQkQ+IR%O?r$EsP3KU&IfubuZ zP;?aqidIsfXcYyDuBJfIH57rOnGr8ffJCO~6Y5!}Xn}@nBO&#rif)Mbi(fEBYgpbC z-AFb?H<3-zTCyp+nQV&IkxkJpWK*=BY>I9ro1zV56m6tH(IyHM-9~|;+bK}AnF2*y zC{T0<1&Z#ZK+#n^hX9GR)X!aCZ;EQhU$8|&>Pr!WDSDP{iguAr(Q{-|^gP)V?IxpW4+V-|pg_@!6exO$0!4c%Q1mhdie8~W(W?|F z+DCz+*C6un7-qC*rYdW!-@Z&RS?9SRh^OM#;IC;~-~ zN4)O@NMwZG{XAic>d0k@??*!FOBH<_@guL8qEA@f6dfj;qEE@D=rgh@`kZWvz95^T zFUh9pE3zs2nrw=`A*1M93KSioK+$&;C^|}kqVFkCbc_N;KTx3PI0cGMP@w2X3KacB zfufTXDEgTKMZZv>=vN99ouWX|Zxkr{odQLFP@w2f3KacCfug@D0!1H2yj%ei`BcBB z|B)%0r}stwL_+FI6?rNC@O`EzG38%h>HB0;RDo=YLS$1ECYz#)WK)zxHbu!~QxqYa zq7*WUQYlcBMuDPq3KT^tP!yv;Q6&l#Ri;2u6$%tpr9e>z1&XRspr|?pifT}xs3rx9 zYEhu5HU*06P@t$T1&T5$P*jfsMfE9A)PN#Tfuar+DC$UoqD~Yj>P&&6E)*#0N`a!&DNu9<1&X>+pr|_qih59>s3!%A zdQqULHwB9NP@t$U1&aDn1d1A`c+UusNHc}g#1v)e!(0E9kor6;4 zA)BJ1WK%SZY>I}HP0b^A3ul-Fja%$Q0?@M2WLfLh4Hu6{YwM-!w(VEN_ZR$fjs6*%Zwqo1zQI zrf5Fd6fGc|q6^8U=pwQyT1ZCG#S|#IgaSp2C{VPR0!5cnpy)CR6fL1Z(NYQ&Eu%ou zatah(PJyBo6ezla0!3F+py(=oYdmT2D4bw~|fK2C^yI zNH#^A$foEvGKy}eK+$Fj6m6kE(H#^hx|0G$cTu2dD+P+~ra;j)3KZQ#fuegUP;?&! ziteXC(E}7H+D?I@2PshW5Cw`Jra;jn6exO>0!5Eepy+XmK+&2M?-~ITIi&A8-e`)# zddKucN=SXFq8%yz_IFItGc0e4c9Koevt(1Wi)@OXBb%b<$);#G*%a*|o1z!Urszd7 zie92X(OwD^y-b0kS13^QDg}!6QK0BG3KZ?9K+)?IC^|raqJtDDdV>N*Z&IM>5Cw|f zqCnBx6exO!0!8mqpy)jc6unP@q7Nug^dUu{=&2O%Eddg7^flVkrl`Aq2jruakorH^a}-wex*RsDGC(*MuDQ=DNytW1&aQp zK+#_mDEgZMMgLHs$Vs&q<|uM00!5#scs1V_MZ5IA=&&iOq>pF`sUh{HiYlb~T|P8L zA(l5qVX`TzNH#@DWK)z(HboJ#DM}%mqExaeN+X-1bTW#f6ex;Opr{fBiYil}s0sy& zs#2gRg91g>C{R?L0!1|_P*jrwMYSkURGR`tbtq6&mjXqZ6ey}kfui~pC~81~qJ|VG zYD9se#uR~~#8fX|fJENV&t3be!7F`vK$912sUh{HicU-QFZHZuO;KyIDQZJDMQzC_YDa;h_7o`UK!Ku;6e#LMfuhb7DC$CiqOKGu zI-LSVXHcN18wHBGQ=q5^1&Vr7pr{uGih5I^s1F5-`cj~%9|el~Q=n)71&Rhz1d5ua zdUpws$SwL=$L1)~`=UXqA@!w-hNk*^51XQ4EN_a2lTFbGvMCx#HbtYzrf4+T6rDvj zMPtaO=xnknI){v+b16_XmI6iRQJ`oX1&Z=0P&A$bMfnscnm~b~i4-WBM1i6L3KUJI zK+zNm6iuZ-(KHGaO{YN7`4lLcL4l%~6eyZSfuceR6wRgx6rGvseJ?;F(~<b4+kL69#1!Pk+pKOX2kWJBrWK(nz*%U1#o1%-!rsxu~DOyBE z(P9b|T}pwX%P3H^gaSoNDNwYG0!7OyP;@y3idImd=n4uHT}gqWt0+*kk^)7mC{T1Y z1&XerK+&}nC|XT{qU$J7bUg)%ZlFNX8j3(sajMr^fJ6%PzNiF6`t16~)R6j8Me9=i zkzbmkTUg!{ttXqJTgj$q1KAX9B%7j5WK(n-*%aMQHbtAsrf3TpMR!o3=uQe0-9>?- ztrRG_n*v4KC{T0{1&Z#aK+$~^D7v2lMGsJ*XgdXp9;86gLlh`_m;yzQP@w2h3KTs? zfuhGLQ1k=^ik_rE(Nh$GqP3~s0s#`)rZ4VqHbsBwebLjYA@!w-o=x@FeQk<%vAijI zj%HkWo1z!VrsyTIDcVamMK6<4^a=%vUZp_MJ_;1QMuDRJ6exO~ z0!0TXP;`(2MQ>1`=uHX~9il+dTNEgIn*v4eP@w2t3KYFZfui>*Q1k%>iaw-3(MJ?0 z`j`SmpHKvfo=Nqd6(EsX`s{kADf&!5K6^Mdq`p+q7peZ?Z%xscEN_awBAcSG$)@NV zvMKtOY>JMMP0@E`Q*@MUioPeCqGMzf{Xl`D;}j@5L4l$lDNyti1&U5mpy+1`6#YVh zqF*UcbczB+zfqv*cM25!L4l$_DNytm1&aQrK+!)GD00&5Wjl&o3KS(!pva>@Q6fd4 z=(AMMKO%~rQ8=HQq6?IipB7SIs;FX`-}tC0N@96aluR~75wa;tA)BI9vMEX32ZFX~8S~ zo0L@Zw2=BzMOkV7jAN!Ko8?VW4%rmtl1))7vMFj!Hbrg7rl>916tyFpqV{A{)Panm zjua^BM1i8t6e#LKfugPyC_0@2MQ2c;s2c@}x>KO22L+0HQlO|81&Vr8pr{W8iuzKZ zs2>H2`ct5200oK$QlMxM1&Rh!py*7BKv9b{Z?yo4R8U1NO;LLdL()R(OBIbs^B+2H zibk@$DH=sKMWe~4=q$1+8bdZkXOm6QIb>6GF4+`~C7Yu2$S4{|fucML6pg1qQ9cEV zCQzVgA_a;jQJ|=R0!5Q4P&9=CMN=tIG>rm9(nKokJq3zxpg_?Y3KZQ)fufrzP_&jJ zP&6;itNoKG+Ny6fUSNve)^DoaoEB1Fs_51<|MZ_t(FT?`MH|VcXcO5K-9|P=x06lL zX0j>TLN-NrkWJB@WK(n(8AV$uP;@s1indXp=pG6b-AjR@`zTO!KLv^&pg_@f3KTs^ zfue^fQ1mbbiXNdr(W4Y7dW-@^k5i!N2?`WFNr9rLC{Xk?1&Vf1py(NjK+!E}-b4Ws zX`}Z=>rK()`WEEQw2=BzMbD@COMf**yII~8?ID|@7s#gQMY1V+iEN7Yl1Hbwi$D0+(Yq8V zdXEA{?^B@Y0}2#&J^{~ zw;(@H3#l(v^mUs5%5SFV8Iv$o1)`nQ*?ri zq8}+x^b-Y&PEw%gX9^VkLV==RDNuBZ0!6=3py+oB6#YSgqCY86^cMw+{-!|DKNKi( z((PqCid+g5B~YNqqd-w21&VwM6jh)=QHUZ?^ktg&g8+$?=!4i-rs!V1FAArJ)R!uX zr2FZAnxYhzH$|yrQKLqQItV}qG}WVW3KTV>Kv81~6g8nhQBw*O zHKRaLa|#rlMuDOh6oI0obg!)diBwcL$?3r>{g?IOtz~*heW{|{bbs{Url=Lmo1)fa zQ`ClRirSJ*Q9H6JYEL#r9muArBiR&nBAcSlWE6FwKv7o;6rE0iqBAH^)Qti~-6>Gi zg91f8DNxjl0!6(kP}GM4MSUqy)QLK`P0@K|Q#6ijit@;&XgnE3`4lLcK!Ku(6eyZRfuaHm6iuc;(G&_4O{GB5Gzt_= zr$Ev96eyZOfufldD4IoqqCyH3&89%n910W_QJ|=p0!1YhD4I)wqInd7qLJy|a{?st zsebEhlqt&4SNa#Eht!uUx+vZMEWs2lWO-9`G1(MdLN-N<$fjs9*%Vz$Hbs|_P0Cpy);l6x~FDqO}w#x|sq+>nKok3q_!4LAn?6MA5DKM&pI1XqVm> ztxpfBFIBWD-ES(t4kCVEbQ{Z?qT9))XfxRqZ6TYYJIJQ!PO>Swi)@Ovl1g(OlMpLw0U!y&j9#UVb z=!JBDR>%~+$nvJ>C9)~nOEyI>lTFbpWK;Ai*%a*~o1)jqrf5Ie6unMH(E$n+9i%|f z8x$ydlLAGDC{Xkk1&ZFLK+!uCD0-IyMek9d=zR(leL#Vt4=GUe5e14qra;jr6ev1O zfuc_-Q1lrEiaw`6(H9gb`jR40v^(9qUVucV=zY;1Q*@s`yZ$OYq`p+qk#zr&il*p0 zmN!L5$)@OgvMD-7Hbp;>P0?|(DLO$mML&{F(NAPkbdrpspD9rE3k8aPr9jas3KacD zfui3jQ1k}{ivFZP(O(oO`kMkp|4^XFiQ3C{6uA^AN}xcIM}eY53KaPiD5^k#q7Vg& z!W1Z~NP(gxia^mf>E3$+BvL3b@mo{0HvWPw8d6`XC@t#$o@|QJS>6;y$)+eqHbs@l zrl>O66jdRcqN-$5ltDH{)ySr(IvGVZC{R?B0!6hbP*j@&MRh1pRF?upnG`6hM}eaH z6ewyyfue>KC~8E3qQ(>`YC?gcrW7b@MuDQ{6ev240!1w-P}GtFMOhRm%BBbur9{2D z5mEGyzU!D84PNQruJ=Vb(UAI5MQx&fw^UQqmgP-RJF+QiPc}sz$fl?x*%Wmmo1)HS zQ`CiQin@|b(dlFqok4-3ZWJi$PJyBx6e#LRfudd%DC$jtqCONT>Pvy5eiSI`Pl2KV z6et=l(GqBAK_G=u_0Ln%-+i~>c&DNrTAQN5 z`s{jCG^D;%(b-XddAcb&hviMtxnxr`mTZd7Bb%aeWK)z!HbvvfrYN6miYAav(L^$e zCQ+cMfC5F6DNrBDLCIyOSQJ|=h0!6baP&9`EMMV@S zDyBeD2?dJgQlMxa1&S`9K+${(6fK|#6rC0I?hzo7FZI4?j45iSk7yT0L+VQvT@v;8 z#Z1v6mN!L<$)@O1vMIWZY>JkUP0>=aDOyH0Ma#*i=yI|tT0ut96%;7Ck^)6nQJ`og z1&UTtpy+A}6kS7sqH8How3-4%*HNJ8dI}WXK!Kt)6ezlp0!24bplB@xif*Pr(K-qg z-9mw)^%N+&l>$W@C;~+bquvPt5*ed+KNp*#M>TAWhSZlT+8p&`RZP(qmN!LrkWJB@ zWK(n(*%WOho1(kPrf3`46x~BMMfZ|T(S2kT-A{p{2PjaqodQJF4vog|y0 zpUI}^7qTh(m5icO6e#+Q0!6=5py&?@6#YqoqQ59m^fv{H{-HpT6SJ4?C~_%Klt6(Z zj{-%B6e#j3P*i~eMIj0lg(*-}kpe|Y6evojKv9GOMJW`4qVJ;KZUGV*q4z~cO;Hbh zL`#i@)R!uX#r!X7nxaZ9Z;C3DO;HuHDXK~~MHysMRE=zks*_Do4YDb!Nj62b$SA5! zfucGTD5^_=qD%@D)uTXBeF_vcpg>VW3KTV>Kv81~6g8nhQBw*OHKRaLa|#rlMuDOh z6ewy*fubx56lGJOD2DzJYrEN_ZBl1))3vMK6JHbq^?rl>2~6rD~sMQ4yrQ8%(F>P|*c4+<3Zq(D(G3KaFG zKv5qG6!oP*Q9lY4^`}75016Zhq(IRi3KR{dK+%~LC>lb6qM;Nh8b*Pl;S?wuL4l%? z6et=+fuhkAC_0NGP}DZ&4G|!b(-clSQ`BDXi^jx4>Pr=kjrp@PP0@KQZ;Hl|O;H}% z6pbgFqI|L`nm{&16UnA%64?|LkWJBKGK!{9plB)uil$MZXgURo&Zj`p3#O?c!KSeW{{LWBz0HP0?j6Z;F=aDOyH0Ma#*i=yI|t zT0u5NSCCE7m1I+N6&XbnP;@f|iq=t}=oShTt*1cItrRHQK!Ku-6e!w6fuh?e0!52r-Uk9C@|DEI z#ir;74Y$Wa>dQ%Y5)vC!Y~0v&q7TWpY@O&K1sDBA-lhykt5uZGCPh2RH{sHwV^bWb za&%Lg<5Y`&6?L3i(H4~*Co@`9)o~g|pQz?IO{0I;aGVy=UbP)3CwgUF$7vHiP|tBX zM5{J*oG#I^jUA_3^!BEX(<}N-bI0iy&1&g5gQ6wbjx#j+RIcNUj5=)`XH2wDJI5It zUD?5L#z)`i?gbY4HlSs2|hz;PBw z69zlZ(rCXSjXH&FQp5ttZ z&d+z8t*m3qo zkIi+QebF}ZCov90FTBuk4n=n@bewmi6&5+phtWZoI?mzfbxR!Qi|D({9Os*8ofVFA zG&<=@$2lI|w$gDjm47jl~*U2exV>hgq zbKu6_-ykQ!jb+{@XTgn4-YloVjoo{PoCi0if6cz38`D2W-qelh-;-|P#`F&Y=eRNb zi>__lnEpx54sJ~UreYU2rhgQ#n;X-=YSzn*>7S+Q=f?E!3Jr2&`iEhLx-tFB9wXhD z{%M9WZcKl-{#ZArzZ`wM8`IxzJ;{yfuP2`B#`O2g&TwP;3qohRG5rmXC2mZAMc;fk zroUrtp&Qd*lC{{4>2En&>c;jSmNVqW^!JRcbYuF9BCd5~`jh@QxH0`v?X_-9f7W)r z8`B?_+~mger`@)=G5v9+t!_+z-sE04rav&S-Hqudz8`U8`jOoy+?amma)%q!56$gz zWBRG5J#I`twzAia>E{mixiS65@c}oc-}yV_#`Ie^@47L4@BKqJrf;4ec4PYP*B5R~ z-@f?9jp^&pqi#%JKpb~t`V8=-8`FpIQ*KP}ga34$O0UX|CUHw}ldHVWlatw68aX*S zxqf&v*QpXq(zc6E*Vl{WtIE0Zu`RdtNI7ASzTQ2dW1%k6rt>D5t}HjpAEmE4Q0Hrx zdX02HN%y7v%MiSd+dkeo8OLO6ZU+l1bqyU;m&goG#>a9Kc01W6vvju37Jkr`cCqk_ zhOQQd%QoH9xkNVRo?+o{y%OClOx8W<9)xN=WSKE?-Ky)t1u{|4#C2-8Ln}l-e|^pG z3v0N;{K)04YqqK34)-I=@*gg);f|;f{dMW?#q*t-lVzDAS!Nx}9C`2YrMgUo=xrPB z{&IeNp;p!0#_@$Nzwgik3!R$R+Cr}d3;B@|S9d)pzMZ+_KFEtNvj4Gf&WklYiGxg#-H!~edWdRtM<>_FQf6DyZ+K6U&$78WSRID zyV(}MWZ|9OV{+W&P=0pB%6Bh}FTDQKl@sF&-|+f|*DrFa^e(q}-E zlK8^AkKeN+Sa{td+2i6nd-j%|mpHYi$|Ab6@!7xXzcrYB&3)f)SrET+hc~?OTyW)% zeK!0o#|b5F5;wIM2sr)cSM(~>{!kuy^q=oZ*dr7A&rk3wIBwK!lv*j-ORbqYDkJKq zXE;tmLnk@;bg3N2tLk{Eosv5zcTDbINp695Nmv$c>u6Ji*(zF`T@aarXd?o)}XOs@|cMXjm@g0(BJuSLn?e!?@c63^n zihtFT|D~2MxjVEkou~X)`Fy%Oyn9Z*uF?HN?ucCZl6mEyo0XMal%GAhcy@Mi(ZuYc zyyA%kd9#ZOOA02I6imvVShQevNud@K3ntAiDkv^@na(eBcg&t$G;QXzl49yre=39nlyLXtiqm!MFlNOkH!3wqWB>Rj>yoW z!s&9%i?c_}&M!K@&)ivgBjvhG89HNbao+Im?FP5~zc@|v@=FTzXvqU}aH89^pPMyN z9pp_an4CX%MoC`Dg4qSdSyPploU2LGW|c?~S|fV)&Xawd*t2lv%)(jHi9EDS)Aa_G zBTuRQI8CpO>-&}dw=dtV;7xJ;T3+=m-}RQrVh6}G7?KR%UIp`Bl^g6p4_>8E7* zNfn0whpC>tigmq;1AJd6Dm3tubxiZ)y{s=DvwXioD?d}B-_WmAOH#I9NmGTc|6{D8 zwd<#M@f$VpE80raf|WLkN7s+XEWe_xw4uzKp_AGFugM%;xJs~Wn%}VesxspnN|4nx zl{!K9Oh<2amfs*gkuF<^Uy@xqN6YvHh0GCU9c6O_>zKtHvHxw3naois%Wo3jiYHYS zow6N~9m@2oX8!vz&XiePxh#H+6};_>Ci@w(;)>Z>nSMrHJvrI&qG~-ETf|RRRlQtx zF&Mo_)_=RiE+^P(RJU3vTYb26t7BxVo&S@qzGmx)=sHSd9Xm_c@gMK`^T9f*%NiDB zRhX_vqOxDHMFnrif48oL5%PF3ym#NcJ~{my9dkS6^vjzNOtx!NI@z{o>14YOHfNg- zblq7vr%iBK@18bKuFO1bP+{ThTxW3iF?l`D9N8*ZcP|!cTe`jWRISUl+p2WCJuge{;wVldlgKWJ0-X_awcS3@&H@zRM>vBDcdzU?ZND&*9BiWWmlzR>2Bu= zU1wnLv-7(58XjLx&Zu1@k!w@E{$)vLM&Ya}neqSrhpybR9qD0!a3<$0z5!q<9lIge z^();<@Az7#>y0ITQI4)EPam4Q7Zm5V>d<>u{0UpHg7`3M_9S^+9x*q#sfusg>mH^1 zueap*in^C>BDWVvTH9r%YS_`-4yCKgErSUp9Oaftm1}I9Mo*~|xzh-)WEs0$aTjzs zTv#SCw-2YW3?OG#u0*gL6M72ccUZi68w~bnTm~<< zOkOGWGH~)hFITE~YGF}H>0>KO6m#5HDXr3H0dfY*ucjzJ$%`(5g*l)1rbI1^LAV%`#igoH%=K*NJk(3g)+* z*}An9B~$0loFL=m8HM>JE#>uZS2-<{w2(O`&z{$|W%2BmlXBZhlV3D(YFBwdJg-B` znOQUCCG}~Oif5lTd3I*YDVZ&Yw90HLFXOsSlpSa}d1gUzasHHomNN=wO(~h$HAkx8 zSx`$o>yp%2$+W^*EsN!~sEozZ$%9CKX$}sBJb!Td&-z!jxn;K$eGIWfptpkm?GZ7! zHI#eQj(d+k!L-{>*|SS|juGE<*^|t&r{)5qlhLy0qVlX3O2I8ccdyhm&tuD;VwQV`$cKd8DjD2%Wk2mHZTuPrx4_bC%`L9fHLUe{?D?hlw>(`fdm>r(JTkZJ z&KT>k3m76}h+;p#U)7?AD%JcP|E62^2NxwtO z!C8a5_dnCA5Dg8k=p}_?iIv?dZiZLQt?t%vYr3`EItlgNEPZ3{-@eLMiOz|C%3tj1 zyEo;&JbPo1%F{P*%6)nA#!YIutZyMkB`*%%Pn4;$w-j|Y&yn{I%YAu{d=sVIm*>a_ z0?K`P&cD9h?>X`zfpTA-lU6S2`gQANU!Ei1WhnRMIk9p{=da?(hYaG^I#aG%O!l`! zxjE8hy3fDm@^8xP<-BnfJn}UxaT-qg&z?q?K2g-i;^2vQ@N`n1HkMwdPc9wjbU7_a za#beiSVg~~9gO;RulD+L{y@kJWXQ3+w49r>3d(YE|x_j8%NnV(Z=aE z&aqKG<`7?Qsg2j#xYfoTvY)!0y*7R<+%zAt(UEWcX^z-fU#^ShEE{_XFU>=3oGjNt zbCHer2rtb~*myz?fabq#Y%j-3b1xe&t{UVkZQL#2*wV`n*jTYKX$XPZ{X&mGd8}E}7pz}Xv<4?_l?3@;i9a{!t9~&3RiPHI3 z+W10lkl(N|xlNF(**Hv2sLnsm#+&5EqIrvrA9V`y5gQxGiPy_>Y@BvRkmuR>K=&Z; zu<_@fK~CrujGg7ir_1-V@zQ=lzS_o@1_b$#jVXhJT*Jl@LxMcs#+!!)`A!=@84={8 zHZ~d^uh{gzRjfDf7iz7q9E6?@vKXOJjupemjrp6jh`pzdpz}*!bF-Air;8rL{rMwDIh9L7r^m#`QtI*Tye5 z1o=lBPrEJ19c-MlImnmT`1l<`-ecomcLh0VYcTfQ7K}q}yyD&<-)Q6O_Xqhy8>>7R zur2XK4zx3x6f>>`Dc)u z+L-@$kZ0L=mppUP`5&?I`-C9>Zewft2AW>p&Bg_xATPJ^*@{8lXQMAaC$96yY#f*x z#V=a#z$;?&c^*VeqiG_HvVj5f_#`vuXmb_wQOvrqwIex8zadu8nuw_>hfX+4zHv_2m;)y1lb?l>Ir+#>qBLx3Sp93v8^f&%b23#x}~+ ziFnSnv4f3WZ0u=cUmJ(nILgMcHjcM(ijC*n82{vhY)>Ax;@i2{MtRtY=c{a#hlzN; z(Z+Q)%H4Oozr)4{Y<$>8xx0*CzSG7RY<$^9xqFIVE_XxmQSM&i<7YPN$13%B=#TK| zC|u)XLmTx+HMGyRv7?P$ZR}-ZKO2YGIKoE#fQl|Z&c*^8r`cF+;{`TeV&i2tUSZ=Z z8*j4l78`H3@lG4{HzDcv9<=dk8=tlDMH}^_Ksukk{?JiByQt$QHhyknWqp1weKi~F z+StIx<~C;8*xts@Huko$zm59(MAxSuXVLLo8}n?OY~yqr=h!&c#zi(RvGGb9ueNcG zjW^r4*~YtUyx&IsM7wVPNgMT#`)Gd2##e28!^XF5)Q{Kde81ZGkBy!e^vO1+*;v)a z8aCFqv9XO=Hny^{lZ~g_SV5hJ^~3nV`elf3UtT7~$Jw@hc^Ts*q{(@*-pMLnFta3o zf{Z0a!8nyEd3&+M$P4&hh%+vo^=1@rdhha z9Wt%Us0aP(*}-)#iUia8zh0*QUb2z-cFKdz0O|N*zC%*zG+*J~t}}xmqh1gFIw1eb z@85^zu5Tr|jO+WUOv`DSEkpdPMAp}dAS2t-k=u%1yj|uSFJ*>I>$`QjzI6Gg+bqY! zNf&<;q~nYAMWrY|-%;7W6U-zd^V#Rk+U88oD$LHz%*<_{)2>5Ks}8L?$aGFlZn^*4 zwQG}^*|AOgwyk8o%*^pgi+T_06MX71Sg|Ybe6e0_R?LbgKe(+omFrT~X*V$a(f6mt zjxQS0?!f!g5{@tG@z9CIiw2cWJB!XJo$j`%?|~1ddB+#^eE7uT!hQ#u4s14{S^wt! z{`vLqf1CzGPA*PpFzB=VJ*N)jem?E&ger#`4s0}_QUAvA%eyt$b81KK=4rcsa&kUM z{QXe+GxY}68&JQ0{rIKteO+&0eMt@eW#0D_|2$N;U-~n32WAe)>|ZZ_*`BX6CDpU^ zjHG&!g0(y*Ybjgj17ADoRl9w1+cT}!74Du;qvplO4()9G`nKMGpPc*TuFlt-Tytpj zgvIwgb|TVe^ApK)e!S@5^e5UMdAQ%3cRu#iv)XkwzT-w#Ph z3^kG!d2h?9_gYlyF0*?{netyw<&iS&>vPizMRE%cCF)&Y;=t5OAql(Ge&|uT<+!1r z#d(61vQVg?vdj}ol|A%BZ_2f(5E?4eq0n+!eK_=yT!D(A-7G7 zb>-(aL!R7^rH0zqkvojg`?clf6FMw&MnezQlABcMk4*XCe@K4@y>jR$xreF}+8}dQ z4Xu<%w2aU*_2uC|bU?0U_0S4Aay3GQ($@@4m)m2l&|q1Aolqm$hq|GIa%pBLN7hy^ zv|hGSKa?adAsU1Z$(#*Ci)6Y{sB;7P8LrT;_2kD>Lc3*pZ>Wmw!^@$sWuIRO70Oef zS3^tX7P~LhPOk53p>t&G`@;w1XtZ#{SIKU*bi?1tTv={-xE%3pH~gjSS&kciQif~Y zaJn4v)pD8a%Jpvepd7m!-0(eexYoGgx^j$ebixa2_rmAN z7EZ_lvV}p3;bXGu!HMDave#!OhA(j(XGmgrxvXqxV)zl+rD2KT&t!YU6T^CcI3h8e zC)*n-fBjDu7?l{_Bv)*7V)zv~u4g5NTMMu;iQyt~d3Iv>K3Um0iQ#kQET5Yg9wVo1 zY+`tp9GC5h;r+4`mHqHExkgp|aGo5A`F{8=Io1pOaD6$Q7y98rQhw-%pOkfeMK>!t%J}ycr7r zBB%UNDEyJ^(p#bMMRFwG4u$tg`A#TYOODyQp>S2X((i@BPs{E;ksMAJ(N89azmUy7 zl^k9mTX;G-yiHcUDJ}e}n7l15e2?t>?P=kfvP+xO!uw^|k`}Hb>%1c^tbZc$&a|*T z^Qlv!dL6fp-FhRT-(_h;m)!zb7YV`E6NBrlg$=qgsaKoB^lwL z3|u!lUFmOga+2L3XL&NO-kehsj668M47or;@8?;M@zD$5q>M1MI* z#X9k)>|u#cjF&SqS10t9(L9|PC2LtMr?lezGV`T6F+|pLnNBQ|1F=LW+SivKqR@#% zIj_rfVz5wOt`n!pb+}w7ZkL0;I!`7l$i#IzF-Z3IdY#xM*X#zJ_(rbx8l6ayO)Quw z6GLUkF4T#^a-H&M-;gt)-^i@^t*kjwCpyTr@O7e<+(_i7 zy_|}}^nO?;z7R-Zow!@JRZ%CRaw3v+V!2Et>% zOVEkG$0o5oRc&{ z_BC;q>ur)O4}JQxmC1>IW50=|RI9DVk;f zI$4fLZYBHI*>bXG*}pE9lQhfzb+uekv+UpLmcyE5|IV-+(k%Pe&2k0JvVYwz`Ec@5fvZq=0ub1Tn$*pDodRvyC&hOD$_OFj+VUUvOH}v|;`A@xD;P{Q=zlbJv zqTHbUzM&>^V^JXk{r-X}E@Y4`YC;BEG$ChNG$BJQnvkIuO~^2dCS znP?dylPn{oz%oK6TSmwf%Ltij86ndwBV@W|gq&|V5Ypc}U(SDOf!tU50|FrxM zGC~$wM##mM5ps!TgevO1)4RLB~C zl|0bKh1_V1nvk0;nvk^?O~}m_O~^WnCgc{2CS<)u6LPCX6SBdg3E5~7A)72C7Rv~^!!kndw2Y9uEF)yAWrW;q86n#&Bjg^-2)WlXLhiGSkozqo!*rKea@j)c7|9LQ>^PkpEan<*1OS{0HRe zQC!H=wx|i&VbO#P9?EhFR&%LsYXGC~enM#x*1 z5%RWWguG)JA@5p7$a|I%^1kIj$P?Z{Isd7*%hOf=$w0_M@UXuA>Ud=$Pvp3`OY#zj#@^@ z_m&ZI%rZiLu#Ax7mJxEoGD3c|jF6u!BjluIg#2t7A-`Bg$gh?Wa>_D7ezS~_-z_8L z56cMo(=tN-vW$?wEhFR~%Yl%OypwYNQ+vtFAOGXHkhDQME$^2p9Vb1}Pjvk%@*ot| zS2MnAOV^bwPkSqn>qwTThv^iRwUAwmQdH7H_Ay2g(?WK#5=B%C*~`il z=~~EcR-s7KLiV#NMXDCEqZt$_TF9POqlieMuW+hUBx@miT7x1<3)$0}6cx3QJ*`C% z))@eW?ziA}? zVy7X60Es2~39i>kfTVTTmpGmqDDvbLw%^DNDKAyj%=OQeyPmkB<}7cDP9vM57GzV@ zl5C2y$fhWpY>INorYM(eidvCPQEM`a+EAdVEd`3&QJ|P3N~-V`Y6LxG~c6e#LPfujBtfubg^ zw^)FrT_)$4@;);f_yeS$=Hbuk8rf4|X6pbL8qLE}% zG>UABMw3m^S!7c*hK!=KDNu9{1&Yq4K+#wV6rD$bqHz=`%A-KhcnTEdQ=n)91&St8 zplA{WiV7%DG?@ZLQz%e0l>$Z6C{Q$=0!8OjplAjKie^%vXck4FXprl@C_vKAllSHP z!KP@G+z0uEZb*HpqGH$oTHbYxD=J}mQ#6-sisq3`(FJ5vG@opW7LZNRg=AB75!nPr=^b^Vs|ork!hn_1ozts|SFTgawpJ=ql9N;X9s$fjr`*%WOeo1)vurs#GuiZ)ZA zXbT03?w~-?ofIg#ivmSkDNuAb1&X#&py(b76x~aKqWdUNbUy`(9-u(cb_x_dNP(h< zC{Xk;1&SV_K+&TVD0++nMUPXU=n0BI(T%P*T!5s_)#pVwnWAm+*J5r+eW{{nT)$Yp zr4m=PljTj(vt(1Wi)@OXBb%b<$);#G*%a*|o1z!UrszeoDSC;FqP-L-dYJ-6uTY@q zRSFdCqd?JX6e!wHfuh$bP;`I-MF%NR^acfr-lRa$Aqo_|MS-HXDNytd1&ZFKK+$^? zD0-g)MITV0=tBw=eMAu`dfN5Y3Xrsm70wP*^qzcc%m3I7sV`OZnd?6(-^q$A`kduW z(HCS>^d;F8eML4!Uz1JIH)K=vE!h+uA)BJ_$foEh8Aabypy(I{ihiI#(QyhCouEL` zj}$2Si2_9@DNyt?1&V&5K+&%hC^|)fqTeV`^g9KL{-8k7pA;ziivmS|Q=sS{3KTgB zrLXdX*Jv&UiV`RSMTcGQV*!%(s8I4hHAN5V_ouvskor$W>6ey}jfuiaZ zD5^n$qM8&aszrgK+7u|NLxG~Y6e!B1Kv6vk6xF9dQ3DDTHKagMBMR<|8dIRC2}Pht zew}N>#-eDIeCykP&&6E)*#0N`a!&DNu9<1&X>+ zpr|_qih59>s3!%AdQqULHwB9NP@t$U1&aDnpr}6uiUv@iXdnfO22lixnkRVE1xQ*0 z`A(;QnkmvZr2WAOA@!w-h9&q{H8(}WS>6GycP0?9oQ#6Kbiq0mR zqI1Zm=v*?2#!{f@JPH(zqd-v}1&YQ~peUaLMH47cG?4;DlPFMBK!Kvk6eyZPfugAt zD4IrrqUjVUI-deXGbm6rlLAGvC{R>Lfuh+ID4IhNC>oOBZ5JSEkIP4b{Gq1k9({N# zN(iYhRWvWbKiI+)UBL3DXg=8#Eg+ks3(2PFBC;u3NH#?mlTFbjWK*<=Y>F0>QFJK< ziY}u-(Gm(2Eu}!wG71zer$Eu=6ewCjfubuYP;?~)imswS(Mk#wt)f8D)f6bYh5|*` zQlMxx1&XetK+*LSD7t|HMQbQfbR$Kes3gJrMS!GztM59_HAR=p$KU*$5<==r72T5H zXJnhA^(=3SZY7(d4P;Zak!*@KkxkKUWK(oI*%WOio1!gbQ*;LzMR!u5=q?HrZKXib z-4rO=MuDPxC{T1S1&Z#YK+*jaD0+YbMcXM*^dJR_9-=_e!xSibgaSp6QlRKD3KTs~ zfubiUQ1m1Pik_lC(bE)xqMH-EE&?R2vwSkcUuTM@>%-fQgpm4DMY|IG^Kwnmb1ZL) zo+q24-DFd=hir;oAe*8W$)@NfvMJh2HbpO!P0=f46unA;qJ0!7dW`}_`zcWLIt7Xj zP@w1_1&ZFFK+&5NC^|%eqPHke^fm>G-l0IzyA&vTj{-&SQ=sSr3KV@vfufHnQ1mec ziaw!0(P4@}(ar?#G69lyQa*<3KWmD<&`)=Knh;W7s_4rEe{*Y7^cBmSqOZxO=o_*r z`j%{pj*v~!cVts^lx&K=C!3;UWK;A58AZn_P;`O*DM}-oqI9w; zijqxHjBJW3kxfx$GK#8Dpr|SZiZUorRE+{f)hSR^g91f0DNt040!6hcP*jHkMRh4q zlu3c2dK4(CPl2Ka6ewy)fucqfC~8cBq9zn5YD$5kW)vuDP7x>ydtPcgQPfCZ+*kC1 zSNf3z38#4>^`(lkJwLmHDav7aQnKokJq3zxpg_?Y3KZQ)fufrzP_&i; zMK@CfiZ1ZH!vZAjQGG%^-xO_CMeDqf`cg$3Jl{RT6m4XAQ?!X}if$vDqT9))XfxRq zZ6TYYJIJQ!PO>Swi)@Ovl2LRw1&X#&py(b76x~aKqWdUNbUy`(9-u(cb_x_dNP(h< zC{Xk;1&SV_K+&TVD0++nMUPXU=m`oGJxPJ0rzlYLGzE%wP@w1;3KZ?62o$aNyv70~ z?OFY9?5(D#o_rV9f7T1BFIBYL^ZRx;MSED@6um$;MK6*~(Mx1gw3lp(UM8EOSIDO5 zRkA7CM>a*Tkx{gt0!6P=py&VviVjks=nV=Ky-9(hLlh`_ivmS&Q=sS_3KYFdfui>) zQ1m_piaww~(T5Z$`iKHWA5);{6ABa^ra;lB6e#+P0!5!w1d5*Xycq%{Enh!s{k$m} zD4$OAzwkopOBH?N`Kx-GqHkH=6dfU(qVLG2=qT9~eNQ$;$H=DW2eK(TPBuj+$foE= zGKzkpK+#DG6#YzrqF*Rb^eY95PEnxfHwqN}PJyC7C{Xk#1&aQnK+)e6DEfy2MNXo< zY)6qxfuaNo6nPXVN~A!MPl2Ke6etQ&peRfcDEi9t9ugpFGxhUDUz?)7`W=vpi6Ql+ zisYwJ-|TIQQd!;O66jdRcqN-$5ltD&OH3}3}r$A8+ z3KZ3(Kv69U6xF6cQ5^~t)uljDCIyP>QJ|W` zo1!*kQ`DAhirSG)QG2o}>OeL{9m%Gs6WJ7XCYz!zWE6F!K+)+GC^~}zMcpV+)SUuF zJt$DrlLAHmA942q9Yx*$eSel^vgw<^E?o_Z3Q7wd6(yuVBqSk)W?2J--b0llDvDym zf=E$R?7g6(f@1HA3W^H$Ucrv_{{3b?@6Cqm`rqe%&T~KK;T+H8`_9g0%WG$MW;d~b zfTBVIii!v*8c0CVAOebt2`D;|fTFSzn5lFiX)H%u=+JS&GhNmZGzmrRZ#CDO$!XMdvU}(YeehT24UG zc?1-lPe9QM0*Wpmpy)yZiY_9c=wbqjE+L?3B>_d35>Rv*0Y#S+P;>ML^LS0*clWP_&MKqV)t{(dmtYFB%}>{bqC*N>Q3U1bKDiko9F1UDw$Crc{cq zXMHK!$Sg%SFiX*m%u;j{vlQLTEJe34OVO>&Qgj=$6y45@qB{sEx|4vSy9g+{n}DKw z2q?OjfTH^dD7v43qD=%8JwQOwg9H>kL_pDI0*W3cpy&|-iXJ7PXbS;FTL~z7jDVuY z2`Jh|K+zKfU(trf!K^Z)C?{;-Tq{LG?I&iRY#g$_tfFTdySYQ9=sDJxqUV{V=mlme zdXZU*USgJ_mzkyL6=o@Vm05~jW0s=r%qV)DfTA}DD0-8Cq8$Vj?IfV+Edq+(CZK2+ z0Y&c+Q1mVVMeh+%w3~pUJp>fJPe9QJ1QdNpK+#786n#uU(I*5HeM&&lX9N^|PVf~y z-8eYR015wMerd>kMvA7To8gPbA?wR3`lhivuTqM>Wqm37j#-MnXO^NLn5AehvlQ)P zmZBe-rRXPSDf*dNihf~6(XRv){YF61?*tU>C!pvL0*d}5py)3GivA{`=pO=#{w1Ku z{95)pa|1UHpeR5&bCZNbApeTueq7VT^$pjRo5Kxp#Kv5dOSM*im;Ccfj zywx7A{#uHr+dchsH)MTTMOm)9wOWd@Szn5pFiTNWW+{p=OHq_rikdM?QFCS~YQZc; zEt#dL6*G!j6HwHKfTDv4C_0#cqC*HM$|0brEdfP`5>Rv)0Y&WyC_0>gq9X_>I+B2* z_5>7lAfV_d0*a0%pr|7OMV$yJ>P$e9`5$5X-ci(*;48{>gC83p;VbP2)55O5r~kD* zke%y>tS_smr|SksNKr4=m!jUxQq+f8iuy83(J{lgSQ858UClXLJn1G@Z0*ZzZP*h4lQ5gY6 z2LQuMezcr?rnSzlJsDAz3>B}FH( zz7(CzEJdded_{}h;3fkk zJluZndWjTeWSikyH)MTTMK`$a&Qqo6M%I_2o0z5OW@ah6g;|PjWtO7bn5F1;W+}RZ zS&HstmZH0uQFJ!}MfVU;bT0u#_YqKZKLJIX2q=1hfT9NpD0+y1qRj*pJxoB+BLoyZ zNcxdur1Py43FcTyC!zmFD93Rz!PQPU*%=2|I=u)Y*UnWd;1vlKOF zmZBESQq+=Jidr#CQEO%?YQro=2Qj1QU;>H`A)qLSfTFep6dg)H(P0D>wIiVDZ~}^s zAfV_-0*cxbP}G5dqN4~XI+}o@jsz5SBA}=<0YzO1DC$Z;Q7!>R-3Tb^PVg0FCk0fTDo}6b&MvsF;AF6A369Oh8cy0YyUyC@LkO zsEmN3asrBm5>Qk@Kv5+DMO6e8RTEG&jDVuy1Qd-R_=%Mx6`hjgcAq3gr?S2j#h9h&G-fHPVV0uN%u+OlS&GIoOHnPe6pdq+qVdcqnm|C& zL;{K?5l}RlfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P*g`i(QE>W<`7Ucmw=*q1Qg9D zplAUBMW+)`w2*+JMFbQrCisd@N(zoJK*Bri`)DUiQ49N#wIxX*>&q%SE6H6jMT*X5 zeJNVTEJf!qOVPQ^QnZ{|iq2z}qVt)hXa%zrUBE0w7c!&hA_9soCZOmN0*Y1=P;@B) zMVAp!bU6Vj)@XPe9St1QcCEK+y&QimoM~ z=sE(5t|$14mL>(SF+jrC+fVPGDMgFyhG}C`$ojI1ZccI^pC(1Ou)Y-C$}B~n9wne?3jsx22`GAufTG6K+$sqU(t<8 z!A}j4@F(_3>?SFC$^Kszo=*x{Usln}Nv=Cnie6!TDSDMzie6)uqV3F5^g6Q?y}>L+ zZ!$~K4rVFZ$t*>0F{9{h0*ZDKQ1lJ~Meh<&^d134y9p@TLqO5{1QdNhK+%T;6n#WM z(Z>W7eL_IdrvwyzMnKW$1QdNiK+%^36n#ZN(bohNeM3Oew*+6&i%G$w43O|{`##!B zQnV~+hVPO>)|XYZFUcKTCq+N9z7+k$EJZ&vOVKaPQuHgc6#d35MZYsk(SBwr`h!`D z{$xhcUj!8WO+e8<1Qh*CK#>#DZaazs1QazQpeRT{QDXv%Tmp)c2q+2>P?StSQ3?S? zsRR_I5m1y)Kv4z(MVSN?g$XFiBA_Un;4AteDLBIb2`@E&+S=VKMK{@BacmL_SzlIB zvygk~94Ttf`cl+_S&CXROHnIkDQe9uMQxa+=pbe(I+$6C4q=v}9A*@?C7|d~0*VeJ zpr{=IMTZkmbOZrKM-oufo`9kb1QZ=bK+(|z6m=w^s1pH2oe3!FLO@Yh0*Z18DC$N) zQFj80dJs_5lYpXL1Yc1k6nxMC3BO?9fQ^RyJ^h{b8Lf9HWPMph$A;Xu=Sk6VtS?3V zn5F1=W+^&>S&I5IOHm%P6b)dOqI_m4DqxnPLS_^d5l}RcfTBSJ6crOtbRq#og9#`q zA)sgo0Y#+*6qONBR8BzAPy&i72q>x~ps0#~qG|$)h7nLSoPeSc1Qd-VplB2UMJEw_ zMSVlTzYLIYce^b*MvA7`4`H7i3Rz!P(P<&~pwp$OhV`XrG_w?qVV0t?%u-a#EJfp( zrD!~}6ir~3qKV8>G>I8SlL;uALO{_}0*a;)P&A!@q8S7f%_N{`76CM1_4D&3BICJL%{(CNcd6vK3YtQ z=H{5;%uvYsvWm_LxnmYd(YdTIMa!9`=sadAI-gmJRxnG^1RqC1(T=q_d{x|>;w?qQaqdzq!^K4vMppIM4FF{9`K0*W3apy(k2 ziZ&Ba^e_QMj}TDwC;>%V2q@Z0K+$6a6g^Hr(KZ5#o*5&=y?K)ULc_8MS`#BmQe6j10=jR)4;h^ir%-!i(U$atS_tRwUGP6QYqTb`cm{d zvlP9-EJbfJOVJKyDcZ>_MQ<@n(c8>Yw2N7a-eE@3y95-yM?leT0*dw!Q1m_lMIR7Q z^dSL79}!UWF#$!N5K#0f0Y#q?Q1m$gMPCq5^d$jBUlCCBH33E65K#0j0Y%>tQ1m?k zML!UHMX!W{ku!~=SW^S%RVnId-cOm-KZBSo!PUy52YOHmtUDLRN*iVkL$qC=RaD2G{! z+A>Sgq0CZr7&D665m0nE0Yyg;P;?{#MePYF>OerzQ3MnnO+Zmc0*X2jP}G@#qAmm! zbtRxEmw=*f1Qc~Apr{7{MLh{9>P0|NZvu+?5Kz>Y;45mL9K6;53BP%mfzu+{-_t+I z{wC2e$sy~@Dmp&dePX#3oxu81)Sp?3@|dM)0J9Y3GfPncvlJCFOHmQC6b)pSqCw0k zDkh-lL;{Ki6Hrt_K+zBaib@G6DkGq%oPeUC1Qb;eP*h1kQ56A2)dUm`BcNzF0YxJS zC>lvX(I^6nP9mV_WCDs#A)x3~g0JYf6wN1~XaNC5rxQ@Lkbt5^1QabMplAsJMQ0FDw3L9NGYKd< zi-4lD3BID5C*9L(C}JOhD1Y1Qb0&K+&TF6m21(Xe$9lj}cJxH~~f52q=1jfTAY}D0+&3 zqNfQcdWL|aX9*~Jj)0=)2`GAjfT9-(D0+#2qL&FMdWGOCx;;6#*#HSYU_T^#hZJ?T zZ-=~^9J0QwqBoM=cUDT#o2)NIJD8Q1mGQMV}E+^f>`VUl36AB>_cW5m59s0Y%>s zQ1mSUMc)xn^gRJZKM+u~mw=*u1Qh*9@D*)O4*p|+gio@c-hW++_S=uF{gfQCzO16( zlHEftm!jWUUyAlKOVJ<9QuHUY6#d04MSn9((Lc;m^e?j%IVswKmZAVNiW(766eOUi zF#$y`0Yym!6om*VN+zHvg@B?|0*cZIC`u=wD1(5aOah9+1QcZvP?SwTQ4<1+ni5bH zA)qKqKv6RSikcIAMZY8m3k;C(pd16|S1DR%-wtV!60*LmqBbdR?J6lci1nrDU}h;g zgjtGmn5C#KvlJc5EJcSgOHn&!DLR~4ijH7L(UAlcwI`sc0|7-x5m0nA0Yx1NDC$H& zQD*{*x)4y*m4KpL0*bm3P}H4(q8&q${m*VbQBSqs`Uy3F$OVLDTDVoGAMU$DOXbQ6wO=Xs%Y0OeIomq-z zFr#QD0Y$S2D5@i%Xf^>wa|kG!OF+>)0*dAnP_%%6qSFZ|T1Y_AA_9sQ6Hv5-fTA-9 zC|XKD(U}Akokc*=*#s0VBcSLU0*cNh_=?7+1e>ijiniFlR9q`XJMA;t@|2MEWffhJ z;`UxIMHjNZ6kWtDMHe$m(Iw1Mw31nhE@hUY%b2C;a%L&If?0}IF{9{80*Y1>P;?am zMQaEsT1!CDIs%H;6Hs(D0Y%pkP_%)7qH75#x{iRN>j@~@NI=mI1Qgv!K+#PE6x~cf z(JcfN-AX{wZ3GnEPVg0-pAtOT010off4^vj6di2e)4wAnWPMph_oTRsuaTmASzn6o zW0s=(nWbnGvlKnREJY78OVLBjQnZ;_iXLW`qDPof^e6#ETL>uHN{(69S4pC7|dt0*XE-py&$%ioPVE z=qmz>z9yjP8v=^HC7|d#0*byTpy&qziuMvvw2y$I9|iGZS?2`Ku7;46AFCHSQQ z5`NJhuHGRS*xKv9T*qGSS!QV1wYC7>vcfTDB)iZTc&$|RsDOh8c<0Y%va z6g45Bs3`$O5dw;$1QazRpr|V8MfTGR>6m=n>s4D?Qxdaq-BcP}|0YyCsDC$W-Q7;0DdJ|C8hk&BK1QZ=Z zK+&-T6dgxEQ9lBTjwhh#1cI;Vpw!@O10-B(;T)Xm@9FQiL;uu}^<@x{plCD!MPmpk z8cXmM4M+_>Vt|Bu+9$DmDVlFT8B&`Xvc9aMiK*^;w@T3@)|aBm%u+OkS&F7IOVKoD zDVokKMKhSCXeP51&0?0KI%X8jCZK2z0Y!5OD4It=(R>1m77$Q$Isrus2`E}bK+$3X zik1*ibOr%MO9?1ClYpYL2q-$6fTCpt6rDpr(YXW^EhnJpJOYZ&C-{oSrv{zdjG_wr z4#)&4YG!{2WJPMo`m%~HPIcSfAw`$4z7(xwmZD3UrRXwdDY~3limqUmqE*aNbS1MC zt!9>@tC&%=hJd2A1Qe|!plCe-MOPD0bPWMT8we=6mVlz`2q?OqfTE2A6x~2T(TxNY z-9$jq%>)$PLO{{21QgvyK+)|46x~5U(VYYo-9_*fU6>jyGC;z8?B}j8lA<&0i=?|# zL)Mp7bbqQl{w^un#QIY70J9W5$Sg$c>;=FAfV_)0*YQDpy*`+ie4e0 z=v4xWUL&ArI{`(n6HxR90Yz^Td`0)B1}`)~!mI7h{e4oj(<<7L8nV8uqFt%(o%cx5 zJFG87?=nl#d(2X_n^}tXFiX+<%u@6LvlM;EEJYtNOVP*7DEfqeqE87Z`iy|0&j~2{ zf`Fng2`KuCfTFJnDEfwgqHhT(`i_92?+GaSfqeihd%X=w||oej%Xf zR|1NDBcSMag0JYU)ZiNiNcb81Yaee*(L(#lko~D4>&q(oJJtQ^J}LT#^`+=vW+`&g zwC65G0cI&`#4JTYW+`gSEJZG}6eTfBQHU8u$pjRo5Kxp#Kv5b2Md<_-We`x5NkCDU zfTAn{in0kPYC=F!Qv!-21QbOHC~8JPQF8){S`bjwl7OOC1QfL4E#}iO=0s%$+2`I`VplATWSCo?$Jkc+2(uKGGD}ezvlNvxOVLnf z6jcyVR7pTl6#+%n1QZP;plCP&MI#6(8c9IWC<2O3BB1DG0*X!{py*Triedy5okl=W z4FN@?2`CyvK+#wNifRcc8b?6Uc!IB}FfDk40TP~Q-;FJjq78?cVM1ES`m&0qq`A*L zEJagUUy7zNOVM;@DVo77MKhVDXcn^+)iF!aY-TB%!z@K}nNc*4fTH;X6fGd2=yU># z77|djh=8KS1QabHpy&(&ik1>kbS42sXAw|zHUUM;2q-#-fTD8=C|XWH(Rl@(>NYQ1iFGZI#OVJg~ zQnZR$imqgqqSee&bQQA{tznj;waikqju}Pk2`IXnfTC*%DB3_k(X|8=T}MFC^#l}c zB%tU90*Y=Vpy(z7if$&L=oSKsZY7}THUf%nC!pvK0*dY=py)0FitZ+$=pF)!?j`t& zE=db^H9*4Y_H)-OrRXC2y6C>Nko9F1J(%VWeN2iTVtpyv%q&F@GfUAU%u@6yvlMM% zmZGi9QuG+J6g|!?McbHB^aKG#PZCh{6ahs~6HxRF0Y%ReQ1l!DMb8sZ^a24zFA`An z5&=ao6HxRD0Y$G8Q1luBMcWA|dYyoxHwY+tlYpWf1QhKgpy(}vuV_;qD?*lw8KP77IIR?&ND?&@t)w43#%Xb-a#z0WK~A23VNhs;v+5wjG1%q&HpFiX*= z%u@6jGm1VZpy&$%ioPVE=qmz>z9yjP8v=^HC7|d#0*byTpy&qziuMvvw2y$I9| ziGZS?2`Ku7fTCXsDEf_nqTdN9+D|~y9|RQrN$?fDlNQ`!fP}}`!`1IfQP#m`_$w`B zeOX0Ly1VB|DGH=(PhN@|F-uX9S&AAnOOeYgMM=z36k?X5WM(N!VV0s)W)!6nP?SzU zQ3e4;nFJJt2`I`UpeUPwq9z0sH6@@ZLO@ZJfTCsu6g4NHs09HpR?D3+1rD&T~)HXe2eOX0^r@MzeBSlBBz7!qF zEJf{^rKkh56dlDZMMpDBQAcJe>clKXotdSm3p0wk5>S*&Kv6dWinpMatQ0*VR= zzM{j@gM$o^@I?E$>vrk>p8oOnt=XdVko9F1otW-Ud`^l6v%VCSFiX)8W+^IVmZCCd zDJo}{qM^)ERKYAomCRC9#f+kA0*ZzaP&Ax?q7eiXjU=FG6ahsi5m0n80Y#?}P;@E* zMKJ=3P9vbGhJd2c1Qd-SplB=sMYRMJjU%9FJOM=$2q>CJK+z&icTk>XdwYbiwG!MOhC~R0*cNcplB%pMQ0LFbQS?cXA@AgjDVtZ2q-$2fTHCD z6rD#v(fI@vtstQ20s@LIB%tUb0*Wpspy(2UuV`v|aEAdBe#U<8dYTjsvj>k>riZLA ztLTb!_m`KXXcg;A(Ur_nw3=Cpu40y=HOx}9mRX9{F-y^UW+}RwS&FVqBLPJ>5Kwd@0Yx_vP;@f^MYj-8bSnWxw-HcuI{`&^5Kwd{0Y!HaP;@r| zMfVU;bT0u#_YqKZKLJIX2)?4r(u1vDHi{mxpS!+Xiq5ic%|4JGvc9aMhtu6-UzMUq zSYL`BWtO5X%u=+KS&ANGmZHa*rDz+o6g|N#MNcwI(NoMQdYXWuX9y^ImVlz?2q=1< zfT9-&D0-2AqL&CLdYOQtR|qJ2m4Kqx2q@Z4K+)?26um(}(VGMm?I56NCjmuo5m59t z0Y$qAD0+wBD|#qBc$xtcPP2bwcC!?1Pc_54=^^XODtbTNJ#)JheZcxs^dYkpeZ(w9 zA2UnQC(KgxDYF!P#wDUkE7rm4Kq(2q^lUfTH~b6#YR!(Vqkq{Y600-vku>L+};t zP7mH>fP{zJxAFH#(fFoj_%}UdeOX1p4EH&6JUe?pSI2Ff(Qr@SWtO5OW+@6WOHnej z6s0grQ7W?(r7=rUIH`A)qLSfTFep6dg)H(P0E%Q6MAutpO4~*M8Kx zQHH;dcC`IJp|{HjSzlIB`wTZ@rxbNyeQk@5VwR$#nWd;BvlMk=mZHwgQq+Z6in=mO zQ7*F-bz??RcLIuf5Kz>UfTCUm6!j*cs1E@}eF-Q!hJd1D2`D;_fTDf`6dg}M(Fp_; z^(UYxkAR{91Qg{HP*gxbQ6T|EMFbQLB%o*z!B=!dMzEU!5?*L`?vIqBO;%BHM#%cI ziiTvkm2XQ?DeFs78M73XGfUA>W+|#*mZC~#DXLlyMnKVN1QgW}P&Ar=qA>&%jU}L{mVlyh1Qd-YplAXCMH2}q znnXa+WCDt&5KuIg;42!O5u9&;gwL>_yDpI;$G%9KmJzbPtfE;N?wWU`sE+leXg0GH z&0&_Jxy({Dk6DW5GfU9|W+^(IS&9}iOVJ``6fGv8XbAyDXAn@dlz^f$2`D;?fTFVr zC|X89(K!SZol8K`asrCZBcSMf0*Y1;P;>zSMHdoKbP)kX7ZXr)2?0eb2`IXhfTGI? zzM>f!!N&}c@KC$?nJGn`GR<&#M#%cIidJX1AG{|;SFyentznj;waikqj#-MvlMM$mZEE!rRX|l6kSh1(MAG_ZXlrOMgod%BB1DI0*Y=Spy*Ztif$vI=yn2% z?jWG(P6CSVBB1DQ0*dY-py*x#itZzz=zaoWII!B?~@BiMMiQS^k} z7F{VtpIJqlGeXvvRkS6;J^Xzs+RFM;^cb@gJ8AZ<#Q1mAmNvq8#s?j(Tn!&kUbe8 z>&q(oD8rrnp%i`0`cm`>vlM;GEJdF&OVQ`dQuGD06n)7oMPD&X(bvpU^bIqLz9pdO zI|7QnC!pvD0*dw$P_&PLq8|w;`iX#|p9v`Xg@B@82`KuFfTG_CDB4dz(H{g9{YgO4 zUj!8WO+e8<1Qh*CK#`NF9di@~2)?2ZGJ-1&kZ?Eq@x~9OXlq+DG|CKFUsh34rhD(l zQWRo+DN1IRq7-H+N@bR!G-fGEXO^N2W+}>KmZC7T6lF1^D4T$yCIl2UC7>umKv9%{ zqGkjXH7B5`1p!4Z2`FksKv8P~irNrRbPxeW2NO_q2mwVo1QfL;py*HniVh>7s2u@C zhZ9hA1i@F-I5YT`0TQmUA53#I^|@>Nk+mZ;L)Mp7babZs+ow|0k@cmh6SEX`W|pEZ z%u>{qS&DL*rKlUT6m@5oq8`jr)RP%Sy$C4kO+Zl}0*d+)P;?9dMaL3QbQ}Ri{Rk*J zo`9kg2q@}LKv5n6MFR*Z$|slsW(I5hfiU}w>k$|GX1Yc2y%wU_( zjG|}kTW3c}(FOMHkdn-h^<@>6XS)5qkfNciFGUs1QdG$-MODmFRLv|!!(If(jCKFIJg@B@|1QbmpplCV)MKcJ#qSDOZXagktlKpsNnG}t(?|{tA z3|U`R(VR^8?60I~F6&FtJZ34H&n!g?n5F1+W+__8EJcf$rD!p;6fI$vqBEFLw3L9N zGYKdz(Q*Qc&Lg1cd;*GA5Kwdh0Yw)QP;?OiMHdrLbO`}P zD+wsNlz^hk2q?OofTAl1C|X7E71d=1Z!ti^wf0GDwiNy0?XYErtS_r*ZKnIeH&V2Y z^`&S%vlLy;EJfEaOVI{qDY}+fimqdpqU)KZXd|-}-N1~Z8wn`7iGZS;2`IXSfTCLo zD7uY+qT2~5x`TkCI|(Sdi-4lL2`IXUfTDW|D7ue;qWcLb+C)In0|XR3NI=m;1Qcy1 zpy*)&iXI{Oimu8Ges6$;pR}L5UL!>Xjm+?9X2|-oiXP8&!{1BMHrAJ-Czz$^NoFZ} zidl-DW|pF7n5F1hW+{4(S&E)#mZBG!QS>4KMK2Lh^fCcOuMkl5Dgi~W5m2<9fTGt4 zD0+i{qBjXB+Cf0kP6CSFBB1DP0*ZDKQ1lJ~Meh<&^d134y9p@TLqO5{1QdNh@D**% z4E8WU!nfPcT|dS%TF?w1W`?XUtLW2Aw|cJ>ea8Ay^f|K>eZee6UouP4SIkoMHM10b z!z@MLGE32S%u@6{Gm3s7plB}vMf(US`jLR5p9m=WnSi2S2q^lMfTG_BDEgg%qWuIE z{Xsy{p9B>BML^Nt1Qh*4K+(Sh6q!Fuz0TaPjRPnO5Kz>JfTAD)MU4r*qK`9!ryC&Q zRrYh&pGeVt_9JU@40*ayp6g4BDs5t>eEeI%TNkCC60*YD_P}GKiqJs!1I+%c>LkK9!A)u%& z0Y!%rP;?jpMePVEI-G!_BM2xul7OQ21Qc~3_=-Z|;5Gv!e3L!Um>l-^^iQ{+m^~^S zvc9aM&SCeXpQWe^>q}8rW+}>LmZEOVQq-MUih3|hQBP(m>cuQYy_uz`4>OAT5>Rvu z0Y%3WP;?vtMg0gUI-Y={69_2kPe4%~0Yw7{D9R_GsDOZ?LIR442q+pzK+zxqii!y+ zI+1{)!2}eQ5KuIPfTB`@uc%`2?P{PB%o*#0Y#GuD4Ie*(NqG8rV&syoq(bl1Qg9AplB8WMRf#U z(a>!54%(MOVI+>m!i{|rD!3u6fI(wqQ%Tow1ioT z&R~|JrOZ-vCbJZs#f+k}2`E}dK+!n_6rD>z(Q*Qc&Lg1cd;*GA5Kwdh0Yw)QP;?Oi zMHdrLbO`}PD+wsNlz^hk2q?OofTAl1C|X58(Uk-gttO!8DuS&q&-I_%#6rxabo`ckxkS&FV@mZIyJrRaKQDcZ;^MK>@@(T&VfbQ7}_ z-OP-lTL>t+m4Kq#2q?OpfTBAHD7uq?qPqwvx|@Kadk84Hmw=-C2q?OrfTB$V6g@yd z(SrmOJw!m!W&(;HCZOmM0*W3bplAyLMOz8JqIKcmE(0Xo&5Z7PDcWP7-X05wtS_tR z$*{ZsZz+0;^`+=(W+{4xS&E)zmZImFrRaHPDSClfie6-vqL-MZ=w)UUy+T0Is{|Ci zMnKVa0*YQIpy&+(iryrkXa@mBI|(Ryi-4lH2`Jh{K+!t{6unD8(R&0G?IxgT4*^B* z6HxR40Yx7YQ1lT2MIRGghSSsRrE#JJ;AYOU_N*K zCF@JkSIkoMHM10b!z@MLGE32S%u@6{vlRWnEJb^nrDz{Bihd-Z=qCb-ekP#k7XpfY zC7|dx0*ZboplCk{ZS&Eu6OHqVbilWR?)QlNL%?T)KK|oPU0*YD@P}G`$qBaB+9YjFU!2}c? zLO@Xt0Yz;IC_0pYqQeL%YDYlP;RF;NK|s-w1QfL=pr``@MMn`(bTk1)9SOdo)U4ob z21xiY`%)+^%iq&qYu}pflohhRtfJg3_oc>C)Q$C}s5`S1^gfT95e6y+08R6sycApu221QZP< zplA>QMa2XZok&2@U;>It2q+ptKv5|HMP&pOl@m}jl;A7sk`>%*fP}Z&_tCma(Q^B4 zY(-Yc`m&0KWx3fQDH_iDQZ#~DibgU^(I{pqI*D0|PG**(Q<$abRAwoPF-y^D%qXfM zplCD!MPmpk8cRS?EdfR22q+p)K+yyOiY5|JG>L$s$pjQlA)sg~0Y%dYD4I?{(F_8L zW)e^|i-4j!0*Yo6P&9{tqPYZLQB_v3mjMzUW8Z+SmZI;Pm|17S z>r2sMW+__2EJbH9OVLthDLRu`iq2w|qO+N$Xc@BWII0Y#e$D0-NHqDKfQdX#{oEd&&8C7|dr0*W3dplBPxS9DEQ z@JRzCTxQ?K-ylV!>@S2okrlGOtfFVK+)py3=vmg6qUV^U=y_%-dVyJrUSyV{mzbsK zWo9XQg;|PTWtO7Xm{GKyfTGt4D0+i{qBjXB+Cf0kP6CSFBB1DP0*ZDKQ1lJ~Meh<& z^d134y9p@TLqO5{1QdNhK+%T;6n#WM(Z>W7eL_IdrvwyzM(`Cql@(0RG>Z1xLqtzY z(P#GE*w3><)|XZEb(Y&9ONzc>eJT2uS&F`6mZI;OrRWD{DcZ{{Mf;eg=tpKL`iWVJ zer86|F9a0*N{wS&I5FOHp5DDLRH(ijHNLqT`sQs2{Tw9nXxS69_2kPe4%~0Yw7{D9R_GsDOZ? zLIR442q+pzK+zxqii!y+I+1{)!2}eQ5KuIPfTB_YipmHmDkq?5C;>$k1Qb;gP*g?m z6?MxFzH5Mlm)M>A?o!m=KD||EhpaEFXk@ngXEP}p#rjfo60;PY%q&HxFiX*?%u*C% zmZH;`rKpBkibgX_(HLeFjU}L{mVlyh1Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x z6ip|fXa)gAGYKe~ML|joFqv#>~>Ux9} zjcsd&)3Za?msPYR+s$h!MQ5&~tsj z6Hs&&0Yz&FC|XNE(K-T())P>4H33D}5PU_8vV-FckZ^%L>bO{n`r2VbcF6j&iZ*7u z%Ues)4XiIkH!@4nP0UhsGqV)k!YoC%GE32I%u;kavlQLIEJb%Rqv$RIitZ+$=pF)! z?j@k;J_3sFC!lB(0YwiGQ1l=HMGp~Bw3&dShY2Wpgn*()2`Jh^K+#qLiXJ1N=y3vy zwh>VD1OY`)5>WIM!B=!$cJK}ZBwU+r;9M_7&ss%KXNRmWtLXV`_mzXB=mpl7q8FK^ z=p|+;dYM^@USXD^SDB^gHD)Q=&MZZ*GfUAM%qV)3fTA4)6zwFS=q&<@-X@@E7Xd}@ z5K#0k0Y&c-P_&zXqCEr@y-z^V2Lu#-NI=m?1QdNtK+z`z6n#oS(Psn{eNI5p7X%c2 zN$?dtn;rbo00|$~+Q4~Eik`B+)%aC*$ojI1zRPx-=19@^tS?1BFiX*1W+~doEJZ&u zOVLlvQuH&k6#c?1MZYpj(QnKs`kjEH{R9;KK|s-;1Qh*6K+)d>6#YX$(Z2)~IZd?N zj-mhoMU4n33KCG%n1CXefTAPMQsTvI+TE-!w4v9M?lfx1QZ=XK+%x|6tyRyr~?5- zM-fnTGyz2&2`K7BKv8D`in{kS&EKlmZB4wrKmr%6y-6aXaE64 z`2-Xd5KvS|Kv59^MFR;a8bm-*F#$y<5>PalfT9utiiQwSR7yZm839G*1QZP=ps0d? zqDlgast72mCZK2-0Y$?JzM`H@f=?SD;pgmIXT7B84sVC8Nyz%LicW6ges+Wuox=K3 zbSkqH#h9h&G-fHPVV0uN%u+OlS&GIoOHnPe6pdp>(Rc!iCJ<0Gk$|E}1QbmsplAvK zMNG@F2;IRq5VC7@^?0Y&o(C|W>3(dh&fEhM05 z5y4k9s!1^QNTcXt`@yu6r09A3TaAmGgsd;C=*%YW(H*4dEY_Ezvzeu68M73f!z@MT zGE32NW+^(4S&GhQmZBBRQgi_`iY_Fe=pq7&E+(Mp5(0`=5>Rw00Y#S)P;@x~MOP3| zw2FYDD+wrCO+e9A1Qe|yplB@tMe7JCT2DaH)dUn>LqO360*bCBpy)b+ujq^>!Eys6 ze1jR?rBd`&b2D7uBxHR#O`S&WVJYi62As%|=2f>7DK>wOwsB;#d6y(Pa*=r=Opn}c zUQ}g8UN@VwNF-|hCS;4qNd{$`$aUrelsS*?l>ipuX;L8d8A7p$Ek|U zImU5DL>@iPaZZi|PH>#lA_MarXKdu6e8-s(d9%=QrbJo}a-12F*olraJ91-*j^CH0!j&ot8c$DL;j9hZE<6IHhd8*@F6=_}LIO`)d zV;tw&$j!Bmb3^32@s4v#r28btxg)Y*isRf9d3>7VY>K!u9cOc7aGm39iCj9zakfR? zp657EM-DpOah{KiS>!k`M{Zr>INKvXEOne6k)CHe&aTM9a~x-Pz5UJB=;CY4 zJrIaKb*;Gz0@0L><~|5S%WgDxLLj>8W^*qDqVL^m?uJ0L?H%TR2t@7w&AweAYX5iS z?E_K!|C8<*h}!=laMwW8{vTa?1fuqT$=N3mwf|4W;{s9pKgH`Gh_2pd?vOy#{%@%U z1)}!4&mL8QsQq6vj0i;S-_}1l5Ve0C{j@;T{&nlIfvElS#1jHh z`}bw11fup2gw6;=?O%AD9f;aL(KkO3o&2G>dje7WN3xa%qV}&GEek~LpQ$-75Ve12 zWbl1)}zMZPy2)_Ln8E4Mgp4yWJ3o+Fw_?B@ng0Z*oT< zYJXwioO;OU2fs6G1iX&`D3Uwj#e+WpUO15vvJu{RL4uK<4z zMD0`f?}4b@2LBasQcJSU1M3F=A=hkD)ZCff)0&3NoofD#HIKEx`oB8|oaS51u5O@b z<|Q^apP6ZfUK-}xp|^&s%|k8FC)0p3CtG69I?z|&*v3WHTI6=cX=D{53?+-1^L(8!j^0H0=r)8i#DSOA?Yxgf|85o+B zz4pPMe_GNqP~oPpo&MD5mVrt){e$bac5_-xFzcjt2{_NO&Rb8P`R(c6I+uL)_6>`@ zb>=+0?O3x;Qub{Z?7#U8r^UJUTA7vpV5QAJ+_GVzS;mFF>v@nkb@8^v5S8~&P zRBbXB#9W`ZHvaOdxn>nf*&8nUcZK=NT)1_Y+`VV9)51J3yp`7Qlh$m$`uqjng}Z(G zJF~r&w(Q;WgSl#Er4RP)x!!4E-|c?wH*>AbkNErDU2Dy@ru7c9nYI5VH3}xRe%olV z|0Ojx!^fuD|B`~iBqxv^I6SjyS}?P9W_9!IKvr|dY1Gb1OFP~q#|bubf|z`p- z(?D8U{fg-sPB57tmzI{1mY&wfoJ~ga2B*q2r%Jd`VU0S=ES;qp?PbZn4>fd7ZfR^@$H1CmciR=|` zasF8WbIay7wcl;I;;ewvsKuoN%%i6j-!S)3XXk{L$F-c6>7A{)Am$!!WBxM_IP=eZ zfJOi8<{7;ewPWYZs;x`-o;|%eb>A*CW=)(rarVTywN94_)2G&U zshLtczf0#S)5p|I=~6eLW>#&NS+&z@>uTz{)OL&2&7L!M;`A=Fr%#_UWT__s*; ztm%`?ZC=-C+)d`n{(pGx|8Ee?t(jeG?+eEf zqn=&Ibsl4t#m3f-tC=%pc5L>78MSqtCs@2j!q|z^W}Cs_H2z{^rca$ZeOjz$#zfPM z>&pDXn7LKP*s?d-yIZ#>Qo^spzc&IvZ3{eN)!95<_*xdIv9PdFuK#-jO+2AfB6 zQDu3ou%aSXTskbTq_`lKS23`9NMUJ}!#9Q$R#xT>ER0o^mBmWRN(VX>g#%-`dHI9l zr^v6WtTyZCmklW|DXcQ5tS&9q>5B3P#YWekFt4H@R$5kNPFz`7QB_zF|IUf!=1i+g zE33=P%j`E|<;5ckOJYT36+`l>{GVvfs^Q58l$7NUjuqrp<;6;?hYTpJu-Buk!asHQ zK8ZiLv@BLxJ)knbqS&6SsI0oQz&ly*K7+hv-v$@6qOh{O%v?hMoO+nka9h~RURaS= znQ+Ou-G)>Sj18zRDl+F^Sv;yRzRG`Gv*IE4*7QzeZ^;2&6EA3SX{?$b+*cPax2VBM z@+(G`SCyHoTv8G%FDovsD%4f(rqkz{rFmp@?-rZwU4w!Ks}CqK4~vQ-?`|k8%`;?S!ub7*kux4?^ z(AWTDtf08k|6$yg{#n{H^X|4-Npb1m_^md)xTrXmSMFWP{Ib&0!hEa6lULNk-eBIB z1tL*dou6-%#@B}I(CWhK!dQ{HrQ+Wz&#Ne|8W|rg>LGchBX!r+pM`g~RhCtHm!QC? zj$eSD-p}V+=yXN7=J64$EGsICH8^o@-v+17&nt~pRpgac4k@nk&bgv6uVAEiWd<|= zTTz*3&d9r~%?&Kr{LHe-{8(jGnYm314M*LF{%zCXOcEYX&i~ElX`bf&?K783F7ryf z>l7<1FD#AU%sfa2R1^;!R8?y3t5{`WRh8XJuzFE`$zbn>=-$JBO!oAyi+8oUlDvnh zm&}7h3i{}qx#o_EpIdQpMNwX?Fh4(*JD^w_ko*P@a&MzmP@Fd~R#shAUR@O%R#sAF z9+~m8;BjU*S9Zf@H;M_5`+~w@#pW4iKy{^m|CvW!;+D>TklKfdx%=#9!`>bVt5=LL z8;e-ku)>O>lCt3k{?Lljf$VLHVNJ{v&xg*R?5-S{$Usza>aFKO`m~D4ep4s*cE*u#v$}6_p5AH*q!annw zi&j=$VZJbr-lCG?{QBn;&%fPF#&5dZZt+cr*@*ZLZS%+;J7?Ghh2~!J&ZAHKUd~VWf#v2ts;tO2j`H%Wiii2nX1x-gM0rq} zr~QGY-c!Cup}RSW{UWcy(?;Spr+!Wg!e+v%ai$d=XubVi2TJ6{zvv)8n{^P9Y zvLbVK21)(KzkU;tpI;UmWHwFl6}WANloj}w-n^cOe>13ye4W16FD+hQl1Y(tg%&Q*%lxB0rhArVo4ko4S37NAahO$uhj~;4(6Ub06?+b)*Y~wNqjA09{1kk)w?a? z4};vE4bF(i3RfoKWkCZa|MjV>9!W_-nYY!9KU3%q^>2T(MbZ71o2zFe^V}c5>3Lvx zjTH>7iWLmF%M7g zrmBAk=jM7k29{RmzzP8hp+G*ow zPw3axB>w@`$x1QPxH;3t%$_)XTBka*w{4bnrj4zcT@#F#cB9JaX-&@?T-*n!QwSm4^Ga_DQ7vrIgvD z)#J_Xp?f#G`9jI=LVL-)6!yOG_bk2CHGV4pD>jx1uj#y3qGne}udmF5*FQINr4nwH zgca;dM6*fq5O^o8-$#t^-1gGB_`7xdRDTm)IHWvbUoGDrJxF{)u$Mb=S98#CbATd$ zu-Q8L*QmjR1nl-jNBs6CChkZ7Z}!-Vii^q`?oQV0DagzB4mnksLsaqekH1p*&qssV zyEZr4Wcy%FS7`&x*b&X+UL>}~ijOyb}0 zxY`$=Wu+zQ(^*c2Mdg9A9 z`vY7xb1TFzHLr3L(R+gPy_<^5U@zMNPt19h_BdMn5R7>Y#m_Xpo0T`fJE9iq?qf#WimU1W{;~lzu0?vDbF*{F5aokbAfZb7r*(3f^MOP8|#oXnng zrQI&pyR;|yuP;Zra~mADYw$8S{<4}KNq@hGTR}Hz!$&6fm3MoX*F27Sd1juH@@nh4 z_3TwR&3kL4pw?RyO`KLUrE-prYMC9dgqzGh2im=mSmp5ID)XI$Csg*-a_e{VbIr!v zsheP4D8=`A?S7ee8O(FE_l4aLv%%k8^1hYum@_Y(>u*GRVAnfFVqcV);{vgPdBy(W zK0`BpGHyS!OHf@>|N6r|B6tat_=+`tXr>#7X6zmuw>b7LoBX2u`uio<9@6F~>F9<3 zH0s^a{_%MGW#VCNZ};thO-ucY%7ViG;bo=0gGUzn`>pK5HQYQ{yzG7O`pvr>_87JI zg@5FINZyE8erc7SZxRnYdl&6LpFRD(Ev{$$Fq(Ik^+&LC%~7w!hf@8a8hd5^2SJ1F zQ+$Wqo@4xGO!OAt$<=M^9bEQ)EF1ayr#JsdvHhmqv-3`54{ma)z2{?d-y662=3(~V z-^cI|3)eqc{l}Ilmwkd$Gw3 zw`q9P6YbqvQSEQR>?WD64Y;{a8y*);*wrz|SG>E>JemI|DXxUs+?gjVy}Z}kFYF`r zZm=S2nAfaEcY%4elJGKyZ^qvw;_1}i|M0n)i|_42>2Z{BZ4&SN2JfoqYF3vHE-f4G z-wN#F*n{WxeEt0gZkGY(P_cQ7&3pU9`?lSG;hPCBBpMt!@h)Djo@DIajTh{pN$(5) z@TvWh{h8dvqmnvTdj!15JR}ki6gAw>;B}36rsl?tUoP))WuA+w@+#~LL1W*%==h%= zUkS%fb%}HR1E2P6{XHkHuQ~Lt*Dc;_3XZ;eKR;okE2#bpo%r!X^C;!jiXicJU9NxF z(>oh`l+pXbf04{jwj0`p&mr-LSK=eWza-`?yhmsJ_Q)^E8&aO|1nl#$Z@k&_t$zoq z{$+k{kN8Fm_PO>rqJPmEY$@`}&8zVdW+%7-;Dn3k-wyr*gX@EDi_^TSbCY_vU&Gh*^=Dz;!{qf9mzlk)%IZq<=8^Vl|Kp&d zJ)U^Ly9NF$P5yfB zh`&eTzxr$v@TrDn}JsW@L!25~~s(-LC7Go!u zGfvn(52_e!?kxYISZwb2`lD#W^UQuUo6-Z;w1;o(Q=)(S)E}?3M*`y~jUO_$du#(M z?EdiqH*bS|MC-|W9M~Nd&V-AWpO7tnTl$5kPzlq={dXN3e|LNUC-Ev&4_^Tg(2gAEJ?IA(V%zKV0&8z>AfxYhzyb;P{ z@%QfR?a8x8{dxHJ&hWB|!Fp*KfA-HcuNuvj=A>pr!&?vy_jroT8^!D_*pEgy1M~Bb z$!Tv7ujkF0no~G+bnV!&=B=?RK0N0gapyyE9scLz?@qe;c+|hD$qL6CU9`0Lj&dms{ipXF*SDf{hN4#p#4->!oQ$C&PWQ{4}~TC3z`pvna`Of z{4>ANV5Z&iQvX3nn}Uw{5NX1{pkqFZn(!~^*xyX3{}*)Z$13ap1s(I-3JL#$j`_WX zgn#DOClV(6^Rf<@n|imgy_WX&ZDKBe?}Ss>Qx_gER~|6)VK@I%8trB~?Z*Be9fC+W zaNh8_!|a_Ud@tAjxB~NEs`;~?W9`y>2K6kvG&ojjHophp&5vmLyq0fiX>a95=BBj1 z8kw8S-YRx!KB?|4TiT_$Y1`VRIZ=CcYs;RlmzMps9H3>nmepFC&lGy6H@{8cEoW+Z zhL+2;w3pkS?{!+sp#$Iq=rsqva=BnqMjK`VU(EqNVwj0k7MS z)7qbF|E8r~nqLXmX~U|TFa}o+^FTPTHdYY16n?+57n}RmR+^%t>y7r7HV0dWu=y*w5-u`f|k>@oU7$x zEthF|ftHtPxkk%twY*u&yR>{j%Pm?yrR9rSzOLmiEkDrmb1lEq@@Fmo)UuJ;JlfkQ zMawKLn`?QnmWONEQOoXH9;0QRmV>k`({h-Wr)W7=%gI{K(sF^8OSN3C<;7aA(sI3) z8@0Sm%X_ultmWfcKC9&`TJF&DJuN@h@+&R(YWbU%|7hu&rv-aErEA$#%T`*p)v~>o zU9{|_Wj`$ov>dEug_a|=JWb2-T29k)j+TqGJX^~ZT3)K_zUCXz%d|ylZ2QKaP|5nSNwERQMfcZ?d{eH5RVJ(|!d61UvwCtp1FD*~da*&oo zwH&487%iu0IY-MSS}xaerIu^7yk5)OwcMoTRxO{^@-;1YY59?sUu*f3mVasKnkOuK zeKWOeu4Rsv9klGG<+1;ZvipFJs_fe}o@8fdW|9zK=tT$}si7AE=_R2FQbjsS5u~Gt z^rA==5J6NFPyta?6bnjKK@m~FLKl^;6cJ*>^MA7M%j0|AZ>@8VYr&rTO7>(j`4KWH zsAE$d+vwO?$6h)P)NzE4<8_>-;~X8A==h9|FY35a$9Htxq2s4I9@O!ej;D3Jq+_Oz zvG%iJ?)6L5F}IE-bgW{3SG%Xz*RiAh-RyQR9mm*Zx2Nd1)IRKSdzFsw*kAB&f2iXT z`@xiX4~a>^djd19W_5Ua;5e_=A0b>)t+B zbS$?h*tK*Vz9iTW>-g5vVDHrN&t<`mEDw&2R|Lm)IzIADu$Sn#Z)LEL=$Ly|u#4%~ zeNC|M)p6yE!QP9xWBMaK#+2fL1rBVP&jBpu)080-&qylFpk>|WobH-cl+H-qCH zI?mo4?4>&Hw-5B)^B>bO@0MVf(6Pq{!5*aJ^V@>`s*Y!O1p8MVD}5O3+jJcLaj>W8 z`0k!yf2?E7-e70bvH8AWchqst{$MZD@k{%OXLox~=$QXduuJLK^Xp&_(Q);+!G2B0 z^Y&BG?))1%rX3GDaCmrXV3-(hw9=s6j?{qBq zbFj>6K_9NYHzp3NT_CU_< zKXj~aKjiIpBOS-vPkXyPOUG^YW8ZFnrelKr(}!;7(y_HY5Olknj*r_Yg$rr9Tu+|vi> zxLn82biC<~cDv*3=eyl8NyqFu=GU>Xj`rbDOkCLhfdhB6>vjLRqkY($bvzXp9Np)^ z;!^Afan)lgje2nC=stbzIC^Ao9LOd6*45E5mE8A=##HJ%YE(=m`|j3CE>`+~_{NZ| zXYTL5(ZD{Sp2J*LTpa?@0sXuFu^ET;CwO%sF;3=KZwT zn0fySTzu&Nc)pCPu`#Lc1pUYJjkEplmwVsP*etj1<+{$xooAOh$1cVUvFmfb`H!dB zhZ6sBeG~q5efDAgKi9X?E_04ujCshe?$R)QpWeQX;tQes?d+{o1S}&sVj3Y)rZ}{^R*}S@`$un_$mZmS?h~yIu*>%94Yxzqf2-~K>N4!e%W_9-yC*y_ijHH1ZTko*`&ox|*O`cr3 z-L?D$yn(M|ov|U~l~%hlFQ#p1X}@pVU@!Az?_HUN7yNzW=HKnEO%BJDur+yC=Kd<* z53o?XGnnu_R-Wtq5MGi8ca-Q56Rl&|Jm!a_SlRA zneoM9%KdTp{J@siPmb7W_fW&@$E!EFddhCyq&RzB>ewv|x4WD@rQPL}pCo->X5000!j&?cg`fnDqOIa@^rnp^7y*vGX{~pRJlkNADsqL-P&; zzZd!E9xp$*P?oA8gWYqk&-(pB*6-Cbc4V$jYjibNiCn!)416Z`&x7r*ZR=b)Bdt|h zdX<)^vu;gVMv{35o~uOfq=8TBx$IU|Z+Cfe!$BZnzwMd(V>+IU$&t5V zwt^|CS$}k5;wGOh-sDp1BQdoP6gfM(!LC)`_8rvkYRpS9X{qi{+)Js|kDguge(r2% zc644ca_w75-<)h16F>RnV==XN9Ei!W&5kR**vT)x_w}}gHx|G2**%};FL$wU=DM0U z#%=pN=h^|YC%)A4-ab?8sv2&dbve!thhuKb)%)5nJvSUm>azPlfsfbz;fL)#kG=ec zZ^q=XU#aO`V`^_d5RzOAzE$02>P?yL1f+-hw1%vpCSc1Px}9PU0^7QFVI zx@L4s@7Ah&%OA7uqi(jk+j4KMm{MlfYuEbwKK7QnBluG|WAdFDozgqC>YVi)?XG1u zw)@$$KV_-GbNx6d&*e$Y8t(sokau}flQ*tRo)mL=;}llRq{ja|rJ+4#-9Jy6e1C~A z8eZ*FwUPbljW6cjO4vG_8IxMiYD}@inenN&Ia_uqoEjXHbJTM0O>)+1zjL5_BQc;EmWdPdX-jHTYA^~^>fb?Jk`Cd(*NVjD*MmND)V12t3=kz zDv|ZFK0Q-Bqj-9WRwV-2_TFksl~sd|#Q%BlMCRm;!AohDyudyX&D(I$mTDvS@=JqIs8IT2QjV3w}60#{2E_ z_YS>VuEnrUU)Q!=XRp!8-fQi)2k%|~{T^^&v99($Fg#^d#wzz` z@;~1HbuCtY;4@i{E5%Fda{Mx|9zfl`$Wdl^rfwy%(^$+{p{ZV zF3ETz{fSmf?S8!2JL|qLKD+g7-Ru8-UGp;LrO$6Q|3BV)%*~jaKCjih;6AqZ9&=mG z&3Mq=(*Jtz5xjQ}-X~wkde0oZKNFvEr^x4xeHg>Z6bK~A$E^D=a#;cP~jjHf?tA0KE zm0NmCt=)C~O;ZazU26UEFIIm#VCR^t1%F?^_0ag!uczL#{as>>fAh;YyD@XC z#p+|&_}B)?_BE>d1!7{3*eA~a{a;*c!Z`b2J1#an+TQEO#ra$9!_c_6&?m+0gUUw5 z?Q)y^ZR~`&cz>onNb#;j?Q**Uy|Ys2k%G3uekhkagf83l$H)8bM8%dRsv9B&`o zy2sgeW_YwcAczldvgL;l*ay4`;p=ue6rO1>BOIP)mm}dX?E~k;u)Vj5NeXYU2i?ix zL8~nv<_k9}VUOR#h3s;H@MydH3Wj&tk+ZV=08rV%)6dM_5cj)5S$a=fGmc&LrwDm-6Ay-GJ?Bi-!Y%8ZTt zYUg#0i)!uA9;v>1u&c^u2XuA=){YWQ!jq>=B@9joB;78inz4V|TdCIPA zydT+b@u(l!ZP$6sj}){!^0*(lZqQEnk=AxwPWq8#yMf>Nk#%-2o$@37?Y8U>MZUJ@ z{2~4lMaOl zySZ;CMgFwA?wzE_Y`d~|lOk8`CA^mu>1S+LW{;$rqUW+lmfDSfK6@nDUfWgKBL(cu zu{wLCh+XHJ?2$k1SzgE<8DZ;@T#fVOzQ`pzeNw*2eRfAq&KFr>uh^7) zk=N`-G+YtsZ!fmdipW=XWsO%v4%*$?bVVf2uBF+ENOrqJny-l1r%z*AtcWzVd!qf$ zNKt#*9Xlg)?4Iv^J~G|@1oSx{$*`N-_k3i4ndo;u(%fE${^uh@?IsO4AE{-p!#(FC zrR`SVdp_|Id)n}v_OD@Huvcb;yKvpEccix(gowcYz+ccG4zu)DC< zURK0i*lcfzM0cTrU2~GVaLk@3*yU@~J zg!?|e#0B<;Fy37-VcLa@%fMb?vCzcGGHT=XBd{TTSg8ZrhEkrJdbv zyLGj-Q{1+jS4TUW+jjfvYA4&SYPat;?IgGD_SMr)blYxUeeHKVAkJ@_!zeT8?`;%ruGW?!~D@#agohl)1G$o|1ri8T9 zl#uqC5^{&8gmlo9kdB%Xa;K(*bkamfXKjRZ(MCvDZG?2wMo4#UgxsZ#kRI9yxmz0{ zJ+%?iOB*4*wGq-s8zFtQ5zlmByEID)<(z_ZG=qKM#wa6giO~)$P8_S z%+yB6ENz55qK%M8wGlE~8zGNrBV>*?Lgs2CWS%xc=4&Hlfp#EdnD@NB{d3N@k9qw2 z10j{|10R23$jNa+miW)xU%XjDp3tchvQ$$-p460(WttMQTvI}x(v*-DniBG~ri47B zDIw2lB4njDLY~t`$n)9=S*4AT)!GPIqm7Ukv=Q>6HbP#~M#x%igsjs>$a-yrysV9o z4cZ8KMH?ZnY9nN$HbP$0M#$^h2zf&rA)B-j@}_nmWRbVa-u^j%vJZ0n#etAp?1Liz zt&o%BguHA2b2Q$k*Bk`9>Qd-)bY|uy!EiZSS>^0PKVE@>m=vNl4lXd~pRHbQ>UM#wd7g#4;IBE^OOAERV1Y*|rbM6WIlA+lS>z>;ks!!}4Ty ze%tn8c{X-F+xB633OlcD_qZlIA&(1o3v&>1yI?mlC&7LSD(j(5ln`~nZe%V(P8aM} z<|gED!ER%mS*f&s}B@5jY@?F>ltUH1^jiwzXDwNEnmrD8*lms50WtUuh|^<*h3$N5rJo-IWc z*iuxHEk%{sQdF5OMQLm)s=}6{s%$B$#zs+f0*Y!7P*jtEqFMwL)h3{*4gp1V2`IXa zfTDT?6xAo7r~v^*w-Zp*kbt5_1QazUpr{D}MNJ7PYDPd&a{`K55Kz>TfTC7}Kv9`k zZ;1hk)^?v>Dl0{k>@zujdThw~a*Eo<`fnMmEJf`&Uy9nZrRWZ}6m?)rQAf5E-N}}s zPHZXa%$A}qY$@u>Mo~8cinPtXTKLU#S z6HqjOfTDW{D7u$`qJaby4I-duFabqF2q?ObfTE!U6b&N;idx5dM+`{xb^AP>-$si1 z+lM&*{jnkE%PATa>$}fqXDJ%Z`BF57Ek$G5QZ$Y&MGvs0=s~s=jb}^ILu@IUz?Pzi z*(jPwK+z-uiY60KG=+eosRR^FBcNzH0Yx(iD4Iz?(JTUr9wDIUQ38r)6HxRR0Y!5N zD4I(^(L4f*<`Yn~fPkWf1Qb0^K+z&XplC#_SIqu0i+<%ka2_c|X>Kfz4LM&<(UY-$ zV|zfJrDz%FOVM(+6g|b3q7`f@dYUao&#T{}fTGt3D0-cMqBjUA+C)In zn*<9E?O!@?>I&8#D<(Nr|A7y-+hrQOVJ0MFGX9~ zQnZaNMcdg@w1X{0JK0jSi!DVTvZd%FwiJELM$v8piuMpt^a%k)pAt~Cmw=+r2q@Y| zK+)#}6zwOV=nDdhz9gXN00Bh@2`D;5K+#tO6n#xV(KiGXeM>;mVFHSd5KwfKfTClB zK+$`#-Ub5_o#Wta;o~Cv0-1k2HspLcMW}F#SsEUCu6-|3`n$+ z`()vFQZ(CreaedqIbTjuD9+DaT8hG)FGUfy6eY5yD2Xja$!sag#+ITKwiIP&OHmHC z6y;>2C`v$4E&_^j6Ht_gfTFwv6y+nJC_e#31qdiANI+2`0*VR~P;?6cMMVfGDoQ|6 zDgi~s2q-E}Kv4+-ib@htREmJ2(gYNhAq0y2IIoTYiB_{Oh5HF{!6W@m_MHZP*|?DN z2K~!j__{Y$>Y7mZIuxDXPJiqMB?J)gqv%HUUL- z2q>ycK+$ak6xAc3s6GKj4G1W@oq(c-1QazQpr|ncMNJ4OYDz#+GXjd56HwHGfTETJ z6tyCtD4l?!3<8Q;69Pr$;=D-)B)Z4Gd&Ms=MQ__Dr2RH=A?M2}x+BhCSx$;NaK03E zWJ}SVY$@u*mZHvVDeA(OqONQy>c*C$?rbT#i;bcl1Qgv(Kv7Quih2=H)SG~!J_Ho? zC7`Gu0Y&`@C>lUO(LDqd-Ah2xKmv*e5l}RkfTAG;6x~Na(NF@4h7nM7KLJI<2`Cyt z2o$x8^FA~n(N*>>LVkNGD(U`u8yOdJzMP`5asFxhS-h-|i^g%j6g|L}q6gVhG@dO* z53!|a0$Yk6W=qjTwiHcbOVMODilz`yG?jp&X#^BaC!lBs0Yx(jD4In;(IW&DJxV~) zYyyfNBcNyw0Y!5OD4It=(R>1m77$Rhkbt7c2`E}bK+$3Xik1*i^aLSLG&;^ps%VPl zyU#j~k)n$39n;ddkn`mfJr(Cys4PV*IA4mMW=qjCY$!(LZHxM*E7oeMsWI z8XHSMQ5*q99sx!11Qhv%K+*Sc-Z29bon&9(@PCk^RQD;!1TW-#IYo({f3t=ZC2_tK zC9|a{8(WG}*iw|8Ek!xlQk0V|MNzgC8H zwiMN5OHnPh6xC)+Q5`ml>Jm_N8v#Z22q>ygKv4q%if$*Ms38GGjR+`eOh8c+0*aav zP}GcoqUHn?wIHCVB>_dP2q;P?peTcYqSgcywIQIWEdfRC2!W!Co;S#VM7z58MU|we zqGzMM7jnLwqB}i*c3mmz#Q9RxnJq4E{Rt=wj}cHbhk&BF1Qg99plCh;MGFWhT1Y_A;{+5fBA{q70Yys)D0+f`qNM~B zJxM^(GD4teoag;&K%#Zr2hQ+YCr_ zpZjX;(^9nDz6$Ga^+L{uP;{7p zq9X(p9VMXX7y(7c2`D;2K+#D8ioPSD=oA4(-xC5w+dXfJ0g1lszSVk%6xFluPV;~8 zLe7^{bk_5qZz4tKIA4m+v!&<)TZ%5SrRXQN6#dMWqDyQky3CfMD{Lvc%0|&I1QcB( zpy*cuimnq-bc2AROah92BcSMa0*d}1py*EmivA*?=q3S0e-ls?6R(HuD2gSZD2{+4 zkAR|h0*ZVBiV_GY3K38gCIpI3d)~(eBzoFCxIZIB+w5!kek4BRd^ttg3{o>GO5uDd z%FdRe9Be7d$(EuhTZ(eAr6@OBit@0fC@))z^085rpMatQ1QZn{pr{Z5MTH3{x`lwE zA_No_C7>vkfTCgq6cs0+s00B;B?%}hML;eoAeFBOa5KweG0Ywc7C~8DNQDXv%nh;Rblz^gU1QazV zpr{1_MJ)*^YDGX%Isru)1QfLduy;yVz3HgDpjOv!$pfTZ($IrKmSs ziu$lo)R%ywegqWtC!lBm0Y&!^P;@T=MFR;a8bmJU5Kwd<0YyUzC>lmU(ftGz z4JV*z1OY`O2`CyxK+$LdipCI7G?sv(afCoor+9Cf0g0}5A5eFeqIaF52jWA{ms2#s zey+8(6g|xOQZ$h*MU&W4G?^_$Q`k~8l`Tcn*itl|Ek!ffQZ$o|qFDqKJwiayqXZPq zCZOms0*dAkP&Ai-qIm=q%_pE}0Rcq|2`GA;fTBeN6fGv8XbAyDPY_VFlz^fq2`E}d zK+$pnik>2%XaylqG(O%tVL+n4+4LWhqTcRPkWa^loG+*7xp+UOofJLK`BJosEk&!@ zQnZFGMK7?W=tZ^^y~LKHwQMO`$Cje?Y!tmrK+y&Qie4e0=v4xWHWE`VMb4L^pV(6LGh2!-v8CuTTZ*o*rRXYKihf~B(KWUd{mMqs zbpncR5Kxp!K+$gm6#Y&>(H{g9{YgO4Uj!80B%tVT0*dU%vY)a$I6f9du>=&w5m02G z{tZq+Q9J=fJ^@7u1Qdk`C<+r$6d|A}k$|EkLZIkey!V;`iS~1!u0AhCXWb+HWIyD5 zIYl{q|I1ENl#}zND9VQl*fTHpQ6jdOg zs3HMHl?W)ROh8c@AyAa!dp8V7)cxCZes({2r2m`yM0OQFanG$K3j?!u%+mBHi{Y&P}GQkqQ(RiH6fs=DFH>z2q8&K|oOl0*X2kP;@5&MV$zN zqH4ZZ-+)99yYIWME=2>}CyzS&A?M2}>hAkJyGzksoG(Q^*iv*iTZ($JrKlHMih8r9 zs1I9;`m&{{A6tt0vr#mFfTDW{D7u$`qJaby4I-duFabqF2q?ObfTE!U6b&Pw=zao< zh7(XUf`Fot1Qd-TplCD!MPmpk8cRUYI0A|uAfV_$0*b~H0!3YYZ<+y#rn&FC?j}VK zxPQIsAwT4NIYpCve{~Njn#}o9G=(iiQ`u59jV(pf*-|uvEk!fgQZ$P#MUSwh=utL` zW)o2K7y(6d2q>CMK+!w`islngw19x3g#;8mPC(Hj0*V$BP_%@Aq9+I_T1r6ClLQnk zBcNzG0Yy&{P_%-8qNfQcdWL|aX9)BHDGFyr^u%+k~Hi}*)plBljMXwQ1^g01W zZxB$liGZRv2`GAtfTGO=6unJA(K`eby-PsRdju41A)x4e0*XE$plB-rMcW7{+D<^x z4g!jH5>T{@5GZ=y_pRy_XHIEKtR!t1QeYnpy&(%MP~^pI!6c;ee8Rk z3`lgZ`$XezDT6vZUyF*u512`GvqpvWVjD4u{K zpMatS0*XQe6om;WiV#qgNI+2%0Y%9K6lEizD1{Ixy6AgP8IWjur|2gsde41yojoDs zd^ttA68tR#q$oG%OHm%S6y;@0Q9ia5J&Ttdk z)n!Z3ZEPv3$Cje{Y$K;CIl2UC7`Go0Y%LTC~84KQA+}f zS`ko`PC!ux0Y$9|C~8AMQCk9v+7VFHo`9k|2q@}6Kv72mitZ$!s1pH2oe3!FLO@Yh zLZGN-f>*|XMEAMB#A->=dG{&EZV4gh%PG1$!EZTOih6Rs6!l_DQE#>s^x+}pOYCxhtxUZx2 zkfMd|Th=Bfgq$y@XljB#?>;G-#`#h-oh?N(*itl;Ek(1~QuGL0iXLT4(QLL9J;s)z zIcyZoC7@^?0Y&o(C|W>3(Lw@>9w(q^5dlSu2`E}ZK+zKf6fGs7=t%;KmJv|2oPeUI z2q;=XK+)3#6g@*g(X#{;tt6o6IRc8FCj^QnCwOldkZ7S224@O?qq%oXs}e%ams9j& zf`4$B6urdxQnZ#WMeEp7w4N#6m2J7SyebhHNFGx{S_svGT6GG0HQ?xh1FE~PqKI42T+Q*in z&)HJ6pDjgSu%+lrwiF#;OVL5L6dhtq(N}B~eN8~oHv|-YOF+?K0*a0hP;``lqGJRU z9VejZ1OY`S2`KuGfTB|b6n#%X(GLU^{YXI3X#$GQ5KwfMfTD8*6rCra=mG&n7YTu) zPZGS_4M=pV`#RdEQZ(JO@l!&``ErV`B>25YNzql#m!eP!Q%FmXf0&FQN$d;l)Y$+Ns5AjZWe6xLOF+@B1QeAcpr||nMHL7rsz^XlB?5{n6Ht^! zKv5L}imDP&RE>b5>I4+kAfTuwAyAY%87wiMmYmZFAiDQd))qQ-0~YQmPHrfex{#zs+d0*YD?P}GuuqE-YH zr4vw;K|oP!0*cxYP}G)yqILunwI`tH4g!ig5Kz>SfTBAIDC$H&QD*{*x)4y*m4Kpd z1Qc~Apy)0_pr}sB%lUvQD(c=B)s>lyY(J%sv?kAvVH~~c?2q+p!K+z}y zibfMqG=_kpu>=&2BcSL30*W3aplCb+MGp~BG=YGkhY2W}NI=mf0*WRR0!2MTUKaxr z{ltA8t(O#CO0_X16mq_tq8TCofeBJHlk=r$7F&uQVN21YY$=+}mZHblQZ$DxMRVCw zG>H+XcYlPs|hGtLkJX23wci)kmyABDWd68)YyIQ`h`%) z`ErWZh5QdDO3`}Gm!g;1QnZ0BMX#`>=vB59ZDdQ)Yiuccoh?Ogu%&1d8%1vtQ1li7 zMVkpIdYgcvcL*qYmw=-82q@Y@K+*dI6n#KI(N+SAwh>UYoq(bp1QhKgplBBXMIRDS z^br9?9}`ftn}DJ{1QdNj2o${(^1e49(XUes&RQut?ml1iX(;4;IYpm`{P-zSw4d{( z=nJ+KeaV)h18gZe$d;l*Y$^JREk$3mrRW>B6n)D^(P09Lju23Elz^gR1QZ=7py&hv zMJEX;`i_92Qv?)!Pe9QR1Qh*9K+$Oeip~&Fbe4dka|9HfC!pv80Yw)HDEf(jqMr#U zxwc1`ZaCz8IYkY^ z{#Uc4=yuMRqK0fKYQ&bJ#%w8S!j__@Y$oq(bY0*YD_ zP}GKiqP7GSwIiUYJpn~`5Kz>CfTE5B6x~TcQ6~b5IulUTg@B^21Qc~6pr|_mMRyTU z)PsPcy9p@jNeC3x3wwVUkm#N~2B*FhHFBd@IOKdeMg78l;n`BupYx??09%UgVN21y zY$+PZmZCvyDH_a{q9JT4x{obIL)j=AMnKX11QZP?plAdEMI#9)8bv_SXab7H5KuIh zfTD2(6g@yd(SrmOjVGY!Ap(jf5K#0m0YwuDD4Ik-(PRROrVvmxm4KpYgg{ZBu-C|d zMBgiDaQaHoDW_<9IOKdeMURC2zH_ALQO=j5*=#9#j4efT*itl?Ek*O#QZ%0}MGM$c zw2&=DkF!yk^dtdA%Lpi1PC(I91Qe|xpy+7=ik=~$=ve}a zRuWM3905ho6Hv5@fTGm|6s;kk=mi3bUL>ICB|@NRX4so$K%$F_7@S#BbkTi~v^E@a zzMP^BVgIFhQuGSvOVO)rDcZ=EqSx3`^g3IL-e617Cbks4$(EwG*iy8ajiR>+D0+v0 zqIU@>dXIpjEd&(3Pe9QJ1Qcy0plBNbMcWA|+Cf0kP6CQ{5m59Y0Yx7XQ1meYMY{tP;`ob zqVEYP`hkF=9|!U zt`Y)8`@>$Yg{Eku`@ZWhq$un@k^M_J`BL;7TZ(>XOVJ-}Df*Kw zMSroS=q6i={$@*2Ohk{{r6`t-qBsJIJOYa12`KUjC`urpC`3R}n1G@P0Y!-f6eST* zluSTTHUf%L2q?-Jb7(1tZ?G1|*u-{d4<;BEcj5X*q4wkA$2rr>IfH z-?mhW8gsrBHDOCpQ??W}V@pwUwiLBsOHoU<6t!YYQ94_SGT10;O+Zl_0*cxaP}Giq zqV@z7-9bQ62Lg&Z5>Rv}0Y#k%DC$f=Q5OP=x)M;-jew%=1QgvxKv53@itZ+$s3!qM zy$C4kO+Zl}LZImOi1(ubiQaJEcim8my4%zIzLAjg56MFZJVG>9!l zgV|Cvge^t)v88AzTZ)FUrRaXP6b)yiXaoU8BMB%PML^ML0*b~EP&Af+qHzQiJwQOw zg9H?fC!pvd0*WROQ1mbXMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gAGYNsB{t>Ud z0f~m(BmDtV^n?2wZB``Yd^tsrMf}z)q-YN3OVM1m6wPBx(R{WPEnrL0Lben=&X%G@ zY$;mImZBwW6g@#e(NY46o+O}X839Gh2`GAsfT9%y6g^Eq(K7@TJxf5*N&#6m2Jet?)$D^m7J}5;|_cz-0NXYqeihhsyMOI1CADk~mf3l_MFSZojWJ}TC zY$=LK)FXE(ie*bt99xP!wiLy)QREX)lt4gHh=8In0Ywo4iV_JZN+O^rnSi2f1QewZ zP?Vj3q8tPi;qWjrWG@LC(BiK?jk}XA}*eDuJK+zZiipCO9G>(9x2M8#7kbt7`1Qb0) zK+yyOiXJAQXd(eclL#o9OhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q=1lfTBkUfueg8 zy*%qo(TnaYAOodnzWW)F*@+?N%PE?d=+}H%iso~^6fIy&(L%NqJ!MfnLRDnLL{K>~^j5l~c^fTCLnfucVWy^01T z+PQ?m`BRG4yH6e!NeVe%PEqkBzwMh+RD$!Rs3cp8O0lJ=G+TyaKv69MifR*3REL0~ zx&##6MnF+L0*dMrP}G2cqT2~5YDhp)BLa#V69Pr4N!};}65W$(aEc`bkMt`!QcaRV z&X-fvBFSI8S&CY6z7(}$OHn#oiZa+z)S4|tZP-%OmMul?*izJ*QPhEeqK*U< z-AO=ECjyE(6HwHJfTFGh6m=t@s5=2gcM(w3gMgyD2`K7GKv6FOih2`J)Q5ngz62EY zBcP~10Yw7{D7uG$qI(H}qGn0nI|d}W$^Cz0n@dp%_X8mVlS0myQ*>XFfA}3K8p`=n zG>k1p_p_yFI9rNFu%&1uTZ%@prD!x;ipH>|Xe=8=;|M5vfPkV02`Cy*K+!`46ipzY z=wSkiCK6CIiGZTX1QbmnplB)qMbiiPaYfTBkTD0-BDqS*u#Jw`y$ z973RIaFX}80g1-C@4Fr%MPJ&}{JBXX=gTQtnB=E!k)p>rUy2s7rD!o*ik7gY=n1wI zEoDp5lWZwk#+IVxY$WIR0Y&== zDEgd$qWuIEeL+Ccmjo0YAfV_V0Y!%hDEf*JDB6_dJ!U|nVfR_bH>K#h`==kiP6|0+ zPSKGh|K)8`bd>X@=onjyj+R2^kn`mf#U%SzcSuoevL4Ax zQ5;)}Jhl|Yv!%#qOHl$_ib8BD3bUms!j_^$Hj0u6C`u-vC>sGqDFhT{C!ixL(Z2|bbqqH zYmXES=X@y|!Iq+tY$+PWmZH&YDH_9;qOoi#8poER2iQ{dAR9&F2`GAqfT9Tm6g^Bp z(L@4@CJ|6HnSi1x1QbmrplBKaMbil=nn6I(Oah8#5m5990Y#4zP&Au>qQ?j*nnOU* zTmp*b5l}Rr5GWd&?42_p(IM{pu7^p{bMBKz3z9?5ms7Mj*-zXnMN2qeik@Ig(NeY) zJ;|1$Wo#*0&X%I5*iy8DEk#eWrRW(pik>B)Xe9wf&k<1cJOM?k2q;=jK+zfkie4a~ z=tTmGULv4qEdfRA2q;=lK+($t6m1}&=oJErUL~MtBLPLP5m59x0Yz^RP_&5aGxT2TZ$e{ zv~f5&T z0*cNPP;`NSqKgC+{X{^~&jb`*BB1Cp0Yz5`D7s2O(JurPT_d3AR|1Nz6Hs)6fTBzS zihd)Y=yw8&{ve>}PXdbmBB1CdAy9NQ*?Z4`ME`Q%40240#^$o|cXG)2a*Dic{!#mU zcJ9V$F@Aiu|9qtHv!y73Ekz-=6ouJR6k$tIB3p`**iw|tmZEHI6r~VQl%0U090U~Q zB%mltKv6CNigFWBl!t(#yaW{GBcLch0YwD}C@M%mQ6U0~3KLLt3jsw%2q-E_Kv60I zMa2jxDo#LA2|}PKHk%iFz!bG|-)bF~EqIJp*ZrT+OJ)l>UrtfkY<}@WQgkcl>wQr< zwiK0TOHl>36jfwPQ6;t%Rc1?38e590u%)Of8%5O!D5_3CQ4Io$Y7$UXi-4lq1QgXF zpr|eZMYj=9RF8n7`UDg;AfV`W0*V?EP}GQkqQ(RiH6fs=DFH>z2qwtH}2Mv8ViMXj=hoG+)SO*Vhv*HYA$^QEXATZ-DVrRWZ}6m?)rQAf5E z-N}}sPHZXa%$A}qY!r1Rpr{)GMcoM~x{H9K9t0HKO+Zmk0*ZPOP}G}%qCNx^^(COF z9|1-E2`CysK+!z}6x~Ze(Le%<1`$v+n1G@o1QgvzK+#Y_peQ4oH`jnf54x{_w3eca z?t`RZ*+R~jQ#3N0|H`*gG>Y@3Xf#`j#;~PmEL)1kv8Ct%wiG?cmZI@&DSC)4MHAR4 zdYFKsi3Ai)BA{q80Yy^?D4I$@(KG^zrV~&!gMgx$1Qg98py&|-iXJ7PXf^>wj}cHb zhk&BF1Qg99plCh;MGFWhT1Y_AjTH3SsB zKtR!p1QfkQK+#$Piq;WOw4Q*XmkB7^KtRze1QfkWK+#45ie4k2=yd{$-XNf869GkU z5>WIO0Y#e$fubeZyaGo}QC;^1*e9fDuT%7PwvhAX6m7}o*F7#p?{mHseZZEYt!ydU z#+IV(Y$@8omZF_(DcZ%Bq7T_p^bs3H9}`ftn}DJ{1QdNjK+&fJ6zwIT=raO}_7PC@ zIRQoc2`Ku4fTAx6C^|qu(Ln-=4iQlF6#+$G6HxRG0Y%>uP;{7pq9X(p9VG;c-p%Iq zG9b~-`3%l`QuM9+a>%i4A?M2}`YxM4`J@z`;(RIko-IW`u%+lnwiKOaOVJs&6rE*D z(K)shoo7qY1vZK<5>WIL0YyI(P;`laqRRvnT_K?8Dgi~m5KwfDfTCXsD7sES(G3EM zG6^X9jew%x2`Ku5fTBMMDEfvXfQrJ?Ioh?N<*eJ?L zKv9%{qFe+Nyc zK+$ak6xAc3s6GKj4G1W@oq(c-1QazQpr|ncMNJ4OYDz#+GXjd56HwHGfTETJ6tyCt zD4l?!3__sj))cRb0g2{t{|Z()DXQYW9MU=^fpOF+>;0*VF^P&Al;q9Ftn-A6#tPy&jE5m0nL0Y$?Jfugo4-Z%pi zZCb?Ow3DJ-?kgZ8QbNv`Q#2;UfAX9ZjpckP8poER2iQ{dAX|#Yv!&=EwiHcZOVPt@ zDVoTZqDgENO(vjd3IRn^2`HLIK+$vpie?Z{G?Rd$Sp*b4LO{`@1Qg9Cpy)9Iisled zG?##)c?1;AC!lBn0YwW5D0-ZLqD2H0EheC72_aB4D#d%>fJBqrUt*)BXjIk%wv>?b zvie4t5XafO7uMkl5Dgi|s2`GAvfTGt4D0+i{qD=%8y-7gP zTLctsCZOnT0*c-tpy*vfpyvd2{~U*(bg2dRx2fTDv06dfX<=qmz>z9yjP8v=^HC7|dq0Yyg$C^||&(J=ywjuTLH zf)FTrKgDZhK%ym64bBHr)ZMdjG9~1EIYmFD_=7J?(T|)jMW@+PbcQWOXW3G8jx9y! z*-~_YEkzgEQuGsBihgFJ=n?@%mkB7kLO{_~0*Zbipy(O_MZXeIbe({r8w3<(5>WIT z0Y$$PQ1k}@MSl`d^cMj|Hwh^En}DL2?0VRaqF4fo;s_}62q=mt1d2|jc=HWNbcy@E z>+hwgtNWHUKYPgea*86^{f$?pD3SA}D2Xja$!sag#+ITKwiIP&OHmHC6y;<~QIsu3 zx!5SmO+Zl|0*dkyP?V2=qWlCD6(FFfAOS^%2q-E{K+!D(6cr($s3-wNsRR@iBcP}_ z0YxPUC@M)nQ7Hn7N)u32hJd271Qgv$2o!~~dxs22^i}tX#&GuFk^T_(9kb=Khnz2` zs8V+S`ZX!4%=uE3#+ITgY$>YBmZEBGDXPwvq8e-|s>zn3T5Kt*%|=lj0*dMqP;?ss zMfC_Ms!u>s0|JU}C!nYy0Y!}nC~8bVQ4<1+ni5ddjDVu%1Qh)*_TD=_in9INp3UxL z5dtKkWa*)(fTYrqmI{G1QYeZn0YXulAs}J_1Qih#D;DfsvG?A^-n-ZvcI?>S^PD-4 z%?9uL_q%_e_j#W8`Qy#!1LuB^oonXWnPbW|o8629V9|I07L@?7XaWF>CIYai6o5r# z04yp8_!bRl8|?CvSoD{^>5*X;9j8~<6>Y=nms(Wa)*bnaSyV%Nv#6GA7ELCbMN`OT z(NwZoG>vQ)9Y8jV4kVjJ)5&JhL1ZkN0l=at0E=b876Pzn5de!81F&cb0E?Cau;@?#7Bv8{Xc@q_Xj0o? zod}Y;R(~r02XZmV9`kc zEIJv0MW+C;XfptdP6c4mX#gxb9e_n=0I=vx02ZAEz@jYxEIJ$DTePBW@JbORb(WsQ z4l|1`SBuVR8&<#6qVwCjPyB8cT|j%Y=t8ntbP?Gsx|nPhT|zdCE+v~qmyyk)%gJWZ z6=bvMN-`E*1;C=K0a$bm0E?~#V9_=J7F`FxqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v* z02bW_z@pm$Sab&fi|zzq(Om#6x*LE+_W-cyUH}%|2k*mv*;IL zV9^f%Ecy|EMLz+s=w|>H{Q|(E-2g256@W#*0kG(I02ciLz@k3^So9YFi~a^+k&|r0 zb}R}2uqXk5ML_@-g#cLO0)rI5{{RI*vrj%*gSC!0kb$YxPTG8Ux)uqXn+qD}xT z>I}f5E&wd*3c#Xn04(Ybz@i=iEJ_DpQBMFC^#Wi~ZvYnc0btSI04&-EfJOTPu&6Hp zi~0eus6POU_5)zi0Dx~%%jDn#B1r01y%cJd?2q(6=_DZ|IjnxEMLEgt`ysO^m-c4S zK(bjhh-?-OCYwb=$Y#+{vRO2YY!(eCn?)nYX3_p+EE);GqEP@W8V$grF#s$Y3&5g0 z02bu~u&4llMTGz?Dgt0pF#wCk0kCL10ETi-{^HjBpUyRlWtVf9Nbnw;$J6E=&c(B3SXN;Zq8k1Hhts02a*!V9`7P7R?7>(E&a%(v1BYd4uD0+1F&cV0Ef`7M%&eqO$;4v;}}gX9KY48~_%b3&5iD0KP?sCkIazK~jHB7jagZ zMOWy}qpitd^-C?fC|SN)%`Cc@_GZx~WV7f}vRQN)*(|!8Y!+QXHjAz#n?+ZV&7!Nx zX3;fdEV>qeMcV*abR7VTt_NVz4FD{<5r9QE0kG(102bW>z@l3LSacfzi*5&C(H#IR zx)Xp!cLA{IZU7eD1Hhtt0a$b&0E_MiV9^5rEP4>&TXaEk@O2R+wL;& z7XVoFA^?kC0$|b004#b1fJLtYu;?`a7QGI@qBj6o^d}l6nnfq-yRn}pht)5& z=!;}`bh26WCGE|kugGT6*JQKk8?ssSE!iyEMK+7RBb!Cvlg*+Z$Y#-xWGwm#fJHw8 zu;>>67VQRL(XRk3`VD|ZzXP!74*(YZ3BaPi09f=l0E?Uy8@6Ln0Dwga04xduuqXt; zA{T%~i2y7L1F)zC0E_klU{OneZ_&==;A{~jHLAb8|G8N-uC;_#DPi?XEoz(Mu1__K zl4)-irI5{{RI*vrj%*gSC!0kb$YxPTvRRZyHj5%;v#1jpi#h|as0#p#x&pAM8vu*C z1F)zE0E^NASkx1MMZEx6)Ej_BeE?XrHvo(F0btR-04(YYz@mNtEb0%yqWu6^Gys4_ z82~KG1Yl7Xz_+M%O7LnCB=t&H#A%b_kMzgrUB~Q{u==GI4N7sJYHt<|roCA-glrZK zC7VUV$Y#-SvRO2OY!>ZLHj74*&7x6cvuHFKi^c%3Xe34R1UzR3IG;W0iIhJpha50X z48Wo#04!Pxz@kF|SkwT(qGbRqY6M`>asU>s0ASH!04!Pwz@ozezC}|~f`dhn)I0R* zda7CUPEQG|Qo`z&T6A=ZJGqltw3_y2(HgQ@w3ciZ9YZ#Y){)Jk^<=Z?Sh87k9N8>7 zo@^FvAY;)904&-Fz@ifYShNX%MJEBU=wtvEodUq3%>XPq6@W#j0kG(F02ZAAz@jq& zSacQui?#r;=xhKModdw4a{*X%9srBB01NMYjU5=r#Zr-44K_I{;X8Cjg7?0$|bI04%x(fJOHL zu;@Mj7TpiPq6Yw2^dJC>9s*#|!vHLL1mIhAaZ2zZ5hOJ|NyNFtELx~HvL8(et6yr- z6DjV8-OQpVX>S%iMK+6`CYwdikjH77S(HXLiy~yRs1w;N>P$9^x{%GHu4F9g2Ed~304(YOz@l^j7WD*RQ7-@% z^#)*39{?8Z4Zxy(09dpy0E_wpu&5sZi~0kwXg>fJ4FF(K1^|mP0a%m;z@lsb7Ucl2 zC>P*cl$;toT?9#;t;4dERDYy@fymG78L@ps0e^X#Q-cC2f(8704yp2V9^8s z7EJ_TQ7Hh6$^ckY4#1)c02WmOuxJthi>d%vR1LtQ8UPm609Z#zwKid9YlMxXa?CVijvKunPju5j%*gqBAZ3C$!5_U zvRPD5HjCzxv1lFui{=BcXaN9=4hCS+Apk5|2*9F604!Pzz@jApELsY{qC){#)BwPu zWdJN{1Ypr}02ZwPV9{X!ELsV`qQe1Lve|l zPc}){)Jk^<=Z?Sh87k9N8>7o@^FvAe%)ekj|8tpF@KAAm&{0I=vn02W;Yz@m!*zD283gY_av>SYq$HD=MP`juFhq=wZm zr=yeL_TKBp0Rbm%q+E47X*1;OXhUghOKw0!vsHGR`I^mLp7Y0t^qE!k=9_i>y-X$SOmoMCAf^>>_+ zX`c>ooUv&GvK*%{ts%#8#;4sm&~ZxB{u=B!m1%{;9H%C2;|Rx@n)bp-$C;kiag5{4 zOq-tPICIi2DR7+mX*-J?XJK0Ac*j|q);Pg&8q@ABb)1!HPKDzfnN~c>an_`5s&<_9 zX)o0}&W5zeRL9wrHsb)t*_?LSbjLX(?TZlE=s$%-f=EVOPKFC zSEY?V*m1U{oxIR-ZcKY+vE$sD*7;D!xif9%GRL_$?TY1&^I+OnhdIupX}PN$=ZUnH zM>@_kY4;!PI4`7y);i8BX%p5t&Kqf)k9C|KX|EmcIPa%*-RL+Ur_I{rI6Kp>I@xi) zO8aKBT5Yg|}pB{+lm!r=NMD*LO=L919^~Cc75&eGIg@K5ELFm#zy>jM$}nwkxPh8e0PKX0-v5YZ0|+!%=HZ+zbxi0H5E-WiDK?_Ay+ zi0CiPJs61SZ#_L4i0H4aJQ0ZK?;Si7i0B)~F9ag`&fhD6h`x36Mj)d1-gg8ddh_)C zKt%6;eH@7B?Tej(h>kzM3Pf}Ou`3YKE5IKE5j}>YNT&L_#^z`#}!d8|KcWJe2Z?KLpqbh)FYJ~Kui%bgSNr%UhN!Uh#6n;;}# z{&iU;`(t3R$Ih0#UfE$XWDX4RSl@swMgDb7=_+hkn^WX@r|X0^5{6rtq+x`G6J$3I z?B7OYmB~($ZU;u%GiBW+jIyw*vxLzW)@m4IVXS=hd0?!CcG}@Q3n97E3FKQ?AqR>; zfgieEBn#^+FDjH7aJmO76I1TraLThsbq`E(lV0w=v$1=iDlui}W1D_Ex_h8HG3CRT zPC9+H)9nvyG=fIAZ+ZVXnPO66%4^p=_4F#Q)fwk*-EySYYR8LPzCOa~Hd#6`SQb_8 zw@PSH>2#YfEMM3$K66v9dE}kI`-61j-RF)yai!OdPtN%55x*M`Uby`UZSE#rGvt@UoNhl`qn}vfIVWFvkk{si z`)<2VUb(#B6R*Gc0(m5hyyuEFm&yz7EWhQT-Rzg;ttB_2!O;dbge4y?S^5ani_5 z+WzU)6TCLxT=V(UM|izk_x%I!%EtJ^+WbbFUeC@R;w|X*dtX^6lgcal;?(lKUgu`t zzhJJ@tdiw~UdsCf=)9SNcsnv1SU>E%p|(={EF<5ngBCef;XXWHU%-2b@+i+ndb|t3O=k z^q3<}7D$tBE3IwE9DAXUEdRc<*M%1^d%E81!ud~cdsSv4U2tzbrjyg{4C_LFzlqm{ zD{MA1n9a_Izs&Hu@aZ)lUg59eRiECR?!EfoUjOU5qnsYsNShVfhuh_Wu7-1I-2b2- zCwYCC`u@22ULV%K^XIGnYPfY|Zab&jAUTq0ljmsiNOeL<+Nh2$!!;$zDsrx zS=-N_`OZ4g;CgAJt0|akyZ;~eZrUk6i#vZTo#=Xv&OCm{4&8$iQ|>tXu@_f4-R_k} zx>bkJXxm3$KdQUGn>47!q0%K;x1EnarrKLS&yPN}r_*hREoUK3-o5^%+hi9IvDf|h z-ET5`5&M^4x8COW?(>UxTp}){%i&jhccI_PP5M2!bFjCZk%Q)I=iH+?7_3hQ; zPy6_Ar`uF%qAuLxH}N*aQk%_A7XHLfcm6Ehl!f2_(Rb@)k+SgJ*Z+F4zcvSS-MF{Y zqfr{IlNqINu-4wu@$wUQZ}C^pi6{Qu+v~xsx7SSedT{aDD^FSNI6XspOzl;c?l}4{ zF(H`P>rpwm=)c6hgDraB&Rt}LLaA9tI>iSC)m*mwi(fC z|5n3Wm9&#f7<)!uk~`Q@lDLmo!l6L0&FEIGWGa8^fIQctuQcu|3);(jAUkGD?}4b< z%I53(^Gyl_O4@0Y);(o*S<<9UyFjZ}O|xp-+6lIxAFW!oZk5z(m`o)n_xPz&WU9E{ zrdqUxw6j@C)J3(oS$fYl&9Z~d(x&PtjohYwq_vj*>5?Pf19?fE2E{FNOsA3ZX_3yE zfia!v$iAIQ+NA_i6URojbvxmhfNYr@Z>4nKcuc@a zh@6@)C*B_NgriT$E`H_>1ZDoxA7J)ufb{lbF##MQ>o=GIf93r9|DyZ z>Z5n%pFE*OuVnlunz!}S25%0Nv@nNBadVgyKZi*d{;N5}vk~6hsgg$z~e?m(yQPqD!A9)vPPHlV-nm?8`EVHcE zqMZmh2Q;mmYOe=Eb$-={sl5Kvl{BM<}O>BwX9)wRzq~z?E2`^h9!;lvm5K@WX*0k zd}-qn1+(ktEN`e^7WbS^FH;ZCTH3H+(SpVWE9#xB`AZhnXVopNUzwG;aLMetg;~qy z*EQ5O0dw$)5#mlnh&7K{tYgm+(lN}ux&CSlu ziRNT0%n+Edc*)}WjQYA+3o>%DGY4kq)0y&gv!}8aES|k^`JDQ!MRl|1FIfElc{i3F zzAS!C%$uK;*Dz=Kg2hV;mNe97#MZ^i#s+Vd_-mxHVadU=&X;9XFRg1hq?4JjMUW|9~Czj5yWZzNbz*I2LH!f{Na!PyHkXRBq=IrVevmM?6KHXgpT zep%*xl~+udvtV(fgrMVyf6>`X7A;z`I9j)KfiUs9x}Yd3Yh`wU$A!s$fS(I=Sw3>) zvn#H*GX#eOT({l7`*8z_!Fd6&2|z( zfevmfEp6SNT7-L1TjaX!64Tty{oK?(Zs)FUyL7K|?T~O=9(f`|~?%dn$vY#x$dj(n9**V$S z!A9*XFX>;`EbuOU8Lf_XK+(SOPU~!P{VgFIMqh4Ee*^XH z?RJh|i~rF)x=35u^ZRAHoxA9)Vr$;-Pr{UTw$cBi)z!I=+r?kk`ZD|OBQJYZ^OxOO zHfWatvLs$9a`pNjy<&H-?0HQGjEVBlKNd9|Fj|lFc8RPESr*G^dUbtd`s8#u&X4tW z@`34YhfGQ3%~G)K$UX9exSS#f2t6`)&vJY8a8qOWXJSqY{ton!QYRZ;0A&lgF1`ggpqFh#Na?_D8I}gc*r)T zRU`jT^`~`k`UHOmlcVH+wcXn1O79+YGDpfr2;O#7!e}{w%j<28sk(Qo3|VsM@7zNl z=&sM>n2Y;Jn;yN~BS9=d>l-rtNKs(q5uCN_P^sG#_s=r+aWCY<9q9R&aQ9jP8DjFBf$txHio1&nm zx>nj3RFqYg7S+gyqdgdd2LyKQI)=qiYkBVfy3e#TwW2a zuFbD5s4CIPiYsc%3%$vP4jb>);mx{PRa9MBAwBfxG)SglU1;Bns`9Gidd_+)s~#84 zuPrW?`B#@5P!wzOk5^VwrfbuiM%QG1c6>)m%A>U`c(`>gr?}Z91y$23YbxX=mzG8= zD@w|1itHul+Vpu+WoS4sH`?gEg2HCa^Gju1SXJz8hNAL3iG@x@adkAW(4Wm z(PCLsv8O8Ys!D36#iB}GmRCN_HeJ&!yvP${SC^I4cyq2Q$}61ay_o!F!d6x1$&9>BEi2f>W|D^)@Zc4sHR5uWfomr zP&(1;?!ZC*o-^26qPOsDkhe2=NEEhhHO!vOk<}NQTS-Y(abC2jpdgx)Ut+s?L9<=a zJG2y*)l-9`p6PpElgC11$@S}&WxV^KmXmW|%2+6Ol_SdrP8}Y{@ ze^*kOWhLv*t?MJMdDT?erK1&-i>iuCE2iwZ(5murvBRc#l~)#&bjOBT;dmxGqa1~K~_c|coPht(BLrzt(` z$DXs}ZdFlfk#}s?l~vT-BY#WlYnF{!QtYo3zXwC&mf{_EbmQm|&O4h~FPnM8P9M!H zD5$N1NXeve5jh zJUOMCLb^oRI`O-ZtSSz-r4`k-6Az0mP&R|V2J?AP(u^VEGQ=cn} zWp*M-(;>R)5KvH15gjjwrdR{kO<6^u-+MXh$DS-GDlM%o&8rg0$CXrz&w8rjgU{5X9jzWO*Czgyaya9_7PrW8vy#%% zqH%epw#&&`zEJl0rqi6~d+dx9x0Q2-H8b8+8835+yT~f!Wy!|f!-*0-{OxhziNA=D zLxHyod#fk5XXFfSHY0W)wpQHvykv11Ogd9&ANM++y_L<`6JXYl5y`yp}D+Yzfwj!Csu-igUODi+JC zsU9D9JjUYEylHyzXlGn`BnPXx%NNhi9yHL2PlK$t%_NQ4zQ;Oe`^R1Wmdf7HWB^Ma zmseJn*R*tTQm(F89kS1Q3vJr3b859P_ z%a&%$$r&P~u3`54QSx@xieVXxG8f4kUi-~iwsgO_OVcyvrDs&+rf108AfskW2Qua^ zs$aIOZeD%H!urMY8t0G77Ub_`8G4YBr0cSA!IH%p%jBIRsmp}T5s6~idx=Av8R%_u z|Ma3)?A`_}DzB)OgHYTi89dzIB+ak1V`nV6Sj)>VDJ?mm>1sJ!4#Q0fmn@!BztWq< zz-9;6rXzvwPB9Uie3rA193yJv!c))Uu?g6w-Uz8_Q_DVAAlC%>c`|IWgRJ^5SNwkW zhc@{y=X#$tAD-yoK`#|bWOU$PRCxPup{L@4(j`ll<~Ux-{YPJ#ov@o-2bam5@++ps zuh1dG{?WdmRL%}^zSX0bE>tc+)y~*nl9QcluOfD6mdz2HP18EltGTGHIKPFQL%j#G z>3tx_wYbBX=Rnh_ZI6p_J2EyukqnYK)kpPhx%!3%f1Wak`xl+@593uu1==gQMD<=y zUj4G%!9$7`dv6~X)_bL7@q)(ck-;i@-Ne~?=(?{GF6%RjxV8`LfZf|z z^1zUes68at+};C!py{FP*i`-_4#9C3kKQG(jEw9;P7VnE+~mc_t-ZJgdMzr4H%}dJ z(xxF}Y^*!P=Hid?SgL>EFDk2y8@d(f&4l>VjP^TzVgOfMQe4q|blGHCVP1jv7HqS#Q|uu9&wWS++p^LQ(OoFk9sgC=mgh~D zJwyl3v1j5|YF@1j&E*0vekiUNU939auyHc1@vnelPk37ERc=MO9zwj+dd`3OtnFYj z&NG3UhIh?JZR%ibhoB?Xl_gOdee3pMw3rv0o18hAv0gCQGUQs=9_7eTA=baRHBebq zF}_5`kFqJs5-m0Px+P6JU z_IcHMTP=1+M)slDOk?A@ynOElTkMIr6QEXm(g%hsW*uXhGVmf?JvbsqP23z%yjX*B;IM}}p0i#y%}Iv%)p}fP@=_=HmlwHg+-A4&nq6A<*yGJ#>K4ZCh;NVMM$>g> zVbQ<2($oz+t*FNF2JAXd#(vEY0BW#Y%@oO<47smr*L5;=j^32^dgb40FUy-6Ehw+C zGfMoOX0Lz$JU{wlGhS@$j+{5krd!rIasw@Xe`>nxqp#TC6Pg`?Vq<%qV{BcIl<&Qt!aBKD=|es3p5af$YWq`YjRv z4s+9q?jJ`n`E44Tx8AK~-tjA=xTI9B_u_9zG+psjR~OiOL(SGO`v$Jd9ag&#S>lfu zyprpmfSYxR4#ds^u}u+oT-1>%6S4?@KZ>1~y|op8XVp{eU!B(dgM92(9P{zejp+}d_Lv1PM~vIiB)HBa2d5KqS5dE%t(k9K_FAilPuRjXm<>kwrZF%3$dr!rCT1QJf8Fx9->|T!7y&OB6=~&7GdMDL;;NR`lhm4JK z;%}nbT=j;1vFse&#A2cTYvZ_OJ9^yx*ybY|uAsaH%La(`-P;T0#8{J8rI(ztr^w~a zzuOz*ZU@_|%JJ{z>TLZn8r_q36YL7fyL#ab1#kIrX8_aMzod%Y5|w?L>moY@^FCpY ze<#C!ZF=jg zX+V)P$n#m}r#p!^U%fTzcdglRC9hJh`=`pVyqV;2-SgLjzw_{V*auW#d6Rk1yP@8- zS8-nag$*s3RC^LPPLVUKtzG}jqfh$-3Km)EU!}_(z}R~6JdvYE3>1_VHXEvn=WMgs z){7Ud>7c8(#N*$YqPzaf_Ewv$Qg8h=A3Ze9Lf$;(VvjyEeygsnmiNPK{QQqwp?Vi| zk2gT#Z^vXeyE)S|vXuAU?d>$}o(_Cs<1v=6R}tPx>|c$2)g6_O@tn@3*j{6f+&_!0 zRn~=nUp4Mm3H(8bw{qeyZN1Ur6nT4C-ypBBcYNuRe`{ag9^CUppeHzeL!HAFZ^+Uz zzcjCWqU^v$a@TE->n?pMdrsc8VM;6H4L~`Z$nDy^^0>Qux^N9D zxqq}^;of1O`ro}*YAcZ*#x9%ufsf8DNAFiMGw*a$p4aq?4!RllTpyLu*gKQDYB`ZK z&BNbNQ!1(^+DR~Wv5@26Z)H+B=I|a$^O0Dw+>2xoqraZvj4LP@k=|F|C&+79lwP!G zR{fkg^2T2cpJ4IcI^dHj{r>$M2~LuHwuw{$XQ2RiK zKw2;o=oIK2=o07}=$_CkAfG7y$4@*8Ip6&qKS5AGsuA}Sw9goUg8E5~xSybWN<%(a z6!#Nyj#|3`uryOWEGi5T7!;!(l72O82dQ94}(tg zk3a>T<{wuJI`YBBxSyaSAGweF33|P60zpSU0T=fZbmY&a#Qg*v`IZvNy4H02rONsk z68C(vJTBZLPuU~a?~#}7kq_S^AHPSIuZD>I=<+U&CHXX?K5q6=oIZ_CA2|g4_xI@I z-jvAJ5%ZpJ&c>f6bK*{u+44q`e>XpV3K=BFW|%GSjKrlu@?K!mbMii+{A`tfE#*^; zyRBBqr+Zq;N9g8gmCr-!hxA)^mM@RcD${*$HCsGOkncO_C?6iu>3V6E=L@aAVtlvN zvErRhSFTk)QumuyonAE4gm3rwS!e@;v~pM z?x|It>}y<)5jvf^sCAUpe5;jK^>d5*{A{ZSTRqgOe0bPR|bFD72s{5-h{|KwcSUth&W~*DQUSRcdtNQ(D+Wr=+cUyhP>JwI`YE@5fn!{GxSnXi7tJU6C`&-SiI?U=AtHoB!tkzgP(CRF!3#=}+dYILt ztsZN2lhxC$o@@1Dt5;dQ!RqZ+@3Z=-)u*k#Wc5v}?_2%M>Ni$@vigVBpd3GSJ+-u& zVl`s5hgJQ?5uGl>>L9E8Tg|sxVztuh6st3=)>~a@b(z&wR@YkHVD%KMXIVYp>Sb21 zwR*GFyR1HFb-UH)tiEb>ht-d)eqr@Ht9oA1*Za5CL^+>mZf&)_Rr$oe$9q}rXEoRA z{#FaEmRX%_HELC_qjdgeE(VvHFhHPpy7y zb+^@koTzkuEv>e*+STgbRx_;*wW{9_r0q(qR#`pJs(t~AKEKH73ahKFZm@c))pM<0 zYIU2{+pOMib-UFUtiEaWL#tm}{n6^5Rukp?t^H|hwUgChR*U5tP@k`|I$th7H8)z_ zDCcs`XIb4Qm!F#NwECQ!!!^HUb(dUzYW~COVEIBO&G}Z3kZT9c8>~Jg*F>71vl^Cb z7R~LgmdUk+<^!yr-qX()S$(s&pFg$QV;?^cuv#w{7}~zU>b3p-e5cj#2Kf0et3%~N zM5iybdQ^^|H(Gr}uJ-i#7p(3j7c81PTCEu7=jm3@9O36ntiC0zcnv^@k!qJH>t-KHjgzR##8(^Cqj0mHPQ5tF0>h9I-lSlAmW--BRu6%dEa5 z7hL-KzOdSRs-Ls1E;zu?E3Doy-Ou-0{b`1u6QX|Izs|4Yt*)Kz=aa2&ulMsSR$I^a zb7!m72m5)Z)pHj5`3kG=E%x(QR`)*C&$(6)S?1@JR&QGF=liY7*IRk7H?-2PqgMHK zg4K0L`gya}Cy(~?YgXH?^>bINwd?#m%j$W@`uQrW9~|%JZ>;XS(a(ddF52YhRaS2~ z+0PGJ{Z%e-b^9cq>en%+`?b{Sv1j`EG^)eg`2xtG-gpY!v4s~5|FL$}}cRzG{m&p%qtc-7A%tS)=q&ugsS z^`@U6xB9nyL7~nsX@_5n-t}vh)f3O^qHRzwtDI3e!kJ_ z=U@8yXRBG?_<5w&<-7cRjMaO-_wy5013&q>jn#3#__@aFNx%B}T&pk3*CXodd*5oO zzx=$9)u;@>^!bHWFHi9E%~rn*`FXe19QiIqoqn{{!{kd9HLtgNpM1Nb=BKO%+xR)z zYDu!6CtE#526{UER;#bdH!y1c&}tX?Dn`wHt=7qRGHPCI^-B42M$NZc{aU`IQS)zB z2d4XZtkuJN`T01j56FO0r+>z(E8m5xIo0Y!`ASF4Q?1@Kz|Z$veah;qT3z`{AIslr zZR0pUSlw+rnBnuV)g-Ml|1`^8tfm{^&vKU4LB{i}mRmj0>U^uqtsZ0b6sudUUTyVu ztB+WHL94tDH`A~CTdlCV&gv$s4_W=$YJd4|KW#t5>KRs_u==~zOc}WAbahtGuzHo% zx2=9`HBG)?PN(0`YSij{tLIsL-fAe>1Ru8gTXZ2vKi>)4J^$4r$t!}W|!jb(`UT2ckc2?7@_O!aU)d5zstxm97 zZnf6xG^?|%&a=AMYJ=6Yt;*@l>xZ1Cyn3b8>#g2wRZa`u^AB3xZuM!aav1iWm&2`B z-?#d))o-kRZ&eOk-gJLjmBWme<#6Iv{en|nKe9V{RaTot@Yrs9)jF z$tUvFT=B84LGSO{vivFjNfzoCYuOy7vreXdT~ob$-Yssaa~tXw$wYZoWtnx2jSUNC zEpL?B{>MLZ>sHP*a{Xm32JO*OR;TyVQ~uZKf_`-NoKBz9pMB+@?lb@0bh>}+x!m|~ zPt)zGKe|8dCI80CKmFNon0z6xG?d|(-1+za>GGz_Kl&gKom-{RsVbxW@JKHEo6T>t z+)zxGmyY<`t8KV7fdzqay^`Q0s#wT=3q zKX+6FoM<2avHq{m>A%OUGF?YGAn37`AEtXrfIjADrc5`CAXS&EKhMd(_}4o%?)B<1 zp8mZjkHzJsQoNtDWqu{ilwoVUX7(SOPpQbuUR|crQM+%XTRUy>ODV{ z@$haZXZC#k|5ES&kG%hL-n^{%_To^V6%$|9i{8G!zqMm`a{42?ot`^(x3?Ox+SRL5 z=jS_ry!x_C(dN74Hs!mM2k7I_pz_^G-lNO&%Xhc%9wmL3oK(I$G~mTIW=yD_f1tE_ zNtPZORlIxeY<-mY<+1J|GxgE6-v3|De0hPs>P|1b9DBvZvB%Ep17eTIu3j8_yk<$m z3-|5Zwf65{{`y;LUg5-|2}LEv<0U^Z_WM~Q3ndkeFP^x4cjzIV=BD(DU2F2j|9o7p ziXZa|ga)?nzA<_G?#t4Tm|6dswir2KWXY)UqyEw2tXZFY#!`k(96DiG$*|Z`hE5nN zY1kfZN@Xce$J*ph%$+c>WMHgK?u1-P1OL(HiqxB8Z89ciOvo(B^xClO0TTyI$SBE( z&1b-b0g^KIn9um{Z*Ms1Gv@&(x#QR~r~deBS|prvXZAbWLUj{oMlSd)di1c*r_HH4 zIW_Oa4x_qk9qlfA=*_ihXTP}q&$e^xzqxAJFMF-~Zf)5YKfj-RN8K5N4>|vwqm%D> z=A_d`jCeEa?`M~+%%6V23QDL38!ZNtyk zoqyTNP>T&$tlV5WqTOfrC0&<)ZRFR(UJuR4?0-Z~hld{Mx%2O5-+Rfq?~%`6O|Lpe z#vA^zBNW(QcH*R{?46_I_juW15(0_(1-%J@77w?SlHg{`Auk~ze6zq{N7ytm9h6ms>m0tun;i!w=YnoJNJ&@N9OUm}YR zX1A}A$L=ZeU!wje%hx|084hV^5en_&-Yk>tm7nc|_O-t`)PAJ1-Cy7JlJLD}!Bo1>zSr*eI4tGM?7CTDJ zk#6N!?x0!vm20`ZX6e{K%k4Bv&jwje)ht~bY&k`<^lgacWX;mKp_bcfmfj7s+(xr> zZ@A^wnx%guEGJ3MmHzE-xs_(=-$=_XHB0|SS>8*t^l!A~7Mi7hV=RX?OaI1NPSh;@ z%d_limj2~i4r!MD61yz|5k6vF()*^ zH{^6VScMjb)f_cssr$1$=^1jUH8n#TESe$9ESe#W7R`|57R`_q7R`{uESe!JEt(;R zTQoyfS;UYdEMv%#mNDcg%NTOBWeizu8AH}s#*np^G2|G_7_!bXhOD=YA;((AkmD?4 z$nlmjWP@c4Il(f9Y_yCaCtAjkO_nj_B+D3bvSkc8#WIF$w(J|SIH-RerB$7rdqPWm zL*5WILZ^n+95v)jHzFrQ&ycgMsTs1xq8W0wMKk0ai)P5V7R`|JESe!(Et()HmNDdU%NVlVGKM^18AG15j3G~1#*n8iW5_d>G2~gx81kHD40+x%hP+@I zLteCuAun0Rke4lE$SamHaLq4)-hJ0+%4Ee;O8S<$`GvqUi zX2?#9X2|CjG2{!&81kiM4Ef43hJ0-qL%y+$A>UfYkX@EBC-Uo2zDZp#?*t7Q!N%`%4kZW%-Vu#6#pTE>vSEMv&umVHCs39gpy->Q|| z*$utx8IqKu#}FqFR&|`#p-?E`Ues3psECec+<>+2Az3ba6Up5r%Vl|(+)c7vmbV~x zl`NO#dy%_Hmdo;%Q^bkfdw%@+27WEy~cV*}Vf{)k`hv7jQq7 zduyIW{b_F&?MF6?29V9746<32Nj8hJ$YxPC*(}N-n?<=~vuGe0iv|I(XfObah5)c= zC;*Fw0kCK|0E}+PG7U=aaC$UAgq3=Mdbl^Kzp;Og7#)nCD|;R zL^g}6$YxPB*(|Cdn?8vXXc_>E4gg@$fdDL;4#1*=09Z5wfJIRN z7R>};Q5^t_W&yBhHUNv}0I;YYfJJiwSTqlSMe_kzv;crb2LrI^5C9e}1Ypr302VC< z_!gB0f|Ep$q+2D1%FLprs??G|Sp8CqmId4fd2hfw7B$k|ELu)Bi&l`$qQl5$(Mqye zbU4{8T17UCjv$*wN0QB=qsUlvGyscM1F&cf0E^ZFu;>^77Oewd(Ru(D9Sgvs;{aH6 zJOGO}0I=u;02XZoV9|*HEZPLXqLTnvbTR;oP61%iW&jqQ3c#Y%09bT7z_;koKyZr) zl61I?v_lPM(R1E7D-c${)S|Nk?w#^3w`b8gv^R^+C7VU(k?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4fJJuzu;@;JZ_!zS;5#Bn(jvW} z-eMM=rWV~52&-Re(R~5;ug+%C{j@iW9w3`V50cHIhsb8p!(_AQ5wcnIDA_D}jBFM? zPBx3SldWs#)mdMvuvEb6Ui zw08qx^-C@KFyI!-FTQ)nqK{~A7JW=Mi#{QnMW2$*qR+@?(N3~i^f}oq`hsj0eMvTp zz9M7M*8nW~27pE100e z02ciYz@k3@So9|Vi~a&&(cb_pauQ;re1D7<0ANu9z_;lAKyZNwlJuwiYFFq3vnZ?w zreH!?{Zfm<3GT)oW>E{;n?-w(&7ziMv#1r>EJ`AqMXkwZQ5&*Z)Rt@(C6mpf6fzd2 z0R02XxtU{O~97Igz)QFj0q^#EW|Isl7$ z0D9u&56Ji}nU^EZPTvMf(DLi`<0Z4I)U=EqX&SF~J|{ck%{o31Rh1EgF#E zzR=Sw%Ambjlu0&=vdCspHrXu7A)7_HWV2`>*(@4FHj4(6&7vV>EE)>HqG13m8V^>G0I+Bx0EqQw9#S^~hLr2s5C z6yRG_kr3Qp1WCF?k42Sck$y@t)Q}KXzto}?3GVcL%%a0+Zx*d2n?;9{&7xIgv*-x2 zS#%`XEINv879CACi&m4(qBUeJS_{CUV*psR4uD1L0a$b_0E>BK^#LXiGv^{Zfn0OK>mgYZh&#y;*cV*(|z%Y!+QeHj6GIn?)Cs&7w=l zX3?c&v*?4*(Ukx!x(a|rR|Bx<8UPku3&5gn04%x=fJN5>u;>N=7TpNI zqMHC%bTa^pZUJD?tpF^#4S+?r1F+~002bW|z@obVSadf4i|zsV7M+t2+%AG7of{Bw z&NYjU)??AV31Rh1EqXA)-PzwPdWiOB(Zgi3=n=A6^eEXZdW>uqJx(@@wv)}GC&*^e zlVr2#DKZv44Zxyj09f=a0E?ajVA1mcEP4TeMK1!d=p_Iay$ryjR{&V_DgcXK17OkX z04#a~fJJWtu;?uS7QGF?q8$J%dIx|-?*g#sJpdNH5AZFzKOxw9Ke4Elj?o@4i%!J} zv1k_ni@pP3(f0r>`T>ANKLW7mCjb`x48Wpa09dpefJMIou;@1c7X1#uqCWsw^d|s| z{sLgp-vBIk8FU-7%%WDbH;aIUhS=5GX7PTdtMag8dD1~emrIO8}c4V`t zJsFES0I;Yd0E^N9SQG(ZQ6~Tvbp~Kj7XTJ@1z=G(02XxzU{MbM7NrBQs3!o6dI7Mg zHvo(J0I+Cp02b{7z@mKtSkxDQMg0I+)F0qm)FK!>M+8Z_OMhKxub@BDZ>twc`vt@5 zms*q+bnnhFi?V5N7Uhu5qFl0BG>~i-4I-OGgUM#m5VBb`lx!9aBb!CT$yhW3fJOTQ zuxKOzi$(#kXfyze#sIKrEC7r009cd{z@h>G78L@ps0e^X#Q-cC2f(8704yp2V9^8s z7EJ_TQ7Hh6$^ckY4#1)cfNxPoF!-Jbl60kB3T2u_yYyI884RmmYEezl)lW5g_pWPc zZx&4^n?+N|X3=*Q9S^Q<^r&29srBx1F&cT0E-R=V9_A}ELsS_qD25KS`5IVB>*g13c#X60a(-k zz@lXUENTS!7F7jEIJc_MP~u9XbS*~&IVx7IRM|H z!-By>M35x?Vy)0hvuM34b#5@MeyK$l1l>*Ysa5Y-bRq4{qKn98(Zyu5=n}G7bSc>^ zx{PcVT~0QOt{|I5SCY-5tH@Y%H2{mQ0btR!04&-Dz@qB_SadxAi*5j5(TxBsx(R?q zHv_Qf762CA3c#Y<09bT80E_MbV9}ibEV>JTMRxy#v6acL7-R9srBp2Vl_$04(|tfJGkxe2X3m27eJjk{;6w z>W9su20a#i91N>pYSGT18yRI5eNKC`=nJx0^d;FW`ig88eN8rtz9E}M-;&LuU1YQ9 zJF;2yJsFFB0ASIN04(|mfJHw8u;>>67VQRL(XRk3`VD|ZzXP!74*(YZ3BaPi09f=l z0E^`JyZuo*76kxUlmNh@AOMR(04#C=Sd<9BqA&o9S^#{DJ`Dy(i6BWs^mg@UX3?>F zb-h<8tbVCQtwZjNF=kO4+M7jf$!1Y9*(^#Sn?R02XxtU{O~97Igz)QFj0q^#EW|Isl7$0D9u&56Ji}nU!(LMky z+82ODeF0e14}eAe0a&yj0E-3yuqXrIThuBPTqlAgov6p6q>w+-|3Pm-W`@G*ms*q? zaxcp>iw4r(EE+^Miw2X;q9J6nXeik%8b&sYhLg>r5oEJyf3jILl8i;809Z5{fJI{f zSTq)ZMR@=$$_HRk0RW2%0a#Q7z@lOR7L5a7(RctBl>o440sxC90xyjsUC}}Lt*txEt(Q?zbG(^rqbRlnnpH@ z4j`LF2a?UA>14C$AhKCBgKQQ>$!5_^vRPC|#-dpOESe3#qB#I8ss~`vTmTl$17Oj7 z02VC(V9~(0E-#`ShNg)MU4O~S`NUX6#y(c z4B%T-8w$296pLy?BF<#9=yN?5tqg_LFSY2%kegj>79B-8DS+tsL7Of$hMQh1s z(J^GRXdT%sT2D5MjwPE#$C0tXPq6@W#j0kG(F02ZAAz@jq&SacQui?#r;=xhKModdw4a{*X%9srBB0(^^Bg@Uyr zNYYsS^~NL2qJ8B9uc7lpVf9Nbx;W&n7;hF`LVL65QnFce8QCnloNN|dK{ku7B%4K7 zk?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4 zfJJuzu;@+z7TpEFqPqcDbPoWF?ge1ceE=-FAAm&<0I=vm02Vz2@GZJ96g*D^NzyO$ z4_#yy9ieBmheKiYOD%dli{7QG3;qPGB8^fmyCb^x&G z9RL=+3&5iH09f=s0E<2VV9|#FEcyt5MIQsO=o0`IeG2d`dNdULKm}MHj92Fn?*m7 zvFK+27X1RiqTK*2`W1jhzX7o5cK{as0l=a^0a)}G0E_+xV3Fh6upNs604$QX%xS?7HJC%%T+9n?SX2w}EgI+sZxKO~>RX67gUq52HB5HH>X%w{fa|_eZ5AC!d$VXd*(^GUY!=NR zn?+HwSu~Su7S)l>qFH3KXg1j_nnT8-dH@#91z^!U02a*$V9^2q799-0qC)^!v=D$r zivU=(7=T4f09dpXfJKJ_u&4omMauwK)Cj<$rkO?W>9ObtH>`fCMXO!6^JKGV4eiaMwPdsC7_wQkj%*gKC!0mblFg#y z$Y#;;WV2`k*(^GNj71v(Sac!)i#7qU=p+CZoeaRDQvg`B8GuEn0b02ZANz@jq% zSac=;i_QXI(G~y}oejXEa{yR$E&z+p17Ois02ZAOz@iHPSac!4x9BK0I7S3XnySOH zqs^lBdR=sp8&<#6qRU)&=2Wxja@w0kSCGx3E6HZjRb;d1YO+~$4cRQZmTVSnBb!Cn zkzhMYjO3=vDw0-3Gv-+W}Z~2LOxi1Ypr!04%y2fJOHJ zu;^X@7TpKHqWb|@^Z)>h9t2>~LjWv#7=T5O0I=v$fN#+yZtz$UB0fFVZI|al zkGWy>OD%fRb+0(UEP9IeX3^7Rv*;PJS@bN~EP9S?7Clcki(Vj`MK6-gqL;{K(aU5k zdIf+*uL7{>H2@a94#1)}09f=U0E^xNVA0zEEZPCUqIUpT^ezC4-UDFK`v5HZ0Dwgw z0K02X}=z@kq8SoA3Xi#`Kj(M|vseGc#~+U^FQ7D1BQ=&|Stv*-{#qkZ9q)i1T^ z8`u3x{$hgnn<3xQ-YnWhHjBO^n?>J~&7vR3X3>viv*;(XS@bj6Ec%6P7VRcu(XRk3 z`VD|ZzXP!74*(YZ3BaPi09f=l0E?VN8s;OkXWSeyN13ti}um0>$Ztu^-C>km+0n3 z&7$_SH;X!u&7zKEvnY*h7DdQrQ75ul)R}A+bs?KYUCCxqH!>D=2VhYT02ZYKu&5^h zi+TaDs5bzM`T($KZvYnU1Hhtv0a(-*fJOZPSkxbYMf(A;XaE3d%vR1LtQ8UPm60X48Wo#04!Pxz@kF| zSkwT(qGbRqY6M`>asU>s0ASH!04!Pwz@ozeShNa&MMnUz=tuw-9R=_$IxsQ#kqDCX zvHpJ1bhBu_H(*N)t6yr-F^O(yu35B>_GZy~vRQO2*(^GaY!)3)Hj6fp&7u>?X3<8n zS#%=VEZRiIqLTnvbTR;oP61%iW&jqQ3c#Y%09bT70E^B5V9}WXEIJE-MOy$^bT$Bs z&H-T2xd1FW4}e8m0a$cC0E;dFV9|vDEV>AQMHd6G=n{Z$(VE0yKM^Epwq8)LHH(&b z1GdDl`lS|KndnZKZx&red$Z_jvRQNu*(|!2Y!+=Jn?=`=&7$kcX3-5~v*<>$S#%Q_ zi*5#B(JcThx)p#$w*j!|b^sRL0l=a=0a$bw0E_MhV9`AQEV>tfMfU-)=zaheJpjO> z2LV|05CDrF24K-604#bGfJKi1u;_6B7HtRk7G0hgTq1%b^Fz5rm+mjEpK3gBDx{}6W{&{5Uh;{MNMa+sN9NHRkSO$@!K&_R&i zdle9c0HH~f1O!9@LBtLSh>8fzje_{!`<(qGdEdLa*E*%X~-HbuWPo1#CMO;I7UDf*My6#d0)iq0^j=qv$6e-lu2j)0MwboMtz6_`y?MP^e}iP;oYW;R7t zm`%}n%%-R+vne{C*%W0kqo^7IMb!x?szE?eO#+H)5l~c{fTB7C6xAi5s2%}D^$93y zKtNGL0*V?DP?SkPQ5FG3*#s2j5Kz>ZfTAV@6g4HFs2Kr8%?ZAuvY}uH0TP|B@AS)s z{CE1j^?|8HD5Snr(FGxQ%;l!24f~s-w#=sJLS|Fcj@cBoXEsG0m`zbfW>eIO*%WnV zHbq^SQPh=yqHY8fbtj;x2LVMr2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS z(O?3Kh7eFRlz^g(2q+pxK+$jlibfDnbTPqK)G8FbPJl!Y$e7sL6rIw?qLHDH`cg%s zL+(TQrYM*FP0<);Q#6*@6pdpxMS0AoXgsqin!s#|CNi6%NzA5bGBb)UBcNys0Yy^@ zD4Iq<(R2ceW)M(xIRQm82`I`Zps0X=qFDqK%_gAe3IdAe5KuIifTDQ>6kSO`(R>1m zt|Fl5Y66ND5Ky#`;48W`6nsyBMDN$PWur{dSbcT9C=^m(s_5E~`|B)Iw3Pi#(RIwG zXc@C9x}Mn--N0;$Ze%t^H!+){o0(0~EzG9qR%R3}C!lBr0YxhbD7uY+qE!SGttOyo z4FN^B6Hv64fTBAHD7uq?qPqwvT1P<9-2@b^C!pva0*W>eP_&VNqD=%8-Ah2xeFPNU zPw*8j4h7517DXFnOk84$e%EgvJrD}1FIBWTxB!Xn z(SIBJuqnDrAB)}zh18cS`XJ=an`eslu)itV%WR51WHv<~F`J@&%%fSDvnkro zY>GZ*HbtK?qv&%2ioPJA=t}~Mz9OLL00Bi`6Hs)JfTC{*C^|$y(YFK?eMdmi_XHIE zKtR!90*Zblpy($8ijELa^fLiPM+qqUg@B@82`KuF;46AB6ud`(L@&~pLhqZRqxx8M zEEG~-s_0b6-7()3oo0Vi^gFXD`h(dN6*8NmKbcL@U(BZH46`XZ%WR7NW;R9Vm{If( z0Yy&O-nOGCKtNFf0YyOqiV_JZatSCZMLc?IuQzfFF>L%>O1|DrYNqY%7sJfOBGcNyQLPGqDt&< ziYhakqAJX$=sadqRF&BjozHBFGMG(KHD*&(o!J!CU`A0*0*Y!8P*j_MqB;Z=)g_>) z9sx!52`FknKv6>iiW(76lu1BQ76C=s1Qg{EP}G=!q9z0sH6@^^839Gj2`FkoKv7Eq zidqqTMd{&S0|64LyS*2gqIT?WirO=qq7KZas3Wr} z>cnh{Iy0N1F3hH=E3+x;#%zkZGoz>n0YyCtDC$K(QEvi@`Vdgmmw=*v1QhirplARA zMFR;a8bmJU5KuIffTD{CC>lmU(QpEaMi5YRF#$y*2`IXRfTBwYzM?ka;N=1& zxFl@o1%%#rf3qgDVoe|iY{X| zMN^nf(Nty>O(URaIsrv92q?OofTEcM6y+08R6sz{ECPyV6Hs&o0Y!5ND4I(^(L4f* zt|XvnJ^@8n5m0nB0YwW4C|XEB(INtht|6dkF~L`q8xC$2AkmKcQfQ1R>ZhcZghT2} z6)g+9pI&Q~^%BKV4yhJ$|#km$C6z`4#8U81BO4u{m2DtavJR$XR_9%p}3 z^aQgh+QMv#o@6#fPcfUKrjV_-CZOmI0*c-wpy(|Eiryxm=p6!z z-X);uJ%X?3k#Mk+0EzaMG4WAT6xL_7_roFerHVcbyW?&!MIW)hDcZ+uiausGMV~O6 zqW#RK=u>7>^ck}$`kdJmeZg#szGOzxR|FItAfV`L0*Ve2Q1lG}MTZC|`j&vA?+7UR zo`9ks2q-#CK+%r`6#Ya%(GdcQekP#kC;>&k5K#0h0Y$$NP;`udqT>VGl8?$6gAYB+9$&y^`(mb2)mnaGDU^#Z;Jk8Hbs9io1!z!rsyoQDf*k)6rE!> zMgK6HA}3<++f7k`8AS;M6a@(=N+h7jC7`Gj0YxDKioygGMF=QLBA_UlfTAb?MWqQS zN+F;qm4Ko&0*Yb;6vYWBDnmd~Sptg65l~c~fTDDQujq6*_<;b4?$n2$-%Zgu{T5_} zNJxFDqAC&h*e#~$JoYz5RhdoE`OKy$gV_{SV>U(AnN3j*W>Zv?*%Z}cHbu3WQB;S3 zqPheW)gz#&J^@7y2qTSd{eIK*%WnUHbvc-O;LAdQ`Cdm6!l~_MZK6&)SG~!J_Ho?C7`Gu0Y&`@ zC>lUO(Le%<1`$v+n1G@o1QZP=py(n3iiQzTG@O8<5d;)nOhC~{0*Wpnpy*NpibfGo zG@5{-T!OEtT_kw10Eza~$D;P8Xpr}YEfP{+s%U(~oqwAtn!x_1Xd<&In#631CNrC& z%a~2k6lPO2mDvU(8nN86QW)xjcK+#MBit-64Dj=X}76C=G2`IXPfTB4B6wM`| zXdVGYR}xS(pMavP2q?OmfT9Hi6fGp6Xb}NL*AP&&n1G@s1QcCMK+#fyuV`E(xKV&a z2kOI5o+;|9KWubeB&5Dn(Tx%J)zzlxCiXW)H#3`}TbNDJt<0uqIkPER!EB0FGMl2? zm`%|tW>d798AWRdD7u}1qO}AR-9bRnodgu!ML^Ly0*dY?plCe-MfVU;w1I%4jRX{J zBB1DA0*dYTn zjfB*fD%uip!)r~^lk9Jbo?U(4Gn=9pm{Ig1 z0Y%#hD0+#2qL&FMdWC?Z9Rw8ZB%tV30*ZDKQ1luBMXwW3w3~pUHwY+tlYpYP2q=1+ zfTDK@D0-KGqW1_WdY^!z4+tpQL+}+n9tk!QAknw=8;wtxqJH`wZEqx`zEsi25x4K1 zrsxy)H%0rIP0^>!rsy+fQ}j8rDf)uh6n)8TioRktMF*Ho(bvo2q^lQfTE)W6#YU#(XRv){YF61F#?K?6Hs)5 zfTEKG6rCcV=rqAs^id?3FF>Mi>rbieGer^oogu$RLh4Hu{S|RntusYu*xwYLWi~~B zGn=Aw%%e%O**kYr6ks+*3CyM_$ZU!dnNj2tP*jS5q7VT^VFHRG1QaC^P?StS zQIvq9(gYNx5Kxp#Kv5b2MKJ=3;sg|xA)u%%0Y&8qC@N1tQ91!d6$mJ*NI+2~g0HAB z5`12OM5pTOqCZX1i~3kpIVq&RRMGiK?&s@GQ3m^)qH4^hs5-MLs=;iEYBHOmTFj=X zHnSz z2q2kDeA^-in=qKq8`kqs3)^2>cwn|dNZ4%KFp@5 zFEfhz5m3~hfT95e6b&SxXb=HKg9#`aLO{__0*WpoplBEYMZ*aw8bLtO#RL?MB%tUL z0*WprplB2UMWYEQ$|ay^3;{)B2`Cyz@D+7T3U(17QT@ zztF;tHbpa;O;J8GiV6rQnngg-Yyyg| zAfRXt0Y!5OD4It=(Uk-g%_pGfDguhGCZK2m0YwW5C|X27(KQ4VEheC72?0gd5>T|1 zfTHUNC|X89(e(sh(S)SnjRGWkS|5HUnxfA7jCMm(NPVfITaw&I?>9xavcD->&TNWS zFq@*4%%d6^*%Ym2HbrZgP0{Vlrf4lQitZqw=uQHP?joRQ9RWpm6Hv6CfTDW{ zDB3_k(MAG_HW5&CF9AjO5m0nL0YwiGQ1l=HMGp~B^e_QMn+Yg-gn*()2`GAufTG6< zzM`9wf_nu>^cwv}-PbLM^9}-20 z`d4R9nIiqm*~EQGA@!w-K2364ZZ<`qvA-$$oY@q8!EB1YWHv=#F`J?T%%a*K z*%W=lY>Eysqv%@#ioPSD=z9W+ejuReFabqB5>WIL0Yyg$DEgUzqN4;9{X#&|uLKnR zMnKUq0*a0kP;`QTqLTy^og$#(kqx zNg?&6ivCV=uYS}NonwDf^bfNsa+2+xyD17Vo1z3}Qxs%2MTyL&$YnM~rI<}oh#5s; z0*WF86eST*luSTTlz^hr1QewZP?SnQQ5pe7F#?L>1QeAapr|YXMdb)6Do;RBIsru$ z2q>yZKv5+EiYgOORE2<|^9a78GfBaF1xWNOeG)rsiq^Pr<>Pj+8>+!WPd ze^XSG*%Z}cHbu3WO;H_YQ&gAP6xCxkMfI6YQ3GaE)Q}lPjR+{pB%mmZfTC;yigE}j zYD_>;69S5w5>V8PfTHFE6ty6rs3ieKtq3S;O+e8F1QfL)pr|bYMHdoK)Q*6n_5>7l zAfTut!B>=#9Q;XuL~H7I9jhh#@AUWUV^OE%koreIQ z*%b9=Hbs4yO;KNFQ`C>y6!m8|MFW^oG?0LzK?D>HCZK2t0YyUzD7uJ%qG1FS4JV*z z1OY`C6HqjgfTBwXD7ut@qEQ4CjV7Qdmw=)%1Qd-WplBQcMR^1ijVGXJ0>M|*B{`TS zK%$xYHy~Y2(T#Fg;>6^T`cg$xlHLAKo1&@gZ;GZdo1*E=rf3GUDY~556wPEdMfuF8 zsDRlN&0;o1vzbwJ1p!5K2q>CMK+!w`imoJ}Xg&c&R}oNjH33Bn2q;=eK+z%simoA` zXfXjrO9&{smVlzA1QcCIK+!S+imoT1=mr9cZX}@SCW5bMa&mB%0EynKe~o{cDLSkV zOgATo)R!t+k?gK{))cK|e^YcDvng7|Y>HMho1!($rs#HNQ?!=Z6y3pWitc1KMRzfy zXdMAXcN0*wo`9lz2q@Y>K+#45iZ&5YbT0u#_YqKZKLJG#5K#0W0YwiHQ1mbXMVkpI zdW3+YM+qo;jDVuY2`GAkfTAq~6g^4s72TQ~d{KZz&*|TQEH_0r=`-3>$szTnik?e$ zzuanywz9t|+Qw{(o@X{iFEE>;7nx1bc4kxb60<3Knb{P*!fc9mFr#QE0Y$G8P_&DH zqSpv0dYyox-2@c9K|s-)1QfkRK+)R-6um=0(Ypi`y+=UN`veqyKtRzR0*dw$Q1l@I zMIRARw2y$Ij|nLHgy1WBCOH_`CW=NXoM%l@8Sf2Sa!7rtqA!x&>Mxk0FWKJ|eZ_2w z4ltXdubEBJL1t6*4YMga#B7SbWj00MF`J_AnNjou0Y!%iDEg6rqMryTIzm9v&jb`5 zC7|dR0*Zbmpy)ROijEObbew>q69g2UB%tUN0Y#??DEgg%qCW^IDkPxjPXdbmBB1CD z!B_NIaXO;HjvijoN^iV{#%nt-Ad0*X=zC`u!sC`Le0oPeS-1QeAepr{-H zMdb-7N++PG0s%!82`H*WKv87^imDJ$bRGdkRS76MpMatag0JXYa`0vW68%NL>-di; zYAlB(R*Qzzmny0ibsvA(6xC*bQ&fl96xC%mMfI3XQGI4p)PUI(HDoqLjhIbQCbKEZ zVn$Im0Yy0k6g4KGs0jf@O$jJ!MnF+>0*YD?P}GuuqE-YHwI-nG0s@NK5Kz>XfT9Zt zC~8MQQF{W4IuKCQk$|F31Qc~9pr{MMS5zY!{78UAE9+xX&8YuQe})cSqapRBih4%f zQ#(viFZMS@y_ro>A7)e3m)R8cV>U(onN86EW>Ykf*%S?8HbsM(Q8a{rqM-y7T|_|9 zFanB(6HqjQfTD{DC>lvX(Io^FT}nXFC<2N`6Ht^(K+zZiipCO9G>(9xJOYZw6HqjP zfTD>66ip(aXfnZ9)IA!kxKk9l`d!B!rf7~FmUvk-q`p+q^r+iYki z*%ak7o1y|{Q#6a&6wPKfMOQGJqB+c_Xf88~<`GbIB>_eA2`IXXfTF7jC|W>3(Lw@> z77Q}mGz%cCLnrHWQX-G#54qSfqgiqeLqO360*W>gP_&7FqI(G_x{rXO`w1v|fPkV02`GAqfTD*9 zDB4Uw(IW&DJxV~)V+0gEPC(HU1Qcx{py){gik>2%=xG9qo+0>(Rz`#O3y|n_`d!D{ zOi^X;4O=v%zEsikQFr$nrsxIsH$^Wpo1*Q^rsySRQ}i;kDSCz36zyO(MLU^I(W}g+ zXcsezUL&CBbpncZ6HxR90Yz^TQ1li7MQ;;O^bP?~D$=GMl1rm`%|kW>fSnvnl$H*%W=xY>IwhHbsY-P0^3cDEf(jq9X(p z{Y*g7Q38s7A)x420*Zbkpy(I@MaKy!Izd3uNdk&a5m0oRfTG_CDEfndqCx_S{v@F2 zF9M3r5KwfMfTF(%C^|>*6@3{E<_M7J1^QjbuT0TweJuJX8d6`XC|KGZ_^v5REd8(V z^j&6CREpUYg_uoInAsFXm`za4MHvJXRU@FNIsrvB z2)?2~>EIOtBzjcgB$W2wqm_}v5^I(YsV`Mjx3s(VeN$AA{q3=+KC>xmz-)>dGMl1C z%%&)l*%W0lo1$!HQ0*YD?P}GuuqE-YHwI-nG0s@NK z5Kz>XfT9ZtC~8MQQF{W4IuKCQk$|F31Qc~9pr{K0MO_If>PA3OcY?2|cIn_t0wh{b z;nXojBkSa(}vniU-jH0UuD7u<} zq6GvLEhM055dlTl5Ky$3fTAS?6kSU|(NY46t|Opm839Gt6Hs&m0Yx_wP;?UkMK=>r zbPEARw-QjaoPeSg1Qe|#_=;wf4)zcr(VqHq*O!~3=k&4Yw$dT>rHXDZ?N0vK6s=`{ zQ*;NjDY}!{6y3#aiqRv>0Y&!{Q1k!+ zMGq2C^bi3>4--(dnSi242q=1#fTG6;D0-ZLq9+I_+Co6llLQn!ML^Nh1Qb0(K+&@V z6g@{k(N==5Xm#n}tpX&vPrvK9#uSD1foWUmkorfSkvnkreY>HlEHbt*9o1)#!D0+i{qBjXBdW(Rfw+SeEhk&AY2`GAxfTH&a zDEfeaqCEr@?Iob-LjsCEBA{p=0Yx7ZQ1l4_Mf(XT`jmj8&j={`oPeS)2q^lJ;46Be zbns&V5*?v`jsK!4>Y#rE@>S`O`cg&Tly-mr%oH7Be^c}=vnl$H*%W=xY>IwhHbsY- zP0^3crsyYTQ*?yc6#dMMqN4;9{X#&|uLKnRMnKUq0*a0kP;`QTqLTy^og$#Y>kQ2`M4b{HY>HBu zO;H*%iedy5#R(`XLqJhk0*cBJP*k3PqI3d^DiBaqk$|E~1Qb;!pr{G~MduMvRF#0D z^9d-*AfTuk0Y%jbD5^m~QB4AhY7tOWo8T)-ObO-+kZ4%pxGDZSeR)EYH*6^(^`(j$ zq`21{Fhvd7-xM`sHbt4trYMWq6lF7;q8w&Z)R@^6HDNYIO_@zmGiDSuC!nYW0Yxnd zC~8GOQELKGxOqv&D+ibfJpbO`}Pml9Akih!cg1Qg{G zP&9^sqOk-NjU%8akAR}_1QbmmplBiiMUx09noK~^WdsyWA)sg~0Y%dYD4I?{(F}sG zsBcQ}7XcETlq7KanWE+Tmui=%gw&TRnw8?Fd~1qkv%e|2g4qa(} zvniU-Y>KX8Hbqx6o1z8GC|XEB(INtht|6dkF#$zO2q?OifTE=Y6kSI^(J}&xt|y@A z1_Fw1B%tUf0*Y=Xpy(C?if$#KXgL8zD+nlBNkGwU1Qe|zplCJ0SCpR;Y$8CSujpe@ zfhlUPuddgmgw&TRx--Qc{Jkld6@*%aN& zY>Mtizy-X zrHWojaqm2AigvKSDcZ?wie6&GXjb} zC!pvH0*byQpy(?CiVhG^^fkd(^ioRj6#){h5)?Quo1#Pd&L5`0C6QiARgQS_3+`PLNeRZ?zhNPVfINUB@=s3}Tfe^ZpqY>J}Hrl>Tt zDN12BMXAiDD2>?^#h6V|oY@qWVMb9|0*cBJP*k3PqI3d^DiBaqk$|E~1Qb;!pr{G~ zMduMvRF#0D^9d-*AfTuk0Y%jbD5^m~QB4AhY7tOWn}DJ^1QgXJpr{_fR}@MO_7Wh` zkM(ar!m0i{{o9pP{nU{9Qbn1m?v!6mQ5O4~qHJbUl*4R_8Z(=sCd{U&DYGeR#%zk3 zGn=9o%%-R%Gm2UfP}G`$q6-KpYC}L#TLOwMB%r7r0Y&WzDC$5!QAYxbIuTIRnSi1$ z1Qc~8pr{)GMcoM~>OnwJPXda15m3~dfTBJG6!j(eiW;T{R|t@3DOJ?S6t&QyUusBw zsiHxt?o-E1(O~vBMMIcP(NJbnbP=;D8pdpjhBKR@5zMCOVrEk`lGzkp!i=Iz2`Cyx zK+$LdigF1k8bd(QSOSX15m1yzK+$*tiY5?HG?9R!Ndy#4CZOmt0*a;(P&Ac*qG<#a zO(&pe1_4Ev6HqjhfTDbYuV_GOaK8YF&eZQ+4>Uy$^s%TQHKe{&(VSGb@PsLv%l@Wl z9d6~*%U2eHbvJkqi8V!MN0@Mx|V>Vr34gRM?lds z0*bCDpy&nyif$yJ=q3V+ZYH4U76OWHC7@_I0YxhaC|XHC(QO12ts_cEKJ`{BB1DD0*W>hQ1l1^MUN6t^cVp}j}uVz1OY`` z2q=1zfTE`eD0-TJqGt#wdX|8q=Ljg;Nd7A*%ZCOY>M7wHbrkS zo1(XwP0>5drs!Q}6un14(fb4xeLz6b9s-K?5>WIZ0Yx7XP_&PLqK^qE`hWIF0Y!%hzM>te!G{G%w5z@?+i8l{ z>0{BisUh{HiVml`Z~tkEeq?`B^b@lwI>KyZv_*%XyyHbv!`QIt+VQ3V2uDiTms ziGZTY1Qb;vpy)gTimDP&bUpz^83YtnBcP}{0YxeIR*%UQrHbpI%O;Jl`Q`Cyt6t!kHMHeums0{%{Z3!s4kbt6g1QfL=pr``@MI8w! z>O??MX99}45Kz>WfTC^$6m=({s0RT>Jqal4ML;moFJ1hXl+nAsGK zWHv>YFq@)FnN86sW>Ykp8AZ7S6pbOEXe(If(jCKFI} z839F82q>CLK+!Y;il!4#G=qSm%Lyo&NkCCP0YwD_6wM-_Xg0xDG&n7|Q-DOj(Z4zy zVv5rBo&FVRA@!w-u1s?eC77c5>~D&$Vm3urGn=9X%%*4|vng7{Y>KX7Hbsk>P0kbR7Xj%LpjCo`9ko2q?OdfTEiSD7u+|qFV?kx|M*URvp0Y!HbP;?i;S2Q;*7z&D_yY(B5^Gs1CeJom+7E)iT zXhWJ?SAHFY_gJ)%{Y}v(W>a)8vnjfd*%aN+Y>FOWHboCIo1%x9P0_>5rf4%WiXI`L z=urZS9wVUWaRQ2-AfRXq0Yy&|Q1lc5MNbn@^b7$-&k|7d905gJ2`Jh|K+*FA6um$| z(TfBWZ6~1UB?5|GCZOmQ0*ZDJd`0Wif_(%?w7Ne0++&Iks-m4~A@!w-UQctUg-p?I z_BTauFq@(`nN87K%%fSIvnhI)*%ZCUY>M7zHboyWqi7ESMSBS-`jCL4j|eE* zM?lfX1QdNjK+%2ziasTv=raO}J}02)3j&J1B%tUk0*Ve0Q1mqcMF$Be`i6j_Lj)9k zOF+?g1QdNw@D=S!3*II`q7(G7=rvRHn7+FHAuXi7RMC+%_nC+(`kDPr(NSho^b4~o z`jy!f{l;vHjxn2}(DG>%C!%h18cSN{zXHC7Yr&_BTZ_W>XYrHbrHaO;K59Q&f)G6qRQ- zMd{3@r~qC@N(2;DCZMPa0Y&E#P*jzGqVowT${?Vq8UaPs2`H*TKv7KsifR#1 zRGWaJIs_EeC7`Gt0Y&u*C~81JQ9}ZX8WB*GNkCB+!BHYio1&J?rl=LODQeAZiY{O_MQxZ(QCntHbRjc} z+7VFHo`9kb1Qc~7pr{i8MV$#K>Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq z0*d+(P}HA*q5%XH4J4pw5CKJl3BIDnv0$D6iMG)9XiZGfgZj3ANGznjRMGI5yEM%d zjbMLMbTP9j8p&*mE@3uBmol58QOu@jG_xtnWi~})m`%}GW)zJhpeT=kqVWV2O(39X zA^}B{2q>CNK+$Cc6ip$ZXet3k(+DVd6?*%V#F zY>E~$o1!Jmrs!H`Q?!)X6kW$`ik2~>=z0Q*ZXlrOMgod%BB1DI0*Y=Spy*Ztik1^l zw1R-5l>`*sMnKUj0*Y1>P_%}CqT2~5T1!CD9Rw8JNkGwE1Qe|!py+M_iq;c+Me}39 z;{qi5ls^1iWr|YuJ=#67korfSKvnhI**%WPN zHbsvxo1#aVP0?e_D0-ZLq9+I_+Co6llLQn!ML^Nh1Qb0(K+&@V6g@{k(N+SAwh>VD zJOM>75K#0Y0Y%#hD0+#2qL&FMdWC?Z9Rw8ZB%tV30*ZDKd_@~$!4?7}I#qvqf0HSy zs*gpl#X{;!6}=gAhozgMx7gnlz0GWj-eERH?=qXB_n1x5`^={317=gShuIYEWi~}0 zGNb4t0*dw#Q1meYMV}B*w4Z>YPYEdcjDVug2`Ku4fTAx6DEf+kq5}jJeN8~oK>~`t zA)x3G0Y%>uQ1l%EMc)%p^aBA!hY2Y9k>D%Z9SdG1K%$NG9}m4@ivE(r5`T(?)R!vy zCFZWLXo`Mie^c}uvne{pY>JLEo1zoUrsyQIDLTb$icT||qTiWK(I3nxDkPxjPXdbm zBB1CD0YzsCDEga#qH_ck{X;;J6SueRC<+izlt4gHkbt5@0*YJ$ib@es6e6G~Oh8eD zfTAPCC360<$Tq$ZU!#F`J^w%%-RcGm6e5pr|SVMduSxltDmIH3EvN6Hrux zfTEfN6xAZ2s5SvbbqFY`OF&UQ0*dMrP}G2cqJ{(%H6oxWlYpWu0*bN;D9RzAs4>A; zlok(0s)(X5^hqoh_uuK?DtHo`#6#*!6}5=F^{bkqmh5keS}~iV*372p0%lXxhS?Og zWi~|@GMl1y%%-S4vnlGpjG~SN6m=q?s51dYT?i=ZNlyY(M1GbQL}ikp8$zAP&my^ z(F%Pm8WsPaafTHOH6wM%@=yC#zW)e`8Pe4%t0Y$S2 zD4I<`(G>&~%^{#@E&)aJ2q?OefTH;XU(twoaJ2x59?*CC7n`DY_37=Zcu0MzqD67{ zx$36q8um9uiU(0m`&03%%a({Gm35^py*}-if$pG z=vD%XmJ?94f`Fox1QgvyK+!4!idGX)w1$A9+X*OIOF+>b1Qgv#K+#44*^9R2q@Y}@D(kH2fq*?(H~??Txg1Z(_vFQq`sUqCn2#$q;~Cq6MIVj%GQbP zQ*g20<+}mlScQoEY*MVX{3TpkY-DN2DI436>Npi*Kg1lTN~~d7$H|DzEbllqW7{e? zPTknKN{-Vo*7-cg$&TG{zT-5F?WyKCEo0?tI!>F|$l8w6KDMc@<8+SwSl@BF$1)o^ zPVZPjmgDq~y^!NLgJVup#~Bvu+T3wQ#%^lqIHO}9wsxFxu?lS+XJYKqc8)V8c3%g_ znGrkE$#Du|*Ry|#c{UBs!VsB9kDT&JI-sdhw>fg&DgKA9OvCwQ~573_QdARbDVv#9rGRM(^#nm zj`L-#_aetR7+bm6alVUvdadL97^}L>agN5u-QYOKVw-ProKvx5w>VB=toaJZIUApU zo810^_^Yes4hY1;Eg%I}q3Z7^Z(9uK%;g;6PmeYldNgxc+Yak%74Wa`e%Gxc+wQ zae=u0dg6(Jxc+|GDS^2Dg3uX(xc-L6f)asA%=mw~u`^YmaKuHXIoE)dsmU;G$|>-*26fw;bb zI2MTOE5K8MxITp!2IBe{d^X^esioiBzt8`YE4xU(jsi{O%Si5E`N9gU8&)sil#3^6 zZKK=O^&t5u_pIy|XfjytFh}3-9@q7)ptPnJY>@4;viAw;jYYO%}MXBM`&ro4|)o%QWnb*ob&_oB^+pNhrB5lDsX`fzv(`0Z1`P=wl)lu^9)?b zA#!Gcb~c>TE79Ht`C@Sb9sHp}d)enwxo#Ev%f@B0F|JO)sTAn%MiX;;jjj|JP%5_V zn^Ql`s}vaMM$;>Vaw-J|xv|wx?(OGP9w)oZkzLlX%eaBJ#AO#ZdUea6hI@NdSbunw z?h);%oeqfGwE+?-!e2Z+!xl~?vq3iAQck1{&r@{kV!sqM~ zM(TQ(uvBdMuS@Tp>+SsBzAvu3T6QiKyMF2JTjgX1m5Tkk_x%?aIF;YFv%JvX%Z=W= zvUO{3r*j*Qem~#a>Df&X7z zU6@(_O1Zz}vR<)2@lxG4_Ub2xx_kQ`KJ(O%^PDPOWf#2*<>;kiA1*p|x7;9dm;db&Nz~Ne-q|P8pIO3#6qxPC`v5Ir&0KjuR~J1XEfkUy$4?xknlKIOR3u4 z5=xa_bPksZBq#ej1Z0eqc7kE{PfjkK98GR1Uo}bT|8lHkIaY~tiQ4G;XIk1$Qbs+= z6gx@p(BhL!wUe}CrO8fi@#Tn>mW!$99QQWl%9pWgW@l11GtjOg7otwZSRh`ieTCaQ zR@8GW=a#s53F%uq%57A>>3?nMC0i9avkKQ=Bd-7gIdU2mWm9hI)g3G5l+n|ybb}m} zP+>*K3XW6RKg>U%3WMB*nNGWkZ7NPn@h+EKP`O+G-#+@v(E?6?UE~Q=HV5l6-`gCi zi$0PhIwu4D@6oLh@<)!Yi(D!_x-K{QRhLbE)kVL;{XKPShj&1KT|V(P2kW9=k^XUX z>y&pue_fJ-fG(ZAGaRZ5*K>e(J%@P* z4A8~Do~fy$%EJ(Jg&C2{;3EiF;RP zs4n_o;U7o0YWoN1!VNIs9^Go~9WX!_{|1m3R{xt1|LPCa^rJ=!Mk_q}zI-^o(^|Z)H6n-Il$)k1Fz6l6=VP3j5IGl>8_;hvi8==;Z3D1kT6< zQ9wTAxbi2EnVB^+H*0+UjI8{bW3y(C${(9IYR1gz1$ko&^2TM2ojG?#!E_B{^Ty4Z znU`PUFg?B;yH(bVnUkhYDws4o&&irNeQI7-?v%VaS(#I&kIkKul|M0eW?t6JylHv) zx%pXnjYs7d%o;aodRD>o=~Ko|%$+nXKWoC+v7>TlPR+{69@S)2zA z+Vp98jq-BGOlp*qo!O+39-Ju$|I0yHlctTGGHYC3*3{gw6DLjk|NUa*&&@A+OH7!U z)nVqiS(Bzs?=*d8UZbMhVot$K?MvcoGpF3+x!Ki|{GxG8?Cn_(wuf|Q9 zRv?4CdK}cL%P6^wV>?ZsI(7OqX(A6Tlk{}`md*_|S8g8<# zsjk=MRJ}3NbxSpNGh}pYx@D@!l;xJusZ`tlvX;{vaMRkjwQ9H#JJD4CL~D6t!1cyV zHzFrmQ;wUin_2(UX14BJ&fhoHty%JwhVe{C7%KCh-zmN!+))LXxrZU6gb6*+!5L+?M*W<{={MWVKf8JNmY?sr< zJGYpg+jKd%C;q#0(>?au9#P$+K=#=FKkf0Fzehzm{@lz`llA<{x{-#Zf-nAednOE( zNB)6bx{d0Z-QCeOr)75cQDgkg=1q$>n{_JMY~Iq2*|a6C13PCo^$+XP$&QmFN1oJs z`t%t&PM;3LMs?~txUqlQo!O;X(fPF?H7P#d#zp7bsl-Xz1#HX?&5MrJ%DYUnrsYqX zFfDIfhCEhzXV=LtS58+>MK-vaU5c(pj$9b;_^sqzAQ-P_|u2`Kqw%+Og({?`qz*;9=X8cv6FaQPnqEEsQKRUja*8>_ z4}CeszU6kZv-Zr5($^9l^70!uYu;s=_X@Lfp0^B{F-~4c44UOXA{7agha>-di$Ujz zXuoB1V6pL>t^g^fjTyP3{(fvI4)01CFz>>RpEYf4PIk6;fPHP2=sErlImI_)33n~* z^swQR)^liCd>hL>;Gafg&b`=VPBF@y5-R0xwX-d{F}d?{I@*oFUDvAUC~~LREnobo z$^F`_`11H>yqlqzNlpnTC44lO3sU^$!DFu6TK?tJgY|@DwR6squNW_JKgwgA9n_@g zCX^e3qZe!8PUb!?x?fw$?KizhxS+Cqc}CJlFH5oyC)^SN| zo9#fkxn-+c-ys>DTD8j1x1yOj8Tw{4yJh318FgpoP07p6&#RZwXzJJ*v)Yc8TP$x* zqp3}rNGO;%Yw8$T$4{A_ThK_}$+nfdWt;{%=J*-2n>EUx(P&&wb1Atq$4+c3Z*6C{ zY&11%*4$ZIquZ`y={iEXnb z`LBW+>AfzKK76kq%XnxbsbdnIv|Hvvc<1Ti(iZuzZR8OwRRKe4z^ijn%A+#FELBJ!sKOa@ykiR zIP?{!clBWGzm)W@xxRk2m$cqB^uGd&t~FnAMXq73uVXJOdQ{})YVixn;@6Qm#SfWS zR|wv@^V&71=%r}UtIiT%RK;H!#jhFVLCiae;#Z7C_o4r?)9Kc!Q|pYn`eoE%=G2TX zQ^(|u8z(Q^2lLG!?<K)Dn}PzMgyWN6?YKFDUU5bmAo@J$^YyerUkE)_R}CvLEMH{)(lH{t4 z*0r4Dth80XajSi|&HBw-o&T~~zk#c>e*aw8j=IYJz2)$#a>bvr^#@xk$>G{FZPj}# zL4W2#SGlA0*40%`!dolqDhF26RqmR)*43yUPkwB|Tjhr(ytSjP{cY86TkG-UyMf+1 z+1AT#l^K4)tSxvg~WZ0l9!{rLu4cgbH->EU~9ja2sM^0xMqpG?ui zN7}mje1G0#>lbpv>ft}yTCJu(XWBZUwm%ox`k34Sdi)n`Jz3wMod*8es*%5TwRM5q zQF{EFY<)e)pFgxUxv4)_uyugkp?dsFZM|K-SaiP6)~{Oo^ATHX$Q`eTXWKfdoj=dE z^@$GtyxrE*o%}hWv%g*-UwpcMcUu>A_vc$|eWRy8@3XaZAAhc7>!5!AJlfVf2Ke&> zwthXxpO4yFYp6drw)L`M{yfLlCr9}6%eMY8(w`GA@z=Ja{I#d8i*x;Xxvg&rbiF>G z*qS=tpR3q9WTHQhvGp$bg3#kXWa~Fm{P|Z~>rD6OrnXMK+@I&!`gFcO@38gHS^ivV zw!gNU^~Iue9|Y`3oaG|4(g=E%4{6wqCTzpU2sH_hNtEZ0onz`tvbc>n-!= z=C)41!Jp^b`s_{q{Hm>IZt>^vt^V3!g}?T-^}5^qd6lj2t@h{7Z7s9bpEGP7ey2Z= zxAmTN{`{z|->>)Q6Sg+k=+7-}z5HH(zS`EU_xtl}w*LK~KPNrpubnpgYkym>f7GAX z*!sca{`{q_<(~BC>b73|v_DU@b>p-C{J5=$xBBxbTN}OL&#i6E-|o)~ZGHY_f8K5D zKRf(6y3=2~?DE%vw%+)rZ?9`FC5h zKJw=_w$A$4pRcj?#r^*Lrmca`{W-d#ATed(A#zin&qq(7(G+T*l854H8yKm2)} ztsl#ejp^6hAzLe-_2;^_=AQHCX|_HnuUz!_&)E7)fEywuiL zBL4iYt*-pLZ#{n8)?V^+XgUwGbw!##ueWu7+@HU*^*s4`F+F~LTgS@Js_8t#)`#VX z)^vW(*5Bl(*K|H>YqP5U+|kx6GyHj(tvjpx^ZT~esqN2AZM{HO*KvBwrOs{vUtyOHT zr>k84#6EaJ$^e|yW2Y7)-AR^Z|hN8Pup5oel|+?AEm2Yp0T!0 zv2}*6b8WrK*6RBDOZKa6tGt}><{VpF+S=PdYP@>&oIdO z$lXtj0 z40)?Oym;#&TlL2z_4d$zlB26|_12oU>OZ~Eo@Hw*Tie>IKX0Rlcek~lt%GdUA1~6w zFSRw#)=9SJ+j@nqSKE4xt=HRnv#qz=dY7%6Y<<91{mn*teoxx^qOGsky4%*bZPou8 zTaW*#tzX;vt*!baqk4D+ThF((hOPB&)%P8GycV`zU~3m!d)V6FR(+qT$G_OtQMQh^ zb+WCO+d9kE1-34>^#)sSv30erci4KbtqNKoBT<@R0EZ+Ic+azzD zVdpPzW1NIkxu2{%nfY_47UYhRwP2>dPGn2Iy;$I6>i6@U%rW`-PNsYZGE-xw|L*m_ zfA{Mhdz}8YoBXZk_~~*&-gfSoF*EaK`={j>`5B&)WA4n{X%q77-27ww*D^(a0>@5K zF0PX~R(@h6PyTAQ#JP^2nLAaE)L~$s%-n*4nUluMDv*=?Uwp`0I7fIFeMdvyBK^yU z+@#(|HTkT^le@zE`1j-KVfs-={>WYQKOQezj`Q#5Tk;33^gh*(hVn<=<~r@=kA76? z7I5asT3-I>arBR#-=*@0%OIOhL%E?VPVZ2XNZ5={%7Wa58km zJ~-?;nMq1X2S^jW(>t&mLWYhUTPEWsn_~0;ojwyM1Q%am(X*rD3+alZS zqo?t;oL*FKIQ!tRM`bQ~dh_M<^nTLICtsRHr?*|UbszPhA3wJUI9EpfZT+l=>7O@j z<#^-e$)=|?J~-Y!3A)Y47CGJ&23hrb=*J%UQ}XgHDRF(v$YEUHZ)98UrWvw$A62>p zoYoAoa$dUfwW0?PljDt+m@eD;-8wzJH2I_FS%QbNt!uy;BaIJEFD9Yn@m9&@JI;}0 z<#_z~S(D7^S@I(|896Poo43qv+_G^?+0M?+De<{^^QIXYty(p1DhJ8O=%fW*dUy4I ze$hYSfPCkR)7A3k0&jBtul2f4MR`PR^iyHK`+9v;xIMT0vGc?2kIlcPY}YO)0*!YS zF3Ff!J=C>y*Ik9-MY{?UtF7y~tMFjPN3!MAKlAyp>a8ZO>AS1YiRoc$yu&^zOw4f_ zocVlE#y@|Y`)5hl6}?vWT-oEc?z;<}om%uyuM-D5?Jhi;om4|V50lS{IZJzeU6{6V zcj3Y8&;IQcuI+Vg&!s(7s}Hw0BsK$(cywnu#q~v}*#1OnjpWho zq^&J#a-F2bYrHe2tL(EUySsO8&5O?M%feOJ(c@`RJ-09A+*Wn*xBT<_vd}-j!+Y!X zEHm*AJJpYJ+n*TII^`{e=}` z{#wP>3~#O7L-tB5GrGydT_@X5xGV6NciU9!c`~HScleu!cUw(3u zydpZ@d(nBls`jkf<9zSXv}zrGpD;6_*KxU*600>k=%kfzf6xgm+z<>beEXtueYUmw z85NB*IN)Bd_;2NSMcc2Kkj z7H+-nnA0V?+^ODU&zbG{?=M-`r_pDtmOQln(|=a}^7`i1+pfRh_~u$auj-EJ`V+hU zz9%5}aka@4_48)$^AYcJ{YhT;K5zCuAMrldpX_z-^Jee!5$|*T%e?M=-t2uo;(e|^ z#p~YZ&EDrD-sk#Lz3zS9?0r7seXc*v>)z+h-sdCU=lavV?tR|ueLmuS9^P~Km_d{8 zPB^xKjd}#Jro?$eQ=L8xvR&%T6oYYGrCw+-@fnUK0Rr;yX)k_>VNI))9b0+ zK0W&M?Caeh8P(gLSlpy*pA%#9M_)E^gmd=ekL4EW-mCg(UAy%dr0Z}Qed-skGM zde|86^Cs`}A@6hbF<$pRZ}L7L@;+A|>viw*Chzkh?{oEWUiUt4@;)E(K3C84y7zgL z_xX_bx%zmod!ILXpAUJTt55K{_j!}|`Ot()J=J3S8mT>BFWjDU+oUfN&+cpA^`##R zZxUD$r1e;oBG#un{azwzBahmBoZ>4yiZ zAH47DDeXsQmhX@@;&89uYMt!5cVYYMe?EG)VDpMK+pk*lX1j~eG>VJVr{xWo|GbqL z=pfIH(dtzlXQw`smiR~rlv*NBunB?iB6*HUNO12jr%ULLYVt&qR$aFHRFLl{%g>Rz zx5@K$aKAh&CG@K}+DoC-N-~ArUo?h8SIFOpBqqB0_oE4kp-OT>LH#?KV8b#U|oh;Z@pKJ|a(k`r2Lg438)) z#|iJ0$qj!bPjaQgLAl7G@KQOCaCo`&NO+qZKPfy+P9Zsbi@cDJhFfOHKh6%nC9l;| z!b{}_NDc2fPo7i5AImXg;Rmb8^K7`2T-h?=jdGl_;UDE?OS$kba?JAKOXX#5dRTtK z*QpTRBv-X!c!b=1mBJmQR}Qz4C+R9-{acHw;aYMT&JW)!hh~K5$T?OEuatAC9{xv8 ztw#6(IcCjpfqajlR(Oq^+PH8#xn=XhRcp$#W%#h1+FRkna+%)_%Rd=%-U-i@r}1~g z4dnX17v3btd_VHK+!_r7k&k97g$|cJVL~fL2c_1P`7VNAD zL~6=Kxh)V`A~)!&K;#j*xmE`vAIh{Q5P4c|w%Y@dEpjSr1CdYV%HI))441?1l-=bb z-4%#r%C$Nbh*XjbdpZ!QEsTB-L|&A0|058oD?1bhBCp8>8S7e-1{@$aFLq*(kTmFTuzNxiNkXMjnt`j9jr}!AMZf z;dn68LC&^!Vx)(hZJ)$Q3%S&N6C+nUj?*tO(n?OOe`4gU9A!XaWWSu>z{JRDSq3FW zYRNeamj4h|b{LWv86;4LCPsG1eS1-2q^nBzwJ$gMQjjZ~1kbDkS{P~w+viiQY&WDv?iNKGQzQD9aGO#izsN5(7A=hd>G?7kp9GEZ*Eh3S!N$&Hk+8}G{{EYOWI!f=*u=(kH|>qbvGm4$MbCfz4TUZfk<cQdT!s%T+F?8>i&F^in4^ zkh?&>FY6=?mJ6St8z0E6sy~yFG(oG-}x1NpuFYs{d+vxxP4!41g{;%(F8`|jq_71m^js7q1a5HW6e|LwQWuyPAJKSs= z?KgM0IX2rb?rEI^6${syhL* zdhY)}eom+FoR(>tlbWeiLWsL;ktC#K%^s3u35AfQY)J@3ls$xyJ$q!y9+G|ELiT;% z_uu!^c|WfI^}nyH>+*Vbf5yo?nmPOQj~(ySk!=<`-l!uR5If$dBO4ey-liklJa)WG zM>Z&Syh%s4MeO|Z-@0kmtu!S6{MV1l`DCjsd(Wx*J@UWS*_P#X^S}5>$hO&#oYXQQ zgX3rj*)C=X**<0n*&${K*)e7a*(qiS**Rti*(GKO84@#u>>87h-C`56du&36#wKKs z*n|v=O~{_H2^k)nkiB9PG9or1d&eeZpV)-#8=H{*ViPhlHX-}RCggzFgd7-~kWsM- z86BIDgJKhMaBM;jiCq=4b!mM5`L7?Af5pnSsS5c!2^mvPa*~j-+4!8#G9gFA(GYTE z%n))^%n)*P%n&jzW(XM{GlU!yGlU!)GlU!$GlU!;laLc)6EYz-At%NrWMXVWPKr&) zq}YU<9Gj3+ViR&|Y(gf-Cgil(gq$9mkTYTvG9@-4Q)3fyW^6*vicQG0*o2%Nn~-y2 z6EZzEAv0oEg&bCznScK4$K_YWvcs!Fvi#~!c5XSzNkT5nX6D~+mkGHjj)stnV}_8K zF+<2DF+<3uF+<2@F+<3#m?7lym?7kfm?7lKn1sxZO~_TT3As8pA=ktvWKL{Cu8mE| zb+HM#J~kmY#3tm%*o52^n~SB0EkxPCS-AJLY|3D z$g{Btc`h~~&&MX@h1i6=7@LrnViWRmY(id%O~|XU33)9xA+N_KK9A-~2ZwlA^$q!rpzOV6LMmO-KNpJSM5oZEY1TA@N9Uw~&?X&iU?@-^FHk%J+JOthv2>zSl2gE$oi@?p?@Q+8y$}K_P!KReb#R`R-H5 zTG@^H-ms9>*$w$#C%=HLg?1_Am#|)Fn?imOE5dRqGKKt-b`)BqkYCc}h2|;bm$Z}6 zEQS1%b{5JhBD+~Gi zp$+JjU(#+u4y0|;8$qq$3+o5O|I}{DE zL(#5wDB8^qMZ4RfXsAum9s)(f1d8?)C>kzMw3k592!W!#1&a0&DB4$`Xg`6Xkpe~g z3ltq7P;{U`(I|nU(E>#W2^1YHP;`hu(HMcELj{Ts6RL^^7fUbYKq_nH_s(V8g`#cp zuR+=2#d7kM6dhH}e$4NCT&Cz~=R?srI~0w#L(wsIC_2^-MaS8p=y*F6onVKe33ezt z(WYpkK+#D8MUw=IP8KLSMWE)(p$__ja9f z7bvz7;6?PN3*}fubJ-ihdL*`bnVZXMv($1d4tYDEdvH=y!plKLm>Y z6e#*jpy+RbqJIR6{uLfmHs7;5 zkhGw7EdhAc3MS1d6s4DB4P(XlsF@Z3K$86(|}kR28k! zq%i=Id*+H}rF$L6g`&Rc3)96-%E?z!bXk*ZrL{uQ zEayYf<#s5#!VX1O+M#H+9g429L($cCD7wZDMRV*>bgfO%bpl1#3l!ZTP;{d}(M+T*(oobne`?Ty9f}s)6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_I zK+$UgMXw7Ky&+Kara;kK0!42N6ul!*v_zojU4f$a1d84lC|W916+P6XbaoD;@?`#G z-0a~{v}t~=I{TnWIr&P8K53HO+A9=&>U=2r%nn7L+o9+SI~09shoZ0SQ1rDOioUT! z(YJOe`p%~4dx4@K1d4tXDEdjD=x2eVUj&MN6)5^mpy+pjqCW(R{uC(sOQ7g)fuer| zivATS`cI&!P>P%F6cq)Eng|q?1d5sp6lFqH(ML^6ujD`~f2T)4J`P2f=MQ&eHKlU$ zl@zroWk0VUids4!ifZjp)XEM;b#^FfZHJC|XsZXf=VN z?gB-t3lyy(R24NVl{)m!6?IHE?wgmYxAbe9mi?w6{RfJ_1Gi3KZ=pP&87YXn%pC0|bf=6et=cP&8Vg=pccjg9VBX5hxlX zP;{t3(P08bhYJ*q6(~AFpy)_}qN4V_V zI`-)~9f~H}q39$#6iu>2(aClwI>in}r`i-v7AQJRpy+gg zqB8`FrU(>G6(~AWpy(`tqGie}rP=qfuD zU2TV=YwS=o#|}l;+M(z=I}}}ShoT#7if$Arx=EnuW`Ux)0!6n76x}LNbellY?E*!2 z2o&8ZP;{3-(L8~oy9J8w5h$83P;{?A(R~6%_X`v~AW*bGpy)w?qKAa4qFJTVIysQa zy!2@7<)P@H{88BK;ZiyIN{SvYWjk*ciWWK_ik`4T(UW#4dddz(i|kPJv>l2T+o9+g zI}|-@hoa|fik=rJdO@J*MS-H11d3i3D0)Sp=v9HD*93}Q7bto|py*A3qPGN!-WDi& zN1$klK+(GbMehj|y)RI-RG{bsfuauuiarvmiXJVMj>&;kdZj1HJ{F2P=g&^dJ}#A$ zucYYnQZ{p7DEh+rQ1qo8ioUW#(bsk;`o<1L-`b(*J3AD8Z-=5E>`?ThP0>#RML!D^ z{UT8Gt3c6j0!6Y zfuc;Hs79cuEKt-;s4DujRC+K6QW=?^U-Vfhnw}m3Y2LJ)d?iKsYdqc?6pHGc4@Ir* zP*iV+qKX}g+Ss9JIXe`!wL?)mI}|n8p{UWOsJ%c@2Z5rF0!7OU6m=3P>MT&yMWAQ} zfugPgMJoyvtt3#ivOrNcfudCeidGdUT1}v+yFk(E0!3>G6#Y-2sE0sNPob))Wz$k= zi(Jv=`74w2pXpt_rGH9#UFw=m%gI+#v~K>I=B+|eFXuzidUhyU-ws8+?NGFV9g6zc zp=d)p6!o=3(MEPC>St55u|Ux#0!5n&6!jM<+DxEmfI!hefuhX?iUtW3Z6Q#!r9jbE z0!3R36m26=w5>qVV1c6T1d6s7DB3}wXh(sfodk+@7OINYZd%$p2U0mI-O^tt6n&LH zQ#RYBX*u~yigs_B9lT8_8tQx~+QSY-!|YJBryYuh+o5PLI~0wuL($%LDB8ykMf=(m z?I%z)QlMymfuaKhiVhSg8YNIPTA=74fue&2iVhJd8Y572s6f$S0!4=l6pa-qIzpi6 zNP(iG1d5IpC>keFG+ve!~`!btsRQ4vqRDK zb||{R4n;TGq39+%6y0o7G*_VL7J;H$1&VGHD7sys=njFRI|YjF5-6G{P;|FI(LDl1 z^973T6)3t-py+;qq6Y+u76=qQC{Xl}K+(ejMUMy+Jt|ZcUD>p>{0_OIcCB+bvqMqq z^o-fZnwFEVr0B_}S-+h^(NoTcqD6KndfE;}i|tVKj2()ewL{T!b|`w@4n;56q3A`M zqL&1UUKS{NMWERM`{qC@Po=9uPlTc#wfXq0X*u~yioR-^ow7?P z`r7$W^o<>gzO_TqcXlZH-VQ}S*rDi0I~4t7hoYbDQ1pvU(XRqUzX=rmE>QG`K+&H9 zMSlqt{Vh=Rk3iAC0!9A`6y-0=zAXO_+%$hyPX5Z~{B_Gkfube?MJ0ivrUFHoKv9iA zQCXmXxC6waXu8a zu|v^vb|`9VhoW|NC~B}nQKKD-+S{S1gB^-G+7vA>P}E7FsIx#(7lEP`1d6%}6s;&w zw30y4$^u2*1d3J>C|XsZXf=VN?gB-t3lyy(Q1m~6q8-5C5)>-wI{`={U>~*qo@|6^=pJjDJLs4(%L(v9yDC%Q}q7Cg()YlG0 z8`+_#pB;)ewnNb-b|~7^rl`L_(Pjcg0|bf&3KVTFP&7!OXbXX&Ed`3U5-8eQplBO` zqHP6=1`8BzCs4G#K+z5YMLP-xH5t z)161VW#!~6DH@h#LxzQ-J)I9l!|hPCmmP{m*r8}|I~46>hoXJ$P_&;NibmR@Xn&ic z0|bf=6et=cP&8Vg=pccjg9VBX5hxlXP;{t3(P08bhYJ*q6(~AFpy)_}qN4nw5^rfmGH`&%53u6pcvlUUfoNPQH?&ld|m6;h|`f z^P%WuI~1K_hoV#MP&C;NMW@-J=yW?2oneQfDRwBDYEyKkK+#zOMbiX|&K4*-N1$lB zK+z0=qH_g`&J!p)U!dp$fuaiqiY^i;x>%rSra;jp0!5b!6kR4zG)ti9a)F{N1d6T{ zs)|m`N)P8iDxK5wt|x|~CY5~5&dSMGQZy&amW~KT*E%1HuCqhY^>!$_!45??+M(zs zI~3h)hoZT5D7wWCMYq}%-6l|UyFk$$0!4QU6x}6IG*6)DZh@kE1d8Sh6x}OObe}-c z{Q^Y~2ox<4D0)z!=plikhXslr5h!|8py)AyqQ?b_77A5GS7)Vc?_AO7^yTN8P}C(o z0`f#wPQH?&r?YI;eM8Y==R?smb|`w*4n@z|q3C%#6un@Fq8IH@^pYKlUbaKgD>g;1 z3KYF2Q1rS$(HjCqZweH>B~bLXK+!t_MN0&V-W4c%PoU_1fuf}XMIQ(heJD`$kwDSM z0!5z)6n!dC^qD}>=K@7v2vtQ-Wu*vhN7ZCQ4@ipl0Z>Yfuc;Hs79cuEKt-;ps2Y(Q44{hmI6h!0!6I^it2=_ zqOY^kxjB%^bLsBtZ$i5Ma$cvsFNLvI@=U=5hz+gps1@r(TV~^D+v^>EKt-N_( zK+zfkMgJ2h>LF0nQ=n)~fugkpiq;k=T1TL0U4f!rLRC?vru0S*q_R!d98Q~>>Mi~K z(s#7=YRbu1Qq-p=`+Za>+R*t>)YlG08`+_#pB;)ewnNb-b|~7^4n_U#P_&sHiU!ye z4HPKaT%c%>K+zTgMOz9KZ6#2&wLsA}0!7;j6b%+A+D@Qodx4@I1d4VPDB4M&XlH?< zT?C4T2o&uqP_&ys(e468LxrlM-ZiDpqjN>ir*C2#grYCgU66a!l#{QdXs?=VlY>Li z2$LBL#|%5-2)aplF;x(RhKPV+4wh6(~ARpy+skq7wv)CI}Rr zC{z{gSyLLB1F0-dkE0C_MRn;ZYZGhA$yZWzN=-I-Oei|l`A{_34n?Qgq3Cow6rEv* zqA7MLnrerlGwo1xmK}AM_AWonkgxh@oSOiwmiR8vmAlA>p8vic)J z(R0p+qUY^U^nx9VUbI8eOLi!F*$zdo*rDiEI~2WUhoaYQirx??dQ+h2ErFu91&ZDg zC|V*=^sYeBdjdu83luFCDEdI4=tF^`j|7T77AX2epy*S9qR#}1J{KtZLZIkNfugSj zioO=AiWb+D*3W@drl-fzo(V;hOZoVwrks2wML*PJyB!sZesn$*{bYxtpY2feiyex7 zwL{Twb}0JY4n=?1q3BOL6#ZpW^tV9KKLSPn3Kab(P*f<#&31~40!2*(ib?`SO$CZF zfub6LqOw3yGl8P!0!1wZidqU3)e01~5-6$@C~7TGR4-6e5vq#5t0|q31F7tszqNJt zeJDCMy~MFixtx3@MGfU_*0@mA=zJ(@Z-=4|b|~s-hoa@}P}Io|MV;+X)Wr@(E7+l^ zt4-000!1qc6s;^!)J>ph6@j8v1&US^DC#ayw7Nji8UjWC6DaB-P}EbPXib5lwFHXR z7ARUrplDrzqFw?;>j@OCFHqE5s48k(E=XWVuzwl?NHR;4n>>Up=f{|iU!)DXmdLh4YDcPLZE0%fugMhinbOg z+D4#gTY;j%0!7;i6m2h1w1Ys=jsitH2^8%tP_&Cc(GY>6T?LAE6DZnUplGN-(H;Ut z!vu=<6sn3gESJj1=8CfPwWx0>nwJy}FPD?Aq-dXV*8TWUw6F7_Xg@m?jkH72{&pxj zzz#(R+M#Ha9g0TVq39qx6di0+bcjIF7=fZg1&R(6C^}rAXskfd5duX=3KShBP;|6F z(Kvyk@d8E12oxPFP;{I?(eVOBCkPZx5GXoPplG5%(MbYDlZ2|G5#`c$IgrZj>2b8Z zL(xNB^Ko*yoO~rkr`?Tk9g5zvDSBI==pBKgB?3k73KYF3Q1re)(Nck;4+M%n z6e#*gpy*?PqE7^hJ{2hXOrYp>*m`*Jz?N{W6iXZ=qNMZY*7ihi|2(QkGr`rQsif7qeuPdgO-Wrw1_ z?NIcO9g6<7Df&;KsL(8Kwo_CTC~6{5R1zp^Do~UO6x9e6l?95L2^2LKC~6^4)KZ|R zR-mYrKvA7QQEP#sdV!*fKv5fkqU8jN+6q-gKbA`e8FLFj?RaoNXosRvb|@NchoXb*P;{^z ziVm?u(HJ`v9coi_m_X6t0!3p5ijEK{I#QtMD1oA*1&YQA6pa@sI!2)ASb?JB1d5Iq zC^|u)Xo5h|i2_9v1&U4*D4HZtbh1FvDFQ{O3ROk>HY;tA1E~y1SB3TqMT?T6$<4~i zS5h>kSvGW9D4ObgC_2*)MQ7QeXqp|0&bC9*Id&+TZik{7b|^a64n^nL6rC?nbb&z8 zg#twv2^3u{P&8AZ=n{dVO9hH96DXP`P;|LK(G>zkR|*u(7AU$(py+CWqH6?-<_HvB zD^PTuK+*LAMK=glMW;6_otOiuRJ!DF&Im=%r7KA{HY+DzNzpCMvMbIBMYlR1if*$* z(d~99y2B1dciN%oE;|&>vqRC{b||{X4n^~AitZICx=*0!eu1I~1d0|26g?jT`B}Fec%RZhFie7O(6uoMPqSx$D^tv62-mpW_n|3IA z%ML|v+o9+kI}|OkDSB6+=skg=_XUcU3KV@HQ1qcd(MJMB9}5(HB2e_HK+$IcMV|{4 zeIZcvr9jbF0!3d76n!I5^sPYAcLGJ<3l#kzQ1qivRrF%BQuA|jMLpBKjxU9xZ_`uO zeri@uzLKKfnq_O8ABui=J{0|7hoV32Q1q7_ivG4k(LZ)5`qvIc|Jk9a&^&IphoYiQ zQ4@ipl0Z>Yfuc;Hs79cuEKt-;ps2Y(Q44{hmI6h!0!6I^is}T4S_>4_3lvoZirNSi zEhkXaR-mYzKv9E0QKL{*^h>kS4mps@jIKGHUqjJx>EV#}&CAJGQq-w=Hul0$)YG6#Y-2sE0sN zPl2K}1&Y=ZC|X;fXdQu~bp?ug2^6g-P_({4QE!2w4Frn%2o!B7P}EnTXd{85enM4I z$L6IAb0C$5^mhBpH?Q8(Kd6$AjhmN~ucTkzMw3k592!W!#1&a0&DB4%3D%!Mp>75)%<=ym6tbZsP zmj7P1U-NSEl@uM=Jp22SP&CTOMF-iT=wLe(9b$)~F?J|A)DA_5*`ergI~0wz zDLO)+=tzO0qXdeM7AP7gP&8hk=oo>bV+D$i6DT@fpy&jFq6q>;Ckhlz6ev1LplFgn z(a8curwA0CDo`|8py)J#qSJ+{qWznfR=hM0!0rC6g?tP^r%45V**8w3luFB zD0)Jm=t+U1rv!=?2^2joP_$T}=ox{cX9bF$6DWFKpy&mGq8Ej#qFbAnZpndE+NS4S z-xi9-BtR2BW+ytH8sq%tSn(fCIwYM$PPX89K7L*aNu|Ux#0!5n&RYjd!lupWlRN5vu zU0PIc>CaE2e~WVRl@x8>BAb1EC>rE^DB8jfMO)gTXe&DuZEc65ZR}9AtsRO6+o5PX zI}~kiQ?!FX(T)N|I|&r+EKszIK+zC^qFn`wb`vPtU7%>FK+zroMZ*M&_7o@@E>N_W zK+y<+qP+!*_7N!BSDE>6sx1v?wQENzp+q zvQKXeMF%?{iVm?u(HJ`v9cqW7!|YIWxE+ed+M(zOI}{yhhoYlwijEd28YfURUZCh0 zfudstijET~I$ogY1c9On0!1eZ6ipN;I!T~tl0ebP0!60?6rCziG+ChNG=ZYi1&YoP zD4HTrG*zf78r7oI@}^u-xAX|e=uk8wy$0mW7UkqCDLSV`)?;ocn(llknqh~cbL~)c zo*jzLw?okdb||{g4n-H)q3B{e6wS0Lx$Yx1&Xc` zD7spp=o*2dIRZu33KU%@P;|XO(G3DcHwqNpBv5p-K+#-*qFV%tZWXGErnM;Tlmn^s zOwYSMI~1*wt|Z;oqMUpsMR&Exj=VJ#&2v5!-ED`Wd+bm&-ws9h+M(z^I~3h-hoT4U zP_)1fMGx8(JtR={ut3ox0!5Ds6g?(T^teFLLV=# zD0)_)=sAI+=LL#h5GZ<4py(xmqL&4VUJdy)zX3>wGBs&kjX} zmT}8H6cz1I)Wi-&B|8)~wL?*6hoTxg6qRj?nh6v&7bt2WP}EYOs8*n;l|WIQKv8Rf zqI!X%ia=2tfuiLEirNYkwG$|65GZOCC~7ZI)Ip%Aqd?K}0!5t!iaHBbMSry@t$bJd zj<#|R=kHK-Zo2cROUrWdl@zViGTZ#_P_(l1p{Sc3idL~h(W-VRTFnkc-R)4cx*dwv zutU-R>`>Ihrl_Yt(V7B9YY7ysEl{+MK+(DaMZE-y))OdNU!bVBK+y&QMSTQ{HWVo8 zD^RqNKv6$|qKyTLHW4V=RG_H8K+$FbMFWJYqOL7V2jxI2GrQ(+R%}_lrT=4kGoyhm z%gI+#v}Mce%=w{cE9XPe)^;e`#tuc>+M#H$9g4QIL(%qjDB8geMLXJ|XeXPZodt?^ z5hxlWP_(N+(QX1oy9*Qz6)4(6plFyt(VhZD!v%`=5-1uWP_(x|(LMr2`wA58Cr~s} zplE-Aq5}kq4iqRFB~%p+YFWB12U6K6JsP`3DEc#fVH(}CoO~rkV_Ie}-WQ4vbv_gw zW{0A~?NBt<4n;@Uq3B3E6dh%UqND9lG|mo1<86wL5hyxVpy)V(qT>aMP7o-XAW(Fo zK+!~jqLT!QCJ7XsEKqccK+&lJMUw@JP7^3PU7+X;fubn_MN=6fF`cdRm}pu|Ux?0!7aX6g?+U^t?dP3j#$i3KYF0 zQ1r4u(JKN)uL=~sCQ$UcP*pUqW$EM`NaeKja@e~=(NXCO(;F?z$yZYJPRs1-M?%pO z=R?uEb|`w!4n^@`p6DNAKRhm6Puz>1&TfsDEeHW=nH|OF9nLe z5-9pwpy(TcqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7lEQ*1&V$XDEeKX=nsLSKLv{Z z5~_;cYFTI)S3r0!8%#MHPXfHUdS<2^6&zC~7BA z)F4pQC{Wa1ps0gDQAdHI$yZXeN^Q306QO8T=R?tIb|~s@hoaT(P_%{}ivDMZq8@fA>S>3fHSJKemQB&x z0!8Zx6s;>z)JvdfJ%OV21&VqL6m1|-)JLFbLxG~c0!14M6!jA*+E}1y6M>>l1&aC$ z6m2F@G(ezepg_^)0!4#_s-l%^OS|MiDkIWUin`TSZ|V0+56x~-TTZ@`qHSukqn`>z z+d3bL2HT-%J3AC@Z-=5C>`=6$9g23cL($H5DB8siMMG?gb`>bvO`vFZfuf-TMSBPo z4HGEZQ=n+LK+#?TMI!`?_7*7GN1$k5fuj8cibe_)?JrPtfI!iK0!5<)ibe|*9VAe6 zuuxUBRc+~#97tt+x{GM*P;_N_ZR{bn<>V_VI=nW!|LIUP*7;C$gdK{Gv_sKRb|^a9 z4n^baP&D2SMaS5o=vX@x9cNQ?yg<A^6$yZWzL2XueHWXdxd?>oe4n-H+p=hQZiY~E3(WQ1My37tmv+PiGxgCnG zuqnDyplG&0(NzLPR|^zfBTzI)py*nGqU!{Tt`{h}L7?bHfufrPif$Gtnk!Iri$Kw> z0!6n86x}XRbcaCEodQL72^7r}s*295Ev=FRsT`V~cYS^+Iwn0ddv|R)`AUlJtIf7} zJ`~;Wd?Q1qZ3iXO5<(ZhBqdc+PzkJ_Q=F*_7JZd0^Spy&yKq9+B4o)Rcp zBvACUK+$4>qGtq(o)sv1PN3*{fua`#ie3~bdP$(@Wr3ns1d3i2D0)qx=yidjHw22_ z6exO2s4ALYTRJ2MQh7JsMRac{x~N4y-mWbtUrEt>wb`^6L(%)rhoYr+DEhz-MIYLs z=p#E6eQbxKPwY_isU3P_(>2 zQ73_-&H_bU1d3J=DC#Ouw4y-KN&-bI3sptMR;Ax^AeF)Csn$(eRd1tpO+N{}TdQ*N zl@xVvm9>8@6s_)jd@WkT4n_a7Ls1Vq6!o-2(VBKBTFVYaYulk{9Xk}QYg5!qplCgT zqV)xedJ7b7AW+mtplCyZqP_w}8wnKk6DZnPplB0;qD=*g`U@0oCQvj$plF~#(dGh0 zg9M7U5GdMGplBqEP}xqXmi%5-2)Ypy&{RqA>zRhYD3i+qNp5 zngglql%97zI265{t|T4Ss+@c!MMt*E=DZb(j&eQ}9c_oAads#gZ-=5|>`-*99g2># zL(%beC_2FoMH6g_P82AbC{T2gK+zja9f7bvMW5QC=rcPM zeQt-MFYHkCr5%dCvMKsnpy(TcqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7lEQ*1&V$X zDEeKX=nsLSKLv{Z5-9pxpy(fgqJIU7{u3xF)Wr>Rii$#2(fh4Rm*qezXQ!t(E)7Ll zdN`y>T{-zmifZbz1s{f@vh$&+nH`Fn+o7n19g14op{UjlMXl^mRA+~x)^;eWw<)R! z6txj3T27#-tw2#bfuaV1qDFzD_5wv61d2Ke6fG}M)JdSIvp`W7fua=zinZ-T&_eyUSx>{X1`AUlZSC=*UBoy^< zJ{0w|L(!UcC|b)7MQhukXdOEgt!sy(UUn#2&kjZF+Z6Q{DB3`vsE1&THj zDC#Frw6Q?ZCIUs93KaDhDB4V*Xn;V`K!Kvo1&Rg<6m20;w534NRsuy^3lwc5P_(U3 zRkV6tX|)_k<>K_v*&3l}lk{-N;JR}1l@#q*mu>Y~DB8*SP_(lhigvL>(GWWn?P`aj z-Rw}byB&&#+M#F8utU)VI~1L0hoXsgC_2fe zXp%tD$pS^E2o#+vP&8Sf=rn<%(*=so5Ga}=P&8Gb=uCm4vjmE!2^5_zP;`z!(R6{L z83IM;3KX3uP;|aP(FFoU7YbEHN7a??%7Ikcr*C3MhobM7-C(OLCtpd?rFGe>UxlK} zoDW5_>`-*M9g427L(!FXD4K1DqO0ssbhRCduCYVW9GjwR1&Xc{D7s#t=mvqJ8wHAP z5-7S^plGf@(JcZ+w+a;9CQx*{K+zonMRy7m-6c>oPoU^-fuef^islOx-78RZpFq+5 zLRHbsy3!vxkje$=dDoYOqRpG+dIq3Cft6fLwv z(GzwkdeRO>PuZbpksXSjwkcXHQ1pyI(X#?Y&j}PgFHrP?K+%f=MK1{yy)01lia^n; z0!6P06umA`^oBsun*v2|2^768Q1p&K(Gr28cLj>x6DWFLs49A}uC!?mr1DdGlI%mF zXjmy9OY6$XS5owGUAE8nq39FmL(!*pDEiC}MW5TD=nFd(eQAfHuk29twH=DSu|v_f zHbvhF6n!sH^n*arj{-$M2^9S-Q1pvH(XRqUzX=rmE>QG`K+&H9MSlqt{Vh=Rk3iAC z0!9A`6ct*>&31~40!2*(ib?`SO@*qW59>;&teI%gI+#)Vy_e z-H)NDh4Z1Pr5%cD?NHRp4n=i#C~9qoqIx?NRqRmI#tucx*%Y-EC~7BA)F4pQC{Wa1 zps0gDQAdHI1&THoC>kVCw1q&?mI6gv2^4KDP_&Ie(Y69bg9VDV6DZnVs4D8wx>WfkS5%u6 z^$bO&WjEMbmy@rgXqVR6y1#{@A#W2^1YHP;`hu(HMcE zLj{Ts6DT@dplGZ>(GdbgM+y`jB~%sd)Vj2L4x}7yJ-W!-#c zvqI6!>D${wt;@+*QuJ8stm(g@=yB&m(Ly^EJzLpF1ClzOX~lmv$)n$__ph6@j8v1&US^DC#ayw7Nji8UjWC6DaB-R28+TFWsF3 zsdPwJg<95EZ|RRo56$+hFDG9~(K_|n>rF$^y3U89UUn#2&kjZF+o7np9f~%vLs1_) z6m4jSqP})0+Q_D;pFq*Z0!5n$6m2R{)L)=zGl8N30!0G_iZ&N08YED(g+S4k0!3R1 z6m2a~w2eT~wgN?i1&X#4DB512Xa|9!9R-SZ5~_;UsxSSO1F4KnkE5*}indFS#_n8S zPQH?&-RiSWhi&q4Ono`|N{UXX&wu7#D4O7WC_2#& zMHB5%bdnv4CfT9rWIGg{Vuzwr?NBt?4n?Qg6rCCU5B_2uL%DVklM-Ow@=UFCczy4ns!*Vv(Gjvb1wwL{T$b||{u z4n;TEq3A|C6y0P~bhALwT!Ern1d47ID7sCc=yrjkI|PdE6ezk&plF^z(cJ6g^R&ecLJ&J?VTXdddz(i|kPJv>l2T+o9+gI}|-@hoa}~Q1rYVie9iOdQqV0 zC4r)s1&Uq~D0)?(=rw_&*9D5+5GZ<6py(}uqPGQ#-VrETB2e_MK+$^wMehp~EfpyG zK%nSDfufHDiar)7`b4NIdc3~0TwSi{lXMr+!ccTpdNlUa`f~D>6n$Brtydq4zH&Yk zeQk%LZ|qR?tsRQKvqRDMb}0J64n;rOq39<&6#Z;d^ou~zuL4EC2^9S|CQ#H| zps0mVRrGm%X^$L8rFVMv{uiOBU#onytdx_lq^NZzJHAaQs&_sVRqRmI#tucx*`cVd z9g5o7p{T(QMU8eSYHx?44mL#{1&WpzDC#6o)LEdYi$Ku|0!3W~idGaTT1lX2Wr3n@ z0!6C`6s;;yw3F%E?z!v|c59q-`i#-}z9~+YUt=*rBM89f~%zLs4Hl6m4XOqJDNL+Sm?7 zo7fa>Dp1s4plCCJq5%R$0|kmU7bqGeP_%_W(Ut;5TL~0xEl{+LK+(1WMS}&3wi77Y zUZ7|PfubD+igpqx+F77z7lEQ7LRHbamC`3Ukjm!i#(l3))H!{7+qF_ozLKInDp^fq zC>rK`DB9BwMZ@h-w3i)wU$2oxPDP;`_)(a{1$;{=Mv3ltqAP;{(7 z(Q!gm(e9Pf|8gLe`RUsA&`>mY#e5uJDJNe^(ZotNxI-v9$@x$;$qq#)+o9+bI~1L2 zhoZ@LC_2p!MW@@L=nOj)O|dDODo}K$K+#zOMbiX|&K4*-N1$lBK+z0=qH_g`&J!p) zU!dp$fuaiqiY^i;x>%rSra;jp0!5b!6kR4zG)ti9a)F{NgsP$mmC_M8kjiiA{fkZv zMPH|JWu=^aB}La%vh$V?MRS}FMc3M)=sG(TU2lh?8|+YYqaBKFvP03$b|{)_hoW0- zif$Dsx=o`vr;~5GYz8Q1qZc z(L(}74+|7MB2e_GK+$6YMUM+rMORfy^K&4Tm1}c2SBIkG(jD0gE9K-XDOyy?-s~KT zo_0PIEw)3^Gj=F?)(%C_*`erpI~2WOhoTqlQ1p@=ie9!UdPShwGBs&JIQ2+o9+OI~4tB zhoYbCQ1r7Mihi*}(XVzW`pu^3cY&fm1d9F?DEdpF=x>3de*}vD6)5^ops3I$ZnjfY z6ewyUP*f5qYAR5a2^7@`6qN;vnh6v&7bt2WP}EYOs8*n;l~7gmRi!jA2U5AalEe8r z6m60o4ykKXPQH?&Hf^%~R|-YTIUkDJ+M%eO9f}(4P}FFLqV{$u>R^YWj&>+o-VQ~b zY>GMy6m=0OT0x+wt3c6;0!1qc6s;^!)J>ph6@j8v1&US^DC#ayw7Nji8UjWC6DaB- zP}EbPXib5lwFHXR7ARUrplDs8s;ItAX=)CnazwgWR%uhcrGG_^C+pRwoO~rk8??!8 z>K2OnI3J2Ov_nx}I}~kXhoXLVDB9Q#MVr{6Xj3~B^|wROW;R6w1d0X<6m2e0G)SOm z3xT371&X#3DB4<}Xd8i|Z3T)33lwc9P_(^3(GCJdI|>x-Bv7=oK+!G&MMDINb`>bv zO`vFZp{i*8Hl-JGAe9B_p|jqhXzsEbY;DTPS5h>*P4@k&p=dAXL(vF36zy$?qJ8X8 zw67hC_OnCLNIMkmZ-=4->`-)|P0=WUqR|3H2MH7%EKqcaK+zb1qC*9W4ihLkT%c&I zK+zEbMMnx09VJk7v_R1~fuivOMaKvf9V<|DoIug>0!1eX6ipDSiiWi*wOcJ$v`>0s z+Mc0kQF>M5iEYZsS5kCxo2>Whq39InL(!>rD4J}CqSNe9bh;gi&agw#6gw16wL{UF zb|^Z_rf8Z#(b)n;=Li%{7buz`P;{<9(Rl(z=L-~FAW(FnK+#14MHdSc%@ioQM4;$W zfuhRicV@%+A{}InUl|KQYd;Ly(QMwZOX}4p*m+G3k^f^x1(*^Fg|~jq*=qv{2O6y!~OY{s``c{`Iob{4P6@wh4u{x z<|sQg%+0T|cWwAFzn0alp-=we+wKh$S1c5IG%U;?Zdtpb#j1tEdJQ{vFBJMTT(m}^ z(63=hk3yk;!%Axv3Y#~KUZ+sls^QjNg~H&5pVu!Gc5LX|r%)KuFsW~$Ftp*xeucvD zhT2UFg?$=!-mFmAzhUOULSb~ndxHvvF%8|eDip>x9K21TaCF1%gA0XY8-CrsP?*rr zZ>K_GQo|{`6bh3Y7VTOnOlhbaS}06w7&5F-n9*?Q@Iv8&hNUA4g_#Yj?pr9#Y8W%J zP?+6t=K+PnoQB^=6$&>rY;tg+Ft=gym_p(9hQ)^!3iBH3k0=!GZP@LoLSaF}tZ{|H zBMl!OQz$HK=ze^mu&Cj%35CM54f7@z3NJSNIjK;1wW0s1g~FQ+r=M0RENOW5j6z{) zLz^=Tg^wGCPAe2XZ@A)|LgDL%k7pDL-#4srexdMl!`KT8h2I@he0 zJQN$#PqXhL#NX|aR#`H54`xP7055?{x6}KiOkQu`&HXDmJEf zIhtH-Om9;&rP!F>XJlHjF}+d5jACPYrT+!R#`IF{nZ?HRTH9I0#`I#z*~P~6YPUJX z#`JQf8;XtT^(J$Rjp+pgw-+1JGrs2)8`D#E?=3c_=Ugr*Hl`=dJyL8;&w5%|Y)nsE zSyXIH&pUXw*q9zTezDk?9{GE<*q9!=d9&DFtv)!!_1*g60EQ|vV|wLSB;L;kBnpZsUd7keGwBmW5b zXR&Z|{;T6T%ja$Vy6O2p|C9g9|C1D!Kd>%uy_dDZ@`t9eL5#!mzpceSb-Bs>|8`V< z>53c1?<~$=2UhGGqnQ6iE^ZW~SsMLfY?m&=#xXuzDIc4}XqsQ4DQ+5L_x$TYv43@R z%Kx?%M(2NyM|u_uor^m*X|_wDQ~o!qFfMODS6fZxzaM|S?zqmyowC{=jvR78=i<&a zm3x0$^1=z7i@RjCi+69gU7^d^{LCr&nNIoNhh-nIvgZH$fVaj699V5x?fs*t?z`;c z-7Y^7Mi#o{e;*3d(}#OLKHT2bqs6rgoes|bFthUCyP%qC zDi=(>`j>R^YAOppyYISV)5oh^ecq!Z@{dM|c?9cSXYhON^{!BHMH~)L)>xqRe!)9_ zdfiIP&b;{G>7Ps}bow%Qf z{fDpFP*|aB&MlqE|NmL-rhER?v-*em>#cZL~A-MvtEccV@nD%8L0Uh8*GCiHpU_xawv_p$%jIgZS= ze&;M-=aPGkMIss57qkk6+<(UBX&KqqScm)1_`*VW>&5+Nq*-sznttv-BR!H43TK7; zwdv3*(q_9hwOz8p?Ye|QX?;VjTJ2>h6pC~XMcVAvYWG$nTa|XOL!O>-HxP$~9Ldswe8ZPuXff~%1mY{YTWHLN{eo$I%t&sv(2OIs8On~PBxI& zJRhC6v88lV?&5dYl5Cq3-n%PP-LY$Fhpce>j8WU3Q_$5-q^p-QM`>N|DzLTMZRkJQ zcB#y*sqQBp6Sggq*TIct`;(3dhtjrPRbYE=4|^iyo(P3{(vP{26WY7$9$n|P@#n>s|!$GyjiS{23jd!KO9SuU0T*uwleI`c3%CtnN0ml&5_n_ zWG~wwY2n{Z&9MDhzxE%_$r;p8H)uxVfsYh$UzGlX3w47G<#8fXwatHc56sKW88Xm4onue8cxuq>dDG@BoL)a@Zr!w5v*-O^pN+;P zjj3y5=Bz>a4bvCSo;Sa6enb7hLnh4Wp&ug+^JE7^9m^Odz-1+kobqi)2Gp(x&ixaj|rWN|!nE8#Kv)!Zu6!OCM zb*WDL$dIt-b@+FGUN|E%GwgMWbj|T%dw5>PeqQ^GaE^5h@;YR6*j*hq3Iq0x)xAP# z>ETXZD_7cjy<9QwM>pJHH=NhEr`M~m*P;9WWcW@Q;cU;_)9X;`h91Op$7%ZZgg+m9 z`ngwcul+98U+#Z5S2kA98`nJ2tw+-1KOIT?J@a~c9df<)dwCrqOKeX4HPfM|I@~Ji zrCDXxUGCtu=p}fnUth2Nh+x357k7)Wt=BeKvHi4S{g~rFnPw}uzu`1nlrFA<2mKGR z=SC7)loO22u0Fi({^%WQ@49SZd=U1sBiq=bS_o(KVcTc>QQO|Fh{4HC6sW=`+so_a z)_%*O|Ajg2GrD*kcCr!KcJjCJKWi}JVB32cy}j&zj`+Wwt-bz7LorP@D%pGtd;Kyx z1>4Wo&VRN6gLS_|>wcIvaPyW7o?ooz`~Tzl|5||U{mtgKV+YsuKi-aPhL+p2?El~P z%pTUfr!c~;>sH&=;bu-)u0OOkeAk>K8b~fA7gF*NFf3Eh;=;(Fs zVXL5bi*?r5C0j}UDs(G+uv^=`atC^S`*@wVGtkRl{mpfd@_#ZOudi*g|8}DOJY)y6 z;5JfUJJxpY=_WnJpBaBF!G?Dx{0EER^od8ZbG)vR1KmRP@`Z{=dOA{I(ynIbPGoI|3+u9OZDyTb#WV9r*rL@TUiz!>a~mfcH|yjIC5NCj$8SWhX!~3&$k;D6FZjwc!gZ%g2`$*I1vm6{YI0q;O1PYIBeIRYi%4 z${Opry11&QxG4F|*zq>f+KTGh@#8Dq6N&MqlZ(p|C6!g>`8B~5ZB#9LFDR=l9G57{ zugOnT)Rq?%SGnb=tP1)bG9q=t6_ttV+JfrBs#4cmNo8$Ck>A^{BgXi3WQ*CXDy|-1 zX>%BiX{hzXx^VMeT$Nv)GUu$f^6Jrvg4&W28-I1_KE=sF{;_1Gw<10%mYKpbUgVle&RlABFGC0xXFF{d@!3)al z61u9y-weeS`4)>pl_k}Q{Gwnq!~DM8oRy?3cyY}b)^B3`m?;U{*5$U93-fDAD=UKa zG%`70USZ0RrBxFW1?E^$X>~9$)@3kCH!^>-CCW-G#wFLf{Uz^QX^JsK1gt+dmT3l_e#K7Cq;UY|(dNenq0DD!-z-ytKw2b5(JE z(G-7S3R(zTRh@4m@;9}uV2RB%E2|3=)iss2PK!-PZNp&Qv=~Xs{*+u`*^^)9PdQOJ zzPKX!94Z%7m5v@$Q(e z+Yq)&62+4Xi;Ig=W?3u5j<7ZPc7zyLJS9<*U+VU9wxRlPZE2ge%GxUHuzjqgthBKC zsP9|q4ra+!mp3@MgWIkis$AGqRM%9OsHtBZ9A@%tXPmxp?%XBG3Hkd*ab;=CeTdnx zV{&ehNqnO*hB41J-Wg_ zOZ%&4i1p$+@>?9~Qx6l(hp)Wiu ziz9e#b%B5GPE?Pv3zeWxJGOC@OPOSOu^qQ`1;dow`10(K84OqKd$e#~>f*aT>{O7P z@uI;+IzLtwR}`78DF@@^1}^lkgyf8^#d$O96ZP|^&#s%7aQjknWTj%&F4Jd_vGm*Wh>{6Xkolm8DnEgx#B8fv25dRQ9p zXXFiQF(P&!wpPl?y@fdc^3>MsO<7T;e^gDLNwkfFO=1TbZOXhnow4i;o?L$!=d z2{nnLF~Lc^xaYL_4Ndin2hJTb z#6Z)mg>$D`oiS&AUDH6jmA|L$`_mn;K4&agG;Cnwf`QZXh8wACm^N!qySKk+#K5^Z zbM4iEou@Z0*m=f+?13}02UZTw9%wg>_nc-kFmT4)`o_k(ne_wb)X$sQG;7aXL&3f^ z&>3RMt;?p_^XCn0wA<=d8;wo3vsg0wi@0kG@BD2ZoK)OJyT1X8D=KU4(Bu2s^71-) zX0j`^{DRW5(tVmQk#p^E8*Ig@#=5-R!9&aEPhU8vuAzAG0((VcUQ_Wr|D~1cg;PVN z^Zb+RxcVif^QPA?_NO$Y#j&>ez~J_-q@m5C+sVid88voM>dx@V9@yA^>#5lR+XV~l zdZ8fSnp8UGx}~$$K(Lg%Ht!gA9T2dVO&8a&aF-FK)^Z3gID*yVJ36~;{`>`bA-@d% z$Go&Sf48_sF1IliR8IcK5QSxSdax6&JAApx*yX4bHMzss+SPm~kIlB7lA~!}OYYh( zp;Z+OVJA_)!z>7Z9oSNiXTA>2ZMdy2&2?yOc_tZZW2#TM*E8xH8iH|JlkQ*4OmG~p zDlT+$69VhhGDWrJ6vN4+Hy=aIHDJqk56f! z6}npnspk(j->L1(F_Y}BMBz9)meQuAxA0d7}jsSR#- zHN~n6%o%Nsm*CPS`Gl{lyL_#za0dhbe4Y1SKC2zaT5}Spxe?d0ZRQ+Iiq4Ewk1tKA zjqSDvZNmKI*zDxMh~1TtrePPk>dLb=Kyv<4*1-6x$}y$ZO0-Q;VHd}C*MUj;intkZ znv~jA>OLkzB4IDCHs1ruv&(FofZwu6HZK@~J94Ee21k^V{35$yvsFvjm%vSRw7H(V zdTDMW73qALXDtdA&DKJ4uDMQ5mEJeF&|g)|gPXUl&gc2n?&ewYzKiWc$&n^oZTSWM zZM5VQDJ!z7xaMD8Q2R$hn%8blg2tFXPj*dX%fLKY+tS)>rG=&b>1BMron8FC>>Lqv z*#6m~_u$TA;TUW47MJb!94rQ0o z&1=Zrs`c-uxC<4#hmaVZUmD!NGw+hUv2v_=P+Qh~ap835vL^NFHF+CnFt>4B1CJHO z$lUcs=pg^t=VsBhujnPUF<`exOAGB7V#o9ve?2Aps@29ch}kP2=1kq=TA-)R@CTZl6ouIpS6FU8iSS>%bC38=8v-Z zo^+nwAxqtrn(ySeg$;Is76+eXd)771Y^AZ3oq>TK(|?|YJ($~JKn-|bhd5U@*ZkRJH~Fm_?ytq)c;h9 zg|Ne&osD$ut`}5j0PWghK!&gjQnS0rE=5wVQFt=>vJdCVpm7oCX0z`%khCAAEKTah zZ}B>b7PGcuTt(%iU@g#oaW~rCc!S0P>!rYME8B}^{tFuZ)2?yClPOmTE$*WDv*+&b zx(?TL@qxQ@>30NoS6wHKmAurOmKv+OTV7(j1UHSCXs~P?Q?wJN-2ZIZ(BQ(xpRjF! z{h-mT>Og)?&kZ`PdPA4 z=HN;vc?;6^WG+`E8!yu31$R#U(YPCxen)VX%#_{1xaD~!xeKQ5HNl+NDEvJ*xjqWZ z^2^7koTP)*>|Snj<86N3srfoTZ)oyB$F7m*Zbkm@d^ad>CiUM17%X#(!&LrwyUw3% z&FdC>Ps(x!D>&FISyAj$8>0fJ=n=XktEt<@MK>Z6sfomd%9b zQP^vtT-7nNG}NkVtL^12HI)BxThraq-0CHa)cYy9E$*%~HzDn%biF#}X3w>7k_|7W z@2(mAli|N=s$!b$dOuY0|_ zQZL{#OTo=~_iEqPClq(0bgz$d0Oa*mhAb${uNY^CgkrlMPZ{9FvmG*j` z9iZ&iYkoz_4LP@UTHa&{8acr=e~VMGzl_cIWP{fon6c)|yB19vH+tIxYHhKYH#eG~ zN#b{L7!PiHCK9xp8F9*4VNBIH+gQOqSZW)-`NrI&d~2F>aNcT2cSp#bh=cXheCO2N zTuk=L3p9QsaCDVxa&NVITQobJPyT-3nn#R;Su4yhv^8Cl@Gm4nZt}dlffkc9OZ#MM z^C-||tLYY&7qz&>N#}1RHEpWz{&HUXzz0dBKfSdbMK@uZy&7dX?C#+q7ET zyDmbb3k!G4?(gpX=QqsFE}lEJe)@EK39p8?@cSZZ*L@wWDormp8d;pM~sh>(o`Z)zfTKy8R=~R+8IFuG*;mYJ-H*>|<@cT(wQw zU)=2ruD{``d#Vj}y zzN@-H^$XQ+RqaE!{&2skI>Fp{GE`fuy05Nud|TBXs_rWa93P;Xt2$hD57h$IF{%}+ zHLCll9;iA)b&hI->SEQSR9C2;q`Fe|Y}GZYYgMmSy;1dc)q7PRR()LcS=Com-&Xxd z^$XSSRDV|eQ`LQd)~%mbs_j*~s%ES1sG6fXOmz>{Le;UV6I3UwCRCm0ZhCW7n^X^1 zJx29J)s?E}s9vOcg{u2T6F0uwRPR-NMDRYNGs(!Bet?Eyzf2c<6IOVoOrfQa|`=qhsJymy59jH1~b$8VQ)l${* zs*_X?P_0*;quQu?nCj80C#asTdba9?s+X%?r+TaEJ*p3@KB4-&>T9a+s(!4xQS}Ga zEvkR3X4rAut&eR~JF0G{+FNxe)xoN}s}`x2t4>r+sLoP7MD;M$<*KKso~3$`s{2}L zH(xia-lO`c>NBdZs=lZCnd*0{TU5h#qVj!E?V#FSwV!H^>aMDzR7+K>RQFY#t~ytB zk?K;_6I55Jp09eD>h-F3s6MFrgzAf`Z>erj{Yv#m)jw4;>}wI+a<*0Ns@h+554#L= z&yP_(z|P$+AEdg>E(%>fMRl#6vt7PXb-kV7U4BvZGrP!gd6VkSc8%fk2-QREn!@Fy zRPVBD2A9{X{%Icxb~)3&dBN4fo79W~p8} zAjmhWe!fePe^ec47b33z-BcU%g1k)io*_YgT=nl^L2hjqE^fHu5kaj|J$bhvpR4+k zeQewH_r7YEy@T9Wb^rVzAEbI&VUTZD{jxa7KdTNJ6XZQq7mf|`F{<~K1^G$UaAlC& zsE(cxMM4^<>vQ8)vl9+yn||DpCHdsy<)#0->Ul60YToPnpYR(y;KjK z7UUJG57YKz^A_NwES2YIsUs$+wEk?I@A2l*4#?N18w z0M%)y1bKn#HKzsnPSx*L2Kf)wVXK2&pnCXOK|VqCk#mClylV9PAa_(PUlZhgR99aV zuw6aFFj+-TY{fL+gS%^0ARBw7K z$oH%M^iGh|-VN&R?+0~^>d_wt`83rhHU#-q)onfvayQlL&x3rR>Um!V`AXFfz6$c! zs{OtV@?h12zYp?a)mt_N`9alRtO4crxAdQay5}!J9jm(h*C4M{ed_lhzpmQ$uON3< zt+fW28{bsb3+ziNT)tZMqx2wutGc6o`;mKosOnt%8YGtwQ@zc;56R_+Re!ZFMshi$ zO;Go?Z%A^vO!Zi6=(&7`>NED8NiM&snq^;}Bmz(7sN|LS;_r<&=iO|O%3SJfWkJFAXREmo~kO{mUMU7~uN z>T1R+mZ?OTG}aI;;t<(aFxNcAw) z<*LW4u2el!^+MH4Rj*aOQ8hDUKHGHKsCH8As+z6ZS2ag7Msu`|-TWPjQ{Qj)?)tWPY{m8YGZ9MkVYN50&yZ<5{%4u9O zx2bNb)ux7^&Z5iS^4%25aqqDX zPF+(|!|bUGn{2fI>ECwNqpjZL9o(T?4QQ*>|LbLsuD?hSLtFRfo^yXY+JDUc|GWNj zt)H!@>+aR^=eDW)+r|Fl_CL!0-QTkZheHQiwI+t$)eZjL^y=)Nd9cpV)i$oXY(L|V zuKf+9j&GMa;m{~^#f{JT<;Lm8H`o3d#yUfZVd2nADS%G557F)V%iT5X-`{iH?vLjV zx9-&G&N(t{-$EEn*Kwxn_C1EN&d@$1!l7)}p+BB;`)ca=*4Rxxw_mvBXl4J5?^5e# z80!ojX5(}H@yBx)8b}@A^(o`C=3sJsb}80kd?(rXqIM48kMZ4PAa#8A+xXmib@SKO z{+YjrtlJIad~koOio&7ceS>cI=$>=`Ppi`36SKmhvBvnLKf6?FF@GIrheOspOa8g( zy1!TKKXv}rrz~#=dye`0#JbJp1y=mOG8^A+1gmbk?$1^B6_-!2{%$td#k$?`$c@jf zcQ;M;4eJbzFrQbu4*fAcQ?f;WuiE_mNKaPjk8dp+nlpb;w*BSpnmc?%?%)xFM_6}m zZeGgc@Zm$Vvqz2`oNG_n-+`G+i_1!aFVzZ09JV|3jMtG%mioyH_Vxauu69Hn_~n+$ zwc}pda(`Xt?|a5ZeP4e}$CBbrX$9-HtjM0#J6f_$$+|7Eqt|Uo?{)szbz45ne#N>% z1Ac#da_^C|&a7CsC6wi!JJWye^)2anp`Cw!yC(bZU;g@gMak*oR*qd+x@yehTSAXG z;{L~N`mpfvEnnxh>f;_K+hcm(ig6!oiJkHImJf5^+G-5T$1NYbqIAWWr&7jH)#oYe zYuUJk6;EwhpUX5u{xmDU54Y;rt8mluor-^+df5FX50==p!;5SV`rmx>RO?>(!_=ly zo93mDZ+Wp@L+SK!(I1wjJ-%gqJ6o=-&`!U<{r;Bpc5bQO-x5=8?bidgwCj0xv3usr zmnN3Bnsrh5k5?;ye7O3VI-6RbRtIMF8By}g)cwajvgO5G_qaZ{y!0h4&5K)BY)DzGu0yVV%m_jzV&sXspVxITAea(wUFcw7I_uC*J- zyIZ#8o>?4p{o#-8U8634{?aaEJIp#yV|}G=)TXIJ9L&<>yD*1RJ#rb4wyK&o%?Oxj5f3{t( z{GVqwq>cN*woQ7k+z&$!+1K!n`Y;q;c1a|>Y~(NP-gvWa^FtYn{_4G={i%12{JHBF zM-JckX#2_M&+b>&_qp^~y7_%^C=?Biy6gDw)9gP~+bqu9Wblp=NH4aJ$oHA%ROG}KW_9N2h8@l|9GwcxY2(caFEaa z$7}t^jsD|+gMIElUh6+@^dASz@wxwat^c^ue;hE^=lb(@#<{_WMWakti$ zm6ne!_t$lH?@^nU4=E|%G_~=-gJwTcBC8bmST0Ca0UpM%Vz3bd_ zQ~k%a{^JJ!vG-J;`;Tk=#|{2t?`b~wAJ_Vi8~n%K(|ztguJs=`_>aBoeeOT5^&dC* zkG*I3+<#o_KW^|Jd(ZT_|G3tF+%U7-Sm)WOKJCUnw&ni3)wAD8|KrtBB@cYD<#an5 zY#Vg7AJ=|thtdxIdKlHm8~eE5=eySD2V3@77W5OiH)P0tJr{kt?e0HcRDMZQ-AS7p zcW=1no2Jo!ts3<5voAfo|BS0vwZ5&fslTDY3KX0+M9v5*mX&89!d}A+qtu~ z`^w4l-I+1vFD;z0!cLfJ;n>l3&PYr1j5y-|N2;>zA-7|V zb$h4VLxy{ZjZUT@}Ra z`(8rrVmDf!S+Tde+w1nRLR;7lu}iI=j>5Azsx4~Q z*brNN-C~W#w~KYMlWzCeSv{@g9qVWF&@*;~J)0d{Y*XwNTfcoM)I0X3jjc~?srA`6 zR&EWjezCJ{Y|~?V+nTM9_2_HgWgY8k^YB#cbDQUlqAo^7jrP&odj%~@_Z{(zO0;rRPD)T(g&Puq;E!|@fi zLeC7xud~&4Ryh8$rL%1;w%X1K$KC55=Z52N+QOd~j!&`Y&JV{uo23iF@f=&KAH(r( zHnTs4-$?QqD3Y9SCt-r-b!_Pyq`^>COzKP2B=Ms zSDUC4)8p>@(I=(H!zS3|^!Or^b4q&r1{>Kv>G7_%UG`0nPqxjrUwXWkxpQ-Ryvb&w zqZjXJThYGA?OvOS#a`UK>a@g*kG0Ktm>0jw;JaS@cpK+?UVKMek?(u)xQ+S)FW$-) zr_Iu3ZR0Onxx8(>hmG@!w(;w1gg)C);zI8 z{1zL$-H!47-0rYre6}s^f-dp6&C4NO;=9|NHFSx;YLjj35`W+NZ0Zuf(pJ{OF7d-{ zF&A}-e{WMbv`gHsQbLQn#NA7cOS;5gw80PS5`Ww_@!?(KlWabZ=n}ugmf^@Q@rTTp zqq@W&w858liC5c-T-GJNuTA0TF7X966QkC|r`u%n*Ti49krk|oueQ}%v?l&ib|_T5 zCf?RoNXeSG-8u`6UK5{SYhwJm__y}lgmv+KtsJ;9UT9OO+Zdm0vpaQTyxyFcwlVHn z>C-pHr`jylZ;Th&GR)W*|J0^8b7STO_S}Lj`%du7&E7*?N5qD0a2DOnytn~uA`4F`!d_4nXg;VN4t({8_zL*hwY5ZUB}Yi_C6Qa@u+RrV_nBW zTm8qmj`wX|j&~gkY^|+ISjVfj#AmpUZZ@~8T}RAT;hC<(y|>{k*O6tDSTfBzezy&N znCtM{J$Bg7+-Tb{>^eTTNv3;k&vPBa%?bOy=ul=)+Y(XN z@r8*La~;>%wBoMgF53{9u45M)b1T&3u~c z2-_swd(JXv+Fq3II?O#=3hOw{CYs?oZm{KYePxa|+rqA+)>e3$>$uQn)eRSFHOWSl zJ}(@(!m^$J*4va?r=MdhjOONHh+66$6dDh+eo7!o4+FEG|NM5{)&~uF5CQ-DBJdLo9^|E)Y$fKH`Da-`uV>@ z)$U~5t-aCF!M5W&L&kaThdO*i$~349DOZ#s6^b&XQc;GCSCkLR~bY0Q^t_}l`-T1WeiCuW5|KZ7*eNw0&BHRA$hS(9y8ygssW5;rD zPSly>3|Zj0A93*wIYfiXkOoB=(x@myniOToLPZ&}NKu9yswhJiE6R{1iZbLdMGQGy z8AFax#*ibGG2|#^3|Xp-AnmMde(3S|sARvAN%Q^t_vl`-T5Wehn{ z8ADD|#*mYhG2|3w3^`R9Lrzo1kkgehWTkRo$h^q8w*A{x*qPaz9~k1<<&L*1>dbM5 zoaMP6`0))nTZ77wa};IBxr#F6JVhCDzM>4dKv9OQQIsJUD$0*tQeHv7T+^;A@9#E7a4=T!#hZJSV!-_KG5k(pDsG|81lAqV94E(cWwK(TVNNh-aUaKciQE=_fFKA;|%%0b3Y8` z8}gwBl_4J~%8(6;GUQ`L8S;su4Ea=1hJ2hQWz!cR|;cf{Yqh+tY0b2B04&-SfJGw!STquVMY{p8Xm?E%1| zJpov>7XXX)24K-B02bu~u&4llMTGz?Dgt0pF#wB709Z5{fJI{fSX2rKEZQ*~IoSls zDt0%O`pcqI?5>J8HXL<+Ig2X7p8MHK-=a!}mqp{rvS)sSUTEm;;# zB+H^nWLY$sj73ubShNoSi}nRz(S86d+8=;L2LP}r0l=aI0a#QAz@n)DESd(uqUiuE zss~`v3;-6*1YprD02a*#V9`MUEIJr~MRNdHG#7wH^8kTGW#Pz6CP-GD-JSEwWlIk1F&cX0E>04zEkfJG|-ShNa&MP~r8Xf+_P=#X%vi=E7}&T<#d4YKGvXVIDAsPoHN zbZ*#lKbz}YbRNUYqVvhJ=mN4VT0@pa7m{VsMPylYF?G<(NzE}x*C8**8s5SS^ySZ2f(810a$bc0E=z}V9`wgEV>zhMYjO3=vDw0 z-3Gv-+W}Z~2LOxi1Ypr!04%y25Lk3}II_P9l69fGE;>gRE%w`D;i&V=S@b~IJIY>{ z@hy6g;bqZ7WLfkuSr$D)mPL<}WzjmaELu;NMURnX(c@%U^aL4;o&;dgQvfV_8h}O5 z0I=v;02Vz5z@p~?So8t_i(Uj^(Mtd`x#k}{!QRkPlXhYa@KilnF^fANB zqEE=O=u@&R`iv}#J}1kfFUYd!OR_B5NR~xkk!8`>WGwmyfJNT|u;@Dg7JU!Eq8|WQ zvse7+Dq#Cu7mB04y2-z@m`=EZPl#MY{vAXb%7u?Fqo5y#QFW zHvo%90k9|^fJFrWEGh(GQ4s)(iUC+u0>Glt04y2q{a2Bbw6 znjl%P+j~~Lon_IH?v;!3w5apTSu`QdJ9~gEs$zIqR85veHDp;-OO{0w$+Bn?Sr$zu z%c3b{S+oyX7VS&MqWu6^v_Alg4gg?L0)Rya0Xe9uPRspc+3;-6b24K;d04zESfJJ8m0*ji`BH@8%(HeKxaiJ{Q%^jG| zNsBtaoJAL;dA$e8qBRUJi!LO~qKn9~=wh-gx`Zr?E+xyNwPaaz8Ce!xPL@Sikg@1W z02W;Zz@n=GSab~li>?J=(RBbUx*mW-4$+GAPvMhR%EQ_8Z%c7^rSo914i=G8w z(Q^PSdLDp9F95LUMF1AP1i+$~0a)}30E=D)V9{#;EP5S)MQ;GG=uH3?y#>Icw*gr6 z4gibZ1z^#804#bRfJGkwu;@cTV9|qVkyA~Otc&ek!rnu&Xm7i!_C89BI=`GnpQd>? z4v|HlF}y7LoGgpJAj_gJ$+Bo8Sr&aomPKEaWzjceS@bPg7JWy?qVEA%^aB8kHUY3` zGXRTz1Yprm04(|$fJMImuxJYai+%-Q(Qg1O`W=8pe*m!PPXHGE1;C=e0az4@sM(H1 zVE`7T0k9|nz@l^j7I}ccqL0%eub3cNIra*N_lYce!G(-S)cNHs%8YnF4wFT#7+w~& zCd;C2$g-#nSr)Y=%c6EfJMCkSkxPUMSTER)E9t7{Qy|B0|1M51Yl8r02b{8 zz@ho44Gysdn0I;YOfJI{gSTqiRMP&diDhFUu1ptdG0f9vWBaws& zk`;A_pBz~-)(M$jq%>rQ2YycJ=1i+$$ z0a!E#fJJiwSTqlSMe_kzv;crbhXAms0f0q~04!<(1Qu0AB3GCoS)1)mAYQdBa^HLD zEsR8+U(TW>5%2LmWYJ*^FN+Q*%c3L5vgk;%EINuTipU zELsh~qB8+lbQS=M&IVx7IRGp=7l1|Q0RoE-jYPgOL9+gIZFK5w3 z5wG>$vgl%lmqnM5WznT%S+tfci!LL}qRYv$=nAqdx{@r5t|H5#tI1e&4FHR-1z^#2 z04%y5fJHX|u;@kr7TpBEqMHF&bPE8BZUtb`Z2&B~9e_o50I=vz02bW^z@obWSac5n zi|z$r(R~0cx*vc=4*;;}K|o;9nn)zi1j#zpy&8L=EShbv!g>!yqRua8(YlCNl`o6d zGrTN%j4X>DC(EKI$g=23vMhRvEQ_8d%c5ti{7QG3;qPGB8^fmyC-T`3Iy8tYD4}eAQ1F+}=02X}+ zz@m=;ShN9vMIQqKiynzY4mClt>fKwdAC*NvyJr6_S@cE3JGW34eaY~$Xd_t` zeMOcv@-yUb^&0~KtNzotMo{u z#4NhdKAG&bP7hl8`?}Ai=A=iRU(TYz_L=4}vSdR@2f(5-02Y-4u&4rnMU?<78V|st2>>jr0t6Q2rbkLmkgO}*`>yk3 z(e^G>r$?P%&Z0@_-a%t!(PV~~MN`PKXdkjH+LtVg_9M%p{mHWE0J1DfkY&+4 z#-gbJESd(uqUiuEss~`v3;-6*1YprD02a*#V9`MUEIJr~MRNdHG#7wH^8i>hAAm&* z09bSg0E-#`Skwr>q9yhqEi4^bSeOgP6J@k=>RNR3BaON04zEKfJLhTSac=;i_QXI(b)hjItPG7 z=K`?kJOCD*55S@e09dpJ5Lk3rdgL_|BkIAB4T3h%$J?i{&7JZfO9aAlfzGiq?^bJ`SeM^=_-;rg} z_hec016dYrBFm!9WLfkhSr+|7#-g7ASo8}3i?#r;=vM$1{RY6I-vLilvRwe!3uYh_Uu!^@)fWLeaKEQ>mlWl<-xEb2^_MP10U zXj`%@>PnVH-N;z99RQ2E1F&d&02cKCU{Oy17G(pls22c>dIPYi4*-k$012 zV9|~MEb0%yqMZO(Gys4_I|Hz27XTIw1Yl7P0E-3zuqYQ0Sk%Ugd}D%SmAW^kwe^CQ z{@w0IcAgh?emRSVd0v~zvS>KN%c5P$vS#MvEZUdhWzl|QS+qY{79BvAMG3MjI*=@j>d3NaDp?jyBg>-cWGt!&V9^W!7R>}; z(JTNK%?4o6K>#c|7=T4{09Z5^fJO5FSTrAiMGF8}bO->88UR?-2*9Ey02VC-V9_D~ z799$}qQw9#S^~hL!vKLrlfB3i6C^9wz3+O8EZWt++S5DSi#orYMN2*J{QYFnGKQB$ zN0VjIF=Sb^oGgo0kY&-aWLb0^Sr#2nmPIF!WzmUbEIJ8*MJEHW=oA1JoeIFB(*Rg> zIsl7S0AQMHd4Ci;nan51AlY+q?H&A0><4aTZzhMYjO3=vDw0-3Gv-+W}Z~2LOxi z1Ypr!04%y2fJOHJu;^X@7TpKHqWb|@^Z)>h9t2>~LjWv#7=T5O0I=v$02ZwSV9|O& zV9{DH;w8+Yd?(IjvgnsA3y*nG=a;kSDbL%XP8L1Q@UrL`vMhR*EQ_8a%cAGWvgie} zEP9bFi(VqjqL<0C=oK;+y$Zmh*8o`bIsl8_0ASIZ04#b7fJJWuu;?8C7QG9=qW1t; z^gaNKJ^*0RhX5@42!KT!09f=f0E<2WV9}=lEcy(9MV|w(=nDWAeF+FGdcup0GeNQr zcQ+cJlttmNg^ga+`Q02b{4z@i-iSkxbYMLPkoXaE3d)wR0F`G zS^ySJ1Ypr502WOK1Qrd?h-^R0EPCFZ#CDZM8{I9)DH&1cm$PX93~#T4WYGZ(FN+dn zS#%&-7S)ku(NwZ5nnspI)5)@^o-B)IkY&+KG8WAOV9{&<799k@qJsfgGzWl1a{*X1 z4}eAU0a&yEfJKJ@u&4omMU4O~Y64)>E1tgVT&pDY^X-m-R7M%4M`EIKB`TQNr#EoXRHw1O;)jwQ>YzoB+H_c$g=2UvMf4T z02ZAMz@l>iSadD`i_QaJ(fI%@x&VMhYXDeuApnam0$|a_04%x$fJK)AuxKqHuxMFE z@QfqU*`B=mxSZ zx{)l4ZX(N~o5`~17BUvy3c#Y<09bT80E_MbV9}ibEV>JTMRxv07Cj2UqICc)S`WaY#{gLLH~@>D00b6YkrDaM1j#zl zGjXnzMcv$+jh@ViI=`Gn&t`b-4v|IAF}y5#o-B)AAj_f`$+GArvMhR;EQ?+t%c57w zvgkFkEP9=cMQ;GG=uH3?y#>Icw*gr64gibZ1z^#804#bRfJGkwu;@bo7JUT3q748n z`WS#kp8&AvQveoy2Ed}v0a)|}0E@l^V9`bZ7JUW4qOSpgMNel$hM6E)r@PnDo{>c> zA{M^Mh&sQVML%SC6B}jGCWeilvR zb&hRsV73@?keCCj3&WLeaWEQ_`y%cAaNS+qS_7WE*@qMl?~lugE>UH~lW4Zxy4 z04(YYz@mNtEZPBpMLPnps6POUb^>70000*448WpY09Z5-fJHd~EE)vBqFewLnJuxL0Su&84+@`wqNb%eV`)F~RY^!vIq+OE;4^UGPZd(_)-s4Uup z;bqaDWLdNqSr+Y0mPMn;vM8S{iwelHsE{m+ipa94n2bdw04y2}z@jk#EGh+H(O3W$ zjRRm&832pQ0a#Q4z@kb37L5mB(F6b%RROT58h}ML04%BnV9`VX7EJTR1uzb$&UEj*WWrj*vyiF}y4~o-B(_Aj_f?$+GAqvMf58EQ?Md z%c4`svgkCjEIOTxMJoYVv7M%ycqVoY* zbO8X1)&Q{RLI4(B1i+$;0a$bi0E;dKV9{Ct7F`CwqRRnTbOj)=Xn8cU+62iO=x!0M zkVRp4@A}GU)cNHsx;E;j-3`E^djME;F93_~17Okp04#a{fJF}iu;?KG7Cj8WqDKH& z^e6y})&a0+JphXy17OkP04#a}fJILNu;?iO7Cj9JEV?=xdCLUJdeFUl{~B5JzPn%a zOf>5Jau&T1^?q9>i(X`SS@aTF7QIZCMX!)$(W_)x^cqGkA0a)}I0E<2cV9^%< zEcz0FMH>NF^c4V$z6M~?Hvla97Jx^66jQSu zi^2dbN&{d~1b{{904(wVSd;<4q9_21VgM|P1F$F)fJLnUSkxMTMcV+ds0{#%+5)hs z9RQ2609e!>fJGeuSkw^^ShOh`sW(BgzIBcJ&9dkQXHlnE)cNHs>KgNoJ60BTV|ZD# z9a$E2C(EMk$+D;iSr+vq%c5+uEb2v;MZL+gs1F&7`U0@19{`JX0ASIM04(Ycz@nW1 zSTq2DMLPqqXcqt$4Fq6O4giY=0k9|+fJJ!#EE){Jq9Fh*8VbOoVE`-|4#1*a0a!Ew zfJGw#fkjjUn55S@c z04%BkU{N&yi)sK^R13hOi2y8`1i+%n04$mUz@mKsShOzyi}nLx(f$A|Isgz@v_~xR zg9(y#f@|sTDT_ibBw|tLm$PVE%xiy=ESk>nvZ$Uci)N5z(M+-|nnjjHv&pjPAhIkv zm@JFtkY&+aG8WAPV9|U47A*i^(IEgVY5-tSBLIt<09dpTfJKV{Sac`=ixva0XbAv| z4g+A(;Q%Z;0)RzF0P02VC;V9_!F799=1qGJG9v>XsvR2PfvYJy}nbu)3M%A!l1 zMJr-a=a;kSgqSz^6j^j4!^@(R$g=2UvMf4?4*(Ukx!x(a|rR|5izj*CT(G(oZodzd)K%c8%xwQx-=>ilvR z-4OFGI!zYc$ndi0CbBHLnJkNLAX zbT0sl?gL=a{QxX_0Dwgg0I02VzAz@kS0SoA0Wi`D_KXgvUn9s^*};{Ysr0)RzN z0Q02VzBz@ldWSoACai=G1n7F`#MtTREfX2ndL>t)eL?qfyI$D+Tu&5INi#h|a zs0$#l=%-ku(gev`nQh|yEQ_k#%OTswqs}j9QTMpF;4E3RJ;TeQ9%Nb6lPrs}$+D;y zSr+vs%c4GHS=5&-i~5me(GFxR+7W<7{Q+3C699__0I+Ch02b{6z@mWwEXo03(I5a8 zilvR<;T4{&yht13@?ic$+D=3EQ^ZCvZ#bCi$;@W(HOEU zDkaOJv1C~^j*LZR04yp8U{M7Ciz)$FG#-FO698CL1;Cw2CZ?&LGR8)nr+8CRrApMaH7D0a$bn0E^BA zV9|L1EIJ>6MHc|DXbk|1E(BoFMF1?i7=T5W0I=v%02ZwUV9{j&EV>+kMOOf@=t=+< zT?N3Rs{vSa4FHR-1z^#2fWV>?I z02VzAz@kS0SoA0Wi`D_KXgvUn9s^*};{Ysr0)RzN0Q02VzBz@ldWSoACai=G2u z(enT-dI5k%F9HIKZj486FhR09y7yh*B#VmOJ40TIN1b2JqSxZy^Owk?*BM?Gy+M{m zZ<1xvTVz@EHdz+ELzYGFl4a3*WLfk+Sr&aj#-a}aSo9G9i#7nT=wkpDeFDIuPXSo; z832nu2Vl_`04(|vfJGYtSo9SDi@pY6(Ki4r`WApi-vO}bdjJ;w0KlS604&-Jz@i@k zSo9Mhu;`U|WU~p9wb0$JepME|Su&6Tti@E@?Xj=dlbp>EiH$Y&~mUv{O z36gcWyV3ZoEQ-6Yq1i4o>ilvR_0074xk46YGrTP7MV3Xq$+D;qSr+vr%c6c{S+oOL z7VSuuMg7ULXeTlj4FF)#&Hyah1%O2Z0a%m+z@k9_EXoC7Q62z`1_Q8Y2mp(Q0nLuxM8R7L5R4(MSLm?FPW2-2qs%2LOxq1Ypr#04&-Y5LmQ*W@M=elGV|P(<3uz z>EGqTsLZJI%UM*E>0NS_EGlMrSyV!nMWe~GXbf2vm6B!ASh6e{N0vopWLZ>BmPHk0 zEUE-x(RctBO#om~6#$E>0a#Q6z@l0J7EJ_T(IfyCO$K1m6aW_O1Hhtv0a&yj0E_kq zV9@~pEJ^^d=s*A#)d8?*DgcY70kCK~Ah4()GxC@Tk`-~yvO-xj+`TiTJ~Qh4au&_b z^gg>r79GU!vgly4ESf`>MRUorXdYP>%_qyE1!P%t2w4_2kY!OL8H<_#ShNs;MT-Df zbSMCe76Y(o2>^=@17OkN04zEJfJH|Fu;?fN7A*x}(J}xQ9Sy*uV*psR9DqeD09bS^ z0E>{Xf;_Dok^BOXOU&m*<@LC4p|nROU9z}09bTB0E;dFV9^=?7F`Iy zqKg1nbTI&nE&*WCr2s5i3&5hw09bT60E?~wV9}KTEV>GSMOOo`=o$bPT?@dX>i}4E zJphYt0ASILfWV?tG9wdAkgN>%zUxzEQ9pN)bW>*3`QK<7QG0-qL%KR`UHSQp8~MxGXNHS4#1)>09f=T0E;#Pu;?oQ z7JUuCqHh3L^eq63z5`&<_W&&V0f0rD09dpcfJHw7u;?cM7X1vsqF(@5v;`1Y^m=CG zJrgABG54{LH)K&x)WWZsQRkPl=+8{=uUlo&Ukopc{wB+!(Emr?dxu9+zyJC(*-SP| zLXr)T1w;r%MU;@xQ4m531VR#01ZxNoiqa$j!HSB#VMoP=z4zWwu{Z1u6|rMOY_Xr` znR)Kb2K}7x_d4hMyMBM1Tvzs)*S%BTGjmVfmS$J(W|2!ai;~D@QHX37C6mn}k8BpD zkjI}f5E&wd*3c#Wr09e!wfJHk30*iic7wUbdSk%9_i1UY8bdcUW>Yf%> zzto~$XIg3H;ej^&7z&iX3@@MvuGExS=5(o7VSzli~5nxqTR@5(e7j{>JPx8 zJOCCA0ANu*0E-F$STqoTMS}oXG#G$ILjYJb6o5s;09Z5}fJGw!ShNQKi}nOy(MSLm zjRIiNUH~i_4Zxx?04yp5V9{7WU{P*bXs!qnU7ai9^h^t`^tb7k85O04)i1SZT$*>v zy=KvPhBu4K$Y#+5vRO2dY!;Q1&7w(Uv#5e>7FCkXqAIdkG?|P=)c`E20bo%r0E_AX zShP0)i>3guXet1U_5ongz5p!R4}eAc1F+}-02Unxz@mBp7EJ?SQ3C*rrUS5O1^|m@ z0W>;&evCCOU^7799(~qT>Kqv=V?t#{;nF1OOJD2*9F~09bS~0E^>O1z^!-04%y3fJIjTuxKp+i>?G< z(NzE}x*C8**8s5SS^ySZ2f(810a$bc0E=z}V9`wgEV>zhMYjO3=vDw0-3Gv-+W~<^ zXQqYr6hWeo>IwBKvuL=U7u}H-R=?Dud(yo9A2EyWWq7mbKC)SKKiMpLfNT~$NH&We zBAZ1Ilg*+>$Y#-_WV2`;8H*kRVA10MEP4WfMe6}r^dta_o&sRe(*P`b27pD+0g z02VzDz@irbSo9(Qi(Ud?(aQiV+5o_!R{&V_DgcXK17OkX04#a~fJJWt0*mfS3mqeZ zMDNv)!`^KcU9CH&x6;Dums<2*nzweHS+tSi&7$|oX3+;^v*<&zS+t347JWoEi#C(Z zqL0aD(I;fH=uI0I=vs02ciOz@nc4So8}3i&_9!^eX_1egk09?|{IfchW*niy+Y(^>+2U z?2Ecf_#-W>eyK%Hy7$H7W|5n2SMp|264@*YkTu&5INi*f*16a!#UX8;y; z0bo&A02b{4z@lydEZPx(Mcn~d)B}J;xq!f;ztTeOpAd_>>HVU=&7w?Is%Lsw{Zfl| zO84@fG>dj-c(Z61vRTxZY!>ZGHjDa^&7$4NX3_3sv#3AWEXpIBMFYrKln=n70ss~b z1Ypr102U1fV9^i&77Ybp(J%lO4F_P+2mluC0l=a?0a!E=fJLJKShN=ai$(*mXbb?0 z3ISL&7Jx-X04yp7U{MJmu&8%>s73^d4%4?3^+^w|^wagF+0yi|`lS|4NcWnbHj5@Q zyjfIEHj5^a&7umjSyV|ji>k3pxXa)d_W&*IN5r9Rr09Z5|fJJiv zSTq-aMF#-_i^iviE)+qcOZ65}nOXFTem3^t^sxG+7A;Ko9(dL)TEy^X(II5BXffF= zY9gCO&1AD^3E3=KN;ZoQC7VUd$Y#-UG8P>Mz@ozeSabvci;e_f(NO>_IvRjQD*#w@ z3;>Ic1z^!}04!Pwz@p;;Sabpai%tY!(MbR-IvIdPrvR|%Q~(y82Ed}z0a$bf0E^B9 z1QyLt4}BYT`w?;_SKt5tJ1^jms)ggy63!L7M;iNX3_a%v*-e{S+tsL7F|d- zi!LIYMHiFJqBUf*=n}G7bSW8&E(2iE4OMb`qb z=sExvT@S#b8vs~zBLItT0$|b204%x%fJL_gu;?}b7TpfOqB{UsbSD6d?g9iBot+-q zNd$?`*Y{nYV-{8EOS5;Uht)5&=>BxC^d+WXZx(GLn?)ay&7#d@v*=^8S@a3nEc%pe7JWuG zi#{itMPHDy=t}?=Z2@4>R{$*f8h}OL0I=v=02X}*z@n`HEczaRMcV*a^aB8kegt6A zPXH|X8GuE<0I;Y9fJMIou;@1c7X1#uqCWsw^d|s|{sIIRZA=f{E`mhc>0QV7&7vV4 zB>bHoR=?DuPIA@|8~_%@09e!+fJI#ZSkx7OMLPhn zs2c!_b_8HicK{ak0ANur0E>D8u&5URi+TeBi`@31Uqp~-xxUppseN#b_N!Xdr+rxc zQj7Yw_d35}7VXOLwlC^OHj8#6n?<{m&7%HfvnY>j77ZYqMfqg2sDNx14J2dHAOIE( z24K+;02U1eV9_uD77Yhr(Fgz*?E%1|JpouW5`aac09dpa0EG^xFJ;9F)< z1;d*~m1MK1ifk55CYwdoWV5J-Y!=m$&7wN8S+qCVESf^bqNxBZ+6RC|`vS0NKL8f( z55S@W09bS&0E_AYSTqfQMGXKfnhwCC82~Jr3BaO802a*xV9{&<7R>=*(Odu)9R$Fl zg8^7H4}eAU0f9vm+lP)5L88a$`>xB)q8s%jX+it2`lS{vZtq?7j#<>i@Mcjn*(_Q@ zHj9>$&7woeX3;XTS+tyN79B=5iw-B7MMsda=tuw-9R04zEkfJJ8ju;@$x7Oetc(OCd2 zIvWsJw5WaPSrH`KLw7%im_@(0mvBz|u==GIUC`d!@}60=n&Hi&3(02DMP#$+VzODZ zhHMsHLN<#oC7VT;kz@jSwSacNti>?M>(KP@px)y*%*8#BTdH@#P z0KlRf0a$bs0E=!0V9_lAEV>ndMYjR4=ym`W-2uR&I{{d97XXXy24K-W04%x}5Lk3x z`%vaavFJ1DOD%e+y_f%iS@bZ&n?;Y1&7w!iX3;vbS@am$EP9-5 z7Ck{Wi`J9Pq9@5_(NknBdK!R5&j7IKSpXJ22f(7|0a)|`0E=D(V9`qeEP5G$MH>KE z^a=orUIk#$YXB^I9e_n|0I=vy02aLkz@oPSSo976i{1rb(R%$*pODR>PswJ{XJoVJbFx|V1=%e6 zl57@jA)7^Ck+JA&02X}%z@l#fSo9qLi?#x==z9PbZ3AG@4*)Fs5r9QM0kG(202ciM zz@ioa7X1pqqTc{m^g95H{s3Unp8zcS3xGv`1F*=+unTi6ash!wAGQx&EP_N&*S9xr zGK)NYIV33~tbVCQDH+~Fo6Vvy!<$8^WV0wjHjCPk&7w52S(HvTi`tXTq71TGlu0&= zvdCBz1z=G&0E;>Ru&5&di#h?YCj77ZYqMfqg2sDNx14J4aIgUDvlV6s^>gp5T)0a!E) zfJMUrSTq8FMSB3SXioqZjRauPC;%4i1;C=w04y2GkD z02Yk{V9|I07L@_8XaWF>CISMBcFhRwB7#Jp)tAotnMHf)%OT|%Vf9Nbs><-je{L2{ zW_Yuxnrs%;kj-)(M$jqH3G0`766N81F&cg0E^}Vu;?HF799-0qIm!;nh(ID z1pq8s2*9F6fWV@PjL>`$B>IECy|L0P%GFmu4#^0sUuw~k4DXCD&7!3YZx$U&Hj9># z&7$RGv*<9gS#&trEINX079B}8i;g0jMMsmdXaxX^jsalNu>dSO4uC}~0a$cA0E

    Isl8#0ASIX04!Psz@oDNSadc3i_QUH(YXLD zIu8(7)RYmrQv`{2)`M8HS=39FIzJ<?M>(KP@px)y*%*8#BTdH@#P0KlRf0a$bs0E=!0 zV9_lAEV>ndMYjR4=ym`W-2uR&I{{d97XXXy24K-W04%x}fJOHKu;_jO7Cit6ELxor z`c(vpKBe!wzR)ZxPLl9oMp*q)iyqDJx_)aGtz&qz=rOWc^f=ipdV*{gttXpBPm;}| zr^sf}(`2*g8M0aQEE$WQ17Okf04#a|fJH9?u;?WK7QGC>q748ndIf+*uL7{>H2@a9 z4#1)}09f=U0E^xNVA0zEEP4lkMehQz=sf@yZ3JM^`v5HZ0Dwgw0s@O3&IpYbL83qC zn`9p`i}npk*pv}gzto~nGQ4S9&7w~k-YoizY!-b^HjBO>n?+xe&7v)2v*;_bS@bp8 zEc%9Q7JW;`qVE7$v=x9w-vh8{8vu)b0ASIN04(|mfJHw8u;>>67PSDd=vM$1{RY6I z-vL1Vv#0|Z zi#h_Zs1pE-asXHq17J~S02XxtU{O~97VQAQqHX{z+7W<7-2qtC1As-j04(YWz@lCN zEb0xwqCNmD+6jO~I|Hz27XTLZ1z^#xfWV?~X6ShlB-*Su8dEcaEB&4H9kcy1!|In> zl$Ys!{i9hlfZ@%ee6m?oKsJj8lFgz)WV2{6*(@4DHj9Rm&7xssvuHROi$(yjXb%7u z?Fqo5kpL_j1;C=c09Z5{fJI{fSX2nWqOkxhDgt0pF#wB709aHCz@l*gEE*5MqA~y$ zO#oogL;x0*1F&ck0E;RBfknG#hN3@-MW5=69{tUtA^rthW?21Fi)u2xfxnnVwG3|- z)sfAjy~$?L6tY<~m24L6LpF={C7VV2kqC)^! zv>1RzO@P3n$(f-kB1m+MzNM(zEV^GUYR(L+Uuw~^OmEq*X3=tnH;WD#kv*;+YS#&hnELuS}i;f|iMaPn{=r{lttps4v@c=A30f0p(0L02ZALz@k$C zSad1?i%tVz(dhszIs<@3X9BQj6#$FQ0$|bE04zEOfJNs5u;@Gh7M%~kq6+|6v>Fgt zv@|nxi3k$yrU$V@&7#`w5-!XPt6yr-C7IqMznevuGQ3%I8QCnloNN|dK{kullFgzk z$!5`2WV7gMvRQNu*(|!2j78T0u;_XK7To~Aq8kBNbQ1uJZU$h{EdVUK6@W#z0kG(H z02bW=z@j?=SacTvi|z(s(LDexx)*>&_W`izegGCd0KlRL0a)}90E-?51QuPK8TwcR zi4K(Ltuc#k)RUw~GQ;YZTJ(6Pm;9Gm^aR73MeE6C(UWAe=qa*U^fcKldWLKkJxex= zo+Fz@&y&rf7sy!jA^?kC0$|b004&-7z@k?GSoA6Yi(Ug@(dz&#dINw(ZvwFBEdUn1 z4Zxyz09f=c0E^xOV9`bZ7QGL^q7MLA^dSI?HUY5cBLEg{1_TzZ%M9%*f<#y8>u8Ue zMVWe%^l@fb{ZflQ&-5lZIs$p$^%o3p7JW%Ji?)!>qOZti(br_N=o_+G^ex#e`i^WC zZ6%vU-;=Ru8vu)b0ASIN04(|mfJHw8u;>>67PSDd=vM$1{RY6I-vLI^FH;XdJW>F^DEXpFAMNzU@lub5^I*`qxj%2f_6WJ`vA!AVt zfJL1FSkwi8MO^_{v;zQ(x&g3gM*tRe2VhYT02bu}u&5^hi+TaDs5bzM`T($KCjb`h z48WpY09e!)fJM6ku&5sZi*^HG(e8l2qIOxKyG4-bL_HNs%L=aaFV&Z3`)7sKFSV#3 z%X>4~EE>r0X3-$BSu~hz77ZbrMMKGE(J-=EG@NV}jUbyvdyvhdJ;_)!5`aac09dpa z0E>jb2*9Fp02WOG zU{M7Ciz)$FR0Y7I$$-G30a>BnMUdzseH|^|ESjXR##U#A)i1SZ?<}ud*esgD@Mh6e zvRSkb*(}ZDHjDNrn?(nZ&7uRzW>G!aESg5fq6PpKO$T7n3;-6*1Yl7k0E=b; zuxK^_i{=2ZXf6PY4gz4&!2m3p2f(8F04!Pnz@mi!ELsG>qC)^!v>1RzO#m!v24K+= z02VC;1Qyk1g$hNG=xlw*Y@J#3V77!qv%>0^T6B1p{N|onbOghjMMsj&qNB)W(a~hH zXa(6UI)-c(9ZNQgjw72zE6HZj@nkGI0f0p(0L02ZALz@k$CSad1?i%tVz(dhsz zIs<@3X9BQj6#$FQ0$|bE04zEOfJNs5u;@Gh7M%~kq6+|6v>Jd#7Xq;8A^;X$3vRQN$*(|!6Y!+QZ zHjAz$n?=`=&7$kcX3-5~EV>bZMK=Mk=w<*G-2%X(TLD;f8vu)L2Vl`104%x_fJJu! zu;^|87Tp8DqI&^YbRPhV?gwDe0{|>~5P(Gw0kG&{02Vz0z@kS1ShNlhSafMt=tU7E zTB$GNUuG8d)enR`mK9dN)S@S|yl>l^MNcujS@bm7EP94)7ClQgi=HE!MbDGXq8G?! z(TilW=q0jQ^fDQXHUO~b6#y2!3c#Y*09f=o0E^xLV9}cZEP4xoMQ;PJ=p6tSy$isi z_W)S55r9SS1F+}=02X}+z@kk6Ecyt5MVkRw^f3U7J^^6Sr+~nsC$d5vGQ^@s^cK;2 zv*=WPHTJWtu==GIZOQTmXPHG`F}zvyHQ6lshHMsnOE!zXBb!BA$!5{_WV2`+*(~~j zY!>}U#-g79SoAXhi+%xMQ40Wzeg$CBZvZU%9e_oD0I=v!02ciPz@onaSR_9JeX*>T zWEYEE02UpX*0bo%WfJLbQEQ$cIs2w1%=!>k-J|akTsJ?suOS5RC zejY6?8dks5qRgmwShiV|#qefPlx!Adlg*+IWV5Iv*(~ZrHj8q|W>Ji67Ih|@MP0~P z)D?h5I{>h#8vu)T1Yl8j02cKCU{Njri+TdEs22c>dIPYi4*-jH0$|b304&-CfJJ=) zShOnui~0euXg2^B?GC`A{s1h>17OhrKwwe(Xy`H#BzmnU;$%dFEB(QG*D*gDR=?Du z!BKBrN3&=M!<$7z$!5_ovRO2oY!;0mn?-w&&7wWYX38Uw(h zLI4(x1z=GT0E>zNSX2VQqEY}BjRRoOcmNia0kCKS0E;F9u&5k>MUwznQ~|)EN&psB z0kCK?0E?;tSX2YRqFO*;(ZFcvQxPOutQYr#%%Y#wqPl2U{ZfneiFzq9vuIz2H;eWo zn??JR&7uRyX3>FUv#6eI7EL3YMGa)LXgb*}nnA{*nE)(m1YprD02a*#V9^`^7R?1< z(Ln$#Iv9XO^8i>hAAm&*09dpTfJKV{Sab*gixva0s0n~Y%>XP~0>GlB04zEbfJMsy zShO4vSTrRX+D!zB-m7QVQ_Z5AdP+Df8dks5qNAc-c^9+jXofe7R*=o2W5{OFv1GI8 zII>x^l57?oPd1BAAe%)elFg!%$XIkT0E=nMcBoe99ARRAnH z3xGvu1F+~E02ZAKz@qa2Sad!Bi!K0Q(P{t|T?oLUivU=3F#wC!0I=v102W;e2rN1x z8ahM-iTJTMRxv07Cj2UqICc)dJKR?j{~si2|!@c717YWB1p7% zx`?yZELyHNve!q$>X%ydOw@aON3-ZzhBu3zBb!Cflg*+R$Y#-tWV7fcvRU*p*(};X zHj7>%n?k02XZoVA1;kEcyU| zMIQpNXcGX7J_2CTW&jp_48WpK09f=X0E<2YVA1CQEcyZvSoBmh^rr|C-DL+6=V`NO zX+*-8(XjfZ7JU=-y62ij-!i;e^c~qO+DbNyz9*YS+sJ0o4`j3GN3vP;6WJ{KnQRvQ zLdK#N02ciUz@py(SoAvpi~ay$(VqY;`U`+Xe*>_{$+pXOEOG%@lmx({5CDsk0a)Y# zuqXw9MPUFIr2?=h0>Gkn04z!aU{N{%i`oMMi@u76ibRm;8Br1EYqMyPz8sQ~9ag{8 zqU>yMW-qg-1H+p|9m!@GgX7VQYYqV51J z>H)x_TmTmJ1Yl7w02cKIU{N0c7VQMUqMZR)v`U0?MR{$3E17Oi^04&-afJOZQ zSd<6Aq5%Lb$_HRk0RW2z0s@P&vO_0}AkhhW*D;!Hujz|C-k|KT`lS{P%l2;QV-^i( zc(Z5(*(}ZFHj74*&7x6cvuH1}Su~n#7L6gBMTKN68VkUpA^;W@1F)zBfJLPM zEE)&EqVWJMDg$8A1OOII1Yl7)0E;F8u&4rnMU?<7ssdoqWB?Xb1F)zDfJLA)SpX%xyf3~-EXS3)4hBu22B%4L`WV2`* z*(_=xn?=*fX3-3?Su~Su7B!O1qFH1tnhn6BIRGr03&5g-09bS|0E^}UuxLI2ixvQ| zXdwWL76Gv65C9e}24GPW0E?OdShNIyMN0u#bSMCemI1J6IRJ|e17OkN04zEJ5LmQt zcBs=XV$leFW7>XZ(KGs~#v`-C>X%w{Otv?4SF`9?hBu3jBb!Al$!5{0E;dIVA16OEV=>^SafuDXg?7o zdX+?Pg;{j2ekIo0?6CUfbaIls-jQo|cb%Mpa@OtS)XLYopWZ1l-+V}k~dK1=4_L*tUfuz<-@mqbB^liIJ@VpmzP`ebK33f zID>Pl`Z~_=ob&rR&d8jNyF1R9oL&PQr#NR$f#ZzNxn+>!l;`|7#Br)}_89IswK*&H zaGa?*PmOe({d3YsJI=J6>O#kvnX|gcapvTFP~tfAa{7#SoJBbYO>ms%oZHGBXIakA z6^?U6&dAA*vm)o%8pm0g^Gu!NoRpI>)p1VCsomFcR^?o@zvG;nv*|#`S)H?UgX65p znK#36F3-86(Q&TIX_@Uf*X8VWkmKBxvvQu}+?Mm)0>`;4C+iT$xi4q$CdYXwXU!7F zS(mfw zKE-i9$(eeZ<9v~G=^2jmb-vy>z*(0yoz2N?8YPY~QP8CAhK6ua&jn#y-1VR)ZVc{U%utZcKm8zKv{c`kaZcM-3dZruGuP2`4#`ODT=eaTc zg3v{7Ouyl=*^TK}^euB^OE<~tabx-=Su5O_e#_BHH>O`xbCMg=?-@DGjp-Lfta4-e zN&j=*n0{1ywHwpV+OBb9`eDh--I#vb?J75>A6L50jp^r2ZgOM#fq~oHn7-rtE;puc z*}cz=>3c38a%1|Yxpi(#-}SWKjp^G~o^fOPzJnLsn7(kl!HwxFf3LeSed*?HH>UUA zH@Y#sdAiAs>D{kS+?d|J_`;3p_2<`aOfMj|x-mTi{Lzi+A-u(n=|1=m*GcOdl@05v zV3X_oRCigKgVH*OWu?kru_tlOv;nTuWua_a?x2yo%QNkQC!H?Uvi-P&4$$ZK6ILnz zU53kV&AWq|wLe*l&W-Zlb)8%$yF)V0lo(`Nt-ar!scEQ_Og&HCp7M83;D7?aK{9p zn`~{)ESZmW{at5Aw<;;M*6Ai&l+z^ar+}qIS6+SBLx=C^PWIAMmj2aiN4Gj9`t}nq z{w=5`C3^q2PuzE;(|wT)v_b~zCL4r5#_YV-G2UWh92c;Z=+&#w`tk^WjM-B!n(L48 z&#$k$K#-2{>(AF6<#d;A!Z}^X_>zrrMliIS?{u3cGjx$WcV2+J^gZ^zVv0Y$6@_OF zknwrx%ZJo=mC^9DA5Q%%DLJ$}rE!+a9i!hULq@EYFnaSsy<0 znLnq|Z@#=_vEQ;+)*Ud*pV1$Fe&+eZoF3b380p_j|1{^psNbx*C(>jA%ZxOYUYg>0g%IK)wsva?^p$!;iPue3DjE9l#m=TiI1z}=(?5x+w=t#*Eg*qUbJ z^@8!HXUY_HbnQF1X=$xv$Y}3`Qki^OTKly0wBa(o%vhVgvZSwsMn)~#xU+4P617ns zY?S`9t)uK{qqM#{$v|FfJ965~T_De5@;Lq@aV2Wye#Fb)BTnXN{HZw!1vx=o609gMP$? zJZE&5kzE#K_$`sPJN}>R22~#SmVei&(z1u{3!EuhHi~%3&JS+YW!kk_{-qx+y8jEF zh>u~rj*wu{SkiVk8rYa;NK$(L<6N^7pnrSw{@MMvj4 zwOWF4RcrYzpjsGLb$nb&a!_HmQ>7!x$-iu0sr$=+$Vtt;>;~z$DF|cYt<=6~O*iR~ zWg~ww0sGVGB>pAlZ)ItRoL6O#B=>hQ)s;W#SN`3+ya9_F2Fz+&G@xnmi~)=5n`SiD zFIv2?xp78wI?D}_7~WH!NLWN{Tmym&+T83pEsz#KAk5|w|Q#7+yyh{ zEt%OkV1C1lIdd2M|K5zINQz6gN*g z26!D(I_zm3G716mjMTlHq-3{~m!>7t>#0S!A9c8aI-J+1hu5=@*P+}0$?%<0++5Ea z<#j02p$9PCi8g(C!f(eYKlkkAW$!Ni<^NZ$lCgT;#MY5+Ka%eM-H~LED(K;L$oI1M z@;Zc;OH2JF)1ilT=pyQAO{M9YJ9uq+37*=ikC#0>7|``1It!h>%wWOpWDC}hdH$10 zvT*wfPLf%PX$24XKg6DnB(yXy7@M4oc-{QbE6Ua`nHe9rUT&zp%&G)8r8nz7*N?XD zbwLb_ucAN|e--u8CCd^CR+^V0E7A3KO6e5Lw2bnF`@!?ea)TM_ z`;X`SrI!2eIM3VBpI4pv4%+oUG4sK?P4M-9Xx4}PV;*eQZPEOPS^tm1{7=n#uvM|C zQp>%bx(M3Z^Dldj?39?-VOKAANb8ox2)C~Zg2^)OrK67TliGNxJGHo%H^&7H#y7z0 zE)7c+BT_=`N6z+gbj#}L?Ue83>?o|K7ZVUkNgCWSn81IqR3^|zddvysig}@FvXo_? z5DYr%|GC;HrK6YAT^50@6kBF}{I%}}8@ev=fx5JNdVS){S{MF*F_b@&++ZBKl>5kT zHK&Jk^xWtFU~Jk3UH_3#Zl2dAG)-I8(?|~`4T+??lIg8Pj+pfRf7jVVn$R^E+5a1z z!8XySmlsn_?8yD^nz)0#tk4NZjr82mZ*HD0{LmRk=gsyvs{hsqvIfeaUpaXrlXjHz z`_h`K`jYDE`m&0>3(L!j>kF&L)lDj?sC9T^Qb|os;kc6e+RDoM^2&;FPIbw+`hvou z@$o*2YHR9b_@c^5RplkM(q~;one|s%G`@a%YmbH1#q|}HwbFAWar~JHRWj1L zikiBrs!DyLzN&0$NqK!~W%Z=O+F*(@sq z;fWKjsI0H48(ULUU8cR2R@PM%`@IbtKHje*+BCDeq^7D;S{RIJu=K;S(6*OU7uF=S zoaHvDW?cQ)y3$e^e@)rGCGkQ2F=u6ybZPqi=#m_ppV-i{iuyVxJi;1RP}-)KqUwFB zYAa=y%ggJlD$6QrOKg@0TK|Po<%D_A!1`u?4vO0hKDJ!Wma9ws)lgDVD6!b7EUl?8 zEDlC9#P3^MR+=#5CAH&OzV%h(_ocWbeNoBSEn5#<)i}&$oW^5Z_t7{5nMEO+@ErNWmQQ<{5ez}TU|D8d~Jm+ z(fXQ_+FIR~nRIDU`9#0Dg9Zm%&Jcf!{>1Y^{>J1ZQP|eiaC@>q7GHd9Wo6Z+h4m#x zMfC+^%WN|*YO^W&yO!dz!g2MLb+uJ>we@>fmeC;b~bBvPkMnrWTcy6el#< z7KrR&YYSx$F|lNy`qIKO-O5>q)`wm;OVcXrs-;7=vC{IgqSn2>Z>jFg;)||eV0;6Y zP2H(n(p=oo+)!WJxGdPs6v)OnbIJVq%i|OBw~dm@vbNh0&5(Waq{?btH@eddHt2!= z)-rG5g4wyU2lLrrnU+8E1=7K=vOsGpTaQ_K42VBxJK^e*@)CbXtpk^|l`2^6x&UO& zmX!ueD45F7gsJ#DAzf3tyYmli*2*>#u?MIxEGnw2E-bSBS-d^t<)AmEP-e8YY*LA= zGJhPyOwibn@>7LSv!f_lPoIsz2%iPwnYz* zPf%7vums1_QR1)grn$2hG|tSG+kA`TlT*1XOJ#H-N$dW)b$?J)R9Qb>_EYfzST>U? zi-Xq7DM0+mqLT9Ry7IzmF@9WGjmWLXEoKC(*Z~A>%$LFaS!}Zhud5mBAG_;o#>|h*nC)92?zH! z;{5BOt<{_I;!1z78b6ZQIu2He>||_J78KYKOOD|21<1CZUtc`Aw!V0La1d{M#2=c_ zzwM_c$)2dL+CMh=`@&LLAT{F?cFDL~Ubv5*KiWZ8x?~qMYsrEc`GW^JiD|I4wvC!` z$G2P3to4L5;BwgpTGu;MA6GbOQeo@V#Y8#5VsXfp>QA(FYc448tr%BPms>PqM6TX; z&nw8)8}IqU2M*5dySQ;)V?$HpuDSi^&sel%)Qp9Tn;Vz)pFe1jfaW<%=1-S8Yu>_! z=KgZmew1wcGZjdmvlcBK(!Xg@|Ct3tg)}UlF=v$A#$P(T|NOl9@pVE9=t;Z30!u0?>txsC``Y&OI(}r5Gql37W#wi2ww@yA z%kH*pfq>*tooG!OX^G{wM~u*@?Dp@w(Z>)oV3ajxw?@sFkx#J#@!=U@iKWMXf7W zwyh#L5g1!2*GjfC)n?0Se$f13t;Wj%K45LHN%V?A&kxGvk{~#f2uVB?ix&sulxwwr zX-u$#t}ZFkRt0CG1#->l57PEZRgW*Nr(AM=by34g^ith$;KRvO=c=#sU!@br;@U3@+I(lZN1`)U#bqZu>==sOf}e5 zmrSZkxbiB}djW|D25ooZh2!`sa=W2uqUoc!Cco>6z(mq>$PwEnS_N}SSMH3 za>|u>C9S7PEV{s)adK4>oU_EA@O9Pm(#i_m8Tbd{g8%Kaw&BQSnhDf;b=LNxOC5}h zPD5&{%IfXnS=R>_dxi0_$zGok>nV;+L(X2Ut3Xcf z1SaV#q76|^%H;HOUy-4{US1$=y}3~!=g%?$|B@ko-M|QR&y}bc98pROi{(ztc9*!m z1Ul7m;(GkFr1j#b*bamRa;d3xHX{6$3@v~AlRs0(ZKu2}qriflvi zk;X5_3dj2Q$Kp>UEXeAT+J8M$_VHipu=MOI4v9 zUHrb}7!h>H_SvTQ;Fe+0c)6G@DffGkYuWhd;@eBPB> zUV&LFTgN0<=ry`uZ1qxm`Pb7@R&JZSaBa?z<7eDlV+NN*ECpMnZMRI;mA^dX94J^G za^aP*JoEskS0D8?Q_5=PnS`SyS7-&T*ZKvrXLg$A$XQYRT34^f{0Ybb*zeHmF9pG6 zlK)h~1|{dmtxHJn!TL8!^bAC94%Ck;EDP?;iFfhdSU7UtUsv9Ga-q6&zLI!a8oxg? zkoz-w<;H?yWO{z#9OUo&w26A*L@$YF`EuX0tVs4DvQMw|ms7m28o4}`%XzzGXSpT3 zN92F%oe{;2)0fQlm#AKZ(Ma7C3&#d-1^0$|hB+*iYb&`7tuHMvtZ5yNXX~oeY`wnc zw)b|IK=E}`R9e)!UJCT?GgGp=7Qr#nU(vy>bL~vL1MOdg;VQ`Dr)UuqW6gZC*K&v`-=QG zgs^Pq5ULy>&{f{iC=@B^yMMY`_2hT1Iedxb+bCkNsDHURn6# z*4wO%JF&^7W#w|Fmw5A_^<1Z>rpR8@X|o*IDzIE`joK;5!r+|WF9U-^Z<{93fcXAD zzQ7XphV z%Q|g)*EQh+Np9Hqi&;(q{;3o*A^TA|%-KbOy#&LR)vz`LGK8GzirvL>j+1cm!;|qB ziZ}=dS1tas(R-u*l~=Ix^|mZ?leqHRys~1mSywT!qH;>G6u2eaPv|f7%8UZrIvf6$E!% zb+o}X8O@WM|8_>?pRI8J-=BWM9^YgRPNCvAEoDpQJji6@WxaynUaLPEy|w9g1gGCj zS@-g74`A_4FmbC1S|X$Hx8V5lC@L?URF!b_4;Hh&K&RtveWj}P0-|7Wd`HKoQJ^<3 zgQm6Fn-o^bdHz(nylx|TLi2*<5Ntfm58HqWEUyV~f4|Z{*D5X46Pe%!L3LAu+#eV` zY2nNz^BNYHEL$Y+30=@!+~~hKwPs1;iEc1C#;6TWxO|ZVuC0XN;Gs_k*BP{|DmZzU zn|krZ=j$Z97H;vhzAz%&0qZorb`wQx-4*Li?Zg+FSOCFd@fWKsa)0@@y_#qpg}fHZ z$sdj7dakCfMqb{s>*;^o*3>(i+r5O5c-tkv%}torD@}PR-CiBj=IMn{{Q8XP>#2o* zX#2NoVRcL8Qfl*9Aa};%%a>&l+#^kRXFzaK;xC-UQ(gb+af-a!tFL!g+6%Ze zDY!YWul8+!c+kV1zCO!i z!it3ZcDi=j-iryYg@Q|iHV0OJ9$W9p2CqBNu-3D{Hdj76df8CwWVUFVjwZNr@w?b5 z2e&=z>$$vU#0mTO@zoP$Wd++#nXLHM`*%|c=6*i@^dZHaH<0lmb!TnWwm34 ziuTCutM~p37thZvnLoX8=1h4Buax2wB@+s*Bs)XSAmK>gz{5hXj{>nGgef1&t?Fai{^ zk5te@NZ*;B@E4MIrOOBH68@5%EJ>?^Phv<{@ch<=kAMS%&mpzzB%eW*wziYcJL*Rb+sUV*R%;c0gYjFm%13~nGrqs9_jX+z=P;|E zi9VXw%W7{YpMm_=s;>1US(UndB*{Y3wWL)>?N=GZNsw6Ag97PP;iR!3PK zYqiR1omKf9hTs1|Ru8dywAGbXS6RKr>U~z_!@U0R>#gd1>hw2QebeejtDCKUVf9<9 z@?l$lxZkX*U^<=@tLawtD=U?Ew%XmQel>yeepd6X4z)Vc>R7AetyWmAwW=Sn((z2Q zI?L)jtBb8JvwD=(l~zx&y2|SLR@YcvYxO#-w^+T)>H}8SS$)dt3szsV`mWWFtbSqj zJF7oi{nM&`a8~Cl&1$yQE>?4`?qW61>JY0Vtrl6GV0E(9saET)&ayh+YO~eDtsZOj zWUIP=)b?Fq^-`->Th(te(dX~9`heBPtUhD)Wvg#mec$RQR=={k&FZgKWk=_aKWsI_ zYA37RtoF9r&uW3y;Z{dmEwwtyYOU4%tWLK&*Xkmxhgv<#>hV@jvwDuzi>zK@^*XD! zTD`~W!&cW@ectM;R^PF@$?E4;zqR_4)jzC;WdEe=p`F#J)y`IXSl!ubf2)J7?rC+b z)iSG9R;O4!&}yUAc~+aO9%l6zt0!4K)9U$FFR^-+)f=teVfB8i>#RO)^(CusSk;ei z>U@7}b&J*St+rVG+iHp&8@2!TRy$hV!D=t7yILJ+bx*5$Y}Mf>S>4-ez12BZ53zcf z)#I$5X7xO)ms-`Ylh*OxX7zrnk6V4->g!hDxB8jY@2s|1b>%>%<7;QNgVkfKf!vHG;t4OZW=y4mViR)4hm zr_~hsIs~21Osie2_O&`vPQ@m3F%W4GpmtgeugLd~aHT`R|I&9_)xF9&$d8?1gN zCs~@eS=~*}F*FaidWf7;XgjlLdA-#?<K;K}ZS@uTz_#}Hfz{aPAosC)Kw*#%vU+7vkZ-g4Wl4~KwmM*Z zkVjfwG9k#vT79rQ$j?}HD}$V2b=>42*IGTjCde0AeN9fdw7r|Gc9|OFovqgI8{~Ob zuiih%cUb-Ez#z9+EocbxURDpC5#*ItA8ritb5=uhf}CZw?4Tg;ZS~A~L0)6^jRis8 zY;}i2g51|?LsO6!SiN>hknghkjhxi${QhQj&|yIyV|DovK|aCiqelh#1*_gMLC&^1 z@wgyQwR+a^LB7=LTPFtj6RSI(66AhXXPg$~MOLprBgpqy{ccr||FAmboFI?2diZ%k zKFR817XN%GN`Esl8Tpr}ltoFDv$h%u@ygJB>t=@QTkngkl z{q;fq%j&S3f?RC%$XkMZiq$7>3-Si5kvoH&W3}?`An$MWynBPZ*6Mrr2l)%DJs%2k zp4Hip1i9Jj&Fg~vfYl!!53=(_P)9r&)KaTQKON-LtUmc{kYBZ$_Ck<5Tb=w;kPoza z!G<7TW%d16gS^FR?>B;+Z*}flL0)S0)^~#Zkky~w3v$xNpzirWP{&(6W>b*Qu=@1o zAir+4{ii|hYPII`AWyS;;g>*NAV$2Z;T#qxC&ny<6^QF4&KwYrOZ z>ybV`*y?=w`XkMUS-n%f2TAiftG~(@B56*^2q_x88wYvxTE~}4f^&ICV%kOAScbxaFZZ`gnKdWR?oJ2vDM40UT5_ttL+@| zS*DX=wUgB@R&%ZPv6^Rfpw$sp{re{}9=(U9kceJ+PZzb>(QwAJIR%3;WV z{tT<YV~icAvc(=Yl=T3S(oG7CU+RT_f@mV&aHqEpC`EJr!0@%4=wDUOadDl4cq0 zfA?<(=}{JM{EqJ6?FN)Z>i_kWN9`{ZL}&Z{^f~?8MgCLe|G(-lU;5d8x`|)>qw7@v zc9;K%{Ev};{X6$y*O?|&E;-~bZ}6|vYmk51Af3)K@!)RR?)anY00D{P`%%U>MqJVH zsb4xy9p8NUXBg>p`VVoPR}ui7x=qoo{rx33_eLZDIuDoU5~n-(NSUrYsnb=?bah)~ z80mC|4R@Vf?XW+d(``3#e9dyxPqzylUz+?gzAL1gVWiWUBIDEk_~W@t1SF1cWy1L6 z@-RL=IW=oDzS%OqZ8|~wV|=$tP8{F4GCp0d+P+Nrr+tq~w+^E|=-)oYt~0bx(5;X9 zoc=#&mHy70<2neQxv8>K(FT#NtdboK8w`A=-$nuPi7AkWdhPo!I1UL?i; z>p0hK^V)(=SO2uKt!S>2{%#W(lWyG~>G*WH>onOmq*D$yu5*sx5j-$HQL;^cH%a?` z{Fnat!lI#h3kT%NU%{~ap~LeB4j(vNy7Ti35*~*R9qgw;gY&h|Y3+_KDK8DaPm5{y zZL{psSNg5-f^EI8(?#~E{l9Ffe5~TlmWK*DZ0(UcX6v%!O18N(o@!Z{Kc{!Nw0&vE z(x+Ndk9n#kx#0eZPql2ye^a`g-F|;}YVSSfJk{d#)MxJWpSexO5T!OFKJ(=(OUlybT-cSVH$5)%Flxf9HV?+`(pPuf60uV@I%Asve6UAjMw#E`QwVv4-K-^5BXuP+`s?6?ASdg?m1y(*+~D{ zte!~sI|2LEx3|JZMy@)4WltANLBa@-Y{hujr+4s)Mv zx8ko$7r$T8@s_0GmYcgRIPsL!q5bwd?ym{%`HN0UPEB?~17&;4bjF-`(x#;2Pue6K zox9@R6Sq1g>8qUj+LKcbpZoi*AKx`LX57v_cl~tNI}Us;(meKc>Gv4d zdDJ<`pY{#@;}-w1-+aH7{^Je);}-w1-vXcek2m;_Tl~j<3w`cC-rzrO@gLu4S&^&H zywS4K>Pc2lv%1RaxmH(OU1Rlft5;dQ&gxB8Z?k%r)%&bIWObd@^;Vy;`hwLBR$sUJ zw$+VRH(C9}>K9hOwz}2ok5*f({*hbxW5p7k_j4y)+HlE?Ct5Z+U8Z%2Z%t=Zyw-5% z+Hgzd|8cYb*lW7a{l~Tb<7WS{*9@Qgk8AzM&HiJrnLhU) z*ZPl}{l{L7KKCEj`j4Ca$6m91?mw>eA2<7ty=ME|e_ZQ7ZuTG7ixK+FdNCrXCs{qs z>ME<}T3u~*jn&JoUS;(Q<{iT5YlVM{bu1x)&PLJ9EO5a;!UN?t969ygsJ%;V)Xwlw(Hcpes5tdqQ?u z2j7D+y}b!f`F(DbK0j<3xgzLC_Yq$oc)^<6oyNJ{ell1s{@r0|73<>Vo&mvm3+JW2XbO7^~%liN_foY^E*cA4g* z@SLuaQoT}zso@QB6`Gvv=|@nKlEY0hqR^YNy9({zp-_4cRp;vP9c!iAJ5wG~^dWqq zoXUlhkC4vfi5dF+&Z+D4Bq%l1QTA7Azj7zG|D6`ng=ZrKb+hl~=1$d&&7_M(PROW#^f?t2}0<=1HH? zR7YM%$WASineCAJn_L%mOzkR{)}2znk$!Sg@0ClNSgO}st^-qlms#zSdZ(Oxc1^uV z_ztP($)fC*dR`B?Ta&8SnLSefkY{sKm&p`+rhX-3?v+{~W9yyzxAfU3^&08kDfN6A z+sxF_vSb@myZ4drJx?9e&2gSh{ao7oTIZ~Q(jvIMj7U;QdBv}^M zd2VDkSw`o(k#w2S3*1OV*5_(B^0v(Ug>K{y>GL8t;z^S(b|ZN*S3kOuuF}|_+{n=~ z_|In$&tfkx!jfQvHlZ^9yFS0`X`@oCj%cwu}BBx4QHhGcvq=6rK zk>#?KHhYohq%9l5kx{b9UkOLvmBC*PN92OXc`Y3ISyuV$;mG^aq&LEmXJtve8IHUl z@U3uUkSw#e!;xMx)9-{Mo29w;rA77>qwi0PY?aAAkQRANrtn}|?ti<9E;S-WSe4`W09Dw@Izyf zm169&SmZldg3Du(DzWvjSfqz6rNd*9Dbmg(Vv%2E9*&GfMoR;aibWog!HO zSz98F((2h;+C47MEsDBMyXR$Q4$+SNW!S~qv07GplXmPP{WNRGJXs@4wBrm}j7zoS zN*T)vS*7j%l%9{#j>BX;$7;uGvLKGrj-z|Y*Ys=04zga4*N!!^_)pM|VKNUVYR6WY z(X;BMqgFc3){Z7=?K#?!DvR)3?f63G`#kL!E|XY3LplzZMR%BX>?89eyG*BDkt`zp zlI3<8vi6g-qpM6^-|^ROn6xKZJBnp4Jnc9@oRDu9ciJtJH4)a1Od+Y-alK3{q8(YX zBHC%k@zRl|9d}AU>Dn15>-N zWr=mrj?qFoYR9*-?R3%(ePe*Oy4^}y1#&M{mWDJwNjv(=B=miX?PkkXl&l>xe=--+ zp>OX<(GGn*Tl;Evx!C4v$1P%Ql6LGU&CubTw4-E1$qU@j)sp4-x1;oto_wZ+_Q~GP zp8jx0#@Kwv+r@tIt%t+{$LnjcyTpNxx2we+B@S}Deipk)9PD_zS=>S55XalyVpoYn z<>t4=E)s`1UY^Cy5{En90E;n+BOEW^VvfWDX;y*dPMW1%11)#dEDalExr1hD*15$^Xr=tUF}0_Qr(=s#;>mL{ERz#W$qf1~o$_ zSu{f`ESe#e7R`_t@%NR1tGKS2yj3IL@ zW5`^~7;=zh3^~|xU`SbLsjUC3J7tgMO$ZFBlYO~2FRbRMA&Wfy!5`m{Lu^npWU)mv zq{*Tg(rnQTSz^%)S!&S?In<&Vvdp3xvfQE>a+pO7IovXa9AOzljv$En~X2@k0G30W~7;=SW3|VU#L$0)pAy-+( zkgF|Y$TgNR$4Qhrw zWYG+H*rFNoh($BxQHy5CI*Vq=V;0Sj$1R#6PgpcV)?37oCoN;hQvSEMv&umIFiH5B)9cKWm{}1bH9$hC~n5ZpRI)I{J&2$?}U1auDjE zS2Lb#L)$M}rjYFyEyHB{MaxvO{i0=rY`eZnMSr>v`i=4FIu)I+b>#XkoiT+ zOaQ-VnFZh%Eu#Q_(J~vrFIsj0@Qaom0sNw6Cjh@_nFHV#En@(F(XumuU$pE3;1?~s z0{BJC9RU2IWj6r7Xt^VRU$pEF;1?}>0Qg1ATmZjl*%QDoTJ{3)iFs5 zEE+&Ii}J~4Q32U38b~&a29dF7FaV2&0I+B%0E>nJuxK~{i$(yjXb%7u?Fqo5kpL_j z1;C=c09Z5{fJI{fSX2nWqOkxhDgt0pF#wB709aHCz@l*gEE*5MqB1~W(JpT2R1qY4 zsoe4L`kF(E>nVQMns>MFfeSBzNb$NoLWN zvJdhWx?%N8EoyQ-{fS)PqGpCSitpZ@tSpY0L8-PXU00N5+aYHdVm_<9u-Cl38S+r2kqR(~1 z>X%xy+V%7&mVJvZWO%daBC=U@G1)9yLpF;pA)7^)lFg#a$Y#;yWV7fBvRSm2j73)h zu;?lP7F`X%qH6$HbS(gjt^;7v^#Clo0f0p}0N02bX0z@l3KSad4@i*5s8(d_^% zx&wekcLK2JE&vwY4Zxy%09bS{0E_Me1Qwm|h7J%xqU-g%=mN8-#lIGF!|In>^swt4 zC9li)7Cpl7X3?W$vuGXJEP9M=7ClZji=H5xMeE6C(UWAe=qa*U^fVcZo&jLdvj8l5 z4uD0^1F+}?02aLnz@nD`SoAUgi#7nT=oJ7Ky$Zmh*8o`bIsl8_0ASIZ04#b7fJJWu zu;?8C7QG9=qW1t;v=M+s?*jsh9&|%jiXhSFRh);+qPOJ*F7E?3tbVCQn_W+T;@!9C zV}>`2J|UY$pOVd@&&X!c=VY_!3$j`CCD|<6LN<%OBAZ2Dld~Bd#%0p-e;fl$3DJZn0(%udy>pt37O0!d?irywLsA~0!7~n6n!U9^u0jQ4+2F$ z3Kab$Q1r7v(Jul;zX}xnCQ$UdK+zupMSltu{UuOTsQLR=e#hqfqlyAWH9}R<+r`o+ zIgrX9Ii>6!iqid4rJ8c`l@yh0verw5qLz*iMXl^m)Y=Y3b#^FfV~3))b||X1Ls2_B z6t%ZQQN^aHgFsP7fuaQjiWU?oY7i)D6ewCqps15T(ZT{niwG2T7ARU&ps0&L(P9Ec zT?LA|2^1|ZP_%?VQFno&B?X_0mJ%phTBs_@YD&FwAeAHXJHWHrn(8h6@AJnOWXsf) zldq&`g_>;4GNGu4<3mwTI~4V@Ls4%#6!oz~QC~Y0^|M3KigqYk$qq#;+Z3%LP_(K* z(P{!ks|ysZAyCv`plD5jq5%R$YY7ysEl@O2plFal(O`k1Ap%811&W3V6s;prG+dx) zgh0`{0!8Zy6pa+Bik7P>?U)0p^vdt)%$5&DFXrEn&epFfCtpd?1~u7<%Y~w`jt@oS z>`*k`4n-5}P_&^PiZ-%C(Z+Tt+Qbe;o7$mhGn=B#1&X#1DB4n>s7at`D}kbk0!3R3 z6ipH+nk-N>MWARKfugAbMbiX|rVA8pD^RqZK+z0=qU{BWW(pL|5-6H2P_%Q?#!@(S8C&`wJ8uAW(FmK+!=0MF$HM9U@S4s6f$S0!4=l6dfT@ zbfiGhQ36Fr3lz;4C^|-<=vaZG;{=M17brSGpy))Qs%TzKsn{b|^h5ft z1&S^bD7sjn=n{dVO9hH96DYb|py&#LqALZ8t`aD^TA=6}fud^#imnqVx?Z5@27#g* z1&VGGD7smo=oW#ZTLp@46RL_%sVS|K1F3A9KQbdbH5BcX{(8H;rks2wMR(U^)B1#> zdmJB%?zKbFeRe3i-ws6&*rDh_I}|-+hoXn=Q1pl$iXOEodQ70`ae<;I1d5&%D0)hu z=xKqXX9S9#6)1X6py+vlq89{;UKA*LNucOufudIgie42cdQG6{b%CNc1d84iD0)kv z=xw2@=+2tbkvWjcV(BjWyF$@g`B&B1J2mCxD=GS*CcCm5 zMGM#zEhtdbAW+mOP_&RhQ73_-g$0Th5h&^`P_(E(Q5S)t#RQ7F3KVq{C|X>gXbFL$ z?gB+i3KT6RP_(o_(J}%>%L)`NCsY-+ER{N~oGTicZrryjRd4CHsmaIkrE>C>6!j`) ztFIc0dOJQ8^|3=yUpo}_vqRB}b|_lO4n-^5p=cF56s>B9qSb7QRu?E*L!hX?K+&24 zMFRwi))FXMTcBv5K+zz9qQL@1Lj;P33KR_!C|XCLXt+Sp2!Wz?1&Y=aC>kkHw7x*m zD1oBULRC?ZQmH8iQt6pK{qzh)Jxci)Qz|E4NzwRHw$JLJXoBNI(S~*?+Q<$?8{461 z6FU@bYKNlD>`=719g4QFL(!HtMNI-lTL~0R6e!wSplFgn(PV+5DFQ{?2oy~fD4Hfv zG+m%*TY;kO1d3(|6m2h1G*h5xmO#;LfubD*islFu%@rt`CsY-UEtM|FfmG(^Kctk6 z3q{ALZ$a)@Dkon_(XOTJ!TzCWH^+yf-R)4chaHOcv_sKeb|~804n_Oep=e(_6zyk+ zqWx`(4iG3hP@w1_fue&2iVhJdI#i(OFoB}O1&WRkC^}N0=qQ1rqXmlQ3ltqAP;{(7 z(QyJr#|splAW(FoK+#D8MJEdsog!2f?OZB-mIJB$ksdC+ODMW1DLS=OPQH?&GfP>U zwL;NZjt@m=+o9+jI~1L3hobZBP;|Z>iY~B2(S>#>y2uVi7uytFB2aXxK+$CaMVAW{ zT_I3(r9jbD0!3E~6kQ`wbge+qbpl1#3l!ZTP;{d}(MB~bLXK+!t_Mehm}y(d%^-BT*`?Tj9g4oPL($iE zDEh_@Mc>*KeJ4=#y+F|q0!2Rx6#XPn^s_+GF9Jos3Kab&Q1rV%(H{aue+m@+B~Vmo z5jWc@Dhd?U2o#kBidqO1WdcRD0!3wkqLxBc(TAnd9XXK7?dkDFABCc$(>)-qT9lKo zq$vLxk2i;gqI$=NqIPyDYHx?4iXDnN*rBMS9f}sPL(zhEC~B}nQKL=KLIOpd1d0|G zC|X3IsIx%Pq5?%-1d0|DDC#Ou)J>phae<;G1d6%~6fG%Gw3I;6(gH=x2oxv zQIj2twz5OfM4O_m1&SsK6ipT=nj%oNjX=>+Z{3KZ=mP_(m9RWzYR>F69tWp4U{dc#mOKPlR!MLGFO ziuP!cT|F`s?dkYXw3i)<_O?UOK6WVD*A7Md*`a8EI}{yYhoS@RP;`(@(ZK>mhX@oM zDo}KoK+)j>MMnq}9Vt+Blt9tZ0!8x$ijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlLd-S z5hyxUpy)J#qSJ+{qTO1QUdVw|e#vLHdnj5teGBr87UkqCDLSV`_T#8fbgtt=(Rp?# zI^PaO7uccbLOT>)WQU@Q?ND@y9f~fsL(ye6MVAW{T_I3(r9jbD0!3E~6kQ`wbge+q zbpl1#3l!ZTP;{d}(Mpy*kFqUQvPo);*3L7?bGfuffLie45ddPSh$==vzA!eP@TF@9j|ZgH6$o z0!2Rw6#Xnv^ou~zuL4EC2^9Sw16Fo7PLcAgB^+*?NGFk9f~^Hp=e>7qD2IXItvsnDp1r#plC6HqOJl( z-2{pj7bsdnps2e*(UJm1O9>P$El{+KK+&=SMau~kEiX{CfkRD3KVT8P&7lJXnTR8nF2+#1d3)06zw2TG)JIlu0YW|fubD+ zigpqx+F77z7lEQ(1&VePs){zwO1tJjDu<@WU2hVKZc4wsYWJ+1d?iJDXW6NnhoXHP zABy(1L(zVADB9l+MF-fS=s-IZ9b|{1gY8gsh#iU!wJADGpy+Ucq9X)~jua?5N}%Xy zfui{WMaKvf9V<|DoIug>0!1eX6rCtgbdo^P$pS^E2o#+vP;{C=(dhz3X9yIXDNuBl zP*t>NR=O((Qc1rNFWV~=ZC1(0*;zUHN{Y_UvbVPkMHe_e6kTYCqKoWMbg>3Kr09_>TWVq`derfu=rKDKJ#L4hC+tx4q#cT$vP03+b|`wr4n@z}q3AiA zqUQyQUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k; zqW1-gJ`gDSP@w1|fufHEiarsliXO^J>*YWy=caEoJ{*dQ#e964m6NZe=*ujdF)0*% z<@iwawH=DSu|v_fb}0JJ4n^PFq38!Y6#Zz2qMz(g^s`OTF9Jos3Kab&Q1rV%(H{au ze+m@+B~VnTjhpQh6$OfF1d2)mMJ)u1GJ&F6fugcNQA>fMRsuz>1&ZnfirNSiwG}9; z7pjUr&q~MSKq^ZmMPG!XZt3UI+SQhmucWABZFcRHP_%&KL(zhEC~B}nQKKD-7P3Q8 zCp#1^Y=@#n>`>I%4n>RF6m=0OT1=p*t3XjVfuh9)ik1*4>Ml^Uq(IS90!2#;6fGlA zw5&kUasoxm3lyy&P}D=9sHZ?tFM*=o0!4iUiuwu^^%JU!Dz&ATav+s;yXJ5@)K+il z-k1UDCr~s}plE%8qEP}xqXmk_2o!A~P&8Jc zXq-UNc!8n`0!14N6m29>w6RcCv~q1}(P_D&C(~bItAwJ#={L`8Qd>^GlAV_V+OIY{U`8m~-|?a706P>NXosSM>`-*D z9f}UIL(!pjC_2mzMTgs==m?vlBL#|%5-2)aplH58(J=x=#|ji3Cs1^}K+y>TMJEar zog`3nvOv)(0!60^6rCnebh<#%83ILT3KX3sP;|CH(K!M|=L%It`_z^$$$?ZpO^@E+ zHx%uWJ~5qFTTZ@`qKj&?M`wnjiya?|F0n(=rFJN~%nn7D+o9+RI}}}MhoYlg*I)S3=1&VGED7sOg=q7=pn+1w)5h%Jum+K7pe91&SUJD0)z!=pmu1=z`kPS2>W%yXh~n3q#Su>A^-1*Ors7r0DV5 zto;t5=n2P%q9^T8^pqWnp0-2LGj=F?)(%C_*`erpI~2WOhoTp4ie3^ZdRd_86@j8x z1&Ur1D0*F>=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>n z1&TfsDEeHeDtffGv{DYF@^QK!?XghwMkya()RvR4r0AR4Y{R*s=v&8!qVMcb^t~O5 zey~H)k9H{f$qq$7+o9+eI~4tDhoawXihdU;`a_`TPl2Mp1d0mfxY`=6@9f}sQLs4ft6fJ6pqAqqQ zTFeebU2TfG2^1|ZP_%?VQFno&B?XF>5-3_)plBI^qGbh&mJ=viUZ7|NfubG)MLh+I zdI=Qu7AWc?P}EnTsGmU5iULI|2^6g?R23~yF5Qy@sl1TxfL*X$y`|qh{f)Ltxtx3@ zMQfC^cXtj&{T&~Q*0e*>06P?|Wrw1*?NBt(4n>3PP&C*MMMLaRG}NYOm_X4w0!70G zibe<&tt(KpoAxm4aISF~mNT(o*9x;`n|yj)JclA^83*)qF@qKS?VMO)jUXp$X@ zCflKCiXDo!u|v^RI}}Z`L(z0Q6m4r$w4FfF41uEU1&U@06wMMSnk`VYgFw+7fugwr zMe_uTb`&VuNuX$Ffudamigpz!+D)KncY&fk1d8?)DB4S)Xm5d{eT1r_Ez70#b0C#g z=?>VYP;_V4eC%5;Ctpd?f#q!G9--(U$A_YW?ND@x9f}UML(yS&C_3B@MMv17=tw&h z9c722qiu@j3ltqAP;{(7(QyJr#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_6rCYZ zbf!SjSpr383lyCrP;{<9(Rl(z=L-~FAXF9YUoIV&1F4Kp-y%976z!Y7cYR^GoO~rk zmzJ~Z_X`-*29g429L($cCD7wZDMc3M)=sG(TU2ju#gFw-Z0!23o z6x}RPbc;aItpY{22^8HfP;`et(VYTCcL@~TEl_liK+(MdMfV95-7iq|fI!iM0!0rA z6g@0Z^oT&wqe4~D#pTi~IgmV_Vda9iLx=$#2+VP?289Nj` zYloue>`?T)9g1GCL(z+ND0;~bMK9Z-=oOoyR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2 zfueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzpy&&MqAvxCz7nd6o+y_V z+c#HqMaLY@lc8v%^ick<%jM)NDf+>-XIJ`oZy`=tnyg{bYxtpY2feiyex7wL{Tw zb}0JY4n=?1q3BPWqQ3-+3N7PiJ4Ho-q8fpsl0Z=lfuc;Hs8*n;EKt-^ps1BVQEP#s zI)S1#0!3{Fis}W5+6ff37bvO-6m<|N>L^gOfKXNRZMifh2U3~2P!8w2Q1pCKv|!6} z@|6^IYMC8$U?^JH@u6rDI}~-cL(!skDC%N|qQ&e`)YT3}-Rw}bxE+d?uqo;;P_(2# z(NY3MOA8b&BT%%gK+$pnMav5mtsqd;L!hXqKv6G&qTT{UeFTd73KaDdC|XgVXeEK7 zl?94c5hz+!plCIrs;IGL>9QP1rDyjX&O$A#xAfySo zw6-0J2HK%$kR6H!+o5QP9g2q9p=g*Liq^41(Quoh5duZ)3KXp;P&87YXnldAQ36Gy z1&YQ96m1|-G*+N!oIufdfuaclMH>nfZ6r{%u|Ux#0!5n&6m2F@w7Edh76L_E3ROk@ zTb91bf#jdmayV;-qJ0+3M^npk@|6@#YMFI7EEG+4d?=b?hoWulP&CyJMbqq1G~EtG z+uEUMJ3AE3utU-IHbpZ9ie?EE%@!!yL7-@kK+#-*qIm*EI|>x-Bv7=oK+!G&MY{?V z?IuvPyFk$%0!4cY6zwHYw6{RfJ_1Gi3KZ=pP_(~LRWz|>X_XvE<+O!!I9rFJZi&nHMTgm;=x{p}9bt!}BkfRhlpTtWwnNc;I}{ybhoWO`ijET~ zI$ogY1c9Ox1&U4*C^}i7=oEpXQw54n6DT@epy&*NqB8}G&Jrj(TcGG1fueH-ip~=# zI$xmZ0)e6n1&S^bD7sjvDmtiTY0n%;W!o+}oP$HrQt4M>UDC3gd?iI!w9L*tDimGm z_)v6}9g42DL(w&MD7w}TMc3J(=z2R8-C&2J8|_eZlTFdh0!6n76x}LNbellY?E*!2 z2o&8ZP;{3-(cJ&heq>c{>!nV27d??NIcR z9g1GIL(waCD0z7?v9o^Dxcbxf}4p!B%w zXF^fe^aCN^wJaxJNzqR&v*nHpML#<}6#Zg{qF?P$^qU=uez!x>A9g7E(+)*{*`cV= zDsH!jqM}VvjX+UJps0mFQ6^ASD^OGxC~7HC)JmYJwLnpwKv5fkqP7A>^#Voh1d7@V z6jcO@ItUbX6ewCiplCsXq6UGYMxmNjnrRWmB}YK+!S+Mav2lEhkX4 zyg<%U7%E*XprMW(O^3i4Y5Pf zP&*V2vqRB3b|@NdhoTX7C|cJJMeErVjT9(aU!Z7|K+$M{qA>zR8weDQ6(|}fP&8hk zXo5h|h5|(!2^4KCP_&6a(WU}Ln+X(cE>N_EK+%>0MNI-lTL~0R6sn5WYE^nI2U2O5 zKK-m6iZ;z(mTldtoO~rk+qBAlKP41Rb$lqAW{0Bbb|~7`4n^D9p=gF3ing~y(M&rO z&9Xz$Y@4DT1d8Se6wMVVnkP`Sqd?J40!2Fu6zw8Vw5veTZURNS3l!}kP_(B&(Ov>Y zdkYlpBT%%jK+%2zMf(dB9UxG2pg_?fub`6ip~@$I!mDFY=NS41d7fTC^}D|=zM{q3j~TT6ezk#py*%}?bG9~uL?yEBt_4(Dkon_(F?7zC(jN=FFHOHy<~@?m+esWiXDnxwL{Tsb|`w? z4n=R+q3BIJ6uo6r^tM3JI|4=T3KYF3Q1re)(FX!W9|{zGBvACRK+z`xMV|^3eI`)! zxj@ku0!3d66n!O7^tC|IHv&c93KV@OQ1rb((GNmZ(Q~az-{n9mKcqW7o)1OKr7x0x zY*kLalA>Q*Wec1aihgr^DEi$FMSs|#=ubNo{bh%uLhHEY9*T-~D5|kTQOOQPEo_Q1 zfudT0qOw3yOM#+R0!6I_is}T4+6WZ26)36~C~7BA)Lx*dB2d&pps1rj(EY|{%uQCG)@ zqHcC5THFprOW2{PyB&&_v_sKSb|_lf4n@n@p=eo~qU8jNmKP{mL7=FIKv7SDqFw?; zy#KHaCkcI$HTl@twWot=GAC>rYcP&CXAMeEq1Xt*7UM%bZf zT{{%5XNRJZb|_lk4n?DEibe|*jS(o?K%i)>K+!mXqVWPn69kGj6e!wAplD-(qD=&f zHWet^OrU6Ufub!0inbIeY7!{gN}y<>K+)C$MUw=ICJR+XgIbp!$bnQgPk)IG4n;>N zMN?Xrldq&`dh6`NOG44Mjt@oK*`a8L9g4QML(xn-6wR_j(QG>u?O=zZId&+TYg05& zplC;dqMZbab`~hwMWAR`fuh|6igp($+C!jdPl2Mn1d8?+DB4G$XkUS%{RE2k7brSF zpy)t>qJspA4i+dnM4;$Up{i(V>r&mNxuQMOJs{IU(U$3FKn`nNPQH?&qgrPxTpo&! zc6=zBZ-=5|>`-*99g2>#L(%beC_2FoMJL*!=p;K7oorKdia^n+0!60@6rCFXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M z(Zd2oj|db!Dp2&8K+)p@MNbG6JtV_VdbxFW^VOl~6~~97SM5;rnjMN>w?okzb|`w&4n=R-q3CTp6uo1I zqIYeI-V-Q#U!dp%fuauuiaru3`dFao6M>>n1&TfsDEeHW=nH|OF9nLe5-9pwpy(Tc zqHhI?z7r_=UZCg)fubJ;ihdF(`dO$dda-rsjT}hjf%Ib^FNLCm(<4KEX4_ z2^6&vC~7NER4-7}PN1m0Kv6}YsDnUJM}eXR1d0|EC~6QWY7{71NT8^bK+(biMT-a& zbrvXERH!QYt#xUM>vBasmdN4!9*RCq-#qG4S5Cf?qQ&d7Avc7gB^)1$y4#^>NjnrR zWrw1r?NGFg9g3E2D=Av1E<5a|P&C}}p=g91iq^G5(Ry|$8fk~3_3cnJ$__=N z?NBtv4n-T-6pa-q8YfURUZ7}#K+%Q*MH>keZ7fiIjd6!j4(>MKyxPoQW;fufZJidGgVT1B8}Re_?_1d3J{C|X0H zsJ}qbngT@w1d7%YC|X;fXrMsRAc3O60!2dviiQeRMN70Pjmv>l=BM90)4fggmj0A< z*X*!1<>V_VTDMI$@1an%p5sH&NIMj*Z-=5$b|@NchoUidDB8ddMPuzyG|mo1<86v2 z2o!B7P_&Ui(Z&Krn+OzbDp0hUK+)y`MOz3IZ7ERHBv7=KK+!~jqOAprCJ7Wx7ATq` zP_&Ie(Nuw=X#z#l1&X#6s)~lUDV>r7sqB=#MKmH5{hWS*$aZbY$yZV|t4((6BcW)v z<3rI7b|{)-hoZT5D4J)7q8;r}w38i*cD6&&E_Nu|)uw1Sfuh|7iuMpF+EbutFM*=H z1&a0&DB4$`Xg`6X{RN5+5GXoOpy(ihqJssB4iP9iRG{cEfuh3&ijEK{I#QtMD1oA* zg{q?M+mznQfmH5KkGq~3iuO(4JeuF8oO~rk$G6D}kB6cY93P5Kv_sKJb|^a84n?Qf zq3BdQ6rE;=qSNhAbcP*@&a^2yOQ7g%fueH+ip~`%I!~bJe1W111d1*cD7r|X=wgAQ zO9YB86)3t)py+aeqALW7t`sP`N}%X!fud^!imnwXx=x_zdZDW5*fymlb0C!m)8np> z3q?<-yJl}_Q%=5;qFdTz!=4O9w>mx)-DZcP+wD+vhaHOUv_sKdb||{r4n_Caq3B*a z6y0Z2biY8+0|G@43KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`|v_R1_0!7aX z6g?+U^t?dP3j#$i3KYF0Q1r4u(JMk#(M@ei+vPwiE2m!*a&sv9s&zhIZBtIZlA<@; zWJf$5ir#X3D0fucW!s-oB1l&;BvR3@dn@!tqVH+0O$Uv0|CS5j1Jn?0LplDHnqAmhOiwP8U6)5T^P_(!}(Go&cQL%05 zryNM-g7moSnzq&3XuB?ukM3>D$yZXeOxtXs7edjpj*rhp%h{o5c{>!XV27d}b|~s; zhoW9~DC%v8qCR#g>T6TfPoQW;fufZJidGgVT1B8}Re_?_1d3J{C|X0HsJ}qbngT@w z1d7%YC|X;fXrMsRAc3O60!2dviiQdl4HGC@N1$l9P*t>4+tQjjkjf+J#{JTvs3zS5 zGNNrc`AUk`Z<}rTQYaeb_)s+34n`=739g6m_DcVz@XfJ`Hy#5&{r<*f9V*bbp+e0@HSYgrs!OOqVoib&KD@UK%nSCfuf59iY^u?xp9|Vei6e#*hpy+3TqF)4xeibPCO`zy^fucVIivAQR`b(gw zP#-tUDJlw8MQ^n&ot6Ws9GM>8_;x7D(%m67_2uL%DXOi{Zhtovl^q|7TH2wgl^u#& z+o7n=4n=M3P}J5AMfG+lYG;R{_BKTofuarqMI8l-77!>}P@t$mpr}!xXd!{3P69;> z3luFPP}EtVXikxa)iq;z-4$og{fl@yJs z&xU^#iZ*b3C>m>rqH%U88gGZ933e#j&<;f#*`a7-I}~kVhoVhwiZ&A{+FYP$3xT37 z1&W#kinbCcnkZ1TwLsA%fuhL*MNd&8;t8mjkKn zkp2>z7m7wS-(agRCtpd?srA|OpM|2+93P5Kw?okxb|^a24n=3#q3CQo6rE#-qI2y~ zbe2cSmgrXre`M9mVoO~rk zchzSLe;JDIc6=zh#|}mJ+M(z^I~3h-hoT4UQ1qZ3iXO5<(ZhBqdc>yaQGuez1d1LP zD0)Jm=t+U1rv!?g7ASf~py*kFqUQvPo);*3L7?bGfuffLie45ddPShT%8a`KfFyrxv!11BzLpv0G zWQU@U?NIcI9g04+L(yk;DEizEMPJyV=u4ZTuLO#|7AX2gpy*qHqVEKXz85I^L7?bI zfuf%TihdR-`bD7VSAnA61d4taDEdR7=ud&7zXXa3?c!!TMMZ(48iAscKv4^!s_5PN z(t$aU$_eRl*YAa*Ytlp3vUcU!#~XNRKp zb||XYp{Ro$iaOd9Eg(>|pg>WBKvAPW(Lw@6odk*&7ARUops2Gz(V_xHT?C326DaB` zP}EJJXmNp}B?OAP3luFWP_&dl(b57%%Lo)LD^wMg+m#;6fmEJI-)L;vu6j%Vg7k>l z<=T~#ucWAFyX^DtLs2ishoatgDC%Q}qP})0>Su?d741;8k{yaxwnNb>b|_larf4;R zqSXb8)(|M_FHp3mK+yn!qO}By))pulC{Q#=plGl_(GY>6p#nw21d7%XC>kzMG(wjl?O}(aJ?&7mmmP}s zwnNcAb|~7{4n_Of6zwlibbvt7fdWMb2^1YHP;`hu(V+rGhY1uNE>LuYK+%x`MMnt~ z9W78aU!dq1fudstijET~I$ogY1c9Ox1&U4*C^}iFD%z=C>5Lpm<@EHI*v_G7_w>!9 zQ`(i2ucYXVcG;c3g`zVZABxVhL($oGC_2XuMd#X~=sY_Voo|Pt3+zyIp&g1YvMIV) zpy(2TqDuveE)yuaT%hO*fubt~imnnUx>}&<8iAr~1&Xc{D7s#t=mvqJ8wHAP5-7S^ zpy(EXqFV)uZWAcFU7+X=p{nS#cBS`nAeFxP%uWwQEz(2Q?rc|1zLKJQ+hr~O3`O@j zJ`~+=hoT4UQ1qZ3iXO5<(ZhBqdc+PzkJ_Q=F*_7JZd3GxK+%%|MNbJ7JuOi5j6l(| z0!7aW6g@9c^nyUqivmS22^767Q1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH17 zLRHb-?Mln$Kq~Fi1JmvaMbpybi{5KjPQH?&kJ@GH7Sb8ykGuZZ@uBDwI~09thoaBy zQ1rPSioUQz(U*28`pOPPU)!PR8=InU1&Y2CDEeNY=m&wK9|ekj5-9pvpy(HYqF)7y zeiJDAU7+X>fucVJivAKPDzuNA?GzOSifROkN&-bK1d1|&qFRBXvQSm@LA%nd97yHf z^zX)g7>Y{iPPLZp%gI+#)TVtlza|v5b$lqQw?k1oI~29ILs9PawESFK6hl!5I}~-a zL(u|uC|b}CMGZDZjRHjr2^4h_C|X#cXc2*;&H_b?3KVq_C|XRQsH;FxH-VzX1&Wps zDC#ayw4^}MQUXOw3luFQP_(Q-(Q*Ps%L^2(AXF8#ZeO|~2U3}nz7(o!U%jROKvLAB zeL49`iu$zAUThJH`Z_)o^|M3KigqYk$qq#;+o5O`I~1*IhoaT&P_()oiq^0x>Mu~V zra;jEfugkpiq;k=8YoaSNT6u2K+zC^qM-ss!vu=f5hxliP&7iIXkCG#^#qDW3KXp` zP&7)QXtY4l7=fYkRD3KVT8P&7lJXnTR8nF2+#1d3)06zw2TG)JIlu0YW|fubD+igpsJipIAu z4a|X5j_RDlnGlNBNH_a;ZeLEmlA_()=l|wjDB8pEp=eJ#6zye)qP^`lg*I)S3=1&VGED7sOg=q7=pn+1w)5h%JSO6Day!py&^QqCW+S z{t_t4{}Jfw?N^G50!1|fMJ0iv76L_?KvAtgQCXm~b+AKGM>`ZPV27dw?NHQUhoVM16fIplDHnqAmhOiwP8U6)5T^P_(!}(Gmhh-35x46ewCsplE4$d1d28gC>kqJ zG)|ysyiirtw^I5b2U0mB-MH@;ibkh9_$O4#$yZXeNhPao3`LtdJ``vQIj2twz5OfL^~91ZHJ;sHbs*Kilzt@Z6i=LRiJ2^K+$x8qHP6=wi76tAyBlv zK+#NrqFDk(vjvKF5Ga}>P&8MdXr4gPjsitH2^8%tP_&Cc(XK*O(MFZh@;Q*oP3f!a zjYHAp-SV+prJQ^vMSE4Uk)1-(-i{AN``DpqUpo}-XNRKw?ND@p9f}ULL(xHYC_2~< zMTgiF9V$?Cm_X6t0!2p%6dfs0bd*5R(E>&D1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ul zqLT%RP7x?NRiNlJfuhp|ip~%yI#Z}B+M`n1AqP?!lfLV?XDAw)##xne@|6^wSILfD zBov+R_)v6#9f~frL(xTcD7x4VMVHv2=u$frU1o=(%k5Bfg-y|w0!3E|6kRP)bd5mK zwE{)g2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xNMYjnQ-7Zjchd|Mt0!4QT6x}UQbdNyM zy#ht|2~|bsR7yAHKq`B*$>E$Eik?l1?yr=SucYYVO7`-iq399EhoVRAQ1qA`iXOK^ z(GzwkdeRO>PuZd9X*(1>V~3(=ZHk@~D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#K zU7+X>K z4(Fjz^i->Sd{QYVUrEsym8?tGQ1qqaL(x}uDEitCMc>$==vzA!eP@TF@9j|ZgB^-~ zv_sKPHbp-R6#XJl^s7M8ZvsWX3l#k!Q1quj(O&{Zg${AEouZ;ZQH?-RNua2OKv5=8 zR4Y(a7AR^dP}EAGsI@>*oj_3=fugoTRncda(%>9OrM^QB=kri>Qo1{&zC$_rN{Tvk z$R;lyiaI(z6fIzfq6O_x)L@6AMmrQOWQU?ob|_ld4n>RDp{TP>(V_xHT?C326DaB` zP}EJJXmNp}B?OAP3luFWP_&dl(b57%%Lo)LD^RqYK+*C7MJost^$;lPDNxi)ps2S% zQ6GV#zCu+|`wpc;b0C%T(#^6;hw3f;GjlvyzYgW(D=Au~Lw0HRP_(M!L(yt>C|cbP zMQhlhsJ|VG*0e*>06P?|Wrw1*?NBt(rf85r(O`k1Ap%811&W3V6s;prG+dx)gh0`{ z0!8Zy6pa)pT3?`Olt9sFfub=2MH>hdjTI;wCr~tAplE_X(S`y=8wpiKD|IM6l>@0P znC|pgITT&qe1ok+Ir&P8Ht&#qy;LaL!ttSKOFI-b*`a7FI}}Z{L($fDD4Jx4qRDnB znqr5dZET9B3KUHfD4H%%w5>qVb^=8+1d6s7D4HoyG)tgpwm{Ji0!4EKislLw%@Ziv zQJ`oifufxSigpnw+Et)vH-Vzv1&a0%s){!4P+D;5T+uD*ao3xLqHgIPkUcw;ldq&` z-wxTz%Z8%;93P7Iw?okZb|^Z~4n+sqq3B>c6dhuRqC@RabeJ8A4!0>fLZIkKfuf@X zijEd2nlDgvj6l(`0!7CO6df;6bb>(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaK+%~3 zMP~^Voh?vwj!;#!cZbquIgrZv`ONkSMGGWS=XNM3Uxft=HQ5raE?l8lXy}`N)m>;9 zpZ_}A77aV)_mZ@1I641|uua3Ql|rF?!|VAY0TyWJnm_b*p@wbpbLiY~dHw*(t_|Pj zUuAV~ST+CQ+hrQ|>Q*SM&~Sf#cT4Yv)=L!%D>jT-rchY5;l$+%h5ik%uTUtg-LQDC zLSab5v_6Hx@P;e<6$&F8zF(g~A>U{WmBS_G#E}T%mA4 z!^0B_g+m(ZH!c*8Xc)g~p)kMU)XfWp;~U=IvQRj=VX29Q!s!h&CKU>2H(WcVP&mKg z=c$Fl#SH_tEfg+qIABJhaCO6@GYf_58`|$sDBRqz;oL&u_J-4UEEMi;cz5SQ;r@nY zb}JMfZkV}8q40Ra^?MZxPdEI!PoeO9!`k~73NJStbYP+Idc)%f7Yc7TbU3U~c)wxe zBMOC&8_qncQ24yz{rQE$*A2@ZS15enF#Ci;;pc`MPbw6CZ~Xm~{PHh04mv$OR|Y6dTh&2;95anEplA6^o7OpX6M%*qHuJ#s0;{^pE1LU2Ht}?)(ZV zHl}};YIw0R{kuXVi;d|Yh8a_AO#iaS_+n%Frx`XbHm2XLzj?7S{c`lJijC>FTTd=F zre9Ayt=O1;zwC@+WBLW5vx|-CH$2WOHl|N~r`VW&N!C8a#`If`4k$LJ zUsH2Pu`&Igkt2$Y=@&)JFE*y1^gq7Xn0{3IIa&n`BmpLRRH*qDA? z>EdEz`gxPfi;d|A2CgnPrbm2VUu;Yd*}b{gm>zR^d$BP+XzuP}V|vun{l&)gu$704 zjp=a*j~5%$9mh`>8`C|1&lelhT{kZm8`JmRUoSSMZ=SwgY)s$%dcWA1zJ2j=u`%8L z{JhwhZa{opY)oGPeqU@%e}(^CY)qene=ip5POao0Sm#$ii)h$%cuhjg% zY5CLQ=@WYu3!NU$Kemef2Bqg)S6^7@G&cYEDfXL`+Gcqho&V`{On!$`vEObh zUw_(l(c-w;%5`5I@bDgmF0=Dv_RWv!oPRttpJAovKhE&VIK!dUR$JNk@_X;wrTH8; z+yBpX^K;DF9M*E><(kj%id$~JZI?oq{3D`pR64^a;|wQO4=(mDbe@*KJE!F@JHDE- zHsz~dnUkMgZRNLTzxZpn=JRVBe`sxfep#FMu3vM5Lg$0xkVm`;hkktMxqCJrbIJR^ zo|-?GzgHLDd;TSRH6Qf!l!w8c<1ZhlwBuYKFV{N%NjH@VxwYuXeF=}+y)`RJUVB>kza$xrrY zt}p$mZBeQ%6f4Cg>pRw!>KCb>&{!$9Z_JPCUZ|@Zkf%bS)KDnZuU@xC-D-6sI_978 z;w9<(hbt9Qsa>l1Nx4O_R6n4uEUEnho(adg|;1wb#?zZhx)dKQcJJCuC8reo4Qr=^J~}mFQ;mspX#69$V$vO?+$U6 z`AlzA$2iO8m;U1{7l^ZrQ!SVul>OuFXlR?im+3V(Hb0ZUCkyo~uGPtFUAohVj+J7E z+O-!tX;7#1N;+l#^cK}L-ZUt`R2N?H-?v5nxur|0^P&3{^J}C}$8;`>9=2bxP_xi6 zgYpmDF8K=z=>>(tVosA==vi2+Q~ypg>zm(_{B18Z|5q$lpXUGHF#l65j7d*MrcVZi zjnb2vTwaU9cf~PhrRQ4afAZ6$C+QPl^#y;Q!@qfEljbwrAU%0C|3bG|n2?@0!ws6x zuubzBZjhezZhm$`dg8n{IP2e>WxTolo6mV{dXmnrSQww4RL^T{deXI8(-Y@4_V4qm z$^TZV{?{^prl!#QtlRUacjkXeg_cA9ezVdG;&g@1=`}Tv{5^>O(i#8rfB(EEqz{O~ zv+43H{+81$=KtlV&Hog8_UtuhVy|uH&h9mL&ZJ&*n&wWL(lmR{ta(!=&6_g0*Q7bS z&Ym|bg-KH;?>J}5+<$smI(>fX)q2gIGkyE%^QP}KrO<2ItnH`tnmA+1F1>orm^EqQ zj9zo6O`J2O*PJOcr_7x=x7U=uO>^h%IC=W4Uh`(nnlWkG#OX8V_L@3rQq#ma+xP0z zyQyDO-`;)uH1+A7Vvjubm^o|alpa$iZauw6pWZ$D^++%7nZNj7Ues&)%tSwi~wN%%<`A`!aRRj2-7TjUBl1`YXAb@^|+C;JN?rAlPZ*yea9rC=`Ox zN-OuAl#n$|p0drv9cRpInz!rhDRX;HOLlVzlc&#|myc4Rkn?MrG;90qXU%MyID2~D za@OMp4{gdXlu3h|d*1TTU3gAUud12~Suy`@sR@3mUop!%{zw01#oE%;VzywZQ_rkr z|E$BPtmDWms~z4k>sXr~SKI6FryZL2fI>}+;(}RSdeScImY(FjdG^dt-Zwva$E^Ee zS;wyby@RuE=}ejrTH-%Bj|FRsUGsD6mUSGF&ZSqctoq8=i>GVG8?|Qh?zVW=VTJs3 zz5hpVT7I@!w%$L^wE7rFm+&%quF21|F+G)g z{V(QpWz>{*>RCOv{OgabbMx7!)FC}ry}r`x>so4?zpr^K*8Y9vb#0yjAYBrD|GtX; z^(q_iU%cu&)HY@vm(9;8zn+>exPSk&ddAhOEvsET>zYpYKlx@2_@6%NU#>dWsy8AB zSU@?Ha6J_`Al1zfxSo|F|lvFW)6zzRbUS`F}2;OS<}M(-qkzS zMYz-DQt9d3^eVb3#JqOw)U;pWen~&}K_umV(-SfX% z8Wu~hdXsb}-LiBpRp!b4|KQxxt4<#*t#al)vrbj!-6E}(%E0vYDFad&^pBE%;oyb; zd(SSGzYPml&+PxUXM1ITzsLXovsDED4_pq_&s5zP&l=N5RD5~(-~aF{u9&qi-Mwf3 ztXR6crf0%kdVH^*Q=31f{g=+5ec$}hD~dh)*L2QrMh+V{rfKNdu}vdJZ8&h`h#^e_ z$F4JB{h_1A7rbEoq2tC4TxV$0_|c=AMvfk}PGRiOb(;DN96bE*Qw$zIZbE+i;L+=k z898)(e#!}>M#Slc4IbXK^*>HHaO{w#QKQG_CmuI+?D(NW{(i~2WAZbdFlyX{F=Ixj z7c`9-vGLH6O~XcyU4P*C>TAr;>R(SjXyoX@>opA-IDTN$s0r&28ag(;AEU=sPu*|T ze}2WIMmLR{FlgN1u_MyShK-&uYDn|RR#|m;^V8M-<;@&BbljNH`CC{$rxo+lxGd7! zK6LEBasTv|yWG|vw@%Zb3B!iv=Ra=5rbGWe&lL*rfU8>b(bKh1BK_3PU-ulYR~@-K%E z8kyfH8#}D|Y8X0dU_OTwMh_d;G;m1uY*uPMb$ZK&{nI->bo_9aZ_}9Jn>6Lu_4@g> zJb2*v5u-;{FQ?W1KCsW=e>!r+*bSNn<;I4L7*~B|F3aj!rZa24+L}g=7`5Ktm)b@n zhK*<%IHvin96Wl|sG)3H;KSfM6gg* zL_tCa3xtqBXu*Ugme8B@4kASmQBhGu5m6DW*swQLn%GdmUQiJ`Hblj!sNZ$ZoX2Lv z^Stl({qg1Z%U*LHJ8frvvpXK8G+|FnFOQ}OLA<5g~bKArTKYzr8%7nwg1Sg zu#Nlstj>kGT}q4k_UYZXPieoR9(`=XOpb!h%!1fiTMg8)N3wjjwKYXIay}Bg#$0lrU&twmUy=^b4 zRovV5Q>i;@|0R`}3CX>0^W*~Sl(KN#3M!v;upy;9Z7aeSNooFoy!`ymDYL8vV!Q4> zxwh-+o_}^}L2jYjeXtJIhr8@!vsTo%*g9azUo?r$w) zCyXCi*LICQYiZN+Uwn>rFsv=mlA`j1p*y%FpVQvGIKM}}e*|y?=U0>}SnX~B*qSXY z2$oPVmDVX!@%L_SO}YK3f6UZeR*;B2KxuAXUf<%}Jnblx^V8Liru}p6h4v}znQyDi zA4l8dD$h%qU~gMtCB=CrRc>CN!hXS#t#!%)l`Ygx0lM_^5C8t6X<@y%j@$}|kks8o z`F=4cKe-xRXL2@Wg^6Grd|w?@Z8pn$u!(jm&b1Q<`Q)Z(YbSMkvPH#Cy+=`rw&=FW z3EFB1mS873^8FP)W%S7L!-v(i%hZ#TlXG$x71-!ZlJWyV`Tig;uc)-E?Wd9huxxr3 zbq?m<&MlHp=H>V3(YHr#u^Hc`u*Bqc2Si>7RJ<|@739C zP1zYIS8$$xiX~@kDUKgGyma{ZVWS6+FLm2ea%6=)dgOP>?V(N1&LukA4xs#C>ieEN zJf*DVoVFE=mnvOtOev>woq1Wdau0K&(CrHk+Y6XVvLkqM0kW+(EA4z%pVH1%Bc_cX+N@=ZP-<$a zxvijP((%KVG;2NO)Vhal1LfSm&yxv@BGOZ6vOzBT9M_*Qi3)wgb5 zyLNTmZKI|+b={4lW^J3dtlMbv@Ug=OPZ@qv-6rFPPMmhe&08AELbnv57Xe9Dx;BZoH`JAC}esiV$lW+>RUnm9u& zxn((Z^n~$Erq~@It5b{(v!hrt`!BIg1@HWI9voC$YrtQD`Mrwz+OEgeu^2lUo zXt|vVdlU{VKlg5CyW7I?{!z30@L7f9hYg?UkD^6|ooM+M?>3vHdgTV&QO5QKee7)0 z9lDb}uonIHR{6@cZ7a`C1UltfBTPF}H`~^J2xh-cx$$;@4_L*zJ2VI<>=jJLn6V0*4tUpM_Ca^ocl%H~0!&lp%YsmYH-8zI^ zOWQ|w%ItRp4NxC7OZF9XvC~XB_w&zKt;M8MFWZ=dvDu4CSt=<5xKl~nHTe=~jTBEA z+`L)Kwml~dn>KdvAI)3hgX)pvh2LYVQLmzqpcPr`a|Ezh#kZUN8c;gG*Hmjwl7Wo$X4{VJ%@_0yotz zwn-$vPE`QWj)!exLt(LhbJ`Xp^SWA_H@}D9i#2(Zqf2ft1^r9=+BGvQwRXIIQvg0|yOr)#Kb zF3ZPc4fztc`z-g;_3~fOURk*nt^!s#kxrhN(-aL_PAmm2(u!Lq>&jmqcB&LC4{M*L zEDv`abd8kKlKzE#?3t8c<>w$ycTQ_k&t8+4ahh`( z$2IU+P>jr-hJ?oW`#v{|u6;!>sf_`y^Y9_lM*2(CwbhtOw<+d!3fu~=P4f(|u)vyN)>xo+|b^2*msj=TEJlyq?;I7a#_I=FQ2I#aKJ`%SsS_8a9VmYwtehf_Z5~6>NRSA*8cO*7__{2 zoykjX{wT{YcIVg?veZqf{7Q~{vB5@AVds-OzoOI&oW2PE?YJB4g_9S-7_WavhpisyR%>zJU=QZ@w{Y#9ZJk!UhMLmcvCA+1 zVzwjoe=5a`u-%;2VsVl$24H&)5zP-BlD(W9B1)4eTLc1Gp(1u`4o$Ru*-Hr3_l=x4(HVjXu zoF!DaisH|nyT0o>Tnons?#iX#5nNq$owR9kQZHI+tnO-gfo&38G-9H`Yh$0HjWFf< zXT|miCpP|sZ3QIf-QV`?c-1Gj*qsU5_F-oo|I;>@a`{!SDkr#h>P8#1u$Vo&l&=#P z|D=Me`Tq1%cFdAFIMYd9g0wA}(-q0a-M^gR%BepZccIen2+oq3vfCL~JkBIH!PKoL zm=ha?zXd0kM_!NIp1o5J(!pYO_wn3#%kMjtpXcYaOz!B|G;-Xf$Y9ng>`iie+v)fK zYb;lgJZ1KRS6ixK<@;E7?K$;+5c3(lUVnMnvh){R#k2YH zQP{muPQI8~+EXQcOYAO`+Oz+0_0e5;JnT+G>eZ2E6|R+(xAg2*x^7~**>eq%Wc!He zyFfah87n^vtI+arqqi-fue~hh&5b5# zIrv@dZG)?mrKL1)8F9+ayK8ZGTUo(2SZFK0{4!hrTx&tI4?S#1cYVhlFN5V%eu2|n zDopmueH6c~)}`3Bj1OD96@JuIe?L(2Ki!A@jL69R<4v#J z^7k*e)p^+b*?}Z^E6^=sjwI#d2v%7CqT=p43MS7Ma)QgC^lJMaZeLVvAr;t7Xc`yp zT^FG)d3o*YHgcEfb0?3hn?G*I@L|L3PFo*76yjgC=ffT+{m<9%?Op%&IkC{c_Gh0r zno}wJh)_fKQ2_n9kHB=Q)M#PmqWC4T#nDSMmUx$?Umm$4?W%Anx1IGg*nP4j6t<5H zhrG5;dN#GDL$6RqBHA+^$&6J^uO6-ut{FKhTq|5Ve02Dj@NsGN!}h_t|M*Kq>7k$h zP3x$Snm!|&NXUS8eJzw>(Y@g3J z;+BeAKUMAZwomE9y_TMbW%rR){@nAU307U6aag|Ou*~O1{I|$7oEmC4?Em#b@qf8% znR-~uNja?jmz!ZJw+AX70GkINZ_BJ<%fRL}(>_P*KEj%5AGTZRs`2&W54dU{qkBbs zn0?kIvsNf{v1+z`EXL)1wwg2Tv$fT2nY!xMdYY|Dw|%79LUL=#RU5TmZIDo!eJre= ztF}rTiMwsV_19YU4AoAmy;b|F4pkkaI!Se&>LS%;s&}eBscIh*_ouf_)xAzP{hg}s zs_s_ZtNM-VkE-?|ZhyExRh?jNJQ=Fls_v^$9Y0F-I92zR7mhbpZKm2<^>o!vs$Erk zsrFGFs5(e>gz8w;$*MC|=c+DJyh-FtRoANCt@?oKqpDARGA-R7+JysE$*es(PWS z^WV+SWva_mZ&1BO^$u0{4LPp=M^v9y-K_eO>Km%>s(!5ch3a>z2UP!1wH=*5{-|mt z)f%eDs5Ve-teT_RR<(m_fof0HKC0)a4pAMgI#G3o>Ri=JRF|qQS6!ugo9f-F52`+{ z`mE|U)mK&DRQ*78kLuT|KdSzwdPp^5hbOllGF20*N2%6PJwdgJYD?AAR6D5_s`ggx zuX?`faMiJ@Q&eZGE>K;fdbR5HsyD0Nu6nQP!>UiIZc=?w^>x*ERClX>uDVb4XVo&* ze^oPVzwVaP5vtWyk5;X(dXj2$)zefvtM*jwr&_8yN_CRzY}JLTOI25>-lBS!>IT)P zRJW+Us`|F-$Eshc{-j!_8ny$K?}KVJ)ninTS8b}=Mzy1Ap=z<}IjX}{$Ei+Nou|4) z)qM+woBk@*b*lHNKBoGd>Wiv7RXNY#TyS!8ND?7<@`GD%lc8=k4Th&Q+PT}%g)hFzn z!R2kLf7@rwUCulfJ;zQk-1tVR-qtwC52${9 zN|1k5ZDJ=PuK)I`Q*welU-hXLLEf(VZ>u0@+lh-CF28M1i&d{^ALNy)yX@2YuD?%I zYjy~7L)G(ggFHrcU0#qksD7It)dIb3;)o@XeE2(xlE69CR zuPh1jD%H2_gv-tE9@Sa{f_#E%>A)b5RlVcfAU~}7-T6T-Q_UG1Kuj-|%; z#q1z=RGl>^$ct5^Q)@*33-)&%)0 z)jI2fe2VJuJAyn}_1?RJ{G{s7_XPPL)i(D9xwGm;4+Qyg)vX(Xyi+y)NRW?IEqW}- z=c=xFBFJl1KYA+2->BBx804m^BcBWMRMq=81^H>!U$z7}v^A*hUI=P|>bw_&yj1mt zmxKJKYSxY*AEkQM>p?zW^@g26zFqa>H-o%SwZS_v#tdXRrqJ<+~R%RS#xb)0>zmdmqMAF=P(a(R>LANECCE@xBH6QI`j>r|m&-BxRy&#DK-!}e8Ju76K8(^Z>Z4dq&@$BCb;+Ez7RwOF-Ob*$iw#jA@kX$Q%SXkYAw~estr|}sy0_`r|MrnvGKTTSZ;i!sv}hG@ac0qEc$ht z>O9qjs&*LipTA0Vh3bu}kEuSTx=D4L>Z_`6sQTAcY<@me{!H~t)xTB4;b6M98T!*d zLiI@1+Nv3@e_Lp_O8ow;_|=*-e*Mg~lWltTt+k=Fgk66T4>g@KYuwbqL#$4n9Mn;C z*&DN`hMKx}LWi0TnKC8R)ZV+@)WN2~MY#X#`#k*thPk)R*nNo+6Kq_5_uwHzCJ&z; zj4mMdWksoR@MQO41x+yM<3Gt*_fSd!K3Qh(=5vJkEN`E$-QL@YJc3 zM-Q1c)kgdO`ggSTXp1*_1-Ip41KJ|>|LWPJ>n{?-(Bb{L=iJ|k_8+tV|66~}te?ZD zoBDN9Zk@WnQ|v!({~hh${Z*M54h^zuO$_%9KK{R(-eCJ@9;`F8IvNT+Zrd4ube(4) zb$kzddH$LZ=8>buJIQwT9>kJjQ35Ry206N_^M7Qg&LA$Vjeb05fKc2hLx>KjS zVS#-eo;~TN>p0VO+aAMMXQ*fUaHy{9&>zpaZ8dd#doB+9+l3onmi;rn+pL>mtTQyu z#^<&l{&?bFnnKet@m{8h7m=I;yZHkT(_@&A_D_}UY!y6L(12I^op1_LtM9S?jjVnzwD<*1DTD z%Sm}`-MXcpTDEHK`W%!wFTY1Y@GWh@h{JY;p7A;|f03WOU|Vk#s%3lBCf}A7ZRz!H z*~Xk|`|HFy?w`Fd|3KQ5?PZIajcO1rIHI6>!S=G)g6(DLIZt=rUbd&%yVeyt`L7QL zG-y9+ds(QSd*)I9nTKpF!E^oV{`>ns|1K(cu=|E?8wwxlYW;0?#Qk?auqSVO+4s$k zXy6_P*kgLm?cF~uTXL-%`v-@OVO{ri-EJ?uz3a;L$vh}s5`-)yKmu*YVPspEU z(f)8&^?Kb84w<#F;5nP~Q25ib)oZV}IcT)O{?{}c^z)GG3T>L#Y%kkc<=VnU-J`$F zpS-Xz`Kw~Kz= zRPyTJjtA>S+7@iKS2M5sW_t~D>~Uwai|lcmJ!TEMpm3L7)lREbnr$u%8l;iR@yGm{BE0bfd+F)eY*q~R3jPS=g${%aLhDVx~|5fPc8KO8C|uP-^XbGdH=ET82=gn zalQYz&wp%ufzSQN_5R~N|FQ8{$J_4-J#Swt-EmJSJbz6jJpb0+uhp;r)bWW+_ovwx%+9wOirBt3KYLjy zE5F&Dljj!Xoqf(H+j_jZYHItB?>jaBj1EsOe(Ku}=XIztqfThkg0M|;j6e1D{^LIX zvGF*6KK;k_{^LIXvGI7H`;Y7W$9?`|;|V_ZAJ_Yj`~1gu%I4Q~&%9H%NOg(oQq^Uu z*Qu^lU9GxC^>)>}Rqs>Xp!%rlld2n4H>qw@eMxnP>Q2?SRo_?Lt-43`3)OE_zgOL_ z`m1W0>Y=*n$Gca4UAL`ed-iNC`+k%CPrP~X%AuC4)E@N6=(D}8zs#@y=i3htUh4K= zb(a<{?RKSaW!?H64@6pA(euENDT6K;H86DOop)?ZOS;z|sr6=^&jgG zcFzs*AJ_Vid;Q1yLwxQ(uJs@H`j7R8`rLn9>p$-GAL|eEx&OGq!<68f5um4zoq|g1wwf^H?|8bic;hx!MMg(<<>QdEZs@JKmR9&sQM)h{p zyH)Q~-JtrY>XWJ)RX3?_Q+-Kwhw4t%w^iR)-L1Mu^$XQ+RKHiyS-q?yXB)lN(Z8)?wWBa+y>!0<)eV48K;pVcLL)?Dj`Iq0Xa{jIJpPINWS_I_rF+ZmBsX%Zo#CVv)f(iZ=&0J3VqU(3vFJ`~ zeWs^-?vo#B>CwqHqR6|p%Zi**E!TRF6xX$fX4U&xw|BKYWVnaueRfJ0O`l_(>D?>2 zZ*GolawkKvG&}VP$2!@`Oqx5X4n<-Q8%d9SZOMzhWhX)zv6F0;qp`&{jack)pwH*?$&0-zP3hOcC2k(yGs>oWhb_kVvCQn9cb(%d#n;`VtpoJp=0em94czi%)8#&G;>du~-Y?%6Ee6plBwSM_T+UfX8&w{YCu?K~KcKVwt>JsfXj z1C)j1+ib=Lq{WBZgf^zdkFMR@na2z>*C#z**#_vF9xpLb`=!Tg*&67d9v^3d4M>mQ zY;vBR9>3p4HZVPYi8V~lNskY()pl-ryq>wUAw53TW}>p$-0KG;SMp=&fk{psn(^qw$YzmfnfRU$Q0fZZy8b;Cs<{fi1K5qw$w* z@DHN#-)wfD%!;38Mn9Dmf7T}ZbXI(`P2riW`1LmGHI?HB&4Sx1$Ir8uvbJ)(z-DP( z<@g^~Zm%3a&c=C1<@lQ>+MSi-lPoQ%7H?;3^RjC3Z*B2ZIWhi`y`sd4@zM5bC)SKF zv3Z$PGk%)Q+2oq>J~r7YHRIiEAy2It-(gdjRx^H~z0Bz~<27xC&!`z+XvWU08F#m( zXVr`snXR*H#+%!yFRU5wZ}T~)W<1+g_(e72XWG)8TQmNg4L+}C{CVqTe$Dtt=EQ=U z@t$Eyv)#j!1>iDj@p-}$ncx7841*_wBnKjg9b$o^`iQZe| zKiYF=ZH=E}WzfF(7TW>_?~Bj1;Y_DO&zW6Yk z>yi61x7c$N6ZU%quiA^5v@6em~G>^*mb;V3u2+`m{;F^_Q7>Dwe@<5>sW1zf3fRGx7To~>-foD=ryI* zQDPm}x{k#*x655e%ogEwuEV_#W`*l$Ym=BY)H*J-MK{}Z_-$m{?Pu<@br^OXm2B;& zxsKX4b@xuc%+@wP>8``w2liaYdFF(DS$!z;3R@FV*HPI>%yryj(~7%}Cu~Jzx{gz9 z%vrAE5$h-0b>!NzwlC}sWezs|D!C5#4vWgJ<0b34itD({`boHs>uvSA15@UAw#2Hr zj^ReCyN(}h+o|C?ezj@2xz0SxR)JkZ4Q2MRnNM>ajcgL`{fU_)Z7WK59rpU{RanPW zHqi{%algGT*H`8vw#9^9$7ZuO&2=1Ov*CsdWzDq_rH>Cs?yzjfzh>4)cKX#8j!5@T z@Z1leu@+l|yvB;hSZo>cPF6hHVylpMiehbx zt?i<>Vl9hpLS9qFqb#-!d8aDYwAjvmXI=3~i#ax1Im$I$w)twVT-{}xu@=hJT(&uD zsa(}%o3&QT372i&S}Rv^*=DYda%Goo?%FC>a@l6Do$?Vb+x)dx&bHj#=I=D+ESGKm zPFK!!+2-#I<+#f>e`hMkT(ZqL zhV;;&GNh-X4C$pPLy8n-NN+_Ma+abDDOQvrC5kenkD?6etB4`}lrf~gGKLIL#*nj> zF=U`JhMc2}A?GS%$a%^ba=tQ#lqzG$AY}|0tc)Q;lrdzeGKLIO#*pF47&1Z`Lq;lN z$S7qD8Lf;VW0W!E0_DJv!pL-6|5YBgJ(kxkFr=^T%e}EtXO1&uqUU}<$~R<^29+U` z6=ld2MHwuw4=7{EgUT4PK^a3HQpS*nl`-TIWej;# z8ABdZ4h&fydD_;0m5p|4<6RdRa*mw}d5=e(InI!$J@>@`5skY*)sR7nL#OC1nhGSs6oKQO1y0l`&+8 zGKRdSj3KWpW5^rI7_w6tLv|@+$eYR-@|H4&yseBO?S)w$PdaG@}n|_{G^N_`;{@|XJrgI zpo}5EC}YU4${6ySGKL&f#*p8YF{DfxL;g_4kUy0% z$B}<+{a2Y_jUew6-;l%%*BuH+ojUFpQq%3%LhK+^&9!E{u!hzzq-K!y3#n1EejznR z)-R;S$@+!VOtO9lachk@LwF-b=NKF9vh19A5ej&9Q zfL}LTXI_zmR$qfL}

    hG_YXkU&)T06XLh3O9ej)W(0KbrW z9DrX)tpnf}QtJZvh17Zgej&9!fL};$0N@u=8v;y_>giruIFfIIB$l}*P9z*y)YL95 zc*lpMPA_NCNnvk`r6#%fP3jm9{09mPI9GS=5Iti~5pfQ9rUQ>Q9zM1ISo(HUNtT0D z02ZAKz@qa2Sad!Bi%J1lGzfr2g8^7H1b{_D0a!E)fJMUrSTq8FMI!-NGzx%4qXAen z27pBu0I+B*0E@-}uxLCWu&75kvdaWXEU~L|UQb!H*7iZ(gmBdPESgD{MYG7VXf|0ET}YNibI7vjA~F`u1z^!U02a*$V9^2q7F`U$ zqJ;n~S_HtNO8{837=T5W0d;!s2Tu^sspg71^|nW1Yl8302Unuz@l0JEUFE_qN4#=bPNECjs;-R zaR4l;1HhuX04%Bpz@qv9ENTG2qJ{u0Iv&8j=mY>3od^gl^3o!wnjnc5b_3kYNDEr} zQM;7rHA;&*znn#OzWznf*S=5Xyi*m@as5w~{wIIu)mSkDfiY$v- zld-4`0E^lJu&5mXi`oOQ=rjNpoesdFGXPk0CIE{%0I;Yd0E=<~SkwuCMR@=$>I}f5 zd;k^|0I;YF0E@Z;u&5A#Mcn{c)E$6DJph44jng92OpwGOd;g4gvMf5}Eb5sSb$&UE z&PwyHZ!C+78D18ZkY!OHvMlOLmPP%@vZy~<77ZZFqO-}eXdqb@okPZ=a{*X%9srBZ z2VhYt0E-3zuxKyH~@=A0I+Bz0E^>0 z1F+~)02VC)V9{j&EV>+kMOOf@Xej`Tt^{DwRRAoy8h}O109bSl0E?~#V9{~_7F`Fx zq7?uvx*iZ%G&L;}ZekX#c2^yz$)fgd$8KE^bi1x9tL31BLFOV6o5sK0kG(C02Vy~z@jGsSo9PCi=GBx(KCR+ zq8rm9T}+U~ID2P?w@Mb}*&BJhjcHNmm$PV7nl~y(7HwvDS+s>Li?)(w(KfOydVws9 zwv%Pii)2~!5?L0#OqNBjkg@1h02b{4V9{#;EP5S)MQ;GGXeR)Rb^);HO#l|X1;C=W z0a)}70E^xQV9|R3EP5Y+MIQjL=tBS&eFVUw-2g257=T5e0I=v&02b{51QtD)7P-;{ zNz`$-=%1HG9qg>y`z$T${Bjn3ndUvvLKc0+@UrM@vMlb(T`+V^b;A2_5-l!X8;x*0ASHC04(|yfJMInu;?HFi+%@SQ5gV>{s3Unp8zcS z3xGw309f=l0E_+sV9~z-EDA-`Y{#N70E^N9SQG(ZQ91yNJV0R4=V_6*OpruhyTjpq zA&U;WkP(SGznn#x5%1SlvM7t;Wl=U+79ByBMU}|1s4`g=RUylw1X&hUCCj2}WLZ?5 zj72p7Sac)+i)sR}=qLad)dFBqZ2%S>4Zxyf09bS^0E>vq7Uhs-QFF2^YC)DoEy=Q|6_S=1-u&2KM@`ZByM z>PMDE{mHUu09h8DO_oIi$+GAivMf56EQ`(~%cAqiSX2tYqCo&G8VtaqApk5I3c#Xa z04y2~z@iZVEE);GqEP@W8V$grF#s&O0Dwhf0a!E+fJNg0STq5EMH2y7Gzox3lL1&X z1%O3U0f9xuk;ok;NMee8NXaXaMeaLNy=jrC^UGN@E8=ZGT^7w|cv*BISr*M9%c6_O zvS=<@7R@8eqWNT5w16y&E+)&Og=8#R1i+$809dpbfJK)AuxJSYi!K9T(d7Uvx&nYj zO95DPB>;=A0$|bA04!Ptz@lpaSadA_ig6n26^S~(oJF@pyzCCL=vIc8MQg~i=r*z}T1%Ei>&UX`cCswG zgDi{gB+H_^$g=2eG8Wwfz@qg4EV>tfMfU-)=zaheJpjO>2LV{L0f0ph0kG&{02Vz0 zz@kS1So9bGiyjAH(GvhHdJ=#|PXVy#X#f^I1Hht<04#bIfJM&%0*h8hA~_~VBHLYc zyjd2Fw!5(2^O30Y%UQHF;uYu0qHPQ>i(VkhqU~f^^deany+oEpFOy}_D`Z*pDp?lo zAj_iH$XN6`0E^xLV9`zh7VQFH(VGA)dJBL>Zv(LC9RL=+3&5iH09f=s0E<2VV9|#F zEcyt5MY{o5^f3U7J^^6SrvNP41Hhus09dpafJL7J0*f|BA~Q^o#8UTG>n*Zqx@-1- z5s5m#oJHS6yp?&f=v#)DMf=FI=sU73`kpL{ejv-DAIY-lC$cQsPnJbLlV#BXG8X*; zz@lFPSo9kJiw**?=yw1Xl>xBm4*(YZ3BaPi09bSgfJJ`;u;?EE7X1srqENb;?N}5B zU{M+Xiy{ClN(W$(2f(5X02W07SQG;U7JU_oJZpj^HoEs0eJzWwc6UJH=~3sGv&cT< z@kzccs>JZJs4`g=RUylw1X&hUCCj2}WLZ?5EQ@N8WzmsjSyYpZMMnX!s1^W=Y6Gz7 zXaE)+1HhtV0a$b#0E_AXu&6Eoi|PTes6GIT8UV1UApnbx2Vl_&04zEYfJKb}SacEq ziy8y4=wtvEodUq3CV;@Atn^5vz%07iKAG%grw1+l58dZdo2EydU(TZD_L=6cvZw{a z%c7QKS=5Rwi&~RqQ5&)>YD<CMV(zJNsl_eoJIZ9y)oTn(Ex^*MQ4*`(Lk~+I)^Na z&LzvD^T@L3e6lPmCCj2gWLY$rj738LSTq!XMZ*ACG#r3MBLG-55`aac09Z5{fJI{f zSabmZi^c-5XdD2G#sjcu0sxC903mwXc_>ErUS5O1|YDgZ+hfv z6C^Rkoly6aMa!H;Gt;BaFK5x5bZ+kMOOf@Xej`Tt^{DwRRAoy8h}O109bSl0E?~# zV9{~_7F`Fxq7?uvx*mW;vcd(Z%TFdaVXdPJ=-Ab7g-kFO_oLXkY&+&vMjon zj79eWu;_jO7CivKq6Yz3v;lxc4*{^~VE`6A0>Gk20a)}H0E-?6V9^r*EP4`vMNa{+ z=xG2JJp;g^jQ}iq7Jx<10kG(K02XZmV9{nkV9~AVk)w;uqJfo7oHerOLidi@E$LC` zm$PVlx_A0nvgk#Imqjm;WzoxIS@a577QITAMLWo{=ryt|dYvqb-XP1Oon$Q91;C;= z0a)}F0E^xRV9`4OEP5A!MehNy=zRbdeE`6s4*^*85de#J1F-0002X}$z@kq9ShNR# zMV|q%XfFVZJ_lgY7XU2!5`aZt0RoG*rAG#vAc?x}AohYRTA6L(>-4De%USeYx_5Dj zEc%||Wzi30S@a`W7X3t)Mf=IJ=x4GlIzX01zmR3ouVh*D8ySlZ0o} z7X1mpqQ3xGbO?Y&e*>`S9{?8p3&5g~r)E1Ag#lQU2Ed{S0E^NASmXh)Cbp&8hE&z)<0k9|!fJL1FSdeR{$0j z0iU3&D8-PV;0kEhTfJG$$Eb0TmqP~E@q847Hg$a^4 z%080swUkAZ-NmDRUex*JEE?!}eFn;+a~NJ0olBNQ=aFU6`D9sCN|r@~$g*fKSr!c; z%c7xVSu~7{MZ*DDGy;G{BLP@63V=nU0a!E!fJGMouxKm*i^c)4XgmOmCIGN#A^?jf z0kCK?0E?youxKg(i>3jvXgUCkW&p5gCIE|O0kCK`Ah2kF7nx;(B$~PRU7szB9(Uhf zb)gq^emRTgdETmXWzl?wmqiQ6vgl&6ELupGMT^L?=n}FlT1=Kjmy%`C60$71jEqH> z1F+}{02VC;V9}KTEV>GSMOOo`Xc+*Dt^r`twE!$y4#1-809dpFfJN5>u;>N=7Oeze z(TxBsS_QzOn*dm}8h}MN1F+~802bW}2rRnDi#%_FBrbFByPhkH1|}@5@uJQzXVLAR zx95CWbO*!BqC3g5=q|D>x|=ME?jg&f^<-IeFIg7dN0vqRlV#BZWGs3RfJGYsSo9D8 ziyj7G(IWsXdK7>~j{&ggaR3%Q0l=as0a)}D0E?amV9_%GEZPXbqGthE^c(<-o(Evj zCIA*~24K+^02XZpV9_=}V9{DH;+2|3o80baoh+K}?tr}DMV(*HqL)4Igu$}t6^55Z zuaafa4zetIjVy~^C(EKY$g*fBSr+Xg%c3{Qvgj=`7QGF?qIUpT^ezC4-UDFK`v5HZ z0Dwgw0K02b{AVA00_Ecyh1MV|t&Xb%93J_BIUUH}$-4#1)>09f=T0E@l?VA0nA zEcyn3Mc)Dfi(d31-A$0hT6dxGC0P^>TiEAConOwPA3bmEP+9a7!^@)mWLfkxSr#22 z%c5V%vglW`Ec%Tsiw=@y(eGqgR7S?4KLA+tCjg870$|Z002ciXz@mQuSoALdi$WP{ zwqsEkfJJElEQ$cIC>?-B9sr9n09X_SU{MT!MR5QYWdg7$3xGx004zEJfJK!6fkoeY zk!wtl#0k!#A7s%>?(Dj9M%4M`EUK2_Jv>|%RcClvRD&#wjwH*Xnq*mY6j>J4BFm!M zWLb1HSr#2bmPN;svFJDe7S#b@QC$EQ)dOHreE=3U0ANu=02Un&z@ifXSac!)iy8s2 z=p+CZH3neO$p9=m1%O3O09e!%fJLVQu&5aTi*f*1)Et0CEdYT&OtLKMK$b-v$+9Sy zEQ>mku_zCKMV$dyln=n70st0u0bo&A02UPju&5gVi@F1_s0RRxdIGSh7XXWj09e!; zfJJ8ku&5Y-MI`_%>I1-{z5p!h2f(8K04y2+2rO!y5jl30S@gO)h_#VL``jhSvooU3 zFK5wt8Qz&=WYPHyFN;davS<)l77ZrLq9J5iG?XlhhLL5_aI!2KL6$`$$yhWBfJLJL zSTqKJMHc|DXei>3guXet1UrU9^MIsl7i0I+B# z0E=b;uxK^_i!KCU(HsC4T?7a$IwvDC)C5V?cW2k<%A%3(Eo*Z#qRua8(Zw0wqOr1Q zA;Zg}MPylY30W2`Cd;Br$+Bn(Sr%PJmPMD7WziL6S+talMOOl_=qdmfT@ApZWdJO? z27pD^0~j{&ggaR3%Q0l=as z0a)}D0E?amV9_%GEZPXbqGthE^c(<-o(EvjCIA*~24K+^02XZpV9_=J7QFz#qU``I zdJzyc8 zMV3Wxl4a3bWLfk!Sr)xRmPPN9vFJSj7QGL^q7MLA^dSI?J_2CTZU7d248WpK09f=X z0E_kju;?=Y7VQOK(dPgx`T~GOUjne`D*zUK4Zxyr09f=b0E_kku;@Dg7JUy0EP5p) z(#ix$Jm&7By()_qMJ)V~5p{k!i+;}V`c08V2N+%!{X&*SzmjFqZ)90?kSvRSC(EKT zvMl<8EQ|gm%c8%?Sab-0MSlaZ=pO(U{R_aNP*lx!ED8g#C=Gx`5dapY1F*;gU{MAD zi=qH5iUF`F4#1*J02XBduqYdVMMnUzs1g8+Dg&^n3IK}|fWV@kG9nk6Ac^(vKH7d+ zw99?Ov1&Bx{Bjl@8TD3AlSMTdUKSlimPNJ5vZyv$79CBNMaPh3(XnJ%bR1b0)gjBG zx@0V>2f(8G04!<%z@ml#EIJ;5MJE8T=tKY(H3DGKNdPQr48Wq30a$bj0E?Ocu&5~j zi%tb#Q8NG*O_`Bd1P7CnJkO)$yihXz@jby zEb0otqCx-`bpv2gcK{ak0ANv102cKEU{MhOi+TgF=qvyh6$7xS1b{_-09e!)fJOZP zSkxbYMFRj>bT$Bs1_H3?96(@EyJ#dj(=0mA?TgyWqDP%Y=SHK>FK5x9sMlz=EE>%4 zvSZE0OaK02W;cz@j+-EV>AQMRNgI zG!KA9^8tZH=SL$wO^`&)-GD8XMbFi>upk~FozbZC%UQHO>ODGF7TwG6vgkgtEV`d8iyk1$q6f*cXaiXm zJw%p850holBV<|hC>e_$17OkP04#a}fJILNu;?iO7CjBXqGteDv=M+s&jPUMIRF+t z55S^L04&-Jz@jYxEZPddqHO>ydI5k%+W}bgA^?kC0$|b004#b15Lk3~H1dH7l4$JS zy?>7^`ovu?dNmq#emRTYh$dJ|JV!hX5@42!KVq0a)}g0E<2WV9}=lEZPIWqR#+Wv=@Lyp98Sy3jh{<3BaPS z09f=j0E@l>V9~b#EZPUaqVE7$^gRHJegI(6j{q$C2@qKHS~OB;fmw84H52D`S=8UX zm4AOU>ilvR{TlT;E|f*TF}y4~NR~yvlVwpESr+|4mPLP(Wzk<`S#*dji~c6dqJPL( z^e+I5LNPVlu_z3{qBH;&MF3co4!|N0fJGSqEQ$iKC0a%m;z@lsb799b= zqDlZPstmxQDgZ1>0I;Yk0E?;tu&6p9u;@TEGTa17j6cf6`9&7J?JTMhi#orYMYUqy z;!9*vZHAXcN0VjIF=SbEELj#EN0vo($g-#|Sr*kJ%cA;ZS=4}xMGXO1bUXlyP5@xh zi2y8W1i+$`09e!*fJG+*u;>&37BvB2QBwdGoeIFBW&kY80bo&c02Z|XU{Ol|7PSIk zQELDewEK@v?Hnm9+rf|mXz?vq6AV^Qaqv*^s2x8qV-)Pdn; zQAe^Y$|cL9PGnh>N0vpM$+9S)EQ<=rvZxDL7Ih_KQ6T_}x&g4LI{=G%0I;Yh0E>D7 zu&4-tMZE!7bQS=MiUC+u0>Gj^04(YYz@mNtEb0%yq5%LbIvapR0|8ic4gibJ1z^#6 z04zEm5Lk42Eb_Anl8CyN{u#1pUJVPSv8eOQSu`}}RlQsm4P$s&G@LApMv!IENU|&% zMV3XQ$+Bn+Sr%PDmPKR9vS=I`i^c=6XaWF>CIYZ%5&(-P1F&cc0E?yquxJ_pi>3px zXa)d_W&*Hi766N81F+~q02a*wV9`YYESd|zqIm!;nh(ID1pq9%7=T3!0f9w>W05u{ zNaCj2Ce9F9@TgqN~WV=xVYo zT1J*d*N|n=wPY+>4#1-809dpFfJN5>u;>N=7Oeze(TxBsS_QzOn*dm}8h}MN1F+~8 z02bW}z@jw(EV>PVMQZ_Av<`qpw*#=~4geP23BaPe09bT4Ah2k0EOLCJ<);+PP^UGOuf6Tk(Dp~XZ!^@%v$+BnzSr$D+mPHSfWzi#KS@bAb7ClCmMURtZ z(Gz4WdJ=#|PXVy#X#f^I1Hht<04#bIfJM&%u;_UJ7HtAx(PjV^Z2@4>Rsa@l17Oh$ z04&-Lz@ircSo9JAi(Up`(JKHfdKG|0I{;Yp8X&Of-dJR-36i)fX5!o@i#~H7D|$T^ zb$&UE-i&!)ER#iVF}y5#n=FgoAxM%c2j-vgjkSEZR-RqK^Ss z^a%iqJ_TUW9sm}72Ed}d04(|(fJI*bu;@zw7JUW4qOSp1^bG)uz6D^>J^&Vd2f(85 z0a)|{0E>PEV9`$iEZPsiqMrd+bN~=ov@;foUt<<6cJI61C5sB&Th@MwMV(*HqTgd) zX2noU9v2yN0vqP$+D;cSr#=U%cA4Svgiad7M%#dqDBBLIthS9jR9D6G60KC0bo%R z02Va`V9}`nENTY8q8tDgH3wi(3jh|i1Yl7s02Z|dU{MqCB!J>P(hJ`D9sC zK$b;a$g-#_Sr!$NWl=Y>Eb30iq8IuN2UH~jA0$@>Z02ZAEz@lOR7L@?7s1E>( z`U0@19{`K`1F&cS0E^BBV9`JT7M%mYqH_UQbRGbU&Ie#oDFBNG0kCK=Ah4)IJo1qV zl4#|2KOJS!Kzq&`5|28+oJAwz-k}?1(MX1uMWe{FXf#-k zWLY$UEQ=iK1 zMF1?C3&5gz04$mhz@h~JEV>wgMGFB~vjZx{fT1R**47QG6< zq8$J%dJTX@uLH2?4FDGH1Oyg65Rcq%f+X6z_gz0Ii?%t7cEzL4FK5v^aqsmtvglog zmqqW9WzqX&S@Z!}7JW#TMIVu6(QdLV`j{+>J|WAZPsv!c2Y^MN0kCK<0E<2cV9^%< zEcz0FMPC81=xYELeFMOvZvj}e4}eAA0kG(M02ciKz@i@kSo9MBi}nMs=w|>H9ROg_ zF90n16@W#*0RoHOibsAiK@z{Zn;vh=qTcQ#>0mtS{Bjok8TYEMlSO|qyev9ImPLP) zWzj!mS@bVi7KJj^a+gJ6vMfp?%c2Nb7NwK1$OB+e1^|nq04$0DuqY0|qD%l5WdX1# z8-PVe0I;YM0E;REu&4?EixL1VstUlOY5**%4#1)s04zEZfJHR{SacKsi)sO|s5T(5 zs4O07XM!YdcNZG}kVVtn*U%iD8FhX+i|S;01MiSUbs1h3)g#NI`ea$ufGmp|l4a5H zWLb0qSr(m0mPL)ovgjl-7BvQ7(a8WTIt745O#oQb6o5si0IcB0{s1f*0KlTN0a!E;fJNs3 zu;^R>7M%ycqVoY*R0_bNK>#co48Wox04y2`z@lM*z@ko>krzym#KrC)mM4qWI*W#9 zMx9^IqS2Y&SNF)GF$^z@E+EUIv1C~^jx3ADlV#BavMicNmPM1uvS>0{7EK{z(Nq8y zO#@)jbO0930ASHf02a*xV9{&<7F`IyqB#I8x(I+pa{*X14}eAU0a&yEfJGMruxKFw zixvT}=n?=HEe2rGr2s5i0>Gln0D(m#Gb35+&7zCk9gtD7=zRAXkjpcp&M#-tRhix? z_sOEG8D17GBg>*|$g=2KvMgFomPOZ*Wzh<z@l3LShNO!MYjR4Xe|JX)&a2Sb^sRL0l=a=0a$bw0E_MhV9`AQELso1 zqI&^YbRPhV?gwDe1AxGyrJ0elOpwInN+!;gvgmkslJsC^)cNHsdL+}E{D3Tal;LI3 zV`N$MI9V1wL6${Nl4a3TWLfkySr$D*mPH%Mvglbd7Ci^RqUQlvv+DonOwP_cOgGH^`z77+w~ANR~w(k!8_t zvMlxN%c4)ovS<%k7JWvRMSICu^f>^Fz5rm+mjEpK3V=ml1F+~D02X}PBV9~DtEcy+AMF#;`^g95H$^d~y z?`B3mHbD|ExQ~6jCySa!E&P!gb$&UE{?7FNc~}P8vM5T%q8I>+;s7kl1Yl7X0E@B#Sabvciz)%Is4@VHssOMk0l=cF z04%Boz@q8^EUE#(q9XxVR1<(jM**;?766NC1F-0502Unsz@lRTfkl61MjAX~7By*L z;vAAi-@1!O$7MyGU(TZXSzhPIWKjc#mqiW9vgmlSEINTKi%ulVqDEv{bP`z>H73iV zlgYB^6fzby0bo&602ZAJz@laVEXo03QF8zmwE$pIO8^$N0$@>V02Z|YU{PBD7PSLl zQF{Ouod&?7(*am?1^|oB1Yl7I02XxwU{Njri#h=Ui|S@YMw=jsm32*=dRakB|A6~4 zqr9xB^UGP(CCj_~30c&Y;bl=FSr&C8%cAaNS=56pi+Yk}Q7^JADk96G-eg&H78#3* z0a#Q5z@k0?Eb0ruqJ97@>JPx80RSvI8-PUv0a$bn0E^BAV9|L1EIJ>6MWp~N8U(Gl704y2?z@p&*EE)m8qLF~WqWrALgCzAl4a2(vMicRmPJ#@vS=z<7EL3|qUmHTngPI~nE))B1;C=& z04%x?fJJivSacBpi{=8bXdVEI<^!;30RW3G24K-b02VC*V9_N2ELse}qDui-v;=@f zmjSToasU=x0l=cAfWV?LS&`pNki>iL6V?~VqBre1@5-#G^UGOuO_q1$Mp<+%!^@)O zWLb0_Sr)Az%cASavgih~ELusHMK_XV(JHbmx`~WMs{vSaGXRTj0btRs04!Pqz@pm# zShN;^Me6`qbUOfx?f_uXod7Jl3xGv;1F+~G02ZwWV9~t*EV>VXMfU@+=m7v0JqW;} z4FD{92oP9wbynmw6D0AxJE2}Ci=J@jMGt31onOwP$Fsb1pOZyTFuW{!k}Qj!BFmzu z$+GAfvMkz2mPOB!WzlnFS@b+v7HuM9(PjV^Z2@4>Rsa@l17Oh$04&-Lz@ircSo9JA zi(Up`(JKHfdKG|0I{;Yp8UTx42Vl_~04&-Gz@l9MEP4}wMQ;JH=xqQNy#v6acL9M# zk7h*{m>`Ky+{a-blSMn+j_JLusPoHN^ih_#c9SgH&G545W3nvzge;3bCCj2cWLfkX zSr+Xj%c9T8vgix4Ec%j+MPC81=xYELeFMOvZvj}e4}eAA0kG(M02ciKz@i@kSo9MB zi}nMs=w|>H9ROg_F90n16@W#*0kG&G0E>PHU{M(Wi~ay$(VqY;`U?U=*=otlqBOEBijZYdI$0KZWLcC!mPJvrEQ*n3 zQJgG`GRat!1;Cu;@qt7S#k` z(NO>_ss+HJ+5jv%8h}N|0I=v-02Unwz@j<;EUF6#Ecz!aa>Q1%=oojs=wDe>*(p^o zJL>#$79F4MHGM%Aoxt$2=tQzCYDAVrCy`}QW3ntdnJkM=A;RM`1As+m0TuqYRRMV$axln20~&HyaR2Lu*1$c~hlAc=MEn`atk2QB?8+^yMy?5Ok0S=24t zoBEdx@8s0UdV^(4!pUSwHRM3zOp$+GAyvMeel%c2spEb2qXqP_qu>IcB0{s1f* z0KlTN0a!E;fJNs3u;^R>7M%ycqVoY*R0_bNK>#co48Wox04y2`z@lLQEE*2Lq7eWr z8VSInQ2;C&4Zxx?fWV@z*^wJfki>L%iKtK(mANkvxgb00{Bjme$o8IoSr$!Xcv&=w zEQ= zSVDl%n-CNb6$BMK_5up_?rm?k1q7_9*t=ryiU=C}xvrV(z1iS>-_LW-^PJcD<9G5R zT=RMF%y+&!^PajTbIqa^dh=*a>yY}T7G2aj=xj5KE@pbO=n}G7bSc>^x{PcVT~0QO zt{|I5YsqHOI~97F`R#qU!)ybUgrzZUA7>jQ}jV z34ld61F+~802bW}z@pm#Sadr8i|znm(LVrKbSD6d?gC)Z-2g1Q2Y^NQ0(^@uXdT#3 z1c_Xz@4LRxEP7F2n!T@eNc~ca9%>yde8DVwnCZ=;f0E6jN62Q;qhzz_F|t|oIN2=P zNH&W$kJEZPphqL%14u;>Q>7VQFH(T@Nu+6};> zJpe5F34ldE1F)zOfJMImu;^C+7X1dmqTc~n^alWo{sj0Iz1uo)mk1JRsdpXUGmGwR zE8(x!A@xfw3bYBnEcdh9=4Lv<#5T>Z^n+xxD2Z$qg~(=6m~0lcAe%)k$!1Y2vRTxc zY!I%T33;-5&17J~i02cKC_!hZs0zZo&kq7mC*9mR>YqZ7fB=l?( zQoq!qUTuOMUNeghWO~~d9Yi*Z4knvLy~$=#AF^50muwdGBb!B;WV0xXY!>w=W6=Nr z77YYo(I5a84F+J*Apk5I0>Gj}0a!E?fJKJ^uxJE#%EE+>Liz>-xQ5D%NswSI7HDt5s2(no;mW)N?09Z60fJGAkSac)+ zi;e;<70kG&)02ZAFz@pOuShN~|MP~r8=u7|>odv+6vjJFi4gibJ1z^#604!Pqz@qa3 zSabovw`hKwz%wF9@G>MQh1s z(K@nObS2p=x{7QTttXpB8^~tS)nqKX27pD^0h02W;jz@i%fSac%*i*5p7(aiuX zx&?qmw*s)}HUJjg4#1*209f=702bW|z@obVSadf4i|zqn(Y*jHx(|Rw_XDu#0f2AO z#ccv9?}|mK`U31FW>HtYk^Nwskou(-J<=wa`Mz27DASuokCDxy$H`{VMzUG7iEI`< zK{ksvlg*+nWV2{1*(`dJj73iYu;^(37Ci&NqGthE^c(<-wgIr{c>or@0KlRb0a&yh zfJH9>u;^s~7QF(%qE`V}^cnz*UI$>&8vrbN6M#i;0kG(802aLiz@m2nzC{nW3Dk%n zk)NU>&OgnfsGcOf*CwQXsYM^Q2_Cn@Ec%G)&7zOVX3-~Pv*=T@S@ap%Ec%>m7JWfB zi@qeAMPHH4qOZwV^bG)uz6D^>cK|H<9)LwV0a)|{0E>13u;@ns7VQRL(H;O6{RF_G zp8;6Z2*9FW09f=Z0E>PDVA1aYEcye0MSlXY=q~^kImvcmjzuoOx9Ed5fwdw?5wJ0e$_{c|QQHbfyqA=MkYC$%OT9VD8R%ElNHQ6j`LpF<&$!1Xs z*(^#WV^IWvMQH#mY74-kb^t7D55S^y02W07SkwW4MI8ZHv=0D_Isve#GXRVB1z=GZ z02XxxU{MADi@E`@s5=0QdH}GfCjg7~17Okq0NeXb1p{4h3M*PyiMk2Ed|W04y2~z@ozeSTq8FMcDu>$^l?eE&z-209cd{z@h>G z78L@pXe0oOiU3$t48WpM04yp2_!b?Q95_G(iR{#u&JHq*rs&HdrO6@nOD(EM4iwZo@^FPAY;*y04zERfJH|Gu;>^7 z7S#fHt_Y34leD0a!EzfJOBHESd_yqGx*32)w*au{Rsa^=2Ed}* z0a$bg0E_+sz@j?=SacTvi|z(s(LDexx)*>&_W`izegGCd0KlRL0a)}90E-?5_!eE3 z9QZ{9iF~W?yT05k%1@B+&*YH$r4~J&9NgzSvuGpJn?;+*X3-O5vuHEfEZRagi?))@ zq9@5_(Nkoz=xMT9^b8q`o&{jha{w&b2Ed}{0a)|`0E=D(V9|B}7QF<(qL%?!^a=or zUIk#$YXB^I9e_n|0I=vy02aLkz@oPSSo976i{1rb(R%YHRAGm9n!BHI~H;Y=4&7#(1v#1T(EJ`MuMJZ&nD3xp$MaX7R8rdvr zOU9yh04!<`z@l^j7DWMA)B%7+9RXOh4*-ig0kEhu0E_koU{MzU7Ig(+Q3e2ux&g4L zI{=G%0I;Yh0E_kmVA1{nEII&yMZEx6bRfXDD3lU-P6UbU(A(AF6#q*9dVR<2K`9~i zOD*b~68vVjS=5i|&7w@QS(HUKi~5tzq5)*HXdu}v8bmgW29wRAL&#>)5Hc1W3c#YF z04zETfJMUqSTr1fMTY~hXaoR@vH@6>1HhtO02bu|uqYpZMFjvXDg-hxV|y1(k$Ac7B!@V)GxJYaY}IUFJ{parZ%&7u`#v*;8u7Oeze(JBBIoeIFB(*Rg>Isl7S1F+}}02ZAI zz@oDNSadc3i_QUH(YXLDIuC$FYXDeuJ^+g@0ASID04%x)fJGMru;>y17F`O!qRRlj zMaQKCt`tEc>+~RYyjgUD-aNWIC8U0-MOUT-AN$QLx{B$|qV;66Xam_Sx|(bjT|+jD zt|gmA*OASl>&a%(4P>+EMlu%N1i+%30a$bk0E=z~V9{*=EV> zX3?``v*Zv(LC9RL=+3&5iH09f=s0E<2VV9^c$7JUf7qK^Q+MH^EB2Z|t(6n$gb zCiX@8{-TdlLh6@V^m$5fl%oyE`>wxWdb8+DvRU*M*(~~+Y!-b(HjBO`n?>J|&7$wg zX3bEEJ^}kQ3&8$^l3_9o(K|oLjP{;XJ%1A zUsMaHhSV>$sC8;^O@dj}hUv|sWU^V5LN<$1$!1Z6Y!;=F&7!tsv#1@}ENV|Si_*zh z6a`>W2LKjz1YprV04(YRz@p9oEZP@0KlR`02Yk|U{MhOi;4kQGzx%4B>*fc1z^!= z02Y-2u&5k>MHK)n8Uyex>X#b$O$3QtqOYT6nners)!53^kou(-9g!OB95Rc>GQC+e zj%*f@X3L>qLpN`XcgHkI+ct?rvb3&bO08u24K+{04zEafJJ8ku;^?67M%mY zqH_UQbRGbU)&Q{Rd;k_*0KlRP0a$bq0E;dLV9_N2EV>kcMVA4v=yCuST>-$NwE*9u zC8>eaMUcqT86wV7v*;7GXkBVZ{ZflIqy}$lWfon{^k&gDWV7g6vRQN;*(|!AY!=-> zHj8c~n?*N~&7zyhX3;HVEV>ndMYjR4=ym`W-2uR&e*m!PP5>6&1;C=a0a$bo0E_Mg zV9|X5EV>_nMGpY5=s^G$Jp{m_hXGjhPXHD@0>Gk20a)}H0E-?6V9`c^Z_!n$f#*e# zNV&d@zuqjmQ9lr}DK(^isYP2;gWt6=i=Je9v*;)z^48WpS09f=Y0E=D&VA1OUEP4ZgMQ;MI=q&&iy$!&k zcK}%QE&z+(17Okn04(|dfJHk1So9$Pi#`Hi(Z>KR`UHSQp8|Y~Hm3&KCW}SG^%l_< zv*;{+HTJXAkou(-eU%yG%(02UDHjCPm&7yR&SrjFkMIFdyQAaWs z?E}D~P5>JGr79sn%r3BaQL09dp?0E-R)U{Nms z799w{qJscfbT9ymdIPYi4*-k$0zEk{sb6Z* zz({aoJF{pI)0;(u$!5_ZWV2`p*(^GgY!(eAn?;9_&7xssvuHTkEIOQwMI!)Mlnub5 z8~_&O0z@icW7L@|9Xfyze$^ckY4#1)c z02Yk_U{NIii>d%vR1NSg>K_SwDuP62>c#y4vuKjOz+V#ysb6Z*_((7*Y8Fjkdb8+A zvRQN#*(^GmY!)3uHj8S>X3<2lSyV?hizboHqRC_|ngYP0dH@zp1z^!M02WOLV9^W! z7R>};(JTNK%?4o68~_&01z^!U02a*$V9~JvELs4-qJ;n~Y5-u-A^;X02f(7^0a&yc zfJI9HzC~jrfrCYm$OC$IJy17F`O!qRRkSbU6Tvt^i=sS^yTU17OjW04%x+;9ImT z5;#@_iTteJUv#2b^o@q~k&ybO7F`<&UeL)bx{m41qU*_K(G6s?=titfMfU-)=zaheJpjO> z2LV|05CDrF24K-Y0a)}10E-?4V9{d$EP5P(MH>NFvPX-L5hQY6 zYZ2!fvuM5E$lekOsb6Z*(~;nt`a02X}?z@jezzC}+)0)L1gk+M!A&QoU5 zx)u_?jD*xLwdmVOuuFzn^c~ZiMcPFV9{>?EczXQMSlRW=uZF^{RO}xC(SO~vB(8rQ33#q0st&Z1Yl7R zfJI3FED8azC=9@&762@23BaOO04!<^z@jz)-=eQ0fjki;(k4yB`Nk}|R9_BBP7A4D zYEfERa7uTxs4df*MeWFDQG2pklukB_qGYqE1KBLt$Ia&A-yWO5_O+NDHZ7YSAHS!CQKo zMMIe0EIO2I77ZnvMTe2iqG4pSXgJv{I-G14jUbyv*<`aQhm1wJ04&M_U{O8*iwXc( zR0zPLkpL_z0$@=w0E02ZAGz@jw(EIJ>6MHc|D=t2M%T?D|Q zivd`42>^>O1z^!-04%y3fJIjTuxKp+i`D_K=t=+=?;hkh73o8VI8Jr? z@}Z71F8#@2j&oFc>k*DKF}*U!ai*kSmghLr)88*}oZ0C;iyUWu`pi*|(~y2=spBk8 z|EbJzmZc9H<2cLHPpNX8Rq0RHIL_+yM@f_)N#SEq&E&$GJ28*}0B$Z+hynj`Lvp5epsXk@R(o z9A{(tN5?zPmh@gr9p~xvxyu}9Tl&2xInMU?l?Qr z)6R69PtwPo?KoegUv;kIe3Smk8pqk0e$a)EvpaqM#g5aMe*dM8^LzC7%Vqhy(cE?V zT3dAWRk8-$=nETU6}ZuM*UCC@qZ6)|mEcA<+$d|ojed5stOhsQ`!-n*ZdCu8eNQ*4 ze~!GD8`Zxj-P?`o9|X>Hqxu(J2f9)Hlbl1`sQyjGVQy6aC|faSAb)))+VJh6H{$-D9H>!V{VVoP)@76!cjp~=9PjsXD?bcJ=sD3^1bT_KsFFV_f z>KBC0ccc0Zj}2~AzoKuk8$E7^tR6S2Uy`-ljq0}?t#YIKH8rcw|&+~7v_({9(fQT@2mO>R^_Z*rR()ej8Z=|=S(-}kyv zear5HZdBiM`G_0UH_dHyqx!C=EpAlbw(_(a)%P82bEEpg@pd<=ul&90M)jqeH{Gb- zdwdn&~ZdC7ned0#-_Qe-&RIfk3aie+xvD1y}8Q^X=s)z7KH>&&K-(9EG{8gx8ai_Wd`yU*uxnd}ZqK2L`Kl3!UQPN!Rwg$?$Y)9G#vhgf(@`!FO~ zoRra?lis<9+9N%>NEm8if^5j{VHWB%46`s=yD;3sN8KeHZXr=lXxtGN?v(w3o9&0r zvb8x=<#}xE<2w7g6$#<7PG{MooQ1-6`z+XcMEO3c`?_P2B9C6U?&-z*x|K^t%=`vrYSuWFbmhHi7Fw(cF!8@$Me4hnd*LSU4A`J#xA6%BbpV!_! z_g}eUnb+RKXT5g3(?vE2=NxVC1#54jKdqbTbe<^B<_dZ2BAP3G?urJlxdkT`=6TJX zb>^nKw0lXBx9|DKe zyNoK!?)}G3*(S|b23ucoY_ZH*7Tx2|yqW5B?JUaZG%|j$^|fgS^zuf(5taraAZ+bWRUDY+&ZaZ{s?lhD&?)#`9TjuS|C z0?9*L9oFj5R>f^)hi8xI?ZZKilBE5;5=wLf$%nUUC1d$xyYg7LmrUHbmE*MV24tzW z^af;6wX$}De!HzxWRBWgo3?JNR!uD=w{ZetX5Xq+n^vt`4UzUzqRqxim9gSF8L?<> zr&*H{wNq`aN$=67Cfiw)HdcF?DA?4G^fvM=b^J_G;GI>j?xQk~B@#g#RZ)mB^C_smmVC!xdnxw74Mkp~=o zz;U`Vj=0d*8PRcA$GOQ~Po(dT_v5;LmH&^BU)QP7qF>qKI%BmYiFt|6k8Z_!9cnGV zGL9DA|M?HZTG(q~yw~6uE$_-ZeO#wT3k{C(8cg*X9HV8RH&~;Ew#TgBt4WK)yp}7q zXmhSpt;KIk-e*l))$wgr#@b4dg9=YOECUHn=K4uer^s)>3FoZ8R|f9)!}3@!bu4<* zSq5a;$d5cB`_Vqf|HS8Ob^CB$mPr!a-^5f`eq>zvb^G@1x1g@y)P?i=EnG0U--6nO zlk02eFPPU*Ke?fPO25eqmdtOMr(kmZltl~b7sfrNXz z!hX{xPp++7FsENuX6=C5{+a!=YO^vG_7T`;?!3A6ed_Bb&FGVr*>^x6eYmeY-0Y!# zGv-d7y=Y2(zd3c2r_Y%C|9LkSE?F4AB&JR8m$P8Xq8W4N<;`1A-zT;#7B?*L7Ky(^ zDi+L}Da(9ezpD9l3uYBAnp;~f&t+Q0>_rP}D{}^q9>i*rC;R_m>;Dr8j;m{^*LC4I zrqQ57`c78KYNymsty?s^p|)Yk{Q8A`r>nan!ju_v8zcneV7zdC?c{lL=FFR0TQ`4( zFwwdyub@^I%H%wc3zJU`N#>n^4+N_eqewb47UAuKS4JsFwG6N4|MDs3=a#Y zl?B_D27^gOZG&x-WV)n&v6|-P!<~dgw|%gcmXu&OEyBInS4QtIqqhzA>>6yF@vkNh zcGE_@iF*8pHrgk-8PZy}VB2DCrC-0GKl2i+!>v=pz1*#PFs-+Ym-%0HO_~h`OPU(> zpJ7uYUH-d`qz%ssw(S;7J3QDnu*83&X-RGS>GX7!Dr0%eO{*-^u74Y4zn;OgAwG43 zE%YgL2&QOB3GU}DDA$jDy$2Iy3HK75AdN<~g8ThH#JVyP0>}0BTa(j~U}vv+MQJ+Z zuP>cnMxc#6S7B~aY~^Km(FD*X(Lc6|xrwoly_ zyN!?e>bKf2*hN$iX9Qa$1=2qMdUg*+yNIH8viYyKEO%fqHL&%>VL>hkj1((ywuTuWYMsj}Y&J?><@k!~a(T+7rL`61#bwn6_LTeE_&HMLDsMpl z+6M0#i#`b}zM-fF8YEiNmGEw!=5g~hcw z6<#m%%FD_M^3)d3yuyLHz`VhHQ=+OSFHbCuO^vc+Y6@x!Y71pa#U852sVuG@AB!sW z=$x|gw(6Ri@K#$@d6n0Le6c##fkEESXg|*E_&N{T&*m*f+wbhk5 zWmTh#tG$*h3v%+udru~}nXr{rInt1~s$~J2*vzxMDzCPxx?GlNf#_)K&|fyq8j0JU zVo%uY$tm^bTw7jIP!@X(m2)eLM;29=$r7!tDyXj3ZJAjY=9QLs-5oH{-*N_dbM$7O z3Gy~34~fFIu7=oyS+e+ItrZtn7Ut9zqdZVmrzHu?3bJ zw{Ua?HO<=hJ?>#y5wb{X3&!OY6y(Qs*%pZGVXJdw4^dJuzP2!@ShsT4p^c&UdZcUR zHI*_T+gM>~abDA2-?LPAX0b(=)jzg@%cky>FKWoIYpAQOu3zl$X0l{soU&-noF%at zdD})od2#b?h;GO}d31TDt{dHH`WtkAZ)=%7Z|<}V*@Jm(pv=pA@>w##w6Z{}%A1Z^ zdJKp?W;@}^g3?YaPD%@!B>OUR$g;JCSXJ0V?Dy1VlZZPv?X60rxU z&B@EFsm#f<{aLI(MRL#^nD*n`qj7WfjC$qYlQpX;z2`vccEbu}`|$G=j`D zw=zeL@8*-vQPxiU_9TmneQ#-bRg+EehYvaY73bAfn1>?y;Nj`FXGBz=(A`zkj|RMJo%+^2O=6U3N@^JnwwT%#x)z zcUpaI{oE-t>gLw!78h%*xU{rjWKOAVm~vu}FT07RBcr!f#13L{E@Ta9wq2M|Mbc8- zd09SBOIGe)<`nB5bFY0>yg0JM@HTXB@x->DtU=8hVk7(Ce2IluXuMnN&Gh@1htVec zO7qLTJ$US>Wv2KmR(5D6L{^p^9p!8xwi?*4WY*@7sjkg0@=q9=pIr=&8{hVcqh+sG zQ|TQCz5Q;XEY_-`xZOWnKxxi+Jy*2@ybQ_iaO$GDlQRbnaN^TI>uoc^V_V8z>kD_{ z&bCWsOKP%*xsS{lJvygp?&7nY%&|CRd-rBKByI_LZjCIf$;dnO&N*U(2^)*3E* zkSPje%&GH_8`Njv{615%1`DZMFnRiLd7bOHA${ibog=T59Xw^>{DY^?&*(EPqfdGN zj6U)L%J9k3fj(2`)Gu6EH?6+U?E1OW8m14=6y$HAebf+1x-1)J%$wV1p}fQ-b)m2+ za>R^f?KA)W3~08)ZrX3?#urns$zVC6$sVOz&TREGAvOYQ(Ypj|TDh`?=E+G% zuI$^{C2P0klEUx)Ax-O3P9}WT{Q5_)PV`))SS~;Ovljn(d-BaFoi}fOmgANFf9p%L zlYnL?+M}hV-12dMn&rKJCd!66gp0oLZW}viGU#l#$r-yh;9sVCC^I&e zKg6*!?$pyeVV3JEJM+upxFF9nZb8LOpl7nOxAMI3=GSz=8M{&*Y_0g$h|JZ0#s#A* z;x7F1^j1Xt5l8zSf8AO%R_=DlIf`9%%Jvl3E&SKhq1b{2#$S~Ghs(dh;==Og*QQNE z<>%yiuf!o+>k+_ALQzIAla>f^b zA+P6OEIMDNk#bSwpA5ww@C??|;_@=xKX^y@tpE6^ZA)^MXaY4|95%n^QwL-2(~+u* zVmW8@uHAJ_ajlsXYfTOWG_2=NHV-*@wxKM!wutpFZV6OWmKPPv)u*hAGCAp%yBW;V zQ$#zWniR{~?*x&dwpQL$&~$GlOHSWq2Hq7*?6QRhbY~W?7#vXwbMoaz&|X*Ao&-AA zk>Yyne5dK!E8mWdS#qVqQow=!@zVR7skf-;gZ6E&V|PxK-js{o&yj5?)@bZ% zFelf$Jr{c*Zb4QSRR7CUaBt_xWxMvozsU3YB87^0?>Nd z)RNpFsM7snlb1TmzdYY%iU6SX6Aiv1gdd2t@GaO8rbrnKpNLv`mACjLw{c6+Elw}(_Xew~MNQ&W z$>p)!POw`BEV#HgR{d|iohZM4(xPeJBGt<~o``OXIk~=E{=I1);VBl%RhwMk))toL zR5eYPPCjLRvThsondmW6w1MXe@?X}}* zI*ZIN_&4W~x`xLW_*cSQ0yf|H)m}MiDUjP9a!1xbVe|T-x3j$g|0ezDoN={zWz}{x ziN8nfb?xuRM*lL4=NY?~=QY`MvpY*}y~S@!O}B{j$@*JCv%OF35?@=4Eynok)z~$% zEnDwCv^QIJ;Y|lG|E97&sF!r!NP35rUVBGdS@&|oBu}=pfBlk&e+RkgQ1rL`OqO00 zcx~(5SlW*7a$#|)oRP)fJ!m>7sjAAe*M6EU2joRYxr1t_3iJHab+7dI50TBfLDU5`+jHrqAR{shU-a0K(|bnocTPPK{?&ok-wns^uFq#6e{R<9n+2}1)@1n_H`Fi)3XA{5jo4o*IPqU`1q^x|bzZAHp(L4Csu77nvOSy8t zT3(IwUMcY&)(aLMj5|$ecFV-;p58dt0ll2@fZh`I2K?K$I;a;g9*VykYOU&R_(Itv zxX;8){pZF$#WupY8>`K)G&r;I<{~Q~)^~5)lLJMIg7I68-xF!V+k#`uBd;`PbVb}z+F#82I-a)M^nzB?iGJ3=*p7}(BTMgI z`dw?bH_54x^YL+VW!y~ixbFGO!QXgzK5PRju)K7<_YF($oTxA-{)B@m7*%@`cl{s- zJUbioj|%#*f1=MUEBv!(xzQF|E}kc{&)~L8(+eXaxHZ>w&K_@A(>_*jSI585L_huK z>n$%?mfnJs)2jHLOY9IYuZ42-n(|uC^6$LuhbQad^ z(nFhsuO*+j$pNmdMKTx4~jr@lE&C#^%T+H2cuK zrqnw(dc5?PPt)B@y)PIWm6u+;i?xxJdTG4Z;%#<$s6KhyfnLVY2wls|$&)2rSnD0{ z9i2VzZs5vB%`$1?FJpXN_L^_r==^54g7g~GUlX?E{M`ke@b&{$|L#>!TbT4TcD5Av zN|@d=q%rS!QHYYe1#>bA=1i)eGDTjTtL7sn-Yt4QI&$E@zhN(* zA&?KDIe*EIe3)rja_cruPyJwl{pbg3a+7&|C#{J0W)Z>!2 zpSD+)&;AS1Wv1&VO`h-2xH0s(jNU8j$6@)=$7c|vYCe9ieCl4APoa1(!S!r#dQP#! z(SLc3|1VzXj6bYp#U0lE#VcQNuLU$e0QUDkJJ+(kd~RC$+EPBFJ6o%KlJ7FD!f!FI zpK@&}pV52P_)+r7nU)SC)WSzTrIOsi|GUSf5f)oZNYWc3cK`UymR zUJqN{X!S{}+pNA~^=+#kTK&T6_f~(h`iE8hu(!6~%4(X`j#e|Q9$>Yv)j?K=S$zsKssRySFF+Uko|U$^?6 z)laN`ZFQH`U##kGT-y&>O}5(JYGXB9_S)E~ZzSZNc zo@Dh@t7lui(CQUdueN%V)qhyM-|C}Qw^)77>dRK&vbw|S=T^V7y2tA8Rs(W)(&g0B zYQ$;>t6i<`Z?%urfmRQ*nrpS#YK7IYR*$h-Z*{iSg;tkZU14>#)$^=gV)aU^*IB*Q z>fKf!vbxdgQ&wNF`kGb!AhSO2kF9=X^#`ksR{ye^B>Qz8zl~M>-T=*=tai70pw<3X z53`zYb+pwZtkzncZuMBJORcW7dbZVztzKnSzXDzRai`UXtUh7&IjgT)eb4G=R=>B} zXw{VimA2Q?YFn$Ft?p;Fuhm1WW?L<`T50u2t5dAbv3i`K|71=Eh+RN%NIStdti>w|a$8OCttuB|7Ld|De zy+)4Nn(wf>MGo+qw_E*8PO>!bvU;$bV`v^?^;kKl(0r2B2jrYV^A@Xr$S2k{x0JsY ztu?Q!Un{Jh(aq17SbedFpWn6Get$oAw|b)sbWTTy6E7DnDOg^%Xhc z(*EwS+Hstp_qSR*!Oyd;UVoII@3#8&F@A2enpNlL!>t}a+0U!2K3ebRXRQXN`#IHW z@k~D-VfDP(eqLwwwYh%&$ZDr!{oKoH-9kUlwR+em=>oW?^Xw0=;vIkCtU33)mArM>gN}%hOY2)JFBDD`FVoX3$OC?2CHvv@bhO@yI$+( z-d5|c_wxd)x8CUI2d(~av!DO8ddO{l&bNBv9ezI3>gGHByxnSxd;FYkwfsImA7%C8 z2mE}E)ps89^A}dTJ>uuSR;NAY=LV~{Z}juSR)2iL&(3DQ9=g@9g;q~~%Fkz8-TI85 zU$)w6o1Z&a9rJ>pkFk2`c0XTd^}Uz<{FT)nulYIC>Wnx1e4N#PyyfRdtnPWo&k67P z^|1H-T4Z&_4nLo3^{J2i{HoP9pZa+pt5u)-d7{j&Dw>oR5 zpBG!bYnPuNv--1KKD^I!C^;OY>5z_sDm5Y2Ik{7x@w|%}L3A9UhD%F5t0!AsX;ltG-s9(5z1ZsIR`0X=kkyS=w^)77>Wfyr`zq3(w=I8Y^;4^VSq-@U zeDx2mY5!BKdiPHxcecErRngfSFG;7Dg($1Y%Tl~5mp5MhP_LV1dijQ2Cm|yDV~jg} z7cQC8P&Y|x!veofXGq?a-Qe`qw?R97CoNp)^p!Vm_f^=}zbW@$-p=zTn4)i^k=H4v z&Xcyh;krqa7Stc-H|G=iDx~;Ww?IGdU^Dc`_&b@cUu0x0N{^ks`u#ZamZA8DrY@+P zBO~Qhj_zC6(6C^}q(u$V?0@&ClZ+^fH+DyN;9e8TBK3Z{$^SZDz>m(}ZBu$|Z+>KalsU^Q)6z`XGbObs_nB zL)q^5Vd!W9@$J1T?PZHA+MfEQZEAaS4S->%0^P7}RZwVIA+FLtRJy#eNt( zK}h_3+nplwl?Qdc%9*cji%cVf&g7x4lc59l!(+Pb#^VJ`%Y%7{G=eqI@qVffNGOYU}ZBLiG&Xa9J z2Av)AT<1a^upinJC7X?Rw)Af|BS~dEzGSPe@4S8)@{@H)=HMZj{fG1)BEy-PS#kdl z9z0OffFYSuGcqQ&Jh`B>(EkoNzhPJI*we0(i_Z5_(BIa3IUQw>`axsw&3(RXEPuE0 zk-C=a(|2}F%HBD2RlCB1pAx#SC~Q->t#MVxrcv7(!*$ylw`9EAnApuZ=(o4Ce|kSF z`=@n7vwxaC|AWT)E9Lj&HybN5wlzB4-fXP4I?n1*UftIC%?9~R{YUY(M){hkuG<=S z>=-uSC2O&wF|prextnDAJugk~apR~nCv9p>%(|iE+EJStcVxaS!_L9Ky*;kSfzv-| zTz1V9jZWkVVe3ntkVoIPM<-(_ z$FnlUnvxG1Gw*&@rhjLz>CY`WZ`66kYl@zWo4&Hgb28T1GR^N-Ki9Y=Hc!W!XZBB% zmYr67TFK&3GEY}p-}G$b_S9!(JbFHBy7W2gR`36>z5frMp=8!5#>m^%qubgZ)0Mh6 zdH;Xm{oiY*lE}nYCQTgGcKT)R@2{5c-dOcY-O;frXXzMOw|f77?frl7EG5;kF|_UT zdrVjA-sJuNh4+82*|c3OZC@U1JA2op0lIw4cP`I+qH%j>(XRUzJ|WL0JJw?EuC_g9 z=+u#$z5l=T{y%WeA)}QQ6wBDDZ6_W){R(&UkJ&SS_4=GW>g&4f;+&G4B3&cpyO#&P zuG`wU{pzo09GT$!khpSK$?#Fbix2l6jr90>TK2B$go)o|TT6#{j|U0| z7j2d2s4WHL?Ho4J}5R^zB8d!$*zq{%Xe-}&e=7)wY2H>C<>Hp zZEU!+Ti200+U%2@AzyKw?K-DBI~;fUhJd^L(_uZHYxw@^o#(uI(B#7D4_B5wQ*`?+ z3(uT+@<~hAwNCB+MPgX?6agpu^wm2O3RImS?c%rR<-kOxi5l z*#o1N4a7Eie8kzgvaYiBymZ&7s(D8THvhOhN7vJx)#bYf<}J@C-+k4hSL?=1E8qQl zL-wwux(^y>Z+@cjn~fhdPPaNmYo`1<%5At}y%_LKg{CV@*6MJ!{K^%p*Zq{ji%TvjeY(+cr2pNd|Cz7aTK2c)U?JP$mPTicPE%2+|DRKG&Zu*X z&Mnqqr-zu7@KN2C#_d@j&yd%Me)w*Mti|~oyG`$Yddbq!*G@XEWQ+7bep9!|T(-zu za7p}bUB0_RySEyhjFV(NJKat!mZh0_;;0iP?bvu?(KmHX^Y}__&GKzMZ^iMWj@NNA zCXG6HV%zEK{B5T?wa3Duql;gyOO@@l6(4UQL~HZ6n*No zKU>lqNjfk6t?XV}I!k)3z1i-vd|G(n>pWB!^;>_G{Um8#{ zVAR0kf!@3-yU*R>Jg(bjwtl0eoo~xc!4xfsrXor++(Z%Ba=H7j8-3 z=h?uQGwwO#BiA|4$(HdZq&P!99d+}^AHM$U{d@YJ{A2$uJNn6XwjvaE!hs=fI7RBy zH9wwv*2?{F7}>4#s$*9SS={xS?4!@0bL@?)&p4uPdvdSrRju_<>n?v{^(CF3{PvF} zndiF*csId|BGmaS^i=Katua{4iURWEu#*MZ0?@@CSTs8;f!07-Q@$E%nTzm)CyyAVdo5X#*|H>4)l55LjLF`W)?-NNOLbMUbjSNkx7(nSrBh`2b{kmyuvZ5Z z{p!`eqleaKjZzb3%b(nDlzKK8FRJrA1r^`sutuQV?+N-{=uEAD1nz=@xg z?{w4sY40 z*E|1{vp{!>+&^jESFXAe^~^BtC&5ixEhoqcZunF=M@&cve$ie_=;Lm(J|}dS;n5vN z%lHY2!As>rC6Fd(sR`vBCweGUxsRl9u$RJc=wZ2|keC?MkMkrXhK`no0-uX*f!=L% zWc0wg4EZm!U9}7c&y)X>PL?zBP~tKfOe{%mD_2gTm-JjV^r>OR;n40~xbRNZ(e`HT0Q0nh|E>-pm{U)tVkw2Q_IQ5~GJ>^d>gjRNToM%Ff(&uMG`^z5TxzJ70w{4-R z@_e5UeIsMO5Z3ef-fnnbnOPq z5K)8)~_e~)DwJeu!1K}%WVSE<|-ziJu`#`u%R`bq4xSh=5hd_9h z%&#;te1|kWIx$=%y)H`(t0v`%;o;I)MPj&6S{aiVPLk(dnHcUVr7AIeh|I4#F`OY2 z)Fg(-ilav)hL4hUJ2o+#ErN|p44*Duj!z6fCXG!<3=fm_a%5t7hOD-u62tq6J9j3A zPnAxz3x-dUXVg9z?kY=SaWH(0ETtvE@V(O5(qOo?z;}b;_oU7Dg5iT@LB1ah?;}lr z5Dd?ezU&Bw_md8O7z}TgrSwrSyh!@8Jrw>)#(XIh9wC#z916>Irt?ZDtnaOOH5C3% zy7XEoe5)*p*F#}_gT@=7@Hg^|-VBAGm&xA>g>RGYKG-U}pBVj6tMFQB?BQ17R0x@~xw ztj#mphBwRPsRxAbmJKIzKv-WkpC1j+lD-@p4Id^wTM!K&F0)-24eyjO8=~P`WMM6e zhPTS9IxZS^WrZIf4Ns8Ozc?DcF;Ny)G~8coT^bF`7alq%M8j9hl2{fEZF08ldMy?Cj$daho93CQ%joBQ&UfP`aRrq$<0_wgB>z}2b^i}vcS;&(m$#asFWvokq-PK&--E>=q|HZGFb-dWzj9wfkbIX zc9~9#-((%?_q(@fls@Y*pv4rKyS{O=MMvpRq7Hm7i!rDJ8$=uV!v;=^V`NQ)bf8j5 zSO*@Kd9~1ir)5R7)PdpBaw{G9NygEWh!(wNSvEbs&!2uU||I;Z6(X((~78`vPZ z)p_z?rmWM}%Va>lkk?ImUFO^-QF(G=aR1I5?_ zrc2C{Ze>|+uUY!l-*P+6(y;-S+iI4c4YZu5S-LjJazwNAZLsB3&C$o z(J8o}|K}6;$UY%BGNi{NHKZh1D~frBl-i_b$Y_gZNSQ@5q}-wzQen{y8Dr55skCT@ zR9Q4bsx6u!H5M`C2+J5U)-r~Svy36*En~<8%NTN`WehpWGKL&&8AFb-j3Kp_F=V1; z45_n>A(Jd)$YjeHGQ~26)LX`osg^Nhnq>@`ZW%*nSjLc&HA5CyG(#3zG(#FJnjwoUnjyzoG((QJXof7d zXof7YXof7ch#@Cf#*k%}G2}$c7;=(j3^~~{hAg*?AuB9n$SIaFWTj;cS!EeRPPL37 zr&-33(=B7jYRedMhGh&n(=vvfWf?=xwu~X?SjLcZEn~=emN8_FW#5pwfoo;`M;??j zpWr;-kRmyI3Z5TQbJUQFgV)O8*E8f2o74=s)S?-3nME_?a*Jlj6&B5qwHD2gbr#K# zD=nHKS6MVe)?37o4VE$FYRedMjb#kE)-r}%XBk7Tw~Qe-SjLbWEn~<{mNDdJ%NTNt zWemC1GKSn{8AEQjj3IYe#*lwl#*jNLW5`{WG30K`7;=wg47t}bhTLb_H{`;=R$2d% zBssAOUgR6nUrvpJ_lMLRHRR#oRyk?%4Ed)`YKA;w(F}Riq8aj-MKk1ai)P41i)P3s zi)P3Z7R`{&7R`_?7BOV2Wej=JGKM^58AG17j3Lih#*k+%W5{!sF=U%%40+x%hP+@I zLteCuA=@ou$V-+naLq4)-hJ0+%4Ee;O8S<$` zGvqUiX2|Cj&5$oFnjv3W#E`EnW60N*G2|P|81k)U4EfG7hJ0@sLv~umkRL2#$S%tm z@}p%8*=-p^_E^S{pDbg@&z3Qy(K3eoVi`kzwTvOZS;mmxEn~xmecZ9Pt3@`jO3|OtM*&MK+82lg*+5WGos8z@k9_ zEE){JqC)^!Gz5S}hXSx@C;*EN17OiG02U1gVA0_KEE)m8qHF*bvRPC`HjApsW>F23pxXa)d_W&*Hi766N8 z1F&cg0E^}Ve2Yrmz`G(y+H-QZE;!mOI#o__g7e&v`lS{vbc6cI9?zl%rZ$&7u>?X3;XTS#%;9i%tSy(a8WTS`NUX6#y(c1%O2>0a&yO zfJLVQu;?@Z7M%{jqSXK_Is<@3X9BS3EC3dr4Zxyv09bS`0E^B8V9^=?7M%~kq6+|6 zbRodE=vX($=utPQpCa@udW`AKqQ}W*(MGaaw25pMJwY~$Hj~Yw zEo8H3E7>f1l57?|MaH710a)}50E?alV9|2`EZPRZqUQlv^a22jUIbv#b^sQ=1i+$~ z0a)}30E=D)V9{#;EP5S)MQ;GG=uH3?y#>Icw*gr64gibZ1z^#80Nvcl5r9Rz0a&yLfJHw6u;^z17BvE} z=obJM{R+UM-vC(jI{=IR0ASId04(|ofJIJ1>?+^CMsopJlmPH8+TjLviy&zu<#o~E zhi1_=`ubELA*6n(MWKYCeq!0PD9rR`Q46wJ)RJr#wIZ8Et;uFl8?srHOg4*B$YxP0 z*({2Xu_z6IMQs6C)DD0}?EzSn4#1))0E;>Ru&5&di}nFvQ6~Tvbp~M3z5p!h0>GlK z04&M?U{N;!7Ig<;Q4atX^#owiegO7G`vb7(0Dx~%Fd;Bh1WC)67sP`}3I3J-HhI56 zuvbDz{Zfm1Cj|9#?w&<`nBFYvOE!!8kwx9IRGrm1z=Gg0E_YgSX2PO zqCx-`jRas(5de#d0a!E&fJG$$EGh-~79ErjST2I3y)ExO2_9?~Juf$;gQF8d>X%wH zCLyTbj^J5T$@FGX71=DRCYwbyWV7f9vRO2iY!;0pn?>WvX3+$)S#%^Bi;eyGKtgpm5B7OhPP>Nl}?7Oi7?v*=2) zS#%ZIELu-Ci#CwWqN~Yf(KTeV=vuN_bRF3&x}JXC{*)lT4JN%LIxp7bv`-*S9f}^XL(zkFD0;{aMGxDd=n*>< z6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0K+($rMXv}Hy(&=jnn2O(0!42K z6ul`>^p-%;+d^H@o$V?oCm^+s`AhV7g`)HGcXzzgu9|&iMIW>)@^5`=Q}m(ZL(xZe zDEinAMW5KA=u+M%eM z9g3RmP*k%+QFl8O^{^?LNuX$Efua_HqE>;To&rU^1d4hK6wM+~)JLGGuRu{hfujBb zMFRwi1_~4n5-1uhP&BJR(QE=mvkMf>Ay71@K+#-6T~UWhW$*$?(aibIeaA}uo_?Qp zY0O=zW?xy+uu74C!(5x9;f@bQBkWK#(hf!Q+M#GZI~2`thoS}SP_&>OiWag%(ZV)G ziwG1gDp0hTK+!0HqQwP@mJldfQlMxlfuf}aik1;5T2`QFIf0_(1&US>C|XgVXeEK7 zl?94c5hz+!plCILqSXb8))4B7hEytBCm^-$^KH@4P_%d@jWsLP>?kPF zgu0^9mCDr#NNtn!LrcY&P_%0P6yy$-YW9^C?NTZ7Z?kMuw5#Jo(QbAq+T9LCd)T39 zPdgOtWrw1@?NGFj9g6m~L(zUVMf(dB9UxG2pg_?<0!0T46dfW^bf`elVFE>m3ltq8 zP;{g~(NO|LM++1kBT#g#K+$mmMaK&iogh$jqCn9}0!1ea6rCc}741~1{Fs2$PRL(J z+c^}C&5BN~RI{(F=*&uye+O!tqO%+yiq5t}(K&V~I@bm?d^;3fV27d$?ND@) z9f~ftDY`_U=u&~A%LIxp7bv`?T$9g3c?DSA?%=qZ7srv-|h z5h!|Apy)Y)qUQyQUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc z5h!|Bpy)lJuIQdhW#0s(wqyQQ>w81dX8CUa`;}_;l@)zlDe~`IZo4h|#POl%Q#%xW zW{0BB?NIcE9g4oRL(x}uDEitCMc>$==v$kj?*xjz7byBcpy)?|qMrnceikVDMWE`*kb9g13PidqGVdI}Wv5-92|P&A7`Q6GV#z5+%41d93#6b%q48YoaSNT6u2 zK+&uMMY9PM%`Q+hhd|Ms0!4EP6wNJAG><^h5TUN9v3;d!`K0Ka^pnX&=l1n``gi1? zOC8$2ntf$OBh#Jz6+_Xyjt@oi*`a8DI}|NohoS}TP_&R8iWas*(IR#zTGS3ji`f*7 z5-3_+plAt!q9p~2mJ%phTA*kdfudyvik1^7T3(=N1%aX!1&US@C|X&dXcd8?RRxMx z6DV3;plA(&qBRAI))FWhEz}haZ(mtE0jYJ(_w+}EqJ#1`VUKBF&Azgt_1YKtF9NjP z7On62P_%&^iZ--E(MEPC+Sm?7o7kafQ#%xmwL{Tnb|@NWQ?$82(RhKPEd+`t2o!B8 zP&84XXe)uDNdiS%3lwc5P&8SfXj_4zDFQ`P1&X#4DB512XqrILbb+E70!2Fr6zwQb zw3AR*v`+iVsR>B!j{E`jx}oT~tZ3)<)$A)P+P!^||BghPqCFfRiuSZa(Oz~a+S?9A z``DpqUpo}-XNRKw?ND@p9f}ULDLP1?=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%Xy zfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMSQv`}m6(~AQpy+g=u4vcxmA4a+TBmY? zvs)X;XBr<3rJTb|^aE4n-H(q3A+86kTM8qKoZNbcr2` zF116^Wi~~Z3lv=;P;{k0(NzLPR|^zfBT#g$K+$yqMb`@y-5^kOqd?J30!23q6x||F zbgMwoZ30EN3l!ZUP;{q2(Om*XcMBBVBh(e0)xI)Y0#X~&HNiPM6phT^F?(j2=Mdkdxj-88Y_LUWND~kO0vDy?hJ3bWE>`>I*4n;leP&AVr zie|P$QHvdlTJ2EO(+)+wY>Ijd6wM+~)JLGGuRu{hfujBbMFRwi1_~4n5-1uhP&BJR z(QE=mvkMf>Ay71@K+#+RMRN-j%_C4WM4)J>K+!OPqTxbaQBzU*IRUAymcKErYf-2}o_J{C(FOgrXzzZ?D>|sAgYT(OyN7|AJ$iqP-m-iuSQX(Y|&l z+RqL}``e-D06P>NXosSM>`-*D9f}UIDLPc3=rDnz!v%_t5GXoQpy()pqN4?hju9w2 zR-ouOfuiFDicSzHI#HnLB!Qxn1&U4)C^}W3=rn<%(*=so5GXoRpy({2u4s><@@N85 z8Wa=SD&58=MJMH(pYuY|2Kg%>4;0nx zD=T`WDDq#6ZBz89<3rJ7b|`w>4n`>HdhoYW# zDC%X0qTY5Wn#B%9eQb*Q3KaDdDC#dzG(ezepg_?efug|zMY9SN%_dMZyFk$#0!4EQ z6wM`2G`B#}JOV{S1d4_V6b%z78ZJ;YLZE1*K+(KHT~TvG<=q6Nc6|Q?r`Axvr+-F% zk2YUJHT%kn7HTLeTZN*99UqDou|v_Kb|_lR4n?EvP_(!mik7fL(UNv3TFMSZOWPDJ zBT%%gK+$pnMav5mtsqdeqCn9~0!1qe6s;mqw5mYSY63;83lyy(P_(8%(OLpUqXmk_ z2o$X?P_&Lf(YgXf>j@OCFVqz+&`_Bp0ja%}--#_4ihj$Vg502?ntf$On=}+FZ5@g> zb$loqYlouE>`*k$4n>>Wp=i7ving#r(F8jbZE1(1i8e)B2^38dDB4<}Xd8i|$pS^& z3KUHdD4Hrzw4FfF_5wxI1d65$6wMGQ+CiXbM}eZ91d4VRDB4A!Xjg%v-2{qu7bx08 zs4Lp2p)w@_sr{0_j<#_qx-@^w+MW&7>?`-*69f~fqL(%1SD7wN9MOWIP=qfuDU2TV= zYix?H6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$Dsx=o0#ZA*NN_F;MVsVrHhQ?Bntf$Ok2e&( zw+}^6I6f3TX@{bx>`?Ty9g3c@L(#K#D0jFh@2o$|3Q1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJD`$kwDSM0!5z)6n!dC z^qD}>=R#f4qYafM6Oh_*`Rizpg`yKGX?)R8&AzgtZyJhm(?ij>jt@oO*`errI~4t3 zhoT?tQ1p`>ihj03(Jyu=`qd6azu6T1E>QG`K+&H9MSlqtm8x;KouaZpQ9FU6ia=3& zfucg7s6n8pDp1rxps1rjQ73_-MuDQv0!3W}ikbw9x(XC^6DVpH>WaQ zNBcSy-IjmEu~w~SUs=)2)#9QZLQ#w3Ls6?8ihA0isFxjzdfTCB7CRL6u|rW`I~4V^ zLs5U5q5%R$0|kl(2^0+$D4JEEXf}bO*#(N`5Ga~cplB|EqPYc%<`F0wB2Y9`plFyt z(QtvH5duXc1&ZbsD4I{8XnujB1%$ey9@Wa@2}o`4{3)WDs`Y#N6Z3nt1*_HUD=S*G zT70onC|b<%p=gvHiWav+(GqqjTG9?hOWC1lX*(1xV~3(;?NGFwP0{iKMJosttte2m zl0ebQ0!6C`6s;;yw3HkAZZ zAW*cSK+#4*UD3kTN^R$)XvKV6v`8rWGb`G-TFt()qRpzsyt{^?agGl~o7 znjuiMgFw-a0!2Fs6zwcfw2MH|t^!572^8%vP_&0Y(VhZDdkGZnEz}ilTCJ>~fYjc~ zUq>4oiaHEPW1ng@`^t(As202I9*Pchd?-4|4n+ssq394h6dh`ZqQmS^bhsUgj<7?~ zk#;CL%BJXOfudssijEa1I!>VIc!8o51d2`+C^|`?=wyMSQv`}m6(~AQpy+ggqB8`F z&J-v*OQ7g%fueH+ip~`%I!~bJe1W11gu0^rs+BVnklIQ4Q$+iRqVf52*B4f+*;iI{ zX|=d(&ro!k<3rKqb||{S4nbgdnVuCqhY^)^K}2o&8YP;`?( z(ai!yw+Iy7Do}KrK+)|2MRy1k-6>FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M z(Zd2oj|db!D%2HST&=vHfYkoTzrW~`Q1n&)e9>doYW9^CJyk7=eL~UGjt@o8*rDiI zI}|-N(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1%l~7moM71(k z0#ZAwdxG<1C^|KNEC1KkYW9^CeP1nB*)J6R;P_DVqaBKVvP03&b}0JA4n@D(q3Aa| z6#Z_8qCf0V^rubHUjjv?4so}gqOw3yJAtB#Kv8>vqC%jkL7=EAP}D)7sG~qpCxN0y zfuha=MO_4nngoiv3KVq{C~6icstFWz7bxl>)D?YOt!$To)YflJaJ~ygE%^)lGj*tD zUs+Ml4#hDCgrZ)K4@JH0P&A7jiu%~0sIMK0`q`nVza5GO*r8~k9f}6o6b%+AnpL1^ zHi4qq1&ZbnD4J8CXfA=Gxdn>m5hxlWP&8DaXqZ6JaDk!`0!1SQislt4nopo;eu1I| z1d0|EC|XFMXknqQsHH>Y#ss8x+~5SKwL|@${@nQ|i5BTl&Azgt#XA%)9TbX|aC|6Q z(hfyS*`a7@I}|NrhoWWeP_&#Kik7!S(F%4bTG6IxC4r)q1&US?C|XsZXf=VN)dh;y z5GYzxplB_DqR|3HV+4xU7ARUrplDrzqV)ud))y$+K%i(tfufBBiZ&J~+C-peQ=zVC zu@05r6Oh`sGbK2qLebWFjO|d(zOth69g04OhN3MTABrZ}p=e7x6iu{4(N=aSnq-Hf zt?f{>jU9?6+o5P%o1!TKMN6 ze}`)Jl@%S_p%{O7C_2RPq3BRM6dh)VqQmV_bc7v>j*rDiHo1)_c zijEg3Izgc5M1i7{1d2`;C^|);=v0BC(*%l67brSIpy*72qO$~w&K4*-N1*6jfui#S ziq01(xWU8RP&qgOsa?@G!8s@tb<4jJ>yi%D>?`-*I9g428L(#Q%D7wxLMc3P*=mt9!-DroRn{0}17AU$!py*bCqT2+DZWk!J zL!jtRfug$vitZLDx<{bsUV)`?Tw9g1GDL(!{tD0#r(&GqMscfihi*}(XVzW`pphSzuTec4?7h7X@{b}>`+wd z828&lQQ4-boj_4Vps2k-Q6W&&AW&2lDC!_k)KQ?QlR#0UKv8FbqAmhOO#($-1&X=} z6g3MJ)dY&V3l#MbD4I#2Xl8+;7NM@_hYpnu6Oh`g{S%xYL(#=qQESI)_LUXQ(y`d> zgizGS@u8@%9g6zdp{TzdiU!!BXrLX62HBx#upNqKwL{TtHbt`w6wM(}G^aq(TmnUN z3lz;GP&7oKXsAHZFoB}s0!1SPibe_)%_~qepFq+40!0f56fG!Fw2(m2!U9E$2ox7l&q<+ZX~&16W$aM2tR0G$ zvqRDHb|_lG4n-^4p=c#L6s>HBqE&2)Ruw2(O`vFXfuc18iq;e;T1%j4v_R1qfugkq ziq;V*T34WGJ%OV21&THhDB4h(Pjcg`=6|9g4QGL(ybA6m4sVqA7ML znrerl?QDv+7bu!0P&8ejXof)14gy6x3KZ=mP_(l^(Jlf-y9yNTCQ!7yK+zroMSBVq z?IlpOw?NT80!8}@6zwNaw7)>n0Rlw_3Ux(WbgayifYhGJcgrS(qF*wpgF05TudL{> zj>T%HhoZwBABv8!L(!3TC_2gxMMvAA=omW`9czc88uqirGpy(ulqLT%R zP7x?NRiNlJfuhp|ip~%yI#ZzNEP zpy)n!D0)($=qZ7sr-izrD?3(h zPC#m{`TMS~3Pl%XMbC7sW?xy+3muDB&JIN{IzAM=WQU@c?NIcJ9g1GHL(yw?D0(M ztY%+X(XSnge&>av-y9!`ez!x>A9g7E(+)*{*`cV^Dek$4qOu)|+S#F~VuzykHbsR% zQG-BHRiLPYKv745qD}%ujRHlT1&X=|6g3GHbrmS;CQ#HYP*f8r>Ml^!L!f9TfuflO zidqDUS_O)F3KaDc>WY5uSXnj!sa>2u(fCU!>YaZLP47?~<)c!wyAr+7!(tP&Btd(L4f0Lj;P33KR_!C>kzM zG(wRb_{YUaxvQstt%8HilR9tpZC|b_(p=fzK6s=%~q805>w2~c)R<=XY zDt0JZ)ec3g*`a84o1!%Yiq;e;T1%j4v_R1qfugkqiq;V*T34WGJ%OV21&THhDB4h< zXd{85jRlG}5h&VJplGZ>(Pjcg;{=K}7bqGpP_%_mSG07e%F_u*ZG-$yY?)BBLH^E= z37x9hS5`EsQ}N9up=fKzhoWulP&C;NMcdk;Xo?+*rrM!sJ3AC@Z-=63b|{)|Q#3=M zXa|9!9R-SZ5-8ePplBC?qFn`wb`vPtU7%5-2)Ypy&{xu4rPX%FLH0MR(7V;A|C&F3vv#a%iV&_LUVK*{N9Y@=$b? z<3rKWb|^Z=4n@b>q3Ad}6diAeq7&>;bfO)KPO?MM$u>o&2o#+vP;{C=(dhz3X9yIX zDNuBlK+)L(Mdt_FXmq5|o0!8--6x}OObe}-c{Q^Y~2oyaiQ1p;M z(Zd2oj|db!Dp2&8K+)p@MNbG6JtK+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mtmjXp!2^4)TQ1p#J z(YFFc-w70bFHrP@K+%r^ML!7?{VdcKz1XSpaRO3%G5^@dOQC3FHH}|7RkN?G=#NfC z$Lm7TpNrGWP&C*MMYGzWXf`_( z&2ERHIqXn0ryYvsvP03_b|{+1rf7&j(NKY+VFE?N1&T%p6pa)pnpdD`K7pe71&S6B zC|XdUXd!{3g$0Th5hz+zplC6HqEP}xiwhJjAyBlWK+#eHMN12HMg1EqGZK*6yZsZK z0gd&0`YU8o%QRNAudHZ=#^QvVLeYwj4@E24p=f106s=;1qE+osw3;1?R<}dZ8g?jJ z(+)*z*%XZyC>kSBw6;LeIs!%O3KXp;P_({4(FOuV8wwO{Bv7=mK+z@wMVkr~jTI=` zOrU6-K+)y`MdJmEwh$Smq5|p0!8}>6zwZew4XrH{sKh@2oxPCP;`($(ZK>mhX@oM zDo}KoK+)ksUD4K!mC~(AQLp@c*V}}m_tMjfBO0sOS5|aPV=>_NP;{*0L(y?|C_3H_ zMJL#y=tMgdon(iilkHG+iXDnhwL{TqHbtik6rCYZbf!SjSpr383lyCrP;{<9(Rl(z z=L-~FAW(FnK+#14MHdScT_R9)sX)JePu;AHWm}_3`I9NJ`~+-hoW2TP;{#uif*$*(d~99y2B1d zciN%oE;|(6ZBulQK+(MdMfV95-7iq|fI!iM0!0rA6g@0Z^oT&wqXI>b2^2jpQ1paA z(USs2PYDz~El~7~K+&@TMb8NoJugu7fs~I~2X{_)zqQ9g5zxL(yAyD0M2mvOQ5K?K+!A$MSTQ{`U({F6DaC0)D`{NSZTd4 zDH@VLU-VZf8l6cE=v>XdvZ7f#7YjcSie__sD4N|4MRVApXihs6&1Hw8x$RIij~$AJ z*r8~s9g2q86b%P$El{+KK+&=SMav0wMT0t5HcdckJLcbaJ-BoIp8n?fOS8*& zu4Z3Z(aN2Ry&eiht2jOst!js&)$CBTx*dwvutU+Bb|_lQ4n?EwP&CF4MQhs>ts_vh zu0YXx0!8Z!6m1|-w4p%JMgm0}3lwc4P_(H)(O7|^%>;_Z2^4KEP&8hkXbXX&2?9l1 z3KUHgDB4P(Xp%tD)N_GK+&E8MSBSp z?JZEWk3iAB0!8}?6zwlibbvt7fdWMb2^1YHP;`hu(V+rGhY1uNE>LuYK+%x`MMnvB zMca0+e42pNcF*5;JtY)vlRtTMbmwaJl@%S|xoCVm6rJGsP;{alicYda(aClwI>in} zr`nZXZik{X>`-*3P0?8bMP~~Xog+|mu0YXw0!8Nw6kQ-tbfG}eMFK?^3lv=< zP;{w4(PaWfmkShKAy9OsK+#nKMOO?6g?wQ^sGS9 za{@)r3lzN|Q1qfe(MtkFFAEgCBGeV#)VZ=_0#fUre@)2Eq3GgHX}sFGntf$OZ+0$D zdO8%n<@iwawjGMzu|v_jb|`w!4n^Mc)b(eJ4=#y+F|q0!2Rx6#XPn^s_+GF9Jos3Kab&Q1rV% z(H{aue+qR)uXnE8o`BSv@@F022t_A#Pvfu7)$A)Ps&pydcs3NZ@AA+0^b0!_HQ1r3 zYKNi@b|~s-hoVk)C~CArQD-|8b+IXG5-92_P}EJJs9B(>CQ#H}ps0sH(M$qGGYb^8 z2o$vn6!jD+>LpOrTcBtbfucSFMSTT|`Uw>E7bqGaP&81WXpm4>RPIt~_gqr6Y5rF0 zc3tZC(KhOl#^5g1>?ZHJ`*ks4n;%lP&CXAMZ@h- zG{O!=BW;T26)2idplE)9q6Gws78EF2NT6t8fucnOiWU_pT1=p5lt9tq0!2#*6fG%G zw3I;6(gH=x2oxSfFSVfucQb{XWF6Y zEISmPZHJLhmC^}D|=zM{q3j~TT6ezk#py*<6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9C{Xm0K+($r zMXv}Hy(&=jnn2O(LS50VT`HR;Ahow!5}eyY(U-VR0YIzAM= zXNRKq?NIcA9g04*L(xZeDEinAMW5KA=ul6^ZAt&zVR(ypnRePu-rO~pg+hN7zDLs17i6m_&iQ71bTHQJ%5 zvmJ`M*rBM&4nCQ#H}ps0sH(M$qGGYb^82o$vn6!jD+>LpOrTcBtb zfucSFMSTT|`Uw>E7bqGaP&81WXplhBV1c4p1&U@9>WbPoRX$HZYNzCHOe>n|_w>i* zUllrgQ#Jd_iso)Ax_l6d=5c%|8e)f{p>`-5W{0BTb|@NQhoX^oD4N#}Mf2IAXnvcb z1q6x~6ewCqplD%%qD2IX78NL3OrU6#K+)m?MN0@2Eh$j6lt9ta0!7OR6fG-Iw46ZE z@&ZLG2o$X-P_&Xj(aHivs|a;Pb2e2*CLpy}^Ow%%3PnrjFNdt!RL#D!qBWa}F&~AZ zwHzOcM%$rij2(*BwnNc6b|_lc4n^zPp=fSfFSVfucijEX0I!d7EXn~?*1d5IoC^}A{=y-vm6NI{==}nb86Oh_0`JLE| zP;_|P9k!-w_LUW#+El#tStvTq@uBE+I~1K^hoUp>P;{0Ziq5t}(K&V~I@bm? ze4C;R1d1*cD7r|X=wgAQO9YB86)3t)py+aeqALW7t`sP`N}%X!fud^!imnwXx=x_z zdV!)F1d47HD7s0Y=w^YUTLg-373zvkZmP8ZJSiHUKkIl(C|ajo8n-o7v#+e^uBKwv zFGJDYjt@om*rDiNI~3h#hobxKQ1pNuiXOB>(L;79de{y{kJuDFDp2&8K+)p@MNbG6 zJt?f>rnK8<3rJhb}0JD4n-f^ zq39Dk6n$!kqR;G5^tm01zOX~lmo`OT2^4)TQ1p#J(YFFc-w70bFHrP@K+%r^ML!7? z{VY)Qi$Kw@0!6mEVtf*tx;+k(mQ76ZTqDDIub+$uM7dsR+*`cVb9g4cyp{Uso zMKwDVb+;+%Ay71vK+((sMJ)nFtpY_o1&VqJ6!jJ;nnj?fk3dmhfueo_Mg0Ye1_%@l z6et=bP&8PeXjXxu*#wGa7bu!TplD8^uBh6z@?ru~yFY)Tu|wDTJ^iEdcg)V!wVHip zMMJw5KYbsHhB-bI4Yxzl2s;#wv_sLnb|{+94n_0Zp=bd+6fJ0nqJ?aV78WR4M4)I< zfuh9(ibe?(EiO>Bgh0`f0!2#+6fG@Kw2VN}vI0fR2^1|aP_%+T(TV~^D+v^>EKszH zK+&oKMXL!EtuE9R&C|6q%MVG>;H+p!C^{>DbiGE`YW9^CjpkeFw7Edhc!8oV1d1jI z6m2O`G*O^vD}ka(0!3R36m26=G+Cf%TY;h}0!32=inbFd+Fqb&nn2NXp{{7Hu9eLb zklMNV8`DOIqCxp?|BSBH>?N6DZnWpy&XBq5}nr4iYFjSfJ<-fuchNiVhPfI$WUW2!Wy_1&WRm zC^}l8=oo>bV+D$i6DT@fpy&jFq7wy*P7)|OS*R=8v1{ex1f+IgekZn5D7rH%I;Cqh z`^t*W=vqATTPQly@uBD}I~1L5hoW=rP;{;xiq5k`(fM{Ly1))a7uuodBAcR%1&S^a zD7sXj=rVz#%LR(A5GcA*py(=rqN@dpt`R7@R-ouQfuidLif#}nx>2C$CV`@x1&VGF zD7sak=r)0(+Xag55bBCf>st9T0jZ5lvp78zmGif(-PyI8ePu=Wb}hR88H(<6d?>o# z4n+^xq3A(76g^~zqKEBJ^oSjb9<@W!V|FNd+@|OWfubh`ik=cEdRn098G)i_1&W>% zD0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+XHT%knKI&SmQ_3eWyi|Pb_)zqT9g04+L(yk;DEizE zMPJyV=u0~kePxHDukBFujZM+F0!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqUzX=rm zE>QG`K+&H9MSlqtmAb{TZXk9(E|2$qq#` z+Z4436txNz^%N-TB~a8`plB9>qCNseeFcj82^94gC>kJ8G*F;ukU-I3fudOjie?ii znq8o14uPUM1&ZbpD4JWKXda=is8hGf-3dtThWw#WW4HP}{j2hqW`}gEW?xy+h;GF@ z?L*N>$A_YM?NBtI9g60+L(u|uC|b}CMGM)XXkj}PEnsDzflA;;;>uAG6(b)Xe*wNjp*;iJyZnt9gYA9OI@u6saI}~kThoTMb zP_&U9iZ-@G(I$2%+SCq3W9?A1nN86+fuhX?ipC2RZ6Q!JL7-?$fue~5MOz6JO%f>D zTA*kffuhL*McWD#O%W)XDp0hYK+*OBMbiX|rVA9!5GdL~plC;-u4wIUl~ogv+B5m< zXzPTcKKX9{PTi{6S5~xJw_@9lp=fu``V#sKRXod zZ-=4-Y>EyPC^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VI zc!8o51d2`+C^|`?=wyMSQv`}m6(~AQs4Lo~TjkgUq*fb{;OrWT9?FVN?^eyevZAxQ z71uR}qH`P{iq5q|(Rp?#I^PaO7uccbLOT>)WQU@Q?ND@y9f~fsDY{Ic=yHLgD+G$J z6ezk%py+CWqH6?-t`#V{PN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCc=yrjkI|PdE z6ezk&py+O)uIS8em6sEc+GhF7_-BQpL-P-W+|#X^ePu-tbSr-85{e#ld?fo% zB}F~*r-<$kMW^Sl#(vnXntf$OpLQ#j=oX4Tb9^ZJ+zv%w*rDi4I~09ohoZ0TQ1p!* zioUf&(RX$z`rfAK2Z5p=1&V$WDEe8T=of*aUj>SO6Day!py&^QqCW+S{t_rEHOJj{ zipl~-?F5P{0!8fwiVA_E27#igKv4&QqK*PZorJogkGoa2NI+_*OiWag%(ZY5pTEq@Ti`t=RF*_8EvP040HbqMa6fG%Gw3I;6(gH=x2oxG6s;*xw3a~8Xn~?J0!3>Jbwwka zD_oixhudHZ;=AyYJ6m97EP_&U9iZ-@G(I$2%+SCq3W9?A1 znH`G8*`a82I~0w#DcVAyXo5h|mI6f+1&X#3D4HZtw6#FdHUdSH1&X#6D4HTrG*zHz zJAtC@1&XE#6ipW>njuiMgFw-a0!2Fs6zwcfw2M$zv|e*%fdr)XaQ^6e{ZRDdfHZb( zu4Z3Z(Vor4dObtYUXBk%d)uLCA3GH7Ylou!>`=779f}UHL(zeDC_2avMF-my9U@S4 zs6f$S0!4=l6dfT@bfiGhQ36Fr3ltqAP;{(7(QyJr#|splAW(FoK+#D8MJEdsogz?l zszA|c0!60_6rCYZbf!>Ow0m=9_XMQ&TmJn;dxWB|^Ej)yntf$O=QS5+^bSSmJ3bU$ zV27d$?ND@)9f~ftL(wI6D7w@RMVHy3=yE$0U13vnr9jbD0!3E~6kQ`wbge+qbpl1# z3l!ZTP;{d}(Mr59w?okrb|`w% z4n=na9Q zHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFwdda$|Dp>I-jOz#Bep-{AI z{;9@KnycAYR`f-4F=zi!^rhoN(N}gT`q~af-`Jt(TRRkeXNRKi?NIcC9g2RmL(xw* zML!D^{UT8Gt3c6j0!65Gbk& z6m<|N>L^guNua1vps2GzQ5T`E=(Fa^>Iq2g{pJMc^HB6^{&GlDt(tvhMYUQnbzms! z?)XsD!wy9=*`a7=I~29pp{UgkMLq3M)XNSkl$ z6?Lmsj!!^phvd6u&9(TNe!^4CTdQVYS5jqCfMm#5%WD&Av)Am)aGBI$kqRxzsW$ebilQ8Jm6`ZTpse z(pO13w49gT5q55QAbn8Pt>vS1bJn9}?({n$TU)kIC}(N8DSZQF|CT?}M_GegmPvo1 zW{#Fa29!$kv^{C^+PI}k=+%e=dmN)NZ} zvU{oYc*|XTmP${z6#JA)&$q0yU#awR%P|L(O0T!PbWo}Ec1xc_OQrW)#vfiPecW=% zk)_h-Engj7Dt+BD|8b?#_bt1fP%8c0a?eSn((kR+Q`7ZdZe8v4^a?1q9(QJX4U}77 zIXk@y%B}s*ORs}+>x2u^E1}$a*+uEKP;UL^lJsgQw=Q^jdOeg|^Ix+cTyD*Oj(m=C zYyNxE^ORfj9|Rs=Zq0wub-r?I{*#;wm0R=QR9vjwn*S)?lI7O?SIw3!x8^@fwPLw7 z|6QR~%dPnj!>n0u&41Zr?Q(1W(+umETl4SM-?-eGe>wVQ<<|V$t+yz*=3h^|Rk=0) ze%Z<8*8B@Xw=1{i-|#r2+?szy-_GUM{5#fmFSkDQZhHNcTk~%@+P~bIe@)H7<<|Ur zMh-8x=3f+Xbh$PEr2p~d*8HQ|Czo6E&)S||Zp}X|d3L!q|Fqlr<<|V;N*9+~^Us@H zUT)1lFmQFbHGjwV_2t(5ExR|DTl4o^-d=9a-!yl3xix>+)BWYv{B0`_ms|7q9Xwuc z&0jcvy4;$-^7nkXHGk>m<#KEO-23b0*8IuSx67^hvtRF*Tl1$cJ}$TB`=6heTk{== zugk6ZBf#&=t@&N}&*j#98~l5@)M>l)hEkkgf0OI^QhM8In6J5iwN&agdQf`B&fC~M zJ)Zx~m)_9Ir!P5gxzu~Hwx=w)V0ucY`V&jNk4PlT(hJ$f74Ovm;=+^J^k;qc~fc& zw6#*7NqH<70SF_!I>#-cG+$z!n?Yc-@XD#kqd z2{d@{;vu=$k~9^3~EXv|Q>}Ub9_?4NHCBPi?i- z7OA(Q^YUBWI=WwZt)lZ0&(Af!UwL#x^Y?EabiiKy%3~UuKltVFS9UM;|2Q49VLGP& z=joA&>5;zq3oQARH~ZTu=Xav{luxL)hUUZ1KKPzJ(@8fp|MmMP@9mOKyXbuB^h399 zJLxBnJ@3<9Oa13a2hGT*xO|-AHT9#*!%Ka4O)uX*>1pq|s9(MGUb*d}ZhYbL3$>lx zlqJgD(#aK_Km6eRRZ4wNjw4!!wY|U%%_m;}+Y{-G(@S@8yW0o1y>##HefF;@rI+s3 z`<^;z=ThIB(?R)V8CE~2=sfYmj$4=d-XD1dr**&^XTG*usqfR#H}&k(zMHaGsqgEN zcl7MHetOrXyO#QX9Q_E-zSrocwMu=zk9>h=Km3^!Uf!kDw^XTLnA<)3Wv}eluhh45 z;%@bj(8aW7?&g<-Yf(mR}9qI-OIGKkDK7>-CclFFZay zmR_$rEq{Mg+m-s+!rF%8Y{T=CgWyR{wk z!yCV!wpXd|f$5-piC=Qi_WLZfbK5}=-Fx-78Bjy>VF#Uh&8}?+J$%^{Kc#azHqNQj zh_)BA==^lk980#nlm{QO?zpyNj(P2Y+ww6*=YHodxk;)2iRqBj()skgHa(KBzuD@? zW^^6Wn_Etc)Kl9v*()DgkK8(4ed*R*aK7#K{dP_1!Q|?)G|XXg=wemo86laOo9u_Vl*-y83`AS&4enh@r`gf?G@w9qsXg>L_ zQ?IFO8a3vk`uPs|@cDGLq_?c&zJ1__gn8L?%nj*eE^@}BE*Uwf?e%%?LHmEXdphTa z=5tRu&yMqHN{6M}xuWyl*RDNR+xfhCl zzoAlT76IEKmTuNmyX$@l-}K^{|#@Z zr@WuuW90u0MS9A)>5=@u;ivSJ7tg89T}{DwQfTmnuz*G%nh>aN|nd)5kpVl=N~I^OtgIXkV^0E#BCeo?L&na*EYC(owUd zi`b#7(#Z`=hji(h&OD!TQ}=RX z2bZL=u}fp;#)Zmvlk%Ik&bwl3uo+^Zo5Sm*}}z`T>((L(5C_bU|kCxl;G$a;;&>){~a*na{U( z@wWrowcNCHy3S|$`-w#B^Y@mo&c282TTZX95pCC4zeD#em)f-+vvhjz+&?`beSk3{ zo%jIHlXML&<%=_=sqK=a7bns9=YLD5SuU-a9~_!qr{&TH`N7d`kFJ>?9H0KTFMU^D z^Q`<>+XqFZ4gUEwtVP;RYpwiXbb3crF0GRv&JVs$@2twDwey1>>3v80(v1E0Ix9cs3`YO$3`XZOxVG)Q*3J*|<<93d`mFzW z9=YtD{+CN*@`Dr8|4M24vS;N-oc5T%o%Wc&U-&Wq;RM%DXV zk8b|<@8EQ06hu^_m}yZo3*b%$Fy>IOWoY`9Z!`@-w@3Qg%}L+OA*3baed7 zFUjBk{e6$?manmA(;@B3zcqC!mD9iUyy<^==+I%)#tqwY`gX&nPa8jM+SuviCyd>0 z+SC~n#?P3r#jx?ycG+&m)Evf7*kXri6Q=*|Y5Donb1yt>yJ?fQoit<8juT45wwk)_ zgkj?*PuO|b(8*KBkDEMf`c~tnO&B(9!juWq$4wtLVdU89Gj`Zw($rxyrcRwaeyeel zrc56;as2qPe)0}mOc=K9xba&}n)3hq#hAX!^uJ#d6So?+)U+*jm^5YTGE=8b81j$n zV&@st+OCrNHL~WksavP(eEP64+l`yH&GI`;8M}6RSthPId57s^M=!O&YV&(Fr5E=9 z;i>7NS zi>Gt^Z?CZYdMMJ>vQj=c{fjHw6*a1D=SwrszjA5*-KoX3{l9S{-P19{1{CRxzw}T)Y}7w4$UpDJivjWaDmM)JZ&l4atbRfMt5d4Kh(*JIxc&wf{r}@B_s_44 zl-s;!TiI)7{jXk*f4=np{<8e5r&4S9fBVw7T>0%czjPk1`Y&JG=}mCXbf6RZ=ZF0h z^;yzW8F1AP{3q)F?z(Q9{r~NjVsQPkrPIi7djmFzi|U+)6@Al1@6f;K*ih-R*u-My zv^u79Y-xMAO6=k3)*@~j5}*I##v#3udp49;DO&oqokDti)c>W&i<$G=Ys;{?+D>@p zhM9{w2NyF}cFvc2Sh|SqR<6Zk={D*g7d}6w{=)Pu7hUpo)>?GW54yJ9fMuU;b78bg4E#C;X-LCb{kIY`=o5A|+TF?AgJVV^Bxu(*Y%-Jwg{frt${9it&VsNEX zdTG$PrW5F1%$z}{7#aqqhn@QuT{8HhS3~z~j~r(vki02_zZmEb=2g zieB@yJ<`4Cm7g>qpLjez>L2GbTROjP{fp*?O4r5mo9KXk>G5I3Jn8Vhebb|Hjplc} z$@4rRp>5`)M&@IN_bcWZRP>!C?E!6X=KuEaUpYLT+rXl4pT8abuN+l0r<;_O+79Y6 zd}95I`^U8qSLgro>g$tU`d*6ug?5h{MU}^oz84PG3UUdSMR?a`#%ORL z|2XY`d#V11x}0{KtPO@uYERtSfvnImnX0d*ar5m>YaLqZ-0Y#s3(VVZi*0zt{ z{u4y$iTOrxWZT1XF(f}6+ICF4bd~-e<@yJZl^ur`ee$W+Z=TaFZ$qW?(1~qt1HIa9 z-@TY~c+vasZ-)Pxn^Ec7POtjj`PJve{r3<5H46V@KtuB@J$-zf%?>Eq)`()xy1}+J zyqL4^Kb|(nyv3Yt#zv)AVD}-Z=STh}srlxi%djHdDx@>opzRu)V_?xcpY}grN&oI` zqdb3l%dC8|XTDA8KCEvs&)}l(Tq)&SmYIsabN}zZv3E-+yT@Yb{>=rIp=}>ce6dG* zRp#5=!2^qyzUdY?F4%wmPN3V!bkQp>mEzU^FTF55Mz)(TeM({ZF>8)pZuID}E3Lln zQmd}C?AWD7udvQ)%dNh4$rDyvZp@gaR# zLX}t4RoCWM7gUwF-ij+~%L{|v`t}ulqf*=8@ut0}1{57$%w#DKX4Nkf)Y4Xw*J=?Y7# z!-=sj!%@1C1)Hs|w4{7UVyz7?DK4qYs|@C{prX9IsKD70s94-9aLid*C?%?E3kpoz z#LzfAw6>_WsIJ)7RN|$|ysDC#k%{OmFUu<*sZG}~ieR%HY! zVl&N(>VmrJnhIN|MW&;+VYqG@jU;J*N-VJK$tw+}Tvt(9RGxSZmGi4g1`etzw>4T< zT~t%!c5WtJTu?eBnBAVe!ab*VFvVcvIiT<$;5Lvc?2ZT4*-tO#+UiS;t)!%?IIpg# zpr9@{zeKxvL8DzUIMx)Fb-0#o-$*(vXkaI^tz@@zyY-PYc-08orRyq&6;&0NRt(>DqE+Ps6UR~WDz7Zj zLrJ9_%(RIs?QoKOfDIO@+Du3sHG3phSboyVaT};%(!m-oOnTWigsqagq7el}MTJST ztYxwzY)zgWA%+xQqXW32rP96v&5>)?UC5Q zZC4NXMce--%$Yj%q{O&`-Jz(Wr15UUl7;qSB(^*z8tTQDcw7gQi<%+n6QA;YtbTpik0Ng5!?c zIPM4+oZd8-jl5x}ugfbasIAH?&><`_KZEQ%H$2Z4w5Fu2$hJ~2j(&-)T#z)uO4~-& zRR!izUO`RCu<)GIC+SqjPHAWBf#t!OI#8jf_2N468Xeq|j|>e*tlXl+mUEqn*-YqP zZu@wxPIoq&4L#UI^Q-dg950336m9Dy??Se!INX+2RBI>hmzbb!hHwq$(@_*`@L7{5 zPOG1gZBG|wCMM^6t|+$AnIsK|=!Qc;K|w{`AUiZA24LNkRTPGEZ)g3)iv>lcrM0Db zRVMksl4|qWovK(6tYV)J=P}0y4;Hb}LA$m(KR8|2RS&Xjldw-aoN-`Fnq*m#9jbKE z!j#B~}%c7n-f^;;P}2sz=X6pNY*~5L^n$ zAX}%?Cf3*0Pn$4#?6f+!XC($GDJ?A;m{+PD(9ZdVb_8fR=>_&D&QD3(JhxvX|0T{K z8&lFHS0M{&n|c>RO5DM4m%~uQ&%`BJc~Cz<@ZVIUq`JnJ1*5$ z1t+KA$XIMEq%*Jc;=@1N}+ z26oTQc8>#d`t|6Q-DPI|l=`u=>JP~7Hg)`rIfsv*K67^cylzu__B1ei(wwQ|tR6dM z`q{;UBc4(O3fc1Ioj1zlzn>C}`gxo$x#?Bl+>2Q0vcw)b9Q@c;K$CC$5m^I^| zV`pS{o0#3LqDOW&duny~c$F^vw;jY)sDPzgCQf5z{ zKCRmn>1`>ql9CsNXY|*0fids7|1p+s|;7**l?3yhvzofKe zRKrDcjvbA)CWq9YR5EQs{k&ilJsTZk8x9C=KT5dRptPNY>`+l-*PrfWp6G$i8Z?v| zwzlnT1$JqWpJ%Nn9c$fe+l7BP`+XaB0XyY~tZ^&FwISRULy0vK!fT6gxdR&~mrkEP zBR3M19{({fjn3PRE{Dr(O!*Zfk~Qzs?>~kwD7BM>op#+}%T3g-L!F?B!((nvk4DLM z8|y2#Z{m1u8z(W+hBfFe@#?f1!y)X%8g$sE4}l%tl8$PD0}V~NU9Qk|fNXqr>1AW8 zuX9gP>u1gk$7wCQ|1vY-(Y>z|GajNX4Al!M@hWkX&oB2IB}Dy4Cjhx#9BDov|9O z+pLkReb}|)gVkXjLatREAiM4kI>N?gfN~Ojg0&OIQ-CdN(#lF2 zz+I2p;Vtkcm|jD(G11=bqp^f7J*FBS?u*JQlbUY@?uJ70$;Higa_e)@aJz|7FvO0u z;Sx34uh>7_6;5I^0F#^6|CdHwaY=DS;}&LvRE2p3!2|Ldd!U{ef8rqhpF5B>xNW5! z@AjWW@8MF{mgfz#-NQAY6R#w#)Vx}2p4&xSa&z2Wc(Lk2p$1yhCcFwtybxIIu5>HP z-SHzhnK#_7`ERe<-sScuYwOvp>d@tmm*KWdnAW%z=X^};3(Qn?Wl5b{<8G9+9`h1= zs+}~j)LlSHSi3e>SFSZ35=)Y_HY%$s29;QQ(l$%ET~pir2__ln;%3AtQ(_mlqfCst zI(yeg!`+fxyE?ZC1PziztAr7_17EUkaHJ{DE3{iXyR?}DA>334n)ivzoQBqvYt;oS z)fyr!nyrPzTyuGyyaNRN7X+({d2sW#%ZWd)+TCVL+@Z1kDKXMS`z|j(xZ##~A!$Wc z71jLL>+s-UNkiPtN!W%9m!Z)-Su50xq4+cz9i{-3+spsu63vb}NiEX$KQ^x^|xCwqZ=x^sjcu$_77O zFaPy&m$_7e&%0d7Fjvgo~SKtxJGf>bJ>%8xtqB0(}Np7u6@YzGBS6W5;-n79=cg{ z%`1~B3-`Wn^e!Cn$8ZJBwi~fg8Pq%?b7KN>18i3XS+C^TwmMOBE z8+NNz*LXJZTz8*3n4$3Qds*Iyx`Of=onVr0J_ob*pQp>Psm5|9Zqfy#Y`BY^YxmTW z=ceICkXzVrCkPG^j409EcVkSf#$?|TEo80R;0ALrS&rnvB*Pg=bh>6?fZVN9CKjAx zZQGl-1-2>w`?HMj)^Nia=|2uLxvm`%jN9F2W!%ZLTwGFW7ir0Na+CJ!>H$VTh0wtPr=#qe-0+TWFdBCQHRuR0!$~QiNCHC#)-7%aK8%1zv zNUV>7(!8?Dq_cmxn%$E>H{OOvU}2*o7)h_hVUt}W*WDrwXRVP%d6jm(Kf+q#jU-Q+ zy>LB*I}gjlKHvnlht0d*2Mw;Zit~~$WEg^8-JB$~PwY&pwHuyp+{HQc zrrlOuTW!z9)Q0|#+oA4G=q?XJlJCdlG`b(t(7Lo|@OrG~X3sTv674Xi@9qx;=fwZk z{&ns+`Dn+vu@vh-lWRB75^I%p5#C!(dP_k=<0CiuQZ{HM4!6g|?m>Blp8PUP;Vpjm zm~hwgiaTGr2kRWJcreS5`K5W~Lu>~wvfFOETxYpO*|qnE4O3cS4+8CQVz+Gb%9C#I zxvkUq{!7@_2`~K{osk0p8t&zWPcN9UhO4|rEgLs_+YxGQv6weEny_UObaBuP?~c~h z(TrxqNyqR(RYPoJg}Y*jZTJz1tus8&TIw81cNx;%EOO`LaQ!sgV0E`D6TR}7Cuj=} zta2^zT~=?SR;cqS*biJQiIFgC1$hOwri<%>>xqb)Ja3C|4JY01D404SJP?Ilr5;w(%)z6%K?Bwxd-HqkyISuW(P_CqlA=i2f$LVfQx|JIqP?*2q zNKySiJyz9vW+4(6YGGR_*!J!&CL;^ZNacAA?}>0*de>D}S(kW->DE5ynuc+N+j4kC z)exO06W0^D;XPS;wZjsRS{gUbitUyq?Hcz^j>y1*fN`k(mClvSMD=cg-yFG&RCLuM*K|w zthBSeb5fVa&P`bsjpX&W9>=e^8B+;XC;}5dM zB8@*28QW!UV-fqVhNQn(#J+4H=`R+sPh2Mb#Ul0{5J`WrNb8^vx7OVD%d+)xMAGYS zS%&VC>vqXgcgd&hlF!*CU$#rWdY63HE_ux^`Ndr_AB+kb0G($?I@@6+cy95(I(Gb* zr@F~!+1#YFY)<2ch4#R>q0b!m=rHMNNlqkubkM-`p1lT;o6~3n_E0AIwH}dIZ8ph-y)u!9gKC|ZP z>8{%A%aq-B7i8=ciQMI?4WDYegsW{_wf@`}4`gK9u|#~BxcdeHw|vLCYU6!Ib*=4t zZuq@yS8{xSs~zn7VO+KGtyF$Y)dq{C*iP?`Whu5hxIM-avZ`>GzKYG1|>yxv#!aMc3U64eUT zTGi32V^t@rPF0s*kHat@^y`tEz9QeyIAn z>K4^)sykHeWEiZ6G}~W-^{CoPbx+lfst2g%sPRJB@llU`)fZJas=DKbo8Bj?U#b3}>b~v8z5bVKiaUN- zPFHQN+E%r_>b|P(9PIkPe~#RnJmgrh19$O4S=w zZ&STj^%2#lRG(9QMRk+v2dbZ`eybXMj^38PXcwsuNYGsm@V#-?QW9W3lQ|)#a*}t6r;mv+A9y52!w_>b_FPjqe53 z*Hzz9{aE!&)$dh*R{c{oYUd3%p15i=)i$bot9DlHrrJmKNYz2ALsdtqj#r(cI!ASZ z>RGB6s$QXbz3T0%52!w&`kd-(s_&|Ps=7t>XVsmmo}IAV@-|g%tD3EPfNBrbLsi}R z(+yXq>dvDs*QriYJwf$k)y1mksa~Rbjp{9`_ozOq>dwb*{4c3)QvFEvE7hM=cc@0~ z{OyLzP;I5!Q+1$Sm%7)hRVUjevCDH*&$V;8%a^I%X_v$r~(G6y~p0v-b;g zH`Qb90>ceIOZAQe!~Ce~_O4<6SGAvAh`9cXR2Sri`CQd?J;S_FHN!4gT>ouVEBl4{ zXw^#(3G)rAA08IwZ&f=U8RmmkC*_5Cj_O?nVSZfom!dF7i^F=zps?E8xPtjuI5@25 zt3Fp6<~LQFRD^jC)vBRku2a3dI?Okzery+9Zu!1b?K~pPxvIyF3iDjmdyWe86RN)* z6XsZ5SPvT;))Ljz$A|d>)eZGweoM9Kq%iNPT60{O$EsdACCs;|Zk`tAA5`}{Ar<*b=7!mu7uF+A4(kxrCG*3)T=hl!9w)bc-cfD7D9n4S4qF`N z@v1A&2=i*y&&~?-PpVy(hPk)uwDZDzis}Q)!u+)ApLT)krtdEg>wpzuEmJ-7k}$7O zefhF5zo(jYWtjI-9kDXZ^{Urg6Xx4hzgQLKZK?;}5azzBGj0m=sj3g%66R-Bcdia| z`fXv&zay*_s%PI7=1Wvxy(i2csJ6O4%pFumJs9SRs;eFj^PQ?+*@eDaKR>H>T@&X1 zsxzMq^J%J&tPS&e)qkD|bLO*QEnFYgp{h%t5A$WJufGuHk5t>d9Oh1{N4*;6$*R}C z9_G7Mzj-6fzp8eBE6j(g&VDD%i&P(bFU-%YMm`MlZmPu}hq+qyyvi4N({zJ8gHPGDaN2<=V z?;>^i4Am#?OG#aRNj24O47l7vb#U`A4_Cb~E6i7`zHMJz>iYj&b+5KzK0tMxH3Z%3 z(^YS^?=*G!LDe7a%S~PWOSPBXkZ?Iq_2iCWK1+42-KcP{zoMG9f0$dUmL3r1k*fFE z_X@lIpHh8E^=((ZNaRc9t*$n;FT_>-Lp-%x$m6QJxoYFvU3o9n4&q&vb5wha4^S>t zEfKF#9-(@)_;IRpRhOtPSG`8{cGX8z*Q>sv`jM-)T%W3bCH}Lkw)}qgupX*fs9L5v zR`pWVYgO-4{X%sQ`x;F*z8uv-s&%S!RhOyWtonrNCe@Erx2f)HUu@~d+h28>>J6&z zs%F{^1=n9I)%{fuRh_DOqUuuBCsdzP{ZqB8eV3ve-;t`bRBu)NK((2Dfuid#&sFoH zNVQzGN_Dhqo$4gjDXMc+Pf|Ty^-R?ZR9C33R9&UITJ=uVhg2U^&4}1>#OBjf2x@E9 zJyf$*JF6a~YL|&Y|NT{i`&KrdValUa?Q$pRuU>VE>I_x8ya--jpn8VtIjXBw?^Jz2 z^%2#lRP8hsjOP{AjjA80exmx7>K4^)s&*I-hHnuKYirfLRPC@6yl#h&pxSN{)V`{R zs^+V@FX46T^(fUbs*_ZwsJibxcKt0?y-4*^)oWC*SG`U3F4c!rA5(o>^?lXPRKHUF zL3NvIaKFi>zf(Du63&mW+Dx^jYMNV5P3#*ewZ5zb^KZ@Qpnj_U?02;zDJ|`IC?4rP z>!hi($Bwf)duCWC(Pf`2nH}jKyfL}^xLLCz-R+|%-5u;6-n;%^-Et2Gn&95qXOA|I zoo?d`y2p+iH?#i4aFijjZ_!JRV`sV#U}>UZAOA_FxbMKz7;Ua2-Q8EK)!Qc^lcsv? z%&}9gr@X4N?qg@qo;i8koY^+o|LxzN)}w8L#FLy}y9{WnHTdgb|GWNTVT|nBpL@;y z?Qj3$_V54IUyk*&>vWU9=g@6e_t(|_rQ5#&_RsxwJ~rBy4B>?G5dyfMoR6$z`L$Pe~hn%<>dZW+WhUHC#&?A_RJv)$nz3!R?vplPYwYx*-%>iYE?&1|NzT1P*6oOoUAJRh&ZZryxsikZ zdVk3Fweu>ru5FsPeUg9skWY5hJlk&Sx*d@Yqk{jh4F3OMYINIx6r;K8c6`6k{%u~j zBlU!JJ2tOvvd_wrjT%$Uj?^Qs&wtwb`gNm?b^hAUlR92D5R$6Yq$=^fv%wSNPi z-jUkj=^dMM-qA1>TNgH|_+|H2DU&W3^1MxTS;_M|zRy`Uc$uZmYnKh$IriV*|M@r4 zsp6M~DSwWAe#h&%e@z~p64|zJ(bD?HQ!+KwIOL8hQlu@9`4rQ)58Z3FBy?ol3_y{a{l&$eid7@n-18X z-|4{OPj<|Bx_VI8QX6KWw{1Z5`5j$1+xlJm{El^zQ^t&+R2SL#)+XDQ)nnZMD}w*u z4F1pG(fr7z`9Ewd98xs6sH8ZUR#nFVzbz@)qk?tD_6^sWZRNs2zpZbPzrAIr=7VjD zHnrCW*p!;PZKtg?binqkPVv%>W2h-T${(AlC&lhgVdhezsP28>(UAW4|cS^f+4xP~I zg9A?9{j+@rjJ>4S*=^@WTm19hklyd_wffSWD;|FB_tnEDt?#ScHdab{sL!{%px0b*5Y(JZqg?6wQ&|%P)U^%iY4y?}} z?6&fN?P=rp8SG3NKjxH4qing~vE|)!$bn<_EZJ-DUcuTO(5aQJwKcgbCV!B+b5l<7 z6W?rIRPb9tO7l*wOH#KjEVTWg`HjDx*7=Yze~s%j=~_A7Y)JFL%}ZLy@$n0lalHm zWFv~XYuH%VmU-5DY<#x;m(!}oy1fhRzqDFAYx$}3tuu8jMb!Vv zj_oN1Z6N>nR@RUIfX%4qziG$tH2*j2_I-EB9rqVoce?+C^`GI7urXx%*V?se6Tc+e z9$NcrtXkTDe{=tR>$8P__g?mP7Qe=pv!#Er_0!6K%+AWK{ok#hHvUq( zifik4=wz3@{{6O;d-%uOnrr7zHNK}`X6K;2{G0c&Z#4JaWAAc;{q2Oj!Eb5v@Phxf&GUe z%cJq$HY+Ql@wv9{E{?`;x7Bq?G``-_rP27!wvjK3#_zGQTpo>oYYTrxG+t`2T^Wrx zwOP6<8t-RI^-DBZTu9AceVxF8jHtl z3fp4wAvV3z)VTWU9CfJD7c&&LkGBtjujcinEyrXTG(W!Cwt2IZZ z##@;?_oT*W+f20b;-$7kt-biOHWTx_c$uxGlk96pZF8RN#qTlrp%-^Qe)EwRZ)Yp= zV=w-ViS~&XFR;zA*^7T~%kZfeUutXVGcP{D=H+!i{*Lvz(T{&_gTLX&``KjQ^y9zT zCg0@8KeAbR%a1RzHSx9|cW=0P$NID-de@JyvBBT-8vdE#`@BhV| z;ncSA-_6ejHk=K9n!RQ#a$(!}3R|#6ZR0C#CI+mGPq4}6t&G2IBgb{8`;aAmyE)TyL9w zmh1S$=5V&_NHY!RxQ=DE8c%c`6*iWIwn@`{Tce9yM-Lm%>8|5kTM>(0$Aum3twyfn zCEEsPxQ?5x=QCZ$Mw^$jT*s}p(wEm+M-%I~$aS=|xn1Ep_OMlWvFrH8mirRdvDMc5 zN#m`fr_I>OuH$E$F?ViFcaMne3;HAJ&)IU>xAjNT53;GdH$A5RWMfWs9Ut3j^jt@d z?IiZ|8Ikl}?l|l^J~NTxu4A=LE8TTGY#SoOb#%2cXS$9vZ76r*P5;vt(7r6+2DhP_ zx{j}HeK&I*8?5K%t|Q;JM+?_cV4F9~bzE+1tflM7GSbR*+-w`Uwd?rBrsd{3y}fNd zyVVv+ueX^`aUGj&t-7~rrq8gwDAje?I;VG`; zEt^$0TqI+t&1>qkXl#|`%nR(l99wlw=3B=;b`DH?*rvQ&s^d*lz5P7*V|C5)b0XgU z`jz8-EapbME{g3f_K0`~DDG{sXT&>DaW9L#BHlrYds^%r@wzIuv)Cu%byM8KV&90@ zU2%7d{UYAMift|Sk9awXZ7k;6Y~?DqcG>2uhjJ^IZN_>kw{+R&te0|@%QkDhm0P%M z^VUbXxyv?leU+QJY;)I7xv9%Gd;OJnbJ^za5alM8d)WLPs+{Sv&EH|l87|xW9j=`2 zvd!NS%5j%%{*F}kUAFlfpq%Ei&0n6f=d#UTzH+L|Hh%@m_Ac1`9yWi4$|;t6+WZwM zM_so0D^|Ac-#pd6&A86Ce~THWlecg1JH0K|*fGHy=pXL(H#202=YGgAFr-w2%8)We z8B(q&Ln;(yNTs3-8LB8lsuX2NwW18EQIsLIiWo9X8AFCEW5@_)3>m46A)}NrWVAAd z9HopQM=N8Vka>zSDPzb&Wei!Qj3K8h zW5{A<3|XR#A!jIK$eGF*a+WfNoUM!@=O|;yQe_M|R~bXjQ^t_owl_8fY%8<(yWylqZGUQ4{ z8FH1P3|XltL#|eoA=fC%kZTn&WR)_8T&Ij7*DGVl4ayjDqcVovq>LdqD`Utl${2F1 zGKQ>H#*o{TG30h-47o!YL+(_@kh_#I`AkuUe6A=%zEG4QUn8uC#r!{lhO zzcq@yj{`%p4tCvk7tN{Te#JdCY7G%sQ?4Wc`YJI$6Ks zoUbSKM0w_!ajo0Keki62Pyxw*v4h z?yUj*ihCOXzvA8&z^}OP4&YbZ_WLQCyv%4zZ;HdBXau$_Gy@&0FPGC_5 z!^@&dvMd@(mPJ)$SyWAyMKxquR7;jc!^pB|I9V2rAY;);02Yk`V9{s*799n^qN4#= zbPNEC>Ht_Y27pCl0a!E+fJNg0STq5EMfCtIIu?LM69HH>34leD0a$b#0E>xp$U>T+V0kQWwL0rUE+AtqrUUYSu`u^{cZOm1B+%eyeyhSmPIF$ zWzk%+ESg7_MJJJE(aB_4bP8D(%_qyEQ^{Dg0DwiO0kCKx0E-p@u;_FE7A*!~(Gma_ zodLk2GXYq1766OR24K-S04!Pxz@l>jSaco$i_QmN(J}xQT>!wM3jtWP9Dqd^0kCKV zAhhU&Xsn~1%(7l_7tS+f(f%%69QB=F&Z5hsUV$~p1B@WhqE%#BbRAh1T~EfM8vs~zBLItT0$|b204%x%fJL_guxK>^i*5s8(d_^% zx&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^mEP4QdMGpe7=pg_WJq*C2M*yKkmqufg zOpvTs-F4ArvgjUX(W6n{`Q@E`|Yq1k& z4cA5Xn9Tb)>N~%jMW02z*X;RLVA1CcFN?k)%c3vIvgj+aEc%)(i@qVtqHoEvXbV{u zeMgo>-;=TE2LKlR2*9GB09dpYfJNH?ShO90MLz?u=obJM{R+UM-vC(jI{=Gz0I=u} z02ciTz@onZShN#>MSlaZ=pO(U{R_aNNJ^rW-zs<>6$M~X3Lvy-b2Rpg36j;+-7Nf6 z7R__dr(!9-^UGP}r+BURlSOfcmqqDhS(HJRMVVw-)PyXHb|cH8res;vj4X?qlVwp0 zG8Sb4u&5;fi&_D&s5JnK+5oVqEdYyl2Vl`204!<;z@j|?ShN=ai}nU!QF{Ou?E}D~ zYycK@0ANu^02XxuU{PlP7VQh*ShODii}nYE7I`VLLrjpYp7uc8OG^n``q$h04ZJQX zzVpjj)HTH$-9;94V|ZEAoh*wECd;B6vMkCa%c34+S=5s(i+Yh|QE##=>O;n&z5p!h z2f(8K04zELfJKJ_u;?%V799@2q9XuUbR+6Ji;e3mwXc_>E zrUS5O1^|mr0E8A*q{N;xL9(v2Hwt-`vMAM^-e#uw&M#-ti7DRK_Mw&Fx@a!L%c6N? zS#%Ov7M)C%MW>Ku(R{KjI+ZMo7LaApX=GWnkc>r(09bT70E-p_uxJSYi_QRG(U|}& zItzeBX9KY48~_$A1z^#+04zEWfJNs6uxJ?oi!K0Q(S-mkS`NUXivU=(0)Ryq1F+~4 z02W;e2rZhO5^K`UEV{tmb(|xMy14_>WhuV%%UN_)ir4L6S+tVjWzp4SS#%9q7F|o0 zMXSiN=sL12x}GeHZXnB|8_BZhCNdV?48WpW09bS@0E<=wu;?}b7TpfOqB{UsbSD6d z?gC)Z-2g1Q2Y^NQ0l02bX3z@i5LSo9zOiyi`C(Zc{NdIW$)j{>mhF#r}l4hSu} zA|+O3f@J;TZdYF^i<;XTdAv0#zVpjjv^K??l`D&$W_Vfj3|SUEOO{3J$g*fXSr$D< zmPOB#Wzhz*EP8<~i(VvS(Mtduun2f(8D0a)|_0E<2ZV9`eaEczILMV|n$Xfq(R=*g7W>67X1pqqTc{m^g95Hb^x&G4*(YZ3BaPi z09dpWfJJ`;u;?EE7X1srqDV~5b}WhluqXw9MKJ&tr2??X1B4cRo)Y`m1j*`RPdL0U zWYJA7q{V#am$N7%=Kb4S7G*NLENViQMZ1w@QB$%kYDSht&B?N;1z8qlk!4X!vMg#v z#-i2$ENTP5qP74m+8uyJdjPPg9RQ2=1Ypr#04&-YfJN;AShNoSi?RV&)B%7+9RXO> z34leN0a&yz0E_kmVA1{nEb0Qlq5}X}bRZzKC?1P-?qe2x?`{#L$HJC=lN1XF#eC46?KQ7?y{&`%tB?%cYZmGYGU5GhsdH@hL=Ud z$g*fSSr&~T%c7BFSu~0)i$;@W(NSbsbTnBO9Ye;VIsg`p0btQs02Yk{V9|I07EJ(P zQ9S^Qjs;-RL;w~|0$|Z(02Unwz@p;;STqHIMN=oYRm-A7-7UyDG2i*+EIKLXZ9GgCoy_pE=oGRnnopKRr;=sS z0?5K7R`;t zeltO`_HY-}^JG!Ev*^m0@BDHWT@&-#9x02iWq4V%iY$w+Bg>-e$+GAMvMjohEQ@X; z%c7gfvgj7FEV`A9MXLc=bQ=JRZUGk20a)}H0E-?6V9^=?7CiyLq9*~NMJr>m!%UE@_3mlx z)w1YhdkX7474w~6&Z1{y-qCroXdT1LqV;51^c-0hJx`WJ8_2Tg1+px9kt~Z|BFmze z$+GAbG8VlGz@paxSoAsoi#7tV=nViCy$QggO#m!<3xGv$1F+~F02aLqz@qm6SoA&s zi#`Bg(T4ym`UrqU9|N%H695)%24K;r04(|pfJL7JLW`b`#ZEUtvI^asWS@~m-R<3J z-WM_7`QGkQ0a)}K0E>PHV9^c$7X1OhqCWvx^cMh&b^@^IZvYnk1Hhtx0az4CRkIz7 zq5v#P0bo%KfJLbQEb;(Ylm@^eAAm)1KxoldvDgL^B{u&M#-t zZmHh4MY5YTQU~y4#1*409e!x zfJJ)(uxKv;7VQndqV@nR+6RC|*#Io+0KlS-04(YRz@p9oEZP@%qMX!NjR}%G>O_oK+kY!OFSr&~U%c8MlEE)&EqVWJMngGC}dH@z33&5g@04$mWz@o_j zEIJN=MaKiMXbJ#}rUI~N8UTx?1F&cY0E@+(QE(~%>iK1i2y8`3kWT$ zO^sb?f@Cdm7u3UK(RioSyj0)$OEd6i%w;DS+syGi%uiUqJ?Bxw1_N=PAAKv z#bjBuge;5BAj_gN$yjt20E^BBV9_}MELsY{qH_UQbRGbU&Ie%8G5{7`0KlRP0a&yg zfJGMpuxJGUi!KIW(Io&Zx)gv#mjSToasU=x0l=aw0a$bu0E<=vLW@pLjcqnTvi`8> zog$0U-7UzgQ+?-`v*@~1FIpjsu4i~zbOTuy-AI;2H<4x0&16}03t1N3N|r^d$+GA+ zvMjotj74_=DclS8t znN;8T#2 z7HtM#(Wd|``V4?Yp98Sy3jh{<3BaPS0HHJm$T@* zRPX$1S@b=_%c391vgk*$Ec%Hoi?)(w(KfOy+D?{5Ka*wAFJxKtD;bM^17Okb04&-8 zz@k3@So9|Vi~a&&(M|vs{SCmPe*jqYF93@oo|^4g6a`>W3IK~@04z!cV37yFqBH;& z`2Z}61F$F^fJGSqEXo9g7JZuwQEZUtci}oPPqIP5~+7p09djYU$ZvYmx2Vl`Y04&M| zU{MDE7Ig$*Q6~Tvbp~M3z5p!R4}eAc1F)zI0E-R)V9|j9EIJ5)MO^_{)D3_|-2qs1 zFaV2k0HH-qz1R*DBWzk_|S#&sA79ByBMMsjcXaE3<@&H(r55S@V02UPju&4-tMa2Lt8VJCm zK>#c&0btQ!02U1aU{NUmi^>34R1UzR3IG;W0$Bb#*<~y1Tq%Y1F+~=02WOIV9_K17EK0V(QyDQIv#*UQvg^r6@W$409Z5~fJHL^ zSabpai)I3_XchpAW&^Nj4giZz1Yprz02a*yV9`kcEIJtwS~S9oEipl|a@_l_N6Mn{ z?%S(Q@qFi(v*yXh!dw2 zj73WUSadD`i_QaJ(fI%@S_Z(P3jkPjApnb(1F+~K02ZwPV9~_@EV=}MMVA7w=rRBn zT@JvaD*#w@B>;=A0$|Zf02W;hz@lpaSadBQwCGeX_M!=r)!e=j&s!ji{1z5gdA{?@ zS#+c4eRqs3x{2Xs(amI8bPHJ)-Aa~4tI4wHHnJ?boh*y)Aj_gV$+GA!G8Wwpz@mEq zSadG{i|zwp(ft4{dH{e$4+600ApjOV48WpC09f=W0E-?2VA10MELsD=q9*`Y^dta_ zo&sReS^yS34Zxyj09f=a0E^ZELW{2VV$JK!qN(oibAv28*gXMR@A=LzXVD9umpfJ# zy~yyg=q0i&dYLSXULnh(SIM&IHL@&voh*wsl4a2wWLfkk8H+Xnu;?uS7QGF?qIUpT z^ezC4-UDFK`v5HZ0Dwgw0K02X}=z@kq8ShN{{MV|t&=raHoeGb5)F92BdB>;=Q z0$|bC04(|jfJNT|LW`dFV#7?3tU2yR;|5t2jat~^`OYtA(T|=tcf2h6iQ#3@R7D4Zxy*09f=d z0E;4NYPMrh6o5r304$0DuqYLPMIHc)(g0ZG1F$F#z@l^j7G(giC=-B1O#oQ58vu)% z0z!+v_hKtekgPx4LysS1(c|vwx>=g<{BjnxO!JI}f5eF0ds9{`K? z2VhYb02Unpz@h^ISac8oi@E}^s2c!_x&yH2U;q~70I(<*fJHq3Skw~`TGS#f_L&Ki zH9FhG$w~`b`m@{_tyh}w{BjocOY>rrWKn;Hmqmw=WznHzS#%g#79CEOMMscj(UD|X zG=MCN^2o9%pNvHX04yp5U{MhOi;4kQG!TGAg8*1m0>Gld04y2;z@kzB7L@_8s2qSr z6#y)%1Yprn02WmNu&5eNrGzEY~Qvp~s4S+?{0a!ExfJG+&uxKU#i)I0^Xf^ii{=Bc=u|*x(de|;G!rE2HTN9tC|T6Ty=84dn(zE_7M-5v zT`)x!EoOLGw1g~+&LGR8Gs&{(EV3**n=FgYAX0l=b*0a$bi0E;dKV9{j&EV>+kMOOf@=t=+jWd8h}OD z0I=v<02ZwRV9|8|EV>>LTC^}N_J9eJ^_TmChefi;{UV}wLz?gWau(f^=Djsd7TwD5 zvS>9~7TrdcMYoe>(H&%2bSGIB-9?r~cavq&J!DyQFByyO17Okp04#a{fJF}iu;?KG z7Cj8WqDKH&^e6y}9s^*};{YsL1Hhsu09f=S0E?aiV9{Ct7CjBXqGteD^eh02)&a0+ zJphZI17OkffY73w(qey_AX(>lCeF>WsIz;s(S|hN`QahWzidCS@b4Z7HuNSqPNJh=xs6Gwa{v~70l=a!0a)}E0E@l`V9_@KEczCJMOy$^^c?_; zz6XRBy_gmoV1i_w?w+H)B#V~BEc}q>JHMPo+tR$Tvt-eBhL=S@lV#B_WLfkpSr+|9 zmPNmlWzi0@Ec$~ii~c0bqQA&kv=e|ue*>`S9{?8p3&5g?uVyGje0Ev00KlS-04(YRz@p9oEZP@1As+60a(-vfJMClSkwm)TGYyqy=;PHO?S75TKi#3 zzq>o5^|jwPHNTuihx*e9XuY%ODBpK}Ig7^l zUeA+d(O8C;MdQe_XgpaKO(4snda^7!mMn`Vl4a2(vMicRmPN;rvFLaJ7EJ+Q(Nq8y zO#@)jbO0930ASGx04$mbz@k|IESe3#qB#I8IuU?Ha{*X14}e7{0kG&~02ZABz@qs8 zEIJi{MGF8}bQ%DQ76L+xj`3q7OpvSx-E*`$S@c@Ag+;#a{BjnZ;d>{|mqlkXyevA4 zEQ`)2%c670vS=w;7M)9$Mdy)a(fMRqw2Ul^E+Avkg#avC4#1*|09dpFfJGMru;>y1 z7F`O!qRRkSbU6Tvt^i=sl>jWd3V=l`0a$c30E?~xV9~VzELsJ?qU!)ybUgrzZUA7> zjQ}jV2@qPe*pFRff@H^cet)J_lgY z7XU2!5`aZt0kG(602X}%z@l#fShNLzMc)Ci=z9Pb{Q$tC9|2hO6Ckwc6+d>M36fRc z(!_aH79Hpw&2II5=a;kS7vCGQSQh=t@UrMPvMlY=`9DqeF09cd-z@nA_ENTS^E!ytKW|$yZ`|WPx{49%ZaTc|X z`_33>I1-{z5p!h2f(8KfY740@z_HqNLJs@CeH5hu%+M8eUj*qxbOUO79A1y z-Z@Ja9m(*rXaHFj<&kAkK3NtOkY!OJSr!$MWl=F%77ZlJqCsRVDgj{8U;q{k0bo%n z0E@~1SX2(cq6z>ORRXYRC;*G909aHFz@i!e7S#fJ57+RwXIE@!(~xF7wY1^^UGN@KJM+kR2EHOcv)0WmPN;s zWzj^kESf}?MU%<0=s2=0I-V?xrjTXPR5BJ#17Oi~02a*vV9^NxESd?xqFDeenhn6B zIRGp=5r9Q=0a!E-fJG+(u;^p}7M%jXqWJ(UIu(FL3jkPj8UTwH0BA%cA9ES#%K@i&g-z=wbjCT>`+OO95DP832ne2Vl_^04%x^fJIjUuxKR! zi>?M>(KP@px)y*%s{mMZ9RQ222Vl_+04%x@fJHX}u;^w07Tp5CqFVu>MQ6riXPY2d zv)h|EXUU?E-9^&sxbOUO7Tp>5Rxgu9cQL#yx|=ME?jg&fd&#osKC&#jpDc?WAj_f$ z$+GAnvMhR-j75(Cu;@_$7Ci>QqQ?PPv<84hPXMs!NdOi-1;C=U04#bMfJM&$u;^I; z7Oewd(Ru(DJqN&|=K)x>0f0p>0I=vq02aLjz@nD{So8`YwCMJD>{SyaYjoVixkDCh zavv*tHSRmVoJDWMy`L_WMQ<{^EZRhtMQ@R1(c5HM^bT1Ty-Suw?~!HE`(#=40a+G( zNXDX%09f=f0E<2WV9{m(7JUl9qR#+W^f>^Fz5rm+mjEpK3V=ml1F+~D02X}{&Q6@;%b=fA)Z?b5CdmOTRy6^mQ7VVYpopOmR z+MD5JQG2p1+J`KQvdOZj16dYzB+H^sWLeaiEQ|If%cA|rShPO?i@E@?=l}o~9SFdp zg8*366@W$E09e!=fJFxbuqX$BMY#Yh>H)x_o&YTB1;C=-04(YQz@okYEb0fqqW%CZ zIs|}4hXSzZFhFQgyY$#96C|sR`?~!-)5Dhjv=$Z)PxqZ)&Z4|@@9E2AQ9i@Vq5`rk zDkRIIBC;$hCd;CMWLY$bEQ?CWvS=__77Za|Q7Hh6$^ckY4#1)c02WmOuxKa%i>d%v zR1LtQ8UPm60nLuxJDTi$(&lXcPd8Mgy?uC;%264Zxyf09aH9z@jk#EE)?4 zEjlti_LT{e^_e?~4Uk2n>@{y(y6^mQ79E@J`B%!Ki3~4`CXr>)WU?$ejx39gC(EKK zWLY$oEQ_X*Wzlr9ESf>aq7wjEG!uYDvjA8$8-PV~09bS)0E^}VuxK6ti%tSy(a8WT zIt745^8r|NDgcWX0I=vZ02VC-V9_D~7M%{jqQw9#S^~hLGXPk0CLpwELVB#L36gcK z`=;W0S@fDaqn(xRJHMPo=capQD`nAn3@?k$C(EK`WLb0pSr%PLmPO0SvgjhRELuU9 zMHiE0(IsRox)gv#mjSToasU=x0l=aw0a$bu0E<=vu;^+47F`3tqH6(IvndMXLc=bQ=JRZU=-Gos%A$X@X=GxepI5l|{R| zXZm-f`_3PGV9_rCEcz7?TJ&am>>m>(>rQvOdXp^r+g&96mhL;hoJD`8d;8oV zi~eGGS+tWZi~c6dqJPM;=wGrdie#weE{mdMS(HMSMKQ80N+n~F2f(5<02cWGEQ$lL zC>?-B82~KG1Yl7U02b{Az@nxAENTY8qUHcBY5~BaEC3d@1Yl7s02Z|dU{M<^?Es-gJJMr?CP>z0?ndJuvS??9g*`KT=a;i+pA4`5CRvot@Uo}_Sr&C9 z%c4$XS=5;Oz)92avJoKmZmU1i+%M04(YTz@qK|EIJr~ML7U0 z$^~Fi4*(YR1Yl7w02cKIU{N0c7WD;SQ9l3{^#@?lApk5o6o5sC0kG(B02Unqz@j4o zp+$RV#Fm;MS-$)JqV^eKOMk5k12TN)m$Rra!@K0a#Q6z@l0J77YVn(Qp73jR0WL zNB|a%0$|Z-02Unuz@no8Sab{ki|PPaGzNf0V*yw+4uD1D0a!Ev5L%R<5qsSP$vW6I z%L-)Ck?x%#^%=hN%ULuz!`rr679Gd%vgmlSESf@=MN`SLXc}1-O()Bu8Dv>>0$CQ# zB+H^%WGtEuz@j+-EIJW@MRNgIG!KA9CjqeNWB?YO0>GmA04zEcfJF-cSaccyixvW~ zXb}L5P6uGoVgME`0btP?04zEafJJ8ku;^?67M%kKEt;4SYjc}fRJoUlGf5Urcb@@S zn&CUYoJGqryuNqHq6-*a7F|e|Ma#*u=pwQ#T0xdY7n5btC1hE2DOna>MwUgFldxS%c4)nvS>3|7JW*VMW2ze=yL!TeF4CtF9BHe6#$FA z24K-Q04(|zfJIvXSo9qLi@pb7(GLJD`VoLdKLN04D*%hO0kCL00E>PGV9_rCEcz9I zMZW>C=yw1X?Er)py`2&J#stY)?>_eNjx6fnTlgcxcYZmG{?72y@0UgYFuW}Kmn@4S znQFPqq9|DwrI2M&j4X>%$+E~J%c3;0Eb_@%6bE2YIsl6@09cd>z@jDqEZPl#MNI)% z)C_<{%>h`{0)RzX04!<=z@kMZ5JpfqL6M#j%09e!;fJJ=( zSkxDQMg0I+)E|IFhXAnXPyiMk2Ed}j0a$bd0E>9gssdn9H2{lh09aHDz@lLQEE*2Lq7eWr8VSInQ2;C&4ZxzK09bT10E>>0$CQ#B+H^%WLY$uEQ{ulWzmUbESd|z zqIm!;IthS9Cj+qP6aW^@2Vl{u04!Pnz@pOtShNs;MT-DfbUFZw76Y(o2>^@E0ASIX z04zESfJJ8mu;?5B7A*x}(YXLDIu8(9bX;aE@|aolsr!WW@v`U*d(AsP(|3M3i-8$+GAQvMjoiEQ_upW6??g7F`X%qH6$H zbS(gjRspc+Isg`355S@u09bS*0E=z{VA0J0EV>1NMYjU5Xf*(fZUbP^?Eoyg1As+$ z0V02bX1z@mEqSadHSwCIA&Sg{F`b)UPSzEBp;aMwlmW%|x9XVF8M-oz(m(ZdWc ziyk4%qDRTH=rOV^dYmka){te<6J%NRBv}?cMV3Wt$yoF>0E?ahV9~PxELsP^qV)hQ zdJcd^&jYY%0|1L&0ASIJ04#b5fJH9@u;>*47QG6^AjGbqKWZmmN4*Q@idfOeC-pTZxU(TWrGQB(3%AyY$UKV{smPH?v zWzi>OS+tofi#{dGqR+^(=yS3x`hqNrz9eJOR{$*f8h}OL0I=v=02XZlV9|E~EczaR zMLz(r=tlq+{RF_GtpF_A2Ed~204(|$fJMImu;^C+7X1dmqTc~nv;%-ee*m!PPXHGE z1qdyAFEjRr36izO-L8IL7ENw%VP~fA{BjmWns`4yBa5O<)RLD)DgTGK_kfS8c;CLy z$!4<)=^J2|o)8caLb9Pt%chadrjbo(BAY@WbVvfy2?_#=2qIDhMZu1}p;%C`AgHL= z8-f*3A+#te?|q-SugwPiJkuX3}6bw)l4FeR}V1S|+ z7@(*b3{cb@1}JI)0~Fa|fFcJBP}C9zC~5@*6t#u{irT;cMQve#qINJqQF|DmC>DmI z=4l=s&_YocXrZVpv`};J0-F^??D3`oaK3{a}Ei z{xCq%RWLx&02rWXAPi762nHw`3N90n*F0Rt3`gaL|1!2m_0VSu8mVSu7BFhJ2YFhJ2* z7@)`p0~D3O07a!RKv5YCP*e^B6pe!ciYj1$qVX_5(F7Qvs1gP!ng|0FO@g5)$_g{> zAV6%(`TMTjLeb;=+1SZp7Uqj7njU6;eZNpN1L=jLnb1N}6|_)P4J{PaKnq2)poOB@ z&_dC*&_dB1XrX8>G$@(}0~F1N0g4vD07VO7fTBe(K+$3tpr{rGC|Uvo6kP`c6kQJk z6fK1Tik86uMK{0zMayA;q7^Ve(MlMg=tdZz=q4DTXcY`lbTbT4v>FB|x&?-!Xlj`0 zI00gt%wWC^`rO z6ukoj6uk=r6uk!n6di&Air$9-iavk=iavw^iVnj7MIXTcMIXZeMW4U`MW4a|MW4Y? z6g?ManoWS%e&r>iT|&`He#h+RVHW0#Df&9hyy1{g^bOJrMMt28qHm#vqNC74(J^SD z=sRek=zD0P=m%(_=tpRw=qG4U^fL@lbQ}gKIspR|orD33et`jseuV*weuDvuPQd_0 zr(uAiIvAkn3=B|o76vFf2LlwHhXIN%zyL+{FhJ4oFhJ2CFhJ2o7@+7+7@+7c7@+8H z7>c4V!%Qy{Ahy5w%^+V1MN?x)Tne)=UrdoH-24@-XE#et(#*l(jc591XrU+sS}3wW z3q@9Fp{NP8P}CG!C<=uZio&3UqHt(X6afPiMZy3@Q7}MJGz?H=g8_dMeSjLqF5N9C=LcF>Hq^2 z#luh(>EWiJ4~e27{8sCra5YDB^8bY1G2Fs@F-2X%&G8=zMO~3z`l2hLg`#fILQ!{U zp(p`bDCz+%6eU6nMM=;?krP@dN`?kSJz;>NUNAsWZy2Dc4-8P$7X~Qm2LlxKhXIPN zf&q#KzyL)9VSu7RFhJ2@7@%kf3{aE;0~EPnfTC0wpePLnC`yL`iZWn;qD&Z|XebO& zlm$akbVax+ivY3B;>mqyq38vs$Q^EBzL=uiaP!1ZgrYp87mD(sg`xszp=cPiP*eyl z6nUYAq9SOas2Ex(8V)TKjerJ4BVmA|Q7}N!Xc(aAY8aqs3=B|o4Gd5;76vHt!2m@i zFhEf$3{X@C0~D3R07c_qfT9W*plCb{P&5GsD5``3iYCGUMU!BFqRB8o(G(b?D7qd7C|U{w6fJ`R zif(`bik8CwMJr%{qLnZ}(Ty-b(M>Qw(JC0A=w=w8Xf+H_bPEhnv<3z!S_=ad-3mid zG$Y(}m;kYj;O=LpP;{2xguO1@!hA7B8^X=!z7UEwBE3+w30f%H3@sGh0WB15ffkCk zLJLKALJLKAK?_COpoOBlp+V6-FhJ3E7@%ke3{Z403{Z3*3{Z4G3{dm{3{dnS3{dnC z3{dni3{bQa1}J(21}J(I1}J(A1}J(Q1}J(01}J(G1}J(81}J(O1}J(41}J(K1}J(C zhN5VFxT)2bMA0kU7u_xty%j-XSGa}wVv1f2HxKw)D0&I$g`$_Cg`!uWg`z#sLeZMeo7@ zMeo4?MTcO3qW58dq7Ptzq7Pw!qQfvi(MK>q(Z?`A(I+rK(Wfv#(PuC~(dRHg(HAg4 z(U&k3MK6S#N(d0!qjmykw@|c?ABTJuZehNdqHn{^OO6OdN0DAAItDEieFrTReGe@Z z{QxZ#{Rk}-{RAx({R}M>9fuZ*PC$dAlQ2NhFEBvSuP{K-Z!kd7DHx#WGz?Hw2LlwH zfdPun!T?3*V1T0YFhJ1-7@(*g1}OR+1}ORi1}M4+0~GxU0~GxQ0~GxY0~B3?0gAK; znV5qj9fqRln{d;81c>c+ev|AGp{NBv4hf2|FkehjNQC*#qe77d>4hRIv{2LpS}1A? zEfj@93q@hjLQy!hP!s_z6h%S{MN!b8C>jPRvcUjFF)%<;GZ>(#ISf$L0tP6u!vIAN z7@(*n3{cbx1}JI`0~ED^0gBqf07dO!fTH#=Kv66VP!tCP6m@_BisE5_qK+^?Q70In z=n5E$qTmSANdm++fd|y)2sP6$;I9hp9ARO;n4)eG=J4-@qV7m96eU0lMLnQ}qC{w+ zC<$69azYD5$g=Q3ec9lnDbA4TS-UvS5HBHw;je4FeQ; zU?_^ZMwpTb5ZeR%=F2=g~5grYl;UMSiEEfj5q7K-kK7K-kI7K*k( z3q^NB3q|)p3q{+Zg`yqMpy*y0py)mrpy+-Wpy&Y@py)vupy(kOpy**3plBxyQ1l24 zQ1mDaQ1loKQ1mzqQ1k>0Q1m1WQ1lcGQ1mnmQ1lE8Q1mPeQ1l!OP_zpMD0&_SD0%^g zqG)4;DflE&w1?k!y-6ra4=v8Q;=rw4eXfL!-v=3S+ zdL3FQdIMT0dJ|eGdJ9@8+7Ati-i85+4!{6K2VsDscVK{`cVU2{_h5jcLoh(m`!GP! z2QWa)ga~PoL3mBm2OBkT&D;S{YYZ##D z8yJeBmm*Br1c)s-mcV&gC>m`daU{aRd@)7eMVKd_5{kY@dZFkCXrbswXrbsQXrbt5 zXrbshv`};cS|~aREfoC%EfoC<4T^q)0g6t+07a)^fTB7Wpy&(?P;?dsC^`oN6rG0w ziY~waMfEU1(eE%o(H}5C(M1@b=ua4+=r0(c=x-RH=n@Q2q(#cK9Te#>Kv573P-KDu zih^M%ijGE@)({}J_58l;V?xnLe#@FU(!zW(MNJ~jPt*xTO_5$G3WXMm!k~qsaA=_@ z0$M1FgcgdTpoOAnXragkEfmE-gQ8|IKv8oTpr{25P-KSziX1RNQA-%0s1*!Q)EWjT zY6AllwS@tS+Q9%t?O}kTSQwxv4hAUd00R`o!vIAcVSu7eFhJ22FhEgf7@(*N3{cb+ zhN8$4Y5JG|v2EssMr)*+>0iU|n7uO6!hA7BJtEB)&I(0|NG}v6K?_ArXrU+>S}5uX zEfn>F7K(a93q^gPg`&RDLQy|xP}Cm=D7p#;C>j6*6b*y{iUz>|MT230q9HIqQ3?!D zL9R?`MfB}j!VSu8cFhEfj3{d2T0gAF=fFchJP?Q4$6y?GIMR_n3 zMcpG!ZO#!zfAB+(1feLDKaZ9lX<@#YB5$O5&;_BW2W!2m_oFcd|@ zB28rkh;0tPF|AN2I?fc;L|T|Hrf5#2`TF05qPa*f6wQMcisnNLMGK&XqJ_{x(IRM} zXfd=ErAw_u7d_e*TVosOJRVbWiUX|4KP5_au}d!1q@KM5(X%`5e6u_2?i)y z1p^e_3qQ_x? zq9B0g5id07ZYo07ZYn07ZYp07aKzfFdnQrtP3ehXIO$V1ObM3{Vsd0~DEIfT9o> zpvVG4QS^PJX&wP$o7alK`9Ub!&9^sel!f_Xio&AIcLWJV;YcqOML-Khk6tqwj z4J{PepoO9sXrZVXv{2L>S}1A(4T|hAK#>CmC~64<6t#i@idw?}MQvb!qP8$VQ9Br* zs67l&6bl0s#lZkY9bkZ>co?9lBMeZ~2?i*-0tP7R34l=6&_Yo!XrZV#v{2Ls zS}5uZEfn>G7K-{q3q@B!3q=EbP&60@C>jC-6s5obMJ^biC=~`MN`nE4 z(qVw23>cs&69y<63Ih~n!2m^W7@#N{1}O5t07W@4Kv6CXP?QG)6y?JJMFlWG(J&Z_ zqQoduh?yuV=jUiiLQx7ojV+9_Fkej3@F;UKI>4l<^&_dBDXrX8{v`}<4v`{n# zS}3{(S|}O|Efo2ng`yH@P*e&76qUgMMddI+(Kr~Or~(Ek8V>^$O@IN4Dq(=4i7-IX zBp9G*G7L~O1qLXZ3Ih~Pg8_=B!vIAyV1S~TFhEfi3{X@J0~FQ307bK4fTGzj6h%c* zrW^vqR>}`xi-n>yHWJrHS(q=TXnvG=Y7?Po0n!Ua3!#OgMbJXgVrZeL7FsA;0xc9> z2Q3s`4=ofeg%*mIL4%?jV1T0KFhJ1?7@%k+3{Z3<3{Z3v3{bQR1}M521}It$0~Fl? z0~D=+0gBeb07bXL07dIyfTG)AfTHydISb2dK3mIdJG0AdK?BQdIAP0dJ+aGdI|<8 zdKv~OdIkn4dKLyKdJYCC+64m?Jr4sEy#NCg?S=u0UW5UPUV;INUWNgRUV#CM_P|gS z-5F*2lmM~i^JDzGgrXAuK*+067Uqj7dOgbgd$>^a2GR>fZ$b-2Z$S%1`=N!Rx1oii z1JFXzL1>}q9cZEGU1*``J!nvL2nHy69|kD;00t=f5C$kZ31OpU(30s|C% z3Ih~<1_Km*4g(Z@0Rt3$2?G>;1p^d)4FeQ?0|OKtfdPuXg#n6=!T?3bV1T0UV1T0U zVJM3BMw!}05Jks%iD;itbQ3>~{UOT2d@)7Gqs&91grXBjFBF}G7K(m>7K(m_7K(m@ z7K%P;?d=6rFP=noj6=pqbI^d}5Z z^cM_J^fwGpbO{D1(xPSB4vKUbpeP6iC^EqSMZqvYkr@Uk3V{KNEHFTk6$U730s|B^ zg`p_=DatgC0I?0>ckll!6lL(|(L$pw%okG>8Esx>6N;jcUMPx&7K&`pLQxE~P}B@s zC~6KZ6t#dBitNxrkpo&NY6%UBTEPHCtzm$oHZVX@TNt3I9Sl&^9tJ3ig#n75L;iK-1iiULizSq9BpB~n4(e9=4iW6G#crJqN|~WqA}1y(KXOQ(O77q$OkPH zl|TzcrO-lA8MIJT4h@RN!2m@SFhJ3G7@%kZ3{X@F0~Ae!0g5KU07a8wfTAfdK+#kf zplBKlP&6F|D4GES6wQPIimG6MqG}kRs0Icongs(C&4vMru7v@L=D+|&b73foMns$X z5Fobacyv8dD0(T5#Jp$=^TiY`iZ+jEDHJV6dZDNmS}0lqEfie`Efif3Efg(<7K)ZZ z3q?0T3q{MJg`ySEplBrwP;?^^)iq^saMYqBL zMeAUIqT67AqV+I9(d{rm(FPcxXd?_zvZGi!bw!#2KcfwEQP zAV6%#Ed z3q=n@3q?Djg`!8GLD8cyK+$6`K+)qcK+zL0K+%&hK+#h$K+)4MK+!WWK+&@>K+$tB zK+!H3py+uRpy&k{plCM?Q1l`UQ1lWEQ1mhkQ1l86P_zdID0&qJD0&SBDB24{QFM2- z=`{kx);)~Cxko6P!VB5^qAko9Q}kA}`B+<_Xg|^mMQ=k3MF*gTqJz*v(L2yW(Yw$> z(R4l$g8_=V!vIAIFhEfc7@#N-1}I8`0g9Y3Kv6ObMNyQ^ zbQ=L;^YOGS+NNgucM?42o;C~f#T50mnV;z>6!k-Tp{PH!P;?cvP&5EqC>jVY6b*tF ziUvaqMMI#4q7-PM$OR3GQel9iG#H>L9R?`MfB}j!VSu8cFhEfj3{d2T0gAF=fFchJ zP?Q4$6y?GIMR_nlQ9cY%Q~(1M4TAxS3SodEFAPvr1OpTm!vICYVSu6$Fcd|-ZKlr& z5ZgQa=&X-Ww9}Zd*(}T#Q#8hAzIcUDbPduAMPs3bA|JF+R01s&l|lWXci1mG#dsex)uf~ngatA&4mGq=D`3(^I?FZ1uzsvqiv?x&P35n zeq-9zLeX3Nsm6si3-iSkEwPzhU4^3SkX|Ud9$F|`3M~{ZgBFTzfEJ3DLkmSKpoOB9 z&_dCT&_dBo(4c4)3{Z443{bQh1}M4(1}Its0~D==0g7&g0gBea07bXK07dIzfTG)B zfT9gBK+#4RplA~eP_!8aD7pg%DB1!86m5k8itdB~itd5|inhT3MR&tc6fL%y#uFg6 z9VE@QLeW9~O00Wq7UoN9p#_=an>^87*X)C6)UDZl^mVks_9gU`#A@G8H^MOc>oll} zvj0fkSu=aL7MkX;Gn8%Y&(RwwW9@&@D66AAjsAz4F7}min%3R^9zAYJvNyj%(|Xyj z?xJb^>~~+OX#?#)cGt8NdqSe7rQ55WnwDjMzNe<;*e~_gv;uoZKTRvL-*lCxjkLc% zP}9cP?L#!J#D0xS)5h7ir)gTH{pSo#n_^GQ(zF@&S=pLaW8a;lX>;s)zNRg(4;`jy zwf396nzq#bVX>yIu(uqkX{+qM(VDi#e(xAfyUl)Ltfp+hX$S4EEYh??cJmTVJ8bt{uW6s!*DlkvFYTW!*R&({wl`|pclPpCn)Z|Z!PS~} z(*D~TO*>`py-w54+UKv=w0iri8#L`thh;O>zwXH0LKi@Hthr-I?%;2?9;Z9_>xnCM2YbbZqXh5 zVaaW}gFo%ILwE4Ul^)O?{CSg|x`RJ3@VM^acYHssJNPZTyL1P?=ki6}!Ec(|qdWLr zPy2KSzis6$-NElWIH)`L!SNy8!B74U>kfW&^QrFOwf8S|2QQu;(H*?{^_}kE<%^$m z2hTrG>JFYjoYEaU0z9ib_!eHTJGc-2Q`eeiQbRHCP))AoBh+?6dPT=tG_6%6O>Xs` zp)s`0Km4&`eM?f3uC+GB^D9Yx=@nWzF@9Rd(>u5Ho|)_s<60{Hwq8lO={>JuZzXA> zOl$K3=h{2s7TVrLzfaO{+kO$`^)WoH?GP4yMbuKu)%!(oO0Df2DyiOIUP)+2;wllg zRwM?9Xvt!rh!py^bA6DAGaX0_77-joVu*-J>KpVFCE5`p8lPuu*#6QSt=(Ws!pA95NkXEJ-}~L8^Nck2T=!%Q3o4-395%nz$^lyJK}s=>k8obH`z9beE7clj7n3Nb`QC*GhZ}Ws`?ue{ zINvDqGf$s+i%x?wjQ;yGj}{w7X=ZYU4%*-o9wv#SFYWld!bp7I>bFj-#7`V}YTaDp zgs;EhgNNp8?P?^^QXH|@>pSC&6S#KNq+H{GFMe>-Hg&+MFTd1FYj-Op;i}o7l5o{L zYEp+jfLsP&-D8}Q%i8z$_A_!>d*37PEijH;yYI-u3$=D1P?|-Q&EH7#przepBhByY zPMeLYd+zkcF-DS)Zhq&Tg<4z-Y9w4e1~v)jrqZP&Y@S|P|GUEG_vfB|R~=*H#r@l< zBkqt8t7-fj5@ZVLFn~7rH^fBZ1!@TV8)7E0uL*VF^c&L2)U?AKa``vpLQqJDC+XJ5 zzac-7*hwz`h6I~JG(B4H6cH0@ifA2CY>(EX?3xzTQ40+nOqQmZT4<(-t3n5a_78Q( zQ0FbLP=hx2*4PON)=d$ELqq9hwVO_+r3cl7xnahlYjrqurzIjrNMBy#mT>6DdcFkt|8_ zF`G%2#;XlkHkT}AuNIWZ+)xgCI2DwS>@YUy+*Xet$OG~TB0DGTe@SS zbz4Y^V?%07K5lDsK!PCqbE#D4Z2~h9uWg{m)!A<4bvj)yr%_|=Z@f;|f*fm8saJ}n z7c_oB)8eoXVbeq7;!KM$NmRLD`YDHq{l!`ftJ*G@AFP)NDU0GUHkyuqRt)jZLItaq# zl~E&HE1y1f>hx*8 z(is!UBbvQw89u6(@-)LIkGdiNI*|{iEREhIZ>IbR@t(Tb9P^)k%zB7vf^KeZYT3hV z9cZ@Ynav>-LMTm0BE=YUOncd6D@h9q)|;C{IYgS{IMA+!>_IOlQ;HUe=9oltE7QCl zW?N@-jA?FSxOj7ZQ zuLe;GI+7j48F8eeo9(>O*(hvK2pi4WkR3wk{F}t`iBhrS%(k}XxGT&y(>yLS$&lu4 z8s!I66Mnwy}*$N;J2l6S2mc zn}nDm2bx=i=yC07JJH;clDB9_n;qy>=z2(v@Tv3lFeIl+<}^v|%^l;-E!vQdV;vCx zo8)w~4(1kZ|A(o}O%ly5+(sgE(gZ#?-E5=qKZ2<_CmNh!j*U0Rv}tr56e&`Cp)pp@ z-jIC#m_|L(9Gj%-oG&Ny_1~o;9_XsYbuiny^3{>F>O@r2;Jp5~1n?=CJ?0oU?VOmX zkdC1OweMi$-J0$H)4Yv39hEr2I9=yebiq0i!gEx!vxRWOY&Ztmn2K>`YFkFTa{MQV zxUo=GUTH*Xh#b+{;{MNU?mwtW&i-eU4C^sLAw!oS$s7~d2>+`pw+*7YrVAg_xPlv> z{C@|+{}`Vu_>w1^Cciy1eFE?`UoZSlr`MJjg> z=0tN#qXQXb)L3i>a}4L*xSB3&8+uP_nWhtqxKD{mY-jG+(cI!nvbbkyZf?=-|9xYR z3Ng6{nsw7&y+>?NTN+bkdJB9Rg@rzM-f&lrJKg6h99o>4kyoVQh1?9U*EKZ5SCpUc z%gN6hsugAo^*LQ>S^hoJioC^?J}p1DASa`U_AJhG%YK<@S-!G{9bJX#zP$V*+S!{? zSd@|Oe_w0ddu|=^`#bPW>WrM_vj3Nl7F0;JC|$I*oSK}H7T&5?mS;H4%}Y~=ge%h zOIqQmf}(sn<(wQ}LB2b$C__#;S@w5Pq#;VrWM7SO2I-BGr{>W3q%hOC3>kSYlIdE0 zrq}06SK0J7_U4jh2Ap_CQ5NdgSCBQzN7p)+u5y~I$eo|3>Z!j!p))NYrMqyLFO?We zcYD>rP?su8&dj)Mz8rU+$6sqB+?j5ltH3B_T7F($MjF#%keAtuE6mtT7bLvJX=y~M zKQ)jYR-93s;mf3&^1oEzDs&f(@=Jy~*OfO)E?q+w#%1&7dyNvL6V?6#^fr!#-*kT7O-*5 zd~cf1Ta-_Ann5_qHB@!eD3gHp`I6D5n;>hh`P!QH}b%8AV0h zmT~CJv>cC7+@8Hu%js<#(KvV#ETb_Q79lLxs-L{*r0VnM=5`lmx_lXFX+CGFTbg-V zqo!zdE$MF8P+xv=Q9*H$Z+L!A5w#zG7HAFJsc`qhT~|QsOwSnZrU7|su~*eHwT;03 zNHryfnJSqZH`hl%^1_kSq<#6rGYT_v@<&{L(89c-{%(`Fa^?DWa2HT#CYQK?x|6{E z)Ho$Ck>Kwnll>Kz8c;cWff^32cn^4)E(BGHFJoj{Mn-x-k)=YYhb?kZ58=re<;!%r zxs~G@${svXp`zs%7t#i`vCJHIT0^gIP|BT|zv`UH{svA>T{S>zf8%CNojTW_x6vFj z^4*P_4USCRaBhAfUk>gkRTjxc1DP^?+Jso@v<$BovUk!3(o!9I^BZnc-0k~clYX}_ zBPYY?o4K+w8grzsG@mnFOn0WL6jg#g0Y@?V9lki+!x?uoDP<#W(CB@xw6x+vSDJKT z{_4|RKqXTDY8L_ihVyeeZ7B{xp7QKwz( zO*L-UK5rI{P1K&$ouOk3IAm@HbyYHG!I3yWC-sslU53HYtZ9L#&wEhs?=N_Ia=P3S z3p4W4iPnJr*MEW2jKPmEL$x?m3b@M7evOD1RI(_ifI(I|PKz$?WlXra`@5{;2^>UFS70<@qk8-;!`Zu0Mrb~` zS^@X-M&SJG-K>F|ob-I7BlX`rLY<6UN~cq9QgqYyS0LJYk}rK&kuN<<-M1Ux zQ!A>gOD9w$OsSYQp{8}rMh$6 zqZ`J`Nz@5*lAeva(uQ`=jmHmQ1IKi)p&p@#hM9cN_V0kJX3U2gE+)0GG#UY~pDLY=1p+r*sd(`Ps}BP9Q$ERAl@jYhq> zlv8T{NR5~W#eMqyBYj#9-3#dM%6*klQ>wr9r*S4F2jt*P>M7^s@0RIe_%m&&K_1EZ zq#9KUx_=rQbg7j=eOf?QW?b`z8QWz8ap@Hs-$Z&*P8B|08m_3SQhCw@?q3R{x^Qaa zT&hu8{;ZmGBGBilnCqT4u40Z#N;6YqL(ONsw5r}P%H$hU!|;seveHC(Zf;yD+7OE; z&xS?AYhy#rDGe*hzn9uVZyPX9G)A{H36e1zwRe>poohg41tj2MC-rFtH^#0FvqS&1 zwvXhZCUiKe>fBExl)aFHUA3%6>?7iGaHgL(i{Oi~j7q`*sU87;Pf7p(Rs+w1!7NklWw^Cdy zqdsWJr0RoaZvpke_eY+>_`DWl->{oB~! zNgNw$u4TLw(4c6L-B3fkc55uK@PLID6?{WoZndIE-1&Dy<H{!xL?i(GPMFdG>`}0;dYJUg}PxK7{)BBBP%CdwFS&OKSo$??=4_ zJkS5X^%Oh3qHNX#qegiqheC2wbfqe`)S5D0!5L=K1dZmhzRVn#w;>%~EiPcPd659i z<(JK){MRNeGp*seIC<3?N0Oxvb-y$&v|4iK&A^pwW1@FiztJ$@OwafaLr%WHqcYT_ z7qh*_ZJ*)AJjFk@qk}tn8QLh2T3pX{jr67E70HbyaBbNr+COiTYF>u(^sm7gSvD+E zJ88)*uqidH^YF>4M$oA9@z3TtM}IX2^5&loOWhjl$HrmNgE!o})M7Bd$a6qrCtevv zsf`;iU3=m-jhflNKdMkGzYTYye{?fW%om)zii*4gi=64sp}|?;LP5ju#OqCyXEu%M z0q_DwTKSYw!*n&WH$t+yLpCZB3gGXi{S_9_aq%n>JK_)ubpMUhsI9;iPXmO1yYH%A z*uO-Ee2phDX!S7pvKAJr9*p~2_|iMmHEq188ZZr_#Tl7YWR#DqEJ*I%XIRB78kWzP zRpXtd9y!oW{GYVp{HQ0S83paR(%^KL<${JV?oUNKY;e2UHU&brOSOTm1|2N->hBvawJCKZ1 z3+U>ld8o0If60^j1`L3t!^Lwzr&_5svf+hMV?&L*aZ=p9H@S~ zRS&Ao;e60^n0tDNeEDjpG04hv1&&~l0=sfa0wyGM3zgbc_Zfa!%^YyZ0yP|`wLX8n z7zk1?J1={{(XePk_oPM(Fb&g5dbTc)%eZ(v!|_kNaC{y!7&pUzoA5F_ z3?C+LoJ*$kPfl7f^VcfsLam?%yj4KWHjK&%9K#yZ!V&cNmmh%V%M)D`NiE&;NH+( zQIi}s=5KT>HqNnOZB{*%K*1V@ca5eroIN#!Vmd99jk8fx5@QQ}wOao4`7m!r#sOV_ zR-uP3mTHP_y6_|YS7(Harsn9SFH6a*LwqAv_0zC|%4?JUUGezFm;??jlU@i+i)f$sXB9}dtvVZ-S668+Ho=NCkTg&S`e=Xc2R55F-yHNvqp zWSRMf;N_+jL92Dm)t_D{<@Z@@dLnI_`z7S|pgBmM77}gAZDML_wFNiRo9lLyLvN|K z(p&3o^maiVboxllKYjwOVD0p!z#UBdX5fGy6TcBS;K#)81rGQz(ffeu(^COI!5V$S zN;~3Dre5FTPo`e)=zlZ3f5XVbq|qld0)9;XPi`sGq|rO&1Aa_en#& z(wQ{+a8|&NNuv)e1pJtc(l;0;tvUTO-idEq7aN^#Qp3wy6m1W_Oy^vtM_;C=UZ&?? zrdM93`7>zv;p5>w)-rbLSfh2M)@(d4`1iqlz@voA?__~@xt`j;JX~$qA&H({1SonQ zrrv(k3MXpUB!_!e~zpveb8hyNBYRflM?rFr2Y6KU`^?xD|O=Y zC*RoT&vG@T56d;E%O%q1T#a-yB`%h@RN@+mcT0Rq z;`0(;k@&jA0}|ht_=&`?Bp#Fav&7#do|AY{B7dZW&xgNloFjc$(}*z=`CFyfZ!fWv z#BLIu68lOVBr#2*TVlS%Vu@EvER{Gx;#7&%66Z=>EOD8{nN=%a2SK?ra z84`0OdL@pQSSqnn;&h3#B`%b>RN_q%`QwFLo=pod#6*dGBo308F3}^gP~s?wB@!n{oF;LW#03(smw2PZwGuZvj_YzM^JR|WBi8_6(i0j8HF;Zd+iESlzl$ao~kHjGo zvm_3aI9g)4#3>SINn9jxxx_URH%Yul;=>Z3miUsyHzd9%@l%Q4N<1#{jKn`Bn(2nc z=Nlo>E-_YOSBc3I2S`kpm@9F(M4!Y;i8Ce6lX$(vRT9@ryi?-+5+9fNyu{Ze9*}rg z;#U%XkocR#dWkxH&YsV&sl;XydrBNiLp*-nD{&&-yIIeYcoPlrSZ|QXUk1SXd5Q1Q z4W9KE5>L|*kM&;?`_Pzxb(+KlG=^ZkQsQeg)?odfL@WKbuB@9&%xkao)e>)uQ~GX+ zpT{fxqr})NlunR1o(344U$w-YS1SFy#JcWEUy|651|qzFhQviqrEikBucy-QOKeI5 z7T(`3v7n#Q*GRnmDy6qe{BoeuKTGT|MCn9{l`f@cNqjU->D>~~W+<&^s(2MmmH7Dd zW+5Zi(ibhTzFFcMG(cwkp~SF!rCUlY9Hz8S;zqC1_e%Vl23(x}gv5>`m3B&;G+OCv zB|bhz>6av)AFH&D6^ZrNDs7&l;^28IdL%Agp!8aaZ!c2%6Nynvlx{0= z`1MMcOWd+d=?5hqU9R+R61&`}bZ?2%Rw+GS;?t{@epTWhYm~OERWW6qin$VRSg-Ut zi3c|*{h37DW~JLp9Jxj53W;~#sr17VzuTttX^B^ESGupn8TTr^P~x-qE4^3ZpARbC zInopEoBJqXKlzvm9_NCI{5;MP6+ADF@5v4at{NSk4-$-

    PqB{kO?h+`v zTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM}@kgi<>K*MkPhl^V1tI2}Qm0 z!y%6~m)TcV^kj3S>{9?|e(YLs4d5Sy88=cyOao)YL(%MZD4N3#MRVE|%_UGYw?NT60!2Lqislt4>LpOrTcBt@fui{ZiWU$k zT2P>9A%UVk0!0f86fGi9w5UMQVgf~r3luFOP}EnTXi0&henMSQTT%HW0jX_}pO{uF z>bLao%Xeh=FUssID_W)~Dw~F)fsPMF%i5u6kR6H!+o5PVI}|N%hoTkiP_&{QidM2i z(aJVOLj;Oe5hxleP_(K*(P{!k!vu+5-3_*plBU|qLBhc zqXdf96)0LyplE%8q74L!HWVn@NT@4Xs;DfSfYg4;&%0ha6djcBJleP@v#+dZ^P*T| z^H8*f<3rJwb|~7)4nrt~$J(LjIGdv51&U4(C^}J~=p=!n$pS?u3lyCqP;{z5(P;uj zrwbIFAy9OtK+#zOMP~~Xog+|mu0YXw0!8Nw6kQ-tbfG}eMFK?^3w1>Y7nM5_kXoPo zyz4_k(fe7^B}JKiWkpvM#p_##qAMLAimtLl(baY+y2cJg*V>`zIy)3yZ-=5A>`-*0 z9g1$UDY{vp=oW#ZTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i z1&SULD0*0+=n;XUM+J%=6DWFIplFIvS9DoX`6B_Tt(xIn9*TbNoW>JHnSEtN&lJU6 zqeIcNjt@o8*`erpI~2WOhoTqlQ1p@=ie9!u(JOW+desg^uh|q$6)1XLpy&;OqBjMK z-V!K!TcGG2fueT>iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzpy&&MqAvxC zz7i<D4K4Eq95&0^phQm zezrr=FLo%JVTYn$?NIca9g1e!6#Xtx^oKyvp8`dH2^9S;Q1p*L(Z2#k4ejD)J4KBG zMNI-l6@j8=fucg7sGUGjDNs}uC~6TXYA;aKDp1rxps1rjQJYX#^lec&IsvIQW<}qH zqF3`**R^(K_LUWNX;)l5E);cjd?@N>hobIwDC%K{qS@_GG>09E=Cni6Ty`j$+YUwZ z*c9~?D4JKGsFy%dZ-Juu1d8StC|W?EXhDIZg#?QF2oxN_D zKv7?Tq9p~2`Uw>E7bqGaP_&d#SJb&(<@p4pR_&GG%+{`cOMk`unEul3%IqsE8q}`% zZii4b*zuugIXe_BZ-=54>`=6#9g0@6L($51C>mmiqE+lrG}NYORe_?_1d4_U6b%I6s;vtw6;LeIs!!_1&T%q6s;>zw4OlG`T|882o!B7P_&Ui(Z&Kr zn+OzbD%2GXY*(3W$E4`R{D;`Gp(y`@^TlTE%IqsE+Nxc#)Xt%3YsZJ8ZR}9AtsRO+ z+o5QT9g4QIL(y0}6pgb((e`#I+QFu1M}eZ91d4VRDB4A!Xjg%v-2{qu7bx08plDBl zqP+x)#tRfp5Ga}`P_(x|(LMr2`wA58Cs4G%K+ypLMF$EL9VAe6uuxaDMZ3zT2}teA zT7t7>DC(J?vUW(jGW*Jk4sTcNziTKu!ttT#NIMiAWrw1p?ND@#9g2>%L(y?|C_3H_ zMJL#y=tP^MlLU$;3lyC!P;`nw(WwGOrwJ6DE>LuaK+%~3MP~^Voh?vwjzH150!8Nu z6rC?nbb&z8g#twv2^3u{P;`kv(WL@KmkD)6liF1-N+Dc;y&Z~futU*}b||{Z4n;THq39Mn6y0i5bellY?E*!2 z2o&8ZP;{3-(cJUezu2K@h8>E2wL{Twb|{)@ zhoax@Q1pi#ivF}I`b(hbZ-JtJ1d9F@C~7FZvL zmf2TU)V(ZD-8&TZaC|75-3~=_*r8}nI~2`jhoZUdP&AJnihA0iXkI%M^|C4IEl@O{ zK+*gHMGFWNEhtd5kU&u%fue;4iWU(lT2!EDF@d7R1&WpsDC#Rvw4^{$KY^nD0!0G^ zik1>6T3VoJ8G)jKLS0eUvT|1fQad`|MbxdV-_n0K|B1G2S!Q2Z(eh>S=Dwk51;>Y? z741;8k{yaxwnNbnI~1*AhoYf&C|cDHMXTANXqZjWaDk%L1&T%p6s;jpw5CAOS^`CD z3lyy*P&87YXp}(Fx&lS(2^6g_P_%(S(S`y=8wnI`EKszGK+&cGMVko}Z7xu>g-};C zxUBq@fYb)(&qd3HqVf4j*jtum_LUWFTNd*i5Q;`SJ`|0yL(z72C>m>rqH%U8+TIRD zJJ_LUM>`blWQU@iZHjggDB4w^Xg7hP-35yF5GdMHplC0FqVWPn69kGT3KZ=vP_&Og z(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3Eh(OVy0!5RAx}vSi%FqO)c0zs}ZJSVZP_Hx& zE6eOFD>|wywmT>k9qsr~bc`K}jwAl%j_#Fx~?p)JtP!e@Ay!3 zgB^-)v_sKNb||{p4n?=vq3BjS6y0WrqTB6IbcapRodQL72^8HeP;`$#(Y*pi_X!l; zFHrP=K+%H&MGpxSJuFc4h(OV!0!5Dr6g@6bG)18334x*~1&W>$D0*6;=ox{cXN9_= zYs$)t2}tdc{OtW}L(vEM{-Wo~GW*JkUMh%aC>oHz zA8mSBW?xy+FJ-aJ5us>?<3rJ}b}0JI4n;HVQ1rVUivF-e(VuoG`pXVQf7_wxADg0o z1&SJ~akHJGMuDOxfuf2)QL{i%AyCv#pr{lmstOdf2o$v!C`$i`ef|0U6m<|N>L^gu zCQwupDC#6o)LEctHi4op0!3Ygx}u-T%H|13ZH@dFJp3GrZqACjRm{#qxI&EmtkGudHaLYVqhXp=f2thoT{NC|bo1MMLdS zw5lD7Rk1UDCs4G$ zK+y&QMH>nfZ6r{%u|Ux#0!5n&6m2F@w7Edh76L_E3KVT6P_(sBSF}R4@LuYP**g%T3I{+sqHgof-@!*{go9RSuL}#tmxQkvCfI1 z=s3rRqT}sQbb=jijY=@$g?ND@z9g0r1L(yqAMW+iCogq+kra;kI0!3#F z6rCebbgn?rc>+b}3lv=-P;{X{(M1A97Yh_!B2aXxK+$CaMVAW{T_I3(r9jbD0!3E~ z6kQ|K6&+ozj88ynz4P7G$AqHB{8wUKTP?G%tmwvSar)#?bd%#l(am-!y2TDfx7wlT zHaisEZik{f>`-*49g6OLyUs zU7)CkP**ggT3Iatsg3NF;QShjHp~x)%-&LFUs=)IEycJqL(x2r4@EugP&BU{ih9|h zsJ9)8=Cec5{B|f>zz#(V+M#G6o1#7fMGFfQEh12~s6f$T0!51p6fGf8)K{QrNr9q% z0!94=iUtT2EhSL2v_R1^0!0G_ik1~98YECOSfFS*fuiLFidGQniso#o9G`&Hy63-c zf3BALE&bK<_oJ=YQf6OS(JC#)^=F5op^gtltJfuhX> ziZ&N0+CrdcOM#-T1d6s6DB4D#Xj_4z(L!C($}N?b6Oh_H`46!np=k5;YsHwBGW*Jk zwr?qZJU0~W;P_CqqaBKNvP03%b|~7#4n@1#p=dWd6zy(@qCM5-2)Ypy&{RqC*9WCJ7WBCQx*^K+zEb zMMnx09VJk7v`|+xwx!bjyrk%{e6ws^D7rHLiFQm&nSEtNC$tpHUJ!~-bbKf}$qq%6 z?ND^G9g0q|L(!>rC_2p!MW@@L=nOj)ooQ2amO#l|a$e0!7yd6kRJ&be%xa^+H|IaV?cC z6Oh`l{LMqhhobNEpJ+Fy~;+w4$uyB&(|utU+Eb||{b4n=p{ zq39kv6y0lwqWf%$?iVO}K%nSBfue^5iXIjydPJb;QGuez1d1LPD4HTr^n^gslLAFg z2^2joQ1pyI(X#?Y&j}PgFHrP?K+%f=MK1{yy)4uf-PBUKECH$Y%+I^NITWp)pBeH> zOPPITMX$FMk6#js-f(;a=yEIYAAXwf06WSOPPITMSrvuEtiL)KOG;6 z{<1^S-*zba#|}mR+M%eSecW;nMU8eSYO+I7#STTyHbsR%Q9FU6QlO|RP}Cw&)Lx*d zRiLPYKv745qBen|nm|z}fuha=MY9PMbrC4)Dp1r-ps2e*Q4fKl*#(N`5Ga~cs4JS; zQt6w3)NaamH2xlny5zrxX0G;S_LUXQ+rAieWhm<9_)yf_4n_0Xp=f?P6fIzfq6O_x zw2&Q&`q-gpVLKEpVpFuJK+$3XMT-j*Eg?|USDm~uqSftCG{O!=YuKS^O*<5=Wrw1*?NGFi9g0TU6pa!n zT34WGJ%OV21&THhDB4h2*r8}oI~46@hobRzD4JkXG*O^vZ-JtH1d8?*DB4e;Xn%pC z0|bf=6ev1Kpy*(MqC*6V4izYxBv5piK+)j>MMnq}9Vt+Blt9tZ0!7CN6dfy2bevFE zv_tz!!*xl~ruh+&9YfLF`FlW)Z(n9#S<&S7MeiFz(aDYvMW@)I=u|rtoo0uk)9p}n zh8>E|v_sKZb|^aA4n^nK6rC$jbe=%b`2s~32ozl?P;`+%(ZvEqmk1PHDo}KpK+)v_ zMOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?}S9D_g%J2lFR?W}5J}DF} zn7>H6xqX>^Wkt8QFLt;o6y4$YP;{pqite&Q(cN|^y2lPh_u8T8K06fMZ-=4>>`?Te zP0>RFMGp%UJt9!_s6f$U0!5Dt6ipE*dP1P+Nr9rL1d5&(D0)Vq=vjfH=LCwL7bto` zpy)+`qL&1UUKS{NMWE-m^o|`*tY$zz#(p+M(zpI~09vhoVnxiar%6`b?ncbAh5S1d6^C zDEdmE=xc$ZX#z#x2o!xQQ1qQZ(f0yHKL`{}7byBspy(%oqMrqdei0~|AyD+IK+$gk zMKguEqBq)CUQIx1Pvmd=crz3YD%1GAeVKh_MSr(1e!eXf{p0vh^sgO?8d~F)dnjtO zLs63*iYj&}YPLgBVTYo2b|@-simC!dEdoXD1&Ue)iaH1sbrdLS6DX<)6m=3P>MT$+ zn?O+)fugPgMco97x(gKb5Ga~mplA+(qB#YM<`O8HTcBtjp|0r9_LbRhPl~?HfAh>= zq3DTx=TXnrGW*Jk=4&km-x-SLcYG*Xzz#(V+M#G6I~4V?L(#%^C|bl0MT^>@XfZn! zEpAh^gg{YWfubb^iuwr@^%p1_AW*cFK+)0yMau{j4HPI^R-kB*K+#}>l1&THkDB4`0XbXX&Ed`3U5-8eQplBO`qHP6=Mhg^;5h&VDplGZ>(Kvyk z?FEW<5bBDCwN|c3Kx%vBM`MSFqI>60W5?Dq`^t)TZ7rU-Hx%vW_)xUF9g6m_L(!gg zDB8;oMdR&IG{Fu<6YWs6w;hW1u_@YDplCmVqWuMm4iG3hP@w1_fue&2iVhJdI#i%& zl0ea60!4=l6dfT@bfiGhQ36Fr3ltqAP;{(7(QyJr#|splAW(FoP*=2bYh_vjQk$H= z!+Muc^lJLG;-uCx`^t(=Z7o_K2t}tkJ`|m9hoUp=P;{mpiq5h_(b;w=I>!!0=h~s@ zJUbMfZ&P%EK+%N)MHdMaT`W*^i9pe%0!5bz6kRS*bcI0Cl>$Xq2^3u|P;`wz(X|3a z*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>LS50xt(ATWNbQ;Y1@$SR==A(`(QU0|_LUXg z)mp6gP$;_F@uBD*I~3h(hobxJP;|c?iXN~-(Svpp`az&*xx3Ux(qw^klV zKx#YXyQ|*`McsR*@mFh^ePu-r9g6oK3q_3`;+A|UYO+I7#STTyb|@`=6@9f}sQL(!skC|b-8MT^^^XbC$M^|eFMk~T&C1d93#6b%q4 zT1ud3X@R0;1d0X<6fG-IG)SOmut3pr0!7OU6s;gow4y-KN&-bI3lt3zC|X6JXsAHZ zsscr;2^0+z>Wb#?P#KYc)CT9L6fMx9eoMbCKQueMLz#VLMQe5_c6urlt>ySow6-0J z*0Dp;NIMjbvP03jb|_lU4n^zRp=bj;6m4izw2?s3#sWo~2o!B9P_&sq(dGh0TL=_w zDNwYPK+)C$McW7zZ7WbTTA*l*K+$#rMPmhu#t9T{FHp3DK+%o@MLP);?JU$4jp$IB zoPgAp&UX>55sF^Re}Tv@9m?!0E83$&aq}~wXivw7qP^@;G~NzH6YNkl(GEp>+o5P5 zI~46}hob%LP_(~I(E$QQ2MQD&Bv5p)K+z!rMTZI$O%fijEX0I!d7E zXn~?*1d5IoC^}A{=y-vm69kG*6ev1LplGr{(aAzx(QX|oQxlNdF8O)ayN9AJ^PNYh zbSSg0tmupm#f;}d(V319MQ7Qe=xjR_onwchbL~)co*jzLw?okdb||{g4n-H)6kRM( zbcsOGr2<8l2^3u}P;`Yr(Uk&4R|yndEl_lgK+&}VMb`-wT`y2{gFw-Z0!23o6x}RP zbc;aItpY{22^8HfP;`e-S9Ds3%AC(9Mf>LGU7sF`*3S>k-r1qdzOtfwI~2>m7>e$5 zd?>o#4n+^xq3A(76g^~zqKEBJ^oSjb9<@W!V|FNd+@@%XK+zKdMNbM8Jta`|v_R1_ z0!7aX6g?+U^t?dP3j#$i3KYF0Q1r4u(JKN)uL=~sCQvk0py+jhqBjJJ-V`W$OQ7g& zp|0re4wY>akXq;bcg)@siY{rN#ycI#>?`?Tv9g04&L(!*p zDEiC}MW5TD=nFd(eQAfHuWX9G7ATq~Q1p#J(YFFc-w70bFHrP@K+$x8q8|l{eiA79 zS)k|_fub1#MZXFZ{U%T}Q=sT~fucVIivAQR`b(hbZ-JtJgu0^lI#jMoKx$p{y^imP zqGh|J@o$GR`^t(c9gC;Z{n?#|_G>7bJO1xm`h^{e+S#F~v_nzV4n-|?C~9wqqEqMyFgJ7fuh+3isld~np2=?E`g%C z1&ZboDC#LtG_OEWFM*=o0!8x)6wNQx6*YFOe4BvOHqKAAZt7USjrM0&v_Qu)`^t(I z?pSnuJrphC`1oA3s2z$HvqRD1b|_lH4n=+KP_(2Siu&21sJ|VG2G|rWB~Y}qK+!S+ zMFRzjmK7)(Bv3S1plCUPqU8mORuCv!QJ`ogfufZKiiQXjts+n~RG?^8fuhv}iiQak z4Hqa{U7%=$P*=22$I5^Nq_$SRao;Bt9oaRFH9D5rS5~x6$6|vwL(xdbhoVt-C|cJJ zMeEt2Xni{rZD5C@4ee00ksXRQwnNb-Hbt8X6m2F@w7Edh76L_E3KVT6P_(r`(KZ4_ z+X@to7AP7cP_&&u(O7|^aRNo#3l!}jP_&~!(M|$II|~%;B2cueK+$eOUC~+{EBhrN zwWIR$uGbDl?eZ5%yLT+JudHZ%$Ku?#L(v4shoXsgDB9Z&Mf=#HXkR-N?PrIg{q0b6 zfE|hsv_sKBHbn;u6dfW^bf`elB!QyC1d0w9C^|x*=tzO0qXdeM7AQJKpy*hEqT>XL zju$98L7?bFfufTHiY5yboh(pvia^n+0!60@bwzu2tUQ!})OzPnKYN9uzdNRJddD*R z%8JhJSbX?yC_2aSq3B#Y6rE>>qVw%gbb%d;F0@0@MRq8<*bYUP*rDiBo1)7EiY^x@ zxja9f7bvWa?nSZRJQDS9e@E;=g|-PxALJsr#JD=T`SW3k`|q3A)!hoXn< zQ1q}JiXO2;(W7=Kddv<*kK3VWiXDocutU+4HbqYf6g@3a^o&5!vjRoW2^2jqQ1pU8 z(Tf5_F9{UAEKu}{K+&rLMXw1IO%*75U7+XWc2` zSXnaxslC!8!MQ&aotGaDdB0p`az&*xx3Kab%Q1rJz(LVx3{|Xc}w8af`iW-Hwq7OS(PDwy&Yv-poeiVux z@0~_dTbX@jMeW*(TR#a!rQ<_U)ec21b|`9ZhoV+H6m_seQAaxzwb`MlW{09qHbtEU zie?ii>LO6oRiLPwKv8#rq8Ay71@K+#+RMRN-j%_C6MQ=n*GfuddlMZE=z z<`XEIU!Z6KfuaQkiWU;;ikjOhZzLeK{`rY%MO*!r{to%C3hmQYW?xy+Vr|85pM|2u z9UqF8utQN_I}|NxhoXLVDC%#Aq5*a&TFMSZOWUDn8JnVk0!7OT6b%w68Z1z>oIug? z0!1qb6s;&ww30y4$^u101d3J>C>knIw5mYSY63;W1d4_W6s;~$G(wWUU=tIYj*QuJJY=xotYG$KD7vUXdUePu=KwiPRW8H(0(d?;Gq4n-T-p=d)p6m4XO zqK)lPw22*xHnl_1W_Bpr+@@#?fub!1inbCc+FGD!8-b#21&T%s6paxm+D@QotU%E? zfuijNigpkv+EJirCxN1!1&VeNDB4w^Xg7hP-35yF5GdMHs4E)TRvD9k)LzL?ZyXhh z7R`@0!1eX6rCtgbdo^PWPzfS z1&U4)C^}W3=rn<%(*=so5GXoRs4JS#R=Fktsm+)F5Sti^8ZxP~+RE%JD>|>Oc;=f> zbiU(5(FJxWy3h_q7ulicVmlOFVuzwj?ND@?9f~fuL(vsBMOO+GT_sR-wLsA|0!7yf z6kR7!biF{)4FW|s3KZQWP;|3E(JcZ+w+a;9CQx*{K+zonMRy7m-6c?Tw?NT70!8-< z6x}D(6`j*o`91-uJ)NI-eQqdPttpNB+sf=KD|)!CsC^%b9&vmqdeja@kJ+KU4f$a1d84lDEdI4=tH5d=)tzi(g{fI*8IHd zheFZjl{7wTE3>bx=(DzBqv@gObH|6GFYHkCr5%dCvP03=b|{)=hoW!nQ1q=GioUZ$ z(f2k*KL`{}7byBspy(%oqMrqdei0~|AyD+IK+$gkMKcA8eitbEL!jtSfug?zivAWT z`bVJXUxA|Z*HWLKKCaD;6g3JIH3<||1d5u4x}s0oDhDJWwKMbcu0IV$o93si6}2+^ z%8FWQ#rZ#lqV|ptMXh!y>R^YWj&>+&vqMqM4n>{pP}JEDMYGwVsEbWeSAn8#0!7^g zih2kX%`Q+hhd|Ms0!4EP6wNJAG><@0Pl2L&1&VqJ6!jJ;nopo;eu1I|1d0|EC|XFM zsEI6s;vtw6;LeIs!!_g}S1}Yn660 zlANXosSM>`-*D9f}UIL(!pjD4Jx4qQmS^bhu5?5duX=3KShB zP;|6F(J=x=#|ji3Cs1^}K+y>TMJEarog`2+S)k}-fud6cicS?MI!&PHbb+EX1d7fS zC^}1^=xl+abA-C0eQK4{5|G-y`46#uL(zcz{b=Xb%IqsEy0BK<{%0t<$nl}*VmlOF zVuzwj?ND@?9f~fuL(vs>D7w-PMOWFO=xUpyYXpj}6)3t+py+ymq8kK?ZWJiGNucOv zfudUkif$Dsx=o`koNioUT!(YJOe`pynT-`k<+2Rjr^w?om7Hbp-P z6#Xnv^ou~z41uCw1&V$XD4Hoy^t(XO9|A>x3Kab%Q1rJz(LVx3{|Xc}bc&np6g3JI zH3<||1d5skiVA_Eb^=AEP*?PMtui(Nsa-f{g7ZZv`XK-DR_#<~Us+LyPQ_78p{S$d zLs6R@ifVQ!>STwa&UPr8%??Ff>`>Iz4n^JUP}JR~sE0t&>;gq|2o%jJP&Ai7(cA(> z^9U666eyZkps1HXQE!2w`2>pQ7bsdlplCsXqJ;#C`Un&)EKszFK+&QCMT-d(EiTj* zweM89E&-`6lD`yc?Nq;|e@T95c8N}9_LUX&?^Hb39Et`wJ`^owhoYtJP_&F4iU!)D zXjwZH4YEVgU^^5oXNRKYZHiV9C|XgVXeEK7l?9512o$X%P&8DaXjOrt)dY%$2^0+% zC|X^hXoNt~8UjUY3KXp+P_(u{(K-S}BL#{^2^6g>P_&*Y;{}Q)2oy~eDB4?~Xdj`jXv0pGfeA=$r~HiBjY83bv!$_br!xD>iVo~lY|;{n z4sv`bI@k_HhuER$P&*V&vP02fb|^aB4n;@Uq3B3E6dh$#bhJRxF#<)$3KShDP;|UN z(Fp=YCkhmuBv3S2py*_QqEiHlP8BFRO`zy>fub`6ip~@$I!mDFY=NS41d7fTC^}D| z=zO8BX#Y-?gA$P1(Y+F!147Xb`Oc#YI+fX1R&+_H;=0!0rC6g?u;6l{=8^vn!h3B(N1Odl@&eFsra;GD0YdR3t4HG!h30!6P26ulu(^rk@3TLMLI3lzO0Q1q@q(R%_#?+X-t zAW-z7K+#76MIQ?keIiiwsX)=Q1p%CL(#W(DEiJ0Mc><@=m$F#O}9hQk9H{f$qq$7+o9+eo1z&4MZXFZ{U%T} zQ=sT~fucVIivAQR`b(hbZ-JtJ1d9F@C~D{&H`^&{6ewyED5?k)H479K0!8fvib{c^ zsz6bTKv8?4uIQ^ym5~WZZN_{F&ex%6Wd44%*3M=2l@--G7kkVWiaI$y6m_;k(QI}o z>SBkYu68KuW{0Bgb|~s$hoaf-P&9{4(VPNBa|sm9El@O%Kv7SDqIm_1dI=Qu7ATre zplE)9q6Gws78EF2NT8^XK+(biMT-a&Ehe#t*Mgmg1 zx=3)^I@fRM56t&E_Ul|`Us=)8or^oWhN5L0ABqOrp=en<6b-UN(O^3iEoXz=8g|VTiBs!OFI;8Wrw1z?NGFh9g4QKL(ynE6pgV%(RMaPV+D%F2^4KF zP_%=nh{unRUs zMC{-5&OG;KgZ|I=UDtQcb#l2r^SgJ-yYJjnw@?SbqIv)pEdXHALI4(>2Ed|404!Pz z@GKga;7dssiyky**W=ZqnVlspN$?xLj73WmoKPFJXc^P1Ma#)*(F(F!bQW1HT1i%m zR*}`B)nv8kY_eLkhO8E?C1cS!04zEefJNs4u;_dM7F__qqICc)S`WaY4FD|K2*9EX z0a$bq0E;dLV9_N2EV>kcMVkOvbQu7PE(c)I6#y){5`aaU0a&yJfJIjUJd4gq@J$s# zTG-~UGk20a)}H0E-?6V9^r*EP4`vMcV;b^b`P#o(5pi4uEITH3`1kMUWN)nu$2q zszob}Qacm;#xG;h^9jx?9n_*1m|iVGwa{v~70l=a!0a)}E0E@l`V9_@K&!T4&dAmV(d7S)=!Lz=hp8^4T2 zty(z~x~N5oOs^IN$!bv&SuHx6tQIAc)uPs9wWtkQEow_vi`tRZqV{Ag>Hxr^jsPs` z1i+#c02XxyU{MzU7Ig(+Q8xe<9Rt9kV*yyy9e_nW09bS!0E>ZE0OaK02a*wU{MVK zi{=8bXdVEI<^!;(7Jx-{04%BpV9^2q7A*u|(P;oIS_HtN#Q-c?0>Glv0a$bfz_Vy# zD__&@V$sFsgJ~zJMbDdWHJ;hZZ~QVAt!U-+JWee-i|N&(m1MPO6O;(G}CaXnj z$ZFAAvRZTwSuHx3tQMU|#-j59SabmZi`D_KXgvUnHUO|_BLIso1Yprc04%x~fJK)8 zu;@|%7HtAx(PaQEx*UK-R{*f+N&psZ24K+^02W;Zz@n=GShN*@Mb`j4iD`@^L$h6=;$5>YX zV0I778XP?Dc*`0V+||pnMh27nSXNf>lyu9=4PMvJvI>HG2Uu1~u+L!2Di1CgYFXoh zj}Eh}lY{mM%bFA%6|$@;!3#1iYkKg_Y|EM*Y?EtQ^Mc{gmQ^3Tp}?{h1-~t_tTTe? zV=QZV@U$|^S`~b}!m`!|ed8_b{9xWh%i0iJf3js=9DM6k%epMsuF|qL2P>;AYisbP zYRkGl`294?x;fZyre)n8Ts+&dwgsQ8v8?-o&V0*yD41VoS&s!bF0ica!FNuxtewFQ zODya8VAUCx^>Xl*rIz)2@WnjFM@^VTh=$h zi`H4zcft2ISl0evr;9A>V6gfU%Q_sqZIfmFne@};(*JhSpv~r+tx0EIC2PP=+Obtu zft}RkI#~yHQt=J466~Z)Zj!ZNCw*{>tOh%&^X;-8>?HHA*>|&(%s)ro!%i~)o^&re z$^3)BX?BwN7hU_?N#>vA9Be0?HHgQsvr7=HC@6u#?O` z3{zq!nSa@%+)gt8G{bm1$^5qd$##;lofzWw& zlKF+ldOOMdMBgGiY1STDJ$91$k*wu*lKGXRRd$m3nVPkBlKGvH^X(+_LlGP7B=b%G zi|r)yRqe~{B=cR{&32OcvgB4f$$Z=GdOOK{UFl{!$$a1Bc00*@VPKn`WIpkIpPghr zvip#oWIl8Gn4M%kG`HPOGM{?dX(ySFtvqihna>@(Y$usFj$gNv%sYR(?IiQo&AWDz zx%d8|on&sF?y-~1-LEg~By;=X8#~Ede|~2tnG1;hc9J;*JZLAGL-=7k$?Svww5_J? z6J*1>-rMAk9^OS(X21AEzpPaG3&;t8y?JUM+e&^~E_Lkz&DR^89BM9MpoUx%25GoX zHZ^;2a}i2LE0S5;L-d*V$Rc{a1aGz<;i5g-}V@7B= zPc~+Iq!(H@m4%r`wvlbXs*{0bskYVDE{RKcV$EGIEwS3vE8hhF?21qKpKi60ZNMG> zF8E(t&wh82)n={oXFcvTJN>~MM_O$z7Q9?$|BZ)Z7Rf@!_%@y#*VZoeooU5cZC=y~ z|6#%xntqjGwGrvuUO8F@G%5S%QDD4up+y>0> zcuf7j8gN*rT)~tdZD0H8Qmc)q=COJsw+U~me4EFeW*1c7HP~unZpxdEd=5P0 z%%R6xZA2&Q0>OJd{2$97s}tHXmb(VtxZ|enXIgDeRo>d;PP1?OYzkU!rYr6P?z{Al zldLwiibpY*egAy=*b=MVQsGy4?BC0_+D{R8%p>mgn7H;I$brE;;*Rk(ZU2qz>CGd~ z=ZkCqz6_X0T#SU9#9s4=i}l4>c7lCO^Tc>x^LEWEk`wHf$(9w<&5DmdQIKW%j<$Tw zhsK`}KO{acQFeFwjJbI@z%nE**7h|&F+N_N_C~V>`g_P!?dA9sa0eXAYT^z^JDchZ z9dCy5iFSN^!-UO_vU~v+7axCAe6#q$GMl548;#Xm#)@iG3ynI$y>R5>~k<-wQ;8F78%#xGb0eJyO_qIp0VX58QQ+u-jvbCEF`&qREx|D zZ+*^La-_G@<+(O8D4m?1Xhv*%uJD-F8#82EZpRaHaOiD~Xfv!$O>=h%(k4;5y*y;| zmp}P9jsBUPQ}kbSzE4K;S#QV~G4>zQMYjCOxbm=j_wG|$*=K6qygqfcRefs1byd~j zd9`!vtE=j(r}U|+T|BRTt^rlmQx?=#*F`;N#+R{&^qE&XW6q5F84IheKGWyUsqRxb zyLwTd-m~XcRnG2HH@&j9x=(F&O?6#mU7zZ{;kx<-Q)bNVQ$Kg^?5gRNGivJkOslF2 zSJuwylb#mt7w((ZH$9x5W?-to)S9_9)v48$lV_x+r}gfaYM$;bPd9q1&y1R?*$bvr z_nA{!HGM|S|Mh0nEv}31iD}dOgleZOm{Bt~b8c;QYNRg~)z`XR;`K;L?cABt=XHI` z=2h0t%2`koE|=Fbtz`Csx^QV|VBr8(lf2mfgLD7?Bf-MT`f9T-EK4;SoZh?2NEV(_ zJ+*Sd?D}y1;(66|y{8*@MT99cYU(BUMYWuMD=Zro&Zx-Ak@=V9 zP0Wr=@~>BxS7>_E9mn)!Mp|@3^NPY1EO>}EEQQki;yjIHxQe%JOD2z#ZGPEGO!PXP4*F zzu}VH31L~+g|e12L*;qJMP5G*iA6mbaIF^-H<}HlA^k!*h=B~DIL0(aQ zq}Rsf<>ZA!C2lJ-i;Ie~GmR~-c{%+}hq;4Uszg~uW~NvgnHpusRAg6VhjXN-B2Sfs zO7qGmM52+pFjO=_S6#y_+|^cAT;{eQORSDGV1T=PUWJaAlP=pwxU4uQC){Y{^dXJL z&I}cW%S%H=Wrca=?wm`rLs=8t7n9LQ*wV6)%*b8U(!nY=%PcO-440J`OP^+oj=B!L zzG*a*sO>58g4Lc-fxF~zaY=Sj_vG)+f`Y`yzA8%PY+Zg|jm=!|54$x|wG-+7#VgOIBWJRJgdJ zyriN$Jhr%?T(+OcEZ7>%PQ~ng%&seH>&(g?n~RN@QoItGGmVC(-*;_a&8y36Y&- z-$;jLM0Ji?K@E%ce2;osR)lm(ID33%c6L@&leI%+4_h9RJw$%?gm6wM&urzaLmk5$ z{H1Bd6{RvD+gMIPUS`8y-?h~2%pzTv-Z!#=%ckyafU^BfSukhL;>f(+%^|xu?}*JN zY!+5lJ$q{A^y;cv>17Kh%YTuHWba&9Tx!;m*?oF*?(1$hv**@KOObt<%lfm_bQ$2q zNY|DXHypjp(IE1i?v6{d3$oo^w&}y{#(H@InAXWU&dc%o%4@;EsHM2OBeTxTj?X>F zX)7D)#J(UL%FL`N4Q1+{Ez+J`IsA*)j;v5K7-^>ZAxg-mU!g}q zX=cL+ve1mukR0jNEVD#eJJDN~bQOEyg5omWwg*QRD67Hi!3+kn-4$LpV_Hr1loYva zsf{eoXkMHnvlB@g_S_A7hRn?3aIWmJA`{Rzg~eH3>*Zu1@?>UqK|w`9s8rk^l~*R3 znH}S+Xl=IQqH1M-Eg`YdL*zBjZ(-T$xkUxmOl1OIGd?PUM-r z;t~6!=yMC%6}X$Q+dYvjBYi-l8L|1WwxSO6jl}uSgIt3*1zE-J{xxz;(RJ*t64}Y< zs!UJUW0xGuBOS=Lo)*p;Qy$LB^$zEakNpFq#@GE+q3nq&O5LNByNk?`4k^ox+BxHH zL1=vdIWc4oHh6Cx|GVGm)N8r|c#engM6_M^^;3uIepSpT$QRH(2p6lsO& zA35csTV#uMyQ*QUPEU937*$k}k~w5Zin*Q8J3YnRP)Hlxw|`2H+UnWWm37s}rKHZO znzvwh)!f?p>P4w@`t=h~KYhWR$x^4zo?BU;Dt9A>%RXR=0W#*)c?$=m*3CY8cw(}$-C^0u*5V~V7y3u>zBXUwfht&=+gQtO0GsjRPzWcMWwYUH20?!AMHIgNK$ zWOh+;h3tY{ZyTR*M~+Z(&KAnZE6AJJaMGM6yInI$zeYRHhArJ}E)nG#%$1{y>;uZ> zeA67fBO|cZ+zX?Il_}d)rko07gyd>TccNyQa-#1wcTj`ra)|d>(b%Iv_VX{VkL^WfYJ9*A$rrvcH!jsM#O6edFy@-BSp& zw$ju3YP%ylTj}t~Y#MsWoVJCvtGp@XsOS#J>hyr@siHO)cfB@To*i-4t^2yhhlc(# zr|Ph|w^ChO>&;WH*8Zb0-i}$eT+=G=Tr^#-I^9VcU#ptqO2bK)T%qdrX0Ev1ZkGW? z=91V&a?@73Pq}2{_2wooDymnaCNL+HvP*I$a7S&p z=8Igc4%E4LmuW23+eK#=mPB29WtzJI(FX+6?&wR$+;MWlAv0h0j@~P3w2>gYIS+~S zH!%9T_BcjugvXZ>8UOt=k!R1~kGB?@FGh=gVqsx%9Rvk*0lln;eqI#gD zv^Y0UE&yd!6v?qnZYZ!wR}s??qe-5ec1{!-!eP15+i-g$UCx_j0q&(j2is{OOsxRw3-v&Xz5*pGu^JD4W?~J z9GF98=Dt|umWpgck(ov=$U+(J9kR$1Q5{*DUH+eE$nKtyD`(RZ@9N5Jlboc;YoJYX z*(eubd6{|c;iV)bM;CW2IYxK`vVArh-MeX+nJbsG*#+(>ay1*7U1WR785gdQyH?Vf zIzyeG+_RzwWyhg|=E_T3*)S)$MlUn_#Rf0UDF1mn%F1nYAFk1vapX*!YfJA^h+fbx zZMw2AzgO) zR^4f~)~%W=>qJneI;2G|^m%F-r7hgWOWh z%aomy94yM+eu|7$CfB=ie?ad6&~H(1qW$lB>nN*w@`7n@kD9AG8fmuiP=+V1ciWj~ zc!fD~u_o8G;hcg{S;KTZTTx;*8FRycJL*SVQ$^NIW=>|qdPz4owpo(i2JsHQ?uz#A z%A3LHo7?V1-w`{chEvh3?Em3p)U4nM+1>>(SALCmDn?$eSvc!++hOihy93_+_rlQl zaAr}t9;KphKf6u)_c7PIM&orxZqvE5Y`Bk|E_cHMqKIX-G8$qMJTI9;!%rVl9 z(Y{44jkRyxTg>iaIW#mJ6utY!=1Frs=#FG=p3-XfC@$+>yv>x&?7!d5@NNz_9OC}9 z|4QddBHi3*W!}+E&dDo~Grj1W1`X#rWo4QAwoapdKwe~&o1=OPGS@rjcS~RI(A%g< zG$6A7k91hnj>}v>G9rucM2{Si-QJ46De8*wUk7w=_a3=j#(dp3YuM_6X0?`9czZCj zBZup5U)E{k`>s(JNOGgbU4?QA@NcDf5wg3J!<=3e=$kNHSq*A5AydeiuGpO==QvR( zKRg+EtB8ZJch%zQCe3%RymUK?dNt82ztMXu`Z6nu@{5YcdA-1ek-0f<=IdQ`&@UNs zD_Y)YbKeAUpEg%LJQ;QR(dd4Q+q`r=$e3#)7npmT?tph6)(mnLlpcM1Q|D^#u;<7o z5q*29@zn`uL+(tab0h6?w<|dom4`~r>7%$Wrz-!`_7!y#R$H9z-9a_8^{%&gy>e?` z&vx815$^80%a7XWs;J)SQRGIXY^9vzs7SnNm+sv^b!TI4SGohHQ-+F|k?^o#3>><=O!voNdCWv4jII*Y8mXwe#Wqvl3*^xH%<*L&G+w@H_}{nz+P zpkWsBPA2D9w3%zMvWhZ!b4ss;|8*iZ3nr1DDP`{w@lKk=+tnPC~t)8dt0V? z<{~C?ZN>7<(c3*N{nvG@amUEVwV9bqj=sipxvLfFRrUd#`|oHJoTQx@s}Amkpsp zUKVXLv+*tt+#z-m`h`39JPPWEzOse-=y^RaW)i=A+Bc?Preas=z z>z{_ZobLU@f4{L8S>utd-@W!5RcfxZkLdD7SDVH$ciS)*FSLQ?W`;7Q_jAJTVcs%L z;`0hz&luZuJB_}0@f3oAu|-Y(4CH8fr5?KW7VyFVy9@*PZ`)!w98kuxIiqQhOo z=H?=!yT_fPP{YR$%=$dC6H3C7HwH}~b3|#FhquPY6_@7g>1O1NAYINRj{Ail_n3(>Vk4I)SZ@T_Mss%L8bWwqGijs9xP{YYGH4=P$;tE68wctd`$zbVuN;)o$PCEx3SyW?dBhH!8Z-TivGUk)_eQ`~StvJO2Oi zj%4HGQgmv3%<3y2c9ym@Z6#l$FjZdYJgxE_6F0BYy1`WWDaB_szpC|Jt)FTA!BiRV zpyofd#>x6M^Eba)WommxWuD*Sb&ZPg)Oam7S~GPjRwMyZxv&sI{HeE?SS%nx=J- z))Td6Yc0@Prgfs$O0Cni&egh5>zP_tX+2Ntg<3Dyx>f52w8qHp+w@Nptu3`CYwf7@7_Ggu_R~64Ye;LZ)?%$=wVtANiq=_L zYqc)cx?JlTt?RU2qII*@>$Kjg^=_>XX?;@bvsz!#x?Af9T0hgeSL=SQziRzkt0RXk z(@)K`CTeY~wX@b9TKi}nsCBs3EUo!kOSMkWI!Ws^tuv&Y_(^_B9`nuM4w0^AhORe8&{aNepT5b6lyqRx6YYVMMYwe)5o7PmV z1GSFOnyYn;)`?oHw9eMLKyeOBvhTHn?Bsn&g3f7be^ zR!0t4=Jht$nyfWN>v3B9YCS<~mexY8W3`60PS-kL>k_RiwVto_60KKhy-Djftq*H` zTI)+%cWeDf>sMNT)OuK}E#ECPudk`rpw_Nh)8$xgo*%BYOpeVahqW${VUt&A-6W@F zCSRxZVL8B?{EXHQX~@fAt(Rqb`39{Y zXM6cut=)3HoUV1|XfL0pbz6a#AJ=-Q$jiQBuMQjI)jX|dm3eu+*5~Df%e=0)v^F2_ z<#t-jCwjS3>lG(^`6jJpj(8ep2hdiH8BU!?WrHC}#CYpZj;+)3;B^SxZH^{RDVzD?^Fa)N7? z|C83^FY@vrt@AGN@|jv6*yQCMTK~M<%T2EEYQ|=-7HeI5m6tEk`s!9Mf1ovZotHan zop^(nr)k}Klb7$%`qeF7{#k3U+r2zQYwew0UZ(Y-ZC-vx>)-cyIsRU+X5H`AF$Tgxe3#a5p7!!DT6;g^TWHPw+RGJM*X{N4m0EXy>*Y_iw*A4&-L+2I z@8vmKZ#>}Td$oQi7oeuSziI9JtCvS;UG$rmS8IJjF0jn_FKLba+sg@BN6Q@m^ZYoi z8|3T$CU4RDwtVm3jwT4ZVt3yv-1sunwbq)ZHCO9Qt!HVy zLhIdHpVzuiYm9uq-OR6z)-U4(WgT(b#Z}Z7rtM}x( zI;*#Q*0{HUy}esXjc-r6&rUI)*pU0>Q|HQr?r`Pg$+guBy=j%ynvc-y>^$^uGTVG1 zT4y2cv3i^D*;dQ9R-zU&wYGAOj1(#@>|I%3Upr&+f_jAnZI80Xd;i1@-Tlb!?ty^ zRI?7vIObuNS0oSGAcNL0Y52|J1%C{U77#tZhh%;!3EuonA22^Tuc`KummTfcPm zhRy%YbLL^zQS^8dPqr=7_xv%QoLac!!LOI`vItUX>fJIN-9Br6L;uO@i?r`)85T$9 zNpb(ak@*cJNHxnff2QKL$=yz|<%e^;d#TLN^t)Lm&YSTrmY@GHea|2BGt)$m*HYRi zrx}qy#^dYteS6RClOliVgVF{LPU}0k?+_VIOG}UX|GZNWm&MIo>whLw+iywUxT}aPg}JyAMB>p18l0Z{&V^W$uBPl+w;Gj^25A zm9_J5AbscI*o2*jcc$z<9Ghlznq0aX5u8$T!R`9^+XJou*4u3aK9+TuTQXVbkkycjI#`$x1p!1#iW2R25X(huM z2LkaU4^=fCd1zH&nj9J@VKtk9qPak%uLZmhwm$owGTAbKVxW-B#C8hwM=C!R;|S<=M|FcOHH{ z{qq@#`y^h4K4RW+@prNsv~lzm>= zb@~Kr$Ir`af8T9)?K;UkUsco2eb%bXJ&>7sR_@Btlct(w?L53krtLcYYFl3Aq1fiq zhLbW6ZEc!)z{x$mc<15v+hnY*@>nj9J@S~Bd0_RZ1%;m+ZuzvNl6qPCciZb^y?j?v zmsgi-#xOl?pSW&U{(-F{rH}HZe`bz6l+k45p=Sg62bLEV?~iRJ<1yzAGR)k!%di!b z(z1K;!Gtlz2m6&}99W%USbotd1>`mDU_XAigE(Bzk0GG_Y?!j{Wpk37sA zx65OsJS=&X$Rq8rpS!b}*_30Kw=9{^H6YWA zO)a}lN}PVV*d!*EXB4Q! zDEGpGG4ks6$ar0+Z}G+(yFP#Y=nZ)ra=)tdw(s@%Yi0ZXuWftefzrNf^H&sjTXk&b zXa3bkz8ot>`X}Ap6EqsOBizYZl)rfN;=CndvNcB6+=7flU4094Pa8cWPqxew*`6$K zyNRE^x#5*|otIlV`sK=}H&yzjq$=h@D@}w2R z+*XY2+F1;IEd8PxAH@E-dvMO<-yB}=?Ri3lq5O=zjM167)l<#9ul=&BrjzWEM&^#p zpEPyk=ulqBZTF?ZI|v_WI-J^G3S-+%Jpw+sWP>hvyF;ePZ5;E+5%7R<;_m z#1CbOLyLEQ{gHTW{9i6!o*tZkxO2s_g^Q0`zTt;AHXMiz#9NMR5BIx0JQzzRp6pMTYrw;!9h^o(Hk;a$PouiE>{_Tn9n1@;ZwarVSbQ@_7$ zUu?6Z>_yxD*&KNDt#__#w(5?uK07CrOgujOf}HJ7+>_?a`(&hb&MJ4iFh4lhv*q~E z?5|$BD)d+C^l=^9Z%DB&X#IGvQ%9e0|X6vfzqdO0tMiE%b2nc{EJSq}bZ%l~2uTNla%F|p3s zax&?=tCb8Fx0&Q3{~v861)OIL4EU=g#l|}3ivlsR{y3SD?``QhU$4ZFjP85Bll(6& zST4iPdih`6kQVZWXY3g=7@ObR{HmRQyE%XHpOq*lGybP#&l4k1Ci3UVIa{p%K53}q ze^bs$;{1nX*zZ4EW*_jIe<7fWe}jzQ)IVP45bs|i*Fnwvcgg~f@;}y8ZrA&N=^+2g zyZB*ZhLv#-~VumTwMDvmT`jq+vTh<$$xT3`3)`qXt|0=_Ma|2*4n?W ztz7W=bEN0m`cs9s^Y=)Wx4QlDGXIW#^Hyvp|9W{g#s7nl&i;wAlrH`qGPkb&3uVl1 z{=sr-c8tHYtNa3*|NhQ$is^q}hM)JpDRXVaKqu+(K6cbI8Dk1JMfcCwb2f=l%`xHQ2Op- zJ8+wH*Clq~8A+Ggfg5EdZ?Xg1WGO^u~|Az_;=m_WJ@pS;9}gz&2SzL2SU0Mij;d21%=n zVgpNM?H9)eddbX6Vgt3(yJKPl=Ep-zV*{^9DT@uXmL-(O23p7j6|sRFadd2KV6Cj% zaj}8lWkKU(18L&rgxJ6xGP8-X0r|x=>!jGgcv)>HOA>ds#Rlr75kV)=UAivG2`rRG zEOG*c(o2h-z#f^|5+_h4@IxnXwn+Pt6KE?P`LPq&A)o53 zKXU@+$L?PD2i}n}cliUC%H(hO19EL)z3C4el2yLjANWX`^p-!6E35czf8b?-@Aw06 z$t!x-A9zeAf6pJNm*zecA9z)|?&0{rxiYgy;sb+Z#XTAys1j|rwg{Xf7G2XKFhd%D zZHvHr(xmHJ1kRTieSM2SN15jhEduLgo;S7#%$Kw_F>td8dQM{CdYQas_rOVJbLbwJ zA+L5`av&gWnV%duL0VRu9QaxmTbCTzC1chn2QHV+T96$0NmkXuIq-(~vNSo+UwUa-a=`o~`tsyJ zjVxhBa$v4BV&vw)6j^L&bKq^6S;pqTh0?8An**a{F4>y{Eu=$oHV5R+nl);3AWM3p zWJh3%JU3=XV3*8u(!Ri0SwiK$K)y70^1eW|I8n7PkSHB8WnZ9BnpC|nFi2j*)O~?3 zWO>u}HK~y2<|WuxlT*ds`DWmd%(vDI_@$HT%)lek!g@0hCmJp=1M8$47n*@C^4gcn zDs3`bMqXhCj*|JDWd^3o#<8s5HJ0Awi(zZZCPUm=1Q+^49mcq z@`^7s1CF%zA~Ud5Uf{)M;2U|}mzaT$j2KI|K@~etglh$TGYzD3s5-_IavRNR@}e|8#tb|vi!dKSYtmJ=qF6H^eITzw z2Fxb~;>^HSd0l3#CK+OzZ3c3s!(+_AHfgGv&T5(oMo z$H2G;WywdyI>$PL#DeA-X_nJn|HX?=64NcGhsKT)`&!O%8aqhrXF11fY%j6D<@D6p zPT~N|>7}u)#DSKRs6(*FmUi{k95h)P z)=zVy$GHO&g#&!DMOMK+P>pmc|Xz+`?pO-C)hlO_t^j(R`H2(!QaZn@R2~ z?K?qpyvfqOVVawoEbSYvxrxcrz7sVEOqTYI(Cjx^+BZ^joXOI@kY>kZXGHEr5e?cGL33TxkfdlLL-KZ)r=wI zG-Jqk%@{I4Glopmj3Fm!#*mXWW5_9*G2~Ru7!uZuA(J#?NTp^BnXDN@sx)KB6wMe? ztrJwx(*r_1_p*;n>m&S=k&oyL&aeq)X?WS(=n z=;InPUnf;VYBj1MbsE)>dW~wx0*z|OLXB$3X&Tj#MHwHD>SMhS87y4HfvNvwrEsCuF|N6T&)p9wra+ZYcylX zwVE;HI?Whzy=Dx#K{JNjs2M|U(u^TDYsQdUG-JrEnla=y%@}gKW(>JQGltx$8AI;U zj3L`JW60f_G2|Z27;>*>47pD;hTN~&Gvp%Qld}F>_U$58TF zhCHVkL!Q@+AunjgkQX&$$V-|rk&7L6-`978P-*Tm#zB&(khRl-_d*=hcF~=D4 ziSwzP*Sm)7(Mi>iPc^C`pJ`M>KG&#*e4$Yd`BI}A@|8w4%W(@gNGlm@2 zj3K{i#*p7NW5^$xG2~Cp81k294Eb9#hWw-1Gvp&*tjN(aMlOe(k6l9&nwnv`e`eIN zTE#lCwsVXegc8lwjAQH6og~X?ZydR!WH~MOlRHS3)A9hhy<|BpZ$fS-Sx(EFlG{p_ z)AD$78_9B7-i+K@vYeJ5MNXD1r{&GbM@u%>H7x*121pBA0)hre6B7XP1s?a(rWK%- z0n*4sK!O3%${?Vn0n*GQKnnw;oks(j8z2o$1{`I8w6ry#nE-Qz(*_W4fV8wNps4}U z(sqC*21swV2Lud|mUaO64Um?01jHF2E$sww43L(l0AdZ0mUafnSDM^Qoi2bF0p?n# zE5J5DTG|aDf&^oo7~3~m1W7QTp>=$=XVFu}qGN2o(aTtLobAk#U5{(g@l3B4^(3oB zy~t`&Dp@V+O;(Hgkkz6zvRaf*R*U+Q)uMi6Eb0%yq5%Lb8VJCmK>#co48Wox04y2` zz@ifXSTqcPMZ*DDbRqzYMgXvABmj#-04&M?U{NLji?RS%lnub58~_%L0$@=t0E_Yf zo<-el-v$vRVX(Qq)I%*=CihdE(YD|CWh^SPox9~$j%!gd)2l@#WVL7vSuH9ht3_pG zwWyq|7FCedqOoMPXdGEB8c)We2>>jb2*9F~09bS~0E02ZAGz@qa3SabmZi`D_KXgvUnHUO|_BLIso1Yprc0MDZNwy(Y1jY+uKoH*C2 zMKLB^Z2OI0#-ht?XSlp;;97J!)2l^Skkz6q$!gJNvRbr-tQK8GR*SACt3_MMYSA@h zwdh(h7F`FxqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v*02bW_z@pm$Sab&fi|zzq(Om#6 z+6KU)y8&2q4*-kq1z^#A04%y6fJF}gu;@Vm7Ci*;EV|V8O%_2C`k5Pho7AH7j71OI ze&d(1=yBUwDeqFa7CpiAYSEKqwP-t8EqaQq7ClW?i*}IJqMc;5=ozwF^ekB|dX9`m z&jYaN1ppSk2*9G309f=g0E=D$V9~1pEP4%qMXv*}XcqvB-T+|Hn*c1@4Zxze09f=k z0E^xMV9~n(EP4-sMehT!=mP*2eF(s!j{u%UkJ`SQMUaG3jW~~SULX0E>PDVA1aYEcye0MSlXY z=q~^k{SCmPe*joy#YC?1y=ycZfJHF?&!RoH?*|bip-xnCK2?imn)j!CF@EEhvB)3e zv^Z8R3NXD|)P$@SH6^P>@np5A8CfklimVnjC#yv*$ZAnbvRaft#-dgLEJ_4mQ4oMd zNdPQ58h}N~04!<^z@jz)ENTnDqILi*Y7fAo4gf6b2*9FF04z!YU{PlP7Igt&QC9#K zbpv40F#z^O#{#gZJHWHZiShLpK@$4OTj5SzjCZAfwtUjS=@H{Mei@5;#W)o`)S^_T zSBrX+)uKLRwJ43O7NwKbqP}Fcs2^D^>Q7dS29VXFfn+Qi1i+%f04y2;z@ni5EII*z zMZ*ACG#r3MCjzi&1OSUh0& zln=n70)S`H@iD$7B1pmu^63?)r&_eoymL_)<2Qa8i^jw_S01kxl`_3rR7O^d%E@X` z1z9Z`OIC}d)wG!=kF(*RgB9e_nM09Z5=fJL(aSTq}eMRNdHR0F`Gxd1Gh2f(8F0MDZ0 z7~gggBw>MkM93*oi)NU^TWyTr_+>0w7~^~@Uzc*vi%w&DwP+DpEm}-gi^i_QjM(Ha02tp#AwIRGp= z7l1|Q0kG(N02W;Uz@l{kELso1q748n+6cg+3jtVk5de!W24K-804%x`;8|2J|4MMG zShU{UbzGnprJ5bnrWn8R%UE<}jMKf3TC|zz)uJtAwdg9cT68s8E!s*}i>@K7Mc0zm zqU*?N(e-4t=ms(t-3Y*l|7TpQJqPqZCv<-ko zcLT8K9sm~I3&5iL09bTC0E->~V9|pBEP4olMGph8=n()GJqqwFx;(~LAc7Wj12YH;wV*JK0W6|~)XHL3W^c2&pMNgB}q8((lXeU`MdWNhPJxf-Lo+GP8&y&@n z7szVSi)1W%34lc}1F+~702aLpz@paxSoAsoi*^C9=nViCy$Qgg-2g0l3xGv$1F+~F z02aLqz@qm6SoA&si#`Bg(T4ym`UrqU9|N%H695+N0eBWY5#zg11WC9@K9=h|sTTcV zKHc$YjNkZWEc!CWxwoHM^cB;qMPHNEqHoA*(O$Azw2!P7eM?r0z9Xwe-;>p%AINIa zk7O*`55S_I09bSYfJHw8u;?HFi+%xM(IEg9{R+UM!vHM$4S+?z1F+~102ciTz@onZ zSoAjli~a#%k^Cd`SITOXchu#S#Jn481F$FtfJHt47R3Uv$N_j3eIDa`R|HA;#=Haa zg<4c?-kOc``Hf%3qNYCQw*hKVJkzU1&B$ueQDn8KIaw`gK~{@elGUOFvRc%NtQIAb z)uJF7i;@6XbTj~qk^xxM8h}M@09e!(fJN;9SkxYXMI8WG)DeJ1od8&r0>Glq04(YP zz@n}IEb0cpqGJG9bSwaix&yGN2LOwX17Okd0MDX;&)0FFSoE>EMbyOSUFkQIuPrz| zeSYJYv8a#F88KKbN@IGpD4nbp^(CuC{m5!jf3jLMfUFh`B&$V($ZFAGvRX8Rj738M zSabpai-rNPXgC0iP6S}l2mlt11Yl7JfJGSqEXo96Q5FD;vH@6>1HhtD04&M{U{M|b zi$(*mC?9}D1pq861Yl7S0E>zNo<*rX-xLuf;VH8(>a7-~$`>x25})7rWh^T9Ije`N zMHNi17L6sVMdQe7(Ri|2G=Z!ZO(d&DCy~{nlgVn)DP*0w>~mfkrWP$>dbQ|uvRZTo zSuHw~tQIXLt3}JmYSD7CTC{?!7M(>_i&m1cXcYj9Rs*o;YycLm0btQu02ZACz@l>j zSaco$i_QmN(FFi3S_iT68tjt3_MMYSA@hwdh*1T67&* zExMkp7TrKri*6*VMK_VvqMONBbPE8BZUtb`Z2&B~9e_o50I=vz02bW^z@lvcEV>(j zMfU)(=w1L8-3P#;`vF+=004^~1Ypra04#bKfJKi0u;@_$7Ci>QqQ?PP^aQ}OXtU2Z zPy|WXYTk|Aq85E(zL)W&&u{!P7VYpk<3eiDPNr9jo*}D6&yv-m=g4Z&^JKN?1+rT7 zB3UhZiL4gAOje6tA!E_204#b9fJLtZuxJ+mi{1cW(VGA)+6};>w*Xl5HUNv>0btR) z04#bBfJN^Eu;>E-7JUf7qK^Pr^f3U7J^^6S9sm}73c#Yz09f=nz_aKnpYIG2B%zb} zknGcHQ4{%en)8LvZ~QVAedBYsWU57bnO-g0M^=lzC96f>k=3H_$!gILWVPr=vRbsC ztQP%5R*MdhvFK+2799j&(JufjIt0L?UjbNj7=T5;0kG(I02ciLz@k3^So9YFi~a^+ z(LVqzvSRhJ9gA!L7R3Ot$OpipSO69|04$0FV38kyMFD_k(N{j-(;`ShPxJYruhk;Q zyaUoC)^GeW7Rh%!KF?N*nlrsx)Pk%QwIr)W31qdX6eR{$1u17OiH04zEd zfJNN_Skwc6MaKcK=y(7Y^#ov1F8~&$0z8Z2W94@>#G(!I&19!ptaqh9(R?qpcdXy| zWi09|AK=ebi~2FWTGXGc77ZY)MFYud(IB!~G?=Uw4I!&VL&<8<31qcs7#WL(1F+~s z02Yk^V9`hb7KH#*fM1HhtEfM-!!tglD}NeG)O{dBeH9r>iJQx@wtei@6##X56Gt3~6P zUM-qHR*NQ*)uNNgYSGDLwdfSGT68K|Eeey>qDf@6sFI9DlL1&%1;C;y04%BoV9`_n z7EJ?S(R2V7%>ZE0OaK02a*wU{MVKi{=8bXdVEI<^!;(7Jx-{04%BpV9^2q z7A*u|(P;qBqKa7G#Ue<;UUNb{RxRpklv)()H+~t5&WLsHFHnolWO}t|DOoLAMplcK zlhvXXWVPrlvRbr~tQM^zt3|8HYSGzbELsD=qO|}lItPG7=K`?kJOCD*55S@e09dpR zfJN&8ShN9vMH>NFbRhtXE&^cD#Q-e21b{`C0;jZ3AG@-2g1Q2Y^NQ0l02bX3 zz@i5LSo9zOiyi`C(Zc{NdIW$)j{>mhF#r}l4#1)(09f=S0E@N*u;?j(XVKNMzLa9I z=xg)w#;s~mQ}cGn)3JWzm$B&CSSK__EqadW)uQLgYS9a1wdh5%TJ#cGEqa-(7QI4N zi(VzGMX!<7qSwh-vGSu$MkB^_hhx`2eMl9BUvrlPgaY5BCACQ$ZFBgWVPrZ zSuOg7j75h4SoA9Ziw*;@=r;fs{SLsQKLA+tCjg870$|bK04(|kfJO4P>?@^%V{I(5 z0az3Rz#<<2i(&y-3oe)2l_T$ZAm{SuF~Z)uJS_T68p7ElMVH@%`t^h3R2Ed|Y09bS^0E@ZIuN2UH~jg1z=Hc02cKDU{M;tv#7b_J0OB23^N~0YvFiT`Y)Lq+3Ako_+=~_ z;5don)uMq+uNDm=t3`v!YS9p~S~Qfb7M(y=i-wWaqTyt<=tQzwG=hvpBLP?x0$@=F z0E;pKSd<08qHF*b-#(PXk(R7F;crjW6y8h}Mp0a!E*fJM^*STqBGMKb|d zGz)-5vjJE%2Y^L204$mdz@m8oESe9%qFMkJ)d8@m9)Lv)09dpTfJLVPuxJqgixva0 zXbHfxXuRWFDuN`Wna^EMP>Tl2k9<0(JAUJrv1pm&Tz#@yw4CYHq7`Jd=q$2Yw34hA zts<*MtI2B7*<`h74OuN(OIC}{A!E_G04zEWfJNs6u;>B+7Oewd(Ru(DZ2(}=MgSIF z2*9F?09bS}0E;dGV9})jEZPLXqRRkSbU6Tvt^i=sl>jW-48Wo-04%x+fJIjWJd4hB zd^<&ugqHG)c+OI_=zU|+R>yDrG8SF$IA5Ns7Tv(~YSE2kwdf|YT68m6ExLuQ7Tro# zi*6&UMYogHqC3cH(Vb*0x(k3s+W=T}Hvo(70btR+04%x>fJOHMu;>8*7Ci{SqK5!j z^e_O69syv{qW~;=41h(C1F+}`02Vz7z@qH{EP4unMNb2;Xa@j`b^<($u62A(!(!1$ zBhGbd(V+wh&p3YLm$B#t$LU$A7QM*yYSBw%wdiHCTJ#E8Eqax#7QIGRi(V(IMZ3sq z(Hms7=uI*f?FL}cTL3J28-PXc0I=v?02aLmz@qm7So8q^i#`Nk(MJF*`WS#kp8&9E z4*-ik1z^!<04(|(fJI*bu;@zw7JUW4qOSp1^bG)u_5wVMo^yO9B1po3_9D*nYLRVA z*ys3-U&f*z9A|!&TJ$5+t3~_CYSB+*wdep@E&7?P79Aw3MZb{MqC;f0=vT5@beN1q zzX7o5cK{as0l=a^0a)}G0E_+xV9`GSEVAPCvK@dfM?Nnj_*z=uvZa-6GC!{4y3L z#yJmGt3^SkSBsL!YSGbTwJ4da7PTg;MQzAxQCqTF)Q+qcwI{1Z9mrVJ5r9RV09cd) zz@p9oEb0QlqOJfe>IT4~V*prmEC7qT1F)zE0E>D8j4WVPr7vRX8ZtQHL?t3@Z0)uIt(wP+++Eees0;5V<{&mmE!t;pK~9MC8^4T2r^Gp#Gu5I~nO-dllhvY0WVNW0 ztQJist3_30wP*@iEvhD~MN`RY(KIp^O$T7n3;-6*1YprD02a*#V9^`^7S#Z-Xf6PY z<^iy1J^+hq0a#QAz@mBp7A*i^(Lw+god&?7MF1>X48Wo#04zEkfJJ8ju;@&HXVFP< zzUd-J!nG|#oRig}x6Mh?(m22I%UE<)oO8}>wP+>Nt3|8GYSC)4T68v9Em}iXi`J6W zqI1Y<(Ya)`=sdDobUqo2E&yQBIsg`}2Vl_#02XZoV9|vDEV>AQMHd6G=n?=HT?)XW zO#m#q41h(K1F+}{02W;dz@p6nEZPFVqN@N{bTt5rwgRx|8UPku3-Byj9_PDL1WA}= zKE1y}Ejq*On68WS8^4T2H^n)x)u=@`Grd}L3t26?m8=%sMplb%C#ywwkkz6)$!gJE zWVL7;SuMJoj79eVu;^X@7TpKHqWb|@^Z)>h9t2>~LjWv#7=T5O0I=v$02Vz4z@oY z9P?qL=i~gwFJsZmaZb{FwdfV5SBqXHt3|Jo)uPwQYSAvTTJ#24Eqarz7VRdhMQ@SS zqPNLd^bP=v-UVRMdjKqYAAm(40I=vo02X}&z@m=98H@e| zV9{RyEczROMgIV>$nxuDI~LghEQ$eOkq>}Hu>dS`09X_Uz#=~Yivj>FY68HbrT{F8 z2VhY%02Unuz@p{=ENTJ3qLu(GN&t8k{TSz4E`lVSC_ioO>{pAXn6Egt^81Zn#-gMB z&NU0vqGYC5i&~S_qBdl;s4ZD7YDZR!+LP6y4rH~cBUvr#L{^JZ$XL`FfJI#ZSkx7O zMcn{cbPNECjs;**cK{ak0ASH^04zElfJHq4Skw!EMX3NR>J7l6J^(CA17J})0E_wp zu&5sZi~0kwXaE3<1_C^bf_~q#B1pnqbBid+?_KF%WR7Tq{C?w?vFHT9^Yv+J(J-c0 zi-wccq7%t#(Fn3yG?J_qg~)1A23al2B&$VPWVI-pj72#BEE)yCqFewL*fM1HhtE02Y-2u&5k>MHK)n8VkUpaR4kD55S@c04$ma zz@n1?o<&3azGjQWqMyur`a{*CX48Wo#04zEkfJJ8ju;@$x7A*x}(J}xQEeCiOo$B|M ziXaJV&HHF!wWxoJgcW|j@yl4W+V9kzp%$IZ^lH%>vRbs3tQMU^R*TLht3~IL)uQvs zYS9H`wP+n#Em}{;q748n+6cg+3jtVk5de!W24K-804%x`fJK`CSacZxi!KLX(G>tJ zx)Ojzn*ms~1%O3Y0kG(502XZpV9_-IEV>qeMb`na=z0Ja-2m_`TIu&)CW0jFFt>EP4chMUMio=rI5mJr2O4CjeOVBmj%H1F+~R z02VzBz@i-hEZPacqGteD^eh02o^8hS*0f0p>0z8Xu_WM2-K@uJ`pWeSkE&ABp zFM7%EH+~t5Uh_NuELV$OXL_}07g;TOgRB<4Nmh$?lhvZP$ZFBsWVPrWvRd>mSuJ{x zj79GQu;>E-7JUf7qK^Pr^f3U7J^^6S9sm}73c#Yz09f=n0E@l=V9}QVEcyz7MPCE3 z=oPAV9}2N&!SiSzHTeTqF#w2&Z}zCzP1wf`~Ai* zW6?pslf6D8u&5URi&6nt)Ej_BeE?XL2Ed|p02cKHU{OB+7WD^U(EtDz4Fq7( zAOIE(24K+;fM-#1z_(2VN!Zs_#AzMyuJnWEn?yqce&d(1=){1tYmHhog6Y+wkz}EGhzEQ856E zN&r|i27pDS04yp4U{N^$iz)zEG!}qG;{aGR9)Lv?09Z5;fJG+(u;^p}7M%jXqEi8$ zMZ*HVLn27RmF7x+xLTBGLO9?zei@6Z0#5R|YS9#?SBt92YSC1(S~QKU7ELFsMKj21 z(M+;hG>fbj%_gfwbI4d!1HhuW04$mZz@qs8EUE=yQ5^t_>H%1^0Dwgc0a$bz0E-p@ zuxK#=iwgMVA1u=u!X{Z31A?WdJO?9Dqev0I=vv02XZqV9^!;7F`9vqN@Q| zv=x9w*8s5SS^ySZ2f(810a$bc0E=z}V9`wgEV>!sS#);5ca{i}@SgeoqBUyK!{#LE zmVn>*Wh}ZQ;9R#(ExMEG)uOw|YSA{bTJ--A_a5L;lR)6N(BVq<|Eq zrIL`4#1xt(1PDc`p$OQJqGH9ah={#D_TEM84HbLChN7r|h}hrjnz_!+27R9QU*7Nd zavaOGzjLS0Irq#xTeypC7TrxYi|!$tMfZ};qWj2Z(fwqz=m9boJqW;}hX7dgFaV1l z0btRi04#b8fJKi3u;>W@7Ci~TqNe~@v=M+sPXn-M699{z0btRy04#bAfJM&(u;>K< z7QG0-qL%qi0kG&}02X}$z@n`HEcz6H zMV|q%=yL!TeF4CtF9BGz4S+>o0kG(602XZrV9_@KEczCJMLPgk^c?_;z6W5@4*)FM z3BaOV04&-K@GROK=TA9bENZ8B9bY$#p4E@6{TLTiztp0i;{ur%nnn8<-z@rtY!>}W zHj92En?=8q&7wcZX3?Kyv*<6fS>(i9zuheIk+CQSfJJ@)7PSCiQ2>BNu>dRz0cseFQD?GQ)P-yoWsuFHu4J>Q z8`&)CPBx2rkjF~_i^>34G#Y?Kd)wR0F`GS^yS}0btQs02Yk{ zV9|I07EJ(P(UAZwItqYAM+30v7yuU40kCKy0E_AYo<+ms{aZzl(0zIm8(|hrkkkj(E0&Lf*eYshBN`DC-`00E;dI zVA16OELsb|qALJcv<`qpR|2qTJphZY0$|Yw02W;hz@lpaSadA_i>?D;(e(fQ02XZoVA0b6EZPLXqGteD^eh02o^8hS*0f0p>0M02aLrz@k?G zSoA6Yi(Ug@(Pn^W(e3g6yG4*tP(OElhgnphpA30DKB#`FMQ_Ci-rQgoz0LS$(K}?b z=v}f|^d8wPdY^0-eLyygJ|vq(ACb+XkI81yCuA(z3c#XI0a)}I0E<2cV9^%g{TBy@(}uHIr6ZPtsVz41ZyOD*~}KG5!3v*9 zFcBnlsorS(#Vq8`T($~F93@&0a%m;z@lsb7Ucl2s2>1}`U9}& zPyiMU0ASHT02U1bV9{Uz799q_qQe1LGz5S}LjhPc41h($0iH#j68tMgkWf&6zo>J9 z*VDgS!-#~S`lS{XBm}O%(JU%te6y&CY!;0qn?=QBv#5k@7L6jCMWtl3sElkDjV7B# zd)wR0F`GS^yS}0btQs02Yk{V9|I07EJ(P(UAZwItqYA zM+30v7yuU40kCKy0E_AYSTqTMMUw$oGzH*Ul$YRtQ3MIaXtyliEXvkThBPDu)i1SZ zMnd4*o6VwQ8Q&~Aj%*gqB%4LE$Y#-OvRO2TY!=NWn?>`;W>F*AESgWoq6GjfS_r_R zMF1>19)LxQ0a&yIfJI9ISabpai%tY!(MbR-IvIdPrvR{M832n;1z^!~02ZwPV9`nd z7Oetc(P;oIIvs#TX8^EhHNdlIT7p0I7O^N*-vOC!7H#P);mm}f`lS|~n-Ivp%`7^P z@y((&WV7gevRQNi*(|z{Y!+QaHj6GMn?;w9&7w=mX3=G2EV>+kMQZ_AbOiv5)&a2S zN&ptE2Vl`v04&-7z@n=GSab~li>?J=(RBbUx*mW`T>ANI{{d<3xGwt0a)}S0E_kju;?cM7VQOK(a!)Z+6V9~ zdON}YnFtbkM!)v)j#<<-DB+icp!%g2{gDvx-(wd2$@pf`Uu3h$Nwl83S>z*|MKNTv z$WJzlT9D160NE^xC7VS-G8V-FuqYmYMF{{bN(5k05&(;m0a%m*z@nA_EJ_7nQ3!xV ztpHe*2Ed}$04!<)z@l^j7KH&=)E0n6?EqNR9)Lw109e!!fJL1Eo<+YU_Vp*8x; zGryZfC+W?j&WSF8aS#$u|EIN>E79B)3i+YmHqF!XP=wPy0 z)SGM;9YV&UJ^(E03&5gG02XBduqYdVML7U0>IcB0{s1gG6o5qo09Z5-fJK7j!= zi9z*CEgG2^IPU?osF?B1q7t%MG>U8%m6FY(GO}4Tnrs%8lg*+EvRPC~Hj9oRV^I|V zi>d)wR0F`GS^yS}0btQs02Yk{V9|I07EJ(P(UAZwItqYAM+30v7yuU40kCKy0E_AY zSTqTMMUw$oGzEY~4FD{f3c#Xi0MDYrME|`aNa!GaH@3(uy1%=G>4`!0OD&q27?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04(|!0E=!1V9^}_ zEV>hbMRx%_i_S~*j}SpZck2c98ndWWuZ!+Z460vh(fx^m`p3ThdXQ`uJw!H( z9wwVbkC4rxN6BWkkCB+I_!OB(c#)Ky^|PJzto}+5(76rX%>CR_-4^ZWV7gFvRU*A*(};h zHj6$bn?;|I&7#lAX3-a9v*=4Q7HtDy(N_R0`Wk>m+W}bg4FHS21z^z*02X}*z@qN~ zSo8w`i*^FAXcqvBb_1~JM*tS>0btQj04&-Iz@nc4ShNp-MZW;B=vM$1{RZ$XdN0xc zvIr9Dsy|uuzFG9DTJ(EjQ2kPioTR{a8_gnLlJ(@xq8PGSUu&4_Fi!uP7MSmvxTRklnb=3Psf0;!m z>pLJ_lY;7(T692Cpx-lQ(SeL_79B)3i+YmHqF!XP=wPy0)SGM;9YQvX`jE|{zGSl~ zlZ-`K04&M|U{MYLi~0eus6POU4h3M*000&Z1Ypr102U1fV9{X!EIJ&3MMD5sG!%eE z!vI(`9Dqe509cd@z@j_=7Ucu5r~rUPg#gc@?n(Y}B1kApKT^~q$?NGS>RYo#NkR2X zEgF>+Sn`}%RLb~fQ5o4R8cjBf%E@L?1=%dBB%4J?kjt0 z8VkUpaR4kD55S@c04zEZfJH|Eu;^$2799h?qB;N;O$1<3JphX)0kCK?0E?you&4om zMN|_| z@y()nWV5J|Y!=NYn?(!AX3;{jS+t0379CGEix!j3q9tT3S_;6T698CrA^?j{0$|a} z04zEMfJMsySad1?itR(*zB1q^s{oM6zv#7P+JX(_!RKL`si;@C?m(8M!8Q(0rglraF zN;ZowBb!B+lg*;FWV7fBvRSl_Y!+QfHjCDivFIuQ7Ht4v(bWJfx(0wn*8;HUIsg`3 z55S@u09bS*0E=z{VA0J0EV>1NMYjU5=r#Zr{R@Caw*#=~4geP23BaPe09bT40E_Mc zV9~t*&!P*G{0EC5p^5sr>kG}I3Vmz#zNDb~r4~Ju6exYwEP9yn&7w!hX3?W$v*6AEC7q117Okf04#a|fJH9?u;?WK z7QGC>qE`S|^eO<0UISp!W&jqw4#1)}09f=U0E@N&u;?uS7QGF?qIUpT^ezC4-UE0R zJ&@#|D}sbx&|5?gnnkMgilx!A#MmCE+C!0lI zkjeFwmz?*Ul!0|1M5015 zu;@ns7VQCG(N6#@+6%y4N3ApjP&0$@=Z0E=1!u&50Hi_!sD6b4{XTL2cd z17J~m02XxsU{OZ^7Igw(QD*=abpc>e1^|n?0x0>GjM02WOJV9_)H7EK3W z(F_0<9Sgvs;{aGR6M#jt0G>sq$^J7$kkC;5+;y2*^tfIm%}x%gUuscfa^U9o%%b^> zZx$^en?(!BX3-+DS#&(vELu!9iRM`1As-V0a$b<0E^B7VA0tCEIJ2(Mdt#r=sW-x ztpQ-s`2Z}s0N`0PH`)KH2olQC=4YN+v`s&RePMD?{ZflAO%D9?7+(X{|9x(PVMgIa|(d_^%x&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^m zEP4RoS#)u-zx9V=(J9&%U1Ap9mLlQ7Vc7Co9AIP_z)=rP7OiykMNMNg2;q9@5_ z(NkozXd~GydYWt&Z6cdR&ydZcXUSOf8~}@+2Vl_)04#bDfJH9>u;^s~7QF(%qE`V} z^cnz*HUqHebpRH<0l=a+0a&yJfJJWsu;^_77QF+&qIUsU^d10<-UndO2LLSk5a3z# zaI$}b2ohQy7I7Xii!Rl-Lq19ls$Xi+r^$g6wwgtsF}_*!IoT}wf@~IjNj8hNk#-benEcy_MLz?uXdeKJegR<7uK+Ci4S+?z1F+~102ciTz@onZSmdNw#~h1%0MDXNlKmS* zkWh(!ym6~pbb`Je5|a{Cztp1Gl)zJ;nMFayH;dxPW>GxZEJ`4oMTumyD2Z$qC6mpf z6tY>=l57^GlCdZRz@kIlH1 zP5>*-hO zPlX&s`qTVTi;Fo66A&hSp^&y)@eaU7~CfO{?BAZ3oWV0xTY!>w+n??P}X3?Q! zEE)j7qJaP`8U(nKuxJdPblg*+DWGp%ofJH|Eu;^$2 z799h?qB;N;O$1<3JphX)0kCK?0E?you&4omMNf02a*z zV9_i97R?4=(HsC4%>{TCm8bX{MUc>H{a{*!S(K*lfXqt?s$Xi+!j!;;+s&dyjBgel zPd1Adlg*+fWV2`~*(^GNY!;nJHj7Ron?)y+&7xDtShNg)MW+I=XgL6jRsgVQB>;<7 z0kG&a02ZANz@jq%ShN~|MP~xA=qvyhoejXEa{yR$E&z+p17Oh_02ZAOz@iHPSacx( zi!K6S(ZvAIqWLNQ2St!jqMpPSm_-k|9k!I9`lS}FO$ogBtyy#hY!+=Gn?+ZX&7y0_X3@1|v*XRA1%O4j0d z02ciVfJL_hu;>l|7TpQJqPqZCbT_MLz?uXdeKJegR<7 zuK+Ci4S+?z1F+~102ciTz@onZSmd;{ZaWtF09X_Qz#=~Yi&_9Yi#|*7pDBWbF4oUo ze{L3y(~qnLS_aiGwJ5%2;MUz{Q3B(eMTumyD2Z$qC6mpf6tY>=l57^GlFgzJ*(_>B zHjC28SkxMTMQs3Bln%h6FaV3%0q%3jm8U09e!& zfJNN^SkxVWMLhsmbN~R04g_G)K>#f33BaOW0MDXeOaEpOBs5EJG{&{`disO(6SD`m z460vhQQww6o5r#04y2}z@l=1XVD=o{pml6MIY;%9(~NBm-OnoqGeG1Qj4lv1_u6Y z7S%AmSyW3li^h=6qOoMNXdKxr8c#NhCXmgdBgtmbQDn2|XfhTZ1Hhs>02WOIU{O5) zizWfEXfgncrU0<00f0qQ0a!E*fJM^*STqBGMaKfL=r{lt%>-c4EC3eG24K+~02a*! zV9`7P7BvE}Xgp zCy>pe6Uk=LNo2F=WU^Uw3fU}LMmCF1C7VUd$yl@kfJG|-ShNa&MW+F<=yU)UodLk2 z)c`Cy6M#i$0kG(702ZACz@l>jSaco$i`D?J=zIVcT>!wM3jtVk5de!W24K-804%x` zfJK)9Jc|~!^j{-_gfjIccDz~ijaqbh%b@zD7G2pg@bqtH(R#)=i>@M@MH|Rw(bZ(L z=o+$FbS>E|x{hoXT~9WPZXlaQH~V9|pBEP4olMGph8=n()GJqp00#{iy1 zSG4qhErNt{BnH-*MYrfh(&H_I>X%xyv1K6sPqXN0#y5*Lk&n?)~^vFH^57QG6AX!uLH2?4FDFs3BaN)04#b7fJJWu zu;?8C7QG9=qW1t;^gaNKJ^*0RhX5@42!KT&1F+~502XZpV9}=lEcy)KS@dK}e_s(K zbgjOR_LN!ltA4)d^OiyNOD+1UWuU^*3CQQJzh->1Xgk>~`i5*4eM>frc96}Y@5pA+ z_hhr^2eMhTlWZ34B4g2R02ciSz@j|>Ecyw6MSB5Q^fLg9_5rZy7XTLh3c#Y@09f=p z0E_+rV9}odEcy$8MNX=9+p)+8z@iuc7Wn~K)B=D-0RR@o0z@kzB z7L@_8Xfyze$^lqZ0l=b402Unq@GQzq^*aHvXtKVKmSq-=(0602QiJN3S~Mm#&^2fl zjb(hZXdKxr8c#NhCXmgdBgtmbQDn2|XtG&!4B0HIBb!AN$yihmz@kY2ESe0!qA36@ zY5-u-Q~(xD17Oi~02a*vV9~JvEIJN=MKb|dGz)-5vjJE%2Y^L$0a!E-fJKb}ESe9% zq6GjfS_r_RMF7vDnpA(02omb5w}@)ZqK8{aI6gI~eyK$#qz0zNn?)xwzFBk<*(^Gl zY!;nDHj9>#&7xDuX3=u8S+s&|7Of~V9|pBEP4olMGph8=n()GJqp00#{gLLH~@>D0ASIR0MDZJ zss1-akWhubjenI{bhv&Y%n?c_7JUiuEP6WC-!?@o zdQ5K-Z8D3_(syIGr3Te6wdkAFz~EG~=v&4&i*}IBqVLFN(f4Gt=m)Y{w3BQW?IN2+ zyUAwJk7ToG4;hPo0$|Zz02ciWz@mKsEcyk2MZW^D=r;fs{SLsQKLA+tCjg870$`E+ zC(u{OZfW7eA|C*YVgOj=2VhYP02T!RSQHDuq96c^;s96_55S@XfM?Oyss3X`kkIaK zBF=WRXrSINN(=?nFSV#;C~!(EvnZAE&7u(5ENVqIi_*wuQEReU)P`&prIXE~Fxf0> zOE!zzk+G;f0E;>Ru&5&di#h?Ys51bIx&W{!1As+c0a(-xfJNN_Skwc6MF#+|=s*A# z9R$Flo&YTB1;C<%0a(-A+M+3McDr1 zV0^RaNU~XU6xl2~nrs#wLpF=*$Y#+*vRPD5Hj5^a&7#Rr-L;frgB=mq@U5_)1x^T02ZAMz@l>iSadD`i_QaJ z(Ha02oe#jG3jkPjApnam0$|a_04%x$fJK)Au;?-X7F`a&qO|}lx&nYj>i}4EB>;=o z13ZgP4EYy{Afa!9BF;%>(I*VXMfU@+ z=m7v0JqW;}hX7dgFaV1l0btRi04#b8fJKi3u;>W@7Ci~TqNe~@v=M+sPXj!Qt`7Mh z6+uFslSG_r%%YikBYRUQsD7zM&xZmZbux=yV0^RaMY37+64@+znQRulLN<$DC7VUB zko}7X1mpqQ3xGSQG=mB0m6& zS^%&p0KlSH02T!SSQH1qqIdunB>=D}5r9QW04z!dcouyd@)wIBp>ska&JMHaV0}9z zrBzVks+LFzpc4V`tJ=rYkKsJjylCh{0 z0E;>Uu&4_Fi!uOM)D?h5-2hnB9e_nW09bSY0E-R;V9`MUEb0lsqFw+jIv9XOy#ZKs z2mp)v0I;Yp0E;pKSd<08qHF*b4I`UH!^vjR2(np}OU9x+02bu~u&4ll zMTGz?Dgt29NB|ZU1F)zBfJLJKSX2tYqA~y$jRs&*IRJ|)09aHBz@j4nSX2eTqG|vZ z)c~-l7Jx-#09Z5@;8}ENEB_V|By^F!bvD2(y3OsdwF;_VYSB@x0zVyS79Gv_X3;TZ zv#5@27EL6ZMfGH}XcE~hnoKr}rjX5|2C`W+m5fEx09Z5~fJHL^Sad7^i;e?e(M$jq z%>rQ2YycL`0btQw02a*yU{NCgi{=BcXaN9=76Pzn5de#h2Vl`+02VC)V9`2+aDwrmFWl5jx>v&*KakR)GDZcsYR!@3LM_cELzU^X3+|=S+tUD7Of(i zMW>O?qSMJ{(HUg3Xf@d^I+JV`okhl?vjJFi4gibJ1z^#604!Pqz@qa3SabmZi!KCU z(M13(x)^{(mjJNnQUDfR2Ed}r0a&yafJIjTuxK3si>?G<(Ru(DT?N3R4FD{<8sJ%U zN-O_F5hQe-#K1DM=tliXtZP~Y)i0-w6BFnjf9oMWCw-t?bvxzQyq@N(~lEkH7 zDJR0D^e5z^DmDF6Y0g@wACT@iZPSkvDLba$C70|O=|9U=R*&?d^5xr}=_|TA&LQb9 z$d4surMEoLar&p%_H>*<=~o==I78AuJ;ZTFq#u;&I0fmmvK^;5{hoe~Qgj!F*=cbtjoV{;v6O8S-gjx#;|^Fqg&ncl0|aptDa8Ra+& z((fyCoW<$Cl{?Of>A6QZ&a(8=s~u-$`YW}Lb4GgFILA3Vef$K+S(AR%QI2y_`j^Kz z&SmMn>m6rZ`n<`GvmyO~2FJNB{f}vmb5nZ$v5s?F`s$gEb7%T%vmNK&^fvPx=fU(N z=R3}$=~pjwoF~)2I^Jo_`>b3m3`m~*Ih3=!56;%M%fF#@V7V1Zt#V(ZzOep}uKj&s{VzEO`NH~tDh~05^*_ZM;S1mR zr0fu1SpQq9VqaMQU!gKzSpQ>~N?%z2XO9|RSpRE=alWwrw*FDRu>LsuL|<5c-Fk{I ztUpgY-51v1m!0Vg>kov^^@a5p9vAq+`V)PNec=wIDTy3$R)uzug< zHeXo3FmR_Yte^P4*B920>^|rV>t`+>^@a6Ab5Huh`l+W)zOa65<#}INKX>r5FRX7I zZ}x@toxd%TJ z(hl5#2qpcmR7DMz1gP>ML_RLP@A9vw<$roO>8^ab*1 zRNrA1zLQU*`VP0SN5c>cBjkt6eM2pb>n35Cg%)z1;u~%uUk-EM2rqP$!_(14zN(MU z>Ex>nB#n9aIiJ%}jxZPB?O|V*(@}PwbCeAEDMOynb5B+$-w}bN7l*bywv(?aW{FIp zI*@egGkZok9XI+MXNC+O?(0rCHnioo*FHT-hK~(h^Y-(XFP0HvLswpP-^LSVq}b5f z9eZC|>U4ZV7F1_4${Q6qj97WHUv z6kXJ|@{t0a%K6Ou`|F>+=oEL}zpP!ha)~>guC=Eu(&Y{PcGISOr(=H^M>oWEO_Ld8 z=z%6Q$gMzuh*`U9sa2N^Eo&XvL{B+yzRy z@7<4EI34%c7-PLLVnY|b`|HamyDM?gnV+5~n^HE$foUgu+i%yS-+!^x>AX)yS|qdS zDE}v&JHLw=d)xbWyycDk^f})=>}`TajG-blJBb8I>v z*>WdUXKotrF2uE$ui3Fw79uuu#trX0E{h|3ao^TIzgpsS9v~yROOa<|x6d*OJ~{Q& z=VjN6G1abzJnFE-TqG@e|*llAtb6}6@J$9Pv85??c`Ca$OCXhMJZQVQ7>G+w9qKZDi(*1eS=C$6^ z9ewmg748OJw*7UPii~nj+s6)ZI{s>-Y-cV*ZFvh{+~L>Vee=`aar5!dXFcexN!+SezA-znjL+_1|+PJC;EtO;g5BEA>RQhX^H-n4k@+akS{gtI59n(#Kd8O9LJyT z_)`u`JUnr5Vu>_*E$kI(+X9C=N@831{3*i{6Xj)ZFrUC+PZ_JDTzJH}Ph``@yH8~0 z5^RD2Z-R+FUrCydlGIfumnowpr}+{SnJHINw^+y3%YCv-vfYi+>CELmC#LQB zdD3uqmKPj-!Ew4UjO_ouj?Q{^iaS?XbZM)lC6#tw|B;215aVQBrM1000?vrzosL)O z(;PPr*Z8umPG{LUI;1zA3>g#Svx&Iq3;9=H*Q!l?tP_{9NXFIYo4njrvp#Pvlje1u zc59h7S)cDeua54tbvDw9*`J*$wmS=VvzL)XiV8aLSB1nG5F3 znK^lS{fyc3Gp9|STvy*XD>FN*u3ueFR!(+Zc9z0E0{hIKGrOTrL;a)~eX_Iq_UofB z_m!8My_7j)_T-rhr!-{Fs-HZ4#_a#!7i0dC`O#Zq+Vsra#wiPD%$}1!r?H_=WLqp= z(CBUwZ;Mnm&N)`L`TWf4x%G|56)l`yS0n2(t#anV`E^yf14bXpZjzP#|8VO68wnQG zFKEzx;W(zzpq##wRkFG%4O8nE&RkHpV9DHu`F*GB5ho%{nK65T1i2~^{pu#qnKf(9 z?7I57GlYrO)%k^WvQZ}IyIhzY7w9=dXXPRNcz-~qCxZ9$1p;aR?l0hr^-uE!+W6b` z4a5xz1Y*krtzvzFw5&j@uAL-i2GS%(SA97Uo8`o`@U;mfYH1nhsztaP`^w8Xfi^mo zp)!>~*KUEdj{nn1v>MhevtzeFMvp+6e@TWr6>kAD-R0B;`{&$z0W+c(P$!e)j+W6a z(5kbfZq3%_p9jv=zpnBK#AgT6Ww!qL|DEOecgxwtTl)g>t)~UTv8@B?oiqCc;$_{^ zWh=(Vb`_{KGms%QDI<^)>rWUJI6y*XMj+JpZ#mw5T}JNOC2BIZmMy(~*26Z58#83E z9GlxPZ)5!PVD4BM0r$neGExs4iAA-|{?8+O^GM6;-L12X+I7ECnZ$oyOj)=XT~xQq zU5XYlz4f2W$UnLSF&zW(T67D#Rkq&$DmTqYRgaOK<4w-}w~aTGPR*d~M14_KG-}8+ z4@O20sA@6(`%mc`XsyrW$a064vvrG@j9CB6PKJ2e*1xo`YhSPbhW|}o>G6@?U%YMQ zU#!PwWHOUcd)v;h=E>stZCn0NvaY2+*1yDCOTV|4 zGND+1ysn=wQ4dufASD@Ju@?_PoPKlK)Qda zQhfh+^}lc^`2t}%in<04=oUy9<)a!3ui*1(|y86CGWh|NA>3UbdmPb^ezVN*}61Hd}!I>vnXncE$zT zbPc5GiMy*_{zyackIw_)%s?A?MJ|gD(R~-276|KrvRifidx%DQFf=!Bzq7Tke<0aC zn*D#CG$fFwPg@3h+VSnij6kv+ob6?T$z22OOC-4$X$Aj32bR9#tDSXEV5Qa&cPtfZhWw`yeV=)&?EhZjZ{ zR#)eaEUc@ksHiKeC?Dxm6^^XS&do2543S?`T`S|~SB$PKE3Afrz}1CSHH8I{S4LIJL~F~dYbz@&^o6?0l5vG)bww3bqjPJ#Im)D(51v<6 zkzZO@kXw^mS6(|hudqtjqoT?iy5FGa8JAboRoCWK=U0{JU_}+Ry1d$=BAI@5$%MklD1TeClF_;~-C=Y~ z=4C}MXi0fpEi)c$3zuEgY>@n_@s%|dvdU#;b(Iw*hi>~f|6=)W^7Auk~%SWx7C%El$S=f+Srn!lDgbVcPaBL z%F7G$)fU&hqW-$U+@}SmM0IU`zE~O=8)c8EEvzl9E0Qf0d8snDs-$LoB&yV-bIZru zu4|fvyW6TOs@)|h5UV2#aHu%9i7!uDYVAsIJ+-*@K%6ou6A?S5uW+UOl>` z#+`CiVQ#^AcV+UL30qa2D-&{ewQOJ$n|W4L=hs!&RLC|h6di3JdfTSiM52zT$O@Z1 zxn=I0>nbV>%OkI$a$Z%*$l{uE*`jsTg*7#LEHmq({IXJaar^c6j+{f?Il42?0=Wm1 zi$r1DSA*=uY}tH~sg;ye73J0y=I7UC=atxDp5N?HbeooflH8GX6}2^$wKa8PD#~i) z_=!w{qd^-LZGN=riaI(A3dfX4-#xFk+S|%040^unAt9_l;$M5J#|;9T1<#Ek~xtLmKU{gbO$xf z+Vef?W!Vw3N$Lv6F&^W z(wjt%dw|TGGkaQwG+Hj}&*Zb^3FFE(tgdJ}O=+_qdCl70s=~5Dw{6yqRoL7kZ%^ww z%g!t*@-~XM1OuYx;w&1**;S#R45CkRn>Fsy zEkjd_m0cLwbNV#0m?nbkdpX8y?Q|!L*))L6G_NXGPU)tQ&QbPG^dTghisrVgqS_AP zL6I5CZt%8X9#0D09X@}?wAl?)GUT>vV`O&fb48I%P9$k+qMMq4{QQc#VriNpBd~2o zR}^?lFK7M8i}{6RWwm9wRU-Mwl4|i;PgSf4R&mUG%a|pjyQ|o&(XOq|b5GZG)x~mc z;teUy84X+1EJqhgQ)L$|%t@!0Ev=+CUZLyJ!r9TQuR}=dA6f8%oB}%~Ruz^Ph^1+>Kf6wkrO3oe%E}5y=9bwZCujKrIp&*AbFS}^Gg8!E z&K}gvcvGcVrWAFNRlsV=&fU+65^etWYj~nBBBUvB4`FxnM2?K?Lz_*A!-u^Ubv|z< z&Oe^bn!G71sBjz7$jQU@vA0X4k+EHwooy#6IcY~WAjf)EUBMAGbp^%VdAs>Zen8al z)=rIf)$Y7f*Odj)kWE&r*!c9X&cXvJ|>~}=PLk>#}+`GW^%=-VNE zvorJ!k*q;E{WE$tHq30OpWo0cqtC3#a~BSsJg0F%!{R=(`t=jAVEV#YlcY|aIj4R> zA9*)rsI&o76v&WM=Po+5&-}T4reqHgQr|dv`cQd$WznEMv--}GH)wiKnLoGp)VUdb zre*Z0$jRs<_w9#HmIdfDbymat`SsHp`pj&YJ#E4Cp;>~wW2}#wB5CTv*^?K{m@~W2 ze0gU>>U?2S>KD{Uvb%}{oB8MNd++3;*X!<%EG)06l_tpbw)vHHfgI)@Yd6nZARIgIdiiex8(e7S(=@Yn_cIQ zmMP^`jQiUd`DN1H%NbPLBX`?)ZEBsKq;+p)XXQ9@WJFRwTZ>53E1N$u(WY&tS8H{) z;k+^A9O*uho$CQ1)S50F^<2|*#Ujd%-IG8oLaW1KOLKtXkBzi5fw#B&C^h#c&60>hMK+ssn5)ULTFQdd+s> z=*p;$SH9i~h(1Z^a!2e-Ys+)Ti2vI4jl2@IQFCjhV=b3o z(H&{MWMb2K{*07PiFf@HdBK%duTd+?wSjO?%Gv+%RXLbs6K6{=%>-)doHg%rse=*S zS&-_=k~-@<>tyKbOfs+=$ul%^ za~&zJM=nvC`aT7AGR&541FI%mA+pq53`a}vZuoq6Q?U%XZ2O(8bF1~HSmb_+97BI%w0~on345j zIi(*dowbtu68AJznJZ@@cPKfRcu(Y*Z8o@f7cswB`nQE;?jX{=jZ7|b3>A&7tCibW zvVm=aHa)qC#a5NZ#GYyoP3PK7A?dVNYg^gmst)pxm#ysZW;f=VT|q~#$mxT6T_(1I zZRX}jEBnvg9&&BuZ4c>~MQsl~5o+(Gu6k@qjl2?dR;34*-PHZhme$&tKV7btB7I@) zuemdj6Sez9`)3NgZj}2{)IlcK&rRD}Z_B#(PV~w|?ibXJ%q{V5)`^Re!Pq#`FQ_eR zx(Lxjfa{p(%ht#(n;dT0XwQxf#l-YF#5vY&4|Nf>W5poRy#TotT9PmAinQ}J?skd{ zRW03D>F!&Xp6wR(nV$bwpJXX$n6z-3yG6B=#zN}hnVaXi<=rmk71ppw`d-patt%?a zt!^5RS8FTPZ0-MZCw#vyQe@xc7v(qYmu$Tu&7AD6hIig{ceHmmU7tqZly>`Y`?V!a zSC$2Z|K{3KckuW^uRlviuKBUA^3nz2BF}i)y&EJIH{{ z!V^7mGIh6B^vz6Hgnv30d#!Nf?ibT_-(=ya2kLIEs`XkhZExY$I?Fz7e!n!Tza#fu z++8SV@4qX>N=S1jXCu3+w>MAdC=F~jB4fx!s@Pp1mnTuzExZ_ci-&Wi*X{6hlf`#C zQg$3gtxfdKZ}y&ut!8a`X?ew1Z!6HV(VOZzU9ZEycFB`l$npl6`{srFvUXc|G3v^p z+3gc|@v`kCqn#QT=q*e4iFaF7pVE!Vj=o!IQ`I};MRG_)-z{q1vEV|+ov3Ww$a1;I zm7I%ea;x;pPu!O)ihp-}Mcq@iCC>J4i0Wj$t`h4jx8&`j#JynPuDm<{s7BXB^{!$f z_Z8(RYc-32+B+1B-1e0|xwu4k5&-o>)qP>XCA*Ar41&)$*p2 zbz}c_XHjn|?)NT2^gWNPW_LiEI(YI1w!J5%i>LjMNVkaj>)G2qE&Wp$RNYbe=vL`e zifkRT1fq2~w z@9MkRNzq-$rrV+3t$!A*=|Zbn=Rzkh2STl^7R#oS@j3_YGa6Lyj$>UNy;>$5)jk(j zmCDZY4#g7L@lChV#^y@LnWl8VG4+0po)W$7({$5PZwE#OjodfZ?%2pG?GW#`d7E_r z)hG8j(2fcdVbSt)^JPmH)w!p1M`zDx3h2A2S$0fDcT_xGqOLHsOXU2&{4xOFC2&6k z?(I+8{$AU|s<@3x^}l=j(sl{!8@a6VdM@r{^%f%&b5CC7xlNxvP$~A`x|Ma2Hw$$~ zaawAchPT_tR#cVRHEZOuB3mv;Wot61v|zl!(Yz~FBsUo8h3F?HoRRtYhh_BCoA2O=_4jMc#|6;cF1?{d~UO(Cgpd-FK4YlkR`XpL}xm#FV6Dr-y#@-Tw3|A9*P~ zS0t>AUln&+@buU-0;^k`=|3yxT%VIWSO%)sZ&Elu`3ABR7}RHUU+H0#JF%hQ=y-oZ zT&otXeQo56vu%CteC>T5d>wtAW4ig|i+O+hi$*P+U4KOn;OCn(2L1YB|ENE|e%?Ro z&o7_#mv5&;{k3pXC5?y-=Dq%4RMyvr$k$@LzoxIiX!gq&XQKc7k?)my)bGfbzoP#9 zj(!EG>CeC4()bS@{I{^46=Og66)mFLk)qvgoxYa!E1CNGFv}C{^#xX!TRqq6TC4YJm9M9LtW}nK zuhkS$OY?zR<@HTcW7_LiwWNwhdThqX4pKw3%A&Yc26bZO%Yj|Bica!9M3?JvsKX7g zI@D^O)k>?iRwrAPZ|S?^&9i!n)sjSM0wVH3W#A=1r zTB}D|t+zVO>MX1CtuC>8iq%zC&$4>H)l02jY4uvGH(R~K>U~xpvHFx%`ChoY9KiS(V1!9Y0o%7u{aTR`qLwnmbtSX0?~qEUN>p4zpTlwajX@)d^PX ztxmT($Lb=hCs|!-^(?CwSiRip2CFw(z1`}4Rv)$cwAB}_zHaqhtDjiiX7xL(d#wIu zHAdPI-5&8)KLm>Tb*L{IIE3Tmsnk9^>nM} zTD{onI;+=Oy~XNXR`ndG>+^)wXRW?sb&J&xtbS&7yVadmf42Ik)qu2NQqxwW{YOo!(K3aXS>0y!2dn$6`s6xG*DJwlYpeaN=E^0YzCPOOWI1e5kOKHch*WnO;8YHWp<)2x;q;pOpGFR1qNRaW1X3oc#$FRgYS z=jGm3r%dqjJgc`H<>d#g?mWiJe^?z*@8x`}CrSgP_e7)6=H+cD5t39sua<b{L$4m|DEVb6HA)auITynMdZ7hmx5J62O) z_HrkyV_x<0WUK2od--OopS|JbAFTF#%gcvao&AoNPq2FLdtQFZ>aQPoIryPhM||wn z(N<5}>g5ZqzWkY&-?Q54OD}h^I_@hkH&|W2-OIOH{o-3M@3MOE_g)@ob?#0tpJes^ z-Clm$>hF8J9RHJ7^M3Yfh1D~D@$$u1UzHA)?#~abw*J%0U9C=#y9@gIG^-n8y!pr#Ugjs|BfEJ;Lgl@+)Hc`lVJk z%g>2v{>W;&{H~bh?pBYIj-cilR^S#v{jXQn3@sq8#)hfev zwA$5pU#o{(Ew)-~b&}ONR!_9LTB|I_2CMg2{mg1xxhbcwms&l>>IGJ>xB8&fm#ltl zb(hud@>5khopDy{tzKgFW~(1t{mN*YQ5ECtLjbPtu|Uc+3Iqu=UTnM>Uyi!Se46ECnmwWm#53Ae_EwG;?_@Nyy`A@NPd*a zxYKw3l35GtCrMq<=+)^wlMj0@aQf<}tDU}+t3A z$kaJ9qWipl(xk?QMc%j`kzetNj`fZDtp}UBH^kq`O#KZWo1!e9(^r4mr9r-E6gAhW zjrFr+pxmm_ed`x2Xq+)=;R2cLf8(!%4C|AJZcF{^@0G~EvI*V4uJW%A=l9~@hSS&d zPhC)N{%^x&$uRrRH~OcRbRX*9A@Ycq#|U}oU))^zsYI#i^3Y-Qq4O)32g@K&ouh)% z?+}mqFF`V zIP%mvU#2HbMC6axo!Y%v(bjp!f>1HIWNtW;RX?;>U{O@ zNqIzXzj0CPnxrEoh(ZJ1ZV8TXE-> zefQS;E=b?mDR#upjVp`y`WiRwTbWU@=ibKTqD}ka>No9c(eDjtGS#QX5r}uB~kL%uR`Wa;#_c@`BLe4JTD6h$~xv!mRqkp=`vlt_qpuP>z9vOUi$Z?NZYflW$Es% z`7(Ugh@CMjg0eh2vc|bfHM>-oX{v4&cg`g?=Xs@#qZ&)*H=Fa^(s`ril{6OX97gP( zG+)j2Xr5`roXtg|@r@ z_BvLdA62q(-*u^J6T44e>-&96#hxdt$Bp{Deq71;((&%xb?k96-|I34j_N)!ZTb~9 z)SLCPT>W%=R_t7szfqQ}c=vttH_DRriOgAFnQ?4MvCijacW&F=e|sILWaGX&v;4b$ zs`mdhw0rKTyb}NJEAn-H^JI=4%ZAH5H)V8}<+{rE^p7JNes!1au;S0_4;yuO>ER_! z+g`TG5ueW(C;NZt3Z?nGpR3lb?zxa!8o!?lNtXvk$Lp4IZHRYmsNCv2A-`BX!tuo{ zb8gP)@7$EpzjF1%GsDw9Ua{5jE!*JtE&FQekRwKq$m#Ur_x~E5v+jhgammi0Nr(3N zbL-b#{ZCJ6_2{}u32#06&E-7~+%)x!1MeFaym)=?cV4?a{jlRNJNeT7@8!)dOj_e4eS76+ zM-F`W#~0QYw>%-|rnlcRZ$_CnFO|ML>gAGGil2!xHh=fF{AXO_o{^!SD}Ao)nJCv8 z^Xby3M{O$E)Xcd2-QT;`R=KV|Ui#2zwTyW>?mVlyJyd#+OwsYl)Vn?-uj8`!x|qKt zu3PEuWs6h0kJ$V1u+rTVPi)b3)ZVSZzyWex`Fxkjepz$pu0WzxX$^KP)BPlmt@3zM z9;xz><9E znbxKav^K@N)4I)=-eQ2vF?92E{dc?jZ?75pT#mst-6nRMeu3w4)o1m2yMLD!ZAV7l z?hhIVON+K6V?}XZk(zW&;mM_eU8#ZR-t=8@d6%v`<>#rg&vv?XYOyOW&|+7TUs{Kb zvIHrzGy|m;$q_L3xROuy?K|};S+}S5ZQc6RzK%~O{q%ZAtxxT1G4H8;nVtDDE^kx)NMUzKq(66IJ}-*haDIkNPq z;-f|#U9zqIpN@s#^4NoX(th#}n9Ci-Q&->FBlwlbQ(l(v5B1|`~}$UaN!J<4V7F@Kq` z5qo>YDA|#bzqc+=_L8)M`ur5xJ}}agX-Ay&LA|>E6p~Us77s-fg=c$cx?O z^E*55T-Leh!LL@2ulaSx^7OkW#SD8yK1=_H9@BcvkKOy^*t8#KZVZm7{`!ljF5TE7 zu7%S=-q^Uc#mGk{zu0C=i(h*!(c>}ekE@4n&HJEk^|nJN58J(So1E#F-QT$`;i`ic zzklE9JDo1h%4N?bI)l16%TJXngi|-XaPK!me>(QbfNTTK0k^y7fZHSI0M0(Ql-@e( z){@(r9g#Pe-ZJWzl3O_k^wV>Iwy1gzxS{k)Z670N0k@5J+q9eAf495;_Hx_#b=JbK z8I?Bua?kqef8Tna9%;QDIcuC-?6%$RbfV81+IF8&vbuEjD0T0EFDv#8KT4J@PL7E5 zRi&p%+p!~SmA1RfR+Vn6UsdvD{VG|v9Z%}ezAJo(`z}0X&xf~<*!x$%ik-3X`Fp#R z%l-Cyo*?vt-ze{N2}|Aa#xG*`+!qadzIede;bjeXCAS9&_c96{p+Sk;k3# z*dUKod1NJD;q)%soP34v%DT=eS5!(X5+|)l+y(MjeoCBwSBu0Ed!J1ixi_|~u3U!K zDgGa-?m9rK@{jvIyR(Ng%PzY^38Es{ErQsAC@KPCi-m#RnAnYhji@NL*xfC5^RpGZ zQS5GguFLtpp8LN2L+A5$&+hE(i`_Xh18g^D{W0lll>eLlJ$<9Kw;8t0y7gaSTmSd9 z8~j73v17LzyXzJm{(9}z^mDfDf+4>R>OXeZEz{1QL%Jn4%YBWtho`>5dc(8H>7(*z zzg_<9Zyr)4lMOG8qN!Dt^S6^@SVT0>V=I@!_#~sT|+HGcf`&EYj zpSN0Rc>1|HY~^^X&i~h2eL1Uj?bZd)|8&ss<HQ2$?`Qffzg|8( zv3>sm_x|~DOY@w4KRkKNrZZmYKXvtk_I+;5gu{Ctvhc&Jr(X;I{ft}V(7B64_Wb0> z3x8)|M&ND6j+UU@CaEBGPdw~9pBP*-5uNZ|LX4B_B&$Hu}^H@ z`;GAp*WPqZx5W-xzWc;u+gn?^rXR9j&shAD-uLwWeb~WE-g)^WYxbJ^rym!7`P(l4 zJoeRNmwvqIN?SLkx0!I=tY!N5IduJvH`sap$pahWT%oDq!Snz~>j~+BhRyT6`Ty&m z#)ghl(n(EYL-pKrzrL}tSUH{EG&Yu>_e*!)x1BFt9@%STdi%zvVp2M}tn84^EE-46 zx!r%MoYp(7YB4^?YS}rhrlunQCa%V&a$1k{=C3!Te=X5%jr8V~%lf8&_3yq(x?G%* z{?+k`bQV=M9iA>W4R6bTBS1MlpMR8t(%D8sIVPPyG^UsiDnCu7seC0YkgmR_h+4oXk8%~Af89#!aBZaaT^$faB%U7oZ2 zF5NJ_%Qw>HxyqN*tvGl2NqWmZWq#?(yyc3i^evxCAF*FKFnyHy%5Bnno4;HoJz}#! z`Et6vVEJx(Z#$;H_ozdMoywgSNPlZadD7hJslReoy3Ws*J<`KI&y`=N>-KzkSNeQk zD8El{IitEky1Ya~b-wh$mTah=mELNphU)!YJ9JpOp*k{MoBj>ee(67FHdN0{xA<8N z)%(&FozzgBoNl{w8miZ)n`?4I_2ab8ZKyt-ZnpCps<))~a(+W~;q(EfG*q`p|L=l^ z>WFleE^MeCls?c;4b=^wdzTr1fh<_26`C{nk+JmOhcujnymC2YR5f zIv`z_&nwjr(pUeBO7-`2Q_ikb?@I6U%S!d&o--8Oke#`P1P0CJKLbCIy}9X4by+p z$J?l>x?B3s#!c1B(#PARsoI_n*tDs-aWcADQ+50FwcWg_Iw5_a(M{F2l7=mssyC*0 zwq;Xwayr%Ds;N3Uec85dst!nYZfU9>kgi1cqWV($jCvH+hIC7eFRCNct#n9Hy*ItH zLyPJ+>6*P$R9n+2@Vn{H4Nf=Ydqs7x^se78s#m4!@c<+7R{gX!=}S^Xt_$zLt2@20EtT3P)w-4d^t)#p=uqpWV0ZnHPb z>NDx^nPs&t(YdFkIzBnNx21YRdS~~wRBP!AcYjOuz4QzE()Q|VNzrBP)o$t5y}Z48 zT)IkEv{#o)Uydu=t9{b@oYr3Loj!-F+Nx1= z^^zoZe9!8+=@vYsXZ6^m_0XQx;pvt?tY`JAbW0rGv$|mV9FFK&Jv`mINA|3CPPfug zJ*#h~H#xdzwO9HG$MmeWr1vs-YIVo-Vb_>ieLcOiAycbE({)*EYPD~AFGHtR+tUrQ z_S9;6CZfYSQ>#0tTVjL9s;j2|x8Y;e>(cw&Zgw?4HnaWg>R#z~*1hJ7mDn!hvqBOSE9@pHczFRFI<~GR&%~^clttf$`_VM@3|#k_%pptYrb$m z`UKOTAK#(*;&justGhJ4|rq_#0%7?rL@KCVNj`_nsW+Pk50Y1-*W-{ABXElp>n(b`lj zR4kcHbso~cL$PrDeWCNFxlD&*k(hnb9MGXyH0C^M4(w1Y7IW@2m+eq29&@fV2X!cx zh}k>Ml3LT22WA;pQ#STUPm~*7LOuAaj#O{%Ix?Tffch5Ur zv4OF><(;nCva!47ovzxT*j@5Y*KN7jwY<}nTRwJs-s#$nPO?9O?o z>$g(u*0cwt>$h_3mb}yTTP1dH4h}yP9{peyhhW^G?@qaO{qGr|Y*y z>>}@U{f5L&uL~bCAYH#TW2aYc4;hfI-&(O7(;k?v-_Y0%d8g~QcI@;?wlx(CR7Rz* zfBRR7PqE;Cf8%BQAL)BQu}-;U`h}l`3@=6{F#ib|5r>A5kugKa`Y}VusF)#SgP0*? z!6IM z+t`F`7n_jnV-vDNY(mDyCS=FhgzOZXkey=_vP*12c8yKQZm|j3JvJeG#I6e&RvDMR z{_Qi;_poBUx{!;~_wr)TGRw(A_ASOGKK}_B7l($B{bGiY{bPoZ17e1d17n7egJOn| zgJXt}@i9ZlAu&V9p)m6*n}Jzn~ajIW0CJr^hDbjM#*n8M`iI@5-d~^>1%U zKbebt>Ow}QdrQSxWtNkLOfDv+AGiMrIX4asA?L*mA?L>oAyZ<8kPBjlkPBmmkf||4 z$VD+j$i*>3$R#leximH*m&GRJ^4Nr25u1=JV-qqhHX&EVCgkeagj^GwkZWTTa$Rgf zu8&Q~4Y3KiF*YGL#U|wD*o52?n~+;$6LMQ@LT-;u$Q`i>xifZM$fU}h>FeL#lJ3Y9 z=hTI4pY943ca>RA7II&4XS!SYpOE|G&=B%K%n`6Olt`7~w-`7CA#nH4jH zd>%7|d=Zn7*|7=vGBzP!#U|wI*o1r&n~-l~6Y^bbLcWhp$Pcjz`7t&jKgA~G=h%e& z5}S};V-xaQY(jpIO~@ay3HdWNA%DdtK zd^tU8mg#ip(o{4x6mzAM;jZ~?rf7(x=S@4^?d@pyNju#wFYS5KPIt?z_S|WwyXDRH zTxqAf<(=%_X{Wp8E%uygr@Q5?cCWP4-SW>_l_AzjC=Lf0J9mFy;T$st|K?m{hxbTxYj?K!0DIfu}eL%O0ph0ZyoYuZa_O(CD* z%qg_wkgjQOp;Hd&n$9IO=a8=H+(I>nbWP_G${f-)?IU!|AzjmXg(8P^P5TN>Iizda zPe{MX^uJS``Gm$4^106ZLPHMenl2zDAl;gZ#)it^1f=$6KE6s;jpG(@0iO@X4d1d4_V z6s;{#w2na0x&lSRgu0@I8!8hLklN7vpwc3t=#TXHO|f1>nSEtN>o*ivCs_X}8s+#< zw1FLpHnc<0Ms_IL*bYUT*r8}sI}~kZhoa5xP&C@6XbXX&Ed`3U5-8eQplBO`qA>zR z+X@tICs4G#K+z5YMPmhub`&VuNuX$Ffudamigpz!+D)KncY&fk1d8?)DB4S)Xm6pe zXhcKh`2?i)M0#|t7#WIQOW%WveHzN_D=XT+q4+vI_V}No0~{ZU4zxqjL3SuQ*bYVG z?ND@x9f}UML(yS&C_3B@MMu~a9Vt+Blt9tZ0!7CN6dfy2beurZ@d8CB2oy~aC^}J~ z=p=!nlLd-S5h$7{P;{z5(P;ujrwbIFAy9OtK+#zOMP~~XO%m#g#x+#BrXOatb@CnO z{X)@Y>0$5UoQ5*{%8Jf!C}&<8iAr~1&Xc{D7s#t=mvqJ8wHAP5-7S^py(EX zqFV)uZWAcFU7+X=fucJFitZ99x?7;=9-*%2+=j~N1f1vdf9G#M4}_wl($iwadktmwl@)!|P&}L-2KrCY$Bqw0 zpV*=3Q#%xWW{09#b}0JX4n<$sp=h=pioUc%(N{J_Ukem{BT)3MK+$&sMc)e){UA{E zqd?J50!2Ry6#XJl^s7M8ZvsWX3l#k!Q1quj(O&{Ze+v}-BT)3OKv9Rr|Nkt%evZ~4 zP}C^Y6@Ac9`6L0UjY!Xf79WP9ru58kQE4o*udJwSEQ*CfQPuIGsM!uho$OH5Vuzwu zI}~-cLs6R@irVc^RI@`-7n`E40!7^fin}Q1HEIA%UWWg}S1mv9eeKQX80_053W= z*3b0&riT)XMHP6fJFsqW*R$TE-4V1ME;V&<;h*+M#HW z9g3E-DOz5jXa#|y6$Oe`5-3_(plB6=qE!WoRud>%U7%>NK+zfkMMDIN))XjOOQ2|| zK+)O)Me7I@tt(J8OrU5zfui98MI(f|qQx33`z9c@FVkyHip4`w{;itD$i_1J%8E8@ zEY4ai6m8`AP_(ffiZ-!B(WZ7N+RP3`o7l4JutU+7b|~7)rf6${qHP3<#t0N` zD^RqZK+*OBMLP%-jTI=`QJ`oifufxSigpnw+Et)vH-Vzv1&a0%DB4q?XfJ`Hy#S2Qa9&EE+~ZQk_IP_aQM8j^p!?bldlUs=&Xjl~;Fgrb8TABx7?q394h z6dh`ZqQmS^bhsUgj<7?~k#;CL$__R{lyr zYE$#0jt7RK;rScWd5vZEl@(psSj@9@D4Oc{P;`+UiY~T8(Is{$y3`Ium)W7{ayt}V zVTYnC?NBt$rsyhxqN@dpt`R7@R-ouQfuidLif#}nx>2C$CV`@x1&VGFD7sak=r)0( z+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj3`x}qtKl_3d8?TGZsjN*b&G$6f@r+A>T z%)YXs>5awMWkS&-jt@nT+M(z%I}|-`hoUF!Q1ql7ik`AV(bIM)dd3b#&)O6{Cs6df zK+y{VMKc77{wGlMqCnA00!1$i6ulx)^r}G7YXU{D3lzN}Q1qri(M*A&w*-pb7ASg0 zpy*wJqW1)f-WMqPK&UHvsIhWV0#e&LJxpCZ9Ev97S9g5aSY}^Y(Wi~YwF5)ZXO0g= zv+PjxxgCnWutU*oI~09shoZ0SQ1rDOioUT!(YH25-w70bFHrP@K+%r^ML!7?{VY)Q zi$Kw@0!60$^9vL$AW*cRK+!@1MGFfQEh12~s6f$TLS0d{Qt7^2QZzn4MATfVpXs+Y zrm=XX%)YXsr7Ojt6+%&e$A_Y2>`*ko4n+g)P_(QaiU!%CXgNC+EpLaS73@&7qD|3C z0!1qe6s;mqw5mYSY63;83lt3&C|X0HXox`3ngT^@2^0+#C|X;fXdQu~bp?us2^6g- zP&8biXoNt~NP(jD1&T%qbwx{7DqAKXwS)5aqNPI7l9e?hoVayABrxuL(ye+D7xGZMOWCN=t?^jO|wJMRdy)4+73n6*c4qW zP;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS6x}IMbeBNU-2z4T2o&8b zP;{R_(ftBN4+s=JC{Xl}P**gyQduGasjZ%$#=j^O-IJb$Egr6v*;iKdSfv=bMkspR z@uBDmI}|->hoYzKQ1rANik`7U(X)0add?0-&)cEs1)HK70!9B5D0)$#=p})omj#Mm z5h!|9py)M$qSpnA-Vi8yQ=n+3K+#(QMQ;lfy(3Wcu0YXy0!8l&6n!92^r1k}M*>A3 z3w1@0R4V%=Ahl=mORXObMYreE{!c1p_LUWVUMVK68H&Ded?=c2hoUd-Q1q1@ioUi( z(KmJ|`qmCb-`Sz)dpi{UU{my?K+#VEML!D^{UT8Gt3c6j0!6S~9gZgwc@Zik{Cb|{*|4n;j} zih2nY%_&gSTcBtzfugwuislh0>LXAzuRu{>fueo_Me_+1%`Z^2fI!iL0!0f66fG=J zw1_~_q5?&W2^1|ZP_%?V(UL-4QA<`=6v9g3E>L(vL$C|c1DMJw5%Xk|MTtzuKOszA|d0!6C}6b%+A zT0@{{h(OVr0!3>H6b%(9T3euK9f6{C1&W3V6s;#vG+dx)gh0_qfui*Vibe?(Z6Hvz zp+M0_LS0e+rpj6gNUb@a=`RzCj>#{=-ngmEzOtgtn~I&*3q_+HABwiHL(!IYDB8*n zMO)jUXd62ejj=<~wst7m&JIP}+Z62}P&8JcXh(sfodk+@7AV?9plDZtqTK|Fb{8nx zL!f9+fug+xiuM*L+DD*hUxA`=0!8}?6zwlibbvt7fdWMb2^1YH)D>;oR5>L9sXdzS zP;VBBUdW2ZH`-*P9g0q{ zL(v4Aq7wy*P7)|OS)k|?fue~5MW+fBohDFpxPqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+ zXu3erBSKx#B~6t%MkPi2w-sm#8zq9>b*Xiaro1`cR$ zoBTuUiBNP+YZ|kf%IqsE`m(7wV&hQsmE%Lv*LEoS#tuc_+M(z>I~09yhoT?sQ1qi6 zihi;~(a$zTzX%llDp2&BK+*34MSlns{V7oNmq5|q0!9A_6#Xkulzvp{Qeitz&CZ zW?xxRttcMbG!%7ld?@N_hoWwFDC%y9q8@fAn!^r7J?&7`%ML|z+M%eoP0?HeMRN-j z%_C6MN1$k4fuggXbFL$ zB?XF>5-3_)ps2r4SJYNiK2JbuWAY2r+Kc*`{_gpK>}85F`^t(26-D#tP_&%mL(%ef zC|bb|MJw8&XeB!ot!#&)RqRl-svU|}vqRD9HbsL4iq;S)8X{1%ra;kJ0!2dwiq;k= zT1TL0U4f!u0!8Zy6b%hdZ75K*kwDSL0!5n$6m2Th6%8yZ zOC=z+&GPH6mkmY7LubK+&B7 zMRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el2^2jnP&8ej=n;XUM+J%=6DWFIs4Kd> zsC3viDS9b?`?(?%ot^(=&L@g8`^t)*DT;pEhoWa4ABvu{L(%hgD0;yTMKkPB^glZk zy=aG`m+VmVvK@+Eu_=00py)M$qSpnA-Vi8yQ=n+3K+#(QMQ;lfy(3Wcu0YXy0!8l& z6n!92^r1k}M*>A33lx1KQ1q!l(PsihvjmDh7byBds4IG^sH~lU)Mn=g8lMhD4Gn3` zF3RjHEBdA=b{QLrzIA*k`pynT-`k<+2Rjt~XosSo>`?Tx9g2RjL(#8xDEiH&=y!pl zKLm>Y6e#*jpy+RbqJIR6{uLA#+TqAlC8%)YXs6*?9_?h=YtbbKgU$qq#;+o5O`I~1*IhoaT& zP_()oiU!-EXbn3Q4Y4U&Q=n)qfuf-TMQaNbts_vhu0YW+fui*UiiQgmjSwgrDNwY& zK+!0Hq74L!HWVn@NT6tAfucm>rq8;r}w38i*cD6&&E;dEG z3KZ=oP_(;1(H;UtdkPfoB~Y}tK+!$|Mf(aAjT0!^PoQXjfuaKhiVhSgI!K`CV1c6X z0!4=i6dfv1beKTV;Q~cR2z5nUb*zj@Kx&KRd)HfsqMP&YM>{h8-Al<=R&;E~;;21C z(Q%FsMaSEr=ma|yO|V1JiFPPD$qq#)+o9+bI}}Z{L(!==MW+cAoi0#xhCtDo0!3#D z6rC+lG)bW79D$7RhquFTJ)Jr|0OucYyH$1?lMioWky zY`A|Y`oZy`=tnyg{bYxtpY2feiyex7wL{Twb}0JY4n=?1q3BPWqQ3-+{uU_uN1*6m zfuas&oVHWcAW+mOP*f2pN-v41KVwf(AyCv&pr{lmstOb}3lwz{C~6TXY85EzEKt-Y zP}D9^R1+xbBGeUq+p%&`0#f@tKaciZC~E7KM%S{;zOte@%Hq5OLs3u1hoW9~D4Np_ zMZN7%G?yKU=C(u8Ja#DRV~3)7?NHR$rl_Al(R>0$^9vL$AW*cRK+!@1MGFfQEh12~ zs6f$T0!51p6fGf8w4^}MQUXOw3l#MiC|X9KXn;V`K!KuV1&Rg<6fGyz6?HEw4C|cbPMT6~7w1ypuhS;HK zO*<5=Wrw1nHbrX-6s;prw5~wWFoB}=1d4_W6paul8Yxh;zCh6^fuaoriZ&D|+DM>i zV}YVg1d28lDB4V*Xmf$0(E>$V2o!B8P_&g$SF~bTX&j#vU6{WYtrUtXebd;wEVHky zXuGnQ|Ikphz2igC4t6LSYlos8?NGFn9g23gL(wjFDB9HyMZ4LdXm^{UJp_vO6e!wD zplEM_qJ0F4_7x}^Cs4GXK+*mJMF$8J9Vk$AkU-JF0!8BmiVhJdI#i(OFoB}O1&WRk zC^}N0=qQ1rqlLPnF=b`l1f;e=egbyeP}I3!8po7n_LUW#P!_u#9*QP7J`|m3hoY10 zP;{~#icYaZ(L_5Gooa`o)9g@mx*dwnuqirIpy(`tqO%2xCJ7XsBTzJ1py*tIqVoib z&KD?}B2aXJK+%N)MN3W1_41&XE#bw$UOmD3ZD z+SL3I(ea^ZYJTkcs#D0)_?E4rqvyqbX2*37Tozcv)Tmme>Bt}L^! ztmuDb@$=E4=takeqL=JY^s*g_Ua>>bt9B@Q%??Gc+o9+UI~2WXhoYG_MQ;fdy)97m zjzH170!8l$6umD{^npOphXO?(2^4)SQ1ppF(We4Mp9vJr5-9pypy&&MqS*pPUkVg` zB~bLWK+!h>Mc)c_MK6?<-p3?G?{`aZW`v@1@=N)@E6eOFEBdJ{Rz5Bi{p|Qq^ot#e zezil6*rDi8I~4t8hoZmjQ1p*Y(Z2#k9jbB4O;LkDQKLXnMWCojpr{Zi z>L^fD3KUfZikbzAItdiD2o$vn6m=FTY7;1G7bvO;6m=0O>MBswO`xc|P*?OrS=lZD zsa>B>?tctLUGfwBJ*s8)l@-ldEsi-M6!ms|D4NR-MRVJsXdXKh^|3?Iymlz+YlotK zb|{+94n_0Z6fGc7w4gxILIOn#3luFPP_(E((P9EciwhJjAyBlWK+#eHMN115^%p2w zMxbbbK+!;fqGbh&1_=}`Cs4G!K+y^UMJoz*MLnyPs}hjffeR!!y{h#y{mJ=v60KA% zv#+dZwQBLyiJ@q9$A_Z9b|_lI4n;%kP_(8Uiq^72(NH@St!;;*b?i{Iu1(P}fui*U ziiQgmjSwgrDNwY&K+!0Hq74L!HWVn@NT6tAfucWWsWR=!F=YD4px{;HwqwjOD0TP?G%tY~bt=zK~j+R^c$XeT=q z?QDmlUF=Y_s~w7VvqRDDb|~7z4n=#~p=d9gqP+!*_7N!BSD$)ynt;q;^}M1n0z1G&cW{Sl3p| z>?*C-m*i{+jb~=$EN6Afui>WiryC}`aq!QLxG}?1d2Wu zDEdU8=u?5B&jgBQ2^4)UQ1pdB(QJXDF9nLe5-9pwpy(TcqHhI?z7r_=UZCg)p|0q~ zYNhF{q-aJyEqf^xjmR%q`>|SPUs=(w)ndU(q3Acqhoax@Q1pi#ivF}i(O-5b`r8gg z|Jb4EUpo|aXpZytP}E>k)F@C?5h!XBC@KVsItmn(0!3AUqGo}jP69E~ZC|X3I zXic@Zaps)4RL%Z zTGI|iYuTY_s2z&dwnNc6b|_lc4n@Q4P_&*MiiX=1jSwgrDNwY&K+!0Hq74L!HWVn@ zNT6tAfucdIyDrX>iAG}njMNxw?okxb|^a24n=3#q3CQo6iu>2(K&V~nru^a zu0YXw0!8Nw6ipE*xG0!0@I6kRM(bcsOGr2<8l2^3u}P;`Yr(Uk&4(*%mH z5-7S_py(QbqH6_;t`jJ_UZ^WNxw*1K0#X~AfAi2Oq3Fc?oc;~XW%iX7-O^kfcX24X z)$yU|HaisEZik{f>`-*49g6O?6g?wQ^sGS9a{@)r3lzN|P&7lJ=zju5 zFA8-qT81d3V&idqGVItvuF2^6&p6x9TZx(F0?6)5T^P}E(Z zsE0t&90El>1&VqJ6wN76)LW=4`mMRLYywidGC$Dxdnh^~|1mUkbt<#3tZ3d&#ir9j zQD4W0qJDNLn$HeJ^V^|l0Xq~eXosSO>`=6@9f}sQL(!r(MT-d(EiO>Bgh0`f0!2#+ z6fG@K)L)=z8G)h!0!0G_ik1~98YED(oIug?0!1qb6s;&ww30y4$^u2J2o$XKCqIK+0w5}bB zhS{NLJv$T)w?okgI~0wyL(%#+MWY0YHV`P(T+l0(U4A+=?O^fr2Io{ z%}{h(R`=6~9g6m`L(#r=C>m#nqW$bp zw7*T!0Rlw_3KShAP;{_B(RhKPLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1 zI!>VIc!8o51d1jI6rCtgbdo^P$wFPxE}beJuS<%a$j^Z68j5brzmw>cPG$C$6`kIx zSonrebcW+Y(V2EAI?E14XWOA@k{yc9u|v^hI~1L3hobZBP;|ac(G-EA3j~TT6eyZ1 zP;`+%(ZvEqmk1PHDo}KpK+)v_MOO$ET`5pBO`zy1fugGgimnkTx>lg*I)S3=1&VGE zD7sOg=q91A=+sV?5eZ0bVq1c9S}0mD-$}Z;Q<;5bMYne<_PQw)-QoC9bf+DP?y^JC z-F7It#|}mJ+M(z^I~3h-hoT4UQ1qZp(L(}74+|7c7bto}py*M7qQ?Y^9v3KjLZIkL zfug4bik=oIdPbn=S%ISG1d5&)D0)GlXof)1{{)I&6exO0py*|RqF02vqFXyv&Q3sT zJ@f0XZwo~yWks)cDzmSw=*>>W?YD%YnT`)dZ`q;fZ95dbV~3)5?NIcd9g5z!L(vCz zDEiP2MIYG|eJoJ)i9pe(0!5z*6wMMS`dpys3xT590!3d66n!O7^tC|IHv&c93KV@O zQ1rb((GLPeKMEB6BvACTK+!J(MZXFZ{U+2Ez22$vW&%=sBLB9JH$u@;Wg5SCDzmSw z=`>Iv4n?I+QB|O*S)izs zKv9c8QL8{vXMv(NfueSSqMATa7lER#0!7^fineEtYUs=(7Eye10hNAf$ABq;RL(zhE zC|bx4MGM=ZXc0RUEoz6N#q3bDxE+d?uqj$nplB(9qNN3j`U?~-BTzIzplF~#(Xs+X zg9M6}6DV3*)I~1+!_)s*=4n^zPp=h`ribmL>XrvvA*0)2^ zC_5BwV27d&ZHhJ$DB4({XcK{=O$CZJ6DZnTplGx}(G~(lTM86yB~Y}rK+!e=MPmet zwiPJaPM~OefubD*ipB~Q?I=*RlR(kV0!6zBbwxv4D%T|-wU_dXWY-QwYvkV$vTIA3 zePu;^wiM6Z8;bUFd??!64n_Oep=e(_6pgb((SCL)+TRXE2iT$LKsyv2WK(poK+$-C zqC*6V4izXmOrYp+fubV>ijEX0I!d7EXn~?*1d5IoC^}A{=y-vm69kGT2o#+tP;`<& z(a8curw9~H6ev1Xs4LpNrSe?@Qk%C=g0n{`dO7{S;qTY2o&8a)D@l4 zQduqmslAx*P@fr!`sarrZ)+*DudL{7*bYV0ZHgWdD0)<&=rMt!#|4U>5GZ<5py(-qqNfFlo)IW|R-ouPfuiRH zie3;Xnjuj1KY^kb1&Ur0D0*3-=oNvYR|Se*6DWFJs4KdorE+)zQkyG3>Ud`;>Yl$b zz0p!;Us=)HEyYFCL(w~q4@K|Vq3At36uobUq7Up)^r0P!KC(m6$95?C#12KD+7x{z zP&7-R=yQRhF9eEa3lx1RQ1q2R(bob+-v|_aD^T>EK+*RCML!4>{U}iMlR(kW0!6)T9f~S;C~C4pQDKLoj&>+2?NC&;Ls7FGiaOa8wFnfo3KVq~C~6ZZY8NP~2^4h^ zDC#Ou)J>qMyFgJ7fucDCih2qZ^%5wWQ=q7~K+#+RMRN-j%_C6MN1$k4fug=bUC}=+ zmFi7@ zqP1Jg>?=XWVpFuK zK+$FbMVkv0jTR`{LZE0%fugMhinbOg+D4#gj6l)00!7;i6m2h1w1Ys=Sb?G)1&VeO zDB4+|XcvK^T?LAE6DZnUs4H5xwQ^1ZQhOr*C7;7W(V%?Vzej7CePu=av=(hA zd?*@chob%LP_(}tiVm-)12iu`&yd8=Tu_-!Kpy)7xqQeD>ju0q1QlRK4 zfuf@YijEN|I#!_QIDw+$1&U4(D4HNpbfQ4fNdiSD3lyCqP&84X=v0BC(*%l67brSI zs4Lp5wenU1QrjcH?t1S~^iWoGW^0*!Wku(-7Joh$iY7Zg6rF2_qVw!fbiN&mrr4qA z0y`94XosSyb||{Y4n-H+6kQ@vbg4kmWdcQ)3lv=;P;{k0(KLags|1R!7AU$#py*nG zqU!{Tt`{h}L7?bHfufrPif$Gtx<#PqR)M111d47KD7r(aD>}Qi()anK=-B+a>q()g zF+VkXXKR^#WkvV47HiB1MfW*A6y0x!q6h3y^q?Jz9`?Tm9f}^a zDSBL>=m~+MCk2Y05-56Fpy(NaqGtt)o)ai~UZCg&fub1#MgJ2hdQqV0C4r)s1&Uq~ zD0)?(=rw_&*9D5+5GZ<6plGI0S9Eu4W#wts%=?4D56lwbJxR%@AkWkv6`7AL+K zir#m8DEhz-MIYLs=p#E6eQbxKPwY_isU3<@0AAzEI1&aC#6!jA*nopo;exa_Yp>ySj1f=$K z{`S+@xqgmzefKmL=v-!BSEa76fG-IG)SOmIf0_(1&US>C|XgVXeEK7l?94c5hz+!plCILqSXb8 z1`8CeAy70#plD5jqO}Byh6)s|El{+MK+(EFUC~0FD=Q=*wNLWN{lcMW*&b;O>s)4E zS<%SO#TIXbqV*jgibmO?XahSGZD@z0jqFggu^oywu|v_Ob|~7+4n>>W6pa=r+Crdc zOM#-T1d6s6DB4D#XpBJ7wgN@l2^4KFP_%-VQ~F*rDi9I}{yehoZx6ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C* z;{}RN5Ga};P;{a|(MbYDCkqsvB2Y9@py*VAqSFM5P8TRTL!jtPfugeniq015iuUbX zc{~BBy_A25jSEFbx1}+ubD4c*Mdx)cK7BhBo$vTiG{p`@7uccbLOT>qwL{TGb||{o z4n>#Pq3BXO6kTRhbh$v$6#_+93KUHfD7s3Z=xTwYYXpj}6)3t+py+ymq8kK?ZWJiG zNucOvfudUkif$Dsx=or59w?okrb|`w%rsyew zqNfFlo)IW|R-ouPfuiRHie3;Xnjuj1KY^kb1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;O zqBjMKW(pL&B~bLXK+!uwUD17=D;p#rwSoE1yS_gZ&6DpWz1z9WzOteZI~U_V2t^+` zJ`{ayhoVpHQ1q!CiaxVL(JVU@eQt-MFYHh>+YUuv+7x{yQ1rDx(KiA`-wG6cCs6dg zK+z8ZML!A@{UlKIvp~@=0!6x3Kab%Q1rJz(LVx3{|Xd!Xp0kb ziW-EvqW3#j&P_mSujUuYeh`W_$xnwgww2jeR@AYrxcj3}R60HsRqasJY=@#wb|`AG zLs6?8iaOh&sLc*V?RF@t*%WmVDC#Ou)J>qMyFgJ7fucDCih2qZ^%5wWQ=q7~K+#+R zMRN-j%_C6MN1$k4fug1( zik1^7T3(=N1%aX!1&US@C|X&dXcd8?RRxMx6DV3;plGl_(Ha6pLj;P}6ewCtplGN- z(b@t<>j)IBD^N5{plCgTqTxba(V}gY`94jGmdt+&)?%S(_;%=wLe(jkiP5A$BM_ z)DA_5*`ergI}{yZhoU3xP;`_{(a{1$#|RW1D^PTtK+*96MJEUpO%NzLQK0A~fufTI zicS$InkZ0oszA|c0!60_6rCYZbf!SjSpr383lvQfC^|==XtGdOw0~RWrUaz6X#VrA z4+uqP{ddCFR%TyW(FJYA|Go@G7dk!^O|?VOMRq8<*bYUP*rDiBI}}}JhoZ~vP;`YI zimtRNnkGFXmq5|o0!8--6x}OObe~XHbbedqrv#+-ap$CHN+?>ZF^&7%%IqsEdbq9V z@l7b2?)Xsjh#iU^wL{Tkb|`w>4nvjRoW2^2jqQ1pU8 z(F}p2{|OYmC{Xm0K+($rMXv}Hy(&=jnn2O(0!42K6ul`>G*h7HErFu91&ZDgD0)|* z=skg=_l3Hm2iqzuB_OpSeG{CALeZ9$G(Ko6v#+e^leS{3??Tb1jt@nj*`a8b9g04; zL(vy@D4K1DqA%@G^pzcozP3ZrH#SAz3KV@OQ1rb((GLPeKMEB6BvACTK+!J(MZXFZ z{U%WKyFk$&0!4oc6#XSo^tV9KKLSPn3KVr{kJEOF8U%_O1&S&HMNL9o(MN5SqZ5$Y z1S@Pl2Ld0!4EQ6!jJ;noFQ)Zh@kC1d93y6wND8)K{RWpFq)k z0!8x+6fGc7w4gxILIOn#3luFPP_(E}S5&rFo=iY$zvqXmtL^nO{g3iPkc+jK*;iJy zRC_V&r%<%C<3mw@I}|NrhoS*?C>m&oqGjz+G{_D`%h{o5c{>!XU{kcBK+#G9MJo#w zts+pgszA|d0!6C}6b%+AT0@{{h(OVr0!3>H6b%(9T3euK9f6{C1&W3V6s;#vG+dx) zgh0_qfui+=x}qi8E3H2#MZ0H3ONOE=^S$d)?Pd0r6>Z#JEct6F+QjjpXj3~BZDxm} z&FxS$+73lq*r8}kI}~kYhoY_RP_&Ir(HMcEZ3T+96DZnVplAnyqOk%+I|>x-Bv7=o zK+!G&MY{?V?IuvPyFk$%0!4cY6zwHYw6{RfJ_1Gi3KWeKDB4e;Xn&!uXv6l(MhQsm zhy22{jY82P`LzFl_A>j*ipIAW`~Mz_4sm=aI@AtDhuNX%a61$oVTYn4?ND@-9g2>& zL(wsIC_2`r=s1C*;{}RN5Ga};P;{a|(MbYDCkqsvB2Y9@py*VAqSFM5P8TRTL!jtP zfugenip~}&nj}zkjzH05fueH-ip~=#I$x+OI;g#JegaaPnSY2K9Eu*xil(%e*;iI{ zQG0RkpP}et$A_Xz>`-*69f~fqL(%1SD7wN9MOWIPXqp|0uChbX)iy=f2ozl_P;{L@ z(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS6x}IMbeBNU-2z4T2o&8bP;{R_ z(ftBN4+s=JDAW~Q*j{-r0jUj0vzQu+rsiir9%?VMudL|N_Tt~aL(yZ74@HmLq38)a z6g_E&qNnUo^t2s{p0PvGvvw$Y&JIP-+Z4SZP&7lJ=zju5FA5aBBvACSK+!7#MXw4J zy(Uofx?wplDu!qP_w}{RE2U6DXQrplAVsq6Gzt77{30 zSfFSTfucnPiWU}7K0#ds#-xX@9)z9=BGpQwOW%iX7EmJFAY6?XI z93P4X+M#G!I}{DFL(y_}C|ceQMJw2$Xhk~|tz?Iym2HYv5hz+!plCILqSXb81`8Ce zAy70#plD5jqO}Byh6)s|El{+MK+(DaMZ*M&))OciE>JW=plGB((fR^KqXddJ5GdME zs4H5!R{13XshyCYN9!MocF51hZd5C?udHaZTG6u%MVmW56pgk+(H3?n+R_e1TiKy# zYdaKeV~3(Kb|~7`4n^D96m2h1w1Ys=Sb?G)1&VeODB4+|XcvK^T?LAE6DZnUplA<) zqCEwQ_7W)CTcBtkfuel{ipB{P?I%#Qzd+Fe0!0T36dfeg6>Uj*rDiHI}{yfhoa-{P;`P# z(FB2_69tM+5-2)Zpy(8VqKN`UrwSCECQx*`K+zcjMP~{Woh49owm{J&fueH+iY5yb zohwjuogzO_TqcXlZH-VQ}S*rDi0I~4t7 zQ}nYy(Jul;zX}xnCQ$UdK+zupMSltu{UuQJw?NT90!9A{6m{qlr|lFq2oyC66jcO@ zngogpfufEAMWsMdRiLO@ps15jSM+(UvPl9`J0ib&|BFy`PkymcOP4bH%8J^%6bE(< zMK#BVqAqqQ>S~9gZgwc@Zik{Cb|{*|4n;lfP}Iu~MRVE|^%f|aOQ2|OfueZ?iuwo? z%_~sUSD>h$K+${xMe_?3Eg(>|pg_?=0!0f86fGi9w5UMQVgf~r3luFOP_(2#(NY3M zOAB>Hox4;nNI+^=7YR;Vm-?Chz4=kc{$0xKD=S*IOL2eqP&CN#p=dcf6fJLuq802= zw4xn~RIf+S2i%Xe&DuZEc65ZR}7q#tuc>+M#GWI}~kihoT+q zP&C%2Xh(sfodk+@7AV?9plDZtqTK|Fb{8nxL!f9+fug+xiuM*L+DD*hUxA`=0!8}? z6zwlibbvt7fdWMb2^1YHP&8hk=n$c zb><93M>#$e9c_oAW9(3LtR0GuvqRDGb|^Z*4n-5}P;{alicYdAI$5CT6oI0N0!60^ z6rCnebh<#%83ILT3KX3sP;|CH(IkPQa|DVe3lyCzP;{O^(fI;JQv`}G5GcA(plGT< z(M1A97YlVohj*#$nSj))`BBFsLeby(4>P)?OPPITMOSnwPMa$fUFrBxG|di0SJ|QH zYC9BNV~3(^?ND@`9g42EL(vU(D7w+6=q7=pn+1w)5h%Jum+K7pe91&SUJD0)z!=plikhXsnJ3lu#fQ1qxk(PKhg(PdpKwXy8OMjBXYEk*oE?guw?okjb|{)*hob-4q3A_B z6uo4JqL*!oUJ)pIRiNlKfuh$1irx??dQ+fira;kK0!42N6ul!*^sYeBdjdu83lx1I zQ1qcd(MJMB9}5(HB2e_HK+$IcMY9BoJ{RhWp6pWjEdi-boGZb3Dilr3zpL?!F8?2K z?*Si0^|t-b?CxYYB!m=p1B8+gI;7L3WV1=gX46Qai7o*`lbQqsL_w;61w=&z0mWWH z!CsIe*io^f0v1q21O$xzz3(~qwb`J*^8DZD{rp##d#-EFIdkUBcg~zSv%9e~Urf;t zQAYE4q39Iy3q?Od3q_})g`zXiLeW`hq39=Qq39g6P;?$zD7pYG6#Wbhit1p1qF-Qu zqF-TvqTgVEqTgYFqCa4OqCa7PqQ78(A}v~O+d+{I0~A?cfFdglP-KGviVPT_C!2m_!FhEgb7>c6rqpSl6kjT!_1kOpJ=rBJHiHNo{UrbSS zwBc_n6vZIFP}CG!C~`szMJ{NeC>B~MY6dM7HHQ|8T0jd$anM3hOK4Ek3I-@@4FeRl zfdPu*VSu6p7@(*v3{aE^0~ED`0gBqg07V^OfTE5tKv5?cpr|tpP}BtmDC!CW6m^3E zijrV}qGTALCH{ql^@SFSE`b(``augt{h@`T0nkFxKxm;T6Iv*8LxZ9$7@)`l0~BS$ z07W@4Kv6CXP&5bzD9VEYio7sDQ9cY%+1wa9^I#~7Mnqd9I}$|~_;c5n3Pt<*Ta8yo+nFz>=-Ox_t+P1}It!0~Fm30~D=;0gCQ`0gBec07V;M zfTBBLfTE2sK+z@`plCA;P;?gzMbZ3d>ktAY@*a}L0-};lPz=%bXUc_bP#mc`upi9=&qv=(qYhD z9Ur0Npu705*|*bO{O8C!=`Q|z(%p0y|3TnX-Nk>=wY%=(Kgro!ck$m;?5Df<=y6)m%c&yc3{1bh%br=7}+C1IGKa#aTck!vb3ZP{b_;Uwu>Mnk8d_Z^c zlfQ$yiyz&5th;#b{WIOglcz^?7telut-E;o;#=Lt_n#+q7vDgf)?GXTJg2+(5?-gf zxDWna*BbGOV%(!nx!5i(>0oAr#n|bf((BtsBscWW(6wgnL|)UmBdwv?67$vU9G!1^ z#z6K;$;qO3v#GRJ&lpBTY46bcdG<~?*{kMsm(kffC=IywaJt8<=8yccm>D^*a1bID8Piyf8i(X1JH)2Wj zj^G-7Ln%Mt)W>P3^*)mNiq<6hidakigMNvKjV$_!DCC;-7m>!zF+hZkiqr>+_<_0^ zJyVIe&9qT&zVu|Bpf54P2bW!%+EO1J61Dd2UpCHesh1kzCCi_i+)^(Ki8}h)(Oc(g zaVIHHKIO?(c`S~bw75UX8%o|B<%L8&@yw}3*HA%5`0J-0Ei}t1%uH`Zd-eu+Tmc= zM|zrdD0}M`+K*D&qi64aV7{68))(K~I!B8Op;qO#n}R%beXhUM+~DGezCAI=toX!P zndUx6z4X9CGpLS~h3mK(S>Acf)z{oi_fN8>nw$A~>#xsKUTUWG2Oqv%i@RI4@`1_{ z5_SEDKXZ-f5dHS`<{ej?nGT)$_D-&w5&qi7ye3+!XDHJ(yk8rws-e!R+!jZ^7Ppl= zu0)4awXadf7wn&87Wn1jx=*e$3;b^Jr>khG%!pe4tL>D>JXjw~fgY9FEbxRB zI9qukQC}}Qe9Jtu#AOTK+NGLr&9NufkVjPYWHx;?eE@}zIARN3st2&04(l_3o#+7Do8; zV?D;0l}P>LuKrrwE;?nnDY~SYO%W2c>766*QbyVx~xf!)@lJ|F?alWTHyLVhP-n+ zzC6&(d->9Nv1Zs*{_^qaO@sjL@hNcdR+OWxf_SO!7F>h3(SP_qv`spuJmYeLnu90t6HTGiCS`M$2-K&U^*~noj#fIVhp7> z+i@u+UP+1XMd4%iR<$ zV|8vn_CQP*GtWn7mh7i)>Ql+nm^Nj0ZFj%oX=dhm?bMD38FM4*j?*Xd%sfBb`S>q$ zwAQ~%9y9${6@5pV>34r})6%(S`u7g+n@;JC@RsL(>PVgY74e$J?+}YMq|GtP%CqvX&DLf$=Z!Qof@)-meL9Ppvw8Qwdo6-JZmGEC3w1gaX)#<%%M}ZC z&C+aj7F|MH(F%=MXj*HeAtI8sfzA6hpBiD-gzBy}eDN?u*Gf3tL8#cYpY)PVymU9c zX$1!!)Tk9fd3Cx#HFy<~(zU@HmQru8YZV;ws88X%gE#R~Hy-O~6&$d&!RFQ;Ft;|C z!)bb}9K2)>sI-a(TlxnP4}^0o_2QS+vwm9Cy-N*M@N5i=I`R zHE$Cyw52!sUFc-ZqPIm$+r)7{y~*al%}=|FBhLlyqAGk%Z(ioe9krp&)Y95*;>A%) z>Lht_v?*(NE$_uHdUM7T6xAN323n6Q!>L!j{i4d*l>hh45K`^9lVi@>> zgmt`pxv6`ZX?b}Zy$!8rjn;A#FWyX>NAmi{t*;6VwyB!@q9&6US2y?-tna3=wN-nM zvRL%rA{x^^n0vv;Bsn>yx-w;4&GeL->M<$R{+cmW{^`}zYOBW7R*g*=Q$1&T?KC#V zRE?ckT~!mbj?+`>J}J|yCr+7IJ8@Q(mNH@5l&X}<$yKvck|$3aQ#m=MWa$+iC4In%3Zk|!{`1j5*f zQ)@}ksF?8ckC`@Q%CxEe%IOoyBdp6jIeu!CF&@(=kIp~fIgvM|EX~mAN3z+Aj5hTE&0^D? zMi_@CMgj-&O_@x|(~UMHW8!Hs)kxqRW{SjrlOZ}J#^{n{L?;?Ct;`KZhd2WZsc~fW zH`KOMC^l^^X}EF;K`YG4hBP&zy9FnBO;Yri-RN($rb;>DjnEKl<9@7^71gqkTIgwj~)UQc8+hN@$3*(7(>#oHyz-V!fO> zg|o#ZbTdK|4Oc66Xdhf8X(7gNCDB5HPfG3|sBc>;B0Sz`k!pnJ8I41%-IHUC7UVUi zeTkE(^Z=tXYdH!rYNtBOPMI>9a-|!sIF-+c^OB-UjhAA4X0e?UjTWtVg=|E2@n4sQ zI{b6|Z|l?|B-V)QY;@{q#98OWo7?~A0{aJcUhQ;S-an@y_3IS8w_HrRN=|#zhE&3E zk}*lN)Zgetjo+d*E&g{U1X^1)Q{xcCg8#DBTZFibxGqNH_C{PBZ8aru@Gjm@wO=Vl z=w`-+sQ?sGQ^BpB?5io`4O7M&0eIUfl8CuB4A$_Az)CR$EJCVrKOAkMA_%F@ZB+}& zY4YzFh%qwS7@gZ087+;t;KPT4Efq9h9(17oGnR6k|3B8~BF6vk3yUN05)5jQxRyaj z54-mtTZrq^qJK&P{YU>3(G|Xt- z*4ikUbfe@D>!f_M%Z?(TxNEGBQvFyyMD*)u0+uN$FP%iK>GbSHT|=8zBvXuDl)Fv* zzgbkpr^sf6TPeO=3Q;mZ)mCUk@q)st1Sz0IL8!dT3^@0|v zWglyYVMfNV1Zr~veMT~Y&@{=2OEX%eq*&*2TXUDdjdpQc1H6m<|9Ge~sJKo&>iaR) zaq6gEwAdn*s>1!!#oPF|U6R?y#j75Vi*2WNfXd(wopx0153UX=MhB`uBp)rl47x+C z5xUXZIyc@rJDz%fMl#iKXBY$GjSkkZcv?jx1U|?EC_SgFQ3tx=A;qEn?_<19Jx)`@ z-PUl1w5CPs*_;F-_d-tET00IzRX?glqj>9_WTUyY4KX_^->iRgO4@<*G^ez@L(S1| zx1j@0(01p*1#pa~)#;S1X*XI(ko5nPd`WHo#~GPB-l!S5tF%yMO+ghfBURdrR1u~5 z-xU4_DY2$Oc9?(5esOW4si9QyN=tUyA=6EvANipzS}z}FI3<~nqq=}tLXrbEoiE>C zZOPRCpAI*09sRE_H8M~L9{u2wg$VvtY)e;q)gR~~H14E*C0hQ~IN^WiDoq*54D;lqLtv&b1s@7lk|ac#R8uyo+A5{d zm!ow89U@-9MU5sFZI)pn))v&u@{K^6c{L4j8m-krQ=@fjYS#qX^VUhckRsP>+2en{ zfa*PsNbBx-`FxxAqBWk!71rg~^i#w7PBdWQL2kpV)#R6xY%D%Tr@~4%^BoRb9?dvDLmz66_npoTv$?& zQ%)%>ioB98*OTWTU7yfhn(Z$tE~mt0Ii=+}*?~3rB~)ldQCUSvNinbRmw1Qe6!>$C zOAFoQYKv4(zlzKT?ZgE9X zwwbI~?>sa1X;975oU)Q)s-Y^WJEcKeaNToC-DN>FN4pi44f1DIR9 zGjAccrkRFYGAlK>qTV8Z1vcDADwmeqAc?1Rcu9FN?Q%hZzogh(RGuTdoG$6z6lszp zBi&zX?m>2g>{$gg!%>=R9)_GEH_2?RIJeC2&Q`_rFjI5Qa)Wj}r#uhs>o3V0?x$m2 zNJrV@F83A}sdnlU$e88{%IPf~?9U>`vb|+$V`xiNBo}5LHh+P)$QNj}q264t-(6zX z(o-O?lj$a6OG^)&;B=~M#WQQOD{CwLs$8dN9-LPTMkfK8+TTmm0LJxc-{O*MPt}>4Zyj3UbVjnltA# zgi0NDZU8#6-dxo}YAZd1wqkZde5AO$GcRpY%LWjk2k^T+o{CbpNBXlsee&p{H`Gl# zTJ9~(p+lw(Ep?Za&?Sx!P2e)nJHUV^s0Jl;1j|Z2M48)D?j548NIiotgg9mC(mkli zylk6ol|e~(!QG(i5AHYW`?Iv1z;WfpK)nSMB7=H>3b`0kHR}`5Mzc!Ybio(Ec#Cwn zf=@7NJ9Nec#bxCh@3XfkJ7-w^p3|{W&6PJ<+922gYQ-gP(Q_%Gx zQ1R^aY`JKb=1^mn2KUf`gX}SfN5T!Y;?(g~{;H{CCst1N^9dFx%v(^9Gss;a=OK*) zvZ+_7zYv-yLExGdbfnXIH#iLhmpm#dXc(4_-J*kg5f@(WAf>$j&F6u5oM=7=!chz! zzfi|xb{J;62Tr@R9t~=UlNAL74JBxRM?J^5nN!E4W~6Ej`25GqYCWC>*~Mm$9=M7L zO6tf{2Ped&rODNjMh}7GgnlN~pFOzTpPi=$5DiBgJ%iFqA6ZDfU`45UT{QdQTx$2S zyr9bgPLTrla2~tL1wUvfyJu*@s=L&-!5I)Zl`gv00Is0XcLAMh^>|_HgWQFM?)t40 z@HDtXb5Mt1ZnSq$3z_f@DyoS0^yw4Nk7<+B;`u>sYVY*!@tvxxCRbI~RCSI|nlfhk z%>HAhRo7O{PMVUDK}PL_nNvnn95;DdWo;5YMAs zdN`BbhC}w6eJO#=+p zqfD1N>U+v*$jjr0Kmr_2^WLofDAOtDq0vZ|n{L>o^XB@~y@uM4UiAl-Mj6U$cw@x3 zEj&o^(tU{<&Zq`3DV$g^ZQArS%?#;(t4o8?L4y%^A(fO>JnU~dJOy-}q02e@tdh^FA##UFsd^+e7Vx6VO5Mo%eQ-9Mr(s$b73ED5?P^zbxA@a2j3CitEfjXMkx}3%zzn`&|2MaWx!&C3hWD-YOl7-0=EoGu>0=Fn@&ogzf=`h^ za<$hLMeZTgc6?hNSQFH~?h3l;r@>$FO+F9S&~%EYL3G2UMoxhhCd52sE-vCO!W<5y z{oA#2I?)}Z9QFDe$AzDg_J|4Iabq7kLivkxc-QLjZ%IVXq#y05v zc>E=srs1_LrP1w3pxQwVQ&L)-=cOA~IzmM>ET;(&)Wjr*>&NtXX?#3_81eh*V>tEG zF=;fwrwy1lIe|MJ6u{kFFnRF7Pp&(g=8i79DL2{Rtq!8IAuzP5zg^3g%V!$h++f$J zaRRl*2tD{*Fv0eiEr>dB-7dPkyUTbUFE9l}r&gfQzzw83%bd{*tO#nz(wy>t9LAg7 zChqjPChES>tP>4!Xdh4~y3M8AN3X|gUW-cHbSW}Z(FH{<&}rKsxtiqkaU<#Hfl^MP|Bk@Hnbr1C$h-*j8e<`l4wq$j62bKTsg@O$&An%O!3VywvrczBMwuf`2!!)|~_bu_Tap(zrY&Q*gtvmQJbZZ4=9{zCUK zzo)2NE;qpw+-BAOe(_ZIWZ2KZM4(w@{Y-fp&D#a_GC@6DU~Hmp>rqf(!hlN*G-EJt zfje$#TXPcI+$=it`m39ok>-_r|7RxR=~-;dyd2Z9CvH7-n*H&4~`o2$AA|w()6p0C8nt%y&2Ng#j-(_P=P>? z9cZwij*IUbkr10upa-s@<{kx4yP6>U(cP0{g)d~# zF>N@r8+89epqR}}7wx|zg`J@8jxJ0x=9kAjxN+*$AR}_nkd^4prcp`Ia0M#^vyixK zs+$tCZFv6Gys?t|A9qy^jhuK4RW`H!IvmVFg9kaX#}!4sqT->dL2wJiPXc%o>iz;v zltuI2^i6Lqg))`_lt z(z@yb!KNDhW0NInNKF%Tfp#!Cq3$DKcnY%{+-?%*IA(#P7Ytf`uglZn!OyKwUA5b) zigFS*9O~B>L625397COP4^~!DMo-J+9{6uFl{`s#(G!v236#_Z(<$|LhxBA#9=37y z_%0=I^Mvj5#ooM%{nPy`v%~P==8H?om3>U3Ij%sfqAk?4XV3=?)E$G_IKhKY^VV)C zJv`>e=f(0o7*$f!`uyOG>Z60DPDS&nP~hkcb<^!Ny3&hs^1KgUK~?+IPlobr zVjw9V?U*-mgG%|f`J(1+aO=oCnbqd|8We)6dE6dq>0G}#0x%z8;lmPqt0S`to+)G1 zeyfR8Zi3)j97Rsh*o1GUR0f_pB2umUY>gt?WrgLK{|+|)b@!pnmHhoL zO;4dkqjyqaGTl}bX(3Ve!cc1?N3^Y}?$l$g&GhDa3q4M6skgSY)#(Qj{`LyCY}%Q> zf)iNzYf3>ct9-oJucG3Sm4F$hXfSuH!Y97NLOE^7hI(A zZ7}ocV!K+c9i8>&bAg8A;)a*He|Y*DoFFaeTA2Fxr)`194*a+=IA1!|Z3Dd<(U+{h zqm2>^|c&nJ^zYFqd5L88@1j-3~{d6FOAIIE*e~Ts{z8uQ$K|(5{7_<@L?+lmCk^)x7Q%^%<4C_m zV@4`Mvk(Xg9BE}I@%g;xbUh{ZmzX87L?VBMo70VvI7#9RiSs2cmbgmdT@s&^_^ia2 zCGM5@hQxOzekAd8iC;&br!izEGzkQrkn@-H5<-$r74iCrbq z?_ikgdr9ms(Ie3-u~;Jiwhxzgsl-Z&<0Vd!SR-+c#Q74JNL(p#wM71XATIY#iCZK- zDDiQLJ0$XN2XXpWB<_>=w!{x4ekPHBTZq%2ka$L7okY68nCtmRX*gYDiA^QONo*^z zv&2-1y(A8hm?N=3VwuDd5-TN6kT^}^EQwc3Tr6>=#G56qlek&p{SqIOxI^L#5_d~{ zUE;eEKbCk{;xUOoNIWO;H;ESN2e^GgB}Ph&mDpNhdx_m7W=QNS(Je7gVzI;_5-*cD zR^k;Bt0m5nxIp4Ei8o5TRpJJTTO>Xtaht?vB)%;1Rf%s&s~cA%etWSt>#GL1c0&yn~9jcHiFEU}KpKCBHI zV{jbMMn#{*#R*EUmiT(2(jQ5T?4Wcji9=|B!R3sRxS@;E4@&&9o6_h_*PTxb~ z)HJ29lDIuX=~pEFN&{d{Z>NC^$IRX;7D`;&SLrnp-|VOKClaFvD&0onFt^fG5;uC3 zepuqyIZB_A*dG>H%FRC%lvEXf` zhfBQqfYO^Je*B)&-$-ozfzn+ij{QjK84@4*MCqp`o<5}X9};_hp|nThydz34m$>Uo zrQeb0_(o}`#G>O$Un=pI@07kv;-}v$eOzMvDW#JnjytV%jl@UJD*dd)v-ESVe0=_r z*!yRtb0l8#i_$A4?x7njPXDgNMt>?DE3t&;czFF~5^u98y+z_@Hl@Fl*p_b4IDLx5 z386~Ql=v9^5G=2MUg9~rkz=h#sMt4B#X%AmL@RxR#8>IZVmbZ$62s|NV_7$sSV}j7 zto;&ik5l?yiC@qU%JTZ}CAN!KI!)pvnsDItS4!O4PU#mVUZ7tg<@MH%D)#HFqF3VG z^jprn{&9)VaWpjTHPHt-M$pd`OZ;5?Z$+P!ct-r+MQceapTUvJj}+ZhVsr7^iS8sZ zN&McT`$=?*Um&_fVukplM30p?QT$mF7fHNP*552~t@!sy+$QlQiEl{!SmHMl&r1A@ zBehosO-6DYByq09MG~Kq_`1YDCEDo+OgY~r5~oVMOX7zT4@>+>Vn_NhP|lYsFb}i<$0VMRNZqFC*GZ&q&(zetnK43Qv_x~>iQ0#{6LY;e??jrq15;Bon$ethB7dN0 zbKZ&cWundbCDIc_PnI}K;#`T>N;Kz}DE)fTnk~mS~bcsBV%iEnNae>6^ zBwjCZt;F>b@00kDM00+K%6V4wD-!og{6^w;63<9HFHyIudKeNLON^4(N@9Y30xlYgz`qv zGV;)(wqt;k^5dObGrGNx;6?sAGD79>fr4*U9HmbcG<^vuL{aTi`rr8?BaPr zUf9-^q=U<=y@mc*26ujBXA5|J*Q zI(0slcp=>$GI$xUd6cdIf+BC1Upwg?+gmOWjdVGDVVSQR9;^Qir5xM zoGZNAc9l+lih+JInU;B1yv-myw6E#s@%b3xh4Q#bgVQ}i^*f406p>DTpt4VD z^0btAdZqPB?b$muy?1&aT24((3;MTb&+e>x_w3o5Q;uphKc^s9{VuC2Sf?joD3_gE z?lBepCJVnhY0aqzP5SP1@rwnEwjQk8Uio=l_pPqetwQuQnWt-(de2&{&fGn9i&LNS z?WuEA?y1|8da%xxrgi=8)8cb2u6)AxL{W<=d+M}=5$3;lnExJ{@=!i`X?yByGxpRS z8TFpz2%E5r+%5Ug;p;aS#F-w-v`(s=>cQVy;Hq@haSkTd$P<*aKXz{rP zj>C1o-_2|2z4>t6IbM#xnd-*sa(Yd$5f5X!@M|Io`Q>d+J)Q`s?RE|Dw2H zPu+pauO?n<(asE6T70fq^BP|*wE^Wmf5K`#zsAG4resX_PXC8oG3ORExq`PxH8?`s zY`H4)^zVzUXHJc=p5NkWnNgKL&O0uz;g&d0@#zUxYU8xb(;qJJ`wD4$M^e$Y!xB4B z$Sa`sj@m^jhWmEWI<&Gcp34f!E%#OAS9pg|jkHR3`0YD;gz9=Sb+E5g)&I<2wD)%; z7JEzbtY^J7oMu>JdI4|OLv{Xpse^oj^7FiT4NA@R<>n8f?{RbP%(J6wICqXOp0;ox zHJeJ=6R7tUCJzsr|9)@&+jSyS;|x&aJ{yxbablFYZx8aisPD{wJ5S=}H1Dpudm>{- zB~Dnc|9-Ie+|IJ({I4pLy~(~5bL*TtiMD%Byq=#ps`7{y>B?-}A|l>A9dzr0qwmux zeVx|($V#nu+cR&^jEVeYfZqBN-9aBg8Q-Pq{k4yG+PiyilOFk`?|Eb4bDM8??AL)$ zwYfi2*B5NI>I+(wKDA-k<^kD{H=pZVXMc6bI`4rcQ%0@qf62b45s$TdWmUK3jsKkg z{_v@`?5tn!`L+3%0}sSpy?ymFBO3ql!N$!GztDX^A)>mAR%$pi7-V7gG~4Vu^WV-_u(PXfYwB+A9^amPK2}-OS}zssqW0PopGa-G zQQ!SjX4S7|yS_y2`jYo0-^*sZ(z$8u)OfqIHMUddTg*!*v_(ruWVCUTEtXcE)C>8dMX7 z2{-fh7{k;>Fn1MptH{YK7+PfI<$^{$F>Kp(P=LtGpR>B8Sl+4&EyF$-_0Wz|3%1-$C9I-1^(ldVih72VJ1NyGzO$LsL-6v) zuY@P?61~|OMeh=NZ!JC@66QGbZJy)2ui4?cXYQi+YVtM5`PkVMBk3Ja@6^l-FJ^eo z{zk2!w6oHz3f2*AtiPe!9@)&! z9pvPljfu(1H$9UTKL0!y{2q2rre>Y}g^oB8aACelMAn60Ggud&%QA_`y0E#%&Fz|+ zp6|;|H<{80JpV4W{>TOGsSRV3eaS_)JPGwA`~N@2g77Sv`HXPd}TI!220E)3&KI zEo{+?zL)Y}@~ZRDbJk(DFQ+V}BWFu{&i7m)_pl$(GGDhfv-i(CYfs#fzumi+nBGfg zK-W=W6K+?%NJ-||CW(*c@2?CS6=NQ2Vxru0_DJTigok|h7apvnvy9F_8}$`O0;Lwn zHRW#Kmi#T=d-AB5qX(ZBl*U#3Ddy~la z`4^5@UZqxel{ljJbb4pfJCfcd^p2-@s=ofoGe#rr^q&j04o&VHS8%wl8TBR27S5pa zhU7fzAn(H7D86R2 z&fiZhy1(wgPD&R^%c(J-tBkKv(TRua$`_Q4q7qVvYrlQ)G4=UP?&#)?8O%#v^WHaO zc)=PomJROY>ttS!GS7yL8GIyn>7LlcWlgU+{&;-Px1LEI{_BsQAB{P>vFYM)x_Z*} zoJP{-wb*$f@9a(SGZzosF|k{R6zjHQkGbzUe{BEG_Dd%|wDkP7duaUU_sMoy%AKUYqz z`S*J7GyB5&F=oS&-~9_V`R-tP0wX9M`P~*6`Q6@N6_H zYAWw!>T2(5-_7Q>hb1mF$9qc}jQ3F13g3$SmEM&N%3AJQp1;Do!pwa!^-FzIsr>p8 zpE;i6kzUk;=D**W|8_RVbn|31H#$Gi6Pf({^B8AXVAP<|2yvE- zH_;^Oub*#tzWB5rht?l!?qja+eHjr9YukB3R>5wn-EMMn@^{lw#W)%*Fw8eRf4Fx< zgBCz*8i^HVYnFQ}d=+MU3_b4iCI9V+bq*Y{ZViqY#_EH7c{Hl_{^K_6iP`2hJlijG`1w+Gj-C;kw9e*x&xX0r>;G1J#jAbV#a?Db@G%L{7i< z{uR}mPDk!reel8dS8lv-LKi;2-n{I(;W48Yj_l}mKZ0@Z&A&|eZsIKOXwQxoE5G`o z?>67g+%8u>KP=*|(SLTl@xqfm!=8Bc?Gpn(&l~#1{q06Ref4e2hQFTBV`;lZ#%s%- zy)mRTHu~2c?j17j?cc7fGG|=h79ZYRvhw(ro!=dy^Lg?wZLS`+?cv3F&-cDM|IV>@ zXyN6PdJnDYvG1|g)4eM$ZQtd1tB%j;$A`SPb;1{aZF%MS{AZRAXz}8t=O%3qAL(A# zwPbXU%RhB^7CbbmdF70Sf6U!C?&X9>BThg5*z(6CS{`$@p=nlK3-vY1Z{!V=wrCX8 z7KiKNwx7QeJ%N+_9m3Rk$n`E5N78;3>t1Wk*vKR{`k+Aq*7l+*q@rE%F`rCG~Z`|L!T(zWvkhMU`8poVE-e~^~r?3<_+ zTiXAi_H1pZCt_L~dk8u4_9L{#1pBX4a$9@j2%46+hf+=2*%#7sdwVENI*qm8PmNk- zUro#V?ZqwW(W9L|?D)F9DNTdFVLw21d(*y<_V+D&Bij1gj+V6CO?P}p)k@MG{6Vo~ z-LaA86H|0Y8>&sJ?)Zrg!z$e|l3IMV?pR6{U86geQQO_3JNT1^x9W}$NZqD8o}*@4 zt2-X2Qf}8BnN*c^y2D57?$8~xsY>g0$8EG%=XA#nwDI%0qdm5gu+ZkWX}jW+ax#o?s7d~0>^N1ML0IyTVM;0dea0V?x*t0R@TJ85-zbPZQ+d7@gQxsz~*>?iY~M{dQz>6Y>uUL^owndu2fiw%`ui* zcd*ToOxr89ISMG0*&Nxly>go)f-+Rt967}35SybD9f6@XM=1d|%;tE6xEyYC?4ZI% z*c?T4lrOb8M$us#X>+tAcDC9aHB^bFhT~4!Bd6g=qL!F#I0~qh<`|9zRM=d@(Spp+ z49AaD=I4eZnHus7!!eMGK5RIaQ(cZ24i8oEsNpzDd;6u~7(;bAV0U~^Dc`j_3Mu=0 zc1I>{_IsUs0nGx%_glbkD>$sdY zTNCT}gHqPUIv%CQni=c(iVoGRSVsri!j-X(g+%P^SjVl@f^%XWMMUe|SVt_i(p9mJ zm#HP@#X3HqeYiT-kw+E0hVoG>&5w25LrE6II=&$$u8nn^qDo|La7?Dnx;HpJpu(~? zIHIU7*&7^vsFa)y4*twy?gmE;wcwx)j$zaiCA%F%Xx-r5j@?w|s1uGi=?thm;qX&+ zN1t%;hjz!DaNI=uF!qFFEm2o>!ZC>UVcZGF7^?O76QS?Yy6I8W*M3SnGlLfzQQm4^ zxStMt4KJionp$2k2*a7Ya2qw_EMB;aN?FjG7Q(4TujPg1RL(+Pc$XSt5icBXOJ9TF zg`;#_m+->Flz1sGd_#3v#tWxtM_2o4p_CSG=7nOa?HXQ~PCIxDFPx_RzLggS(I)1M zp@k*XbaQ#ZO65?OsfB(=$B_R#S!gSQz`TYmq^y zK}W*Q3$4j<@WM9QRwyq#MF*l0FLb4n!+2pArQv~XXePBa{nahXPMuH$FYuQ%n()Ft zN*u`x*HM}%URXhgm#;~oC#c0@c%g`#ro3>H&K)N&@Mm+m)}iTi2k zn@NY=ME|7HF%6$b3-m_?^pM$fs2khZkFXgXjQ+$}ldM$D=;&Hco=tBoA%}5s6jAU=kND&!JvX5q@ zigb}oqiUszcCw~=rHgLLnktqdI)*jXth?xF)>O3~qN7+--Fk|SWKEUpCAtY~s$Fl< z5v-|teMC2AP4(+5I-GPm)$bC~VXUcs{X{onP4(+9I+QilZ-8hAYpUNs(RS8Uzf92~ ztf_u((FSX(UzTVaYpS0|G<`EHE1l|>E!skwzU*Y=h}KzC{c=Uqv5vGE?W}$}{!tqU zC!>8+1|aGc>JyAX_WlG76XG-cgqTT4fn*gz3PlPbMIwceVv#~fiAW)2ut*`KRHP76 zCQ=9~7b%2Phy)=+M1zo_qCv_&Gzhs=Gzb|f8iZUX8iZUf8ie>ogOE|8 zK}e-&5Heac2pJ<9gp3spLaIcAka40x$av8pWP)fAGEp=LnIsy7Tp?N!;lA$n~N@$PJ=F$c>^w$W5X_$STo_kg3)!bo`^n zk}{?#LTFxAGgjM~946#eV+&n=O+s#ytU}0IkwVDrB88B3B88AUL<%A6MG7GsL<%8y ziWEXNiWEXNi3A~=MT3yLM1zpKMT3wnqCv<#qCv>LqCv=gqCv?0qCv<5qCv=mqCv<* zqCv>RqCvxqCv=3(I8}-Xb|#*Xb|$GXb`epGzi%tS`o6wx|fcB zR682j7`G@wvT0~!JY{Ecn2_g;y)1|jc@1|bJUgOCqIgOCqJgOHCzgOHC!gOE=|gOE=}D?*;J z9;f3Ub&3Y?#4%wL;CgiYjobDS;LXJpQA>^n?A>>PuLdaJlg^;gB3L)Q! z6he-P6he-R6hgigDTI6{5`>%(4MM&b4MI+e1|dI)1|g?JgODFZgOJmrLC6`=AmprQ z5b~2~5OPj52stkrgj^5}LVgwvLh3|=kY7ZDkY7cEkl#dukl#gvkUvC&kUvF(kiSGL zLO!=PA~>S1p_?M(3zLxOrMyhDXpD{)V>4_z-H6Z~7vIeoy5w#{nufh0(5*?+u-p#a ziZl(&9ndXF)37`gI*v3A%Ns$rAWg&aFzDu_X;>Z(-HbF1%Ns+-lBQvK1hk7Z-`6yO z;benq7zv{(8&t(87%^;69iw4Hvq6=Nff2<9)v_s!NH(aNP8dztpnAGsM6f{>jfK&e z4XSA~7~y2_9Zqu?VQf%MTfk_<2GukUMkpIp)0QwCY*0;G!LYMIHEj(egbk``8yE%~ zRMU7EHa4iH2{5c|P)*yyu#my`I*BlJHmIiUU=Scqn_WZTNG}U0V z*X@iKQ`A{EW>D8-Qq%?cg`%#|LQywpp(qJjC`yJFic+A3qEu+1C=FUDN{1GTGN3_G zcNn0k2Mkcu69y>i1p^fIh5?HDzyL*kVSu7bV1S~2FhEg%7@%kX3{W%>1}Mse0gBu( zKv5P9P~?FDin3vVq8u2YC>I7O8UzCr<-q_&UKom^j=J?W0wlT@Pcn59iq_D4j*+k1 znJ=cONH?A)uuO`IkzXh(ffkAeLkmTv&_Yoev`|zIEfiHi3q?bqg`%O*LeVg2P&6C{ zC>j9+6kQ4f6pe%diY|iziY|u%iu^D@(I^<8s1gP!8Vv&!je!A*#=-zaRWLx&I2fR4 zJPc4Y0R||V2m=&Nf&q%IfB}jo!vIB7V1S~jFcd`vy7e;xBzi5)))|FD(OopeF{bHu z=8Gw+(TzW7F4Cl^7Wsvunb1PfENG$VN@$^IHndPQ2U;ka3oR5~1uYcKgBFUeh6Y8~ zzyL+_VSu6qFhJ3@FhJ2l7@%ko3{bQf1}Itr0~9TV0g9Hv07ciq07c7TfT9&JK+#GV zpy+xSpy&n|py);zpy(zTplB5gP_!BbD7qO2C|UzUQ8Yuhwxx?%bPUb@8r4G46dpz2 zqT87-rs#Iv@X!spNzppw7mDtH7K+wG3q>2Cg`zv5g`$nnLeVB@p=dL-P;?ixP;@sm zDB1!86x{;@6x|C06x{~{6x|O46g>a~6g>z76g>n36g>h16g>(96g>t56g>_D z6m5k8inhT3MNhy0MNh&2McZM3q8%_m(Ni!$(bF(M(K9dNY z@5OXG^Tiass2j`aIgLrtOUN%2y$mfB?SvMJUV#>hc0mh8yP<`mJ3q_&OLQx}Vp(qSmC<=!biW)-;MG??KQ4?sP zC=yyIih>43(J(+!3=B}z6b2}A!T?1s7@#N?1}JI<0~9rf0g76{07Y>yKv7E=pr{oL zP}CX*C~5-(6ve{;MF}uKQCk?GC=muIY6k-pwTFSer~?d8)DecF$go)Z5+Kp(^g!GQ zv8X%!FX;0IMkkA%`C^K?S&U0N2}McBFBBz13q>i=LQyKTP?QEO6s1E8MH$dSQFmye zs0XxA)Ds#M^@0J4dcy!kePDp1zA!-1B``oyKNz5>KMYVb00t-;2m=&l!T?2X7@#N% z1}O5t07cm_Kv511P?QS;6b*s_it=E9A}D5`=1ipIeJMdM+B zq6siS(L@-aXc7!ibOj7hG#LgcngRn9O@#r9rojM3(_w(3888$@#TM(U1W5Gve2-Ql z6kW=fw`z->`C^J@S&ZY|grX~vUnrUlEfmdx7K-LV3q@B!3q|vwg`%sWg`#Vqg`)Y; zLeTp)mp6KNkq|&JnJ}9 zDC*B0(^`w2`C^LJTa2U>p=bm03q^NA3q>2Dg`!Q+LeXYuq3AAXq3CXCp=b-VP;?Kp zP;@UeD7p^@D7qg8D0%<}D0&bED0&D6D0&zMD0&12D0&nID0&PAD0&qSv88(Hk&8(VH+p(OWP;(c3UU(K|3e(E%8s=v^3~=sg&q=zSQV=pYPG^Z^V| z^dSsT^brhD^f3%j^a%`5^eGHbbO;70`V0mr`Wyx*`T_IefAb%FtkI>P`(U0^7R99C<)ofTBVepr{B2C@O}bC`z(gClMgg{kbnn z7K-=>^^Fp%o%v#l%B{xAzCuw2@(V>npoOBL&_dBLXrX90v`{nxS}3{{S|}O`Efie_ zEfif24T}6QK+z}|pr{fCC>jj|6peuaipIhKMO83B(Kr~OXgmy1Gyw)Eng|0FO@aZ6 zu7ClGCc^+lQ(%CisW3p%G#H?0It)-W0|qFnh5?FdV1S}p7>c4&t92^@5`8s&X~`%P ziu&>trb`C^LZSdDl42}N^}Unsf?S}2+aEfif1Efie?Efmd%7K#=?3q{vL3q=c| zg`!2!plC4+P_zUFC|U{w6fJ`RimrnJik8CwMJr%{qLnZ}(e*Gu(G4&_(Ty-b(M>Qw z(JC0AXf+H_bTbT4v<3z!x&;O(x)lZ}x(x;>S_=ad-3|j3t%IQ`y3%UBK!8L~=K=L> zp{S54y2EN`zL=toRwH(xP_zm8g`&;SLeX8&LebsOLeUmzq39lHq3B*{q3Awnq3C{S zq38ie06g>$86m5qA zigv&NMNh#1MNh*3MbE$hMbE+jMbE(iMbE8C|bg|{a;({%okJit<~7#5sJP;exc|Dv{3Xtv`};sS}6JfS|~aNEfoC-Efk%G z7K+Y53q@z4LD5ezK+!oEpy)gdP;>zXDEb)&D5`@2ihh9sihhLwihhFuihhRyivEBB zivENFivEHDiZq+twu2%a1}L(?07X_9pvVRT6d5o;Q3woBWQPHY9556`$E?=<1W5E7 zd~<(XDEgV6L>QoG5)4pu1q@I$83rht0s|CH zg#n7D!2m_mVSu6;FhEf?3{X@90~FQ507WxlfTCG2K+%;j6h##_>m3A0^dTNl4-tws zF-5a&cIJyInrAbfFA$2ZMt-5_8fc+tKD1D@09q)z7FsA;2rU#Xf)_jP_!NfDB1u+Q8d?PJwkv)>pFpRl~9z! zQ;>Js?93NabeGN0i-n@QkzXj<0xcBX11%KY3oR7g2Q3uc4=ofu04)?f2rU#n1T7Rj z3=N7NfdPshg#n5lg8_;jhXIPV!T?3vV1S}0V1S}0VSu9TFhJ1`7@+7W7@+8B7@+7G z7@+7`7@+7m7@+8R7@+6{7@+7y7@+7S7@+877@%k;3{dn63`Nl!B7-^XR|&*fJBex z>FN_gQ5*iOW4K{wzL=s&!+5_!D2hUUp(q+!D2jm=ikd3usUj2LlwfgaL|L!2m_AVSu7GFhEf}3{aE+0~ED|0g4h~fTDIVKv8=bpr`{3 zP}C6yDCz_Q6m^CHin_o6MO|TlqHZuiQ4$PLlnetDrN971sW22p5&ws|`v8xsTpzW+ zCc~OZNS^>Rw2)Awr_hlaQXmkLkU|p)0YWDry(owx0wMx}SWr-!Vpmk`T@dLH&&Sq9c-I!HTcV<=8gIN{zWL8DJm{HW5 zfT9cniuw>xlu1BQ76C=s1Qg{EP}G-zqJ9JvjTD+nlBLqO450*clV zP;?~$Me7MD+CV_jRRk1mB%tVO0*bC7py*lximoG|XcGZN*Aq~50|7;w39h0GZ0|k; zB+y-c?s}0b8WwMcEw*2LiK1<`{q;yyw4L>;Xa}<@+R3bnZe~_Rw=k=sUCgTJR%TUn z8?!39ommy#!Hl9i2`IXYfTFtzD7uG$qI(G_+D$;weFPNUPe9QF1QhKdpy)vYiXI}M z=wSki9wDIUQ38q{BcSMU0*am>py){gik>2%=xG9qo*}r3ZnC{`Wk%6%Is9zp8BM+e z@~rI_U!v#*+fFZ6Mf+H-? z+%c-?JJzeBW6Y}PduCPi1G6eR&a8@lWL8B#F{`2z%&O>TW>xeHGm3sCpy)ROihd`c z=p+F}e-Kb~ih!a&2`I9B`nDZK9s-KO2q^LrP*j6}BAb9B9|1*v0*b;3D2gDUs3rkL zkpvV)5l|FOKv4|ARdm$$ZZbdu9YxVMs^~>|bsg*Ti!V`>;IkjCP(`&^uZn6jtD-v0 zswl{;ibBk)s4lZAs>iH~>NBgN2F$9cAv1~+2`FkrKv5C_MacvdH71~_2?0e-2`Fkt zK+#zQ6g4NHs09H!TR%&MplGm0_^D9R$BD4T$y90H2^5>V8SfTCOiiuw~!G=PAjJOYXa5>S*+ zKv4k!MTG{-fV^&4unNc)> zfTD>66ip(aXfgpsQwS)UNCOK+zlmislkf zG>?Fy`2-X#AfRX=0Y&E%P;>#oRdkNeTWNpviZ&2XbQJ+b8wn`7nt-Bf2q?OifTHUNDB46o(e(rr-9SLmW&(<~ z5Kwd@0Yx_vTtyf9yt@sMKv5F|XNf9WDhH;mKEL=9MLT`=8WIN0YzUEP;`{wD%$7s_BKEQSIPI$ zUQ|UFd(H5T&o912(f2;Pe5NY;f%U5BII}AHky#b}#H@-=Fsq`UnN`s*%&O>DW>xeX zvnu+X8AT@vDEfndqEiGE{YgNP<=40EDDn_c6h=Uimw=)g1QeNnQ_}qwK8kz<6!{4# z3MZf_f`Fo$1QbOQP!vT#Q8WQXF$5IF5>OOJKv6uwRrHwUHSrs*8Rz-=-s;CjODoSETQ8EEV zjR`1fLO@Yd0*aauP;?dnMa>B)YC%9zO9F~o5m3~cfTA`86tyLwD20HcR04|92q;P? zpr{=IMePYF>OeqIM*@mE5nM&J{NDWrNMNyiiKw>UeW%}Ep3yq{{o+d$b@SWb%vD9* zS+9zEFsq`T%&MptvnuM%tco(2RZ$;iRg}rBin5qhQ8qJ*atJ8uOF&US0*Z18DC$o@ z(EtL9@(3szNI+3O0YwD_6crLsG>CwrA_9tv2`DNdps199qQL|d4I!XtC;>&o2q+p( zK+!n_S5a5LH!#mA8ZXD9vsF=pBr}Zg`^A?i8s)d!FHlA0tXD;&nN`skW>qwnSrt_< ztDQl0K+!Y;il!4#bRGdkGYBY}NkGvo z0*Yo6P&9{tqPYYV%_E>_J^@7w2q;=eK+*XG6kR|-(INth786i(A;DEN((fH=fCT*V z4cIbObXKw%miYbROB7w=x96X)ik7in6qV)t6Z6KiNDguf&5>RwC0Y%pkP;@N;Mb{Bfw26SC z>j@~jfqm7c- z_!33C{PyFERMD-hS4FomtD@VPRnZ;Hs_0H;Rdg4#D!Q9l72U(Eitc4rMZ1|%bRPjl z_Y+X`00BjN2q=1xfTD*8D0-NHqDKfQdX#{o#|S8ToPeSy2q=1zfTE`eD0-TJqGt#w zdX|8q=Ljg;OF+@{1QfkMK+!&etLSFG_cH?|5Gy~ue~T(QEMG5r(eD>uqUaUBZ7)$p zud-ehy~eDHUT0QC2bfjSL1tC-2D2)9lUWtL#jJ|nW>!V-Fr(;Q0*c-vpy+)9iasEq z=tBaEJ|dv#V*-jkA)x3G0Y#q@Q1lrAMV}K;beMpmBLozEK|s-$1QdNmK+)F(6dfg? z=owUfSrs*5Mp07&ikcBnbQS?c%?T)KK|oPU0*YD@P}G`$qBaB+wI!e^g@B?| z0*cZIC`u=ws2u@C?FlIAKtNGP0*X2jP}G@#qAmm!btSlpg5lo#4UoW%O%0q-xcg2& zU;ZZ1+2MZiC5n26+izW}ih8kL74>FTMH$Shs1LI$%4AkWS^n^_g*Fsq`z%&Mp# zGm3HvDC$o@(EtL9@(3szNI+3O0YwD_6crLsG>CwrA_9tv2`DNdps199qQL|d4I!Xt zC;>&o2q+p(K+!n_6pbLD=v)GdMiN{_-NU^n4Uj;*ywmTYiWb#2Ls__Ae2Jnl;daB7 zs%R|hRZ#`ADjLVEipDdmq6y5ZXd<&Jn#8P%CNry|Da@*9Dl>{I2`HLIK+$vpiq0dT zXa)gAGYKe~ML^MP0*dAkP&Ai-qIm=q%_pE}0Rcq|2`DqB~fxitc1qMRzf)qPv+@(LKzn=w4=3 zw3}HK-N&qo?q^m-4=|%>4*^9F5>WII0YwiJQ1l1^MUN6t^cVp}j}uVz1OY`)5>WIM z0Yy&}Q1lD|Mb8pY^c(?2dkH9do`9kk2q@Y|K+%f?6zwOV=p}-y=+p$a2UxF)4l=8vH<(q?o6M@{EoN2pHnS>vhglW9%dCpt zV^&4)Go$DO0*XE)py(q4iasWw=o12p4iQlFDFH>F5m59w0Y!%iC^|ww(H8_1eMvyk zR|FJ&O+e960*byNpy*oyioPSD=okS--xE;u1Ho1FYPh%7TBB%#{M_|xswh={WbJsk zUwnz8pTq5rSE{04Sg(qHWmZMMF{`5AnN`tAW>xeDvno2ptcw0*Rz+5XzHe7W9%dAU z5m4kMpr{4`MK%FNJ_3sT1Qdl6P!vHxQB4AhA_*vpBA_UmfT9=zied>UiX)&Xo`9kN z0YwP}6xAZ2s5SvbbqFX55?n<;g?on^Ac0?!44f0H=v7e^itvjsQPd#9UbsOOHDtXi zN@P|=jhIzY60<5wW>!UwnN?8}W>wUbSrs*7Rz+tqqo_FnMJ)&@YDqv*D*}pI6HwHK zfTFep6r~VQluAHR8UaP=1QfL+pr}0oMI8tz>PSFQCjyE(6HwHJfTFGh6rD{#Q8xmL zx)WSQ^&-4m43I#g{JQ=65$-$vC*+%IJtF+#OB7{9*iUX$MSWPWiZYp1Q5Lf*%4SwY zIn1i4FS9D@$E=ESnN?ALW>qwR8AW*n6b&SxD4&3$0s@K(2`CywKv59^Ma2XZl@L%= zNDJvzcKzC_Wu2-|CCK+#MBie?c|G@F2;IRq5VC7@^?0Y&o(C|W>3(Lw@>&L^Pg0s@K_ z5m2<4fT9ZtC|W{5(M1FlT}(jHQUZ!DA)sg(!BsRi!rR6G37n9(WfiI@S&l`QM)<{- zD7q}d9=J&rtzx|@x|~@Rt!7q5S1_xhHO#7LEwd_G$E=F3WL8D%nN`sSW)xjTK+#45 zimoQ0=o$iwt|g%8Is%F|5m0nJ0Yx_uP_&tVqAdgz-AF*uO#~EeC7@^<0Y%#hDB3|l z(M|%2ZYH4U76OWP5m0n1!Bw;(!aKtN31rD%9$Kl2Cdv2oZ;SAYFHv+?gni`=s_1Uk ztD<|DRnfi7s%ST}D!PwZ72VIQiXLEAMSGZ4(SyvY=pkklJxoB+BLoyZN}dy39~9{%B+f-F{`4pm{n18W>wUJSrxTp zMo}vQidqv;)P{hfwgeQV5Kxp#Kv5b2Md<_-wIiUYJpn}>2q@}EKv5?GiaHZe)P;be zt^^dFO+ZmM0*bm5P}GBfqMig4^&+^68rJl#G(ZCF1x{j3_nrQmGW4$L7hj?%tEPSH zPF0l6dR3IetcvIUMFW^sQ694@8py1Q@|jUoKtNF;0Y!rdC@LbL zsF;AF5(0`!2`Cy&K+zBaiiQ$UG>m|v;RF<&LqO380*cNhplBokMP&pOjUu3^oPeUy z1Qd-SplB??Rn(`Z_f-QVFj=0&GF8!J`N@!qntt&miYC^yzrRHlO=7(&n#`<Kb#=yB; z6*ZL?Nq5%ti!V`hZ%zAxJ5vI@Srt9Vtco6DRz(jptD;Ak zRneo&D0+;5qQ?m+dV+wWCkZHeih!c02`GAofTCv!D0+^7qP+wZJx@T<3j`GHBcSL- z0*dw%Q1lW3MK2Rj^a=q*uM$x78UaPG6Hs)3;3~SiruQZTB=D)cxxYshEf7TqYx>2P zD0;i5{q$X`=pELpqIa29(R<9Q=zV5Y^Z~Of`jA-_eZ;JaK4w-$pD?SUL(C}plz^ho z2q^lTfTF_$6dfU;=nDdhz9gXND*}qXCZOmj0Y%>sQ1mSUMc)xnbc}$a?+GaSfq!T$W>w^8Mo~BcMG*uP)g+)Ol7ONp z0*ayuD2gGVD3*YtI0A~|2`CB>P?SJGQ7rc?;64=tjz&WXkj>{L15+nWMOB6MZvOnwJPXda15m3~dfT9cniuw>-MM;s~Sq4bJ zN;YtkBi(oU6+$XA(l5S5QQt^=!vm_QAL~_7F0(4?&#a0DFsq_GW>qwhSrz3otD*vC zRaD5ViUu*GsEB}~Vgiav2q-EgplC1wMMDTE8cIOXFanB(6Hs&x0YxJSC_0ybqLBm? zl@U-hih!bW0*XcxP&9^sqOk-NRS-}#j)0=^1XodZr1v2MB(PP!8=IqwrpjLknGoq0 zU!rJAr2XE5s%R?fRZ%6gDw@Wuil#HGqVt$l(F|r)G?Q5s&03(Lw@>&L^Pg0s@K_5m2<4fT9ZtC|W{5(M1FlT}(jHQUZ!DA)sg(0Y#S* zP_&$Yq7?)btt6o6G6ITL5nM%+BE8l_M$uvU8`hIm(Yxkz_T`a&@g<7ZM%u}bsG@bO zS4CGctD^PHs%QhVD!PhU6>VfzMOQPcqHCB{(Y4H~=sIQ;Z6cuPdIE}WAfRY70YzH~ zD7uk=qMHaP+DbstHUf&a6Hv5+fTEoQ6x~cf(JcfN?INJ)RsxD{BcSMZ0*dY+py*Bl zitZwy=x&0m=!!^hjsX&QN?uT}QAG*zCCGas{o+d$-5+U>e@qoUzxe!vnqOm8AVSLQ1lc5MNbn@^b7$-&k|7d905gp2`GA= zfT9-&DB4Fr(TfBW?I)n#+B!qW9#$^j4%_e2Jp>BJJCsP(|;vUKM@7tcpHlRz)8%tD=vYRnaHR zs^}22D*BXJ6@A96iauvX(P09Lju24v1p!505>WIN0YzUEP;``lqHhQ&`j&vA?+7S5 zMnKW`1Qh*1K+$mmihd-Z=qCb-P7qM^GXX`v5K#0h0Y$$NQ1m;&RrF4z_jLm#kdS2H zysL^T6U}fk(l5S5kribhe@Yd3qV%1-Dhgv(MP6oARD)R++03fQ$E=F{%&I7ySrtVv ztD>6BD2gPYD2jlhXab622q=mrpeT-jqId#|0t6H#5KvT$fTG$26xAW1C`dq2h=8KH z1QgXHpr}3pMGXijYDhp)A^}B>2q;P-xQb3idP7eeMNQ@FMSrTIMEMR#a+F_uiK1pv zcGqWB(OIllMa`L2Q43~O)RI{hwPIF9t(jF(8)jA1mRS|0Fsq_eW)!6nP?SzUQ9A;P z+7nRJfqPkS-*#s1IBcP}|0YyCsDC$W-Q7;0DdJ|BTK|oO- z0*W#TD9R$BD4XCaY7*rgX@CTl%Ws}(8s)yzpCzx0a-#g=OBD5wvKQ}FMFUu`it?CM z(LiQZl+Ub+3Yb+lXP(YXW^jU=F`jDVt11QeAMP&Ar=qA>&%jU}L{f`FoN1Qd-YplAXCMH2}qnnZ9F z^^5XuGe80#%0Kd%tBU;cwtsSzUwnz8X;JpGFQ}sFtXD zK+$sq6zwIT=y?K)ULc@o9|1)#5>T|CfTEWOD0-QIqE`qgdX<2p*9a(joq(bP1QZ=4 zpy&+(iryrk=q&<@-X@^v9fGUqfhg}B10>K(eoe?8Rdjt#GrSw+7hj_2!zg>>tE%WD z)~lkAnN`sz%&O=Rvnu+OSrvW8tcpHoRz-)IRnZYz9yjPC;>&^ z5K#0j0Y%>tP;`udqVEYP`hkF=;{+7_NI=m~1QeYhpy+1;ihd!W=vM-Yej}jhcLIt| z5>WI90Y#?>uA=v&ypI?lfs^vXARnlrdlSs?XOv%ji6U>b{lV+1s7Cae@APeERpet< zMSf;g6wa)QBA8WCO=eXT$*hW^m{n0UGm2seD2gSZD2{-lcmj$71QaC@P*jV6qS^!$ z)ghoLNI+4DfTFqt6xAc3s6GKj4G1V|NI+2{0Y!}nC`uxrD4Bqw#sm~KA-IY>(cZ8F zM$u&XQR}d1_dVL&T4rb(?H6C7s718hQ3e4;eF!MZB%mmZfTC;yigE}j>PtXTKZ2|1tY~jP10=9l-rP4=MOJMy zG>BOh6)~%#VrErT!mNr)nN`tXW>qwV8AU@0 zC>lmU(QpEa&LN;^1OY|o5>PaffTA)2ibfGoR8BzAXab7H5KuIhfT9WlipCL8G@gK> z2?P{PB%o*#0Y#GuD4Ie*(Nuz~Xh5`gwE+@%P=4+@PZf2L7fF@Te(@!WW<=X}zN3m} zvR)OqwoSryG=Rz>rfRnY=wRkV;<6`jwFq6-KpT0}t6VgiaTB%o*s z0Yw)PP;@Z?MN0`Nx`cqDWdsymNs`OvnslQSru(&Rz+KwRnd*iD7uM&qOAlJZ6ly)I{`&I2q@Y~K+(+v6x~8V z(JlgtZY7}THUf%nC!pvK0*dY=py)0FitZ+$=pF)!?j@jTHvvWW5m0nL0YwiGTtyqA zz4hKViW75Ky#_fT9-(DB4dz(Mtpry-YySD+Cn1Nxehvnu+E zSrvWFjH06i6n#TL(YFK?eMdmiF#?LdC!pvD0*a0kQ1l}KML!Wxbb^4Qp9v`Xg@B@8 z2`KuFfTG_CC^|_%(H{g9og$#RfTBbKiW(76lte&LG66-6 z2`FkpKv7cyikcBnbQZx?R3pZF)Bp+GE^o{1826q2BhDMP7{B-uMXh7(=+9MA8`i6$ zw#=$1g;^D)GOMCAW>u8Vtcuz(tD^SIs;C3AD(c9LqD}-9bta&w3jsx42`D<7fTC^$ z6m=({s0RT>Jqal4MLRJSp*bi6Ht^xKv7=;iuw^yluJNSe*%gI z5L`tqW4!GQkiehvt+Q6DC|kZAk{9C_U!tfm#x6dhiUzS>6%{e7qGD!MRKl!^N|{yB zU}jY`gjp30WmZMQm{rkmW)z)6K+y;Siq0jVXe0qeWdszBBA}?8fTGa^6pbOEXe(If(jCKFIJg@B@|1Qb;gP&AEzqUi)zQGSefo&geQnP}h? zsG{cb9gy>4{NhU#&5p6J`BD|lVZADv%dCp#F{`5a%&KSsvnpE1tcuQORz(*utD;5B zs%SAYiY_FeXbAyD7ZFf&F#$zO2`IXRfTCpt6kSR{(Q*QcRuE9Ml7OPi2q;=bK+)v{ z6s;zp=n4Xg)(}v%mVlyl1QcCKK+$>viZ&2jMKfc(j~O6=`ttj(XQ`s0&KtHEzxWbG z*T&c%eXWYFW4$Wc#H@<0XI4cwFsq`?%&KS$vnslgSry&HtctcWtDfTCLoD7uY+qT2~5x`TkCI|(Sdi-4lL2`IXUfTDW|DB4Xx(R~CI z-A_Q#0|XT9A)x3%0*W3YxQech@zywM6rGfxyS_#h<%OBy;TXU85=D>4*v-CGMNhC^ z6+OwUik@OtMNc!UqGy;@(X-5|=s9Lpw3k^GJGuMtr6Isruo2q-#8K+zin6un76(OU!*y-h&TI|LNHOF+?k1QfkbK+y*T z6n#iQ(MJSV(W5cm{su_koFoJ1F;z6oYle?w{NhU#eHLR+KBkI3XT2&q%&dxzFsq_3 zm{rl2%&O=sW>xexvno2utct#2Rz=@3qv$&VijEOb^gRJZKM+uKoPeSq2`KuBfT9xw z6#Yy<(JurP{YpU5Zv+(mPC(H~0*d}1py(6$V)&`4T7ua zP>gqt0TQ@ge(w5HRWw9?WX+ECi!V_W5o_Q5gDR@YdQ}w3tcs$TRZ%pvDvDuNMX}7P zD2`bb#WSm-0JADeU`A0b0*Y!AP*jJ2q96f9Ap(l(5>Ql+fTH>Y6g42As38GGi3Aii zBA_UVfTCmqiW(D8)P#VdrUVoOnwJPXda15m3~dfT9cniuw>xlu1BQ76C=s1Qg{EP}G-z zqJ9Jvzl7ONz0*XcvP*hGp z(P#pS#t=|6mVlxP0*b~FP&A%^q6q{PO(dXb5&=b%2`HLEK+#kJiYf^xnnpm;bOMUb zBcNyo0Yx(juA)J)-q8j~;4%5Zv?5jXohX_W>la_5XkM&+@vo|AKI>J{0%ldTkXaR- z&#a0rU{*zom{rkYW>s_{vnpD`tcosTM$yFt6fGs7=n?{omJv{NDFH>x2`E}YK+#G9 ziY_CdXcYlPmlII5nt-A!2q;=ZK+#$Piq;WObR_{r>j@~@KtRz|1Qcx~py+CXt7uNF z_hthmaH~9t%~eG!<%>tx#QMdTD7rq@e&KgjbOY;E(Pm~wpZemtNTbWhS zHfB|{ommy_U{*ytnNf5z0Y$eEP_&DHqFV_lx{ZLM+X*PTgMgwt2`IXYfTFtzD7uG$ zqI(G_+D$;weFPNUPe9QF1QhKdpy)vYiXI}M=wSki9wDIUQG%=Jx>)bG21uZt8SPD~ zXt8_;Dtew-6}`Z$iuN(9q8FJ} z(SBwWy+lCK%LEj?LO{{01QfkSK+)?26dfR-=pX?_ZxB%QCILln5m59t0Y&c+Q1mVV zMeh+%^gaPa9}rOVApu1n5m59o0Y#q>P;`jkDtaQ;+ra<{)RiAhdr}o;$V<{YXI3PXrX5AfV`H0*Zbipy*cuihd)Y=yw8&P7+Y`2LVN=2q^lKfFdhS-?pR3 zLqJg&0YzQ{ifRy0WD`*2BcRAna20(X>s?@g1YWCW;2c&(0r{p{c${B+iK3`D`?@ey z6wP{76vM2FVwqJ@9J4BlXI4c4W>u8Htcq$etD@S>s;CY#ih=|bg$O9BOF&UQ0*dMr zP}G2cqJ{(%B@$57h=8Ib0*aCeC~8bVQ4<1+ni5ddjDVuE2q$Zs2ekix)V^;gMgx*1Qhimpr|(iMHvJX^&y}rlYpWu z0*bN;D9RzAs4oFU{Rk+^C7`H30Yw7{D9R(CXdnSa`2-Xd5KvS|K+zzAt0*$8ob zx$=FqG*wh0-;FJb^NTN0G&s&~?pH-aSg(qPGOMCt%&KTOvno1=Srv_7Rz>GBtD=$2 zs;G=v6^&v>Q8@ucqX{S)LqO430*WdKC>lpV(Rc!iCJ<0Gk$|E}1QbmsplAvKMNiWW1gq6?W-(Gq4=bP=;Ex|mrNEoD|kmoTGf839F? z5>T|9fT9%y6s;tn=rRI|RuNEiIRQnh2`IXPfTA@76s;woXdMAXR}xUPo`9ka1QcCG zK+#45imoQ0=o$iwt|g%8I)bZcew=rm0TM_{HgFcGqEAK9rZ~U&5=C3$?0X|s(T%KE zMK>|4qOHuTXdAOC+Rm(sb}*}=oy@A}W@c4%3$rTP#f+j`2`IXafTG(8D7u4yqB{vF zx{H9Ky9p?|hk&Ac2`Ji4K+$~!6x~li(E|h&?IED(K>~^%BB1DD0*W3Xpy*KoiXJ1N z=y3vyo*=l2Ziw@~ZGZ%Z$hYw~tD+t97ebzl^NTN0^lY5{YqTnQj`gZ&FS9Coo>>*W zz^sb)F{`2%nN`t#W>xeOvnqO-Srxs)jG|WwD0+>6qSpy1IzT|tK>~{2AfV_?0*c-u zpy+J^iryih=v@Me-XoyseFBO;AfV_&0*XE&py*=)iasHr=nw%#pAt~?839F~6I?}4 z$9WTDjH0vTOGMA8qLuR9*u!yt@g<7BinDvgsiLo0uZoT`tD(MbY|{ve>}6ahtl z5>RBt>)Un|c?c*9BcRAjKv4|>ifjUkd;}Ev2`CCDpeTZXqM8I((HC*vu?9%s7Woy| zU#g<>qRkK)?-yU9C^p`{B%q4oSg(rWnN?AMSrsKPtD;)Ws;D-zDyqY*ih|6lD8#Ia z>N2CK9sx!52`FknKv6>iiV_JZYD7R$5&=cY1QazUpr{D}MNJ7PYDPfOSp*a{C!nYW z0YxndC~8GOQELK<+7M9GmVlxZ0*X=zuA=C8?=Ax*u){WRV&dI*`V-}=j%o3J@g<5n z#M>{{QbiqEuZlV`tD?@#s;CRID(cFtiq2+MMctTHQFmrl)Pq?S^<+j-F9M2s6Ht^v zKv5q8iZTf($|9gBn}DJm0*d+)P}GlrqFe%s`V&wzfPkVr0*VF_P?S$VQ2_x(g#;80 zBA}>s8S?%&KSv zvno25Srv_BRz+pZs%R9mDk^7IMWdNj(HLeFjU}L{f`FoN1Qd-YplAXCMH2}qnnXa+ zWCDt&5KuIgfTBtQilz}zG@XE=^9U%KK|s+=0*Yo4P&Au>qB#T<%_X2{9sx!339h0c z@!n1bNZ>8`4#-edRI9NW7R39-mnd2kZx5-fiWak86jTD+nlBLqO450*clVP;?~$ zMe7MD+CV_jRRk1mB%tVO0*bC7py*lximoG|XcGZN*Aq~51Hn~ve!Ta510?X9-@v&* z6@4ee=6JvO5=C3%?d$8SqHU~KMcbKG(GF%+w3AsC-OQ|tZednMyO>qct<0+EHfB|H zJ2Q&zAfV_@0*dY;py+M_itZtx=w1Sfb`wx^9|1-86HxR30Y!TVD0+~9qK615dYFKs zM+hi-lz^hg2q=1-fTAY|D0-5BqNfNbdYa%Wx-s7SlmQYL8fD3(-FJwOx?-yU9 z==pg2(}t?(1=g#geax!pMP^mBpIH^X#H@;5W>!V7Fsq_hnN`ti%&O>hW)vMDpy(h0 zMQ;#L^dxe(vnu+5Srr{;Rz*KDtD>KnRnZA%RrE76ihd!W=vM-Yej}jhcLIt| z5>WI90Y#?>DEgCtA}gS8+fn2ppeT%hA};|&H3%rO2`KUrP~<0|D4c+z2m*>~5>OOL zKv5I{MbQLT(bw_bd;=s96)VfTCsu z6rDvtQF8){S`bjwl7OOC1QfLkW{= zb@H|>KH$F7-(m3B?E`-CC5k!+?EB0w=XZX-s0-^=QCDVFbT+dp>c*^!x-+Yy9?Yt! zC$lQ*#jJ{YGpnKuW)$@ypeU1oqAUW6vI!{4A)u%)0Y&`?D9RG=^Cfjb&Cv70jw=95af> z6HqjPfTD>66ip(aXfgpsQwS)UNCOK+zlm zislkfG>?Fy`2-X#AfRX=0Y&E%Tt&kJ-lXP6(ev_i*XO9Bz4EsjF9`U>mnd2iurpe! zqKjCsiY{hWMN64g(Iw2PXc@CAx|CTJEoW9mE0|T$N@i7b88eDj5m0nF0Y$3`D7u1x zqBR5*ttFsn9RWpG5>T|BfT9fq6kSC?(MAG_t|p-98Ul*0C7|d!0*W>fP;@;3MK=&o zw3&dSEd&(ZNN^P`4tU2IAc5P=XkVy`5{1-F0l)aN>R4fRlZd<9c&uO#^QzklmYH8i zTO+u{e3v9VxYaxnMg^aZx2(9}5%ZG(wSuk97oI}F^UNhQ2tHtbfHEoghk2FNG?;1r zg_;(@70H&>Cisf^c1v2Y_F0zIA$U#;%jy!mv6W?Y4<2b_S-pd8Q!OhiI5XX{`UM|s zZ&`W4KRa4hVKBRkWt9XkJKM5`24CxLStEkMUY0c~cy5MejSX(iw5$oiFS9LcN-(vb zWlayx?r&MMf)D3e*1Vvnz_QK{_8nwd7X~jcwydSW1ErR=JXm+AWvvR94Y#Z{!R;d~ zYklzRk(PCJFumNeHU;O7v8*k@M=LCAThKefvThFMPO_}qf>%tjth<75R9e>VVEywf zYfrFzre!@6+&SB_o(O(3*Rq}owqIab&j;t9Z&~|;k1w*USA+Hv%Q_ewaIs~*9b9{f zWxXGK>r%`5IM{HdWqlSLv&yo*2;Q>VvW^D7TVq+rf*r54tRI65H(1s$!6!Fb*2$3n zTC@K>p@Eys9pDLFd4stJJfU~Cn7hCeYP8kd2cA&Hc5^3qLbvWT_kt(%{VnEh@PsD+jv6q4+5uoLh>)VcJPGcpXBV~3CX{y*xeJ7e-y8` zCnW!>S(Yax|14EMPe}e#?4Y{CeUEo{;>0*(sio{DRQwo{;>8$620`{EEJLo{;>Gwevk8`6XEwdP4GBj+S~t z@@s0AdqVPiMpk)3@{1zYctY|w{nvX!@>jL5_Jri`+HUfM$z#=jr>1?_R2^8JIF=1=|mYfHOA&X;HAe$pN?k4;beyQEDw^Au@g&ERSOoUC1M<~7ou zmCb5@NY1y%%)8B>1}Dtha!v z9yf;}Pj7cf>}@tpcIl`TkJZRiXh(SxyLlRU2H8;waqskO_(nqJ8E}) z`2;I*j;>hGil?8A?Pyl`;x~SD(=F$lCBFD02iISBfwShP!Lz$qiMw>o^X?j7{NqPY z?O7mK6TjuUhf19_+csWyaG|s2@W|=Cti%&$%|x?h@4IWl!UtH1;pTSCF)cP#xAq$U zbAz3&y|eCu+RoMv-O@A5T#7IL+HLQAKHo}`n|`rbl9;Az^W3$*_&Z)$x@^9)xZB=Z zG0x(tqb}>=EI#z)!P^&DiSk=DWE)1gYn*Kush4vlm$U7sBWo5pw`J+_6-CbFEIu%- zQf^B8ZR_rzZY7O2OV-FXRGJTDZ@Jo37bCZ4X&u!dtOs>usf8~##>@|DLtof*eFWgy^IeF}GE3uyWkq_BT9o;o{ z)aKE93Y}Z}$jTLSofYF2EjOEL?$p(@QC z$V$A!JoaSko2M&_oMq1hokg##e`>=#XVK25Pi%L2HMz8wS+if)3};QkCpXk`*8KL- z&#TSmnGJhsPuei&79Y7YsgsrTwpp@EZt;)i17R`8UF%7+68oE@ilmip3JcG(5=WRO zH~ew8`QmqcxN5oC2J_(Rb>GA`&SqWlzG}w-clZ4C($;0BnTtI9!LpSLtfXtrDu>^Gy~q@Ixor1Q zO&O=t1oMJM_GYD<-22lPfANbiy=V5i*)5|ZPl-_H{(9G(S#INI_sn)w>x#1@oDEvH zXZdBa8^h)r31(xquKegSv)@~pL$_S|0TwJgS<>HGu=k~-``ugc{=w}R$xgAO{3o8v zuo8338rivrPjBQdy_mY~^)BE2?XxqTT^l=nZwF^HJM`!o|QPyyhMA( zT*^Rqi7)=xjhj}x2Y?%POlak-Ie1Gm^Y{>18}|J^-%8wO*2vag$eNuOU2@25q#Ped zU1Toa?2i5CE_apu)N#1kqsPn=+1T~&lCbbKR$`cWCX>DN0vGe?dta{*3BLHJzxwKJ z5o$+GoRd4+x$bqxx4yW@O7fXS&XFrgSKA%*Ucce6BRlAUdM|JxJyx(A;jAMR}GT+CO!KIms9 z6`3WDoRQ`O*$*pN8~E+M3}*{g`-;p%%{(eES+{w=JivVM_pMrYjoIHP_4*!VO^>F< z<<6Syac9?a)*RV;(aXk&S@Y)hr`|PddYUI}+3we>ZFiw*vh(bYdh_=^wC;d=zx8{# zi;(oizkTSA?XH+9zc#wSN-8mHoJUcmF7E9vwxe=ap3}_Ph%Q4a%+r?H?^aaFBlt^?*$%r^Ajv!bW7cG8xp5mw?MvqY%=%Jp6J`_~V<_xPl` z<>xs!dHJ#>2aQCt?+$(S%j@QuBHX;DkVS3HALpt3aP3CZotwJi&X@+yn$;ga{*$}r z@Tp~AF0hhonHMjz#yNkxgNsw0^QTm-9O`VAe@U_Vz}%$a#|sBoR^z2f=0%kG;|ufp z8ozBG`trxu%v-bZI#cD3&uc!j+iZ#a@%P#*d||5m@zwD9EKj_rSxiEtH>Q3}X)xXs7qqOfrdDKRPm?UmTgURo zoE_OMvTI~+f_V#|pD~9uyQ3w=SHt6t=@}VmKJA{(W1_!>S=GQ?UAXgsc?OGcJ}}Qd zHT42*_W~n5p4xu6c2t;^|eF4QXCCHzD2=@bwOD>{C~+x4vC%L0IsCK4zacsD2^Z8dh(zI}=x2 zdj9s?@HlFg}%akj+V9P7;g%v&b&7Nt;5 zEc1}4VIB7rZkCUH=8yS=oXFb({luAzooSo-zsDLRCtSiH=MtivOBf_4T!Q(;>Hj?D z<>z1i>uqL_RU{`Z%!?n7RVpW|%|^@h7j2f0nP?{IN4oL^?%ta)1B><>yVHC`k$Vs zhMeko%q=_fzouq1Ys0x(=i@Wa;#`O6QPnQTJPEk}g}HlF{_lL`?B8m8`DJsBVOH8^ zIsMW3xZP$sZD9b*t~Mv~O4Do2UbI<0$Z~rv^N^KSm>z4eoLp=Ec&#~$H_Hc`+}_w6 zq`I3wa_Mrq$NVv8mlJvUV$Od4X8GWl+hybBo|3c6edO+tw5q$s_ISed#&Fxr=?Swr zvO-SXk2^Xa%L`hswQ%uf`Cy+rEZQs|EHl^Re5U#p$`v0of1FRqwYPBYvb4=|DqG@w zg6nNyJ}~bO%ztJ_>3?#j>i<=rKQ`|)z1HhyNtoyNm}qlHa94OzQc`D>r;eLBJ$2@c zF{v}kW{#;Sn?7UOtco$SD#oUcnK6I*tZ5R)RE(WHqhe;Y&&m1Cxx1!LpD}Uj#90&P zR9LAKrcJF#EuT^`FEwS#v@zvVQfE#mpHY!IqoT56X8Fw2igsl)XU!fvaa!uEY15{R znNU8la%SrIF=NWgXG~2^Pb+I*)-J7GdRcm!#I`23t(;a_(YB&|^u)I5X({d7%BNGz zr_cCQ>cq-1Q)Z8?NS#_fX2QhE|KB%b=KPt}_r&-KsTniI&YoB~Epyt8indkzV&1G7 z&MtBHNa2iWlgvJ!nOZ!(e8%LQ*_CA_=C+J4oHBc6Sy4u(fgQP<%#Hp3@Y4TJ5X>o` zRU!9>3DTCsxifgV(YQzp^pYrcRw! zSyn!MqG^V8ab|Xz*(qZ(ooe%&K*@0$uz4~@SlC!j)Im^HQFuAFn(7-uQLe(|?qpNAeMW)%wveMa* zCjVi(TA6btH?~_Px?A!;-i{{b{DG>ibN9yp*)Q#zC3@qM(#+0l>uh+nT}23a7q~av zd@ik%cYadqznqhu`+w{7jJq(^SKAKsl`ZnsvIA|L4-)J^H~B#Bad)G*KN8Ixo@7V( zywTn5I=)(M?1(0IorWgJ@;d#T4-)J;-Q zQ_QE^*^P|bv_^K@rgozSCZw9+aZcq@;(a}3MQ!`<*Ndt60d}KYS!8aOyKI1anrtUF zaxN@-i|ual0KElzxe4xewbbo$#uRgF+u04x*vaDNKGAo#`=~`?0OBW_D?ih z`S+LRUU?6_kiVYxv|GxxIUCW${`*U*=L_2PTiPv}+w~1q=lcKdg5CR%`?0aR7xj`` zRKK-yG40%)V(#rmW=bAr#)P)!qaJn(Bd1=X`7ms3t$%bGX3d#9njN0^k8figyS@R} z%&uSGTyN^%>@sdysvR-hP&S(z;Txc)_14D92FKb>_0~FLk~=2Z&Xi&nHFX!6$3r7C zncMC@E_(d+abX?-(cRt0L$tXjcmJL~t$w3hHg@-!+W-6evxT|W>kGHEf4p;QHA*wc z4T94f!AAYhrw!yW?XiR1W&u^W3Q^*0~Y zNikbF*u9+EK5t98O+%_KmWy{z&7B%w%N*{^Lm=M3bdP_j=F3rL^q9+w>~8Mr+2)d) z+O>U&wjAbboAaGMH4AH-eeVW+?9?~A);xBcyVxvnM)P9C+@X!-iKVvLMeh0kn{{m) z{nrbfyWCu0wY$>(jFWOjU=*2!&}G?eEX^U5mGc{Vdo;E7U_&2iLuK1?=Gclw;v!dskTyAMgj zHr2TFB{WO(&Xc?O^x>_ZuXgok8fbDVM9(+_W~-k;9`^DYpx%Y%gRtxbvkmT%ezrpA zpq*;#^SOB@kM2HRF%95JxrY<}@l(4zH7E9LYqx2_b2~WQQ@MjqKex-lL0+LcM;>!X zkb{TMV-6Z=x(jt{{@JQV=3tWSyb7r=yIUN3~SBMDy@1<~U%KO_%@&V7E9=o}>M~a<1G&wod+>ze$6mwT5 zB)75SdsjO=wU+x>4o{|6-Pr@ipP?|`muD{c^kenkypDGs>^;nD6Z3d&B#*hjb8;rb zfB&dA%U%BR;Fs>K3JJe=ob+X+|-d>m&jdDC_)7WnGuWxz&vfR_j9D=={ zEbL$V_No^d?rX=YWAFd-@1=(S4~D{g}5g z|MK?g@7@GeUFzxA_U?z4y3hmV3PVM-Ra`@5%G!t82H`koSMymlyUQ@4VS- z+Sm>znxY4&fB*K;Ja~Wgge~;AUk_-}*sd?{j&+GX0{%j)Ry*?o{9RA?usHJ-?VRGm zvh1RwvfTW^8F{%`Wf?_%O9y7>msosaV0LkFM&InRl7fP=yn_6`R#A4}vhoW@m7UpG_m~)oq=j!=#GW(T{c2=ZyskR`aD61^Lpu{XH&Mqp+&Z@eo{)Ohk zOY@6M3kwV66J>?DL$mYBatewDW|X+sY%cQ5v-im>$Q)3Xl~IyWmR~xsPj->qo`NFx z-0i!_25?*Q3(AU1`xIvu<;vM|3QF^{oU?T{8z(obtFyVByC}Q3u)u7gdr2Lt-2mD4 z?4pd~YFp0!8(7@8tWRl9j=B8e+~L_(SN$)yEO(&nRp&f%)qT>cZ)k3QSt(cCRW~j@ z=Zv#t77Z&bDKIxVFR!eyAUD4xTW@kZJ%5HdHD4-j->z(ya|^Q0Sl%bke4V%`$GID_ z^E1qtWfkNUmt|zR7t_%>w`^HXwHuyY(vSUHR@iS?nYqsgntMAlqa?Q=-`!7Ls}`nb zR$G}{G^nhPv6huv>|Pmr*}X`)Fz0S7%gfClP_@^FUFxJuoAGnBHTjFT%OEiVKRJE6y^g ztFE_W)z!+QM$ea%ZXOja+^7chOI# zo84D+X}P&YIT>ZynVDtjeRB2Doq5J1&^fYXf zA%DHnqWr#9M@{1@V_?-8atqBdOz+}Ca}=q5ICXAPv5`=9jBHo6!}?U)IdTV`zG`O= zXI1;Oxg*RjDa#(3nVp?gZIksjnFDJ{hB+_{$R1XflaVVAZtg=phkT#NY+6BSk@>(p zv~u!tGfyA%9i?&%tJ-zx?W!Kv<`M2b1kI6n?Chyi=T}{}^Ki&6$UXC6!!?_u@4$j0 zxjW?W=w3uS=K(ThTIKj8bF6Y&2QEI{e85_>4~q*v>1Uqa zhGdu^@R3eBBXT$E{GWn`A*4tAe=I#qkh z<56m!to!CWPt=Z$_U0_|LB<&e`Ra#?(}%G1?5ev`KCIgAs>egVdC-^Y)1KMP(`PVO z+NUVPJjJUixkht$RewyGeaG=Pub{ZZlG~h{pOroI^es2{jk{a>@IkhtVCKZ}l@()? z%=fovR9&SYFUT<$Y2=(fZl69bWM&qW^)tt-ss-$yfdyIaEikVDsy>;SotIadmr-Qo z_suOf$mMB^8v`{C1nxG<>lWu`o^d2EE$-vop0eV8=5>mDPIHXoXjknj2WFe&m%f1E zn&k4*&7sp>m+j!1U0MC+%Q?(bLe++6wae0{$D(YrGmEMpl&kLKOy`A=x-omPa(qQu zMdjFu<&|af0IRyN+`PQ(z8QJ?I5f}rS>`}+`nk_}5L7))RlBFtyPWYbP%iz2r)3*s@wy;bc=-n`;65AbobE61d@ zPqT6>v&v_cmkp?xUt+#}UUlRD?Ni@rPkC7d&QZ7OnMUt>_pUNWB)yB%)Abq6Ji}LA zHV1~ZvaCTRWm)~)C;2m95p=3{em$rSG>5IyBImiwIdJBf9aY?~+94a$c^SjxWu-nT zSG&0#+FRA94!X5xkgc-+mwNyW)m|9qna4)4USdYYOtTA1E9cHApI$us^h;^Bsc*)> zff=W_$+*oreb<@CwX-Q*s_i$&P~ZI0q|B~eljNsUQqq&;=Tp+UwCj-6Vn)T3it?Ei zEtA?#9W#A)k1^9`%&M5zc53_fCd`^Jd+KO&I&R9e@>y-o54ZF%M~bl$%sIzRpVP7J z%;{~%rgt)>e8!jwJ zN*xLA^O79!ox3$Vzo66{s2tsAz80@~ax<^%GWz7^9 zXB>7izbES8#I((Zur|Lpa z??HJPSf;ztU16SUoe#`i?*?=1t9Hn944i(K_m@}kdh|T=$)3{6v7U+eTPR;w{0Ka&1N!_1c3#Vs#F1y7C=NqC4?3d2)!%4D!n5L z2uM>w1r?>)J7RALNKp|BDt1v&EMP-KM6tZrZ|D4mh5LS<_xbzedjdQ0+RnCr^|l0Upy`WI#Hn1EOIkMZg2}dW9HGRw zKCy9GxK*6=*wR?%ePYwlZKH+H5UtvGOxp0vaeE+=pO4(7N#0y-+rxHtw!aW91mZyd_xZSntQ^RIPo>w=TFO;1p3nVpmPIj)nQxC$S?|MPBTTj+NEUGDBx zg{u=@>TVsfyW4f=wzvzANxFWsyV>@?rhlB%q~1Pd-~vv z-77174}0OPLs_<=QMi6d*FeY41#NR}>(g$E4)%iEc4F`?6GYsKI3~IF%D1;+=-1DF zAo0X5l`MPdZr>oW`BJzI!x^}Tz+__dKxv)b()RzHvW1;M;J#}cV_*1c=)|^{+XhTr zk+#{wMYC(6aIJamos2$l`kcg7#X7ikJLPpib{DrVu5dSw-G>U#v~X)MyG3HJT;UN( zS7hf_UH|I~^u)s^o9%8*!Y#h=GMuzdw#{lAhPgSpiRY<~+4eM*IF&uwga_>YX&0G` zz}1-3*0!Zvg%1z5DP4Gc;r*p`kAB^3PnlhrIzyeG?I+_Jv7?0`RIE3ELw$!VQ);)cm``@i{4+M5zSUnZ``6Fc#f_kkxi6Hj>zIq@>I zWvl<;g{ZrQd$sBsNo?i2vuA_RHjI+)-Hx!mylG{-Kx_}KUiR6kv)o?o#9D>>>f2}c z?3dG_tDaqwcU33W??0a_!%a9YY~jAW#95x$=bdG{;*!_q#Qvkgmm=Y2J7-k5L%^M5 z;dPmeu5gQ5S8!s#bmH6cke>LK;ffR)4 zyR&;~X!j3$-}HaF4<_y7)uqY`chI`CJ$b9g-ZRiEnZ&CM-Zn^l|D;D}VGiG`E!@Xx z_heqb2pew#W`(%p7Y&+dg-MyK3VbnT1`Beu?a8kD>N!t_ltfy-?d{%HrhcEp9fBqI2zeJY!?H?{n z$M9vk?Hw$GQu+ggaZ4e)1sP{776m$**J+ z+lf8wZDsd>;6*?SebyRhGLb zr=I-84U=DBZyeeKlF5`*axZxWctk{XycqeV+ zxU;vrRyVs?teZQV6T6Yzb(}cka8GH!er!l{#!1f#Z9C`LjTPRx6K@_B-a0+9ZCjlO z=Tnw+dyCu?ad`cl*xBlKTNa*_cYqRGg>5>!ZSYgB-jlXNou|ZVyNx8ygjLJQ&arE{ zb-%<5iNrfy{Pcv|Zqi=coKb_r%N_2qbyq?1_EIS4lvT)S-}0p0Pj0(5yis%|h7U=s zPvRk=%m4JYtFBj8y6_cQxaGr5l62whIjuwXiJzHpx9lnFXHQmzZ*sb8n`bLli0{>- zpmUy{X$xPGWQF@9q+oEW-x#{zQYyJ6Y z3%rG?i(-pYZiu!hT0i!(mr=A@i_Dal!ZA59B9ZJ1>)AoCNuBm}ZKI__ zBrWc@Pmg5;B~nX8Pmh+iUj-=}Ef*~xtq?scrApL3sp&tylB?9nFaIW=Am)B4H0dj* zUuLF?x!(y*`ij}_gW9h|Cw-+xid*_C{2gdJ6du31aIx_CGWK~r;a7P4%B1X;UvHmC zk$ikt`^{{!JHCv4&IH+g|Df) zaiWc#a%p3c!f&MG?Nh>%zG4ykc!i{|Sj0ZqIq54FIX!U-cda`YCG7e-C+T>1Su@X!ce`1|K5)QI z`@XI1Q&ZgR>835`KENuYY9umC{Y~m`ansi8HTB!pI5mYcX~$G1~vDCnte0}Xb#gHr8z-!n&wQ+d76tgZ`8b1bCu@Znh$C| zrunqyi<&QMzN-0_=KGqTX?~@7Q1chfW199vowy#-?EdVouhTS3X_nWlqIr&{`v^mK z`tvm})@-HeKCaLm-$m0sj<`HPbGYUh&B>ZqY0lMLta+2>3eB~e_iL`xd|GpZ=2p$u zHQ&+vNb?KLZ!~|@JfeAAGbI+Tf4XLI&C;4@X`ZcFTeG2NQ_XD6wweW+-8C=O9ISb{ z=6KC%nzJAHk*50;NOydmW@pV_n*BA0X^z&Mq&Y)#j;8z5qwf4} z)Vxh|jplutk7_=p`J(0)%^jM%G(Xh*T=Q$qA2ff}{8KY(&xdY30?lHYXK0?OSxvK! zW@F7uG}~%+((J7{Nb?HKNt#z{&evS3xkB?U&4)Fg(tJtt70tIbKhoT%c~J9L&A&7~ zd%|*;x2R@m%}Sc*Xg1KiP_w0Gd(G~e{WOPbj?CvfAapH5=Pumvb~{*aw`syijwCeJZcZZ)*njTEykkH9OdA7nl2J zE~^~oJ2gM48s={`D^(A39nGQk0>dpoLGzJXVSZloaP2VvtJ%a}h`7_Y(!4q=%!@U* zH4O7Rni-A5Tw1eZlQ3VZc}vqU->vysvoIgfta3@1>uCvQS(TvFh^U5 zvuWFK+7Fi{)_YdFa9*$ZN`9E%(=1XD=CYcdJB7KQ=51ZVe6Qx`_JYe@AKzlx-O z&5^ysJVkST-!Q+VdGxX{$NGh{*?@57YF;xa%u6(18xrRCHH!`pb9v3KBf~sE^Y$yk ze81-2(P92kv--F&H`KghLYVFIrV^LyiAmwyqgO=4)d9s-RFdPkmkyHVSZ5a%lTpcS+nM%FrTM6`noV*srl3mVSZWjPkVvuZXf@~ za5ld=ob5HQT^{C}HQ%^3%pYr(xIN4jHG8fM^AOF|tHb=T=Ki%|{zbFa-C;gobL_og zzDo0%`@_6d^REZPoc>TaTRalZ0?h^M!n|Dbt@UC4RI}8RVXmy%`{^(b(_H&(m><>r z#$M>V>*rU^+8e@rf#&#)VVA|v+nz0zEE@Ghhd(r`NGFxepNH_S(s1LZ2ftd zyJ%jwH_R(E-~BSoUuc&3I?QKlUiNL6FW0>1K$subJotT>f7h)4QH3w)e(_E#wOEc9z z{M{|rSaXEtc+HzMH)$TxtZ6$K+;V+12Ww8zT&%fSbBE?0&5{km7r`cY!yXGRzjhgRjrkxiqS4=Zovzz8Z z&6_m0YyPQO*FN#tecwynwA*)p=19%ano~5d)SRoiK=Ve;<(jKC@6vo&^D)imG&g8& z*W95QMC@_T)~kqSNzKxll{L@StgTsJvz=xK&2E~#GzV!8(;TfiUh@`Bd)bg!k2^K* z)qF&Az2*y=8#T9U+S6oW`CXd3H9yt-LerjZ5~ur7^N8j#%@Wb@_%k%^;WBah%9{3Y zm&kT^O-$pFm`ybEH9Knd)a6?DTDv^E5kacGq z5t^ek6Z^xgpRPPxbDrk)nm1~?zt-Z;=UL57nu+~i*6&n)TQjl$%lglhzt%jUd06wP z=0BQ={b06SW-R=E#WWN9!K^Q@Y@5ds`wWD{`zCI^+?SiS8zeFJ>HKV0btJ{^RAtmh z>Q0z8YT|%_HYbh`=Wq_$Z!1lV)OEie6sbFK!h}d&`-P^uuB;orBXa87Fp1*_yB`L% z_rr&du|*Sy2MioIe#qo->9DcS1x}6w#=Bqd)A@&|_|N7F_o==*M_a*2UH4(JL+saV zlfLWF@dHNLiLyJluRCDk#PK5rPMTd-en8g!+7F$cBgaS zucQ5A9qeFaMzKibU3;A6i$nQVB%j}|>+G+<*aNRSKj(?_>uZNu#tue0w2nr8PAWL) z9#c8&PIr<0F(tQOmM@MQX+`q)ZL&5RX>O-;-`Dkg->d8}%hztwEj;Z0cgMMZ&uenJ z>hq(Czk6kM;)~P0V#yumYpk8FBf+M-p550L`o%{10V;%l>= zUsHljzL%TaSKQHmx$kR*doC|$|J?Z%w}0+?Ch>^mFN#KDJr&eZ`4v zaymY8x(|dp`oD4GMlNMta6w~t%KjNMTjjS7KM_4V z)X21cCPYR-u>;j9g9Rc{(T)EspO82Rd0T@a&%VJ`wQ;RU)65Aoo>5*FZUR<-Ru{b9nE_)?a6h{d0G;>Y#R+{a-$|Ez)Il`NSzA{o5YS z$r+P-Y5Pt?N9S&__1JQ3ubsoW!`DRr+FiVwt<7aQhv((z99^4{bJ)vmaWplEE*sKe zNdC}*?Z+zY9g=6)(Apt(-Tkn1aIXD7Yj9ipKlwUz*X3q+ZQJ#dV~6YauIm18ezZj_ zoUbHi-r-q^V^b5y<{e&}NGVkdj>J0_9BJ6O#o>9`?)1@>4ch1DMVq<9_K)urvBQ<@ zU-4hwX>qhteso#O{8^O?j+7~5UZz>U*}i)Ro6Q?mv;UWFw@Yd3KP&j{oic9PcXzk< z-hx9HXSh=}vrAsRh#hk0>yEMSYyb1z+;?)vtaZoKa@WDwTJAdNe~!EK_3dBtn%3?u zUc;`F3W-ba+|cw-;c0YUB5KHCekivZ>0Dc&3`|0_@YY=Zr``H$M#2tFD`QQ zr(***Tz6r5r27l6MpFYnQt5$6{YrMP>-hD(XBS^n`n>B8*J|@*+m0Vyc2*=iTFrhG zVZD3QSUPKH$4K#@W~D}Z?cb_<9xQ!vnF$S_{bbEG^J_i0Ftte}+I&HzNq_s7cf86o zEm!thf9KoZR}X$qUAuR2q)C_2Wz0i`N}Ve&$y<`≈y~sd2MZcz+7-FKrK(thz9F zzIk=`sJ+Fj_Afbng*h=LU0WP3nKP&DtlZrLY`I9u{+YvX50B|`WxJgNx{S7aP37|5 zpS#_8Om90mzmt8By>_~)32Al?-6!QuZZ|o1O51M|_w&wGCgqK?`)+u@KKXvz{BY+6 zWAcXNhxgdj%G>{AO=GPim254u68G|x4o3@nuXVq?e(n0__P0lxNGEqnyNxEbI9fG! zY1>QNb+AXFT^;Q)C1RJfQdPS=t500gs@>bRZuiCjcTdW+>tI!QOh>y8s^;ci(tek_ z4ifjGmEken^YZfB<>$6<`%~hwCGHJ*dDi6XaVjsbfnA#ac1hA&x5{hX&VI?-t!3fT zE%REnYn9ttOSj6a@;_cvC90NBTu+zxA2hsYtFir(2~feZAA>K znYL%MS$oXqESqoldwAdZ1p^OMdSiRz)qN}UPYp67p1B@;ecQX@zjds3+tEF>w&rfz z{`<4;sU?{0+3{5mbpHK|7xTxqi%p$5w&BMcRvdmPGHCgx$A4P>?a#S&cg#pFa$0m= z&D*|ta@u7p#`Rlqv~}Ba=el*Vul)MIzIFcY3P1F1 z&~wWBbI0G>J+DW*9=Sae*PXlU$+>ft9{=%N653B|-6^kgyUzBh4av7d$GlGMI^}lO z?a(Q&)Bkciv@5(FdY^PVwEBO(9h&7ev)iFr?nOzr!+E+LK25qE3JyifbDPx3%^Q8D z-M6#aX63aVn$@mBZiB?yezQL-uYsk8iPXGmReSt$x94YeK3^Q$zrNJBXW5b!Y{_%m z*0v>Ux2v67Cvn;x`^(rd?(w2l+gf%^t#;?;o|`yk!~VCo>_2)&o!kB>b>7iSZ+v0E zJB?=5+4b@6bDuiaxY0fPGoEbaZnx6McUJED)W^>)etf}-wM+VrcyL|!1#jPZTD8mj zEZj7u-h~wsw_C!H{f*Ls9RrSKj-R=?^wv_l-p~E5!qQ5S<^6Znowsq{N4?%Vb5VBw zl%q55`?C3xzgvA><<*MM^myp!K4;l!UW@cS`@LNy`_AioN5!`;>D=^8>smaus!#W4 zzi55U=LgocXkEkJl8;8tvHecr>%G+IgGFpV%hwt9BHz6tOZrNQrY*J?rYX^2fxR|M zN%0Pz?uI|Svb_NN!v0HXU#7jCJ|)#l{IQ)1_UbUDplts{<#)B$b}50^z?Ff&p{(6C zQa$&Jp(&|;KRct?K~oy5T{7EF9;;l*{;OZAs~z^1*nesF*(+f`b%q^G%`58u?yJAs zy@vFEwzG@+_2PD>R@y@Tno@Qe-~9lZ=YMOj3)B1zTU+11*3LfgZ?!(%|J$A^GW;v- z95Vg)Y+JX8?^m)Pw()n_r7r4sILlsm`@h&*vc>&!cFuACwF>qlk$wrgh$a08>@=nP zvPEs@r~kB_@(llO+cGTe@2+B-&HlG`Da-n6?6rG2|61$I`?Kv@tl$r>Xnz9BcR%)2 z(f`hlt>m|{?^xM?(!NU-zrLMYRsVZCWi|g^JAAg^xvKp!V85uH=Mdk$>HC^r+ty)+ z?|uO0b^jdObl>T3v~_#KA8VKQO@Ex7@~t4l4%dzbciC#yi3a!Dsp>|9>uf)Ey=d^4 zty%qOu*=5MXwc5C@f)MT2wRn#qrqak?v_OZ_tPiKqru0PZixmj*wuDxG}vb6a$7XG z-!A-$Xwct|yFD7bY^!ufG&pMC=twjuXBY0bXwcLI9gPNato%J1{BD=;STwlVR;*`A z(AmDxhLj*?>+)SJSYj)2AQtSg&98&8;1N5|?_N|f?~S$2s|_kzi`5>vfkfL%+|yx;=6Ij4KUAS*xf zf?w@C_jo~FyCOgLf(mxlUwFY3TbI3F@Q|(GJ}+o%SL>HvFxA#&mmhp@r+mi`Zn4GR z^@Aq%ZQt{Q3|rmZez3<@>3u(V+OCNY{9vy+_|Okp*md@iAMCQlKlX!twz|({1~p9d z^O?bFJF^!ugQfNzUd#-p7~8eQf-lYFoyCGJw(@rs3mVue-CZpB+QvPW>^$!+796*0 z>Aqrt+qJczWDvDmb79HgIa|DVjo>xAoTr%aG|Z)_|idh`?eEG z2N&Do6H5n=+Lbk_bkNQ&=H${r%x>^0rGv31c53P1A-e{rl@6Mj*6F2#+IB5nSvsh0 z>p7!zaLg{lRiy*>chRpd9b9jV&nz9dAHSGYI(XGg%q|^#W-HNrWiZ&jZT8CGpq*KZ zmBGJuwYFRttgRG@v|1TdwJW6c${^FO!8R*{o_0-i+#0-O$938o)Uwh4VDOmT0|p!n z`q>2=crb83$TjF-aD`ol!3TpEOx=)!L7rWPp$CIbw${TArmwT(#>S(OboY1K$GHO; zw(NL!pugSh6WoE4cAAOqKsjSL$sM@MuExpkz!E!`S$31AZ?_ZAb_a&q`CQ`;Y_cn2 zjyuqyifu}|1GVgSo#ze=wyXbIci?MVm-+6%XLhCE*v}3$w*xo11LJLNZ*~Vhv`e`I+>4L& zx^`XL-xQ0ax3{H=x&z1U`Yz@Ud}b%M4`+>}Pqx#<-GMoF^OkT2KC)}9q&v{rno{n- zCw3#B?hd%0*K%u}-oS1Gd#l3M*{-@2cc7Gg3-{{+=~eAslf3EvWQHBEznu|HbAPPz zv{bLUcfRQ=+M<5Mt8vC1c4TU_qQ$I;S5xsUiwz>)If`dmY#8xsDORx9DB_)~Sl;4! z5wEslIg5=WULD1<7SE4(brs84Y!dP6DVDZ)LBy-Cc!tF+TdgeR(_OapYM@-oWm~a^ z$|YU4HEX0?!ev{v^OWN*+qyMYF7C3e-1*AIT(-4qqFmHvTfGaEPjlJUuc>ko%MEP( zE>zBR+19U_a)!&ceitdHyKL)sv2x(Dt=}cezRR|L&6U$!w)M+a_FT60YoVO#vaMf^ za?E90zn01=mhH#;y;jOmmu>x8E8A^dEY+(P>t(lp@wW|86N~?#c-1p^T88 z$_VMDjF8^S2>=LIx`%WQa0ChAJau zm@-0!D*;Lgp$XWS%lYu2n|Jd}V|zP)5i?WrQqJM#y4igj}bLkn5EZa)UBL zmM9}+sd6Y}bZnK~{>5Lg*F4^sP{^B3$c?^}CS*0i;s}&_=jUqzUDkJ1hWrWPY$nlniLfYDkBJUaB$#Ftn@HW}YrG$_dwWx$_P?V6D6eVP%qJ(Txl#tDe z67sU5gltiikgbXmvP}^o+m#XWiZVi8RYu5b$_Uw^jF8ur5wcSmA#W%nR2zg%_As;9sDeRAxD%E@|!Y3 zjw&PMcV&beQ%1-i$_V*W86n4&5%QNZLjG1p$Un*m`Bym-gzq*{*uqjSa$`!VX zaf*_zuyrg!QNk6rk|inPuCTQ%MN!-pwwk9?6mx~G=NS}5U12L)n&LE9*qWB1C}M@% z!YNCU=?c3p%TZ*w!q&7rMY=0&O)F3YuCO&dlfrj}t?5}5X|Av}tw`ay!q&7BMXD=o zO)FE_uY)Hxb*fOLSmCyHs!~KcfOpW4pHxMgOyNJ z!17Ymkt{`>$WqjqEJa<&Qq+|!Mcv3!)SWCvJ;+kjlZ>KX6e#LVfucSXDC$drqDv`I zbQuMT`ca^$KLv^gP@rfa1&RhyplC1!iiS|2Xeb4WhEbqsI0cGEP@rfe1&S`GK+zQx zC>lk9qR|wgqWoy=0|OGDX#45B_ENOOUgCITqQ3Lx6itYFzuR8OgrbQoFGZ8cQZ$(? zMN`O9G?gqx)5uaZoh(IHlBH+{S&FVAqv&c16wRbS(JTrS&89%nH54eCLxG~X6eyZU zfud_EP&A(cMGGiUw2%TtizraEm;y!DQK0C03KZQyfubc8C|XK^q8lktbQ1-NZl(wo zjf=)A*ppd2YWsb?@lw>sy^3BI^_?%L=(ebLk-ZaqQ@vuw4MS*k5i!N2?`WFNr9rLC{Xk?1&W@bK+&@lD0+?}RCG%;Hqd~? zuXC@9Zk3|_iEXi{?|eB$FGamM_7+P*(MFb+qD^Ee+Dw+Bm&sDJg)Bu|$x^h9EJfSN zQuGR0ie4q7=rsxy?Vv!>>l7&3Nr9p_C{Xk!1&ZFHK+)S2DB4AVqIW1z^ezR8-lIU# zZVD8=Pl2KjC{Xkv1&ThRK+(q(DEfo~MW0fj=ralw?V$)2y%>!>U_j!}Iyf76U1V={ zd7npp=gTSjGV1NHceWCWzG8VP+E13EugOyM4Oxo5B}>tFWGOm8mZF1XDf*r)ML&>H z^dkj|exg9p&lD&+M1i7TC{T2m0!6=4py&t%ihiR&(NPK%{Z4_RV-zU*g91f=QlRKK z1&aQnK+)e6DEfy2MgLNu$bJtid|MGkQ3@2LP=t#1Mq@u2koX%$$=fGIAG-IaVky4! zIMa9TcRGchDaWaZZP@t$J1&T^h zpy+f86rDkVqS6#7Dno&yvJ@yPM}ea96ey}dfub`hP;?driYii|s1gN=DpR1S3I&R) zQlO|B1&Yq5Kv8uH6xE;z6?rMKMg}C_#@-6|(o(`L{a@`T4ZNBuzVqc2)lTuc)s&(- zEH6cM$x>90EJgLnQj|rOq6TCsYDku%Mr0{Ek1R!v$tXIX0!2+IP;>zWikecO=t2q< zHKRb$MHDEym;yzYP@t$e1&XpMP}G6~ML85GYDs~jRum{|O@X2|6ewy-fudXr6t$y3 zQ62?~@+m?^wd`-R8<6-O`>7M}Tq*j>c1U~eQ+(&kDe9Es-BC-5IlV4qJb1B8bpDj z!4xPOLV=>86et=-fui9QC>lY5qLCCRx|{+yagr2e zy9cIQQ+(&kDY_%Yt5HviR4Nb#L7 zr)YDEH!4etUS@eI+CrA1tz;?MMwX)OWGQ-uEJd%9rRX)X6zw2O(d%Rs?W91_8x$yd zlLAF=QK0B;3KZ?4K+!uCD0-IyMek9dXg39l-lss(2NWp!kOD;?QK0B!3KV@pfuc_- zQ1lrEiuO>T=yM7beL;buy%eFMjVZC43`jiFy+yxCijKRV?%0>&J6}%G*D2nU4W;NC zmY1S$$x`$kS&9yjrRX48ioPdH(GO%P`jIR}Kar*AXEKToQK0A-3KSitK+&%hC^|xc zqTeV`bd&-`zf+*-7zK*{pg_@|6ev1Qfug@CQ1mwiivFQM(Z3WZio~?pj-n_9ic%<0 z6r(^icry4DY1_XNIcu#;qdlL(MA{2V!rd`6lKJ`KhBe)OqQ3TB4jB#jVwh) z$x>8|EJel1QWPgkQ3VqH+`{Do=r;3KS?h zlLAF&QJ|cS#c|s?YLLltq@J24pE}NS2~TWGOn2EJcmU zQgl99ikgt6=mIi|no^+XLJAZ$qd?I`6ezlw0!5clpr|rNr9qP z6ewyDNxj&0!1AtP*gw>DykEU4K^V0a_-@$t`xbC zSN1x_eCNw4>KgOrHI<@nEH6df$x_sVEJZ!ZQq+qqMZL*V)Q2oZeaTXEDOrjxBcrGv z1&aDpplAREiUv}kXb=U822-GD2nC9UQlMxU1&W4KplAdIibhhP=yD1aT|t4OQ4}Z| zO@X2@6et=?fueB~C>l?Jq6riznn)2U>KuzbWI*Em?AMjNE>cwBc0o>x`OcS9G%e=s zY$iq1Szd~+Bumi@vJ_oKmZGc4QZ$n+MYG6KG@C3%*N~-X4jDyrDNr!>fB~rA8<)vsXS&Hr? zOVM3qDY~01MfZ@U=w7lE-A9(9`^i%D02xIOQlRJ|3KTs|fuct!Q1mDTiq=t}=rIZu zt*1cI;}j@*f&xWPQlRK53KTs}fud(9Q1mPXik_oD(eo52dVvB(FH)dr0|km+qCn9` zicrzYSgf%DiT~l=ja?;0P3&D*Z&S>7zMP`1F|S9q6m4U9DcVk!qF2aL^eS13UL#A< z4zd)zPL`sbWGQ-sEJbgUQS=rCir%I`(Jl%Uy+eVbcPUWx9tDbaQ=sU53KV@nfuav7 zQ1lT6iaw@5(I*rr`ji4ipHZM_4+V-or$Esc6e!wDfuemBDEg8DMPE^bie8SzW*Ct8 zRQIFSTX-yToBjJ^zVqc2eHZgq&`hx;Re^Q|6I0cISqCnB#6e#+K0!9B) zpeT~6&2|(;DNvL`fua}%ic%?1tkoGe8p$Wm02EJdZrQgk|5iq0TQQE4)Y%21%F zECq_nQJ|H6ey}jfugf1P*j})MKvf; zRFeWl=TM-i76ppVr9e?_3KZ3$2o+_f#)8(S=pOscWUokSxTXK9`@PhwJhBuuCQH%zWGQMwmZA&DQq+_zMHiB#s2LeW7g3<-VhR*pLV=>@ z6e!B3Kv4?{6y;E$s3ir8T2Y{=H3f>=P@t$S1&VShP}GhBMR^n`%BMh4dkPeFpg>Up z1&TUSpr{iCiaJw-it4AvIv9}nbMEJ^v!tlL3tduu=gTSTk?M_UCq+G3UW$5=rKmSq ziu#bHs4rQHE+tFRWn?MpN0y@gWGNazM$teD6b+(4(O?P`4WU5MPzn?cqd?Jc3KWf? zK+#AF6kSe%qAMs+G>QU6qbX1{h5|)nDNrHO5lPOR%g(6hc zEj6~xfW%w47u4OQXogcXHPv^%oT3@2-qZO~bQQ}>(bZ%rnn{+TS!5}iO_ri-$Wk=v^sA zRopJfRjI!7K*SOMR&2h6x~ghqI<|vbT3(o?juXl{bVV6fGkB1lBMV&vJ^c` zM$sb_D0-9vMe8U~^cV$-)>EM9aS9YYL4l$tDNytj1&W@gK+!W4D0-FxMbA;7=y?hh zy+DDY7b#G*fdWM@QJ`oe1&TINplCA%ie9D&6|G5)RVpw=U5go zie5?evO7u9t1K@?uaTu_2U&_r}vK0MBM$u6U6#Y(tqGJ>&`hx;Re^Q|6 zI0cISqCnB#6e#+K0!9B)pvZnL`wqK;Q==$~QlKb>0!1+j6s1z2$fH0}8U>1c3KRtt zC`zY5Q3eHyGATku2U25?7?AiBx4ZhF6kY4K^ow}D^W_v3_q;c|Nl~2TrKkj1ib|5D zs1#X>PA5yz8DuFcO_riEWGO03mZEZG6qTnyQ3VPVok@YBvnWthkpe}PC{R?H0!39Q zP*jxyMb#)!bT$Qws#Bn-1_g?0QlRJ@3KZ3%K+(ArD5_0?qB;~Ps!M^QdK4(CPZ26A z>ctKlka$P;gK5RQa7(|M`|;T<&v(9@qVqhjWKSt-%<@unK3R&IkfrDXvJ^EXOVNd7 zDQZTRqKn8P8VNYUst97!Z4eF*uE+ zXqwx3)ZO!)FQ=%t=k@9>MSWOaiu#hJ=u)y2T}GCoeq<@?PnMzqWGNa*mZCvqDH=>h z(GUt04W&TQFbWh6r$EsN3KWf`K+)wCD7u0IMWZNCG@1fMV<=EGmI6iNC{Q$>0!0%j zP&APOMUyB{G?@ZLQz%e0l>$Z6C{Q$=B2?7Vi(PF%;_hzo1ElD6mY1TPWGQ-sEJbgUrRXiP z6unKBqFrPudWS4U?~vtzNSFYHxwxPmI6iJQK0AmMX2aiFV@k3 z#BXpr8efy5Xw9?I?;;peTg`MKKB#rBa~C zqd-v_1&VwM6a^G0N~b_k1_g>TDNs~|0!61$pr|NCsOSeTc8dXtmvD-Hl%luYtLtKE zzVqc2l}z)V9U?`gSYC=wCri;8WGO05mZCCbDJn~rqH<&@Do>W83S=odlZ>LXC{R?9 z0!5W5P*j-$MO7$JRFwin)hJMOHU)~RQ=q5@1&V4?py(V56xE_Y(YX{Ts!f5SIut0X zOM#+#6ey}sfubx56g8kgQA3JQQ9Ld7nE{EHtz>XYq=j4h_q%7bMrpqD9wYDSi#i^x)RFLrKklNML85GYDs~jRum{|O@X2| z6ewy-fudXr6t$y3Q62?~@+nZ%o&rT3C{R>DfufESDC$IkqRtd3>Oz5{t`sQhMuDR4 z6e#LJfuf!ip`ylVu`0t&(U!oT6*eyoFat(HxeSqPb)#nn#wRYspeHpDaZS$WpYB zEJcgRQnZ*XMc0v0bUg)%ZlFNX5(*S8r9jb*6ezlh0!24dplBHdik4HL=oShT-AaL? z+bB@9f&xXiQ=sS$3KXrRK+!4+6s@K}(HaUAt))QGofIg#iy~AsD=oIpfW)77KfOO& zirgO{_wG*foiC^8{xt9H(NgpP%S+LNWGQ-xEJY8KrRWi|6g^6oqIF~`dW&a5| zI2lDxP@w2Z3KTs>fug4=Q1lE1ik_uF(Q_0idY%GBFHoT9MG6#cpg_?}6e!wAfucF%7CT}<;;TG^bDtD_>Hez1YiYjo z-DSC@6MQ@X(Xct+E-XTlTyJRVPk1R#I$x`$_S&BX&qv%5l6n#X2 zqK_$1^a%xuKBYj>XA~&fLxG~tDNytU1&a1kplBZjioT>k(N`2G+E0O^uPIRU4F!t6 zr9jbl6ev1Cfue&HDEgiPML$r4ie68PH8mjdTip9-JEiEhn1vtHeCNw4`X$ZlGeL?D zv%D1jN|vG{WGVWMEJa7jQuI4nijI+`=nt|K{YjRh<75>5MS-HfDNyte1&aQqKvBfk zW;=?a6evoeKv9eWMX3}h@+eT0Mu8%q0!0A@iqa`iltF=_ObQegp+M1T6euc6fudp* zC@M~YqBupU=;yT9ECUk1)xD2)NQz!^zv5WJ_nj}N=nUVxbCML5W_c+pLzbelWGN~~ zmZI`xDXKu0qBF@-bQW2PDw3tB5*bC6DNs~}0!39RP*jZqMQ2l>s5%9TYEYo4CIyPl zp+HeB3KX47fuha*8hWy>F*TQ8Sj8qKn8PCU0?i48ML4l&46e#LNfui0NDC$EID!Rar6`5*^+{f&DO{Hj# z`yuSUzVCcFMg4uR&U7gn!17WwkSs-m$WkXwCq>s+vM}5CoiC?op6^YV zAw}1+ycEqROVI+d6fGo6(IT=GEhbCRbz~{Jo-9Q-kfmq|8AVGeP;?^&if*Dn(ajVn zT1J7Qlh5|)vDNuAL1&Z#X zK+)Y4D7uFNMfXyKistyS+YCtDeL%W5SBgfteb@K-zVqc2J>+}OUoAxsv%C~NLYAUO z$x^hAEJcrzrD#1_iXJCR(Gz4TdXg+fPmxjdGzE&Dp+M2I6exO*0!7bLpy&k(6un4+ zq74)%dWix>8!1q1&X#%plB-vindXpXgdXpUZFtIs}v}DjRHkGC{Xk| zMX2ZjKlZr+iC1$!z5k#T9d`SRcKW{avXpg_?<3KV@$fubKMQ1l}OihiO%(a#j2qBs3mwb`a< zMM;D6mK5cblBMW(vJ@R7OVJ->Df*KvMaRif^cPu* z{w7P&KV%gBOM#+Dpv`s^MJZ5}LV=lmbP?C{R?K0!48O6qTSrQAr9Em7)k09rj}*4M@Cq8H4ky6m52jP7i$N z%PA@wc#G#rQ8|{EqVi-Zsz8>aGs#kP7FmialBK8;S&Ax?rKk#7imH-PRE+{fXH%f4 zIt7YqP@t$L1&Yq0Kv69U6rD?fqS_QFszZUIx)dm?M}eaH6e!A~Kv4q<6g8wkQ6mZz zokxM9#uO+zp8`cqC{T0(MX0EB5L<6R;s>i5oH9YUr9Zofg{Fb;d^trI2i`mLrRWlt zm!jrmDas~GQ46vZ<&dSQC0UAEk)^0LS&G__rKl|#MY$9xYDa;hJPH)$Q=q6l1&TUQ zps0WXMI9+n)QJK`oheY%g#txgDNxjn0!7^^P}GA0MLj7{)QbW|y(v)ChXO@?DNuAN z1&S`C2o*I8Vn+=~{K)AB=OQV(!i9c;?|eB$g95MgA}Jco@=`Q}EJZ`fQZ$S#MZ?Kb zG=eNeBgs;9Ia!LXAWP9GGKxl1plA#QipEl)XdDHK##5kZ0tJdDQlMxO1&St9plAvO zil$PaXc`5Irc~bUj&$ZXiq160#I6B}>tb zWGT9djG~(5G8P6`y=MS-HbDNu9|1&Z#aK+$~^D7v2lMGsJfimnY}*BFp^1Gl?+z7&;kABpu~ z;5%PV(W8NP_YG3Cj^(B3F|rh`Cri=eWGQ-rEJaU}rRXWL6g^FrqG!lb^eh=g&rzW0 zc?uN0K!KtcDNwY50!1%TplBlniZ)T8Xfp+hUZz0N777$?r9ja(3KVUpK+!7{D0-Cw zMXynyXa@y~UZ+6OP6`ygL4l$-DMCdL2eH=-NPJ9Sa2}DO@7%8yy%qS*ms9j^;2l^h zMenh^6zwKU(fed6`hYA&ACjf$BeE2IOqQZg$WrtvS&BX*qi7EWiaw`6(H9gb+Dn0= zeH1AAk^)6vQJ`o)1&Y3=K+!i8DEgKHMc+}N=l}(Z4pN}#dkPf&K!KtkDNyti1&V&A zK+z!z6#YVhqQexSqFq6(=#8dmy!*N9cciGH+mZci;5%PV(eHs*?`A1F#`0412U&{# zBumk8vK0MAmZHDOQuGg5ivA@_Q6yd4?NSsaqbP*}MKKB#rBa~Cqd-v_1&VwM6a^G0 zN~b_k1_g>TDNs~|0!61$pr|MXii%O7s5k|R;uI(?bib_+2 zihc`XT@6UQUnPTcREjn_MP<@`=gTRoknT-dE=6auycC^9mZFMeDXK)4qRM0`szR2c zs$?muMwX(p$x>9EjG`J8D5^<;qH`!vREq*d=Te}kHU*06P@t$T1&ZoXpr}3tin1tB z)PMp-4JlC6hyq3DQJ| z)59(Ob#V(9rTfm8QwP1NE${|ZpOR^NTB1=(gvJ|x;OHo_06y=hos2y2~ z^2jL4r$AAA3KVsqKv4k&iaJuDs1pT>I#Zyi3k8b0QlO|C1&X>;pr{80ih5F@s22r_ zdQ+gN4+V<)QlRKk3KU&NfuepCDC$pvq5%}4qD#_adksjuihKBJE=9fVIB#IO?|eB$ zL({$J?NT(1<)vsiS&BxGrD!BsiY_Nh(G_GV8by|((PSwaLzbekWE72~K+$*#6iuK& z(L@RqO`<^2WC|2bp+M183KUJFK+$vx6kSPyq8St@x{3ltS5u&9CIyOSQJ`ox1&Xer zK+zlu6wReT(L4$iT}u%v8k`=hZb0Jixy`a6QdG=67R^uhoiC?oak|%Lr4(Jq@=|m? zS&D8TOVJXt6fGr7(T!v&x``}BHEpy*Bt6x~IEqPrP@w2R3KTs= zfue^gLPZPHV^3KV@wfugS{P_&-{MPE~(=o< zi`iYy3&0!1AuP}GS6MV%>7)P({?T`5r1 zjRHm8DNxjd0!2M3P}GY8MZGCd)Q18^eJN0MDFuoyqd-wV3KaFHK+ymS6b+<6(I5&G z4W=<26s>lOhGh88ms2z%!~6b0DH_T0Qgk_4imo6_(I~PMjV4Rc z7_tsbvJ{OcOVI=}iY8K^Xc7gACR3nj3I&R$QlMxW1&XFqpy)~p6wRPO(Nz>E zx|#w-GbvCsivmTnDNu9`1&ZcSplB`yisn(E=voRC&8I-o0tyr@qzDxa%ZL?!$P|rm z?|=-KqB`z(Ko({A&X-ekLxz|2h!ibhc_~^-mZBTUQgjnpif$%L(K50WEhkISEo3RW zl`KWKkx{gQ0!6n|py&xcoT4W)yeaFX=qZ+$qNmAH^bA>wo+V4sb7U!co-9Q#kfrEFvJ`C~OVLYY6m6tH z(IyHMZKgoc%M>WuLV=>K6e!w8fuijcD0+ngMXyqz=rsxy?Vv!>>l7&3Nr9p_C{Xk! z1&ZFHK+)S2DB4AVqIW1z^ezR8-lGT=J)RL;X+YxdxQ+WKq-cp#v^&FhzMP_uGQ5}8 zOVP(HFGZh_rRY<#6n#dPqCI3O`kX99Uy!9}FIkHAk)`NMGK#*UK+%2*6n#yBqHicr z^eqL7zN0|V0SXiyq(IU46e#+E0!2Skpy($G6#YzrqC*rY`h@~Thbd6>D+P*8@6e!B3Kv4^dP*J7K*k}V1A6CiW zRL%^y^j~(Qax#7A%PDG;=`DFyirTWg6y=hos2y2~^2kz@PnM$gWGU)EmZAc(6m=v^ zQ71BrI#Zyi3k8b0QlO|C1&X>;pr{80ih5F@s22r_dQ+gN4+V<)QlRKk3KU&NfuepC zDC$pvq5%{r8c2bnK@=z&Oo5^y6et=>fudm)p`uoqv8N13e3pARwzU*JQ`N%oOyBu( zimu4?-hW<-MzOpUjV4Rc7_tsbvJ{OcOVI?f6ip;c(Im1IO(vsg3I&R$QlMxW z1&XFqpy)~p6wRPO(Nz>Ex|#w-GbvCsivmTnDNu9`1&ZcSplB`yisn(E=voRC&8I-o z0tyr@q(IRk3KT7-K+$y+p`wwQu|Ew+e2x1J>&vC+T|3UZKGS!;oT3{uz49BR=q8qz zqMON5w2Ul8%gIu73t5V8B}>t5WGPxfmZICqQgjCyMJp*#w2A^nt0_>lh5|)vDNuAL z1&Z#XK+)Y4D7uFNMfXym=spS*-A{p{2PjbVAO(sZqCnBZ6exOx0!5EfplBThiXNjt z(RvCLJx&oST9O%SZb0I%xEIt*rRW~_y6A~a-}!Qip2_qEY?PvBSzd~sBTLcqWGQ-q zEJZJprDy|Lie4g1(MGZqZ6Zt2W-^Lira;ja3KVUnK+!e|6m6$K(JK@vdX)l2uTh|A z2L*~=r$Et83KYFTfuc7lQ1liBir%I`(Jl%Uy+eVbcPUWx9tDbaQ=sU53KV@n5h{8r zGj^>3iNEfC9rkG{TIL>@KFsu;FQ@3!Oz-~9QuG27!R zCsI`7EDL{S`p%bA6e;5UxJ8PhMYJU^MJZ${ijk!#l`KUbS&GugQsk4RC?HEwI$4S` z$SBIBKv5A26rDzaqM{TiDn@~#;uI)~Q=q5>1&T^ipr{lDicY6M(HRsdDouf+G88B( zOM#+t6eucBfuaf&C_0k@MQ2fhA$*lLO@xcx={O3{Z-QRO1O^W_ws zUBqj+U5cu+ycE?SOHoa-6rDqsqFQ7rI+rX(waHRchb%>P$x>90jH3D!D9WNhQ3DDT zHKagMBMKCqM}eZo6ev2M0!2+IP;>zWikecO=t2qI`{bEwMZzupsqU@W)qJ z6y=kps6APVI*_HPfGkBF$x_sbEJdBkQq+YkMP11#>PCU0?i48ML4l&46e#LNfui0N zDC$FjqP`R;x|9M%mrUiUw1lXb1(0hEkwt7zK)kQ=n)B z1&T&ego@f0iLEvu@m6jZQLYs2cOM{fc@f|Fa*Df?^jDD=K2|y*KO)6%`dbcE#SYf9E-K9-9r`-tT=s&-;B}em^+p zf9#ZNt~sV|cH?=Q%%ZhSZx)?HHjBi5&7$+kX3+&?v*<#yS+tI97F|R(i!LT( z(Io&ZS`WaYO95E40f0r90kG(D02W;Vz@jSwSacNti>?M>(KP@px)y*%*8#BTdH@#P z0KlRf0a$bs0E=!0V9_lAEV>ndMYjR4=ypJ0(OIoSdx{{@M*Y3(HD=NM`qu0nt;6b< zT69lqZ|w7C(Y;J>7TrfSi|!|zMGuh8q6f)l(L-djXd~GydYEh$Jwi5%9wlSZV*o6A z9Dqen0I=vu02Vz3z@n!CSo914i=G8w(Ix;EJqN&|=K)ys0sxCP1F+~t02aLjz@nD{ zShNLzMXvy`=v4p~y#~OdtpF@~9S~S_SL@Is5hU6}zb52vv*@Ch65ePXR=?DucUpU^ zH=9N8GQC-}jcgXZM>dPzC!0kdkjH?EqlWF90n1 z6@W#*0kG(I02ciLz@k3^fkkh%4&5n&M5FrD@olr{(zX)*Y8_U;)S^(T_nJJ34leN0a(-pfJM6iu&65li@E`@C<}l^ z-2qtC1As-l0s@QN)X?uDNc4LBz3ZgZ;2y1^orIpLVf9Nb>YeKC@`_os2h-cJXiu_P z)Q4;q^(C7{{m5off3jJWO*V^i$YxP4*(}NEGhzEQ856EN&r|i3V=nU z0f9xkr-lkdkmwzHbKlD>`bsS-O%1DGYSFkl47EK0V(G&m{?FYc3sQ@h6AAm&%0I;YIfJM^)SX2+d zqUiuEngPI~nE)(m0ASH902a*#V9^`^7R?1<(SZOgItYM8^8i>h9}rkHHZ`X%w{ZmRe7n`Y5@Om7yQPd1A#Ae%)OlFg!ZWV7fZvRQO7*(|z*Y!#*Ps1LI5P7SMH zYSI0v-k^8Pq6e7XEP9Y^7Cl5Zi#C$YqKC<5(IaHD=uxs+^cdMJdYo()Jwe8zCjnUW z6ab5!24K-M04#bIfJK`CSo9nKi=GEy(F*`9+6=&=7XeuG5&(-{24K+^02aLhz@k?H zSo9hIi?#x==yd=Vy#c_YHvw4m79gX%ydUaEKa zHnZq`rZ(#U2}I@v7BAY)M!fJJQpSkxAPMeP7s)ETu&5INi#h|as0#p#b^%~fR{$1u17J}W0E@Z9Dqe5 z09dpS0E_koV9`hb7Ucu5r~rUPg#aun0$@=w0E&R0_bNF#s$Y3kWRQ zBQ4Zd1c|<-Z=LOF78UE;A!TV{^-C?PO!LNlVit{Odb6mCY!+3M&7vBzSyW3lizblG zqKRa)XcE~hnoKr}rjW5{KL8d@1z^$s04zEHfJJoxESd(uqIv)pO$T7n3;-6*1Yl7E z0E=b;uxK^_i{=2ZXf6PY4g_G)K>#e82f(8F04!Pnz@mi!ELsEzEGkb6Efztd@9VEO zR+vS-^c|3c)57YPTC_CHTl1M&bO_U%MTe5jqGe>WXgS#|I*e=<9Zoijjv$*wN0QB= zqsV5_(PS)I0l=bT09bS^0E>#MP~xAXf*(f&H`Z38UPlZ4ZxzcfWV?9X`#DCkZ3nOi8Y!qeMb`na=z0Ja-2lL%8v$5!699{D24K-G04%x{fJL_f zu;_LG7Tp2BqB{XtbQb`N?gn7dJpe4a7Z6xOOR`z?6&Z`Z24K-Q04(|zfJNT{ zu;_aL7X1Lgq8|ZR^b-J!egGkQ0a)}K0E>PHV9_4{Ecz3GMSlUX$Vs=` zb}VuMSd;|7q7VR!k^zB5@27=M7D1wG_4lqnFpK8tudI3LVf9NbYLV_;_nlePlIhK& zR%ElNHQ6jmC7VTQWV0xpY!+pZ&7vsTENVkGi`tU0s2u={+5@mC6M#iA02XxsU{OZ^ z7Igw(QD*=abpc?}E&wd*3c#Xn04&M^U{QAf7WDvN(XIe2>IuN2-2hm$I{=G%0kEhy z0E_kj1QvzULz_jA=o|XDI+7mT>95w`nB6lytbVCQ{nNc~e=v)(ncghQA)7_HWV0xb zY!(e5n?(c3X3-$BSu~hz77ZbrMMKG0Gz@@6djYU$ZvYkz2Vl_%02b{7z@mKtSTquV zMfm_MDga)G63;>J908px zqW#Eb(NwZov_Bb(4gg?L9RQ1_0kEhZfJM^*STqBGMKb|d)BwPuSpY1W4Zxx~04$md zz@h^ISac8oi{=5aXg&ao767nlApnaO0kG&`02VCH;7M%#dqE!GaIthS9Cj+qP6aW^T3c#Y%09bT70E^B5V9}WX zELsh~qO$;4v<84hX9KWkEdYzo0btR&04zEW5Lk3bdT4_P5?!Syu|v(GLj642`RQTx zOD(!6-Fx&mv*==`H;XPIn?>u%X3?c&vuFd^EV_(r7F|v@i>@G>MOTu|qN~VQbTt5r zt^r`twE!%-4uD111F+}@02bW{z@nP~SadT0i*5m6(X9Y1x($Fuw*#=~4geP23BaPe z09bT40E_McV9~t*EV>VXMfU@+=m9`r(S_-uPeqVuo z0btR)04&-Dz@qm6SoA(1uxMj?sJ{pj{axQjd)O?Rt-oLNL3&vIQj0!G_bMEnf&AX} zr%Z1aeMUBmwv)}G&&g)d7i6>OOR`z?71=EMnrs$*LpF=PC1cTd04(|*fJHw5u;@ns z7X1XkqMrd+v;%-ezW}i4R{$3M2Ed}<0a)}00E_+vV9{RyEOIjJwjGOH02UpX*0bo%W5Lon4dZr#QE4P`dUwKk&LkVr53f$@YW`oMX5}07NwER zqI9xZltDI&qGYqE4cRPeOE!zzkD7u&6fxi}nCu(VhS->I1-{ zzJS1@mKmXYMUd!TdMVT@Be>JQMc@6o5rz09Z5@fJJ2hEE)&EqH+KhRRFN45`abH0f9x?86n3L ziw@QI(Q?e98htmmDkH3ZsYMeqyzXJMXd=^_MU%*8(PXk&G=*#y?MF6?rjpH~{mEw0 z0c5kNj%*f9BV$oL0E?yruxJJVi)I3_r~!aQvjA8$8-PV~09Z5^fJFxau;?HF7R>`- z(R=_FEdXHALI4&m0$|a>04!Pzz@jApENTQ`(NX{w9Rdg}s>ukIh#=9!^fzW}&7xj< z+ka?ASp8Cq4$tsrw=j#2V0yFYNU~XU6xl2~nrs%WAe%+UkjV02bX1z@mEqSadG{ zi|zwp(ft4{dH{e$4+600ApjO_1OygcoDq6S1c}bjxA8AAi_X>$ggl%PR=?Du$1}X| zQ_Z3$nBFXUl57?|MK+6`CYwdikjD*!Bd6@W#r0kCK*0E=D+V9^@@EP4}wMQ;JH=xqQNy#v6acL7+m4S+@O z0kG(O02X}!z@iTUSo9Gfu;|f@P=_?JXit4a^q5(6iM|{AaYk7EQj4}{c*8QxqR*M$ zEc$|M7JW%Ji@qY8MPHN6qHoA%(YIu?=sU7m^gY=u`hko^KLW7mCjb`x48Wot04(|i zfJMIou;@1c7X1#uqCWsw^d|s|{sLf;6SdoREOG%@lmx({5CDsk0a)Y#uqXw9MPUFI zMF3dT0)Ry=0f9xIW`qt9L89OF5OF>;i!M)<&?*{Mztp1isCRT5vnYe<&7vsTENVkG zi`tUSqIP7ns6E*%$|RdbF|t|Ifov9aBx6x002XxyU{MzU7VQGSqOJfe>IT4~EC3dD z2VhYT02b{Ez@nZ2EZPl#MY{vAs22c>dIPX%4*(YJ3BaO004(YYz@mNtEb0%yqHI85 zQED`Fxd;-y&l7RdqQRa1sruA0CmL42)S`h=@9}nK(IBQbiw2X;q9J6nXeik%8b&sY z_9B}_dy~zg;bgOD1lcUwhm1x00z@pIr zEGh+H(HH<0jRjy)832pM0kEhXfJGGmEUE-x(RctBRROT58h}MLfWV@>XlT0#5*@2I z_XEtLsrm+gZ8WTYsYR2cUaOc{G==HSqW#Eb(NwZov_IJ_I)H2z)sfAjX=Jmgo@^FP zC!0kx$XGNJfJF@eESd$tqS*i}nghV1xd1FW5P(Go0kCKu0E^}WuxJ4QixvW~Xb}L5 z4hCS+VgME`0bo%h0E?Cau;>r~799$}qGbRqS`G*-nivh`h#=8t_3C<(S#)@J35P|) z>X%w{RMZ>a(JVTe>CK`QWV7fPvRQO2*(^GaY!)3)Hj7r0&7u>?X3>dcvuG6=i%tSy z(a8WTIt745rvk9(GyoQz4#1)_09bS;0E<=wu;?rR7Oeqb(b)hjS_{CUa{yR$E&z+p z17Okl04%xyfJGMquxK3si!K6S(Zztkq9dZALqw41pJ5T_NVDjB4VOg2>X%w{S=2kX zvsrXG)0;(Ckj!v# z1i+$=04#bKfJKi0u;@`hV9}+~(ETDv^pw^j&IYq+g+9oBEE-n7)S{=N-rKvFMNc!m zS@aCqEP9q~7HuM%MbDAVqUXtG(FMmjPI`1%O4b0I=v)02aLl zz@n`HEP5S)MQ;GG=uH3?y#>Icw*gr64gibZ1z^!O02aLmz@qm7So8q^i#`Nk(MJF* z`WS#kp8&AvQ$S$R6VXsoSFva>{S3&HX3>%Qsm9NuVf9Nb`ZDV6nq?M!#q?&;*JQKk z8?ssSE!iykj%*fvPd1BwAe%)$lFg!@$Y#;cWGvbNz@lFOSoA9Zi+%%O(eD5(`U8MP ze*&=RF8~%fZS1xki(CK}B>}J~1i+$X02X-wEJ^`jQ5b+l5dapo0ANu|02Z|ZU{PxT z7Nr6Li$0HrMvEZPU!x+<7iQ6M`gTZKo3Q$&7PV>P&Fx_pwPkv@EEb0otqHX{z$^u|fcK{ak0ASIs04(YWz@ps% zShPC;i+TaDs5bzM_5fhfo&YTB1Hhub04(YUz@q*DEXoF8Q4Ro$asgPB2M8?6XcIbJ z1c~0Pw`I{b!JYoaB9AwqO<4U>i-xrEZt7_k4P|<>Xc*Zn+KX%!?M*g|hLg>r5oEJy zAF^4rFWD>_Nj8h}$yihXz@kC`78L=os2G4nB>*fM1;C=w04yp6V9^)=7L5g9Q5gV> z#sRRX9Dqd?04%BmV9|I07F7YTs2YGpH2^HC1z^zx02WOI1Qrcy6WStzL|uK;W3XAY z(Z6A96IQ>}qN#1XA9pv4_Gfyt=m4@=R7W<8rjgB}da_wGoop7(Ae%)q$!1Xl*({nx z#-iB(ESdwrqPYMpIuL+G2LZ5X9srBx1F&cT0E-p^uxJqgiw*{0(P97=EdgLrBLIt* z0102Unzz@lXUELsl0qQd}KbT|NujsOG}O=%PA)JrV7LVq!BKeOm9{Z!+TZNlo8 zT69bsZ|^;oIJs$8~p{zL`(UmnG$7rtj`J12b!TJI>I|3-@%K;hFFCb)1oz zy|NvrD063vo-USm5%dP=8Gpf&bG|h$&T}3=KiNT&Zn7|o$feaWPWz0 z<9w5uy~c5V$XvSCadu?hcdq079&;~{{&!=e*2xBNW2ap#TfmLIyk0he8|!$PYy&q| zcZF;OH+IEUvK8Fe=hw()aAUdG%XV;M`q%7xx-tE8LVWBNz&M!K=9Hp&KZWBO;QM!PZnyFz7dO#d)Ur5n?~>`~*!^iMNP za%1}4`cvJQemVLyH>TfiJ=2Zp*AvfiWBUEF^W2zzLFghkrr+?`=*ILb`j)w|!?(%i zabx-=Su5O_e#_DEZcM+XW|bS$?-@DOjp-Lfoax5&lm2JBG5x6ad2UQUYrD>k>4zoP zyD|N=+vRRdKdyAO8`IC5T<^y80|Pg^G5wA2+ufM{%I@86On>L{emADSG`G=>>2Ezf z=En5bR-STW`g;eP+?c*`yxEQEJAYf;n7(zh)s5-1_qW`bK0Mv##`Njehi*(CUwrDu z^#1b;H>Nib-?%Zo0{p>^=_!1N8`ER(@2=DG1ldu%%Y$96!M>x4@um0pXa$wredct&Si_JYbh=&kK6hxE zIOZH6|7zr4=euR0?l2qsbNP6eyO)KMP7?OEFiyj83pMgr?A;L-Zs{Rm9}6AiI>p`B z!aCW_-H}1)q6^d}KiJQ8c5y3HqF;S`$_Iz<;*L*=etOQWHy^!=Ta^-h^rp2RAGV8I zof3U$%eki?<#ZAGogFgOE5TG=>k0Qh={jAmHT-FS-5jUOKGH`z|IYnw{m)J z{$A_TzT0z@%wB#e`;yoonY-7z@}nzubGm3_y#cOM!6YZXa`|)1{3hLX$6sg5kW8~r zhb062X)e0_nwT85LcwB=XPU?E{`lBnHCBDKW`#6fR^!>9PPs*xEa=h~KHuHx@`g;L zYjJKckv6wPei=cV`)q)`))!ChGR<#o)~3e?`*XSL;**{|%I}O99=hQ)>5SkP%3(A9?aG?eRfxmS=j>3{&q)>yOp#v}YTo%hq*d-}Z* z{jsvA-=q&O*l^ZiPM02DFwI#^^UcQ}eyrW$wH^~%rW@63{qB8bi~MOWd+FJGk9NB5 zF4MG;Zts$36Tc8l?6ofK|FkYo+_>)Izhu>=D?hmQ&(nggJpVh{>RrlZ8tsGkt=+PA z(`+`GIsOWJt-m_!t~q`a4z4?2rj@ze_Wdu_iNf@!3OyIyIi>+K9|WMGpGboo#Qy2*M! z6ik*9edVNQ?vqwYUro)Mbf~|qyRQCzTd>VHZQJzo5l)xuWmnUU@;wu+{_%uU0weBD*oiiFa`8)J{Q^B1+F)nXyCYo1f_biLE%N|{8D z0X0nW@Of|Frjw*ZU%&F_&3X(-iLU(PgeRrXWumpyHurbB+-}QR6-?x{o_Ouo`}xys zIQ_4ib(K=0XZ&{VwYnv})<<0V{z#|GHe1lWO!NG{ReSkOTRHW@Zhq5V-rRPoKgCnd z)ZLtJzuFZ3nmlsqMdt^Hrehzt>Sx__axA>--4cKNg4-|JPtM_=%SDv_OGyf)WNnqJ zG5wdaTc~B$FGBTSN=RO5C1)1>m*PqIL(UKSFC{sY;=k`tKgdy%lI(`k_G#5hUJgcc1%`XeR9)nv zFyar$KG4D+5Gz{R48356tz5UXtxnRqyUZ?ICP{7UwrbThtF%-n6rlmFTBWvX-D;?e zl^$z0R)&m~(9EbsTSyz5r9@p+Tbrf-YSS#+*(`0W_A-&z)Q-$lX`e1R<`2j!br_hi z%zZl!m(Ou@?CZE1M+O z@049mKGt=TI;<{`lWJFaK^_p~%8a@(j%@$_jxKsZn!i+Ox|}5C3@7Jc{ZD^pN=$Nc zF3~zmPkzqGMyJaqI(U>H_tm&wHqF)Io{ssHRK48L;b0yzl^dU-AU%odt6Fu+Bqz7o z9CS`P7v=wIZe3&^GO7H?>BoL_iHSdnd9|1ua$eG(wTD?W;ZTe zIB&+B`ne01WY3;4qpp7O{OsJEx&d{0IeEEtxj72^3GBCE;ev*K4fWIK_RG!bKcJt! z++SX9_EPrT1vBO?o!O8*zkbG?xeNY(Z^n}4OA>ox_MGhe#WR=AU9hll;o^pV@xEBr zxY+NKphqefFFa8Cd`WioqWZ-Ll`LIQS0n2(yK>&rC3RK#gU1bGGs(*Szc}~*jRc3( zH#X?Da2(TUSYH1bDp}pkhFSGX=QY+fE??BJr2iasS45aOcR`~Bxy}>)>SipQKY!tZ zy81P25p3x*QT?M zDbvbg|FL#wgb`j_8?md@NS4Ke^Q;%e>scHeR^cerD)HdUQAc7X=)nsPqldidnPteXOriz zN6#K!W>-l)nyt-FBl|I{Y2A9tr0uhFL(BVTXXkbg9j5F1Pp$Y*`B=X>sk?faef+s~ zaJ|%aW4%r(ZToqtDLNn^rMuVJui0KtsToiBK z8(Z79!M5vdUE{|r878Zdr{a-K>5MwQ;>pIuu%vrDd=`yu81bZ2!Mt#87&F8*hm} zUUz-1tNz!;OVyI%k1ab|FgMxR5^+bvVrC-lU|4p-L>vpStYa|eAnF$VALdd(@M2-G~we)(@--+BC<^FL4Tchl}V^Jd+=Om-4~iP<#OA2Fq! zzwV)w;r`2^lnlR5LOl%2mY1nQ)2S;ULgicH!>c9zDEHvO6RkeuBeM^Zj}c>0vzw#195}-Yyb5?bFZey{p$*XTXk3 z{kO*!I}qjgliTux<^DI5d;h_4O!~t==(YP_E-FouEhr)xC5plh!OpGjW(?w(vUwUAyDAlI}1 za@dPyd+p_w9$s5Lf@`ly_iDram6z+nm>zPQw{@pwx&yt8(3wY$kqh;2lKOjnLods4 z)ISRD>czCCdwuPo=*KKCD$Udj>u7hcYd1;Vz0}a>&a6Py|7cUS%aaAIIePeiy`a7+ z2mQCxBpo2P;3d_Sb;VUxb*1GK^2hh~b)s8DJuW@)`Tyb@E{;1-*nu?0LvWoIi zPF3-!y4?K2(eW_~YpQEy`ofBFm1V^>GG=Xgsf|}sIJ$0n(}?+1MRnyBH8OH_aaB!m zQT&xLl`_-X^6J{k$_jm9=v!qv{H3OG;$^)umI4wg{*Q}SzTpCX?abtta6>+r&c%2n^iccVa7oNs+Ud=8lPwL$d@YjxdZa* z8vPfFn$5DHOm1?kO8iYzT%Iqn$f+o)uFEe9dUKFJwzjq;p)-nWM$_kYm7^!u$@U*7 zTfQ*ArnI6wSp2Z~gt>(YQzGyAbv>0pzcWmZ%d)>YS3NS_vqqP7i#zG*g-gncZ& z!e&%{nZM+^ipt{h_-p80P*pl=bWOSRXkB%2O^xo~EV`tyY^>kh0Rw}*X^_7}f8jYG ze+ToCXl>hSsJ)mg-4~x*X=znSeqC{4VO?%PsqOlO&2~@!a8p#8KdP>xwx+VSrfxz- zS&i&d@ma8k=z&HLNqRU-*kg-|CzQ(GQcznR^s?+5iN~m5_fnaqlXZvJ{z#a-YLe{c zbrlnet4hi$Chok@s`63sL#cR`KQ2B(X{8+CY!g??Atvz{>#tI^m=Hg3=EXa#Afa<~ z12ru=@IB#W*$~ntb;Xkki;IgAnrs~+N8OryIckh8o?KUwU#fdK+t9|)qlh%EqP9u~ zWFIRjD=lm~6Zn?u0WRKkxq0y&Tz2(f2bBG9=F<7|m&fPr?+(QkrOkI6mMn+naTQg% zIrP{W%p%X~m#+X{8UVE1FJSdMb#&X2;^H;<94@c&(jP+}xvJ zOY1tz#w;xfIwfeq;Dn|4#~s}`dW7@OaMsFZ-mufxh2l|uVNL0T;5;-q;q=E&DJSev<^IXqS7CsRq67KO z4(^FZhNdG{ZgG6e>0rE>CW35x*~e?`6e!JX8bKCXP?ayIc~eN2C|f6S7m}{xa9dVU zZ9DPM_yT1!1U*>5K(W8Um&~2LpkZc~Jdj@;U!3|}Q6jSwNtzDPO^1NO!iu`la%hTA zK;Mk3C<tJv(IU0Yq?pTg^^ zN6Ym}Fs2;NIItxwa$K<-s_a6BCF%TflkwMk2kz1ugFe`RmJ5+ zVr#Vaa)#y&%<8?kVO~T1l7>C9`puuQXz7R<3l}#wEbBLa zzyJY_bC%AZE_K$th4qd7CbqxrgR_?29QYfuxV)lPj&1%9 z(fpD6=|ZkCQnSR80EY6oqASB9T+G9_akO2@cl&eUomj+?+hSiwe>J zTZ{NHUAjL$)22St%fLG8xL^u7`T7I0aRVR+#Dty4-^xw5fID5q+ab028EBx)si98a zoNQRUIGCs05&nzD1jm2bkF{07wQa84+4_?N_rullCT`Oesh-4|F6HE2*!DraxA!-N z3>eazZy(8}xIYlwllmwpK2|UkKPEO^U-?(Ua>HcTcd|nVbCXp|=$nL#P`yNz!;~+E zKWfvRWc;>xu+1g7`D3ZU`Ji}QWx^d@p+0v=Jo{+76K_aIPn1U+g=6K28LUyW9fuu2 zFM8s=4vgP{%N+mBeO*auNk#LU&L)S7@(ca9nQP>2>G=HPS1NzsL*yP@I_)6cLE@ta zYh7EOKSBK0d+PWr37wi>D|hU2U6*)=uGeC8UEt3sx!VaYjN&i&((1);MY$dz{Ih-T zzkOA9Ch3q|x&1SNn(q3V-^{6laouT1b!BOt-IVKWxQWb<&rOc}%vi6ZY#DNiY(u$n z2N7>yLJw3{Rg5l`+e+CK<#K+L#}q8mS4114nv}{l?i7)su1LHfY;+I$7se>l3*6gBsa~;xmok=H(ao&*I`QBy?m|am~NH9QTih+>dKZf?GMi zO>*HP>p+|2W>oI@N()Q$&)a8P!1e6sJD66%BDHVoqx3+7n{7)QU2w%FB`Yn6TfDc;ql9Q zZe)Y|E_%VbwE3RNw(|Q!u7iU9kh{Bt{?L=2-s03%Pb{sGR}#*k+y>@0JwwQqBeSz) zj$9eVZ>aUA&tHI?l>Gs{$x{&Ai}^1l>`-zM-qb_-yw`sKqgNsF(4lTrerfQ;PrQqd zM(4=QMQvHr1&8X+HA~_pYW%rR9?yOB_K=QZW_r!x9OxhWw269m#wdxm67r0-v`~&A za!jxB`zbzFwcG>CGXr}rK))sY%Gm#{Uz93pn7(wj-=lh`MNHN9;S@XT`ToVM$@rcFENz-7Lu-jRfaNe?te4>2)yi zX}5nPxYKc?=_<0Q_#dt#bpuZ>4sMFM8*IMstGwK9aKYxcLmyN71Hl9Naru+#3d?Kk zWRm#o*>Bq4PmRIt73&#)M(5A6=^=KmJW@;Cm71s$Z%vcFi4;7#YQ;9;@8sJC+dNc!ZIR{JMg+4kaXq3mY=`t6P2$#Bz|=x>LaTy6q# z^(ia!PHb{XX_;J*B|b=Kx+JNtF0}V~n)L(nBBMMRwJU{%!R5MN@`5vDvnJ7i_+dKU zVF?E=z4c>677>UZKXLlKmH0%|7vW!>cY~vF{1F=S_20c=uLtU8t*Q-Q zTp8SA1iDG{{hKD+j}q1D+j`{QXMKMK$?VdX*>c%N4~x?OzEGX064!!BbV8ZE#z}`pR>CyD0H572hTThnmz4kx|x%A#_f$QZJyq1#BYIEzMj4P z)6&1X-Bfo}K5n6OE+w{(x$;0N-mCOQ@JKS@jsD=e-|w8nt4aR`ZKAwUt8Z0T*n6)u zDR{`PZ`AF4XxCGgzO~Jvh_^ZN2PUHz^ zetE*jpJs^pf|MNxc+jBQ0}Be!{b_nT1MI=w{zRehuk~39oB=MNIwsf@Dq~Hg2?wGB>W^h8ItNO^-iraephist9~H6 zrF>SuzvVGnWj<3aPqWwOSzcwYZ?Jl^)%&eJWp$fY`LcmiMX4nD%-+>fb$R;vWL@6f zmS55;%lpu>esox0|G~2SK^gz`J*^J4T4c4->Kv`IybW5VpKiANmgS$Ujuwx!Ju-VI zNp>zhmL!RGYNpoqR%I4Wk_gjXtGw9TxE>#LyunsSSS_$xX|>ks466rPJ=p5eR*$!O zrqxTW-e&b4s}EUy-0HJdU$pv~)wivFU{${E!f)@_R)4hmn^pZVq^^&AcZFY5t+utQ z->a#wceA>i)jn3`1K0lRL#&RlT4=S@YK7HWtNU54w>sPEe5*^WF1LEL)sRVPnu)5vqw^nypm6MS_eTwX-+Fz+w zb-&fz*=i4~dsxk}I>hQeR*S8cS*^A@#cI9PIaU{1J;dsfR*$!Oiq*5Mo^N%%)vK)D zX!Q=O_gj6`>N8efw7S*myH-E8`lZz$to~*-Nse3EA1$oPA0+d0%xYJwyIIw9osK`i z>Rwj!t&X-@VReGl{jJWldXUw{R+n2{Vf93-r(0cXb)D7AtX^yN7OQt#eaPw)R-d!F z#p;_@-?#di)o-l+Z1qp8o*bujy<1ytYqgWr?pAwS&9*w&>IkbvR>xYcvO3x7G^?|% zF0i`P>Je6tvwE`C)mHWVqV3c_mZJ4at2bD^-RgZ-AF=wh)y-C4v-*zJkF0)S^?R$o zT6N|8qRWd|O}Cn9br-8Wt@g7z*y_GkM_V0lb&Ay)R`tB6%UNpmD61!0J=5y>R`tB7 z<6mc0zu!ai16H4~`hwN1R^PL_-Rk#N^;%A+_vD17HO*?wYL?YKtmawW+iH>3aaJc- zt+P7E>cLhIvwECW|NJe>U2FMbt5;do?+(#+-DC9;tIt~9V)bpSA6xy}s(#ytPVdV3 zS!+wH`i&l%2UyLQOHa+?tj>^2Pt6Ohu9S1R=G9iOl1op`w^@B!&f%J0vHH1OSZe;+ zYL0x>k>(Lr50PsU&Bs~2U#>|sKW#NhzWGRVy4BI$f?R9$^zK2v(CU_5gZ!S=PP+%W zm(^)X@NH zo@n*Vy@Gs^)mP=FO2_}eYL|V3yoc54`9WT2_3FYP-(mHu;voNKRi4K9^UJq-*q9)n zXmw**ke{=fQW4~~R?Ef*d9u~Bs)Kxq)va>DrS1L5YS&3Y?qhZ4lpr5$_1dXHzRT)2 z@_kb}{U25b*9W=K>Jc-7e3I2i8iM?S)ySM6x3^k;V37B-diJ~^UuyM@1wsDAYSzI) z?q_w@k{~a!di~NM-(&T=LxcR6)uD$4x!CGaM+Es4tB)NOczTfUv-*Qv;A;Q6tAo1NnxKxdx?*jRPqX^O zxj}x}YU>Mv+|g>)x**qCJ@4WmUt#r~^+EpJYR}7poNM*KD}sEe)tj#h@&i_Xx+ch> zYlAxc`kRpJDZ>n}hs{)wJ7!+}Uc)9YLmzRK!0xzN}C`O@m{_Xl}^ z)p-vFdAZeFHwO73t2-VEviE3E_jx?1W33+lWRO=|edg&Pzh*UKQ;>JDI^p>s&#<~~ zbC9pG`uVnsTe7M!yUk~!bR)2jn$lW7~P`CF@deih^)Ru_E}f1U27a^<()?LCxP= z?JGBEnul3kEZ;Jy`Dm+m%hwHRe%$JxawDg?Ra#JsGJ-nZ>d9?_e6H2a@|A=-{@YeF z<+}+r?`n0b+z4u(YjuNsTcPHgtbQtATd4U*tNpWrytmcH9zj0F>b>%fhC2R}R-Il! zPPJOHN06(nUN7Gms^i~d^>M44wR(>8uI24o(;Vk3tKS=U`UTUcTJ4}!#_M9WyYc>3 z_qICPYOU4jRu@`5!sPoBUS>0syU8~<&_2hf&bh-{! z`&g~By2k1{tDCKUU^OP+1EiAMp`YhdVtmGRu8ng!0I7Z<@D@N zf2`FLte$T5EUR)^>?E}go>^);^+&7R{`mF1q@cFb+*bTB?(|=>e12p7bg7MtgF1&H z`3?0(r@#J6xYK{STv+s%Ut;gCuz&DGviV0j{a0t|?-R+pIkOhZg#K{-^y!Nm4hg0W zhJC2V?x5%+v3xvN=lgoc{V1NDcC_tAwS_T3kP0M#`@m*T258aq-;g zOB-dj|HV&d8P}D6+L!vH+c5D*y3qgWF8}Lzp&b-3%ilmHlJ6Uq# z{FWumPv2jmed}eIX=Kp3Mdr6QU5A1nUXx4CX7gJm^V995?bFej-}N%A)2I*nQ&R3a z-|ZR<>;L+i{=3U6;|*QxI=U_SVZ6r#=rBLW%XpOpsk&VK*(m=K*Z0hX^_4?KynQdq zu(-TPivP1k=C>C?D$CN!zM?N@EYUABmaj9EVO?ikZif8RWwLL`ptG&fb(ZOX{V>0% zYl{IWgo_sV% zf2OrOy11+)_@=*L#;!cUXTD0d9qK19I41OVI?55W-)B22jwxAH5-aIia`u?DW7n3R zGy1Qe|NN`shZUi-%RZ=gc71He=G+hF?w{m*+wzz>l9F@J82i|cZ8=+ZB#(Fc{q}~l zTg5jk(kgz~y>-P8t;be;liu?69Zt@>JFY(Ku^mqC%F@Snd~x$inc|D}$B&W!&pdv# z{9h?^*!I|tE*n|a2lcX?@gK~coHX*=7gmh?u0Hqhv5hi*a`dqsm*>1BOLhAE_QqD3 z^VsjQiXM?UZ{3lcvmz@PisURR4Tf6h%pRvhqrYq0_K_W5jFf-QBRjTbw4K&x&IRu8 zTcoYh&W%$>{?xri#ScA4kNs}jQ5oF}e%iKZa@n*o^9?k!*ZJXU>ipw*4OzSjfwXXFK8^=rg+GLfz zUO#2p^f^_sq%Av~?gPi>O_LfOFy>&t=8e9^uis9~DfQ>JYg<{L`*YXKee`=L=gs6_ zw>COex%sGV!t)#yfU(v&HF4jFg;U~#WIa3aLNp9pc+3%B* zykpyI2`6=zoqLu1mo%=!I2k`F*}FteKB3#?M3hv~ahi|9Uv!id@t#o_3D-zUPWJS- z)svFLKg%^u=v8S-sBhbR89j8LJW~thw5yR}?+p1brAUsl;p8J^FnMg6e#?1yqaL5a zC(6;y4L>Qzq9lPbQFw^VD>?j}G}H^fEXSObaJsZM96mv29|^A$-XgqK#%~#(By(sL z*1t5+I((@tFg5&2OSwD@e=QIA(!*!T{~6(1Wz1-JZWlSLhOf_(Z-WirAmg+PKQ3pH z_TdR#sx8v!Yky} ztnhoX#O~o5SxS%aTQav@!^g>(J;USE9A~%iQM<|;*WtUmJ5ED5rKf&B>T@!;r^BB} zo1Y1Hm&?Lu!xQAFx+xry^?fefNtXV6WP|iZUpG=H3+v}bE|RhOyOEyKq4MloMBR&g7PLfmm_E6*&ndj%BNV<6UMJUozru#A!86utWRVZ?t^v2hr$TzYM z--IF|S;DuW$hESBvgAk`X~ekX$Pj6Dd2-|^+4>d9kz$!yWpboJdUt$sl5Tv=XCawJ_Qs7;RO^Y97Dkz-}sPE3x-_cA(@k|W*4%gM=+8)Rlvk|X_OyX==7 znIxNSsw8pe=H$oMTkGWqM_$Z68tyIVyblCHa_Rpc_6 z*}bhI!(_wV*D7*^XuCc=a-3LnX?kReG=4*R-iA64yB^(-yL}WWGi$yj_4=#^Iw#ej%#UjthCO$kC*(g16L@c6z zJpIU6$VBPL6|qR2Ea8|~q){3%a$RJmEH-~#cB+V8IRL}pJiJeuLG~j zHdv_xp7h@dIG}&xE$)*=B(v6-DY!_|h%fFo# zyXtXR2i6IR=)g6ytQI=(sBDOqIxtk`+)4*V%HAL+DW}B~vV!tG%ub7sr0ddj;1lWZ zbRF0tBWLJ9nrx4#4s@38ZleQ>q{rIoz;;<^I~`aotK41(q*d~h9$&mjQjJH$?~Ztt%a?#eQO&s{{4Y;Ym7hsWermb6O_J z8YVArL+d5Wsc*9^sa5hB5?UvFyLEWaODkSFacv@E~DR*)y{E3%vlvz$?VqlH z!^qps|0{m!on^Q7Muq#yj<1G{^(sUu-;gq!)C?JC(F`fKXogf+G(##anjzyYnjuvd z&5&w~W=M@iGo;ochD@-GArmcQ$Rx`cGTAbQOtFk1`&q`2sg^Nhf6EwhfMpD+vy36r zEMrK$Wek~a8AE1R#*mqoF{HsVhRm{zA+s%G$Q;WUGS@PO9B3Is4ze5=QW`o~wtxB% zIbwNZ0z)2DL*|9m95rN-cd+Q=8*;EsYKAPfXof7YXofUeG((nJG(!%tXoehW(F|E; z(F|E`(F{4vB8D7p8AFb+j3Gx_#*m{dW605#F=T~h3^~R!h8$}dLyohIA;(+Bkd>A( zL^|MV(3 zGkXgILl(%{-di13bJUQv-Woac`G%ZhlbRvtS~Nq>vuK8#Z_y07z@iy)p+z%fokcU` zB8z6o#TLzwODtl@ddnDcsbvh=U>QR$vy35^TgH$pEMv%(mNDci%NTOCWemB-GKO4h z8AGnKj3L)s#*iB{^47tTJhTLiyLvFK-A-7w`kUJ~~hO7zQA=^KF zU=Ok4?7)z10=zrJYK|ImuXl%BB>9HiXOo&C_ggeW9uR7yy%|<>)R1?**W_y6H)NYlYKFXL(F}Rtq8ajmMKk0>i)P427R`{4 zEt(;pSTsXEwP=QXW)VZSTgH&jEn~44EfnIhU~D6A-`D0kY6oh$ZwW0X_Hgz}2a@m_g?kZU>%fsYdB+F&F zJV6Ss`@2Y%%kmcF&XVP_yd}AlWVtMFMeZnBF3Ve!J4lwx@>Ft6vRsy@kuxRheN8%` zy#i@r2B4h+X<`)6R)Ms!4WNwzX=GbKRDraz9Uw!2G_yS*U4gVS6Og7r8X5znDv*|T z0JIjMcQ_pZtrSR0I{{iMkd}4^v``=|?E;7>ke2QO2rH15b_Jv;kd}4>cnYMYS%72( z($ek#`LKFuqS=5(o7WE^WMg7TUQ8w8u$|0LYxn#2_k8BnVAY;)$02U1b zV9{Uz77YPl(NF*u4Fh1&UH~lG8-PW_0a!EwfJOTNuxMWZ7L5d8Q9b~R3IJGC2*9Eu z02UPku&4xpMWX;%G#Y?KrGUVqUT)|F5hP>0K2+*$7M&+gRlG57Sp8Cq%3bd&d4S_v zRKfISQ6o(hHQ6kxA)7_DWV2`j*({n!Hj5^av1l>?i>3guXg>fJO$A`l z{s1gG0Dwhx04$mYz@mBp7EK3W(F_0<%>-ak0|1L=0kCK`0E^}TuxKs-iw*=}(Ln$# zng_t5`2Z|h00=B9b3>a%kc`&ybj}-R7WI;2khjnct6yr-64(1uj#a)zjZAMAEhU>p zhmg&pL&;{*GO}5;oNN{yMmCEMC!0k_kjh02W;jz@i%fSac%*i*5p7(aiuXx&?qmw*s)}HUJjg4#1*209bS<0E_MdVA0)x zz@l^9&?FHgqn|$5JJ&2a!oL@D!|In>^nmLvm-i-oiymZpv*;nRS+tRC7ClThiyk4H zMURrrqQ}T)(c@&Z=n1k}^duRJo&sRe(*P`b27pD+0GkI09f=Y0E=D&V9{0p7QGI@qBj6o^dHxr^jsPs`1i+%s04(YPz@l9MSkx7O zMcn{clm)<|?f@+60l=bN0a(-%fJM6juxNJx7WD!I7I{gbJw=d=0rCd8my#6R>0cth zU*Ppl3aejgQQstQY;UuuAJdyf{mEugHrXu7A)7_HWV0xbY!(e5n?(c3X3-$BSu~i8 zMMD5sG!%eE!vI*c7XXX)24K-}02Yk^V9`DREZP@h zAAm&*09dpTfJKV{SadKTu&6@*B&`UNF-v|i$g4Dq4${-x;-s+pr4}8MdSO4uD0+1F&c% z0ED;8S`lS|KnB?t}Z5FL#db8*vvRQO7 z*(|z*Y!MOOl_=qdmfT@ApZYXDeuEdYzI17Okh z04%xzfJHX~u;?ZL7TpZMqFVr1bSnUhZUbP^?Eoyg1As+$0V02bX1z@mEqSadG{ zi|zvi7M-6IDiA?3Qsp-@ybH{tJ>(a8y!(^F>X%xyG0B^eYZg7s^k&f`WV7f|vRU*P z*(`dTY!*F1HjADln?+BN&7!BtX3;ZbEP57zMVkOv^c(<-o(Evj3ji$I48Won0a)}B z0E=D*V9^!;7QF(%qE`V}^cnz*wgRx|bpRH<0l=a+0a)}F0E^xRV9`4OEP5A!McV*@ zMGq#0R*4`Pm&tDldk>jK5xJ`N-b)IrUuw}uN!~RB%%YE(-YoirY!-b=Hj6$Zn?>8n zX3^(lv*-)5S@b2@Ec%LU7JW^|qHh3L^eq63z5`&<_W&&V0f0q60O02ci}#NBsv zRAt|{{XOjL?DR~489IbsLlSz2R0yPzLK7JRgia_4RY0mJ0)l{mAWZ~Otf<%(6hTo$ zMd^xQ!H!q}5qQpX_U{Pcy03dZf4u8m&$VuE@;%6&OlCgQk^q+pD7r#G(NzM9{vn{~ z8UaQB5>RxVfT9}&6x}4C$S~z)JBnNc6qO^O$RwaBfPf;4;3zs@&OEGuxXIE6w2|UD2y$N!r7uIf-Q<7*`mnJ7DZ8PQBV8gfTA7*6r~YR)RTasUIY}S6Ht^v zKv5HDJQqA12xBippKFRdugwC?I4it;&L6!l??qP}cV)Q>HS z`m;sR0JbQ)gDr{%vPIFIY*93bjUpcbMS}?_Dj=X}2mwVy2`CyyKv5w9MZ*aw8bLtO zNCJvR5l}RmfTA%36pbaIXdD4WMFbR$C!lBo0YwuDD4Ik-Q858UB?L!Nj%jXIK-`zr z4}n;@qNt<(669pl*1oi&>87=}lPH?O@uKK1wkVp(7DcnzqG&c-6y41hMRVAqXf9h6 z&0~wA`D_#|AfRX=0Y&!^P_&4EqI(G_x{rXO#RL@HPe9QU0*aOrP_&GIq6Y{lT24UG z3Id8AB%o*|0Y$3_C|XTG(L)3jts$UjEdfRA2#%turum%$;-0L3TzZ-)8lV+DY}(qF zR{EA)3`9}z{L>OYt9mT7BWTG2bEm60Hd-sN~v zw4W`C-eZfR18h-rkS&VdXN#f_*rMnVTNHiB7DXSiQFNGqqK^qEIzm9vCj=CINx#1=(AvqjM_ zY*F+pTNM4q7DX4?qUd+FD7wT((H{g9{YgO4Uj!8WO+e9Q0*bB>P;`}mqJIb|x<)|J zzXTLrC!pvC0Yx_nC^7=%Wjl&o1QeAcpvWYkD1d+>i-4j)0*Y(`ih>A^qVG)eWd+1t zU;lj3_oC=Zv>L$yw)UkJg$GzCQbbV%$BUv!wkUG5MNt%66qRR-q6%zLRFN%;JZw?q zWs9OpY!p={pr{G~MO6tXszyLjbpncN5KvT;fTCIi6h#wIRGWaJIs_EeC7`Gt0Y&u* zC~81JQ9}ZX8WB*`n1G@t1QazTpr{!EMKJ_NQD}g9LjiH`RDUwr3JY*v>HGAbOKl!t zYhPMXivX)u4^h;T<3&*`wkT@N7Da8?qNpuf6t!cEqV{Z2)PXIEIpeTiaqErHkx)V^;gMgwm0*ZPPP}GZnqI3d^G6*Qj zB%mmZfTC;yih2`JltXY7#RZtj3W&SEex)BTiVmuul(ljLZ0$=c>KkAc_7p|^I9?R> zXN#f%Y*BOvTNDjsi=sQ(qG%9X6#3YqXfRt86|hk>gn*)<1QZP;ps0|5qTvJ-jUb?C zBmqUE2q+p&K+zZiipCO9G>(9xA_9uW6HqjPfTD>66ip(asF;AF5(0`Q6HqjTfTF1c zM^S!&xmW>lpVm*P`-q~7n$)xaTl>)f#4{b5nvusK-^c=wC)l` z?`TDj1lZb_R`VUl34qjDVu!1QeYhpy(t4MW+ZTI!!>)83KyFB%tUk0*cNOQ1mqcMdt`8 zI!{2+Hv|-YOF+?g1V_=k0p>sj#Jx>F71}R~x`nCneSocfX+=K;ShI3P(a#(&ihf~> zqF>pf=r^_~y2utqzq3WrCAKK~gDr~wWQ(G|*eLp&fTGI;6kQ>p=qdq4{}51gjew$m z2`IWwK+z2Xif$56r2bg;dUXK@xKQLGpr{-HMJ5470R$9T1QZ1lP-GKO6huH#Fabp& z1Qdl597R6_m|GPP_jvu~>K{c>to~WYFw54yv?8}vd;3$f)%nJ&LJ751` zTBPN?(tlllAv@l(wJ)uxwPgkO6Gd$}UKF)ui=uXHQPiF-iaM}GQAf5Y>ckdBo!O$O z3tJR*WuvGY0YwP}6eSW+lte&LG66*?1QewbP}H4(q8RJSp*bi6HwHffTA1%igF1k$|ImCpWrBJX_?Ix5cebc=dN3cqS^Y3M|~_?`_hUA zSXR~mQFI5#i=u&SQFJF;6b)jFA|G264Q7j?0=6g`!WKnC*`jC|8%2c#6b&b!XaoU8 zBMB%PML^ML0*b~EP&Af+qHzQi6%kN0o`9kW1QbmqplA{SMa2XZl@L%gnSi1x1Qbmr zplBKaMbil=nn7?B^|QVcwY4#$h4xolB1 zk1dMkvqjMYwkTT27De~4MbRR*D7u#|itb~hXfXjr_Y+XGgn*)@1QabJpy&Ytik1^l zw1R-52MH)zNkGvm0*Y1>Q1lQ1MQaEsT1!CDIs%FwCZK3N0Yw`KD0+l|qKyO;Z6Y{| zW?AN|3W&S0{<-VfqUbBFXtQN&Us};N%Q`hk6g|fAqG&r?6zyP(qQ}{yXeV0~J;4@5 zPqIbPF19FoiYH+Xg2{xFAz}lA^}A&5m2;;fTEWPD0+o} zqE`thdX0dh*9jQW6n(}< z(NO}5J}02)3j&Ic5m0oTfT9xw6rCiX=oA4(rwJ%JLqO4&1QdNmK+#zOioPbG=o|q> z=LsnKhJd1P2`KuGfTHgSD7rvE(GLVi(E-a$RY2Ua)fJqBqR8b^<44QZzO`o6kTGAqCeQ8=ufsN`im`!{$`7!%WP3}g^i-C1Qh*4K+!b6j=lm1rktX6HpXHKv6IOMIi(fg%VH{ zMnF+G0Ywo6N72ugxkLeR@77RfTBhO6g4KGs0jf@O$jJ!MnF*v0Y%LTD2gSZD2{-lcmj%A5Kz>T;3$d;G(S~9 z+`DTjIOPMKSNdJ`_w-u@+S->^)GpBaV}vMb&+($D16vezWQ(FsY*EyiEsDCZMNwC_ zDC))*MG0(Cl*mR=5&=cY1QewZP?SnQQFj80dJs^QMnF+d0*ZPOP?SzUQ3e4;nFJJN z5m1y(Kv8c3igE}j$|ayEkAR|l0*d+&P}G-zqJ9KNQJX-s@<^rVuznD0D~kTsUxMr( zXlq|u(Vc--`_ZCk5XXxmA6pa+W{aW%wkR6H7DYqZqG%Xf6cw^X(QvjX8o@@_A)l(u(EnHWE;@iGZTb1Qcx{ zplB<>Q8Xve+@^rIhv=W)pDT)H>N}=K18wa~E7}og?Jp8Vk8`{z+Q}A0Pq0PNlWbA6 zi!F+tVvC}u*`nwfwkUd*EsCCFqv&}8igpuF^a24zFA`An5&=bf2q=1)fTC9jD0-EE zqSpv0dYyoxHwY+tlYpYP2q=1+fTFzw6zwCR=p6!z-X)-DKLJJW5m0o1;3#@5(EL#W zaj&)%ob94$zW!mOgMqg8r4@Y`XoXG`MIUjzC_2m*MIW<8(Gj*N`h+ctK4pud&)A~q zC|eYL&K5;quu*i3fTH6B6rCWT=p+F}rwAxIO+e8Z0*byQpy(?Cip~;H^fduR=Lje| zPe9Q(1QdNsK+$&u6n#%X(FFpEejuReM*@m|BB1DJf}`kzKr>DOaj)0kM>`~n7MN=M z5@>5*TG8);R_|g_bcy3d(I0G4^e0;s{lykVf3ro=Wwt1~!WKnW*`nwlwkW#BM$x|n z6kR8v=mr5rHwh>*Y=2`H*VKv7)+is}(i zRG)yN1_Tr}B%r7f0Y!}oC~87LQBwknnh{VGLqJh;0*Yb@D2gMXD4u|#76cTvB%r7j z0Y$9|C~8A+6jij%*A)==z4}W;9@}}Pzf?b>wY6>SODpPVTW6+dF>H-Pocifh~#>*`g?kEsB!aq9}!pqErHkx)V^;gMgwm0*ZPPP}GZnqI3d^G6*Qj zB%mmZfTC;yih2`JltVyKE&)Y(1Qg{HP}GNjqP_$a^&_CDKLJGp2q?OP;3#Tuo8_h{ zMd$SQ^gD>68v2Vz18rOT(uxM#R^1t*sDR@|(Ga#M8p;+$!`PyzkS&UavqjMewkR6O z7Dc1jqG&W5MPmpk8cRUYI0A}_2q+p)K+yyOiY5|JG>L$sVgiav2q>CNK+zNeil!1! zG>w3w=>!zbAfV_j0*Yo5P&A8xqS*u#-AzEz9D<{0kZtx*K-^39_tAW!sA04kb8TDu z(ux+^)~K1H=pK$2MT^*?=w7xcx{oc27PCds{cKURge{7evPID{wkUdljiTiQ6s;hj z=s^OCRuWLOih!ck1Qb0)K+zfkiq;ZPw2pwHhY2WJPe9QI0*W3XplBljMVkmH+Dt&v z76OX45>WIg0Y%#gD0+nw+JYDn}DLd1QhKfpy(X}iryulXg>i(?-5XRfPkWd1Qfkb zK+y*TN73W9c~k*$@6$iMzf%-_slQ%y$hNgFt>|Oh`fH9TI>Pay=o7Xm`jjn-K4Xib zqij+1Ia?Hc!4^fw*rMn-TNIsOqv#|7MW+ZTI!!>)83KyFB%tUk0*cNOQ1mqcMdt`8 zI!{2+Hv|-YOF+?g1QdNwK+y#PihdxV=tlyIej=dgX99|TA)x420*ZbkIEp^9&8l;i zqWB65&S6n>s;U|nZCm@&ivF~%j`Ky)UmP!r{$`7!%WP3}g)NG%vPIE9Y*BQLEsFkS zi=yjnQFMciqMHO18A0-r8$~VxipmjCWD-ymKtPd2Kv5t8MK%FNK?D>96HpXFKv5_G zMPURKg%eN|K|oO?0Yz>CilPW8Do;RB1p~PvgR%nMO8Uo6jfu3qUvl>RD&&wYO+O9Ew(6%W{aZQY*AE)EsE;0QB;qBqWT0B zH6Wm_dP2q!r66;=0^;`8Q*bH=Ij{6%^q(Z^5M*m#T2YrE>%byW)Rp5! zQ8%_IN??nkM7AhOVvC|=wkS$ri=tGvDC*7@MLpOkN+Y1CCjmvh2q;P?peTcYqD%sc zvIr>3CZMP{0Yy0k6y*|7lt(~OJ^@922q@}HKv6#eiuw~!G=PAjI|wKmNI=n@1QZP- zIEp$2nLjHa?j`z_erHh>pocHW*1oi&p+Q#oVo@}V<3&*+TNDjvi=q*1Q8bb*ibkW?k1pU4gp1T2`HLJK+$}Hqo^RrY@vX-Yw4##LqySI zTG4_aTl>#6g@^j(RKogb`VhXIKfeLPmnoH0daq(|Nf#yqUedrYU~WMwJ)vcsUU0J zGEww2$BUw8*rMoJwkUdzEsCCJi=y3ZQS<^^6urn6MK7^M(H=I6UM8UE6#|N0C7|dv z0*YQIpy&+(iryrk=q&<@-X@@EF9AjS2q=1ofTDK^DB4dz(R&0G9U!3SAOS`16HxR4 z0Y!%hDEg3qqK^oUq9=pQHx&?fNsxlGOBDU0|5(xCAY1#=iargpzFIDdKI3>%bd)WM zK4*)fFW92!7+Vw_XN#f}Y*BQQEs9RDMbT+Cip~&F^d$jBUlCArmVlzK2`D;8K+$;u zioPMB=vxAcz9XRMdjg6s5K#030YyI&Q1lZ4ML!cz^a}w+zYH4yhb$YhPMX^c>Z_1U7R z0UJdP2`FkrKv81?ikc8m)RcgtW&{+)5Kz>dfTCCeisA?;iYK6`1p!4Z2`FksKv8P~ zirNrR)Rusvb_5i)C!nYU0Yx1NDC$IT6jcp2mn$G{um0=ys|7o+^i!kM=p1ZoUs_Q@ zu=U&;QIyE>q9}V2h$OwkYb!7Dc_-C`u=wD1(5aOah9s z2q?-Xpr|(iML7f%H?2#%tz!R8kVi2GIjAl6M34N$*l4GFfjFRf^JuyuKzC>p`>qG%*r6pdnw zqS0(oG=?pT#3qqxdar=BcNzL0YwW4C|XEB(LDr5(Xe2% z`ol`m82vXD7mA`C`VnnWu&sS*MfV3=oi~W0B^)n`ma;|BGPWpsfGvuavqjMgwkUd# zEs9pMMbRp@C|b=%(L)3jts$UjEdfRA2q=1(fTHyT6m1}&=n(>nHWE;@iGZTb1Qcx{ zplB-rMUN6tw2gqG#|S9ePC(HP0*W3dplBxnMNbe=^d!MibYHMJL;-R4)_-_tu_(Hz zAJKLN+uD~_^lY#-f1@aRj^jnq^K4PHn=Oi7V2h#`*`nwrwkX=e7DX?!MbRs4QS>Ss zMXwQ1^g01WZxB%QCILln5m59t0Y!TWDB4Fr(K`eby-PsRegcZ#BcSL20YwK1D0-iO zq7MitIz&LxhXfRTL_pDD0*XE+py&v}QS@}M`M3h&j@CbS{fsC|(?1#VNwBSbX+@t0 zTkmfcMPG2dC_2U#MaS8q=mc97on(umQ*2Rmnk|aXutm|AY*F+T8%1XcDEgX!qH_ck zohP8^8v=^HC7|d#0*byTpy&btML!Tw^dkX9KM_#$GXX`v5K#0h0Y$$NP;`-iqTdN9 zxAFN*$U zi=yjnQFMbXif*z+kr5)V+(nU#EsDyqMUlxCMFDISSp*aX5>R9lP!vQ!Q7{2TAp{hK z5>OOIKv6gWMG*uPMG{ctCZH&afTHpQ6jdOgs3HMH9s-KI1Qb;wpr|qdMO6qWs!DJa zT?sZ@DIo4=^%okiiXxBxYiO#4*xHv?R4c^Fe@qlbbG#_3%@##<*rKQ|TNKq}i=z5$ zQPhAfiW;&-Q6sh}YRpDa69S5w5>V8PfT9=zikcHp6iYx+905h~1QfL(pr|DQMXd-Z zYE3{<8v=^j5>V8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm497Q!k%oz%ZJ6gl38RERs zKcq*u5L^4wijqUD^*cmS3df70RJJJU&K5;I*rF(nEsA=wMNu!dC`xCGq71eu%4DM` zi-4kR0*ZPQP?SSJQ7!>Rc?1;Y6HwHLfTF$x6!jyZs6PQk0|+R(gMgxe1Qgv#K+zxq zihKkV4JM$dfPkVQ1QZP=plBGuQIr^BzO8_`ZT+$=Nfh-AQ=>4%*1oi&Q6bjXJ4MlG zju%B^*rI4GTNI6Bi=ra7C>qZeMHASfXd+t_O=63pVm69O2q>CNK+zNeil!1!G>w3w z=>!zbAfV_j0*Yo5P&A8xqS*u#-AzEz90H2w5>PacfTH;X6fGd2XdwYb_YhFDh=8Jd z2`IXc;3ygqVg^2;6ou&TfQ%GH2WqOZIKNJQ=mCxwMa$WuXa!poJ;)YC zE7_uG6fP_&tVqAdgz zZ6%=SQ38s#5m59P0Y%#hDB3|l(c=UZ?IfV+2?C0qB%o*)0Yy&{Q1mpxQM4q)OjkhM zA^PX8mx`iz{Uqs`5L^4wigt%sD0+{8q5}jJ9VDRWeFBO; zAfV_F0Yx7YQ1lT2MTZF}`j~*CBLozELO{`{1QdNna1=ckVm_#VxJT(1_s@%>Ra()} z5L^4wijId^yPp+BCpcadon(umQ*2Rmnk|aXutm|AY*F+TTNIsTi=waDqUanOMdt}9 z`i6j_ZwV;+j)0=?2`IWiK+z8b6#Ym*(N6>v{Y*g7F9a0*Nn&F>CHtin8?&?Efo@iu4zcYKGd{msV6K)av@8D5}fxqNpBQ6xC;oq6TbH z)Q~NT8nH!DW40)2!WKnM*`lZ!8$~e$6g4NHD3*YtI0A~|2`FkoKv7Eqidqp+)S7^z zHUt#4C7`Gs0Y&WzDC$5!QAYxbIuTIRnSi1$1Qc~8pr{)GMF|8HB@!G((V^xr1;p)& zR&Z*EI%Yt>Db&`!w4&~z*1|oas0YW3qBOQB>d6*Gz1X5Coh^zo*rF(tEsC<( zq9~g!ih8qAltVyKE&)Y(1Qg{HP}GNjqP_$a^&_CDKLJGp2q?OPfTDo}6x~Tc(I5hf zd;}B?CZMQ*fTAG;6b&VyXcz%Sg#;80C!lBq!BLbFYCfTWxGU@L#-@s*b9L1i8ER`^ zTG7~0>(DErXdK6jq9V2^8qXF*6WF3?B3l$qVvC|;wkRrLi=xSFQ8a~(qNxNFO(URa zIsrv92q?OXfTEcM6wM-_Xf^>wcN0)Fhk&BF1Qg99plCh;MGFWhT1Y_AJp>djBB1DA z0*dYw1nU&8Xan0R6yL_^v_+75k;S>-?Ns6+S->^v?A1sdR-Jf$nm0R zC0i7&VvC~HY*F+OTNJHfi=wq`QM8UNiXLW*qV;SPZ6KiN5dw-f5>T{>fTGO=6m21( zXe$9lj}lO{jew%Z2q@Z4K+z5YiXJDRXeR+hPY_V_BmqUc2q=1rfTE`fD0+r~qGt&x zdXC^IdLYznqky;%=_l07MNudHyy*E*Tl>WIL0YyI(Q1lA{MZXeI^cw+17YQi(oq(cC z1Qh*2K+&HB6#Yd&(cc6VT_&LD3IRn|2`Ku9fTC*zN70E;bDsj@uBdiX+NH$~Aj{T-0nVYc?A71a;38t)fH4LDvD zHDrsTMr={km@SH$utiZ*wkT@G7DX{^QPi9*ielL)iX)&Xo`9kj1QfL-pr{oAMXd=a zYC}L#TLOyO5m3~gfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P?SJGQ6d3FNdy!n6Ht^w za1_-IGcy$scSrprMfJj*SNd+Z8mVEn_N5i|470``5JkN>UKFLXMNtM@6lJnSQ5IVi zWwS+5Z?-7PVT+<%wkXPDqbQ$%qCNx^^(COF9|1-E2`CysK+zop6b&Sx=uQHP1`$x? zBcNz70YwD_6b&JuXea?i!w4uUB%o+G0YxJSC>lvX(I^6nMiU%GJ;KaY3W)pH+6qpZ zD4MDNZ0wjYTl>t8a zrn6BrgMgyD2q>CKK+!A$ie?i~bT)0*dAnP_%%6qJ;z$-9tdpA_9u; zC7|d&0*V$BP;@^5MN0@MT1r6CG6ISoAUKM~g_$Q65cgF5bJsVP^D)O3`%vbJr_HQJ((R?2BQx_N5iQ5@sbF7DcaeyeN8& zEs9=ei=sE!qUcSwD0+)6ir!|6qP=WUw2v){-eIHYT>^^s6HxRX0YwK0C^|?$(fb4x zeLz6bAp(j%B%tUc0*Ve3Q1meYMMnrI`h1;qWT{u0s4qG)S~8YjbS?Mo~AGR#_ZL==6+@uKJ~TNHiG7DeaSqUbzZ z6n(=MMc=YT(RXZ7^gUY?U0|c=2Lg(IB%tUg0*Zbnpy(F@ihd=a=r;n2E)r1mI{`(P z2q^l4fTBMMDEfWIH0Y%pcDEgOxqU!_{-5@xMPKTMh6cD#p zf7S7fC~99pjhkV%_N5h>;nqj$>)GWK;|wbx{PtJ+7F!ervPF^27DYj9Q54J;MImfa z6v`GwVQf(p&PGuL0Y#An6uAi~iXxz>JOM=&2q>yZK#_-lA};|&l?W)ROh8c;0*a~< zP*jb8qUr<`)gYj#CILmY2q=mspr|$hMRf=$s!MPbxx&p$3W&R({!#04;m&Kc>snF0 za9jJ*iW-Gm6+Rb5jX7TKi<+=SQB$@kYQ`2tF>F!PoGprC*`g?pEsEmVqNoKMMJ)*^ zYDGX%YXXYe5Kz>XfTDH;6tyRyr~?5-9SJDvL_kqz0*bm2P}G%xqHY8fB@j@QNI+2% z0Y%9K6r~VQluAHRcLIuf5FAAf!p(LHh&w~SxNj(m?y0CoTDYx!X+;^~R{vw7D3jww zQ5IViWwS+5Z?-7PVT+<%wkXPDi=uqCDC)x&MSa;Q>PJ9Pe*%gI5Kwdn0Yw7|D7uq? zqCo@{`3NW)Oh8cq0YyUyC>lyY(J%sv3JEA0PC(HJ0*XcwP&A5wqR|8tjUk|DECEI1 z2#%s&;pS`w#NAf^+;zGrdPYA3t6oh^!Hutm{bY*93mjiOlu6wM}}=xzdv<`7Ucmw=*q1Qg9DplAUBMGFZix`%+G zMFbSxOF+?m1QabMpy+-Aik1*iw3L9NWdsyGKtR!Q0*Y1;Q1l?dQ8Xdkd{+T+*VT7F z6GhR@a5Ywj+uD~_v?kp8_LL}E%kiRU9a|JV%oauK*`jCzTNFLQ7DXG`qG%Ia6m4dU zqAhF`Z6%=SQ38s#5m59P0Y%#hDB3|l(c=UZ?IfV+2?C0qB%o*)0Yy&{Q1mnbMb8jW z^eh2I&k<1cJOM?!2`GAjfT9-(D0+#2qCEsh(duwBJw?oc^+uD~_^mVv3@vJC1$MK@* zJX;if!xlx~vPIE%Y*F+*TNGVji=rRcqUcAqDEf(wqMr#U`h|d^UkNDsjew$y1Qh*F zK+z=vivA#==uZNQ{vx30Zvu)g6Hs)8fTF7e6#YX$(KP~!{w1L3IsrvD2q?NqK#>t4 zFU(QoA~=e^3O658K-_)wk2jtbMYHs`L&`CyH#27ezsAQ54J;MImfa z6v`GwVQf(p&K5-xY*7@+7DaA0ilPW8Do;RB1pVtJpvX%=Q6&P3Dicstg@B@} z1Qb;xpr|?lMKuU0s!2dmEdq+72`H*fKv5k6is}+jRF8n7`UDg;AUKKwBFxhYh`XhJ zLTyDjuk=Uhzbdq0gspvPMNK2D>)(i?W*jeyV%VanIa?IPvPDrGTNK5!MNtd3C~Cp><(H#U74J4rG zP6CPs5m4kKplC1wMFj*D4I!XtC;>&o2q-EfplCP&MI#6(8c9IWC<2N`6HqjUfTFPk z6pbUGsEB}~@dOl2AUKLLBg~NshN!L%$<)J%T|WMYJ^eQ8CLBdq&=5JgisUKCAb zi=t_4Q8b+`ie|7y(Oqm&G?OigX0b)lY_=%6n~kD51Qg9BplBWeMe_+LT0lV2LIR5J zA)sgx0Y&!`P;?&wMT-e2x}SieB?J^LC7@^-0YwiGP_&$Yq7?)bJxD;&N&<>j5m2<6 z;3z7NFrQXH-1YQ>Scxcl-v5Fv!q&dDqK6}_kAD(H>p5N&ZD5O{N7$lhBU==0VvC~9 zY*Dm@EsD0XMbV>dQM8SXqQ?j*+D<^x4g!iEC!lC20Yy&`Q1m1LMY{+ndWwLerwJ%} zhJd1H2`GAwfTHIKDB4Xx(F+6=y+}aOO9T|{A)x4G0*YQCpy*YCqiAh}`KJQno}qv4 zdYvdrE~mz85w`ZF6}=Tw;V5uzGI7`@7bd00$UXQz!pV6vPIEPY*F+xTNM4m7Dd0ZQS=)DMHdMu z`kjEHO9T}CK|s-;1Qh*6K+)d>6kR5u=n4TvR|zQkhk&AM1Qh*CK+$yqif#~4bd!K0 zBT`Ql$fTGF-6jdRh zs44+P)d(o6PC!u&0*Y!9P*jV6qG$q&Y72(I5hfd;}B?CZMQ*fTAG;6b&VyXcz%Sg#;80C!lBq0YxJTC>ljT(P#pS#t=|6 zmVlyh1QZn!P&A%^q6q{PO(dXb5&=cU1V>TtNHa$PaVP5^DasK=Y5HYUYqXgbG>q8V&abQfC`&18$BS!_`>n=Oj&W{aXZY*93qEsEx`Q8b@`q6GvLEhM1m z9s-IM5m0n50Y&!_P_&qUqWcLbT0%h4QUZ#W5m5910Y%FRC|W^4(SrmOtt6mm6#+%7 z2`GAqfTA@76s;vVil#)GYZVZ8w0;nqDvG|*iq=Ki+Lu=JNTl`3HBq#Y<3-UXwkX=n z7DZdwqG&5y6g|ooMcde-=rOh^+Rhe5JJ=|CoPeU81Qb0%K+%%~6zw9Q=qUn6qSpy1dV}C7 zS|4eCserg!sA+8wMbGFbNpD8l+LuOnwJ8UaN;2`K7CKv6mYMHvJXWfD-7ML+i(9xA_9uW6HqjPfTD>66ip(asF;AF5(0`Q6HqjT;3&#-o1GL8cQySb zqI^;GR(Un1x^3-CE4s^V-5D&3W^%kJn#C4Hv)Q8PZnh|z!xlwz*`jD3TNKS_i=qW= zQM8baqI(D^T0}t6y#y59M?leH0*dY@plAsJMN0`NT1G(80|XQ;C!lBr0YwiIP_&YO zqE!SGttO!8Ap(ll5Ky$1fTDE-6g^Bp(RzZTXu8{+r+~QQqZOPPqG*)<;?V}Tt$k@l zo88uB)=s5z4o+qGaHvvU25K#0Y0YxtnP_&1DqL&FMdWC?ZR|zP3jew%p z2`GAlfTA}ED0+*4qPGc-qK$6zpaSB~(%;74B#N5pKM=ClZEIgz(SEn}L%1kMaKvzI!-{*2?B~v5>RxCfTGg`6rCZU=t}~Mz9OLLECEGd6Hs)HfTHsR6n#TL z(YFLg(K~K4B0?$Jr@ut>t|(fgzZ?6V+t$9cq95H>tXmZQ#POo&XSOK%g)NGHWs9QU z*rMnnTNM4y7DboXqUaB{DEgC)qQ3|z`kR2F%LEi%A)x3g0Y(21P;`xeqJIe}x=ujR z4FZa85>RAB$;);Wxd^Jt+_w)UkJMMhbZ%Znm6$BUvUwkRsk7DW}XQ4I`kakbt7$1Qd-RplBokMWYBP8cjga z7y^pM5>PabfTAJ-ipCRAG=YGki3Ai)BA}?4fT9utiY60KG=+eosRR^FBcNzH!BNyV z%50#3xcBI1*Zo9Mz1nKbh_baWt!Q?X)xC-+x|`!g(HyoYn#&eN^Vp(jK3fzmV2h%K zY*BO%TNEu~i=unkD7ue;qQwLh-A_Q#5(0{r5>T{^fT9NoC|XWH(Fy{J9weY>B>_dN z2q;=jK+!`46s;kkXe|Ln>j)@%n1G`71Qcx`py&|-iZ&7)MKhz!u?mRW)L(U+C5o=- zzszV;l&yVfMUO^VORI^ZZ5%I(9%GB5?QBuBgDr|4XN#hpY*F+CTNFLX7Dc<*qUb3$ zik>E*=otcvo+Y5@IRc8FC!lCI0YxtmQ1l`JMK2Lhw1+0*c-tIEuDJna?XA?zUkH&Q?*hP?LH$%GSQLqJvS^ zXEj98`y4NdK46QYLu^s>AzKuE#1=(|*`nxUwkSHn7Db=1MbW2h6n#cO(NO}5J}02) z3j&Ic5m0oTfT9xw6rCiX=oA4(rwJ%JLqO4&1QdNmK+#zOioPbG=o|q>=LsnKhJd1P z2`KuGfTHgSD7rv!6ulQ^UQs~YpX%?%9uP(I^q*?{A=vR&xMZd8{ z(M7f>`kgI`F0nvqjNmHj1tgP;`}mqJIb|x<)|JzXTLrC!pvC z0Yx_nC^E{+%XSpG2q-E?K#@s6Q2+r&76C6a^7b6ih%-2mwW*1Qdl4P!vvZ z6#W!sc2Pjw4@N0CKl8jue>)_iysdp{Mdiy|zB;0)0>_J@ifmEjVT&R!TNG7di=xVG zQB;L3imI|jQ8l(Gs?J7H4FZa45>Ql&fTCyuifR*3REL0~x&#!}BcP~00Ywc6C~8PR zQ6mD18WT{|gn*)^1QazRpeTlbqUHn?#S%~yM?g_L0Yxncjv{w?bAbZl&eUIZj4JQE z(%-1?SS`!j+Lu<;w!HONJyFz-<3&+>wkYbr7DXM|qNo#F6m@2cqAqMv)RirYy0Jx3 z0vkn%1QaC^P?StSQ3?S?sRR^tC!nYY0Yzy96!j#as22f6=>!yI5Kxp!Kv5O}McD)t z^(LSwhk&A70*dkoD9R_Gs1E@}eF=`D*5%C)6cG11{jIY$qG*@@1zUMr`_hUAmbZRt zAd2qfcu_QnEsA_>Q8bt>iVE1GXb4*r4P}d>VQf)U$QDJz*(e%8K+#A7ibfGoG@5{- zF$5HiC7@^=0Yyaw6pbgKXaWI66A37qL_kq70YxPQ6ip_eXbJ&EQwb=VMnKVY0*Yo3 zP;?goMKcMGq5$qEXJO8@#2N%kadgXWfP;OZ|1U0iKEKyCgxLmFj^o z%=4mpQswp>Q+H<-J=MI1QQ1?VP*(TsP*2&TJ-?`DS@k?E)gQiXRWV~%H5u3;?jypwMj_j-c+8O9P%)&Rp;?pZz1Fjjd^4Kj?ip4tV5vB5K9 zs9|jOJXL5I+dO}aFpS4N?MEBNF3;U#4dYqQ{vyM8!4o>sFkbfbE;fwUJ!>W##@n7V zQw`%?Pu&@YanLhrreS>Od1kg@9P#`$$1sk1I?gwYj__M7~gnu zml(zc&$?xX@w4Zv<%V(5Q-7sl{OK99+Aywoo?BxW|9UU4Qy!zi%?Bw$5e-y8q%lpXN>I!jr^*>A1!{ycg zu28zmtN&q`Y?oL6%N}_yul}bQ`nkON@75pa^6I}FeXz@`|90zPF0cOUiATD;`tO$= z>+y16@AlOUj28h&2)M7Uy?P)<<)=7(E^uO|1~xDy1e@D8Cl}; z>c1#rxy!5nr2i_HSN~D%wJxvzv$h*tUj2t9H@m$0PrGe%dG#MxdfesJf8J!5%d7vu zz_Tu|{)z7wTweVnyDz)E`e!a*cX{;>&AsjN>YsXg*X7kewsO$r)jxOeq06hkaeTz( z)!+F$>hkJu-5hs$_1E4{yS(~~r)OPW{nf8;TweXt-oqn>c7g#>ff4owJg+4-+q+`qjHM+9=NOJEZx3PTU`@Im6B?z zwT^f|y&d8*40Rb8Rg)rAYvXT5)t-8^m65J)!LD`@%Bgy{Y;}%Z?d5lts2^o@b&&C8 z6*W4__*RcjGWzSY)mg@XI%;&05ul#rxVp+{rS2nK-JDTPy=~~v{kIsG5}O?u_4(41 zm+q?W>TQKpIUX2U-IZg7CB0Q=W_4F?VAO_aAQWtmX8t(~WA$>XX+Ws6PkYJiPTU^$zNwg;Vf_Qc9*MzuH9 zLHDbJwm1j5;*4rXHM($lMCu|QXl-njg!k}_)qBK3pbDG6SBgtZ*3cCRI8~j zw6*GVg4BQNqOro}HXZBnf9!}W4cn+gtgy_JcNF`Nuzsr9(Wur<9ih)|7w3q;s67vz zIPQFo7r$G4WxD^vT-td4A^kZ9M(tmHe#1Zg%y;`1I%jOf z_M^x2MHv{i;`03`)ID3xh3ZaS{}))!46M0Qy`ldLG}Snx9xC*If%VOhnmZLQ{a;{! z8ECkoT=gR=gqji6BJwLmx!jc$$a+R-Xcv_X!}JO<+%39H}=4ZU>= z;o*iE#K#Q{4G#?qZKqBzqS9^e6{+5<%(-*Rl+%uqlT=fmsq%7?{@=ZIk`?46<-IDZ zgREQU!xOGPOZ}0({x{TTQmMJCYZX3f!zyVNqFm(zyH#G3SVe!3%2t_kRIbvVM0Igi zY4tx_)v`@rQq}I8=TcWidJ00< zgxmh7er!wKv1aRE2KwLZuYXBYk^+oBT-lrSTZ7eq>h`98(f4uAZ>abBFaJ|Nk*eOc zxBf-_s{XH^{-u?iT<=Z#E$8I=l|8xMoBro%DNE|u9Q})PMBlPUOafqHqofQNx#{~KfCIw&$j;5^?UjcQ~$5J z`cGx`KXr#K|I_bN_J3t}2X%*T8lR~{%DJvZgc~mPKlQ%qKUeeSv6Bj7hZj$XEuJ(q zc9O4nXrXVyr12$%LrV&W#SWb`eL~529flSTn>?woxXkbA_gC-TK6b*SQR7CHjG9tt z#Eu+4t}wP>Y~i%n=3~bXEf^bHJhEU?VeF*BqQc^W;@H9#zT%R}!$ysdEg3(4?9h<~ zql$`SM+_b6E0{DcHa^bR($^xcMZ7OQPRAG(V~WNX6~+`63>g&@AJ@EPjQ;KB>bGzE zt=LgTL&r`YRv0_3VCcwEMgPywM)CCGvX{h&k+BJrhD{z-G(Ktkq{5ie%VJu|B>zR? zTq4<%#*bE)d2wv+gn~(9QYRPr^3>-tB75xQVqZ=|n~c_6P3n{V|MArSzaW@WP*SL` z3&Rjb?OP9TK2$674J#a8FnMf=uVng!!s6y5HC`oQ*r=isH56Rs&o^}ZxN+l)d<7Fm zsis`#CZ+h)r7|?h-&IrhXZReYKbDgW%ccIlR4w0Z>9VW}|J(m8SD-n<)!eeoDm|ms z{{myJ@`37rz+P4b|F4~`n(Eh}Xe&6-4DV!BQX@F9v*q>w+Qldr;PP0J`j<$nzWzmZ z|7@<_t%Z6wZ|&H|u~x%omN(w2)KtaTz{-}_oS{!JHn5WAt>%BjYk8~t-|$%88u|_S z2&KRBMrSz-u~r@Rp~9lA@W3usHT7oISgUazt6B{eVy&twga^hsXRm^D_8QCC^Uvn$ zw_8|^^l>e$YEAqH`Ai^4X)XJ)+&$#meJWb^d{gL>H{95O>kKCy2N7l!;P-oE7 zG&VLa)~Z>*nL5av%E|t>Q{z-`{aV9iMX3`tD_Y_Dmq52wQ~z4Wsp{O}q@zjJu3 zRilF$e9Na|7g9!Yt*`Re$j ztc>jRlsxsG`I%|*eyK@4d_!)%V?s`{FEcAoy>o6#PF_lK>F@N+RwtUDnVX-Touz-n zmz~xxCEb^rm6MT>=X^wUQn$Z*VtQ6mFJE#(UV<+(KO-?EM}Hn!InH~xY*+RJXJ+|w z^AmHEa?

    rDo-4Ci~y5ZMz=+U)$eyHgi&Pv$NDWbWW+2dLJ$eecn@Y5^~F&b1t`x z-0r@_{M1x+`nhQXQc4f`AD>xThQ2iY@1rlt#JI9&G%eGY&j)TVXD&YVws%R&>7SjK zr9S2KbYFH>T4r8~e9A54{S(x$>anL~3tx%|~ezZz096VyyLvQl$> z3CYgMwD!NZK4+i9$db@>>mAn>blNQ*K$%qURqYBb2+syJup70%#mq1y?u$w zSaMpf^TD_*os-lj=D*r}>1mn0N-wp(X{l+xglzx0Ov=j4Oi9vO{PI#;=?l#NX0njT z%}+{FN=uK1Z14P({1jiRx}-{fD?1@4Ew6v+)TlEOGW*L_ck3klS6gmYuKye)E7hfE zptb+w^I6FIrN*nW zlbfJU$bVI<3s_+DF|%@$e7Sj9>M~7H9OXK6E}PpA#yvPD|+S%gWEo&d>Ap z$x6>tx24jP;Fh89VDw#)z8foZOHEGclct_^CFbWkm$ zvqk9zmRRP((O1^35AE15^V{l5Q5T6XrC(A?N^+UAEEkBnx6MmX_ZGcU`ukE7()2B! z>r>uCKO0qNEh|4qy`gSzsp)A+w;lofV)Y$c=|vacqV&eDZuSOOe_r7<=PoB+-7tqu z9ye}!=?C)PPExYcZofToHq`xdMpll#ZuA|fL#T!SmNRyI(THeuZ{}~U)W`CF^6}~o zj#U?EZq}{GFa3B>`g?MRoRgBC;=j|@2dCVQ%DLM01)#3kv{dI3az09%G9Sf%horA5 zeb?uIn3HpP8zSxvdfgHf9@kAd7;)uVRzO#dUc|DtKB-bKHWaNE6p*}IHecV+P@rB|bV zv-E6=3I##k`19p)P@T&GxY5ma#p;GD-eb-4diyzSmRKR40;IPS~sp`Nrj z@2T$FxR)#QAv03c{gynN;UnqOi&uA_&T%PzN0W=ne){@7)WbsQ8BcDJERU5rDVfPi zYneOd(knR0|Ex&Ns7tYEM4_*+XxONNBA>o3m7Z8ydU{Itgmk&dsfYh$bq8?k@z3wQ z^r5QEwH)8>Ht|BGhdQM)&%ToRwA7XRA12cDec^xH3zdC#q3#O&H(~$9Q+msYZ++Vd zar5EYD)T^p8=U|8Fn7yMdUBTkUbXa*M6P4!Dp7Yba#hC1%OjS0G%vjXxvj_fl6&X* zl6yE0=(j)mw<+`fazB-!?uqhq{Etok`@&Rpf#mimbC-z{McJs~3_q4Zqn%SS!w;$l&^SpP+J z>sB2f@7K{iGe0`1efwzrWv%A%(fSKpaqU{Pif%NiaBN{gabe@=m~lfVOzu2%{G^h? zX))tkwp5{H7d?o_=G8~V~Qul42y50O2MR|BRi`v zlTB$CGp_kK^@X;k!-^*~9X=sCW<+#MR*UEu_2rk&L)96G89uJCxVT_MVa(XVq7fw{ zJIATy+{R+G6t#v=E*e@gYJ5>lvHA*?`n6cKVd}|D>Gpq$ZEy4EzwVs}7yU%ue?_Kb zX6389Aivw&pK_NzLaAqM35jXxX#;LOZH`lSyZVrpx7~T(x~1!zODVZqa@C`Yx(~=x z&p7o%cIi8Ct@&RX-MTW>Z7NAU0Z2?xub1RbRDVqMRNpzfZEs0e5A066{dI|c)u5jj zq^Xw$&NB$-^YmjIl|Fv_gm}aMON;+;UT%9pzU>KchB~FhtbYIFh@^CNf3F@v_5G3m zvT^QHefmLKUt95UE#!Qc-r1@Py!2#lT}t}Nnolk&=Lq$v=zl|9ola2qRAp{1{_FMD z3$*`u-Yxfaw?8zrQm0ht(_i8%oHWTfP4#;1znmH8j#=Gu^|^AMfyS%Xo&G~^f3>O~ zS8hGkQm;|v_NHHR`!9C&h9v!>*q_u>W&az_Yej#GD}68LE$%GKJm>R2Q&lf+2Woy9hG$(}9bASC42 zavb}f7JDd^J+fw(N=YG=kkTS8T9qZzDx^q}Qi(Q6rBZ!g@423jeE^X@#h>1l@? zTIATXV|a_s`5^(j+YZUSzbW(X8UJ7Q!CGgx?s)DF;#oZ{ZD+=j>t=^_b1y%4Hl9&y)&axS;Mk#Jij z_ZtbWZhN$22lr%jy_#`W_PpiGe<@bv8|xoeO$L6mbe0Y0ZyE7`(3UG zcaIX^%JTzd+r?+^A$J@$ae%~aao9nDK9^@@hezkkUGCYqb8LIRd%Lq67mhpICwVtV zbC1i^;kb<3W8;qE!rb;nbq4iBHZlX;IqC-%+$^}KO* zi?L;^|FO;J9^fllh5M=Opq=}(@9?r~!Nyr)J=`JX#EI}gdHbwheOh$rrWcdE$B7fG z_Mb0};jR?7Gxr!;;v&x;aL%+tUU`3%&K{a^H#YnsIOoYHcL&^EV(#6T*IVu$tnS;y zvEanj@(h0VwJSWZ>%QrB+Y)DTM>$#R#EY#x_U5*Q{h0mtw;jTxxMyF9{^MyTlMVh% zcNCP%&b!L3v)kDQS>Ap7vzsJcySC8#FX!A3;02={xzv`z4dJGFV$=y=A;Y{3Hd5>5oApE!2-SAmB_ox<^n|N1+pL$C7uy*MlK7+aE zTY5b^+hcm}LD4+>F?Kv9@etZ8^?#D$M%dGxy&7rTUGJ8#1JvN01zEy2NKJQ3+Z4&O zjlwr`-_vo=@QG{ZMKj#X2;JH3NbD(v!rb9gZdP6e=e!%D+uOZEPKS;?!@GkW8FvWX zU2eFSz$G=e1IG5&SmJGq#JAmE3g67Lxp2<$k;Lk`Be(8^+lNUM?wDlaM0niPon)^i zGws=4!~>cB(dedG5Eyw=Xv&(*l=?u_rRh3xUx+mQM}ET86NLUT#P%s zm^cw`3Ukfw8TZ^5liZ)PygwS@n%G4oeoS-kj~4B++IPzHN*wZVZ#ZlZdTwtccPEJJcdy@x7pDKV!|BjCb?ijBOKGj! zm}!Tfa_?X6i|_zsp10t`E&s%wlXrVEv5VHz-d1&QEO*p9rL0nT;u!TqrF*X&m(p`Gpj?MgJbT|Iro4^ zxWf@{f1mTRm`7H-K_kMSpR>n3!(;rc=h-c6uce|CWs=MdHy@kXno>;>} zi+%dAOUni4d7f_5CC47S@JBM+9GpF7)-%iYnt4k7*OKmFjeCs@@2;~)C*5(s+_UB$ zAa?s_mv?b{!~eRs&)Fk%yb||^+jHSUShW^eE$ohO-6!!HA8}XDrwZ7aanST5ns?77 z)bp?FZPC6ZM}PibevXrmfrg*oOK5gS58a9I>4;mEc%JF{zuvOcqr*+l-Q)`QY7!Tl zILMgz$<7)yIf=3+bN9kp+dJ3nz_?FWL@sa9qEWf3?s$II zsNv;W4evi_;6QtOt{b0lO&sFqldIMK_W^(VSh;;Qql9GrK4q%Dn#uU3I5|NZ7Tr3h`G;l=J|^0L&#Jy z_fgI~Uora_r~3@`*{|e?{YpsU6VhRK_T$Sg$0GKb`#fK~#|BpJq36 znq9S<&Fmp`)BWOkn%%gU-7IRqXr{iDeU#RI?IF_GP5XXZW%tM=+1>AqCfS4P?nyUo z(Zsah;fW;KH_N+e4?|V;&Z9eDea$AC%{4n|cGt8|4=2uVzbluRBQ>XL&eU9}`H<$b znlEW?(zIVVOI*%7n!7da7s?X-LCqtY$25P`{6*7#AuMrz_rZC0d)!|vcGG_0D=`ae zy1z{0`m&lAXkMt9so6lYiDnDUY|W0E-8HY&?58zZ$C?$+F| z`I+X|n%`@l()?31$(~Z({gbL$P_wvZ8O;kcYiQQhY^0f`*+#RYW)ID)H3w>5uQ^I{ zg61^MIhwa?F4kPGxk~df&8IbA)ZC=`hUR;kdo@4N{6h1X<_XQ;H2>E0?4`urPZ^qp zHA`uh*Q}~}k!F3(CYmiZb2PhXUZL4nbFk(J&9R!3G-qhe*Su46iROcvYc!wKd`|Nf z&8?bmY3|b8r+G;8E6wjTf7bj%Gitv*;qIS6vw&tX&GR)YY1Y)NuX&kf8_mv|y)_4D z4$~Z~IYo1h=0eS-nkzLQ*L+U%Rn0dv-`Cu)`MKtC&7U>TXnOX7f6OvTY-{Tvv0L{q~>B6EvT(U*C6mljdproi&&3_c0Q)Y1we*XwEDj<~udtt{CQh znguI|`FzbDwt?X;Z-D0V>S121`9+N||EO8jHbmU{FV-B98RnZcpQ{_@Et-E^9A@7( zT-0!>N*?LBpyJ{|& z73QUyd*+1sGtCn7!+e3}H4DOgz2@rM!~C@7aofOkkI!$KwHJlCiRQS)VVC7h4}`} zM>mIggXRxg!~Caaz3pMn(ww*>%yTq1zZK^9G*jLUb79SPJHvd1=3TqO{GjIkJz@Sz zv&@HKzEE@EzA%r}eC*>ezo2=-{^o_dy?<%eKNRK`nv)KPd7kFhFT(u3X7E**i)wZ_ z8s;lC?>-jhhcpj-8|I^$<$efrP0edhgn6{)6DPy`lIF=%Vg5(6;csDXr8(vIFyE@V z&33Td?c1%H_IH?zYj(0@5AOR{Yu;mjh{EMnnxEQV<#73!W(C_pbNM38A*o>=tGUkp zV2AtuE1IWlN6zJF{%|(3KjGo><(kv%Z+We(GQn@f^YF<|%%;PoJR|@m1n!nl~2XV{Cs)Vy~wQy!@uC%|o zFw|&U4c)zo2pv&64UXDOc63 zslJis<(l0z`)Q8QyjgRu=3>p2nontNbklCv3C#=apq9(MHSf?|sku)x)&9JNJKtrR zqujLHGfs1=<_ygRnhQ0TYTmDDcS+*%>>?7gsAfsca+;MiYiZWeyhJl`e8kr43gxRc z2Wr~OW#aO0&>XEfS<_yg65pSzxj=KZ=A)WVY1-3m;`}dbzNYz+<^j#mHNVpQPSbw; z6U(PX!Rm}V)>#BmV2UB)wU{(71XHEpvtk`#o;$lT-NzT8aK{30pLc1S9cRKWgr zh5AUX(G!M`>DS-pm{H*z!YTXU^q5F3_eteQt^T7&M{3z;t82NkR(Oo;e;#p5oN=K0 z6pX#)aP19t8Hv;V`u86-Xk2(PVPk*fAaCq9%Kb8dt|&ame>TJ1pD55J+L}gcxnF!A zWWT?Y=UT5F)o-|+DXUBSTK&e188x*3*fDmo|9`*EvoqS=ntL?0-oF;KyE5@r-u`vx zi-j@r@AJ9uxvwhrpFK4HpXaM>=lS>b=KV7i?y+=VHSE7s`>&b(=e~*zj7Hknv|WkB z7UGIla@>|$F#cS2uW^evY2Uf#xW z_Q%z%bC+kkZMm1X)K0UEos6W`56|aLyDz@C*iPrYym#|lo;y;``aPa!89Ny%X_wd3 zcc;QHF7FYGc`xr%yFB+ex%IOj$=u6(!A`qnoCo*S(++Z$sT7`e|GMwF|F&v!zOi<2 zv#oV}alZGhaHsj&Z0EDxu-q?qJKWbh_Fvxh`!dh%Eo|T8_I_%ojna)a5?`n7@){9r za$Ronv*Ny8uYc73{Fwb!9XlPj|J>!d$H!eKKSOphvU-4>&z;a0muDo;Io~N;KleP! z7w60U^BF^H-EdL4a^*4`)UMyKcAbWGF0s?KYiH*9w|@P4<;q=hNrU>e?R@3R^-Y`F zs$J{wue*eo8nq+wT&`>0oSsNt__JO$QqrDDYaTn%abvp~>-V1CI5Ojb;wQ@b(M8Qp zRJkSlWK!3Btrxc5c6w&*4LRFR2P3zg-d20>>Ez7Fg?}FCcw$J#(>YIPmm0q9bfkRm z#J|fD|9;~B&D?f6dCRubhYPN0#}ct29ZyV4ci-!Hszj-1#Z_%rXKy?GUAa|l?BCj} z+OD$eIJ|z_>C!9y`R(t2I-Z)A8mVY$;kMJeGLH}w-$2Gg;{il;P1I>)Y zY^B>#>g?_4)VX}Kll4XyZNICZ-4=VSR@eT}Zj;j&NjyrOD>Tf>-){TqNOb$@z%U3FYIsK$ei_DEQylUp& zEe)&8ZMJ9KnM%ukdFW4j!>i$v7VnInSLN}8OY2nJc<0)^<(oyL(^kZy(>~gG@WCf1 zwEtn*O|vHNE%A7doXxGP-*o)pN4{uU{`vuxmR0{@-^pf=?frAdqdSXy_2t6We;gfF zqfF`Q-FH-3GJE^0$G`ft^v;h@ZkTf-$qRx=tBi$_mv&!trgW=6x;)f2?Urqg>m8dF zB-{TsJSCEB2W?Y=!;#%~DkX1`O} zB&SK+rrAw-w2~qf8@KzyJ!1Cr)H|vD-iEDX>tFrm#2pQD>i@^jN1fcCkIeu2^HDRW zX4_iXwazik&xcpBTH@!UT6VRZ>WOO~@pZ=&(c)ZR<($fGt7KOR?N=;r=iQjOXz2dr zGkYs`PFs+=9-X$Mk!>QSZGS z{=V%%yLS#8*b=w%jJ7xS!q=hXXwwXPAL4J@1E}j>De`%a9-Cgy{;6H0o1OOVuzyl=3fP;L$&>74a!!8tcO(7H z?zPQ-)h;gTpS0JpBr9zpe|Ql)kN=#lsONuRuWKp(uXft^XWPXG{tP>v>TkC5r}@3? z64HIo)+ECpT+ZGM_201lp#1*2GPXhBceZ~E`UmZth5V{^*f;KvvfEkMzuV4J#DC4U zK#KZB?eK3g|1;ZSE$-)3w9R_Iq@6D5ziZnRrTndS`aFM~-HWCDZFbHwzT1r`>ld}A zod1YjV|l-@T}uW3L%Xz!ehJ$vsN}mpNO^((mR;IFe}vtsgZ$2w?1j%CQrdQZ{iC+d zZ~H}U*Ww+2fxRNX>o>LA`<}ns&bc$#Z}&!xXpm%ARx=vhY3HgH4SL(da8Wd*B_?^+<9$V2x(O|sYcXvmF$L;P~91XTxx+fZ}u?P9yXt3TcWl1#f?FyDg zgLd}4WznFat>7TG1w-xn+9d~*>^^Fr95k@C?vNZzu}8mSa!|uAtW$Dupc|j{%m&0C=W-Iu)7d&eB(idJZ(AH&_AMCSp?)HOxcJJ=-1GjVe zfgk*85BXj{IB2W%p&!h!d*UNMc-P8(wt(HD{eG~~7XR1}X4~q%m>zU9M=zxZ^X5 z<`xe6*`qnHaIo4IFIXiQ?tUDq1VioC-dH?nVe2xocyOt$*{I^daJ$;k#e+}moMVay zOYP1YTReEo9;$K0gNyAN#upFj+QV^E@!%f22PYH{+y^u!77upYLws}bV79I2q~gK- zb{i%a4|>@OPAMLIZ;MYY9$aI0c<`XDM6>0=K)c$k<-tdGVa=BZ@7dkj za(NK3OKG({C}4L;>*awR9gAGPJZNe6M5ot-^X+?`Uk~QnJ>U0uFxh?r`W+8)Y<2q| z4+fcu0mp*}>^2NM9`vzQ8gx8pV7KAg<3SNy>%qrU58L-{EEJ8T9(e6YuJI@$*BE=Yvbti7OyK$U5(Zw!hnmwec7uY>I-JMusmvf6dahu%{Gu(-F z73|Odx)Yo1ah>H(Y_l`Zb|-e*y3BDW9Um8iR?w*I;i3ZjL?!;QVu2gs81$!XU+=&`?$?5LICw86;cjAoQK>NFm zk<@wi?33S}IBNHI0e9j}J99yIqNP0^h1`j%_VBvbq|`Nbj}>+&ezPkr;!Zqj4{}j= z;*?#NTkF&^_VC%EuSn_)Tlpk+qP1Ox`)F6{GW#J+b|>ui*{!e>?%n2+wQuINp_;Fy#}Vtv4=Wevg`9F zdzHN=W}!gy+7Yjc{?9UHEoMf%s)}VS)`@u46wkL{wiT zvwF&Lmu=N9RxaeSty_KNf-c+2HBc_#vaMZ1<@_$&>RqCo&t+S`M#>qM>)85Ts+{h! ztzTp1G?#7tnkc8bZ0pxlIdIw5?=ofIWm~^y$|)|}`eiA5F5CJwS59`>)~|)Ked?}x z9b3Pa%1M^%+WNIpj=F5?*IL;g|ANV0rC1+({0j{*wI^Nx(kngSVp7)&`C*);syKOWjguJ3fC1j(bguJRKA+IS)$Rm%Lf%wH$Xm(?d0QDF?PY#$_Ux7jF69&5pqB|6!K#1s6GCL9(BjkH!g#4h4kRO#1azYs)KPe;Rq%uN&Rz}DvWrX~qjF4ZI z5%QZdLQX3qWrX~r911xYbGzMzZnK>t?@&TWe6c%i zN6{ReNa18JIchs1w#Vi6X1u7DE^FB~dsE0|EZb(ePd?wWZI%b*(w1$rJe7Q&W!o%I zBbTylo8{@`l9p|=JcC@qvTc^n}QTYTw$wNh@!A7 zY#rkiaaY(%7N#iV3R}w}6a`&jt67wyfGcc0i&5lvg{^3DihQoHH7!ArVTIenDM^v; z3cD{$QKY%T*7Q7zR9D!VmZk_?VQYFmh3^Vm(=rq(uCO&NOX0b~*0dZ&vMX#&%TvT$ zVQX4}BFPH3uTzmC>Iz%aN)!g9XtI|Sjde00@fY1LPAnQKYG;QUybGeflb6qM;Nhx{d-x*HfTq7zK)kQ=n)B zMX0Dy&7wfjYzh?3 zp+M1G3KY$wK+${(6x~XJq6HKvx{U%ww^N|#4hj@4q(IS~6ezlj0!51`LPaB^u?qHL z7JuJuIFFK|YA)Oz^_?%LXi3y-VLRjrMN3&;ik6Y3=svO(EhkIS{bVV6fGkB1lBH+` zS&AMaOVLU)idIpeXf*|j9;QIi8VVFWLV==3DNwYQ0!5Eepy+W56g@$Kq9-X(w2lHr zPf?&~Jq3!Mra;j%6exO@0!7bJplAaHik_!H(F+tPdXXYjbWb!k#DK)VbK6DtO3^b; z(MwU^`ErV0je7I!eVT-#*H~VPHj$-hGg*qZkfmrVS&CjKOVKv66m2I<(Hmqb+CfIq zn-nN|ivmS&Q=sS_3KYFdfui>)P_&Z*MekFfXcq;Fc2l5e4+V-opg_@H3KV@vfufHn zP_&N%Mf)jG^f3jB4p5-z6ABc4N`az-6rrM5qOo-bBtFZ**~oU0y-nsFiu%r%Q}jjD zd*9yQN+>$Q@>29AS&F_QOVQV4DLP7)qHoAjbc`%T$H`LkEm?}bBcteh3Kac7fubKN zP;`O&MHyr%%14%>{A4LAK$fC{WGN~{Mp2vsMTIF)RD=RWMJZ5Ji~>c) zDNs~`0!1Y$P*jQnMdwkVs5AwN&Zj_88447Yr9e?R3KW&6Kv4w>6jh`^Q6&l#T|mKe zQDq7gRiOwKc}cNG1|(kB-VpavlEOXxHTHP}uWFL-d^trmlDsRcN>NRgm!eu^DY}R( zMYYLNlu4GNI%FxTOO~Q~WGT9sEJgLnC~81~qJ|VGx`YBnjVMrbDFuoeQ=q5`1&W$d zpy)CR6g8tjQ5FS?np2>t1qF&)QlO|61&Ufzpy+Z66t$s1Q8opN+ESn>hXO_IC_+Wm zlVZ~hNc=7P42yT66wP(-T(nQ}oiC@TbCUN^bt&q?@>0~5EJfYOQq-L+MLoz;)RQbl zy~t8@1zC!ElcnfNGK#LEK+)9{D7uCMMSUnx)RzK9{U}h>p8`b#C{Q$z0!4!;P;@N? ziUw1lXb1(0hEkyDItmnBPl2Lg6et=_fua!4FeKiZXXo# zI!RFl_wqI>$#=e-qH#&yQTqj*#CFkmmY1TN$WkcVO4h4$lQlMxa1&ZcVpy*Z#6fK}Y(QOnc zx}5?=cTk{cAq9%=q(ISK6ewCmfug%9P_&o=MfXsIipC_xGHRNlJKRynu~JmiJu%&z zqc`4dTmZI0mQnZaMMcc_z^afdqc95m$O|lfdMV6ws$tZe<0!8mqpy)jc6z!xy z(fbrA+C_n)-4rO=LxG|XC{VPQ0!1HEpy(qC6z!ux(S8aPeN2I(0~9FwgaSpMQlRJ{ z1&R()py)FS6dk4r6}^@eTVg=s4c%Mxo1|!zZB=`pC;85oQ}k7m_flOc`kLjX=qOo= zz9CD|F|rgLCri<{WGVWNEJfdwrRWE;6#Ym>(FqC^{X~JHlN2cWnF2+pC{XkZ1&V&9 zK+$g$C^}7nqTeY{^alls{-i+B8448rMS-HfDNyte1&Sgu?Y5&RN`ayz3KYdCP?Su8 zB99_ebR;Qu$biHr+dCZImr_*59fC}W`OcS9los>;xmb$QSzd}V$WoM#EJgXrQdEE} zMFq)HRER7^ak3N@CQDHfGKz{)pr{xHii%U9s00OyN>ZSx6a|XTqd-w<3KX4Bfub@L zC@M>VqH+`{Do=r;3KS@+NP(hC6ezlY0!5W6P*jBiMO7(KRE+{f)hR+nK`d6Oz9~B4 z4iTls!ae8@EJbz6QdEyDMHiE$s6JVW8jz)^ zAz6wpA)}}f1&S`EKv81~6g8nhQBw*OT}FYTW)vvOqCin|3KX@VKv7Ey6t$v2QELhm zT~2|bHWVnzra)0!3KZo~pr{=MirQ14r~?IxI#Ps+YQ|#M8IX7n_gqv0pg_?;3KR{ZK+&}nC>l(Gq9GJ08cKnp>nKokJq3z}QJ`oz1&T&cpy&n) z6x~RHqLCCR8byJk(G(~eLlG+K5{s=jAn^tEOG{o?DZ11hf*c$3oiC?oLd@IUSc)dH zycFF`mZC{yDVj`{qA6r4no5?UX=EvyPL`ru$WkqCnAl3KTs} zfud(9Q1mPXik_oD(FO_>Jx_t67bsBlA_aC{Zh2V-i7rx#eC<>DSAETU7aOG+gM(Twv(mk4YCyNAWPAkWGQ-!EJbgV zrRW{96unE9qW8!s+DU<;_bE`civmTvDNwYB0!1HCplB}ziaw-3(MJ?0+DCz+{S+wr zm;yxyC{XkX1&ThUK+!=86dj^K(PtDWI!uA0&nZy!1qF(ZP=t!M#A3G?koaTnqt;uc z=x(>$|7FZ~zMP_OV&1A2Qgn>vrRX?WioPXF(RXAi`kpLBKai#9N3s;1AWP9tWGOmH zM$yj{C^|)fqF*Rb^eY95expFqX$lnmPJyC7C{Xk#1&Yp4py)3O6#Y$sqJJn*6iL=@ zJBp$dC`zJ0QH%mb$rLE^C{UC_fg+y*MFB;q=<8VQO#>4D((T+Im7>?|y?ie<*>}F2 zqI}8Tu~t%)pXH^f09lF(lBK8+S&HIhDJo2sq9SA|DoU23Vq_^QPDW7)3KW&3Kv5|Q z6rD$bqS6#7I-deXWhhWomI6iPC{R?M0!0-lP*jluMU^N}bO8m5DpR1S3I&R)QlO|B z1&XRupy)yh6xE?c{V7m1fC5DWDNrT zW|5_6HW@{8C{Q$)0!8yEP&A(cMYmF*XaNO^Zlgfa?Gz}wg91ehDNuAL1&Z#XK+z%! z6x~gMqQw*_x`zTq_fnu}2?dIlQlMxV1&Z#YK+$rFP|?KX*kJ<_|J|Z@vlLz94nf|Z z>^omh(L>2zw4)TQWO*rCMV6w~WGQ->EJbU`QuGK}iXJ6P(OR+;Jw}$I$H^#qf&xWP zQlMxZ1&W@cK+$>%6g^FWqGu>j^ehF6o})m~1_~5CPl2KrC{Xkw1&UsxK+($-D0+ng zMH?wl^eP34UZX(KCJGd7ra;jaicrym$+5}?B>ubmc;gBwvj2~r?XV^L&X-g4MzVK# zXDQmj@>29BS&H5wOVQh8DSC%2MemZO=smI&?IcUl`(!EFMMlwX3KZ?3K+y*jDB4Sb zq7Nxh^brM$_EDf{KLv_Dra;jF3KV@pfuc_-P;`(2MTaO*^ce+;4pX4$a|#rFL4l$p z6e#+V0!3d@py+FgP|>#J*f0YUZ|Yvewo6g93=2n-edo(5`Zn3St*aD$$MRD2Jz0u= zAWPAYWGOm9mZG1?Qgo6mML(0J=oDFsej%giR|*vUMuDQ!6e#+g0!4pNpy*Eu6rG_! z(O(oO`kMkp|4^XFel7bxyMvRXD2h^`D2W0^F$xqVQ=rJBKv4<>ihK$b1r#Vsr9e>{ z1&Y!sLPf`tW6v0n_yBjf`nVK*?e_FDJm2|piVAw(2i>Kp5X(zZoGe9!$x>8=EJa1h zQdEpAMa9WdRDvu;CCO4$ij1Q3C{R?I0!8Ojpr{N5ipo-;s2l}~%2S}I0tJdHQlO|3 z1&S`9Kv8816jh->QB?{QRii*rbqW++NP(gn6ey}mfudRzD7uIOMYSnHMftthX#)~( z>^_)Qzzg^EPr3uynV#=_IYk$HUddikRG;Ogr~z4u8j_{x60#IEB1_SwWGQM)mZBzP zDQZfVqRYrAYDR&gED97gr$A8)3KX@ZKv63S6t$*6(d85$r9e>*1&Z2H zpr}0siaJoBs3Qf6I#HmgGX;veP@t$Q1&X>+pr|`VsHmlzEqU$J7bUg)%hEbqsI0cGEP@w1r3KZQ)fufNVC>lk9qR|v68bg7i zu@op8M}ea86ezlh0!0%jP&APuRMg9h%`_nK+U|4LS4dGC`%|CZ&7SXkIYm=F@8PSY zXd25)(R8vD-9nb48DuG%NtU8nWGR|WmZCXiDVj@`qIqN#&8I-otrRF)K!Kv$C{T1e z1&Z#VK+!@96x~UIqPr+iw1@&lcT=EfF$Ie5p+M2S6ewCkfuf}pC|X8=qWdUNw44G( z_fw$g0SXj7ND(TU?8V+TAn{W67xBC)Qj}K6!V1rKzMP`fp7-rFQuHv(OVJv#6g@(g zqDRS6w3aMIkCCP5ak3OWL6)K?$x^hAjH0I~P_&)`MNdDGNQ!pbQ52;>Q4$4;ViYJ!ra+NLfua-& z6!{b=3Mf#NN`ay@3KXSNpeTa^MfoUDl%FD0^qm)5Zb0H4oTBfg=oPnhT_DAGzMP`M zDc-Atq^JnXOHom>6cr;&QE{>ql^{z|NwO4`B1_SEWGO05mZI~?C@MpNqOueyDo25$ z@)RhlK!Ku)6ey}hfuaj2P*j-$MO7$JRFwin)hJL@odQJ{QlO{?1&V4?pr{rFiY}r+ zQEdtoWm2H14h4$pQiO^MrNq84An^(13{E^H+|wWHUeW5M_|BJ8)G)=14UwWtSYC=6 zk)`NTvJ^EYOHmWD6g4GF(Pd;QYDSi#EV2|eC!?qZ1&Ufypr{oEids{k=yD1awV^;! zHU)~>QlKb@0!8g8P}H6RMI9(m)R6*3ohVS$nF2*!C{Wau0!7^@P}H3QMLj4`)RO{5 zy(mIO^;2S14M=>adl73OMaSJC$SYEO=gTR&I>pPrPKvH!c`52cmZH97De6a-qW)wl z8bFq!fn+HfM3$m!$x<|!jG`eFC>lzEqU$J7bUg)%hEbqsI0cGEP@w1r3KZQ)fufNV zC>lk9qR|v68bg7iu@op8M}ea86ezlh0!0%jP&APOMK@ERXc7gACR2opu1txIFd*^g z3K*QLr05R!k+mr)zVqc2-IC(nF-(ePu)Gw_BumjOvJ}lGOVJ#%6wM_|(LAyg%_mFI ztz;=$Kt|DR6ezl#0!4RFplBfliteO9(OncMT10`OyD3n#m;y!jP@w2u3KT7&K+#eP z6fL7b(R~ysT26tY`zcWL00oL3q(IRM3KTs=fufZZp`vLivF8j(yh25TGhK=%xhJMo zDZcaN6g`sSeK?P_|BJ8^izu0Z?qJhWO*t2nJh)8 z$WrtRS&DuoOVMv+DLPG-qTk6<^aojr{v@O53P@t$H1&S(Bpy&b$6ji1`Q56alRi!{tH3}3}r$Et# z6ey}efufoeD5^z)qKha{RGR`tnG`6hLxG~Y6ey}kfuf5kP*k5HR8+)|y=y??H@HJY zMg4G3znyzUYheG6Q}g8%UFv(^kC&pxEH6b($WqjlEJc@*rKlNMin7R3)SN6uEyz;T zk}O57$S7(}fuhSPP}GJ3McEW6YDP>;7D=9)nm-w;xO{QqPdoF4uMMs>Xt9;-2 za*F!;UfqdO)Q{z*s6SbX29Tv_AX$nAk)`NbvJ?#_OVJRr6b&Uy(RE}LT~C3cVH7AD zPJyBk6ezlZ0!24cplBooibheOXfy?i#!#SWECq_jQJ`o%1&VH>K+yyW6iuW+(ajVn znnZ!3$rLD>LV=>G6eyZT5h}XIkM%Mj@fY3uXnmyU`*Ieh`@Zw#6wUIz36rE~Hp@%V z9I_P6B}>sfvJ}lHOVO=lDOy05qT9$)bURs!?jWORAq9%=q(ISK6ewCmfug%9P_&o= zMfXsk=w1pGEulcsQVJ9;qd?Jp6ewCwfuj2O;*;DVqM1^3sXKPP#`m2sr|2=?+cZUr9%p$edV(xPPm-l*9a)N= zB1_SFvJ^c{mZE3KQuHiYik>5*Xafa`o~J<33lu1Nkpe|8QK0B$3KYFUfufBRD0-Cw zMXynyXcGmBHdCNz3k8a{QlRK{3KVUlK+$#z6um)#q8$_{dXoZ0Z&9G=ZHiFQqkim5 z0}_ABeR_Yb6diKMi{9~l=gTR2-}k)fQnZWZrD!) z$WpYQEJYuaQFMR;MW0Zh=u-+59i%|fAqo_IMuDQk6e#+f0!3d?py&t%ioT>k(N`2G z`kDeoM=4PB4F!shQK0BJ1&Y329GS&DumOVMev6#Y(?qCdz|^e0)0&XA?(FR~QJD$-8oB& zO0m2Yoky0U(qt(*pDaaX$Wm06EJfwWQdFKSMHR?WRFRCLN)#x%fC5F8DNs~}0!39R zP*jZqMb#-#bRh+bYEYo4CIyOWQK0A|3KZ3*Kv5QSKRVhR-1r$A8y z3KTV@K+z=>p`zkJ?0Ewc?^ns-lnBB-{bCsw8U?=doFzN@IgX(C09T<8<{&X-d(An?wgFGT}cUWx{hrRZ9+6b&Xz(Gao}4JAv_bz~{J zo-9Sf$Wk<%jG_?~D7t|HMK@BQXe0%SMp2+>GzE&rP@rfm1&YQ|plCb=if*Dn(F6(< zO{754%@in_M1i8o6eyZPfugAtD4IrrqUjVUx`hHoGblnu{eoC?0}_9!l)>pQMaP_? znSt+oIYn~=Z@>a6n#b}|G@mR*x00o30a=P}BTLckWGT9XEJX{+QgkO-itZw#Xb}a9 z?xsM|VhR-9LxG}uDNwY80!2$HP_&E!MfXvlXgLLn?x#S}0~9EFkOD<3C{Xke1&UTu zplB5ZidIvg=wS*Jt)W2CBNQlllp<6#JBZCSAo07(7@Rp$)YAP)thIsfd^tr=2Hx7+ zrDz??OVLwgDOyjKqNmAH^bA>wo+V4sb7U#nK$fEC$x`$J8AUHrpy(wE6unG=qE{$T zw2=ZuuTr4sH3}4MqCnAR3KVUjK+#qT6unM?qHPo?+D?I@Hz-iFg91fwQlRK93KYFf zfueUPQ1mVZir%9L6+Irrb{dfQm4U%|LW=gfUn|-f_|BJ8v?uU>Tqs2!u)GxQB}>tV zWGVWHEJgdsQna5eMIV!;=m1%YJ|Rodr(_fzq(IRj3KV@tfuh3{DEgcNMPE>$=m-Uh zzNA3WR}?7vngT^fDNytc1&WSQpy)USioT^l(RUOm`kn$sKTx3PM+y|3pg_@26ev1L z5h~gh#ERT$iq^T$UGJ8n{q7@cKL@_^C{PrmKv6OUiaZJwrBI;Ar$A9afud9j6s1w1D4haD z85AhWM}eaJ6eub{fue#GC@MsOqBsSL3R9q{2nC9YQlO|91&WGOgo=I%V!aJWd{a4t z^Q#mMaBqi{NcEjBr>JzQck^N?I-ljGs0>+(%95q199fFWlclHvS&Ax>rKl2FiY_2a zQDriUs!*V)Dg}zFQJ|5egaSp4C{T1M1&SI|go;X~##R`Rcro|q_RmWV_w+{=vd|>e zcfOpWtWPUg2P82BWOo5^<6e#LSfue2{DC$muq8=0|>Pdm3UKA+0f&xXoDNuAJ1&Xes zK+)9{D7uCMMSUnx)RzK9{U}03m!-zOHX!jG?nSJb6!o_6dHqv;=gTR&Hr4Z&Nzq`I zm!ctLDH=+aqU*>~bUj&$hLNRcI9ZBDkfrDbvJ~A&M$t$L6pf-l(P#=3jiEr%SPB%4 zqd?Jk3KZQ$fuac%D4IxtqMIpDG>HO5lPOR%g#txWDNrKJMHbtmtU}~&}0f~EVPk)dU?QySYb5ech%PG1w)oZ_8iWacE6x~LaqT9(*bO%|A z7LujtPO=o;MV6vPWGT9vEJcgSD7uFNMfXymXbA<1mQtW-83l^&qd?Je3KZQ>fuaW} zQ1l=LidImd=phOet)xKFDhd>>ra;ld6ewClfuct!Q1mDTiq=w~=rIZuJx&oSnwJ_I zWkBMs+%FH!m!itQ6x=!?ot#bOHmS8ieh9bN+zSoqd-v#1&VwM z6a^G0N~J(i8U>2dDNvL_fuejAD9TTPq5>2sDoBB%LKG;9Q=q6Y1&WGLpr|MXii%O7 zs5k|RN>HGvBn65}QG|+4r^Z?ukodjsK;!RHl;Zvj&3S3Q^W_wkP4fmlEJfv5UW&?- zrKkc~iYk(&s1jLP&&6E)*#0N`azo6e#LWfubH1DC$XpqFxjz zx`F~ly(v(1B?XGEqCnBr6ezle0!4i&P}G+KMg1sH)Sm)H11L~5kRnvnJT11%fW(Wq z-Le)^RM&knWKf##d^tr!)4ZS7O3`&JFGbgrrDzygiiVS=Xare`ZXiq1jbterNtU8f zWGNa=M$s4w6pf`o(Kreeji*4-O%y1aK!Ku(6ezlx0!5Q3P&AnWMN=qHG?fBH(5G8F$xqtPJyB)C{Xky1&Y>Dgo+lV#jY|S@tFJE^=(pgf!j!WD$RGkoT6vbyvggN z=sA{`q77szdY&vrFOa3^MY0sVM3$nL$x`$RS&BB2rRY^Mie95Y(IyHMZKgoc777$? zr9jc^6e!w8fuijcD0+heMLQ@^^d<$0-l9O!+Y~5zhXO_KQlRKP3KZ?6K+*dYDB4AV zqTLiI+Czb&4=6%KPp8FJ8j$#dZs-0PDZ1Gy+MDJ(Ury2fH1GBGQuHy)OVI(c6n#RL zqEE?EbdW4XhsaX&8Ci-Blcnf$vJ`zmM$r)p6n#m7qOT}W^fd*Fj#8lL8wwO1qd?Jd z3KV@yfuipyQ1m?oihiI#(T@};IzfS=pD0jtk^)6PQ=sS+1&V&5K+&%hDEf^8MW-o3 zMIWWbzA+&2?e5n;_DNBB-@@-{zVqc2{gvjWJ}X6kv%D1jLzbdQy7t_qC`y*1B(fC6 z$WoL{mLiWVMJZ${^2sO)C{UD2fub}D6s1$3D1!n;`6y77p8`b%C{R?80!4)=P!y*? zQDF)c6`?>;Q3@0lqd-w{3KW%~Kv78w6qTYt(RmaoDouf+^C?0_f2PH18IXA2iU#M5 z6s>j#kIJO`&X-eEA>He^L5eD}ycAU;OVI^nDXL7CqAFx5s!EokYGf&@PL`qz$x>8< zjG~$pD5^z)qKha{RGR`tnG`6hLxG~Y6ey}kfuf5kP*k4+MGYuW)Q|#2mr$Un5e14a zr9e?*3KTV=Kv7c)6kSGvqGl8*%A!C~bBa(=x%Ai=0}|g+&ft_!5BKz|J5nvuedo(5 zx;))m{DKsUims(V(O`;DQLFUW%LXL=jQfymYbmPfej#K?y6=2BMZ?m)PhOIu;Vdsj zBgj&816hi0BumjqvJ{OXOVMbu6pbNE(O9w+jU%IIJOzqwqCn9E3KUJGK+(+^pE=u>+7XxkA2U(E!}s%oT59^z49BS=q{F*qD5pWx|=LTi^)=S z4_S)tB}>r~vJ@>POVKj26x~Ng(Q*nD-A{p{2PjbVAO(t6P@w1`3KXrRK+!4+6s@K} z(ZdudT0?=NM<`JAC297S&CjFOVP_@DSCx0MH|Ud^eS13 zUL#A=@ZVD9bp+M0G6e!wDfuav7Q1lT+sOY)$*a8C*PjN>bH%QSb z_r$a>-FLp6qEFJjCpSycrz|f;2gy=&h%7~)k)`M`S&BXVR3KZq1 zKv4k-6cwaEQ6UNx#VJr!m;yybC{R?C0!76rP*j`(MI|UuRFVQkr6^Ez9tDa@Q=sU4 z3KW&0Kv7u=6qTb075$waEAhH1D(#LJ{Ub#U9I5gdzVqc2U6A2jvR#TQv%C~lAxlwJ zvJ_P#OHp;Q6kSM`q8el=s!5ijT4X7@h>W7z6e!B1Kv5kE6xF3bQ9TM2T}*+Z`V=T? zK!Ku$6ezlc0!57|P;@B;iW*a(s0js%no^+XG71zmqd-v>1&W$epr{1}ids^js1-%1 zsA5L!8UqqOp~`o)jqRMS-F#C{Wa!0!3F+py(LV=>G6eyZTfuiXYD7u9LMKdT+G?M~FvnWtBn*v31 zC{Q$)0!8yEP&A(cMYmF*XaNO^Zlgfa?Gz}wgCbNkJR^48fW)tNpSvC*MGrbf3p0G@ z%PG1$!%KfxiWalH6x~CXqI=0ww1g~0OUY8Sj4Va>k)>!kS&Hr_OVI;l6g^0Rq7@V< zdWZr=D=AR4iULKeDNyt<1&Y>Cpy&|_6g^6TqO}w#dW-@^k5i!N2?`WFNr9qu6exO% z0!8a7Q1mnfik_iB(X$jNdX6GgbXP{KwgHLvb)UOlBt`SxTeBN7eCNw4dMU%}yi6m2F;(H624Z6!<5>tqydqd?Ji3KYFTfubE0D0-6u zMQ>4{=xquVy+eVbcPUWx9tDbaQlRL43KZ?4K+$dr6z!ov(FYVL+Dn0=4=GUe5e16& zQJ`o)1&ThV2o=4M5gTVf;)UFs9xqDKyfh03GJNODDLRzl-MdSQK4W<)I!ukfkUe8AbUiP*i{dMFlBPREPpaaS9X_ra(~<3KSKkKv6LY6cwjH zQ3(nZm83vXDGC&wM}eZ!6ev2M0!3vgP*j!zMdc_^RGtDw6(~?tks?$S%@<4hz!YV> zk6I_?3-{6Ly8jb;rF_2gK)u%vF0}2#1q(IRn6ewy$fuc((P}GO_{J&SWX-LYAVgWGU)KmZI)tDe6I%qMl?F^`b!0 z6%;7yO@X2-DNuA31&XewK+!c6DC$FjqP`R;>PLa1{uC%0K!Kux6et=*fud_EP&AkV zMMEf1G?W5G*HNJ8dI}T`qd?JcicnEbzS!*sB)-SJ1JX{4es=GpjmYOaUry1eeBM(Z zOVMbSm!dIbDH=^)NST7C;J=JTB|r)Xn7@6tn3^eW3s(Q9NW+C-M3&15OsLYAVf zWGQ-`EJfSMQnZ~cMQ@N%w1WagZ&IM>EeaI9O@X3!C{Xk+1&ZFIK+#SL6unP@qFody z+D(C?JrpSVfC5E(DNytw1&ThRK+!%56z!)#(Z>`hIzWMKAca6_3oVl1(9#kjkP;Gzv{X|HL0YUx-QC^YUEjL9y>)kY z_m=v3o|(_R+0gg>{r~4W|8t$Q*A<@q+&kZy*_nIfJF~kKcJ<%8zEc)m;kQHH>XLH5 z+@kloga^DUi{7WbEc$>fi#{aFqL0Y3=wq@h`h+ZtJ|)Yd&&aaqbFwV@f{aC90S z02X}>z@l#eSoAFbi@pP3(f0r>`T>ANKLW7mCjb`x48Wpa09dpJfJMIou;@1c7X1#u zqCWsw^d|s|{sLgp-vBHM^3*ZMq68qe=$$UfOHGi%`}}&*yRvAs-ww&jOSxZeQBGd? z==-uLMSEG)fh>zUl4VgRvMkCa%c9O?S=5Cri}J{_s4H0(<&&|f0Dwh>04(YTz@qK| zEb0NkqMiUODgt0pF#wBt0kEhy0E_wnu&6Hpi`D^PQ9l3{^#@>42>^=*0I+Bv0E^ZI zV9_7|7Oe-sqV)l>McH}DFHMlbMSemZ=EXhznf_Cu8|04Bv}@XBFm!DWLY$Zj74JsSTqiRMdJZjGy#A`69HJXF#wA; z0btQ202XZuz@p6nSTq@cMdbi2ngYP03IG;W0-N>?Ncd{(ngDi{oB+H_`$g*f}vMkz% zEQ|If%cA|rShPO?iw*!_(SZOgItYM82LrI^5C9e(3c#Yn09bT50E>&(Y|+ZR`7W zq7GYL%KdVS&ddwn`9c<*MSEFvHdz*(LzYG7l4a3(WLb1RSr%PDmPHqmWzj`sS#&WO zi!K3R(WL+^x(t9tmjkfq3IG;e3BaPO09bT20E?~xV9~VzEV>SWMb`tc=mr25{R@Ca zHv+KeCIA-Q48WpW09bS@0E=z|VA1UWEV=^_TXcF}GW$!jsE1#5JVO>$W?8s1FXeu@ zMfc`~>wPVY?xVddx}PkI9w5u22g$PNA+jubm@JDPAj79$jV9^r* zEP4`vMNa{+=xG2JJp;g^X8~CB8~}@+2Vl_)04#bDfJH9>u;^s~7QF(%qE`V}^cnz* zUI$>&8vrbN6M#i;0kG(802aLih%LH1FS)r1QaG^0#JNWnZJo66ZeGg$a*IC93wQoj z7JWo}S@bbk7JWjNMW2#o(Pv~?^f_4;eLQ>7X1joqMra*^fLg9egR<78UPmk3c#Y@09f=p0E_+rV9}odEcy$8MSlaZDCnwg zI~FAXSd<08q9g!|vH`J0@8>0tH$e(d@y}gew~B;d@!siT1K6 zmn@4qlVwpCvMkCY%c8DiS(HzfMFnJ8R7jRZ-N;zf9e_nW09e!$fJH?BEGh0E;#NV9{Uz z77YQ!7Nxo-Up7Gs_wx&l9lFLn{RjOLd%vR1LtQsQ@gR2Ed{k02XZyz@q5@EUE=y(F_0<)d6CQhIUQ% z{mCr))^B!!_l>6ltHFgar{UVE+XfKPJ$+Bn*vMkz?EQ@B7Wzkk-S+q4- z7Hvb8Mca~P(RO4k+8%&KEdVUq0f0qw09dpm0E^}VuxK6ti&_C#G#`LP3jkQO5P(IC z09dpW0E>18V9{a#7A*l_(NX{wEdyZDasU?X0>Gjb04!Pwh%K7cHMye+Qn;soFs(rr zb?|Qgs;(*b%PrcyYk1JFvS<(5%c4EWvS=@|EZUnai}oSQqJ7D-Xg{(n+Mg_o4j{{- z1Ibu)5CDq~24K-404zEbfJKJ^u;_3A799b=q9XxVbQA!Kjs{@SF#s$&7Jx;^0kG(J z02ZA9z@ifYSacEqi%te$(J25dIu(FLrvb3&bUd z`{fp$(=~kjcUg2U?Pbw?mMK=Jj=wARVx)FdyHvzEdW&jr50>GkM z0a$b!0E=!1V9^}_EV>hbMRx(P=x#u4(OF%SUz;F>BQ1t!%c8sdBFj*EoLY763l4a3jWLfk$Sr+}9EQ_8X%c3XASo9PCi=GBx(K7%n zdKQ31&jGOLc>or@0KlRb0a)}B0E=D*V9_f8EP54yMXv#{=yd=Vy#c_YHvw4m766Oh z24K-U04#bJfJN^Cu;_h2Y|(vPlcPo}7X1mpqQ3xG^fv&Df_!z`u_yt+qAUOwB>`BJ z4ZxxhfJHd~EJ^`li$3a_+|vXpeAn-zeJqOx^s>+)KjnV8MV<4*v$AAS7uw6BJhCk6 zN|r_WWLZ=|mPLhRS=5azi@K9#Q4g{#>Pg0;A^;W@1F)zU0E>D9u&56Ji~0hvXdM6+ z^#fp0e*hMh0I+BP0E-3!uxMQX77YSm(Ru(ZS|5N#8vw9qFaV2&0I+C702XZoz@njm z*rHDP$@@%@!ZZC;C^tXu>3`rB4a-ltUv5!Ze)wLtEE-9BSu~0)i$;@W(HOEU8cUW% zGjQ02WmOu&4@v zMb!W-nhL<8X#gy$0btSQ04$mgz@l0J7R>-)Q5^t_>H%0Z6M#jt0I@|Q@{>8CSv1%0 zqm{~{$$mGsAwT7QxkX##ha041(U!EAMYGAWXe+WT+L|njwjs-+ZOO7|JF+a=o-B)6 z$g*e$G8WANV9|~MESd|zqIm!;Y6W1?d;k_L0ASHV02VC*V9`zhEZP}>MT-Ggv;=@f zO95E441h(;0a&yP0E<=tuxKR!i&g=!Xf*(fb_K*1HRUI3O_0J{{61Qodt+3+9N-Cq6t#?ONoiIrz|?pFCLwppK`z4qVw~^ z8*^pR1+RvFIuQ7F`X%qH6$H zbS(gjt^;7v^#Clo0f0sS0$|aN04%x*fJHY0u;>;57TpTKqT2vibUOfx?f_uXod7Jl z3xGv;1F+~G02bW~z@qyAu|?=bpRH<0l=a+0a)}F0E^xRV9`4OEP5A!MehNy=zRbd zeE`6s4*^*85g@kc!Te;uJhSK-zeMzqEIP{X#(tcia=+Z7&-260@@3H%w3kI+l4a3X zWLfkzSr&ammPOx^WzlzJS@be02ciY zz@k3@So9|Vi~a&&(cb_p3JTP1$D#xPi?RS%lmuW=HUNu402bu{uqXwIlH1 zPJq~=PxF)WOpwAw{^|YCWYGlwK3Z-;%KdVSx)y|o6w0D}+RLH>vMeej%c5>%S=5~@ zi+Ye{QBSfgDk96GVzMmiMaH7u04(YQz@okYELsPEMg0I+)E|IFB>*fM0KlSw04!P; zfJK7nJuxK~{i$(xqi@FpfuQWjl zFAGhayn?u=U*=aGOAAu&ms>QtAbg^`EE+?5Su~a`i^h><(Ri{fnn0FC6Unk@W3nvT zge;3Dk!8`QWGvbYfJKu5SX2(cqA36@ssLb7B>;=609aHFz@n)DESd(uq8b1eZ4SVq z=>ROM1z^z(02b8&u&5q@MKb|dGz)-54FD`^1Yl7UAhu{^LGoJ@q;Q;f?nlX@gdg6T z3sUZvTeMX{SWqO3wx+!-+J-EPwk6A=?Z~odd$KHQAPSTqlS zMXdlVnh(ID1pq8s2*9F604&-GfJHk4uxK#=iF_Oj>_ zvMjokEQ>B9%c9H4vgiu3EV_~`i>@NeqN~ZW=o&H>T?@dX>i}4EJphYt0ASI-09bS* z0E=z{VA0J0EV>1NMYjU5=r#Zr-44K_I{;X8Cjg7?0$|bI04%x(fJOHLu;@Mj7TpiP zq6Yw2^dKO%=z@ae113meNoN!1LRqxfFJwPdkaEA=qQ?rt57v=IkJDZj{hKU{o*>Jj zC&{wtDY7hjnke02ciYz@k3@So9|Vi~a&&(cb_p3JTS2 z$D#xPi?RS%lmuW=HUNu402bu{uqXwIlH1P5>;*1z=HU02Xxt#1?%~kgPL7 z3Lh&lalVvA_xkOSyuy_G);7OexoqJ97@>JPx85&#wr0ASHT02Zwaz@k9_ELsnMMe75wXafKi4F+J* z5C9f!2*9F^09Z5>fJMUqSTr1fMI!)MR0_bNG5{8h1jH8Q7bZ_OK?<9_TUJmQ_w>&- zdBRbJDfi1Q8dn(JJV+Ler@btiK$b-l$+Bo;vMkz!EQ=f02Un&z@ifX zSac!)i%tSy(a8WTIt745rvk9(GyoQz4#1)_09bS;0E^B7VA0tCEIJ2(Mdt#r=sW-x zoe#jG3jnc2`xPeVn;?Z3TMYM?MZ;XF3ky^3SI{%a3fJv;!_Y)fG|A4ogQ6DuIoj-^ z1MDtIhoXz@K-jtHVLPeHFZ#rGXWff7>KO#ZMZ4G-`WD@4AD}EL`qR#`1{GD<|4=iy z=!gM9Ftq3yyWLV+)MNc17+ti@;2;=Zbisx}uu0J;LxW&)(XbIgP+7FHEC{9*-99P^ zYK#6J69hAhs>TOFQ_)cqgJ5>ibDIRgwnaso1;GwQ+m#2wyrPRLf?#3MXH`M4xM;+* zAXr|sdh;MyRdi=<5bR!*s1Jg@i>A&Bg8hq*X$*pci(Y6Bg2Rh?%?^U2i(0l0g5!%W z*)|AHF8X5oAUM6KY)%lIU9{WWAUMD1?$#i;5L{pM($XNf zsi@B`L2z5qoRvXvSJ7pwgW$fRuXYQ9hl)n+83d0N?XhJi`F?Z2tF*Ddvp+dT6D#+LGWeKH^&FTw?$)43W6Vt_Btg9 z))d`;S`hqEoI2B%f1-HC*|q`_#V4I>Yamhl+WEE$62<*5vUQLsZoR}-LZbMp%WN$q ziod(URzsqA+|{-o62<<%*$+w-`+rA1I8p5XpY+f~vHyp_rHNwyA6-W$iv7Rj9G@um z|5I_3M6v&;c#{*w{=b@4CW`&PrJ9x~_WxI?Hc{;VG0e0pC?|JDE8l%U7RTP9|&EZDE41?T$L#HpXl2?QS865ws)e~ ze1OXMjH@iv1A2CQ34}bpHz56E`!p_fM z`^TXEiN>(t%r6exF6j4&nl#YlgezVg5H&gCnXA9rCu(wf#S<&7Nlw8TA07SPUO_*< zK;FkDGe2&V)!~$&pRK}Ru(2~4&x^%ZZDHdHJD<7xAwHU%f@^-b`TKpN@x1)&&wuR^ zlx%2i#`x@3s`1M-{`!^geZIra?{7L_=cw_T7f-u;PoMA3a|fNdVbE^}&BNyz^RPmr z={G`e|C7Z-`}t@JKD^+}hG;aGpYy`y@jP64#W(lv9hB^9ZKn7<9B5B`*=-j$&M7$i z>`zYJFIp0JzjWFs@msj;`ZKS##b}G->=$3WWAC8fcv~0V>I7On^y{;a+XQUZ`&Rwt z(+mr4zv$jMQJV`+x#IZUgMN2d8((}E$88d&LBH39ZcU?-*ONg|?=$wXJ@HBW5Wg07 zF5K$ASqQUA+H+ADk8 zw(Ng7zhvbMywr~6{+IKqh3k3*f&b-nu)$6@>VG+(*eloD@cx&Roy-Xm1&Q_Yy5%PG z`s6hi6(sVDf*@;9kej=yp&&^143c>hb2rYNkXzHuj#GNY_Fdtaz)4PaBAK^oZmzu? z50)^P8f>ll+T=P!Pi*(sF?wQqicT6~7>_VFk*MkBO*#*-(T%VsUAo%Deav~?61ll; z+yD%9!6mMNO@nMrqNf*Rv9}Yne;jBr5zO>5-}KB5en`wb&z~)}KYPK8AG_igGTJ6=7nJeX)Sf4TSzh|u z{vi=Gd&$x$XPxKIe6;q0mle^|SzeBgsTU?R>%5FHr=L!?XNjP}OFX98ZDVTiF-6DN zV79&fkB1!&t!<+hZKt-fr3 zw(R^p``dDSy;Yw-e@+vh8(T>Buow04VKN_?xvQNxB!d@xxh8(k>k=gFVZ+*AV)*b8 zE9Q)tzjFDAl`H0sSkba_Zfnc(70Xt&&Rx|yZ^Yacdn{kI%)#8&d8=2nuFQDNhqs|8 zj99*6(UL{07VX*^j99pAN$ZF?i(7XeF?{i|xpNkeSh;Y{iq;V;T9>x2oU?L7>&TXs zt5(ljv~0wxWy==NT{vga(v>3?%$?gZXT_2cWu+~nT1J+RENdw%bvVr6u%*kEwhn8Z zv*V&+Wu?PM4fB_W+so}<8nI~U+{LTswT@UaXYRs9OaDKgjg@<>%v=%+7LF)iF>m#v zrOPUot!N#VUKYErS`jUhc!|thv1}(><|{`uE}yev=jzoESR}?^~#op^070< zu$t`6{=Yc(|0fdcI%id@uM68qV~r+^Su}jETh=nKb^e^yi&wR*+GBa^%Ha!LUNd3d zqNS@WnDgde%iLv4mMmM^GH3ZBW9D^ZMOBL}mAMrWH)ew4=OUk0i~{@0LKtlf$x(?g z?DpRtVIn8FAQARR_8J~0k_$@wS&2Uz9(HK|tZ?M;Fw7Yq7UtOaazr)an>=un{lD*<1m=yN5+AZ@XpG-9F zaDdlnoa_D%lUUb=DqJ`0wox?t!kivMZ4L*8g?&Be^au;riJo*13x{e5ANz=SGTp4i zZz!Ih5n(?YU5ApeV@|TmCSgwt9oG$eu48#bPWQ0q(CA6GuxEdNG9oOpB@#ckr#7rD zq=8mDmxO&v!_L#fE;-5G!@EUqa>&52cRvGKX5HdtHbl!Tio@;YkzpSjr@eMN2Nb;%hR4))izaOKuuE!-%USnH9ILw!uC0pXC+u(#_uU@blWmwLONeQdfm zih=*x@c$d5=;K=yZxYoMa{f4uHXF)O*7UQc!``Nt5^h=+$|(FBvb4iDGy zXYum4Imk(NF0swa*N`vkczb0hu)fiJ-(45@`b|E*@8GkNEJ zHVt1;gUzge?rYcbx%&E*<4qn;i@a9wd~k7V0lAj zOI>}F4cu7O&{S2Ker5BSHqz$0#^#wb>-~k6nKiSkYFn!78)lR@#Z$CVwI6&+ZGFY` zmdf&`@|L>h8B?kn{C(6n#6yo7pE=>W`j*D#DUB5kH9lB%eREx9G}yTD)1o?|-E1~g zHO{QJIgH0N+J<3S_`Fv&ls9I~Im>NEGZEtI|#W@y=>y_|lAq@g+H> zG;>C4>ROta@C40VS#`TXDjK$$*;H?Dxwf`tW_?XvQK}F$}Ls~_0^3n<(2Vh#zaH=oK%y)3$1{bv?t@az%Ml zO?_RwoF=3jmQ`f5tZA6lGQ}LLtZ9rV#e@yTt+vMc#%K;I&Fb_FjESbtyU=jeWww2^G}c#Fx3n9$Y(l%CE6VFyni|UM8fVlr zMPqKLDzDrsdNWhn3ER+EZX=3TwJl(Y%{1#9D_RTQ`;nT}eA@v><*l8o&s{f1>v zd2KZ1min1hb?Mhoc}hdg)M-t1wnSSRtD2g8TV~SL6}8i&*&Q`H-g3r7Q;a5F3W_$S z2${lKSL5|!nJvEb*lKDTs>@rdDk@sarqpONuV}X^M!S~En)0bF_03H)o10p;sIP6Z z?I%47wg%s+`0mGdT^UgR@to8H#gW5 z+s3MEYbx6I`jMr+GfOYJvXSWx+&1-i1GMdL-s&Yw_DGLA+8nCtYuax%OxbqBGwK_B zb@+ZV9>vIL16jOm>4Fm5X+>-_qc5{3w6$f}Sl@P-^4)&=HSKpBs%opEeX}pDs`ehm zYuewlt<0M0c%j5|Fg9Z<(SFBQj_={3qnYNioi}XsE#(yz%?;%h+J&X(XPO=7wk)?d z+Eg>6%GOdej`8WWT#+%snYNA^8!F7B@`|RKE#hO&*o;FR8>Jnbr`AOW=17H6Hi$nd zZ?|*L+%vT8vC68_YtEmhXHz2By0>k-S%*8D&9(t-qEi~m?T{{oe2TVqGB+VxRP1hR z>l?KZk55m~Rzti5r|_gITHz}fEm+z*uf#6>tVmDJeXg&z(U~M|yXdxEKt)A;%QV|H zr5mtpX4F^4b8koe^otc$wYAN)C;`&(+EO{IsiksSd<1WQxF4G_y!Kc#Y@gKJ5FMDJy<)X3n#O4v`(rGwE#Jyd9(BaE zXSTDNzk2E1($S-W%rsha+fLH7?Q1P_)_=z7Z>?<&Z3Zy)spT_fl($XYoV2qm7Kd%K z(L~#}>$0-QkEwOdB^47Ul=wy2;bkR$S+;ci$k8Q(SF|o}owKraNXf7zbC<84Gsn7eS2 zUF6+${IDg%m)K?EjpnUfzR~>UCBqh!467emGR!U>PMT{oFl_#k)|D&gENC6JxOM4* zRSPGT8j82FVZM{Gsy4{)Y3>(vw`q`OQj~)My_7$~uJg_6I@2`BK zcFO5Krnif-(vf->>7B8yj`V2SmYJWwwP?Y`E$pZnJ+YM?1KX2j?7*V6-qufB>-1au z!uE%b(Ke>m7QcMmx?)8rrG3Tr(botW7M9*@o5TE?=; zXyE6Tw!4bNhz4!z0;c<}V>Onz*Tz)i9eLG^nbsAHS7>?b%CeE;E9Ne#S{mJJs#&^d zRpaWlE*)eZRQz3K_A{q#X;&vIrrUlse!uNDD>e^5mr1V^U}h)!f9S4N*HqWH?@P8B zR#{#V-KJ=FEK2W^|GE8G*V-28wAMNET358xwk{2J_AMzrXYt}`t}EZdHWcqQr(elf z`sK~mC$}@V%s#lEZLy4F(WY8|CO-8^zYy8&r?>TWz9)%}=VkxntJ==2gD2D4`gQHQ zYc6YgyI@8dXV$c++wH4{Zen?QY<9?C#D1ovY1m1yo|Rc2Aw7Q?OJHV0{j?hEINDmN zvy*4L5WyrX+AcKJG}YKy?AGQ*ON-rmYr8B`W~bpcfvD$^?tU-=-|c1E2FID|@=Cjg zvsULg^1sd+ie}T#L6n7Ma4Y$ysdSVFK_hg zY3WNbwy~v0n(oMzPl>LqrC-QckPTH$|M7%7+Hun3_H`F`)}jr}&UEZOFi+Oqv_4%; zMNM>Unptj#rf4WTz{F2%Q*AeRe6g`&nstM#YNJ7{7n~kldef=ivZdLscG<$z2sJ*t z*2NOEJ&c}uM^1CuHYV%aH~J2=%}XETKc3yPa@$?MYj>iZK5?h38uzSN3RENpo%6iH~nhoJ(b%GN&&bjpV|S_b-_yBlB~gV5ex;>hIaRcMOu*7qJVnH5Imt zvZF^+v>MVwHCiXyE;{JK0;?tC(+&Tp?&(*y?znnEw2Hi|$V~c{UOpvOH@;}iE4;&M z>j7G4xuv?cys@nvuQt#04acuSa6Nvlj#_%%R8&{At(P*tEY6g4ZAHgwTZ(1zHGN;8 znU}_+p5$7)rM9!#%BufzKIZkU-bTEG>~6^Wv-(Gx(Q(NR@k=opKpl7 z*O%LlcK_Iwm3a>(8n<7oW!#ywTwPOZXNQ@WBihb@8XGHgXQ#I5&Sr+#l zqB1f*3b&gjW*~hiNH4IAoul_l8IVcDwx0={BRIWtV{H2-a*7EpR(8_@`XF9ozfau}>Wf-O-`1Hm+Sm zTG*Med0uHJJ{f03yqLc4#F07f`9w>}ue(NlxmW|g%FFx8)S%ss8olA>y6JWGTgJrd%P zm1SN+)mZ&D%x?U)qs3;6G+KV`yAW-ouv@2`k}=P8;u@P9?QWR*)Bm^->eoQm zy8V%PX{NN@g_^eRrQLbg%`~4q@BO4ZWlZ0X_0d7>KXriJ9hZ+zosXqj@3G9TrKOiD z%Obw2n(;w`xF-@VoXiu@sLQye-5mDYPzZn6b8Vvv%DbAH8h|&GxpKHy=&hU5TEt(~U2bwzSZvX2co$@M#UxZDqxqVvVi% z+3B^jWw~|R*_E!<(l0Cd0W@AdZP!};s%3gmZtg@K#HkJ59baqlw(F9*PtkVZoh3%X ztW}g(*pjYpiB16Gy^Y<62z);HR0JIKTJV$$vK4{8KcD=H?I4E8$)2L?1=z$Vz@wW8e6oAUf4`*=bheMI|7{QZ;=1p9SXC%Cwe4`lEsN$iQb7miN1+`SpyUHJ*wo` z?K4c$KmDBXNZKc#?VB?hkL~gZ6@Q9 zOn-AQhRMLb7?kly2JOG+kqqqng&B`z&^06Z`|-JJdn5z<7D>h<8Q3q&XFQUDeWBa3 zFEd|fh4y|%X1s3SeGDeAl^fT}bJohs*2?>=l@D4gw|x!6z5!&frN35T&pq=g^Z0_s zpjE-3dH;*6)$Naf|KYZ5<^W|GhsaX9|IzkZ>FCixd>5dNMVEWh7k}E{6ZAVF_Bhf0 zI@x!%9#GA!fDO|ROkeMMylTRlSW|ryZ z+jW*LcsI$bjWVh>OF@=x3KxS#_@JPO7`8?x%XN>hY=< zsNSf0yXw8F534?*`kd-3s&A=&plV-Qj^_6p)t^-DOUV)U@8bCT@n6mNYF|2zYByE? zbu{PwRsDOqo;Omp?;l2aoa!Xi3RV9OuMc0Z+N`>b>KxSts!LQ?s_vn>pXwp1N2#8m zdYbAvsu!tVp?aO_&8l~*-mm(o>eH$(slKWDf$Ha~->I%qwF5)+K6A|1XgR8OSM8%Z zP<4oEsp>e@O;xK@YgHRnw^p5_x=?kQ>aME$s2;3(lKBekktn>H#hN|zkJb$M8t?DnT zf2oGHpYq{4t9DcEtvWz;u<8iav8t0)D^;hfHmGi;>ibEb&H~k?s;gD^Ry|1dNYxWm zPggxp^-|SqRBuwfQ}qGW$5s8@!KeR<>f5RxseY;YgX(Xp2|Ip!yAG;dReP$gqdG`+ znCe*7%~YqU&Qjf4b*}1S)zzx|svf3#yy_XM7ph*RdXwtis*k8Xqx!1qd#azS{-FAY zYG?;6f4_OEMXDvLLsUnqZme3VIzx2})fUx-s=KJ}sd|v=(Wh-F(t3IIm zgzAf`Z>fH)`i<%u)r9>vgulN|s@+vbsZO<1MSs0fb&(yrJ+D?h%1#wMpQd_^9kV^( zuKJ7};61;g`kkFBdj3;&ter!6u29|E&RIMkq56QGdw70EwS%2gc8$h8^-x|)$fPK`ES+nb|T`#SE=q>7U!c>9~u?s z=Ttk{35yS3q&m|&FrK$lJ#}K7FH(JTlQ@5-I&iZ%k5FA$9_Q7n*H*;&PSqc);+&|C z>qP5}`Sk2VOi|r`^SBkRe#<-&dHXzZZapXHL3^Bjq`D;kG016CDpuzaqgqqv{RhtsGhkv z&X=jayEM*Usjk0EoJXlHUKwZmI&bv8{_g&wh3fl<#rYf6!AHheJW9`3=?XH^zB@>ee^Md4cNrx5oJz z)sO8&-~IhTb?9Ajo}jwoo;dHPdfR<*epvOd2jZOjU|cI7j_WMdBOi_PX{ygY9_P1I zdp;TGbyc^0I?jt!FMKx6*QtK`e4Kw$9sW|BH&$KsN}LZ+z2mhwKdKtM8Rssl)o;hS zQT6C|<9vqd^Y6#`9o6EG;=G>f_MgOgXVr^8i}MYtpMMeOUsOxKj`JkdUB8XC^ulkPamtO7t_8%VC zM%4wXXQ^JS`iklos{QRJj=cR~)$LVJRJ}y?Hr4x8e^l*YKOE%kC#qJc?xuQ`>f5Sa z?E-->=WeQfRZCQds18#dt2$A&LUpR@Ow}gU?NsNe?xea@wL@Uroz1T)5!G(0MXCc- z*Hay;TBEpsxPX(s``!U530YZ+HNOmmy?KVC)EPg9;&vvMZ=k9Q5~Z?L3NgD zv+8!L(RCbKJ`0r>tFBVrT{Xw&qf>mX)0d||yjr&|s_$pTwY%p6+djpE;Vbu8vTDwb zR#&Zv>q4H{r~Fq1!~J9R!SEedt_+6T7XgMl93EfF{BNK0jfR`&pMtU*O7oZ5D5B?c zcHD7A>#p%wVq!lhlNsl%@UOmTI`I(yB#ZsWU^GUX(O|g$#7L`s+bmo z%osjr)v6VXc3i#6M*F}0=wn0LVohIVAH7yfTa?jbfc@*kCF2;ZJ)FPhj}7e4x0nCb zaK3GAS-{PA_^58swL+TUdR^T#Ta;x?<+#fsLq59iaHZGX&zJq>m@A9l0tmj}<9 z3}lXP=o0(ELvzH(=Uy?sdG?$(_B8lrY$Et31Mqa$wT63pe8PU{(Obk1p02Q%Io}l}O z&WYd}f1(HDGbP&%_omICopz=l443|;qSeEfjVLK8DH~_EWJ*VlA34FEmzI`g{5y8+ z=#rB0W5$gxwc$!icIdQURc&?rLt61@6LyD!@jA(#9;Gne)&~c@Y)`uU=84m@tMjUR zR8Odxu=&JkfB*8=-!}}X|FOJc{N@j=$u1aI^T3*m^BZ?~eob~+u+i_Yue&gN*aK^V zvbhWW-;1JuKZyPgdE>%utkv^2 z_3TO2Yt}3EXE|RS67FpC7?fQV{rklZ{yy&hbot~C(>re7v8I#1uX}$^4LRVeLk_&R z?<<4%+waUf)&%)IC*P8KH~4&?eNOE4%fCy4lV*W3RFk<7@?Y-os4y zi}0C`tVGU*wqa%^I^1KMOIB9+e9BAeT7$`+wxF|S6wj~*S=r&2_Db?eAF96B4iQR? z_tYVbuKaaK`GxK5?9e~Vot2$>&IU;~+W^U--OBy>g*NGAX?Ne%g~xgOM9$GR%A9Nu zsqF0a!)t7a4pT~l><#q4X7smM7Gw`r>}PRgkUd0k9gCxa>-MlvCL+xOu2_=o3D||-96ikjZ*IB z+2(Ata-nCNwK2*Co^9U7D(8E)nH#6v)w9jrc;!6LHhUA4yLh(wo2cB`@<^M%jg@mf z+x%^!+{v@e-z4RZo^Ad%Rqo)~=5I6QlxLg2$;vsNZT`xYL(evUQGKOrUj3L`9W5{;O7_z-GhO{VS$PUUFGDjIhc2vfYxyl$aPZ>j6l`&+# zGKMTr#*l@|7_vwiLv~Weke!udLu!)W+4}FawVe@VZyp;Oh8&`dA%`ks$YIJDa=0>v9HERMM=E2;QOX!{ zv@(Vqql_WPDr3lT${2FIa%{-br2oEmr|s;plf5i9#BbwfpOA8M+>lekZgwn;3^`Rz zWyooYGURkc8FGfA3^`L#hMc7+L(W!|A?GN{kaHDf$a#twa=tQ#T%e307b;`OMamd* zu`-5SqKqMzDr3lH${2FFGKO5Cj3HMlW5`v?7;?2ThFqhJA=fHn$aTsXa=kK!+@Oph z|5C<~8BC`0a3lp*&k%8&;XWyphyGUOpe40%`?LmpAakVlm<lX4-{p{hl(=fBSjhVv7!w5L{Wx(swhJ~Q^b(Zl`-TCWeoXJ8AHBO#*nX-G2|O% z4Ea_WL%vhSknfc-7iA1tql_WHDr3lR${6yyGKT!2j3Iw2 zW5{3181lDrY{*;5J#GDWO4*gy?6)IBa&Po~NRUXmI`+wy?CeB%mR(Tj;=P$Lq1OE^ z+i7nOxu0b_El-ixv23U19mstx+i7`6av#ffTHcA=+p?XO=aPF_w$t*?^DjU~}3V(8+<#X&*pG2R5gD0UaFJoUQ{%Ij}kH z2gq??bJ`yeIQX1K!tJ7m#pZb2+ZWLY$dj76gXSTqKJMPmV2G!B48;{jMS0f0pl0a&y#0E;#OV9_K17HtZ^qRjwU zG#P+JGjQ02WmOu&4@vMb!W-nhL<8X#gy$0mK$^O=MZrOqNAkkY&-9WLY$uj73`k zuxM)l7HtE-qHO_Kv>gD8wg+HQ3jm9D0ASG^02b{Cz@oVTESd+vqE-MF%?Du70ss~* z1Ypr302b{8z@nW2ShN^`MN0r!v=k6qRGUcFnjpD1SH02Un#z@kF{Sac`=iw*-|(cu6rIs$-2M*^_uC;%264Zxyf09bS^0E>i!K9T z(d7Uvx&nYjR|2r;DgYK;4Zxyn09bS_0E?~zVA1seEV==JMgIa|(TxBsx(R?qHv_Qf z762CA3c#Y<0I@}h2cZo=CZ0ZqeO|@Ymk5=pNe3qI=1*=svP6 zx}PkI9w5u22g$PNA+jubm@JDPAB@AAhp%l12Ufi1v0O<$k$E?@&{MzUTwm%c2j-vgjkSEc%!% zi#{RCqEE@P=rgh``kX9_z97q@FUeT+6#$FA24K-Q04(|zfJNT{u;_aL7X1Lgq8|ZR z^b-J!egPHV9_4{Ecz3GMSlUX=x+cP1zG7{e%wb(0I(IT4~?f@+60l=c304yp3U{Nsui+TaDs5bzM`T($~ zF93_y0bo%-02cKJU{MJGiv|F&XdnQK)&*eEAOIGv2Vh^cJ^+h00K^uBS;;F+klbdw z{hpnZ75DUeL>;!Ql>6lt4b2Ll7$A#=(Own}C(EJ{WLZ>7mPKV`Su~O?i$;-U(P*+P z8bg*vW64-F4uD1D0a!EvfJGAlShO(!i#7pZ(IfyCZ3@7m%>Y<58GuFQ04$mUz@iEO z7F7bUs0x5Z)c`D-3c#Xi04%BjVA19PESe6$qFO*~(S}*cZ%vTgd4ADxBU#kNd-^l7 zQtp>qG%G7C7$l1tXfKNz$+D=4EQ^}SvS12V9^`^7VQYYqPYMpng_t5Rsa^w2Vl_x02VC-V9_D~7VQMUqMZR) zv>1RzO8{836o5s`09dpffJM6iVvFjtl4DJf+)CdU&6Gu*{D`(9E9HK84h3M*VE`;T9Dqef0I=vt02Unuz@no8Sab{ki;e|g(QyDQIv#*UCjhYML;x0@ z1i+$`0a$bj0EZ^7F`LzqN@N{ zbTt5rt^r`twE!%-4uD111F+}@02ciVfJHX~u;?ZL7TpZMqFVr1bSnUhZUbP^?Eoyg z1As+$0%D8K$Vxt7g5;i=FmcY5MgD2$?7Om3?w4D1Usm|RhO+2>+RLH`$g=1`vMhRt zEQ=l{%c4ifvglE=EP9MAiykM-qJNXI=m`K8Jqf^~rvO;=Gysd90btRy04#bAfJM&( zu;>K<7QG0-qL%WLfkL8H>IJV9|E~EczaRMLz(r=tlq+{RF_Gp8;6(3jmAO0I=v+ z02ciQz@py)So8+~i~a;)(O&>8`Wt{n_BrIUY&F^)b-PsKcViO(EXo34Q4)Yf*#ImG z0kK6NWF_lNklY=7U-Y3Y`prX5GUa}`MV*r2vJtW3>I1-{z5py*2Y^NW09e!? zfJG$$EE)j7qJaP`S{Hytg8*2x9srBh2Vl_#04y2|z@i}lEZPtdTht+$JlO=vZSju_ zbxg)R{aimu+9;WFzuck`$?)bfSyW1USyV=rMI*_wXcSo%jV8;YF=SaZmMn|Lk!8_% zvMicF#-fP;EZP`=MVkPyXc7R6HU(hOW&kXj48Wpt02WOFU{M7Ciz)$FR0Y7IY5*2Z z1z^!M02b8%uxN7t7EK3WQ7r(AW&p6L4uD1VfY_p8$>i%MNUs0xN%nAA^sVoUW+qea zms`}741XUbi<)UKi?$%kqAkg?Xf|0EZAF$vTa#tcHe^|}Em;!UjD*%h;1F&cT0E-p^uxJqgi*^EF(ar!YS`5IVB>*g13c#Xe z04!P#z@l9MShNCwMJoYVvSr+Y0mPPxJWzoK5S+pNn7VS@#MF)^&(Sc-HbPySf4hCS+Apk5o6o5sC0kG(B z02Unqz@j4oSacKsi;f0h(J=rlIu?LM#{sbDcmNii0KlRX0a$br0EqeMb`na z=z0Ja-2lL%e*v)QMgSJw1i+%30a$bk0E=z~V9{*=EV>}2w46D0R7x9A*M^pS^qlPUMhEqX8+K4o8Fjqb)iM0;8EFj*EoLY763l4a3j zWLfk$Sr+}9EQ_8X%c3XAvgj!?7CjBXqGteD^eh02o^8hS*0f0p>0M02aLr zz@k?GSoA6Yi(Ug@(dz&#dINw(ZvwFBEdUn14Zxyz09f=c0E^xOVA1;kEcyTtTXcUi z`Mn8}d%vGhKOl>i`o8GHWXk<=i#|<;-6qMR&uA};J}1kfFUYd!OR_BbiY$x1Cd;C4 z$g=2LvMlH{Q|(EH2^I76@W#*0kG(I02ciLz@k3^ zSo9YFi~a^+k$t{9?zUr50)RzX04z!ZuqYdVMIiu-asXJA0$@=GKy1;+$>ewwBzLS| zuKq+8`A@HAcg#+?Uv5#C>~O2iWKkaNWl>kMEXpU#q5`rkDkRIIZe&^1oh*xbkY!O% zvMeehV^J{xi+TaDs5bzM`T($~F93_y0bo%-02cKJU{MJGiv|F&XdnQK)&*eEAOIGv z2f(8B0a&yF0E-3#uxJPXi#7yc(MA9)8VbOoVSw18-0bAOCP?mKzAx&W9ryJ8hcvT? zXQ$jRw`gQ`cwV_I8by0qG@2}n#*k&vSh6e{N0vq7$+BnySr$zs%c70RvS<@B7EJd%vR1LtQsQ@gR2Ed{k02XZyz@q5@EUE=y z(F_0<)d8@m9)LwN0a!E(fJF^}*rL+x2Xy>TImYs6H+@ig+!;PwC(LS`7Mf;Lv(SBrE zv_DxE9YB^v2a;vcL1bBUFj*EILY75`lCkJ802Un%z@j4nSac)+i;e;57TpTKqT2vibUOfx?f_uXod7Jl3xGv;1F+~G02bW~z@qyASad%iw&=X< zH2@a94#1)} z09f=U0E^xNVA0zEEP4lkMehQz=sf@yy$`^m4**#7Apna$0$|a{fY_pkvXgI`Ai4ev z_Sp~1qIbQg|4DYr{c?-G$PWLspHPdg7kx>4S@acI7JW^YMc-hWLeaMEQ@-QWl<4X78R3aQ7^JA>P^O? zJ^(E03&5gv09e!yfJOZQSX2VQq5%Lb8VJCmbpcp32!KWF0kCL&02XZkz@otbEE)p9 zq74C9v=IP{h61o?7yyfg1F&cW0E14VA0M1 zELse}q9p(1As+) z0%D71hshsJklfGxRA?(%G{;Yp_6k$(ms_-781~pg7VS@aS#$td79B{IMF){((ZOU{ zbO>1%9ZHr(hmmE`;bd8K1R0Bt1Ypro04zEhfJMguu;^F-799t`qT>NrbOHd2P6S}l zNdPQ58GuEn0I=v(02ZAFz@pOuSab#ei_QdK(OCd2IvapR=K!$iTmTlG2Z$}&CrnN> zL2_q%w`^Zol<((7=Z7ix%PqP%47Zsri!PzPEV`5|i!LL}qRYv$=nAqdx{@r5t|H5# ztI4wH8nP_9mW)N$0kG(L02bW!v#1c)uVFih@mg5<99Q=yAw z(WCZS_QPSy{c?*Q55o(#mPP-jy)1fyEQ_8b%c7^qvgm2DEP944i=HLRqUXr6=y|d% zdV!2ZF9NXWB>)z^48WpS09f=Y0E=D&VA1OUEP4ZgMQ;MI=q&&iy$!&kcK}%QE&z+( z17Okn04(|dfJGkyu;?QI7JUrBqE7%=^eF&~J_E!SJsKt-F+pq94h!=qIu)`k5??ej&@EHDoOM6@W#* z0kG(I02ciLz@k3^So9YFi~a^+QIMlOq!8J;}1Dh%AeW$+D;ySr+vs%c4GHS=5&-i`F4yQ9l3{^#@>42>^=*0I+Bv z0E^ZIV9_7|7Oe-sqV)k-v;hE%1_Q8Y2mp&V1Yprd04y2`z@lLQEE*2Lq7eWrDg|Is z832n$0~galF4kAR~71QZP*plBcgMS}<^8caaZ5CV#Z5>Rv*0Y$?IC>l=i6}5;7Y!Dzp z^M99(ZmEi%GJhR1BE~hojG`-JoTtaAqN}*PD#~T6qET#Bl*d*@quHux3|keAWvilm zwkjIORz>64C@LVJXaWI66A37~nt-B71Qbmsps0|5q9Ou{rVvmxm4KpY1QZn$P*g%d z(R2ceW)M&`lYpXG1Qg9CplA*OMb{8eG?##)YYD!hD`Enl3y|PZ^Zi95Rgw80P(@!C z;~HN^(ZU$#LcS_m#N}1dVzw$;!d68~*{bMzwklf2Rz)|kRnc;`Dq6u-MJw4Tx{-jQ zRRk2RCZK2y0Yz&GD7uM&qICom-Aq8ydIE}WA)x410*W>eP;?ssMH>kyx}AWcO#~F( zK|s-+1Qcy1plAyLMRyTUbT`3QG(RR#XPhW9|HtX*1*)iGT_Y*lnWTNORPRz(l8RnbFiRrD}h742fHqDR;$dX#{o#|S8ToPeSy2q=1z zfTE`eDB4Xx(bEJJ?IED(83Ky-5>WIk0Y%RdQ1mf!RndEFRdk50iVm|?(fe#w^Z^@1M+hkTkbt6(2q^lPfTB+bDEgFuqR$8@`ka8G zF9;|)N>PSWS&sJp^Dm>k7z%}xW<=J^h=EM?j%)on#-%AU)ieY3|kfb##TjV*{bMwwkkTu zRz-iXRnebpRrD7dMdt}9`kR2Fe+VeLKtPe@>Zk1}vI!`PBA_ThKv6USMGgT)F$5I3 z1QdA$6vYxy6h}Z&kbt6i0*Vp{C`u%tD2afg5CKJDg0JZ3n7~;95`4nE`#GhGwwhJU5KuIffTGI?C>lmU(QpEaMi5YR zIRQmi5PU_g-M~Tt68v0dbQ@K)(Y!Aj>AJ?3Q8dbR?kQG9d0buF;dmaU5N z*{Wz9TNRCGtD*w7Dw@DnMHAU5x|)EZNdy#4CZMR0fTAJ-ilz`yG?jp&X#^A%6Hrt_ zK+$vpie?Z{G?Rd$Sp*c#CZK2z0Y%pkP&Ai-qH75#x{iRNc?1;AC-{o4as#glkYIiD zX<4o+a?FRf1+Hs+8AVH6=lkiZXepOhMc1=c(K5Cwx`C~Vma|pS3bra*$yP--vQ^P4 zwklf9M$sAqiq;ZPbQ1wZ>j)^inSi481QgvuK+&xP6m1}&=r#h1HWE;DI{`(T2q?OP zfTBAIDB4Uw(G~)V?joS*ZUTz#A)sh00Y%#gzM@5LAaRB$x=UvCVpVk7eDUaB*EPP3 zqMfdjIZGAY&*fFo18i0FAX^nZ#8yQQvsKY9wkmprt%@FHtD?u)s_1bxik={#=t%;K zo+6-VHvvUY6Hv5=fTCvzDB4Rv(X#{;Jx4&%^8^&_BcSL70*YQFplCks&V2A(-9yC82d!H(5XWkdR;kw3`QS^@MOrN8Q4sv-_ z^e$T!y~kEXhuEsonxz_ zKiI11Pqr%hi>->zvsKaGY*q9R8$}lgD6%~Lv>in@0Yy;+6a@$lhuvO8;Y*m!TRz)@0s;CxQ z71d^=s15-|bqOe{M?g`10*V?CP}GosqDu%UYD7R$V*-lO2`I`SpeU1oqAUW6vI!_^ zLO@Yd0*aauP}H1&q80=cwIraZ6#+%93BICKFHlc_1V@-}lCA9dpXvW)e#Ehj=Nex| zQG3tnzCaaq;PR@dBU=^auvJkfwkqn(Rz+Rds;Dbl6?J2)qV8-})Ps$po&*&2BA}=@ z0Y!ZXDC$c`)BMer51^#YRwNU)}PD%4IDEi~_oay{4hGK$7{&W(#y(O538it^d2 zXdGJ=jc2Q(0=6oez*a>Q*{bMjwkn#$Rz;K9C@LhNsEB}~DFhTvC7@^;0Y$|G6qOKA zG@XE=83Yu~B%o*(0Y$S3D4Ih+(KQ4V%_X4dS^|o$BcNy=0Y&o(C|W>3(Lw@>77=_! zd0yaA0TOI)o(hdtMdp83AHCRfjW45Undcl@qKa7jcBcSMJ0*clXP;?6cMYj@Aw1I%4+XyJyNI=o;1Qcx|py&<) zitZ$!XfpvtTL>t+i-4lL2`IXUfTFDg6m27*=w1Sfwi8gagWxM#>IKdTkl=1x;9ReY zMi^4}d9Lwg6g}uURhFruhq$~ddYG+>cCl5_BWzXlC|eah##Tj-vsKX(Y*q9mTNORU zM$v8pik>E*Xb%BJ&k#_wmw=*Y2`GAwfTHIKDB4Fr(F+6=y+}aOegcXP5K#0I0Yxtp zQ1l7`MXwT2^cn$0uM<%81_4EH5>WIO!B=#@7icd)g8gJhKcI>{^AYWB&o#b`qW3%} zceyG$#N}1dVYVuIpRI~MV5_1dY*q9jTNQo8Rz)APRnaGGRrDzvMV}E+^f>`VUl34q zlz^fy2`KuCfTCjr6n#xV(KiGXeM>;mcLWq2C!pwi0*X!$Q1k-EzL5Q^=Nex|(eIwKZKWzY$K_SgA8b|h zCtDT$#a2b<*{bMowkrCEt%@$NRgo2|pSP5TNTw~qo_UsMGXijYDhrQB?J^TBA}=-0Y&Kq6lD-llu1BQ76C=s1QazP zpr|PUMa>8(YED2=3j&H-5>V8NfTGp}6ty9s=u!fT+7f(4RbvC8)uO1ic|u(+*8fa@ zvKj4SUE|9r%87Nd*Q%mUTwWD*W~-tuY*o~it%|y_RZ(}gD(b;jMLpT7s25um^=6}} z4*^Ae2`K7EKv91JiUtr+G?0LzK?D>HCZK2t0YyUzD7uV*qG1FS4JV*z1OY{t6Hs&o z0YxJTD7un>qN@lf$|ay^6ahtf1Yc2y*uZ51B-r1)FY2g@`bR!ti*=1Jqi9^LGjp9P z8qeibQ2|>OO<=2{iELGLHCq);VymLbY*kdqRz*c@RWyZ-qNxNFO(USFn1G@Z0*a;+ zP&9*pqL~B~%_5*^HUUL*2q?OSfTFns6kSU|(RBnA%_E>_J^@7w2q;=eK+z%siWU=4 zw1j}7r37Em*x0}(0TMiHzUr8-ih7xEHo896HNK3Z6|v5<>s8T8F0YDiWUHc8Y*nt+m4KoR1QgvyK+#45if$*MXcGZNcMwo? zCjmv92`Jh^K+#T|AfTA4)6x~Na(M|%2?kD()Zio$h zB|w5*WkxSoMcvJ({SU;t#+OmFE7l2YP(_b$c~$f%TNORVRz;7qRnZe{RrDlV6+OjP zMZ4Lm=xMep+QUZCGXxavC7|e80*am^py+u5iuMsu^a24zFA`9+pMatR1QfkQK+($t z6um+~(W?X$y+%OM>jV_NK|s-)1QfkRK+)R-6um=0(LsW*=%Ls^0|648WWIL&uqt}j ze2(^RtZRH3MeoNtJvXYN54gN4I>J^(AF@@^M{HH}FjuBAwH33E65K#0j0Y%>tP;{JtqVEYPIzd3u4+IpQB%tU=0*Zbj zpy+1;icS$w^a}w+rwJ(fm4Ko%1Qh*7@D&}34HOEHU>^hLuqtxQzZr5i)-}G2qCaDu z)tgk&UtC@looB0}zuBtjAGRvGz*a?8oPOr6ifpzjiejsx09zGBvr*&_P!vNzkxM|4 zM?g_50Yz~H6a@(=iYK5bfq-=k zvsFyLs;E9&6*XY1qK0e~T|z)nBLa#V6Ht^+Kv4z(MVSN?Wf4%6O+Zl- z0*aavP}GcoqUHn?wIHCVB>_dP2q7GU>Y*o~Qt%`cGRZ%atD(cNv zMSa++s4rU;^<$%`KLJGp2q+pzK+zxqiUt!6wN1~XaNC53kfJ%L_pDE z0*aOpP_&eQqU#ALT1G(84Fq4&__)AQ0TTShy!$CoMK7BtNz3D0t%~-rRnaqSRkW9_ik@Yo=s5z4o+qGa9|1)#5K#0Y0Y&=>C^|qu(Mtpr zy-YySD+Cn1N*iC^|+!(bohNeM3Oew*(Y@M?leW0*byTpy&hvML!TwbdrFg9| ziGZS?2`D;6K+!J*6rCoZ=vM-Y&Ja-a8v#XU2`KuVfTD8*U(p9~f#Cuq7-v2$JEDqO zn-6b)#JR?oQS^75Gy4Hm^beO;MHkqr$O`Ib?yAUUtD-2jDhjYwQ8Zf>Ic!xF!&XHu z8$})gMX>}F#Su^xB%mmsfT9EfiV_JZN+O^rL_krPfTCmqic$zDsz5+dMFNT{5m1y$ zKv87^imDJ$RF#0DY6KKjC!pveg0JYWxWJtPB>0*6Aa-6A-6AiGt`T&NFQced(0TqL zRaBeHtD-t=RaBR)it4ddQGK>5YQR=S4cV&b61FO8#8yR(*(gdUpeTcYqD%scvIr>3 zCZMPZ0Yyy-C~8JPQF8){S`bjwl7OOC1QfL15mr>L`=s1t4q8?mc74>ARqF!uO z)SIn}`mj||U$!dh$5uuC*{Wy&TNMptqi7HTMS}?_8bUzPPy&iBBcNy)0Y$?JC>lXP z(d7gbT|q$6NCJwkB%tUj0*Z18C>ljTQ62$BqX{S)LqO430*dkpC>lpV(RhNdsB18A zi2w;6G~W!;O%<(>mqix@UE|9rniO<;Kc32rujjeoT&nqWTD zzcJ_RwM z0YwiGQ1l=HMGp~B^e_QMy9g+Hgy1V$9Sl4vK!RJ$`=T|fD8qb2do<`8Uq;cBLFdR* zs^}>$uZniFRngOIRkVk#ik@MsqP=WY^ekHyJ;zo>&$Ct0J~oP8AfV_)0*dw%P;`KR zqL&CLdYOQtR|qJ2m4Kqx2q=1;fTA}DD0-8CqPGYrdYgcvcL*ptNI=oM1QfkTK+z!r ziVhP{^gaPa9}s*+j|T(i1xWB8^LP4BsG{}eebJGiYkV0+p9GzY_Nbyyxx6a+jID}3 zXRD$w*sAC#TNQoDRz+X2RnalFD*BqOioRi^=vxAcz9XRMH~~f96Hs)5fTAA=C^|_% z(T@Za{X{^~&jb{mBB1CO0*X!(Q1mMSMP~>o`i+31vji0VPC(H)0*d}1py*EmivA+_ ziarVkIth?qTD-vdSQXVa?~Bd{UE|9rvf`aFdsUGgub;`QqA0d13b0jCG+PxpY*iG) zRz)sb6?tq`6w6jcacmR?2`GvupeTWWqC^6Uk_adY5l|E+peUJuq7(v(DiBaqk$|E~ z1QewbP*jyT+GMR5#wa?>SXekISo~`fOFyfUSxevQ^O~Y*o~Vt%@46RZ%)y6=kqhQ6?Kj zSp*bi6HwHIfTE@Z6g4BDs5t>eEeI%TNkCC60*YD_P}GKiqDu)VYD+*-I|7Q@6HwHF zfTE5B6y*?5)QNzi&IA;7A)u%$!BjLL2Oktn5~M2uu(LWfTGI?C>lmU(QpEa zMi5YRIRQmi5KuIdfTAl2D7uP(qFe%sMiEeyM?leN0*b~EP&Af+qI?31#t~37o`9kP z0*WROP&AR?E9wy+sPKX)a?Dp9d#WPy56(ni9q$@nMp03`(|o@wn!@E((Nwl7n#NW| z#cWkn!d6Ao*{Wy;TNTY@tD;$KRWzH8qB#TD%!wSMYpk4(MGl^x}B|x zHnCOF9c)!}CmThZ2`Jh^K+#T|AfTA4)6x~Na(M|%2 z?kAw=0RoC1B%tUa0*W3cplBBXMUN0r^e6#Ej}cJxIKfwRQ+!~H00}lUpQEi)MbAb) zVT*T-FQe$`c;|&zRM8$TuZo^wtD?PZRrD-d6+OpRMbEQU(LS~+dV#HqUSzAH{cIE+ zAfV_a0*YQHpy(9>ie4q4=rsb0UMHaF4FZbZB%tUm0*c-ypy(X}iVhM`^ezEK?-5XR zh=8KQ1QfkbK+y*T6dfU;=tBaEJ|g&vo{A5AD?oyo=H1V3Ra8S>7X5L&YkV0+pUeNx z`gK+G1(#PvN7<_AOSUTdimi%{u~pI6Y*q9PTNQoFRz=^jRnc)aioPeH=mY^pKM+uK zl7ONg2`KuBfTEuXC^|(z(JurPohG2@R|1O85K#0R0YzsCDEgg%qH_ck{Xsy{p9B>B zML^Mc0*d}7py(fhujteGKw|+CeAfJ({%5MFviVH^LcD8y8AX8vr|+ApC_3TapXobn zRTRTkMJ`(vd2Ce_%T`5kY*iFwtD<M-Rg}S2 zMVV|>l*Lv>*=$wRgpH!61QazRpr|qbs?arD*;8_2q@}KKv55Zuc%%^V7CAXHZ*YRtD-pb z;jL$aYkV0+eG{CI4yvMlTwWFRXRD$CY*jRnt%?S*RncI!DjLF8MMK%D=rXn{8pcM^ zZ~}@(5KweE0Yz63P&AT&qALj~x{83JTmp(l5m1yzK+$LdipCI7G?sv(d;*Hb5l}Rq zfT98diY5?HG?9R!s|hHYL_pDGg0HA|Lf{_(63jR6i~6V{^JSvw!UWg&GK!`pI2RvM zMa5iR6_v16(R8*dn!#2@Guf(W7F!j~W~-t(Y*lm(TNTY^qv%=!imoG|XdVGY^9d+g zKtRz#0*V$9P_&qUq9p_rEhV7ndIE};5m0mk0Y%FRC|W^4(Mke}ZX}>+6#+%72`E}a zK+#$Pif$tKil!t4x(JY9H}g%hQ&mwb^S)?Zf@^#kMYkq6`R}Wu4P0Io-Nsf$8`-Mp zcD5?o#8yRjuvO8WY*nT|AfTA4)6x~Na z(M|%2?kAw=0RoC1B%tUa0*W3cplBBXMUN0r^e6#Ej}cJxH~~dZ5K#0a0Yy&{d`0UM z0?P$R@UZ!+<1MOar}<2OcY&ocoWcqG!3hDteBsik@eyqJ3;t^a5KIy~tKY z``N1K09zHk#8yQwvr+U40Y$G8Q1luBMXwW3^acS%ZxT@S76CiGZS?2`D;6K+!J*6rCoZ=vM-Y&Ja-a8v#XU2`KuVfTD8*6#YR! z(Vqkq{Y600c>;?5CZOma0*WpWP-G?QC*~-!3BIB)5(1Sz7DfBa`=X<&=x6iovr&nz z@nsanBswiWRYfkBS4AFM6~(euQ5;(p1=*@7o~?=!*s3Uzt%{P^swl)pQJ8?DWCDs( z2q>yRKv6{kiYgIMluAHRWde$-5KvT=fTC&y6jdjn=pq7&Y7kI#F#$zs1QgXIpr{rB zMYRbiszX3gT>^^g5qw3_iGh&0el<0Sf@>B}>1`GhUeHNK3ZMv2a~pR1zATwWEW zvsFP|pW4+4sM5>V8OfTG?6 zUs1!vz}*5Qc&qtd$4gYv*M?M|MA!H-iUuS)`;V%kfm~h{4PvXJ!E9ADgsqB(vQ^P# zY*jRjt%`=TRnZ8xD!QDFqALg}8c9IWl>`)BMLl>dQ2_x(69_1pNI=om1QbmoplC7yMTGy+| zq9*3q_0&Yy_%e#7CpxjmRM8ABuZm`}RnaWADw@q!MRVAy=o+>vn#)#2*Roa7b!=5M zkBy@F1QabGplBfhMT-b1T1-IE5(0{r5>RwK0Y%FQD7t}wqU8h>tstOiB>_b@5>T{? zfTGm|6s;kkXe|LnHxW>@j)0<@2`E}m@D&v&1~LRlFvq+vDnXHXc702tYkV0+8xx)W z->9P7xx6ac#8yRjuvO8WY*nsu~pH_Y*q9MTNS;^Rz?iMQ;#L^dLqO350*b68{j?oLHUULZ1QZ1bD2gWdioQw=SSLi$ zvj)yFRW#F(a*|x*%P5LXa%!GbMR8nS6$RO7lAfTut0Yy0k6m=q?s51dYT?i=ZN0Yz66P&A2vqR9jl6%tTXL_pCL0*a;*P&AEzqGE!tXkb#{ zJpmG&X1;bkNEJ0Q?~6*3T;t0qnw8}IdRi6D=JKj&4qFvn!&XIe*{bMTwko=gt%~Nc zRndI5Dq6r+MGM&|T0}t6Vgibm5Ky#~fTHUOC|X89(G3I?EhnI81p!4X2`IXefTC3d z6s;zpXbk~HYY8a2iGZSY1Qgv&K+$>vif$pG=vD%XHV}M8Gm-+8e-%ZG&EKQVR7H=P zZ+yHh$u+)=qC1kD*1xHuJGs0n+RRo(TiB}TF19MVo2`oOVXLC8Y*n<4t%~kttD@~} z6zw3O=sp69b`nr@KLJG#5K#0W0YwiHQ1mbXMY{+ndW3+YM+qo;jDVuY2`GAkfTAY} zD0+&3qTK`(JxxH-9s-J1+Eex!Di-t(I!>&nE4Xqb4jl8WfZ-b z5m59t0Y&c+ zP;`)hqIU@>dXIpjLj)8ZCZOnj0*XE$py&tzMIRDS^br9?9}`gY2?0f)5>WIR0Y#q^ zQ1k@>MMnuJ`jUX6uL!=PeMy0>0wmbYd|LK`Dym_=1bHmUHNK3Z?~buvO6yY*loUt%`nRtD>LSs_197DmukhMZd67bee#oUkNBWLqO4Q1QeYmpy+o3 zip~*G^alY&e-cpi7Xd}*2`KuTfTDj0D7rvEkrmQU+fif_P!vT#QGkG=Xab5H0*Yb? zC~^tDqHmG{Cj>}vfcYTytt#4K-WPcx*Z4Au;zLgGyedlI@~SA2t%{P^swl)(MParo zN@lB~6t*g=z*a>S*{Y}#8%3!E6jdgms0sl^RS77nMnF+@0*Wpopr{4`MHdrLltw^N zO#+H)5l~c{fTB7C6xAi5s2%}D^$93yKtNGL0*Wpnpr{c6MU4r*qPS2XOMnC&11A{r zKhuBBe0WO_xyF}KlpS&g{-cVTaCueKl&y-Iu~kuXwkm4DRz)q@s;CuP6}4uoqBd+* zbSWD}Z3!r9M?g_~0*X2iP}Grtq8tK>IuTIRnSi1$1Qc~8pr{)GMcoM~>OnwJPXda1 z5m3~dfTBJG6!j&bs2>4E{Rt={Xe3(|UCCBOSFu%5E?X6iVxuUJfTGa^6pbOE zXeyzjew$J z0*XoqD4I?{(F}sGXhThY*jR$t%??~RnbDWDq6%=MT^<0XbBrdO9?2to`9ld1QgvsK+$pnidGO%w32|L z8wn^{ML^MN0*clUP_&kSqMHaPT1P<9%>)#!C!pvS0*Y=WplAaDMYj=9w2^?K+X=p+ z*`YvGKos3(zR);F6>T!_i#CN^~{2C7|d%0*Ve1P;{7pqW1|X`hb9%=@APs^~%U?E2e~ zYkV0+CqmA{v8w0?F0YDCvQ^QKY*q9VTNVAxRz;`Ss^}NCDmu+pMZdCD(HS<1ej}jh zECEHo6Hs)HfTBMLDEgCtqQ3|zI!{2+-vku>LqO350*b7#e%g*An}DJy0*V3z6h#wI zHCZK2t!B^BI92g})f*+Zu zLQPdsL-Xu~w3w}mmatXPQno6(o~??Ou~Bpb0Y%FRC|W^4 z(Mke}ZX}>+6#+%72`E}aK+#$Pif$sHXdMAXHxp2_o`9lT2q?OhfT9fq6x~KZ(MAG_ zZYQ8<69Gkc5Kwd{!B;dl95^XJg3ZjkpKDdoS~E6>UE|9rx+m-;R8&P%*RnbniD!QMoiXLFAq6gV1dWe9chY2X!ML^Lb1Qb0=K+$6a6g^Hr z(Gvs|JxM^(Qv?+4CZOnP0*dw!Q1lD|MSBS-dX|8q=Ljfzo`9l#1QfkMK+%f?6zwPY zitY*rnh20!lKJlayH!zD^SIRQmq5KwfKfTAx6DEf+kqGJRUeN8~oHv|-YOF+?g1QZ=7_=;W*2WAP7U_Me-lvj4*^9N2q?0W_0x6~*#s0t5l|E$peUMv zB8PyY7y^o10*X8Wied>UiX)&XNI+3M0YwP}U(pZYz;gm5_?!6~kdvyYhWUt=nCu!~ zMp1II^F=jPl)~jzQ3bXts>oJFmDs8%m92^@vsFJm^?kAR~31QazOpr|1MMVAmz)QEth#sn0l6Ht^v zKv5>6K2QOjhfZVgq`ip#5_ z)@)VOhOLS&WvimLY*o~bt%};SRZ$1FD(c8qMLBE~bt0gsGXX_i2q@}GKv6dWin-2RWy!`qVWV26%bG~fqCL zK+!Y;ii!y+Dj}d~Isrv92q>CKK+!A$ie?i~G>3qqYX~TsOYjw4o*Y;sK!T&p_g!D1 ziVDqB?Q4@=Jo(B%tU<0*Y1fP;>_YMRyWVw3&dSEd&(ZMer5POAdS>K!V@OjGnKGem3LoWY_qzlB}rc z+Oak3*;eR5`72v1^o{`+`bEA>>4j2ag;}V%{3To{G%UfgDuixNvaHIXFT<8qJygGf zWu=8CSF)@+p~os)R)f$VRV}M=sKZ5;l@(fYv1K(2y;0M$T7|-OEURs3SUtR-aH&rezHXJ&|o$LqdNwwXETxoEDZfGIV__%NiAWtBqxi4W+cR ztb)*p4wf}3v^mGJri8xfY*{6tM%^rHR%mJu%bFW{s+VQW5B=T8vKEIr_qVKNp&JHT z*2>U3gDq=KsN!Xob#v&7;g+=_bl2sUwJG%7NXyz1O3$^dt)b#P%i0lodW>Z~5W0|W zS-V1A3oPsL(29wcwLA3gB+J?xN-eUieW5F-TGoNkJ;j#wYUumvmi1;RQ~sA22Sd~6 zSk~dtGjlEL!;n4CvOW!UUtn2BLpLt6tgl0dmRQ#DP?cqtbuyH@+_FxEwym_RGoc?= zS=PBw_FBt2AD+2R?teS{?0R_s>~LU%JOXyO=SF!5?C|PM@)+3R_wSSk!46luOCAL~ zoOh2r40d??HhCQEu=&5)*RjLqe@EWH4x9gcG&zMU7Oiq^S|V5WrxlG zQ?acbHvdz+j&|7mU(LGMVe`MG>S2e?|5vDw9X9`Cm;rX!{GUCB*kSX(W*BaV&A+Wb z(hi${9DS4>HvhWySUYU~dEx>)Z2o=ONp{%$1EEvwu=y7rOYE@uC;DdDVe@aS&9%ek zAIX|;ht0oowAc>sKPr!q9X9{Y$VxkG{-KC9cG&!+|IK#T{HXQ@J8XW|c9R`8KP{4q)7(BgY`*L1 zfE_m9w(_bSHs5#frX4naaeUAYo4@%xY=_NX-F#?=&DY*PwZrC%r$_Cu`Rdo#cG!IR z;67hR)xekQ?uluvOM!5`Bh<n0D1_IXzo`i#e-ecXPhxiKgwA z-;c`gN`lw2TSS^w>4bTeEp@Ck*U&0)k(|M*^s)RAwp;57_b0n9)|p zAakqR={PIz8|?Nv{xoky2OZSga^kBWX)v#{Jvb(OcJ|Q#zp6ai*8O_H`0KW{aOHwd{E-&V){x7^ zgm1g^*vGRY7d-LTZ|mebh+*3w-YC0w^Z}n2?Sy+J8aiYObG@O zt0fLi4cnnq%ZjRF1%vG+SyrHu6-aCoyfoN4*fT{QKYfWjI!<%Tl$azruQ}nS*ukKG zPFtpzUd=)E2{F^PL(aIioC!wFR-kt{(07Ss$y2P z468$xwp9ufBR55En>^g*e}!b&@_|4OgCZw~n8T3B$&uz@{uo7DzuE&f%lMC9@v?1e zpgA0koV?5&xWvH!<`R}A558PxkU7XZJvlkl9ORvw6|km9Z#E~mfFLSl!f0f@$Z0|KD#$@$BOA_r&;u%$#Xs zr%xy>>RdD}KfUz6m{l?@a+mn`$be}@6XiZH&Kx`?Z`#$}rWfW8k+)_1fJxJfa|h+L z=-d4N;$fPRSCVh;Ez8mex^?sE8Dort+_CxN@}^HJ$t{^ZCBHbM!0?jCYV3r<5*hMt ze{konxpEuFbS|1axu{T@kV4A@bG?4D&SUi&B@IF?PQj@ za7C`FPWh`!i@c&Jxw;0Dqs%Qb$H0^fr*`B-NM1waC7Gq?NRParh;xLwjU}IPmD^uW&RQkIscBYb zWYx?t_kK-1{U0YY<*`n2ob;%w@_uJf*Y3I9vU*tNnB6L?NA76uGW#;G`+BR!uZ1cv1#%rCGzSz>+Q-I$hKRPM&e3*|1>%QY{(GPz~E(k6QT zre(LIbLl0rJM*gKhU+Dag>oNX{;%GvcF7+-eZ2qH$Ri=IOWskJdnojFG%LGl^0517 zFMV6^l~wkpv@X5b*+SRq-E~B6PM1NE%gH0EZ;{B=Q(gXbNo!J3;rO)3fBuWE?6Mou zNde(Z9<#_R0G6Sne-QNTD}60pBiAy~{9%c_C`+$O?CLG*RC?RYpVG*ga!N0r-30(m z^<||ZxDnZ{O0O!r3>`=?l3k`y-Wq+?$S5@+?-2Yqpo~S}@ zyb=E8IAI>1$U7r_h;z*cx^dGB$7E+^MP8tPI?DBI{{q=%cTu@VzNKCtkB*PZyoOd~ z_n+Lm{&h6rwU?>LE@P2h&V@W=`f5w>C?1&XPI_nXu(U2ci`?OQua>>v;xTJpc6)pe zk-MRcKz2C;`RqrT>BF&jxdj`ChcU(~epE|fchvzJNW zLFO?oeOz0~{Z~|~SHS3H`Iunde`u1+m{XC5FDJh^yGg6gVa zKL!a||1OrB6*(dI6gR5uRYY#GK{7<1De3vSpgdlYVh}_=6!{;4x|UvA9wEKPvRjA& zxd-)SrH{2dME+|ivm@_pLyt& z{VSCBwU#{pp61_;+5SO4UY7C6F7s1Lwv3H@D3(`UTu?Nvr1Ya7kF_BgQBn$|^y9Sr zL5ti5^B_jZ$=&0hC}*b3NOl<#dGNT4c!;v)#zrnIAIKv|9)fHE?_aAg;Q#XT96n9* zpFKz3hB7MhX6eJ2El+Cvn;`Eh^hBwIY(cH(EBC=7TQ4Di^o9QW(eC|*rgd)JI?a3% zl#!igJ`Kuh)udTkgK7Db^7D%G8>XdC9y4WnyD{=uvDq!8&`v(7n$aqKa>iu&w5-wC;wg>BO-V~1 zpO)UgNm{ymD$s6>+<^3PlkeBbeJXI}w5?S^fGP~@ZHP#J;$ZO|$Yj)|= z(9&m|<^E8W{n03Uz9{b=BUe%OY*9Y)mtLvdhgSE_o!g`}Fn^44rcF-kI(c;d*s=1Y zeF$HMi2TXo%L@(v=RariRTJ~|pbPR#zB)BGF+Raclg%&lMVFk!(BkMNfu&Ka?5Lu* zUw-L;d@(4ewVWf*d>zBGGv%byD!p$;-<+QPteCLdH#QLGB}Z4VE83}n%61jIs$I>l zZr6yaWoO9s{pYXpDcbtwLiv{m^y^5pfPR^%Y|E$e<$eX^(|Gf>s8 z>&C^A%@51uXg7opQed*1x|ZCx7Ww?xp7PN&m6UYcKm1u;hz;<$eXM zy%h^#{Tcm7s@>yl&6WM zEAsKRbY*8{%j+_?Ax_?m56w|->~T5Ps3>0pmSdFp%P@142f@7M<|r?U9IKe4ys)M@ z%H7sLyYXYrCx4$6Im+K+MULj}G~K*?<~UT3^3|Tmo~XyEdYq@n#d=($$9wenlzbV- zT+e>v-l*}e6cCvSt0!}Pf3Vt?PE#}DL= zH7`G=$Le+b-B6FC>-oD#k2~Z6Fz0_lk3U`F@4xieEZyHZdYmHTk1xs>q0RNbqeri=zbopoUw?mJp~ssC`ui?DemvOU-{~>!GJmJ* zaoli!7whqX%l-Yd9#4<-_XRz+%Jp|wJzkgR?-hDHAkfY2eOHfhfzrWXGts;MC>ak#|zo+Z*p<;hOqsKGT{cX?ik8Ni8$L@NZKgZuU>ha~d z{ywC~_<8=WqQ^lC{GF@E4U7D}O^=^1@%ImUth3DD*?OF~+}|_xxND`qpVi~pRsIgF z_K$7X`p2GnT)58PtM&NmdVjyK$HWc(uBOK!8~vT9$Bmo(yuRrAPBYF%y;_r*}c-dqA9;3%i zPx$*jJ%06+zkk+agFXIkuE)Z?{=P|2R;O%YXOxt$IB8hrd75W2N){uC2$B z|M+`?9`BZC73T4LSdYh}{Qa9AGvu#2%*!v;V~OkU1$x{g-wt42{)!&uTP`9yL66+10;`6dFhuh!#M`ECNUAJO9p`L+VH zf7fG{e1C!2?esV!&EJdkxVM(SU(;hP`TiYq{!Bf#Fh@tepFsBjbBvR}r_|#J?PGNp z=y9_4S-R)yae?-gy4UD&z4p8H_^=-L>hU!_exS!=dOW4azx5a=f9-E>f2tnqn4{eO z;d;!|<4yYVTlBbDkN4>D0X^>0qi3EU$@RqRF-4E5daR+xT6%1#M|oP{-+y}SsmB3& z9HPf7^e7+ZBIlp2$7}VtSda2N|)8i&RZqegzJ?_=x0X@E|M|pP0 z#+akLks;l3h`c;nk5kO^L3#Ttn4KhlQLo*~D4spJByY4FOQ!k90#3;nB}%Le^Hl&V zV{~z`l_6iZ$S^VEfBVW@~8dantf9%b9Wp_07mDDVa85^z;(B+W!x~ znS``7h# zk?Y$nufSZNvBmYt)3SeEpWV>5Zs$tMy=+#w({j?on}txFJ87tcKPf3w5NPOqcn4U=CfL^Z=;;%GIG+|EZ1kw z$1h%Xi-hvmce32|CCJOTz6azqmoeAzuw37A^FsZ_%XY{ve|_iW`pn~GZlC&^DIbyevqyS}ir^5?4{x9`XQ=6rmsM5}QbMVay~3fV2QTC~b)(yB>oIh~c2 zUGBdvS~N>bYu!4lWeYi9TH2_%d0qQ-^S{@|zhYZHi|6ezrTV*Ej4Sy}y0%}?xqrgHWEr!24c>7&>5KNX5QaL&s9;#_Fm&fYtF z9XNL~YiCdS@BI7BWslz1AdWYr=KXkMlKN@K5%Yp)_eL^HZACVI<3o#a?QmB^V7`nv4U%R zn&YnpMg7dN$LW-m7tfvSD8H>2&m9e=jA~l2(LR58zTCcjBRZa~>GeNTr=Q$Ab3?T| zojp2bbf3bWMZI1=SAEUPa_i*xQTaVZe(y6!`%<~JA^DvqzpdZj&F?*~*SMbJBae;T zl5X?UI-X7$Gq&dd^R|sL=aIK8G-lM`f-9`^@4qLvC+@bMy@IlHOLx~^y=7ljx^sH1 zkUdg%$FoC6<(y3k$mPOuo4y>?uV-aUKu>e;Kuw|VAq z8d$62*#n)k`pA7%)7)1)E>@a(X^z|ltS5%lT>M9&6k) zt>2Nn|GeLBFTLM-o$feX?z8LU{)-RQG51@A-i>?KEPub5`>gc7v)k^M`%QkQ$#1#e zZU|GX@Jg6ALTHEG+Vu?-t1e>&>*-{*Ifuf;B&f3%U+wnJMhIc4(u z4X*D!@3*n9r=Crq7gcD!xk!6#hHJ|X9KJjXiGD6N^b z%xZ{Y90 zEj`Bpxwd;Id@L{j>AM=eFYa}5&oq6BBLd88`cPhW^t-O{Yvg^>;sxeD-`Ve~g^Mqm z{`Tw@x4yXVl_r&&4EcG@4eb+qOx^y*GX|cb7H|zp`RoEqg}$&L^y!f4Zvo zM{zm55A4WE+;ODepeVVf&l~MbdwKGiAD=rkf53!37gCOfb6W3w_{mLo=On&&?~JeB z=p`S2{ErdQc7c2xivLXBd)GJb#moJQvSSv@2eT;K+amAJqoSNYE1HA5u%^7z_G-!L zzLn+cQ1Z=5&N_Kg5qL$eBdULuQIX_MuPV!PTFQr+D9`<@ihOX0cFf;iL`Azraz%j; zJy%Xf_fAZ4W$ZH_cib~_b+-Gle2j^b zC>L@ct{~@eUyvK>xQFCpNsJqiTkE<@YX_d|JhP|^KB&Qr-fAkQXK z-M{4ysO)-jx{A9`KHgV#x6A2j?%i@PR(G$vSiZpQ)|K0Eu^THT&CQe7Skpaxk!96# zf0k>j?Z(S3spF27Pmk)lt7^+P-McO2I`iF1b>wFd+`e)fUUR>b+x)s)QJ(6*;ZBf` zmT$WA6wp(p)mt4yR+dC+4{B5>3LSDAf_WqWe zcf0MS%3F2D_L61&W_$HS&{^BtDzE)_+Y8GD&e`5xxnaYjykdDpd!xLE`;O$y2ry0dJdJ=MMr%+?@<~%jJIgG2rc!JL#u@cZ=K`KL@-kmUTcc)zEXO352?#Ry_ubo`= z7mim;9*(1qcR+67myS1D?xn9BZ>rpugRU14TkpEwdvfvjT(6b9+C#2qz9s*#>zSuy z@4Ma}xhFnwy*DKuaXnk^vkzVGHM#gluD3;Q?(U%1LmWLF^q!PgyC>*9EwAC3ptoAC zdP|ZQ5Jh(-dB^0&-<{+QmYZ}>k{2Tn$JQjThFs^iByW%0OZO&uQ)Mkn@oLGVc|(eK zP%a*-?-iRr4)whW^43mC_2$TJnVRZdDz|J}s+T9Pwm8-MTh3XM>fI}M*7Q_wth|{s zQoTCz8fKh+NucwMTu zT`oQ^)te}HRm54qT?oSti0NsP2LA`Wt}#8JLPWevdP<%W?5Y~c}a4I zblc>~PkmV3H+ci)o*1y-J0dR|xZmp{hfycI=jBg8-U)A}+}zP8ynHb+=7e{nybWVd zc(dgu<)84n$lEaPgm+$E-}n=;@5sxhgl#MKLwRGSniI9;veV3o1@f>Ln-k6CJSFCY zc^5U^oLD7y;|z16jlAvi&%H?%!$9{l~yn(mdJx#(VRFVugl!(*k1Aw$d{0; z*gkUOqs)os@+!<v#aIq71`{Oh<*ef`%L{2#}38tC+Y8q;a0 z)Bj;i=MtU%&tf`_boxJv=`_~q|0Jf9uG9ZPOeaI9|8tm5rcVFIFr6%&`cs%rwr>3) zOs9!%{TWQBsc!udOsAP{{RvE`xo-UdOs9oz{rO9$rEdN4OQ)4?{pm}mwQl|4OQ(%) z{n<)OQ)M|dHfTjojQU3^7tpM5Fx9vQV}72^r9-HuTB-xPp1m$uTzB#(5XTO>Qo_vbgGcSI#tLJohoFgPJ~>h8zIAV zBV@R4gpAOQkjr%=IWVTKfGDjyuuF;Kr$P(QMS*jZ$*Xu^eGTjKdK{rB{>qf{5-3VE! z8zDF9M#w7N2wANgA!~H|LJ9-x^U6t15;7&5lz-)0AmoBL8bYSV3?UcB3?UcA3?UcC3?b8EhLGtoL&zmD zL&&8uL&#+@3AsErAy>pEXM6LLpvLT1OV3Yk=zoqzm0+>u|k$tG8Y z{G5mE&T^8Igxs6W&aWgb5OQA}4I%f(3?UE13?UE33?UE23?Xx3hLDG2hLA^MhLA^N zhLFc%67qO#LY|0C$dj=Nc`7y`Psb+Ynb?Fp8=H{lViWRwY(id$O~{L}33(|tAuq=! zAu?d=xW;d>k``d=fK+d>S)^d=@i=d>%7|d=WE* zd>NCFuVNGOb!D*o4fFO~{|I3Hd8FA%Djv=lchC3Ag{;BumhV*xS)<)G--8NSlielXs}{0myDi@<w42b7LViiR3++?LFKG{6Q@+H zDjJ;MwU8}VEGJ$`(Ne`M-2=2h(bCR`qGjw*)Xxq@%i5u6IXe_BZ-=7(b|_lG4n+g( zP&Ck{Xhngdl>~}b7ARUpplFal(W(MPs|geh7AP7bP_(*0(Ha6pYYG$%6)0LuplEG@ zqG19>>j)IBD^RqaK+*aFMZ*P(HV~?cmME4^$$?bXO?N6S8H#Sm?^Ve*ES8h6q-aDj zyEcclK+&eohoa5wP_(%ning#r(Ux{7+R6?^Tic;%8#@$jYloukY>KuQDB3}wXh(sf zkpe|K2^8%tP_&Cc(XIkTy9pHSE>JW|plGx}(H;UtdkPfoB~Y}tK+!$|MPmet_7y1F zPoQXjfuaM1s-lgHrRQ=Wl_~kXbJ-@LXmb8JC_AuNPQH?&LyOtB`F)QI6dmS#C_3B@ zMMv17=tw&hjkQD3QFbUg+73m>*r8~g9g2>%DLPJ|=y-vm@d8CB2o#+tP&7fH=p=!n zlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugeoip~)zI#-}*qCnAk0!8Nw6ipJUiViN8 zI_6)@DlPfFz1bn5XxDTtdUCOxd?iH}7PEo*;|~iIUF3Wyy4Vgy)9g?*-3~>U*rDiB zI}}}JhoZ~vP;`YIimtRNx=NsEhCtEP0!7yd6kRJ&G*h7HI)S3=1&VGED7sOg=q7=p zn+1w)5h%JW2C~C4pQL`P2I@qD8Vuzv@o1%^aMV$nSItvuF3KX>o6m=0O>MBswO`xc|Kv55Y zqMiapy#$JS3luFRP}E1DXkme(MFff#6)5T}P_&pp(c%I{O9)j(`710godc;1%pU;H z>T0UD^k?PIFUXdxDJNe^QNNmOqa{Ppvd)L157 zqLu7Ww6aanDgs4=1d3J_C|XURXs|%h5P_oA1&Y=XC|XmXXsAHZS^`CD3lt3#C|XCL zXkCG#^#qF67bqGoP_%(S(S`y=8wnI`EL0UOoxg%w4y5u%{+yL;nNT!2J#w*0O*#2W ziZ-vw&RaSZZQ*<<+R_e1TiKy#YdaKeV~3(`?NF3Iv2$AfUTce?XnQ*p?O=zZ9c_w6 z3KZ=mP_(l^(Jlf-y9yNTCQ!7yK+!0HqR|3Hdk7TmDNwYRK+)a;Mf(U8jS(o?SDibeSEBF1JI` z6?Q1P(hfye*`a8L9g42DDY{0W=vslInF2-E2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xN zMYjnQ%@QcOU7+X=fuh+0MRy7m-6c?Tw?NT70!8-<6x}CO661S*BfB^h zr5D%8?yo5)UrEuNnrzexq3B`fL(wC4D04h9fW%v9Mj_i|A^nMz3rE>C>6typ9->(#k8k`SBjdmz%vO`g` z9f~^Gp{Qbqq82+8b+kiKCp#2%wkc{AC~6ZZ>LO6oRiLPwKv8#rq8Ia;ng$0Th5hz+zps24v(P9EciwhJjAyBlWK+#eHMN11+MfIgp=aq9s z?bD6>cBSeq{l=PnEK@2cUrEvOrEH}^p{T#}p=bp=6b-OL(Lg&Ct!Rg$mF!TovK@+6 zu|v@yI~1*IQ?!~u(O`k1Ap%9K3lyy(P_(8%(NKY+wFHXR7AP7fP_&Lf(YgXf>j@OC zFHkgGplAbuq74O#HWDb>SfFSVfua!tMVks$Maz~-JLEtrgVU#<+=`P5_OXcJ%DLSf@Jv<~79qoK5I>rt~ zv zav+so)6=ELhN2Nk(Z!{5@|6@_TFT06hN8=y4@H;Tq38-b6kTbDqO0ssG{X)>SKFcJ z8aotSYlotlHbvJ76kRV+bb~PqS*pP zcM25UB~Wy?K+!z{MfVC6-6v3Vzd+Fg0!0rBRYlWFrG7b(O1pHg<0YYJi~Ld8?4eRQ z`AUi&EoGam6^b5nJ`_D}hoUF!Q1ql7ik`AV(bIM)dd3b#&)T8rIXe_RZ&UPwK+%f= zMK1{yy)01lia^n;0!6P06umA`^oBsuT!ErD1&ZDhD0*9<=pBKgcLj>x6DXP|Q1re) z(FX!W9|{zGBvACRP*wDBsdPvVq;gSus`VqGXhOQ#|4FHwd?iI+l(I>~LeZDbhoZ0S zQ1rDOioUT!(YJOe`pynT-`k<+2Rjt~XosSoY>IvsDEdX9=vRTF-vo+&7byBeplH58 z(VqfEe+d-*El~82K+(SfMgIvD6>8&F97RQeq8fpsl0Z?dKv5=8R3}hW7AUG0s){}< zmF~`gRIX0XFZw(bjZKe$w5u&AUrA9@ZT8l>p{UvUP}IQ=MHM>~wb-GkqaBJm*`cVj z9g14*P}F9JqAoT?T?LA|2^4h~DC!|l)Kj3Smq1Z(fue;3iuwo?Ei6#9h(OVz0!4iV ziWUW`egZ|y3ROi7wWWV^AeBqHBqE+lrG{_D`tJJ6b%z7T1TL0U4f$Y1d7%dC>kzMw1Gg;h5|(!2^4KCP_&6a z(FlQ}O$CZJ6DZnTplA!Bs;GZ$X`LKM<*oF*>lH%L=4otMTTZ@`qHSxlJvIzQ+c_VK zwzosk4t6No(GEo;?NGFn9g23gL(wjFDB9HyMZ4J)?JiI>N}y=8K+zroMSBVq?IlpO zw?NT80!3p4iuM&K+E1Wpe}SR{1d0w6C^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~jufhj zwyrImkproWOjoG42}PGAMPqBr$yZV|t~R@2<4|<0^P%WCI}{ynhobRzC_2FoMJL*! zXo4MzPO?MM$#y6@#ir;~fuhp{icS|OIzyo7Oo5`a1d7fUC^|===v;xKi2_CE2^5_# zP&7%PXtF@j6oH}(1d65#6kRA#bdf;O#R5gs1d65$RYgbFmR`z%ROaV1J0=tjOLswD zQd>^GlAE2n47K2lpwzLKIRYO_@~4@FNp zABvu`L($WAD0;>YMbFxy=s7zSJ#UAi7wk~<@=m$F# z{b+}xpX^ZdvmJ_lu|v_XHbuV)6#Xtx^oKyve1W1r1&aO>DEeEV=pTWie+7#E6DZ2R zEqhx27hGGUs3=fWBT!TlD5@1G$^?q)1d7T6MfCzj?F5S23lud7RYhOcmafc!R7Rz{ ztG^0Gx1?M8jafPQN{T93_UP83sKxnE)X@$_o$OH5*$zdmb|`AILs1ty6m_*jQ8zmj zb+;+%AyCv)ps1HXQE!2wg#?QF2oxqLs3& z-FBg9W#>cDDt0IuWQU?v?NGFu9f}6qp=gL5idMHn(HeFrTGOUzs6f$L0!3>J6b%z7 zT1TL0U4f$Y1d7%dC>kzMw1Gg;h5|(!2^4KCP_&6a(FlQ}O$CZJ6DZnTplAz$qAdlA zwh}1XTBs@-n3a~xfmB-aZ^_SA3`K{eJCC->%E?z!v_qC{x zI~46=hoW8WP_&yJigvd{(I`6LuYK+%x`MPmhujuI$3TBs`8E-M|D1F7^+ z&%53}6phGV+A}*QD<@w`(eYU}Wn?HC?|dja!45?y+M#HI9g0q}L($20C_2RsMW@=K z=rlVNoo-WfhCtDo0!3#D6rC+lbdEsLxdKHK1&YoSC^}!DXp%tDWPze70!0@H6ipQ< zx=^6#B7vfd1&XE#6ipW>xca)Hi4p9 z0!6nA6x|_EG+UtPPJyDk1d8q!D7r_W=w5-M`vi*a7bto_py)w?qK5>E<_Hu$EKu}_ zK+&TDMUM$pMOS8}!Y;X@?Gl`;LQ!*i1my9ooO~rkPiNV}yM>}>oDW6M+M(zUezu2MZS34B_W{0BR z?NIcGP0@UTqCW+S{t_tqTcGG4fuer}ivANQD%8czc8ZDuMKuCNC4r(^fuc;Hs7|1$ zEKpQ0P}EMKsJ%c@gFsQEKv9!GQL|80^i5VeD+f{;m=t{*ik?c>t~=C~ldq(xQ(bn` z9-*kS^P#BK4n=KtDC%N|qONu*>Sl+c?sh2ZVTYogb|~s)Q`B3aXd!{3J_1Dx3luFP zP_(E(QD1?g#RQ5L7bsdnplC^fqNN0imKG>lMxdylK+&=SMau~kEiX{iU!Z6OfuaEd zMFWMZqL#YSD>;zLz&<&gj&;>r`dg&0Xe-v0ldq&`P+j)(UZH4J=R?tIb|@NbhoT{N zC|cbPMQhlhXiYm54YfnjT6QQ}+ooukK+!q^Me7O_ttU{lzCh7%fuaoriZ&D|+DM>i zV}YVg1d2uo6m2R{w3$HB<^n}q2o!B8P_&gm(bfV*+XxhGD^RqZP*t>YU8(EdxuO@+ z7qL}B(O2m%$nERO$yZXeQ(d;|m{7E{^Py-LI~46|hoar=P_(-pibmO?XtW)Q_OL_I zo^~kO%cf{=fuel`ipB^O?JH2UpFq+60!0T16dfo~bdW&N!2(5x2oxPEP;{6;(cuC` zM+g)hDNr<4py()pqN4?hju9vtCs1^(P*t>JU1{eWNaf!2INHciv{`z}+HrN|+MW@-J=yW?2oneQfGwo1xmQB&w0!8Nt6rC$j zG*O`FJb|L~1&SsK6ipT=nj%nifk4qzfuaiqiY^i;x>%rSnn2NXfuc(UiY^r>x=f(x za)F{N1d6T{s*1+fm1g8XDj%h1@1GEg#-&e8SJjo1ucYYOy6o`-LeWg;L(z41D7xMb zMK{=?=tesf-DHQNo9$3^iyew?wL{TuHbt`pif$JuxK+%T+MIQ+ieJoJ) zi9pe(0!5z*6n!pG^o2mtmjXp!2^4)TQ1p#ZRrE|6*r8~?9g6<6L(yM0MSlwv{UcEH zuRzg%0!4*#+-#?)C{R=*P*f5q%AXQZeZ-!kOrWSvpr|ZRR4-7}PN1m0Kv9E0QKLXn zlR#0kKv4&QqKZIKi%?bceO>8@97yHv^f=lNp=e(E7RQd|a`KfFwUx7}hlipr&WEC| zb|~s*hobIwDC%K{qMmjr>Sc$b-gYQj$PPt)Y>E~ZC|X3IXiP$El{+KKv6$|qGbh&mJ=viUZAMIK+y^UMFRwi1_~6dC{VPLK+(!VRZ-`1 z>HZu@Wn8+8sI^?ZrQejkqODRcCtpd?;Bxlfk)dda^Py;UI~1*9hoUv@P&CvIMQhoi zXl*+b4YNbhI(8^p*QRJafui*ViiQgmZ6Hvzp+M0_0!14O6m23M9*`h~>qTQSiMZ4RfXp|j_M%$q%|EaarPxPT^PdgOtWrw1@?NGFj9g4=- z6zwZew4XrH{sKh@2oxPCP;`($(ZK>mhX@oMDo}KoK+)j>MMnq}9Vt*WR-ou8fuf@Y zijEN|8YfV6tU%Fm0!7CQ6pa_EigqrShUY*km#4?kb_qq-_Q}Ty<#O_s6rEho_8Aw7 zPH{dIooa`o)9g@mx*dwnutU+Ab|^Z_4n=3%q39et6rF2RG*O`FJb|L~1&SsK6ipT= znj%nifk4qzfuaiqiY^i;x>%rSnn2NXfuc(UiY^r>x=f(xa)F{N1d6T{D7s3ZXof)1 z)k0O#gmUSe97tvLbQjS{p{Q%R@A{f@Ir&P8t}kb|92bgia6S~>XosSk>`-*G9g1$T zL(#2vD7wuKMYHTsbh{mj?yxDEEl_l)K+#; z6wOQb7d=}pCtpd?i{+c63lx1IQ1qcd(MJMB9}5(HB2e_HK+$IcMV|{4eIZcv zr9jbF0!3d76n!I5^sPYAcLGJ<3sptWmrLDG$Q51MDTnhyC>ouf%Kt;ToO~rkzm&7V z6GG9i&WEDk>`?T(9g6<2L(zOY6#Z$3qQC4=^tT;~{;@;Rzcxkx2^1CTlt~rp(Fk^)6b2^1|YP_&FdQ9psAWd(|s z6DV3#uTFVYaYulk{m>r7Nu|v_ib|_lU4n^zR zp=h{G(FOuV8wwO{Bv7=mK+z@wMI!`?HWet^OrU6Ufub!0inbIe+Df2kYk{I|1d6s5 zDB4b-XnTR89R!MY6et=gP_&ak(au6u(UAJmH#v|>ZMvnudMFy#nvY%T%gI+#G^##p zIwKT~c0LsCVTYnU?NGFr9g6n0L(x8VC>mpjqJ8a9w4WV{_O~fIK%nSAfue&1iVhYi zIz*u8P=TVu1d0w9C^|x*=tzO0u>wU$2^1YIP;`ty(KvykV+D$i6DT@fplG~6(Fp=Y zCkhlz5UPrHt1k`6fmCL8&*AJIih3ndC)JmeucYX-`fSUyLec5YhoUp=P;{mpiq5h_ z(b;w=I>!!0=h~rYq8*CPvqRDOHbs*JiY5ybO%W)%K%i)2{cDG!|LjmyXcxEJLs8MDs79cuBv4c`p1&ZngirNVj zwHGLA5GZOCC~6WYY8EK!AW&2hC~6TX>L^guNua2+KvAneQJX+f7on=?*ZR_iIgrXx zeR4Rzg`$1Z!y#SUm6NZesAs!u-zlM}m-C^hw;hTWvO`fHI}|N!hoVL7P_(EWiu&52 zXfZn!EpAh^gh0`f0!2#+6fG@Kw2VMeKY^lU1&WpvC|X{isJ}qb3Ias~1d0X<6s;&w zw30y4$^u2J2owzxC|XsZXf=VN!2(4?gsP(M?Mf4KAeFZCa{E2nRd4BU-;$5j+m(~A zq-d>n*=)N4cJv$VwZ-=7cb|~7w4n-TqVb^=A)3l!}jP_&~!(MW-!odk+@ z7AV?9plDZtqTPh5qBYx<-pGMeo=;!IhK8aY^54sLZ&yyflA=A^Wxrn(iuQ6o6zy$? zqJ8X8G{z1^``V#sKRXodZ-=4->`-)|9f}UJDLPo7=n#RTLj{Ts6DT@dpy&vJq9X;0 z#tIZ2B~Wy%~wnr$sH+@ArwOu*+N{Y^Gm#scM6rJUKC_38?Md#R|=v+G#O|(PNd3Go| z-ws8S>`*k>4n$Xq2^7r`D7spp=o*2dYXypC3KU%@P;|XO(G5aX(dq3!xoWIwKU7(qsBJ zwks!JNztwCvI&=lqT8GgMYHTsbh{mj?yy7AY&#U)X@{b_>`-*K9g6O;L(#o9MfV95 z-7iq|fI!iM0!0rA6wMJRdRU<75rLvd1&SUMD0*C==m~+MCk2Y05-56Fpy(NaqGtt) zo)ai~UZCg&fua`$ie3_`if(RKnwbNsbWYE^z9kfmOp0D^S5Cf?qSxDHPhTF2-f%t? z&9y_(n|3IA%ML|v+o9+kI~2WZhoblFP&CgDMeo}beIQWup+M0`0!1GS6n!F4^r=A6 zX97i^3lx1JQ1qoh(N_XRUkem{BT)3MK+$&sMc)e){UA{Eqd?J50!2Ry6#XJl^s7)+ z^lH1(cR7&CkLf{=*Fw=3=}OXX?aIklQuJrLtix5I=r89((cg9``o|7M|JtGGKRXl^ z+Q%*TP*k)-QH>pnN_Hr!wJFL3is}T4$^u380!8fvirNblH3$?n3KTU76g3MJbr2}3 z2o$vl6m=9R>LgIqS)iy@pr}otsEa^RSAn8#0!7`0s-i#Il~&AwRA!_*8s~?iCDY5$ z^k`pBzLKJa+Gkr|9g6xmABq;XL(w93C|cAGMSbm1w3r==7Pmvu5_TwB(hfyS*%U1; zP_&FdQ9psAWd(|s6DV3)T%V27du z?ND@(9f}UNL(w62C_2=p=rDnz!v%_t5GXoQplGZ>(NO|LM++1kBTzI>py*hEqT>XL zju$8zFHm%XK+%Z;MH2*yP7)|OS)k|?fud6dicS+KI$fwL+N*u3?)qHO8R-#_y+hIZ z>3cxVXkSjglA?3kXG`1|iq3UD6iu{4(Rp?#I^PaOlk8A5*$zch>`-)p9g3#fq3A-J zqKgEIE*2=7CQvk8py(2TqDuveE)yuaT%hO*fubt~imnnUnjuhhwLsA|0!7yf6wMSU zx=x_zdV!)F1d47HD7s0Y=w_j+=&bgojdLKCUg>$)XNRK2(v_rJ+Lx2Br0Dkc+5R_& zqC1=qMYHWtbf+DP?y^JC-F7It#|}mJ+M(z^I~3h-hoT2;iXIdwdPtyXjzH1F0!5Dq z6g?_X^q4@=;{rub2oyajQ1p~Q(bED&&j=JfD^T>DK+*F8MK1^xy(m!hl0ebR0!6O~ z6ul}`72Vdpbbbz`GA`Y?pB0KuONw4=UrxS~qBq-Tx8E9y-f}(^y={l0ckEE~t{sZr zvqRB5I~2WdhoTScQ1qc4iaxR_`dFao6M>>n1&TfsDEeHW=nH|OF9nLe5-9pwpy(Tc zqHhI?z7r_=UZCg)fubJ;ihdF(`dOgp7lEQ*1&V$XDEeKX=ntW)=#BQJH*+AB$J4ic z%ne1$mGd#beL49`ivDSz&7T#D{&hYS{bz@wLPOkg4@E^g6xGqMyFgJ7fuf!QMZJWoqQBagdf%QaT5QoA&flTvvvlWC?}l>nl@u+~kgYj8 z6fNp}DC%p6qQ&e`w74CLmas$7l6ELs$__o;U4-xZ36J0FTRutU*?b|~7& z4n-T=p=c936pgS$(WZ7N+RP3`o7)s^AyBlXK+#qLMOzCLZ6i>$tw7Os0!7;k6zw2T zw4*@LNP(iA1d4VRDB4A!Xjg%v-2{qu7bqGfP&8VgXb*v+Jq3#P5~_;UZ75xz1F2k* z9*tcu6#bMwG40(@PQH?&{Ti}o?+HcwJ0FS;utU*-b|^Z?4n+ssq394h6dh`ZqQmS^ zbhsUgj<6{@QlMz8K+#bGMMn!19V1XQPN3*mfuiFCijEg38ZS_Ef#>y2uVi7u%s|noZGkfuc(UiY^r> zx=f(xa)F{N1d6T{D7s3ZXof)1)dEG=2ozl_P&8AZ=sJO->jjE#5GcA)py(!nqMHSZ zZV@QDRiNlLp{nTIhSJJ8kjg{p3iZTLbVs^gG^?SUd?iJ9He}mA7>e$4J`~+;hoXDz zP;{>yite*R(fxKPdcY1v589#VAv+Y!u_=03py&~SqDKXa9up{fT%hO)fubh`ik=cE zdRn098G)i_1&W>%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+XLO~`AUl3X~-^_6N=t-J`}xYhoX6QD0<%xMIYFq=tDacePoBC zkL^(Oi5-eQwJG{cpy+dfqAvuBz7#0>N}%X#fue5&ioO*n`c9zedx4@K1d4tXDEdjD z=x2eVUj&MN6)5^mpy+pjqCW(R<_i@4DNyv6P*wC+L+OzmNM&-myZY@=G`x2{{%$BI zUrAA+G5h$DP*iM;Tk@f(#tua#I~3L0p(wLMQJo!%%62HKw?k1oI~29IDQXZXY7{7H z5-4gGDC!_kR1qj@5h&^?P}E7FsIx#(t3XkkKv5TgqOJl(-2{rd3l#MbDC#Lt)JveK zw?NTC0!4j`=6<9g3E-L(%d!Mg0YeRuCu}AW$?=plC&bqLl=SRu(8)MWASq zK+&oKMXL!E4HhUGB2cutK+zfkMQaKa4HYO_OQ2|NfudmoMe7I@tt(U&E!tQbkproW zNKYy1+gQD&zi4`BcD=@O@|6^A*q9yoWGLFm`B1d69f~%wL(vF36m4pUqRs43w7DIM zwy;CdmUbxG%BE;*fud~$inbLf+D@Qodx4@I1d4VPC>kkHw39&5&H_cd2o&uqP_&ys z(e468qXddZ3l!}kP_(B&(Ov>YdkYlpBTzI(s45!XSel#zsT`2*BHADnW$9-BzK!MN zD=9j#F`NB#C_2dbP;{^ziVm?u(V=!II?N75hufj(2s;!VX@{b*b|^Z^rs!yaqGJS# z#t9T1D^PTtK+*96MdJmEP7o+MQJ`poK+#D8MJEdsogz?lszA|c0!60_6rCYZbf!Sj zSpr383lyCrP;{FpdyW#9C?>jOg3IZ4sP#&YtN6isf-{(3ePO>sUHU0{cz zsdgy3&<;fx*`erSI}}Z`L(z0Q6kTG6qDyUxE)yuaT%hO*fubt~imnnUnjuhhwLsA| z0!7yf6wMSUx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*plFsr(d`07cL-HQ=Qo!6 zJeMolKRxeyQYhLhJv2MJv7CG*MfWsjYrPPP?sYyC-DiiQ`|VKlfE|h+v_sKDb|{)- zhoXn=Q1pl$iXOEodQ70`ae<;I1d5&%D0)hu=xKqXX9S9#6)1X6py+vlq89{;UKA*L zNucOufudIgie42cdQG6{b%CNc1d8Sg6ul`>^p;RnbXQ|(&m2f)SbCX|yF=0J_W5|b zv7CG*Me`c7Q(p>2?>irgKCna4hju9X$PPsx+o9+aI~09thoaByQ1rPSioUQZ`ck0i zD}kb~1&Y2ADEd~Q=sSU;?*)o}5GeXlpy(%oqMrqdei118RiNlMfui39ivAENnlDiF zr$EtP0!4od6#XMm^si7=^loG6#vDkceY)52y-;*br+oa^SWdo@qEb`#e13m+$F=(x zvf8Hqe@j2JLs6X_ipq8LF0nQ=q7qKv8djqJ;#C`Un&)EKszFK+&Q? zRZ+32^ivL`vTu5-bxl+CHrnBx^U=4doO~rkOEzVlUJpe}IUk>kmbOFDGIl8HXNRI? z?NGFw9g3E>Ls5S_6s=%~q5(EV0|km!6ewCrplD@*qE!Tn1_>0cDp0hVK+#}(c!8o5 z1d2`+D4HNpbdo^P$pS^E2o#+vP;{C=(dhz3X9yIXDNuBlK+)L(Mdt_3qKoWMbg>#Sq38;mqALZ8t`aDkAy9O+K+!b?6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_IK+$UgMXw7K zy&+IESD@%kfugqriry9|dPkt>U7@Pz-lo!KIgm;zz25bGq3D+MaL9X2<>V_V`miZG z_=8aNk@KPGV>=XmVuzwn?NIcY9g04;L(vy@DEiV4MPJ#W=xdvzZv=|I6)5^npy+#n zq8|i`eiSJBNucOwfudgoihdO+`c0tdcY&fm1d8Sh6#Xes^p`-<-vUMd2o(J*Q1qWb zQK30*m{U{~s*2ukDqWBRshpgi-uOW%`e)&M)HIiqucWB1IlJqlP*iq46xG|IsGS{( z+S{S1!45@@b|`AHLs7FGiaOY#sA5ypB2d&(ps15TQD=doR)L~6fub$~MO_7ox(O6@ z7bxl>P}EbPsFy%dZ-JtP1d93y6fG=Jw1_~_q5?&I1&S6EC|X>oDynTRy_*B6+>oA_ zmNi#z>F<*`a88I~4V|L(vL$C>mggqJefO zTG0+gE7=sSEKszHK+zz9qE!WoRud>1EKoE=plEf0qBR7H))XijDp0hRK+)O)MZ*M& z))6RLSDA;{J`Y8kJ0FU+utU+7b|~7)4n5~_+uG?(_yfmBNADMg!xqBYYaAO|;>ldq)c@aF9FFGJB0&WEBS?NBt< z4n;@Vq3CEk6dhxSqH%U8I@S(F$JwFic$=c}0!1eX6rCtgG(n)~B!Qxn1&U4)C^}W3 z=rn<%(*=so5GXoRpy(`tqO%2x&Jid&SDs46KWHD7r?V=vslInF2-E2^3u~P;`Sp(TxH{HwhHoEKqcdK+&xNMYjnQ z%@QcOU7+X=fuh+0MRy7m-6c?Tw?NT70!8-=na9QxdKIR3KYF1Q1rGy(K`Y~ z?+O&XCr~s`py+*}s_22{(rP)7%Dd@#*AIrG9ZLE5pt+oUB}Jb!XFL87iavEd6n$og zqR;J6^o1RYzO+NpS9U1++73nE*rDiKI~09qQ}n$+(GLPeKMEB6BvACTK+!J(MZXFZ z{U%WKyFk$&0!8x$ivAQR`b(hbZ-JtJ1d9F@DEd#JsL&y9wo_CTD5?=CDhU+T3ROiP zHJ8TcKq^zx^R7P*McbvPtYsa_$yZX;u0wXkPob#2^P#B04n>W2C~C4pQL`P2I@qD8 zVuzv@I}~-aLs2K2qRs+EtpY`D0!3W}inP4%ps1%nQ7?g_-U3An2^94a zC|X#cXc2*;MFoob3KT6SP_(!}(GmhhO9~V%B~%raJCvTtfmF^+cQn>_sNT|_mF|LE zxkbEw2na0x&lS(2^6g_P&8biXaj+w z4F!re5-8eOplB0;q7gz>QNIqQ#$R(qf2RjMmJLPgrfb)mb|@!bNzs-avSoh{MO!%^ zing{x(KdD{+SU$5+u5OLdpi{EV27d|?NBt*4n;fJ6zwcfw2MH|t^!572^8%vP&7)Q zXtY4l9s)&s3KZ=nP_(x|(LMr2V+4x!6)4(IplE-Aq5}kq4iqRlNTBFofuchMiVhX3 ziZ<_1+9C&1xh*|0ZHrL!bW(I!hjQ|j6pihW9XdZ09p!u|I@%6J$Jn80oE?gewL{Ty zb|^aD4n^bbP;`PFicYjCnjlbgl0ebP0!60?6rCzibecfX=>kP(2o#+uP;{0+(b)n; z=Li&?D^N61py)h-qVolcCJ7Wx7ATq`P;`Mn(Nuw=3x%qpBRZ5W%z;#{OJBr}3`L{U zoktgSC?{V@(Ip+Sd;SVVmpUJcF0(_?<#s5#!VX1O+M(zwI~2{ZL($cCD7wZDMc3LC z%@ioQPN3*|fub7(if$Arx=EnuW`Uwx1d47ID7sCcXqG_H?E*!22o%j0D7sUi=q`bx zy9J8w5h%J>py)n=Hx{S%5F zbv_h5W{0B3?NIcD9g3c`L(x-qD0L($^tO47$2%E?z!^m&JD-9mZ;`SY&7a6S}$X@{b(>`?Tz z9g4oOL(#W(DEiJ0Mc><@=m$F#{b*D4lR(kW0!6N z=r4hyzXgi^5h(gspy)q=qWq^xP0K$>wMB}G0!1|fMJ0ivT7jZWpr}rus4P?!ecGWk zCI?b^G5y@w&q7fpJ*ZY+DJNe^QDY@LvnCWZIUkCe?NHRg4n-9^6t&o)sG}Wb|@NThoV*OP_&vIiU!*h4G}0>U7%V_V+NP3qDTktMoexFZ*`a8A zI~46;hoT+rP&CpGMLXG{XlFYV?P7rN{C_2^-MaS8p=y*F6jkiP533ezt(GEou z>`-))9g0r2DLO@<=v0BC(*%l67brSIpy*72qO$~w&K4*-N1*6jfue~5Mdt|=oi9){ zNuX%5K+zO|q6-9yrV12YC{T2fK+(klMbm_;qN6IM6LTPy+xp~ijt)g{q&ttMSIWs( zQgnGGyQ(1+UEzEvy3!6sSJ|Oxh8>EownNc1b||{m4n;HVP;{LgimtaQx@14njXf#EELU1-w^U}rJQ^vMUPjqFPlQq6V8XCC+$%5 zlpTtmwnNb~b|`w*4n@z|q3C%#6un@Fq8Dw7UJ@vJS)k|@fudIhie3{adR?IC4S}M$ z0!42M6ul)-^tM3JI|4=T3KYF3P&7}V=zW2r4+M%n6e#*gpy*?PqE7^hJ{78p9<7v` zn{!34r@M$A3q@z9M`J&$l#{Qd=&MS$d?gfp?R+Tu#tuc_+M(z>I~09yhoT?sQ1qi6 zihi;~(a&}$`o*T`SAnA61d4taDEdR7Xud$vp8`dH2^9S;Q1p*L(Z2#k{|OWoTHTHLiRy!26*`cV59g4czp{ScpQFno&9s)%@ z1&VqJ6!jJ;T1cR%k3iAF0!51m6fG)H)K{QrF@d7R1&WpsC|XjWXeoiBr3H$X5h&^> zP_(Q-(Q*Ps%L`RSO)aI1b0C##vm8!yOZAriM(JM1{w?L?D=AvBCA+V4C|b$+P_(ig zidL~h(I7h%t!js&)$C9-*bYTQ>`=729g5blDOyvYXsAHZS^`CD3lt3#C|XCLXkCG# z^#qF67bqGoP_%(S(S`y=8wnI`EKszGK+y<+qD=*gHWMh?T%c$Rfub!1inbD}iUzcl zKFEPoMx`6~14B_$`tr7QOF8*Uinedbid{m{4$g<79qmvw(hfyC*`a7>I~46=hoW8W zP_&yJigvd{(I}gu(E>$#2o&upP_&mo(cS_@`v??`5h&VMplCmVqWuMm4iG3hP@w1_ zfue&2iVhJdI#i(OFoB}O1&WRkC^}N0XskfdQ9@PGwk@T_b0C$w(zWaDLeY$c^Ko=b zIr&P8j%&%*?-q)VcRm!2w?okhb|^a04n-5}P;`Lua zK+%~3MP~^Voh?vwjzH150!0%Aip~=#I$xk@l0ea9fubn_MHdJZO%*7*P@w1{fuf5A zilzw^O&2J-M4;$Wp{i(HOKHCxNagqR`bEcvqHof;tficMB}G@YWM}sXMKhcaMOWLQ z=o&i|U2BJ;nRY0;&JIP_+o9+NI~3h$hoYNoif$Gtx<#PqR)M111d3(}6x}XRbcaCE zY=NRX1&ZzxD7ssq=pKQhdj*Q_6DYc0py&aCq6Y;BT)3PK+z)tMUM(qMOU^p-%;+X6-J2o$|5Q1qTa(L8~o z_XUbR5GeXkpy(rkqK^fNJ`pJTRG{cHfuhd^ioOu4ik@gG{gDHy?ARlR^JFMGB7Ilm zmo4SwD=GT6CF|BF6n*D>DEi(GML*b~=tnyg{bYxtpY2feiyex7wL{Twb}0JYrsxlW zqWJ0!57iMNL9g(bp}dHF6-8t6Oq7-?(0s9u8^lSWdo@qK+N2T^0#NotzIv zo$XN6YKNjWI}~-XLs3^d6m_#hQFl8O^{_)xPn)7%0!6(AiWU+m>LXCJut3ow0!51o z6!jG-T1=p5ae<;G1d5gvC|XLOXla3>Wdw@)2^1|WP_&#t(eeUC{RN6v5GWcTR25Y^ zmQKonRCY@@%UU{CZ|Pr} z1d8?+DB4G$XpBJ7z5+%22^8%wP;`Jm(SZU*2MH7%EKqcaK+&NBMTZF#9WGFGgh0`e z0!3p5ijEQ}I$EIU7=fa3LRHZY9ZQuZaz#(1=Uwj@ik?c})p%^ja`KfFozO8`VX07b zqVu6>f*p!ZvP03yb|^Z<4n?Qhq3AR_6rFB|qBHDJbf!(wSpr383lyCrP;{<9(L{lw z^8|{{7buz}P&8SfXo^751p-A=1&S^dD7r|X=wgAQX#z#l1&S^aD7sXj=rVz#%LR(A z5UPrf?^xO<2U3}l&un}sS~!uqvST^-}yU@C6{&KXntq13i zlGL|O%D)gcw$9G4R8?B%=FbG^+}b05>TTE7-SW54v-R5i36yMoSh7gIdp9x=I=5e;FtoMT@`b`Wt)o^b6o$86 zH?UCHxb^#$3Wd#DR~l3(Y}IS5~raKf06I-W@EEFcUzO!?oaAE7hyA=x4TlX4OC|urp(;kJwjMks`Dimh6t~#br zxUu#4{R)L!TOU85P`IPD;ow5y?$*r@Efnr=oqBkoFsJpsBMXJcS{FUKP3+qw^aFwW7u(WLbX~F7mVPAXpkiD4nTkV-ZRv;N4K21^GAI9l6x-5|r5avrOFvg= z<6>L-!7!T@+tN?=*s9o;el){&#kTa?`Xh^N>BZ4^Ew-gsw;o+=OD|8ncd;$KzU+R* zw)6s_2Nm1WD?A=nY)dcEH@4W8USn-su`Rtw*7#yudX=M-if!p-YECP*rPmobtJs!a zC}Lur`VRB_4HV=Ej?}JsbX7t-obOlw)DX9OU1VI z$lq(lw)D`=o5i+t-}}48wshy|2gSB@@7E{AwsiN!7sa-8`}3P(Te<=9L$NJg1N^1f zmcE4lQEW?}ga0lT+ON=(|HGP5{U_Jug#2GqabQEIa{fWh|Mx-u;B|3&xBkUK*TMO} zmEyn^m&kvovHF{Zu2b@VImLk+r8YWmxz$3~G5HmU;=nypyEfm`QX7!}`zsDSCbeR* zP{{vE3S9@~Ka;*VaB6BB=54+Fziz+u$lFTI=jOkEbiT*r|8?J{Id3a3Xoc=OrLjtk z*V9`a)STPR|8Jx6KSgoX_?^by`B*K+Uim-x;@}tuq%kDMCg~!q9^>sr^07vY+Wd-7 zam^SH0v2m@D3_u4UGvk3V>H&*J7;iT>AlpoJT~RF8}eUmQP*<*-4kBT-%NgHztKzeEA+S{{T1dH?b0~Y*rhOY zxdmrFnf(5($1gZ@>ePR3$bXgI&;GA3S?Dn&|AQ``pLxY)n=|YB3CAw@D)=-*xxp<8S4p`(FDw{SmXqIZqDg zy5P;szhK_vbaCriuD@jd`C|(`e#;LH&EL+5>Y=Q0?|BbzvEcIl_`=Qes(&q~uhBew z!I@bzA2{`>LXWl_WV*a3Iwf>GQ@eIP=?!Pu!WmpT7B- z^nUJeX6D=x>HTDlkIh`GIX{y%zSVxM1s}1-$=~g~QK83rapH3)_SyKqP76*v`0Du0 z7QB}y-g)`^I`G0jarMljo@?WI?>Pq?eA^%61{;ON8)V}xqIr;QoU2UnZP;4nK z*4(L~)ZC+a>n<(DN|!>Rrf;F4VU0W$3Z=F}sd=@A!40c6Y|ttHbR55v?%Z6dkV;)` zvDCaqLqq=C)&E;DkL4xvQ$6#qpY;oVkrfK<7W^Xr$I(9CU{-yD4IT1#mEKNcr(#3H z|GtH$rb4OS`)z1wYG`a2l)t^^F8}ZU)gk|X{hv!$i5YLZCEjE{(}n67Z*sx!{_mUY z6mK&AU!C(q+5cXS)~5VVncj2Tf?wo+k}k^?*X-uKF41j+PA$cbbwj&OUAtR)Ctb7u zbBSuY+_iT8*V*lVhlpOjoTz;9G>R|ub3$E-Ff5A=p=jPC)f37t+L5D*V-FbS8zlq7N zu=vEw8Wx}Y-xhbQmHihERk(7g9jDWj0r%AJ>?q&{=+?++1#&pQI#r1`qrH!Y;JFO$udQ z=IVO;&kK#I4|TcBO2{axH@3%dW@oUXoN|Jj^N?Ikz)o*(yjk-g*Qq(|K}+v{Qz zHn;s)eX)G$62D7=9w}e4 z@KEdX`pn8jwMz~wShk?1%HGTD@_EbZYbtVvl?-J!*_-|Uaqa(KBsjcwX`R~_p^!8h zIbznp8P2krnRT;jm(5#RvvkFxy83~0oV;ej%()AeTCk(v{HvL)S>*D8Jx2*t$ys-WCS!aG^aM<(O{M(NgPKnG85A?i9$5CE5GCSQ( zrQ1(Rrk9ptOQsZgZTvdg>t;2U?xm(gnve3@TS!eA?d{>${X$8};dWk2S6X^|x?Y@&h*+xRyvkxi+1oQBdO`$9+4y5nln>6+2rzIvZGC|2qrt&|S1*;9d07yYS;cn|qMg z-{$VLXGYI{nVDYa{)RGBI(VI2%iLspuTy7#Vh^uV7k{Fi*Qu+U&}QP5iP2urj!dtQ zt+`dY*E(fCue(il%k(m`yzX5MWcvNyIwi|Br=8b6Xk3OG=f{CI+aPa%Tdud)eQ$pu ze=U}}{7V|p$LsDI9&Dgpe@%q{OYPZc%L5X(?3N#74YcukW|npFo&&78ZdW$6oA&>E z?Gg6c*-9gAz1FUzwDQ~*BRvCZ9pFcMcm7-n*>yrBWpA&CtJZQqhEw{?c3qa)Gs7Fu z%j?$pf6|u!%B6nu+ zqdRH_x!E(_zOohQNb0fMDmYrG{~N1p+buII%j=e7I(Bk8{+DC$UpLZKCbjk43Bl>u z&DEar%X%#E>>t^kFr1EEUA5CoFk4EWpkp(=em%X;iKm040(-3Hj_H5z-Mw7z?&)>z zr+3iaRuNg@PDY$M{F?X%*>kS9+W5Wtf4p1#y_6m_%WbQ7&{tVrrva9F*lIgDN9-gR zoIYtw!f7nheBf;VOlF5pcX#MCK7H+W5(y8pIU?5{J1X*cXzBmKa;+lw95c`^TW^Qm zwIOopF{5Vdbl>=b)Z6v5b)|nna-9|FW^=l8Z(r-sZU!2A-dNM5eeKq;pt8IszoMe1 zuyj&RabaFfPQ|$DlKj%D5HFPES61eX%de>_E2}9kD;*cA$RAgeos&C0K1Xg*!&9jKFTVBxd)F(+;C}GO=b1i z%G`=VH(Nnjb!nbI+wc+N{W`KyGb{2d%gd~V!J3BHJoJTYdwxYuWkSp8x01?nHDjv_ z3T*wAh12rmi~QrA6_&W(^yhIsIW{Y?p@pS2)oggA8kb$rXqMcHspVB=_Lhr_Ys$+C zORMtrmIrD69IJM#HF!|XQvV&~HClXZvE64?6!^O#zcj~UUZ|{~vL+`lSj|v>Zr8Gc zgg2gFHJ<*hDIY(z#`blI?d9B@s=~6;pr1y@7tGF0ShBEUV$E1{EU&OK*cg2otkSK_ z-)%L;g{4LDUYlH4P*{^w?zb|xth6*g*V*EmS1`nNm_L~(B`T|PbIsED(kMHzI=?!< zroehC{!)2PMPb#{cyv;i-%?RF)MK z)HIqodt{@zb8|{-sw#3yD@zKi{54nP=j2WG-^|!X!d6t~*oypJZ5=GJ*=AW~ZcSxX zne}PD>8O1e^i89cBpgriH!OQ{iv2Cul$Ga~#$Q9_u@!~m##fbEkJeP?S5>)VnN1hu z78m)=9XupBa)$a_^f#Ub@((5-nZnvvBlKdnbzgjKg@qLbIW_sYxi#5i3w4<1HaZmj zQ%hc9&bXSg>Zq|aLsbpfcR@V30LG7=ldsWw{U)Ase;|^I>7d9VL{MC!B&PPY{fqb zxjp4hcmAbKt!yL_XMmcV+}!GloLrsH;_Vr47rn_j_C~7;OY&`(`Rf=F-{rXp8!WdS zR#}m2Qsv}U6;28+K*JKQdmN#5r5;!6U#0!78Emt-iJV4f`oz;j!|5wKKfW8?WW1TO z!bGqGzFOBlYi7d?w$ZT_Id*-QPi~90cM^{$>nhH@#buQ`qDRCxXuBck!Ldx_`#ZdT z?(7A1Gt=z}(USP)oZMvvwmOrf;e6e2KFG~2s~K%t{m%MyK5@P+l@*vr=8n4%Oz~GB;U?k zx`Sa$ZhhHy$_$pv56+G?PQ;wL`s_g?a%arXtMi}270g{wJFjxt^w6>eiM``iU{{Lx z`^p=Xr^{zWercY`oN%s=@Bdu?MoCIpCoh;?S5voO=G@u^HSSQ0udJ}RIDcGDv5rW) zBgnJ!L&GJ}KOEv$uLKFQM>IMhWYTzBQ^E~d9`D-r{cg$>x>MzDC#l364m(r$N4Vd6 z@dGD&XrmQzbg?rNuKkU?`ma~M2Ca(o%KVdV{6ZrIf<0#EAnobwY+cao0w3={P6b&t zc@wK@^2P_(_{KK`!xHA#X{^LfRMi#!rOQ867FdT=j!!saqjqu5RCjy1+ci1ps*3#F zd^=^tcV5E@#5Fas$2k;s>v8se!i{pV9V!j`pH_^^DJjW`x5D+0-G|XFc0l`G)o{>f zXZv=HE3Hn?9XT@HJ=h(Xo$em(W{ns$B)#vFx_NcA^>zKyGv?1&v~2W@g-e#!Ezg)g zc(8$`bC%7YZgtkYg|$mF?78r0J4MWNz~-E_=DrpH*z^+3yTYy9sqy^!N`)9(I*<_>Q#-LCrqYdlnO0||HAP-r8C;07ajpT2B!ix)0j zlpXTRpntTb(e=8~J#mSxX>8e)e=Lz(Y?lMOz`FC1-#5W2*FSZ-y_KCcNbQcFi><@s zt7+&ZcQ03?t_qg0i>5zeyE6cGrb;+m{QcT6X4~ynT<5yRSB@dJrn(yUkh^Zll3<-S zg!?az2~Ny*lY*6!jNrJb-nVorXIx8@B3rbHi}I+igO~jgx(3chdeuFnsh; zR(!5tij!r+EunuSYvUc=k=el;tj*q3La!t&;O;Q(l;lg`&)P5$jE`W4X)VFnjjaZ! z==_rMgaKKudqj|UL2&I(98Zp)Y)>I_i|p(eyrV`339`G}lz4vw69>!xlVMpwVL@5r zF=K;0c{#cM2NhNJ!A5-j@q3GZ9t}2xwoW_D9Srf=gLhqBnls5g4Ezgl_W$%%9XK|6lRyoFw#H*I=U`lP z8d6zaSfequ+aHVpbK+~Wvpg$ycRt#N-PCF-+wS?}?Mvu^@`|$Yg*Ga*T~TV+GJDFv zCVfR*L!2gsc2_#hWT>gJkK7ubd1TvdwQb=4=Et3US{i)J<&RO~0~MO)&WVZg!cnjw zC(j=J>~{V3^>XiLoE=5+8=Z#HR-P`Y*)}$z)2x5v{lOh~;^E{U8@c{Ypbf5VyIt~g zD&1qa_!AsEI^!#ikN9J|$u zkF(ua(BFVv<^2ga_H!T@qWLccM{UD?EcS1pg2n7^yrIk717ZKEjl0jWClxj0atedT zgyv*?HhRlO8P&xNw>0ih;I1g~COH1EXb=yJ+%S@!V`c8HCUmHO#&vCWqc~pbJ>-o%I~=NT$MIfwr2}^en3Yi{I0|Qtxx##>ZUK7?RTCV5zRMM!+yzjkHXoK9-#zRW`EBI z&+*-4;^T0CM7Y~IrQtp`FaKZeRNW4qnjZ|F85TA^89196&~QuWx5GW#_9ucT_9Zz} zYH~}fbO}p*VC^^UpBLm{0LS}`KiKnE+3@5$+n&QE9$O91i`<(Hj*3QSqxe$+x5juk zCi)g1H>+>`htmFLIlDJpF@q<}?nO6P^k;I9TWPg_iMM@k-sak2_TNAM2p%UlT&4bT z-pOW|k?kJMvhKtt7ZeuTZD8UPg@zlU%F0}Q5Y(t2kQW*4ajNc576t3Yzqb+}qxvHJw`+26T8=+zW4->zI~?^uw_7W!gEN>r z0mF5=wtd?8No~UD$sY3fyU?!U|5S=MVW&I0JZZ$Bk8K!s4R5p{OW19&*_~%MKnZt7 zycqv*iHm12qzQDh=KI4k9Y+c8CUNIC`ZPvwv%0jXv}|(F3yhlF<9xT?U`Rs0jJ1c? z_R*aGv5Eh(8xrwi!W~4ThcSNh+*4#X;RZ}TaL-5miQpNon`DTTo%m=}Yjw}$3+#|c zeD>6M=)w(+zf$Ymc)R@L%C1FKITh~S(%iROjDI`65+2~H#o58rSGU?=Fvk0}4+C_U z;@?5=d4RwDgp;mB4Q^}V4>9d1<=#Xh@iAX^@a)xJjeFGTPXzbfY}uV?8(%}>hgaee z5wyfs;UAsx{>UxPDJf6500(-w5A57}8$P*e7&&AQiJ!#KKHEL544T&HOp#M=H~3R* zT-`|EgyseP5F8l1AN+Q5+GoVOKcMvQe+qIE?4^mljY;jI$ksZ1D_JnM=dmQ&xcAvdr#}t>@ z2X}TJv4^KQr3p{s+}>&YbR`&g1oz>Mu7(L_**$h}{4_jd4L)z6oeei!jYb`AYj!|X z+qE0o~*r8=`Yc-EB$tWXN3_ zgYIg06zU!_#%GN`jdtU-aTRWWyjyQK8W}ph{Qhtw7*;~la&vO6;|ps1OMA#|p5JO< zP~$|?A(}W~3GCTzySXKKjUF|*;iWI1d$Q;zg0lyW@J|bs|MqF8I+K>hZ;XPmhre3) z0FssYm!Hy{hTmIoyK}ep*>xrU*`n)WE-Ve}2zJ=yvWg06-p>esn`=s}E5A$=D%ummsKfP||O#A4rieK>dpYQXF+x`CiX}|y7 zufOfbzVdKXi)PJ3y%T<$-TgBA*cN@)G+CQ^eC&kii76*}Cnuj0IW_5waL9e-B~KV5082#fX z5haJd|2uJpi2F_EgrA6h1s@b~zsQ{M6R}@nwy(}4{3M6$t7M^{g5TV?so?eH@x_AI z7sY>(KR)5FBNDRj%_RIpLiY8Wgr7*rzSxuS6A3l`Vn`%p-(gMoiG=LitO-96zjX~D z60)zLB>dQyZWEIGLP0zGwyggx0{^QNY4&~wC(Pl#;E}UiF54|n-!1bC-oYca-b+Kh zXX@hfuOEjdUYmBmQvH{YHWOzb`JNv4owZqk2s+(tyG|5%_4$teh zuN?ouRr^*>n(ZR@db+EY$EqHv>h@TY?FRRKnI!8FxBp$WRrs}|t0qYgS8aFn6?Y!H z`G%>ERvoKau3D`+L)E^o>o2!h^;p%ls_Rs*P`zFCUe$+H?MtuzdY)5#S@jLocU3=9 z{X+FS)t^=EOR4^P+}BOq`*D9Y-BtV2sbAZuy1$O)cz4x3Rr{-Es}5Hkt(vP^s9L64 zt$KiJt?F#m`KtA*D^!nFJzn)x)w5JDP`yNTqv|HrTU75Q2>PRsT};>^$ZAshMgU)lRBCRQsxCst!{ft(vD=q*|dm zRrL_n*{Tavm#H45x<>UB)w5JDRJ}~~8r7Rr?@+y8^)c0FRJW?Wq57WcC#qko{;2x9 zYS_MWN?enRIgOMLG=#R z2UVX`eMxn@>IbS{s{W|@r>bWcEcbp}sJ2&4SM8@dNOfP;JXQC-cenf`)f&|~s*6=u zs;*HzP4zt0OI5E`-K=`A>SLce({clkNh59}7o&gW=XULv_R6LEfbL z;ea52r`p$UMBMyCRTpFj`AF3}?1s<1{;2BjLxUW(8yCmNj0kFp>IwS<`5e{fM+Ny! z)wKPC++B4_PLS(VFU<||4XPjK2l;!|y~hW6xay(_K|WgbuHqm+uKH(bkW4dtYy>ww)5>9;(x(1$nmWt?svdk= zkPlP6>Wm=Ys`}-+ApfeGbxx2+s~&z{kk_a_a6yotQB7JOYy8gyua%5n}dA3>O-4@{G4j??Lls> zI^oVBPgY%bcaSepecf*KoxdNcc6lJk{Zywv6y$}f*F6&CJ5|4ZEXaST4tXNTIjSq4 z3i64nk319P7gST84{{sT;unKFRrTzxLB33N`zt~IM77&%LGG_Q^Nk=cR=xhsAm6RJ z^X(x2M|IeHLC#e@YDbVyR(lddzP@K2>##4Y1t)d|9>0UqNoKT5iuQ-0KIa zo^O8;$mNZy@7P}ka`_9@o;E;pIa75`YLJ(y-fVv~$i05Q>Q6S1b2;21sQa`E>NwR^ z_V!+(eX@6MAT{|uslKlImg>ip0szAz>Mt47D5?4yC&Z{jloeEGMpS*U|O|ERDJM(bWE9eHYm@%h+Tn z)7IzaMIGmyBxm>t}#&wWC``rJ8;W!yUUxAkS%vB(dvxpQ9P`a0P9+WfBeDjK7&OwRv$C=i z{v9@KNP7Cnk;8|Lu=&!{4{362esMwYH=lx)hV7FE*6YaD)qe7VW4&*vqn$}JzSvpz zQ1P10+jc#$xY?!ccXp44&l$6`-*JV%Bt@DRtSi{EYi-uuMO${o7H`?LC2QNRIv5rZrSy9deZkRE0TULNVDmzE5~oNE$!Hx^h=LHTXuE1{O@1?`n&9>RjHv~ zmey_AwKe;rxd$YLzTdHWebM>}Zi)4U>-{Cxk7xeGdE5N7s-?9wVy(#@v-9-TXBDlr zrFLY!qIWT+SHC&O7C*Kt)cP?arxrbCuhHI|bhq`j1t%1pIN`*?lWhH=M;&qh75%Uy z*KK``zdoylYm3&7cdtz8by%_6+H%*b__{9Cx{fM3dcx6#$23~kkwr&MII8eyf9Wwl zOdsr)ww|)}Z_Qd>G{xGxCEnhgAKLVqJIA$mlmG7*{=fa^I>_|e>hZ0}^P9`i$O@IH$A zTKlg`Y=4{WyF#tpnz!#tR*k7P^J}i&N5_WuQ9iN9m>-7Jw=3CNYwyMO)m2%q*?V#x zhWwtL*mHPM^WrCVg~CtlO78K5z0O_?Uca?xmhF#F*!s4IYfot4qOJC~V=oRBR__S4 z+G9-fPA$@P#H<$iL&;NO?u|4ZwlM+)|S>YaNAyz;=r2aEF76_k`Gw_CA) zYQM$9mTp?mZfet=_bzNR|DoUeUACrG|3R1k^kn<@UcCR#6L%(gu~;a-*}71_f&1L^ z=ae0XJfC{bx4pZz{P_4-a>$FNgp%#SbV_Vz=w)kvXzxGX>NKa-;79GatK8LWKyp?v z6&rBE*kCGofUBQxcRr3T8a-jZ!u{A!Nuge&ia&Jw%8sOINhRAx6ht;Z`1#H=M-&bF z$B{88eq>}fIx?_1qbOs-z`}uzZ05-DdiAsQeVx^>uwT*M{?-?NTDCLXp6&H1>N8=l z!o33Pd$qTDAILsu?)KzAxAiJxo}NWLC-f@prFq;O8|S`lbA0nz_oDO(>4iP?N-SaN zu4U(a7J7Kg*6QWk2VQ^h+SjVSNd2qLaJP?lgo1tc_QE~i-x99)G=0|z&HJ~wWYk`_ z>^*Vs^xCW+(_@$1anBFeSAQ|=-gSc_>jr#vNz(_Lt$#bo&Y-`(^4pBIv2E>+>~YqE zPi?;SsqJ-_c6n<>?>6k*u`OdPn$03;15!gy@&1QCDO;PTuEge53yAwB}W%` zvJ&$~IT(w++0iaS$)5W@fxR}joz4Ebo!%n@+T_^mk$LI%PgdJ1oA%DMe^S=kRXUn{ zluafVwQzr*H~NUXzD0kt)rF(Y?fR5t&=!hrvg=!N^c!oa7k$;PZ7I=AYi%^@h6Sp=ord-H$hmR;1epzR|z!)}cl8qHcCm5FKUzwu~-LHpGv9W^H~p+RpaQbJ1(b=P^}*k6{;569lO zZo42H`@+_8VK~;xHgHimcD%i|J{%iiO}aQ7%dvO$Q#e*<<>zp$j~Vn!IQF7#{nv18 zto7EeaO_W8Zc0+@P}|T0NwKf3$)87JH(DdUh{SHUTf;9Sv6pR~Uqxcs=H1tk*!|Wo z-$Y_}TPJ-Ri9K$;@m(Y~-FEZNNGxJo_&yS=vh5Wo$Bwc-DoKtFw^o-X$BwbRUzQxJ zvz3)6$M&$bOtdqPz4wabST8G;$*}`$dsWG?mbO53a_m@hbW(C`fbD_F$+3JBY)W$M z8uM~$a_lBs*|g+XneF8Rl4DbBw;h-qD=~LAC&!jrBieeg3+)}X^J3pvBbIxy6Rek3 zc(Jv%vXx%!EraiPv6pR~?|QLH>&W-K*hpLT`(A9dwPlAF``O;Z2VU$P>!lC9*d^AM ztE78~p+w7~+*e|xrw?$*`T9aOj#vZnwcs&|>-ryUyfc4q-XzXWO z{7rk!ntM;v*#73xy-j0}+h*@;8vD(*aDUU-23z&zEn}%>(G@LYZ&~B7Y#A%FCT(mP zOS0W@Rm)g6Tj$j+W1rY8*R+f+wscaPSh4NRliS4JwZ&WQ6}!eA4tvF}w0FCxee76k z%i{L2eXV6n+Q+8YX6xI>+FBrhRO?Eq-kK*abGrs`jz>&570R zWA|Aj#%zeqw9V#hh`nwr8@nNvYHi8e5c?`U6w2Qa8*d#_upwqo07K(8#E!O}D1ST_ zvn@<~JhsecIpoXOy>V9Z*2OPu{v{N#+R{^?LEx=GIpU^SNCOXk-djmU&b=6 z)w91$ea>E6)H)nW-DYoQv75-WWtX^#8*I1NyNUib&r&zBziGJ4O`Kufc(|LGZ);g) zyEL_x_2_ChvBuVOoSS&YI%18RxVxwQnRPd@%R2FRH*t&2e1e;3V(;NZH}R>x(X(o7 zVuDSa?Iy~twdc5rp7sXMbrYZ4`##T2`Lt?O30i2?SW+Bva0$FN?wI|ts$=-$MCKj0!_V<@VsWWU(MBPMBBQZCz$+ng1ChoQ!(Zo$m zGQ*p?i6?EIW^Q7H^|k#)*HG$GI|;RL6Q5asw{#O>Yep+KvC8IY?Ivn%_quCR>Z8_U zZQMkbk+yE)V_S1OH}R8g%e6Xnvh4zUTo+0`%^IKNCbDf4?$_Q@*V{pu>?Z8}*}Jd_ z_Ztl^ zW5{G>44I;gAybtxWSTOD9H5LL2P$L8LCP3%urh|!C}YSW${13sj3LvNF=U1^hRjsP zkUC`ynWc;&vz0MqjxvVKRmPA*l`-Tn<-m}_$ZFgFtvA^j%$pDxGRMyC-n^(Y#~HH7 zTW$LIhAh^iGGvLO45?R?Axjly$TCG4a=4-lIYLo}ELW5vD->nON<|DgQW-;zQpS*@ zl`-TPWeho18ADbnW5{Y{3^`62L)Iu`$XaC#IbIn6O}RKBxMXaSs6o4QO1x{ zl`-TrWeho88AHxc#*j0WF=U-`V90{VM%(|bU$HwMZ((3a2fO|8&Wbv7oFV6V8}0Jz z8*;uDl_3`>%8&~cWynQ}GGx7?47pfQhHOxjA(tr1kV_S1$YqKca=9{wT%n91S1M!3 zMr91SN*P10R>qKPlriL5WemAa8ACQHW61T&7;=L$hTN!(AvY;w$j!}&KzgReclsx)8rd+ zzZR7t4=Boz2Nh+=Ly9uwVMQ78h@uR6R8fXJrYJ)mSCk=J6fxupWej;z8AF~@#*n9# zG2|I#40%==L!MK{kmr>#)Akh2sS|3G>?Mb7AYvmfH=6On zTDrSsyX{ROce8A_t0$^l@}SO6B~0es1|@l(*amC1As*{0a#QAz@k|I zESe3#qB#I8nhU_9LjhQH7yygr0kCL30E-p?0*i{nk#|gxw2SR&omV1@F0xx3Z(%s< z{Bjo6hrR#Uvq;~fr7SOtmXT%A;bd8K1X&g>C(EK0WLdP5EQ^jL%c7&mvgl|s799h? zqGJJAvBC%c2crS#$|m7F|k~MVFCf(dA@WbOl)!T}j5GjQ}jV3V=md z1F+~C02W;fz@qB_ShNX%Mb`tc=mr25-3Y**47QG6ydJTX@uLH2?4FDEx2Vl{g04#b7 zfJJWuu;?8C7QG7yEV@4&x!D9sd(?^Z0QW`qiL3WsIO_az7JV4@Ub4@(e2YF}d0F%^ zSr&almPMbEWzlD3S@bzs7JWgMMPHI-(N|PA zV9}2NEcyw6MLz?u=obJM{R+UMT>vcl4S+?z1F+~102ciTz@q;Eu;?!U7X1ytqEJ$N zlpl=I!T>Bv0t6QA2uFT0LDGi0hlL-=qC4H^Q<0>o^UGNjP4e3Hkwr0$S=59q zi<**UQ8ThEYEG6#Ey%K{C0Q1=BFm!IWGqSpU{MIT4~?f@)G2VhYT02cKGU{Nms7WD>T(VhU#MSTERv=<<- z$V-asV}hg&whzR;l%!y!|Gxdcf!8-F>ilvR4M_41=qrmdSY8$lB+H^qvMkCX%c5+u zEE+_XMT5z*Xb4#r4JFH>VPq^C4#1)j04y2_z@mKsShOzyi$(#kXfyze_5)zi{s1f* z1Hhsj02Yk}U{Njri}C z1HhuW04zEbfJKJ^uxK6ti{=BcXaN9=76Pzn5de!80|JZ6k|Ix>%I zB}q}|m$T^bB=55Uvginwmqp9TvSpUW682;6&Z_G z1F+~g02ZwQV9{Ct799`3q7wjEbRqzYP6A-j$p9=m1%O4T0b02ZANz@jq%Sac=; zi`D_K=qvyhoejXEa{yR$E&z+p17OklfWV@qNs(q5X3^8`spB$PG|PS|&buHf>ilvR zU7X})WXhrqEH8^LAi}4^34le{1F+}@02bW{z@nP~SadT0i*5m6(PjV^-3q{>+W=T}I{=IB0ASIb04%x- zfJJu$u;?BD7TpWLqWb_?bUz@l=%S=Zg$a^2+ADk}Qj!BFmzu$+GAfvMhR*j784@u;_UJ7QFz#q89;J z^b!DzwgRx|WdIhv0>GkI0a&yRfJLtXu;_IF7QF$$qU``IdJ}*}Zvn9AZ2%U%1Hhtp z0a)}N0E^xSV9^dhV9`TKkqb?bv|jEb`iEuF61%JRK1hl>znn#%BzgA^mPMbkye#^R zEQ>xT%c3vHvgk{)Ec%Kpi@qkyqHoBu=v%TZ`i_i6I{{eqJphY-0ASIN04(|mfJHw8 zu;>>67X1pqqFn$i`VD|ZzXP!74*(YZ3BaQN0I=vU02ciXz@kt@!*(nR1F$FwfJG4i z79|6)$O8lxeUub=&jd-EW1nz%AIqXt_Xsj25_Nt#i<(5dzlX}ArYtXunvrEubFwUI zL6$`=$+D;wSr)Y>%c3;0ENVlRMQzDg)DD0}djPPgJphY30I;Yd0E;>Su&6Tti@E@? zs4D=Ax&g4LI{=H)0a(-nfJHq4Skw!EMZE!7v?l02b{H2rP<4 zBE5&1Mg831J~a}I^qVDF=pTtXznn#x5ifs)EXrbeS(HtdMT5w)XfRn84I#^-p=4P! zj4X?WlV#BevMd@&#-e=yShOzyi$(#kXfyze_5)zi{s1f*1Hhsj02Yk}U{Njri}CGkr02VC;1Qu09BAZQ+v?J_GOJ1cc+SfgTTo#Esznn!Y zBHqiRWYJ2NmqkaCWzkV&S#&g679B&DMaPn5(JHbmT1}Qk$B|{x8Zs8G1z^$f04zEI zfJG+)u;?TJ7M%>hqEi4^bSeOgP6J@k=>RM`1As+m0MVGO> zEV`U5i>@HcqASU=Xd_t`T}75fSCeJYHDp(jMfU)(=w1L8-3P#;`vF+= z004^~1YprafWV>+k;o_$BrW2eI$k1+*4U@8-oufo^UGQEc*Hv>M;2{id0F%XSr$D> zmPJpIWzo}QS@aB97ClRrMbD9C(eq?k^a2@+UIbv#O8_j|3c#Y50a)}30E=D)V9_=J z7QF_*qSpaf^acQnwga%}O#l|X1;C=W0a)}70E^xQV9|R3EP5Y+MLPgk^Z@{iJ_KOV zM}WYhM*TWLeaf zEQ{KaWzimFS=644MI8WG)DeJ1od8(W8GuDy09e!&fJNN^SkxVWMd<)6>H)x_o&YTB z1;C=-04&-QfJJ=(ShN=ai~0hvs2>1}_6A^4e*hK@0ANuDAh4)ua->CpS@ewia(}br zV5I-D`(En6-UWLY$VEQ>~xWzjxlS+p-% z7L6if(P#h`?FYc3{Q+1s27pC504y2{z@l6L7Uco3C?9}D1pq7>2f(8704yp5V9^8s z78L=os2G4nB>*fc1z=Gb0E@~2STqrUMHPU+qO9adl?jsezWcrFY*|#|LS=H)`QGkr z02VC;V9_!F799@2q9Xu-Mb*iX^(IK#>F$Plk}TTjELxr%b$&UEj!O3KFP23|v%D-i zhAfMYCCj2!WLdPDEQ^jK%c3=8S+tfci;gGDq7%qibRqzYP6A-j$p9=m1%O4T0b z02ZANz@jq%Sac=;i`D_K=qvyhoejXEa{yR$E&z+p17Okl04%xyfJGMqu;?NH7Oe+h z(Zv8P+5iYFTA3W#VS=RnX3;xR78SZjke4J!onOwPE0Vo%nJl`J-EvMjoaEQ_ut z%c5(@vglf}EV_;?i#CyE(e-3mbORZSZUkV_O#m#q8GuE%0I+B?0E=z~V9{*=EV>I}f5E&wd*3c#Xn04(Ybz@l^j7WDvNQBMFC^#Wi~ZvYnU3BaO004&-IfJJ=) zSkw=IMSBCVs6POU1^}=q1As*X0a%m?z@jWbU{MP%vdaWXTjqW-t)&-?^ar{J+1Xyy z`QUkZf$f98^FN=ngWzh(-EE-9cMf;Ft(Y|C^G>R;XMw4aHeq>p+KN*Y00I(ESdnoq9Onm6$7xS1b{`Q04yp4U{N^$ zizWiFr~-gRl>jWN0$@=!Ah2k#7unAQN$YA~$@hlHqD$Swqe))W`QPqC?2CsFo~?rjupS46-bmNyef&02a*xV9{&<7R>=*(Odu) z9SXpr!vI(`4}eAU0a&yEfJF-dShNU$MT-Ggv;=@f^#Ckd3c#Xe04zEjfJH|DuxL2| zi&g-zXeA)9Xo?qEYl5WBb-#B#RTiywf4%BRFY5eq79Hz(S05;gR47M%*fqSF9abUFZw&H!N1nE)(W2f(7U z09bT30E^B6V9~h%EIJQ>Mdt&s=mG#1T?oLUivU=(9)Lv`1F&cV0E;dGV9})jEV>L3 zSah@(dDa9;t8~A2eT*#Hv$ciGy{PlcS#*`>eRZ%bx|-!>(KTdQbS+sHT}PHho5-^0 zda^9Kfh>z|B+H_k$g=2WG8Wwez@p6nEV>ndMYjR4=ym`W-2uR&I{{d97XXXy24K-W z04%x}fJOHKu;_jO7CivKq6Yz3^bi1x9tL31BLFOV6o5sK0kG(C02XZl1QuQCMOxLE zMW?#c&qi5P>^=c`!ize;oJG%gUUsc4dY0v7(Q{;3^gLM>y+D>lFOp@^OJrHJl`M;1 zCd;B%$g=2FG8SzEV9{#;EP5S)MQ;GGXgdIl-UMLLTL3J28-PXc0I=v?02aLmz@qm7 zShNFxMIQjL=tBS&eFVUwj{#Wp2>^>e1z^!<04(|(fJI*b0*jvVB9lyzv^(8{#;0Xb zIBeldFY5eq7Jch^N6e5#-?6+b+DVp0-;-t04`f;NBUu*xM3zNAlV#B_WLfkpSr+Xg zW6^H_EczXQMSlRW=uZF^{Re0a(-ofJIFKSkw%FMa=MV-j9s54m>bs@{5u4F9g2Ed~304z!e zU{MbM7WD*RQ7-@%^#)+ko&YTB1Hhua09e!)fJOZPShP0)i~0kwXaE37H~*$WLY$uj74(*STq-aMTY{g=r8~l%>!W3d;k_L0ASHV02VC* zV9{a#7A*l_Q9S^QmIAP7832n82Vl_=04!P#z@ilZELsV`q9XxVbQA!Kjs^r49gq@P zV1lH5<32|_P!_Fpzp{2rO4Rw~EIKa5J9C~aTEp_PXf0V59Z!};Cy-^)iDX%H5?L0V zOqNBbkY&-SWLb0?8H-K_V9^->EIJc_Me6`qbQS=M&IVx7IRGp=7l1|Q0kG(N02W;U zz@iHQSacBpi`E0M=wbjCZ2(}=B>*hC6o5sS0kG(D02W;Vz@jSwfkmrQB6pY|X+3+H zIICrm{a;FLz?KqqemRS-P4Qk^Ad9YJd0DiHEQ_uu%c2{|vgk&#EV_v-i*6>%qFcza zXfs(B-Acxy+W=T}I{=IB0ASIb04%x-fJJu$u;?BD7TpWLqWb_?bUy%#9spp`g8(dg z2!KTo1F+~302Vz8z@ok02aLuz@i-hEcyU|MIQpN=pz6YeGI^& zPXJi-DFBN;17OkT04(|ffJI*du;?oQ7JUr}EP6I2GR6c+yWf3|_M9wQ8?o?BO4Rw~ zEc!mhtF4zsKd`(k`jIS)ej>}FpUJZ57qTq+l`M;Pk!8_uWLfk(Sr+|4#-cv~So9wN z7X1alqQ3!H6pCutjzwVr79|0&C<4HuWB?X<04z!YU{Mr+MKJ&tr2??12>^?l0)DT`inUvW%}Mx9^IqCKMCwaa8t zdzP0)9muk%BUu)8BFm!AWLeaOEQ`95Wl=Y>Eb2~{Md@TL>H)x_o&YTB1;C=-04&-Q zfJJ=(ShN=ai~0hvs2>1}_6A^4e*hK@0ANuD0E-3!uqYFNMOgqW$_8N3AOIE(24K+; z02U1eV9_u@U{Tv>Q~e_m17OiS02a*$V9^2q7A*u|(INmAEe2rG5&#y}1F&c*0E?CZ zu;_3A799b=qU8WAS^>bKl>jU{5`aZV0kG(302Unsz@lRTShNZdSafhSGQ|W*d)0l8 zRwIkHr(0MZjXJ-aMaM_I6-UXU6Ifmrok*5NCy`~*$z)k{3RxDNN|r^Zk!8{8WLb0u zSr(m1#-eoqEIJE-MP~!B=o|nRoeRLC^8i?MJ^+g@0ASID04%x)fJN&8SadM}i#7nT z=n?=HT?)XW%K%t(IRJ~U0ASIT04&-Fz@n=FSadZYuxL#*a;XWDHrqWSS}Ti=aL=x< ziAJ4Y&Z6t1-owYpq8nIV7TrjeMK_UU(amI8bPHJ)Z6?d2TgkHMHnJ?boh*y)AY;*; z04%x-fJJu$u;?BD7TpWLqWb_?bUy%#9spp`g8(dg2!KTo1F+~302Vz8z@oCK-#~0$|bG04#b3 zfJN^Du;@Ji7QGL^q8$J%`T&4M9|ExGBLEhC48WpK09f=X0E<2YVA1CQEcya~MPCB2 z=qmsgeGR~(Zva^IEdYzY0|XYm5RL3@f~0M1W8%Chiw+QUO@h1b{_N0a(-wfJMy#SkwZ5MJ)kX)Czz_tpQk+ z2Ed{=04!PnVH-N>@2J6RT`lVwp4vMlOJmPNhDSkxPUMSB9Us1E>(_5xs0UjP>M17OkK04(Yc zz@h;FEXn|2(LeweWdg7$3xGx004y2=z@otbEE)p9qM-mR8V10k;Q%Ze0l=b>fWV^m zvB+H}NLp=g6Q@Hg80nX}ZxZbji#orYMf=6PH%^pA`?I_(8bg*vIb>NhmMn{M$+9Sq zEQ|8VvZ#P8i^h><(ReZz6#}qm0sxDO09aHEz@icW7L@|9s0@Hbx0>GlF04$mYz@h^HSacu&iw*){(ZPVgqEWHPpC(9JGdI#7 zEsG9sXQ3t*b$&UEX2iU%r^uq2EH8`d$g*e_Sr*ME%c41CSu~d{iw-5rqQl6tXdYP> z%_n2g0ss~*1Ypr302VC&VV9~h% zEIJQ>Mdt&s=mG#1T?oLUivU=(9)Lv`1F&cV0E;dGV9})jEV>MUMVAAx=n4Q9T?xRV zjQ}jV3V=md1F+~C02W;fz@qB_fkh|8A}5(3X-9W6aZZ#)neIS#&E|7TrdcMYoe>(H&%2bSGIB-9?r~cayQ`9sm~I3&5iL09bTC z0E->~V9|pBEP4olMGph8=n()GJqp00#{gLLH~@>b0I=u@02Vz7z@n!BSoAaii=F{s z(X#+7dJcd^&jYaN1wdfY4YA0JCP>=3F%#!TS=8Kp9P(l;>ilvRy%O`jTPKTNWqDb& zjVy~^Bg>-K$+GATvMkz8mPK!pWzkz?S@bqp7QI8pqIUsU^d10<-UndO4geN?0KlRT z0a)}A0E<2bV9_T4Ecz6HMV|q%=yL!TeF4CtF9BHe6#$FA24K-Q04(|zfJNT{uxKX$ zi@pb7(GP&YqOGw=+q2A~i`?&BzbuPdy9e1n#-h$IXVI@QZ|FI)Xcx=NqTk4}=y$R# z`hzTs{v^wy|Bz+TUu0SIH(3^iQZ;UuMPV`)B>}J~0>GkV02X-wEJ^`jQ51khF#r~& z0$Bb#*<}HAz2np zAj_g6G8PpBu&4xpMWp~NDg$6qIRJ|$05)799w{qJscfbT9ymY5-Vt2mp&}0f9yPr$#8VlY zm$PVAsux`^i)ORDESf`>MRUor=uomOI*crf=88H*MJuxJSY zi|PSbv=o3v%K%t(H~@=|0ASH_02ZwPV9`nd799z|qN4ydSu1;C=! z04zEVfJJKnShN;^MaKiM=mbDu(ahAy023r_ryG{l$)azZQYWTHonOwPQ&YW?4YKGo zmX}4RlV#BvWLb13Sr)A$%c8T$vgmBGEINlQi_Rs>qVvdDbUpx!E&yQBg#awN2!KWF z0a$b~0E;#Nu;>y17F`O!qRRkSbU6Tvt^i=sl>jW-2*9GN09bT20E?~xV9~VzEV>SW zMVkOvbUgrzZU6)potzq3VuGaQyDtx&B8zg|XZkm$Mx9^IqRpw^IhV?!TUlNf-A0y0 zx07Yj9b{Q_Cs`KVMV3W(lV#C8WLb1CSr*+##-jTHSo8n@iyj1E(L(?%dKiF3j{vaf zQ2-V_2Ed}n0a&yJfJILLu;@tu7Ci;PqNf2^^b7!to&{jha{w%Q9)LwJ0I=vq02aLj zz@n{yz@nQ|BlnmfX=B{)UEd;$?spcwoEmk0Ig4IP_1?T(7QN2$vgi%6EZR<%MQ@U2 z(OYC$^fp-*y+f8o?~-NFdt_PkJ{gO40I=u-02X}+z@m=;SoARfi#`Eh(Wd|``V4?Y zp98Sy3jh{<3BaPS09f=j0E@l>V9~b#EcyD(mh{Bjm`Z{pQmEsN4wUKaHr%c7oSS=5Uxi+Yn~(Vk>k)Q2pK_9Dxo zzGPX{kBmio1F)z+0E-3yuqXq7MFRm?lnKD1EC3c|1F&ci0E-3#uxJPXi-rQQXcz#C zh6Au@1OSUh0`*zTYH^ z4rO^+bQoC{%_GaA`D9tNfGmp^l4a2%vMgFmmPJd*vZ$VnMN0u#v z2Vl_(02ZwTV9}8PEIJB+MMnd$=okPN9SgvsRRAnn4Zxz~09dpJfJJKoSadu9i%tMw z(TM;oIthS9Cj$bDW;coKalKizu8WB?M;0x2-vK$LN!0n}EIOl!H~dCfbSBHoqIG0h zbQW0_olTZS=a6O5xnx;%9$6NhPnJa&kY&+@WGuP}fJN&8SadM}i#7nT=n?=HT?)XW z%K%t(IRJ~U0ASIT04&-Fz@n=FSadZ2i>?7+(X{|9x(;GWLb0W@ z7Ci~TqNe~@^fUmAo&jLdvj8l54uD0^1F+}?02aLnz@nD`ShN*@MK1%e=oJ7Ky$T2{ zy0uBilvRZExZ|zF8K%$?~%3EwU_nn=FgoATLgZ_hd2&5FrVYAcY`pp+yp$wzQ2x zAS4heR0D+|Emo|hrS9(T?(XjH?(Xg_^>g2Q|E|e|zVHA0&N|;&=geB+p5Hb5+4Ica z*Oq6G0KlS;0a)}20E<2aV9{p)EczUPMPC50=t}?=eFeaxuK`%}4FHS21z^#404(|* zfJHw5u;@ns7X1XkqMrd+^a}useg$CBIzVL6E1lw>nIHuZ``12Rl||e6CqsVgl<9uC zMSpclbi7d({Y`sW^bc7U1z8%o%c2-r7NwD8QJgG`(#f(YL6$`sWLcC+#-a`YEb0ir zqD}xT$^u|fHUNuq09cd@z@p9oEXo65Q9b~R3IJHt1%O3e0a(-xfJNN_SX2nWq9Onm z^#EW|PXHG60$@>Z02XZkh%EY}Q+${SQZQ?PiSwr{de1K&^~uU~zucn!S&90aWzhiI z%c6l~S+pTp7Hve9MH`c4(IB!c8cdc&n~-JEres+(gp5T)0a!E)fJMUrSX2VQqEY}B zjR0WLNB|a%0$|Z-02Yk_V9{6r7L5a7(RctBZ3e)i%>h`n1ptdC0I+CF02XZpz@n`I zSX2hUqH;iFQE^s$r3q4SL$Qg|FDn}9Z{kW-WM#TvZqdZ7#L2hHqDi!uMKxquG?^@m zrjTV(Em;;#CCj2ZvMj16%c5yySu~xDMGXKfY6M_W699{v0a&yR0E=b-uxKU#i?#(| z(RKhV+8%&KI{>g~M*tS>1i+#e02a*xV9{&<7VQkcqB#I8nhU_9Rsa^w17Oj7Kx9!> zR{RbVq~L6SH?~?94fQXCEXc}qzucllS&27qmqm+dFN>CtWzkZyELujEMZ1w@(Q>jZ zT0xdYE6K8G6PKxEM_S@GZwv*-)| zhV`zp=mmQ$adcLu`{foLpOxr$mn=Gg_Oj?ivMf4@EQ?Mi%c4`rvglN@EIN%Wi%uuY zqBF>{=u9#eodv+6vjJFi4gibJ1z^#604zEmfJGMou;@Yn7F`6uqKg4obO`{9E(KuG zWdJO?9Dqev0I=vv02W;Zz@n=GSab~li>?J=(RBbUx*iZ&bZl0<+5{>1(od+5lSS9~ zdC?77neLZcbW2uZ{ynnjR@%#=+sLx$cCswGgDi{gB+H_^$g=2evMjoXEQ{_X%cA?p zSad%Ciyi=A(SraidI*3;4+F615daoF3c#Yr09f=m0E?agV9}EREP4unMNb2;=otVO zJqy61=KxsrJOGPc0ASIJ04#b5fJH9@u;>*)WYJAo@uN(Tg75w7us6%1cYVk7YF4KE za02X}?z@jezSo9?Ti@pM2(boVh`UZeS-vY4cI{+4a55S@y09f=R0E>PCVA0P2 zEcyk2MZW^DXdM8Hegk09?*J_N0}xsCdRF`e6Qtl_zg+!>ELz^j!k<~0?w4B>WG8-n zKo-TaHIkP_X=GUxC(ELAvMfrFWl;uM7G;uUQ3tXt>PVJFoyb^}1;CI%T3ZU8Lm4#1*902UPiu&4(Bi+TdEs22c> zdIPX%0{|BF0bo&I02UPkB8&dciWfa-7WMY)MgPd6{;pKN>`eE|E!r?UG5%p$v=QxP z(Z*z1G>9yV29sscCS+N(DOnZ`A;=60Fgxlvg13MAO(B*FV76jjz;?1_*=8p*_rN_TQoU4vG1d@XbSCRQ7u^(O(n~s zI^#%Pl%7JCXI2EIOI?vgj1DEIO4ei%uiUqSMK;=nS$fI+HAm&LYdA zv&pjP95NQ23&5iD09bTB0E;dFV9|vDEV>AQMHd6G=n?=HT?)XW%K%t(IRJ~U0ASIT z04%x+fJIjWu;>~97F`R#qU!)ybUgrzZUA7>jQ}jV2@qLyLUz2w1SvS(KX-kiEPBM> zn!PzY)BSRbZqH6ke?}JFL3>$rCs`KVMV3W(lV#C8WLb1CSr*+#mPPlIWzhpmhF#r}l4#1)(09f=S0E?aiVA0b6EP4ijMb84T=s5ruJrBU5 z7XVoFA^?kC0$|b004#b1fJLtYu;?`a7QGILEV?y2zS;yS*vx+>MV-j9D2ptMvdOY2hm1wJ04(YZz@j_= z7Ucu5r~rUPT>x0r6@W$E09e!=fJKD>EGhzEQ4atX^#ov1F8~(x24K+!04(YQz@okY zEGhEGM4!qFHo+f7CiHCmN$I?P_6QPNw_i77fZt40u@<4W_;J zMVpXi(WYcsG=waRhLUB`FtRKfPL@R_WLZ>7mPI4TSTquVMWX;%G#Y?KV*pq*7Jxy}$+D=4EQ^}SvS=H!ESf>aqL~0J+7^IC+X1j>djJ;g0KlRh0a&yX0E=1xSTqZO zMY91|v@-yU<^Zs0E&z*K0a!E-fJO5GShN6uMGFB~vb_HP3A^;XG21FK3$%!9h zf)w2CpS!M=MZ^6hX-Q6|`{fob&q-YSx-42jds(!SEQ?l=WzlM~EZUtci}oPPqBUe$ zv?o~>?M0SFYspx&Hvo(F0btR-04&-MfJOTQu;>5)799w{qJscfbT9ym4gp}%p#Us8 z41h(41F+}_02Unyz@no7SadW1i;e+c(Xjw5Iu3wE#{;nF1VCibvYhx!CP=}_zWdot z7M12&I58*F{c?*=%}MqVveI z=zKC3T>!wM3jtVk5de!W24K-804%x`fJK)9u;_9C7F_|rqALMdbQJ)Lt_EPyH2^HS z7Jx<90kG(L02bWXMW2vm(Whit^ch(eeNL7|Uyxo}7X1mp zqQ3xG^fv&D{sCZ7kgI_?7R3OOMepXsFEK$1?(+}Hz9)+&_}d|AxtZ>lTa=NTc=Q8V zlu3J8)PXFEI+A5kC$cQcBFmy|vMkCW%c5MeEb2^_MR{Z_$_HRk0RW4-0I;Yl0E@Z- zu&6r#iwXf)R0P1H9sn%r3BaOW04(Yaz@iNRSkwoAMSTHSR1CnPegG`$55S@U04y2^ zz@iNSShNu!vM4<_{*?(*aIt?dEs-0I^bhx+3f(w2)BSRbHqA}sd@PHG&|Ve|CCj2= zWLY$vEQ?CWvZ$0Si$;)T(MYl^8by{xqsdq_27pCl0a!E+fJNg0ShN`ci#7*f(G~zK zngGC}Edf}x6#$F224GPc0E@~2SX2SPqDlZ3RROT58h}L;0a!E%fJHR`ESe0!qA7sL zqQSZG5hh5%Z~oTVCbDQ3e>Bo!8b6gq(`he@8pyJ!kt~av$g-%JEQ_`w z%c2=%Su~R@i?$`pqV337v^@Zeb^u_}jsPs$34lc{04$mXz@pgzEZP}>MRNdHG#7wH ztpF^V2f(8F04!Pnz@mi!EZPNtMY{s9Xb}L576Y(o2>^?h0e=uiL_9R|Rn!vR=y1OSVU1Ypro z04zEhfJMguu;^F-799t`qT>NrbOHd2P6S}lNdPQ584y{tA~$}I2~tq$2eFm1XoqmX zmYeB*xkYE>Cf@y07M)3ZS#%az7M)F&Mdy%Z(Ya(GkI0a)}J0E=D+V9^@@ zEP4}wMQ;JH=xqQNy#v6acL9+_cjv|@n;-=_#U{=@vS_=wh4*qZ-7mN3quj)<-^rqn zX)lXDAPBV9~DtELsP^qTc{m^g95H{s3Unp8zcS3xGv`1F+~H02T$EHEhSC z7yygX09X_UU{N|Cvgm`{_;Dsk!O8x)>knnoO#jGQqI0JE=r&Gg%hpk!4XnSr!$LWl^bCHUePL#sDlD1i+%f zfXJfE&hb}Fkb>L%LSu){(MbOq|1bA8>740)xkbY|Cw~1&77eGpEGi+(qEfOf8bOvt zBgwL86j>IHCd;BRWLY$pEQ`jGv1mL1i#7vb(dGaw+5&(@698DWB>;=I0$|bB04yp4 zU{N^$iz)zER0+VMDgYK$1F&c!0E;F8u&4%rMUw$oGzEY~wE!%d3c#W|KxEO7&hg$q zn?-}&qM@>Ash?ffcg}Rb+@i+Li3z{Tq9)qQqGqxz+J-EPW{_pkOtLK6mMn|5Bg>-g z$+Bn%vMkz>j72*Eu&4!qMY8}{G#h|LI|Hz24gibh07C;{n;-?Z_y^M(WYLdq z(aO%5?w4D%N9V+WzsaICw3kJDl4a3eWLdP9EQ|Ig%c6bAvS?qjEZUDOi}okWq65fS zbRYnW4gz4&!2m2e1b{_{0X02Un%z@j4nSac)+i;eE7pbPnxh(Ya(pOqNBLkY&-OWGuQ2fJK)B zu;>Z^7F`LzqN@N{bTt5rt^r`twE!%-4uD111F+}@02bW{z@nP~SadT0i*5m6(X9Y1 zx($Fuw*#=~4geP23BaPe09bT4AhPJp&hc+dkb)5w6KBbypZ)N5Pv=bc%Po4KbE5O# zvgkqD%c6(Kvgl#5EP8}2iykG*qQ}Ux=y9?vdV(yAo+Qhnr^s0JGysd90btRy04#bA zfJM&(u;>K<7QG0-qL%6WHn`#~MGTkq?C_684W|}O@p}j21CCj4D zWLcC)mPPqwSyVulMP10Us4H0(btB87?qn<~1Yl7S0E>D6u&5^hi+TaDs5bzMHUMBz z9{?8h1z=Gz0E_wou&6%(iv|F&XdnQKHUwbNMgT0@7=T5C09Z5_fJK`CuxL{N77YPJ z7In&t-)Djp9PFn;S$WY&{~5PvXkMoK-kWLdNsSr%hAAm&*09dpTfJM6iuxM8R7A*o`(P97= zEdgNBQUDe$17Oi^04!P#z@ilZELsV`qE!GaS`COSYRZe(nji(|`}=6kvZ&OD{k!L7 zx?gV5UU`Yd9c9s4+RLK7$+Bo4vMkz{EQ|Id%cA|svgiP^EIN=Ziw+{oqJzm;bO->8 z4h3M*VE`;T9Dqef0I=vt02Unuz@no8Sab{ki;e|g(QyDQIv#*UCjhYML;x0@1i+$` z0a$bj0EB9%c9H4vgisj7F`LzqN@N{bTt5r zt^r`twE!%-4uD111F+}@02bW{z@nP~SadT0i*5m6(X9Y1x($Fuw*#=~4geP23BaPe z09bT40E_McV9~t*EV>U6S#(Zb{52D#px)ocKUWr=<6j85KQGh$a*H0$OZ=82iyoo9 zEP9kIiykA(qQ}Xy=n1kcdXg-Qo+8Vlr^&MD8L}*TmW)Nu0kG(K02aLfz@ircSo9JA zi(Up`(JKHfdKG|0uK}>=bpRH<0l=a+0a)}F0E^xRV9`4OEP5A!MehNy=zRbdeE`6s z4*^*85de!m21FJ;m>2JpYZi6zZ#6z7i;nbnV?W8ubidr9FY*#w<;kKiX)lYuBFmz$ z$+GAhvMlI=Z4VgMHP17J~q02U1Z zV9`JT7HtT?qKyDpv@rmS1_7{WFaV1-0btRl04y2;z@ni5EE)#DqTztZqMZEr6(&f* zdkGUKH$NKb@8VY-OY$?_FSlq^e&WflvS>8zWziV2EE-FeMdQe_XgpaKZAO+wo0DbH z7Gzm8fh>!*BxBK504&-XfJJ2hEGh?JQ3U{tDgjtj1;CBD%c3jDvgk^(EV_y;i>@YP(KP@px)y*%*8#BTdH@#P0KlRf z0a$bs0E=!0V9_lAEV>ndMYjR4=ym`W-2uR&I{{d97XXXy24K-W04%x}fJOHKu;_jO z7CivKq6YzyMd#XS!c*(PR0E4>yoSkJDZjJwcX5Pm*QP zQ)F56G+7osLzYF)l4a3zWLfk)Sr)xO#-bMiSo9JAi(Up`(JKHfdKG|0uK}>=bpRH< z0l=a+0a)}F0E^xRV9`4OEP5A!MehNy=zRbdeE`6s4*^*85de!m24K-A04(|xfJL7H zB8wi$k9X)}7R~5o;yfygF7R(Pex9G{ez`?o=O+di%c5^+FN?k<%cAedvgmuVEc$^g zi+&`_qMyjJ=x4Gl`h_fuekEhkIsg{^2Ed}<0a)}00E_+vV9{RyEczROMgIV>C@9dd z9gAWBEJ_1lQ5=9p=>RNB0I(IA@|EC3c|1F$Fu5LxtPe!R{E zDflqo#Q91VUEyzsfJMUqSTr1fMI`_%Dg|KC2tZ^}UP1gM6Qtl6AC~18L?iuk zOrFHZf=u_zEgD;pxOt!~8b^CsG@dMrHY3ZT&B?N83$iSlK$b;Yl4a3WWLdN|Sr(O% zv8Wt?MHK)nssvzB6#$E>0a!E9bidr9{RWzk_|S#&sA79ByBMMsjc=qLad9Sy*uV*prmEC7p+17Okd z04zEIfJG+)u;?TJ7M%>hqEi4^bSeOgP6J@k=>RM`1As+m0T02ZAMz@l>iSadD` zi_QaJ(fNSLqJ0bE^GuL}i!3JglSM_Y)CC2Z?pM$~NJ|Xpc>R!AP&mQPx`VW z3@SXlUl0r_eAeD>DJkr>Q4owO+%!(}Q5Y!lN65;Gn`6n}gu6!X7h&;Hbiu?SkOA z!i#qZf|Clr+$ji7D=eKI1ZNfQJ|_syE4;fk2rep&F9?Fm3Tt)=f~yLTT@(b@6~4SA z2yQCuwObI}Rycb_5ZqOG>8c>Oukh>LgW#dUk$VQgV})zh2EkK>_wEw}&lM*24}zBp zryLjruN5ADa1gvz`0AlS@Lu5tM+Ct~g>#Myg3k&sKPCviD*X1iAo#9u^oc?6Q{i4G z2f@0+`%evmKZ`QYu;m{sntGQ1-$z9!o?~kuR`mLLwhCfJeJ`|i5G!iE*j7TU=*mlN zEyRkxzuZzpFNslMgCti%#0QJ zZ|m<6EAk&lpA{?eU$>qcEApQwUJxtt-U{?6Y^u_Ax#=CxRnUweNmR^%5?--{Lb)vu3Y zMSl6>vsjUjKfj6<`2ga(SdpIr{uC?nL-@K_k?({5j0K(M+J=(2DB9$DJZalb#;E+_ z%pmA_qiq+lky%~rzTYM#ES{B98Vh=T*U29lIo2MrD<|Qt*TuH&#YRqbHqA)6{q>q< z!{gY<1G{3cGmNLSapYg$W8hy^mWe zq}xeQY%7J^Z66ZbItqQxvnTWA(PvmJ=o_1s$lmnstj+tzrf1|I^~1yK*7l7xB(nQ; zxnXtRSYsml-g&Q%4f>dbVUxzFNk;w+Zys{YK4F^=FTeBHJ;F9SUhu&HYmFMEYM)%#aB7Eu}r`~`kMtN`R)bwSVPMwzCE$qSzzdiEBUSZou-@0u`*mg?gan(VeUDSim>A`71pS7Az z@8Np&-`&2ni}xUVNw;mYY%Ur3-+%SolY54Ouf7?4KuCq4Vdmk34@v5kCM*dCTKk=$9MSGo_ z6wfXR`>^q~o7g(G#y{SF-e+rqJ_lHv1=jcq+T4BmXK(Etwi)u}+0n{4?&G8OTN5^V z`Gq$h-z(^Ii5k5_qetI= zx!E>l|I7F_Eu;Utb}0A1jL$55*)0hCFQbD^_PkO5%lOnD`P`=Wzl`*FMi9%7ZJ667 zE1ugcx4AGsmRA@AX#<0-tSt=%LA-kq&)qC*^Q`e%HC^m5rAKVnl^7j3$w-gIbGOXO zvWKI|Vg@q@S*zambREJww)g88-mx7;C(SSs%`ht#tLfrRvisTWhFg=I&i3R!=iDx_ ztgN|lU zmyLXnA2fT(&@88)>-T)N_JEhw;oa$8j*F-lo@n~HDRWNV-P-QOf(9?qoMyJosln$I z9%2JK{rmULwkB)a=*1hQ1;;nFHEyJ_iz6^41k8kNNaA z_4wh-mM>hqaOJ|)t-EuAxa(eM=uW-o6YzPxow>x$VchPRGr zS+R1}+=WYruUxux(VPXd7cN;beEys{Ewh&|9$s3~GO}ev$%xXH(h`S54GvwhbV=*b z*4aBR99mj3Y~)aXc$huh?xEoem&{qTYHsWB#k1!uSh(c>^KPtIvm$j#%wI6PZ28<( z3zsadSh~D*XmVNXv2uC1NTMY&ZTZq&Y?-eZ-neY`@?EP}Eoo`8*D`-2b0QuzL2&R$muEAdSY4TR3cvTh=nSb>8e%i&nO*T(hio#jph~ubD7+ z;gXdW%z5*#WzN#YiG~%AAUj8#BT2bD=+1gaZ4^Twxk;j6!$g-}#bLuP;k+i;BR+!(iJn%wq(0Tfl>IMJ&lkv%DqlM(MZtV{SZ2lr3(>|;PntxL4j25YH>ahN?kBGJp{ zX|H1Nz(lX!28J7mh1C~UPR5qrqFds>x8J}go08~NouhtjsD6cUn7yzOi5@oJj#CnaHQ`GiK7YOT(R?=SpXlDlCeW+=?{n*(QJ5$k zY*S9qeEwa-rEiZ%wSQuucOdN7fP`i|FtwY$)<$S*=Ekd|)+RRm_gwzNi&ggqZk#BL zukjiCy7m>!jN9sZ-Si%H`;YzGqOE_!BWwC?yIyyb`j|N8U$o|^UL*@Kw z)Z6v!WzTD~=>MM$|GzPdUcN=~B2j&KVgrAzu|(0Z#L&`2e)uxdW_C*y`n}GHp?Y0m z92P#FX0L6S;WRCUG+*g`9c-+}hbJE&>o~s0u;}qY|9ae)Vp@E6Js$5^{I4m(84pX8 zhEEt@JuI<--;0*N^&lgjU2L0|uOVO7(e}ztU?Zb>zQfM<^&5YDpUMBf+`Z&w#P8U5 zo^|u{*sySKddogrM0<>Z{S$@%-b1XnA?J;-rVqw!(PhMUn>;_!*Iso#yC|*3A-2%` zfD=a7Gk)j3_8h*T2ANs^-q)_@bJr1R6YLbQx^Y@dRYOBdP2DzSwKbJ3WepRXr&iT9 z1w1gdsivP1X*DyeYFn!78>W^uMbBun zYCm~-ZGFX*mddiGvX;8$spVA-{yOR#qNzuYOMT+H`j*D#^2UmW8lSAXzPYY4oNVm4 zNnst|uA2>2jnnF_htZry*)%K*?|W54Sz}7iS#DDsC$^L~S6AEo8*8?!N;dh|E3296 zOEa9tmt=WKYDa78TAF#{@#c*C`%4jyD!>PSz)hRE$s%a9-w`JO-ZCh+z zPqnpNQPxybUl%Q>@yUjz6)7!i8m70Dn`4zVjnR{_ETdWa%)-^yQd?6uCArjQ)Ku5B zluZkJSy5kCS5@J*gyvO`@&y*&t&|dt%@q}9X|grSPH(Piu4<{aC6#<=T3JI))3(Xz zQco?b+g7WtZ5H8bYpib!dr)asCp$1Ye12YqrmHTs?W3i!zPh@l-NdEi+f7|jR@c(h zP*&GCwWcYYb3;{G<+kCADQ_oiLt~lEC|uRHfF(B1S>IUE(%4jQ%e2aL)H;loO}m+- zY){D-EPKjo!)I=(pH@|ud<>P#8)_y_YO1p(+R|9n)a2VTPhDM6J0mqQ&{V2oE|K-#h090O-(~}SxZ$#MN4UUjW+X&cAH|jYpJX$o7hs{+%&DZ zsb!n`+9un6lCxlI@STe9etg%JvUOHgZBt_di1OyfXeryak-9&MHYJzY7P4>LzC2Qz zH_Wt6x}|=bs)p*?`WeCh$x$+c>}Yhv@~xR>dqKG|&Gtj7JK}IzG@3%mz3YhNk}gkK zs=j91`W$U2DG%Ekv}M^+HM63ssxsxZYDwCzxv9){EmNwtZK*D+@!bQR(-b};v#!-Q zH`pE9IIC-GD%uVgq29h1OfK`%5y?G+?IWTs*EZa_s}?U_lbmb|h5 z+6x#d;;-2(sHu(?O4NffDbEt_uzcnCt}#3es+aAAV{g$?R#DO1P*$ORU$Q@w>;O5V z%wA|y&D1JeOW{1mCD(FA$`ekrb=25UVTaPPil&-vqJ!0#lw%}YvmMnZ)`ds(P=%2; ziQg$}cT`B-rL^tpN~@A<&hI9>DG_Yl+s>g`$4TpE+XVKcc8Ex&PZhN+< z*iYBiH)`u2mwZB74bc)T=T23)!dEPuzod0;v0XJi4^~vw);8CcHJIcRYZ}dGKgRJwu!@~U)W;HQ9=^nOd;8|b z^6)s{(m2UZYN9D^Kgb?2fQTl-4y(b`>i5a{uE2vCW{`%KC7Znmqn!ZAUA|b~jq7rKLK~ z*>OKPZ?^i9mdfc(EtQj^Lx218gfS`8YmYV6_DRhR;Snv|D^}a0X`Ga@KgQzPvTgmW zQ-^B1XFIETtCq|u88tFUO{3J?c9JG-UvHVS{!`AIYi(<2Gk|BGST=QPS=+OllXhCh z;;?NteA2e<<*kcaXRl}-Ts(B~oMo#f z%vrj8W$PY87mpliVC8~Ui+8pnjD za~4dn>%*(Z4P88Jv0Y)_bnc2}o6cKSJam5X(E1U@L+!fbggMrMq4O5Eu2?a9e(TUh ztxM*wTri=;P_&f|^_`3*UzRHuE?qKogk`}XwnBP)7@Mv!K z(o&X9N&`Q)wB1!GMmTBP*fBZi9izEK!#$og+L2dHot83&tMID|sfP{kcj^#y(hR$B zQ8C5#oY5<4x8bk>_}NNw*#T3>*Z;#vuDYhWzWp$>&7sP&its&*c1N4!PWRtih>f~! zp-pO?J-2mvOKt0tU{~K(l0AzSKyzK$Hnu7FfI9g|%JMC1w&A*+o23rV{d|h07^yVT zhC0#7P4a=zUq6AZuk(FHc*HLKA0O40WMe3&lH_LH`GnEH56T73T+A3MEjwh z`p<4nC425N6}1DY1AVd)rw!|BDr&;R z)3h=>I)zi&F($fW+j6_fBabR3*+{smHk`x;!pYesx2@_KEzNeN%oe6*sQKA-GM1q2 zWOUcZa_VKQ$~ji1lhb%vISWi`>&L9;M98H>us6V0`4rz$Q# zXFsVYxyfrpBe+K7BSID%GxM{RV3%-L>0R^z8Iz=r9_-p{O@-}I>}b#wF16%TjW+DH z%LKX4D8v7$H}ET4cV0C=T%ta>qm#a2mX$}QMc1c!gjZN?V>TP!wp7=aHMX_m z(dKFHxnDQn())TttK_<=sIF*RFQtA3oM+P2km%?duIT9Uz28l}3LcLA*4vA;oqtwV z{g*RPU%}f}H3i|&-RH?Du>J19eYUflD!Zm(mu7XoXH%E@b?vZM(bf8?WiwkU>Y8)_ zO1)Se_V3?E)@YQ*i%nkC3uoDO)w|R#rKN6NZP$PN6-Qe_yZupel<#v)F3VKulEY*z z;P8TU__XZQ+YV>Z)n$LsM}*--eyNpShX-gAz~rs4ZS6n5_Yqx6ZaX;rYtK{aV~TLz zep!}zr*^rzrq<5qQZFF1ozXNlR_INjcFO^SG14xj>g-}^bhaOs5z#@jU6<%Ua?hPy zU@7}DA4xJHPZ8OkJeG#9DD_HcD8hd_6h}MeXv5I0W}9$<+hP3Qa`AF(?`MZ94F&Y(4Wp~E?Hba;&TP%|N;^+UIf3E9 zE7u;MorLKNPv^*FN`9*!7Z#2qaPUUtb z+TNfG-#iH)_OT8Rrkp~wyY>=xuT;kz9|?uPuY87gqN}rhm$6T2>P1h@)z3GpZR6mg z6HgkwHuf&s98<2JwjZ%@))PLlt$<|T!>!N`Url8Vewt`oik*`Dx2-Yd@~vJ~X>{$? zXB&;d=$>8u*I7+?#=#o^;q#~Lr=@jt8kD?*Y1=gCGTKq{hG1!QC)}GI|?LDrxQ9|jcI5-^TA4T48`;Nu|7PA{igw~yW{dP2J^X8>ou0z)vtdoi|9IN%4Y_mfkU`( zQcpm`5#9`YAK2dsuh(0}c0(>6eN8@ER?>wri(;6*4&~Z`OpPy@?Gzwq9@H zw;Nx&ZQ)kpBOhi$*DA^?Y&}%Bgr^6AKRus{U@+v~*%qtovC&nUaCWKVph&Hha~B_f zMY}e?&gcs-+MV$H;eMj=zrFdXM6E&Yf%TlQ1F7sYzSdd7OiddK>t^^e(?vHo>SMd`u!|D;Y3 zPx-XJ^SC~|&opuW2z1IVZXbWPug|31(gXWyoj24idfdM`5Z$83UrK%(AbBTzI3Cz{ zXHstQ*c-I%LlHP+rEnt%|H3w3Y*TKkB^#1 zpVAn(G8i~lN4x*F`)z+@{10!ircO|ra_B6vcQV=@D;YH^h_2_ivGA%*@)}P2clZ1~ z4ZEFXf1T_LTlU@Cu=cctYhRbLZ}nQWuL#+9&4Nz$WuM8)^Yr*0%KojwPWI)a!@Syj zwzQAbd%e%A&F4MU4(42%eSy=zsnW^5D*B06n{JdT=hIbtwdb4c)xM`PS9u?=_TLF! zpn8|8o0(?1`F5RV3*JrgYO@Thbty=*jiH}c({7NsZ?8Vx7}W`?<*L(En^oti+IP0Y zcDt$Wt9p>?ajNI5-l%%J>bxT&YF}IqpZ8nUpH=@*^)KZ3>+xUC z_iA4}4r>=x|AjQ?eO3Ltx}G;xwJ#xtd93OL)e2Sr9@Z^sP3nFsOmAQC##;NdZFqSs@JRDrh2dHBdSlUzNGr5>IbTy ztA3~YtLopX3ENNka>`ciqS{lnpXwmh;i_X)C#Y7cPEl=8-Bxv$>U`BDs;gAjsvf9% zgzE9Cr>UN+dWq`Qs{S=Xe;s$KKA`%z>T{~Es=lN8vFcZkLc9jZD;bt_dr5AgX+SKUr^j_M-SRjT`_9;$kr>glQ%s9vdhlj_~7kElMY`kLzd zs$Z!7sQRaB!VXy8&s^0))ne7bsv}f4SFKc?s=AG8i|PW^-BkBfJy7*1)st1vQN2|4 zI@Q}%A5eW#^(ED}RX)YC-sZ+`KoUWi1MeZ#T!L=sOmgB!SMO5P`zrCDBrI7!;mQdqdLw`M11-x)qP5% ze5C3_BcuGhY9~8k@#zayr`Z6;^Ny;gY!>AURo~ho%Ac$D-zv((RTq>+d6nul6;ZxZ z^{1*R$Eu^cnT^N%`RwCJVclH%}2e5~qYtxw*)pff^Ik87nx7;(TQ&bOH z8|C9wpV%kLud3$lALR{Hw>dD%b5zedILeo+esE}%zf~P{M3hIXE;%a7d#T=ZOqB0e z{r$KoXC5Ebtxt^VRMkUHj`E4BPn{a&*HsJ7h;m=mnP)}0RrQ>6qI{+5N9RTPd(}-Y zjPh93WfwSr%R`DfK(FGqQE)s?SCd4JVAUXSvls=-@P z&QYy?C(4bgN4*#2(^X&iAjtQO;MLoEPO8s>j)HO8N9> ztG;4CF6H?{)!z0iQ=SK_?rZ}=&r4M=v)`Tae6#8|_5)O&|4p@UilDUbF2-%T#|8Pahib4yrj` zZGJ_{y;b{(4^b{r9WB1Ka;0jGc$4x>)g8rmQQckjAl2hl&r!Wn^)}UqRbNnjSM@8e z_Imr;#Xzr3stZ)lP`yy~71b|PH?Uti@^%}kZl`*z>IJGdtKOsfy=uZP=y?0_s^zMy zRj*WiS2foz5cqN~Q0=AKS9Or;5Y^GD<5kO5t5xe&8&!8uou#@^b+KxPz_vTO2Vcu8uKvg?jhWr@SlT}Yw zwZldD_^qn(i<)slKNAt?G}ezpL7ACv2Ayi)ts;eARBMwz-AVnPy=f ztvX(Hx@xoPj;i5x99upMlozS4RQ2n9zWg%0ADyCWou2*X)rNIp{U9x>T|MX9_9-3= zTd`*G%Go z8{406FaN9QeA`(6d3_ws&DW*hd|T>he_Pw1-`1KGw^_9zR=B=>I)A>I_D3J=Zm`zo zwc55{Zrp1!kUGCni|t1b%@LoUd&T_b+I`yC-Qb5YvEbVjz}?mBP51t|Sa==U+xU&? zmfQW*=k0A5BagEO{dt}9ya%VWvAe;-&0;~Z-_ecv?Qc1Cepl@m3$OkA{A@UzoZo47 zpEhjr-uYYbs;G!hz9!|JNV$zx!30u5e*2m~4z2)7hzJI6Zu>O;<~>>d))9 zC+sh^e=qIVw)}kmPXFGt`{wd8E8*=ro8M*xtNy%x^UAj3`74|5J%fIX=xTpHKVR*C9$zzl@@A9%`StIAuJ2d>Q(48h$q%ec&mUX!z`Bd_8fU$*F1<9^^p7_N zEJz>vz`CGx&I14U!tmb@!+%R(zo`0_>hyt|OnGsgouCf-tzdHF zg6*x<3-;{k6ROv3SmO6GzC1XwtMxG`y)yjw%US+9?*44q)*YsFoZPXdlfSNeyLEf; zq%)t{>%`}$?mzd^3ock2(hdu!jD?R+!xDm_+c zD>(a7+xhrK_|#ikEaL*(Fw&lhBD_-9A=58xr>7_UGudhBna|rK@n)MKKBP;T-@m|~I$qM%cXf$l zy?rd>kxc(xIuDuY=^G`kwkbN4mjvk>>wnJZYq2y)AEemF;)o!9u;K<5M+WJeDE78E zDoEc{v6scsLHZEIo)*Uh=|dHJSR5Oq4^u3%I4(#Zu2^Vsy!{TQVt0$B)~!a=vHl+Zg3M&(^uI%AGx1@5U+TdbaM3SI+Tl{o71A z+wutO-{#6$o~?gdD0lK~{hOfN(X;h$OXUupt$$l7XL`2&ZLOT)+4@(eobYV@D_2hU zZ2hZHws*tJM_B(VmD4PbwEk5o+dj8^r1h^_+17u@^z?!8XKnp=I>9a4F#NwCI!!k} z(kEtydm=MrO5#})Iy9tKO=ZYbMHy13C`0NMWymx|88Tf_hBPS3kVZur(xfOuniVl* z8)Xccp^PCjl`&*nWenL)8AG;L#*iJ9F=R(&4B1H;Lt2zEWR^09%vQ#bos}_UjxvVK zRmPB3Wel08j3M)tF=T-7;=Czh8(DjAqOdA$id1Oa)>g99IA{Vhbd#o;mR0t zgffO4sf-~=}RL+{B7Ly<1^hHH{|3* z7dsY)hMc0NGUQZ68FHGU3^`pqJ^lriK|WemAY8AC2t#*izNG2}{R47o}fL#|fFkZY7NFC_^4llpzl)%8-W?G2~%o40%KuLmpMe zkjIoUaz=r<5_|X=My~Mj1n%RmPC#lriLaWej;i8AD!F#*mkkG2~@s z40%NvLta(Jkk^zkTmPN9+v#rl?U5l{_&Ld&nQo5nL*7lyu)$|& z$a`ukL*7@EAs;BpkPj7Q$VZAYqKTlriL6WeoXF8AHBT#*iPBG2};O4EaeJLw;7qkYAKBFU@gThh~Gi8Jkj zLXMAS5;3*zYuQeFGst}`+i7_wc>~LKTHb-&+p?XOcO>_+Y^UX&$UQCFX?Yg8hh;l0 z&n6dHw$t()a-n5AEzc!)x9sDZ&VX(XtcQ7kt`4k=`G77Ctd9kN0teQ~E`WRo*2}Jd zJO|dzZh+1Xte@QhxelzOg@7Cf*3%+DwgDgE^Z;Zzu%7k=baG%l?FH!Qz9{Q+qPe5^A75OZKX9SAT%a?|ZM zI^*}5AX!)X=}9~mSv1(sW;cvwx?XP4;8@~)yW|pDv7mPI4TvS=h3i$(#kXfyze#sIKrEC7qf0kCL10E;#QVA19PEZPEqMH2v6 zv?TzGwgO<$)&MLj17J}(0E;RBSX2qXqACCuRRgeSA^?jf0kEhB5LvWwES^zd7Cr9b z43b5UxKfj2neLZcR2NHZY!~}Ni|T1Fi>8rf(R8vbY9Py^MzSnwBFmy?vMkz$EQ@B4 zWzkGB7Htc_qU``!v^@Zeb^u_}jsPs$34lc{04$mXz@pgzEZP}>MRNdHG#7wHtpF^V z2f(8F04!Pnz@mi!EZPNtMY{s9Xb}L576Y(o2_UklHWsfnL9%YLm_Ah&Epnxn#xmV6 zw`fHyvDhw?hZe1*y)0TqmPM<{vS@d*EZT!Ci`I~3(Vk>kv=>84h3M*VE`;T9Dqef0I=vt02Unuz@no8 zSab{ki;e|g(QyDQIv#*UCjhYML_lQGZn5|YCP-Fa8)>I6mqk~Ewg zMVA1u=u!X{T?W9S%K=z)1pte#1Yprs04%y1fJN5;u;^L<7F`FxqU!-zbOQj3ZUkV_ zO#m#q8GuE%0I=v*02bW_h%7oK7JtnI$*S>7zo*KgC2rB}u}t^NExJ3F_^qcbx`+0% z=w7lcx{oZ2?kCHl2gtJML9#4*h%Ad9Cd;Bn$g=2BG8R1sz@o0E@l>V9~b#Ecy`S9{?5wX~|K3 zG)9X7uqX`>S@d2kKGy`v+SlGVO@Ch&edzn5cv`0WH@%`t^h3R2Ed~304yp5U{MhOi+TXC zs3!o6dI7MgHvo$^0ANuc02cKHU{Nsui~0eus6POU1^}>VAOMRt1h6mK2!KT!10stO zY4IyekgQ|lYn2 zl|?x|(w~}^>3+FI)6)|917%SI?PXCTSr#>sWl=L(7Hvb8MKj2iK1TmTle0X48Wo#04!Pxz@lXUEZPkaSyZ1EA7g@K?c@8RX|iapAJLYlWx8K( z(dx9sjE!W`?zERhdyr+(8nP_flPrt&BFmz+WLdN~Sr+X>mPPxLWzl|QEZQG{MF#+| z=s*A#9R$Flg8^7{2mp%?1z^!(04zEjfJH|Du;@qt799n^qN4#=bPNECjs;-RaR4kj z9)LwB0I=vp02ZADz@n1@Sab>?vS?*me60zRwb~D2t7OrQzArj8Ez|vSi_T0-oIOYu zoke?DbT(NQokNyI=aOa7d1P61K3NuBK$b-pl4a3FWLb1E8H+9fV9})jEV>MUMVAAx z=n4Q9T?xRVs{mMZH2{mQ0btR!04%x=fJN5>u;>N=7TpNIqMHC%bTa^pZUJD?tpF^# z4S+?r1F+~002bW|h%7oiE&hNBl66MR#5qG2ZRh) zSoAyqi(UX=(Te~qdI^9GkQ z0a&ySfJMInu;_OH7X1OhqCWvx^cMh&{sv&tKL9MU&mo^_tI^(3w@WqtZfp#IMQH#m ziUY7H9e_m%KxEN}Y4JJ}Bx{!Mi$0P?zkA4tXS!c*QKxuf>2O(;MSEG4O_oJDWLcC; zmPMV(vM7%%i}J~`sDLbsx{zg2S27lL17J~i02UPju&4-tMLhsm)DwV3y#QF$8-PU{ z0I;YJ0E_wpu&5Y-Mg0I+)E|IF0{~bw5P(G+0PEp18SG7M0Lm7L}4^(Fn3E8cCK#qsX#oG+7pn zASTq@cMNja-3N43<)g0gJ?!jEl1Z5f zy@;WRv@|*h(wl;Gq-hKxbOY4MfF)6$P;?>ixd# z_etXa+;i``Yn`<&YvIoOWcH-YkIAG6DC$M<6{WiF2?Hc#|DKYlG$}e~?~8i7LF>yZ z>hF4gHkP6RoG(QK*-~^hTZ#s;rD!l)iiWVIXee8XhOwpS8nzT&%SKTa0Y%plP?SwT z(QpEaatJ6IK|oP10YxJTC>ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}q$|Im?5&=b% z2`I`Zps0X=qC$eNsITj$G%*nl44NEvYqb(E759*16uo7E-jH^QCA5TZ%TarDzjdiZ-*QXbW44wz8$@ zKDHFy&z7QXY!p2}K+%H)6g@;h(RKog9wwk@2LVMp2`Jh{K+z)v6g^5n(PIP@Jx)N; z69g1JNkGwV0*dw!Q1lc5MNbn@^b7$-dkH9dmVlz?2)?4VuDjg;2{pHh?vdOgO|(YI_VI>VNt@7PlGJzI*-vZd%8TZ(>QOVN2Yihd-Z=qCb-ekP#k7XpfY zC7|dx0*Zbopy&?*ivA>^=mG&ne-TjhHvvWe5Kv@(zT5w_9Yp~GipmgB~9 zKv6USML`0JVhFyXFI=~U0TOCvzg+#L6xqLeH7YhLXnk2l2~pnQwo;VH`BId`mZC6Q ziXv<&N@hz@S+*3FV@pwawiH!hOHoBOiYgIMRGEOHDg+c&C7`Gp0Yw)PP*k0OqKgSA zN+F=A1_4Di2`H*XKv8W1iY_6bs15-|ml9A^mw=*r1QgXLpr`=>MGXlkN+tM;LQ(Eb z21sb3y)TN7@;}qJf01TXT2#>bvWgl-dF$ItQDe@Rq9$x9YRZO(+LUxKeFBg#E!fQ06n8I>tTU)cMi zeo;Z|%PP7$$~)ariUx7M6b)ue(Ga#24P{HwFt!w3!ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}q$|Im?5&=b%2`I`Z zps0X=qCx_SrVvmxm4KpY1YgmBC^xQ?QS^uXs^dT@8fWi|rbh*>FRN%~l-Hn(6y3=A zQgjnrie|B;Xf|7l=CGycX0{Z~WlPaKwiL~0OVI*0iWU-3w1|MBTL>sxOhD1C1QabH zpy)ONif$*MXej|j%Lpi1PC(He1Qe|xpy*BlidGU(w2FYDy9g*+O+eAz1Qe|ypy(a~ ziq;Z*Mb}5Uy$z61HT!edH%O6d{)gA7d!vHZmsPYe%A4FxiZ*e+6m4cp(H6E8ZDmW* zeQYVZpDjh(*i!TWTZ$fJOVLAY6m2J<=wSkib`VgslYpXK1Qb0&K+&TF6g@^j(c=UZ zJwZUxlLQp)CZK2!0Yy&{Q1mnbMb8jWw3mRQX9*~Jj)0=)2`Jh}K+%4JuV{UgyUG9w z9kcgE8>Hw4`w{JhsG#*_6}=SY?Y=^a4spH|9cD|>%WNrng)K#|vZd%XwiLb2mZCS< zQuHQUijJ^Rbd-Riw+JXYMnKWq1QfkPK+(Gd6un14(fb4x9VejZ1OY`K5KwfIfT9lx zDEf$iqK^qEIz>RyCj=CINF0{hRlqUX-F!_A~u2 zqk`6#RrGC?_m}xA)QY}dbcXY#=sUI)eb1Jnvur6k$CjcW*iv+!Ek!@FrRXQN6#dLb z(JurP{YpU5Zv+(mPC(Hg1Qh*AK+y#PivA*?=x+jw{vn{q@$_jsiUI@_l_8+WC7>vZ zfFh58qG$q&f&>)B5Kt6LKv5h4MInN(=<6uAW>2GNo&AXRjT9x=k7)5;(E759!k*W$ zmlQ=fUy731QdE{LMdjF1RGuwG71&Z#ku61)*iuxPEk#w>D5^?8Q8faJE+U|)Isru& z6Ht^wKv4|>ifR&2REvP3+5{9`LO@X+0*Wprpr|eZMfC_Ms!u>s0|JT~5>S*%Kv5b2 zMd<_-We|KtiJm*!015TAKX;wv`Jd_kYJb=$(+gT(R#8*WyQPm5HRF6KYR;CT7HlbM z$(Ev4Y$>{oEk&)_Qq+bmMVGUss4W{s?FcApPe4%z0*X2kP}GTlqRs>qbs?arD*;8_ z2q@}KK+zQh6kSO`Q4a!&dJ<4{6#+%P2q@}JKv5q8iuw{z)Q^Co{sa^aAoz+Jd+rVc zB-B2}z-b~y&)G513tC@R(Gbsjv!4_V<$Ng`#+IUM*iv*YTZ*#SQgj_#in7^KG@LC( zIczB!!A4Oo0YxJTC>ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}q$|Im?5&=b%2`I`Z zps0X=qCx_SrVvmxm4KpY1QbmtplAjGMb{I2MT0!|Cj%t(jeRIIScx2q;=kK+zop6s;hj=uQHPRuWLOih!cK2q;=jK+)X<6s;kk=pF)! z))G*3F9AjC2q;=l@D<(YxvdP4&>;J1*-cV(&fXVo@PgKtRkX$Ph7OXVt(-4K_pznu zezp{CV@uHkY$EkzHprD!`_iXLW5(GE6>b`nsui-4j>2q=1#fTG6;D0-ZLq9+I_ zdXj*m-2@cvA)x3f0*am{py(L_iuMvv^eh2I&k<1cJOM@f2q@Z5K+y{X6dfR-=peyY zw8?X48z7-V`%q}J6df|pi+a%uT3=St%bvG!h!nlT`BL;MTZ&#|OVR6WDSCq~MQ^gD z=m=YijW7og$#<69S4pC7|dt0*XE-py)IKMPCq5^d$jBUlCCBHNjVO$a7yZKthT3zUZ(N zeP>C1;{~lRtLS^r`*N5Ro#lKfI>(lxAJ|fKo-IW`vZd%JwiNx$mZD$SQuHfZihg6G z=yw8&{ve>}PXdZA5K#0N0Y!fkQ1lN0MNYInZAVdnfTA)46uATxMG;Ws5l|FOKv9r@ zq8I{-VhJdUBcLcmKv6saMF|8HB@%o^XFNCl8l%X5-!q9sKKtuL#nY_yk} zB}L^pUy91JrKkd1iYl_Ds1jR>Dzl}i3R{Y*vZbgRTZ%4Xqo_IoMHdrLltMsJ4FZa4 z5>Ql&fTG$26kS3ygKv4q%iW(A7luAHR8UaP=1QcZuP?SkP zQ6mD18WVg)k!ZKC0TMcIA6+L$`=99#v7h!gi4Iy{R#A&+uOM5BT5`S=wPH)rWo#*G z&6c7zY$>{&Ek$kFQq+zuMeW&A)Paqnjsz5SBA}=<0YzO1DC$Z;Q8xmLx)V@z1p!4@ z5>V8GfTErR6kSC?Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CV)dUm`BKV4$MZ2pF zkdXb?Wuux)(Qf&q&-Cfa){M~bfHd@0IeOVM>~DavL`(QvjD<*=n_1Y3%7 z*-|u;Ek&c)C>l*b(HH`X#u898j)0=^1QbmmplBiiMR^1iO(LLZG66;T1QZnzP*g}j z(G&uTrV>yzjew%*1Qg96py+x6if$mFXeI$gHxhhBL!;e~43N+%`}0M^q{#jQR8coY z2dyuw=;mnepIj-L%lT3?k1a*>*;2HCEkz62QnZLIMYph}Xfa!gZe>f+5;lr%BcSMZ z0*aOrP_&GIqU8h>-9bRn3IdAmB%o*|0Y$3_D7uS)qSXWx-AzEz8Ul*$A)sh20Y&!` zP_&MKqV)t6Z6Kg%BLPL52)?4((QfULMv?s&r=#XbQTd`z*rJ2hmsNCswAXpG6m8>t zDSCh{MGvy2=pnWgZD&i-!)z(q!Iq+(Y$@8smZC@4D0-BDqQ?j*dYpiwCkQBdl7OP! z1QhKdpy(+Aik>E*=otcv_7YI^ECEH&5m59z0Y&==DB4dz(F+6=9U!3SAOS@$5>WIK z0Y!%hzM`$s?pOmPRNX$HzE6r4+Ha~Ijt*L1R?%zG-mPP$=ylGQqBq!5^d?)1jWIR0Y#q^P;{DrqAv(2`jUX6uLvmmnt-Bj2q^lNfTA-5U(qYk?k)o) zlw==JzbZv->_@ckqJ!3#RrEu&cXYfIo#%Wh`jIU~Ke46gXSNjm!j__6*;4cyTZ(>X zOVJ-}Df*L*q6-8R{Y600-vku>LqL%e)Tiwz3J_3KhJYfMfTAb@iaY{}q6sJp5>OOF zKv66KMR5cag$O8$C!i>SfTBbKijoK@3KLKiA^3{UM!UZlAfdDN?&q8oZLyE8lY>F) z%POi6^eW~_QAN&|qDpKjs?3(6Dr_mL%9f&PY$>{kEk)JYQgks}ic;7pszE?eO#+H) z5l~c{fTBwXD5^t1(WL|w)g_>)9sx!52`FknKv6>iic$$EN+X~soq(bY0*W#TC~8DN zQDXv%nh;Rblz^gU1Yc3PpxfF22~D@3>6Z`spXqnAcTCNLLF>yZx-95jGg*pSbG{U{ zVN22FY$d2O&PHZXa%tlcc0*bm4P}GfpqV5C~T|q$6l>`*^ zAfTux0Yz64P}GZnqTU1)^&z0BF9AjU2q@}LK+ymKiUtx;bTt7*g9s=ZOhC~P0*Zzb zd_^sT?#%{B=p!?uT1n9wdtWpx7_`2uqU(a*<^n0o=6op{&X%GawiJzEOHnRcibk@f zXcSwDMzf`83|orEvQadSfTHmP6ipzYXd(ecc?1+qBA{q80Y&))6crFqR7gP46atE- z5>PaafTHOH6wM%@=z0Q*ZXlp&CILk^5>Rv#0Y$S2D4I?16ML^MN0*dY?plA&NMfVU;w3dLPdkH97M?lef z0*W>eP_&VNqD=%8Z6=^-3jsx23BIDaK{s)#QMA#_sCiO!-hT1uzF^S$vWgxIdg;@p z=poLRqU~%cdYCOmJJ?dRlPyKN*i!TeTZ$fKOVML&DSDiZq9+I_dXj*m-2@cvA)x3f z0*am{py(L_iuMvv^eh2I&k<1cJOM@f2q@Z5K+y{X6dfR-=pX?_FA`An5&=br2q-#C zK+($t6um<56>ST;{SA=N5&QqfJ|IQY?0wOz!JzeJ6}=hsrd%&YM>t=KjWIZ0Yx7XQ1meYMW+ZT`hX0*byPpy+!7ip~;zMXv|l zH3mrNYWq;=4JrD{-WQz<2CXlv=%=9f%uFfzne(OS7q%4r%9f(v*i!U6TZ;Z*OVOWf zDZ0RxqQBTu^fwzt{}52*#OTv@6a@$7JKtNF<0Yym!6om;WiV#qgOh8dt0*cBJd`0Jj?kNK#beH|AtwiI2&mZIuxDY}>~MJa44s==0`nrtbm#YRzW0*Wpn zpr{T3MVAs#RF{CFdIS{JC!nYS0Ywc7C`u)uD2;%kbOMSp2q?-Vpr{c6MU4q4YC=F! zQv!;b5m3~efT9)z6tyJyiYmsqbqtWuVEaR|m16wQ^qbm`Xsu#`)|XXud5qU}juf@! zd?{+jmZJ7-DeAzMqK<4S>cp0!&TJ{_!j_`0Y$@u-Mp1VHimo7_=t=^LdJs_5lYpYD z2q@}BKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|D7u<}qCo@{4JM#y2mwVy2`CyyK+!b> z6kSX36}66W#~UD_p%zXXDZ1I-7iGl+tuL!6C&s&Nt`v>nd@0IhOVLQS6pdm_(P*|5 zjbTgCShf_6V@uI^wiHcZqi7-lMR^1iO(LLZG66;T1QZnzP*g}j(G&uTrV>yzjew%* z1Qg96py+x6if$mFXeI$gHxf{E69GlD2q>COK+zlmif$&LXfDB5lpW(fYJh|;w-1Ge zOHl($YF{f zjiMC<6x~Tc(Mke}RuNEi7Xd}92`IXofTA@76x~BW(OLqE?j@jT9RWq_2`Jh?K+#45 ziZ&5Yw3&dSEd&&8C7|d&0*dY@plBPxSF|9;{mlRg?Fkq-3#DkVCG|i|(E7599**%U zFOs4ioG(Q?*;2HNEk%#8rRY(%6g|e4qQ}`%^aNXqo@7hWZZ?Yc5K#0K0Yy&}Q1lD| zMSBS-dX|8q=Ljfzo`9l#1QhKjpy&kxiVhG^bdZ3e7YQhOiGZR*1QZ=6py*`+ie4e0 z=v4xWUL&CBb%L+xp&0ja10-~nnNi!ND8_z7dm|=jeOX0s#dukZrRW&vOVQhGDSC%3 zMenku=smU+z0a1S<7_E9!Iq*A*iv+ojiL_;DEf$iqK^qEIz>RyCj=CIN0Mcj&WZxKtiMJ-On#l^tb&I zWTn`k^<@=Ri}k*}U5YN^d?~8VmZFQzn3T5Kt*&6c7|*iux7jiO5l zD5^_9Q9S~R>Jw1ZfPkWg1QewbP?SbMQ91!d83Yt%5>V8LfTG3(6g45Bs3`$O%?K!J zPC!u$0*YD^P}GWmqRR*duy;E7($WB^yOO2q@}FK+#nM6!jvYs5b#c zeF!M(OF&US0*d+*P&9ymqJabyT}?pIAOea86HqjSfTE!U6b&Pw=o$iwt|g!-i-4l* z2q?-X_=?)bx&sZ6P%nF5)J}?e6@9`M8??TxqLH!Qv=ve`iu0vtG+TJa?pgyRlxFXK za;4}B`@=>HV}sV0Rdj2t_v}h3TEh8KbQ@cWZf8r;QnnN=V@uI;wiMmLmZBAGDY}y_ zMJw4TT17z7T?7=ZCZOnU0*clUP;?IgMQaHtx|e{Wbp#ZxC!lBp0Yw`LDB46o(PjdQ zwh&OXm4KrA2q?OrfTC>#6g@yd(SrmOJw)&o-4g45YJh|~n;ErOin`iQ`?tpituL!+ zSFGo*mZC>EUy2@OOVML&DSDhOMNhD$=t;H|?Pg2S9<~%c#g?L{*(iF3fTFzw6g^8o z(Q^b8Jx@ThI~p6bzO15mV!iHbr08AFm!kLB zQuIDsijK3T=mcAeK444HNwySy$d;my*i!T{8%3uGDEfqeqE87Z`iy|0&j~0xO+e8X z1QdNqK+#tO6n#xV(KiGXeM>;m83KyFBcSMe0*cNOP;`!fq8|t-I!{2+j|3F`L_pEc z1YgmySa+fU66#^$ye&niW6by^HfViWMSsM4OV>)#pPVm67uZtt7h8({W=qjOY$iYA~aNI+2x0Y$L{6vYux6e6G~o`9kR0*Vp|C`uxr zC`>?6gn*)C0*cBKP*je9qVfb3RUn|KA^}B}2q>ydKv5Nfujsc}_i+Ox)ZIQV`dy0J zcxF_M3tC@R(ZzAzJL{w_z5dTbQc zC!nYS0Ywc7C`u)uD2;%kbOMSp2q?-Vpr{c6MU4q4YC=F!Qv!;b5m3~efT9)z6tyIv zs1*T4ml06Znt-A<1QcCPKv7$QujryU_YVUk^oPCssUGKlrhmeYc5y-L%PQ&==T+S( zMV&ccin_3+s4H8Fy0N9GJ6npbU`x@JY$@u&mZF|)DY}Y{qFw|P^(LUG4*^Ae2`K7E zKv91JiUtr+G?0Lzs|hF?L_pDC0*ZzZP&AZ)qG1FST|+?8wFDGp5m0m;0Y%va6b&b! zD2ITe5d>dRhd8&L0TQx*Q&Ch$DSE(;+_<3iWfhHy^RhQf(OAxxqH$~~8qb!Z32Z5v z$d;l!wiHcbOVMPu6y>v}sDO>4LIR4W5KuIgfTC#x6ip|fXa)gA*Aq~50|7-d2`IXe zfTEiSD4In;(QE>W<`7VHGXX_&2`HLJK+${xiWU%1w2*+JMFbSxLhu!higOnjAfco7 z?q{?Vy<{IGEshIXUsloWao+t~rD!SVOVKj66fI{<(H(3lTEUj0JK0jSk}XB6*iv*C zTZ&e*QFJ!}MQaEsx`%+GwFDI1OF+>&0*clXP_%)7qKyO;Z6cs(GXX_g2q@Z0K+$~! z6x~li(KZ5#9w4CTK>~^%BA{qH0YwiJP_%>KD_RogzGi@gZn9r!yiJNy>}UEr2B(GzSbdXgyZdOyx<{Gb#a=X@zT z!Iq*A*iv+oEkz%)rRXEJ6n)H=qEl=s`h+b-pR!T(839F~6Hs)TfTAx5DEg9sqOS-j z`kH{EZwM&*mVlx&1QdNoK+*RE6rClY=o|q>KM+uKo`9ks2`KuBfTEuXDEftfqF)Ip z`i7JKtNF<0Yym!6om;WiV#qg zOh8dt0*cBJP*k3Pq6!2QRV1LO5&=b(2`H*UKv7i!imDM%bP>T<^kyZsu}X0-yub{IA4ltv!&<~wiMN2OVOolDXPnsqIzs8s?V0925c#6 z$VO2r0Yzy96r~eTltDmICILl_2qV8RfTH#U6m=l@ic&)E=LSgV75m-T8X^BP{m1NmQO8iw`m&0; zhCJ^PDeA`gQq-L-MOUz;=t{N}^4E{Rt=< zKtRzz0*bCCplA>QMS}?_8bUzPPy&jE5m0mu0Y%pmP?SYL(RBnAWfM>|oPeSn0*Xcu zP?SqR(MSS{MiG2PokMPY10)n@zXQ@mif%Q}iy9pYT3=St_>gzyV^TDM^QCAaTZ;17 zQZ$JzMU&Z5l+Tu;0=5(tvZZJWTZ*Q#Q8bN!qUi(_%^;xYdIE}WAfRX_0Yx_wP;?Uk zMY9MfnoU5_90H1NCZK380Y&o&D4I_|(Ea zMR&8MXboG6?qQ>7EdfRM5>T{`fTHyT6m1}&Xd?kdn+Pb{OhC~V0*ba0P;?&wMfVd> zw2gqG2M8#7kbt6x2q@Z4K+(el6zw3OXeR+hy9g+Hgy1V$8gidBKtd<%cR-d&(P;Y- z?a@%s`m&0i40-SEmZII9FGYLUQuGvCik@am(KBo*+RK)rXW3Hp99xQ>XG_sOHj4HW zQ1k);MF$8dI!Hj#iv$$CL_pCY0*Ve3Q1mhZMXwN0^eO>GuMtr6Isrv*5K#0c0Yyg$ zC^||&(OU!*9V4LVZ32qkA)x48g0JZDkbA)Z3AM0ro{*xI_P*%7P|*6aiarQ=7dF9|66ih!c82`Ku8 zfTC{+C^|zx(RTzCeNRBqSptgA5m5940Y&EtDEg6rqMryT`k8>DUkE7rm4Kq(2q^lU zfTBMLDEgD&D>@!>I~X9Llz0Q@gcMz4NnHp9tuL#{iT85$N>LzQpUF#68MYL;Y$=Lj zOOeNxqG+}h1=&&*!Ql* zfTHpQ6jdOgs3HMHl?W)ROh8c;0*a~RJjR+`eOh8c+0*aavP}GcoqUHn?wIHCVB>_dP2q?OYfTGp}6ty9s z=yC#z+7eLIj)0=}1Qc~3pr|7OMV$yJ>P+wz)rxoDFhD{T?R`=0c>go~@pg2H4_aSV z(G~ID*?m%UCFe^~54IHbWJ}RiY$@u+mZIKlDeA+PqP}b?>c^I%{%jNtAfRX<0Yz66 zP&9~uqQL|d4I!XtC;>&o2q?OSfTC*&D9R$B=sE(5vI!^}PC!u(0YxJSD9Rj-E#YlBF}!+vAY!6zi=jMTzt^_vWoKJy`~4GXcFg3(PXw1 z<+G)zfGtIZY$=+;mZGU_DVoNXqUmfYn!!fV^#l~%KtRz<0*Y=Vpy(z7ie?c|G@F2; zIRq5lOhD0G0*dAlP&A)_q6GvLEhM055dlTF5Ky$3fTCLoC|W{5(QO12-A+K!Qi88& zLcBY~010)p52zUXgvW%8we=cNI=mh0*W>hP_%`BqOAlJ-A6#t{R9+kBcSL30*W3a zpy(k2inbF_^e_QMI|wM+NkGvq0*W3Xpy*KoiXJ1N=y8It=#F@Ig8>rCv0rsuAw|F1 z@kD&k`m&0iiud*(lA@fHi`}s zQ1l`JMK2LhbcleW!vqw)OhC~q1QfkWK+$Ui6unMB(HjI5y-7gP5dw;i5>WIO0Y%3M zD0-WKqIU==dY6Er_XsF@pMav{1Ygnac=rnfB$RINe)dRFb@RNa6Y)Xo%PRWF{Cn1~ zNYTffFGZ)=QuGO1iaupa(PwNa`kXCAr`b~U1zU=~WJ}RkY!rP>K+!h@6n#rT(HR1Y zz9XRMdjg8i5>RxGfTAA=C^}C-(T@Za{X{^~&jb|xLO{{41Qh*7K+*366#YR!(Vqkq zT_B+7F9M4GCisd@#=8v-kWfYYRmTsdsIUD@|DX7v^<@>g30}|Fq$n!k-=FDwY$=Ln zOHq(5MKNqCie*bt99xP)Y$=LoOHl$FMTrCyB@s{*CZH%nKv6OQMP&&nDn~$3c>;jRvw7#sOx(VKjH>9W@=j*V8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P}Gg!E2@*=?lC|@^(>rAr6|sRclvX(I^6nMiWpp zhJd261Qd-UplCb+MH2|VqAL^JzYUPkdV62gLyGK|iJ~SZ1g$TtC_llw_?Q$GaK023 zvZZJWTZ*Q#rDz&kil(!rXa-w~u4hZp4Qwfz$wtwQ1QgvwK+!A$ie?i~G>3qqn+YhI zOF+>)0*dAnP_%%6qJ;z$Eh3=k76OVE6Hs(30Yys)D7uY+qT2~5T1r6CG6IU06Hs&q z!B;dX!R=&#gu2)tlASC?E$n^KiiDu`Wfk3(;N`v}MXNbqitc7h(HgcC-NTlmwQMQ6 zmn}u>*iy8fEkzsHQnZncqD=%8Z6=^-3jsx22`IXcfTH^eDB4Cq(E|h&JxD;&Lj)9U zC!pwI0*ZDJP_&bPqFn?OJwiayqXZN^MnKWy1Qb0%K+%%~6zwMXidH7Liw%&_+xDxD ztEA|2`%qHozKIzvFwcLWrD zPe9RG0*cNNQ1k-PyW zr6`6iMX_utiepPrh%H6&Y$-}$OHm?Qijvq;6lS9+LO@Y60YzmAC@M!lQF#K2DiBaq zk$|E~1Qb;!pr{G~MO6tXszyN3MFbR8C!pwJ0*X=yD5^m~QB4AhY7tOWn}DKA2q>yU z@D)WRy2A{R&<+d7OY}d}H;=T&q%?km%j`krXxLd?`w0OHmqIiqhFql);vw zOtus?VoOnDwiGpCOHorcikcBn)SQ5#76cTvB%r7j0Y#S)P}G`$qBaB+T~0tzTLOyO z5m3~gfT9ir6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(qALg}x{}~4s+Z_)GC)E{?N=S^ zOVQ_+RFA}<^<@?HPV^3(lA=DGFGYRXQq+$vMg7@QG=MEd1KCn^HCu`Xv88A*TZ)FT zQ8bi*qG1FST|+?8wFDGp5m0m;0Y%va6b&b!D2ITe5d;+F5>PaffTB?Z6pbdJXbb^G zV+kl4M?led0*WROP&AQ%qC5hMCJ}r^S0%b%86crt`*YX5q-eZ-bUisSXnk2lQxd({ z&!lK7=S$HvwiHcgOVJFr6kX4jq8r#!G?OhwH?pPZCbksKVxwp_0Y!5ND7u+|qPYYV z%_E>_J^@7w2q;=eK+z%sif$pGXfXjrw-Qjagn**k2q?OpfTE=Y6fGm5XgL8zcMwpt zf`Fns2`E}g@D&v#x@iVT=pK7tR47G_?4#>di9zejDq551^*Sv@_i(-xtz}Emy=*C3 z$Cje?Y$@8nmZFVpDcZ!AqRnh6+QLTBRsxFdBcSMh0*bZ~Q1k!+MGq2C^bi3>+X*Oo zn1G@k1QhKgplBBXMUN0r^e6#Ej}cJxH~~dZ5K#0a0Y$qBDB43n(NhEzJx%Zxtxj|c z4Uo_R`&GxgrRcc5FM1|1Xnk2l&nJ2-zm%eVoG(TD*;4cZTZ#^_rRX4Aie6+((MxP8 zI>eTu!)z&fnT?`X2q=1$fTGt3D0-cMqBjUAdXs>nBLoy3C7|dn0*a0iQ1mtdMeh($ z^ezEK?-5Y+J^@9?2`D;2K+y*T6rCiX=tBaEJ|dv#V}h^f*+lng10+<B6n)E^=mG&ne-Tjh zHvvWe5K!bK>C<);1qdiALqL&BKv5LISM+J3>wIGrJ!|27CPmXMDK9B#eOX1ZNnVXJ zQWVGeQWRoKQ9N6U64+9d$d;lcwiJcgQWRlJQ8HVK%Cb>Zj)0=_1Qb;upr|4NMU@CB zs!Tvp6#|N?5>Ql)fTD{CD5_3C(ZvK5r4Ue5gMgx%1QgXGpr|$hMVAmzREL0~O9?2d zOF&UQg0Co;>d*O7G=MEd1KCn^HCu`Xv88A*TZ)FTrD!NyiiWYJ z=o&VPt|g!-i-4l*2q?-XplCP&ML7f%jUb>Xmw=*?1Qd-TplCD!MPmpk8cRUYI0A~s z6HqjPfTD>66y*_6G>L$s$pjST6Hrt@@D=q*a^EsQLizS<*L|g^fxRy(ObS|GR?+k% z@5l2}G=uY{=z6vk-N2TjnQSS#ku60xv88AhTZ(40rDzUYif(43Xf6Ro^9U%KPe9QE z0*V$AP_&4EqFV?kT1-IEtppS;A)x3s0*Y=YplB%pMau{%T24UG9Rw7uAfV_@0*Y1= zP_&AGqPqwvT21g3O-*tu{b&@;v)@OXCPne~)Bd}Yg4UN+bZ?T^@@FYp$N5sUo-IWi z*iy8SEk&EyQnZ;ZMO)ZXw3RJI_pznuem07>5m5910YwiIQ1lQ1McWA|dYFKs9Rw8Z zB%o*)0Y#4xQ1mDPMUN3s^f&=UPY_V_BmqUc2`Jh_K+#hK6g^Eq(K7@T?Iob-S%RYM-WRQvqQ~r)AfHPLT3=St3rXIrU!~{(=S$H+wiLa{mZF!~QgnzdMTgl^ z^fFtDUSUhot86KHjg6w$2`GAlfTA}EC^|ww(NO}5-Xfsr7y(6Z6HxRH0Y&c;Q1l)F zMeh?(bew>q69g1}KtRz+0*XE)py(q4iasWw=oA4(pAb;=DZy8?FUj3vfP}i(Ps{d8 z(R6!X^jT8S`m&0?O!8j*U5dWqd@1^xEk)n3rRZC>6rEv9(RXYq`kpOCXW3G8jx9w$ zuu*iLfTAA>DEf(jqMr#U`h|d^UkNDsjew%x2`Ku5fTBMMD7rvE(O(1<{Y^m8KLivx zVSU<;q5uI!We6y82`GvppvWVjD4KwxAi-C3I?4UU015T>44f~dXq&w+iU|j;FRLg% z?1e5!Q3B^nQ6gK4lGsudW=m0oEk(&}DJsjBqH=60D$kap3TzZrB%r7g0Y#MwD5^q0 zQB?wpsu56h5dlTj2`IXlfT9!vifRy0RFiR;46v?yBP*Z=ya@s6AJsE>A!40yrqVN)|XY38TR`8Ek%tuUy2&DrKky8 zikh;es2N*|nzN;-1zU<*vZbgMTZ%4Yqo_3jMQsQux}1QbwgeQlBcP}~0Yx1MDC$T+ zQ6~b5IulUTg@B^21Qc~6pr|_mMOP3|bR_{rJqRf3NkGw61Qhimpr|(iMSTdqqV%vk z)c^?v?0r#&6b0-@w7%h>^<@a`ov)NKKhb=`nv!!S*TZ-nfrD#4IMGFWh zT1Y_AA_9tTA)sh60Y$eGP_%@AqT2{4x}AWcr34f$BcNzG0Y!HZP_%-8qB{vFT1i0B zDguh`BA{qB0Y!HcP_%}CqI(Fwq8VYgjB6C#ZNJcXy%eprcT8);LF>yZ+7R|?nZFLA z=)Pzp=S$HhwiIn`_QnLI=q1jVqC;#cI?R@$ zm)TPE3R{X^WlPa(Y$RyCj=CINUiX-@nz6!f<8z7-PGo!wiqC4$p z`k_eB`m&0WBHqs-DGGDG6h+ull+2c*vTP|T$CjeY1mZFMmDXPSlqRMO(RUx3L zDgi~+2q?OUfTHRI6kSX}Q3?S?H3%rGNkCC80*Y!AP;?0aMRf=$x|D#Tx&#!}BcP~0 z0Ywc6C~8PRQ7QpNX#^Cd6MRJp5w}XbQS^cRs$*ir|4e_Ay)Vj$1g$Tts7b`TEK!P@ za=sKbV@pwUwiLBsOHoU<6t!YY(PeBYYR#6SHf$-noQPSFQ zCjyE(6HwHJfTFGh6m=t@s5=2gR}fHiB>_b}2q@}FK+#nM6!jvYs5b#ceF!M(OF&US z0*d+*d_|2S?sW!8sI2`Qt+5oD{#+IUM*iv*Y zTZ*#SQgj_#in7^KG@LC(IcyY-AfPChfTEEE6pbRFXfy#uV+bf3OF+>$0*b~HP&9#n zqKO0)_S^fS zK~m(|k7(CNg4UN+bW_ATlq^NFIA4lpv!!SbTZ(RGOVM1m6wPBx(R{WPEnrL0Lbenw zVx#C50*V$BP;@H+MN0@Mx{ZLM+X*OIN_YMJos>x|4vSl>`*6BB1Cl z0*Y1>P;@r|MQaEsx`%+GwFDI1OF+>&g0E<1#64qxgqqm9pBtrUxgF~xLF>yZ+8pr` z%1hA}&X=OCY$>{rEk*aUrDz*liXLD~(SvL$dWbDW+u2g|FdIcX2q@Y~K+!G&iXI`L z=urZS9wVUWaRQ2-AfV_;0*ZDMP_&1DqNfNbdYXWuX9y_TOF+@H1Qb0-K+*FA6zwCR zXg>i(FAz|4fZ!|I7;zgJAffK|r}sBW(I58PAqOKt>&q%S9P#>9l%kh8Uy5E~OVO)r zDSC}9MX$4^=nb|My~&oMBWx);%9f(H*eE(iK+)R-6um=0(Ypi`y+=UN`vepnC!pvA z0Yx7WP;`=jq7Mlu`iOv{j|nI`ML^Lf1QdNrK+$Ie6n#!W(P;vTz969JO9G0%BKV44 zin!AakWfAQKMx&3k$GO!*O8$0WfgrF@$RlHMc;G26rE*D(K)sh{lJ!@^K2>lku60( zv8Cu|wiNxsmZD$TDEf_nqTdN9`h$R?KM5$hKtR!71Qh*EK+!)06gkQIv>inO0*cBI zP~;L&6h%OhM?g_D0YyOqied;TiY1^Zj)0;N0Y&iy6eSRRMc+o;=M0cgy1g$tBSqEi zN3_J`p!H=HB`13ySCyi&oG(S?*iuxUEkzaBQdE&GMU~i6RGBSBRoGHgl`Tcp*eJS) zfTHRI6kSX}Q3?S?H3%rGNkCC80*Y!AP;?0aMRf=$x|D#Tx&#!}BcP~00Ywc6C~8PR zQ7QpNX#^Cd6Ht^vKv5SJ~FEx0g8Yc&>FRQ3|vUf>! zDQdy_Qq+9AwiLBvOHq3^iaHQb)RBOqP6QNnCZMPb z0YzO2DC$N)QFj80t{|Z3N&<>{5Kz>UfTF7iDC$K(QEvi@`Vdgmmw=*v1QhirplARA zMFR;ax|-lCYMSg`VSt1hSUAn3sI0v&8k8KgzO15Q$=CNKv6ycMFj*D6%tT1g@B@|1QbmpplCV)MKcH}x}Jcd8we&q&dlk7cGQ;Kfpd?}jCmZEuVDVoogq6KUzTF927MQka$g)K#k z*-~^X8%0Y9D7uY+qT2~5T1r6CG6IU06Hs&q0YxhaD7uq?qLl;`ts)9h;Ja)|Zpy zl!>YpTcb|E2|sMUW$T3BwBW)&nD5xegv*-G=HkOm%{Sq~;j0rIr(F1+B*&=~{v_f! z)xwvSbDWg$gbI#RJN#HB$Eh3sy^7;B47a_=aWca5FLs z+J*0}>o}dlpVfDqZsB^Vj?*KYm+m;d!%t*7PXF+qjU8uDxP3Fn85UmH!f~z(zuwAm zMuf|@ah%cN!EGI9e0Y6($C(s9-O+Ih!wtGP&h+r)ZjLiEy!#5rnH~PChvUo(ckJaj zi^8|`ahxULH~TrxvT*rv9OgJ1!l_w~vn5=R?Ks=QPvtny z_V7Qsjp^9=>&~_1D@EfBH)u27FaJ|LK2cAY%Vl?bU&Z z{eNxO1|s%5V1dZ@LC{Zzj1sd5V7C+dpi)Z-@17}5V2o-KN*PF zFP@$XMC@0;J`Y6fmoL5wMC|9EX95xX3B^GXF;X}oIBxlH3NJ6db>wXby>jbF@tL*R0aKkS>V1$J{zzQ^%I*By(B&M6hfi6!I?_Ff%5>abq|!6iNuihgz6-b8N+bT`JC8 zs?^noG(G>N#p^1~v{#v+t1NnM$yFxmDs`zObCOr`dV~|qt7%_yr05CHagy~W>4lU{ z3$(4wD{*P%NFX`7U8TD^RJJd%oLB1AD^qcI2lLJ;-{ilx3Z+{$^TI0La&y4EV>8Rz zYpJyO=73YC(((?K9H+8*hGU=MI92@1tn5(PuBvHH+sdsgPfRR&Rm|&VZtl{*!e#`_ z2Lf~GTl8dqd+1;E9|OJDoADpN;>`{?eeB^>(USx1fiwF2Z_aQWbK{$H z`r3oJ(=$&Fum^MJ=D5z3sP*;z@zwHNB`?~YXUTx`LrS}4JG1tj9r<4i&nV8@N%rA3U^E;51mY$!TKC)m^ zdO?0pdVW?xPHxtu{Jg^4oWk4@={fl`CKcw{kdr%NN`7uZspr|tn@hJ$pOiml!kEG_ zQ*)j4(RmYc)3e9tPESu8pO=$8KD}Ucc7ASpe(uEFg6x9y+(uaig;Pe1$xAQH%Nw6F zI(y8-g7i^2Ia%5H6Vfv?vKnVK%4n3Cm6>5 zF7e+Zz4P+lmEb}_%bj+JDA#b8- zh7?-H*z5I^V?H8!MKs;U0naP@-~I9e(e5a70k?9B7jQ?V*r!^jq@+Zrdu5{oUUE&Z zY(vkBZsR4JRdTFp9$5y;dm(!;e{Y68nCBPGG;^^=UW&bVZLe%Kv;3>FC)=wmeJpQh zzzetbE~(|k7F|m%&pv83S9*!Av}mSzvF1u^o6A zMK8rQsl0tkuZVetQrrsWhA=G`E_MHPY;RzlNUv zk0;a3ZC%#$Qp;2^_d9(%cg^aO(ao{P%oZ8lvWELlHfvJ+WYdntPd00zOEzgiYtP9U zP5kF|?x@RTnhTHVk(W0q)9KlMP*%sQ`Zw~gyA!80Eq-~;NsUWhZlmIt+p*MD>J@Cn z3C)Tx)w1YynliCq%&3XEBT~$tl%f~cQLk5K7p}!T!JFB+`0dCvuT0V9TbheyWtp=Z zH_Gy_A=A7tPUyn5wb!+ED7gmn9xxXhF=fJp8U8itvQ2bRa|&0}Ue9V?oXoqHXPVnX zPd4GDbt-wcn0JPrYhHQ(9cr${f1=bY)0|VyyRqn*=3T7wnigM~dChpCjdc0OC9g-v z;xjTk@}kTut~0EKQXgObr|wldY3Mpvb{?G7zEj_#^UN)(x5&uVQ=R^GrZYZo;;59O|NIwSnI*4C2LZyF zxy_1R0I)0_{Xx*%SNu{s7hTI(`-i3ISsA)2V^^$E5Me$W-mY@R(Mlwqjnzu$T8X3g~%pHRN29%J>G^YHP!81#gWp?2vD#69AX5I+@ zJf5&OPtl!`ZsIKafo|lKi8+}W8AZ>~pN>*J(?21zGMDy6EKc@sRf!bxovfgC9eT`%zH@BD^_A|T>mAMs55s{=2Ash zUi2)Z#_V2G3Oi*NW@q)!o$i11DSlfFYNu~8`$ief{VO#0(vErLp6|b#GW~--(w4x> zERk1?y#$>3AZ}iC!RWmF!s3sc+?Ez|k%D3X#UJ6#AJL-M!QMzkj?BBqf1;F$5(Akf z2r^3)a1&*kSGMS6^AMou$W4%G{;2rZTIv=qxk1ef*E>7YJZSMRXzmL1MDgvFX=v$k zr9K#B>I`!;>zV%jWY?<(q;zcAGR1z9la`rcKh4Q#(WpsE-Td6~x!DD|^-@wN2< zCda(Ta;K+GXx!L@!qHPE3^&J-whWRyWJuITnt|o0wW)K3_4%0@FqqLdDyESD42JPWOrbwv}1p*?tVs zyTDrg-+Z(yqSrpRz}$8nb0&1kE&5z^z$Ejca{Eou!$x0z>5te&YKtCR>Q6w)BTFmS zvMG6hS@N(l)Bn>^q{@8M(3?aRzv9OL znLLUuc|=sCh&SHUCeHef5gX^BA_|;bo~umpp_mc__&r9{cFB=*@$<|1h%X zEw_(d^>DW6E%g6{7QfZ}i7a*xd;1u6T=Bgo4^>MZM3y{;%q+P}<-34WC50uG! zmZ)q-(ZNHA;1k%luUW?S8X+7I_zsiY@1bfE1aWTnJSbyM(#-Y!=daQ!%K71+($9DGbtIarFB6q)^QnBPU#|Hy-hQpBX+;M`zvzhn@**kYtK*mk8NLi$uHM2U*s$G z%XN}VEqi`>$9{d-zEAA?KH0oIO-fzDe&Mgff9&4>vH3EF|M;YKp;LQ=KJNV=?tF?r zE*3pZEM7$)C5u;PMy7dL_H~FeZ^rxfXkOW`%&~fT^EF^|EMwkX)>9dCBiOgx9?i3g zj+O1vJhO&9ns-}Wb?e7o&U`a0?Xfye)^V1O^K@LM z<7ORqn=j+o>p7s~aYMoG(>nfX-T=FU<_qNZc#(Nq?6IDXZOu(@_mw(ko43L42|C_q zZhE^P)A5XX2iX0)j*ZOw%I>y0PB-5aw0pje&zUa_+x@DJQC0mN(eVoNEkpbKt94v< zvA^%t@m=$dwa@=d$7;3xT~Ej1b^M*D<2G{x*vmhmNvBTzi-j;1@lE{d;M?f7}L|=<#oKOm%oSVcxNAfZ`AQbKYxFz zW6D5(r|LLzkiQFb+&;wLPw9Amn7{wgu|<}@JL`B;w!d%H@t}cjU*DrT#*OrMMIC#O z_V+b9t{Us_%{rbO@9(d5teNNUbR9=e_V*MWcNF;h86AI`;_tvz|JZ7}f9$H`?Cbq~ zn~pEd^!G6x<7fH1vW|V{_&ZC-)pPy5RmYF!`}yO#L-Ssj15 z-QVs~|JZuDf9$T~%`5!9RL8?B{r!%PiL3oxRmc8o{GF}inzjDEU&mAH{QaGdbvF9D zv5w<6`+J6tk8bt%^E&=^zrVe0{_*k${o|E7&fD(q9PLy>-fh$e+T#b$94z&V^19yyy)*0 zI=*(u-^X=Ke#PGx>p18&f9LAB?hSuGq~qsD{QZND^^f_xxsH?G@%N27KKY)%59oN| zxW8jh_{R<>{bMg37k%XKl{&t0%HJR8Sne}_*U)juX@8H>al@DXeptsZzV`QzIyOAx z@0L2|fA8;EI_^2=?-zCa`@FwHKl;Z`Kl{f%Ixhaz-*@SFWPWzQ?n`vM*8C8G-Q#rJVt$&y?niX|#{5`;-M{LX zVSc{A?lwA3P4V|!9rxDs_scrgG(W#%FQ2YsGkf&R&l70(w#PX0eM%h%tB=qgt>Xms z>Dn`OoTI)(dzp?a)i>$5Q^&nJzO3WBI)0|(IUWDfG0uG3-@g78b*ycV=Jg+>W44ZW z==rO3T(9G19k=VaOUD@d_{dyOypCmctf*sk9c$`XPe=2xz<>Yg*j>loI`-FbsE+2t zT+!uc=y;=!^K>+K^F_}$ci%`pS@s8@H=3T8|w%pPuzh57z*G*6i?S`<2I_NxR=+VFw`C(V3a zBhAJ%|0_)Y{Uhz7OOCK#q&MFq8JTCUr0D7F;luNDr~2397xVq*(la|hd*Y~Ey(Iq< z|Fw*_-!0ZPnpf3H%Q4^G%r)Q0DfLoE=4VeZ7i!C zi2r!so@O5I{p*)`cNYDsVg73`=lb)%T+Tkv{<_rswg&%im&-7h`OlYI`iBDS?P-5C zG{0lb?{?<5{nfCo`8gYNtYCiI%h=!coX6_{&jtUdI9GiuB6oSrk8r!Jn5{hA8^cvnBrfYQfNx)x8s6&1y7k~ zU#{)E+=b?8&M{9qv&;`wr`RX-i|5TXyY%&)>~4OZ(KLH~_On{9Z;g4HbIg;@dUJjD za{S_Xt4t_;eP>EtUxIla*SFm~%{lfucAD#3Y@exLJa3!XrLXUTxjuV4+1Jnfu`Iqm z`{&=DV?EekEi(enG<)ZzU-o(S_W>Qb+^*JvqMt|6#fmQTzu3A9Fe&T)@87#SdvVQD zy9^+LsFYnG1~wKFDz?}l28!J+D0X*YcXxMy-Q8W-SlG|^%Y4q?^Lzfs|2__J-Y@o= zy>|9=cV>3r&Tscpyq*4cdb|H^+NnO5-r#?qU-QWSd;8_DnLgh4)8%A&57#$vrN)Nk zjr8yQKJ)+bzx}t8_b%z}#-^CR?&fC&^7XZ)fAafG*Y`jFdv4{%hOPf+{om{BlG^`% zyKd?HzWe`qJ1>>ke(~LxNUu=nGicd?%M2N~Eovz^dJToVR)C zk8e*N@mpp5^jT8|4*l(e!P93|SDilV+kvajoUnH>Z2GL`LAQ>&?5F0=(`S7&aK$Cx zNV{Q?zuwt;R`V)nuQ`2I!=PVZzGh@~-rj>=iQic-{m$go9-I9;6Z%{}>XH#>Y7TZAj(zjly&2c-_!CB*F!IC^Ck}t|e;vO; zzvD(7vhI`Vh$m+~@jvgeVfK3*`rEeqA35^KQTvQY@3Apm>z>nRz0_xVdOK%5al)=6 z^EqEXA^-Z#>|YnzDPQ){uRgPX-wXOr*eQMdjn~Zn^{d&xF1T|pTMh3r_SJ1G6E14} z`?b-(JhI_tBOV|3Ki9qUCiUyydG>YB{&kUw|KICAt^b6Hv#)#huV2mnb-`V7=`wcM zh*!7mFyY+#b#FR!=C;d>{&CXK;WO{tdzFzdj!U<4`sbyFN7KjSY*(Avwf|1}=q}gJ z{`KqGzb?4z>LUiPldto!Sx>Ze9lOYc^BN!jdFT#*=5yY3rBN%7TzSMQ!+#i;KOdui znN;~^+_YIQjr(S&&6^s2dUDcoqn01J{D>8X*FRg2>_7U)E**!?zvgfK8=LztGkorm z(`Fs=$h2AC?vef(J8jlS4GWE(xMSA|7spwT{$;6Qlllyu*>3!zBWmlsIqtFaR_ULH zWT$Pzu@fh3-SGG8uctH1*FN;O%~u@y+tfj0`jx{zoOSF+?MD^szA&qyAzgER4{g)Z zXF0uxfy;i>&^E`=c^b~0)Yx!L`g+|s>5@w0q}|WE=$Oy9m^k^t`)_{mt;xg2+<5XA zP4{j&<A(E+Pea51E4dgp->CUV&Oc&-EP4HW=0k?% zUk8jDFmk@(^Nq-t8~UePvT5eHByP~pJB?|oz1C+`-;sSs^qYM<4(;D}bZ9Q{hp(Gj_fs}SNwi!y7gVl z9BaSxWv^d%eC?2rPn_}0QTOk<W>hXUTIehFBH(&5s_dR-Uc2HCLYIFaTf7`!t&pqdFzSLzK z9@OF2b!(~Zp1udvzfLzdZkWCobbPK`dhKHVO8US4*VNc<|MU%|sj<3G`kLC*RD9e$ z|EqklZ@TS=^-Gu6nKL~XlwKfI9G$+gSDs2=g_}nA96LLeTlPw;T6~|M{i~Kw^h{r% zn~VGtgr??llXOLuH`15B%A#FYO>bT~wom$HV7HCZYV?6 zlk$=LwZA+kedlN_-%VfVn^H^%m20IlZ!YghCt8%RrmyGi%HPuEvOGFneYHF?U2Z9_ zO>f`69Fwl0L-}sHZ_}~dtxtMoZ23TX_|myNF5P2qEf-C{ww2Swr z>{{l(+o@amYWfb{z5Fq~%^ckQpQ}7B-HN@- zXXi~%@|N?ZbC|dMG5v0z@}~42`(XSRI>A<&4Ja{^_63g;WA&DFE$22?JEwPWUSoCb^n2$wRu@dCbU|ZvtMpO*(pa6G z{`G5Pb^avix5ny2>AnBnSlv3^TC*Cff2QNcG*w5Wcl1D0_2zWSUsbB-q?7o%Qr#n2 zm{F;oo38VlO7-uwzO7W>Ot;H-mFm^$#`wNcJuTfDKUAvuY5yN9)k=B~Kc(Z+`&+xY zx=Xr^)@iOTo6dUO=IUYTvp>4Ix@fwx^_r_orfXThx%yOke;YJczexYuu(>*CdJh|= z|I4Iwz{bthVaezw&DGxNGq7oMwQB-4rn!1ra=BS^^~Q8%n>SY%NuQT3nyX{dr)|sT zYPV$Pmged{=_I-p)nn5~)V-*_pHAX{qPkAHl@2Vb`=l#7sHi@Z;(JB);&h$w7u8@fp{&hubb)IycSGHDP zPtdMvt?rrDv0bYxrqAYaU8`55!`l|9?vwv>SfIL7`e^s)QJp)T%bq=|E2J~qt4DQs zdbfM`sJ@)ua-Sa6^U{sAZ;$G&=~J~|k7|eX3E#g*wRieF9MGeBcDe-*>{0zJ9ez-c z>Rahkd~lEIN$ETf=~2BceGG^8sP;=Icvz3>FX`~ZdsMeiH{_%q)fbbA$vvvarjr;t zwYpt;x2sOAzLBnMwW-zX)6KfZ)M}ZoWzDJ8)^vjmn_5kO@}gm_sns>oEwSF?)dA`E z)_=TuTDs-O&Zu6M{tFm4qdF>`?zS_k+b0v_XH@q|AH#O(U+I*#pHW>leGEIysQ#1Q z-;Og{?n=M6N0-KimWR^^vuD2WTe{x8@`Vf1r+x2yVXpKx`{WDl62pD-g_G0GxL>}o zLi*SzrB7)~L%KyL=L@@~>p3D{*fISld}O|GXTNk8aQ21tc|9s$xH!G>(fPv5>0FM< z7pA0J?X+#ug|E^_e0sjHXgb?7@`aVt2YBY}-%20%S+jpDy^90Kr{CH=-E;@#3qPk5 z%lCO(W~9$yewleoQ~K=Z?+Y#KrT3nHVA%3(dKb<4!UySQEb@i*lZo_)92!~%rO!l} zFH};g<_p)R_tlaw+?_rV?em32(=~U<7p_ik(=lI|FWuJZRpt#X8z+99^Mx_!qMqN?w&9FlHON7>y~-ar!PH? z)6jB!I{Bu2p?7*0`Ny0s$EW{_n)8M9@uiOypWcQ_^eGBDkA9S=zt=1t!N+ufbsbEoFqJ2w~e7b_(T zt?6&iE*6Nt5nW~`EP4322{35pZ_igCQikCv;Rzgmpjwf zgkr67rTpJp5;CgTCJ~!0WbHUKgsc-YgsdAggp7_ELe`5JLe`HNLNc_glrR=kg>4|85f(7ZDSKM zJ~koS#U^C?*o5p5n~)u26EYz-Av?t;Warp~OpIL@GNLj$eg3k#!+s(%1H4 zmom%ALiQ*oCqA=<>=}oKkiBAtkiBDukbPo?kbPr@ko{tYko{wZkON|dkOO0ekb`0p za&T-y4v9_3p|J@$EH)vB$0lS_Y(gf-Cgh0Ngd7>0kSVbVIVv_GN5>}QnAn6I8=H{h zViR(FY(h?mO~{F{2{|b?At%QsWVg!Y>GR*^v2@R;*u5^Kn(qD-rpfs@Q~F9h;DAViR(0Y(lP!P001J3ArIQAveY*3*o3?on~;}c6Y_FwLSBhY$g8mlc`Y^} zug50jjo5^|8Jm!|ViWRqY(n0NT^Djs<;(Q>?=mIbi7oD}3wb#`Bq`o4vz#pC!{W$Ff@_Eb<@R?b@^wr?X2d4so7jYW z8=H{tViWRxY(jpBO~{Y23Hd2DAv0qW@^frLeu+)UudxaFEjA&)$0lS}Y(oBsO~{|I z3Hd8FA%DjvF<(y4qGdV_U7L&M#`HiW zJ>trbW{So*dfv3t-QITgJZY!9<)uA$+Uah2)$W~kx?A32&y{w%Ti)L8m3F#Y-ofsf zcDh^M(VjEybho^d-6QREx4g4GN80&uO{GZlTN}o#{M6yByM)&MOo-q%-X!H0O}cw69RfA)RSIp(%y@Sf{^` z{xXT#4|WC!2}t+mqN%a6UIJ1(BR|BcG}aaMOHVZv^EH;4S5~x8W3gxY(lcAp!j2C` zi`b!PQ9BeZW{0B1?NGFY9f}6pp=gjDik7rP(O{dRr38wW7ARUqplDfvq9FoB%Lx=M zFHp3CK+%cZiZ&A{+FYP$3xT371&X#3DB4<}Xd8i|u>wWo1d6s5C>k$N zw4FfF_5wva2o&uoP&7fHXeWW9odt>}3KZ=kP_(N+(QZOr(b|ob_Y#oWA?ew=Vx3U5 zY`Tk6?A};rUs=)Kjm1Cdxyady_HleD+Sd+6``Mvre>)T%V27du?ND@(9f}UNL(w62 zC_2=p=rDnz!v%^a2^38hC^|x*=tzO0DFQ`D2^1YIP;`ty(Xj$W#|ac2FHm%XK+%Z; zMJEXqoh(pvia^n+0!60@6rCzkR|*te zB~Wy=K+!b$EBas%vSV}<3rKIb|`wp z4n>dJq3AI?6g_T-q9^Q7G|di0)9q07q)pLN0!2>?6g?wQ^sGS9a{@)r3lzN|Q1qfe z(MtkFFAEgCB2e_IK+$UgMXw7Ky&+Kara;kK0!42N6ul!*^sYeBdjdu83w1^JH&$*+ zKx*4$I1jjAlzvQBe9%~CUs=&7jm3-U=UcNCed_p7^qC!sKDR^B7j`K6(hfym*`erb zI~2{ZL(w;ODEii>=sSU;?*)o}5GeXlpy(%oqL~6kKMNH7B2e_JK+$gkMZXIa%@Qd3 zL!jtSfug?zivAWT`bVJXUxA|k1d1A({^wDC{V`gjKv9!WSM*V1<(CAcHaI_7_;DyY zE&qI~(o|+&Sy9`>Iv4n>{pP}JEDMXh!yYO_O87n`D* zKv7qLqHY33-35x~5Gd*)P&B7NQBQ%QUIImP2^94fD4JWKXdZ#0c?F942o&`dDC#Fr z)L)=zfI!iFg0DsM3luFN)D@+_^>FzFq&7JHK)h(zRDYy@V|u+ov0zh~ePu<9HWgbe z7>X8id?;Gn4n<4Yp=h8TiU!%CXh}O14YotkQg$d>+73m_*c2@*P&7oKXgPtR@uBDdI}{yghoXb*P;{^ziVm?u(V=!II?N75 zhufiOl1ijEX0nj%nilt9tZ0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(a8cu zrwA0CDo}KqK+)*}MP~>UoheXsmO#0!6n86x}XRbcaCEodQL72^8HeP;`$# z(Y*pi_X!l;FVq#C*Hqac0jd3xpRPVX6t$%n@)Qp=mDyKT^hi^&_n=VpsN+M?V|FNd z+zv%g*r8~e9g3#gq3B6F6g_2!qNnXp^o&i>vjRoW2^2jqQ1pU8(Tf5_F9{UAEKu}{ zK+&rLMXw1Iy)IDnhCtDq0!42L6um7_^o~H$y8=b;2^76AQ1pR7(T4&>9|?6u4>eWJ zO+ad0^N;8s4n^Chd)39qO=b3#6@A`R+&efFec|{}^ran&zOqBn*LEnHVTYn`>`?Tr z9g4oQL(%tkDEh&s=tqH~p9G3#3Kab;Q1pvH(XRqUzX=rmE>JW}py&^QqCW+S{t_tq zTcGG4fuer}ivANQN`LeF1?kh6exjb9s>wf%Z4@YK5-6$&6g3MJ6+&Inr%ja)5|G-6 z^b?NavrzO$9_=b+_LUX2uN40+9f~?QJ`{DdLs2I?6m_;kQL7z_+U!u&#STR^I}~-b zLs2)IqV57ka|jgm5Ga~cps1%nQ7?g_xde)O3lz;QP&AJ~(Yyjh>90(#f5Iv1D^S!= zps2q<(Ex#>`2>pQ7bsdlplCsXqJ;#C78dG?s+G!sWs;&IKe%tH)F0`0Y)WI1N|}9S zMN3qQHHUW*Zd?-5D4n>F9q3BRM6dh)VqQmV_G|3J{ zlkHG+gdK{Gv?-b*P;`_)(a{1$#|RW1D^PTtK+*96MJEUpohVRrl0ebP0!60?6rCzi zbecfX=>kP(2o#+uP;{0+(b)n;=Li&?D^PTvP*=2nrSe+>QX8D_P#+MA*3F8}uawzW zR&-IN=&?#Dy4dld=n^{=U22D-%j{5exgCnGutU+6b||{a4n=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1w zU!dp#fuaWmiXIZ`il$a7D<&YdOY=`-FAPN&r=P+W4_C_UD=T`uQf#$qD0;&2p=g>N zil*D4=t(;iJ!OZYr|nSmj2()ewL{T!b|`w@rsxHMq89~x6DWFLpy&gEq7Ma%J`yPUSfJ<=fuc`^x}rxb zl_L_6+NAta>&HUT&iP^gXO%Mh%8I_K6qm0aioSMyD4Jo1qHpX_^sOC=zOzHo_jV}y z!45?~+M(ztI~2{dDf(HU=of*aUj>SO6Day!plFsr(H{aue+m@+B~bLYK+!(}MgIyE z{U=b=&>WBAC~6caY7!`_2oyC76cqwR?F5QSfugEVSM)`t@>Bv+dpN(o=*v(vE&VLN zXlX99udJw3bMf_>p{TRtLs6?8irVZ@)Wr@(H9Hh_wL?)iI}~-dL(v>|DC%KTG^apO zPl2Ld0!4EP6!jJ;np>b~9)Y5H1&aCz6!jG->L*atU!Z7!K+${xMe_?3Eg(>|pg_?= z0!0f86fGi9w5UMQVnSU}hvrJ>VM)=c=}#sX9h>Wq^!LtxE_LzdGW*JkmP`-!hlirU zjt@mk*`a7@I}|NrhoWWeP&C92Ma$WtXn8vntzd_u6>W-E5-3_(plB6=qM-sss|pmY zCQ!7xK+zfkMQaKa4HGC@OQ2}DK+y<+qLBhcqXdf97ARUrplDrzqR|3H>j@OCFHp3B zP**gtxw26LQhOx7?s`xt8j{C`&1LqL6>ZvF>^m|Pjd6S^+RP3`o7`=6|9g4QGL(y0}6pgbf+E$=wyg<=*0!7;k6zw2Tw4*@L1c9QR1d4VRD4Hlxw2MH| zt^!572^8%vP_&0Y(VhZDdkGZnEl{+NK+(PeMf(X9?Jv|7ZQNWrKLM#-o9|F>5{jl| zMF%vO*;iI{NON)j+M(!B$A_ZB>`-*L9f~H|p=h!lijJ^D(UEp2nqr5dqwG+0v`x`5 z0!7CP6dfl}bi6>(2?9kY3KX3rP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owm{K2 z0!8Nv6rCqfbiP2*1p-A=g}S1HnkyeAAhkczEDjDu3+JaGFKjNeudL|O=Av7uC_zbHFhYv)(%D2*`erqo1z;8if$Arx=EnuW`Uwx1d47I zD7sCc=yrjkI|PdE6ezk&py+OaqI(32?iDDyPoU_2fuaWliXIdwdPtz?VS%DY1d1LN z>WVIIuFRi+q(4TS;9L@l`sP>6KGs}jUs=)g=3=e&L(!9t4@FPeq3CHl6g^{yqG#<; z^qd`vp0`8M3w9`a(GEo~*%ZAjQ1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH17 z0!8l$6umD{^npOphXO?(2^4)SQ1ppF(We4Mp9vIwE>QG^P*?Osb7hwVq}DBe6Pp%_ z7VDVCm(6ANl@)!{T%5FFDEij%q3An16n$@pq95!~^rIb$ezHT+Ogj|)Y=@#>>`?Tp zP0?=xMZXIa%@Qd3L!jtSfug?zivAWT`bVJXUxA|k1d7rh%f2Apz|D;mH3}3p2^3WX zikbzA3W1__0!5`jQB|O*MWCp?Kv4&wuITIL%54cqZG3*ZdPXSvE`>I*4n=d=p{R!)isrOKQBOM*^|C3NOQ5K?K+)U+Me_(0 z%_~sUN1&*$Kv6$|qW%I!0|biZ6DXQrplAVsq6Gzt77{30SfFSTfucnPiWU57qLu7Ww6YzFRDp0hlK+$RfMXL)Gtszjfra;j!fugkpiiQgm zjSwgrDNr;@plEG@qICp{))gokEl{+cK+*aFMH>hdZ75K*kwDSLLS50|qOx)VQu{l< z?s}HL(wG1hoZ@LC_2IpMMv79Xo?+*j`zIy)3yZ-=5A>`-*09g1$UDY{vp=oW#ZTLp@46DYb}py&>PqB{kO?h+`v zTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yquIRF&(zZ=f zv{{C8c_?bl_lu?#W%iX7JzW%o#)YD193P6FwL{T!b|`w@4n;56q3A_B6uo4JqL=MZ z^okvdUbQKDO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zW2r4+M%n6e#*gpy*?P zqE7^hJ{2hXOrYpV@6SCUs=)j zMX~?*Q1pZ2L(z|RDEi3`MKkSC^s^m`ez8N*uXZT<%??Gs+o5QdP0=3$MSltu{UuQJ zw?NT90!9A{6#XYq)X**-wo}w7P}C$)R1qj@7APtNirNVjl>$Xofua_HqV@ts9R!Lx z3KVq`DC#WK6@6P&rY0b@URlw1q3Hg6@4B^JnSEtNUE388ZXb%eIX)D1w?ok!b|~s$ zhoU*{P}I{7MZN4$G?yKUdfTCBZkwWc1d8SrDC#3n)K{RWpFmN6fuaEdMe_+1%`Z^2 zfI!iL0!0f66fG=Jw1_~_q5?&W2^1|ZP_%?V(LjNsK>|ff3KR_%>WaFwt9+7x)F$;w zaBA)9kMuXp-_e$8S7u*X(U5jUWkM)g&hepWc{>!XV27d=?NGFm9g0@AL(wXBC>m;q zqE+osw3Hn2vqV4QZw7ngQcCbUyjy6RT1d4VNDB4+| zXre&TE&@fn3KZ=oP_(;1(H;UtdkPfoB~Y}tK+!$|Mf(aA?I%#Qzd+Fe0!0T36dfc` zbg)3tAp%8*3Ux(Ww5#lvfYk2KKS$d#6z!Z}vUXUzGW*Jkj%Zh$vP&pB(($2aiXDoM zvP03)b|^Z=4n@b>q3Ad}6diAeq7&>;bfQhsNdiSD3lyCqP;{z5(P;ujrwbIFAy9Ot zK+#zOMP~~Xog+|mu0YXw0!8Nw6kQ-tG*zJJLV==-1d1*eD7r+T=u&~A%Y?e3N$o0k zBp|gu{S%zYq3DqOh3WEkW%iX7UEQvDeYa3_jpIYnwRR}F&JIP_+o9+NI~3h$hoYP8 zP;|2$if*w((XBQ`w+R&8E>LubK+&B7MRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el z2^2jnQ1pmE(W3%Ij|mh#E>QG@K+!aTqUi!fPYQKKSGKGCnSj)eD-xWmLeYr)Vxy

    N(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1% zl|a$g0!1?fioOvj`c|kbdZt}vXaZ6@BL5ui*-$j4lE!!K%IqsE`l($pZtqYu)A6C` zXFC-AVuzw%?NIca9g2RpL(wcd6#Zd`qCf3W^p{Q1-vUMd2o(J*Q1qWbQ9~II+bL=k zC~6WYst6P{3ltRsMePKNN`a!PKv9c8QG0=+4gy6T1&TTe6m=FTY85DI6DaB;)D`{E zu5xq&QoA_))z-z2p=etEBaXGQ%)YXsIm+VdeM3lt9ta0!7ORbw%CE%5w=wZTI{XQTH+)>F4ig z%clR2)8s2FTA?hy+dmYo==e~yk{yaxwnNb>b|@NZhoV*OP_&vIidMHn(HeFrTGOUz zm_X550!70Gibe<&jT9&vB~Y}sK+!q^Me7O_jTR_cPoQXhfuaoriZ&D|+DM>iV}YVg z1d28lC>kSBw3$HB<^n}q2z5ovm6h57NztnLYtizdXhv4FWm#rlS<%?C7<^DD8t3>> zw5=VA#@nH2J3AC@Z-=5C>`=6$9f~H{p=c*N6zyzNG*O^v7lEQ(1&VePDB4}1Xb*v+ zJq3#P5-8eRplBa~qJ0I5_7f=DU!dp!fuaKiiVhMeI#{6S5P_mY1&R(6C^}rAXp&G@ zv~^h-lYrDN%|A!mCKUbBCymKvnSEtNN0r5ahlHY|9UqF0u|v_Zb|^Z|4n@b?q38rV z6rE^?qLb`Ubg~_aPO&LERiNlJfuhp|ip~%yI#ZzNEP??$Xofua_H zqV@ts9R!Lx3KVq`DC#Uw)GAQaCQ#Hxpr|HL)K#FUn^0FYv#jiqfYi2~Gr{>e6g`y{ zb+4A$S60-sTAX%NDC*_-P&AhvihA3jXl^?c&0~k6dF@ct#|}k(?NHRu4n_TKiUtT2 z%_mSazd+Ff0!0f76fGoBw6H+YA_7H=3KT6SP_(!}(Gmhh0|kl(2^1|UP&8PeXeoiB zr3H$X5hz+#plFCd(Q-mvQIBfnt^}mE{(uB$&T9RUey{u|iI%UH*;iJya(XKW{y9pHSE>N_GK+&E8MSBSp?JZEWk3iAB0!8}?6zwlibbvt7 zfdWMb2^1YHP;`hu(V+rGhY1uNE>JW{plGr{(GdbgM+$XC`9l0jcdePl9ud?`Zk2#JaXxW?xy+jn(4XlS9!> zjt@mQ+o9+dI~3h&hoal;P;|Q;iteyO(VccEy2}nlciR-*BT#g&K+$~yMfVF7Js?o@ zpg_?>0!0rC6g?tP^r%45V**8w3lu#eP&7@TXu3erlLAFg2^2joQ1pyI(X#?Y&j}Pg zFVq!XU#+~5fYi3ACO9{QqSx{tD|(??W?xy+E7jtMQ$x|Kjt@nz*`erlI~2WPhoU#_ zQ1q4^ir%(E(K~i1de;s`@7WZ+FHrP>K+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pG^o2mt zmjXp!2^4)TP&7lJ=o^8eZv~3J6Day#py&sIq8|l{eiA5}Dby9cRIPM7Eh#!EzwY|w zQ1oGb$=c7=GW*Jkeyn6tx#9>L5_mQJ|=kKv8FbqE>;THi4op z0!1}}qOJl(-2{rd3lz;EP}D=HEBdus**pQMP4AQ7{1%FK&OZ*Bv!%?wvZCHC#ldHV zqPZO(isrFH(Y$sj>SKqZzIG_;XNRKxb|@NPhobrHP&B_y(E2Ka8jg?x;>?nfZ6r{% zu|Ux#0!5n&6paxm+DxEmbAh5Q1d6s4DB4P(XlsF@Z3K$O3KWeK>WWrrseF-u)LzKn z#D-Foey`ZJrOdvvq8(a_^88S=qvJ!-1UnS%WQU@i?NBt)4n@1zp=eh-6zyh*qTTIK zw1-X6o&rUC2^8%uP_&Og(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3Eh(OVy0!4=j6df*5 zG)bUnvOv)h0!2p(6ipE*I!d7EXrZoXyOzqL2}teT{IG2MP;`I(j&@8-nSEtNC$tpn zObtaRIzAMgWQU@Y?ND@z9g0r1L(yq=C_3E^MQ7Nd=uA5lon=#Wwm{K20!8Nv6rCqf zbiP2*1p-A=1&S^dD7r|X=wgAQO9YB86)3t)py+aeqALW7t`sP`N}%X!fud^!imnwX zx=x_zdZDi9xR%OZ2}o_t{D+5*4@J%SXZkm^l-XBSbW2Nd#zmp%R>y~;+w4$uyB&(| zutU+Eb||{b4n=p{q39kv6y0lwqWf%$?iVO}K%nSBfue^5iXIjydPJb;QGuez1d1LP zD0)JmXqrILbb+EL1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq89~=$A_Z7?NIcO9g6<7L(zYBC~9aQkK991qaBKx>`+v(Ls7F$Q6W&&PN1k1 zD5?q+wFnfo7bxl=P}EVNsFOfZXMv(tfuc5nqAmhOHG!h80!7^fin28Ir)jkKSI&p?bDd6eVKh_Mf0{Vw!bnI^>KVC>T8Fhes(D8 zZ-=4*b|{+94n_0Zp=bd+6fJ0nqJ?aV78WR4M4)I`pg_?efubb^ ziUtc5EhSL2v_R1^0!7OT6b%t5T27#7d4Zx81d3J^C|XINXk~$-RfM{tx!YHcPe5vA z{`-sOX)4yV#*ijEX0nj%nilt9tZ z0!7CN6dfy2bevFEv}60q9M>g9d-hInCWN9h^Pd4ZzI~Z}Wkn~qFP6O_6rJMuP;{yt zicYgb(dl+5I>Qb{XWF6YEISmPZHJ`-*BP0@J*Mdu3?T_8|2RiNlXfuf59iY^u? zx<6ipK-nl4cEq(ISA0!2>? z6g?wQ^sGS9a{@)r3lzN|Q1qfe(MtkFFAEgCB2e_IP*-$o`^serNbS)4;QqEybZ}Pm zTKh8l%8K4`*kH9g60+L(u|uC|b}C zMGM)XXkj}PEnW}mn z%%oQDP-b6Q(OMmfv+fQ>!yO-rM%bZfq#cSz*`a7{I~1*BhoW`uP&C>OMeEt2XnmWa z4Frld6e!wAplD-(qD=&fHWeruBT%%NK+)y`MOz3IZ7EQ+l|a$f0!7;h6pa-q8YfV+ ztw7OufuijMinbRh+CiXbN1?80%?_3O5|G-l`KPhNLebp$4}?tUP-b6Q(Jmc|ckc~F zyE;A;?PiCf-R)4chaHOcv_sKeb|~804n_Oep=e(_6zykIw7)>n0Rlw_3KShAP;{_B z(IEmwhYA!OCQx*^K+z2C$CV`@x1&VGFD7sasD>|h^Wmp1IyDi_L zJ~b3wknb1W)}hS4vZA{>6gxf?itcuND7wcEMfcjF=sr6X-EW7Y2kcPvpdE@HvP03s zb|`wprsz?DqQ?Y^9v3KjLZE1xK+$x8q9+B4o)Rc}TA=6|fud&xik=fFdS0OD1%aX$ z1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;uuIP>ql@k+?+AH~w!`>N+Ud&&Z-t16jUs=(+ z9f}(t2}SQYJ`}xghoTScQ1qc4iaxSK(Z_Zu`os=JpW315GdmQ0Zd3GyK+%^1MPCUN zeJxNlL!jszfue5(ioO#l`d*;u2Z5p=1&V$WD4Hoy^s_+GF9Jos3Kab&Q1rV%(JXY6e#*js4IHAL*XT9g`&oe@kl-tHQAx4 zVuzw;I}{amC~9YiqS6jURXY^5*rBMsO;HDdqK*PZodk+H3ly~q6txKybrC442^4h| zDC#Cq)Lo!x4uPT`0!4EQ6!jD+>LpM#mq1Z(fugwuislh0npdExk5E_iZ->g9k0(XF z^Ycajg`!#})wg4rePu=Sbu5;f7K-L~d?;GL4n+&vp=cpH6fJCrqDAabw5T157PCXq z;&v!n!lr1TK+zz9q9p~21`8A|B~Y}qK+!S+Mav2l4G}0>PM~Ocfua=zidGaTT1lX2 zWr3nq1d4_V6s;;yw3H`=769f~%vL(ztIDB8%TXk&q*O$3TI z6(|}bP_&sq(dGh0TL=_wDNwYPK+)C$McW7zjTI;wCs4GlK+$-CqU{8VwihVcL7-?y zfuaclMLP);?JU$44ewaFA_1x0&@aIm5sJRee}Txvj%D_h746=!nD%ri+QadoXiqy7 z?PZ6ez3ou6j~$BkwL{T(2?9kY3KX3rP;|0D(J4Y*(XJgU zGZK*6#QeJJ-9pj6`N^YGJC@m3R&-{^qQi5c=q$&FqO`?T$P0`^t(cor?F<^V!{28`w}Zclv)H=@)h=YG;R{ z(hfycI~29pp{TtbiaOY#sG}WLO576DaB`P}EJJsJlSX90El> z1d8SqDC#Lt)JvdfE`g%n0!4ER6wM=0G_OEWAAzF20!94?EKszHK+#Zv zqE!WoRud>%U7%QEq7Cd&w4oh}HnKy}#&#&$#12K9+7yiuDB4V*Xmf$0 zEd+|T6e!wCplEA>qHP3<#tIaT6DZnNplG~6(RKnw+Y1!!AW*cUK+yz&qMZbab`~g_ zC{VPEK+UD2pcm6H>Y+C}+w*K3EO&iPK#Zk@{PD=XToQ*ra#p=fW%hoXJ#P_(Zd ziuSWZ(f)QQI=~J^2il?NAUhNtY=@#lY>EyQC^}4_=x~9eNdiTa1&WRkC^}N0Xo^75 zQ36Fr3ltqAP;{(7(QyJr#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_bwzu0s=Stf z)CT7-KYRL));WzcI+fX1R&-9M;@5XW(YcNfMd#U}=zKdAU0{czsdgy3&<;fx*`erS zI}}}FhoVbuiY^l3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ZW1WE zS)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssyD>|!FrPq5&QP=zf*t0{?w5;f!PG$C$ z6+O_YSmA?E^q}KI(L;79de{y{kJzE;Q9BepW{0B3?NIcD9g3#ep=i2I(USs2PYDz~ zEl~7~K+&@TMb8NoJugu7fmlGkPRA_lKfe@{dE_?^I@AS<%Oxipd{^qE8$jiaxbN z(Pwrj`rHmhU)Z7OOFI;OWrw1#?NBts4n^PC6n!gD^qoM__X0&f2o(J&Q1p{P(M*A& zp9PA35h(gqpy)S&qTdCIW(gGiAyD+EK+#_UMSlwv{UcEHuRzg%0!0m-G)7owL?*h9g5o9p{Ro$iaOe% zsFNLvI@_VB)ec2%Hbq?oifRHyT?LA|2^4h~D4Ii{sE0t&oB~BX1&VqJ6wM`2)LWov zZh@kC1d8SrDC#3n)K{RWpFmN6fuaEdMe_+1%`emyHFvIjn}F0#&o4|XI@cfRub2O- z&;>e|*;iJyNav!{=b>m($A_ZD>`=709g3E)L(xDx6b-UN(UNv38f=H6rR-3&v`x`6 z0!7OT6b%t5T27#7d4Zx81d3J^C|XINXk~$-RRoHL3KXp>P_&vr(dq(4YX}srDNr;_ zplB_DqTvEXBLs>@3KWeJ>WUWXTv;*!seP7zbhdCP8kBz=vUcY(`^t*e>s)O3Whh$T z@u6q~I}~kbhoX(_P_(ffiZ-!B(WZ7N8e@l|&FoOLxlPd)0!3R26m2C?w6#FdHUdRs z1&YQA6m2U|G+v-+JAtC@1&VeMDB4k=Xo5h|P69rk|x<3rK@b|^Z)4n+srq39qx z6di1bqC@OZbf_JQ4zoki;WkB+1d1jL6dfT@bfiGh6oI0n1d5IpC^|-<=vaZG;{=M1 z7brSGpy)(_qLT!QP8KLSMWE`>Iv4n>{pP}JEDMXh!yYO_O87dsTy z>`>Izrl^}hQFno&IRuJ&2o%jJP}EbPsFy&|TmnVC1&ZbtD4Iv0XkLM$J_1F31&aC! z6!jM<8X!==c0XkHtdKHu>K5=+-j(%8E8@EmrzH6m8`AP_(ffiZ-!B z(WZ7N8e@l|&FoOLxgCnOutU+7b|~7)rf6${qHP3<#tIaT6DZnNplG~6(RKnw+Y1!! zAW*cUK+yz&qMZbab`~g_C{VPEK+&!OMY{G zZIoY_wm~TRG%MPtwamVpf zP&C;NMMu~a9Vt*WMWE;?fuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!nlLd-S5hyxU zpy)J#qSFP6&JZX%Q=sT9fugeoip~)zI#;MG+OM^8O#)IoHGdP^KNKC7pFBFRwamV< zq6=G#r~e8?7dbu@U2KP`*k_4nUZCg&fua`$ie3^ZdRd_86@j8x1&Ur1 zD0*F>=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFao6QQo?k=Dvm z2}ted{ByKNLs8#+C+XAHGW*JkzHBWvZpc@VUU&VK<3rKcb|{)*hoW!nQ1q=GioUZ$ z(f4*J`oRuGKiZ+_C!3;~0!2Ry6#XJl^s7M8ZvsWX3lz-~DEdR7=ud&7zXXc@7AX2h zpy*$LqW=Vn8rtGvJ4KBGMNI-l6@j8=fucg7sGUGjDby8x-dZ^*0jb^9E5Z396#bsR zy;a-F>?IMLh(H z<`gLEDNxi)plB|EqTT{Ua|;yBBTzK2Kv5roqP_w}{RE2o3lt3yD4I{8XnujB1q6x~ z6ewCqplD%%qD2IX78UA>+P766NkD4*=DR{2+Uk$=@6A7&U97FlzOtf0ZNcEo+COA$BNQ&JIP(+o5O$o1zs3idGURT3MiI6@j9m0!6C| z6s;yuw7Nji8UjUY3KR_!C|XOPXt+Sp2!W!J0!5<)iq;k=T1TL0U4f#}0!8Zy6s<4R z6)n+LX;&mg`-*L9f~H|p=h!lijJ^D(UEp2nqr5dqil+f z7AQJKpy*hEqT>XLju$98L7?bFfufTHicS_NIz^!9RDq(?1d2`0#f_8Pl9t$C^|4dc{H`H%)YXsOWKOtJA|T3 z9UqD=vqRD4b||{S4nbgdnVuCpn+UZCg(fub7)if$4px>=y; z7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaWmiXIXudRU<7 z5uvW=qPEIg2}o^p{xSZ=p=ibY2SOfgE3>bxXj)tGN2gFU-SMI5NjnrhWrw1t?NIcL z9g3c{L(y|~D0U4f$a1d84lDEdI4=tF^`j|7T77AX2epy*S9qR#}1J{RhW9&fA6(>W=6BR@s- zL?}8T|1|cCwle$5ie|JGtF(opZyX`+v*Ls3^d6m_#hQFl8O&0&Y49(E|2(+)*FZHjsc6wM`2)LWovZh@kC z1d8SrDC#3n)K{RWpFmN6fuaEdMe_+1%`Z^2fI!iL0!0f66fG=Jw1_~_q5?&W2^1|Z zP_%?lSJbIX<+=oo~AWnSEtNOLZxp?G}obc6=yW#tucx+M#HO z9g3E-L(%efC|bb|MJw8&XeB!ot!z`Yia^m&fudCfidGXST3w)M4S}LH1&W3V6s;vt zH2nV%_a5L;l0K6?@12Uf0ZZZZ_!iKJWkd-tYTz9O0VZxik0NGjmSe-2lL%G5{7$0btQo02Y-4 zu&4rnMU?<7ssdn9H2{mI0kEhBfJLjFu==GI z%}n#sqGr)7rZEv#ESgI;i{_EBXg&ao8Ua|e z0Dwgc0a&yMfJKV|ShNoSi}nRz(Gma_Ed^lFG5{7W2Vl_(02ZwTU{MnQi<$vg)B?bw zRRAp74}eAc1F&c{0E^ZD0*j`ng+_}Y>9_0E^$fGf@NDHf9YSF=I-t-=3(IHH4 z7Of+jMeE6C(V=9s=rFQbw1I3E9Zoijjv$*wN0QB=qsUlvGysc^0btRw04zEVfJMgx zu;>H;7M%#dqLTnvbTR;oP61%isQ@fG4S+=(0a$c80E^B5V9}WXEIJE-MP~!B=o|nR zZ31A?xd1FW4-i@M@MOTx}qHD-z(Y0hOx(PVMYjX6=neoD-3h>=y8u{pHvo(70btR+04%x>fJOHMu;>8*7Ci{SqK5!j z^e`Z>=)$znLn27}ppGKWMP|_weUSY~T3G#3i=IgHKI~%_J<0TD(Nkoz=xMT9^bFZ7 zdX{V!Jx4Z+o+q0{FObcm7s+PPOJpp18GuEb0a)}30E=D)V9{#;EP5S)MQ;GG=uH3? zy#>Icw*gr64gibZ1z^#804&-9z@qm7So8q^i#`Nk(MJF*`WS#kp8&AvQveoy1_&&A zEG-o2D;5>%cR(IDix%s*8b419t6yr-S83i(S!U7KOm7x_LpF=PC7VUxk}O#-eQiEcz9IMZW>C=yw1X{QCa0I;YX0E^lKu&4t7i#h_Zs1qQt=!>*ar3jLK zS(=FRrCD^Wz8%szJ* z1i+%50a!E?fJMUqSdZCHj8#An?)1JW>End ziwXf)R0P1HVgMGE0I;YOfJKu4STq@cMP&dingYP0sQ@f02VhYJ0E;RCSX2eTqG|vZ zO#@(24FHR30a#QAz@mBp7VQDRqUnIZqEYFgH${;2EA_3j(Pq&#{ta7tSp8CqW~Y0< z?_d_~#q?&;-ej{VMmCG)kj`F*AELuRuqJ;n~S_HtN#Q-eY z2Y^NU0Jd# zYXDeu004^)1YprxKw#0V^ib9ivFKX;VA`H$(G&Wu#)Hzs>X%xyKHV$W$t*gQ>CK|U z$Y#+7vRQOE*(^GOY!)3!Hj9oTn?*;H&7xz-X3?=^EIJN=MaKiM=mY>3oe039lK@zB zG60KC0btRo04zEUfJGYtSado7i_QRG(U|}&ItzeBX9KY48~_$=0$|a(04zEWfJNs6 zu;>B+7F`GkEIK4Tv_J$&zeJ+9&Mb{jx#Zuo#Qyg(dInInH;@ygyWP) z{~qNy)zOl%j#C#sb{EH)5q)vIBXMXhJBF9-2{k+6+mPB(VJI;#e zsws}s61}_JaaKp&D#uwHoixpH){OoK4aF=Q+*=(R&*m=aOh>k>gwuE!)R&u8E$w#BpwjzOu}5Zi)6<={R>p z8=4*Gp6KPP9Or@PSNl88Bhe8DIL;H%HESK`ndtooJI)JHZ@uGej!r$yabAy}e7NJh z9ewRc$Jr9?bByDB6rFdR<9rsq@&w2EGWyL)j`MAF)Txg1WAwm{j<77-`rnc7=w|BwCq2x~)c+7T*Ui-b(RHMossAPCST|GuPsQW@5?T6GxZOIu5dH;FFdxmnffRCR=b({H`dm=nfgbv*14JbSB^HgnfhmH zj&d{g?~EMhX6he`ILXb_Z~C9+X6je9&vY~OySAI$O#QOt1#YH(+wBrJQ@^fsg`270 zH@U{m)GrL&;AZM4zHf0e^&`7?xS9Hy%X{2R{m|S4Zl-?f=@Bj7-Z4J5J9&vUj*6I%LSO{>+y*vfWM5 zT-WKP`ZHhdPT$*v z4HA|y+-F|L*VmWM=;uyLNxS!#`@TA`pIeiX_VMl49=p1qTbq*h%}u}Ev)akJOD4*b ziTZwIE#?MO`z`)#EzYOKr+W)a>$iC4ohKhBL$zMVYftzj$;tXnrrAv! z>@J&irfbLRxbfcKXZlOC?*U&AclzES(=^I7w*=F89S?o# z!D0R+FTV5fE4qoij=#KoeU?ATC%?K&oW8HxB%dZN`LfOBQL7;M}PIZ4_=XVEnDpF4S&f#GT;$8P3dpS z;86PkbF$=EB)=)4P|AQ4+C`kV5Zgc=z|e^ZiVwEbmI(BG8b<(1oI zAJN~GU^G`?ct@G4w{#@p4|tB#&L5Dysl7Gm1r2s^-Ledwq+@?+ zE=MNm)J0~lEqBgvJ9KDmvr8u@6rm>_I&|vLvBOvyJvG{9tTY)bp}*-CZEhLXq(q%( zS8LLLwYAA^)})QqT_*Bc`w{IV9o0E!`UA3TJw_(XbN3$Od&tpmxVw7~Ix?h3Sw@jKUr|-(FtA1WD1`3uT@6PHeEPbcb0Ybdm@YDZ2wauz;&v%4AKLdQ?KPAu`}8E!L2@Dhx7tm#?hh& z@!*B+8wzrr-`q4U%j7rYtek(o4$$Bx>{nuG>x5*w_EHz>>F|7aUYPHubx9k!R`VndFE2|w@3MEbhceS*c;a-TmqU1zTI z(lNAd4X_qnp2UXbtR`81-Zmd1H4jq`KnHLY3EvRuKu#`&w78k-Yd)A42OaXBlR7B5}g zvUtBnCuh;}rHwfaOBz?_3}3Q*Uc-`{=0y!njX6z?%Nm;-nsXZSW6dqA<}Y5J)3SW| zl6i|77B6egSvYTAtf6UXPF`+oL@YlyKQES-t1w$&_Oj*68nYW4<}S|8%N;%REe7cFmU%#N>%)h$i_ zDhbv|b<^^FWSuwX)UIe~+P8GovRIug%fjjOV9B#ay&0(oJ{6rq(}oPIbOP7XL{XSubq>W?C#)o(bB~mtVLe*<8c4Qq?CMb zC&5WNjn>eb;a*e+hIsvbuArL^*$6V?;84e`tgN8%l!5=H^&x&M|7<<$KeV0_YL_L8 zlHsNI^ZF0+(tFD?^_OLm2v%QE9+Z2)8Feqz)SCy&>i7Aa(wOo*Y0iKwoV?jo6+Zg+D^s<5y9_M zM$o6WeZh$T+9#c?|6s38BNJ@FsJs2Q^`4&6T~>zngGv5bvr@Ww>AIM@VRf|)Xw#~y z5#O3w@^ZdETK`-xz3)FpR!id}v+4goT8^Oe{k^P|uK(7x|F9gg$EJ%-x;VO;`fsPs z|MBKZPlVf1;iL+tuy&I;(Y8l6_FOk#tMiPR z4pKs$#xL}`r(|U34#?^24I1Qi53Nz2BT$Y-|FQPB*R5N2v>Id^){ojuzK)iYGa%a= zG*Fs8KpB(%r&;{hCc8?{x|ip8(HyU9Z!bN|>psF8EIYULJmVi-kG5Hqq+PoP>i&mA ztaQ3ZiYq;x;6=-H7354<=tbp7)V-f1f!5jpsU5StPO=V%FZ6mz+Hru_tFHjtYcq5< zUA!G_rT8(+b4Pipq00{*?zy2i+~NN8`)2(Qrtg|BQ+C!B8M^%tnXz_f&;T#mSBTB{ z-?v6;ep0SnhLzS<$4Y8yVr7+k6qJ`0#|mmD)mM~M);YXTQBqr5FsUR~S5*}&ud1Bn z)Rat$eyqh`g5oxl7naLKO--r48A>V(Bo;eW zrM0nw;-HyP{@B{H(u4&sshiCDja5&c8Ix^YAzQhqpsuW{GFVUJ;uGc-B}`dXGc8sq zjun^H1~X$_22E;X{$`7nmsL)UueIrArDd^#YQL97Rh5+`MQV$0Ug=0(Vg6vTDN$Qr zR3w(hr$*Un^(FNsu~J!6@t3L#YRc+n#-mDIQBXP4HeG8I{${JKs`YzNELO)mFv_1l zOJU=c=E?pMtF0<6jkOs$Z(N(PiwY`Zbu|T*wH0M`e##1>!wX33Hwugfz6(Ra(~XTs_K%;_-m+KSW`A>a$TjY z(O7LsU7haB%(}Fwe5&8w5hH^=XOurjf9AO$e`oTMC~Vtmti6~gt1sSKSy@eKL9C>x zD3(`PX1jS&n_baAv=o;WOo~<2*Hzco#rCKwuao^J-UNGt9#r)3qld19y|cJvk21N6 zFRZT(*0SsyiN~X0S5lc}CF{myn^Gf$s?~%Z89u5-XWeR8mr$&}Ca8 za)hlbkR!y@l9{p6f->F9*@iZT-rY#os_JWGK=!fH^0K1VqrPvc9?asaE-yd6gUhZS z?0~ZW&0n>2>6&=k{_apxRn~U5Va{?GuBfWf&7sH1pox5c2U)Uw*}^P2X!&d;&F9Gg z)50v+qnjLp*O3F+8W3#TTlC~ZNTUwV{HfC9Auu_5^j82$~f85cHqenRZ zY-YV|;|)7~te~iuCFchPuH>9$#QKHj46jR4r~dttSFH~m0h$jCv7iJ zj*`K2CB8?imL)E}jv+_?c*l$Li|v$HQ&L$hwk8~Z;~TihzxXj{WGyaR*cfYEHh*!$ zvY75m@y5!^%S$E|l-n*RXZd2;=UY#6zVGofQo>fw8{5WsQ)RNWlyH$%%woyL-OhqWT*DbmSikOJ#-BPEI%q z<8FDuOub~Z^Q;WXA!@;@W%F`Jj&KswNb7AIHRFzNx2D1-U-!5BL+|bextCiijp+z3cTJL;mCRNsF6^$F0rO!); z=Vj>=)7-K7BeQmFYFyIT(A>CFR`$|)D^^XIx4fyPadr065hDb&ELyd6uG9rfmN&Fy z%j4Dwa%h;ZK*n6KV!u(@%`39!=ZzN9&@^w+1bP0t-`MP>!R<=CYn=ns0kiB4OV{>!E!p7_+jms9cESiujDA@I~RUk>as#_K>UzXi0k3OX~ z3!5)X7SH~IjcKE$uS9Up(aU&$`<7Hz)yt8|*SYNlcl^X9*K7raW#whFS}&S&@@_+q)FKhtMmAGPy|zt}TM)_T5}uzI^$LJjXBj|L9Ab z^LCrd;Rp(zd%NN<#VB$v|uKyd%)qulsd z!4OA)glj_oN>*-o?D{N^W4tU{!n#SAKrb=n_~onM&#(1PFn$X=+FA*2-k57}JTIxJ zPPij0(q{yTXAkXn;tl2G>GBw&XsR4agC%OStDwAIw8YmsF!65re{)|}T2@-s_NKAb zq2huf|80Rfc^e_#e*7r>&wWDfp=G7*tGh&e^kAv$D+~4z9E>Roi{!_RR!py=!ZGGo}v4b*Ce> z)nzfesn+emO<+O1H97XvuwDn*JmeDBhVtYNAl|=(HBensHMvY~3uRMO%B8V9W?+`S zBH9tvq)e_+XNe54n7qH$`p_d!F0yR~ZLehX*p;XkjUq{DL9slY+3vR27eMDYNj#5V zx3u0672CNnPwpjHELj8b9&?49D7eFg4HWG zdI_sn&zO3*6RVwGRwu6{oPN0@%xis|kS7Our+JZFX2tKV_5RPFft=C(0lnW-5Zspe zFD2}oay{O^-Cpll#`716yR;}D0 z%ku<#X26O}`1rv8tvAh!8|SWC=&xeE3#5~}s}~do?gr1Jd4(k`m76=c4~~_V7u2>+ z$E)?#y65Nv1|GFmp~=*+(Vwi2A6++KlBl{KM*{auPB%iE2^xs6IJ4K zX}@d#JnaVebS!85`JLZn>jUmQdEAz`Z?!%n(uEE7iZ%zg_>%x_F}@lTeT&~p+q(6i zJ^Qoe4AFXC3?3xwi+ca)kEBmk>9v0%mu)ZJ7Ri41?{9MiPmNpe>i%)u$4(BWJG2Wh#o&N`%9GgwA2^j-_Gm7VLASIjduNaaoFpDx>;-LgF~7gfZ=x7mu=ei zfo#H^l04Y)SF>CR{8K3wLXLlOwzInfdv}IgtTAmSWD2?16}yY&GAH5shZp1TA#pAa zZeRR$qt8(NTd-i`>l0g+CUN7pdDF!fv%Yd_W!3axEpUgVPwlnc;KqZN3gsEKyaVUI zJL12rw?Dj?a23+#`HbJaJUi>?&5;lEnW#SyJh#b_pIw*-dms z^TOhV%`Ndh1dGZc#`ejC2d!=IX}FH^`ytyS-i*I1%K5CWphhn`Wp|N_od2{-COqf0 zh0F^c(rUB8T^g%M-X^f?B>x(QcMAOZCmg5E?cl;H{;X4WY_5*XJ>CG!3m(z>&FB+R ze;~LZXU=+TZhP8^?~#c+QP2}!YZ=prShASyr%`^{qT@xAi@()?13ak@4dm zdrF=@^9;Jy=HOCLEm!_Ca)Ciy!~TN|B|V+An|&HDHv6I zl5nRY=RaM${#8oJy!p)ym5ZBOs`E#Ujz96*qp@l6g2nS1^r=zps^A^T;Dn-01-Bn` zuR6G{mj{CJb?7@KhnqMkswi%AV=KD|+c&j%#x>qs_}sQ!k4} z-?W+FX2c)jcpW?%jm5b6rs0Ic|Kysfvay2QwoEpB>odOT1#*ASVRySJ^|6wkaf9{K z`gB#FQ^rT-Js$sVa#D@nyKlF8+uXmZPyT+OH%2r<*NO^?WKEaG{3`}WXU}IMxK~oM zY@bZLF$#1^xPZ}Hu;9?9Pa<`71&0&n=)mRkCz$^yIE?H#Zu}bbGix-Ck~Qw{Ow_SH9-+kDo-8?0olk;s_!AWO2ez$UYGd3h4)n z6MjPSpuVj_<-L=$dRv|B>aRN`Swb}PsouE z-6#BnoVMSS2yNG!kR#u6OZW*n^2M@*pO7Qp!btcDIq3;WKi}WYA4AuQZkKdfp4}71 z&}G#xWbmVT4neAB{Za)#n%5GfYL@R`#(y-Q6i>nH7jBpNz_$MwXHbhXX#W4`r2a4O ztR|k`@)AyO|MG@i{27Oy2!rSOty9}`k5-^>Wcc3&Y~RgsZj$AYZxlJVX_ar$Y|$$G zd*eTAmG8&s-x^e2Dh{=m@8`_7`jA%Pv&E&Pp23$rG_RGc?H;OCzH)eiR+;V^t+Hdi zWc7QiYFLtJqx)cztZ+3#t2E_Tnbb*=uT%BcD*EhbT=zR2Z?x43Rtv3GTdlV`&+0x_ zS6V&9>ISPPS=H^V?cZ$mPOJA@ebnmHR$sLGn$>r#erWY`tKV4t$*O!Y)t`@kTSe!m ze>q*NeDTz;8CLZ#WGU}wb+FZ;R`aZmu{yzOk<~J*RaWb*?rF8b>O!katu|X-WAzZL zhg&_?>d98muzIf5i>+R1^?IwfTD{xqgH|86`kd8QtiEmaL#tb@erI)?RXK?J>nTP2 z^w*=+u2y?l9bk1QtGQOkSl!KPiPdtewN__YZLq4}<<$8tx4NIzgRE|_daTt`te$1{ z0;`u>z0T^bR`0R;u+^umzG(GztM6HrudDj~`O4~#R)4peB>SKCx1H5gt5K_ctq!(2 z%<2fMyI3u-I@xNK)jh24Wp%#QeXTZGU1N2f)g!IyaYOsJ(ds6v7hAo`>WxKv;JtuC{=%IaFHhgm(w>d98mw0geP%dB2&^%kplTYbptlU84_`kK{ut$u9vORGOv z{mrT?-&xZ26S3OGYIm!BtPZl8ZFRKO-K|cxI?d`VtMjZbvAW9Y!B&s7dXm+%tX^dG zYOA+cz1QkvR-d=}y4ClsZngS@)jzCya>CN(?QAt_HOuNwR`adyYPHyEh1ET*#;h)~ zy3*Z4#_Ex)E9bt8n zT=MDbwN@9)xm)uptH;U(sOB@QUMuHp&39UTUQY0u-?I9hT=HrD)9PrscF%BO`+RqSf|t!J^|wtyYf>@?KU?mv7tZ>la&n zdwh^Tw>n_=Am>Rr-6A&x+TX9N?yxe*BdjiI4zhgV z)gSMsRYASq>bCuZ?5z&!ZU+Q)s?`l^gM6~prw$JCYgSX&2f2^cJq`=`d`y6m_hA87TK6N3Dp)!$AEa`@z+PCPZJ6;_Yf801r}K66Hp->{l~ zc98p7ov|s%jaJV)FUVJ0{pf-qe`j^)i-SDI>WWK)e2~@KE)Vj2@{Fc?OHwU@D)mgU&d7;${ZV&RcRzHyoef8l7tHbUI@;Iwa_XYV7 zt9LvQGM}s=e>M@T8`3$QsJQ?J7tag7U$OEm;elEz1tzPs(kgvD; z*-JtG$?EV|g1oEMme+#3-s)X%1o?5R&f7umWVQ6&AlF(wZcC8Qvii~oL4MC_=Ep%E zY<2HXgS@ZROFj?sjaIjQ5#(R2=6)UI30C*}Hpqury+>|Hb$dK%HR-1ycdl0NpJR2i++gYS?_2HpSCEHTog>d!^!24yFG~vY%~rpZzYe6Y|7tZ~ZqPLEZgsW% zy&%npTfI;IaFFJwttNL4a+=jCsX?A@^(48$*747^`l|eKAm`Btl6%O4=p{JYhWSwSwadcc4nA8GZ0K|y}jYRZrxXIL%YDabRe-Xwqf zOWVKS>eE(V)#^FU$Ckg<+EM;!mDOL3CuavdVzrZ2X)n`qZ>#-{53`(Wb(HZ!t5sHK zTU~5*KdXmXJ<001RJU947GJ=E&0RzI_vDSuH%*H3S&gRSmlHQ(xJtGin*vRZDn+UiWJds$sz zbswwk9oavmf1Ry%v)aRImeoO4hg;3JI?k&9JVx4?X?ZWJ^R3G1*`JS`X8pR#>LFGS zvnr=G|Me5B%4xvQ*IB*Q>YY~Q@aw<+nAI1oZnpZC)%UE*VZ> z`djs%w@4NpeC|JQkv!J&c&q;N7U7dDS6QvKI?L+bR#SAoveIP}`|V2ctK44s_5Gxv zcGa9F`-yR9c=MX2Ee&&}wloEG5kvB!_ZDZke#+b#KDW8q87`lTAFgnC@G$WI?EOZ6 zs`>iiB6;s+!E$NPA8wdCx2bWzpv{2DpFv5C4NdxG5u0l;#y`mt{UavUqIBCCu74Y& zQNEv*FxLf54NGODf|`oq4J|EAi|4Ltk!Jq~KfPpJS8PKQyh^GyO^aKm=v{WjWl zmhoc3YwKh4f&fYqv;FY;T3Mr|VVw z*F}D5?-3c+Y19Y($t!f7nS+91{a0Vp-{-9|-Z2YYXNoX>7*8(I+VpR;jK?%OuFh9~ zUYFm*{;f_}-VAw-{(UaP;_?b9{!j8k*V%<2Rp+ZeTG>}LPn7Xq5EzwVJuYc`sq(Ay zWZ#fMCslmDUI*-l_C(1x;~gda)8j8cjAwrfry*~_@Z~vKSy_2waz~HN%^#aTPKI-H z^Ai3YJ$htT*0?eGqw;0EtgJch4=E`x4gLgF(5fr%9MGc@4VGs{10a0WiI?S;G#7w?tie3!m{k)-6j zQ>Q+%ZA63yzv1|DJTzWcjyRTG;Z)w%!jguMZn!KGQy2JTqzHcdxCR_5tY?ULM=WbV$;-`{*)<}mg9tm21c4zF)Z&Rv%k3`KIA%7USexr-}w zX!7?N84qpya-#e?4{h6$nlWeSqO;vUHcRW$-v?$*{JDR-svieUp8EZkgH!t#{=8+y zp5=3=%$xe?w%!*!D!rB8b@Kaw{BF_ej+5SJ$#1UwI={R)bLy-qvL*O~OFWL?(8 z?=$AjC@a%tm8JaBktI!?H>Y;dp3Wbyyd*s;nzE~;y)5lMZZEsdXYx1OfH-3w?1va$nr_D9+Ug)nvk{M-`QE#ewMC5ue4xl;grI%B3ZZ2G=H6byKds- zpC3&t_&y_j2bt;y>Bl9h1LpKxbh0k}j}J_fex_%YztJ#j&fG;cGRMu^oc<%H=FgFu zHe$+3zvfTA(XZdl$t}}XCl1Vz<+>;D)Wr|~;N-rQ{M+VxKihWV&Qpg@8Co{X@8#8> z4wW>_(nRs)p1g|}zn=WZ=A9<%xVzr>VW*-GcHV#Nz1=pftNLN9liGcv>}~66&O5Q= z*_)nzVaPLke!1IzgU-J7$SvaThILzpI^%aA@1(!>;Jr)cemT8ic7AT>@x`_B7RiS7 zo$l)UKw;i4i(iXfetpubAHBJuqvL)yqsNgapW$4;Xi)B&^ONo^{cz0AyMA!`(FYEB z_=elMcHa2p6PaCJoAvmLnrHtUe01Y?r4u(CdfVA+R$qR}WeYznKjQH3{z%e2<|t?E zxpFNU99xpzdbw8ac#ND`@71GS!cUT$a*`YblibMhavVrX@(z_t$E2iiQ-9gnx5+ep0e`zMPCgx1`H(RgXD73U}x!DdIh)FcNO=AqSOYPe0q9lpOv=jxnKEr7NLf z83i(WXlR!FliRgUhCMx3q!i0hH=Mjy29u|D*1ww?en5{`;Unc}=Y}7bV^fkqnJ7F) z+DZ;TD;@R1FUzqiCEP`N8x9{K%}2tUgtrTCl=0h#XGjYj!pF$yE!mb@Vsenl?R zI)`I@sHXFk!gX9klh9^iLo(z8~eSRw3UoJnN4(}mH*=NEL zS>9*E$HBj?Ik!`;XrS>rhZrDwTrmor=_fa`gBbL)8#ztp{);p%6Kr!M*GR`^Bt^E0D)%Hs&XF#E7K)TgCq55Fj+RsX z)==a|Y4eLvq>Fg>Whiohte3Askv(K(d>x7$CTruHP~=-#hHpcWkj&w`P^72KwmdnK zC$p_cj*O9BS0+aemaSiv94V2;s*@wH$SBj2Be%%>YLX)_NvV|yWPWwYkuEYpeR4#f z%kPmK`CiuR^yG;A0W)Vta%7@-IWswOtu!_(Ig%~gWzXcu4B2e6C5byXBuCasC%Sr( zF|z8qd6A2x6RW+*Oj%27yvP*UoCkQ369vBQMUIs=-|-?NWJSK~MP3%s-t!_|WKp(w zkz1sL?|YFNSxX;yk%Oc!FN7oC%9t;PBM-^sFNGs=ZQ{Hfj{Gc}d~-PRj&$jjaHK*u z@vGs;GXh@=N4}ONdOaL@MJ9hE964UPdq;=JyRz!;>=3zF8oR4Q0yfw^b-wN>A(rH z8u!zIA+qf2WRtdgRYqQ~1AU~OLv>)f?2L!$z`_CYr?CBTWE&i=1FK~9AE5(Vr7uV7 zK#Q!klVdXQx-9W2I?z{od#Vn+FH3fs4tyrdy-^3=lJ&l3o{l3OJ3t3IN;`VJ*Y0Q8 zhOQ3WD9feifp$qUcl|(8ySrr;$vW_htVT}e-77aH&BnmI?z!_Lvd9~Al zhh;;w*MYIpat9r_LB^4jl+*4pSwQ)Nold)C(XX=(d@Ad^iw$QsMgfvqyrt~$^pi`-2Iq*wBjv%)#e^u%yG0*XKwAfc-zT@p=v5&+Nj<>VL-V#ST-cXCZB#v^t zVHSHz9PN177JEn><9Nd@W=b6EcsUlM6301SuEp*W^Q2pOmb+<|e&t*4s#!WV!g7XY z>Dfrj>6)c$qb#RsmcEU)oT^zmH^y=o&Cf?v1nDNwf5C7t0+b=S%-~wcJ6o z^l!Z7_L`-C6D+sWEdATfazwNAZ+FXK&CD9>}?rCVwN#vj%5sKu#6#dEn~<$%NR1>GKMr- z#*hV;F=U}-3|V9uLl#@ckbNv;$i9{XL&`!cW&3v-BS$Q6N?^!vIhK1%!fK8hvcg*_ z`uK*dv`Nj7CW~fBvqdwc#iALq%Ay&vpG7lde~V_wYKvyb8jEJg0TwajK+71i)-r}1 zWEn#awu~W%SjLcbmN8_#WehpgGKL&x8ACQ$#*o7;W5^MfG2}?g7;=dG+mrLZ*#yc%AWQzdrwy>I`hTP@d zDi=we%NX*Q zWej=TGKM^18AG15j3G~1#*n8iW5_d>G2~gx81kHD40+x%hP+@ILteCuAun0Rke4lE z$Y#qJ@`_~)dDSw8yk;3gUbl=PZ&=2VH!TN-+!1aLq4)-hJ0+%4Ee;O8S<$`GvqUiX2|CjF=VS{ z4Ee$`hJ0xmL%y<%Azxd@kZ&ww$hVd;C-Uo2zD zHp>|Dt7Q!N%`%4kZW%-Vu#6#pTE>vSEMv&umIFiH3H>J9ze~E@1bOfJhNSk?VR>q% z>Nsi1Ub5@;l9N!n-pzQfP2EqjT=u4r`%0F}@-VrNWVtMtCrIZ=E6Hwe$#PlVj@(PK zT$Z;d_mnJ`0v6Ms{-j_8X!Y~ z^f4Wfu0T4O0Z3CIz3d7|RUqB$2I!(d`q>@OS%Gvk3h1OjdYTF7C_wLUdH^~oke>Dg zv{xWK?FDG3KziC65K$mK?E?rake>Dhq$rS{_5*kdq^DVcWChaG{s8&1jen~%0FWd= z?{x+OX5Bw3F*K$f3u#XlJH3 zi-wZTqG4pSD4T2+4JVsLIb^damuwd0kSTqWNMWX>&GzNf0V*yw+ z4uD0w0I+CR02Yl0V9^8s7VQSWqTK;lG!cMB1pq861Yl7S0E>zNSX2VQqEY}BO#)!i zWB?YG0RoGLxS=CNkko1VP-#cA=uCO4;!SbG>X%wn>3WyT103I?DyBD!s>x>2G_qM# zLpF$iMb`kZ=vn|4 zT?fFT>j7AF0|1L|1Yprk04%y0fJL_eu;^9*7TpHGqT2yjbO#`?=yW$ULj*}ZSFelC zFpJju_hN2X{ZfnWb-gw6)|PM4eN1l_-A^`)9w3`V50cHIhsb8p!(_AQ5wcnIDA_D} zjBFM?PR61q09f=S0E?aiVA0b6EP4ijMb84T=s5ruJrBU57XVoFA^?kC0$|b004&-J zz@k?GSoA6Yi(Ug@(dz&#dINw(ZvwFBEdUn14Zxyz0D(n!yP@+$kkl#_=N_}@Sb2lX zd)E!CUuw|@u6Mt@pXFQhA=8^hACb+XkI81yCuFneQ?gm~8QCoQoNN|tC7VTGkj!(W>E*SS=5ni7Ih+(#Tkp4#1)e z02XxxU{N;!7Ig<;Q51khnE)*60l=c304(YSz@pv&Eb0TmqP_qu>IcB0EC3eu2Vl_v z02U1dV9_7|77Yeq(GCDC8UhF`@{&S3iy)~ZG%bEE+*Ji$;>oqETeCXfzp%#sIKrEC7qf0kCKn z02b{Ez@qU0ESdnoqTK*kv^xNcCIYai0Dwh>04yp3U{Nsui%I}kR0_bNNdPRG48Wo? z02WOFV9`_n7L@}6i*`;5tq?&{KakIwctg#i_4>|5MN(M(Qj4Y~c_;5|7S%AlSyW3l zi|WW`Q9ao#+JkHsO(&a0GstGqOtM)ti)@rZ*(_R1Hj54-n?(nc&7wodX3;t_7Oe+h(V+k=It+kC8vs~zH~@=|0ASIP04zER zfJH|Gu;>^7799(~qT>KqbUXlyP5@xhi2y7*34lc>1F+~602ZAJz@pOtShNv?A-(bWJfx(0wn*8;HUIsg`3 z55S@u09bS*0E=z{VA0J0EV>1NMYjU5=r#Zr-44K_I{;X8Cjg7?0$|bIfWV@&l0t9wD1WkCM%z$H->U z<7Bhw39?!AB-t!_ii|~11F+~B02Vz9z@p~>SoAyqi(UX=(Te~qdI^9GXRTT z0btRq04#b9fJLtZu;>i{7QG3;qPGB8^fmyC-T`3Iy8tYD4}e8m0D(pKC54U>K~f)* z5950Gn?*z9s@i)$DXe~}MIR@5SB@}?K4E&Z=u@&;^cmSK`kZVQZ6%vUUy#kBFUe-n zS7fv3YqDAN4H=8R1z^#404(|*fJHw5u;@ns7X1XkqMrd+^a}uswgIr{R{$3M2Ed}< z0a)}00E_+vV9{RyEczROMNY_W+p)+6U{MkPi$VY_N(Nw&2M8?sFe&t$2$EVO?{Ih@ znMKcQNC}12FSV$B$opoLS=52)&7zKEv#1lJPx80RSu- z2*9F204y2|z@i-hSTqEHMLPnpXeR&`?FZFHj8GH&7!@?X3^ecEQ$fJXbu328UR={7l1|c09Z61 zfJKb}ELs4-qJ;n~S_HtN#Q-eY2Y^NU0&a%(p=7h@FftZx0ASJK04zEJfJH|Fu;?fN799=1qGJG9bSwai zjssxP@c=A30f0p(0L02ZALz@k$CSad1?i%tVz(MA9koesdFGXPk0CIE}h0t6QA z9}0aUf~0<|AD3Qj7R^$N&JKmuFSY2rkQd(FEIOa*&7up)X3>RYv*;qSS#&YkEV_hj z7F|jh02W;jz@i%fSac%*i*5p7 z(aiuXx&?qmw*s)}HUJjg4#1*209bS<0E_MdVA0(GEV>7PMfU=*=srMT(WX#nm-Kd{0`qV61r0;;V zOAf1FYEh?T?~M|(s58@>MP0~dQ7YLiN+X*^>14AggKQRcC7VUv$YxP@vRM=*V^Jmm zi+TXCs3!o6dI7MgHvo(J0I;Yp0E_wouqX?FMg0L-Gys4_0|8hx2!KU{0a&yH0E>nI zuxLjB7VQMUqMZR)G!%eE!vI*64G1jikR19;1WCP8zM1TGOb+h!WBR?+;mKk3OD)Pz z_WDgWi$*ZLSu~Pt7L6jCMWe}P(HOE>G?r`@jU$^yyO7PIUCCzAcrq4E0ASH>04&-a zfJGAlSX2POqCx-`6#=lQ7=T4304yp6V9_K17EK0VQ5gV>rU0;LDgcYh0a#Q4z@kb3 z7F7YTs2YGp(*Rgh0|+e2O%4@{AgRmsbJuxh(WmlBS+6!ZtbVCQ)04f%DQ3|OrZZBHjDNqn?*6QSu}@i7B!HuXf6PY<^iy1J^+gv0a&yEfJF-d zShNU$MT-Ggv=0D__61GkG04&-M zfJOTQ0*mUCL&u09spWb>y@y#eLX}#b99F;7qP5B1)#YZHJ9ZWWh4k4RG>&Rx& zda_w`DA_DJjBFNdAe%*plg*+d$XIkF0E>(*MNDrNT}(EME+Lymmy*q*%gAQYXbT0sl?gL=a{QxX_0Dwgg0s@Q9PY!jj5{tgq zk2hXm77f(5Lmo;Ft6yr-W69o_X=c&mOm7xFK{kt?B%4J~kb`8UTx42Vl_~04#bFfJJWsu;^_7 z7QF+&qIUsU^d10PDVA1aYEcye0MSlXY=q~^k{SCk(`C4}H<#Q}@0a%m- zz@iWUi;@9YfK1%O3i02W06Skw-HMePAt)BzA!^m%gVA`v8YxjwGmY8IWZclsT@ zu==GIrF!1O^=45T)0;)EoW>I&tSrjFkMVVx?s0Z0B>Pg0;UH~lW z4Zxy404(YYz@mNtEXo34QGWmy4FF)#KmZmE0$|Z#02b{4z@i}lEZPx(MLPkoXlDQx z4FzD)FaQ>11F&c~0E=<}Sd-B?aUA*8<{~mpio#%zsFSTft=e3(* z7L8_lvuF(2EE-ETi^h@7qFu;l(XM2(Xgt|0nm{&-b|afbyOXhKA^?jD09aHAz@j1m z78L`qs04sTr2s6N1i+%n04yp4V9^u+7EJ|UQ8@sMDgani3BaN%02WmPuxJ_pi)sK^ zR13hOIsg{c0|JXic%k7UNb0%zx$BW;(ZTxgXb&%}eyK&XJg;h&S+pn9n?f02Un&z@ifXSac!)i%tSy(a8WTIt745 zrvk9(GyoQD1YptW04zEKfJJ8lu;?rR7M%^iqH_RPvEF zS#%BAEV`C#7F|ciqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v*02bW_z@pm$Sab&fi|zzq z(Om#6x*LE+_W-cyUH}%|2f(8H0a)|^0E-?3V9`SWEP5D#MUMaii!Sm)PE0H+QE@Id zi+)d&@TeD7zto~9J+FU*S@aasn?+BP&7x<>X3?``v*#27JUl9qR#+W^f@4~=y5MpDuSe*uMZlZFpFGQ!d5S= zeyK%Yd)~r%X3;lHZx($^HjBO^n?>J~&7vR3X3>viv*;(XS@bj6Ec%6P7HuPA(XRk3 z`VD|ZzXP!74*(YZ3BaPi09f=l0E?UyyKToJ7l1`c04xdtuqYXTMIHc)QUF*K24GPH zfJN;9SkxYXMI8WG)DeJ1od8(W84y_Xr58F*1W6sJ7JX$FZPu&nE-7L4OD)Ps@vdz& zi@GwsS=5be7Ii0^MNzU@lu0&=dXUYco@BGA7uhW8O*V`Akg=#Q0E_wouqX?FMg0L- zGys4_0|8hx2!KU{0a&yH0E>nIuxLjB7VQMUqMZR)G!%eE!vI*64Zxz|04&M@U{Njr zi}CVwh+MR3`O(dH|1!S|Rkc>q|04yp7U{MJGi%J1lGzox3lL1&% z2Ed{z04$mcz@l;h7F7VSs1krhRRAoi24K-N02b8%u&5S*MRfoyss~`v9sn$w4#1)r zfWV^BDWS|oV$pMY5*uR{{j855XQqVJFSTf|6mQ%{CLNXRD0$|Z%02b{7z@mKtShNIyMN0u#v>iQ5r9P}0kG&~02ZABz@k$DSaccyi#7tV=yU)UodLk2 zGXYq1766OR24K-S04&-Bz@l>jSaco$i_QmN(FFi3x)6Xx7Xbo`)}@3l5kXR4(ogTN zH;dNlf$8Fuu==GIU7q4Sy38!Pg6YkoE6HZjRb;d1YO+~$4cRQZmTVSXM>dPDC!0k# zkjndMYjR4=ym`W-2uR&I{{d97XXXy24K-W04%x}fJOHK zu;_jO7CivKq6Yz3^bi1x9tL31BLFOV6o5sK0kG(CKw#0ODWR<*Na{vU#JS8Y`a%C! zg(p(N>X%ydOp4cGrCIbW)0;)lkpX*0bo%WfJG4i7PSLlQF{Ou zbpT*dM*tRe0$@>R02XxtU{NXni_!prMc<@^_7g!;E9FmHd*7NxE&3J5^l(`HQj5BW zy)#ysMNy_Vi!#Y(Q4g|N)RSx$^&*=^y~$=#AF^50muwdGBb!B8WGw0rz@h;FEE)*F zqCo&G8Vtaq9ROG~1b{_50Vwh+MR3`O(dH|1!S|RkZcwekxA53IL0y z0804%BnU{M_ai|PSbvr~7OevW7VRAl zO%_2?kJtCnVrJ19SrXQV!|In>ba>cXyw)r_g6YkoBgtmbQDn2|XtG&!4B0F?mTVRs zM>dO&C!0klkj!wM3jtVk5de!W24K-804%x`5Lk3rICO#tlA5iL zh&Gr-o<6(2EF4z9)S|1x-t`BYMOQPuS#%BAEV`C#7F|a+i>@b|MK_Smq8rI((M@Et z=w`B6bPE}aZUtb`Z2&B~9e_o50I=vz02bW^z@obWSac5ni|z$r(R~0cx*vc=4*;;} zK>!v#1i+$)0a)}10E-?4V9{d$EP5P(MNa^*=t%$;Jp~9Xx*{CfEP|vyq@Uiu(kyyc zpBFtH4y#{k(eq*Nr*&r03rueoy+}5TULu=CFO$up&1AFa6|!0MD%mW0jcgXZPBx3) zAY;*+04#b7fJJWuu;?8C7QG9=qW1t;v;}}g?*p*t0{|9%2*9F`09f=f0E<2WV9}=l zEcy(9MV|w(Xe$7Vz5rm+mjEpK3V=ml1F+~DKw#0c;ZV=@Vo_d(i1VCT^jl8}--g5L zms<2=*xU6mv*;(LH;aBIn?=8n&7y5&v*=f{S@av(Ec%^n7X3jsi~b~=MSqd8=x+cP zIT5?%#v&JhMM(fG3IVVv8GuC|0EPI$nLuqX$BMY#Yh$^&3gJ^+hG0I+Bz0EsQSTqHIMNYFVgVaq z!!GuQ4Y6Vu6?^ZfsHoV_eeZo=lL@}>`G0GjbJjO&!9Blg_Ot7?%d@AX0)R!M0a#QC zz@jPu7F7eVs0M&VV*pq*7Jx14C$c(Pe^0@*B@ zK{ktKlCfwO0E=b=uxJhdi{=8bXdVEI8UR={AAm&*09bS)0E-p^uxJqgixva0=p+CZ zoeaRDB>*g13c#XM09bS?0E?CZu;?@Z7M%{jqU8Y3qPmd3j|dVzLNA3Tnnl;CMJqx< z^-C=}GZd&g$1FOF_GZy)vRQOC*(^GTY!;nMHjB<9n?>i7&7w7Av*-e{S#%*8i`D|L z=pq0XT@1jYO8{7ODFBPs0kCL20E;dIVA16OEV=@KMOOl_=qdmfZ2(}=MgSIV0$|bA z04%x&fJN5=u;@Af7F`d(qRjv-x&h!>v@+yhB!YzV^mg?sv*=m9NV+i;RKL`sTSI~M z=b1&f(cUb&oop6uA)7^akj=t%$;Jq5s`rvX^>3;>Is z1z^#004&-8z@p~?So8wGv*_lK{}B-+JU=Aj++r4et6wX6F%(q4)S_2Ife+T0MX%A` zEZRvni(V(2MQ@PJqBqHA(Jr!C^cLAHdYfz(y+byO-X&wvdjKqYAAm(40I=vo02X}& zz@m=15u;^O=7JUc6qVEA% zv1{oM5{X3-A)$l6b#p!%g2{Td1!wAL)zM|-pAH?mpu zJJ~GygKQT4Nj8iABAZ2jlg*-k$Yzm~Wc_xt$VbMa1OOKK0a%m>z@h*Ei<$wjCRNh4#1)?0E;pJSkwZ5MJ)kX)Czz_5daoN0a(-; z;92x@$UjO12~W=yaegt2#^~E2ZIXiOms->zDR9EYX3+t(H;X!w&7uRzW>F^DEb2ry zi#n6dqAp~!s4LklI*4o*9ZbfeLjYLR4S+@60a$b>0E>D6u&5^hi+TaDs5bzMvH)0= z4Zxxt02cKDU{PNH7WD&QQGWmy4FF)#KmZmE0$|Z#02Unvz@ozeSTqFSS=27czeWTJ zNA>6S+b4NF{lW|hLz9B)ms*sY6u9G3vuHT&&7wTAS(HyUiwekQQ6bqZ8bLOTMv~2< zBC=UDifk4Yld-4-fJLPMEGh$FQ8@sMDganC8h}NW04%BkU{N&yi)sK^GzNf0V*yw+ z4uD1D0a!EvfJH|Eu;^$2799h?qGJJAR13hO;{aGx2k?X3-3?Su~Su7R@4?MYG9f(Ht@s z%>`i5JOCCo0I+C20E-p?u;@ep7A*u|(INmAEe2rGNdPQ58GuDg09dpXfJLVOu;^3( z7A*r{(P;oIIvs#T%K=!l0)Rzl0I+B!z_Vy_lE1@cV$o{-rQ&+CXtSQtRwV`1FSY3G zq`=TC%%XE>Zx)?PHjB<9n?>i7&7w7Av*-e{S#%-UELux8i!LIYMHiE?=n?=HT?)XW zbpR|{55S_!09bT60E?~wV9}KTEV>GSMH>KEv=M+sn*dmJH2{mQ0btR!04%x=fJN5> zuxK*?i*5j5(TxBsx(R?qHv>G2&Pwu66hXqH^~*!6&7wVeM!O{`sD7zMTap6HuQH47 zpuJgiC)q5zi)GkA0a)}I z0E<2cV9^%5%1;hlzS%4)puJgCNH&W`kj@M-0)R!M0a#QCz@jPu7F7eVs0M&VV*pq*7JxB)hQZZwOIr@dKp0@*B@K{ktKlFg!7WV2{C*({nvHjCzx&7yf^v#5cLMe_kzv;crb zCjzi&ApnaO0kCK>0E#MJoYVv+kMOOf@ z=t=+AX!Hvq8cMgSJw1i+%3 z0a$bk0E=z~V9{*=&!TgZ{UstuI9We;eXd!QqZdiHCkNFpwdk(oz|7msqPuBt7TrTO zi|!?xMfZ`-qWj5a(F0_&=s~hs^bpxB+DbNy9wuYaBLFOV6o5sK0kG(C02XZnV9^r* zEZPphq9*}Z^b`P#o(5piGXN}l7Jx<10kCKX0E?anV9^TzEP4@uMK1xc=w$#Fy#m0Z zR{>b`8o;yYj%5FZB1m|;cJA*qi!M@&b|weaFSTe_a^S8lX3<-;H;djTn?>)C&7yb7 zX3=|Ov*>-YS@Z$fEc%da7JWoEi#{e}(I)^b`V@dgp8>Gwa{v~70l=a!0a)}E0E@l` zV9_@KEZPmgqHh6M^c?_;z6W5@9sm~o0KlRj0a)}C0E_klu;^z17X1RiqF(`6v=87} z^hUCOmk1JmQor``rdf1YP{MD?LG?>5`YSo`+nr|7-?TT2{vn%1PKx#1%_1M!EJ`4o zMSikblt?y<0%WtO8QClflCdZRz@j7o79|6)CX%wHA|-IfeP+=}+M7j1WV2`#*(@q1n?)sLv#6A87L}3BqH?lXR6#b2Mw79q z5`aZj04%BoU{MVKi^c%3XeHt_Y5r9RL09Z5`fJOBHESdtqqNxDSqJk9vO(IBmpuQVhXcm2}2c~H$LG?>5nvoLN z@qk%0llErOEV5ZNn`{=%A)7^W$!5_!vRTwXHjCzy&7uWlv*<)J7A*u|(INmAEe2rG zNdPQ58GuDg09dpXfJLVOu;^3(7A*r{(P;oIIvs#T%K=!l0)Rzl0I+B!0E<=uu;@$x z7M%saqSXK_IvapR=Kws5j!*IL5kbOR^c&VEm_@J3Yk_l9g6fxAbU{iWW2;$oA??kg zwPdsCBC=U@G1)A-glraFN;ZqukGSMH>KEv=M+s zn*dmJH2{mQ0btR!04%x=fJN5>uxK*?i*5j5(TxBsx(R?qHv_Qf762CA3c#Y<09bT8 z0E@N&u;>neXVLj7{sAILc!yq4uQ7{;=ylPZDM9s1ExI=)F!m9%=swz;Mfa19wD1WkCM%z$H-XpH~@>b0kG%^02XZrV9}EREP4unMNb2; z=otVOJqy61=Kxr=1As-(1F+}?02aLnz@nD`SoAUgi(Ua>(W?L~dJTX@I{{eqIsl8_ z0C*PNo#J02f`m`gufyJB7G0+YrZ-c9>X%ydPDS(2M>dPzC!0kdkjm-vF>^Hvo&i1z^#4 z04(|*fJJ)%So8w`i+%)P(N6#@+6%yL}sQl%V>h7CEVbPqvvwzEtbUn?(s^v&c_2ixSCZQGjd~H6xov zL9$sCBAZ1?WV0xlj72E`EJ_7nQ5pb?(g9f19Dqe(02XBcu&4z9i&_G(s1*QOnS(dXmkeUSzYVH`y%8 zB4bfD0E=<}SkwoAMSTHS)DM6~{Q+1s0DwgU0a!E$fJK7=SacWwiw*~1(GUO@4FzD) z5dbVY5`aa+09cd@z@p&*EXo65Q9b~R3ILu(T~hsJB1rgf{YX*QRIjHW4ofIZ4XR&i z(WunG?5EA5V%nQUC1kUxlx!B2kk?3R0F`GF#s$Y z3&5gr04y30z@iBNEIJB+MMnd$=okPN9SgvsS^yRu2f(5_02WOIV9_K17EK0VQ9S^Q zrU0;LDgcY70kCK~0E>s0ASG>04!Pwz@k+EEIJc_MP~u9Xf*(f&IVx7IRGp= z7l1|Q0kG(NfM?OnRR7x|NO+-s?s}G4)KzaDtw{~4Uuw}ssewOsm_--U-YmL=Y!+Qg zHjCDg&7$>Wv*@ML(FOn(Z3JM^CIA*)4Zxyn09bS_0E?~z zVA1seEZPjfq8k8MbRz(ZZUSJ@%>XRA1%O4j0d02bX2z@jYxEV=`LMRx+Q=q>;j z-3{<8x-iwB`Mg-PSU-2Y)-0;lw`T824XR&i(F3W0+!xKF2Wf8>Jw!H(wvx@FhskEq zBV@DaQLXav*;tTS@bd4Ec%3O7JW)K zi#{WpMW2(+qA$p1(U)W_`U-$WUjwk{8vqvV24K;*04(|rfJNT}uxJkei+%uL(T@Nu z`U!wVdjVMVGXRTz0btRu04&-Ez@py(SoAvpi~ay$(VqY;`U`+Xe*-*=-c9x2B7%gY zde`wivuJQj3IC)9)i1TkpB8vQ?q|0cp6vt@)0+1517x$P8QClflFgzJ*(^#Tn?=cF zvnYjZ7NwHSqBJrVr30|2IRJ~o04&M?U{MPI7PSOmQ7ZrzMF3b71z=HY02Z|YU{PBD z7PSLlQF{OubpT+|0RSxO2*9EP0a%m?z@kn7Eb0uvqAmc>B43*SM-e1EPCsg$kmmK# z{!)v&rUlh6wWwQKpylgkQFq$gvFK2;S=57U7WE{XMZL&oQE#$Yltng+vdLyq4%sZ~ zL&l=M04(YUz@q*DEE)j7qJaP`8U(nKu;>T?799z|qG13m z$^~H2Z~zwN0k9|^fJFrWEGh(G(Fgz*jRbfW9h~MLB!YxXwR3-nS+ug1grc;d`lS|? zrUk~oX%>~y-YhC7n?)65vuHHgEUF}%MO9?8sG4jR)sW4iF=Vr7EE$W&0kCL10E;F7 zu;?fN799=1qGJG9bSwaiY5`bu8~}^z09Z5;fJKu4STq@cMfCtIngYP0sQ@gR2Ed}} z04zElfJG+&uxJJVi)I2mi;C0yr-&fo&HB0P60_)by-1ps7F55~qIqe74R4u64YW6l z=9A5$1!S}6M6y}5kZcw$BAZ2v$!5_>WV7gGvRSl*j73WUSab>ii%tb#(J}xQod&?7 z(*ant9DqeD09bSe0E<=vuxJ$ki_QdK(OCd2S`EOWvjJFi4gibJ1z^#604zEmfJJKn zSabmZi!KCs7R^cXZx=zrUG(rX*DU%cO~Tr=p!%g2U78m7>>aac9qrAc^<=Z?GO}58 zIoT|_f@~IDNj8hFBAZ1U$Y#+-vRSl=j73)iu;>~97F`R#qU!)ybUgrzHUqHe1^^b_ z2*9G709bT00E=z`V9~7rEV>PVMYjX6XbS*~?f_uXod7Jl3xGv;1F+~G02bW~z@qyA zo<$d@`IFxji@wrh(IsZled!YJPYbGFYSGrTK#%v$qK9d37Ck~XiykGLMURoqqQ}W* z(KfPK^aR-~+D12u;_UJ7QFz#q89;J^b!Dz zUIt*%D*!Bd6@W#r0kCK%0E=D+V9^@@EP4}wMY{l4^cDb%-UeXNI{++t7vNd+V4A-| z1PQNiE#f?67G0rlhrE{-RKL`skJ18jKQxOzroCD83E3?Alx!A#MmCE+C!0lIkjzHGa58zq!L7M*(5hT1o zKi>GES@dlu2?^;z^-C>kmL9n8W3wnod$TA+Hj9$TW>GTPEJ`7pMX6-7D2;3urIXE~ z=47)dOva)N02Z|XU{Ol|7PSIkQ3QZRQ2-XT24GPe02Z|cU{N~&7PSXpQ3n7P9RR?h zjsPq=5P(IQ04(YRz@p9oEb0QlqOJfeItYM82Ln8d64U+fiXh>>dO;mX_j>x%^`}A) zNe`-DYEh5$z+a!5MLlV67WE>VMZL*pQ5M-O$|jpdIb^e_57{j0OE!!8k7~omdJ>B2=GqGr`zIAq}Su{%D4k<|ws$XhRMS39b z3$ti6?aiV}vRPC`HjApsW>F2Li^h`8qH$!iXgt|0nn1>)qX1ZRGysc^0btRw z04%BnV9{{^EUE)w(L?|iO#)!iWB?Y`1F&cc0E?yquxJ_pi>3px=y(7YodCe182~Jr z3BaOR04$mfz@j+-&!Vz)|1=RK{F8pXvD_@`sqcWyO%JMHYSDu9z*%3JMJLkUELuo5 zix!d1qQzvh=p?dPbTZj2T0%C9mXgh)Q^;n~sbnl#2Ed}z09bT70E?CbuxJGUi_QRG z(MkXotpZ@tnE)(03xGwd0a$c40E^B6V9~h%EIJQ>Mdt&sXbk|1E&yQBg#avC3&5g_ z09bS}z_X|!-G7@167H%evH50EXI1Kw^q~5s7G0Jec(jMfU)(=w1L8-3P#;`vF+=004^~1b7y$ zOZV>;LBe0_=dRbAMfnL59!d|YUuw~#>4C_1X3=A`H;W!8n?>8mX3-O5vuHcnEP9e` z7Cl8ai=HN%MbD7UqG!oi^c(<-b^x&Gc>or@0KlRb0a)}B0E=D*V9_f8EP54yMXv#{ zXeR)RUI$>&8vrbN6M#j#09f=E0E^xRV9`4OEP5A!MehNy=zRbdeE{$*dN|#GmnjFX6-Vp!%g2eVQIPYL8j;8STxY&&g)d7i6>OOR`z?71=EMnrs$*LpF8`Wt{n{{XPaX>Q$iEb;-cC;@;)egGCF0z8X8PWLYpLBbd7=dM37 zize$w)&k9g>X%xS)I6~1N3$rI_GVEE*(^#Wn?-44vnZWx7BwfEMPag8ltDI&T9D16 zmSiky1;C;R0E?mkENTtFqBa05Y74-kb^t7D55S@h04zEHfJGevSacu&i!uRN)Cqt^ zodHF5=Eb2oxi~5qyqJCtvs6W{(8bCIS29nL9L1Zi%48Wqp z09bT50E>nIuxKa%i;e(b(UAZw8V10kTmTjg2VhYi0E_YgSX2POqCx-`jR0WLNB|ZU z0kCKk0E>zNSX2VQqEY}Bl>t19dN%i`{wx-KrEhxlGK>1V9k%8{^-C?PY98qIt65Y{ zd$Xv9Y!;0nn?+;EX3;pZSu~z(7EK_VMMsg%qNB-X(J^E!Iu?LMwE!$S4uC~<04$ma zz@kY2ESe0!qIv)pO#xuhQ~(xD17Oi~02Un&z@ifXSTqBGMKb|dGz)-5vjJE%2Y^L$ z0a!E-fJF@e&!W-I{gom}IA1?fRB0AHpcc(<9#p^7qD9RE4ZoR1i)n8bokTW^P9~d0 zOUP!?QnFce3fU|=m24I*Bb!C1k6MQZ?9bO8X1E(BoFS^ySZ1i+$;0a$bi0E;dKV9`2& zXVHnx{p&=K@R52FTWA(l>-W*tHxH^`YSER=0}uRR7F|VqvuFd^EZRsmi#CzXqN~Yf z(KTeV=vuN_bRF3&x}IznZ6;&U4FD{<5r9QE0kG(102bW>z@l3LSacfzi*5&C(G~y} z-2uR&I{{d97XXXy24K-W04%x}fJOHKu;_jO7CivKq6Yz3^bi1xwgRx|VSs1R<<0%? ziy+}X5(8J5MYrok(j(1->X%xyt$E;|zs#a1Xm1v6C!0l2lFg#0$Y#;gWV7fQvRU*j z*(`dFY!>Yxn?=u)vFHT=7QG0-qL%E0a)}p0E^xLV9}cZ zEZPOYqPGB8^fmyC-T`3Iy8tYD4}eAQ1F+}=02X}+z@m=;SoAT#v*@wr{;q$EMHlJ& zXpfskE%hSlljcG7OD+1Md7!}25yrScVx5Z zd$L)yhin%8K*pjU0a)}C0E_klu;^z17X1RiqF(`6v=4wqzX7o5cK{as0l=a^0a)}G z0E_+xV9`GSERs*mUoIOd(T7Do02Ue zR{$0r1i+$$0a$bh0E@Z-u&6r#iw*@~Q4atX^#phpC5Qc6M38W?UJ9jzy`KIweQUN? zIH-Q9MLFTXD~V=NAKIHmeaU7~KeAcWpKKNlAe%)4$!5_YvRO2kY!)3xHj54?W6=-* z77Ybp(GdVFIud|I!vI*63&5h`04&M_U{O8*iwXc(R0zPL5dbV23BaNv02Yk`U{Nsu zi%I}kR0_bNG5{8p1F)z9fJLJLo<&(<|1Tm)c!|D`mTeY|*LPzp!$I{+EgBOJv<{j@ zV`*;|jU$^yH%0Z1%O3U0a!E*fJM^*Sadu9i%tMw(F_0<%>-c4EC3eG24K+~02a*!V9`7P7Bv8{ zXg&ao767p5M1W^eb=W^d1PPz5pO~#NiymzuVPQC^eyK$#hXcnXnMF%zZx$^jn?kcMe6`qv>t#(mjSTo za)4*i;;{d85hT1RQ^YyRESj!2kFE#@)i1SZV>ob4idnRY_GZ!5WV7fRvRQO3*(|z_ zY!+QlHj6fs&7vE~X3>pgv*;!=7TpZMqFVr1bSnUhZUbP^?Eoy=0>Gj>09bS<0E_Md zVA0(GEV>7PMfU=*=so}z-4DQ`2LM>~AOMRV0$|Zr02VzAz@kS0SoA0Wiyi}b7F`wg zKO=&K%k^#i4Q5eK{X)p&;h_4Z7Cjjbe3fPvJwa91#iDI` zi)g!9bg8}@`*}F1eyK%YhXYw*v*;Vzn?<|HX3@7~v*GEZRdhi+&)RML&|w zqMyiS(OxnZ{S3gOUjSJ2D*%i30kG&d02ciYz@k3@So9|Vi~a&&(cb_p`UikTPKI^c zvB(F&q67dI`2kpz2*9EM0E?OduqX(?q7VR!k^oqg4Dc-aGVHGwLBbvN)B9hUMHTve zw3LjX`lS{%&j>7NVHSmHZx&^c&7u}$v#2H6ENVqIiy~yRC`vYqT9eJ9He|D?Eg6g2 z0kEh&0E;>Ru;>5)7Ig$*(SZOg$^>9hCjb_824GPa02XxxV9`MUEIJr~MTY>es2c!_ zx&yH2PyiP70ANv102cKEU{P-X7G(iEi_$Xumx&> zBk)iwv#3Aq&7uKhvuGgMEE+^Miw2X;qQl5$(cxsXXb9OX8cH^cjv!;vkpL_j2Ed|R z02U1gU{M|bi}C?jQ~0K}(FEF?MMsg% zqNB-X(J^GR=vcB@R7*CCjw72zb!4+>BH1jOM8=}Y04%BpV9^u+7EJ|U(KG-SO$T7n z@c=A30f0p_09Z5=fJL(aSTq}eMRNdHG#7wH^8i@X0KlU804!Pnz@ifYShNs;MT-Df zv>4!7G&aM3um}>qPp_`WnMD_Ml5kQ+Q2kPiPRR(2XloXoN_(?t8QCm4jcgX3PBx2{ zlg*+PWV7fDvRSl}Y!?BA7A?u} z&k#Yve!c6s)GXSkKW4NcBdC6sgGW>UnAmM?j zBF@!j(HW}L_KcwVr4~Jt5qRwYv*=mcn?=u&&7vJ-v*>xUS@Z(gEP9b_7QI9^i(V$1 zMX!*}qF2dS^cnz*b^@^IbpRH<0l=a+0a&yPfJJWsu;^_77QF+&qIUsU^d10<-UndO z2LLSk5P(G=0kG&}02X}$z@kq9So9eHi#`Wn(H8(L`V!z-^i+m_p9m8ELEnvi+AKO< zzt#9vMo|4yi@wbWw9Pb&zN5Wa^gY=u+Cw&rejuAgKa$O&pU7s>Ub0#AGubTqg=`l6 zO2(pn04(|qfJMIpu;>o}7X1mpqQ3xG^fv&D{sCZ-)55y#SmXm>Q33#q`~WOU1Yl7B zfJMy!SQG?cQ3!xVNdPQL24GPN0E!(W>E(+799YtR7XB3?NVrVzI%c%+diqz1Jb}I~g6fxAG_XbBx~^u? zAljQngUM#mVPv!DaI#r6glrZKC7VS@kjEXo65Q9b~R3IJGC z2*9Ed04y2_z@j1m7L5X6Q856EN&r|?3c#W=02Y-4u&4rnMWX>&R0+VMDgYK$1F)zD zfJI{fSTq*kS=7IU|2YvPyk6fr8(>N& z2`&8LL&Tz^^@C|gnMKd&w;GqW2&!Ld(P=FLIo-{o(`j!OEhn2rE68Ti8Dz6)CD|-m zMK+7hB%4KNkjSaco$i_QmN(Ha02T>!wM3jtWP7Jx+;0kG&| z02W;Wz@ke5ShNm+Me6}rbQu7PE(c)I6#y){5`aZl0kCKT0E;#PuxJy&v*^?o{xKp* z_*#j9WoFTR`jc2!w+O0VPAexN&?RY8PoER%C0E@}q+EWEHZd|+-X#e|*2;-6HFA$! zRD~mN%Hgb4qlSmv6g87I$)-o{>l8?Uw9F;9$q; z7b))MID;Y=9O^hjB5(F|oMDjzvK%KrGAYM#Mn-Pz>o_Hm@B2GWMWp{A$El8-e3;{m zi#$HWagL4zk93^lBBi;GGdZ$0&vB+j-YRgM8Ic1=I?kL({V2zoAGx{2aTY~>D07@8 zk%6NfXIW%vmE)|4JW=B~XGW67InFte@(GT!CUWu7j&o7uonswmU8GZ;<6IG$I>~W1 zMsBTloNFULO?8|bB7={2oLeHN&TyP9ktb(4&fSrexsG#xWORe$Y>iyHz;PanytmMC zwnw_0&9W7I(T{GF&ESh3a*J#SUsV5^eOF&p{~UQYUsV5| zbWdMY{~&O-FRFjhwVyAlf0A>MFRFi2afmOfe-v++FM8!;vO#=N{j*dfeNp|pLM6Va z{$ZF3UsV6HN3}1if0|*OFRH(-f3z>EKaPH!FRH(8J=qu4pC_K?i|X&o&hSO`2SVrg zqWTMu^LNou_ z@j z*B8~Bryu&FdiU#7UsP{jeCdm7|8uu5svU?uzNlUS?)63W6u!?F)no9VJ}0?jhU{3^ zdb?cfHnOMq`lhrD%0`t(8^6RWW@P!CHfP9Q;_KV*5P2opd(mmrL-rqE-!f(6g_UcI zeED1RzP|O!bpI6}oHhmW9=NaXQe|&QmM!75{j|NX{^{q-^JJgn$U1P^<)sT7;4-J( zC=CNGoS^eHC|x|2!75~qeS__lKjph&zQZj1)mFmc77}Go_YJWyUT15lh37g;ID*0C zBFA^6g(^8l_=b6*y*zhx*}w1Q6JslyWh~q9!kedb@QrSkasTgcY+TgAR~bk>{E<)6 zI{2yrsd*nCy3lFA!rFB0ZEYUeeZeb>rA;8U@~ZPwrAf1l&FjAZSVmLTEaS2VZduM-+eqpfGYaMMz^(b0Xf)7|Mz+ =oz9z&KRm-}f0Hy>EKSa#$?3POeN&q> z%XstAEB`vlZ8JRQu<7n}&fWX_vL#OYr=-zJX|%y>D& znl1A!vwOkqr|*;T$?Sf4$7lC1a@zNnHMUkp6O@1MdfB}4iF;0Vr+v{CJD*?TPW$6a z&JrZ+<&%Mj9`3ZSkTyEMhkI=Tsr5e;4s)Bl@W-XkdaH86({n1_={$4C*87(_2OMkD zk!b`nR-XOTRCm6vpZZCOJ72%;x$-)1zE+&^_Unrsr{mA!qyB4_;BVH^pXoUIubE%M zdvcc0f6Wf^CwIJ2%+i0&68+5_Uxx3X^p+|9^!DjBtuuV#*5YDUCne< z-ccmOZR_U-K)*>*_V zS?TWNWrk&6Yx`1WmEuvN^OLV)gFc%h|KtTNdU*3*kfHv=Lq3cu zgO1h`lKsTzjMJjO^`fmtZ_sDn=*Gp5ZuEwKk4s#V_LW+^7GvXERQ`t+VYfw<7O%ya z_!d>M76}RN0?A-{(iD50>C&3UkCXoSRQh$ zwucTA|A@~eaxC{duSt^x-yi8|j!zykto-x!?wvKSE^A7|oUDdnCSTnzwk){Mia7)lXh9uf8GfH631t9-K92-t?K%=TASe-pQIaduDxB-HiH0 zS-oe>o>Vs@t6^H*y!xzp^|R_5>Kd}@`_wkfUod(4?5z2-XU~{4t#10PhODWRCe_x> zo0*l9UE8;|Pj;W2+MH~Ky#)4}HG5Wlull-)(|hG)_wL(EU+yh0H+d;*`m9Ma7EG?s znprn#+Volfzt2X);)eJ&F?Cv2?!3thrq7z4H+x=vuh_a+G=HAEO1w2vF>m(qvd$Z_ zs^-+qJE3sFtlDZ>mZ=pp7BtjW<_;+B&t{T^{eL+2{}TyLteao2+rn{7qq>|ay(g(< zwUg_o)Ge4XzjprOIrR;_r>VSR!sO|*=1UN9#lPA~vuDnnJ*&2E&U9hobyZ$Lt*n(v zc`g?w$20t#uG8|66Y$ATrK=9<$rqwe9in*eZ2z#f7?-+@@SS7Xwgg>G%F6Y zbnDPSN2#IAKvFY*+K@nN2}#X{2BK~~!bwQ~~ zH>!W9Zv6u7bqTx)M0&(cY5ysAZZhR=@l)3JePl)>J+iX0vjQCt>M4!=3mI+v{O>>3 z#(aP;kRc=Ww+f_bX%-H2)Y{pjvLf6lOXm(1mvtrhn;jZBK&wp4jlO0FPt{eI)wx%o zTbDq)_WvhKrrW1mcHn@HGLrvsHT=IFI4vu1z=1LwodQY6y8cA70<8~>)64|hDzPF`HgqRP>=!^N@uqAG7rP@svaMUDs^dY*?8M@jiYck zTUB|LI|un*m+Vs?77Y zOg1mOJC-|dqO)zcLH1&ftjgG!i;5}>b88Fo@@jL27uhbK*JQVJ4>S2ixg%=JYpN@1 zs%yuTmsHEX6dMJ5h8|$_P^5>kxIHz$U`&x*hYhc(^47TQC-KK7Z?{shWrgdGuInbQ zdF43Sy=%+I6jTkgEq&@fJUY3m_tE9GITwXyze%vhE3X!92b*>yOiVMcq7UmY|9?$l)A@urG zX05!YQl7~ER#;M$*LVhSjnxBNY}MuTiS6vN+dFLj>iR|AAty(6%*hL8&RiUukh`B0 zlovJKpO_6fK9`nP>bB7XsHadLch8wId)CxUIhwhwpG?bL_#AmcTUnu1<&EbrJs-qg zvjcKvK}mso(ALHUO{MZSyRHD)vPFg78uF$xAZ{w|0ZF%%9{SwVoXuqui8vb6=H}(q zROaT{u`M<~Bjp4*Hdhw3x~Q~3Hkmt)L9tDq7dOEQ*D2G_R=|?w-eMt47L2i#Mbk+c?U_O|rB=j$3v$!<2Mq>L%<>MNhcl8w8c6GeI~-0vt9e{~^; z0(Td7S5Iuu$m!o?MC?9nt+*3?6LJ3IX|BH@qFEO65pYQ|X?Y++$&(tdOdaaff8wEy*3P*OL34 zfW1{!S&&yC$As9%Ydk{etj4c#T;Fevv-RVyic4f)Xx#qH#faR}(%jfw==zb1E>?@| zvF@sB+^chPTsuaT)nw)k9-OH+x_aki>aDKqL4EpVcAHl}qrR@8zI$e`nUm%$7&>Y8 zy!rKudd=+HSHS#f3uaD~I%US}y7|52KG{$?2255ULr$4j^ma-|C*O3C*&pK^kS{nR+ZO6&Wi36*_NdTQt=W2&#! zn|}54=6U0k{@Q<-8SlU>d#=uvcLkaw{Z6+@)849{R~j$1q>pO*oA$Zg)hy^*cg^QssY>U@F1cjq^~NR(6}ML68t5gY9FklK+(8?AeX;K9 z02_?yLkBb-XQ&DS!pNe&JY{iTk4v!+%e+1_J3oq z#I4la8tGljrB-}zS}%`Sb)GpRq&MPStHfS#b=B+9@-jUbxF_J8|Lv=`<4E_+1ZwP+ zHSKJvgE7&Wk*bQKTI)dT_MnrO8ylM(QOBI)+Y zrYMthncPxflCB~;BdSS}Ty{xShHckhwKUWi+fl?B!R@e0{J64GDRIq`Z|?mWpwiYx>3B%MX+gcao# zxu=(kTsgbAL&-V9dm{U1lfk{)hIu2U6I)Q?4kCTn*yv*WOX1ks8o6&JE7L}3cp8e>CMNv~CU`PP$XwZ^?k`+w`L$^80>3#Pg&T>ECsr0%J? z!#(x9+sC}Z5*A9AOM0iZg(bOFjqP}~rb5NnZa;U%_v;zOHeFs}UgKuV(HqoE$!=zN zr%=}e@9w%jjlW6lcHQ&XGG}@q1e1of}M^I zb&Rpq81GxGgKO*7y;bZ^mIHj_sm;6Zt1oJ=&K*c^f-=|cxmdQnc$+7C;eUQt!n?`a zc%u5(Q7DK0K#txdW!&+zTv${h*K6@z|Hdnps;WGDd#1^HKwe~&8=H0^G26RxcS|4d z1lnYln1R?)JhsB(j%(TrWI!h2i5@$zx@#-`hNdgRe>yFD2kF>NFUIS>>B3$Q)XiF1 z;~n7ia16JDw`|j<_e|ruIdZ$j-Gp)?|F=>sgd7d!WM!B3_GSwGqk&Bt(n79R#qNB$ zQi;2S;lMt)kFW6Q7w=;WZqLm2(75#!uT_(GUu*@|logkikM-6s z9VfkIuXF76N?7B=;(4&*TEV2kJiY?$hd1 zdPzC)w?A#Hdf&ZJcDDH2PfdF-TrIgHmCY8LFL#fXlVEjjrCwgjUL}_@|838WyGd(v zoa5bL)zNzWF_u?u_}kTxd!@oXe|P$EhjZHnyvwK9jY`@7xdt*td0Q{XyT9s=MsH`j zPrOTSrmTnXre~+vjvK$Pd2=G8aQFMz`p7HEEv<;V5#{NjZ_w#@8{esF>^$W3iya=> zp>p(wr8jF$jzPHaug%N@GddT~9GBaKru%YBop@m&s)myH$MZ1ILQ9+~wH zb^N8`k@U4+I_$eWy8(J`}h(yD5z(FkrQV+0@BIkx;?BF5 zl5LlIUTW+<%6sJYR+rA6_HJUGE~c*+1n!ycKXq_b8nup2n~tT>mN7?ecg5B(>%zO? z8TXdI*VAxUPW<(&+a(+;Z{zA4+2!`mEVJa@Y1g;z_CH(bSy12j<`~2qr?ebil3P|R zdv1Z;B-`)mNf%}R!5cSBNx8f^C&v-Ff0|nscQa16PSYDKUI)j!-fwcAjWesHewMfY zG~Q?R-cw*c8!zRW^lo%&vP0C!QZlQ$=DgmC`-}stcPq2DmM%0Sjyq0|tSpvo=k1b3 z;z8p*y0N*^OXrZfUrW6?q$gc(bv51%)%%RGL1QT^{^U@L#8$qDueHC8 zudT10uf4B>uVX@IpM0(0Uypc{==|_c`~ZIaaA(}ZZ=XsA`Sr7%aSy+Iu2Vl$-S|j! z%}4hu@KJ3B*18PSa1B`yKg?S=__#G>=O-Ab?;kIdw$QR9wA1a@%mG40~ zC0gb636^!sB*^MlM-ybD>YCIlP2DPA?r{?2#ZFpfGjubqKI(7-tPZt0+-il@8msbg zVt07?-ke+KT0Pb33ae|ZZnAop)d#FTYE`~`=8k8F)mN;_m&;uKp4CsRer5H0t3O+n zFNe9q>nG`TdGyzdwaS;j+}hHr{z{GV1FarpwTIOls{^eLwVG$O$ZEOO8mmWHt+P7S z>P)K*Ru@}6)#@2m&$fDj)l02jY4sYbH(I^j>OEE;vii8yr>(wd^>wT7TK&Z8*H(Y9 zy3eW{TIhgT3u>& zh1IjIUTAf_)s0p+TfNQdJyy3`eZuN+Q^^%|=;S-r#R z{Z=2f`jpidtnRe>j@6H?er0u!)nBdtZ8adL5?xQJR$E$aXSI{nZdS9b4zN1ZYQEKC ztCd#ATRqO|RI9VBF0i`9>T;{AtzKYtoz)FiueW-u)w``eWObX>XRW?$^-ZhqTm8)H zZmU08{oSfhzD}X*CuFs`)u`12tai29%jy8DM_L_eb+pw9Rwr4VVReDkQ>?DCy2k2y zt5;jS+3MX^AGZ3G)t9X9vigzLudV)M^-rq-IbrGYrdw@oHPdQ$t9`5)y-D7Sbf0iHmf_V?zH-z)z7VdZ*`wl`HM&Hd?s6M zWwnddfpV_a<;b%-UM`h1*IPYV&e57zS-ny&l{DXI^-(#&Yu;h?Be`bK{H@i4wuaUTfI}h;H&vjtNY|jY?|eJ8E!q|K(7{CUD3(Q7g&9+izqi^=E<|+r{#Iw@c==?jclY)3<5qv~@8zIexM;g!gS=X5 zb>(4RUTgLFAzpsVYKtSie4y2Fxn8cfdR3m6Z?^hrftP=!I=;^otvvy?l_>W6$yO30AK?&&zjM{aP+?b^H8kHG8d>hgv=HVlOYZy7f{oKWjDN zGA}o`I`RrH*H}I8DlcDdb>~Jee`K}YHC{f%>T%b3d8XCtH+%UmtGjRX@^4oA+~VaU ztuDIF%V$`9WQ&(~SWUdk%NbTj-Q(r4R@dC;XbcRZm@dGk6wPj>W_Q9{EyW^zk0dA>M6f@ z`E0A(rGur*_lnizzrEbrYK7c;(AST#dWrlfh30FlzAL}bq4_JTouz}OIm_y_Brh+p zdYk-shra%h)xFY@)9g$4>S6M89-2p3T_(Tlq4`{^PstB_XnxIVs{GQ2=C)QVr6Z`h z*6KR>?GMe@S$$uA1Vr;UR=Z|;ImhbpoxQx!>Xxove%R_S@U+k&w7lEu561tr?8xtJXuE(`8GqPvE30jdceUKj zYA@r5Ssh`u+G?HESyoTBdZyKjtzK>QcB@;p%5v?odXU`I(mc-UxmGt?-Dx!>zjdL* z4Y4{?t1Qo4t0!4K#p)`nXIs6<>N=~kO5E|uDBK#c+SY2O)vi{1TkT_YuvPc|h|Je` z%g0!qY*kK|?)Yb0ZLqr3s+^wO*Uz+ij@4_e-eC21t8%z?hkwxOBUazA`nJ`NtbS&7 zw^iBw-S+P9#K?T7`@9^r+RmzbA4FakJ>B8^Ssi3mE^D2Hkav$vw~IcsCR+VC!OL<> z%1LN0zmZ_v>D{n+=KQ*eQs>X}>NK9o=cea7z4e32PVb2g4Nh8_OLw9#?w?Jx7EPwc^Kr%R3>->wtoht`DYdXa8hY<%nG zIc?;r(`tY>oIckFuU#z9xw$z?7!QVfNq|1*@vaOf-LTk0 zmqQ;rM7sZ2{N`-;9?A;ZlP*jk>qkbgQp z-99=^_91!dJT^&&(N8lL zXJ_Zc{XbwpKR0C$93TT`9+!M-K}n(ab1&XleR3zB@hVAN?xujZuXl6W%8|6!S9{7I zELpx~=f16TQ?F{h=fI$E?XW%7r;qwEp=Da(n!@e-R%G8*ynSD2?)H7#vv=-G%yD}B z@pk#1X{omt-(J*i=JtI~rwQ)=m%0DHqyOh@-G+KPtib zA$$+q(CdpXbBA6pZN1^+hi$ocS#y~`zsy6vDXFPHmyiRcu_FY+Ory)Yme;a{upsygr{&v~AzD z;g-jBnYPaN=g#uIk5x??^-0~NqDjS*-KlHqi89@5GY60Aa$L)4>uspl>SVt9>Kc;m zmbXpjYvhmjG;EVO%Zg2TxK8=_9^RDQseR@C-~9xga+yqdyF2A4ei~MPx$k#(>P0g3 zqM}j7qui;>cJ_Z#Crds0lj+CEHXeG~upjIC>e|RFj_6#))`QGv%U%2AZ@9^rckN5G z8nT+|)`7OH%|^wRqhfTYVL$e3NGN@|PL?I3_CqHe9hTNEJ=6A(WzLz-ppmoApZ89y zNU+TkpYMmKN^X}ox&}>tdHd>PuIu;euBF*8W)JCb*)X4P*+#!_+3u6CAN9|L@4Yzj z(}&JmS9i;f^+hkAkumgxD>{9&@x48j=M3NcK<&d%o^|@YzfAe6AiH+csr`RGqR-D; zzph*}x8}et4;=c&_0OF6oa~gt?pw7dArJ~VyFYqr)Kh6EmW+Ms^{qSC-}Xizl;jko zu5tXEgI64K@Y#}}yFLYePMt2@pJig?~eU9(R zeTki(l-IG@d;N}1vIU2a7ONbetl5n1`?h52ntkyO`JKnhM-{yyt(-&uc)Q)SaNoye zZ?4*x+A}fRdlu@sa=7;_v8UEAcd74377rUWtSFZ)nBa67T=KDQMcGp)B$VzPROsLG z@RxheA6(p5wqesfuXk+E>)T|{V{hqQoHZ(|D7(qt!k!oG(nH3#JNwY09>qO8dp|GV z<7>_I4k_+7s#{Ta_myE?TFJ0mbJk9OH}TJ%2bD8Sm*TFYx)vQ|!{`v#On*m)`1XrV z#hpfVF6wNrBwFiT@><98i@!+Jo9E)rnDYY8t(`YTdW|3W*vWJ6I{vlh3)_F_cy46p zYr)1;>{M9)NVj|5+{g>php@P+2fIVm9_kSV9;goNNLo#ezbva>udZBr`4CnN?| z%7u|XU(SjN5`%Zk zj0S?Q$$7I`@E3U=46c;Xhl0!Hc~Y>Q44)hvCu2wnrpuh92IpkTo2|j8q@R@@ysx8N za0DmF|KZ?388Rc7Be#`X1W%UbY#F>rhG`XiSFUg(!H#l!IU4*@u83O)i@Qj-A=p`- zw++57E2dp=hdgf|)L*ad5PU&~>=@K;%7MX-LNbF}WQv`F9b_tl zo2>bRg3rp>CI=VFO05r$?kd0C8l2lfy4S%kWS*Z3M#PjI!Ovyho)4~*<$WRewhZ}V zsE<7F=?kUE#CrKc7syb(eWAPMVj{~I8YpvCF7}0-jen5tv~d-tfcS!A?=KP?++~#Yxej$1eqDWXGpVyLH#tRgYgPsTDjF_bUUt4s_{lv0%#8Ya`LP7F1d1~rMHLUD9VVrZ0X z+p&qE6*8f5iJ|Rc!}!F|tunF+G8Wk`MJbu5Gs|mv^WsDT1IwKAoRAtcLSlYT)w>*2(^ubT#FS5yZ21D=3EWIv8*2EjZ(DMS{ z42FJ|CE67XZI$M41w+@$?B1UeIz~KtASJX~M)qJz=zmdl*I`nZ{ojXYclOKd61(hx z4i+fc6WDoq1Y|A^}8EGotcF>=~uY7Q}f8gc6wWLpQPy0w&p+5oxiNDd7pHbX0$c;N}rC)+nRf(pYw{g z=5qQyT-nwq#rV|*8F!eF{#!(C*6s` z)0#)6Uv|i}<~Pz$w&t|vKIy)!HLbZN{VZ!wYi>&)kaeatr)S?v>rQK4D}5w3eYAP8 z^xrmnw0TPU$nP?{`OWnIfDyBsH%xbT*V)aZlZlbDo3Bd0hf(RjrT-6(p544c`aSG6 zyLsPquXmr_@>Tk8`?oigT7F8unX&oCZ|UbfAm4a8eaH^XH`Y%-=Ae9|Lt;2C-#9&e z7!S@ju1`P9#Plg`Svq}0C*>QLrl05Nd}CJnKpc~A%v>n_Rm1tl`|0y~T)y#q`oYKN z8!xB(azeh*lz#A;!_$p1>34iqzA-S}+bQ|R;Pe|jJKy*+{l2H>8^hBtaag)uXt^kT z=*H(8Kc_pEuR&V!OPdY(#=wLif1POAJpJnVO;{}(reC5d-}oSX7>j)4^u#9pg{h^M z%hG3}l5Y%7r8(cYCjDA1`NqujiRhSb^h-Z;r+nkH^kX{b8(XK3b^41UOD$)mKYd#B zjaljA-Ii}Wm40y7eBFLv(zb2)>syzL9n{VuwO80!DG5wb3$~S&VzgE82 zEj`nxFFmzZYB@FC`Nn)>So$UMTgO^1NdG5n$~V&QFa0jkjr?wc4*ACP^!v&`s%6)t zts&poKYhR(^Ns%LZsc>NjyI*BsA=DZ^7OPjoss@$+4Q07JR#j!FntZ|FgbmyyENtA z+Egr7td=aat+{Ne=o9~n&4Ow6FBOZ&?3w0rrDBPg3#2)qRP>EGf11meiX~&tm*&7y z(J$t_X%0%yiN>5K%@s<;(lL9axnikUCT1B?CyD| zJ2oJ8x4hFmTRwI*?{wD&#%|9$-M2xpyXKwl+zPSV@=o_|#n`QRr@OaO>@Iny`?qrJ z&S@`~?%yi0JLR43->R`Y=AG`}YO!1LPWNy1*v)yT`?p5yO5W-I4UXL*?{xo$#4hqq z_ixSEO?jvLH#By7SKpe;rTe#5?8dYQr2Dsa?1sG4{aYt?`uuloDi$dZPoMwxqZ6lM z(f|G(miAB6p9#gfmDTe9-;$6Gi{Xjbe?m5jqakGDm?317m?30X%n-6^%n-6!%n-79 z%n-6g%n-6=%n-6wOhUGfO~^K}3E4I_A=||!Wc%2J>=2uf9b*%+Q*1(Zj!nq$*o5p7 zn~)K)3E4F^AtPfGGAcG9qhk}YTWmshk4?y!*o5p6n~*(Y6S7zAx{&qDlhWtE{mJxa zTCqW0$nojV_G0f!mXn3-Urb7T{u44bj)sr}Vup|dV}_7}Vup}$F+<3~F+<29F+<3q zF+<2KP?LVYPKE-}@ zA%oJxpW@6)mXn1{EoP)IzyAq2Cys`Yb7O{(^J0dO^J9jP3u1&Y(i$lCgk$igj^AukSk*oa#d_Xu8vK}HL(e~HZ~#G#U|wX z*o52=n~)o06LM2*LT-*t$Stu6xivN+x5Xyp_Sl5n5xXvAO8N2h`EUOvJ=7`At_vBR z9vT&QR3A@|175OQD45OROa5b{9G5b|Km5b{vW5b|)$5b{XO5b|iu z5b{_|LLQGz$P=*%c``O3PsJwW>DYuk6Pu7{V-xaRY(k!oO~?ze33)L#Auq)y@_lSVeuz!TkFg2)DK;TL$0p>L*o6EVn~>jP6Y_g( zLjH(N$eh@O{4X{kf5s-{uh@kA9h;DUViWRj?7EQm%lZ2*+Rw=Lu<0sv&mrB#cA;Ai z={{D4Y7Xg6b`#ojNcXb4&^3p2H|G-Ca!B`cZlN`YbVqAKmmJbP?ICndAz$IlBXr6k zeJtk{I_8k>>3l*<4(XoGFErp~xZK(_TVT4(Xou7RouK zd%BR&m_okRSy*VuA>GqOgal-+rlPT-ylDbbeK=p@lpE@bwn|Sm6pJ=gGOw&?iH2fq zxSu?drR-3&v>l3;u|v_ab|~s^hoa@|P&B}%XnBF6fdWN?1d3J= zC|XgVXeEK7l?94c5hz+!plCILqSXb8)(|KfEKoE=plD5jqM-ssYY7ysEl{+MK+(Da zMe7L^tuNFS^=T-dlYmrL%ug~c9*T}i&*u~yG*q&$tZ0*lVrGK%pQ2&ThoVjGP_&sH ziZ-`H(H3?n+R_e1TiKy#YdaKeV~3(`ZHl%NDB512Xa|9!9R-SZ5-8ePplG;2(Jlf- zBLs?e6(|}hP&7)QXtY4lZURNS3lxnJDB44yXitHny#$K(7AV?BplDyAu4to%@_PwL z_3rd+U9oW}nwcKr6#F$)vahV@z=q=Q^jzeBiVku<6pgb((ZO~oI>Zh|huWd&Fgp~D zw?on4b|{))hoU2FijEX0I!d5uqCn9kfuf@YijEN|I#!_QIDw+$1&U4(C^}J~=p=!n zlLd-S5hyxUpy)J#qSFP6&JZY?EKqc&K+#zOMN@>jqOlF-h0+(Z>Js^Z^8umgnDmvb zIJ=>eePu=GH55bB1^Iu9&UZc(U0{cz3++%e%??Eu*`erSI}}}Fhob3rD7w@RMVHwW z%@8QMT%hO*fubt~imnnUx>}&<8iAr~1&Xc{D7s#t=mvqJ8wHAP5-7S^py(EXqFV)u zZWAcFU7+X=fucJFie?HF-6hl&ozqYrlYmrz&5w)D4Mm;*yB2GxWM5g){SC!Q>2;d_ z6g}X4D0r59w?okrb|`w%rsyewqNfFlo)IW|R-ouP zfuiRHie3;XdQqV0C4r)s1&Uq~D0)?(=rw_&*9D5+5GZ<6py(}uqPGQ#-VrEzSD@%U zfui??x}tj<$~Pt;)erL@KlgcDlwKw)K4_?9Us=&74aJM;^{xLDed>HD`pgbRpWC76 z3p*6evP03Ab}0JF4n?!=Q1rDOioUTa`c|OmJAtC_1&V$UDEd*L=qG`qp9PA35h(gq zpy)S&qTdCI{tzgdBT)1|fucVJivAKP`dgsrAAzEO1&T_I|L-clevQ^3P}C^Y6@AoD z{v`pa4$My$ejJJ}$gfY88!OpYR#a&$=2|QiH9H@QTI^8N(GEqO>`>I%4nD5ps1TbQFno&xde*l7AUF-6!j1&nn$2$UV)HkPAw5CAOP=TVg1d7%cC|XCLXkCG# z^#qF67bx05plCyZqK$;QqP~sgi3v#c>GU3!V#!dH-`ien+*rxJvZBozi%a{4qRpKT zMO)aRXiGa3ZDog|t?f{>jU9@%wL{T%b|~834n;fI6zwQbw39&5&H_cl1&VeNC>kM9 zw5veTNP(hJ0!5<*igpty+FhV%j6l&I0!4cY6zwHYw6{RfJ_1Gi3KZ=pP_(~5(O99b zXjo(Ui3FtjTYf;jX((DUe|bBgv66jdMF%$)v(h&J{r9-&5a&bDp>`-b%nn84?ND^M z9f~H{q38%Z6dh@YqND6kG|{GLl0ebX0!7CN6dfy2beurZ@d8CB2o#+tP;`<&(a8cu zrwA0CDo}KqK+)*}MP~>UO%^CRQ=sT9fubn_MP~~XO%*6QN2n`0sIlC6sif$P{H)`+ zP_$J3gX!GHO7@i%UD#MGwM;0Q=6oo+$PPsp+o9+ZI}}Z~L(!#nD7wrJMKkPBbh#ah zuCOV(QlRK6fugGgimnkTx>lg*I)S3=1&VGED7sOg=q7=pn+1w)5h%J;e!BXCP}DWOk*Bz?v66jdMGrL= z2lfv|4?7=<9hoYzKQ1rANik`74dRCz5If0_*1&Uq} zD0)$#=p})omj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J%OV41&Tfp zDEd&K=p&)7=z+%ac?n2$NP3#OcrX+lkRDYRA2(LAudL|v#^UY)q38?eL(wcd6n$xj zqOa^wG}{hEU)!PR8#@$zYloum>`?T*P0l1d9GAQ1quj(O&{Ze+v}-BT)3OKvAh2m+cfa2oyC66qN;vngogpp|0rD#_|UV zNcH&i3PzU>6;1CKV@CN((l}u#**bq z_LUVaQ!dtCF%&K9d?@N~hoa@|P&B{}Ma$cvXrLX62HBx#1v?b2XosSeY>HMEC|X6J zXjOrt)dY%G7bsdoplGl_(GY>6H3f=>3KXp+P_(u{(K-S}>k1UDCs4G$K+y&QMH>nf zZ6r{%u|Ux#0!71wx}v4ZhSz$(bA!4sd5^dmMhs;R4n;fJp=f8DqTvEXy9gAG5GdMJplGB((I|nU(E>%g z2^8%vP&7uMXb*v+Jq3#P5-8eRplBa~qJ0I5_7f=DU!Z8LK+ypLMF$EL9VFBhZC)`*k( z4n>pfP;|5%ijJ`?jjE#5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ37x>KNNra;kM0!4QV6x}0G zbgw|seF8=I3lu#d)D=xDmsd?ds=f2Gju(ZZOVg{c#e?Na_LUVqS}t}P5{e#kJ`_D} zhoUF!Q1ql7ik`AV(bIM)dd3b#&)T8rIXe_RZ&UPwK+%f=MK1{yy)01lia^n;0!6P0 z6umA`^oBsun*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ+ieJoJ)i9pe(LS50r zP|Fd!>`^t*GEEh9|hN7>W4@I->Q1rDOioUT!(YJOe`pynT z-`k<+2Rjt~XosSoY>IvsDEdX9=vRTF-vo+&7byBeplFUj(fB zMN3m9`^t*CG!m)^!(|0Bpotx@c`rqg8OI^CDl6_@G%cYC`^+M4A z=R?u*b|@NXhoV7tC|bb|MJw8&XeB!ot!#&)RqRl-s!h>q0!6C}6s;jpG+3Z$h(OVr z0!2dwiq;Y+T3euK9f6{C1&Y=aC|X~jXaj+w4F!re5-8eOplB0;qG19>n+g`bl zWQU@i?NBt_4n@1zp=g9n(XIkTBL#{^2^5VMDB4Y+Xm^34F#<(<2o&upP_&mo(cS_@ z`v?^6D^RqbK+*mJMPmhu4iG3hP@w1_fueB&MF$HM9U{~fZPir1AOWdfmmg4X9f}^# ziVkh6WM5g)gr?%&jY828&WEBS?ND@-9f~H}p=gpFijKBJ(J^)?I@S(F$JwFic$=aV z1d2`+C^|`?=wyMSQv`}m6(~AQpy+ggqB8`FCJPjuDNuBlK+zO|qO%2xrV13DBT#g% zK+$;uMdu3?T_8|&p+M0zp{{6rQ~9F=q&g?f;_y(kdwvS?qNYmrl@(puR5T0=MVC1r zie}iM=yE$0U15i!EA3Epl^u$%wnNc1b||{m4n^156kRV+bb~LubK+&B7MKcA8?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0^ zE4rkqyjTKK9ov@RObgXMNiqG=xI9?J!6NWXYEk* zoE?guw?okjb|`w$4n;576um4^^ol^ys{%!@2^769Q1pgC(VGHAZwVB=El~81K+(Gb zMehj|y)RJofk4rR0!1GQ6n!jE^oc;xrvgQv2^4)UQ1pdRSM*p@dG7?Ix^Dg=_IM~- zw{se^nkv~>R`hjKaoQH4=o{xl(YJOe`pynT-`k<+2Rjt~XosSo>`?Tx9g2RjL(#7` zMZXCY{Vq`Shd|LBfujEj6#Xes^p`-<-vUMd2o(J*P?Wwc`@-}AZfc;YL7=Enpr|ZR z)Fe<;2o!Y?D5?k)H47BA2o!Y`DC#8C6@ArIzBK``>I*4n=d>p=fS96xHld)WZ%%^Vp$iUYnx%1d8StC|W?EsHZ^D zf&xXo1d4hK6fGoBw6H+YA_7H=3KT6SP}E1DXmNp}B?OB43KT6VP}EPLXeoiBr3H$X z5hz+#s4HqM%6}vv)m8Hw)7pyqmHtNgiR}JGCHu;X1{TFU+lHb+&WEBE>`=6#9g0@6 zL($51C|bo1MXTDOXf-<&t!{^+HEfCo3lt3zC|XmXXsAHZS^`CD3lyy*P_(W<(RukAZZAW*cSK+#45MH>qgZ6Z)KOrU5}fuhX>iZ&N0+CrdcOM#-Tgu0>uMS1lEq`FG_ zmi%J*P&7I}d9-y=$-c6p?Tcdg_MvD8=R?tsb|~7(4n;fLp=h`rigvL>(Fi*f?P`aj zk#;B=Wm7a-plCONqTL0G#t0PcAyBlZK+#?TMSBYr?ITdMuRzg$0!8}^6pa-qIzXW4 zK!Kuz1d7H96df#3bcjIFp#nvR2^5VN>Wa24%Eu-k)n)VhuD1(C59RLxIlQQ3Us=&n zMRCQBp=hG>p=gpFijKBJ(J^)?I@S(F$JwFicsmrGV27d;?ND@*P0`5$MW+Z9ohndt znn2O%0!3#C6ipT=I#ZzNEPPQ1q%z(Q5)luL~5tAyD+DK+#(QMQ;lfy(3Wcu0YXy0!8l&6n!92^r1k}M*>A3 z3lx1KQ1q!l(Psihp9>UyAy70+py*41qOXLyq9=>;)(J@U)%--`Q=zD#A&uEZCHu;X zzAK7DMuwvAoexDn*rDi0I~4t7hoYbDQ1pu(ihi|2(QkGr`rQsif7lew5h(hfK+&H9 zMSlqt{Vh=Rk3iAC0!5_`aoJ8$gFsQEKv7wss7aux5Gd*(P*f2pY8EJJ5h&^?P}E7F zsIx#(7lEQyp|0qgqC71Dscw@MeH)7I&5y3zI#jZ+tf*Uu;{MU0sJru_Xf8Vx&25LG znjMOI*r8}1I~2`phobrHP&B_CiWaab>M2mPpg>VCfui05MGFZOEi6#9h(OVz0!51n z6!j4(T3n!L34x-%0!2#-6!jA*T1ud3X@R0;1d5gwDC#dzw46ZE0HLm^y+iqv1f+U& zuLP&sp?;vXcs#ajj%(}u68IIX@{awb|@Nchoar=P_(;E(HMcEJp_vO z6e!wDplEM_qJ0F4_7y1FPoQXjfugYjMF$8J9Vk$AkU-Hmfue&2iVhJdI#i(OFoB}+ z0!4=l6ipB)Izp%`+Mz>v-vp%EFF(58F%+Gb-?DaOhf4O96&>B7IAiZnbd2+%=vX@x z9cPE4ohMLqzCh6h0!0@J6ipK-x=5htVu7Md1d65$6kRG%beT|BG_gbZ z_5`H5(83AMq);>=|G_k)LnZslimvKVyuNQJy4v|rbd4Q~uC+tab#^Ga-VQ}K*rDh~ zI~3hyhoYP9P;`q;(X9eSw+R&8E>LubK+&B7MKcA8?h+`vTcGG3fuef_itZCAx?iB^ z0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yKq9=vAqANO-|CfMNPbw0eD?`zS`OQX8 zb*N-tS z^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&nLyF!0!3d46wMMS z`ck0iD}kcf0!3d76n!Jq6+P3TJU9WV9-UuDdo~muTTbKK4wdXHEBdiRG2*~b^po?U z=w~|={bGlrU+qxzn;nXNw?ok%b|{)-hob-4q3BPWqQ3-+{uU_uN1*6mfud3+F54+; z5GZOCC@KpSH3<|I0!1AJiYfv{%>qR&0!1AKiaH4tbrvYMf2OC zXaPGE^|V9Lf_5nCWmD8!plBh1qJ;&D77-{~RG?@vfucSFMT-j*Eg?|USDWv|Z=5DySk1UDCs4G$K+y&QMH>nfZ6r{%u|Ux#0!70FiZ&G}+DxEmbAh5Q1d6s4DB4P( zXlsF@Z3K$86)4(HplEx6q8)^~qLnJ;>Y+)|#QbN`%Ax3+tZ2tdCHu;XcBvEt#)qO2 z&WEC1?NBt*4n?EvP&C>OMZ4LdXm>jljj=<~9(E|&)23)Ifug+yiuMsG+E<`xKY^nC z1&YQB6dfQ?bf7@dK>|hN1d0w8C^|%-=um;8!vu=P3ltqLP&7fH=m>$LBL#|%5-6G| z)D`VqDQ}yARIB*~*x{k*w_a&Xs#LPCtmwE(aoB`VbiDJS=ma|yooI)mlk8A*vK@*} zu|v_Rb|^Z{4n?Qiq38^oqR9e9X9^UZB~Ua)py+IYqNxH!=Li&?D^PTvK+*XEMHdJZ zT_{jAO`zx^fuf5AiY^f-nl4ausX)+Mi`?To9g1GFL(%JYD0;&VMQ_@n=q)=Gy=_zUjzH170!8l$6umD{^npOp zhXO?(2^4)SQ1ppF(We4Mp9vIwE>QG^K+!CLqAvxCz7i;!El~8eK+!h>Mc)b(eJ4=# zy--*5e5Kqs0jWOREx~yq6rGsg%Kt;9l6_@Gzf_71j|oM;IviW9GC4BH3$?n3KW$Eikbw93W1^y0!0;pqGo}j z7J;IU0!5t!iaHAvbrC3P6)0*GDC#Ou)Gkm|6)5T^P}E(hEBdKY-ai4UPVJH4{2Ypk z`~v@6&6VscE1IXdIP&2NXI1?*7N(+))o+M%eI9g2F}p=cpH6fJC1 zw1_~_q5?&W2^94aC|X>gXbFL$z5+!{3KaDdC|XLOXla3>Wdw?r6)5U2P_&#t(Ex#> zqlNudHbG=Hks0 zLeUz|hoZrDC>mmiqBZSMG}I17YuTY_Z95dLV~3)3?NGFyP0{)SMH>hdZ75K*kwDSL z0!5n$6b%z7+Ek!uGl8Pb1&X#1DB4n>Xe)uDtp$p<5h&VLplCaRqU{BWb`U7qQJ`oi zfufy-x}sH^%YP*x)xP;kf3;9__FQQUZ?0rtS<%SmVu6!G(J1Fb(P%pq?PiCf-R)2` z#tub$*r8}oI~46@hoZghP_&Ot(Y^vj`w0~7FHkgApy&XBq5}nr4iYFDCs1^-K+z!r zMTZI$9VSpTUZCi3fuaclMMnq}9Vt+Blt9r$fuczQMMn!19V65gjc6{fnSfLunK!}N zH53iaq>gQ_WM5g)iOt2xQ$x{7&WECt?ND@z9g0r1L(yq=C_3E^MQ7NdXtEuO&a^|( zSvEye1d7fUD4HrzbdEsLxdKJ!2^5_#P;`Mn(S-s<(*%kx5-7S@py(2TqUi!fmkJbJ zCQvj(py+aeqALW7t`sP`N}%X!p|0ro=JJUNNcF;=3C;VqMc*$-c6p8=8x2 zP7g&lIvw?okz zb|`w&4n=R-q3CTp6uo1IqId03^qx)8`vOHD2o!xNQ1p>N(Z>Qsp9mCvDp2&9K+)#{ zMPCRM%@Qd3QlRK7fuh+0MPCaPeIroxtw7Ot0!7~o6#XDj^rJx0PeNVMOU>o(XC_56 z^JUq~p=i_mmbIUoE7@08^m}tLa7rlp!}(A&#|}mRvqRCJb}0JG4n=?4q39nw6#Z+5 zqEbs-w}+wzo1#X6qOw3ylR!}+P}D)7s3K6*EKt-UP}EVNsFOfZXMv(F0!6I?MQs8_ zT?LBT1&XQyMco97x(gJ|B~UcCKv7MoEBdv$ynO;veX3W2^IIr-H!JGVQpvuuqWN2j z!>5L#1)L8>J?&7mpdE^O*`cVn9f}sRL(#%^C|bl0MT^>@Xfd0jJ_1FH3luFOP}EnT zXi0&hegZ{H2^1|YP_&Fd(Xs+X{RN7a6DS%WP_(>2(LjNsK>|f92o$X-P_&Xj(aHiv zs|XaWD%2It+ftsMfK=zsf8G9kE%ht?XY-3{tF=_JudHZDOY!izp=eF#L(xz>6s={4 zqP6W%w2mE$*0n>?dUhyU-ws6^*r8}co1%>biZ&J~+C-pem_X5{0!5n%6m2e0w1q&? zmI6gv2^4KDP_&Ie(Y69b+X)nHFHp3DK+%o@MLP);?JQ6KgfvpTVJM`}E(6U0W*IS5~xJOHsKX6z%SOC>mpjqCM5-1ucP;{_B(IEmwhYA!OCQvk9py+Ucq6q>;M+g)h zDNuBjK+!~jqDcZpM++1kBT#g#K+$mmMaK(uMWb5E{SuIBYrfJS9g6zpKZ{OisbpVS z(J3v(#?wO4sm_O@)9g@mx*dwnutU*gI~1L1hoZCWP&CC3MQ7WgXsS)oIRZuJ3KX3u zP;|aP(FFoU7YYlg*I-#!Uq?Yml2}pJA{LMorhoXu3HT~;bD%n?7baP8F<>F9ui}RuARy!2k zW{0BN?ND@w9g6O>L(xn-6y0TqqPy)-bdOEZy#ht|2^8HgQ1pO6(Srg-4+#`KEKu}_ zK+&TDMUM#-JuXo6gh0`g0!2>=6g@3a^o&5!vjRoW2^2jqQ1pU8(Tf5_F9~%;H@1}T zN?Ex25A0C%p-s_80!1GS6n!F4^r=A6X97i^3lx1JP&7-R=u3g3uLO!_3lx1VQ1p#J z(YFFc-w70bFHrP@K+%r^ML!7?{VY)Qi$Kw@LS50TE#-d_kZLVIUHzKJMfpL}Z!MMV zD=Ye6OR?aLQ1qwsq3AC=6#Z?7qJQjA^sgO?N*&|MJrp(Ap{UUgMP)k_HQ5vu0!1AJ ziYfv{%>qR&0!1AKiaH4tbrvY?W(Hnv02CN@RG1d28lDB4V*Xmf$0Ed+|T6e!wCplEA>qHP3?%s2oxPFP;{I? z(eVOBCkPasC{T2gP*=2j$MW3QCPg>SpWuuMMd#%20Xey2CHu;XPVZQ(aD6B`!}(A& z*$zc#+M(zyI}}Z^L($oGD4J@AqI2v}bgmtW&a){xU!dp$fuaiqilzw^T_jL+u|Ux! z0!7mWiY^r>x=f&GhCtEf0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mFHwYBnDAX05 z+OfQ20#fbWn&6xkiWbcel5Xl)$-c6p+d39U+!%^(cRm!|VTYnS?NBt+4n=p_q3CWq z6y0NoqI>O7be|oH?zbs=K%nSBfue^5iXIjydPJb;QGuez1d1LPD0)Jm=t+U1rv!?g z7ASf~py*kFqUQvPo);*3L7?bGfuffLie45ddPShR3E_b0~V-`B3zZ9g5zyL(zM7D0<%xMIYFq=tDacePoBCkL^(OiA~X` z0!5z*6n!pG^o2mtEPR^YWicL|oKv9c8QAdHIP69=p1&X=| z6txNzwFwk;6)0*KD5?q+brUG+E>JX=K+)U+MKyt<9s))42o%jLP&A)F(fk5M3kY>Z ze|9V{oq$w#SvbM@D-`{c-!a>>QziS#iWcfr47(!~E$no$6Qm zeKV<{ohsQ^R!Xni{rZD5C@4ee00ksXRQwnNb-b|@NVhoVjGP_&s% z(dGh0TL=_wDNwYPK+)C$McW7zZ7Wc;oj}p{0!2Fr6zwQbw39&5&H_cl1&VeNC>kM9 zw5veTNP(hJ0!5<*igpty+FhtCTDw#Eo&=(9i2_9@2^5_yP;`nw z(WydR(Vm^krF)X1=KQ|vy+Y9|>Aw}Hb*f}vS<#uDir)8yqO+V2MN{lhbhaIerrM$C z96J=9Ylouq>`-*R9f~fnL(zpcMbiX|E)poZSfJ<H6UON=sXNRKu?NIc99f}^b zL(xMvMGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kGd2AW-z8 zK+#JAMK22!y&_QbszA|e0!6P26ulwT72V#cd};zxZOhL(-Vuua&VTj8o1H4zS61|H zr{ac(LeYE9hoblGQ1pQviaxYM(MNVD`q&OdpV*=3Q#%xWW{0BBZHm4SD4Hcu^rb-2 zR{}+|1&Y2FDEdaA=v#rJ?*xjz7byBcpy)?|qMrnceikVDMWE1d9F?>Wbd(RDLA^seYQDu6`#JP0nB5{_0f8zOtfH=i=u_LQzBKxRMV=jdmz1 z+o7n*4n>6>iaOY#sA7krW;+zM*rBMSO;IO-qRs+ET?C3+1&Z1PinH z`T3%ML($+&s(0r~_LUVa+PPTi@ldpw^P#AZ9f}sWL(vj;DC%p6q9yH6)Xxq@OWC1l zX*(1xV^g%OKv92zqU8jN1_%@_FHkg4plFal(Fy`ZD+&~?Bv7=nK+!4!MXL%FttL>k zxG;s`uo-d1jH$^(+0U`K8%)I#;r< ztZ0MI#Zga&q79u7MH|_nXk$ARZDNO_VRk6m)DA_P*`a82I}~kUhoUWQinbCc+FGD! z8-b#21&X#4DB512Xa|9!9R-SZ5-8ePplG;2(Jlf-BLs?e6(|}hP&7)QXtY4lZURNS z3lxnJDB44yXiuT8XuZzm%M+05jSD3>>xZHR^JV{Doh#W_RFBq3AH1qVWPnhYJ)<5GXoApy)_}qN4ul&C2eM8aJS<&RqmFz1kI=gex>A6re)%j3#jvb25wL{T)b|^aE4n-H(q3A+8 z6iu^3(M5JBy4a@Z5`m)W0!5b!6kR4zG(({1a)F{N1d6T{D7s3Z=xTwYYXpj}6)3t+ zpy+ymq8kK?ZWJiGNucOvfudUkif$Dsx=o85tj^_S6OigI`F+<@LeXdWrP(_= zSF*3H=>`?Te9f}^ZL(#)_D0;*WMUUDPJtk1} zxIobp0!2>>6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(Uof zx`?T%9g4oNL(wcd6n$w^^p!x-Y=NS$1&Y2ADEd~Q=sSU; z?*)o}5GeXlpy(%oqMrqdei118RiNlMfui39ivAENnj=v3KY^k@1&aO>DEeEV=pUi3 z=)KP6`x21q-}%iT?}wtNyQT4O=SudK6_vXb@2BUpyRW%ysc7o*|6l1Bb|~s#hoXud zikj_E)MAICj&>;OWQU^8b|~s%Q`9O@)Fx2WRiLO{pr|TP)J>qMyFk%g0!4ER6x9TZ zdI%KFBTzK2K+${xMe_?3Eg(?TQ=n);fuddlMZE=z77{30Sg0#%=u&QcH7VLXzty_2 zOZ^({wC-sv(xsApWkrj3DHeV`6fNO={8`l34n<4ap{So7ik7lN(b9G(TE-4V%i5u+ zza5H}vnd)NP_(>2(LjNsK>|f92o$X-P_&Xj(aHivs|XaWDp0hVK+);~MQaEY4HhUG zB2cuZK+#ZvqO}By))pvQN1$k3fui+kSBw1+^^o&rUC z2^8%uP_&OwSF~Z5^63dk_1*jm$VQ=Pm#n zqJ!;Fbch{_4z)wkVRk4QZ-=78?NBtqrsxQPq9X;0juI%EC{Q#>py+6UqGJS#juj|6 zPN3*`fua)xicSqvqRBEb||{o4n>#P zp=i1tiY~P&x=f&GhCtEf0!3E{6kRD$bd^BS)dEG=2ozl_P;{L@(e(mFHwYBnC{T2h zK+(+tMYjkP-6~LYn?TX+0!4QS6x}IMG*hT6n%bp2?|Vtnko*GdIiYA!ej@v>E|u&n zE4r^svC0Rb=zixz(F1lUde9C<580vUVLKE(Vuzwf?NIcX9f}^eL(vm9MNbM8Jta`| zv_R1_0!7aX6g?+U^t?dP3j#$i3KYF0Q1r4u(JKN)uL=~sCQ$UcK+zilMQ;iey(Lie zwm{K40!8l%6ul?Z72VUNyh{R7?UDb!>w7~{@BAR?{VtX4D=YfAOEKxAQ1prOq3BaP z6n$ogqR;J6^o1RYX4#?WOFI;OWrw2Kb}0JVrsx}iqHhI?z7r_=UZCg)fubJ;ihdF( z`dOgp7lEQ*1&V$XDEeKX=nsLSIRZuh6Dayqpy)4wqQ3=-{t+npSD>iW8W-jiH3)S@ zA9g8UnSfLu%5ReWC={)hUk+((tz=(WQHR#z$xlL2#raUwY=@#2I}~-aLs2I?6m_;k zQ5QQDwc4Sm%??FfZHn3jimC!d-2{rd3lz;IP&BtdQB9zzhd|Lh0!8x*6wN14G`~R6 z0s=)n1&S6FDC#9p)LWovA%UWW1&S6CC|XpYXfdI#sHwI5O#)JVG+&k#t@SJYP4izB z+NZUWePu;UwiaDJ4@Lc)4@FDap=fD46fI+iqGjz+)ZY$8%h{o5fE|jKw?olDo1#Gi zMJosttte2ml0ebQ0!6C`6s;;yw3HkPAw5CAOP=TVg1d7%cC|XCL zXkCG#^#qF67bx05plCy(u4swY@^T4CwU+-DtiGYBe||Y+qt;6Hl@)E;T5K^Z6m8~w zDB9c(MO)aRXiGa3ZDog|t?f{>jU9@%wL{T%b|~83rf3I&q8$Z_b`mJsS)gdRK+!G& zMI!`?b`>ZZDNr;@plGx}(QX1oy9*SJ5h&V2plDBlqP+x)_7*7GN1$k5fuj8ciuM=k ziZ*F2ADVzvH|&|<3=2iw@+%-?TPxXDRy3})IRC3qbg=WG=ny*;9cqW7!|YHr-VQ~F z+o5QJ9g2>yL(!3TC_2ifXre&TB!Qx%1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%R zP7x?NRiNlJfuhp|ip~%ynk-Osra;kI0!32`-)(9f~ftL(wI6D4K4EqD$>ibeSEBX4s+Va+{(n z1d6T{D7s3Z=xTwYYXpj}6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$Dsx=odHq3BUN6g_5#qQ~t}^n@LXp0q>JQ+6nN+NS6kfud&xik=fFdS0OD1%aX$ z1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2fueT>iry0_dS9UE1A(Fs zg}S2qTgw|HAk`&%B{&a+qV3CReAHUWzOtgvT8q7Y2t}VeABw)PL(wcd6n$xjqOa^w zG}{hEU)!PR8#@$zYloumY>K`YDEdL5=tqH~p9G427AX2fpy*eDqTd9HeitbEL!fAm zK+*pMivAQR`b(hbZ-JtJ1d9F@C@QtZWjjR;0!57iMP-4aCZVqAlh*R&1f)7Ozwi3f zP_%7+%UaP^$-c6pmbT)SpF&Yb=R;8^I}~-cLs1ty6t&u+sLc*VUF}fRZik|(9g4cy z6m=IUnoFQ)Zh@kjKv55YqIm?0<`pQKPoQXifuaQjih2qZEhtdbOQ5K?K+!@1MGFfQ zEh12~s6f$T0!4iUiWV0rT0*ERsP&*i5e`?giGudHb4w&M3+ zLeVnLhoWWeP}JWJMa$WtXn-AxmbXLEKsyu-vP01db|_lWrf4OBqLl@TRuL##RiJ1! zfuhv~iq;S)8Z1yWM4)I*fuf-TMQaHZtu0WrjzH160!8Zy6s<2%w1Gg;h5|(!2^4KC zP_&6qSJbbqJpZpr(U`1gsZexUesn#ot&)9ZMO(BLtNk8|wsbxeZDog|t?f{>jU9@% zwL{T%b|~834n;fIp=d`t6zybFw6j3baDk#-1d2uo6zwWdG*X~wlt9sFfuh|6igp($ z8Y57&hd|Mu0!4cX6zwfgw2wg1z5+%22^8%wP&8Jc=m3GD1BJSx&DzSlCLq<<@*C4O z4@K?yvj3pAO7@i%9okkLGba=s=6om`Z-=78?NBtq4n;@Uq3B3E6dh%UqKS4Wnq-Hf zqiu?g5hyxVpy)V(qT>aMP7o+MQK0A~fufTIicS$II#rK&p@CFJgy;qU*Dw^V=%fS5|aUTk-Ut zq3B}gL(wI6D4K4EqD$>ibeSEBX4s+Vayt}VVTYnC?ND@;P0`f?Mb`)vT`N#@oj}p` z0!23n6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07cL)^SDNr<1py)1vqPqo(?hz=uSD@%V zfuj3`x}po)%HJg*)#cJGriG&A^Q*BBv{kaNtmu)pqV1nh^r-Wp=rKDKJ#L4hC+tx4 zq#cT$vP03+b|`wr4n@z}q3AiAqUQyQUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDf zD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiartQiXLh!FQ0%^m&MYX*74OWM5fP z=dQ(tjiIQE^P#BK4n=KtDC%m5qINqJRqasJ%??G~?NBtA9g60*DXIw+^$;kUN1$k4 zfui{Yislz6T0o$vr$Ety0!6(9ih2taEhJF1ut3ow0!51o6fGuD)JLFbae<;G1d93! z6fG%G)K91@>e#jXPy$k&ksk_m>RP|j|0XM1s%s_t%8L4TEk14vMawxKiU!!BXn8vn z4YWhiAUhPTV27d=?NGFm9g0@AL(wWWMXL%FttL>kxZ(M=u-(r+c+PJwzWgic6KP*-VQ}O*r8}gI~46?hoYVB zP&C{QMZ4G(jSwi>RiJ33K+!0HqR|3Hy9pHSE>JW^plA<)qCEwQ_7W)CTcBtkfuel{ ziuMyI+Fzh(tU%EL0!0T36dfc`G)|!CV4<#P%dX{(5|HYH`E|6dLea2%*?&maO7@i% z9p1IrrzI3ka6S|rVTYn4?ND@-9f~H}p=gpFijKBJ(J^)?I@S(F$JrDeFHm%XK+%Z; zMJEXqoh(pvia^n+0!60@6rCsmf50jZXHCphCn(VVPkTGvYUl@(3zTHMwt6kY0kD7wrJMKkPB zbh#ahuCPPVm3An)$__`vr;~5GZ<3py(l?uIS>f<+l=$ z>ahGW{w1O4zWfa#4|lC(Us=)PU5hzgLeUe>hoUF#Q1p}?ik`MZ(KB`^de#m_&)K2q zc{>!nV27d?ZHitJD0*3-=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!TcGG2fueT>iry0_ zdS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzs4IH3Yq@7@QnYS?`=6-9g0@7L(%FsMQaEY4HhUGB2cuZK+#ZvqO}By))pvQN1$k3fui*Uiq;n>+CZRa zLxG}=1d28mDB47zXqZ6JrUFHq2^4KEP_%_W(UwA8(Q@tO9}I}{DKL(wjFC>mjhqFwD!G}5MMlt9sF zfuh|6igp($8Y57&hd|Mu0!4cX6zwfgw2wg1z5+%22^8%wP&8Jc=m3GD0|kl>5-1uc zP;{_B(IEmwhYA!OCe#&e(_S8wfK+GZN7vhiqR)D#F}}T$ePu;QwinyX6N-*g-B_b3`cmFpo>xE7@08G^4$^XueQ%x$~ju3Of{CX@{b#>`-*I9g428L(#Q% zD7wxLMc3P*=mwjj8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFie?HF-6c?Tw?NT7 z0!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyyj|z1~m$sK5NkFQrcTR9F3q^b9C$b-F zuVi0Y(NpckrwfFlr=1T)&)A{pSvwRxXNRKa?NIcB9g1GGL(xliD0^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7& znLyF!0!3d46wMMS`ckMXdZNAD+%qW}H(!GDWGLDre^=vI?Un2+EBdy*SfW=b`p)@K z^t~O5ey~H)k9H{f$qq$7+o9+eI~4tDhoax?Q1rV^(H{aua|DY1Cs6dKK+#_UMSlwv z{UcEHuRu|$8kg-9H3$?n3KW$Eikbw93W1^y0!0;pqGo}j7J;IU0!5t!iaHAvbrI@{ zzHTpXl7LhfswOz!grcYN%OS1RO7@i%Rjb8*3x%R?&WEDzb|{+54n=d@p{Qnuq8@fA zn#T@B^V*?kK06f6Z&S2@Kv7SDq6GztdI=Qu7ARUsplD%%qD2IX78NL3OrWTbK+)m? zMN0@2^%W>uQlO}xK+#eHMN115EhA90tUytJfuiMvx}vVt^4SSU_4#~R)?Te&>0g}i z6a%W2>?+CZRaLxG}=1d28mDB47zXqZ6JrUFHq2^4KE zP_%_W(Ut;5TL~0xEl{+LP**gtT7D-1sVXQ_Gl;3x~LnwMGe^=uX)k^l26-}xZLzW0dM>`*ij1UX~HZ#3}vRCcz^eAhQ+R*eb)GS^*sduT=ul8bkxn|ZLaSG#*askBk;-+`slrnR+KES0vbow9PN zv~BI>RZFEEYqd2>rCn+}4JnmI)n*JWmB!S*TDw%*ySB`FrPBVjaT}CM2i5M~s8l+% z)-bG8nowJJvr=hd?X)dQrDJQaZdEFsSes|tQt8y%@a;>b$+atXES1i#eZ6z3bY89h zh*D`qf4dBYvnPe($%%~_bipJubr`XsdRJg^?ggF+iUZUEtT%7jX1DW zy03QCxKin%+P8<4N{`hBj4zd*svS0=RC=!V;E|=$OSNKBsq|WH!(&RNw`yk|S1P?% zd-H@+>7&{LCznc})kdCLDt%eI=JZnOo7(r2OQj!b1E-Wqztj$&S}Offd-&W^>8~D@ z3)08Gp~uG4(kGyy$CQiHXP}|S+tbshprOZtGt%dvp~vVe(kG#z$8}ew&q70wAFoND zhK3$1T%SG<4L$O|X1_>7kN;!tEx@BV+rRDI>~1#6;!*;%5GZY-g^=L1&=Q3}NJ0du zr4)j+Sh2bbb$54ncXxMp_fn_+UDwR-+-&Icyzl=wzV|!cZ;vBf`#X2;+1Z(M?wNa5 z@c)i{U^L(VKk32IeE$!Di=z4dKe~>H=KFuiIVPI#|EJ=(XukiacoU-e{=b@)NAvx^ zrJ5AY_y1R@I-2kQF-%=F-~VTi#%R9(*9L$I*9+=KHT(&yD8$&l4|* z=KJrm@=KC)^u8ijUPxS2(&G+9}+b5duKazDoG~a*a=#Xf>|4hx{(R}}% zk)xye{zDPRNAvxg{wGKC{j1uiNAvx=wr5B4{mYW)NAvyLZWl-M{p(7XNAvyrCRa!E z{R;!vNAvv?-#16|{Uf`#NAvwNmv=|={X=v2NAvwtPY*}){bMVSNAvx22Tw=y{f*=2 zqxt^M-^bpr_K00M32wcQw0$o+e5$iLBc=A&dp{cJKNXUca}eM z_KGb+boeR9*?n86$R_r;Vg823Ms{#E&2p9fZM1C%W1|8V*=V+h(F$MM9v&Uj!92Ff z-uKy!)gz64ENrQ8U@r?>DID%$oWcbARrKh1g_9&hI?=;tBg&qwLNfpMTP;djzds|Kox0_lflJOXT(TL<_=JSve(< zKDH4f&Bo4QPNzR~!#n!~bNcY{?|!!SHm83s`Q;a54T*MN?|tdyNWtdTXpt{*xmv$P z>&t%p`^&w9))zc@@HgRdobdafpW3on>$UYqmqz;Rq{aA-#ke5SXSrt7f2h{M$e*_! z7OaD!<_q=@*1<3HzNiRZ%_AordGp?pg4Nb!PhW_G?2fO$=CEyc=Sxp`>!t7|T>s;h zH~2y%+8w`JQ{P}2e!lz5`beLMZ4Ga85^Y|->CRhhN?YlVwqIQxH2M02M<)kQ_}bC0 zeY$s~&wgt2IBg#M{?c>8m44aNPycDpXshbrXU}~;Z_KyqZp`Mx!@l1ln9cOp*Nh2X-R!N_bPrzL^&cMo>AsPIi>=8? zz6kfK?KQORdfFBXgSKZJbw;~j5&pVj-5GlYYxBzAa&67LZcWa&wjYE|vO9lr&jkmW zI<_{e)?79|c)sTS=lXid?)>?;FWkFlq|cvf)6Loi)?e|`Okc$8&JTQY)%p7cZ6Zyp zY*UyxH^+NVj`Z8Wx(@SoE$`lPWoX*7AAWXDxRLkWcc8zfM7u3ob{!gt^lvP% z9^C%2vtrr(AGRaB|7C9y%j>_hQUA-1*&{z$7vO){zh>EF)?N8u_U9IItv~R;>>Qiy zR-^ux{h2*7u%jJm>@PbW%Z@}lM>pxvH5Kd7yF*it&e2XiB9W{CkyL7HLy<^qgGj8y zmZ_~$V^dXK?eL~YtjkM`j5x`TM`InfPNnSOaI&buwraK~PHZg9ssm^{re z5za6bjaGH_Chhv!?1oyC_8slXea;=aMpLQQd3J0ciRG{)sZ{$^yVMw)yi<=hQ+2kf zGM2ZCqMog*W@*u%vzulaJlZ0ods|R{=KSD}y|$hsGM;mrp5yGh z1icEQ+w^2XHtSi{wR5yf_JsV?N_+bA_D*Cp$m(%hsjc%3GiM^UQ6}@%+2@FZqPD$? zgEiLoNb5YZ@=qwW{PNOJXl4()Mcc(;O;ap zpN7;6Pc-ekj5(+8POy8?NWGVEPBUBQRPS>N4$ToeZT$Dmj-uAK!HYM_ik#5c+PHzn zj@NHHz<}|fnNR2UxnxvuW)wT39%A`Rt+dRxBI3V)>k*%bQosX=z@z zeCf)TIV)S{4xO`n&t)r@I+)Wkch&Ni6&a8D^fvX_q05#pT)c4Q!qqL2p$nESZW%gz zQOh1f3l}Y&Gkej{6$@rBZyCD0Wl775*(-*&3~OGoa@E|0ONXvpx^&T;1+y0}Suu3} zoH@<2moFY#T+}?gd05e~;^yKaheHewS+aCV%aE4YJ1-nkTvRxGh(BCt54U+}=)xs) z7Ok4wGIa6mISUpp`M7+SJ??y7}LmX84+7$Z318%do;kBD*lrCEMngJ=AK~MAyE$>!>J_6_0jLq`Y)Y^z&kq2GLs%OLWcN zAkk~{M3+qxU3(V<4Z8;O8gGyI48|vVS?!wnkUvc@??gYZ!8|wqUp&ReHdU966J56m zX5S^d`(Rtb0f{afdd}{i=(168r(2@SU`^q39~wSQS1aKQ3YTYSqL0lkry!A=9cw=> zv4Mr$jT0MeWO-gL&ZdJBy9o`s3R0 zl6;^xPY?^N^{_zZ-sX0{#Gs-?FW*o4Y0g=5!u{=ku&4Q+(%YWdX43yZ?`;3uoi#lR zdx0BeyiRtz*1D0u>}VptATgvk(OECBhu4mYA$oy9EDRpavKLusI7_P|%l+=_U^6{F zH2wH!$FV&M!^a2y>v3P5S+U*qcr3TzUsD7#E=&{$PZ(QWnAphgg&V?_AUoEsz;<}w zRKC)~9)xabQ=^^y0MgkvbnMpsCjbAk!|RkCyL10}wwQlL3xodsqW#8&eb|8hi5|X3 zYh(ZCKB3bvYx-)`R$X>%x5@JpeeG3urqk4B9BeDi4}d{*Pwg4)IebM8G{OGe`>!W< zw_#Zm?3A>!p{}{2zP`DtW_n3=Re5ts{luoJ6*Y|!9++Cu&`>h5qPelQwz;~tW@4ni zVq$Y~N!g_I6lIMKP1e4wc4}R9MWapGR8yttD$6D{@7y|JNqu>9O>Lu1+)z>9SW%vS zWOAL&w5g_{sjjZpA84+tnpsiZTv=N`wWKk8Mw?aJ$xEwi%ceA!mo%0%*ECHnt*H0c zQClBQJ$y{&6W7!>H#C(tl+{=HWRex1mSzpmmS8Gcc&S`{A!@BTg zuc$9+$XIgL+th}M&81D1l{Wu|s%<+DopkZmz4Xs%fmyOCF}_ORU-{-tb|~D}z^1-llnJwVmJ9R|cD*qNc=R zd8D?op}C|yoXyB!YG1O-j2B+fIEnS!TsLV}vu*3Cww23D8mnq+!u2#Z-LSYUqh(e7 zwB}NCth}lrd@|N$I7^>du-Tfct7@jC*V>G#%Btp)x?m~GYHMmL%G{Q~yvh;2!h*Zy zQlg=$tjsJ;w?^4%O%+WQ&6T#M(ht>@)K@jmN=KJ^YDvv3ZMxQ31e>j)wjo%8aE1TO)Ts*eT)MX_#&5iXXH4Rg%8iP64SCo{`3SLZU8)54k zN^C~KrnVIMKi{E6U26i%YAto0qlO6@#v&ysBhkb8S;&T~lN8^xEo1+keutU~lkF#k(Kxx-$08 z@`~wIHlQhOY6#b|?Hif>QMfC)%(jw!=l1oH(Y$`9?b6M)(<|yLt7~Vh|D^Rb6Vu(M zc~vqsJwa8Sb!OVcb=I9^_NT#1YA_Sho#e3e3MfsJ(``_GEix=;io_DZ2RMb|r-EDYg>xQS+*8Ar0elncJuwVySv~;-ATe&Rb3F~Yd zHPn}xM&wi-lg4vF;@HRWb&M*o}Mz-7V7kDRf!xMY4y zbIX#s3uiBB_I)Wmv#RRqiisuF+U4vhUvB$+>tQbNJ$*#V*viFY+88fYCfS@aPO{2* zS+;T4bE3+-zx6tv%##S~3W8lYSUu@Iqj+SS8L|7YwK9(9RZGfeubkaHrDe}XySSBp zx&QIF)@o37d2P_8rVk_9+Tq5r?nWE6xY!R@&E8#T;6tfuc z%TFzJJPwy_-l`>Yibf3Al7?x7UP~K=)BD1DTLe2YPL8W>UupG&XP;Oyb!tiLvzxJY z?#0ToJvw;O*1f*CIIw48O;bVH*s%qE5xKCqz%L^gjTttgVBqqWMJ=;evz!K!K%eOTb;LP>Fkw5>>BiV>m%kmuqo#)TRn2fie*FQ7LPJA zd-M=tW7cRET+FQ(Bv22TZ%L<0fFBnogtYC;;>>NMG7GTJ{#VspV%%0ye zWKqkK`70NUFESMFgG0OvvgB)T<-(;)hODsb!B$ron`?@tbMO*JxA8OB=HbD|&*y^; zSW#2kWL;F?b=x!V^byQX-bzZVs;jnbJ$o*)Zn;(IswHz<_6TM%yiI4@+B5j>l~%9S zZ#x=UpV4S1qJC6QPrz0TMog_6*Y?3OJ4Yxjv0;=tU0-Y)0fdV`x^;iBV}Hon4p)3I z;inE&Hd+WzGQ!s#$hWY1>C$Dzk)RBV{GWWsgEvgVE8X-CyvjDG25ru`r`j@>*3Qh_ zUq+4j*IFv8w&Rc;*}b3imt&{8ZhFugxFy9!!?b?V2LapA>Djby4L@&e)+PyC*wH$; zV;Y6PdeDrHGw`W(e7N3ezxv>|hpZ7cr$#r|l(o0}z(3f?c1OrZ<^i&E_ux)AU=2`FdaCdq8!O`^ zG&ps(5tdE}t?LNqW-l#c-DEWIb6V>N1LcBATZf+MG4m+RB^)jCtl=S3pxu$#mNld_10hBxC)SG}&n1 z&IvO|_kJG7S`1a1Xd|WYq$>SD;IE%J*VcG16r3p(|1Tfao@7HuxzsvhY&#Hi9nRogZ&&UNkq``;4s@T#D@k-<}{C)1(JB%)q+NrPXhOJC%%-6=iO z^boP6G`MD$ejsB-)>kzC$5Z*BYh*0%OA-zPgJrU_Bzp}klMQ5Tv{+SE6&%;ETbk~Q7 zTFTZr*;RuE?;=~h^hy5Xc{3Zg&6UA6r|{_^0fXRh%*I;KDs8)GvaN#kVJBbV`mm8< z#`^H%pAV0k8)j5B+9Mf;n)~oEcse@|2=4fB z(Lp$>3m(eYz3g*p=C;GV4*Svu_O6T6(Gm8%^8Q2VG%c zEoOZ1;{Vjg4a!?~UNt{hqdsP2A$`XzDGf~vuU_*AudvdFf;MVyuBqS~mT+1u|%c-kx z;8_)ok>HAe&y&Gr+wQ=9wv(6&yHsKqZgo0mQy2SH?_jCIYxz@4W;U1AH0t=0c_}+s zzJDJ$!@(afHhsx2m}ToV@nX9|m$`SfURLr~9PSBi`lIy41D|7hU1my`9(`*C2bZgZ zr=?SGJ)DKtp8Y`|N(K}8g;%r+?Jx{R@MuK_!MO)^b zxyY4O)poj;d0nFQgr%XOOm7jjSq~VDk#?a~Cl5=*VM0)bg$K%>-Lqlb8sz-Ck14To4P zp1rA{vzp+HgZCAJ=g;V;rFD23l)f@*`!we=>L_`;usFP+8_dS9p9XirQ)r&q`{uTX zo%GI_x&MSqVzUVL<@EX}t1g*ZmvPJvSF^wI=kslS2ds4vP&^{t<@rt$%-64whKtsw zUn!}xbM=`vW^N;S#^QzRA>4U*J?sN6u)Wv3{zcK?e5tY|^YnujOzKOLF}ASdpVn@8 zeDH_EK>$x#7oJ($rM~of2|TghBMr)?mbV#cn&)h@^w!H1t+mtjE904OP_ek-%MMnX ztuev)fA7e0|OQl|8v0XMxuT|DXcmXxz69wVGAy_$?C!oOy zZ-%`~?C+D;>WyC(DZIk(?-H(mAn*g6zpqYr#rv|fEUhl7nPNL|g3Qj>8}&$mw7ODExYB|Kqoa|jJyW9tRm@XZSrto7Wi&FI8uZ#zPh zy)2f^XA_Ptf_rqj;Wg3bW`@AbIHM1rR6oTwR=6ux*@mB)-a0c%Y?Mt`x?W4a&f^Er zaQ(DiR`m;%=}CE)Cm7F7toPCLdaJk12-1BD_5&Z=FcTK7tfb7=bY*jJ0ub@1=Ti|3 zcib%7Cv~Ydyv!2JE_0+4%9C++;v=lE^YROYzVgBjgXa%=f`!D0)-45@j zv>h^4+SNox8~#C!$i%X;Eei(vdjciP7Z+44-nnJ&Tzd|eJ`6pwuWPv!)%jBg(}kLk+Sj4`qlyQqi+J5;Y7P0S2 zX53;C`#w^}Efy?YD~Ltxt1TI~nEl*&<}DVnFQ*&ub>`cwi@ly<857udIwKR-%MI)0 z+3V${>*amd%LlKQTfZA(UrVyb(%<#4`=0sed-zVnfR&K}b9FrXukQ<{FQeEv%15*7 zzcZV8a4gO^I2PGk5v`9EjTjLLFUYsD;JQqD_HEzz^EV~zcB1{|b&o_IRPAId*S@|L zv2W5w^6V>1{`Jc|`|{BQ$DJg>8wWnVzO*PQeD zzN_lrpvkkZ&5rYG(;ey69zWZwJ@5Hm?fWx#D!=U2{*%phs$FdRdv-&!OgrDdvup#n z?_O<|LA6DTWZ6#9&#UP-P~7)hpKg@uc-2zXI@KoCIjZ&@^q}2ts{5-RqI$gQ1*$ix z-l2M*>LaR8slK54n(8~MAF0|Gv4iLRPW5M1`=WKg{fk2Wdi;L^@M>SA4r*6b|HU`w zeO3Lt$DX%PwQns3d9> zIjR?_UZHxO>Mg2wsXn0knCi2tuc*GQ`jP6Fs^6=wQ?&y`@H(^ITVIc=-Bf$4_E#OG zTBJH!b!*iM)oRrS)ooR0t1eJos=8WrU)4iYk5WBR^$gYXRWDP$R`nLuyHy`jeNy!W z)z?+uQ~gx+8`Ymw|4_}c{n*z}u4*UM9;$s*H&Gp|I$U*2)e_Z7sNBb@tG=b`-;ws$|Ap#W)n8TrR!vxc z<KwV&!h)uF1RRL859t4>j^SDmH0lj?lcC911b_fb7q)%#mtt`k&GS3OVl zQq^lzZ&tla^+DAqRG(LUP4!*XPgK8F{ZaLI)u{F3z8pEK9aa6S)Xq0j9iTcyb(HEh zs*_Zwscx$}M|F|vD%Jf|*Qg$^dWPzSs#mGrta^{?qpHuTzOMR#>X)iNs{W~(umhIA zt`4d_R0~uGsSZ=!O0`^ds_JyrX4M6%yQ%J_da&xzs;8))t9qI0^{RKMKB)SX>dUI{ zsD7&Yo$5N(sQuoBzrH-xZmPpoC)z2aKi;6a(2m`nSE(Llr;MIYQ@zHH*`DuEea;T> zp5Ida-cA`k|D`(0&LKRPsqSOvE}oB2ebCNDJU^$JW9JZ_yQ|jp4fA%YC-)2U1*&gu z9Olnd3pNe&5Y>5hg5mR9p?dY^VZKB4hrwa~M|F&yi1_pss{0j(`6$(ghllwE)jT_4 z@#%Z0*4aSD^A4(~ZW-o_RNo#K<}XzHZxiOBstZcOyh`=jvM}GJ`cp-iqm^OZ(#B=} zeD;Z@pdK(etjDN6S{>$>RNK{txuVMhPhaEmu<0tU0XXW{0&(^`JRnK2G)VmN37f+F?PMd#g6?66V>eXD$l!WvcHl z3G+9qo9-6o;i`*PgxS7p9K5a@SB3RH)pfgvIk87rx85tPQ&bPxC(I|PKDl3*UsLUL zV3;>joqlkb=ct~2Xqc~1{cuf~zf&D}WSB>)E;%~Pd#m1jY?vQV{r&hbCr=3Lgp7iiy(P@^RnNaI%-5)XYA5>c z?~kg3?+)`=)#dkwd4JX0?+^1Ms((Ki=F~%BEq^4e(^QXqEX=2=KL13R-%;J*=`e4s zy8W|ZUZ{HE^I^VD_460Q{IhD|D`DPBb>(YeK2Y_}H^TgwYUJ%Ow^yxvH_Q#HN53ED zGgM#vFwF0%=6@3AO;mUMEX=#AUi?LvZ&3a6t1$nnTJ&w0$E&Vh8|H&m@BSgoPpD@7 z9OjOylYR|zlj^a*h50Pimu-OM+w%j}UVn#qGu55!YJ@+&SoPAZFyEy5wf)+aKmMEQ zFdLwG-bQtg+%O-idawNumOuWKYP>_3JF8B%0lGgvL-lz3jV#aSsJ?2yq2&1^)eY@e zvpf${-Ps0$o|md#Zoi}D`4-i0?FY3y|DigfAj~DId)b8ne|(MV{R6`MjB55~VeYD0 zJt)kxRByE3vh()$sXnFps@Fs$@`>_VukGw-Z&ZI1j}HlXj%s_aHotu34ORPz4^}Qx z9VtFRxm>kMyis|k>JH+&sP3+Mi0TQd=c-<%db{c)sxPX(r~0*5d%b-N!`h^}Q1x8Z z%T(W1U8}mW{Wg=gAFR5Q>dC54sJ^ZGo$5N(E$o+&y!|$+%T@PQy;k)@)$VqIz^AYD zYU_KlYJ=(w)tyx5sxDUDO?5BT{Z!Ye9;JG+>glQ%s9vI)6S4izmc!HtYFE`Bs{K?q zQ5~#Wq*|xyKLg|Q*-q6?7lJ%b)eiSTUa4w_=OFK|da$Y;HUoaF>M5#csM=v8c>Ffi zdsVHQ54d&PL48K`W!2YJzf=8D^>Qon z?w}f6&$0EhKzWhsO4U77vwb=8!fT(tKK1xXD|0_u6mwuihq+u{);u5qb+Ep(0>P|#lC=+@vQTf&t7a3mDEoy zoV{}8@`XFET4}TWAK!Z0l(t&aSKUXf*V0yHaO-FP`gE}{M%JIsAM@L0_UHS{|86?p zH`agN%%3IlZRt1PmvZfIg8ljJ{KfVYj#h1`6>M*x&Yy3l{jm&oH{xUCYi7ghvp&#r=KS72FdDoU;IG4mwdwhtZuet<9L9zoWwP*(q(hjopn5vH4wM`yw~ycd3EQ`9%(j2HVM(ucQ4jzgz9T zw{ai*_F_devT#6n-~aW;{Ok%Ur%3 zTfR=leEGb8XZhZ;`{wd8E5Yq$o8OiMtNy%x^UA*Bxzn!xlc6?dw)@@e&*$g!_vd8a zu)C49*2!JtcXVTZrevGx@@@I-^fP^9y7bQ}ttwnPw4k7%c(lDmQ#5SMu(5W(sHiyO z-%+DR6cmgZIeO$Uo35Z>r@Z|usw=}^`wC|pwRb9*uaizwf|LmN^?{L|){`!~W!#i_ zWrxb{m0MM9HF?~me}4V@pW3wtl-WWE{NIa$e?JQTEq>$T%3CYr12&)X(mFd~9r(waZ?EfA@X)$Q zzqi+QQ_WZ1FsL&Zlt%u1AVy>d?flwv3VDtAc;O+R0zfJ)bX|kTWHBa&A?g zzrOpPy>{+H@Av7|?W5|MN0yBKAs*?p!Gv4aydQb?m8YlNTl(d(_iXd&y$8Ma>|eLo z`Df@?JUZGobi1Fd6Y`7lnYXNH_Jy{CW<_)EwcREwD>2x*udJ-(wFYAw*b2{@nm^SV zWW^Je_DJk$pQ^U!P60}e@syL;!DgJ5ldLe4;_-xk8apeVe8DD(HQ5BQ!Cg!I{)P6` zv7&C?&mes*7DwU(75i8m7Ksm1+{oha zNPKg}4K0p{#J5oFZE<8IK3K7r#Zi&?5XGJrM@Qm?iuo4DMB+mgdsrMBi5DquV6oU1 zt5~_aXIrje%H2HMf(=*h>e-fTgmM?pwrC@jJA1Ze8>QUIvn||c<&K_h>BcB`@NA1W zR=K@rTfQxo+gToF%eR$s%CjxsIOROgwtVB2b3NPgZLOT+*_Lk`<)mj@z6r|No^AO` zloOt9`AU`Jo^AQclhuiX1C|loKI^348QrWhDZah99_MC11yc^x3 zO@ja1B5ybIBR(-1^hjpNl*Dr;bYMuen#z!=iZY}|QHIni%8)um88S^#hSV#{kOoB= z(x@myniMf)x-y2$P{xp%$`~?B8AG;J#*polF=TsX4B0^$Lv~cgkY;5J*-05gW-DXJ z&dL}vM;SxrDq~2CGKS1k#*q2S7_vYaLl!Dy$S%qlva51vNLB26+x~feAwE7iG~_tz zr{ar}ZjSdM%M#z)gMlHtsi_QEt|&uRD9VtPiZW!Cq6}HBC_{Evlp%X4%8)%3WyoHN z7_zrAhU}w^A^R$0$bQNgvcEEh9H5LL2P$L8LCP3%urh`mqKqMjDr3lD${4an8AA?N z#*ibFG2}>P3^_^}LylI)kYkiFDE?35oE0i(hN@WbWN*P10R>qKPlriL5 zWemAa8AGmD#*iD7G2}*N47o`eLvB{akXw{PLr#i~wC$gFmG>bhhlcdxRVREB(@C__F}lp!A}%8-v0WymLrGUQW58SG2~Ze3|Xg)A-^eO z$nVM+@`o~p{Hcr~e<@?g-^v*Bk8)_pJF&fN`{yO?3T*t{z>rjX??WQdq^o0}bcx5K ziL>m&LVF+0B%*5F*Rq}VW|R9^w$t(?c_YhqTAoAR(6XJD=aPF{w$t)FaxcqvTAm{J zv}~v4?a29-?XouqEsS=;pu{u`{5n16#%}fG!SfA-e)P zJFunf2I%C#7PC8`qXS#c4FDY+*n;)|w0B@jnh$7az(+Ve0VxNzq`d%n4s1z#19BbM zl5PmdabQcj5g_Tnmb4Eb+kq`&1F{VGSZ8BE)PXJO z0DuY7A#T6j8N1&ENnPcqC$VT~(I7vY-6WcHz1*Tf(ZmOK=_RmebK1+IEy%KHFj*E2 zA*MgXvABmj#>0kCK^0E@-|uxKm*i?#${(N+K~ z8VA6l@c=B^8h}OH0I+BR0E@M-0)R!804$maz@kY2EUE&87Ht-d zWp^=)o^Wvn$|C>ZVtjHm>3+FIHPOUocF`}esFwD!sE#a)rjcb)Jy{ktkY!OLSr#>s zWzlr9ESf=iK1 zTmTle0I+Bt0E^}WuxJ4QixvW~Xcqt$?Fzu6MF1>X48Wo#fY74qXsp@<0btSL04zEJfJH|Fu;?fN z799=1qGJG9bSwaijssxP@c=A30f0p(0LKxol!(b$P5NNO7!X~&n#q9=oKRy65; zxkaZ(6F1o#pn*ka&|VguNtQ)tk!8`@WLb0$Sr(m3mPO~0WzqR$S#$we7F|fjqKg1n zbTI&nE&*WCr2s6t41h(K1F+}{02W;dz@n=FSadZ2i>?7+(X{|9x(PVMYjV&i%yNkUN=Ef3;l%pG+A`4TXaV>>3+FI_e2xF z^^!&R(q0zbN0vqRlV#BZWLfkeSr$D+mPHSfWzi#KS@bAb7ClDBqQ?PP^aKElo&;dg zQvfV_8h}O50I=v;02Vz5z@p~?So8t_i(Uj^(MtdxT%c3vHvgk{)Ec%Kpi@qjf(Ki4r`WApi-vO{_EdYzY z2Vl_;04(|ufJHw6u;^z17X1RiqF(`6v<`qpzX7o5cK{as0l=a^0a)}G0E_+xV9`GS zEQ(~MNBQ9xEegP*EI??{`_b536C`zwy}ud%Ko-TkV~S-Z-7mK&nUy%SuPn-;y)4Ql z%c4B8EJ~4OQ9H6MYEPC$9muk%BUu)8BFm!AWGw0ez@n}IEb0cpqV51J+5mt>Jpfpg z55S_H04(YSz@pv&EZPu&MH>OIs1E>(`U0@10DwjP09e!?fJGYvuxJ1Pi#7q!7i|i_ zqRjxIMTxA~l_p5)I=`TpofVGsy9Wcdtfc$p77flyJk?JY4WYd(DkRIIp=4Q9M3zOx zWLY$fEQ^MdWzh(-EE-9cMWe`AG#Y?KV*pq*7Jx-t0*fc1z=Gb0E@~2SX2SPqDlZ3O$1=kBmfpw0kCK?0E?you&5dkTC{mqY^@2B zn(G%Gw~$5t)y(+Rtfc$p7EQ}abRHm!>S-^F8pyJ!kt~av$g*fUSr*M8%c7ZNSu~3* zi?$`pqV337v^@Zeb^u_}jsPrb24K-n04$mfz@nW2STqNKMRNgI)B?bwc>pY$55S@Y z04!Pvz@l9MShOnuixvT}XfXhbmH@D5DFBO>0kCK{Kxk2IR&10Bk~-J>qB>c0h@V|A z&q}&qZqe$j#Eea4(eAXDMSGBC(Vk>kv=>NrbOHd2P6S}lNdPQ58GuEn0I=v(Kxom*tk^y#NNTko#8%0oo4hYNEi37MxkYDX zCC(Wri_WIKEINlQi_Rs>qVveI=zOv)x_~T;E+osMi^#I*VzMl{gp5U(0Z02W;i zz@jSvSac--i>?A-(bWJfx(0wn*8;HUIsg`355S@u09bS*0E=z{VA0J0EV>1NMYjU5 z=r#Zr-44K_I{;X8Cjg7?0)!TwkrjK;1WBD4HF3_AMgFDT_}y7a_scE1KP&Ok=CbGk z+RLH`$+GAnvMhR-EQ=l?%c4igvgk3gEP9+Qi=H6Mq9@5%^b`P#o(5piGXN}l7Jx<1 z0kG(K02aLfz@ircSo9JAi(Up`(JKHfdKG|0uK}>=bpRH<0l=a+0a)}F0E^xRV9`4O zEP5A!MehNy=zTzF(Y;x*oGr{E|CWCIK3R06fBxr#tfc$p7JZVH7&Jr{eM);-^ch(e zeNL7|UyxPHV9_4{Ecz3GMSlUX=x+cP{R6-v`yBFFwi)dmb-PsK@5V*} zSd<08q8I>+;s7j4078pC%8J#PAgP_aFZx&({q7+PE(*?f@*>0Dwh309cd{z@nZ2Eb0ZoqTT>3 z+7N(68v(GW4*-k$0UKXaE37Su~6+i-wbB(Fn3E z8cCK#qsX#oG+7pnA>iA0bo%n0E@~1 zSX2(cq6z>ORRXYRA^?jf0kEhFfJKu5STqHIMb!W-nhL<88UPm60z!+1#A0unAgPP| zRH#rEt@XaBE|zq^+@i)<;*a67sEPKnXgXOI%^=I7nPgcsi!6(_CCj4i$g*gAvMkzx zEQ@v|V^K2zi*^EF(QE(~?F_)8IRGr03&5fl02a*yV9|U47A*i^(Lw+g?E=7}T>)6M z2!KV40a&yIfJI9IShNg)MY{p8XgL6jRsgVQB_On@J{Bt&VHOqnsZfI~y2USKuZktz zFSlsVSfXTgUGVzU@{gR0>Gj} z0a$bx0E^ZDu;_3A799b=q9XxVbQA!Kjs{@SF#s$&7Jx;^0kG(J02ZA9z@ifYSacEq zi%te$(J25dIu(FLrvb3&bO08e0SGPHJr41WGnRC}+@f=1i8W(n z(Rs9&Mdy=c(FJ5#bRk(5T||~e7n5btC1hE2DOna>MwUgFld?7+(X{|9x(PVMYjX6=neoD-3h>= zy8u{pHvo(70btR+fY73|W3j7Ekkkyf=p0$(Kid_*FP3z_+@gnKiD&Gqtiijn57S;2 zJwld6kCJ84V`N$MI9V1wL6${Nl4a3TWLfkySr$D*#-e8dSo9nKi=GEy(F*`9dJ%v{ zF9ERVWdIhv0>GkI0a)}J0E=D+V9^@@EP4}wMQ;JH=xqQNy#v6acL7-R9srBp2Vl_$ z04(|tfJGkxLW>@V#eOhBQV;kE^@Fl#iT6bx$CB=sTl9G>(RI8m`hxbd=u5IJ`id-z zz9!3}Z^*LfTe2+rjx3ATl4a5NWLfkB8H;`dV9`$iEczLMMZW;B=vM$1tpi}uZvZU% z9e_oD0I=v!02ciPz@onaSo9A7i|q5=;jkTxq5v$)0$@=LfJJct79{{!lnub5Bmj$Y z0HH;n#$sbkkklx@T>Y6W@}FXj=f;!nms`|6o|v_bEb2geS=5m%i#m~IQD?F&>Oz)9 zUCFYj8(9{0C(EJ@$g-#h8H@4(Skx1MMZEx6)Ej_B8v?LsBLEil0bo&I02UPhu&5sZ zi~0kwXk!2t4FF)#CIBqj6o5sW0kCKw0E-3zuxN7t7Ht8*qQL+x8UhF{O2uRQnINe( z-WRotha>%q{Or0go^-$5qG9pGc_p%FIPGQ82(m01NtQ*U$g*fOSr&~U%c8MlS+pft z7HvhAMdQd=G#-FOTLZ9Y8vqtf0ANuG0E=uQ~(y$0I;YQfJJoxESd(uqIy7RQBgehunCen*kZg`7Jce{QA0fG zez`?6;)zenWYJ98%c5CiS+p%#7HvnCMcb2Q(GFx;v?Ey-HIrr0PGng$n~X&}1F&cg z0E^}Vu&4!qMe_hyG#`LP3jkQO5P(Iy0I+CR02VC*V9{a#7A*l_(NX{wEdyZDZU8J= z4#1)n04!Pwz@k+EELsh~qTKlkS&Wv`;*-MWrm- zm-ez~Ke8;^pDc?GAj_fy$+GAmvMf57EQ<~y%c4Wcvgj}}7Oeqb(cu6rIs$-2M*^_u zC;%264Zxyf09bS^0E>XbT0sl?gL=a z{QxX_01#SqUOaZH36lEJ-vK#a7VYgvvqTGFUKV{rmPOx^WzlzJS+tfc zi@qnzq94ez=tr_F`iU%yekNnlF90n16@W$S09f=J0E>PHV9_4{Ecz3GMSlUX=x+cP z{R6@|OC;Sdx2RJhQC2I9I@4Yjbs@{5u4Gx%jVz10lV#BcWLeaMEQ|8V zvZyCn7WE=yQEvbiZ3w`kjR08G2Y^L=0a#Q3z@mNtEb0%yqKyGqGys4_n*gwAQveoi z2Ed|$04y2=z@p6oShNKIiv|O*Xb1p{3ISL&6o5rVfY722iP!=YBvtR9yY83>NBTXy zV=7K0-7mLjWFm3IG+8u?_OfU+Sr&~U%c8MlS+pft7HvhAMdQe_XgpaKZB3R%+mNwn z0sxCj09aHCz@jn$7L^0Ar~-gRl>jW72*9FA04%BkV9{g%7EJ+QQ8fUIrUJ0227pDi z04%BlV9_)H7S#i=r~!aQjQ}ia0)!R~PsFY@K~l4GOq>z2=v@!f6G`{WE!sAbc&PSkwZ*qIm!;nh(ID1pq8s z2*9FU09dpu0E-p@uxK#=i<^djha%FF04zEkfJJ8ju;@$x7M%saqO$>5bPfQE&IMr6 zd4SNOeG{=QO_0<~AC~PWi#qvv(fNs_`{fp0oJedpQx;u9ds%cTSr%PJmPMD7WziL6 zS#%{?7F|V_MOTw$(KTdQbS)W+t^;7v^#Clo0f0p}0N02bX0z@l3KSad4@i*5s8 z(d_^%x&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^mEP4QdMGpe7=pg_WJq!pfx-bzt zzywL1>{lHxl0}c%WAR54N%zYwdLogyU|U)AB<*F`@aW)xrCs z$7NA_Kcan^NV;Ec(YJ}jXWPr7?`SWJ){_hec016daRNR~xEk!8`(WLfkJSr+|D zmPPBxSo9kJi+%@S(H{UT`V)Xfe*v)QZvYnk1Hht4wubFk6a`>W766N404$0FuqXk* zqHF*bB>`BJ1HhtO02bu|uqXwZE%c34+S(HzfMLo%~s25ol^(M=r4au@-BQh5C0bo&I z02UPhu&5sZi~0kwXk!2t4FF)#CIBqj6o5sW0kCKw0E-3zuxN7t7Ht8*qQL+x8Unzg zLI4&G1z=GT0E>zNSTqcPMZ*E1MV+%_^(IK_2S2;+k{yopxAkHFi0q{Mzk$g-%Ej74PtEGh?JQ3U{tDgjtD z5r9RL09aH7z@o_jESdtqqG|vZO$A_44FHR30a#QAz@ljYEUE`!Q3C*r8Ua|;1i+%{ z04$mTz@nLe(4tYaZ@@zJvAHGex~R(8_;a*KAzPTVm^7VSuTS=3CHMLUsY z(QL9T+LELsl0q7?uvS_#0SRRAnn4Zxz^0a&yL0E_knV9{OxEZQ4@Mf(7-XkS2R z(RSIfcTJGg`~LZ&?PZbwM^y3svXkzYTXax%;-3~-bTI8@(II46bSPOC9Y&T#Ysj+b zaI!2qf-H-UB+H_s$g=2YG8P>Jz@lRTSaci!i;f3i(Fp)7IuU?HCjqeNWB?YO0>GkE z0a$bz0EEIJc_MP~u9=xhKModdw4a{*X%9srBZ2Vl_!04%x?5L$FVc5J{r zvnb&w)CbCm1JL!J8MVDnKDi+A1%V{r*t{}^zE6K9xDzYrPnkDRMK=Sm=oSDL-3q{>+W=T}I{=IB0ASIb04%x-fJJu$u;?BD z7TpWLqWb_?bUy%#9spp`g8(dg2!KTo1F+~302Vz8z@o{sdsr zUjQun8-PXs0I(>M)UX|kq5v$)0$@=LfJJct79{{!lnub5Bmj$Y09cd@z@j_=7Nr1K z)DD0}?EzTS0f0pv0a(-tfJL1Fp+(+UEGi&lQ9l3{^#@?l#sDlD0KlS6 z09dps0E;#QV9`JT77YSm(dGaw+5&(@g8^7H1b{__04y2`z@j1m78L`qXcz#Ch6Au@ z1OSUh0qQw9#S^~hLr2s5i2Ed}-09dpffJG|+ShNy=MXLZ< zv>Jd#y92Oj4*(YJ3BaPg09dp)0E_kkV9~w+EZPr%Mf(G==m0=y(T>U3<0eRIq7TcO zWl^)AT_2cCx?gV5p~=J-t7Oq(w3kI|$g=2gvMf4+EQ^jL%c7&mvgl~CEINiPi;gAB zqT|R|bUXlyP5@xhi2y7*34lc>1F+~602ZAJz@pOtSado7i_QRG(U|}&ItzeBX9KY4 z8~_%b3&5iD09bTB0E;dFV9|vDEV>AQMHd6G=n_C^(ZR`Bht+1$1s3Cn$f6(o;?bqa zr2FL-U71V_-9r{#MSEFvHCYy2LzYF?l4a3#WLb1QSr*+umPI#`WzkJ!S#&cQi*5m6 z(X9Y1x($Fuw*#=~4geP23BaPe09bT40E_McV9~t*EV>VXMfU@+=m7v0JqW;}hX7dg zFaV1l0btRi04#b8fJKi3u;>W@7Ci|FExJ4zYcxSpYyG>iSIDB%yf1nxnRLJ0qUVx{ zReQ;z=V>pCULeb&7s;~dC9*7fnJkN5A#27JUl9qR#+W^f>^Fz5rm+mjEpK z3V=ml1F+~D02X}E&3^$xN9F-^fT>c z(Jy3K^eb5wts~2#-^jA)cd{({gDi{wB+H_|$g=2fG8X*I%T3Zh+9DACj^6O_0=WKGOeD77cTyy5}U_FSn>?P9nO$Eb2vjS=5^>i#8<7qK(M1 zs1I2d^(D)q0&GzNf0V*#N>J#u23 znjon){tiffPB_wU@*~=oIZ5}+E!sLKG4ViIv<>ZL(FC$ADk00FQnD;6Bg>+4vMj0~ z%c4rMESgA`MU%)_R0Y7I$p9>x0>Gkb02WOJU{MVKi)sN_R0qJKX#gy$2VhYH0E-#{ zSkwf-qUiuEngPI~nE))B1;CmqizP zU(}qFbidr9IXQ`A4wgl8X)lXf$g*f2Sr*MF%c2EjS+tNWi*_N)qFu?dXc1W!Ehb~p z5z^!K02b{Az@p^KmZmU1i+$$0ii{+b7D7|AgQhWRA^^eG{u!VBq!;9xkZQP zBwjjH79Bx*S#%^>79B;FMMslm(J^FMbSzmG9Y>Z$$CG8z31nGxA{mQL0$|a}04zEM zfJLVQu;?@Z7M%{jqB8(kbS40c&H`Z3*#Im$2Y^NA0j02ZAOz@iHPSacx(i!K6S z(Zv8Px&(klmjbZpG5{7`4hSteEGM?k1WDZ!v#1i+$)0a)}10E-?4V9{d$EP5P(MNa^*=t%$; zJq5s`rvX^>3?Q`Vs+`!?CP=ErV*F}ZG|-P|&*miEFSqE$oJ8}Hvgjq+%c7Ubvgj4E zEP9nJi(VtkqSwi?=nb+gdXp@R-XhDQx5-%a4gibZ1z^#804#bRfJGkwu;@bo7JUT3 zqK^Ss^a%iqJ_TUWX8I}f5E&wd*3c#Xn04(Ybz@iNRSkwa$TJ&>H>`4nJuxK~{ zi$(yjXe0oOMgg#BGysdn0I+B*0E@N+V9{0pEE)$0E$WpU>vWu1bW^s8(>pgD>3`;7 zd~VYHa*IlG6U8UUqEgz+qB629DksaL3bHJ!B+H_SWLY$cEQ_khvS>0{7EK{zQ8fUI zrUJ0227pDi04%BlV9_)H7S#i=r~!aQjQ}ia0$|Z}02a*vV9`tf7R>@+(Y63A+75t4 z+XJv@2LKlB2*9Fd02b{8z@piJ(4uW}W7AEL)Kc$$Cdi`NV8E7}bidr9dAW(*Pm)FR zX)lWwkY&+AvMkz#EQ@v}%c4bOS+tlei5)799w{qJscfbT9ym z4gp}%p#Us83=mp0H#c^+36iSu?x#f-P4*8Pt;tQgUvAM+xruvDkwr(-UKSlgmPN;s zWzlhDS#&&E7M(zrMJJMF(Me=kbTU~MokGTtJx)Ojz zR{=tcj>wIDXo93FEXI$NMH7A4e|2us{c?-0&rQTmmqjfJOHMu;>8*7Ci{SqK5!j z^e_O69syv{qW~;=41h(C1F+}`02Vz7z@n!BSoAaii=F{s(X#+7dJcd^&jUh>uFZ`N zG(l32`h~{pWYPCNMtdPQ>3+FIujD4G&Xh&3(q0z5MwUgdlV#BxWLfkkSr)xTmPK!q zWzjoiS@bSh7QIKtqW1w<^Z@{iJ_KOVM*uAP7=T5e0I=v&02X})z@pCqSo8$|i@pS4 z(N_R0`Wk>m-vF@aTL2b)2f(7W04(|*fJHw5u;@ns7X1XkqMrewMK9&XmY5)^MJ~?E zvMAxd8S+bR(*1Iae$P!DceX70gZ8rMPqHlfi!6)&Cd;CK$g(Jsr;)oXijrkf7Fia> z$g(I-#-aoOi?RV&lmuW=4giaC0a%m=z@iiYi`oIOs67CSIsmY!BLIs!0kEhu0E@Z+ zu&65li@E`@s5=0QHUMBz4*(YB1F)zk0E>D7LW|br#%?x2QVadO=r>ukYr;bByrlc( z7WK_bymGEADxkeA>PMDE{mHUuW3nt7K$b%c4PKEZQ7^MOy%{ zXfObah5)dr5P(HP0a#Q7z@lOR77YVn(Qp73jR0WLNB|a%0$|Z-02Yk_V9{6r7HtW@ zqOAZ}G!B48;{jN-H2{mY0fZK9lo$Km1WEPs?x#;)IMV+;$HIiXr2FL-mFFdTUm%Mr zXfKN@$+Bo7Sr$zq%c3f>ESgM~MN`PKsG2N`rjlh*4H=7S0a#QAz@ljYEUE`!Q3C*r z8Ua|;1i+%{04$mTz@nJ|ESd$tqHO_Kv>gD8wg+I*4gf6L5r9R_04&-GfJL(bShO<$ zi{=2ZXf7bMs5CD&!30V9FBQehWYHBKTJn5)799w{qJscfbT9ym4gp}%p#Us841h&z09bT50E>olKTR zr;ugQsbpDn8d(;dPR61$09bS;0E^B7VA0tCEIJ2(Mdt#r=sW-xoe#jG3jkPjApnam z0$|a_04%x$fJK)Au;?-X7F`a&qALJcbR__bt^#1u)c`EI27pD^0z!+9&Wk;5f~5BI z3ysIfq5>c3UzeA3zucmm@)F-%CW~&Sy)3$gEQ@X>%c9%JvgmfQEV_d%i|!=LqPxhl z=x(wsx`&KK_X4o!J^&Wo55S@a09f=O0E-?1V9~<>EP4chMUMio=rI5mJr2O4CjeOV zBmj$^0$|b804#b2fJM&&u;@7e7CjHZq89*I^dbO@UIK&`-H;dSa=BR)_fPNND2x7d zrC!cUx?gV5>v@UcSIVL{XfKQ2B+H_=$g=2dvMhRsEQ{VH%cA$lvgm!XEc$>fi#{Y{ z(MJF*`WS#kp8&AvQveoy2Ed}v0a)|}0E@l^V9{3qEczONMc)9h=vx35eFwmzwE!&o z9)LwZ0I=vs02ciOz@nc4So8}3i+%-Q(KIA@|&Hyax0>GlK04(YTz@qK|EZP8oMLhsmln=n7 zo&YTB1;C=-04&-NfJGYtLW};$i=AtNq~7s^*q^fKRC_GmCzW)++@k)e#C_MwqK#=U ziw2No(I#YBv?*B@ZAO+w1Ie;z5Lp&&PL@SmkY&+eG8PR1U{N6ei-rQQs0e^X#Q-cC z2Ed}>04y2-z@m`=EE)yCqR{{>8Uw(hu>dUE5`aZp0kCKs0E@;0uxM)l7HtE-q6q*j zDgj_oDIm0{AQk)A1WA4A@5c5^g(Ll!ye}$CCEYK#XrleR(G9X_676MC6AmPJ#^vZ#hEi)zWTsE#a)rjfCz9)Lv+04!<*U{MnQi>3pxXa)d_W&*Hi766O3 z1z^#304&-bfJHk1uxLjB7BvH~XeR&`%?4o6&HyZ$1HhuW04!<&V9`7P7R?8Q7FDET zo0}l1&HWvaN?CN2Jr-Y(O1fWe(V|ph%1yFpG3{m160$5>N|r^-$g*fRvMgFomPISb zvS=k)7Of)7qSa(9+8uyJdjPO#PXHF}1;C=c0a&yT0E_koV9|a6EZQG{MF#+|=s*A# z9R$Flg8^7{2mp%?1z^!(04!Pqz@ozeSabvci;e_f(NO>_IvNmKv`Z@X{}6W{z){uz z{{PR(*~2bu%5DOLCWKzo=)Hr4-lb^>ArO$71Ox@?iiiRt0)kQmyMh%|R1_>IA|i;W zD2j!q0wSWK{@$NG?`IOf_ujelpSd%CX7KFmncdB1_d&7=2~H6p!42lG@o!W`cbL!g z?+W^jFQaHh&|UF@D!PZutD==`Rdg>~6|G{cqWjpYXf<0EtzoO8wQN;%KU)>8W20z2 z0YwiGQ1l=HMH>hx+DJgrCIX5!6HxRJ0YzH~DB4Ou(Zd83JwiayqXZN^MnKWy1Qb0% zK+%%~6g@>i(bEJJZ6ly)I{`({5IjZ8g3gNqB>0E<8<6FyXtDW-_H58^d>KVA2Hm4O zRM8GDuZniERnbdqRrE4j6}`e%MZ4Il=vB5VdX24$UT3SK-E0)SK|s-)1QhKdplB}v zMQ;&M^fm!S?+{S*E&)aR2q=1wfTH&aDB4dz(FX(+9U!3SLjsBp5>WIJ0Y!%hDEgRy zqQe9f9U-9T6N0Dc`Ji)EfCPsaI4`K87tH&jqd~v%WfXlLbgy|?6@9_wRnc*_D*BSG zioRm2q7!UY^fg-*eZy8oC)uj#Ted3tj*X)42`Ku3fTB|b6rCoZ=nMfxX9*}eM?le! z1Qh*5K+(?x6rCra=mG&n7YQi(g@B?<1Qh*BK+$Caihd)Y=n4TvzY|dO2LVNY5Ql*fTHpQ6jdOgs3HMHl?W)hhJd2V1Qb;vpeTvpDf&C;EEXWa81p&WKdPvqyv$cM z+HZUrMKz<{$6ixKwYa=0s?AnKb=az?E?X7VW2>V2Y*o~Nt%{P_swjo6ic;AqN+X~s zoq(c-1QazQpr|ncMNJ4OYDz#+GXjd56HwHGfTETJ6tyCts5JpaZ3rl8OF&UO0*cxb zP}G5dqK*U1OqP}cZ)Q_!-`ml*bQ4Rq`V+bf3OF&UB0Y&2o zC>l@j6m^SsO1~kBT=P}O3{_9Os%QpV70qO$=wgP_&7FqRj*pJw!m!76OX45>WIo0Y#4xQ1mDPMUN3s^f&=UPY_V_ zBmqTF5m59r0Y%#gDB4ay(K7@TJxf5*a|9GUPw*7o6YXpiAi)LZtBxyGQDWp1wrIcc zWfZ*>?Y{AjDtejAtD;xfs%RHm6}`$+DAaqdju4{Pe9Rr0*XE$py&VrMIRDSbdZ3ej|eC_L_pEU1QZ=6 zpy&tzMV}B*bd-RiPYEbGM(`Bvh<3ggAi+N7-Oo-{R9Rl;`z+dTd>KVw%Ky*$JyrA- zmsdq6*sADjwkrCDt%^>vRnfO>RrDQO6@AZEML)1r(J3~HP7_dchJd281QeYkpy)>e zihd%X=w||o&J$2{fqc>_^{n@H$09zFeWUHb%}5m59v0Yy&` zQ1m1LMNbh>^fUoQ+XyJyPC(H!1Qb0>K+$sq6g^Ks(F+6=y+}aO4uYp>RgAMlfCLYl zuR7kRihSlB)6N*b@nsb4igBMfs)}Ca@~Y@Hwkmp^t%`QDRnZ%4RrDrX742cGqP=WY z^cGtcz0F3^I|LNHOF+>+0*c-vpy+)9iuMyw^Z@}y2M8$okbt6t1QdNlK+z!riasWw z=r93AM+hkTgn*)>1QdNrK+!P*iasNt=yL*!z94vtUXF1N3XtGc^X}&rRn*4(4ao5r zzwu=heI4UoIHroe;qt2JBwH1I%T`6-u~pIcY*q9FTNRyRtD@6vRdj}}iq5i8bdG?c z9|iGZS?2`D;GK+y#PiY^jR^a}w+mk22Om4Kql1Qh*7K+zQfihd`c=nn#l{v@F2 zDgi}*5m59u0Y(21P-MmGC*~-!37(>_Vw|#{iK5-+ebEV36lX|9#rlmeqo_oz+w2Qf zb5>I4+kAfTuw z0Y$Y4o+4kYGeUp_517BxcVoTJ^yLGZe8Lv%H@=Lb`myfpFI72q@}KKv55Zr>JhMvsr)y zFPQIjtfz|PJBs8JwphRMWfb*|b@!Z5Mg6$ED(cTxMFZHXXdqh^4PvXJ!E9A@9a|L* zVXLB{Y*jRjjiTWM6pbLD=z0Q*ZXlp2lYpX;1QcZvP&A5wqHF?+MiWq!LqO3O0*b~G zP?SqR(KrH%#uHFCJK+z-uiY60KG=<

    K*Hx5+K1G^L^KSRMArNmugdE z{l=G3G%eOGc~TWk=kluPCblY?!B#~x*{bMfwko=Xt%_!`Rncs=D!P@eisrCUG?##) zc?1;AC!lBn0YwW5C|X27(QO12-A+K!VgicpAfRXo0Y!HbP_&eQqPqwvx|@KaWdsy0 zC!lBr0Y&!^P_&YOqI(G_T1D^_<;OZH0wnl~d0$kZiW-_{*Z0NxjW46<{#duqcdBR| zmsdsW*{bLPwkmp%t%^3VRnbPaD%!+WMVr~G=pnW$+QLTBRsxD1CZOmM0*W3bpy)9I ziXJDR=m`Rfo+O~?DFTX~CZK2=0Y%#hD0+r~qGt&xdX9ji=Lsl!fqIYS{o6D=BH`uD^O|~l9 z!&XIm*{bL*wkmp?t%}}ZtD<+=s%Re@Meh+%^gaPa`w1xefPkU{1QdNpK+!=0iasKs z=nw%#9}`e?n1G@q1QdNjK+#bGiasTv=okS-pAk^>IRQmq5KwfSfTAx6DEf-vDS9>5 zd0Bu2TbpOsuc@LaGfu?%jW46<+gSJW)2iq@F0YEdXRD$g*sAChTNRyVtD-Y(RdklE ziq5fB(T{9Z^b;FJKNC=No`9kY1QcB)py(F@iY^gQ^eX{HmkB8Pjew#n1Qh*FK+zur z6#Yp+(NzM9{vx30Zvu+`A)v^L(@)z`WD`&nML>~5K#`B&Df%YXvCfF1SIxina8ebm zHj3Ohzwu=hm5g(%o>N7oxV$O~vQ<$uTNTByRZ%Qk6~(btQHZUI!faI(&sIeVY!sCy zpr{N1MP&&nN+h7D905h;2`H*SKv6{kiYgIMbPWMTl?f=SLO@Xx0Yy~_D5^$4QFQ`} zY7kIVlYpXH1QgXKpr{T3MRf_DB7dCIRe%IPGJgXSi1R+vUu{U$i}M>_Mo~(fJN744 zl*;8*Q5stnrL$F0L$)ev#8yR(*{Y}sTNO2BtDP0|NZ-S?&L7cNxfCQtAqGVOn$c#R5e&fq18W86`bzT(>*s5p< zTNMputD<3SRWzKfibk+i(e-Q;-9SK5CILkw2`I`UplB2UMcD)tjV7Qdhk&9n1Qd-W zpeUDsqHzQijVGY!Mgoc^5KuIcfTBqR6ip_eXbJ&EQwb=_BcLds;3?`C=Nu9s!94S| z>;9^!zIk6%5a&0(jG`HF?k^Wr(M&F{if(4BqFdOiXck))&1S2jTiL2;4qFw?Wvilj zY*jR$jiLnv6fGp6Xb}NLw-HcuI{`(D2`IXQfTAS?6x~Tc(NY46?joS*ZUTyy5m2<8 zfT9%y6x~BW(Mke}?j@jT6#+%}5m2<6fTA@7Pto)^r`#{1Xp8wm<4vmQg!#tDwQ+vq z%P4vv&Ta9lDteI1tD+5TRkV?ney zmsdr5*{bL*wkmp?t%}}ZtD<+=s%Rfu6}`t+Menm!(SA0HJ|Ljz00BiG5>RxIfTE8G zC^|$y(Z>W79VVdY2mwW(5KwfKfTB+cC^|+!(Psn{eNI5p7X%a?C!pv{0*byOpy&hv zMPCz8^bNsNv^&n(B0z#;%%^2FIOOPky{Kl72^h2Ec*6*t56qi>;r`f9L3|keQ zWvildY*q9lTNVApRz*LvRnd92D!RZ%(M1A^ej%Xf5&=cO5>RxRfTG_BD7r#G(eDHl z{Xsy{p9BydKv5L}ijoK@s!BjnH3EvN z6HruxfTEfN6xAZ2s5SvbbqFY`OF&UQ0*dMrP}G3nDJm6m(gaA*HE@CV8RfTH#U6m=k=s3QSIod_uEOh8c=0*bm4P;@N;McoJ}${?VqI{`&K2q@}F zKv6FOih2`J)Q5ngz62EYBY28ZL(X&o60B<87p1A9BWCmu`He55XmH3~ZJ8@bvwYWa zc~vxot%`=SRnaiEDjLpKMI+d%=z6v)x`C~VGTEwVBpXFp1Qd-TpeUPwqR|8tPaWfTGC+6ip$ZXet3kc?1;Y6Hrt@K+!Y; zil!4hMFT_5E&&oeZvN_QkSasKs%QaQ6)j||qD5>J-9|vs?F1ApCZOmJ0*aOpP;@5&MN0`Nx{H9Ky9p>- zMnKVW0*Y1;P;?IgMJov?x|e{WRRk2>M?leP0*clUP_&kSqWcLbT1W5{%?vqFjwo7d zzR-BHDtgbnFIpe+8(&7z#*kZG{yB)q`=U);UKMR-tD=Y4s%Q&a6>Vj!qKDb4=n=Lm zdX%k-9%HMb$Jr=)f`FnY2`GAsfTE`fDB4Cq(RKogo*|&fzRnhxwRkWY2iaubgq62JI^dTEX z2MH+ph=8I)1QdNtK+$0WijELa^a%k)M+qqUlz^gR1QdNnK+)#}6n#NJ(QyKbz9gXN zD*}p65K#0r0Y%>sP;`=jqHhT(`i|f!+7oi_79hcF^S)@WDtgL1yZ%1pH@=LbGa+|d zNmX=~%d4VuY*q9lTNVApRz*LvRnd92D!RZ{MHkts=ohvsy2M7&uLKlbCZOmy0*bB> zQ1m+iMSl=b^d|vDR|zQki-4lP2`Ku9fFdibpSGjOCZH&afFg&0A|C-oE&)X)2q^Ls zP!u4bs3ZYJr3jv)Qz7TD00~Z(={v28?u~rH7WNxoMp0bY{WYkHLR?-Ih1seoo~?=! z*s7>BTNRaItD>@ORg}n9MdjG4s5~1*6$mJ*NI+2~0*bC7pr|qdMO6qWN+O`BDgi~+ z2q>yfKv4|>ifR&2REvP3+5{BUA)u%(0Y&u)D5_6DQ3C>sk_jkEA)qLg;3P|pW z4+4sM5>V8OfTG?66!jsXs4oFU{Rk-PPe9QC0*VF_JVgz|&PV|gY-B!1Yov-Y%(Lr3 zVZZTZ6b%i#^Fpd<7?)Q?!`Z561X~qd&sIe@uvJkeTNRCDtD-EnDjLOBMcHf=jV7Qd zhk&9n1Qd-WpeUDsqHzQijVGY!Mgoc^5KuIcfTBqR6ip_eXbJ&EQwb=_BcLdsfT98d zilz}zG@XE=n+PbHK|s+=f~V-Zu=B7034U$f7Y$KGHO)t~o5OzN%P6`v?7kDPiso>6 zRWz5aisrFZ(R{WlTEJFC3)!k@5nC1A##TkQvsKYzHj3^bplAsJMRyWVw3L9Ny9g+{ zn}DKa1QabNplAgFMfVU;w32|LdkH97ML^Mg1Qe|%plA&NMQaHtx}Siebp#ZxC!pv7 z0*W3ac#39)opS;tIMBTNnXQUmH)BKCZ+sa=4~5;BGOB0`msdqw*{bMawkmprt%@FH ztD?u)s_1dHDtdygik@VvqNms>dYXWuZ3Gl;C!pvV0*am`py)XQik>H+=mi3bUL>Gs z2LVMp2`GArfTEWPD0+o}qFn?Oy-GmQYXlU%PC(Ia0*c-spy*8kiuMpZMVrD-Lje*T zXTE!Xvnr}!-WTl+`;9N7=-se8AW;?V-(pRJ1avsKXtY*loCt%^QmtD=K! zRrC>C6&+%u=wkwk4iivxgn*(?2q-#AK+&fJ6dfa==raO}J}02)3j&Ic6HxRe0YzUC zP;`QTqOS=k`i6j_lLQofOF+?g1QdNwK+z8b6rCb?irx-8GXzMmuKD4icT~|I@-pA) zu;2JHihc~cYs;&mpSZj#`kAeY&a+j~1-2@>$W}$auvO6|wkrCSt%@$QRnc#36kQ>p z=yw8&{ve>}PXdar5>WIP0Y!fkQ1lN0MOM6i+KwWdfTAb@iW~xpd;}D^1QeAZpvX@^ zQGkG=k^~f$BA_TpKv6USMKJ_V(b=%`ng9v*G4G4csiL;#BU)^{-}o|$;^W<~DypIc zF0YD8vsFoJFmDnh{hJd2V1Qb;vpeTueqN)TG zRU@FNIsrvB2q>yaKv69MifR*3REL0~x&#!}BcP~00Ywc6C`u-vD20HcR04|92q;P? zpr|3iQxuAKe3eAeQS(789PfRmzfAD>8pZpKFQcegyj!!fDr(Nqbs?arD*;8<5>V8QfT9cninlpV(Rc!iZX}>+0s%!62`HLGK+$9Zilz`yG?jp&JOYaH2`DNc zplBKaMbil=x`}|I83Yu~B%tVK0*Y=SplBAsQ#35zSuQ|=bItc%4_8I+nh$TYgP_&8QDVh`Sd?G-C-^=vPRYgCWu{qvvd|7c;l&^ZpsAU7Tf=3w<57tV*HUr7bHdG_kB@)d)RT z&a&!+ey?Cz4MOd%v8=SvqAHfvIP`v1%W579*RZVCq3dc{R{PKcbu6oM=wv<1>K3Y- zY*{@+lT$6LZ|H?|%NiK^vyo*D33X^{StCNXH@B>jp$}SG*62_|8_UWK4Q*#x6G9t0 zSk{!#cbzP&AXLArWz7gp?PgiCLOZ%!*4)rvJuPcts8b)yS{%BgpJgo#eK^3fmWRp= zwyb+Y!-rVbn$V_UmbE_g!wAdT7)s8xtSzDZEX#T{^isBEJsJ8Z$FjDEy5w5c^PxM( zTh`9dM-wb-S156^W$g}KKh?7Kh91hdtan4Fr&-qiP^$bdF%E{N-E3KhL$A!TtWQJs z9LxG5bnQILIuW{Sfn|Lg`goCLoeGs-Y+2_*nM*9|d}!-Z%eoXgd$(m>38k;FtgGRh zR?7WvhhJSK4}cwZ*2p7ZhcoV%hrkXmTQ84+9X|4)JP3BU;wE_%>~PjY@-W!pN4Co2 zV292B&Ax^mHvc>FI(FFn|D+q(Ve>x(PP4=2|LEG-4x9faXLCDj{-27i?XdZu;1Vu#JY@K|7n%|FpM!w#E&V{MilHvdT0Tsv(3m7|4r zc+UxWgzT{ScSe@lVe=0~EVskvC;jiW!{$e|*Vtk6v$pH)u=!!hjds}lwA&UtY<^tn zQ9EpY-sDL;Y<^&1yB#*)@%_9VHs7+l(+->Ox!h%k%{R^Mw!`MTp7z>d^KC2d+F|p3 z2m9@?`HSO&cG&#Q-(fp!{_5saJ8Zu8{)HVjUpzfwhs{^NzO}>V%NM8Yu=)J+oEDW@H zrpZHP1rX|ADp>;gH1RrWLaBW$NYyc znrmyT;}7#jw9_%h+=BMrNR;;omU%m`li%g+zHW4fW*2?s?0#;Wah2aeyfZkAR4Te-}Ga{daJXh_Rdi z7Yqhtg3-a|ayOSu{MWfk$+?PMeNddqJ6p59m|{7SlTUi^P&=Wbd)=%OymFB z$`)^xyOSvWUZ7ZtWijL(htGv9xGB2>K3f_5Ebu4dI#T2Vu`PStp z#YS$5+%|c*i~kDAu;l}R9OT`zoE&HlBO)h9n1lIaJXHZM+*7ys);spBSPPnb43Cv{?0cJ8=I|G(di{F(X1?}@RwsU7l0Pa8LBa;M38 zImw0h#f*Zy$X(*yBYpEGkC*#AKXt&Ath^h$PMefDP~MiYeJ4!I&+Ol!X|E>#7Z20) ztb!bKZ&{W;&{^rzQnHPM%+WbxvZhTa$SjySB_}^6*YJ|ZYV^2C1v2Cv^?*)YGUYaA zcbYtL;^axvgcMrFnd|kEB_9#p2u-Jv?Yas7(=XR9;f$3tIOUUE+Zmf=PPI--N-B}+ z#+OKN6OvuGL=QPBXNe?pY@@raJiWBbxIuG}e>}q+WaL_^yXL8@Txm_c(#TA4OUjkjkn<**ld1pP$ux7}GF(-S z;#ZXvc|}ojb#)|1nOkO#&Xg3ldgMe%UPI(1sfFiAj=W$p=LmBhMd$FYV-n|x|DVn= zk#i)ZxV0m%#gSCToYEU2Hz>&|E02aWyF_*Ft>l_dh@hynWMauO&b@UY|^RlWYgw)&c@AY z9k_5>WA9~MI_Y`R<;>%HPM$m^-Rjk0NM@(r0~>nR-IJ4nj1)3I~t3~8CO`DWIZtSF-(Mj^hCGzSz>FrAI%C*P|-pnqAZ%4Y^n8^8C$k{S8 z<yCywvV?C=}gsbVGFKSkpuN*n6=8x`G- zPKB39@5HN;8?Kiy7K(k4`M-MC+Bs*`w6We>Baeiyp-l$&FF>x6acMxl@Wjq!$xWOhQw+S^t;MGkKco zJ$s4V25_2JWr7^_tuSwWBq2oJzv+t_6+Sp}7jyO^WAH&wp_u0K$V@K$b0HMI&?meFJY9lA)Ugc#)R}r~M<{isGc_OCg=YsM`M~dMS`5@;E%#W?jO2-p8c8U~oi=fl9LG$UoK=u4 zpGdWlhh?-0a?UYRrZ-8>pOQQ}y{VL}yzJaI@|o52=E)ONCd%h#^+)GVsXt~)Qu5fO zFyk|hk=24erG!%@RJSjO}KB>~1hDFg6 z%%Z22>7M?G8u_T8H?io^@}5f-ez=VQ&&>Sya|NE)7Co(nka_ymr|W>ikMZd|i!FLa zTJ%J;=y|9-qlJ?9C&JvkLeo5lEqZ!c?AawxVT+zh@`uAbyNtYfF!r8CM&5Gs+*O~> zM&3g2PhjC&&7ZhJ*RVFvVQ(yaugFu?q9>6>&mq%`-eqFlK#06{p0}nKJ`F8=##!tS zRnZ@fqUVe9PAqa2Mb8!sA4Bgcr*&bZRND4W;DGIAM-*W6#U6avAwLupFbzUx=BbJP773H%EC<i<1gd#?f*yOy z18VkAJ>JvY+Z*)wX-jW^r^m|jz?<{e*W>7R-kz$*$2)j?haS&&^7dbPY}(b^o%A@X zo44=KR{h=NMy}VsUkG=bNd$=C&?dR=Hdi-pFw|~%M(qL~V>v7BwZ|CdrN%``; zd3#>c<3;%*xY_^cv3aJqyXf)OEN|bb$GrmGoc|*|mKx*jL_PM+_4f68yl=d>AJXF& z6TE#|kJTo7J5`UlQ@uS+k5A`&`xQN2n&xeLx_4|j!#iH9$GJCq`z}4cJoIzc zx6A9X|2%JJ>T%5iZ*SG(my5i8R*y9ndpli^g`wcc=>K`JIlOd>lNNH zLyz-UdV853-(BVHBYKQoQIEAYdApGwCp_fs znRH0_E9~Cp7HiIdK~8BP)_K|6P4qZvm$z@xIdG9&dZg+bi|B{~d21 z(_{R5-map@A^W|ZqsIpic>4)GetXc{7xY-~V{bRp66~Bs>fm9d3&rLH~!%5r}X&!X>b3c#|G!T-9nFf zKY4qO9(SJi_FH=V`=Ymlzj(*azk0`hdR+3Gw^!@&;P2i(uE(-hyAne@*M?cKcmMp@~s7C|E9+@`5pta z+vst6lD8M=aaT2O@6%&7`5qo~{!~3SHAh#zr$BdKb1Ws_&!NYm+DGfo)#F6%Gjz|= z<2>z4buZWBD(#!~xJ{3{^textpXl+V9?$FXFFlr$zxp?~KT(f0%u#Ot5Itt;@g9Bo zeR|xW$A|Rzq#n2HF<_n_$@N6*F+q=sdaSI+YI>}zM|oP{-G6$_&|_ac4%FjtJ<5l< z$oXgLakd^8>QUa!M_w-Pz9Yw#dR(u^je6Xv$6b2dtH*csDDN&Jmp`n>66PpxWJtFh zA}{ypaf*39C~tphv*YA1>$O`c`7E6ZQEsZ0k}ZG3nInIXQ|z^l$;+B3XX?)R=>z+9iP z#r4V4vVUD)$-1_+jw>nlvKhrr%SmfXJ=>BGF@?XlNP(2%Z$}_QzU@kydA+9ddT*E0 zTt-e>x63zHCz%uaikD+ZBaf50ee%b$@cPW3e{&h*!Tjo) zW?MIzcV7C-yv+RGqess7YHQo-uIDia&Ua8x^P)f-`(IYMsr%&&#cy9oZlAed%yY!GURApulZ$;{8=%3hMaGtMDu>vd{w|)pSgbXI_3Hbe|_54 zwr(g~Mb{UWR{VTPa{GS#Z_dZJOEeynGC5VgO(DHmTGQrf4VyPglhbKw>Baurv}xm{ zq!umG8#R>kB_)k4HK$9@uHN_Ccvo!8XYsr}rVN}DS+4g!p^jBv{^TW}zS5^e*SM}_ zy6(|NQLJD^^;c^K)bSTq;+o&v`4*$dkwrQNc(%kPcyd%3Bm@w!iD$?KhWa@=rvy(i~+uXl6g_1@o;*W4=C zyk4tzpG&o(`&^3d-sgN=$*->LoNr$98uQvVu8~WeTfW-7{<*8=b)K8@-@cxy=Iv{L zVadGq7qiUU(xKbM7xL%IrF{0@E89bRuWU&>q;GAb+#VN`I=?BeAwPF+k~uz?J1@f= zf62}7ZI0b8CM3Lhx?c6=I{pG5GK9_3rmV0SdsCviC zC#H<)nU|5@{p~B2mcK2xQhuM1-&5rGZgaF-$*q=Ka4t!HTfcoYuE+T9<1=oIJVtU$ zy3S2%e=#9DH)EiA8%LV+$Xgi79yuU)xOMf&A-O%J*7oWil$}|)GrISXeM8~y()~`^ zBMP_N16|)A+3oV6ksU54IQ=r(^nCNm_K|O1*`jYx_1rb`_Q+c^xJQp3-Fs&A?Dl<@ zdEEL{Ykzrfr-nV{eyeKkGae@^De|bwwRVvErej83xviGDXXW;82~{7Nkh|8qzU$0= zJ2%PPgAFp0dLPaD&--y*;r-bCV*4R-AKohWXLP8BxgSgSXpm90`2A?^!@~R0ZoNnD zNBNy3zvX^3k95@xfA>A|81Io=(eZ@!`tjv!&m69^W7*PSE&C0svg{=*RJMJ4+n(G0 z4y*Z3gX7a%bv-+6;-kl#$9=pmUH)Xxo&EZY-Q7QT%((Q$)h}9%YJ1wY7S26U-)h~i zwG|({LTlN__zZ-C^ zGxd`iTZ^scIIC}*bugahCYeWJQm&lNdOGsoAI*RJHR>ggNME^!Lg^U|&ljq{OLNI_12YxS!c%$i7I=zPLDd>>t@uAh-zQG zO82*}>`Grb?sMPO!%1CVJ#}SSjUF|+*UYFHd3nqaHG0&PRZGuZTF-q<&RwmicmAq9 zs&=oIQBBXWSFY`$ai7V{fBKuHaypEW0A>g;JBKi>SMp>M?Y zS$lfWw_P&i%JuvI1^769fL^<>iBh&ozIk5#{su zl`C>Sk$1;VgMk*sam$BP?Jn|ortF!%O zk!LM4Uff{u}a}uMCI%rz^>aIe!CrI}`kypa|CihW<@^CTUEaS*KF(I~KO(0q`WMK(Sjm5D75T!mzoy)VD*iL_(jRWKR@#Aua^Kx+2cD3-Yn2^1B+C?Hyj7R%K)kG9?LaLNblDDUk=Op49SF+>uGoQHa>Is11qRA1 z+7%TzEjRg;6WA^{;@bc8#pG{ zdE5=umOJuGH_%3|`YShZz1)@)ZeXw6z^~oFD7lxuaRXE3wjA^azLj%+`4N_KAskiGereMzmia7%i{1!}`D{ za%COY2fmZLwe$MG%So2iWqlw{?vSqQ1M(9g*0t*c{p6nLyC-l|Ue<32t8+9g-BPO!X1SZMbF#1g3c~O^hCeT^lhB0RX&E!^(JyY^SdD)b(ZI%2~ z-k7Q8gd>;DGbiTB!=7(Wl#%lkm=oq*)HHMAZn+z$n-kOITIR|_TJn22^E`9ncDbJU z=EQcnBNmtwH&v4#r!gmL$m6=moLD4x|83^PmvUQfHz(edJAFl_oTw!y?lC7O$gN#z zPF#?;>|S%?l)T-m%!w}YDrRQOiE(n*-E2-oK24F22qn+RV`#qpy<|l}U_M5ajF;DL z{t~lfN%Jn$oH#3Yqiar#7dG<47gous@<{m2iAque=EP(2x=NZ8JLG{VWll7ZYYv(d zyX8F5=0p{_ujRYnt&)@EolvYf@q^soapuIka^{dZF;>nKHYdi(!y9i-ye9Wpf;rJ# zN@;Uqw>-#Y%!y0#y3DOESzjIk`O=bAvZvhmD08BTybAMIuO&0(Pm#}@khf3X3ORAN zywVcp#8dKinRAtVOtjhN#5PeIWlsDdZ@amiRq9T;BHtw2*(h5+^zD_`6!a~V5$$tp zxyfS6{L8s+ZT*)SydTwc>*(};Qq!%g)B8b9x1LV#=QQ2=I=vs$bQ|dOeoE6#*6IC_ zrkkSE`x#9)Rj2nOnr@m-{RvGsUAO*#rrS`r{(Pp}NVooYrrTJz{&c3>M7REMrrT7v z{%oe(Ot=1MrrTV%{$!@xLbv{4rrT1t{#>TpO1J)4rrTP#{#2&hMz{V@rrTDx{!FIZ zPPhI@rrTb({zRtRLAU-urrS}s{ye7JNw@wurrTM!{xqiBMYsMirrTAwJpQphw}#V4 z9{;#~!pE%{`L_k)*2y1h_ga6l{J}RudboXrR76Nmy{HQ5rBj9U)~Q1J=u{znb*hkl zI#o!2ohoF2P8BjxrwSRQ6Cs0jBjh^W2pOUqAwzW|WSDM*4A+g25xNm_y>5iupc^5X zx)Cx`H$t*>BV?3rgkeTX|pZPVgH!M#vO*s_=;jnW`66A$dAgNWM-LQlL|XOw*}Crt4H8H|bO% zGjytunL1U-%{mcsi*AI>(v6VWx)E}#ZiLLyjgYyz5i(CVLgwp6$O7F6S*RN!i*zI8 zHr)uhT{l7&>qf{Ox)HKOH$v{zjgY0f5ptJqgxswgAQo{3>r^4@bgGc`I#tL6I#tMn zI#tL9oe0^e8zGx?BV@B~ggm4hAzO4KWUFq3JggfbkLX6oqq-6Dm~MnTt{Wjw=tjts zx)Jh}ZiGCo8zI|tBV@a7ggm1gAPEb~R&IU}Ef zxS#ut93$i__o#fH5D{`hFRDVm)~Q0i(WydC>Qo`$>Qo`$=~N-#>r^2>=u{!6bgGck zIuUY4H$u+pM#wqc2>DSrLVnVXke_uUi@Fi=i*AHm(v6T`btB}mZiM`% z8zEP8Bjk782>C-dLjKf^kgK{8@|SLe{H+@y|LFFF9C!YZ$3JeCd=lh-84(g%Xim#l z%?uqY>~np#TTwm;#hcG&Tw5<)MRvL+Kd7m@vh0TPB{lXnvKv`$fL%#;W6Lect|+^S z`~W|@g6yW28)TQ4-OO^M+2v$6x7-+ZqU;uy8_O;$J6&#I9HEQ}atlL*(k94F3=a!acc*{Udot%_3Fswj=EiqhGts3BVwHDaTvF#$zQ2q0Yz;HC~8YUQ9A;P+7nRJfqPkS-wFDG(BcLdQ;3=wYJGTjtP#5z>r8=r;seDz%?QZ*xFQcfp?LH!~B8vKOc~#Vx zt%~}wRZ)MoDjL96MFZKYXb@W!4Q8vN>)5Jj2pdI12`CyyK+$jlibfDnbUgt@HxN*i zNkGv^0*bN-C>ljTQ8ocZqX{U=A)sgs0Yzg8D9R6wN1~XaNC53kfJ%L_pDP1Qgv) zK+$3XitZqwXbAyDcM?#vlz^hU2q?OnfTCpt6fGy9Xaxa9_YhFDlHe(tYCG}r!7Oyq zJaNubMIFqz*Y+Dp)mB8&Yg}Fxz0OueyVic~F3a9yM@wsiHaZ*JAFMw%_p=yw8&{ve>}PXdar5>WIP0Y!fkQ1lN0 zMOKu4-i;!gfTAdZr|5+3d@DdgzX~PyYgP1-`THp+%5QubMgAz)t)+?rTwWEGWUHc5 zY*iFwtD*s3Ut`G?g6Naz#!o)x#g zD*8~qAno>w@*7`9QNJj6MLkv2pUbPF0c=$?kgbXau~pGvwko=gt%~FuJJ-o;_1UUu zC|eZ`W2>U!Y!rS*& zK+!k?ipCRAbRz*p69_1pNI=mf0*WRRP&9>rqNxN=QJ*O1MFA3eUA{5M?W>B;nh$Sz zQGVmgD4HJS9&MnCZsPK)Xa-vq&19>ho7t-97Pcyy#a2bL*{bMPwkn##Rz-8!D4It= z(R>1m77$Rhkbt5^1QgvyK+)|46fGv8=nevkmJm>MCjmuE2`IXYfTFtzC|X89(Q*Qc zRuE8h4*^9h2`IXkfTC3d6x~Pg6ct1{R|QCDz4@x+G*#5nyklA&i(bEJJZ6ly)I{`({5K#0i0Y%RdQ1mar=tJ~4VUlCaPL<|<{#Z~cSZS)FQaI8l$)Kdir(Pzs_0F&D%!(V zMSIz*=qTNRyQtD>`P zRdkN6ihg9PqMz8R=w~*H&J$2{fq)OY;G zmr<1JxJ{a?qBJhAiqhGts3BVwHDarx#%xv8gsqC2vQ<$twkm4QRz)q?C~8SSQ7Zz9 zS`$#zhJd2B1QfL+pr}0oMI8tz>PSFQCjyE(6HwHJfTFGh6kSU|Q8xmLG6*Q@PC!u) z0*ZPPP}GZnqTU1)^&xnQk{xH50134+?|xELQL-bWuj4nqjG}>#drM1IG>FTqqQPuc zbRAn24PmRIp=?z&jID}>vsKXuwko=wt%`17qbQSrqLBm?Wf4#`ih!bQ0*XcxP?SSJ z(HH`X#u8AJOF+>$0*b~HP;?^!MH2`pnn*y=Bm#;i6HqjTfTF1c6y*_6lutlW0l`z$ z-*GkykWiNVkdiw<6}2*7f}G~~jW45UrsKZRS{2>QOYjukT{* zfTEoQ6um@1(aQuBy+T0IE&_^PC7|dvf~RP`<1`Q;p)=-hV;@jO{pD|A-Pawz@nsb4 zaok=VRMB28uZrGctD?8rs^}fIDtec#iuSQp(R*xF^gde^?Psf^57;O=KtR!l1QZ=4 zpy(q4iVhJ_^f3WNhY2V;LO{_c1QZ=5py*QqijEOb^cev~pA%5@1p!6J2`KuKfTFJm zC^|tv(bohNeM3OeNrI>74adn7AfdJ9Tdm(zMWfB9{ogu%`PRdkN6ihg9PqMz8R=x4SnI?q-`7uc%kA{#}&5Kwf9fTCXsD7s8Q(QgD4T_K?8 zcLIw3AfV_^0*bB@Q1ll8MSl}e^bY|=mQO#6Ly=8DQ4|414gp0z0*YJ$ib@brIXJNNB71{-PgL(G2r9ASHc%swl)(MParoif5~$ z1hy(F%~nNa*s7>3TNNd;QB;nAqVfb3RUn|KA^}B}2q?OSfTGF-6jdRhD2afgsst2O zBcP}{0Yx zVymLoY!tO2pr|bYMePVEYEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?Q*Ah_Fjew#I0*bm5 zP}GBfqMig4^&+6CHvvU`2q@}HKv6#eiuw~gMQJ{#vj7PlGv9Zeu8R7ZF~H|HzKo*l zd~Qy6RWyXltD>Q7RWyvPiiWdQ(FnFGx}L3yZeXjTOtvZ-$yP;KY!rPaWfTGC+6ip$ZXet3kc?1;Y6Hrt@ zK+!Y;il!4#bQ8f-G|1;H5g?%v<_Yy+RrG*SG{fgNzKo(-KKF^9s%SQsS4Fq7RnZ)_ zDw@kyMf2FIXg*sNEnusng=|%{h^>llW25MH0*V$BP;>_YMN0@Mx|4vSr34h+ML^Nr z1QabJplCS(MJos>x`%+Gl>`*sOF+>o0*dYvTiL4UVYVuIgsqAm zWvimc*sADpwkmppjiM(BD0+&3qNfQc+D1Upb^?l?A)x440*am^py+u5ie4a~=tTmG zb`VgslYpX^2q=1)fTC9jDB49p(W?X$y+%OM>jV_-CZOmIf~RPM&neqS6t#~NI2%=w z`6oHtH+_EN%P4x==Qiu7ir(S!s_0#|D%!_ZMengy(fe#ww4betK47b&18i0FAzKw4 zWTWUK0*Ve1Q1meYMTZF}Izm9vCj=B7C7|e20*a0iQ1lrAMV}K;^aTM$#|bFNPaAPo!r4b8$~t&MNtG4IRq5>2qKv9t3DLU6jdgms0sl^Ndy#C zC7`Gp0Y%jbD5^m~QB4AhY7tOWn}DJ^1QgXJpr{@JMfC|NYCu3yG66*?1QewbP?SdS z6vevEDFG77FyELK=X#&%moeWyo9_CJFQcf5>y{j%ikfnHRn&~Fikh=kQ46*zYROhb zt=OulHCq+6VXLCHY*o~bjiUAh6m=k=s3QSIod_uEOh8c=0*bm4P;@N;McoJ}${?Vq zI{`&K2q@}FKv6FOih2`J)Q5ngz62EYBcP~10Yw7{C>lsW(IA4SsFCZW2$0Za1E;Yn z$}?X)8tnRwFQaIf>-HI@iiUG}RWyRFimqp?q8r$%D3h&GMYpq6(PFkLx`U0PB?J`RNkGw30*dY; zpy+M_ik1;jw48vV6$BLBLqO3=0*dY>plB5VMfVXjTH3Sr`C7|ej0*clVP_&+a zq6Y{ldXRvk4FpfoY}a{NfP`)`-*wbQND%#5BRnfz2RrCm3 z6+OyUMUSyn(c^4Y^aNWKJ;_!@Pq9_e(`*!NBcN#e|6}exprb0=zu)g+*qL-DKte~l zpg;&6r5I8m5|WTYvy2fUpfo88h`peQiXv9*z4zXG@4ffld)N2A_Wpe*6MUZkd(JxV zS?92p-nqV+J(Q%RwwIzOn5F1RW+{4#S&E)!mZE2vrRZ5^DSD1sik@edq8FG^ z^dbR8FA-4mG66-e5K#0g0Y$G7Q1m(hMQ;#L^d`B5wHHkC`u1^tJEL znMp1VHinbx3s0RT>Jqal4MLCNKv4w&MLQEvG=+eoN&Qk{ zKv6XTMKuHzO(USFmVlx<0*dMhC~6>}XgUE!GYBY}NeC56iCK#FVwR$L%qW^q zK+ysMiuNX;XdeQK77|djh=8KS1QabHplB%pMf(y^w2XkFB@XuC>Ljs3{lL1{7bWr_|<^ABDq zMTfJ!6dl1VMMpAA(NWA&w2oPdj%JpkW0<9AJ+l-Y%Pd73m{D{b0Y%3XP;>$TMH>ky zI+1{)lL#o_`sV3wj6nWg9@W+{4^8AY!UQ1mJRMXwQ1^g01WZxB%QCILln5m59t0Y&c+Q1mVV zMeh+%^gaPa9}rOVApu1n5m59o0Y#q>Q1mGQMV}E+^f>`VUl36AB_UMwcv^Ib0}?;M z-bZ^vijIi7;j6Tm`7%Y{rTNpAOVRgiFGW8vOVN+aQuGtE6#dLBMZYjh(XY%>^c%Aj z{mv{!e=wuyPXdbmBB1DR0*d}2pva5qupLDa0*YD@P!uJg$o)t}_>Mh_d;*Hn2q=mX zP?SzUQ3e4;nFJJN5m1y(Kv50>MY#kNwIQG=PC!u}Ayo8DT68}LB!0U4tF8TSrRW~} z700%*nE5hA1u_5Bl~UA!?WL$AvlMk=mZHwgQq+Z6in=mOQ8#8O>dq`h+b~N}4`vkg zB%r7l0Y$wDDC$E%QC|Xz`VmmHEdfRS2`CysK+$#t6m3sH(Le%<1`$v+n1G@}0*ZzZ zP*g-f(NF@4h7nLSoPeSc1Qd-Vgo@h7qIWtV@wN66QGP5u($BF+v{A8``7%X2#{9ST zm!h$3FGb^+rD!~}6ir~3qMewfsF+!bCNfJ=39}THGD}ezGm6RyD4Ik-(PRRODhMdr znSi1x1Qb;gP&Ac*qACK4stG8nA)sg)0Y$Y06x9(>R8K%r0|7c z{j0U%j$VrPVwR$L%u+O;S&9}gOVQrUDB6dBqJ;z$Eh3<3F#$zO2q;=gK+(Pg6fGm5 zXgL8zD+nlBNkGwl1QhL0K+!4!idGX)w1$A90|+QuOF+?q1QZ=aK+(Yj6dghc74062 zPIf@zZ`k{22`RdyhZ_!!#mtu}Ix^-jSSv+GvAqijHTNq7#@=w2^?K6A36fiGZR_1QeZ2K+$FbicTS*=u`rVP9vb`bOMUbAfV_> z0*bZ}P;?dnMQ0OGbPfSU=MqqK9sxz?6Hs&k0Yw)QP;?O?RCIVOdb|S?A7?KS9U(<^ z_S*Huv6%TXMVH6?YYvj4E7)F&u4I;?tC*$eYGx_AhFOZPWtO7rn5F1?W+}RXS&D9C zM$t_K6x~cf(JcfN-AX{wZ3GnEPC(He1Qgv#K+#IRQmq z5K#0b0YzUCQ1mqcMc)uYMNh?|oey=24sPe*JS|0Y?ML~)jm6BDDf%(y?|8Tr{lxZC z^fR**{lY9ozcNeFZ_HBkJF^u1!7N38GE324%u@6>Gm8EppvX(tGcgoJ2qd7ocy_lt_H#3U*5Kz>YfTDf`6m3gDQGWu81`trR9RWq#6HqjefTBSJ z6b&YzsE~l7Ap{f^5l}RgfTCdp6b&b!XaoU8BMB%PML^ML0*b~ELPZ_YqZd0M@qT?A zoQ~08lUbzvQCO7u)P%R#4JU{%u+OwS&B-SrKpryiprR!sGM1f zCNWFVWM&jq5Ky!;0Yy^?D5@l&Xet3kRRk1O6Hrt`K+!Y;ifRccsw1GNo`9kT0*a;+ zP&9*pqL~B~%_5*^HUUMu5Ky!$0Y$qJP_#QCR5Ug{`lSOB|0v(V87D=%*^o$&nJ-f` zC*99kFGX|NUW%HSrD!i^DVoPDMe~`ZXaTbn?aeGj`!GwCvGMNc_^y4$huZ^tUNGB0XllOwrNle%%HsI)?3~Xg#wO z9m_058_`cV3wkd%u;kBvlN}gjG|2h6rD^!(PjdQP9dP^R04`lBcSMX z0*cNcpy*5jinb6?bQS?cXA@9#4gp2y5>Rv=0Y&E%P;>zSMHdoKbP)kX7ZXr)2?0fy z5<*2srAJpeAo05H4$e9$8fJeb)@A82^JR*zO7~AcUW%?}dnvkxS&FV@mZIyJrRaKQ zDY}7Kif&|Txl)SWvtKKEIz48-Owse{{yQ6`=moZyq8FK^=p|+;dYM^@USXD^SDB^gHD)P# zomq0Yz^UQ1lJ~Meh<&^d134?-Nk;0RcrH5>WIJ0Yx7ZQ1l4_MV}H- z^cev~pA%5@1p!505>WIN0YzUEQ1lG}Mc)!o^c?|3-xESb&!$IPpXd~AvY)$tPKr9& z3)w%U$IO>0`X$}(yGe?EWqT?5jaiC*XO^Nrn5F1XW-0oMS&IH>Cv4Xkof8z4$jX~bfGEgm=QByrl@O%zt3hV z>c;j`)SX$1wqcf{9?VkIlUa&-F-uWzW-02!EJb~prKle>inb-7s6PQk0|+SEj)0== z2`Cy!K+zxqiUt!z8MLECPyV6Hv4Z0Y$qKP_!EXMY|JFlpvsJ4+4rB38A718PS&= zka)W7es+?g+3s`xo*6OoWs3I7@P9d7isrGs6wPOrq6N%Sv^TR9?ZYfZ3z?;85wjF6 zW|pEQ%u=+J8AbaNP_&GIqU8h>tstOiB>_eI5m2;00Y$3_C|XTG(Ha7Z4j`atEdfOb z5>Rvy0YwKBP;>|ZMTZhlbQl3ehZ9hA1OY`y5>Rv$AyhOsBii*0r|3sJENhaYpN!PH zjF|Z{MaO3N0*bZ}P;?dnMQ0OGbPfSU=MqqK9sxz?6Hs&k0Yw)QP;?Oi zMHdrLbO`}Pml9BP839F?6Hs&oAyjlsMs!aHBwl8}JhWbl#@l=PS7yY_mnph7!$16N zDY}mBrRaKQDY}7Kif&|=x=5z`iEJH zyi6UrOHqVbidr#CQIuJVS~H`_C!i>efT9=yMd<_-We`x5NkCB+0Y%va6y*?5luJNS z8v=^r1Qg{FP}G)yqILunwI`q`pMatQ0*X2iP}GrtqD}-9btZ(0e$9vucR=D7+6#@p zNzokpYiPP;#>|%~+9uO)xJZh6u)P%ZWR{{{%u>{wS&I5FOHp5DDeA{8McXn4NPMxu>7E%L>37O@!%mqo^JR)k zGyO9!k)krTm!fiJDVoGAMU$DOsDfFFc4n5MDa=w-$t*=vnWdw3w zS^|pd2q>y2ps0a>qUi(_%^;v?CILmW2q>COK+!G)6zxht(QX73?M^^Zf`Fnu2qlh^xwNoiuPuEDcXlwiWV|U z(IRFkTFfj(OPHl-DYF#q%Pd99n5AerGm2IaP_&YOqWuUc+Mj@;RRk2RCZK2y0YwK8 zP_&kSq5}yiI*5Rxg9#`)gn*($2`D;@fTF_*C^~|Gq9X|?I*Ndzbp#Y0O+e8xgiz7E z%xK!>PSJXM2V}k!O|stsS)Um*U#95zOn=)erRW5~NDFH>75m0nF0Yz63P;?~$MOP6}bTuJVv>`KE>43y%<~lgX zNl{;Wl5|aG%zT-m8#4VxS4+{2Y%fJOF-y_S%u;j zpy){gik>2%=xG9qo*|&`qjGp9x#BZ^K`|G9XXjAlJX3Tt< zqE|Eh8?Ke2*VtZ)UT2n~H<+d9O=c;2i&=`^W|pFNn5F1lW+{4)S&H6gM$rcZ6n#iQ z(MJRneM~^nCj=CINv{Y*g7F9a0*N(dFboEd%90f|3kzxMHp6b+8K;kV3~`7%X+W%|EeFGYW| zy%hb!EJa?Hj@+dv!YoCtn58JnEJdxErO0QNqBLeHiZP=ooq(bY0*W#TD9R$BD4T$y z90H1R2`FkqKvA54qC5hM+7eLIj)0=}1Qg{HP*gxbQ3nEwIucOSiGZTc1Qc~4pr|VW zMcoLYqCYaD-EVM;`u28k{*fTG<9DB7KX zq67g&dk|36NI=n^1Qg97plB`uMNI@0?L|P*JVL0bEGv4s0}?;a-iRvy0YwKBP;>|ZMTZhlbQl3ehZ9hA1OY`y5>Rv$0Y&Qw zC_0*eqGJdsT2DaHu>=%tAcTtc&We8PfW+^$->}|Cik^3$^N-7lnJ-gxVwRtGrxcyU z_ENNoS&B|(mZHtfQgjNl6rIW}MW-=K(do=mbOy5&oym-%Ed&&uML^Nn1QeY^K+(Ab z6rD#v(fI@vT|hw5g#;8`L_pES1QcCDK+&ZH6kSF@(d7gbT|q$6l>`)BML^Nj1QcCE zK+&}X6kSIM6`hb39qE9?@3AM;8>MKoJukXGD`vh-(al-@jJu`i7Pgn7TbZTkHfAZh zomqxMfVd>^Z)@x4-!!H5CKIG6HxRB0Y#4z zQ1lo9MUN9u^aKG#PZCh{6ahs~6HxRF0Y%ReQ1l!DMb8sZ^a24zFA`An5&=ao6GBBd zW<}RJAn`Bk*I{pxqMK~T^h#FDe3_y*vi!5|m7+JV8RfTH#U6y+08R6syc2Lg&Z5>V8M zfTGR>6m=n>s4D?Q-3Tb^PC(H%1Qhikgo^&oil#r{6m_-Ni~flXP(MSS{MiEdnnt-A)1QhK+K+%o_6pbaIXdD4W;|VC5KtRz>1QZn$P&AQ% zq7nj%N(m?`BZP{2XGg0XkoYn7H_!CR4v+MAx3^}?vt#DV6z!btFL^|Yrm(#fRWeJ_ zRAwovVwR$6W+|#+mZE9QQdG+wyAV*c zD*;8j5m2-{0YwP{iuNF&sF8r8Jqak9LqO470*aalDB6pFqIm=q%_pE}0RcsO6GBCk zv!f?FAo0ca5>bT|`F7a9Pj<|FnW81x{!Ncb(NeaTqJ5dAXc@BnE5hA zw`KdqPfOA5Y%fK3FiX*$%u;k0vlQLUEJgP)OVPc|Qgk1)6y47(MGr8e=s^OC9wMOV zVFHRCA)x3{0*W3Zpy+V|ik={#=t%;Ko+6;=X#$F#A)x440*am^py+u5ie4a~=tTmG zULv6AWde#`A)x400*YQEgo*Rx~h%M`tx?XP=Qir!&+ zDSDS#ir!^z5m59w0YzUBQ1m4MMPCt6 z^fduR-w;srEdfQ}5m59!0YyI$Q1l}KML!Wx^fLiPzYtLLD*;8n5m59y0Y!fhQ1mAO zMSl@c^fw_?^k#PSN(UsKX|FoIB}MDnx#6GenE5hA(H#FN_j-2Qi9sC48G1~O@Zs?N}Ghe2te~#boB`F%f_SzS1$1FwLGfUAxW+@uPEJcHv zrKpfuiiR*tQ4zBg4P{2rFanB(6HqjQfTEEE6pbRFXfy#uV+bhPfqCN2o?3qiH>$a;%C~y{kBr{ zjw!0hiJ31`G&RSc^@C93zgBe9L z2`HLHK+$XhigqEOXjcM?b|au@cLItM1QhK-Kv5$BMSBuZG>3qqxdaq75m2-j0Y&o& zD4I_|(ET{=5GtCI6FtZQiQi&BcU>t(>GmXPaZb#9nWAMm{yDEn z(Q>wzq7}?iw31nh_G6Z!{h6g`6|)qrW|pEg%u;j!vlOjmM$v%;6dgoB(ZK{19YR3S zp#&5iMnKWw1QZ=XK+%x|6dgrC(K-T(jwYb!7y^pc6Hs(40Yw`KC_0XSqT>lDI)Q+q zjRX{(NI=m^giz7aoaloNNPMmBe)g53skv_0loK;wrs&ih|D!jg=rp#MqSKkB=nQ5l zI+Iz7wlGW4SqN@lfx|)EZYX~U1mVlz`2q?OqfT9}+D7uk=qMHaPx|x8YTL__| z%{kG`H=Uy2Y+rPW6#4c-_N_TF^JR+e%<;E>TZ-;tdnvk`S&HsqmZE!^rRY9pDY~Co ziXLE=q6e9!=pkk)dYBnSj}TDwC;>%}5m59v0Yy&`Q1m1LMNbh>^fUoQ&k#`bECEH& z5m59z0YxtmQ1l`JMK2Lh^fCcOuMkl5Dgi~W5m59x0Yz^RQ1m7tRCIezw8jC6f7rpn zxkHLRH$`vd#LSl|dN0S{_gyJ^pY5gS17<1ukXed8VwR$hnWg9xW-0oVS&BYmmZHy@ zrRWQ06n#lR(N_c%eN8~oHv|-YOF+?g1QdNwK+z8b6#Ym*(N6>v{Y*g7F9a0*N|%~O3U?cd0&cRY%fLW%uJ^@7q1Qc~3pr|7OMV$yJ>P$dU7Xpg95>V8QfTHdM6m3I5Q4a!&dJ<67 zi-4lu1Qhilpr|haMg0h&qSm?5Hyx1p2K&J@KQ}zm-_8E2&~0;L=F1dqpX>kip%e{d zdnp>kEJcHvrKpfuiiR*tQ4zBg4P}<1Va!rAoLP!SFr#QB0Y#$-C>l*b(HH`Xb|9c= zM*@n*5>PabfTHmP6ipzYXeR=SiU}y1NI+2u0Y#+*6qONBR8BzABm#;i6Hrt^K+(ch^W;3H`7XpfQC7@_G0*ZDgpeR8=(H;a8H4;#?Cjmus2q>CM zKv5F`MSBrYG>?Fy`2-X#AfRY(0*dw_plBfhMT-b1T1-IE5(0{r5<*2)xzYI!NIYsk zQdBKPJ?tHjeRE^x%M`85^^f^XiuPlBDcYY|idHd8(Q0NXTEi?w2QW*~T4pIakXecj zVwR$VnNf5I0Y!%rP;?jpMTZkmbOZrKM-otU6ahu+2q-$5fTCjvC|XZI(Xj*+Z6KiN zI0A}}C!pvA0*W>gP;?>zMJEwZw26SClL;u=Ob8V%&y8N~fW$l6gV+iw8frf=drEH1 ze3_y%a{Xt%kfJl$UW&FbOVL@(Qgk-66rIB?Mdvb0(Rs{LbUw2bUBE0w7c!&hA_9so zCZOmN0*Wprpy)CJiY_Oh=n4Xgt|Xx7DguhGCZOmV0*bCBpy)aRimoT1=mr9cZX}@S zCIX6XCZOmR0*Y=Wpy)ONif$)_icZUo{^)?jf485zK3$4RTe;zm+?e??Mfc?T`Cm)X zy=*T<_c2S+{mfGI0J9W5$Sg$UWz_umZDFX zrRY;;Df*0AiauwSqA!@G=u2iP`ifbKzGgv z{Y*g7F9a0*NV8d z5Gr~Q8u#_qbs?arD*;8_2q@}K zK+!e?6!jpWs3!qMy$C4kO+Zl}0*d+)P}GlrqHPH%>Q6w?079rJ)+YL}0}_AOUT92j z6CUYrvVU@KyEZZNWr_y3@jv-diVE3YiiR*tQ4zBg4P}<1Va!rAoLP!SFiX)$W+@uQ zEJdT4Q8b2tq8$h*+L3^wu>=&2BcNzJ0YwuCDB6jDqGAGyCK6CoLO@X|0Yzm56qOTD zG>L$s$pjQt5Ky!;0Yy^?D5@l&Xet3kRfJH{z&6qBpPZsmrf859mD#iF>NYX+Ws2(B z_=A3tqI$NMq6TIun$9dmGnl1lCbJaHVwR%W%u=)qvlQ*hEJeF9qiA;miV_4A?Lk0M zBLPKw5>PaUfTFns6g3f0v=;$I^9U%KPe9QE0*dw~plBZgiWU-3w1|MB#RL>BA)sg} z0Y&=~P_&GIqUD58(X=+vS_dS4lKo&>trR_GidM9VnJ-hcs*S(=Hz``p_ENNlS&9x| zmZG)HQgk4*6dlAYMF%rW(IL!IbSSeF9mb5J!wD!lf`FnU2`D;>fTDE-6dg@K(J=%R zttX)9SOSVR5Kwd+0Y%3XP;>$TMH>kyI+1{)lL#o_cO5m0nB0Y%pkP;@N;Mb{Bf zbUgt@HxN*CBLPJ>5m0n90Y$eEP;@H+MYj=9bUOh>cMwo?Cjmuw5kf_0wu!#&fW(Ko z(cdCPf7!#^-ECs#%M{(;#{cIpDSCkIrRYIsDSC)miXLW`qDPpe=uu`VdW>0$9%q)K zCzz$^NoEv1ML^Nh1Qb0(K+&@V6g@{k(enfpy+A(H{g9{YgO4Uj!8WO+e8<1QfY{ zP3lZ{Bejm8C_+F{D*}q51QfLjQJd)A4oLhN`*&kMmZG@5sg@p( znJ-h69rurIB}F-GFGab`Qq+c7isH;tl*cSZZJDL09kUd*XO^OTW+^IQMo|X>iaHWd z)QNzi&IA;7A)u%$0Y%*iDC$l?(KZAW^&p_ACjmvh2q@}JKv5q8iuw{z)Q^CoZ3!sq zPe9QC0*baHplEvniUtxwMVayFwGK#p7kes{6%UW}pEpH=;xY4Oii+a?bFHOlDBDZX zFlH$l&MZYEn5AeWvlNYDmZH(jQZ$BHigsX@q8*u0G?sv(aRd~NC!lBo0Yy6zP*hAn z(L@4@N(d+_C7`H`fTD5&iY5_IG?{>+3Id9DCZK2v0Y#Mr6ip?dsEUB1Y66OC2q>CH z2o)8^qdz+!@ul`Y+7Kz4YVXF@#$)Eo6itu&9b!^6gYBhgCbJaHVwR%W%u=)qvlQ*h zEJeF9OVRGkQj}npqCJ>V)JQT1i0BeuPj_eLOnW0g0b!KQY@N zMLBlZzkfVtzD&^paeucADO$_+Qgk4*6dlAYMF%rW(IL!IbSSeF9mXt0hcipj5zJC_ zBr}SRBA{p;0Yyg>P;?9dMe7MDI+lQ<4FnV&M?lf>1QeY>K+#45icTb;=p+J)HW5&C zG66-K2`D;+fTB|gC_0URqSFZ|I)i|sGYO%h)$!V>j)^io`9ko2q?OdfTEiSD7u+|qFV?kx|M*U+XyJSoq(b{2q?Of zfTFtyD7u?~qI(D^x|a|tIy)YH)B%ZC+uQi(NYRn@3nBN#W9G{gJrwsp%aNjo*jV_NK|s-)1QfkRK+)R-6um=0(Ypi`y+=UN`veqyKtR!l z1QdNl2o*gLkLKn&Me(?U^Pm(RYwyN>9FLhVQ}lV!yI5Kxp!2o-%AkJdXN z@xk`f`=3eC**R{=%8QvVQ`9EUU)ffQ;%qNPdCXGOmRXA0F-uWNmZAb?DeAy1 zMID)?s1q}aIulUTg@B^21Qc~6pr|_mMcWWi)PsPco&*&2BA}=@0Y!ZXDC$clsW(I5hf1`|+JNC*|>(eOO~j`mVCg6*YfB(oHaVwR%O%u+OlS&DXGmZBY*rD!a(6pdq+qVdcqnm|C& zP6QMc6HqjffT9utib@G6DkGq%oPeT91Qbmsps0d?qMZpSnnFNPB>_cK2`H)}ps1RF zq8b8(X2c_(m{%5v%M7U z!YoC*GE32J%u=*FvlJzmrDzXkDQaYvqCJ_VXbv-q<`PiUL_pDA1Qg99plCh;MGFWh z+M9r)eF!L8NI=md0*V$BP_%@AqNM~B?Mpz>G6IU06Hv5*fTEQI6zxYq(f$M!ts z(Gkp2bR@GB9mOm~>zJkJXl4{0LqO4b0*a0$plAaDMaL0PbUXn?ClFAyk$|ET2`D;= zfTB$V6rD^!(PjdQP9dP^R04`lBcSMX0*cNcpy*5jinb6?bQS?cXA?q2YxAND9gz4h z_V*VZC`Dh|a86##e3_yP^8DkvNYRCCFGUwIOVP#5QgjKk6kW^(UZc00BkY5m2-}0Yw7|C>lgS(O?3K3JEA0LO@Xw0YyUzp`v)( z=n)P`e2X2H<+Tlu^v`y9{9$cl=F1d~YU^LrM~X(Xy%ddMmZBY)rD#WHDH_WxMdO&I zXgsqNO<ESA2`DNdps199qA~)C$_Xf%L_pDG0*WdKDB78TqA3IvRT5A% zm4Kou0*a~$D5@c#Xc_@UwFDH^5l~c5Kv4q$Mbil=nn4H^jc6Nv+yRMyVsD*|l%gwx z1Gcs?^JR*5ZR>y0Pl|S9dnwwTS&92J=<}yoB6SEZU#f+kP z1Qg9DplAUBMSBxav=0GA3kfJ%L_pDE0*aOpP_&eQqJ0S{T1G(8asrB05Ky#|fTH~f zDB7QZqE!SGttOyo4FN?55Ky$15GtD8HX7g7DSFs`?s^v~denZa@xZn*^JR(-ZR-~e zkfOubUWyK9mZBq=rRYdzDLRT-iqfTFVr zC_0CLqH_r-I*$-4I=F3gx&sow(2f2fQq;;wo!>TQzP$EcE5CQfc>^O}{vh|P+sm(Z ze;sY>{C(ZKBxW}-^Kl%kR9_I-8pp4zr_6jWsm%?+_S7c z`NP~V-}cX6-P7|1=HKJqZW)sA_w&5r`BVCP-st=jxAVNQ`L7K0yq)s96?$H2{+uGu zo1A~yFwd*Z|7L{e)#Q&D?RoY22khW^GxP5o>v_B8$0m5*9{E#?J#TLQrV`JapZ{8! z=Pk_NX0qok&2QS-^H$_vQR#WB^1rL{ytVnGrg`2W`3Kf{-Vyl^GyDYKFvSUH_4Saa-(1WD5>I+uZ_@g2&EvH$kMJ%?0i@h!iwj1@^Dm_lXqPKS$m_Qegj{^uS1g{e!?mA_ev@x(<&N z*gwfRI#OW&rsCL0f&HU+J4Fi4y4T$xkplZ?sU}AX?B5ltj1<^E3{w*+uz%U3K2l)+ zG{ekDf&Jb3yG9D^FGt@aQec0(_1s8-{q@B2BL(*N%Px!**k2I3G*V!H!{drbf&CSI zt0D#VcdV_A6xd&qbx5SZ{+6R7A_ex>)Epftu)k+yL!`j|qKJ)=0{cz>lOqN8tJwiNP!)Hei{VN{M$zyH@W0>-1w6 z*GA-?;6A^`&3n85I-i*9+Q^`Jolmo2l!lw_Tu0|RyY6IXyYC`0MxV*Xw>1|zcTP(Wtt$+g$SHIbXYr;V#!tm0*KKkTN!MQy1;9+0db&{6%$gP)raiG^F*V&rj&SnbREbMpt^x!+( z?(U7Ff(twPiEqaRUwGlzTih0d-4=FX4`hprmcF!;ZIQSB)khZuTWp;5No}yj9fxJj z_qvSL*SJ31A}#Ot&DTE|-dg8xJn46L?YZyow?i*FCH(%bSm$=7U3S+-pYUb2tUb6Q zxK6JB=l-&uD)zB;&Imyf<} zR&e_7et+rA13j<1-^1PQ+<$4UqG{dRxex5Ww5S`NbB}2DUs~U2X7^v5c>6D{bu`V3 zDVYkhNphn5>F+Zf~s5*lU|3JS%Cf zBhlRPSy}GW;mIN{#`?Rhy1IwY^xy;E^D=@D+C=5xr& z@uKN`-K?yftn94O?)-8)v^Z58cdC?27uTrs&eK`C(JoY5on`RZ=Cf?4v(%~DyN&$j z%aNbszDxVc1;GdIJLxbuGNBV+b=yuA?eZdR({}23>cmd=MLPN^m#9^TTPC`zv(xZ@ zx6Y}}uBk4^92RjmMNvCDm#*s%i+HU%o;cC%8M^Tacl!?ZCUhFxX>o4w<=qAL{{6@8 zDcvJLjV)E~z8mqT+tSNPYVG|HsX50!8sh$QpRlDi`3d_d*fo38|9!6E{yE}Jv)%NA z!Izj}3!6_nr+M=k|7mk;ara-utF`53ci)b94YqL6YEv#+L+VAVO*!udJD-35Y3owN ztFxsx_;98zT)4X63>LcYFXGL##lB6uHtNoCr)u%XE=()$#Na~NsqAC^v}$EL@JR4~ z+PUt!ZRHI)$JX=Rf4;ZVaQ@1WviF2SYlyL)7+KInwF=0&Q9-6J*IH! zvIUD4tXQyLlUF!@$)cvh#)VC*3I{J-GN*B2;qv*7%bE(8H7#yh-nhK5X=q~kij{L0 zEGb;EWXZxg^BWf|US2qF&YVQ!vPFeOLlVOhLx&74N)!#TILO68i&VhS#Xtv*GSE>C40N;e0gEr(#B=`l&@TzsCVDXyqbk8mnUkAM@}8V&E&q> z{}<2w{|SQq8do&gZQ*%h)Hr;v!E;PmVs6u3jVl+fNUT`Bv}yU^`G(g?n7d%{3OBfW zzw?)vvt-etC5sb{OBcB2FxQooCET?#rzGgExxFqv7ueSdljld=Up{N{qr)P;-|oNt z@gr%`d6B`sAMG^Ok3{G7u#bAUKWT-2+cdXj+7!QCu#WS)yEVOspOF^L8S8g&Lq^&- zzaUu0d#zeW^4;IQ?UpuvUt3%c#=-7nL;V46EGQ}*SXAhDh_10#=r-*bd>GB>;TJ^r zw{tE`>+C*U6@J*seYiUOu%r8MP4J<bXVw^5%q2J4Gkln-22`+vYH{`gB z-#J*v2bV7=xY)h@cHwt1K;K0$4tA#=>TmB(-MR0eUIPjX{VvksoGvepFGmWbC({r#t zu$SMnyE~u%zns2%Prv6NcX@icZ?xTz{{!Er-N*CXEmRSlY0mHfXy=}OmqE@kcNYo# z@As2#?p!*LbC;)oZ@)`$pV;~ypjp?W&Z)n<`E0)tjCP+IY9}kS8_=DR?q@y!%UN-s z`oD0N?YkEa8RB;@c1Am!(f@D{{jXo7n|QVNZFgZtyW84J=-gEoWDqvbwmUJS-E4I` zpYUX9{laUw&>zst?~=N+XjSfBbF(}8f4`cywX3i;+iK4e8R*!AqL%HZM3uB>QxcS_qc_jgxlcNbcMZ^^XPj_!$Ld0kDSthP2$Q8m4|vZ6Fm zTsx^@YFSmi$0w$i)zuYGDofN?S0^f~t0sB1Ws?#`#U+!IrzokfYjE3_R8Os`EUR~? zY^bWx>B>tcC-!VUVR3C~qN=*yow%;7w!W-1`I((-+?h61)iu=ARNE&KH5D_{Phs^!TiR#ulxNt71X7bmJ3rcNxYweO?4HazvP(Wzg!syb2EFtM(rw!%(U zUfobt8k}s@=*hu4rp3jqEvu`kc9$?br{V52To-oP%W8}3QZ6~y+tj*AiHQy6w=dO<6y5)FLeF}iR?WZrR zGJVTKb^2nrx+h}8h9*`7-$7}M%_mm6XJNJF!Oc)sRqV!6ue!W0QCu3H&4}RCcFD?9 zzVWj9$y~pQn#r>g?zW!lZsn5V`iknR@Om1P+_0!5Wy^}%X^Dx>SZPIF_{F#`!?UzA z3vRYVWkuDLifb$CXC+5NJ+-)MmTtP{vj}dsy6U>%5|ldC$qO(d`1*VoI$e2@yMH9= zs>{n0ElylCrp2jCimMX!wZ&C+Q!DC&bFM8bE}a#8GZR~Yt*t9|XB6Dj?g|!czGih@ zNusX4+Fhq*j-zhF@VaSnCMox)ixp$V9O|Ni=9TOYs z!fV;xH&XXU;a$lvyDQo5+;)AWY+gIl-K7)N)5~hhE30R0{Y7i5CM9>9&Qi2nNbV$uCaWY^4Aufj7Cr_=ewcEyan&BOK zXmD>?xMcCX9&Qg7wBhb+1>by;`+#lT6KTBSo$?idKMzQ-w z>no;~xtlCFkI~7Syd>od*0>w2uC~OXDlVz7m>xa=jZAsm;~wfBsV7whkJ7ix-G zRqT5!tLt=+9-aJx?q&$D!HIlO7Tn;=7tCASG`EL){b*V8%Ng$Ka(8wPN%Q`?d4Et+ zQk|IW_EX6XxNfFamxh<#Jq1X9vZSoCvZ1oL)`_1~QRi^m;}+its@MU9mvM;OJopw{ z?7N5(rD+unw z!PS$zXB3TSaYo#IxV2Iq+*`nD@zC~v^3_mYOl=Ha1><5gi>xfI4))i{$0+FuZ)~^w z5|W}KJr=s>2FaU-y~vP6>9qPp>E!U~LCfb7BU4VVJ>XQgk87w69`%B~Y`MFt>n5k{ z?73G|7SFP0rdvInhc`lPSxK4O+ay^u?|bZ`rrws^i?+Hgah38MyVBjunq_e*CKXSe zTAaKTcKx`ga9k~JUl3eX&HIa@qQKpxs)imVW5)EbSBwW2^|05Bhm0ONyhs0KO$(bE zmp2XQF=)}8r7OqHS+Zh7EIJ#r&0v_H^rB3zsym8021X9_RKhb1k@2?zMEk z5rdX59W=LSq$`cf=FA`GUV+|k^q@t97rEE4x1YOw>Gpdq?J;Oxk3rQ#dkk`~Y>u1b zF2JC@7Bwwj-Z-ym(88w0^H$6sH^imz-aE()x@oVKi|4FZuw?O|Wu6vwJ z&cU}hs)g*}whte+?64rXABbI$>bCstHe%x-=XKE&+LM9g3AojQ1Fhy8)7@K3+*6B*#qQ`!yJ!2F?!Y0u zxTBh-yQd6cYk8Do#~}8Mqrx3zgwIXF?=!%*pmNEQrA1z_4E@(-Y4K3s;_38McTN+l zXZ~x8l1leT;vSoAPZwM_;odr75C3*+6%84x%bnbfyDL0-HqFXU8?Z8 zZIL^Q4K`_c>}!u$%}?Uo5wGrVb_5?>?d}65JH!r>dlDXe5FU93X-M)^;YZ2+U-Ofx z;5o26RML|Lo?hMJ3hu?KWRq=FZ-HxV{pGmn=iyPdrx_c6r zdTee_ytwK@Ig{LRPWUV+`H6t5J=3kOvYkQj&|dUEepYuJci<;L&BuE!597>W5;_;8 zuBIZP!*RPkID9Nlo}1gtbH?_hNngV~AJ#`j?rsvCO?d z!Iun(*aa~r748Y`Y=s>QwZB;F92~;xgD}+vc8V?>gl(5)JMJ zF?YS{40V3)Wc6g@?+%@W0M>k(X_FSm1xm-t#d{Z2le=KwZ5 z-r`!&wcGMe%FPyBAMWW-czw8|x|Hj~9_#GTCQ&z|qTYQb<$;sKzoO|7jW=Iq_KI)tvWz_&aW6$A zCKXqNuLC-h$&+zyxucAR%H}5?c30rJOX^eARToEKbqcF4zt zw7Y5X#1LEfN;IG0J1loca_*ovQC?YG*SsB{ZKyHo_G$tzvTt?3mAq|A%1fGWmm+(u zo3EtTNW#a@;Fb?xsJ9POU+)f%2)Ej&G(VdxE&DIeC+!BFRTdr{b6D7NXJDE+?BI!8 za5?P7>)?a%CHbkvGZQ6M_3nWtc)nKLw0!7@ktK5$l{N)G$x^;xapS_em3lci^#$wT zlK=ZrH9QLAYDm7Y7ktI$SH6qf>u{-ez2>Jlc3p&bnie~&&5|m1FX-T33DW zqIB?O+4(m=?1ir|+b8XaFF29C+{&d69;Y1*$GXJb3;*-`AK}Z%%@1P#+AS4vtWabx z&2rwU7rDHm(mj_;eZism*-TwsiQWimaXnxgtM27gJ;_)SKC2Iwq2YsTi;KhsNbc5? zS6Ir9&W;c{AzvcAA0!`hgKI1GWz+z|e|pFc_u9#q+Bo0f?HzUsM7vpQ8^Rr&?Vst| zo4ebzo#%i+5x6Z8lU*sj8k4UJD%h*vt8LzTt5N*ULor z;sojzYLxpl^3Tz)nE%wYL_JCsKPzg z>DmqV`1a}W=|5kxCVWoqUSmsMFM$)cKk)QCsrelchnE{Gd9$SoYuD%<+;tgTaV?+ZH=l)j)05|2Tv!gX>Kf|Y`&c^6{nx9E_5$Np?^T44uHma8L-bf1 zPR$2^?mct84Q3b5j!%+@O?-WOR1Y4H{?j3w7G6FIXk7U#^SrCCii_ z0SFHef-5KWS!QrhH^aTHYj12<>z!IIQur#oy{)(PKHVOx?2T~tLA;U5mJ=(BtERYn zZkcS}&H(_Se|o;3NAvK_`vsVw^!tg zmo4g1wrJ0$xpUoHclG@Eckm)TKh{0qzrSQ}Ki_M=bnuV+<9;V%ZEkjs*TqmuH+{ZekqWWRBc?|z#$ z_%(yzcP-kw?{`?rDeN~uinp4px0?6dYUU@v8-q91`mFH!%>CaU>!rMOzx9LFe|YmV z^|5VeaQQRy-LGQ0%VF!UT5okXwat^=PoBHqW%Bm2)%}vs*Y38mp6PCyO!sR$+u7twbh+Puy(T5A?azWyE*!+n`1lONUh_vPSjeXwL$9~ zt?rl5g6;Ozda%|bv~JXTp4J<*-lp{)t?rj%gY$Vp>vLLP(fXFw545^pY7I{Rjn<#E zx?friy8S+ieLwcMs@v**DK%KzX|=yS%lbB2`)b`@YmwGbTE}TE(ORLkT5E&WU9>i8 zou_q?*5z7PYdu)&ky?+{dZN}-wVtK*0v<}faO6z#7Wm@f*Iqm%Fw9eMrsCB;9C0h5> zdZ5-Lv>vPVB(0}wJy+``TCdi6lh!-6KA`n+tpt;@8o)_RE6by|@TMtruv$ zTt|ZO)%uIpzqR^qKV{cbw$^r9J8SK!wZGOvts}LL z(^{%^idOrrHap*0TKCX8PwQf>E48lGdbrm0T2It^n$~l)Uaa*htv71DL+kxoAJh7* z)>pK?t@R_VUuyk9>+f14?w6A6`$*T?Mr(oAZd&_j9i(-n)(KiCYn`Tbw$?dX7iwLp z^&qY5v~JXTy4LfxUZM3yt#@gCSnD%dU)B1a*3Y&6p!H9!zI(v3?>AR#2dzD{4$wMO z>yBDWwc78++xFA7CbZ7iy06wXS`XK{LF;C%XKTGg>$O^M(|W(wC$zq(^)0O*YyC#+ zuUg%|#1>q>Os(y;_SQPeJ%zH%U!rxEd+fHkN$UabDU{9Yw4UW2vu(ai>pkuP-sUH? zzUQ7o+5DB(e(t$~&BL@Vbk8AdUaj?d_m>RVe2>;&-LHb$?0(rISjTS@u2Zxg(KDP+ z)cSbuaDGK=yk9tX(>mQf!Lak2qjk%6;e46a_XmdaH(L9pP7O*Qr{M+98}bX?=2RIKQT~?SydNM(fPtaBk9ic1bv2q4mSE zaQ;r~c9X+-l-8v?hx372Z>|jI2ekfK70wye;W}|zxK?XDx-OhIYkk^1;j-`R4Xy2G zhI3D?vuB6%Jgw*M8qQZ~{do6q{z2=&#&8~^b=jP7K3MCmP2v2I*1zY4v-=wgg3D35 zceqZ|x_)6epQ`oQ#o_#x)`ES*xwqC`mxuELt>>={=WDcnx_>zTq;>F`aNbetinZZ< zsMgyL3g<_(dWVK{j@I(S!?{lDh9krIbgj>?3+H#Vc3dCMeYNhsA)NQodg1?K>`vfp zssq1|&z*D6oHIMuG6>nS?}S8lVaQ(A>{%-NPWB}dN_L?vB@!W7QnpG-WM7gfyF%8K zp5JfI_tUHY^E|KD^LV{-?)Niu?%cWaX6DX}X=Uep2uo{;`u*d4S zb#}1#=omdO*vUH9SrF{zI!;{}?D;w#S{&@3b$v>AV6W5h>WX0B z*Rk}fU{}#`@akZX*KymLV1KJ)cwMm5>sW6?u%FX$`o>_tt>Y2%fxh*7PRHz9gI!3+ zj@yFWOUL)W2=)dYf7=o42RfGB9qej44*e?F6LtJzPq4q!F=lVDGw4`G;C+VE5B;)y-gU((&f4VE?0Ig}cG7 zrQ?YE!G2B0UFHFneS03zG45foQ*>-(K4)Q{-d4w1(ZOD#<06phnK(o7q zj@@E|JwV6R=7$Q|r*F~mmU$p&cPJ@1R!kQhpVo1d`FTV3>96bfrTM`_b|2I+!Tbaw zyR+)p#5@qRyPb}6%+DmUdzp@>%?~HC`-+bFas|7Tjy>`OdytN6@&)@d9q*VQU}VpC z3IxYWg@R*U9p5!S7tB8WBON!}qZ<{qNBfXHCYT?2rQ?t47qzeIctia!?WkhGd9FR0 z>rbbhQOB(6`Lqk_SWLZwb|oFFsXwD*YaP4kI6%iSI!@DZfsQM5{6xo{I_|ee^ZL5x zlVkQ+UdI=8T%_Yc9nb5S&HTU{`~3BF9HHYn9WUyb)%*+|`}*h5F~5$5bu6P}c^#|j zSW`!H*QdQ4a}{aF6dfPYF^`Vs!=1FJm(;PWj!)`nKDAiI9 zr=xkdm)1w<_^OUmbbL?8l{$W`<0m?PrsH-Uzt!=39gpaELdRcpyr^T^=TYq2CluU{ z1Rc}qX#NfhIiUFcVpVItd92QXW6&gGde!2V=Eo)&(g9_AEDy} z9VhEJQ^&bFF4ggU9oOi%UdPXM+^OR}9e>dAgpQ|mG#|D{MaKm{RL0&8`^z59!?U#G z+34VCKMxt5-uz%5^{C?ghP>RrLq~J$-#0jR}Kzm%`;VN(x7;U{{8!Q?>L~px!V8VU-r+4xm*AJ zEVBJG@!wzOu1x!t+x%{y&k1JK|NeaTY4%qE^Pg}2`+q&3{WJK#zuf=+^cwrNw7-g) z|6~%bAt}oU6S>zW_vw!FP_xc){>$7hsd;5~je_Y>2 zbJ?C_J=kCGm`~mo≶_zuTwT|90re^L^hn6jjeOe(`+v?@W7{U)j5bqRhk0e}CDR zYk%3lWB+^mTKwnr&0wC!?K@>I8_T`TA?;T)bA1&V=E%#kNB*qXCr>xeH{C@0zR3PP zWUtTO@AhT#XTw~K%4Pihd*xQ8KfjkNS2k^xtYDs&D_8rtk+tgA4t^+9aHS#hl?JZY7JqEoa)UqX z1*5W>ze$T-y54YO{jqBf-P_tHVPVSkN4?ODs@GeNsdqEFMq=&hwRhbcS8`42u6ur; zUH5jCJajKyDyqnX6AiC-OIVee!BZ-!f=lFjXN%xx%D_4XoY=R`b%lQ7wTazcdEPN-qLg#+UM;yC-m2$hPS?G+P>bo4(;o|H$KOFrZ>hq{{nX4vdOUk7`6{DhFH9x&~YlAJl&u_^5O4FWO_Fh|A)_n1m=@7oUL^0mlnVO+T6PP#}~NQW?PRxE4CT1 zH8pGY?GIY#iR3w6Wc|`fi{B{Uui5Bg3rbCTdG^oFx0#-D;W5AH=E~Ctifg6W zqsF&C^jGJbi6$ z^Ome$=gza8jOviNXVdSxwpwv*xpl*QY&^ zTH3q~|L32<;{W~`Ed77|Ggv&ec)b#JOZ<;NH~bm&@)kDNceP~Ux`k7Vq`mY?=Nn!R zrSS3!q!y@Gux`P$r&P_G!94HQQZu@r3jcK|UqhZJZ))Cp`ReA=^VsKD(*2})j%yck zrRJ`eyKWvmC9JcLnWyD!IP*f_DeSvZ^_xC6dU)-@uZ>u@sQsU<-n(-qD)8cM8rOC0 zy?e87FrGtUMkQfJg)h!eFw)z8yu7B z7HoU1`zIX=E$cfmU56q)j=fp&K+dwW=F}N=AVa2|E4N0>^Q%j&|SAWDnkf+~yrnojm4pgDhzegu?Cw^8u2x zH)2x5tnJNJM2Ee{vzdeMp0&~UMrJkd=)$i3R}JQA$>xfjBj#O*Q#3<0^X$&#T;{iu z8Jn5Q?lkjTOse@vzzYvI7sIJZ_GbipU)cAd-XilJIOH8N?=PcGG$(lt&HK=>x8B@P z*E?w5f5v!s%w^BB4?TQuthpTPy=$I7&TC<=A>Ny1KITvGdgn4ikF(#JbduJ zHm_w?udTV~vUz<>f5fX|-mho(zBBh{PR~A^demEPo|?;BV_srzZ-@EBd>-$xxwgFC z3iF)#yn0FIN6mVB%(Zp)2AMmxi`O`x`PtcCin$GYybI-(K&e}?crf3vwaiiZ5P=4KTO`EQu#DjxDHnR~oM$p6vYvXbU$<}f|v|7p&8Bjgt_ zH)Tf1A7t*kw?h6(b9c=Q`Mb@U74nyxH}dR|zs6k4oRFW+ynwkOzrK0eypUhP+@$#- z-!-q*t&m^H9BzmF{6^57kpHH6>32hZdvkBy3;BPU^IAmv>C6k-8ttz$H~FID_ck}; zlH(7JH$Ual@#mQ9yyE!x%)09M$Ibn6&GFlsJL5OUpKR`p-yPpKuh@0Rcg#z;;rLn1 z%c~#uhnxGTLD(;EZuK)^e}sAKHw^nl&6PC@`(@3wG!FZF&C6>N_Ai@5)3Be%yo6?9 zKiQnnJnYvtMxPD)*UkOa;`o?9;u>YaCvQ}Z={5aRB)?vSed9$?%`x%X$ zHDTX=Z$?Jff6BZ@nOy&xxeDnOy=z{IK`i3?!h4`{#A4O&=miGc@qyy@u!*FIXuOG+q@31 zr1+Q2-v}d8{5$6KktzQ3=8hbd;*U2kVRVW=+T4h$3;fRJ#a3J3A2C-}eS!axxm#;4 z@MF!j)LP&tn>(cT0^fX=G3x0Beob>vG}`IsH&1K4)1P7P`SzFncIG8?xa`|UBpomN zU5trNm;Dmv4(V*3W^PiK%YJ$DI=pb%zhhor*UPbe%+q?O4@Je!F?##h3wO-*_O%y! znKyesd*Oh&h5hY?7{hRYy)f0>jRWn4vgUOkW!|K*hs-mNwili@*E7am=w<#ejS$}ORpV&)T3Zb{9|W|lHHtCV&oyUpz? zt)0?KZcrf_9SK=H@-2ooKhY zeHFD6%r0$i-;>($cAMK*NjuJNbNec5$J%Xf-&5MY-RAaH(e~^%x38*pjNRt;RnvCu zHn*?3cGzxn`)X*L?`o`G+T6aH+RwO*G|-fgXEY_Gp{9g1(v*86d4?%D|Hp^cCiwF4n_ozdp)pT42_8_ca22q|j* zZg*eutQ;$(w>#SKNfXjXr%Fg)O$q6zDIxteC1il6gbdV_kU^RfGFVeWhG?jtBsIx+6Wo1jgSf22$`sjkXN-4GD#aD zleH1@nl?hFXd~oxZG=qKM#wa6giO~Cg!FWln74oW!RA9Vw^tzKloj%ZXXRKSGunPXwGpyR8zIZJ5%QikLf+R#$O>(Qe4vexmD&hdrHzmewGpyf8zCQQBV>&>Le^>{ zC`E zA>V2vWUn?tzSBm?K5c}2uZ@uX+6XzIjgTL-5pqx)A&0aPa#$N7N3;=gR2w13v=MS# z8zCpO10kO}7tGr~{S@;-th*@?GR1tH>Ynth94q7}*ZzMN(}bMSsS@(Dri7f;l#p|p z67q|tg#4;0A?GzE+6cL-jgV{F2>DGLA-`)Q8DZG_y`M#vp)gxu9e$USX@+}B3PpV|m{ppB5fv=Q>RHbNe1Bjg|LK**0y zoWYSkr+HB1o=y`I$!{;4&!Sm6Q5nK+IAk7(m`7ap(Tp3?*^ioSKJ1NQ=QP`VSnjcN zm~B2R_u1LaHXoM9vL7+qd{`dG&Stjxusoif)ok-&c>+6&+2+IYM0SeV=EL$Nc4o8f zR>rl>IIOHmQF6cuGlQ8Bg@6=zFP3APlKWJ^&gwiK0S zOHmm%ipmmD^f&=Upr|4NMNbk?REdD1$^;ZWMLyeK+)3#6xAW1s4gK;R3PNo&%Hf?mMulkv8AX58$~S%C~8GO zQELK<+7M9GmVlz?2`FkuKv8=FiaHQb)RBOqP6QNnCZMPb0YxtmP}G%xqHY8fbtj;x z2LVMd5>WIK0YxtpP}GwUD5@WFP8lGPcILBnZUZT*Vm`!idxg@zwqq6b3%P%r&qbyw z>d*O7G=MEd1KCnEh%H5f*-|uwEk#4wQZ$S$MZ?)r^a>kABM2xONkGvk0*XcxP&9^s zqOk-NjU%9FJOM=$2q>CJK+&rN6ip(aXfgpsuMto*g@B^h2`HLMK+!Y;il!4#^acS% zZxT>6gAgd{6LRvHcV>~b_5QWS5;TOrT-vWn(}+#2TV5owC%a=sMJV@uI|wiGR3 zOVQhGDO$*uqD5>eTFjQBci2+&E*nKl2q;=gK+!S+ik1^l^d134?-Nk8f`FnA2q;=f zK+!4!iasQuXf**v9}!TrhJd2A1QdNtK+!q^iq;cQw1I%4PY5X5NI=o2gh0`(kkico ziOjbj7tNNUx2&Q~As zH(QFnWJ}RkY!rP>K+zroioPMB=vxAc_7YI^9RWrA2q^lVfTH~b6dfR-=m!Fd4iZpw zh=8KQ1QZ=1py((8MaKvzI!-{*2?B~v5>RxCfTAA>fub!TXSD$m>1yF@<>MmrWit14 z$g{qzqO&3Qd-L_JG)3n)Uy6QVOVO`vDLT)Vq6=&(y2zHIOKd5+%$A}nY$>|RM$t6_ zihd)Y=yw8&t`ksngMgx&1Qh*2K+!D%if$87bccYVy95;7BcSL$0Y!fjQ1pO+qQ3|z z`kR2FhXfS;LqJhf^uLetgU4tg0*ayufub`Z=avBydE9=o@MkF+ZofX|M0?hkRpdpx znet1K&-qdm%a)=zwiLy)r6_?dMTu-FN@7bsGqj}TCloq(bo1Qg{Ypy*KoigFQ9l$(H}JOmWwC7>uD0Y#4y z_`4`S0YwD}fg(5Bsc3*i%9t;RyD`zhBmL#(`wiTJ(Vq2X6%~zkTNjj~Vw^8U#o1C+ zf-OZQ*-})BEk&i-QdEX5MP=Di^f+6J%CS*Yo`9kX1Qb0%Kv6{kik>8(s1gB1l?f<% zih!aj1Qb;zpr{%FMb!x?szE?eO#+H)5l~c{fTE`fD5^t1QC$Lx>Jd}o!{Qc^qF3!#E*eC8)|XY(INE)uuoN}nd?{+mmZD~CDQeD^qG#Ds^c-7? zTCk<4C0mMGv8AXr8%1phC~8YU(enfpwIiUYJpn}>2q@}EKv5?GiaHZe)P;be7YHco zNG%1XfRufhOnh*C|in#v88A@TZ&#`OVJ3n6pds{ z(I_^GMiWpphJd261Qd-UplCb+MH2`pnn*y=s{|BHBA{q80Y$G7P&9>rqSpy1no2;? zGy;mI6HxR90Yz^TP&9*pqPGYrnn^&>EJC2Df3%ZO%qW^>KkGO^ii+94m}W?8_XsGuPe9S1 z1Qb0Wpy)3GivA{`=pg|`{}50V<>+BMib4bwMH5iu5Kt5*pvWZziq1tlrwx!uQS%iJ z_ZKPp&W;$zv%ajNILH0xaVd)Dd?`v`OHm?Qijvq;l+2c*bZjX~&z7PHTZ%HUr6?mC zMVSaF%1l5}3IRn~2q?-*Kv6aViXI`LC_4c~IS44qNkGw~1Qg{WpeQ#1MR^D)%1b~| zJ_3p!BcLch0YwD}C@M%mQ6U0~3KIfFzT@O8XB1txpCXENf=BuZ(Pk8JJnPFUD&e@b zDo9aD&X=N6Y$+hK)@&(i!PA3OcLIuf5K#0Y0YxtnQ1mhZMLh{9>P0|NZvu+?5Kz>YfTDf`6!j+rikdji8UrMf z!+u=UREnOopMo6Vc-EIyG{kWaRFa~hoG(Sg*itl{Ek&=erDz0Oibk@fXcSwDMzf`8 z3|orEvQadSfTHmP6ipzYXd(ecuM$u+iGZTX1QfkSK+zNeie4w6Xet3k(+DVj@~@KtRza1Qcx~py*QqiZ&5Yw3&dS zEd&&8C7|dt0*bZ~0!0fPr;-5@Sz*5#`?eIlW4;ROe(reImsPaWaobjtqFtOXMZ4Kj z^d(!0zG6$!*K8@;!&q%i47-B5Wzjz?PznY$?jbmZHpTDN13Z zC<_5aSqUi0MnKUc1QcZ_peP3cML7v5dX#{oTm%&5CZH$}0Y!NUD9T4b(PIP@2`DN=Kv7`=ii!|WRFr_CVuV0ZeAr2hK z)@&(i!PSFQCjyE(6HwHJfT9-&DC$Z;Q8xmLx)V^; zgMgwJ2`GArfTEWPDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVAVQ$1dDxj} zfJ9c>52&A&qOMla;ILCNK+$Ui6ip$Z=yd{$rV>yzjew%*1QfkNK+&576wM%@ z=q&<@W)e^|i-4lp1Qg97plB`uMe_(KnomH{0z#l@XxKSpfJE+_=?;^kMEfbox5J+G zWfi>>c0&!N=v~g2q9tr8TFRE9Wo#*0&X%J0*i!U9TZ&e&rRW2;6s=^VXcYlP9}-Zs znt-B@2q;=ZK+#$PiasWwXdMAX>j@~@KtRza1Qcx~py*QqiZ&5Yw3&dSEd&&8C7|dt z0*bZ~Q1m$gMPCq5w4D$rS`>Ej8z7PU_S+j5OOg5i2$~0MVbA)qioOiHPdApLuQ*?d zzGh3&9<~&H!vPXdY_5K#0N0Y!fkQ1p<1qJIb| zGXE@lzPW?LAryrOD2gVa$RVI8OhA!KKv4_uHi{l0peQ>5ML7s4%1J=cqXZP?BA_TY0Y!NTD9TGfQ9c5S9wVSAKLJGr2q-E@ zKv5wAiV71@RD^({q68EbBcP}_0YxPUC@M(^6eYRNJp&|C$$n#6vKu_oKV(0VUCQ;W zFRSQr*Uj2Oipp`m6qRR7Q3bXXJ;9cuifk!*k}XA**iuxPEk#eUrKk!UMO6tXszyLj zbpncN5KvT;fTCIi6xAl6=xG9q>JU&=mw=*r1QewbP*k6Qq6P#MJwrfILjsB#5m3~a zfTAV@6g4HFs2Kr8%?W{`GOqKK0TS71zwf%N6m_wmJbKpktS_smmFu=^B}J_{Uy9nW zrKl}iik@dnQ9HI2wP#CF2euS-WJ^&ewiI<{qo@l3MK2Ig)RlmuZUhu{C!nYY0Yxto zQ1lW3MK2Rj)RTasUIY~NCZMPf0Y!ZYDC$Q*QGWu81`tp*kbt5=1QZP>plApIMMDXJ zq86?*&H#y&wBL8#Qi|%BANA=Db3Nw3w=>!zLK|s-)1Qg96py(|E zie?f}G>d?u*#s2LA)sh30Y&o&D4I_|(EB2q@Z2K+zTginbC^^cev~ z+XyK7oPeS)2q@Z4K+z5YigprEw2KfZde?Q*wKIyESU5|hD1-e9$ZprOzO14>u3M^u z6n(?_QuHlbiuSUl=sUI)?PE*P_iQQJ&z7PCY$^JIEky^}C^|$y(P09Lju23Elz^gR z1QZ=7py&hvMJEX;Iz>Ryj|3E*CZOmi0*cNMQ1mkaMP~^pI!8d!F9a0*N&q(o&2XMSl`d^nie(zX&M$n}DK+1Qh*4Kv7hT9=4+> zL_kqA0Ywf0MPUMpTmp(>2q^LhDDnv?iY1^Zj)08IHi~i*Q1mDPMY#wl%1uB~9s-K;5>S+nfTG6;D9TSjQ2_#q3KCFMh=8KP1QZn^ zpr|MTMa2jxDo#LA2?B~r5>Ql%fTGd_6qO+aiqgk8XAO|Zm|O-REaG`mDy7C6kCd_u%)OfTZ*c&rKma^MKuU0s!2dm zEdq*a6HxRt0Y!BPD5^_9Q9S~RQVA%kPe4%v0*am?pr|1MMU4n3YD_>;69S5w5>V8P zfTHFE6g^8o(Q^b8wIBqF%EdSZ4Uot_`%bL96kWETf@~S%SzlIB+ZeZQ4=H+{^QEXA zTZ-DVrKkg2iaN5Ts1sX?Iyr(fHd6GI{g$;6F`o5h6^)5;r@bUaV>w@n#<8VnJX?w;u%&1sTZ&#~ zOVK2@6isGJ(Q9len!-lW>jV@{C7@^;0Y%dZD0+i{qBjXBnn6I(TLcu%B%o*(0Y$S3 zD4Ih+(Od$G<`GadpMatT1QfkZK+!@1iWU)2w3vXRcL*qYmk=l#72~WoKq7ha8aSh+ z$o!vB%>%X=&-${8-ivV$_mradIbVuau%+k&wiK;oOVKK}6n)5+qSb6E`iLz>YuHk> zmW`s12`E}eK+$>viZ&2X^a%k)8wn`-lz^g51Qcy1plAyLMOz6d`iy|0Z3Gm3PC(HY z1Qcy2plAmHMLP*7+C@OoZUTzFB%tUkLZE0_jPs`f5}D*0ILoEzhW)=Pd>!LiUsloH z826DrQuH0?OVK{I6n)Q@qWx?sI>45qAJ|fKkS#@r*iv+uEk#GzC^||&(J=ywjuTLH zf`Fov1QeYjpy)>eicS+y^b-L^X9y_znSi3R1QeYkpy(F@ihd=a=sW>M7YHc2NI=mg z0*WpZP;`ZWqN{{J(Kj(pRRbh4#(o{`TPYgnm~kz}v%ajN8!>K&eo}Ok^QGtywiMlB zOVMq%6y0G<(OtF_-D6A9eYO<+$(EuAY!v-PK+)d>6g?!M=pO=#qC7opM^T7?qG$q& z90H2M1QfXh6vYrw_2ggc%JoT6=n9^_XbE&3g=5v7Pb^+WlK>uwiG?WmZI!zDayf? zqMU3gdXz0ix!5SmO+Zl|0*dkyP?V2=qQ?j*%1=O10RoB&5>Ql#fTF?#6cr($s3-wN z#Rw=WPC!u!0*Xo!P*jS5qS6Eul_8+0ECEH26Hru+5Gcy%IeQI|NH6;-qD)@!NdJL- zk5=CNKTeG=tLRD3y*5aSDsjFPRc1@kQ*0@!!j__{Y$>Y7mZIuxDXPJiqMB?es>Mc8 zZ32p(CZMPe0Y!BQD5^(5Q7QpN^$93yKtRzm1QazSpr{c6MU4q4YC=F!Qv!;b5m3~e zfTCv!D0+^7q80=cwIraZ6#+%934x*~JSQ^PDDv&!MHQv!s{JPHHlAmFSw-zVx6Du} z>cII@)R8Sko!C;;nJqQ|DkjOmyb+mR;bSIY?qdm|1vWmug?vUY9G=cM_Xd+vRUS&(sB(@Yy zW=qj)Y$=+;mZI0$QZ$tPacfTH;X6fGd2=xqXu77|djh=8KS1QfkPK+(Gd6fGg3Xej|j%Lsv@v7WQg0ErZ_ zpCTG3MLF!}u9thB^<@=(;JKfVkfN2GFGZ`^QuHBPidM6w=p(iitzk>iTDBB@%$A~c zY$;mLM$rZWiasHrXd?kdpAt~CiGZTb1Qcx{plB-rMV}E+w2gqG&j~2{f`Fp!1QhKc zplBxnMY{+n+D$;wmjo1jML^Nl1QhKdpy(Sypy++i`NaTv`6f zRrI~*x}&9NKj%x)0k#zVz?PzeY$-a#mZHOKDLTTIqN8jnI>wfw<7^b2AfV_Z0Y#?> zDEg6rqSFKv{X{^~83KxaCZOmn0Y&EsDEftfqF)IpI!{2+1pRxBfTGI;6kQ>p z=qdq4*9a*3jew%x34x;TJg2Y$5~-WPz}Y87#qF17uX~>LWfk4>+|;pBber>~=nh+o z?y{xm9$Sj;v!&=ywiG>JOVM9!Df*i&MGx61`iFp`C|?iTQ4}JeD4KvGhk&9m0YxqW zMKJ^vc?1;s1Qf**P!vZ%Q9J=f2?P`+5>S*xKv6OQMd=7AN>4zM`6xN~X9XzAKtNGO zLZIlT=kzu}A~~`cIDbgdN~1d398=Mw`Y(jlLLlf@4n z>1Ve8lBlBZSzlJsQ@(q2q7+r(d?~8RmZEBGDXPwvq8e-|s>zn3T5Kt*&6c94*-})8 zjiR~)6xAc3D3ySs`UDg;AfV_O0*V?EP}GQkqQ(RiH6fs=DFH>z2qvqn+u ziaK+?6m?-s(F<%T>dKa)Zfq&)&X%GcY$l*b z(HH`X#u5TW9ek&{0TSt!&A{m>Mc-OQ<9yHhvWi~y-A+@aXcFg3(PXw1y~dWJDQqcv zoh?OE*-|u(Ek)DWQuGE}ir!?SXa)gAZxK*5lYpXG1Qg9CplA*OMRN%#nnys^@h5Ky#~fTCpt6fGy9=sg08-X{c#Ciu>)21ulu z{dDz2DLQOFNLt~0)|XZEq3^DkDn+X~Uy43rOVJv(6s=`T(Z_5lTE~{6^=v8Hz?Py< z*iy8SjiOHpDB46o(PjdQwh&OXm4Kqp2q@Y{K+)#}6n#NJ(RKogb`VgslYpXK1QhKi zpy*2iioPPC=xYLs_7G6?4FN^p5>T|4fTHgRfufbZv(EsDwDt|0RZ?`w{ZbA+{79W=qi#wiF#@OVKg56dh+v(FwK`on%YVDK?6JB%tUt0YyI% zP;`cXqMr#UI!i#&IRc7)A)x420*cNPP;`NSqKgC+T_T|9G66+b2q?NrK+!bL9bau_N)S*~l7OO81QeAf zpr{N1MP&&ndYpiwas(8WC!nYT0Yy&`P*jnCq9+L`szeABWs7wd8z7O)_Q&l%5*s|y zZ<^kW%CVmHWffJ6b+^x!qUxM4MK#z`RFf@5wb)Wrn=M68v!$pGTZ-zkrKlcTic;Aq zs!u>s0|JVkA)u%s0Y!}nC~8bVQ4<1+ni5ddjDVu%1Qb0>K+$sq6ty6rs3ieKtq3S; zO+Zl_0*cxaQ1m2ST8zO009<0Ev8M--%U~qE_Z9`m%~%h;_Yr zQq-06rKlTQin_CQMS}?_8bUzPPy&jE5l}RofTC9jC>lXP(MSS{MiEdnnt-A)1Qd-WplBQc zMdJx5nm`B?b&hq48X%Eb_9qp0k)rkXJ=(-r&-${8UW;`bERdopoG(SMv!!S%TZ*Q! zrD!@^ir!#L(VJ{3n!%Q$x7boNlZ~QT1Qg9CplA*OMRN%#nnys^@h5Ky#~fTCpt6fGy9=sg08-Y1}F1p!4L5Ky#|5Ga}y>-051 zBDL&49-1sgzWtj1s#wqZvWnKkx-%9^(OS-zqL0~9w2m!B>)BGYfh|R!u%&1tTZ%qq zOVK8_6m4dsXbS;FTL~!ojDVtT1QdNvK+zWj6m2J z^<@8KC)rYTiY-MyvZd%WTZ(>Sqv#9)ML!cz zbe4dka|9IqLO{{41QeYopy&btMHdMux5KwfLfTC*z6#Yg((eDHlT_>RE z1_4Dk2`Ku5fTCLj6x}8SiVns)4-JsWBKzs;LsE3sevou0*0a8>qCaEZN0&&^1J0MC zzt~drH(QDxvZd%BwiHFh>5;n>h1gOQ&6XmEEk$8Aid+JUVhAYm2q^LiD2gSZD2{-l zcmj$N2q;PV4G80ggLO@X#0*bN{P?U`j zD7qKx)HFaMv+XAu?@LjP{V_C;#Cg`2RrF|_+hv&)<>GuP%FULdJZve-%a)>iY$7C|x@;+`$Cjd0wiMN8OHl*16g|U6 zQ9}ZX8WB*`n1G@t1QazTpr{!EMa>B)dX|8q=LjfjK|oPU0*YD@P}G`$qBaB+wI!hF zc>;>s5m3~gfT9ir6m=w^s1pH2oe6=W>T%9~10<5sJ}j#tMP=-FhIEPZtS_smdz^b? zg%tJRd?|X7Ek!S}rRZh06!m0FQ7^U>^=3;^AGQ?rWlK>%Hj4TaP&9ymqJaby4I-du zFabqF2q+p#K+!M)iiQ(V^a=q*BM2xONkGvk0*XcxP&9^sqOk-NjU%9FJOM=$2q>CJ zK+&rN6ip%oin_)*nLjX!nq@a|x=GP2`)@!d$9dM5RWvouEx$^Nrg6R$O=nBd8*C|h zlPyIv*i!TsTZ(3~rDzsgie|H=Xbu}ia|tM#M?leh0*V$8Q1mtdMGFZiT0}t6VgicZ zA)x480*aOpP_&eQqGbdWEhnJpJpzi}C!lBr0Yx7WP_&YOqE!SGeMmsjYC@oBN}SWi z0EsyE`>tP?qQ~q9Ngu^|)|XYZF3x>rwG^%Ad@0(%mZDGCQnZmRMW3>zXcJqCHnXK@ z3tNh|vZd%VHj1_pQ1m$gMPCq5w4H#W9Rw8ZB%o*)0Y$qBDEg9sqOS-j`kH{EJp>ee zLqO5D1QhKhpy)dSiuMsu^gRJZ`w1vIKtRzC1QZ=41d7(iIqw=Ek*LZIkKoO96tiR`xj?Bl2u<@U_DALm(LR?**aZtOZKddT@w z^bcE#qT=<)U5Y|%DT-!Gk;9gvFk6aTwiLy%rO0EW$S0sEmVlx-0*c}ZC`urpD3O4o zBm#<(2`EZOKv8-EiXsFQWgws^BLPL32q?--Kv4<-MOg?a%1S^{HUf$sA)qKb0Yy0o zfuaX-PH_Vy(mt<&^OqD&u%A528ShzNR#BdKx8VjU%FFpul#eY%kFljFKU<0lu%)OV zTZ#&?rKm7lii)tMs3;pn#Rw=WPC!u!0*Xo!P*jS5qS6Eul_8+0ECEH26Hru+fTHpQ z6jdOg=m`RfDiToiBmqU02q>ydK+#hK6jdRhs44+P)d(o6P6!m`ig)@OAd&sK44mBY z!6W^`mQ;;+&-${8o{o2CZj_=roG(Rn*-})GEk&tpDXPzwq6Ta!dWJ1U4cSuEh%H5p z*(hp4Kv7cyikcBn)SQ5#X9*~Jj)0;T1QfL-pr{oAMXd=aYC}L#TLOxnC!nYu0Y&Wz zDC$5!QAYxbIuTIRnSi1$1QfkMKv7phpr}^7v)KTN)UaQTtt~~x>^}(U7VlYKR?$oG z?#WG3^fKp5QBSrM^ldR(O3eC#t~37o`9kW1Qbmqpy*WsiY5_I zG?{>+*9a(@LI@P~hg zPHh7u^0EDZdb$)fvmY0I9Pe3QR?#Q%Zr5#6w2||r=u@^7ZDLE&X0{YeeLqO5D1QhKh zpy)dSiuMsu^gRJZ`w1vIKtRzC1QZ=4py&_*MTZF}Izk8(t&ex67$A`i_MgLUkfJ5_ zFQ%jMp7muFos4%s{6dOOalRD&$d;nhY$^JQEk$S8QuH%hiq5j7=p0*$eql?|uWS^Z zC!pv80Yw)HD7r*I(PaXPt`Jakm4Kpa1Qh*7K+*366kR8v=mr5rHwh^EgMgx21QgvS zpy&<(MRy4(x<^3KeFBR9B%tU4Ay9NY-ub}*iJY^au0A0}<#L+wSG;F^Sw&F^?jJj( zD3qW_@=_GdmLi8OMParSxojzlVM~$6mLi`mMX_utiesZFo`9kR0*Vp|C`uxrD4Bqw zbOaQoC!i=oKv4z)iZT*Vl!<_%%mfsr5KxqbfTFAf6lEiz=n(>nvJ+60gMgx(1Qb0= zKv6D2py*+|lVzt-l-+*5=pQLMZx!WE@T@PZ=&=O%iQQ6^pYx@t09%R*vZbgHTZ#&^ zrKkv7ii)zOs2E#{inFDt1RF&q2`DN>Kv8J|ipmgBRF;6E#|bDZM?g_|0*WdSQ1k== zMHLAsdXj*mN(2;DCZOmk0*a~-P*jzGqG|*bRVSdR1_4Di2`H*X2o&W_aGp0nBGv7; z6y-|@9_i<>Uz)9*;8|Z*QN09r2-2`GA&fTHIJC~84KQA+}fS`kpxnt-A<1QfL;py+u5irNuS)SiH%4g?f+ zB%r7h0Y#k&DC$B$(F+6=btRyv8v#Y#2`K782o%*xaF!Y%k=1z&oVrrf3_42U`x?JwiFFwOVMDq6b)gcXea?i!w4uE zPC(Hs1Qd-RplBokMWYBP8cjga7y^pM5>PabfTHmP6ipzYXd(ecuM$u+iGZTX1QfkS zK+zNeie4w6Xet3k(+Gj0mlK@J21w*Z`+e6vrKqI+K+$3Xiryih=v@MemJm?1lz^gT z1QabNpy)jUiry!nXaxa99}rNql7OOB1QdNpK+$RfiasKsXbk~HYY8a&n1G^n1Qe|& z1d85Fa7r2=k@oicu4hQmOZH2%8xlP0%PQKG;5ObTMVmQaing$&Xe(QaK4VMKHntRf z&X%Gt*iy8eEk!%nQnZteqFn?O?Ixh;O9G0%BB1DN0*dw!Q1lG}Mc)!ow3mRQ?+7T` zM?lf{1QhKjpy&VrML!TwbdZ3eLj)8ZCZOmD0Yyg%C^|+!(Q!hcXk&si&;W^?v7aLP zREj3WnQlj^ebD6&ap=qdq4*9a*3jew%x2`IWwK+z2Xif$56^alY&w+JY@O+e8d0*dYu zP;`%gqWc6C{YgO40|JWvBB1DR0*W3I0!611oUH~(Q4#?~$pjRo zBcLcf0Ywo4iZT#Tl#zgsGqj}TCloq(bo1Qg{Ypy*Ko zigFQ9l$(H}JOmWwB?O8>iB9xEqo}U^R_o}*;4xYz`+q{um*`nvR#Cx3H}7F7D#ZEv zyQnZ*ii)tMs3=>Cim|1rI9rNJu%)OZTZ&4trKmI;MP&#mDoa4o;{+6yBcP}}0Yw!E zD0+f`qKX6*JxM@OB?5{n6HxRN0Yy~^D5^?8Q8faJsuNIDgMgx%1QgXGpr|$hMNbn@ zREH2K%Ae@eF+d`%?1TFPQnb)2s+;IpUsh3rM7R42Lg&Z z5>V8MfTGR>6m=n>=mi3bx)M;-jew%=1Qhikpy)*cie4h1=w(8nC^gZUYJfyW+wZ%s zFGYv#2T45>J?qOV>YM0(bX<6b)ue(Ga#24P{HwFt!v8 zXQSv90*XcuP&AT&qEQ4CjV7RI3;{)B2`CyzK+$*tiY5?HG?9R!R|zPZL_pDG0*YQE zplAvKMXwW3G?jp&X#^BaC!pvJ0*c-w1d4hmI)@C9$dmT3pFUD_FVTz{iJtXk70pg` zZ=aN+Ih-#=bJ*;2HCEk$p$rD!2riWae@Xfa!g-eIHYT>^@h5Ky#~fTCpt z6fGy9=sg08-Y1}F1p!4L5Ky#|fTC3d6n#iQ(P{#UJ|duK4FN@K2`KuQfTDE-6s;$q zXafO7pAb;Akq{`FndoFYWfWboe;3V?qHRfLe46N4Uslo9MEA+lQuG<;OVKvA6n)N? zqA%D|w4E(QJJ?dRlPyKN*iy8cEk$3lQS=o7MPCz8w1i(2M8$ofq>((X+m+qMsAp(PyOSEaywnIkpu2!j__6*-~_#EkzgDQgo3m zMVHu8beSzhSJ)`JNWJjfTF($DEga#qK5<&{X;-eRFWQ;qbNiO6#bOwEH^+RU)XPwJtIYx z?UzHMlRWFoDvC*Rzd9>L9_LGu&z7QCwiLy&r6`^)MG0&vN@Pn>5?hLr*;15_jiU4f z6h#Oq%0NI-Mgod55m1zwfT9!vin0(;l$C&@Yy=cNLO@Y=0*Z1FP?VE^qDKiR%0)m? zZUTz(5KxqtfTDZ^6g@^jQGP<8D4gV6H9#V%_5*4+DR`vc$o{C%0!g0rWfc`kaua`* zqN1EHMa9@sRGckECD>9_k}XB0*iuxQEk$M6QdE{LMUS&lRE~h6@&puBAfV_80*WdU zQ1m1LMU@CBs!Tx9Qv?)MA)u%#0Y%jaD5_3CQ4Io$Y7$UXi-4lq1Qb0@Kv5k6is}+j zRF8n7R6?MrP?A&H0EsNJUpgx+MWyVQL+U4a)|XY(D9LSlL5do4z7#cKOHos{6g6W@ zQFFEwJP$dU7Xpf2AfTu#0Y%*iDC$l?Q4a!&UL>ICB?5|GCZMP%0Y$wCDC$iJ6g`vV3^qU_ zH|)1JHk6_a_A4NLl056nDjJaF&b=f>136!c2C=1RFk6a-u%&1yTZ)FUrD!-?ie6z$ z(FnE_jbx)}6aht}2`CyvK+#wNipCL8G@gK>2?P{PB%tV30*WRPP&AojV@{C7@^;0Y%dZD0+i{qBjXBnn6I(TLcu%Bm|23B{|y+kVw3JC)Qtza#>Qdl056n zDw>z%{&Yo(=5xLjEnrL0+iWRX$d;l-Y$;mImZEpqQuHocik7gYXek>-%Lpi1PC(In z1QfkbK+y^UiasEqXe9wfs|YCikbt7q1QdNlK+zfkiq;ZP^f3WN>j)@XPe9QI0*XE% zplBljMV}H-w26SC&4fVFoFpfF)hOC!zwdgk6xED2V@r}}eOX1HC%KRPCPiOxz7%a| zOVJLt6zyb7(Jr;*(OD;95c=&dDfRz^h=Wa;&mzdmGhzWVRHgV@pwbwiHF!Qj~#> zqKpI-Wg?&`GXX^@1QcZ;x3$AfPBG0Y#4zP?U>+qTB=&xPc-_;!6W@<_B&<^CwtbHRa89L zy?aZFN^rgum1Ij%DYg`qW=l~SwiK0ROVQ(ODJsX7qVjAhs=!9k69g1hB%tU?0*WdT zP*jqbs?bW z1pV8QfTHdM6!jpW=tTmGULv6AWde$N5>V8OfTG?66!jsXs4oFU{Rn}g#>q}c z10>SMeq&k_DcWci^-uP!FRN&9vOD&^6b<2gDH_U_qG4<)8qSuYSJ+ZCf-OZO*-|u$ zEk&c*QZ$B*qOk-NjU%9FJOM=$2q>CJK+&rN6ip(aXfgpsuMto*g@B^h2`HLMK+!Y; zil!4#^acS%ZxT>6gMgy92q>CKK+!A$ie?i~G=~r<8kp?7Z-7Kn?K`nSQq;u$d$hU9 zp7muFy`Ajtc_2j#IbVtvv88A+TZ-OcOVPV*DO$poqNQvpTE>>5kBy@D2`E}Y zK+y*T6s;tnXcYlP9}-Zsnt-B@2q;=ZK+#$PiasWwXdMAX>j@~@KtRza1Qcx~py*Qq ziZ&5Yw3&dSEd&&8C7|dtLZE1Vvh$k(5-Dw_yFiMz+7FVpC41JFRkS17O@1gvJ2_v9 zcCn>sH(QFnWJ}RkY$^JhEk%3SQuGa5ioRt_(Ox!+z9XP$9|1+*6Hv6DfT9Bg6#YOz z(Ln-=4iQjvn1G@q1QZ=5py(I@MaKy!Izd3uNdk&a5m59a0Y#??DEf(jqB8^({Y*g7 zSwf)bi)5#)0TS74zmB$DiW2MxN#~M1>&q&-knA>(vR7cf@A@L=OVK5^6kTRZ(G|87 zU1dwrHMSJ}#+IVr*-~_!Ek!rjD7r~N(H{g9-6EjqHUUL<2q?NsK+!z{itZCo^d|vD z4+tpwi-4lP2`G9?+OF&T!0Yx4mQ1olEGt>Zy zOv`5AoR^}H?YlQWoo9VnMG5KL`O#98$oW!~#FnDu|Ha%}fJbq*f7`R!-7FBGNst67 z1WH?Ikp!oOLWn>hBq36$rYQtzu_ASMcXxO9K6Q6@cXxYA{kyK2-?`b)=Xu}%aeVK0 zyx$&2xb}DM+_SSY=iD>*tU#7UxnxUK zXfObah5)c=695)%3c#YFfXJdwx$*l90zZBE9bi2y8`1i+##09Z5`fJIXP zSX2tYqNxBZDg$6qIRJ|)09aHBz@ljYESe6$qACCu%>ZE0OaK;D1F&co0E=n>SX2wZ zqB;N;%?3mkjmV8>C(WXH{yti;<70kCK_0E^ZDuxM96WKm;o zyxIiGZ}m^iHp!w_^DXR_n{vP0qP=pHOFPPH;7M%#dqLTnvbTR;oP61%isQ@fG4S+?b1F+}}02ZAIz@oDNkwtst#!oas@`C{; z&YrU90Ka&2c5cf3a*NK-P2Q9vi!PwOEV_^^i!LI|qKnD0=n}Flx|A%7E+fmL%gM6n z3bHJ^l8i-H0kG(502W;Xz@lpbSacl#i>?P?(G37Bx)FdyHvzEdW&jr50>GkM0a$b! z0E=!1V9^}_EczD!i|zzq(Om#6x*LE+_W-cyUH}%|2Z$^>H#h#836fvyZ{wdQi^}~A zA@}E|+%LE2;oRh}U1ZTCw3kJXl4a3jWLfk$Sr$D(mPJpJWzkb)S@bkn7Cl3jMbDD4 z=s5ruJrBU57XVoFA^?kC0$|b004#b1fJLtYu;?`a7QGI@qBj6o^dk02aLuz@iTTSo9$Pi#`Hi(Z_(uq6c&1{kob(&-x{zhh))F{%-6ixheO{ zE&3uiIXPDreMx&+^c7haeNC1{-;ia|w`5uL9a$EAPnJbLkY&-2WLfkR8H;`fV9~z; zSo8}3i`D|L=vM$1{RY6I-vLSr!$LWl#e;5P(G+0kCLe02U1fV9^i&7HtB+qD=u>EQ_`!%cAYbvS@pi zi%tb#(P;oIIvs#TX8^G1OaK<01;C=S0a$bn0E^BAL>BFx7vI|i$^Rl{;_M@f-t}-^ zUdsJ)i!RDbp3_GbT}*pfbO~7&T}qZkmyu=B?mMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4fJJuzu;^a^EV>hbMRx(P z=xzWO-2=d)djVK<9{`K)2Vl_y04#bC5Lt9VUi<+QB)_P$iF2VWTH+V7AIeL)UvAN3 zdC3pgmqm}$UKTw;mPJpJWzkb)S@bkn7Cl3jMbDCD(Q{;3^gLM>y+FpI7XeuG5&(-{ z24K-E04#bHfJLtXu;_IF7QF$$qBj9p^cDb%-UeXNI{++t7l1|Y0kG(O02X}!z@iTU zSo9G9i#`Tm(I)^b`V@dgp8+C^9?6S$=w}x7@$Y~H>%?`Z6zGV}j&gnP=jBC5x8%+aX=^Q|^~rl%JnmK2R2QqrEKZPL@SI z$g-#>Sr!$LWl_qTXa#)Q2pK`jW9|eE=5q17J~q02UPiuxJ1Piv|L)XafKi z4FX`%h5#(u2!KT!1F&c?0E>nIuxJwi7HtZ^qM-mR8V10k;Q%Ze0l=bS02Y-1uxKP8 zvM4t{ezFOY-{ixxy!>dSf3C@s9F?DPzucm6`N>-b$)fSJmqioEvS>51EZUqbizbp~ z(Im1g+JY>LCX;2+6tXNTC1cT402Y-2u&5k>MHK)nssv!sGyoP&2VhYZ0E=b-uxKU# zi>d)wGz)-5H2^HC1z=Gf0E=b=u&5q@MGXKfY6M_W699|01Ypq|KxEOF{P-ItNd67} z*4bEDbagmj%TKvqZqc^+$=^4UMcdI{7Hv^7799(~qT>KqbUXlyP5@xhi2y7*34lc>1F+~602ZAJz@pOtSado7i_QRG(U|}& zItzeBX9KY48~_%b3&5iD09bTB0E;dFL>BFrA75aCztxxXyB$A1#*!u*u`74!_U zk{fiqVQ4HUm}F<&K|!mS@(iXdj>&a!7e6c z--6rh1C&Jtf7)5rpn@{{Pmcx{95EmWh88?)Z?_Z|^w=l}Mi*=|I0(iUT(C(HOf2|x zXb?;(7&amZ$_rMN1i|!zJ4OXTb-~|bf}pOTVtf!Z796!%5X>!jeqs=8TTn1L2zDsg zt~3bd7hF^p1d9qjuLy!A1tX>h!HR-4GlF1s!JXAXuzNwQHVF1Em^M2I_AfZ5AqWmG zc(Ex64ln36Hwca{Xx=&qjxV@m+aNf(;LGiU;Pir$mLNF0V7GZeaDKtvtwC^cL3~jV zTwYMMQxIHTaNLq0xW3@!WkGOrL7!cM;P!%+RY7o9!DVZL;J$*dcMF1t3P$Z21dkQ$ zv3C$WRdDaVLGWBb@_-d{i*+=pgv4;EH2| z;H!dfj}LSm9Nd*;a@Zet(5+hFIaat8F{P3jKex9~3L}|BifctkC~I>7lVg z{||wSV}<@dx{i(&`hUqeK33@er{cs|q5r3NQ(}ewznYcD3jM#OnjS0k|5vCwR_OmR zOkJ$d|7VZJSfT&d40B_J{@eQ7#tQw%(RYXy`mbBhj}`jQ6EBJt`tQpwi52<}gszAc z`Y$}LjurY(^z9xi^xs(9J67mFlC^)V(0}FV;8>ymOwHl3LjRqSqhp2sLlMWv3jLe@ zC&vo?tJ3jMpbXU7Wt%aZ5E3jNz|7sm?y>q?i$3jO;gSH}wd3j^233jGt`H^&P7 zBfGc93jH&ecf|_*Lv#1V3jI@055)@oV=Irv3jK2jPsIxTjpOHHh5pXpOR++K>*lps zpZHZ9r*k%eF z_qMRP!f+206{gs)qQ@pF^!8=kLLp%%L9xjS&DMv+rbMCNsrF>PKKc*0zgS(e^NLSy z>DfOvJ3H@`wYR>pSN~XjcHWg%gU2mKyVo2IBucHS+o?*HoUVWS6r zJMn?N!$vpUdexc68nW{ay8Dcu_6qv>HS$J#ro~aKtPU3k{cI}+Eym7ePG8-3;oCl^ zWasmHkK87l(Pt;z@}AAoX7u3khwr~{P_&6PT4s&^ww5H0$eyJq$Z`t6{F_$Ff^R%$jIj0jgjcHT<|-unI?(L$UsZdEv+t3EsN>FCv5 zc=6$n?-La5YK`{tg*ede_zG-}S|>a2eqpJvz+~sr%9ZE;8^y}=hU*?GZ&JB9`Qo`^?l{EethtT^cRh0xb&RJ4VCxZ`ktB{S@f zFV?2TS`WY7a?UOLg)e2_o6fVPv8VXs==a}@*27bmo^r(QLBG?jk#E(>QKN9HUTMs? z>dJ^EJ3sLL*iFOvd_U;wdEtC+`2NFtZJ}*ZQ+FJ^Fetj#nw;Vb@tE3P%R=0F+8+l+ z3$b#C;e*3<^GfrSWZ3q_RNbVY-v`#@LTmd0O&&Vu*>fX_S`!C1g-z-^FWER;osS%Q z?vZ;3{j#ki@HRc{FVsG_Wz(I))p^AePuyvZZ4-RG_|}&2X^yBGyj?J$NKI^V+c^%s z?ql0fww0&v|9rRbC7t`(YY+KL%FcW3k}riVRX1a|_x{m1k3BEN{M|o~@f^Y0;mvyJi_a z+BVA`nx&@dX^oO?%Tdt97Sx})FuY^0t=H&`=bYSYq8&AQ506dm#e!_ytEyXGEI)fn z;b~KQ`SbQkW;DnuxNWMf^S+rg5nDf#`ReR<#DOu}UM1lg>wl#69$AGaOtl`l$Q}s% zfgl*bH0IFoz!zs(*KkSf%RK_J9{Z=tU1?w2fJ} zm2um`?#F`JUUsyeCKfb#S)f_YKF{y@Z0!LruY`AJd-*P+UU;I}=Vi<}eRqo8iv{&w zqB+fNn^V2dDLgm_cH;QYTVF%5puvkb$_h?sY-`*=W5?^Z9b~|G*vzN%``of@p4>Wz zj}@Oc-s)!dXY0;iv%jpYp!mG*whn#y{60;5X>29g%_h>#r^&o!=CkaKBObhHO|oLY zckL3y>}J#2Uu^jB5i46pELgQ-#Hy9^MyzaJHLtaK#meQYTj#BAoj+pU$~{)BUhZIC z>-;q~NUDVat{;YaQ0wvg6`mCB?%>4fBVG+r#Z18nJlUyd`Vqw~koaGH=o1W&hU~W7Qt3 zGS|eyMI%aA&R?^5+48dGD_e)9*TwFuSB9%3S|fEUm+xfjeAS4C6)h`wu3WRMxzS$B z!n!4ERyEg`j-54z&15h3|HHZezmZ_qmesAkErLKAwTxaoe4bm@Jim28%bF#tn^*6# zqIK2qMJ}(IFn{r~)fVi;!2D~Tw|wc+<;$8|RxCDVUN@9gG}~I4R~B+(COCdB_UDRF zVBd8}hC4%iR4ke7_TO&FSay72EZHO8Yj`piUs&Y#iu~U2WQX?m@<$F&CbNep^RsP! z*(0oWOLpt8yN-&3tVFCwGRMn$$pKz$(lC06c_#;W4d=PR|Kce&u&MGlNOs#aoPB# z>7L9VswsT#BciA2W+i$-(ejK)_Osb_C`xwBj(3@u>}jFn2Faf5TON_!J=t?;c&A&k zXMevlB3WQ-B)V^RZCYDN1Fd#0O7Fv37AtiGzcWN+audL;jQ`}KXYnaMs?-pH0QYBn>f1CqV_ zhcoNAwU&5h^eUO}deL%isO1XdaC>1Rlf7)d9cLyBs=}8(Vqv@X8?u)Er*n%|*Cfqk z-MU3`Lw~k#AvQ?<_hsstU63pok{q;gvLL>PZ#CZ}z8%(`;Up~=bzrm>HRnN@uhwTX zGMaouv~dS)WwG0^aJGY7gMN1Re>R8og0PyY)&Cb?;l#FAm_6y5^qN`6U~|`Yfk?i{ zp8v7Jy=}8>G$h%_g~neq(#6bftC5&d7tkepU~;fO9&U-OmbBo5wP`}%i>&>~P~<-5 z^?>A%;$&~%M+U63kNj`{zm}C^@Vo znHRpE4Uz?3*Gmr5%M0W1@X;)LiNg(NX?0||+5H`Ctj9;BA0Ov9zWea#@xlLi+*fB- zd^bHF?^yJYDZ&{KPnLvF7~gexa(%xSZ3tU}?0DxQ+tqzj`6`e44mzZbjOO~GBhNQ< z{MLPE{Qt76%gv7eYrh4yn195Ehduj6`%a8{uR#No1->t9WB=#gAa|rSeI;hAE<3)< zjD^Ym_Nw#fF0~nl+Dh|7Ul`p|dq#T>Ur~ciuz&XZ>uBA5WY%Om8Le!nYp$rTZ?3A@ zvb4IYyt%Y~TGOnGn#OqvaluoN?Zmg|suCA?_7SvZvYc44*o1UJctg)fV+LzVN zs;jPOv?-fvsx)0?+4SZe+a@fnFK@1?ZM2CSD(V|6%F~a`sI!?i)igBK)z$g~&2?3C zE2^6-YwKr~Hb&2AvuZ#2)au%@na$;;jit>sO|zy})cfnGt&gT2H9qr+YigStnx;0C z)mQmsm96%G#!nCHgm#NrU(rxkYfBi-X|zqly6|PMs4s2ESaR0etcGdLQ=2L) zZT<~aTUVr;{Nt5X&GNMwPUCBGYH{X*R@F2&@x&9fa3z)PCMm1ms;;rtUUGGHb6ss! zO=E>#@<>fzYSm8eMvZJ<9lnC{cFm_&+nHT`Ww;qCYDz7Z2ep+A&86khY{rCB`;t{= zyzq*~>8#)8y6Iar+qRx%Te+;Xv8uKvT2B+w4NJ;0T2|H1Zk}q6l~*-HPsX~8X6Z8v zH(PUcRn5%wTANcsiLW( zxzg5D`k}hg`l`mQ($S@!Ra&!^HeK5+!p+uD+Yl~6xmlfFfHC3o^C~o5Wr^({%?-7c zmCfxYE}777>axHY!V)LA}4Q0&@ zjkUH;D@;di!)V>Kn@Pt0lzzdor?fhJ=H}YEikkFes64g4YTES18e5~y4Hb=zzAy9C zm1Wg4!^IsnI@)u_gwGg0c`+#5nL=a=Yg>)igC(~5(sQe-s;?|zW#yx2&yhwEZVN3-$)@RJ{A~t}A2jEU(zI%7!vin;N3EZ2LxL ze-!OXF0-v<-?@E#WHhgzYrAxF?UohwmDRO#)_v0YnrZ27)4VF3m7bug&N?$~;yUY2 zGW*l;B{i4{=}vNFdWB8RSUJ9d+MYV{J>y~95VlI1E9RC}RFr2dvQ~)ou#KhGL(Ht$ zs=2bX%J*`%p{DR5o-JB!Q@!1>eXO#&s;sTo4=wf1EWPSVMy7Xg+ts5T(DuLiYnCqE zBR%hMcc`eXYQNj?%+?Lhs;&3U;r(PZi;>|DvSj(Pg+WZ*$_LWu9-lJ$s`)jt1SydUWlxPXYW;{#S@A$^?9xgnZX(`)z!%p8^ zT2|InUs|RvEWJF_?Kn55)Lv*~)vOBJO5r@lr?+xh#uL`rHfpFZGmlEk8mqR9jyYp9 z4t4C5c5t3n6CRjD6-L=4ey6lu=bqU!wDnje73nSKchie05p3JrKHj9moh@eD1oos; z>r3sBE`|IVZR=$2Lbj^tZmVk>v=fg{KcQ`gXbn!~PDQxES1n$+taW~oU4~kjemeKL zw$f&2lC*WvZCyZFS#9%l>zdLHSU0n3%cG^Yqkj6qvWn{Jrs~pqlYClLgZb=-DqaXy zvCl`#SZvM1m)Ne;Zfcks9m{Rh6`@CK zmSw(tpTc_o^n#aQaxGQOShQf0c$DdQxooR?)AcO56Hy!%_HJbF}+nMP}A+ewbT# zTIsA=rESk{PTJWOtHbu$@JZYD>ynbtk7+ecMP(Bv6!`_>;Uz_WiMV+D$k9cESGF!` zZCTYiq-faEc`MdTnzwxA>ek(dEgdz=!0JV7mhNbE!II@ItB2Y3+(bpEOpn=V*UG;Cqfu-cJD!|X!lqw>%O>L8PLZP|s&#lwPC_6nXomy30wRPM1aj|v0ZPHdPo8P*7IEzv3 zy3@9O-*=$2dTj>V@y2?EMmyE?<92!iwqiIYYTLNBmzCLBz|>M3D5+cZ#kO<&Xz|Cj z8E;4Th_xS(_;A5b4ytTC5S>OuuRD})arN@$D@uZ}jQq#4v^zw%JM*1obDCN^H`D5| z&%4nW8Z2J!j6LsA66=l9u(Mf5E4L`#s z(V(@#-g9U>mGq-e+c}sGShY|306g3jc1OrZ$RV9r2b947xS24t00m9_0hi){{-mzITZinKf0 zq&wYz?jbgKwv{%$wPk+m%I50UWx>wAucVhOS^-TprCZvr;N#--BN^+rw8=)@c5aqA z%J%aq)?%d6G#jx*CpYN_LVx`PwzkImitvbC^1pmkdy);|E~MwM(_Gyvu~9&J`7+i(U48BJDjOQwR;jVmW4qMAQ--$q zg19kNcAmPmdC}Z#@AS1@_$aXxZF_=nY>^&dFaz({GHrw7Ol4`gU8PxP_#67*&pOSt zPoKZE4UEcloGh_11uxCkLVBq=Q_l21l({TiRV;%q+d9Yb(gwd`mcH0xyHk3m>7iQb z)bQF_`hkoUSzpokA5W>nu8}ddFG(~U3zx~xW$ZPuOg5mjQCn46Re1ENE4719IF%hj zqC2*$wwpYr~EZZnEoHwlXzC&Cjl8u?DRV(On;^X(`+0 zWTW>6?;_j0^hy5X`70Z@-4(iar_$+Da|WZ)*on2ERoZ^fWLt&n!%mT+^Ei zKOd$vH_WMOv_~=yrVQmubR8glfE!snCYqIX*}hPAFGX-`N>GIQ`i&wBKmlXNiqiqc7?R6%z6~->>IAIy94*xPGTzTl7(GB)#;o~UE)`t!=;L@sn05%+gw)DsN+lKCFOAW{(0bx z24TF|^rg3OmTlLjOYBNn=HAtIdBiKOR)IZ1L)bHEq3g<_oHa+wPm>&S7^>{hfH`;+r;{d$@!_aD6 zyN0x|(^}gL%Iz#Ba{LrR_RgapFm%*GAu?oi*d)Y5U;{=S1NX+XhH4d$^Cj3@{&mh1o{w<#KYad-UR+v7CrRn+m$t`qrlW3@ zH}y)Q%dX*U{3>U7Cpy9AnZ4(3e^5&AjG6mSv?Ml*a9>WZkFx60S#=pl^k_Bv+jBnO zw)d&ph6p92(;cGkB;kDhI%c$J?fR9{Iy;k}Ya{A*l4mSlv>u|Jhu6bC-~!t_!s}kT z49})2OEXVSXu+huBpD+QJ34CZMn?~SI2t1Gly%X0w_UDFub0ph>pjw-Y*snr(EpR4 z-{j+;(dYKUb!dAKHl)4CRJg4>_bcO>Z&0x!q7@p>%r;iIW!jH4+Gb(zp>it7+F-2L z(9~dWi)q;Xk1L{nF?5~xK{Bt=6t}x#(>4mVx8U`znlGLYlG0;0p5M zdx-Hvr@yaGN67oKw47R9S~JtSh6=kBx6WCazm#<+Z`&}{we~)sbyRlMwzMYWlAmv# z_Lpp;aZ)r;Xm@Z9Ut`Ad)oL29n z_H|ZoyOFE=6z&H;reY>6T3KnCt?A0<@YEvkr{_}<471!U+b4A)H@dtN&MtF=70Huv z-s2;?s9W?4l)mz!u88Lk`2yw$+^4`k6Yyrq4u5qU*3sYTXX+rnDcbRoYcdMmhdLjbK_?*=9w9 z{T+kSl}n2%mhRX(f4;p1*vO~R!#5H5l=+bV{+5D&(7v<%{cSh<9>v~WJ9i1jJJiiT zd_T48po2Re(&5n5VcCZ#k4PLDKPv0k*wn7Y@nKn=x(=F}vupToUHEV51Z&vhpK}jl zBkXQ+{IFTWZA?=WWap)3b&PlFke}!t>k%u67sh(UddK?2`o{WY4UE}$$^LQ6M2X=0 zzcVL@XMFF#d0by3V4App7(3$@w+~|57kM&niNL-d7jOC*u}Re*-dt@xZ>PlyQp(?Z0*s5A1uA8Mk<_UPkiy`_i@D;(>jsCF2&i zpE}RH#RL0dx&dEjzRmLO^^DAzAlL3sStmEFlUvrw%h$>FeXR7&=XX##*%y%Pe%rS~ zqMZJghdt(x^P%_Xs61$OFlfGxXa8*^*8bS{AKsbGoS-D*;8<*LfwVnVJbH8xy%EsH z!s|ilt3&PI7W6km>~^C4b+WIHJ)oLvE7!ib71+0EgHHBkCI9ASC;Qsb6yWms*|f-Ku926#3728;WC>(h-@ zouoQdwNAB3b)Kqy|2%BBi|T%=2df^hdV%Uqs&}Z~tNO6&ld8|FzN-4R>W8ZKCG7Bd zzg7KN)xKmMa{r2uzaINWby)37)M4$W>c95pkM~#g?;U&IRMo!U80K-RlT^!8{X5A% zeXVMf>Nct^stZ+@s;*MqLv=sZLsXAaJwf#})pJxYQoTa;I@McL?^L~C^-NwRcR4Y`gRU1^dR&7yTq`F*n zSJiz~eSh-hIZE|J)iYGjSG`R2TGd-r?^1nG^$FGIRbNwmSM?LsuT_6i{arQ7_G4e3 zj;gt;1*-j2H&h*}I!bjj)l${zsanV)sGhBQk?NJI zH>lpOdatVYSN{5*R((nJP1O%nKUe)u^%vE@RFl?k`Fz6f4O;D{+*@^k>R{Cos$*3r zsg|qGRIOLtN_7X-g{sR`*QoBTdXVaoswb%W_p^OD&r|h&*z+~2H>=*M`he==s{RF1 zpZ--<@2@?7tooJekE*|^#;hOr={l&cr`l6>ebqs#!&JwrPF9_+I$L#X)p@E*RM)8P zt9qE~@v3L2UZ{GN>dmTmt3IOotmgKBD zsba_ysa~&ohw1~WPpZD8`nKvPs^6-vRgKwiUHI$k zq}p9|lft_IZ z{8p)6y-AesQ2k+Ol>b&8Zzm!?eTC}2B~d;~^`TKweqObcov`@y1*&y6kny~o>ZzMW z`6AV~CPw*l)q#_vJVJF*X_VKfURxIBJ5_(Gh;pnls+-xk%%9Ib&lJ}EXGHZF)kmtM z{Gw{-+9>x@t)Cs`X4TUhqI`+!J9fh5^Z!zH(A+4OsP43Nly_6Te%mPDt@`inqa1IJ z>cp0)R;eC1FUrTMKGquLmsPtiigF*-#+{y zTgKt*x^YcZ?^Rv9Ta=T#M|F!mqdHUd;Ju@Kg6b3dM)_6M+ykP#zUr0-MR}g;*@r~= z3e^t|i}JUsgO7~z7}aG*M|m&Rn~#n1{i?qmALY~uQJr#9RA;FkdPR6jaD%HOMQa#57Wsjj#r%KNC^dRdeoRQ=d?EQJVABkJyG6I z_4fOs{IKd@4@5cV!Kju$9M##XM?MnvkOq3U^Uie&;uT%Z( zg(&~5I{f7*Z?3xf)hHjJ`mfic{HSX1R+PJ_R=yME2GyhAi}D$&FMJT?cU22Nj`D`8 z+kYD6omDUXJjyqye(`0Le^D*|Cd!jkcl|EP2dUomLzEv^&H6dY>#0uvCCW{z$Nn1S zvs7QQ0hVvi_f>oU73Gapcd)Aw{`gYWOS7VUlj>LYOIQB*uc{+$faZC!>h2w*e2D5j z_9IyS_>-!Mu2IfYonZrXe|(PW@%H;zp3hNz#eP1?^M|T^?H98=4^iFG27;cKt6pxu zq2>7&)o<*_v^@W=I=U#zrK)?{g#my3FxC48Mfqvf?2V(`O|^PRl($m7(SFCy+uy7D zr0OePlXkwS{GHd%_5*CHzltY@MZAM*7q2$ILgl`y1H^|a7psmDpQ2o@S|#47JXdu) z@tst6Q$1Mq1l4m@uTs5T^JF+Wt3Iasrs_AUzo-tiA3^f=Q&d-}?yY*A>W8X5?E-;MKi#XX?`qX1)vZ)_R9&FD zTy>S|-m3en9-(@S>Zz({s$QgenQDi?_CH$=QzNY1R0~uGsBWk_RJB;OPSt+^#^$b!CwCYQ$ zuc>~k`lIS^s@DC4?XqK0?WCHg+C$ZLyKp+wEv#cyC#cR=ZBpG%HN2i<>t~Vj64lkJ zyQ^mVa&(HWefs+Jn^zm&h4q81sCM_9XZxvmFnrY>OINq-Xm$0T5}t-D5ZiHQB$O=fIa z>EDLY^F&kplPvMys?i*6L4)D`3n;Dj1+eVY3@3>~Q&GvtM z>tj>eYE55tAH7aXTb1E$fc@*!#iJOkJDoq~w~g)3_m}_ObiQw_`@ESyNaWknZ@w>e zw7)6#=eLWO+RryywV_tHy?r`=zPa|tGT7bVJ@esu+kd%nuhBr}{N^vSpKdfqe17f~ z^P6w?X=8VT)1c`)O#m3BY#c^mhS*-u+W&+DA$JtU)z-3?Nk z$ATiiqZ_k6z;fpNJ~|*4z8B!H!-lo#`JHa}X=8VTjctC`m8NezcCwMo`TdkJKYvGs z<+D@TcJmu&^E=P>MQ+URQUjUuOB@&rx05g5diKZsZngW~#(nVHD;4%DjDw>4{;xmg zfA_00-Q=BO!3<;En9fc)+b!SGHeEFnS@q}j+Y|PexqO{%`Fy?j@_GNx^1W&I&E*wV z!rN;$zs(3%{dxW7m3_r?_nrOcLT$|K_wCQ;=kxdHWZ$s6!B5u7UE_CjV}7P&yXpGc z^4aNU`o?tWA5vN~eEEo?qN0*<_7+X?$nm3!?S64_Nyfip$Br&48b4;-n2|PJQPB>a z_N%C_jDF`Unr+P9sbIcNa%YAq8SU$XgI?B?uDE65%tU3^${v-QS8YCH;`G0N`Rni6 z@AfadVZdfH9$1^mdtmML#p7o_u=e8O+Mi0x8g_VLZK5RD^!GP5Sd-Xj0^ zqVV4j!+%R&zqs<&%EX{eX1=)APFM&3{>EEtbBi8a8w_}BZFki|)xKe!yJ%|g$ICC; z6kWg1?OL-occ|Y_jILSRIlOnt)S9&&!h4;+&+S~ZHZk=1*YamHEZW9eydhzuduJ&)uJ`n9^Zp#~B@~I{E9n_mj&{zT()`NBnizQ_t_U z_RbqW3vzo-x%IH`f}PJAHsQ@nPn^>0v-?-Qv)S2K-E8Ndkza|}INQ*j|1u-|qI~8p zE0%qs?Vwq)4)@q@la-YmYTZ{>R_a=V@t(HAvt|{}vIbd+WTib4f6Aw-?X^RQQsX^! zNQPJLI;8e9lM;!fe+oP+k$T=Hi8t8<@uA&H{r-ja)bZl(-sL5a^Y*dqPg4GyiXKvl z#74<$Y>Ez3i-W|*`d>l%TPz6@gBAN(92q2rD6VgDRFK$2v9HC^L1I(IJ{HFWiJ^+U zEshNm!xVd292X>pD;8QDA0$R77Fe7RB#IS#S}d`}DpBs?*_Laha(B}zU-xTF+&$fJ}%1O_*d{dPZo^AQclfP`18z>L^>jN@d&r9TSN`@n>!OclydL+A#coEjsODek7))!XC*CnVEdn zgbodAuY-nvZFGF%u~jY`N|m5s*E8ElrdzX zGKMTt#*oFz7_yTxhU}~y8B!Jh-nM@yzYw385gBrv^;3x@DL2RakQK@A?ZMEHUDQ;D ztW=aCs}yC(YDF2cMp1_BswhKtQC4h8(XP8L}+yzhB;IJ3H(omPdy8+q#JpQf`hLa!RtB9ScK4PE}JGa+;zH zIbBhPoS`T~&Qz2kXDP~%vlV5?If^pmTtyjjo+5^vuZ$rVC}YTl${2EyGKO5Nj3JjO zW5}h-7;>31hFq?UAy+74$d$?%a+NZMT&;{D*C=DiwaOTBoic`8uZ$r#C}YTt${2E! zGKSo&j3KuuM~0jfA7k6U(^1}soE#Za;76HTQ{gY)n<4*7jGUQ%G8FHVZ47p!XhCHAsLmpI=ArC2H$ivDQ@`y5qJgST#k11owj3Lh{W61N$81jNLhP&h7NhH_-c?eRIb{X31d)7``!ks+u0Imw$TH^=*scaw8$5E>fto|?*#_Z4Nx2Z}P} zLq!?#k)jOwSW$+2q9{W?Rg@v0Daw$~6*1%sWeoXJ8AHBO#*nX-G2|O%4Ea_WL%vhS zknfc--^v*Bi!z3+RmPBCl`-TuWeoXU8AJY1#*jaiG2}00 z4Eb9*GUV;}p0@ovrR)l9;+@ctoG#vn1hJH>W1n zE4im-AJ?o0=;6SYFc;9>fh}Slpqm3*#(Y4&16#;$fIJ7bl-&Wj4s0=d0M>J0%h?mq z)qyQ&0icTmThc;6X9GUM=>^DfU`yH?(8+-~;5BP>doq>QX13uQ-01$IvOF9T(f^<#TZ+FJ;GeL5$^3#)e zEV5{bpUrLROM0z?*V9E)e?n?;YiID=);Bd*kpSjzo! zi)v!YjqRdeXi+WgWl9OQZ_6BHZ(HXRtMQ4&_ z(OG0!bT(NQokNyI=aOa7d1P61K3NuBK$b-plCkI_02W;gz@ke4Sac}>i!K9T(d7Uv zx&nYjR|2r;DgYK;4Zxyn09bS_0E?~zVA1seEV==JMK=Pl=q3Ob-3-8@TL4&eD*%gb z17OkZfXJd#WAWEaketPSLVcPnTILqr5lgvWZqePbFj*EoLY763lCkJ902VzCz@jGrSo9n7`{fpW5KB(B&pd~H(TB8`MIVu6(Z^(2^a)uOeM*)^ zpOIzJ=VV#*1z8q-NtQ)lk+JA&02X}%z@l#fSo9qLi@pb7(GLJD`VoLdKLN1lX8;!c z8-PW>0I+B+0E>PFV9{>?EczXQMSlRW=uZF^{RP0HzX4bjWTi*>(HJcTz@jWbWYK%E z_G0E;#TL>48p;#Zm=IoJ6G#q6wT zq~9YPuw|v(FSlrDR`SUKvS=9XWzlf5EE++UMa5)UR6>?TBgwL86j>IHCd;BRWLY$p zj78%BSTr7hMH2v6v>5=4HV0tQL;w~|0$|Y=04$mez@jMtEGh+H(Nq8yl>xA*9Dqd? z04%BmV9_)H7EK3WQ567-W&p5gCIE}70g*+UWW~QTL2~B%MaNBLk$*KaF)J(Oez`@n zvyyp(WKlisWl;lJ7B!M(Q4?7fZAq3zbI7u2E?E|BMV3WdlV#C1WGvbifJNH@uxNV# z7BvH~Xa@imwE(baM*tSh17Oj702Z|ZuxJ4QixvW~Xb}L576Y(oCjb`h48Wo#04!Px zz@lXUELsl0q7?uv+653wQt3ESm3U*DJG9?w4D%YgTg3MzUx(+RLKd z$+BnvS=T&EZUbWi}oYSqW#HObN~R04g_G)K>#c|7=T5G0I=v# z02Unvz@ozeSabvci;e_f(NO>_IvRjQ#{jVCSO69s2f(7^0a$bb0E6ltot2e5XRs_foA$Ek9I`Armn@6U zBg>-m$+GAIvMjogEQ>B8%c6_Pvgi^r7F`O!qRRkSbU6Tvt^i=sl>jWd3V=md1F+~C z02W;fz@qB_SadxAi*5j5(TxBsx(R?qHv_Qf762CA3c#Y<09bT80E_MbV9~z-Sac^K zvgnMg_yZ{87Cj5VqUQiu^gIBIUI1XxivTQo z34lc}1F+~702aLpz@paxSoAsoi{1cW(VGA)dJBL>Zv(LC9RL=+3&5iH0Fg!aWW_sd zY8HL!BmH}2(UJc7pZBv;?w4EiaaMB3Fj@2o?PbxYWLfkXSr&axmPKEXWzm;pS@acI z7JW^YMcgH?w4ECDV|(DLKfxFUKVvG%c3r1S=5y*i`FB{qFk~p$|K97 ze6lR+MwUh0$yn3_fJHq4SX2POqCx-`^#Wi~ZvYnc0bo&I02Zwez@mNtEb0%yq9Onm z4FF)#KmZnP0KlR_04&-NfJGYtuxMid77Yeq(GUO@Z32ia>JX2gY=Y$6;U5?37>`E! zIewC~X*}hAxkV%5$y-WfQ8DdhQ3+WVjU>yWQDj*(nk@M-0)R!804$mYz@q5@ zEUE%v(F_0<%>-akH2{ld0kEhBfJL={$f9BK_!}ljj{j~+Vz?~&&ikUec*^~9iyGs} z-$%)!CfduQEy=QI4p|n>CCj3%$g*f_vMkz$EQ_`!%cAYbvS@oU7BvH~Xa@imwE(ba zM*tSh17Oj702Z|ZuxJ4QixvW~Xb}L576Y(oCjb`h48Wo#04!Pxz@lXUELsl0q7?uv z+690`D*;%v3V=nc0g*-Z@p#c_v#8ilg&Jg$|1?ixO+4j(xkY=#lci&2(Vn!IMSGED z(cWZPv=3Pp?Ms$L`;leQ{$yEn09h6tNR~whk+JAt02Unrz@kF|SacWwiw*~1(GdVF zIud|IM**?M>(KP@px)y*%*8#BTdH@#P z0KlRf0a$bs0E=!0V9_lAEV>ndMYjR4=ym`W-2uR&e*v)QP5>6&1;C=a0a$boAhPJ} zc>HP;BxjskbdD^V?BU*c%KdVS9*ifSwy&~=@5Vkvds*}_Sr$D)mPL<}Wzl0~S@bwr z7Ck|hMNg7t(Nknu^fVcZo&jLdvj8l54uD0^1F+}?02aLnz@nD`SoAUgi(Ua>(W?L~ zdJTX@uLH2?4FDFs3BaPa09f=k0E^xMV9~n(EP4-sMehT!=mP*2eF%swx<4NO!34>< z-%qF?kVVV9FZw8+a=+Z7&*I5$lVs87w3kI+kY&-AWLfkTSr&awmPOx?Wzn}}S@a!Q z7JW~aML&?S=tlq+{RF_Gp8;6(ZvYnk0>GlR04(|yfJMInu;_OH7X1OhqCWvx^cMh& z{sv%?eZD&ywqsEYfJIpVEQ$lLC;`BtBmj%D0a%m*U{MD^WYH(__;?c}XRKeY{!|wE zPq8LCCQ|N~Tht|y+-kBc>PmZAv>sU&<&tGl9$6OUlVwpivMlOOmPI|tvZyCn78Q`O zs1Sffy#QF$8-PW909e!)fJN&Au&5sZi~0kws0e^X0{~bw5P(G+0I+Bf0E;#RV9`bZ zEZP`=MS}rYGz5S}n*gwAQvenX1z^!IKx9!)BEGK)l5?2%MV%ATNZ)@5Gci1oa=+Z7 zk%{DarLt%g?PbwuvMd@ymPKR9vS=Jx7L6y%q6uVKv>90zZBCX&6UkUK34ldg0I+B> z0E?you&5M(MNQ7Zt8767nlApnaO z0kCK>0E>14VA0M1ELsANrbOHd2P6S}lNdPQ58GuEn0I=v(02ZAFz@pOuSab#ei_QdK(OCd2IvWsKv}Yn- zXM*HR^p7|0C5tw&FT5tsNu=B_x9EaIa+m3{=tA1dqKn9~=wh-gx`Zr?E+xyN%gD0m zaSWMb`tc=mr25-3Y*l|7X1r=MRx+Q=q>;j-3`E^djME;F93_~17OkpfXJfr67f?_kep%O z7o9JQ_VOdz1BsOT7ClOPS@alL7ClauMNg1r(UW9Z^b}bZJx!KH&yZ!& zvt(KH92twA2Vl_)04#bDfJH9>u;^s~7QF(%qE`V}^cnz*UI$>&8vrbN6M#i;0kG(8 z02aLiz@m2nSo9tMi{1xd(FXu5`VfFc9|5rFV*nO?0*EYnC=q|l1j)J34`L6?qW65H z|7jxSez`?oCX#>JPpO61i@u`0Ec%)(i@qVtqHoEv=sU73`kpL{ejv-DAIY-lC$cR1 znT$pM24K-I04!Pyz@lFPSo9kJi+%@S(H{UT`V)Xfe*v)QZvYkrNe$bvCN&&E_0|1LU0;;sa-yMfdm-?F(5n%#UcDlPUMh zEy_(M%W7p&9_?jOK3NuZBg>-hWLeaMEQ@-QWl;fH78R0ZQ7^JA>P^O?J^(E03&5iF z0a(-zfJOZQSX2bSq5%Lb8VJCm4FFg)2!KT!0zNkwsmT@kJ&`PQ8Ebdc9;c()a&jBT51EZUqbizbp~(Im1g+JY>LCX=yf3IK~r0a!E@fJJ2hEGh?J zQ3U{tDgjtD4S+?{0a#Q8z@ixdESd?xqG|vZ%>rOi4FHR30a#QAz@pgzEUE`!Q3C*r z8Ua|;1c)pem5g6&g5bKT>x0L5`aak09dpdfJJKnShOnui*^HG(e3~&+5><^djcYh<|gAm znIJh|_^HrVvgl6li}p&U+%LCizhttf02Un&z@ifXSac!)i%tSy(a8WT zIt745rvk9(GyoQz4#1)_09bS;0E^B7VA0tCEIJ2(Mdt#r=sZAV(LTxeW+q6^TpyP0 zD~oddyy*O7%KdVSE>0%5nJbGfp}j1+lq`!bBg>-8$+GAQvMjoiEQ_up%c85vvgjJJ zEV`DAMb`na=z0Ja-2lL%8v$5!699{D24K-G04%x{fJL_fu;_LG7Tp2BqJIIf=uQ9@ z-37p+y8&2q4*-kq1z^#A04%y6fJF}gu;@Vm7Ci)rEV?im-`@nudB#Wj7s;YW?Xkqe z$&~x$7CoL!Ua+++dV=<{=t;6HdWtNIo+itpXUMYXS+Xp8jx39wC(EK2$g=1~G8VlA zz@nD{So8`2i(Um_(Q5!KdL4j8Zve39O#l|X1;C=W0a)}70E^xQV9|R3EP5Y+MIQjL z=tBS&eFVUwj{#Wp2>^>e1z^!<04(|(5LxtSGX97OlGD}uqQ_*>G(Vz!kxaQ?ZqYZ% z}FpUJZ5-(*?z3t1MeC1cUA04(|qfJMIp zu;>o}7X1mpqQ3xG^fv&Df@}@ju_y+>qAUOw#Q|890ANuPfJNB=EJ^{er~?3tIs&k$ z699{H09e!+fJI#ZSkx5|S@cyh-g!H-$lrHOd@YLx`q}k**(vwSE$Wt?9M&w0y3<}3 z^&rclo@7~6K$b;?WLeaUEQ@-RWl^MeCEXs2>1}`U9}22!KTc09Z5-fJGYs zuxJnfi#7yc(MA9)+8BUEg8^7H1b{`G0I+CN02U1eV9_uD77Yhr(Fgz*6$7xS1b{^& z0a!E&5LuL$9j`Y*a(?i$>-_9!q`$Qf`$uP|+%LCie0FkGi!7Qzds(y@Sr%tm6B!AR5BKo0kEhXfJGGmEUE-x(KG-SO$T666#$E70I+B# z0E?;tSTqZOMKu5{ss&(C9RQ1F1F)zbfJF@eENTQ`Q4;`*wgh0&8~_&01w#MP~xA z=qvyhoejXEa{yR$E&z+p17Okl04%xyfJGMqB8&FVjt^R37Ww}Woj5=iEe{85*(vwS zExIf_S+PhKT~2#hbOl)!T}hTjSCM7W)nr+84OtdlOO{2~k!8{KWLb0r8H;WNV9`wg zEV>zhMYjO3=vDw0-3Gv-+W}Z~2LOxy1;C;^0a$bw0E_MhV9`AQEV>tfMfU-)=zahe zJpjO>2LV|05CDrF24K-604#bG5Lt9dc6=ujBxeghp}tfWUFL79J(itvzucmyvXe*c zB#WM=y)1f$EQ_8c%cAGVvgmoTEP8<~i(VwlqL;|B=w-4jdWDQduL7{>H2@a94#1)} z09f=U0E^xNVA0zEEP4lkMehQz=sf@yy$`^m4**#7Apna$0$|a{04(|hfJL7Iu;?=Y z7JUxDqAvhg^d$g`z5+xRJ&_&1-UP{6&rhhIltq*Li1u}M%KdVSzRylRzeE=OKzmvA zBUu*xM3zNAlV#Dr$+GAdvMgFlmPNmkWzlbBS@b&@i~ay$(VqY;`U`+Xe*>^6NNL!P zMKJ&tWdX1#4#1)W0E?0UEXoF8Q3`-X9ROI=5r9RV09cd*z@p9oEb0QlqOJfeS`UCl zxd1H614I^mn;rkR36is(_eI~yqQBx6@>41I%Ps1eN){}aMFq5%MTKNp)Qc>OdXr^Q zAF?d!OO{3JlVwpqvMlOPmPJKmEE)j7qJaP`+5mt>g8*2xApnau0$|a`04y2|z@i}l zEZPKsMVkV!Xea=Sh5@i>H~@=A0I;YSfJG$$EE);GqEP@W8V$grF#s$Y3y3W0o{CR2 zL2`EYk$#Ulq`fSfM3zNckY&+ivMicHmPMsxSu~X_ zi^|BdsGKZ|D#%z=3BaOh04$mgz@jPu7R>-)(M$jqRRgeS766NC09aHDz@j<;7R?4= zQ9S^Q8UR?-2*9Ey02XZtz@j+-ESd|zqOAZ}v^4;WwgE&IO-RKLG(mFSv6$FQ7X9RX z(YC3S`{fqxkV;;(N*1-yUKZ_0mPPZ(vS>b87PXRP(E_q8T1b{fi^#HQF z0a&yIfJI9IShNg)MauzLv;u%dy8y6gB>;<70kCK_0E^ZDuxM8R7VQSWqTK;lvG>O_oK+kY&-aWLb0^8HY z7F|u2Mc0sJ(Y0h*bRAh1T~C%pH;`q~jbvGL6ImABOva*H09bS@0E=z|VA1UWEV=`L zMgIa|(VYM+x(k3scLT8K9sm~I3&5iL09bTC0E->~V9|pBEP4olMGph8=n()GJqp00 z#{gLLH~@>D07MpDo{Be`AUV(ZcVn-RMW=aR^kgdKez`@@rjl#+lts_cUKTx1mPId+ zWzmadS@aTF7QIZCMX!)$(W_)x^cqa02X}?z@jezSo9?Ti@pM2(boVh`UZeS z-vT0wo=(NjG(mE1@Kd2@WYK5d7k!sXxnFM4PpRacd&{DqX)lZZO_oK!kY&+YvMl? zBHjE;mbg+qI;7k$x2RW#WNbfK)SLFQs1I2d^(D)q^~tiRA6XXlC(EKDvMd@v zmPG@}vSa|JL2_>LcR&g|L?its zKca2cA?1F#MO$=8PCGyrO{TppnnIRErDRz&l`M10vZ#_Qi>8rf(R4Bv zRROSQ1^|m@0iK1 zTmTkr1;C=M0a&yR0E@N-V9|B}EZQCrSv0Xje2EE?vzLoANfy23eNl6Vl>6lt&Fhdn z<{()#pZ2n-l`M-EkY&+AvMgFemPL!nvS=r=EZUhYis0ASHB z04!Pwz@k+EELsh~qBQ_4+7*CB{||9@0vtvCu6w*YlV&=ZEHeoZHZ^PlLRNNU-vk1( z$|7h8A#4JHBp@IP2qG%72nY(YqqqXDsHh-_sHlJ-;)*+7ds-)|EC=bk!s zt4`HTRrvMuOm|OD_h)8$CYf+61&XFnplB)uil$MZ=r#%zO{YN7?Gz}wg91e}C{Q$$ z0!6bZP;@5+ie^)IigH}vvjQa0+MEgvQ$<;Z)Ew7ud>KXaT<4>^RM9;wuZr#^tD^hJ zs%So072Qu(MGMHPXdzh@Eh4L;#bj0V02xI~C{VPN0!7OxQ1l=Lik4HLXaxm|9-=_e z!xSi5Nr9qO6exOx0!6DSP_%{uMQbTgw2lHr>nTvQfdWMvDNwYD0!5Efpy)9Q6m6#P z6wP&g#R4R--4-}^tD-@M)Z?z-_%e!~cAd)eRM9gmuZp&iRnbN*J1J1KivmS& zQlMxz1&a1ipy(|M6z!!z(c2U#+DCz+cPLQwE(MC-qd?Jq3KYFh;VF93^|cltf$Jqk zKBbC=nP;>QT)**U6diJ%?0Z$wM=Y<34wF^U5wa@!n5>G9l2y?sWL0#GtcpG*tD?`y zs_1hvioT#g(U%k``icTY$0<kp+M2M6e#+R0!80bpy&q*6#Ynnq7xJ-I!S?| zQxquri2_AGQ=sTH1&V&5K+&%hC^|!dqO%kzI!ECtI^g=|2oQPj5jY1`k!w!1e{=oD zmr?YG>uj2@ii%lY75zz8MHk7c=r6J=xG>QJDlE(MC}QK0A=3KZ3+Kv4q< z6s1t0D3t<5X%r|*r$A8#1&T5$P}GnDMU5y>)R+QAO(;;*lmbP~C{Wa#0!1w-P;@N? zids^5imF8Uf(u2_l5zs4YLxd%|3?#AMfr^{qo`e!ld)J8wP$%%)PbyuI+9gUC$cK) zOjbqLkyTL_vMTCIRz=;&swj($qV5zZ>Op~`>nTvwlLAG(C{Wa!0!4i&P}G+KMg1sH zbOQy7`ct5200oK$QlMxM1&VH@K+#|d6b+$3(M=R6x|sq+*%T-mN`ayr3Qtj+C|`d8 z5_sG^{Ipd?J;N{9qWs2}Q8XgTxpj#u8p-miXcSo$jV7z2F=SPA3t1J7C99%wWK}et ztcvo$ze)3dNH}lIz zcSre+FQe$bDCf0hs%SpTtD^hKs%QaO6)hyIqD5p?w3w`l9w4itC1h2!l&p%Dkx}#@ z1&WqaplAgJiXNgs(ZdudT1kPTRTLnP_&K$Me8Y0w1EOe8!1q< zi2_BBQlRKD3KVUoK+)qAD0+edMNd+AitdT>eIq~uog_xytBS5OFZ-X0@*7`9(bg!( zw?Y+dV|i8dELjyjM^;78lU30RWL5McSrxrRRz=&%s_131Dtd*CqE{(Uw1WaguTh}r zbqW-{L4l&36e!w7fuc7lP_&x@MSCbv^cDq*_EMneZ3-0aqd?I+6exO^0!8mpplCk@ zir%L{(FYVL`j7%e2Piy6&qVp^3Xs5F^G4$qRaD=+MmregH@=LbBT-J*hgH$XEU$`= zl2y?sWL0#GtcpG*tD?`ys_1jFD*A$~ioPVPqOZs(I!=M2uPIRU4F!t6r9jbl6e#+h z0!2Sipy)>m6rG?z(MbvvouWX|PZTKnnF2+pDNyta1&V&9K+zcr6rH6&(K!kf{YHVJ z^Asrhox)S}QIv1I00}&5eoO7JDss%<47m{HH@=Lbi&4(PRjTMOmRCiW$g1dXvMTzA ztcos^Rgo2~uiRCUO;$w_WL4xNtD;CUiW~|Qm7_qBp8`cL1&X35P!vspq5uVoVkl4) zOM#*|3KYdtpeRUzq7Vg&5-3oVNP(jA6ey}dfuf2OC`zJ0Q6&l#Ri;2u6$(#Lag^_Q z0TSqH&Wrw3Ma#`&QPpU_@nsZU73~~Zt%{OaUKLd*tD+iYRaBF#ifWNnQEjp+x|*zt z>X21YU9u{wM@G>#6ey}sfuaT!C`zF~Q7Q$B(kM`rPJyBf3KV5hpr|1QiW*U%s4)eK znoyvqDFup}QJ|Pdm3UKA+mO@X356e#LTfuepCD7t|HMg1vIG=Ks{11V56hyq17QlMxs1&W4Hpy(zF z6x~dLqHGEj4W&R)4h4#aQJ^T70!70qJVouJeQgCu!2G46$PTLLaTD^Q{l=G3G&+_RWyODiYAg(Q2|*M6_Qa@M1i776eyZZfudU} zP&9=CMN=tIG>rm9w^5*IIt7Yur$Esi6eyZOfufldD4IoqqB|*2G@AlNb0|=B7X^yu zQlRK=3KY$wK+!!Eo}!V_zPSPSrt7y6ewCl zfugk(C|XB>qV*Ig+CYJ#jT9)_M1i75DNytn1&TIPpy+W56g@$Kq9-X(^b`e(o~A(2 zGZdbp`O&`p0wi#Ud86@u6q#50TcZ8Omr?Xwv~&6~RrEZ|tD+aks^~?sDtd{minfzg z(aU62^a@!Oy-HR^JIJc&H8P4`r$Esg6e!wBfuda$D0-6uMY}0bw1)ykZ&9FVF9nL; zra;j?3KYFVfueUQQ1l)JiuO~W=zR(leL#Vt4=GS|fC5DaDNuBX0!1HDc#5_~`w}*b zqDb@G`_HPPONP|pXut7g6nzryG<-r89b4_LSzZ;@BCDd>WL0!ESryeGtD?GORaB3ximoB6qWWZ2)PRhl6bcljQlKb}0!8T* zD9WHfQ6>e78d9LB5e14GQ=q5`1&W$dpr{!IikefPs09UzuBAXxO9~XVqCin=3KX@W zKv7!?6t$y3QF{tcQF6fdod5~cGVeN84|uQiKQfO+9Rhyi%P6`o;5gePLa18z@lJp8`b#C{Q$z z0!4!;P;?^&iUw1lXb1(0ZlXZZ%@iogra;k93KZo~plBEcigGDXG@JrOc@!ubL4l%? z6rQ3^0pB$OByf%S2}oyEbe~)nIV#{czKo)=0VnG@RWy#}Rnd5|D#|CTq6uVGG?A=| z3dpLckgSS|$f{@(Srtttqv%!&6iuN((Nqc)O`|~3Z4@Y)PJyD^DNu9=1&U@+plBuq zie^!u=uQe0&89%n910ZOMS-HZ6ezlz0!8yEP;?IkiteRA(R~ysnor>=8WZqM5Fmjy z=EwNAsG{BGf$9E$-}o|$76+WgFQ}piSY8z^A*-ULWL30`tco5atD@y(RkVVviXI}X zqKC<EplBThiq=!0Xafa`Hd3Hy69tMMr9jbR6e!wE zfuhGLQ1k=^ik_rE(Nh#CdYS@7&rqOf3k8a{QlMxXg{Np?!1tm630yQk0a>Jq=9y=- zX9IrY%P4v=;2eEP6}`mrs%Se|6}?PWMX!)m(W_)tw1cdQUL&ib*U75r4YDfQNk-8w z3KYFbfuh|MDB44TqPHkew3h-!Z&RRX9|elup+M2Q6exO+0!8~NQ1m_piaww~(T5Z$ zIzWMML$rW=tl|^ouEL` zNeUF5qCnA46e#+c0!61OQ1lB0ihiX)(HRO9ouxq0ISLg0MuDR96e#+g0!0@nQ1k}{ zii#;v^d|+1E>fWAFA7i5v4F3=00|_=2%Jw<(d~xRrGVe~GK#DiCwGS`vSaj>yef(y zt0Es+6-AO&kwaER<;beYPgX@PSrtW*RZ%nX21YU9u{wM^;7GkX2EA zvMOpoRz)dfRg_9rMQLOdrBk3Ng91gF6ewy)fucqfC~8cBq9zn5YD$5kW)vuDPJyBp z6ezlu0!1w;P}GV7MXf1N)P@2@Z7ERHjsivPDNxjb0!1AuP}GUSQ&cm?_kjQjB$>ye zS~1=${jnx=j`15`Mp3sI=hvO8D2wG)QFpQ`>OodT*OOIIPqHfNMOH<<$*QOiSrzpq ztD=5n6x~39qW%;p8bE=fffOhjM1i6kDNr<+0!2e8P;?Uoif*PrQ8opNhEkv?hXO^z zC{UD3fui9QD9WQi(Fh6@jif-)C<+vfra;jc3Qtj&7+?8aqR27tI(Ah><`2$9-V)nWqC&DNDk7_*Nn}+tnXHO#C99$-WK}ekjG}22D7uXT zMbjxzbUOu#?w~-?3$ZEC{Xk) z1&W@dK+*FQo}ve0d}{?rV77VJafvEQ3cp~B@f%-8(aSN;uD4auD=e>yUL~ud9b{GX z8d(*+PF6*4kX6x6vMSm|Rz+`;RncxTiuO>T=q(Bq?WI7`+Y~6;M}eYuC{Xk+1&ZFI zK+%2*6unP@q7Nug^dSX`4p5-zAO(sJQK0A}3KSitK+zEj6n#vAqN5Zj`h)^S$0$5S zFU9zN5Fmkj%)`%iRdl6X7Wrw6-}o|$zLfvZ`dwA@70aul<78FzHCYvXLsmuKl2y@n zWL5M%Srz?2Rz*LORnZADicV6X=oAHtexg9p&lD&+O@X3cC{Xk(1&Yp4py(_Giq27> z=r;-!ou@$2?-VGyK!Kt^C{R>PfucVtP;`+3MSoGC=n@5r{-!|DKNOy#&trTI1V|vs zyzBUdDk?CKMVDjz#+Om#i*U~1&Yd3pr`@`iYii|D2W0^l_*eDnF2*sC{R?D z0!7s*P;>EN~SVg3Qv(8>nji-ffEK!M6CB3Em1CutQG4w zzKo)}vCfhYR8c*a*TxFr$A8$ z3KVsuKv5?O6m_OR(RCCk>O$cux;oakU4R7Y88~%R(Qxzh)-~2|d>KVOVx40LRMGV; zuZnt-RZ%apD(X#EMSaMss4rO+^&_jI8_24tKUozGAfsp?1&Rhypy);l6b+_8(GUt0 z-9&++n<-F~O@X4J6e!A}K+!M?6y;K&XgCFm@+eR=f&xV&DNrxo^ZX>Ir>0}h$PJyC3C{Q$m0!1?^P&A7IMR!u5Xf_3k=1`#M zE(#RQr9jc$6eyZUfuegTP;@T^iteL8(R>ON-A{p{1r#V+NP(h76ewCufuaW}JVg^? zeH{fzptJcU*@>#?0rOb2B-U?y8AZ!uoxCHeXa&owqKC+;=wY%dT1i$#tH`S85wa>; zO;$x~$f{^9Srx4#qi8(^iZ)Q7Xd?xRHc_DHQ3@12MuDQu6exO}0!2?ypy){o6g@?O zqNgcP^b7@xwossGD+P+SQK0Bq3KTs@fuiRrQ1k)?ie98Z(MuGbqGhqZdj&|~uzA<< zK~)rK9+$g1c~vMSn5Rz-Wrs^~4U zD%wj%(c2U#+DCz+cPLQwE(MC-qd?Jq3KYFhfuav6Q1l@MiVjeq=pY4(4pE@!BMKB9 zra;jV3KV@zfuf@nDEfo~MaL*m^eF|3KBGX<=MH zbeaN1zfhp)R|*uJp+M1D3KX5AK+$g$C^}DpqTeY{bb$gze^8*Pm;yzAQlRJ}1&aQn zK+z=%6#Y$sqJJn*beRH0R-C>tN0Ck8Df%kbSMgI(w9`Bm9alwN%`;j=oZt8|ips?~ zO+QyfewJ57E?E^tkyTMNSrrAyswjr6iekyCD2}X(;>oHgNJdeJ0!0ZFC`zP2QF#g! zRiHpoMG6!pQJ|<21&S(Dpr{H3imFnes2T-|uAo5Cl@uttiULK+6ey}rfub4|D5^<; zqFNLvs!f5St0_E1k#W8u0wmxXI8L1RN?)GPc=^^f2oQZu)HctA*-TP zvMNd=tD z6$Oe~Q=q5~1&Z2Ipr{=MirQ14r~?IxI#Qsh69tMoQ=sTN3KVsrKv7o;6m_FOQ5J=# zs9v0Jy#NWEHSaoJql#J^Qr+YH#+OmlE6&+{Tov_Zc~#Vhtcv=QRZ%~(D!PHJiu#jP z(Eze48c0?}gUG7rMly;9Q=n)F1&VH>K+(+lY5qLCCR8byJk(G(~eLxG}OC{Q$(0!8B}P&A$bMfnscnn2+xx<1Z#LVyJF%Ck2XTQ=n)L1&Z#XK+#+Z6x~gMqInc3x`zTq_fnwfJ_;1gr$EvD z6ewCifue;JC|X2;qQw*_dVm5&ODIsZlmbP|C_F`lalTXm5?E;-i;7fHra8NQFwSp$ z8AT7rIX%BuMJrie6|EwxqDRQ8Xf;_Cts$$TwPaPaj;xB-lU30MvMSn0M$sk;6g^6T zqQ@vuw3z}$k5i!N2?`WFNr9rLC{Xk?1&W@bK+zTo6m6wI(KZScJxhV2=O|G0JOzqg zpg_@!6exO$0!7;?Q1mhdie91c6s?H!6$y~Qqvpl^L#pUc^H}t1oZt8|ir$EGmi?%T zcCx%G+C^4HZ<1BfZn7%cLsms^kyX)NvMPF;tcv!LRna?S6unDp+M0w3KV@xfuheSQ1m$k zioT#g(U%k``ijC+^je(n6#){M>=QVztDfWAFA5Z0qCnB#6e#+K0!5c8P-MmH%XSpm6ex*pr|Vain>vtD2oC`-6>Gig91g@Q+SFR#QWw8kU)e{l%k3nn$R=eZ+sa= zedC>{�n)EU$`gAgiMOWK}ePtcnJbRnZ`_D!P%ZiUyNa(GapKx`~XUn<-F~O@X4J z6e!A}K+!M?6y;K&XgCFm@+eR=f&xV&DNrcVO4h4$tqCnAH3KZQd>KWL#5>J@S4FE?UKOn&tD?1JRkV(* ziq?}=(FU?A+DKMKo5-r@QL-v}jEthq6exO}0!2?ypy){o6g@?OqNgcP^b7@xwossG zD+P+SQK0Bq3KTs@fuiRrQ1k)?ie98Z(MuF4+D?I@mnl&63I&Q@r9jaR3KYFY;VD`f z@4H!m1R9ygqE)KsIrA3e>+yc$%P4v?-kI@-D%#ERs%Q^c6}?4PMSIDr=xwqp+DBGJ z?~ql|yJS`L9$6LbC!^?n3KV@nfuav7P;`I-MF%NRbcg~)A5oy_Fa?T^P@w2z3KSis zK+z`@C^|-gqE9JM^ce+;KBqv@7ZfP^k^)6vQK0BJ1&Y3=K+!i8o}!)czKsGTu-3dR z+og)8n8%`TLRLk;l2y?e zvMM@DM$tJ66#YhlqVp6e`kewr7bsBl2L+0XDNyt$1&S_Gpy)3O6kVb~(ccs(`iBBV zmnl$W1@&b+ifjrLMNpu~M}eY93KTgMC@M#RB0q(v==*rzDFG6A!u)2)52|Rhc`R~+ ze&fq1iU~S_OR6ZAG#+Ol)5p;V0qlz+F zUKKSYtD;6^Rn(ZQikgsBQB$%iYDQK?&B>~$1z8ncOGZ&k3KX@XKv8Q76t$s1QCkWW zwWB~$dkPeFpg>Va3KVssKv8E36kSJwqAnCD>Pms4ZWJiWqCio13KaFAK+*LSDC$Xp zqFxjz>P_J(N(=fX3y{EI^H`Lwifr?Y)+gvUzKo*&L1(#TR*-H*4q$mzG?1){29Z_K zjbv3cn5>G1kX6x5WL0!CSruiIRnbr~igGAWG>ig8xfCcGPJyC43KWf?K+#AF6pf-l z(P#=3jiEr%EfgpkOM#+s6et=`fuej06iuK&(L@Rq6;Pn4kOD|?>;_eoWM1jt8uS}qM$v6S=ZgqcG@a#D(d}eabO%`#%^<6ynPgQoi>!+7 zB&(v?WK}eWtcva;qi8M#iteUB(L4$i-9v$*dnr(K9|el$Q=sU63KT7%K+!@96fL4a z(P9b|JwSn?B@`%HN`azf6exO-0!7OyP_%*qMGsM+=wS*Jt)%c2O%3`Ye4^+f^G4$| zRdm5TFs%yujW45UZP2MHe-0x2ShSAiRndB~D%wC+MH|VgXcJi#JxW$ZkC9c;X0j@J zoUDqTAfxC>3KTs>fug4=Q1lE1indUoXe$MZwo#zySqc@2~&~Dr!kqMXkuHs5KcyZ75LGmI6iXC{Wa%0!1AtP}GqEMV%;6)R_WB*HNIT3k8b0 zQlO|C1&XpLP}H3QMLj4`bUg)%dQzaM7X^xXQ=q611&aDopr{{(rzkVz8!A8o4b5w` zhN@_`IlI0gP~Rg^$XOC{Xko1&Us$K+zi%DB4MZqFody zdXoZ0yD2q5Rv0TLK(etUntDym{0i}r;4#+OmFFXZ%1Qbq5uyefK^tcuR}M5~ycBJoL6Ix+s@Lo(%boFQe#m$a$!;D*A=xRnf0xRdj}|iq4W%(K)gz`i-oL z&XZNq?_^bUfvk%DAfu?50!4pPpy(n6ivFTN(IpBL{Y`Og^_ zjua^BM1i8t6ezlm0!3XYP}G$IMcpV+ltqD}?i48ML4l&{DNxjt0!6(jP}G|OMSUnx z)RzK9{U}g$0|kouQ=n)7g{P=-g0GtZ3Dh@mny8|2=CNpCg5UTuiiRXOwlqBqVW_c%BMil1PT;Qq(D&t1&RtOP*g;LqDd4enoNPBTPaX9g#txWDNrOoI%HYZf_2JUR&sD$Ma!xce6EsZ)eZhx#j+X%+gxE;>A}0MvaCkI z_o`b~vtX!}Wwi_rxZ1MX1|O+wSsjDlUSnBZg7s1?t9vj%&9Zt0U&yeme!;&QTGqf| zyC#-3BzSi-%NiPdzlCKD4<@#vy)SDZz`7bdJ1Sd_iti!=qr(4!1L3@T}eIC4SmSr6e-ap&2z6*YImt~y@ zR-R{BKL@k#wX8G2P4g}5eDJ3QmQ@_gSZrCBLbooF{cnd}TP6p<4*6Ed5wJsDAC^O4 zhZe4qV_=7ltd@gdhpMiVqhN<}HppSHLyv8e<6wu(|7Ksy4w?UsysjNG|DSXNJ7oSt z;B-4={zunFcF6pfoXzZz`9Bp~+9C6w;2}Eck*t|^$o!R~Id*9GaXCVE$o!p=`F6Cx$b8a&sU0#O z)m~wT%x7&^*&*{`$+dRKeA;cJ9WozR+H8l+=S`lnL*@emTkVkfjqm5}kolF}?RLog z&gBj}WPWLGryVlC^|Z$hnO|GkXNS!19qhM5<_E_I?2!4%-(fpsesuGR9Ww8|e{P4& zo2SR^ka_p(J3D0FzBplr%a_%iqs@ zKFur`Q~AWM!tjEhJ^DafS4zPPG!HzbAZV3K7;)UpDB)>2uPucGCPYZ16M&^*vJQ4XJ8A_vE5Y?-E9 zyv%DR{E2oT;LT}EbYm@_%YuPGY#=7kO!jhA(!b`4mbuETKA_R@t}RAaDbcJlR#zFm zv~-nmx=NiZUKVmnw<8!Un`y2&6rM1*TyK(INn)zqrZO8*r*gs_uOgAj?G9kYpHbaowgNGX>t2XmQ`6Uu*?OPRmGcU zS^LT+RZX?pRBl;$d|Y@_WZUFum;DM#u;qC`26=Rr$$n-S5}q7l26Hcpw0^UDt_ zUonzxtG5|WgeUu(fhBtXUzV^eIry?nA2aL?Pu^gLL-OsjCPl6>6Re<5$qFKDTNW~3 zedIgBN?&6}vw0C#qctzeXzrS_@$zr@tD5|4o>$Gb^JP|B_N#2ZPiFI3IkHHE{a0M9 zWy_b$E8li%YFa@~+K9plX@v#3X$9GZxp~6lM3<* z%UovWm${p#O(+;WZgkP;$$3`VsQhtxX*px_rlh5g&Cksln^rg~rywt_Aa8tLVNPLM zUS@V-(WK#{^V5p*^T+0n${9VrFl}URZgx(=xU`J)?1tHy>6sbX8R@1>kuqg`{`kC< zyqsa9Q!>(18>X0xQ|01+U6eL@eD2su!}HR{<>ZbUJ^uguW)w~>EW0O0j!J7+FnrSJ z@%bI{3-VG*_QjN@{{$VRoN(O?ou` z-#AQ@bBglJ-m)w`&^e7JrREw3*~9ZjFJ5J(%_vP5-d?RHBU*%-S_Ki$7Q!SH| zlgp(!3FQ)<#1zLVmnD-jOSm#)E6uIt?9#5_1k50RJHrezUpS`9Y?)57S*(_mSS`G8 zVt6I3oc|mvn04Atu%%PGrV|xjOHId|xynjw>q^5h)rpdo){=RX%w*dCG?{J|uE45l zm0eYG_=+NAb#&sb9n0*&m0N=-5leX zBQe#f6TTLoR29sWZisA9vag~X4e9K1HQC3>;i&sqE|u-ST4t@B>Qpx=Eu5;Sn!R6L zr~hLzO%8aX3MUCV`XJan=V*VeIg zx5&=WOJ(D|9V%<_CdzC~Qx=uo7`{+;u`buRWM#5tTxq7x->`H$I+QGt(SfUy4c8@% zg)&bv|632O9rK1w8tL5{ITCVR@@QS=Q0R6vD%~_W?B47pw*_D6r8lK{$!2E=T`Q~8 zpzL-X`&j>*&$v8cdynJc`&G%6%6&rjTE~BFlQlMf{K(|+KmWyTM(Is#uQU-X8p1aj zvIeEz#dOb=TuZ0$TE>{WVfdnSU6tG`bc@=TY@50Nhi7V6vUo;EXf@Q!O02OF8O=&o zl~KwWe(1|6^)0tXuNreDy5yn8y8)$GGeoP`rE_7a-;B;2{8F}fkQ?DG$AmfX;fFcJ zlWm?yM@$-@n~|O#zCiDHW%>+nfsE2!RK`?OT^~os<7%#o5+Tg z0_E{k_LjGO=3=uV8M#4XHe7KWsSd3!fU_Fk!fy`t+UTJ%RCTWFEQn>SUcX z9==G9z2u&giaO>L&K<;SaZ7>HhOip%>H&Mn+sgaCQBpIbj zI7At;vEhZ~6d^ov2r>k`x7IR8xb%R^mFv#Vkdqp3M!7@lM9J~W@D8`x%rZ|F8M=fV zW?hN*Xm{Q9Hzapx-aOg75=zZTHm`-!n`Jgiu3L~dHZP|zuU>M>xZDYoTII?f%bSui zu3*E~O(AoRm@v6UMl zE_Ix|Hmg6pa6G%~zd=G;|JXT!J9y9busYVL6*u3>G?VQ(pU)Z|pP^dz$M95O>6Qq2)k>jpyj z+Bt8{C^-!+IpZvIrz*W`l%6ljgIIVKrDuyJ$Iv_Fw65#Wp+$0Cb2n;NFfO^%xM6w2 zhs#NOKi-Q7-?Mm+q27OgKa;mk%$q`&wUhT3tsL`ahGnP8q|+>=M{19DU9Y#wh5S9De9>+~WO=)So#d-zSGKFz zRqbl_l@T@UR9WADewD2vt+SWQUhdO3ljwZK%U&*`9Ug@*sCp=}oeAd6;mXjYmmATZcFaAHWx%Sd8pC#|~mHF~n z31yO5zJg`mBR2cQ?E3_{J&nrDVcz{~{~x*6e`Mav@J^&_6wi5#w#nx8^JP0m>-ClQ4WH+DWdNy~$ZR=E!X@d7O@q%Aq&;IURqN9bodGI%dkg zGP#Y8Q!0A-E*)Q&cZbd8@97v>)yp9ryUC9Y&E*4hTy&L}AJOq+*|FyGZ*{Cz%ggn2 z9Co#r^L5-T2f)n#f{wpj%qC_VPL%Kke(~A9YOb@8uL7M-23Gp^i_<`}5}ZysYCn zc^BN|%Q`m8_Hrj3@5u4;eLC(D=w|+dI!2H1a*~d{MtS)r9UmOyvVraDeI;^o_QeDSE4ck6iRn3tnI^~Uy}dt*->=Y8qrWjcOv z+{>ToSpHitSJ&~z@4Y-y$F)Ct`Dq=0IO*lzbZqdmmz(QY@Qasc=(zoim*3LypL1Rg z{N{}vfA_}TI^O$-mzV2!;7>1qp<~5MUaqO*kbk^9TF3QrR$;tu(eXrtmw(qWRes)K zF27dCBEOes>G+ELN`SfiZ5`#;F2Xrh$IkLg0_O6*I?k8h7BKlC9S_N`4Ve6uj+Ny1 z2TZQ5nw_c?SNr2TNsqjVgn{S?j9b)2RBe9en=T&Dec9k=MXL&tY? z{8-0tbv&cv-#SLikN(Z}C+S$rjI#X$b7Pst~&P8v7e5Eb(E*M@cdJCyj{mRI?BU*_;Pvp4v$N8T&3e$ z9k=VaL&rTj?$c2oF2c(n*0G!!RDN)%bC=3M|Qby#7cl`8LBq?$7Ie|mE*Jm+xpCcXTOWJJEKBs`rnY*<0w zWN$rQBR_O58*>VB#*fU?Yx3s!ugzHVBV%2oY^s%-D?j4QlON=ixz-T{Ipbuec71xJ z<`fkbj2m z>rq*snU60ndr*q9>nkp^zF4`8^*triEMwO3qO5PBxlq5jY_sID>vOx=;p1esPwti_ z>ofO%vyAazzB;Ab)~)8jOTWxz=6kn}%(tVZZFSRm%)opHbefCYR`$QFvZ?!JhO*li zl%;ffdA=6@cf(+rWma@JU1R2fsnlCeQUom-#%r{g@^SEo?6)@{F>o?aa z>nr*Cq_u6`T#`!H7m}{*e95wXr~fbW>90BrACa1$CcmbToY6GBNwf6KW)0J2Iz2t3 z%)d>VG%_ipY4c1o=g{aGow|4Se&NPju`RFSxjm-Yeor_#-eW>ttFqklQcj-fxx4%9 zt%r+uOpIBbbml65+cUAVujt(4LPX)7;yLM~YR>9>Z|6mw_Y}Jm_Y_BFyqvYC_;~tZ znX>Bt_35!y>&05>dT+`aFYrB}HYv*2_&A2*ib+Bx*R_K%BNF7}rV}f55N8V{JdsF6KnDwSCCv$~wrxm{LeZ`h-uBlJWebUd%n$&$? z@t%@>;myt8B`LZvqU1lrHchyXAHr-bHRl*)_BuSaWFC_HtY52KUMGH+M7tnp@a0 zYhRh|@ag^^AnUev_3t*I>wxgSHrvrZt2FmKQ{L@xA?J>s=O>J<*ST+2gKjm4_LXHC z%yfRAIYGAW>pjI=ca}XWfl+3y*>i(^{OYVS?CExj=^Jf1vQrHgOWDsP_+?s=wG zT-$RIHMe%o==@c2@ml%bd2RQEZaYO+x!-3_-C1m{-C5k=_|D=3J9ifEY1?6F-%$gt zOGggLbz}`S|K1n=_r37H?TUkK?&);;V9)d0bNddnx(zsP1uM2qw(Ob7^Q~sjpKU+n zyRnNtNE^}o-46%7GJCDhp1HKz;LAHs58A%!*h8((Z_Z6C|NMqNPkr;(O>dp7{ZP}Y zJvTV=U!_L6jx{I7-2LpCLqC1wZ1d5*KYYbseQ3Sh^PvrEUa`|}KKt_SUYlk-p8G|I zZQ0uw+twT5nMc+sKV#$O&+RvNJy>CB_q8u=%N_Lnb)5#?zkAb)s8=pVPxEEi)?@D+ zuwJ_Rc!aN}tUlgq+jq>$h)ajNoZIE=JM77BeaEbl6j^ggPN#E`(md8}$>@R3rNbRB zMEW*%?>lV6=t0iz-)7dhczAuzx~z5G)^}YWK8`hNn0>moYxSYu3^Vtz1IcUT-#y8> zLm%v(J8H1(zr(WU+_OPr(EC84qO5 zl{H0%${zD0vV6}oGdr52d_=6>+r^u5Gj8kZO~r&wv_F@a_-65ewr>{iu@dFJqz3x5 zJ(o~(LicxbvWDh{kFD9BY2Ee~M`oI-sa^LLyWy!@yX-BF2~T}hymZ#y;$UV`R`@<# zqwR$`a^H!pF1PVN?&oH^x?FfGB-dSYfZQ7_d!KB9+}Gv)VWlUIdZ^_7oKUl8*8@3y zhh~ksQTES4xn_CfN#9#sKGRHhk?pAzp4wYnO~>TSju$p1?kbM7ca?cuIwHSC-&1dQ z`HU9wSYY-_rSKkTCwt&XaWz{y`Q8{z99nbK?%&$xt+X$iN0lM%v)XsDm$&cM!92R| zG`G!rbd@96+dQ^5INU0$b+^`C+vxEqm)ojajUM(I^XQa2^p^0J%h9ObJS%f(^RCUi zweaSvS-IO=#XB;VjQ%Y0(qVhKy~4NkwG(F+_B>-J+Dl03S?S#}x@PDSF>;j6631kT zl&sRZ>dRw5gRUt$m#@rRKmBO#Yj)JS^pn1K1M^n2KJm_zzT0sv#;t8nTy@{*twnvF z`o8_)xM^)?Z0dTzdO`YKu@~F_kl*jr)mwe19((ed%uX?jth=kccq}5L%h5xRf8GBd zpS%0L;El(cKAk;d-e*lK-uPmj+vL7DEB%(4`;!M{R@^df%C@40?8Hq+@;p77^*cqk_!-vE0>t4HDbQ?7s2I@=tpCelqQt*JI^+ z%NdwIa=J`LX2m7?CG0fkF8;Xka+Cdsb{xyI^#ORlAc|D>#~raxM?q?Z3?d5K-y|B0+^xPPha z)I9&tTJl*I{|(hF>mC1(vd!=ME6B^m_xwe2#xvS;0|CG;tUe@`O&#flze)hSq$$mNQ zb6=O8^o!4JCXjyhxwnd%Gd|ZR*KpS7_LuAH9_ijEtL_o$HkGZuKGMBIj(*Qbw~MT- zSEO4>*3vuDJtWuHC(=D5L*GcZvs_<4`ES2ufg2*-VY2G}k#4FS+X0bof&d#B>24O6 zgCgChWo0);x-I0m432aM%3&K4>86XFt&wh#Y(#m-T_d-sg5zG2jhN!NJ!CIUb=h4+Hsf3Ui!vyXUeu5@Vn-Z zl^^uG<|ikI{BAS3+K>FM`Dn*sziUqGkNDlgvL`UaN=Tl9(F{X`Z&=64^K z&D|bwJBy>21Fm_E_)5V2O|Ie9fV)^$y*Azrh@y4z?$@&M>*L+tvPm1_-AFkc8{^$8 zWu2Si-5+I^N8{azlIA74*UQnoC(%75iwEnt-lib0gby|{pRKVYs z)=ryvmhN4_Vi(atmZn^xEx4%Qf`g?cOT03_az3AoqZr zQ|?sR++nBOJTZ}b%Dqo+!|+pXp=?r~lyVzJoN_P7^^H6g^}bv-A!J)oAIpuIXeMgO zvIS=1X*ukLW+GGODKZl^gyAGJu|Rg?WHZr7Zu?9*q)`d7M`xLdyJS6gnu#xEN6a=8 zhik}3ugt`^a$N5+6We6wxn|w)9+&HiG7~S!frvH}4P?y$GqF$RF(-&oJ!D_YM{T&~kM`jM1iDfcR$V}9g-JM`27RVk;G!uWwm6kUXC*{6V!AzW&>oQv% z)m;vOybURvAsZiICK}3Bm><(eJuY{`NHZa~Pi}=wERZWLXC`*Y?J{#kjS_9PnV2j) zJi<)WmCZ2ASmMUmre-&)D?)c3tyQy_AogqTR@Y9~cZnZL5^)X~4<;eD*vsjJcZ zRIgJ{qxYd+=NgUPXL_Cb8oiJ7It?^>pXhZ`G$K9WAK-ObYu3;2I&C!T$9J8!n)TDWPCL!|;a#V_X8r80 z(?PR-bl2&qSwFe!bkeLJ+;uu@mg656>D2P|l;a;iPxv^s!+(b&{%v^-aIW*G$Q|DZ z$#QxMsj!glx~K~2p;3iguTh2c)TlywX;dM-HL8$48dXSNjVh#{Mip{{Muha&jF17E z5i(FSLI!C@$c>s2GFUT0hG<5}O_~vMvu1>3YevXW%?QcSjF4fP5t6GJA;UEzBu_I! zMrcOJNX-Ztr5PckH6vtYevW& znh`QXGeTx+M#wD92)R=;LS}15$Q;cGxl1!b=4wXB-I@_HPcuU9(TtFLH6!Fc%?O#V z86o#;M#uuq2wA8ZA&WG7LdN@+$nlRqCTBWMz9*!LobEV_{YH)vvdmc`&wODa59*>S zWVuEavO=Q@c}SxQd03+gS*cNltkS4L9?_^mR%=utYcwKct!9L*(~OYynh~-=GeS0M zM#v`32zgX9LLSqMkjF2zg#JLSE4930dNML5_cXNKRy&rJj(}QaCUAjT|H773T#xNeT;jRTotuJ2a}0 z*EFh-*EOn;H#Dk{of=ihE{!VWO^qsKw?-ARMlk9qR|v68bg7iTPRR8mI6iNC{Q$>!c)}U_U#uS!AIoXIj4szdPW|D zoP67Fd>KWBwsTtEdkiZoVtG|GiL8nylU32JWK}eUtcs?RRnauED!PrVil&oQ(d}du z-9dq(85Ag*Nr9qS6ezlr0!6baP&9`EMR!r4Xf6ec?xsM|JPH)uLxG}uDNuAD1&ZcV zpy+-I6fK}Y(LxFoEuuitVhR*JK!Ktq6rQ4qwl6`R%!0}CZm(0Iil&*f=%u#b_%e!C z*iJ)vK^|805X-BghsmmFC0P}%BCDcD$f{^HSrx4ztD?1JRkV(*iq?}+w1EOe8!1q< zi2_BBQlRKD3KVUoK+)qAD0+edMNd+o=qU;mJxzh4XDCp#g#txeDNwYH0!7bKpy)XY z6g^LYq8BJo^dbd{UZOzJb_!3?gSKy=00|y5=S9m^kM$v1wGgW>r6IS#( z%d4U{$f{^3SrzRftD-l_s%SS^740FbqPNJZXfIh6y-h~ZJ_;1QLxG}qDNytt1&a1l zpy+)H6n#K}q7Nxhbbtay2Psf=hyq0)QK0BB1&WSPpy*=?6dk2N(I*rrI!1w_PbpCJ z83l?yr$Esc6rQ42ZQp7E68zXa{OnLgGvvo&&X=~|_%e#Vv7I;MZJ@BCZ&_XyeMeSB z-;-6*4`fyJBUu%lAgiL2WL0#EtcrdjtD>LDC^}7nqF*Rb^eY95&QPG}ECq_rQK0BI z3KX5EK+*3MD7rv_qCY55R7`=QKPgajkpe}3QK0A&1&aQrK+!)GD7s96A}c~)ccaLr zKv4vRr|7ut`%Zua)8yx%&ey7Fk@@+QFT!tp8AbjG$GKV+xh$`WqR6T!nyiWfWK|SH zRzC7{1zHLeXiMGQ z-QC^Y-QC^Y-P?2jGrw!^?)TY`oabF<9oAwc-%oN+CNo!Ll1XxAe*c1OU`;vsN{R;6 zWNQu#MS~q5iiX&ssKpLNL+wyB%nn7v?NBtr4n>RDp=eP%6fI^`w75Xg5&}g_3KT6R zP_(o_(MW-!Wdw>w2^1|WP_&#t(eeUCD+m;=C{VPLK+(zqMXLxDttwEonn2O&0!3>G z6s;*xw3bj+v{3$A_;MhXpYr>fWDAF)Bhz;-)~+chUrEt=HQ6x>g`zQz4@G0`P_(`s ziZ-xA(S~*?+Q<$?8{4616FU@bYKNlDY>GA)DB41xXiI^jaRNnK2^5VNDB4<}Xo5h| zM1i770!7;h6ipT=nj%m%RiJ2FfuijMilzw^Z7)zXU7%=&K+#Nrq8)^)qIGLZH|9Vp zU!+f{M~9;R>BHNsnsV}$6zx=#y)-Bk?dbV+D$i6DT@fpy&jFq7#LxqB%9C-*X_9%hFdJcML_FrFTpx)s&O3 zr0BGoY@U`-bh_h1(HV9qI@1nCXW60XY&#U4V~3)1?ND@{9g5DkL(v5`MHdPbT_jL+ zu|Ux!0!5b!6kR4zbh$v$6#_+93KU%>P;|9G(KP}^*9sI}Cs1^~K+z2XMK=l*-6T+S zvp~@;0!6n96x}9N6`fL3S|JBgnJ>R*Ms{i_8kOIXC%e6-oO~rkch_VShJ~Vg93P7A zwL{T;b||{v4n+^xq3A(76g^~zqKEBJ^oSjb9MO`zy?fuc7Airy3`dP|__ZK0~@ z&YIG}IgrXi>09)7g`$1Zy*u8iDJNe^(FZlzB_l%7hmH?LAK9VkV>=XmVuzwn?NIcY z9g04;L(vy@DEiV4MPJzzeJxP*jX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(XRqU zzX=rmE>QG`K+&H9MSlqt<$tc=wESw!zoVXisV03lwkS|kBT!TlC~6~6lnGTu@70u^ z%z;$4&A-Euy&sC|(w87>OXcJ%DQaKJzFIUC)j2*C)!U({gB^+*>`>Iv4n-9^6gAqR zsFNLvI@_VBi%n6JKvALpM#k3dmxfueZ@it=CaUA@97 z>MKw*pFq+40!94#W zSh!S9zLKJrQnu(4p=hY%L(woh6b-jS(Fi*fEnr51w?okqb|_lXrf4aF zqNN3jMhX-yBTzI-plDfvqU8jNmKP{mL7-?wfufZJidGgVT1B8}Re_?_1d3J{C|X0H zXib5lwFHXR7ARUrplDs8s%UVjv}q2cvSNB)G$a%aF6Co%shoTzMeCQc-IfYP8#q1` zZD@z0jqFggu^oywu|v_Ob|~7+4n>>Wp=b*`6m4l!G)|ysD}kc%0!3R36ipB)nkY~- zNuX#OfuhL*MN`=6)9g6m{ zL($%LDB8ykMf=*JXg`~x{RN5+5GXoOpy(ihqJssB4iP9iRG{cEfuh3&ijEK{I#QtM zD1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%RP7$h#b}p4Z%z;$Kq)({lhN5+n zqEk!dU4f$a zgsP%@N~KvjkjhEvuGaU4qJ7fM{`X7e9A%UWW1&Rg<6b%-tit5^w{>*_?F3*25Ije6|y`}$R`nl90ZOX}4QZ&3x zHt%YoXoTZK(IR#zTGS3ji`k)QaXS<(VTYn6?NGFo9g3E=L(xc^qGbe%MhO%xD^RqY zK+*C7MJosttte2ml0ebQ0!6C`6s;;yw3Hj)IBD^N6A zplCgTqA@~M(a<)fm2x1Jchdc?hlQeb(-_;PoO~rk8@0(Mtr3bgc6=z>#12K9+M#GO zI}~khhoUX)P_(5TipJTYXe&DujkhV+?q3B%4hobZBP;|Z>iY~B2(S>#>y2uVi7u%ue5<3)KYKNlBY>F-yD7r$R=t_a2 zs|1R!7AU$#py*nGqU!{Tt`{h}L7?bHfufrPif$Gtx<#PqR)M111d47KD7r(S=uUy6 zy9A2v7AU$$s46`?Tm9f}^aL($`QD0;#UMNitH=qWoCJ#AC;j6l(|0!7aW6g@9c^nyUqivmS22^767 zQ1psG(W?SQuL%^rE>QG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOpheB1+{cTE{ z=Rhh8rw?Kegrc?U^YKxea`KfFeby%1V{9n;-0`943p*5jX@{b(>`?Tz9g4oOL(#W( zDEiJ0Mc><@=m(pk9|ekj5-9pvpy(HYqF)7yeiJDAU7+X>fucVJivAKP%6}~TwEO~Y zQ>3UUP*fvOR1zp^BT$qH6x9k8l?9603KX>yC~7ZIR3}swebT0MZVsd}A$_^}(@^wW zx}{&Am6NZesFG#(Z4inY9UqE1*`cVj9g4cxp{U6YMa_07>S~9gZgwc@Zik{CHbp%J zih2nY%_C6MTcBuOfucSFMSTT|<`XEIU!bU;Kv92zq6Gws1_%@l6ewCyplBh1qJ;&D z1_=}m7AP7bP}Cw&G*qZ6YRF0-=RhjkraPu}%&NEaS4>~X9+s7pucTv(KtI4 zZDog|@pdTM+73k%>`*k(rf8Bt(KZ4_lLd;V2oy~fDB4z_Xgh(TX#z#t3lvQkD4HQq zG*h5x2Z5ql0!6b0islFu?I=*RlR(kV0!4ELigpnw+Eu73+BhrC$$?acru$uQ5{g#K zf3;_}TUJiKlA^t`?1arj(cX>^Mf=#HXkR-N?PrIg{q0b6fE|hsv_sKBb|^a74n>F9 z6dfv1beKTV;Q~cR2oxPDP;`_)(a{1$#|RW1D^PTtK+*96MJEUpohVRrl0ebP0!60? z6rCzibecfX=>kP(2o#+uP;{11RkTM|x-|z<8I|sLy=N%;JSjRmD<@w`(fL{S+Loc{ z0>_7<3++&JksXRIwnNb+b||{k4n>#Qq3Ciu6kTD5qAP8Rt`aD^TA=6}fud^#imnqV zx?Z5@27#g*1&VGGD7smo=oW#ZTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCA zx?iX&IyWm7#^s8}Bsk}VqVDNCAP;2ahoZ;rQ1pZyik`GX z(NlIPdfE;}&)A{pSvwRxXH)dNK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd z3KYF1Q1rGy(K`Y~?+O&XCs6dhK+y*RMIQwouZ;ZQH?-RNua2WKv5=8R4Y(a7AR^f zP}EMKsJ%c@oj_5&Kv4&Qq6VR==<}>}cn+kpbW-$1D0(SLXCpSD663hR9n5JzeW0pwn%L``AUkGsLj5c9Ez57d?;GV4n<4bp=hKXik7iM z(I`6Guqj$mplBt5qLl@TRuL##RiJ1!fuhv~iq;S)T2r8CErFu7 z1&Y=YC|XybXtY4ldICjb1d7HA6s<2%w1Gg;h5|(!2^4KCR23~&Tk19?SM+51AhviY z`ZRqBa+BI}@|6^AQJXEfZ7AB(@u6s(9g4QHL(zCU6m4yXq6u~=nrMfjNp>jO#tuc3 zZHlG{6ipQ<+E$=wJAtBU0!7;k6ipW>njug$Q=n)EfudOgMY9Ep<_Hw+C{VPMK+(6w(&)RbGl@#q;o9#6% z6z%8uP_(}tiVm-)12iu|O5IYndYKNl3>`-*LP0(2?9kY3KX3rP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owm{K2 z0!8NvRYiN(md?+CRF<7ThqDhw=^fK~wdLe1DY~dOdtiDfy4dld=n^{=U22D-%j{5e zxgCnGutU+6b||{a4n=y;7J;H$1&VGH zD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaWmiXIZGiY}-veVPNQ9Fpa5 zE(}F2>CQ$E*Ors7r0DV5tZs);^n~L>(UW#4dddz(PurpB89Nj`Yloue>`?T)9g1GC zL(z*iMK1{yy)01lia^n;0!6P06umA`^oBsun*v2|2^768Q1p&K(Ypdg?+FyWFHrP> zK+%T+MIQ+ieJoJ)i9pe(0!5z*6n!pK6+K#88kz&CT%Ep;_E;#|zm$(JYRk!2QuIx2 zw%+Ve^sVDV(RX$z`rZyjKiHw@M>`b#WQU@k?NIcK9g2RnL(y+GMZXIa{UK2Fr$EtP z0!4*#+-#?)C{R=*P*f5q%I^|U{f<3FnLtskKv7wssI5RzJAtD10!4KKMfCzj9R!LR z1d2Ke6jcO@8ilH&uWCy>khG zw4gxILIOn#3lt3!C>ktKG(@1NMWAS?K+!OPqTvEXBLs>T5hz+zplC6ns;Eo3bbAh@ za#;EjQB%2kOMl7q5pD5uIr&P8mM&*+>>P?lIzALFV~3(qb|_lb4n@n^p=fzK6s=%~ zq805>w2~c)R<&52^5VH zC>kqJw7x*m1_DJJ3KVT5P_(f?(Ix^#n+gE9_8or5%c{vP03;b||{W z4n^16q3Ak06kTsqbb~LubK+&B7MRy4l-7Qdb zk3iAA0!8-;6x}aS^ngIog91el2^2jnQ1pmE(W63D(Z%J`^Er^pQ|aFOmxQ7>)7Oh0 zE0>e6r0A(~_QT$x=xN7?qG#+-^sF6akC*=;qEjoF_xkv~*Ygugm4+D=GTEoGrayDEh(i zq3B0D6#Zm}qMz+h^ot#eezil6*rDi8o1(u2iVAJxCO1Vzfub6LqLM&S z8-b!spr}@$s4P&_R-mYzKv8>vqB?=1dV!)20!0l1MI8l-Dgs4~0!5t!iaHAvbrGtH zzAcxw%7IjN>6XL!E);!|6g9OiCtpcX_qN$S2ZW*?jt@mW?NHRq4n_0Wp{TbVisrRL zQ6D=L^|eFMe0C_B-=?UaKv92zq6Gws1_%@l6ewCyplBh1qJ;&D1_=}m7AP7bP}Cw& zG*qBym_X5Rfua!tMT-a&Ehk1T&7ARUzplFOh(O7|^^#zJH5GdMEplBn3qKyTL zHW4V=RG?@xfuhX?inb6a+ES=08rin=c@Ct~Io;Al3$u|v_ZHbut?6df;6bb>(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>Lua zK+%~3MP~^Voh?vwjzH150!8Nu6rC?nbb&z8g#twv2^3u{R23cAwlp^fQrW9_4(Fgy zG%Wo}tV`OKldq)ciniG)M~0#+9UqFWvP03;b||{W4n^16q3Ak06kTtJq8sc`bfX=L zZn7!5S)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pKQhdj*Q_6DYc0py&aCq6YeSfJ<;fuctRiXIavdR(CB38AX!vbLo=b0C#N+U9UB4@F<6A1ivYZ8`Z$ik@wo zy>)abdd~5o=y^L7yN}%X# zfue5&ioO-9ik@y;YI97k=(Kdd>t{mI%jqs_-?c3#UrEtVZL|Kzg`%GwABujlL(#8x zDEiF~MZepj=np#-{b`4yzwA&{XcxEJLs8MDs79cuBv8~wpePe4sud_I3ly~#C~7BA z)Lx*dPN1k>ps0gDQG-BHM}eY>KvAPWQ73_-&H_bU1d5sjikbzAx(ZcAKeR2akprn* z-Y19iVev@0iH zNzwA{vTIHXMJqTy6s>57qLu7Ww6YzFRj)IBD^N6AplCgTqA>zRV+D%V7bx05plCyZqKyQKHWnz_M4)I>fuhX>iZ&N0+Crdc zOM#+s0!3R16pa_Eik59xdNBu5c_@7lTP_rBnm;Yux?MT>N{Y5=m;H1~D4Oi}P&CC3 zMN{oiw5=VAwzEUgG&>Y+Z-=7kb|{)*hoYG_MLP%-%@Qb@El@N^plC;dqMZbab`~g_ zD^RqHK+&!OMY{`YzD+mFCWWHw(?_&}+Le>9r0B4A*)pexqQe~@ijJ^D(UEp2I?4`3N86$37&{al zYloua>`-*P9g0q{DLPT0=p=!nlLd-S5hyxUpy)J#qSFP6&JZX%Q=sT9fugeoip~)z zI#;0RJb|L~1&S^ZD7sLf=puoliv@}<5h%J;py)E8s_2k*rLA)ym6g*E4;>nc8q)Xl zFK<^)zLKJ=+hzNm8H%oPd?>os4n^15q3C)$6y0Elq8sf{bdw#5Zni_wEp{ln)u!k+ zfuh?5itZ37x>KO&E`g%E1&ZzwD7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRG{cF zfuhF+ik=WCdQzb1DS@J=g{q<}+m$ZPfm9Yv_q)C-6irTwo@rN3zLKIB+GUTN9g1Fb zd?N}%X#fue5&ioO*n`c9zedx4@K zgsP(F+LgY{fm90V%hk_^qIc6LNk6tLCtpd?ukEsq=Y^u*93P5)w?ok%b}0JO4n=?2 zp{US4Zn=k|q8*BA>`+v)Ls1)>qD-KuR-mXXP}EkSsGUGjdx4@lfueeWq7DK@4FW|S z1&S&HMU4VQodk+H3lwz`C~6WYY8EK!Dp1r-ps2e*Q4gW2=;wB&MRFjO>(Un*e+fkk zrC&qSvwb=FN{Z%fpKWkKDC*<*P}J8BMf2IAXns2s^|M1!e>)T{V27dsb|@NXhoS{- ziWU+mT3DcHkU-I3fubP-MJ)nFLj{V42^0+%C>kM9w1_~_q5?&W2^1|ZP_%?V(UJm1 zO9>P$El@O4plBI^qEP}x%L-LR^RzGRnggjUn&9+qU%jROavICEFDG9~(Ms*J(=G}{ zD?2_Etzw6wRqar;njMN(w?okyb|_lY4n=F(p=fP86s==Zw5~wWXn~^j1d7H86pa-q zT3?`O1A(Fq1&THjDB4({XcK{=O$CZJ6DZnTplAz$qAdlA#t9T{B~Ub8plEA>q6q>; z6NRdx7222X&Vf|Aq?=_chN6w?^D(J?Ir&P8rnb-Cxg->A>-bQ#ogIp%*`a8AI}}Z~ zL(vR76wS0l(GGSfnq`Ng*)~OU1d4VPDB4M&XlH?V_VI;POy(l;cCu(RL_0#tuct+M(z;I}{ynhoTegP;{alicYda z(aAPNrwA0CDo}KqK+)*}MP~>UoheXsmO#biLz4(G7Mey3r0rH`$@+W;+z!Vuzwz?ND@^9g1$ZL(v^JMRy7m-6c?Tw?NT7 z0!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`|v_R1_ z0!7aX6g?+Y6aBh8>FDv_sKbb|`w=4n^LgIqS)izkKv9!G zQL{i%SAn8#0!7^gih2kX^%N-TB~UbvP*wC>`%>@gaz!)d&*A(YihfAm&oq6O_xw2&Q&7PdptAe*AW0!2dvidqDU zh6)r76DS%kP&7iIXc2*;MFol$6DV3-plAt!q9p~2mJ%phTA*m8K+!S+MWY0YmK7*k zPM~Ocfua?Js-ix1rHMI^%JqG6IDPA?xAa#{q*kmeCtpd?s&&}`H-)0r93P5Sw?oky zb|_lY4n=F(p=fP86s=>2qIK<1G};bD>)8~I5hxlfP_({4(FOuV8wwO{Bv7=mK+z@w zMVkr~Z6;8(xj@kt0!3R26pa%o+Df2kyg<>`0!0%9iY5vaO%f>DMxbc2P*t>YUFp&s zNad{b-Plz^(a7`zAyewg$yZV|tuA})mQb|4<3rJOI~2{ZL(xn-6zyP#qFHt*nr(-o zId&-8(GEpB*%a+8P&8MdXcvK^T?LAE6DZnUplA<)qCEwQ_7W)CTcBtkfuel{iuMyI z+FzjP0D+in}r`nTU(GJ&GY1&Xc^ zD7sRh=qiDts|AX#5vq!gsw*v)1F1ZjKA}E36y4X9k8A77$yZWzV_mkpy)n!D0)($=qZ7srv-|h5h!|Apy)Y)qUQyQUJxjHQK%}q zzOJ-;4y5v3`f=DBLeV?v9n(v7<>V_VdaW)yUtdCprp{T|VMI}2FwXs7{W{09$I~0}eP}J5AMeXcR)ZV73 zPN1k>ps0gDQG-BHM}eY>KvAPWQ73_-&H_bU1d5sjikbzAx(XC^6DaB~P}D=9sHZ?t zFM*07g_)R&X5q-c%$Y{o;OXidk5qP6T$w6-0J*0Dp;x^^fU zZHJ=u>`*ku4n`0!0%9iY5vaO%f>DMxbc2K+zO|qNxH!+X_`htJRl|&w*4Pn=gm6dMGNT zoBi9>my@rgXhwZ@!y}<+rsG4=4t6M-Wrw2Kb|{)-hoT+rP_&aBigva`(Of$e?P623 zt3c6i0!6zE6zw5Uw5LGPUIImX3l!}mP_(Z=(S8C&`wJ8uAW(FmK+!=0MF$HM9U@S4 zs6f$S0!4=l6dfT@bfiGhQ9@PG_VuM#b0C%N(*3TdhoZxiqND4}$yZWze0}!YW1;8- z$A_X5?ND@*9g0r2L(wUAC_2>+MW@-J=yW?2oneQfGi{2_5-2)bpy(WdqH_g`&J!p) zU!dp$fuaiqiY^i;x>%s-5`m&i1&S^cD7svr=n8?ND+P+K5-7S_py(QbqH6_;t`jJ_ zUZ^TMw!YNo@m$f7>3-M8g`&sOw`OmsFDG9~(Jl4a@=u1MTOA*YZnHzt?RF@-!wyAv z+M(z!I~3h*hoXDzP;{>yite*1x?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yK zq9+B4o)Rc}TA=6|fud&xik=fFdS0OD1%aX$1&Ur0D0*3-=oO)==%)J8HaU>W^67rp zH;1B|+UMid`f~D>6unuW9rSc4ddu;l=xsX`y<>->ckNL0o*jzbw?okfb}0JL4n-f? zq3C0qqE7^hJ{2hXOrYpp9|Vei6e#*h zpy+3TqF)4xeibPCO`zy^fucVIivAR;ie9fTU7iD}bWdM(d?OUy-8mnB)t8g6q^Q&( zdm{gOcBd7F7P2-S{`HoAW{09$I~0}eP}J5AMeXcR)ZPw7b#^GKw?k0}o1zARqK*PZ z6@j8gfuc?VMV$qTx(F0C2^2L86m=CS>LyUsU7)CkKv7SDqFw?;^9U667ATrmps0^P zQD1?g`2>pQ7pjVi9ZKKkKq}j(yIR+DsNP1~ze_&)btoraNzuR#S?3o*(SnYT_eBfY zp=e<{6b-UN(O^3i4Y5N}iyexF+M#He9g2qA6paulT122|QGuex1d0|HC|W|GXi0&h zr38wW7AP7iP_&Fd(I|nUWd(|s6DV3`=6!9f~%xDcV?|XcK{=O$CZJ6DZnTplAz$qAdlA#t9T{B~Ub8plEA>q6q>; z69tMU2^4K3P&8SfXo^75RDq&x1&X#4D4Hfvw7pPOv}T9Wo;i@pUFm+;YlWi4(kDsN zJCu{Jq-a)$?5tNp(QL=wN}OLj;Nr6(~APpy+Ucq9X)~ zjua?5N}%XyfudssijEbkie`2w-Jb)gT$(ohMLqzCh6h0!0@J6kQ}x zbg@9uB?3j43KU%?P;|LK(G>zkR|*teB~Wy=K+!bg9QgnNVY~eRU(H)KtMR(ev=q@`H-ED`Wd+bnj zuN{i+vqRDSb|`wl4n+^z6g?zR^sqqDBLYQ_3KTsiQ1rM!(GvniPYM)0B~bLVK+!V- zMb8QpJtt7~yg<!-^=+Z( zlJxD6H#(G)ucYXm4%rTGhoW~KABx_yL(%(oDEhz-MIYLs=p#E6eQbxKPwY_isU3SO z6Day!py&^QqCW+S{t_rEG{g;aii$#2(OVr#C+0vZPo+D_z8#7-P2UcwX(%UONl|S> zcGJ6|sOqMyFgJ7fuf!QMZE-y<`F3BEl@PCKv5roqP_w}^9dBqFHqD^ps2q< z(E>tMQJaR+>p76ht?6c2)=<5rzi0YYp#vJq$yZXea6|UT`=Mx%<3rJ4I}{DELs5$z ziiX;uXqX*}hTEZNgdK_&u|v_KHbsjG6fG`Lw1hy>k^)6b2^1|YP&87YXc>W`Q36HF z3KT6TP_(>2(Fy`ZD+&~?Bv7=nK+!4!MXL%FttL>kxIRYeOnl;-;&SM*!@ z*4aX#Xk7Ys$XX5MW(Hnv02 zCUz*=)TU@NfuhX?inb6a+ESosoIuf50!8BminbOgnjla#QJ`p&K+!e=MUw@JrU(>G z6)4(PplCaRqGzC4*ql(bW$O*LhH~@q6-9yE)*!bNTBFqfuc(UiY^r>x=f(xa)F{N z1d6T{D7s3Z=xTwYYXpj}6)3t+py+ymq8kK?ZWJiGNucOvfudUkif$FEicW4QeV+rV z)TFOEo)U^ys>#P~4dvu3DY~m6Yx*)2-R<~LbdMd1?zKbFeRe3i-ws6&*rDh_I}|-+ zhoXn=Q1pmR(W3%Ij|mh#E>QG@K+%%|MNbJ7JuOi5j6l(|0!7aW6g@9c^nyUqivmS2 z2^767Q1psG(W?SQuL%^rE>QG_K+&55MQ;gJMRzommdb%tI`+xo+!=~CE#>3whH~p`az)RM}eZB1d4tZDEdX9=vRTF-vo+&7byBepy*G5qQ3-+3LWES zJ4Ho-q8fpsl0Z=#p{nTJhSJ_Skje?^e%J4XqK(sC*0PS}Ml^!L!hXq zKv6G&qIm?0dJ7cID^S!&ps24v(R>0$^9vO96DaC0P_%$R(Ex#>fdWMf3ROkrj->~4 zAe95s7aH4ktlrYUI(-Rpp^oL`D=8Y%G5hHIP}Ji1P&CvIMZ@e+G~5nFBkWMLh#iU+ zwL{Tjb|_lh4n<4Y6fG%Gw3I;6(gH;z1&WptC>kYDw5&kUasoxm3lyy&P_&{z(MkeE zD+?5@B2cudK+$RfMXL)Gtszjfra;kJ0!3>J6s;pv6%FcGs{bKZ^kYK~XK*OmA$@ke zZpU)+l@yKbm<|3Z6s_<0P_%&^iZ--E(MEPC+Sm?7o7kafQ#%xGW{0B9?NGFZP0^MD zMdJjDwh|~BFHp3#K+yz&qKN`UlLU&k5h$80P&7rLXsSTbwgN@l2^38eDB512Xu3er z41uDV0!2Fr6wMMSnk`fnt=F+MCI?b^EZs3}Oep#xDVo!`=739g6m_L(!ggDB8;oMSI(!XdgQi?Q2uCpFq+60!0T16dfo~bdW&N!2(5x z2oxPEP;{6;(cuC`M+g)hDNuBjK+(|xMaKvf9V<|DoIug>0!1eX6rCtgbdo^P$wF1p zP8~}p=RhhKr4M2|hoYm?7mrTqSWdo@qBA;XxBM20&UAbzI?E14XWOCZ96J=9Ylouq z>`-*R9f~fnL(zqHD7wg|=wgAQO9YB86)3t)py+aeqALW7t`sP`N}%X!fud^!imnwX zx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*py+miqC14DqSHE--pqkihUYUoJrv!Z zK1sT>V>$Usitg>0{q;vEy3g^U=zcpCJz$5T2klVwkR6I1wnNb)b|`w(4n>dIq3Cg& zq9+83o)jp0N}%Xzfud&wik=lHdQPC|d4ZxA1d3i1D0)et=w*STR|JY)6)1X5py+jh zqBjJJ-V`W$OQ7g&fueT=iry8fitg@M>i1`^sAsxk+C8DDPx>V3y^iJND=GS@W43Z3 zoj`uS>yI5DiaxPJ(WiDO`pgbRpWC763p*5jX@{b(>`?Tz9g4oODf(8R=sSU;?*)o} z5GeXlpy(%oqMrqdei118RiNlMfui39ivAEN`ct6jFM*=`uSuPjUrB9>6cq)EY6OZ( z0!3{EiZX$sT7janP*wCn$I`YrkjfM3@5X)@iW<^4)!J6d$yZWTU&#)u2}K5MHM>~HQJ%5lO2jW+o7n79g3RlP}FQw)K#FUn?O-_fubG)MLh+IdI=QGBT&>^ zplDu!qCNseeFci<6DXQrps1ffQGbD=1q6x)2owzzC|XdUXd!{3g$0TR2~|byE2XP* zAeDpCr$Tj=>Mi}JlcK?ua`KfF4Xb3&v1O}Vm2&cx6zx{YwrCfMc6WRz+QSY- zd)lFBFFO?NZHJ`=6?9g6m|L(%?rC_2EV=seCq<`M%E?z!bao{>uPzjwc?t{sZbvqRDOb||{Q4n-H*q39wz z6kTkGqD$;hbg50zWdcQ)3lv=;P;{k0(NzLPR|^zfBT#g$K+$yqMb`@y-5^kOqd?J3 z0!23q6x||FbgMwoZ30EN3l!ZUP;{q2(Om*XcMDZTXI4rN=Rhj!rf=h)6^gD)KM-%D0*I?=mmkI7X^x55-56Epy(BWqE`iqUK1#KU7+X`?Tz9g4oOL(#W(DEiJ0Mc>;L{UA{Eqd?J50!2Ry6#XJl^s7M8 zZvsWX3l#k!Q1quj(O&{Zg~qtqPEk>ys79cuBv8~wpePe4sud_I3ly~#C~7BA)Ly76 z`nXbBKL=8oo9?~;NhsQ)Lq6&n%gI+#)Uh$!u~R6jI6f3L+M%eE9f~^Jp{R=;ikj?D z)NF^Mu68KuW{0BgHbp%Iih2qZ^%5wWN1&*;K+(JcMSTQ{`U(`yCr~uMKv6$|qW%I! z3kVbq5GWcbP_&>x(Lw@63kwtt5-1uhP&7oKs70tM>d;s^H3w3;D9hnAG*)lvubjT> zIJB{xd?iJTG-kJT2}O%KJ`^oxhoZ&pP_%>{ik7rP(NcCOTG|dpBkfSMj2((b*%U1+ zP_&#t(eeUCD+m;=C{VPLK+(zqMXLxDttwEonn2O&0!3>G6s;*xw3a~8+5$!E2o$X= zP&8VgXgz_VF#<(n1&Y=es)~j;mfp^RR3@bx_aj14IemEBps}2MB}JPwX2q_dXj8|B zqRs43w7DIMwy;CdmUbu_XNRJ#>`*k`4n#Rq3AL@6kTqIqAP5Q zt`sP`N}%X!fud^!imnwXx=x_zdV!)F1d47HD7s0Y=w^YUTLg-36)3t*py+miqB{hN z?i47xOQ7g(fuef^itZICx=*MoI;XL8Z4RWeQhg5R+)#9CB6WXbIr&P89&XH@np#5&Vf`m>6ycMC={KPeyZ`4#&YtN6n)W{b?+03zI1#j`pOPPU)!PR8#@$z zYloum>`?T*9g2RiL(z|RDEi5!=x2eVUj&MN6)5^mpy+pjqCW(R{uC(sOQ5LGDQ>n? zR1_$x5hyAN6txj3$^?pP1&Yc7MQsI&+6ff37bvO|D5@7I>L64Veb!hSl>@0<-I&Aq zJQQ7?z8%ugshoTzMV&fjS>3f zUN%MZ2o&`eD4JKGsE`=6{9g0TUp=cR96pgY&(Xw_ZTFwqd%i9#KAW*cTK+#G9MJo#w zts+pgszA|d0!6C}6s;jpw5CAOS^`CD3lyy*P_(W<(P)99^#qE>2o#MKC|X~jXaj+w z4F!re5~_+8?NoX+2U6*izUi@8D7w7$23x0c@|6^A-YNTRfl#!C<3rJwb|@NWhoY_Q zP&D2SMO)jUXo4MzCfcEBk{yb+u_>A?P&7rLXsSTbwgN@l2^38eDB512Xu3er41uDV z0!2Fr6wMMSnk`T?N1$j&fufxRigp$#nk!JWi$Kw?0!6zC6zwil6>Zw7R2h&fxucT<7PT8;pL(#sD4@LXgp=f_Q6dhoPq66(vbdVj24z@$lA$BM_ z)DA_5*%TcvP;`Vq(UAg0M+p=iEl_lfK+&-RMaKyg9WPLHf7r_zQwkjnY_%=QjN^CnW~b}A=dg)W7f zZ2orV3@R3y2Irr37n;`1e;sX`rXBL{lC*6)F8@GS-*iL%NmZrkrTm@%U7FHeZ@V>( z&rhLO(?$6mDEl;hk$;xeuW3a77itDJ?b5eU7}RuE{_U2bP1yp4!Xiy;4lERwXgX%0 zLSbanOM?o9<(lScDHK*}nlP+TSgq-j5rx89O3%rRkNG3x#P-^R8AX%xs#pMxijL>9Vy7g}F`NtWzlL z-n967g~HxVdyFj<_HVjxgF@lprgj?_3WqnXyJ?|tbkhl&7YfHWy|!hcaB@@M@rA6HBPFE%f8db*2j^L}UM*FdrPk+buwpxE5;y!<*SHg9l2ekBx}PrE3;7K+X9T#{c6 z#pVH*=hs8AIsG;Je#PeW=g0>Zo73Nu9#m{je-L6fE#Rcubb-FjlNIsJO#DaGdW`(>vUo6|1{omp&7zu|FCu{r&UzPZKb^gGseFE*!N zlC^iSIsKNS{fo`%*VG(bY)-#th`X66xPCu%Ba=bgFE*#U?A}~#PWQRIz1W=YG-}PL`trrc#pZPT^YdbJx&iTZu{nJP_IB`sELcr(ZLySm^df{#H^PvBZG9)K{Na=(c+Pb(7+VO;VeZx7=!> z+t&F_;^K&%QoBFjH>Wnab83gBmY<>ALf*E>Uu<#2g{jTS_ssl%_utd8i#8mUA9HHH zkI(=27~PP!#adgT$3|%^ULD<^%ipStOElzm3s2_H`CxkP>FHFLjOSjWcRrSiF)4q$ zFD@NpS{fr`Y+jp>WnwHoe?CT4NB1`Q=Rd_|TSv$I(Q^L3$8Gt0k>YaIXXu%~O&8Lo z(`%>vkvsE8dJZWT<|&S@ZG8Wgd%oX&p5l77jZavVIbW8Q1nznBhdfl71$MO@}y4te(?=POvlAlgifBGw@EYo^2x4-t$y}PB8 zX*~Xx&vz~KdNe=e<@}J{<79Tt&%t^%yX0?WFUGmL+PS*v#@kQbwe?&*@Z3p{?2?~c zR)6`szirWarn+2z-k3tK{C#TcnYyofOmS$T=OTIfAib8O<7sdG<7vGvj`Ur;@bo&| znz!^i3}|V+FtYjuCw$-7`a0ZN?z>g%>u}4n5B!=girU7vum9=ry$U_=%#Zmty^K%e z1Xrpa+-n@WzU*uf~0&FW9T~1h2mRfv0vW^ep68 z)?euahvtu@>*)CE!Nn1UUMu7&oxz8k-tnjGb4PxW=BIb>JtsD`p5FNvzg}#;SSAnX zlApg-oZOiFk#tSB85*zLt-rQU7im_1-vuYPYklP&I`o52^J_eR<*s??gG=`;^lG2q z2P7S{xMLo+c~6R*X8opFF)k+ z#|}F;KRCbUrd~Z~O!dXQ@aM~O3%!1hW6r7`Q`>mq+ebc~pL%}Khi^UeZ1v^b)8W?@ zT3^mZmn}5B(5p*Uy>zav9+O|)y`IlgI=3G=nSI|q`_}5&{qvx+PtLEl{AE9T$vYdi zzU+f;c=?Gv3cbFLgL>o#=5GL5{iZh#s9vH6zqWXD>miF@F|K+IJ$BB=kLHJT%ir$m zhZhU$IAqR<$2zrMl6^KAo({?1VqSaautdGK@#+`%d4KmpuQlSBeX7UQHs0{$Q-9@` zb$;E$#&d-dzvx4woe4P1E5LhqSzNb9-UVDg-uS}%~--aYBN>ZQ2rW*^RO zefFao2A2wjdB4p+p-BI0`3?l0A4li!iqikupKEI8 zy)l0z{jbgPr`(=@E|UJ&ew07u(fpD0zxLyNT%12k`d{0oR9h%E7W+4Jt}8Y4Y}lY{ zW3ke;P^jrwsH+>5r$V9BTqrdxRkw8Al69-+?>*bZQ}TDX*`kG1YTFb`4WsJn@+ViH zt(eF1!2GCQ`HO4Y`bd7Av}=7NzX;mL31-z3tm~M+sB}8@or`sK|2%~b9SWtkUT$4o zhr0T@CGyj2==v|u)iHmrzn!~E%sB1FILUmbGu0_hvh}I|Jju>+lJQ(!@`JK}o{y#u z`D>Y8a&zk=`D@a3NO9TjUh07Et9NcJcB);j+es^QPcNif_P29X)Agnm@{6Bm+kIsB=?$&t zBtP$k|M+i(JQWM0(}Uw%AKfH97@A)RZ3^ENN1v4*TO$9TKTmov@gGk}kF|ctEo_n> z@NfUEn%81sz4YMz{5?^zuxWbWwAX7r?NP0#yFX%->IY%->Es|J3y#|BCs+|M=G{f2>#-n;u-BUzx?i2I+y*9@~1_ zi?p8avFU;HJ@#*>y}>_DEFMWm*A$LvJ(YB^rN{lN$uE`azuoi4Y6?UDaqiROE{ycJ z=gaa>!~FX&j_H@bM_nNQUn;a+?!P?&pBAMPNmqC}@$~Td{KSfdP13nd7u$dK^3z3A zJ=6IMjDP91`uo4X?`!iLJEg+2>6{jSYv@oY=Ku2N&HopN3~8A)zGa))Gh1fQn$R+9 z-0TUH#?72HW6q=rb0$q}nJ{aYnR8~OFk#Zf9cN9N{kNy3=g*&e$(EV3rfxrV&eWYI z6iTBICVzLoEbBw zO_(x%>h#$ylP63VH-6UkEyIS68!>M9(BZ?z4I7%`;5-hVK4bc%!IQ>sJ$3M~p+iOt zPEQ_^Klxvt)G~GYglRiYoYb=Y_z6>{PXGV?Y|P$e_TMjw$x~XEpEYsEsnchyIAhkN z!T-1{=FXYbdXZEwk{ZvFgqnLK*hjWUbAIC{%-DYW8Pms&pE)&eIqR`2t~@TkP$sO{+Vhsb55RM3dQsI>$cp*zDo*fA zBZ^tp`9J%Y6>CeAi&;~t`;e?yn%pNn)+aqSBx{=<%W5~zI@K13bral^Bw`~*g3o%&{-=Z(WU4~|E=3~o)eU9wJt zQmXBob!vT@6JI8Osp*9*ll9IYw(XO(t1WdHnKkC4|M0A_SH4@auK8-0KTC7#!%EzakEchcz$b{(0Hbi&nF@qc{Y(g`$= z8l3f;KkHh(q^g&Yb1>h(oP&OUzlhQWJv^P!maN~x{zCd@>8$o_ zecip}>LueG{I?gcD{1xCi@{;(g6*6&&ztq{mo@*dFWYqG|MPS^XI)!g(f$i$&81z_ z>+hv`xJ+EFcEJDdh0U8zY?GGB`30E2l>G3PC9?$w<}YS$dNJv8ZAuq#x|XYqTv#4< zFJ>LmwbL!@oE~({7L4nvbq;BLVoiR14a##(qL&_)cIlJlH{#mV42Y+<{2x!BJEZ#b zf&by@t%o_;e;yV&y)D($mUbGFbx)7Qi_2eZzfy<%70O$&_8)I}|6bM5VXF*n$p-e% zFN2+3)c^ifcM(({_RapoMKQ4TBl+y()dP|Ev6;z2dc{`XTYg zF)Hg9mw&OgX48MXA=N8t(SJ~MMOB}k zQ*FH>|4G%;|K<8^`9H7U0j&xW)gI}we^AY@u|Cyz_{}ZpomAKA+h6rHODFwbzRw?+ zUpCGEc&~0%-@~TWZ;`C4cOhxV2Z!d`E`$DdC3-jVUtTf)`}e|w(iJ#78&Ex4t!r2| zp!#~YuA$k0-w+n@v9fA z*Y;me>EFLy{4YM{3`rOB@NB`V)U^69k}c>;NPEHR`9eU7HQh^Stl-$8SHM%{|vOGiT16`JOZ9oY~!Er{rZMW#$@Ok&%>><4sA* z&kY9i(}S5QMs`w4zQ^lJ4Q=7e&B>GfeZh>Z^rT$bGB4AQ?UH?|`9+l*db1PrGlRLZ zaZXZpZc<`sO&?&1 z%ScGd*7FEvTU&SU6Mo>#V17Auc?l{>=P59=IW_&8;UP zaDIX?mgvv14#u*ylGMb^%a)(+&kTf0ZKyxlpYP2wbLk6aW+wTR7L&Z>9$FgaVj_^p z$@BSy($L;Sc5q%&UQ&LtlvHR{mN(mI`q@a9p~|B+Sc}6U;GlkSJ7#GSJgJ zKFP7)w;|>C;QR^W_G*xuxd_E^N8lb<7k5<|KrRMi%Cwudge7<~7 zf*;k~SEVYNO-rKRo01>Q%gxHm%^wm>&z1TUN`kdP8x?JSwCM_~ory_9{4&H($jh-x zS?Wf3dt_B5g;@$&E4P+M*zVcGq)O)pha_burw4~#dC=_4lu)xNTzNA>8~C%NF~cR! zlIA45JvC1$M@R@YlHEcDmJn7rdVwkrZSfwqS}ueXNq*8WUs6(HSe8*B(!%C?rG*G2 z4bM;Z`n8tx8e$8b`jD&z^Ri_@>R58R-&fh{o0Mu}7AiVVw@?L_svb&>(D>3NH(skA znwgclId<;Usq;cxnpGt!=&xF(m@8?bGlJQAsk9BX>UTG@@=TdNZ9IhO8vgKBqp~&gB!#Z3E{3uRNQ4Wi|9Q9-N;WGu zkb@>@d*bwIfpPQ9JjnG5uW(X$Y@E}BIjHh|LRpXtW0h$F z7m`c_W>1_jZQR%xnaiCO%7D@zOqS#Xo5}{gvcd5Ag88Y^kcD<&X=MZxt@DvSLTIHg zDLp+e-J2~{BE_F0^y`g{r&h_R)k0W#jFa89n0r)d;`4G6%$s|DPO9`|tSzPSV>1|b z$c!Xu*wDq{k<9BSZK}0jl1bLwY2l}@Tgbg4l<~xFiMWAgCuJrIzhSL)=#u-)t`aDc zQk*tnT>iLeV<#3)%h%c!O3a_0o|NKEM@9(Zz#4;3J5e_Vdz;N1MgRO>EZwM)<|Y~*Jv&UT>(`9P$jJX4fr_Y)*?uIT?yLT63PRZP$9$gL%^Qn7mf)e~0c>(uMOT_|yF(D*MoJ(g5o&-K#X3l{H+eNeHz{ zV&y&~bw5|SpL#D3ZNRH$j*}`crqm^$^b8WbGI&DcsmGLlzm?tIm4wS3-}0&sQgjHR z9R|OQ5v;C-b)F_{6VsgW>ltF*6W1+l zD^Hw|FZuWM4mGk;;GqLomXh}3@=;XQ9&&#)7vyqUhO|&&4U>6YD@SWrbi&cbvD0WJ z&_hxhm#+_+#?6{#Su%M051FwV2X^Kn;%uOqY zfT6K#FQj6P+IUo}X->+>3LA>~baEj4Mxgl)A4#STmH7u>Kw3rXjH*-;!md4%Pc z{jFli%k&Nr_;qv~S`${v-aHw5OD`;ZtgZbdmZgPKii}&VPD^No$**=*gPGbon0I2& z|F~A_mDVH~$bqQJ@mtklnL-&NpBc%?^5Hz`VFs zCIqYW#Y262j&H5u7)t>~TD1w_wKB^?dRta`$e=H*JoMJ89`d^`OwvGkO1IVr4T+p$f8rFc!ToqQqq$gfkLOLC6&e>>RN9HN=Q@nm_ zl2Et{ZN|cp5k_8mWw%CgXU{0S100$v>c*)e9V4=!n3(o#j7erAt69_`8aD|aPskLk z-zSZg+)Z-LatdvgBST}EO2Bjh%Ps69NB_S*Xp=auXzm2FM0L2wOlnp1CRl7))6`tU zGfb9IoD6vLlheI9mHTmRUY3%ra|@h-zhbZzx;DOKU*&c2=tMY=gc%d-?rdIYYZhM@ z!zaVd(cl&BMrB_$G3mebR`mi8PqIeF91>Qo`wFjgjgn-_Lndd@EtG?MbY|PkkTqYQ z;T@Lm%gn`HD}1`z%-X--l&!%V&oeZwXC_%W@9mLUxbUh}IX$E&YgK|OjZbLEuPKI# zF`T#1m>FejPDz`GWeZ+;leFfSb)^mz&5d-jmAN+W>T>OcTc1?3|NQjBnoO>|GyPjL zKbV;ULg90;jv+kHxvcwF8 zn(0u1g*99{z~qKJgavx&#%Y#T_#~^!Rl)Ap7= zT4%YYRp)8LMo=o|yqI6Qi zdM{iVddS4PrZvE^z>^a(2WhBLVdoW&L6xU6IN`j^KxS~LRURBe>9oG4YYkAC%LJLk zmPd5v;}dhW4v@GqtiMoYO2*8d2e%s?KADD2jG7D9hb$0vwJPn3 zH%mI|!(=301@f@$S><3=9-a^DfC4Pfldqi0G&@Jh-te9W_u!_Q6Klj`=1FdSC|&FR zpr$nf;32cDZnR9~h04X`L|TuK;mb&@GKv+>dCfvsFC4VWMpx&v!yiI1yVhx2SwtnQ z+P$w#LY|YdH^w}3B$tzyBagl?wEnjlO`XiV;(12pY@^&us?5h!jxpsiJD!|r_H<+t z8bI;*dapNcV*hCrtn4U!9Dr#m$v8)kOp=94m1SW~kA{6}z#1i(g%jTQG>3OXwU z3lHMqF0*9K%j=WCD{lmPgVSf{Y_9n1m3t6RWRYuCi5!{X)#JPzHy3Wo*ti_=-Js@=5Q!R>4-zw(2})Xj4AaF-LtV z**eC);<{8BXDWzh1Ek|2Cc>=wygs=^$@yl_!O+9=BNH4VDUztn;o~8Tv#^egj=ZdP zPG>5$M6I@kM>HFaod5Qq6eY)Og*sW*IL5?4Cp4Lud2`D2R(=9PFYlFwkd+^LEUD$m z+fHQ~*3}sr%nsm|8R}Yiq;o1K%}u3+;)9c_1FK|tKF%?Tes04^@%j42bkK(b-dR&) zlBO1o8#`8>@#XS68|L!@ei!5F|NitqK9sLtboobK^8Kgocg+-|=k;%-|)tvGwMy?U)S2{n?;zk|)c-oCP9p?(>}u*rAq4QHP& z8C_)*l4(TNab;AqS9eD{>e=es8rmD#8rz!Kn%bJ#T12$A$=6N)?G}8j)E65jY!d?y|N>shjX4d+>VOrOh$~SzhSLL^ORNIZv3Ujr5 zqsZC}f9-~R!TK%zi~~?1ucxLD-W0(()1sqkf@qp1ui=}JtXvnT4?Myib5wn#S5?UazOXI38AhUHw|afavPStLy8N1fspZ!RjOy~;!?!ic zR|h}F`VLaiy1jg-)~McCf33jM|3Z9OqwJ^Oovtq5PX8W$1$_MqbanZ9d}sMujHWYC zqinBVWmZ2^qvRt}u+umS@gicBeA7nvJE&3CpF^xCSXP&>o+TqrL6l%b2!dMIBjn;J zT^c0`Gs-C#5%N9NRvHDx4)C=O>vp{m2OuUOW+CPw79+}USeX0GL|llt1aSr8qlhmc zZb#gKxDW9?#6yUmAs$COiFg|EXT(d0e<132>hyf{KZ$6RA7U_LT}1uGNcCGHwnglO zDBn{y*Y`#ofapW?BL)%k5Jw^wB2GY@iZ~l_9^yj8rHFSRu0(tQ@gc;Gh)*MKL3|1E zb;MnW?;w7N_zB{dh$j*C>-$62vA=#Lb8=A-;jQ2k`*nA;ixSPavA# zES3EK2z?Rp55x$$pXm8jLySUfh}Z(LEn;WH?uh*my@;uZLBt`5qY=jxu z5f37MhWHiYcZlZ@e?j~m(I)M?mX8~;Hev(B=7?<&yCC*L9E6yPI2dsRVlm^4@;*E&6Al`|%8u4MoClR+IZb#gW_#WaB#N&wHBmRt7fhhld)I7iH zi1iR-5qnGbQP1CpI9%@Cs>dPDm(Hx}<%kc-JzMqDh&$v4ulha2uciB_`bWfe(q~ZJ z9dU~EZB)-gd|vu2s&^n(NS{Krv$+)qwzOgZaY-vnuS7f$Yw6DrquN=zIpPrMU}$>9 zi0eCA`f0>(I$Qc@#17IC(d~O8PV-oLKH`hrExilz_nww^NykO^ikYGXE5s2aEIk2n!zfEXhxq*%OaFq{xzN&m5oZ-! zdLiPg<1D=o@$U(iu2Eve#7R~hjClJLOFw{kaGIr$BQ}_6=~%>3vn@Rl@v*s<-h%kU z^_ISb*!4zBUyC?rfu$EAzIL;v-$67MS^6r(bgcYs4lSE!`fm;BiY&MSS8(OTU14?rBT^hS=>{OAkW4VY8)|BEGfN((fTUUa)i> z#I%NUCB&b0Tlx>g9{ViqMZEDH zOD{*<`L3luK#Y9f(sdEjKeY64#Cs1~`Vqv>W#Fgz{SL9kCzkGnIQBD3&qRFYsHI;) zJpYBI|3d8bm8E@%3(72g8{+P7Ed3Fp`#Ve5N6b8B>5+){owoF&h{w)a`V?Z!PnPb2 zIR3n)XCppaZt3labnr%u4n1Ph&AO`_jG+@#B3P|s?JATBfrC^`fklQ=_CG1ziuZG5j{r9T2;~?*rW*(F;ElaU|k+te=E99sUBu+Ys+Z+=#dp@lC}2 z8s$9SM?3`oD~(bfrx2UT1fuFV#A3vo5Vs-jMf?D<4Dljj2l)v(O~-?ngg6gzG2&{( z{fLJUoiZV$`}aYdg17iJX;$g&Nh|>I;`S=0x9O5sC(%hNr z&3PlaPV!4Orj}}MMybwbH0Ot8yUMTZ8dq+o>-5!L-fnsSZ`)}-zw)@@zhb7>Q(v9s zT}|Hc^43?JOmLP-l;Ng%&2>9H-e`F<53*5`%roh$ujqmMdL9^Pq*WX>(+`9p5BJA^z?Zb^S4Eo zxsRstyrlQCZh#lpZ4w=x-d0IZuaoAlw!E3%>$0r-C=dE73D}Gq+E~l_SJ&zLZA5NY zHr-~ViN_bW({@>x`RY8wW~5U{)Z^+)+wt)Hy&87Db!8p%S0>BC@(c;)>jp`$AB997 zOJmq&H(r$O4vN`Od~J&~JuP=VChLYQ8cSx`3@t0Zn4UCURkqtN`8&^zByv0aO4_)% zuG6oHk(Z};T(3TH-THKoljXQLPuSmHy?Ti1)}wE?KDuQ=^@U04$<~hpS_#|aX${j= zr_r~ja$0r0gV9)8(=Mma2j5O#y7frKtGgN|H#^@VqSiyUl@a%P&p*HP!Q{+x`90L+ zy%kI1-U{rkaJSl9u{Z8Wg~MZX`s3J%idQ$j7C2Us6|>#Hx58+3tRgq&)l_R~Sj>rv zy^F2oQ85~yPy6TBzyHzqw!pTu=l##8>T-7MUP*1Mq`f!pbEIp;=$ew&&jvQ6@2@ay z`zsu+_E(gJj@!K?Lh@mF;xGTxy|ne-igR(ni;e0&Dn~wNSbvQRF9AacNnUF72%-i;1|fKH;$od!kPk8kc(&tPZU9KX&P@1U-82VyRtR$=yNE z$%(@vY!|Lyeox?@v=#mpX1;?L?<&@u-yOIc7bAA zI5xP#am~{Sd!!659ZI=eTb9nn1TXH4I96!1-cxa~)v<}u=NATp=Sw4O=T|I}bEy-& z*e0oE8((?Dl;Fj7hOfMF@`;M9-SS>6?{8%Poi#6vskuka;Ao+!($G>_XlbXlG{Gb@*9@*LGp}uAaz-E{O}?j}D%%xm zdFwk+Ugp~;S94gbKdp7TEX8OFUNZ$U$Ndum328pRPid>Nzg$__e_&d4hAatp4v$CJ zs?43kJia5jcc6D#AAcV`zL&@E73h`L+uz$f-+D1Amy2e%^3NT7xb zQ`_h>u}0Tg^PgJ$+B+W}w-pZ?^@;1-X`Z)tjorF4!dcp=gW)cG_RC(2jtuQ_^3od@ z1~wfsaqEyzcHHuQwMh+bwNJVGng+L*8MacbyBqAb((9f{dt~$LUrx9_z3IcZf3&03 z#z$VWy;JAuokd^z*VmZeZ0oY`?Mc-7`4}Bf`T9cdF9samwMcco&U9R_1 z-$5r{c;fejRjW0 zH{S|f!5qD|o>k`G!{*=Yil{-06VyF-=*6_UC6CztJR*GO94?HGeJ-PZ!QrCKX{;ZI zB<(1V){sLL6>*CatffEWtZ0~PemL})r1EemmH6_a?z?3_sUg1IlB4y3-IAlVp)^y= z>&6Nn(UL};BNcAMnut+mT;bncQ5IFV;7&>Tq5qn4YWYjEHSNWrv=hv<>mjX1h|LgV z%y^@uy;stnD`~F}rClfX@PzpCTuIO2al}qb&zV4mr<;V?lcy=Y9;MHoJSA*-QrL1y z*z)+W<*{MQMWJQ0#W){PQ(C8X!HZ2j@#U`BBh!LX7Yy6pia9%_PRx*ZfxON3uee}x z$uQ&3Pd<_LnveL)kK2tE2PzCh>){PA7_q^N!*6JjYC5~RI1G4s9nY?%EF^*LjaZx>ANI3eraetpc z-?YB|er9=;ww0DI%7~Q~(yOgwtMs0kR$j}p$_kB3hoZ^~HQ(RJUu~1?N}K6De`Bd} zVNJYo=}V(ypi^2WY2Eu3=ux61wI&{4d4qU+Yb}N9nNJjbS0wuznnr8Mr{CtGg|Cg4Zmw!d!C{3zaYE1aP+N7nMC%iuE zmuda`T?#(FFuT^^J4>7oZaR8P%f=s+jg;!QsPlkW$(|>DU>z5^O^9&@$84s>Wh%Y}}YFlT&Q0lW?8*%m)`-zH@Rkl?h zRMgyB68o+&xIOT$w1Y=wN$=gZbtfvGeIdKTG01lByK;>jv4QfKgf+?UN@>VD&Q~5& zEBKXqtsb&m5lesBlQ@ZWK&YAysbPsvYkoQ)37a(RyjF-0| z@2E%pkC}VQa*Vv=9tmvFRO9UBnlA%nOMuev{ zMpBAh7QE=mT@qNDw$#5&^J#AT>IIv7;l+7dO4~~*G)TC-A<116=f5v>xYk|FdyXG=$o_}5_6(!zSw<=-K<$ha^%k?O2C8!GQ z-Kb-Q5tj}{A1j>hpAndmHq)#RGXgWyX8LED%fhj5eEJM!Rr)$LeH!i3H#rv}wm!ErJ~<;TL+h1U|MZ+~JvT`$_XpC_()AuuN>9drT?va$`y>m}Rh4xpHEK6K1&C!Zeu_ipjlHX7Lb^04_mZhNIg>6FnC=lV4p znU!#%+xebntHm7o^qa?9)s$gROuSM1RMGvt_MVvhSl=aYX&a&S`cz?X_Am8zwW#w{ zt>#}{x_jeCv0FC}S-$AoYr3Co-mT@paq-eN6v*2(%y8Fs8}7@G?e2Ezwk|ClV*{Os z1lPT{;JVBmiw;$k41eJzUy`I}n{tb-)f63FL@X+hHlqK={H4WH+{WbTqwITrDNXoY z?z3BS&K63W>6XI+%E5w&a z$L17lPs=IE7h*q_BfeqYO?2rsxt};Zx+G%|Grl5qp{D2MfZ5i!-V``i9SkM>yc?K*Nh3CFOz<>`cW}bmr|_ddNDEWtffZc zmL*xs&0^v&FSS|AF)<03>sGgx+u$f25IZBrA@)G*gV-N29x)Ly6)_z#3o#dQ7~&|z z0>rV1C5TfHXCTf&ya90mVkzPh#9I;XL|lP*AL1Is^@tk~|AqJz;=|G+El$Z0fI_aj?+pPj)I z?aThz|I#nlReNw*?bFTWX`p;&;(@XRd#v;=q`jEjanga#AI^V%RpGp{3vYb>-3N`0 z_~C0hZRzsZpGT(j=~t_9>4g3+W62^z`W=5Z&Q0DqasFEOlb1hx`L~#H!eok)f4-d( zDJ0rArf!sabxwNh=L%#rCjGZ6^~=ondjGnxd_Q8_^Gp1AZ9#TQ3u3>J=i7Mcqq_H{ zZoGU~&Z@Ng{F=Uwg3Z>X@T@roZcrLN2G&-mN}D5FX|K#UziDaw<@LR84czMARAj%< z)n~u-L9D&JdH1Dh%cQlj?hvIhdW4M22Yqw>lZyhA)l zil(LIOnO9?l!To;JHTy*m-MZt^l3w-6ic2TjjgR}ibX*(+% zU)wIkJ9kzb+_|%2?~KTTJw+US)F`pW9)qPNyUQGV43@S`#~w09H{*5GUcf!^tQHpP?HM#z=O`~8TPM@k?iE!Cfjwp!;Pq_;cxq>Q(X3;yN4Kw?^= zKZ$FLe1UfUqT*sHJuRd7az}i8pjDc694(`Wm}>*g{aJF9z@&#n`^)9m^3C#HFKSq; zwt)s2tBQKac*;>ncn*!>-&(NEsJ?OFKr+ekQfx-bvAp?sw1oyUng?0~a6jKC(YOX4UJ5ZN_q=-P~od zkM6&4SKYGXjod3Dj9okBzpxqiNL@LfpmpZWhDN;hyARGVO8;*6``(%h>wUfN`TJwX z_aESnZ+`jV;g@#Zx3K8!lvjqdz31SaMyY#+Q7WB)Qk&ajTT;`o$vwZcM#&n~U+Ede zJ}K9XE?1>AR)xv0G}CybI)=C2xb}#1T-O z$*?o|zQF3V)&Bc+)H7I1Oy8>l_em{UZI)!z+Jtgn|CsjiLbl=W_v3Ixcb8O_Jr$&$16Ic-3vDB74I##-}GCnPfct5%5!mo}!8@ksY`bzcr zw&d>V2Ol2UWlzGMXJ!sMf7i@?GE=?CwIg%t`loZ>{r=1KY3~eJ-$Lh|hKz3Y=%`(r z4g_w$txcKqNwq)fl78vY=3UE|moBUqeEpmGGtO3g$9bZFd1m_8I_w57x3ZCI&SBjoz@O%wP#!X(D-zz8!}=^kiO`^Ole^Xte$B949A6d+vJilLW}l4 z|M#A#C*Voz=I>@6uWC>9>i^Iaz1rWVN>4O=R!DoI&7>zva$EXi$11TcQj5*F(foUI zY}3FhxxXEj``fO%jnnLxPsdud|K-<=9icMqW4K?P6}PC@#@HqwCyd&jpSvLA2Y1Bj z*T(c8I>ymFCoe+(ZLZZf&}(1v^2JH+q084lyYktW`~M!lNBac_7rDBfeC@#>b#7w& z$^$Px7ucM(*}uhVTdtVtc&5rs$5Wx1jwhrpor}@GI@3{Xo?F$K24A){)6lB;q5nA3 zV64-z#F1kbH2eQ^9?IyhN$9RV^xWaL>-=c%vo2qlg2tnJDqE| zJ;S(H+8&S0HTZ6ok>>mIgy3A9ju~aX!7gKYX_d~!nR5s|NFwA9yLq% z(D8PS3$_{~lLlQLD6%rbNiq-gu5?N(@(A<>^0NJ_JM5r6;s-i}1`TKNJxzDI91 z=VW2LsWJY~8JKpmaG-x+V35h&uv5LweR`SO;NB|x^f5K=t2w=7pI-i60c%Em=_zB! zp6}zgef;;mhiCNse!rPc^$_;*>BL{f`~Wb zb?jbag?G)lrsG`2&R1p(U$pf;9lJkupLfOnq;31-f}^JY>3eYG{lm8X-SJENp6#!f ze93Y9D{nNss(9|JxBgiF>jAH|-#1^!?b8zae)H_mC4aY1xH+-fuyxR)Hbm> zznt83>$`(GZyNoHwvq3Cd}iWj?LWTo`ktF#*w&?_^O!|OkPue2AQwPycUYxZtYGT&}SYo5HO^nk5i@ZDxF7*7JSgBM>dzAg1YVE}#i)bd^S zrD;Ct4QsE|5tCHzurKnjD9kCkW8x_1pGOieJM1?}KXui_VNRLnX!ZM%VKEB=^D(v)5js^au;3N4PlG z>J=6Qh6T|pWREaDyjS=c=2op|R7;Zc0(sJt8Il_H&^r~zF6++l_dhv-+_YSOo|*49 zt#l41CpBtapMu|tvi6^`$c3NjcwA`b*)h*EYd_s;HSDAkg zOP^30y|fhhL0&yVYnknih#lx}Rq##GKxr!u#w5t!z0%@eogQlQJyAXNX^p1#l03I@ zm`nTQN~*I@=2cD~3V#-+eaD2$E_=_^p8iIfruG|U9=gozJEFFmea9&D9V>fu9Rs^6 zqFPJ3tvaOcs;JjGSk^1@;oB##I+7M>ekh~FRa3s6w!`e}n{)1ZBb55jKEJdH(vNqB z`tjN?8dLO7YW^!fzcj1=d+&TSerK%XX5XM6w&Z>F;l5eRH`Z%@z#L!Kw)#fv#_fnJ zPdoeK9Z$F3vw!^DGU+cFKb`z}_@kdJy5-u(I~A^2_pI|p@#G)tEgI_0U;I<8UUzC< z$7JlPXk_MkS4FedqtZs1{ZXrjEq6D$W9$u$m8@})lu;u4*Fp3v4#rATe_>+&kps& z*L5`e+1i`Yvx{2WRr=XoQ>E{Ues*g~Rr}dT!}{4*2Rf#8^mj6;ijQp)wnh6uWqZ{& z&^E1|za6%U!dBW}KYOZmpmkcTKNjn%NvZG{$4|8kv`mZf$6%eV*<|+e51!KN-*!~n z1KU2l=I>*7mY+YcdY$X@qkSfwS$9M}669Fa;)#^odhUH{+T4eyPR?|HJo52dKij{f z>#)`_rK9io`iw8@~ zlwbe*qq8r~vz>lw$HFd84Ea+&^P->Uko0XeMBBYz?r$R|x)js>#l2-MR5 z+3ngHA;R@SJ*gtDqje-vF=Z!LaedjwrC$zmx(-XnGSanFmR&CSbdvP%qh-08>q*(Z zx@(xEP{Z{=V>w;dUorB9SJx!@oKY=TVoUizkLy$msfn(=vSl6DEArKzXqWu67Nf2! zR<^0<)=WMWpCTQKH#b^SLZ#~0{M{F`>q~xz8|>e$(A3wKa|qwY;&)XY<01@qvg|IU2X0x zDe-G;?sp_-aW?mZ5?0vUwWP#X+T2|vE30hoNckMoeKz+dDX!Hvcdn@WZSJ0Okspvr z1W9F$&AmlVeyz>@ft2z(oBNn#=|P+OoE+$)%^f8tcgg0~e;<0;=AI|!uQvBtIll@y zo@8uTgu8(p=#2>XF3Iu_cJ~O$#A&;`MNPvvV|TZg3wHNEa)fk;`zpyqhQr-ka-HdL-z--@=x{$L8O(CHcS)88 zJKV?Qc-anjg@hc3`)#>&xej-2*&)y2en(Dhh{JtQuI*5V`!hMvFo!!sxEwC2NMa)# z?vqj#MmpTXsQ&BopnZXpBCo6a=Oa|v=dJEwQ@PiobC;h!LOa}{!*;pINje#UJkn4UmwUdH+2=0z06FQSF85%;=+zqT zvr=^1Yq%RrVz1S3uaP6XUc+53YC~=Jb3)OhwcX1k^N-bbUzRLwtnJ<^C;hM5?iP~f zqImR5)M?%i^>Ga9=4N?v9*bYCkuo7K?m zki=#;bT5=G=QMP8kdvO<&>b(Qd0j*IhjN7L8@ijwb-1CS`+h0Gc@5qA4f`7#y4Op| z&zE(Q&jk(LC2|foHFW?mOhf7BzG)lT5^~caN3Bde^%@ zmBbR(yZ1=3Ca!ni*UB)G*1K0oc_y!S%Qqm5l=bezl9#MK?rpMe@E&)Jgn~2f*>Z%! zGwx$jE=6bDOXZSQdtEkOqzfKNXR$8aA_Z}a zE)0>%vP2i8-)}6{g%N`KGF>Q;b6Bnm8>G-z=F5UZ7Vg!BZ=}dp>B4(*X7}mB4|3kC zb>U|z_j$##&`C0Oqb@9#bCM?0s5V)O$fgT#$$9BLquK?z0{Y`2)lNyu4qeEXvvBG{ zJz+xrkGE0nl9Y@~7v2_-+`90z9IKixydoE(x-N7UI%?>`B-u+QAdPC}a)R=2dyQ(1 zWUpGfa7xO%wl4T38&SH@Pp(HDUFagk9jy!ZONrIhg+Jx;*VBcE5R$aCU%fA+np{yc)8($nJ)-BV;p?Jq%|j$fhED8qUs;O+@xGoLwLri|lPU zyFxY+*~f5R1KChyU&9#(*+8U6vgLuUuUhie4Z5Cc$yj&jx~e5-J)omiOV)Zq*HJBb z>jfR9S~Axgy0&V`T_5OLswI1Up|4Uc`RfN=Q*<}U-?h*+R7?K)LswTV`5ORTO||52 zAhcVxs{Q02e*JcvBN&XU{BSd$X{3Su#R7?Jn zq2*dfIpiN|=F9c3Ge~f9wymcC)R`#N+?nFirdbIIIP(Pm=7(t zkRarGNDy)ZBnX)Y2|{j!Bq8&mNyq|d5^@tX3Aq`Xge-(6A*IkHWDzt8Sqx1=Zh&?MvzXcBTKGzqy2nuOd9O+xO0CLt@JEkdT* zH_G*|bF*~KoYO5r_9!7MT}qA;vf8;(ZoeiW_hVNO@&F_VSpx||)tAB}WD7J2*$PcUwn3AS=b=f+3(zFwMQ9T860}9gD*HaU z{&iMKSI2puMM$}HjhrvLlpH1GHRnF*J(+~Oj$J{>8;~I6O-K;(79l|BPJ*WA$`2G+W)sP%U z(Ws|}WU&s7x@t%sqiIB|A(^a8qmCMq%X&1T)R1h}r%_uC$!7x^wbYP|Hl%Tt8j{mS zG-`^WBb>%GYN#POZ9=2E8j{ndG^(i~Ic-M6t%l^ZISrQ@lG7G6BGr(bwxr=yLvk8J z!=Z-cv=t4z8j{o2G$O>%u}&-vn;MeSHZ%l~`VMD=&7LKIM5pKw$8NJI`c5foYjY`H zO3~Fe=S-P&Fe&QD{XtPDYEaaf8WeS*21Q+|LD4nTpeT+S6nUsYQ8#K()Sa3X^`JqD zdeR_8y=ai4-ZV&29~z{nFAY-Ej|M5amIf*6PlFT^9p$0{{)SxJj8Wato21P@uLD4X3QZ$?fDH=h8 z6pf@oibl~OMWbnuqA@f`Q9cb)R6v6i71AI@MKnlJF%42QmIf&rM}riNr$LG)&>%%6 zG)U1z8l-3v4N^3j1}U0CgA`4rL5il)uqaBm*}oJ(q6f)roihUzZlytrZlghpZl^(t?w~=6?xaDA z?xI18?xsPC?x8`7R?r|tD`}9TdufoORWvM$X4>qnWwJVYpLU#Qfufcw?z6d+FQsUW z&FPZ?xk=Gl?hlIAQG=ofsX@_tYEbkLH7I(R8WcT34T?5UgQ7>NLD6H>q-Y}zQuHqx zr08)Pr05A6r07W+r06Lcr08iHr05wMq-YZjQuHhhQuG`RQnZ-{DcVAV6m6wJinh@p zMbFb9MK91GMK97IMK94HMK9AJMX%5xMX%DZD7xQfFA+eZ=WD;{0Z{amITo|IlrN>| zO`G#Jc}`nD4N~+m4N`QN1}Qp1gA{#2gA{#A zgA{#6gA{#EgA^U5L5hyiAVpu$AVpu&AVtS%SQNc(vu_qaqUS3(Z-65GaaiY9Hkb0H z6n$fJek9XCCPgQ?KPdW^8Wep;4T`>}21Tc+LD3J?py)I;C^|z8iq2AlqI1-w=tml) z=qDPa=w}+F=sXQlbb$sbDyKn;exX5%F47=HmuQfp%QQ&QuQW(e1r1X48x2zQI}K9w z2Mtp6Ck;~c7Y$PMHw{ws4-HaeM1)59))>u3gA_&3uqZ0C*)Iwp(MRN=uJdb9l%mh4 z>=7>IODS?iIP13qMQ-j7imFkAqUzM3s0KACs!0usuA&A-wWvW+ZE8>yMGcDTP?Mr) z8l#Sq8`+ss3$cj>P1b8 zdeb09eQ1!PzBEWtKN_UyS{kINKMhhefCecVNP`p&qCtw{X^4N{aqgB1B_kfKBy zq$r67DN3e6ic)BhqEs5B$WMb5rO_Zo0UD$zorXnG#|V3=01`b+o^(1pfubCJa*+|? zQofX;!4b|!JA$HY?hlG`s6kOKH7LrX21P@tLD5iZP&AAh6b+{aMI)#|(MW1iG>Qf( z8cl-~jiEt`@@bHw0ve>KkOnC#qCtv^X^^6^G)U1n8l-4E4N^3L1}Q3`L5e2QAVrgC zkfO;nNYNA;q-ZJ)QZ$VQDVk1$6wRPPie}QVC<;c{-xffk@0F<`XBH?rptrYK5iaFR zDY`Dgd8#ugx}N)kq8q3|(L8EUbR#t=nokXi7Eptto2Wt2&D5Z1AvGu}r6xs-Xpo}C zG)U1cG)U1B8l-3`4N|m>1}R!jgB0CLgB0CHgB0CPgB0CCgB0CKgB0CGgB0COgB0CE zgA}cxL5fz=AVv4mAVsTakfQr&kfPNzNYVW?EQ;nt*lTtXilX$RZF51<8}gwz=K~Qg zJ421OgGLD9dcLDA#Xr05A6 zr07W+r06Lcr08iHr05wMq-YZjQuHhhQuG`RQnZ-{DcVAV6m6wJinh@pMbFb9MK91G zMK97IMK94HMK9AJMX%5xMX%BzMcZkRqSt7UqSt9y6s?W0XA2^r3OX&s6o-&)S&1cYEZPF8Wg=t4T=s>lcM)% zkfQf#kfIN0kfIN1kfM)hkfMV$NYNo0r08QBr06gWQgnm{Df)y4Df*NKDf)~CDf*lS zDLP7n6dj{MioT#hioT>lijLDDMPJb%MJH&GqB0s5MQ=se*9aidAIUVea|bB0%g0uo zUq`r@-M`g9a&b(y%Bx8DalQ0EwucmC586xHDVpr|G_D7uOo6xE^zMYX9xQ4}>OszVKmqNzbqU20HNkD3(K zr$LGu&>%$(X^^5uG)Pfn8l(@Q9NU8jhu*{zX&P5JVI zvy@MX? zDay4w@8}1L^0+@J8bS?AVv4nAVm+*AVq6vkfOCTEQ+qT+b;_s(MM#O+Ia&g%2bNh*DgjdW8Ffq7Brb=uv7=^cXcL+DHwG{zVOn9;XIHPf&xRC#gZvQ`DsBX&R*H85*Q$ z6Ae=IEDcih91T*mnFcA^LW2}-r9q0e(I7?7(;!7J&>%%G(jY}I(I7=H(;!8!&>%&x z(jZ0KX^^7VXpo}UX^^5fXpo{eX^^6~Xjl}jx7+&*AklB?)7XbVQP&s|JM1pyODWo8 zcaHXgqP^T76z!u1MQ>AsqIal4(SB-B^e#0hIzSDI-lGOZ?^A=K52#7ehcrmhM>I&$ zK^mm!5DilFF%435m%%$(jZ00 zX^^6?Xpo{4G)Pey4N~+q4N~+C4N`QHhDFgXyM3_$65U@uO61%PirVQX^S`yblrN>| z2fK5l4-}o|{-Ed#H7Ghu4T{cDgQ6d)LD5gtpy+36P;{Oe6kVVOMdj3_=ocEK=pqeL zbcqHjx=e!<{YrxrRnQsh6BTPQe>k+ ziXv!`B0CLIG%Sj~x7+s%Aknk+^F^mXQMNt-spfDgUrNzc z4(I74P*jWigQD8hpeTwO6xE>yMbXrts4g`qsz(iq>QjTF2GpRaAvGy#M1vGHra_9D z&>%%kX^^63G)Pf%8l99uncgUB5oLwC*PHQVuB8S={i#XO02-udAPrJ9 zhz2Q&r$LImG)Peb4N~NzL5dP-kfJ0Sq$rsNDN3P1ic)EiB0mjMltzOT1!$0>bQ+{6 zg9a(eq(O>;G)Pev4N^3i1}Vy>VNn$4u;&UO(YNSG-vf&Nkl$W#<~Ur+mr^v;;hdWW ziiUB2P&Awx6pf$;MI)&}(I{$AG@2R|jiClb`P87OfEpAPQj?-08lZl) znoWZg&7nbx=F%WV*U=zF*VC{l%5&J)2_VsZVg#HapeRL=y20U6zLcT`4(IFXpy(#< z4~lN421N_0K~X6+C|X1fiWXCYqFbmz(GqG89=&+XwAkn{xbj}AwKPp8JIb6z@QuL_9X$yj)$GATz z+DHwG{zVOn9;XIHPf&xRC#gZvQ`Dg7X=+gP3^gd)L`{mGr9q0Gqd|%`(;!7#Xpo|< zG)U1l8l>oX8l>n28l>n&8l>nY8l>oD8l>nI8l>n|8l-4D4N~+P4N~+v4N~+54N~+b z4N~+L4N|m&1}WM}gB0zeVNvvm!`@B+iQZdVz}Wzbj>;G7ox2?_(PuPB(dRTs(NP+t=ok%B^aTx4^d${abesk$`icfAIzfXJmC+zYU(+B( z-_RgMCuxwPZ)uRC?`V*s?`c>R?RD6v2q4j)X;)|;DEh9Zh*J)i@}(4=bvWY#X4Pm1{B?`BmJ6Am-3|)MLC^^^FUD@ z?hlHhsX<8Wh#121O01K~Y0$P}GPT6g8#>MNOzlQBxYEs2L4X)SLz>YC(e( zwWL9cVrY<}Ry0UaYZ{~|mIf(mLxU8xr9q0?(I7?bX^^50G)U3aG)PfL8l5X^ z{-CHgH7M#s4T}0wgQ9-apy*m^P}H9q6b+yTMFXip(I9G46it1Q3efClu3gW1!<6?EE=R}Fbz_a zO@kEW&>%&*G)Pe%4U3}gPWwOsB>G+b+;tC7bWuM(JH+WyzLcU7PG|lIP&AVJgQ8K? zplCETC>lczit?#JQ2{k5Dx?NQMbx0Em>Lv~r6xt=Xpo}uG)U0|8l9oNDcaz4DPKy_znspqV?fd4+#eJ@K@EzY zqy|M#QG=qVsX@^*)Sze+H7I(P8WcT84T?5XlcFs&NYPdrq-YxrQuI6xQuG21QuHDX zQuGoHQuHznQuGQ9QuHbfQnZ~0DSC|tDSDj-DSCqjDSDFzDSC?rDcV7U6z!xzigwW; zMZ0N`qCGT7(Ow!BMUOe{QTamAPz7frC~BooK=wIZ%9m2~uG8r$1Vsn9KPY;S8Wg=x z4T?UX21OrIgQAb9LD4~KP;`hI6n#t$iVjngq9Zg&(I+%W(Wf*>(PuPB(dRTs(NP+t z=ok%B^aTx4^d${abesk$`icfAIzfXJmC+zYU(+B(-_RgMCuxwPZ)uRC?`V*s?`e>t zQ#44?4>U;8X&M$q?>Oy41d!s^4}e-VLK_Z(I7<;G)R%11}SpTAVp3Zq$rXGDRR*uMQ$3Ts2UAYRGkJXszHMk z)ucg+uA)JTYSFMLI_I>n7eJzq>vZ*xpeRir&DM@|DPKxa-ALz~<3Le8?hlIUQ-h)g z)S###H7IIC4T>65gQ6zXpr|P|C~8IxikefCq82nrQA--6D24_pYDI$-wWdLeVrh_~ zHZ(|4TN0(I7>gX^^5WG)Pfb8l>nN8l)(W1}XB; zAVuA1kfQE1EQ;zx+P@J%qHDJjaH1ovk^W@8qxFb%DPKxapGc>@1Qhk<{-CHIH7L54 z8Wi=X21Ns?LD4{JP&9}d6vb16A}=*4N}wi1J{qJbkp?MBqCtw1X^^568l)(d1}XB> zAVq03NKt?WDN3h7iZW=BqD&g3C`f}8Wzir-gK3bWY#O8}hXyIir9q1FXpo{IG)U1< z8l-3#4U3{)k@gM(Nc4w#6YC9%&gc~6@JN^Pr4)^hbowWOqA}bb6y;Ncq5^7AR7eeq zil{+RF*PU}OAU&~QG=rK)SzerH7P2gL5e2QAVrgCkfO;nNYNA;q-ZJ)QZ$VQDVk1$ z6wRPPie}OvMYCv-qS-V^(Ht72Xf6#>bR7*+bUh7HbOQ}iG>--;x{(GcnooliEucY) zZlYmPG&0gYO#q2rs6X&93KX@_kF4Ds=~BLwqQ#NUd!~S*Tev?cT0#wqmQsVFWz?W( zIW;J{l^PV?Mh%K?rv^oLP=lg7sY%gYG)U3iG)U1sG)U138l-3?4N`P34N|m<1}VCa z1}R!igB0CQgA_eLgA}cyL5kMWAVuqFkfH}^kfQZ8NYO(yNYTSINYNuSNYMrwr07u^ zr06jk7Dc6z_7??^=v}b_&LU8>KpUowkuK#+DS9%}`N=d;^c438MNdq(O?_qCtvw&>%%SX^^5_G)U2I8l-3s4N|n11}WM{gA~0@ zgA~0(!=mW%Nc-;sNc1;O0p|%&^m$7W`y*Y-ms0e8q_gQvQ1k)!2Sp!JgQAb9LD4~K zP;`hI6n#t$iVjnQq9fFx=o4yC^eHtd`iurC`kV$SI!c2S9iu^tzMw&hzNA5lj?*AT zU(p~%CuoqOG8&}lYZ|2J8yckOBn?vZEe%ri9Su_SJq=QHiUukAfd(l$O@kDjp+Sny z(jZ0WXjl{-h_uHGAklTI3pnqAq9t|_KSsKgFQw>0q_c1~C@Savpy(HBP;`+R6kVbQ zMVF~T(XZ5?sDc_4{YDLney0XSe^8U6KWUJnzi5!6ziE)7e`t^*!-ZixDYDTZMG-Ve zk(~x9a?l_}P8y^rk_IVq(I7=`8lt1Q3efC zlu3gW1!<6?|Hs~Yz(-NFfBUmpCYz7~*#NuLG1oTm!=U3kM|M|T5S$DqI%$alM%r$4q zZjwO&EE){JqEY}Bl>xA*9Dqeb09Z5>fJMUqSTr1fMI!)MbTj~qjsf@v&5og z9gDh|MYGc-92*L$Uuw|_A-BWnX3n?)y*&7x6cvuHHgEE+>Li^h`8qH$!iXgt|0 znm{&-P9kH`$p9>x2*9FA04$mez@jMtESd_yqEi4^G!1}7(*amC1As*{0a$b@0EvqJ?C$Xc5^gT1+;JmXOV&rDU_{0y17F`O!q7?uvx(t9tmjkfq3IG;e3BaP204%x+fJLhSSadZ2i&g`$ zXbk|1)&j8T8UPku3&5i509bTA0E=z__!i9%1y_q8;RJm|bgo&Hr_Zi$429G$wP=0F zee^7|=oZSGMH|Rw(XC{&=r*!hbUWEBx`S*M-AOi!?joB-cazPcd&pRHF93_~17Okp z04&-Fz@i5LShNX%MGpe7=pg_WJq*C2M*vv#C;*E#1F+~Z02VzCz@jGrSo9!Ddf8I%%Ybm zZx+2mHjB2A&7xPyX3=)CS@as&EZRXfi(V(2MLWr6(HmqedJ}*}Zvn7q7XXXi24K-U z04#bJfJN^Cu;_gN7JUG~q7MOB^br7yJ_caXCjcz^6o5s$0a)}I0E_kju;_CD7VQOK z(H8(L`VxReUjclJUI+zSiy-0S^bg3qXci^wN3&mtLh6@Vv@hiLpKlg@PkFQG2eMi8 zBiStaiEI}AOg4*tA)7_NlFg$1WV7fuvRU*y8H@e^V38ANx9wOI0ANuJ0E>bEEUE#( zA{T%~u>dRz0k9|zfJN~DEUF2>q67dIB?7Q034le(04%Bnz@pj!EJ^`jQ5b+lsQ@gh z1Mn^SHWZvHf`pssFL?OQELx%#)r||OUusePICuF1v#0^(&7y{6v#1f-ENVH@%`t^nVnNL=tf5hNUJ zCgMcn{5$<^`jbT6;zH_|TGTVnef@m1=m^T2MMsj&qI|Mh)QfBu6_CxM-ej|=kZcz9 zA)7^g$!1YMG8Pp9u;?fN7WD^UQ856E1^}>VAOMR>09Z5#fJK7=SX2tYqA~y$l>@M7 z2mp(Q0nLuxJDTi;f0h(J=rlIu?LM#{sbDcz|zF_qgDG5hT1(zrEkXEXvhT z5f@Uw)S^*wZsWyf(P+w>MPtZj(O9xsG>&W*jVGH$6Ub)KNo2F=WU^T_k!%)CB4g2H z02WOFV9`_n7M%jXqG?MMPOZBH3Pc(~OQH#!v3#ngf(ZV=) z)Kar(5#`OI#bmQ+3E3=KN;ZowAe%+Y$Y#-nWV7fZvRSm8Y!+Qi#-d9ASac}>i&g-z z=rRBnT@JvaD*#w@B>;<70R02ZwRVA0h8ELsh~qBQ_4S_{CUYXDeuEdYzI17Okh z04%xzfJHX~u;?ZL7TpZ+EjlkQxKIQMx75eg=bJ@4^df0pTuA*=i*Ai`*DW)PZlkXQV41h(C1F+}`02Vz7z@jYxEP4unMNb2;Xe$7Vo&jLdvj8l5 z4uD0^1F+}?fN#+)alscwknkS;lI#YvXo!9s@?u;_{Zfmz#kpTyWEQYxn?K3D`wH#`jxfs;zH_|TJ&R_+vyUs=qJjXML(0xqF=~n(XV8) zXg}F3`i*QB{Z2NE{vex0PQ2Z>n?(UK7R3OtCV02Z|YU{PBD7PSLlQ8oaJasXJA3&5g002Z|e zU{MDE7Ig$*Q6~Tvbp~M3VE`=Z0>GlK04(YTz@ozeSkxWhTht&vxK;!S*VA9O-!R_4 z(;ps|&?7#ieyK(I@$O@nn?=1SZx$7h&7$69v#5}47WE;UMSaO;Q9rU-R75t5jv|{y z{mEEV48WoR04y2^z@icW77YSm(O>`;l>)G+41h)D04y2;z@ni5EE)#DqTv868Uetf zqXAfS3;>Ic1z^!}04zElfJGGmEII*zMI!;eMMuO3KM_H~*XT*?NV747EJ?S z(R2V7%>ZE0OaK<03c#Y%09Z5&fJL(bSado7i_QRG(HsC4oe99AvjA9hHUNv}0?4*(Ukx! zS_#0Ss{mNE3V=md1F&c{0E^ZDuxKp+i>?7+(X{|9x(lUg7Tpo=Ub5OOx|8x|(OqP- z=x(xEbPw4qx|eJg-A6Wy?kAf?8_8zT17x#k6B&yh1Ypra04#bKfJKi0u;@_$7HtM# z(PIECdK`d7PXMs!NdOjY0btQn04#bMfJIvYSo914i=G8w(Q^PSdLDp9F95LUMF1AP z1i+$~0lr1I#RoTvAmPjO_ZQu67R^+PUWpH>Uuw~7@$MUI&7vKYH;Y~;n?*axX3-mD zv*=B-S@ag!EZRjji{2)iMemT!qIbzy^d10<-UndO2LLSk5P(G=0kG&}02X}$z@kq9 zShO2}MV|q%Xb%93J_lgYUH}$-0l=a!0a)}E0E@l`V9_@KEczCJMc)CiXdeKJz6bag zy&50E&&EXpLCMOkFCs43YjYDPATnv>0<7G$%i zCD|-$MaH7m04!<)z@oMQENTb9qHF*bI}f5 z!vI*+1%O3e0a(-xfJKJ`u&6r#i+TXCs3!o6jsW-;HLe+4EP{mZRdJfsv^#zMO#jH5 zA@xfw>Rr>l3jRauPi2y7b1;C=w0N8vzqEpCb(KNDIG@Xn^GXPjL6M#jh0b z02a*xV9{&<7M%{jqB8(kGzWl1X9BS3EC3dr4Zxzg04$mZz@l>iSTrAiMdt#rXaN9= z&I4f4`2Z|h2*9F60N7S#$~6EV`6z7OfzgMVFDyqRYu<(G_GYx)OjzD*;$^6#$D?0kG(502ZwV zV9^=?7Oe$f(KP@px)y*%*8#BTdH@#P0KlRf0a$bs0E=!0V9`1N7Oe+h(JcTh+5o_! zTLD;f8^E_{Y0coVB1rhfWD(~Av*Sv2gqj8CbC)dAlWQ>h-?-;Ova)|09f=W0E;#Qu;?)W7CjEYq9*`Y^dta_ zwg9l`DF7Bd4ZxzU04#b2fJM&&u;@7e7CjHZq89*I^dbO@UIJjz%K$8T1%O4{09f=Y zz_;kmn!#&Dknjq15u;?=Y7VQCG(dPgx z+6%y;=Q0$|bC04(|jfJNT|u;@Dg7VQII(f0r>`T>ANKLW7mCxCC!j+(*U zB1m{kK*V|7EV|aaVXGNZztp1NYP#`vn?=7<-YoiqY!*2QcIR#u1;}Pm4B0FSlFgzT zWV6U6n?8|=+~OTY!M{FimS=5${ zMeP7slnub58~_&O0G)Nn?*%rv*;+YS=66w78R4tq5)*HXdu}vDj}OigUDvlU@{h!0+_>jAT966MXJ z$z-!=3fU~0N;Zp5A)7_h$Y#-WvRO2PY!=NVn?@+(QE(~oesdFGXPjL z2Y^Lq0T02ZAMz@oVTESd+vqH_RPG#`LP=K`>30RW5617Okl04!Pvz@kL}ELse} zq9p(LOY!Zu>H4$-6HjB2&Jokcxkou(-El+SW9x{tAro35n3E3>Vlx!BQ zAe%*(kvRSl}Y!+Qb#-ddKEV>$iMXLc=v<84hYXMkv4FHR-1z^#2 z04%y5fJHX|u;@kr7TpBEqMHF&v<`qp>j7AF3jm8Y0I=v*02bW_z@pm$Sab&fi|z#Y z7G0PS>?4AN^Ywez7nw!l^}6V;gpm5B7TuTNj(fx`x}Wl9(MGaa^Z?l`+C(;s9weJZ z50TBHhskEqBV@DaQLbG9e_oz0kCKXz_;k0gy2#U zB)p=Lh;y%5G+zg%*AqhOms<2zf_v*`vuGFP&7!x-X3;xjv*=y2S@a&+EP9`87JWcA zi#{ZqMIVvPqL0Z~^a%iqJ_TUWZU7d22Ed{{04(|(fJJ)&So8$|i@pS4(N_R0`Wk>m z-vF@aTL2b)2f(6z04(|*fJHw5u;@ns7X1XkqMrd+^a}useg*gzy^#>yCW3^gri(al znnjKE$BOnRgw!v!$Vqg+d)zDvB-)+4SrkJyi-Kgcs0P_Aa>-^Q zHj8SKu_yt6MTr0`N&;X}G60Ke0kEhx0EHx5)E&z+_0k9|nz@jJs zi|PZgr~v?r8UnDW5de!C1F)zG0E^N9SdV7WL+Y1W z)GX2My2UJNPIHHjCPk&7y3wS(HP@qFewLSu&6Ttiw*-|Q5OIfbp>EiHvkqL4#1-B04(YOz@nZ2EII;!MMna# zC?9}Dy#QEL0KlT&04yp5_!ea)29Fm(!b$p-qNa)doqnc%G}|XJq<*PIMG2GEGi?LMdf5H8Unzgp#Urz2Ed}>04y2- zz@no8Sab{ki;e|g(QyDQIv#*U6#y(c0f0p#0a$b*0EO?qFH3KXf_#(P6uGo82~Jr1Hhs)0a$bv0E^BBV9{Iv z7R>`-(K!Gtnh(IDa{*Yi0Dwj30kG(N02VC-V9_D~7A*!~(Gma_Ed^lF1pq8s2Ed{V z0lr0(5`%k0knqX+z3a(lQJy|Lx+pQEeyK&5Cb|jFn?)-qZx&rfHj6GNn?+ZU&7v#G zX3@Y{MXSkJv<84hYXMkv4FHR-1z^#204%y5fJHX|u;@kr7TpBE zqMHF&v<`qp>j7AF3jm8Y0I=v*02bW_z@pm$Sab&fi|zzq(Om#6x*LE+_W*p0E=~;Q ziXh>y^n2Hrm_>8-quF~CL+Y1W^gyCJ_(ij56XngK2gzp9Lu9k)VX|5D2-z%plx!Al zCYwc%ku;^s~7QF(%qHO>ydKG|0+W}bg8UTxS0I=wF02b{8V9^@@-=g~ygQtoh;ZO7t z(MGcFF4*-ik2Vl`&02X}#z@je!So9SDi@pY6(Ki4r`WApi-vO{_9{`KK z2Vl_;04(|ufJHw6u;^z17X1RiqF(`6v>$*)zX7o5cYtrvuEgL&B1rfw{TTmkvuKR| zdcHprL+Y1W6ijm8mgm`ZdgVH9jidwb^j)%96iYUXLS(Zjj%*gilg*-DGft?Ei>niNvM z)S{M2Zq{pNQ7g*ZSk#(q7PTRpMQzDuQ9H6(lub5^a>!;;F4-)~Bb!C-$yn3@fJGev zSkwuCMV$dybQl1Ox&W}KD*%hS0kG(B02XxzU{MbM7WD*R(GdVFIud|I`2Z~H1;C;L z02cKIU{N6ei~0bts4oDE`T=~4nkNPOi6G$$y}55;7Tu*56(xn#FSTeuk~`sbvuGgY z&7u;rSu}`j77ZqwMWtl3sElkDm6Oe)A!M^?DA_C;M#iGy04y2-z@no8Sab{ki;e|g z(QyDQIv#*U6#y(c0f0p#0a$b*0E4*Hx4&T)O{ctBG=ppw%_N&e zr;^R0)5vDgEV5ZNn`{=HPBx3qAe%*V$XIkH0E^B7VA0tCESd|zqIm!;ItPG7^8r|N zE&z)b0I=vh02ZAOz@mi!ELsG>qQw9#S^~hLr2s6t0Dwiy09bS(0E;dHV9{~_7F`VR zEt;AX+%AHIOLX`-#VmRvS;8erA@xfwx;)AK{w=fU3d);BSCY-5m1MK%DzaI$ifk5L zO*V^Glg*+vWV2{3*(|z-j78T1u;@Af7F`d(q8k8MbRz(ZZUSJ@%>XP~2f(8B04%x% zfJGYsSad4@i*5s8(d_^%x&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^m-=Y;s!3Mj; zqNjB%y38zEq`yLaV^T={Qi~o+au0vUEP9yoX3-;Lv*=N>S+tpK7ClBbiykMNMNg2; zq9@5_(H62<^b{G3o(5piRsa?~1HhtZ0a)}L0E?anV9^TzEP4@uMK1xc=w$#Fy#m0Z zZ2&BK6@W$C0a)}J0E>12u;_IF7VQLJ(Hj6PdJ}*}Zvn7q7r?h@Q&R8*5hQ%0{xPcu z&7v9lamd?AA@xfwdOyjX_nukw0p-o256NcHM`W|;W3pNF3E3?Alx!C5CYwc{k^`t`>5%%WYH z5@M1=>X%v+o9sUQfmsxyyjc`SHjCoPW>HPDS(HFFixSCZQ4-lKN+z2{wa8{sZ88?6 z0I(832o#1AL2WBnS73AmIwVpmvk}JNB_&7$^Xv#0~vEb2%$i#n09s51bI4g+9O7XTJ@ z1z=G(02Un%z@qK|Eb0NkqMiUOIs$-2M*^@YAAm)@09aH2z@pv&EGh(GQ6B&n^#x#2 zKL8dL0kG&O02cKJ_!hNF4z?FT!fW-Tv({$OX8ky%I60(#sYQd5-Lg;3qQR6mi%Q96 zQ5o4RDkqyoL&#>)P_kJxjBFMSC!0kh$Y#;eWGp%cfJMgwu;@4d799`3q6z>OodCe1 zkpL_@5r9Rb09Z5{fJI{fSTq)ZMdJWiG#-FO698Cr5&(-%24K-d02WOGV9{g%7EJ+Q z(NutM(ZJ;3EDy17F`O!q7?w&qUp)O zM?{eDNaygJ`lS}FOm^S>+$_3^@@CO0vRQOB*(_R3HjCDf&7!qrv*;SK zS#&MgEV_XP~2f(8B04%x%fJGYsSad4@i*5s8(d_^% zx&wekcLK2JE&vwY4Zxy%09bS{0E_MeVA1^mEZPXbq6Yw2vPD zVA1aYEcye0MNTcdZO5Vj0E=P(SQG?cQ4N4^(Fe)Fi$sv{3jN;ohi1`m{mPnKE2Ms@ zMe()VJHIuHYEs@TN+6p>iDa`ViEI`nlg*-9WV5I?*(^#Sn?+%=S(Hk~qB;O9stdrP zdH^hn0I(Gj)02ZYKuqXq7MVSCB$^u|fQven< z17J~e02Z|XU{Ol|7PSKS7KLgBcZeY2qx3;zTrK}je@J}^t!stUFSRJUmiyyAvnYr1 zW>GHLEXpIBMeWIEQ3tYF)RAl!bt0QZoylg=VPvzY3mJ>L0U{QAf7WDvN zQBMFC9Ra|iBLP^H55S^c04yp1U{P-X78L@ps1E>(`U0@19{`Jr09bSs0E_wqu&5Y- zMFRj>G!Woh)V5Zz(f4A}gZiOIJF_U&yJ4#pQoq!qvRZDBAI+k2%9}+)$Y#+{vRO2Y zY!(eCn?)nYX3^1Pv*;MIS#&JfEIN*iMaKiMr~-gRCjhW$Bmj#}1Ypr902Yk~V9^)= z7L5g9(KrAWjR#=S1OOJD1i+$`0a!E13qSb2Aj9MY}OD&pJ%bowTSu~sSX3^qQw9#S^~hLr2s6t z0Dwiy09bS(0E;dHV9{~_7F`U$qDuf+bSVIfRsgW*G5{7`4#1)-0KP@1)(YM%f`p6p zBzBrv)Kz~T?aEpq^-C?fx|aLQuV&F|%9}-N$Y#-6vRQNu*(|!2Y!+QdHjAz&n?*N} z&7vF0X3zhMe6`qv>t#(w*atc0|1L|1z^!_04%y4fJJuzu;@+z7TpEFqPqcD zbPoWF?ge1ceE=-FAAm(00a)|^0E;#Ou;@Vm7Ci*OqK5&#MOW1dekp>4+e>s;nMIfB zMbaa+Lh6@V^mr||*6(J~6O=cLo+O(^TgYb7Q)IK~X|h?gm24J0LpF<^C7VUhkbEEUE#(A{T%~u>dRz0ep)-t`$681PRY>DB^r#7Tv9E ztnFSEV-_V*-YiNcn?<$AW>IajS(HLHi^62HD3xp$)ghZjb;)K?Ju((W09X_SU{QSl z7Bv81Q9}S0H3DE!V*nO40bo%Y0E^NASd;<4qD%l5WdX3LDFBO_0kEh!0E=1xu&5;f zi&_D&s5JnK+5oVqEx@;^X6@i+5hR?emqH1({X6}c`q6B=+9CBzEy}CyzF)&EYEOBy zr~}z7>PR+=I+4wy&SbObFtSp02UPkuxJ1Piv|L)s04sT zg8*1G7~or!Q#%;zibdb*=V-ZR(M$SiY-#O~`lS{Pt?jl5nMK1WZx#(Fn?)nYX3^1P zv*;MIS#&JfEIN*C79CGEiz>)w(FtTM8VSIn69HH>3V=nU0a!E!fJI{gSTqiRMdJZj zGy#A`CjqeNWB?XT1Ypr502WOKV9^u+7EJ|U(J25dng+n4=>RO60l=b}04zEc;9FE) zJ6J4&gbVc>vqQ|H&-G_xPpchLzto~LYP*x-&7wJ!H;c|Bn?+}l&7!l(X3<=-Su~Gq z7M(*ji{_KfqI1b+(E>6Sod>|8^8r}25P(IC09dpbfJI9HShN&?MHc|DXc+*DE(BoF zMF1>X4#1*|0a$bi0E;dKV9^Qy7F`CwqRRnTbOiv5t^{DwN&psJ1@JAJT|0QO2oheB zA>y2F7Ol{SN2_Xw)GxJYZEg4N1heQG%9};klFg#)$Y#;?WV7f7vRQN^*(|z=Y!=;2 zHjCDg&7$>WEV>1NMH>KEbSnUhZUbP^?Eoyg1As+$0V02bX1z@mEqSadG{i|zwp z(ft4{+6cg+2LM>K34lcp0I02VzAz@kS0SoA0Wi#7v%i&obT?i4}7CHgV`8nbA) z{y@lMwL|KcTC}CM`*V_6^c3aIqNmAb(N?lq^bFZ7dX{V!Jx4Z+o+q0{FObcm7s+PP zOJpp18GuEv0I+Bq0E=D)V9|B}7QF_*q8$J%dL4j8I{{eq1^|oR1Ypry04&-Cz@oPS zSo976i{1rb(R%?gHD z>X%xyr?z`UZL{ce%9}-d$!5_PWV7f?vRU*M*(~~+Y!-b(HjBO`n?>J|&7yr|EczaR zMLz(r=tlq+{RF_Gp8;6(3jm9L1z^#B02ciQz@py)So8+~i<}g@ZO5Vj0E=P(SQG?c zQ4IhVxd1GR1z=GKfJJctEQ$wUQB8nv(eB#8(IQCr7ybQ3pP5B<^m$Q2N=W@ui)y8~ z3&LhmZOWTPDP*%KOg4*B$!1XqU@oOa0Ry$tnJw{(iM6HzlNgsYM-A+~?|;MV%;b7Ih|@ zMTe2iqAp~!s4Lkl>P9w;4kw#M-N|NA53*U*lZ-`20I=vt02bu~u&5URiwXc()Ej_B zg#aw-1Hhub04(YUz@j1m799n^qW%CZDh6QD000&Z1Yl7K0E-3zuxKy+kMOOf@=t=+nU#*-9R>rZX}yUH<8Vvo5^O;IhbMRx(P=xzWO-2=d)djVK<9{`K)2Vl`g02Vy}z@kk6EP4=t zMGpb6=wSdBJp#a@M*GuEP0kG(C02Vy~@GZI~CHS}q65f?4;#_MM{i+r{nG#aJ z)S|5^?uU)dqGu>?7ClQgi=HE!MbDGXq8G?!(TilW=q0jQ^fK8jdWCEjZ6jmRs{kz8 z4#1+<09dpGfJLtZuxKX$i{1cW(VGA)dJBL>y8u}9HUNv>0btR)04#bBfJN^Eu;>E- z7JUf7qK^Pr^f3U7J^^6SrvNP44e%{`DkT`#L@aXkXF#4di+<9dYWyrEq<*PIU!=IL z(#@hTDQ^~iMK+7RCYwdykj}MHj92FW6@6lEczLMMZW;B z=vM$1?FV4dZvZU%9e_oD0Iu*d~qQ7iz9LI5m^17J}+ z0E=n@uqXk5MTr0`N&@&6eV!5=D1wAHhDDscX3;?XI3zh7Qoq!qaM+!aX%?kY-Ylv^ zHjC<#&7yi_vnWC~i=t$+s6N>&YCtxN8j{VTMr15%48Wo$04z!aU{N{%i!uOMlnKD1 zEC3cY1z=G#02Va|U{MPI7PSOmQ7ZrzwFY2O8vquy1z=G-02XBfuqX$BMY#Yh$^&3g zdw_3I?Qrl?5hR?hPaRXj{+<46k;m;24yj*i(P3ft-lk?z7s{JOUCCxqH?moDIN2=f zPBx2rkjv78L-ns5bzM3ISNu2Y^L=0a(-zfJH?BEIJB+ zMg0L-R1CnP0RSu-2*9Ee02U1bV9{Uz7L@|9s0@HbGl704y2?@Ga^T4!$XZ zgtzENXPwQW4c-k~IHZ25MaPESUz?jn$5GxaI-YD6Rglf16Ub)KNU~XUBH1h&MK+5@ zlg*+rWV2{28H>gNuxLC0izWcD=p+CZoeaRDi2y8`1i+%n04$mUz@n)DEII{%MbiLS zG#!9NGXPjL6M#jh0b02a*xV9{&<7M%{jqB8(kGzZ{YbaXhF-a;&zpkGWo#w^;Z zKh=0xn#3w0og1%k8Bp5Pd1AdlFgz;WV2{7*(_Q@ z#-gPFEV=-IMauwKbRhtXE&^cDasU=x48WpG09bS>0E<=tu;?-X7F`a&qALJcbR__b zRsyi-DgYL(0$|bA04!P!z@jw(ELsb|qH6%YMQ4YDV?~hg^%C8=X3>-SE3vK(htw~p zo)hC{#oyUB;6!@JRkstVkY7hzBQh_^apEG^$@9s?$QJq4qO~KR%J)g?MB2z#Z=;b@ zWDSiX_sh54(j&jgg?rOTfqV_FWn@u?Ns?!n&Uhf>2SK^Y>mvG<2cVp z9zDx(UXHl)9A|r^|9r>U8Ckx-adt&sKi_fQi!@&BI3GnuEp?pTk#)-)XK&=IiyY_c zNT*92XJ6!u6^`>$gXMZ%bQu;p-9k5DvKp=X_YS{yU=o@Qg7X+ed*U3HzM9179 zJ0TFgYpQT8HnoNlWrS`>K_Eo4Mg=Xx^@gi z^-pqk2}Jd8Ds~S<^^f8m8HnDxS$0Sus(+TMUm&V~SEx7;)jtd~C=k`Z>`@+w>Yrv9 z9*FAi);~57)nAT&LLjQY-FkE&s=uCid?2d7Uv^?3s=pv~Y9Ok=;c-SFs=uOdRv@as zV{J|#s=p*_ZXl|^<>=f%RDVs)!a!7i&&bk1RDV&#MS-aPr2nOXsQ#$-6@jS!tnI2m zRDW1Q{C*2BP|%%ZCC{{nFg# zKvci=^kg8aUt8H4i0bzao)1LzgX5P2QT^m^dmySG-RulR_1XKbKvW-|z88q<)31*L zQGI-|I}p|T&%J@D-avdEi0T#KzCct@;XehUItK3#I5l(i?&Es@kgI=OZO4i2n35iH zoP-Ny$G#3S$b;ZOhvSu9BV>`h8l5O}10Bv(Ru*ua ze0eqcDpA?B%JxWpR@o+xJ)-PkxmLMXUX9i@(BT{4)a6fSrG|clIQDML3$9*Vc~%+2|fMLxP~+|aD*2=mJWPNUQJGr^Jw5me}S~g zQn&Wv((Hg7IfLB9FYZ4jD?KpSO`QGkv=h?g?4rZ~L&0QcG;gho66U z!P!n)b19-NTSqm^-rf1~EU!$xg~5qlnfcGhpX8OfmF}~ zPuU6!eC8&e_erpUx56bqd^1qXjW>NDtCp>K`nu~E%yBZFl|pyw8u!^6EBw-d zj!s&vXsVraF)M8T>b5j*L$fwDkY1Ga-L~lIWoOCy+{89teR{f+QB#U|tE(py+Dk9{ zWn)u*S@6OJsaba5qmR6F@9Ey={ZQxLu3lq)dT!r^(oM6(L+z$dsc_sU@h3TH=NkTl zbuD;%^;@#|MaJvpnIqG_o7~+=TV*)g$FV7!_B^`&bSLd*G_PpUG;QBATcZ`#fD94&MJ#DH?Xs12K{I_RZ(#_lMC->d6 zbB=6x%xQ8+mBq|}$XT)Ws!%x(HpC$E$CEPVIlGo7>@ zR;ERJ+v>G#ZY%co%4Z9@)bffnU-?2`Z>KcO%1LoDR?1N1we3cE_N>*7qUbrJhd1$x z*8ld{L0UBB!&iTp=GFGV?LR*|%Srp%id^m&iA~wNY0-PK$7Me*`s$at;=MHShv8@F zA>t-p8SQzPlh!ES?}Fzjv;Ed3x62-v1F_TR@##_|Hs$dTo||{JSEgH|V+J{CCt8_5 zD0A(17wz*8-p)_Hd$L#N!WWm^t@65wZ%*#sRE7;J)4qe(6R|1peE#4nzn)J=mQ44W zmU44)W3R|}bslTtq+KsXvs9I4l$V~~{Jl86 zSIT(ZH?*d|U90`VF|%Yp$~M&)-M_6@*Y}Is$>AZ*`{CNh+dF9!WpS-*8+DDi``!Yt z#JpF28t>J$fA0go$VN(CJ63lP-DUJq=M&$r+Fs?>Fo zl+x`Q?3dC}_i;fg?*dkI>yzK!1LAGH&^bW8R&v;N$1a<~nZQPon_vCnIe*XXuV3EB$#_W0JR)V%8p+90TmB;zu3!56tGWwg zQ!ZZk{5QT{{Z6>pA5Fj8e#K341az}PZ97>ft-bNftF@JGV*Z+~ax6%VU+!PHU6AzA z&-*V~BwIVn3Z38=auZYEdpqitX+HBjIkicdYnDI#mDDI@R`0lXpNtr1Ntx%Qbu;`j zF>!O9jAe4Izf+sOQYN(Nce28<-Fw7&E8KF|W&R46{{G5BU!~t)*nN{UVxyJ$gqGib z>x!SHN@@AoCw{Kyj@Xnp_MCsC_LcP7rky{^K-54kP;@{2Mn!=*87?w11$!slo;JU} zoB-1UgLFUklB)$R(#}UQal*=l>3%xFXKrHFvKC#us;|Cub5E&ShMG_M)$nTm?xyGV z%jssg6!}<+q>Yvd-PWrq8|ZVKY@+O?{i}bwRW?8hA9wT<{k_6(-oN1Cvz)Z8R%RPz zYMv43^>FCErOV5+NE!+D11&fx*$@LQ{qz(VrFXU~DJSEb)>mTNAo|||~ zyC-^i>-qYsr*6>!)lGb2{V7LytGWA%$9|A5TPbC}l`_SCnb?$7uWox*7L|T}y2q*} zUYSpJtvX7|$i=~<11C9YN7ePaXCBq`U%aTPSIuMVw(a(tyX&0WUz4>+b9Zc7ut)@1 zYK88lp09U&c)RRzsptH;XV;N>WPd)mak)Rzl|1-?oVCWv4WjOc�)Pe2!ekNRiIh zWi{}MZ2b7KMZSpJ7JT!plsQ$(Xdg7{Vtp_qW^2$Zb9{})W!~m&I==fbuW7rNFWf5K zzr%_Q_KU=(JhX5AO6>v}39h^AUVnoY-gfmz{&6|}zI}40-6w^#`$zkQwEIitVpN-Z z1?&0n`!DzUoA~m)P&ht5uiS zlx@E~x5__2pLk*Z;xn9#8gk35b*F8Y2`wG$YKQkt-|xTDKfF(fdFV(f?Tx(t88lO_ zT6N*WSa`|W^B$K?lJ4Bwa7@VSno;ikQ@yTvbQTP2GUeoS>D3atg?ZZ9qZ;_GwcPkRx&9;5f-sik+ml5sU zkC#ioi|s9Xoh8@NWp2ub+n3L9(mKjbh&HVoWj5^iK`(NpY1iHO!WzF!?Gq-6&9aAX zS@_HmPTF`YGubcWCf?a@yqv_O$m=g{T_(CpHP39@BbUM=`-A8IdX-3cmfTxtJ=ajC z%}GbL^fu@1zOSDkMP#S0x^lPg({Byl&y(>^is;^Xji&8hcE=Suyt|408^0pfOEo87 zvR#kE*p&O0{{PHALs3xoo{sU&%AG5`Rw^JJjbN_Gb5ylf5DX$_gb*i_-&x z-H*OSL?nQ*+5d5)EkD&z#*?#7{B4fD2L_nXuui(fPSd#{3&n?HKD%yF{bm*w>p z8xxGpIzz5u^cCw$D3fbFeZ@8l*39}!7SUI1Q08=(ODcWEei{>-b(Bo#D|WYpb#ir~ zuh>^4Jk!*1^cA~P!Y6XUuCLf#5@M5OLSNrVm?RbIE4D^3)(NBpnkAFjX2|Mtq)1XNsa)5boEk_-s9I;OBqtb0 zOA->25)u=-$l|pl2P~B$OI2%c*rL^zYO9o}b=I*}dULB*S=Ux+OVyJ?ZdE%XNzzcQ zIqFTww$<-gtuVHrJi2AgsMg5}Glt4K4$mr$0>T3fUxz$R>MDFh; zo!_|n+Ke@+&a_|C7M&B29hc{IUHam40!~bHc`rHTWylOiXE;tK%ZPK?j<#!Zvey#X zF6UqU8zeJixYM^A9KydovW(nY=-WG@a*VUQSl?;SV6Qy`<@!nI==(j=gSz^`Yjmo+ z^oY*UcbYnQjZSUwnmSnDXzJiKG*ydeTThjjzcO!1TCQ`XEr0V*E~BNzrTV5HX$PEP z`bL9Gy#_z-b>J|4qgAC|tCo4K8m4cws~XL-|-wci3U z0eM=c#Q&$cDjh92#>rjNTw2mnUOGKm-p9%-=)@hl<`bD{AOos|bJyrZw!CyHeLr4a za=_`EK1vEYr_NcU6LWn2r0o07-o8K6(Pt+53`DyuPEI~`q5aE2ty$)=9H z6n`Y=8hz>X;#9dDkXMY;aZQyeXF6AiDXTqea@XXF9E0SgtJilGM0O}<$fWK8f1l;9 z`9P-irE6a;S3>&IweObqJ@S%`?Y%}XT~r?l3oGr>64sH9D}5W|_qc}+O#V`;zm};d zdrDtS>tiR^={U=2v_>b>z1T^kPU?YTb5#O=oU_zqXCPp*|^4f;=GHC4 z*PN--CQOh8~Xs5HYW%dEHawbe3HF4(XF*%b)jv7B<^8fK>OrJfydQXfSpOZgr^vns9 zrxZ+?Hl|%=U(A{@&Fd1sM+Qxsa+37<^qjJ(Bd49*XXfOJa@m$~gC@?LUQwFgc|a$2 zlWgq&;M)Hy5}Z16#u(ifa#Z>njmga(rIJ;Q9y502%!xB9X3U;CW_tE`byq|fJz??; z3G$JG=vOgn%A`qCCRdD{IzgCdT~<(7A)PX+z~jQ?;tf3~XjMLP+<^R1A{9T_A>g{H z|MH(3hz*VnxOIaKvfV&%Y`RXR>r}QISA8nmbz=v*;n;vq^pJ^EH#JQrbCk(@t`k!u zP}fb+w_0w7z6tlDmT2!b(8c7fk^Vnb{x3y6mglB6u1p!7-PGVLE#c2i^(K4djB``H zYP4ppuIE2hS63EGm8CP>j7+NYS8>QKZY`?_H*-@PdaaRqI|XN_+jRZlY&t@lL$k(N z^Q?}hZn!mtT{p`Ox2a08InssUA^{omtyGW7jcg)S$ECaRvB9M7DFr^$@;sN-`~xwzrC0(v)jAvW#NcU=D76(ZmZb3Zj!fgwl_CM%5@YR zqZR7AZe>HAXyG>XxPtmRWedcLKJn>Z%V=S|^oHN!9&WmjV?BbDDI>2~N(=%L|?^ReL+Tf$n#IG9d36o*h-$_u)U|bsJY(F)OP69%)!@fqzwV z^#a;L-GL3#yr#wHt(xi)sl9yA>UG6+ z|Ie>?ociK6lwA^YYOQ9iq@@S%os5H8KEisphub*dwiE4BtdAo4UdwIgML9O~J=>eB z+P9FX+NbGzy5XGv5bJJ<37(qmuPsW~7hFj;5Hc~fGMbN`Ht%aK+``gcQ$fdQc%xTgeHcKWmy!J{3N&kL3 zeVh7QyLmrUX&b~w-7Fm$O#Lirz~4>Eaj08Yd1Pg}Ej4@HSb1>#O|SlSYl{!@5Ni+{ zakEfu6{<--Lyd$TTr@5W9Y;dNu+?zsL2t?{$Ld4TvWw54>Xm2t1T^xExy%l5}TUYE-y<@&^kWo)k%sB#Qr;(_Z|mv zGVd|@b)@0qsqKumnq-Y$)C$|XjU+bd-@a{5TNS&iN~-wR?@?`8z|C6g)(>WOck9Lm zkI(iFzPd6v=()Hqr(M0Qk<&q*)$YY?ncd#)B8xTGLA#5N*IBw2J&&iR<)qo9t|rHA z7I5p=aht~m@`5$9TLvd)r@8e73*fz_9t=K9&CJZm49@D#tpEDEwy=5dR4S;fv}(;Q zWWHRnS_9fu&G1?&Cz6Ajt644!ntMz78`47F{N?m~q08%aWh1!=j18uC*KKW|(YA@V zgp7jC8+xm#=QeNTP1JRpH})o^o0{kZouj88sYuK9_s&Gs*DQNPPL;ZLZ%V4wcPXoH zMShZ1=@oEH@ZPhtUA_91Q)*p(i1ofp&n>ps2cmy2^L>|fV-PB3iK7&(J`3*@*}!}U0IGOw}i z)2yyC!O+XNiKcRM9B^~x8d(pWKQQ{^C^I({20bYX9OqrdOdU?cFTD zN-yQPS^lokl;xjKy%{-rtEVkX3U=&Xx!?WWTPz*%w-$9R{>$ zgWwU0@~iG3|7+y$*Zi1Q|D!TiR@MJ!rWYgrX8phS|3CCYOTDIU7@Sf4B*ysj@4j== zqntg(`s>lq?tA_F3hyb!!NcDnjlD@ynLhot}7j#D~0^ii`*RQIQHk$ zi@$2QqRX@jcdKO^A`eB=IrI7R?N+REe$|=p;Q4ln`xjX6Mf`_E z2VT+2RjWKCI>b)QJE#-w5VNlTi`$(x((cTrdXmx}(v;qBp9~)*jTAiBuH)Xm(scwtv z_kL!GZQH>|fNYySX>Q@&x%!U{n`gM4GTj#5t)2DHA+4jiT!D4Wa$9&ehgOhV!kGSc zW&BTFEZeOW|64moAAIYbtk>@5RX62-anCG=05|a5@%s6Ywy?h3&B`6BK518x(sQ!9 zWw>3M$$fa`g8{l2PSO z?tkJ=57~zzeGBgqL*+hVU-|Fu0!abil|M;XSL7=C#n~ z9e70OBhPAMVnCjW$wgQ2nVCoFMOViT?Q)yu$`1_Y@r)v(k0rUtI{3owuXvrdhgjgB zKkYm05Y|K!4t~#Y8wVea+3M=2!;NL{`tSC6^j{sca&*ZU>Mz#+-&#D!ZJj2CbAm%+ z$^!qJ70T10dtzoB_#h!8xB8QWswW8kCFuWql3dzJYbV3_(3Nx?^K~n^sp!4 zJ^W|v-UX@ujJ>1YqWbNK>c^t>|7WXf&jnh&)^2^dcsbyd`yXtEe-$BLoan=P?=D5!;61GO?q&4`Bt!hk^go?x9lTH; zK+Aa~B3kNjJ(1Mb}On#jeu z3~>MN&RxcL{|42%`XBDxy~oRyckcc$=H0n7qWO33B>$t!f9uX&?zrU%ksg7x%*Ow} zeVp@eJt@lgAFRUb#_CT1jT)Bd{rG3rqF zovtHO?uT=;c=F;`&aEi!v$H={@G+XNNd!Xuo^VK-888pY=(5gph|LCS}U)}z0 z)-WBo^=??6&SkZ3>i4%_hi_BI=5qR#(_7WLM_3>J#pAhyZZiDmX!41@cZQJ)z4M9O z4R_Fq7WVi~?$-{OFL%S<{FZ;3?_oK;dW%;TGtA?;^n=b;{s&Xu_Ep;ojupOkz|U%vY& z3yY;${-^MMgAYl(Onq1&gO*$_|KGLA)i<#Ew(8NLTiN5^c&4f!LAJ=&XR2~Heh3fC z|Cg4po1sq^WmFyE?LTQ=mNxIe{pKZUzjp@FubW>kpW(~5oo||Xl>c?-rkQT!&tG%a z?;z{#l=n5~bhmbUDY;Fq>*dMqi)TqmePVY=PbX4hgKN)}XTAF6u(p|QntsX1TKLy@ zZt^7KqSK{-|AC#|?WbyUYPkn~h#%8KevYJ1*`SKT($b2efkX3)i+We&m-Zbppm1Qh z!;AriWo7w&3oFV?N-By=2KIGI3;R~&1REC>b!QxUgK795S%Tmg`f{ zuj0h21@lXLR}3sEmxap;OUny;SI#+VkgRmbz_KBO29@ZHia|xg3yUlIl#~w0FZXMd zRUNo^ui}z|{uRCR%kwJ+4jIs^uvE9Bq|{%!Lzn6m4=kxD8`7(+ptMLA>r*mhU~g}+ z!@BhI-n$;q%+kWLK_${ce@z`_8TvxoURau6R;}gq+kmpZ6}^V^=_BheD>}NcvdEvd ztZ0DtrnijtWUt)n4J{g2F@%b{TI2Hi9I!}1>4-t)C9=uI#TA1}iUyV!+9tQR<@4oT zelVj$`-&Of7W6)#c&}plsf^M--fk!ym@l!nQ_`obBEPr4noi!*+Oj^?HoUOBAN^Y~ zsNaYR+1CSPFBjyO7nKb3`>AVX!MuWMC5uW2SM(CcdKZ=XmC={}Ds^SvZmTFR8rZ+G z*M=4KDXPdH>RXJ-= zerZwph{~u^56B-l!ggKND!koRR#N7*pto3E*?>-7{cMFT*C$VokBYLAK7A?-3@RL0IS-Y4l@|5wS3XdBw4$uAyj+iEs_s)z+}~?% zhmQV{)5)vRt2`Iv9ZVh)g>7GTv6*?&eU)n~Dk|-hUr|_4P?6WG$PV*@0}e%RXz5*) z-?yS{OHhC?da@XIJ8K945`3S@ zb9(%kpZD`w>>IDI%0#is(YJl&p6I3BU!gydRX%Zg>69rm3dT&EF=6b4QSxJ0L&r?> zrzT99TsE_6v{pl^w%tGAs_i^6LH0>S;qZdO!rs;T%=U;3@#Xn4MD;HmQPC&ANQarq zhWg#Et&zSd8B!_}a*+2aE-I)x?RbZYj;59SF0Xy%2qR;SKLW@AFnZ>sNwX{0?H!MW zB}E4wx6~}>fdM6@>Vpo{{wmsgN9e>UlgFjYsOhnetUgaBC@VX$tfcBZspp-_c{cEu z78VzJCkO4U!UILF+Geq-sE^+%ehWHRtHm4mbSLT%>zz)ml?RB+s8f+&P%xx4zre=O z%J%e=6Ya2k+0gQ$0fn-cY~PQaIeAoWZWnKjT`Juus8;<`q`%N1d!}w231o$dEI{&c4#jss*Id zUZweRg<(Qzjk2$*AJNirjQ+(XWj3aCsjN_Tir=5Tm?-pi|MUstCXX4NEbI6dgUf$J1MOi<&RPvXU(UozwT9pF|W#qJLC~DI6<;kG!mn-zF znmM`p=Iau2GOBEN@Akdz3|(3{u(!Bd?Q~GNgA2TCF>^+Gaq_q^6=Noko-lH9g&tXz zD=R84F6^6MYzLrRbo7=Hpz5sa*zx^O-MrMAZZ|> zcNIYhO+Y|E5NRSsRK$XUT>&AeC@KgjMFmC0f(nrmEb#w+XU^Gd(BJbs?|Z%f>&bQP zo;hdQJu{z~x$k>6yKPD>h$j<|R!H^2oUfI@Y!c)f-8E-oPFCiSky+`Jasxvq_mqE| z4eo<~z4w-2mC`lMyy^yTb-L`sF=B5A#STc2Dai zm#~l{*`|ZFPf9l%f_FcudB(;2QhfbOs{S#;y+SJdhaBya>xQ0uK|)JFmphkSQF=

    pG>mVimVt$%!HL1S>1uw$hf5Rx^Ckw6Q8A z=2_d-WOP`{m@#9$hAA!oQI=9S`%;zoR9RAdTHk-nk&q&H54k(*)y>>D))m^Ug6XmI z#E0MQePnCA?SdC_+5N$Vmh3aFie_QQS#!u8*Bp>TZ3S`_3^@wsF)wLy-q4Z= zsXd!50kaIPWl2M_^gsHCj2~|;Q(B<^QW)!^-y<q?bJyZ_8yrsxa3E8V5Gid!*u7@U4=K4z7!NCT6TP($Dx^k`7?ISTYJ)}LF zpgkm^H!Cf7XmdKbk95K$1mx0eZBeOHj;D^+k%GsIVQ62$f6*#U@+GB}ZZen9*EKG| z{8oojx3gfy=AY-5^dQJi`4T7}VQ8O& zR_C}oEgHK?`^~Cb1xJ{tfYzqdy6fe}tT1^0%dv85>d7b#TJUGJV@K#U!W>n)k*Zt= zYi=w~X1Xs6oejD$Hjd+h%anTy7q1mEtV!zH81hQPBv{Ij{gB=xE!ii{WjRRQrH(G$ zFI=Swj}}A$@=0a6zhIJ;C0|@p(i!BH+PruHHRJD}w3 z3NAF*dW?%V`xApBLUv@2#Ge0JuQ#u;>}SxDSS>`eOj37}ZD5(CjVldFUxLrPjitxQ zUCf+H?nTysoVleYx4KvplBJEFm|{*MP4wX6f@e}vpR8We$0s`z3&irIhmU(uE-4t) z)+0(;vLxxz$kc0X370y_zgD7oa7*=Cma5MO+XrkPTManw1?Sqxj&@pW$h1X zCWh<}y^(5LDJ!#&ucwR&xhu0h=`HEP@X9sYn2;}ZuV6b}TaV@nB(zN;{lvZmxrWHqzNfjLf>UKmV_Lc*(A~iO7V_Oq|F6EW zsOym2Nkh#&s!c`~QcuOWc#AEoFP&q!g-Oy9ltyz_Qc7HA$$T8!D_zOfz6m}ixS_!o zJT?hQ2_?tHtG)GH6M9^%yQg`etw#+y7}{fRwkU77Zj{tayC(jJx~U%Eeu-A=n$616 z=f1)#Ri8xZB#|Cus}g9IL%ZM20qdbcYFyu}gzi0YO9|~$H;eYqo2J#m<8}u79?eCT zbk2LFM=$hLD(PO*jkQjKQWu|Kw}CD(xEn)x3%0wlZ_R#lbG5vJm)yIoPH-Kmtx0nt z?Ga|F&0DScKX=&XkOO=e<7`$2s_gl#IOBkgKqG58gk`ou>V= zoX+Io-)_Iw#W>g{$LY-nQ9St>>e21d%es*1WtTZF(sF1^cj<;So1`u_}tMy`0C&f40V>q2cwkGu8 zmwIl5&Fs}Z&^@h>wHMex(gzQ^T&vx|QpQU!w>(5NAMlu?we`c1A(e$voi=9iytvnB z+sF*GAJrVNdVY0~ts!q{7b=#jPY;sh%wQK5S88n=FD*D1LwaLNw?tUKF;^@HAXs+u z6qMUm&$u31A(Zn&Dj)ypR1E11##VW)o?Kn5)eK|tPdCi=HFANJ(*_wGYn0Nwp*)jS0E^p}f{TLPuM*ey%dzs!B_bUvR&exX7g= z7$l^2E!EN#+m=A{;`;S|Z{EoMt(mIqD12;m z=~9wpDVbTxiE-({eabyy^`eG+xWQ^Cn7byl_Gvcg`p5%oePo}8XV5H=)w{3VHaFe_ z^xmeA_<7CZBVx`OpAy$SAZKx+bfw);HPQ{aaq^PGl9DD*1m&6{owIS>L%Qtr*q9GM zgB>SU^TevHm%4lYOJ{&}CYAKqS`RZ=*pkXxsRoL!QcjItvZ*Yu?mnx5VGi+XZ1sU= zWw8~^1&3VRlY0c@@L4CPPf#f7&g&B=4Q*ayZh4d@$od8tOE5@zlXZR~I%ELuWbg6#dIEVDjf=<4~Q4Yq&0Ru`;pe`sUJLMWtq zqRlGocI+nWqQNzqSA)#|^b{3)j>QUAovcQRNwM}ua$)Apr+Zw1I@tboH?Xq8}wO zx+NrZjB2Eh0piAwib@=nJ7n-+c`DeGUv+Cf8Q@pgHvZ4g3FNy><-47Y>+&bx@iVnT z`J0Tc`UR)>(=YaouTXDxnK_;Z+;hX`x#l|`bS$txWQ(uR-qE9M*$VaI%Q;3lL^H}c zTH8&ZVZO`HAa;<2(82hNAQdGt@-=Pk1muNAL4cXp8B=% z=ASkHw;^7~FOjcfxBjg0jpR$V>2-Wx`QmAMEuVf7HNB1>Dc{FVuj5nXtG4OQ<%f73 zuV2d@I)1GD&IrAZ53gO~&H1BBJcm>rhJ5dM$e(=EbcoaO^1a$2e-0zKszRwMQ_znKv8~g(| z_~keFH8=PTH~6P-@P}{k-`?PhZt$U}gl-SN&Di`DPQ8gny}|#}hZG?fs~amNt@IJ{ zjgQYuu5I2JZ^+Cs|9I?*db9Q51=WxLlP4!PUPMdQY<_U0WVAje3_5+9B|mE*ud)pd zW3*}`!?+J#k5k#k!i2z~1HC=U*as=M80Aj`5xr@ zgPLWV%1;p^x63s~m!rRnsd=QTEbj?Xdo%g5V%6sIwe9i+)Vllv=tAg9=o8Rw(6^xP zLp^fJ>HH&AWqq?%Wj&ulSGcY58|75g{2a7u8Eg7M(B;tesxsXVs*Me!M_FsSd{xPR zl2cYSS#Bn(cd5#BJ5^=-;C%@?(|ke_>2A0yx7FL3JgZK3)#_3H0a^~w(n$f;dc z4%iA+$#+0+k!zzazm}>TzmD*0MRoai$R$9>r>n|(^_T0)wla)tRas6U^cz)~?hg5C ze9c#=wl<6;xz_4@^PstMtyMo>Ri^tCdR|rL?=II`9Y0%C*Z-D!na+?e{nzmaRmInm zulQHZhAvT+`Sw8nfX2wRTJyos`{Y`zeut{ezgxbQUzhv7s%-za@IB>c5;V_OmFe{- ztaQ8YRh9WZfYy?0x%!2oTHXe7Emt3}D)T=He@#{PM^u!hNzh#AG^k)@*k##rxD9(< z!;r&ds@}5H%Vrt&D8s0uDsNI`GnZAH+7@~{G#;7`?FG$)4u_6|PKVBhE`e@AD ze%Q}c`5h`#6QDk58nhR505k_W6gmnz0Xi8v9XbcP0J;?VDD*MtCg>LE3(%LLZ$jUJ zz6bpndKCHv^bAyg8e8|*1!yr;Dx+o|X1DYvXk};(s9ukC{>IQ4XglZ~&_rkoG!xn% zngh*;j)C3{y&pOox&ZnxbQN?x^eO1`Q2nWIE$3U%y-@w_WX%sjk3mmCzlZ(;)t^|_ z>Gh|=RrP+NS_T>ptpcqDtq*MqZ3XQJje{mb)1bYfcR~k4M?l9zCqoOMbDwSyTg$Nux)Hh+ zs=u_YI9`j7hg&^=PGQU3|lBXtM$ zH$%Hiy+i!~=<+(2-vB)kZTYj%s0NmA2E9uv7&`w1=(AE6QvW)%sHx?zL)%M5M8_vW zr+F>E09q(@C>?(YT2?A7>Z?H0+gtul=!%Y(-vs@lv*mw;*6m{X7SQ}S%TIznpJ4en zp%)V^Z%eYYW3r|4c}TMy1%68xLElZW{9$PMG|N|m_QPZ`IfH%?K#}?IndQ3 zE&mksv^3t1SU z>@rJJp$|M_`DM@pk6QjXG;+1&YeW04wfqq1x^Q+hqB6(6O5>e?Rn< zr!2o0`qviAmwCq0_-8FmgU);2@{d42-e&oe(8}8_UkBR%Wy=qRu7B0?&q2SJioWij z-=R(4vU~^V_??!Y4t;I6<@Z6a?Xi5hy_R;}XK4oX!S^ixDD>cd%YO;I<$&d*p#wj* z{4nUogO+~*`opJ|zXWZ5)bgF66F;~74CoujE&m?W_`>oxL6g3+d?s|^Y0IyIe)^5& zPeH4GXZiZjL1!&L0{X;{mVXiY)6bT_0*(3A^0!0pK5zM1(6@>#zaMJ9WciBF41Yg#Ch|q_OQ9=}Z-CzneFpi<@UKI6 zBL5J240;CR&qB{3zX}bLhY@<5DnX;5&7d8jiK?<+e9-R52dK*aTLfJJ-4Fc&TCs&S zT>|uO=rhor&?4xc(26nEd|jcb&}`^3=vwF@=nqgsIvlioRiG`PNzg&iNzjGRN1%J4 zm!XZM!&H~&g${YfyJvYrg8x=FlAIaOgVdVd(eJ>g}xgQ=v1VuRwo--rC-pt_O4obQSbt z=;u&p2W$HF(2>yf(8Ex7M{BxH&@s@B(9fX1Krchfbh75V6`BF<4_yo`gkFI*m7iwU zS=r~n5za~MaL1#i2Ko>(-Lf1k!L$^R*g1!RX1>Flh06hpj z4*e4PJ@hB&@6apINJH*BQhsUHm@3T`Q|mw*L7PIQd0>w32#td#LZv!xj?aYlhYo^D z_17Ff5;_5T4|D@`GxS;LHt1_msrH!5c^CQtRH_?h{u%T%^jqjTsNBZQ>HdJqZP)ZJ zo27EwG<_v#6{y+IDf=rLUM{QVbaJ^cH51wgItZEz9R?i*y$3o4IurT;bP04hbPe=z z=oaX6&>hg%pk{xhl=oNoOVF!OeYC8{-w7=b4Tn~T)`HfDn*Eb9pBKIjvW6lR z_J*4MlrsNdc(b2U{8;#j&?(UA(D~3s(B;sT(2dY1p>IRqf$oQX1U(8p4*eSX9n|cX zlyY5%cRQ^8RSsGSYW7dcbS>b`{z∋JZM(K?BfCXdmbr=;P3*pj)Bap|3)BLkpp1 zzoM-75d3lIm(XvaKR_=)FG2r;$|Gcx3lG%nXO!huhOY{Zg4TmJftvk|GJQMvPS6Bs zH)t9(6FLBz1vUE}WjQ0@CqVCkPJ_;b&WA37J_20@-2mMTHTxlD`7gr10o@6G5BeeW zPv~{1TjtgCryR5rv)u)1d>PSho4D_Y2VN&^MvGpzlFHgnkG85qbf733?4`53`nE7HalO$~d!MQnUtg5yM_nK6`=d zuZVR$g7SQn$C!pa+I;+IjyIZ5m^^A?POj+0@s{RuNd7^1qS0LcBiCr2J7I#+T>gi+ zxrWXEhfm|JIR@)LV8}<;mK{&@2c`T7g9oYq`-jn5e+6UFsNZJsl6;`m{?lP1by{}2A;v8uEj<+(iOkw>1T z{^W9I{?(CpolZ`B^Y6y#be#S*l$S?d|J`&kGR=+a)z75xPfi>2PwNw9yDCyLt4KGU0%U^Hsc3@Mwh4ifXf>#!<m&$WUUA6s^fOOf-VPb&Ji3epvb_E+ zb;$bTxNTxXm*CW%88Ggz5 z$LWqqpu_y@yvt@t*KP1m*Qb^UF3Zz8E&sSK zRh}z4?x0MkoK}(H2J+J7>GE}*JU3*}h}vs2DsUm(>>XyKat? z-zU+(M)FyPsz$RP&!>HyGH2V7;@94>JzVpAEqldvj)&vUpP92Vse6&Vk~`_9q{8Ca zG4BQni#>G;iwk3p6g#~}lRrRPvB&6del3N?-yOXV@PkYTyLj*yOhK5#$LYOs-SLR@wu3^i&ZOaku{$)tasx=RQmc$%VRZ>SNIdY%{o?8 z-)$ET$Js6|j3_KV9c8=RFXK$k_ygL&|i}duCXc-G1SZnX3b9{A+w` z&C;e_T$HEfT@{$=m$_p;MTw6U8!_J6d!$TL1LfNumhu|6{dppz*xBO6_`S02mkxEi zTv3M3MWtQbZ9kD?)ZJTru+E8Lk>{tUrJXOZ+s?O}A=?mIit@*7}G$B7f=O+}M9;b68Up_rP_VQO9(k@PSq+MJud#P*H zwDa}~Y3Hw(w>6YwwnUGcyo984F^Pdw#jTg>ki3leWOoBqdFfP|6{uf->6diXPI}}| z>yU9FKX!eQKURn36)vwRdF_^0Oe@)vb7OVL8;~PXR)^#mIP4eRiML%y&M+=~8f(Aw zcjSgkb#3b}ZP)p;?U(EK=yTc#za{pj>J_3gZo0N<l_38EfJDkZ`f9d<| zSN?_i0dj=j6B>JE>OM#)%7M;=ZZfs6dEP!{9{;COctpQ8&)l%2O@Sx;);VY7=y|2D zje$-6O}-~gs=8f{NU-+s?vV4XlAH~3=jRk87v;uOj&7WEThglTPv#0|wv}=W4;uPj zXgr!6m3=1n!4%h}g0Wn0rD5SMm7~o3CGo1u^7Z|&`F`%ubbqD%b+*5b$hnt!I43fC zZc63s!?}}#TplV8_lA3w%tONTym)KKgQUEvKO7n*OIaISiZGI}r}$vZq`)4za@`eN zR&tR$`e<=@q%0%iXmMp|RcK99hxzstpAN5--A|UdGPuOpqKeU#vU^IlDkRHowMWXt zwIvt5JVDpz53Vo1sFJKN3d^qtZ3Jyz zk#tAMaOaTWjv>SCLx$Ui47Uyr%N4PkTo202^|wLV#Twq&BKL%5{xYeu9$R7YL_LG` z+|8Dk@*S0zoqBryL#}t$J8T8!`MG7t=p9vx2F_W%p?q=T17mJ~a$uIH_?NC@?s)N; zK96aS+b+YXZN$Dh_q^R9{kkvDJ#WOyxtdshiLu$3m~m$0yzN!@yH7Ssyw+>miP}G1 zd|}7X%U{g-%-dwl!N*_UGi-Y1k7HkQAaCVP4Y_p-leeTuU|ll+cyS2nyO@^|aK*Sj@;m$|oo&M$kxDOWGU z8<6qlwJlrMaZ>J3;cYS#j~{y_@T&h+-)rWvDyT1aop2*s?oM%fXWE*wy}Pv^Pp6;G zF)kenKP}h&bK$)D>lqq*zG&_CYh7bE zn|EAsQJdu6V7=?{$;%%gd*BH6KtfSsQbN&ZQig;cX&39{t(N~5)IB0|=rK)~mmF8? z>K|Klpuo1e?1h2^TPOR^vmB?2io( zH7YR5zrVQVZaq%c*(XlsJ?K4NTr(!iZd{l!N6IMlSFK!7KQAr2yUe{iSC=t1SLQso zK1bJ(og?c#EoG@0`|nE{C`%eMC+(uQXP-b{e_vleEvGr{YZq*u=@%!zP|#4;aZCK= z^<8bNdjv95Z7ppN_b^M}L)LS8Y=*3}W_E_mSJT{Pl4V=HEWXR-E-w_+k@+L52kInC z4a1O{Mfiyv`=vvXCvp;fiE;%=GKmSjmIyZq6;cwF4Y}WzH}47#xwo8)2^7Ve&S^TK z!o2S&Vb&Rb_h~t4<=z|CX2s#}Kl$sAwO6Oxci$ShYI}`k_g-rWi+es+2lj;w0L z%l$I1yb%*6wfnRARgL%CBtFwe#;v)yZ-wOTZy&X(!5=S9{dA9H&SuLtW-Pi^Id9;- z{$VekpEvmW_SMUt$yvEMJMF+zkNSw8YFCg*}z4qKb8@yCyC32gB{<9o(DhL6jz+?70XoTau_wN|W< zW89Tc)HX5kayk2{;;wr)rff>yB(>1f1$$-5^4h((xR^E1beS)fj8xCAp8v3QU+OVG z2n7zLj#1C-%A$RO;nP+n3>XeW>)FMRd3sM)Tb7q)zE%MA+5LoD6=v!o#D(&Lf zyr?=dKIXyH*dlxMZAtTGI|_|?QfK%&H!pjf)*8m;gss|{2O!g@&*L*a`T3-v;TEO>ea1uj@Zlj<{i6NAV$h~ zI;O&!YPB5~IvcE=OKYWzRrk4cDE9JNsdt=<=^L$k#UF^4dV5JdpS8TiK%!s1xJvIk zW-YJ6O1&N=1iJdW`V!6Zb`2yZ>on%|NbcMPj))ZV_~o1#*4J*kFnM-tAl4t}vuX}{ zoJ+P%j-pJZTV^|Nn<*t~TR+g=zbTjJeYTt%?!JbnqQ~&;j@|NyG3E5Yoa@K#uRNv2 zGrx75-EPBuJ7<2{^pqn}t^u}@vut%nYAfA7bL)7Y<}X^CU4t}xyHe#je=Unk^-%7yfNov$G68SJrK6C!PQy|n$>I;ef#TBr5~4mvg7h%1yf%J2jywp+R``BWaKLmiTuUJHNJFh;{BR zKDc{#apBmo?7g|-Fv^(LJjZH;+|%G z`e<=qQ?2^zK%0z{S7G=lU#0AFtY`OfMvY4uC#}(sau(($=LKXNb&GYoMh0?Ibi49o ztM~pM+v|@bx?hIMwE1YcDs3if8E1y|7uMR$8Z2kh5S&ReHg|9!!zZUoZou3(u|>|< z>_DpDT92MN_NV~?pD$h35*YrNcwdpnk?7Y_tQFU{PGTS~by;ptX#qGR^!zv~=Zf}= zWSH#lL*1rF-R^;QDf^^PV4v&}*5a&dMzYlTyZK|Z1}E2y(^1i~?Pw9C%bhN|vFyik zavj07dZ4t*`bdkccS6z3UI|5;()-rw5QvgPTVCn%GFT?AucgV2E2(*) zxxa<4g`Tq+y2td@EYQr~+}GSJb;PRpqJ+*-4P%SqqdiHtb#IdD(JR{S*qF0Yr#mRM zvBLDc>=e28o~ZFl?y48wSli`9@j$%~dzRRZcXk^EHe<1zPv_(Hyn4He5t~@PK>DEM z92sjAT<$onYSN>3#zjk&fjIbTe?soqDKQ`>|eQkHOo-Nkx9wOgc>d^Z8 zX?vzwv()QqxVK!k>Wuh+sSC{a53_$cG(WXT{^Qmir}x~zJpVl3{N!KFYgmuEdVQbq zAC8yY@e-3S?~71s@5Pn=pwv!FUF|dUT0bu3P)?@Qa&gbD6R~PspzIL2ztkC<>^Jp6 z^ZkP%qx_@I>!Zw-H&U<6QMvxS?2`LL#HvC5a^m~qz7esizds|q zN30qc_#k^=@<9Kc)^ek}%TizSE*o~z`PUK0O4qixe>lHb?%CnezhRRer>@ev>aIO4 z+TY}8aH_aqhP;-_-MPSXAxG};=rvjr94dJFg2T+sUMRW0>lE=?=ac)qd0&@%z4o^h zWZPqOtT~ZLpmwY^@oxfe6y;;s{SN85~Yu4TM-H;l*5wp(rr`c+k`lj^D zFntVZbFDSUH1i45CcD?KjC`YkxrF+`X;+3ULC0CkT@{i#F2p2kx|CI^wm-@jmAvWl zkXF`tG2#uYez~oDi!wH)kZLY5Ou?vMC_NYAK$KHd(`VVEFja;qAB@{*1T@yV!dA;_8M9h+F#li5I z@?IETH+zQvOz=A0WSCxGN0{$h&G(*jB=DYTBl=QvC7X5pFMp|$=dS*2q zCCiE!X1;GR-+wgUyZNksjIOdw_QWJeKSn~b);aX3UAwY+S9~DBpWy3i5+V1w308eD zE>*5;F?vF28h*u-3oS2pjvV z;yPhnBSQOjv_=>qH9~C(>vgKO)Ckk1_tfy-DmB8M=FmR5Pij(KYJ>y5)yx{<^(&Wz zO}(aC*Szy~z5Z%n#m?KRRY|^7dD3me*X1sF)7H3PL5D8$hd;UXYT+%LM$DT0rd*QE zx=!y;_m_QO)sfwg7k%Ha-Rk?^*LqIh%q2f>Ik&d(xy?Brf0*0zj^_g}_+RjCGq>}` zHvZO9ZTv04HvUtxt>>cj-D>0Gnq>BJ+}Orn_g}X0kCtlVFPDChzaF+N%a^vG)BCX5 z>&QEsZMCz3w(l3E+VpvYSK9Xp3#9FHaHiHJ<&`aMe2283CMuf3(lh2;fS4}wf9ZP==n#{0(W@?~jT zOD(NrS&j?45*(MNR2t@YTz;_CF!TCn)mK=fmru!D@XRQ^+-zUAxm;OJy6wW0jFRPT zx=g2HUxjQ9rHYdgReNKw5JzdW;?M*6s!B#divCHK)X!SRdx<0P# z!B&5qFFp|OPr%jL@midD* z&*Zc|f68US8Y#eXl(e^H`5*w`=YF`T%eq}FTVUf?Yym$V;S%J#;(wHpM7k5ueTrUQ$4?XYDTxC zd)zw%yZpO+yUjVn>n2;Euk z*|0$_=?SXy$C0J-)Fz>*&$yZ?+O9dA%WHo%lT=5N)LzX}>$U0s#)V6J=6K3YJ*J#3 z-17LXx4gUS#LMy&f0sT3n4$Mp{YIhxZrLAo*De1HZ9pwi$sF$rCI5f97gA*DHtvzq z>y;9PtoQ$|Tl&AWy%YYIwzt>+()PCdzu4X;a;N5zZyYk*Fl4xX$Z&LUSZe<=+)_4B&R@<~KKXmIt$ppvZ*N;|tQc>MkzFS2rXjZE2W)nyBg$#GUg=n` z{^X=X#mo0xUAFSj%Rj#uc**~gZ@YQMzZ6KgoI7=s^ka=3S~+@K_if29N{OBC*rj(@ z+DBup`u&;Ub>dTf!fQSu)*h*)@w#_Dm404J%bWVcp$*c9g&Ics8MQdTZ5NeONW^GHmu?EjIhGP&bk1S+C_inEXLb0DW-DMejHs@Fz$wlJ+q< zqY{gpj+wqCvR@YryVLd8k*=4Wj%l)Amkk?;t6$%!`vdo-F3pi^pDe$mpJ}qWFG~8E z?hcIo5B(O}&oo9p)1gO|SK82irrdw_Gf5v)j`T6j>}mBg+9liGHt7o8>zn8DKS?+puw1>WDa>VNP*;jKj{Pz`WpMSeRJAZp$dvlrE z;}b9U!M4e5ebscC>9Rz*cbzu-_t6S9dwe3$mFRzFOWz&pj^b#=IL@;k+q&7ri@ z9cpL2I4iE<%(WXI`Lycb!%2Fd(f%@h?ri?a{f7N!hW3NabCv1`+dIH`*1PP@eM|4F z(WGH)<7FSmY`W^7-TLx_BV7j@Rf>C0`?2K%d1hbOly^5Lj2S;V+xJpLn*+mp-zoiL zMnc6U>(0lO?a?Rf?wl%)Q-wPuGwik*yQk`t7qfRvpXg{iIbu~Ovv+I|{pxmR?^sDc zTqo%r>y+Ht-`QGjbPGAE+B^0|Nbgu%A)p-yh>dQDDUQh$tpg=>>6U?({#L$LCMU7d zGJVavY1na@=G@s9@{A?M=f#*Rm|y$fzB=1fdRwK>>K}6*I(u8-Hh&XelTu?&$UKE- z8wMKr8~GYzj04L%CF5Q>tM!xc-{U|0_EgjEw&!;^p1k_z(hWo3-aGZx$xF3ws$cim z&$~VRcfA24`b=p!bgDf2U_;6vv~RS1e^K!NLjzlB_B2|A5mVufJ#3(8S-bhg{_fC z9Cn*$rF@3cZg-88k80ZO?u5G1uknVw*;A{g%Jg=pYpr~)*0HXV45wAgHY4}->f$`E z9U6Mv+2Wi|m;O|O-Rb`NW|{mmISm|5E5*s=j%!i!7E`&W47>F6xMAV)$xXLYKf>z_ zRH)<@v)eAlJ+88xa_$!+WT6tuOzt|eET{XJ6x8KDEKiWa+|{MDZnyrMj>r9!{%$oO>LfWQmke+kN!hJ zbDO7v?C};h&r?#e7@KE`$P%09fb6BEHqXy;1ee)7Yh>Row|VqGS01r>eiXOD=J`N& z+oLv*e$CrTn`fpJWtGj7E8|w%JkLpy*4R9UWknZlo+~1kY@P;A!?=Fbk#^Mc$thbJKO{o?S{ zk)83Y!xJZa<2Q%rglxlkhsPmnke=-CWeq7#&uLk7s?*a>O5NS*nI=a+&FP7kg{3<^ zPs{$!aC+9s`g%A$Z;50&J!@orJ)NG4GD9z?XP_|J+v(XR$F`5tb4XUy*Xd~{T=sK% zo|A?3cY3~*Q(=J9(^n4LK&Pj@u(QqSnJ9&*?DE*3cslQ$^1b+2|)K zdh{R1HdpivlO6J8Mb9{K^D21`$`;M9*>(YGfcL2Y!%NHIV$6-csfbR z##iwimeo$E;^`?SGM8)DxT+rmuXcz!)5mARXovh_7_y~_+$+;s(1#;QexM72Fq&W z)_OjZg~hM+%#gBlUF(@5^dzqJ)R!HSwALg4L2q&cfrk-pcnQpRQM^|(c{fAV-` z4LLt~#>jrj{mC;#n8^Fdb6wUj_$N<2DbkRiJOgAK?)u4dSk^c6r!sM}v&Kf)j54`G z?>HT(F7uApffllpCg{MEGXF#!s3{mu(t(F$H{PuS5pvuM~G!~*~>%b&Au5)ytm7xBB4qTG5%+-NGve%Yo$-o}j;)iwM3)yAMbl@e~vgJDP zgKYOBI-uWiGdWKNev|`#pAJ-!<;W#dJ_Rqk$fg5}WV`g9Ql?OjfPSHEna#2arw&|{ zX%fzecyvJjt+9*_yebExtPV64I?CyQUr3S%f<~EbvVk}0K(TCc z1symm`@5nJd?gcyo1A(>={FQZJpltHZI&e|erKK(tFNZ+> zjn^o1O$u+yG@_)w^|>%amj zhR$b{y;-)ZNq;;VY<@;&p((NxhV>BYb)BEv0;&;LE9(@^ywUt6s`?JA4`SQocLj zJ?f==UEtm7rF^mQVd|xPaquqnQoeY2r+O)00=#^~Z+uHBUsrg$_*PQBM0lHeDPI!2 z9P4nWtDYlEj(vH}p{lhfSQ&3(H-ql5%pSptknND5{JA*rw+q&qAKNrMF; z>98Oq0~UnzfCV9$upp!-EC}fZOG0|XlaM~}B&07q3F!w|<%coLEaPeKO6laL|sB;+o55;7E?gyh4MkYVs7WH>wt83At* z;&aT9;~!B+u3#>|MaVfNWTackQ9{PLW=M6zBxD?B1tH^MLC6GH5Hb-KgiL}3A$P-q zkb7W3$i1*2WHKxWxeu0vOo1mMQ{hR-{qQ7Y8axS^4o^Y~;7P~~coH%bo`lSTCn2-p zNyr>{67m2%37HE|LgvAfkooW=@uSv)X%nCvtg#{riVL`|$SP-%r7KE&U1tDu; zLC9mUAY>gZ2zeZqgsg`rAsgUH$VPY)vI(AqJONKaHp7#UC*euRQ}86@X?PN{1)hXF z15ZM>!jq6^;YrAI@Fe7UcoOmgJPFwbPeNXVCm}DvlaTH3BxDCX33(abB4n9kpB(>) zyQE^{T5b{YfmDrLueg;QCFBj)KB+yKguIDaLC9OMAmnXW5V8{%gzSO^A-iEg$UCqg zWDhI|*$WFo3SmjeK6n!HE<6c&51xd)4^Kk&!;_E?;7Q1b@Fe5_JPG*-o`if1PeML{ zCm{#nNys6167nfL2{{Z;LXND6X6Yv%xuQ|@j@sAiJ zl~~v779j(r`s+IBR&tb(Q?9de3o;2gjafm+*RUYu8(0u>1{Q>T3kyQNg9Rbq!-9~r zups0ISP=3fED8Auo`n1iPeRVYlaOEFNyxA8B;+@E5^^4%gj|3pAw}>c3@T|LWsGDHseu%-5`zd0q?DBzglizhyqQ5o4Wyj6FsPt`6toJ1n>3J;R%K9L z0&U?`V^B^5DQR^EWi^nJ)?iRZ11V`u1|AKhq_;9~Yak`9#UM-rDQRs6E)ArlQ4E|K zNJ;B3aA+VUt;@hJfwpy`8Q3(ClGbA&fZXhK*=>$=0VJ}aR$v`Ai=ur>QGJ_R@luK! z+g#(MH^ijqHqH-cW5&#WEm8aSTXNJOfgc zzg!qzs;?DDMj6F zu2%&tlcF@v4~o+1K~V-hDC$8EiZbazQBQhM)QcVz^`-|!eds|^UwTs1j{zy_&wvyS zU_gonG9X2FG9X2R7?7eY2BavP0V&F1K#Fo1kfJ;Wq-Zb$QZ$4CDY}aRDH_Uv6y-A@ zMZ*}7qTvik(Fg{lXe0wtG>QQ!8qL6>D8=UZLI8=ZExmQFR8SNl*C5vzn_Kx(iYC}x zf6I82qKTXz6iuQBMR(JKqI>8;(Y^GbXfi!0x{n?dO`!)xQ|Up`{q&@08Us=^odGE- zU_gpyFd#)U8IYn`3`o&z2Bc^X15)$=15z}X0V$ftfE3MVK#Cq@K#CSHAVmuqkfKEl zNYO(KNYP>jq-Y5PQnZu-DSDUzDO$$BqG+7WQCB*vBWG#Fc|0ikQYl()b1Pp;(Mp>u zK^o*HMXNYJC|XSqiq_DBqP6s(=rMXww2mGWJx&jb*3*Nc4fLRBBRwhF#DEk%!GIKP zW+Hb=ey5;;KYMUR4_yUezj&8>VXMQ__& z^W`~>NzqQu4~lltgQDH^py(ZXP_&006z!!4MTPXBXdgW&dY2v)y+==q-e*9H_A?+w zA21+AA2J|C2N;l|j~I}mj~S4nPZ*G*gA7Q~AqJ%AQwF5yFauI_gaIi!%77Go#()%k z&VUphV?c_IGayAL7?7fq3`o%z3`o(J3@nP?v^ky^Kq5ORIB$WX>GGJ&^_9)7d?`iW z*j%4TH;_ru8O{%izNH66-_e7j@99C&S$a_P13f7EkscKNL=TF7rUymm=tJQsC+4T|FQ`IN)% zR=$)Xx7~Gf15o7Q{Gg}|Jt!(m4~ojsgQD{Epy(!gP*i~)6jh`LMd9?ID1x38MKT~o zl^Bqs$_z-+%?wDfD}bDAVu{UkfQnwcr9wcfD|=kU{U0P-)d`p|=-zVx7|A3Z4QPY;R)(37Hp3`o(P z3`o%+2Bav90V&F6K#Fo0kfK}$q$rO8DH_ax6b)fOitb`SiiR>EMfnU!(J%(2XgC8> zG=c#s8p(hZjbcEGMl&EqV;GR4u?$GjI0hC)X?DlE0!XBG4Y|@m(PMgh8*g_jUrN#4 zcGuaapy(dX4~p)k2StgXF!S`WI&1*Fd#(>8IYny3`o&K3`o&p2Bc^S z15&h<0V#Tz0V!I>fD|ofK#Cq=K#Eo{uqc{nca(1?6m8aC$4Q_lLoZB^+TF^RQnbeI zYSsc2t>yfn=rMXww2mGWJx&jb*3*Nc4fLRBBRweEL=TFdpa(^p=}FO(3`o&a3`o(_ z3`o%y2Bhd22Bc^!15)%X15)%H15)%n15)$?15&h&0V#Ts0V#Tk0V&$ffE4XuK#E>w zK#E>rK#E>vK#E>tK#E>xK#JaAK#JaEU{SQn?&u+aMBXEx%y6v+MXlw7Jg&FwZskiU zk}m_D-~~nRaDGsmq#on~NBwA1cbDS$+-lWuC)E>QHDe!AmpyIc8E zioUbEUT+18zUTa)=qx=b`hgx4{YVdrexe6OKhuMvbM&C-7kW_iD?KRsjh+;pXF!TB zFd#)m3`o)M3`o&M2Bhc`15$LE0V%q|fD{!oAVpUhkfJ{rkfJ{skfOgBkfOgCkfLi0 zNYQl$q{wif*-naV3`mik0V#4YAVp3Fq{zj@s$7)c}|~zd<%*eNpGVo%;8qP zl%lc@*Y!4_s2t}9Mdj&1(M|NAr~*AGsz?ut!s$U#1U)E#c+O5nxv zbOc4cI6o-rO%ICt(1W7B^q{C8Jt*o=4~hoRgQ9`-py*C|P&A016lF0WMcE8UQ4RxA zl*@n=dgBg&bAq+^-T?|OkPzIzZp8+Wv#()$JXF!TZFd#)E8IYn;3`o&v2Bc^V z15z}W0Vx{CfE0~qK#C?XAVm`ySQPbeIJOBOkzeaap))~|{w$SilEbZhDMgbVu0x$c z(S4jB6iuNAMN{cP(f#zGXc|2znobXj3g|)640=#BlO7b!q9;YO8IYnm3`o%f3`o&j z2Bc^n15z}f0V#Tr0V!I*fD|ocK#CSIAVm)`AVrHAkfJ3FNYPRTr08J=q-YrfQnZ`_ zDSCtfDO$mR6g|p-6s=@HidHeOD7wetxGaD~KBX1vdqGimrD(Oot$Zm(>m05sT|m*} zoF5derw2tF=t0p&dQh~99uz%64~jO^gQ6$tLD5t6py+9OQnZBuDSCzhDcZ__6g|s; z6g|g)6g|&?6urQJ6m4Tbie6+uie6$sincQ#MLQUfqL&$vqE{G@qE{J^qSqLZqSqOa zqBj_jqBj|kqPG~3qPH24qMZyZiq<+DoduA{Df%?_F;H}Kl$c!(xALVF?RB{Bi~~i5 zoF5eJqX$Lr(u1P+=t0r@^q^=zJt+Es9u$2@4~h=ZgQAb zQuHYUQgoOBDLTS{6dh$iiaujNiauvRijFZLMaLPCq7w{A(MblR=nDp<=t~Bq=qm=K z=oAA|beaJv`kDbL`i221I>W%C=pBb+rT`LIQ$9-M+5?I%X|w-ZhgA~yq4o{zdW~- zQ9pW6)Sn&{4WI`_1L;B0o%En+5Irc$q6bCU^q?q*o)qOWAVql$NYP*hq-Y2OQgjys zQZ$qSDavO+iiR;DMZ+18q7e*8(MSfQXcPldG@1b^8pD7Tjb%WJ#xWp8;~9{m2@FWl zL|14+D#$UQWkq0VJ|^lz`J46g5<&?sdAAFQsUz)AeQwD7v5XgQ98l zplCWhC@P=_MKkC@(M)aY-&87!MbLc_Q1N5Y5E(20Dj{zx~&wvy?$bb|rU_go% zG9X2Z7?7fe7?7gH3`o%u2Bc^y15)%b15&h%0V!I}fD}E#fE2A@K#Cq^K#Eo}AVsSf zkfPNLNYNSwq-ZSzi=z9Sj?)52hrRXuITlrFoHaK0jG*GmW^Mj&I^q}Yo zdQh~P9uz%E4~m|m2SrcQgQ6|;py(NTP_&hv6g|s;6g|g)6g|&?6urQJ6m4Tbie6+u zie6$sincQ#MLQUfqL&$vqE{G@qE{J^qSqLZqSqOaqBj_jqBj|kqPG~3qPH24qMZy# z(Jlt0Xg32=^bP}yqQ{+%1_DUr&WZxgdQfy&{;}S*$LUtSl%jW?u5KBi=snI4ir%LO zMf>SN(FgRP=tFu?bbuZdeMAq6KBfmnpU{J%gY=~65Cc;5DFae;m;os|!hjSVWk8BP zV?c^NXF!UMF(5_98IYnA3`o&Q2Bhc<2Bhdq2BhdK2Bhc|15$LF0V(>L0V(>10Vz7e zfE0bpfE0blfE0btz@n(o=@==1M82w3p?#p}RCzIHoo?kzDf-#zT9gTj&T)QF^b0*G z`js9O{YDRp&eMaU3-q9u@hn6v6pHQ6xPm zszeWpD$|3ao9RK(E%czM3Oy*QN)L*v(SxGu^rWZ;15#9z0V%qb0V%4*fE3kcK#HOm zkfJ&aNKst|q$rvJDXPbS6xC-yiW)E=MGYB{qDBlzQDX+A=r#tVs0jm7)RX}!YQ}&R zHD^GIS}-6*F$^q>wwxanwW9|` z?dd^L2YOJ{kscIvq6bBt=|R!$^q}YtdQjAbo)pD0AVqNuNKrfkQk1}e6m?}liV_)+ zq9g{Ss2c-Pl+1t>`52HQKLb(}U_gpe7?7e=2BfGv15%X6fE1-OAVnDrNKp?4q$raC zDeB396!l_YQPj%ixI+MmoU5O^ZVig&Yv)mKms|N#iu$`;S^YuL0L~AJ2GWC~JLy5u zAbL=gMGuOy=|NErJt)eh2Ss`GplC2XDH_6n6y3#u6b)rSit-tdqG1e3(QpQ&XaoaN zG?D=+8pVJVjb=cK#xNj7V;PX5aSTY&cm||s0s~SskpU^1#DEmt&43i$!+;ds%YYP3 zW0A(JwOkN=F)?rdGw%YK0PUVkO3)LzNo$YuJu>uI29zf!c`N6lk z4H%H3h73qiBL<|XF#}R`8v|0*gaIjP%77F#V?c_UGayAR7?7eE2BgT#fE2Z4K#E#1 zuqcWMb9^I!L|%>(a3aI3mVRS>rr$cut$Zm(?ZaG-d{ESZ^Mj&}^q{B{Jt*o-4~lN5 z2Ss<#gQ70BD3bvx>dAl<^mi z+J-qA2_TUl>rJd3DEdjeAp3>6l`o~}&M=p6I4By#`9V<@Jt)ei2SqvbpeUCf6y?!_ zqQUf_Xb3$hx{DqZ4W%bV`3y+WFb1S(I0I5Nf&nQS$$%7%VnB*UGayA{7?7f|3`o&9 z2Bc^_15z}B0V$fufD}z)K#J~WK#J~RK#J~VK#C?aAVv2vAVpIckfNy!NYVWaEQ$t% zIYtX0ku&uR9tMJ7?7gv3`o%q2Bhd^2Bhc}2Bhd!2BhdU2Bhe92Bhc>2Bhds z2BhdM2Bhe12Bc^w15&h$0V&$efE2yMfE4XvK#KME=cqKFOOb7sy3 zEB5;-|MGc#9`5Y9l3&W?n`DwuHZhx`*O^VxW@b~gh1nEsWi~}`Fq@(`nN87K%%*4? zGm73OplCY*MLP&6+DSmsI|LN%BB1D90*ZDMQ1l)FMSBP+dY^!z4+tpwkbt7S1QdNl zK+(qp6n#QK(We9yeMUgh=L8geK|s-$gh0_NVYih4i7wOc(Oxx0Q(PIo3P;qJDmoDM zdJZ#1->}{k9b`5|-!hw`@0d-|A!bwbJ+mn~%xsE&U^YcRGMl2Gm{IgI0Y$$MP;`WV zqF)Ipaw7J&9YrAmijoK@atSCZLO_v6Kv9^0q6h&+$pjRo5KvTjepA#^{|rbp5>a2OsAR-jKEf2mSZ|8r%%-Rm zvneXgY>LV-o1(JJrl=gVDJsuwiYhRhq69OFatJ8OC7`Gx0Y#MvD5^|AQ56D;suECC zjew%+1QgXEpr|GRMYRYhs!c#q9sx!91QZnzP*jJ2qPheW)gz#&J^@7y2qum`%}% z%%a)Bvne`-*%Y;AM$xGR6rDyu(dh&fwIQJB3<8SU5>V8RfTA-AC_0OPqO%Do zYEM8>2Lg&Z5>V8MfTGR>6m=n>=o|uyx)M;-jew$a2`K7LK+$=GKv9#38yzi*HtKi! zO-<272^r3hMAVlmx+vn+8*7SsvfdP3%xsE!F`J^^%%-RhvnjfS*%b93(d`5jEhM055dlSa5Kwd{ z0Y!HaP_&qUq9p_rEhPksCP&Pr>f9r2#J$`swhdQ-HD z*%Ym2HbwU`o1*)eP0<==Q?!=Z6y48kiXLD#MGrEg=ph1%9wwk@9RWp;5K#0e0Y&Qx zD0+;5qQ?m+dV+wWCkZHeih!c02`GAofTCv!D0+^7qUQ-HdVzqV7YQhOiGZRF1QfkY zK+!9NK+%ebyH|ijuh-wbztR-#*3XMxjYQO!DtbNQc@s_1X4adcEzG89E3+wjgV_|l z$!v<=Vm3wFm`%~!%%*5NvnkrajG~&q2q-E}2o!x2afb+y=vVsY{-7zkOuyhS zksMK9s;E@5H+!lnD$RORREF6Um1QyfKv4|>ifR&2REvP3+5{Bk5m1y*Kv4k!MRf=$s!KpoJpzjA z6HwHEfTD&36g48Cs4)RWO$dRaShD-D0Eup^Byi%%!8`qp`X`B+CP&nlDr%AJy?wPQ zYRP(2)QZ^@oycs8PGUAiCo`L(QvLqJhi0*bm3P;@QdS13`Z1fL{>-N6Qf5JGNWh^0Y!reC>laQ(d7gb4JDvx7y(7Y2`Cyt zK+#A7ibfGoG@5{-F$5HiC7|dE0*b~FP;?~$MOP6}G@gK>2?P{PB%o*#0Y#Gufuf$t z?nwe9T32_4E;dCsD5)vQ5%r~trYC#7W}2dFSZ|7EFq@)lnN875W>a(>vnjfs*%aNt zY>H+vo1)pwrf3c`islkfG>?Fy8wn`7iGZS;2`IXSfTH;X6x~Wd(QO12Eg+!ib^?kP z5>T{=fTBAHD7uq?qPqwvT1-IE5(0{r5>T{^fTHCD6s;fxil!yI(*;O0q#svbZHkua zzeKz;IikK)(duMx<@KiMUe=qU`WIM0Yy&}Q1lD|Mb8pY^c(?2&l6De0s%!Y z5>WIK0Yw`KD0-QIqE`qgdX<2pjRX|EMhFz$lk9F1Akp#30%w&e`dt55(Wc~x`cg$( zlf8YjOwk*xH$`tUo1(XvP0==HQ}i~oDca6#igqxYqMgj9=pANLw2K)C^|qu(Km!Z(dJ~g_-s*BPCs?rVu~Kp-?DZvIikK)(f7$-gSn>YFzZdx z56q_MM`ly>6SFD$nb{Qm!fc9;Fq@)ZnN5+CV(;5cQHU8uNdy$R1QZn^pvWVjC`>?6 zgn*)C0*X=yC@M-oQ7QpNX#^Cd6Ht^vKv5oC7`Gn0Y$|LC@MifQAq-d zVuV1^cgb#d0TOMNBXACxqE`BKNIWH?zEn}!6z_@~O;I`4o1*f}rlygKv4q%iW(A7)QEth#sm~KA)u%!0YxVeP}GbNC@P)e-XTDuCH1e{ zFOw3y(=X6(K$@pS)R!tcF~xi4W>a($>rK(g%%eIf*%Y11Y>G}}Hbtj1o1!+% zrsxc2Q`D9jMePVEI+K8+vj`|Un}DMB1Qc~3pr|7OMV$yJ>P$dU7XpgTA)u%$0Y%*i zC_0ybqV5C~oku{?`2-YQKtR!j1Qhikpy(n3ih2?PMJ-d@j|E6{iN1)nGDZ4FV!ew~ zBI-*OU6SHOZZ$=HS#OH^F`J_P%%a(-vnd+DY>Ealo1#I?rf4v;DH_6zqRR;= z8cIOXFanB(6HqjQfTEEE6pbRFXfy#uV+bf3OF+>T1Qd-Upy)~himoD{XgmQ$69_1p zNI=mf0*WRRP&9>rqNxNFO(O(~dZ)Ox1W0sLX@S$n6wTIGw5wAh>Pr<}o8q0hz!c47 zy(zkm*%V#RY>IARHbt|TP0?&-Q#6O!6wPHeMe~?V(T&U~x`}|In+Yhog@B^@1Qgv$ zK+$ak6fGd2=yn2%77|djh=8Iy2q?OffTFtyC|XQF(GmiRmJ(33jDVu$1Qe|xplBrl zMRyZWbPpj=bWMsoRDeWV>mMGPVTyL@E841*i271RYf`+q3r*2l)|;aHnN86H%%fSKvnhI**%Yl~Hbsvxo1#aVP0@O06g@^j(c=UZJwZUxlLQn!ML^Nh1Qb0(K+&@V z6g@{k(enfpy+Aie4q4Xd?kduMtqRiGZTl2`Ji32o&9$ z;yxlkqBZsRUEgPl>J^h=OG-q2siL=1yd8I#qHU}SUyUeC&H?t{vj~PXK2q=1=fT9lwDEg3qqP+wZeMCUf#{?98LO{`{1QdNnK+)#} z6n#NJ(U$}ieMLag*8~*pBcNzM0YwK0DEfwgqJsn!eM>;mcZ5LE8!7G)0TS({A6LI= zik{M)q(dnY^`(k_Oz|o#HbpIwiHbqC6P0_E+rpPI3@7zsMh}je+F`FWn z*%TFFMv+HAQJ8?D2mwXO1QewZP*jwFqErHk(g-L@C!i>UfTBzSin0hO$|j&FNh6Hru&fTGfbK+)k8_Y?sVU9BH9{$Ps6>t91trf5WcsiF!+ zy*^7#QG)fRD2Le;O??MX99}4 z5Kwdu0YzO2DC$N)(YXW^btjYkb8AZbhC>lXP(MSS{MiEdnnt-A)1Qd-Wpy&z$ipCL8bR_{r zR}oM&o`9kW1QbmqplA{SMUx3AnnFO)R04{o5m0nB0Y%dZD7uCaDC%3(EqS*nDz4vv z^fN_86Ee&w8c|=W==!2wqgAHp2G*ORSa(%vnjfn z*%aNvjH3Aj6x~Wd(QO12Eg+!ib^?kP5>T{=fTBAHD7uq?qPqwvT1-IE5(0{r5>T{^ zfTHCD6s;hjXe9wfcN0)_4*^B12q;=jK+(N~K+(*i?)d^Fx*MNkGw4 z1Qb0@K+!V<6g^8o(Q^b8Jx@T<3j`FsNI=m`1Qcx`py*`+ie4e0=v4xWHWEzfQ}hnADcZ$sir!^5MZ1|z(R<9MXb-a~dY{=8eZY*O4+$vROF+>_1QdNtK+z`z z6n#oS(Psn{eNI5p7X%c2NkGw81QdNuK+!$|iuMywbbx@OZwM$lNI=oI1QdNoK+z!r zioPeH=rAErw5_Q7sQ`(-5E3|Vo1#V$8Ga}lQD3U)m!e+E1E%N*>rK(G%%;dmwRi5O zD8y`vl9)}A%WR5@Fqpg%REgOXRc1CtRhUgtRc2FEjoB1cXEsGO zm`zblW>Zv)8AY`TD9R(CD4&3$0s@Na5KvT?fTDT?6xAo7r~v^*4GAb}L_kqv0*aat zP}G!wq7w)xYDPd&a{`K55Kz>TfTC6e6rD&w(Mg0rQ6kkHE8v+JZJ15b8O)}rEwd?V$83tuWHv=-F`J^ZnN3l9W>eIG8ATll zDC$H&QD*{*x)4xw4gp172`K7DK+(Ab6m=({=sW_7&L^Pg0s@LIB%r7V0Yw)PP}Gxv zqKgSA>P0|NZvu+?5Kwdp0Y!ZYfuh!_?s@?dt)$<^o@$C_>mLZ|ml{!Ds%Su}_s*lH zXdvrN(I941G?>{G4PiD#mouB9q0FXe7_%uF&TNWCFq@*0%qSW~K+$LdipCI7G?sv( zD+nkWM?le)1QcCGK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@D4Iq<(bWVLO(&q}8Ul)D z5Kwe20Yx(jfuc)OU1z;08dP53TxN>4%5mOxsS)+1ie{&JIggv7IjlEDbD2%iJZ4jL zBeN;GiP;q0%xsEoVKzncnN88H%%kw2XkFzPf_W6Y-Lab{EW z1hXl6lGzkJ#cYb6W=7F71Qb0>K+$sq6g^Ks(F+6=y+}aOO9T{cAfV`F0*YQCpy*Ws ziZ&8Z^cn$0n+Pa+oq(dv1Qcx{plB-rMQ;#L^d>b zQ7?UBdOJ0uzEsgWsov_RP0=pao1%A_P0?;{(69S4pC7|dt0*XE-py&$%ioPVE=qmz>z9yh(9|1-C2`D;1K+!h@6dfd> z=vxAcz9XRM5CKKs6Hs)RfTAA=DEg6rqMrzXq8+L3Rsj<2nh-cUP0=A$^mA%NeW@ZR z%{%z4DGH_8J9$%-#B7ROW>Zvz*%W!qrYOv8iXzOWD4E$5r7)YKqRc2tC7>vcfTDB) ziZTc&$|RsDi-4kR0*ayp6cr<&s5k*dB?u@gNkCDIfTB17MWqNRDosF983KyR5>Ql* zfTHpQ6jdOgC_xAm9Z7ZL&xxY4`gzf>rf8Y|;k2Bzi271RmD9W?FPNe#tT#nfnN3kO zW>Zw1*%Z}aHbpg=O;IgoQ&gMT6y-6SqI_l)6%bHVhk&BG1QgXHpr}3pMGXijYDhp) zBLa#V6HwHIfTE@Z6rDgoQ8NOHniEjef`Foy1QfL*py)&bicTV+=wt$lP9dPEH6c(` zG0nYDfJ7tuZEU5q;GO=DI-HsoQD3U)j5KfjOQxtT>rGKRW>a(~vne`@*%Y14Y>L`5 zo1zZPrl=#cDeA;*iaIl+s0#r_=MYfTm4Kpd1QeZ1Kv8!Biq0dT=zIc-E+C-jLIR3< z5Kwdx0YyCtD7u({qFw|P^(LUG4*^A&5Kz>YfTDf`6!j;d=u$$U==3yqi2#Wv^dq7+ zrf8J@+1Sg{BI-*O4Nmi3c-a&UVZAB3oY@o&Wi~~_m`%}eW>YkR*%XarHbtYDP0?s( zQ#6JdMPmslx`KeBaRd}yNkGw61Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6kSa~ z(R2cet|6dk1_4Fa5>PagfTHUND7v12q8kW-qJe4d=K>^pnf|`(L8d5MKRlY17ExcS zXkMC^y3rKf$a+(B6SFD0nb{QG!fcA>Gn=AYnN87c%%*4ovnjfr*%U2gM$sYyitZqw z=uQHP?joRQF#$zO2q;=gK+!S+ik1^lw1R-5l>`*sO+e8-1Qe|zplCG#MfVa=bRPjl zYX~S>OF+^61Qb0$K+%JQK+&8uw?KeIr|9pyo@#)fbt!KR{ zdW_i=J3o?tdbPcoaLr-TEVC(kju}PI6HxR50YxtoQ1lW3MH>hx zdYOQtR|qJ2m4Kp+1QfkSK+z@wie4w6XfpvtTL>uHN`aTOFIBWV&AWNCDSD6frf3hdDSDsT6n(&K ziaumEMSGb|(MQat=woJ6^a-;m`ji<(pAk^>IRQmq5K#0b0YzUCQ1mqcMf(US+D|~y z0RoD?A)x3W0Y%>uQ1l%EMTZC|`ksKI!vqxlKtR!t1Qh*5K+(?x6#YU#(GfzRXjhv1 zxB!V3(@!1WHANNmujl(UEuy|uk(=(lE1zcPr<>OZO_iWs0h^-kytUFq@*9%%-Rovni_0Y>M)jO;J9xDJoz#MRk}> zQC(&f)gz#&J^@7y2qr)R!tc zGu`X|wkbM`^`_`-W>eIj*%WnPHbotoO;IOiQ`DK+6m?-XMdvV^qOQy+>PA4(xdaq- zC!pv&0*cNjpy&buiY_Fes0RT>7ZFg@lYpX&2`K7CKv8c3iuw>xbO`}PeF-S)M?g`3 z0*Wprpy)CJiUtr+G>{M|YMbs}FF>Lv>hHU5XNuYkh*%XapHbtYEP0<);Q#6*@6kWk=ipDXc=t=^Lt|FjlJOM=$2q>CJK+z-u ziY60KG=+eosRR^FBcSMN0*a;+P;?CeMKcH}x|V>VnFJJFM?lf_1QgvsK+!A$ie?i~ zG=~r<8j|k5DL|s>`t)IAUHbo1V zP0{Vlrf4CvDO$vAitb=GMRziz=q>_^786jkgn*)@1QabJplCS(MJos>T1i0B-2@cf zLqO3g0*Y1>P;@T=MfVXGDVa1uTXy^J)*u;(c|gf3A;_v6RbByPcoaLr-TEVC(kj@cAF z&uofbU^YcBGNb4v0*W>eQ1mhZMXwN0^eO>G8wn_Sjew#}1QfkaK+$Fbinb6?w3UFO zHwY+tlYpYP2q@Y{K+)R-6m2Jb{UY>En)O;H_YQ&gAP6xCxkMfI6YQ3GZaH6);@5dlSw2`FkpKv7cyicTP)s2Kr8 z%?T)KK|oPU0*YD@P;?>zMJEwZbTR=&rw~xont-BH2`D;^fTGh0C~8AM(HR63wIu|K zs%N-$1xR#)esxyE6m`+BL)v9T)R!u1pW$`-#1wU4y(#L*Y>GNDo1)Ilrl)?&Lg1cd;*FtAfV_%0*ZPNP;?OiMLh{9x|o2XUIY~NCZMPf z0Y#S(P}G-zqJ9Jv^(Ua{QUZ!DBcNyi0Yw7|C>lgS(O?3Kh7bZpXJxpf1xR#ld4Y4b zDQcwOfLxvtQD3TPM20v2GgCB@^`>YPvnd+QY>LJ(o1(GIrsxW0Q#6j*6kW+|imqZd zMdO)KG=YGki3Ai)BA{q80Yy^?D4I$@(KG^zt|p*pIsrx35KuIOfTC*&D4Iz?(RBnA zT~9#K4FnX;BA{qC0Y!5ND4I(^(L4f*ZX^VXhGn=<3Xo{NzK9JsMSJ`=Y#9;trHXFN z@ZS5v6y3&pQ?!8D6y45jiWV}PqD9Q6=niI6bSJYZx{KKqEoL@FOPEo#lz^gT1QabN zplAgFMJov?x|@Kadk836ML^MN0*dY>py)mViq;TNw3dLP`w1v|fPkV02`GAqfTD*9 zC|XBA(IW&DJxV~)dP1P+mJGMZm!fEj{=Vz^rs$L;86L}ss4rFYREAgiYg6rK%! z%%fSWvnhI>*%ZCNY>HlFHbpNno1zWOrs!p66um+~(W?X$Z6u)RH3Et@5m59x z0Y#e$DB40m(N+SA-XNgpO#+JEBA{p+0Yz^UP_&(Zq8$Vj?IfV+9RiAW5m59l0Y$qB zD0+_&D0(8pJwt#*7bOJFlcuPfS9vnl$L*%W=nY>K{SM$tY3iuMywbbx@OZwM$lNI=oI1QdNoK+z!rioPeH z=r93AKM+v#BLPJ}5m59q0Y$$MP;`WVqF)Ipax(30JBmUC6eST*MY#kNRV1LO5&=b(2`H*UKv7i!imDM%RGkngie$Rm1W5E0{h%>9GkB+8Nq@&| zjm(JpQbl>0-uK^{qI}kyq5@`9REOCV)nztC^_WdjeP&bCfY}r^WHv>Om`zb*W)w9c zpr|PUMJEtY)Qo_l<^&YAAfTuv0Y$9{C_0gVqLT6ZOY6g{M0dek;W2X*iI?97PzQbnCIz2@JW zqRy;0MO~Op(K*bfs4KH6>c(t}&Sf@5-I-0%dCaEhd}dR00W*p&B%r7V0Yw)PP}Gxv zqKgSA>P0|NZvu+?5Kwdp0Y!ZYDC$Q*QGWu8E+wGoG6ISQ5KuIbfTBSJ6b&YzXb1sC zmlIGllz^gPgg{Y;O!r~|63x@!Qq<8DjncRM!!sl5OBIdI^d|pcipH?s6pdvzMOQGJ zqH)Zo=t^c&bQQBH8qaKsCNP_#iOi;G5;KY>6HqjTfTF1c6ip+b=xPFrrV~(f4FN?n z2q?OifTEcM6kSI^(e(rr-9SLmECPyV6HqjVfTFns6wM=`=tcsHZX%%QW&( zX1Xf`NVJT;h>bEuQT_91^D`srOBLOo>An1uDO$*SQ?!WL6y3pWitc1KMRzfqqQ%Un zXbH0^TFPvSmNA>6<;*BrK|s+;0*dY?py(a~idGR&w3>jTdkHAIkAR{z1Qe|$py+-A ziXI@K=s^OC9wMOVVFHTQ5m5990Y#4zP_&+aqQ?j*dYpiwCkTO}+cMp+1xU26jNSrM zG+%d;p3ID>FIDtxrk8od6g|g!Q}jHuDSCm~6uro7ie6$iMH`q+(aX%H=oMyD^eVF{ z+Q^Ke*9a)uL_pE&1Qcy1plAyLMOz6ddV_$XHwh?ui-4kS1QfkZK+$#rigplCw3C3M zcL*rjML^NJ1QhKipy)jUiuMpt^gaPa9}ogXPiMOI1xWNN{T}TZQ?x~Yf6<4T5%r~t zKFRdDIC=*1`>sD_y(#*P*%W=wY>K{MHbq}Do1(9nP0`oPrf46tDca9$iViTN=ob{KY>Kj(O;MED6cuAOMa7v-Q3+;KRFWA*F#?L>1QeAbpr|wfMP&#m zDoa37IRc8x6HruvfT9EeML7f%F3aOi^9do1%Kmrl>x%DQduM ziW)MTqDIW7s4=rCYQk)anlhWB6PQudjDVu%1QfL(pr|DQMXd-ZI+1{)lL#m}nSi2G z2qV8RfTA-AC_0OPqO%DoYEM8>2ST7IKg$h! zqUdV<9<9I>_114=J7z`Hmnu3Z%c~kOMO|5Min=kIqH~!|QFmrjbRM%QI-l7TUBGOL zE@U=EJ(x|=Ma(GbNkGxX1Qhimpr|(iMSTb;x`cqDz62EYBcP~10Y#S*P;?mqMFR*Z z8c0CVAOea86HqjSfTGI@C>lyY(J%svh7(XUf`Fotgg{Z}EVrEiiB{H+h`N}fmHKC6 zM`cCSmnym<%Nv+tipH_t6kW+|imqZdMdO)G(FA5wG?Cd9O=31hlbKD?6lPO2l^I3T z2q?OmfTHOH6kS6=(F_8Lt|g#oCILm)5m0nJ0Yx_uP&A8xqS*u#%^{#@E&)aJ2q?Od zfTEiSD7u+|qFV?knomH{tppU^MhFy*$#Ulikm%4Hfiu<=bsQ*;-zDO${Iik2{&qNU8HXc@C9TFz{WRxq2QmCUB-Ze|qSLqO3g0*Y1>P;@T= zMfVXfSEvnhI&*%WPLHbt*7o1#t3rs#EM6m2G;XbS;FTL~z7gMgwp2`GAtfTC># z6unJA(RKogb`VgslYpXk2q@Y`K+(Gd6zwLU=sg08_7G6?J^@7^5K#0X0Y!TWDEf#H zD0(i-EuSHZR_RAX&zqua_1oBwvm)wC6@8xNwahX_U$EX3eaUQ!zG5~-Uo)Gceaxn4 zKeH)1z-)@XVKzkvnN88R%qaSffTBYL6n#%X(P09LejuReM*@m|BB1DJ0*Zbipy&tz zMZXeI%qHJbU6lFF=#h6V|ab{Cgg4q<6WHv=HW>XYr zHbteFQB<0MqA~;&l_j94905h;2`H*SKv9B#q8tK>atSD^NI+2~0*WdVP*jD0qN)TG zRU@FNIsrvB2q>yaKv69MifR*3lt(~OJ|R$)p6%W(K%&b%fs>IPywg9ViVCtL>Pr>X z&-Pv|Zi*VP-V`-tHbsq?O;KZJQ`Cgn6g6cwMJF(uqGrsds5!GKYQc=6mIM^FBB1C* z0*X!|py*@*icTS*s5JparxH+f8UaP86HwHKfTA-9C~8YUQ9A;P&Lp7dECPzoCZMQ2 z0Yx1MDC$T+Q6~b5Iuim#b+g_50wj8#zPYbwieA(&_`76B)R!tcH`~jOnWFBjH$~?$ zo1*iXP0i`^(LUG4*^A&5Kz>YfTDf`6!j;d z=u!fTE+e3500Bh<2`CywK+#|ViiQwSbU6VCOK+zlm zislkfG>?Fy8wn`7iGZS;2`IXSfTH;X6x~Wd(QO12Eg+!ib^?kP5&}izvfXh4B$}b0 zI$mjtTpbo=N7R=pTAc0OUd9wHVZA9@%4~|3F`J_0%%*4svng81Y>Mt?HbwU^o1#_B zrf4-YitZ(#=sp69)(}v%mVl!B2`GAifT9NpD0+y1qK646T1P<9BLoyZN(QRo0=Ppw;OBFqz9Z_GZ zXhXL5VL4OuGV4vzE6k?oRc2GPk=Ycz#%zid6<*%WPMM$sDt6un76 z(OU!*Z6l!QZ32q66Hv5+fTEoQ6um=0(Jlgt-X)-DHvvWO5m2;;fTH&aDEfeaq7Mlu z+DkyuM+6joOhC~m1QdNr2o$}T?IxEOMIY(6u`ijT>-0}GewH0kU#jS?6gn*)C0*X=yC@M-oQ7QpN zX#^Cd69PqFWV>exkm$Im!1>Y?<>}WU8PSOPQbp0IH#pZ66=S_AD$Z<*N-&$ElFX(k z#%zk>%%-RmvneXgY>LV-o1(JJC@M!lQF#K2DiBbVAfPCRfTCOiiYgLNREdD1$^;Zu zA)u%#0Y%jaD5_3CQ4Io$Y7$UXi-4lq1Qg{FP?S$VQ2_x(bqFY`O9&KYMcsJG}`Hbu>tO;K}ZQ`Cal6t!eF zMXi`k(TU6`I*EXylL;s~g@B^g1QeZ0K+$Og6rD~$Q5yn^&LE(uEdfRC2q-#}fTFVq zC_0;fqV@z7bs(UqBLPL72q@}IKv5S0iq0XRs4F2*)FA5a6d=*b`qf!OQ?$x|!xoLG zFI9AY)cdK5DY}65rszUuQ`Cdm6kWt@ih44eqKlbLQ7>jw)SKB9^m|v;RFl*b(HH`X#u89;1p!6l2!W#RQ8!Ul6gAf0n0B5i+Ms``@ycjKeW{{}QSZd+rf3rD zP0?g#Q#6Iy6isC|Mbnr~(bdeRXgaegx`x>l&0sb~*D|AMCILm)5m0nJ0Yx_uP&A8x zqS*u#%^{#@E&)aJ2q?OdfTEiSD7u+|qFV?knomH{tppU^MnKU50*Y=YplBfhMT-b1 zx`TkCI|+fJ@lp2@0TNvzqc_16P13&->#k@-eK{qaB(Gx1+FBte)?D_womda~>u8I_ zCZ;=1a%{1DKA9GKLH=sdtk@^=`$>w&YRYfDjmIvRb0`~IC%@Y*5&K2{@OGux$@1Ia zs>QC!ahzJQ*X8S$f>?4`5X(Q^ zafZZ3oZ&dbV~@3SoYAq+*^V$$5{{?)yr}2h&|EAahAl~evY#u*5*>jSrxlsfa9!*y*0>j9*mW_ z+;JX>^&I9nkH?meaGa-OUyX8{=VSH8I?jgJm~oD?G4|9|j~?$V{Iop&i2^s zsgAQN_V(3|vnN(=hU4sw^_uB8pT<^R?>Jw^_RVsf{jmmf9p~HF6*oH0;n*`bJI>GX z$gQ&dL-8{g$Q=-h&s`|@Kq$WB4!H|L@d}IOJ_yD8ER{PU6u)P=+zX-jft7MMgyM}> z$^8(D>%V4SDHPX#j=WkZuK%8Ntx#P5LEwT=T>nMa`k}b~lbnr1as4+Hn}y=~kK(lo z#r0n`J0%p?f0pX>P+b3Ap?0CT{=+csLvj6=JvxWt`cE@-3&r*C);~WK*S{S7qEKA_ zcI)1uxc>FT{X%j5`(+1&;`$ea4hhBeZ+ILYitAs|H#!v8zhiA&D6W4=)`U=8|CXaE zp}77vHPb_J{d-1chT{4cMa&At^-ucG3&r)1YTpuy>z}n<5Q^&`mb@br*FWvHBox;_ zuCyW)*FSHvDiqg0Ft8>R*WdB|U?{G?W%rR#Tz}8yas6FS&xhjr+g3J& z;`;jzHiqK*#qs7)T)+8yGZfdaZnlTw`q}%gP+UJe-4lxIr(b(RasBw>(@l=vup}6h=ejAGGOZeeXT%Ut~4mm}W_1(vk;2~G4YnJ1L>t`n-j+1(W+_CS-L#(uT zao+QsQm4oRCEOtU6=`K&E-LqWy;S|n#Pz?<@`wp7xbEbTQ?|N16hrlz=)V>&r}6(Q zyH*}(p?cl54VEJCow6G|ZNs#k7jm2?@~iA>|6J#3J4^OGn#r%SpQY*P9@F-k%r9uW zK(1z}-rL&JUAg-5tL!zUwf&^mx~|Sh7m-^OYUvLvOhZl`?a)-*ITV+w=DqH;$tFQj% z`5&*4)#2>xzPjq~!OVL~m(&g{v0$o5o8! z+= z3N~u;;jd2d*EU~veh(*6M1<(2-5e|lXMeck&INjpdTC3Y;j;PVeyG;^NEiQF-!f;> zcDbclvPN&|M%Em9^yUYH?Xz~<_h4Ut(VB;T-F%gksB4RUWzqF7e!fue zaWCz}q=GiOCi~ZAzx4L6+oDIG?e8So%M#r>CF|Ih==*WXrB32}%XvYTJK)`g?_A*| z`dM$y$%h^s)J!&t1%D`}xfi_R0fMHqnuqQ#<;b^?@>T#gwRf`mqfg>oe;X0AH-(wYxkT*XOjw?!LR^w|f`z7#O;b^hox{7dX`-I3z{B~ID7ah`1I zBJxzM8{rqO*0ks366KcdJ@WcnddqB4em%SQZ%8@6 zoPWz6+i^`}|8g#zU0fc)a@Fdc+~qtcG1OM{WW|B}@00x%yHCBWn!ln;ha2npD^?$g zc9-WfS>bO1R`i-S>SX_lz4Xr1+w_WgX|E>A=so166}ju?#!l|T@{;6ly@b4$=#ARQ z+Md5|*9U=@=3KEy?t+d?Ui%*()}FuFt!2{pO^7 zTF*(;ko{J@oW5L6kGp!8@Gs|uol}Z7mCns^bEYX`ZHdvz1&v!`D z8@Gl_UU==gNqXzT+4tSL=tsS};p{2T@4jCzI-LE`mNy<5?<7{)Wq-)37rwdgv*5|3 z@#{nS`L{8)Wn*Rkvb)b1*xE@n&Im61`(TOx40wh#z3>_hY*UrLwsu*))!Eb5+^WwM zVr1>>Yl2(7e(EMyo+@O?CRx%lSmMrh!tz96=QEV^*>py00V?P7+4q~z@~_QBWzHSw z--6XIemhZaK|fidTW=Xl=IDXIu$Ym{*;(eRi~XyX z@=Z0l(Q+~K-~0R{c|1HQOWu(sIl&Uq<>YRZeUeY5CAP~CdVUvheixp0Q%(Q;qCamA zUe#Z`ciSX=W%SYxHN7hCBo5hi>pF=e()9jKZDcn-^wveE`B%1C zkYvYy)D!2TwVxLIQyk7a~I3y$YoF5IcbGJ7n!>b-L*g9@xbGc+#+}N9$EFBoY7%c zZCQ8ZNx3AsuOFVC@AwesV}ApMvk!c_c3SYb-?g}- zoKh}l!>Z3Gh%LE|uYI_Gq1-vI*rJPqMe_PxZE0!$%02MSFAwOIlU<3ITb=D+&Rxx4 z9p)tTcO~oP%wYy+;gL(ZZT_7{^eIW+{_2t!SaSMz#RZGp zm?vwLiup^feJoVnzmOW2F1*-D?2;9FhyBQn`C{6~@92|4IQxfd-nm5|AK~n4-kSfe z-Wo4$!nI9WI*Deor>u+en%EXt_u%Kx>8AG57Jc*ax&E4I4{V*L_p+CE&Q^H~k?1aK z^d37gSflsY{gU+Bj^u1s?l`E=fpXc~mp!vfgvn*Ees$Wx;Cx=axN{39Q7Il=_T9lE zFKzX=XV&)DJo>=?^}$o$E%&|sT<~DJ_p9D@Wfx4==w&AgWM^Bi_t{e$FEWY_+wLtpETsl0X2jWCuqD?fREg5CjM z_J&_yl$}9Yv;5vyYx!$#y?^r@c}}ZuYwlys)H%;D4KAnXJ*N%vuiO2v>{9)5L3jOd z?{*Q`&lY`Pw$bafqMd&^c_Sti^_LuYWd$wFIF@&vn|7r*!QO|oI- z_UzkteV)JO-U){q`fDD(<)(>aoWxdJ(%$sw|uv%o8Sstl6Kl#&qn-9d16M_(*BB1Zht^`a=o;EXPw!>NyO!io!*aY zxMEK|^!Dw6oJEgqUn4(>oS!z$-6R`D7VT)4-qA@sD{tRa!Ao4sufNI*eqyubcY>Uh z@~d1UYx@edFRi)F{EgwC?ni5}Lamm(1J;YFS*SI&*0NAL-CCzY?LupP3$+2(t|-*T zTDzf8n{I7!p>~tCb%ojzYp)h+_gj0fP67Sd%aK_ZSBKCZJM?33$=OH zQd=C`26tJjP^hi3RpRZ*6j+cEsAvg<4upu$}KI)Jj`> zs!*$D?TtdMg|$x#wRYBiD%84L%WQdU8}zeQu}~Xntx=&i#ai1!ZH~1bh1wm~h81cL zTf4eYd*0e@h1ynY_Z4cpt-TmDFRh?Xfjs;_xBM>oqLgsD?0;GQF392Rk0#x5|7dx- z&JDJ1S}XsSdugGhBChPhSguG;6mdK!F;=oZvvmz}IQy2xZ@;TgpyBL!Q$Jax`$Jy# z4>Mml)qk3LxM`)zvL`8P^to*&XBF@Lh8!V$3GPuudlwHD+Np52vSmV9eItArq?(5ME}-> zvzJd;IzQO8nLW0Q?6S&buU+=_>fnXtxpfow$mdT3WRbt~H(GwsYkn%LS1g;dK6qB1 zvE#-G!Bu}{`qs7no?P~(_h+6dJ4Uu>bg;-v+j!|Y7x+*9ZSK!*pc^P{@X$dQ`5Wkp z7nhza9{^PjE@l-MbMv&Hm+8fLXoQZ{wn z*VtdO_q|&BW+R+E>*H&8>g|&E=JB$!6Wq(>0=^o~J!6Gm1v^l@XKEJG4e)xx-!A`+>mvxnw ze7QS!ESR|dN+*%18mzgFHT}2m4*6HN@|{aB^>5+4forSym$I+Sf-{`NskY)7R)jLz z>29o$n|0H);8I468{fjelmnlyen4*FMYiS;H)qaQd*09uDf`a1uhJVPH)qw{ZM&74 zmv+mApQJd6aki+2+$8@a%7-UST^{VOTr=k#*?*O-UwKk~@V;%!C->YgH|Hi>b3w4i z%YO2i9r96<++k%pX9aKlqwzbN_}6X4*3C1naw@K|CH_ThfA;Yux|zMS*IRFt_dIeD zqboMm{dg~}$HuW&$rlS7EYY~4w+@yi`;UYlap$``%_YZVGN-PVa~CWYkAtmALaoEeisPEvgK zN%F2CSB`M>2*;_&X+&F|qt|s%hJWqkwu+OP34;~jZTIJx7+ycFX4vX}s zneuK_j?jYz@-8ztLVwyUZwKWFJ>bfA@ULu|ewE^M(1YUg&#+ z&|?a3fsTvV0(#8xH}bc0LdKBONe}M!4RzB4ZgD6778m#L$ZmSTmG9(V`Mo}_PI{o% zQg3gkqt`d&bknPgx=xGaB7XOuUXWZ#{{n4OIE6Naze)5Q^fZ6;pRF&Vhqk^*q4h;{ zQ`&l=di;NK#(K`ldaG=8a-r37*Z=-MyTr6YmzY*)Oote(BGLCbwo-|8ee z^%u>G$T!CFOS>MvDZfHacRkQACR}IixJCNI{-Cds8?EN$BzlmLPsbIJeiGl#e%>n2 zM7!meo}(VtklQH_&M)QQ8~LUAuzU)vFM9fOTs~yfU;6WAd1&b`y<$9m^z5IOXN5iT zOHbn;$|FcmlO%`D{GS^y(!&e=pPMbxLw%GbIjt5Qk;5YTq9|+U+2c#Dz22w61FB%r zF4^1FUwV>TE6Luf{L-`ED~BJ;FV{&vWs&Z^sbU$XA4RMy^e)r?Jh?}bAV2FbUE&|g2PCp&q@1~a_EW?k8|bJ%#*ZC4Kz`IsWhXAY)s8*!6cl=@DJb;h za%|hAVf)y|ampG1J=D+PWy4Nbbhqr*={$!-n?CAKGJB zuRcA73>`eYPp{#9dgu2VI%df5!5Vt?={;g-pJ9cL)6>hTo8%7}+J9jG;r&PUaq{~O z9@r@s*zgg(`wz|^K6vneUj2IZ zA2ck#Z?9fGdJY|!U#Fl)y&iQ7>elH|r$A$EiM0m}9@M9HpPm=@uU)4guU>6EI!})N z%~ARN2lW~-qIaMCfjxWm>p$rK@vAXx%&@{+qHn+a6NmO5(SOk3lLrs&Q~T()7(INb zze$2E(thaROJ$o6%kMO#=g`Ye9Wkg!XSpqX+YcBqtVhQa8=l#KyGd^B|KPd*R}hTs zIlPbF7xJVWFzQn$ua_e0(YwzjJx2@}-edTfA$^AB^;5e7p?Cj5!)0(CNBH&VHF)5_ z!Gn7A9MWH!umIUEdY$ZdY5HVuJp1cK1<8@OtQC#guNgqNxZnO=?_ zNcTrwQP(T2CzFG+`oG2Ge`TrP>UhP<9i4I-dd1w)x*|BXnEzw*{Jvf>|6-ck#kKgm ziz^`~FD9qX@p5vxxZo`Q@ind?XA!OJ6)WRk8@ZVc+%XCJxs*FbuNhZ|!@hR)>@q5O z(cp##+o*ZCxEDQL&q20cw6^?^qgzrpU-P54ue{93iG-IDcGL6vdNCPOWP_KK!^*i{ z$?`JUw$2Q;b!FSu{+K66*Y)bliDS*=$9%6;$g3VM;ida0l1&|~scvihG0#6XN!B%# zoTL}1hk6Uk=nqxBN`BW+N`JBwgoRE@!oOx*!xXt8!8LB~CFG3K5?<*#URq5rJ?xgx zll!~4o0^wjzFxjND6dW(cdT5re@BbYK-@^WIkv;X|W!FjikyIIa#?w(M%;-B5ka@Kn4e|6TS<$BbT>!Dkqc&$3} zN>i`E9hk7GD&1W29CO^+$lUjjF7UY1{eEHY(OcoA z%N1Lv3*-S=I_bPD|3~i7bM4%l+r8G@t0LPhE8%7Pccnf)v*oV*v%?Dh@y+e{7G7t@8=3O+<>~IXXW!i8Y^%u$i_5cgxSdx~(B;-` zBtPfN&+;5DhpMiGJP3b#NYC*qhr9;zbf6F8P`IU6A-F;f>?^d zRn;G=22TQVVLV*~$B(w-tNreHe_7(saveR>usbr((`Pbya`DejZbyNeE;m$~iq>Z$ z*>wJ+L5}lB-3)aL-Bh{Hk8OkFZfnJVcU$xR=C<1Le{x&dgvU0KzX|fZ|GwL*cXQjL zx1GCHHdKX7xraku1-TCX#)*3k^?A0c&T@U^s6YL&Ah;LgtlhNG(en-{<$49O^xxbY zdJS9r%T)nmZWo8`ygI+XY~7T)i{VSiGYK)TVs(GRa7M=;{`PV4uWpn)h}2h(m+ijj zbn7dR$YNgk3jT9J@Zik%pSS%7r#$EPwGGH)lN)2t=jQnjZbjvAsI6Bqpe#Q(|8M%) z%Ppu~kY7;SE2!vIbmhT%?4iQb!`~eywJ)w4y~JNU81+RzSDqYe`)8jBXM4Fh{*NM5 zcgbYOrfPv#%1t{X><(|{Rh3kVm$<)vGO8jMofMWopHUW)43 z4C5cIXRRlz92{?_mdC(vj;$0NTlVO)6UR2!weAReQj^^lPN7|1H~i~Uo*0Z=q+CcN zfBDekpVY!`me9!!7t8S~%2QYQ{D5n~lI@>kba)y+)_Iz*C6^SJ+Z%4zS6-cp<<_nv zcWLkl*B7f&qBJ(-CiKdMyqZ(I95=U_S1#;cnCI1$Qchm9bhoD*dq)-ZvNOFVb`|_F zPmZqZog^pAbBiXtlk`QSrk;yF^omu;uV6pw+2nh*LtajCFE1Rb;}*@U<_^fK;N?h` zz+rBA`>9mf+?-r@bTf|luOI65%X3F2{`{P(%JK4=8eFAfwU0ZYyp|nzWp$RPoIL-O z`JVr?o~W(-7~GpV&XAXCJ$L^nS)hlqP4%EnFv%uvtfTwT_&k4CM_$s)1t-`4%?rD)IeB`2peEJkxy?V(@lSYuEEcRhfm7PE-avUd_Ky#F{qxSVG>~%9CC` z+p<_ePJUf^gIPBx=RbRGI<_5u`&??b|F3r+3ku|^Sniy^IB_#M`ZxQUdd+#F=ECK* zS{{O`M>$z-3eXClfMQyKsMX##7@*dUA2Kj5Wat6PB@oM3J;Bnl= z{=sWkJ>3{}^%+nv(x2++(;!n`@Cxc5AS$+x;CZV_C9g_wMFoWqqCFm(_#4kQPwS;>A#*8egFoime;x5 z;Ogbr75Yb)QBzJWw@jWq*ya}?RUrfnX^5%%(6lZ z-n#p*7)M{{<)vKSy8pwC*yOm4Xpa`#^v7G5+oq4t8g;#z{+@w9)eJV89$`P$5H9s< z9h>B;$yRNwh;;YipWIOe6>|MMSocJZ-2s6-=6`ZN|B{K%I1$Lxn^j3Z3<@r^x$P(i z@8ad1l|jhu5~xKRS;* zd5vmT(aZODnQb9&ApZ7t1RGdxwO;JMx?AJ}Ku`WZxYl|4)Nt&!bMe1F> z+}hka@?g{bP4+v3w}QNx=P*a!rIhq?%gRapF9}M;kNeQv|Bzfi?y}Fz|Ln)3pO^bz zsr>G<_kVpha(?Nu!>o7AKm5i+cdxlw`A5Ip`H!zj9likguic=dXY+4wP;kHTp$muq z`s07zhX4NXw;=wrkN-=#ue!taW7lKv>T?PTzpdwO-?790`?g-5dP?!~P$78v{ew5? zydw+_|0mzpyRToF)G+k_;SbMa{u|}~&Hj@Q&uip*CzaQa(DU>o^n_QF_nxw+tgnJO z@~+#x{I_pJkA0Y4Q(j4R|D|+}J4*K)n%lk&hqiC?*B@`|E^5Af(&g_Qvp2+{zb~Sv zXl@^EH~0LHwsl|BKH9FYpW6o4Bd%X>=KO<;`;&dJoJB`(K(Gt_`%A0K8-S8Eyd2p* z{>?6(-U_yff3xiDavuBB^OXmHevF>?haaQMj*EZ1yl>P)`FOkAAAF3S(9gR4kJ0lB zYE%q98$bTj@*Ljo=E#dJ?+l|O^YhLoddU0KnhKBw(FVM>hyRVFu-)a|fm!u~W z&E$S@zZkREe_HaY%Ik-IjlqYaIsfR}QrY57;;3N)WOD}}!OM3H0{fr-oZMW$l=!m+UV{R!>OcKJ zT<++9da3z;b)ki?%>TUt|91=gcWr^-Ypp>0zxvs$BA;m0&;9LJc06hP;5u-*&EZ&UOCy<+?J@exBK7?X~Z{_FijGGVYB2 zpDYzDY{_XIEtRz^kKuR^hP3nSOY_-cz0IeLBXvcMl#pbhBHmx(7Kt*x~uX z|NlV8eW2(6(gPj4p|)p%?pB%V7g7J|Q@;Pv1H_L12RHGz2Se8Nv)lTPG4}w?Jqt7D z?D|;;o9?y$;|FQ(qsji`QwIf$`gL^=Ium;4^xs-XH+xJnpfeBT{KG0p|L;`s|Js4E zrzBQv+m5e+x+kcqbwDxd^nam__AZHaAK@z2eK6Y|+IH^N#n*T0!@$G#vre;hO6%%> zl{Ue5z7<_QcnIO& zvPnOJXdBp@51Lq2XCG*%mkmt>9}QF8)*V-WEdCGSc9`u!e{0CQ#QOWE&Mw$HJJ#Qy zE6yF9R@E-n-+iLb5x@fJ2bHws-0JS0`cvTl-ihU&Az7o<{r}Bfb~RFeU)|Z^_VV!m z!J~Hf$4UqFbdTEYAk1zQC6BRmSg{7z20>00vb^rU0nLP#Dd4kQVzbtZvY|Wn(byd-WzefuGCT3O0 zW_6!{Kd@7*!#?(TcvX@9*yTVi5ZKJLA@*0cg;fV@%gbv@%gY9ZDhmeHWas1+CFjVit{P^`=amnsC@rYAIfs=MYrev~ zqMGq_Gv-w0*OZl4+ssu3mDL6L$#(`<*h+_$RSm1CD0gqvR1}XaD6J_huN;z7?YC&F zsy};fX?b2rO@2;wPEFacA-M&WZa>N^{oK6=q;9yZyrybcZdG1ov74>1d{|k2FkAlt zMS&h%ub7nuRTbq{LcgXyHV<{-%3e^JQTO8Xpqkuag@v~Ms^ZZF$wmIQXT?KY zZ3gqWn#|2gEogCB%`i56unL!5SZ|iR%25^7<+jVEr8O1h#bwn6+T~uFKgZPmY_)f< zn)$&V1&6Jsw79G!S!*MT3yW)V zDuPnxm6w$ja|J zXj<}%a|YFv538;iR$Vi^ zytLZRpX4ey8(gE}njhD6rJSAl1;dN&kF;}#Rry-Bb0f7q@~4u6*(%wc+^#-S7Oxy> zr*uvE@Pf+1(()0zZ?v*(P_o%Hu5yMXXDF_)#!QE}!kUxR_B7a~DkCA;NcKurSZ+$? zxC2zTY0rDg+jbzVN@@y5<`op=Tak-r=8u~{uBO^rxk+>9Pn$e#g8lt@vOuaPYj>-2 ztlcOn7*$i4Q|!)tj;!Wzf6{IRE+1BD6L#hmmKNvLT?+zsT@#nA(Cl8x)7}~Ye_GmE zIdQ>^87C#z9h@Wu<;C?+Cbn#i^N{jNcaU7`=~vM!IBllSnmHxYnzA74!|Jnbf@Q5{ ztIF#xUhZO$d{3=$WkG2{&|_R2E#k16+FBEN&vF-UT4F^{8vrvI~;O(M=`` zEi8-#YX^qul4!-Oo541kTbW~*eF5dRXvZq`G_#7MNiHp~(uqDGxj{Q9zCLrACn|#xG@)Lkg@p z(~S*Va_h^smeem-5Ky&XX6o*{IqV9NEO>sed|fsx3(E41-IO*ud4ThR8zeDfwK#Li zq?$=HCr%qTv&NlS$(0qCmKF@kDb)#RcLMp=0@Pg!1NxI!t(2pjJ)j={LZ!&olyW1M z&u-bl-HnN2*F^5t45i*^Si=yU&_VSCOaI$Ou5{AODf6f5Y^t66xAB z{)JE0fL?tvyUv|7ebTsjlMcx2F=N8)1&2?VHFy4`6MM|)-P?lsQy0t_Z#sGUta0;u z*#G}I+#0HhF0eT#&py6yk9o6uOw8_Q$+)=_rXFtp5a{>;J!bTrVgFL7`^0&(yHB2- z*<(s(kMdrbJ?uZt96rGc&|~t9N%Q87n=+}#^nmKavn=urK@UfvId{F7Z#?&yXa9@G zbe?4s?b4t0!H)H>2YEn{zaF}dM}R{?S@|$)CsQs$eGm3^QoqBHyu{i)XHIT$Y4PZ~ zoBk|2Ib5aNNs@9@>l!C_h9@zuI~(lsXw6o&-7mY_jN}X))SzQmcdV@$$g`W4+#Kue zsoi(mw2q1|ZvVQo$8JV^R=-!}`aJGlrr0_){;nrrF+X5&TIsA=v$I2i^!i&_>fKS) zyL}&GYsxJj`L`wVO6?M5w*amQ4eG{U29no$`>!1-m7bl|TYHhbT3GcbS6WwR?k2QG z73Y_*%X%ER~$rH$+`R#ZF$N)ZE$~X-8kJ}+G+3CX1knHXDJJ~TV!hz17Lz#>-x9J zj(I<=#dk^Bs=tC145>)zXXd$)kJRg(D|c!)xoCt9uH=+JWa-U-Et;cl~%M}shR z4B$WMZ59?6me=nJ*RhqKlNbCit9nWuu415ojA$j_`M!hmNVSW3)j<6 zzLQd^Im2um!R{ne#|_-wA64hM8f1Mie=C-JBY@f6e3zHGh9kJY$o@~?wUf-MINLg< z0;sMpTEC0wZrzfn0R^e5D6Y{^fm;n-+nnUu?E1ip-JP4ZVK?QP%C;U%vV18uP*GW4 zRBWAHI}~MhGjD?@Y%)N^6~tjuY4#&Y|Q=likdm++Z{?`9?}bRu)wM+YUg`PBKd1O5(ecL7D6($@YOVS!dXK zoW*&?!KJ7o$F4-dTy{P26Lx;qo81qP<`r4jy`VIh#d_|^)g{lD!VxvYY=q7#Q!CW^ zYTWml z3;u%}PItsd75IKR9n$)Zfuq^(X9{e1#Ri1^on25cH<}(y_-6z|az@tVl~wENk~%~l z6z%WVO5e9*$CE>e!7A&<+OuusFZJB28<=uC>(7dMtxH2u ztZUMfx1(8Ey=&%X`(3QNy7@tFH@E9p21~gSUv?w792*@*cAlMx|Naq-AJMM6R{gCZ z%BK5}?M8=vhbOs-)LkhoF10(i)G>~_dzY%JJUx=CS3gh=wKlM;TZ&o!em{_2{!&`6 zWb9+IJx^9-N(<+@mdwZ|{27tF!UmO=I-nZ>^6xItzPV10?y=tBK@-gbp*!4_!+cZc z8fJ1e<94j;j~SY$OW2*OQJ-)3EGaiL zyqSE=#YNTkQ9OoL{Giw6`EtX@6e{)L*LyCc-5gd{QdT~~*8<%j_h7-T*LNydQ?3o8 z+e5*Mfd%I!qG@tdG{*}59J9#9atA=zNU4!#izI~*1rt3kTQaoP|{^VhQI0qcS_C$O4Vb$Q?sW2z?#)Ku9)s-ZrpJ5k5E3d|} zQhLe$+TmvQ-2)0x;qSR^3@}+s0X5cwB!j#m`Sm)UMmQ-UTZMk)$%=E^phE>_4IQ54AHW=#0L3ew~Qg=nO%Sy`iEjz2OpJK`3T-V_HAMwE70EiKCj7W+%4ZmSha#w& z)Z5gc=QqNhOS>oY<$Baif&B9V_gr%KOM$z@xhMHFT|5b9$=uSMvJyL)3vAqMw_7H+ zBfHODcUVfx?a8AxEjHqsQouxLH#}*O(QjwC6>YC3dL%X<2NCy>6UtM2_{oX;ybz(hd5! zOQ^3OKR#+j$aZ6m$yt+Q)~=s7sM7VScdOodJxfPZ(5AQ^5G$c*c{zDj(}gv`EkMX^ zp3h;>DYF0Y%Nd#41M;|}+>yAxmT$V;_@S#V-(0Z8;LNZ3kDkG*<|tP3Zprstf}`n% z8Ch9yy(!D7`&flLcDq+XMNRUFr>jq{Bz5cXM`uKNWr?nW$-9MYyV-QjP|96uA9t6^ zvexeKB&B}es?bIq>6W-phlB>@0Fk}3ri4*OaVm1HUKN#}ofA$~n zA3p%FZ>_LzBlydH!lATNn>KC|%1`+w1NTJ+xlOyA-Qb+Wx$*PT&yQUYy)bf7+NI&# zrUN3sG-%kgOKzjcu88T-Mv*gPfgc*YhU`mGZAIhU_XmW+2iat7K#w6ktqW2XN^cP# z(jd|>kr8bbZXIqDX&Y`A-ZQ*cxP5q^v`*oksb6`avZO}Q&`*D*6w&^Ned@dJ%NG3C zGcZrY{g?ZcpNRd3d-r`IbwAONeP2juU~)G9{@(VlFf8Tx6 zhX3))&)&DryXBkP7ohkb|Nbib)(t#UP9yfk+NnSGRUWC<-nTD8OZka}k`*7Mk=>4V zB$TXpy>DL*o$?b2+1G@m{6s>@0}-T=Q0rh0N1Z!AGK{DGDf7F!DA>(c?dB)%=I8I` zPu|U+zni~)H@|c@|Ilv!+1)(f<`6u;>@q*pWun@o|Kc%ovfbMKUZl5smc09O__}7! z-K_X0Cv{ntdn}h+p}On3<4Dbe1~N6UkCY@Aa}S;D=UDq~*gX`Q>GZ%*$km_oS2^ur zUw&f;%lWR-rq)C>>}lW2=G5{{cCM#cBlV}L^JP&}TW+jVn{T4iEc<2{r}n->(&dev zn(rwsb!y9vlune+mYym-UwV~vsq}PfQ{3{OI<@uJI<@s5X2?5T=+xf7(2#e2qcmh~ zkDLE6=}hU#PHn!28~NqhTVwC$>*dt)7p40(@jlmoInP+qP#XN5ei=Zl{)SmsZ;;=(an?sU5!)<-eBha@y05 zk5fAi4egY4%a1g5+i7U0tn*!++Ir5G-{iEfdHZ@JxBNP3hP9o}zi40PslET5soPGbwW;p?iB9eP1MR#0oIhLop7c+rwp^CAxlSiaZ;-w&{lMB> z_kJsDYu$RDvF~1X>wQ)Ff%I$XPN{2q-F*F|`O?wSsnX-6XG^b;E|oqgeMn-vX zU3@;#sm<@cqtEIPPP(UEGo8QK)bZD8KktulYTLU_ewS0@y#4-ObERXXCrYo7 z-Y-oL*?MgstQiQU**fg>3e--IKn-K}?Vll=C6s1mu*+SLTT>ZmKk4DpTxo@Lm~?{l zSm_+;8Pc<*i>0?pACW#TeOCIs^cCp_>ATX8q@PK@k^U(CMf$rm9QOMYmo|~Ml(v(0 zknSt(F3pzqm)cir2lZp$4I5~&v|Kt&dX#jWbc%F_be{Ai=^4^ytbd&Tm=~n4a(psr?B7*%*PxIPD+Df{Yw3GAzX_mCV^ayEz zv{YIp9W5OvohqFrJzjd6^la%x(krCbOP5OTmOdz5DSb-1M*6aJgY-S=$I>sQ-%EE$ zf0w33eEl?#HkY=M?jzk-dZ4to^bl!|v`AVm9WFguI#GI@bguLy=|bsw(o3aROP5G* zm)yGjp|_LCki z&6k!)E2X2P?mo|LZ;EuLbb<6#=~>bXrI$;ulinh|OZtFxh4e}3YUxYT_0o5xo26e! zzmxtf4Zelb${UXPawnwCqLTqS?I%4_S|lAR9W9+8oi1G21>cq${LPOV>%?kiIAVM7mY_v-A&XEZy%6g+UrM1#<-0xpQX)9@O=^(q`cbry9r#13^ zf%Kv#-d`(y!0x-<{EtiDunWBNA4-3+`(x+-CGBVT!OrJNPj%n%Y5oG~YP)ZB{tanj zZ|_@6%Q|>}l=P~O-rp+yptJX1Ni%I-ZhbwZlkEn>`FYa&yLtb(bi3U{x%dB)4zL>$ z=L@8#XM2BwImG+hrJD}({u^nhBfURJIyJ}p1=0ue zynj-E1ok~S{)zMZsksP{F}>#DrJQ@Yu1xZM7I zEA2AU`)uj4qrE>tx_pfHPfK?m<9(#Y>tW-(7E8~Z;QeLN7bkiDwzTO~@Ar~cAM5=% z=?&ApzgxOxruW}V_nYH=Z|U@T-rKi&2K)8!0k#R=S9^b@^wn#uaW+7kM|Ak^_qLX*K+Ck4|;#K^!4T5e<*GBi1!_(qgQ%AMY{B#-ajDy(r)x! z{roIF@G0*Pmd<^~`!l4Et@8eP>7T2;Z?wj1{_|dkN-uoD`)j4^U-JGV=^n3o-&s25 zb?>K1Z(HyEKcrv3>HRO#o^N}9sC53j-Y=3q@xJ#jNJE>vZz3(+?0uE=;w|1^FMab< z??0Bd{lfcwrN?~b{c+MezVZGc>DF((|5cjxgZGC^kKg9~S<q|5g5ex>w> zy}kck+9%Wd9O=oOygyI6s*CrpNz?cDzNNJE0PjahA3o6gXQi8@UrT>>8nZg?;pc1O zw3GGgrF$svD8H|?oASQ$2TPAoUMxRETB-bK`Ek<8%IC;0ke;mk9Qg~Rmny$O{$}az z${&<}So%-pYo!~coAmw`=@-hkOaGEKwuejZ__dSnC+#gg!l~6)u5^&{YNuAO7f7#= zz9{`r+Wa6tUxD;Q>4VZwr8}ivv;6$o(uvaRq_0UsHo)Mv-$r_nv`~7Cbb<5|=^fH1 zrE8_zq+NRX^^TB^m0m4uD_=EIm!SSh`O7o3!TuzuY+K zRnm3R-=zl~?B~mso*=zXx2cu zU#_k6Kr9n#07uS&N_cSsX90OojYFU^wXOGiqlOBYJ7k}i`zC0#H5 zTv{t_e1zXlrnHZ=NIFJ3TY9$iI_dq=Rnm>pucd!Tn;+@7(?vQ!S}GkYoi9CKxh*K&@XoQhJH>4(S8ZRnm>p204ED4Cx^0Nzww@~W%AcZZ;;+0 zT_*j9^bzT6(qR1A*7LsnN765(-$;Lw{vvG>@%!6C+D^K+G#Gcb^&TLfE$u5Ukp|<< zHs1*Oqofn0Q>14|&yrpwy-a$o^hRkg&TQ+wTRs>UHvhYP#EpZRk4u|LgYjX@_mb}* z-Cx>W+FRORdZaW@I#}vH2jI3dLVA>RymYd3hIEefBF3g~rQ4)Cq<=_5wyfLVU_9Bhv3x6OTWO{= z7+1FG?(zpo`%4d%=1B)h%cWJ)G19TpY0??eTcvkOACNvIeOwxhFWdBs@~=wYm3}Dw zQW}gi+w^w%ozif+uZLi~*|H|`Eu`(FdrS9~2IJ2*e;@e)(md%PX{9t6hqn30$xo8b zkOt$?_Wnuor%BI|ULd_k`haw$G#HPz<%98P({;+apr5GSY32O>_SrP$p`PfFy-sDy{vpBqP*3+C z075;-&zl$OY5%jJrwe=fkN^DVA5{wGp6LEi%sx$Pf0y0UPmdcve(t2>{knWIeb$6j zJ8rJ~7?ZZ<=lFXvecH@PtkH@a>N#Q7j2V;c|M{eBb@JSCGi;`u${{_+&7VJa+V}u1J1e!qjMcFLiw< zZV3mU&vEN>e6hY`ZJK3lGIY`OaHuhrk@DWDDbsGgYiEW-?s*D7tiy(m>uq=7ui?-_ zo6l|6m51$KWYa8TlcD<-ghQEbLO;BBp83@MSoLQ(I4|7#8rd)FyV<5$#wJ6r*!tZ0 z!w>J-P;b5Utxs8>J?2TSZ@Epgj9bTtw!RY&byNO__iX64-ukxK`rL7HImZ8=TBBh>ueaA>S8*v9g1_UqQy+(1Q|6mnGjGDAn%R?j^_+E3ru}61&+0cItJi?uSvH-O zm7Vh1uU{YM`eqNX_cAlbHaw%Cv@jfIO>UiClk0Vx+HpAavtiQ&-o9vhPYs zjtY`nQ<9rYZw#`HS}Je*mN`W`x6B>5bMqnPJI-iOzGG?EzxEH^_;Kxu)gMm1wrH)b z@tTsgwcjnZ-{$t4X}^o@H_Lt(+Hc5yS2g}=YU%yk%Szp}{W9Ndo6ZV%cCY7_l<(ND zshc{dq({H^V7Mf+IHJ-x%HPh zUGxt2aYAyx=LNnd z=^qLFQAt0tb0wM=ygm}V{v5paNS3?zvB4a{>m$MI&%x`yb#ok7vVGy8V6Nk4 zcX9g2aea!M{(RhC#ZHU1_wKy9_Pg2kJJ9w!)N*X2sW*oI*jT<})rf)H$M-4Uws2t4 z_LcLR4}N3ZbG6Z&=W5r7o=Yv|^p3%L=1q?WHTcMMx7OV4Ejw>>Q{mOMYn!(m+ha9@oEf<9btTtU``gGUfp@P$<9X~J}UAQz7UYOo%*A)wL z_rBxnbr%d>Fk{qpONLj6KbSD;nGK6KtzWeHye_@kUH+prAOrt--nO)8=;DP1jTeWS zy%!qLdFn0UH9rrWyers;btUTtzfk-_(N_UQ#!%!l$I!UXrX6DpbvV0x$FMPZ+sBQ_ z+kR$6-uByvj_mYw$unhkEFH;?U`MzS9qs6j>N`5By#p%Zg)2%{4qjROXwkab&>W8H zBPA;auP9zw^vL*?C1jPI9w}K?y3W?J&gu@fLcv;!w#Pf)Kls*SBg@W!Et#F|2wdln zK*hlA%{t#O_{DLJ#BqGTudv_Mmlm(F z^(20JtZ0p`YuPV7+M2HVxOVDornBvL;JM}Y8d^|lug&c@(|#9!Tw8jD>GEaUBPWKh zt}Hygq_}WkVcp)(vvb1L;NSPXW#{>J{<7ztVehD%?a`(=+xLy-Y%dJuY@ZU&+u1U5 zoXy#OxgC!!_FGYRY+Rjno_dqt!(+;K968Lj9ETK+Eg4%p&d%8HDqKmzM?Ad2Xl`mP zQDfWllgqa?Zt!vKb&Krxq3}&3t%Tn#9bsGeZt(~^7T+x#?ph+-QhOtz{qp3#SbG-D zKC+~*o$qUtXE{f*S?9rndluU{ZfEnB%tP%+E=eBAc;~J z;!Hb(+NU1BkR89~)*@v?%&cvHgWtlx)w;pPiYv zvv;Ixaf5POv!i05{RV5T+R}6X4wnx8ap=mM&pZCZckg&{h&$)pIr`)=Uq7{Sp95Zg z?#O1l8t%QXjZi-uy7l$HvRn8`Ipy-4NxyDd_UI2bv=>=8 zFl^flMHYoa7cUA&n-5Gx)52BF+dg*O5yw6Faih?HQ072ukq(`DgRjNWMcc<8+^TbE z$;Y)tXW8#(AJ=}j`f+PL+b``{Xl>}_nfAJVVf2@U^Q|S_V#i_C@8h{DM5Z;*a&1%I z)U$J)o)ugL)&#HLZCEzACG1tbH7=v`okh*ZzBT@~WJ|iCwt05*Y`5G7J02GYYuHem zP|`TiuQyy%+{jv=p!KYFE$3AwR}6mD+RgfHX6X8hi)?+p{MuSc+e+I9dY+xnTe4i+ z&~j`9iYi@ua9Z)|agn+*VcqH{i*c9gZEV-}4o89#V@@r0t_-EGmv z@Y-#BkO!~#2CrL#*KQMnJb1k~c-(=14+oT{5UhfTFw+64>CI@-& zdT;Q$HF)hdCCG!Yq#}UfA^eEUmh^v{WWhM@M!k%ca|I#{p*jrk37EPuF1`(*?e|xJsaA*G=KTj z_x3F5ReaV-UlxC~Er0YO>6_QTG2zgickBvv@Ym4iYp>Hbmq?dN?~pE&-Y;D)T_Jr; z`jm8)bglG7>8sN9(v8yhq?@E$q@PQ_mVPJQCfy;emHv^LIXGw~J9jYpp31&*+K16U zHf9w@mOuUVw#&-5h4)~(ZArVq?TYsdxEu4*hWF`NI!b zc}n%0TL*QS(qWGSdp&dap#6`USeprKQCVw60=WTKut&)}#*VWYa_14zc;uqA@oP6|w)~A4)54H#Ugk z*X(I75!=g!iMad2m}oTS{$*2IG=8f+r-}S#Eqvs_mN_DXoVl75*r z@$snZ%129@wzOV({4;kYh-bI5%R#)Y^~KUGw1wiISQ3r@UW&jk~EHw$h5(|_|As*=qSE;AL{_ed)sUCc*NG+BHqwG z)|e3=Z~NIY{<_W6DxPLfm|DkwwR!f4e_uMLcGYz&>`Nr+nlc_N^SbUaN=_-R*!JP zeb}~VII$oj6gnuJIKoPk6;5QBEDk3wwi>@YoVd>ldSy8Akk#E);l%5<@~gv%zsy|| zPHeGiyEdG7%hqyTIMK{DaDCYR`ZpB1A)GkCigaT*QD}R$Bb+$a+rm$g#3S#zbG1^L97ERo0N54Fp zm~1Pnh$i;3wG53WVz%#<(L`sHs%WCpwpSfZ^s)tpMHADE(c$)<9f1+iM1=u1GMaeB zXc!euthbeojwZ&~xXMw{#3^>z#zYfk#?JC+;#w<2t5{;S?NRGkVzU+E#8_gs)zV3^ z#3{D2lVgcjEZh`JY_fHJ6iZZFMQ)BIj^%DD-YTvA5OPd-23h zTm1ca;$}X!lGO^hfZ@z!xAvccWv`HLq>2#CLXjcOx&8d-Kd+iH8IEbVe;0* zAy(=sTN`Y%_hz>UhZ_85J2S^kWZANF-NbEn*yp*4VK&cvH!;vKT;L`ivT8iuO}Ia0 zTsXic;#Q-J+{7|l&zWu_Y(+WCO+4Dk{)Es?#O%19<0kI1na_0-jcgyza})bmtzB-< zV;dY`wSR@1ILbwVRl1n>cBLP26J#{A4%L!}iIV%uoaOC?o79 z4l@YcHKM^#+q(NB`UaD16HzzO*7hRiCN45;(%r;NI}&j>akwRp$p)`l9XD_jAJ~Ct z=qB7loknir6Pw4~xHp(>JJ`fcTxP9LQ#aAjW^U#tzO|W~yNSnao)&Imx*gsOH}Ra+ zSW7o?s3oo3#2P!ut=&W$TgsKX!ALs<_7Matp%p&OO$@h9xIg`GaFLxwQ8!`xXM152 z?ypqR-NYK(cQ;pq>x{Orn>f>`O>+|^Rt&dXsGM z&Gre!y36imwr|L;uYOf~n(Y^g^^k36wtpzrQ?{+y0ioDIvTe*B9ExSh?qN3Dij^(j z+IcHiFZou^TfutEw{+f0)<-_Wc`I69`4-Mw+4{*hcisxuU%r|1R=NT5O`W&m9W39( zc`M%`@{P^+vhp1&-^h6@-(m6%owxEGF5kd;E8h|F3FobRN6N>YxAF~?Pj}wRmm?o@ z-pZFNA9dc!mnU!k6(F~ll`mgD&3tbwUx9qsc`IL`ydCT2(O8#AjUE3Mj~Py}eOtMs z*5WB^6JmqnhZ{7Gkdj!9Ar=r)szpV}5LppYCM!b9WkpDZtOyw@D?%z|MM#yb2&tA8 zA;V-LWVk$pjF5+rk@65SN*+Q+%R|Uf@(?mc9zu?mhmd3BA*4ngLdMEN$T)cj87~hZ z6XYReqCA95l82DV@(?mb9zv$dL&!9F2su_BLXMO7gcL^>+3|02zO`Vn!Jd#BYujVf zXURjz+42x_jy!~%D-R*($wSEb@(^-? zJcL{*41Avem3kR`Gr>WvE)OAh$V14T@(^;DJcQgW44T-kcW`<@({8?9zx!fhmg1AA!MUG zguE>eA@9gT$h-0o@}4||ye|(SAIN(`9*cZs$G^osb`u+W+!NBsZhvDR#vM71kdI?u zS-&A5WQ!IRA)m;KkWXbr$Y-)5=Q4Psm4+hSs}lag(EBb3jPOoo?Dj(HuIVmeE+$zNpzQ zLakhHCKlGx9n9NpZ#sS-^LASv$M0?4Zp#z+_U7%jya9eM^LAU_5WlB+yDe{oZ)e_a z%Nyg{nz!5XCiphy?Y6ureh>4mU(<}BwF|6-%?Vn$z>3&{prs3}j2Q$OF0ewjBxvCR zD`hK!<}R>ewkBxi0xRbp1WjFF1#Lsn#06H;wginWa6O!M1dUu^CEb&tp$n{}dl58n zft9p9LBa)A(!B}dF0hjBLy+zQD`^LUm`y_atNR(mjH_L2%spR0E!9-ps0`liUtutQ4s+Y z6%%-h_76v{F+ehovcZ^GS5fr1jjF^3hvSYfM^RZg_D=&Vps1YXMNtJ_6b;3TqDs6d zs=|w+YP={Kh8IP{@uFx1UKEYQL(wP#C>l)wMMn`p(HH_KI+_5Ajv;`e8UiR9O8`aV z2%u;@0TfLjfTD>6P&A1EiY604(G&tGno0mg(+HsGSOO?IjsS|L6F|`n0w|hE;3+B% zM>ZKC8IRg%U2KRb+F-Xhv034`n6l6Y!$wM7$_E z2``FH#*3m;@S^BcyeK*i4@IXFK+zclP_&Q$iWU(-(U}BLbQS>=olO8m=MX^Axdc#j z9sv}cPXI+15J1s|1W zqFeByXenM4-HI1Qx8b4ab^<86g8+)|B!Hs32%zY00w`KW07dr@K+(MfP;?&w6x~k% zMGp`_(Srm~^bZ0kT225(4-r7o!vs+D2mutWAb_Hk1W@!S0Tlg{0E!+X@DyDWj<|og znDM&1FS=F~?HBaL!g0r!qv+{y>;ijE6HxRF%Zs9C@uFxIUKBlt7e%Y_qG%0X6s^UJ zqUZ6VXdPY@y?}?J7YU%~B?2gVnE;AjA%LP+383gT0w{W&0E*rqfTHyTP_%&niryrE zqPGa3Xd?j>y-ff`?+`%Iy97}59sv}+PXI+95J1s~1W>ez0E#{$@Dx26jy!09Wc=ou zpQl98ZT7$`wmBSkd^w6f4aeTF=UV|qpRv3s`W!EczQBv3FY%)2E4(QB8ZU~z!Hc4; zcv18%UKD+YhobKZpy&qzDEg5Ainb9z(N6?Ww4DHoekOpT9RyJH3jq}EB!Hq{381K! z0E&JifTCRlQ1m+i6#YQ}MgJmzqCW|s=q~~&3Z*4``M!@9CV-+e0#DJFaAb!8lF`Qv z7Jed%R=MX>k+itu%TW|hi?!ZQ6eU<*6g9w$qK0@;)Cez%8skM#6TB#DiWf!A@S>*{5kS$N1W>dW0Ti_-fTFz#plBZg zDC$4}MVSOp)R6#+IuSroX96hdLI6ek63`ayM*v0p6L^YZX^}$=kc{E>Ks=V7=6m{^ z?DGb(u4!?{m!s&wwAfKyMNtoy7ezhsqUa#JD9XZ%qHMe<>V+3Yz44-`4_*}Y#fzeT zcqr;m07U}`py*%%C_01yiVh`!qQeNF=x_okI)VU-jwFDhfdo*LLjXm&1W=Sm07dx( zP*gwwMTG=VG>8C-iU^>nm;j0f6F^Z30Th)Ic#68EMHU($84-KZ8S5^JUbO+~*pRfi z(H&Il{@}j5;FN&)1qG%Xi6b;9Vq7iseG!ie0M&U)#XuK#o3J*nN2%zX_ z0w_9$0E%h|plB=s6pbT*qVWV!G=Tt$CK5o=BmyX!OaMhw2%u;x0TfLmfTCjwpy)UP zD4I?HMKcJXXeI#^%_4xJ*#uBDhrm-*o)%eWfMhgx4@fISQ8#yao0}GQd^w7aPm6tZ zpeQ@y&MF2%t6F|{51fHV#X_3Y~jG~9#sN(`rG{rs?7rQns?)Y*P-Ix~ZagZol z!t$c%CcG%R883=%!Hc4$cu{mKUKHJi7e%+@MbRC2QFJFBitZwSqPq#8Xc++%-9rFH z_Yy$SeFRW+KLHdyKmbJ#5q%ie4drqE`u^=rsZ;dYu4@-XMUY z^#o9~fdGo$B!Hr~2%u;q0TjJW07dT*K+(GdQ1l)F6unOXMIR7A(T4<3w21(UJ|cjk z%>+>NF#!~9A@CGElNPzo0Ld6)!_={7MbQMitB!q=7I%C(ioQsTJ>FXseaZ5o=qtP^ z`Wi2azQK#4t$0!NEnXCThZjZP<3-UAcv18t9*VXRK+#VGP_&%@ihd@5q8$WK^a}wL z?IeJrUkRY7mH>)=BY>h^1W@!l0Tlf~07d^IfTBMMpy)3GC<;Z?ZHJ;T0TiVXKv9GM zilPKi6eI8yeU=v4Y=C5(WluO_pNpc98-h%a#2sIbqK1*!UwuVUBbFCMjq#$W30@R6 z#fze5cu~|GFN#{=MNtM`6t%>QqE>h)YE1w|dk{cT8v-b5O8`af2%uPP@Zod}?)GXWHJA%LQN37}{{0w~&_0E)U2K+ypNP}GgU zQ`y_atNR(mjH_L z2%spR0E!9-ps0`liUtutQ4s+Y6%#ZMPu-y z=xDqsItC9#H3U#JmH>*z5kS#+0w|h507VlCplA{S6ip_8qA3JWG?f5~rV&8Vu>??b z903$fCxD_E1W+`S0E%W2K+$XhD4Ih6MRN(DXdVF+%_r~_RYoGq4Umjm?T?mXRifw^ zHw3vL5_fz#icX5eHXJ63PG)&gbP8S+or)Jlr{P7>>3C6e23`~`#EYUucu{mFUKE{$ zhoZ9ypy(U|C_0w_iq0c|qVox$=mG*Lx{v^hE+T-UiwU6U5&|f?lmLn@BY>jC1W

    kHLj+LtFaZ=jLI6c82%u;s0Tew-07d^K zfTG6;py+V|D0+ebik>8ZqNfO;=xG8ddWOJLv?LNa%mB$a)IG+(Nfe!LPhn%vM&gby zN70%{?C2a(w3g*X(erpwv<@$dUcif@7xAL#CA=tl883=n!Hc3-@uKK8JQTf707Y*Q zK+$>vDB3^(MQ;*7(OU#iw2=Uc-X?&ecL<>9T>>b2j{u6^CxD_42%zXg0w~%<07V}W zK+$FbDEgQHinb6y(I*5@^eF)peMaCZdM*+<(*VhM!hO_wwJ5s7b^AY$#2sIbqOT*d z+w(-xH!LrTw&F$6w|G(X9bOcDj~7Kh;6>4ocu}+sFN%J`i=yp#DEgTIigpk{(Jus0 zw37geekFjSS^_BgjR1;v5kS%J1W@z`0Tlg<0E+%3fTF($pePhow;hVY1W=Sl07Vf3 zD2ft5QH%hJ(g~m_P5?y-0#DJGk;sb%NX9zXx&KNOxo7#Y2GO|V%Td%M8vCX|6g6de zQPd1Cikjm^Q472%%D{`FmUvOr3NMOU<3-UPcu~{_4@GSWpr{=I6zxd>MSBrIQF{U? z+M581_91|x4g^q?NdQG1381JG0Tgv6fTAu0P_!=r6zxX34J3e~90DlHC4izl z0w~HSfT98dC@Lg?qCo^uR73zp#RO0^m;j1O2%xBx0E&hXKv5Y16qOS|Q3U}M4JCl0 zN&-(&Ry0y=fMo1)pS#W$MRT30ipCvZj-nCK*n+{LXe7&vqEUEJG#W38j>3zgF?dmQ zG+q=PgBL|Lcu_PKFN((Dp=dk-6ipz2qKO1hG>HI;CKEu>6apxkN&rRE2%zX#0w_9; z0E(s)K+y~WD4IzCMY9N?Xf^>9%^`rIxdc!&j{u716F|`d0w_A30E$i^@DvS;Ms6@b zGTir($A*idXB57cqlrL0E*5hfT9Zspy)yZD7uIMiY_LAqDu&%=u!eGx{Lsd785|x(U6x~PwMN0@gMJGoiTMUp4_bn!| zQ$*23Hw1Z8H17Cv6x|w)h08_JZ7eT}ZpVwFJMg0DPP{0(3onZ9#*3n5cu{l@UKHJn z7e)8sq3C`BD0+YZiXJ3@qJI!T(Q*PPdWZmu9wvaIM+l&31pySTB!Hqv383ho1W@!C z0Tew>07Xv_K+%%~Q1lc56g^D- zDB3^(MQ;*7(OU#iw2=Uc-X?&ecL<>9T>>b2j{u6^CxD_42%zXg0w~%<07V}WK+$Fb zDEgQHinb6y(I*5@^eF)peMSI9pA$gQ7X(oBC4r}CZ8S370LdtG7qRC>(X7U1zKX^j zUyh=0qp?e>MA3IFFN(g$i=rR!qUcAwDB6Y>ML*$1(RREj`WY{ZcHl+PFL)^0NdQH^ z5yQ!?N0zjT?wG*00JoLMgT?K z383ge0x0T107X3spy(h1D9R%66g7=SY7LN#loKDe4`I9ASWD404~l?jwqBaf3(0V{ylqqiA$2Rx?@@9mVpZXbfHy z9gP=7$KXX#4PF$D#fzeGcu_PSFN!AMMbSh&6ip(4qR9kMG=%_)rV>EWGy*6(mH>*5 zBY>jm1W+`C0E%W3K+!A$D4I(Iwcl&d^w8Fh{f(4BZ?NXyeL|P7e!~{MbTM! zQFJz56rF#*Aqa|4FphhBLNgGA%LQr2%zX@0w}tL zz*BTuEb_7ek}=qQ?)r35l-0t_(pcQ_Y zDEbvIifZvt^cw*b?IM7p-wB}T4+1Fq7XcLgNdQHE5kOHWUEOvl3KKw48UYkV2%soR z07WqZC`u=QqBsE*B?zFX0Ra>>B!Hqu1W?qN0E(IrKv7cyPtkX=$Pxo2quNpQy(s#{ z-CZ|Jk2}5`MJ>}~Pfrp>tyo?ZwZ@C0J@BHa4PF$r#fzeLcu}+`UKH(x7e(#yqG)eC z6zxL*MI8vBD3bt+IubxpCjuzyOaMh)2%uwR6m=tjqV5Dx zbRYo~^&o(vo&->I5CIfr5kOHk0TlHjfTG?6o}w1%kxvbfjA@w$PDZ-#=`VIyv_9!^ z$CsmMKzb}PRTLe}@}lSvyeK*pFNzMsi=xBvqUZ>`C^`}^iU#6EQ4U@d<>H|zj{u7D z381Ke0E!9;plA>Q6crIbQ857&4JLr15&|eHC4izK1W;5)07c~lP*gzxMMDXosFDDR zstBN{ngEK15kS#!0w@|m07WASJVpJ|BV7%UjGx>^tiLE~;{Nl@sPwqw%TaW6daU?Z zQFIK;i=rC5C>o0wMdR?IXgppNO~8wyiFi>o2``E!<3-UFJQPhOfTC#xP;@K-6dgwZ zMbinOXa)fk%_M-LSp-ltn*fUD5J1sf0w|hC07df&plAUB6dg|hMJEtI(TN05bP@p+ zolF2lrw~BVsRU4T8iA+isPxE810GZ zD+r+IN&+aliU5kPCV--A2%zX%0w}tU0E(_BfT9}+py);dC|W`QMK=*Z(ai)R6F|`u1W@!O0Tew&07Xv|K+!Vh82s}l1rbl)eAQ|_&i`ZSFsF(Y&(TnME$Csn%)%4h2b41Z=EH8>)$BUvj@Si=sF2qUbHWDB6e@MQ`Ip(K~o3dY1r--Xnmb_X(ir0|F@ekN}D{5kS#L1W>e@ z0E#{)fTAq~Q1l4_6n#nnMV}Es(dPtE^aTMFeMtaCUlBmj*91`X4FMEwC4i!D383gZ z0#DJ)>5+j3NXAp{Iod0t=9KM1MA3GZ7ezngMbQqtDEb92igw~f z(XV(>RErlyzu`sEF1#rE9S=o+5J1tt2%zXs0x0^60E$9!b=#pROaMh`1W*(qfTAb? z6vYUjD4hU`;sj8XAb_F<1W?qF0E!wBKv81?C~86gMNJ8ys2KqiH79_g76hK6AJZe} z8Xy_(yXR=zMA2XFPaHGiamSaVXpea8?ggT#4aO=rVoe7|*3jq}EO8`at5kS%Y1W?qK0E!MEfTC^$P}H3O ziVh@zq8;4kCb}ECMLXCV-+|1W?qQ0E+q$Kv7=;DC$SxDQXpuylQ}C+~bCb zTE~4)|1ft&>mQFhz8pn|#$(@~Ac_uSc~NvYUKAaH7ezBMaSZy=r{r> znoa;kGYFt)CIJ-9B7maV1W+`G0E*@kK+!w`D4I_IMGFX^=y(DsI)MO+P9%V$lL(;b zWCAEUg#e09C4i#S2%zY60w_9z0E!k8c#4jRM@AYT8Jpd6v>H+LQKp$i@wns5QFKl` zcG9V$=vV#Em-MBZ|WA{};Uyk2}5`MQ_Aou|=Y2J z#fzd^yeRq&FN${IMbYngQS=916#WY?ivGky(O(2m6iTSu4n<)CC`u!Mq6h&LMG2rN zMgT?W1W*(wfT9Ee6g41#qJ{)e)QA9z8WTWK69On|N&rR82%xAr0Ti_$fT9cnC~8Rn zMXd-tMcd<%*#=0)lC}oU&!Q-;y_wdDxZ}%F)GiUb{2WoVC(DbXz3`%_Jzf;;jTc4x z;6+gfyeP`Vi=vKrQPc@9iaO(=s0#rU?Mnbf`w>9V{sd6el>mwkAb_H71W?qS0E!MI zfTA7*P}GwEiVh-xqAUU^$|iuKUIb9on*fUX5I|910x0T707d-?plARA6dg?9DQc65 zJZgYsRCY0N+9rHYe~kM}qC*mK$Csn%h(zq&^F+~+EH8=%;zdyoUKHixMNuAJ6y@VZ zQ2|~Q72-wFAiO9l!b4Fp0Tc};fT9utC@Lj@q9FuOR7L$TV381Kw0E(&z zps1PviiQzD(QpDN8bJU>BMG2r6af^CCV--&2%u;T0Tdlg07b_Tc!~~7ME)>9GWxlm z{^6qN!PaJK5^=|uqi8}Rw)cgiXd=stqDgpBG#M|7rr<@4S z*@?L0%TaWGA~xY-QFH;zi=qqhqUa*LD7qLgiY~#6qD%3j=rX)0T8tM(m*Yjz6?iDR zk^qXXB7mZ+383g20w}tc0E(_7fTHUOpy&nyD7ujVik1*S(M<$UbTa`I-9i9GO9`Op zRstxxjR1;nCxD_m2%zXr0w}tR0E+G=fTCpto}zOTk@F3ZjQRT*IOmC?YWFX(?n%TQ zUyh;&60v(O6-5uSyeRqyUKB0Ii=v0{qUd3~D0&1hidNu7(Mr51dK52;{)va8#|WV4 zaRMlMf&hx1B!Hr)2%zX`0w{Wh0E(U^fTC3dQ1l!D6s;zJqBR6iw3Yyho+p5!bp%lK z0s$1gNB~7I5kS$)1W@z}0TjJT07b76c#7^zL|!*QGOkV-IQNU9rtWdb>xsDI%Te@Z zBKG5AQS=tei=vHqQS>%m6upBNMepK8(R+AN^gdn`eSjB5AL2#PCOi~ z0w~%-07ah=K+&fJQ1lrA6n#zrMPCp=(U$~J^c4XVeN6yG-w;62RstycmH>*rBY>js z383f)0x0^C0E)H|K+#VGP_&)EQ?x!2X?3|#w8C}EHi)A3ZXo;TMBMS^DEc)K>wBdr zs%3dm^c!9j?ZS(q-|?d854&NB~8R2%xAj0TeYMfTE@ZP}Gb7ikcHZQ40bn${>KEmIVJF zdG7%oRoVV)@5!(;kVZ0;2`wam0t#t#5g`>qLK0E{v4j8-P?`y#C@3oS-W&Gbd+&(7 zVeg6^6%|nwl~>Pw?|omB36}SL&;OkDowdGME8O$DWH@%`t^h2G z0DOzKwhvAhLBh9Wia0-+Mc1fB=^aAqms-@bgL~-NW>GKNn?)I9v#2-OEXpLCMOkFC zs1MmJ>Pt3@`jO3|oyca<&SWg=55S@U04y2^z@l9MShOnuiv|I(XfObavH@6>1HhtO z02bu|uqYpZMMD5sG!%eE!vI(`9Dqe509Z5FE@EGj0OMI~gjsFZ9LjVGH$6Ub&! z8QCnFNH&Yg$yihYz@kY2EUE-xQ567-ssUIu8GuDK04%BnU{M_ai|PSbGzEY~Qvp~s z4S+>^09Uztp1rI=G<=%%VB8H;d+y&7yf^vuJ;^S#$u|ESgU?ix!a0qJ?C$Xc5^gT1>{G z0|8jn48Wom02VC)V9`^qb70ZK~9<9YX4tT6AIu zchVZO=p@>kMJJQZqEpCb(Wzv!=rpofbUN8AI)iK$ok=!}&LW#dXOpq$8~_%b3&5iD z09bTB0E;dFV9|vDELsD=qKg1nbTI&nE&*WCr2s6t41h(K1F+}{02W;dz@n=FSadZ2 zi>?7+(X{|9x(JB@r+;IIkou(--P*xD^J25; zHrks-x0B7HJIH3yon*7*0kG%^02Vz7z@n!BSoAaii=F{s(X#+7dJcd^&jYaN z1ppSk2*9G309dph;9GQahv2;;NVq^hcYTXlbb(s*a)*%mr53&3!F~Huv*-=ln?-Mu z&7!x+X3^VZv*;bNS@bU1EP9V@7QIh4i#{NmMIVx}XafL?J_2CT#{ew)1b{`K0a z02X}?z@jezShNvi02XZqVA1ygEZPFVq8|WQ z^dkU^wgP;MUhNS4T?7gD)!WstnMFJ65$&fAA@xfw`n7}G`wFw@H`<#;+sS6pzsP3M z?_{&+53*V0B-oX^Srj0fMR8=aC`dMo+L5uy1z=G;0ERP12Ed~30NX%y7JHc(b$}GyHy;+n+HjDa@&7!_!v#1~0EZT`| z7VS(ni~5tzq5)*HXdoGjb^&0~t^h0=1i+%f04&M|U{MYLi*f;2ln20~d;k^=0btQk z02U1cV9{^@7L5R4(MSLmjRIiNZU8JA4Zxz^0a!E!fJJ)%uxKp6x2RV_@B|SgT%h7) zB=}eQziJql5K_O?qT&SihHK2C655+ZrDU^cJlQOoKsJlY$Y#+*vRPD4Hj66AX3-?F zSyV~JqACCuRRgeSG60Ke09aHDz@j<;7S#i=XbJ#}rUI~N8UTy-1Yps002b{9z@ohY zShNoSi}nRzQ3C*rW&p6L5r9QA0a!E(fJL(bzD0!z!Sy0Yc$yx>ip-+r`pJ-{gpm5B z7R^g=zrW5b+Mo7j(E(($Xg=92T0l077Lv`PMP##RG1)9SkZcw;lg*+QG8QcXV9`iPS#$>3EIN~H7M(>li_RvSMdy&sqI1b+(RpMnIv;>V7XYy6LI4)6 z0btQZ04%x~fJK)8u;@|%7F`CwqRRnTbOiv5t^{DwRRAoy8h}OD0I=v<02W;bz@qB` zSabsbi*5v9(M

    x*6bGbW%caZxJLsK1IYi*({o%CrP&?gw!v!=#B(;<;`Z%owPTL z?joB-cazPcd&p+dy=1fKKC)SKKiMpLfNT~$NH&WeB4g3R04#b0fJKi2u;?)W7Oe$f z(c=ItS_izlGEg__SsYP!kxR2jz7QIb-v*;bNS@bU1 zEP9V@7QIh4i#{NmMIVyQq77uT=p(XO^f4KWJ^^6SrvNPa41h(S1F+}|02XZoV9}QV zEcyz7MPCE3XcGX7z5!s-w*V~q4uD0Q0a)}s0E@N&u;>Q>7X1joqOAZd`U!wVKLfC6 z8^E{djfCJv5hT1(e}J~8GuD804(YVz@k(D z7Nr5OC=9@&P5>a|XMSW>+7WE^WMLUtrqMgZRQGc>oG=OXt4J4aI zyO7PIUCCzAATkyW24GP(0E=<}SdnLuxJDTi$(&l zXcPd8b^~D1XaE-N4#1)@04&-AfJI{gSTqiRMFjvXDg^izWhMrfh#=v6GDV!MME^>E zpej|A7*fB~qVb9D+4q=56KHQ1m66S&iDa{=oNN|VkjqL~0Jngzh3*#InR0$|a804$mV@GUAy4Bjt-gxBhaWJ}GW4E;jL+{BRjr54Rk zbl<(tELuQ&vuGjNELuc1ix!j3q65ihQ8U>rY9X6NOUP!?QnFdJjEqGG0kG&`02VC= zV9_A}EIJf`MJoVUv=V?thXJtYZ~zvq0$|Y*04zEZfJH|EuxK>^i;f0h(J=rlIu?LM z#{sbDcmNii0KlRX0a$brz_)1s#GrG(SoD#8!}GSMOOo`=o$bPT?@dX>i}4EJphYt0ASIL04%x*fJHY0 zu;>;57TpTKqT2wzMW-ePOGS|ICOx4(%`E!7i-g+~L+Y1Wba$dV=V7zx9@?8l_ma(` z`^aX|{baM~0kT>2AlWQ>h-?-;Og4)iA)7^ylCkJ902ZwUVA10MELsP^q9*`Y^dta_ zo&sRe(*P`b27pD+0g02VzDz@irbSo9(Qi(Ud?(Ru(Dy$ryjR{&V_DgcXK17OkX z04#a~;9GQOV(=spB%Gvo9q%%W-q0P>n~5RyOD%dg(Y@(Wv*)F&7u#;X3>Xa zvuFd^Ec%FS7JW=Mi#{QnMW2$*qR+@!^f>^Fz5rm+MgSIl3BaPS09f=j0E;#Ou;?2A z7JUoAqVE7$v>AX!-vh8{3jm9L0ASIN04&-Hz@nc3SoAXhi?#u<=obJM{R+UM-vGWv zZzl#{5kbPw>h0=x%%XW261FFX)GxKjNpgQ!YZe8P>`LA&iX)pvL9$uYj%*gWWV0xq zY!-#cW>I^xS=51S7A26eC=q}~NdPQL24GPN0E;>TuqYLPMQH#m3InjH699`k1F)zI z0E@Z;uqXn+qI3Wjbpv2gcK{ak0ANv102cKEU{MADi+TgFC==jY^m}43{c*8qtllsB z!z}8iN@XR5)GxJYrzCgO6K2uQv^R_Tlg*+5WV2`>*(}ZGHj4(4&7#3%vnZQv z7Uht!C>MZ5c>pZR2Vl_<02U1eV9_uD77Yhr(Fgz*jRauPC;%4i2Ed}x04&-afJI{f zShNQKi^c-5XdD2G3IJGC2*9Eu02UPku&4y!ThuoxxUUEjK1P3ereBhOrQfJ;&6XyG z)GxJYVv>9KQ)W>)?aiVJvRO2VY!+3L&7vx@SyW9nizbuJq8hSUR7*CC>d07B55S@+ z04$mcz@ljYEZP%*MbiOTv=;!2_6A_lJ^(D*7l1_#04$mTz@kO~7R>};(JTNK%?4mm z699|$17Oh{02a*!V9`7P7VQu4Et-%Nyix=S-_%FMDKm?9*313_l0xd2TC^z1ec~Cj zXff^0q65ihQ8U>rY9X6NOUP!?QnFdJjBFMiL^g{KCYwde$yjs<0E-R&i_RgN zMdy;uqVvdR(fMSv=mN4?bRpR+T0=IAE+U&n7n8B*5&#xm3c#Yv09bT60E?~wV9}KT zEV>GSMOOo`=o$bPT?@dX>i}4EJphYt0ASIL04%x*fJHY0u;>;57TpTKqT2vibUOfx z?f_uXodDmWGm?V2B1rfG{oM7LX3qE`S|^eO<0UISp!>i{fz1As+u0U02aLs z@GZJ0DY#4o3D4HI&h9mf9#4?)PEttyQj0!Fa?f3F7JW#2vuFd^Ec%FS7JW=Mi#{Qn zMW2$*qR+@?(dT5d=nJx0w2_QOUjne`D*zUK4ZxyJ04(|jfJNT|u;@Dg7HtM#(f0r> z+5*6$9{^bNBLIuG0O02ciWz@lvcEcyk2MZW^D=r;fsZ3ke{zW`YDJHWT-y`X%v+Om^RY#Vl%<-1bV}C7VU@WV0wlHjCPm&7uxuvnYXV z7A2C+q9n3eluX8=6aW@=1Yl7r0E^N9SQG|eQ6~Tvbp~Kj7XTJ@1z=GGfJNy5Eb0cp zqV51J>H)x_o&YTB1;C;V02cKIU{NLji?RS%)CYh?eF45jf#hJ^t76e|{itdP{ z$yhW5fJH+ASTqcPMZ*DDGy;G{BLP@63V=ns0kCK^0E>19V9^)=7VQDRqOkxh8VA6l z0ss~j0HOu=j7l75hQ%EUflOLi*ofHkh0{E`lS|4 zN_OYHX%fJL(aSTq}eMNI%K+7Ez5a{yR07l1|c z09dp?0E-R)V9|U47A*ky7L_LlPZ2@FZ|OTA6=u<%dXls-Ii!B6Ma{|XEpMAeEwnd_ zmXOV&rDU^c8QCm4h-?-eOg4*_lg*+-$Y#-@WV2`m8H-i|u;?%V799@2qE!GaIs$-2 zM*^_uC;%3%24Kb z02ZANz@jq%zD0|ZgRhAo;TQBEcA#0bdy0fJlSAs4T6Au*yY*eO=sen+Mdy>vq6^4o z(S>BQXbsscx`=ERT}(EME+Lymmy*q*%g9)CIRJ~U0ASIT04%x+fJIjWu;>~97F`R# zqU!)ybUgrzZUA7>jQ}jV34ld61F+~802bW}z@pm#Sadr8i|znm(VYM+x(k3scLT8K z9)NGr*~!7~?}O7VX|5D2-z%plx!9~ zMmCGqlFg#W$!5_yvRU*5*(`dJj73iYu;^(37Ci&NqGthE^c(<-o(Evj3ji#75r9Q6 z0kCL20E=D*V9_f8EP54yMXv#{=yd=Vy#c_YHvw4m766Oh24K-U04#bJfJN^Ce2eZ+ z4$crk!u|C3t{*UqzEO+bPY$VHYSBl@?hzZzqK|2B7JWiCi#{crMW2z)qR+`@(HCU1 zXd~Gy`jTuGeML5lz9wVQCIA+F1Hhth0a)}M0E;#Qu;_aL7Ht7w(GLJD`VoLdTLD<~ z699{T24K-P02ciMz@lFPSo9kJi?#!>=wARV`W=8pe*mz^NwEuaED8X8i#|*aUM+%z zZ_^LSZs3TfZ->OCgw!v!C_cq~>SMDgM0>NSJ=rYkKsJjK$YxO@*(^#Tn?=cFvnYjZ z7Ih?>MX6*gN&{d~7=T5c09e!+fJI#ZSkx7OMG*iNr30|28vu*C1F)zE0E>D8u&5UR zi!uOM)Ej_BnE))x0$@=e02cKHU{OB+7VQMUqMZT0MeS08n?#WC`+8aCrubL-C+JUw z_D>0^Uuw~=DQ@y-X3-$pn?-}kW>GfTEXpC9MY&|ND35Fw<&({#A!M^?DA_C;M#iGy z04y2-z@m`=EE)yCqTK*kG#Y?Ky92Oj3;>Jv0ASHr02Yk{U{L`8iwXf)R0P1HVgMGE z0I;YOfJNg0STq5EMP&dinh3z6a)58qz?5LV2olcFU%}eNEIL5n4yi~9sb6YQb&6a2 zg;_M2_GVEH*(|Chn?-eGv#6eI7EK|WMN`RU(KNDIv?tjtnoh=|y#QFWHvo(F0btR- z04!<%V9^W!7BvE}XeI!QW&yBhHUNv709dpi0E^}TuxKs-i{=5aXnz0}9RR?h`2Z|h z0KlS!04!Prz@o(f-=fNt;K3qDxL<~dQ)L!S(sw`(ObMx9YSGdZ_xvx-qGhx=n%45bST*@T0u68R+7!4!^mdQ;bbgY1;C;s09bS+0E>L02ZALz@k$CSad1?i%tVz(dhszIs<@3X9BS3 zEC3dr4e%{$NeMnIf`m)-AhyITs`W0|QbOvNT695*`{CDS(S@`(i`J0MqKn98(Zyu5 z=n}G7bSc>^x{PcVT~0QOt{|I5SCX;lDgYK;4Zxyn09bS_0E?~zVA1seEV==JMK=Pl z=q3Ob-3-8@TL4&eD*%gb17OkZ04%x#fJJu#u;?xT7TpcNqI&>XbT0sl?gL=a{Q%#h z^HPHCHi<<&^seLiX3?BD2@j-%)GxK@kra2QZ_T1dX>S%iMmCGqlFg#W$!5_yvRU*5 z*(`dJY!*F5HjADnn?=u%vFKR<7Ci^RqUQlv^a22jUIbv#O8_id55S_A0a)}30E=D) zV9{#;EP5S)MQ;GG=uH3?y#>Icw*gr64gibZ1z^#804#bRfJGkwu;@d8Z_z_3!HFVB zIGicsJZu)N3`*FL5>mg^qEA!Y12&sQpV8hd`kZVQeL*&hHj>SvFUe-nS7fv3YqD9i ziEI{qLpF=PC1cTd04&-Jz@qN~ShNLzMLz(r=tlq+Z3SS_PXH|X8GuFG09f=30E>PF zV9{>?EZPphqJIIf=yw1X{QO{t(&Hyax0>GlK04$0CuqYjXMcn{c)E$6DJpfqL6M#j%09cd(z@pv&EXo96Q5FD; z`T($~F93`B0kCK%02b{Gz@q*DEE)j7qJaS4qEN@+8zM;falO&lzN3Go|Ek`C+@)hk z{ZfmvJGwvrXcpzr-Ym)`n?-qKvnZcz77ZbrMMKGE(J-=EG@NV}jUbyvBgt4a3V=ns z0kCK^0E>19V9^)=7VQDRqOkxh8VA6l0ss~j0U5bydfZ`lS}tc67)5Y!=ng z-Ylvon?+N|X38y!qP@sw(cWaUXdf~b?F+!71^^b#0ANug0E=b< zuxJ(li)I6`s0n~Y`vI_M4gibh0X48WoT z0a(-wz@ip_Z_(tA!I>gR_*?y8T8&xsm0GlY!+QjHjAzyW6`w$EV>SWMb`tc=mr25-3Y*l|7TpQJqPqZCbT&8vrbN z6M#i;0kG(802aLiz@m2nSo9tMi{1xd(FXu5`VfFc8vt1J5de!m2KW{|+A%m(1PSk< zA5449EUMPe7k$z(q<*PIUvzZq9ql03aW~T5Ec%jc7JWrFi@qkCMVrWG(KlqX=v%T` z^c~qO+DtZ!z9(bR762Cg0KlRj0a&yZfJHw6u;^z17HtDy(Jufj`W1jhzX7mlI{=IR z1;C=;0a)}00E?VdyKKjz004{P09X_RU{N~&7P$Z{iU(j(2;f`vS;ycZB1m|%zK`~~ zS(MjJLi^N^`lS{nrMef!nMKL8H;YopW>H77S(HjPi_*wuQJ8ENbt0QZoylfV7qVH@ zm5fCZ02ZYKu&5gVi@F1_s0RRxdIGSh7XXVg09e!;fJK=AEXo34Q6B&n^#x#2KL8f( z1i+%50a(-@fJFlUSTqoTMY{m7XjcFh4FdQUC8P!)6+yx)^i(J@)xXmJK`k1b8dAU1 zqP$f1qjqLdKJCq-A!M^?DA_C;MmCFvlg*+LWV2`_*(@4GHj8#6n?<9^ShPC;i^c%3 zXb%7ujRj!QH~CLpF={C7VSJWV2`n8H*YLSTqxWMY8}{G#h|LO#m#~ z4}e8;09Z5^fJO5FShPO?iw*!_(R=_FEdXHALI4&m0$|Z%02Unxz@laV7PSDdXbAv| zmIAP78Nj!wE;U#of`lK`_tEOjqEx-?KPWY%eyK%=rn(C{m_;jSZx*d2n?;9_&7#A} zX3;9LS#$*1EIN{G79B-4i&m4(qNB-JbPNECjs;-RaR4kj9)LwB0I=vp02ZADz@n1@ zSab>ii%tb#(P;oIIvs#TX8^G1OaK<01;C=S0a$bn0E^BAV9|L1EIJ>6MHc|D=t6*R z(el*b86rsdi%b#c5VNS0ew2SrYDoQ3i!M!d??^O@E~C9!bUE29x`J#LT}d{Jt|FU7 zSCh@6YshBNwPdsCI;57TpTKqT2vibUOfx?f_uX zod7Jl3xGv;1F+~G02bW~z@qyASad%Ciyi=A(SraidI*3;4+F615daoF3h*tuI5qf| z2oi4AxA8AAi{4O+9!m|WUuw}4sqQbyX3>+hH;bMkn?+BP&7x<>X3?``v*j}DtfskAqX(#U2}m~0kxBAZ2>$!1X(vRTxXY!*exW>GrXEb2zaqV51J z>H)x_o&YTB1;C;V02cKIU{NLji?RS%)CYh?eF0e14}e8G0kCLi02cKJV9@{o77YYo z(JlZi+7*CBg8*1G7=T6D04&M@_!cFn1+N!D!q2)QPD+}8rN30~I_9Q@)GxJYXqx+6 zXR~M+?aiX$WV2`l*(@4KHj74)&7$4NX3=P}S+qOZEE+>Li}oO6(O3W$jRRm&0RW2% z0a#Q7z@lOR7L@?7s1$%j;{jMS0f0qi04$maz@l;h7F7VSXc7R6Dgjtj1;Cc#yKv#3Ph;IB^$sb6Z*o@s7c#4MUld$VXSvRSk@ z*(}ZHHj5g_X3-3?S=2~2i)NC|qFH1tnhn6BCIA-g2f(5^04$mdz@m8oEZQG{ zMF#+|Xg&ao767nlApnaO0kCK>0E-R;U{Nywi&_9!v;=@fO95E441h%k0kG&`02VC= z_!dn~3l0}S!tdzW^)$2SlPn2`q=nQkwdk-kcWO7Y=y2MbMXShW(Gg^`=t#0zbQIYv zT1_^KjwYK$$B@mUW65UGabzqy9)LwB0I=vp02ZADz@n1@Sab>ii%tb#(P;oIIvs#T zX8^G1OaK<01;C=S0a$bn0E^BAV9|L1EIJ>6MHc|D=t2M%tpQ-sMF1?i7~os9A}zQ= z1PS-kyN)Z(qHY>4Neii8YS9&G?nOP!qAO`{7F|U)i>@Y{Mc0tcqHD=!(RF0A=z6kQ zbOYHex{+)a-9*Nsn*msK3jm951z^!_04%y4fJJuzu;@+z7TpEFqPqcDbPoWF?ge1c zeE=-FAAm&<0I=vm02Vz2z@mo%So8=0iyj4F(PIECS_{CU#{s@Ym!$>QiXh?rl0=-# z&7!N-qIGE@^-C>!I?es0ms#`-?aiWR$!5`WWV7gbvRU*3*(`dIY!GkA0a)}I0E<2cV9^%liEc%XY7HuY*Mc_A9g6}0EQ$kQQ4oMd?EqNh0=D}5r9QW04z!d_!fPg7OWIO!k?sxIGfC(C-m)*lyFG>Qj5Z2 zcTpd+s1xnYqRwQqs0-OF>Pj|?B4o2Doop6$Bb!Ct$!1XxvRTxVj77ZwSd;<4qTT>3 z$^>9h766O-0I;Yp0E_wouxKX$7VQkcqW%CZ8UVnefdDMp1%O4n0S&d zBAZ3KkZ7HjBoR&7yH+v#5ZKMTGz?Dgt0pF#wB709aHCz@qU0 zESdnoqA~y$O$1<3IRJ|)09Z5$fJK!6EUE%vQ8fUICIhgj27pDi04%BlU{O5)i>3gu zXez+BXjnM-jtCMi(l`lS}_9d>`)*(}zFZ<^Zs0E&z+>0kCL)02Unpz@qs8ELs4-qJ;n~S_HtN z#Q-ci5P(I^04!<&V9^o)7A*x}(J}xQ9R$Flg8^8y9DqfK0I=v#02ZwP_!dnM2Q&MN zMPKOWuJ04zEkfJJ8ju;@$x7M%saqO$>5bPfQE z&IMr6c>pXrAAm&{0I=vn02ZwQV9`YYEV>wgMVA1u=u!X{T?X(iIy@ZQPXq}+CDC1F z78R;emxn{@m($gWbNhChnfMAPX2*$Ek~)xSQili@dzM zQ zvnq0Ot>dhYyjt%#$3?nLbDWbR4bvUxw8&L^JI+~=ulIGF^CEeTjo^-Cy-skPPb0HVa-5Bk z>rQc;O_A?TbDYhQVP`tdkC8*qcARaI$If+}?dhQlWcdfuC#{hc5J*4sVp#)$^tUgS zRS-z;eTA%pKzh?vvJwL6H(VoYA&~z4b+Q@)=_78G^$;LFFG?1?UCFjUMy8fSvy9d(sKgAmtNZ0?>tT>Ra|1H&oK)U|FLKT5@ z{f}X)1L^udd(;Ke^}lAA7D(6M*55mju0M`GBap7YZaq7Yu0KyaH;}HsFFQYwu0IgE zIFPQt@VF$9u0PRta3EcOV{JtsU4JBNRUln|H1ae^8)GmUE4K*bp5jArGa$)w%e6~bp5*0wSjc~zR8V&bp67>t$}p?#P^+n zbp6Qgy@7Q7%;kfDbp6oWqk(k&)YG~^x_)fs=|H-E?%?@Ay1sF|K9H{O{Jj=P*SBuo z3Z(13_xA$ndh>KcAYJc%eHuvD+ZP)H>3aRSDUhxg5Ss((dItDoAYBjP+XCsj58fVd z5*EpZ;$G=*a^2pLZ6|(cT4u;`y3f`XJ0!7_JlDt2B#CQo$qP6=`pI?^7&20SNj&Vo z==At7UfE=2X9!y@e?6X)Eh{jjMVZX8Bg@C>*`=qjVJWA|^MwIjL5|aFRf@3T9&>sf zt6_wNpJdAoj7$+fWw6U+N&}7fBrBe)HJDKlDqc@~cMmw24?Qx%&9=i(D9?zi1+izdD{V=b`BR)8`pV#Bd zmu)#_rPt#-PkpxKP$#pyH2Oq)JSphU*LuIToAl*7=2c~{!Vd_DWYQ`aBr zwZ8eq?VAsFGTxC!IvJlb8AF_mO~Q0C(sOJ9CG^^9v`$6ZV}CqY?e%llLs!1M!t3XO zhc5d+b>|#T~4xDsH*_TN8JP{41Sg9`Q;?Co|5qPI}4{ z?d0y(PL30#bF|S%@oA5Jbj8s!{W4MSY`pU_c~%p5kaiZIcFCq6UOCjs&^K0fHhSgS zGPw5cZ%26z9((rvFZ_l1%F~-pR7v8~UOVfRi&i?BFER;V*(8keTkCw(iK#kOl|Bk4 zI)6ABugINA9m`QZj8A*~s%vhO^&`{u?Drd<@kg`%r6MRh!1(Img@C^a=c?Sse8I8sI^ z>tya*-OIf;pP#w)n8TfnL*$tIFKN?L{&X`*dtlR<_1) zNdxaXw9aes?N!H3ak4gA3va{S@Z;rky`kf-ym+cNbpO3(`$OkHe9d^r=`%Xhar7@f zE*RhEcUcPh7r#?5p--7m{fiIED~HROh5p5V9~a+elZ-*pjU?jgu=f?b_p%5I6H6GtVMb&_MJy&|j5 z9p)&BZx;xr?2(u#FZ+W91cnAktDZ9M_TCe*sDt-J+)1zwUBAP`K%lIXHc85o?sB9_ zaz`1t_MFlwkeJxoXUAkG*q$j#OiWHpN*pPJr$*Wgl_o>QOmEntjjfY)DN)DS*}C*z zZSAs)b!kI&l}2vsbVQP6LUqjP-V>R(ZbM_nIkwyG@D7bQz*;4XKW|Ndc`tboEgU-8Ibjr=Pj|`Cmb1Y;?hsoQ_f6z!O<5S zCyQZ3n`}oXXJLvrB{DnC-#vDh7XnVTmXlU`IAAkoaf<{UR~oo zKfPM(gT}Q!YFw)xleNp3M?j7rF%LOEmCh$?SuA_tfHOslj<%iiLtyeH`b@_l!)Vb? z{TKAvd)^CEwCI@p7h*c!;i(+irJoutTV$s!yLc@&t97kos?jmsEq`&&>2+EeYt1Fh zl(eODJxt3y1p;va`6qVnwD&kC_Y$qT19zR>mpMHz(WfVPag0WNx=PMK>{WfLf7*jgrOKI9opYI7dB_ymLl<1^BR0>HvzwsviZqD} z{Faiev#0Z?bDN!=)7+S|U(4d0mgZSG%?&NHni>{2FIv(xYf01WoLSAw7cW_)U{=%Y zrOiz(F|X%?on!avO#;obqZeFy%Ec2F}+Qp5{2b3;d*ia|)GN*d}(w2sr zg5i^fv6^IN|1b9bKapTr@eg56kKaar8(h+$b_x*?Q^wFMm zB)R`#gHGCQe8qn;bXFg?Q--wJcQD=xWClp{>+Et zyY}>!g1;15n*VK`V{75xwbKILMJ!U+n)YMbJI;HuH223X`>t# zf&l5MtJk%xYwg;f3kEQY{(h!+?AKq~S>EDiT6F^H&^E=t@6aFr7@LkA>wmX&cWh1m zZ+ht}3w@X9lF`(}yY?obQ=9;;u_VG7PTMGSR<NTGrG~ zxo+1U0<(5lHT3l#Ez!T9QkHjD*|s8sWISVR1EK%85uN{OYQ2fibiG;84X2;qTw1GY zS@go9&vA7hn3U-zdmE?hYSqRbvZu{*2ljEh>%J#h7NG8f|El(A!)@L>=>&Fk2ikJ< zVzxBTcYEpJJs*1g2rXh*g@k#eq;)y(awse`+f9|?=Ioszn=QE z_%3euUA@kG1!Q!cgT1rkgN>PUa@^jsm@=~5-n|9;yZJPB zSY67o&ZDlkJ$gEh@wC*fGDBMazr9VkJ!D(z?GEfKbNp|1Avo#pO8&FiD$n(|b#D>c z)*4-4|JByp$LomI@;6<@P3`nwbn5Ls^LLfq+u$KG`?gc)5zpq;h1J}4oAj4Mma7|? zI21^C|7IKV1j~1`ebId3bRqXv&_60>+t+2|_Ff^zdKJYxcjHS9|?$=2dn>e>Jb! z{-*ptn^#@wdL;0+@~l7Ur0Z7JYe#pmY|#;af0!*#2Mlntb^qI2k*otjfBSTRKZUZV z2`0%tJZ9IB%vHueu8#k``WCrcUqZ^o)h~|hV7z@_AGgP!&)?c!lEh`nP36+s>V}eLq%2Pc&Dahd_!JA(S+y_MRm3H(!Qu_Qgua1oeWuD zS!TnP7ENfF>C`mnjlsJ4EhP)Ro72_JO_Lg1mNYfjHqB~oT2i}oW@}#sHN_2;Rdv!| zZAndCNpbX*iPbXR`pVk+>gptE0R*Vd$EY+UhEq zLcgb>G7PWiw3pNr)W%FXi*{1&_=dvz(o*TawrqMyw8@|5tZb4laBmo0*oC>V6Ixc; zP|t`**~I0Qwi%?TX3y%nDw*YqiiYZ{vdX#=o8^2PzCfzn$Q_d3u*92#;x^3-E95S2 zO{upUN-7H^7CTj?wG9QuemBFsp>@hiV`jXhZUW1Lk+CfOF10gnwKY_fRhCDW+SIbrvW9|cZz_wbDl1Eh)D}<9 z(xIMp>S?hlQCnYBBqB#!WA)_vlKPT{Qdv^bm#PbD%IfxvM)iJDLFJyd>RP+-R$FaV ztv3b5B7SrNhI!*>E^N5cJlTXAYO6|18`=z%ChMFo`&bu|T*wUf%~yq;@H3X1pi z=Bu!cur;*>(vi2SWdWPmjI*k?sG+v5N|tGf=xFQEUp8$ziP@f_Gi>%0RCr@SX(gcEQ%5 zI~CnS>E117>ntvrQYL$+!unc&Da*DIvs#+N#zgneO(TvW3NsOB&@(sWwNPXcOBV*OXM0c)M&} zh9zzF^7o~>C}bU%mHNxdpRnOEBlmVky3TaR=N$)a;@jxNzM!F?sHncCpvd-Y(dn5W zhrg)>GXHgDlS*Xed3}tGuKc2y5mw8ptF0*#y$Xuz%BJ{-qTw+|K(H{d2<#v&CZlJqMM_mQ_ZVNr8{w_bz%$BU&9h@lBz2Xl0qu6r`*+Y0+wzqhqTSnfn zHXX6~u(o0j^KHcW%Y$62HxH-uBo(JZ5;?eNB=*QGJbfl=60wrLsV3C&cWWakrviPd$^|;qdD(s+y9b64@t2 zSDx)5yz}t=mM)x?J9MbcLmOeE=I^llaUtdmxk9##RvVb6@dcA66-1{=mzJD>v5;i@ z^+wvdjpyZgu8gm&&ny}>DpNl$lAV{S9~j9UnLjjhKy%alrpA`0ftiCB%v!v3%&bMt zOPUTIykN)>0ZZmCT`*JXe)AVKE*UJJHW?#(gxLyY$o&>C8#cIQ@!;8c!-X_9&zd_% zK7O)nH;W_M*yx$yA8PcZ-dn9Dl~wh! zL-H?;yj3!6l)p;ao{UEiYH~hTP*_$`Hof(PI#+hdx{Qak*|E0n1$0x2>ey8_ zP$%c2dSH(Zz&i9Unp#(_Y;Q$!now9ES5mfv)p5#2fIqn-TDJl@{QIo!6^mX^=-ES= zTrl|O8QMXfoT`W!^C}iCTAb&X{69^Lx23ZYw>dSQBs~>YP5V=eq6#?{$kA2zRo=4k z_qS2=^K$cJ7J6Rp5SxqWZdn$8wA0pQrYCp}w&460a{Tn3$g1{%?9*a)W!^e(y^!1C z{M`16Z4V+trKhF_{aj5`bF<&4T-W`@#Q3{#*~WFM{Ik|Pxjyxp_*b>H^7*6Ib4@)C zwVtHO6|HTNdJ*rf3VC8kFQGjoC)wT;|H{%sxzVBgXVLZ2dWz(o>8?e`|L z7PD+(PA~Q3Q+8pV7~Y_**ND-J+u_!We_6*^{at#=r0SS!wIaQH5PJa8>5jeBoG?}H zVHB0i-qfF?HX9BbfS$KRmpU-^I{F{3*hpwmMW?P~?3=s!l#p741K|%l-2f zB3IY4&<@ZIBs#c1*Y%YJQ^bG0T8_RFvrr4_;^>m6w=le5Wu4DXjo9GLk zw0izpRjE4&?|_~6kFUzcq}#Gw*qK1B*K=(z)6~JJ?o3E+by#2~9L(X#TS)N=QM5ixi2~^iqO(>HKMp+e=a_o~E5RB4OL?=WwDU;LG=^{fzgM8Gl z^>#>}oM+1jyep3AWd|MT-YixzIHHsm6wAGv9gfPL1UlC7;<~p}`#<>^PCf$aeRfY5 zWb1X9UJrU}NUl{_X0mvri-R-p*saMMzQ|h#%$&~j4(9{~wR(dtdT&QI&SeVURq_4vn81arb(_}=!RH2wV_^apUGOX4y`}AdBzfyJ(4}uOF)~-)}G{M zL9Om^TZPv_{_?ySYuelpY;%epJ>}=x*S{uXDcB-yyUDYzyyYRMTmJHpE5DfKp+{4_ z{AsA2T2?2o#2lKrM9gcw?T{zCe5YluoPb5I!S#aB8-X0{y(fABsKCEY^InSCQso4_ zbqVPmWAC1gp5DlPiiYt8W&TY<@h&ML5$WOO^?WGME$IC`rnpIb$G>Bxej zGd-Dc_V;$GI*EGa#vrkm8FCA@tVniFa-io#x{jxw~Z-#ppi975!T2D`lOaA5rRafwyCH@67SBh=7 zeU+DM9L@y2>Cijd-V^_R{iK3v4Mml8c9e>}UF}WUpO3lzH68OAy{+eU*?QkQPwv9S zZc42uKsvMjM$l&G6TK6lJw_K}tZ&gvX_2gZ}+xeNnF;y@B**D^u+q z#bw=#w?(p<{q?&a{>|jpL)@QsGkIKHC61N;wTrKtOulzfX4_HB+{CW@Ht)sQY}Qwn zS5{5+mjahZdNW`9^{+aZy+XNlEpN$MLr#+)Uzxj*AgUY;Ff^vcKsdQa4Q z;@`K`r(6r=#oi9JUiFTAscaIlx1-u#op93Pbt(%tI$hp&CC8$=f*L)26!+zf;_tSv zn47jX#d-c6SMAon-eP{`tpGbI@lF_cH^3Wz%ud%t_0M9WH!fu>2uo*{H!b%j*5Ci@!2YEI6Hx7+Cd>W1=u+~mk-b9{6iq5_a}g>= zvj(H9Zw7IF$dd(Q*f{$0_SPX+i_0p7xiJ-76(1EA`F^_{*Qcl3Gy)Az>N zG4b9iEek6OD$8YaE|I%sJDm9Ftn4^=>x!wUlK1jt=OVXN3o2vo%IVr^dsoH3`0&rg z+Z-aRmM;0rH@m!fZ@mxezXQPpx1Nr*xdhSC%H~opv&%GVH~uAr_l(`Hf2*^hfeUCl zj@gS(s416~=x?xPB1G$5yQu|ojm{2thn9M4NDrL;a`W$&$|U6JoyX{)yj9~}w2iOP zYwsNvdz;Hd^~~Eo^m2wyn6#pTB3T2a4c>v@(b4mX2d;3`INMfZFK2v>V$MVK!pYyM z>D@$KT>g%PF?#!i+P`}b)Rr8R6+K7tFGIYwsW%i8O|cfX&nhYtMvyZ?@UOZE?W$j9ARq$DLf`h{g4`jy$jlzyu_ z9Nqqy(6RByxyQFVA$VfkDS^V2+~8U_A*EkoVzKvcwfAqqC~4WK-%fP`^1D5bJ96-( zY`KJ}bmG%OlR5+w+K1b94s;1bg6V;7f$o7Gfu4bkxIO{-g^NEuVo^Ki`#)j_2)Yfj*8ZdQYss2}PPAk1<)9y$=u*{n9+u@bJZ5;Em*O4r)E#ou4!LEAe8dj< z*d4O`vQhM*6ALRnx5^4kcHYLy?qc}1)IGOhmpOoDwUU3pl(kE>jNMJ7T1OZ8OoEKYt# z=Qyd_{tc}%+(xZ3oc_#(_r1rbWV>z~`})%t4{GTe)zo4&ru>QK>5^D@yaAya-g$?DTqKeejX#))dW&xn)XD^$z0 zcCjj5IC1jBL|IxzxdFy?U!cROQ(DJZEwox~ReyRwU!P@FeqYPW2UT0W}S-s5a z9aitN`iRvhtUhP;Wvg#mec$RQR=>3Roz<;Yf3vDT7NFCq|I3+H`H?8EcCxC!X05!p z)t#*FYE^zy#e02()iG9!td?1=vRZF-FRP7K=U81}wZ-aktA|@X+Uki`Pq%um)r+iN zVf8wzw^+T)>H}6Ev-*_P7p=Z-^*yVfSpCZC_g1%Am4lAA9O7lW@Rp<1&Q^O^m0u$A zULR;R*XjtXdsr>8T4A-;>U67(R_9t>WObRg_)yM=WPp-O1`8t3#~rX0^cT1glk6 zr&!&`>TIhASZ%ht-0CW;$67tb>e*J;SiQpP^;U1Qdau<-tUhV=1*@-Feb?&8R=>2m z+3L?$f4Az&{!o`wlGRRDyIak&I>2g<)!|mhSS_|%Znehho>pgAonv*O)umQfSUt+> z306L#l{Sk>c&E|-8D2eh`g+RU68Ktj@Q()aqeYkF|Q5)$^@hZuJJMcUpbOsvggDx?i&T zmer4}>W_Nq>pxiCZq=0omhu#<5v!S22U^XyI@)Tn)k#*TSZ%O6*Xn^*53zcb)sw8A zZS`WS*I2#P>U~z%T7AyyYgXU4`nlEbtZuU!(4Wwe`Ae|c+3FCh3^(8sLYkt@2_i{|v{4cA+7g=2)zuTnwc&lsWTto9q zR@=+DkLE5`E9Klo^IlfZ%JTDNR^RFC=P#^g?(FBmR`-(=3~k?H^~PQNe4o`VgZ%u5 z)sb={qQjS1JuJ`9Ct6)M#Lq8VO^_279X?{US}u+>?_>3x-TZuo)%SMy^OsipjP-Ml z)wulo7I}her~XO zUag<6vigCXaOwPfZMEMtKj&H9f4ZL!vU=;@etyX6Py6~g*x=XQ8~s{l^~hO%KGo{e zO@4meYRX(c_pn;Gzn>eeUNGO!*I3=K(9hpk-T6R253xGG#n1A4L*9JdzSOUeSlxDz zpWTD~y2l}YEw{RQg`ZEi`s`tTe$#5|5q|Dvb;?nGo@I5-(SE+p>c_|W`8%rvPVnM>{g`AnctoP`39?>Uh3!Xt?qJ#pGR0-e3hS9TD|)kKR<4D`*nWqaJ^p(Z}e-G)#GmV^VwEk zyw%U|TJ3y?pR=q^zst{atX_JLpKr4Ixt!?h^7+B)pa=at%4+k&em>mly^s3&39G-a z^>gCmel32&uam8w@RXm=wYvTpKfiCa>+^o@Yjy7z{XEa=F3+5e)YAVf3}+Yt)ItOUAEcJM_GMvi=Usd8n@NY9j#9I+0XS>Px-~q7g~KyF0gcc zeq^=#?|$xYb%xyc(bpGPy;^>mPV*gBH_0#gYW~G)zFeSb9&7br`E6g#M_YYZe&kp4 zb5`4>_&Lq$#8f{|wR)QT{;v*yk<~Zkhk!MIVzsCIBCzIxR%gnEpyowZukGRIyR3dI zKNhU7|7LY)rk@L}9@59p$69@~pPyf_8sFc~ovc<2^z)upZOEH1X_e{UW;ID}AZjkKI??LBR?oD$#_G#fKeO6RetcHj_pv&~YJ=5gs~1|m z(&{}{zqFbmKjNzW^tZa3)hes2t=?nxYpcEFhJd!KvU-HoTeZsazSHVMRv)watkoB- zzG?MctDjokX!U!mTdn?XH7?&DPuP*|O{POm=e#PXX8hShVdUS#z$tJhkU!;9DcZmaiOeaz|;R$sFEs?~R_ z%I?!^FS{A9%I?IgvYYT~vQ^p4y_{}UHd8Ol=IB-L{*Ej^(ZS0jtd6!?VztcbLaWVI z53zcf)#I(6Z1p^=Yph;l^#-eVSiQ&UBUT@``kd95tiEaWU8~;x8kzntEPrS92di?~ z;l!oL{YzU;QoQ+;%S*3*r1vYNy(sI%b&>sqaVNWF`GO^lGo>zR_Ul}p$(Ih6INACs zei_?2#$-g>W(2vfJ!|7}K=r4cmTVemXzR?@yNj z{mql-w9!6V_6RuYA`hM(DuCzu+RSkQC&)sJdF>#19y{I}&kQ)3GMvtba>gsC^m64Q5! zJg1HJaklg~M@MQ8Ub{hZY=4`iKV45cXh->@zX#;GwoxDSv0eUCfa(4G=lZX{rhiXb zWw z*^6>A<&ifcclgNM{E5bCgrqkqamHcgxzeoT0`S(Bcucpt{@>)9?c3tk9HXbKa zUzxC_Q{PJ`o>%eIHYf1Zwhfu1XY`$WL16o9RX;wuZ{e2AiVMmwl)igzxS;Gp8GCGx zXOy2H)A4tGo;dNSHho?g)93N!CwP4xUv|O{eXcBD`VW0Bo4Bw|pO;9V zw53m(EV&6EZX3B)ruWh%-m+Mt%VkwdnJ$l(9mX}YeEL6(Yi?QXL|Z1Qqi1xQyT+gX zX;nYg?_0E`aqprnM@}u;az*vDtcLOl6>GQkT(wrlA%Bm`-(vZ5)^2N;wszZw=z9Ic zTi&74y7Ib-^=0+CE)Qh=6#mpHSR>QAA#<|)yDoF+#J)1l^Zaq{UA|?*_-R=c6N<~T zbxi+u429)I6N}1<+l-;0yl`S+SF^ZhBP9=9dGZ^yFrjkPn%=T3LFzy7i~mpF0PMy&^U|K8yJ`*maO+`Z)WSA+*E zcAcs9fSGk0oJXA0uH%xsr)28J5r5hJCyjP4JbKmE+iwhA+wJkyN%EsB&gxaS-%$DM zl=8x>~--6?f1F8>&mHpZ@S~|ny)wY{-$ED#h>mg zdx%w+1_P@u+<((Wb-^ABHeZ*!J+9`oNy3kC+s8X=rql(VIe6^om$pv3{K+@2UAgP2 z2}4R(6m9RB0RJ}F(+uKb3adyJfT1izCjpSY@SGdvXPFFnS!m*39T5<0b; zXwc5pZ-~UT3*}2kL4AKeIH*&B3?7`6DgWelu9N5Psq#i0#TIntjij!kYoIq(5YVIt`7gcv1E@j#8eVDao-OMZ&tQbHL1yNBf6h*LuMd-X~G&Q*Ctx`wCAU!-e(rrb3>9eB1pJ^ieoE9ZaW@cHuX z>07=~c`w}?%hXj~NSD>Gt};D+t7YpdqtlmRxw^^{>1z7dRsK$2hG}(`p6MQ+URN2M zF6GR+%EWZvomE%4F5O)->MD38>jzveqE(V zmvlj0Ws&r=`lYTiEd9TEb(O`FpkM1Mv(u0MTU}+*bl~^8${XpzM$}gpOFz(k^_ADt zC4X6}+?y`qt5W5x^ssJjsd8@mKEEzimPqctDOF~s`{mnG<$!c&d{?Smo9>P8OO>V5 zPwa$(vP=sLuG?>A8pc58I-Pi(}v0s>8rn4LuHxtoo(Jw`7M2uEgCA{ zryp<2hDxV&7YuKx3{F4ZRt=SwbYSa-%CKZ~oAlq(S76(Q%Bl(2h=$6j|&P)QHq+Kpdyyi%^LoPO9>%avc#mwZmS@?N^6*UFU>(mnBdx$<0!ZmM-_Mrplk`uDiRba%1|=?rEybNk789O_k#l+e=z1%}LRvEtMJR;xB8d6zOMs zc}wN4^#87Csq{+U=ans$ThhHWtEIAkS|@a_eRs*Rp@N%4+G#4(L|toPK@>cB{-w-*Q5?%6aL|I;dOa;PlfxxLf7*^dn5{R#_)~ zIVN?hoSp8$L%LO3lHAGND*vS~@uA%+Tc+zgtXt*T^m918Tjk&6^N4PhyVLO_yH!p} zcjQssD(9!4*pzOS+36zInpqi}e%Q5VR$fov*^rr)SJK_O?##+_z1y`LIGTV1=xPm;d`4De238V7~Er zy21(hM*GC@pnT)BbT=NHZ|su3m!r~`wDHIEji=-rXQc1v=>OeFcf>LOyRk_6xKY0G zefk<4n{P}@cmHwu#=LYb$LAZf)15wjbh^2UmF~7Z={t1$HjnAi_SAD+GFa7BGLx7FHrti5S-*`XW zjYYn3P-2t*37~e3Bl54q`9|MVD*47W>Bnl!H||Vdhz|M2GUHqXkcU{NB z(v9?2z}B^YC;iBs8gg%LC>AgBKit?dq<_1jZ~Tkj3#GYyyJCr$z0zEvU9n`$o@owf zS1c8C!8BKFS1cWKfizcYS1c2=N16lM75!q)pXQ);#j-KGr@3;wV!4>z(p;ro(Ld&V zX)d2GYx&q+^G?^bLhLSirwbbpyK~;@%2teB%{yJ%O0nDWPS-Xtc5B}0;s(WT$va)$ z%CVdCPM5bz>`r;7>svK;$Fx^S*SA{iro7Yj4UXL*?{s~u$8O9!UEdn9D|x5uTQhb! z?{s}@#crQ>y1unz7kQ`a8xp%A?{t0Z#7>|39I`^XzI9{Qr#&ED-_Y1~d8g|e7CU|Y zTN{c#rP1l@-*#EzR4n$tf3v!6R{EcLv0i!g{J*y(WTPVgqn`g0vT+;@A)CYuA)Cew zA)CbvA)ChxAzQ=@AzQ`_A;V*akgZ~dkga19vQ2D4wvA25h}eW|7n_jnV-qqmHX);8 z6S6~WLUxQz$mrOF>=c`jonsTSOKd{M#3p2HY(mDxCS=#xgp7|($ZoL-**!KPd&DMW z&)78~8^Q#A>`ngA!K6A5Hcxd2stEX2$>v{kV9h=a#(Ca4v$U95wQt5GBzPc#U^A*Y(kEX zO~^5^37Hz3kYi&La$Iaej*m^q39$(|F*YG5#U|wB*o2%Cn~+mu6LMN?LQaoO$h6os zA^VgrPhbDGQ`1AUV&9sOKeCYNa&b&TE{RRZrLhUQEH)vR$0p>8*o0gen~+(t3ArjZAy>yH ztYjfeQZK*h)u|iu?d+Sn~%jBXVru(kRBQpca*c7EaaZz@${hSe?sn!qaozJm?7l;m?7kWm?7lBm?7k$ zm?7lhm?7kmm?7lRm?7k`n1nnYn~*1B6Y^wiLY|6E$kVY2c_ua?&&DR?x!8m}ADfUD zViWRWY(id&O~}i!33(+pA+N?JWKL{CUW-l0>#+%WBQ_y##wO&g*o3?tyC&qW(iiFL z-!?lvh%N4}37MH5-WTtbvz#pCgChSU;{Ox!VH^!1AH@tIAIA(KpTrCypT-O!pT!Iz zpT`U#U&IU{U&ag}U&SP3Zfrunj!nonu?hJ$HX+}|Cgl6rg!~YjkRM|c@>6U=evVDZ zFR=-k7n_h@V-xaQY(jpIO~@ay3HdWNA%DdtbfMjZPC2A2 z?JjgoAwR>JUueo9U1<-YLk{Um7Z4hANLRX`P{|=(X-}b?L%PylLi-%jl`bR{IixG? zEi~kiu5@9clta4GMTGhk@^hU$Q?!)xp=fD46fI+iqJDNLTGkFl%h{o*za5H}w?okib|@NPQ?#N$ z(MkeE0|kl(2^6g?P_&9b(W(MPs|geh7ARU>plA(&qBRAI))FXMTcBu&K+!q^Me7O_ z4HYOFCQ!7VK+*aFMH>h;MSbf^XD1-lmGg^CON64!)2k}QhIQraD=XTxuDCP3O!hxT zn>infHn&637IrAw(hfz#?NGFp9g4QLL(w*NDB9KzMI&sAwi77YUZ7~CK+!0Hq8$W^ zb`&TYEl{+RK+(N_GK+&E8MSBSp?JZEW zk5E&zab4-%1f+UNdbO_DBoytE9^w@H)|IobtmweH;-BpfP;`hLiYD8k=ukTp9cG83!)=O=5GXoQpy()pqA3DJM++1kBTzI|py*hEqT>XL zju$98L7?bFfufTHicS_NIz^!9RDq(?1d2`q?8H-^{9W z@&o4sLea8$oK;uOzOtfo>xy;K`w{2BLwm{KM z0!23q6x||FbgMwoZ30EN3l!ZUP;{q2(Op7K(b;vS-4c-MUHNg*Iicvztmy8#a`u%K z-CtLnnBJ%PpP~nx4@D2!q39ty6g_N*qDSmd^r#(*9P50s3|JyORFXz)dA@Z@uGcw z?V0`)>GKA~67}WmD=S*2z8JYgDC*~YC|cGIMa$WtsJ|VGmbXLE3U(+OV27d=?NGFm z9f}6p6b%w6T3MiI6@j8v1&US^C>ktKw7Nji8UjUY3KXp+P_(u{(GY>6bp(pm6(|}i zP&7=SXgz_V^#zJH5GdMEplBn3qK$=`qNVCfMVw3uE_LUWF zQD0oTR4Cfg`A{_64nzRV+D%F2^8%rP&8hkXg7hP-35yF5GdMHplC0FqP+!*_7N!B zSDOHU*q)l1U{g^JBXQTo?o(-XG(a`u%K9b8|0u}mnM=zJ)eWQU?d z>`*k>4n>FBq3AF>6di7dq9g23bfg`MjPsE_ zB}J#_R~-)uMg8(GOy|^>v#+e^g8HK0a-nFZ^P%WMI}}}HhoXz^P;`kMiY~Q7(Pefh zy4(&$SJPuTDAl2^alNrVNp(y`_Z^eD} z`?T$9g3c?L(!9VD0<2cMNiwI=oy=$X9bF$ z6DWFKpy&mGq89~I~09yQ}lyC(T@T}KM555EKu}|K+!yb zqF)7yeiJDAU7+X>fucVJivAKP`dgsrAAzEO1&aO?C~8-Vr|lHg2^7@}6qN*u8U%_8 zp{D4Q`qKLeNOkY@4oC56D4Lr``%*dk%8ELaivLy$MNQ6!qKSTwaW;+zM*rBM^ z4n=KtD5~0_sIwi4y4VzT6)2idps1TbQFno&`2~u42oxxQBQ%QUIIl62^94f zC|X#cXc2*;MFoob2ox`6s>57qLu7WG|&!3gX~bWvK@+6u_;N1$k3fuf-TMZ*M&))OdNU!Z6Mfuaos ziZ&7`+E}1y6M>>l1&THkYKr=mN_!+A)nWOUpJhW)zfu~Tm&(~!RAIC<4jw6*i0 zXd62eZEJ_35q2or&JIP}+o5Qr9g0TTp=bv?6zynJG+Ll&CxN1!1&VeNC>kSBG*+N! zoIug80!8Bmigpty+FhV%4}qdR1&a0(DB4?~Xdi*1eFcj46DZnWpy&XBq5}nrCI~e} zTb4>UB_P!m^5df6p=h=I668Upa`u%K9a1V@9vq4$J0FS;wL{Tib|^aB4n;@Uq3B3E z6dh%UqA7MLI@%6J$Ji826(~AZpy)V(qT>aMP7o+MQK0A~fufTIicS$II#rIzyo7Oo5`a1d3(|6rC+lbdEsLxdKJ!2{lC%OQl~EkZNmwKs_lGZJHIG zUn*x`Sl3`u|v_bb|`wz4n@z~6ulr&^rAq~O9DkN3lzN~Q1q%m z(Hw!I*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>WiryC}`aq!QLxG}?1d2WuDEdUG zDSEh6IywQVZj?VH`$#BSDSbMv__S2czOte(OU32ugrcvU4@GnBQ1rDOioUT!(YJOe z`pynT-`k<+2Rjt~XosSoY>IvsDEdX9Xr4gPuL4EC2^9S~|!1d0lQqV@tsWr3oKP*e1Isq|C=QoSjEzUYfk zbW(aRzi4bIXJ1)Sr-tIIp`obR`B2nihoV+H6t&r*sA`9z&UPs3Vuzxxb|{+94n^H; zinYHBDo4@-)sr9YWmbZn?S(?37|xzuGF%Gp;|v_g8a zzkVnh;Cv`r(GEo`*`a8l9f}6op=f106s=;1qE+osw3;1?2HO;^E>N_FK+&24MQaHZ ztu0VAM4)ILfueNiV}YVg1d28lDB4V*Xmf$0 zEd+|T6l#k4Hibgmeing;u(e`#I8fk~3 zQFbWW!45?`+M#H)9g23cL($GQMY{+TjS(msD^N5}plDZtqVWPny9pHSE>N_GK+&E8 zMSBSp?JZEWk3iAB0!8}?6zwlibbvt7fdWMn1d0w4C^}f6XrfS4v~@%2`~;-BPkunX zO(?oLE1J|$&c3pu!y1ZvHx5OIJ0FUUutU+2b|^Z^4n zP;{B|q3Ciu6kTD5qATrCG|LV}SJ|QHYC9BNV~3(^?ND@`P0{rNMK=f(-6&8rTcGGB zfufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>py)nYdR3rkjzH0C0!6P26ulu(^rk@3TLMLI z3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keIiiwsX)(>=zBX9{a}ZpAMH@|lO2kFwnNb` zb|{)>Q}nAq(Qg7pzY7%oAyD+EK+#_UMSlwv{UcEHuRzg%0!8VMWnYl);D$Pi>I91F z1&T@nMGXQ)g+NhzfugcNQAMDrQJ|=UKv9!WQ}k6s>6QefIwrqdJvS6Rlb`8#EXvte zR@7P)uWlWR+MEwXRXY@QwnI@DI}~-bL(zP8DC%a1qV9Gmn%@pZJ#2~=5GYzups1%n zQ7?g_g#?Ov3luFZP_&3Z(V_xHeFTaY6DV3-ps24v(GmhhO9~V%B~Y}qK+!S+Mg0Vd zmK7*kPN1m2P*c=glzvY@sypQmrnMBcXZpY87qXWx%Gp;|v{F&bKOz(jbUqXfvP03z zb|_lK4n?clp=dQb6b-gR(du?6TEh-SYuXg8B~Y}sK+zC^qICp{))gokDo`{`plCgT zqV)xeHV`PXt+SpRsuy^3pGUpiqaYh zNcGM9x$6}}(YXBL(Kban`^t*8FN)FIhoX_rhoVt-DB8geMLXJ|XtW)QcCtg!&UPr; z#STSd>`*k;rf8f%(XIkT;{}R#6DZnUplA<)qCEwQ_7W)CTcBtkfuel{iuMyI+FzjP z0D+B6fBxL{cA@Ct{I^#fT9mV| ztmw$1xN=k|I?DM_G{p`@N86$37&{bAwL{Udb|^Z|4n@b?q38rV6rE^Obdo^P$pS^E z2o#+vP;{C=(dhz3(*%m93lyCpP;{n1(OCjTGX#px7AQJLpy*tIqVoib&KD@UK%i)* zK+%N)MHdMaT`bfT9bS~4NkFPA=FeRp5sG@WrEy77&c3puD~jUl9YfKT&WEB|b||{a z4nhqjW$KI1&VGGD7smo=oW#ZTLp@46DYb}py&>P zqB{kO?h+`vTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6KaYsD@v`S zlcJ;YFF%)uqJjAxkjIO1_LUVqT@=gj9EzTCJ`_D`hoa}~Q1rYVie9io(TjE{ddUt& zFWaH$6+0BYYEv{vpy)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J%OV41&TfpDEd&K z=p%umj|GZ85h(gppy)G!qR$12z7Qz-QlRK7p{D4`qO?r{QoSd?(D+m+O8-(udcsze zv#+e^yP}vlCKP?|d?@W`egZ|y3KT6TP}EeC=|`jFF|hC zzMOq!MLV=FHrOK+?dW_c8f}N7o$OGwvmJ_du|v@qI~0wzL(w=p6zytN_GK+&E8MSBSp?JZEWk3iAB0!8}?6zwlibbvt7fdWMn1d0w4C^}f6Xre&TB!Qws z1d1jL6dfv1beKTV;X+N($o8du5|HZ0`F*rep=f0O$l4L@%h^{}baeaT^u0pSG0umg zsdgwj)(%C-*`eroI~1K@hoTehP;`UB@`W&e_^`3eL4Heimqy3ytYp$y4v|rbd4Q~uC+tab#^Ga-VQ}K z*rDh~I~2{fL(xrkD7x9E=oW#ZTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCA zx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yKq9=u#qAS~%{!BosCl(3LtWeaP zKWy|=`*QY`6+PF!SYZE9^t|(-=mk3zy=aG`m+VmVvK@+Eu|v_Tb|{)-hoaZ)Q1rS@ z(HjCqZweH>B~bLXK+!t_Mehm}y(dugzCh6j0!1GR6n!L6^szwECjv#E3KV@NQ1rP# z(H8C>kJ8w4y-KN&-a#g_@!+<eN3 z?U{b}{5#s9^lzLdUs=&=<>K3kp=hx4p=fnG6s=*0qBZSMw3Z!;*0w{@5IYpDV~3)3 z?NBt-rf8Tz(RukAZZAW*cSK+#45MH>qgZ6Z*#sX)ju0q1 zQlRK4p{8iZa%n^YQhh4Fk2X3K-Q7ElDdlqZl@%RZE)F>?6dmV$C_3H_MJL#y=tMgd zon(iilkHG+iXDnhwL{Tqb|^aCrf8Z#(R6{LGX#px6ev1NplF6b(b)n;=Li&?D^PTv zK+*XEMHdJZ%@ioQP@w1{fuf5AiY^f-x>TU(GJ&GY1&Xc^D7sRpDLSTHx+npuuAg5b zni`7M%CB9|DwngbtmxWu@!%1m=sM>^(e-vHy1@=bH`<|SwjGLYvP03$b||{V4n?=x zq3AZ7qT2um+K7pe91&SUJD0)z!=plikhXslr5h!|8 zpy)AyqQ?b_o)9Q{QlRK5fug4cik=Z_imon~K21QXzvaKb=$cUUetx~^*>XAi%8Fhr z7sZrN^pf+T=w&+;y<&%=SM5+V#|}lW*`erlI~2WPhoU#_Q1q5f(c1z=?+6sVD^T>F zK+*dGMIQ(heJD`$kwDSM0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2R(OiL|uLX*}5h(gr zpy)e+qVI*8qUXz{r4o?pUY!%17edj#`J?|Kv5x3)Lx*d zEKpPtC~6ca>L5_mBv8~*ps15TQL{i%i$GDUKvA1OQB|O*vp`W7p{D4ka%sN=q}s20 zg7b4I`X(#tS}A8=S<(EJV*0V6sE6~RXaPGEEog_Lo^~keWrw1L>`>I(4n+&wp=c31 z6fJ5~)JLFbF@d7R1&aC#6fGf8w4^}MQUXOw3luFQP}EPLXjy@x6$Oe`5-1udP&7!OXk~$-RfL+NZk5s<2}pI>J_%0uO6{5cu>2>9R;`q?udHZ| zO7X_=p=eF#L(y7xC|cVNMMLaRw2mE$*0n>?P&*V2vqRB(b|_lkrf36!q74O#HWDb> zSfFSVfuccU{hfeRpX{38tR9Ni%wu$=oPA|QV=6_@lS0v0=R?srI~46|hobRz zDB8^qMZ4RfXb(FS?P-Uiz3fo5w@uML0!8}@6zwNaw7)>n0Rlw_3KUHcC^|@>=wN}O zi2_BF1d0w3D4Hx#bf`elVFE>m3ltq8P;{g~(NO|LQv`~R7AQJKs43dHQW}zgRB!E( z;Or8LKFo@yR?68|R&+w87;{P}I??%1bdnv4PPRkQDRwA2)ec3c*`erkI}}Z`L(z0Q z6rEvHbf!SjSpr2f1d7fUC^|===v;xK^8|{{7bv~3yI<8VWApxoG*ek&~J`{bHA0%B)(p$qq#~+o9+dI~3h&hoal;P;|Q;iteyO(VaF$cL@~TEl_liK+(Md zMfV95-7iq|fI!iM0!0rA6g@0Z^oT&wqXI>b2^2jpQ1paA(USs2PYDz~El~7~K+&@T zMb8NoJulQ0T~{f+kbqQ2RuY`+L(!c4$BJI4l(Vm_=#@(G{j^Z@s`H^}jvb0#vqRDA zb|`wo4n=R;q3A6;6uoVSqIc|2^sY_Odjdu83lx1IQ1qcd(MJMB9}5(HB2e_HK+$Ic zMV|{4eIZcvr9jbF0!4ELioO;o`bMDWTY;kQ1d6^FDEdL5=tqH~pM;vCmnx+$)03i$ z^5?E!4n^(r3)w$c%Gp;|^joD^>C8~{yYr#w4?7h7X@{b}>`?T#9g6<3L(#u>DEiM1 zMeQ2nd3z|Tvni?RDp=eP%6!oz~(PDNeTHL0nuRzff0!2#-6fGrC zw6s9cG6F^Y1d5gwC|XXSsJ}qb@&ZLG2owzvC|XgVXeEK7fdWN?1d3J`C|X6JXjOrt z)dY$L3pGVO8cUZXAl3QuU$?(NW9^y#l(sZhZ!BkDS<%{!#lz=>q9M+QqIK+0w5}bB zhT5TMm>r7NvqRDPb|~7w4n-TqV2!W#Q1d6s7C>kkHG)kao2Z5p;1&T%s6zwEXw6joCv}R-J^8}F2-_ee5EN5R? z(aDX)CNo3PDb9zYQ|(Z6njMNxw?ol1I}}Z~L(v&_C_2*)MQ7QeXogME*#br92o#+w zP;{O^(fI;J7YG#16ezk-py(ojqKgHJE)giYRG{cGfuhR=imnhSx>BHMmO#-}0!3E~ z6kQ`wbge+qbwW+iiH)TL5|HZ9{D+553Pnrj_w=uCEN5R?(M^rTnHPnko1G6ux7eZR zRy!2kW{0BN?ND@w9g6O>L(yG!D7xDYMfcbg-78RZpFq+50!0r96g?`*i{D|)%HoPA|QuQe8LT@s33cRm!oVTYnO?NIcV9g5zzL(w~SD0g-TdZ-=6i9f}%kiVA_E z_5wv^fuf2)QKLXn2Z5p{fufEAMV$nSngxnl1d3V(irNHXi+;9^|3?IVsWdw@)2^1|WP_&#tQGbD= zplA(&qBVt@qMjW} zCnX@&r8Asf9cs_?Kh0yU4(04CD_XZhaots+XsGj{XqX*}*0V#=`gSPVzz#(l+M#G8 zI}~kfhoVjFP_(H{(Pjcgn+p_eAyBlXK+$l4qOAmqwiYPbMxbb0fua!tMcWA!Z7)zX zQlMy*K+z5YMLP-!+`-*C9g6O=L(%;DK+*F8MK1^xy(m!hl0ebR0!6O~6um0c6y4mRbXfvYy&^xkzaQVmkCJq@%+a=-Uvktm(%#8Lpl4(ivHLF0HfI!iL0!2NA znxeltl$K3Es{IyCaQ+TO*W?$EdNq}^udHa1red?(L(!tnhoU}qC|b-8MT^^^sIMK0 zmas$7l6ELs$__kQv6!mT@O-MkhXZB8T7H+CN z(=Rfqb(+fAS5~xMQ!(StP_(}Dp=bj;6m4jSqK)iOw6PtEHnBs|rgkXW%nn7H+o5O+ zo1!fRiiQgmZ6#2&wLsA}0!7;j6paul+D@Qodx4^n0!5<)igpkv+EJirv_R2L0!2Fu z6zw8VG)ACktU%E?fudanipC2yMMIlP_aq?I;rZRzVWH^HtZ28Ua`u%K?bTGgb9X4( z+xbwmj~$BkwL{T$D0*6;=ox{cX9bF$6DWFKpy&mGq89~< zUJ@vJS)k|@fudIhislFuy(Uofx=>SeTT|(j1f=?F{^PK>hoXn_FHCPVm9wv`=$)qG zhKEAYyUvHA_v}#gz8#7_utU*@b}0JD4n-f^q39Dk6n$!kqR(uKJ{KtZLZIkNfugSj zislLweJxP*jX=@20!7~m6n!sH^n*arj{-$M2^9S-Q1pvH(L8~oUj>SO6Day!py&^Q zqCW+S{t{}6-fAknl7Lia<(I494n@OzrSW%DIs3|r+I1{`ek2stb&O~7p{U*tMI}2F zHQ1r3utQOMI~0}eP*kx)QKKD-I@lC72^4h{DC#6o)GSccB2d&SP}C++R23-dEKt-% zps1@r(R>0$-2{rd3lz;SP}D=9XaRwu1qF(F3KaDcC|XFMsJBp4^lwwC`=d$Gg8B8L z|3XnIlUlfAIs3|r7VB87@^~m(-1$({*A7KX*r8}iI}|NthoYtJP_&F4iu&21XjwZH zEoW2IU!Z7tfua=ziUtT2tte2ml0eZwfucbIMJo#wts+pgszA|d0!4!bidGjWT0@{{ zO@X4d1d7%cC>kPAw2na0x&lQ*g_@#8JC=4#K&t!Y&t3QFSbL_wQGRQ7SjTeql@)E+ zu{iR{P_&Wrp=e_}6m4RMqD}2kw3!`>Hn&637IrAw(hfz#?NGFpP0`i@McW7zZ7WbT zLZE0nfuijNibe_)jS?u@L7-?yfuhj@MLP);?JQ8Vi$KvBfugYjMdJjDb`>ZZFHp3b zK+*03MSBP}MeBDgU6FuPPt1Sc^#-Bn&irR%_v~2CzOtfyI~I>W9g6mIJ{0Y5hoS@Q zP;{UjiYC~h=pZ{39c+i9iFPQOWQU?dY>Fle6dfv1beKTV;Q~cR2oxPDP;`_)(G-EA zqXmkN5h$7}P;{(7(QyJr#|splAW(FoK+#D8MJEdsogz?lszA|c0!60_HAQ=OEX_?o zs(a?oUGEc$*2*s)P3u_BzOtgTIu=dOg`yeGhoZCXP;`zRiq5q|(Rp?#I^PaO7uca_ zrX7kdv_sKFHboZ;6kQ@vbg4kmWdcQ)3lv=;P;{k0(JX0!6n8HAQE1EcH)7s#EjluFnibr{}k3Z|_*n zzOtgbI~H5K5Q^?`J`~++hobxJP;|c?iXN~-(SvpK+)p@ zMNbG6Jtpy)M$ zqSpnA-Vi8yQ=sTAp{D50j-`VWkm|hr6470u=!Onyyxp;!ePu=OcP!3%DHMI+d?@)Bm~^lw)*bo&3F=@)h=YHx?4vK@*l zb|`AJLs17i6gAnQsG}WMBq)pFmMJfuimL zMe_?3^$;jpK%i(rfuf!QMZE-y77{4xEl{+uK+z%sMT-hGMRlD@^{*yHWAaC>>pRt+ zqph6(CG%Gp;|v_z+3(bq!JlFrAkMN8SCXlXkXEn|nGes(BY)(%C>*`cVv9g3E> zL(vL0MFRwiRum{&NuX$;K+zz9qLl@TRuL##RiJ1!fug|zMXL)Gtszjfra;kJ0!3>J z6b%t5T1TL0U4f#Z0!70Fiq;b-T3@IsTD((f{RE_XLVj}JHxxab6>ZR|oPA|Qn{+C6 zeU=2L%nn7H+o5O+I}~kchoa$jDB8*nMO)jUXd62eZEI6BLZE0nfuijNibe_) zjS?u@L7-?yfuhj@MLP);?JQ8Vi$KvBfugYjMdJjDb`>ZZFHp3bK+*03MSBPo?I}>S zmq5|pLQT;|ol2)AAk|0m=dL#nMRW6mq`-b%%ijEX0I!d5uia^oP0!7CN6ipQDudL{tPQ|=;LeaU-hobZBP;|Z>iY~B2(M&rOU1*1*i|kNzu^oyo zu|v_NHbs{S6kRS*bcI0Cl>$Yx1d6T_D7spp=o*2dYXyp~6DYb~py&pHq8kN@W(ySE zBv5p-K+!D%MYjqR-6l|UyFk$$0!4QUHAOQzm3q9J6gA{GV9yRk-(*F1bt-3HS`?T$9g3c?DSA?%=qZ7srv-|h z5h!|Apy)Y)qUQyQUJxjHQK0B0fuffMie3>YdR3rkjzH0C0!6P26ulu(^rk@3TLMLI z3lzO0Q1q@)Q*=+K(oP9T_4aNF&b^`Njr?}Vd!5SJS61{at#STS{b|~s#hoUAs6m_&iQ71bT zHQS-6#STTSHbrd$MOA^K&H_bU1d6%}6wN14)J>qMyFk(W0!2LpiWU$kT2P>kbEw4OlG z`T|882o!B7P_&UyQ?z7rX@vx&Iy=90wp1wEI=>yVadSEQ%8E8`E{1;*inee*6m4mT zqTzNZ+R6?^Tic;%8#@$jYlor{b|~7;4n^DB6pa)p8YNJ)gFw-a0!5<*igpqx+F77z z7lEQN0!3p5ipB{P?J7_-UZ7| zqy(he+$+J^EEEmO?||&zT+Y6-qJx@?^S%m22Rk2%CfcEBk{yZ;u|v^hI}{yihoZym zP;|H*ijJ^D(UCSqM+p>75hyxZpy(KZqNxH!#|ji3Cs1^}K+y>TMJEarog`3nvOv)( z0!60^6rCnebh<#%G=ZY&0!3#C6rCwhbe2HT456mzz~<5e2}rdm|0Xse6s`WhCv45- z>?rixo^Py;_9f~frL(xTcD7x4VMVHv2=u$frU1o=(%k5Bfg-y|w0!6a~ zimnnUx>}&<8iAr~1&Xc{D7s#t=mvqJ8wHAH3l!ZXP;|3E(JcZ+w+a;9CQx*{K+zon zMRy7m-6c?Tw?NT7LQT=R&83EKlAUdr#TDLxpdz;JIS61|3bFtWWq39v!L(#)_ zD0;*WMUUE{=rKDKJ#L4hC+tx4q#cT$vP03+Hbu_}6g?|Y^qfG^^8!UL2o$|2Q1p^O z(aQowuLu;qDo`{>py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J%OV41&TfpYKrb} zE^U~ARKLp~l6@c)ZC^^`!{&1Kl@)#3TLpOLkU&vyfue;4iWU(lT2!E@k3i94 z0!51p6!jG-T0)>`Nuj2w+){cy0jb`QUudkf)Sl^&&7YWEs->KLWkt)j6uvP028I}{DFL($4MMXLxDttwEonn2NDfuhv~iq;S) zT2r8CErFu71&W3U6s;prw5~wWP=TUh0!8Zy6s<2%w1Gg;h5|(!2^4KCP_&6a(WXL8 z(K0Qi1?MG2y|SWyp=k5`=z6o3a`u%K4R0w{|1A`4<$NgG+73nA*r8}!I~0wuL(z72 zDB9i*MI-G{G|CP|JJ=NMC{Q$7plBz7qMZebb`dBVBTzI}plF;x(XIkT;{}R#6DZnU zplA<)qCEwQ_7W)CTcBtkfuel{iuMyI+FzjP0D+nn2NXfub`6ip~@$ zI!mBvhCtET0!8Nt6rC&76dl}Bx;g==j?BM_O$LubK+&B7MRy4l-7Qdbk3iAA0!8-;6x}b> z6kX6#`Yr*fu8?LiGZf9uzr8)sQqI1zqDNYamVZOhqt1t-$Lvt_xE+d~utU+4b|`wv z4n80!6P06umA`^oBsu zn*v2|2^768Q1p&K(Ypdg?+FyWFHrP>K+%T+MIQ+ieJs=zJ=9WKF#)N*nBPZxI25g# zKN<2#OF8?>ioR$mwr-cdgY>!UFP#rXU)iB(t{sZLwnNc3b}0JR4n^PDq3C-%6#Za_ zq91LFeiA79S)k|_fueZ=MZXFZ{U%WKyFk$&0!4oc6#XSo^tV9KKLSPn3Kab(P}Ht9 zp0-m|Cs0%`P*f5qY7i(Y1d7@V6qSXVqR(1NlM|5Y+dUGT&qL88`M0-9YdQPMiaNFy z7u1KMPR@s-W;+zM*rBM^4n=KtD5~0_sIwi4y4azps~w8wvnlE(P}E(ZXnujB9s)%R z2ox5-3_) zplBJPrl><}>7fLqx@&$Y)YMvgrav{mHQTSXoPA|Q%eNLEHH4xSoDW3<>`=6#9g0@6 zL(xDx6b-UN(aLrxTEz}UtJ8W-DH@aC zN9!Mo#^!fpw`?tEUs=&MtwrB*DB9NfP&C30Mcdh-XnQ*pjkH72C_5DGV27d|?NBt@ z4n;fJ6zwcfw2MH|7=fa(0!8Bligpz!8ZS_^n?TX-0!4cW6zwTcw3k59-U3DY2o&ur zP_&;w(f$HO2M81$C{Q#(py(ihqJxE+qODp>8z&&uS^0gmtwYhD)ifrymb0&{=+M?; z@5WGcnDe3Na61$oVTYn4?ND@-9g3#dq3CEk6dhxSqN#Q$I@YG>IDw+$1&U4(C^}J~ z=p=!nlLd-S5hyxUpy)J#qSFP6rU?{H7brSIpy*72qO$~wW(X9WEl_lhK+(AZMdt|= zoi9*yflyO)NNeeg1f=?C?*wOZD7qrQcr>%MoPA|Qm$VkQHie=~oexEq*`eriI}}}E zhoUR(P&CU9MOWFO=xRF@U1Nu$Yi)|I6DYb~py&pHq8kN@W(ySEBv5p-K+!D%MYjqR z-6l|UyFk$$0!4QU6x}6Ibhkj!Jpx7d3KZQZP;|dQ(E|cS4+<1LB-9jL)LMEo0jX}5 z-^RZ<6phb+AmriJa`u%KJ>FXU(J2%?;e051(hfyW*`erZI}|-*hoWcgQ1qM~ik`Pa z(F=AcdeNrnC4r)s1&Uq~D0)?(XpTV9YXU{D3lzN}Q1qri(OUvVZwnN?BT)3NK+$^w zMehp~eIQWup+M0`0!1GS6n!F4^r=A6XF^TUqphW0%}LQe`6Z&qLea_j-Pq4t%h^{} zG`F=_vo#cb?R+Tu#tuc_+M(z>I~09yhoT?sQ1qi6ihi;~(a&}$`o*Sbo?THLiE_NvDYKNlv>`>Ir4n^JVP&B_yQ4fKl1q6x~6e#K`P}EDHXd!{3-U3An3luFP zP_(E(Q6GV##RQ5L7bxm0P_%?V(UJm1O9>P$El{+KKv6$|qGbh&mJ@1m&oqCs{jTG#7BlDB{0ikHQ{M*~sZRPAM zE84EDXzLb=ws$@hjkH72C_5DGV27d|?NBt@4n;fJp=f726zyV%qA@l_V+D%F2^8%r zP&8hkXg7hP-35yF5GdMHplC0FqP+!*_7N!BSD?iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT z6Dayzpy&&MqA!J-q9@u)m0n5Ft_vhMPllpX^Pg(`s;!)TWkuh%6-)LGMc+9eioUl) z(GPYg`q2(WKiQ$^XFC-AVuzx6b}0JQ4n@D&6#Xtx^oKyvp8`dH2^9S;Q1p*L(Z2#k z{|OYetH#rIis}T4>II5Q0!0l1MTJ07dx4^|Kv6}Ys8OJ(gFsP}Kv745qE13h(bsLI zO%ssn^KA*vH=$^DemkVOTF$<*qH49+cac!k+4)e^#STSX?NBtI9g4cyp{TnZisrXN zQ4c#5EntVD1#OCY3KaDcC|XFMsJB4T!U9E$2ox&plDfvqU8jN`U?~-FHp3CP*c=eEuEEsRFBC|%i5~7XZjZg+S4k0!70G zinbCc+FGD!8-b#2g_@$3s-?FRkm{WL*4e;Nbp8LHuvN?1S5`EtTKu(mDB8jKP_&~R zibmU^XeT=q?QDmlUF=Xa#tube?NBt%4n@1#6pa@s+D)KncY&fk1d8?)DB4S)Xm5d{ zeFTd36)4(IplE-Aq5}kq4iqSwAW(FWK+(YhMH2;zCJ7WBB2YA0py*J6qQiumqV21t z-hGpzN%@0mBSXfud;wMbia}&JZX%Q=sT9fub1#MP~~Xog+|m zu0YXw0!8Nw6kQ-tG*h7HLV==-1d1*eD7r+T=u)Ak=*Vhm*94?`MViG?q3G58S7KfE zf9$bIzG9v3|ps zb%Yh=^lWxdKidk9lwP+LtdyUljSjAmyCi|&4RRrD8GKecRc(V`OLNvf*!Kv_iVrRn zD7yq7k`GWO1pky?RKA-nZnvZaI~-|Q1A~+LSk}jlx$hq!TMCo$_qY{W?2QnzXw@XNib)qWt9id9d23UgF8l8*5qLDc*~j+JR!rf zrUh@vvaH(RH#wFyCzzaPSqp-TMq5@xa7%$@Ee_hnmbEN6YK&zq51vuo@L!1?7Yyj9u8L3Th?R2TNYW?*5G$1Th_K<+EUAUA-H6jWxW!7@-)lZ z9&}b%*3Mx58J6{K@PgHr^h3pdCCu;VYfMvj0T|K3J91a^G)8{`<+@ijNeL9pXD z-6BW9j^BTq90ogn$YwbXcD(sF`(Adu`8)DHcD(sN>3(*+`9t6oJKp@G>p(l+{3Yj5 zJKp@K;s`t5{3%|#9dG{CEZdGZe@m5T$D98ZDzM|tAH$T`@#ddB%I$db*9_zBc=Ox( zlkIr(v-;OsQ*?riKH=ntD%#Jr7n%io}n@>G$ zv*XRjR$j2<&F2nYvE$8+`4AKwb$U@| zMeMW|ak6Y4@;6|Xy`eV6wmRP;XN;XTY>2!g>$s0Df6GwV9@KiBQC()W7BN`GLL-K# zSR<#RJ+!p|C##(+o3@APJHc)uhO6k(>>AkG})Lb_)AH))y*!6X}4wh-pz}<*<)hbo%!^hFJ-ATrrq*yU;c7wH@hsR z-J0!RUB1lfzEV;xl2ly?B6lbd6Fe>X>`<**~GW=V!l%Z1mjYbp6T zEyw=xa;;?Nw7d76M@y~lJIPHbadR8!B{jL33!^DtEx83wxc3ORcppFX>rbb;*_~hW zP?=l0eVY%yu*B-#N7A^Z%a#RGx>b$&t=Ie>CcjAwzBth>-QMos6}WqQ-*+#)f0~=$ zpLd@3%~GrT#pHLl=C`vkzm`(7W)r(TD=P50)wP>=>%{AvtThl-y1vkCqustYpRRI? zT<+^U*WJWbZ{72Q6uE~a*&s=}&eQycdTHJKmTP{q$*=Fa=4o!3pL_dOQw1^YUjO#< z3(XO7TE4jW_+zc^t0c*7CcpKvVCwHSFKtY_oqzxFxTKNe`_84W{I$eQed8BbJSIzW zK%P5v-c+mW7d|i1M*Nxv>q(l+U@wW}lCW8< z2R#|nZr5XfUgy!dVgJn^dUU>g#w~lieQz`R13B*!g9&oklV?nnFDCJ0ImOH~#u2ew zu88It)7#fPvA3*Zo-saoXQo^q%`;|yR7~RAa>+E$nB5|_OJehkiT1@$n!a z)}32d1l!qdgO(N5%WBc$II%3tcZB6@J-o%SErzuS#YwZE??^-746=+96K(riAJ?LV zyzQ-Ki|Owpsk+GK0`7veCC%IgIh&hnhK`qE3)>FGnItU}CA(xv(yEPY+~nLk&Ti47 zG0!%wEMI_|4iy5!*bz;|TeLeW(8R@f|71Q5{2Z?d;f?^!Up%JDTlwb|Ml) z1s}?kI`0yhiK)7-XRoy7*rd9()9svlP>Bg!1wY%WFyT3OvBU(^;zwIQ+9lVLu!}6nxh4;JTOVev$Va3e(_DD5 z-jF0w_V2A*S++c6U3uF5`zO~`B~PzkkX&C^om^L0UtLqVpl*IcO?5-fwB+i#B?}tn z8>6~r+M>Fe`iS?;`m*-0)(on#IZe=ghCJnv+~#TUA$+ zTvs!%roO5^xn@9ReZ!(@Gv_Ba%%4A}y0&WOy!zxB)zy_%b#s$bQ!3Lc2c!&0txQcZ zW|Ejm^XAX1Nvf%uIx{IXrGHwIdAq;7-Q=z0ne(dWESgr6Jh!U4cILeQ>&2*FQXg3p zGisAF>ZUE4Id6W}{JNT?a9u2JsB^2ttC5nr`Lm?X>yyhCRMpMST{N$-DDxziHniM5@X$%Vns#U9h?>>v~dzm z5Z{&kWwimaTF2yLl9QcIzNKRLnkC56$qC+4oVz4>b&@oRzE%lNoUdNqbDcORE-7+@ zF+nG`voT_haALc-?|4O^DB&nuGlh&zbmF>4toI*_+QB3`F3Cyg>BRlh26{Bv*M!J@ zHH9|&Y9~96l%tWK#e+sELjozF6O4572+Zo}L!}*jI&|-s$QgEodpyIt-?V!E$Hh;O;u{$8%n$y;| z;j|Hs?fb&+pAgkux{$eLC6zg)rIn$gu^9!S?8=PNQ5A(bMdcQ66y}tbWsJ(HEH5su zEGRA-WtHZPs!Ywu$_uZNRbEyh>9dLpOA2zzWzCABkgk`Tl~*~nam9?%?8>6za#^`7 zr?fmLJN(Y*63MipsH~!-q}aSsSrQtbQ&5>(Tw0h>?rl-BYPx!6L2*`oWp+k+MrBb& zVP;OL*^lB(8Qc@l7HE=P@$Zu;F1^ zxYXPxt7MfQJj{Z^LbO{kP(T_{I6E2BJAT;$c$uyDfEtcaAM z(lM2p!dP~w%-a}s>1Am$a}Qf(L8vG{Tx;V(xuMF861S9D#YIIqS%wyuyxf7N!raAd zMWU=CD@!O1rv}+E6*(0-mAO(=;kQaMN<-xn!qPxpm{BxA4_#vx?qMq{E^|weEmVgK zFv#6Ld!g&)rpozISyr5zTiImg)L~85&dMmNEHBL{Dk}_?yE&KUWMofpcP6t5u%%@g zl979;rGgb~wpm=3RasVEEOnYAIO;L<>ZVC15$98Qhn1d;0(Z-m#U(jK;rBo}votg+ zue?ZVw6ZLxyxg42Y&tiqAm1%++CcBj8RTx!-FOO?dosC}Agsq~sJ@vh)fdh!6e`Wl zsLaXAs!Yuc>1m$T3v!cwaWjQw@+avE(GB8Ueo0HqrM?~_{@p4L67LUy-%`GS%clbt2i$;Z;P2nn| zFuX#jL>egRz+z>mNsGG^5n^NZd``!XnCkGM~;%4$I$Rm&WhMzi5#P{(k$U9 zBda_#*1P5mj=0ouQp&}7RFQjOc2P)^Rm?(0lg2%=WoT@%Qggyb&MbzDsUXO)mvg*A zFLzSR#ua3vnWY(WNmqo-7Uk$fojajs-1kTf>YjZHvSR&iyXG)>_I)JdI=W>uMUx7I{|<=^2DG$jT`ws3^!Nl@no9s7#nQmos)2@@N;l{Ya7IZZ$M% z*el91-Aj69S)TM?yfvlCqw$N_WMPgpXWFr0OD4ZmX-U0wIWB99=0#SKSwpT6;euxm z$kxkdX--kL5FOD*hat#vJ4niv)bzX=HI+5IHS82|-aAu)`f}Bwq1$tUaPas>` zg~m&vdrpL}S`j3q4sCK)C{B5jQ$$BBo81xs4&x?dn#jW%r^t?mG#Bn^?p9Cu>`5Ke zBqL5Sj#k7qzX@Fbc*SdEt024BZEV9A7(K?`A(4hi4`phqUdZIa9E*sH42oU9yaH^K)` zTM_qUn7(LUb;`hjx(`i&4U>OZ{lh{;cey~$j7AzL)2NKX!i;d4Ol?VTj7pMo+}&tn zJCK^{vNEcuA|Y$oumm#=+&?wJOa!M49WXGVPhHKNnyUJmqZ5+mRxemIvU+}9L(Sr( zxoK%)G}JDdJ5}QJIrFO;l4KTnq_i5-j3H}IUvSc(r1}L((^3bEQ&m@8J5r{VPa2vu zxBpz3nC?5RenH>q3lfrMBqS9NNJx_T%8}JlfTZbjYwGK(X4E9jshKyUp>|}7Sl$_z zWVjJ!YOi7D{CP?BGNUW8Uc6~l4OL<7?&6RpG`b{smm|}|cMoe$QE`PdT3-9)9+E-B zyhGBoXCA)7N#`yjGgJ_o*x0*Hk!IV}aaxncx3Lv4r&1WlMyloNB<(}FbWF`vKD+|Q z&>cZF9$GoyvZT+DnIXd}ZG_D>Wklc=cSz$|AbkPPYdU-}gA3D@2+8Qd>vWh5QnOw3 zW){q!zaZ6e!+?J&OOp$FlYVlc zW<2d$(&Kg)ykVwmrG(e=mS|ifx{hv#SH?x!jg!;c%T0DIqHZD*n4YLKVJ;Z%s*MB2 z@JM&C=HiX<*s9m0=Mn-v2ad-yNV2j!`X$;m)voc6*A=|m8ltOelp=j z4NAkIi)J*ZrEJVe2KZ&BU2Npitn!cDR}OBINxUXK>2S}S@v1kxq87ADo1U2*E4MzR zSLD@)4B{f{!(8;tNT#xET&P^$iMWC?+DmPmDoB-<*{ZLVeo}bcY{qu(2IQjbE|{^L zF}xv{`&PsWCH?5e8ZuM3?mUa>g~;4O<*1C1H?b$&g;%3;WPDIj(AeQHxYK8e?7oJl zcLp%MV@82g6q%Vmhc(M>`%Dqd0E<;3M*}i#8p@J3MB4Onx1PdlmB~<7rUrEQPrXHa zis66Pz5DE%sf%W~HEITH6w;iE8JQki-qbShu!p%a29qIeWo|)6Sz|ihttc^Mo4EpJ z%?}$Yg^x{EZdT)QNi~z#Y)NN8ylbR;puL%Qvluyn?T+ORYd0Euk=Z%_rXOhz@Pr(1 zT+4v2>A7#FV^?lC*-odiu9pYVX)aV*7mM`L<|M(j-_ zRZVWp=x$aNy`Ff)cb}v)rvE?qEdk4jR+l+m9Got&^WPZjiUaDTb z%*e+0E)5lSe zxZ{`V&B?minCVS-!RuPHWz&K;y*PzWugEjPD~V*`p7!DT$STMvEQz?Xdw7_8cP8J) zn^=v5gVcfH))DMe%><@bv?fhZMv3&{$IAe^3BVD>^XkDnG1wpYHgL-A;=|`G-F{SV zMr0?26s&4W5;5kGtEAShcPTM%dxHZuS>pA$WyUUCFD@t29)yjo!t5r)PGOj17Cw5B zpf$G7W^z079uvj&cH6BssZzK8nvMh-vyj`MblfO2W3jS|GP$#*W8r_9x-_$vhuz9( zoUM|}PLpYr#!;f&Mb{f+rg&x$6CPW!ebX&)uXq16jy3EU_!yg+Tyk|EQ)Q+rT&vWD zHxC-|p#X0{;Z{y$H`N{ajguR_=2myH-n*qp-UPh4(RX;$Zmxyq);LWOw^m7+S&&hb zFDG!0%#R(`hcdfz`09-Zrl44EWfd>XlhB!S}BS%IaMiD&^GX~RY*J|>b4z}pF z31$E87O2)7#R_+~yb+B{vYBQiGxyq4l+pP41#|2UuY{7y@C`>(pIlWM^YD(&xZ=`$ z?aPLH1*y_am7Qi)X@Ix^(sYQGE0c_jPRyq+tWjB6!xQ?L>HLhkxd}OQr`AlHCinBo z`9Qck!_No3kN)@b{qn^G`3U>p@{rHpFKgYhm6Z_j@ptp-_srG_s{*V2XU42?&Wb+U zcTUv#wv{nVR;n@|D7S3+E}`WNO)Bg!!;T^=rk%gAnXh>uHoCpt!4CT3?T&UQyR+TJ z?iSUa z^A46}zB(sg(6KHzQNENS->G!{?dtDUKS3(ktZ%-`X4X$PQPy9p{(AK{s~?b$&YSl; znJ8ajF<&QZE?<+GrT#MYmzyZx|66OKeBPey&lzkm{EA2aP{#lrNmRzWLsb*&p+Z z=q9$(7^l(v@|E$sYwWGDuf|l3Lo|-mn58kKu~=h;#z`8hG|tdCS7W`#B^poHxLV`6 z8ZXdznZ~O%-k|X|jdy8$K;ssTPicH!<7*n<()gjq&o%DRxL@NTjne45^%NsKy7j2B zy~fTO&37Hm`$ua`(KtloaT;?p7HBNfI8kGj##)W@HJ+sLRE_4lkY;=5YP?Y66&g2c zyhY=k8XwU3n8s%`zNB%7#&x-;iN@s`*JwOn<0Tq5XuLt=?HcdV_^`$&H9n{DRgF6} zexUI)jo)b8r|}n!e`$22oig>*Qe&LPP8t(6_R*NEaj?db8nZR#Yb@0`LE{vSGc?ZA zxJctNjb~^)N8<$=FV}dj#+xHNK|_H5zZxc(=w!G(N5IWsN&Eex&g$jX!8Sq|uh|E}Q*puCcwwG>xOAduZM-(>PPE z-9|6cc&>C-jlN8y`Oj*jAJO=_T;PrVK;wSt9vc0p#=+7zF*-}*GUly>{*Rw`<&{)*n(~~q_oapK6G``={(_d>$IMUNe8mCJK!{k@5aq}^renjJeexCkY z<51~{nDuiso|fwAb2V;D^Yjjl&85R))(>hd8S3d1G+sK~(>G}RaD=D7(b(g7PbX`v z&G7Uhjdx~wdW*)Nay)J4dU3dnw9NM9<3ny-KH7`tX?(80({E~QS?uYK8cWA`x>Doi zWuCrCxe=hS;zzPjt~*S(9p_@u@|Cwtmi z?8W1jdNE()s%4(OK;ui&VK?>jj>fhtJl$2}*fTs`t#QL@Pv55Tvo)UnL1UkDJUvL` zytSS_MdSVFd-^GjzpeMQ{{k5DYJa+#;!(-?cDr@Lz$zroWr8n3y= z)0;GYvC-4}H6C+=r-x`zsEd1Ok>>>o<3dU!&^Q5tj52d_H>J9 zyqNv07sqHk=Xp$iLQE{(h8_i{{mf7aOlEl(e- zvEdz0uh97Dd!Bw?qxGSuTWQSw*wbYi*Y5K46&m08%+sG}jQ`Tpy)~ZrwWnumyzv`P z-=lHQx1Rn*W6JlQ9;xx9eV#r;<74t`J!b!2)EM=%r`u@E`^D208qfdL(^qNSDFZB% z{!@*e{_^xu8mGv7jCp^q#+&8GevH0P3G4+0te zvc~Avo^GdcbX!l4)3{!KE6A*WwZ^yQM}v(1Tw@pc^&q2<);LuLf=18Rc&q%LkkJol z{9b-o$mriS4ovWLhQ_5mJiSKaR+$hm>%Xco<|t3cX)HL}(-Sn_E5GSw)_+pt%NpM{ z(Xp&ARqr#grTiF`#$VNsN%GRiX-v?Vq;a^$Q5wrNR%x84@f3|`X}rWl+5XEKcWV4v zV@H{&Gw=7%I7s76jddDVYkWlG(;DB>_>IOc@(VL2zup>$X`G{Rk;dCKeynl7#$NJc zGA8{HjWbP@dY!BBB#lcoo}qD##`PL6)_AqX>onf3@lK5oY22bQV99wP+m}P+#yE{Z zjomc%(0H`QB#qKtw4$2JkGZIp;N~O40ylmd<;C_!x09bg8XD?m zPF>U>+5Qh6GHoWUkT)l0k_|L35f7CW<8%L|7AV%o_QQ4Pjj6A(|Reg&f(jQ z{FNAUOwFU8Je$cgU7qe^mi+jcEJ#<~{4j_6G}}8-o|Hirt)ar%HsOv3OB2P2%Mr8RmN`9tZP5Ii$ll-KM{LJ%tjjXq0x^0aXj|c1R6oWFD_qxomo3LuOYaZL>8CkwtBlg#{OO)?ZSr(QT zNN^t|lHYKIM7Cuj=ZblIt*p0QOw+cR_Q>SdR-R^?oEx%eO`d66H<|@~ke?vgWW9%_ zeEV5RBJ1(%HUs<5Pfn0W>X4MdLsJF}O-qsGl$6wn*TI7a8Z~IxK#2(nQ<|TiQ;_TZ z_>z~gEi>KZYn**oxXSU`gg#bBX;G8DIaK^uLATtUhaP^a`L$j4b@Qd~+rD~zZqb3L z%vQPE4y{Vqb|{egK>oHv+fsHOicYoq{{DXPzS@@e{A^RJdHx3vz8O_3A{*M>f? zx_0!n`G5cN*WblIE%$w1W%b;4XnX4CGbcq^`>$MG{L{pG$vyS*{B@&c{ggMfM15R0@}jI?B$%zQ%3YDaV)V+;N-3-L zlyS^6I??Pwd|ZRO2d3nw$kMKaQ>5Idj6UTb${qL9@;3Pgc4f)BDaHH7OYN>-RVQWN zEA<+kIz#GpSIXpYJ*DWjXXnozJts7$$+puEOm+9YHorvDZ%;94w>8$lOj851-PcX- z>$mP}PI#XeBo_ZPFgx!+&z^l|$+~u}`+BSUy4!ty`q18VdA1!BlKN;HH)ZhXxZ2C@ zKXw-Xw6*Nbs=NbnzPKr=;$0E;q)ch128;JC&w5(Qly~5P`lqE-eZpJqJNtOaO-eTV zxI7a#%{H&!y063Yj~#7lwM)TpcV99O#P#esrDyFkKc?4QW&h@Gci`yHs|JP!S^vN(ZDLT<(`Mvj`FA5(aSgb?B!oJzkARRBc6LF z)dnhzii8-w_<+(V8$zQ z(xpGNW}h@4YnQKmzu=+nvp2l=!ut9}cmJCHPEO19R>G~FW4?=yJ|pq05m8^gFf6s9 zzG`lLLS0QwU3HCD&fG|^LS3=_2&mP*lRi3iOu7ti*T5ya? z(hvB1J~R4-suoki$Ec(>aclk)1>39SC<*J0lsCAf$?;nxb-FO`;2PfpLX~ApEsl}; zZ5zqfyN9e4bJX5F6s<9!v85Yt4j=7z54BB^(q?;Ww@(QqcuVm@hW{9Exl4-hG{G$Q z>zQ@XmzQyPd$ zEk@eRfNWpZm?a z%%3Fr>`l30|IuYP{QRc0czYAZnHJ{mai*o%`026ox?Y~LB{xU2g(-#<^UOS$;I=O5 z2WQ8LFZI8?ta#ttmS%Zl&rv3alu@Bk`FSQslX5F5v-7hK_KY$uQ0JaKrhGniV18%W zi{IVzF11MVi~q4oat}$Vo9*sGobr_6ubljElOe=X25qrRENp^5fJN zwbytpPDz%uK`oT<4W2hS{a|8@v}!4Rdv+^`7J9mD6@sP=m2=!@ow3}U=jQxQkf%N8 za@(2{Z+-W$KlI{9`6I8|+^KNL{y$1iTHox8+sg-b%|H9rA6r^ytr)c8{lwj?UhVK# z`)0q6?Z0ODq+2p?m^ifMmJP2QKgpTV@5zVPML%`t+dKNze{t-q&%HZ(YD;U?3R})~ zIlt1|PI*(xtF30aw3#WJdfqnrm8!s$m#2o$$}#B&;?iy`+EEoZCC%l=w6H%`nc6Gu zac%z91`gB<)KUUJl)l{r<~_n3*(D_syH$0K-J`|11ra79k`)n zeB!$NbA{P1QmVbX%TN010INwUy-mZid^13bI zgVPSsV=(mHJLK#v9(`<;iKn=) zTin;*tIBF8$@_1JKdRu^sV1J{zHV_}f1g@id!oF*Q+hHL`NOMCEDtSpV_Dv#ZX8zh zTlE$n;{opD&+q^5y+uFK#M@O!K*?9+_ZD+1xNkY11KX+)moEzKPrZv`?9QoLu zy$g0oxvOg@=ys3IA3n`&cX(*28;9jR>c-ARzfBvW+wCY<$bZ_Z$*-O8V%hbQqp1m# zQ{VjIQ%pQ2wA779=RNAi-=-Yp=9k_xT59#-)Qe_*5dFu_KDm$YKD5reCa!8}x{Thn z@7uGcFIm6$iWdgXzwV;`)^mHrU*QB|ENA19_FJ1zNPDU6**(v{%(s70hbseb$BimF zdgPwgw}1KDgWq(k8z-ITbU7zhJhWz4)S>;GrrxpSq}{teTycExt@$TDTzq!F?Z2;` zaDi`m=$WT0AMJJD_fPmH`x5TklvcF!>)ubhM?69HH+6#BKN=tIAJI3f$gdbZHZ<0d z6z-d)ADo(I(v;>G$i8h)8S~%jA7zBEU42a-D0Q~`y2*Y0)_oloUV|P~TF*YF|6J7>y(-uFwa zEEjj2;#&SOokRtkRx-qk3iu!CD4U9Q%s1eoqW!}qBj4LXv#(!VhOF*8K0#hm+Lz0+ zvrb-O=E%s^A8m&G(fO^-Z=n0PnlYdMCCSeA|19IXC^03Gf2oZ5qWv#RK^^~_GTw{v zx02HO{bx${0socaH}gLu>o@n0mmFI7cgS2-OMmYK`4Eo(O&LzN_Ro>our~fS^4iwF zOV(`Xf1`_hRLyVxnIO);N!Dra|3pUS9sF;~I!E|7%1lnszr3eRd-=bRz3k{;Ej8E4 ze}?#-{WD}7+Qq-JyL_n1Z$8G;-T#`ro8W&!wwUPOAvZF6_zy~MJ^edm&0hZ5t!0|g z|Ci)8&Ht!WYK{NQUh+Qy{-dP~FZ#chGQZ^SAX6+a`&Y?G^%Z}qc?7*uM*4u&JQsWocfov(tMRwqPsk@8qz$U4# zOYFdhqAs-qk4v>(W(V$;TrRf*Wm1$Y>_D}=ccmSeD@D4>4z!oO`pFIqmGHA2I5OI@ z4%&h1Wb41!fq7C}hwQ-dQn2w+fh5_`V^M(@rO3N|fwfYIZ+w9@GF`IA7r0CE{MHxf zEZpt&1-_Pg`OX(uEtT=TFL1Tg#t*(gn(WvGJ37!Hg=p^trpq36Z~{G~ zCKfw^LaC)CP9RGT=TaxoM$8YLfVm6)krPOjiu~9Kbdsz;aRMWyEW4b*3sS&Ooxqz? zOP@J`X;PN${=oOL<_>=#QT@ixl_a7J*hm^dl_-*GXoNwg`-n1Gl9`V5wlcu}$C;Ve+~*fm@~U z*S86zNRe)66ZlNRjco$vLw`553EU)k-rOdzP}Es*f$nlN&yEXhk>qWU3Y>3Fhob^B zWp5V*10_W;7HkQeK4?F)@%p{?v~106b#hLZk`kjSaQHm4h9Cx;aD6D zTq-rVBp3(^xl4nA19FH@2?p+wnphSLJR$pVYA_HZ1w1Vn*d)nM4+c(`id-HH+#yV? z2nMc~LZoj9Oq0!KYzVw9nPqMWyf4+7y&({kTyi!9+DL`uZV1R-8Ee#rz$B@Ol4k+~ z<-IY_1o9FrYs#L$IdTS6?Fmek;!fQYs1YWr_XJ91AExaIESDnH>}j@H-doVlwwm29JG0O%w34)SW?_~b_Ik7MtCX<8EOZqN7nz0gr5aB%3l);fayg{U zK9`kOn1yP|XQf%VQYzvMv+$c7t5s&7enT3bsKr}ZC{UqlW zW?_S*GM$uW&7`j7=f%v#MB32nAnsFVtiG7DeGu`ubZ<})Ot=y|qpqv#gvQ}Ia*~`k!hB5jLI$|2U<>Fm7PTn zvYdV@JBb`@IY}xziX37&{Z+<`9BMhqDuW`2$^Xi$JVIou6f0GA2cxB215~#+S_+n? zI?iY**+A8?MoZBKscvVqlx?u;wnj_ghNy01w3KeB>efa}@rJ2xWwexUxayXo2T1vj zRo%j9Dc=ay&5f4wja1#tXer-usslz#`HolZH(JVbc zR<5Z+D5{{*eNW zAtc{1h`EFmXi_DlP^A)5q*4hfR;h%Ps8mA6s8m8qRVpE6DwU9Ol}bp3N(dRN8bZdY zhLG{9A!LGT2$`rFLMEw(kjbhcHXs8m9(R;h$sqf!aERwaaNR1G25sfLj2 zRYS-Psv+b?)ev%%Y6!VmHH6%v8bWSW4I#IwhLGD;L&zr85VBb{gxsMTLhe)zA$O^U zkh@hw$UUkd>)r5b~UA z2zg#LguI{{LS9r2Aup+hke5|M$SbNL%7XP1O*x zQ#FLVr5ZxsRt+KVsD_YtRYS;osv+ck)gB=a`@WXr-|ivl#5#|7ggh_Zd*=hcA;%E% ziDUkR(IsS;CRIW{RjGu0rcw#{T%{87g-RvlOO;B8I;J*pw( zTh$P9(E5+C&C&Xgur1K~kFYJ#`j4=! z(E5+CtlG1BwP=K+#|fC>nwRMME*5Xcz_* z4ab0@V=`*hw)JG}0RAyD2(YD|4Whg4L9rG8#E=9$pSBgr|O3@g!QdEjo ziptPRQ8`*Esz576W6?^{IJ8nU9t}kkFra861{6)gfTGD5P;>$Y6rG3xMU@y(Gz9~S zsxY8vDh3o)V?fa~3@EC>fTHObP&5MrifS>SXeI^}&BB19*%(kX2Lp=cVnES643DA$ z+xMXW61z}l>zqQRXqI$wocXrj@MS2fw;l5r(=J5~q*sa-p_QVO&`QzCXr*W|S}9tB zR*IIQm7-J7O3^a3QgkXBicZ6TqSG;;XgLNHt-yeyl^9TT1_l(Z!hoXH7*KR31{AHq zfTFW7py+H2C^`oNiq6G=qO}-MbRGs2osR)U>oA~bJq8qAfB{7pVnESF7#>9nZC?+$ zn8ki*I?i=U(O@Gkw*7`LL(%27lO^{fT#BwBy;5`~S}D2;trTrQD@9kMm7;6VO3}4w zrD!8sDY_1=6kU&oq8l)v=tc}Ex(Ne{ZpMJ3TQH#LRtzY*4Fig9$AF?u7*Mns1B&jz zfTBAwpy)0PD7qU1itfRHqI)r*=spZ6x*r3I9>9R22Qi@NAq*&b7{jCJQrl&`QxBv{Ljf zS}EF#hNABdHGqh6F9IX_!Kr2Np(MnM(v{KX>trWFED@AS5 zN>MvB6vbjdQ5*&owa0*>4j52$1O^lZF`y_O1ByCgKv5?QDC&#>MO`qUs4E5(b;E$7 z?if&%fB{8`7*Ny$1B!ZLKv6FYDC&(tTXZA_6di@(QRGDVh6^CEX>vo{iHY(?`j5!x z4V*qve#4ics9%&bsgF{WM0%yDKUyhDMk_@rXr(9>trQJFD@AE&rDz~pDH?=UiUy;h zXb1)r4aI<>VHi*}90Q7u#ekv_7*I441B#BrfTH6upeP*!iZU>uC=&yUvM``18v}}R zFrX+G1BymrKv5nB6ooLLXfy^CF;Twd0!ZvG`Rs|)S1GzpCZwIhD8J#$ zP&6jWx$YRHsFd_dQ5jk(Dn~0t6=$Y z6rG3xMU@y(Gz9~SsxY8vDh3o)V?fa~3@EC>fTHObP&5MrifS>SXeI^}&BB19*%(kX z2Lp=cVnES63@Dn90YwWiplBh6M^SNPY^_BQ#TkW-=*%`=y`x+uTl%TRPul=F2z zrRZeRD@BXZO3@OuQnVDU6rF-rik6|3qEpdI(P?O<=ybGFv>XjZD=?sFB?c6ofdNIU zFra8P1{9r%0Yz&tpy(_NC^{Phiq64+qH{5zXe|a5oreKM=VL(8It(aUj{!v&U_jA@ z7*KQ(1{7V40Y#T!K+&Zb9z_jNzLrTs(K<8hxJW6=HVxBdQGUahq3Eh8Cn;Ge+CX}x z=xVf5bPZZ5x)!YzZA2?Y*P)f7>(NTl4QQq4Mzm6N6B>$c#(<(*FresG3@Ew{1B!0P zfTB$pP_!8XitfOGqB}95=q?N>x*G$E?!kbfdoiHsJ`5=yePz z+KvH5J20T=4GbuH69bBNVnESb7*O;!1{A%60Y&d(K+$^`Q1m_q6n%gJMIT~7(MK3i z^f3k$eS!f+yD&V8o`~{YE`Y@Dmk;MUPbx*Xm``_n8s#^98H&D)avn)jioPPfQuH-i zDcX%zioQWBMSIXn(YI)&XfIkR`VOrWeUDa(en3OfJ`5<@j{!voFres13@G{u1B!me zfTDvKQ1lB16dl5VqF*tf=r;@~`W*v`{=k5uKQW-_FAOO98v}|gpAOrh$i{%8C=4j_ zVL(wd1{66M9z~x=`92mvVvmzM9L^U?(Ou@AevHp=_%akV_c?zLQi@uTUMXscR*G7o zm7>;YrKk;BDQb&WirS%-qFA(26o*!d+M}VU0|pcwfdNH93@D1nfTE5VP}B(niaKLJ zQ5Os->WTqH-7ui2I|dXbU_enK1{C$cfTErlP}Bqe#4icDB0)a3{{F!NUs#7qLrcnXr(9(trQJJ zD@B9QO3`4nQZxju6b(fyMZ?fgG#mqpj>UkY5g1T35(A2k!+@gWF`y_N1Bx;*pePdq zin1`EC>sNcaxkDM7Xyk$VL(wH1{8%bplCD(6y;+;Q2_=N6=Fb95e5_$V|WxL`Fyhk zkl3JUi~1`?Nj?!JKEL71P*m=7&K<54RghjO8jDtn#-Wv>@o1%J0$M4Wh*pXwp_QV^ zXr<@`v{G~;8j310plAvP6jfnB(Nqj5s>Xn#X&6vcg8@a;F`#G$1{Bp|K+#MLD4K-< zMYA!WXbuJx&BcJCc^FVM9|MXOU_jAA3@EC@fTDT~C~Cm)C@S^&?iN5|b4Q_xD$GPF{3Dq1Nz4XqTNj#i46qm`l+Xr*W+S}8gM z4MnRkplCG)6rG6yMQbpi=qwBsIHwF}0(K>90A{zsWqA;My zhXF;=7*OP3Kv4_^6!|frD1hNn^p(%|f&dbGzWIF7*GkbhaxdR$7VS5D8H!p(JKy9e zMXgD%6tzJsMQzbaQ9HC!6pL1h;?PP_d$dy20j(4rfmVuwXef%ufTE5VP}B(niaKLJ zQ5Os->WTqH-7ui2I|dXbU_enK1{C$cfTErlP}B6s;5uLn}qY(Mr*=Xr*Wb8j40@K+$m+P;@*76s2Q8Q3eJS zWnw^476ue$V?a?31{CFDK+z}+D9Xctq7ViYjmChYd<-Zmz<{Dc3@9qXfTCgyC@R5# zqA?gyREptIloIVL7eHbkFrT|lRf>{~D2w(Rz6?dfTHObP&5MrifS>SXeI^} z&BB19*%(kX2Lp=cVnES63@Dn90YwWiplBfm6xCrsQ9T9}HDEx|A`B=x2?L5w#_%Yr zi1uA6fW%HQ9qO@4(Go+^;%L9&%TTl|+SyW|6rDRd4hcTe&5ez7L6a$L3U_jAh7*O;$1{6Jk0Yy(@K+#qVD0&LRqv+ab-;n}HY^OE? z&PJsu*?eO5>1e;<%TV-Ov@>dqQuI9Om7*8WO3{mGrRXKJQuH!fDS8F16upX8ie5u2 zMX#fkqU~rX+JON@Z(u;tn;1~E69bCg!hoW;F`(!j3@CaR1B%|mfTH&?py&e(DEbfs ziax@CqK`44=o1Vm+Jyl{pJG7KXBbfQIR+GcfdNHdVnESX7#>C2qJ47&kl1GCBKE9O zRM1ky*U^5%m!as}Xy?2#rD!kdm7?#^O40XdrRWE=QnU}P6zxYVMF-GI(T`}Q=qI#N z^fMZY4q`yjFBnjC2m^|K#ekyUFresn3@G{o1B(8{fTF)Jpy+Q5D6$+KwnLGP0Yy<5 zP~^jaqG${#axkDM1_O%x7*G_zfTCs?P}Cd)idtZJ6nzuzyH@~-tv1uudz7Mf=Ch71 z9lznrP}J6O-mFlH+L2x zMO`qUs4E5(b;E$7?if&%fB{8`7*Ny$1B!ZLKv6FYDC&&?MMq*l(NP#s)CU8Kj>dqZ zV=$noF9sC#!+@eB3@GZ40Y%9eP?UnX7XsP<2QU6iY7WvM)?F9s`ORFra7=1{9ry0YxWcK+$3h zC|ZI6MN2U}ipD#>RRTzCiuv621f^)E`Sq$(9KYeqP;|QE+%#D!T26YUXa!m+T8UPQ z&Oj?gtI$f(YP3>xCR!<4gI0>pLMugQqoL>=3@ADm1B%vSK+$;^P;@>96s^O6qV*V1 zbO8nwU5Eii7hyor#TZa@2?i8hiUCEJVL;L47*KQt1{7V10Yz6~K+y&aD7qR0imt(c zqH8fcicWQWF9{&AN14xEpQaSGYA0f&<2QU6if(kAZ%bTe8hx&^Hi-HKL< zZbK_Yx1*J!O=zWPGg>LS1FaO@iH4%PFrese3@Ew>1B&j&fTH^_py+-KD0%<`iXOy( zqK7b`=wS>fdISTC9>sv7Ef`Sr7zPwQjsZnaU_jB67*Mno1B#x)fTE`{py(M4DB6bM zQFOiIYg;K4)tlz$2Bqj|a|h&E$8Y#D6usy;sZ~nROQctdUPdcLub`EpSJ6t*YiOnD zb+l5n9jz4YKr2OWpp~LG(NMG#1B%|lfTFiCpy(Y8D0&wIir&M3qW3YN=mQKW`Va$( zKEi;ak1?R=6AUQYg#ksMVnESn7*O;%1{8gP0YzV8K+#tiQ1mqh6z#@sIHwF}0F*d4Airz52>ozfd!MyoDe8z;iaMc{ zqRwcgs0&&t>WYSD z#vAFcG*`5NF@D3Bp=fA~!hC&W0RSxV7~q*sb6(Mr)2v{F=sR*I&gm7;32QZx;%6xE=WqUmU*Xa*XJYB8W_ zCI%GE!hoXL7*I3^1B&KiK+!x5D4LG}MGG*XXdwm^)nPzUJq8ptU_j9#3@ADY1By<@ zfTG11P_zUCik4zP(J2^Ev*<2QU6idM!r z>*gp$XOLbgT7_1MR-=`oGto-X8njY$7FsDf8?6+bgI0>pMJq*X(NJ_A1{9r-0Y&RD zplCe?6kUJ;MHgZ~(M1?gbTI}LU4j8cmtsKCWf)L&IR+G6fdNHVVnESV7*MnU1B$N3 zfTC+Kpy*l*DB6etMb}|K(e)S}MayG+_X{AgH9ZBK6-tr(6SEB1V*G|LL(wfU&Rg@8 zqFYI?6y1haif%_MMVrt{(Pp$#bO%}~x)ZGw-Gx?)?nWy`_n@KZUJNL@4+Dzs$AF>- zFrer`3@CaC1BxETfTBk*py*KyDB6MnMUP=X(c>6U^aKVJJ&6HDTQQ*MDGVrj8Uu=+ z!GNM|7*O;q1{6Jq0Y%Sacof|fM*fiE%nFREl0D zy;AfVS}A%RtrTrXD@8ldO3@o=rRYtxQnVAT6upI3irz*;(K{GW^ezSzy@vrs?_)sG z2N+QFAqEtEgaJh#V?fa-7*Mne1ByPyfTGVZpy+c9DEa~eioV2vqOUNZ=xYop+KmB4 z-(Wz|9t7+4d>M-N$2e8>O3?w*D@8w| zm7<@}O3}|~rRX49Df$Ji6dghKv5eE zC~AuVMeQ&=ihhXkohg9Co+>|W?d(&EZZKbQjP?5sUxuP1{LU?ll%gQ%m7;jGQq&Qx z6m>!?MV-+~Q5UpQ)D^81bwevf-O)->0vd`EF`%di1{C$gfTCU)P}Ca(ijKs9qN6aN zs1F7d9gP7+$6!EFUkoVfhXF-N7*Nz71B#L{peO|cic&G4XaEKjrC~tPKny4vgaJi^ zF+7Ue`+ctnAhBnfDWVR3Z=~PcT+xQef1CF%0MecnP{ab3#}Aoqm`l@G!*4xK+z}+D9Xctq7ViYjmChYd<-Zmz<{Dc3@9qX zfTCgyC@R5#qA?gyREhybWf)LYjsZm#7*I481B%9BK+$*%D4Ku)MH4ZgXcC4;(J;R+ zcCk>@+q6Z)m7?nmMU(x0!gt$1`H@#gaJh- zVL;Kz7*Mnr1B#YlK+#eRC^`iLik4wO(Ww|vbQ%T}osI!T%P~BPPW1c63m~yu%zd;< zr6@X4#0tOP@MS1k?RSD@Es^m7;UeO3_-hQgj|#DLNmm z6soK6{1`H^=5d(^D!tf|M!|%IB0Es=)OcAY8iqg#7 z_04|2;mc5TyWe^8G^J=0>6N0*Xr<^5v{G~@S}D2fdISTC9>sv7Ef`Sr7zPwQjsZnaU_jB67*Mno1B#x)fTE`{ zpy(M4DB6YrMbBbD(Q_D3^gIR>y?_BlFJeH^OBfzSxB7iw2q3Y0%10$M3bL@Px-&`MEHG!*s1fTG?QP;?{)6di>D zMSU=!=x7WmItBxZ`eHy)KMW{J!hoXw7*Ldq0YxboP?U-RMFTLPC=COO24X>1{4)yKv59} z6cuAYQ3(bVjlqDTQVb|6!+@f43@EC=fTFP&P&5t$ipFC=(F6=Anuq~KlQ5uYG6oc# zfB{7(Vt5pd2>AXGKw@9-AmEHtibfex8Sopv3`Nxer|UUN(KOO4MKx%pXgXRcnt@h| zYSBv3Otexo3#}B*Mk_^g&`QxGgPRD?vAc z0biy761%FCfHPGo+HELW74RFr3`J)Joa(ho(b=R|iq1hRMdzZGqP1wH=sdJibUs=s zT8CDO)}xi83(!i@g=i?c2m^{P#(<(rFresC3@Ew`1Bx!kfTAlfpy)~rD7p#*iZ)GSMOOoyMaQ%a9w&l?E3-tLW6h#;{Yk9# zZ4=ZlwdlIGq4g)5Mc32bEV_Yg7TriTi*6#DMK_bpqFcyj(XC{&=r*!hbUWEBx`T{G zcLK2JE&vwY4Zxy%09bS{0E_MeVA1^mEP4QdMGpe7=pg_WZ3JM^!vHLL1b{`40Y z02VzCz@kk6EZPjfq9*`Y^dta_wg9l`DS)%++P1-`MUZe~TM=i2S@gMnt?22t3F?gijcgYEPBx4FAe%*hlFcG7(XQLgq5v6-;s96_1Yl7c z02YM+SQHPyq67dIwFO{NA^?k$09cd^z@iiY7Nr8PC=Gx`?EqMm4#1)e02YM-SkxYX zMI8WG)DeJ1od8%A0XU0(Xd9d%f`nhr7IA(wi&pE~A(@E@>X%y7EirV+nPyRU+M7jL zWV5IT*(}N?n?*gzW>GJ)S=5_s7WE;UMSaO;(N1J6+8KaF{Qy|hAAm)>0I+CR02U1Z zV9`JT7Ucl2C>MZ5c>pZR2Vl`402U1fV9^i&77Ybp(J%lO4F_P+2mlt11Ypr_04&-a zfJLJK&Y~`f!F3`?xRd_ee%C~IrQe((VRT}G`lS{XB!(V3+bkMOd$XvJY!(%f&7xwm zSyVzci^h@7qVZ(2sFZ9LO(2^^6UkUq2Ed|804yp8U{M7Ciz)$FG#P+JRRAoi24GPQ z0E=n?STqHIMNdP*lg*<2$!5_3WV2`i*(_Q} zHj5UK&7#F*vuFt!iw*=}Q6m70ngCeT48WqL04!Ptz@mcyShO5~MJoVUbT9ym4gp}% zN&pre3c#Yn09bT50E<=uu;>T?799z|qN4yJd#M+30v7=W{Ac4BaV2oio)FUuOt zqL=iDc5GsT`lS|~m>8OLfmyVM_GZyZWV7gGvRQNr*(_R1Hj7Rrn?5bPfQE&IMr6c>pXrAAm&{0I=vn02W;Yz@m!*ShNm+MVA1u=u!X{ zT?W9S%K=z)1pte#1Yprs04%y1fJN&8Sab~li>?JYi;hnWHi{tOV*T>a31(52zNfz- zF+u%Oi*8H|oqmy7bQA5(qMONP(Jf@N=vJ~>bQ{?$x}9tm-9a{s?j)N3;>Is1vrbYPYm8Ef`qg5bJsVRMQhZe=ModtFSY2U z#L%nj%%YcRZx+2mHjB2B&7xPyX3=Y8v*>lQS@Z_kEP9h{7QIC_i{2(<(K`SvdKZ92 z?*XvreE=4H0KlRT0a)}A0E<2bV9_T4Ecz6HMV|q%=yL!TeF4CtF9BHe6#$FA24K-P z02X}%z@l#fSo9qLi@pb7(GLJ;(F=*eKSYr5y?VR)MYAZVN3J7_7R8axq9EBUYD31N5CDtf0a%m(z@oMQ zEJ_4mQ4#=)k^xwh0>GkF02ZYIu&5mXi_!sDlmWn^FaV3%1F)zA0E;>Tu&5INiy{Cl z$^>9hX8;y;0XU1cCkBf|knq`hqw#06sJ;FSP1mFZ^-C@4krZmU!Ysw* zn?=3JW>FuqS=5(o7VShfi*_cPMg7QTQGYTP?E=7}T>)4$0DwgU0a%m+z@l6L7Uco3 zC?9}Dg8*1G7=T4X09Z5>fJMUqSTr1fMI!)MG!lSCy8*ChcK{ZR0$|Z-02b{5z@j|? z&Z6!~!4pJ~aF&XbmE^AUU(qloDM9^Gi;9v$*Is2771Q1bhEUExtQ6&J2CIhgj3V=n`04%BjU{Ngqi>3guXet1UrU9^M zIsl7i0I+B;02b{Hz@mKsShOzyi|PPav>yPA>H%0Z6M#jt09Z5|;4B)O6ns_$2@lnS zSfN=oML!wRkd&Z)sYUaXLf@=6i}t6zS#$u|ELuP|ix!g2qD5r0XffF=T0%C94kVjJ zjbyW^iHt?f04!Pxz@lXUEIJ5)MauzLv;u%d2LrI^5C9gf1Ypsj04zETfJKJ`uxJ$k zi;e(b(UAZwItqYAs{vSaGysc^0btRw04zEVfJMgxoJDh!f}O4ri{^9_apsvt6ZJbF zCnP1PUux0GNul8z%%W3hZx*d3n?y17F`O!qRRkSbU6Tvt^i=sl>jWd z3V=md1F&d40E?~xV9~VzEZP9TqU!)ybUnaXv?eLIw+IsMqo2Dz$t>!tCrLLXC8%F& z(Je`#L$5cBZl%3hbQ{?$x}9tm-9a{s?j)N~j{&ggaR3%=0$|Z*02Vy~z@jGsShNLzMNa{+ z=xG2JJp;g^X8~CB8~}@+2Vl_)0B6xnNx@4+knje*xWCyfIz%mcF)2a)Qj4}Gg&w}q zEP9ppX3=Y8v*>lQS@Z_kEP9h{7QIC_i{2)iMemT!qIbz=(R*YpdLMvA9{{lELjV?i z1i+$?0a)}20E<2aV9{p)EczUPMPC50=t}?=eFeaxuK`%J4S+@80I=v=02X}*z@qN~ zSo8w`i+%)P(N6#@+756Qy_^*ML<9*xs$ctf#Vi_;AmQhv1ocZT`aLO>c#B!|2kp(G zKgnj1muy$=W>J7_7R8axq9EBUYC|@QLS(Zjo@^E+kg=#O0E-dx0r6@W$E z09e!=;4JzzDVQUIgwO0P;{0Y7-J~~G7L5fsi?Wl0 z%_2znt!xpeXR^D}U#LnICMT$0YSFml(3y9bMdN927L}6Cq6uWPXd>AxDkGaklgMUK zIoT|#Ae%*%WV2{88H=g_SX2$bq8b1e)dH|+3IL0y0UkQ{pbF0*JM?aiV^WV2{7*(_Q@Hj54s0ASI<04zELfJG|-Sac`=iw*-|(cu6rS_QzOBLG-*Bmj$!0$|Z< z02Un$z@lRSSad7^i;e?e(eVH*Ist%1Cjzi&4ZvBne{#^fTP#|y->^QwEP7sE3!Rjl zpnj=ErzVGb-fI?}Mtig9bh24=2H7k+lWZ29MK+7hCYwd)kj`+OO95DP832ne2Vl_^04%x^fJIjUu;^+47Oe+h(KP@p zx)y*%8vs~z9RQ222Vl_+04%x@fJHX}oJFT32TMed@Mb-sUTYQ|uIEKJCnu<1YSHb< zp}F^)MR(BNEV`3y7TrZQi|!_yMfZ@+qI=0^(S2mI=zg+U^Z?l`dXS7o4*{@fBLIsY z24K-604#bGfJKi1u;_6B7HtAx(PjV^JpsU?CjnTr1%O3Q0kG(402Vz1z@ldXSo9nK zi=GEy(F*`9dJ%v{F9ERVWq`Bj*5u$C5hVP$ejWBUv*;q-F};$Upnj=EuP2ADd(bR; zgZ5_8n`E=-EwWkkHrXtChin$TOE!z%Bb!C#27JUl9 zqR#+W^f>^Fz5rm+mjEpK3V=ml1F&ct0E@l>V9~b#EcyJW27R8gzq6D&8)Rt@(C6djeBr+By1F$FsfJLbQEJ_1lQ9A$@r30`i z1As+g02Z|eU{MDE7Ig$*Q6~TvMF3co3BaPx04(YPz@n}IEb0cpqV51J$^u|f4*(Wr z1Dr*FBnLAe7K^&+{h~k3q94?vo+%0Hms->}B{cF;vuG#Un?*a5&7yu}v#3AWEZT)^ z7VSzliw2O*qJd z04&-KfJM6luxJzji$(*mXb%7u?Fqo5F#s$o0ASHr02UPju&4-tMa2MTQSX%Cz9L9? zmVWNKPl~(J-$UP;ElEjGzto}$DWSt3H;X3H-YhC3n?;kzW>GoWEUF-zMU`Z;XfoL> zsv?_3)nv1%hKxnE04$mUz@n)DESd(uqUiuEngPI~y#QFWHvo(F0btR-04%BlV9|a6 zEUE`!(M$jq%>rQ2YycKD0I+Bd0E^}VuxK6ti{=BcXn%mSXnacWauFo_js7E_rDoB4 z`U4^dq$H?cYSH49(4(8pq9wF9iw-24MU7;$sEKSAHIvPvrDU^c8QCm4h-?-uC!0kp z$XIkR0E-R*V9`nd799$}qQd}KbT|NuRspc+2mlrx3BaPG09dpdfJH|Gu;>^7799(~ zqT>KqbUXlyP5@xhi2y8G1Hht_09bS~0EGSMOOo`XgvUnt^r`twE!&I0KlT_09bTA z0E=z_V9|{LEV>DRMK=Sm=oSDL-3o9Pot6^J6G6fU>F2IbH;c~Jw`OlkNl?GkqPtQ; zlb<$=?xww2bPw4qx|eJg-A6Wy?kAf?50K5G2gzp9Lu9jPBiSr^n2be_0I=v$02Vz4 zz@o+fV1e1l;AQEB>cPHBD&KoT9+i@wUh+)OD%dUC3N<)X3^WU zH;djOn?>)E&7$|nX3_g(v*-h|S@a>PBV9~Dt zEcy+AMZW{E=nsIi=#7-%y&_1sgWh#~(=1xqUc#R#3F?4(T>Q9Ri!N+6p>ZOLX)BH1iTBAZ3YWV0xRY!;=Gu_z6IMeP7sln%h63;-5|0a(-? zfJGeuSkw`KMV$ax6aipSCIE{%1F)zI0E@Z;u&5gVi@F1_C<}l^Jpfpg4ZxzF04(YS zz@pv&XHg(E825r$G(|sZ9hd5^(Z=Y%gx)7LLH$yT`lW_?zhoBmr@ifqb|ITZyOPbK z0c5jiAlWR+A)7_HWV0xbY!>B{&7whMEE){Jq9Fh*8VbOoVE`-|4#1)j04y2_z@ps% zShPC;i$(#kXfyze_5fhfo&YQw1HhsJ02Yk}U{N6ei;4hPR1CnP5&#yB17Oj3fU{_) z)Zlm#Bz%Zo-0y4_ZB~m)QxnuLwP;dmX#Oi^Q913+q6)HER7p0ACX>ygDzaHrO*V^a z$YxP3*({nuHjAc`v1l3qi>3pxXa)d__5xth-T*Ax2Y^NU0d3V=mN0I=vt02Unuz@pUvEIJy1MaKZJ=vV+29S6Xo;{jN7 z0sxCn1Ypq`02ZADz@n1@Sab>ii`D|L=u`j}od$3gElCZ&D1wCN=dPjC!0kVkjtJx)OjzR{^l-Y5*3k2Vl`P04%x|fJGYsSacl#i>?P?(G37Bx)Fdy zHvzEdW&jr50>GkM0a$b!0E=!1V9^}_XVICd!7guzMepgp=q$77ZMEpm)CBcQExI=~ zwEJ6T(S5Wxi|!|zMGuh8q6f)l(L-djXd~GydYEh$Jwi5%9wnPakCCzHaR3%=0$|Z* z02Vy~z@jGsShNLzMNa{+=xG2JJp;g^X8~CB8~}@+2Vl_)04#bDfJH9>u;^s~7QF(% zqOAZddKG|0uK}>=bpRH<0dN-Gof_Ov1PO17h&cC{MNjD4A#bK8s9$Q)yQ!fg-Z6{b zqrF-5KG`h#fNU0hNH&W;BAZ1Ylg*+}$Y#-}WV7fqvRU*w8H>IEV9}QVEcyz7MPCE3 zXd3{Fz5!s-w*V~q4uD191F+}^02ciSz@nc3ShO90MLz?u=obJM{R+UM-vC(jI{=IR z0ASId04(y-?7|$20sv>x+o{1TMUe0h`XSkO%%WBLc1T=Wg8HQv#ixZHf6pvRpuJht zmTVR!lFgzdvRRZ&Hj7foW>G5HEJ`DrMeWFDQ92omG5}Z<24GQp02XxsU{OZ^7Igw( zQ3QZRnE)*648Wo;04(YXz@lydEb0!xqAUOw^#EW|HUNuy0D9u&56Ji~0hv zXeWTPs7+e%3lSu|Oi!poY3@pYuKrZ$&S?qims+%IS}65HvuFVA&7y&1vnYpb7Uh!7 zqCB!$lutH`29eF8!DO>&2-z$eO2(pL04y2~z@iZVEE);GqTK*kv^xNcMgg#BGyseC z0ASIc04y2G7L5g9Q6T_}iU3$t48Woi02Yk{V9|I07L@|9XaWF>CIXyA{nLVj zM3C^S`qtSlX3=S%)kX3-R~Su~Yw z7EL3YMbpV<(F`&c?FGQ1y#ZLX4*-ky1z=Gf0E_kmU{O5)i)I3_XchpAW&^OO0f0qw z09Z5^fJO5FSTrAiMf(G==l}o~EdXHALI4&m0$|Z%02VC)IE%{Dg3Cpau%{m>sxXUo z(RV-&OiNI|)S{(np>sbqi04zEQ zfJG+*u;>&37Oe$f(Ww9|It_qDrvtF)3;-6L32+uQr3LR7LBhTCAl7Uab=6PIo|TrM zeyK(0rG?)9+$=hu_GZxqWV7f(vRQNy*(|!4Y!a%7F_|r zqALMdbQJ)Lt_EPydH@z(1Hhtd0a&yFfJN5MGuk9qK#y;=wY&1^a$B3dX#JyJw`T*9w(bco5*I-W-=B%0l=as0a&yJ zfJILMu;^(37Ci&NqGthE^c(<-o(Evj3ji#75r9Q60kG(002aLhz@n`HEP54yMXv#{ z=yd=Vy#c_YHvw4m766Oh1~`lEOAAgALBj9o=dSNJi)I8RypxuoeyK$tq=gRHW)^)& zd$Z^xvRU*o*(~~mY!-b=Hj6$Zn?;|K&7v>JX3>{qv*;@_7JUuCqHO>y`UZeS-vY4c zI{+4a55S@y09f=R0E>PCV9|B}7X1vsqF(@5^eX_1egk09?*J_N1As+;0E^+EJ`JtMQLQSs2$lXN++8|8Dz64Og4+!ld-4+0E;>Tu&5INiy{Cl$^>9hX8;y; z0bo&A02XxvU{QAf7G(jjs0RRxvH@7s6M#j%09e!;fJJ=(SkxDQMLPkoXlDQx^#fp0 ze}J&vo448~}^P1F)zRfJGAkSTqrUMP&dingqb2a)7gFK)YbK zAH<>zwP>JOl%r?Y73~t#FSV$;U1;=AW>F38&7xYeSu}-g7EL9aMbpS;(R8v|G=ppw z?L{_=_9mM}`;f6{UjP=>0kCL402b8)uxKU#i)I0^Xf^n)X!$o3fh}R2b0aBL&#>)O0rpWDA_DJjBFMiPBx2Hk04zEQfJG+*u;>&37Oe$f z(Ww9|It_qDrvtF)3;-6L3BaPW09bT30E^B6IE$9G3tlaPgcs>S>>#tKUT+?q+b%)< zQj0EZ7ux)*S#%NY&7zCRX3;vbS#$~6EV`6z7F|X*i!LXdMOTo`qAST}(N$zDx*C8* z>j7AF4FHR-1z^zz02W;bz@qB`Sabsbi*5v9(M

    c6D0&dSP_!Jr zQ1lRdp=bqsq3B`wplBroP_zmHC|V5x6s>^(iq=8^MUOxLMe87dqV*6!(FO>h=urru z=rIVOXd?trv~M+6(~{Jplm}JqZC6Jp}<2ZGixawn6|!PeTAj&p^-=-5YNG zfdGkYMy|P7C>qU^q-Vo}nJ=bjTeuniyHNBZ;)SB^@P(q6;0r}B!xxHPfiD!j3STJN z0beM34ZcwHI((sMCwx%!1_V&_CInFQ76efAHUv=g4g^s2E(B2Y9t2Rd3j!#59|9=a z4FMGGfdGm=fB=d@f&hv>h5(B8LI6ddKmbLbLI6ddK>$VjAb_IJA%LPUAZUu7 z54W};KqC9|d$bpXqL=yeMPG&oGha;6*WqTN!3ogkuD?ONP;?N!Q1mT)q3ApKLeU}k zLecl|g`ywe3q^Un6xkqv zqF@M`qOZcO;|P$*UbP6E147XlUZaIX1T$Yukv+n^H%KT7MZ8cH245%&hc6UGz!!=f z@P(pC_(D+?_(D-t_(D-N_(D;2_@KxM0Tj6)fT9`@Kv7Kypr{rEP*fWND5?Vi6h%P* zMbQvIQ49o76bk_q)rA0x>OlZSaS%XJeF&iFG64mMHvu4QCA3{s2c=OlnDV8WkCQ%*$_Zc4g^q?3jq{$ zhoC7+h_KpBqUafZkCrGDE#kMac@e?P7gN+D!n{0KDC&uLp{N&pp{O@}p{Nghq3A03 zLQ!A%LebUmg`#WV3q>CILQy~Xpr{A}DC!RZ6b*m?iUvXeMa2+6(X|jj(I5z*XfOm& zGz0=D8VUgvT?YXa4TAuRhC={FB@jT-2ne8PBm_`&Jp@ox3IP$VN5J1r=2%u;* z1Wi#vgf)`@iM)|NFzEE^Ce4%I} ze4%I(e4%JEe4%Ixe4%J6e4*$T_@HPS1W+^`0w|gR0TkT|0TkT^0Tj)I0E%Wo07bV$ z07Z8|07Z8~07bJQfTFt~fTB4NK+#+XplBWhP;@s0P&6L`C|Upk6fJ}Ritd2`iWWft zMfXC`6pf9r&LKb|pNb`L#tB7!WW9(f)9$`h5(A*fdGo$g#e1)g8+(lK>$VXLjXm) zA%LPi5J1rf5J1s~5J1sK5J1t#5J1sh2%zW_2%zXw2%zXQ2%u;m1W@!j1W@z^1W@!P z1W>de0x0?lf~M%j2y0XrQFJSB5p5TWX7bzE0};W@7gO|Ygn4CzQ1l(*g`z|7g`)4_ z3q?P`7m5zU7mAL+7mAL;7mAL-7m9v_FBBbz4~kAe07WMufTEuufTEuvfTCX@fTB|n zK+$Okpy*c!py)RUpy+o9py&?>pvZ8@vKL7`}WC^?lK!ORy^6z(u@i4=+=5HA!t;0r~O z@P(o(@P(qP@P(pk@P(r4@P#5Le4)q%Unr^p9~9Mu0E%is07bPSfTB7OKv5I~P!tUT z6vaRQMX?Y-QC$e2s2&7R6bAtm)rSCzE`tDyE{6b$8bAO=4IzM{Mi4+zV+f$A2?S6S z4*?W4g#d~YAZUt09oE$ZNTh|o`XkJtSNh-au4AGjnE7IgS~$$ts|rOe5ib}#!f&hx#5I|8f1W=R$0TiV| z07YpKKv6mbP}CU$DCzaXlm!74WkUc(IS@cmE(B229ReuI zg8+*1A%LO+2%4g14(kyDB=Rm^+&34Bw(<-9LPs$3#T4~+m=32<)CciG(N*w;qQ3Bj zqO0KxMc2R=iahXzqJHp&q9XW0QGfVC(E#|MXdnboR15(WT?+ve4T1oQ215WvLm+^n zp%6gPbr3+&FbJS%I0R5s0s$0_fB=d{LI6eALjXmk5I|8G1W;5C0Thjb0E$LK07W-I z07YXUfTFPwG(|lf)>Z^a!xxI)fiD!j3m+7{2LTlAf&hx%hX9IpLjXm4Ab_F| zAb_F|A%LQfAb_HeA%LR25J1r<5J1tV5J1sq5J1sB2%zY52%zW-2%zXo2%u;`1W@!9 z1W?=Tz22t_|2UMM;Y zUnn{PUnn{XUnn{TUnu$!zEE@=zEE@mzEE@$zEJcNd{Fc=1W@z~1WF45ow)AfJBD#uA?JTuk@D?JZAIAVCIV{Y8`1l9w!vFLA+4Z z7QRr_4!%%y1$?2XJ$#|41AL*VBYdIgO87!iC-_2<8$KvXh5(9EAb_G&2%snp0w_v{ z0E#+807YFOfT9ctpr|VZP}B_qD9VHYin1VpqHGADC$VN5J1r=2%u;*1WP_zI7C|U>s6x{;>6fJ@PitdE~iWWlvMfX7f zMN1%nqNNZ((ftrW(J}~{qMIYF*AgI+%gHq-3PsoRNBJL!3}(KJ>PC=Rui~RkEQYfK z&AJVzhyERH1?MDsOA_LIkoG6-&X?$4i$*xVrq7d9bvC9?xVfC1LT%?0^p8kloWIe; zJr8877zNIm?F^%r^PTpF(bws`(lGituXY>8K<9%ghB4TAFwHQA zITN}V#z^O=u7*+W+?r_^W1N;8!x-=E+}$uHI&aT6jH%A|3Jqh1vqmq&nC0~JF^t*H zhx!`EJm+`U7{)?pQjuXScHS_+Fz$CgQ*0Q^oz}sIvC^3_)G*dM?;K_r8=UW#7{(@N zt?LcrNoP@+VLa`8c$8s0@BID-!`SX@KF%;+b&efx7(1QM-DDVVJIzUkvCG+QieY@< zyz3Uj*z4Rg-7xk!>)d7-`<(-38OArxRd*Q1A?M-QhH=E%a;{+Iz;&?Qd~qEv62zxaKaQ9OQ=i53@sqiYL`i@%byjm5>^so37);xEPPWO4Dg znx$G?{IyhFEH3_Dp-hX5zZfRh;^J@iD6qKrs~LJ(T>QWF`&wN5&(Zr?T>Rgy2U=YG z?}-OnT>SrKhgn?w4?;&;T>Kv%%PlVc7ky(aF8&{D<1H@!Cs`9MF8(h^Q!Ot3H#IXX zF8)6wvn($DM-j6vF8)jZc@`J{srEvPi~rVkvBkxIEP21h#eeO#+~VRtS6XRt@!y-Q zwYc~X1~yn+{E6>P78ieH_eqP3KXduC#l;_*d*0&WPd#n7xcFl$uUcIExr3b+7r!`u z+v4Ikf4eL$es%MK#l?H?do3>BJl$t;@$T1ti;K4}zOlG?{dvgZ;swMJi;HJ~$1N^? zg#T=D@fiH8#i;ZZ-6-aAeaqFzj4%va3r9?_Vblx{qmFG}xe6WgPp7uzE&JoW33UPj7r@c6f=zW}}gE(K;Bd4P{6{y^nE5!+| zK~5*_MBh)Dal21%YN1;u*XG!@cGSo8cJn{QUJH^= zR(yE45!-}9RJOe&b_23Kw75%>%J$$=qqQpX8z-N5h^jf-`(Y5)9*qJgT^tDZ=!pfbMM{Fz#u3jJG9pN>ZC zI*L#g{zyWXA+-LL1E^)Fom0n|omGW*EP8MK1QlDa$4VmlQ^bBt2aMn+h~3-lqjFW| z7ase5x~{O%{_3tO_Vpdk8b4m8`s+gvY zkM}g9U!@5ObJ#$~n0CuV8oy)TCOMf=IV9&(^?6I85#6_v4(X+(ppfo#|B=Rxbi3AU zj)lALT*OUm+FPCaZjj3Q*{!>NG52sMe zQvdAQ^2aJCq)! zyl&zAPxaVTWylh%N_pzmgB^`%!>&_qrDIf$N#gQdhh!EVJb09XDVh7ed3Fl*9~Cfc zZ#LgCHpkt^7Ct)8h~6YYOLUNF|8`F2ZmLB(W;EdzF&&@0GN(|5EO>GG+zCeX+miL; z2(fgEq|W$&WYrnR<@`Ioq7CHd3$?>nS_%ruGonY6#+^~4h1}jl)_j@4IXhP0@pH23 zi$|9%d0h9!kI((Sc&rgSj$%|_Orry?YY!c4bG)>55s!1!lg^=a=#fq1@DIN$P2zivcq*EC$wa9{JQ`B*;E!P-rx}v%2X;vu_wY*v)=aG`eQd4(JLs1+oM5C zpHq!AJ@T+ zXSFO=!8Lb$G*|_1*+1hAdT{liDHg|MAZGVBr?>EsZgU*D{n-cUE~d)q~)8A z^=oF(V{JSIab5fBAg;@slFpr4GVPxYc)UpU%-+GB5>zVN=AL+;o6NM&{`PdK5gkQy z6wZ1(LhiZsE`8%ae0a?=zCCS@DHAuZ(an78oX>Bi8><~pY$)rG5oC$rW={@~SadVCN_-;`CSCZntu&-~>s{Q&J6S8coz zJCs6HGmoYNF87T(*5>&7w-@K=o5beXM3tuCTlateyQ-^W*}9Jjsb3{#17hC%V(o); z0cBWg?UoW1^T5U@rt|1*bF6y#`>E77HEF|(>-wS&;$|)dGvWzHj&D-6cp0hh@M6oxAO`l^WNdDja9XO zJ-kZK>rT#n>-!tAw^4{{=lOKN<^EE~+8oR0-@1X@jGo*}mMzuge*KA0 z94a_8e!1I-{y}0~ZKbZ8*RS3|sZ-2}mo`1CW4>$>soVMM)rY>Nk#`fV!MQGtbr9Dj zf+o|PcR!@_^J>L`~8+luT$Gof6bn=p4P0WKedEfT? zcR$dj)H#dRe^y<^Jao&hPbg+8&)O;PHHfiv;&z@zvTEm*a{d)x*<7?)z#$)NDJZ0k z5#5M1Zs)Les@{}!ya2==4QnF@#zQi^|0~i8yi<@5bq4WnkFq2 zvuSH?iV?kyVz}IMbPP9h6s;vV>z7b$`@{8U7^j@~zd3(0--o9CkENSisZ`P?Sg)qR znL@axr;zgp3l4uv-AQ-S^LsY+pb(qm(CWh*DVTcZkIzm$OoOwH);T#8)bt9$;=4_g zR_a^!z2y@tt9)_?oT{f{zM3{^J@rfh#cL&l~1MSPC|i-)^%p@PAcTn ztxLC$F``R(IYrrwL5O|^j3Zff=6pFnPoL)&sK9GU3R$V8ppdpkbam3Wil1oB=GgH1 ziql+0n`7q#Kke1cQnB|)dYV%ecYpuNc6x@_q#)Ium(c;2yJmZhf@AyV&(hdW?Nj%q z_h}A7?X!N>sV6kKAKv-QUaIQ`iOH52`_rzcN2v@yTC?j;t}M-LCNKMuju?T*(r6O) zCdF{ci*yWErU5NjIqL;lvN;~!GVOpS>BCb`AJR|GCCAo$qBCFe(Z;znq>quP*OB=H z^~Vm=wVmU1RPdwSOSwmBc6j{8Mn?2JUK&&8Um!+51{Ra7TKY*j|GTen8+d1c zLLxh;b_ojUL`agxEuE${T3T*ibx6ZB;ktS}ESq-6gok)SVcJu|f^v=6mnlTG^SgAw zm7S<#P5a`FPxYi?S8zPPYCBKQ9(s~RR?i1zb)zfikufEepyj9*xgfi-lbc4+oE;L z)g#+(oZLu@?iktw;Jg!PrA-TU(;l~La}yQw%*Q+SawD7eyQaP0LDlrDx2ugZqTBPf z0p*;I5X(dh4Na*et2XW@=lkpPs$?RK)>2Ri4ar}S#%;VtYc|K}XQwg%MDw1F@4YI| zto{XkRjr@Vexa*bc1cm+)hK&yAm-E8UJzMm1Vl7`w#u_DIL+Yf7gRYsiO&} zwUwMi;181V8suW>#EpECWYx%#b#=jB@fB>cNFQq{C?uKg2hzBa9i61k2Va~rQ;)~< z9{FT0H?qy~#S>d^o1kiaa>sKsY0OwiQL2@f(*d_~mJT=V_2OpnSVu8;Jido!%S6Yj zT?^ml-gbHoSJt%W2H%#cGCaNE(J30jZz>PH(umHa7;fcx zI)+=h1^p=j=lm*?Iq=S{Cv|6K?QE>?!0gOZdYD~1XV3JTjp$hv!<9Xa()RqYe|=Tj z={xRwlrp5!-kZ~u#tMt1oV)Y<`xa6(Q!94F{>;X(jdIof~MSLb<$u-Na@pm;Gbi`806X*Yz8N2uloY zpvFd#tU9xuoS&!9bNyF}v{Fk!A@rc!LK@faW3Aa7Z>|4jnQoJtw{*Wo<(x4phUXFV z(92v^Xv98CA*v@|qXTZw8nip6Hsl_-XW}#(5~y279$wN>)%4)@&!*^_9(!fhDY|1i zU8aLFb&zS_J?<+W{!ROvO}1-x4%~N?M{>%r?vy7lGor7d5bjEk4&kbhtg@bqR3^nV z=S>UK?t1O2rYh&TbH4aY6S(QArB6^Bhg_~>UP8>e-KT1(m>So_#;cmHYrZL8W&Fq3 zIkaaHM-iOyUPM?Tf~bv~kgVFci=6*ipXY)lH_##W6xAj{A*u9qCym?qO0CfXvcFC5 zuq?gr=`ZzAywzAfTIJm1Xv*bAY%dB?Z9I?;xQ!?7j+0% zCA*={`XsWRUt_05Wj%Y%9dB`0nf407$-Km)HBGn2(~amQ64EGD)!wvke6C3!74r1f zg>)-3`>QwY+^$EZ>4mS;jk<+mIA=FvEE5fCb=?tomm5_G$dY*iS)R-6lGSt8=Ka&bO~pM< zAza0#ouzqtzcHWEq-^%Q_V6AWl8B0}rlXAt$vXK!A0s+4L6Y116fQ$VVf=BnhXQ&G9vep@;g4f+Qlj}~6+-k)=jcL}Fs6$*`q^3i^Z=fHJhws{T zOgHGR9+9-sLLs&0UQ@-0?n5EmFO78w*JP8Vay3$EaN2R1%J``rG1sf+N}hD=N|ne< zp-)nCRY=nL-iZkF+jnSzPfyF8kAF=M6Po&bF!dz&BTW!)?2trLQi|YgS0F-<7BHKryO;`_Tb6aAyR6^W&n2sF4VzsOF=1gTl1uAFIt=*c=aS{c%0b72lPZaXQ9y zEZ+2-TZJ5pcv6SNj6LX7A#XkY$1=k22!(J}Z`UE*!d;u|oL@lBI}X1vNf-ObGdp=% zKv`dXq!F#ysKwTIfA}gRdXdDOK+NmEZatw(TP5;SlS1gV+m^Q{lSDD^w4e_WL~o`T z&f4Bpc+j)>XGvDA{E?h*pwFwKwa_8$wGf$0Lq7^pjXaDFxRD=0?DwD6rYos~R&2cG749IL_dj`pT3=s;-XTzM9K-tj%$9@$)jjtQOUjCM7Fc>VhBFFN=oWHy!fGcAJY9X%xbZe7)pi*R%MWNLG!!NY3A`&vU^lwbmiav=kJQYed&3jT`xW zWNrz*Bj{tTMWghR&GKE+{%&kt5$gTKJ*4Xr>K=* z{@^|JCf4TI`|;85G#p)v*EOU8OJcg{7M#icC_o;6O6i*=uJP*<5dNF_UutfmG$)8&%UP2 zC=ZLhaj?qc@Qb&v9B&x)LTMqzzqTN&tzJ|mdNoeJw))me^=gsIzcwqK*&S*a{A)WJ zWUCizHw^x@eM3$(?KknS?Ok$)h8qU|+DwY+O9%XGt6;Sm7Kf#NSe44wuv%e-PKSl} z4};>2%9T5kM6dX(8`iLPm9MDWwsJ-l`ZS81389ZSv@}?;Rj^pYI##Ysr}bqP5`!C1 zRBd{T6`~GI!>FhZY=%)u5;S#!l`WQxDjZ^urQ{MQBs82d=aj>$SSnZcr5PS-SVK^f z%9TSa+bg%B%OjitS2^e^zw$(XP|n$< z4ybN5TKMI8WsUaK<~5sIuB?HATwWuiio+6V>*QLHT!ZtiW%>mKIiEhN`$rkFvB-M&Bw@tPfL9V-!X~!~_P8fW`FzVtO;;N~^MJx$ZrK2kH zr!M?{rqZ#+$YoQLHvK9XKU#8^@=*+L0UEh%_){zTgkNC5VJGq|Mt3&Tg7~l(8zk6W zCD=tJ*qzPqbVG51-Iwx_`cRC~i(=3Gu~T$T(kR9HlB&$OakbtBlvGj0@Qy z<9xr23(u7+Cm&?orLu{WW42tiAY+2Ek5Qt04ckNNc!ILrn5>`cN7AmqR?@EEmv#lt zL(;C`mv#ltL(;Brp0q>!(hl)UJH#*T5WloT{L-d@=IlRGZo6OFcE7akerenN(zg4h zO#|iGeOCdp)(_x`h8C4ysjiqVRgwmpfYs*F^ zl$8!hDD{*LDE5pj9Z_C9puBis!hq7TBg;pyFrawgsM6vxzjJ&&UEMZeWa*IML&}GY zE;bSdj~HH@P&BM~OhVIPBL)-=ODG#$R9c)+T3k|GR#cWy+{{x}K5F2Q5eelZMhqJ; zxM)a8S;C+J13X2g!xNGcJs zRKk#w0mDWOEKV3+G+^+MlK*%y%Ep%Yx5S{q3GUK?qlT1>NEuOD9Pe$5G3BMINpy?k zmW~)oZC;j;KeDLwy7W;co&u`Npxj}j$~<}QR#`34O;p)`Vd{Seg3(3g#oQN$As7|6 zY&w8OWWzJC_}ZdT!^%D7V@DR3H66_C5(oo_l$4WWH4MVfGhoE<;Uh{sMI(ohMp);k zq>ERW;L6|v{Y^sk!tTki2 zM@>!B*2#>tS@@uXS%oe)Z3!%p?Pvs5uv9ZEvk5n2*^sVWzPuS-UfrzO$c(ISR;gvi zUT#*gj^z^xk`B`AVAiC#DlvYikVWG8vS>_^k@d_fbyP5wD+x!{8tVjgSrcqk&B!Re z$X3OSjOK%GQjKoj;zUtmAx+JSHfv~m(@9Q6TQ{>h+4^QUrLal&r0K5%VEvT zCUmir4-?J$9IvjZXP!Gi=aTs^y1GiVS-+X-Y(xc0kP0QJ3ROhsox5Z;xcuErX9fo+ zAdCcR!0ME4oLT*!l5Rjd*E6fvQHAAJzkos_`0VztH7i$5cX^<_&{V41oY6_9lNo1j z0u%B1x@KrkZR5_UcOYkR{+z{7;?1NFJ9snEiE3CY+Wta`O=rV%mNw3dj!wRVWLuZZ zQw>lDl&-0%+!%e58-g(5R;7AIlb6t2(m;D8n04v2y{Q?hZn|3Jgi_=2fDlUcXvkJo zKgq1ZHr#9|t)X0wYi8E5S-P3EqUkt+k2?e&$3r)3CL|=rn+@ujwXEY}l&bSdko?ZH z(hZVv1OJRUyqSdQ@hjBU(QM!?Zcs`!6!;&+>FVnEhIP%FO(@mCOwV3hvlhkBJ=rkP ztW`@@M5pwRD{z*y5~;wobW@-#fwrSx7tk-&8j$(#_Y}Okn9X_&F#3@QeouU+#y?CFynX)KtYS!T+&25m)VzWk2O{vH} zt~KA(c{QU*J#U9|CpD}e*we(gN)lF{#s8>-s+m!7EfTqjYgtRE6))r4z}F+8^nCYE zGm35#zt*=_;zs`;ZT_0Js)_M&@rhh~UpIK~7MqKx`^O^!O&`?V>5b_?y?2&Q^`*{t zbrmx-R^sTmrW&DCV3h>!c?=wMjY_Jn-vHvh+0H(EB=D%laa9s{(BNWK#Q~$ng3i62 zcuG~7|LH;mu>HST?4XY48Ls~g?R`c^4N{$ZahSBHj#N*lR)lq8V)Fz&&@wMo>++zC zC#)A|I^$2l#p`+qNigFmJsS8TZPs}ex~hjr^BA*QQx;a7DNH+4xGO+#*fIz4U>_SV z!+sUBNnJCl4tcTi5RfU!IUWMk78Fj8{wDRzsM>yEc!vBN!p-PJGb-MU|5FK~si7Qr z2uKCu=?TJXDdje$)6LA5g+LcLCjapO*AaF5-H=`*kmfKaZ(4B##0;d*d>6BP%&pVwx3#anx_$vw<&_0LBm8-inf19J zEz-2~NNUCR{CO+%Z@S(QYqpB!9_)=CB<2I|lnd%a|KUv!m47{r|3f33ny8r3G`ckL zj!E%x`ticZ)A)y3%mqF6`3Vzs(Sux2Dvh<5hPg|_T;PaK7&3%}6+esrn+C1FI*57) zIqSw@L2;HxWDen*h4EeZm&ZA78h#Y~Tc>fVLpWClZ6xx01m2Lc*y`y;K)8A4&X!)( z_(gS7Wp>coPN(9t7dC#z>b8DO_AVFEomuvrU@+Gbd1v zX6K$gITFp*d?)$eX_(TYzUYxmGyc#0dyeHrR0lnWy4cl$x5Ic2dO^3knkh9q_q^%s zHND6&g-Uhdv!;LD#g2r4$r9lHO9O!aOzEN$_`B02Z&wG7AVF!>{+q@S9+7cF{FNur z|LvjUFAf?1oOPGCr!I{h{O0j2Phho*4jel!c9HZSA3hW_0jq`cE@kPS{EzG-sa2NW zel9i>U@xfPe|_gsR_=~-Y@+aK+CO7O7i)f_t+$8577XC-~R?k!4a}Ems?VAokDOJx0 z2&#^~RWsE3TzIcR^1+Er9e(!D3t3v45!QJ_+S6w%4^?j(!$X60>&TFpL6`O{F6~)V zu<(?jnR>VL-?e9PY2iWhHudtyuZJ#eS}0o8%Zb1F_L>sHZh-&BUQqgZp3{DD*jD?q z{ikhwUfQ%!Z%_T+7N30=(7(ayV>^FspHoe}{`SjaFBq3LEiP?ZoNdqMKe}mQHt~BI z%%5(jLgAJ&?cnnW;11xc-fa z$3=`5|DG}Cyt}hlW&htEVS>6;JMYKU{@b@yF1V}xHdNjlRjxNw8q_sw{rL}M&iH$X z2e8RMT>5N=_YdYS z=;QHcJoEnpH~7EgCgI7%**~)NuO1fuGsECH2ZjIdHWGqzt6$m%xU>y$-rI~vfWP~9 z9hcs7QX^jaj6}G3j@j|w{otl|trz%*9hbHN{;U4F>(VIjzcLD3+6M5wmBh0A&sKky z2l_>=68_si?QlV}1NuK4=h{`c(9b#q71IB=hH^&oO8f9@16R$wg)cw<5A}=1}`W62?NGo8g>5{hl_vregpj{ zl=FSSPP*=*{{@9v(fa%_`sf1xpN( zfUYde&XDWUQ@VKi`!00nrFyb+3h3hew7i0}RPULtxs+&Oc79=QZVsRDJ>B-H>$Sz2eDmRns-DK&X zxHoU+DOWW}4G2%pr2pWam#(@YE!$0Qs*#hP?{TN~cIoY* zzRsdvPH`7xS5O7V-#$m{M&CdN`T@^xltOPwSqrn=3OnUUSi+iE>C(lb2n zTvf`Hob2qh6sARym)?RKOdX~Q68VKGDMYC^8pw7pOe;+Dq*F_IPvyGvG75ToU4}Z# zo!wiy&X-3b&ZmPJ=Tj)EdrOHudo(M_ZOiChz zrLWq^$s}q%Z)zDCdFgIXT1tv1DLF%K^Ar`GGpanbsJzINUtBu6xHQY1(ye%G&dB1@ zqVgdlN>WA)EcT{>+kr^UFW*-685rAJB>1^}agkJISwCsEcz739MczX=$l`Z6Pg9V|Rg@#-46zy*=sf z3?4s_uw21k5jNR$9Qr!mrLmNk+PE6kUQ=ez~X-jeDKPPW7CWQU(Bt;l$%kNh!>8r^w*w zEl(GEg7$P%MGG>r(x{hI8g0Dzr1)i+OMR4|mqLKLQwlPA=%-mLzlSJpcY5r1&Q_0n zg+g<>gb&;Sj}8AZ$2S%xrFnaf552{dMxnl^(W6ivq*P4b1(a!Wo|`5Mf)M9Oz2kpx zQd40d&&@-n^JFf%yUjUB}b6>27h%Ure?T1 zds0$zJY8te^9G=8vT{;&>1jUUJ(-f0nOT_W&LhY>XXF#l{18M%KotfPUB*NTS5*vn z92Dj!tBHUozYEQJ^p!MFV#xH%GAoVBDbpe3#OWo`_^ad66i1^<{HxDb&~wFG@YH6h z^03WI%T6U){YG|g2dAiMl`uoCSTd;CQ(Q7|NKuK0?rOd$ZAvpy$%++?QasDaeeBPX+frgi9J-6b^0NLMB$$>Wcv1KtM2y`Jbv?OxzX z?V@J{fzyXpe%H%5l|>^_VV-)XDf}qGUjE+L)2Uh71@|?#&E9 zXS#dy4E2o1x^BO`w3IX&D7-x?!-j{)^J_Xl@xz-pC!u`ssNwy|UOQ|=QF%OlgH;C_CI+%VS6(}E zbj$d%k?{kQT9HyzI$&@I`bw+OZQ_SF9Zp}0)p%gp$i~->jENr<6Q9#8CZ4`4slxy& zK>W4Ci_6N21{KE-D=rySKDa|7N%}U7XPC(2*5jE=d>MV46xlM;2Gab->#HiZ4nS1l zp`SmzSWtbPmYq{bqZDRGDZ_>omz1ZK4EWRRh`Jb^*0Qbcw7_M6_n}8KNq2HaW=0>G z%B#SFVP&1^+renMRh&1uTPQ^ zn@cUcgFW?*H&I`k@x;?34W}dMsjLo&6)n(6={GQdk0)w}9$ zC8_B3CUVseinOd;zeQvUZ)^BJmbl#hYv3+DY3C%R8;#MrMgcbtZUCMQd0QQ#{{sIX zEG5%3(sKgWxju$c-6`s8+Y0Dw-n{91$Lv4fA++qLM!Sx05bx!>)`i*b9>hN{50m!$| z)ays&$qagNhnSz6;gNj+P6q2%w>LF{W0FCW-#!F`$3x#g=-a1BqS-rTpcX9NRSOc}(aaw)=l~_%ol2WZ zXFS#w1e|MUV%<9_@~yULEYuB23l&t2TESatOuzl1R}G({nhIs$vYqklcjxm4pLcJF z?jdiY-u0h5S#9-sPxv)tURuFf=jm!Z^q*_#HJ&OHO_it)C=;zxX(^bIlA#_sxo&#m zsH^C?p%3W(47gnHex`JxWqDerx`bBc-sHUZOL|XFA#J}=V@iUO9&Nr+a`a%%EH05Y z^?`$H{91vx9P)X1^x?_nJL}vSeH^f_7%)xuPW!RY)$1}ehO}(p4T>&P%|f#)U20nW z`85ka`*;cD$?us_Kxh0Oq*x{<`8F?-Xn;1#2Ge}YyWr+Up~`@s&FX*`fh_2?nmXlo zU(qDp*W|pbtX5|{SD{S_PiJ?A-fJZMyqBSIXz@{)>6>>j^_baU+zs4f^KCvg!{!sO zB++I_muDfyP&FEIX?Y=sOZ->!HD-F_8)s0%bXx1tve=WJ>CX4X;cQ_pv(Ebs*wa5_N#^aQ zl=Ku|7bWr5I&zX-6#djxeXidN@S*?qx>_@yF_QS^m8ogxm|1dP_fFI6XDl28M+4>< zs~b$=R5^IBTpj2)09o!{o|NnYdA#rjxSq86&xc3#=ZP??ri%RMhp1lq;Ue$;p~}j) z!=6Ojeg1cw-i_p$J2!&9PXdN1?}h=V=q-akhu#&pw7J^+R@u@$BbKt%1@S)cc$ujr z-quB_)nl2MAf8j`PCV;-7CpoAJ+cA@A}mw%Chl36DFi?g))Ps*M~uw<>y)06Npm~@ z%?jV_COQRu#Z0It=Q>Xhjc4a>xtEjBJxHP|b zKxuLL87s%L?W=RS{T5fWt)$4%%ce83L)B@ZrN^NxA>^$SR%NXN5Jv>fi0P(DrMZyb zBncF~|UstFm3B-%G(CO8qdM%_*^CAk__|0PiwvSZtlH~cvODrYumaRI_+sb^1MOBjj zZmp!suN>0pR>W?ZbaH<2Fi*;mk%OtDM-3_W&GRwGQaMmpcnhg+ZhB@Gxbt{YO7|B{ zfX;D~C;4qKOYxKR?l32-S8=F3z4(whl$zM!-G|EG?};EcgPwGGH(6;Ukg*AiFTB%C z(tE=y8QzMOYU>S)>qilv*2@rNnX4a0wBzV)2gMGJLtY^zD>Yz& zOOT@=`jL;gJ7P|wS=t(ch|h7YSiP9EP&%e?~;zp#}%5=rH{)J<_m4`@rsOzgIC;7`3aP3nFDIiHJL(9du-=39c(5=>!hVB#m%MJ& zf%^8$AQ*hRfj!-{_Q#NWMkH@J@#9&yncBuxHQ^mi@1=OLq*j@o^LR~vMw17uYnd^1 zZ}7qkiJ)jH?i6b2bdQ=|7@R#m;(@go(6w$)P3FPg zIYkmpajDX{lm;KnBm$Rh>9m!J6%T*T#OR!o(k`X}zjbhz4v$G2-oJR@Kzh$uFk-|o z+T|ZoqFzMA^J|EvNr?^5{aV7X8;0=*{aB2k@nQB*BaVFhbZToDsbLMKRGM1xmXK+| z(`_@%TPxgVof&k8#cXZ@uL#?e1~XAHw?_@8Az$p19?)-(JHMreRi!H6I~(|egd zzthj>^T%xn(&vW-`+Pn>rjpO+^dlD86>y-e)$oEPe#jZ;E1uzd!IJAa zH{Xxd@Pea6tKsmSq$8{01xL<%!4kikx`OX2zP}@l3Wm2SNaMP6qF?;5pAUyD`$cE? zBhK(AoZ(M7!@u_of7KbjQR*ohQ0y70J|`4cZo~~d%g#sOn?S#JTZzV5J}2NmmrC-R zOC|CPNpCQ}Q`WDI&b8CxyH>q6^G5P3HDfW=qY|}g18Uq#?F^$G+bayCBir_dF;w*N zqEBSo!7$d*kj8Nb*izgvvA>J8(^$oNF4>@tbYA?0Ch3&^VzyTjlj83ZKaSAj^9|V2 z`2z8KiN8|(wc>vu{$BA{&=|<^tJzZgZt*`7{{UMm_ew&V?RG+$%ej+nC&Tzg{9ZJ6 zvObh8rB}k1+M_z5&T+|X>HJ8s`$Yd${9g2s;_Ehu-N}}&-^G^lIU;^Px>Z;&WlQ;t zW=r`@W=rwwT)_+9DNV*dfQ6n|3ussue>Uz;uE*GBvmVxMG7*FVjc z@_UsnrISauCfhM=DgHI_Ytk*rdMmc1cVtWH_7OjqZeiB@v!!&eWlQOnvZc76#a6GX zuN%ph^ykIy6@5QjO4p!g2d6hu>}0l-?liWP?i{uh|E<^!^lahl?M|%^6g!bE=`+|; zy356{>eBjUY$@GFY$@GVY$@Fb#6HWG;%nB>`boBQeNauZZsMCQU0=eMt{csk@|h#P zQA_KQY$>ifTgs;{TZ&sN_BFN?A6HxJEC4C`VN_Ug^Yw20X`m=1WFpO<%+Z)E4 zY$@G>C~ZsG(setJ~ z>+5Q=rF>e6zg+BQwiLI8E#>nvTS~9}W!m;(OZjXPzry8Ok6}xC1GbcIs`wonXg!xL zrCY$3((T8V(tTI#5w;ZHwV~D*iQUYW^k>;px*v((wUO5QvZZwUv88l}v88mki`~bT z;=gIE^-fK+?aP+*fov(=iQ*p-8x&7ErE6nL=|-}pbZ-*7h%LpR6hE8hAbkB1wsc)s zf<9lJEv4T~{QJc|#+I(%%$CyM#+KsRBx>7(Ev3Ifd?QKgwb_y$$ClFVB!0VQTF+!l z>E^Pfbo;WUbl((vh%LpZH`n@nv5&DOeG6MkcenWIEwtW?Ev4I+Eu}k{Ev36p>;o(H;cVR>`bwDiCrM}KCusqT_twC z*vG|g75jqNSH!+4_ItBS29wyxNQViU!-7TZy5 zn%GRS`C|KsEfPCe>x zekPXZryT#i*yCbPiw&~s^A*KLh;@pM5?fzv6S2+3wiD|X+eK`S*dAi97CTVvbz)1! zjuksm>~yhrh`n3vVzCd3T`l%eu}_M9PVCEK-w?Y??8joi5PMMU5wSms{avhCLAR4# zY!$IJ#m0(lAT~j4E3qBKri$$*HcxDCvHipj5?dm6l-TiNr-;2x>|J6Pid`yph1f^L zZW6my>^8AG#J(+dkJwMeekJyh*dN875^FJa`-F%M7h7Fy9kFp@1F@fr{Z{OcVt*BD(gTa{t1z)n zu`yyBiftzL3bCnTv&8lg>k&Ix?Db;DiJc;Lme{++E)n~%*bQQz61z?8>tc6_{Y2~m zv4_R}EY=dN>sLu^Rk6**cCM(;=ZhUe>ppIeQDSF?YJY*)N5ZxLl-RfE0ngWeEcR#> z?f)jWRdwyBh#gPs5WfCavD<2D|1Gg0H1Fs0)x>7ge4YKP#LkP={xY#2)zkjhVq-4T ze!SRgX@bG=Wn$OT{FD8s#2%yhCHsGfZ9@|g_S3}Pl%)NcVz<+rh0nhuwh~QP*msJ} zrTGy1SBsrbb0zj46uXz^RO}xVTlY%sCx{*F*8V85>r%A8RqXLJ?OW2dZP!Ix`Y^ak zcVbs1E!KXq*d<|n$l06BL ztVJYbX+cVsP{}$<+@H@}?^n0)@At=jdp!7@_sd*oj+rNBQ~sH%bJ|*e&((Q&y}y6d znR%nX^XY86$=}cGT)f%eYjj>TZ|K{X&rO{rw)?xP&cQqU{i4n-JN>;+=Y!q;j@{#* zb@%ya3!Sfg>F;?uj~wv#8J$@V`MZG5_J{r5OXqt>{Jl=++h#^zJAZ&3w0hh?_k;2=g&HGKJa%D zot@0*tnAPC)43wj-y3ya3;Fw=&T{4*H2d^5b&iPk_Y|EwV*PzkXDGqn8Fe;J^!Kwm zXNLX#w$788{e50%?ri=prn8HAN6CuaoQ7gzN9`|d!Eik>K|yY*117_ zyY^0<`_zx={7L6Eo%eJ`nNPCXUw&#o) zfBK?2+v^;n^A(*-bZ*vpQ0D`kZW;f6s_Lw*bC}L?IydP2ROjzH@8~RUK2TvFe+8XA zbPmw@p3YS|&*}`9^RFwWvz*R)I@{=cUFSTVU+Fxf^SaK0<^B7sth2AqcXfWE^K+fY zbY9e%vx0wp0iDn4?5%UG&UHF>>%610SVjN(jyi|w9H(=Z&gDA4)A_T`ES3E08|&<# zbEeLHI#27opfgQpTxI|InmQZm9HVoC&b>O*be62*UsqRWQ=Of34%PX-&h$^P}ZbT-pDQRiHp2Xx-o zS*DhMT^F4rbxzbdSLaHdr*&S?nX|TkeN&yCbk5QFh0ZfNFY3IfGv0jQ)4tr2bvDvD zPUi-ldv)H`S-h@)U2UByIy>qdtaF9VbviHT%vsOBzNF4BI^Wc}M&~Cw59mCjGqJvZ zeGZ*XbxzPZN9O^Z_jQ(T;9pl?XR6LFI*050Q0GRS7j@=n=wDw#XGfhgb-u52z0N&4 zPw9+p^5_jI1r`IF8}P5kQ{>1?larp~=OZ`;%SeSJ@7WK(}f>CB)rlg`{alXMo-SyE>u zoz-;K(b+&}bDgbpdJ*RBSK~TPXC|H5bmr4pNM{M1=1sBm>ze6&N@p9L9dvfnY2JNK zfBL~XhwB`x)4aQy{`0TuoS}2A&X06%)%lsuy*l^nJf`!c&NDiH)@j~NNPj+m>b#@# zZ=Iol|MQ;CB07ufG=JTvUvK`}OFzvYtLdltVAbHqWIvv7Ja{@2b*6v5!}Q$R zNji(_ETOZ4&MG=v>1?gDlg@5B`|2F1bA-+@I@3STVV>_a?U_2~=v=S!W1Z=r*Dz1N zQ+vP8LpqP^{7&aNoxke5rt`W^`}H^W<&pmR40C4J&aJbc&Z0WY=&Ydg37yG0(?73a z?x%@%7o9zH_Sc#I`3&=PqqN8ATM&eb~C>)fU@{qq*)`meMP>pZFR2b~vmrhneT zJpC>0G@a&4#L|ELA)V=;w=hqasBJ#X8xdK`|JpG7a(Z;VJD}^Mv-4p4AD7WH@}J`WE`59T@6J7%M;cM8 z>wtd!%zyRb(L3rfxN|@AM75r3TB`HVp@VyM88+11?f>6zxy%!q--hX*!?xF$zZU-I zn|V>Df6Hfnv`=SVMd{!E&!@9LXTKFO-|e68|6fmM|1AGMpRfJ;K)%`6rTu3A?2k6z zlg)Sgt!LKAh-t3*S{!rRK8^iupP&6ZfX85NMhrFg)xrFI!#8d{ZNj7Xcm1)*h%!0+ z`?IdNzwYKX*Vy|wIyDdxoPCWv`h1hjCux(-)7f8# z?L6P9k6dGJM%`PSqpRzgE)TU#$7g{mnPGxyIa#$oyI${psv& z`;DKQYi>V!e*+)6Kl5pj|L$+qBiERl5e3ctP3>rJ`QNy|_sx9t{>Gd8v#%%n_%fL9 zJig85w!OxBu-`ts8i*)b$iHoWv_EIR@7BrF9ZQUiXlxqac)D*)u($b^J7Z)-6^1$O z^R?d&n(vQ3zG;vAdhOdIJU;UwMQeGWInuwiGWS=FVNRZxJs;r_G1ELQ)r@yv-Z`!rR=KD=~#dTV^}eCNGsM<$%_ z)h;sPuL6@&Z?zpXJLT2JdQ@eO=~q#_=Wg>@r!;2wN#7Ix+pE&|*#CCxd{=vpY+|pO zkh0tS3U{ZS`|l-kG08sf$@NF4jA=Zk(OCPd+GUIVo^s<{9rMV`v@S5B@lR>XCYakv z=CPC=U|y!@%6z9szS}3qT?MUK& z^V;BX7w=^sQ=jx7SEc`WHT}nC|2^{Jz0;o}{l``5KVD7$vHt)26n#=}RY?D}_31OP zpnd99eOflO=hZ$>G_q&I8|4e^PP?|#d`~vN@`y~GVtc+7xPLtL*3S0HH@Z|vy*@s< z;f+m0$~N9*UK_j8LbZ0K9f{cW=;Q30oPJMz`W8)pPOJLb`>lN=Q-RC&R$zD9-o#9u z3iMnM*mESNTUZ%Ns+Lwqqjf*2K{MT>(iN@3r`|>re($5S9 z#^<*?^;Y&wiH(Yy>#i9q*P0hLPR=D2ZhXFT;gtWqpX3`)mCJN%e1_yZQ-bC-ldtBv zh{UYP@i`Nc>~EHHuSQha`E5kv_`Z4CT|GRs=-gjlIhh;?jb9uLj6d^hmAn@&zgzA7 zGO7K)9MUJhv$$}eTlT}J=N~Ke+58e8&i!}qxz*+mk>t%U*|!9zkFOUuGor_(HJ_b3 z-?H+__2*xxv?u=dtQLR%JnQD&)O+hLjvUwXz}@lYem6I@zu%It*O_oaK0a<}A9Jw& z#)kXMOU=K%;gQ?x{<|Hjzb0i(}+LCT4DPPKsB=g$IP+&=8^ZJW0-xEJDuZwf$ z<(;YLeE+rBJo$!OV1A<`o$YIOfm+Y}@21RYvcI!=edgQsi1!8QkH);-hnd&V;D&cz z3chMyx)A~M(raN}H^%qgGDr2u%lDjYOhl9&($oI9G5yDz=|3X4M8T9Bof>UN0S&a%1N+$#{~FqI>Fv!%!?nb2R?y;Z=GS*^{n9(Xb~Pt|N{u(SJDKn4F74~2_MN2k z-|NYD`eaJIo@)QZGWXTG&eGfYGPP>_bfc&3eT`pw<8ym2|8r&Yl;(|FG-~0$T<=VY zO1_gXqV}B(!Dfvrm`AkNK5c~k6R&`IjV;n^r}hmuSW>Ss{a!S$#e@Py8}IL&(y3+7 zHWBwv*w^Z@w1|uanpEv%&yndrZtdj%PD}s&`%I;jN{uTws@(8mXZveNE|A?k$L(cj z_xdq(|9H{*pIuIyfx^;KSn5A*!TK25*i9=+(bhM7Qoe_hf!*`WMAFyUxVfcfUW`-MkAtX}tLxY`poYh$M3c`kKGI z`g#%1KiT}9Z+0x(5~|s<_rnIqYc5%qX>b0jb-TqMET5@mz6J$~6&ObQ6l=#L8jS}<}uAbtwd5YgJMSOnyQkLG!XZ5{MsK(cgYA*`y zvcJAa^EdBnTi;uLXYSC=3-jdruu@u`7q6Mm8~AUpgaTX42TS5An;$yZw$%H0$8Z6LRNX7j3WJD9g&B26?Gx#vv@xd+Sxb==G5?V2bz);wC* zU1;v!bKf#O+AVILKE~~5?jhE#ZQdl0b6-h{h=_NO#+WZva*yUQZ#cR`&5wz0L-Ujw z-IT}7mqfdB&95_)yV5*OX17v;`63$EetCRWw{ULr#+UnS0rT#k`;2)nCx?5-ykK&= z(Wd8ezcVkz-0mgwlzH4j<}u`TYnqbeer29xKDUy2F8ST2=H3dpwat5v1>N1|b|LqK zxwmfaEb~I`?sh0>{^5nY&fMDp_r7_|U%8K)cR>%jkzw-%`|ii)*ZZ}5%RJ>_ubH`B zBH$G=&#Yv?TVbB6RKPo8o~(4h>th~SnSfW*95Vyn67v$D74UYN2Rb|8O*b#QIcAv` z*W7?-{}Ifa0dJdmvCRv3`^>$(74RN6&tQJQ>ui2*LBOkP9@4^qH_|+#TLJHFbKDMi z)s3J#0WZp|y8&;Md1<8uysYLI(mK*xX`a#cNUwo;ESH1c1M}MdE$B^&HUBar=&dpL zc{S+eFyyWUy_@Fc@_W#`V_ryq1if44rSWIbTV&K+4|>_nbNDOhO*hY>NywXK?z(Bn zvma|{7V^fK*M4fqt7Y!2dB|&K?xjV@>tvqaQ|9N)(K6(fG|#V9$g>~Rcsk^@Ge(~Y zdELzG_Suj(+yHAG^3sfkHX(0~xwEz*Z>D*Fq+Q7CXI^dXLtZgsXMMMW4%n~6}K(cv;WF-aR#ru zQM4q3m&3et-^<`FF%M~J2CtQQbu7!^l{fdfJcGB?+~?&we@Kz--=D^H>ID^QxOiHaMF%&pg{9*}RM9DTikB)|waAux#Gf=2bO3 zn>W}zhZnMW@0j0BBeHp`%u8@&HgCMqI?7ybUh<=}c`MCJVoWwKi+P2Q&E`!sFWqt3 zyhQU-dNG@K$vnyUY+fGo942J*V$8iHFY>yXXIpELch%fk?L}T4^H}OG@(P%Hskg|p z|30k#A}`jw1RE^!+L)I_^F3a&`MDN*yfx-NJ6-Xj%yZ~`#p`4qZkH>b{XkULE8ZUS z9J*ccPMHVM{fgJb{2F>(@m@5~@A)gykC_+Nz>I;2=)&f=&>(vw)?7Q--Z*bw?L+L1 z-sbwD_C_wlaG1TZ)Vvsn+Z&&mdl_#&try+UyhJD18z;;QWum>2)%<3hWN#cbudB)S zhW&S9Q|ygP=831;8yC%EdCA^LGB34R&zT#O&9C?kdt-)qw6pDvw&oW&$KLqY{JQ7b z8?()`7}?d_*kNAbqwEdO+>d?#EBc{%9R}=;Ugp#+#Da-pFHq$yw};Xmgc) z)Y0Y5tH69pAtHK(dGL|;#w7DB>_4TBUSWO{hU^XV>odO!bHjc$bdK_O$Ham8P`Js$?oyLtZH}aal1EUU^=Nuoh zJt5>2c4`=78ETh_aEfGIXj&+c*UYjJPEpM~W|oU^ifKM(X88!`an0OjR)}zlYvwYu zVuVvdGpCuABAk+%In1ma;gr(MZf2DTr?h4^Gpj~8Wi+#zS=KzPvf5efHjk^Ec4oWH z11qnc$!_z=Drkr8HV>_$c1F9+W2>Z{Xt#NAm9;b2Z5~|}?F75c!>g(tZ?}1T)wJWx zE@vKJb?sQY&EtDQJH~GF_-bfJ+if1-liHr$=JD0kcI`HgFIhXvZu9tRX*+hC$5&fB zWVd;Ib+paDLatrTJifZxk!F`SkFTC~z;5&S>T8?Vbz;aV7<|sW{xe=PoSZ_LEr5*w z8vITJw}wGug`_yo8Di-|n&?sqX{sq9%`_z>RZ~KmYf4B9O$m8QQ$kv5N=PeB33*x* zA7*|XGC><56SWaCNgE-PwGlE!8zED*5%Q8YLZ)dWYe` z+6ehr8zGyteIc`h`^@VDhUA;+~5azYy+C$$lBN*f{HX(Qx&ZG`-w z?F-owykuVg8OxhDVx6tNkSgZQU*|{H%CSOzaxR%SqSJ+()1?yfv!;anqA4NgH6`R% zO$oW6DIpg%CFGK(gk08?kl!>Bazz^DAJAvd%U za#I^2x3m#*TN@#Fv=MSw8zE`h2)U8ZZC}WlV2pY1 zF5_2L#o2Tr;bZo;`6!yD6Ok$8gaYOr5%V6GeQ(AI=<2*?n>Tx-*m=x0Z;+Y=e1-83~zeFpn`z2-{#DWF|sJ8_c83Oh~lBJj^VF3^tg@nU#=WgL$CY z2=O+UN1B}wXM%kXCkG+c2J=XB5@KvHk2Dt{+6MDTa}zup%p-k_;M!mwX&yq94d#*N zB{(*iN18+k*l7daY%q_sAi)615^^E~!R7`?_(%ILPB7pr zdf9xa!6_7QEibF6Sil)%J{pp)=y9%>qT*~RD#4bbl58m|#g?MdY$+ydKv5L}imDP&RE>b5>I4)$K|oOr0*am_pr|GRMacvd)gqv% zHUUL-2q>ycKv6vcis}66ip(a zXfgpsQwS)UNmn}t$*;2HGEk*CKQM8nRqGbdWEhnI81p!6x6HxR40YxhbDEg3qqE!SG zttOyo4FN@K2`E}eK+$>viZ&2X^br9?8wn`-n1G^91QdNjK+$Fbinb7ZMQ;XzJq?g> z2K#}%c~Vq8{e7{3YkgTop9P$k&F5*-746`9Df*l(MLXG2w2Li8yV+8-hb={W*;2HR zEk$3jrRYmGiuMywbbx@OuLvkQNI=mc0*bySpy)6GMc)umbcBGSqXZNkBcSM80*a0k zP;`QTqLTy^og$#_BA>!s*dwiI1pOVLHP6kTFV(Pg$2{l=D}D{Lvc%9f&QY!v-Y zK+zur6#Yp+(RBif{vx301_4Dk2`IWnK+$aiitZ3lbeDjlGy;n55m59u0Y(21P;{Sw zqJIe}dO$$YLjsB-BL90Y-+v!1KtNF>!B=!H5WHo8gj3DuMV+6e=$8HbR4~%DzN{iQ z(#cX-iaf5DqG+}h#jvF)mMukbY$=LoOHl$_iZZaJD3L8i8QCZb6Ht_ifTGL<6lEcx zC@TR)*$61gPC!u(0*Z1HP?U>+qTB=&Jw`xL9s-K;5>S*xKv6ydit-asRDgh@f&>&5 zBJgKXVFHSZ5PU^WWU!h65^iWdA?`#)`tRu{nhzy9MI&A7%PJ}n>9i{DRGEOHDg+c&C7`Gp0Y%jbD0+f`q8bDg zJxM@OO#+IN2`H*XKv8W1is}$hRF{CFdIS{JC!nYS0Ywc7C~8DNQDXv%QV1w&Lhuzm z9vK{OfP~MQuRU>!OHoGqnTw{8uJvUVwTN_5&s1pH2oe3!FLO@Yh0*bm3P}H4(q84E{Rt=R=nquEk4hAl;7*-|u)Ek!S~rD!}G zMH2`pnn*y=Bm#;i6HqjTfTF1c6um@1(KG^zUM8UE6#|N0C7@_J0Y$G7Q1m(hMKcH} znn^&>ECPz&AfRYA0Y!5ND4I(^(VGNc(a^|XTuGy7nf<8aFe$2S|6rOI=~`b_(ZWcl zWN9f{#Pw42Hd~6`VN21wY$;mImZBwWDSD4BMN8RIw2Uo9%h@PeK|s;_1QdNhK+#G9 ziasQuXcYlPs|hGtLqO450*clVP_&+aq74KTeMCUfMgodHCZK2&0Y#q>P_&tVqAdgz zZ6%=SQv!;%5qw4SBZE&FAmM29l^MXkjL2`=~`b_(auO`NLeY`#r0COn=M6q z*iy8YEk*m-QuGB|ioRq^(SEiR9bik*S8Nm=B%tUJ0YzUEP;{7pqHhQ&Izm9vQ38sN z5m59k0Y%3NC^|tv(MbY|P7zS_9RWq(6HxR60YyI&P;{DrqB8^(oh6{?CjyGj5qw2E zB7<)kAmJ|N!_>~_QZ&wfb;r+WJjfTD*46h#E}Zaazs1QbOQP!uGfC`3S!L+}-yj|`qQK*D>?XE>Z+ zrKpzu)NEAHwZ5#Pn4t5pq7=n)y%fc1QZn}pr{A|MMViHDn>xj;{;!k7Yr7xWEAx@|Cqpu4*Kuu=ZiF>c+j=JtfJCE zr(P8)D#P_sRF*A8<=9eGo-IWc*iuxHEk%{sQdF5OMOD~RRF#dQY6KKjC!pvF0*Y!7 zQ1m1LMKuX1N+zJF76C=I2`H*VKv7)+is}(iRG)yN1_Tr}B%r7f0Y!}oC`uuqs0jf@ zO$jJ!MnF+2!B9;gx|J*7L}5s+Cej#2VLvSDryyUUaclYPjkH#J;RowXW3HJ znk_|b*izJ%Ek*6vQq-O;MIG2u)RB#%=Ljh3L_kqz0*bm2P}G%xqHY8fbtj;x2LVOT z6HwHXfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwVy3BIDIg2D9$ zNca=`rO+*q-Ye^OVMby6pdj^(O9+=jblsEi)<+x&z7PI zY$=+^mZC{)6ip_eXbJ&EQwb<~iGZSM1QfkYK+!7%6unA7(R2ceUL&CBbpncJ5KuIe zfTCFh6um(}(QE>W<`7Ucmw=)-2`HLJK+#(S6wN32ie3l??-(HARQm??2r24n6)gz5 z)|XZEPSD9#Q;Oc@dMR4WmZBwWDSD4BMN8RIw2Uo9%h^)2f-Obwv!&<*Hi}jfQ1l@I zMXLxXT1`OF8Ul*e5>T{`fTHyT6m1}&=pzD(HWEu zP;{Jtq7wuZog|>>6ahuw5m59!0YyI$Q1l}KMW+cUIzvFwSptfFBB1CT0YyI(Q1lA{ zMdt~=qFuq@L<1yz$$qKzZYkPo-|hc3=vrS^(dD4Cw2l=0#`RKkg)K!_*-~_kEk(bx zrRWc~6#dDTqU&ra`im_^H`pk;NkGvp0*Y=EP;`fYqPqkXr4dkckAR}T2`Ku9fTH^Z z6#Yv;(E|dC9uiO#5z@QuC<+iz6iGl)kbt5P0Ywf0MNtG4xdaq>1Ygm`U~sEjeOX2EA?LSxQk1~;Qj~!$MTu-F%E*?YFk6Z;v85<8TZ*!u_N)S*~lHe)9sx!52`FknKv6>iiW(76)R=&x6atEx5Kz>VfTCsu z6r~bS)SQ5#76cSMMer4s2?bjjAmQrvJ^iv$w9$SMcFT}!eOX1%hMZxIrKmO6OHmuP z6t!hbQ9HI2wP#CF2euS-WJ}R=Y$@u*mZHvV6m=n>s4D?Q-3Tb^PC!u)0*am|pr|JS zMZE|p>PV8SfTI2c6b&GtXdnSag9s=ZOhC~P0*ZzbP&AByqTvJ-y+H64 zJsk=zFhIil>>Je2NYO*9Xhg`hzO14#A!l0?DH_Z5QZ$Y&MK7|YXgphrCa|SwB3p_k zv88A-TZ*QzrD!S}MK2LhG>w3wmkB6(g@B@02`HLQK+$Ui6unMB(F_8LW)e^|i-4jx z2q>COK+zlmislkf^dJWLQ38sN5m59k0Y%3NC^|tv z(MbY|P7zS_9RWq(6HxR60YyI&P;{DrqB8^(oh6{?CjyGj5m59q0Y$$MP;{PvqF)Ip zx!m2nmZD5-Day>2qAYAF%F33aY-}mY z&X%GaY$?jgMo}&TigFWB^cVp}c?c-VOF&T)0Y&);D9TSjQ2_#q3KCFMh=8KP1QZn^ zpr|MTMa2jxdYpiw;sg|xAfTuu0Y#+n_6yT8IR1P3qwNQ> z%Q~+0WffI)oE)vCs1nypQDwFiRbfj}RkjpWV@pwWwiG?VmZBPLDSDDEMK#$dN+zJF z76C=I2`H*VKv7)+is}(iRG)yN1_Tr}B%r7f0Y!}oC`uuqs0jf@O$jJ!MnF+20Y%LT zC~84K(NhEzwIraZ6#+$06MRMGo#2xONVvWIy6Xy3G|GPP=o!bgzO16Qj`LhwDQd^{ zQq-O;MIG2u)R8Sk&#|Sb6I+Tpv!$pDTZ+1}rKlSlMcoM~>Onx!^8^(2B%r7l0Y$wD zDC$E%QC|Xz`VmmnpMatP1QZPQMS}?_8bUzPPy&jE5l}RofT9-&C>lXP(MSS{ zMiG2Pt)1Xx10-C}e%*B&DLQKZ4ajK6wZ5#P7aeDLdnp>v^-?r}EkzUAQZ$JzMU&Z5 zG=(iiQ`u7V5?hL3qqxdarwNkGv&0*c-uplCh;MGFWhT1Y_AA_9uuCZOmY0*c-x_=?6l!LJOEa3TA3 z*W;vUSVl7zJFfL*6)kg|s~x3iIoC_k3bquz&z7PO*iy8TEkz%)rDzpfidM6wXboG6 z*0NEwj)0=|1Qcx`py(q4iZ&8Z^f3WNn+PcSgn**W1Qcx{plB-rMV}H-w2gqG?F1Bk zMnKUH0*XE-plBxnMY{+n+D$;w9s-K?5`0DPIl;u|jG`ayA3sZ_=zaTN=G^DF)|XXu zz;ViUmZGn?UWyK~rRWe_ioRw`(P6d}eZ!WbBWx);%9f&IY$^JdjiTcO6rCWT=p+F} zrwAzej)0=?2`Ku3fTAA>C^}6*(HR1Y&Js}c69Gl%2q^lQfTCXrC^}C-(XRv)T_B+7 zA^}C02q?NtK+$gmU(uIN@EHRnoY8)%^?oU`|BoZ*isM>eR?#1h^FmiC`jhLW=sH`9 z{$fkf4Ym~BWJ}R4wiMlFOVJ&+6y0S@Q5qXX_XsHZn}DK!2q?NwK+(Sh6g?oI=pg|` z5m9=#9Yp~GiXsUp3KCEhBB012peTxfBA0+7^PhzGKYW0qXab622q=mrpeT-jqId#| z5(vJcYff;H0TP~TKV1F06dkc|U1x}LtuL!6QrcPYxu^-`3DEk#+`Qk0D?McLU> zl!GlrIoVQ_i!DXD*;4cv8%22tD9TGfQ4#?~`3NY=Pe4%t0*VR}P*jM3qQV3e6(OLg zC;>&q2q=1-fTH3A6qO*Ls3ZYJr3ff0O+Zl@0*cBKP*je9qVfb^QO2m?F9t|>QIdfZ zj`H8rziR(Rs}SW{Ush3-C@0ucimGzG6jftOQFXQyJ;9cu8f+Jm^?kAR~31QazOpr|1MMU4n3YD_>;3IRn;2qJU5KuIffTCdp6b&b!=mi3bMi5Xml7OO7 z1Qd-XplA#MMPmuRqIOZi{su_6hJEY0y%c?9-$)u4(ZnccMqeqK#Pw1%nJqkALX3rFGU}4y%eovOVNjHDO$yrqSb6ETEmv2 zwQMO`$Cje?Y$@8nM$tzE6m2A+=wkwkHW5(t2?0f$2`Jh^K+#qLiasTvXd3}V+X*Q8 zjDVsY1QdNvK+#SDigpoDw3~pUJp>f(C7@^@0YzUBQ1m6iSF}7T__qNPe#bFzR!C8I z`^854qg?CDDmoP9H*6_7!j__=Y$-a%mZERjQgoaxMJL!&bdrst zQv?)!M?lf{1Qh*1K+%r`6rCoZ=nMfxX9+0!iGZSW1Qh*DK+!J*6rCra=vM-YE)Y<3 zk$|F01QcB+py)ROimnh)bd`XjYXo1>S5d)a10+1peje?h6wMEs@q3hOeOX0+MLC^^ zNYM?hm!g|&DZ0g$qT6gKy2F;DyKE^+V@uIJwiNx%mZE>yD7sHT(Z2)~Js_ayApu1Z zuHIcnQGkG=NCJw21Qdk`C~^oWiXx!MC7{S7peUMvq8I{-VhJdUBcLdrfT9EfiZT#T zlt@5PMuM;C&310?*1{XE)rDavgB4M^B^tuL!6tLwZ!Op3B`y%c3~^j5l~c^fTAJ<6cr_)s2Bl7 zj}uT-oPeSd1QeAdpr{l9MWqQSDnmd~Sptg65l~c~fT9Wn6jdaks1m_fl-Ug)GC;zU z?T3i6xc+s0|JT~5>V8LfTG3(6r~VQ)P#VdrUVoITCjjG`s>&!TEl6qRH~d)KwT ztfEe?Q+|{bb>@00>cWJ_Ho?C7`Gu z0Y&`@C>lUO(Le%<1`$v+n1G@o1QZP=plBEYMZ*awdVzqV5d;*CB%o*%0Y#$;C>ldR z(O3eC#t~5TA^}C?3BIC^Zm_ih5-wmr0sEX3CFV0@g6mpeR?!sK897FZrgFU$y~LKH zX>2KanJq=Hu%+l#wiHcgOVMj=DSDkPMKjnann^&>ECPz&AfRYA0Y!5ND4I(^(VGMm z%_E@bEdq+>6Hv5(fTD#26fGj4=xqXu-XWmqT>^?06Hv5-fTH&ZC|XKD(J}&xmJ@tM zlic7t21xi_`yryqQnbN-?0SXkT3=SthpzMaI4N4i^-{E&Ek$eCQnZ#WMeEp7w4N_eI2`D;1K+#tOU(p9{@K*yQT;6{5{z@sj zX+K_c&~>dZtLPioaVAL75w4e_qiiWU#+IUQ*-~_zEk!5TQgo6nMW@(O^c`D@zGtK8 z2Lg(IB%tUt0YzsBC^}0((N6>vog<*=X99|TA)x3y0Y$$OP;`NSqKgC+T_T|9G66-u z5m0o6fTF7e6kQ{r=yw8&{ve>}PlB)LYd83~0TMow$-p@*MPJx2<-hK_)|XXu%XLyF zNzrYtm!dmtDZ0y+qBOP?-D6A9-)t%Rhb=|-*;4c`TZ$gAQS^|2q6km#wxcLOKv5(C zML`0JLIe~!1QbOPP~;L&Ql%fTGd_6qO;Ms4M|R7lAfTut!B_Nz7rbwPgj4K$`Zc6zPZl$t^IYr8 zD(dPvkG&#A-MC(gy0fLI2V07sXG>8}wiNYZOHpsO6!l?CQD3$c^<$%`KLJGp2q+pz zK+zxqiUt!BA)x3z0*aOrP_&GIqU8h>tstQ2eFBO;Aoz-= zdckQ1NO)5o1Lq|vnqdEvSSvl(`m&1Fc+Se#rD!eJOVK*E6s>1V(FV2@eZ-ccjch6U zm@P${*i!TfTZ%TbQM84CqOAlJeM&&lHUf&a6HxRS0Yy6qDEgd$qMZa3?INIPHvvU^ z2q@Z1K+!$|ioPJA=t}~M_7hNafPkW}2q-#8K+z!rioPcJidK2S!v;urpl9H$mZIP6 zKPx)yxz?9ebj)-9oGC@$a=jECXG_ruwiKOYOVKH|6n)2*qVL&K^aERpeq>A0X*P<^ z5KwfMfTEuWC^|<#(a!`F{X#&|c>;=lC7|d60Yw)HD7r*I(PaXPej}jh3IRn|2`IWo zK+*366#YR!(VqkqT_>REF9M2g5PU^PykO>8M$v8iZrM>O>TJJc?WX5iUslmw?D ziqg1Vite$c=x??Z{lk```)n!tmn}sP*i!V6EkzO0dcR$Y0&EmT5>ON*peRH@kwZXH z6ahsp0Yx4GMbQKl#Sl;wOF&T^0Y&iy6eSQ)l!1VvL;{L35>ON-pePdoMVSdG%0fU< zRsxE$5qw3ryYQ~fpbTSu31Idqh0IED#{)0jGik+k8!;e?hS~M7!3PRa7h5*)>m!YID65)nQ9fUA7d}V@pwewiGpBOHo6%6g6T? zQDe3grLa-dgn*)^1QazRpeU7qqUHn?wIHDADFTXG5>V8NfTE`fD0+r~qGt&xYE3{< z8v=^j5>V8RfTH#U6m=k=s3QSI&k<16iGZTc1Yc3j=-@>IB;4Ho@slh?ZOzX)U7}s< z%PQ&-?YIl1=y|S}qMmFi>cy6#-fSuA!6 z6ip(aXfgpsQwS)UO7InRiw>4BK*F`{d-~m_sD}Ns=%r}a`m%~%jdq$YlA`HcFGa7h zrRa6G6wP2u(M+}!&0&6c7$Y$=+{M$wxD6wM=`=q&<@<`Yn~fPkWf1QabI zpy+J^iryih=v@Me786jkgn**=2q;=gK+!S+ik1^lw1R-5_X#NafPkWv1QdNpK+!6K zuju9I;9vtJ+}8f%p;x46k^P+h>S)*cvWnJ6JG0-Bq77UxMIW)HXd_#SK4weNCbkrP z!j_`VY$@8pmZGg}Df*O+qHP2eZ6~1UGXjcs5K#0v0Yy6rDB49p(QX2Y_7G6Cmw=*u z1QdNiK+%^36zwOV=l}slUlCArkbt5?1QdNuK+$0WioPMB=m^1Av^F}p#Q+KCwqJL> zPKs_@MMtAu>&q%S5$$}xSc*<^y%e2dOVM|1Df*r*ML)2m=ts5`on}kX8MYLiWlPad zY!sa%py+1;ihd!W=sW>MzYvNAX|z;Y!o>J6h#qG}F#Su^xPe4%u0Yw=IC`u%tC?f$yVFHRW5m1zwfTAn}6lEo#C>sGq z*$F7hK|oPXg0CnoI#|~L39q&vXuKyy8SQ_DCRdDWeOX0$W1Q~Gr6`H(r6?a;it@9i zr~q4v3bLiB5L=20v!$pATZ)RZrKlJiMUN9uRGfgK5(E^LB%r7i0Y#+=C@MohQCR|t z$`Mdho`9kX1Qb;ypr{f7MU@FCszN|fRRW5t5l~c}fTAY|D5^m~(USxe)g<_e9*YUS zVt|BmTR3@Q{P*-v*pVFLT3=RC-56)p`%+Yo>!qkZTZ$U6rKllWiW;${s4-iLQrJ?| zge^r)*;3SujiOWnikcHp)PjJbrwAx&NkCC60*am{py(L_ik>B)s5JpaZ3rl8OF&UO z0*cxbP}G5dqK*UlpV(TfBWjVGXJ0s%!62`HLGK+$9Z zilz`yG?jp&mk21DMnKWa1YgnfF~O`K8b#M~8#q0sXubWHM6blS)|XZEdW=(fwG_?Z zdMTR8mZDi~DSCq~MYGvbG>0ukbJW;v8CuOHj3sGP_%%6qJ;z$Eh3=kZ32qk zA)x480*V$BP_%@AqW1_WT1r6CG6IU06Hv5*fTH&aDEfeaqLl;`eMmsjDgugD6Hv5< zfTFboU(xiKV0!~3JUYR^c}iMFF-HMY5$R$d;lITZ$aE6h*P6$YrC*BcLdnfT9=z zied>UiX)&Xo`9kR0*W#aP?ShOQAPra!UPm$BA_TU0YzB|D9TDeQ8ogKvJ+60gMgx( z1Qg{WpeQ#1MUN4DMgPPEOBo>Hz6A`N`%+ZWe()$ytZRK)Mfqc$)J;-Ufa|5GAX|zG zv8AXmTZ)RXrKl)dii)wN=yA3b6=zFP2{wvK5>Ql%fTGd_6qO;Ms4M|RyfK+zKf6xAT0=t%;KY7$VCOh8dB0*Y!Ad__sI z!J!67_)3z2lP}hPPrt4uRVUW9zO14KvCiDhQq+*^rKk~GiW;+}D1|LWP1sV@lr2Tg z*iw|rmZIitDQdw+(NhEzwIraZ6#+$06HxRF0Y%ReP}G`$qBaB+wI!ga9RWq{2`K77 zKv72mik>5&s1pH2oe3!FLO@Yh0*bm3P}H4(q8&YJi0Qv|l7!Uy7>Q ze-P3$*0sK@qQ0@tk6WdvAJljT(P#pS#t=|6mVlyh1QfkUK+$*tiY5?HG?9R!Ndy#4CZK2v0Yy^@ zD0+#2qG<#ay-YySD+Cn1NT{` zfTHyT6m1~*ie|(H>l+~9FYO!DGo|RCEM|NZ>snt{(I>Ia^E;$yGuKPe7Pb^^WlPbg zY$@8tmZI%!Df)~pMLXD1^f_CKcCt~li-4lt1QhKdplB}vMf(US`htL>F9|5xPe9QD z0*byOpy(h0MTZC|`kH{E!vqw4LqO3H0*a0jP;`udqHhT(I!-{*2?B~v5`0A;#|Ebx zAmOI=qmG-TD4YF*=~S$1eOX06#yV?uO3`Vqm!dOlDLTuRqMz7ObdD`WKeMIi7q%3g zXG_tqY$>|HM$ttAiY^gQbeVvn-v}tWLO{_~0*bB?Q1m+iMSl=b^d|vD*9j>4i-4jV z1QgvQpy(C>MYjnkx^^I2q?NoK+)d>6#YZ+6@4EYJZ6A||Fs{k{y~a9w2JP> zy4IIf6cOj#+$}|cIK3w?MUiYN3bLgr#Fiq5Ek#jmDRS9TW&(<`5KxqrfTC;!6lEu%CfN-?=gyU+m9DLl%lqlRK7UZ`m%}&#W_{?Nl{_0m!cwU zDJsgAqGD_*dYmmq#o1C+f-OZQ*-})BEk&i-C@MohQCR|t$`Mdho`9kX1Qb;ypr{f7 zMU@FCszN|fRRW5t5l~c}fTAY|D5^m~(USxe)g+)OnSi2N1QgXKpr{T3MRf@%sz>k@ z6^ILVG(f_u?SFZuV4VM+{tEl4+4^y=^<@<`j&ol8Qi@WzUW%HqrKl-eikh*dD3vWm z&Dm1af-OZ)v8AXbTZ&q-QS>wcMb8jW^eh2ItqCYfih!cg1Qd-SplB=sMdJu4dXa#l@dOl2AfRX>0Y#GtD4I+_(G&uTrV>!}5&=ci z2q=1)fTC9jD0-EEqUi(_y+%OM>jV_dAoz;<#RabzAmQ=$>#qAt(P^t_W}It%Sw(Z= zoY+HBG?(k8=uNg1&0|Z^TWl$s&z7PEY$;mEmZC*$DSDeNMendt^ezEKiwP)NLO{`b z1QabLplBHZMau~&T0ub3`veqyKtRz-0*XE)plB5VMXL!YT0=n5S^|pJ5m2MPCw7w4Z>Y0|XR(ML^L( z0*Ve1Q1mqcMTZF}`i6j_BLoy3C7|dS0Y%>uP;{Jtq7wuZog|>>6ahuw5m59!!B@07 zE;!r(36Hd&I@=;e@5Gq#L!4`USw&~#oOws2=qIk1qH}C1`k5_7zp$m~JX?x>WlPZo zwiI1tOVK5^6kTSc=r;n2t`Jakm4Kpa1Qh*FK+zur6#Yp+(RBif{vx301_4Dk2`IWn zK+$aiitZ3lbeDjlGy;n55m59u0Y(21P;{SwqJIe}dO+|MosJ7`H$cK+`%%X;Qgp%o zS@bZ@wZ5#PV7zn2d^|gI?J^NgDE@!n(|6cX6vdVzmn}seTZ*FDQWV3MqFA;R#j&L* zo{gde0*W#aP?ShOQAPra!UPm$BA_TU0YzB|D9TDeQ8ogKvJ+60gMgx(1Qg{WpeQ#1 zMUN3sl!t(#yaW^_5m1zmfTH{a6cr%&iURS$$Zw6JR`yG+Bjf$|(N<(8Rc*-})TEkz~RQdE*HMWxtMRGKYCW!O?wmMul)*eEJbKv4w(iYgLN zREdD1$^;ZuA)u%#0Y%jaD5_3C(Gvs|)gYkgNdk&$5>S*(Kv69MifR*3REL0~x&#!} zBcP~00Ywc6C~8RX6%~#THZ(xO=j}W9MWm>n{R~K>c-Q)}ikikdy-rC{Gp?7SRJIf~ zXG>8FwiG?ZmZFwyDQd-*qNmwX^bA{yo@Jw`H33C!2qqTy^QdVwuPBiK?j zk}XA}*itl_Ek$G4C>l#Z(KrH%UL>GsJOM=$2q>CJK+z-uiY60KG=+eosRR_gL_pCr z0*YQHpy(9>ie4q4XgUE!uMtr6Isrv92q>CKK+!A$irygjiU!69j~gK2Z|q-UgQRF+ zf*G^pUF*v#niucf{!xnF;(95X&z7PEY$;mEmZC*$DSDeNMenes=v}rHEoMv65;lt7 zBcNz00Y%FQC|XWH(Fy{J-Y1~w0|JUx5>WIZ0Y$3_C|XTG(Ha7Z))G*(j)0=|1Qcx` zpy(q4iZ&8Z^f3WNn+PcSgn**W1YgnI_+ZY{Mo~NaXVIHdRMdVTdrQ1)eOX1@DNMf(XTIzT|tR|FIt zB%tUJ0YzUEP;{7pqHhQ&Izm9vQ38sN5m59k0Y%3NC^|tv(MbY|P7zS_9RWq(6HxR6 z0YyI&P;{E$EBZ7(*vSA1SGE7W>upk0&c2a!Cf>EatfHUeoeAfp=ohY+qVsGi`jst3 z7uZsCku61+*iv+vEk(bvrRWMQB%mlvKv5Ql#fTF?#Ur{I_c+CI_->~nNISKxI`rYk+ zDzr#~YkgTo#S@(P3sO{q>!qk9TZ&4trKmJpipsF1s4QEG%CV)WJX?w?u%)OX8%31} zD5^|AQ56D;suECCjew%+1Qb0%Kv4|>ik>8(s3rkL$pjSDBA}=?0Y!BPD5^_9Q9S~R z>Jw1ZfPkWg1QazQpr|ncMJWVdQL%(zIRhk|V*e{xk4sT~`{|G-39j{J6*W(AT3(W( z7F;hyPqC$_C0mMGv8Cu~wiG?XmZE3bQq-C)MQzwp)Rv8+b_5i)C!nYU0Yx1ND0+^7 zqD}-9bta&w3jsx42`K7DKv8!Bih2-G^gIDYJqal4MLgQ1meYMVkmH`h)!}A)sh00Y#q@d_`|11Vh)1qW1RduIEcpn@BUZCAij? zRrGm+Q|J#V+R61&w2Li8yV+8-hb={W*;2HREk$3jrRYnx6zykA(E&D!z9OLLAOS^( z2q^lRfTF_$6n#TL(GdcQjuKFGjDVtV2`D;FK+y>TicS(xbc%qY?+7URo`9ks2q^lI zfTGg`6rCZU=qv$6KM{OIpCtqv8zA9&Ne0diDH;$o<6MGkeOX1nCOCbrOVI_cm!gYo zDZ0d#qRVV4`i(6`SJ+Z?l`Tcr*i!U6TZ;Z*qv%fpimnq-^cMj|HwY-YNkGvp0*Y=E z{vYDr13rps@Bg34X0i(b(turBNTEZ@CUilw*(7AsHe?f;=%x@z=p;dkC{?i{*bqfT zu>!U$wks-96vYCFh#kc%h^Ta9|9`({zMsv8d%e&7J^$x&ZS zY6UG6wT2do+CU3M5zs@O6hLJLJs zXrU+#S}00~7K-{q3q=EjC-6b*#|iY|fyiiW`eMZ;l$qKjdG zqDx?aq6`?I$OQuwWx@bOZWy2_3kE34h5?FlV1S|#FhEf*3{d2O0gCcqfTDaDpr`-_ zC@O>jii%*E6!nX+bUsHEjpK(NNkY*hJi7KqSeY-T$QNM@|4Aq+#r{H38MII|3R)-{ z4J{OnffkC!LJLLXpoOAKp@pLH&_dB=(4gpY7@)`x0~D3R07VrrKv5+OP*ep26it8u zimG9NqKPm-(Ign4s0Icos)YfHCc^+lQ(%CisW3p%G#H?0It)-W0|qFX2?G?(f&q%^ zV1S}}7$!v{BP^8!Nc2hmU|NY#)R(9I4G~u6iz%8LVJ!VwD4K`;g`)Y;LeZ7bLeT|=tdZz=q4DT=w=w8Xax*VbPEhnv=Rm=S_K0X-3kK~-39{`-3|j3-2np>-3bE} zt%d=L?t)=bbVY>aQ353T3%-cW5sF@Ciq=F}nJ=d3-U#E(UxlJ|*k35R4_YW%4=ohk z4=ofu04)@4fEJ1#gcgb(f)Kv4(`P-KAt zib7$4A_E2}3WEWPtT0T9{t;oBPk=;s=|tdsBNScUfrKs6%6u_Jts;$kLWH8$*k34W z11%IqKnq2Y&_YoZv``ccEfmE-3q@_Ag`#%QLQ#8YP-KSziX1RNQ3n{Hs3Qze)CmSC z>I?%Eb%6njVqt)yt}sAR91Ktt4+9h>zyL*wFhEf^7@(*-3{cbq1}N$Y0~Gaw0g8IV z07ZRZfTF%IKv6#!CPghHE!zl?=$CmY6dq~L^yB!^Y*M6^`C^Kkk;a#yLQxv_7mCuM zg`)n@LeT(dp=cnqP&5cyC>jhc6b*qEiiSc9MHfMXqG2#V(Qp``=wcY4=n@#9C<6v4 za=`#anJ_?+8wM!Kf&q%MVSu6>7@%kb3{aE{0~C2+fTBDYpeP>(C@O#fiV9(Xq9Pce z$O{7$6~h2UBVm{nr9@i745DZ*KSxUyipuzDY)Pb*`C^JjMH)S=LeXgKFBFY|7K+9~ z3q|9gg`!KLg`)A$LeXW=Leb^WLXjU@C@O~rMHMhWQ6&seR0RVRO@IN4s$qbli7-IX zBp9Hm1_mgqg#n5t!vIB7V1S~jFhJ2X7@%l63{W%!1}K^d0~F1I0gCEifTDUBpr`=` zD4Goe6kP$sq^LB~Qb2%2|IW|R%7mgRJnf$oX=T2cqAMefX)T1J1=wFGx(Zq-x*A$2 zS_mx^ErJ$`7DEd~OQ40KrO-mrGH9Xb8fZ{-Eeue!90n-54hAT?9tJ470R||#5e6u_ z2?i*-83rg?0Rt4>0s|DSgaL|H!2m_K!T?3L!2m_K!vIBhzyL*e!T?39VSu8$V1S}E zFhJ4WFhJ2gFieW(MOtnpK%zUw6FBpQqIUdI{A89-jE)?C5{e_|jpoO9h z&_dCJ&_dBe&_dC}&_dB8&_dCp&_dB;&_dBhXi&5X1}NGL0~9?D0~9?00~9?80~9?4 z0~9?C0~GxY1}J(41}NGB0~9?A0~9?60~9?E0~Eag0~Eao0~Gxo1}J(71}NGJ0~Eas z0~Eai0~Eaq0~Bq8VN$d%(sGCZiJriZ@$VCg4lzZqMOv9Jrf65B@pEgT=ymKb6ukj0 z6zzr^4^gawwbN~h@ z`TzzfItT+4eFy^-9fARhK7s*?K868`K7j#>K7|2_K7#>@K8FE{zJLLW4#NONU%~)I zU%>!HM__=WuVH|qf50#)+7W4qZ9^1|;afyIg`)NRH1?ZFEAzz^9gj3Fi4=;y!~R0i z3233{duXBP2WX+_M`)qwB(zX;3R);S4J{O%ffkC+LW81nFhJ3H7@+7U7@(*T1}OR& z1}ORk1}OR!1}ORs1}OR+1}ORi1}ORy1}M^^WZDjjbQqv01O_OwzyL*|FhG$30~Ce9 z07X_9pvVRT6t#c>idw=jDLNKunLvO<&*o3>e=8Kd)|y0kl$H5niXx(nYodjsNbD~Z zML`Qi(a=Is475+Me#5|Q34E5ln4V9b%Ozly2AiPJz#*Mo-jaBFBqVxHw;kJ2L>qW3j-AO zg8_2?G?Zh5?H1f&q%wzyL*e!vID1zyL*S zVSu80VSu7_FieUTL|GOPAklyF?-yMq6rE*pUzC;kVv06I8TWP)iXO!NLeWFeLeay} zLeV48LeZnpLeXQ;LeWNOp=cAdP_!9ZD0&e06g>$86g>q46g>?C6#WebD0&74 zDB1!86g>+A6g>w66g>|E6ukfg6uk%o6#X3rD0&G7DB21G6uk@s6ukli6uk-q6m5e6 zie7^OinhZ5MLS@a6x|CJrf7GRaioh-^d|Nfir#`2 ziuOPYMQ=k3MejfhMejljMejiiMSG!zqJ7Xp(SB%9^gawwbN~h@`TzzfItT+4eFy^- z9fARhK7s*?K868`K7j#>K7|2_K7#>@K8FE{zJLLW4#NONU%~)IU%>!HM__=WuVH|q zf4~4m-@pJxM`3`XV=zpLUXQZaVu_-c`DyGMLebUyt;TPotjrfv^nH}kJ5DJ20s9L@ zKSB#dC!vL+Q_w=uX=tJ7475;m7FsAe2Q3txhZc%{f(Av6FhJ4IFhJ2SFhJ3-FhJ37 zFhJ4oFhJ2CFhJ3tFhG$OEz@>Tq{9G3AuvFZ1qLVzg#n5T7@#N&1}L(^07W(!pr{25 zP}C9zC<=!Gidw+{MXh0&6nz(EDI!3kFODW~P6$O|{E68%(N^Y*DTafTDO9 zpeO+bC`yC@in_r7McrY5q8>0nQBN44s22=S)EfpU>H`B5^@Rb7`oRE2NiaZBG7M0Z z0s|DK!T?217@#N(hDlLmwB>dJB>GjJmPJLIGyP`>9wR;4%6u_JgQAURy9q^uvA<9> z1X?H>3M~{}1T7Q|gBFU0LkmS0LkmThKnq0~&_a<58Wd&107Y&XpePFlD9VNbigI9p zq7g7aQ7#NnEjp00t;3gaL|*V1Obo3{X@I0~C#f0g6gsfFd6ZP*e&7 z6qUgMMWbMVqR}u+iUvemJ|;k-v-zRNK%wY0HDQakGG9#5_-NzT9zxM&*k35R99k&y zLkmUa&_YoKv`|zDEfiHj3q=#4g`#R`p=csBD4GNV6xF~0MYS+M(PS8)XbKEaG!+IY zng#9BsII3q?z?zfiOkS}0lu zEfie?Efie~Efg(>7K*Ne7K*Ni7K(0w7K(0!21Pf)07W;$07WZcfTCMqfTEQ!K+!4~ zpy*Z@py)Ojpy+lOpy&=5py*B*plCG=P;?gzP_zaHD7qU4D7ps*C|U~x6x|C06s>~+ zitd8}iq^vbMfbxnDOwn9nMi;{KSP`n|%Xa2wT~AMQK{3{V08&q^-R#ee~90pG7Hjwm(mwc8jy~hfccL-Si)7 zdfBg!*R+22_vmp;s=ZwgP3v#Jw3nt0w%^}J(}vlP_S3Wsds2#~W!dYUnwD#SFv|@YqU`;Ev-#Ap$#@P1_)3ot+`z4xIZokZ>X%p-l+?rNn|2A9GrrJ|-HEpJS zcAlm+*k3Bpw7GWOt7!}DBSvc4BKyrgO6*61-f5PmyZ$Ky;{@u+Kt7UcEFy$RMQUGS6!oNpV~iM zu4#wuU2f2{ukBSgY1%RSV=FZ6g#E{rns(AY;5JP=YrpaiO>4Bjwp!DEb6D@D`qv$W zYv}~&j@#DJ8PFXct*29J2pK+XF+$IdW=qk?ijS0&V%mY|7PD! zcksU>@1;BV|4H}L9sCc0Q*{UbN7w$kga0MxVBNw0Q*oH?;D3sjp*#4$nq}z@{EH2miMIc-_H2j$W=i_}8r`=nnpQ;u_t-zb`vg zckmB{&eR?J3y%%DgMXrLuI}L9SX-bw_(!r9=??ytqh-2-f2QU--NC;za+B`hABtG1 zJNTRax9bl6s`g#FgTHILR(J51CD-c?{7?bIFov6bDrgFkohw(j5u$9r`LKlwYLJNVJfA>G0E z-apkHeDn0M?%=y$U+WIOeQ`{8@ci?H?%)Z;N!`ICz_Yr8FX4^4gZtp$bgktUYAD8o zW|QmCDN@tI`bWiCHLc@rYDao{cnmG`Ybr&3?d?uo>+~t@qNn#CL=N3KQLj$-(NtJZ zFJrHWoJ{)bG+1Y^fxV5Si4Cojr5$^>v-c-ysvfQLsLtdKXmblKUrf6Uq`xj(+K@L; zd0Lm3SPT*oZYMFg4KYib{l-NZB5S6{k{BxD*^VSG60w!VFcD>8B!-LVpGe|j5glm2 zqhBK84D}a!hACp-rOf!)TPEvTSH0M1_0gqunO*gfVNrLyxoOK)UG);9)pzeU^y;en zj8==L#$Kw$=Fwr?PrJmLyM)-j(PGDw_XK&xNal_DDG8K}(dv;@?{t;QKaSluRHgFS z*MqxiapknfOPtD0lH9bQi6rH9-Xg>wdSKoAD>4FhDEJ;=%sJ3q!h!V zzJBV3Z?4kf9-zH;bCOTd;qpNp#_rEu`~0H|RdEhJb!3hz&fz1zL2Bo3-hKZ2E4A20 z*{5xas)(?tRU2Nu;)55oTFV0FH#foqn%yOj=x zPR#3lpSP;=?09VVS97)4q4b#yJ~J<2A5KY&%{9!Vel+c{sP}%qbr;nfot@B2e3MmW z9{p|GX+AciRp-w(57XibXrB+bE|yL&1;_EQ%^*G{Osi_!&g?WUbjGtO{1Ooz_%cu>e{JQTI|JQ?}0rru3 zEcREh%@Z+7?4MzqC!&UIJ`u_E$1No4*Y%t0RC$(tx0|bxP+WHU%nHJj$T+oh>)Cm9 z6x0pyQB;~cg+*6oRORQ6wwtWQr^!C584hf8Gq7P% z_q@DpA0g@stc5M-nx)Oq@QcESgnMG>0x4^#(=-NX?1Y8tmNplMhtq0vGo4IpFWRd! zt%3*I!1?8L_YJrZe zL;s*WFX=Fhs<~sben|%uq-O_DOq3oSmf={P*@5%zWCZOHVt+o9>b!GsBI0!k_P9D@ zuV13m`Esfn>w3cyT?=un%A{UCj#g;ALet{04Ple4adD=%Q6-_n(VD-mCP_Uxhsktm zLbWq`@qN5Blm2K02fk>UD}wgbss9bU`qPrGjpVR`uRdBC2P8OBB^XMn&^8=;NP;8p z<0W-X*2)5jU9dnGJ=(8?!*kT->Dnj`-K4N3_wf?vL@QK=Dw`6{#!PtB1?eeCBLv#P z$Du*(JDLOU#0ToTuW9$u*qsiD_ffCcsRSWf>U|s!(x0IXo~?Dhj~9PXau7={8JB^# zH20%(ObaR{$_OvsCioSspQWa3(e~3WA^NXvT5CGJXj}Tzlao{GDpDra&rGSWt4gW! z*H=~hXV%SVsIF?Lo{&;iH*aRc3^uB&C(NcxRnR)#p0*y6GPACBT5Ut^71dfw&5UW) zDHT(z=cXi2ol#XWHKo3$qOLlnu6lZPeMNmrb(+7vVfKXD87U1jW=yTBsi>V^pE9Yc z%3o18EybDYPxq&#raAr2R5p{yOqxDpdUaBDMP+T0Gc`FqiB~7n>Sn7_YNuCCojsvC zWm-j5P3`pm^J3J`s}HV;Ni`|1x(Tyur_XTDsH;v2)WzI}I#nfRjTG0-m`rtEpW>TY zQ8y)L_H=(K9m}NRsk7_-C9Z*m18|z?VE-3W|NjHQ6%`HDd@eLiFsdGyT*Z+2Csa?Y zm_4<@-!N}xb$xOTvr8aMsGZ(Gf<`TbpTBCxv}rS@`zvPFl1Etk+}VDrlq$FK$)gSu zc-C@Orlrx>BMj9REa|#o#QfFE(8DZ~bfcZ6L$aY;CdKhmoMB5&HjJvF? z8u6TkN;2`^Gpk8dgf7J10n0L5BkD%&DxGv)s3=p0g>Q;S?y;2!_{ePL8Ld= z|8KQ>;oi{yFR8SrN^hzeR_0-;18t_d^)T#~`AiHSY`eZeM~$OLOlSsQw_x~q|1`y@ zowlYk)jic{-$|uqRt3^P{Euq1dAWm2iu!FI*4D81qkM)-13~)#wydh?aYmrobmN^< zjTT8pdy}+4Vkmq9f!Hd}Xsy~NcRQ`a@>TaEF|i9dDdbQEw(iEgmMM9|6e?rKShWyi zbnHqC@n+Y>n{-lXr5HUZc1d4p{WMVVna(!#+cdm zl5Caa3Q6P5Q;c4e64ybz?ERnYWptvv;*H)3W_`s6D#I**AR-y}4$e4PW!#0z*@=ot zxb;poI&~tmsY06{%zv4dlhW$ly?G+Tr9g<%t^9R?I)>T1Qa|3Ue=2uYoh(zig0Oe< z7#ql|c|lW*E;?Na+V-OJW0@PLE(&};`Qi|T?q3k-7mPrhLL`LFM{BY}!Yp$r9bU4u zz$!{bt)i4v{O@a~fU>AdHoEW<;bJBnW{Hd=0PN1Bq&_JreT>$ec}L3}u7{Mcj!3yIe|XVubnMLw!q8vF6vj5t1{J+2VeO2Lvs5b7+WG~jl9D=!H&01T zGI}K%9ZgIwtaVfWC)ED;SpRSB)z0YEH{D3&62}|8=!g>;{AP>)dAW_&RG%K+-)tnk z5{ypVD>ZK#7qoAE0D7L|SJR+`&hr0M*Ap3L*-A<3mJdRb{t4~sG?msG9 zq~*GWJluRVL=BquT{Ucyy6$$PF;gsE5}IFPnqRI$95hYK@fG{COG^BnqEW5_PnO?R zGNP<7yQoydio$H4&ov_3U+VSx3%o@mw36%*ey7Ww8`#2K>MNuD-QL3Dg6vY-vaHA> z+vT`({gq7{x=OPAMcz`{*q2>Wnw=F`lUGcMmKFKRii^Fx!e8telU?A?@spnxl25}S&p}?C`)ZNXmGBI zLz)${B->Z)r4pJc^`~u67hLx25|@uk?wOud(NN*ft(ZQ+S5q;iI=7;}Ca@hUv(Puf zpIMfZLz((KzWGFq&-=GdFtJ&_E1vC>X$x-JfyU0Z{OY`RV{H`oBnE`5RE?G`c zZDg0`qSF1vxnunVKp~xax2x3SEix-_NMJ{&J7`Z&$w+@DftTg+nVF%2%_KQ7buRq{ zo}&Cft&R5Nc>JznRZ6$Fs3_ab2q_$M`g4V;#Vp~(SLSvTx`DmH@yN35vTT12)l^_r zv8%*WIyNAg^g>tBSUGh~NvPB2^ZHZ?vIzA+0S2i2aTKy$j*}XV-{;NA@i*JpIi%Uv zZdZ}Nw8T~9EA*7AluNQ*S!30~WHzI?#OI=f)TyQl7TS@g*XQ>8O1)I4*~F-vL$hw0 zB@)!g0tYPgxC&Ixes6JhQD7ZV&Mfha$Sp0R8uk0KOG~+dBkLS@LB1+(dVjMy4Ny6% z%u`{h7N#shSkBd8S?Q$e3#8`pl;pVl*>1Prndy}53^i%L zcT{#sPJwsyg_)KVjR^Fm#FeWsuz{zTdN?`7#ni_Hce3h`d_+Q^=S&M!SY}Y=@CjcXoDGP?4oVsM{@dQ4f)yJ=UM&@^CB1Ig~BbE#_z?0~u{^k$i*r=dV#r8~Qz zpsc`ELXeN}_=sn|RN+8C723R6##Gu}9b&UiyUdrVF4ulvE)7`BEvY+0#}<@jVK#MD zGLk_~oSu_-g57FFB+O7PPM=im zubw`kwqm-U+fpDgPeDQU2v>nLIl9VcQJZhN%qiXjSEQh`>>S*TctItXQVJS*W#O>s z#6>%k){5uT=Tl!{31UvXnX0W3aKY5D^Zst)feVah4^xV zdSS3z;2O(A#tW{qW>uAByR)fJ2%J3WA^hBpO`JWwDz$%qIfiDy2FSml{=q`f__%;t zMiUJv(+F2#p({|P|H+3scqXK7=JRQwAslL-ItFz#O`V6+sURFtR2JtRG9->4+9W&U z__0mu;I#g6z3Qr`R#((l_l`@NRyA|>@TwVg4b^j#rlqHo(NHscS|!DaQ)g5(B+)aU z;ndYkV1u@tIP;1DN%b?6CO8L@Q&Cq{Gn^g*T`@RmTJkh{jMR5R{mi}-XT~K>ic9jQ z#U;_xh2d3HfTW4js_W}3CRHa*t)4!qp=Nk0S!PpCVjxNJX=$jPF+HiCp1)A6CvO7H z9s*h&;-F@jE5yue7*7inFWE)jGV1Aw44mr$L(FsCd^jJtEYgV3mFX$)jB6T_r&3?f zb)4R;$8PFgxQzxlZ)z@dNu!RZlt!~WGze?}IMiIMi5Y6hZW?H0x@dwXJvZk`(+IP; zgPNKb4IoUf`J9JmBs~7`(3Ha*sc-_$EX8zf!HgL*otg@1|5TP{qkv|E>q1H?(>vy$ z_HY-_MTRch+zG0>F+1`=H9J$&q}+iXo+><$Oj9lKpwKT>W$r2WS(788nGIEc?S3T9=M1y%k)ajeT?I@6lSr=tRu2IxX zcv>D<6I9i%GMe<$&@gzC&%-%Xs7cibnlPDTtH26HI**^dMcj|50fY13u9Y@NGf2Uz zY2w&?KFDMS+6W5bEB5$hUe9L<^H5hHHM(3NVIGP}9yH39B_~Zn0_6*;f#MQxu7_r( zbb^ZL+Dmsjkfj2L3&QYtXqY^X5b^uzxqQ=o7blJLDFZdN3CwSh0C#%9;K2tzIj$_a zNp!)eK%v38j-VD07(O-4%c#pVIi)EL4vlIdP-+a+gPVfl+O4VzW#F=1Fm!PF_%2@H zUJtdbK%#+}qAOF~&kL*ws>qV;(tkOkSDh%P^js2iHmJ%(gDN@(l!@lEG->p>J?hF- z?4k>k+KMhO<^r|aW}BP0INiB4&(1DTo6s~{^UiKi_ws_;2yzHCtenyQGP=V?^(%Qu z7Ic3Nl}bH~Eb`=03LYpc-%s#y2ik-xZ}Klk)HvVG?in^4+y^ELm>!$6xj?banQimN ziqog6h{jW9715kAsEYV<$rC5PZ?vbB)&yO9F}ZX$-I;Jw7p~RU&3774F3q1$Gne7C`BaBzS^CcWFIt>Q<=pFIDvv*vdyUYq}F5cNvUzBY?-&Wu?9z&L(@Wv)V zxO0EO>@9F^+&S*1^Wx+i=*UTKxR@7Hb)wC?|GXG{6J1R&FX&2|#-CZ)e=!2(6FfHC zoN8l^*}OYocriP|P*0VEZ+@!<^FDu}YmDDrR4UgOzN2l9sDlPiG-L`MHK`&uzqYFM znqBz=cLdd{rd#Gtx`7wm#G39paV40Iqgg){xVOM52C6rh!@%TR>RjE;R@tJnZ@SEx zx2Aa|&q&oqe4iF)OZP$A8{m^LdC3J~bN0~Hq3q4Crb8zKv{0R*nG zs6|v*;*}v>VMTpIb)B!e zs;;_0ox`9R6x}{jmN_@NATb;mb&Yi8l39a11H#m6P%}QU2aR%x_$(U91PyVpGVr7d zms)dLVB)kOY1H5X4;NJa zK^?TfYYu_}w@0bvV%Q=e;hCY+ysN8{;hU&x!5ly%XYQ1nUvC0UF1VGLC7~o#iw)F= zyTDag9CWcZ@!+R_oNm)&u%;=1vwxst1NKh7O==dcS?}R0rjhy>np-ymIH-7LJ(vvx z#{<3@PI?M`;hj-6G|F)Wk2|mjHsz88%`E7`C$(!{1$ebN1wfX?=D3>f3kK>%aYB7W zz;G94HJfr0!#HPwvlk3nQ`gG3$Ah0zp}6K@t7@YvRrS|=yx)`rJxIk^3}wcQ%U9;3 zXJaxC{-+zHd~fuEhapY3uIP#pbR)}|+B6rWhx77ijf=-qmB0)N`SX=tU8?@oY?awz z_%H+GRC44PopjqPP^+j5^KNUNcW;=gt>Y zZ?pL$^Q77VPil||isp8?sit%M>N2l!_V{Q7<~dB3w8`K}jfqRpsDr0ZW_QK65V^X{ zE&@5Kw(t9^how?;C{|!ZWKKrZ+2lKoNK9R0id;>fbl`J$VI>s%1CJ)TK5_MEO2a%m zqrD~hGTaPY{hc(Dq=Uw$)Y0H^O7q!K4&6w^#DYJcp^b36hsO2dd-$%pX>r-pDyt_< zpeKK&_|As9t&i_w^#1Fc{Pblk`j*L`^rG(I^4WSJy_r^+{P@ezE$Pc?*NK0(`24Nr zmh^S<&GZcy-tVl$&cs&;eGBYSik!|CiQ6Q;E%9@Xl>R{aLJe=1MPH&}&EM~BNk6Z3 zwP^mzF6$K>DW6t^T}%23c``@ZZ>Yo^i6s&zaHRBF5esU2iDYXb)KIwnhY&(c8AtlY zyNa}n7DBMZbEK8M#OJoo+YOXBTwB+`!`sC<8vcupeyxPkKdYj#{t{_h(c>BkFHjFHH{vdDf{ ziQOgkl}O(OR_g~z94^r<(Ie3-u}tEn5-TK5k~mFby~KGE7fQTF;*AnlNn9=QUWpqd zJ|^)=iO))WN#bh~-;nsO#1ABXD)ETK;}TCvY?MeB5LFLh#J{RXiESlzl9(W|x5QM5 zgCt%oF;mc)G$ z4@vw&;x`h%m&pAA*T=6CL#Vy8ZXq#JqFrLF#O@ONNlceGRH92_u0*fIQ4%kcI6>kR ziFFd^Nn9jxxx^I`?~u4w;s%KuB|a^Ye;0v|=T(WXOMFM-0g0bTYIVlsHaemBgtMXG`Sk5pTa-;!25YBt9T> z;}XwE{7s@k7c9=VjYPY|IElR_@~=klb{9#^l2|B_e-MJ#`z7)(L9m`BalXW*5^s`t zhs1RfACdT!#1|!Qm$*mb0g0bU{6^xB5*sDzbY13hw3OIZV!Ff;G>qi+K8dw7jAT7q z;*E4IXT4hD<1~z9{i4M8=o-%Y6N#s27|Hr~i390pr&zlsE}$_5>+2U@mJ}NP;hpCe!PNV?_r&lj=b01T`DDiYZQ~xP(Fbza_ z`)r9e&*X zaGUxiiD$D-t>>6=D9ze9fBO89ii`5hc(cUU3rzjK#8zHYcaT^z($s#5clk{Hki^ev zz{Tl*C$ZZYQ#&P29%t$~5}z7x>X#*+zueRozZr*Bn9(C~NtLN@k+{3s)E`J}Q)B8* z5=$qWx6`lMxc)ZVjIT;;oMUQZt{E?$Z^nFy z%NCe=mBhE`r!TmEK9m@_*wkGlj#_H!Dv4{aG4*2-zglkUA0_s>!PEmJPQS_2S4!Nn z!ql%x{DlU%oWFII88dD(W1+-r?=bak65n2J>W?Hw-)-uy6347Hb+yEG>rA~#;@9g< zeM(}V4W=F>apps&zDnYAkC=Lg#NQq>b&HK=%-n27uf*$~F!dc0-+ju|pGa)`jH%-# zj(gVBlO(Qx-qepv{DublTt8dz#$f7{fF634%5>RO2p>^1e15|8aS^*M>jADH?gi47l`da=a6e`M-6 zBx;|Uy0yfd&rR)5 zJzU}yCr!On;?~oqep6z|Ia5bS%>BvKWfE8XZ0dU?9-s*ppU*EPcKpNCJtdaYeH~su zP2$5LrhZ1^3HpUOUjMViG@78XzC_|&`pr4k*GPPYeteGg9*LoCOdTaLFVfVbC9b63 zrQ_}Im3WYTppNwsiJj?}>R9)dSV)-xnNO21vl`dNuTbTRd>68p!Q+9h#*f~l8F z+(y4|$NRq{F|4PlV$0dF#u^s(B8t>mvqFdrPiL)d=Byp?6lM;WHm_$Dy#_0@{ zSSxXz#AhYGE%AuNUnHi`jRM}kO5zN*iT}r#3G3$630rsOyUHIbop2L)JeQT;#Csqa;w(g zDDf7FbeU296B3`5_@cyZ5_d{`SK@w&A4&X7;@1+7N&HiyMK|+lDY1>jb`q(1t8yet zq~@qJ|JEbdU#7%7iA55}O1w;Bjl`)EX_&8tP~}HTIVh;~Xga6jmwbPK(r?R}PL4x- zExCT)w1$dGiVbyUticj}Fuy@d=1;S~7ihKbg(sf4be-{PwEaZ~}i4ik>Y^ zoIz=*<%-J6y6P*;WK4&CA}Ux`)bV#>BqMW+e|Dzw4?IbVR8lROe>bR_zJ?Z*>%_W> zX|$26q%gUnp`os}a&`kH`=7q(b}L;q=m+U!2mU>>;1^Y;dd1T_Z)Y*3cHwrsj$b|L zkK4z8wH>#G3-jfB?0E6HmPKy+@GU-G^AvfXHrnFPbs~j5EPLYN3<1Q?U>0wy-RasS_Z3;w9I*;ZP21-Bc31Q z1$iMoLbBO*Sya9g*oY#w!;g;*N}iDtM=$4~)PaLj(*~zIX*o4D_P|V5L z7Os;+78RWisb89NU5-6xXXCQeZTUMJZL4-R?o2(<80yse{`&FOyqEK%roEiIvr&s0 zIgQ^}srUWUUi6TPedk#Y)_`a@xMvc2c~3ocC;2G}fqEQ0|`z ztxm;_Z*@AqfVXRPs-|G`={&Ve8hOO=emWiRiPWlm{Z#2lUaH8~&t+0gpGdW;HH+x| zFx6}i%lNz_72|Wq=j-R69obZ0R9jCUslAkHYsnJt*)kvR={{W{af!qYDvqJFLY;+l zJ`bm+6rgU7sx!STCpSMg&*SkhJ+E>4{5K+hL|(2ZS8+1pe1w}*_nzGrbe>{PF7#%c z?6ElabY*JW__Un#oG%(9U)$N(i|Qd%zlc)Xs|}_1o%9}8{$*uULD;!PvnX$B2)};p zsEtf#y2jM3$>exf4Zj~!?c1VJ9DO?~q7!=;gqH89)N{ui)?U>j+h?@y z*d~tK(3hKs40|Q@*4CTGW@HcSf9CdSyWfbe+kbLl()@dF_~FQ}wq>na=!bQE(T}aQ z!H3`1BEO`++lFp>>CXslaLX^Z+_A&*MeX*tZcd~gY0=>uwZYqI{Wgkg#$5I0&b`aG zjGOY|+4UBEQM~PkStYFwKKlKOPxnZly}WW)RoT!h3YK5l;pl-~*DW=+XkE38=a-)h zv82(@K3}h;#!>IGjndMoxO=5t?Qe{9My72eHksWUGR-BM(~PZDJhpF8UQEqBa^&w< zcuy{JZ*Sb2nwGzvT4-v3^4!zb#Dk5I(L{RG!N#@{9TGdM*u%5E@o;2Jc><+~x_rMP z<8(w~OnDdb?h53Rak?^nJCzB!<(_`Fp7U!P$S?DB4CNOm>35UZOJYA2!zsU=lwTO7 zy++cudfuiy29EvBk1)cZ5){fv5FaY1eW z>zZ8_NQZ0IIgQeanx)>KR_~|O`vQ+yqw|`btqrFh_g#@U$1^8)!?}yx+*Ys1H#IM7 ziPW2hOfC4T!t71QQva}MQB>lQNg1b0>$w*QO{|)P9$<=U-)O(|P-$B=)0Umzu zPw$5#JC?^aBcdjeTSIa_wV%|Efiv~7l)I<$d*#QJ$IxE)1zJ(J{D^{>^2C~T;>71A zcoK4tR3xZt9Fa}^9ksEuTK!16itkMwN`0BGE$4xV>N~h?aGNMjy!7CfVg63rW>OdmG%ocE!HC2dCDRAbz;>7%7xJG^uF zQkPw`Y_sT#>2FblO|x0YXtpu8C%yQ~x{Is7yX@NXbGvr?w&(9q*ZY>IQZ<~De03GQ zQN8a`?;{%{FS#z0&(n#08K=_{pD*y0_sB`e+2Rd7m8xG^Ge-OEgAZwKWEyY7ORH$> zP_?wZ(I&B#^V@xo#WI&q6ATrqlY!i^_w0UoMred`_OP#!tEKr(;~?eZ8@mNYO0Oi4mf1HKM{$iEY%G;HM&fuCM@dhTMJb|he!qg+50#g$>nAn3%A80o zQe+oWNryIT4|(JaY+e>>A&oR1*jWEX^0?Y(eZJgvMgt4{zZ8g zd4}bZ^V%1UH!WiKP-8>tSj&zxi!y(v>-R0%`Vco%|%dKvr?P8dhWv5x~*x0{kQb(zyEue z&TX8>5Z}Ji?czTlsSkaSa`J`onn-dp1@+ocl=LE~=x472}K4IIi&gUiXyBDUAmi| z^QKh#Cf`MBUB0h!b)IkX8d|3Qr^;7#H#xVG!`l+AGl|^U?$hr0$V56j+qcsgj?U>w zqE}m$OY~|{+x!3Fqix=h3$=hA=T2PBW zNbQKPZ<>>sb((REiYCwFb@J$MXJm~hraT-Yn6l8g>Vg^hReA4J+*Fxcl`ls~M^#aq ze|f>kDqm$49p{cS8D+m5;4@vFU!6D6Gf~wlT^VWoN`3FhBenGDoKsttRpeLZReGwh zwz49>&{J7eRhd8eKB}3F)1euc)7aR|XB{~qabxqdJjIkt{^WZ}drsRd8F^fawWP+x z`|^hu-d5?Ob`(nO?r`b{LZesZu#1j}%T$t3ke^<#i>_k3s77!tHhZL88lUCl_2pTc z&hw;1I(8YU6=%?>uRGOaIQ3G}ipSH)e>9EyN4ZZgDRZCRP&_7nP=4ov?Twx344#-t zf93R7On(~6g#3Jp8Y8D)eo|hNCz-F@YIeaT?3>>&ub(GLmAdts%+u~+aXm|^z3ln1 zuJ@s1-r~bE?GMh^zlJL}FbjxQ6*Yvcl4AEZO zrY++3g0`}Erncyk)uFrIZrG6U#{93V`u+As*QxK-JRXs{?3NSJTiyFZ?s|3aP1+*c zO1_1|cU|>GdWchB)=JZ9T)l|fQp6{9>+jfc@7d~$2432C{4>42IQGy_-QL}?eCOek z`n6d#OEOMpCfagF7L6<{;StETjMSqvn%rAXqsZc_a$n7*(w|2Rx%hJe)J_Rn?QyJRH|K zkB?%!97XFjj=XTvd`;$~X}zXxUOwru(04}`+(tR^wbRV0eg0eJ?Q`vUb~D{X8>RY! z^S0VgLaFb_dHGo5E#8xQ2Xo0BpBxV1bNt8ik6D-8y85Ff`r#@0V=WykpZ5Ix+ScVe z{g1e3FPJqrp5{@DyUwWmX~Ba#r{~5tet&I`^Sa&rhn4On6iJ?tZH8 zemyXr>r>-BTQrNtZ1Iz8yeC83@X|(F(pvG-aURpf_u&y-{ABgMQN15m?|mjKU%hWs z@5j}9pDD^$?;F+oarNG3s`AzQM)iJNz4w`>eD%Ijy&qTaeWoj4y>C?S$JKkE8Om4h z8`b-9_5MNQqBvgjLE|!s*Gard;!26POT0_sT8Zl=J}B`~iJK)pC2@{9Q{G#A&ttcf6(};#KRK5mUv9!35h2qo|V`r@i!HBG&&CNXzagj zO;wS{9B1b@8&~A!-Bx>50pBd#g8X`I_$? zaGRsK@?!qh18Sss$^LiiH+6Eis+0eVBR;wK|K^A<|8E>|Np92GFAiER3R*4* zTFwhB(>;%ownP_=AvL{s`IJe)cZ0lVJJa}PsEij~r&q=JDhCF}ilH%dSL*BvpRdwM z9*==C&hr+@q<}oVzihcYYsFpWKksD@xQgFL4)LnKspaOjo93N4w|u$m`+hDd|K>Iv>%xkB=tg zC(=m2o2+Xo>pr7(Zy)WNAD0*BiI;VJt=phdeDx?bGHPR~&Qz_uMOf=bk;==ZjSYTcVyeqaqbo8o_Ofa ze9Op@DbK8{S-)c6k9$|_{`jsb5yShxd-AErA6m6-?j0-kf4*|@rQw6_ndSQ3laRM1 zIU2b3)i9RgS&e}j*wzm%H zOb>sod+5fk!+I4xW$j??Mm5*b+L`=L)-ZY|-P!7-^kc33HHfa(X|y)Z+Lls_w_ZlM zBv`X3wM6So+OnJVMOyA|_0WT{308yBthRnd%e$@HDYZAPN2$zjS=-Sg?>*N2RJOOR z=coqWvDVO*@7ivm<$k)Yf{K--+g8z5$+~SleO@9(x7|u5OVw=?DXi3O?@=wS(rrJ` z8N5xmt)#lUUAJwb>bgU>eNO65-FBL)ZMANDiBh>sx2>b|yGFN-rgeAgwl}Fr_vp4A zl+jt;c9g<7-PVH$Ib4uGU}HjTA5unJLu_^`%Q1_sI~C$vi|q(i z_i>BuX-e}ui>;QpJ7KY1MEiYjv2~-$_`zcPj%wpai)|TEbJAk7P!6Xowu6*IL8$FF zO1d!AHi$}H6l%Mg&c2rvB~~12yNl|3WT-8b@+%3o6;beo+HR!$N<(cCv_n~_Z6q-| zD%3WI&h6+>+m!^^m{40+;&N=L?Qu$MT&Qh1J?^|T)W+Xt8Xsy)B6gk%wKY&7+8Q?c zNp`KBVVg!ZG1ssaQZ3ChZ0}KG^9|cLGCwtJR(cHhnPHnq75TYgyPrV&!m!;)WjSov z=1>8@G;BSoTE8-EGpHRe`K|tqvF00Zre;%_hPv1AZ7daaNBaq;iYifla%!O2-{qu z=>7=X2rB#o5w_>4NE;$-SJFX07-5U0G#`qv>6GTf5w=;Ru8Xm4BS5c@u{F}}kv(mn z(h)`VwAIql&a~U^r?Skl+b*J#)!A*kDBF6wEsH9-!EXB-Rn}~~%}$4Th26G>a+qVc zEhA#*+HH4I4bHRMUL#uP+ie+C^HQ^d>FcH21GeWBg<4sEi? zZY!W17TawnsSp`!Z4)S4*IFC@Td~Zww!T!BthKf&L{IiwTSuypoV7OkRGT(pt!*XM zMDY&Wb+m5e4%<(ZX8Cbjf6AfaxNS8ZSmkkBH8D|j+;)m`m~h9p7L!dEr|JBtuP(ih}%1;YZ>4!ZAATJ9y#ml*PO%S~x)`d_FI=G62T1>&O>1$4s;&($9Hsh>;Dz^T<49ikm9~lEh1GO=qj}*3)mRKKOeCi* zFNDz{x8sGgloyw}#bi1K^pP;FMMtW-5MJ0wS@73gTXgKkM?nj8d~_7Fz~9mdU?PdfY-dP}8q+G+tUbfs%xSXNv{SX232q7BwmzD&`ftf_o%(ezE?%rq)r zmgo@D=~TXK(K>4?Uyf)x*O8${H;bRnf7B7e$>`pe0f>sEW^RnI4ku`skbHyxfw>~2 zKz0>E3PlPbMIwa|uSg-JSfmg#Qlt=4B2ozPi4;OgMG7HhB0_+Gzb|h z8ib4!4MHvz4MN6?1|gS;1|gS=1|fdYAf#M02&oVaLMlarkSft2WP)fAQY{*UOcV`5 zCW!_iHKIXCt!NN3Su_ZlBHARxV_8h+Kk6B}`WtyBA)hiKQ>{!66Ef4_e{Qb`nI*dl zA$1~!kb03qNP|crWVT2l zvQRV#StJ^SEEWwymWT!+OGSf_WuigIHKIYtwW2}Da?v2qH76_lX1{>qUc*`$dD02SkIA z4WdEFgQ7vmL!v>*!=gdRBcegbqoP5`W1>OGM$sT-lV}jKSu_ZFTr>!ILNo|@QZxv8 zN;C+0S~Ljxn`jX7jA#(DMKlO`R<}r0>=X$?c8LZduZspD zZ-@pVyG4VLH${Vxw?u=GJ)%L#+oD0pJEB3zyP`qJd!j+eUeO?ApJ))WUo;4LUo;3g zAR2^xAR2@m6b(W?6b(WSi3TAbi3TAbi#7>)!E%(&e^dnxVvQF~LW*ekYkXp5a+r`W zjH5J&R)iduU4@V@MG7Hbi4;PPh!jG;7Ab`ML!=P$jYuKns7N8?m`EYyTah5-xM&da zooEnpLNo~ZUNi{#K{N>YQ8WlSDH?>F5)DF5iv}TQM1zpCqCvp5G!4sJKzAZd!}6BU9ZA!$ zJRG_MX&RQdf_9LmVR>t4J82r0w}Ea?n&&kUFxs&}C5(j8mJKRm6pR=)sEpAtqS>HA z#=wYTgG$*JMkE_l%yuv$*r0N@htY-&DySVsYc{B)4j8S-;2BN_7~yPCNjt)5$p)3Q z6O0yYP)R$(u(3fU?E=Hf29-1xMi?7Z(ylNJHmIa=Fhbd&lE%ZZut6nFfDu9l&vg=E z=xk6)yTKqp+Jzb+x}}%^iT;7+_l89`DSC=-H5lD>E91o!_12A9bT>p%)Cc1}GW?0~8I00g8se z07XM#fTD|FfTCeAK+$j*py*;4py(19peO?dD00C7MVT-_ksAgm%7OukvSEOt92lTz z1PoA=3j-8+V3-v3)Gc=sAkl8V$<#|I+C%qqj6B`Sd@)5uy74@Lr6}@Zf1#)tS|}O` zEfkeN3q?L?p{NvEC@O;%ibg>TMWdmGqA}2*Xe^$T?PXbT@C{j z`C)*fau}ef0tP6mgaL}GV1S|tFhEf?3{W%?1}K^Y0~FQ307bPhK+$9vplAvVP&5?= zD4GTX6itU=QdFQ@J|#e+ThiS+qfjV%iH11F4Bg6nF-7&d@jI>f zP&5ZxD4Gi`6wQMcisnNLMOQ)#MGK&XqN|`m(bX_O(LxxYXb}uhv={~`S^@(UErkJ! zmcal;*T4Wp*TMir%VB_`>tKMQ>tTSR8(@H<8)1N=n_z&Vn_+;W6)-^2EigdQN*JJM z6%0^xD-2L{8w``8S-K^GE@si!^1!)HC^}46GUImL%6u_Jcj<@{-3u)gt%DYd?t>PJ)$s6nzf^6#W1L6#WPT6rF?t zicY}*MWrbeue>xet`jseuV*weuDvueun{y z{(u3B{)7RFw2;6o-<+fAFhEfV43nb6y5%eZ61{^S>Kb1PMc?uBDNBfz`C^K!Ax66% zLXi#o3q>uUg`$?wLQy!hP}B-qC~6HY6t#gCiXxzeqDW|=C<+=BMZ*9^F)%<;TNt3I z9Sl&^9tJ3~!vIAN7@(*F3{cb&1}N$T0~B?J0gAf707bDdKv7p1pePOoD2j&xiV|Re zqC^;=s2dDW)Ex%;q8>0nQBN2qMMj8aC;<|kP7lP5un=>mZ>3v_Mz0Vn^TibP3o$P3 zB@`uLf1xNDS}00^7K&1#g(4@kP?QEO6s1E8Mg5_Lq5;rC(LiWWGzbPL8Vmyz4S@lQ zhQa_v7r_8U!(f1-;V?ka#V|n8B``oy1`JT-f&q#$VSpkx3{aE>0~BS$07W@4K+y;o zpePpxDDuDnMR_nlQ9cY%Q~<-Is85Jx5djkY6@B)^=qnWc#1s{VSeY-TXk>_Se;=W! z1p5m`K4_t+6j~@MgBFTLK?_Brp@pI`&_dBzXrX8vv`};@G$8ZwH7q8It{Ru^JrzL=sbLX4yRgrYgv zUnrUjEfmdz7K;8q;_f=W>N@`a_c@ISVG)q3CEk6iv26(J^)? zI@S(F$JwFic$=aV1d2`+C^|`?=wyMSDFQ{O2oy~fC^}W3=rn<%(*=so5Ga}^P;{n1 z(OCjT(*=rV2o#+yP;`z!(YXRe=Lr;@FHm%WP*F6YRiUoi4n?!bh#ahuCPPVm3AnaYlot%Y>KWHD7r?V z=vslI>ja9f7bvB~bLXK+!t_Mehm}y(dugzCh7JfuautiWUhK zMGv(qT$BMR&&Y13EQQJcCzkZ>p#`#cGYlotCb||W|Ls5G>6m_seQN10C%62H~XosRD zY>Ji?C|XLOs6n8pQJ|=kK+)0yMau{jbrvXER-mYhK+$pnMNI-lT?LAk7bxl`P}E(Z zXa#|y6$Oe`5-3_(plB6=qE&^8qUu7S`&yZz!PyTJ6x$Rk*Ys<%A6_V~RwyN3Nl~vt zar6G6sJHW>sE-|r*04iSUpo}7X@{bIb|_lQ4n=F*p{Tzdiq^3yT34WGJ%OSD0!8Z! z6m1|-w4p%JMgm0}3lwc4P_(H)(Pjcgn+p_eAyBlXK+#qLMOzCLZ6i>$tw7Os0!7;k z6zw2Tw4+c_)U!}HI0I6?CA}|NJrwmUWMil7C-X92NzpEa;u-6PqFtR2MZ4LdXm>jl z?O}(aJ?&7mmmP}swnNcAb|~7{4n_Of6b%+A+Fzh(h(OT+0!2dwiiQak4HqanP@w1_ zfua!tMI!}@4i+dnM4)JtK+&NBMWY3Z#t0OR6(~APplF;x(RhKP2|`8DphDr63`qHt z^sUf4hobe;O^_1{rQ|CqI;v27c|a(d%L(y?|C_3H_MJL#y z=tMgdon%vVvOv)kfud6cilzz_ohndtnn2O%0!3#C6ipK-I#ZzNEPFXmq5|o0!8--6x}OObe}-c{Q^Y~ z2oyaiQ1p;cQ8cqq7?1%eADg}!ds!$dHf7`CLMi!5iXJZ%_uV)YJ>h&PdeRO>PuZd9 zX*(3nw?ol0b|`w*4n@z|q3C%#6un?m^rAq~O9Dj;1d3i3D0)Sp=v9HD*93}Q7bto| zpy*A3qPGN!-WDi&N1*6kfui>WiryC}S}0KTfk4qBfuauuiaru3`dFwadbChDF#}Sr z%f6MU_*f|VJYDVoq)Q2o$vzC@KmRRS6W81d6JKilWa7h4~qf^3v)1i#`uU>!+`Pv}s*R zzLKJLt&3l79*XLm4@K?mP}IQ=MfG+lD%+u`qaBKtutU+3b|_lP4n++%MU4VQodk-O z7ARUqps2Gz(Xs+XT?C4j6DVpDDC#Ouw7fu3H-Vz=0!1qb6s;&ww30y4$^u2J2o$X< zP_&vrQ4fKlo>l z1&THkDB4`0XbXX&Ed`3U5-8eQplBO`qHP6=wi77YUZ7|PfubD+igpqx8YoaSNT?|4 z-MX+#2Bf@0x~AVJ6g`#w?uFvctxL&QQnY*P;>2x2(H_o+qCM?Uw3i)<_O?UOK6WVD z*A7Md*`a8#9g6n1L(veMq5}kqh6)r76DS%kP;{U`(Ln-5BLs>@3KShIP;`hu(I|nU zLj{UP3lxnJC>kqJbeKTVIDw+^0!0%9iY5va9WGFGgiukmYwN-#8IW@OrVP$*p{Sfl z9of2+d?iJbTNm%&E)*T(d?-5B4n@b=q3C!!6rEs)q7&^ohMLqzCh6h0!0@J z6kQ}xbg@9uB?3j43KY#0DvBnxE-cD`l>f+P@#s)=Pf~PQ>r(QS6kXoBnBOrJUEzEv zy3!6sbL~)cl^u$%wnNc1b||{m4n^15q3C)$6y0D`G*6)DMuDQ61d47JD7r4Q zyd8>OutU*{b|`wu4n+%Wie45ddPShTbGirr0DC`#WQyfMT?yeMc>$==vzA!eP@TF@9j|ZgB^-~v_sKPb}0JU4n@D% z6#Xht^qWA@?*c`C2o(J(Q1q8T(cc0^{|FTQD^T>GKvDK%*_GeDMNwX$sFgrbL7=F$ zKv7Yks7j!yBv4c>P}D}CsI5RzjZjhaW$VIi8IbbObaVArp=fxzre9kuC0|KVhhp*7 zT|-g5^P#A0hoX*lC|be}MN8VDXem1sHQ1r3(GEqO>`=6{P0=y}MV$qTmK7-KB2cuP zKv9!GQCESY~}b7ARUpplDTrqSXY7dI%Kt6ewC^{X(@|6_zD;7KL5sKDwJ`}BOhob&=C|bu3 zMeEw3Xgxa=4X{Je`gSPVzz#(l+7xXhP_(f?(Ix^#n+g7 zwL{S`o1)!oSlA_~^ z#jExSMaMfIicYXY(TR2_I>`=2C)=TDiXDnhu|v^RI~1L2hoaMLicS|OIzymnnn2N+ z0!3#D6ipW>njuhhwm{K20!8Nv6rCqfbiP2*1p-AE3KU%=P;{|C(Io;!mkJck6ezk( zplFsr(QKij=$K;R*$hber1X8)$A+T4>$5SZSW3Q`-*Q9g1$SL(x1t6y0ctqMK}rZWbuIMWEE9u_EiM4;$VfuhF*iXImzdP1lux}sRMJ`wR(1&pIE9p0h*I^L8kD!45?)+M(zrI}|OjL($82 zD0;;XMX%Zvy(UofxN(Z>Qsp9mCvDp2&9K+)#{MPCRMeJNBFJzXs9mH{buPv2@iKNMyE!diBPtyoIF zlA>>m#UqA>qVJp!Mc><@=m$F#{b+}xpX^ZdvmJ_lu|v_Xb}0JI4n@D)6#XGk^rt}4 zUjjvc3l#k$Q1q`r(SHI(xvIF@PElTP}D}CsI5Rz zjX+VYKv6q^qB^0XXmPPHGXqk-Hr-tPO(=RTeRkcxs+4>sMIEb(4-OASOE@2jmb63B zQg$e6utQO!9f~^Hp=fD46fI+iqRw_GTGpnhi$KwG0!2*%MO_7omKP}MCQ#H}plAhw zq7?;-RuU*$S)gbYfudCfidGXS>LF0nQ=n*dfuddlMZE=z`Un)QAyCv;s3@whDtwdy zDSy_K!6{c&uIb;OKBBEzRZ6~+qW)FI!iZ3`j`N{tT{{%5XNRHzb|_lk4n-T-p=d)p z6m4XOqK)lPw24j8rUFHq2^4KEP_%_W(Ut;5TL~0xEl{+LK+(1WMcWA!Z7)!?gFw-a z0!2Fs6b%$88YED(vp~@<0!6zD6zwKZw7Wpj9zsRYT2+OWGa%&`(+9D&L(y01CdfUj zO37DJv~N{$>w`nle$I!Y!FDLx-ws7X>`-)o9g2q9p=g*LiiX>v=s-IZ9b{89LZE1* zK+(YhMTZC!jS?t2RG?_IK+zb1qOk%+hY1vo6DS%lP&7fHXre&T;Q~cR2oxPDP;`_) z(IkPQqXmj43ltqAR21!9RT!NCDR)bsUGEc$o=l%49a~jOzLKI7tBTV{g`$(34@D>2 zp=gR7icYaZ(NsGWooa`o)9g@mx*dwnutU)_o1!xXip~-!nl4Z@L!jtvfueH+ip~`% zI!~bJe1W111d1*cD7r|X=wgAQO9YB86)2i1P;{9<(JXXZy=;e~SL{&qsvU}6vqRDAb|`worsz$9 zqPGN!-WDi&N1*6kfui>WiryC}S}0KTfk4qBfuauuiaru3`dFao6M>>n1&TfsDEeHW z=nH|OF9nLe5-9pwplGpBQS@w8VWSL4`Ni~gwC6(6$%SluQ&md7lA<4~ibKYSq92_P zML*f0=w~|={bGlrU+qxzn;nXNw?ok%b}0JO4n=?26#Xqw^p8N%zXC=72^8f@akZVI zyg*Safue#yQEP#sqCioVKv7Acs9KpmDkWb@(Nd-2H4{TogY%)N(GEqO>`=6{9g3E*Ls4ft z6fJ9qqAqqQTFwqdO*Tbc1&WpzDC#Cq)Lo!x1%aX!1&US@C|X&dXcd8?RRxMx6DaB- zP}EbPXmx?2UIInE1&aCz6s;jp)K{QrO@X3*0!3>H6-7&w3eRUi%BQBAh?Xo>uIb;K zKBBFi{Trv5ucT8~4#c52GTKBZFfl@#q?D)yZe ziiS8JiVm`*kq4n-sFP;{_O(IEmwqXdc$6(|}lP&7uM zXskfdVFE?t1d7HB6ipB)nkZ0oxIobn0!2p(6dff{G)bW7Xn~^10!7CN6dfy2beurZ z@j^w>ex<@58IW?D`V7wCP_#$aY@ARkC0|L=lv44i$)V^J=R?s{I~1L2hoaN$P;|N- ziq5b@(KI_0ooR=nv+Phb-KJ=UK+)L(Mdt_$X`1&Xc`DvC}j6=r2X%D1JPh)xbg zC#2i1uP&96ucYYuQt{zqL(vV+hoX6QD7w)OMK{@@=w>?<-C~ELTkTMEn;nX7w?ok# zHbr*|6x}6Ibhkj!Jpx7d3KZQZP;|dQ(E|cS4+<1LBvACQK+z)tMUM&;Jtk1}xIobp z0!2>>6g?$S^t3?He1W281d5&&DvGWx6+X#;l>4Xe-oGvsEljr;Jy$9vUrEtRrDE}f zP_)4LQ1r4Lie9lp(W`bSdd&_+uiK&M4LcOQX@{b>>`?T!P0>37Mehm}y(dugzCh7J zfuautiWUhJeJD`$kwDSM0!5z)6n!dC^qD}>=K@7v2o!xOQ1q2R(bob+iv^0l5h(gr zpy)fHqUeQEVbu&s`N@tMoEJmU+v!{Rzb}=NucYYbQgPdpLeVeIhoWEYQ1qJ}ihj34 z(I0jw`qK_Yf7zkvZ#xwIV~3)DZHoRAD9TmG)pm;V0!6I^iV6Zntp$pT0!38L5^5FHlq#DC#Isw1iMm^kb`=6v9g3RlP}J29Ma$cv zsGChucY&f61d3J^C|XINXk~$-RRoGw6)0Lwps0sHQBQ%Q)dh-r2^94fDC#3nw1z-Y zUxA`E1&aC!6s;vtw6;J|e}STPgo>hu>cU+akn)e+GdPXam23J_(@zquTU|=NlA;Z& zi*HU1MH@OFiZ-%C(Z+Tt+Qbe;o7$mhGdmP*Zik{R>`=6&9g4QHDcV|~Xd8i|Z3T+9 z6DZnVplAnyq8$Z_b`mHWC{Q#=plD}-qFn@vb`>bvO`vFZfucPGiuM#J+Do8lZ-JtH z1d8?*DB4e`C>l^*_&WnqJ}O<)Uq2N6uw*s{SC^8nq-bb$aoN*D(J<#j(QrEy9cYK5 zgX~Z=!VX0v?ND^E9f}UIL(wQZ6dh_)G+Ll&j6l&?fuh3%ipB{PjTb1IAW$?>py+Uc zq9X)~jua?5N}yg4KD@|6^wT3sAEEfk&Rd?-5I4n=3!p=g>Niq5n{(OGsVnr?@p8FnZ- z+YUwN*c6>BP;{O^(fI;J7YGzxC{T2fK+(klMVAN^T`EvCQ=sTFfudOgMY9Ep<_HvB zE>LuZK+%-~MRNs;t`aD^TA=6}fud`LilS4h3#Vp4%0G0;;7kog7p8xG_`2#+@|6_b zSY5pCtWb25^P%WwI~3hwhoW2UP;{Feif*?<(H(Xuy3-CtciExnZkwWe1d8qzD7sIe z=zf8s2Ly^96exN~py*+NqDKUZ9u+8hOrYp-fubh_ik=iGdP<<^X@R2o0!7aV6g?|Y z^qfG^^8!UL2o*&)R2N>%fRraxXK?0)q7TxK6}?zpO1_e!SE`HO%?L%WIv-m@usU!Z8AK+y*RMT-QAJ`^bWNTBFrfuc_Y ziar%6`b?ncbAh5S1d6^CDEdmE=xc$Z#R5g&2o!xQQ1qQZ(f0yHKL`~4C{z?Js4gsV zcBZI0-Rk&qDB3c8%i2%XrQ|Cq`mMUy@7z%IyYr#w4?7h7X@{b}>`?T#9g6<3L(#u> zDEiM1MY%R{y*(7=ZHih66cq%DS_>2v1&XQ!ib?`S)dEFr1d7@U6x9e6)e01~6DX<^ zC~7ZI)Ip%AUZAKfP}EVNXbFL$B?XF>5-4gADvExoF6@;7Dfj4_!TB{5y^<6)wkaiF zNm1uE#iP#;Maw!Lin`dLXgNC+HQAx4s~w7#w?k1kI}~-dL(vL$C|c2`XeEK7l?94c z5hz+!plCILq8`=719g4QFL(!IYDB8*nMO)jUXd62eZEI7soj}p{0!2Fr6zwQbw39&5K!Kt` z0!2Fu6zw8Vw5veTZURNS3l!}kP_(B&(Ov>YdkYlpBT%%jK+%2zMS}&3_7^A`B2*M@ z*rxDV2Bf@JdiS$YC`vyPTRfmmDfvo@4s25_T@s28ay}G|utU*EI}{ykhoVF5P&CR8 zMTgp0!1eX6rCtgbdo^P$pS@F1d2`(DvE}+DfGyIlt(U|!5JQkx~2C; zQ`?l1ucYXVHpT5{hN5ZChoUp>P;{0Zil*D4Xoek%&bC9*Id&*I*A7MJ*`erso1zN@ ziY^o=x=5htVu7Md1d1*dD4HoybeTZWEP?^V*b>ucYXfHpO#ig`!)X z4@I}xq3Cuy6y0HmqC4$SbeA29?zThGJ$5L%*A7MZ*%aL`Q1pO6(Srg-4+#`KEKu}_ zK+&TDMUM#-JuXo6gh0`g0!2>=6g@3aG+&_T8G)i_1&W>%D0*I?=mmkI7X^x55-3_A zR21FRrf^RNq}-Ig@A~FY^kh=>a+^}}l@z_+rug=pQ1piLq3BIJ6uo7KqPOi(^o|{h z-nB!~dv+*#-ws6!?NIcAP0=EOq7Ma%J`yPUSfJ<=fuc_Ziarx4`dpys3xT391&Y2B zDEeBUXt6-iHv&c93KV@OQ1rb((GLPeKMEB6BvACTK+!KkMbWEm3jbz6$_J*Kt6vL6 z1Jfr-zqTnQUrEuQZHmiX8H)aLJ{0|JhoXP%Q1q`IivF`hQLb%Va}Py%I~29DLs7vF zMXha$iULJd0!1Z(qH2MnHUdR$1&V3}ifRRl+6ffZ2^6&#DC!_kR4-6e7AWc{P_%?V z(UJm1O9>P;2oyC66m=3PT3VD&MI+l5f4D9b9qfE4I>Zh|qwG+0s2z$%+o5QT9g4=6pgb( z(RiDp2?9kE1&R(AC^|x*=tzO0qXdd32^1YIP&8Sf=oo>bV+D$i6DT@fpy&jFq7wy* zP7)|OS)gc&K+!1zMNoZ0Fbja9f7bv#P*k!hsun0}BT&>< zpr}Tms8*n;oj_5YKv8>vq7DK@^#Vm@fufEAMN0@2Eh$j6lt58~KvAPWQ73_-r3H$X z5h&^`P_(R2QS?{a!s;22@}h1ToWDcS-s#4pE;Xg(D=AvOrnuvsp{Selp{TnZidL{g z(Ta8`TFDMYE8C%H6+0BIYKNlL>`>Ihrl_Yt(dq(4y#$JS3l#McC|X0HsINfLngT`r z1d7%YC|X;fsJ}qbIs!%O3KXp;P&7cGXnldA4Frld6e!wAplD-(qD_Q~qNbX{gbYZz zCSB9-T2r~Ee@`N{X-z5lN{Y6uDV~3KDB8;TP_(rjing&s(YAId+RhF|+uNaN2Rjt) zXosSm>`*k&rf85r(ar)zy9gBRDp0hWK+*03MSBPo?I}>Smq5|p0!8}>6zwZew4XrH zV1c6j1&W3U6dfQ?G*qBym_X5RfuaKiiVhMgiZ-t)+?N3nP&C>OMPuwxG}aD9huNWMoE?hB+o5QJ9f~H}q3Cd%q9X)~jua?5 zN}yn`n>42no{zW6x~%*Jm{fNbhq=N=pH*1-D`)U`|MD3za5GmutU*< zb|`wt4n+^!q398tqDKXa9up{fT%hO)fubh`ik=cEdRm}pzCh740!7aX6g?+U^t?dP z3j#$i3KYF0P_#gx=w*STR|JY)6)1X5py+jhqBn$!qC08|(=s6C{nM?EcZQ->(>ta& zYf8yiQuJ<3@y16&(RQG`K+&H9MSlquMQ_&>Ude!zw`|Jbyc3E(ON#!kDJ5S?QLeW5(_^71UmMrt zLs2U`6cy}H)Y=Y3MLQH#*`cUphoWjb6t%HKQCpj$8iAr(fueQ-MRfv2?FEWD2o%)| z6qN;vItmmmAyBlWK+#eHMGXQ)jRHlT1d5gxC|X9KsIx%PvI0e21d5guC~6WaivF!B zG(Mgw>YQ#b`Y#k+kiG)awYHReB}FUL7T0+)6s_odC|b!5MJwB(XcapYt!js&)$CBz z!wy9~?NGG39g2F{6!jJ;>LXCJhCoqYfuc19iuwr@ttC*jwm?yTfueN;iq;h4n;fJp=h8TiU!%CXlFYV?P623 zt3c6i0!6zE6zw5Uw5LGPUIImX3l!}mP_(Z=(S8C&g9VEA7bqGcP;`Jm(NKY+VFE?N z1&R(7C^|@>XoNt~NP(h*g^HrBY728SAmst+CZerF(a7|(v4_-_lCPv_Ol|SWXF}0f z=R?t9b|@NWhobRzD4Jl0qKS4WI@}ILN7$k0NIMiAWm7aspy+6UqR9e9#|RW1D^PTt zK+*96MJEUpohVRrl0ebP0!32`*kzrf9Z6(Hw!I%LR(A5GcA*plGf@(NzLPR|^zfBT#g$K+$yq zMb`@y-5^jjPoU^VfufrPif$Gtx<#PqR)M111d47KD7r(aC_1OM&^rTCo|nGw`rJ^o zAbn}}&e~G)l@#4uTO9aeD7w%2P;|c?iXN~-(Svp`?T$ zP0$P}If_MQ!a+RAYytT00cAvni?*C~7ZI)Ip%AUZAKfP}EVNXbFL$B?XF> z5-4gAC~6ca>LgIKv_R1^0!5t#ik1~9>LO6IoIp{NKv7qLqU8mOx(O9U`F4d?uV#vF zOJ9v`)vj_K?W-lS(Y;+M`AUjbZddH~dMH}O`FLNnsvU|}vqMo2I~4V_L(%GXDC%X0 zqTY5W>SKqZHEfFd3KXp=P}EPLXf1)FwFQd$3lyy*P_(W<(RufuhX>iZ&N0+CrdcOM#-Tgo>gS+ZDFTfRvv}SMFB|MdO#u#@6jh z$yZXeeY@hwH$%}5&WEBM?NGFn9f}6pp=gjDigva`(Jpo<+SLw4yV;>=cblR;1d8?) zDB4S)Xm5d{eFTd36)4(IplGl_(f$HOLj;Nr5GWcdP&7=SXt+SpfdWMb2^5VGC>kkH zbg)3tAp%9C1d0w7DvGvkS2!yJQtpv{^UQXkXlD8(X>_|%@|6^gYgfGa?NBt{`A{^$ z4n-5~P;|H*ijJ^D(UEp2I?4`3lk8A*v>l2j+Y}umP;{(7(QyJr#|splAW(FoK+#D8 zMJEdsO%W(MMWAS^K+&lJMW+cAoi0#xhCtCYfub`7ip~-!nl4Z@L!jtvfueJSilVXY z3a@2A${o_XpTk1YL3PiG}8`6m)W6c zmK};_+o5QV9f~fuDY`2|E-$X@{bxY>J*1 zD4H)&^o&5!vjRoW2^2jqQ1pU8(Tf5_F9{Sa5GZHT)4`+u|hoW|ND5|qVQF}WSb+9R_7bq$V6m=9RT0)>`Nr9rJ1d192iW&uqItdglEl{+K zKv8FbqGbh&x(F04Cs5QRP}EhRXnBF6ZURN!1&US>C|XgdC~93-SeyYVH>FRgi*=Q2 z`Xke?3SFtLlzb&ctJM|TeHw~-I3J37+M#H5I~4V@Ls4%#6!oz~(HeFr>T8FhHSJK; z&!%WCfugkqiuwx_ts_vhu0YXx0!0G^iq;n>+CZRaLxG}=1d28mDB47zXj6fr%>;@z z7bx07plC~hqOAmqwiYPbMxbb0p`vJ&y22V6kn*_nrL$E-(J|@EA=}lJlCPv_r@G?K zpNFD>&WEBwb|~7}4n@1zp=eh-6zyh*qTTIKw1*vv_OwIMUN%L03l!}mP_(Z=(S8C& zg9VEA7bqGcP;`Jm(NKY+VFE?N1&R(7C^|@>XoNt~NP(h*1&R(4C>kYDbf`elXn~?J z0!3qmilQCr3P)x@%G0`JaCQtugWG1~u)0$6l@v{^D_;C%C_3EvP;`VHijK5H(NT6N znq-HfqwP>M*$zd=*rDiHI}{yfQ*^vQ(Fp=YCkhmuBv5p+K+zO|qEiHlrV13DDo}Kq zK+)*}MP~>UO%o_OQ=sT9fuiXGMKc77&K4*-N1*6jfui#Siq01*ipJL!9?F1}yQdFg z6GG87%~#m!O37DJbV*(DgReu;rOt<`*k@4n=e9P;|K+imtFj(Uo>6 znrl;Zl|a$e0!7yd6kRJ&be%xa^#VmV2o%i|D7sOg=q7=pn+1w)5h%Jum+KB1!MqPjxs#hIcp>HDrP4n>=_%EtY5rQ|CqdbqB* z!ndL55$8kEqjo5I%nn75+o9+QI}|->hoYzKQ1rANissv)=oy=$X9bF$6DWFKpy&mG zq89~@KFbv_h*W{0BB?NIcE z9g4oRL(x}uDEitCMT_lF^o<>gzO^a(PN3*}fubJ-ihdL*`bnVZXMv($1d4tYDEdvH z=y!plKLm>Y6e#*jpy+RbqJIR6{uLP*h`wqFOr?wX;J}ogIqW+o7m~9g6Dh zP*k=`=6p9g5brLs5U5qICp{))gpP zPoQXkK+*aFMH>hdZ75K*kwDSL0!5n$6m2R{w3$HB<^n}q2o!B8P_&gm(bfV*+XxhG zD^RqZK+*OBMLP%;MLpUVI{%U>8k`jM3`O^)&#rfDUrN4`qMh3p*Z(aP?c#hW+SLw4 zyV;>=cRLjAVTYnU?NGFr9g6n0L(x8VDB9PiXg`6X!2(753lt3zC^|r(XsAHZFoB}s z0!0T36dfc`G(wzL(#EzC_2s# zMaSEr=ma|yooG{Zl0ebP0!32`-*M9g427L(!FXD4J`BqO0ssbhRCduCXb)R-ouQ zfuidLif#}nnkP_nqd?J30!23q6x||FbgMwoZ30EN3l!ZUP;{q2(Om*XcMBBVBT#g& zK+$~yMfVF7Js?o@piohCY5T&r8IbZC*(}ZsMXRN+#y-@(lzb&ckF_th|2Gsp?tCbE z!VX1G+M(zvI}|-_hobp*D0;>YMbFxy=s7zSJ#SO=f=na9QHwB8`5-56Gpy(ZeqIU&~-V-Q#U!Z8AK+y*RMT-QAJ`^bWNT?`! zq+?=sPQEi9frL96yJLf}DogIqW+o7m~9g6DhP*k=qMyFk$j0!1qd z6s;ssw6Z|aDgs5T3KXp-P}D=HC~DiG@JI%v{73qPx~4`=6p9g5brLs5S_6s=>2qIK<1w4P1T0D+?Q1&THhDB4h< zXd{85jRlG}5h&VJplCCJqRj=0wh$=VQlMxnfugMiinb9b+E$=wJAtC@1&VeMDB4k= zXeWW9fkH)5uMUN(Vy0+v`Z`+gP&6%lHFi*kQu37)?be~VQYjSe?tCcP!wyAz+M#GK zI~470hoXJ#P_(ZdiuSWZ(O^3i?Qc^wM4;#Zfuf-TMZ*M&h6@xOC{T2eK+y<+qLBhc z2MZJ(B2Y9+py*J6qR|3HV+4xE3KShCP&7`UXuLqt1c9Q70!4=l6-B#rC~TJjDR)RW z5$zg^c1~COkLXZJzLKJ&I}{IX6N)A~ABv8#L(#EzC_2s#MaSEr=ma|yooI)mlk8A* zvK@-1*c6>2P&8Gb=v0BC(*%l67brSIplF&v(U}58X9*Nd7buz`P;|CH(K!M|=L!^^ zCs1_0K+y#PMHdPbT_jL+u|Ux!0!5b!6-7sND4df4DId@^gEJ`oY4n`zIy)3yZ&P%GK+!ybq8kN@ zZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pKQhdj*Q_6DYc0py&aCq6YeSfJ<;p`vJ3hr(MKkn)b{%lNZHQK$3+A&+(_C0|L=lO2kGv^5!w#Y7Yv)7JVmlOlV~3(|?NIcc9g4oUL(va* zDEiS3ML*f0=x3XvUj&MN6)5^mpy+pjqCW(R{uC(sOQ7g)fuer|ivATS`cI%JS07i~ zDas2JwGt>Q2o$vzC@KmRRS6W81d6H!irNSiwG}FgzUWXGmH{b$nSOuKm!asMcG;+@ zFC|||QTzJhlyWHQ;Cv{mw?k3c4n-a9P_%>{ik7rP(NcCOYOq65qaBJm*%U1;P_&Fd zQD=doWd(}52oxoo-z`tvKDfvo@_N*_~H-w_SoDW5N+o5P5I~46}hob%LP&C*M zMf=;KXoww(4zNSfP@AG*0!70GiVhSgI!K^sgh0_qfue&2iVhJd8YNJ4s6f$Zfub=2 zMPmhu4ihLECr~tAplE_X(L{lw!v%_t5GXoQpy()}qGpeozUdv}= zQhh1;N{WuHFYewc6dmV$C_3H_MJL#y=tMgdon(iilkHG6#STTM*r8~u9g0r1DLPG{ z=yZXiGX#pJ2^5_vP;{0+(R6{L83ILT3lyCrP;{<9(Rl(z=L-~FAW(FnK+#14MHdSc zT_R9)sX)<8fuhRr2U3Qgmf~@v>z?(Ol<4 z(N%URy4ns!*Vv)xT00b7XNRKe?ND@s9g61Jq3A}NqMHPYZWbuIMWEE9u_EiM4;$VfuhF*iXIm# ziY~7&JeC0|pIw{5xgr!zNu-{rFC|||(fs=2$IFJIXPgg3&)T8rIXe_RZ-=56>`?Tg z9g1GEL(u{|6uoSRqE~E+UKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zW2r zg#tw%2ox<6DEd&K=p%umj|GZ85h(gppy)G!qR$12z7Q&ko~kcYcgYkjNMDV8IuzZR zeyZ`y`cm?h6n#@)T%{=#ed~NE`pynT-`k<+2Rjt~XosSo>`?Tx9g2RjL(#8xDEiH& z=y!plKLm>Y6e#*jpy+RbqJIR6{uLt1d3V<6cq)E zssxHk0!7sVMQsF%+6ola2o%){6txp7ioUKd?2rK|*OfCki$hVT^yQGcaw+*ripu5U znB_xJN9RM)5_TwB(hfyS*`cVx4n>W2DC%T~qNVLnw2U2!I@=U2D^S!$plCUPq9%c& zt^!5N3lwz|DC#ayw1Pm>i5xJ0FVHu|v_ib|_lU z4n+g(P_(`siZ-xA(S~*?+Q<$?8`~6ZB2cucK+$FbMVkv0Z6Q#!r9jbE0!3R36m26= zw5>qVb^=A)3l!}jP_&~!(M|$I0|kl(2^8%tP_&Cc(XIkTy9pHSE>sltD;M6$fRs;3 zUpiYW6wPbC!d5ONUrEtE<>Fr}hN69)4@LXgp=hujiuSid(GWWn9bku|p>`-5W{0BT zb|^Z~rsyDnq7ec`BL#{M7AQJIplFmp(V+rGqXmk_2o#MKC^}4_Xq-UNc!8n`0!0%A ziVhbjIzpi6NP(iG1d1jJ6df&4G+C%9+N)e>S}9YsYWl{sy+hIb^iz$;luOB1QglMO zxbZ5X=tSp3(MfhFI@u0IQ|wT5iXDok+M(!FI~1K}hoaN%P;`b((KLagGX;vy5-6H3 zP&7lJ=xl+aa|DXc6(~ASpy+&oq6-9yE)*!bNTBFqfuc(UiY^r>nki6pnLyDjfuh+0 zMRNp-E*C0_jw=@q%z%{VX0v#FD4LRfCDs+?Qu38sD%Yymt<9}H^0|ifv(LJ74TG~^ zN87sLgzT#%)eTo>9|&t3o~+O1Iy8KqeLu+(4Xb6}dfV7=Sau1W8}81&+pVeLpX`UX zyEkl_{Y1dZ4X1U@<$5%{lzq9Scf*n^=5lK`?7ea>*T3QNRdcxk4WIYOQ*(;aZ ztYLhgTyCp|d;8{c+co^xFPGb?Ve|gE+%64gteea2(eUzsTyCF+h7EJM{Tue(IF}pN zaOI}C+=zxRH_zopHT2plmmAwKahqIjLc{&r<#IN;mnpk%n)M$mO1B=sPKw zo8NHM8?=`$RHJ4k|uIQslt?)QdAFU;lsZY*7rz5er!+s{m&v^SnRD|-v% z8{eLjy$SM-%Uzkh4f2h{ugcyC`NkWr$=(Y2#viWB-VFK1wdZAThkRrD*X+CJ8`D2W zzH+`X{d>|q@{Q>q1n!-0O#hQ76aX`K?{iApr4zofE^9`W4i7Ay?kT3@pMtXG2Qz0Nxm`NeDOuTF&NrqH;lJk_)BE7R^SQQ{WPeeLb1Q%4I^{d$a#d^AH$@>U@eXXW^L?$7HuM=lgbTj`i7RGi|cFE+ac< zv0q(!`9@}Y>+Ej18?xs$zgBb0Eq7ZQYsXk8y=eXGvcDqPqdlL!vhwT1L#|KH#kw)x zTRI!-#rQal0Wr3%%EtOJuI-kM4JxBc>+C7#H*6m37jn5i+1+wovk#s5jVh1Ov|si# z(<}A()$_To`JIZj5A{B$UDy1;V(krkZnSyV{Gh7(yS{k-nxnercP`d`IB%T+x#bVY zj(nXRX&N18A8_{DkN>L9&Q{gm`13cf9hn_2){cAS`{SC=9yDRcFLa*lMpsN1dU*^4kbo0fW{@ANGW=}c0n8ynrjBLJ`$DTd2Tdrxv?8QpY zb$@4`xP129bf#E){<3}gH9y-I-}=jQle05b_3ym#{?*6jnkHn2($n6qa;R1H=eed+ zvQ}I#pF6J7inVP^|x&YtnZx0{-!>~;6#&|TNfH7!ivtC1c4&eQv8YE_5kr}x}l ztvWV8y{l)QHRqV-BmLgIYe24Pt?Z4Pj&$oCZ=pvf4&A!>$Q=U)FVlQv!BdNGOGm2e zkH7DqSB}j!ZIYcyubep0UK z>gdmT^y3EA4a_y&7Wre3KJDf6-#RMS^icFaJ^BrApR`=A>DkEjed1No>4imm=bGNh z{ywIcb~E|weNWlH`Gx&+)&|3yUqf$Qd)G6Sx5F<_&fhuLw5YmrLmwCUNaEPJK?d+T5C9hqwyl)XbrPi9`_OjZ4NUtIB8dV6QD)SDNr(ELh$ zs#v{N^O;AdJ~$s-^~ET$*8 z%o_3HzVgk+`R1oLc=~E_53JF@`Hgt&k;iq(HSLtWXG|B}t8${5_yJi|(0wFQ4=E{h6DL>3`RZZ`FJ`Up~}*gIv>y?96i6nIqzIvXAghf5+wA z;JJD0iye1rer}%oZrm!(ud?4}{d05WRrbm!Pn?ncm8-6;yaXS3+W*eIYJTNaw*PtO zR90;hWC6c5<$1avZs+a-^#Ml_`tW^dgb5j>Ev5wZ_VXD%X0I(%U0R@{PghWmo_FgADvPJf?=KICVI(hCBqq7rL^`}fZZ$`3NRX_iMMc-v!vln*u z!qe{0p4~<9bk?dIs;d9=jaRNpqKmbQ_np6E^PzKpo_}fOWqkSPFRz%CYijIRd4{+5 zl>YlK`|#bgV&ox}+^Wrgxu!LvO>EINiFR6xwo|mrTD1M5-P)p!iuPoSHYwWME!sKJ zzG>0sM9Z(${0eG*{%(r4WQ+Ddv{hQPXQQp(qNSgDPj9z@E!t<%hPP-xM?0!T>yh1Z zlg^&mqOBY4@)m8YXm_?~=^Lig*=Jg`VbR`i(Z)slp+!4BT5;|Fc^#Y;ty7D3b+n!> z+8xn0ZqXi#wrh*FAlk?lZDF)yTC~N{&Ti5EjCNIvR=s59<-NB>>k{pS7Oh9L4_mZ# zqy5sNZ56Fe|NnU%>=td=7HwFxJ}ug~Xq&fa$4A?squ0(H?Bk7DjuyMOz&0(-!T|Xn(Y59kMIg$xyp>{^xbjC0f@Otw*$eEn5F*+f`bz zws)W2*{GW-vP0=TVtw|4 zHh)6C-rRYW&rIe`E^pTSKJ=AmMwOb6oHy_B#o2RJ&aOYCBU@CCRMr3T{snhtpEqYu z=kq(y{4sksn7!jYYv0W(pCW$n#`LM#hqxYbXp%z@l)Kb1r-8-|XFKcBt3w zvqq%%*0tLf1`fnz@=EmoqI=S+(`Hq>7$EUm(9nyaNT(@CysQHE2 z=8o0dH@~Ca_@Aw_kGR>Bs9F2c!`?yBC)Mtyd%>8`4Ep(>ZJ&#zF|v8GVBOx>;x_4y9jv)rnCuBK*#Eah^ArE-P3 zb!*nES*K>}?A>DPcu4jsWU*f^m8#bHLfr;6HQ9qJkCxA3Y31xx=j@ZF>gGQbv#W;9 zf5<+EZ5tO@tXyDCKEHLxbfmUxc5%J3BkkH}Pdr_6UB`S)&Hr3x`*yiPwdbU!rd>^K zP5$GNzr@3LL0ofa1>E@Rvd)P9o=Qr%+Ia;aH)*b8f<*JPuFWjV4dImZd zTbyjwaQ7zJD}UMl)rwnpjMk;)Q;4=)%a&f(O{blh&)%4QnqQq=Pd_oAYt?x6CfUt$ z%V!VBr3d74-8@dFZS`DwUPsq8KX=*7n)`qKw^0`Jxt-FzQQ7AV`P|;=-s#zAA+2*i z<#(E${xl=I%N{4)Ysy}L$^+7$24r{HiF7aBgi(1wc1i!w|2D{K_OUtL`y!K`&+U=! zc}fGDpVDj1PibJf=P3=Go&MB(3rQ}!Y4892-?~}OJ}*r7Zpr=<Y2uwf?{Vi}STD&eyg$U)$n* zdSx{K*D8C}F8w*(&pwo7 ze_nHTy1!ZTpL@?v_YaJo?$2rdbN|`t{$tI59xyxIPd6U4%55}zRQ6Jh&F<1=&dTmz z8-HGyT|Zrv-K9P=d(LNNcj?auX73r(U3$9dWlk?&>dDz2&2OjP|Lg5so4t(LOZmV4 zTQmDxlpZ(TPgfcXx$5I*_s%XjT~PB#e|RhVIF}wP-TyJWYkmO6=>aY;yD2Su#Pr|) zyk*myy5)Z@cbApYg}stqvH8F1+BLuSv&T(uht*f_HEu|+1ILf;HGbUCUgHLjA3A*S z*l}Yf3?DjS_^@6>#~n3x!k83>4j(pg-0<-&9+nZg{V8!$%JvKV*Eb;cE;YKVjmqkz;yI7&B(n&=EsM zjvn9ZprJzt4;go8uRgs8_Z_@O?=|`i?$bNPo>}ZUdd%qIJ%VZ(bJI%MdGk)!{Ae>TP+HNNF*;-C?|HXb)@;>gisHXSo=c+da! zx;S#exaL<$`96flK>}5G`v=6d{GCkTRiHGnpi0(n+C-3?T$U?+SaS8T6c0TsJq z?}DPDhzf`p`~Ukrd#%YN%B#M=_x|sF?sM}z$vSJDw$DDFv(MgVCNn%ua)p{-*4q#M0Af-wn3s0_|Qn_g6!tlZ+bE_Am)F`_G!sKbQ7mATfT<{B5&6zc8 z&g^jI+-Z^t)@8x$uvAJ_(9R{3OP6>~(_NX!A^)>%+1G-*kJGYRAMwX>#<-_At+wtC zDVEbcC0?iEbt=X3X%<^#Suta**cjPLOsZ&Wt92JlYLw=1d7N#nCMqqg1Ql7-wka|@ z-RhugcC|Wm(!Z_cuWUuL*71KfX(eFu!&0YOt?iu-vv;15XvKE^JNs*^+a6{mBihQgr7Td>a-O*lIR_fk*EG=b;`&(tvO}9%-?d`YXj+GLn%8|tRkL9EuoJL2| zHeHhcVhLf8^lpPorL7GE$AAIbrpVUP zt)q3Re5+$fTxzOZL-jX5%;ILd%7QK9tyVDwRu`eNbNT?8&X;MYXsV?&wvr>Nugnvy z1gGVXX=}B$OK_ak(G%99(AaKPF)=|I9Av3 zZU5QPru@axV*U}1mX+AxXj82J-qGrb&W{{DPpni`#};yqomNLFgIzsGS?TVjQe5>? z9+`E-$=)&cd5}%Jn>r)gHZUbxy}`oYJs(=a;s0>G}`1EkvB1^W)59S*YxBFIBPmji9)pIj#iF;2N> znC4QZrR4vWX{)o8B*98fv$`nmb+;W;(|=j4zH&8p(JQ&`fOwAnp8oxIqJ!V+>t2*% zb9Mj55OSii$&X`C)$p%;oXZMrXp-Hz=QD*d$QmkV& zsOu-ypT8LM>v|5HZ?9I@b7&ABspp_Yp9*wL{U_rb{^j-7S#C^SjMMqdc* zP}Zrbo4=%@m()%x8Pb@`-*$eh`_c9_X1g@2yW*8x73_&ELI%Vi$a9gJXy~oajlmTC%6K!S*Wk_gQxn)yqw9q^i-*L9%PpD&=<^Xow4d^_f5rx?Kkbl59lRX+-)+r0$HZAZ zj^S;fha4^L2!B3VzdrwIgKO4it3@Rd|4IAVN=EVjNk7?K1bXM}EtU0`SFX8%C)-Hr zb@m5vBt2xl+_H3Smz=x$^Q9%R z=lA@>d^_f5>sCXo&6vyXeWXrpjp*fc`EBXY${roSq0J zx}yD5@;_TE;Xm4!)z|JB{EdS3kS3vf7pq@a?PZt)YHjuCB9mrp)ShkM5v~9^Hhm`7 zW2ml?YUypIdxF(3(dwb~^N+UCU3wpVldK+E4z5VWN&Kq{mZSd1r$rtRT0LYxcB#9& z<-yw@ch6$fsUB$Ea=42AeI2#Ww|azhC4C~% ziy#UJ3PYvU?rIG+myibS{nk)}B4^8Kt((jj0OVfVUhedLrJ0mo{NK1%2g!E(rbv_e zzkOM&y|hc(NFZGCa%G#s8lz6-2^Zm)bPp3*- zEBA`zF46+?R-B6VH!Z5i6S=!J?9mJIS~-dCZ4P;E?tc6<-L%<4qWd_F0{<@2y_$}} z|Lw{S(Es_G7~^g(9Srw;J#qiN;+mT~`+ZdQFbJRYMFgk6)uocs4gVWU|DmHHz_k|S zW%UHGX9}Yov_E#5{segG;!CyY22!=VFXaALrY(P(m89K%T+2u98Olz_{+D(dU3j|y zS_8iSttI$Bq6+?B4g3#lK<_BLJpR$Nl_(tw8A@Q>^Unt&vSYR;f2V!W7Z=S={@K$1 zKkP%=C9S#ytG#=a&AOj*$_nP08VZBg zcj`UdiFakl`{8oRO2XNtrQuM~s6as|D;y{tQBjy(RPNx6!tAoLz=-T{d2w;Lptxv+ zqcnR&*dGYyMwSScmsQC6!Q#S_g6wixvZ5%2<#K|#;YoE121>KSMaAW^a9MU~d3IK0 zPF{&@w4$i2qNJo)XM{^aW3mgvImM-gfpW7)*;M_-GYg7?`QfZUc_3U=QJ9%ss>e}W zYL@OZFnY&D#o@Aw%(7rf%fRsL{fp+c=qdl{|C%(Uo&hKj-!-0>h3&Yx3nkzncA zlJa6Xa$>EVU;5oFa{J+naGT~?Z7pN8zBfY>ZYaZXt{ zkYzU0&t6(fmJ@a0+2y&c-*8Fp*sz@ILOIL9KzXRR$kfxI$cp}8)S98vk>N~XEGtxI zcE-9io79cjr!8C%D$0-4+UQVDC>$uUOBpOKD#{KjEjD>MeYL{u$t)mIRuK#erIEFX z?8u7jitKQX)Kp|vNuV@TJ~m<%>cT+LSe&}LP1vWcthmfBL6%S*DL_Aa|2zsTm*bb~ zBV1OTlM}ADuzyg!rGtT@aCvED2VIK?H>oJ6;$ z_92xC36VxJJyKzrQI(@7sBYJW_edqyucU%}shx24m|%8xR#fRxH`3Ua2c)sc&mJ4j z354{5=jp@}`i@g6WpPEROvvSyQxFQ)-2iN0wOxzUqCY)yt;NCoh^cYe{6= z_LY%c9IAf>anI5s7Z#W5nb9WGY$DyhR%XtbJvCn1FFWhY&HH77>q>Q&71!Od^bQc2 zhbFi*yCB(`b!>3Ym^UPC#iQcMZ@NA1OKg7iFTV`tykP|A7;@%j%3g29T? zKoG52q&&HD%Nre#11%2~X3JS}$n8P)JY~`Bsj9MRQO;HLwIvnDcDSIp3|IHS$PVSCnEK4*M7DkU7fhQvyLxiGyhVO~ zWOqt;agJ)M83usED6ZB}Fj)=gn?mMOh-2O=|r*#!j^1%XmQenhBD=+=7} z4}^@dF)(FJlhw_ME1$Wbta|>5)$R}t z>JzIMlr1thslN4Y02O7K_N_l$mMi@nvvFw}*+@o}vM^hkJ#>IrIQs-ki)+@)wn1Dp zJG#bn3AvL*jx{Si3%A$O?4m5eJ*q8_FcGvnQou|qe)iPraP{oT(<*0&^eMB-X#ONa%D?V9kwhUmhjL3qmVYG4O*_~4vDlS zb{k+@Fc2w)){k`OSS`{P*i}{6UikesL?enS;)8<*#p^%C zr1<0Y-(u1RruU8SIlp>lb>)KUW8#x%Rn1*AtZL5uh1H9bXZ7hL!NQtFvnGj7nK`F& zVY2*B%`j4e6mjB)uRwV^Uo-)gjl{~Y0_SA(n!_p)&mtwN=BTgInh12HDPF^7Y-y*s| zvdO|_#M_5BpdRn`xi>d49U|B#GP|g_LK?TIJ4e4k2Bi93`^bG!dWV6`P(f&1UH3dq zu+};jyrWKHUGt#VSOma2j^&;v4M(~3Y_)F?S%Bxz9)i`KTDcH|($mNc$hZuRweC}f z6sEWX>bRF4gvsiUe{^)B9gvU=KTKCeH{j2*(VJEnNPT5X)nWbbq3Zeb%{FC}_$P%iZM$66S}M~A_RDD3 zUd4=&%jCbT>UyqvgR1N2$@myoq>lIPQy~+GbU%jcZ6NGBx&PnJm5WKQWf>*{pt{jv{Xw5H7{Q$dDJuzuF?iR_aIhJOY)$S1 z+_1lHR4P4Y?9DI33rEyVUH-jpuKZu;g8EflH#jIMEzS+euvAV_k=zC4F$arcqoV~> zd_vL{9w(55!}5=gbq`(q(wCPV+k=_Nh=v=`RxTPn<^(7wkR?xu8r+|4ICQTgFNXi-|G@HJXzl-fw9jYx*)tlN@2k|@)Lxb8yGMgFuSO={{rcC6Q@kBkvGtTy95)&i=uepA46W!Hyv!%Th1 z=rXE4^e(GItZ>=rP`S*Bx@B`1>aTma;g?&1V?m8{%p${k9dz0|kY0d2p@U2f%vjK# z6?Fyoi>_;Z=xje3(r%ADmI{vugv_Hz;Vx2sz9C;v>&IeLD zJY_|3W7^4aOt%|bEuxMNxk&W5L>}~pg3@ToO{Cner^r%eG6t6?7hQMn@9F`5J2PfB%F0tUAC7qtA-VkR-UeV&s(+qM9e^PvV*k-`ehsG>a^vSRH z5)clvqA0(pc(kbnj-&K71l_I~o^VT<^2A(T542yav1jWbi8G_R4fP(~*v0eXuA@UJ zJJ1KQ_JnzKtdkrx`JK#p7z(GRrh4`bMiu{SD}8!4B4UCGUVky9dD+A?*D}wZZ_^bZa6{OXVtM-vl7>wMD;q z$ZKy#pQ)lh9h^C>diKK7%Gs0W%rX^c`sFN*w#M~uG?7a#`YJJ{tJ|zTzbljH!IcZ; z6IdMfWgMxvU_qd;Bh9@;WX1X)H6xdSw-5^3of|+JAT$s?R|iyuea-Ka-nE)ZNXWRyPWjm-+F^ofc0A zLy<8W_piMG`)>AU<76dC`Q#W+w~`}UDGTRj2TCG!%9=3GRioasU`7vi)kOD6?eXJi zc^z6`i7&=W%Pf$2?ys*yHoPC`eNJDwXZyuhez|65L7*sKuKH|w`qrSsqzA&qBST<) z6$6(nH&J)03X0{`M`@Sj(QTk8>dBv;uli4J%s|HU>+9WJ?c=U{rfXj2C| z^#okA1a)1zdczsrtz1AAQUyE?-Mkr&*i&q=&EwQ?n1gX{IO+zFTbeJY)m*|ML8R`< z;OKyi_t{oASW_QA={?ufrFkMNMeys>&B&sWhvGT_98s#{_y(t<-jGwtvoC2K8gU~m zS}+ilGmsOu`wR}R3j(URXh&DGD(y0={DxocPnCE>^mqgtQ5J=JZ)oSo6drTOU0M!FY% z>6U7f71f{ZtNmH7D{T~Cb*Vq-%8}=s9Ixm*M;s%9!NKu8^%aG{{8{nYvnEwfo-8jt zmh%(3>=zmM$y>)9`6UPWKr#KCx8LPQK4NfL^QO%lUB&Z9KaVW4dC!%NS2a4rx7xcV z=1l7>&sz67*SStdV2~_TsUP#@aHh(nH88m_MMfh7!ba}KzF1EiXIp2S`zU97 zX9s6TXD4T8SE5rsG5-%g(UHe-;P>bS-1R<`O+OROe2N;EaqEXsMg6$tgQ(;)G^2hz z4*8rmN7u+=X1;z*o%u2IcX{f(y}o>QRrLJ*@+pJ#I)Ac!^c=lze{SSM7tQt$MR}dC zUny>W%=}#WSUP&0uOGuluiMv;s-xG*U*sbn>2-c5`Lteooxd>hS#psBv1hv-^4WP& zKk@-}QBLbqJ~uDw$L)v|+)mvMYSZnA6dd#An;xQm+>S^=F<-u_BI?KOXlpN_=Un-U zmGhMoHD8aVyn&z8z%OdxS2pm`AHJyDyQIPVn;ZDM8u%>@{L2kIKh(^AVAyq`qw8c` z)c@=?_DDO>upiJzU&n3uT6SHtp&f-fmnJW%nO8!hGBZ%d-99?E8=UAs-pLVFj&#R3 zIo8Gr4u^iDM&m?>V>mUHDpRd|WjuXC( zTxL2y5t;@a4lRI=gVsP#gq{oC2)z~hAapzQ4d^G({m`D${^jl~q+8>$)Erm{m&W0|7UIe`sx*7U7^hM}<&@Z5e zp-tt(KJ9WqdqVp{GoS^~G0@4-9jbEvcd5#GZ7yx0YENhubRtx6cerF)@7FH*Fi~xF zRi!w#$|n^&T=H!?f{Me{QMQ9T71|#<44MfofmT4PpwprApr=7sLDxgCf!+&!2>Jx{ zY3K{kSD|l1KZNdvehK{+`aSe#sD2Wy9=Ck^ldbZFPqwy(wug3sc7yhU%6D1V%gcw- z+d2#ygzDEO>Gq4E70~0MmC&isS&{fcNP`!`n{x5@Wg5CtZ6M8@NQRtJ<=b^7c-+}Igeh&Q_dI&&9r_Z~{`h7o|NHQtK);0UhyDQl4QhEzJv4>3hIW7^K;;{O?D|TD_Jg^iO{Lg+0aGMWzdz-wb1jSmqM?G-Uz(|dLQ%==r-tc&>hgXq54%=dj3Cy z?t^{@{R!%n@q{ktgSLRSgUV;c+w;3ZlcD{g$3b(UBcbDeq2ED&fm(9I(&KFojf2KRkAZ4`P?sA5&4Ly}M?u5T8t6Re zQs_$P+0cujS3z%rZiYSt-3EOD`Udnv=;zRHp|wz_^gFfOjiGIzeV`+x|EcrKpwpTd zzX-Zc`hzA(ke}(p!euMfTbeViRfcmqb+oUg`{uQWC zzAjyTTWC=iBZhSIyigYk^dkdhqOCMPML(qf0jsG1wP&y(y zKO1_g-}rUVr}`NGDzve5SakU~Xvsk1Pk?S1Z2Wc54~825B{cCk<5QtE0pk}z?+hCM z2=q|4@y;BhgL93_+ZXL}EYCA~4s?5g@vlRh78~ClS~}ABF!a(g<8Od|Bpoh2zOSHN z#~AO2P9JCdNzl#XjeiV!SO#dizB_DmXr<8*^zn}rSVnJjb|8t3-psU#(xX#xz_l8(Aj4je=_vGbB*5${Yg5wTEE`&jb>bE zv=F-bV&gA_zIci8??PiQH@*vW%tqs@p;ujH{B6)rHyM8bdhB(^4}i|S!T3|4|GLTe zC!xRGVtk`pjb`3%v>1BkoyK1beR;F-??c<%YkUH9-2KK+g>HJl_&cDVOGjVp=R0Wc zM~xo@o&UJ;r$HawV*Jz4-?kawG~f-JN#yR59maB4y*HLL2q;!e=l^O$M_$i=`ujm<&T3dZe;u!(8rq? z{{qz0-1t_|yq3m~hOUn_{z~XuZH(Uy?G$JHG0;ge5Y+w8f!^HF`1_&X$QS?W{GXwH z)1p|SGdLAR3)T>`xWx)u5+bT71% zeCMdHmj;~-T@1Y)x(nJyzJgPi?+NuoCqplTZiYSteF^$8w5@#mrEaG)v<$i$dO7qZ zsH>k@egL!xIth9rbS?BM=snQw(D$IGHkNM!wCfd`4$Xm%gU*JY4&4B~ z75X^zHR$KipPW2=74u_6_=0lr1q)nCb#zNaeW!PiqU79TQkd_U+QsDAOiu0IR92)YEi0(u7Y9O(H_`?;m8e{SLXUY$>S7sub1*~;USmwy~Cxrn6;VCRmM1xscvtehme zaK6zRPRajIE_9^mKP);@CM{UtNRfZBOwlmKyw>@TUZ%BIo~-Ximv`n&nIqe^rz07N%4# zl>gD5v}mDh_V514OF`0OH}$OR^wmF6KZ1q*lOTU}IXOM{Ps8POp8oWZU!VN`)pBXF zOvC*~f4`lcU;XJVzm4QKLw@z=L1_>!m5mD$^3DMBtNWWJzbu1H$~R%l`vj!T=MSf* zNf5og5@}fUHA3B;#r(-=2K5Cw}_tE=Z zyv^y@jN{Op`<2H5_4eCxtkV%M8Gl%&4H86eujh8BeU0dGG?8C!?+%&fIx^`pw6pePEw7nNCadNB!;JzpuLfY5mf5 z$%&0m%Pz>Vzq%89mn$K%U5&*x3S)NHGD`0vQ0Uts%NBL3c*8w+%aH?Vy0;I8?( zhj%R~K6F~+jKd!dDL$0d{y4E50HxX(DU5$+VV!tn*hw3YY2_FL|M<>5Qd8W_IzirmLfc&?(u z%gwwQ-|QOv)~38upRam;i)?$BY}@Hr>^&c465+ z@w-WpGd)e2onimI&Hnq9{dYm+T=$wjH)Jm}UH{%@|NYAT+oa}FL-r`yUteK5LwT;w zd%1F}v`Sm$+Sw{>NA@&hirLPL@isfR&Cu;B?_cPYlVo4+6t=5vvPT`Ce|+Bf(D>ZX zEA_Zcdmwc;(zFJ@pFTQ&bZAW8m|UG(cz8!JCsZ{lfBKcKU*5<)xFeXEmp`d&`bKdh z^N$Oa$(&1Ny7-V|Vp0B(yxc0CdzmEe`273Won=__i$5p_t3V=Aoj0&8JM4lt!NpF5B1B5?6d;ET3$vvU`4u+>uhkpk2ajIo2j2-Ipn!%h4s@ zYwv65F2@tRZd!eD&ixl1yyjfJUi8{J`PYh*XHC!VlKV`0*}4{IzN75RP0PM+^qP6O z>b~&$d*+^g#`sSUB)!=9s5^e_R?9y*x=!u*;zOQxdLQYuWo_Q)m1{%m z?6V)u#sq2gUR|*|e|6rP&>DMgNa|}@UKMC4KJ;?g;s_7AmqqpVInSP_B;+03>Yi=S z(|YzKY)+b9aDL^5Ro6|MphuDT(;IX1=Y_7VoR>Q>)-@XqrxT>Lk(Q=%l(aVG(%O`aNyyFb zSGY}DC}D96n9LA$$bG7naGv%iTAT`d+c7!A@`vRO4-LKZ(nIO?xyn44l%ANBCVhb& zE%onHEt`cBC+?2AJ~9p_Ci(RGm{?Xb*73`muSq-NDHu|zdb0gDd)JQJ9X9hjE^;jY zzQxS+)Mw`}ez%L~!gsga65c&;#PK6vAN=(9&+VysF0=8Wmp{0>!v|ZeyCyB!8QRmS zNvg7~T(4@XT{_Qly?%1~ly+HNuq0>5H}AXzc9MTwA+bkJx4US-y_@cq#20(r=rVKX{UAO=zjDQ*$4- zbxPq+lcv}tl_q8!UKKR0{!@{2V9u|!v{|`_pKhgX=h!?s56-8hWfu-w_L4J=7HMS0 z!PunIf>$fcCRWv)fc=)_53bVv7KfJFT9o^+tv^*2*n5?As`7=KUGc%ZDyiM^sNIab zA>zis4b3|_s^$k3JR*A-hdm6<|7qgT(6GE=_PNYR^2^p9^j|pbeUDtvIgfo&d!F&^LFfU9hi{m`reb+E#Gx8e}1=6H!Kx{r9P0Q9^2!1V#Wiv zc5S?VYKyoTUwO6te9r&Q{!89?c+qF)d>&#W(-}zuHl^KBi5obh(crmxIi*VQ@b zU#%NeZODAS-KOtm^xyXB?PFalPO19jm5CjPJkqbxuHbF{Uk17aqOtPe(2Tu2&Sg#I zeX3hKI2=FdXfW!><%~H=28k}GZ=sBnTrTT<8JW9W-VYOG&{Uo%(}hPB%JMFcwOR)2 z?q)Jla}~FrXh+^`*`mv5C28pM-XTwRJswLx7{cZ8mdJ+OZ^@P5?%g^di@P_(%b&D1 z1T?;1JI*52*1OdD@wc~afh+o_8TnZ1oW$w1N@N|MK0UcWrCY42Sx zHP^xWwM=*P&X+M}C-1wmWM^+TDMJ_UyD~T4`>5Bva@8T?|fM*#pydm9;T-{eK}H^G^ekF$a<%5h}8J`PTx2w%7sqfNm6$gIeoWD zbzSWAJuPm7(|4nsFqjbcNG5Lw0n?={ry4d#A6v z5Omn-+bf6kgVQ%tYOB`i^T~mXaryL(PLH~Lhos0~xP8log)iN{YvobMUbpX3+2&Vn zUw`3lpWFAD)XUdy-+HNxZ`{6Tr8d5G`$BSH``tdb?BRghcdG2Kz~fsgn=bVD21u!k zJib%q>=%1{y=7x19$$uRWu(W~Opd+OnYR7P3Nx$Co3Fj`H|&<=l?; z_{IoeV`Q7c=E)JYwR~SmAr@P{ zLaC)CmT!}6Y^mjYN5T&*->0(84=rB@smPBkUo+YCPRmy#W!YuuW1@ z_Kw&0sI303*Y}zf_rWHFC-LQ)53SJ6#m*4 zz9cEqbuD~viCo{p*IBlCLkr&)sihlR_~wZ_v$d~A&gNOIeQ(L?EqnMLk_)F*58pI7 z+PQJQDN>esalRo^viWg7zwCBFoX;(*FO2hDCY7})&i90zsuSaUhhz^Y#rZ1b^e>L{ zZIBvV66Z@6a+k*Wj+Rr^NX>NdZrd^SPv!PK)#1DvK=$kCN4Q%wiB^%4!=-V&Vnzhl_R<@G8(bqyMBxj>f-ksnWvC)?$HBs`U zFJ0!1eA0KdY;)pX-zK>ND);*G<-jKG^;HWKReOCW$T3Xb>$^>;tKRDyAjdFeuP;+d zJ#}xRt7YEYR!&Ewn}yzaI&oOGJ6|WBk<-3FCp@yuLY;^a3>WFdxl)ZM>cn!{%5piS zje1LsuF#3mvK@Vau+e6zh?P3=q@1f&I`OMi;u$*ef-JmRCtj7ZtkH>=q|(n1%YK;IuRq) zq8*$@U8Js?>BN1~`ZU*xJyPE-bmCcAxTQ`^m1SD##6mf}u{!ab)L3hs2ujjMCti?~ z+*T(J$-cDIjXKNelb0kNjV_hKyL4iL>_Y#|u+gP*5qfk&*ps7>34OP9j81HlfObhCH*K?oHyGoF{+Mr0SY3lL`4sDrd}>vgc+V&6|6y z?$$72p+#nz!|KuQ3duaqE@J%-t0!z{vFQ%$7}%r5_HkIp!gdnd*J1U7?I^aN!|Dy& zL2Q4Al?>Zn>;Q+A0(+F$fetGbHcspyhm{7~POM*w<%e&pUdojY-$uO@tPgx^^-{9F z@UiNpX#L<@sh6_#hi|D~3O4}0g?cI7K=|hBrFetjo2i%b4Tf(jK3&Q;1ip!SDc?}| z#_FYf!{8gKm+}pV_o3&30IrF@z29`#bbAiVsCWM;aQFALr! zzK@hI8{Vm2%9jH#=eniG>go>5`ERvZaI(6!Q2<(fEbv<+yuupnj=Qh-%K zNFgi;DS`zd#jqfx1Qvvhgasj`upp!i7KD_;f{+SW5;6*&gp7tKA!Fc4$XIw1G7g@E z91l-I#>1146W~e61b7k>h9@Bt;Ymm(JPDZuPeQ8TNyub)5>gFMLZ-lzkg4z_qz0aZ zOoJyO)8R?T40uCG$h|_&f2;MJi34hurAfCV8NVL`~1ups0rSP*hGED6~JPeQJNCn49ulaTA+Nyzo^B;*Eo5^^Iv z3AqWLgxm~ILT-U4A-BSlklWx%$nEeXJhu z4huq_fCV92U_r=MSP-%e7KA(r3qqcPB_U74laTH3B;*-*67noO33(2lggg&VLSBF; zAuqy{keA>|$jk5~}ZePk07Tdvdc6iv}_wDwpYrwl}7#HFJd%ZatSh?j0}41H(u z(k=JWA1z+GOh`ytE>6SO9?;u{fK^qOEh^-j3)l2L_Ebkdk&}&`1L*X(t9g4Wy(;Gw^C4CGE^0 zMgu8n7Y3FFQqp(^9u1_V2@KpCNJ$eJxFpcAP7(vB22#?l3k4ewsXODU4CRh}nJk4@3BTptwmq6bC2=|NF4Jt#_{2Sus$peT(V6#3~v zQ93;+>O)V8`Z6Fz{TPs<{tQUb00yLJAOlh~hyf`Y%zzXPVL*z8G9X367?7gj3`o&& z3`kK115y-VK#DRMkfI<1Qk2Dj6lF6YML7&e(Fg{lD3<{#3NbJg^>Dg32q3Wo^&wMF zP;|FERk8A%Ugb+EDsoy62v{~n#atg0mC%Etk@TRblpYk7(SxFLdQenB4~j<7gQC&& zplA#|DH_Xw6pdp*ijHSMipDb_MJF&IMH3j1qA&weG?4)*s$@WlCNUsIRSZbcWCoad?`f>oYt@Mywavv`@p$A1v=|R!S^q^=N zJt#Vbo)n$RfE1m^fD|ofK#Eo{AVsG$AVn(~kfK!#NYNP#NYQErq-YHTQgkK*Qgjvr zQnZ!6rIa}6rIO_6s>1Kiq2<1iY{P4iY{beD4OSVC(6w%_Mmp0 z=YygGH5WO(%9m1fsnZI|fZV3&GOiDbE~f`YSI~o^jr5@CN_tRq6+I}rnjREwq6bCS z(1W6D=}FOb3`o)S3`o%p3`o(93`o&U3`o(<3`o%}3`o(f3`o&!3`o)K3`o%(3`o(P z3`o&k3`o&t2Bhe22Bhd72Bhd-2Bhdd2BheI2Bhd;3`o%f3`o&~3=BmZobDO{B=$S) z7hM91-c*Vna(b07rRXuIb(XwNV^j1v*9S#U(1W5a^q^=fJt*2n4~m|o2SrcOgQBPD zLD6=4Q1lEvDSDOxDSD0pDSDm(DSCkcDSD9sDSC+kDSDX!DSCwgDcZq+6uruT6uriP z6ur)X6urTK6urrS6urfO6ur%W6urZM6urxU6urlQ6ur-Y6n(&e6n)6RQ1pn?eWw5t zd$WS`C@4BjUM90Xa(b07rRWo<^@=h6n)Ep6zyj~iViR!MF$y>qVE`xqC*Tw(f15U(P0Lp z=m!R*sFndK`jG)C`iTK4`k4VK`h@{0`jr7G`i%i8`ketOlK-+YFDsHFCj(OCVqhrR z<#ZnsKw<;(x~TOrD0)_3pK`mr%9m2)by;n@gCZZ-2SttOK~ZCRP}GDT6g8y>Ma}3z zQFD4w)Pf!qwWJ3{t>{TnECW*1ngJk>zp^ z7C>VA$P40DjLVGlKb7|zSUp`{O&8T`qG1eDcZomP_)qH zZkj9}YlqL%VT9_vw;SNT$kwz#YXeo(ZP>w}_g^q}ZTdQkKfJt%sb9u#e- z2Sv}&gQ92YLD6&cpy+veQuG1?QuHDNQuGo7QuHzdQuGP~QnZ5sDSDLwDSC|oDSDj& zDSCqeDSDFuDSC?mDSDd$DSC$iDSDRyDSD3qDSDp)Df)l`Df*BBDf);3DcZ?^6zyVQ zD03Mw9b`a?zGFa&4ly7_-!mXZhZ&Hf9~h9L zS_Y)(M+T(mCkCYGX9lF`7Y3y0R|cf$HwL8WcLt=$;l{9?6ge4?A{PTvUg5Al1x4NT5oCayuch~+x(NG=SH*%YizJ8>N)ywTwzLcU=x0O8*6s2)}P~@ivMd|dQs1H3T>Prub z`q6`;{`8<|06i!gNDqnz(UYRV3`o%s2Bc^x15z}M0Vx{JfD|3afD~mgAVmQNq$raC zDGD+mMOh3;Q8oiol*51&jbK2Eav6}K5Cc+_$AA>&Gay9;3`kKS15#APfD{!oFcc-b z-O~k-*cI9qrGTPjx0n*QSNT$k%H7tw!Jw#u>w}_E^q^=oJt!JO4~oXpgQ9Wtpy+sd zP&A$%6rDg1iYCyLqA&weG?4)*s$@WlCNUsIRSZbcWCo}|9SVw;a(z&AGCe3-Mh}Wkp$A2$(u1PY=t0qPdQh~2 z9u%EU4~kaOlcH4&NYNP#NYQErq-YHTQgkK*QgjvrQnZ!6rIa} z6rIO_6s>1Kiq2<1iY{P4iY{b8iY{V6iY{hAiZ(DHMVBxjMVB%lMVB!!6rJRD9~MAj z1KOcp42p`BqRZW0e+8IU3u15)H>K#DvJNRh>W6vZ$gMP3G^$j87?^ts#p ztN;@Gl@9LrfTGvswS23Q$E$oPMa?|cm)W4GIoAh8E$Bf}OL|b$iXIfj(u1Pb^q{B> zJt%5R4~p8+gQ7TkQgjppQq-OSDeAz06m?`kiaIeMMMpCrMV%RtqAmi?ytc)ZG&Qj{)({ajGghwFo)zVx7|A3Z4QPY;R)(1W6Z^q^=E zJt!JX4~mA+gQB7Iq-YoeQZ$?aDLRe;Dav3#iUJHsQ6>XY6l6e(vKWw}YzCw#hXE-X z!GILyG9X1E2BavD0V&F7K#B?&kfK5cq^O7iDJo__ib@!eqLB# z(UHC%6fM;^VV8Nl%9m0!+G8!s14U!FJ}4SX4~oXogQDZ%4D4IYIio*1u zXd*o*s-!1HlNgYqDh8xzG6Pan&43h5VL*zeG9X1Y3`o&52Bc^@15z}D0V$fvfE3MQ zK#FEFAVqT+kfON^NYOk7q-Z_^QnY{pDO$*Y6fI&vicVxeicVr+D5~(dFBd>!AJ7i< zC{VOpDO&9DDql*`GLQ900Vq0!>w}_G=|RzH^q^=tJt$g14~kBw2SqFCLD4FDP;>@8 zC|XTViqN(b)`0(K!rA(YXvr(RmC=(Rv1?=zIpG=mG|$ z=t2gh=pqKB=wb$>XafUMbO{4ebSVQ;bQuFubU6c3bOi%aw2^_KXsO4&O8|-eQLJ?` zC^}0UrYk*Oitb=Qitc1Uitb`SiZ(MKMRzkGMfWfuMfWlwMfWivMfWoxMgL+ziXLD< ziXLP@iXLJ>iXLV_iXLG=iXLS^iXLM?iXLY`ik@IVincHyMOzsdimvv!y9*$(*)0T| zO`s@G-!Z$*<5j+tqU|1Q#7I!|4A%!m&(edU=jcJv^YozT1$t2QB0VU2i5?WaOb?1) zp$A1f=tF0V(>70V(>NfuZOrk9(#75<5z7 zVo!sjsZGV~@pzRlrRXb3`o(B3`o&W3`o(>3`o&03`o(h3`o&$3`o)M3`mjuTef+V zJSlQAAVn?)q{z*H6nPksB8vejieW&CybMT@j{zxa#DEkvW2cp9fW%hm zQU->iF_wFk01}&~@4FrgiZ0SmuR7WC zDql*`X_j@vcu=&Q>w}^d^q}Z;dQh~I9u%#j2SsPlgQC^+plA&}C_0lK6rDv+iqyFgQ{Q)eDkvJ*O3Wt9 zt9&U%*IU+C6F|`oTptwONDqo`q6bAc(}SX0=t0q~^q}ZAdQfybJt(?^9u(b4Pm1nh zK#DdqAVqgGAVv2uAVv2wAVv2vAVv2xAVvRTK#CqK#Cq_K#Cq=K#Cq^ zK#Cq?K#Cq`K#HDVK#I07AVpglkfLo2NYRrFNYPUa3`N&k?v`Pp=qhb~t^-Bo`U=R? zmRI>wik`D9eJ z0V(=~0V&$efE0bofE0bkfE0bsfE4XvK#IO#K#IO(U?_UVa*q-~V!zi1jn9H2r&G*c z%d31TMc-J~NmZceTdog^_S1u+1N5NiAU!Dhjvf>pq6bCa(}SYJ^q}YmdQenLPl|qI zK#G21K#G25K#G20K#G24K#G22K#G26K#CkO7`BrlCj(OCVnB-A3`miO0V%Q=kfIm{ zq{z#F6!{pCqDBlzQDX+As0jm7)RX}!YQ}&RHD_Qb+Gn{p3Lvpdl%lUe(IeWsZV}^E zzLcWYG1g<%pr{Sk2Ssh^K~Xz;P!vZGijJZOMeXT9Q3rZZ)R7((b)pAFN7Iv{&J0LV z7Y3v#o&hOJU_goz8IYnR2BfGf15(tD0V(RvfE4v$K#F=YAVtS8AVtSAAVs|xkfPoU zNKrBaQk24g6s0mCMQIF3k)Hu6N@qZd`YhSGzgVf3JAI6Wvjjvf?c(1W4?Jt)egCq+R9q$rC4 zDavL*igFl`q7e*8Q7!{g6kri%n$Ca} z&0s)^W-=f}vlx(~*$hb090sIlE(20Dj{zx~&wvyyU_go%G9X2Z7?7e98IYor7?7gH z3`o%u2Bc^y15$J{15&h%0Vz6#fuZR5824-eBv!vr*BTFsHt1W{PL1&@UrN#GG1hrA zLD5RC4~kaNgQ7F&LD6b@P_%{~6rD*Aiq4`3MQiCn(K>oibT&OHI)?!%I+p<{I*$P< zTF-zKozH+2UBG}8UC4kGUBrMCUCe+KZD2r(E@425E@eQ9E@ME7E@wcBu3$ilHZmYZ zS27?)S1}+(S2G|*n;4LyYZ#ECYZ(}dmdCj76F_29k_4O;plF#kOxMMDl`o~}rWotZ z*`VlVt`CZCp$A2`(u1Pg=t0r#^q}YtdQfyHJt(@19u#e+2Ss<&lcIYVkfM7TkfQq- zkfQq;kfMJvAVm)_AVm){AVm)`AVm)|AVrTbAVrTdAVrTcAVrTeAVp6wAVpgkkfN;& zNYOS1r07Wor06LIr08h|q-Z+>QuGW1L(vT}?wZd=Qi@)T zu{zEJMK5uEQ1miAD0+n+6z!k~MX%C>qSxp_(d+b}=nZ;M^d>zhdW)VEz0H6Wy~BVM zy~}_Uy~ltQz0ZIYeZYVeeaL_meZ+ti?PNfTb}=ADA2T3DpD-XryBUz8PZ^M+&lr%R z&l!-SJq$?E7YsF6r=}5S@fVNo1PTqFd#)E7?7e| z2Bav&fE491AVv8MNKpX;QdG!*6csTbMa2wAQ3(T5G?D=+DrG>5${3KMat5TRf&nQS z#efuzW-u(n$Lg~Enq;37BV13ix`li6B&@AlNgYq#SBQ%5(cDbDFae;G6Pby zi~%V+g#jr#l>sR_jR7fI&cIMK!RsC)fW&^TBmFQaawUja;q@wCO3@i!YsoTDw3_RK zqBZoO=uCQ0bQV1*T1yX#*3pBav*|(6IrO0DTzXJ+9z7{q&wv!2&wvzNziXLV_iXLG=iXLS^iXLM?iXLY`ik@IVincHyMOzt=qHPRF(US~F(Nhda(bEh_ z(RK!;=otp2=vfA&=s51`uUGj}ieB+r)(TLx zgX@E$SLs2~YxJP#b$U?r20bWxlO7bkMGuPJrUymu(1W6P=}FOh3`o)Y3`o%j3`o(3 z3`o&O3`o&V2Bc^g15)%c15)$}15&h`0V(>F0V(>70V(>N0V&$UfE0bffE0bnfE4Xz zK#IO%K#KM;AVps@AVuFWAVuFYFciJybssB$#I9{E;Jgfq&e6B>@ArC@FQw>^*UDcB zioWOipy)6?DEfgO6xGs$q95r&(NFZC=x2IR^b0*G`js9O{YFoUerG_696k)&Ns*HQ zDRMC&MQ#S9$isjXSqw-~3fX%y7Gu1!p0JEqU?aiXzWV5Ib*(~ZyHjDDfW>G(~ zSyVtaiwenRQGc>oG=Pjn0|8jH5dez@0kCK=0E>nIuxKa%i#7&e(Ix;a8V10k;Q%Zu z0$@=w0E)wQ6u&5D$MNI%KY6f7@ z762@o4Zxx~04&-PfJIvYuxM)l7HtE-qHO_Kv>m`%G%+>&s|XT(ue*pd$t>DdLp(L2 zeyK(CQ~kb&nnep}Zx*$X&7vL1X3;{jS+t037A+>5MLUwsqMgWQ(Gs#*w3LiR%K%uk z9DqeD09dp$0E=1yShNy=MQs2qS_QzO)c`Eo1%O3s09dpZfJM6kuxK{`7VQqeqCEgu zv?l3&5h|09bT9 z0EIsl8#0ASIX04zESfJJ8mu;?5B7M%;g zqVoV)bUpx!E&yQBg#c&KfvMqxMUd!8`6A9iW>HuliFHwGMEz2WE=%<Icvoc3nX z6=bvMO0rpW71=Dhnrs$bLpF=9C7VUpkGk20a)}Hz*%%jYWQ&xB)WB~h;yk~^sN4@=<(Eu`lS{&n?)~^&7xPxX3?u;EP4%qMXv*}=nViCy$Qggw*Xl5HUNv> z0btR)04#bBfJN^Eu;>E-7JUf7qK^Pr^f3U7J^^6SrvNPa41h(S1F+}|02X}-z@o1J zSoAf(S@dLTxZ6=;(Mx(+_LNyPP;X>^lNwRK)S@3!{n5vmML*KsEc%IT7X3^%i+&-S zMZc2GqTk47(eGrl=nt}4w=n?(c2 zX3;>hS+o(^EE+_{qQL+x8Unzgp#Ut}7=T5a0I+Bn0E>nLu&4-tMa2LtDgj_oDFBN` z0I+Bz0E5)799w17A@!!9wvfB@72q)7PH9HebGT(BI=h~bXXUE=BZ}U zI@+5>hm*~sBgkgakz})IJ=rWeifk4gO*V^;A)7_VlFg#y$XIkd0EIsl8#0ASIX04zESfJJ8mu;?5B7M%;gqVoV)bUpx!E&yQB zg#awN2!KTw1F+~4fV1e3F5y-YBwDFI9y-)4s@Bi+FYOXhzto~DyZFbPZWdidd$Z_j zvRQNu*(|!2Y!+QdHjAz&n?*N}&7vF0X30r7Tp5CqFVu2bQ=JRZUGk20a)}H0E-?6 zV9^r*EP4{)EV{f)_(l;V8qx1vUtt!Vtrk7iC8B<*MbCBdUpmt)dY<-X(FGkA0a)}I0E<2cV9^%JxzBz@l{qJF7GKX>u_onsdLLVL65SF&038`&)Soop8U zK{kuLG`n&)i$Y|xs1w;N3X{#E&SWg|0a%m*z@i8Mi&6nt)CGV=X#gxr2VhYK0E;pK zSd<08qHF*b832nW1Dr*D)53>}AkpzEPJWuZ(*Ih+ zl(dNYr507B`IlT^7FE*TEUF@#MbpS;(R8v|R82OEHYb}!GstF94cRQ3Nj8gW$yihe zz@mBp7R>@+Q3C*r8Ua|;1i+$Z02XZlz@pgzESdwrqAdYfv=so0wgzC)HUKQz7JxQ5yh@RspbRH2{lt z0btP@02ZwUV9~AsEZPl#MY{vAXb%7u?Fqo5y#QFWHvo(F0btR-04&-MfJOTQu;>5) z799w{qJscfbT9ym4gole7N&)JTr3tn*+;}#WEP#RzX3TkEuwy@MMtFhV=py}j-ajwYK$$B@mUW65UGab&aTc(Pe^0@*A&k&Hzr0kG&~02ZABz@k$DSaccy zi%th%(HQ_NIun3JX92M2YycLW1Hhtl0a$b%0E^BCV9^BtEV>YYMHd0E=wbjCT>`+O zO95DP832ne2RMt?rG>WE-7JUf7qK^Pr^f3U7 zJ^^6SrvNPa41h(S1F+}|02X}-z@o1JSoAdji@pJ1(YF9B`VN3a-vhAd2LKlR2yhlX zpBDa51c~0KKl^yWEGmph_$e)-eyK&jrTJa1F^hhuy;<}J*(~zX?aJLO3X#pCPGqwv zOg4);lg%QZY!;=E&7ueyi&6nt)CGV=X#gxr2VhYK0E;pKSd<08qHF*bEGhzEQ856EN&r|?3c#Wf04y2_z@kwAEE)~KqA>t08VkUpaR4kD55S@c z04&-RfJGAlSTqTMMVkSzXfgncrU0<041h&b0nVa=^l+O95`DEm#3@X7SNdaAsq*xQ z`lS|4OZShv!7Q3id$XvTY!+=!Hj8GE&7vBzSu~Su7S)o?qB^o!R8KaGW|6U|0f0q~ z04!<(U{Nywi?#q@(QE(~%>iK1mH;f;3V=mh1F&ct02XZvz@qH{SQH0f(e?l=nhU_9 zc>pY$55S@Y04!<&V9^c$ELsR~7FDK)Zx%tKJL{*hRc6s9`h$=~=@IoyEn1T9zjBjV zw3PN{(K51Gw47`ftst94JCn_#RNl57^Wk(l*(x0^*b(B3S%k!%*-L^g|V zCYwdKkj~ z5P(Gw0kG&{02Vz0z@kS1So9bGiyjAH(GvhHdJ=#|PXVy#X#f^I1HhtZ0a)}L0E?an zIE$`L53dtJqNRG*@jA2U7k%`@3+WN{OD%dO-M{Qkv*=aYn?F`ySrjIlMV-lJkxw>@Qpjde zglrb2lFgznWV0xZj78}HEXn|2Q6>P3vH)0=4Zxxt02bu}uqX<^qOJfe>IT4~?f@+6 z0l=ad0E_YfSkx1MMZEx6)Ej_BeE?Y07l1|i04(YUz@h?xv*`EqaNa#)Q6Ifu^oLor znJQJ75mCR?qKz{A@%NcUgJ^FS4JMmKL&#>)P_kLHG1)BIglrZKBb!CT$!1Xz*(@q1 zV^IkJi%J1lGy;G{BLP@63V=nU0a!E!fJI{gSTqiRMdJZjGy#A`n*y+CA^?jf0kCK@ z02WOKV9^u+7L@_8Xet1U$^lqZ0l=b4fU{^oMtD0BBzlBCd1hdSyV75*AI(-}MAR>} zX!8tzuLsPc8MHTxYRG2MOtM*2OE!z@$YxPJ*({nxHj5g_W>F*AENUWSQ8NIGwg6z! zYycL`0btRV04&-HfJIvauxJ|q7Htc_qU``!6bE3@_5duJ3&5gz04$mhz@h~JENTH@ z(GCDCS_r_RMF1>X48Wot0nVc78R2t9km$|*MVxB0=sA6W$W9p%^-C>Up5fp3kXf{X z_GZz}WV5K1Y!|8^8r|N0RW3G1Yprc04%x~fJK)8u;@|%7F`CwqRRnTbOiv5t^{DwRRAoy8h}OD z0I=vJEP4sx zEV>~hyjlc_cGYLh-e?xxk|yEhjEMTB7QLR~pYWtv^akzCqBqHA(OYD*=xwrD^bXl9 zdY5b#y+<~S-Y1(yACS$W56M{c5de!m24K-A04(|xfJL7Hu;_CD7JUK0qAvkh^c4V$ zz6M~?Hvla97JxQQNPrpaHjv7+|TYdwZ!u~XLh{O_sM2a3fU}*kj3>I1-{z5p!B2VhY@02UPhu&5A#Mg0L-Gyvc%3T1{nJtG$FtY5Y6 zl&5+Gv*-=As5&#E zeyK$>GyTOcm_@a;H;d}XW>G!aESg0&iyFvgQ6t$bY9gCO&1AD^3$j@>n~X(s09dpo z0E@N)VA0k9EZPQuMcV?fXgdHF#Q|8fJpha50o`i%!V&zk9_jI+6Bf(Me>p z=wz~4bPCxlI+bh|okli`PA8j1XOPXJGs$MrS!66a8-PXU0I=v>02ZAGz@qa3SabmZ zi!KCU(M13(x)^{(mjJNnQUDfR2Ed}r0a$be0E?~!V9`|oEV>$iMb`kZ=vn|4T?fFT z>j7AF1Hf5yTxPh}t76e){Q&lOvnWk(WZ#$>QNPrpTQmJlUpI?xqrF*lJJ~F{gKQSv zNj8h_BAZ2blg*-g$Y#;KWV7f#vRQOL8H*kOV9|pBEP4olMGph8=n()GJqp00#{gLL zH~@>D0ASIR04#b6fJILOu;>{87Cj5VqUQiu^gIBIUI1XxivTQo34lc}1F+~702aLp za2DO18Qxw5i9Qn(ac(h-zEg`{%Z#XBYSCMn{yuM-MQ_vIEP97*7QIV0i{2xfMemc% zq7TSs(T8NS=p(XO^fB2i`h<){p8~MxGXNHS4#1)>09f=T0E@l?VA0nAEcyn3Mc)Fj z=sN%weGkB*9{^bNBLItj0$|b404(|ifJMIou;@1c7X1#uqCWsw`2(cAS)vTvG2)%tNrr>uzjr52@R`47Bp7DZ@p7NwHSqAp~!D2;3urIXE~46<32 zNj8hJ$YxPC*(}N-V^J;ui=qH5>I%T3ZU8Lm4#1)w04$0DuqY3JMLhvn)C+(`y#ZL% z2Y^L=0a%m|z@mNtEGhtCQ6T_}`U9|N004^y0V*pq*7Jx zMHK)nssvzB6#$E-0kCK~0E?;tShP6+i)H|vMMJZ~BSetsWBSqA#%58eejHMh6;Z#` zqWUbq@dLAH7VXWV2C`YyNH&X_$YxP9*(}^pvuGg~ApnaO0kCK>0E>16V9`zh zELsAZ+fB?3@)*zto~tS^h~MnMJE< zZx-!BHjCDf&7!qrvuIbcS+pD3EZUuH7VSYci}oa&MSGF4Xm0=(?E}D~eF0ds9{`K? z2Vl_w04zEXfJFxZu;^d_799e>qC){#bQl1O)&a2SZ~zt^0l=ao0a&yifJH|Eu;^$2 z799h?qGJJAbR580v@$Dvy9g3Z*MnG_S+pj&V9ScAUux0GS^gWJm_?`1-YhzmY!;nH zHj7Rtn?+}k&7w2OX3<$>v*>KHS#%EBEIOBrMdtyq=zIVcT>!wM3jtVk5de!W24K-8 z04%x`fJK)9u;_9C7F_|rqALMdbQJ)Lt_EPyH2^HS7Jx<90kG(L02bWMR#QR8+~pT-AQ}1=q|EZbT`>7x`%8Q z-Agu$?jxH;_mj<{2gqj8gJiSlAu<*{48WpC09f=W0E-?2VA10MEP4WfMNa~-=qUge zJq^I3X8>6AEC7q117Okf04#a|fJH9?u;?WK7QGC>qE`S|^eO<0UISp!>i{fz1K=#W zEi1ga2ofDzAmZF^7Ht)l@Mcy-{ZfnG&GL8p(kyz9_GZ!hWV7f4vRU*Y*(~~qY!-b? zHj6$Xn?;|J&7#l9X3^(lEcya~MPCB2=qmsgeGR~(Zva^IEdYzY17Okj04(|efJHw7 zu;?cM7X1vsqF(@5^eX_1egk09?*J_N1As+dwq3SkQ3!xVod8%A24GQVfV1fBtnhjf zBzl~F@A@6HXpVkm&CiagUusd8Z2zjS&7w5gn?>nlvnYdX7G;vnqAapmlub5^a>!;; zF4-)KlFg#7WGw0iz@qK|Eb0Nkq8I>+@&H)W6M#j%09e!;fJJ=(SkxDQMfm_M>IcB0 z0ss~j034leL0kCK?0E?you&4}xMNdd7EM%(hMPr)>DhH%c0~PBiyE{2 zNk5oHO|&!W3d;k_L0ANuI0E>12V9`PV7A*o`(P97=?Fhi4od8(01b{_L0a&yQfJMsz zShNCwMLPqqs1<-kD*?`;S=r%vB1rT!{bE{!S(L4p{cYJ1^-C>UlkM;KlUcNu_GZzp zWV2{DvRSk{*(}ZFHjDNmn?-w*&7ytCX3@T6EZPr%Mf(G==l}o~9SFdpg8*1` zFaV1V0btRg04zETfJN&7Sadi5i;e(b(UAZwS`WaYqX1ZRGysc^0btRw04zEVfJMgx zu;>H;7M%!i7Ol<>Unqh^*XluR7qjSMwdkbmi29`#otEuC^ov<^I_=G(GstGqnPju* zEV5a2HrXsXhin#|OE!znBb!C%lg*+F$XIkC0E;dHV9~_@EV=}MMVA7w=rRBnT@Jva zD*#w@B>;=A0$|bA04%x&fJN5=u;@Af7F`d(q8k8MbRz(ZZUSJ@%>XRA1%O4j0d zfV1e7?C|FzNOXim|5URmRll-!dv-+qQj6}+_OpLCi|(PlS#&SiEV_?u7Tr%aiyk1G zMGunAqKC+4(Zgi3=n=A6^e7pN9s^*};{Ysr0)RzN0Q02VzBz@ldWSoACai=G2u z(enT-dI5k%F9NXWB>)z^48WpS09f=Y0E=D&VA1OUEP4ZgMQ;MI=q&&iy$x^{-I*O8 zC4xjh)6dcFGK=Qu_lw@ij;LR1(FfUnv!^4F?_GaLd$Z^xvRU*o*(~~mY!-b=Hj6$Z zn?;|K&7v>JX3>{qv*;@_7JUuCqHh3L^eq63z5`&<_W&&V0f0q60O02ciWz@lFO zSoA9Zi+%%O(eD5(`U8MPUXES1V^IizMV$ax6b4{XX8;!Y04z!YU{M6%EP5|HysHQj zJ)@V1^S)X1rXJo>b0X@OT9lFFpVG-J%A~znltng+vdLyq4%sZqC7VT2vRTxXY!-DR zn?>EpW>F6^7R3Nqln20~o&YTB1;C=-04(YQz@okYEXoI9Q9l3{6#%fP5P(Jf0a!Eu zfJFlVShNuUiv|I(XfObah5)c=C;*E#24K-904y2?a2BQIgzpqVqG#!;P65Q~|)EN&psB0kCKq0E?yru&5eS(IA)7^8lFg#6$Y#;jWV2`+vRSk(*(}0kCK}0E<=tuxMuh7PSJf zXe9uP+5lLz3V=nc0nVbPoN$c@5`9ZQM{72V^7OKQmz;?Dr55d$<1g)E7VS=ZvuF>p zS+pnFEZU1~7VS+oi}oR#Mf;M?qW#Eb(f(w!=m0Vn9SFdpg8*1`FaV1V0btRg04zET zfJN&7Sadi5i;e(b(UAZwS`WaYqX1ZRGysc^0btRw04zEVfJMgxu;>H;7M%#dqLTnv zbTR;oP60TJ*5-td7D1vJg(A+bX3^bh(WyBR^-C=}GsnLs-7Gqb_GZ!9WV7fTvRQO4 z*(^GbY!;nQHj6GGn?)Cr&7zCQX3@oDEV=}MMVA7w=rRBnT@JvaD*#w@B>;=A0$|bA z04%x&fJN5=u;@Af7F`d(q8k8MbRz(ZZUSJ@%>XRA1%O4j0d02bX2z@j?Y zn?+lb&7y6{X3@4}vuHcASrjLmMcb3jqPb+VXdc-tnoq`}1pq8+0btP%04!Pvz@kL} zELse}q8$NPv=ab}mH@D5DFBO>0kCK}0E<=tuxMuh7PSJfXe9uP+5lLz3V=nc0a&yP z0E^ZDuxKs7Su{I0JVpeG-k@jKbIhVI3nlED8&SX1qCIo{**(poy=ZS1?M*g|_92@^ z`;yI~{m5p~{$#W00J2$hAlWQBh-?-eOva)^09bS=0E-R-V9`1N799@2q9XuUbR+vq6^4o(S>BQ z=pwRNbTQd1x`b>NT}n2KE+b>nR02W;hz@lpaSadA_i>?D;(e(f< zx&eSiHv+KeCIA-Q48WpW09bS@0E=z|VA1UWEV=`LMRx+Q=q>;j-3`E^djQU&vvR|C ziy+bMGDMuS&7viGBm3Umi29`#J(%mi)7LC|i1udD!(_AQ5wcnIDA_D}jBFM?PBx34 zAe%)`lFg#0$Y#;gWGs3HfJM&&u;@7e7CjHZq89*I^dbO@UIJjz%K$8T1%O4b0c z02aLtz@j$*So9_Ui{1iY(c1tldIx|-?*g#sJpdNH55S@i09f=Pz*%&EZa6hxEZV=f zi1UD1v{--D_)%^|{ZflQ%k_sAm_?t{-YoipY!-bGEc$_rMLzGkF02XxtU{M+Xi_!sDlmWn^On|fKliYBv2on7ySH$_$Ec#eK z4#|o})GxIt8ugd=H;cN`-Yn`yHjBEG&7vM;vnWP3i}J{3QBSg2)QfBu^(LD|eaKkU z7l1|i04(YUz@h>G78L@ps6POU1^}>VAOMRt0$|Y~02U1fV9^i&77Ybp(Z&EQ+5~__ z!vI(`9Dqed04yp7U{MJGi%J1lGy>o(%87=L6+xnB>1A1N)LrSHF7o&zqY?E>EgBp3 zuN!CMHK)n zssvzB6#$E-0kCK~0E?;tShP6+i)H|@s0M&VGXYps3&5f}02b8)uxJ(liy8n})Cj<$ zCIA*S1F&cd02a*#IEzL{!!L^<(XaKRvoU7TrNISTG@^c~McYLEUj~^)+tS`F+Ky}% z#mQ#T_GGhYF4-)aM>dP*lg*+9WV5J+Y!>Z6#-fD)ELsG>qQw9#+7W<7I{~n02>^?h z0f02Un&z@ifXSac!)i%tSy(a8WTIt745rvk9(GyoQz4#1)_09bS;0E^B7IE(g* zhIbG_qUTEV_cn{Z(nn&Q9gV18UJtL6KcLH1!$MwclALvWvA8^rwsUMB`IICzc8(kf zGh+A2NmWkl1KFK*i)|v$gv^WWEK>G~-5_6}EQskNBL~LH<^NDKBz8!l=M9TJAs@Gt z#JUgiyiu{Ohj`w&*jXEU-o)4k!#rHmwvTOF=6MTZ=ahTiqS!~3p0^}cJl*qF#8z$Yd2O*I*rRUumyI_^) z-5L9A7tgylHgZ?bdoZ?kch7q?cE_Hc_hii9$Mc?z&DhWLUW^@efakp$d*L9@do$Me zP|tfeHh-PxeHgpw2+#X8_QiV7`!Y8A7|;7Qw%c)@_ham?6Fl$NyvWJY|Dn8@r^*Tl zh38B18E|9el%KPdfSq-7Qv6sqv2<7Sj&3<4g zPycu1Lqd7_|C1gT%G3WLa7idn|BtStLV5bXLwWj?qy0m9`k0!7LwWj~ zk#(UweNe>uP@ewM|JYET{#5(KP@ewQ_S8_G{#f$NP@ewU?c7kF{#@z8P@ewYRer5N@P@aD0^43tEerfK`P@aD4>E2MDer@H!P@aD8;L%W?esKI` zC{I86dp4A(AKknd%F}!AuZHsU=INWEJiYt%ZYWQ0UwjzK)9cSqLwR}u@ntAa&j7y- z<>?{($55W`gMSTqX}idV;-Bj_xt_1fwv#d{w;LMiXEBWRbK1gxD1J>emf%M z^{$rfCNy%|Sa~PMz3KJ7QMSF%$nBLKCTutP*ZTyyJPwWAP1&!KrANFz6Z!}nopq$V zo)Xg4?0J0;&Js2zU|!!NHH@`zo@}|HaarQ040e&sX=uE?(~vJ=f`zfYBy4J7GYu0h zOp&LZhbCDVG(f^;F7)XvCpV$VLAX(7;zFH~!(|r{n&Jk?*ICoW{cU*2>ldo`Gp=}l z>mB=rW~JnQc;L~G?%6NY;Aiw|og3{JYVb)=DEtrP~fBpX9-KBL(?i1f#|Ja(K`Hi<9^4eN2f1S0ufmXjCd*m}RtW0vk z^Ji`zG&*SSn+}pikU4Me^?0VtrL-9$lYE3Z-`mUYBwt<7se8r2(xj|DUc2mW8XXIyER^ZgEZ1E=;j)AN^SD;7YNfXm}Vo&J?xA#@7*Jq zq3I8dXbi@)bjKO}g8A9)x8~ivf<@9K=z=M}n~D8hTR&sKqiK1;JRES-QAh3-EX?}% z?mk9)z|VMm{-b)6Vp5PlH*U%>80czdDcEh>Z(i0z3|jK&v1<{`)QL>FMk`c zRG0QsCiK#s7s--Io0slbf8yF;CW{|zbxpp@UNXYV-_@EFh$>=8O724kTy&<)l63TU z4}GvGn9Nh>e{zxZz0BJ?J5Sr%%YWP2G`co^#=Ny}R0orJb)OS{+%=fY2Yu3u-Qv7@ zRWGlgMs81zRvi|}3+>zGu5GBq%fHvqehzg?ZT9k?7pC2PJ(GyPw8fNQ61Tki&g&|T zpK)N#+Nxj@RU;evc?B;^lc2jh%i&Zf@eJb=gL??m@kL5)LwN6lSm$6VzaQMg>Gb;g zJI|E`7lq$mcjhI#dIi0t%~WZVKS*9^w^q2uDY@r8xcAjg#y`Heb80X%J3myL9W=i6 zyVFkH&C4Gqdme4G3log(^hqR`VA}eHGNi1%hu(SfK%JnUvC|C~5A^b<2Ro~fcc^Qk zU30dL@L_w8^@=*QP<6A8)^4A5m3i?!NDzyg+SB$=&~xTOQj}47Emw)2Pe* zk86>V``i78{Gpwnl6&bjhaBuW;ge4f zK3{hQDY*|{w)bg!d4;E2t6*U+DgAX^Fpbe&-YgI1>yabQ`da2thJW+=PhXN9egEwX zqtP6i(~EOsM`#3ClaX$RR@irF_*XrT>_Lo~Qp(UX<{w?DO?s ziZ6q`E0foMDIdx^p9|H0DV@V9UMM%TQC8RVa8~cE=2&hhC+2yb272k~n+fu~a1Sq> zH6eY|^zrG{UFB@V-Vw9?(Vmi&&Y^JDX6fnjwi_%YFfv41=_*VOUdW!KOYlOD8)-H| z-;FRm6sqp3P2{_#)m@9FNoKZ8T*sW%HI$y-KF;h+FPzGpq^D=5XQYpl!E<6AhRT(p zlIAyR(WchbMk!IJ+08~7yxTs??lwvrs)sc4+vg*eDKn~5&I?}1vh^I5G|kC9C(2Jh zdKHBx_hd!}_pI)k8;Yh($va_cPn~XWKdC{d*bP&q&-)~g#8}^Crrnu;$i5+2U!_5h z^*eOmkk={isHt*%Es!@neZ%t#8Aco`@^p5VWd(C0i{k}T23(1Sz1QPKOO0;GxSw`@J6#1W@FYF`YJfB@|u$-oOmgnB~xk8 zqEiWZv$eQMG-z>cXVailr;z>;gZj9{PF~3w>*RQPsr=K|TAvJFk2*uEjo zqIG#&%lx*M1;z7Q*RE(=u3&!4f>o_8E0f;S;brLY#VcADFJ0WWcy)_cylDB-mg2cf zTGkX7Em=N)?vmn_i{`er6t}i4YgsvWWpT@h_{z3b3l=XgZd<;5$^1og7cW~`ym0>f z_}tc|#ib?jk?|2FBTD0?B?^ZN9KLM%vXINU#w|s4Z6hjNPX+_9i`7# z7B{Y#+qzTLs%7yeS(b(MOIEFnH@auLlD2r;+7&G;ix#Q7BEo{j%i1J_Jx}zD&tJZD>GEaqxhob66RjJ|E925B z^UDJ+Om;iyxmYLVkSD*H@q=w4JTm0_UH|US52b_`hWzf~o<)A@MBh)@#*e0iisZ!% zdC}GH+D~2g{(e2%7eiLH^^* z!j$fQ*S`N|GW{84iC?HQ7R<_=UCts2h%RlDywdXLrLlED!XfeeB(C z!}LW;H$R#@e4(yw?W0Mu4qeTcnp)s@NeO38^m|C?B1-&SjRo&dviCRhH_~jYCEMw; zk?9h|A{pBVzo!m0!;e)(NJ=6#6|w zex^<*&+qD{I@G2b#G>HMPBP_<1$VM}>=a&G;P+NA*xoPR;QclB{*XVtA2ciYJFJV` zDJ8tR$nUAIT$ku%2Zl4HXN84Q2Kd%L1A`cHQTu&FV!>TUY}orX|FD;Pq{RH#P=DZH zKc-76T`e80t8>zys$0GEaDSbn?teLdx`J%}WIgngRJi2^vs>)zW||?L6Bwksfy@%W z*L2CnU5h9Ay#@3t_J{WOd-ql52Sc#I{mtr=i4K!?y>+Z5vf^!ZOE3O?1D#N&Z2bRx zXq~5gor3FtzaMok+4xI`mX7gzhuaGLUW27d54(jCBiomXrTZtf>u_ni>FP zgIOum z>Hn;Miu>D4vw`R#pnbMkjQ?9_Kj^7{>gJz&sMF+bDsy)yarWOh{pWW7WJ?h9{>@qp zHYa!1A}90RWjpPk(pA=t>Ruwdwtwxzzv`NQGVny1mtY$&_PdK0I%|4V>fcZ2afWS^ zll%cDP?6NU0y$$0_9J?L8dc&C$`@e0*U#-oM%lhKh&ud;;Ar;$!+{I^QT_cvePs~} zgGKl+OByVAfgdcloNuNKl+GM9TwBl3=KpeR|Hu37|F-%0$2t}JgGIhUh5qRN{$O1@ z?sTaqCyVCc=wuIdeT)dsKL>3#+#fZ-AKWLYAtU%FBFhPq%z(5ArawqeiQ4CY5&gO9 zEVmD5XAu8+PJ7Pq2Ulw&nV@cNgJpB;*I$=TF|LgkE@%0?xkJpv!M$)s? zAMa*qvc6a1PtZM9p|5H5NPj{wwuTah2%$Y9G^ooo^ZZ zf6#lu5{>XDxTOtJsXyWGmUcqWv$~Gu@dH8!DVZ3>V0rX8t9Q!&Upvuk=ADTug|^Zj?V>qN&~$~ zFtEQL%a^NrYw*{%D&#uxkkG`-f^+_1{r!IVaw%X9{_-lK({#DhUe#D1uWV?DSJ!S) zR#ROOFKd|AJhQU4$>WWgm5q&M(<i7<`*-+V7Ung_u#xzQXp)YjaD;vrhljfX$o7p%mKDD{3O2*$< zy;WtR$)A?2dZzYfFpT!()RN>Gt*(tXGvV-AlPb5aM~;ZM1xrxTq50Grxo_Q26|9EJ+A@h1UR_mVysW~FW^^#L&RJE`f>$<8 zr+?%1)3=Pvx}GU(xxB2Yx~|ss)A&Tg((P9y)`qGV3M;5HMcujTf zj6|=^uCA(%m(>SzSzcFLTUoBQ1m;zZ(hdt=R+tiv&E@4{X`(gC&T6h~u8dbnPbJ=} zFKei7+AX~J=TiU8?A4Ra*8tWQ^Ij9h;6EiS6m_AEk!&Q~a_7QKatE!537`SwN zhoQ^MYU51}WwnhntDAx`H&m8YY#A)f)DFTnG?vMTf>kXYY+^Iby2kQ&V^f{(KR0hmj<0Pl*LKd&+8pDaY&TD{B+)q4Ly*>S@!PYNbcxjg?JJx-B#5s`8o{!R(G4 z<+hyB!4!jumwvVrC|f5%*#7$iovd>qPlEa zyso*azPTyBMO{skY(I%nur=sTMRz~C>q^=>D=N3BmJe#CHaEInmTe<>f8;hLm03Dj zH*W2Zq~;BCWRs59ZBf}!RZ};6!-+Q3PD|`I#jCQJi2 z#7=TVqQj;pb&jr}_DMV6lirpUAzc!$oKs#|S&=l$)*-ToZ7P#J#Ei-<<5gwVx|OpI zZ3z7UOJ=RExj|mYHda+rUEaRe4=mN4S)%JoMl$=*=zh|TVnnckELpy6VS((l0yc`#m&yy;N*^}XwI8N*x1V^=_PY(0 zHI>1>Sv#w;qepH{>oUvAtgdpM;^tsX(o}-|j;`eV?R%`!%EX$}mxXnc1?)}^v%q=3ODz1)K9!wURhJqTvOH{l25B{6rc4_#e!fJ+q|2{5@{YR zVuzh}bK}(Da2;=)F6Sn0NZFmSV@sOk%u3l+*+~mi((#qbUedLz3_M!3EP3&D2-*85 zX1roVg&h(bDr+mm)};M!Vg;86CqL$l^y0FGE%BCR3l`5^7T0YlF|z8Kn#yTqHMYsg zQNBX9`S!zH;CteTl(d#h$8|8?RGBVgN;=7^V6kN7Zs0_>Wzt6|iR!J8&PEXozV|z{6mU@!8!I9Z@RYPTYrR+r# ztK0S|!3x-6)w1~|qej^>bWl98t!!|pz@DU&=Nj3T+Wldkrj^Z{S(cb5?JYSsqmyKd z4<_2aS12tF?3z~FTu?rKe1U#HHO|Ce2^o z+SamW_|lOh1+*<%wRE1;9hNMg+csRjdNWD(Aqy19kUOkcJ$m@c6~h;ljuA4qb^fAB z@?D(O*<``W6`Sm^qG0&Kg5h-|3Wm#rzF9)ToI_axMunC6{TKKM*L}BIvnmhoJG%+F-@(T z^QRW&HF7kORP=su%OYs*o3k^lCdmay}lsa2KHgDoG6GUa_-HIb=P9Hj#ZbgI+D^~C8+ z`<0dK3tdObMG1>0y^xq|PPLPz4?4a)=qlzx=WT;Sd0C_0a!cH;k!>h3(!{l1+0@|X zTjGtRj%=uG`pa|jV1LL(xz35Zo(twlPI6=!m?ya+mCL^B^6KD_Q(q=WoM0$9Znzh+ zeRde!-H$AvE?3HxHNhZqp_~|9Vtc8Y9dDK!V$zv5LK~ml4xUPeN1xs z->Cb=b}x01zdQkE<#xEm*Wp||acdrY#^66~i=FbRj{^&I#9mUA> zoWt8O*!Sry>LnV3BwroKP1Wjh*@wtJy(#FY#88cLAuKlz?B)Rdmh@Hd|6N~zu4tLJ zYGKf$db!6;>ZVvW)w$(vJo64qSS43+a={y~swr!1Z^ygM^=h`>N#LIP1{Yh2byHqd z-o9Q+_0~31vil?M7#XZ+cVAv#Cg0u;t_C;QZ?vC9R#g7Yd8Dr3Ei2uXF_(lLw|$kD zOA}7mg89&U)xisQ2YzPRoOpR{lO0TwZ$JmL_UA*RyA)$N6F2IDQMTX7E|vRg$(vI9 z%^+P^w-I#M`6Mp+b&QE_O!h5t&1`)e+++?W%O1S_*yZjR>zjJn7YwAgPnqlBU@Plh zye*f_?5{u1aJPrsk3@gk&6MgzK`?H;)ylY&XSu4nMo!3*?7 zQErdgnZj~+x*n7f?g-gomY9LWZaUFnNjomRFl0a`;Y3dyID;ihzAYMvkbK zeqa*(GJrXAyZ6KmI&kng5W5qg`qI$sc8$6thudynWa)TIH|e5DZVd(N&s`4Ht!fLd z?>4wq;;!{J7%N>TJ6Smf+I53{_`{{x*bZ9&E#x#9pH|cOQCz!obJGAL#QvmdqYw*I|7S@+sD3vDPZMCuLo&74=5R>nAb-Z-pR4Ev# zbZ%n4f~{GOfK6o$dTuFOoSet}-Bz7+PuS+T)ZNh4(YlKTUCI=T3?HqOxz`1jsDo!@^Q`J2x1O-aQRoxbtqNth@J)N3O(1oxB~oIgwEW`-DV) zl-HEatWP@ZJ3aJcKOJxT=U?qt4yB_KyH2)=QoTRwX05~isjOa3@aM?Ybq9fyX3zD5 z+b~!j{8l;TljaR?i3TTGRb|O%FtlJ$os*;s5;=rQ@7fKS`c?Dfo=h;a?x>>!yXy#M zpx&LF%gw$-F9p`ft|I};XI6B$LKUM~gNb#StX=!ATrTv0ZK909f*mU;vdM9xi z#`N_JA~-bu)g`Z*q$+Y5r(>zIWh|AOVu@a*FWfEEq;D6vYmcCFlFw*^i^SRTiLriW zUS}TyGfVDnzkXu4;ZZ;joBA0$J0?D(rRCI`vf3H4IakW9v<*(TbWt`OynV&g)X8Up zvU8Dpuw}JLx9oK7biC!_E_vJ)K!*c!u#D|DXWa)G%vk%$UWW@D9ldN8&9Yd`n~ug^ zpaiejy}J9K@iE=gxOdRgXnUV2MWyUXn`m}0Q)H~!scrq*-JR^klIUE~C7Q|~-7vfzkQTh{)C z2VHj?c0zqT@d>5&C&!ZZak#ZJyRKn|o!%zS1xh!(k6KbPD&E?@Da)RR4^28=hE>Up zNUmV?dmG-g^707{4u9~J9Qi~o>6 z`8oUUSs9t$z@#4<>+g)GW)0adZT~I@q#hVKDCJ=Pkj{sO59@S9$SWH!1J2c-?|PwP zdFhWEKC?)!PinoC+{nx>;k49f=We0yp;$OC)HBp8)H~ECl;5d;NFK-Xr@v&>+575` zCq36xJV^CjEuw2d45!hNQpF!83gd5`($-Pfg1D%%4T_d<6IB-hVSG z>-$UO2@uKe|Cp5Z{VU}+;k?f)tzj=Qq5#W}y_4UT_Y)(s_Y)(s+;M5bUiJp<CaLy+_r_M%Bi=cjuxg!Zbg->CFgWzrD3ER7rF9X7~q8{~aA$j5AuPud_~utAom zV;{i($Td-+jV0j)=9?dy3% z#LG_dD5&41DzBB_OKbb>wMu(^^pLinD8HH3_qVb-M;^nYd9~Hotxgx+(&X`03$)63 z?zH-}RvF*(TJ@m=qM^PY)hb+{k&{*+&#}-d;~gSTlF?eBRfap=^5y5H#}|3fmhS8I2xG6}DfC@Z7#I*H0djO#u|hZ|#clGUkJ>#gd8 zCv>>^R(G_zv(>$LXU4vigG6*Q~x{^&_iaSpClGFIM#t z6FQ&zfArHT4@3)USF8HucIEx7Ze(>6tMWjf;Qg^yCs{4GT5Yw?YO~d?tQJjCR>xZ1%xb088mo;~^+7B;{<&5cSzT^*wbebW z?r-%ltNJ`LZGV#0Gp$}=^>VA%S-sWjJysvK`jpidt-fLPeXE~Y{nqL)Ry*l_MW)}y zYL3;I)qJZPSsi9|q}2&l%dAefT4!|&tJ_*#V09;}tyb4s-P`IxR*$fHoK-zO>-?T$ z^2A0wyZ-O{S=&owW!y3Fb-tGip>&+4I8kFt8A)ibP~Z}l>(*IK>B>fKf! zvKl-uN2dRR<=3sgXZ2I7-&pT6ctxB7+EAFYPuJVECp&1yHRBdt!8#N#F*TQ4-CdpzrTGx6cgwkk<|nMC$~lte?pAB%+(z@(R*x-o z`7En14{-Sds|ABx9&U99Il<8OE3IC-vCB7E{d$Z=o7{>WRj$=wPBXaajPdbx_qA1*X4vum+up+1LwG0YIVo0 zT;9d%mD{*{o7L~Pb2%J$b>duCtF7)k-{m8%KG@>&b5^q!x!l`o(~d6BwR-XrmoKpT z<}#N*vpQ&Jmq%J%veIRF&{MEnSFdvQ4y!-z;8HDViPd+{bonc*8=vFySgR|}b9oP| z*I(fBJyw6c$mK2`Ee7VcVS$+IUmtV2k?HZR0t!{Ol%L}cZd4tQBS$$tl z^tFG!u{!Klm&aRez1`)#tloI1%lBFR{ce}j?{T%_K38X1J@f&WPq6yrLoUB&wa23_ z53st;<1R0@diIkpUt#sbr(OQeYSD8pZ)&ye1()}+dh<&zKVa2+)#Xg9Rj<3;Xm#D2 zE}vxe>9<{e!)o4pE^lOYyANF6$?CZuxqOw?k3Vtw2dgEYyFAJ2>Mvd1&+4sTyZn&V zPT#qlZFTw&E;m~};wP6+vHGlBVCnjN%WALRT^?+8d%2&a?=Q7_zC5g2^EFmKm8Vu~ z{>kbHxj@rA+3Fg3j3myxi)A@;q$K*IE5s9*nK|7ptQRTrRV^Yk!vyvU;aHGh2s$%xcPDm%Cc6 z8S3(uRw;O*%t1Qp&R-;8OS6Z#Ly1&&M ztv+fsBu`n^_T8;cw>rz}0akCe`kB>2c`mWGYqGkn)fHCvw|axsJFPxzHC1i|X!~5N zl~&hSJR78~Rx7R6Sgp6ZmDTO6 zwpd+k^)RbPT0P#X90r5wo@Mnst5;Z+!%p!2%~o%>`k+C7h0WSwZdwR)q1OQtZrj?Y}JdJbxWd|Fp_wY*62_;R3(9%l^o?SG02N(zdztq_(xXx`J}TA5C^PRB=@U3xW@<#_k_kT*q!)8$akbWciZBQL#I zhjoZevnM`KVVd+H-gf1oY zBGOwDkd8FzNR!@sl_ny+qX>cmiWC(DM5>|!f`Fh%5tJq((nLl1o+o=>zJBNYJx8+l zMP@VE{0O_r0vuy5hCMRZXFn(NA3yiD3IDymvj4e0`<*MU&wd`{7<(PD<`dKCZ1z&< zKYq@B-u&KTh`i63qWx-xubxJ;r*l|4lPr*dCrgblLuBf6o4YN-udm`w1-7 zH2&lDE}392^Irq=dKDSwrG2~hzw_q*|DIoi|GdAM%+GOtznaU&a)0w8{lCfP`YJQb zOWu}!`JWGa*dFtGi6+>a#(qw+*Jp2c`!@NtVJ?PUoEQk(Z!hRSt}mn6|9!o7=KLP> zO6Dc6$KT^ysYJh$iRQmj6_U$WOfFrqOtQJ0oLuTZKb9|F)~+(i70t`U#E#M9>NKeP z-@ljJ{7U%udhMG!Ff0A7xS?O`g~M`~_oVpshqYEVIQekJ4m_Nkc;KNw;K0KJ$tNF1lnQ(5ukWfqSYCQz+M@b7`W$!|ma%pEk4w^jJlkh( zifN_hrmgNg*BpB@aZc*v-~V|$KGFVI|IV>mQ&PKhZq{pA_@k3E(zvkWxw+iv zURcNJY2#AscS$opyEwg!@AOjIs0K~CH0#`@*Ai1ErAduqX?6ukdo93IC zcH!Zn2?riVx~Fze>G6MDQ(JRQh5yfM zib<-SqVr0Q>9II;O^vJHiAk!OdZ<%O$4otzs5QEGv{|K;W1Z}6wba}W)$hz{RxZ`v zPWD!8aA&Vm>fhTjA~E$&WK!|eX`RwK&+FOB-G6s{-apNI`(d-f_2-ytsFi+8R=+c` zOa7Evy1vvq`<%T0USCpLo|Ji=8$LKzi;s={sO3oidHZq6lh&+rmegkH*JD0vopPlG z^)a$%Q#h?~YLS#8_3iB$`j{6orLao%2jSs`(jrqjcj;o@w!Jn}!t$pD(m(EXE{0{u zT0Jgje4=&QZ|dk$Lw;JZGY~d4tkm^}Lq9mQzN9}pJZ$ftu<^&t|ADaSVa1w#7WU#( z`)c&RyuIdyzposc92*wc-#c^mw=!-%vhUu@`Tocr-8kckBAGY09CvWlg#v4LeRVcp z;qzZMMt*tO-`_y@f+9nU|a)Q$M5$EKOJ@Be!nFQ!XCNsoU&s;NdvxBn>Fl+;P@14ia_a`L{A)~>$& z^;Rq0S^WpGPOEe!_9L76;F!}q{rc>$S3j{`T9g00x3wR{CN=!`Ow4jp(%+gr(yqGy zIkHh&&Ho%(_d#rzs{bBoR;{Q1J<_fU{~l>q+4P^Yx34`e`QPJO<*jUfrM*9X-@}NE z`yO8W_wzvc^jmFm-EwK=Qp=~5uWx?E?fu`c^+V>@dg-($&9CVHeQpbV=BR%s!Tc)9 zZa z!ZjN{eDl)b(FucVH(0mnNY$;!>Km7h&HsbVF=2u6f$&O!d85DUzM%B|Us}{`J)+9i ziDRt)#4u<4N+&R$&(+t{KNC)_J11>!>fDrh=5y5lZh_fpb5iG|%uT|B3q`pdgrI;Owfj%h7Z&Br#`9NVSKf8M7isb$Qv?}2^K8m101tDTnpY`(Rl z`CTTtRoGvr&X}KXlzO*gqm;&Jjni+%eEF*1$ycVj5mn6mZWEE*CHPu=i23YYH2poPo|Is29s8Q!o7XJZDD)a(pL{vVjVZik>#V2p z6uC9L^3E5+k}@7Syl!&Fk-yyEH0hIxf0{cR)wfN(7;ar}NZhjJiDN^HjrwTwKYdoY zJq~wRv7v`sb8yu?xz>7Dj+w8bMoj3`a?YlQ5$CEFE%Mvu=8da#UEZX5!jrF_t$n)N zgCRv%=DoVP(&G;sw=LR#@zfL7ue4lHC9HLeYDbP9i=A@&!0sPw)HhEh2!ypaUk9=G z#mw~us+h+Jv0D?v!alS2O8@g;cp!3^xw9G`@CTdwYvJMU2J^@=Jlxxs*W4*9k-}xM z@)GCmiZ76$ya=7YQ_;BPY5vN+&BFz@`5 zfZxFU+|q!b*PPO_fPd4xp?d*8gL&uf2mFFY(1UOrCzd8P6^A;LJ_|462)G)%YV9xs42!E{k=r@Y+if2egRr>l&jiBmC3mc6~0w_YJUC5q_$1**e01*IZef2;clO zPGM~${8r|}*3K+rXH$ef*qlUW*RNsTqb#m}(453@*KcTUr4g=Q(tJ2ay8aduzjysL z<~q;0zWvA5&b$6O1MPzAS2Q1vi>|-YoZt_xzsTH5mt4QAIhSLef7-m}anJwB9R9WE zS2S<-gy)+(cwr|!|C~9cQ=UK6+!Eh-{$UeOd;Tf&9-Z<0UFPs_J%6G(-R&{{HFMK_ z6ywh@SGFU@zhK_N&KTeR^N=eO{4>Vn8wvg-bMmVa{JZ9qRwww|%sc&Nf}h7+=b8k6 zmbuQg3H|`Hre*SfH}BE(O#YkZ@C=3g>GqdHA-|`2Z~JHS%bRl!U; zW3H^`a(|DxS!*x%7bb><)miQ*m>Z<-a^HSAvEFjOwz(x5@AqTPTWGT1Pc*O6@rK{u zyoF9T{4{gAop1QvjEOEc{Nm<)=z7C%Yfh=#4ZnhUA6~fO2hCY`zY*2X{9ONxfv~9Q zM(+T7;eol{f%Za6b0ZD17fzZp9BeN{8iqsc1^dj$q4q*!b1mb|hcs%ZdF2WALPc{u z6YYiZ=9lm!dtpUB^Us#r3m==0!Atf+8$*4Hy>Q%|%hdGOF}K>B4yM?D?`y8Tkjb3w zJbR&_c?aj)3)js1y}(|0U~cyjUCf2T=EO$Y3wOEZhP|f@zG5?^Oc@y^Yu)Xk`f#ll@>&)AVvKO|Q4@9)RP|RF& zjJ>eH9A)lMg+={p-a+$^H-$yjGDpSR3s=qUonS8v=^3` zTP%~kkja$H_QEprLC#_?+%s>>o^@0n^WigJx(|yQXih%dUbtdzRr@sRsDb8JQG~r< zZUggPm<#q%Jr)rN2i|%O7HKK38S!s66tLBGf zbJN9+HW$p_%NvN?X5MmKgzfPWZb8@n!^R0Ulf&FXS(lj>5qQ$fQekdk%{*q74s(lW zK4E5=Ft?~?ZZpehyg+L`P&XI54_Xtz1Fa@rZ~Hs@AeJA>Wk|-J*^#Mw>iHm+R=8K^Ls`+%5HOhRkeM)&G}W+_Utz2 zS6w^OZgYM$v|YQ+`PI~pu-lwpEp77*^qQs3`PJ4AH@l2EzdG6hyUqF4)ixjN3=!s^ zi|JrK{u%olPHutB7C^@S=9jr!&wIxHdNV@OT>Fn+rweJILnWl4ri47JDItwCC8V*Y zgf!8Vkfxdv(o9oAnrli(3r&Qy)JDj2+6ZZ-jgZ#b2x+5@kha{`LMCe?zW8z zsf~~~v=OpO8zHN;5%Q)sLe^*_WUV$r-qJ?M+u8_Or;U*H+6dX8jgWV=5%R7!LN;n6 z-f2Q(3KP#YniY9r(` zZG;@sM#$&d2>C)AAzx}EHHbTDB4hh-rTs0s6j4RBYSofolkQwIgy?fTPa;%UG?p1T|K3&K~ z9V#I|XiCT>O$oWIDIq^&NMf{x51q0 z69mr&bEbI+kv5n!eUjkXV9qp=5MhHk)4T-726LwQ2;nB!$2v)bfDPtM^Aik^ED>&a zz-erN1fR7JahyO%(M_wUK)|!StfC?TcYyiSldh;J$4k*uY$+ydK+)3#6jdRh=otcvsuECC zjew%+1QgXEpr|GRMYRYhs!c#q9RiB#5>Ql+fTH>Y6r~VCiV6jsg$78lqWvOMVJRAC zzN+G;20ZJ_Dtb2HZZludNmtZ}nrKl-eikh*ds5x7TTCk<4C0mM~V@pvh zHi}vkP}GKiqP7GSwIiVDc>;>s6HwHFfTE5B6m=q?s51dYT?i=ZNPbLRF9M2s6HxRb0Y!ZXDC$cHDQXaKzBfREz06nZ+=f!r*xbc&`vpAf%PJZa zaQ`-6i%eHEnB%2r2wRGVvZZJkTZ)FWrDz0Oibk@fXcSwDMzf`83>!sb2`CyzK+$*t ziY5?HG?9R!Ndy#4CZOmg0*a;(P&Ac*qG<#aO(&pe1_4Dc6HqjhfTC9jD4In;(W?X$ z%_g8|4gp1T2`HLJ2q_v6aPpbo%!2#u9p`~kl-rK^0nhrfiWUdlTITx^>57(cyc8{E zOVKj66fI{<(F(Q{y~dWJ*V$6Ek}XAVu%&1f8%3)LD0-8CqBR5*ttFu7Edq+(CZK2? z0Y&QxDB3_k(K`eby-PsRMgof7BcNy#0Y#e$DB40m(N+SA-Y1~w0|JUZB%o*;0Y%#h zAw>%VP7eblIMLoOS|mkltfG$sp7muFeH?J7oA1-4E85NRQuGO1iuSOjXfIoe_OYdC zKU<0pu%+lATZ%qqOVMX+6dfX<=yL*!z969JO9F}x6Hs)7fTE)W6n#ZN(J=ywjuTMy zH33B@2q-#9K+!1zioPMB=rjREX9y_zmVlz~2q-#BK+*RE6rCf46zvQ+8x4@)a0_P_ z_lwN8$=ve+&-${8E(P4L%=fp_6W zOVLd>ihd!W=oSG*zYTm%&5CZOmE0*dkwQ1m1LMTrCys3IRo_1Qewa zP}G1BQdBhD8E=3DKR3@|ai5Z+1?CIVZo_cT`m&0egu8DPm7=B`FGbDRQq-I+MJ?D; z)RHYl&#|Sb62Lg&Z5>V8MfTGR>6m=n>s4D?Q z-3TapfqP_c;2`D;3K+#bGioPPC=okS- z#|bFv0Rct76HxS!fTBML zDEgCtqQ3|zdPG3c-vku>LqO4E0*b;MJ#0r&fPkWK0*V|0iXsRoatR?tm&2X&21u}i z`3{HsqZGYwN2KFfUsh4H<327YMKK&NMX_utiepPrJX?wq*iw{%EkzmGQWRuMQ6{z& zWoDx&3jsx02`I`&Kv8xAigFN8l#_s>Tm%&5CZOmE0*dkwQ1m1LMTrCys3IRo_1QewaP}G2c zqJ{(%Jxf4QBSJ_~amVRpfCMwxPd_E3sJLTBW5=_;tfJPA4(3j`E( zC!nYY0YyCtDC$K(QEvi@UL>HX4*^Ae2`K7EKv91JiUtr+G?0LzK?D>HCWI6EOs%a)>XY$+PgmZAx4 zDVoTZqDgENO(vk|B?5}35KuIgfTC#x6ip|fXa)gAFB4ESlYpXE2q>CGK+&rN6wM}} zXbu5Ia|tM#M?leh0*V$8P_&SMqD2H0EheC72_d9tnBzP!K!UmK9qQpyWdFedcd6r9 zUslm;j+?ET6ur*zQnZpSMQ^aBXcb$ERT{}fTH&ZDB46o(PjdQwh&OXm4Kr62`Ku2fT9lxDB4Cq(RKogJ|duK z2LVMp2`Jh{K+(qp6zwL26fJk0Dh5b!hy8Bs3MndKz6t_Y3`4XXMI^k*Bp0sEh)Or@lteyEk!@GrRXMGihf~B z(Ji(V{mPc2+iWTNjV(oY*eJS7K+!z{itZCo^nie(-w7ysNI=ma1Qh*AK+#_W6g?uK z=x+jw{vn{~F#$zk5qj8;q5uI!;RF;p1QbOOP~;L&6iGmlM?jHJ2r0VaIEM_7;7I%Y zqN`H$uK8ZR8x`SMUsh3EgnPY?6vcDA6eX~wC<9xHGP0#8$d;l^Y$?jjmZB_dDay*0 zqHJswWhbC02LVMn2`I`%Kv8Z2ik={#C=UTePZCg+NI+3u0*dkxP?SVKQGNo73J_3K zkbt5>1QZn}pr{A|MMViHdWwLeVgwWwCxjHmL^$zvjiTA+PbRyu5ur!=)9jy1EfL{a zUsh3R^I*Te6qVt4DJsjBqH=60D$kap3T!E=$d;l?Y$>YDmZGQGQdEVFqGt#ws!Bjn zH3EvN6HruxfTEfN6xAZ2s5SvbbqFY`OF&UQ0*dMrP?SPIQ7QpNX#^BCAfTur0Y%Re zP}GQkqQ(RiH6fs=DIugNIl^gffCM+%=UtbQqHsH!MR?YiRrFkhJ0w+#T5-G-wPs6E z8@3d+WlK>zwiG?jmZJ7-DeAzMqK<4S>cmD-X99}45Kz>WfTC^$6um$|QFj80dJs_5 zlYpXL1Qhiqpy)*ciuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gPgpi^Z z5zbNrBv{ejp>8Qf1FfRr5uWvB6^)K?cQ%lsF&r;NW7$$Pjx9yw*-|utEkzUAQZ$Jz zMU&Z5^b%W&rm#^om4KpY1QbmtplAjGMK2RjG?Rd$R|qJYML^N31Qg9CplA*OMRN%# znnys z5#d>1R?!;~ZlIAAt>SnoTFsWCH`!9OhAl;F*;4ctTZ-OhOVK*E6s>1V(FQh(-XWmq zT>^?W5>WIW0Y#e#DB4Uw(G~)Vwh~bEJ^@7^5K#0X0Y%#gDB4ay(MJRn?I56NCjmvf z2q^lPfTG<56n#QK(H;Vd_7XyhUXO4J8X&>@_UVl)r6}5dJ7iykXMI^kpGLU#nn=-S z94|$O*i!U4TZ+D5OVO8XDLTxSq9bf6I?9%!uh>#_jE$n>1QdNuK+y>TicS(xbc%qY zZwM$lO+e8Z0*byRpy)dSip~;H^gRJZ=Lje|Pe9QH0*WpYQ1k-hY$>|WM$rQTihd`c=pg|`e-KdgCjmu&5m5AqfTF(%DEfzh zqQ?XjnLn1j%-p~c0TcxYC<-T_$RVI8f`B5IfTBnOiaY{}d;*H12q=mspeTkAQgl7S z*sen`Q3lsN(L#zca=a7;*;15=Ek&8xQj~=)MOoQWl#MM# z+1XN*gDpil*(l0IKv8Z2ik={#C=UTePZCg+NI+3u0*dkxP?SVKQGNo73J_3Kkbt5> z1QZn}pr{A|MMViHdWwLeVgwWwC!nYV0YxPVC`u-T6veyFLjxpO#Xd1D!3{mq|H*zK zyOir$Ush2$*UiyNipq1m6jfkLQAM^CRbop~WwsPO&6c7nY$yeKv5k6is}+jRF8n7`UDiE5Kxp#Kv5b2MGXijYDhrQvjh}1BA}=- z0Yyy+C~8VTQ8NOHniEjef)G+v#&xP1Ai+=V^RCNEQ8)X=qn55`eOX0qT(?6TDQe5{ zQq+zuMbERPs6AVXI(TfBW^&z0BF9AjU2q@}LK+ymKiUtx;G>Cwr!2}cyA)sg|0Y$?IC>l;c(Fg*H zMiN4bTDi_-10?Fy z`2-X#AfRX=0Y!@lC|XQF(GmiRmJ(33jDVu$1Qe|xpy)LMie4v#6peA6FAR`i2J<)K zxnrfs&uGR<*R#H?qBmXl=k`*xhU2AZEnAA-VoTB6Y$;mDmZJ4+DcZo6qIcL*^e$V9 zHnLIl9sxz02q@Z2K+zTginbC^^gaPa9}rOVApu3(2q@Z4K+#786zw3OXeR+hy9g-y zn1G_)1QdNjK+zroiuMvvw2y$I{R9*pAcPdHa-9qvjH15w)6Z%t%5T2|a?tgxFRSQt z*DcjaioW1@Df*HvMTgl^bc8KMN7+*J6^a@}EFr07?Um!jKjDf*2q zMR(XzbeAnf_t;W&pDjfX*i!U6TZ$gCQS=7^MSl`d^cMj|j|eFGn}DK!2q=0?Kv7tv z9=4+>KtNGA0Ywf0MG*uPxdaqN5>Vt3P~;O(6h%N$Gyz311Qf**P!vZ%Q9L1}=%(u| zH$Z~ERrHG#?X>r<6Cyq9%PPtg>3-ZziZXM&6lGycQC7ATWn)WGcD5AdU`tU>wiM-J zOHppN6g|O4Q62({o+O|sk$|GS1Qg{XpeTueqWlCD6(FFfAOS^%2q-E{Kv59_ii#3Y z^b`R_#Rw=WPC!u!0*Xo!P?StSQ7Hn7N)u32h7eMeG19qYfCLi~4V++P=#hR8`#W0M zNYDDRiYi9BP7f)n#PL#8nJq<6v!$pCTZ*1xOHoy}6jftOQFXQy)nH3eO*V>Z5l~c{ zfTB7C6xAi5s2%}D^$93SA)qLgfTA=4iW(45)R2IpX9*~3L_kqv0*aatP}G!wqGkjX zH7B5`1p!4Z2`GAwfTC7}kfQRDPGJKic+~zTRzZqx*e^l0j`XZAtLXViH>H;pwdZ&# z>cEzwj%+FF#FnDYY$@u(mZGj~DeA_Sq8Hdw)SZo@9t0HiB%r7l0Y$wDD0-2AqCNx^ z^(COF9|1-E2`CysK+!+~iUtu-G?;**Ap{f+C7@^+0Y$?JC>lXP(MSS{MiEdnnt-A) zgpi`PkxpL&B)B)hz-cE%1?*GS#zuP9msK<|(tY(sDVoIbQZ$(@MK7_XXbM}3rn04I z8e58{v!!STTZ&$0OVLa=ie4e0XchrQuM$u+n}DJ@1Qg9BplBWeMe_+LT0lV2LIR2w z5m2<4fTAS?6fGs7Xc+-T%Lyo2K|s-K1QfkaK+#G9iryfgXcZx(Xndsez5x>SlMI{* zQe^*`Zg+L0XMI^kZ$-MN`byE;94|%d*iy8fEkzsHQuGd6ir!^Q(MGluy~mcKO>8OJ z%tp}`0*ba0Q1m_lMIR7Q^dSL7+XyJyPC(H|1QhKcplBxnMY{+n`j~*C-2@bULO{_T z0*dw$P_&PLqWuIE9U!3SAOS_65>WIRA*5(cr1Pf%5}fWDIBTWojQv*?4n=y_msNB) z(#wfw<7_GVnk_{q*iv+oEk&o;QuGZQMW+cUIzvFww*(Y@ zM?le80*byTpy(U{Mdt}9x`~(HD_Ubps?g(S9H8ODUS{nDI-bXMI^kzeT#821(H!j+dglY$>|O zmZJM?DSE(`qTkt4^pGt@f3T(KPqq~O#YWL10*d}7py(e0iXIbC6z1t+JBk7X6onH| zR_3p^c5h43So=pDgPv!7Sw&er_pKpPl#S!1C_7tWfTC0aiqZ%uYCu3yLjsDPC7`Gg0Y!}oC~87LQBwknnh{XcoPeSh z1QfL-py)XQidqp+)S7^zHUt#4C4>}J@|@ssqbSCHE~+d=BkYr~+j*Y#WfgVw+%hAj zs1wIaQD?Rkbzw_USGE*&V@uHsY$@u_mZBbPDeB3VqF!ti^(LU`MFNWY5Kz>YfTDf` z6!j;dXaE640|_V^L_pDC0*ZzZP&AZ)qG1FS4JV*z1OY`O2`CyxK+$LdipCI7G?sv( zaRd~NCxjHW_ncM+Nbp1ZeY6fzG%3-H37%(tSw$~-?ugM+G=<}(XewKZrm>}HI$Mfn zu%+l_wiL}|OVKNADVoKWqF31{noU5_90H2w5>PacfTH;X6fGd2XdwYbiwG!MOhC~R z0*aOrP_&GIqU8h>tstQ2H3EuWC!lC00Yz^RP_&AGqSXWxy-7gP8bV0XB+q%x00{=| zmxv}yQ3?CC>$RR|eOX28J@=EbQnZ2NrRW{D6urxqqK#}RdXFtdo7hscnJqF5m0o9fTGU{DEfjBQuMax{Ahp#55^lf>!j$s{d&=to@aeo zMPGTYJ3)$$al8~AXG_u7Y$-aymZFnvDLTcLqHowzbeb(iXV_BoEgMDO5m0oNfTHgS zC^|<#(Rl)jE)Y<3k$|Ef2q?NlK+$Caihd-Z=qCb-t`Jakm4Kpa1QcB-py&nxML!cz zbd!LhUkE6=ML^N7gpi^mo>SBS3AV{(;2f2rO7_pA-S#}|%PP9(xoMN6=sw3w(F3*= z{mz!6hiobOgDpjWvZd%RwiG>LOVQtKDf)+vqQ?Xjh535ej-mhoMd1V#IRq3%5K!b2 zP!vf(kw-w0Pe4%=0Y%XS6vYrw6iYx+905h~1QaC@P?UjyqKpI-1qmq1L_kqyLP*ga z&*^V~1aoCKaPCUchgMM*-?P4~q8z?E=Oro1$?;N@i!DXD*;4cbTZ;0qrRYhv6eY5y zC@))z^0B2TiH)NC1QZn@pr{}LMTH0`Doj985dw;e5>WIM0Y$|KC@M}sQ3(QyN)k|% zOh8d70*Xo#P*jG1qOt@Ol_Q|2JOM=&2q>yZKv5+^NKrQ5`Op9frsg+rviqS&`kC#Y zB&zIt)|XXO)pt)%m7;1KFGbbaQdEO2MK#${REsS|wb@cshb={Q*-})GEk*U&C`uuq zD3ySsGy;km5Kz>RfTCv!C~8DNQDXv%nh;Rblz^gU1QazVpr{1_MJ)*^dX9jiRsri21xLOEC$XqQdHcI4!&o7Sw&rZ_lX%&)Rp6< zs2f{~USLa6ceWJuU`tU?wiNYZOHpsO6uronqCRXC^(COF9|1-E2`CysK+!+~iUtu- zG?;**Ap{f+C7@^+0Y$?JC>lXP(MSS{MiEdnnt-A)1Qd-WplBQcMdJx5nm|C&L;{K? z5kiVO`A$s(B-lEqfzw%vj#@>Neb4%`il+H)mzh#Do#Ulw23v|=W=qjbwiLa>mZDi~ zDSDMHMYGvbG>0ukbJ-}GM?leh0*V$8P_&SMqD2H0EheC72?0e*2`E}dK+$pnidGO% z^cn$0uM<$Tl7ON&2q;=bK+$RfiryrkXbk~HYY8ZNi-4lH2_Z#Od}o>g5-e=LTs>8a zPS`t1>wM4pvWnjI-F361Xd}l<(R*wu+QgQk&1@;!!j__~Y$+0*dw%P;`KRqJsn!eM&&l zX9N@-BB1DV0*byMpy*2iiVhP{bc7I6w83|d8X&>8zJc?O6rHqxtmvrkSzlJs*S`Df zY$-ay@lte>Ek&o;QuGa5icYho=nPwmzGX|%cWfy-%a)?=*(f?kK+$;uiY^dPbdi9f z9|$PAL_pDH0*Zblpy($8imnh)bd`XjYXlTsC!pvC0YyI(P;`@kqF)Fox*G>%&pu`CuJ2i2R?+XiTW+2dJ>+;P`hzV+f3l_M zFSZmtVoTBAY$^JOEk%#nQWO@Y$L&%SV52CUfFg&0q6h+tTmp(B2`KUiDDnv?iXxyW znt-Ah0*Yb@D2gMXD4u|#1OkdO5KxqnfTAD)MVSaF%1l5}76OX05>S+l5K?sCciI>r z!4`=I&I2hLXTKeiJ<7AbtfJge?x+P)^aRICQ69DwJ;|1$M79*=WlK>$wiG3?r6@mJ ziVCo$s303fg$O7rOh8c)0*ZS*(Kv5|Iib@kuREB_} zvIG>BBcP}}0Yw!ED5^+6Q6&P3DicujGyz3b2q8r|qnwonNHDAY>-KX+g&yhm%V@?k zQJ(c>71fAx_b!s6nj9}hwb)Wrn=M6k*iuxNEk*U%QdFNUMJa44N@Yt?8XH9o2qcN(xo@^=V#g?MpY$laQ(NF@4 zh7nLSoPeSc1Qd-VplB2UMWYEQ8bd(QSOSX15l}RqfT9Tm6ipN4X7`OVLb@m!enLQZ$P#MX$1@Xf|7l z=CGw`E?bJ`v88A}TZ$I2QM8bNqD2H0EheC72?0e*2`E}dK+$pnidGO%^cn$0uM<$T zl7ON&2q;=bK+$RfiryrkXbk~HYY8ZNi-4lH2`E}eK+$>viZ&2Jil#?70}YU19s7re zW=K&E`#t@4qCD%%D%up~&U;OYHgmibZDC8%R<;zq&z7PO*i!T%TZ*=^rD!`_iaugX z(GE6>b`nsui-4k!2`Ji4K+z`z6zw6PXfFXp`v@r7Pe9QD0*Ve2Q1mGQMV}E+bcleW z&j~2{f`Fng2`D;DK+zEbijERc^c4X`#|R-s8>5`<21wAe&%1t4iUwLm$D=&!%PKk* z<$k+TioW4^DLT!TqBCqM`j#z4-?63WEL)1cXG_sJwiKObOVI^3iY^jR^aBA!mk21j zOhD0(1Qh*5K+zQfimnn+bd7+b>jV_tAfV`H0*Y=DQ1lA{MYjkj`jvp9+XNK-MnKUW z0*dYuP;`%gqWgr9q7zZhKL$u}mHl${Nh$ir-bs28^~ha{0&FP?XG@X8mZAtYid+JUA_*w+2q^LiD2gJWD4Kwx7y^o7 z2`GvqpeUYzq67kpG7wOdk$|Eg0Y#YzD9TJgQ5FJ!>Zfm3{k>jN(FI$T8v85=9Ek*g+QdEE~MFrVX zRERA_h1pV6gpH!21Qb0*Kv6LQii#6ZRDyt_k^~eb6Hru&fTGd_6qO;Ms4M|R0Yz;HC~8YUQ9A;Po+qHFJpn}> z2q@}EKv5?GiaHZe)P;beu7r@Hn$gZN10E=q>&q(Y8SVbIPKtVQ zycG3jOVNvLDeA+PqP}b?>c^I%{%k24z?PzcY$+PVM$upbiiQwSG?aj%VFVNnC!lBq z0YxJTC>ljT(P#pS#t=|6mVlyh1Qd-YplAXCMH2}qnnXa+WCDs_BA{pr0Yy^@D4Iq< z(R4ycQTJ#k>w2T8Lv917hZH5*KLau&+Oxi_qFK>yg?FUrRgRaU*=#AA!WI80Y$3_ zC|XTG(VGMmts$UjEdfPu5m59t0Y&QwC|XZI(FOvF-XWmqT>^?W5<-e*Mmy~ckl&q(I8tsnRC`IpcycB)FmZA^YQnZaNMcdg@^buQ%cCe*rCtHek zv8Cu^Hi~u=Q1l4_MSBP++DkyuJ_3sN6Hs)3fTDv06n#oS(Psn{9U`FUa{`LKAfV_= z0*Ve3P;`WVqN4;9eMLagF#?K?6HxRu0YxVWAw`>`omB=%aISrDzeS2hSw$zKJ?qOV zIuq^g-y}ufa=a9M$CjeAY$^JlEk)OvWotWcB8gR(LWq7MUUB1 z6c(dL?ot$BOHnvmiX65SMX;sFWlK>cTZ%k3ihKf!q6jF8CZH&WfTCCeisA?;iYK5b zfqrdpNW8?%mfr=A)qKL0Y%veD9TPiQ4Ru%auQIKi-4ls z1Qb0%2r2q2+9_dx1S=*PIFF=gk^SOPo*2*ivWoJ>xQ#xLq9l%&qWo+rD!`Vaf@~=& z#FnDMY$+S*(Kv5|Iib@kuREB_}vIG>BBcP}} z0Yw!Ed@ia;Kv5+EiYgOO^fUoQRR}10hJd1~1Qb;xpr|?lMKuU0s!0ebN{n#^8z8~w z6AhfaF`-BL87!$STZ$U6rKllWik@XlQ6sh# zHD*gu6E=#P5>V8PfTHFE6ty6rs3ieK&k<16ih!cl1QfL)pr|bYMePVEdY*uy_5>7l zAfTut0Y#k%DC$f=Q5OP=x)M;-jew#T2q@}K2q~%)m|v;RFl*b(HH`X#u898j)0=^1QbmmplBiiMUx09noK~^O9T{6A)sg~0Y%dY zD4I?{(F_8LUM8SuCLyG#SBw+3!zfx{|AcjKDf-&{ocl_QXMI^kb7I`QyQF9?$4k*X zwiL~0OVI+h6fI;+(IU1KEoMv661EgAWlPaAHj0)LP_%-8qSpv0dYyoxl>`*MK|s+e z0*Y1>Q1m7NMQaEsT1!CDTLcunO+e8)0*clXP_%)7qIU==dY6ErjRX|EM?ldg0*W>h zLW*9Eaq1c%!7cU<^=v8XX73kmiSev2tLVcRxBG4>+Q#uxw4E(QAF-uq2V07EvZZJj zTZ%qrOVMt&6n(;$qCIRB?IoaS9|1-C2`D;1K+!=0iasTv=raO}4iQlFIRQmq5K#0b z0Y!%iC^|ww(NO}5z9OLL7y(7c2`KuSfT9xw6rCiX=oA4(-w;BI-j8u+8X&* z0*dYvQ1pO+qTdN9dPqRg9|RQrNkGwGgpi_dW1O!IkYIoNik!&gQ*iz)Pr6`ImMbT^&#Sl;wOF&T^0Y&iy z6eSQ)l!1Vvj06+~2`I`$Kv8A_in0(;l$C&@Yy=c#C!iS*#2r2p}#>u|lD9UZWUi4Usj#x!`V?FE3Dk>1`Ryrs}1vy@d3bCcAFk6a> zu%)OdTZ*1yOHnbl6cuMnQ3;qSRP-+-Fjh#_>|rfGtH0*;4c@TZ$U7rKmAmikh&c zs3}{Dnz5y*IU7YS2qPSFQ zCjyE(6HwHJfTFGh6m=t@=mi3bx)V^;gMgx*1QhimgcQ|}b>1{Ug7fnkI4M%J#{SvZ z-m#wbWfk>{bq{_nMg2KmiUzQyXdqjP2C=1RFk6a-u%&1yTZ)FUrD!-?ibk+eG?IX# zQ3Mo?CZK2x0Yzg8C>lpV(Rc!iCJ<0Gk$|E}1Qbmspy(w6ilz`yG?jp&X#^BaC!lBs z0YxtpP&AW(qE`qgnngg-tAvoEKC#XX10>knKJU7(6qT@FJenQrSzlJs{8%^UuoNxe zcqv-QmZC*$DO${yq9tr8TFRE9Wo#*0&X%GTY$T{;fTFbo6um`2(c1(Rts|glJpn}<2q=1ofTDK^DB4Is(R&0GZ6cs(GXX_g2q@Z0 zK+*ezkfOP}a2NJx_|p*l*2#5bIfAR?$bXZj+-@w1eZNXeV2WcCn@CW409S zW=qj0Y$@8qmZH6EDcZ-DqWx?X9U!3SAOS_65>WIR0Y!%hDEgd$qAv(2`jUX6!vqu^ zA)x3e0YzUCP;`udqT>VRxCfTC{*C^}6*(HR1Yz9obdZHsk=8X&>T z_De+DrD(c+#_V^op7muFosV@F9h0I994|!|*;4caTZ%5RrRXwSihg8E(NAnCy26&C zt86K{#zxU~0*Y=BQ1mkaMK=j3`h|d^TLcvSN~M+6l8O+e8+;isZ*_mr5hq)1P|NkR>mn}t+Y$@{CQslFxD2gpb(QGM-VM|dgTZ-b?D2gYb zD1m^Y39_k}XBaY$+O%-AN{e%586d%# zxec5KQgp`NN$MNtSzlJsz&Q84Z>4Au$4k**wiFFvOVLoa6b)lb(QvjDjbKaBNVXJ> zVoT9zHj2g&P&Af+qHzQijVGXJ0s%!62`HLGK+$9Zie4h1XbJ&EQwb=VMnKVY0*Yo3 zQ1mhZMKcK~dWC?ZSp*clNM(IM4dB ziWbGW_s>evVvd)hC2T2L%9f&KY$;mKmZBAGDSC}9MX$4^XeC>U-e99>6#+%72`GA# zfTA@76s;wo=q&<@-X@@E9RWq_2`Jh?K+!t{6unD8(MAG_-XoxB69Gk=2`Jh^K+#qL ziry!n=mP?ZJ|v)M8zH1)83KyFC7|d#0*cNOQ1m?^ zq-aN+)6oD4uFhuQ?3AJp?YBeD#d+43RrEugJK>@fUE+8ty3CfMAK6m$6I+U|u%+lK zTZ*o+rRX|aif*u_=w~*HZW2)R3jsy92q^lMfTG(36#Yg((H#Pc?h;URkAR~41Qb0W zpy+o3iXIYB^alY&e-cpi7Xd|&2q^lSfTDj0D0)mlQCPeln4>5_2r0S{=d3kAf{X2w zWG_lllKpl_c)VwQSw)fY?q`>z$m4h^^4U@p#g?LIwiLy%r6`syMR9B?if2nv0$YkQ zuu+tefTAD)MVSaF%1l5}76OX05>S+lfTHXK6y+eGC?^3$xdZ9FGa=KQdEL1MJ3r%l+2c*Qfw(I&6c7vY$+>JU&=mw=*r1QgXL zpeTiaqErHk(g-0%MdF>(21szD{nlAgDJo^Z9nv7)v%ajN#_?{mt5Vd2o zrKmYuidwLxs3lv9o?}Z2Lg&Z5>V8MfTGR> z6m=n>s4D?Q-3TapfqP|Xe?Wb#<5W}o`9kW1QbmqplA{SMUx3AdWnFdDFhTvC7@^;0Y%dZD4Ib)(aQuB z%_N}c6#|N85m59h0Y$S3D4Ih+(Od$G<`GadpMatTgpi^^@y>1oBp73V6B{f=o+Y&~ z-m|`}qNVZfg`cHp8OKY}a<&w$U`x?!Y$T{}fTH&ZDB46o(PjdQwh&OXm4Kr62`Ku2 zfT9lxDB4Cq(RKogJ|duK2O*?ral8|8(45qgKR1Klr2S{v8Ct`TZ%qsqv#6)ioPVE=r93AM+hi7N^#!j__|Y$>|NmZIxy zDZ0UyqMzAPbdxPbzp$m~78^ys5>RxTfTG_BD7r&H(Om+H?h#OQpMatV1Qh*FK+!`2 zivA#==uZNQ{vx305dlSi6HxRI0Y#4qC<;r^!*&z}2q+3CpvWPhD1s1DbSd7MZGZ$9 z*ymkemZDbnDQj+mXMI^kQ3>wmJ5m(Q@lq7SmZDg;6veTnD4s1v32Z6Kz?PznY$*z| zr6>~{MVSdG%0fUH@mxd|wGf`Fnt1Qb0RG5IGB7~44FTwf7013{tUug6bLXY&D+GorbP4KKQ ztEfbR`};j9D#`Iul+2c*Qfw(I&6c7vY$+nuBB?5{n6HxRt z0Yy~^D0+r~qN)TGRU@FNIsrvB2q>yaKv69MifR*3REL0~x&#!}BcP~00YxbU6r~bS zltw^N0|JT~5>WIkA*85Sf|L8cQFPOO)1$Z)2Lg&Z5>V8MfTGR>6m=n>s4D?Q z-3TapfqPL$s$pjR=L_pCL0*a;*P&AEzqUi(_%^;xYWde$35>WIC0Y$S2 zD0-EEqS*u#%^{#@E&)aJ2q>CQK+ysMiWU-3w1|MB#e|Tep$X3021qc){w6j|iYnPZ zkG3Siv%ajN6$$R=e@W4694|$$v!!SyTZ-ObOVKK}6s=}U(VJ{3TEmv2wQMPRi;beU z2`E}eK+$>viZ&2X^bP?%Z5m0oDfTH6B z6n#xV(Fp>IP7+Xbih!bT2q-#DK+zcjioPYF=sN<6&Js}cJpo1M2q-#FK+y#PiY^jR z^aBA!mk1$6dlH&q&-n&7qwvsYlAcYTfHrRX|aif*u_ z=x4SR-DFGAFKj8g#g?L9*-~_yEk(bvQFMoZqPqkX-6NprJ^@7!2q^lUfTD*46#YR! z(Vqkq{Y600BLa&4CZOma0*W3JP!yIy58F``AfPCmfFg&0q6h+tTmp(B2`KUiAw@qW zI3o>^;P{*d&J`)zWPf|}GkDgQRTP`ST^24yaU3s2@oXtdU`tU3wiIP#OHq(5MVZ)A zl$k9>S=dsPm5rio1QcZ_peP3cML7v5%0)m?ZUTy)AfPA@0Yy&|P?ShOQCqh2N^B{r%$B03*(j<) zK+!V<6jddls2Tx9)d?u7K|oPW0*Y!8P*j_MqB;Z=)g_>)9sx!52`EY-peU7qqBH`E z8W2#_kbt6R2`FkrKv81?ikc8Yib`g1B3+}Xi~T-YvJ_Rf-;HgW!Lz=sqLvxlLY@>o z$MI6siY-O0*;3SoEk$kFQq+zuMbERPs6AVXIV8SfTI2c6b&GtXdnSag9s=ZOhC~P z0*ZzbLW-Jaa2gmO!T$Ccvn{0PTF{JP89eLDDjJo+?Gq(Mqd8uR#;~PmEL)1kv88A{ zTZ$&IrD!5siYEO(>fQuCiei2D@199#2EvjBn6QO}fU<>b?6PDsNyuc9Ovof`E|Y~o z*fAlZ)&5S9Q+}&_dBlXrbsLXi#)93{bQR1}It$0~B2X0~D=+0g5h#0g5hz z0g5h%0gA4G0gBeb07X~A07dIyfTF8lfTHywzet=tk@>6x{?Z6m5qV zif)D$if(}xif)A#if)4zif)G%itd0GitdC4MR&mfMR&shMfbn}Mfbu0Mfbq~MLS@C zqWfWhqQAiaMGwFLMGwLNMGwIMMSq6@iXMgmigv;PMUTJ$MgM>SiXMdligv*OMUTM% zMUTS(MNhy0MY~~Wind1E-y%R_{rnjJ2BD~&zYww~+QED=MNdatKeZK#p27Y?(X-G( z(R0v3(euzk(LQLQ=mlt@=tXFu=p|^O=w)c3=oM&Cv>yg2dKCsJdJP6BdL0HRIsgL{ zy#WIh{SyW#dJ_gHdJ6_9dK(5PdItt5dKU&LdJhIDdLITT`Tzzf`Va;vItT+4eFOs( zeGCH>9fARhK7j#>K82wvdMetU(2giN!ncU_3PqRl)7a0V9n2R~^kuX)CR!*ug8hY} zub_pZuc3vaZ=i*uZ=r>vqtHUpchEx7F=(OaduXBPI5a5w0R|{K0Rt5M2m=%~!2m@+ z!2m@+!vICUzyL)jVSu84!2m_S!T?3T!2m@@j7-}>kqHA7*!MhpC>r|< zMKRDqQ7p7j6bCI7b$}L%IzkIYouGvx7qn0m4=ogRh6Y7lV1S~oFhEf^7@(*-3{aE+ z0~Gau0g4h~fTAQApr|JdP?QV<6!n4uih9EUMW?|4MW@36MSWm^qP{RdQ9l@i(NJiiXc)9mG#pwe8UZa7odGQrjf578MnMZjqoG037#N@^3kE21!vICuFhG$9 z1}Msb0g7^AfTBDYplB=%P?Qe?6nSBQq5>G8$Oi)y6~X{TMKC~7F$_@ThXIO8V1S}= zFhEf$3{Vt+0gB3CXo@mo>_-WZ*r7bR&lHOO#T1ptIG8V{Xi|(7;}VJ{V}GIOOlYC# zENG$VY-pkA9B82^2rU#Ejp0R|{q00R`A z2Llu>gaL{c!O#>tTSRtuQo2OJnRy36R(?9R$uYq3A;vH^exYFQ#aFjCFliq3CApFBIJZEfn1f zEfn1bEfn1jEfn1WEfn1eEfn1aEfn1iEfn1Y4T|oC0gCQ}0g86O07du107ZX;0g4`g z0g4`k0g4`i0gC<(0~9?B0~GCq0g4`h0gCey)h2viz#|8#yZqpD0&|I3q|{& zg`yXrg`yXsg`$_Bg`$_Cg`!uWg`)k?LeZ|eDEb5j zDEbrzDEbTrC^`%S6nzduQ}j%X-I+iXwc+o8JS!AU=WjKB5#wOKn4+&^tiFjt(Kpy% zDEby!C^`x)6nzIR6di*WioS;yijG4IML$3bMJJ$zq936_Q4s}9Tb@`K#>gwD6+!Va zP&6D`C>jAR6rBMr6pe%yibg>TMWdmGqA}1yQ5LjNq0fdPtgVSu7M z7@%k@3{aF00~C2-fT98zpvVUU6cxe%MMW?`Q85fq7@%l83{W%yhNft6to6W^~-5O(b?EvC^`pP zC<;OgMHSFOQ6;ocR0S;*RYMC!Q=o;S8fc+tDl{mX1_Kn;!T?3nVSu6;FhJ2v7@%kt z3{W&11}K^X0~F1L0gC3q07d7*07Z2$Kv6vmP&6L~C~ANKiWa~CMd!f)MGIkoqD3%3 z(P9{&XbB8Zv=oM>XmYGQ@pPhSDt|ETOrhvG{#N6%SO@dP6fKXn+nJe zt|0v!ZG>w%Jtc9vw$p{Mjq7O|R7JZEQ+L+E)xVQr#JkQVD7(2HrVmgiy8cC@tX?h; zefhSJ>yjkH7~pz^9=D{qI-X`2gIs6!F^plZ8~Yi?NY~*3hLPn;Ni~cdSADu+k&mZ-Wh^#FabDFv?t)jxdagu2)AI##t`c7{jP=o$WS^DX#4v!>DzAk!u*UT&ekn zG0)XdU>NgVj}{unLYL_`jHRxz;|!zGb$P%rR=Qp8h+Zj9sqV8VqB%>+ACjW3MZ7v0*&tTC~(KUUWTizG3WlS<4OMfXlbSFy3;lyT~x! zbG^CBFb=x9uQ7~IT-BEu#^I%;8&!cB-(x$~ff-+O3sr&{f7fkP3ugRxcThE$@k8&XdNAYp zf3xpp#`Awi-p7pR|4({=8PESAaGDv<|D)?5GoJrT&S7Re|DTE@&3OJ#@v_W#{$I^< z%y|B9sq)Qu{(prE&3OKgVM@$+{+~U{%y|B<877+X{M-6xneqJN=oMx>|GM=QGoF8* zxYms4-cuqgJwK`WOt_-&!4&6WybS|=60L${HdqCW;}mvq=8P5-n_nYzj zK+V$}){Y>g%@$F1 z%;B=;Bl_Z(IYLBy7ZPWP=)q#7h%EX^b90mkBbmf#ExJe02*wIcj$ zy+J}1IebnZr>52_}-EpW~tTYq37;Q?O_J2HtAm!Eie+O z(HW5$rg1{=Vskbc34fPl`VN$2<{jFZP03hoX7zv4tx_2fc$SV3h>ZF0m+PKgY9#)H zc8Q~865gVPL|Vwz`bo#ahVY`lN5O7H%A{&km5FXr{W9gM^>q*o{D zebSuXcq&ycwD?px+iPFR;zG09-2cSF7?s?;@89s{B6YgA@4D{t#YVzev`-3UYk=NI zm0GQ&Q=z@cnEMYrx^tmQDDKr>v^y34+wD%wRO!6&=&=n;jD*YV`q=An>_-+3>!Z$P z{Y#&Jc)r?az`Vn~RM8B~nK{l#xKnm{4u{!s-7lM{YAL@Tzqqu$%J1>j_wS>Epz3*Y z^GCN)eh<>;Hn)Vrpc*~eBi=mDyj19Nu1-zm<^vE_?GfPysTgP z&NL(O1nr_~Cf3qP4%GW{MSm<-wzh1}FN}oaWnm-TWP&VPwqh zpS=776%-xgg%wtmk=R80jHP`NBB&{F{vME>V^;jOrcCYp^E+>@(mcO-$4aUsI@QK! z_I|$9NH|~i`3(E~a_pG~bxz&)FBqVXch{chHqg#=yxBKdwMN2b+J#H!C%p@w$_Ytj zARV1rQe@2IjoMl6DReC3@O6Luw$e24{+q;$s*ed&Mz&>x*oY2|rvG&~@wa=ZqFMdQ7}ieI9wccJ0eA(*~5ck~90wqkXJ4pN-!zQXS_0?@vCw#7OEu{T=V4dWBEi`5kEU z$e4>iT7N>9;!7{@Z=*`Ym{d;J{GK1tV1oZ5ZT85X(Y@%(M}LuT*&=)1O`RS8MOw6G zFO66DFS572bQNyFWadb(RHFPf4V1u2=2-DtfbW{|r z)|;7RI{MIF-DnKuR0{-CE44sX+FBB{bb?W)>5b!E+9XkOskBSm_H=Mgxm}zY71f+( z`?iMNiJU}5wT)^MHH&f;TAUK61QTpmXayDD0SHI*+6Z=rYh8(-|2#y|Xti#*B^3ir<*snUCAm3fsZvdN`ZP zyjyr8Ty)*T4cRE+k_%0$uXI&nJ=R=k8n*a#*>wF$q!k9QFpMN@LktZxI6HINshrU1 z(3Ro$uVG}FMhS=WiEGms&*4}4i!i=7OKwn0e6co4A}BcNPp{ymerm;d4tzn^D}H|r zc1F;jX^i8*Nt#AE2Tp|C=CsPg(;9aJ@5!$=CS5n=brwaNk#++|PQz|E8&x(r6<)!S zv!hmEuWo8DR@8yYi#G~?h3iFBn0Dhex~AC7U)r@bOnT9_^k)tnm|9nvI<iIQOQmgA0&6_`$jp~{y4Rtm3Ve5E%+Io2Eyt?VLr_Z0hpvFk8 zojbcGwQ^R?!qkDY=2lnEO0BQ0tgA__tC>?%Us<18lM$?+-!NtR+|>DV=gz9Gt(-om zK6P4kb+EE-c4~TBFf*8umXRJzPh&HM%#=BE=hURsR8~z-NlzP?nZm0F(&`qgQm4UiUy;a=w$y7rvCp0f(4cHYq&0`m;k+d_#SQXO@TZGw>Mh_I)TS*+qS8^b2mO-1jtS)^m>vXG&eNmznm#B8`LL2?@ zqSeca>lSu^)W{B2tU7Yss8Q;miD}yC+2YWN;fLmf@S#mBvFD%PI8|-ko%T(Vv->lL z_@C`%S#*pu_)w#Ck;W!jNj5onS2OPbb;3%q06Q6ZkhJWKmUm`KYO= zTV2eQo7e&5w@l;@YFOvOqH2lbvioB){x3W@l^c=tKdA2i!CvZ6O!1!~>Mw1a^w-Wp z)k9))1MNkq#Qn7-LQU&0wZp%(adOLg8U3eP`d>K$VQnQ+>#U7nn$?L^uQaPu0vXb5+jBLvw|XgROiM}LKI8w@jgzci zJ*`gN=@gRGDg2i+RVSXP&wC*4)Jt|!JO9PB{*Ra1|84pCOECREo%z3Xrhk587d6OE zNmlQkma9L(mn!hd07cqn@9?(CjAmG!X}?xJ%jM;rXq3b0w4&aC8#pDV8u*_|q|@jW zt5>q+>K1l%ZH<>i(y$lK-QP8NvTh zzq*a9`c1XED=;T<)21GjF5Z03IG6ug*gPU^HN@(wn-~vhNDn4W6IVt<=|Q9yH|t*Z zRs+d7ui5FUG3AZ_)1oTxB*yAbH>CfTza-A@Agdel$GV%&&0kp5%+t8Q#dZ203(Xv4 zMcWTA8EKjJO%VgR2<-cp4V7-6VX(ySEiTKIQ_hg>-4yBGRc1zTzB+@P z7Q1H`(v7RqJXH<3#cq;0hCeS5bm!<~2CJ<(XL(^Ko?DiW@(q^cPYP097f~&H++|*W zu`Z|Kp&ipbVS9Q@#|5*Au^ewe9}H!wljOuywFL{k#lBFfP4MP6p zDDv_Kae=AD96=&b?(q<%p}m3Zxbocc++ZG+RA^O+yVP4YDI^){B6sm5sk-JQRJ8^C z0hNOsqB@j;!Rq)p3)wC&o!Un*;Lpnow%9m*c#Ew)?&4rssk=B(2CaIIj zZUJm*z)cCMs-^-KuyIU(z!MCV`Ke5E2}h|zT{bNe32RTG6Bc^hh3d#be@Sj}XdO__ zF7=MhFDs@J4F+<{%D64#(0QIhpUQ6LAl-5Xt0Ss|r@>N2)KhjN!VWvXn#?9pswtMMBYSKaf_}tRGLjQzQ4_aD0Hq>nrSMH+F z2Hq0t%%qA-s5=SoPt_>}h=folnGq_m?6AV&3Ti&I<~?jRRRk4DFn6LSH#a9N%TgfJ z!c*A0-` z-;{>gvloTZR?Q*T?`_#^aAfL+i~OZr9o$dqBr;S3nKgILv_$H(ls5>;r_%!Vr7{fo zn=ez`?T6M$zgwDHn5+6`F09;^9O;_obEeAl=IKJwIT#Xl6xHu=kSake5t~TfGV_koyRoV zU7cc!PP;situEKWKt7F4^p@0}p<@d>WKk}4RWfM7kvP3{>LvAlxr(EPIpL?zTTt&G z%6Lvjj$9H;bBl9`*0BCJRKXrK_z`BP6z5E<3D(S+GQDz6klRuyF>hgE?pSxBG&#D; z=TMt(zRW4!Lsz7*T23F&c})Ayj$I zJp^Ypyu`u!DJ72D4;%azQd?-Qf8=7UyQs(=$_1AXjjd2D)M8apHMi>YbVbM5;_^h# z@ZpL4@Oxl-B0v648@2eQa`W% z)Om?1(-Kqs8Hp+Mly+1#Wgunh?3()e%4szzvufr{n_oLBjV#^9QkWD{Qyb<~&!0Yb zPD(vJ$EH|M-jvGul_9N8acB$vRNd=~3y;@TMdlX!%c%>ZDx+%&Cz>{RxCW`^I6HK` zqM@2Q+gs?J+&orJqfVI1II~4p+T8BB@q_?u=9sQE)FYJ9Fq5y@p$$-nYChClwba5q zGy=$W(3Yh&lPVkC!-k4EJuM@w(9_d0*4&O)~rq^K*#6ps!|;cg~cWg?d+-i>d`ZgALHfE1JiZd?{)kkkRZ_nkdi4ky=SZ z6(y+CB44)P*|VxW8egjgJ*iYyT4*c1gzh$Mps0qoGz*eJ8#RBO8l8Gr*@f-E<4)?- z6gX3&Wff+u9{tuJ2Ja3-A6PPtAi2>7UDiS^Kcrg^4BeWfl)nq=VAs1!oE#?Uz&dR6cqRaD3W=k1hB zyF0+Q&_Z`#s11b@4b9!$+3IFmXhm2-mgbiI;TT)>mzZR8PW1dt<%xzlbPmW9%`j;i z=k<8iC8@+sS0uF+U03u1wa*rt>-&qIe46>@7OG8X;u}gX)L!x?1k33L7Zs)?DCyDd zEtDX29J0uBH_2slN;I7ha5ve^C2#VF16ovWi(7Ur#@3;+I%cPOGKEr*B5m0+QCF%w zXw;<3gQjd@<-r$4p0@-86TD@#ChQ7}xm|kmje&IPnT`5d8b^g@$vl%&2cV0#THu)* z8+wAJR)sYv8d*1&5Z|y>cU5?lLU$5^W8GeT8;`gPZHB_38AEwt^MHhL$CxI3KpVQ5 zlYyH#Jm*6}Au%447&BDg$64el7d8o>AJ9!wuZQ{&>eI_qIfb?g(8QK*1ju9`ZW^n@q6crjcIi97ypkt=Y9qcKid?IU zE!917>!D`$`{xs(F>PAf;9y<4PC?)QZN4=9uHQ+=tRbE6rQ%@W=aAG7##wLnRp2lkvmw`fM`6xB>j8eiBMhXc~$5sMT>d9kn9KS7rirbc{^p3~J644hsz-I1o} zZR%NwTFvtwtPC4kw746ivX?GbCY}{3gYST<1$~#67cuQg55M^-sq&5XJZeYbH=kP0 zJTTHxiBjQ)@}(LhUBJrRr93pG_CdptKWdbeh4ipnw36d=eSejc)pIGFFWupnk&GH; z;3mI1eppW}FzcaD=r$#_WQ<>=zr?ea4ZsP243kKA%XF=N15m zWlxubZWuTp@Xc`2gWpr{P^vLfo;!R1f<3S)=Ok=CL03R2U45D0)q3EMLzd{#G~J&I zm5btp`izj_DavUvr6h(?XQA2)2d%lQ<=fQZPm7RUecGzns7O`$wH)O)CqWN1F(^Zx zG0zH=2k04<%yWNtqmu7Yp7Kzl`A!vGL0a5GX`TVn^Kf~@#o6NtN@(7M_yXe3*A}DtU5_>2#MXRH`Toeb+PW@xGocsKN;!f~r~F1bSr453T+36!w4TmxAz} zBK2huoU6W%&(8u+y{_=}lAoTVkHgbf?3rEYF7{E+kV`k+P8oP{8J)U$bB!1J>1iMJ zQ*?LMT^x3EkE^}q%@;lS(Q|8`s3oED7Lf$wTJylUl z=&ALc(O?ksX(Sxh@#mNNhyvZly+l;=O}+_knzEyhK4nk7Q^eO}T|WBeDrF&^Z&Zdh z4c*`7$>G>io{FDRye+1q4615iJZ(ZE$ePFPp_0xEs_}%uhsS3hFq2|rrLl)kn>2@E z!yBHU>3)!JK5}vCz6VECol4-}Jq?wTL$*RgFFoB+waND=k(j!86}y{1%D{DZY9W*a zL(d+$JaJiSPD9tu1b?Yd2D+hPMLLaP`J}@}r-OKOihZd|!vmC-6S6$ILy5Tze+y_8?86TS+;y`Pb7xo8OqoK@`pWR7I`zB&UzY3p@1GtRZRmSbztM}neYvz< zR`%A;*oY2hN7H4GH#?hM%&ulPGr`u=q%X<;?iFrD7~lOCzJZ;;Iu`b_^Vi10UUvTG zSlG)>-x{N@1&6&NjA&A;L%Zqq9YVY5^$Y2XW%{Mp9|+UD|A5dJE1SP;$=llv`VMf| zi@u>5rg%MlmpSZZH(Gva)qYBD?FRi$MA*x2(C-k)APtoH~(Nj**=bfTgpQ5igMQ=Gp-+7A0H~7@Wpx1n(*OWgu69_e# zmRH!cG}VBbTNFRF_=9J)%^S#sP~Y@#w$sySk{CLOdf*gN{9NQ5I*-=$)n+cA*7POi zzlr7_w`fgYl0LwZes_a@uS9Lfzf!?I|E?4Jh2ocpKS%shVw2OI$dP^$WQyo3Dca~; zzN?8C#Lqa=7w)5pBaXD0VWY;y{e_LNV=_5*lt@`HYy?;mM_SoOeC{83yCD)s zNz9g5BC%XzwM6>e9<|@O5-*UrQsR{oZ4KxmA(A<#@@gxwgT$^9drIspF-_u7iK8XvN-UHZkT_Xlr9}Q&6+Yfv zi3=nylekjir4p}_xJlwRiML6-SK>nwcS(Fo;y#J5N_C4@ zM@h_)=#y9~agxLeiPI#`k=P({sl*i$*GOC^@mh&DNW4|zJrW<3_^8AuB|a~4zr;5s zejxEviC;ScZt0urbrwjag4-#iQ^jL5Z~z&y~p6Q$EfLiI+*-AaSe2+a&Ig_=vfW-GDekSo-iA@qsx<2!9 zTTAR9F;n7L8hY~jfW+xE^km&2@lv{$v)(B29vXVGenjFcbPZ?yuEg(X=*jwD5{Gos z+9Po(jfr^uB@&;cu?6c_Bsys)#{}qk#x-pDXeFbgeIyxHnVlS0%Ql0Sj;MlE^zb>(j zU+c~iOUG#)lz44G>sus#Km#s5pCb}`P1HJF;*7~!pC@t0Sz13P@dOQsd4GFQ$B~sf zdL>?1t@T=o&(&!ChQxNYT6dLLHbd)5iJNC>eVfFCbF}_i;%VnfG=u*5l+X}v_^gEW!i^4ufwXByzLcC6DeYrT#|5-;AM^?HdfZq)j1iLslt?jdpF z7OiU}Zr!T&T@pXpruBCc`)${HsKj}!y zY8~~IjyX^3I8Nf4XSLoaasTsLzb~=Vi&`g3JnLnxr%SwPzt;Cj{QNboe~>uv4Xw|R zIR8zpmrMM|+gd*>(Rfemwi5F`&^jRTvV&T0lK9%kT7M`p{!^`cOFZYW)-xsE{Ds!{ zOZ@VP);~&2`$p?g5*HlRdWFPY$FzQ4qU{H*+e^&)brKKI1dHqQBZ*yp z)%tXa6?89%*Uy%CD^0XnKOpfd`h`%|KS|7>2^#A$5*N~MhO)j$;^Xw=p{!q!7|~Aa z7>NbZT2GL8WvtfMOZ+GOz$ov3NMbkorBT*>C05Zyko8=Nx6^NrvVKV7H}oT zC{b&-#Kk?eUL|oi-ALf=Uy>Mky4GFyinp=iJLjn@wZCcF8&UVl+QyF zf0Wp7p!PE*=1E*6@j{6kBt9?kHHn`}>`Xsh$?2y^tdw}Q#OEa*lo&@p=E&Q3lb9;e zBk??mjS?S}cv#}k5>x300H;$e@fwNyB>v2i%K2A`4*Hcv)=?5WNQ{@5B(b-|ff6$$ zo*{9J#C(Z`63Zn{l1Npd@<)eMv9m-Pwkh39Vjqba5^0#E){m0tmgtj6!xFWAyu`^8 z7f7Vbuv$--R~0Xkc$vg2C2o{>oy40Y-YRjo#Jv)!dsgXDH>@Icrz*ZL@l%P^?I}N! zV;j2fC7OcrX&R;CM>ZYl|35ZtarDE9;u{0&7tNkuSw(SvosP9wq7UZJHwN-2;f;Y+ z_4UR;`t1HdHV5iEj{o^X5Nhiw{6Q&tFf?^8C8U-stE%d17U;CJL%+8dE-UN!8!K`& zy~XdHS^R5xk|Jf-7|1`uRzqJB3p?u6y2{zKk-M~LVCDSzb?wp|)+bLw&VzBpc7r~Dc~f34^*i~jhv zgKwhIzfQEw+wdRnb`Jd^5430;C$oy$4PIDcwp*mPn0|0NMyJPRfb?jn+akU3XPCyf zNF;3C(y(P(G;-;t;m^DvFYH1?+ZM;Y_A**S|M)yOKRE8Cw2Xad(HJw@G!l71URbw^ zbohB(d%3CF1*aE9e@JgDEn^>AG=h{Kw;#N)ZZjF->D?Zd9zVB1dOK(t`*0d_DZORX z*6_l*yU7SoZzrY4^~CvWPk%^{hJ-3T=7C>djWdnXUV53|IX(V+RwA|=y}&dI$ioZU z@x6ZJf!D33?ZTPne)I%iQ2TT6@vDJpVD9ZEw@c#M+*Fo1EkRUUW;<-lmA8 zhYI#K9ZWnxOGdw6-m%r*m%q2kNaAfGlI~OM_RG4~wYL}Urggq!yX$s0eU<1xzD?rS zRl8}Mn+xpUbu)KUYF&Czdg(_0U*0KgiWsvln^H{w;nl1YzYQ%qc5sO2M1sw8?D3@q z$F|LjNb;N*)vmGk-lnhSec1Hg->&v=@bNPJ?O5-p_lot!{^O@Pd5QiK>2Kaz_S1NY zoy#eYU+tzpgZ`rF?;!p0c4@0Pr4nAc*mp5+l~#1@qfCw!$^3qyZ-rMPoil5CSKHgw z`U^-OB;Bp?w;zA~&40YneyGx*HT%;KO+V9Se)rbOg}#Lai@b~S_4+{`|M9U){l_=W z@gLth&wu>nxgR#oUtU2+?$h{TQ^bXoIz>Z8J|6vXUMpmI_lHfN@1f=0^vC(%AwK5_ z+ZePwkNvYbuhI0!Yw7P`TGp}1>gtLyh1IoZ8z7Wr)@p@IC zg1Fji&65ZG$9D%_uk;-|SkGHzC1cyfL<9jHFdSANil?v!O3 ztBfqW+1N;b3C8Ni#!Msa;Oo?_wlRifQLD|OUqdycjbW498)=E8KmPpfU0d24!^UKf znDG&9m%KWs%fU;HVfVIqao-nHZ=PBIMnuGAiAhDH?q5Qe9dkLiy*JjhegA?!W8U3Y zySt%n=g%6(EuVDqlG_`jFP+@M`^EbkckZt>8hg;O`$XG}`#T%adv+U*iH5_-qP!&1 z@v~_8#=<~V^^EH%|6C(C_--iJ=G~@hq?9O&NZ;z)M5OOcdsEtyk;vP5j>YwiNxrJ^ zS*qa?6~9y^*WMsycc_xr>wVV}AA8d-DMULA?VG%kcr?u9in!V>p)z+L>ysR)S|(+? zoXUBzl&mi2^GI<%3y$rv&sVwTx>@L3MD#CKIp!mWYn_XQDi_mE$%P}Y-dA5R-#eds znsa$iYFqW$$C5LsZKd@}o=dHAZ*r_wDNaP{oqkGii%A$v>wcxsv1A-f9)k%HOWyp~^FT;YWU!j@&PKg7;ZE@`#Ev z3V!*6BM%Nca)v*-N*!0dZ&&Y!s+QDFmgD9YBv7W5gr=(s^S;|~7hDeAcDeY<);G-XNcL^*E%g5(-LZa;6eihc99t9YoUk2-E? z^0P!!)`^uKI@2`MpLfuBg4@iCX+N(^Img(U^4`)`b0^q(t!!hM%6Ye#_f^pFVu-ol(nY{_Wy7yc5XJ8h+lV*WZ5q`@`4UY6o34BI)Sqn-b$v_Z>NT z)hB1hnO%2IZ^?T0vAE>*-t`5{I@in@L~V1gl65RL`7(bXthUz_Bv0kDzrIdf^j66*E1M`1Tmy^Ppr+I6q;O(0M;U)V1s_5)S( zNHP1mmzquLdQ#`oUNdN!)0s=l(`cDf(5Po~)uk z)yx^2NsaZ5Ey(xgtJceX`P0;wHzs>dB-?nYL$b&Fbko7;eiefXj!;`@W>TN|KskB_ z<*UCOJB^n6$dPp(d&`manfLW2g^tc`ufK0V!2oZH^mtDbm;HV5{-^)2$BRpjEkcji zKa`sz(&O>I-F&>Kv*?Xed&^{d!PCS~|B61u`b({->m}Zwh}s*mbzJPOO&=e2F1oM7 zt^4mbTJ+Vw#s4GY&i?CfXn5<}*M?8397cWl^2+(krj$J2X?Xgjkl{U2nUSBN+MA3dGMK2Op8PZ7D3 zE1cACa=%FZr5X!S3Jo7Njod+hjcxoi2$a5$`#G*(zE<;fny=fNZd`JC!-Hp>UBBq8 zxr3fLbQ6swmQSzR_t1e-@8+uq-uc?(Ja^tOHIgz%MeV=FcTK@Y@5a!TFr#*Z&+PZr ztN!EP1ghJ5VPjW+ul-WcI#tzNn zx!s{LTHoXup>3;Z+v`K)1*FT@ZH)eUC!Z7AdID|TJW|v>tL|?DRV6~1c1wve-zk)3 zaWAB}j!n)FrJ3C#x760CEsUZ)!SV=NR{f?L84i)7=-x3?j!-~7V4A7{Zfk>mLkfm? zhpJj@N$P+QslABQEA@Ggdz(p3CkCU5RFfl->Qx8MSbSB|(r>u`>T=g>ulJpF z{PpjrO_;*$GPB%=G0O$hD(;>(y7Jpjk3ITYhX47U%La;x@DPx&pKRb>1!cn%(OZyW9h05xX0ujaHR4o?|R>Ql@6V~ zCbsg(^mB;V3oiCjsjn`WDXqYN{AKFlR!WU^$0Jd$9;QtFrE`d8Sc8)bf>?^NhC8Ol_CsNuk^oQ0}&d+D+@^0L`=lRk?Cb z<7hdXmYca9O-heF_&5c$p1E#5GPk1rnSrW7 z_v%AwJ+8{gxw`7B_76cl=J4RKDON*YMY&tdxW-)Y0);ZE%y#+$sLnBNjIu!?U(FFxT^Tee-j=yFTT_-g$TLxagCf%=I>!$E{8N zz4)?cS^uTJJ67DcXPfG$mk(&Incq`kG}32{8~0=xjr~I-Yq`eBEm_g&%%Az<{~EfDwPtKy(akzDS1uu8Yz3NR!P}wl2?$z zl^eZgQu2yWDK0ss#D7onB41q#k|TuV`M&uD4c>;|k?cNJMdP}Nbh=YhP1lgLIld|y z3++vNO~y#cwNKJ$xmvw%SMP_^`=kPF;W?I^)FC->I&EiGsP}E^{h)g1y8^{6>b@Yf zXYve{wtC;L-Vdqw?9djRcK77OnJR7dzD>O!RPUVjP)fVG^<;+jOrE9ER`1)@`yut- zKePp>-6c73wn|&QZ&U9F)jOx1NNG1;(fatFq;lyR+Mj10NpooLm`e42qk8{Hy(f5S z+vvE8_LPFmp-XsF9Od0#Nmnz~+B*511wQHVI`}Lv``n6oq-D~YL>YV79*RkNEXrKF zW7ff5xi<#x2k-ZdTD4%`_%m*tcVU+`s}^5>_Y(x5GOH=Qgr`DiPn;lA>)0iGA3IFkK)l=0vPM_OL zmAbRAm0M-GzP=n%W20cfp~|4Q!dDTxz8tEgI|btoO+TAj<=HFz#|Kmgyw!3>TpkmA z{(}5!oRuxH%;%Hx(LL$Qfw3))OuzmqWykr*QtSB4xZRFY>*T)JU~0ECl64mjE!ac% z-S#vc%yL$|(0s38JY9bpoQV^YhWkpm8tC7wsH(X*ox9g;G$~8iL?gDD%4blOP_pg z@FR|2{yu7FL`IhpPf}mIf3+SbbKiV^&m$)vc|4-`m2ckt)3W||-OS?=?uR|Xzb)|= z-z{O~zuk9JsPwr#Yz>t@*WLBL%~E$<1Gc2izH7qhc%`RC9b zxd+O{BqpjD zg{yfv^|*rxCobLfY)TtF9?@5W%YB!(IHxtC zb7Epw5uv)b;`6d4uJm0f<$<2@{6ZhyDGuuyC(xX+(-Pm|$|VI$y-V{yQ{z`2uQd0J z4F}GnrxOe1=|umYbT2V;R?){*)fF?-*&)2+FjxVPm*PAO_^^vVUpskJ^cKh4~+1_kfmn7@nr*)$#g{KaW z_KhwW;~gXGJJUFdbM!W?f9dcUzB39&dPmB-SXsxped6#i->`z=-r=$?O4f1C?ms-( zH<)IiLu6fq9P>R|xBam31arxJg3V!5ir#bOe6%d#_**}u-*S8AmzkOWSo>J}x*dV2 zlXu>=JuMQrDrcVv}gQlcMVK#dVS1*`mw96qQ!Ibdt|>^(|B6%K6h7p?%sR& z>|K-B?V7gqv9nsIe>1rLh4Y7*Mg-pwrvJ%%5q&Vb~v~H(ODB5p8dau=sP|_LKA}8=Jp#g|Zy$x{z{OvGi!z=5+i- zpS+2Pu=ppDY!Qwzl#uc!iQP9qs8^uZ>LF$#Fpk+QxB|GHN+qx6`hU49cy;aWN(DbUZrr04$a90PjL19rzN35F5v_?fnhaa>NH4~lhslSKcUuVa5} z`rk+$KhYEYj*j)TWhX~eH+o3zcr=+lF5?(Yp9bmdIG0MVi{l$w?&`RkO0kzLEkEbD znvU|k<1poUpCgw(V)cS!E1mU=juJZGmmEcO^p~AqQfUk@opgK5NHLvzXsdyya~4%Y zs_6_+ZqiKW=@hOso&Bi9*O|^UD5L95=L1xBSDVhesJJ$mPLs;$8q@hP728JBd5}`M z)^x6*tZXu!t7*&4rt@~n(sicu03GPK>1?9#gXzqTFpLwXvy#-0rt@_=zb4Z;mohfd z=IliW+GTSdqAY)IcYa4Kd|`J!M8*B3-Fbl0JYsid5_ezOorSdD*LLSVDx`1h&WEWq zzO_4t(TN?kJA2X*zOy?I(-8_IoL^DWMG?-Sl3F3P&Ms60fe7c>biA?%XM5VAJi^J}aTp)ryp`&9LWFZH0X8wh`3%u8DZ+UVB{n(2 zIgV=i%n0X1s`B#eb9-k3rFlzx zXOPa}*7nYGNv)1^en@~`66ZWfyGNhyyq%lF=}!K7%RHB}obqz6%XtRntj^_}Nr$a> zIXh7y&v!ZBpu%c!Is4FQE^s-s=m_VzoF!Bp3ti4D)-?Fy%|d6GhfU$**~*3FACjaJ>MNY3Sj4BEGj7eYCCPbTrE(cT*wPIP(iHVg?`C~v62^lrb4`k z7qSWUi+Q0fox>_#*hPiDE=UWBv~U$Klu~Zj^TGpkW>@pV=XBm1c%hOGv8b9BuA-t_ z%nPY>PW;)IRxi>jlNSaO1bm%o^)%H0e<{6{ox4z8=t5^f58{nhFA+BM|4$pOYN#e0 zyiiS!lNauwW3}Ri!&IxSdEqRoktkkBCz9v^jM1tcl{NjZyhf{=srPBe3z4*OdtPXw zjiY&CJZ%%h3)NJ;d`)Y$lS(X(7c$7{zzhGNO76%D{5>wtb*sr#1@sY8qt$Pec^fax zq(ksm>07n##b-eabbfRew7}oyi{yp(2oK(>)dfVG$qScLf!lcD3p#h+&uG1e5{j5( z+P9I8T1#(fR2prT(n1fq21cHwBe#uUzg>iNnl*~*r+s#sVV&OTI`SgS9wgHZtB=S8 zk{O28S7djRnTFL*WH*w746DD$t|SK=)&P-RNDeWq6p@`t4mGTSBI8L8GptmRE|S9y zD@|l4lIfJKbkQAIQ@%1pcVJB!%M=~QnsPQsbS!Ji+F;Q!tSN6pL`Sox%ncRYo;Bre znCNz_DSN|3w`EQF8zH(4=?u!>8KR?DQ~pMZZq1tVH%fFX)|9`|qMfWMe`7>DSX2J8 zL`Slw{JBM2tSNulq9a&S{yd`TR|>K-D1SMkZKN|Pf4QPf)|9_I(Nx#b5mqmIkm^6? z2Exhe-GKp!nMlpt8tWKE&@drBD@cebLJDP9A*4v85K=5s2=R*)LP|smA>%{}A*CXP zkbp=bq)em`QZ5pNj28_;CWrWYHkxOwl0ZEYTq3Y|$X(9MK>oC>n%R zhz22*qCrTNXb@5@8iY&{4MJ)}gOI7BLC7@GAf#3_2$?P#gv<~PLS~BAgm~@Css3Xw zpdQRB(1iTLgv@d9og^&i3LdXJlA$VH+- z$i<>T$STnwWVL7za*1dVvPLurxl}X=xlA+&xm+{|xk5AuSt}ZZTq#-;GRMB1>ObaF z8k$*iH6eG=)!$m@U~-s{4c2zL{3=4OkzIw5jUt7RYefnnn?wpBn?(vC*NGHDwulr$ zt`{kUY!xYl+#nK!Y!eMaZWIkdZW0Ybwu=TKH;V=#w}=KIw~7WKw}}QJw~GcLcZdcd zcZvofcZmiecZ&ug_lO1|_lgD~_lX7}J4Az!`$dD0zljDR4~PaK4~hmM4~f==G%2JSI{Id0eCr@`OksWVc8m zWRFN8$Ue~^G>Ekx(S-bqrX<$84km{Q`OrE{^9Du8LD^LZ`ADP?^07!EW7wA>WDyAxA}nknco; zkYl1j$oHZ_$Z^pia0{v{fO{3;rR z{3cox^1i(_!4b2TCPmfn!5~07Mp!n}UP6Gx4&ec;-P9CK zp!*3{Z_~keF-3h%>s;!36h-~8zfja4S|}O-Efl3d3q=E=g`!kwp(qVnC`yMGiZY;u zqD*K|GzbPL8Vmyz4S@lQhQa_v!(f1-;V?ka2pFK~3>ctjBn(hA3I-?|4FeR7fdPuL zV1Obw3{aE}0~C2+fTA22pePpxD9VEYipIhKMfos5kr#%h=ycP54FM8cO*dn#K0?u> zbXUbHFdfVnQ&enP4-;65B0u&Qib|k`qH)kdQ7N=g6o3|r%Akd!a%iDwJhV_W0a_@U z2n~uR!2m^*VSu7DVSu8uV1S~tVSu7@V1S|^3{X@70~A%l07X?WKv6XeP&5SwD5`-0 zil)Kt|VHNpTz%VB_`3t@nw6)-^2N*JK%A{e0PVi=%k6%0_c8U`r31O_Nt z0|OLY3Ih~f1_Kmb4g(Zj0Rt4Rg#n7LgaL}y!2m^9!2m_;VQ7lZHSIm=W_9dGJaDcP ziq2qhwdr8Kn4)V<%R>`#MbRegFBENt7K*Ne7K*k&3q{vM3q@O@g`yjvg`#cHLeY)T zLeWjoplCY`P;@g4P;?6nP;@H{P;?s%P;@&CP;>_jP;@5@P;?gzP;@s8P;?IrP;@U0 zP;?&*P_zRED7qg8DEb==Q1k!{Q1l=SQ1lQCQ1o{gpy**3plBxyP0=-`y_Nupox$Ux zjY830rsxsV!F(}AkD1mb^qfXf^f>kxik^TLigrT_MSGxyq9>t+qNkvRqP@^U(bLdE z(KFCO(X-H?=s6gm=y@2RXdetv^a2b}^dbyU^b!nE^fC-k^a>16v>yg2dKCsJdJP6B zdL0HRIsgL{y#WIh{SyW#dJ_gHdJ6_9dK(5PdItt5dKU&LdJhIDdLM?S=uy*tF98y} zk-^y|6x~M;ysQsQ2lK@geQa8<&}|?^(IMgH=zAET=r{~e^aBh~bOHt_ z`Vj^wYJvfZeu4pteue>xet`jsPQn01|AGOEeuV*weuDvu3|nZHujgnc3{Yf)p(#3O z+K&?;vA5H6QR^e2=wW_7Ww$w)FQ&+0vpSw86gjcKP}B-qC~6HY6h%P`MQxykqPEaN zQ9Ed%s6Dh$6b&sD#Xy6iSQwxv4hAUd00R_tgaL{=!2m@r7@#N~1}N$b0~B?E0gAf9 z07czkfTHd&Kv4n=P}BnkC`yC@ijrV}qMk57Q8Elr)C&eE>J0;Z(P=P1(djTWMV8Gz zf&huFrU&9yq)pHCU#HI-Sbb~`=8GvBV6)EbBNU}zf1zj~v`~}^Efl3e3q|SBLQw{^ zP?QNR6b*tFiUvaqMMI!L(NGwmXc!DoG#myf8UX_oodE+Bjf4S;M!^6@qhWxeF)%<; z77S42h5?GQVSpkJ3{aE<0~F=L07ZE)K+#wjpeP>(DDuJpMFlWGkq-taDukga>Swbz z5+Jb_J?XUi3q?=S4QZ>$=3u^c&LeW;fyw%wp%okI%z-ApDAQYX4{e_~1&_dB7XrX8^v{1AJS}0lyEfg(- z7K+Y?7K$!_7K$37LD6y;py)yvplAgQP_z;TD7pv+D7qL1C|U&r6s?8MOVN8MQdSzqAOv5qIEDp(N!=&(Rvu5=xP|CXafvTbPWtm(R`b| zO$t%OzesI02u0KBLvhwdn}hjcimtO+DXBuy7VIw+T@Ni3ZG{$!Zh#hwwm}O;H$n?V zH$e+U+o6S`o1ulGTcAPFtuR2*Z7@L5?Jz*m9WX%AoiISrT`)k=-7rAWJupDgy)Z!0 zeK0`L4j7>5ei)$WZ!kd71290*gD^nRLoh(m-(i5Fhhc!CoiISrBQQYGKVX2OM`37+ zHrec@1W4>~`ecT+Stu&x%iAuSgZW~LcH6A_bfIVu_7{qtgcgdPf)7@+7)7@+7a7@+8F7@+7K7@+7~7@+7q7@+8V7@+6_7@+7w7@+7N z3{BDFHv6>%NbC@PME`_P^f7HrOjI>G=&onU|>7YtAo4+9i+h5?GYzyL*EVSu7; zFhEgv7@#Nt1}N$Q0~95~07XeKKv7Q^pePvzDCz|R6!nGyicW(8icW_Ciu%9+MSWp_ zqJA(mMNYfD*ASwpKTq!I8vy(n=GZni68-HC=8GvxwOhHvgrYR;FBGLi3q={wLQy8P zP&5cyC>jhc6b*qEiiSc9MZ=(lqT$e>Xao#UbOsDiG!h0V8U+IsjfMe=#=rnYSujA6 z8wM!Kh5?E^FhEfb3{aE{0~F=K07YYAfTDaDpvVgY6cxY#MLrmys1ODyDuMxuieZ2v zKMYM#irqeg0ExYj`=WtDQHq^JiQU0`F-2u|>(UWIQ91S(ipE0=MH8TfqKVK#(IjZ0 zXfm`=bSAV=bQZKwbT+h5bPhBq3c>(I6)-?iB@9qh1p^dS!vIB7V1S|;7@%k>3{W%; z1}Lh90g9%>07WxkfTEc&K+!B1plCJ>P&5YyD4Gic6wQMHiq3@rit1p1qIwvhXg&;0 zQK{X&g8+$LLtk350z%PDz6IG}cQ9W}(IUI`>PVqzG4>aVmOu+dOQD6LWza&=`Oreq z1<*oKBeYPo99k&45Lzf&0S$^)!T?1V!2m@U!vICAV1T04FhJ2IFhJ277@+7<7@+7f z7@+8K7@+717@%k^3{Z3>3{bQV1}M4;1}It&0~B2i0~Bq50gA4H0g5)l07cir07aW% zXo}9W+fNW6u@CTodZAEsK2x;W?qI%{qOEqz^}pD=5BMnSwO{woWb(|UCo_~8Y7z)V zT0$?DyX749IuMzvQ^O=Y*q9oTNTY?tD^aARkVPuir!+Y zqJ?Z#w1|zO#RL?+O+e8*1QabHpy*u!iryojXej|j%Lpi1PC(HL0*c-zplBrlMIR7Q z^dSL7s|YAsO+e8a0*clWQ1lT2Me7JCT2DaH#{@^wEVsL?0pdR_-;I4;6=h5^;}f@6 ze2JpZ-1gIzRM94mS4ErIs_1jJD%!$UMO)dbXd7DrYkDICxT`o#S{_ z^aEQJooB0}3v5+%k*$g@u~pG!wko>9Rz*LuRnb*8ihd%X=o$e<*9j=PK|s+>0*Zbn zpy(C>MZXYGben*pI|LN{NhwUhG5l|FHK#`k(qHqF=Yyyfr1QdA* zD2gCBioSQdw;CY+mh$sOXH-!c`3^{AxL16MqS$czTs2h`$MLEto~?=!*s93KRz-fc zDoV#zMd{h9C<9v+Wn`5m1z$fT98f6cr>milW2aagP{9JLNC; z$AmkN^cTwCODz=c6yeKv5k6iXJ7P=rIC{>Jm^?kAR~31QazOIEvE3-H#g}{v>&%Usx55lpn%w815Bc zqNs7W-K&-=YQpiV=t;IJYRXncPq9@|Gqx&vnyreSVXLC%Y*q9uTNSlnqo^eTMXd-Z zYE3{<8v=^j5>V8RfTH#U6m=k=s3QSI&k<16iGZTc1Qc~4pr|VWMcoJ}dY*uy?gSL| zAfTux0Y$wCDC$i>Q6GY%s8P84RRhGIlw{yMp^8q4qQ2o?@g<4|hT9+2QAL9|UKPE- zRz)weRnbdqRWz8biiWUN(NMN38pc*d!`Z561RF&o2`CyxK+$LdipCI7^fCcOV+kl4 zM?led0*WROP&AQ%qDcf4O(vjd3IRn^2`HLIK+!7%6ip|fXa)gAGYKeqm4Kqx2q>CG za1`|qcONrA{I|@s2dJVka>w*~xL16MqBp{AS6x-~CdaFyd2CfQpRI}(uvO7pY*n<7 zt%?@0RncO$Dteo(ir!(PXbAyD?-Ee-9sxy52`E}dK+$pnidGO%^gaPaD+wt2fPkV8 z2`E}cK+$Rfiq;TNw3dLPj|eDQM?lef0*XE+py(3aJ(wo%2q|&*s5qdTNUkKtD>E3RrCd0742fHqA%I1 zXg3>0dk84nOF+>+0*dw%P;`KRqJsn!9U`FUD*}oR6HxRu0Y%>sP;`WVqHhT(`i_92 zqXZNkBcSLw0YxVWC^|_%(J2CoP7_e{J;715Dcs%30P(ky4`Q2DQR^5p&V+l#mnb?P zZjWoIiY{=xD!Ry4MVHvB=rUUsU16)DAK9wtDq9u(#8ySu*sAC{8$~w=D7r~N(a!`F z-6Ejq7XpfI6Hs)AfTCXsDEf_nqPqkXnZK4T-?j`lzsAx0&1UoWmR$rCg%MEXCZH&s zfFhfKA`byYUIL0D2q=mqpeTxfqG*Dn=v=sag#qH9B44ilK^3)>NBS|gSA2=01l!)% zNEP`wUKRP-swf>>6{TmZq6}sGq*$F60 zB%mmXfTCmqigFN8l#_s>6atEJ5m1zyfTBDE6y+tL=ph1%@)1y!pMatQ1QZn{pr{Z5 zMX3Z7r4bxOakl$s1H|7~elRWGb{^@6%a6|%w!Pv@6cxAaOiff#3657qCE2Q|6k8RQ zW~-tyY*q9yTNRaMtDiYl;CRFQz9N(2;DCZMPa0Yy~_D5^$4(IW&DRVSdR z1_4Di2`H*XKv8W1is}$h^e6#Ej}cH*mw=*r1QgXLpr`=>MGXlkdYpiwMg&JuQQKYK z0P&v|IK@=a8}h}YCv30y5=BjIyLnSp^c2UdqGoJW^fX%)J;PQ-&DpBxS+*)_!B#~r z*{Y}&TNSltqo@r5MQsTvYDYj(djg6&5Kz>SfTHIJDC$H&QD*{*x)4y*m4Kpd1Qb0_ zKv8!Bih2-G)RTasUIY~NCZMPf0Y!ZYDC$Q*QGbG?sEO?!W`OvglApVNQWXuA-(EGq z_KGi2^rCGqXr_u@;&@dwn5~M2uvO7ewkjINRz<_vs%QjT6^&%8qET#BG@6Z~F$5I7 zOhD0C0*b~FP&A%^q6q{PO(dXb5&=b%2`HLEK+#kJilz}z^a=q*(+Mb=K|s+=0*YQG zpy)LMie?c|^g01Wvk54gLvR!gvfbMa5Pu{2x$75HQ68Teb8WBq5=HZE`}{MiXaUEo zqPN(pXdzn_En=&p#cWmdHd__F!&XI0*sADVwkmp$jiRLl6fGm5XgL8zD+nlhpMav3 z1QdNhK+%T;6s;nlXf**vYX~S>OF+>_1Qe|!plCe-MIRGT^a%k)8we=cNI=o21QdNn zK+z_Gqv%cBozUDU8Yg!@^Hfn4`3}ft+bh0A(Kg#I+(H#?=Xh1LgRP2ovQ^O+Y*n<2 zt%|;6tD@a(RkVk#iuSTq(LOec_7hNafPkWd1QZ=2py(?CiVhP{^fduR-w;rAgn*)N z2`KuGfTE)W6dfa==r{pICkQAyNkGvl0*X!(Q1m?kMP~>oI!i#&IfA2Ti|u~G0P!cu zk6Le4MJ|^aKiFRJC5kTDcAr+N=rYHvqAP4w^dnmpU1h7HpV+GC8e0`zXRD$cY*loV zt%`nTqv#d^MZXYGben*pI|LN{N^k1#6j1GP6}t7PczN%2q|$*eJ?QKv5zAMM(q{ zB@+qTB=&vc zfTF?#6cr($s3^fvs7$E+eNd}JJ<2=$IDId{_dA#CF6qWMW?)IvvG{>u=GHg}! zFk2OsWvilcY*kdAt%@qJRZ&H@Dyqa*MU~koszN|fRRW5t5m5990Y%jbD5^m~QB4Ah zY7tOWn}DJ^1Qb0=K+$6a6xAi5s2%}D^$93yKtNGL0*W3dpr{c6MNbe=)R=&xCIm-O z36DFk0pi~!AH+(kqRjG}XP)$U#g{00+GE%3sEVH9cvaM#t%{yytD+WcRn(HLidwN% zQERp;YQt7VZP}`*9UDdM2`K77Kv72mik>5&s1pH2oe3!FLO@Yh0*bm3Q1mOnwJPXda15m3~dfTBJG6!j&bs2>4E{Rt=ol^hO<@C2(~I3$yP<9*s5qWTNRCAtD=|Ls%R`5 zMdJu48c#sc1OkdC5>PaWfTGC+6ip$ZXet3k(+DVfg@B^z1Qg96plBumMXwT2^cn$0 zvj`}9oq(d*1Qg97plB`uMQ;#L^d`Yk^peND(g5*K%W2>YRz(Blj%l99E51b0LXUl* ziz-^g@v3MsTNS;{Rz>fyRnZc*Dtec#ir!t zP;``lqGJRU9VejZ1OY`S2`D;6K+$OeioPeH=nMfxX9*}eM?ldJ1QeYopy&d@QMBFT zu4sVxKbG&K?NCL-+-6+#c*U0}`q5*z=%I?Pa=a?~iLHvRu~pG^wko>8Rz)}2s_197 zD!Rp1MZd6B(QP)0?hsJ)D*;8n5m0oOfFjGQ58F}XBA_UYfFd^mMd1V#*#s1M2q^Lr zP!vHxQ6vFHQ3Mo46HpXGKv66KMR5ca#S>7JKtPd?;3&H6agQ)S{2k1%wzjXRqO z9Q|Ie_!31Kz4pRhswlwmswl`-MVZ*DC^K6XWnrtLtZY@3jjf8ZvsFS6uiM|(D9S4LMP*b`izG9edA;IG6g}&;i}qJVEjV5kwPdTJ zR%}(&nyrf3uvJl8wkm4JRz>aEs;C276?J5z=s5z4IuTIRnSi1$1Qc~8pr{)GMb8sZ z)SZB$9t0HiB%r7l0Y$wDDC$E%QC|Xz`VmmnpMatP1QZPQMK2Ig^dbR8FA*F? z&v@NU3=sbT`94~6Rn#HbjKN;7_!33Ky>`EWs%QkqtD=!?RWypNibk_l(HOQWdYP?? z#IJPPp&sIef*eIGvK+z-uiY60KG=+eosRR^FBcSLN0*a;+P&9*pqL~B~y-GmQ zYXlU{BB1DX0*Yo6P&9{tqPYYVy+J_Hn*tP;``lqGJRU9VejZ1OY`S2`D;6K+$OeioPeH=nMfxX9*}eM?ldJ1QeYopy&bt zMHdMux;T2z^C{u(zX}BuN%<-xy3tJUsWvilWY*mzu_N)S*~l7OO81QeAfIEn%h?hg$R|DF^BCm7*8(yuRn zlc-FDSA2=0@)7o-k*cTy$E%`>Y*kc=t%@qMRZ$hTDyqs>Mb+4<=n=Lms?JtLHP|Ss zNkCC80*Y!AP*jJ2qDKiRdW?Xgx&#!}BcP~00Ywc6C~8PR(c=UZH6ozs2?B~56HwHI zfTAY}C~8VT(NhEzH6x(tX#$F#AvlW4M!4@7ApZRs44iVRsE&;05nk~nidse3*~X}% z)*P>j+OSnoTed1{$5ut{*{Y}mTNQO=tD@)Fs;CoN6?JB#s0#r_T?r`aMnKW?1Qc~A zpr{7{MLh{9>P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_V^L_pCC1QfkUK+#JC6b&Yz zXb1sCLkW(e77^~s28e%CW&@|CD!M3&hDCVAmna$)VYeEqibiw1DjLI9MK7~e(O9-B z8pl>eE*{bLeTNQo9Rz-)|s_1LBD*A@4ijJ^R^eq8J z-w{xBlz^gR1QZ=7py&hvMJEX;Iz>RyX#$GAC!pvI0YzsCC^|<#(GLU^ohP8^0s%!A z2`IWmK+$Caimnh)^dkX9R|$@y-4X8elZ>Kp`Ksd{Rg_M?ko{AHSA2=0n-O;LDXQpa zj#ovu*sACkwko>KRz-K%s_0j?D*BDBite&ikrk}F#Su^xPe4%u0YyFniu?o=r6ZsyJpn}-2q?-( zKv96;D7qfuZfbz|%Ox8)H&oGVQ51~yiZ4-=HPRk1O%-M1cvY00t%?%aswj!Aijvu? zCQA!U!tf|q`h&vDyq!!s;CNE6;)-cqH1ha^axuORcEWB8f;ZmldXzs zu~kuRHj3&HQ1mDPMUN3sRF{CFdIS{JC!nYS0Ywc7D0-ZLqDBN1JwZTGV*-kr5K#0a z0Yyy-D0+&3qGkjXJxxH-GXxYhC!pwA0*YD?97Po(-QOD^{xG@wsi=yYnwQxvBfa8F z6t#`Cy|1dGb{wyY+Ot(r2evBe$W}$qu~ktgwkqn(Rz+Rds;Dbl6?J2y=y?K)x)V^; zgMgx*1Qhimpr|(iMSTb;>PtXTKLU#S6HqjOfTDo}6b&Mv=mi3bUL>ICB?5{D6HqjS zfTE!U6b&PwXgC2yBM6S7){*W428cgF9_hDHMVE!t$VjjF5=AdZ+K3qqxdarwK|s-)1Qg99plCh;MGFWhdW(Rfg#;8WBA{q70Yz^UQ1lML zQ8YTz-Q583_mbaVG)5JblJDs+iS&vuQM4@5o-$h%E$4Vuw1TaQ-e;?#m26e?0b3P) z$W}$G*s5qXTNSNgtD?1R6n#WM(K-T())P?lF#$!N5Ky#%fTE2A6n#oS(Psn{Z6cs( zGXX`P6Hv5;fTFDg6m27*XgdK#I|wM+NkGvT1QhKepy*2iigptmMejwrR~sPyD)MvJ zOI6V%QM4!0E51b0fk^xCTvc?C<5kfiwkrCHt%?q_RngaMRrC#86&+!#qHo!%=sUJ5 zI?6`TF#?K?6Hs)5fTEKG6rCcV=rjRE-xE-DhJd281QeYkpy&qzip~>Ibb)}Piv$#1 zBB1Cp0Yz5`DEg6rqN@ZH{X{^~H3EvR6C6eRBHh0kApVW=;Ss=?N&xKtNGO0*V3z z6a@(=%0xg>W`d*W=SX)|1H`{iet*#|Ra8lS4NaCPulN#0iBWc&1*#~C<5f{ITNUMC ztD>B2Rg}V3MY-6jC^uUbM>&u5FUzPHPJ9Pe*%gI5KuIbfTBSJ6um$|(TfBWy+lCKU;>JU5KuIf zfTCdp6b&b!XaoU8BMB%PML^MLf}^Nilsn_wM$zr822Oib6rE(om?*FK5=G;q?2=1V z(FBfHMHAVoXcAi$O=hd2DQs0Vm92`Vu~pG4Y*jR!t%_!_Q8bf)qE`thdX0dhSp*cl zPC(IY0*dAkP&Ai-qBjUAdXs>nc?1;AC!lBn0Yz^SP_&SMqD2H0EheDoZ32qkA)sgp z0Y&c;Q1l+bQ8YHn-OK>-mya`W#;Kxu@=4OtD6jYuMej%1gWgj`D>+^jeZW>lAF@@^ zDz++G%~nNg*s5qPTNQo8Rz>UBs%SkMMIRGT^a%k)8we=cNI=o21QdNnK+z@wiZ&Ba z^f>`VTL>uHNe4UKM@KRz=^iRnZZ)D*BeKioRp3qN8k8 zbd0TvjRxCfTGg`6n#%X(HR1Y&Js{`j)0;c2q-#FK+y#PiY^jRbcukX z%LEi%A)x3-0*bB@Q1lZ4Mb`)@x=ujR4FZa85>WIr!BKQD%6--V@o#n+IEPfx)AExc zx1zk_OBDSYWkJZx3uWuqv9 zfTBnOilPW8iYA~ahJd120*c}YD2gYbD1m??9|1*v0*cZRP?Vm4q6`ESWh9^|KtNHD zfTBzU6lEr$C<_5aSqUi0MsO6}j&c_=K>WLN8aQ`U(TDQIqwLXM@g<6KMB8;gP(?X8 zUKORVRZ%XsD$31PMS0k&C@)(TJ;YW;`Pix`KU)#L{arN1Cwb`nu z4qFvH%2q{>u~kuBwkoQ}Rz>yMC~81JQ9}ZX9w(rv5dlR{5Kz>ZfTAV@6g^2mQBwkn zo+6;A839F46HxRF0Y%LTD0-HFq80=cwIraZ6#+%92`FkqKv7!)irNtzMb)C+YYh

    df(~s0&*ab!DrfZfsTbJX;lYXRD$fY*o~g zt%`cFRZ(v?iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(F+6=y+}aOO9T`RCZK2t0YyUz zC>lmU(QpEaMi5Xml7OO71Qd-XplA#MMK2RjG?w5f>KN^|)*3~FvKu(hsiM8+W%jse zulN#0lcMe9b*gAG$E%_#Y*jRst%|0xRnaSKRWzNgie|7?(M+}~dX=q;USp$Z76C=C z6HqjpfTB4B6wM`|=nVpj-Xx%C9sx!32`E}XK+#(S6fGp6Xb}NLiwP)tn}DKs2q;=Y zK+(Gd6un14(NY46mJv|2oZu*$5bb`%0P$avPpBuVqG9rR(TZrV_!31QM%(Q^Rz<5g zUKOootD-e*RkW6^iauhiqIGOlw4SYsK4z<;PuQwx0~0I_9Y0V--Q|wyP_$QkiK1_!?RPh*q9YuyioRv5qVL$M=qOti z9b>Da<7`!Qf~|^9vQ^P3wkkT!M$z{K6rCZU=qv$6=LjhJfq6djIs?=?XD zO_B_puT_yPf34_Fv{!tIA}hxJ=~GqYiqS{%swj-Dirj2f6wX#fHd_^W*s93ORz(qP zRTRlqMNw=NMH5gILqJh10Yz~H6vY!zlt4g{kANaS0Y&KuC`wO2Q3e8vG7?Y}AfPBn zKv5@|RcU92`q9{4WE51Zg zt{A)YW>u7%<5f`}wkpcYRz(l7RZ%{+D$37RMFrTZs32Pv6=JKRR5psz2q-E{Kv59_ zii#3YRE&V4;sg|xAfTuu0Y#+`T{~-CzGbu67BmE}wt=UInyy8m~)rzrS+@gwVbG$05 z!&XI)vQ^PzY*kd3t%~ZgRZ)GmDr&%1MGe`i=y5iR8WB+R1OY{j2`FkpK+%%~6g4HF z=qUndfTCv!C~84KQA+}fS`kpxnt-A<1QfL;pr{=IMePYF>OeqI zM}niMMvQyD0pd@VFA>#LMM3$yvCqYL#g{1R8e?zXri!|8yefL0t%|y{RZ$PND(cBr zMZMUns5e^`^m5>PaXfTGa^6pbOE=w$+m#u898j)0=^1QbmmIEp&QxPLG}{IAK+ zU3XDMZ-}CaF<$W{il)Zc(K}VqG>%tAudr3obhav*!B#~x*{bMOwkmp!t%_!`RnhBg zRWzH8qB#T<%_X4d4FZbZB%o*>0Y&o(C|W>3(OU!*EhM055dlSu2`GA-fTDK@C|W{5 z(Ypi`y+=UNQUZ#W5m2<8fT9%y6unPC(Mp1&XmX4@%>ePwlApVtqKan8w`MU|Y*q9zTNQo6Rz(}ws%Rry6@AK9MW3-zw26SC%>)#E zPC(HX0*ba0P_&JJqU{6}?I56NCjmuY5Ky#>fTAx6DB4Xx(H;Vd_7YIEkAR~61QZ=0 zpy(h0MTZC|`ig*}!vsgssu*`~1H>ODzhic_D%vdH4*5F9E51b0cQN+#-Kyv)$E%`a zY*loet%^>tRnbYdDmukhMW@-S=zF#*I>S~)XW1w^M?ldJ1QeYopy&btMHdMux5K#0Z0Yz5{DEf(jqH6>cT_>RE1_4Dk2`KuRfTCLj6#YU#(QN{X?hsJ)D*;8n z5gbKFV%+Nt5Pxa;s^hn+XmC0+?#6hCH%q^@=Z1lsDGSc|a9C#PNDxl#i{7^0QS@0k$eC$W}##*s3U%t%}mv zs;Dqq6%}Els3-wN#Rw=WPC!u!0*Xo!P*jS5qS6Eul_8+$VFHTE5>Ql*fTHpQ6jdOg zs3HMHl?W)ROh8c;0*a~W~^6y ziK0hi?GA@j(PJF1it4geQ9ZUQs?SzM4cMxvAzKwa&Q?W@*sACWwkm4OMo|+2ik>8( zs3`$OPZ3bmjDVu22`GAofTHFE6g^8oQ40c!S`tvyih!cl1QfL)pr|bYMePVEYEM8> z2Lg&Z5>WIU0Y#k%DC$gb6xEJ(k2gU4dF40H)KNt@<@;z|V!h%^6m^fammXF{Jvd$! z^<=A}UTjs=o2`oauvJlCwkqn!Rz>~Us%QXP6%AygXb=HKFAz}lA^}A&5l}RkfTAG; z6b&VyXcz%S!wD!FK|s++0*XcvP&Ar=qA>&%y-YySSOSX15l}RqfT9Tm6ipp$2`HLJK+${xiWU%1^cDd{3kfJ%L_pDE0*c-ypy(X} zik1*i^ezEK?-5Y6lz^gT1QabNplAgFMeh?(w32|L4+tpwkbt691V_=dSa;?lM$zkX zU-XJ9x+RKM$9lz=C|Vb5Km464TF>#S=wr4j`h=~DHn3IEMz$*Yl&y+BW2>S~Y*nI7s^|x{Dmu?b(FFpEE)r05 ziGZTZ1QcB%py)>eimnn+^b-L^*9a)OPC(HO0*Y=DQ1mkaMYjkj`h|d^+XNKdA)x42 z0*Zbkpy)0EMOK_XFh`M#;3zs8>we1s@u$g;Hy%?(%W{|z7UvaTqR10xZ#kigyd1BJ zBG{@ZlC6rO*s3U+t%_pUswkGNisIO+D4wl~64)s65m4kOpeP*yMd=AB%0NI-Mgocg z1QZ1cD9S`YQDy>)vJg;|m4Kpb1QcZ_peT`mq9g)}k_jlvK|oPX0*X=yD9S}ZQEq~x zC_K)6!2t0OkWZ-XIOmc6Sou|SRiVCt-Q6aV}N@c5}G`1=# z%vME3*s7=~TNM>!tD@p;6qO*Ls3ZYJr3ff0O+Zl@0*W3cpr|YXMdb)6Do;RB1pQl$fTGF-6jdRhs44+P)d(nhgn**z1QgXEpr|GRMYRYhs!ebdJrw6IVu1KF$#22R zr;0kuw?pd0dBv9~suyQBJfn*0bG#~Qz*a>K*{bMqwkm4GRz**+RZ(NMDr&-3MNhI- zQByXGo+6;A839F46HxRF0Y%LTD0-HFq80=cwIraZ6#+%92`FkqKv7!)irNuS)SiH% z4g?f+B%tUy0*X2jP}G@#qAmm!btRyv8^KZZSe(1B0pj0~-N31lyY(J%svh7(XUf`Fot1Qd-TplCD!MPmpkdYOQtu>=&2BcNzJ0YwuCD4Iw>(If(j zCKFIJg@B@|1QbmpIEs42xj!~Q{MF@ySWi`SF!X>e&MUq|(W`Ox(etY4HI7$Bv)HQW zb+#&+%~nNo*s5qQTNS;*Rz+{JRna`QDw@wm(ET{^fTHCD6s;hj=zRi;RuWM30RcrH5>T{?fTGm|6s;kkXf44} zG$YO(e!(cJBtLgOQx#PWGvlK;ulN#0pTya@E~%mo9IuKtvQ^QiY*q9bTNQ0$tD?

    VXwqOELIw2h6T?F1CT{{fTH~b z6dfR-=pX?_hX^S8ih!cS1QdNuK+!h@6dfU;=vxAcz9XRMD8W&*KF(ds0P)XFGH^at zMNQpi9E?00$UYbWUHb} zY!qE4py&z#ML!Zybd`Xjp9m?SqLb~N>1V@oK-hI#j@voIHG)BZbkM!5cmmu@Sd&QS1Dim+uyrzm$IbIc|u~kuF zwkj&ZRz*eGs;C%S6%}Wzq7rOXRFbWVO0iK?nt-A*1Qb0?Kv7u&ipmjCRGxsM3Ir5Y zB%r7g0Y#MwD5^q0QB?wpsu5812mwXa2`H*TKv7KsifR#1RGWaJIs_CwNSU zcz4$8Mp1rIR8SS2lh3Z}#(Tw=C~6pQm%FKo9_M&f)QGK$o?xq@#%xv8gsqC6WUHd4 zY*q9WTNO29tD>jbD0+r~qUHn?Jxf4Q3j&H-5>V8NfTGp}6ty9ss4W3S?FcApPe4%z z0*X2kQ1l!DMV$yJ>P$dU7Xpg95>V8QfTHIKDC$l?Q4fNnsD8Y=r2*m}D?galKoyOU zhy6X{z2Zw0^^LcO-cm*VI9?U?XRD$CY*jRnt%?S*RnZGLAfV_&0*Y1*w27^XHnUaH z=WJE9g{_LVvQ^PGwkq1rRz*A5s%R%0MPCq5w2OeEF9|5xO+e8e0*dw$P_&PLqWuIE z9U!3SAOS^(2q^lBfTF_$6n#xV(KiGX9U-9TTLOx{BcSLg0Y%3MC^}9+(Fua1XhXca zm;vHHBHu^bsEVq~PllX~_lhr3bSBI8s^|h+6^@%1bx_!A{PNgVFVPp2`CCDpvWem$U{Jpm*6Nm9q;aMfcO)#7&zan zqMVt`h)D2?FHsbeV80foiefol6~(btQ9N4}C9qYIkFARQY*mzwt%}mKRZ#}ED$2-4 zQGkG=AOS_02q?--Kv5O~in0<=l#PI*>;x1g5>S*xKv6OQML7s4%1J;`3IRpA2q?-; zKv5n7it-Xr^bi3>`3NY=Pe4%tf}ydKv5L}imDP&RE>b5M+hjYPC!u&0*Y!9P*jV6qS^!$)ghqhQ38q{BcP}* z0Y&u)D5_6z6s0D(J+@IaN4}4iriup2cVinQc*U0}dLqHj<5fkCIbIbtVXLAi*{Y~1 zTNORURz=O&s_1F9Dtd;kikh=k(X(t6wIHCVB>_dP2q7l zAfTut0Y%RdP}GTlqRs>qbs?arD*;8_2q=1h)Fp5U%y zfcRtNOGJ%Skyjq}_et=IFHtlg!R{QXiUxALDjLLAMK7>b(Ti+V^b%VY4Q8vNA#7DN zl&y+}u~pG~w3w}m-e#ld9RiA$ z5K#0k0Y&c-P_&eQqGbdWEhnI81p!6x6Hv60fT9lwDEg3qqE!SGttOyo4FN@K2`KuA zfTDE-6s;$q=wkwkJ|UoJ1Hn-=JHh>x0phPK-^QP#ih9al2-%q66C2`GvpIEv0DxLX?_ z{=@S7i_URh6l+Gb&nvz}QM}I{?pH+#9IuLeY*plEtDsGq*$F60B%mmXfTCmqigFN8l#_s>6atEJ5m1zyfTBDE z6y+tL=ph1%@)1y!pMatQ1QZn{pr{Z5MX3ZwQLNAXwgKWlWE(hfKIf5sC;6&ln$Ih~ zL{TxHy(7IUD$en$s03RTm1L`;QfyUJnyre;uvO8+Y*kd2t%}OARZ)31iYgFLRFQz9 zN(2;DCZMPa0Yy~_D5^$4(IW&DRVSdR1_4Di2`H*XKv8W1is}$h^e6#Ej}cH*mw=*r z1QgXLpr`=>MGXlkdYs@WD&lirF+lu1pI3Z|q8EI2<4mgPMUGcRFR@k8V74k6!d68?*{Wz5 zTNMpwtD+HXRWy>Vibkf! zQS=@GMN0`NT1G(8asrB05K#0!0YxhbDEfeaq7MluT17z7Y66PZ5Ky$1fTE8GC|XBA z(Ru=kJ|>{(69S4h5Ky#{fTB+cDEf@xD0;)^{?q{RKNVx(ys3&7iK0zDulN#0TYdJ) zY^rD*$E%|4Y*n;_t%`QCRnZr0RkVw(ioRs4qTOs&w1=&V_Oem5kAR~61QZ=0py(h0 zMTZC|`ig*}!vqw4O+e8%1QZ=1py*oyioPSD=qLe2#|S7oPC(HK0*X!&P;`obqSFKv zeNRBq83KyV5*$UJ``i)PjiO2N-PkRvXo38##&bTe_!31IefC31s^}8OtD?(nRdj`| zihg9PqN{9G^b=bZU1O`F>ugnYgRP2gvQhLi0Y$e6DEftfqT2)%-65dpR|1NDBcSLm z0Y#QyAGV{&MLCioyvfvI!{i5K!bLpeTZXqDTUYq6jF8CZH&WfTCD}qv*WP z{g?sb|JrBZTu?jew%;1QaC_P?SVKQ8EEVIS44qNkCBw0Y$k8D9TMhQ62({@)A(= z5CKK`2q?-=Kv4k#iV6}?REU70R04|92q-E{Kv5BbqbR}eo@#*jC(6SzpWk_;KilB3 zi~7CdOB9v#+aIK;qEZ~Mib}IpQ5m)>dYG+>%Cc2aIkqY)&sIeh*s7=^TNPDeqo^_g zMO6qWs!BjnH3EtrA)u%_0YxH+s5=2gJqRf3NkCCA0*ZPQP}GNjqP_$a^&_CDKLJGp z2q+pza1=H5yOZ)5MZ4wauAfpxTjg&x4)S}&mna(Sw<|rQiiU8!DjLdGMZ?&tXgFIH zjbN*yk!)2oimi%9vsKX;wkmp=jiRvx6pbUGXgmQ$69_1pNI=mf0*WRRP&9>rqNxNF zO(US_6#|N;6HqjRfTEcM6unA7(Q5=0%_5-abpncJ6HqjVfTFns6um)k6uszow>3cg z^UbthQbqZN)SG^<__8uuVRp{Q_Rm_jU=#{(~y zv8*P6J!LJcSs+lsvYrh*UCFXq2j*3=toDI()hw%1Ahm{Nbqn;WWm!D~AJws}z5!QV z%NiJ{Uf;4_3XE%LS;GSR8d=t;K&B>^H8#+^sbx(JENEs~Qv>Ipv8)+^!YwRoR-jKS z%bFWl-^Q}$2i)x~Yf+$PN6T6gn9#|xmIV%Uv8OhMgmbEUhu$N_R2wd!A zS(^ey`&-u5K)->OwKMR^3zoGzU=Oye{ejv;E$gemq~VrzByeb?WgQD-8)I3g0MJAUBO3ZnH#_roHE<#j>uT{G)gkT|xO*&8oVB^3PJ$a0TVx6{_P3 z%0CQK&lQw^+2e6nQ2uF#Ca$3TZvAGip!{<5XI(-0?bfYbLHYH>?Oj3n{j!~0LHPxt z-CRNW4UautLHQMZeO*EM9cu$!LHQ+FFS&y9TaJdgg7Rx>M!ACWdq&2(g7S+ZCc1+1 zH~pu&g7R0jXSjm$cWr06g7TLo=emOOx83Hug7Vju7P*4*_f3|#g7OyzmbrrR6W=Rc zLHUv0)vloY%;h>)P=07`gDWUM^|Z+qlpkB!>I%xw9qe=k>!@vIs%G9%JjH$6P0Nzm{FCyo zqS5KhE6RUUvzj?;M@g5JbwcPR#Y>u(m@lh@{>%D$PI>M6(#$)6RoVQ>y3o9{x{9`w zW|&#Sq}4MIeq2R|NZW4q25BqJkEgnd&XShFWm!J+C)>mF=8DJ3Ic#Wlaq}m8pE%P> zgqoH81sNrEj4<#1u2OLZxp}o2=Hj|a>r1v}H=~S>p_$EiSjQL{Wpz9!7pa_%adKJ8 zJ0n}T`3%WbAvB7cXA7D?*|(Vc8CON;6%w18vnE$dl|nAVy`CMDb5zyLNv`^KOohs2 zIwrXqczh@JocVr0lB=P|_ukB92M1b-{q>k$98+%j0Q0Kmn6XL8kD6obm>vhh!_6Uf z%(=GnpRyVZ)AzkXhi-4b!8~K$+}+)G4i5^wxdYQaJUhrr z%xjK0ZI1ceIVQ~9VI&sQ)4Am|kMG<^M>m->Y0ksTP1Dy5orlqjUP_Sj;M+6g`<7Pn zTDN6gmGkhqc}C7diB!GFT^om`gbpouWME|IJiNPZ@CN51?>v5XLO(0Zuh%^hx{8Kh z%3!Xdft;ND^>{hrpWc`@ooNc$02jOm>c)(g2Uz=*W9=x4%BRHB`(rqM(}o~gtaeb4zXhvz5Z?K z(3@FvY1-v}p|d;r`mn(-T8T+UtX#;|95eaUQ|aUw-_of|+lAgro|#Fen787}vbuwn zxXTnG8h1fs`x>$|cJSB@45UHZbu`q`oLP;XmCb2XSlTl5^%+DhDSj*v?-%{f9WUE|ae z%x4SovgNCl;*`PrrOj)s+ECrs~eC1*9CZpg_b zb~n$&lyX^dMVyP<$Gnr*59@3G-ym#&c|RJWFR$#p+>WU~W~lLCZo8v{c6AD!_|bJs zetaQx6;2p^W%UbI@(6QGCUcsJyUjCly}jfd?D4&NaQkd?b(y1oYS*}R=;*~O_RKNK z+yKYdY~5{cfKujeRSx=)gI3I5@VO)Gm0vDRbFS?(cZS_|-sbjQgHM_Zw9XtAx!wb+C8roBm%E|4+*WdV^U9%fKg2vEXQV7g zEgOC+N9fEKuGFKTImq^1`FU;Q(0RWx`ZIGb67!jlK5{PVIfsNrT(J`6yUlWjhC9vU z+p%~29p@^nGAO@!zcqM<9)ACZdCpu36ShpeIlxM;Xb#G44oa?So+&ENq&Ii_70ok= zb<8tzw)S&+n?Kz(#<_mhPapQPyxZC_VITOC&FR@O%Q_uPu@bMDW8{3DagK2nvl2ai z=WJyy7P?M6zLD3jpK`90E5m-+?Y#GIfA`{O)6D5CEjO~al^kUb3Z1Pu^NgIW#1rOc z4CUOkbWX;O2``elOz2A5TYQZ-bm5j?TRPRbaJMhs*f_vST#~^#H@%!=T*a-#k4=&* zX%Xk<*MmzIgsvpt#HH^$A2QZ_9G*+gi|@BhOWIk5NI48H+IW}~qH#1F6 z?>48mdC{re&ZRqWX!Tw5oVnIl-~R5HbEmUm^4?hn?z85oN6k^moy;>$<+La2X(yYH z(B`9G=(OL|(|*Ef9^aZ*HhpR^8ctWHjyUbyqVJE}GDd*fF&EdbDs3gdZ4PQDr#RVs zaFr`;3P<0Ves#S$#=K8N)jyU!bnCT@Y-8@?jE38{k6-O;CEhWgLC7&%oMY^m!V4A^ z4ZXqHXHUK-cldTppz3kw-DvgJ4^Eg5ib3=7UyixW+j-}U8{^Gun0wG=3*UVCw!5p)1&72ycD{a{PnLjwU=GPMsjx}#+zd5L< zxn!+5X!4bF`_0vAu8yO-R-Jb4Wlz@`-z0QxSTFqYq?H(MzU?5#Om~hkOk<~HleZHy zX~dV+LT~5%=^cxm`_qn%yHzmnT6)M1-psg-n{LQ?GoKKQKXO#wiS3vbt6!`adNbeL z-B8p@d_<3Nnd`yadLG}(uP+XD&f45XmlvAnjDjI2w=Q=s(DZF*$C+!ptsYg>Im(VH z+2HBkp)=Rw(7ZOGx0AQ|M!CPRW1^qfYOc2-dPG}}s6NV;kLGsFz6u3;$PvDGz8zaB zbXA`m`psl>t_4{g3kzh&5+a-f}SXjJa%?irw=zD`YBb?mjYyE{%CvmO`!ynK(yz zGSy7ybNM|LgVQT#k~5IizURoWz^cmT%FlN1scFl8Z@@nHYc8g*D*8;S#rL*#D&g@xm?EPz5i7;!+aQ(CqJ0`mvHMRSG_s% z+*R|(yg;7FLpJ9H_a4dfLqexeU!HIZ^+TudbLbT6%M(ta{v3|F_i2(DE~|k&kyCJ4 zPs$VL@CF=is(JZ8`EQhIE~}wDSz-RTt>;_Mk!LtF4MS(Exy+w`Jaw7>c(HjZ=OD~Vn^VAC$L-A@d0w8%XMSFDhv4dEWt}6V zrxRSEAY=T!ud&m7f|X+4|KxCaDxYWlez=SRPH+yFQS08<_}oCcB=5=QaCw^9&AH{`k<7i+HZ->>sRg;Kk>NNwArTWXK) ztx~%;@6oDF^KRX{_H5ItXPefkt-AN?*0ZaGR&84M>fWZuJuj2jH?LhfwOjWNojdgG z(7TP5+P-V&HmNN-wdtE$s8iQgEjp$4Xy2lHo7C=Yy0q!hqDN|*BF%gB?A5wM*VLX} zyLM{TzD0*FJyP4XYSp|&_s*$>)0!7;UL>tZ;pTUHnh(Ol;}QX6(_(fzqcdUa|3xVbFt>UHYXqj`f$B_1u#&15d@ z-+1c(CkT4C=-EbY3-iwDFlw7tsFl29H*ejhZHr!=dN%LbuUnfQh1!c<1EFHgJ!w#(yg=dv@nGZnI3?siG?T#`Ij$c~U^dpg>Fk4v6OwbOahXAeDNiU#MYv&&my z;jRpJv^1u*xmcy^TrjY*MA=K@_zTcJh$1uUzUG%lAdy& z^tS&G9JoB?^tLExXE&EGBFT>QxMRzzgvrI0(akh_n(B-LbdLzx@y zk5B1;^_1iO>ht2f#~J!p2b8x{BKqrG%!-nR2m;*y+t{`J330Ic$Fo z6Oz-VmXoVME~|6WDLL$n+0Du!$7c99r(_OFE1-v&cfd$bIX#_ZeVXGw&yw@jIXZOB z<@ld;!uNaCJC`%&)ma&HMQMUY9{5CtV>s zC6}Epi#apNwuXQ8>|frba(rYF`B2YEL>9Kwi3;bmBh&13a#wcmTMC`&|H^A1rRYDo z`0`Gb-h8%T&g$>a{^iA&*EAPDy>szHtFWEkx%i=#W{2*{?>Wun|I&*uXUbgs^v z>(7_@p0oNlUHp6R^CCTU?zz(mtNHuK$A5LVQ@)^`lJk#udwc}{%d>m$$Hn`7uMc5( z;G3BDOXq1y`Tyvh`tQ5Tle@0_`|QTK${y^sAMAWT*lR!7IpJpbJKx5GoudbP?fbgz=|OVE(6nz8RK3{e6C-tDh}B2+K&%{}Bdk|LPMw=UwPOdno&N-hhAS&HbN!9Qxnx=~7Z`^JOBwt{|VO>Xmt4?*``6q=NG4 zZRlkGj$0>m!sadf`6-wF&z=3xUY<_QDlfQSETJ#O)UspE7oE(PwfdMZ%9yLje0ea| zTt8u+h~0K#=oxq4CVZ(+9_yN~3CjPI>{w5ZcBvWd1oLl`#-`W_a!nW0Yq*YijlcTZ zjXWOytH*9-&1n|-(_^=C@BSW~&x}*;9Om=#7&$}c>uGjoGh)q^YMz>};>4P-DrJ_h z&&Hao$9Yk*o!2~U%q&Si1x_btH{Q-GPt4JwDJNG%kKo9Ed!o*X=P)PkT!Zpuu>T$> zZ1DcmtKt9T9CMY_`HwDd+5;W+w_WY!ALwj6*qMH?(|(ZG&YO0Bc-x8IzvH$K-5!Qi z=xJ)A;xczZjxu@olXtq`-wk=yKlRW7IJ)2W8~FlC##*+oaAiBAyH6o=lI8)p%l64# zk|(S{W;dWQ9$>)*fQ-q$S< zx;II3?gHd|ru^~F#9Tvi%_Tqid(INN#!~Iv=4nEb?F-$T$+rp$q}kcCo2~a&@_iU{ zZ&g5^n3sm8yn2z)_Z58Rv1$R6B6ukG^EM#7}h@C74)wUCBnw4t)3!U2EdRuVD(;n#J zhAyW0Q1^fR`g1O^&wOV8AfO)XwI2-Ye|80NRGkO99RF{*^nV+VzxRaiy+bIFVrMsZ z)uH=`d+!#)()1DSU){->Z~i>+9qE0&r-$x@lbkzQxz{jf^q#vKpLw&1rkXo>vU5+A zYUeYrmfrkWLFi6iK7UP1vvXuOTkqtvICt`)J1O(h(3Dp%68dB}gSnGWGg-a^FL(0) zLtfk5rWwqQm_zR5GnhMhx!f7doxJlj#{*p?j;^gom$P$*PR;3sb2!(g-pT9rQ&{ih zL(}~Hg1I*3XD>3;wsY2$b0&B4&Z%&!&eQuowfyGPa>~t=YX8NvX?9_G%YVH6{>k~v z;mK%DE6aVJs`F6jKfOxJ-{*Pyi;H&8W&i&#rSq=oSo?qSw&dO8es9wpo`9YIp$BBf z8+m~D+|Cg=j6f9{sY{( zC;$C#;z2*yq&>hr^8Zp#O|qW|w-8=((>N&mPHO8H;Ry$5_0RonN! zo6TgG9s-E;gixg=bW}7Ug={vBY(h~qgpTwoC?bf81r@|D_TIZUcCdG`cg2cgN5oie zeXncg`c5|J{XF;me4h9JfAjfluKE3D&Y3f3zH{cBGh6(drF+Yj+eH_>5-0e!clR6M z^p~5{{^{~CS7+38Ksq?f>CsuVU4S|>C}YsUc0+ZgZaz>q9^ee_>h$O&GQ&;#@1@H4 zAEo+_3ikiV##sY8JA=D9JvvAYdBgqs_@C66^j3Px_8HC)scwB+Vts|zXWLUwUVZk~ zAF|UoB=Pk1m(2z`y>;`L(=)1xWC#E0xtC;F&S1^N%{$YbL;jbf{NFnv1E^%LUh3;Z z52(IA{-f&l2<<4zNk;t7u8O3dt^Pl_E`*7H_k#V8PQ(ARSNH#{0r?*sj$TsURo7D+ zIoSGdudSXbt(@UqoFVewYK2JCwQ_oP`A@R=yUVj(N{k}Nh3n!y(&bB=1x4V$Em*@` zC6884yMAu@+6?HF;f(0v^whVP*B>hTBXS*NIK6{Tr~RGG7S0GMNM?Vhle8%Z%VHm0 z9PnQ+4o(Rz>#sSCNNFQmXZ}q#g9kf(^osuX^K#pvP-^hMX^48tp-6K#L~e81EN56n za)8ADwkn4!8~zDaB}MK@Bc!^gHnf^wYiD@hdX?BJ{g=&&d(Tbx4o9<+8;RuFPI6R| zzu~ff3M01{Era$>v8-$xcz&l*F`nm zebgf#!RaKIfRH-C=_J!?dIB?~{W{}U%&RJ-qF;rrDy3Fl|n)RQd-P{c4 z;4G(qCvh^|UT+4Mg?|1;E{lWhvT&s)9OxV*d1MTAhH9IbA$hubh-mqwh_45WmWB#_ zus&oTs-Nw^8QTBfS{&&XvY%}Gzg9kNk23~4!ziEXVP0wegT;}~07-XnS4VoY8Qf$3 zzS4rBrv07N&`%4C_0v?RH}_6Jp?vn`-_9a6w0Dsv-quXta~#^TsMz~3fWD_+-!N?r zvwfs#pZD-f(|2)G*_%Qj%~>CX#1j1dHPvmPJemuAx?IxeQ@LJUoeuhT0Za4u4+mu` zcXyH`&>@se5@hNWrzQCNDFu1JciSpSpi{zqyEh-O6*UEwl{L|_vAHGD{F>a#(bc5|WmN%IlorI}xuXkes>;i2O3KSd z2Pz9j*JS7B75Q7_RmH0%eO`HKMM*)GY*}3vwe1S?ifSg;ZJDys_e z{WZlEl4*5Wyt<;ITvyaoM8_AD)D)IimgZJ@dz7piZa%7{JTF$0pIen%Q&wF%s-RMj zqrB4FdeHF19ha5Y#H&Ze^D3jdSz&o~S-!j3u;E2+9MPbdl?CyNaw(yg(_q<#y3n#0 zROZGLN>06%#z)tTsxB;){NvHX3j8F0IkIS})~36S*5s(H#DYf4YO2}s2rFE6VS`Qb zDkoG_mCGTQl+;v|N6V@T?2rfA_PG+}vyg)Z)+}+4AiqKKQ6=(0$jU&+WS{CzbZCtc4T9aGhmNKurtgIkUX>rLb9IO@QF6J8&@#?%h zq0~kR=GJ>7Ubqna1Ulw17IuTxss84s-=Pr zZ1!0m&#Q@7l}nu#2#$6Ry}D_TNy7EyAFz9^=0|f!*Tf6T;&~;pn$fw@vij8?T)8D~ z!D`AY3hLKE`l!n2=%T7Jsc^}os!A_)N>(Tt2IK;e58F;(I&VtWu&kOz1KqUZs39|^1F%t)2g6pYU+D9BGJvQ>z*$W^)0qQnX&)D-4MwN>!WW5JZEi)-VvX3VQy zBA?hFEg!vKB%hX!FRgFYU7)qy^J^`8px+iqtKeO$a;Z*TI(P00|Crq?r=UFA@Cu90 z%dcHhTa&kR(Xwe(^7(Fmb7{g$%PaNNXdCP0Inceh=FFcrBV8Ii*Bi|KvSk4*74`D^ zTb$l9{B_o5R~D2Mxb3=DTtP#oytA%Q%ZZH^dKKiAU}(Z#+%`*3l(vrUozP0zfFT-; zn%um+>dM?aYySN56v;huT&^5wRkXA~&X}9WaQ}?wCG4<5&R4uLPngQhtBQ{G?pH$- zZj)TGa$_G|=HAp@EC$IYx{%x8#*o;m)VFro1^%hjMZcJajkL|u094zpQi@r>f$Vft zWv+Awz)AKfXD9J;lB%MqE-8=O1wGu~p_~S<21l__;GXcsLgTcl>GFjSi~QXw+vSCl zoj_9Gyw^7ed3ohEMbd8h38 zm?g=zQU^C^@T=pa+*^H3yh!>r-j>p|(a0t2va~>2W$W;;C--bgi|M5+a5-8!FY)ko z3%PUn1H@9)!!mr-u=5-!dcE9-hg;RrATs0=%D3uSaNdrVIrzcq2)(qCw4%jDR3`g zw|e|5BYQ}LjJSNrAfYedrW+(MHz4S5?|JnAmE@PZt*d`W(Ol$Yd*?=48#|}j+2+Ze z->*q7`mCD#F;zABMc&Q7VNYRb!uHl+l}eLTUFqJV+*YzsY9?Nk(0BuJN$v#gciP=J z;RZZ-P~z=)@L(%#14ez=_o;GDe?rf>L@tJU0NDHJ+|ttA`n^lNNXLxokW1FxY5irL zo$cZ=x~w`qZ^Vdn{U(g2Xxf}WP=Tz2`L?%jif$?hl1g z8A@1>LNdtCcj22=GJpPp?0_2v`h}$|4ernlI?bh$)2Q`5yv?5^?m#6aziFXYxcj6$lXq-%4 z1OK%;ups|>guxGvBJNOqy04rm6}^Eqjc$yC63Cq4@K2^{EU_ni`Sv?SGdq>r?tFH z8wmFeVwsv?mo6e&5XB@aebd7PhMF4r9Yt18vO`5yJ_VV>9WAW;eU|#sk+g+gManpWLz7zYOHJ=M5qh`c z^W3VU3|h8*Zr-_ZoniAQXXG04Gxf)7xue{hR1;S)Y@P-s9RX)^n+w{B56=liOfMuR-_O?~XG7^~Ouo zf>mk5E0c5O)`#?qy!wz)Swem2O;3j=HSuxLDp`|o2W9w{T|WGYgjfDH$s|UbySB81FB2vyBG>My_UqzsXtpY zkl7j?$Wb+9roD{7QEqGZzxnNfeEFdJt#Nv^IzVIJiK7Xbj*aF?b0oKiD!0o0t>Q8a zmT3c<8sHQpd@JGq)_3vcPn*1ShI?{!uty>Fs?HtdVd_m;vxcfGlrfwPcWVkua^v;s zSX*787m3azFdM(mP)n!n-KoI5!aQ#p(4|5r#o3e1j(E3Qcda+0uZxKjqiJ8~>;8UK2_^@eV2u?$?GS>vt_C+@$#&n6VjvhF02L(nm_W_9Q`sRg69vN zt&-h&YInC%Xp1yy-lVgdI!r8Iy2PC&^QYzf{M|db&>$q|$;tiuXCvNJbNy}ZFKw81 zkh~J;G%Qta(2(gC(^$b4@s;D&+T?YBXZD1d(t z@M|uiRn&2&zhV8^k*3NW?zkh7l4xFit3^4y>%+fwyA`kVs`aCVL0N<9vv%iB{24d) z=spypg}~G^Us>%v9?@nV-);(W+8fT-CJd=$uE#wA-e75;gp^#`T)7F_z`-8&xMMMY zoRc+daLuA@Hz#kTLr!EN9b>s7@}*0Z&{txm|BQ-zwl~!A(3InG2X7uHI?YSoiJUZe zsAI=nT^1`VALmsIqbZ%`*L=M}3OS9EIc<5u=RSRDa6YmcDDMDu7)8Q_o=k&joy2oG z#4CBW-4=Do}DutHJ zuK0v$+lC`0dS-4p`%fZ^~D*^~Qcwm^^^6 zo|oGz+V>fR+jJ)Oe%*p4+$U@UuMg)>se0oq-IlQ&&nUCKnP4{?op^N@y#7B$(tAV0 z+n#^@|FtBNh1-1i6_r<#TUwFO8S(00pEhc~^^e_T>_Hpr&D?59xcahnYSk-RgQhIE zLIxV+Wt89GvPmeOR}bFx$?y&!pQ!a|@9kyF-%#Su4 zuGD8C4{rB;0?B|eULBWbYc^p2%Ur5XqweznrT*HM+gC#SkeyXOl$GcH_GnIvrz0(Y z07#u_hr_*Z{@q|(*-`iyKx!_9l1sd%s35n(uTyHmo0d&@6N5MAajPb=U+oS~$H{|f zeKcQg&zdQa_h3M$i}t<0=p9ub<U)L_23DHATn5#0Sd>k( z@difj5>2x=(^^x*=$(uc+Wn%+n4Bu_LX663ub(m;mn#zlw6Oc6)OjhrFMIVFYIevd1cJ*jeh4N+ndT|chchU2&Um^tx%>Q8R+O6 zLjt4o@(xVzrH>hM7tKvCm^*pe)T#2=u!`@Bcb`1)9q_&X^>YaM8vLg6`cwYon{8G$ zZ`v#{JmIVH^_%fWHScy}qmv>hhu5W?;+&d%TIlqoGlQd=XNBfBYuvoss3ryO|1s|W zT>19=K&^fWeIPhM7M-Fat(7JxRUnnns{k?_6_1Ei0?w_|l zS$^ILt*dU9AKO4{R$nJ*U7s(%@8bP=>DMP{UEf!JFeGvPh6JtapO;@#U_DD3Ljk`c zTs!3dfTFimDBxFwt@jVyw142H<=3wg{z3u&KyAH$V5a3~sS^G|fi?l%La9(@)8u>) zN?5PQlDm(t+DA{@N6+3zuh>Vg-bdH}REPXDjI8s2f}m-oN!6#{`d(1cao^vl0Y|UXWhZmzkb(C!*0gkJUy@9z~27kJ(Q`pKFtHXKY?El-4frO(I$fw59Yjk^Z|%PcmP zpF?QeLw*TUqxju4_LS?^^i*jNl6nOK_eyNsI}mtOqipwqMoIUF`R(Ob7*sFODC_lC zA9ec^O4<%qip}Z`Ar*n`ZW0&C{4e=TzGt}grMg`Yxoma2;TmN-{RzCr{R090RlCLmgnPM+8)wN6-)fZYztGt|_bGrQp@*{J)-SzU5Z@S(68f82E)i~X*P<~KG{qY*b*I$2YoGm|h zqft)qdRu>~t-n^IGz4eLkI!hnb<)0RY%M=Jqj8DF?HUIQAkyAx>|t?~#mN>|S-i;N zy%tj>X_72A)tD|n{c2H)?P_gSljIj%Gc{gvM9g&>*_8RyIbsIQGVFcT`#|t=Ejj0^DIU!mRqd0c(}z{i!&_FwYb>g3X8{E zJjvqe7B^Zv-{K_}ud;Z9#oH|2WAOot+blk1@kNWTTYS&rCl+^E{J~)nou&6(xtLuAP)OJhtFpGy+EU;K&F>diNi?tSKTAXijnZ@HQo@nuOi)UNB z(BkD5ud{fo#d|D1Xz?+N&su!h;#(F!wD`HjZ!GSy_?yL~kaxU|ET&p)Yq7J%?iTx6 z9Axo8i@6qyES6gwYw-w+?)^aOced$87FSqYZE>B&GcBHLakIs%EZ%7G4vSkXK4MXS zpg2kP_kzXOEWT?|e~dUu)_-a7dy79?)caGCtas$Tqp_*QRu=WXrGAFRUKR&f9BOf- z#e9n~i~7rgntp=CNfu{VoM&;VMg3`G-F~gb(=2YZc!9;sEM9Bz7K?XVe8A$P7N4=W z-Qt@TKd|_j#jh>?Xz^EzLB}gs#9|AJ`&sN{v75zy7Kd6q)MAmvF%}QAIK|=|i%Tu8 zvbfIT28$P3ywc)L7VozBki{o0zGU$&iyv9sW${Ogzgu+VhNb7Bxy7~?^~adi?`?6Q z#e*#7TP(FW)?$stnHCpXJjUW$i|Z|(Yw=Qx*IB&X;(Zn$wfLOH*DSto@pFscS*)`d zl>U+)M`MevEe^6cTKY%2K5lWA^nX+@wRpPpe^j4u@s<{zzR%)Ia)a0P?^^sp1|O>b zX>q8GvsC9&fu6p~;(G^s`b&#l5B2l_i!*aQz0~5Zd7gg2;+_Ie2MfJ;V38N){f6#- zR~LKn42w^ec=}a~P0Kyq&SK>lPuEzyAnxgFEPfyzE1>Nf9p>qyE#5xS z(+^qPd!(mBHC{Zp){9Y#Crt75Sr(t3=IPfhHlOL~4i>A9@^r1mi{^OxI*U8zdHNfR zJr;U;ki|KRJuN@C=N{LcOTGAr#k!+C?JW1=A;)+zX7R+8p5AEj*;Sr?(_-oxPj|97 zcCDwUSloP)r*E+M@j6d`XR+65o*rUx-g-|TYw_+gJ-yB1uhPLylJgVZ=*65(UM#hE z^0}VgWbyg)J^i-Dw2M65#p3wQo}Om$(n~#klf_Rj_w)}I54g(H!z?bi#?!}Hy!Sd! zKW6dw8$8|UMlX)K*^A{CPr238=URO6c2B=+vGrY^&aimcJ)WLn@$!Fo`WB0yOGjVp z=SPcuAN2GHi;Eui^zjzAZ1waL7XNtE(@h@pV*V3e9Aojcr#yYW#qG~{`hAQ0J@4sE zixXe;^el^4Zuj(U7QcAK(?414|GK9Svbf|;Pp`3f|J$B^%3|O>PdBqz_<^V67T53a z^o15*`PkDRTHOCLPj|O?Niy@L>*rd$Hp$a>S^Qcihjjff z76-}zP4%G`mpAhCNfsY&;_2rsCO7wVON+&+o*rj$Lz<^AvG_)7Pk&;uV_Q%6wm4Y^ zg1Z0t7O(H%>3b}G+sV_vSsa}1>0FD)boKN)i(9*S`UQ(AJw4sZVo7gLPq27rUr#?` z@jZ)QSo~3=BX!)*+pd|$jxw&dxS#nMrn_4_!2BVmM_4?>{HWC7DF--ujeIIqa1&}#bp+cw|JMu zr!4+zF*LwSH_T$O#kj@k7B94TrNy@_er2&smX}Z5;yR1>S$y7NKqd^doUJVuSsY_= zt;O>!US{!5i=SKk&SHy!UVeENODwLj_z#O)Exu+kILJ%a*y2cwV=SI*@hpoMSiHjG z>lVMT*lDnrUk{4|EKaew%;F6e@3i=&#osMDL%e*NTkL9aoW)5N&$0Nl#osMv5B1Vd zvv`5U=Pf1;^VScxIK$#*i_dEmp0-}xU0 zVzI?Ci`5nzwZ$_m zZnSu*#Vak|Xz^By?!27r_Yu?2TikB(eTyGi{LI=;BP`}xbm!wFojV^VvBLcE7AIOv(Ryv~JwMX@>7PcKws7M|wq0x088Xjr zexU#26?2!=PL{Z2kr!vOBp*0i66mj=@Cx*wym)b-zkDXGzncBMrzQXT@sPXaRDD0M zyg6a|e96RJuAMx2(X?e=KAs~#Xr3r*7wN|^ZBO17e|6^Q&yib>Qq(|y{gvx!^2z6f zy-r_LJ6AT!tt{<~%|D-D2?Lwya-A?n+ zzn=2aHsHV8POtZU_nY{u^Ljq@Puqt^^2(8y{yq3mFrZAxG=h81bvxbPVe+C3vKV+; z?%^j$o5UYWW5r0!ul3eopiUYo%}?1Pzv;3}8d(e!SIc$@28%L0Y_Q!Zxsc~jX$k9= z$a3O-o4ytdOtRxppZ%^&NF$4ZTPFkq>AGNl?02o`#Qf&G5pT$@Fjh~+k=Ngpn zMaeH!JpRbln4F0X;U!pb~kTX|LZz^J!X;ZPTUd<=)HnJw%aa-F7vltwkttM)cxw;^YTh8 z-#H1#tM@F*r_XzY0|z1`vM-GZr#&!UwyThYdf(H-(fm^7rTY}y|GWOd zU?7c5#AUIiEGKSvwUqB0KUMv9_N(^Ov-{54O!?K1B&l)&cVha?u20rQ7Cu>*oUx_&$+{isZ^%;MfZyIpn)zg1AVb$C zXWZqkxvh+KIeR}iICuBVqZ`k>F{)eLEbG7Cn%+gWU3lW| zd|7e3E}e0GD_D?UDe;;ame#wV*JI=nS{KLBU?z}K2 z|4)$D$2oid%znJ?>(uk2d3!r2=~C(L9qMe*WqB=-SGv4zmsgg&R;$k2{qQ1<#k((e zV{%v5-8(XAbq`%C-?M*e@$Rh))4P6HxAM{Ze+V`fcZa+*he`6<`gq-rNjqv~DOFzS z54>Eu`=hK$8KJJ_dwPUEtSfm`xB0NH$c?fb&@Jah=M{NT|Idxef6dFyVYa9pla4C> zr1q%TpFjWcXZfDhp-&|L?N@v`A(hfcL*fm$l40?J(W7-c0xc)KIyt?#)yxZmzrR+#XKVb`TG=Ah zYEo+EtCQP{f1&TkcJElMDa-d94TWO+2)PII44es1nFEx+8|8(YOEPqjQ6raDtn9clS#?uVDhCm$>4 z>9HSk#{VjO)Wv^uOERwbx7u;hak245TrI!VK2^7U&2O^~ldI+ZHRXF=jF;4N=kC8K zA>a7qd{KJ-i``nu6{U4l&)908v5d?^ea40fW0(1i#ddFXiHu|_i{s^ga`uo||8n6v z>rHFNen{66o>-U_%P!824lH`AF0f4a^M;MrZp$1s=<5-E*IYRN z{t?|@d2Uv_k2^oR?zYCVopS7zz&nPstqjy`P9`ltYUXpDHpBcyCYt!!HMLGE@J$r`PVEO$GjT<#gGk5;BKG6xs+E=$199EmVckzR8lO6?Y?}W+}}s!>>U+}?Or`v?(7@NzyG0$#MScJp?7+DEs$40 zUa5JzS4!{U>)UlXXYc0h_ObTb8%S+m)IO?LK>Ju@?LB1W><&*^JSjeNyxdn_vHObb zZ`p@+6|2+ao?o&debNDL8!arZQO35v7I525<#l_JyiSqV&4Ja*pz=E4me^g_?Y^(# znLU-Q7Y%�%_OR#Fw}Jsm;=l>t!dVK77zxDdD_Q|^K3xAwdlN9)2{kl-bF|ozP3#TkL zT7aJ5lv>cP%bxMe;BiwbgeG_~}Xi3%b3y z6u0#Y7Z%5gi(}DPk@N=_()uNJEs7l&T_i^tbII0rX{cXr<$j=FZoSe6_~njd92DzQ zG)8J8&uzmrWzT4y}W;Z{d>{y1Mi(V6*{9H6ud;jPqRcJqVon9f`Vy)aYv^lAM zewwPOpQEN~TajUr>PeCc|REyIclmy{2WKd4)XKURKxxJG}T}~M@cm$+s|=8tiPY1raHjS zPgC{ubJSFsevVyZ>3)8i%A<=qZ0F}#zUS7sN0(lAdcCIkIcgi;!q2gpoHM;|Ltez) zPIJ^Y+;O+lT1?7tVnO$uh23^h+r+JHgq22t)p>r;<~sK*>bcVE=_-FO+M-+$yUbb? z-Iw+QE_T=JzLbv({L<&`zIfTp^z&kyv_+V-tu8qzEkYI}wecB!W}YFfKp^|f*uK|4 zy`NKKrxu?UJx#BFzxSi8**$q^`S+`Higw?#cu?_6wNn4`+8)@Jcsz3s za`U;#&EYHe|ES%qGJDPKQ7U=Li0kpxR+IY3U0v=*)Ae4obzGM8KC`9w`CYA^2_12M zRr^HU_S&yz9VvIAX(tNlp|;W4(yA(Ny<)9hI+R}}J=Nz|X>OK4)|v4}?mCaEz@!c_ z$9g_WR#L|P#%({B+ij}@t9Jx~ZvQfP)7tM3X?J?dS$!`~I{u5pX8+M@`;M2^R3CrA z6*Hsfx8C((aztibLV=uhr|d{7Xu2VA^n$UcWwtwM*bz@|eg6KfD{t0oU|Wv#1J>&` zaEa_qk72&wlFg0HX>bfP-EwN%rN=PMUB|Uh>#oxh>$Nf|c7z>+<{C*qA~wOU9jzO^ zTB`k=lhVh=Ds8Rit?A>jQcJJ-C#6?N%U0pu&DldqtRP_z((f3zx`*};yJn6qRYtUL z`1K^Yw^n%M*?3v*#5v=(x?5&u9$Y$DuF#Hl&(Fawo$Zfz2j)@S9v|Z?4n*m zhky6h+}++^pP9yWh4%iwaC?8!^IMSE^V3|OaC?8jCK6Z6YlpnH%4>nVCdn%xJ-)1V z(&Llm+uKFeY3KHMw71t*+#TtW;@Q&c)7gZCUfuAv z&p-ROmx{D6IPu%vjefoHfG^K|Z%FDzy^DHi->~MqE#brOx_IN}ZM|PCc&hZFefx%& z2bP?1V9)DsxhDJB-Kk>^{-|N!P|uc@aHD^0+WMX0AKUuaY5tLE3D>!6I4-Y8X~z{> z?H|{w*l`VxYlXXpeJ%6%<(<>ZmkRNL)|rb+=4+cJEs9HVj@M?{%t@t=zGoCYD`VO` zmz)`~sl|Chk(On0%xihIBw9*uw4yaEY}Otbn_&G^w;#24d#Kv);Y4>QhbsN@Xs=4X zZqvpDrLkCpV=roO?D_7x&3cVj{HkN~v2qm2tuynymRFA=pe=7}cVuoYZ>9FAhT2hR zedO-l*lM7A93EG7Rnk(V>S(NQ^tD=VWT>sb%&xWSRTBG~R;5?0chSz;-o?G6e{EI9 zC$*MQN%!LJ(H>qKn%P#`lr7ntX1$yI`)d`24}DR0R{8hA_TEzGSm)v{(Jr=SQ`_=w z*-~b-FZZ@-7i(ACKHA>42_i(d(TCQTJyh1X?_1s1&)u|e z#tlcGJaa|CjYY>b$~kt|ycfECu>6xxrrh@XmJ9n&Z~FW}AFiLc>h;{7-z<3Z+xt$- zIQEH8OF|=)G5m2O*=cpIu>_~cCvLX67oE0=l*h}?ffH+$el;iz30}(_{%5ltnRYnj0-+^ z;e>Nq{$Bdyx!3-x*XNI^Rih{T`THrK9l8CI>*sZt@kjT`XDq+3|J83iT^h~0!N@)GEGa3;`KFDAaJR0~*ST2!C6(@9D%&R|J5R|2 z%}^J4nw3=EZjx(-C$|?BafYZF2|wFTc9rbtmzgCchbK!$A$iOc2=#51E1QSjPnUmL zt*d0&IZOVfoFq@~!pSRTF*(+}RanHvSc3#KQ4Zw@O$z+tZ`T$<~9kxEzjwjh966pHxPvX*;w9&A8y=59u$Ue z=^O~8hJTSQTZYr5Hqyc`W&{GQ!mrCVt-~qJ!cPthSMeg&S8D)MVIimvNk;&lH4-F^JOnx!<{6z%a_3`vix*-fIL=yCcIP1{A{>D-gfX@_!2ql=fjKTcwY$jlfAzf zX(r2kgOMYpSp9;LZL(GWU}Sb$ATS^p`BO@k6^y(pVM8!dDmA`Qwv?i53P!d_-JKJR z+$7a?ZZMJ}b#z`ZvQw(<{9t5<Ia*7n`;$Y-X+0mY0M+|A&-l9g(7cD zo?nF`1BAP;Ly^9c?we5L8mWwLLy^a&Hogl*4wuvXeJIjZ_V7a}@`UW6BsucDWL=sZ z878GJOOC9PvtOPZnJbx9BuCaseUC|w{3iRWOpdgZDu^dXCdmG(k|Ql7L3MIunJ_vw zInqbY?YQJfp#U~MIdZ;mIUzZ6i)40Ka^%Qn^0xov$apzz6O$v=QZKhBN3NDaw00s( z<%rrik&#jp%bmz^QcEkG$Xdzl7$l0rvQ+EGPUIRX%l2?&e_`w8aO4O{{z^D9Tz30vI3iQBf!D&3_oYa$ha+30Cf*1~ zo)`1YaHP4^*<0brKPCCw;mC_p+$~Ka{eWw*JTBPmjrQJW)4QkMM9k%^K^!RE-JQXz$#Bl3>f z!0649lcXjp9*eAybz>fjd@gxT+7-D|u7KKIk@a$5lXpd?$^NG7iY$_2n7S)+olrMz zS7f;y!}MK|EGhMjU5)ORbqiVs1C6efle|zDhDq8*y3kQ7X|XP}lWmsh!f3&8sV|%wyp{vncsk&oyVXz#NK5uW- zUaBal3lTZ{darAAjgX>W=Fq5zlqXpiy2w$;1HM3`N?{^J7pBUY2D7Bu zqkl+^wbF%baa!xb`*Q8H(FOhNmzKIwjhq5`TcT8p6h288+R85UD<~T6lFCfh1vx%B z3R%!k0H)}|M{?}CRipJnTTmBHl?qSNg{D#rO&4f9S29YT7Yto4y2)AcFH35p=}K9U zUo8!$)XAQkC9B^&+3Deol=IVKR93+0x!=X&B?r5R%nmrcOm-GIFyQny*-7M}fOCM! zjv@yKoIWNyh#V4d`kHJna%jNmXR@8hVF9PV$^AtR4>$u%wiP)d;AENHPh_?fE8BD% z)l#m3rdz9)f((O+^os@*QNliE1g|!KNFlmhz1>-AJ{R?-0`w)l$AgO@~!W`EpFBsFw2Ons!u6 z`9_&eRxRbrGaXVb<;ypnBzlmPufTLrwUn>Ww4CeIWT#uGM$UiBn*}GQdus)t@!Zd^&X&ORmOhd>d(-2Z?8bT(UhL9z$U;kMge)>?ge*2`ge);>ge)~_ge)^@gdAS#26Z)|iHn6HG(MTGJ46qG<>@$uxwVY#Kt=nTC*4Ohd@2 zrXl1s(-3mHX$VG=yAj8bYoy4I$T>hLGz_L&)`}A>;W*S0XHw__gn1+xyO+(0ArXl2Q(-88GX^)UCp`CL6TYe}Vc;`Nkke6gg z;=CJHa+Ht{ot-jna0%IANsW+?Od25{n>0c`F=>Q+YSIY#%%l6VAlokUBwJc8~hTDs+p&>cie zx4bdBy=du{H$k@(E#2~_=>0`Yx4ap;t!U|%H%IR$TE{glFxsdgB}~O=t%ek_B}OYX zq>O18X=+FzTVb?RLrU2iBUKG4W*dwaYDhWv!)UIC6tpcyGc}~7`(rc}Lq|C6Fq)_# zC2fzbG zXrpL3+9+CqHj0ix8%4*WjiQxkqv$v^6s^L5qT?~3Xf*~Dt-*kz6EL7?Ed~^whyg_> zVL;Kz7*Mnh1By<;fTB||py)IVC^{Vjiq>O5(HR&}bS4HAorM8K8!(_~BL)(Z6y1mc zMK@tU(aji8bPEO)-HHK4w_!lh?HEvW2L=?~i2+4-VL;K{7*KQ%1{B?k0Y(47fTArJ z9!2K`Lo)@Cv?A>noo^KFbjM=Bu=1r8Jrs0KmFF}rMGuqSD0&2K6m3NtMcdFu(W7Xi z=rOcW^f=lmdID_}J&87oo(-=_n3B<+3$=Ru?BHhJLXd=LyPUrN!(LFXlz268F-g!D$yr)Z<-Gqh3kIoc@Ni8hM9 zKpRD0qK%?mXrt&Wv{Cdm8j8NbfTC|Ppy)dcDEb})ihjU=qTLu!^dklo?ZJSepD>_k zF9sC-i~&V;7*O;J1{D2@0Y$%IK+*3QQ1nj>DEb2fivGlaqCk>A%J;@-K@2EL!tf~C z5e)4SK+;Z;=c3L>M$zN?d@7U_R=$*?aFWxehfx$Ey;0N%Z4@;|8%0gfMp09=QPd1= z6g5X1MJ>=qQ7YOfYKexTGz=(eg#ksaF`%do1{Cdw0Yz;wplE*#C~AiRMeQ-5r~?KR zb;N+8P8d+s83T&CU_eni1{7srKv7o=D9XfuqHY*a)E$Gis0RiV^~CTfa*{#^3Lt4y zn@1iUy&L zqQPjRXb9RU8j6OZVHi*}90Q6*U_jA<7*KQ&1{58P0YxJ*py&_`C^{4aigGZZC>H~Y zMqxlv9tITUV?a>>1{4)yK+$LnC@R8$q9_Iw6=OhA3g(F_bInu!5L zvoN6OC=4i?jR8e-Fra8I1{BT1fTH;rP_zI8iWXvc6qP51o)kdRUe+;Mg;BIhZ*Pl| z!pfIYv@FTl+1DsKn)F7|agEoqeMH@vc(MHj6XrpKq+9*06Z4|9WL(v)x zC^`WHiq>L4(TNyPbP@&>os0oR>oB0`6bvXj6$6S+!+@gGF`#HY1{9rv0YztGK+#zk zP_zL9iZ)_E(b*VKv&cT49b1|UkJPePbB}t*C{e+_JI_tR9D4Hj4igV6S3M*eq z(ZxwlzX3+kX3`r)m!OTJOVLKrWoV=5aPo#(<)G zFresO3@G{s1{7_Z`U3-s{=|TyK*)ye zP!z;~q9hC`3SmG|G6obm7#>BRB!xZ@K+=Zmu=qQ7YOfYKb`Kv6pk zC~A)ZMIA7ps3Qgxb;5w6&KOYC1p|uGF`y^|1B$w0Kv5(J-`8G#qUdjX*=uff!J95C#+-i~&U>F`(!W3@ADj1B!Am zpePpuibi2TQ62^q5r4&_#oYN09imFL(6pck2MdQ#$(Rj2`Gy!cC z9fmfF4o4eB6VXP|5on|6NHi4HU_j9%3@EC_fTGD5P&5Stil$;f(KHMwnvMZQGccfN zCI%GE!hoWqFra8Q1{BS~fTFn=P&5w%isoZL(EkkhnAeUQ8ZhpAeV;1%9m2KBILY$uu*gj>5Zae(MHiqv{7^%+9+CuHj0i%8%3+p zM$sCyQFH>@C|Zk#q7yNo=p+m%IvE3s)?q-=DHu?6Dh3pth5<#VV?fb*3@ADS1B%YX zfTFW7plAaI6m7(SqO&oeXcGn$or3{I=VCz7c^FW1J_ZzBfB{7pVt5oC9SZFgK+-m8 zhkChDv`Q(uC=^z{l%h*RPTNC`qRU8c6kU!simpH#MOUJYqN~tG(bZ_9=o++9bS>H_ zx(;m=U5|#M8!({gMhqyr2?L65#(<(*FresG3@Ew{1B!0PfTBAvpy*BvD7p&+itfgM zqI)o)=w1vc`UeISZNY$|`!JyBehesj00W91#DJoQFresR43DDCq0qqsNZRlEH1-ms zXpcOFbsh5ZZ%&_>adXrt&Uv{Cdl+9-MkZ4^C=Hj17@8%58f zjiMLOQ1l`O6upE2McXl;=w%EjdIbZDUd4c-*D#>ybqpwa0|ScQ#DJo=Fresd3@CaB z1B%|ofTH&>py+)JDEa^ciax}Eq8%7e^brOWeT)G`pI~?tZ3~4?5J1vS*0)+eY81`X zuJ)&)u=1r8eGzi5$}@_-B)w6z3vCpAg*J-5MjJ)nppBw$(MHjCXrt(Rv{Cc}+9=wM zhN2%aplA;U6#aw&MSC%z=w}Qls>6VyUofEPR}3in4FigP$AF@LVnER!7*O;l1{4L7 zZP*S)K@2EL!hoU>1{5V@K#_w1MJX6i6vlv}2!=<|=b_Nk0!UhpzQ1UvQPf_afHX=D zD_=@cvt;MX0;8xo>5ZZmXrm|WTqHnHW&i4Fih0V?a?43@GY} z0Y$wqpr|(n6diy8MSU=!s4oT-^~3NeYLXmkUMLj3tRL=gn(U4ApViN$_D>EgUrNzH z8SEDsMT1Ch6b(ijMMKa=(NMHeGz@JN4M!VABhW_CfoP-XAhc0*FdB+RVnER$7*KR5 z1{CFBKv6CR6pg}wqC5;J%Ey4B0t_fB#DJpF7*JG%0Yy;^C@RK)q8J7gm0&RS6(z59s@@vyGxbD&omujp6hcKY%VGJmG1Otk;VnES043DDA zl0!WNkhDQ91f0u_qAGpI?4!wH)SZ4~{0Hi~wm zjiMjXM$sO$QS=iUiuPha(a#uAREGgYzhFSouNYAD8wM2pjsZpg#DJndFres93@DP1 zWnU~6oE(IrAO;jAVL(v`1B#L{pvb|1q7)1$3S&S~1Otj1VL(x13@B=X;ZgKua_CM0 zByE#USMM^4M(IeusS{Sdl%iC}d9~UoYDs#dC=G2CwL%+3tvG!%8ffTE5VP}B(niaKLJQ5Os-O2>er3=AmhiUCEL7*Ny=1B$w1Kv542 zDC&s;MZGYfs5b@_9e@EveK4S?F9sC#!+@gx7*I3-1B$XRJc^n-p*jI1?Kpj7S_{V; z>G#yP&t^MeM$rhgQFI{MC^`sj6djBwiYB6sq9f2o(UEAQs0M8mO+p(*wP>SgGTJDbf;Nh#qM>LS1{6)l zfT9@~P&5+*ie_Oz(NP#sG#dko=3qe4Tns3hhXFt0RMLk-IxZDXVUrN!{j`P)#M$t8- zH;S%B8%5WljiT$(M$rvuqv%GoQFIg9D7qPK6y1V0if%@(IXg8v=sx2 zwqZcgqZm;17zPwQj^R;sr4vf65sKDp^K+F^G)kXCCQS=tuVFyZ>lje<1_l(pi2+4#VL;K_ z7*O;M1{A%E0Y&d&K+*dcQ1k%?6n%&RMLRH{=pzg$`WOR>KEZ&ZPcfkAGYlyD90Q7W zVnERs7*O;jhDXs;PH3zEl6H+wG(K$<>2F#)yPUA{r4)VZI7d%0ioPSgQS?39DEa|y z6zxVEML(jAqCIG%=qI#Mv=?m@{fst>>d;X13kDSZiUCExVL;LE7*O<23@G{o1B(8{ zfTBQ(4cnn8hyg`O7*G_#fTCm!C~`2MCRy(~P3lq&JG%ppBya&_+>Pv{AG_ z+9+y=Hj3J#jiL@{qo^a=DC&fUqRtpl)CB{I(lMYY0|Sb>Vn9(Q1{8I}fTHdgP}Bnh zih5!|Q7;TA>Wu+K2Vg)^9}Fn!ivdObFrcVE1{4jzfTAo6D9XlwqJbDtGzi0^sAWp% zV*w=X^>hIzEyWw@pR9MZ!6{+oODP(j;)G@zMI%UW6di~*iVi{>MF*peqLFB$=n%9~ zbST;=%0U}NxoD$k6dH>1FrX+O1BwbTpr{Z7ibi8VQ4t0dMKPeL7z2u87*JG#0Y#-4 zP*jEiMdcV!RDl6SV=$no5(A3j7*JG&0Y%jqP&5_;ipF6;(Rd7xqM<3FUIIwki+U3q zW)!v8Z=RWu5>~#Hq9anA=ut+|k)$_@YS2c}B(zafi#CcTqm7~|XrpK<+9;ZaHj1XB zjiMQ7D4K}@MYAxV=qL;*nvDTPb1igVT+qi8MZjiM9LM$t)Vqv&L`QM3+i6rF-LicUovMW>;SqSMhv(Rwr# zoq+*GXJSCnSr|~X0RxIQVnET^7*Mnc1B%YUfTD9Tpy)gdC^{bliY~x_q6;yg=pqa# zx)=kBHe*21B^Xe2DFzf>h5<#FV?far7*KR2hDXurl+fJ*NZQg&0cVX-v{Dv!GNOsFresu3@Ca41BxERfTD*mpy*)?D0&0~ind}v z(KZYydK3eS9>aj5$1$Mj2@EKD5(A2!!tf}%CMEQ%0Fri}-o&moiZ0bR8$F#8R=$*? z=Tn>x3yq=|NN*Iqh&GB|LK{Wf(MHkBXrt&Av{Cdb+9-MrZ4|wZHj3UrL(!WUQ1liC z6upfBMekrh(YqK>^d1Hjy^jG!A7DVyhZs<_0|Saa!hoWWF`(!Z3@G{(1ByPwfTGVa zplBxs6n%jKMPFh-(Jl-q`U(SzzQ*tnmrq9uyGm1_OiTEZZtb8d&KcqOd zi;be)q&JFwL>onW&_>ZuXrpK^+9>)NZ4}j^jiO)BM$xZmqv$s@6#b3?MgPQrqCYU8 z=uZqN3WROg4n;u>C`!VBq7ViYC1XI5g8@Y;7*G_(fT9Qn6g9$tqQ)3d)C2>Hnqojv zGYlwdjsZn2FrX+E1BzN=cocn?5;|D`Nn5Ya(Y`l|9@CFFriH`Gmr}G}*tu@0QPh_7 zM$!Igqo^I)C~A*3iaMZ;qK;^zs1w>K>Wnsux}c4sbTkxYU_en<3@FOPfTC^~P}Cg* zih5u`QBMpg>V*MCy)mHZ01PPVg8@Z-F`%d)1{C$jfT95yP?UuMMcEioG!O%d24O(a zU<@c4f&oQCF+7S|heOW`AZfSj6j7V7H`2de?`Xs1H%^5wrRbor^Ucvl(ZQrQibkT1 zqC?O|(V=LgCoCeMH4Wf=r9Z@ zIvm5JXhb-awp=JWRNJBhjiN)-MNABbl`o}eQrH=Ej8RledZTDE+9;ZWHj1XAjiPC2 zqi8zXD4Kybie{pXqFHF8=qNN4&BlPDIT%nh7XymsVL;J*3@BQF0YwWjplA^W6fMSp zq9qtmv=jr1mSI5A(HKy)90Q70U_j9^7*KR91{AHtfTH6tplB5a6djKNMXND9ijEA2 z#tR^6ujzBN8lxzhA!1E9tb8d&Cxx9AD~+O)NpBRbLmNe>ppBwa(MHi}Xrt(Kv{AGk zZ4{k>Hj2(f8%1ZKp=bjJ6m7(SqO&oeXcGn$or3{I=VCz7c^FW1J_ZzBfB{7pVnESF z7*KRE1{7_^fTBwMIx(Wk|uEv0(YcM>D)`mlu3Lt6I zb&BXjqo_pZuCEP;l`o~}#<26qDx>Ho(i=rLqm80l&_>a%Xrt&hv{7_B+99R22Qi@NAq*&b7z2tP!GNNz z7*Mng1BxESfTG7Rpy+W7D0%_|ik`%PqNgyR=xGcndIkfEp2hGex;`BGQ~*f}>8#@o zM$rd4U-Vo!tb8d&FNGavjZw6n^hVLkXrt&Av{Cdb+9-MrZ4|wZHj3Ur8%1xTjiR^E zM$y}7D0&A2ir&S5qW3VM=zR<*`TzrpKE!~c9T-sb5e5`}i~&WTU_jBQ7*O;X1{8gc z0Yy78py&$>DEbluigsZ@(N`Ey^fd+)eS-l--(o<~cNiW;FN8w}2q0;jTM0NX8byWr zR{rn9VdYCH+7otSYmK6xNN*JFMH@vwqm80Ev{Cd6+9>)JZ4~{6Hi~{n8%6&_8%2Mh zq3BNxC<;Vu*bYTO3@A#%fT9ov6eVLok%Iw6DHu=`#(<&-1{5{IfTG42P}Bqiikf0T zQ8NrEYK{R#Eij-c6$6S|VnC6+^VR!U0Ti{ufTGqI9!0yup#=g++NAvjoF9#%$CRQr zk+AZm6t#;u8&5Kd+LPWW>VP(iI--rDPH3a3GukNXf;NiM(MC}Q+9>LZHi|OQP}B_r zin?P!Q4b6#>WKkGz5Wk-=K&u@x&HgvER!XbWGM+PgkA)a&{0rRArg|10*ECdgrYQQ zf?~xkA}Wdn5i9oId+)vX-h1!mKF_?*ce6pyIpRIu|2g+wKOcPd_uYACr+nv~cV;)c z04(YYz@mNtEZPcyMg0L-Gys4_0|8i+2f(6y02UPhuxJnfiv|O*Xb1p{h61o?7yyfg z1F&cW0EH;)c!8BxE~q9a=R(^i>9N7CLbI*M!-9ZfciR*}u3W5{OFYO+~$EZHnt zLpFf`7HtGz(U|}&ItzeBX9KY48~_%b3&5iD09dpMfJNs6oJEJV3?CtaL_f_DaSk_& za`h{*E@&B1zto~jTKX5PHj6H$y;*b_*(|!8Y!+QXHjAz#n?+ZV&7!NxX3;fdv*=o~ zS#%v4i>?P?(G37Bx)FdyHvzEdW&jr50>GkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO z-2=d)djVK<9{`K)2Vl_y04#bCfJF}hu;^g`7Ci!R7G2ab{HO>LUEfl~x!5dft8a%q z+A^YksYOq=^gml;7Cl9Kv*>BES@aCqEP9q~7ClEci=HQ&MK6%eq8G_#(Mx2r=w&h% zy#m0ZR{>b`8UTx42Vl_~04#bFfJJWsu;^_77QF+&qIUsU^d10<-UndO2LLSk5P(G= z0kG&}02X}$z@kq9So9eHi#`Wn(H8(L`V!zQdc0-0&2eJUk@~soC(NR#-pKx{Wkmf_ zi@s~=4?V#w`kwY?(GO&^=tr_y^b^@E`k8DN{X#a2ekGelzmd%%FUhV#&7u$)ixL1> z6b4{X3jh}R04z!bU{M5sMJ)kXlmx({WB?YW0I(<(fJJElEJ_DpQ7ZrzWdN`!6M#ig z02Z|dU{MHtNS=5be7Ii0^MLo!7QBSg2)QgNoy#ZL%2Y^L=0a(-zfJIvY zu&6%(iv|F&XdnQK@&H(r55S@V02U1bV9{Uz77YPl(NF*u4Fh1&Z~zvK0ASHb02XZx zz@lvcSTqXYEb5RH-Y9}Z+v(TscT93u`p0BS7@ZVRztp0_B>#?eW>FFC&7xwmSyVzc zi%Q96Q5o4R8bdaV#*)pVad%vR1LtQ2>>jr0bo%r z0E_AXSX2+dqKN=3ngqb2$p9?c5r9Qg09dpW0E>18V9_oBEZP--MGXKf+6{n3QvuGR z?UKUpiXhRDc0b#jMN{NCfA^$_`lS}lNb)16nng2dZx+oWn?0E?CYuxKd&i}nU!(J}xQEeBxHJ^(D* z7l1`809dpi0E_kqV9@~pEIJT?MF#<}=wJXAtps4vApk5o6o5sC0h~qClfwN)kmwtF zS=MM4eX2?wo)l5P)S{!4{PF9}qE)mvi;f|iMXSkX(XnK+XbsscI*x1>9ZxokP9U2_ zYsqHOiDWD~34lfG09bS~0E4cV^-C?fJjp*{gIRP1?aiVq$!5`2WV7gMvRQNu*(|!2Y!+QdHjAz&n?*N}&7vF0 zSacHri*5#B(JcThx)p#$w*j!|b^sRL0l=a=0a$bw0E_MhV9`AQEV>tfMfU-)=zahe zJpjO>2LV|05CDrF24K-604#bGfJKi1u;_7sv*^;K@bw}{bgX{v`ZBZVYPINzq=@>Z z7Cn>Xzp&9PdY1NP(Q{<8=y|eP^a9x|dXa1vy+k&PUM8DGuaM26SIK74Yh)~X9e_n| z0I=vy02aLkz@oPSSo976i{1rb(R%CYwdSkj%*>618EXt+5S=5zm z7Ih<=Mcv6}Q4g|N)RSx$^&*=^y~$=#AF^50myAXI09dpY0E_wquxJ1Piv|L)C=Y-| z`2Z{`0ASG|02U1fV9^i&77Ybp(J%lO4F_P+2mlt11YptD04&-DfJLJKSTq`dMcV?f zXgh$jsB?1oC=nz&R>jFlc31izY1lqFqJF7GCCUCpo6Mq8+M7jXWV2`t*(@4MHjB#1 zX3-90vuGUIEUF-zMdQh4Q6(9RssLD24Zxxa04%BjU{Ngqi|PPaR1d(Si2y8`1i+%n z04&-OfJIXPShN!Wi*^QJ(JlZi+7*CB4FD|K4S+>c0a&y<0E?ypuxL8KSyYr9eq02J zR_aNt*eu#tKN-@P98tg2qS?v*7Z;dCd(hr2+LLS+%^{mbbIE4WJhE9dpKKN_Ae%*d zkGj}0a$bx0E-R>V9^l(EIJb4ESi}dZg-(rbYLeDXO>y? zf&L}YQOObYOD$TR><_=#EIO9pXdT%s zI+=_`rvR|%Q~(y82Ed~A04zEkfJGYsSab#ei#7tV=u7|>odv+6vjJFi4gibJ1z^#6 z04&-Bz@qa3SabmZi!KCU(M13(x)^{(mjJNnQh>8)RdRS|5hOY;UBo%YEUMQ*(q+jJ z^-C?fD%s!fQnTo4+M7k!kjvb)8-PXk0I=v@02bW`z@qyBSo8n@iyj1E(L(?%dKiF3 zj{vafQ2-V_2Ed}n0a)||0E?akV9`?mXVDeO;j=`L=+k;}f2CP;vs(0Yazy=7i=I#R z@4DP9dV%(4(TilW=q0jQ^fK8jdWCEjy-GHVUL%`DuanK9H^^qun`A6{3xGv$1F+~F z02aLqz@qm6SoA&si#`Bg(T4ym`UrqU9|N%H695){3c#Yz09f=n0E@l=V9}QVEcyz7 zMPCE3=owx9?EzTS0f0pv z0a(-tfJL1F&Z3`^!vjT-=;hr-oS)627xd;)PD(`mQj5B!_*K`KMcrv{7WE*TMLo%8 zQ7^Jt)SGM;^&y)@eaU7~KeAc071=E6PsXAF04y2^z@j_=7Ucu5r~rUPg8*1G7=T4X z09Z5>fJMUqSTr1fMI!)MG!lSCTLZ9Y8vquK0$|Z-02XZvz@qH{ShPI=iwXf)R0MDq z<)(xeiy+bN`pJ;4Deg-D2vw>$C8B<*MPpL@6R$Ii#?sy_DkqyoJCMzyab&Zof@~Iz zC!0l;WV5J>Y!+3M&7uipEUE!uQ7r(A>Ht_&55S^{04$mWz@o_jEZPx(MN3jvXgUCk8Ua`|1As*{0nVb*l<0FpK8W-Yl9&HjCzy&7uWlvuH1}S+tOB7A+#1MT^O1 z(Gs#*w3LiRdjqg&832ox1F&cx02b{Fz@ilZEZPr%Mf(G==l}o~9SFdpg8*1`FaV2I z0102Unzz@ozdSadi5i;e(b(UAZwItqYAM+2~E6~I}vM@rbcQ7qa?KX<*SS@fhl z=O2?2QNPrp<5K*tH=9Mr)7~sPfovA7C7VSjlFg!%$Y#+xvRQO8*(^GRY!;nLHj7Rp zW6^p57M%{jq748nIs<@38v$5!CIE}h0$|bE04zEOfJNs5u;@Gh7HtAx(fI%@x&VMh z7Xq;8A^;X$48WpG09bS>0E;dIVA16OEV=^VEIKwNTqc4u7HlT~9WPZXlaQHf%jcgX(PR61;09bS< z0E_MdVA0(GEV>7PMfU=*=so}z-4DQ`2LM>~AOMRV0$|a@04#b0fJKi2u;?)W7CjEY zq9*`Y^dta_o&sRe(*P`b27pD+0-Qxxr-WCDAkjzk&tb1Ii>kF_dM+iReyK$-rTCZJ zZWg^vd$Z^jvRU*h*(`dEY!PAV9}2NEcyxHEP5d&{Gda@A}`hd>Q1vLlxkP< zW>Es!EDDp&q84Pc$S0dciDa`VLN<$9lFgzdvRRZ&#-bDe7Nr8PC=Gx`=>RNh1;C;V z02XBeuqX<^qSgQ`Y6HNcwg4<@2f(5%02XBfu&6x%i#hzMSX2zaq7ncWl>(ea-BZK6 ziXhPy`pq*vQr(sQBzx>2 z1hQFFLpFqC){#bQl1O z4hLY-5dbVY5`aZV0kG(302ZwRV9_xEELsh~qGJKhqPeNz4@HpZY5KYAd1leRdh=*a zYDE1~i`J(4DG!@PC(_<5I*Du+ts|R7CzH*hQ^;n~sbsV0G_qN=o@^GKPBx1+kg@0t z02XZoV9}WXEIJE-MP~!B=o|nRoeRLC^8i@134lfC1F+}<02W;cz@m!)SadM}i!K3R z(WL+^x(t9tmjkfq3IG;e3BaPO09bT2z*%&BYB*m6iJqySyFS4zx=r7jy(TrHeyK$_ zr1}#cHH&Vfy;*b<*(|!5Y!=-@Hj8d0n?<*g&7#}MX3-sFv*=E;S#%c}i|z(s(LDex zx)*>&_W`izegGCd0KlRL0a)}90E-?5V9_H0EP51xMUMfn=y3oRJpsU?CjnUW6ab5! z24K-M04#bIfJM&%u;_UJ7QFy)7G0MbUMhk_d+OJOTyGXVm@MJN)QI|}7QLG4uY24q zdX4sG(d%Th=nb-2^d{LXdW&opy-hZY-XWVs?~=`;_sC|^`(!No0Dwgw0K02X}= zz@kq8SoA3Xi#`Kj(dPgx`T~GOUjne`D*zUK4Zxyr09f=b0E@l@VA1ygEcyX}MLzX%v+PV--p``K-Z@;$#r zTJtM?pKKN-lFgzB*(_>FHj9$TW>GTPEJ`7pMX6-7D2RNh1;C;V02XBeuqX<^ zqSgQ`Y6HNcwg4<@2f(5%02XBfu&6x%i#hJD%gh0?+aPl-hb>PM{;(%d!LtTqyQq(#&(wWv>;-~Ac0s4wlUFX~4&i?$-0 zMg7TU(EzepG>~i-<&n*ze6m?oKsJj8k+Enn0E>nIuxKa%i-rNPXgC0iMgXvABmj%H z24K-P04y2>z@pIrEZP=;McV34GzNf0V*$>h zUTNX6B1m+tUflOKi@s2c%F`n1ms&JF&7b|8SyV}Tv#5$}7FCnYq6uWPsD^A7)soGk zI)6s0KlT%09Z5?fJM6l zuxJ_pi>3pxs1blgGXPjL6M#jt09Z5|fJJ)%uxL*J7R>=*(OiJDXk1!&wFnZuL_c?3 zVHS1JLDIami29`#Ell$-d%-MPM0>MnG1)9yLN<$*lFg#M$!5_qvRSm8Y!>Z9HjDNp zn?)&W zVA0tCEIJ2(Mdt#r=sW-xZ31A?`2Z}s0Dwgo0J02W;gz@ke4Sac}>i!K9T(d7Uv zx&nYjR|2r;DgYK;4Zxyn09bS_0E?~zIEzk93wL-~Eb6A;y?>Hf^u1bieOg5QQj2a* z^S61`EV_mEX3?!=v*~2*9F;09f=e0E-?0V9}!hEP4!pMUMlp=m`K8Jqf^~rvO;=Gysd90btRy04#bA zfJM&(u;>K<7QG0-qL%m-vF@aTL2b)2f(850a)|{0E>PEV9`$iEczLMMZW;B z=vM$1{RY4yFWoN8u_y#^7QL1hK2HRRX6VNoUpI@^bd!*f9#Oy4qQrFnzBkRH2<^?H zmSnRiiEI`nlg*+OvRRZ$HjC28W>GrXENVqIi!#VqlnKD1C;*FE1F)zK0E^lJu&5mX zi?RS%lnub5_5dvE0KlS-04(YRz@p9oEXo03Q5OIfD6u&5^h zi+TZ^MJ>|9AB!N-4f??}KiysFAE#dx+B-d>eyK%UrTb~`m__|*Zx#(8n?(c3W>Fs5 zEXpUFMFnKDXb{;f8ca5ehLFvop=2x?2Ed}>04y2-z@m`=EZQ1?McV+dXcPd8Mgy>D zTL2bq2f(830a#QBz@j1m78L`qs04sTr2s4{17Oh@02Yk}U{N^$i*^8D(Kvv!sBe0B zkO&g}P~ST1XBI8gw?it@BkGr0RGseEzGoIqpuJgCLpF8pVXeR&`?F_)8T>x0LD*%fc09dpe0E?yquxNJx7EJ?S(R2V7H3G0` z1^|m@0pY$55S@Y0B2EUdU%-#65Ws^;#8SM zb@~p-Ug;6_OD$TG?w|63S+tb)X3^ecvuGLFELu)Bi}oR#Mf;M?q7`JbXg{)9v_IJ_ zI)IEt2LiC@AOIE}48Wq504zELfJKJ_u;?%V799@2q9XuUbR+%au7M(_WvuHipEIOTR7HuG#MQ4!BqK#y;=uEO%bQakxI-6`3okPZ=a{*X% z9sr9r0kG(N02W;Uz@iHQSacBpi!KIW(Io&Zx)gv#mjSToasU=x0l=aw0a$bu0E?~$ zV9_-IEV>qeMb`na=z0Ja-2lL%8v)Lulhea3J{F5!*3Vs^ViuJoNVq9IqJF7Gx25|% zKQ)VPr@dKp2iYvTlWZ2CYwd~kj14C071=DxAe%**WV0wrHj7%5v8W9Ii`oLPs2u={vH)0=4Zx!I04(YN zz@m--Eb0WnqRs#;$^l?e7XTLJ0T7L5d8(bfPg+6I6{qX1Ym8h}OH0*fc1z=Gb0E@-|uxKm*i^>65v;zQ(#sRRX0)R#10a#QCa2EA%74Gzn zSkzA~8ekU9)6sQRtBCrg7S*=$M}KD))zRK8swbO86Uk=LB(hmFnQRvANH&Y6kj<^djha%4gibh0r~799$}qQd}KbT|NujsRfMkpL_@3V=mN1F&cn0E>`?Sdz(eSsYR!>il|>| z(dn)H2Yxb(HqhQII)iK$Z6upTXOhjLv&d%A*<`cm9I{z-F4-(Pk8BogB4g3{04%xy zfJGMqu;?NH7F`U$qDuf+bSVIfE(2iER02W;hz@lpaSadA_i>?D; z(e(fZ2Z}s$cYpaO*r54@U%5U|n zS#%fe&7!->X3;%lv*=#3S#%%SEV`d;7Ck^ViykDKMGuk9qKC;?^aucp9tB|0V*o6A z9Dqen0I=vu02Vz3z@n!CSo914i=G8w(Q^PSdLDp9F95LUMF1AP1i+$~0a)}30E=D) zV9{#;EP5S)MQ;GG=uLpL==N6OAtFfhH+>)N4zs9EKN<2?tBCrg7QNTXulIBY^118x zX>S&NKsJj$B%4JakPGV9_rCEcz9IMZW>C$jh+Hb}R}3uqXk5MPUFI zwE$p|55S^C02W06&Z2i(h4&FbqBnOCao#nHe$mrg%Z!Nnr52@T_@^b9MQOA*i_*zv zQ7f`pltDI&GRbC9lx!BYCYwcV$YxPnvRTxQj73=hEXoF8QF{OubpT*dM*tRe0$@>R z02bu{u&4_Fi*f;2)D?h5-2hnB9e_nW09e!$fJMCkSkxPUMSTER)E9t7{Qy|B6#$F+ z1Dr+48R6SSkm$EM6iUf(SNgZMnFxe~`LN<$rlFg!F zWV2{E*(@4CHj74*&7!TzX3;ieEE)yCqR{{>+7^IC+X1j>djJ*{0ASHt84>kMEt;6&_l}rFlW1=iO(vT~JCe zN;Zoc$Y#-QWGtErz@ps&STqfQMbiOT)Cj<$82~Jr3BaOR04$mfz@j|>ShObqi{=2Z zXf6PY<^iy1J^+gr0I+B;02VC-V9_D~7A*!~(Gma_Ed@A>>N3I=B1rT&{q%mlS=3K2 z`}fX>s9$Q)z8U`9B(rD*?aiY7$Y#<0WV7f1vRQN>*(^GUY!)3%Hj7r0&7wodX3?Q! zEIJH;MTY~h=m-E79SOjqqX1ZRGyscM0kG&802ZwVV9~JvELsD=qT>KqbUXlyP5@xh zS^yTE2*9F~09dpRfJG+*u;>&37M%*fqSFA*qU9Ok<3*5YZC4RzAG7FbwP<}tMEz2W zHfH!&rISWMb`tc=mr25-3Y*< zn*dmJGXRTj0btRs04%x3Qv*>=ZS@ZzeEP9Y^7Cl5ZiykJMMURlpqDRSQ(PLyRdK`d7PXMs!NdOi- z1;C=G0a)}50E?alV9|2`EP5V*MK1ub=tTe)y#&CbmjPJx3IK~<1z^!@04#bPfJJWr zu;@(y7QF?)qPGE9^bWvTbXP_=CtWN`(!XlF+bp_C-;I4YBcgt(MIUDP+hv$VAJN_{ z`j~7MeL^;iJ|&w)pOMX?&&g)d7i6>OOR`z?71=EMnv6x?0I=v=02X}*z@qN~So8w` zi+%)P(N6#@`Wb*lzW}i4R{$3M2EZaO(=OYwCJ zwI-WIZOCR(Te4Zyj%*fXkGkN02Xxx zU{N;!7Ig<;Q4atX^#ov1F8~(x24GPi02cKHU{OB+7HtKyp5%o(g8j|Th)W$3tN_(?t7}+cuPBx21kj7VVhnXJ(m2Q)q7%?L;<-)(M$jq%>rQ2YycMR0l=a?0a!E#fJJiwSTqlSMe_kzv;crb zdjYU$ApnaO0kCK>0E?CYuxKd&i}nU!(J}xQEeAM@CS`_)i6GJIbaXx0EE?WT!akW1 z^-C?4uC}` z1F+~602ZAJz@pOtShOC1MW+L>Xam4mv?4RSLIjC!rFR|oGmCOHoRJw(ztp0$GyT&$ znnmZ(-YhzoY!;nIHj6fq&7$+kX3+&?v*<#yS#%NEEV`I%7F|NdqDui-bQu7PE(c)I z6#y){5`aZl0kG(502W;Xz@lpbSacl#i>?P?(G37Bx)FdyHvzEdW&jr50>GkM0a$b! z0E=!1V9^}_EV>hbMRx(5MQ3J)?-W6zlTt;Tv&^DP)S|mHBkGr0bbqG*R%f&50ot2I z50cHIhsb8p!(_AQ5wcnIDA_D}jBFM?PBx34Ae%)`lCkJ102VzBz@ldWSoACai=G2u z(enT-dI5k%F9NXWB>)z^48WpS09f=Y0E=D&VA1OUEP4ZgMQ;MI=q&&iy$!&kcK}%Q zE&z+(17Okn0B6y?ncV$o>*8<6|Vq6_t}8b8R4s9$Q)Cz*cVT(js?+M7k6kJ|vFLjM7X1Lgq8|ZR^b-J!egDHjA>z zW>GfTENV|Si#m|aqK;&pM2Y^Lg09cd@z@n}IEb0cpqV51J>H)x_o&YTB z1;C=-04(YQz@okYEb0fqqOAZ})E|IF0{~bw5P(H_04&M}U{L`8iv|IlMH$iXS`j3A ztX`I7M%|VE29d`f9F3@7YSHkhe@zdwXaw!eqLE~?Xlt@rv<=xT8bvmXMw88=ZOLZQ zc4V_?d$L(nNXDWf02UPku&4xpMWp~NDg$8A7yuTH1z=G*0E>12V9_`L7F7VSXgmOm zDgjtj1;CrjpH~-N|OrG_qMVoop60lFgzSWGtEq zz@k|IESe3#qCEguv?l0kCL30E-p?uxKv;7A*u|(INmAEe2rG5� z1z^$M04!Ptz@p^>iw3&5fi0a$br0E^ZEu;^p}7M%jXqEi7_bQ%DQ)&sEU zbO07@0ASG>04&-Fz@jq&&Y}aN;Ta-G^c;!)fo4&nDs@&gqJDYpyac~{(iQzfUe;(C zb$eM2@^!Q=vh-b&mRV=Zi7++m9vM_+WW6V!1Zb1Bm3${;cGg}phfZ17$p4()bpydN=JBJUDnZCd*0-%Cq{YR&RJR8dERbWyA*of^sKXsJ#SXl z2c@1jCo6BP=Pk%uvV-R>&bq0>^Oj|WsyuH+)|d&NcVN~rwVroK)>HMKcSKhE$)2|= zt6_@gt;srfXU|)k_0g`LcXC$2RL@(Vwf8j7+n9ArqvxHI6`tjJ=Vz7g;dvKl9XrSK zF3);qp66Yi)p0M+yFP2`BG0=yYts_XyFKfZy*=;ltik(u-u+q2S9spTS-0))d5>rL z2YKGpS>slE-t$?<9qM^6XFYeg=e?fQ`6$nOJ8Rl1&wD@Xg4Le)an@&RJn!?Yp(l9W z*IE0X=y~5~-LcN|e$I}ZD%(GlJ$}9HfKc`c8)OfJvR~LJyC9U^7lg9)8y**jvh^$amW8tQJJwc& zvh_={4h&`Mw;UZ3%GR%`IUYUghqCpJUUk_#L-LJPp z*?Rlp{ZO`Ee|{Xw)(eQwL)kh4{5q7ar||DX+1dyH9P*MI?FyDD0`-pvcr_=Jv&)3uj3x6$~G$7UGlE-uhX+~X&oAxeyp@PRr0~| zuk#`4!iELR>wL6^;TCR`BRn)BT|Ab_*2x-$M%pu*awKeRp{|33Z7l4hVU&dhx=N!h z%++<-)`dwD^RGpZ4(>d?`v~QQt zgv89l-~4Lj0bN2hernDq$xFI~Y7;ZpestS&E4-ZRteO1OK+4H%BhnF`iiIUil-iV<}K1jUh#z6*8j93X#Mgl zcYN+z7hkdS5-(?pG`d6@UE&%gEcLvcyXC_PI-@t4(U&iO@XUU}jIQ|Xw~J&YWYG`Y zaKe;e(VxBdgje_Ta%T8$F}}4Kwfw@%Stjg8nNi=oU>o?UMT0*cDf97Dk2~*SDd z=CT(rJ#}9%_f%;UY|~%mfv&;BLF1Z)<+6Fw<=mp|duBM|wj=X{wQ5o6FO>Nu>@9n| zHes1`Wl@>-4VgCQV0oZRF*M&c#SwJ{J>8~Qy7%_M%3OEjl^@CqiVa_!_QbjayqxLD zZYjpPHlbl&&Qd}8+AEmN{D%gY1uOIGn~$C6R_5l&1I58?9{uX|vk&lc_mMWiCY>(F zhOX5qu5rS?vNB7B1uMu54|spdp22d>?tfZBuyM9+e{^Orzk{A#eTdFantUp=$=zQb z{3H)@&axSQ88_prZN|L{%>Q*4od26jpWT(I*$l?S?Q9&oL7 zhvxih>^tUo`*lBGB`YyOT$8yaW`6kH(`soU@S;XG;Mr(QUAza(kmrye$Id8wE4rnT6G7O$<^Sr^hz zoss(RHbIM@uRmpA@FH*BckEC5csV)<)E7CPCT~}SM+fV5)LkE6 z-gu_l=D$94guc$x)@FCtM)u07n;v(rue|22^PRTs&$`OJ&hUAui@mO&TbtlD7Ct$A zw_v%hziq>ruB$xssc){(7x7b99ACPNY_Ltao~Qp36T*qzeCZ?fUt-U2a<>}k|Mg$u z4+)9gu8~RfUt(A$yGKrr`Y$nE!azB@>c7MvWwH`Ef$P7-GSA^=n#P=mEl^&^*=Fdw8K#6n<*l_zYFC+Eo-|2oB`>aXPH!DbNoksAt28g%k|jw=NlQsh z86lHrWHp;AQ>Kbr-l#=;wbnLEiTavtY?i^ZO|xukv$Uz&Nh7~$IkM7ZLG_ihg9oy1 z?T5s@=63Bz$uOS&-iC%UfrLqKVsQuPbV=uiMd&Ymkt2U6E|_PVqA_);XT( z=FBNE7wlk!iV(4vD*_eAryF6|o3VS*OsFd>-3v%wrDXkiW$&iJD_G%;~q zUbIHbn=%LvdG%VDZB5*4Yjn0h%0FGOnltp#V%Z4NLdzQY=bq3<_q!*wupl-6U_sUd z3s9@&R{0n97EC`wAFv3uaf?tJzhdWe5{!5Typcj(Sr~Z?LcGW$* zSW1GIAH1wwBzV3jSB#y`(1#^K9Hj9=IsCqte>$aB9XUn3WG}Q-p48yU2uMIE02*=} za8qoM^XmKZPn&Dib8pami8R;nxdWk)0uAZnRcs1fH(h&e?v`3FHD&2y|5eKx>a$u8 zkzr!Un;74S{iT!WF1k3_MH6W*y_B@p|D<2E|8yJ1{}-R%8L9i~Nqx=GPw8p0Ib$1k z;K00vQ}bplT9CJB;k3Mk4U48VHY`{;e{tiq#f{VRrY&5)VDWqf(;BBQS=hKJ?m3-a zrXHEMVBze!vlq`^+UVuYnm@NOZ|a=JWqAYV%%3)OPTrzfQx`VoEo_|ExM=F4yv9Kd zixw}LK6`%N;`#IEOq(@z_Pj-TGp9{!n7VLoUO|4t;D$l@g9;i7@)ZscIAGrVd5r@a zr|v#`KtcY%!2|T^f%0^-r}Adcn>J_3^v1loQ>V?EJ@0>fF%~Uf6u%{A&dMuXIDN_N zdGm|sFKiqT+ZM|fFAO$`+alEq=kFogd{JKQf~gDlEL$?Kp-$FiX7!vUiyCSQhm9Y~ zZjzP#8|VJNBf-+CiyL)c$Z6DRG^1ePG(CD7rZ>)*x@6AchQ-SlG%gxAOWhR_rq7)PVd2H7aniUTf8P9x|!TVKi{PyPtY4~~WK;E?aP z{zw1$p~Udakl!}kexM%;&&<_Fxqi!mzMr_WA59GDgFL@=V(TvUKxQUDo{_q(m(U{A z)=$yW%I~U0co4PSAit-?*12&lN7K^ps&fchbpIzah$go7Tj%**`ujb5`>n&v-MpfS zZE|d;09V_F{3M-cw%^JvQ%_r_APx+kOpxX3D>%UxAR)Ybpr56ncd!Zxi3-{(a7(BY z_6(=yx>+ZV{}=P_{SW4y8}L7vce`-PsBZb)^12QQULl+qUO3Q~yQDJ2a;pcwS}Po|8KgNA{h!LQ#kJ+xJdciFodR9*&YLZ{?vHR@?0=mCRl?!9wqe2< zZeNB)#pYY;e>Zpihx60@C;Mi$b0h5BkX@9h2aFh**RxxAscJvY9H(-$Sncgcn>^N| zNRJ6Syxd_GYmnH+j|QU4Q4rMwuq(&UXgMUcZJwVawWYY37)~4Iw^L(e6}FKq)3%eP zDi~HUD7>d^E_t2c>7ZtH6d>D5r~lKH8Ek30`03mFJ-Ykt!u#kF$MZj0j(pkT(!JQB ztlDe$5=3o2$ZsPtI@wR^=10d0=-N7uMRc`CH@{tuJkjl6%}BOGet%mc=~|k$m2Ask z6Ls@@Xbl#j`#)KtrY)>1#M0#drPgxP{5^}c?G`Q0mQB57s~SIbLd`$h)o#OX*|Pk# z&A(-@@&CruY)R_hxz@Y}_3wPGEt@w>MBS3sJ@WrVR}^${xvqQB9=k_ek1hR)^p{

    F7X4Xnm{;4Wdpy$k&O}61VmHXtnO` ze{$+^xROO}^6Ggy|tZ!7;DTVTs}a{d-=}{U!OXmcU!kt{%tY`UUd5# zgxj)}{LkFn-T%!STaRh&Z~o4;-LiRa+0^0mr>SG<#zv{q)*U0mA^3Jkh zV|}FdVE^J!`HQW(<>mN&diWi54DWhr-J|ST>J~1DoUXQX@we<8w}oBxmh7@En)Q}U zoR|M^-_!+LnIvuV^TPWK%q!?;`z~A3AM8eU=O5M91AgB?rVFS$+xF@1b}Oyze$hW3 zUt~+~&~67mv!F<>5%<;w>gu--`I%yKLSjPi4u1FGQFz%Xzr8+kV-~qVqaoMNOzbu@ zubo^Lru&&a{5G9}|LYp|(tanei#+0(3>K*?Yao~3TYT*NP0EgvC1F@*3oFYSEZ>gS zdye+q5GK#>CEF`Q*IO_CW+YQpm z^8QjQzkj};lcU@GPrStc^%DojYX2U7j&_Tg(jDr3ncvqf+AVV5Q>O3g50HKOk7nDY z*~{24*7o**_`N+a*xP#7HFKQbrCgUSFIdXI=FES{4*kztc-dF~bqB?N@iHe2Z1Z2# z{bb6>x4#~O!I9bhpLffD-y!z@kDB$N#&V^UvwF1sn7Cd+g7=#J|gq zzwfp3^k#p455JrC)NSSTst4`w>z2r!*ECQ0G~e&%wfSpo*}V0Rd9b|y_Ib;lb9WTC zEeLL$=k>LP5AK}*>-C6VuhxEBiT!m3GTi9aMIVfoZ7X-w+sc_KU;5-f*DdDC?#S7} zZ(lG(?hwlTa$Ul%A$M;)F`;J%e=F%xJ$-GZPH{?aJnMGQ6F^tp4%_Ghw$o_8ySX+{YId&Q zJ~(U09q&M(AwB$FDrI|-QtyKQzIHWkM@JWTZW*FQrVpYvAEc8xDT8^6IPGOC{_#9{ zEuQ}~^Oo6-cI}4b`@M1`{;5`fYT{sRa^1=dlsU^r(XHBEUQb_0w`#9#^Z^S#+V5=} zYmn4Vx$?ONed|C@%w7Ev-TZ!?1#}J0)16sNeal5o$|G#U1yS1#(#i7vQY(K%zTYoL z=3!gnpT5NZ^%Dng9gOJV_fwxci_bbt`hDG^-IC{TCDV8HN6J2Rv!!{{?6+$6GIk+g zyJBSg-X0k2Z5`-$9_MdWuFEC^)4%M@f5;B~Yr_AX3orX>iw}x~;Wje-A3KKr%2NMN zANT(e%lvm7_ko^U+KC5!_@6iL@7j3(<>!*WYqR{h9w#_G=LVmTkiXgKEF%Hwp9^F( z{BJ(7{6)dG;CwHq79AdRl9k|`Mg8}68-KXD^8C(nTI;VbECZ*01M~r>%h5ik%VBaJ z%+2+?%D`#hOg~T3sBXS&=&sz{(?0-`0n;cug$6NK{1Tt(cP$(>)7K9G%U?NU>EA5a8T^m`TtdcqZzm@V3e61GLxy@= z=>gyTq`%n^Pd-ij?oxRT{jiCAzO18u7S|g5@h5oXV<=B1NCUl-CZ9v;^7|W}n|=O7 zhV(}zN&_8}4(aCi)-kKS!XFRU<<8Oh`%448G>|(h-SyJJ8vOA!N~b{ydGcqSWwq4} zr8PAT<&_f)E6Ph63TwvHk1wsP^LS!>X>D!cn9_#2s;Y*Hs>(55P3f41g2Ljlu_=n{ zYU`zaan<^Wv2C&we{82 zRr*9jb@}AdiiWbPn(>8o?iFQL%_lFas45=UP*PY|*iczNzNoZD*Q2V&O+9!-{0moB zHPqG@)fU&3>ttnB^_3;TWWz^{4eH2di&;}zTU{kf=;ky;reRy?vX|Br*2XP4+iiU9 zn1-VIvND-}ZTXbaSd-taS^0R~n!z->C5!Uo7qq;xp`I5WX$x0S)@+jEnjNd_s$`Wb zDjKS*$}8(iZIuVv^o3I8?<5BgYFHesK}oabMHTW#k~L+)ZYZrRlvv_bmDM&Bmblpr z4W`y5D~nt4(z>y1--hb3J2uF^9xr>jxUjCgs?u$zk+Fsa#c?gmYbG=liDM<@weH2( zmTs0hvtYM1RFqeai*2<@c%j)mGI8OHd+K#};5{@cOKUO;=VR z$45hLRasd>vxy5vHk-P*u(F}9rm(Vhe0g0k=bF;Ok{yGUDQYHcO>LpfDA?7qflX{) zv#PeZp|-9{wrQ#8X#3D@n`SeKJDy@I92~19<%MG!YD+6?iz~)8j43RyY#l9^75Lp!iLh~;)a5va_bg~n;p7Mt5;QDS6yG% zFtMtlPL8+OEI4|!6VmQVySliexukSrxh#B9eXZLoaxBI7UvBHD{IXNDGtdnb*Su!3 zbO8-j6H9B#Dyk-J{-QONV`AN`cvv_-HbHr{bbh8pwRAu6{co^JwPH@JQymoBU`25o zNB3CMOS|JE?rGUGvPl|BCl{BNmc%WxZ4l{^>k6eu8CSYvLs?~M>|?K&q2WvHfR34nYq&I1#AefS0E2q4fVaM={%?B zjo5S6ao3bqlm?xE6;VGB_RDQZ^HbUZbI~ zxVXNiu-N***z$~(6Xm2rS<$-k@ujlcf_aRH?e^lh7p#_@R$EgnVigwGl}~ghtzmKJ zN)B5&yN{_1&g_93gJlwZP}uD35Z|>lb$JD)v0bSTV~c5Khz!yT)Z6(|7PDyrdC{Vp zLKzd7Q~HXscjAvJ*;Mq`6;-u%RF8>1&er48tm{zvuDn0oSrM+2(d8saw>RL znaoZkY3k#f`h?=*s)n)BdBqyAZN^uXxTTk2L+r`o(u#`uiozPPeoT3-2(ITkRs^f) z1l%&_OY>kAoAvtjwMD`CzM*!k3~t<%(!bHu#l7VCQt6s))Wa+3{0gMobnQw5kCx1f zUwxfIP9L!aFBw!~=hT|g$`Y|Pu7{58;NoEPWX{M|oHw(vp>f{y*;D5==&=-=S$Rc8 z>6pR_JLF`TP$Hc`(|I!RJ$6cq+sg$bni+4ZjFmaXjnYb3E!nx7IZ>|t;buKi{3t}a zg5VGiHc#xxC>YvoMjSrut+)X}Gjaa#eAnbnMM+iAv&POQwvXK|kxs^TWkG?RwdAZH z+khPF`3)r#>KaPMx)Xo%QNpme>8+m{FFjFxO>lk+I>$2EAhl!Tx@Fw0DBMxUoOULT zJNXV79DgbvGQ^g)nVK=jH`~(e^|(=Ug&YG-`<+)GQ#gKnVbiONi83f-bI6ezyr?^x ztyiy=19$3T`DPefo7t!6C99WXO@K-Hk!0rK4IN445&uanYiw zGaCoYX`DB6@vPDLg51G2K$VfCBb&vu=g%9kNWOhV>LOv&<$M*(!HNxUCSo9gJImm9HH!cfiF}PW;+SCQ; zaTIg0NohIlNas)|LsmVX$0lI62G>?ids_~+Vi_G270Lyd^{&AoK$kqc=@5{!zFVc{ z7dCp?p@W8Uxvp@-3%A~Zjk7D}&tFjB1!d6hmZjO5y4eVNyv(VnYVz+|6j#WJKu)dN zQR&Ob;8T^1jY|vi-JrB!c&rze9T1yM(^k@vT!U>Yw^nkx3?9htbwIkXxSlK6&rMf& zn+@Ep6KsCY7$S3OY|!tsXd2yS4JYKTU&5 zJ?%7&#^h4h4okgs4>rC$Fr?Sk0g};l@W5Si1}Hx^m3u^A8aFHq2D5UFWFxWydUaW~ zxNQ^HKu4LurVj^Mx*V{59yeZjG89Dk!hRl-O1W#$RCnlS{d>^0KPt*O^TYl@t~S-%QkOARFs#_=|EKJ+bMWKV#&A#SLX*PXyBHaJ8yZ zyM*BUT<}kywZliQ;7p*V3%BOiW9nc`cNV0!y1c=z!*zdf9atE5l$K7LzG!OfOfj)> z;p`c+r%lz~wswhK{L5I&UR*~<_D}}CK)Ei6twY>as;;RTTP|0Rvb!o}z$|w!Sgb%J zU07AATt==_M3{yK`5LaKdnpAn^p+P0t~O$q9LzxbxOffW$W&HXA~$|EyJQYT(N`TK z$3tvH({$}rV&~8TxyoSGWJ|@Cnz3{Ife~0<9BfXOL6>c_b9`Z~-h_+YzmelCHq+SE zTwzggJ1+J_+=i?vt^314cF<>X*{w_BF3^Hyl5vi#1Ir}WoN^skUR)lWh^h9E`?*Wiyc#ClN##f7MW~Jo1x85ZjiABrE{@|dhupU z*)%7)z^~Q5v&mhZJX~KDq57*KBdy zLr;Zz;nGk$sk}~}i94@yaaYiEtDr!7Z*S2o89&7?ll4+AcmX+82M_epO@X_@3Z9BP zpk!zrcMi=TUckK_F)g;~*c@_^P+!qB@KC`S%fydiV>fgLaYIKh^Vl@ZOvfJ0UV3Q5 z!UAuPpo`R{)XOf~#9t%Go!0VV>1w3wuM0L+Y^qwhxRsj$cEQi4i~BOdf7e&=l{D_Y zWM;5Y^%9PS)T6Pm$m!+oM)M4-Tqaj$auM55R#8~n)Q)HCt5t5jJHUb*EGhj515DlHJC?euT`u#Q zAO7mEjAlyZriI*tbtAc8IrIj0@W9=cA741Rp}4Zn&N=aSrGrKL{Tb9cc(hp(t3ZB zo`@&)UMWi-oSVe~@wZrZ=^ww@;qDzbos@pp;}qysL$CmPUzK^sFLGIVg^b_g?-VqR zU}|fN?OmT{+X0D@QtpM?z+%1|&j)3YJ6SecBo-jnW5+gFTpy+vk4(r*IN@XG&|r=9 z9%$3hesKQaSS!~H$8L-fB=8h6Dbw`78CD`)E8 zd&H7U=OUvLGN$|58Pc?eaNLwLHx~4dkwv_UM9x|H<#=JdHkZ8B{LT--fZ>h zbL`-ZyKUP1dWEr1upF|FVzUX3NjbsQ71rorQH~oKnEaz-Gw!aftz?0_<*KuFS72;Y zc^AOOHo>@K^EU#5-Y$N8`S1K9UcSdS_yX2ojpI%g_R4Pf6}wj|eF{C79Ra)pS>SH* z2D8ySs=)&{yk}kY^w9jw7wZh-SJ5qr%p&MZVtb&tqHuh5+&IE{t?wo3e4E}>Yq~%w z7!vDeIbI9&o~c{3X8l@WwOk`imW%jiM_%0Gx$WSNXx4`VQ;#Zn`+D=+q`^3?tT28^ zL<=U>C5gMHkyEg3U3Y%cr`^Q|FInwI^m3Chwp{`u?J4o32#lU447wO&3oul493xY%?8m1Sioyx|UXVR6ef#bS`DKjso#ZYXnw`Rfb!@uT z>)y^_!J3AL&8~`c_HrQ9%WAP~IvaOY6Fj2VcQ;QP8o2ak#&M^Vu{GmlXSqYMTy}iZ zUBF3&a&=GVy;)1W@ucT+w|$!Kzv^HxHYxA>1lN&cYV@jov(4M=%2j;|jsv~IVkRtF zabdA+>9U4kEaK_Q^Fa%}=;Dpexzk-o9&ThJir z25L8dSCwaNBeI0CVVk=`(zzAr-AyJBPH>flO&_7q-MIPosBVb8WvQEX^HUeEHL0p* zoSk-KBbWkrcb1ovK8LqinqRV&$-PakcJzZE-k9Rzt#kY6I|qde=jN8q-Mw-8ba_Xx zj_-*N-b~>8-~0aKw-)p(@a31fyx-(M`L?7L>8WX6kGSu}*RRDdO7F8W`H-YTTOJlU zJn;zs$QDP1k4{(}@(Sf^^1Z40ZS!6zPagUs28Tk?8%Qq#QhicVk;WZu-7)2Lak6gqq4t;$4#&6Qo325yjh;TS)RXH-fy#f z^k#YeX8FR+^7WhL2R6&kZI<8JEc4y{!H~4aVy}mElEGUz|KjFw+}k|)-XFZP-87W2 z&nLOJO`5QdDVmaAQ8p!Rd&OR4u)dcROZm;;bR8btsEU7D-i3`#JUCx2e_~1Bl=6<3 z9h%%ze(cifw(>g#$-U&~AGHeCpXp2PEx+|B$8AC%`3X$XRQc|{n{KhzzVbtlTKmZl zg=p>Rd6n{mA<0{L-ac}?YCcJ;%=bsFGJSHAtNPP$$^AWVf2}gzZpl(*x`kS0I{o=J zo$qe)D@Fm=s$A;;nZMS7p0`1(w7XoZJg+~dmMk6Qf=^FwwfqTCdf}V>iHod*9(qPt=g?<)$Sr8$Md>s?c#Z|O9HOv0)2j%)zMaq ztX5mCw>r)09#;3VdVtkKtgf+orq!#g-eC1MtM^!a$m$bT^_bJ;dd2EnRzI-%nbmKs z$`5-6)9a7FXgm28&!Fn>TWW4?Req&2$X%@Vw7Qj5`LVg+`QcVaTP?O)Znes4z15wp zPPIDI>RhXftS+~DfYn2-9&PnFtLvNQqxvU-Qr`>Z}{^%<)#TYbyw zhgQF^`n^>dUwbrWsDyBX^)#@y( z^Q|tmx}ViUtR8Lkc&n#a-Dq`_)l02jWA$dMcUgVV>JwIxYcvO3Y~E>?s7RJPZimKR!GZuLN`hg)53^+c=d zt)6Z5LaSF;z253=R`0d?h}Ea9zGU@Hs~=eX-0F8$f3@mM|DPbsoocnU)ecs>TJ2*s z&+0I%qpg-$9cNX4Jx}Mmqt)H4&a^tu>JqCftgf_rl-1*`o^16DtLIt0#Ol>nZ?bx) z)d#FTZuL2c>{UvihUdknh%`rPWqe+ga^wwTIOKR)<;L&gxjJ6Rb|LI?d`F zt4plzZ}o7iYpkAP^(?CwS-sloEmrTf`k2+{t-fLPL#tm|{n@H7CoJ7>=~lC>=34D* zb&%C|EZ*`*82CK8I?qzi!t1GRpvU;M`4OTZzR`0a>kkzNHzGC%VtDjl@ z-fBq3F}i-qR@+z|Y;{bMd%o7{Y#D~@^h>NBEf)ov*IB)!mCH9+eJs=Em#lsv;|!ht z7pueMcOW$vTh(!d<|D1%DL=HQ`7x_4JG?39HF6VA1KbtX7Y3 zc^9iEZSC^eR$m_F@&{JCZRc{H)meouFR^-QvCB7E{kqiUP?@V+k9Ac(7Z)tYfjhW* zjMaN9Tz<-GYL(0Ft=3F%xxwnmwJx7)^;H>g>H2+SwZ~+a3#{%j#pS)NUcR%-w^;pF zew0z$hZ|fSHPzK}s|QbW`BH@f_c)$~~|ceGl!hs#r~o;t_nO;%r@=kh03d+p`& zV5@T$xh%gQ7cAG6OI*Fp>i2uQ>@Rb5+kIReXZ4U3E+1$0!Tnu+&T7U%E_b#%aiz=C ztgb)Qa*fL~t!})|7ef$BJU$NTmVVApG-T6_MXInk% zahET%`u>wHe`9svGcIpqb@6j9A7u5$7hJy2s`s+XX;#Z#b-C8+s@GjU#p;u9y8N2e z>~~!5X?554T;9{_IUl%uh1Cx~a``)}`JcKx+UnBJU0!MR<}Y1-z-q!bF1NBe_B)sB zt*-vT<NzpZsGC|RtL!inohr+)n!R8 zA8Pg16qg^e+9KWMOshL&xID?~nyAaCTYa|8|6=VwprfkSKkR!ZGdp{y&?fX62u*6} zNHg>lFhJ-aqyW-Hx^zPC0@AA#QK}*~P?U~ z$5AB$dzv2imJIAK^%z_xup{)?;+eqiq{kf<0(*}hztH1ZbF^HppLO3d$HFexT|NG# z-CHrx9X)0n^Ov;@T_dj@Dxh?J>HW=rK-vTiqS?_=5JndVEEXll3@XkE`{# zMUOl6cu0@m=<$L%%FA_0kH2WYV~+Cjmz6I(n`2i!_SEBYJ-)5SD|-A>kL4-{&a0-! z-g+FP$L)IDrN=Mz_?I4oq66pG)MK0;$Leva9+&I!OFf>|<3&B*(PJ6;f`WNDqV?EV zk0bQBO^+Yy@t7X7^yrrV2fR7Ix*qH6aj+hz=d{pra63Zum`#s)^;l4kQF<(+N5>_PPx5ky>oG!)`Se&^kEQfjL66aTjMwAydTgi1 zPI^q!_T&zcV_wK(PYxTH6k6ZP)U5_8@@iRRh(xbdP^Phi8kMi!vzkk%D zy!-I)n|hRod;gY)asSc(buqagAeLl!q<<(fq%q&HW_&{YT;8Kl;D!CB32U zSUtATW2zo|>2ZJ_2kUXU9#`w}O+9Yb;|F@&rN@JMJfg>wdOWSiOM3iSkC}SBuSZW% z;C9=3%%R5!Jx1!Wq#mp2v4$QS>9Ls}ll9m`kNx#HP>-+ZakL&M>2aDK=jw5R9_7^4;rRFUuAAFQ=rY4(>TTa9x2S z|F`R>XUbsnPw@1)1)k!6OMmnKs@7|io9n7%{ujtS^~ zjQH>8YreO|FY`JzzszGwi2RO`-{x1=hi=zAIZ-|(m+yiFew*jlO@4D56fGI33)lBnd=La z-(25nxy(6o(KSe}&paK!_&f6$`}FnIe(L(n_g1;S?Q)rO%ymqV>%0D}xfJ-t-`$ouFu@B=Jw@~-(25rxoplc9?Y-4bKI_7B?FhupXTq(@6Ywf(?#uYyUhC+e(`jt zC78?n8YoX!n;}Q@e9fk>_QOPrce* zKgrWY%8BNErFn78_2rb`=6UkAAs1a<@qEWz&|h3%F4<2%U9#N1+dPpRc{=`A>eVZ~ zTscyHRjCzSvvzdV+SRJa<>=_A|EyWFy0j`atJbJ#o-#RfeA5=q+-|PPTxZ!Q*K3|t z?fw40vjT7HW##){`CS#SXC)qOaXM?~pnSKA+6{00FtKQ}#LS?^2eT$e_m0Zb>|mBN z=wOz&%D#kySsBr%<&vxXgYP}P4`#Wl^o}xrv)lhSJLNh8e;3v}@s=md{QZXsiMP_7 zgIPDDW9~n05EPY=nLctyyzK4rJMvv~X`cC8`JFDmGvs$<%gjqv6K^GlCf+R_zA1Kd zoHUo|LATS}$Z?JQ&S~}==4^A8{7vsRLHCyXuJq{=-zD zlNp?HF>C9(*W~$>U2`#O<2t#1IlkdPn&&0I&8?5r%NZB5W?#OTb$-5VxjgxD;F#_| z>eB>n?>$#l-FxNeKYx_mYX8e=oBPHxlTM{1WM&L8PZ1Nv(?&(T@Z@P@+^!KXD6=|NTab`q`Tu~RZhR!=C_lo?EJeE}l>2iyCF5^v`?#eCN8Kzj$>OpcJscLb zK;*dG@;mzJ*J4a&SX4yvYah5L*A|)kJV~j8 zWUY|D^F}R5iO&p)Z)2X@=}{-D#p>Ic|D}+>NlJ@LNJ?#_&$;FOlZ}&7pVQkIn`u^ESu4%UEKgTk zE}JtO$mJS(PQ&|aBa%|9>N$ybUGmmbOa8v1o)_!C&T@KY!_2bsl9twUE6CGD>6wA+ ziPW>6m;1Cxi=@;v|MM%EP%6GuTxq`u^L8(fJJIP;jqgVVnM=8&BIS`cBWH=^obgvu zpH>if3BvR_Ydb$0tLE*-c;4BxK<+yYT7P@1 zQMvtJys|j)oayV>)mT1zws( z^4!cLTHsz;kTBo>5-pcvUO)2^=EcvCo3GBzd#AbbR$ub9gYs7Y-_9dSL_|$&q0%Fd z%Hv4XlgGj)P`7 zHT68+Q~dkr9~D*q$y-nbd5-_SS9$t_bD;=f2?{y-W$f; zZxm#X37L_N%+XsSu+sfY-jfUt>^1)5UH{)U&K%=kG51#nt|QYQC)3ZxjlzY_w@sOF_UFF`bX8bnl z|K;Y4-)00aJU^mko4z0YY`hwq#;$QK?++#%Iy>+8v2_X*AF=kkhF$#clil^QpG=Z} zTfQiMkzbGz^_@JXE{J!RUl6w-_Sdfy@BW_jn*R~d|2|qC0q3e_d4%m`9^tZ*uB0U1 z^+wE$zmhUDZf3$P|1||Zo{^7c=9`aZT(=uf{ol9Xh^Ptr7Cg%T7W}Wu|9#z+je6zD zYh}QHXyIx1K6x+yOjQ3TPn#xB`|o>so>p$%5I%k=6_xztsXP9c3iC)Acmz#K{nxOm zZADrOwa2x_n8zl+ZC_OUlk05!AGbi>-sF+c7&dQJP2^g5qz!nkrPpa536oN*tL1ok zG_B&l-_2Q1f83yQ{U5CrkE*2i=atk_{~yS;{BoZbTSUcX|3Afc6|r4KY*)Y7=#2Gs zOP-xPsL0XxgL9Pr)&64a+uL3pV;*NCUP!n+yYREmuA5b`-m0BBcN?e1sCle4ZqJ;3 z^yTNi%b)Jbzwg7M6<6LgcDv@#LWH=vuV%6T5B1?&}G!KW#U1Rf45Z zcjbTBUG}ftj!)ZND0UadEldc!6+E#!Az=5;$@`tkFVS(_@kM#iqy`t?&J@~_@=|1PegayA9HDT?H6w^o-)ArULzlqmngHS zMo>t@&4nv{HM_xc-z4r^Q^m~#~oJ$J+1n!*efY-#cxd57#BFte1<8H$fCNVJRWK^&6s}86* zk+l5DJ#QQ@esa&7wZQ*(<~3$i&wcV5mq#E~J-5Zo|5B~@Wmi!>)To{=AL)1}%Kd0Q zo{f>;E?j@7AK^RddR&6M*V{KPeq7x6CvV;6r5KYiHhyf}xF@Ym)DbyzbV9!tN93a( zKEDrq%oCewM-7YbDUXRRw|t}+8I}A*ajTfj98ulkkEDdjM??Dlp>5;LjF^tayUT4% zo^V<|OZeYg$6H-WLP~sUT&npD_sLsbyL~=2kY&eAL)n?&!aD@d-`j*8T6> zZjyYY=Gqtd_}!dkez!^ZcPAx?*)j4Oi*A!(K07cU*EPBymY3`=OG)#8%yC+Jz4#$1=2$oGJ^!&z z>>dB{VphlWYN@sTpH;Le5p#dCe8t6E+}sLYTY>vI@m6}1*!zcaHOh>L3W=Bd#C;^| zWQ@E%a?0g@KR;_7lj)0cxA;0GDYkpJx9W}^~D#gC2~ZQi5!A8*W=BNIl(kBS@Rf2(UGpP!b98X=!coQyPo z9*pc2Up(1-2Bz=B+KPiJQBf(er&G+=Z#=wxwTa2B8r3Cke@f%z1pmGLwcKMJ;`=3= z;}-v)zxw|ypOVzOi`q?W(J#f=-QxfASO1^oQ`35P3%s_9cTDJOUOUA*#BKH;+sEGU zAIqh+i#NAiY{tm#sn#a0zPZKn_Hr=iQ=b8~Zxbm`(J=P@!H60y&dS@oS3Z6_nREaD zJeHWZs|x&Y-z#V3=_@3ZORf-CA-F29)CD%XO#tge(*j# zUAx(**RtkrI=Hlb!D=gaoatKSiyIZLcaXP-3ICM4Uf@Ff+;MBS-}uzqW#L=?w-b3g zGjA*AeNUZ+qt}hQa3f^epSN>NTYP^*lhQ|93|DgR`pKJ%S>O0dkDFEW z`FXpp&3L*0Gt+(<-fP2)i+kQ}*|Aze^|%G8)nltC)bPKYkN)hmC-Ig$U*OhPNvINE zHLj|@bXDZ#H!t0JdFd)A2A-l)LS;GMbGvV2&%F~773H4rWVTK-uhB<;R^L-Tp}hZZ z7dKviZ$`v3@#SLIXC6-q{B5Z{W#nUovT@JowHMTDKPT7z)zzoJrVtYqp?`Nl{%+sZ z;t3_FTN$h0t?hQ1ujR{E z?%gxO<$L30<*WKF%vbrJ`W563J}%$v2y#0|RzDLRyOb=i*E0V(p&+llG><&_S$V|uRETIO zPwx3MQvQg}-BvDJbLEfVsq)qI9Mde!?c9J}0E_;gn=&R4ZR$TtEhDW6zSO%xn7!%Qr;q zy;1V5S-Yux=dpl&Ozw<=_C2{=$o^dJ#lm(Sx&ETI`6ngC>`GE1?ILn*#qAmLTuRtE zv%6eTc9s0{O%;2JTrOodC@KFy%Kk&{*`D@cxqQT4A|oe^@gD!QG0@>G@F&LN-q9=_9AZcVh?sU(MaZfBC*2-I2YwP zwD3B&<*HkHomz6MpZ7ZBghQg&nIKoz%ImC^`@6N*X(!LGjn^3>ha|7_l03h*UMGi~ z(9Y}36r=6E&T4txcJMmQ1z1O~lPMZHd7W)?Wu3iFioBM)c%6>&YU}EC`pEsV-Rry| zHzK#?Y>}5JkL9GwJu$*^#>%}k(sJ(0m5s8TM2Y7u=agLM15 zcey9d+Rkx_-`Y+IxzE0{om}!lpR=8Pa&vcvIWLK$U182edA1*iIlbgLd=lpDl&fBo z!)Yyw*5+^=xp&v)a8}4oTA#ytUS1t<slbk*xpL1C5!IAl#VWM?ZJ||r6rP2AEhsEWewB>WYlb2y^KIf{uj>hG4 z(&Y5<`J83)BjREU4#_v1Yw{M5a>H38FIeggr>8u>v>VP2c@8~p zILk#{&l}Ecc^P`$aAwN$d+|odUHQ9#x!kUhJaU%|G8Yo$+`;BTO({dng--G`L(PRQ z@){XtF1#vt<8X7~h+Ip$yh=k>$P-U67t9aXPc#>@w<^f9_~5gv#r6in&ln zs82N)O3TYI&0NSMPdvZ7To@@Y@oVNn8@aU$%!O_8k}WhBuF1>2$Xu8s&thbn`73#a zk1`ixSxc@|!C!Tgg1%Un1uY=X^&p7NTo z&4s>F9CKllJg*RQ;i|k=L(PS*@)`*<7ix#aKkGWv}t&6$UAw%RGOCcA`zjz8Z7w*Z+Zk{S+u4r?c3#&wJkh#!EZiYF} z6?#Oj$UDI8StC1auKW=#_eS^_xgh`d5_fR8oRQ6IdUmf>+Nv+FpB#;%T~?XAE2Med z#bj1-S!Hz=m08tgJ)^UT%xW&HoX)~BtGlf7It$6H;j${|EGV<4%c`iefXrGhtCG(A zGHbi6$~yDOeAZ<}>&z>&irlO!y7QPVx2vk|+-A!StEM}`Y`JCCb^FYgn^r@2F0d|D>z04j-l(eFz9zbZWLJ~h z*HpLLY`J~Sbj#~Hr`Ia!=`OGTT<-`ct5j|SAXh7SGq;-C^#zR)l3;ZgFn%E|^i&nn zQl|=eUZ)C4)Tu&R=~N-Db*hjyI#o!LP8HHtrwVDO6Cv$&Bcy|Fgml!6kWRW0(pfh` zy68qoSKSDCK{rCW=|)I*-3Uq6jgS=G2uanAkTl&0>7g4TJ#{0bmu`f-s2d@@bt9yY zZiMvJjgWr21480F6Xf-u>pOW&v*H6n?ieBcZ6n7B8E8!qK7JvC^i&lxSf>gZqEm$o z)u}>;=~N-Zb*hk8bgGaMI#tL>ohoFMPK1osjgT?A5i(XcLdNMv$avidN!N{#3Azz7 zQ8z*+=|;$8-3XbY8zED5BV?LxgiP0skQurWGE+A~X6Z)AY~2W%qZ=Ww>PE<1-3Xbd zJ0N6$XT7}sbKRGZE3KCULe|TBe`~&Nufc|$isHt0sko4OJ5mTrV> z)Qyl$x)HKjH$t}PM#xs(2-&6^A#dwO$UC|bvRyYq-qnqe9l83 z;5j6(|6Kj$Lmg{jK*$97(8&7GHgb%RkF7)UVWwZmCwi(1*{xHBe5zB0e5O-{?9r)0 z_Ucq2`*f<1{W?|10i7!3piYDw(v6VAx)JiZZiF1sjgX_d5pqm7LcY+AkmI@$@}+Ks zoY0MsuXH2iq;7Zjn$T{5z`CfNG$WG5y zdHv_gBOk zA;0KUAy;*(kZU?s$aS3vxuF{&zv@QFP2C9jO*cY**Nu=rbR*=JZiL*{jgU;;2)Uyh zA$N5n{>b1R+R*`CKQ8;5I>SX-R?r$>X(x+@4kf#8=6D0PArF6it#ZHCUzG zw&7(IJ>#|p$yY=Cipp`mDk{%bMHSeps3KbxRbs26%4}5>%~nNK*s7>1TNPDfqo_Io zMKuU0s!2dmEdq*a6HxRl0Y!BPD5^_9Q9S~R>Jw1ZfPkXs2q=mnpr|1MMU4n3YD_>; z69S5w5>V8PfTHFE6vYxy6h{asD&zJn79hSc^2HddtSUM!U(d1P-L~;%6g}^@J`z}d zMTwlRidwN%QERp;YQt7VNo-ZrmaU4~u~kufwkqntRz)4zDC$H&QD*{*x)4y*m4Kob z2q@}CKv8!BijoN^N+F;qm4Ko&0*ZPNP}GxvqFw|Py+}Y&Zvu+?5Kz>YfTDf`6!j;d z=p_P*1`q;@TDU#u1&Hq(`D&fjQWYJM4{@xQ-L~;%6b*4(|H#)X{fdTizA75VRz<_v zs^}HADjLC7MI+g&XcSu&jb^K&F>F;dmW`ru1Qd-YpeUVyq6q{PO(dXb5&=b%2`HLE zK+#kJilz}zG@XE=83Yu~B%o*(0Y$S3D4Ih+(W?X$%_X2{9sx!32`GAvfT9J2fTBTe zPYL;AwXcr(zb7Rc_i6l!KI42;mcLWrjBcSMe0*Zbhpy)gSMHdJGMW47mZwnCLE%WfRTNS+{-|(`2l%I4E zUq;boxAm2L8OX2b3g@e$pV+GCXSOQ(g{_LNvQ^PFwko>LRz)}1s_0j?D!R!=(QgD4 z{Z2s99|RQLBB1Ct0Y#Yv6x|`9=q>?8_XsGuPe9S11QcZvQ1ll8MSl}e^nie(hXfS; zLqO3Z0*W3JP~-~I&%;sVCZH&Y5Kxri_S_X9zIF0VUF(u6`pA5L$`fQ8Uq+D~WaTNX ziX6^YMImfe6v|dbVQf_t&Q?X)*s3TyTNUMCtD>B2Rg{a3A|C-o5d;+FCZH$}0Y!NU zD9T4bQGNo73J_3Kkbt5>1QZn}pr{A|MMViHDn>w2BmqUm2`DN-Kv5I{MI{L+Dn&q1 zX#$GM5CV#QC9zdeTed1{$5ut{*{Y}mTNQO= ztD;V9Rn(cSin_2-)Rlmu7YHcoMnF+_0*aCeC`uuqD3ySsGy;lx5Kz>UfTCUm6un45 zQEvi@`Vdgmmw=*v1Qhirpy(w6iUtr+^fCcO0|_V^Lzv20Z|j;)HuvsF<#8$}Zc zD4Iw>(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&>ECPyV6HqjVfTC9kD4I(^(L4f* z<`Yo#8UaNM2q;=eK+z%siWU0*aOedD;jNU!448hP7N3^)&C^b_dzUmr=Ag$Qn{b7474ERkWY2iVm<< z(LuHc5*huNy=bG9lv!d68`*{bLm8%19bP;{JtqAv+3Izd3uR|FKDB%tVP0*byN zpy(60=vTHX zy2(~Wzp+)(?`&1{2OCAV2q?NuKv5?>4(cdUa-o0Y~#x) zs_e0v)>cK)oUe+iuvJl2wkoQ|Rz=m>s;CBA71d;`qFQWKRGY1eo@Jw`4gp1V2`H*Z zKv8`HiW(45^c(?2F$5GfB%r7f0Y!}oC~87LQBwknnh{XcoPeTO0*c}YD2gYbD1m^Y z76cTvB%tVd0*Vp|0Yw!(p1uOaH^V#@RZ>M2Ju+H(Y~#x)YU{CP)lo(5IA0aDXRD$P zY*o~et%^FaRZ(ZQD(b>kMP1pd=moYa>c&Px)R%ywegqWtC!pvh0*VF@Q1mhZMFR;a8bmJU5KuIf5Kz>{ ziB+Em=vbsGs=~tId>KU}J=WLtRM9BTS4E@Qs%Q*b6^&)9qH%0hG@h-B z(%GtL0$UYLWUHb{Y!poVUvqBq&9=q%H zCIX5!6Hv5;fTFDg6m27*=xqXu-XWl9I{`)S5>T{*fTH&ZD0-iOq7Mit`jCL4j|eE* zNkGvq0*XE+py(3KUtJk|>h zRnbAtS4D@|s^~CV6@AWDMMv1G=qOti9b>DaFW9Q+I9nBc$wtu$0*byOpy(t4MPCz8 z^bG+;rwAxIO+e8Z0*cNOQ1mSUMc)xnbdG?c?+GaSfqeiY^jRltDnz zB?5{r6Hs)85Ky$wpn z=q6hg{l->Bzq3`*A8b{0i>-=ovsF z6g?oI=pg|`{}530h=8KU1QfZv`e{3g+yoQ_5m4kIpvX%=kwrjJFabq20YwfWpy(Hm z=ZFCDbv8d=bX65qH{SsX@!H0hQIySVU2m$2vU9#F%E4AeIoYZx7h4ti*s3Ukt%`E9 zRZ$+cD$2`NMfun$%1=O10RoB&5>Ql#fTF?#6cr($s3-wN#Rw>hB%r7`0YxPUD2gJW zs3ZYJr3ff0O+Zl@0*cBKQ1lD|Mdb)6Do;RB1pRfTBhO6g4KGs0jf@O$jJ!MnF+>0*Yb@D2gMXD4u|#1Okd$ z5Kz>TfTHIKC`u%ts1*T4tqCYj^s4zG>?E&kd>KU@ywlsW(I5hf1`|*;gn*)<1QZP; zplCP&MXwM7irRTS%LRxpf26=^uZn&(ibi;C64swkbU ziYBmC(L}Z?n#5K`li8|h3R@LTWus^s0Y%dZD4Ib)(M$r0W)V;{n}DJ@1QfkWK+#+R zislheG@pQ?*9a(DKtRz#0*V$9P_&qUq9p_rEhV66839Gh2`E}YK+#Gs81Jf$6ZG0I;YrU2`Q5CJ@d{wlbt%}}YtD+5TRrDrX6}`n)MH|_wXcJo% zZDy;YEo>BRC7@^<0Yz^UQ1lJ~McWA|dY6Er9Rw7;M?lg01QdNhK+%T;6n#WM(M|%2 zb`enYF#$!N5Ky$6fTB+cDEf?mqCEr@?IoaSA0eRVb+4zi0P$7NA#m2Hq7LRKX7_t- zA;&U$IruNj8eUCZOmW z0*X!%P;{DrqB8^(oh6{?TLOx{BcSLU0Y%>vQ1k-pi-4lP2`G9% zK+!`2ivA&>=n(-$j|nJ}f0n&M?qIJQMQ#F$f(R(`5K!bLpvWSiD42jEn}8yRfT9or zib4q}3L^v*UH5u+2oT=_^X2Lrs;H~^Oh4SRjW44pr)8aLr;2iMzAEyuRZ#?673F5D zqC9L>l$WiF^08G>ezqzqz*a>C*(fSRKv7`=ii!|WRFr_CVgwXL5>Ql}fT9uv6h#qG zRFZ(AQUny0CZMPc0YzmAD0+r~qH+Wjl_#L60s%!82`H*WKv87^ilPYtMcFM+mH_e1 zH$Rw`!wP(+|AP5Kb`{GuzKo(8mQ|pmDyqr(s;CxQ71d^|qG#Evs192d)n%)qdTdox zpRI}-uvO7>Y!t;1P}GosqDBN1H71~_2?0e-2`FktKv8o7ied>UiX)&Xo`9kR0*YD? zP}GuuqUQ-HN+h7D6#+%92`FkqKv5C_MQsTvYDWkts%Ci_2oPTb^K;kLRnf=hi%0D( z+xRkyI$Kuv&Z?*j=c}TwY*q9ETNQO3*0gN>q|1Qhim zpy)*cih2`J)Q5ngz62EYBcP~10YxtnP&9ymqL&FM8c0CVAOea86HqjSfTE!U6b&Pw zXgC2yuMki)f`Fot1Qd-T1Qd0&Jd*{8FWLOubthGH-u&0AMq9S=WfYCKtPNdNQ99?V zq6utOG?A@}Cb3n~WVR}r!d697*{Wz7TNO=btD+ff6wM@{XchrQvk54gLqO511Qg9B zplBWeMe_+LdX0dh1q2i=B%o*!0Y!@mC|W{5(NY46mJv|2oPeSg1Qe|#plB5VMXL!Y zdYuqZG}iJQ6Cl2x=I5@*siO2;GS*nO@nsafVOhU+Q$-s%UlqN{Rz+{IRnbPaD%!+W zMVr~GXbW2vZDp&XZERKaHXB9n5Ky$8fTDK^DB3|l(R&0Gy-z^V2Lu#-NI=m?1QhKg zplBBXMIRGT^a%k)y9p@zlz^ho2q@Y^K+#?TiuMsuw4Z>Y0|XQuBm@+#vphMwi=to5 z!_RtEw9@>SIS*O3@nsYpwX7;Bs^}Q!tD-O1s^~ad6@AH8MJL#*=qt7=I>}Z=U$a%w zH*8gOijAVv1QeYipy(_CMc)!o^c?|3=LjhJo`9ks2q-#FK+y#Pihd-Z=pq3{83Ytv zBB1Cp0Yz5`DEf(jqMr#U`h|d^s{|BXBcSLyA)x4U%hO(f_{x|cwLYSX%>Q@Tx?$PI zmr?Y)WxbN7ivHkyRdkE3if*%2Q6^gz-C?VuyKGf-kFARCvsKZbY*m!SM$umc6#Y#= z(E|dC9uiRW4*^Aw2q=0?K#?n0KW#^mn}DJq0*X8Y6nP0KvIr;&CZNbBpvWPhD1?Bb zPy&j=2q+3CpeP#wMcD}fMK>+aN&(`VV7^@an<~m_{ykcbVB7dIiXwuoPkXAO+?=n9 z@~~A=UbZUA$5uu8*{Y}jTNM>#tD-_|RaBU*ii)sNRFr_CVgwXL5>Ql}fT9uv6h#qG zRFZ(AQUny0CZMPc0YzmAD0+r~qH+Wjl_#L60s%!82`H*WKv87^ilPZ9szN|fRRW5t z5dw;G1$!0>>8|_)I^;yhp1ZY#U!jQSD&M(_0li%lWFP4qFw~WvilkY*kdB zt%@43Rnc>7RTRTkMGe`is1X}QjR`1fLO@Yd0*aauP}H1&qF4fo;s_{;C!i>SfT9)z z6tyIv=y?K)5(y}3MLldR(O5!2QI}xP00H9r!+amDt17x_K1doDY#U!j z(ZpbDZhuuYiSt#_WVR}r!d697*{Wz7TNO=btD+ffRWy^Wie|A@(QGz~<`7WyDgi}v z2`HLJK+${xie4k2XaNC53kfJ%L_pDE0*aOpP_&eQqGbdWEhnI81p!4X2`E}cK+$Rf zie4w6Xbk~HYY8Y?M+hiN5B9t-Kzz%i1kMCiB>$f?`GhUlHolCaw}P!R160vQ&R0d7 z*s5qVTNQ0#tD>!JRkV$*ir!|cqIcM;XggaKy~{??4g!kaBcSMg0*XE$py)#aiasKs zXeR+hy9g-yn1G^B2q@Z3K+&fJ6n#cO(H;Vd_7YIEkAR~61QZ=0py(h0MTZC|I!r*( z=Y)Ww4Z)tj1&D8#c_;R!D%x30#*tv#_%e!)2U~>(siH4AUlpBTtD>*is^}zJ6@ATC zMc=Sh(J8hnI?Yx^XV|LfEE`4N5>WIV0Y&EsDEgj&q8|t-I!{2+1pfTCvzC@M!lQF#K2DiBaqk$|E~1Qb;!peUMvqACOwRVARP z8UaPs2`H*TKv7LXKv8bnb6kM<4w`Sk=CK2x>F+o1(Q3*6<5YYZMRjfKw^vkAJ2WpwrzYFMai~RZImiX;e1t;%2q{bY*o~Qt%`cGRZ%at zDteKvih8qEQ6IJ{>dQt^KLU#S6HxRL0Yw7{D0-QIqJaby4I-duFabqF2q+p#K+!M) ziiQ(V^a=q*BM2xONkGvk0*XcxP&9^sqOk-NjU%9FJOM@Ngn*)Mwx^>2@l`V4fbFh| z(u&KNVB5x*Q8dN2MvhTMQ#oH1O=GK~>1RngmQRrC&96>Vp$qIcPWIJ0Yy6r zDB49p(Z>W7eL_IdZUTxvC7|dt0*dw!P_&nTqJ0Du?I)n<00Bh@2`D;5K+$0WiasZx z=m-HtM+qo8MhGa{XnTGVAU?18s^cbA^rQKD(HFLDd>KVw*_Jgy6`kaKRrEDm6@9~2 zMW@)R=rmguonfn@vusuLEn5|R$5ut>*eLp*fTAA=C^}C-(FFpEek7piA^}Ai1QcB& zpy)CIMOO$Y`iX#|p9v`Xg@B@~1QcB(py)aQMK=g2`jvp9n*!bf2w?{$#77EVe58i>-?OW~-tH zY*qA-t&09(tD;A26g?)O$mQs#?I>~+P!vQ!k%xdHF9Ags0Y$+C6xjq6IRq4i5Kt6K zKv5V0Md1V#Wh0;{I{`&G2q?-)Kv6CNihKkVMG#Pwn-EZxX?q3=5Z@Z}$^9KwRM~uk zKaXP@Uq(>@$C^Jy6&2)sRaA(riVCw;Q4zK(D#}(x#n`GSlC6r0vsFWIE0Y&8qC@N1tQ3V2uDiTmsiGZTY1QbORP*jD0qN)TGRU@FN zIsrvB2q>yaKv69MifR*3^eiEuD4*l`P=NT(mJ~Sooxo@MDdt}i)p2a&%P4B#Sl>=l zMbB}*DvDvNqK0f$)QGK$8nabV6SgX9%2q|q*s7>GTNTB!Q4~i&Q9J=f2?P|iAfTuv z0Y%RfP?ShOQ7Zz9S`$#zhJd0Z0*cxaP}GiqqV@z7bs(UqBLPL72q@}IKv5S0inARqF!uO^dego z^=7N0K5SLgm#vEWu~kujwkmpwjiLbr6unG9(Le%<1`$v+n1G@o1QZP=plBEYMZ*aw zdWC?Z5d;*CB%o*%0Y#$;C>ldR(O3eC#t~37o`9ls0*WROP&AQ%qDh2+q7=u|NPzfm z6%;tBs;HSEHQBL^FQaI>W2MbjMKd^G70qO;qFHQJG@Gr8=CD=Kt87&?m#vECu~pH0 zwkmp!jiLnv6fGp6Xb}NLiwP)NLO{_{0*aOqP_&$Yq7?)btt6mm6#+%72`GAj@}&gMgw91QfkVK+#(S6m28~6iszJ(*=mnF<-8priwRxEfTAx5C^}9+(U*jPqAiZ+gaGkvH$No1RTVvBz8!MHv5haI=o`oSW1cEH#rdk} zG+Py&VXLCEY*q9vTNQoBRz>I7s_1*RD*Az~iq5l9bb)}P9|!Uej=dgX99|TA)x3g0Y%pcD7sES(G3EMekGvjCILmi5m59y0Y!fhP;`rcqT2)% zWfB64PCB04^F>jZ`KsgBswl$zgOEFpZG0I;e>zr;1*#~E^HtGbY*q9(TNOQEtD=W& zRrC*A6+L3BqQ`7isGq*$F7hK|oPX0*Z1GP~;<^D1v~Z+yoTmA)qKP0Y&);0YPiFz*t5ICw z+*d_^8b$d-Y~#x)DjZ^sUZjeOaK0)k%2q|i*s3U!t%{1XRZ$7HDvDyOqLOS?REn*N zO0!W^hJd271Qb0(Kv6jYipmpERDpn^iUbr@BA}=;0Y%XS6jdRhs44+P)d(o6PC!u& z0*Y!9P*jV6qS^!$Jxf4Q9RiB#5>Ql+5KvSw#Ir_#`0|?n+ifTC6e6tyOxs0{%{Ndy$NC7`Gs0Y&WzDC$5!QAYxbIuTIRnSi1$1Qc~8py&kx zinlXP(MSS{MiEdnnt-A)1Qd-WplBQcMdJx5N++Ob0s%!62`HLGK+$9Zilz`yG?frg z)FZ@GL4f$`na}ils-jr)STrrfHolCaSs_--m8xhq=c}SQY*q9sTNTY^tD<>qRWzTi zie6)@q6KVKw2-Ze7O_#Zn1G@s1QabLplBHZMau~&T0ub3N&<>j5m2<6fTGt4C|W~6 z(OLqE))7#&o`9k^2q@Y>K+&576um`2(MAG_HW5&?nSi1#gn*(MA)dhk#5c_R_lst# zqWR`~`ddS6`VM+hi7 zNeH&Ii1{Gteu!;+8AX4GSjE<>q6eI>iXO66 z(LZce^oXsB9?dD$qk2q+3BpvWem$RVI8gn*(@0*b;2 zC<-T_C>sGq*$F7hK|oPX0*Z1GP~;<^D1v~Z+yoTmA)qKP0Y&);D9TSjQ2_#q3K9Z} zvO+vf1c>jZ`R^C~rHWdc{|rr`P}}%2ii(9=JvXSLNX}P9#o4N;1X~qFu~kt?wkj&c zRz;=Rs;CTG6_sVHqG#ABDn~$3c>;LKzv;doT8zD z&-5Rg5ff?~Uq(@rP;1Lus;DXFtDPA3OcLIu%2`EY-peU7qqBH`EdJqDN8ijgJ3J~8$^G>X>DjH{gGNfmyZG0I;eL}6< zn^aL>&R0eK*s7>MTNS;;Rz(BYs_135DjLXEMT6L?XfRt94Pm2bC;>&o2q+p(K+!7% z6pbLDXe0qeqX;M(O+e8Y0*b~GP&AH!qVWV2r4vvzfqcB6fGm5XgL8zD+nlBNkGvm0*Y1>Q1m(hMQaEs zT1!CDIs%H;6HxR90Yw`KD0-8CqPGYr+DJgrCIX5!6Hv5;fTFDg6m27*=xstk(d{2TAXQ+Qyer^j@en_H9-4KIf~V57?^cL$)gVh^>ltvQ^P8wkrCV zt%^QjtD@a(RrDzvMV}E+w1vPXdav2mwWBLp|37i0_bF;C!o!hMS)Z`76{mzKo)OLamVZ zRM8{OS4EH6s>l_lpSi0dH(M12u~m_Wt%|&CRb;VMQ7~H-*=!U!1Qdl3P!vi)Q5XS5 z;RF`pCQ9HuR7E+=7mtdD*~XVqR3gku{6G~&alR@l$yPB zTNRaItD>@ORrCy76_sPFqVjB2RDq46iUbr@BA}=;0Y%XS6jdRhs44+P)d(o6PC!u& z0*Y!9P*jV6qS^!$Jxf4Q9RiB#5>Ql+fTH>Y6g42A=s5z4VhAW|NI+2|LO@Yum}jT} z@zpm!8B#nf@R|NLL#lC@ZG0I;&BLrkAE}~P&R0coY*iG`Rz(SHRn&s5idwQ&(erFo zl*m>^t=OulH5)~32q;P-pr|bYMePVEYEM8>2Lg&Z5>V8MfTGR>6m=n>s4D?QFAz}F zjew%=1QaC`P?SPIQ7QpNX#^DYAfTux0Y$wCD0-0)P}DTc^RWQ&T{k}@+e{U$Gyfo@ zcbIK_8AbiWtRHr%qL(;d6%AmkqLr&X z<9t=LfUSxavQ^O{wklf8Rz*wLs%R-&6)j_{qUCH=w1SPIl>`*6BA{qB0Y$G9P_%}C zqO}ARts|glJpn~;5Ky#%fTA}ED0+*4qKyO;Z6cs(GXX_g2q@Z0K+!e=iryxm=p6!z zwi8hFE+L?3ZkVT;0P)%8=dS0eq6>Ls>nN?dD*JSVymKHwkopOs>orhq7b$!3T2}xjDVtW z0*bN`P?Vj3q8tPiQl(fTBo3K+&TxPyPdo+Y5D4gp1V2`H*ZKv8`HiW(45^c(?2F$5GfB%r7f0Y!}oC~87L zQBy)dQB=66n*i~RHUH(AlHq~R^xrk#nr#+t8(&6Ie7H6Kb5)eU`KqV|TNSlrtD@)G zswk1IidwN%QERp;YQt7VNo-ZrmW`rz1QfL=pr``@MI8w!>O??MX99}45Kz>WfT9-& zDC$N)QFj80k_jkEA)qLgfTA=4ih2-G)RTasUIY}qNI+3<0*d+&P}G+YP!t>Pc|(Bs zN}Dec#i^ol=F|Ru;kNN*6ulg79XhIt26DbC8pKvbgW0NR2wN2mWvilLY*jRzt%_b@ ztD+HXRWy=~qEQ4CjV7RI3;{)B2`CyzK+$*tiqZ)vnm|C&L;{K?5l}RlfTAe`6ip?d zXc_@U(+Mb=K|s+=0*Yo4P&Au>qB#Trn%{M_{bRdm)Unip;x zUq;cwa4YP%Dq6((s%SA=6)j<_qNQwAw2ZBama|pS3bra*$yP`VM+hi7 zNK|=pyHMYjnk z$|RuZ4gp1X2`IWpK+$~yivA>^D2srizX&M$n}DJR1Qb0apy(e0iXIUHiq407b_)<+ z8}n`a3##aQ^J5~9!)@csDDq^pF38ujb2o~1S>9~_`I)}ORz<;VRb;bOk;7I+A#7C? z%2q{TY*iG_Rz=y^D9TPiQ4Ru%auQIKi+~~@0Ywo66y+wMC=UTec?l@WM?g`20*VR{ zP*jkBqCx}|6(*pl2mwV!2`DN?Kv5(CMa2myDnUR|6d|CfAC)X0weiqo`~)E9#6YdWQ4$v8Wtd6_sbJq6%zPRFSQUDzQ~jWwt7cW~-tqY*kd1 zjiPD<6jdjns0IN=H3=xHMLus;C`X6}4xpq7G~nbtIsu69Gk?2`K79 zKv7o$ie4a~s2c%A-3cg4CZH&VfTC0aiqZ%u>OnwJPXda15m59Z0Y$wDDC$E%QC|Xz z`VmmnpMav52mwV2**vcb5MO2UbJs0YQ7iL7(tvEX@nsYZ&St%HP8AK|d{s1*t%`=R zRnc&^Dtd*jibk+i(MYx`8pT#cquHux3>!sb2`CyzK+$*tiqZ)vnm|C&L;{K?5l}Rl zfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P&Au>qB#T+CdmR-hzY_{=b6fMbS-TOfmE#-Vww2ZBama|pS3bra*$yPAfV{Y|A)Ny0FR<-`?zPb*@O~8HUV~NAq9|@ zP6-H@O(UC4vLTz$M3*E4LdOJ9ib_)u5dlF_5V2$Lir7HGUQn=ML$RT#fQS(+-+iBR z|F;Alh39#n@BQBE+w0o==l;)}GiT2H&Y5#&HoGuD(VZ|r(PkK+=q?zb=x!LG=pGoL z=w2A0=sp;r=zbWW=m8j@=s_5u=ph)O=wTS3=n)v8=usG;=rI_e=y4dJ=m{8_qO~o| z?LH=o)^cBTtx)tEQ?#W;IP=96J>9}`_NPM8Ge|EKJ&RZmZf^gLpr z=mo?=(GJ8y(N4rd(Tj*d(MvEu(aSJE(JL@O(W@{((Q7b3(d#fk(Hk&8(VH+p(OWP; z(JmOE=xrFF=p7iKXg3T{vpy)6RP;>+aDEb)& zC^`xQ6#W7N6di*BihhLwiW*>mqTgVEqT?_?(Fqu!=yw>P=noj6=ua4+=r0(c$cU7Q zIVdv0&=h^v!h8n-65WSC-ndUFx;ue_kjQZ6izy0=w7m3%P!x{zLQxaMLQzx1LQyls zLQ!+XLQw=_p{NC7p(qluP}CB!P!xq26j@<_qG%YPC7Y6SxnwT1zT+Q0xsHW;AD z4g(amg#n7%!2m_=VSu6zFhEg97@#N?1}N$T0~E!<07daIKv4n=P?QJ*6m^CHin_o6 zMO|TNib5mJ2MLhqJv=S5MCzIT?fj9ovm(QpFQ%wxq@~4ILQyZI7mAV)3q{F@g`yP1 zLQyJWp(qWpP?U~XD9S)A6!k_d6!k$2iu%F;Mg3raqD&Z|s6Px)Gyn!DIvWNk8VCav z4T1rR2EzbF=fD6(SujA60|qF{h5?FlV1S}r7@#N*1}Msh0g8se07V5bK#>y$C@O>j zid-->McpIK=>$l09)Al~525ICejHL18P0q$MWvAz&o@HRP^1@%$`A`h9>hXXIbxxx z0*@%Ur zIf#X#xrl|Ld5DFgixCS&mmn63E=3HA=EDF*3t)hvg)l(TA{d}(F$_?284OT#ISf#= z1O_Nt3Ih~f0Rt2*g8_=JgaL|{!vIBB!2m@oV1S~lVSu8QFhJ2N7@%l13{Z3p3{bQN z1}It!LsL{AX?~Ufi5|lju^B?qn`*)q8P0q$MK?rRKKouMT95QX(FVjq(T#|OqK$}! zqMHy4MVk-{MK>cBif%zH6y1tgD7pa~6g>z76g>n36g>h16g>(96g>t56g>_D6g>e06m5Y4 zik^f4inhYg6s?OihaMz~3ixx^*9%3tArw3n8P0q$MbAZAy8I{QMSEa?qIY3{qW55cqW58dq7Ptzq7Pw!qP;Lc(MK>q(Z?`A z(I+rK(Wfv#(PuC;MbAW<3ki_ub#VmFvqI4*GX?u1!7;&Ct!f0-(i5FKVX2OKVg8PzhHnOqoqvS zL6HdtC<=iAip(%TQ78;e(HD{Cl>|uiTK?SiexYb7e`L+lGMxEhikh~xJaj}TYKHVe zQFFvXQ3PV4s0Cu7C=#(y)Dp2!6optQvLY6Wq7e&4F^EA?D;S`tH4ISH1_mgy!2m^e z7@(*v3{cb#1}JI|0~B?D0g5`p07bDdKv5?cpePOoD2j&xiV|ReqC^;=s51;u)CC48 z>IwrCodp9Fb%Ozly2H>Eg|{@nM}S0cLiz!NOY5Dc2P?Uo7 zLQyJWp(qWpP?U~XD9S)A6!k_d6!k$Y6!k?c6!k+a6lEd?Mg3ubq5&{K(b+IS(LflW zXb=ogG#CabItKqGA}Js04sKhhK=Io=j1aQ1m&EuH7xenJ=cu)6z2NSD~mJ>4l;S z#6r<9#6r<<#6r;s#6rQp7^he8fW00>nbmLd2kG5e!hY7zQZ13p*7X~Q04+bc@9|kCT00t;}5C$lE2nHy67zQYM1O_O26b2}I3ug#n75f&q%2h5?G6fuSi{-_rae0TP`~p=E4l;lh=rn^h=rmT5er2xAr^{WMl2M)f>g#n5_g8_>6!2m^{!vIBJz|a(JYiaIHfJFD<52kGwiiYqfL-w}}XTF%C zZ(3R^49ppy+oPpy&@6py*E+py)3c zpvZ`lX*(z~!2m@eFhG$R1}F-J0g5azKv5VBP!tYBQ}k6!^Be*s+SZ=H`C2F%(UyWH zQQ^!NQxp+pSsx-4wLp5IC=#(y)Dp2!6optQvLY6Wq7e&4F^GktR)~e7)`*3oHi$uy z4F)K(!vIBXVSu7`FhEgz7@(*F3{cb&1}KV!0g5`o07Y>yKv6slP?P`z6eYp{MV(=Q zqAoB%QCAqC=qwnZs2dDW)Ex#W>Hz~3^@IV6dcn{XHH$KDBS4~~cqr67O3(D$@uS(K zsBq?sDN2j7d>$$kr6avilz~_%>Wx?^>VsG)>Wf$?>W5e;%0w&_^+zle4L~duosAe2 z4TJ%T2EhPDgJFQ8b6|j?EEu530Rt3e!vIA&FhEf*3{aE@0~F=M07XM!fT98zpvVaW z6cxe%MJ^bis0aoqDuw}yN??E@Hw;iz3Ih}kg`p`*i86;-h@vh094%ESTFXyk%c8=W zFQ#Z%l;x~&p=dbL3q>Ok3q>Ol3q_+43q|K57K%nA7K+Y8EEJuOSSa!$7K+9o21S)H zKv5M8P*e>A6pe)eifUkhqH!=l(Rdi3s1^n&ng9b7O@sl8CcywjlVO0ODKJ3MR2ZOW z8Vpc09R?`600t>(imrwMidMn^MXO+dqSY`!(KRqY z(Ha<_Xe|s-bS(@}bR7&(vMdF5sI4eNBK8I zg)?7F(WWTNBh7`Pn~`29x&^UNbSq+^=r+Vc(d~$ZqB{@^MRy_=iZ&w_ita)z6y1#& z6x{;@6x|C06x{~{6x|O46g>a~6g>z76g>n36g>h16g>(96g>t56g>_D6g>e0 z6m5Y4ik^f4inhW4MNh#1MNh*3MbE$hMbE+jMbE(iMcZI#iZ(`>KOjJ&-TWB;CZXsJ zrf7RqIP=96?ToVg)h zArw8uPh-E13TM8UqVJ+C=R^rb-y^+HbP%yn^aEm{=tsmt(NBnlqC<#X(XTK-Q3DK6^cxINbQ}gKIspR|{SE^Z{Q(0M{RsmU{RIOQ z8CIFLgCY|QP!s|K6q#XwqEHy1$N~ctg~0$t;V?i^6BwYVDGX5542GuY+bHu`0wnrV z{{Er^Leb(D6g0PnGha+mORMFwXrU+y>4hRIVxcG+u}~C)SSV_RSSV_ZSSV_PSSYd~ z7K-eMg`&2IK~Xyxpr}0zP}BhiDC!6U6ve^-MV(-PqBt0!C>{nVN`L{15@CR%&M-hx z7Z{+ZD-2L{77S3-4F)Lc4g(bRfB}kn!T?3RV1S||7@#N_1}I8_p($!%HQ!BuM89t# za3ZaGrazhQI;L8~nJ=cOx7G4mE1{?l(hEg>5er5A5DP__h=rp5h=rm7h=roF5er2F z5er3w5DP_v5rd+0V1S}57@)`j0~BS$07W@4Kv6CXP?QG)6y?JJMMGeKq5>G8$O!`! z6~X{TE*PMw2nHxBh5?F7V1Obw3{X@G0~8H~0gB3CfFchJP*e^>QoK+z-^plC7-P&5SwD4Gfb6itHx zil)N=MHj#TMRhPhQ9TS$Gy?`Gnh66G&4K}nE`$M!E`kAyX2Z}F4Y!*65+Kn}@aTGk zP&71wf;rZ3=8Gx1#A+GdRw%j@>4l>Ch=rmBh=rnsh=rm>h=roXh=rod5DP_@BNmF5 zAQp<2A_hfQzyL+dV1S}4VSu9LFhJ2&FhJ1?7@+8C7@%k+3{bQR1}It$0~B2Y0~D=+ z0gBeb07cir07ciq07dIyfTHVRfT9~87c^&~0eGcDs zyjUpe&B0C9aOR6Cy47mAvAs}q8`29!w<8vc?m#RQ-HBKz+KgBzx(l&TbT?w5=pMvE z(Y=U;qWchoqWfWhq6c7rq6cAsqK9CBqK9FCqDNqWqDNtXqQ_u>qQ_x?q9gU0dL9NSdI5%}=w_?=c>*MQ zQUrl>i%_(kDcWHTXTF%Cm#vol9fhJ-kX|Ty6|qqC8e*a7b;Lr^8;FIXHxUa(Zy^?n zb|Dsu-bO4Gy@MDO?S=u0_P_u|@4^5@@4)~?@52B^AHV=bAHo1ddtrd0k6?hJk70nK zPhfzePho(f&tQO}eK0`L=P*Fg7cfB4ei)$WOBkT&D;S{YYZ##D8yKMITNs+67p>+d zu|&~2ej59dQ1mSSSK|R|IP=96{b03pj}wZ1M0%m| zc?|&)y^^P8)@VJ`-$?LSGNQwoFQ%wpwB@nRLQy8t3q}1A3q=DE3q@xm7K#QU7K#QT z7K#QV7K+Y6EEHuS7K$8*K~XjgP?Q4$6y?GIMR_nlQ9cY%Gz11HDu4lsoG?I9Aq-ID zf&q$(V1S}x7@(*G1}JjF07a!RK+#Ybpr{N6DDuDnMddI+Q3VW8GzQd(R3J~ z=mHp^s161ws)qrJX21YNGhu+DSujA+g)l(TMKD0oY#5+u4h&E<7X~Pr2SZadD%u=( z7E$y)fA0ERq3C7)uf~g`!9D`0@4t6_kml`ufjDj1+>H4IR64Gd7U1_mfv z3j-8g3j-8g2LlwXg8_=JhXIOifB}lu!vIAaV1S| zqs`+8km%bew9FTZ@)@aHqQjXlqm2<_No@L1FOy*#M5AuQ=B2Nr4Ye(xrzA~mx6*|$ z!nV_D7*V!w=<_74Y(43tw|3hFltTyG6ZC1fINKle&)c1CIrK5OZni7p4WpOsEqdIN zYHQuqFnZh0?PeI6wwrqx#z5OQy$mDEmXu-`xwiT=!zi#lnPC`3w!iuqMyV|?(=f_y zR}L_Y5w^Dn8pddw?Ht1xV>{1b7-Ma><`_n;?LeMkOtz&I7{+wl%tFJMVSB2`FfOv0 z+=emFHe{$_%(q?TF^t8w-4%wh)Yf){VJx?KM;XRS+wG$bV~y?m^9^I2Ev?cpHrOt# zHjGWSXKD=NHk-NDFgDwq6Aj~D+trf|<3ZcIQw`%$Tl)(PV~ee_-Y}lF-8s`Rw%LBT z&@gt`GUgb@%eL9`4C8g%bC(##E}Lb6VeGNF78%9|wpEuI#>ckzml(!ATgPRF@ujVL zxnX>3yK9AE9JKwk(l8F$`dnieM{RT08b*U{`*nu#yFL5{s(+KccmtgPll_{FbOucJ z4>!>%FxflZO6S02ueqI0g2{f*opcsV_QQA4X)xLQ-Am`eWanSA?`*R3&yjaC+4=XR zdztL~gTSdKJO83JO4Dp2$P+^TYt34&R>o`#$@Mjw;pS<^VbvCn(X}jvXf1A{({iyCOdz_ z;|!CXzoPFVlbyd~ZJx=_Uy?Q7Wan==T5PiO*VHUE+4*}$mYeMSMG-4acK%QQH6}a% ztM)pRo&VQ%gUQbSEV;>K=l^!Q&1C0)SK4f{^Z%RNYqIk{3_NJE^C!L^HQD(iyIV|l z{>IqlRL+O*gr= zZ&2F_>urq-H;i_D=+nifjOH=4tX?(>HyrL~GTLvZ-;+0GWcH&qbmv69+TW7MUO9Wj zxRFio_O)ueiR`VTcrkmACGd7vu$O3}mP_vr*&WF16L~dnL-BNacf2r?yuQjaI$pv- zKM4*|Yc^#@60@|~VJf|;zpU9FOThpM9%x6w*%Ca?!9WQXbFl_Vu$s#~SO* z)O9j>ED_gTw!6C#OQ%&O$ORT*AA`1-dO8F5SL;O&%8>>66&V-8D^ zV}4@E_a}52K3RNuJSVp9c;lVvD)AlbAKGw{5qm$S;R9%^)0k3?xDSxumy+Kwz0MLb zwrh_9RhV1f-v7#MRhZ?MZ5^)i+jacy2QD#UL(DqA3I6=LlBLRbgci7bx1)S}4sSYi zv8v(nZ_Qqn-&F-yrK>t>Il4UAh>fBTWpMGf__B*lw&+|AB9}v#-L-0-D%Q_`?AS{A z(W%{%*S3|)=Cup2bsMq0DNPruBI>M|236Ie1Q(a4xArU%4?aG>nabv?HR~30HeuHH zp8je*RXQOu=am)pM%Q`|FzZXVFa3$@Hq83&eJ6gJXT;q?sZ{CPMCj7ruacLk z(svbaug=mEadcVTrM|*bk=5?+|K;7GMqCftR+W7^EpR#7q^m==L>#{MvZ<=*spmhR zrAl$vRo@?>N}!^DzC3fh5!;SNCR~UfI!Q>Aqeg5m^0+q7M>d1cdB?4eX2Zu%e@zXH zj%MNN#qZ2f`6QgRwvQ2)N@6w;_;EXJO7(YH)sL~N{=%pBY_IBX`CV5` zFk%HScMBKGw-7vN9?|K~=Zp3bpG+!Xi&7a@R&4-Hn zN#WI03QF=vj{|Mht`|T4_S1B%Pg5Fosy?6vF2kSxG9<@n%i2dBzA4R!%_57>RGzlN ztV{0O`v6rV?PAHVhg+&$T=L0xP1P>8F8tvd+C?s@v7H;5roh%tol#J7j*h?hi z4cf9q?Amr`6P52bN5Ac<^37jcV^>F;+x3+^BW@w3P-kfcEpSzRh%()?;+EsOt(*v7 zsp%d*Y^FKhfvu)$6~$j`|Oe#d_ey zE2wu~Oo_OP;&mcEO&?1>!;sJF*Bd_KeTP}^es0Z5ozKP%+h3<*Q2#NecF-6j)@W@Q zcTzoEp%YmmYK|6nJwy73W4#1irC71Jggu{$UU*ZZ^B&+(%_{mAtm zX8msI=Lcz1I=9btTRxi7gjqMQfBH|lZhtEK`5B4sy=KQko#@MDS1jSeSt2$K+(4&| z620^FeJALW5lI6w-qTrhpmZ6uM9gdUr>>Y=mu$Y7mMBe&>i0r)n&nI0C4PHJno&AU zn04zdtH03TS>C@fnbTOWczXx+rgT7k_Re(C37{lg2Uj7k4hecBGEV=v+i=f~r zE$};x{uL)-KV9MY9rg|7wwJc&ci8U~9Of$~ulbgO&uEAI4*P?GPpByT4huDh878Z# zOJq!Qb7cF-3Y*mwMI-%?&PMa*gUK=sa~s1PIiUI3&HFcZQo9M2H8d!&^fA~83pJS| z2RCm{tMz6kGQ+!3D!yVjQ42IuYN{4!xYA5AwCD_*n@r9aP7)DM*`-jD7ANl*&7*8VTUlwVfbvF5D0_>MEGguDwvsH>T7Q_= z4JESp%VBFl1?4^4)dC$`+ui~DJg4nInmV;hHl5QJ1v#s&GsbF)4$HD%m)(~4+ujn8 zAjI}WHr08Dz)ZyJ80c|z#$K_|MCU6_)mW!x3r$9deN{HiQQ~NY!7B_S9@`L}$p#l^ zYNRR&9gY$F+DM_vC}nw>+J30w1UN;vgsAUX?3)T#AFO*K@LMz4)3TO zhO!`sp*PX;sa_@;M5|XF{WTe7EUi@f3YJId%_S(iiI;dcCZmEy@1u<6pmte~(pzuN zOJj(6+MK19-g*Tuaj9s9+OPiOD+Y&Dr?lF`@*Q32OvW%46vY!zlwtm&cyPG1IcLHz zn(wHL=@^4{P)=ju5F_;_Rvuc18_f*U45PzM9E{e6Nf{i>3*6#y#-4_uoSc=%w!Y*X z*tMaPbC4Oh1s?=g6es5@N~PN1WnEsrcZ2i6&eIg|TGm+vyU8f$4D@LzXK9=lZGo() zlcL1@qMi^hs`#K+KzwU=>T!&BC`pLvL}Ux9F<;#!C#Td^ri`nfo>E^|ol@tmudeY< zubVcbrg}!r*p%wJ+0$oCW23re?995F`ha!3J#F1TWqRF&DHCQ)m{nt>)J~gHlTtak z=AxA3$NKO-p4niOi&_)27xW)l^nZNJ>jh&Pd|b$+S9XRmy~^)sttAtx1_u zSzS9}>i>E%>Sxyn*2MVQ6i40InG>c?%b8YJljN(5i)PfRD$zAkS~qPX)p>o2XL@Db zr2Lsvz2$T)<4Y&ctoN2V`WE-WX`+MuFXsNAKrpLvMh%|}!w`(d^-iuPunq6nnsJpg zC(rQCm_5CwKDn0JB@o6=m^y<3y3;`Td8?;QnKEsvw{rRf@(62BPM()4r8-CX$8ZD|Vm@`ZkOU%D|SxjN(@g_@abK7J~lYtgX*l0_1m?@bSQYE?;a8STkTA;(1OYNYW0 zUOStkk}Yk_)059ICpu35u1~d#)*b(011@udKKm{8+3zf8Uxi$tbW1Bfc_S=MQ!UX2 zoL@}JAg%#UJ4k8g1WTJ(ic8ym2bZ+=^4^^i9L!CBFnqXU^5XvOyfgVosuRc4W#`2 zo&y`h-|YERgbn^jE(g+KDZoiVHF|?VQuY)}9G!=VI7?)hTNOVg&SFh&6g8!F`ml>m zqdC#u{<&;{M|5UegOk%qrA}X*J{1g2XF3eJ-2A(Z`*e2cukzF1x>ZtIN_$J^KGd3K ztJWm7jYEavB>K9he|dr?rt;~I{i!BKOOJ?i>LX_5c>bY z*8h!B@R?QHnRU@;w)L5n1pUmJ?c;B|Iz4{+HzpJRjq`$0U}ME`H}(;qYP}jyVa4el zpPIiFT3V!)TB2#Xth%VyCQAz%(1e7AbZcknq?XJV4Yai8CEe$Qgwf66(2zJwi?D?8 zDQzrK^qYSz(k)RPEG;@)qIeQP6B0EGIjwQ(XvcRbVk-#GW`d=OHN6-+et5eKfPuFT&ePq)$7scE$-v{ zF=x<45YKcI{J+tu4y3Gg4@|qzC88a5;s!KQ3OLBu`ShR$*(%P`T6OU}bWKgQB*aoI z-CTR!#jD&X@7SpWPNePQEoljs1b!Ie z&&Ho^B2}5+mo8qaG)=mA6>@U@Y_qk?lGuq8jZ8@yPy0|g3{nN-J@KhIt$Y#&Cs|Sx zEr}fh3V?#0&bdudBy^TLpB-9J_% zx8DD)KGwHiu1UJ>;Ai?Di_K@hHBCBra6kh&t~8=K@#FzPP=^&~F`1ht52X3MdCP?% zr6xVckC!Pw-AOfXxnu@yb9J+1ez;}cFe_PqqJux4@sA&*iAtxWpETv$ljdhGl-r%i z{MknPYHj|(vUU9F7o753dNF;#iSI^qOR%)(d!*{vTK|h%nRK7xHWMY_i8ak$JMpwn z5}fi*MTmnwl$q}-_2!k8d7UN097WDtucK^8MR8t9xq%hMc^;2rNS?Rc?e-SAONJO_ zc|*Kuj+_GD7CGgf3QC{jE-o#~E2k|hN}RG?eole6%Dd1d8!xxO`p zrIcw!iKn8p)XgirrOpv~Mc#aOS+S#B?~$?!-aNa=o#XQ6I?5g1l8WN&yfQuxcbVQg zBQtQvC2p^$BHNQw=H$)t-4!LdYO{Ws1xot|6|*eQQ|hJ?>YRGhHmD0OdtRBt6Hs#0 zTd`+|H@hM~pYr!ON9FmFoOEQ)Vy;cK4cBCLYG6T~CEg0`xW5!GEk9_JoU)OnCrnwUFs}3 zGj-a$Ma~kJuhxb;^POHtsVZfTyQCy9hiOsd<@e?aQ;WHRgr_1WhbZ->2C_pd@+$JY z`BYQBRi%zHXZc89$WRwMN=C}5^Jk$>o5$@@CCDYJeFf;F_K%~G?ef#8eRw_Y{CscF z#%cY7w$5>sc+1NiC7xnuxyrdL&yhP)9ZYr*uw@NJmV zlyj)-CMc7D_T)QY)mC$zjv-!8UWq5C$mJd4aF+O2Yq%Ums$gDsX`X)_NY5^F4k;)v zp$exw%FDT_qh$G%p+OCRK1Mrk=G5xceyQHNbai+cy>(0Lqe`d>n+i)cK4lT|a&9wa zWg1ntFMFr6EZ^bH%gOPkWjm!?$O&q?{=;)ul$TbNdxyD;%Bj8ivOw$MPKdiJ?&<dwx zSt^8jOIiEo{B=4E+B zd8)(b#CgH6X&ks>=!`q_bdg2Ia<{22ky6SaxX_b$9XUA_WsV%_7k%X^ zpo`~l2OVg+vpA1VrOG4IheA%k4om4oddhMLHb+jmbC|x6^$oawqAAlAe@KbC+N-L` zpiOwe5p=}}>~8$sU|OE<^zx#wm_iEyLOnx;Ttlgt{talS*<}tICkSV}M>;!!?To4l zeRz@EBP~7Cw?jG&x(2hckf%;~{e%m#NY4x`-z+!x3_>g zG+zSLO|d&ym!5_azLhz7MMV`wjxuTqL!2Ihp09s65Kx7VL6nWfCkKU5{JoJ76yDZM5?pj7d*c0cMMqQ~+m!~+IIW_R`c?-Iv_zIqzo-5bcvb>U9 zqBWq`_MPAyHKGz`s1~P=ukqGQ9Xp|Ns+Zf6FEeLRQQiM9w&pY-$#8F)A@b8^Sq=6c$gIcQEslPR+r70?glvKp!^zR?X|8td`7RUc}m71B} zJFZ(@&E%TO`kL->NmHt)&m2@et!_rmMM+aKGRT-wJ9A1E>A1<$DrY3ozibVnwm+5) z+H&0VS$&e~rzed~>q|~$U3Kjs`X8=YnMqTUr_g_a^&DG2z2~^;aY^IjlHBQWN%YS_ zgQ}?jN#mx})Yn&zuSuF*Gj;ro+Ciyg>9&=`giyqTn;8?PO--t&f1e_)CvPlW-F&e+ z#C}2CsdKI`Dm?gCCor$XT|r%s;x%}f?z=M4NY9b&EOL(W54BUNyX7PqL7k?*g>y6U zq2?!+t}4{_%W0I#mvG+(IBRM;oqLXgIAF^qf;!scNhL$^Y5JzkI6y)#H8WU7$w}7;vg#GR?kZ zTt_{HE+*AkK&1yH;PET0u7vun4^BaA5;y zw*|xLo=A?1x?o*ZK`jz3iw8Tt(+M+h>i##A#C&JIJ9q}`hcnlaqyA$tXgKWay-#j> zG@++To5U^8R~&uR6(x>g)UbGh?pqU3sg4So{?m9aaJtW9FjSoea|lg^^nl2>LbV1S z^twy9=TTSrw7*?Tt(4m(%?*W2|CBIzrpIvm+7SxkDRp{fhOe-aYmLK~8(mV6F^`{Q zA2c+Ur8Js3_{tYh1Epo|0w>Km=~R@^kecp!V3!IJE(l}dq_OQNg2C&hf4%kJfk~sm zIqg8rM|_hKWWe2IAY$+VO1>kPZWlG0Xe$VKuS1A+-o+5~5>3nP{d;Gd*XHQ(enS9ds#EThRqcFHrjo+Fak)%qgH5bY79#geK6w?0oGd zf4H}TZmdydN`{gj-Bv>lQpX{SJiU`r`g5Y&0v_&g{ao@UryTR*tp>hVz)f z>iHIGL8>&kW#U|^`k(=pt`C~k1=I&$O?hhL^$d5G)0%)wGp2uO{u>Nw)H56PwKU}N zO{96Ur*=SBd$qumJ2vzjOsxuNP&D`sxbUX-OT!%@BF$HIs1BM&R22EgE(|z^KY^oM z-)*3D+y>%_AgTtL@$e;R*L}QoX~sm={c$OIV&?Utog#JMe1h)OI&-K)p$@)WRhn-f z9-0W#jRUzkfJzMbDuVy1f56YJshT-nRWDEXP)Kf;#nFVcM@=;zR_fh@93+$ggN;+`VOHwuYA88dy@Mj`huy}>YM$%7guw}sbi;2!Hq4?Ou0c#_vZqe zp8tLk*N1L2L7kQFt^n`USJQz=`li)V{p#knDj9lw|FurvspgeDmsA_^ZCD(bx;PUa zgmw;{?NdKT(YK}jSFV$~r8LY&()gAw@(wI=zO#r1aDg`*{6iRzCr2JA1=R!i2CsCR zRYn%m^t?eyy1t?Y6$u6Kb?d$g3+U*04vG!23*8oc7g|+Ye0$YDX~;;;@TJmSweS8K zGE>in&>O(yb6HlQpOSE=3}3o%I+4M*Z3AXjbZ1AMH@cjk%n?dXJtSSSWd0z}eAJZ8 zH{D6?*PFXOJ|;ckK@pGz4P&VpyaN#k zdbT6ST~XpHaSzwkf=LzM>{q1>rh#s4(}O*9f89hq`;j?&SS*l0vbgR%;FA5;) zhkQm(ac67l6^6k<_&qw@?nJz^E9YR{Ff2K*#`{j`w7mp`GzWEvIj7Jmd8hEO?Ftfw( zVSdNCFX%~$s+_=qubMp$r$^HKP~I(1nNcKt=bs-jHom0r z^^qUqqgTU2V5H10a+J8JW#`e&yGBDVK9t6r`%g@fn;s%kKSTF*9VG!b3Hj^<-;2?6 zAw4w+x&o_X^xyE+4>eFQ|G+P3=EK=jL#Uv`LfJSQJ#$e@=#BL~Ro}zJx(Tx|=<=O| zfL_0#%thx-w@N25;JXyf`Q_4=M+ za@97z*kE77-DNJhQ2K@*X*6&R7y(iDgXb>6^Rj%p|A{FLe>%h%l9Mwat{XpFaMVqS z%bQYFGj=RJA}q&O!Kud$_=>mg|N7yBLEpM({6#PN_qBPE5iN|)f!}*aUwfAw*=stB*8>q@P5)O&w{(H?>q~5nd$q^ z=&Pp#UZDnk<+0Jrx0zo5Z9vTH%jtVR^-Hh6Eg#_NE}?7W`n+yJK$wDd7>H9qcUS`90AhN!-!CR=a zN_<7r`RW_6Js(SMqj-3uxVBL|t5H0!QG8XSczvVzu14__jpCh+;@yqn&l|-@8pVMK z^YK{&kmeZQ#iyPdbe>^!rXKM$X5zki5DySe@mSkGg1`rs0#alc`k_kTM*1FBz(zFn z@I@IxqY$1n2CfUu^Z|4;D~s4w8{za$OmVi-SiOz9%1 zDRH_U^mU0Gr?PgXa!`}v_*GU)_nyQ@S!sJa{X_x#ompwSELQRl(pM6*4x=X5>@51K zMp6EWf@a<5dzD#fdpk8j){U&ReKhqYynTWw|0n=&Kbe)bYeP+xx9i4A+wm9oH|tL2 zW$i(4YO>9GQeVzW+yBT)+jGar+w*to^Y;8j`MiBARxSrC9Y=3g+J3p{MpjD4-*Mlp zmtow`nnYiAE9<|M_54ls&64TsZdob6`P5agZeXSSR#4Z#@uQ;rW$(PdJ*>382Xz#z z16gT*{7vn=KmPXhW-0V-xw3watmiLW=lv~XrF=8#o6OaISt*|nB>tT>m40@J`cTey zFDu3Lz0WG{CYs4ge!1v$Q98{=2=!f5{YD6Ve=PTatlTBD(w8e6A@qYTR0Jc0zUrDz zmGY^`O8bfq63rGZ6|E4h7M&=1f#{{8i$zz8-Yoiv=#!$)iE=;2<$F!^ZPE8dKM~z8 zdO-9i(O*PQi1HWTa(?uSKuYOHfRx6F@~;*1`c9%0 z6{6>gR*H@nog!K6Cw~F2+`he(TqECr#7kx>T`yW2ucSS!I z-7or`=wZRi zi$%E~<^5eLx?1#l(M_Uvit>-@@b-_1J}vr!=&Pb{i}Ek-@b;gHel7Zg=uy!VqWmK} zynR#AC{deetY{Ze9`o_`8KMJ39ij!IZqZ?)=ZTILog`W(I$LzU=n~NtqH9Grh~6rC zx9CHnTST7|eNprc(LJIciGCq^K=hF4ucCj7T0-@4^Yx35KSs2jXuN1Q(G=0XqJu

    mfMv>FWd1MV4BfH7d$P3A<$y>=s$QQ{E$OB{sCbTMl&Rosb>vy(CFFJFUF4JGtK=u-cVu#g74JB*kPMOaWDD6xo=N_K{4IGW z`2_h2`7!w|nS_Oj=GFOm>r}k(ZMa?~z}V-;(ZJD}5>CcybDvN0yND$$D}b86%G;PbSYG&mp&wJIL$F+sTK> z-Q*kOKGK|Or8j|0BGbu{Z2lux0%ken+-`OYI33XzUl`mdt7&(s2BM&7j$R%V8c>=jnn2KLNqkFp$`MQ+6obv1G{yllS5ZC>g+)erO z>R%3sD}^$hqVKGAc~Q4`$HaDMY$@$P+0)i@cb;hTJ7Y_*=<8QU0h9 zbDkIIew+U9lY1%un(lv*-&3AA!_u2VW(c7#M~M8C2ont>On0pi>4=icC|^zXQhp+N zGUew8F*mrB?rZ3O9r=68@1px2@3#{uSLf(S1AJj|!2_JwnVq z-lqE>LL8rwUsLXyWyyVHq7c_-(mjgIr@T}My$i^r>A#X}C)bkeg$REV`BQQm`D^l8 z^3Ot~?LP7e%AY0QrThc(Gs?dv6H%seeF`~Ji1^2nGbo=;hA1x=;#f-gQDmDC*B>Xu zaT4XHlIIBF|8w$c%707lB5x({6(amYLL9p(f1Z3@2>*A4I6kNRYx3Wed*;9&`Sg>+ zgt%^m5Md@zKA9}0|7@~~@;Y*v5cS?F9AOx}be~H9Gsvx!Z>RfG@^Z?rr~CKh{ggjV z_iplULd5fi5b51V`4{AO^p`YAxJ)7PJBrLEbI4*L!p$bDD6b=zQ+})v@pV$(L!LHdiPg8m2SA2`(VPa-pgh;OtI*XL1Q zL>@-}`Sf2*c_SI4e=GghQNEEpgZ^9T|4Yg*Cx1)-8|i-!BA2 z^4~(_$2iR5Fd@ogI60P_K;{V%zL=~g>&a$vHMvfRvOG=>IjDIM4D=A%_c*|8YW;?=)cs ze!-LOav}6BBx@-@itZTMD#Uf`>3_P=YZw>MeYp^NeobCW`OS3SPTnWPbq@o=KiVZWE%NTqeXG+YNNzM*q9Wdntc{?q|q7l)p~*+vGom(DyAle7=>A zk>mt&GFc!*_!6>`@@jGkxq@sVSCidBT)$3;e4j@7ndHyO3(3oc2!9oM2jzbzA0{6s zpCex&-w@*ZcZG;=ALU<=-;zcM{wV)MA;PDU<0+p+=99(bVdRlyg%H@m*9%B`3@j69O8Agjnmayi*dt|Gh0Uh)(n%H?#@W5A952|t-arjyvNRQ_19 zE5iIL&LjpQowIPw%BEy~82J>rhkTKIgM5eliu{H&Oe=m5 zIg%VhW|KK&0Xc(=kd@?0A=dM)(d(;?hxbe~D?Ag?5UOa6|$nN-iu;re^% zet_IVzDVvBV*URq`4#yMsh*32f3nL8H(nTooh8-taBvsWT~00}7n6;odhQM3yXam| z{)F5nOvH2eIe*R?m~c z{W9IJk?)cpkpCfN?3Q$=km+OrIfE=CE6C;KF=Qv%L!LpNO{(X=5YH8K|AxGte27%f ze<7TD?hAaK@_pnNWTKDhCUeO=@=)>!atXPDRL^rk|9ZN&3$b3flvK}g!F@H|zbDo6 zT#(;M_ub_49~EV8u6-OeZtR@#G|OI$21Tlj^xHq^FVY~npiR2h^JgJ^L8)F!A#SP9U)pKZYub}%_ zvW;vfPbJSF&n16OUPWF@-bvm~K0`i7zDs^U9w5IZlZII797awgr;zG-IIORZ6gOB- zE+kiyt>p1!7kQ=-ee)c08@Zjlf&2q`8+jM`4EY@SKKT*3pZt!6Cy~*Sh;RLLQ$zpOAIgbpH zOUa|iW^xsI3VAwt4*4^3J9#O2Be{!wfP92}k$i>xnA}GuBw6WCBuA4$vWT2XmXiy~ zqsSP!j@(F|Oa7ePNnTCfO5RC6K|VviOMXBeAipKm^NT3|VVHwSJxms2olU1N#yC|S>!Lt%gJlV>&QQo_mPj1Pm-^aZ;}{R3>WT+U}~!RMV1h@ z3{yfi@5>P)Y@rZ=uq~?k`FtVlbcGQ4uM@(4EfWR}W2F$~vqm_{FuH|Mwm~?}Fg6SG z@g+om#I!=uPolZR(*ys}bO*_7Ql$(2C3LIw!L8Ocph_QD(ei?YX+G`jwXYoT4y1gT4#aNDOdl`1oz=|&nL@B_5V!p zZ=ib_c{I6(>>#_zK5{d;h1^P>M_x**bs6HhlJ0BBUF5Cgo#fr*Hg zpM02noP3(xO+HV)Ouk0GMZQOVNPa>dAipJLAdvVyq@Ns0rji+CkW~N2h3j(Yo=(mY z=D;42^GUt#uA{qwTt=$@>%w(w=X^)vE$1rEvI8$#qO zRn~FH&s##|BOvP_r2o${pGCUWd=%*&i!hSTg+ion-7s(x-f4o3V@Zz(*GN0b$pjHU zR2eSZTg?(8{zAG-gowM2?gk;!vy$#sA=1@Ncb^b(o=5jKA(UT3_jN+Vt>!t1Pt9|X zZZ(gATg_v{F3Wfe_jF+p?T&6W??8T5(%mXVzBbXlS%~~yNw=COAfIX;0DWp6fczTy zy&Ko|H8q2MJr>vKGxgTGe0iIek>A|gYvkkoU-=@;=YROCw;A-4416!2(^J2~z$ptm ze!eBHp06z$_?Cru06Tu?`wa%@RWAtCZ#l61EWJPWnubA94ERl`f&P)fZ%7yzM7=A) znYM$xF~RALB8k7-P~OE5SNH>OQ0O1P{*_JZ!k#Xv!2EviRZthS$}h~}-D7y`eZF*?hbo zJinh-NJ&M17=hIzKKt#)A^hP4~cX;wPUeIMB8KYq&y$85r+w z$n*z8kNQlf7Qd7no98-%~hu>XW&&tb6oF>-%6pxCVG^(Sbl6E*;l8^}P&_IS0{~0+};?=Q+|R z_Zvl@)SKLMbLvY)LxgF!KRRByN9WYH-JuV|kgadY0Dalex6RfT&qw_LeLEcWf#J;7 zw|aoSTcK~$LG;PHGw^5kBiT#OMp^5R&WGIlbB1d`rq<{{pbmF60y*=0qa(kW3@7C$ zV~|sy?BPnE(I2hv;Q{(?b?C!TY3KJX>eEU8@CWq0HbCFq(66?l}r*9L&VJzx~NPXVgh3CGs1JtU82x@;u--P`FD3Pqp!y)=oaY&qcY{RMX$!&&l zvQ`4OJ{4Qz4EOZcn3p;t(BXPwC-io==XVtZtxwVH!dY_)i|5QJ4&oJ%g+-3xu8(wP+&OyCRG8W!cyZ`a|=Anzm4l8rD zyAPNJKP~;&bC89NpgCbh)3T=S1-@YSg8jEbR_x!n1lSVhKXv%8xzXfTjInfA4A(iG&%MJgn)%56lTBVpwxh z7GfCLwD*HTNnfcs$;fuEX>7Xmq|~Nm8`Ikxn;x1!ZGN!4p((Mu@b2yf#(kpk9G?+< z=zu3nyAL_u2sV9Tx(;cv@@kBKVCB9qQa76u&-fyBt9Q|gHKqIKyH>0`YRzW2{pE6< zG2cHQx~k0J(+4t)(wpkW`pXuMO*>$YJH7Pj1F5OsJU8(!m7?*BkzWHPXxx{2E3|I0 zv>pPj6R33yv`V^+3Fo!{s_BsC6)i|z&X5hI`%{so<_*7EdG3Z4%};J9{qoe(Uo}sF zyb!5b2+sG6UTLnJaMR8II{otpKO5)TbF(qgTj@IC{*PQm#~ko1%Cgg1Sr=VwOq3MW z?!UjvTyy%apB+dj^ly40jMNv|F7R2XZJ=Q_`4!J4v@ddiU7`O1CLgI^>>#I<v2*qnNl?_bZWRI29v z|Lkie)@zmx@tBJ+!5Df3M#1fv*`>z&k>N6ZL5x4{J78$t)3W9u3YY0$f%%fl<=qMm z?z5BdHFspa__z|DfW>inycc6EcQ3%K#9ceGLwr05>JAa0p*^;jFmX|!YCQOd*n;b61Jz|%d=H{ z7A4E7-T$JP7=LdTjDdgjaETOd!|iXy*zNJRAu_Lj^H^N(--+`C|1HS1-#;Da0smJ> z`4GRntSZs}3BnBZznNngN&ZiV;t?VL8L;{({*RFPRDS|A5A)Yg#H$){*pAC-&OdH8QYEED{1LEA+C)d-pGKMD49lK)C*YxRFQ%`n>hJ-GI9|7}Ra6aMdz z<|qB~*vM1X5bOj$OUG=jig*;2Hr#2Z8rn|fa_v2FdLTt7iQopG=fXafNZf`Y6gmslwX>G zdl2$hX5cdI6$)E)RMN@Jfpkcw>Y zcLzoxhR@uAn-E`>Cs2k&RC@x=7<_6x0eO_J))TlK39R!3?m(F>_5}7LzIsm}8ATBF z1TIX%4w@&Bh6@@!fhh@wvBVSjC>#Gi;tBY1!7@+aM6}!Gp1=e|yTTKghb#LGT z#QugiApg7nrZ;duTyJ>;I}zX8-oP(WO7D0Brywo669V_6$e&9HJO`b75(4rt-Cq*| zm!LqNPY8UB{JoG6n1w2SF(L2{3go4PKr_nh<%EDd*73K5z*Z#p&cwhx6wh6WfwQ3O zPl*Bfm)buk21Y@6WlCT(TG6jl0(D6IRVjf6w1TTs0!gTjYf=JH==@De;0_eXwJCuM z;o6!WNJMR(lO9+z6un_eK;92BY)arGDC^D)Y{0VMgv>xOQr43hI0PN3H#1O*Lhb{G zU^gr?Fd5lgpBb2j7*5O#bfP*oWCrd-32w{`+>5OI1VPZXPs$9Oh;(ks4D3W6PR8`=^09?D901df5-Dccd)g~Eye zh`oGAAPptBU`Jphl3Vvs;2HQWekgDRuySwUCy1eGZ(ukw*1R`xCfY>H-askx(7HEp zJF35JZ{XDc{^N9SpcbiKy?4lS@arCC8bcmIW=@ckH&Mbpa?*)v@0FA1k-|PXDZw@C zzQ)$OBDZEa`F@8 z=xjOhBQqDoa3b#>xlm60NbN;(@;!34T~6{4>BVwVi%f28!O0LL>?d+kElWAforau- zT$pl_jCSdglfO)Z{gjiVP^2C?X-B*A%E^;xHaci zHipRij7&Ls0Qqvs$V`;!(Rf5{%-uF2j%;_8$-Ny5#Ov*hZO5hxAc-IEimBsqxUp~-<3 z1W&3$7JQFt1!Ik*s0bd@f-y$Y3K2Z61*46mCJ{WT1&0_(Yeevr7K}8KxX+gS?v_}Mcv;c3^eMJO+)q-J0(mNt} zUJFuGI2E9xv|nN;iptk_O8Sl_#o6Q#(gLf<|32CKZKkYI_Zq+E<_jsJ0x~XJ4Tfpf4Q_BkU{I0;?Wky%r`yOGb7UMY+@EQ}N3=c}2LD8*z9&G7wUazNe)m?{I2kt$<_CshoKKULcL z&{Qd@R3q_txvXxATNI)Q@5~9@fR2{5PkP&*a;(nfMnmtE&UH5hF0|`zDZ+awFww5> zkb1mV3t&0k7ISpJ7Qk|>m1g{)7Qk|Ri~-d5uoeu5(y0(Uq6O$1znc!hV_JYTz>MCS zx%of}7CKY(0@guqFz5W{imgC(b z8h2x|=X;eJFBFX*zqW1T%!0cC*VerBwa62e9tt>E9ao#n;dTr{8F|_ z5&fHKyiRiG$xRg1q98FhP$mlGb#K0;TzhUK3KDX??V><#Kl=i?R?WzJn0+a^iK1E* zjK~fALKJ+8xtlL5*UF?!j*gZ*9ijzRlG1X$e-@38NhM`aG#;57xLh>u#hlz1q5^4tPf6P-%N?z%R%-G# zi8G?3K({HBW?fE!ANmmIVY%K1CC*YzVSV!$=dYz|D{>PhH4a0QZdRIayC z6nr2>bPN?FNL{z)CW>lN(2*NBK@>bK3c9EO4y6>M4b?GKP(qSAmRnh$%mkd{PIp?6fK4f z(;vY%mN}P6$kpzz1b3nmc)@YWzmyAF(Y_6Tbb?&afp3@pZWMys{{p@}{yQM?`rU}% z=ae<(^M$?p~$>>q>g6vMqA{UzZP_hdwt z@L7%>{b|V$OY~ddYxwgq6U54_5G9;&ru#SW7?CVZBw=eRcBPHX_fT#L=O+IKVU5h4 z;`nLuO*lvSEd~ChANE0p}C-rV*-V5)9E5=DXGBazW?skros&!?4f~rcma-7tHJM(qejD%~Z zNF91Ihe@#COp)YxGYx4V*D8lEbBq+`Z>LD!{h238YrRhS49%R756AV&k(9YZvVDVc zBxk;aW{~hZOdipPo@gfgIaS`dnmI}0xo?P^ zBjctk4+-~)%ROy6eC~IjkMj{hlx|7FL#d~MnevYMglE#O#krBWNDB0|v=`v;WS)$E zlkj2M_i*?#_egnsk(P^G4b7Y1p|SaMfC_ zLSvNdQ(ufkjaFa3mV{?{&PK+vJg4K^cNrvE9?6^v`lKCnx12qO;G=IsIE1+p-#+or z^4zF{e`yE*mkthZX(2xG%JRIbLynb9sWfEEne;MvOKPj6(iqZ<>^j@pIue80d#ThQVT?#>@S)TKBASrUC1HzlMP|Dg; z%qSm)AaRlOwmQ@Ops0BZl7#KZv1QBrGm_g-ZGIobhW}_(gz4W0lj8D!iJs>6=fakF z{MVq9d;Q1Cw8`J5Y*`K3f!}`yY+}IwTd&x%LKu%k{}r%eL;Vv?v1NZi_+(_q zd0NIFaepq+Ux$P+`ikT-^nZU6nup;Zhi}vW4SJKyUxjnGU*1#b@pt3f>pvaeSpG;d`k6czh@MPr-Mx{{noc_^-its{aaPZo36fIK%x*^hW=2?h{a!BOb*CF8|up4aiyMS12NXS5OMs$V`wz=nhJjVY5de zTK@^|I=Dvs0|`m>_oY56*PM(m|N1e~?2Sx$MXvwEF_wAz4n^wUFvc=s($W1Jm1C&k zeo;#BC+;n{cFbF-5&!99|AE3Dy9WYuRi+n#k!$z$P-+L zOXIh$dfZhnR|RLGH^HY>da6?KtX46x4rw$0=t>g1X8u9c3=^CGN7rm|WVgwcx4A4M znB|conixQ_n&-OG#B`Y7*q5B^nyIeeg(eK|8p&924+pm8uTcXo&)4g?s0?MtqSXV@e*R=6aX9 zBUb~#LL9kM5Jp0{~6dDg41yr z(&W;87=lm| z%j^q|bj_3tq>b&tktgFc!qch}GteSJX3PrWt zkoqZ(ylkl(w<{_JRj1c$DV2ZK*@Yut+OK@vbMR%Rxh77#2$H|S>jfMIBAt3AB;UgI zFC6$xlK&$#Z!zr_bR~r54lm55m5y6X)q>2xF4( zUqf&a4lCccnX0WNpnu3445s`F6=~jMs;O5o1UVwyD&6B=Q%%lJhd};!V@kc0{e5P# zwD}ZV6~Ivd{l=8>Qe_XAs{0-Z>0vmK6Zy|@b74Fu9T1v3?hfjlEHn$GM4J)%SR9j8 zM_*(XNJl>#f-^*@Y(|w?AlbVS0=WffWv|*SknBAN!816l?A2P?lOK)wT!bnoORSuX z^1}AvD3n)mo6AhA_h)}6_GP)5^cWJB{RV2mTwyt^eErP2SRPwH5=YS|=qA!ryw~B& zJkj)i4{g)_1<`hRUx>rVl`s>;TfSi54f7P!J0-|)Hz3S)5>Dwl94E&8ILs|(U{R1^ z?uWnpQcOII=Vb}A)%14hFfYOXuM$SZSAi3k`jT+xnBGftIJeXT4r98cOKgZseMz`; zO|MFO5dLE&j8Xhp5S>Sv?<|j0)}+AX>NrMu&Rdh{uCNK@AU6ynzfm3mkBMwR6e4HGCqd+clCh*trG?U{AM9V}1kF^t+ zY?ez;Sc+@qXKV7#Ks}i$X1UB6&Bb}!5Z+8R%VqXx)*G|tP6qec79v||8$J>5@>BJ( zuSk^1@7!#_FbG5yeR@j=6;l4-;WbErMecqnKf5N{AcWB=R;=h_`99# zXViG`6aqhnW45ve&(0KMupjPEM5dDcmzj^@%Hfz14a0G$ngr~gDRTfbYGq=N%EY1Y zorU8tnR}py4P{`b%E=qvX{#VS2EIq(n6?~_KAd!mqY92+;^bl+b9>Hl5~}Lq%xO{&@*VO&RH>AjBY8C9=(X4+5*f{+|f*m4rJ?f}!CVrhG}wL#GOogo&xV zjsRg6Aj}H!k}nnJj`C@Z5Ke%&;Z8m@@vy|XiIo_gJoG_)-kF9-e3KOtJf=JOh{QyMvO>$x#o&Py zce2dI1M0+!CZJA`wnXanT6%}3n~90I5Kg%;2^$d-tMW}uOiCP@I0tHyGy8=~afX5| zNkU2_*f1#b#+9WxgNc8-3W(HXm}X_V#5a6AE-ip$L^`seQi2SNPbM!``In2cQcyOM z@sX2Jn1{rR2ikfF zUnKG)2UarLoBp8x!3@_4a&UNzFU-1~+EeJl@uPv{QDm_<63Ar~?i2=bKr6njk10ZG z(K7i-Z}dbQE~Chf(o|D9%<=nO&ub(tP%Dra2Pam-F&aVYpg?k|e10^L6{KGvN#?<$ zLyJb577KKs#ddBE5}gjzzmz3PNiA|G5R1@1I<4tP17T61hEzwO;2=$gi4`YnD2lUw z9~o7V2Emm$`lkVcexGKzkafXXI3)1mopN@b#%R_J_4(ke>{JsYtP}@A33P1rJLT*`9O@c5xe|wU4Nla@MgC}>QKX`spJGtj zxKN@-Q3>iOmPjRU5=7?_1q8`KJ{UWVB{+r{Cm8FE2^9;oNADE36sOOU?UeKNI1;32 z5y&oG9Y7bc9Y80+sZ}Q>5xStqiV9lQ2YEvWmc&Rz(iNo!MU9*buTCl5nYU;W8WnR33_X^h9%~IFH7WK+#Td z9NRw(T_hEQACnxuhC=7pR`j>D{usu zeu&^wAD8l2h;!{Z$LT2^lDUKD93B}sXes94w13s=vi{LPru>t(Q8MUa_0QW%E~N@@ z>tjmjsW=>2rk67@heGyW6Eir_|0FT-Q7WFqgCs^W53%5fM=75bNRX`p9;|0beZzhT zbfCdKLyuGSGNwsTm^^c*^O|@^(e?79u}h+@k7z_M7^HXt-Ph9^%_0B*) zT7FuS)2>Nstd?q9L|s5u8kBkoaqv=fBvc2ACsfrTN^uA-mw-}=LaT&&bSa8+G>!yV z0*q@oKC57cJk z+6Ek^(I61jF5`qO;c+;;h{87!^J44cW+Revmh1~f1Fp6L$hipRa0uN>U^TrWJNKqq zTTAgcf|_bEEvDLs^74Owh#h5YQYYdL$@>{`D|9- zSPzgLq*z$}kv#cvNH*m9={V&2LL9|7w(+T@5N7Am_LU5ob+}eMjm&he<=SSM0 zQK1O)Ak6FR>TJtvYie%KD=N&Nktg2y@b2eT z&~8Ovu(qiMN&f#m8NC~Ooh9*qvG}Eqk=g%U?FCKU?FDF4_>=b3j5u4?_O|yHl(nsI zZ)q#2kJLn>q3FRX{r`SeB{BcY*+m=dYwB!~*OT!7qg!B-4VC8@+F|}0F;218wpC5* zI{IRL8@t)-)EX$Z#wR#kMJhB-*Lk++&jed9)c5}>76toKj;nk z^1YMb7#;+s(<|RM(wpHki^d>ak(>o_;=X8;={0@nF8sFaU{=0&bkIA@=Wa%(hU1$5mw6gc{%3fk{LuhV|CdW+7%nxj z2R9Hi+E5gf zj@}mZWqSRP2hc>VMpP|SeeNvwx&8%vriv4-+{)WEew8<*6qWnzi6V5nZ}ta$c5Yu% z!cp!ARY;xNyHB)pOApCyj?WDb$?b6Tzfp6g3{?$!edB+CMP9_@%{W{Il~$oT+(cCa zj?<}VPw3-Nw=5of7ETLn59tfiRju-vjGT;hzlPkp-H9+_L(p51!ZP>8XmeBMdq+)> zLK=$-lB)_;{T%MXKR7z-=PKGK?+BlJAI{OD12ep{+*?mZgB;@>;r<*3C((TYoM}Gy zdvJIWR|bNQ@SiA|B-D`UO^{s9Kn%4wK_&a#r=KhZKiq}?xpc()jEZ-p z_gGwGx;Nyb$4w5x0yYP|6WrtB90MbQ-k#xp-7WUy>P?cD3F+zXL(Jjmu748KnISPq zk+~m7L(oks$*t_F@?0jK&%)Cxv36Axuq(fZQY(2cz%$8xy{&GUYFIBS>2tmHQOF~tZWwB8Gg2w7d zO@pC5sw2^8Xh9^_P+J?Ts;yaIdxRUJjkqjaTU}QbX+VI+no4-bhutoe+O)zOB!SOW%iL(anWkyvwFU8ue+R#V#mmC;CjL!`|1Sy&fY5NoW7HrCbEibt%j za#^G*R$g0Q9cnPz90PrKPgh@8OIL>>uU^61*sRG$tfjA~1M%w|)zrqKjiu3WePwB+ z9%>qE%H)EUj^ksk?d$De^^s^@Ez)8vj@DJi7DuC1vFgg2SViT6ida=-2~tp00&!iq zYLR`7q(4$0iX!#SboI0~wZ_(VVb-qGpo_aYx*%5CSYD2VL@QTBZ2v)duB?_y=obcw zX+-k0%5eSix`x_VO=DG6tgg1QrXf;qoY>Re*A{DPZS85pD+g7noY33b5nJ2d8C%o7 zdQGgOZGD@RO|-nauDZ-o9Xf&Kp)y1pX=sqT)lrpJMPhaJ<*K?OH6b|5L_@fyp~#^k z(olhHp>fsL$LcDU$Iw!$(MH0dhRWI+TUTZM;#esfVOeF=QlulXE|&`}6;+ir@q%7j zSzZ|n)u|MOYinvEVQDdv20Itg#&8&I*N#XxgJ`yThj_vNsSb0?_S`ia>thyFeQXYynD5vU5rA0+# zF*$=QA!m|v$hk&WcUz~OSvHW+pZNN_{_a!0^{W!Ps}lJ>4nqo4V(6IxkWUml7@!r@p^X=U6>DPvSt8CnplZEUD( zY=|wXt!hAzv9Hs;Lkx@ai1wN<(SIBFn;&NEr%)k%&b@cU*$Kfx)7p!J^{9q8WolC4)sX z2a9G67R??knq$Ob*kkFNV_B|fC~UyMVZ~^b+l)f82xE@Q)Kam7M(et@Yd6MPuv>C` zucK3yg&IOJSeHmNR&;Q2v0Y@U6Gv(*`x}LL2X*MOGdy_UC>~g67?P@MF&tV$fzi>` zxjHB>6B<|}#e-`EjcQP+5)=nU99be`=(Q7%mKcRC)}~$3I{4Z-+LBwt1$M6R0@XGs zTeaHJr#WWTN2(%fw6iUkH3&&x4>iL6*E9^Y_YP}-o>f`C9Hy+YN<~^3M!l}ai)!oY zG2BJt)?S;=SSTEBtPh1bB-k0Nz}#VJ2<6vMSsg)>Ho9ZjPEn1Z48JL?6IX|kF5QhW0+YhI{+0ZtkotJKHj<=)te5HtH~%R%Kzr)eu6_ zEQ(ll0ZU*_&q5f?d)rrcwzUSaf7oLy6r)jF4xMPTadR0r!QpVNnkE^#kLuFWB`YJC ztt}j>s%oqX;Vs0G1(i_@e=16(8ElK7ojVtCTtgNRaIm`s7g;JLuF-1Nqq97=1ca}LVBE|a9L^NcxK zHLbNBi)UvLd#`+ z!bO0p91KJjt$Am-c(#3&-Jb`vvP!m4$J(n3{XMD;-{8{0T?&+(Of6+%kNIx1>SduY zPMpiDe&f1sXgcu=LeO?N6X$<}!;@$&Hieh^o?%tX1o!()0nBAS7B@apRrkS0cB`C`Va*!Yxmj#v}QG$R8 zL{!X@j9kTp2^Dj=229tih?w(LugW!WjhHUq`&OTtu;Taoe$Vs&Ki}x`cD+@7>eQ)I zp{qL7R#)Tgo+Z(e@(A}&$`Tc^NKd@!y&0a;E7EWN^hL`CO<%Ye?|tt#KN~7Ehl&2)i*SCi=}UnUDRPJ~Ngq z>N9guq~EMazp)jOepn(OG#v``n>insduUz#@bdFnOJ@%%1Lbx`{n)+`nz?Mj^re_( z_gjL}1DAl~Xp;;lJF*sYA9vvAb*P#G)sGoFY3MN57oz1!A4twLFgVr>89r+GQSL<_ z%#SP93@f`=O35=*Js>-tB%Nwpm;j(}oQNx^N#kqll|u}tL$s{-A*wS-(wJe@VvrkB zgRWBsE-Euw2^f}IY~ZCWE+`v@57nKX7OdK%lG>^{E55`ZZ!IVXH{2XoFLZo_+jQ*~?GAS}u4ZOf;l)6akTn=)9+IaXRT(r8EWxD6A zRUbRhmX+}*ImS0Pa)XCYul!}BE05|{r-g{ijmCU*(s*@wryR5aZZu(7`e4UpD|Myl zj-%u2YgratWy2jX16`E4Ze+~C?03cgml6&in=+F-v4S6A*<_OIq?jm9(_WG0uF9e; z`OtcF@|=-VkC9BA>WSDg8~G`KC8&Gp_|-C+F1%Qf({6Pwipl7B_bMVe3*qGicFnL9 z_SaVZ(|T5#T+R+L1h}(x<%>-->Dp>;EZ1YviZtJxG+~HtLej?dI+WJhoeR{D9*4CT z>?SWtE>yt;lgEuhKcN;;TF%dt15C^LjPjQHDQUe1*A&wyFlbss(ys7_O~#UD?Z`Cm z&}{~@&_6d&y{e}5SCgs)6r8^&fXIHlTA9j;wd?QY!ou@lGEj>SA| z%0x~8>lzW46zbY*(wLef(9*eB=3eHh&ShHDg1P*@h3h@ZQ(PY(ifv?fUY(3ky&2UW zJBGcf>Ht#x_rYQ-j75v*jBZ*oH%;GzHTSwnm`6%;m#V`uBgY{sH@1GtLC?oHF{TdH zl~j=KqlTFY!?5a$@m^Lhlk2qO8nA|!kv!Rfu&1q)`C}dCkGjHWXj$uXleh~ob?D*T zu)6?LSMDyr)Rk9fj#bViLc)t@ZupH^yM}<)%7WZmN^zraD<}s*~lWI?Ubv zx}VkEtg;UlqL9&)RO$6)WqM22#um%K$3|m>(RGv7)@mkjp`UhA*RyJ%Y}wY6mw7cq z)Y`u?KW3{?V_Z$Dg{In*8kh9qU&a-N^geDsnlvOXezE*Mymq*nQ;e(Olp;Cp&zwZZ z8e^PIyNj^3yo80`^|%broQx*>YPUAhW<|PlsU22>6>F?{Bs0n!Z_EBNCS!dn{h9<$ z{#Vk{=l+@b#Ed%B&R?Dw|I3(zP4*`@PQvyBMzB<^q;CKu`)XM^QtR&+k7mxosHE4> zleI#pnZQf?q~D~X^rD5kUzM>Vl5u66G0S8=@R_m0Ca12;IU=@j*3304J$zv`NsUCt z!g<)nK@aF|o9I@PTv$MZ((>3oYlcif8+Fyh+J$t$&|*Szj{@B;rlnY(;gbG@$-^hs z4%3;k!PTRwW?W}al+A`@J}JlN{D%v-Lu-crdFdY0(@CQyvNQYh&R9|wo2Z_yr!~{m zihD)+in}fuXVo&VNuP$N*FCnbFhxh(8j1Ns#@f#WY^q>IQkD^Q(f=>pPglq9GbKx! zTuQ;!bfezDYFTwOhr2nbV|0-lu=awLFLzHy^+@Atld^T9N#ocSxFX3#9I3@A(qYgE zFtEFu9pkZ9n>;;Lp|uUQnUyIm$DJ=}oj6RYC9u>SF)2&UPvj~*)jK5T7ZL7t2cBpt%S*vI}`_5Do9?1Yk{ip2fva_ZjLNnxU^|rS!6N&eNwwI>H?olI#AOR$KMD*O4ZwzA&eB$F(3=C=cQuto`wm#?Vo5 zE3dlcfOBsaZHR2d%2uE3^vMRF?C;6;p6u>nPL-Mm3`Yx^=V(jBDMRs s)~%^px29_Ur<$6Ky9iQEThCaH?UQ!ww{tkOzXQcmbrO__}5)Yay`Wz5aiOE147Ewe|fcs zrH^q9xTC?)b8NRatsg&j^!S!~ao@ZF{hZ!wNI7K2$?!vZZk=0Y*iKO)w^gA!bvtm) zriUFFA!Tbsogr6tshOGTanZv}tQpUHjnKDYhIWviH)Hh|7Y%3?auuud#y-Ey_-<&sY3qNZJK`UHZ)G&-0Sxf=GJT z$DHeRFPy&MG^%FwI85)PAtxuVsaELPlsDcmD^~iEe@dO)19A6%)D*_;D%`Cg)~X)7 z(>y5S`lGJCp@y?kZO@uMKK1ufqY%^FcX}RyECf05?>;V5f zGj4eTC+;maF4CJOmXY-$UEL8$%~Olkb@i+RZLU9$*cfJEcy4Lv0*tQ5Vx-*6)-vaD zt}a;5WcQ7WqO^KcevDxVOK-KKj!KH-{ZF!{r99Z}|vW*b=N6gH;%vf;FF7(@w8FT^H_P<947K(_eQG z8;Y43X9Y`^s{0W#)~HhrSIsI~_KAPKDYx*WQw6 zC7|t}2Opy;W20BCoaj9w8UP#U%l^Ec!3}|7<3}c!A%>$Fq&A2q*I=~58Gn7*S!M7 zCf1*&9{eItH>+A~7mu%RaBmJsos31;Azb8dsfgR8L_0loQ>#DpBiuWN9e<&DF`sdz ztU99!EpHBMVOXtKaz)5p5lPLmlGo=Gczv$VRx_0`HK|Kc%s!I0J+YGX^dohGJ6uj4 zJAS0hi!#>A(0S|o6I>1C&Q2X9#=!^`5wT$n^kz_^i<>d989)m``Q#$A>=o5Ul?3;ZJh0#!X9_9nN z>0v&Yn|y2;$E)#IljmJ)u0Tfk@u6A$<3qng^L&#Sk$%oRglqF!t@WIlbs-;~Pd_K& zo->i>)Kuf2CO)ERn0yVSmFPFR1Zyp03_F-T+VSN0^1X#-$P9am%{FFRvz^)A?3mTX zEODR6#~G<#I^{L~b08JNhhNiU8CDO>XtmVOg9r37|h{uPaaQcd*h~(Qr6yw1o*qQQ_Yb8^A@M`AF_&_p_ z2Od0@o*AznQ+Jbj41SO&{TECR;QWFXVZ2N`?dMUiCP)#U4DV+Cd_+9;^JIK+o$=|9 zk24%eCB~5l?`BT_dGN{?9rb&)VVFCYHKcEk9sDr_6|5@uhJ4}UsB!n9;Q z{HIyMl$#HKIa$K4yd3q=J>{|e=ffZVCh;XI+{)M?;ngafYdkDrw)uS2--{AvThB** zy)9wtnUB(Z0pyPl*az{S%s?@Wc3Wz6o1q7twCgPyhFm7O-Xm;`q(AuH}a?4MQXz6>F&pWE+d z!QiZ;EW8PU{bUvlSWHBR$d?{ul^M!=vZ`F)$U>jVI?F0|U!;%~bzh{A1w*r!!3zvk zf1cHgc1IXU?17=XM+D0{Ey(zf`15l;IJ%*BNz}23APjLEZ9S^pI}t5TJSJIzSfy?M+zP; zI9c#mL41KxrJEzjPki#cWr8OQo-TN{;01yk1uqx8TJQ$JTLteFykGDU!6yZu6MRLG zZ-S;C?+Sh___^TMg5L}BJ<&{WVi+X)1o<*(hKmF{2zC?fBUmBGZ@x4AU_pM1o#8Qp zlLU_uoGy60;0b~&1Xl^3C3u10Cc!HOuNAymaEIXif{zM5E%>6~Yl80xek}Nf;J1Q5 z3G#EjERPq{1EOCrU$Bi}M6icoiD0GRK*3tU5rT&cP7!ProGCb8knhfB{wE9aecBA4 zBY3gkrGi%p-XOSL@NU6}1RocCR`3=P zy#>n!6M}s4H{~=4juxCK$S<2Rp0E2R&JkQBxLoiw!7~NV7u+bw7nbwJw%|vCp9_8?_@m(Of*#AwCr2w|OcYAUH&D zxZpU!BL$}k&J|oLc&gx8g8Zr`%YB*PHG+J*IQhE;9~OLC@MXa_1wRt}Qt&&$-vqrF zm?$q-ut<SqGZ=2v9f)5Dt z`(cddTfT{}3BD)zncz2qKMP{|rP4cse7!f%ZztGIu%BRDaIhd>+RgN{1y>64JMHAJ z6?{nW1;O_OzZU$jV8G{|7ZEHM93sefZByX`BRF1gf#Au48wIZy z5?mp8j^Gu7_X$2J_^V(L7c0!Ci(pi+PLK-=jGrmETyUM><%0JLJ|Xyy;J*cb7sLy! zmAvkPg9OJ29xu3D@FKyjf_DnOB>0ZtcY=AC$Wz~Tf>FV-g2xE*TUtzarr%%_v!0Ks8`Qw8}s zai%**@I}F|1Z`YqGrmf&L2#ttv4YbD=LjwoTqbz3;2OaT1-A-r6WlJyj{q{?2L+!N zd{gj!!A}JD3jQSM!-W{n&l4;ZY$w=5uv+ji!Fs`wf`;Ho^M^ zpA_6B$j?AC|Gk1g3wrU2cJe{NPJ;ae2M7)qoGjQZxJ2+{T8j%1_i@{ z9R#}y_7W@=tP~s|SR*)8aJ1kA!6OA51!oE_7F;WMuHeOj{8%LQ+#-0b;7x+J3*IC6 zkl;?ie+a%PxLfco!4Cxa2}0g=LmnH;B~^^D0rvv_X$2D{0oAw5uxvgM2unINcdNY|F57I zUm;?;)ucPo?1bYZyCSiWun&%B9 z!al=@4n8I%;pq}TOK_g>D?dGk#K|HNZ}_-_-MhY!q1a1 zKfq3T%Y;8&!eh-2|gtFjNofT$bD1rBO=Q284>0FN%&s{y%9Iw z5$s6B`CSD23SUmd`9p+n5F97*lO%qo@W%@-mH3r{7Ye^YaEtKQ2;L?9eS$9&QQmim z(D_RV|0wal2>w@iek6(d=LvQv;=JBO=s!^S!GgmDM++Vyc$8ox5$7!=LXVS)=mXD{ z@Fhg#cZJ~9!rv<4I|Tnh#CiOJIOV-B{KtZO1-}veS@1VOZu0QF)m<^o?sCXeBxfghXr>EzCnbN?+AV@_?h5u zf(Ha`(@mcv7$IW*&`q$9V5y+mmqPq-36B$;D9A65^85vYY99*Wl@h*)hz@J+#w1V0tz zH&2;f?ZW^q3}g&Df}I7s3-%Q(6RZ{-B&hajaQ#M{6TC(6aY3~| zh4WsL@T-FSPAld8OOW4VW%xHietebTpkNolLj=(bjjXP6KN9=}NmaXw5MiU9M5HYv zVxEy8V*WFjh1M8Clw<)S-Q2)9y*Z77AU1+h%6 z!b%^c$8wGeM+CbGD*X`OSHem^=sS>M;9$WzL8UMFQ4-er9>cKK8#qJ4N^gXhN_d6f zDT3>WDChZt7Yl9@yi9P5;7vr>W4quE!FvRE3O*(Htl*1+ZwbC9_>thJg8PWD^ACdi z1%DUh4TX&N3brPq-U|hbiRjbX3#$1l?5pOhz@Fq`zrKQHMEFHaFhPWW3=|wpgrC$2 z4kN-}MhU9BJ4L$a1jyZSt_XRS3!By`~&5f=S4j9 z{t6uRKAz(a^u2@#Js%@NzjuhxYb^V7=N-}PsR8P+xgiqennGxsS*_lC2NIsyDLF>CbGsqUtp=QKo-tn0c<=*$1L8agQ znGvDx0nK2NcY>L5qAGp{U+RF@bC(k> zrY+-3G5;4oxE0+=-Gj>0==146Tr#O&XZ*`_xWrJumgyMBUl08G@b^EZ>x(ok^JV+f zKQwvutHZzP>82p8RDia-6+>1dqvbZk>Sbt0fncW#Sx>^oZ@B;D05 z(yC6n*w-FRzb{*)V;@>ZLGsh`@Zpw>@@_?VwN3=o=?Yt< zi=g5M9wc4w7U_78=)8lZ8`L7*vq+aXNV+2=o%S<2PP%Vt{l+65x?p3lma)>EmvluK zU8^bw{q97Or<27XZ$@_=a&5uT;ui8|L*7p8<53>E=A^teE#zH>%D4?O^$*eNx2Z+C zdN_E0j1l^$(_M^%^m6pvg!%x%d@%$h^S!Qxyj4|5r-cEvJl>0(F7Kwlx$`v2!w`~` zcV7#62PjVqNt1V13wgy@RGW&*p*)x;Deu`9@>W%2e9l1v`DxKlwUD=BYpUMbBQ5Kf z^|nXkX&;_jhx<=T5FtOxI)?Mv#*6iP8e0|rN{hQ0C zuj)MFN>A+%M(v(2v!-5o*Ax4@egq$N z81DglB-zJ|$NGJ_uf}c|m$b|1QJY-5glHGnYS*39$y>XpwBe?PC9~VD$m-*JwQl6b z{Tm`f_N~r31Bm0Y$G#tXQQ2dMDt_Vj&*YQ8;+&w@-h*kqvVElCkuUb0zH$H7$Zps_ zs_oyJ`FI-|e_gl#0Lr;_^_u;+EZVSta9Q*B&lIcyQu}lXoAw`4wh8H==b}yfjc)JW zwcGLS^Z2s&nc0z7HzD6$*|~cRm1kSzGI$)NeeFOiC2z~;M?bh}f1=Fnla16BKo77t z@Y7vZx0^oi*}xn(?azxfe{Xo!0ypiqV{7-@6F2S824(|&Kp)TnIul>`+<1&O_ucF2 zX`!As>^EWyzds8(8ZpWF2dKE)iXvP|EdnAT@yStBtNdU9IfpXxShmm(`$ZC-kDjD$ny2Um4e6j82W#&4}%_7yBu^#w(oHiBHNb(<$b;jap$Gu>jrz|_;ZAGw3@GrO5ZKM>kR6!~3X=Lf;oKS;)5; zu|>W$y|KgK+XMNk`do}l)1C- zXpG=pe6N(FU-orFRd(}D>W2GUe4SA}Gkk|2X|wMKq<_}Od&r*iP3n)k!F?N$%L~3E z3b7LCo12ey7heb5S@5#M`?mU;j;9^EWYgi@iY2D=P#@e#VmiCRm`9n;yQu$*O{W;- zdegZJ1>R^n3o!O?G952qv+4ANW|x@G$>@wPHJ!@=mzmDZ5PiAnd<;8XVLE@n>{psj z9W4HX>9j%IkEZi9oZu(ZX)H60pH1fo41W7fry7NtlI1*)^B&G}j>O3Lg~#FjdS7~+ zGF0JSk8?b9|F_3^7*+h0$9b>^?mzN4euTd9I5)wn-+G*fpu|3p!}}ut<8kOtqr48@ z$!LuBI$TT|<8|JQ^19l25Jnm2bq3{s|eoex1C>2)e_!chQN`)IH8BOLx1uk$ishu5ix%?d5&Ja|>ea!y6n zt+1T!P-&&*tVMO6WI3Fxy@&6+p|tN?&YQ^L1IxkL#)p=JN3e~LEa!SS;>VV=7&EDV zTFy??*sg5nrM`yoYPK`C5?k8YPBqH@TDHTR;PzxY9ZaIP`^?_XcCLquJm7a;g_R!kJKv!K9`ZZ0P~m^~JAdHxtpR5bTJ<#n=O^fSZNOOo zVb=wmzo87*2b@kwc|*W?16JA=aCShKbp_7rFu^$m&RWz_>mE)&WE(yb$i^@4Y?DRw2;4MxqT)1Y7 zGYf5b$QI`;SgCG{6Ne@0w>XbM&xS2dd!!t?#rXxc9`~fP4w@bQq;owiF?FxQds~|J zIvruGX?vZs^6{0_z0T7}Ib*MLC+ezsuTuq>xz~9Jn$6mqa|oL7q9DE+J^`nkz=O-+ z+lzUy8>U{u1K#koln0mMU>Ohih}(%gxETklu>h6x6xzq>Jopfrui?S#(Dn=-jD;oF z@?Zgse)aBfYI>aYbjhv5QM|`Qy$XSaf$0yTsE)Sv$<-t7I-QvOB@ML_? z(8#f1ylftPgBI!I!4FWw;XxIQki&y@VEjBd3a;LY2d~5O_{_7Ba|awCj|Y2EGXWkP zi`-lDAP!d!@}NIzIiCm9Tk(no2S>tmg^EE*Lp)fGYNpmXjYy0)8yGn^!I)V*n2#*@ zJblgss4p)M-iNc}i>^jaN7&Hj!3t#rJe7W=vIP#lgG*-Nyqp?z?>x`&H)2q+7MPwd z5pMMs{^3(Fxtnlc8ulCMjc}r_8E*Jq5f(01k&H7qjBQ3j3J>;YrBIkwF1WuQl`F*do#DM#S{fF#*HsK=L(^eC$Rg&o-1k}Hjywb z5cI&c?Jf~NV_*YN4LDN84H(F>cf?uCEbl`DwEJp-*+yU~{M0T<%kpy!qjs52!7NQ1 zAJn{=S$6J)xSo+P6%O|5ia>e9&y0+`EPFu2xi$w`Y(x9C2SwU*;*(_ti~y}^AF7Ew zBk&)z7W*(w#U?J9H+H{bxudqwi`78>s*8W#Ga}NSZ5e5+@uLu=S*}) z_B2hvI!`l~>6(CbOv;#{30Q|K33jt4V4bz-SM6DvaIG^wVts~!2bD?_#X5hd*UgUj zX*XKugoyJ2@(+xr8!w5pW2d5g=No$CQcb`*-(VQDmuUjl$w$9vpQs5~=M-4nUakpP zXB?Z^N=?8zx6+wT(gdu-ZAANIO~5*L(&VRT0@mrxQ%=AfVVu)zUU@Rz*{befVf!` z@Rkoq+@cA1%b9e5TQvc1IS~^P`!-FOMxdz@#2uP|3$*sy>mt?=7$Im3LfpBLVtPh! zKfBi*5kDP^?sI>{SxxsT?hgJzEdcIw66UVD?u z7U%Rq;IW9GnR9q~CgSX779(+v{hS^=U>eRK>=!hF=^I9qCnMI+l&IpKmeJ%gHo=!8 ze&)p<;jM^MfSxgMfZftN(xvcmUv#*8B31%%!A(eNzad>pr~rZYB7TZysXvQ2GbrFS z`o!l_CMRs<4^hI5EUIg;BJIe$y>da6YKkVGjC+S-gSu6^#^Z zXUHtxQHEeFQt$+VS!VG=3|2-8ol0^7%#ZlWP(ac((+XGIFOLBl#T%&u*# z8K#R~Zx+Ab9+8hn3jPKOH<@92)lRec3$nXh{U0}rzi04OSKt$7F`qWEcSi~?hW<~P zVfqbrj~)8r2X3OQtl~ljKa3Qd$UcR`&OQ+Fuy$0kXLYh{!+wCtNWitXRyYT6l#ds<8TNG* zGEqVcuPBCu>ooyQ;Oko|tZwk^U|+^vRpCx9>Q$Fi;ol80^!3{-9In&^j$p^Uqarmx zjAMhoQxj<6Cy=;X6X@+%khn(^=K4*O8-tDqDy*|9U?UvY zHluDKcQcS3^;0wj-loJ+JrUPRBu->gD~S4; z7bUifIzLk40;<#@Q>Ad!YFh*We2(63BLYqVV|R-BDVhQfi8^sm0WZcmyJx0=E>Y`f z3Q%#~M8I3Dpng$5MN>d5>hOWpKqJN_JDw?^ENX3`fG!-$D@4Fz4+4p(pQ0(CCh9yu z0p;jD?AlBLgQ6CnW(}U&9dU<=fScKH>!W^(rhw5=hs)Z5I#$=%Oaa5AR!5Av!BQl! zM~VQ{m|-6t^;0wjOo=-EktpyaXJAKV3YZwR8Y$p&c1%ZzfDafrChDhX`rh=Yb20^7 zgNAK4N8QfIPv_0D8>7}%3gFvS?53#O_wbbs_Ux#iqN%~csPioa3}-c-5N*31vN7s7bRX9b$+76r!b`1 zf71eBsB5Xm)tYd1yfkXH!<9~ODy@CFNW?l4X0uU0^P zI)(yfaqPW81Uv)#*|$dh6wS)NC+b{50o~C{*!M~0v*X#uvHt-fOmsYaz`%Y;26p8KWvHyzt znHNj(P1N}(C0^Pa{5~zft*X6ID;ukG!3WqJz7hdzIs5!B>ZfQ5_$BIeMWVoq^wZxm z1^gJbhEc#j(S+=uML<8+=^s%)MN@zsb7oLLT?D)@=8gd9w`i2Cm~{>XoJ`mB#@rF$ zq!1=oWMSMFH2a;tml3 zuqri(#4JCI9pnR_b{7$FS^|NdF+W99KzS^;2NDGiW0x9@b-EF>DFXV%oKX}ol5M2a z6&@_?k3eNCK+zO1FqS);0w%Na56u*ih&dNf0AC?x_ZI>C2Ouyw7NBUV*(YXQi^Dcl zqYXt->adveC=LVrI1-M?ELUC3`UG*oO^j=ha!qD~9~JXc6a`F(IR_}WBErflvtrh>%)(!ZxH*!=hByKz z#Qe;hS)3HhwXsAJ*g=z?lCpi^N|x+2A(%xDhvQYTPU%^k7<2mI?BH#jBCT-s2~K9e zw>lPJ=FH;kSneEV@hHu6PFfcCvQE!S%YyG&v(L}W;*6McA+uOc+ngy`oW?HXf>?l= z(*c&otm|;thDB+^%$V=yn8OF81IJP7rD@i?Dgxs2H0ymz_r4<2dh25rAD0epW8>Q> z)_aCM(v>kkGh-Il#?)S9;70Zl*QaH1D4Y4Vv@Fgm0C8hx7FWfrIn3fEcI#Uui@T`p zO))<+XBKzFoEvc%SVAwnGcAk#JnQbXELM@YCo_v%W7dnzVhH=7+a!wyc9-|Y{LGwJ z1dqj>9GE09sR#JSW2x(uMiNhG0@o>XNIazX~9z}cwY=VR6eX2DBy`$Z|mL^g`o zV}54NEZ&bf-8&NP&E4!O<+20 zvEZL-0+Xbiz92r+1e(WA`scqi;p+W%%o+ief-kcLzAJja4#xf>=4Xkh_qQ=;CiQ-i zh5L^d06U@J|BhMbQ9v!T|5^k*PXXV@{1naV`z_{_bk)`OhprqfB&q8AuO@W$9nb_W z`Ibc$CEcl@=e^4qg^P+(41oh9hiUrJs3G;;2ezA|-~|?#GBk zOyH@~uu5ws1zd+YraeLgyiNVaRr)EK0;W_tn%hXh9@!{>@FB}D?i^O#t1?E=znHT5l zOJQat3S7uO;l#?+7TXcjaiu2UfoH%{_Q{&S!uN};nbR}@C0^y=dAcUxaOYx{WuKu5 zbXI-Y63)^DI;%MR$390BaLJcB%RNsMaLH?#;sQ-TXzB3TTtC1;CfUy1=zgm+LjU! z*g=EdqzS5I+E=6gDe-IC_ZpG7g5qzk^fNE2bXTRbjS_pa`tA_{+@ zUTM8Ri6?P>vO^?J;ymPjID|-iw9?`3LO#B?W!O8lfNUcl-?znrn05$=hmH?bS{=}x z1$WU$9~OywSgrr4^fNE&_)?`a0*PE5Uumi1E}ey|<8zhPLQ4FMrG7yq{+*t)yVB3R zDDmw|XA2Hp9pBXgw2mKU>iBx4^*ALOtoAoW;vXRdKCbjLFOC{}E1jD$YY7z5zrNDl z6-JF7B)-uE28l8f-)aJbL^X+hn!q42gv5U|fk9#I|0%HQ-mSpeO1jYouCdvL)6WD0Fl*DhEz=R3Ylg}!xmr>539YNgZ zmG1Q9K0g9~RQhQq8UtJRCFrOEueSxC9Z$`GJ|p310>bYi?%aybG2n38I$8@rQCpK3s|ge}OyY1& zpr{>5Owa_{RU1y4Cust{)sHDAYXa>mM&d|Kpk48el=jh@K)V`3;#f_<9fy->)CAfU zA8xmsG=a(2G7{4@frfS}iDpfpq4D{5dzL0J`MQ9_98F;IwVA|ROSW5-T);(efJ-Cu;(O<4+_`)r42oV?*59 zg(?cZLh}xjdi)iguf00%XAN@#p(O_jIJ%w}PmSSx=Z}4XCZKm0rdY2DsM&+W z22DWCCz;WvxO+1Re2K&DnQ?0pN+J@)cj;?71Yfzb-PN^y4v z$g!=Nt!}FjycmCuSzMzDW?|Zw#jOXJ#eg1&yCUvR317=a;M%yKnKO%<1XaXvs;5*{holq&b zh8^l%qW2C|to>-*&k|AZr{hi?X19T%n6%l?XaUgslYt+ z0($4s!Y^n7dJkl;@S-N5_f8ToX##pbg|5+lSre|_kH@V!P$_sW^?p+H-VMfnCGKa5 zsP`Lj=Q-;Abs_k-v;gS+CdZk#H37YcQ_XiY0lj-30^(gwK<^(pSiGkRch=dxVbmyC$F#^!_$(wZ(Nya4lzN{}H_> z(^h}P{VWmn_EtH!AyHrq9nG#vUB*4g`pMP=^j=27rwQmio)zY30(uwG(Q-5az3b># zeoa8{XGyfu1oVE9j+UzlS8t=r+D*OBr`}mrZqKmYLLjfo&k|AZP?duZE5b?WXkje? z_WqELR;&r=J)U~E(FF7^quy;b0lj~tqqWn7>uA9$Yck{qH&KZKQQ}%o#5z>@sUDT+ zR^@D?5(#?EAzA>G=t4*9p$RB4ijLM(6Huavr}WZ<>u8ZG>jmb?jXk@Ib6 z$WqGODhpqUH-hJJgx6mU|Nvz`KWqW0`lv<6V=7V3VQCQ#~e^pMjv zf!f;5-fOKUP+RBF57%kJEyamd)_qjsyFA3L5G8JBX6IJ3y- ztIq9$DvOJ3!B7Bk7iq&Xr_EJowsjeR-8N7vh2!(ezhJo^P_*ZL9KA8|Ha?m2)=pT+bH2LuY};fFAjlDr-9h z@OdwLy9oG4R|M{=@>4Vg{JkpoZ3^J)E$v6E+zl!dI__W}|ClCFR7kwP%K0xPme3g= zbaM-S!#aArD!{xb@!6`}K3Mk)WHH<4MF4NRP+7dBCAx)ts>&IM#6f;##Quj!;GL9U|!62ca_x< ziP})nHk8e5eyDOT0GU62IPRtT$vsoueb9{t`&kok_6R+3zb2r_%^?uK3IRug3=GUV zfr&5{Wq#LTSBHI7)?HL|G3HG6cj5(6xR3oum7m&CCvU>(49{|PvJud_>%Z5}S0zRa<+9v!IO#z(~&UF+pkF)fyiR5h_teFl8>sbmYrXe~d+IJQ)-wp#BjTRB@BUcya1^biz+j6fhn2 zPXP;=b#tcm8&Urh@Hka&5&@Ho5txPg7Xc@r{wd%(I@Xd*0rOG+6z~=Omo&NECR!2>f}O8l0K1 zMo<91BVeB`0`BLSbV0&T(X_$lgfo)@4(Gnzr6K^mBdxwZVVy?-UD*aUihu;K?6xHQ z6iop)B%B8*;Boe^H)##vUuC^P+@j0mO1vgvy-$gybl2-dB6@CI3@7}|ixTfjIPKtG z0fex|tR=#Is%ZXuH36R<&ziqqw>x)+a(luWjI)D$R?FTYS)5I?J(%z_b7rwK;T*#( z9$`=ZgqDaiQ0j*h*69?`4wG2>Q4#PtP4HC0Ptg?cQo^~N0{D(M`<0Y{Ku;38G~v4V zvkB`pN?h9>anFmy|5Byh2|x3q#CHd4iEt3+0{bsd$so_(yh+8tcpMBa9w+E4YUL{YW# zF_q}SW>BmJz!J|>+cuhj5(7CCZ>tID3@6O5w(P;k;I577j&Sj~pgLldyRk9qdg1Pb1Vw(6w`6#Tzo5WO|w7Q9on zwS`(u>Vmk=qE$b32z{&l)R$UCtDW2$XvNo;+Lc-WwCc)EF0Kh^wE*)KyGj$#Y8Kl> zLKD#HvQ8kXH36-z<-pKi6RuXJ)m8;E48DT=?Q+qo3)|YjYCrX*R<+g6B5HLw8*;rC z0IjMxrZ;GUTCp(<)r4CehgDmfnMD{g2fIeH=tV0Jul6%@W-+eXv4z<_Sx zPY?kdAqtEvdv3LLJ0+;d`PJda7&r~F_OfdKQX_*g)zBK5GwjTP$YjJzWCtj0|h1;4O=4DmMq_95O@9|`fU z^=?J#;f)U}^0z}k_YiMHKcq-Ky0O>gdW3jydCw4U|Lz^)J=}eY)UzC+Xu(@Jr*DXN zVV8w?D|LB@_d{0{si!*nN7dsZ(IWLw$AGBPCl=xj&+#JlNXO8q%C#!Qdzcd;-iTZs z;@!mkL%bz;V3B&#;}kd5pb&4_Jv79-Y7YzXPT0XA-o08=q#pUW&6Pi-=nGcR?XGTh zA>N)kEW|rVM--{2KAv->jSTUo&{0L|(T{grO-C20M?T(lC5;L37S3@+>bZ|E+_Mf3 z@g~giA>K(jp-4UZaUfdo11vkSs5iSqBc{qcHN;ybn?k(baavI&V>-Ao(~AZ()G=0Y z8qS&#;th@SLcDQseuy^#E(q~XzJ(#CT2wTJEpUc=<_Sg5vLkPfDLXC>@qW9dA>MJe zEX2FVP7Lv76U#%q2Wv&qYfO8;d*;fb4;XsDJ@cfZFBy6;R`4w}I3<)5!D|ePejxWu zOx5W5Mf?nh{j8h*;?R7g*ie+iX7*-G)!4=mZ(!OK;_X12i$aX~(M^3xhCc-e_@c(Qo9&SLPR^OI^HnX4s*O=F2(u1VXkbo@)rNd43Di+6_M)= zb1^E<8&)ew-Z0mJT6@D>i3xg(U!tm)x=HiBVJ@!}c#E^yAKz4^G%oapxd2k+4RakK z><#m(yx3d(7SH^~J+qBB%q#A;-Y_q6+j)!IP(UD|G-&S)^D?u8H_VI0j@~dY`8s)v zKcRq%L;+QZc*DF38Vmsg(EPo{9lId%*o4wx2n2ww^A`6aJ13#Mq~2Q`WAJ!4QG>Vm zFb3x)3Qk8Y4nuA@XEkyIobD|i!N@gk+BM$d2iQlSktlc=0xrxZW z2jhh@-Z1AEk9flz&>!`NIp{v-4Re&+=`H40G3;5@%0!QQi+SghJ-b@j@dj_!T@#upLuX6^$=WHRgcJ3uaoRZ0 z>YRHpR^SXHXFaMNypeMvO9)vx%Tc@dW#z05sDsuy@(RaDP8SpezrpP;g5CKu@z-v+ zUmZgl0*}Cc{CWA0=UOxd-we<1D6%IXb5-B6{5!#Cw}gB%W(J)6v7MHJxmf<4n`Xrx|-W??C3erq4pJv&Hblk=}Qq z=Qo%$JG&45QB~+$pLYs#c$511u0tnm8Xg~7lW()8J)U!=PDcNNk~m1}9zd@*|6Y9@5-fT_RGm6f@Fy)(Mc3Vevihki~Q_QyXuhvC}V!-wtZMORsq2eMR zB`8_;5WOUz#T5W?h*wpwoHQ_Y^}FMj}b@-L$76{e>OA^S)C6FC7*!FQUO z*P#+NF7%ylwr(DcqKu{G)|vSiAz&1Zf`xn+n)%lwIQHMw4>GSe zJ*^S2Z^1uZ<21Wd*7{Qfy3LQkbt}TGSEJhqv{o(eCX`5k0O?~M>(2SFbaLn+MRotdOK{*gI2fxnACH3wG!R|9(kd+ftW z=9C~8USQ(waAWh=EZgk$m>);|vivN&c?U%FuEy{R=Foc)=yNox$t=stqrQDm1BO{H zfmfirS>Xoy_NnTN(1fKKT?Qd?K2gtG$``Dr2R(WG;_;shvVu*>GfU}1@h&jyYN?~)cQba^%KJ1;V;p= zc(Gyb3(y6M(eV}HubOs32Wy!8N7?B!tN)Q8mB!$3Mrb*5888>*K%5fC9}Hm_gI0i9 zh)^^B2Azoj-|EIs;SAbu&Y7b zg#at085s`R3gRdTnTWr^4nsFLykh%%fFlfcrRGc?4DQP_vE$9n-mV3t;0B>o8k8# z3JOIkGCXT|HEKzdzUC%AY{0*5Qm)!Sqzv z(n8SZ${1ddI;j9BSt-$l$SExt%7q4$U6d}2L|Db36vY`aAlfhneyx;8xSc8{+G+a? zvq)Jw6u?&Lh3goAy(yp*>I8#svZxrmLS~OPu4%ehDwD3svr#8BO*hd-RT1^<9!smU z!`ckQAaY1L)gCU|BW4Vhn&O8GdX^;f?9nCy8NEuNqiZAPA5l5=wvwr+Z66UTb=cRB zhT1Rlyr7wH4=%oRNE<3zl74zt`2HbqwbFDM!j*L}$_vJu4-E11^eO%$t;x`+{G2r= ze6?J;NyWK%U3OOS`XSIgsw2>EmzamON!L3g|H@=6OvO@V#KuKCWk%7YD&1_tCBV_C z($iJ9)Ywmr`*(o0svMKTCKOF($zKJIvW&8;j{(lapJ_~5 z3s@)gRY0E2Bmnh8f0*`Tzsy+TN%%93353(|mxs^cZZdrb+8)|1$5`F@>ioZ{VlgWE3cw8@ONMZTSV$d&Q$;V)#IU>qcxQD6NJ zA{gJ&3ZT?4&CF_CF(&93B8&9@oVg_P4j+@5BZGgMnL;S0LuGN`4)0xH*Ov-dPWYQK{rhI^>l;DrmM08J|!qd;k zpJ`0t>CfYjDTuD9DL7I;uRc&^|Ffvc6m=o~Ok*-dy^KGKBD$g`<4FC`At!$a*K1O$ zSd%DhFa9Wu_yhjn{shV;jl;CxQ#htK*~StB-gPxo{+brf$5~3Bq`pQ%Krr_?bi zq!q*kFm&T^0wD)~UgKci;3hgeJ<;JU)MYdO--^xf)C8dj-N@p%vRJvsG^iuUoeWP^t!uidmP4k*p zl+K!6TC;e@vN;PD)-GJ!+;4I7g61VnOG@z}oyCNTB}F@>9=PjGjoStb3 zJ{{9EuXM@mCd4PRtY~yID_y#9;k@ayo8~N7QaWq;^hU}pFKdi8R+LqgH<6;n zf`tp3`!zRBo71nntR&ix(Itq^h$@}qW?wqLX*yK?|6PqGE0?5O;{TxeS;Z*q|6S>& zO^fD~!lm#(-Dw)~oIZcaoF%1o%_q*8-dsAqeoXy@nh6K1^#AikJ%}>%r!RwF&-=e` zg#XJq!1tFnEtt;l9=Tt^n2zqqP^NB#`9FiIqHg#1O>A5n?w5$TF$S$@_&&r5p**z@W+in$g zz+o307G&Y=(`M>~i#<4@xS%kEIL}fOXLwpgB6hiDd)}d}Pz3LTvLmK7cqXE*JJqxz zwrTkymScCfTH(;KJ%uIeC>Li{gUPjHDiOo2ZO?KD?d)*|g0HZ;K$rdzt4oR1qmR|4 zt5r7ID)5{XL0ow#WOcR!Bs+Dm!k+FWR>X50^NCpnkXqEks%D7-q$;hRpu(Q~6069w zfJ~Vcw#|Vkq^EU>6+)!taUxd8vz#{Q>N3y=i4ZO?qa~23=ay9^Rynvfo?Qmj+_5TR zb)q_@P{y=6m9#vpunVou9o;l#C=Tr5CdXl^73rta(?q#Y$?-U*)z`8{n!2I5}1^t!kR0aTu82dQ*VC|zh3bi`p7(Z4iel^{tW>X*e(rHJ5$ z%yc1-B!wUaZO|$u1@%>uk@&r2;u4jk?b+;w_cL4hYX=>~b8 z#U-7X(}k$!{!mM~#$e?Dj=jPPDovx_EUTU8iBn9=Q^*WFk9tbFS?yKaa_v#AJdqL> z+_Ux+^H5bmI9}r&m~ueJbBu}dc#2J{%riS;m6uvwI-&9b5S7AtHjCrgq~*XzU&$J1 z^|DP*u*B+JY8?`{dUpH1$+5aZo!i&yOT|glW7_h9a5qJsR(duGF=t{HcG~q0~XWl$w$i(q=4aWaN z+k3}HRi)wMcaj-yE<>0w1ZfIEkVI)oX3`Xu$)rLWDFoCt0#Ymp0%BKoMa91MuGqVa z*!$YMVlS(%T^C&yEB5d6oco-a35&nq_xHyypAS6uKKIOf-t(UKob#SCcbZ$1t;zPD zIZjV5m87G#r2~Q*TY5S=6V;7Pjk_f}8?mBjGiq#^k!WhH>1l4Q zsdZ|q>uXz_j@qV<_Tp5Escp6O)G0+Yw)J$iGQYnv!@3DDCKMOUbEgPc%2S)H^ke?bAzZ>z$q+gkj4odzL#5Fh_SM zK0+c^3dXA2+L1&-THAW?O?j9IHfd~3CZ{1Odiwbboc0c6S(;(UWc#eP&eooeWNlAd z0vY0C>5|ZX*0gOM_-tJ&BNna^rEG+Cc0)E+fn;q{Q&&@>y(ih)QrB2-Ki;`pU9!nm z!D5U-bC>oI<~bcT$!Vxtr)fq_2R@dr;_k+}#-2o*F(ZVv_{B-K)#3y)P1W4hlJsS1`ZAWjjHfTloR-!W_)1>L@ARdn_838dJ@Ub z#u>G#r^%*itzDfxwKJ2owKcFqM{8TMxw9i}DC_}8MWeD{vrK@FHOKW!vy(MWXE#qU!L<>ya)6v@1j;cc`(w~MTQ#IE1?LGWl z)8d2M79TusY5Tmniw~H;&w_)N&T}B74(5kL`ySbeDr!b~O;a<~g8Jy_Zcmp+?$X{; zk1YI_Vcf=eVo5nXvA(U7{)P{tWG%b3(>I#vl73C2{h+2xjNf-88#~(YI?|5znpsY= zp=1V{L}$7j%B!WTsi~)}wXubs*+GfZjd)t6xecCUU9Y;UuCBJdr?$DRb5@G9S|$@o z^cHnJrV@?)*`j+on$Tr9X#dHso=!wbPIVg`bs8$fXx)aA<2GfWhGI2Yo2PNo&h|u0 zM>ATy+Df`ywbN6IuvXgI>x?_swy?Tsn5JZV34PvN_)zND&(}20$S7V{OHFNiT~li} zOjQa~6~j~n|NlB%w|12@QPpM3`NL?8y-YzHTVcL-_D4O*hD1w!t<#KdCXsG3>1L8{ zCFw?j#dWo^a#MA_(JfaAZDB4diaxHf&J<^!$$!yeG;h=r>KnCgEoLhO9b;Ehx~pzT zwAXYe+G~3{8=Gs(@r-RTM-!d z=t^9$*}~$0zeF%`ZmL4yu63o?VZU)Q?uV+vqLdni5hK4W)7jY3*lge zU#Y8YhJUc#DT=6WO0-Nvqo_r{uD07<(}{AMVX}lqsh-BJ3^|l?{K}{xR6-YqqMk&3 zXAI-LZJX`2Noe43*l(XvTT@nM2J0>k*6k>Kx+gVtW$j|3i;hlIT}ro_(i%n;Cdi?5 zJ8ZPIcB7N)=xS?gnuSr`1UyDl=-9}HQq$55_cp3-DQzs31KUTUx+B$*rz!_=6e1jy z9wQ>l(o+q4wQCZHr5?@!YxY?-d(QszOqbQt+2ka;I$LW{;&cHRA)vN9U~j(@z!%Lh zrcgy||Ju$5lm#ZM#gN*g{(G|l)`V9bt#!pcHPbtLY8w2wDiz-NV+*RNv8FRqwD}l3 zrXGDfBS2$HRsjmcA=)3P9r$_;ss@1$`xdye?Hud{djZp3l(G~E+RO;xHxK0MkFEYM zG}B3%W}tNJ%o$_h18_@}+Vs~YXl03-VmL7@(p=lzoxq4O2PUD~uyrk(5xebu7WXV! zyfhusSp$^xFivZ&t4qgr41*XsT6?BD8nj}+Q=HM-)CnW}splqJn=ydH5zN4!5w|e* z``?JLxfcCx4?LyCHWrK`D`(E*!O<_NpF zHjISf%nj%%8k2s9Q{C0k!PXBSfwAQeX4qCgV)CLT5r(zU>ybxEO7NDRVo<@L6F2R& zwJkkn*&-RmJIqwW`btV3Yle-BwU8oBc+`?GAu*KnUCB54vV)c^+5b?)2T9-4I@@P7 zrTf5)h^`KHYLbP}Fj!=UWUa`CVXcX}w$KA&L@I_iG&Qk{I_Q99`z$zM-rfaRpj`^D zL*ZDBexT`xg>4L*f=AX-hpmvAna;(SS?TuRg8E6Wj6g) zGs1c3jcEcNEjwWG;=|^_>p1N@XepP=OvF^5>Yp+AAO=7KgbpSCXksQzq)aaewaW%Q?5PYewpf zL9ZlZ&`VXXtwQ9{h>_GcDEnCS{hX_o$1y{oJR6g8ob`UJ zYGQ6X@o-QqHVm6(y34IeB-89>J(~%!7%6nM)IsqKi}rSJP6pYJG+`RfxemMR5d#Y=X!DMW^jp&e4S~WJd*Cl!op!AefH>Ud> z8y}ng1j_`=m+o)t(Rd`<5=*@Il4Wxa#mWg3LN=-L`z2+s*Vx?xxWnP@qBr^8^!<+tA#acHSJW z%p|DP?}*FrXKC-0^%n# zZge4Hg#}a3%F>q=>B}nkz71m$ew!(>&DpkRM9**xvjCORD5w_~V{8YJ;Uj*(01v^i zg%zlb4=Dgmf6DJaGlo!>F5Lpme8WuDH&-fAgDDA{ZhBRtw_Bsv_Pdqllqu8UZA~pz zPd%_Dt!{6uZ|KBsQAeu#T71y*B?m1x(GmJ|6MmZb3bU3*G-iK+!ITlMUxF%?$_VT1 z${G411c0^xh~T?w(T^o&pf@%vFti-zO0ZY58_kX-^4AGE6D>8>voecl`$CT6gq#pT{zYbzTM7mxwNf$I3W_Af$#KEi^qj$>E88vB(i72cG6PU)<8b=W-wvuKq z#{wQ~%0){|VYMNYUSP7ynnuIL8I0NK0W-B$Sl8Xtg;hwzX|<{5Q0~VCrWN$`)O1v* zif897Y=CvGn0m2KK_CI+`0K>IN5-Y|4m@byvgI6OyOUVqLNfH>88fkJ`1v#i)sArh z^nmaH6Ye3kAK|j^G3y&b_CCB%&!^HZZ5&!r4Fs?;J56R{%3uY(Cl_!zw&Gy}*BZ^# z&)k^@?afYoOIJa%s;YoH*Aq($xOZJ#SsE`WS~_q4d9#y_t*t%HiI!QKiko1J-I{%##3G%UdStHrbHUhbM);GxgJtuB+dZScoqi=V6V<(qhTeTsA+35c)gfm3tiU+D0zJ(~6mCfGB<}2qw zY=$=ur)FPpI;<#|p}jNNh6POSMQmw|m{vP0)v;A-&!O1vJqSyMSO!C(O8i2Vq!*0L zI8>M5qN%@WQEVktS;C4aj#(ydFYHc7ak*tG>_tkUDrfI`^Omq%H;$sv!Jj#q*%n$3 zv}m8fNfRJF#Z5=SXt8aW9oc0EYd@?#W3FV^c+3b_$~tBz*;r?%`I#2i##}S@_qy86 z!ksaD9bB)Y0fx8xEbP{?Gk~_uM!(tSl^Jem&Qjl;rD*!?y<5FmA;7kt7A9qs67)&_ z&Jg1`E@3yK+ZJU_SYl0BQVG{%{LN{jEpkSG(ksI5nAMuZniCYZ@gSC*Q79uU9QwPKE)T|A&yb^zwN6$nY${nLrJ)p?8 zN>J$3Wx9T`3Z7!q^@}y}6q~N!(sccnrgs}`0G(*B@9L$0o4-$v*5uEu{P{1dKJHh2 zJl)xFtdgy5caSk|U>Sw|BX$i4b!M)gVM5x&^j00+jh)E`D~Rj%W}mmz^dtVLfo6c@ zW*3sXfVPyebd!jcXgx9gFm0|_+FW>sJ?3t2XLnt@@%u8r@MU!- z_QR-k09y!mmpfXm!e&}VtJQUAO@qr}Y0WeC`Kv+0c@e;@Q zibf5qTs&R4IOY}TA2Zx1Znoe`F~p^krR8ZnbM-6lgN-!$a{-$I#-ikv6)+SO2}hw+Xvgz2$sTUxv78_Xmb-5!@s zIbZgBK$~xBCXkw4%lSA-$ArqRdUuQg}{tBC0hy#(C{$FNza+> zObh&_iFPghfU+%!iMIxf%5wfD*bw#tip+GjTQKsqL;CUirq>O$y- zTE^y`)7g$+CuJvB=~qZ)x|6d_)eIS1E*OU9KY8$HRaEk4byO1jGf`;fTeK=(3EKPY zMl%BGTC;^>))H;cVa|6nE}n+qEs4qDQpB-b7KP#cO>?e|V8)A9&ydT%NLwL2ji!}K z6it^D`|A(rowA+ll$Rpb4R^q^=87I5|^6TV!N}Y3v0`m#ALMj)bU7P zis>m8uleC)TT?5$m(8C>i4)+K#IF-9@VnwYYitq$K}W*1(aOU5*eQ3dy4SStQMBzBSqIP02h4BNJg7h5g^A9-2wD;_rnrFgM0v@MZ(g z^Z*`5i$aiUcH+1uT5FD0S-atcAI}jq;!K`tC2%f(P-|tRZBu2`60`PK?971-Rx#@n zouEHgRWPCE42^2)xW>nEo{no45={@FMJ}h=th{bMB0z2`ce}!t(#9TQl^JSuB#?WW zn7i1G5;jrH3C#I7<5bp8USOtwGEEJ*I!R;v1WqYU|-@TFkQBCw{MJR*U@;DgMDj z49dOg(K=#R8~ntam*c)W>b@I?+Mp4Z+VJHIzM;XNQ=?bbemm8Nj_9O~Kw1nwoZ+Qg zh^-RoEt`xwYG|L9IyTgZ(@8VUinfu;rAC}Q#LOU7T+C77;Yvm+f>*%Fz28(Zw0zo!%Dy-^2#v;`+br;N=VE+axKXk;iG& z9S3y$DYxmu@oE1Aw$(DDo{_k*&hHIULesm*rQAj4(y2Y2V~(Oj7?o$3m$8?~h|z2? z`#l7E5_-y(798j8y#NOa{eA6>s<)9Cy3mqT7n;a)jxDCBc53(u#)by5q^tw0P{9`2 zwkbB#+M1qJi_`&S0+6vsoNZ5GYtoaTYzkOSg-26&XejV)B8gyr{n6mbvN6c zrWY^Lb5Va5W>!*o&@Uyjiu;TmDdiyo2agaF*wUC~@61e64^qov9M{v~M$2wIA;I%9 zhhc-i#U6RKA4A}uI-Z*u`P=82foxqPI$(2Hk&%h<(ex%~N<$t+#!yp@XnylkH1fXQ zOQ!z8Aln!CYfJu)td7x}Afq^AUr76|n~lg;<8;Gdd$5fwrCw%%QY#Ybt<6rWiMReY z=J&)xZ{YR7m+P@Yi&=3jBRTu#dWnA=Vq97sbsYu|5yi28HW}# zM`HYw!Wo+YSoSlaOXh}pYNyR~6g(f1IR!GclyRh|r>$`&rk9!~*z#po2g+)KP;(vx z6BD)NQnNpiF#y|RfEZaTQIWkNL56CsZBx3FO<9jQ^DU5Y;29)E&a*l#2gy~9CP zg5BUVLB9$8&ESe|$Y1BG!9qWmf4KW&W@GrD;lCfmn((f}3_&VBr7$oQ}hyEepmu^e_HFi6-t0nnOSS(#@6*M`L3P%_C9fL%9zX zbby#`52^-a!f=X{j}GpI8S7{GA9GH19rmzaTCJwWY98gWqd>Yp;aY)B_CKv7eV*Cr zwF;|)75W1>hP~Ng7CP|%E`Dqw z1l0Nw59ImZ46>87)WDQXat)~4F8J#3h7IKv_?RIV(Qe98nLPx9Znk#BWIDfV?P=Np zcWX?v=6@Zq_qPGlM>vej+u+`G<^CCsEpCxAVoB+e5k8^s^uM3QZT}|BW>dz-{zghG z6Pl%#8W8TAo+kbE9L%&Z+?!Pc9^+AmVGrTpWEYq1F!b3^roT5~$I@QMnXS*+okTJRv|k*$rw|buqe}^Z$-fK{eyruy@p!9XH89hF$FnfIZod4I6PFg%?4-rAi%7n z05_kMwc>kfZOI;XZfSMer<|| zxTdA)!=TUz`}xq;egg}Am1eX;eH{R+NIoAkowp|D)>+M2BW-nHecGS4!T=50JhJ)w zUQ2(aa{gID`z#%y;Ou#QW-c7IQ0Yb%oUG4E9=7@>j3YAL-R?=~X|MO#Kd=m{{fb$3b@ZPf{`uEE<_vHDT_)9xZv^G zt2dX!H|RjlG2|0?uctGcFMV+Wcq6V8s+`a~5#uj@k!pb3>}B`Oi3alng93x`1^uCc zVR#AW)`1aO+Xf~gkInxwsi3p*kId)UeBVaKU$)-=V=26y*IpXT#``w-E~NAy-oKIY zmyLIC^nQ*vPUAUqp$)U}oHqFy|NOtqcS-T>KJI3pcTM`Vz4;Q3^j|ho_s*~PUA7b6 z?0MM8Ye*HFFH}nZWjnc>rO!3#3sOmPQ&+seuT_}mX)=<&G|vZYc8|BoW&CCL@+8W` z>m@V(vU_E}_@ z&tl#CpZA;-bWi_|!rqtZp8gz#J#Pi_k9CM2aJDa4nd^*MZudJ{t*?x=+1`7Pnco}l{Up5&;`5n1k-Zl5_=>H*qaEiQA_|FD#yEZ9cH~C@ z3wV#`^NDzVx$s)yTY8=kdof*5_p~q5^Dk>VpU>LXm(L$PU^~hx#49?9MSgx+con7L zQSJ1!EFfP^PQ)W83+^$B2sgk-3_n4Lw=SFeYGJ*wOSp${wvhEsxhsT+3t9i<&lO%I z2ieqg|rVpKTKF494j0zEEQG?cM;YI`JP$IX%o&6?jf8b zTqrz1xLkOcaHa4#;mN`?gy#t_5nd_0Ubt3xhwwh(!@?(p&kOnLV(R^t@IB!t!Y_n; zl`+$868;yp#=`wH`fgM}l6+X=@DW5OMU31NerwHqXEy6D09>Tf8eT4@K4-p7cLU65FRaDEj(R#f$$0;f0mp1-Y$GV_=Ir1 z@J-?kQX>Tq!(Vc$4rR z;Y-2~h2IH72(_8tR>DFd->^-dKaoP*O}L-%2;nKhON9RrJ|lcX__Z*Az=-mq!qLLG zuvR!jxIlP_@C4xn!W)G537-@GNBDyfFD5nljuaLP6T)`kT;X!zvBGnN*9h+tJ|%oh z__^>`VQzmv-x0z|!YM-j93bs6N4QM5N_e*LYT=#2CxvecHwb?b_CrWdxkbVA>gI_5yEl8q;RqD2;r5&$AljUzY@j}C{td8uv<7^c!ZEY zqrr5S3D*iA7rrX|Mwk=z(+?Jo6;2jT6V4XiDEv~`7gIy#H&{4HI7K*JI7hflxJtN2 z$X^7aoX3Q(2|pEX64qlv#&mq~Fmbi;Y~fA9r-ZKwzZCu<%)^9(pC2!*5>6K`5*{Wz zL&#qe=I0(1J}dl4$f+=&=L)wICWI}*`NF>mPZM4vd_>6K2By5vgh9M0p7#TU+Y4)j z?ZSP9#|h6A-XOeB_?+-v;m<-B6FcTJQdlfZ2>&A7SNJ#KnZkbv?-RZv{8$*kM33_O z3&#qpg{{H`!b5~72(J>Z6Fx2cMEI>RjHL(Wv$b%7a2Mfj!Ue*kg?|^`D7;(vqVT`M zpM_EUUJ~<}DBMZdA>{8V@%a(LvxIAf_X}SYZWR75+zNAIe!f(=tFT+ROt?~blkh3w zYr-#ueKEJDyurdr!fC>p!X?7L3eOPUEWB6vvhX9}_rd|lgZYdQmJ92JGlk2Ae-+*= zd{DSv_=WH%;Q%ZQQU12Vn6Op2hj6*@Sm8Osb;1XQuM0mD{v;e!pnQZo3a1J85FR2t zR(P@SX5oXv^}_ds-w3lu`T67vi-kK2yMzY{j}o3EyheDJ@G0S2!q0`j3Ujwr{Rk%s zrwFGD=LnYxR|(G+UM;*+_@wYn;RfL^!hWOue76x+3G0M=3Kt7c5}qeqD|}Y?rf{PW zKVIYeop78mDeMvMFI**DBfLrYnD8~>H^M)JgSYeZDH2u*rwVr$?k_x2c&hMH;acId z!Z(E*g}Gz>e1-{2g-KzLaDU+{;n~7lgbxU_3w?Qc!XjanuuC{cc#ZHj;j_YbgkK8( z5awawj_q=kuvC~7b_(YSR|xq-@ci6)!rO!o3EvcM5dI?Ux4r+lZG=_AI^mwe#ln+> z=Ly#e9}>PK{8Gr@`KDe)JNQ^7oGRR1xWDj7;iWm311R^Df~q^aGamd7-5;P zPS`D6C_GenqVPiDjl%nd&kO%8{8|_o@8=g4juys+wZa*~1;RswCkQVP-XVNM_%GoX z!rz4bC;0h}6z(K!5bh;BQ200DCBhqoj|l%Q{6ZL<=*u4@94o94HV9`4_Z1#4JXd(7 z@IK*l!gqyV37tuPeglNt3S+`n;U2=}!efQ!2(J;|C45ErzVIhu-(o+%;llC424RdPM`+*vqPI7hflxJr1o@D||%!qUP(bm4WvdxWnEKNS8V99-t-Ge$UB*eu*rxLCMS zc#)7lYtQJWP0o z@Mht?!k2|#34ayl@94|jPFOCi7p@YXF1${7kMK3&hr+y_e0k%ARl@1QMZ&{`X9#Z= z-Ya}r_?7TiVg6)aez9<8VVCeg;ZeeKgx3fk5v~`0Cj3d*cV}PzSYb>!O}Id~TzInZ zV&UDw$A#|-e-^sC`0_^zi-iecyKt`XXyM7iD}}cU9~ZtZ{7e|!)z4>uaC_m7!fC=i zgo}hH2+tATEPPP7UigLZC*go8etz2uW5OC?mvFxDZ^F}r*9h+tJ|%oh__^>`;gE!% z-*&>Cg)Kt7^wjhZhYME=*9dPBJ}i7$_>u5?;ecvi&In<-uw95RdYOC<7M>-%O!&U= zdtr9cPd{2%A?y|&EId|tzVJce$HH%gxi!ALQNl^Wr0_4o{e;H~&lEl=d`|e2(5?05 z4iauJ#8=-vxNW_k zu30!&c)ajR;giCTg}(^LXMFK>cyvhaA}Il>Et zHwkYQ-YtAk__**5;k&|*gd2n#g}(_SQ++)K35N?u2@8c2gfU^2a93fiuu0e<+)X%J zxKOxQxI%cO@HpXV!t;ce39lF4D!fnll<+m-N5Zd#zY6RaBZOmw{P}Ih zO_jnrAzs&Q_&LHQ!lQ&I3oj5}E4)MasPHA>d%_=tInBQO0m6~O3BsL(jlyo>4Z{0{ zPYYicek|N5+@{6PXBu&PoKw;LZo>VAhYF7qo+-Rcc(3p|;lG5R5?#mnLHAj$xF3e| zL&7i-_8qMI;lcv(<8@ywEEAv5eXX#ChGLkVf-$-?sp>-46Ltu@h5HfFeisW@ z2+cV;@TchhbfGyH2mT`6|APo)-YUFD_<+!ydxPJn%Y@eoZxsGh_^7ZC+uabI z<3+o`rRf(6h{(T)i1HN^VZTZuJ0BwMA;zHTpK#w#_qa5CzOaA@`D27eF535a-UEw? z$Pdd~22DQ57s~@C|0zTWtr0d5p+}Q&HOm9}cM~Dcoa2JL6H!3wer9-pY?(8W#6sv;GTU({F!HKk?I>H-2nRHf`Z`tbdj!ebRjM z6q#qv&9kM8sq@5M=g-Z9z4<0eeBWsPVie0<&z>`9>AV$A##6jMDD!sq(%AG+I)h4=>-`+rSGzu!FHe&FmM+}Qk82|@bhksLi+F5>`-=;_59`0@0DfOcNX3DF?%@A<*&&s2}XUbazdHg)(p?Rg` z9f<2pc|6y?rE)Anx=eW|XUHSZd@28I{L7TbbMZ|i^k?-u9ru~?&VoGlA*1jQ%{3+O zPF!coyA~BX2Aut~@@@r@DeqCpL$fyWa)DOAmvK#b)-RsL1^W{FXXU*BB2(TgkXHnb z`Z0#H^1i?|<=H=utG6Ncvw!y4XCN}={R(+A;cS#Q0ROB!`iA`sE}gTw9OqN(v>DI( zB2i|#!)G}T&l=l5`>YQxGV|?x(Q)=dx=~2Ta@%}|BAxvVWwh+s`@1{#*&tkG%De4V ze@q#L&uo<;Z#>f3&rseukVl`ifA(1sE;8kP0eOE%qEYxqzqb1Edl>dJl<_6x-A#wn zpMAC?E;8jE@mkuiFbzn_n<{zqIsRR<0OiG6v;Cty{_EN--B(vS4wg<*e>NSz_rYuX zH~A{WsP+cPa`10YB+At9M(DQ}_)+*b0{?7z84sh{mw+;VZ$KXB1oqG7MYO)mXZZ-| z*MQg-*ZfC$YzNFU!;PHVu63M$g0p{C9(^%0UBA~I=V<#7&+O$={3aKFl567PNd^2X zsVFY5EH15#mEyX%xFqBM^742=K_y<*Uu;tD)%WPyrn*4DN}|l7lw9hww#+=^Rvi9{ zoC%CFw#}}~s~fi0l6vRCaNoS!h6nmIb^QF-jh&lD6*~owd^;ukFPnnX1}@=qCnsl$ z*S9ec*tjwg_}&>cZJ|>zaOIMEa-%n7^&>xQ3ZGPO=vVC&oCv9b(NC^BX3EsNhXuoZ zcMoK5T$#-N-Wlx_T!3d6to!cMOnG^?^;?*=A-iAGhG4%r8?v*qHuTGK3YdRiqhDrP z=KaXGktFjEjLy5Qb;E%1ts9!Q?zeGeQ@`(>@o#SmPI+ow_RoQhC#?%?$WJ^q>=u-& z(evdEFy;9(y`QGuJLIo#{cdG(rq+44J-zPjh0f1e-)x(V_KOC6S#KeAW~w(9KDF+| zDOt%g);R@y<~&$=dvLWgzG=NPD!FjVH(9m8SoY_SI#a&MZkqBjDLT{P_DH{ig*A&fIkGnEd4UDaUNOx90xODyM*daB1xuz4GYyV9nRTVB+gw;Mq_A z*zUbgQNQm6rfj-BSVt*eeVg~U!02PX&0Ag65?eU@?!v}rmP{G_%#zr`KrFV`-@uPv zefX_&7G`h!W0#RXpZa^&#+<;&roiXV_s@CnrFFvt18YvL?ORu~X|%KT`ka!yg=ehJ z`)=i~tsA1Fzgj=A?@Q~lKF{8|bJO@GOj+>V%Cg1Z=GC8CTLXrl8sElGe(+*ii`c?} zw;=DGVtY}Wl?B<*=gB41W7GY{opW=h&_8o-&z_dOSB@!zQ;>6iXM1Z~&h6>@CASC0 zu3DRQ!@|0Lb%W{xXWq2Q+3TiF{qnNTu%$i@GPh|ABbO;-w{Cc3$>U4HD0A49c|&&V zhWybVtsDBv@W576N7qzu8r_!GF$^7%cBk-O{PfC#ekmQDg5cUE_j^-=pJ(T_Zz|Yp zcmUobszE1n|PvtPz{~!PRY@zKBgMk1#seUEs*#>QoNqUB$tU#a63FwQi zLthXaH>47evI046h+VR>LMLE^&E`?~VAW6#wpm$j84_m&L-&>7$!v7w!PcSs^GVQM zihd+3Cp2Rk!R5wKFc{)@-tp|S=|~<##~T_l5S@$@It~Bzxe)(lk3!cO8k1i~7M-ut z=N7X2VjdDI&fkmdy=0%je{LZP;G*&1ep>$;=$P|C6gN2`On(A76FQjl?^x=|&f&TD zV9qOe7|Qt$Y5L^c0A<~r)##*ia;D>dFNbGv`sNh1Ari_t68ZPbDMYThIXxI)`{xWp zS02g9!Pu9V^UhF24>>=3B}S`xOeF8}RtOy7K~FHbkEv@E(JmE(my~D8q#TZ}2$B`7Yqi zfjZv@yfHOcwGMbUph!OkylY{_O#$y16l!LccQZbBUzT@kAr5qBd(#RW=Ret=JHT-^ zWP2s3x6iY^HK^h*vb`Tl9p}H<-uE~L@MX3ag;l@G_I832UuS##`t-(ZZxamI6!eBB z9j7_yP3(tYD(F2`=QyoFZ!)H&Z9(t!CdZi`^vYny_Mq1R=m>iK!#F-4^j>O3)DiTy zfeB^=J)VQ?4tmq^Y-Z4#0diK*n}@2~4bNch-GkoVaO^#T9#6Wg4SEf*S$@c?fmaO* zd6QAShlIS*sI@~w-fWcpu#i^()4d(?jz($U33<`&uqqt#=0NLzhrCOm%X=YjL7wBh zAM);p@*jk}08*}Zy=5r$i>~(*Z1$4t@#M?Pu6Gd>e8u&?hjm|dy@vp=x!xZr=Ii(X zit>i*bt8v2aR(Q_Ckr45B7dV6F6wFcQ#V480_tXyMyt8d>Cu6_u5z(Yp};1 z=EDYiOVPLvAMBlhBu5PPK6M@E$id#o4;5KnrMl#CsWS0UIpm#h$R&LAXrI;6By>UfhXVj`CtTvKYvVY!oM-7x#}wo8!g3sAg*2_iZG`8$q1DFClRj zFCH4mQsCkV)K`!fPs7xX3DW)b8WKf+vtsFfh`I@Vnsd6Tt#%8w`wa^4hQ)<34Fq zYy$!>7jmDr#BdPU4|Sih#4snaZvkXHYl)#wWH_3Q`@D#(d?)h3a1bw8BI-o$f^WL( z?MLv^i0{!}-4`v9hg_PG?Ms%3IFVwi{)z~GrF%fo{b$g71I3E&0PDLC2e)Riq8Flq z-PePWw_zQpf0p}6aOf#;G{5Yh1;^h4Ix7H)rtJR-j;GbL0{vC?4K_ut%Kn8V!YccJ zEzwtH|I!kk%Ko*8tf0!i(GpoI`#1I@0hRq*OF)?cS?&kHLF=G&bRb%o`%$onN=Fy4 znBN75v&;@^_1)lr7m;Y-JoHcQd%@8xh?CF4W;y)>ZXh(Y8m-wccy?%V5Ysc&eL?R%readG%?4&SAe7C7AwK9o#oa38g~N!)+VI*PcSvaD zaNMA+{TEMpXARE*!8Qdhy8J2q4@83&*6|9rwlErIzULL>?ot z%o4dym*iK0uAvU5(irX4e>(~hgc%ViTsDep_V{1;C{P% zm?io+kxwEZ4!1{*J_vmcYw_ej#y`CD1Ooap4|q3AApH#7axhep&8* zg}Hx+X`-e(UQ}3MTK6<|aDOcvNXycGs|yF*fZ;Im!%pB&v;xp?{X*g-OTd2I(Q!|< z1nk#_c*8x#60qN3ra09Su;11sPO}8;H;TmHEdl%S+kNiomVo^xFvS^`fc-9JiZd+% z`(24B%{|K!u;2A0&b9>Xx0b{?mVo{4AaSlGV88oFoM#Ex?_m<>Tf(>Bs>0m$FwI~y zSRE((JqpIXpl~29OOM{C(EAirKAq6Xrzx}OyL%Lde#P}5dix+sVcM$-bGJuL`a{As zg(IH@9i;d3Y_fZ;CBQ<$Wrbb~5=VRJ{Z|wYXX0oDN1f{mBb3eBTUR(>AJlwgeF^y6 z3QgZ^MxED4+-?cf-rFSZumo!F0}^*y0=4%UiMuR;+T+Q8_ijs|_P!%=k0nrhKa;rE z5~w`~k&JtvB~W{PNZfA;)Ls@Ry$@Idwdav|&=RP0ZUF4Z&1LsFD*)bq z7m4RB0sB2b;sr~V!<=i(d0sB49kGy3G*zY+K|FQ(^_X>%( zE#cemiNf6HVVbCkU!IcvZpPT>zEe1mmZeAESm=F>MEP_=C!eM?-hXLf=x1CHqPGvC z6sG;GFt;!YTYpst85;^mn&^<;e`gJd&n>~+gYHL#UK0{W=d=8u6b?5r*HU&#Ulc|t zo3;0S;eZ8*sw1aw1^&mv(YJs$-hVEMO_o6IT}ay?>DS z)e@+^+e!Rp3Dn-bB!0I9YVRQue^>&w_XG*2NQ$BM4uOVlz!Ipvqe*000=0J>iEK-t z_D&%Yv;=DJED|A0p!Tla6+|CP;3>R+V`1*eFiq6h_S?ddG)< zmVo_UA~DhuzWw?Z2}SA1XZ2_h6D`5qgKlAwHx-Gai|GB^7x|IT(0bfV zDvD4xYp=3sz&!X@WLxq(7NsMfA`&}U0<|}h#AHjL_TnUVwghT#M-sbO0<|}w7{soY zK<%|L#S}}R_GXYsSOT@T2Z?G+p!VjFNLm85*PkuF#uBK#K_qG|f!f=eM4cs2d!tFz zTLQJW1BnJpp!V>hYsYQ01nrmQ#*1=KglVG2w&g{B^GN0k0oHgeM#(P3E1yI60&x~gC~@D21-had{vTrwiN)|t>u*L97`ZE zB%WFn>N6BV2D1hIT@r_)Snjz+Vdh1Nmlk<3B=RL*ZUtD0S6ITAcwtd!CM90n4j~sy z;&)t9xw0tCyqx|;?ombFO}NZw(KS~;xhT36_6p=v`D}kGe11`M4H5+NnSIEg5MNz1 z;s&JaDISE zcoueeBZsqFyV4S1(JU`24UK}gMGxY$OG<|@adh_`adTB^_yvfeTismhoqS6$bYLhb`nGg^+D^`&7J zfPVFQsdpF><#kcOTcy75XH!7HeYrGrDFq}rsJ>e2yZRTkxOuxYOwknZQK@$?E+c~& zM1EogU_BWE-YX5gM*;tefkn0E^W7!C3y0E>N*a2XOtML;8#x^FDRSG7d{ zPRH*jiG1mSJ1`bzUX(aI=6yqn`*R|)O>dP3$3lFkOLPqSK6j`DOk*XCjD;zh0>;L? z7!pO!VWOhm0=A8X`0|&ic{WA@!mOYPu`oqbKs@Fxr+^b+2e-VpfZ|x_ddi6Z7p}8kEX23rM9)A;-9@pj zC@y+t32qLHg{ckm{9DZ9t8pTH&z-wUrOw9S&M(Zm$5{ehYW;W+$6LGL)5zkeScosu zi9R|R&sNGVKl5gFEX>TA#c46`GG=iT8^!4o5JV~VV-=p+TjEKv5GRb$+gOdKNa92` zjI&~4=0%AY#=LJS@mjXwi>&|{YGMM!rIzq@JU12^QUHnP)7s}t;_vLa*2KchixRJi zd2u9)+|O|CIxE0$)K|npvnb&5?eOd>33y>!+}scgQ#338wwQM=1@L`K?j5Rpc09Y# z(eDxwK*w`GTDE(S2z5MbW1;()#Y|T8I=Kg5h2!2A3o~=-_(;rqgISz_>UAIMt>c5S z&~Fql5&yXlNylG!^F%C6(G>7P%xgjmh@3*fFQx@VCRBlVSp-f)N3NlpzG73Ls{XMn zh}SIvaj5)fVxa>eE_x_Cjpvl-ln8F#h=r*Q^L#(%UBW!G*=2nw0raowRN~{_65ol1 z9-+j@1U&nk$qA4Ih?p;m+o1l@qRc`@#@z4_#@CQ4>s03U{8w`(! zDVhSt#JvwGpn(-PRsvvEYETdl<-oSl9me6=wh~a)f}5gvn4&45B%V74i6UFGOO3@x zUI;oM0Tbe0BL$Rj$eiR0kMetFZdp7+(G)N_o;!~M_UZt?OK$;{aqmP57|IxGM+un4 z@Nr5!LeW%nTs(9sE(cMKK@>%)4RP;YTt?=x!B6d7u9|r0Jv@v4&bqBrxh|WGo2Gb} zq9~vv?)^#uN3+hmdJAZchenNofKd$gr%S*Q)W16(rf3S-Gw$t-M3Etl;P>h+V7GW^ z4h0;Y#Irpl;6@r|PCQJ}6tG|1TSEb_uyb3K77$s({%5fW#;8BCu`h`aUxN>tQ;D$3 zf_R8;n2J_1`+bzf_S0~4U_8vsnZ;r8+-&qkk-;?S5oy~;&SA-p62UBLIUFAyADNlO zinzy@Q$?@d3C|Ak^@%=Hi<_142s39E$H#N$GmB+(yc06Acr^s#q>L>1#R>Q1-dP+I z_fBFKt@Pnzl|>H?bxJ(K%;^Bj1l+4LvY3pB z&%LI17MH|B^O?o>?AF&Pi^;UXwec`BXBPj6d)y|7>_RWRB_oS+j%v4NWbqw4vDcU@vtQ@Pq~`JBbGoJ zG3mHB9vY8NM+xp? z$$iBV_%y2b>3HZgX0d{y%CjoPTsDeV<6&mbEZ&KG+ZG{Zw-taaPH6`5o+XgQ zi8S&1mcaOt#n$tIB``#N2tn?LmOwbY9Si=EB@iSv(E1-+0?lLObP%6d!q@xFc&Hwd zqSHCE_?PtFg$4X99%hNC_g8UmF7?i5;WkhT>8gFmT_3<=?8L|K?MOh*`7=JCyL zku&L@MP;eUVB{7i+`$s)&Cn#aEel;vi6-%wGCwv*a99{$7G_?Q7%TH0pu}SKon;b` z)yD{!R2KS>0`6tsS0VxXatN#_3sW=&>{90C;dx{+1y4x}h|Gucy47XF)*u~Mq^Q!4 zWuY=8j_$rQo=vtA*)!IZg_##6HkEnPDY0V;_!db-08ar8WuX-mkcHmWohkuOf^pl* z!W2ybGt0a)C}0P6#k)y>qK(e7(47>(FVea*B;a2N%iX_}g(;c>=9PILQNZ#r_yrQc znNcaniG6yPX?9u28xM(RF^HHeiKCeHeq~|i#dv)=%#1{lGDc7<%CvHX<=3&JKpbib zc;J`J;&4k~`8B66h@&h4B_62*@mEX0;p%fh9AgP|RM!-h#S%~&v&bc=f0pbK`o_{Se-?RdD{f9L3$x6$)wyNfA1vADEZO;KTd}sz zEDMc++-MP(B+iy;exQJhP~8%6C8`^VBKNaVT%8sWsf&WR))G_+ONpp|N?b+zUM7jh z^ux_{Wntz;mDZJcS5V?qR^M$B0H2PGLzn5^ZY840K;q41p(iPEU&beECGpI5+}sI= zki-YdyzgG#SBZ(){b6zS7GcQVfv&=gmm%fhwvI4A*|L(2h zt7V}FDDhQPg8RB8-cx{^_shb}i=)PdGVkh1(D5%Aq1`WRcZE^o01{tX0)xcCB)+l) z28opZ1b#z3m+mZu}2(Ih-ez!-57VN0Ow9SlQqErEhCs&e~VVk@IWpge>hkaMDZldzjz z?kh2aL2O=mnCel9q2;+prj!_7o<4IpoD#RT1QuIRtU=}8<&^mB7(5&7=N3ID3pXRm zBg~5uw=2(mFD0?i3P2qjiA9z`WMImZdAD!LQfK1$7#)IW$|PSZpM{Im^t+r zSRNXNM1!dLAZEsVW98m^AboR|SyR}2%PnE^t*`{_YwEPh61Glvv;_LlpION}Spt3N z`z-ZjOJED@fbBu-YzZur986*tOJECYC5c@vfk@y45>qUJE*C|cR2~W;a*2LF9nVTs zY1?r;t1b_-&@Ae-a_`z0iW+Ax*lY!$s5_BpwFHVRcDZY)c^c;?Y=lt|idWt|2kc z5@={VH|s921cI+SN$g_@1YZx5*v}FOzMdel$P%c>7f39&1nTj15(ioW_4scR%PfI< z{4a;TgDio1%<@1SVhN0v{FO2Ha7$otjFLFg5)3PXZe4lkIaE<}KqHaMOmtFtdJO*^U4(mzC7^dJQ=D!IsM$&43`;=G5Q($Ohu;FxSttXC z+hfZ^?T{aR6^-3JzT6*fZ!E;k+2vuX$6o%Ta_{d{VmI8nmz4VvAjh`-TS2T5!O3`- zSzKlbW)X1DD-YeyEDk}D+zZP6kZ|7!ZZ0nmGjnEfUAgxnv*2$mxHm|ESvd^2SCxl; zpn$>bim#D?`eC@asXR>46mVO)cLIW;$YKtFcUTQj7n9jb-DwFZeF;l>NQ9*$V|S^|;FMHo@t`z(Qif6eN+-x7Yo*OrHFhDy=7Xp`3v8A zZXPHPvqaSUv2rhg336l|E8qz$0D7-Pr{z9r3FtkQ#8Z}l-lvjy+7i%vA}#!kC7}08 zRG|B;C7|~plt8#-D)OF-`i zI$EwJe7&8D&OIsF(0d!|J{Fl-FHWgv2MVn>I$Dt>pv3w7$o7`-9j%}u^d$4#k9lsZJb$GBjH?J!8|GPB;c@3a zG9U>)ZUrFE7a8l6Sps=p764Ih3FLX23!=gjDENW>K~!1-74{M`ajPtW3fpZoh#f6~ z3OkOzxsxUQ3Y%CFS_ze+*N5?}Sb87D%qCZaSt9D4tndb6UgPUsYXw-n>nvgQuD68M zyTKAx??y{ly{B5j>OIX8R_`WD_1I1St9D)S>dgq-oI@H zeufnQy=z&6-IjpfdvkU?%M!jDwN->JWES@^i*{vk*kIi3UJ+*I%wleZ_aw9UqXGOp zD*##i2hZIFmhhGCsR;d-5)Wb9nk|VFig2^ABFwxfadCy`VR0lc=xLa zO~kWk9sOmI1f0O;zpNrm(G+l4g?B0iY3Kd*=|FJ}8vMQAt@4Wgoh zD4W@QSK*xqGOxW6XQ_VhKWR=MTtMZ1v;>@e-qs*CSptfzC;;)Z2sjdCU|_Zh0=UPb z%&+#|*Wv4m5I2>hbI{h@Z{!7gnQ^%yOzo&su+keb#p=|jGCeLEom@*;opLN;b?Pg^ z>J+vKq*Fh8@9X4LhLXrGx;z4%vMT*C_mh#h$*l}iTk5n`rPqT*kw>e+53vIL_Bfz2 zw2A_5VRtZ40_Ib|u*xt+Q^2T7Zw&?HF_+Pm!`6VNp;rSpz<3hi-JId(pYzdh48FufxS^|xQzgOc`8Rt^+G@2}{7PZ8ex|+k51PQk7SF z7gDJcD6P_0IC>c)l4NCs>QbqxmAOw+sTL+`vI3ygsdXTlErA9JiFK9Ue<|^`0G>5S z;`TIjYh{FaF;ToSl!Zzf#Ig>eY-ZC9mjW4inj_pS8Bc>k2kIZsqUKqbjF&?_cdran z6a~yh{Zqg(oaxT%ZT%k9KLy-Mm1j%9Rdj|0sDBAK5cN+1OA5d*>n&gr>YoDMVwEqJ zfC(|&9EAFpfFn@<6cC#R{;1wXI0W^dgn&hC|A$Gya1N;}QU4NfLZ!DY5=AZxfj_CY z2FF&0>M5Wf!`R~`VBA>ToKhL4XxiZHN^dR&1a|;`t^~jywEF3lq16=dclLK@O28$U zAh;J*hAEl?uB!BIr-0*8o$j?(1NhfX427?^W%4CnRvCJW5)Y+MUm=OhvvG4nWte$U z;<`$22!`p%wzzd~vl8JxD@TL4-4gKW7g_Un+I9yqQ2OS|(9ZaD^hj3fT4nJA?S6M< zn3*$+e^z?4n8gPy*~3<%-*E4%3>`%QqiNCyB;XB>r;k>KDVhSFtMqQ5fVViTzK|9W znMGo~C43iuvNE)u65lPvv!^AIO9Jjom0{*ZiEmYUUr-`{HpPA03h-5Wtui#A76PtA z5#2W=AUp~;?^cE>ngTwl^bSO#$TRGQ|6>KfN*n7zY_J46)N9!;Keq(J2mVBr`-LS? zcNcOD|F0#ojA1{h44p$I9;3}Zk`iAbs&v1q3{yQS@k6Ee1C=gpBphS$;`PC8}&DmUkvxKk2H8{^NiDe8H{-_L7Ju1#Y5k#=fD(NeJ`b}*$QV0X70O1nMVIi? z`O2b&<=na|%*>g^=qhhH5=FKf0De0w09icCS{Z8zWHFQjRG}qc{ee?J6j=fVpVbG% z_Le}w%W0Y&Ea4Y?WL4;VYIQavw^7pSOm+z4tHRWmTE(h7zS=*Mq{K2S09t)E6-2ou zpw*#GASx^Yt?p+tt+WKRI&~a~Doa4C?I>eMOZZw%stQd)hEcxr%Po;s2NdFFa#fi6 zQmbT@w}@Kddtx|jY6U>6wcCKGvjnudZaWb5mhh`%*Q(GN%;Mo@JWD8xZD{4jsxUKW z7Hw5tHrzgvHw1jU6@VfuCyypf#ee+@mVA4+R`TW9=ycyRz-i zs|r&z1uU-ej->$ZSGfmDKn|V_#cNjgs|wvf3FhIVs=@d1W;KGm%m?~0-A*Wc_4mJSaBb

    S&gZfEf_$D@A2aX+w#;`+qic|QyL=u*A3JbB1-K19SD62Qhb#9^TVXi5ZjmWiyvYU8bp==4BA8Ha?M`>FN3T4ag!a~_qyKkZFgk4lv zS!`M1(A?>;b(40#E>tI`n|0Xg3onI@#==)|UJ`1NJ5OoXmKMsU(B{xek-erv+7goO zEm^N?ms$&D3uk+%S7d+DPc18yO_;I5;z{@oq0r%S=ZA{Wv(Riu=p->&l`75$7Iwi# zSE1~8JScRo+!?3utO@-@Oyes<>+sat!gpX}W1(yu+*Bx=0DB8%C*S5m*^aj*G*U|7 zTK(i9p_6CA)Lp6c*jFg~?FI^E$Jy3G**&(cP&RlSS}1$44hx+pc6aJ04-Z`-rn~f$ zM})2u)7_P!ClP|93S~ppX`x$1_C%#h(X&GLis?yh|GYxk4|PH436cGwQl;31g|dO^ zqC(Nv#Uc56U)Ddg?Mn(}htFl9H$_%lrNX+sPe6S*)ty&>YM9X`$?$_<3kr2(m;~=qCv4b%nAW;`-2cVsBHG()10XEGf~w zRUv6>Z!DDU4G)Io`+ZsGY2P0XjT6)PRiQ`V#-oL@P2hz>S?hl>G+pl8pzZxGR3`22 zja8xhVejQanP=TyDC_NS7s?v>p9^JO`<>8ydFGv}&{`C~cZ;MjKjRQtEru zTO>=gPkM`FQSupYk*qMj;2rxbu~T0ix?7z07Rh4VZtvLJMS4PY=r~B<^^Sc&j3-tr zy?y5`l9ir+dy8bP#qt%&dWh{Sl2r|luSgaNyuKotbNBg*WY*j7EBYJ=_=;p+H_KNf z)1=wHBAKXkd_^*M81xm%R9ud)NM^QjePf>%4-c5D5+cu6B$HA3z9Kb)wp>+f;u<=X}xc3k2JhJH7b`xePaj2c(AtA;2V3a7=K(7 zItHoO2;cC`aqtZ|-Z%CPxp{)NdxCH5mkx|4)`V_H5}o8Ll0n3IzOh${rE_(#&-WF{ z$lwCs*k6hCD(&lqzOlE9aYs$)Erk0bUy=0wZ}AmLm;F{>k#wtX^NoE#>^!a=`i-wh z`pUQa#{Rk((wDXL4quVju~d_~fr-|s7uM)v_!@)l-@OwpcA0B33U) zX16VGl>@sqUU4I9fsK;~oj=P{m%m{dES&+JTh6PKaJHRW#Ncs8pkHZuo&3pw&v{3L ze&=&Rz_Foe^nCY{d)dx#F*!~Rbc$c%S}e$MmJ4#7kKmV;=k$sx-}0Ud|2=W<-y|5f zpu{j3%k#5V!li}7U@N-=XFK~~oITmc;q1-61ZQ9NjX3+WAI3S5{VL8`*`MH?o$V`t z@7W7b2?n#{IOk;d;GCO%EY5k^7vr3teFM%zoGT0AzU}-5ux&?u_}zBig2`(;^0WCq z+c^TM;J2Oe!{LkVR03J}eLx`Fb`As_+qpUqKH1KlK#uJ^1LWdI1A#o-`5MT#o&0=w zXFFx1;Gf4?4A>q=eF)v-^uy%!IHvkXMtSgHz3dFd;{eBoFS;ohWMPj0A#}F0Nd}V54`!EZ(;KKouR0fe12yd z;P*RcARPjJXMdQo{7xT`?RQQC9KTbB>>Bhti-8=!(}7Zw>vy)ol;?NO1oHjPHNX(R zGaYpXa{EHS4mcfvC*T|mcmvMUC{VtDb2?1^fU^S#1e`m7tbp?uG~(F-=M|WofU^OW zOfcXa1LOppi-6pKb9FBK3pkI#lpkK z{8`Q~fIyaWACQ&hyaZ%tIe!J5Eax&*Ai*r>W*{fac@)Uaa$W=SvYgL={46JcI%7zd zvkE}@-3-{-&I>;Hm+d?}6#iv9c-aSK&iN1~f3`CVra-n+2V`YCPvC*LupQ@3z~eYy0A9y&THv4K z$XBTRj#C8$9A_zz(76Yutf2F2n6iV;V}KKM-bdXL z3_9NdIYFlY)kSX5nGWOyorOSt(CGlMeP#4)_?P3HfO^8taV`TqInK?1H^+Gt@Z~tK z0sb84Ga!)T1V+HW9A_+$o#T`PPL6Z(NcflITmj_dIJW}1InEP6UXJr7ke}mx0Sw7; z^3dWV@-m{abDcSWC)cS5yt&S5z?bW60sOhnDL^3C*$!moI=2DYxz0oA6F9lf{-`{H zxlSLDlj~F!!^vFdYMAnJojZa2T;~~JNUrlTDhO!#L%_~+EIjVXb4CE(JZBc*%X8`g zf1V>RZw65916g^_NkDd<^Ao_ybFLZ>|MHyMft)<&X&^Vx*$w37IbQ+!c}^}yE<^Gh z`4lFS^KXEi?|9K8^5i?C0dKxj0{HTsDB#a`j*|4tce-H8%6AS0vh$s@0Vm(7LRu#qc6O{e;}{m z&ll`N2F9O1*Z}R~FA$uB!iK-BV9Zt*vY%M}Il*1}A{cyYzPic@-Z4d8;7y4qnHU3SsT-nY`L+^ujC%lR1I=>&O^iaH|r`K{` z87V2`v%HJY4RQY9l|%@L-SHon$b+v9{YoB`@Ax`zjF&{SCcIY-!<*yfhR>SldkXY^ z;f3r^-sf-~_ztH@4z%yQn?Jr3v95GJ82ZX;JlTjiIG+_*`-wBP2(|Nd!EhLS6Q;&t z_(9#t4s8`fmR(SZTe+cQQMWlm?1EJ=4Gryvf}N3e!C^2JhGwJl;!M!@Mum=+K4Z-7%`=uH)@g3YUEEHX+Y(iMTY98Zrinjtf}LZGon3A_V#IB+HPLr13^@-W z?>H#G!zE%*Kr;Sgsd|ECL+$;UhQW%0U3kozuoHKJl?8G`vO*R()%(FD2&=q*#G~WN zp}k<(E_xY;X@$6LcNbz+7=O8i@N!>BRR12oM_PjGy^dS}D~A?~eEJJ$NbHf`Jh6Qv z4tx7v2UymOtB?aAuKAaQPwwGwW)Dh`J=&Wu!9w7%f~2!EzD)x&^`_ zZ~nP3Jc;8$5z6lusDK z;-*z{0WzZf0xaGHi)E)FSzwAv%9cs=>=!*zNw%_yV()h}3_+`AzvPKZ)+oOo<<0)R zM`@+}4OD3MtDZt}4QVAm*)m;TA+c|f^*OBwd;5tAsQ5j^1>!Qv*1K{28jhL!i#qP| z6iOwKkBSdpN3dpoA}YSyQz(y3gJ2Sliv1AVY}oS2X%Y_mK9B$BKSD*&gFEsKwZ&rX zH?)?e?82JoQro{$tUZQ18)4;O99G4pFy-RHD<=u6*gFpPs(y|;$HR_%X3eS=d(&`X z%Sq}+&#!F1vU4f!%cs^XYp!G=#L7~ihO!^>IIoC9b&%c+3)kbQs)FGKTs$LBRO|~^ z&%uQ)C!~*MKkD)KA-a_CF4LdgT zL*z+&l=gNsvcX6kGsod%kJiF!Tvv)vg=sGxrlk-x;jn6dEh+W6oy}#9`I`UVOSE<%eF)yg zVbw;*!|E}qC>5(Hy^)O4F?OXy>3dlI2FF5G{*JL*B|+_FGj>V?ag2SCl)PyuTjO!e zbR>qS+p6TPgWy0Bw&H2~3@yAEg7ZbF^6iPu_5}o=;#g3O&N>`9Fg>I0qkS5YgMKCstM*(p zKXyUNrzy&(=5C{c0=q&~AirWZ1BWiA1$K+1Y7Bx_91FZsObhHax|r^B=msp!!5#Hy zkF%%ldpabTa~>hldOunGehHbqecpOxP*sD!UoKwB`b9sEI+cOmZx)}n!+e>@)~s6( z7gq1WlMlgsAC5>qB5Qv!LK+Fr`3FW;qHAS;IYPSop7S@TW*a%e!f&{v$1E3^A=-Z( z>IrGK-+==%yR2F|u_51A(G@qE;~`>AS~?%JBrlKamTnR*ymCSfshaJ%u%}wO(Xca8 z?5UP+9xiM-DSM{bF2ViTVn;XI3vuCj5GUJX`_C4Kq}gtOg*qIn*weo~&wqx>u zoK#ZzZ2t@>P&L~}!_MJ2RAj`4Urx$%G{5wj9(ks$g@!V2zs22|$j6(eWW~CCEudRd4Go`3F&W^JyNVp<;vZtd{^3gyKjP+ywYzk zA3YOSclvVG{e}ynHaT+U=QJ!XL%$VA&OZ3g#4vkmekjMAUzFcDa+p07oo>$*%rq^8 z2+xnOy!rEBuQsPCglxb&*+{P{OC*753Ryneo4+t82e!0r8~3uO6Weh=qD#lQ?#CQT9Qks`Q6f+P>0p3&>ePdjbN+gWHhueFN z*2gTPM-tcb&U2JJqg7(1(l@xSgc}P z3a^rhiTs`JGqQ8Kr>O46!HbxES6z+-cV*5h{|ewLsLknM8h0Qa%FG6iaFdw21@;nz@=@q z3$DfCv%av~cgWR^`UcMG50!-alSb2Hl_ssoHE+Qo`TC6I!GSBWX>1GUt0&8L2!F|1(d^Mm8t7%)pdE&CsaDgzjQz3dE4rcN97S*3M4A&;mm^B z{G~s=4no^nmU?>GU{C8Ow*iMK`!T@@>as&{G7c;g?|Ro>ge&zYpB9ooTg?NA0Q^xFQgsIgf5tB6gSyrE=tcYQ)wlbg}Is+yNTgn+2GX5l%NLhjOP@oIJgE({| znweVbMjAYG~mF4Vnb&Gc|`qr5zKRNbpZ|urtm==>E75Plp{^( zRf5YPbO-ZhNN#gmg(>+b8bMG6b8u*F%atTNZU~knZ{Wi9rxm_TU@R?5swmwi>HrC> zz<3keAyIo1zjlKy0)(pjb?w1si9XwUqiOv>f|@>%)tl?00V zk8$#a9K%l&vV;zs33fkaK5*i#eYwf@sr zaz=+#DOXsG14UafNnOSSQ*h*3TcBu3y#Z_D4v|O{kYmJm$%B$U!a5~xuLmRyX$1f# z_1R|qV0>QEMqKWs|7m5*uVl+-3HPXBv{g|h(o$e7?U}Xnm8F=#SW4wyk4jaMGf&_u z`6uy0@e)+y$gJhGJ<%DS6&OqDVUP%v<8Z72EE7#}zMPsYIhNA3JY-vG@t1Lj7VeKL z*B^!o5+H%NJ9vQ7lwvHU2Pl^h4-(%=+Ihju|Bds;Qo8ea4u4vqF@dp^(m6WjkWa&b ze1^07lS)Ly@<QD8%R5${<%%|mA zZ6g4PKH#UxQs|y;v8Ko-B^9z%MJVAc)^>5`-w04{qy^gC(#i4vw(v{7Vp)?CIe3Dm zl{I52y)cMkL_SDaE6~mhrr;Rdd97dh6i(7oy7Lg@PiLrh!7p(P?$S8iK_~>q(w;79 zOEF`~wmM;5{Yi&MGNx1wl7obcaHN+GTZD3?3B5`nMLoT>v@NOlrHM+j>Y*s6#GOY0 z64JClc+?{eN|>xS@Cjzsm0J$6giI*Urnzj{B9tRd=v9LKA#{hV50Y(et1zj*v?4Ak zGPt63Cs{sVsY-`f+EdX|c96FOI`z`3e{opPy!~ezuz;3bxgjuFuYHd~Dnm0QyTDjV zg+??kfB&OPXTgHDXlfK4W_eIDuKbD9@+YNP{)*LESCw)p#aaHUHInw0(0n8LAZgqa zEz6(egY-WMkAy~ws1%?PILx2OOYjrn{Wi*VHAknGfm!~9Ldh1?fe zGmcgq2jVyb$F(@jpV*P`%YDhRlD*_ujpHaB$KW^t$4NNO!eRa-*Nc6zlNqldElGIg z&*)*SHvU)j`T>;fwa)h;we5f9<8!k3gSR;BIde+-x=PmdZz<{TTT{}P=-IqwbKihf zvSIV4?vk#J-G`N|-%t|nTf4QVcXMQOU-#_3?%wYHuKtql!v^{U<^2O&*Y<2~@7sKE z_nLwJlK7Ucz8^Pi?M-xS=;>YGzHw`RA{MT0sWRU5^sXuC+R{@3kMS>_9t6)ft=S6S zHvX6V?dsc95^0Gy#S>MUB@&gArrtFhx329@_jJz2&1PYlDuMYgM;Cc;psROHcR$wkS!(C3ks^)a1oNB?QnM=!B#n4LyFkXW;M)27Y63B&+0v|_Qj4N`vV8ev4sC(ieEukYy} z=DxSjQs1+=7dPRb2??J@J#8eok5RomjH1rlcmO->Ex*w6-e}u?f5=}H@CI$a z?cG}J_XqYG;kN_B{YB$&Jqec~4<^TO*F19p*3kT;hxtRMmW|ah+xyF7iy>Iz zebp*nq6BvwI|qU>0q>I*93Ado63`YQ_ZRG)bQ<67PILO#%IOjQDFM6KUnqfT@lOiC z!eoEwKLzLaIyj->cxrU9f97O=;okmnW&Xl(a<4 zOpptNKx}8@sRiDlVi@NNms>}EC*bWb#zPs(y2~pH#@`rstn7eylkFes4T-~(M+^`7 z^8?<)Z2vI)PGSIohp)rt;IdTGqS#-Q(wI9jJ{R}Bj_r1Rme$#c7l zknSV=Qv*nH@5W;P6p3iz5 z!YEH9C;3OoedJ_OrGK`BC6O8C;jlc!KfMPYhLMW4IPLwh?eV+ngj@V@NUEfK+@2CB z3l$ckVj1Cm`Dn;ThJ0TC1n-sb%v)Gkf;z?nU%h`i+=jf!yGzLf^R@Kx!)<>KB-wM2 zNYnfyap@rBLVutFwV7~V_292??JW$Gda@s0b&2cFN`K*4f7c9ncRy-T35jGkRm1IqkDcDfRaUQ%FlB@zFjXn-Z)r;V z9*Rv@+P|r^D|FncwD*nD#H-1ERB?#bBCSUei5^1}(iAyWDez?Nh$ztZ{{2YXljTa( zb5*;8IuRMYUrJw|<1QaUxSc2r02u%tNFH;ISU!3^gwkr)-5M zZ$^2|^L{NgI8q$BRQL19^w?|609^t(yEo}dPB_6!L4Z&oE_^o%o zzY76%0@tAI7WzA9dxA)TrndIBSVy8g8f$8AjK;#viAeL(w$6@3q^+er5$lLp%j-H~ z^$k`_Tcj-#OB`hNcMl}Cb#2_*Z8gN(6VX^K5syYX+G2@Vv^g4%M-vU;!_wmRc=iFniMXrgU-G-koqSXrq?nMS!rg+^ua!FaSa4(FR%6Y-94T~l+@>TpL> zTdOrl(8G~LxIXz{Q|t0@b5nhyrL8_{)z>YKwp#JX()y<5kyz5slJ@9giG-yGa)~tq zeH#-4R(*SX1#GppwIXt*HRht$YL7>oMI|db5Q*-D?mQ;c7_hyqUi7nPu$D$wsYfD> z zl72;-n>(AsF=VsWhNi{F>3Dr)DRPR`L=yUdn}&jcv63n=C;VvL^#sXv^<)0l;t71G7^o} z!@+o4d!(f!-jK9lvROm8K8mu?(ILs!9%=1}A!!B3*aBp1L8at{h|)ZE@U7_U8Az2R ziGZlf=pzztZGcKlo{Mxe>r8`!BUwkC;X1D2IL?*oT&2#{>O5DSYt*^cim!+@By;+@ z^~g-g1ks5fYh8>0=whQXfhD=FtQt1kH}$qR#I0B~9*r%J)>qV6i`zRSdqI=wS*x@x z(T=iOT4`i;pT3jJ`RF$~Ll7LYc{GW8vi*3~h|Bh8YTEtMBgWRVxjRH0!B?e96F z8^MW3n(!2K6RTfkMHCP2)G9fAuqP_5xP)byiku`@ zOFMGqU^c4=#=18nevb(y_NU6m5x}q(%l!296I;mfGb=lck zAB{CMx2=H6%c1g8s9X@WqHQXXq?E+mpIkyE72$!miR8fwUlLXZYMJ3YI zpuz?nLyXi$Ji4n?nj7A{>h*I+|LdXv79n zcvsKXAHVbz0gaou#&~Ky9x)Mf<2(MwXKmWF=WeR+Dqd z8Zwo~A|3J0M150uaU#+g!xT?PBHq>+i=@|f;g)t3!r01s}N-X@*Ua3iBg-l*^C(-R=^?g6O?Mh_ z(nJTQU{oyzUFmigvnpmnCFvpCFyk-2VH{JP1@-|XDa%XI9(GI4O04Y~=+Y{}mN}*B za;mUARf5Cq?Xk9%O)a|9(H?J!aLOpL5w1vQp|4x|L@MB>Yd=SP``v zRk_ZnepPeX(%u|xLDC=ulkO`R?^IG7ZK{4$yaOpOWxhOB3DuX^OCL)00i}YF22hvi zCMhxXtu4sqR(lJ|Q8J~ZNQCR+$<`*BR7i2DXk(l+!$i4Enbr67cOA5`+o~&Ff!+mb zveu4fE8N+EuG4blQWIWLAd)-|-7x@B3tb8cg|QOtKtC51Y$S?SKEWz4qs>>n!gyOl zX`+5vN20#5Lv<-q-78arsajQaz0j=HccgoxoItKwj6Q+%dX;`G={x8iggd?1W>#6K z^HFgjK~Ny-0puB}Sx^v6U12VyQc$%=xkPmZDq-ndO6^+Syd2S$+FrVMxQW^}3bn>p z#XF)cx+Ll9y9}i=TwjX34TZHtTULb8h#UlssbrHbOYWTX2x~1veF{7Wdgmf6& z8X8hvPt`F&p9Ebq>Ear#rz#$lbu|P?EN^S>fO^o-hwD{86+Wk`|DIk|1-sf@ovYDz zMP(UD>w!tZ+Ox~r5=BLqK)z}n<~G%n;J{DCM+S;*tE-E%It?d2?!{VO)+h zhB0hNRRe4(q{G{Qv}k53AisBX$Oo^ahHHaw(%o0xz($OhjM|!`%cIQ+=?1B2NRiP! z^*wvTIwkS$F7#KoO5K+t8o@^oG|N&2z&NjmXr-q2nx5Kalp!yUOpPjJ=-x1E2RWNnQDM37g6L9 zJw0Gbh0GzeH6&1}w8d5>)667fyfcoZtWWkXk`^#>=!~azN5ZYis=5X93UzHOt<4+P zCe+YEwZASsl(NTP!CFtLTeXiFWrp^uI0{blUXOj6!>dp*&0tP?xRMu8o>iqJb0Mmd zPEUhUra^{JlxCDpN;66)r5UA@(u~qcsXHH-Fl5vlv^&?WD@tnymDakXCfB*+W~9j+ z3>Bqo#N2ns$4K4rDXSc;#xr)SRda|RQ6J2CcLdBMn5t=RHj@MK&PXI0k6SA`q!61d z+SwZKY?rcz#;?6O9#i#)xv84MaGkzudQ27NmhPJB4sm*DsQS#xSt}WnJcHRCH2KlI z4QAJ^F5_EOGBT{s(4SGQs~V%3L9EL`DkvkMM(Pfzk-7tFr0#$ksXL%XnikOH5TrgF z$qc@!t@VJxr3c*{mAbQ_nQU+e+eqEPHqwegsx|9{T34e*MFvGDCf$!RKIe{(k-DQ}q#3C|7cx?TQg>}(TyV$8 zNZm0qQg@7uG&R6%YKk?46VXT{QC8QKYTwPkS2f^!wkYhAw=^}O9g3l8l(U`|mUb#8 z(_1)8D;0}jdJAVvZ{dvTEu1mEg>xzpX)~FzXh&M}BYg-niHzi}M+;mgLlbH2o6v`m z8eR|UESV%kyN)zcjfmid$eaUn4kkG)=a7MY0Hvu*4eXjwLpC%tMVi!1L3Y}xV!EM8N2QX8EH+j!&X^~lvJ~8$XBKGpWb|Ma2V;J87`x67`yKDF;aK>7-_2QlG(dd^QxxC)co_FHJZ$5 zrxz9KHzVXmn$o&Ss&GB#-_T)Jb;>q4`dJsx01}*WFW+VWm<(8U%7|a<|=*{I#=uGL^ewBj;v**tBCJ-6LnBKW_ zOxd6THd1$hjWnY~(}fJJQ<|Z5N;66{r5PofQg_@;7~F9)(pssX%g|uSwzJ*=>?s{A zgOt|lag~}jGPPG#snw4`q1vvBv7z1!r(TB*p2%)SwCxf>g5CbMCrUALFU?w~1|*)Y-t zG>m%QQZK2ZhLh!tNK6*8jK0il7*-B3s~(PEeqYV#sOg{0TYF`qTV@romfS3LB)c7C zgPPTb7Wb?~nj`gz#j$XEV^btGYSDeA_Qq9eMntVAXczPnpbX_@ZBWnc$~rN8wu1(G)(mV+El{+ez{^ynPWlF{k0oQLMS1~C&FaMl%X6q^jXF$Kf<+ii1ShMJ z)(B=8Fr6Y3{g`rVNiB7&8A z?OH1W*j%?|Th;9TEwk5_RYTI%w`RivY~Ma|V%lt3OoM6N)?T%Fc6PsBL+Xc2)^L($ zHBF#0g-eHJX3g7G@1@mvvLz+f>7Kp70=CK_dp1fn)^g~sTrF<0LRCdwEvTc+Vv`Am z5;DFS!Xy(WqQjMdWKDNDTEwt<`=;}c{&G?K~c zC#@<;Ii0q1Bi7c~gppUGp|chH7%-73GyQt*+Jq#w(ltw9#4G3l1rb4J|Q?`UgFw1it%aj^yp z+GA-=mKQ`@vce>3p*>`(r1XUKVO49UZ%L801ht(;l#K-xvDA66 zO)s+ZBhplcR~xDla}%kND3_PGH3}n6WC|>nD>Ptjzpf4SVbaTpgl|QxsYAB0v~e$w zECeA~GDJmg!thK|Q|dw!P>yyn50824rj%3mD`gGG#h4WvSXxRtb?IWL=&vmGYw22+GYxg}JCS7ggq>+FW3WkLCSTc*BbU9U@xF&AmtJ)%1ltl1NJ1m_)Hp%ced0C#i#6~k?p)z%eiFYHd zPF>DTU8Y8~*t#XJS#Z_k{`r`ktHT>^a3arI6GTpj#sB4 zriwarLZ)v5Kvu5Mimqt*Z@h_8-+j>5_0%~QRdjNco1`i?C8E3nO_(fgver(|WNLWK zHGjSIVO|zVY+2WzIMlV1%r$c(Rck77lk>0AL0T2<;F>e~0^Frlw+bnYO$~VSCAkj@ z!+7acrg|@?mxqmgi(6&8Lehgl`j9Hp?_u#~$aYLY=tMkcnn(-oI?y`2?>S}z&vdHu$ z*t(wes;pM(EL17=g=wU?0VB1m$doc^RLx#lWWTvG4=GhUbR$UBsG>JjtHxI}bwnD? zL$Vb`ulJ*iU|KPx9G4>1#DvjHMXH=ulyS{FskDlef-6!Au1G1kBBkJpxvIOYx{gW5 zYh{lGx;#?7VX|R!U(b5Bz|uriX{A&(p!07+toMH+KRz;fYnErH(_I~dxVo#&30l}N^3_G8g}WkNmoQ`t(s_13d-1c&6dBj zb!ltc3iR|;;7s=7O>91vHchoh(bl%k#f^jX1hC~$N_rHPyR7fa<)F4&)8-K5l|4R# zN2GQDI5@U2Je3@anp$6^60IujGL?Q+sr0K-8)UJ}hP|#Pt*TNfSd~h_s#FQDsvRV} z@%qN5L<{z7$wZ{e6k3^c3Du&Oag&wqF}6pRhOtd|X`P%Ra!T7t(2h9~^sJ@YY?qLs z&eP2}BHpkfiY{Av(^#E~Xmu*0)v1V9SF$Ln7FF%5lIQi#VO&U84_&lQU0GrSj@1#v zhEOR|H97|PZjecBQ-i6hUOEb@0hF!Z(g{{AU0T}7cJM?(cCEF?utzDr6x~Z%{e-VF z5JBsS)sNItC-&w_&X(?wzDW6-8f2^9Ap5puSVNEzCW4U+U^{lLsVx{T1(F}xCANxsi7tls1lTE0MDWSoH5)hgcQe3J-AjFuv1cvX ztG293Uo(oKyCxRP&CX@?xU>v?YuOSan~dSR>HvUxh^|DYElGPzBO1Y6PVf3+seG2N zK;_%9TB;@~hnRVnwpyJr?~ZFsyW@;mcbqXJjB~X*&sFCdb;iPhPBH0vQ2CM>5R!0x zncgC%(wH66GW1A|YGd&*=0jACgX)XZUwbrx={tE5aXkoTt;4nho}o@rJ5N#B@(L>B zReAENB6(%@YDZhElCtXL)!gJ&P4X%=JWFOJwcVqkErw`HH?gG&uT-cVrzk%%g3`4E zCa?5fAQSK892Ig$Qyjxysl846Y%JlSuiS%$7ByRE`EJ=%Mko7u7Y8Q_V6#Ft|=*-mB zW$uwn_93yeqIqdzak!~ff-G};$uS4gQuRrxJhP8Vb`nuB^sL1*{6Bey;;DR3(BvoHBHA%+q=l&+c8y8_`aaYTAs&)DSh&5YdX%Th2^x z9Aiba1Zs6!t5)sqWL-#2$U8gI&||}r${?0&_c<*!CO5emzm3Ax9!Ir>3-yS3MGBEK z_SA$;w5>_i+{s4@35iHRkY1knfepWH^RcYNzzYx3TR-ee2cO-CcuW}_o) zy6_QI)f+3Rt_Wr(P)PN*p|r83y#1o;4ihlF5mnbNCP-`);Psw`v>t`s^gs1Z!$vI1 zsV;toD&UcM^+Qym7Xx}RH;dmI*t|}f{{CblVntFm$u{9V6u!8Vyp@)VL}MwrnSxLH zLWNR;=(bBwRWc-+2tCMVN674vSGA{fK?Y>a3NP2C98cCEGW%-YM_>gAz0^0zT&UU0 zxVHN+@e5w*ZV(Fgo{9^j2}SMJqFj7r3sANyIKSZhzX0o1=?SCOJoF`Z3AD<%UC3eYeDB z^%jiEzZ~iB8GWP@HfTtVRE4pmZmiU>LC@<+5Sv}|Jf{42wxejOw`SC`rT0zP1PDS zVW~{dk|a7X;y@QxZ#qPtPu5B8X1JW1SCH`nG=SlP%a-en8%%yla$?R@PpHaOYUM5* zmnu~Tpb)E>RkcF{TdnXKE%G*`sX;S#Kbz@P-GgTFg!Ar2#>5&dB=zCVSq%Ph6G5)(px}TsHkmwSfKkdSkU}qVcrrm0MLl24wO9s*yRcE&X^QN0(I@^HmR0M_>eQ z;r)I2R_f2(p_`-mC@lA@K zs1e~6V2(s>)RtNrEAn{h%#y(lv_D9`#O$i^MrwMsk8Ut)vgb^O8#0Vf>PpWR)}vF8 z-ENkqd*fj#x8J%K*NxP@O~Odsi|a<3QGV#Idz*x@n^CH0*S$@`*mZA{FjDt62_tn+ z_mvGAHzRe&%}CvGGg5cljMN=BBdtQAmA4hr6Up3j$Hhq9aWPU1R+{m;m=s)OHTAjy zT-~$sZ)#)Zrrt46c4$&F52>l!WMw7GV5UQ2x;JH1^(qO=Ysb*H4U>rP1{b*H3}x>M3f z)vyw8CqwPhUvzJQWHMz0$w=KnGE#StjMN<@BXtMKNHYo!-xkVH3#INblv3&rgOR$! zV5IIa7-?F)*N)Bt-@KK|$xM#95{dr0v%Yc5o%M}0HBL{Tx@l-?#uA#eit5E;ES;p5 z#FN>MJzCf5mC0zPE75>aGTu!|G+=6D4NPi@Jy8m#&v=VN4WwNwN*-08%9;f zn0t-N#HUG9RbJEH?19c!Vq%+fd$Ks3w3=QzkrnjRc>~td*~W~6TI8EIOV6#G2lvXG=^WA^L_>im#d zawx4*s|uLm#VA2fs`9rXIG-d%#BBait96-~X|B$L8CjpwjG$ARk@YFfDDRYJly^$q z*{zh)jB-F}Mgv1>Mgv1BUc$hJ23ZD@pXgCj(m2apr{04lz4Sc`3Kj|?dW?xt2bNk& z*#Nb*DkC-`#PB^CBv1>oB}acyqsgGE$q+p+Mm|${PI~MO>PH}C-2=loBu;t>VuUmE zi;hG_X)|^QRXR%XVD1j8bd+&Dfr_B3u(@ z8M%hi)bu`LXlD8mt>k5D)*lf_N>lUx8P$<_2{bj~kKHaZGDZw=PE{3ByO?I9S@vP6 z4n>&;wiIE?Ib5wV*Ce>aP_`PSk`s<3n|AYxs%p2B%QGhB_o$juKM$a$X$Hw_?Tf?G z8~=}Yk~EDc0V~q8i~ka=8DXj6?9tFs1K8L$qbp^s>v>K z*%ydeBQ%Ln?8s5`OM6yw+7)>r&peUZuB?^|%!H?!)6t99Nvmn|$!Pl356r0T zqs>_Q7$hsZc21hyf*mWI`axx4!l2g)lIvUi__2|+EgELnJeW6wW*byeO>Il@n|R5{nEBtdE@(3r5#yM*F}sSp`+Bx) z=l4x#^B;?(Nq^lSmsl_(T&C8o1*xIOm`$!F8lvA=o%6BGUHf!A~m$*Wv zM?q?Xt?qQFttn~0r^PtQp@|8Ap>F~>W>a5>q)339^KRt7fZQWu+I)JhT zU(TsPRBFT+k4NxBPbf!?n6NV!X{}ST@He;NtuquPWR7ra+HW6275YOP79suZk5Vtv{+5u-6_I+LwlLsLT=_M0OR(3@J_OiOu_ zGi0{Ar&pG7U-wJ7^R7+-JZxnBSLQZcIMx~?2FJ`NUY%ewiK)RCB`!H`AOT!4SI3j~Z?sHMI zvlX1Bt-xlob~PYT-FECok;#2k)2aN@U@{Iau)7YwnzuTP&y_|Z^NOd-dmZ7vO~p|x z2CiL;A0+EAzs0X!^)SD&KjS~Y_@Tbp@dN(w!?#D}=jJK1{Pei|$>$l&r!2%QpJ}Me z_nl-feKcRp_<}<6Pd?p{ZkA6tq??OjPIqf2%!|dX<~`jKd+B!NGaAa@6?@thf70#B zCn}bTyGyiP^Jxi))mIF|`9n|io#Z{)bB^s<6nyTnM<2hQS`^T`RZ_aKgN{-_fJ zC;3nIo#H(ec9Wl`koywXaDMiQnR1D*kr(6I{K;o8;O|Mklf9?lnY#SqBZB!u!#Uwv z-014Yt2OvWH7@-%vs>n%d)aCQhGn%l-e7ituh1TDkMxeRN84lUB73Yo-ZRObgI~1I z{7V=4tiS(|e%~uUfuHv0yYd;1tc?5eHJQ|(7auoqKaU^LPy6%YXY}3o&ByYzB`4p~{ zesTLa)S8I9^8AB1Jh(5<-;P87$%kT6e_r_Je!f82PuY@>%B23h$l-4L=EE%7ju#)G zao-=I+}oaXBK-q368}-^e)6`f#L9j7m|W`5>ne?MU%t?k`tw>7QU+Xkl{Qi$uQfSk zQ1_>1nD@#sPs=dR;0Nh+9awbe4a-0@E|Yxi=k?`W3#tpNFJw0O=xNyq98b1cJr zFw7#-;VrNZqgm3i0MgTGmONO1^u1gx5?qrNQQ}^~5kfv^#CHM4wjH$bW z{m|lIyF$$mC;U%aM*m|c-zZ7F9hC03>YtS& zJ$3q1QNd!$K`DK5e>?93mM5a`dypZs#ayr3a}NrFh{-zkJ7^l%Y!eS z6$|&#WyLe!vZjj}-+`JXtkEC1^`PyOR=_ix?v_hFgBcu7;yd7$r_@rV+k@}3D|c`o zk0^WaLJ?6?TujPW+{B&z$u4p;xs5!UJd-?+ypFt={2lo&`62lk`4#yciH}Dp|Fg+_ zvXC4@7L(J+S!6j`LoOui$t7evxt!deJc!&t_L2kS5#({?Ddbt?1>|MqRpige>&aWl zJIQ;=hsh_&=g61I*T~)E`{c*u=j7KUI;TpX0elok(lw7PB#X#N`2hI>`8N4E z=|#s>{3|4zR`j@15*Bj=F& zlI>&{*+-s8UPRtP-baqXuwV37PA(@mk;jlfA%8(WK)yhJOnyTS!@y45okT7qmy$i? z(d7B$4)PK5BQgsESe4G?EOG(aN+!rH^`&OzulIlWWPXyj@&)#GW*-maG4=2wjZzAs@e@A{o{)-Gv*6x>(^T`f!3wbnoJ^48K z68RCCHATBuNX{Y~$xd<;c?@|jc>{SD`2zVi`8k~%CwT~Y40!{2FZnF_ zSMn<|f0}lG0$EBnldH%>$P>s5$zPNAk}s3*kzbJod(j_qF4;(~BDaz!kUt@BAnzrg zCI3WzO3Fl=l)GW%Y;qnMBYVjs$qUJ!k#~@flYb!pLViOAXE1%pS>yt;l}wOZ$m7Wi z$e)t8laG=-?-;V0jF9`08_Cnii^-eFr^r{xPskt0qP?|0)5%5T{$vk% zJb5K~J^3*C68S0l9a%U_yFZnzCKr<{$sY0u@=S6&c@y~*`3m_78Jw;C8A+Cqi^%=S z9`bnd0`g{Z7irDW?&XnF$!ao2Cdi+Ww~|khuaO^--;sGG+Wqll3Au<|Mjk}=lP8fE zled!hldq5;kYAHdsrGLSi65|34zim( zo;-)Vj@(JUMD8ZPCJX0le{1xrsc6{0aFB@&WP%@?-KFa_+v`{YG*Xc`igsNb*ARXXJzAv*df^S7cVbc7HNi zN;Z;f$wSD~$)AvSl8=zDlm8@rQSJU%ayGe;Y$FdOk0MVeuOV+EA0b~R-y`h??N2^A zjhst1lB>vr$y3M+$s5Rf$!E#Gl3$Vei?x3f$Wk&)#>h3~vE*6g&&WH-$H_mCe<8mi zhc{~fCXw^VrR4tPVdTl=mE_Ij1LOut9pnIc0(l8}FZpNkGcveTyEmSkMJ^&&lN-nr$n(g1$*0M$NMEydw}6~RR+5e6 zLF6{_67qWTe)4zZZt_dg)1v(uOU@+Q$!_v=atC=cIiXcQzl1!HJc+!9e2n}v`8Ao< zrk@`{R*-e%O0t(cn!JYGNj^&!wQKiglC|VXkXy-9$+O7|$;-(d*~*<>ZT4_QYxk@&eqrLPs_ zkH~IvBiTCSmBKa!$7WqE;H}XsJU!?02+k0Vbd&mk`+x0635uP1LM?;;-{A19wBUnXBC|4jas{EYl3`ESzSspFSRhR8AG zL~=S=LROOt$a-=q86#Jb2a@Z_UUDmW6nP?f26;Yt8M%YJj=YJyo!mt}Og=@vK>mUJ z6ZszbG5H1gEom>;`pG7TkR!-(

    smvYf0X7mc@*(m`@_F(V@=fwx@+0zd@*C1x z$$UhPA@?FHNc=XNs&AH(%gEK_8ge7Kl{|(#l{}BUoV=F2fxMl(k9?ebo_v*joBWXc zg8Yv3uhQYoCr6USK=Xibj%6K29!>e_G@nggK>1ZPUrYXi^54+Blf0MmCux3$e39}uX?~l0 zUs!5cpYr~{DF1=1Aj2)(>c z?xy@>nm;4|LAm`SZQoDk3*lafoKE>HvWoI~WE8XOUxt&`&WrlkyU>p7KUAM)?YI1LYgZ ze#*}fB3&;LjR?1`Keq@5&KyD;pS<&X`<+qS`Q2r3jkC9JP z{tC^nk#AA{5zU{HUs7(Z(ed_?K_TKjLYQw^Q)w>a{VKAF@=lspkw2pRV48c$e#(!f z`9$(G$}gh%GV)5we?{|64JDgUc5*RsB**|%25JDbcCBHp8E z9!E~1d=Aa!Am<3--Xh*_CHE%}CJ!SoBd;TGCm$zY zCSN6YlkbuN3;vqGbU&KhLJp8ek;jpzk!O(?k(ZHI zlRqPGByS;~B%dK)CSN7rBHtlDBtIboHsengkR!-(AU1dqf@@4XMQoT2bcz#avSLDA*^}ZnPhrBv|>ODc2 zr_-$74}^Ik&2{7|;V8>e?*W49JwR{+p1hR2f>iI_!M*EfzK6V@d{Kz;$?wTG$lc^uI~KFn@&fV_@_O=S@*&|+%X*A_hJ1m1 zpZt*gJNXYXCtE*1gd9PRA?J|gWRz?oSCI#hN07&m7m}BfyT}K~$H}M37s=m~?~@;r z-wX5c`xlO8HknIKBWIFjWEHtD86lUDt>ilLV6up-e1LiCr{fON*0ncg=hojkX2+Y z*-ZW);@$;5s^aV)KWERL&7R$m1QHSwK+Yx+5Xf!0De&wbTo0TeYpNw_0tjQnXdj)+n~7*0#Uzcg~sJlLhlwq&w=l*! zvVt*)tY!>?Rs$RzE$5zIW*AB)QCtlQNEdL^g`4Taj6fv3-F`5vu$r$v@?O5=K zJh~v@)pk6?j_26%JUd=!#}PXg{G)z@ofrK;zSYjJW{iHUwPVpA_}OvheyN&p$ZLij&tVL`nP}c3jUG{co`2J#OUD-MW2)@S9j)9*##^9sJ zwrl9J;+k&HAGA?!=O;4;t%Y_z!WjIt*!fn*;A^#=U&|Q$_1gIX#^CcxJAVyh@GJBM z?d@S6jX!LcKf)ON3q3&j&zVO*-nPrdc%wgJyihL23;h!NRpf>I(LW(y)D%bS)E0qLPratCmeIF|Wh>t6aZ(?PF z<+rkq0k^)Gm02Lao0SRA{Cd_g$}_&9m5FiGm$Whwj`cmQOq^qURjabEbAyG(uf@tA zi0g(3Qw7KT;8?miC0g+rtz*C;UGYJ!V;Aw$TB4+H69=vG7@ye^#cTPS@A&BHx=k2e zk#1kJrmyoXtFi^bPh~l??S1V%>pP(W?23hPG-N|}Pp6~^9a1VgHf`M4i7%%*YOU*Q z-w32oys@%{m-wlK!xh^vnS%3VaGCZ*@*yR;$eF&u1q|Z@q)<_-wOM$ z@TLJTvt3O0)aABQA;eC+g~*rNWsD@=3Z$KQYmvwFPhAp^_QQ#{75Q-~tTesLGw^mI zZyp2hwhX)nkZ0fICEI-h0B5@gkcat6T@vptK%96($j?b(rTODJ-@1)^Rk@N58pf^Jjv+1hSLJ%d(N^fJ_sw zV6&pU1|M5qvW(wzbGDmTrYZ;EL$KZP2(lk$2E9L>rzl+e;rxc-Q@2Q5L7s1W&~4&fxEL;GM$)`(nGiIy3m2 z6I7K!z{wwNyyTDH!-Hz}0wk^#Z{bW%W)Mr#jDecEb^@;#M5Y2V3xV|V5U2y7m%7~V z!VXCyfXXDFw>a@8Pgj*o91Tc3cnIAc$^H%PXLVL?sxr-*+10b=R0row4P!RJL&Bwq5O^!8~>3=8@aXy0u51Lh8by@`a}jxtH`V((0-oP|9y1 z_CjJ?wWpv??O>j3%H}Cn9i&*N`jOs6%HtQ+Ddx`)`GY?nnw-bH5>U(X9=M<@wEBh3 zuC8ef*ZnQmY(5+x=Ng>g(mr*4l>MQZ9T}QtK7OS6>c@|4y4uxs-QTkRONY3H7~#Sp@BY#=$J9M_NSS!Y88x{AY-9R{kdvEWfQ|tcp z&d`Hu>G#T9liYO|ckLK5&G$C%7z*^Bx$VjBO-B^%%*{D<|N7*g|GJ~=&E8epY6n%< zs?9rx0;W2p@Oj3r`-UFXD?fW-=TMocOc_EPFiU>0YP)Ojh-+2f;{mnwwapiyZ0J#U z<@?WjE8l+M&^yZG6^90!m5KhXi@UYI?9jBoOz0Tvx^VTEy4BVD5BWPTSVIY@Wt4$$ z>ysZEuIm?maq-fwz+p|3GI%r4JUAgcImy*^Vb`y^cMO%SzIW?|L(2XMy~VxPZdXrG z1`qBiy!=B$9rUQ7K~??h{jc@i+UJ`1!uDqs=AXU)tD85*-soM{byaQlZXs+B-nT@sYNSJYqy-u!k{)R7^?jQ2DQWpWT)mjIe1B!+mkx18$#S^aEt zbmU^Ro-pc$N)^|K`}NkL<5z2+<{S~T=fl_1hs^3F zKe(gItQ)&Mf6$v-@VGbN4sceKcHa*8Yv()*DxSPs5Q?|aVij*@>=p5vBkqyKg3cY? zU#s;!|MDT%sAtbvF>X)$3$1T;tJB|VXB)2L?*>PKmi}!A#k}(b`Zt^Q%nNk?E;aYA z{ei`E7I@AwOE4qzTqTD+E#uzm`q?{_55+X+K}$mA$CQxi zkdRq@{e76n)!N{{Tpd5SqdU<3)!Llrf8TYm`r$ty!OI4IbjTB&^Qa!Mczoxb zvaX!i_0TEkw6b)_Y*D7JIg%F*A!Ynl4XiSZdTQkApbC9lh%vam>!oes!G+pOo98@= zakY8mnDz=j1CpPXd%McEt;~Ar$d2ryUme`GziiWyOGX{stR7HLay@@=Tio;M%T~We zAJs2Nb>hWCfz=(`4tH;WE$i5v6__k!dT-Ysdppp+3fK+ksWSD27rxbfsOxa|v!|*- zb^2`sKSuwaeur`+Z+W(UEs$I(7j~`Mer;CM3oqP1axgo0{_|=n^xC{eSjKhFtKAoL zUt8NesHsnOU-Y=^!+!;zY;PV^a`u$J4(ndMV%G4G2%cr&oOw79oKwDn}S8c4VIlXos0G7dcQ&Z@q_cU*xd zyLYE#A!L$q`*fk@kKnFOJOTTHr{IC^#ZK9qmBw_b9^XXxARppT%QJNhTx7+idgu8N zx%9)uD5-^;>zP{|XNfE8)yV*@hWq4c9MegVTmPpApa{HvPjm5B0m>4e_4De>0d#q@ z{)q!9w_E3rrMTQ#CzEIy9Hgu<`O|=|-;A5*>$qtVxU^a21$BhpN9d!3erf_bEq^7` z7feFBx&U6fqQ8Wj=S|+2$~pq~G|RmcN$--Jc68Cpj}t52+lt`wc*TeQyvQq>_slWi z$IC}wx|bgc^LY7Lt}O3Y;Ujsy9|6no7Utun7%xAc?DviV|JmMdG(E!GiB@vFSvWGw z_3kf+v*(=*%#mJqDK=(aem*GQdm{u|;Jpo{qrG1OW})|s0YxeDehXgW81IQD9-Dfn zVH`@l{7lwZ??UW&$9eao)^T3=&&mWZKfh*r??HitD79BS{kfLZQ69UkWK z-jNXATJMb*icardq@VHbM8BT(9t6)n^}gc9OWWS@*xUWwI|=aTyw_si^9!Q@d`?r1 z)nKbaHO|xV=t4DOc-^N8KyX&A8hMDWQH@sUz_qHe9o4Q^jR}y-PSr5LzzwRg9Jw1+ z<0+tgMK$k5BWjSyP@L^b%( zX9zinWrfQ)1r0soGFE`)cQs=wM(2=b@cW*JHDf;7!@7D6w&w3^#*ZPFKWPTPDfeg1 z_$s9Ffo8l5!3}E0-!(<~P%}mCm`MEHl_mDJiqJ-OMM0>4n;}giR&28}1c$wSSS*9q<-Nwmq)>pWV7oZI*-Ny4EwhEYF=@hr| z05ttnw=sbB_PULw=w^X#Oo9kT>&5~^TXlnaQ3Edlw&v!=tdD3{Jm~`13Gn3H{Jm+&u1CGhsa;ZGEN807qbi=DRK1YoSID`wf0p?+1S4>matzZ+v_L zUX=D54`EdH=Ne5A-5t3`BPPh5xyEGByero@4Sl#f*VvBSW%;V(eUB6E=77|>v z%iwe7mZyx#koD51j4wg*s}CFeIAi-^;}kTz=CE-#B++r$I2qN~9yZPaOPz-eKG$D& z*w_uO*B|!1hqB(0s^U8j!?T$Q1$FzF2tr8xO#B)g4lr>M>TF?x??|1+#2*0JfhQuq zbAkLtk-(^3z=RKac_9;rFv%`rq88(NF%#o4Y?m;h19B-7cK~v25{XXq_&O&33XxsU z#4>bnClfjvy@83_(8+BbNK6D{+nLymK5>`m`z9JynV1RvaxrlRTIWyj_fDZl){iQ(TV}dVq!TUUM9W|85>O8fr0Qb!OxlcneaiAvY8kSHbyY54I?*y9z*%zVrTe3%B7Mzv+7{>hU?C*iuFJzwp zVVskl2NurD-V18yE82UgV9d~ZK+Z#&Bi#Bqs&*v`b7J^uVEsHb=Or>@6e+nA0$|{L z8<3T!uRrHHwv0KSmrsx;T zEPe+ltmv1>EPnQ9m7-rNv#OHQr0AE)EEvpl>)Tc1+u(cT8b!Zc)n7(uMxL$cSE$+S zfZ~51If0!Hj{dT0+yPa{KLLW%Ur|SW4;dwYvJbgmtD_!9Zejk#CUUP@Wjpdu z1A_jVRkpw2ear^^H+DU>fG;rUzqKo>1r2QNb-Sioz}H6f-`Q2wg0F+R{)S!GRq!i} zy#A(L*H!RGmL9O{x(d2k_xE;P*XS7jHC{icj(Uy!Y6X1JM1M;i^#-zo?t*8bP5RsF zs5emvH7{h$o)zsxB3IGb&TPb7$V_hQ)i*T`anX%F2(;P%u@Xis(T-# zT=+InY19N^UGaPdOq~ExGEtVe6i*>JBtYCosJ_#%fFYZcSQb)zN%vSbuYx8XCi+&o z^#PQPY*2isxQkdavLU%f@wL1CGXYmny~}Of$Le(n*bBQhv@7>IXua=D3GgVnUm;+F z1n7ePTDSf(>9;AqbvFGr((iHm*)D!B!-tjlJtT|Cqf*SKRK@>3Y>ltit+BGs;=+50 zjX@UzP!-QVSVDjh=OkGInHLerfuJoD=vj(BjX(-;ToY6 zAWANlB{_;`3rh$PCA(#bNAXn;-!$CHHh_ zkS|~ZU|5yBJYSKiXTzG5%mN8tv0234mGohK^p%=^mMDea0B9UiwxXfQDWo8uk@*rnzwxm845AOZNvu)VNzzLOpQ3*iLR9J3bodiI-Gu!|yk^ublTO%2(mjJht`)l?u zCIOm~`%QAXSOPF0{M4(jK>{cpmv6SI--3>p@H6PXx#k#lyySM$ZZ!Rr8>O?%G;Rd- z+-EpyE6lMe>3m@l04pT`()kBy`Bq5)q;n9g$jINM|-N)=B`Rb3XghDFKkq zA*$`4E&-5EfEZtp07%C-4S;hb z0MgmUo}DWJkj_

    ^up8bWXy0?mJ%sAe~pp=?)2ibpAlyxj+Ie>1;Ih*Fd`DVvg}9 zvxprpxe-gZ??Tg0xxoqWU1=Iepj){IsVY~Q<7mFz>I5bCeFCnQfa8?hzY=hb1dPWb zGZ}zuC14zSM!9^Ljt}k0R>9#PYC#$1mr8ZFA#9E1mK7MUMFCe1dLR2-yz@@3BXSW z^4%NXtr7rBQ^AE{w*)|2?!`jr+am$cmghLqw@CoB(w0nnBe9O7?E0JLS23Bb1`0NS#9 zDgfV>09DD|!OneG0-yqUZr^35J_b{%)Tf^l`Vk4hQh_GEXX;;I6IWAm586!}@*?xN>1X3y(VjMqd)UO) zRD@^c;sMb-Xaevv2>@eQO`bCK=SWeM{n%bj_|B;B7p9+W(IUKR8iz>nZ?vPou}z8r z$;05jZ0b2Ma3#N^xqihqDN|_&UN`+D&0hb(G)@Fk?mW({ckDjFbI!q6jeLh>A0eVV z)AxH*Pm{XBu{%`XpsBxz+9j7$k{_944l?s5NA4e{{~cs3FNI*yWKt3Mh2-IrG;q`o zw{Ns*G(x|M=~F2A0o+xl5DFX<$!?{v;fKBCQi3O3s!gg^FiAO9=26(Y*i5)Hphr z61f3`zoU`+BK2=%V5}v2ObPzCnQxQ?z*_v882JIq4OC$*`2L=+KmuSbj&N-mEdkt) zH8d-}LJ5GiXq*U)A_>5jEEbN!x0C?%3KP#C(Cffb$rGG6BLbEi_b}N$F5tfkeIVb* z2gLbSPNEgAo~-Xta^mptr^-C`i-{J+S0VG*Ft!pQC;`|bHj=`034j6ng#N<}*>Q`d zKtSiOgOof?mdb3FUSj`e2K;1}EX@lTldxybsSU%Av z`Ayo)T8UvbIVYeufLci@l+$;j-Q<@!*~0-pnPHQQ1IE2T$~^@}(AOXdVD$JuG`>a& z!062+Mw0}9t4>)O@IoG|_5&$muvtw%{ zz~Ztkpq~xAl1h?WZgY798|w)8$v?R~BVh1ICHDpr*dPf&RQx#;-$n@l-%*Y&D(B>;Tm=uGkTNdWl%Edl)!VDY^!pjUyVk{+<=>$3UI zruq#8{Ol3={zAamL%z>tf6kQz!1trH6z53*_%5dK&X)l2{Vn!vhXjD{^;Dk=Bmivk zUzdCrNr1)G*#Z5>O|_<)e-=% zR&r3TkpOTtgMe!#09?IJ!*ZPjK$`Iwq==`;Wyk^rdYS@ed! zFXySn_BR9iPs#Q{vVE`3_H%6P;eekVBHQ}|#vhT)sf~lpCvA$lCXDza0o@M^Q_{le z_LxmzKegyb0Y6ETz|UYYfdm5eitoAM1fGWdBLV(*qVHLoz-2UAzYO?Engm`67+px_ zUP#VfwFy93xQx6Q(7#LqqU>dxz_(2xz6RT66F3kszCi+=ByccLB9=d!!0Q417bGCc z-Ux`(o07LF-?svOk|qc51&m6JTJ8c)+doOELZPl=Uq6rlX!Y_o*vCN$z(8CCo%DSu z0nqB@ZP4nEB*5y$I{`fb`XwKd{vo>;D>;wGW2PPV~0GvCT zJ$-0mdKWsAfQKaj`@?ohai0WW3x;jP-ii8?s9nO}wDa9R(b}oJN%Ql_M1K+`Y~rbj z##tts=*7+V6G;FYld}nUS^}`IJ&%BABmn!`D+u_h1YjF`Edf810BmD#BH-r|05*3M z@SFr-8+$hazmNcIV{gQi^F1#C*tOnDzzY(9T`T|f+xMabVAuK`0$!2;>{=fp;AIKG zuJthjUXcLoNq<7XuO$F`QvQFm?==a)7BoP>ZzKR)&=Uywtpq?HYY2E<0-%p`3HY4^ zz@UW)ctZkU&|(CRZc!GcrB>+SJ3;`cW0EYgT1RRk74E-wvd@KPN`ri@o7YV@7Pss-06A8f32MHLG z01W+!1pG|`F!Z$qd@2DL`YDvcXA*$3g`lt+65s<30{$fd7?fFbSd~fk?9;+(P;$N&u$LtFWKGNfH2&A0Xfa3BX)>mw+h}fVnhC zz*GsqTpA)^ngn1j!9rrMBLSF8UIHp50K=9?K$Qew*v1f0EdiKIr*Rz&N`N(vo=N&E z5M)Uc#}O}Xya{kgDfeU3C;2(T9LEzU8IJ*!`!&MnO9D`PlTDl~0gzuSCYvuL0g&IN zG|UkRK;N$>ASwaq`&S64lK}L6Hvx+z0Db>D0re7qzJHg1m;|8jg;)FMWRG#9$fud=dq>!0F=_@8?DLcfZ%xE1dqQq0 zKv{p+aTD(o`RC96YFuaP^Lvn2zANqSp!F&@k$o8+un}*H=s<80-R~0d>1onWo z|CFMakah>2#t`^VEfS3?rS93l@DQy`<3IoVPt!gju@5nwO#kY<(V!D}1|9QvjJ+B4 zmB5P_7600?l#Dy@CpR*kWA8(OH}H;*%(}7cxi9c0M!~-xwgXY%W5~2l!ix z{xd{oMBo4<U~LzbTibM+Gj1 z-Sqd3n2k(<)$9II?9P}#KN&qsWX9nUg6nIbuCvnd({P)}8~Q&-^dIR`cK~$5w=t5?X$an({ z7&iZRMvb40kqPXdip;~Kg2?14liRcKDh_H)e4MwR;sy?y5P1kKb;p?ekw~&df&XVD zEc}m|I)pmFq=Y;yDs}%#VzNaGlY*HTL~kYrkpj-YBn}x7H~^L*tvwCj(EkH%84x^k z0LVIwk+iflyCSCt5bu*v3&r~*ObFHcO^hR6jQ9xf?4TAyq!Y({95*d{X5Isc1G&(N z?AaqM)%gO(DtnH|r~&^JWaf$ts5}U|*(Yk}lfd&(w;9><^KQjaU*NY8ZuZIJDG5vL z*$c;8ihLDILgR_$4NNzYiR4oZ*@4hl+@twK%L~ka*t6?IrXaxI!OdPIGGhWBbRfH4 zWX1*V!MJC~^2dRI88``QoxOO{cJ?4p1Le(LB1%dFH6COdM5ZjzgY&)YMv*BOikRIZ z6mfE3K1-GcsAJQFR%W*fMXZLb<7ig9oGr9z``OGyX7EPfw@f;w$2)a@YnA@io zR5DRB8}K?5MXX|_BDny2O=MgOe@Y$=)!zn6!Crt*0eB_xDwfpnJsu*hCen7deh&sI zxDwz2fO`-sSyHnOkZ&M&3&Qk%WVQl254bg3kr~aYicmdky2XL2+(ddFw-H!$%(55GsjMb2=dW=GM&!GcEx2lY_V^%FIhZ_jV*;X_aMYXx60wxUN0hYGgm4 zs=}u#D&9^MjXVen_aTTzUPIzn2$e(;jr88N{Z*Y z^+B{)$&8TtTuPk?S>g_j5t0`|=LfyA5pY#+#0Xu91pdXzrW4!_(D5kd<6utuJE1Qg z4*8T{V>r~6magn%rCkqINL@MI(v^Btszb1JC28r(X#nu+Uk+W_in*=OH87V0a4CXgVD14MYMomT zRf1J!G6&`vz{J2XAqIxq*{DyUE#7*#o7Q(6Z~g5d{&b06_UbMRs?FhfMDcaQ!K zn`0&|86xPZ|GZ?AqP15+;T5Yjp#|lFP97x_bJxGb#%MAA1eEuPR{b~zmln~bOeWG2 zi0?Uo_<1zSTyVS&X+>Gc^1HMVV<0@iaXHFMiC6I)y0sMvm>nYBt&NyZq~8KO7YMV7 zH2YNCekkT?i)%nA!c0J>@CVM-6RgoG$9z_I(TG_lw%QtxbW&U=+wCDH?uL0&eH(=m}u3% zg(zTFfYe2#=@^|u0KI|CZxCkw6&chLINw5I*53heUAs}4$v1@8qJ-x5MU+(K05F?_ zlpX^R7zgM%0FsmUNgx1#>)IZrf)o8oKvm@$HoZa{IUTgcME@rMpCO2eUVsrFg)sYd zAX|1=j_)k|%V!nny^oS|gjv;s_$DMzIt~h~9?(XpG(+>m+Ic{mLqj_MA_GMSHQ~T4 z;Ic9Qw2^>(ppB(#t(-i6KeM^+lCL8NQUh@3)ki>zx@?hp#3t2Cb$m<{uXHLWorgm< z^(r7ztQO)`7NT;}XQe39P{uA;WtvsCfTEmV3!g~!X;zyHD7N{lNv>L(Ah=q zv{J#D&1jc4#bR{fXYhB_pSi#;nm|x@aV$cj^FMP%*!c=DJP9Gh&4l`MSA@h*1z;J0 z^sCh8T#=Vh`6>V|L#X9GP5q^70{v~*wQHxHO}1Wg2^Z;cAbcM|IVsx%=nmHi^=&k1 z^>2qO#wO>z#A&m`)gk(E(jO??(LkgEScs!twPQFibS%{(m*sPwltsjUs3TN52^Qi% z)Fni;DE>q3v?v~*2gIj=xFLo3v>HkyKCQNYbUet5-o0|cB&!z_4B?(vvGqOqQ5?m+c5P;HFSuArHiS4MGetqo-btkRaH1;O61G%0@O9C zpEP+rgP`u32t5r6;%n5|B+iB8V+70IthH*7hX9KaqBo+FiLiSHFt%rd!Zua>>r5?5 z7a-K>3-Qk!z|h1U>)MBXLhHXsH+p-BbOSwx&m#QTv@ z#a$u_B)%kdC6Sbh@4|L)zAMT?1a&~wHJI4oBLLq8jN1?@SyJ;1AU{LyX@o^lfVcwi zznCp1T;I|cH3N#F1eABS=;E`fI<^6M;o_ZkPTivFow6PN>k>b0D4HmTm`w!H#A2d~ ze?1q(>?WE7ly}*LXki5aio&~S;Ve~uTDGtp1o@V_XyIHWw#gPY09_RynsT<#E1e6~1FsL)sI&Ll1cs(~f>P%z_PFN~A+fvCB zPX~Oyq1CEK6PnlsKs*vG}IhCv|`oI^a z8xe3V&dLJC$5NJspMX$zagARhEX!k}2U~#54<;_*-dlZaH4i7gf&6U<4Z>9I7nbT> zLS@$v^+~LJ5YQSFR}f_pcqfWmnT)&ZMxDQ%9Bc)28H(cwl`N=P4ahd+ z&PHgVN6tzf>&sost=+@*D7qQ}SJMY*10T77_VZ4WxW1|fKLhk3U_5|O;{}mlAn|ii zrDZg-?5IoWWxaiR@I*lVh{CrKf|bbp1Bt&eQ;JMEJc3e$mP?Uwp$fL!thiMV?g3;j zie@7OcOuh-1iyiZtC<2_07M9smEP6)WHtwdrP02?JsAPc{w=X02B?K{UtmIKvvywe- zUq{g$2)M+!ohMr5-8pVQ1;#T7V%!cQalon~1d8KmTw6g@J){TbgA;1#r@$COSW1Bk zL5|FY0YeaiWF?n!4>{SVZ-s9s1j(00f(T0~NFl%&a*Ggz0IxzNRoTx<_DJ(z5l%%A z0_;a(GlDI^8$}bZ65AHw6)3y}K?sn==p$S?2=LG3fCBt3iobmBC!=&e zLRxry01-zJ!ea&O9LdE#{Xt5cTDT3xXR}gDcvm5JC4vy%&ru0q#$hE}cz2-aHUuHO zhmm*)!4}?&qKRvWZ42+0DEt|M5FU%&%EK(aQJ=~Yrtm&S@gPDa3xx2B;PQ?}5W-_6 zkMcY#*}|(qQ3V1nAw2Poc*VK{%eES=z=$IV;cY&Ih?v6yR=WP<06 zt{>0;CDsR$p<8=VK&!z)QbX>B% z`L(dRW~BM*s!j9Nm9Y47<3PsMTByU7<#!XkpdOB9_v+ z0iKa-R-yLoRLQK9M2n*LvlfX~!VyT*ou!Ut9gQax^OKOE+fZ})UvtVyE8))S_Zfv6 z*SvY+pAGLb1Ru&tKfwB|z33jR=?hWzZBRlk$et+ShAGHB;GV#oc09`G$FQDi54o-X zy9@sY!=X*E%cH6CfL*@)m$0VTXO7jD@58`rE~Hj)AIPf@LERO67THTscmYE26=d!~ z;!XsyD<4H9Wi{_#cIiJ|2pk^2J%{pVS%JrIA0Y7_0v|#R-<7-00%R^5tV6=On~1qN z6m8{#{s;uYML81uS5P91RFBWe_iH(0bJ~hVs(c*lDp&me1puKRg^HGQqW>iSTz@Pd zVzx^lX?>Rbd6aXiMoDq1gXJupge*Xx6wx3^m&IOoUiP~v!UeU11Bb}9TngP;!nsmOC28rTR z#c85*!0c#eeF6$qHI`4diUR0#73z!;2^1BN0EARZoK*0{04zBg9VgI$KYkc()H^O0 zGRH%U85R>l-X|B&!_k77577#t0Laz@b`t`JZQ^xY3LYo3R13HrLT0Jr<43ELidk`@ zF2)M~-z~=!TSOLGy*gorvdA7iekyfJrFwF)l*pvwk?JVV!ZBZ|6_loe&D6NKioRb9 zt(j)CE(XPhRg70_^5g2mwR&683ja!dx#&QpUu{E$su@ZRxT-!12S$`dHjSX3PEYrP zURx16Gvo3LRAnTxIPM~p{1HA&R0aRDfdJ(u!kjCB>l$+{PkZL3nqv)%DI91?60jhZ zkhi5LlZs8j@I2k28n6t`p2FSot8DmWK3ZAmtZa$wMoVOPiAa)-$*$Ep2~p-@XZ2XV z)p}(3K*U5>Q$rE;qmx$G>yFVia<*tZBq&C~?y`S5w5EO-Lufqa98^x*#i@p&OVkpp zL$(eqvFi&xv&X8z?vNAKn8_7dCs$3!fMelKL50THxGhIP;XzO@u;$t#vstu6mH=yIdlML7L~S&3Aqcy3F|11WmF|0@~Io`>K764#lTw; zeP|^=MkJm!if42~gV;gtwiSztzALvSno`_D^t*LrMJV4>h{UwMdk zBB)B61mP(yk_?VET;iz{v7JEllpu~W2s9wdpydWgabe3L@FpYH6z~4sOuz|3rvLoi zOiV)nVMZh-;F6rE0id|7r-r>qyOi0f&ZVKl`oRN61_#R|g1wD>M3Gp4&5Hi|Oj{}Us!JSLYAGR|LXdSOo3D9&aqD(H7 zbpUS7tVX~^!-3Xwn#xQdhd?|!bN0*&AcKPyywBwxKPCtq{Aq1DYG2IO;kdiLxHSySxVl*Xbu8!7;)5xO)uodWuY&X=x*hR zx^#EC#!`uwj;$JTSwmHprP0$<)yC%(VBgViMw3Lcg%wV;pp3{IObAtO*tG{aFwN*0 z1oGCB5(5BYTJ1snxkxUU%o~9~m2oN6yBR+sDzxHmT`GYL4smJ%a4Uer&DQ;ZJTx2? zIk7xZ6;vh8h$^h(+pV55>nH$O8Uad-#aUP(>dWgV?v}XO7Vb_}K!K6EIDZ!)fH0%Q z2o_<^FmaKv#7YsCxEA5;V-Q|}YO4`In9&9Vi!k;E)yr{Zp3#{^ns<%m#?5$&sE4qD~B zj}Zm@PX=LyppJPG-=*-4J^ND0K1~SKNdiSIN(BT4g;pB1X_BMGIiF| z3ob*>fw7)d)DEu??!{_&P=H$`-w+4@j*HFSiGZdV-GiVh18Sp#~9eRI~zya z;^{`M0Iy)g=M@;1yrYL@0ZP^h!~`Rf%9ICDmI;)U{;+=p|Cdd;1e#Sl#kDH<$sp+j zrZCwK@%}A`)QJqF^H3+V8`}Xp8cv72*6etd9r-3Qa;CcMfm`-2{lR_lLf7>vHn1S>d>SS`a53r-*6kh9(W@T19y31}s@MyT`C2q$fKp2erL^8Fm zASW&hW2wZj_7buXZHkrOfn=@DTtdV(978l@VWb*T#i9E;U}M)|*Fsc>U;$H@bW$mA zc3xgw>UohUFS?Mtp0Oga4PlbKb9zp>^wJb#JLGU7sLNF0X!%4puc}{i;U@yYM2>TEoK{$vY7jPuS z^#Ja~Vc8!MxY9Vo`^bCHZ)XT1&oB!?UXsqo0Q?o<{|28l<>jQ~13U+z5Md$$7g~8` z@=bo7btT@Pkr+g9p)Pro7yED`!U9KFhO{%Bhdjdt2=a2)$i8_IYrLE8930 zeP>;k%Zqi^AoL+@cfc<}T80~uc8150XLu4pUc|i$;W`B3%8RhigG*dV`&e|Hby+Si z*0~+weuRAv_)n0Q;YFmKf#!*Urbu4IrJel+0&(R<*yq6|uB3e|y3V>Rmlx~2f$(R9 zzdGQuob%j=z|DuWBeIM!%Q;`=<;3MaMqW&t2&D+L8}c%dkgzEdh?wbB2&W_5j&L`^ zV+c?ZJNBCu*njLnCUn| zE5c0(@>-3=8iaKSJqW!BTM^{tgk2?pj+p%+zvPo+l6lE;33uY=Ng!gTX;&K%b|T1& zusH}PBFvM(4A^1^TqdO+P|p8}o=7%gnuG9%Ol7; z%dv0{E8mB5t`YkYoHURX7wcYza0SAZ0%F~qu&+7bOj1s~C^KHN-_Katl>GYa{C{Vi z-7%UQ%&$YNF7@wtYK>!YSy|QBUbU{jx2nIdqss9EMM_oIrj4Cd?Hf9`R;}-< z3iYks(%rKuys59VqOY^3v%kH+3O^Xx$0*o8uw`xcrk1`cJZ5vRU13DptTMEOYOGzZLA76CSr-? zOe?NpSE^z?9UHc+?Q}L;iC;%--%!=x)sFI1SA$8blT`zoHf`wWYR7LiR;};oNRn<% zb#i(#SRJfM)>IQ%0boVXrk>7<&h|Ck6*bkB(<@k9iQ-{JRgeUmuiDt&0a5+`&PM;X zey1e<-w*r$F7;z5RmaBu?*6Js=ULqyomKH@Q#27u9Ba`3-*=VF{4aMGIylhY)4`wE zbWGgJ4o+y zJ3s|BdeK;2_f+Xc9^iWdqjkS$3<}RS_2Xygr8RniwjDJ+Wux^{fiYjis`i`nOubaQ zn`Aw;dYLGz_JH^cAg+4yUHDKw5|W)g!`V5aIM^8y?0gBN{F-5=8ZXkeRt{&a6s&z7 zKOYKyu0EQdcWr*~1%C%W4+?(3=t!-MU0^RKct-1ErXo{4TJ!)P|98|lXw`r$eX84~ zS7<*x&vc_)+b0;$G4)a7^^!7OFGJ~6?ZNX*7K8GSRdw`ezzVg!=b=M|`9gwqm3l>` zK9xOeaBKQl?Vy7H04V^TuHABer2xGmK%PpA&W8%y#Vdv9&HEov`N*d7o&OOP{9cdX z<=g)wDu021(a{Oo51~FjI<-B2 zo(sRj;25{(bWVgq6phdW$3xr!B(?1rv^>q2r+dfihG(*#<54*jm=2!&DhxpZ^>BmG zjDkwES}G=p*93BzUJka@2Gl>L(sT{ik{uwf>f=hO2}Ro9pp>cxjzPKpb0Tz_&fpI8aNJjq-9niIl&o{xFAB82PRYttUNN5+KtNEUM z-CLpOD=xPh)D1>c&}`7uO${HL9^uh8RO*H{N!1HLAiI(fqf(C{lUJ#a1ht7sj_@=I z#jKc&dA*g@ChHZHiaHu}noWIfRmPlt3~lTAU~(jea6HAwS+o$eCY0-Q#_9Ph1gjG~ z1;-%~!2HUuU?RW38ueGQhL8GPTdh(5Sin8=EM2%_tLjUB)Rf9ae2CI2f&$ zc(na46^+;Em1MzRrq3L&AFn-oE`=3@l=pJ-7NAdvJmsjsxWEq&L0Z+9 zn0nbtJum@)fHf?lVxc~HyxwN&?GyBImDXsK>&rb_4u(eS6AClJ1R!6py;e6W^mW=) z6D6&p1lFz3qm==*tOhds?3_x>q6+QMdF+p&9nmTQy#rhu+V5PbMsZElPxTb)lQazc zsoFXa(27lD*H-G|Dk$|5twYcr4}8%r*&We6F)D-SaJH6tw9C#H6HFUY*l?joTZ-}m z*p%;_4}lbe2_XGb%-ZqWR!#NTY8}sh}V{Wjj z2t(a;Y;NWqLpB&~%;f)aB>!8ov6sR>z?hXmngP)^J{d&-hxpwflk&~YpV-|$kU+-|NdV#UZ8 z>(33q#rgv!Q$59iXkg33)yPdzybH`J$he@mk7Chx>)F~d?nWp~-H2iuM#dqHO6h+$CBYqwORGsxAJ#ol?;bgV7P%^XG~t z^N{gE7Fb#+w3&#GL#|q%hg=B@Xy!*06zV1yJX-$J>L!A-=jq3BhN#+gFpL2F_1wzz z;!vg+dtfU|b@Mnq7J$*L@~rS^BUODo=;oPNG0OFsNX~-?$n~RYhF*#6NY9dCv8w$6 zYZUyY-Ee!blIWvZRhv>N7Q0ZTUTNws9JZfvtXIvef+H(OG))CrM zmcrWF!v!V;VF*Ri{PTo!lP$akXh{$y6U+4=7IRY{8_*|~>80bK5lDGPQ-5y3kU@Wb z1V?9tHfjauh)26~8|V87?RAemM{eUR7jr~RsKcWci^+83MsqO{J=*WUGI-U#l+B5# zd(bRBCTdNosbiuq#T{D2JEsDweB4jZN7YZDi*>iU*mU7%w;WUbwe)a(<7iP@!!_F) zuGsM5`Zp8vC0n$A%oOcSLbSgX&fI7*mC8*W?jrBPocb+j4&{Q||W( zx&P5}qUq7L&>1Qdo}AA!3tZA=Uocvq1pACsO}b+<3U$l@`1w=xsWV`Apj)VKc$%TP zPkaF)qr$?u{?35`9O?Ea2Zj@-4tB^0t;}lhU0!fa+Mc-qDd*Q?dtc9{gVhM||Y}BGiT4HdL4Y8&rsanfpb+KfqMQ{{uZfc5#rIsYx!eOXp3RCLo z(za+@G+76MD9a(ZrW8U;C?0EFshr){JyG~sV z=0q~lTvwM&RUF=kStOW9+l^Q(UKdJ6!{KBNRb4hF ztVSdjT9j;VYi((3O)hJ0XoY=o%xQUkoa`9r+u)c9QrBrOXme<$9J4PHU4|bafs_*~ zQ?12UU>+u$mqp`s4b96f$)pNnEwC^c7mB?Flblwsy>)@_N}WL+r6S=_#MZC`TZCOlF~Ch@>* zU=HNk>6om2?U)p4v)bL$JL{4`rEBhj)nPof1K_24J1JV-$dEcJCN+`Xw#SRQGGD$wB9POrA(8iiT}B?1XrhNP{hTL&PW&b3LHJ!%$z#-+8f zIhqM;;rG9xNS#Kw?SD}8)_A1D@L8AEwq<8Sp3FjtU;D} zRyJ(vS#R>E!^Ns)8|h|FB3S`ik!VgYk6cTX7`o?}KenllM;oHUmIGT~6Hv-f8_Z@? zt2C2>J;z)LM;jX28ba~3DX@nP9Sb!yS_=ezlp?Bx!i_EUiE0ZXdE_{Ap%EIC;#``k zWGEbNi-*FteNC0uWAR-cf-G8NjZx^C(woFHPo+tY60|ifh8C2)ZIyLw>A=n{`>b>Q2grEUJWHk;|;M8ia19d1w+G3>bQ#jn5 ztcOKZ6H=BaW|}KM!V@e|fDds1=oYN@9f65rwEl;+=xrWJiy6~1T z<0~M1NDdasT2O0dIXo3rLDuq9+Ty~w5i4FD zR3}mI@N*p6hQV%bi$m>TMe7=3VKNg*)TWdmJt)#BHH20|B+~DvL2;^Is_XISA}AK5 z45wZWq8R_6wVH>6mTwvk&Q9^4s+=+CF?-@Uc3KS}o>11nyR&>PJomRvVv3q%cu}aa zF_dB$tIrbH1l;Rj&_jupbz-+uW9@l_qY;kRLSqvxQLNCG$BM!TcDV4E68QP-rpB0K z>WY!F7I3kGid|h(a~sUQ=r6wW84EYYtvluv($hiQvG%1L1nOgLtRc3_+6pE3(^i)8 zN~u|5pnYIVzi!Bu4-bLwY*AO;&2SDZKy5ikQBHbhwV6G$45H|!hOQr z6Fy&xi(#9fMmVgs%_~xcQW3%pSg+yAIE{8Z5rShOCIl7LvdzMkr8j}mN{Eq5#Dghv zY58$ikc4MMAv$^}H8Hi-PFo#o>Mz3UI&rK76mW{H(4$x*4@!g{S*&nyt$i4NVk|9< zG!NEF6_19=%t}kups3JMhkwcSS~vj_+nHr?98*1pslIm0#*I7{XkVM+MUbZ=FN(tW z&|#&);npzOb+&DEnl|+`!uHa2kM#`L!!4Z(%cE%8WGSk&>khkvt#qgn4qe=Gpi_PT zJ!#BkC~}$^Yvakak!~3*kI=MXn~(J71amsPL}~2YxT$YjV|x!)qm9_bTI^w|givU* z5OEeah&j#uhP6cX^k5kowzn9zlT^5*S?5wv42*qxS0K)zoJ+LqbNzChdBNnQ52mC# zas^^vr7O2l@NDyy>b=C4M>CG?6km1f-OxFJt&?m`_#g?+26?EKDjGIL>SA@x)(JknCNP^x?I{0XU_LItS8C3SZ2cGvbIyawujD``O$?D<&okwup9%$0`jf zy?x!(T46hdvm+Xg_4kE0VL!TcfDLC(*VYx*j!!PvqH{`ZElvrnex};A6+8}~J~eJs z^b`UoBIlJjJ)zJdwmTGoJ0v;B;*hkDnk*FS$RJW<9T`MwtRsU+jdf%YshO+PZs~V8 zU5RC(ISOtZk47;JIDdl5Z`jn1ZL$I;>Jpaoi2V@Y|K9r%CkvMIBODf9?ckJ)2xauDp-}BlG{_K?`|I;4)k>n@D1Aa_9=-q!%{VE ziSq~*tC!R)2o%06w9B$pvY8Oh+~Q&^63fD{I>)rxnWSlUMYw%9n>=0OxakCqS|4_fce{{Ccp&suRTgf&12%|7^v2p0+tSgHv* zxx)1!9OyPcC=qN!mxtix^kOAjpF*sK^5XbjoE%t3I+ot^KmkgJQ-7S>VayXt6l;~` zf*%wH46>qi#*xzSr4gb|a4}6u+o5q{Q&ERaLy7@=fF#4>Fn{f)q+`t;w)9CM+0}+0 z`bY;0t59P^oZ~dK*ylLQ+u$mu?N*A9mWH$#xnVxgk$=GPO^m2aJ=w zWY@y;J~JV_6v5SZk%L@^V;7vKCF>eOiF$D=!9%-9B<(6o%(fQptaT9N4I?6%nBl~HjtUB~n3 zdIgK0V>V#!VWLHGG>UTvYX<|Y1k6uIXEz?lq#Q*{<@i?m`hKBf)UM$t0gfdtJ>B@I z)H=#&i8tHNso({}mVEC2$~gaT2Cv`C-U^uv_W+0crOqc4sb?q9&{|mOVJF`Xmw_@C zt3L+AS~F)_TW!af@)2@lsA;8r2A9AIU%VQRC^@}gj>Pj4@!VK!vr$pVNbGhvv5tMp z!-2su47}3e$0WizfD&R>g>hzf)H7h74LIDCVTPO?2vw&9#wLW%CpMH|MU>CBmL&9- z2gJk9f1DG%E`|flVds=-)lMYBixiyOMQwv?9jZlbHzjJjDN)-^iP~;T6mAM0ZQ|?$ z@~eraPJ3Vyv=%-Ke!6Y}yakV5q}bt|`=7`?;F^Sj~Q_WlqL(tI$?BDWOoJnm3UOQntaU0)M2xv+u0V zwbkiljS`Q<>kcaG)KYwJa1)26SFLwjys~ z`^Zh6xQTv;?Q>Uaa}l=07PiC|w!{{;#1@9wQtuz64ll(+u*`Kyo)AlZQ>Ur206Tcg za0UcYRDshu}U^>!h=yfs}VB{dtj_> z6a}7&h{zhEh^5!~J-FfGk?VuKe%a3_L`8dVI7_JwJ5J|>34_yKx+1I|oa__81wMwGd(FPuZ+kUukiRE)}hzeFy7-KQkSbWwf zI6}mC)nbh9-i%m ziMxIs=o{tLBWbzOly#jv^Q;LrI~ zjpuQxUP(z%{qeq1=JO@tnAe5q01Gv=A4n`0Z=;CmeiWrl5_G;Y&eomt4rji?O-@8Y zF?d{|W}K5RfeO$=qW_P_{m^&op}Sb`v6W8Z9S)ofikCQ?&+_CLw^%LWc|?jkp_H)Y zDL}X}A`i(hnd1&Y+cPP(d|Ky3>EjyON!gNE6nXX~ULuoF`Dj|^(@Q6x&hnKGSt7-c z$%2D9oE3r(o)scm&t0YX*I*to;M`4|6{TvXY2uY4xs8!z<&jUK4YM6@hha~dQC-M` zk9jg4vx~ze=_}v>B1MspEydd?_7gjL4`Lyb7(D9}{)+R!O%_s^oF($?g-cP2wiJT( zl*fKqPHu=C8>ZBDD7{@u@0QY=C48*h-b|(a0_)i@y&}oTjVU@ zNr?4`8;5$Fkgciy%vKgPwVC0$b4~uwbY+dn|C+9z6P#gA?(4++J^h_0m=zm4dbiB) zz!tl6YX$yi6@Y=REgRP$UWb#rfeQS~^?W=gUrPWm*Y%z?v!cJZVr|VVK-&8{y5{5m zRL`1Iv9WR^{)>C++Wy|D>w3+K^=3tL(5%4!xz6tZ0~PBw;;aSd;uRY@d)5zh&94T? znz$*4K@yL#*&T=NwdLdqbbR5^EY`J*6yC}~0AZ@D}X$a$8BEG+B zTW6lL@kI?9su+)yxCx45Psbrr#N(J0t8(szLt(5bbxGksEB}YI_kfS0YTv(ScQeV( zY?2Kmlq?9Fgx(CvCRq?Pv{02^M0})J5=5n`pr{C_sGw3TAUx;Rh>D7c3W|t` zih@!^je;8cdtI~Ffxz$i{onWf{P#on&biK+``o9_nc3NyUTE=}*LHa*Keh|5AN203 zt3BRbS|{W^;j$?gc*{t0uYf6k;w(@;quV2yiSj0+!6)AH@cx7PYWd@JITNq7#PNG1 zOa!KQ^Y#CUS4YZlVV>6wte)Mvb&R&)0PQmQl4y@h#$IqfE|W)xnCBsQW7a(9pymHQ zg7K?vK5OJ3eDG+!8R@BM-eW`|c^^IpqicH79N*a+y+>fwmrn567+uqYbNn~>hP{F4 zn$Ij@;+kps+>CCt<3GnU6h+v4_$-nx=^1m9ZV24yzs=V*Jvzco&*&0rXcB;Y&PJE? z`m>Yg*f%8I7`O@PPIy)epTE&Hy~!NshTx4UHzm)tZ%(=;a4SjY<<@hInCk>n!k0%e* z_yq9OffM7CYsB(-Cn+bzr+CkXsXUenk0Yq@!6U;@N+0yzrp;2ZzxYphG7;@NC#82R z)-Thu@A$n38DK-7fE79^eaQ1Ceyp0OkQn-%6kM=ny)JFS$ zq%g;PZPf05g*nb^qkVo;m}9#(>YwlM;3o@zwb(mre6fJ*j!mXoO>lp3jnfZaC^>dT zw8nz$zutCS^PuRh1ZxV3^QW3h&13cnx_6+gsd)GK{x2s7$JY<$o5|yf`8uG6!XH^+ zjd5HtUlRV8A4DXc1?HmSy;r=&60f6o(M@-v{-{S$pMK~g7>2$aWOy{gi04>f_*#X( z7un~j^W!f}Jh#k`!5?HeKXH8Xw@*A5%a6{(naSTwdTX{F!XQTk$)4|TX<0dBD?KL~ zdRxWg)pTCEt|E@cUU;ZDQY;rQ5w8|!iR`b;?{1NE1H-FC_G5;(i$92bS`_sZF-^=A zv&F_@Q?a$!UMvwii`~TDVt;X{c#b$myhyx6oFYyauM=+&Zxt7acZ>Il4~b8R&xvcr zm&I4bx5RhF55-T!FT}6KZ^a+QU&X(~0OkqSt0RWRI$}dHPi!T&7kTX9{%43~;+f(Q z@f>liSRqanuN1EpZxH8+i^Qek1ETltLFE6O!q1DZh#SRs#1F(z#69AE@q6)S@lP>; zr31_9inT=VC4$f!E8I+ME5^jr#I9m*aez2n{FiuvI6<5uUL{^H&J}ML?-K759~Pey zSBWo*mEv3Cd*VmpZgH=8Nc>T(7XJ~G`GhyrN1B)=HV|{gmSVnGBAzbx5c`RP#gXC| zk?)6RewT@SsXfEjh;u}~#Gd*>af!HGd`x^+Tq~{@Ul%uv+r*vX7veYKcj8g;57Cb$ zB>iy246&ZrNNg&$5evnRViyrFsq*ag7l(=Gisy?Li<8Bx#W~`9@h%a# zxJCR({9N2GR*AofcoKl;Z%E7%`I>RoOEd9QF)nry`-p?ZQQ`&SrQ((1Oz~!Mp?I(O zu=tGlytqN!ByJOTiF?Jv;?E*q1kQ5sy~t#Sm@Vdtt;LwwSu7L#izCFb;$`CX;!Waw zagn%0ykC4od`es?z97CLZWOD;T3Ar99M6hxirdAn#47P`k?*+XehtOeVn?yJI6}Ng zyg^(nR*ARcL7cR=Ts$nU2_^J5#2w;K;y+?@oTzjExY%2~K%6YzBHk-LExsc1b;q>x zg;*u}a4JN-wwNcz#2(@>@gi}yc!&77_@cO3{8T(F{w1d4M1c7=7W2g};vjLHI924! z*SX&V;Y3v@i)=MDIE7}Ahr=Zi)V@Fi4(=^#f9QS;s$YxxKI39OvW0R`PCC! zh#kZ};yL03@fwjY&*lF2iz~!e#Sg^2B42*X^fngAWL>ej7#DksBgKow8RC5L-{Ny( zrMOM}O8i^&-aU(a^J*vZkBL3RG2*4-jpE(nYOzw>DIOL1VnLQGTkIhY60Z{P71xPx zh)z~w|3+e4v6INxOVR!q@k;SVahdp(xJmq6{7(E+tc?>C+RG73#987J@k#Mzaf|qw z_>b78Zo*y%@gZ@8xJ5iF*2N_P=3gM5Ar2SI#p&WL;=SSv;zseX_?MWDi)*ysSj-o@ zi06vq#aZGa@nLbT_@;P3{7tNb6FlaVD|Qt7ilf9!#B0Ud#izt|;#ToX@h345N#v6y z7K`J=iQ-&wiTI@Wo0!aZCBxrF;u+!qaf~=woGmUESBS5OKZ<{g1-Q^k`)7#5#VO)U z@g8xF_^SAcct}h=C1J0FSSJ2UyiA-aE)$;+^KdDN{tOn!i&u;D#K*<8;=AJK;t!(L zIAO1rm@5{F-Nm8eh2oXsTycr`r1-M9Mf^FHRiRX%! zir0yEh!2RX#Mi~`;@9FYVoF{j-}+)pv7^{m93@^NUMt=%E*IB}Z;M}wKZ$`RiTtv} zred+!Qyd{yh*ycXip#`j#J9yAVp`KgK8?ge@eFaGI8q!ZULsBxZxt7a_lOUR&x`BD z*ThZYd*XI+m$*mVFIJ0ovxMKZ#l~U>v4=QFJWurA<&N<_UEv$WMdEVt8Sy1?yZEK} zz4(V1Y_9$xo-Xzmhl}Tnlf-MqTg7|C4lNS)`iP^%v0}M+nK)CNFD?}y6W5BbitmY^ ziU-7>MP8HSyciZ6iY>)rv70zRJXahqUMbEI7l@CDE5-kaTg08>cVq|4`bpv6Nz6TU zaIMsjy2=(Ck?^;b!tKNo66rgW*td^3Li)cHzDS%%!tPY@dJ_BJr1*QJFB2bC{L_km zMf$7ao6_G`_(O5G^n(h2C;mbrzdsf4piJ~9O{^M;??4H;v5p`<}18Fyo-e0XT;Sc(p8G@N#8DhO(LIz;?L6mAhBPtO(H&3Y(yfi z8Hr|Ph)X_=NQuzKSR7;@$(g4ATA}5emM#I&xkKee^uel;)f*4|FO7_ z#QujA|A+K{L?=HHA0}bHq1Z}#zKC1#J-a=`fzpSQ*somr1n~;R&rtl$(&vkJDSn0c zn)tE!qxdTc`@!~!{8Pm`Vz$_bL^0(2%rC1{N5b?+buRhNcFA=X3=ZQ z+$jBBg|~^jNcg=+tP+0_gGGt>bTN-aeKZ&I#hBQcggyM+z~f-?Y;n9eQM`eKy_>~_ z;$7nXBBzdr8>aFII_1#lJ|{3lt}qDQ1h!$<~%tNIJMrO5w9e*c~Je zmwusmxj09>gGBnp;!^34k|~z8R^e9_|Ax3(`X}Po(hrJONn-zG678HxBA%=JN*pZx=Sp9!@IB&v(w|WH8F3>Cdz(q* z`?2&-#eL!d@kjAz@o&)|$NngH3JE(I3TKH8N%-HK%)&bi6~^!8z5RNKeWVXn_-yfC z(km3cM4U{*-gSzx-HN|YTq%96xIy|G;wRES6ZcF1PW(%{59bgpZz_rWYm+E< zuJmSNYw0nC<05|IkhCQ2dM1UlCuE z{*J=$i#ti!{ao>fq<=5|u6VwPjp;H-)I*kdikKs|A(5_tgrBEN?<)2c`->yQQQ`$8 z_P?0K{#Q!BTAU-!6&I68zm!D!C#63tz97CVZWK3(+eqyHF^T>6OaE3pDprfW(~u73 zx5ac4`)85ZKPtV6*j8*Wb|R6!D~a@HNgpJhqxdn3pCtWq@ha)F6~0NlgM{6?6#t;~ zN5xf&Ung#ozD4{<{6zekguQP``1yzQf5fy-&`}Sy#0ZJ>Q4;C%rN_jsVwu>VMEap5 z(vOjTfq1DnS-gfs`q?DX-!6TTxJ>a6Dt?vp=f#($Z&Y}bxQ&F}j}^aH`hM|<;(rsJ z&Pb1Pr-^mNh}evTy*4ELj7#q%_7Tq#hm%NuE{XJ)NS`ELC(ah9UNpZ#7;Ct){>gx#q0CStzgi^VeOeZ;}y zaB(z=!rqCQ+Z0#H++>#hXZ^n@_Txr9UV>B|ayvA(8%l@gwmY#UB!n zh`)+{3;RWNpCQ;l;l?5^PkQmVoaC{+h-I7?E))BR=ZNQtQ^jfGb>eLC7V$Rm3Go?m zow#0nOMFM%A?^~t77vO?#cHvRFX6X$-(eKrPb%!)cZhIXg}wU@5soX|N%ZbJgx*tO z?><9>&r|q9alCkqc)d7RoF{ts6Jq}d6!z{PMEFI8z553denVmJenEskQ+S_vK>SVg z?h{11bTlyAx3<_+Y$@i8G10r<^%Sf}83xZ4$B2`~E5w_`Tg88i4~kES&xmh|o5c^s zk45jkKIFSk;cvws#A?yIzYpocfrOu#VpFlD*ik%P94HPIM~S1wsbmD#U&Ncm`QpFD z2gS9bcV8a%t5kTSxKs4*$3y&g3VZkAA)J(y$S){{#Z0k@*h1_eb{5Yf>*2ge94B5R zP7`N{w~LF!rQ*NERpRsFTjD$7=i*o5LD9Q!4u1Ttuy?;4!dW=ipnvtnwj{21v=`%I zC$XE@Qye9Z7B3RL`{H2da)qahw}}hICE|VJ!=iV89QNO!uy#1>+a*g+gFo+EnqzroIh3ST37_rXEGP2q*& z3UQ72vbaIqA?_0Qi{FY)5PmyYpNUyweX*t3RxBm4Z+Ee;*k3$fEEg{mr-)aJ*NF?n zJH@BO=fvm5m&DgZ@BTdau~XsQ;t%2x@psX?Uk~YPp{(@3j_BRDhj3KkLK1zmL_A&W zDh?OV5yy%bikFI$#kt}QE)<^-pApxH>%>ZNqxhcqfp|dl?u$ge zM-={5^l>agx5fHmL$Qh2LhK-R7S9p~iRX*u;??4H;*H`h;{D=7;*;XD;tS%-;udkM zxL4dSelL3Wd7@mYsfqGsi1ow?D?o!^Dx|7}2{wlsZgW~hz zOQLt*DC~To@HgTi@h{Q4j}+;GX^HaSr>S1MH4$5g9mLM!S>hmZoao(W3VT;6e64tc zc(eGB_?Y;txJrCe^zKK6z0VZ>Qam7f_opI03CBA2x1g9Uo+7pr3&b8`Z*hP)L>w<( zDqb#57w3x$#K**^#8u++;%4zZ@hkBg@ptiWu~s-yo;qSfF)GHyxY%1fQ~Z}WR-7VU zDc&O9Cf+G75uX!Ri!X`)5kC-jh=;{0@mKK=F`SVoPo~&hY%QK4b`yt*BgHY|1>$tk zyYCk5?%j6_E|mU|_?Wm(Tra*aekkq|KNr3Ga$&Dp;eW&c&Q;mZ>WK}+_F|FPNh}qI zh$F-a;zaRA5`VXd3&cCc$Hk|`)#3}{yP|iWFSd6oyj%Q1JR<%sdiMciJ6t=Ff2P<( zY$0NqW%--x_kB37)n}N;YZAx279{4#d=h;)PQq>}iTdhAVm&>8#QDPr66Zmq$teEA z$2(q%ST1;BOj90F{T^Y;W0XYxO++t$gxe_W`GIgu;ZhR*br(H<5bme2=NH056dp~& z|MSIiae_EeoGQ*F;oKZ?t~gJ;LtHH0BQ6t{iw}z{#5LkN(Yv02d@2>*C~gwBh+D<& z;!bh5xJTS49uN-`QC3@Xgu=~B-Sv&8x$f4j~27GfJQUyO;~^$Mi( zu2+D)r1ujCh(p8?;wW*nc)mDMoGMNeXNWV!IpSQ=yS{<^?@@S}xLkZ#Tp_Lz*NN-J zN^zsON!%iC6}O8!#ogio@vvAW9u=#_KgA%gFTn3qF+)uBTvs?|KU8 z{mv5Xqxxb@AsAnk5>46v0R)WP7`N{GsQXLTydUwhqze0M_eX8EXOU3SDFR`EK{f-m+4N-Wsc)nOJdcWsHI`6s=I79kOagKP0xLCYLTqZ6T9~K`M zpBC4N>%~fOqqtSvF76a}iw8&?9}bIE;!&|${8RLrh}D>2a}>SSofG2Z%$&5#lJZT$~_I6sL+OU%#3ueU5mCxLCYLTqZtF;yC%VxI$bb zt`pabo5U^RR&l$yN8BeK5D$yh;-8|0V?6Uu620GzBJ5ok1HJ2FU_-^X5WU}zLeEz? zCYFlbMelc{NY_u{0pbwRyKaW~^A#=^Cy3KXtRH5GGsQXLTydUwkGM=+E{aj}!wOYA2O z5Qm7P#q-5-af0YwuY*6{^*V5-^f}^Oah`aOxJ+CwJ}f>iJ}s^j*Nc_nMsbt4McgUw z7Watz#47QqSS|i32C)|8`Z87YekY6VEQaw{pTs)0p%^8x9z5Z?A=b5RsDt?=)`#Bj zX~8(dm|r`Ir6lH??qV;J{aqYDqWy=6-tTTv&!ZRyz3bTUw+H(RH1B#Y{4>{Qz3Ynb z!@C}c{Ihx83Hfi~c`@=0W`M}gJ3l}^Z8H&uT_mymZM1%e?R zWa^l);MBCo$Mz-C9DicVe|`4M@q{%!_8uH_JnFa&^Q@Tv7H6Is^Izli{Fwh1XPzYE z#ZA79HQDaJJXOYvKA%r=#{>5+ybM+DZI2l{cJc*RST$nt!sMF4F?a?dAM;lu#s5?$ zR9t$2v51DX+TqTru`?zPRrH^M~IJqdQrc3cL^d zdd&}(blxWi|1(`65%kU-wdsLz{4~d35P$z~>Clb;N4{}r=7U46_vwcJYx*|<;hH|0 zbo`FGX1e7FW0)WNm~_*j)J(SmVV)nFk4d)xLd|s35a?tQfhOJBlhUn0x~cyq-AZVf zGOSX?#UQYrSYOm>kKxbpS2N!hXaJs1n2*VK7lfMjI@Pd;spy!!->_ZN9@kz?DClGC z{fux;d);BLJ~aA=Y4eype%D^p9@h+yBi?+By;?|A)7~i9V|&mZE_)rb$M588+Ut&v zxY!s|ItKY2eocE5YS^o#bgaKKPqN2jV=6Py$N0x*4ArzZqegjgI5_5Ch3uIo*q4$x zPMmD-f|KkmhP@U@#PZguVUOq1_;>764SRo=9t$3er{^GPizQ%jJ+Kv+57Wo;`$ryMe%3seItAM+Q0G|%c|rgrVs7$@5htU&3qES zFEfdhhUxxRIuo@8=_W8jAJb2NhgP$^LoiS|XVJeV_%r^6&_OZh9&3X5(-v>R1NDfwH7NpO#zEdn2oVpMB&U zCp2+l&u)0a>cq7-Ts&(`?a zm4CUvsBFjn{57$@vsN@1@2?0{h4Xxid`o=yWzM*xx=rb_7hgRR$oX{D1K-veb8G3n z!Q^ehy!vJS75VEY_Vk@ry>;NUx1Ha&t7Z^Ng z!Eg8_Q0w5QzT7}ndTv1-7^25 zU;o}F_pkaQwSQG(w|~`nPX8)jdZ6Nq>g6kES6j>RcL)9| zx8l!gw!6B?9lNWOmM^JJs$8AhuWC=~?COllCDnn-v(HR~Y9ZvW>|b?%u>YadhN)E( zQ~Ol~k;)IhXzG@R_9v&A1j?9)h$=_KXi-huWIafe;nN> z{dfOQ?$2ZTTzDj-Z+FCPuAZ5*x!Q`NZKD5o`)B-L?w_8K*8K)}-?KW$^8Hw84XKU} z=;JK3d{vEo{vStog~vU*LreeN_oM&kF{BbXtco0R}NI&&OX60YK^u^OS|Gg zk~?v2XqsZG#3`u`G`{j+dfpF5FtYPz zAIX@TKCQ6Nn?E|qt4oKKH#-yv3?4nWd>(Z4pMRdJcxq+;qZsYwx#bIgOCRl)XN(?S z7I=FWMq{lq-_p7hy^&acPtW8stHr6?F0OcJW&bK`bRvED|Cs)c7p=TTW%*@w`piLZ z-FPs$a1Q$PSED(`$BoGwJEyvhH`br3Xt2`DW&Axo;q}af*Da?d_j&b4$9HS#!17Qx z`aBap=VLrie8nmamU7OCuYJ8DsVwtFjI#WPR$5K-DxzgM<)2Mr$re{Pi#}8_r@BRS zb#C6+yo#^KAin`tbl0T#D|f&HtMxbA5L1y*tPKfU4Ln;`>nU4lEvGzMR?`}7w1|41 z53q7pH_a`NRxGM`W74aWz8sx*tPHv3gDYx=e0dAer(5(M;IO|&^8@IuU8oQKO70n&N%IyKIg2eEF4swmvPyVj4oY4>cjdVW);-Z#h5Xz*6p@ERFPBR zYdvd&JH2aFso$OSRfVrr@2x0V#gm-vtvgl*T4#K6M|t418_F}=XO!Q&YHY>hJp)l+ zF82(aw((#}U`};Agx{I*>8knFDf#!|Z%%dFXkbPDD~mBF2de(@=dI)s0^88`R#>g8 zwgy_a-Rf_hv(?x7)U7!cdE?)nF}7mcknIOk3Va1VS}m|zf3_{B!ks?u$c?q#Ngwa0 zhZ*pY41)C0YW4KCSNG>sgfORP1VWR@Ah<(XDYm!nUtHZPqvh(H^7?0DUdia?a0~}9 zZln1?zW><%U~W!D->U*u zzXtkF?lbZJ{T%1sc*nTMJl!SH2EG4l8+5PH2F(XpZO_<-diH9`YF&cuQ_(KHx9zRy zyK?)%q>SA0zSCxo@)gXT$~rmi<(!Jjyv@@uJMvcT&69k4e5d)hZl3-Dj*fZdZTl?x zEh9gGxoS{#wA5;icJJO5Th6Dx=t!qUKOE%(qYJFx14p`7=jOkInko&vGYPZR^%!ya zf!3K@eQg(4HyNEg(*o$j4E(y7>U6+lx_oYIHs7vqiqY^?vw@-^{lD zZ0lG1^UBXbtM1*3lJKaRVzvBi+XEF=%UxTSU_G#{Iym#8TWc4Lsi^G9k$vg_lx0e8 z#bVff`-Hm7Si_oYV`?aW5!M@#m5ZvIM}4h&ZrxS!!OHB4&C@IME<>L=#*$2@6@wN12PfkBmiqgD_kyo8P`J?3XexLQHA75iM z{%GX1fysTg`*OZQZQy=~R--X%oiJx*JXn#K`C4S;a=sm~I@gyIE!*YIkePd|7JIfe ztO|x3pvGInhu-W%8LM-xmRTG8If0yAlcHsuOB1!y`hV0)93!(0_WOQo!>Xk4x1JSW zj@4@Kwq5(J7OS?6oc7w0nY9KbZ}}(~rH3Q0$|?6({p#;Me&pm46WwXPR;e2Tx&GW; z6Gvh+`urm&y^UT$i%a1NJ$iKOo%_G47?0J{18C=F7Fs+9eaS*uFt7XI;WOIfJMD2~ z>w)9-=vCRqFhvxWOS012pCMPJUnVWGwIld;o27>-xOT;`aro z^7aM4UELEg@8igv+#!1qWBe(lOk9p+$!FHTfKrmpXC4G*QR<&P&685_f-K7)v?q2U zQqIQJk)$M>ucG!RrBs$7dG~BwldYeLJuUlQ{FnR~{tNKipp+(ANMPAGskM?{;eXr; z{0*N|+GL*1?fGY5J3ngzw(Xrvv5)_8E9I3U{Fk&Co58;6ya_e9K8u0TB{(+-_UlD| zUO+Vjf){m#Q$c262fsj?6ZcXzX_JABR!$Z>(s zc>o1oAYT{79nRhyVpB8Ys6!Ys&X9S%1F5t{XgMS}z_M_E)2sj_YiK>9ps3p#}1I`zy zz2YpB^XlbpA3+5M~}=XDGXgmbOmbFb@RoXKD=;|8NyAmGAxX~p zX!oH>P7_qYuq0DD7tmHO4hQ+Zl!=U)T=sgxZ50 z&>_CG9X_}5E8AI=V_92MoE|9jwiM@6jDrtSoT2%a^XAW zDa!XT;!u>GDb7ns@=1y_0-mi4Iq#$0Uko`Rbhej5P6`_Q<&eW4cr6b*zP9*{O4#A! zRUQmGNigY38&b>%7rJln(_omi!_F)KIUeCD+DX*yKq$6}?J?9$q=V|qv zz9{YVdJcb^cvU@TT+p(vuIJz#i`I;KPA2N*ntINXj`$5(J!emC{6x5(^B!`TSKi92Y?<3HL$EQ04aMeb0X+x173FqqpkdA*W?e%ev^0 zI|iOj#5GR$JnS-w8+-`vWNv(bzCMK;7oiTOa^p8_T+WR@{HOqKtjEU8I5v2V=6Y^a zVPMYU#&~!;n;Rcv2+ZNetC(7vN_~?r#_q3%PM8dhjA{ z%tB2r=0-!zV0Uuk9JJ;1aoBhQSzN`9>(QxrImInNzwmM6L%8ARMly2eJ3QRE=toK1 z;2S_}ZaklhiIf{#(PL7$@hGZ2$c^zB;0`x_N2V?}KF25xaf3J0rE-IJSEg}e5jsFR zH!eZjhq=KAR%CGFZ}?M-8_%MZYja}^24N;QCZOuFxRHyJ*5O7h%2N2@JQCv_GM2j; z{`k2u5LxieBQ9?hPvVA+&Tez#Ds=v2ZoJ@CLcnt8cy)n|J?N5t?B`CxIN^R)D76<# zc&RUN1mTp{s2kgd>CSSRr*Fb!mbwd$PfA^g$!>D$>*zL9QWrKy+ zJ%C>#RUGL_4v-6qrk<&9o%{3}1jhJxIqpDJ}oC zzVw}R#;Iq8??FNR*GWjpu+n?>u>3O>PD-`H4>7^@MhIHzLoEL+1$`;7i12KM@y&1g zK+8YJL?>D4!z{c~Cy|{mV5N7n{5P7Q-%1~8`EN2opOt==<)3SUa4;jue-#cC@VnMn z%YU=a{se`ob*1IM#h1zgSfT6Dd;Pa2%2qom-M`)EJdWX%={-JYhp+ZJ1gy**s7(LI zzS^%KRGRr6#(;lkB5r2pbToIWi8Hhr|RnU&89JMz?dc;VY2+KD-Pm1_#~KjgW4I zAH{*lJ;Mliy%L{)?3Nk<)97ar2wjYT7dBmpMULCe2zcXDn^PflHv(Q6wHQkzw}%l> zvUiwmnGsOCXR|VU8Ub&$!g~)bx0ey{8m#Ye1aW&C0dI18AIAo_j}g!yy_uq)5m-BZ zw1k}!698BE{jDXr1h$V}Akr7aE)Xt!&-3JAacrFc5 z?VOE;hg%*EvEEoalcElPV-Y^YZagL0fHS1mckX0woN5Hr&T=|&xe-u1bz4BV!U(9H z+31h%l}14A^kWyFZUod$l%44+BcOIBqLJLIjey!&&MKc_1k}z-ELz-ajDXrHWIJAK z1k}#e>?+q80ky-2%eXU*fZCbS2Er^OBx>i9s9lbNN3N#_mqqKb;E~7Jk!D9jtT!x2 z+<8%F7Fsym9tU*ywrE2h(UN?Pt?;v0t+}@wp^+8t$`p4P;S`je!U7{Sw8FzEEHpv` zD?FOQA|phs@OTP~jgW1H`4lMkP9xN}!q+mzT}HsND6cz&yNyuS3b*3ibdM40Sm7cH zON@|Zg-a{E_&Pu=q=AQhwy|E&|AKu@T3vYTdJ|*b)PZYctLe%-1-G@&xbzd|F(0%fFzh(sz&_fohqc&g36}gEcajmjwSBSudXo#8f@bXsFDM6y}J$caIHU|$>jmzWBJ4V3a z4M&sLqxL9T^y1#o(c~)*fcK&y=EWIdXVjTSi>+!w-=!&qzn{jGvOQ|wM+02MxjQta zWY=WQBzkX5r^Wx^Uhz4su?J!r~^s>+DEUq)?C{Sp4I(cK%Z&-FuO zHWc@8G{hLIE;IZaf8HTAg&7=;I;Y{d6`s%#>3%sWgWry45N^U5{tqLd2n}ZX+^VQO z275;?=8X4KwEiRp{^XSVS2T150*RFjWiQL~EH8as`oPx+NUS|G$*mK0b|Z^yt|_d{ znd~=BqM1KJ%4o>T2$nC44;XX{qnS@Llvt_b>@71f&3a37wolr2 zBocM?W%Xe2#%N{;M~m*hhMd}#`x>%~KJ3eC#UAu(G_wd69``k5ud4KA6;a)q@c&g` zRw;wq5(Zy`rwo1&&HNe7w$ay+{RX#r4x{>cB9Y&pHHN`2qM4r}QIfwQ`^HRv)G zM>AiAy4>H84T|$mZwYr873kISX;w1p*QVgbB*SqprmmIz3u7pR8glXWPc*>R!H@{& zI4dBB=f@$}%4v|OdJGBPfa2CR0%nUxnIbbMu?+NKwut*7WElao#e=6psAB}4820OL zxpj?z+2WJ}q^M^EoE-M<)&pxxBcN0mc%dBoBe)b9$eAQ9C$Ws1kF$BVQBLR-#L(}i zIZiip!}P&Ju+%gACtK-*a4OK+gmLCNc!1@$HDR2(4q<`Q)bDBTe%&T3+rlT5mpu zGmU`On@ZsXY$m4XPmz>~Z#oR$TA-YE=&dzbZ zM56Sw%CP>^{ya^n#~enPibR&baArT( zWTBj09ExkR|S_C0e<&n zSG&{*@cTmgeVGy9_dYJwCK>@9{j4%{<4Hz<-_P*SI@t*DdubfP6eA@3zA(rB5B+Y+ z<}a7uM=&nksW~B*h<;z4fq zVVIoV+l>IPD!EX(!wB%|ZS3bRFao@KI0eE&BcL`1^+s(jG6LNEf)mSPBVgJX!W4HJ zA>sGj96J@)Jt8)yO!pS~eLZ{FT{$6^h<@Lf<6MJ8;X9e=eq#WBFQu^D2=M!U3J(|o zGfB^GxJL1y5ipFq_wJ4*m=Q3Q^y-fkj~XH2)sh_hL3%Zgo$6kBbrrk$V>u!EORt{I zabh?;hc95?Twx60Ivif}?XEOoI5n~a304^amH8#d$7&;>G7qt#)))apYF!b8wMIZ? zPNML<5zsZiErjrb8K()ipUkn(hDVVHxzu`EZf~S}>vBRY5Z$iKaV|%q^sa;8=4-NO z2fRsqeU8192Kut!|3?Nsp|=}zLNrYS?_kDE80clW@1AJjEzEy3(1QlvmVp~FnBDht zLNrYSJ93;~u^H~f)zeNH2quc~L5|%Ji@}H&w_OHSBhvi@bC(S4$#LRH6mCxgU*$x+ z!=DW7&auy>0Wa?J9PctuWCd$)Z%&A&>A|--&MP!vN1=abY84&o&!!N5Famn@@S&I= ztBin#c#ggLMWbfA~pK=|7Tw%1g@v$v}8TQ)rk@j9IA z&ke8)-n!>+lOn}R{vO*l1+0YEG;_)@@WQ8YzIndc@$=K)OChW?0?r&+JohCd;L0ja zFjh3PFUH=HE-ewas#)S3<|U4{_02*-#4wB3n>mehkj1GyWqH#Wz$r^Hg}01=Gv3Y= zHW>kDyxl2mHUds?`%-wv2sptVL}7~&;O5yB-ZcVFa7R;k&j>idUCrUU)d)DBeVM{G zBj9}YbqXIC0q3*tQ25XYIG_EH!geFzeD)g(JB)y{)$b{MYy_OG4(|rx6C>c{^gIf? zjDVBVizs|*1oYI)DC{-@dg_%FJ~INQy6Y%>ZUjtqH&OV)2$(f%hm8T8oNl1- zoe|K|Z&LW)2x#edDg0mrwDfigRYt(IjZZ23XaqF zuM~bZ0-AmT9Cv>;0-Am*g=!<9>1R;*%?N0EJ`dmh-3VxU{fR zY=SCp$E8%NF@P#BqL6L`RCy-~8Ad>r#7B1S-!_o2|h2&mzK6dD=pWDm` z7&`k(Av8Avs+x$z79;oy383AQKn?g?` zpzP~tqn8m-_SsC)+XyK8trYqg0cBrAp|258c0M4+?PmncBOg&X(+G*mC~j`gLpdXN z^Ab^9l`)#D-?N&BSWQ-1miufoXDt$C^FU-}^H`CT&50$L&Ay(R&6>)vLSNJVfaU=j z#8sx{1P9h~N~O7cV|6u=&+~gwH~DKPpIEyja%}f!zfmnx=t$14nb2G~juVApKr#!79Yq%AhR&UylAmOq4PB@E{sDz4AC?V#0s5@XyBP3^x_i@=-o~<(7Dilmj)hejkq&pAfHofkHQd5)4-X9&OsWO!RG3J zqJiFpb~=VZWDC~ZZeJNdufk=W!Vpc*dtb{d)&(`))$7DIemP+(0PYhyu;b)jT3#`P-s`tzcHBUC4r}8>3An8(+=ktByGenjdX$a-u@PVn zjsH%e%@?Uf(%4k*Do=hJ;O;C8(HrLZWudcxc|MI}xw}^e*uS2m6JMWb@v}nvd0PCL z-TMn!yu2L(-xP+J7cG8Y=zKtni$c(=jDbW`9V)bcrGYgZ4u@snR$j3BsW3#-H1J!Y zlL?z)7emwi<3s~L7us>eMGj&5b$^wC5Zm;x!VpcIK0_BKUat_(EdSx}2uh^A?veJrgW>L@%2{ogH&HGT}T zPX^k?oKA>~v}7xsnlK*uiL+u+EKJih&?%NSf(D9tSULSf1M!%14GnzBUer+rDtaPN z8Vl1j-E1AR7himZ@BP6OY?37NRK{ z7#wqcpn-?k=0i_3&_8BpVc*Cw2XO;s;N@Nj43C9qng;$AbMlcWd@fH&MxSV4WX$H> z#E~La%qSVSsRsgMV{eQIM2%C*qlt#>q`Q90GwqY||i^q_=Yt-Jl<`9_?DhndkbRrFW5UWkArWKYVUT=NcYA<%#2w)7;|Fywk9Mf5+^zv3F!24`$1i#aw#(cr3)snZ zu;#=po{HIgF{vUy_j<@5{1uXui9#y#!>ct9%Vl; z0!}3t^0MG|BVcbd@8+02i&<>uVA-Nl{8)s*N3jqyXBMBuoI0qIa2DsPFN^_Xaa~sk zdyIfAK4BGqX#^ZU7N$e^$_O|_J;g=wUL#;R&9{BJ`;34^(gGYL+^>y*;qeap=Ql=3 z`29)D?g*D6T}l!6sr=5u8qqxv3$aA>`-hk_jDA_{QW2sktCPQf+;E}NZ2A=wDHY&MSdkzxd#SYApYXarmsnohwn z0xk^Aq2L+;7lv-95HbQTY%HaaY6M)^c!WZ_5wLvvlyhH(5pbo$?g^o`5pbm=gF==O z(06{}E_IB6zT;zOs%HfBj8qEQMnKOf>J6cR5in6=jQkq2yP=69m#~e0(-^stvt6U2 z5L=iXp;?hLk?qJsr`w|F*vVkHnDb;SBVfsgo{?K*-${#J;wD9jwLw`L61FJ{F)vyy zEOL1DFZ{d^1- zU5j*Dk#MPFk=+7`BYcyb+esFSFeAI&i$ctc7W)-B-D#1pDRa+~MJ(XyQm-Prf(9lv zMqD2mm`MKy6oqJ-21XP)H_*V%T*i!)0j)NM6xmPGK){cs zH(&T_mgyoH;F-~86vM4Ju}ou%>_2Jo{Vc?dlf|yJ5xBT0#Jsp(pNeWmnZw_pA>AvA zj^FKifQ#noMnDflddt1q2)L^M1{a>!8Uaom;KB2HBcQ|G!5MS55inWZ#i{j1BVe-X z$ob%ABcMy}$9mbl)d=X48<}Fh5#R&PA}6B#;dEp)J(ygSIEx(G9f8}5LM$`u>h2=v zCzk9A&b3R9*A-i9QITB_EBVOIx`?||Rr5LxEJJf+FB*6l&5cCin@@xO=y3z#yI7%* z8-XtQ-22h~w77%y`+zL=p!p|?Ld=U6R~0#YMPIl-n{SN_@J@&sTwbg-7BPlk@!2B# zWm@#3Jnjlv^fTcL=n%5_pCab~Hq*QJz)dQZ#sIz;KC}N>xFBXaL}J*yRAi^2>qcg= zkFJ-++8nWO7KNA>eSEjb>4-!LAKyRO$E_xdgpY3*+2_$>B}@H|ERJRG{-7wtylC;0 zB4-{p6Fz=w3>Y83IMK(CitLrNn8arPSQZzuFMe4RVqQFI94c~_pi#naMxh@z(-n>y zA5-|=2slXWq40wdaF94ip~?t2Nc=?MM^wF~1rC$AoJsR2u=ugas6SHv+EwFQxE@5z^5GaPMD{{U4Mwav$fB{Y8o8 z$@N?=|5X%XHL)`6Vy96jRK^YTJEi#e3g}J>juB89_fZHL0cC&P2O-S}D9HOvk!}R^ zUO3?^w!6W8Y~<67fH`ym=j~2Lz}GwNn?UGn1Y9QRNa1uN;2X6D9I$5?0V{zsnWEGP zL9b}17TeV*MdaNw#I;wW?chqkYjKE$W>NbVJNIHj4)5bMb*3?ZqJB%EzY$Q>pC}A8 z0*d+@g~3L^xZ*R#+@VH5-%6n{+z1#~=@ia30>)Jx3g;LB<7y}`51eZRbjS8gah?${ zu3ks!+%ZPL;_Dp>Ley8Ge-hIyq3BO-0wt06+`+eM<#sK_&G6%vZMu6X==;kgX!0+C)`>7G&_hW3c-9|tU zK;?Z>e}% zoY>I|!XYDYMB+kju{{XpA}=w|y~=Yo6CN%O(HrJ@q}chId458te>Mh?=hIOLzZd~| zo|OyXS0fKOy5?{QqJ*Ea(EzJPvb8v%X~q~8%E!0*01&uw6YfLD37N^JZ>+KP0b z6Pa@2k}v|Nl!WLWooG_x+(jp9v70S(rdhu;oHK!dG21wuz7puy@igK(M=5)Ia_#GV3|A}^;QE?<5>$jmyG zgjgc_-L1q)?rHq)VGJ0*%Zy9z zb*Av31V8%A_)G{7nH1kN}TU$aRb`TeKC<+>p1mjcC2*xK@g7GP263C}i6HfSK#qDBb7g@)Hh(De<=FaA^ zH7y>ZxAduQ+`(=AR(LEAJ@t)&#CWU~x38puW*kVFGLS|Ck$8xvX&@)=ETVziSdDq{ zW4C#*Wlo9P>u6v)E242canHt2Y=EZm5KYrSo4B)`2Bx#Sw>!~;7IFJG8mMF^Y9$X| z!_mjhkB4ZQ20F&mD$ay~H@I%?6xZNFQ(w*D+Sv%G)>3qB_Y5OouN5UJ ztcwv)uLJPokFF++{7|amxN{rwi@b-~!Hp*zj{MOYfo}0I-KA4~;%P6_si{oV&lrGH zOL4mAo@s={98wl{_Ru2VwCeUU7FlWi<6-8-Y-4fzXKXfNSsT$dvl)&qbr!ODs1_2R zt;*9uVKCYsaS<|&M+ES z+XVXEG7v-@YJEZ6zM2MZN<-Wt8CY9@z_NIVrfJ}jxbrv-yn%7!K5jff{~EyQ{Yg`% zgvAHq_PezB7W?!=vRH*F)O{)*VqUbkD(-{^z~XtFPu3WV=sx>+XkKds^y$yo@-LWi z2QzT`*|?pLy(4Sbs4JAk6{jNbVm!pmnMGyX>BlT8(xJa*EG9<&`nWxb1{T7^O#|$G?i&y+UHVk94d58@%_MT@)Q z&KI<}tqt_u#z4ZQ9dSEpAPnTNN_Wb@hwOBp$3rwt1K-4*^N}b#fOUJ&7(gw(!i!Re zjDQLCSB}eXjezAt%P54yMnKy=*$TpUM!+fr75i1(zL`$!U~kwbCwicS?ho-0-J=t~ z#GQk5;xV>ewK0IU8_nAM-3V~vjWC2ii~uJ-;u_{pBfyC&4%feokZ|IsxSc)-PBdzY zxTA97fu0Eb6A#fnI+5JLxfF@QIOO3Bufy?U&0IFOV+2&qejcquMt~EeI1Eya04E}C zA*2~0;e@|~y@*ci;T)UPA#rfI9t#*Z+#y8w=tSKP&Ne!6dwb~hjRDle64rjU5#WTw zm3YJms3%l*?GE-Y%%U6j&QcZ|J0j4qLx`C(i@XlbMT3#WIqaNGjR9mag|*+z2*{#i zZ3xYcfZE@|v#=IMK*8&=u38!a1%HHtt(6fH1#jHJo`(!0b6X-VM_w&0K%h;B5dEcB zg&mx~=v9aoi;MwywW1V4u@T_a=ggwS2t3krn8u9&uTE(Op@R|N)hV>m(Fh5zPVHdl z4uMyE?}gi5UNy}{pi_qs{iRpkIyj?|DBM32dJkg&Ue)1ZyvzvjDmMzDrx6m(aYhIG z24=x)L2egi@hE5Z-W@{BoLLO$;QYcYYO&yhi~(fvJe?kF1Y~gv%?vRD3O=F*grP=2 z!JDw)!;J9%F!wI-byZdV_&N97bDK7ghTQa#_O`ukN-1rV=Gi9D*Ufz-x6P~fCQXar zB~8-@v}s9FCj3R@msGvB5BPxT)_&`K|=s1WY;`2BDzTdU? zKIh!qqRz~J=J!9J?6dY`?bq6Cuf6u#`{bhI%UQ;ViBKKy?Q|Coqg5{xxnH;HU&ye# zI?LH!w(8u@nd^Zxo4-6fYs?e?K>{v2yVE_J1*|2pUaJc@hjV|tvz$e736glIbKWNy*jEnBqn+iSWC`-Wp%^Xy(Cbh5hhEGum-Rjx zh^?_^%z97D%&xP|KTddWOZ28$$Y00L0xF{Ne-l2^BL66%D$0LwHtWuo=ncTAuH!ZT zSRJp`$Ln}&eR-7s;%wIUTWan`0jJjSBKnHxwpPUbOvRm6$Ghb#>vDLns=FQU)lvRy zvsrUmqd!HSHFdm&-Bib`)XjCg58V=#f3R>ytNiDN)~Nh{g)>{FJ#BTo@VqW6|6QTG zRcc*d$2-g&b-ak&S;sxm8Fjo8ydf(8bm3BkwXu#@b~n}WR_*3G-h|y!$J?uksQmYZ zkE`;#qViuC?on+^)$w|2PaSWNZjH)6VEC#kZCf2Lh4x0}zc4(bTG|(t|Gx0gs-*rp zUf~>!j@F~EFQ{DG>v#z>SI3)_`KbIGhCj7NuLEU=q8Aa*YLh;nTgR)CqjkLRxI22B zDT`FfSoEz7EpCg>MXo({ywG^Cju!_H)$tPGL>+JP9j@bbyd%*aoPm2(&I_WeD9Fd# zgpQMSyl*#M#~Wuy>v((Y!a82?x~PtKu#QFBiTi1l^Wx|hh8|EkFNtnr=cBNYoa?C_mwso(d(k43_Ygsudm~MsCPsUGVa@LGGgzn;{~Q0>v$dLUD1n}@@s{C zQyp*kyeE2`aq)I(>n(M>E%Jdn-tf4!j@LA9i@u5TFw-uj{Y@P&T6{424#wr$Yc9i_ z_)s11PJB38HwSTr_UHiGdPg0vL);a;op^`Zh0-63euANi_GoPde&Vr?*Bc&=KFGN1 zRqbDlKFZJy?a|{XXE6L_MIXZ_!ZKEafaDZFn+x3I3e+oP8O@5wrz-9KB$^Y$Os z@r?YrI-YC)DEd6}{HQ%Tg6a2sj3?6%JGGBv+RXY>yO8e@C&nY%$D9}sB_DTUJYjso zsr@!_QtP6}SiBSCVcfG$?Wg7;_V~JJ6JnotYF{MMmFt9Ve{^E;E%*m6PV7nmD;#?S zzz)ZFsu2pucu3%cW0bSuaEw-OHyooOIuef2t~(l{3RJ+74%hV>HE; zhhwyCRfKDQ#|qC`F9T5-j?oxZ6^@AoDIB96s5%^@CFYcH?KjxecPrGIaBN)`@+Vwd zj@du!&h^sb+Hi~pkh$R)?FjS2G49IehikvfoG+@Jb>SFy+zY}nZgLlfYZtMA*&Wh? zSUARQ=Av+no5jW97`J>&!nOaK1+;WToh1-l;TU&8TTnnhrhmA0JEX^~b2_92T_^yt zsc`Mtj6KjHT#^pgQZUUrPa$Q(wUZ2<-x0k4qu7Jmkmm~22JnV(?PW|nu5gcsYx$3L zW?k74ox%`Z6^?NeaecV<1|q#(HT#Bej5~vOgllhM><3h>?+n*oREOZL9nsbbOqXzs z+W)=b7*+QF6^>D@z7NGS%a>I_e;bZbSN>$U_Dxh-pH#7*3dgAL-XE?#x(cz+s@PA5 zV^m@v2*;>K{#`gmMef0HjH=XU!ZE5l4~1jYFFqTNaY6rFIL1Zy^Whj*xrf8GSFp5w zokF57glpfz;Qmgb;}^rVH!*miGx~dU|B-Nv3!CMtZ>n>kntXMAzZKy!sdM`58xXa0x)yo6 zt7hDbi8;f@ytT@=Ry~W9vbRD=T4i6rzKM$+0Ij#VOtIB zIgUb6kArDbewnifNHbcZUbf>^Q_MD_o!O>mA)Dpgii*mwb%uyqv)V&_Yt`*UZ9_p; z*>lh;LS~U%>3=syuKbyrr_pz7Syp=bKy_sSIu9FZ)&F8W(!aMbikNWyXCYDWUr*nNBFpOU zC;5Lg@3X+FsDBR1T=@$UsIpEEF9N#DQX+hLbT+4q|!z^JGvKY|0o(L~HtKg69#B0VEu-NH=`%Tp~h$(wJbZ)#cpkRs% zAd<`f;2c20vL9i1mY4r~b^Kfi)I8fh)2`Wy0RF8l_@cbluGxc7I2tF@)!Q}KAXFCp zB?;GP*SsI0is&eKr~C{Rs*WBbk<)g~r;%10U64g+P^Ha}UW|5>pJms47iqERaW;In zN{d^o`Tz0Tkg(| zulb6F=k)M-28YcT97Mj&M6%r~BT0vp51Ev2cq!k84=H5#2xCtVe-`iZ2j=26W;-{s zrOzRz;c@U$MfqO4x?vO~-Nf|$c8vY8qUVGVI$+1xrEv5gHY0SN9V22H3j76P%ge~n z=iAQ92t-Ne-~NQf|X#*Zd>BF?ftO#ZTp9o3b)!L2bcT*c1$9005ScD8xfd}4(yryTRW z;weu%murEgXgzJBY4p!`sasHOow^br=AjTe6G#)r|(5g63@>JIMV18Dd zALD zYcY!}9<9kEP+k8pIrXWUix8--FC*XlsOH@W%&+G(t$0!L#MG>N2DPktmal(deW!SlN>zqr zzYAnT@);(X?N-So`I`A)xixFx1I{jkbAyLNA5zk2!|CD65ODa9RV#ks3?fV9{fL!! z@>Q;PzJr8i4I5BbsO*U{rK0}eQsl`-nZLTe zz)E{(lm4~!pnz4`H=Ahl>j%-z%6X*e37?41`K7!d$xn0_}y#66{u`(xtQ|r%R zATNOx_1|N!ha_-X{j+HVh9$64xU+I3x`o8A--P*Cxl;nG8pkImt;$^zSY3Y}rc>ov z5?E6|97o_a5@@LJ1`#XImOx{Dk~BC+0&D9(%Fj(M#}DGoL3z( zA1lXY3T^-c{16k$xeN2Ya<7vXA_Lj2JW%}u68U&D63$;n7O?8?;*cF&#zD60CmA@j zjAMyW`V9nb<%Dw=^29HO_^7;a$wz^98z!JU59lyA4a$ASR}$g%7*`zs}8_^LY2y19FZ1+ zvhuWY-LjWNmJwqfqM*cDZ9~UZYN!WgAj_P2`z@=TfpvS4wEhL1?(RpFI}87llAey= zBN_t5g7A{3?UW<@;RJN=3YHU(xW7X=ol6j#L@ZWCtDPwwYY>BOSfg-lpS}=ng~z^) zncf?o`BrB7CSq?x>@9Gek0S60JP*U2(S_GV7g*Mr_F!ll{tcZd?J?wi4*5FHK;UPH zeGX2Fo&|!0USQE*3s-&vC>vR{DzhGGOW~|DuEXnD#G69T*j*HHroG(;k*&7K8!*i9 zgsd4TaYAoX0qI6eGeP+>0n-0D7d&{G$4+aD0S374U=}V>z=U zTQ{H_A7>WKRUaYhjPJEZ>#uAM0zdl0iGgjol-e#aXu3uyR3 zA7&Z}S9Xpe<{~6b!L>8C<1k|0kI>CI# zie_g%86_HV=YoFi4ERIF^ax)?L-voT>~T0eGGr-u>?U1`4B3y7`a{8Jex9qyA6=w^ zZP8Ktmbr(_IN55PW?@Q4;M6#U)Htm{#7a1SocPtG{U_IbnC)bsWSs6ql#CNSGETk7 zzZH&88<~r2Y(K2ac^>6RYsY|6Aez*L#R9*8K^!|WXVpQ}#eh!}rn`J0)@S3Zk^d@H zm2kugmhuuy2}QQ{qZHwY_W|Q(Vy&OVNUtJJ83)&ixSdxZhClms4_rHAJKldBt{2&$)`{!zS zuae>Y~FgZSP#@2DjvzVtwY?+x&dTi)qtDbtTaFhyV*TLeO}f1K2@jHeHrD_8E&Qh z3oq9hZr_{H?4Hbhr~q0CWZK0M^zw*zjrj^3-f_^4-miQA>N}A?_`PhI&wbNlevI>{Ia9_ znBBYp!Oe~gE1ULRIQteV8e3(2H#-CDYBNZ9D%`d@%oMxZnfE;KLN`pe&g()rt6Fh2 z5Uzr2t-_|#-l`%$jEGwqDec{+BA-LVGjN-(hhVyq_40*Wmi=bO?fd{@o53y(a5!h$ zQHl5;h48klhrpQjEmWRV`+gMK#`e7in0dIZ!UjJIO_B{hgos<=+Lpfo|7e`Ko8atK zj_XWex@HmkWh6fW*SQga@4@pO2AUDzCLsjZcPRo7BcI4S=QHm6CxLM-B3C2zG-AA{ zF~au(&AG`vNQ^%qlK=Rv7p|QN9W&6YDTFS7>*rF$Qsq|`oe@{W)LW5qEgYVKn~?tn zctU)E%`E3;xAQ}YycY=fz;%2AfydzaG8{^L2tjr-^jji7=yv`P5ziv+`*5BAgurj$ z`4t0SMPTtv?CatB8_|*nki}kUBi}K%vl|huNNI-aJQIN)crtK!gp@DQ*8^;Owc~D@ z1{O(q4lrH=H%L+n38xV{0@uf;F;nOmGNEZVll*KR?_#}+dDuK@*4+r*1t-m7PweZN zM>p#WNclXRH0vpNo`eH3$H)R+=uRSk#+C8;SET(EPR56+;U}1SlUukB;5#7^Kk7<5Ykjx z!1FSkP>0d0_UmKZB@zl367A5nsKKZ>?*x$Gh%Xpe-F6tw$L=qTJ)iW=bVd3F>V zHbn4$Wo?_+fyl{FoEE^)4f|Wk5B7y2F0cm^qt z1Lg1GtQ~hF^fdAKGI;L-Ugv{I`5|zAK)g-Fqj0tPGI)aX8>Ii5ILah|^%f$5>-TSM z_YW+HCV{Him>_UsZD@n15$+5Sv&h=e#+~T7h_tR?0kcEy*%u=ZccTU1p99y<6wxuK z5t@V(9TRIISOPCL&Fn@|FZjYlQpeoE3a&tmyygSi)gkvYrji>_+*{$K{7=L4x2F8- ziON^7{2Lj`mqem`DgFb9u=tYVPYJmTFt*Z%pP{s$nBuFeG4^oM{Cj|I^A#-qK1T9o zir>W6KZFQ*N%1uySBmBjqHKnfmLGs;+!XydOW`Y6^b?Ha%M@*mG{bUcKjrhK6o1P< zczpSky^(x*3(9>D+|E&Q-BWgfCSrTLV$-J;n|=Z5pM|qVzKw;^{)k^F*~GqO)9Vbg zf5h%#p+5ogb1amn0rs7C4{g)-_MJQzu|I0}&`NFRc5-iL-(~mEUTx=9m3ONuBiJ2= z;jEG4DI~tpuaaWfzU5x8$~W2>R=Ehsb#Oa*>S14PXI>=U_MJTUu-{~7Xg9ZWs*Y<_ z9UFmuCfqLBYrMr)6WSWNi#ZSaHExv}TQ4=8Jg8+nG@)NLVGYn$!foYI ztUX|NQjBd!L?0tXoDJHYq{J~qOfr&oXV~XDc?|I}M0^-d5nzWVz6|(!RyH-1M`-?%?2Fj#Bt9uD0@&*>1Eu*v}6kf`{aklKKiL#}qwc3I{cNg*l?6`v$=_c(hXMAJzuI#g z4s53T`7wk(0;l`QK9uzH?A0q!!wd#$WMKa^Et9pakc3c|O)7PdVP;oWeY3xvV6Q0_96^Y9(nR9$&)B!21F4WR-XZI8PH#RuY*ae3|kD=Ov`SNE~bU zIlSU<@AH~fWzT#X5i{nZ1~_RJvBL6##|B0}(4|=`fwBTlHR~tvIDAR7fOjGAq{@xJ zIg@zOtbd2c=1ZCdJi*B$eLHciw#yFVY9Wy<&eC$b{1;bn%n^GY5ca}#z8!(<;Nh<< zw-c@7qloz=LU+OKpwVgvOW6ovjncA z9f5W5v@y_y06z-NGBAL^Zg^e`*L5}m(2Y6{0KN$kSHk5Xk}#dNhaeZMO>D{4Yye-< zk`KGHr4@Gq_YOE|#pmF8hyk|ZTk!CTnY7{scz(hFTk(J3`2z!NMJ?uZHC$0EIuXIi zp1(WL3P>~3)0bv!-ciJy+XUI~JUXBE5gaP!qcrL`k8XUDdeiQEIuZTAT!$;7N_pT6 zri`^=#c>|!c^XJ#Tt1u!cCiR+_v$tTZlCLL6Q^?A-oYGuQs8UnPG#WO{i)dqymPK| zlZW-r^{U1dP;Z?p=Q`B+RsJhC`T5_Z^M^ZtwSTTdm0V%%Z}Z!=zsqme{=90}d>c82 z<~rP}s~kh?dF-Xy^%`C7awsoOX0F4XgTl(Jlf$vy|H|gCo9hgDDeKOZ8m0H^x}}!n zr67wt!(PZd&NNUnD_0|Craha#>uhzu2x%MoUo+=AG?k?IbJz$;JFM;`dLG(=H0ppV zZO6=JslB@urG&p3Ug%KYO#KZo5o%#Ct>nUPggzNw!jSU<>-^ku#M~cNzZ#wV!!m@H z=yV<_sPv^eef)hat%K&j$bo56Y(qoKgsHpsbDr*US3&VQQm>_W+R%dlH7iD^}M3Yrvx*@ zXn>;eYsaSOXs`?xT3Zx>#?A@m??A*{+s;PWta(e(>9xo+Upz>vt3(V-Sr9A*H$Bm$ zK&3H31OB3-vXO5wQy`FLgY*#8Z2_`xuG@fVx6~gAtS?cJTL^`LVTIl^pbzWKO~ zW6~S=KUX%CBWidaJF$`2Wb;j4v23}j9Gi$mNR|fa*mBxnwy69#DM0zwDfT;AXqU7B zo@67&SMe%|8<#$$+yK|ZSRNz@rh1STkUzl^RQ{fF2*zwMJ{v6}@z!7kniSiD#d3^# zg9Q|2@AJAZlt(v7o&FPIVXpDwf+QIv9ibSUB#{N>POSJQ#Tt1vMED+|n14+7G}>@E z#<3>CvUZf#q1j~Ql|IIOhQfe*J`o{;|jXAVBEQyD7suV(4#1jQ$-N5PzP}o##pdQtc=0hu+wey811yW zIC_HzYk{)!TX_k~s|Ihm!C?(~kv62e(h7ad5Tb~C9h_|q-2qUV4N(w+a0xiqy3`t2 zaO)m;-{J>NHl2zDdBD_iA>*}xA*=b;-vZ7;B>jSbR}cpcFevZ_F^B~f&bkVYxd~an zZEgP~z{7BiX5nmpu!4|OS<)$dGL0n71&4`^Z|_wWZde?v?BQGK zX_3Ix>u;q8IwPA#09zlB5YHyFost94d(MOJ2pk500G1Q5#*`JQhfb*;R%ozhSQl75 z%X?PbYH%wQ?v1v@nk<&R30}J3s34ev%cy9A99-!DD77BC9P{1>aKG~6?LDjDyBZG6 zMGUz(;q#egQ#+(9shzA+t)dBNktnI%jw6mPkTWFv3|3hbsV*qIdMo_VV%CFjLVJ2R z0c2F@Atg~T!G$K?bgE>uE=T(H3LS5GLK1Nc{DH=ClCg+qBzovMfKn16>R~vAvEyYA zV+VYJ=Zo+wwwbKCl~@ZObmL?fCCQ^beVWS@3|4a55fV5;7&Lfvne3C5aT_UgZ>~0!JFaO zzn0|}S<4u>39igK^6=#n!w`?sOG%@O;-ML3WdLb=fJnCki%f&6ysF`0^j#8tHo*gM zW!43iH`<^>Ah$w%LJ)HVEGleW99W@3hI8nTc51HD)}q%V8<-#CVh`&k^MMk4dE4rEZFMQwAZ+ zp#+0OB2Y*WWFAsTP*NcNo0K*4s-ZcLTW(48f-?=1tJ}Zpvn>4)7c_Q zUoJ*Pd!bfBXVu8R1!O0RGa^#3<^yUHFarkD;0J2AtaFj3#w!P(JRvV~hBc|SH71Gh z3b?D`Fir&5!zl%>3O;!_5w3t^vR8z`RSI0yNffvb0R4726ijdroGQ2)K6zNM!SV_= zxT@gllN9_AvV9Q_1rt0DcM_G;V0i@_+&`~!mPx_9wkK?JqISea|3xI=$Q;4ggyAJA zZR>2ts^_GUev-~M3o%983uZeZQf1@277kenI>b9fkWsM&TU9LHMNb5w|7c#rz0|_V zv8<^_`vK%34xf_pnFah?(l%xeZkw19PXiqKM9>I#;&>oZBW({N1+`V8@KJrt5fBv; zYkn|G&J)-~Ru7eV3;_Yf6|(TZtaweyds$Rp$=ZK)EzH6UYy$*uuql4)i;-T14o*=? zuYv>|d7AMCMF}W#%B}Ic-{sKigprk0FY06)q=%25}5Q|u# zXs{`M>x+?Ig${=12smcJcZ} zk<(v-iYnNMp9pf(t%PBr+8})Du^CAhXqqDt+;kOJ@$ZZ&&QBU}0lXK^wuVjj;YEZz z#TY|A#*o2q&`e^fk}d@#JqVA(pG3W?s4gH7t9#7s-OW=WO`Sg9~BrPdEVwYeP5!C=WZu$Z5Ecb;Ciz3*oSy z;w_IY7Z2D$_E|>);c9sAf-7n-aDf)Hj1U}WoOxzxPnCxAHQcY^cQvH!;nS#qm__L2{N=M%0nyIry-LT^+Q{b- z1;muEy#gxmu7)$^n=}(|>SH|dC`~hPTncZ2yA6(AHSS^fgYE@{>3$Ap9#alS>2A0O z;2wf|IN<)H`G{{GQ|`lvcpQ#2d>+m`Cu_gS6KspYXW#CCW7^5mUqZZb7;lcb=T^c` zw}x^0A?|PC{>X43o^h`h@8J?3?quZ#^D^Cg;HTCegIgYmZ-U>rE$|23euU``!kLG- zvON;m(HJ6No^pL2Dc8b11<$;_y=Bjg7{5{Da}K>=>|BC568hgXTfte z+_`Xa~~Xefo%`A?-;@y zpUdH{hPwuiv@uUG?hX?PXv%vI{$P0zBFuVTE{R7_9`aKJj$_NQFMUk9i4Wpdn@B+V z&w$$r_XwPMUJK7|xIJ)t;m(6Q4rdl#YN7S_VQ3fjA8?7x#)D$u?8e5mlcQ_*P90f0H959+vT)$QSmDs<)b#kI zwRZpEL*r{l4~`#OyKn#6#N?i%2PO_D4^NIaOpZ^CPmNBk9X~cbNzgJieRR)(!-JED z&l?|`o?4qfGCFyF=IBIWX#atUeS-&&P8D*Ab$#uuYIO3@+GJlon=iC0xRyn(%}$IR zJi2H6zo}C8@4&>^+R-Bi)}qJwV{dmO_R!c-bn#%Y-o}H6$3_pXo!UQ&c6nWGDX31a zoj!c{;Mo4r0~1qg_l=De*q`R6LTjO=sinEl+{DNRL^ezuo)~W!AKiVRp}DECwSmcv zNG?iZquA}WhepRhs-o`yzi7tP#Zy5_{C_y?dIbJ^OFzl@jvbmhFts){e&K$JY|Iaboe{*-igVUoEW8+i!mLf278^<`c$1tr5V~1K>8~1Zl0cJ1YhBE>%3kX#T z;8Z_t?C_yOhbL5WVbA#9(W3{a3)2@L8J|KNBnQ}k&w+_)1aMyyqghZH3Yb!egQR8! zVD7^Bv9a+Z(+3VuFeB>9t-(tj0QLHD7kQWz> zCkuO~*<^Sv7ylWV>xJdK$+2BG>e`W0oZ7hSMx4WOr`&d<5kyDo-FX6+Aw7x>wr%?v z@A5O&OU6s$?vltHcm8T*Y?^bD98Y;UfU(j&4Mp3{?rDnbGp zWv2pZDZI`lcHFIYW;VKIi`{AwZtzE|s<~b;|(PSfMa- zE+ruTilWrjC8^scCeVITLY?+gij$m(jO08jTV`N1hBi<&ExZBelqUDDG}^PKmpxwYb}2 zZfvK!U<2~4)HHS~w}wORT<3A%JGE{^3T=wI4e)G_yQ@)s+--n|ty+uLmPefXrdea$ zT_DKKJ{6MgLPS+KRdIKrGZ_Z~W;e3`5jFxnLqrrFhUjYyxkXHMFTQ$l=gkFAIM>5l zyV@;lcF%BLx=b-q4ZdX}f-~E$B@*a`;g11!EOlc`-Hrx#aomkHHXwd&)ODRxY!|mc z(bUaowcS`$*Ed+#T&e3Nlxpg_{&G{-xBgOHvG`wA(T`kIR15y9b{DL3E@^BIJ8pyX zt4kV5OXtmQqr1Ra7k9R*dJRbxY;!v?gbSR8Mt6&o2f>|{t6f*=D=-PCHm2 z=A1?E3e0jg%9*(pc%LKQTrje;%tq5++bBtI0O994JCQWU;LvkeA~@O^C%P9CjfEcC zDow4iqwZ=YYn+YDeI5%|acpD6`H)NU%yr&+LK`Ldf4Vuh>*ied|BvQ;SU2Y_uhN_i zW+3KLYW!8BM6nfZbTb%J3{#^wOq46Dh1p9-Dy~NAF3cD5oxL_Rt7yjlfDksICVE?JJ)J&3^n6<-SPm@IsA;&bLeSS}GxUMkRbb`uM-f}&id zY^=4zVMN|H!-g2FU5nWyjPccDj9=(HA@Pw7D)ydZ_@@`~U;<}zYs5hU7_Zf>ao#o) zzFN!%R4fbCGDI$7YScl}X_%9zuaXALtaU4aG&8bMFE8uZe-ar&tQ_;deKGt^BIwF7 zmC$HGcha`o0#T015v*fgpbpk_x^t1_;o?$UPxD_{4<>Pi9`zUTbuG1y3TGBX_)>S? zqS%_|=EV?eY*ww-NMw0Z%E?+vz9=eou7z5_C7?Qvm3o=G2HsP+IAU@>hf-(i0k|VL z09ZKwNe{py{s18M!DIGuJpej^1F%jKP!w15**4afa1jUnoHAe3DYwk|W{8W>J(mfW z%#6F0&X<`yM;4Y+Jf!ed%53>M>tK2d(m9f3wPP7U?<%9F1=i;z-Vos7 zOYF$j$WA?F0%>PN9Hc1)1w5X0?!?%xZ^Zvq0vmbzke_4I;ns#-l=~jcRkt>ZI+i%^ z0vS;^Xbe98dxsS}&i$7*MkqdA68;6~)T=}@i8-IWJdVf;=S$!iHM9?cXTYjh)8l*9 zK;2o+j0>HcPOK$ZCbC0m`0VS6yvq5K6?ZF8CJKuCKuhHEUccF8EZ7Ly* zn-EtSk6cWVz06&|#Eq?R*K>1o+7hHgaB~AS6MESS2>SY%3uOvQX)}V5?6z|=8apfE zyomLd8V&TYnUPIWk?mX`-oUh9BaKa~q)cf-(|_Yn>{%$7vK(lTKlH6}M0r|VE8C&g zxC>#$jaM`hZCDE5W<433+}XfBH7@J%moKvsu$`;W8c67`y)Mqdf_Iz1nUQ|edF)Uk z&K;1C%)Npw+QzOh_M)A-NCv8Q%H|Z*s*Ie9aabL3K5-F8rqcOFnI84KxE}rICLtR6 z8>|BudkkjOxiIdoO8R?TnzA}Nj8>v#NDc>Mv*>sOyx%U{XsuV`NXQYo)LD7^k_&Fi%w0(gBEwgPiV z4>H@J+Nm{S+u9|$wJ=xlTsE_YjE?!tO^*&;;O138LJt#f2raGDTLXn(dH ziN_;x@a8!i+{(Ea^H{|B;4wAk-=Cq!{MKU_bD8PfZAP4*)o_-^oSP2Cw<_lQ!3!6Z|h`L5MiCo-6>d6k(gc^$8RbqLkPR99ZJHNNc(#{(%<)n0Kp};u@G0B`y zhBml6wz^44J#&Lh`)U;2=yqUlwH2z)CbtbGoD$y&La&ZQmo^}7EvC%;<)N8HLiV}} zbR{a{?{^%~lL^_MX~w(h(s+@O1uzLndB?NBp<(&Rn0Mbcqr5mDwUWU zXmq)=f{W~;Ioej>kM)iXNCw^Ci}p}nzkFhYgFMW6DdYVY*8to32QUCe=W~~CC>A9R z5$BuG1u07InZX_BYJ?S=-DBA7Yh*KDv|w@nk0=Tl-zU*6kF|{$X)X~XDPN3Gj)3iz zj=0s?(a5#4cvx@ohxMl?Qc1~^-|Jz$x^!5nQ#rpA;w^I?L3dAB@7}40_m0xx{k9D6 z4>`PZ+${Pv2+eY-yX91OP#NLY&T+S3VL2E3D47qC3ltA!&YhRW-8s(F4r8G@Iv-SJ zD1(cqOIE@}Rjfz`RA8+|o=ls>=sI6Q*$bS{UfL)Xe+jb|CZB_{>|u#jyOhmQnR>F6 zG>dmxvzw$iQsV+1sff=3^}&Y!2%U;-`22|k{?D@EKZ6bDIyXZd?`m-C*MbzAq(KdC z#nKHRQjhKKappFBbZEc7MvL+M;0vHS3( zUrn}uN1`{ID)bGc(pIXgJKb;P)4lmzlUMZC!E`tK5aM%6=B zS8`;~N)6^mk~!4Y1uA4GFGwC7ADtW=pTIG|J}-ANw`*`{ppZ|d3+PxjvrC9$?dTdB zLF+s;7M|`;bdhY*`IaUPo2>&Adk=SyPfMO;Ps_kio&zwHOZ4Y6=pZPN8E7Pq-bAjD9O%zvyG?eXRBN*}bXF$Wi@v6k+rZ`ckF=>gaQ)_t zWHZ@9Vo+ECCG@Kf;!tqUfw8ekA#2}ouLXjP3=gLJo11)Zv+r&3y{*2t&G)wJfokr= zm?wsYq%doI@&FI0h=#U}41rc&zdWjg*2!&!L~iqZPw&5)en>p0{8Cd4ax`nhb(ivP8Mul2OiAj)43h#R5Qn;C2e&N4v}S0 z?9_DNP!H#7)0lhXdxVn$0)X-!E4^X%QD5JQK?4;`Mo*h&p0`_IaOE(gaa z_D%1%#)G9!A2>9A_~>-u&|w_DXL`xnia#JZ(4JL7}FIuT) zf0iprp74c%pXASffBNGeC29GwPB=`Bv5D(IGeKCkFp+8=?xTdoLX^!&&-)YGvgshP zOy>$?(~}1=m(-*K?;6q@_Q1k6+&kn&_at(ukwh+C(A=)3 z6hwo$Od-*mOD9shyoHl=NO$L&zyc6KSl_bA6qd%_vaYpaU6VFLDl6EmVT*>X8n$WJ zuHiZj*K63JVW&qezrDJth5W#9E}6EDOddEqd0_ftAG0^nH;5t2?Mz`BV;n@96?2@- zhT;V(S0HJUM<;RJW*Vvn)q$?zd>$HEZwk`ZmjPxxp%su(yRe{QU1}i~2qI&Fh0f3% zGpk5hN@~%_IbsHb%PiN^{BRy?TFMs!9&h=$W@Liu%xIAUrdM>+%z?plPEmkqJXvg`)?jWxdzl#Nc3VU}v^ZX@rCMzNAbDhzfK{E+#2q zo*POgdi&JcN=YvB49t?>K`JP%rY9LxlXTlfx#%10P4|H*F_wl9^ZG~h{8Y{4t zVI!#_jIofoNsC8c@cIiA){nGOewsOCUE3($x!O@1;jNK-7IQ%q8A2xK*D=hWCiiVRQuWGO9E{e76M78Epp!6W-5y7JI6 zl$P#s2euMW(m@+&L+Im4RxdUi%NH6z>EA!pYbAz<22xNQ{N@T*=CDCYX*r0hK|r=f z#M`V8JB%nF$#&D9T;FFT<(_Z$X&SB)53*4R!WHSDah1(;ufl4>G zd-U+dJjAJ5nsyBI4uL*F9S`yh^cqU^r?7^KE*#LbDNIk?$@HbM*cHI-{YG%8CA|eb z(&I`6v0JaWrVAyqlw%|s16W?f8ghG^)AYpX?t|l^WJ2(PcxsO)3brZFOuL>D?vGN~ zK4Gp07&NG1V@yppVG|kmLMkzoDD)5abx{qaU28X;N4B>dYCu9^X~?(nQ7bu^#^}o)qT5@pq4XTV6;dwjlo=RB>Lf}#5hDqsWEBJf zWZjp}B@+223$JFrT0CviSJIA5Vp*A-J}^#wp=We*Pev}Tg1h~N4y5#!xjvZgx(0Sy z(Dl&B!w2_pIXb^^5Nv;tTw=7O17iozS1OBdI#XgSGmwK+HiArm+_2y9T4fWPgZ$8%h zs*upGSof}z*K*3%1h&dtT-qs3hWdRQUKWg($xy)1R5h3YCwX1P1eM{Td4%1Q zeJ{r`?RO8`8)a0dO@>_FB$~e34YX0ygJdGXv2pApGz{6+?t9n!-cFQZW;--PF?5** z8BU|FqYdcjUN$*0%;{pVC|5X^MixLO!(a}CJQ^bRh32^2;)ZVlkTd@SxZNtLK@>^kzuAAX)L{ zlfTa~10ikVE~=zWJc8h%1M1=OkQDolF%C+!DWMPJ%FT)*Vg_c@61pnOC`_)hFrX+< zH<|SM6BKEB2MY5SHnrYD73hSRHDHLmz;H+&gF0BMaQ7cpHehJ(eS^@s`*&dfuXJ(9 z0Izx8U}A3if-GrHD>5U6VVojCyY~5EoziGzS{4ead>4&PeORl#Ld|ZP0wXg3J0?XQ zIt@aqV?3_sBS~275hD!~11?q^2o6KjF3hWKdTUfH?|v{-8}Q)|BBu8rJ+vEe zFWNrcfRE8OLebpA2w?6#a$$SJ)RBfg&Fc^|Iyts~BR=4{u%qEnBMk+s_e>pGz4u7G zVPCvqpe5db4}dm~p#cqh55ej(x^KKe9Vl#ULX^^D8>q)3wD;%)j=~O4G)&=pKz<5@ zINDddu;?X4BA4f)xnaGtYsTd6rD+L+1wkU?Dg(>qyhWCCwQvK4i_JR7C^MqTz7z~4 znCDOgs3Kc=09n+lhalq3pzs01r{KaiDVIdBi{o>RHZ_Np~V)$yn*T6@9qLF|4-aGGH07X1)hQ z7C6onQ&$G}EW}L76J@R_ymcX`lduALO(e6*;>HoeDXstrl$^*Ck54F=3b>V_PX#o2 zaj2%o4X0|T0rMaWxuv7bs5F~VY3=|obJxNxvsbb&lZy5wljG3b_8!=GbP^_VGk=pk z*z>D%+H@k>gLQk~_;leIE*V()T?0v&UC}{rK$Minh;dQi-4CN!X8t=q z!IkSFdVFBmPy^K>S0M1sJ5PyqR4YVD5^Tex)e<(8eSkR%7E`zx%A$=DEsp*md!`%e zJiA~*qxLX71nmGeC48{!9iPixkAS`xP#N>%V_=5B95MAui}Kvm&|27wyC@d+)Xi#7 zEvi&cGY_`C!9kDBIAPQ0dHq3$@zaa-2OVeCUaUXpFn4;foz|=WTY{qhQGhRsS#=U-N+1zMDCbAAL&+Xf8V~E_+D!{|4YT}Vs%dkN?B@&-V7&Ca&Du8Z$M`hH zkG^<#K8;&_8n?opY`Db3#I_ykr--vm4jV5uue>Smo$FxL<9!5fkicQs;gN3bif-+J zO4xCEyNM$ME%$Ep2LyyKol7Z(aFo_Gn*aDV6@2Z@OtlnvT`4d2Bv*xnsw!}-91D2cM5rL^QgDsvfWAMx;&b-`-9N#ON@43Vzm2X(B4L# zgoQC+ziIb*x!so+?NCWdn?4k1y2s1lUC`RJU(%Nkd5 ztkQj0n89Blcac3nFR^m<&l*f_OYqgjSCTI|kL8&WPTysFFp`GK$)Mq@bv|L%`Gi^L z69zxkB<3e_Hx*Fu@-PH6h=tR1Ickv}bf_M5_>5wDDGQ0dTPEU4%^t|Tt|88hRx>k{ zk)GC^fQ8jR_OOl}nVQt+F$Laqh4zdy)ciK6$Fw1%edJpzww|FFc4MyM(A%}gZ=Sz- zr(|i?>Uwii=@9VxB)7tlC}t>eaTQ_*w-kGYwawjCmeZ-o&{;I?CP$~K#Y;VyS5yr( z6;n`oz;bB1DchJ@xUo^E?s_Ap4$Z}ygdI;elww#ix24quRZ9eAii-sMD$wt$?6{N) zE87}&UC&3%TL>APhe3r^?aTQ37rM@7^F$lFM^AX7wW3@AjzC&uz?5QbICywsU!2ls z#|RVvPv-+wP+JOjK;?#nT)6R#cRXh^eGhiAH`~8Wv=>dO1mt#4zR5ecDZON;7CqUo z>Dval#ib9i#Y&e(bESt`M{aKM36#qxV2P0#ik-AJ*#-6;pt`>4NDH3W>OeIRMs4$l zKyxjypo;n16+fG~>_ufJBePL%8>ai4wBm$2t)8#N^R;@uHqY1Y`PO;9^_~y6*mTMM zB`Px!)zOeTMe@%dKo;uXN_&Khq4Mvtnx86?kkmP>bM^B83sAB>)1kWh?wS=lo! zTqNg*+Ef?3(~UZe`mcsa>(I?mqIsAA9YHKH&}X>^hp7W^C=WcFreXy0n~H&6z>yL} ztiDeo3Wd5;kN>4USs^j8b}2)EHyXM$9@T`ArY8e;Ur?EKHyH z%EABxA*NoD2H>OXd-?fpy^9so29zrQ+|=OeB?{&q+*2M-bDQkz4xVPldy>J6ao#5b zsv;5hS~XG{?_lo$ZTqGc!;Z;b?8{-2=9z&yu{SeRt9i}P^GqgXF44L%&so3)ekELu zva)m=eBS_&%p}!GvuFvpCLI_Gx%rKuFz5PmoX7KHIfdgrpYh2H$M-Z@o;P4(@b|sc zb8zA+lYlmsNw3+OqCMVmJ{ys0X%}ItWSMEPAqyomuF54alXoP<`T<4OD^NsvdLSzc zk9Ql&lmT-EuHN-_K}Z#FLt-Fsb|)EoVNodb;X*M7srWjHDWd3}JIE>;5eCNBYG7E# zs-X6N#Wn`t)`pqMW8NG!_u|hOG)1u0#2ts;0!gPwwdg{K84-QMO&LsOn<7-B{%ACq zW^4E4eytanxHcM8_0h7jdg^72S6Bnun`dVk>>XAI*t|AxXo2$#-YLrB(szJqxGmB9 z{hk3_hbopB>YA1*LHCwNsqCdSgd;Mqcu$f_34sgRkPQ0985J6~NO%`lF}+(ysRL7T z?I@!ZI=>OJz_+P$Qp^)fPAx(?xiVsV=3!zBZky4x(I-a%Javbb*H>iuHFjHXya{K|MmFfuVRafV+{1oxAnTf-Lm?m;j zTYt4Nf;-UUA6$MWq$wCOlK+y7zds&eEC0e#bCZ0Ipl{5O2AIrPqNPH)ZzQr0BVjra zV40rWHgB(x#Wm2Kyud!8wNYtEpWGWTSxv*c6McQS&Fg<|lEcXZ6{y}ptw8Z~mG?q~ z__XGsV3}C!i#Xl?d zRQ}?rp#%5=NEp?V9NLh}`>BRJ+=Iyd6}`Ox9RnY+O&vZuIW`_NUFf|Cb_2L$VxBiey{m{?x z!4j{5rHf9cY10VaTK3KRratViz0YLGCuW0PWc|$X%Q%xGxO2>8v9igHdFsY8Q~gU7 zUJfm0i;gV7;=HmLJl!ySlfiZZ>Qo^E6{<&;O7@!j$)>;wuqaviQtd3?*X0k0PfJPz zBX+!I1v}!Y1$r%$dlvykq~sQBVEVw8i5oU*S8(FiKyD6F5uy$!(g(Nld{vv5TfpV{ zUHHnkPk&oM)j;)H-agM7bA>YV7k?n9N$kyZGg#14^TS=(LS$)~QWq#_VZrt;uqX02 z&xstQm)>Xg4q&%X#0R*&gsYvj8e#9piy~%yKnJslF5JrMf<-gjBfWuLWeXJE;w)gEms(mB5|I!XS`(K@MK> z^qLan2hdG6SKhqCQes4`m%&&X3pE@9`B$cfXu! zoNOxyxlfZIgqzk1QaE^%Ee`fs%Jwh(rK0ft9aT?_uuhFZLXCmKfE|Ooaf}=ksws6N zd`dRnT)ncmileL>%7C20fguk%v4>E$7`(aXMm3^Lh}}SRX|7)oM370M@IZHfQI&$3 zSBjyAGT6#jn_MK5g^-&}%nGfdph<=_GK0y~-PrQUfT;U7oKg6s2+|F8YCX&3G2|Q> z$ZgZJS@wDA8#81?-8ceGrC@82-8G_UAcd+-`xnfu1n4Y2&&=;otE*Z#DTY848q14T z=fKys7$rqE`Ec6v`UWQ){(7;#$q7T~#rj4k90pT)M2qlN_85+r=_vN(SbEiMG0fE= z8SI4me*-C;SaO^b?Fy(b7ZdBn2y7;!9v~EHwt(_&ix`e++RgKzUv63kcEzmKla}V9 zwcn)PY?t2X$$w7}iRc+C4cZCw(f>XN429F3z?BMVf0zCuwF~59x4Ja%cairc>{AV= zlqyPnTG53&S%$VS26$fIdWX+9kKiJ>x)TiL9cJ=mV5)Q}igxK@)uiiEbnQ}f?NVQJ zbm1UH1&U&VCk zuVT7Dbr}#G2`i|nrN4dY0{u;Ul=|)&6wOXa{|^nt(m0`EF-bKZkR=jQe2`RCB~?vH zRT2JIgrEefQGF@?Fvo0^Or@{~4Q#_d|L_`Tw!47^wHH=dtdV%hb{?aKvklW3t)VE1 z@7a%v7u1rkV6eNDe*j>?5~}uoUHbc$E_~mDj{<$M%B$X(xnfcc2nDoW{*{M!K|KyfNtN6jDUYww`9<{(;4U|& z3Roo3k9+VWU%Jh!(=1aoB6^X5ZHcn*A}=Pf8bj*JMRsRp_V&$%yn+tmp4cl2mmVDD z@(hWj*2fl@sGhe?-w!h9d|n|zai7U%25<=y4GtJ!)Pb_GVC~VyGBcb;nsg10W~ZH3GQwr=^jeF#4ZkEzKa zR1D2;Pz;S2%Ozec;ru*G={Cv+0*ywTec_=weYbSiLn$S?^+5zUKdB`o|il;j!lmAtK-m^>6u zAKE>>2e+oN9ny<=8YS>n-0 zs;oqLsN46abS!X#_3>9*f?@u8%W^pL@K;>As+M0h^NnR!&v;Yh8u!}po1M3yB|r$` z@mF3@xoPKM)%?&-Y3Rt|E15w*{I!@wRfWox zKmDNtHW<{t|_hO5#S`M!dKbn%@Q&N+rVF+3AO=8 zD3&$KUqi9%weaHK(DyY$MeMgCr_AV^>C7st3D??l?0L?7yUt!lcB?!7pDF zr$?+P(rY~&{4z%1aqtru#rQL8$TbFH@Q4 zqsPH-WfbS>Jljj24k4ZO-^~blDvd{=W6dtfKU?t2 zJp9=u_@|WMpHh+@ElH0`d10?Sw#I)PYfcIN9Kk>4;m`4r;d88cCHV6MzsbX&SAt(x zf?p^24|rI0o{t{KT3CX=Q1H#KH(5vzK903W(*3waz85~nT2c~TS`uDX5)Mim=3h~g z9+VbLUsaO6rX;+&B;07d1~DWTWpoYZ*D)QYjIP0axHY7fBlU4 zDMM?(pI-ws4|(}{IHprp)_}iW(P7HO8tW8mCgPb+IamYg#dMgmuLk_ER)rS)aI)x&us{NjbOPUs z{n;HrQDX2v*%T%ChPa|=vC|gCsPD*MMT;%MlpC%^G3uWV7DcK1_kpgNPw@j$a+MSZ z{lO^y7p3ATa~}Niy;!om4x?Vj6z$~uk+5rR3lFjF3|8&o!+J)=VfS%Wo-f^ z9)B%v78vsy4apOsEePNVCDdvV0y3p)XtP@5LtW~Z^Fn7TIUm}f>J4pF>t`sbe&sF% zhNeysT2H=FkkW=>N`+9nWi2IKhhOW|@%;U4rlV+qs7heBhQk`3rQv=J4{7*14UcPh zt%mQ`@D>g4(~xtE^?gUfmo(fH9V-{q=uB+Ea!3!Ij0$Zvxe7e$Y1ef{4E-OP{TVlyhp=NYWSdr z4{P{k4IkI=n;Jf?;rBIsUc;Yh_>zXNX!u7BLm}0kG7YOVtkrOVhD$YEso`1;*J-#> z!<2^GG|XwZOT%+D+^6A$hDSBLRKqJZe6xl(X!srtZ`JS)4L`2oCpG+xhF{e1s~SF` z;kPyXzJ@>6@aG!-O2gl4XhS{YxRq%*Tf?~;F4AzhhO0Gf(Xdm)EgE)f*stNRhG%Oy zrr~)SUZCMI4PUR})f&E4!y7expN1dQ@S_^utKp|L{G5i5YWTQ@-_r0I4S%TN3mX1H z!&fx?KN^O^icaMk)@WF#VO+!0G;GwcUBe9;CN>H2k`TPigo)4WHNWUo`wT4S%O0)C}RH85&k; zI7h>nhV>e*(y&>>4h=VJn9;CL!yye{qv3814`_Hq!;3V$Lc?n{e20eb)9`i;Kd#~Z z8h&2G$29zghRRZ8 z!zm3f)$olPzD>h-Yj~T6AJy2U-frc+=_)86cuc3qO68l%7;T#PY zYj~Q5O&WG;*rnk%4Tm&5N5g#@PHT9zhSzEM4h`R<;RiIlUBkOHyjR2fHGD|JFKYNz z4S%iSTqqjs&);hJ4;p?)!~d<}uQhbAog;pYhD$YU(r~ke{TiO5;Xw`Gtl`ZX{@Oq& z?<_Zh?I2-J!z2_MhKDp9*YFJ*zD>jXHT;T(Piy$HhIXYYr%uCF8lI_PuZHJnIHBR| zHN0NKztQkM4Zoz}lN$b5!&fw{fv(5)FVS$lhCLeY((pVDU#H=98opn{do=vKhEHht zLk<5;LkHVi)>o@xlZG2L9M*8Jh8JmgjfOXCc$bEs(eQB%zo+4g8vaScYHXBP?@|q0 zH0;;#H5yK7c$J3l((n!qKds?o8h%H^pK1694J)AFvc5$cHfp$8!$A#4HJsG&N)2z+ z@WUG3ui;lTd|JbwYWRB%%WG7;7K`|JI$a)w2CgIx6^&}efll^i^g;?%kM=8(;f6v8jss((vGfl03Am! zr1R-jbUl55K0{xphv~QUFB;=9>+{f5noj++g3hBW={mZFK22YvAJdccPa56HtoM96 zh!)ambS_;+Z>F2+6Lc^AkbX^nrS8sVeQjxPI)WC^0Ij80&^zdZ^hNp}{hav%BbT9poeoY5;H|xoy z3+R>f4*E3ROOMd+soXe|?Y155Nxk#}dJ$blZ>HPmE_#5TqJPqsJ(^4rs7I)+Z5bLdjKfj&TA zp#PyKs4dwnzXR<>GiZQT(-m|ReVFc{$LM!7qOVzgXWEzM&~jQ!@1Rf9z4QqEjW$a$ z%k4;q(Of!>&ZW!fo%A945=x$d2}Vcn{K18(1Y|ib@pRD^n5yu=FuuTk6usjq}%9j`VRe+{zx7D&H6mF55=c_ z)b?0LYv@Y4j&7k()7R+7^d$Y0Mh`H{?MPE7KJ2OLE2ibNfnG`fMenCO>8tb*{f7QQ zn-4V0?@0&J0ve!~(N%O4-9=xe$LN1)H1=Jx|7uI|P!km{q*G}FT}|(xPtd*eQ~Et^ zHrOn$741of(y??ZolO_h8|fyxi@r*a(Lbqsh*@7}+K(2}skDJ!N$;YM&>yKbl*!{>i@rgR(C?|d5heZJf_A3;XeKSCGw3CB72Ql9rLWRM^c(sIZ9d$rw&Z=~Z+s-AbRMZ_=am6xGws`r>F8 zI*R7e3ObLjr0eJw`Z9fo9;d(2$PBZ-c62b!q8HE_x`eK#chMd6C3=9KqJPqsnPz?6 z=pdR)C((=OW%N3_g+4*wphxKURLe5!X+itYp%mZ8R^zptHqa~SUGx#UmwrgUroU2m zwpm_V+MAA`cwCCAZw6gVZ={>(qx41k9{rsDL|f#T<#nI~X%3x88|W4ER{9{_OW&j4 z&}O-2`3bZ)9YG6dfY#FM=&kfo`UX8j|4Z#Y)*;ND2Yrbir6=k6W6g4hQGAC^wR;u4g+5Q;qMy)qd1n5e6d#aP z^It$OqRZ%=^db5ZJxWhfN4{B3OWKVNq7C#4dMka9?xpWht-vg=9qmcI^a6SjT}JPu z57C$CQF@X(3eEC8v=7aqWweH_r0eKobT>UnkJI01Vv$)-7dnjM^YyCVE9fG6J$-;a zN#CR==r1&89G8Qp(sb&lbLb+vmflOBq_5C}^fc9r&3anX^XV{(uS}Wah%Tfn>78^N z-AxbE<5c&X<;2l0v_H+F<7pjTLf6qP^lADU{g|Glt`f7pmb4EYNek)4bOBvW@1i^C zOY{K!g6gGaJ<+rqO{ax)CS5_-(0Aw;^hX*$-YmB}&7m{tJbE?VM&GBO(LZU631)d6 zX+N4zr_gzHIo(E|qsQql)H%^Cw>9lfhtX0xi(XCdppVi$^ga3&{fWj*GV5tiGw4LR zh~7l+qH&YW`9@Gby@al%JL&uM8~PhHrkLe)qXXzzT1IQ>TKXW}O{1rBIcRTs3B8`) zO&_68(tY$zdVn6H$LP28Z|c0jtT&Rz(GE0)4y40rI`z>~I+M<(4Rk5JiLR%2(tGKn z^dv9ts2M>A+St*6WB&GcdVG~G)-qF>Sh@X47Jd?+K}PRnvuZCEY|Hrq9q< z=mC0+en)?&u5z>d!PG~`(F^ItbOF7R-b6Rjt@LSnXN6h*Hu?g6g}zA-(UbJQ^jGSv zG|P#j9cgbmlx9;uoknL<{J@Lq&#UNKdKZ0!K1=t}_vxqfd-?}8W|-wB(iA#^j-eB1 z1)WP5(`)HQ`Vieo_t1CgC-fveL!C3t_QcbUG?fmbBWMQo(Ly?&R#7}vT=m~PdX0!{ zk{cObC-&B~9b!LCdy+oO^j8>uogNU8|08jLrhQ3IGyYeGZB=G^q=<53Xgd+}cVc=P z;|J1VjL&2^myQ!L-*~3uiG-@$iz$A7TZI?U%SGhBNklt0GX5UAmFbT%eIMiZ(|4Kv z8U2geXPM9q_u(91>SUnZj58|fX4znkHQ=;I>VwUh1< zG5>2!|CsSd>2aoi$MoN+QEko_O*@Jxw+rpd`2Hf=mBn};^)r1U)A4H>YW`WYhVhp$ zd>LIKqPK4(CBoXVa zqu52$hBAF5&0u;V!+ttdME)`n{Zm61G5!jMuc0@K=-+j8vxxa0VEQwRf1d7R`Ws9? zM89VIxAZR&<=SdYqeYY(FQQ#t8Q+7ZF?|rzGZ~*t^BI33y_oTHXoHCIub?YM)N?b_ z*U?Q(znAGd82==Fmhmq$ypO&kqWll&m-HL@r-=0xGsm0Ww( z9-}`~N3B^;9QDvXbQm2&C(=q z>JgFNmG)%(0EUOqk&GY1Z~>hlqQ0qgHsj~g1tR)?shEWQ6~nhPeIwn>`0WfoPM;Go z--{x~&3lahkbXixr{B^a=x-wC|69cTF?A5j8&BJbNbe*fJ(ckT=upOIFq}h+M9f#p z^fJcdm-$rrbD2J$u4Mc*^k%w_-YufM`$e?lF~&bdchi^Y8}uD|NW}a{Ma=&V?=KcDuagJ_0` z{JA39If?NX(2MCDieF$<`7ald|9Zx+p&RKvbgPK+9~F`RImW+0U!!l*k3{4@A|n3@ z#(zhDVfr6TkD7;kSpHbrQp9{68177ai6}Qk9DrvFFn%=66OlfSmNCAP*3de-SVaEi z;s8xs&G@zSZh9ZxCL;gibRXmQ(?j$K{Ypgslk^Y9Yx5D0&f^& zbRg4*(L%=i=~Oz6&Js~xjfnCtW&C1#HPdgPcQXEN`VielcZ!2FZ7+R~9;3&_C`~)V zu;UVhv79d2T*UmX8E#KIGd_)uWPCc!VZ5K=33Mvss~E1Pb49dcG1FJmJLrS-Df%)! zO1}|3n)VyR5ev-aaMKuZ5I#r3a7Wrz#C)ktAHjGp9mDiOTEX}#ieK7R^It-*WBh7* z8{;?9?Tmk%{+sbHi&)?9GyWs`DgBauBci?9LQ|)R`4UB}w>GpR<9jgNn+^~$|4=%H z7Sb|0gI*@0+$D4sy^h`@qP*MagLE6+P5014BFZ~LzoOsJ(;~|Il^U0t;b_{CcBKPE zlsAN?(`;HOqP!AXL1)oRM2w5&qJisihVK+n?%ni$#y?44Wc*&bpYaF9X1Km%_(!Jy zLjPcVzAK$PX7qZmI{bZXjUhG#JSB07ihi|O_BR;J%UA7%V=Vh2sz&+tK} zAEw6`|1HBm(BDMN_qT{~7qtkYy|J`4ZBILk$lqT?KaUn$YFZ(~Q$)-kpcRa-Ww?PZ zWc-y3Urldd{A~>1NuLl=&od(0`3B?Pp@--Z`W5|#o)R(NuMGc5U6-5XwiB^DJ;ZoT z8^myih~>$ld5oXP@KjpH_}L84rSloTjNz5^4iWX-EuvjdF#c)!BHc^hqVLgzBIY~B z@E7!yh;ki^A(kgbY>VSK!#zbTPam4b_z?_yX*T1>FI&;moa@My^-EbH_%P=0s1g~l0HLUqOZ_{^e{apq8+Db zvnvqBdOeShq+{p=T1zjd>*#j+9Q}ZPO24PBWoA7sXg&@6=ds)*nx88p6H#{1KSMFuF#?BTAV{GTh;E}#QuRC$%=bFOZ_!VvdTt2Pe`WYj>c9$=`qXnmU<||Yv^PzmL#TQ# z2=Zq$Jcf>=rSw8NonAsOqs!<@dI!CWK0LWEIL`1XdYZcJSU%kMjHWGV zYucNp&_Q$<&7(!MoX(^*w2rFhcA&m%7*@~gKzJj=JLr@2Ir;)s&*eb=BMg5xq}&2&*MP2kYPWaOfRH!={&lKE~U57Tj|~OKDv#n=Wd|B zS0&s9=SB1g{gnPlf1z%idrE%wJPoLxrvY0tz7JK;(Lj7U!|M4N2&?C1zyRZC(2M9? zI*+cR*U?+(t@IJPgFa24qi@p#^kaII{!D+P>UkMxUu1;2oT(!2M-HIF>1aBJ7SK{U ziI&ruw1(EvmGl~VFICUUK)sJMypz5}U!kAUFR45}P}=LD&1nnTingPvbO0SrN7E@H z4k7_MgI+{0p_kFC>Gkv;dOv-H?x1_=YxF<#82y@_q!BK&J#N~9wxqpiUpkNurA4%a zPN4x>PcNa@(=~KG-9Wd~$LT)0pMF9=r@zqOsa$JH|3=Ubv@`8T2hm)bN7eH@Fn<}t z4RirrLYLEZ^me+HZl^EMJ@f;5h<;0dpl9eGG|p`*#!X z4ZVThP4A;m)92{RbRRuTKcPR+pQw7?3Hs9=X)Z@w+L5Nwfpi4*(g}15ola-aOX*^| zmaeB8={@u*`Ye5mzDK{MKhQJu4{Ai2%h8;+r5))2I)sj1ld~Mn;?Mi=m0M4NVn2I3CgAbTrMOV`(W>&$YpP zwG1~<^?Vz|FJX8ky@sx(>*+&u8-0pCOZQXtJRFp(o`(a!VEixicN&djl`KyjZ9_ZI z{&X-MMKkCaT0jG|oHoz}bPc_QZlIg!Q&c@?2kqL&uzKDO!Y3G3&)Y%xCx(Be>bX0J zPlz>_OFe%F;qw^IpgB}Mj|b_+49}vo>7{fr-5_FLyNTXUAEGbNJ#;^Pn|>+cSgM}i z1Ak!nCmPYhOm|cDJRh7Jb&@dbL3`5?)JrFd9q|4wEvGYS4OP$oLB53yUryC?fDpf) z;f?ej`XGITK0%+R`{~Kn($=)M*b?t!(Lr<=9Y;&) zRH~jog!vXQyofHRSJ4~k&GaF+{442VLT1{)|N_q`lLvNuE(QWie`V4(n#Lb!y=zr)j`ZYaC9awjg z-$i3+JZ(ce(1BDv4+`^n8P1}4w1{3rYv_D>DP2Za((CCOx|wdF>bX*=_i={z&{ydp zdW4>$r)jf9b9p0aJWZlKXm2`#da0jIpcl~^I*%@-*U{B<9lf1CPIuDX^kw=weT#lT z57A@v3;HwtjYi>IRMu}S?L^O`1L;sYmKM_KbOx=Vb@VEFExnnpqg&`!`aFG+zDGZ# zU(=KHPpY>vmm`6;q8{3n4xuAx7WGkF=4!T7^oNM!5u(-c42Mv4TMdAJ>-#ATckRVr0` zP)|DvLl5mrRl87se+fg?J~*7=(KM4wxd00Z<<2;Q*}QX<*56~FqiRpw1}3_iF7KRM%8_1%&+b{!)nGa zpo{2Ix`M8zYw3Erfo`E&>2~@!-AQ-R-SlPpHa$QO(!=y?dXk=^r>Q3Qd9gg|J~mYM zv0)VBV`&0yMcYvi?Ml^sZp`1G;lXq`&82y?h?dZ4w1QUAYFbMh=mNTkuAvT@@7hrh zRnOB#d=G}zeRzb`eR$ZP@q_7bnk#xVP2HD=>b^WIVf;iol}@7-w2D^KTG~LD(iLiwMzBrb1FvIG7 z6ohjn+#CB3T0~2zdhR&Vr!rhct7$E5piAirx{6*$SJSn06WvU=(5-YkeVnTIVbGpk z4DX}+>D%-GJxCAJujxs8ik_zG{Tr08-oJq^dEWy@QT6@}!s`7S=wW`2GwJ zrs{ni#OF#F>o$)TiTEp_6Ga34O{a-bnpQ!pM4VSw(^?Vd!wqzSi1Xe>bg78r_X@g7 z#PR4lx?05XWi4GV;`p(FZW6Iy+Dx~I-SGV?x?RLLdYtYQv7Ec;N3x&5^2W({MqH+d z<*OI5T(RmFqRM zLp@&@^&?ud4d(R;>gvjH4-s|sXBb&jdomf$716FLhO0%iZ!^PNM6^?#Ut{K-5=MJp zX8Jx6?LNuyDG}{Ykn=NXk0{4=hWm>ij0c8`L@d_=hShl}mTx`7>O52Wo8g@zmRC!z zUpTv=Y&vYHGp(|w8t}uVT5?4hz6+f^y}n*cmWbp=KOW?7@?)px$dXZ3T|K?5{9-?T zV*DJ*p`Sf66T^ODh(E`4R(#_hWlFBAtUgD%>UWd=ASaEc4j38M`-@DW2$G>R9YosbZN=ub7s%3 ztigZ?%{8O03}4Dl_7>+Smo+rh&6+;10mc5`zOboi7}9dsQ!m+0!(TYfRE<9M?-~>9&rx1S#D$l4Dy%&0-h<_hYEqt@7w1`xV?GHEYf|2su<~$d z3YIsuNqIeREQ&&$^|F?CVw3W;&Y|^z!%eWfg-y!qj}1lcO;|6hym?K^bA^?M!&R`n ze>Evjj^D%2QQl2W%8Lyv4~M&8d5<+I?=%L{%U0u6ojn7S33;$_RE98V48t^;mf-eA?XyMCo@G@OnihR;9 zUGZlvM}Cv?vL80j@sLHmtoHeuls9pau5CvjN_pMzXO$OdQeN~E=oeYBd|Bm9X;PkR z75W)@q`V&Zv&y@eP?QWY_c;Y&n?T4l5OV2oV+kV=e{?2h*?Yn2R@)yr&{+BSl=8X2qt{=3R%T}Gej zo#GgydD=`n^_=!^ZJIV(T2q?g)9l%Lr`X4D{?*}Wo@e`Eca-0-o$6@Qf3y9!bDFj?~;P9QyTba9mvE!508AE(V9jhGx?vp2iN+o{Xb{vzI&`8d0vN+5ww$ zxE(2}*bh60$b4eJisN`hO2RaWeO6*$ z!GF!Lv(}n9R>}Wkqcd?Rb(NwCnrkx3&|N3dP@C(%&Y0aL@4Gr&^6M*3*ChNO;acy( zT&_FN2AAvVC~UE=kMO_Sbt^XANY~xih@)J4(DvpoxknZ4nu#mn7*{nGBi3~Yn{5l1 z9Eamv^DtMuYYVz7!6lzsXz7yQI7@V$#=J=`1N+uiuD8*ntzGh&_%^QRFmGGePULUr zYKJ@>T+vt;9bF!@+~aD2LOZ!SqUD`k!*L?g#q}LlSyxvJ{C}RSFIryVlFvd{x<+H( zeXdE!|ElYJbmwcXU1-niu5Zwu{jM~W`G)IiwE0crb1YGB-57y{KDu!;mLOR-vf|u z%Dh!KMx$M~=|&!Azg;)vHw{ng#w?WblWxpKubAlJC^sj-S`5Xb;52WVZLwdMjFyi+70<#yKn8rtDSI5!fr&M+VAbgVXT-_ zb|V?R{)64X9#+e97*VJ;-(gf@h60E2Bg!mv7+bImMGoU>R6EXLJc0!)b{OfX-S03? zU{IGhj0{v;>M-gsbjCZ3_Bggra2Ri5MND)U-O-Pe9L6T}*<^>Y4QW#xMj~dI>M(Yo zL$*7NLs-!XPU9;yu%**TM41bm#$YV%LZ>kkrCjPXE<~2YPU9MM&wrdoI@a6~r?C#J z@u<^~&oh4FG~{D&$DGDdjLJ_DLIdA!W_*w4zSGR`p`v%285^^>(TD@h4EbH5 z_nR57p|d_{X8adre%Q>Ig+4pj%y<|@f7HzAhEjG$8uCg1rz4Gg43cLe4Y`l^Y^3o5 zX4n*C6rh23#TaF%_U;&CA;#uCF@}bv-5g^)j+WgUW8`B%-4|o@Mk7|m8?DhxSH~N# zBNW@+=#2HyqPsBzHPj{Ql8h>}6gd|oCvNC0Nit-EUz%jh zKu=teWX#4G9KFH#5tPMsPIxBmFu?3~%Y%t`b4n;2+ z|3-g~d&#h4^h`Tp$bIIr6GkZ_r=KukJ!8ni;1NSE6(PiQXw8thBM=>PrGI0&jGkcm-Pfo_@TfQd+%NJ8c)nYa;^HkXMJm@8T) zUPpUkWTFh68!HpD(5x0Rk&U|IWa28U?s%DKjjl_OiD)cNOPSb;a-`Mn?rLE$QHwsb zNz7c-ZkLHmv49Sl_zQD6WugcZ5i;?f%#B=bxmeO=Viv}?O(vYGWUSc868zV!Mz_C% ztj*-Et5ZJ@ldkU3_aP8<48_ll>WL+*i<<4h`j0Zu6Ae)hU~8BcwH^a-e$;eyz$H;# zFkUW;T8WrNQROIfanvnX&r3ABd=%c*-#!k-MM#;=9mXQvJ_p4_`~1b4u~?6O7BxDI zBrWDDw98n+h-R@`bWWCLEM?dcrN!JN8LqG*Tv~LAW-Mb+Z-x>PUd}M?8%K}Rj1^Y0 zLyI1-8CP0CyB3|H87r-zO^cqa8CO|BU5hTzj8#?;4UBadm+Ho9w7bQ0&A3{3K81y8 zafxPJqesaCXpwSL+ql+Twm3($aX>d#V&UWE%Ol1IdfdMd(Bk`H{TLtWaqM#}h@GwKQQkwN1y=hPEAN$P(%tDf+elzW8p z+7fz6>QT;XOOV^<#wVQDmTEh!SwTz9wi z7++&5M!xXpZtrO;9irPJw3uz!V%#0A2%8pj1PkNt#0YG;T5PO4$>VH}Exz?r*zDY` zJxQ{3t-E0>b9eScN{W{FAfno1imL%tp6@Z_YYZ{N(V6bvR)Nj5nB&---N|89y08Vi zQ>+|PrS9(LaW0iAh@k@>jE5guX3Nbp| znO1~Li}?tRuy^XEzb9D{=pC0V`(!Huy(8}dxu;kW=$(foVyYE^-YLTRc3)_<3ccf&904l= zy;Ftl);-ONK<`}L84+bx1bSzU47KT21bRn)uGw8~MWA;skyBy))NiJb@!`%w*(r*L&JNiD)%;9+w4a zup-bq&q%~PD+0YEpQ3Tkw<6Fxze%euu_DkrTTz&Mp%sDNIfMP7`%)_cz2lK;FS8=h zJ4H> zhp^zS4@i^dc#>qnTc5;%*1g;lDgA~+r29ILaaztEVq}Ql;Atm&S%=#T@GEoOoY>h)GcOD#q|lkdLOib%ldl0t8@BI31}OJ$bZt%x`+ z=1Pg!U`4dhVpdDU9acoF79(H8ao=f0U{52T^m1>sA~0IyCtcl}tO$&jEwVx1Wkq1L z{JS$E?zSQ@TCg9+d9D>9+Y)-)eXkXP(Q-LfnEO5}0;45KR^I(q1V)SeQm=c96@k$r zKT+&{z>2_Vsg!CTv?4HC9+d(1kQIT^BEM4We%Ol8wU`~!j%`*100%k240@TgS*A{sZn(hDzYD zCsK-*rT)TW$QL*3r+lfS^#ihZ|IE`$&J9}2 z*W=tLJ&}^4B}#?0_)~|}W>UdvkMS@fV(hZ!er{61ub~QJ)+3kucPj$TX|q&!pYk~0 zLwsxbF?siYJ*_^IfPB-|{ii4LYXr=*6p2<<1~ipFQQB}O6dAYF;cn?M3a~!f$~lD= zf4g*8S5JI7qGH?0L0{7on#=CLpC^8kgv_%?cYja3xtmp|i|zrQ_Fs2QZq^f4%9wn?6Mq^g?@8G*5N?FfBs**C`PyWr3BFs6|vsibO;%mQDI^k6qSI zdk5|{7NH*#Z$#1-D}O-iP=i!k&zSXy>Ua%~RIbROv4;`x$hQU}N5sjr=IMe>IC5m% zvzT^hog7~wGD1>1+vQ71k)!O7BhYLTwzg*aU}TC+kM4+BTx)S=rMVVkVRY9X97Sxd zxwyAs*X(y=>xj&?pO)DQu~s-+e)M>mZK0Yi6$_xd-o-Xxb3KE7EoRfYU^c&9_GcZx zN4F+Kj*tBU0keS<+uw-lv@Wx1tF_2UDxi0nRX10QoZMcn?ra|UN>b#M_R==HXD%8P zIkmmi=z)0*4R1unBA%2h{1d9Fr!WQ7XE;*7vH5CwMq1(D~; zf9M+d5>13mcXFJ>|Mu^t8!PS8F&*K;bhq!3E%M^%j;B$3LS#*BEh0T5uq%wbB6)o!xO zC0)cv_^;zJjDXmvzOh5F3~E85Qe$MGU_GGgqtare>m6zhMfHo3HDq>h)ZnlVjv8im zux6Jv5H;L>0!4Rt9YsfFc9NmkBMZgrBilH!cf%tPZ8n7Z=-7ed^J4hZH>|)oIbUkj z)AY7dWv@gJ;``}sB?TR)UcKaheSof3bT>?6jA^|+82F!|{65>Td(x-t-PBj1*3>2s zN9qSi=&KjmF2@e00AWsRsrlGe)(PR9PiMMxr1+R*#esBCjI+=^HM@xEi_#TOpE0$(Sie^c4J=-4KX~?R6ss^ADSf*v}Ag6n|-wGN1}E5m*cx{)S(V#$l9ey8I_= z!1j=H_&P*Nr|a^cirk8U++Tj2UDk(fr=)ezjbU=5TRuXThQDF`5g3DsT>RmabuXeT z^drGV!u|z|^bVRdQZ3SvELo!I$a^9FM#<)^AI*~StdAQdqe(wjAOl-39{DqdnEq*j zjBxp^!BYH{0?J5~3&FpwSiOOr^|ee(9VytS>m59MpR{1@JRjr&x(PaE+VR=)ml zuz8s>-v%G{qh|9S9xct2caSIG&urc{)x4z$%XzAI9#)-nr1~t6zSB8u86xgQ%3b(N z|B9(L89uguIoqS?VW$!K8dCS-FHI8q$p;9$GAN}aN3GpM@mywbs`!d^}5j$kF&F+LTVB4H%mz89uY#uBrIUnEv zWZR+^M9XfD7TRu3v`hb*xo#e0&M*50+ww%aERUJ8d}L_;t2qB?RAsA5w9Cpib5-@1 zT)FD2eO2ktB0X2OA6u1Q8meVSU_IMP6790e%{fX2$^-Q(-dt~MA1edQZo`zOx6sdvj*qlQw~a1MYN4wyL3Y(5 zBS#_%c@i~y^w7v*kwYSV=wSy_P@8jrCNUA+6wMsEJ$hthByyR#b)>m^U}pKWjG-p5 zeY({Ij#l_?sVdiLmK&wwaq8MUUXP4K35b^xqMPG=R5R#{kHlTHsK~)6F9y-lDm8Z~ zIyR}%%q_xa#&(6GouQ)R!^@CD@wkgnp@Y%bmf`bDM53q zGvi7EEeWd&PtfqiOC9ah1oF3!K^Nnw(BG_6b?>Ow!?EY?7>}M*eSk=*3^zeSt3V3r zB=bt&ca{T17q(IrA<11^>fKw*jORJks_7P5h1j7=qPY+~`fE8{SvHKzp2_;C)>a2} zZ{0$Vix}N%UAijid^9t-8gOW2t5x^glAe;c6?;eOrAbn2pGJu&IQi;jItH1f^}S}9 zuGw0xNk?>w8I5CVdp$M2Sl^i*S(-F4a*}g`TIw_@5BtCVS}JDje^wqGBqWKo<9#d1 zHYk`)njb1`@HygfM$mYPeesQ!d8jjNIIx;wQVpkvx5u<96x zkt|cKE0!~=Q5-sEboiKHCU0;7R3E9T($9*MF3t$XhBqrS8G{OApN;aUF3v*DvQ|}V zun!8)W9G;SZwhvK;Z4QvhBIIo$da0~j0s=;_)dRvuot_x_Mn5*3kMkWiB(-I9*s#k z1H>f$S1&m@N{-R^vuP)}NjWU&K zCJ1t*HWM(RUgmMxoc{k-f*j33&QzwK2F)h8pNKDJtZ^nkowo;`s9Ungcat4BySSgmWsE8KSISM++A1qw@ zXnB7vEV`` z{u(zu)HghvUzBh0hnB-%6MA zV(}*%j*P1Cm&_|0Pv@{m3ClcD_>(<{^^)mi{8{a>;w`1^*1R|&JnLnpTM6NLue_wa@+vY>M*&W152GTxroJny|BmxSeA-k-7yk6*s`ag!GrO{HS#{-tzB8-(dh06Y&8nG`F{iGwPhDkAWqnzFUwmPz zPDrb7m{&1tPEp;Qiz>?->iha@%jz!9o>vnnshU+Yv#5GreW2JoFn@qm$E=$2zGbzu z`l43+lNzU^=Go=*P+Rr?P`zb!v-@V``+fev0Mov*D1Ci3<<;{lD#I&H#&>|qs{7Vg zl_5R2sA&OnA^SGWnNwX}RW_@pzVFQP@_>|^niA+2NJ~je4Wy<>WFJKKshLw#*{8B> z`m8>wDarl%NOCfg8zuEcPe}EBXP1?utNwp)M*YJ2@Sga8zuNz2OFze;DxY0HtG;h$ z<@{OYm3@n|3bOoO|G8HB|NBLi#{3U2F2-O(Sxvcok<9$$dAV%N*p>pg1CU%LJ88B2 z0gOomaTXX%RDXW&&u{7+F z%$8TF&*J0x*-qILYxZNB?sUdG^@tW8r!&GH>v49BNOHDn>+E8WPjXTSl_#}jOK0;4`=z=wI^P-D1u3Jf z6qeH8=|WB;qO-&1Otj~r;MOWfC;M2B2hA9uJ3GN-`CsZBgIv!qLAFF^rwBdSp<41K z79$SD=v|y~?UAiBmMGqXuiEN}vzGN?1k7cXg4`Zd*eAlid5MlPbo;v+$~R*ZBkWVK z5G}2mWMU5HZRu=>Iy&3qhdZ-9&OXV`cJ|rHtEI3wJzfflupiZuQEV^!T}wRD4fYW_ z=DkQ-%MAT=m7bsMFDiDs_w4z*b{YUQbYnu zPEjqz=OM#dy4ogv+Qu1!cDRzU8dFhcqWvnhg5uG5v*}-J(%YTw>z8<(y;O72);^e) z7N`7QwAhHSw~^jRw69+*y(#P7*;bZCx1Yc$usJ)~|Ft-o3-=Y8D8qqmmL+N5D5A+? zKP*d;h!5nqwU=TlAs#L2Xuky|*b@@W6?^TaIwI}%pPb1NeX&#ylxhEZp|q)Ug#9@T zB8T&Q`%4%^Q68?^?vmKbev>&^I|m2rNllM;=AiHq9%qin=^Bo18>p6Tl`NYYWew)& zID-Z0jht;f$Yby1iI)vdru#abX)@jnSx9?f@;~H?kp4}?C$LrVA6;%0zf5)919*E( zHj(Pe`ITyKp?Nd%i}H$6CX^Os6=>Q1qCi%0alo5iSX`2o84PC>Pbw-Y4CH$AB)PCy zD-NV1tFLZu#*CT4T$yQ^W^w?BgUqaAUqMbVjU{+XOLDUcN_-jK5?^6KAlvK9Lp7BF z*%?;W)uCKzLdLv0oE1|5)BoR~={w=FjjJs7!&<0`GXV$D5v)6-*pcl$9gP^gnU9 z$&@cjYxNC{_ue=`QeS(=>Ceo1tz>d`MqY8SIl*NM_)EO$zC7P#)sMk+YoRl|d3oA` z+WNY{{IcqKm0BP$v$7$upa>tI9iQ$kk^WQ%hrq1*y5P)eS^b5+KtW+iATz5ZDZl3Lh}Dyy<@bAYvQU5wgyL~(_93AxS$TP-d0vd234zk0 zoMLZgmNl~S#%HF5wPJ!V+h-;Dvhw^I(o>~_0|B2uJy@Wx2t&O%bAq=xOLaz3aTa>M zM4MGvjsB{ynp4-H7BRSR=H}tg$O>TL0{*NLRY|bCj1qroz>k4eaE?tv=JMthXL&Ox z1qx*&OfU8O(dIxP6HQX93z6QOlGF@u<9-WmZ<$%X0$&NY9$$T3#+({?=7Kyr!D=Jd zZgxr_a~xK0ZppbGeMouU>nA!<(IB4 zs;sH-k2hB)#zNTMWrEjNa@H=U)Sn)}l26j4uZzcr?R?ZqD=GFC`13IzcNx}V6`8BL zv^ccQ7Wy+VC<}|u9>dsQWM>rzvhs^ClC2U#3nJq%FupLa1Y<3jJgzjWG^^<>jRssv zAv!Bdc2ii!%EntWo<}fqW@Ts_<8Dw!iR`>&`^hROEX~Q)%B$zpR|acsG$3RUhjpLq zu<{Er#{Cm~B^kL^j}(_=_zI*6)`D59GF!F>jL8xie7MqV=$D3dB>Vkbf0JEmK_N=U zpf@`zSW;-9sbS_TDewo=)VRth%r7b|z$Rku|I^eMMpJxPmBE}DdEWdYtk>!}H8VZx zzef8DtJ$(8oV{1K7ADVEfPF~7o0*Am5^6=Lg?``UEU7+UHtS+@D5VD5U=@RzOY=f| zC+zYAMa9{{?J%oAjsl_moHbjXcM^t3c42Y8H#Bo-0AR9lzpSQgW~Dq?qw&sH#%Fe6X+b9TMly0z2V&$D!H- za8_Q}h|9vk9h;Y&Ap~Sag}NQb^jz%zvho`3PpwrR)`QrWzVTVAm(57tv9HRPO+|GsHYk5CMw;yO8?Ddcaq1K+)8}tI z6me+xr59s|V{P|V4d#w28~vhX=Y{VF)S8$5o^@7-6^N=Z;6i6{)sLR+mI+^tHpi@o`>TfxpRy!D|KDhoL&t3-wij%hd!NVcqrSZf71nZ!^Ilob1N z0>wUm_@Pk_25Jq;h7_!f{aTDM=k9mb zFUZK!)VZM5=iytKj7IEy^GgeON*!#P&sUu74P<3x1X9y+YGBPQJuB-(ooQH+R*z)l zmEyphkrBRUl^JlfDa9VL>0VJCgtEP|BgJjIu!9^9P;#KKmR)voGTf}{r2eL56{6u2PR4di%z zpdw2%tt#*zsIWi@fRPW?`NNSRIQiB66XRDA#`-IPer^A?Q7nMoGT+PDtSswHz)y*d-Iin7*TjyFHw8$7MHQq5C{ z9NZ1ZAzH?|mEgSHPKffXVQ7tS_38MUmRG|=hbJc z+sNiwpInfI%H%l*_H`JDnZCvqGEq(y&c4ZjyEefwlB(gZad~L>t**DM#gu*gSrw+^ zkeyqCJO2J)2Q6&ryoqZBdcB$rmW{O~iS5 zlZ%?r$*vTj?oI?t2wqbZXXRiFntbVD|*O zBrP}<>akFV;e&tN*9{D|Pj*}3=O0#%!I~OmsbQxg;fLpJA5NRqO-p|XzW;+$nwpx* zY8jom9G%v(`HOsVSe5%>R+L$vTSLs(6P?DlZl zpc)v~KGj=lw4dXsYt?Oy6kcM<1)92TbJhlcP0_r;8oEU!H(0Gp&D7vjT5zggaH@ZB zDm4^2Fc>)~I5jvpHAD_a;nxMhOD)`9JnIzDJef1cVbjs1`T>{DO%Hcg7i4CQ_u&LV z-9S=TDsqt`@2{DAn#Oyl88gula%Cw^GcSgM>rqynj2#~?vnJzcR4}I|zpVaZIRyA> zcy%n#`V7t>r%dWn#h;7KDHxrOO$M8$x{IpS*3FtzH>+V`FqPXT_S(29QySXAGTvID z>Iy~O0hE@SCzf)@@*mDGu|ra4PI4+ynrZG(3vmB)i_Tp|R$MMJC z`phn`oi_sSg5$1sAG{5Yh=!_pv!}xu)pN=k`ryMLBX9{?ArZ(qqjvs)KJ~SIDpCg` zrmU{KY6RX^pFgiVC#+9( zWzEcnsu3xOGT+kZBUiWx&6rnHE^o~DsmJGWRB={G*cElymL@Ad*jn?%)mOmP zWepNPT8*1|yyar;mCrg!&IsPT_LnxkeGt6)q;}0}P~-51F_MAJM!f@;Kc{9^!<;(v z#$&1Ue%MKqY+tfi+=&HG3f27vbF)-;v(IXgdeXAB6xcC_op(36lHqx>I?=_IX%XJ{ zQSXKN$IBIE%YH_(}^NcvFIh%+%097#DBqqLA&6R?-V621}P6 zo7^xrcfd{VPzKL+Fc_?h-?MHBG&$7aeiY9m8(ndP4Oc9`I%QHj)I48C$vHNd^um(d zKvpK+zA46y6&|itzhKZceWz7EMI-|e<4fMKDh^%ztHVs#8pO>#>z*>RHa$i27n)be zXT5D2TudBAamQNT`1#-UbG9$LFrfDTjZRs3eS!lJ-(Xeazg9l#V_w-7 z%wgN~IX)3-el9Y(JXp1iD|L&~=f@?U)gZNAq}Z_cnnJhBLI?7^%tCc{HF)R2D!{r5 z=YjUDH%mhA*jXzBws~~hgyx8x>NuOHj^7#hy!xC2Q z!7a^NA?6)JD_Qm2xz84?8!^_5!L23OHC9S#k-QlhFfSTIsll7UY2i16t#d&+amy>j zfyQczRT@r$a|-0mipJYo_;G7+a3&netqwQuZpwSs)_JH^vh2xu?@qm?B^zM)6+)x; zV62&f%_+_)RjpCy#Enn2tYtap`?d0RfO#Gy7o|9@Z?tt;`zEYMEhi&msHcaVk$CH7 zd$MLvudJxR2O3JOkEW`V6ze0WJ^%TXMLudLpKkseFMQ2tQFK&u^&4>#FRvB&^F}AE za9-(HX}`*LgM3^V-?s_AGBK4A?O35tep!9cIXq21k(@4R#b%n+W4+{4%HetC)5_VB z*Kg+aSQ%k8{=Cty6{y`C9eaU0+U1Qbigszz40^u(^ zK0}EoK7_p-s*e{0V;sRLnXuy{m5uX9sQjaYx$u$8u$LVlrfi(QnabZgm`A=I8G70A zS@g#F<@4sDmmR5%(+yQ#ZZJ#ZR6D*?&^RVi<*x|lx4yGvM%cCHDm|EtaQMrPr>lj( z?0Ax3_{*-o*%XSgt1k+LhZ92qOxYWaED6i!{X;K%qY*CY_~LKa%Z_g!NsDBy%lMDO z`aCZzJr>jQseDP7@gIlvSHiH2`8cef*$m4#k3;`o!?29=IP~6K49nP#Lw`O5*cfJt!t*U62jl3I6G0DM29|?b?zIR zSdK;bvvtwbmtRB~AELZ$oy~7}*t(kEl(3x>yEFlY!IWV`YjxU+c4~*-Dqzr4>gea@H|oFNGi|&mw0*BfvA2n2aacWDwSs& zNO~2mp$+s>x|FV@*U_8kdU_|_Odq7%>63I9eUa{?Z_)$w5dDOHNl()M(lZnXF10)n z*e%O)$!`yc3A8QkOncH4I*5*>Su~Hz_x+^2$+V1C(K%F}i7)vsrz_~S^d@>M-9+!F zkI*ORF8UIcrzJ@F?@;v{j0hiP_)GdNRlmK6^xqk_;V>oh8&tl}F5x8Ffu2X@!3dJx zj}E0?noA4mczOY?pcm6Rx{xlVSJ4~jEmWRUC-vV$AEfelF^N~dnF#;Q@Lu``Rlk*p z^p6?-lpd$*HxiNl3&Vd=c_M?9A4TJ78`_EXpnd5;I)Y}>v9y>@qSNS1T0`Zz;Zpx1 zx}3@bsU?05Ro~-6cq7C2(TAz}twW?g%kYczRr)slkRG95(3A8>`Ww~ptq^I4i^kAI z+Maf$y=WR8LPygaT0l$bg>)uW4+%!S3mINUucd409rQlBjqao`(ATIu=uMVK9#bxU zLBFHFP&pt;xbC$f z|8orQrEgL7n}0|@#_$RHBmILqar!9jh^9%@LwnLRI*ew~Vp>5jqP28BT|}2rdAgm{ zdjqw8d+#=eH_`j)d-OD2gVS1>{{i|G-9z7_$LJ~gH;u+gt<2w^$}`j@JdBQ^RrC`2 z9(@8Qdy;=Im8Y3Y_(zJI9Rjn1XZ=*@I9-A&)1U(lavGh7r%d97$qI+Tv3Q|WBFnBGV?(MRcv z^ga4H{fS24gjnj8hY^cC=ny)FPNCKGa(V;ZNVn4$=)3eY`ZtZj3AfbOl@6fUbUK|w zucGVeTT>71O-Is9I))a} z3ACKn(sgt*eUv^=U#AD@*VMq}wY0Ad?M(a9;nYXR({g%g_^Pm~Q~n^B5jStLa>Nt%&7cCt{nskKr96%6*bP%lKCqew`i=G2cfb z+H->O>WNvH|3}9E!Fah~mU0ad^F`ARv?_V@ajHMIz26u4VXNBK~fp8yWu~ z!;jFXM9jBKME(01zn{L(^g~QP!T9g!kBrxG8%xTG5K&H?h_po7nd#k`-jDHv=>MYb zy~CrZ-oO8u-JN7gHXE{mB)i$ohTcnd(h`sMP6~B}r^rowDmg4hNe1QsYQGB_I->bq^imy@eXI02os<6B*D!yHX?=eLA z{E2;r`xO6Pg-2BQiwgfz;VBiGXak<-XNdo~3}Jsnh4od~ScQcQVMjj|PE_Gc72dAG zCsg>N3jd?R&sBI(g*xs@Q7>JE4OQ4dg?&_5slrQCI7fxIsqk(U;_}O#hu~s2#P+}q zF*UhieHAuVVWA3(RoG31y;L}sA?ASzD!fF6m#J{J3g@VBfeLR{;Ug-1LWOHpxL$>? zs_-=xzN5nTRrs9>52)~n3V%_d`&*!}&*uFdgxM;@tNh$Jf8dkcy$^=az3+vvkK*oq zF3d+4F^+JG3a6=Xz6uwraIp%Ps*u0m$@A8zkU!AL@$cThLimn~zpq06SSQmDsPKpi z-TPJG{JBo1^UYTbgDT8cA%DD+yoCzes<2#z`~^;q?@=neNQIMBI7fxiw} ztT=ygxM+#tFX2T`F;|nCsbIfLjHIs`A`+|=Q;;ug82^DwCLAby<3TLU%onKJS zLdH?wTU2?)`j(m5f7ooC+WFAr9T8_)lHF6p4B-GQ|0O857Tc zn)gj`UKZ<>ulgU(NvL=!L!94F#RoBj&SVvz$`E?4A94O1#-V$+N?*wk`dahpS5BER zdJMuDmnFk0IpWv9@#b_qnWi-#GhMxAov``;_}nS^Qu_ZrO?|@E{C`iC&$<3TlF$CM z%Y9+{|E`jJcFj?@6hI z(JkG1lKEI(FZ@4SZv*0;@n8Ol-Xwst^KtCc7WpUn76F`{k7GPdG9i?FYyXvxb3niU zCErtEXV+uTS@j^N9_#TT{-0eg_b`*eTuL@D#mz|H>Dtix;Mf@z9fe1vogn+}I`PGw8G|7q^#Am&-k-oCB;qiOP24f%+$D zE&ru=bXsz~rXJf->e2OIdcQz#s)!(;9CrGbUPElkV`xL_;r7XCyydp{Th`|l4cw!4v@Z|;#lD-64{n+YylRsqCt zTpRzXmx2E*6MCorrJ+A>I~_Zthg+8C`}((CM+sKs_2(z7}r z)w=Ai>Tp!+fTPYAj9xi<*CAiW+|eV)+%u--=BZu#B1Nk`uPUP=cl5B)D@G3opNjWv zXRPm36`D1#%G)@&r&o04MWKz|O}%W`_!Z;#PTG}f?C$&Pllp5_BQMGwx3^N>)}2L$qaAt$tv1-_eUl_Zf5B7@V2W_wc~nud7Sv@IB?}cuV<3 zsEc*1G979e-Kv|n96K?-u0!5C&&4WUIe4_wsXzYNf^Z(%2la64vrqe`<@%lQXvVDJ zmv|ed^}c(HUYOSFrpi5&8c(WI_1baIWbdD8$JvrCH+znzdbS?l-tVLG?d3h;7re`T zE8687-PO7sv2K@aKIRQTqouv>`i>1g%2p|Xqx`uF`vHf&$-9&;^W3gcV6F7|43`}-w(Z~^CZa& ztt&ihrdH7o?>)~~?K$9S`Uz5Z@BI0IUK=&&>aVb7`zkzt>c_WNhEub)Xmva@;BimR z7VnJPdd^?#be=dd?3q{DrSjuLDa9Q|Z#|S!=jY=Y3-mhkj%O_7IJ==|!`TJsv$+!s z4r_Yu=85ht*Y=R^?Xi9kX}rJ>weBYIK#iao@w+`llW{b)I%~&z$*NUajbG z*wf*&F;MCC$)S`dv>4j6)hE?W=Xh`5UY)Vkvt)a9*4FLSIa|*kbN86-)p@J7SI3Z2 z_09I`ao=c-%a5*_Q(mFh?t9dmb|uEKX9-8L*6@Oz%g~EonxwUuwsYgG<<;KXt&|Rj zt!c}veYYd*uwv}Ss_oUcWN3}X@6-#rZCqZRcl+|{@T$ItyHD(XxJRRIhb?n^^}>wu zjdxWSWZYF9)4Hd2I9%SU+hN`048hTnJI?c=R`A)l-0}OWKC9ebotU$|y5-i;*om`i zS1db`sjxU1Fg|$;3J8+^( zE6drU7c4u#^QWmZ=jQf3tY_EV+2}KG0c*h8bvvADcKdbCtoIJ+jdORhpB%2Ltn#d( z)n6X+WO#fX4{KvOqFq;49i7zisP5^10KKzS!vj`>EeEWEy$8xG*yep3ki8*)aiOksN6Sc+}pX+r!NAr!R%KKZ5d&gRJ zsV*qra=h>2EypiitkrGMy+d{F@}(#0#?H+d`yV;;RL*+;%31S&|MZxP_U^h!s9j-WeV`Z9zdwkB-%KGPF874|xh&ZuVB@R4l0+I2Lma<|_^V zycPFi4OlS_WXttcdZU3C8#_DwI%j%~jarQPIvt%eJ$ZB{z0O(bb7vX+$+8XR&w_#`Y zc#^tWc!!%0H-f!Ku?aGobTbosKaa<#J|8KsFr_Sa08>1v-xne98CSPO%6+(M zGWzE7`oiN&tJ+FKLhK#GGJLWH%P$PYUeQyzk(y zLrUGO3erbN*O9itelVqFRwe1nq;K&Lk5Zq(K0DR7kcU0fyQkv1#}`J#Oz(;9mig@{ z7Qd$u8s@NJu)+KciH12Gc~Z>G-Z;zrvmDvY$+_6(nOjjG+pHLgkA=+s1JOw4a_s&5 z=FPY$NjLd=$$-hXhi8}t1$fld)UkEQH2G*>&}=ven|Sl(T6px-EUb+UxOrzM+#WPr zb;Rb_oYe>)EtuU=^N`8+!G+E5`eD;*u7z6Ed<#3re3M($nE9s{538ClB2wG@6bg0B z>Da2*H7m+At)BTC^v9Xk!T#~)PL%t$`CEP5WHt}O<{f4xN_p2@SVz;|Gi$^&?R~Qi zKA!x*S_j@#w?0B^H`A>@VS97kdZY{PBI{OaLu}A>>lN&2Z`ZBbo$=_HZuLbES*lx? z!%27QR`q#!*Sv1=QNFwIR&N7$Q+4ZM1b6FJ8KhU}Ru--k??DXBey?sFLyP~aTbDxm zH{JRh-v1pcXzo9B>n~ifRqNJ5RO)<>^|y_Wv^RlJt(msoi5cl_4lhKR=d=}sAG|*=?z)%?Ev+fvykF$K%Ml|{mpS1@S z8|t%$<2v(vpYWL(RAo=9 z)ujnO_)WFE@a6``8i!uF(Xp<^px@+J@1W&hcC5Wc*>?FD!ZSHOC!4X(fg)&#WR z>VS0<>hN&D+JceuNWkJ7Z66I-TVcz>pfw#QEDBm?Ax1+3s|v-|XkdMhoKv%{0$4UJ z+q$<0o>0%W?t&YqXIp%4qUxH8+i2nAi0 zZ8c8AyQ{LT7*3d-ZGDc|HQCmieKqacZ0l+?-F4a4W$12mvaOjIVso>tr;%2^(i(&= z++n4aQH(E^th646EuB|dSD_`kthDe_C9PtmwGuhIuC(}BaKG)=i?FQ!c54z^qVlkH zFplqw9JVejz%N)Iwwj{5jXiAfQ|EDqtrU2A{9)^UTqj<1*a~2FnQ+){gdse&hK|?6 z;*@DT_#1uuG9Gwppz1s*>4M7hpex$zavm(gv^$drZE!FLcY5q*FlsIj987=L^PnEA zoyUWoXvz6JC`RMoz=I3XDmU`r-SaeU0T0HYZ!H;x13r0p2M-3J2QTG8ceLG|Jg7qF zTIL?Wuq(%cOf5rO^I$MK6|Ye3ftU#JBgvY54EA_<;K2ao*IVr3DAy1ij6@$dcxDsB>;6Yt<`_WrLF6OE|7KrwogxMgjHomTFue$d|C+6PH-1`yY*QzZEIFNbRTQ4I#18~iYI=qPSmqD!4m5Wb*7$mkf~p)Q}wKW(1oq9 z)VZFlUzqx}I@go69*(xYQRjNHdSGx^`_#Ffn%(imPU~Aea~tjTW({KMcY5ZVh#vK2 zJ)D8)em(OoB%+(wV#u1gFWU`h2CH1_Wx%y(V6A%*r(DiL9N_(P1{2*}p9<~d(VYF5 zBdqUr-$SUI`>tNTN7xnCwUqrhHVE7lzR1{3!FS32VG4np(oj+i?8$I!5V(JG|5J)C zAFV;_YQ2a*10^fuJ24l5D>6k=JX*>HOdbnEzr;mz9ibU&+n+}XKN|kb{GV1N&`uWYAM+`HVE954w90trLk^0Yv2%t&^+0KDSR=rR<)k7lCC`0x zdg$}Ih-BtDx4{y=;yX9b!khH)l6dqcJ1mNLbNWM=vhAn-va?$X$iYKd=%#jD0H(X<1jPbsX#u=VPP5Ad)YJk` zGy-TVAWIAMWRCU%f?8k)b95At>9$VIJfj0D9^wm-?QGRLZ)5GSEAkw+8(XJ$p4A$Q zN8md)Z(k8W>rChhFhBrW=NIM}EC8*uxe37e0?<1AUXVRP09xk*=D1J*TIXYe(E`vq ze-n%ofY#~V24I2!v`%6Oz$5`^ox5uSOc8+ASw%2a09xm9g6RU#I%^4L3P`q2_dH`1 zDjv#Y>-1EuQ%rNN%5&ImY@NAz*7;b`07 zZWMsl`G{bF0JP3$1PcYAb-pH8Bmk}RJ;6-^&^kX7+$;dCbBy2?0cf4gSZ?iG1)z0y za;V)V0IjowITi~*>wHLXyMSctT$5*9gNlcqtAn)b^0GPVLhG<6weQGt*lui{6?s-G zY`Oxg**f=1^P+Wz5Udn{*7=e$_X$AjJV9{30JKhL>^JNO1fX?r|4Xx12|(-E4FDb# zfYw=uWx{?)09xl>YOEH3)|p4}hyb)sP0alEV*=1RFJlK~KOq3EbBLy|5rEb?(gWaW z0hwB0DZ#S>YG{G^1nUH3V5Z@KeqKO83vkV}*9%BT=OB1NfL{yjCU{W*wm6>?yd=QU z0^bsB5MaYnf{g+!EpU`zlK@i-v||%)766}N%3PLb41v!=^E^mfuDbm;Y&h&!@*KLH zj(t7P;xp!fANqs8DFSfpg#>R2fMd@q1bABj9P8kU!+u8q96O{4V21!WHl5&I0dVYm zI^{h9aBOXY_XWVQx3&QIKmZ(@g*}nIQve*xuN2t31i-O1vF){Y3xH!U2?Km00FLE* zp6xvX;MgY}fV~3X*d+vC2!LbHs{r^)036$e;A;VJY%hXu1i-Na3HAwqV}}!bD*%oi zP4JxnIJSylzW_M)QiAUVz_I)g*gha2>DaA#Mho~XbdvM-Ys#^C4G}q*=g{SJ?9X|Y zfw?eHOg|nI0XX&{Y#!`i1i-Ol+X5UH0LNa11;hST037=qH0|F6z_FYb?B4~zu{UCs zw*L?S$5s(k3xH$Su#^)5;Mmm!e+htNXEp`+TL2u}6qncbDFJXS7HvE!8Bx0pIJOS1 zN^GwHIQH>j0EPfK_HKey0dTCz?qdmnV*>=X064Z5fg=Ep#Y=gyg%JS99`^$H1;DWv zb1_L50LR98N-Vx- z)fWKQZy{(P0ImtmGw%>}^qv)Q#<3V`eV zTtx~6!1aG|_D%?Z>mNex?P39N{XGPw0yw7Q0IdaZOcS&bz%fnGRshE|K|28)(*)-U z;Fu<8FMwm3pj-gQG(iUeaQ!;mj2N*2?j=hGp9V-Bi9ZWD@037>dM}Uh2z_FJy#{>az>`a0x0dVX_o-$DY9J`fZ zk^ngN7B2o53xH!+QDd?II5rXin4*AkY}bhK1$-77orSdS%CR@FB`=LQbU7V+MZ~%e zcZ~!5+Nyn}D8jKDaH@Tk062CM=0JP4066wgD!?@Y;MmJz0M`kCV<&U7Fh>9!JCcjt z^#b77U%4dA69C5!2m;(70FGTujRgYW*p!|Civ+;2-*^CS768ZIO}E`D0FIqbuvh>b z+ocu25&>}R22Ny41;DWrx&bT`0LNZJaF+l$_Hu&d0^r!$1a}L7W9Jd95CF&CL~xG) zICcray#nCamYiKz3NYOPdRfGH7%mDe=1yyd@?)6O<^2(d9;P23jaXgLeFHz>9Q$z* zfFBv-Zjl2+fRRH{mhjKJ~s{r`1 znBX-5@Z)06Ew2lJAMYY~Lje4EAHkaf;Kyd12;UL_KPCv?763o;JD&DC0^rA&2zCg7 zA73SSS3uH_4@Qj1a8YPHYq47S@yYIpydQDsVft}*#Nsz#()r7X_9r5cuchN{EA}20 z_rl6+aPQULtAG!e>X^!RMvMQsk>e4E6{6XHMy%Ix8$Iv|N9su>V4!pIi>LPAqKMA3utN!RAc>I%f{2PoDxF^u=E|)(pvkzBsBjfF%HZ@$!}cxU=&X z%=78!iyz^@c0>bR?+aR*rhtKN^J5EubU6jRWD1ugEIUaJ++yzA5r$<5NX3=TVC1Nw z0PZpeI(7!glpNTrt!)jEEx?2AE~nHSIR!?cWBeX54xsTurIkplRxOMqY~G>{+ny~P zi&|at(J{IXz@4=^A^<1yCspivQUrcb%HYPUz5tY2hoFG~T?X{5x_k50S8K40J>*3b0h>{9{Y$niUeRD ztIHh40?<`_+~=1FKv#K^jaMoFU1bkJnE=dV{8<{ibu{linCHXCE`eGc+2<*s!_B)n zv9*^|FvE1_T-ZSX#?3KQ$nGQn<0geOT^9jq@H@v|w`kZc1s^U18nf6QQVN=UO?`l# z0?_1XZ2@`-z-I{kIzgkih{9YndDE!zH3|~CXqE_|w|zPQ;7S4LZC?;vB>=r`AHmfEQ1u@OW(z=X zyPl%g2taRpjT6(g3gEj*fqw|DQ-Gc8FfN|#xpE3-nKWw56M*b+>a?h_9!7`w3nTV) zRkNxxL~e*WtTStNOVrxQn*E3U<~Ak3T0>xA)cB18ZrV*s!0eBVi=z&uDR5WRs(~w? z0KfNc-+i_~j(tbeC`MYyO}jIi!;cL@FQH_6Mbu%6R*MBx;K=>l#Gv4+s5ORy`4=GH zLuU*6?3Gbt0R`Q(`;|pYIkB&fI+UTnlTm9m1;QM~Pn|39Xw-O{0&d#lN}%U(WPCd6 zP?`cSM6LZ4cnE*&m(CSf8#OG<`5`y$IVEswBV^nVbtp}NEm5l;G6jC8tGAsi@N(4X zK>;`I6(z8#5E);KI+Uisj;M7J1(xHF{oc6(Z$yooDd48Pr38K-fsF4*9ZFN+{12zzAH=1vf?lcpE<^@iu~ka#jjwa4T|!OZWPGkG*ptG&4nz)pPsPK%XcVEfr@-<91a8T z@CvS*vH%}+P@qG;v4{dw8zZfgvfw|w8tRenP?`b*^Q}D;*iA1CRsvp3#-DKk7^*-D zE-v;m$1ur(CHGtA7$G@Q+%o&*8-KG*ol{>wRp##;Fc;)Iw1#Dl%eUH~#R7F`%SB3n zpU&_Lx^|TSY$A7YMV_QU8hSmdRhe&8;_T4(Bat>n6|s&|lk*)G&LS?)w`#(3f%98| zUm=PpqLScB0a%5q2(A`@icclDMgUf!Sp?S!z!;cAFjoM^Kt5-`c>=KKxs5q)5P)Ur zLgrW?05x079E${CjY7?)<{PbHbm%$G(wC{44Jk$BmVAeGX3g%*x7M&`Z(|tQcZmRM zHig4uxd7DcHRf0$0A)^Kj(Y^arAN6ot`vZMR>O3F`vs)BRxQpqcG9YwM<8v9vg&y{ zW>vmJdo}+a+mmMyxg7jfto6oP?;h0s3O?_Yy?64!T@V#g%-GklOrzSwY0BpYYR{#_!pd(vGhMgTV zhT`l{I%j~~ST>(P2tDjYq;||y>W5n-H^VLa z0W?3W$QG!K-BNO}NZqa13H4&E-7 zw+`5&qc4TsUA+M8TkCV%(_R23kTzj}asjy3UCJKYK>#lAJ{=6uNdR`TgSf(V7J$2S zDct&W5rCQd)+=A0lEpm_1F zk6jWo4x-|r;WVi%mcxpN?iz|n@0i1OW9tlwS^Juybqzs$G*y9ACb*B3O#tT5}oWx+YCkRNk&VZPaf;lnvnfxlRCDXH!>z zIRel+{C2y2y?|uvOo%1 zj=Kb4J?TCIV7UOSC&yUTy9Mz6Bf$y*xaX5<0Nf)0S7Vt3_X@y0AO0Apy;1<~KQ<(| zPXO)?+|CWr{Q@x4+*b+kfB^KCMjX(q1faLv)Cu500q89caPRVv0Q8n)97_)iKySH^ z)qg|)dP@f^WcH&1&|8+E7u$~sKyRtyT=cjA^p^JQq)!MyZ@G%#Ndf3Bd*Ew(jR5qP zEG{%p3&3rk`-cELD*!zM8-;~2V=Q_`=s8yWrdV=&oY@wUwK0bsi{0m?nDrpL&nY(7 zMiIb9q2@4vO#;w;K4PcdEC7QUMLZuf-eeI~9EmTeBDQr#WJ}Cp;apzcidn~5#4N1S z_B*n8plPn{0r0MX6n8b*9y4-q2@rDA-cYMa59|o+4`L3>;*78-W+jj*a13j^y;n^s zR;oMU?v5G5D4=6Sv_DZ(N-;JB_7^dS(yaCOG3y2j%&7!Fpz4H&Q`7P0Is1^*5w6UL z+52L~lN7wE2J(Iv%i;5Tq2cU1KgArTXth`%uQ=T$HI)VY8ngZY2uy2$e82yzfD>m5 z2)xVH?JohSLf#zRJ{mJ3SSUkRw?X1Bv7Ba%qk zri32hoL;VHRgvD1%+yiOx{T2qW5KszVP`$Uscn@WVHbT^&)U%fiQ8g9&Sa145%#LB zde+CJJCpWr)3d%|^uwg!YkJnMT8Qq71uJ0x>w1L!M#HnR%=A?rqHqrwH9N}+@07iI2g0}=j7Seg~2QU>%r{v0d@+&^go~ALjjonZz0$v z0Mq}S1Rn{&^uLl|w*XB4&k}qh0F(Pm1fL4P_^$wX`X_=T0^sT61V0Oa zr~f24Dgavnoy+(!0dT!Z@QVPrK0t6>09;>-;8y`~eT3jQ0dV~S7;gU|0Ipw5P%Qwi zUrumB09?O>ThTuS!1aqf04D`tkzPXZw*cJf{umc(_9+2y3V({;)*7h61*eSX4#Xn> zMWV@nsBb)k)(mywcKM)c@=F>a;%(s28EkU9fz_oon*192EKLN^)E9uE^AILPyMX{Sc{lEy8VSHy`ieOk3&2?VfuM;1 zjHM$4O$A^q{Z7zK0LBvU64=cJz-=jM04)T-ZRrFp1z;@w;0Guako03p17i|g6l&W8 zX=a1uocJN;LOb5Tp@-?m)(xxyZQ#d_7lOAF0d)Iku`RLN3qbn~%L3>i0PVNGCO~Ha zsQXU@T?C-+zY$FdoS=sQ)V-LXrvTJFo(<4T z06z+3FYhfN*%-wQj4M#jP$lP)Qq>s$v_+&(1BcC|`Lpb2>RYRjDa?gP3v;dTg*ma9 zVfOX3Fk31^bNcW)tzQE#1+ghxRcP(SQ99m^g-;I()g?acxRaa1hXv3MkG-Ei4Gl z;^==>nYpJoB0CEmR)D+iPYbQ{ktuyJ1@;yuZ|d-OiEzv2qe6pEF@!A679STTZ`pj` z7m+Ut9ZFMRf1$Mkhk+0~{0}04%Pa_dQ)s+Of$1HP_N@{)JOq)0g$||JA&wSWCn-?a z6Z{wDe||JMGYs&nbO=lze}@2mSAg$3K@a(<&?vw}6ncie_=xHuAMlpf$wG&P(?)OH zYKKgL&E?=m{PdkG+IXta7(;=pIJfKZWF_ZD5lM|Zl%_y>+**voqy-sDz`*eOl50k$ z0x*G!cHCG`#TLAmlcp5MaFZB}J1mQe;kdPvir#_Xk#kMTjvK#GU4FAEE?` zIDw9gJCtVM8ymNVP@tkC`1p8oGIH2?J@%-$aWw@l;5nn?$+@SXDI!&Ihtjm*(zvyQ z0#6PApB4|T0@is?G|n3hmkYqmye|*n3IUji+rtKXmVo4lyEtzA47pHyT(a0x;YfZZ*Sz3j9$6e7>qRpA+8R3*bfpm{QmD0azgIg0s;(uZ+$S z4$GqAy>aV9Dz4`kzE1?uP>s1fJRl%x=e_4t_vpkmY;)XU;k0pk+FuNYo zwkaF$V0V8j?ogTn|A||Tv1tlCM&S?72n4Fwjvpz&2anz~0d`9cxaxg6|5E{wgY(~w z8+{=cTFXh}eO0E-nPpGhp*1XXU)-9_GKceO_d6xP{xy_Fe1ERumvQ4kD*nUn{k2l; zjw#0eA?~m&DjtbjuTXIv{@6!FAnB^ZapPMG6qO_GCnYc@7m;7$4y7q@B5wUd0lrMd z{_9+U-{MA{&JdV!KGObB0(?rs{yXkangS^at35IWp5<&{CXy=vT8xe2Nf_fOFp5p; zOC(o--`Sb{35U`Y$VymqDDW;jQLS?YG7`ok6gcHUTBZ`XpBcjmhtd?No3MDtEAU`f z@cK#stx5}G3F8L})Zn#dZ6#1L9Fc|zhtd>imGFDeF$2q6gU1v3_X6umpjpCdfV2>Q z9Ncb^6c3H!DMi(832Oxo1B20f>>lUVt8>D56=|WnFyibARj>7&czPuqN>N~7!rDuL+vxMb z=L+;q7^f%@^&_pn64+S>k)a8P(iFHbVTIwXz-xoSE6)`eo-oRh7COd;8L0$Luwlj| z97GjJiPt8xlJ+8JPkXSAs7(tB3;n^yagQFoyx$a&8gx64pc(k#+&nZcs&()I;Rf zM1X~}sxuPCwK$BjDp3~3a+f8n%{UAcq#*P1vs$kQt_$oHXSH4#2j4yCw%(G2u@7g5 zW^(W?Rjt=M2a$Ud4hv%u4<)SpZYbhQE}0LXRYXm8g-6dSB7@`pv2%;KKVfvn*`W<^ zx4lXg@h7c)JmIi#7V&Jtx}HUx$6mPZtRkACuJ-e174Z;;lfC}jBGx2~$5=#VDbk)+ zMLg3GkrxsU3+ENVmW1^^i+CQpQhQtC%yr5u1g{Ceb;?@=+XY0>_CEXNgkht9hQ8v~ z;FU!3qN4-*+#3mpg|ikPBrI;S0yQ~ac8bwhW%Ibo?h=4Y$(}KQ-2!kn+`A)TOkolH zDS!JtRg3>X+Wt7UFl1mL!r zpCCm5Zkx4Zd!!1$g=IGaQvhxZ4J5Dx;KtB}1hxR&7@A1n2*8bv83btpaAV^-f^-4c zK0VBZI70yLbbQB2FH->SbQ~eb5`ez5g{RaMfWGrBLAC(&jQoRiG1A6FBwFOq!|Vw4i>wj!EdJ)?G!!QVX! zxtZ%0CHDpwa9i56$YEJjj2Bresp#c}P>~YAvl#4JEsBh76iDUV*GdVD>)~^HrI*^iX2K)V0@AF8U^@%GJAp&;FZy417PC0bsAk{9H3%HF4JR`;_+-mE-rFd z7WeBj(9GD=1}^UkKC|e|!yz}70bD5nJ+OEbz|{h9SN~f!?6m@5#ByFV%oTtRx55uF zPXH#X&TRS{1z@uJn#$oC^QL=uksia9L6ED)Q

    4>u+D6&P<8L!0CO z6B;10tH@zlRQ#;Sx&oP!HhwMwV&m86+W2viv66}_*)cvyMon$Vu$PXV~|-;Lle0qN)h_^7@7|jF@s|zqu8N&G$OayKjO3z;o{g^z&<`O`ZN{u1VmlMn#I-} zDpqo?%ubdTnuB@Njur=478UCi`(Hh+*gynCv7rF$4BUD)5&$dFas|cKcP!#$B~5#qZ)@%S{`L#EH_?ky^47(*_=hv6jE-n04cXb0NU5}X_)}=X=?$P zL;KUoZ3JKr?Z|n%tpI$y6XH&^odDb>sY7s{0DPi0mjkxF0PF;cnWJ0))>~AqMX~W6 zY7u&Xn}Sx#X_Lwk=~(Qr(yVIFV(Uiibpum43-%TPRP|j>F53>JXCbsND@0T@@y2!;v3xLQdtLIB3qYJv*{pgSJpOfpIU#?{Sf0HXz9^R<*< ztN;wOdkMx1z(89~FhKw|Uuy^^3c%*;d4h`tVDt4d!4v`T<932e1;CGdZ>c>^0Q~q7 z!E^!eWL$JYpE3BYQ(gWzfbSR8i|TqA(n3OqetY^;HcLNDWw-A(!NFJ7R{ zDR$^#uHlP{Ee8v0z|Yn7=HfGJc%&5IRspcPF>@>t05e+<+#vvFx<3YWXL0f|Nc1Hx zw>K0UEs-zu5i>6+PA<1zcI9Qo4$b2%zp~i61nB{6De*KC;|7*p>97?Z0x2$ z5jL&%V@lwe0z{rJb|_7O^~Kf%?CAm*Z~=T#EPyZGXbSL>02uvSbASy3;GE}M0&En3 zolDC&z$O9Mxg6vq{jvb;Tv`S_N5Rlxp?7Vvpv+C|Xw?Ex@e+2l69V9{pV`s=6aa^n zvZMVa01itp1vn`HCSipATx|SCyPI)NJ*Mow6CKR{yVzlkXt%G#S~whbC(6K6O3qxy z)ulU91;Fl|beJgsb|=^oECH}P%8q6WfZYw+12_U;cb9U2Gy$-?5j&b+K+9eqaWJjw}ViZC@)Q(03l@U9+5sQ>KG>=BqEwSd(h%|Pz`XT@$vf0rZ2!Igroa_$z^i92%v}~NVg{lKm?6Fs>FDgiZwa5 zMk~ctT$-y&9F|4JOG~T+RLrAE)0BX^m2z>3k%sOW>WofoPf-HJoP(y9IFzQqRVCJB zWC~QXm(3OnVA91gfNKSy)*IME<_dtf{G6=j3xKzNL{r!c1te=Rv&2|JBYw?A+AL+n z4if#F7&0X&UiE9q^?hkm@$WttG}T3S@_nwpa-~$C8$nIFzQq{UuhxC5x z<})SM7?$~HAMmwOMDlX{$r57$1!h(t?I|U27pLy$N*qd4;N=qkdI~ft27k3A`2m#< z8$XALy+r_aJ?ITDl~|uqaT5O68ip;TG|} zC?YcyUoWwmAaiIOC)_ucV($PVACv@G7Bjt2Vw59Ol!ivB&0_YH_^047SagXq4J4=GPLd3Nv{6fbMvf>i6WC?$ZaK(ocT~ zKxeYMnf7Q%dQXb=kEkRe;!J3J{xY1;i#tGANtUB%ZWMD>Vwnz@{oLBA(LZ zn%j((^OribmNwNYwb~(5U>)v5*f}DQ9FH|hjWHDXjsig?@IDvkP^m*{3KW!D*HYkE z0eGF#&?;ayG+QN7YOJO}CL1EZv=-As%eo>`uhgM51)7#xTPQFP{myQFt_2NCjr|lD z$4=B(Suhy$nccF~p)>_rm-+{dg}|O(;B8CQ;KIDNio>;?05oe8RN8JY0E6W+?h?uc zz||G}?V1h(_|p{lshN%vM|r4KajA7B$_s6%#L1;egF|!MAkwKcKyztSk5d1mH0nHN z>Lmg&YRo`@-U5l&ptiy4Y8g~LG8 zY-Ap$8c!_>1L6O1P<7J=tHwLOH8PGUbtpxFvG6}K1-|fuk3YBdN5TITSU{6UD}lGU zHcWv3kwSrK@IM7UV8@z%uD}%dp8{pwkanpO7Zm&5-`U^e_uffL;EUwdv9X2Jgy zIK}nnDkbp8AVlWC|4Lv{silpFz>)^wH=k?44W&jsq=l9GOKtEEl`B5O(=mPN(qO0D0ico#mRv)79vy3Ye_{uczGPY zb&Yc5nD^G5@ZTI$!*MQqL>`Gn@f$66sSNe*sm&q zLtIZ^FLfwQf%i+TMHDzv1N=W{1OgQVI|Zb;CcRy1JVV7I?rL@@#Utg2>?(Cw78UoF zT05vXpELXyB9JuclTzbn3Jgs_+8!lv0W1GisY7WB{7`E3odAK8oQ4mH09xrW_L;*1 zFrofZ3Gkx;Y#+9BD)>nNe0P#-_+**8FYRrIs=sdRBer3eZY^0w{9hyfYelN9l z(}+A8Q7r=S-7lz#{igsJQBf1%F99&(+U5W!1;B`roL2r8kTl|#QsV@Tm|TdoUzHIf zIeVTeb!Z-qNGY?1Rl$fSEO4{z%vy7drdtBgG-e|JM*xiI-3lO00F2m7clZS)jqsEi z*FrzEhqIKgEV;O>LYf^Yb7&ros8wcdrV(Fu1kVuxw8Rx`{agVs;?gKUNB{-{hF)fw zv5!Sm^6V^CgvE6#ugqcLETT@CHDDr&*v>hso(Q0bT?F+7pop*7R~iUF>mSGiXea;` zKgzDvNB}C{yCFbh0m+Kzml;=}z|gfNNGniQm2g66TISGRS`{y|4$`XUE$|`{fK@jQ z1t=B(t5&dx5&^L45)RW+0kG<^I6#>ISaqCD-daG?supF2e-f-3fT-O{S@kM=Q`<6! z_R^|OWmZpQ3jD^otcwW1s>2NcDg?l)$2l0f3P`%6eVH+pMXcrSu7fJ#fo_O&FLPKp zi|AKo?PC!eS@8iPfFf>Z#Rm#N5gy765`c>T%{|^=0jT&htoRTCsQ90(_)r1KiuWor zQZ9y7JGeshQC22V}E>^ zLum?JT4s%;WnyIDQcNbdCE|c#W-cuNSz{dGuek~v^`4b3_6$W1fN)Pfy7xv?Y!F!M+ zBh1JA^TK?rJ{IOv>ve;C)rI|4Vdg62t{3Km==Fnq!G(P|$r^VLnRTDm(yx3xoW?(rz6OQZpWOzmC`@?%Ia6NiU@L9&*PUgQo%;%x*2*$arf0}STwlvHKnC=YoaiC?v z*O~jbWbV7de8T7MU{~gj6}h&q4D)G``@?*~!+w?!O81 z^Y(pVen$Rnn4fEZ7u>*ezAFlLyiC*fNBGI~R&Q3n7~rWQxA|W8M)(o!+ujI2lzh({ z;U|ncy;+sa)44dv2eNj1Bm6M#8*kP(h}qW{2b&?>@6EcAv)jC4x7|*9BmAW2A8&-8 zwP?NwKM&D;5q_%S@kRI{f!7z|J$Iik!n@vvFTxwqDZU8r>!$i5yiIEQBD_&)`69e` zX!|0(73cUOyt9?&%UZ$$FDP*x;rB&&Gb-H|aql4cBD@cj;fwH2ObuVw2du#IWY$by zgtu3MzO2<0c)Y~5ILjB|4Uk&CNRvu@ZPypsk08gFb%JLeNuHVOi|~p&gqN8SUxXKnQD20YeEGgCUjgzImIjZY@ngOSuY$@UfS`jft49eEFDP{_ z=m>#v_(HQUYcT1=Qn#0M@nv0uI@ptvnJRo)RZP9OG&mAo?1s{C&K#76V6HD~Iuox? z=DpsR^+pDw^GbuW;iCDz2rnXT_htQ94|H+T>?OVkuMF<+W!=S7?@yMx)R*-KPko>? zxCou|PG5w(|Fymdx9sbD5pJuW^JP8AQ{GGpJ@1Qfue{!u)v-S4?j(J|7vX;QMPHWb z1^p&TU-Ct`iQV9fa2vVN7vV;3lP|)p)XTmIw>z7C5$-Qu@kO|xzv_!{(cR*UaFyHY z%X+#LY7@%bCfer9YEu)@sxr47U-M>vV*$ES9s=pk6bd;ibKTcndd}a~g za&Qn&+liS%*Ss|_?c!yhxk!j@?}6jA{ux&yQsAwF$el&;S}rqQ^B*US@xS;K>D5%cYw^%i^JI1wXK7~A%S(CRMH19}13b@@{3b~k#wIVHT zX~qYL6kHrZWLY*%(h8nq3*D9dGLC%(dGKi3y{b{Y&7hXH(z}8JaR``c4`g^Q$2t8{ zk?>%U=V%4#Wr#c!WTW~t?;cb!ZMAnV&sl{Y8B2RK<9?p=C90VAcqSWEOP2F=PO{K9 z1|a2`9Jks9eb{N9byLy`8ncO>bH8DoQP9Uhpdrc8E)oPxC@kn*w{$wvXm{7qJI!_NL=FWfT6yb`@bS zmbNA1>Y1>&8j-YjG9SUQR&Z%CBD*p-A>u1|u@)kqyAiYC+XN!}-AGzN72KcpUpJCb z&>WL_+V5^8D>yVC5wD)P8wz+kEBa4bhMsvGvAke2jHa}Zo|$t6YzR8=WLjN4vmIh} zgO^)~wbC<3Bi1n39Nj3bjqYkT)f#k1Q!Iu={bl^K3V%?wC9EZBZQq-$**)$dtK{Zq z72NztUn7uKB}G1j22!?43N1X7QeP$Sm1IB6N+t(!gcI4>Qb=q2PDrN0)0s+>nb@IH zNNf9|`0Lum3MQ54)B4w;7WJRS5%P3GlGAD^s@_)jzRPnbfTZ##*^)D$zeW0sAm+?G z2FvF;Srh`%Ar7QfSBdr-j<2e@>wsAC^ch zbyJJe2_4e^WWrBS)y!I$hcKG2#+dSV@$!rmrl$Ui#Nh8GbTsf zd=DMdV-5?@ii%2L^X?j)ndjAp+s#cu6lp#NOXpZO55`%#l@UhZv9^~Z@LA7cENG^6 z8+w(NVcl1ZAZDdutD==#o8t)P*zKDkfMs?+_W&C0SPWK>& z@29y3<#^1)J(z=$@c>HpFY`L6Ld=9=9{=4L=9L%+AvW7RHF>NRbj(5I-kPjBUJ0pt zF8AWp*HIh)O7Ax~wV}`duw`7OX^qm*QT>nAdKqW=@SEI?icxX@6Un%qt2J7K2K7Iw z;yGI5OGl5_{A*M^TWi!F4d{O=8OP6WH)>8Zo>A$UTBAoR5r0;tR$B9B;~Lk0z+27J zc;%%^JDfh8r|m`u(@b75=w>L&)4ncsOS=vU{-fR&$dr2H86%IU-@wzVAgY=3@fU{i zxkUdT-iw&kccwA^OyA6`8(J~z)iIW^9Lv6LHp5`TOCFn|W&Eb@U4mTA`kJRLbM$oo zY@9Mc=ZRDBS2q{pug6@Czh3iI{KY%3@z*ea#orV&;K9k7lf#ZvQ}@0@!4?Bg3+CwQ z6%_mv1#0G=0tz<5@WFi493qr_^u96aTmGe<^}j$!(0HvGEEQm8$oj`rpqkzh@WrY{-*=Bi{`=r_KN1?X!jg* zJeo1rd>EF5%#-L}VKWZb<(Y3{{*0I{&?ZqcT*!BDKLMx2H0L~2z~5Q-4rDc#ql2qz zcGc5|vzkj$1%s*1kc<)-+a4q&N{tNYj#jZs|Q8oW4 zy?~n)J@_P?;jh#SIJi8)r}7XRtru|2c!L%i)jvir;HdQlH;zDTtX{x+nZegXh>c6e z(t^v;9{%ykSVr)rFk%-aV_Cs+ILkjlFJO1i365gxROtom!@0rV(GC3*^#XRlP;d(8 zoJo2Chh8{15}m?-aWa;tIjJ;lvhF>B`lYa1%|mUmCGuaYXMBDgD*3H}^l5snz?E$F zLyTRPjCq11FxLIk^;%r_e8KB!?2Kg04Eo}TU7n1k1@B^PW-^u$yn+pVMKYEZd>TE+ ze>L_=P{|2SU&k1?yuo@4q1#D+p#*BDO$xw~Doc@3S5Yld(F% zFR*d+FVfweW8L678?l>`v3kLi^$@#RugmH+46ba4*e!ZpPSQ=`^v}=)P8)dMf2;2O z3Xv8IFy8#j^w12h_r5IYzqFcKCdr>rj6T#$nbezLV{&BZ!_ucycxz1xcSYC6#^a^-2rlprLPEu@0#zjPQ@Xa{V0KQ{-XYdAOaZ_tP;Kw)znrOD{P)+voqzh7Q~+ z2vI#RnGNF_YOl=2kD^VyY?`JQq`K{iA@2Swx(73`-XJy19L3%4Nm8#?3V$MR%?p7` z7%3f&w6cd)h7`O59<5~SStUGZ{USJ;NMmjJuXx)E%vU(@Xj7?FH`SO2r8XY`W58)> zGh}-HZcH?8rrVjRL28%Bnd$ZaL*1Le$5CACqdn8=!M3mfOWtiPFBlAHmuz_fJe#Dk zN78s^Bw@BemStODOG1*3ApsKhBqV`A$Z|%}gz4@&O`W%8j4Yz@zo8FI*C*k`U z+}Uh7pO_6J652oHNuy&C+{5t-b@M)E`iI#3&!PMc^i+29%?Oij=8bgoI^=Sy%_->S zH!!C^$Gl%4Cn@o4q}jrBp>BSFiJpn2PqhaXcaJ+={YH$;E@NeLq$YU|@A8am3 zuLEh?m@XcW9tlvU+~cwIsc4;$-!>%bVZ!xuZ$^!A6LE6P?c1^0SteSF;1UvCD2YfV zB(RvXkBPn)n|%)xkx~vJ!4%vE#t5bG->$q0PAG*>&2nCVI7=xXLe%@<(6GqxS;=-I0SonEpEzJAT-9n40iV}Gpcv#5Q?R41bIF|jRlylX2w zg_zhDobFEaQsl4R+(_z1`_x~(B%kV{4I=V4FZnns+O>HjJb(9+Ox80wHtt0J;U(GN zj`{*(sHQG_zlPiRIJltDrGx%;BERxxZ~ha48mch;;WqyQo)O%X==nZ8H{<4dxa`<# z%#*GI>B5PA)Jvl}n_q^|cOd$0On)srpTW&1={W??PjT}faA$u99!`mfvyTrS_BQ_k zA%6y3yBon{x=vcKVZ;PbqH$r zWc_k7zhlr17b9r9Ckn5V@mR6jnQDgyZR_~eT6izjhd|Ijx&|#?!``?TE#Bd`_};2b zL5uIL8kH6w#=;u;fN7VLK7c`s+*T!X*1gPs^0ulSeA4OeC3C?>gZo-P?uAuZ$@K>q z&B(P?S!qr0{sH(_RaMhW#;Xc0a#!DnI|09S{opT2@B=T!1QIs*TepGsv~Od;{~gY( zJ->Hlv40i;e}(HGotnae>n@eNx5$wF&6Ocrg~?VAw?#TTQYD?e0RbIw{ge%=wWV=R zZ%BHWBm7;>JWM77p7GhX%@wcpn zKSTUa;G~6&#d?fi+rmef7hCvOr1=Y+wD3d>c@3Pja2t|GxaTSqU|ZNHq5PG0+ZJMt zLJ9mWYvCEljLVR;kQ3}2I9$@gi{zHSYvCf#y55g&K~j$4Ad(f~q=maA9e>MOcq!t? z;G~6&jXM0bEqo{QVhdk@G*`n(3tx$w+u@{zGe{nB_!}O>!xGBhvKCUfjXL}-YvH?* z+5K?R!iR7}gAp#NIjVq*ztY00s@c-I?;y#y;3Unhl7_!!t@{n)e+4J4V{FvnuWj8+ zFz=*w9%|#lN$Zy2W)YmU?oCJ@arhf<-J2zpzh$j^I|8B(fAM%gp&jtG!Aa}3<0ivs zTz!u(Lb6W>?10lJa#!2S9B1n*E|#b*WCy#D{vx-Ey7S9GQ8tjJpBTe+Shs}B3pwZ*?`Dhx3Nfhpw&&X$k!n8D_P{9 z(4mnwH%Su-iaZIzL8RSH(l8Xs7eqkma7A>96r8?QCn0!Vkh^KnLKr4Y?(^JE=Ke|K z{88qfj3Irk+exb$a(@|RxjMI#JT#Iw+;4$t!G9q658#B0Epv_Fz2)X=BwXPxW(jj< zV>sZj0zAx?zBP-ur=mWu6^Y=kJN&vl742YMl6Yh@oN3Eb(QP#6M|POPe;pOpdjsOH zf|J7k7}dgMt^2d_eHyX+xA#upZ_wt*=PQe?2Hlx1_6^tB^|qjdIw|2ZehIflTUf#;@Z^VB!f}fweU2M1wuIYF z3BN}C&*7ZDPcf5Af=qiP(|6uxd+U;D6Ej_bab60SpV=bmv)uBrneI24rVzgsZi`4K zGp62q5kO1f7H&004w}FhAmB>4jZ_2{uta<-9lzH^R}`;9&}RPJj|BI@ZD3UAtqAFS z9ey@OutK%UGhg8|h1jW^YZ3Gil0L}f4DGB(NM{3oHsMFEzB|_;`O^`f9v?t(1B8E5b#=&~pVaOmBdurg7k#ZTk( z9a@Pp-Whb!COj0mYya)Gi{2R#68kQS{&%>oGN|v2^sqNhgzhp6&NTd8rs4ev$iPWM zKM>K0J9-YX{h0AxhuG)AojVVCfWJ6fLqz|-I8%+6nQHt60e^&(YTTjK*hm?k7kD79$ej^SRPvL-K$ehkI(^^Sj_`|u zGMkz1u50eF{c%yGk+UO-)aSq%L)gWpOd}ZXjfh~l53#%9w!D`s&c4VJlFDrecqs$_ z-iN?36ZjDXypMrA-x0aQ1U`#^Kf_7=FVp%veUDJc?Fy<#iiq6xIlp>c5s_y5Prx9+ znJ(!u)#LwSe;%CEx17sXV`VPYue6P9G`YMPiQnMo(rj}1cLaP@a+%H}mj#u%?C^70 z5IK`w^>-xxv!BZ%lS{*i5U}8!o%L&w%R~MY-3Q{2+(kRfd1f`0Jn~4|2X~&RP7n1_ zkC=gf67GDNcAuA7$A9Pi3b^%4UxZB!_KkBcGjt=~f1zHR*CY6Yh<`ua=5_Eqf}1bE zZD6uZNre0mzVE|ER$#I@Vip?9~ITfCja2uFp(+-3b;mg5o zx(J>taWh5FrSNvp(JuYe~~3tb+b3+{#|dfU01?gQS8 z!0X{I{0Ka(6uQk>_$u6g5&?YS;LULH>%kZp8?#g zFxR=9ut2M$50wQ4;+L3I4!D#@_W}N%aPH)e_I!g1X7% zs>Z4{n=99aR6!rY4anL#pH+Vx0X#r_GNUh|qRCH}jw7lw29I+Q)zKd!=(|k)XLvRs zWgFZ^+OfDyfP=v70oC-B;uZvL=Finga2RfL2A=of<}Gj=m~PV`LT1g!Q*fI`;3?r| zhyf^#`tWH;l>qg1{sbN=<;PM=4@=n|F6AyfbtjyZ@;Gij2e*Ogq?9!a&@MPBWgIvA z;BXD>LVnwBgsy;6$eL#mHmPBkgu<@Yu&YC1w`kZag0P`Q=pU{J!731GHVhs)<0_rH z8f5gjMKlw+G!I=&BS!RdXVJps41c2!u^(RGQlm66AKt{6U9>qxKiosMwTohJ^us%u zg)@9Hexmm*aB0OcPu$bVCq|yyjEJ`yjz4@ZXghlQ0+&`7lj`;jro^wGf|%YD+u5!#6>gq{ zbN14xx*IoS7MnWYS-uzy4-Qx4q{t~XwbgFT(wc#VCq-DP=o+WG`fLQDOBOh8&8F(j z)f=lb;7&LoATj7xeCLQEv9$unRYlyIv#YC-%A_Xaopl->UIw{uw%mA7a^xn4twGJ# zGx;7b;TXobwUO#-mbp^1laXLPtC)~atX_*@1dFr- zh4(4uM^0VLhhPR~ic{$~RXWDO$GK|tJH+#YTmT>kOe-?9N*PmUUQS}gp?3_mQkRic}c5U@S6s=js{T$c@ zL4_0O1IO=!WhFPhZ91BA*&Xd-Gij6mRg~zAsYb|s~Uti54>xqUt!Dx&MUt$tnhhS zrc52}lJj*W!eJK(QK1SKR)Z>;1)si%9z#GS9SJSOjK#&;0LcmRLpY5|u`66Y7VL1* zSOpq=Iy-f7J-TzWQA?L8h6PIK8`autt0k)hb)yEZ7EVF@{E471MEeT`M&-zX*s6k* z(JBU11TqJ6Kw%pYSr9IPt8y-T;Oe`_arb=Rha3Nbgy0;2!*;Mugj*Y3O1)Kx)O*s z5w3-+a(*Al-Oal@Oay*I7nW(~0ytzvcp+Ss^L+H7eZu$<9J;9TTn!g-iUdA{68Xf9 zCKSK^wF!47Mc(Ea5ktR85uubt7itVXR)Bz$D+3w8qC+VoRge{B?;dr*om?a>dP41* zgtxpUQD;BG7(R>bEgLXary>I;F3$h~des5ZenO|*7746ah_>L<%OvMNkdWjYpdEJy zPwcSi0yIzL?Gq7aFi4&cl9@YdhHK%_ON3M9Hpd4z5(p)*ayZ+w2vBxK;X|bf>^(y~ zWhvm92N!X65Nx6yKCuUhPm^SMLOa}X=~nelIV=dcICRhT99zpul|RR) zLY1EQE_v@DSGt0K^Bn6jdwlvOh48F-XRFqoN?SHgydaxsh4_2pT^Jb-|T zK(nX${PL7ll9GW(sRVYIUSTQ9>2Ex3{6Opy>amFI2 zqbGufhRY_4Ig_(ut0(Vf+F5W_&h&4byLo4-9!Nj~I8zDUEin-UE|BH5 zW0Cgy-{oLh#+;AR>&*Ipm+il}VxiHPgF2RX%29^w$V6|ZEa7PoQ{#mFwuEoy)9=~WV;Q_fF#Baq_4?koEf{{q_ga_av&Jcdfu4V9{9fSwu zwuoQ7SnUVku%VzKxHXNcm*8X7qY<(DB*nmfzyszMzjB$rYR3I0xTw>5H!%f=T3-nu z1H>(UD=y}X))U&{Ovmw#86X0`M_eQxWJXv5=Q=YH{x^9)gB^DV8Tdt7Lcr?*^7ub5 zGKO@H{KF!{T3qL{YwoT=7|Vjd%tGiS{3s=w9b%K%uLjb~MY=-s2qcB!<3vsM!22~0GLy3gvW*lJReT-X#4C6jIPoUPl}tdM?Z z;?Uq$NuM#pigc#q2MBy*o}Yhg^{g0kTj@)ahUJ^m$UU_*-kMq#38%qDo#{oy${dfc z$Pr2O;!=gaAaLp`M`C@;y9EIV`EMj*LX-6WFWF{MU(}T#JC%X<$CmIiRJDU(QozI> zTK(Kgv@xX zzM?v2t}sogLMC}JNM1y|TpZ9K!@(eh&vgwibDVLcoPwL>9GrDW1a-TczQb^!b;66w zBAZc>^>9IQM29Xu@oG3cOn4ISaf*`TN$Qcr8tD;DNwXrQ8wH*UP2zg?;Hl=xDw!GxViY|jf}{~ zHHV#*cQa^>NkLdIDGt?3inAmIgA7TW%O-pV4%s~fc-q`np+al|LfHaCV&_Wv@)LD_ z3^Z8`@wxBHbNKtJpT`16OTc;2hby|F)H+$3M^1DubdejkUMgK2fSvvQ6TS$Q}8pM+cL9CD>|*00f<_BAVQB0MWs zgt^GpG_%6gW4~;I!)*>wF$ikh|khRQ6w|ylnjOl%!|RyY|sP~m@k8wkz62J z;`=qH-wMFoP}f)D8mkVlXqynqUI+WiT@eu3u?B zbDS&u!L}6&huNBi!)z`lOXkE{v8^@--rFa`ePEvquoJfsJPBLjxSHng=G_Hwh#>5S zGZDNak41!KwI(89vw1`x<=TR7pBaKm2U~5_VfUWKk57>HFK45EYx{&=EbDrTYxj$c+ zVijB?90-3aAZ2dx8@gI?zZDK?`T(pUZf&`^MSxspC1d|S1549GqKZ+q0w?%?%+{2B(w z+b^k~5*DwM4ft52ep^$E&)0BLCohsRFN?-!q*mr_>ub|69UbG?<~8cFKu(4{oV{#X zrepo;;h5fD^Kirb8F#dJTTVFcSmm%jmFW;9S2(=g1_GJa(ekrN*k`t#wm)qgk@2%a z0pYYP(_S1~mQz$`!^2^dHV|m*WYb@au-$MZ(*1DuIvzKym+eQ=8vFNjxb<-Ms!X>C z5jI^T?ps4H+&^^)r(?dP7q;VUxUFy(z+DWt3vLR|(kX65mm>XM33np{^kO|(?pip` z50+);1#Zj22Eh&JC^T6qn`wBx817|ouYkJ)?)7kQg1ZOq-Ej8$8E#hL`LDuJ;iSj}5oTc+LfT zk>+e#J3e803x}<;4*@yW)}?SycM+VuIKIaU-x`YR!+joZ5biv<%Ija*o^U%^E@_)r zC6c~)k#>1mI%D7Psxk2YN&Y*6LoKfJx+<(Tk-y>~6*MnU8kQ+1(%9HEHQcmkda`MH zYNTnZw0CmGY1%h&V6b79rk~1?nfc2kpt6X(@m+-Lt`VOP5E?Rx)3iM zZP5QU6#g%6E@*IOczk4Z8fzt|Y~u(gGv-nWhmafhQK+P6Wa7YqiE-nX{wRS);e|F^ z+C92w_~8DT(##c;qtgfja{!_59vh#52j)(&1bx1Q8H+G17|au7TpB$*GCDakHZjfz zQPv11RB7ZuTN}K{JHMfelRnV{FOJ)Qwq`~TnER>H%-Dg^Da{h=j;a1We4qo`3qChZ zR`0lXMkAhA>qTNGxz+Wa7hCSN$0FY9M%=DKXl*nC9u_3O|9_VJq5oO(@8fHs5wFf& z(C963ry9M8yO4EqchxVht*xE!RmW<#pNxQ}THK=Ev1a$JF}(cu?JFX+-YKz@Rw8Jn z*A%PsPB~Lr+6EI^XhTC(%T?Gf-H5R*MI=jaCWTO zJ2f`n>umAXGN;+G)$sFigI;X4`&QQOTc&nQ;a<4K^A>pXVm03CHOTCgiYniRS4a%C zAkv*(@2y9Mk+ohL1=M@(;xVl>%35UD~{+?Q83BE?Gg`h)eP;+5`ppxaUJt(4Mc zZ^J{M+7Mz3L; zcLo5VXYtWXm}@O-5p$oM6G1i3a9@3}v0mzhfT&kCm0ms<>1!7t^;~cHDad6dAG{K+ zJkg!K#hbMp<8hi-gMty);w?m>pnPDh=ec$D-a_|MHfg2CAShOk-e)=){ng$Y+(xp< z?!3lIVtP#E%@gfLx-S1x67{iz%FVLS0vUmb zZ;6^({MppPj^PngD;vsR@R`~r9KXvWUIQn_tQN0kIfti?*`S+h+`F$rFS$R6a@0ByvOMO# z{wh-KQuoIaxY|3({R-#DeD8dH=0TA0@-@tAc?%wXGK%6`B)8j{n|HqZ(K)Pr6T+6b zpO$G+TU&>xQJ0T_2wjYp`?-TGW-$VgoBQ^|tifv3cD}cqb!^6Mt)b4jc3pUevkq@_ zU~<+OCbUZX!;)f4tu)Q6m1$Y$&8>^MdmIuHnU&d z`H{L~L$a5I*h>&dJC0fu=RYE=tTW&f?#o>^7vEsEi*ReoLPqHDX5aPt;ac%`?Q zZS-PG{Ej3$2EBvo!}N|r$;hDzTp0C>wJg%)=SV;(g5-wTv)08#;NtfFDlqd$pGW?) zgnc)-#cM+r*?KR|1bvc^hmJFJ9ppC)gfNc{!5qW`O-{556~&NwC&ymo)vZR1JKbpF z8Y?>SA#hEs2&cvHnh<-i-fMOjZ83Lv45Q1Q5_!U1gCTX_Bm};wRW%S117*SZ`n%JV>P)pSn?8g1;QyKkOQ6;!$d}DUp&lJ z`%_W^#)0f>g*zfFjSP(4i5HjH);UbBnoR% zp-03M*24V~QgKOOoWWLYN|R!9?P4>hXUF1RJ*u}gW2KCGd2sb2At`nONeklvsf;v( z?3ZoRTvtj6#g8*%wJW@AlQ*%#JG0r_+u*HZb60z~Ck`W$&}Etx`tcXpEpNr{xrVFJfp&52}Z<64!Bngk)s7|E6otk(9n33Fk8 zkjbF;W0+E3y$aLlz0t_tgNL*st75YBKYWN&YrePC=b5bdr)F)Dn$M2qv;}8N&z}@? zZzWe}|3D@?-MhE}C4dXEyXM5!F2od#cqgnvAS7>aY);uPUljqfS>v9Fp{#W$jc{=y z7A8J~!qzr=>*Q{wV5_@p%ej26gz=9xdMNYGpv=@dub~OqHy@+SSYs?}iv0rCSFD|l zLMHozh41XxVQ*!tSF_SsvfbJ8~dS0w*-8N)d zw}pdyqTEGimvP_Ua+cPbMH3yno%6+8=`CR|t;8(&F1fQIuDLPrh=n3pJj4|atb#Ib zS3OtqRrTH(tap|Z*!?lya(3&G)N@~VO``<;y9C8Jtx>J-%r>&YH!1Zj@K(km+Yo^< zpkO-J{f-M#`#)If=cLqc{~s>(VU%h(fSs%4JKy-HwLnLsyV37wU_sS>Z~lMS?_Wk; zmSQy9Pw^t_F@n<^%vJ8oB3NjD501sfY_*HEAegqR+&?&&qc4RR?+Y%zLVG{LIG`&R zyFYf3$KB5d2S-Tc6mRuX$@&o&4}TEBN2<4<7yV|D`vpGvAtWI$owd@dS-~827On>8 zW(j7s^kQp~(L$T~o0<7{Oy;CFRNSUMMyd)G>nW|mJ*>ia|2I{5A*=8LOlh?5*i{Ip zs;I&pV1v?yi`>6QQH$%r5xvC_q@d|7rYgC5C7R#t{xph$?lJ{cWbpxJ;Qj@}1Zfl% zsjE~#-bB^feGGFGkvNi`pNsQtpD%oC%;tvTLHqG=dt_7mli{2#5Qpy2^X~m64MCLT~mu zh_G!HI?7!&;ZFS-+jcai?-}jX8~^*A`s(9N6W;V(o%((4)YnU=8vW!)=+6jNZ}0TR z3f=fasH|68A!>d)2<$Fq`tzk-PO^|p23e; z6{XSLdq+z%PIs|Tbh-+;QaYb671GHfvdE{i>3AVs>WXKw>6DX7r*p}HqLVKrkS;TI zS!!&0c-Q_>|FMBWqEyJ7moD`Wrt?m3p_ogyv?#VJw)v?G>AnIA$@G;9#dso<&72oU z#ru$bcdl5q`IDK8oLfn5c(>EB;W>Tfz{#4pYCA!mn&M3`~rRj-- zQzN5JA)PJcoBib5a_Me1%MZxpN&|hFVyUmcSjy$os7TRC|n zdzHPJ?u#c#Dxju>BJLpChq~c4-`3;7}@+_I<>wPqKJUHy4xJy7V8 ziI48@Pvr-LDU(cRvjf?99%SCvmFc#{br<8QVj`bFO=Y}51YOxIreE>Au4FbZW0`ld zgQ)@@4O%ml>B^MiIhk+Bu+Ma2GM5I+kx?lfoV0T{QRpt_yA%I}EL%6S6Gplb?T5$Rksp8Hqe=L0JNoM<#+e`6eF*6v9R5H6A#9B(9n@p!u z7^y;kF4q;fJ zgJzuF2WPHGUNN$Nv;bZ^f{n*ZOS{JoIhXGn8`;Nw7i^@CmJSThjO;Vhwun*2`qBs1 z4xVc^Q4EVVT||~#D&{lszHSsc6dz2N;)R{PAmDr^Spu7pt`^cyZa1rvu#=W{<`2rr z4rUGa0R8x!Aa5pe3rVXrjcHCAiAzn2NoNrAy(P=mfWnj8CG!M$L_U#~E;1dp3)v3k zbag4r3{TBSx#BbdXVJQn*%d5ODmW%K9hTp zi|nOi+>!$`wG{|anqe>L-du5~Uyvo?WIPFxqN^km!7)@C??NYKk^`k8_WztrGM6`V zuGvZCz*4rSG6m`P9A*T(9AufKt@e4L`=Mk{vo0sLb;5Is`FLNUH$?cH-K27&;V7)fV@nRM%V?SW*MV`+%<$mS15f&SximB(^r zYc|lAO6R+>{X-bGRt#G+mqdX1?Q#m_<#7WE14#p54~$D2(3IWA2S)x}L*K%Y=S)kr z1nkhP%<+J022lZ{4EQ8IucM51y->U%4;#jA#c)ZBQ!N9%Tqh0bOimrb6q}qm2v%Zv zMbb>*E|KdJ=sOd+i`&MO#4=qn6t>4wttrZH5Edz2`s;eT2qu_&n1O~Rq>kj95CR6W zfn?hg&!>jsdGIK3bZ}njwF;R^*?ckIKhWLdjF3B)APAPmCimNN{>c*GDr@{?Y46PN z?wKhk2SL0m-lHT7Vv&J>U}PeMZ`s9#!h13fPMytC{u=6m=v|V)M5!l(`j}_i6x$WC zgmG{|kp?#?b}DYPh3B3AWHCHaM zstQU_VXdonpEEf%HZe6eb48Fc8}H456!Yh%glluaEuGrjgjbYHI*@bnagbBWQfkV~ zO0(h_J%cMHID*6^4M0iKv4)I=x+V`!;Q-GJbS3ICi2+E(%oCFs;;UW7Y&9&O#5zDu zUc>^F*I`3Vz>gtP=d!JoG11pD&Je(!bK2uX5azudad114FPw>8`}Xg43b|y;F%24- znc9!0D65|+@vEq|S`;@aP!-H;0kCnp$k?X!=hAu6@>F-@@M0bq z!DG+V=w$~-$49O(!`-T60h$&vXx-qK7|-SM{pV(S!wO@+D7EQv(MWTJ-Xtn2j8q_D zd>Y7MvSMa20nu90bQ|b#^2KC4+ba@d!015a>}q8W-9<<=-HB2@Q=m#x7)(NjFlvKl z{m)oL8%L%Gi&>6r018dkZ=PM5DaH5Zvguw-Mv$=WQ`?yd2oOC*oG2>zf}u^4$j1A& zmy$hcNSvxF6bCS5L(sqaAn^=O?VUDS2XrF{lT&CN2rRLkVmn1pk+dk%%fXn^<(N~W zrOBy@8Jw>JGn7s?vmK<#CDZcoJ!AW+WX+&2*~2MPundDh!uYVB6*E-Ol4!pP>N3!6 z0ArxaTStd8J#r~#+6W{v$r8=TgN&ddP#ei7BpbBKf1=axDVf-|yTn>hC}N(g5E$P* zQk)vwyLWVoi}u9u?mhcCn^|p4JR^=~PXid7y%h%PzGu}^dO6DP@z(79S*9q{c3CG;lH%`s~UD<?~S0=d;k;00TP6h_BKICLX zxL|@xmx29sLnWiVON0|AiFpjF=4=oJ4eNv0$1oYXi#gV4Koh*R7_!Pk3s=hnv4WtsQ_x2m>{J;c1gEP`Ok4- zInuh(n}#4#!W`a8P635AgZPZ!T+HXhSUmK{nOAeDFvikjWn3X zifQ~EeuYAYr1$`sL0>VGG^?gbY2?H-W|r}9bdZd;AaspCt;DJ-b^**EbcLNX=>D>X zC;NMI{e7&gOb8f;pcku49 zDJ-iv$7&)#dyH>4&|zS`felm@TWNFHJ2NseRoZoM&z{jK5$k-r2W_LYe^8`AFW~p! z`1IJ`@zLG&I5&=E6qzS88DnCr(0yoqNXS@}_Cr_O@2IUvGRL?lcFJ9*n2j3|0d{s8 zWuQC58iJ>VKoI>;40tV_6n{toEuetCGt)4|s#yn;0OVw}5YtEvxw0cb35!-5F4n@D zdSRr4gaSJv5{m|nHCn|62$e7?iq(a>35HnKPHZ-0F`cqTm7>|kNO}Ha8=OoAZQuib z*hahRnDrbZpT;~e#w$DcG~)Gll|Y#N`JJZ!bTb0wioW3t@5W*M3Y*%*Fa_~}LWX89 zn-{v=U$T3#^^)j67c|aBPVCAI9- zQZby;&IfVGbh}avTE>+;!-a4lh0K!9?$P1hVqP?srV`DpFb`$BFfvJdlPZ%uArgRy zU=yZEn0;9oNG2g1m#?a#T^q6MD9SZS8MUF71g1gtJP*Cyh#4VnHvsmK%k}5E(wanB z6kNy)FR{Z&4h6Z;q_V^W9z*#+704N%$S@g5AG<2(11exz1);$>t*XTmwnnh(t4?R^ zEkd&9)-R`1%E1dVuw0DpmTf=mG>E!t8fB}gYzrF$vUH1K%9uDqi(W{`GrL4~ffpG( zg34M2BlF)*;yr&_2MaY4#p)u-Cb)ufN(BTT8gZ=gQ8abrE-KWc2L z=Nm}PovrQlr%jDwcXfJnU46rWk;#K+;k}KS(ZdaRaRUJ}`wkx11;h^B@Js_hI}0y@9O`U1(0BlEM4hpFdh(1tll2XI>l^x8>l^SQ z$yp<)K*OE`qtnyFdq*4gkB;x1*>_emg3OZGz$FpBJqO2S32vA+OYt1VZq478;_T!a$U)K)%PdVQ5CVGH zseWl@le=O%V5g2+56l1qFbnA7-@YNZ-3akS4AtmesB@wiRu&AC6m05pXh6pxDSMnp zXrQef>w|fM9t&@(8E%vFiNt7NWa?!SplW856Qg@e`^UyF<>=$!0m|(zV$A{C+Ntp( z*u6MP=bFtTBMpVr5Ds3z%|!wcd#`Xk+2r$WZKb^+Xj`NmiFgXeQm&k|uzJfVX!OIZ?9h*-28QFt{ov1ewma+#epX+CF?StJ9^9h{U^ zx38NC<3t!%3z-WXI)~?2M8W2Y%?&DSSRLkE_2-M~{#3Qo+4U;kWTvN*CMlPQ=blxq zoK@!WPA+ROU<8|op_NJ{KijK22GRp*(0zOm!W?yX^lJ{is$I&xZdoDOM1Lh1!$E|x z;r(M*!l2<>to>oY!^t76fvm6gv&;nHK%$$7?W1DTPU~eTwV%sgK%_Iq5@xgv;X}!M zJVcGwPJj(;nB3z@>;iB{=BV~Tl?%q!9%*8>1AxR&# z;TA4H*B(WhrqcbeWgDsrS*E4Zv}#pU+8+8qRz`W@7KT-?g$gyRKy2y7e4xF@3}zQL zP5oJ8g3O*Lk0gK(QjX!CA1$0@V$uo+!t5nmjwgHx8y%oW9`NFs5=(u;)p_Ov40Wfj37Ew;+CS;h1=fr+CuG4s_grt3 zJ7JooQmT;P{z@+t5S2;)>2AN6`P(QEpjXhxW=VqZW6q>u;1WID#}rd>my%p_!GD4qX=ZE<<#5ZG>xvL_SpH3DV==w6Sm$%1&Vn@T@gzKFcv{)M zI@b#_E!my0iSxa(#Kp11Q5BKlz*>=@=tcEeX8lHE3Y!{*Wxts03Qo&$<;@S^j83vE zi4HKfQFzkk;0X3$p`!IsS_eNvwuPah888_!O4+RmJg z7i2>=Oj=@?im>X$PLUMl_*WteNxU~Vz}ftJ_u zok9{)GM~h7+BDeW3Jy&gR*zW2byMN4lTBB%oP<7Ib|!h=1o#?x4GCXW@( z<#F7~oSotc5Z$m8MM=d1o-dGEg7(Moj`!3wB5>9ayoGhe$s8pdY(|M6iV$OUV@I}k zxCUb&F;1|wkYn3EQf*If`J^`wk?jKU3X1%@HU~f9@4eY~#OvPJc*|5Sa0*u@e3IJCvf5e#ZLn$Efm8U3^ z+!)tgnZlgsNevWtmXbS@;5yRue7ZYR;8{@k@`Kp?H(LhiPktu>i!)BzhX(D&m~q1+MM5T^ANI-aN@rFdTo zox`(eO1gFq=}GTi945zp26wZCV!JTs3q7D&P$l^%7J5uo8rW$vG#k=rs$nni!zk2} zj2kktS(8D)kGrKrU}-s~cJak}rp0 z)5uDCsIz~IlN|}!FZM&)gUF8H7P^jV#%PRx+ZhOzNyv+`GtO=&Ioipt=38`0+OZQG zo3}LZn6swXa5P7~`nuvEDcj+JT8M*0(D$j(8(rh5?;pspwVBat>-txGv_wvK>(F9v zz>G1Dq?6K(9H~KV5V3d^7+bzLvxU=!Mu;#L0xFI;^(hJ@_B#Yy726cs6+5_+U`;To zg0m}uDU~bl&a_Qo7*EB-3hQ=Lqtp0Miho42g@>*~U2atg9Qp3<;~et`Bc!r$Y>#<7 zv`r2R<*e*!$5QMNpkglLJdJ`ii8IldXJtFAr-g?veab?&S|Z~aSi2+B7TgA8+8U54 z&iRODC~BwwR3`#?5DJ88E9AE{-#t*)(40Aq4<3UPMRphQ8Q z(Qb&Zo#Lk)R}r8L4`0#%(6H_wUi4JXg_n`0BPA8vWIQ0giAsk zCbPsgr8$}tUMF}GkSG0*I0+ax+gG+fI5e_46o&AEMvvX^;Tb3qcv>M;TagOg2$7d! z-jPz1-NF%5k=nj^6wQcloWj-~M8kj`A-)JAoAE(NFw$+oNVf$e-4-yUHf%u4eiC#X zKS!MNlhe4e7IYcyEeVMVniiB4a9>OXNGI&s4l`~Yl;5~LgfxYIwwt?MazMb)Gt>#L zc47&1Qlww(fA-38@802YEPMxWY`~n~0=0A%%qpXMT5?WU^T|6EMio5?ohlY_Ae-|- z1s&U(_MkWL4*^+;&{S!cleDd16MpjG^b$@Os6K@u^S@U_wt@kj-Up+3y}z-GN;$HT zL2^RV!u!3JPEu(o%@hG(2Y|HJTS$sHYCg7vpUUuXl5@neG##=mz2N5pwcXb{+JlW$B- zjB~yPse>iBW24H_%I3kMN*$0zj<7p-%8qATenYyG(E)hiz_LU+PQ#-C*aj!SSidl|Ne>T(I6Phso8+Wx4mQ&TE-NUy+7$6g$ixy zQ*pv99Ka%lfxvl2lBXOBgB{K8HkyMQyPaY_x!oDxGYms0JFBw`LbFvQeNwYsE2lt& z)-3}^C5mCapSA&>1LV5i1&udFn+hfcS-UDf=;n$I3~5Q+?&onM?kMtCuzhY`WgC+d zx*%9{#Lb-G1WV*Q3S>fUmI<-(2d8P-K7yuNnsHpn>@)G*1^*=&=kVn8l%7*5m5?dd z%ieflJM>k`KNvuhmn=D$^%)rCj0$v2$wCb0<`goGcX|K?JKM>wTt5s@iI5x<^d85g zMRo0#<}OJcSV8y>W=|Y1lVzpD?R%Wh-FvY2A=8b9*KIUf*fDD@Cv-)h#sPHJ1^Otp z8>KIpXLDktl>>a>Hk=yVL~>xfO@alG=+)9A?=msC& z(Sr>QCSkFJrg6N-Uq6wN9`xttK7?fi;ER7?q0at^@xAq2iw1`ak1Az6Vy(0+wxUqr0a#JNnt9mTPE|_JU2HZUm$wt3T<9It3%!GaVc$6O@4yu`3~Gknt@rOX_;+|I zM`JgNfLd-^2LrKfv|P@d1~LbSoPs?{ff`bCHHs1#soALHfKcT;)&wpRnH{hz$?TfGpL-NozRhgBy z4fzr=H!Gk3n#EgI4+QcAc%S^{9h?czJL995<2dW&l*sRxaJHs+x`cy3SdsOZwRz7C zrbl+k(bc;o7Qv!XASz##LeU@+S$2Cxu0<}!0&xs=+L9J3EKiM=$}K~FMQJ&a!^@z~ ze9<0hGrgkPPz%%{+b$LQES;ElR1%PsMaZVM%zalswSUM5hp@8SOWpAd-_bH#u{^>+ z)td4hC`*I~?njsQUCGYpUJ3ik+RwPuALE56E|=&YW4J+9ws@RDf~qDbs_ecd?JztT zDH4z2Q)R+)@Th)UpwO+xGV{`zjn{s_9so>l1KdO5sd!q2pmf+o{-+I0ULrcEE@9MA zbb-{yK47~wnZ-FmY*yN1YvB#0xER<(UI6i`ILD6Sk*nYwkAxh{GSw<8v9LnboLZnd z*;*KjwazN4V131`oWlU=2i0efXN-hP`X?g{8_Way2KJlGzza*p?i6ze1)ZKQ>Um+GVUNBKsx7vUPGcG<*vo3`{BdBcoCT|L1b`(78%RA#pj;E zBAPHsr7YCa97sca?}9AW(u}`;$`)hjjc9Y)neRcHM|z;SiTz6;VSGsg)au0kCBTC~ z@O2vi>o@wHnt97!fRRxte{V_OTP%B*$;`C!baHmUh#RRcZWmK$Bd3);>t0CbIcRXZ zpuyQ=$suC3+o)zKKQufwHVh+AAoOqvBrVIS%plJ(m=|9?kv%kE`%aEm<=AhHH>}$-{;F)6j1PO0X51)WVJ6Dm?H_0U_~`3jE)?f z3U5%EVdb_d#*}mc77B|IKJs9DFvQ+_^4onYNd{XI=ZfiHgsuvMo_{u*CpCQQ$UoiF z4h~#c9^W1B?T!0qdca=uIQ77@%GsQrRmNhTOcZ z+W+v4Eb2HwV-WL!@66HMB(J>7TFy@tRPZCphnYURp-?K~drZ)Zjfnt65txYVr#a+p z9VJ>ZN^_%}FLpC)ik=YcaM+CYAL!_4AK%#vzf_CEWLU6xE`+l~*K>WxKZmbL!7gFR zhR0O(fV)w$(KhgGlB^ijff!A`@*)tZ>LJ;OmRr8X!P7Uw+K=3Kq3mGa?+e5$qXzT! z63j;&tI$1qdGAA2T7CcYIcK?;5d3Zw<(yXk3R*Yk*I`Gp24+KD&X^kX{6ldfwxZp( zi$XIC4a{_z6&^2^@80953C_~D${P#vPKEitQ(G$t*l<=oa-do|Ps{NYx$SbwOMG}i zj)6E(4YLY{ul!wPtM9-{SRBJATre5N9eGU+wUsx^Lbdjpy;;p^QD)E3KBnir5Mtj! z!L6Y;J^x^oG=6z!mp!2GEAkTua1uuM6{zInK$^6!*{ICVIZ`eDihfLGxJ7p6?DsWT zN04xsBgqW6V`KRbUlLBIkWLTt;+bQYAYZI_?s^JIJ$DlMzzmaAY#;{)Onf-0AA1GZ zD$Wjp9m(f&`X(eYH@3?18oV0-mHq{2C6jjz;7Y1T6sh@W8-ra4kTZckNQm}+pwx3Vea zn>*(HLN0lJMf8>XE*M+z;$5i=N)JD2#;rh#7dUAGwGsr?j2&3}kZ4DRO7+T^G;ywt z9|DjG<{KdRsfW1b)MoD_bb>bAIA6S0u}sbhKlhXoE3?>5<)_RjVczOP6T*zhu355& zgZffSlSKnBqy;LVoR!1C$tSN0J8@{J*NmYNphHw+ZPVdn%(knP&HH?lOUMzgH2AE% z5PpRhYHDEsN<}`y{U5U*LMt&=82rZ=^X?NRESTDut1*m1+aEc&pBpwRh4Eu#!u}yx z6tfBb;Pt;EOfL9=^+mpAV}vxGD#zYkCXN$slu@~&o58{nT-cObk_n@WLyY7{S@^Oz zUg%MUrD9=3BmG(J6OMg{MLzRa%!SMd*nt-v~utzUpd(eF#{qEy>?i_B!_+$`_fSw;PVKjANvX+R^RZ;Z6q$}%rXrA0GN$1 zqm~5YqpK}OTt!zgXpamZu^`%-@_=H2Th4)^Wz4lWH6Wr|D?~LD(k3b>ML8L8`88`l z&O?Gxw979}LgF58L*sXY{Ngn#+;24d{-A5Ie9AB0lEnF_qp0CHjg`S+b`>Xsullh# zkdU#Nn;qvP(%@(!j&JdZ8SEM=!{o|NPG-tp-Kel*9=Y3{z>d(6*+?+s4GS~hK_>kg z5lKueq#}?2nu;kcx@WUd0U#)f*X|q3zMM5w@gy9-5rS84aZnU59SY5xmujaO2?aZ! zMAuTB-Y7P3kz)e9A`_?iXUrrHm6Wv&(! zmr65}BhzRPL$dM(8h!-Pd`=S&p^ipz#Qu<+H7cg?N`snR5ifg2*z)Dp5rziuycPzH z96{Q(b-_EN+!q&14%bbLGY=N1o{oPn1-dq4FW-{%Z-c!UY|i_kIPj%=D==;Px50i4 z&f0O_qE`6Dr_Qj0Kn=p589cS4FO_6@c$l*wZcZ1(&F8%0=4)Q@4YH?e*_Y^j!t%JW z40>R9iNC-@p<=KNSrMRF1aJ1)*U5uQWHZp7aK=Zi9l=5be&W~l2xb+0`-E>M;PVLb zB}8;38hxx`qY0m_{?NORM zIK3}O66|laZqy?&tT%cbJAC$q9y!kh%4oBPM@@;QU@c#3X!<>2`aNMjj*-x+1z#Vt z0=Diy^GlKPp-8`1eUUAhW4`Z7*gqb{Y+f~@ADYHb}tA{id+` z%ou`|F*7hT0aH}c3}w<3lr-feL&cZ|m46$>P6k`(Mkmw19Us5;D`$;wAps|gbJ+#` zq!v2N*pASD+}HM>Q_0gThQ47R)-QQY|A>zs9GpCw9I6KbogTav9X_tDuh*e)=~H}Z zz+emV<%hnlrc7~E%^zmt(J~ag&di6o%@`VTbb`Elrr#Y(smx^!0z6oV7Mge3wd|BB zI%S3@WrinZh9_mlC1t)#?UN=&>=gRlyd!FfK>Evw(y~=aInt=Y7JSmQ^? zd54NMSa+oMubds=^&OoNhie z33aVZsWF?zK|W>7Qa*8c)E*IQnI#Z^jR+QD@EEo5>sfoqC30-Z@4fIs*p=z($D3kk zk9}FSFa&u=PJiti+q=*3kUW@nZy)5XL~f`sgiawD;Ok&=-Wjx@ua=W@ixpRGpomeM zHU;G)IPj4oU|bdnbL1Rf9M#XEhAp$hC?nI)cV{#G3BT{`z}V0C8jae%*unF<=Iou# z5uZrGM>NbHMHZ`T*~WII_K z;dBs%EBV|7gl40Kjqe$m9>(6y$n-9=;b)Ici5abp1j{vBKT~u}!{n>L3mbO!2HzAqI2~e^T#Bh_Q0hG|?l|4a zAu{l}2W!fn@GZttDZl4 z@tIV15=*uFBn)-9+)SMWvKGP-u-T{}WS$6$#H^grAZmPQ3eGyV#HRrJ} zeE#8wSnou2d3pRN>T%PqBIDPD^5Q>S-_E)e*p5VX4!;@t5gtzW0Q`xXMc2n}@NTTS z$-NmRrfW`{nNzbUQC7Eo_*bsUn)>T!-EiEEv75Y`t6t>37-@4g&Cw6dsi|kxoMmwK z`VwxmZqW-^Ib7ksv;UynrsqHI4#!venL#+d>L~tjyPl8uP=8O&c}%)6#d?OvtW(mV zUy4W8F;-Cq{qc?X8Rq|kb|Ou<^*S4R8=(*MIkA(D>z(b+nKiGfE;2u|5dQ>jab!tk zX=GXCaJit4^5>5idSNeeUPj?t4lMeQgsF-DP`#$&`5LDlY56?oZq)ym@bKVrof9h3 zpWw73oas4_qljmDH^Z6h1bZXsIww^;f0Cr%>Zdx%zvGST)K;Xgb$Sub@;KL{h!0<` zQ&*9`E*y>g7F5J9kn%6^$&8#axLnMd^8Q^U=^ylygl84&yQCuh5V@y2ylRis}f z>ACipYn8nbbiswo^AB?`=C`&Yer?6`r%C=n;Az1v?p){e3jdiE{)P%axmj?zPD|jy zo$It!_&X~68!G(kEBqUs0|+6#a^}qgzarfRe$TnS%pY@ZRX_W19{A7e)KAKs2Y&Mo z^>fXhhu->_`bp{Yz)v1gKi7_V;2+-u+UrEz`~i;Ta~++B`H257=3k7T2S0-z;63Kk zDeC81I1lruS^Zy<_(jeZ^^~qQQ}mx_|W6E6bM%~|L;`xUQLBz-fy4s^(LpV$0m6fXfX z-*)wrgV9g2JsFe8BD_u%i#q2?bcX{@0L&S_63sgf=Weusa)_urSElHIkx!%NJ5D|Q zJ59Z#gAQkc6CHA#Gl>_P`4a8c{IZ-Y2nWtrTuj{NI4gvf#sT*X?&#fmEw$>*5< z48<134T@(eCKWS^{fYyM=PM2??o~XXIIVbv;x&plD85ATHpN#dzE1J~Qhb}@yA(g5 z_%X##D?Y6FsN&ZYzoqyC#h)tvQt`Kne^&gvBKa%(sakQK;$p>m#Zwg<6+0BSC?*xR zDeh1_SFxnHNAZB-jN{L8Qu}iU6v8Z^y;x5H8#Yx4>6|YvjLGc#F z+ZA7{_(sLID!xncgNmO}d{FTb#jh%UOYw(_|Ec&Z#Xl1=s|#EyK58|D%LBmQ*2e- zte8^lRUA|-DehCeOz}#^>lANMe5K;+72l%xZpDu%en#;T#jh)VPw{7pzgB!&F#=P9 z(7$4>;xffk6dM&cC~j5UrZ}WHrZ}N^Q1N++FI2oq@uiBlE51hYZpC{Q?^Aq2@h^&Z zLI7d??^pb|;ujU4Q2d$V9~G;h0P?w7#Z`(eidz-?6%QyrU-1dWPADAA=WW#nKdShM z;&&CFQk;FfNw+|;QSltboZ_(Jl;U-YcPQSg_(8>o6`xT2x#Ba5)pJd`rz*B9W)&|~ z99O(X@m9q*D!y0ovx;9={Hfxf6pw>q#eP|&xK1&xm{+_+@p+23D85ede#K8Iens&| zioa8IVd7zVb&97bu2<|<98sK9yjk%zif>o^nBtcdzo+;s#b*^yguu&kS1PtDCKZc{ zql$+VZ&G}<;@cEIs`!ZFcNL#f{Do6`xT2 zx#Ba5)$>ew%M=?F&sOYLyjbxv#cLIBSG-5@1BwqRepB&D#lI-dhiQ%NT&1{4al7IL ziU$<0R(!eQ8x-H8_!-5oDgH$9kBTuUE-Y`M;%SN-6}Ks#uee|FD#e#6-mUm<#ZN1K zRq;O*|Dbpx6dabjT(Lv3OL0hXpW+pYFIN0F#rqULq4=2M4-|i+7=a;&<;_!Et=O)Z zRvc8^t9V%PMT)Oge23!46(3dnx#FJ`YoLR&+!cz=igCrf;)vpm;th&-D!xVW!-`)} z{I=pR75}C<7m6s$Jz23yajW7E#a)Wiiq|W?Qt{1-pHcj>;(sbWtvDNsD$84|&n-t%t_@Lr96o01pXT@1C^|IW>il-}XR?I41s5q|pV#QY}zDw}| z#m5zYtoVDyD%uE8-h9QiiW?Mr6n83KqWC<;TNGcXc)#MO6u+YQBgNk-y30(tb&97b zu2;+}mK0yD_#7^p!goeM-{)V=)#oF{Oc4?QCzQ>S1c)Bu6VQJYZTwE_%X#V zDSl7!SBlRno>*_nU8&frm{cq(9#XtX@zsi-Q~au8<4Tj?If@r6UZ!}h;_Zs}C_bS0 zsNzo*|D<@_D(!#8b&8u5w<}(tctG)L#n&pnMe$RL-%)&0(OGTES*Ey7afjjo#VZwG zp?JUI#}vP&_-n<#Db}qq`8O+`r8uB?nc~%ocPhSD@l%T5RQ$c7bBgwlV!L8oai`)z z#cLJcq4;sdM-_jr_$S4hwI=`56*nmMD_*L2Sn*cH`xHN-__*Rziq9xEo@(;ntXNQ- zP<+1P9g6oVeo*mY#s5(JjpD4+Ouma1Pgm?xEGS;8_f*m6$cgfDjrsRk>YC=KdAUw#rMImOaAbv;**NcDxP?TiC?LBmf|+WDaGp) z?@)ZV;wKcpq4+b!KP%2UQ~Oczbj8hzS;Y$##}%(pyjAgyitkl?Oz}I4zgMhkFy+lx zT&uW2u}5*I;w6gDQ@lm-b&B^ZeoFBxivOkf7sZnrO}VQS+Z0oZ1B!bTFIT)-@imHX zSNxdbmlVIJ_$$RZO{TnsicN}J6?Z7^Qk+)2Uh$QRZ&v(};^!5=rT7cQzbYQzY|34( zh}|ZkuX7Z0io=Riiq|RLp?I(22NfSyd_wW(iq9xkx0rI4DK;o(6!B$YsmHkDHHxQVFZ&iGq;^!29rs%erd`?s>Dvl{0R=i2^b&B^X zen#nC2rQ$mk zKdJa-#UCpERx!HKlvk^`MiC!ulzGvmIHb5w@e0KkEB>3}eTtt@d`$5Nioa2eY%=-J zQ(Udsu9#E2Q1PJRjf$^Qe5>L|6u+qW9mW4r{JUb!W>fA8#b(90;)RNrD85ng3yMEg z{GH;QEhfLEif1aGrP!xfQhc7`&5CbOe2?O16u+jp>MWCglj4Ztq~gtr_b9$c@e7LI zR{W*nac7(S>J-mZ>`@$0JfL{B;%gP(qWCGr?I|IOOFz}Zyx@BeGho;|bI-edMK!;HNr?HOc3 z8gnG7aT@1S=%gO!5Hdt0Wy&FfUHdh}Mq&r?I&q{pQ+!NZA#N7G5f6)1+PL<^ zA|7k#)C-={?y$EwU0f!v6h9XCiGPWKV)y(@#9XnXc#}9noFP6czASDKw}=PD6Jpi2 zZa$e}uGm$)Nt_`*A-*7fC~g-Iif6>ccCP*UVxibo>?@8E9~7SuSBaa%?P8gDMy%dm z^(7XHJ;c7^cyWgKg!qEEPW(*VE&eG6JGl9ziP>T&@dj~}c%L{|Tqdp&KM=nb4~Qqk zKu0&fh}clPQpERRoPO3vED`S&9}$;|tHt-luf+XgxtP+)wVNR}6+4Kxh_{O~#pU8^ zakKcnctVWp?Aos-ULm#>`-pdm)5XQ&O7S!CTk$W^+r_n?BGwfP#J1w~;!tsdI8$6M zt`;|o2gGAym98p}c!k(j>?4+lv&6^6-Qw?}x10PIv&AdL`^1OE<>DLS$Kto*@8W5( zN_Y7yUM?1i-NpXm?c&4YB5}3&zW9~6Uo00>u5t6r5Sxk}#9PGM#hKzF@g?zN@hj2W zL-i!q6$`|+;`QQCae_EgTqM3Eek^_^9uh0Wq@F5|m?PrLm(FUn_q3Qnb=9ZS-ex6 zCO##;DSjyaAeM=q>s*haio94$@~7l_Y_YsF8*@5F=R88PvCH{beVp@<*& zcG|D6I7+-voGZQ}t`oP5`^3M+_#0GzVz$^$yg|HGyi1%VJ}JH|ZVY5*;_u>VF|D_oZ(Z?9v5VM8ED>jkkBckCcf~Koz2Y%3 z?j|>%R543zEp``&iW9_{;v(@S@on)7agTUfv~PCv%Mf$KR$?DDkUOtFtRT%01#7gvgJi@%HU1Ld#SP;4jm5=V$L z#7D)K#ZSbq#XrU1AlH7Hm@Re^ZxBa`_lZx5FNmAO?czSsbBk*~QM^QKDRvbHi{r(4 z;?v?EL)8Z;|llX&pP>dbo=2Km~L@X5Bi37z^ z;tcT#@dfcial3d>JR>F!b@RJe%obaSH;cE5_la}GW#Ss~1MzF|h-lsF=94B~DqbO8 zD-ICv5@(4|iZ6>B#4X}M@q}1)n48~a;uYdG;z)6#xK7+6?iSCA)rPzFa>Q%IzTz11 z32~$Nxp+W4Ee1xo_G*bu#A30pc$@fy_^h~H{7EbmV{dcqRueA~i^QJd7;(C|NL(Sl zEp8L{h$lt=NH?EGVk>d5c(*u9JR@e6xaVCZ_7^9KOT~@iSK>bLs91HBYbPoeh@HgV z;v{jt_=0#s^pAG!q>BATJSE7P@5hS|h_l5<#YN&0@mcX@agDfD{9gQ1JSLtJJ-560 z#*2w!SZpZfh)u;d;x%F)akw~5d_;Ugd{JB_t`*-GzZSn2e-?ig{}hjjr^J{sZaEUg zsCbEZnb=h9D0UaG6K@s=h(pDZ;#l!6@m}$M@geaEak;o!d`J93{7yU|9uvJ|-SULQ zbn#NLKx`#;6K@u86~~EF#5v+y;%4z1@fY!kXx-uZQAG@k^~8L!mDpYEBaRSwX+iOa<2#TDY~;wEv2xJx`F9u-fC3FF=TYl(Hl`eL?NAT}3UitWTMVo$NR z*k2qfmWboTd&H^YEOEa0l(<}6A+8nQ6+absh(C&l#8YDMPPe>CVqGy`Y$Fa5$BI+M z`QkI;8gYlXPdp}uCb;=U#4NG7*iO7r>?__P4i`s@cZyTR1>%$9Qt>(Q74bFkU2(hk zt++@0Mf^iNAqMYq%TZNK6)zI&h}mLGv7OjO>?!sZ2a9)#lf-G_BjPggd2xmKnz&y4 zMEqX-S^QP}Q#>Y~5Jnjd`o;s{80Q%{8Icz{6X9&{w^LCkBetS@7-?w*kVYmE=I%*v7XpSY$kRQ zdy2iqA>tk46!8&pvG}sMPW(jNDgGgz6#e(Oe%BD|h&f`B*hRcayj2`8P7~*eOT-o8 z+u~>958@x>er^Uol*Pj$I zEM|y}#Aaf9v6nbl93hSoXOOtIc}U?$$(EM&jJQVnda}r}HjBH+PL{Qoyb{mvA=}~E z0r$G}lZdZLBK~5s1HN}FULn0m;r8M+Bevdd^@ee8f-_nx@udu9xiZ2t7Dc*CRo4-#Cknp>f!kJ z?P96orzw7}__Xxp3a=2?lBlos;wL2RZ&Cb@()WpfD*l+_<0iZ32gD>2=hr1sUzd^T zcrJ>JkZeuZa>^GMi#ffY!uN}_ zq(7$cBJmj#c3vRSzHdlhC%!L!EN&CO5`Q3Z{yq}tACrDUjJY2={EHJqVzQV{;`~e! z=Qom`BQ_JS7CVqg-;G52o22&@hbn%g;wMR;EKZj`N8$P6QzYyzQ~V0)tHq6q|3LBE zq<QL$W%o#omKh!>McUt4S_Jx6RMy{*_y`nBRP=_AGQ;zV&O*}$@9iVMZ3 z#Z}@P;>RTX`Aqyu{8s#hguR2}8R?z}-SYw@;*-P->2<|M((}aj(mRXSiZ_Y_NZ1=H z-YHHJXN!-D%SrhEg1B0ILwtwqgz}NembFXa1ByQ=9+qxBCrO{F@WbMK=}(i{mbF6Rb&B68ZkN7C;l1MD(qm@3{>F(3 zB+8LSHnOaG3g;@mP;4%}qj;V4-r{Z2Cy-SwYlgz}75}*Sl=PRxwbIv%o1}k1MlEZ% z!oMm0ka$FT%pBMMM3U_wrb@4^a6Pf1^d<^77u%4?uOr#PvTl~%PrOC?og~stQh1i) zXN&Wtzf7WD-y|=wtdAAmLBh{(#NE<=Q}~crA$lKi)B8!-OHnvYyh!?`3STDXNbf54 zmflAkNTQr06o04myT!>Q{C-i~N+SR7$q?oxh095l=d|dV>!zzhLa!>;ke;dVC1Mll ztrc!3b|#U}wTkaA{T6YA^gGEac!s0G^A!J>_@wmb6n;tEMB==UNz}tv(!UjdBvIZ! z$RNt6uzw!HC|815l|;H)Vtwh2#9ZlDE8I$KC%vb_*NZnxAFA*Ou~hmj(zdLH3NKgu z3*rjt>lEH7ejt4t8E;uXD*T7y4~u_GkD2e5Gfqq(QO-2dhj~KbT*ViP&84?fxRZE| z^qa{nJa&5r?$fN#B4E7yi#l-b`ZOW*NMHwf#MMHPVsJW8VNraD7;Wy zCjEJFgY-?}XVSkE4@f^K{w@8qSY?4*{;Fa+iF`9jlsi{?q1Zz4*C>3g*q225+r?7p zQ^W^J*qy8RXQV$Tt`c7p-y&h}J%v9Kw~9N&A4#M;Lc;zDg@cbF+|IH>Vw#vPW{^0q zzQT>fLa~|HiiF+k#9`tjajv+U#JJfe{w^LDV;^_pFB0pEt;L(gTgA!Z!{Q=wjrgv( zOFSmVJmKb(B4&t<#Aaf9v9~x>94Af{7l_Y@uZ!=CUx?q6wXt51sP{6_TIhyj#VTS| zF)Y>+>xm7-Jh6#bOrqU-D14pRR~#tbM#7)F6rLo;SkQ65GEPhtBVt1_TWle=5pN`~ zz;hMFLE=#Hc5$4DZLgCa%e+H$2ZxKqm&BFg`{Kvq7IC|HKs+eMd0cw|v8q^Iyi~kQ zyh>~-_7JZVhm*K3Rw9lQ?-HkqGsLIFC8G2EKb-%P!mo?Y^Z%eb&-nwtmcCp3N&Hp( zL*#=d=})W}6hor(TtCFuQP_E&AHq!)cAn#ha2JK0=l3BzK;b*Y3F5utRPk}~N%3{@ zE%9CP193N56YGxntN4d_R4f;(c-{0>#Wc}*9v|#nqOkKkK7^g;?}4qPcM!XXy~G=XrZb|GmP_^Ysuup)em5N_(-Q z^L#yot1Ik0PY>b73O5m(i_Y`(5Z_th0peisHgUA*JU0*NXDK{aTp&8n%R~Gt3co9U zAbuup759n1iYLXhVhDRCmM>YnM65417W2i9Vps86(RuzI?35@xM!ZX$B+eBVh|h{I ziW|lE#BWJl|L+#}iNA^!q8Ae+(*;E5d3OkBDtw7pC^i#2iQUA0;vn%3(Rscd?9Ej8 zVevoW^Wr*jqqtSvAv({ogPq?LJ|$L&N!SCk94TT0@p7?+*haioyipt`I?u0zol=FT zi1S6~IdzC%q3~+)1Mw5_JMjmxOgt+3{I0*Y7#3@Z`C?PCqu5pKPbOQ|E#e4qlz5*w zO?;dzu&gJ=W#Y5q+hm?)y(@k!ekT4b?iUYF)Y>+v&4pCD>4T^Um|u9 zuMuw&`-+3bVd7MAhB#ZCCq5-E5uX!Z65kQu7k81^4D1p2i@%G<#1ojeP;4f)6pO_h#ea#TNZh{}D^3(k#Ye>_#HYn)#PwuV%X&xrNZc%bDSj>fDIO6| zif2V%(6wia7n4z3FNyWVMk0UogYoUeu3`^yusBRC6{m;~igU!r#6{xE;wte2@e^@3 zc?s5M@mKK=F($!{j}xniRmC(hUA$b(6|WGl61$2$#9PE$#Zlr|ak@B5oGUI6Uldn} zZ;0!}O``MsN0f6H!??e)N8B&|E*=w4h)K9t!t^O(M7&tc5*vyI;uT_7v4?o0_%CsY zI9!}8-Y?D;=ZOo&e~ZtGFN*8Mcf{=^{_hlj5Pud=h-bvuL^r)(tR-fO&T}e}_A-TA zk?1RJ#V(@r{7UFU6do?#E{+rDi1Wq8;xciqxL*87+$?@6el1pr&hsvjec?xEAd&R;`L%5aez2MyhofR&K4Jl z3&rQem&A|7&&2KGPH~U8SF8}d)!cFh#6&SwjEI@yC8G0OQPfXkg`0@Y#ol5caj-Z{ z94Fo-J}Ax+mx{~9SHxGv_r;IJt>O;RgS{5p&nG5`Nn&lWp4dpt5!;CE#cpCxvA5Vq zyhXfK93_qwr;D@1x#9xxdGTfOHStaHQ}GLNkLWxX73KU};ge!8#VvnGjEZ%{La~|H zQS2(-Bi<*@5FZrhiI0h|im!`ri|>k`h@Xo)#BanO#eL#Iu}t*inv3n3Al4L}=deP* zOyS1jRborAk2pXaCXN*E5GRQDiPOYI;$m^R_=31fd`;Xc?htp0d&C3cLGg%qT&xhi zH8eiOM6r&TB{mV8i=D)7;%(w+ae{b{I8A&&e3q<@_n*X9#n;7m#P`L`;ui5+akscn zbe=N{yGIm0E+*lIAM;BQ)5WNmB{mfE#3o{q*jl_+yipt{-X%^G9}piEpAerBpA*-J zYsL4(kHqcbPVt0zMy#6Vman>4Uu-0{6pO{)VjuB#ahy0yoGrdAt`a{HKNok1--w6A zzr+*b88H_3rq~{S@ggxp%n}=l`C?NMm-$vqv3_R;`vjPE_8+*!aP~DAvd(@eo5Vh@ z35h*L5s9^_9f`TD8;P-SJqg==N!%wKLPl{PhJ>HvN$jgjNf@6_Hn5!E$KrL_V+7W4{Kai0hkg;;bSIof!e6-P zFe=s&v&4oXTyoOE6^C%aVRNya*h%ar_7txdZxV-y!^IMDj5uDLC{7n=iL=Fd;$z|> zak02eTp_L&-w@Y{8^!m;E#h`@r?^WzARZLU#G@jAtjoFYEc(R+F-c4jqhcK~OKd1M z5&64hv|A*$7Q2Z(#p}hJ#3AB^_vgn*FBPYV)5TfhY;m6Wn7BxMmW*N^7FUR?#W%!t z;zsd3af`TJ+$ru7_lSGN1L8rkOgt)F0D@0VlzC5TC4ikK#*i_ZH3NbkHa0A@*V zC}xX!ViAdP-CArXb`qW6|H-l}{w5>GeP3~)I7A#Sju$72rQ#HEx;RU8ejf;S=PA5c zTqZs%z9_B`SBr0m>%@=5&EghuySPW(D;^LJie=(av0OYY`n_&FB#233is-zLf$})- zV}M!G8;aRtp4dceF18apiQUAW;`QQ9;t&$^>2T3`-vi+>3Xc~jiqpke;%srAxL8~! zJ}bT`t`Jv?8%5`Lh&Zn+yjk2S?h^Nid&L9dL9tvsEjsU;z^?PY37CY1f#ppRo!=)y zI9=hWSVznf8;Z{RDp+@%_f^0m>R@ZJo!CjdUc5={D-IM(#4+M{aiUl%P7!B|^Tfx* zMdGt0*7Fy|6(sH_tQOxOao=K{xRJztjrYWlNUWcm#VsV({q5pT66^miaSw@oz+UkH ziS_lMSVm%Ba8xWOF^``XE%+LP`7>7ZleIBliAf~p7w319z%+(AKEx=AeMB8Gi^P7S zp_ol(q+#No5a2(+JB%pge<~%5}o&< zT4Fpg44QWNj^#(Y1gN7unv!UT*GSZVy*Lo{{w<06c78_)_1p#LuzoM`gQ(Y~Bp<-3kVd2pH)(^>mR_+Ce0Wa*R-CY^Yga?06S;dUf^?5prV66G#Y zcnpd1JNq8kpUp7Jut@QXNtES9g;$X9^&^Ehlc=AA3YU?nr*y81uou<(*hJyxB!s{51`gGQ7gm*EFdUe)kgq`&{+p?VX7~#{5M?L$w4j`OB zqH@v{PA5_CSqe8KQE5#SZcd^d`YP%x-;^!pz_ z`+6>kTXyrys;*J@*G2#LABDZ}?DKwk^}1h0>|B`MqG%V9rk>dPaJWl&y zT6gM^`LezC<9}uUZbIO{mBRh-u$d~0{zF1@~l@-Wb>$Z;UA&gST9e?jX`_WQ1NO-~Jcmn^mbCY(GXNq`3vmrfxZ7Wj`*9umGeD_bWxM3>@oQ51?dv7M~pH;FXJEY5#ZlH|E)hK zqOK~ZYmRir22Gk{_K(WxivE{$y)H=C8tEp=x61bTo57XqZ%C!~jVfRE)A1MB+X#D2 zXh<*PANyNnd*dtF%S2kHqrF8J*ei!U>gHwaJ$8Y;>6O~I4iX!CZ(LxH#{QeV)fd>C zUCG`hmF#VoJ-~VSVJut6gz=B}Dk_)vG1%*ic=qQkrK2Bz${r4#R}+ZS@Ht=eVw>{y z`vvyOVXs>^*Is?ZoAREzz~0+SaUFoZYF@@3KeK6$8TZq3mc`$1GcOZoBVFZkwEMTm z+Je13%W)b0n|#wRuy^?;?7xjM(AZ16z+M`DTzeSz+UQmmQ{*t8uK#t z8eCwn4E7eI4r#A3{u_HOF0i-YW6K(h>n8Iu_O86Z-t4zgUL>NuT>Llo_?yu@$F%*~ zJ(iWz4}xBdn|Hi-3 zNQZwVJcqB8HXbL98#>n>%)3%HRyU-ZjsDUMI=Yu*F9~EHfW3cSdpdfox|L3(9lp5c zR8D7M;=HetVA755bIb64w-4zvq@>Zv%cId~LZ#dHR;SEPdKHPGMl~JW* z%{v}Bk(@oVWfi2g+f`0mR4J_$^>$=_X=9PskJcXgIHlN%ZvHitv$?!U68%O$&#>xT z(Xq5Vuc&E<$>lXtrWB{$T6IX|){RGE`g=~s{FUDsM~=B7#$?9)b#D+fi(CKIZD7&g zJ8$V(w{F*k3Eorj$LnlR2LI;rw2~#KJfpm)Vvo*1$e(mk`z5Dh$1ue* zgzFR`wgqFNNono9r{ex*jQ5lekMUh{D(;RYr+j0Vobt9ps%o$KU-B>XKZ3LgeK(h< zblY5>l)bq;JzBQD>(NssW$W2ao+4Ixh5t%x^6p40)=3k5;Q58;pMSn|cgR|N+-p@F zKf57&&8A_KSHus^t(zCrPy z`>hRKk3QOptvPvxXKwO%?^_-IF0Ea!!xHqERrtSfRcQnN)}%e2g`Q@fx&J6zJPWM` zN4Iu8da}g3f-Q!YiJBw!inMm#!y7%_$}@^a9!Y9l1bQ;iKVo~^3oY;AzOB5+`nB?$ zj6J%kytG9+`cZN;=I};uxANLbU%RLWQpS{B9K+OXRi1&=8R5P!?PncWeXXM4_{)AR zYa3hKqHmA2jXEUXkvuk9jJl}suWi_|cHi{}%I^0>t$JO{9eo!|w$_upvuD$iQ{h{b*#bGUCy z3q3pLSihEok0fAOB*NmeW*NT_DtAHjz&D+t*X&_TDg^rvUoa`XQB)&fd%gu zTD{6M{wX;u6tzLvEzdHiJYCv!>+1A*l#A`%^=SQ87qwqmK4s(6Xa~@`_~fk9rK^Ul zM2odVZSS$_`_XzQOAwdsxnkietHH6Y>kfNDfi3F}mxin@C2c*m6FcRJA(>IxH=3owTGp_MKJbv5k4w$*rE+vF(?XTa9P-4ff?2bLzJQer)sdcZ0S8ZBZaeQip5B=!*in!ulYb%alQDN1#8l`N=FZLBrDbLH! zDlS=Har|sH3afs%t)9BAP=>16H#sHr zp?tZWqj_!0>-HaUbWJEgF zEUETtTKla?nHKBW;oFn5lE<#UR@B;)g7IIrp81FVOa2?SZpo-wvU~rQ%y5Y(v(*q^ zdzJ&e7<0msqTY53w8ZXz>W_UTX-$oevBh)ClQyQK7ggE%C2OmtcT1hMKdrT*N$ahw zQ(G#IuQ(emPFjyRya$4sj52-N7&q;&ThR-Xt%m*$>1fS`Ncrpjl;XXZ^H{IhYy6pA z%Zd_9ho*E&>0G@d=D*qA!$}F34w!;g$}Gt(kGXt6o6ORaTes9s=urFr*zY-`qCEV& z!SwaB6%`dDe{0b_Y4yn8x_9qdR*@IivE^?Yvx|a)8rgeJXou!;TA1}qI<0}(m ztwqx6y7XpFxNoZ=;qj(lXLPFEuUl8@*X$GL_v_Y``gMoDJ+-?Yy`e=l%;_BWW?uLF zk9i%+|LeSta&b=3y4++9$H;#wVvAR-Z7?jjw&tG2YfCepACd)i`Pnp-WO0j%=OTlwsaq%|>R@iE(4#THlT zxT!oQsdjlxgB$uj-uLl)D~^{`M2qeA6~{9x(lV`#isOgQ#v-p_u$s1ky#W3#www*n z?58bHlQsADj~T!eJu#ZI-tuImcBnmUN%@|n;MzKS%GYlHHNM)?TcgFbk6OvE9xJ`N zU_+p|>rtx({&%l9Uh8a4lwc!D@YdPd!+a>gK9nH;jCGlR1FShEXmo~T39|MfZ}cgw zMlF&$`ic{aXBU52zN@6-cn#Fg;H2rY*t88*iW52}wBPirm5Cmf`F&{XsscG|QGig|l&df(W_547|ij`fyreQIrozq(bW?cQi>wnn|P><`OM zn;I%#?;n!Zci;ZsX4GhP=-&PNS!+&y$cy`xm4~g7tgnRP(&FmHwThFsS+%jJ%g!ya z>ff-XYHQD)r(3q)k~!X!S5g1O7Ef)fUT#T~V%82<`1oQg>-g5LWup=~)9x&f&CckM zHa?^Muv+((Zz)L`klwoIfO|2H@qc5tx41^_EKf;#$)6VMJLReB+urz9YM!Q?ZMz;l zJ=)4(SL={Fkh;>h$)nLMb=?8mPwIs&{~Q+xi0~MJzq*>MZ)k8*7IRiHv`B z?V%z5JsdNo=zC|KF*9@J8*6ilV>8%S&Q=T?5?dS@Z#6i$C5qL@Q#-DBD(dRce#V*B zrIKF#%oo<2c->yoIi){ZgF0v!(Xi=Y( z4e=Rq8P*=wj%N=2$SMwW+?dy+yiU~fICh*ZTj9vNV*P<^x3)8W+aI5Cz}+{pvty6d zWDRngoYbsVhu*8WSG@-NvGh(jx2R`%?QSg*nvXW~G`wg_Ov9>MQaiF&cp4;Z@Yac` z!yGNAWEtqyoB>#ZhQq9ehqt(4E3*h=;_QY7!>k7Tw^*5`9j&!Z)}K3re$X9`_lgSV z=)6CU7PYKWNA*}0{DE!++_2?G&|ieOSp1K{f4-av&^`RW{(IF_*CzgY=Hd;3goU^g z_SLqmjm$}}nArI8R>;>AceEZZeU~F+UxT!(5gX(2zk?HEVto9;I4{2~;cHs+2FAq1 z??B?1SYNw_h#8FwcVE|KlMS~71# z_#VceINm3UVoFzyCOnZU5sa zO~8M9OUnxSKgF$s1V6t!S;c=6w}KP>AL8ag$bT>H$|U)}!p+>O{l!nt#DXc)q9qJ=Ad6&+nN;{Ebi}>3)7Uua@dXEc3=|J(Z5KKOg#)=zDJ7a#6@`EPUk@IB=6@N@{JH%O^oAb$82Z~~9(y3XYvi#nhVz$u>?!G3 zEj)JT7I;J4V?T`?=XmVfaBFO?$8L*vpXYh(b+|(|-(&AUevf+W94{V);j#HCpvOFR zf0%yUV_$=+e*&ga?F&8jN!0jJkNp`;AM@CMprn6$>?*jQdfa2@1^5oO%?~wPA7eMe zdFx{Abs4zL=C$9(ox5MX_S|at5~~<9+sSxOAt_u8z0$C;043WALuN&wdo8{oZH4 zSc~8NwNYi(4?g=CeA(l(PgTW(Vtn>#IRBH+J{h&FE%EkMDD>8NJLW1p)FR&I??itY zZ>Qq)?eTUW^wS;jb|&yuygeQ@_;tK}0Ij(*-rk2K-^AOOqBY+L+RIQ&YlC(cJ|gjE z(B6%jcq?dMi|Sb%vP&?4pAOj%!p|ik`w8T*G-U5U8J30YB}n;9$o8Tp{u8n@;LG%6 z`>IxW;8e1G3EC*Bo;?@YR;_1$gp?(z_S!2gYgDRT1tlAuYJXH4k0MF6UqOk+q}mCs z@rB7$dpuI!k!tscm2s(dD^%V1RQt&&Dl64~80|L!C!lNGm1-|Rl8LGIbr>jjr`or| zrF&o#9di;+Kn|s;_D~F;dsFT1h$~uTZ$?wKSY-3|bjwBdji`dwi|k}{{Wgp2)G!_o zxX8{%%C?K_5AorNZkz0CXw>eT?7gVLzQ5UPFq!oG%|2SgvikpKcLoOhW;Z~O9Qd2v z94$TQH+vV_;g;X*>rj-zzXhI#XC-*nLx7)S8O4K7(6>kP;28S)?L3%=IvB%)4ydoO zJa`6O;SL@Q!a->h9IV6mxR(cW;rV?$xD4J-=D}7Bfhj!r31fCD557UIOyj`w!!>4O7)4DJyg+>IVQmj|DtCg<_sC>)#5gX!o4cMib8Kx8q22lt`Lx!eR&&~-dK zxB_{_@Zca?+{=Sr=tr?UsDnQ4<3Wu~Or$($i^_}VK{lNC^PnP@cUy5#9hDH^LG4R1 zukxS=Cb0w_bVJQo;lT~)0Es+^N85*Za2Tza#Di7vrz#IVL@QV0fsK)p%!33}T?!A< zQPS!>Xpd&5*MVJlv%|xK&hRIO2S<}x3LM;mX*`w(W6;@sJXnp+AIF1FoJ#P*L#Hlq z&F74M zCme$>V-k+ELCYs(z}_7RP0m_J+AQ z+N=_5PxN^2L_bSx-{Ts~zQ>cek6^>1?LhG2|UL*Le z#GaOYpMsuvSVVZT!uXV5Vt31)VxnWM#A_{kstJ0n#8#F)%>-kt#2YR9eiQUqiCrvv zx(UL;q*!}`$9@8SSM6`vGd#X`P?)OYEc*dZ0t;XT$D#MyGu^UPi%qn*du)D7Jh>Le zxBZo;+F}H(8;u>PdMHUD)2Ob7N9&W9$z)Hzp+$6M?-)=f8=TFVV`e>_KRX4(XjkoaUW|I_obY?0Fj*)RD zCdP^z%oqy)mwz0C{8GH*bb=N425nKOu^3MLWMbgNHpWnJs_nFiLERpt$O^BDDbFz! zj{%Eg$ND8kOts=_;MhmOi77HMwXpSM3^{hJy1a zDJF1p*!L2G;nkSt0)4`1ufehKMyx7i?lLKm zEXfln3Hz>wxo|XsxY6NMo*izDSuHRz9Q>3XAkV2``yu989dlUVeq#W6@}s$d8Ad>! z3$XMD9xwv(ysH_6Sw?X4yf^H7m3h96=`Ju?d3NKO4~B#EhIu|3w!dJWd@4!cF=GG| z2%LT->^n*WPTV}>G!}}$6X76DW6BIH3)}n#ePVHs7FOUt;q=XrW25+!6dPC^_T?ik z?7^%aSQ1WST$tbA4?GtR(liaM2;1Eq18rbn)%gZq4Eye&fmWE$124-!YykqVg@ZKB zhI~70FU4VK2J2vBIGwE>;|W=b9oyW1#U>na1PojYUE|HL?;~2w%0l9G>Kgr7_)o(@ z=0%I!!}c*+%*1jL`07H7-=A-BOV}620vldbABnfgVhP4WV0SpkylC;4u+8t!hq7q# zz=an7Jm2C^VIRLtA6`a_du8$JstA;YgUpN7Rvxx{VucPJ#KIFe6^?LHiuKgALLnwR zV+5>S``P4YjZni1b-@NBP+^4XR_Jmc1S=vNDOTt;b~uj_lC983mqLg!LNzP&a{~xo zBUH6Q185`G2uW7x0aig=B;9o^XoVKBmg6IC5Ag)7P)TD5ev`tsLbug~U>gA~hCXyO z?7I`?3{T{s_&c0Rb76jGG!TpgSxv0oY7zT&Rz@;blR!%3pDqxJPzW0V%d*oaE{>en zClVvRUCg4GR+A#`bTNu86^#U$IkUJlV%tf`;!sQI4U9$8%Nn0=v2MiI2#LdQV>cA2 zCySd{WjT=`^Pgq&(ni}k$^{&UIg<4!VbDPBkffR_KH?&6*T2hdjqe zeC5oOpPUO!P@eB&HxPIr5~Me*_c;+er5f^_z)5B9xxT@Ae=y=}in#EVX!XFu>IzwG z^7)Y|Ga$7s{e97lCIYLFPq^FGcJ( zaG2PmMGq_RiY&$?%Ho>yEj}0VeNT%$QO|)FWN|o$>uZr9^RlWO3=9w32XOt6{4S^2 z+rr6d=%rSKi)2!Aw;X8qgp(ITs+!FGU|>=>nSHccgiBgVGIxQ2husv_ley~)%yv`M zh;RW)OXglLu*gkOGnsq4z>{u@aPoYne=3}O54uizgzHUqgo{RAax7QhH^Rw$Do~RM z*MZi_&oT99?zzRux3VvP9!@?3=i5a%ua8e2OKp#vVnT#7^Tgy*YJa)fJrT~Wr4ddl zQ<7&gCNtucXIk>34AqV#Z$;^*M>r?UN`9JJo}1#K08ytNrHg&dO1l&NeS-#j#iTC^#FlYABKu6KBQoYaKoc=l%rO!en4= z#LEtce)?&|?urDViIhJ(f9QM|@r^-T_%-(JkJT-^ptA(Nhy-&HLjzw&?AbK%B1gkF z=NtGk;#)%lPTUR|Sk8syyGW3xIc5DEvH3`W&~Wy+eVX&UK6GnO;D?CsZyIpoe$<>d zi>~gE1ZkQcltt{?HDF*3cR7EZ^C0vh`{q$2a2AaT9E|wdA#r#PX63*kx%77<1pbZ$ znU__qr6;f{V!w%0?pS+2lKce%Ryr%n@}xL}ZL8ZHF`jgmKGwYm3w$3*=3@ZjJn1Y_ zx_j{z_|@$Y7kQkkt-x=QWG@zhTAp;eUF2~uHa@|z({7WjIOgr6;9Q36H8BAzZaZTr zI5B5UOp+CMh%pp`Q;~I`JmO_JQNNL>-2>T$4sb@lDC({$F>zLCHR?EUu@PdhXt13# zBw)U^l9B?cQQvr+9li=9AW$=!%8QQh!+8i~MuUv8YE;MH>GA7YmEqxJ_7Liq(q z*U%WmM*2y%NTW(wE=-4zZBj5xPvDZM?{}OX&bl0NSy6YP8^f8oaWu$`*yzoo_Ffby z^bEV*mCa|dk3#^Wolsr?3DU*$JWXS*ceq~ z2Wf2tY!Ucnw?G>spk(8?EiX0#YPUTGdZ4Wlu)5vH#i^YUa1qg#{kXjma1jy5ao)iQ zXprf&(a8v`9c)CRJ{$gq)96yusJmI(&dpNiXpr^B+POAr$6$>N)#Js|^-*`Xg)Mog z9;S)F4MsriOv#3DqY+R$vsr(=jey#jjBXUT$q1;O3G530GG3u}^4mb@V+7RBf{P*a zH3DkqW!7*%BcOH~a5e641k}zf<}$ztsGZ&18Vxi8YG)#Qz#t=_b~4$|2OGhyook}L zdMJ3hNBSfswHVSi% z5Vk_QD9kegE}x!dF7u6$W`)X_;!z{udg^PYSYQNPPkqIrK4t`LHGib=xDjwYb&$dn zM!@ydaS98Kfa|Fk+)fTGG6Jrr_>t?tlSaVx)TsIpo-zV@%Vc)@e;Wb4spE zptl6sNuM(UdP@%q&l>@~RM|Ip!?J}XqqQ0g`9CqT~ z*J|Rxq(KOz&3xChPb1)iYj8%gf zeuw|gk{Ztpjz;Y?%&MWrsOG@m7i4haTn3@FT-{C?0Y$i|)DtL+`mVy+;X61>{1r{> z!hny3JrfP~K)}6uNZHA=a7=px#*h> zQf@SPF+73JxJSol<$y7H{OWf~f=b08wJ^&9}d(t_zE%v0d zi!Sq|IM*icM3bAt!n2-q_NtAZ6zA$>i|hY8o)qW8WUFiNT~CU0HL@+5+y~9}o+q9C z#)?UCu1a>hiDF_>oC}g4qRDNLC^jaYeWNrc#knv!6isdbb#Y8O8x(K4INSD*;ht0V z&8#@quaANg^RtPmVa0vP7z#l?g*i|W^|E!GWPyx-x=Y+iCZm9^y*S5ifuqE(-P%}z zr8(LtVTAv}A-2p2mebc4<@jzv;_x2EJ(c5bF1E7MJd+blK@7X%%Q^PfI1IhSiFrlN zxdr0bRS;Gh0VDi0g;$M$+1`6Kgw;mCY#*So#t4}0t8rkxZUl^HObXBE_)gQS)!ae7 znB&enZ?pHV%?Z+9dbKgfz6bL`=#fjIzbgY?EJ_bjc+UvPb2^0&jDY3Bx$6JO2vx1b zmaRJC#-$OeU=&l>Yy`Z0R7~M>BX}G)*X8(@!h`Th*2~*+^I#zYTXKRd0Ozi+bL~zRhuW<6au@1isAi?WKV`IXmyjaW}q`uRvf|PLQT)U~i6%Pxj(o9WJB;zZe7P z4KT1L$5$6|;Z2t#?k5>&&PF(p6QpT&h_W1e01e#Cb>uI#KkiI~?%>RE)N}|ePRSJh zmJk<%EO7ml?Q?y7 zY2bbqyQ2)iQ!CItH%QYoaDA>lkp`O5%^S}*&@r6JTIat~(h8eNNBnlk5A52BJKtU#>g%@XljkNN$j(>A}ccyYVG3a37m-RBm`N zWan)m-d75YH3IfLPjP28&Is7z1i8;0Zv=P54a@ai3v=Pg=p}&>xix4moZS$C3AsUf z!#wZHwdXO;IWITJyl8P@uH6KQ zLVP-C;7MZud!z-t82YynTpt(Y`fjGhmE0CRE{iwt%*DAu=0%IkbL~56u^MNm=Zt}P zr;tl?eNWLqHddp+GcwSRi^vPPL7Hacug%u^M7~|8+w(x$Ft00U2c$>)5lG@_C-h(n#kGd{qud?kn3wn1Iu|W`i^|O zhu!_d+#pTUz!$mp92z)6!&}c82$fZX@TCNNfFQIKy*9Ajq(D=3XXAfu1einPf12xi zjd?!FN#ir+$p`ZWcIF1@4fFgl*Z!G#CUDC7Sq9j@*3pT5=UemX6+^2X51jDdK^rQdRW?P*{shr>Y`*vH-HU%5e=rhyZ=_8=N~ zhW+%^`38>V`W~Qxd2FQPGH`@#dL}nW(=-s5Xa9!=dZRlA{CVyQ;71%PB__}JDGmI< zDvix^SAfr(BTywTNYgZsl4tLyfiV&2HO@DXl;=ypKnbs8D_4_&-b@(D3(_g1da@Tlx7H7r$ybw*(K=ZsR&(pveULjp|zJVrr_7^nJG7fQ9$iTg=5h%(F z(KOv`kmuWr!&-Es7ERG=yFA-!0IR(?;5(dOuGV?Jx`+$^!v0XKa&6|s(vLGU=|Hob>m%s!V9?Ml;(w)IkUJwugVL|;yPB(j7nMTM<)x+tds?xSQVIceioDS z>@CdV80%)LvgpUD>A}1ZGiL`Fljqxq!&)p#EoR1i=jYkAFGIeYxjk4=srJ%2B|KiK z_71XpKXHET&B^n%!`b0-w*Fkz-q)Ow7Ul(+8M9cDXHR1m_i~O{Rw;`n+;sn^QWg_9 z?w6mR#Z!5{7nns(F5(s|i(=Nnvw1;g&MaQZvwvk4e42M)Wu+{x;aRU%%Hk)s*y{7M zcp=Z12;aiTI0L+-EKYK|T$2}M=DZ@F8_XBkeRa-pXb@HFpHBx=v$1_SY>B$mEC3p+@u*^ z1HyJA;A}MSCwac@%z{sv4s2E_#;~Gx=z@ret(nan+2D` zLwRNKo&27GwI^^OFUS(n??3bGXX*DtEZkvZz+HoW&+~mo1MF{sKV)De4IIe}(lndz zRG!TbD7ejc#xxFYBstA@)(EEgDvW?jzUpjGD_<>+`;Zq?@E8I2Aupv6V+358=2Gw) z0auAvQiwGIu1wof@EHO3A-hwEGXm~I-o^TeHv%p!r%~`50rw&2P_T`F`;dz$1dM?D zkjp6qjez@*t0*KG0rw%-Q%E!dZ##1COELoPA=YaRp_&nJ5AhGCNHGHXPC13@MnK>3 z7C}fg0(wRwg_=e{&uGf!F=7OaJB*RzdA|8*qHq%1_=LttgwtQG{2*JH9pRFE`(3u< zQ|z8u`TtxDhF)UA`bNNPh9Qxe@7qs{PU1TG?%v?~1SD*jA7oy%n452Vb71j%&J6i7 zfOoWL;PQN57UII&IrlY|f%`d+7v=|Png*`Qw|mjREE+C4XCQQU285RR;l)Vj@whHs zk?)&8i^B^M*IX8(C|sa*evo<5VyArjQCe)kao}Dz#=p^VrXC)nwth{Ujh9;=M04SV8y_*MxaZcz`xP{ zw0MT~`?M_9p!w(WgUpK-SLNFWXt5u=sTBd;+QF=Sxz<$PZi?481=xq(_C zi(hfnzm5(ei*M)KS0FyIb(@~}Se`L}k3x6u+66bnOowoX&71kYKD77@`{+7Ze2LBa zL4J^V(Z|p7?O8ZY7OIN!$|`93cOa(FB|#@Djgi+%CO{2=q z@Dv-sla838*3r<|7>!QI$p6xbbbcKF*iuv%ML+|~kt z1_dEzPCt?he0`9p7Co=U%$RR(fn68#yPI#msS1;Cfe}o;g+@UAI&Iq22&PT1FaqXK zZzeowW(3TkeD+eHxe@T@;lFA_xY7u?O){9mRYt%EI@fc+UTp;I1ST*=kr8lFhoW6x z;Ol@=gngVZ8mrMZVAmFCSrBBQS=5dN&iC0uYpX-=Yz&~N8!2=(0*d+}h3-Z`QAcyC z?_mUttM8ejml4pn_ENac2pCttQ@Fth7*~H$=xqdys}mG%HUhdMA2S!|V+4$=c$6;C z&j{Fjg(wU#0tQ+tg+WHZK)aa2U?X7jRgc0@BVhA&IfY?Hz~-xv!U!Xv9j~S^(g1hnHUZd=A00qyt-h4DtfYWX^ayNrOvaRY_Bjeu50I~EuCs^O9} z+@1?(JGJ8jTrElqf^1=~;WG;C(MS}!hlyquoLj?tUkc$tBf#$mnPQF+;N~L~9x(#k zypqDag7ZGQJGH>a>*8?XRfxO4z+Gz9`1w$J~9IQKFAaw8v%Z|WQtFW0Kb>9 zhCej|{NB$ioXtjn-!E{Q_{<3K`{HZ}pBusT`<(*c3vemyr{A08_i9X}fiDVzED`ixzD@cSeB{jCw;_m}khJ0rmFZEUk$MnDfhuh~}M%ZB}M z5}nvCC;C7M>@En>Jvy5nhMc(5QyZZ3N``GHc?v5s>FucC>OM zpy18f(M}iv4YraU?W7UVU>WRar;LCG>&cFG+6Zog{aN6<2`+^XaxZmQejnmcJW~*4 ziRgE1q5UWQ?#1SaD?E1@*Nn{(Zv^;#lqvj1fZy@#SGE!0_lp$pk@|%&&C9INpX_Ks zBf#&Qx&25m0{pJWj#kA8uHROnFQo{6AEn?-w)04Mgcqh%QZPQ1xeE;WMN(V~UEDlL#_Yy@$c%JZ!h z1R4|u=?(MDDYO?OQRwC?pywF_$dhUy-w4R_-yR4BMnIkwtiwVhpy2aE5SkbP4Ho9| z+tdhXu=mp;Tww$>*jV<>W=4QZ7$A)beecunPZJQAEx!*jv*v|CmWY10DzvX}Y5Zd$QjbQw4YXswWJ0lps+Z)07-N6XP?~X<=es?m0>-W`#zPsU4csu=WA-~(RPC6F` zSt9z~v(SEve$VAr@A2G6s;vGQ3WIcyPRuE^Q(D6b{zO<{ zt}%dqg+BLSp|2_8!c%GBVHxl;r}>3Jnx=uL3hn7M@MskJ)5ZW?dYHlz2{Gs|?^T7c z)TBUv*~yw)W(1f+o{ty$USghiak*TmJO`l41OF)u(i`Uaa-sb(^UT4PJFvoJ;a-kE zU+6nT17msXbi45>#7fu$R8H;Wq-z&5qp+){4df)?D zEVmK(yfDPPSQBdsef+$CEjn6@wwcY&!YbQw=w|b6rEG##aP}?|dq-hn$aT2$Q?buG6lrHWJne?K10 z%$YN1&YU@O=FHrY{0AT}x~UCi&soh}*o4dr&H1EFia%}6T@eOFLEzsN0qB?z#m_Ps z|53ANGmsZOvjRkZVo_YiCF!;1e6~f#pJ_IC0;!CQmXS7_`E9f38%XBGBDhQSpR%U7 zeQ*T@_B#cDvcEhZfZr^S5Yj(Qg}3 z_dhHx_=s4So3qIsd2;$a!<~vJmp`>G3!dgEfa1xm0E(w93!r$)RtOePIVvxC(){LC zXl~Ij=zu%?a?Ks&+M4UnCb#6N*zdU;Ncn%pE+lJ#A|U7ET)+8c61ad9$!ihFCxJ!& zY?3B{a=+)NBya}BxYWPsIKUJ%M`p3#%<2Mx%P5E?{$iFba?xK{?$0J^5?JT=tN>E} zja2ulOb%B0&CMimJ(XyU#eol&AgjioP0}Q=-k=Q30ERjo#|d0O0U+0C2R7R(kM_{3Cco!JGIb34mgScWFB+f&67=Vj zT{5-FpPL&2Qz0UCD*|BZ`=<*%q5^@SB}L zDq~;ENSno{DlztN9 zPXcai1hR%K0@+*}_G0`k0tYevByckg)Kn&c0~r5JATZ7$AGZix!bR>7#@`}v0mdIl z`PJ|Ovo6Z)!eNX*34Cn@%Fee4{Dr1^2IG$scHwHjXDvywjge(j;(;-*XQMTuaCGHj4m;f>OWHZ+@Kw&f*++mqp;ScsY@E)Spe#B=CN} z=Z_??3~HZskKzFOHIL@~L#j`b;(Pt(lFguaD|PxVi{c$Hp;`C&v)L9YKIHeD38efH z+LMndicp`|=)8Sg0ie^HIr5)W^A2Rd^aFnLQa0iCpzJ}bi7AThQ~qo=&L&RyJ$JH+ zDq8Z-DT;F9KIS(+PXa4Uls#?{IGfAz6aH+HCV{W}J-;G>pJfC7jTC|W7y(Z!fK>4( z{pP%GQ2h6Dlzqjbc#yq*#-Gi$Nb!4qPc4x0`)T37uLww%p7WbqNZ>zN=Xs03bu`s4 z__Ilx1YY)gK0yKj%Jx-708)C4D*Q7AfI)ql^YS$XfcwBp*I7ST0E}Jp8UTKw0PsQ} z*dP1NeHJv%z{IAt0Q^M(BoqJPH+O>mqVZ)Y`>n;q9kiZ*^=FekGU00RoFEg2ApR_O zOKPpz#NqZR07Mhugw9p~Fmd%#0CE%nOx&;zfLsNTOgLK1pOT3yXk(o%a&g%U2PP}O zC7bM#iQ*Q|(q1re4=2_FMF5f*rt}vo0GRj!cSMU600M=u3tP-C)LyicwTrAK&SgJK zTe8_Wn^@Z7`4pS@D3x=$B7i22Q2Hwr08L!NiLz1wApN`9<|+k1$8VynRx1EH{tzeI z8U>IYU(#Z}K(2nX3T5RMSD&CkSl5zGe#upRi>I#-TwP3xjfw!cdXh%HNddss!ZrY! z6#!hdRRQ2v0C08NasXNs09=JgW4!`MuBuziX*9TKEk~f%;_B_xrVTCGXOt)w#^Rse9-%*oKH0CG4^Z!y2aChj1|0jr6R)3Qfeve`JBh_-mTqG;mn z?08HOKod`q>9_)*i6tbHPylrN7b^i6PylrNPIi2Y0-)pFq%o)fvg6$?<^eRg=shb? z)@yO~ODgQPmTdA%u6DL~t|nL0)cs*a0J9NVwxh*-fCR3mu+Fjwd}B2-BQ4n^O#Qt-vktXnyO5E;0Yk9(k(|Hcr*l}L znC;F_gBEIYvTm>Q+&rkht#L=4_hHb{O8B*a9QoDp57voqXXMGRj^9(~eE=8*CA{We zTEc7fz7pPAUnajs{z6^haS&Ku!i(rDTM!9X%vcF; zQpV+%(*IiTy%&;A$giX0>+|gM&Jtdg94g^`$6fNP>5FB_u>4YbS%de#Josg{l2vQ) z?-5JBfzJaayaYH_!kc{KCA^L|A-}S|Th=@%zpOseAmlh%!uxj9CA@KVsD!u2&Mn~u zuk%WH2kWr>D*Gp8%_H(l?2pKr=gTj#f2zTIH~7Awgcqu=l3!f^QiB-LYvotgpOpAF zl<+>(P4X-2-)Rsd_O23MV7j@4*MV;Feib8{^@ha0wS+f(ZudS%n6FXrdbEVMMeZ!& z4Uc0byryy7`+H8>aHF91-V$E4c%Rqc+>A9A{yX@(tAuwa-tT?D3s|zzy9=-nl<+#l zhrIKMcc4*7`aZ9Zxv@s?W!d-#h$Xzv%k(R=S8zT98R zH`6DKqK!04e{B@vd%`H?E7~WGQofY@no-I(j87XyUBu~V^4>!7Mk#+>@2w=@kIh;73L=lQRGbnzOL-KR?JVWVR*tjiY&Ljivlxh6XDJV( z@|>mO1j$*-bD#oeDNkbNI*aZgtG7wiLT4$DSG>-m3rOIeX2Efhvy=xQ#m-WmBg}V} za#y~iIRmc_FA-)=;Z`iGlAx&uBG^w?aLx=GuH_tGs}40p?=XaBKFrQHuo5ZuQgx z3E$b$vi4`z-_vStVf_i1!K{5&eLsnfwPuqt>mO?M9Ay0<>Yr!Tca%}rvktbJx3Yd) z9;!@P^~*fS9BIuaW!Ar>)$P0Fl)TdSuINO?ije|KgF-qmUjvOZJ; z2clN}UoJrAUs|(Cnf32(^-QsTUjXM8AIN0jSgUzE30&Yro%dP<=#gaI)0$1vB=C_| z&l5=Ii?_rdO%cf3JctubD?bOVLZtV#ny-@JQ&i~>TLhniDbM;?Yc`w0PZ2w^wzYbK z+hGu>8CnU4*IB|ra?79Wcw4LY>shc^B@}#H38mLjLK$>Pf9E}|-mR$KUCMspzuS^K zr$Z`b90fvM_iHY;VG@vC40E3KiB^NWEpg)aqyN1IM)M{tc5`%?PtE!5ya$2j{-7Tj z_f7b8y7$gS(tQx=9CtZHQsDj;tndQ&43wu-GamN==>=m7)r!x?$JY=iow5nlsv_8p$~=?=OJ3ccNL%eJzBdyT6Ur@zb44Ape{;<9Sx#4{}JZa)NnPX8?5^ zvr=>8n}eFe-HlKDFP%?QK3#?f#dEF$qgI8@d6%)m07_8-=2>_DWdW;QiIvQ7Ux;ov z-Al3Bn(kjTVfAo72-0)hIXciaqjC<2ZZX!A=>6CN&T&w_Iot9+L81?WoaVU=hC@5y z34oq9qZuy(m~)nKJ*)g+5k7=CbB6MM#45Eg;hMXHOPOY@z>=FYVtft-zL$NFXU@KY z>K&R^emYmDv-3^>7yq}Z8JTlL##v5tl(S!C+~s)?Sk3{F$`2LuK zrg9Dz>?6s)!Xo5MStK7vPjjYyEO6py(N9BcJiHdLLq;3Yt}%T0iqZFioWlhlM5g@g zB`7_A9t*VcudGDoZ6X61eGhWUxxly>MN8`;ww%lId?xh5opVLOPgr*fb#kuqavZes zDhNO4YA*}e^e+*+m|14*L!F#!j87xuy9Uh_<-D`t;F+j$FEk?O`Yfik^7C2$rrhh0 zahBImPPY`YzFShhRb+COk525@a&9ZU9#smKk4_%ca&9l=Z?euUA6Sn%?-nJ6G+u{h<@}5BCxUMVz?W43S3T#>f{V@q zbFWY^_ZHrRv{wFIO8n8nuOZ_sKaCRqQsHaJxXa&YL*~1Mi;{@SA7SraDm)#Tf^z;O zZO$(W6UY>mUkMwS^Si<$$Sm+)?m))S1%*j!&d4p*3-1EvGVk3`#GG}q zY?b#6a?v1j>u?JUxv*aNIbha!$BEe|%No2*F67S83tvW=Ut84+Y25^NSKiK#yYK-S zJj{L*TH!p7-n-r-lI**{XI~}$b3k8de*pafg+md{!a?yfsyH95&njLy4=~`+RJd4P z;rz8iZ?MtVOC)Nmi_i+E51)c9ic`=8Fr9*eA7U!6v|rRyjK-dsIr)vyYf|Vx$O>|cGNt7|ScptqWPIgcfW691h|IF`sv=|tL}pd_V{T-&h|Ie3 zTukKLL6NB`Uk+8z-CDwKHi#*nyIo9ifB9u>=ZwXif*ZsX&)u<@^Sw z3m;yB^vI$=Km^4fLT|g!eX;h;(N>>b3WUAgLk&V!0*s*M|$-yDA=dU z372TAn;=X5g|hR3Eg@@~AP@beMXYb(?1c5#f4+c*Q9{<?7DUM(6{JbiCK9w?7zMwtB_NT&tnMs(LKZXo&S7{0*ZR~BLk_4r+Q>^Qq#+` z@&$g)!;qQ2JZnD5J8qn=JvM_Mz$fBP1buCm=PSE#8gc&&^Z|f&g!;LcNE8S0U}`kS zt>(SNDnkKRwn2o3HOP!1u^*wa*{b4X6)2tN7&PlT0K6LMD-nS6sTut8IT8->!Nj}G zrY{26{0u%|O~~3+Oz{KWtfp6Gc?4^BB6Ac$u*OmcKUOhutJ#6h3)UV+{-X$jwI`AI zB7$Iz*iL?6w%Dxw1nD0kSgbvWghPBVk;xk7A7_e-LT{-l181*#FzPs@LC}vr53n4I zS3T{-`7^-(iBQEw4Y*sms_{H=IYNyas;|H1DdDQ&xN+b5+p~~=-6OR3Odt#*Xs5kx z8K5_MU~ZuyBy;q%5uExA`H;NXBi6Zh0`W>x6wTb`5sRmu*ua%cf43)}OW7At{waj@ zLRbF9<0F5|99S$6HXg^kxokHkjZm6;v3#rtt2lOMr`7lWZ z+wk$g#hCpuBo3m#9ea?t|3dbn-{EeP9nenu_)3r%kRqM{hJLgki0g$kw@GO}0fL`H z2nm^P_joB&Da##FmM@_6d4%iseQ->W9k+g%&j()-Y< zI}z4DvI6DTx&$c-;sk-;!H51%3Cuwk`K_b%cf!8wH%VYG09^z&dI7vu0zUx2-3Yap zKoGQ3Xc`~ax|Uyw=Ih=C=%-QqDTDw^8jb_6rgu_7W%jyVH2Hm zeaac2kE8c*qOY${I|KA~^w=gY<@zCKfPRl2ms9OLr!ZR=q4os`T4e5NC_FvYBo`t5 zsByMx@^oh%o4f_cHzG(X0ZHXi06u{r7s{|xE|i;(%*f?IF95Al(!)Q9`QRwD;tG`f z5EcFnq2VTEOczQKy4{z;mJ*d8)C0$TW_KZgs|e(W0N!tEev;onC_e=GolcJ+O^>>P zfuuJh5mBV0#OFsk=>&oNP^7iU1wMevQqtg>tsjlp(kOE_P#XI{cQ-;+00_VzpfmhV z0Io*RA~(XU>h2U3($|k3x2d?DVi-RHrPhw3Fm4pk4(v>zNvZ{&J7o%#n; zjY!^awj24N5o9Al&^jHVs&XUn?=gb(!uJ8No4}ft0N!f^>6O0|fU6NCJNHR;9s=M2 z1j){W7CWNPFC0o|=L@jP`pj&0UbESmF@$=42eiIrH*%?LfOPq6(x0(Omm3>M z`g$P017TAWEqaBqftCn!xEtGLeW{g=$%dE9hCc@M2N7h$D`msq1>oBVS|p#k_=>|; z4>@xF1FBE2IGWk;Ux54vgiZDNz<<@z%$*h*eudeeIhwiW(yfMn?hwjTfiCe-Qa1cc zhftnQ0D=fwWDQrL$5IW8IeGN3-SA_MCN_KykoO{N`n1H~#(f~(Klc8$1My|DzWzH@ z>lDWBGRdzr)t5V(DIjU8-|lEW!Hh7~S2&t!s=LI}dX;2Y8r-WTqkUa`6{8<@cuBjj zi!adh_c-R01fB}#_4w@l5I*!mi;1BL#YCY)=$B-o(9t895NmazV}u#mZc%!>^JKfx zeo*Q9TnKd6Itot!w*wPc`|e>|5#d996LY&id&!H75aDkw{&(s{i`q6XtDp&)sa%C0 z_w{C9Jj3Gu2J7V7Yea32p#9%e{>Pd)xoOF`=WpTrA8Y#muy-f-S_&LKF$NV5bDtdi zK{@y|4P_YAZ|L?6y#VTjCuRK;~=y081LS1M&iLPa-tzMP?7U*on|Ejm%9*+xxNGRrT6w%Qaq&V_9`8^zpv1TkSm0uu-V)UG+-oQX7GwU~KJ5u~xZOiF45 zfFwd~=ZxIiYlt=dy}D-{dz`xc$lZkE8xZPtB6BYi?`I}~%ri(lh0y;)WZE_OHjnV* zQS&R4z;MEqeFLSxA^Puuk&}xf2!y(yBU6t=EkdjxXj@QCf1Y&@n{{Uc(1nsPQO`o= zOeFY=9Y8)d0|$|Kzv9QIO|kXoJ(CH9ex6FO)VV-M>8<8Qc7Z1n??&k@2muy|z5ip# zJ&F+HhLUw$HLPPDNj!%Vo`2yv<(Wj?7iX~60O5BC4bLDm7anasy;@6@*D4gYFls6-B6EhU$ zgGfApAVhgP>gvZ?*AnFyQ1W@AQk36A;&}v1l*f^9JVInkl)pyVFA#(%S?YY6rMH?h zWP_qC#%fxK5MV(wPk4j~iR*fWxRwY{15Psn9wEXfkZ_0(Cf;od5uOEv9SA~%=OQsJ zYxFDtlI0^h(6UyUT#IhK?iTxyX*hS7oR|&I!=;j^DzCeP+z{S``qv^<2_N8B?jU`D zuL1Blfx;8`wL3^ppt1lbbqMSE{}lA!xC=;Y2LQbYHD7lF_*)5d!A{`Dg`76Oa|;9W zc_4j?wZ*p8>k&ZbT=WcK<5j3}CCJGY`A=@|2~udC0pCxZhkuZXA{r4STR#NYyWfW0 zh7E(MFtVcW)mk4y5$(%UqNrc5k=7;n2;ejySl~&w@*H@A`bVT_oG6xcn5;)@yBG39|zz;1li+nNnmjy zUN0cD7NA{r?Oe2Kb**iM#b;|T671tqyAXXeb82v=skLrFA$$38QP_{swz|2)s;*Uj zog;Ly>>z)dKPo!N=41yic1PI3YA~`Ip-MQOGw#T9z#9VK3<8Dwd5Hw_|BJp8Vg2i{ z`ub(=yc59uEC8QDkiEV_cJQYF{2MXFINv0JeA~7Rq4h~HLpJs!s8!*6fOVm>*IBUh zP}1)_SKGK8{c=pA){lWfaolIuN)yM=P)Kn+AqvyP@hcRFQLn6A2&Q}GVefCDY4;0p z(EF0&=#_`P0dUxYAQ#4H#$j(Fb=Z4k276j3NN6CX4`+EU1R=5MO6m9NybbbgRX;*%x5ujpu4%G$#O@)4x`#vd(VtF7{Uj$r)DseDXEDxrJ0Z0-k zoZjL&qbE@LDgZ7=kV>#X9!Gr!fO`?vivz30^1zD!lBolsi!W03G6|GwvR+m@1Et## zTD!p+)#P1rKT3nvIs+I_8$Xx^y9O|h{bvP?4#iH+g@_is6(z!BxZ6s!JzyoY%11dn z`sE4D&mo$GkO6%ODT98qlSeiDry^qrvS)F5Fmn$8#}Opo!xH#I0Qk!Utwm^qd~XIV zsyF%OX%&@spA8erdxMzE%TUM;%!tC2#ad%CTZ;8kUn7}44raRrvz#xI*){T9>Gx=! zzjPp(T_^ckUyNyoAelW)0zV7DXAoNN0W~uFdyBC{fISWv{jfsNm-7?MI@~juxhNs0 z>qH4f9ktBPvnUaw{;`#4qfo`ni??BY)1&TOo-nQxoKqB4?Pwq1))N3dkMy$$(g;P} zaRUDWz#kCg9ysdWM<5*O%8LRNhexbxJ3&;gYGlk3hbKzQRxuyjRD`PcohI;ySicj1 zAVSS6uuu9rkM;Uye_{rNVAr(uVn5j6@e=!NVD3Y}M7Xd7_-iz@3{h+BIgQFURnz~4p=`0Gw>2vwrn z_d3T2hnQ&!>Fcz+9@RQ3h-V)&}wP=N`avH@uA~CI3EV4 zuuRp9@Gb@+z!G7e_-i`-2*UJL5uYE>4BI@_5y%e#q_Qf{l=mfSATDlcgSt|@V^vT=FV zByl}yxGS+z>)(=A7&~+AX5i~bIb|fv-MradqVFWQkn@~yTNBRi$637pGgv5z1 zy>#KKL)A1L|1SH8YUDzYJAxqS--X06MSmYj@gtr7eggTS=m#%CM(Fk_O zllAvCr1;v`egch1zV^i>UuTiYM6tompRAE+=36_-*BKVwFJc@W;bNoT#tJtPOWU>s z*5A=oY*2)ikz&RzQNh8rStA z%(b&v7tMD47SeFew=zFBkXaxzTKGF|Q8T32GD){8wsizPD5R6 zgOzuqcn5+YdmM?|nPG!3An`0SWM!=n=N1S75@=>a&1~ST=kY;M!*`Jw1wssLhK4cO|M472XW*Uh}gkURL;N5eu3hTMlLrL~E}i@e^jqM;Y9M z1qcD+H?zrRHgy)yg9&PgA<+kfPK0*8C?|F2K2jfnye|ag4ixblD0LIad=rT;Gc$|~ zf2EiIaWp{uhHC)XhFl1t;WlKRL*i*>?ncJ33WO2FduodKb@WcUcv|aOD5JDJZzqh- zolpAFtzb`h-K#~3bz4Ec?H4C=*PvWjXAYP(AV_KYTzz?-H`~Z7$s3qIS1-Wibu81e zvs(eeL@L&dy!F|qWw&HUu!C`0C2qV0Y}5#Gtq{>1r*7o6W@iISV(Tb#uR`Tg>>)fN zVL}^4!iBqB7F|=)%@Oci9E^JP>}*f~oD}kMHN!2l5pQ;OZgx(#AN2A8CRd_%3S2Nh zqw?JJ%9yAiZKg=$pA4jEkZ4f`0L;!yukQz-Sl1(7vNgXPovucm1tNi>g$-$PI(^{= z823f#^l)D}7j@VU_6bO!&SJ2e#!wmIxM!RX;lly&LZCtv5Ix&0x5$Z+Ae{;#vIhR4 zpc*6WB358bms_0MxGU!AD;JW=N>enlih0?W)#;o&uz0LV2b{i;ptb3sQVid^2Cb6= zjR9bJWfho}S(2Tr7rNRO+}18ytTNN&?3n+_b|_di=-IY8K0jqT`v z8w#|!`Yr7X$zy={FgrG@N+>YI5|LOPl9*K|l-@2D(DV*PygngM+`Uj-Q<1vTyM|-> z%wEkJ*G=hlIb@q{?yLc^2CaKB2rZ-!soce9rqUY97 z$4-J`vzFe^jDbjGL(+v%-huRPQv0^p9H!(tXwktGqDo7awxZ9}TQRR-!_#pj25xw$ zxk!ngVKrq{*imK6d*wnOT0XN1W1qq0S=oSau#*`@SnOm0rIGQ#C)RW=$|#25)Nt?M z7*kti0i(z40wk|W5)jM2z?`E^XOy<14zScBAW{65ce11z-0p2Q?iqWDcx0a!M>!bG%$oE9TYMsd7b1l>=2g z@Xf^CBtK#g8p~;$_!WMfMWLsGBtAZMH$E72aX4winJ5hw9Rb03~PC zj$mq&Gc&1w>%; zbG6COT)y#l%X8Y=^R?eCFZrEzOmS6!B4v&L|*7`Ai~u93gGkb+KJyw;fuy zZAYZ2RtZ#F!ElKJ00QS=D7uz6FS7CRovpN@?#v<*r%W7LmtDaWcM}Os^*pCCLHU!XSbTSexN&y14vt*XhG6YkbaJrVx zMM^vzIE7`KWrdp~ac|Z$jI}NdQy3M~WMJ4pn~H28^_eAVL>a9^IJrwil}P;xDXj&T z@*&6QG$YC{lMJQ8=Pi*W3Pm9(F=BhCru3FbiqhZIoJ8tRXT0B5tV~Kg1-5$^vyuL; z-n}JHe-|YpL*k6yT;gwuWSA7Ae7L$XMN$r}$?lviCF~z=ZO$A;4AlNV+FB`C%+xrW zXC!crM3FNpLy(9}EtLg~E)Yq34MWa;WcB{^>ix%3)%#U-(mh!RNk&qLrBjHdQQ#?x zV1N`-3aS{eR&z$=l1TBB2AT>WoB2EY>9fefAwfz!RGO0?A3)0xs055pLx5BnwTWbc z(I%0MGU6hK^_S6h31vi!4Je~g31uW*h{QCK=Se6dIVcIFtcPZ}20{8ETXrM42Z1ax zmiSwcvYxXMPa=R%1xk+#Wf7wak>sJ8ygRK$*~jloC_YbmWL@FCvXUHprj8S#A))a-d?2C@{Bnu;6B$ZW%K6 zLqy6DD+eQza%zX+3?m^PhiF0$uRTr<6#Y$2q}R5+RbB8ii)1>`#$-FhdrJ8Ry}SnuMa=}G8$`07(QyPr zo18et#M20JvNI){N~AZHxi+L4h_M01&&lRra&$g$WKaG{{K#fz(2VS0l=s9wiU8St z4ACcLlF{QLIlyj`?F{3}t70c+1C>yDS1ex^GFm2*gN%4{OAZH9dt?D4is|HWN)hTO zA%&DF;S^FV9qG*^TmV8o1ayZH`Jgdnyh(x?@n#t&7^49R-HPZ8nPjv}ByC%W1`Mq}kkOw-a)1#zKe^NRbs3b&8vUsnTheP}N+7*PELCG`dX02(JOTPoA-J&! zdtO>rzx))FgE!EgMF7`~c(n}jVDzel{v6TkGRf#aMKVnuyjCWGv*dwW8HR=*^AWTe zU4bHiS$8a+LV6PAN*+F5{&L z;FpzF%OoRy9TKEu6@Kzg8NVM1)D)1Ze;M5J2Ywl%nJ?W&mf%WIt1; z$N@uq8AFRQ@*!YA87&jZD5G@3 zoJ>(fjL%2VwX+yqgJ5VEU3`oQ{#S0mpF%{AW-DtcU=;!-&WN}BPO)AoEPGi|xNp8* z@dDs4C1FPYf#9aAyEOf*5?g`RJtpK{g0t1IZyFA*@vjDCe62bn1cNTPrd zhfx+N=`&{SuOUFu87ZX9p(4`H1yYPeAwJ;SnoKgh`L|wRL>aL{hQU^g+zbjXlX#4- z63GEZ?~qVNw~FKzM)!-PeH_B3@C$$j18TO04O8&kHllgn0iVUFjB3?j-^_S0e;d` z1PIiE5u3qTN~*OuTYFJL@hP8-vB&}Je|;=u3yL&Vi!42hz%=6*5i;kyP>@1^*%7Nh zlCdq6%;yAj3uVFj^27)U@z{0KBrod@r0Nc&>SoH(uI&S{lhuWUD<(DwK`tg|TA9N*EP(kaf}qNTLIlR^`p70STOP8jt{=Q;~bC=}X4s zh$-G=P7t%{tw&1sCYtKaR#ih6XVR*M6}KWzAi!KQxr#HamS zfYc2L7-}`=k+h4o2ax=PD7W<_Rfr2)vWQU~0{ayecP!F+a<{-a#d4=?Vt++i^^7YT zG~%qDDK7x*M=}sgXCRiwfEZ;(A?0hS>RCwq54u1FVAb;xsFoKYK5C^AiAO3)0n%KQ zh*gDHHrB7$eMX08`A_}6|Nr5a?*IS!lLEGl5?UZ;g`5jQ6{#^)=9sNBGAEJMC#Mos zA2X4Ws??uRDbt&k^Dk}Iu@Y8zrJ8B4--KaCscOZg9n?H079C?#l7KK~Brpf8_Oncp zu>mL)4|eo;Nb2wCrL6Q%;y_r>H}AbmFr4{8_GwEwOBtVu0GrBamq;cU@zw^Q(}*Pb zD5Y|>gffzLG;tG>w@4@>zVLug$A~r}!?mT6*n}YIZMhuDD-g&BV_9_zQr2?~Vv?c}zy)tq_y+#u>OIJa5I^EZvMW zAJ*q?iRIjU{gyze-A=}MUPRc5{654yejz_R(77M+aa8U`%!i8;PmvNLCv9#UPRKX} zeC|fz0Uz7pnf3&Mc-TJA>`9-Gg5Mys;xh-I?02CRiV!bAScFi4unb`p0(qn5R*%9- zFRMWzbx6sJxEwVVE=8K*as>5kK!Uo~o))$vogV(XdQ=_Cignb}fkYPq+fIk4NF>=SuXPaX7^bBkN$7=n6=9N2gw@Z6*cK|LFgZbRrr zxEA3-1Rni7hHwJmDTJpH)WZ{-?<2f`@FD^aRT$LKmBOQbHXuBT@EF1~2+ty@XAu%_ zRlXkOA4B*Y0_&2Gz71xPRyAyDVl!}R$G)P=hh z5HaBlO$etdzY6p8PK3`PJc%&-A!}{~&Q;ZJ@oXgI6`m@}LV|OgxC{#rN)go4iUdO& zLKgz{JBBd(!H|gd6}?lHr?X976)t7OwmC*+2o(tGA#V(`aa8$!Bq(>v>;i-tgc}gj zAJrfBozLueodo~GcK&(LVW5p?pl#>F_L!!PXV7578Fn(p^CAM%wDAnI@eIdNk%6|I z5BtY-8*Dir%8zN~*c;VsD|Aa3V>3D#K zpjTB@PYzY@nVP7cnjEg4Ozzn~G_^0eZ$hiyH-2EGdT9U1;p)Bnssod|4~>qE2gfHz zDkn$AMy7_Qsz(k_Pco{Tnm)99bUZpae)h=l^i*|xVrcT5@S(9}V&CZ4-st{AQ^{DM zsi#pjG&(k1Jv1>|ji&L(W_O|a1H*^V+Wvo1yF-%)s)If8NIcmn<7#%LIx;rA|IqG{ z^hT@pj}H&+ub$dBgmSy9bxGOD>gnBpS)Z({sjE%a)(}_; zVCC5O*huBb(5}(S+M25RN)}h4IHRZKnJS-a?KX71tOcp11kL(#bw0}A|ePm)}3NTm{X#4Kbv1w#rabO&* z3Q2SdFjyKAfi5RU4iAq^OplI_u_D{TtV#|asINyBZN-|yocZlt$j;F;DA@GK0hv}T zOOjYI6ky*35IitXCjP}64XS25X6mMiuQ(T*y35GYO|NmT&vb7vO_$->1DMz0giTA~ z|BU$FBBN0EdW%@e>%$pbI>ucti7`(vdJ~NASQrI*(Y#YpxYJFZ@+41Vy1Bq8^qIOb z<`b#v)4*J{xd24;T64i#ZFoK67oASt&lzmeVjxj348-9*iPXFpc+I zTqQuyNf3y;jPJUtK)cMG&z`#QpM^5pc;X*x!&T)JU3w8z*#g8cpJJ#GVlXqr@P-tF z?wV^X^#R8?-)Amy&9met#6N5N-kuBMUXYq=&R=FOS!~W<%1;yWahi)=#tnybG(X?? zRTk;h0JzAw>JaJ_0Sxi}DoY0}4|psu_ZFd&ZswJin~Q77xA8_+l|Z=qkgsa4xu(`9 zd-EGnZ;^4Opatz>J*$Eb71kKM&!nY&=aFfH_tW>`%F(0V-WM1@g{T4X{N{UfP@i8kx|K(hEUHq zLJCKG=598;o!Pjtg0OfMVLrk@!C2t~GU}ESuatObaM8kri_A6XqUoyR@Iro{yqL4$ z%Xs5jlrhv-iJ|5s&T;8g8AY#pLBPxDnrkjz4qD|Lsq-Pk0Oejl$e8qNfej4<*$;SiLHDO` zPS++|0mj21h9O_O>6A3l`9j^1IWuPrN(iDb=0l3cJ|AmV7?7J+NT)(b39QWZnI(Wg z3L=KeLOiJJ+UPT@L???xR#-vu4m~b$%{P}WHcM7Q3C}}zxw&*TiptHUF1>sSQ}ZmM z)#&C@m+{nvoNFHAA%~Csb{V%_1b&Jjng=M*g=V=+H#Yk~t`X8JHMZ-}Q)ukcDzlt3 zgKA_6znHi}43}VCC^ohV9#1tgW`*IUs$*(~4etgaLF6`VQUiwZIHf%07#(%!nVtBG z)rn82PP}VYC(wJdTu}6ENU>Y$GV;+*xpDAsV7tO)U@}3AFxudC!=3*fuX60OGv?zB z`IL#*3$4aDtu_|~%#u1eR4}P9YM2fj^K2i?6pTau8gs5Omy1*n;Kq4ery+2RHOzT- zzQV;YBlN8di`@LhW?8Mdd>LxNs}W5uwVK2nN;PS~?4Z#@X^qw{ zqQ${FO^Z_x0=aL|EH|yj^_(X~SpCuWGSdx~#HYtqfeBUVGQN3G&ajWUparu4Xmq%ixE3JZidg2w(gYD!DU1bHQL9+B!0Jd9qMu z`6%J|6*bWz!_u?B6)^QxKA85mL3!a`=&pRzT`P244A39WlLK_6+Zv$Xo_CT^X*>Q# zp*}cA2lMlU2Zga%iD@F1bg6+p^sExZ%B>DAHL-4&uxpsxn2a@M%TjYGmRpaj1XE$2 zS;RFOAe3_`sAeTg%>qtx*oS;k06BOtu^lc7V}(e0&3eYhexC#wMOEfBh53vJdh>oR~>!W0-508I6Ta9@C6x=y#oW|?j*O@+xq}ayd~z!HD=keB_@7Za(=mJv`p++ls2kqC$w@2 zC}WU~d1fmkjxpo4=2AvW&29l*Y%XDJ6}ogxQK|#%eVN>6+4dIt(0B?PKQCqDSDHDM zn9LM4&-ILJE|Q`~2VtpnV*-LT3Sc;l$trWRfwdfqVFgx1V~iqPWo{yquI1?eLbJn~ zc3v#E5UtC2#lWHi=yySBk~3^*YB069Y4hn?Zs( zG!g>afhBt}3x&S&sFpr48y@D4r@|aw$3Yre&T-aD%nER_)U4p1x3;ww4U%LxV=iDz z)7#kKV`q5UYuqOsZqXS*0k)URrQD-}33yf6hKB;LuCg3!?%T6#%wlSA4P_~N&Usw{ z5ic~?Qn~VtY?ucF``rbND5;|?h%zdLVoYoW3e*)Y2D~tw8>FNlgwp})+()KF!?l$V z9V)t5CeRC>Q5#Rv=F08)>S|M8Vy@l@l$Mm)h6b%o(jRl}7 zR%M?#uNCAhGDVhgst^w5V%U6P-WH`XhAD|jlM9pW=`?e(ns%D`D=|Bd_%I;75T6Ir z5b~feS;GWJXqnwr+5ajs!jpD6?C3W3JdilYD%YIHJtHkrKZUx^%*DAAEcE$UUMtMC zP(=q6j>ac_HOk#;8Qm3@6ttq zUboM|Ns6^=RkErOUglh!3u2M;7$<-XidgD7G>*)Jz-Pp?7sFA((-z=O`)F}$&{_8i zvtms(4M{o9BIQy{8vt{Fl_sC^^0=BH+bidwCQ#&*Qu71n3?w2|2fJ{1Vxoy{W!jl#(}&X?U!YA#R{96ChY%`1GfcI`#r7sW(FAxn`!s|0w;Y z-+@^O9J1di#f@2@WGcjM!ppV*E@Q}7HS1XXUL|8_4OAra^zGZwOYHWslP)nn%wwq{ zFZN|ij9bu@QDhyPK8)i}!!(SqAF6U;8Uh)E{>l-08!KJLGX-=X><>HulVk%JP?2KO z^n=izDx;vv;m%OF8+kNYG_OcV=a*#mRML6flFp5Xd>PW=(Wq$gUoVmZ_`L431aQ6R z>;mIMLI614FlMkruP|m{;7gIF`#6J_w35$n3+!U!9?>@*hFAsvh7Qmy!n4Pr3YKmu z8*~H?IcL1L0iuf4TIzE;dRu3D*0`{%;j9KacfiJSSajnIY0=IRCDO!0r%19@7&P5z z^1-Yd-4HcqUIQ$>(Op#~4BGg_$k@nkt*0;87mOu$Y2kP@8H&Y{@lY_)7fZ%M-Jw7{ zlne(V-JuSxBNU1T2NE{cK)gK}k8BSm`?iE)T09u&4uI&L(P_JGq<2f8JJONt>FWq-9qpZ=UM-dkcL(BK z$u2O6x7Z_EJk%Y>mnIa)o1&pkvaZEK@lb3_sG}}b7KtVYdLxNsZ(kxAWqEHRg;uL| zMB{_Om?r6mwxCqVpszQSY>%L~fx#Z|y`?=dm_Ror=fl&J`;%$i7#<(nGrITCr2Eb!E5rmid(|$DAg^?Oapf(eOOmvLwI<&WEd~9@jd@>3AF`HmtJP6tMMUx$& z1jZ8sm~6+}a4ixE1~;Q7-V*NFtHt8rsxEEpgRyPVL|-x<3?-uh@Px_`j-?nJa-|L6 zFrL7G2Qa{iGy)WJ1oDnx47a0IRW}&w?jGn4#FD|j-f*N-(HR=XE77UJ(Xrj*=fy{+ zwRlHxGqh3b-qH~Va!M%&BjHFg5Ea7+61}odqRYW(D4q}!?HTCS02&;KhI(sjQpws> zvM!aZPbC{t$wsZWuNPCGwgn>>NF)R?Z7=~z*`2Y48|>~2ZcYY*iO80aT^j7(jA2TK zwgy9?4u~M$7Y+6#;$dn6`W4BTY)ae1fsPPnULrv)0Af%Ki#=0z4UL^MHL~AsqrE#M z#H{2P4D^N}I?M~}y=`(BS0m0z?wK4pn8ZJdkh$HX=Sp=H6fzlz82&Q3-3CpoK9x#cDZ5bs?=YnxI0V{`Ba9k?}**$q`Obs8@380Pct+ zcaae-+#U>K=EZxr%QgeizCZ`H5GcEb!0CaJ1LKoNw2nlucYBPA(@pi23IP*<#%kpR zigj|P%R#EEgKcPsdPXJ>#;1p-4^0L4j|@%197W>M2;>p#*rs)a1EEMr3wG6R!8}Za zwDv@}yVDk>rSiQ4-QCG(U!<2B4>n_=e!(fnq9+QKj1LHEc#S`aX&t~UkB{uf9U3hb z4S_+W=x}hALo&ssR(T)e>_@WD5kOxESc|2*twPeS=!KClrmr zAaEKF1mwVX)nOEBFba(1C%OeWVTiWCzSVZKf0%$AWi^>=v>tRnkebq|X`GtHsY#5V ze73AWlTaKvfC}b^dO)URInYr%&_m;hWgrq3ou8Vvu4jyn?HRYGEQVLkM6rHh4ydlG zA;r2f(4ATvy8^L}!9XmOOhkG@umvd@LV~!iAv8!X6uZX9r_p*?T05}F-j5wRklb}- z8ka@-f{B2o#;VO=B0iAphy*&t%9{)h#Bf(8)wUYhKzA$@=-8H2qstzKI%72$49t8i zJzQVvvA&4LVJ&6M6%owT)>(1A6*pLMqZKzUOO^Q#8#bms1AQlX16O*Ik zlcUo|QkdO=o+uR%LXh?(Q=x=fXRaH&M=(w!W4n_>yLUq`r!-tu;U$-mAvy~%2*E>> zxDPfByU+=x?e2iFOKGSYHm+UJx^^srSU>8B1;Iq%`1EQ);n6@^Y6v)cgcpKZvBW?$ zi2)8I+qnY3+jx_b+Egdy%Bq^~i-uytC$jt;3LRccnx_+(wKR%xsk6qR&XRv!v)w=- zin+Em(jz^sXuKyV7kgo~VhMDoN3LZwrD8^)bMY-f+Gwc4m=^5mNQp>UMK0$((e6+W zbW9A9^by;;1HGG*!LAUNKg-Sxb|h#9g&>q8MgK9_$NG?SxShs;3Mkx;S_-~>Ggpp2 z*j%yZ*9EaKaUAzfF|x)M-oeOWEuM(b!3zel*vr|NF_EUu8=BziWO;y%joQ@kIau(9 zVO1gPu(oS@&;Gr(w1iHn!4R&dq$yUbBsarIwWxqv#M9 zcuwJt-X2UhO_G}$J%8ksDw44fapnfv<5<_F18l1Zd~dkBvqTF`fnz=pqyEB8flz3+ zdlTJSU?9=g0WTPww?kNggk{CJ25#;nbFr-*Sl)h7uGBYHv~r}X)R&1+#2Cz z$NR!H$&UU+vZG77)V6yW#zHm6@taE?BeS&ZclDkHyr))8%>?-V)Tm!cB zbtfR!RKLKux^S4}ZiNiVg^peyTv0V9bm>oa^m{^BUy{(jUNyPp`bf!GLWf@?EuZ~_+~Is5TM-c2uD-VQ-rz(xq0Zo-Xd*M z3KYuY{# zk4w`ux*OLkaS1sbmDqJN3(b0ISU)&ZXY57thxuZ&+C$?1Ff@<7iD@C*^a^SgF;~=N>hWB7oZNe(| z2D-HoOXGL#9Z%xSKyGvCVWI0=V2*`aCt_Q=({_7uv5WO`qn8MDTjOEv_c@U%O}gWK zXr3D+;T+0M0>t=c7v0nDyyNcdp|Ppay*R?~;g0vDlo;w-TOmOZBh$W3q_|lL;>bY8 zwb)k#I^<3`9F5bS;5WxR(sNPSA*@wD)b*P!sISb>CjHk{#h>duJcU9WH=nJHhd0y)EXB2W@fb3r2VvBz8*D;fssw%3`tTI-ldib1iXNV(m+{4r?oAD~M78kmS;W z^$}*5X9(|MM#noJs;)dkpt?2aK^#N?Jsa2pN71>&+AbcgZf!_E)G};&AiV($8 zF6N9X6zfBvU6$JG4t&>q>r zPy02zZv+PffzCwzKyMfl5@!S)3LcqY2y4WSFo4y!D_$ejTrNlT5HW2?1m@LlG!lu0 z14+1v$yy%ZO{6!1^_r&{Hm=$u2_uNLo-3to7(g5|lU-N6OgVs*JUOH{0@EJbhDD$~ zj1vSKH*GD6g@9le(C9)E;!qTwh4PB2AXT}8Gnsy4n8KouBN{<0mR-!C0JfQ8C!jWL zGFNAxzU#I81G6z2 zQ^?J!WDDk-+Q2}5V#fhv5EJJUiV>xC*ky%qoWS#9^iY+OO%9^+Z*YDcOmqW5nPE(L z9`ndex>#YMb2upm%INMOR#cvUC~DSbB1KM`_cS+!Qb^4-ab_m=Wr~90mMamh4(6OZ z1+yIVl`LI9GjZE!3a1sD+Xy`!>v)xdpxceD0XDnhSj}G8 zr!Ywl;44%3Hkc3_XIL$C0n=j~HtF!RTqK0sEiG?kYBDH`Xm-_Mwe8}G6S*k%>ZFL_ zg}0wN_OpA?KM)!S;iNvW18rZ34LYRyC|4yW7#+c0BiAPh5_Po2o4rt~nV zY|6(JS`+E+gewS+Y<_z%Oxz5~u4h;e36f`sumJE}AdX;=GeoFXy1lb@i#Te+hSVPR zlMZ9|V^ck19md*YBi--bad~PAKfWjRNb)(aX`3I?Jvh)H`bl!Zpv@HLd{zugC-U{S^-N!p@U<1iSg+;ae@YD0TRD)*0!?VaAYu?8UNZCBFUMsClcv0=XOs+__hICs&2Q8ad5 z_(4J!_R@Bo>J^zirhJJQ!#@BL%X_WX8}8;|62=|YLTHLm6?y}8!W-xgcHj^fC|s(V z#DXagreGjImvv}GKJ zS6vaf6v^;FFJAb-xO3Ytcdbe_V_P#kDg~ySjWebJ9Pp^)SXIP{k$JSKN`&jI)+eRT z*7no3JT!4~z2!{J^dhZ8EJaV4M=UNpy~Nsw%^i-JPO)iL_=�WKW=Xn{^x%Py5cF zcxz+7x}gwhk*y^KQdJ~^I0qNIOfFgKjUZ1T#LG)!rEQG(Y9oE8H7Jfv5^V3o(quOy7$1y9 z5`0U7(@F6Hm3suRLXQ&)hrI{~pXN_7XDJKJJl+}GyK88oI4cqsBQ@{kTQd1_%s!72 z?_?$8(!j{~cH%7__ZjN&39p%zA8ow}t5L5l)tfOZh6{+E*2_$JfU2CYaw5y z)hG%r3Q(sK^(xVz66z&sO_PE&tAt-AS~T0I;5Sky_K!^CwgLCb^Z`?DTLfpVa=(T{ zOT6ge*=6dKB(<}^+>he5sygf97hUlt;aqDghLhhENuFu*r6PSaTehi_U3(nnnANH=tMy|7(4O+(V3soTCP2nENjS!01E|Hf^#ySt3wGLrU@xWH8E21a zhw^yKq+EM&XeaAZ$@)~XA(c#R18SR6(A16q9k7YDXc!5aw_dS#lJC*6kLDc{F0(?A z^-`Yo;eW=rzQv^sOW1g&W4);scM$M13w*b0f$FhB@-Ws~N77A+*ion#xZ;FdjZ4Nh zj7OfS5wl+m(#zTwN^nY82PIq4NWORT}lz^Qg0&dPQ^M0GWryix10D9MeMKTaS1$0+)c11S=s{C&IO9o zut9211FWgA2&q#q3@nemuoMP2b49e|!bRR1OxACvzana?_hd1imtot&t)H+YI5VR` z32PDSwVF62NI$EFkcAD84@MHfE=8WN{p6c87+JN_qAS*!mwXp!iMu{E8|!PWV|-hv z^{D}sNPB!fzC7UZ}TkptDOH0b#Y^Mhdqj;!*6$(In=hDzRo9Jz9I0X&)t7)5qHN+tO-G ziN7(mqBN!qNn=X-jSXB2@j4&7XeI5&lo@GEnUTg8ag^ILyUTo^p^S-mYbLK9s8yv| zimX|z(zUj;CPv44Q;4_1V!?#frFTj*!H;%+1o^>hIK1k3idmJ!Oz*;C%(p3gv2L9y zYa!mq;=us@2MTeJw{DnHy=+Q}rYR+wrj%%!8Z_(t96t#n&d_;Y0!eAG^t?xr_Tq<* zFZ6r>jxU?s9K(M!3rfT2mjdvo+)O1cu~5;L$+;m8d#!mQkJjk{9-f$*OrATm|ImoK zE1+JokehHYp`AB`MSOVt5VTre%iy6F4hOK}({GcBRO_kJ23n9>%ipi935$I=W|Mqb zCa)i=GZ49t#I@02R{-}6yM+#`o1>)DB74~q7Ivu?^M(GOC6W$!MDiq2Ip}-`m$Y9S zS}TG&`{5?5yAKx$)clce;xV2WK)fo)K?qJ-H-{3!yjmWX_10Rv$B{1qFxLDD8Lfkh z1|=b4tRCH+-PDZ~FXFWkd}iK~g9)7)u{x3IlG`VoG*{}VRX8hX3GaO|7D(_VGww+3 zA0ON6qoLU{h{>GTPKz}AWH9}-G`)-6k>1TDNL8a7WJwYCvgG@7F>aRkTU(bJ*;qV) z6Ch!1uoJfq`f!*dw*2^&D*Fuu51wgtsH<2|z_oOJLcKM13U33&eZNp|ot>(;QcFXsk_IX?ocXE{`*fua0>Wsu;2zln9 z)_H{l3idT$`)om8Sg^cvIlh*|TMLhuZxrAai%Vwe{sWI#;E3|hO0W3D)jJrK^gUG| z?K+a2D)dmGYl;=nNaEEN3?xQV+=ms03^oXx%+#tb4upEdaxIU+vFAX$0*q6Rj9s02 zdnx+>w@d0V-cm#N+p%P4ToF!f74hz_dvmfg5b3oK_T<~#;XPniR1yvYwLz_{NUNUU z+WG+ATB^6w!e*c3>RB&1g|{N^LCJZLvGS$}T36cRoz`Ac9AelF+6M=?anL)E5^4HO zu~$OtBtx7RbI%4drrNQu-OJ{L(X~7o>DorS`)Dy0zOv52ZfvYA_mjq4EKy?WSzcEy z+%8o~9*bD(u{vh9UY74sjuTtKjEjiHR@F=mP%s>n!$W_A3nBa*?C;?)D%}4^+?{|| zP4#`hPukr!p-@U&Xa$5a&utk51VqX_gMcE6mZ=OfLlF=a6i`&0app!;R8$-g2b@t9 zQBhG*5oc~ER1_5z=kxm~-|TLxKJRtj>pa)l(EZ6;Sy@?G8F#Xh*rq$!&GobsE=9p5 zKD&HZI_LD#2}Mr4GvQ1@dDC?}`p`w=U}bTF#sRv%+{-qEwml1XLD7h!ItZGn1Q!}u z$_{Jppye&NlAiEWDL9|jYe>If|4`lxiVeI@E$D*7!0y_3m#7iY5W51X05{2WjB=;uUKOJSp>-b03I&k;?Jo!;*iT==t7&}y(1Za@-F+lRl@ zG#%wF^=R-F<*SC|)&6DllqqsoxB?Tw8;(_?Errl(|7mCl1co z3TwPQdxy=t?VyisW%;k5aAj1D+3Acy!4(EtPQ=R)o%0Q^e<;JC@vya-OK36{-F(4p zwgWNkq;=HK^(39Iv|VHLBiK#~B%BQmH$y}FazU*m*l9=A({JFwUVZfQip^5|0;U~s z*)Qa=hiFCakmxbFA;M0r7+RernHoq75)yb1e9&9qyqI-@JtvF*tTq3HpXJ zgf%`YZ=d2pgNozV;k3FA(}f3Xy)bYntrzTysoIc(koujdq6m;TDe1ehH{NDoZqUu^K`R3$Bd})h%2Jdm7yh5S_UV zk7QL4tsgcYgHsk#HN|n79i2ouChRlpx3IN7vTH@7f`%P-hs)SGbH*-A*zE+%P%W#6~A!OICiJC}?fW>K|UpinlB;FGl&!MPu*RJKSQH&jU4PIeZ?JH$!P- z%}|142^u%HZKJ(OxWfz@2CJ}ERrbq47nSroY{V2zmsW=v@zL8BA!wu$ZqRJIYd5v% z^jx%rhL;n9HZ^v;O-~(2t04*MY6y2cB+O~;Z%c;sj_;f*EXB5t_v%>^trIks%_KyMQ2fhHjC;P-{|RZmIj{IzAKoTg!5_E60SHnF4vKNa9Yr2 zdW8gGYoZE~2@MUSEn8w^j%a^TezHox@`KxidIt@P^#IpW$`vIoKj{*!#$nU5aCc&j z4aytBXc)EV)B$3`-e`!OV~H=bwi8Y)P`pR{46Plh#g9?-yTO`t4c0NYniAM$re3-N zs@}m0Kd7fpJNE7|U{K$ahL@l0)$h~zT_(14L_biYQ6(Na_U@SWk=+}B;vyAYJL}Iza`irls(ZD(q9DaOv9j5oQ z(=%b?2fN0swbNPy*!ln9E-5=CuqFi2rdC-`oNHG$oqomLtzm=R2zEknim^xcaHAG2 zz43xtjRkG_!dqDq4vuxYI5@yeY+<9HLP5jV@Xi-)+-=d*Z+9IjmseOY;}RM$mJIE8 zqE3piVuUBFtR;~yi3Mj6qsdNO096ISZ;_x;ntoZcF=`WB4NN%Dh;EmP@~|tZLAJp$ zcCZ1o4T)BRaM#mDyPjZy)2WZBxu>elwtYQ{4?oPe*%DoQ4}NY2KRQR0Uml#NpB5$K z$At}kOG^5w@k;o6K0IY9EYRwy`Qqceea;zqTi?ZEI8!hKh`tFkp)^=Ri{_*G#;MQ2KM zK``D~eio*6`DvKe<>z5qm!F7fU4AA;7cuP^L?zI7cm~5p5KWm~i;C9Xftnp*6UWve zM}@Qx=@2wQjaIGTfGe0nJDRkgsKf2Tba2W#VTrZ;w4PjWP+R_e=Dn)UlIpcDgj$7M7oQQq#?Fh17;2IO(Dm*qn@ss##al z;+^HSsOx6&Sl#z*EgXVx9k{AlZpC#eD68EBRH30=G~LnS#0k`RTP&_UM#;)I^gVjm zS_s{CMRgZcFTEh;0{iT*}QEhvlcu^5EczHHs~7IT8Eda?{WNWelRoa!lkwsVM|X9ZudRJhYboBZl!{jK;f1>xWp9AbAGNz z+u?8q2WQH);R^2zSN7osDr^(jOTUHKU}0N+kZAN8hP$UUb$z)`7>%p^$FUV8Z0$@X z#EV?Mr0X`KKF*|BI(-$qmcg#!*#Z!>tL+)&ZU^mQNBKUueE5NOWm-$5=3DXL;4T0z zSI`R7&N-Ejw*25YJRxZNY3*2|+h%Md6rM#bA0&Q+YU^ZQwI+@)?Ybl%Zd}42QQ>L8 z=yxJVEr|z;hiw{r_v<}G4d+z2=&WE^ufbjV+EoU#sQb{7!$;a7kkaU$y`ZUplF`_k zu^)C}?D)a9y6G%ec-hk?DBMljFQjn4o7iGbyIniMY=;bGiAV3(r(AmPgXl~9o%IQw(oaz3=tlt z1ZS3_dI+PqlEketx_?OLifn6a3rL`@=Gu9J_@xdzCelw{&0$-i)%?Jgqux3J7IpM? zy3d=N(4NU2uy9hbrUYkOKeXL^3G>ElW#Owe6bBciuw1kF*Sw_-H=_r|Gu zRIa@s<}ZEpG~hEcDpv`@iV8mV@)zqLee_Vi|6@2WN-XW=Fg-G2%iICa+Pig}#D3Eh z?r!~Ng#8l7V~L{|&)9G|dbVzHM$WR7<+1aU&riBU!M~Lw-xBg^FN-rOFH2sowB0lE zj<1waxi~$1*;bV1adiY`>z820yNXeq-aX!xA0?FU1!?n_dCSwzOFchjMeKs) z3#}B1WnQ5)(ezpOQ2q7J@P=2iZ2M)z`|bW8`b94|Q<0X%mM5QAaU53v(Kw=)pT(zB z{Tk}eKG6%&4y&``jQpfwl`?Wv5%xl$;G+j?j!{Q(hPTYdm00H=DZXb$-m=u?Dd)w` zPhMgDqx|h@qLYK+sN=pFd1Hb)?w(G}y^O7=Ed!e1q~dth zYq7Ao;W+u0P#=2^}Sk-0P$&eaL8JooHYOB0pJ(w!NmiRx}(rB}8+r;NI5*2kyW zo-8>+Va=Ohn&Wk$ID09O>SC!)YreYeV~>q2lL_OV_fO+qr!+mw=UZ>aJ;cTx)vGl84o6R44WvMti|faYo+K)bgc$NTpYv*Mw+tHSZFaIZaAD@91T86^1>me!{$& zXG%C(^Q^lj#;T~D@`^r}sUu-}Csqn4xO=*$Dkw+K^g&S_6d$d`W9?Nuj$5eCl#Zka! z)Z=%9mzTujk`kTZ2_tzU)5|7mVc6+^a|;1$t(XP zYsoo0zskWnVYO=8*Ch3~`Z*9EBymZz@?=yP{_xzA_3E_4V={RkdH7F0Ii1zp%JaDXlGNYI^ML-skA=!V$xc><;j@DD+v7>H;$7B}tf@V`d^wK2FxbYo zLVro>Z)31+NcaiUTfZngRUP&g&Y}8?((ep=>N`wt+xPI3<1AFiJNipZpKl`!K4E&> z=11X6)zM7hRWi!|frS1f3`o{%-wvOiFdV%&&C0VzDWA~riQ|vOSDSGB!AsSG9CMsa zvWog2l+pMPR!FakU(WGQP|)1N#Q5QnXmjGR5)>Y`8}b(m zpTa&XD$nGE{!vOZ*~za^o-iD}XwR0{jmmGHhEJT|yZ<%6`W5o4A57nb_(E9m}(&uQ~V&x6f*KisU{wPSF=X54)`(zb;*{JJ1q$C*ty z%rD=$gz&7Oe|_gagf9!i4V}9bwvW|pHK&#H6k(f|YWC{kgqOmNcN&&C4JVXeAk_`U zWeEu?+(8zA&;}TO=m*jP5E+hzhUiB}OFNCRVZeb3(Fzd=^zg|KQs1zns%c zNES52N-TfES*L_#BZJ!>6C&abof6`D*&{X+^ZI*>kqS2o9Dc`5G7BmB1;n}gqc zNwdTA9Z5P^IH>hK=|X+!Q%665?8u{%v}3QNiyh}4ZDcCdbDU?jeMp+3-vHQA`+f^g z(>~a=eX(huI<1{x3vR<*p>QQ_WbQPzS;;pQZ(Dqe?{DgN;zU#Z?fAtEURpdrd0KdI zd44BZSi{+NxsrAx=aD`bkA^EyxXy5WnWGs_<(aIoP0xuIub1*Fi(ou+OpSj9{WYqf z|2R|mFEKT|ZC8^t(!gsJu<%O4+NgRKRv{{zI#{>uXwvy%eI_Y$RjHG-G~7QWEf4D< zNri7{@ynPWmvDS~k>eCu{FUL$wUaIn>nrI3N53=`e+J`OY};yuWpzBlJj-!Z#ZJ=M z!ZA1zr{Nr2fM??}ybv$Lt8q2njO)?XADd45 zt!6%oThNXhEq({Sj=S*#`~<(m1NamEj(T2yke`p4n2U9=5w^s(*a?fVFAl*I@D!YY zQ*jP1#3gt>UV?UfWz)SHZ^1ipBW}j0a2wk3mJPoP-^IPS4-eqa_$Q{=c1*)p#%!#K z^{^=xVtYIWd*T2bhNIAq(`-DGa0br9GjS!I25txrnumF$3F4zP6<8gQ*mf&QZ zjc4FeT!~lV8oV9toPd@05qt(;!d>`2eum%TA=Imwf_y4rHrB>QsCV}S={jIH?1#hf zWSoH0@pN2_EAVo>9&f=7_#i%s&*M&f2lwJvco6@K?f#Q{!REazKZYTSNJRXemGnnHo^AT3rFA_ zJO|&$?)t%M72z?z$*>H`p4fe;AaT=b5*WqpWB<{h_u~wBZ|E4$^ zr{Fnw4?c!(pq((X@>Rh`I1Ed0KCZy)@J@UTci{W@4gQ6hRm1Vs!#3ChOK=)4!>jNa zd=)>(9380IbkxJ6u|H14xp)!Yjt}4t`~rW(Dmp;5{F`BW9E_*oe7qFb;zoQ1Kftdr zIV;S+F1Ey;I2+H#t+*4vz~8Y_c9>rsY>C})FpkF4@j|>7H{cfBgJ0n9SV=#)tbXcX zOYDY&aU9OVWq1YNkK1q$Hqj3Q%fBn0gp+VF-hk_I3%-Z@(5(^XmxTq`8Asq0T#Q%Y zI`nhHeDbk1cE?k3Dqe}}@IibHKfs?bO+UD7y7RCZcESNT8mHsgcqy*Mjra_{f#2fq zn4=$HHr__q9{b>lI0etZi*PmGjZfmM_z`}GRrEvI##a;DU=JLDrFc4?kJsWI_$a=F z@8N#@6RXw=$J+us;!qrmb8soH!dvknd>(h>KKvEaYlq{jjjgaN4#6=v8_&fnaUDL0 z+wg7t0)N3uM~36Ag)Q+I9E_*oe7qFb;zoQK_u%)KtaB1JAM0XE?1^J=IxfeJ_#}RY zX?4T=8e(glhZo{?xE`Oxm+`;&J$m_JzPZ>A`{O8_jA!G;cnf}mMfJk`2I453jpyQ( zxDFr0ZMYY|#kBfizIoUTJK+U*HNJ>%*Wg3=JnqJW=oW$W@JzfI*Wjc0Jbs7=&>B?P{vrz-U_0!E zC*T}hjMv~M+=9DtAO4EzMdA2rV=L^6LvRev#&hvXT!#u|iauq7UY zx|t=YhZ0_NUgaSTq!<#-d`gWGT~ev4^s!~F8F9Twv# zJPjA&O8gJrgHPd3{20H-jCM>9>bYOR^bEn#Scc2-CcFo?;oJBFI!A^1^}=Cz8ZN?X za2@W$pD?3+m``2QLnwoC7UM7+k7c+Vug2SPGroX(@Fz^}5awSCTjDV|7)x*wuE4dp z5nskV_&p|f49Am$MR*LJhKq0|{s-^Dr*J2JjNfDO(ToR+@EANEC*piuf!E=k_!#cM z_wgJ23o|=~GL;5@t>*Wg3=JnqJQ z_$$`v8ji04cE*8t3eLa_@fy4rx8Q5I7k|LmvEg{CV`J=&LvRuZsdP zgZbSR&%}#y4er6uF|$uNTs>@qGjI`JiTC2;xC;;9A6UI_m~U(BiYMSCT!0tgHhcrW z!rw8kUzl$r9ELM+5nhS+;^Vjr58xkIy+7r}u6P2@!NqtDZo)0N8~0(#fH2=IY>u5# z_fiM*Z8FZoi}4P82w%Yu@i+7ahWX@U7t{lUg8awg99)X4@K$^pU%}7tXY>Yz`5l4H zu{RFKsdy${jBD^-dsIHV=L^6 zC*dSqjF;g}_yoR)d+`U14GqUr9UEf@9FAjf0j|QE@DY3q|BDTd3-j-QdTdlM|4VTp zUWbq1^Y|{h!@}X3;8Ca-;05`O$Jw|XZ^XOtd3+Py;o23Uk6aRQd%Rd^e2!Y%kR?!nLTAiAf9}z zZybT+a2D<_3G?|2tBnc6xp*Wtz~;L{1Cs!UodrS zSk7#$hpn(5o?uSVy`6;5GN(Dtxr8q@XY0N%!Z(@MIL>W^H<@LQvzhSw=GBg~m+&`c zUB~%@us=@WMQXQz`Q~D^3pJJQX!9(!%ccKd97+GtIE(l)JPXgk3r*#BDc(r@EqD*{ zoA6cKg`b)#=RW+N_@6O-eAvG#=3#AYWNQ4)u@muKu^;h+agM2aIK!;1d-(`oWvU$4 z;Tq!aBzzBUB7Q5rO8gu64)GtG6V;BI@bC0@CWPZjF;$Ly!n*Au7=JV3k0N|Db~QD> zh7%r%qfL$H3|xU1n@WE@t|$I(!Vlq7rlxx2`r{DXua!DnzAzG7;6KEnO@E2d2j``5z)?1F=FGS0)Lc&VAA@)5q% zRQ=zBn}~k~U&D{^Yg6eD;7`Qcwmzwv+U=Vv|BHslTQt)67si2Er{&1Bf3<_+%VI{4~O|aH*;BTt)wz%(jkmAK}MMjdu$^ zNBnDq-^4wphWncShs?^3lcr+|o1Sb_`Q&14;+qm~iN|0u_Axd5aI=!52S$bA8T8l7 zc7uH96Mr6Fg*VavR(uE_#Vw}t-(h-=^Dg1f>HifTApS4Rm>v#S)6{g;!9r|{N1MvO zmzkpbt_hE!{{);u{6f44uf<#OetZh|;1~EOX3hx5dn7i;4tN5NH}xBK_^dGfIGkY) zbeyvYUtnrFFUBi~Uqkq2yq)+>gdfJoiQi6m2fjx9`-DHnL#D?6hpFv##_VwXS(s}o zKA&(yY=y0{6L!TOrt%$$v+**#4%gvBrsm%>W&_80jqv-X>f>YljQH;f|AfC0pEf5< zpN_RLADfxVzrfUV9ZP%<9Ed}46rO?;O$|TQ)bNXlUyLhoC0>Qs;mxLozunaEn}~lH zx8Sq*s;Tt5Or`&b_)l;@{lBMw(p;reeWhZ$so`=6=V3il`8KA18{*qzcl!6ik;I>j z6L2z?naXdWsqtM%{3Un|-hk_HJ#I8L{6nUO-$wk4_y)d>AK@ps-_-Emn;QO4;_bJS z)kiv3#hRwl*EN;C1@VR0k^aZfe-QD<;R(b~FqMyPm=5xpNB@Pmocpq~P0zP@ka%Za7#~C5)bP~_AAxmnl8 z{*wt$!`Y_l?+p5{Fjd~w_%ObTADSxHSA>5hoO-(AHC>gks;P9f2-n4i#1|26hrO^L z4mLIXNrX?u@utc*AD7^N@FCn{YWN+5-zEIHsd9dW2Z;ZjurojGpJHnGYJ{s}P2w99 zZjPPtSnO$P_@RVH;3!k&pN^N}27C@*H8uRZguf*Gld1Cmid7bb>FSxvx3Q`D*}+u0 z&e)CkeuM|%38scS8K>ebJQvT$Yfa_58gIor@P1SIJ&e!e4%}mEx;`WPBVl)8m~RSJ zGL^0d;hI>N_!fi5Z*v|v#GK^j!zT+GU3hCeaZT=LyXw5Xsru-M#n=l6 z<1joKOK>ty!+E$6&owok^G((7wZyN+Tk#IOA0NV}a4T*%mCw8Q3GrXxcf|in_)kn< z8kQr|)bK}|n(lho91E}mcE+CA7YCWj=LEth;dq>cv#<;onyQa;@n*c=Jl=7hHdU_Y z@D+R=-^CB{3;Y^?#9uIJSy;}hrt;0kBTbF3KK%=cZ;M^98}`FNILy@am*NcK=ink! z`7fdW#l&BZ*W((z9q+>XOy&Ow;U{n#zKCz&+xVWT@gBfR%foPUY>PTY6kOk_jM=P53Zw#~t`z{2YHbYwODmO~Z7|!W!5D z3$ZOYsTJ=f35aj`j3=jHJ_{14uWci?mQ0`A0J_yO+4 zeYhWg#@{e_Zi&X9niQ6!AvVQA44zY>bis2_%kcud9@pT# zxCx&%$Ln|lKfvJmBZ}Wgct0M*Ls&IA96lTCVgn4GH!|LF+7dn%d*I1fg28h|#_O?d zgfGHN@n*Azt{Y?U{1AmV61Hb$TK^sR1_sX!QT$%QpW%0C&&aglD#t=IF&ArLV{DE` z;n6r4hv5{Qj!W@;ybbTf$M7k94d2Ai@Jn=4!t$nIZ492*q3LNuxIOm40eGsJqx0Z6 z1*hZLcrFIdxf|+#E#cL8uUS*)EAdebp1+~^U4(<@gem+X;s4?<=1`qy##mYy z_OK4t$7a|Hdzh!{@%K0whv8(LhI4T~UW}Jx@VpJ>x0>+%_z*sUPvhHWTOHTnUi=Jy zM|)71rAxzftY>Ox)(Bf-5%$LZcpM&&Q*kEF$3=Llsp~dZ;`O)&AHdD{6mG?LFnC^w z^7)kTKK#SfpX-NuSQ+bMV{C=3u@4Tw;W!efnp)Op;^}w>t}+K|xx^ds7Q7ob;%0mt z-@v!=1Kf*W;{p5`f5Ymk6C3{#n2!yy0Ndcvcnl85k$5VO!!vOSo{tydRd^k)#dY`~ zK7t?MUi=cj!5{G#)FV%W>5E}HR>c}v6YF6kY>7qK0Xw5Th~Mh3Hx9z%a3Y?DvvD4t zh3DWEcs1T_HqibKH{;{D6`#jf@O9jW`|%(K&#O_sw(eT~saOT8VGAt8_SgxFu@?@+ zp;(Gja5m1vGjR!Cfmh=lcsD+PoAGsg3*X0&@kjgx^*WGXdNVN>gXij~9@-M_fPHZw zo`Pes3>V;HT#DD>e{dbH$H#FCzJ+`6WBe3a)K38&&> zT#BpkTD%V*z~}G<+=CzBclaazj!xCE+%>Q!2G0r7^fV&e8IQ%@*dI^DadhVkulOf=nc?^=V>aeuD{PG&u?vpIF*pgQ;v763 z&%$%?Lc9d8#npHV2G2!OJ#8iYJidaj<2(31euBaClQjIdgnz)8j_s`eJ*PdocS@(hO=-!F2XDE8eD@n;~jW6K8?@er??Lf;6eNi z|H4$A(6IR(Jda9NBU~LDV{qLKY;21iuq$@QemDrn<0PDcb8rQGU{d=o?uP}HXoW_%SL^%DGuo_m!y4V1lV*w7tp*Rvx#!{Suv#<=$#&hukycloCyYPN| z2%o^GaXaq7FYs$Th==emOxC#`TmCC!Cgx%-EX20h3A^I)I0`4?X}AJc;+1#}Zo~)i z8Qg|n;kWn`{)(|$tj8EU|4!4DO}H7h!gd%u7fRgPr}#AOwa6brE}_Q%0^GM3<3cn+?>m3Rx@ zjt}5wd<*yBUi=Jy#@{gW$Z&dcunyM8X4ne*o4W27Jnv5)Pk0oL!3j7OXX5F22A+e< zaV1`c_u?je6raTB@CAGW-^LGcFYd$r_#^&;$#uf%OT)(499!d2*af>`9~^+g@B|!# z6L2cd#D#bkuEJ~aM!W^@#Cz~Td<5UZJ@_$xieKXa{26~kyLZgycPduFYM6($F?hbB z(jP_m7%awqI0z@;WSog}@eDj0m*WMv7T4ijcrQMLkK)t#9Daa%aUbr-gLnv&@~IEZ z#2jpah1ecDVKMf?fjAVW;B+j*1-KZO;>CD5-hemaqxd9l!x!;&d<#Foz4#@5gFoS~ zm{~8Zj~uLpb+Iuv#~#=R2jegdo_nd~=M=(|a4OEh)A0(t8vlbg;d-@*6sbNmXw$Dc4$=hkfeIamwpVl!-o?XV*b!xQin9E($NCZ3LG z;Kg`3UWfm|P53ZAgK z;Q6G=rv>3Q*d9mWDOieAa2A%~B3z8;;e{AH=TzgnituV&i?`!lct1XbPvFz|7Vg21 z@l)K7-(gZy=69r{@Iu`WXr}P~BV8ZV<}ruIpbO)a~#OwEf0xCB?=WoBDl7bLtE*W-Prws)HeZ^7-j6L*^fb$<=v zFU+B8r$qRWsrnDv^Qb(YtFX*8Pu27j&Ns*Fy-emrrPs%%Q_T_rJ=A5EAe@P+k|3Oi zs)`_-j}5UYw#1Iu1-oHS?2DSTAU{n~;0PRJs=g=SWSoYxund=&nlH<61+K))a1~yQ zt8p!^!}YiUH{;{D1)s(3xC3|Nd-xH4f(P&*9>U)-n4g-Sn9VO4%vV{Na4=sLu1z?Y zzX~@bT!ihgBX+@V7_{HgaD536#1nBej=>2y8H09R8h#exGF*boa0RZ!%WxI0#dWwI zH{fP`9Jk=JxD$hRU@FgU!tdc1_%$BDgLnvkM=weBuJx!gW?~NJW6)kq>4NrRvL*2y zu?u#?o*1+fQ~D8vPsGtU1}ETToQ6R=G7VowcnL1U6}S>F!&P`KuEzDIwnrQAK70T- zLkg}d=R`~ttm19%Xfshw&o9Jn%Y0+V4m4P>jwty3AH>n zw6JW7EwKpOVeno}rRzeto2lcMp4gZ8fjAULVDP>$4L_Rj7*pGm2{@VfX*dhZZ~>l) zOK=&kFtz@##LI|Zh1Z%oh**tliC>57O>GZ0;C;kDfSd7g++ynZ=~>)P{0`h{YW>)S zyUmH3{}{9jRrgmmKegOcv3M;ng{GF1A*Pm(p!`}cZb(&F%frj2mV@&&jLrX>OwIRf zYwxA`eU!C}(tK{MJZ!#RV(my|it;jlR9@yST+bcD_0M;dx5W>y9(o%_*Ri7OO#Qiz z@~Nr$@8(I($N$)Qb=ChGmC5Qkcu$M!)5>P`RM%8}bg}b#6SZ90am*5qzcsB52{$!0 zP3;JGG&M~<3HLQMZ6gSuXlmMK5iT<|jVlRXW@==s39mI(e~%O1VyetL2=6pi)&qnO znyS~@w%=dkIQi`VyAkebs@{eY9zi%b?os+#goEQ7g@fZ8r4No{6b_DKRF4lZd~h72 z{=xBz`Ul4=3J1p@3J1p@3TN7WQQ;i+k41#rnd%=LFQ|WXyii8}1@vD_cpc$q2?zUa z&BtIrtl@+Gu=0x~hvW0iq3mbXKi|UY-;Ms!{&O{g|ys^xsbZ zU_Yh)Us!lN`yGWdZGD;O=s^f`7fvr5J5H9(37s5um6a|ia|-OO&`!a)xpSQYizrBV zvvK*Gq5sya{Qb~>>s9eB(f?zD@Lkabb4sWEEm`!|=)d&{-yQw;=!7>&muDD%uXga# z^YZwF$^6H6N{88(zeT;mOVY#M@yz4z5074z{*NOHUQQkK30}`VWk$)IvD5Xaihr2+ z@CDWX*el^x)&JN(d};MR_KLs0`XBp-FS7o}UVne3b$PN1FSoAHW6p$yQ%a`Hof9r- z1^@m=^MW}uZBYzTOeif0t9JU>@pERDOqnrprm89GAH2u>ANs2r<7vX)iElv<%2lC% zkP~l7|EKdRUa3+Q^(`JrO433>McE+Sqtz9;o!xVpy znKorcscI<5U8|>4Fn;Fr=~}1~hnlE`MTv@s4JsI0RyJqKxOrvD_W#94mjWGaKAlvC zX;)!bZQ6oQJ$+j`ZBl|y#dOxsK00+2yf^#*l&+=HRUEH&9r2GgRl%o^z7x}F^XWwW zEJ4&gu0pyI3H=h&Ev=Bw_JL6ziRtdFkZ!cXR_5pv4Rf0!bok(OqesJIT_;oB$LdeJ z;vjExtNs$FV}-)g^cQ`i{Prj!F`ey0Ex+g!rTa}0iRoerSNKrL%ChhE2>bPcuHsL%rkORh1|)zb*;+=};n`-_aHFtF8R(cqIBnd7oGz-3X<# z93fQyMFu zY3XeK+C6*vA79TmsIB{%3P+zPKfA{-asIALm|h*~#q;~4LViuPFxm1HeWLt+sgU2U zgz2rV#8LTbX}%|xubnbm7iC5|3+5_aV)@=nC|@1Y+4Q!rkl$|Q7nRBKiMrcV$ggs@ z^7SL1be5mJ8$Gdn?%Ke+g=M!;{|fniV&&@<=2xixQGO>? z$nVZ8^?OFY>7tL-g?;R|K-6vFQ?GNJ>P@XH{6ziiw?ksRe7)Rt);0*o+eS&F@h+;6 z-`uCQeU36wx~Ox0h5T0PX5pslY4u{q08xIIRLJkHXY~8yAEx8N3i&;7r|XPSfi1uG z3Hhz9kl&Tt^}H=x!TChxTU{Z)9Q!dy`8q0XRK5-5XX}oAe*a9%Tko*jzAZodd$>Zn zSS#1*ZwdHB>FhU`bw{6}O4rRs#wY6BQn7pwDxDT?n_gQEqw>9`boxIl8ve4@uG1+B z$Y@+Evk z(rM!hW)|l2Y2BfyeaE6U9ox3a&u?8+)H>n2efxI#`EA>G?AS3#JEqd&UITl(ZZt-l zmZtIPu>$5@6cjVXmM5J}bMl?KPSJzs_5SvU%w=x2~dy8zwJP z*lFModgh0$*f6Kz#@2_jx70qe(V>Q0+_t$bet0c5z{!8*kW*CjgwxII=Hz?bdJNQx z*C45PQormmdA-wT&FbSkW${jaxBA5m`Z?}*ON!kelj^OQb>Xaw)Hi8BthJNh;84AM zr3}(pjKWSBUQ$0vfH(V}auC<}B+`W?Hlr%bgh$J_)nPzbE zi#ixdZjoopaFXjCr_FRyQc9K<-{b|FXURt&G0gfTrCrxS#8T`Y(`0)=Z1RvJrdgj@ z+Anrm$xF#nWRjP*xtT^DOPQkI59(L5fl|)bF+eOYyQPw+T&l0s8}yajsJUVr=GeNC za;wE|wAlNPQfyJq7>j*OUuo@BinQ1Y3lGRRHce~OAzLoJxAHZEy%J?@r=m2Zmt0?i zdTSJu;=QQf2dUmW>Q3_xXo>K=e(LtU^YuHVl6R4ENcUznRn>SGYlKz2QZ36F-bJl- zbAfk@CO*@xiCMnlDLF-SR*R_Ri z;Pl>TsMjfb+ZA8Svr{g$y{oje)$y)V8R~k)ng{vbuNq@LuT*2H?^%=b2HsSqZ0H@8 zYq#(o)mbN8y`D$w@fzM1)!ue*m&)*hXE*u3=ru^uX*+M4j%apx)(q!mZ?wkvitnhq zrR%p)v0Ax)n&xSN>o3)Lyh7K%N+m0D{i&Kwm$`n5^1R&jdugyMUH?a|zpGr|T5eqB z`c1W*T{XbN^8(jYjWqr`~ztdT@U__*q7`dou#LeCHol~-&YE08T~rh zZ=vD#C;R!TjBk?txvGtCll`MKs}882#_(OTzeeL581p-6851A zR{@7AQnhTab(OtMKkEcn17k_ z92N8L(xP-y%>OY*kDZJ8J2cxy$NVofDfh*EyY7&a;*U}lR8R3|i3KVC$(kbzQ~Xk8 zc1DVCuh4!k#s6G~V(%+uWi^gU@&D3-_F;;Ds_N{c6u*ZG_;HG#-$4h)_-eu37( zbyfXRRr0M>{Y=%;ZB>0c-MAv#e@zSM1=;@7TIw^K_=7ZI)tdNqRavug{o}MO&Cd0e zvoj~xuc?)7ZmxfU)}gXo|6#2}^K$(~N_l#&KTuKgXhE)TXVe$w`j=^GJtNmI z(RON4uK%az`$pTq*fQ&|bFj;;<7!p$dDhWQ)q1{lOjUJXUZRds+R|QO9UE0;S6atvP2ei)Xs@N} zD(jf9iCj2d9bagMpJ5%dHBGiptaPi^Yu7qH*K{RW$9^p-$<}d%W=zaFwrjacv5w!g z*rZy=hpL%0>$p=fo^|}CI`*x@u9sD^j!s$^(yimR0{fMwj(wWID%NqjHi;S5QB{en zTE|iqBhxzis;JehBTLniWgWL^?Ag}wo+=^7I-b)^u5KL<=G#;xIh7u5Xj7q%QL4Hm z>o``UNVbmeI@wgHLqlsS)UjCglWHAvl(VI(w7j|vu8w9}T$8NBTJ_m*PP)AhIAw;L zyhGu%542#UB@I(&YEg#WaqC^J>>V#(Gr{%R20Ojp`cC$8v=YX=+3HU5mgzgytD(Hp zygB){|JkIzzPC-^mAq@zH{G*lx0Su8^j*b!L*E(R=lZVd{ig3s&u+fR_g>Zr>v>gG zul2p5noAA5D^#@&y=_|D8hN|4MQQBWZFWt(I+{Ptys0W%b1z*fTX?mUvX%FR>Z!`gnH3Kwr;pzv<__qK!>|?{j?*@Oo;N4)kVK*4Ej(K;MJC-?cao@xIrh zH`KG+{*UvXPSS?iOH!>4_d2MABfR6PX{+r0tn#1Wy{`puly{SA>?E(ZHufibqxC)7 zo1^bjycPOB)mxCQqZ#jBb&v6$)Av~KU44)9CMuutURSLp6TB0&&Xsyun(Y(4k2RJ_ z-eX$%CwrG@{!a1k(mHyY*Igx?>b<0OXqxwoYIwSLfyz0SmJ*#k~4_F8KyuJ=Z&`vz~A>Up&{KqX(}O;P?g zdSg`1wcelVzRP=1CEVcc)?B{Z+okes^z0Vs`@K|cDmHm__5FZ1Tub_c-gcGwA@8Qv z`oZDt(K55yTcx2M@gD4~U4*wyW!U2NRi00K_Ry$jJbP5sR?jY&J?q(Hpq}#{%+Ujr zy(U^(p7+jI%y#cq&G#3)ZTf!E`$YM?fQ?0BS5->-O^HI`Ssv$dq{^!90k z@tXICR=C%_I+}_%ytA~7?eg*!^QL#Jy5I7i)c4!ocba#*y^$*OJKoAHJrKpSTVmhy zHfW08_ny=D2i^zz{?Pkb-yeCuHrKAy8(UL*Qm?IQ;1h3zzCZPrXi7ixuG9DD-aN&8 z;a#HdeO|ii?Mtt#O8%91gXYNBo}EkD@72@yH(pVOjySx2`aa-|)Ax7YB7J}Fy{Q`b z!JDAc9`xKo9q@QpXf6K9v)48M?9EZ#9`asM4!?M_wN(G=#k4N`=6$6(_`8>^>H5PP zsj2wWTc%NZ&dPtEa7x>z^u;U4OoaxqdY*2q~_=Ksltk{#zQ@bNxKk zitqXpRI!y@|K%3ig1G)?qO$8()lyf*_4}&oGhBazN?q0UhpS&T*Dn)UuK$}Bx@_0a z(HzNf{Z^v7>-QElT)(xdCD-+j)0E`7{s&r+hq`_h)$JJ9zg(pq>-zTU?s2Z)PKz`*UnT`cD_KB{arO+hTFIF8)c71E3IzmM!7cKz2i+Qm9%)jGCBHKEPSIj;Ye*4%Sl|3OXkQXQqLNXv9Us*Tce*U!~5cb@BC zp*+ub{nNE{t#JK9&5{dTf0GKh()G{LEVx)Tp&Goz_5Z7BxYYHVXz(jsf3h|KI`X|u z#nqAT^_qz~^6jc+MMu7EGy`l5H(l2U6ngK7VpQdkz z>z}NWz3lq$Yw>?Y%S*1d1{#qD*r}PLtWOahKxL3> z``OBFT8EgQq!qWy@LqkKw4-A+Z_s>k-884l$X-rb=UA;U>?+*PN$V1Yl_sKX zw^*{}l48j;z<`)PS6x+l4IJ*I4T{y?sH920N}Q3D)+d&7jrvvXTkNFui{)9b%zc_` zX+vV^Bh^FAveJ6R{D;(8%`#zx$HlTAvRs_>b41#(ShD4kV#!nk?Q;E3)Ro;rt7uw> zT&7qFHHAgFDSoC#Vz-f{waE=9af24tw2ryy+ieUgaW5TvD^Yfks84QKVz;W3eX`X> z-zXx($-cuTzkd{=`L1c|mYXuoMscn-v1#3N!-?9c*_bvcH{C{Vqc|bgKVOSi_7^tl z6Qc|?if=4pR1~369JGj&qKGO^c0(;tX(vY!m7VOG+FGTJjv~^X?0kzjC5ouzWH+{m zQ=<5iq6mVG$Ff2-nGusm9YLMG-cOlG2XLP1&HT$-L0&Z#eZ=Noz{lvkJ`*W4rbD>SW|Emmb&C6<0jZmtrls?zlb7}oz&gxPO*se z<+h?N%uTkc(0cYjWB(ZKIs$aAunAEk&#qX^BJj9A)z zjZ?;H=*+Kdjkv#Yo(-MZJY9ju8>ibtHf$7I8~Zi1sm%V%7Orhk26de5RBigwo{u7q zbh4{h#P%qnwv(M>5idp&HFY1bMZ6S69N}cww}>54go@eBB3_Ona-HlVi+Cl9sNrNk zr6cXMol!)Nll{C!ycR`dt1>L&^(Z3C$+q*fX>UXk)tu}PEn-&`k?CZAZV_)q5n5rt zwTQQ)2(7U5wQEj$CyLPOxY#20L=jpY&$ozoqX?~zms-SoQG`~^zj{0rtq>pNM*_fdpqeX&LS5JhO#_qB+FQG{mw5R3RRiqNe8#un$HYZgf`xf zSw!O~LaR=awl--^q6k&_4MmD*7DZ@XYMQTz=23*!r6P-H5k=Up%_3Sx5n7kJSwyQS zLhDjriztX9G~1fkXbYnV&9-+eq9}^cy7Ze4#nReD5l*n`q&7*h$7Ez4WvhB)oCh0bZZ9aBt;-9JmmF!hEA;&}+Xt6)d3UO={q57+9Ll#F7s=t-Cg!YUgH0`S_ zqE{55XY|)glH&5t{aP zO%yROiqLjshAj(&qKL3E+BZpAs_D$EVGDIfD&rLOOB>uI-Kxo{oRfA>V}FAZRkIzD zQ_c1jv1+zq@v7OfUb&jpRHl=DoDDX#NwQ_AYcgGI{9A2NaXYGy*C}J9cI;j^ZOt6- zczwIxY5Gp`7VA6NTcz)qcZa@HyeIXY>b;@wG_Od9@1FOo%Ib9t z%HAXTuHqe8MRV4>PuW-Xp4WG#_kq5vd9Af}W_dSh+OoZe^qu2fulO2H@;YVb4NKml zlGgZ0nR+K>bl%=45a@A+DaEXloE-5Tua4E?53C%f=eOOkxD4L2rvs=8Be z&{tZ!^!T)n&#)HBUY>p*I9@A#>jYg-RfRVxd4qc7UaG>>_D;*}rqSg6tUZx8H|sQY zJ9%$+QeaV*J@6uyXSWl2%d+eOj+YnH*4?`#YqJ8C^ZIBec-LgTu0Uqq_(#A-8xHxPAf~0-o_oISATmTM-XXc z2s5!MQ=jEgA1hGU$L4QM`@y5$H%7g!h~>T2=Sf8*PuBwOtxta2M!#DTxl^=l^ZcSr zdy+;_BYvB#$CQ(kck)r1^=-4PM@)m~%G$|iE4kk;d7lP7a=#_$lJ|+a>(~Q0+-}uU zRHeF16*Q5_anr39>{D5P?&_IJlb^0JyE$$vs~7!#2tW01(>!v2kEhqJMd{Zlef=Q) z?=3C4R(Pk84N&g{?Kj*{DkT3np8S(SOFmdB`|Gd%Hf>AXPx@Ld%~g1&{+xP8Yeu>| zDrC_{#R$i^BPigtO1VmZVHP`jTNY0!{D}S(I=AG4RTs)(pK}OH&R82T>95I08oMP(vM>8nf(43e`i;J9c{xIVP7^Dnr;cR%(iX^)**WKCuj|WN zzZY1t=9bJx<=Pjy1xb3VcTY>A)7NvgbxL|YRx8=Y-7-V_+B7CT5UXpU ztwU)!aAUQ-QRTiYu?=+GX&QqZ9(O()-!FyG4AZhE=~ zRL};jQbkn~2K!~Fr&md@oZeB{WaJ)}s%l~?ZJ`vjqLO8`Dk_)_m6aH85!s0m<+XRL)2%8pok2iE8^vI)JEDcu~;N(q&S-ai32uH*P@c8dDrAfw{`X~cXRi2 z3!j)iDt%;7Ax+ykt+UCXSxR|#^M6RM1-3x-8P2XIN8|??v`m~pEw+g%`eo;kKt)>l<@^aEIO)^hx*%RxoF%VVm54PLz<-zb6WFIxaD%? z{+>{#zvq-tCfm^dbHQyB;_7;lh!Xuhr%FMhp+>O1b%v=c{;^X0&nYaae%4rB8^Na5 zIn`qAW4l9be4P6FOLB^CG`r}}b%yIZ_yl`Qb%jY<2T8(Q{#KHIACI+Jva;H=+IURM z&<*aOQipY0r2QpCCI=DPs%fa!@%iNj+g2-gLehajB7FrTGQ+7gt>)}w)odSIPV7@r zTM`pLHl6nQzZt%VmbGNZPQ@p=zh&qOaoBE4`x>{Ppm5IE!ijTd70#VAzA$JH<`hnz zIlZ)S?6lGag_9;17SEY5Z_13BJ!Z}+Z8fKKM(NzKa|?C%&>W-9+_HHSrpz2VXXa_8 z^*~tJ1OKrnG8ZRM57S^)68F!+I4?2}fV3+fP*F|KE!-S8rYY z->H6^#hTdvo!m>tPn={6QQ$a@NsCqZKVjjr`03;4X<2AL{iy$)as&&qrm}GCtSJ=0 z7Hb>x_~~<}%q{F$dis>{rG>+K4em9(c=$gpeE%OV@l?4L=6`u|wJwy6oiW~S5(=Ai zj@RbM2`0Hjt3$zLZL^$`38fRq&YM0HHWbEYg)lWZHf>DuF8_RIalY>U8DLUt@QEIcZ*Kt!)va@qi z+|-Qxl$6xuD*0|KDWz`mv!0uhoRd?S>c*5JHTmKB7GEoQZxEl_C5&A?-%Tw@?c(Mq z_A5}o#;M8bmy%LFrJ9>kIn_<6+bG3Pt&>tkZN{pnv`Vd#Qmt)Dv()4T`RZFer9=Ic zx&=BhmlR9tkW$S^RcQj<)a1$qDYcY^`~R@_9^i3R*V^zoQ#6{9Ez6QDxqDo&0V7$( z6)<=-MH*Yu$TK4sO2)Dzmtf06l1&N45FkJr2_b}%012stgai@-7cLM&5&|R;(r5uf z8W36_!Q8;*d*8j+KIhC>aPRj&-~IpR`JeAR8olSN-Pc}w?X}A}dwy`nEaasLnXU0* z{|!i{93R6&um;|y2W|f;swClPa5AD+LFOX}vck~wRA_AM@r3>wLr%nKW~el$vUq0%XF5@cW!rnZlHGaBICLd*xmbI$kk4caotf@-$0452 z^&(h2)78_N%)>)(cN)&wLRT)|Q^-ReE#Aem$--7QP%N7$bZ7Dim`i5!$pri-JLCA} zvO0`<+JGDsVu^TDAs3Hz7n0qHLYouE+MZ;4p{+9$Usp)P^07j9Z&zCq(PXoktmOvJ z#nVd*`Az9!QVaa0ov6AqgdJu+y{Qzko=YE>bleq#db@MIJv|xnxRCB* z4Ho%HcNcn*u8A_9-Q1JUfR&w{g`P~hJDFQ5jK*;Hp{qZ8f6bShnl^(d)}XS%zSaf%%ap6iXrA>EEo zBkJpWlfB783cPTfAOh+9X6KQOp)1zCS=jGJp;({GBvTvs};BF`pciOs5owKX>jwg|QgE)`rRxKePHwP$#6 z$iuo=dwv<3q}%F69%7v;nL?%~>8T%46>Zscdq*CfZqBKDBTlJ!Cu;_~4zf*F+h!;L zS1QmhTMurRD^Y+Vi_}+()K`ntSBunF%X0Cz!jmsFs+K|)YE4J6%H!0V zYfI%+mg$ygUhZ+r^yCV?8#We_2{6WGGb*F0;K?hi+byEUUl05-Rg!w3LVM7XW1UJz zd!mCJEmawCL#l3q(K`HqY@nhF$xZQOGU2HQVI+End<<%6U2^k5jX-Ou9BK=E%=Bh) zgC?EoOvm$9p@1RH*vi6~CqKCyvQ4>m^P{>2lz3!t6n2y5Vr!FNvy(~HRFj!>aYHVO zW;q#G!Vh#Ah1ht+w(*F%Pw}vm!F7L9LezCuLQIVpr&hovK0B1pr0Q0|fMrT6dkWK& zZZ7Q?yE5qXbnjyA+B390%J)$`LE`C^ru-L#wSy{}0VxAf0UWmoxz1dh?dMPLAL`y>Ytu(ZOL+*e@r1+Ch zcO}s-JV`(rmKWl&o_sIu53xhEbZKTv_Pp5=(kdm;i59PV$g!5w3A|!u)N~J;SuPt# z3yH<^=?$)fQDiU)+q;X*!AuTSn$MtjHl5ozvkiLAp|Rgn7S$4|Kup?FQE0xf8hX7t zNvkn5a2TSV7@+u?imVC6aIcxulirlkBU)Af4$JZhUw%lA+ zi$FXZgM18f^i&w#vu*4Y%w`k@_wiE?rd(8QnG}*l19A-p!%$;e8C7LM8FvT)Y^a0! zQ{xQL^|Ayt+EmhSqIEAw@+{;!V2pa|Q}q?^!TqILDm`uWl>~b&z^ZXJ}71d&;0HfMX1H>)8#-M6jRol)fA4yu%u z>=>A0e7eygZ!1b9O^d_$qaz5?IIJ%U;g#be2X}PDrb}HpZtbo_61^O!cuambzqH<< z>{QR6%QjQH16Xx{77eW$mTFk0fi@Go(Bc9VX;zMAj0vO#9{Gl(zK?<)*MqmoXb-}x z5|+4)AmvC;iz5K0yD$Rb8ML@;&=M!1zQc=J*xJI=Tz zn`}?#AV?h2nTj)cEE-Pi*)>qu-8XttVHXsr+pLwnsI2+UL`IpSjy>;Y25fVsyJTeU zI(VCXQHT;oyCGcJ(__tSGM+@gD0UEfcGXMb^G2LO8yWGkhh{ma7Tio`^V(F-c=G|7 zMlZHWtkve_#pY_FBi+@-S&u|INxm#CjNv9ePCQ^vJ41Dh%!2y>-x= zMYQ2foKV4kPuwomD<3Y^D;zGh)v0*XHFd@|a~|TLNdV-1c>#HM`GQz5F@tFVT3&Hj zUK+j0>)Lw%hJ{)y@z5qQd524g37VqBqiblUJ3Eu@7{_>KfjS|+IZt-Sjlor%ru^-( zuCCbl4Z9n6V;yJl!07PeZNt%q?a_uz zOSA!V(yRNCfrf3n2S-QywhuP!8XVd_wqtb@NV>;t;M@|Pw(TA2AKSTSs9_ZAPry;o z_^B`F*~2DO4yWjJN8k+2T{gm9K|~QPf;pcc!^sSmH`L9FgF6g2I|olyIYT0t*s->BXZkojGv=0uEwFjq zHms@M47+|y+pzZQ)$ZUE3U^R5aT6ZbgWC#Rt&On{td%@Oki&BiJL0jpJF{SFz_cDU zo$F4cVO}cPia(dKovf9z(R*={j|lX1%tM8WGWa zQyM56SJ;MOo__Y`J^^LU%I8$~LApcsR@@!(WOTh3s>~;pOYpVIDYE0MsKn%VdlFr=cXC5>z!`J9 z5mM*t=_)4@GaGE$3G@Qw&kYh!Dy9`RG}TRvGt}m+iJF;&2xs-2jx$){FdyY-eC6$P%*XE}p z?83YjW_38V!qqK@sT~`!$QEDcnH4oP4~yDc@o0i>Z`7vx9}lY`0wwL=tBBMHT`h08 zl_P?b@Ty0p20ROJqMWcVz{#&;_P>`ZR`xCwr*|G-i$`yFYy&hRC*eFfXC*5|%PGUI zgH;b&D^?FYYf8E`wPW#Lk2##Ism`4$JJYSW%;iD1`xwu)#Tp*j*@YpACqGDUMTri| z87m#_74y*Rt%GNSv{j#V^1`;_=w5a%30bpAU@&SLJ9;CwPp&g*FM5=fXkI2uamgXI z5~m$kh^JLD9W^{SvU7OH;7H#tPwuHvmMg7l66wLh7Pt=C^LP_YHts?vRh+STTyZH1 z@t#q+!ztH3prR~@kx-lkwzF}RgA7bNHzW%9c?}#Pxg7MUte$M9BaKxeEaP=!)aF@U zL}zD~pwsy@W;l;SYtxGdtu3fHHQ7DRjJM3JddE&e^5#iMZk}kTjISuftJmrm66Ye! zK)|FiUb^EXtR^=~!+I?}6W=(=LeSiFQNx^K(N&+)!X^t<30bI0$U;>@7OE00-jNq{ zke<#Obj3D_83Q*7$;t|+1(g_Z zYKK@G7j5;*F=pyZx-r%qr~M1LjcH6)o2b|cB+>3nL@Aj3#k()!?JzUUG_m8)Rm2=@ zVkx%J9!qo{SnaUJ)+1c6CRmgQ`GFTu$ zSK6B_TA)#uZ1JR;nsF~$#1f8oU=~Mj0WvHx8RtmSBg`qR>A?b`9w8IsSpVAUl)x*M z*ff*IFbiW)n7$<|FDjC3VzVpHIc)X7a;7XXU3fjn+oQ7oU^3qvKO_v zyr|h3fn!za{Z6IqN@120OIL+dXDrv@q+^)b+rx%k(Cbtlt|FmU??wVw&f=-KmNAo% zH1ctV2kwlwcfJrU&UJ82Wwl~)kiAZeM{i|unb4C-w!<9e{C07UmldyIkH3G&EeUzH zIhj{tlf<3@wHL}wMs+M3)7^>8M%e?P$E;qucN~CnVR=`2Sa(uEscM;bHd6*}BH;51 z=337-=s5ztan7*Uvmz>{p;q{Mi*8X&s~D46$4qh=vmKkkNBYJF6`x9G5w!(ULUg+i zRUhv)3{V3Sulje!%Wj4;G=SO5n39;uSrM36A^{!botjmP$_Gsl96b7R=X*W9IYq}w ziUzux0%X2KFC?HBl$tHFiy^`lJ2zu!&~^pxnR-I5{>wVS2@g+cYED^qQmG-X$@ zq6I?pKwnX57VmR(t<<7^iusLsO+}0o^*UGwSFV-9lc7gUk09c(7&X~zC8}YV8TwgV ztyW7FCU;&nnM!wJKEb;->9&|$F7DkBnA9^I$%9OZrHT!T*|I4rDYj-(Y|SKWO)xNP z>I9~y_O2)El0`cmRPIg7GLu(1Y(-Oxdg{M-N)!#zotW?lW-d!>HJ8;(gL-99FAQ>B zFqd8Bh>zN!X>`6@&xjbqr;@1v?+ANb5AJLg^OEh=y|bs!O< zOYBhBA*p!SCff&PH=1lllRap%1x<6iO*Rn9?h<@%%?O0FE3{O1j@RXbo@bR6pQOj+ zlwhWF(X(4z4ZtW?*4SVy(QI;uw|ZRC$FN~lZ-vt-aE2?T%(-r78%@$FLDwom4*od^`t8;;niu#I;WGhyRN^4cZ($2%rdT2n#7a}Mvs$^Ww~D+N)9&qII7s? zlQT1f+5DUmTg;VttbObRmBE!7mzd3=+*U16+8 zi_k3b)T6SsDLtb*um)JN+fOx)@lBhig3wD$8+TCaa`a%M(-}2-r%04ym&q@52c|ya zow2SS3@coAq4n#%u&#D+eCzhZ&EiZ|ZDTGDiD^CQluMX`R}I`GWRAieXvrF#cLG-x z3kAq^6y;7U_xG97f(O?Cbh#Ak!Q|B@><%iKxS$z}#a?B`Iy`aLRpOaK2R3AT@(!b> z1G|1<+CX~2f|3n&Fb(u-0~as3h-o4<0z|cgw+D>fWt`P$G!-+0LDS^1uOW_2!S3vg ziKa9>hah6Nn<%}?4r_lUV?-G>DHI#X-NwbwO+Eh6J9xmUa~e^ z6cvT|J>8X=vk~*P-gypM@6cONeqJlgrFxs3OZ8eKF4gT`l`0}{-Q2m}yt8&L)vMWD zsyo*f@4|elUTR=_i|dsa=~ngJ9h!&XxGF2{LG_N04xm~hmufuYXV>(Dk>Z3_*>_(; zDH*4`Vd9Ws@2eX|f(}~sQZEPK?Fq$b>1}heAG3HIV+x=&qcUh|7phfUmzQc%!Ds_5 z&yFhRbg@$qH>-Ge#LS(TB+Mj#t~ZC*B@$du+cTt2=`%hQAGl?wWQ#EQ8S`j5cUsAl zM{c<0xP!*Hny7Z&P%oG~FKT?M$~kKAF0*V`i_3Tw5WRv^CTcG>A~O|U6fN4c!)8+o zQ!9GM&q3R5F}toB1$H=QO5T6bTQ<2HwNwFQb1@hy$`aweF^D?e}-aSUX~U)c&x7&)|-rpZ$w1W;u1PX zM_N+U79*D}YJB9KQ*g{8HJRR?<@r9Y&Aba!ze=V|lBPT~!?Vd$K}~Br zl8oulbQ@QbJu!;fFOmya6y1y}li@u$0#zY%SssqCcRV;9Zl)=27f9J%&h}3Jbz}9` zQzb?I-qRsv_3zpQkVPoy>np+sJvX05*`;5}Qy40q?PI z+TG3IwmOTZ-tt#3;yX0I`qGN?h^K&hW#6R) zRM`>^fnQ5;FF!sDfNvOjuAuU7K45~9dEEHnk+Ks1{PK-^`SB@%;`l-;K9|4pWi$!G z@30j6SKpQQ)CWJ@;$D9EF7_WTiNDwthf|dJk0}3cto+K2d--t)hnrW@@u?xt<;Rg6 z-ph{zIlPzO`SgpX`qejbTpxbtlP|`d-+y#3f00y^-~7;*d-*MVD#~;Dt(htZloGaq zYSh2_J{ayP_tmJsg+RJf?yFIMZSu@Iu10+^9NqPExwWO}Ic)8gXY!>Q{QMA*7e2U# z!$-g$^OcGPW7dKJG0K&?)S6T8jMVqz+v?iQY^imh^c6J%W1$ zKO}gLAdkvmxQ`27D#(MtNWVt#%Yruu^80*r$MJXy?-aaO@P5Hx2>x0SpU_wSpB4Oz z;7fw93-XhGjNgU|CYB3M608%PCAdIvu^`VeWw=#>YXsW`y9Ij%PY~=E{Gi~;g6gb$ z#CNtlUm*B#!OsX@CHO_buM6HJc&p&Q3*IOApx~o|Je7(0e^&6Xg0BevQ}7)@9=ApR z6@t}*(*&b}iv)RQ7yU02JX$a=$n!eszFu&XU_o%3;BLV&L7t<@aOVnMBzTG7<$_-j z{IVd=qhz?71#cI;NARbD{5UxM{YLO9!9NPVDEN25w*;xE7%n7ODL6%Nrr>XrGiHZwh5*MdjvNNZWTO9a7^$_ z!3zZW5q9S1bAs0ienaqP!8-)+6a2a0Zv~$bd|vSHg8vc>z_emI69wx8=LjAu*erOY zAU_btaGip^f*%mvE;uZBn&7#D9~JzJ;O7OuBKU2=9|+zf$m1}X?xTV{tDDb%5`04(* z#|kC|*9oo{+$eaWV87r_!99X|1wSNsj^IZGKQ4Hw;1z<`2!2`c2Ep$L-YR&f;Jt$P z3;sgz*Md(7J}dYa!IuPI7ko?bUBMuRQsire;AFvi!C8Xy1rHNkBDhTOD8ZOuyI_}K zPH?keL2yv;Btf3q$o!llc&6Zo1$ks0-9IUKnc!7|*9m@A@J2x%n#ypu3Em}mpWp+6 zj|l!&@F~IP1fLgtMerYj{}Qw@v|>6T!HI%3g3|=&2p%H1Sg=`eh2UzzxFC=9W&9bz zUcuu9`vkWO?iL&sJWY@X(=wj(1wShIDZ$GHKQDN_;0=P`6}(OGZo!`j{#@|af=>!Q zC&+V4nf_~n2L#_0EW^N#?h^%T1!oA(6Ff|?NpOYWF@j0KPQjeuae{qUA{ZCU3l0kI z6a2K`HG;Pa{#5WW!G8$)@Y!jm6BTR}JX&zA;3mOcg8Kzu7mVP8?TlxJ;1Plyg1v&f z18pB8*o(8km$)2kMoFSt}NDY!v! zyWpvUpAo!H@HWAp2|gkCH^FxVd7>86og>&J7!%A2_6v>)o-g=W!LJJbK=6LS#|2*$ zd|PlLCUBYVY{4ahYXnaa+$ngDAW!>bxGxFbB6y$RZv=VrI{opuO=1`mpTy~cJV=qx zJgtD(CAd>?pWuyxcL?4i_^9Axf=>(nN$^F%*96}bd`HlaiEWiH!AXKs1ZN1&6D>z|>PJf!< zLcvzS#{^#xd{Z!hIcw&7n&2UVM-q>)tYhVQ9TBp7oIGzM;!uze3JweXLqzD1i{<$; zalb55#^d8&vOJ9 z2)$MC7$R)EE_vQW#P0;bKB4cD=V8HpLO+LyG2tche3iIgBY3^gzb(%^mW=V=CG?*W zF<0}LJpYl1-(Lk^5_$j!3XondIFX3*O_k@Ff^&s_ggiG1E+ZnHW5hiz^e({-;(ol~ z9-)s4o+m#7^JR;Wbn4nq@!SmVj z%=3uo{#n5<2!2tJXA{x=HoeWaMBCpP{FCF+L?%K(I)K z$8bfViWl*~>`?Kk_z@q}iHbK$gr^09Dm};_RHBkYl`hgzatKuO-$>_J{8&$Fz8CR- zkI#trDI(&tId6%04kIF*N`IcLBf^i07tbnQ#IuI!;Wd_D4uP+j_hGJ8;h21mBRqvZ^T;x+xA$E`o3@L){((| zmd6!`iFhCTM*4=fP?_?0X@!f=Hh_G`Rf9HeZ^>;U($MbhpiNA;6!{4_` z{5^wb>IHL|bbky2(=~km8}6we%w_!j5ClwLT5H7NN4vB>LU*lpe$XH5fotxJ&s^nr zcnAHTxs2NrAb8_@8}Y4y{mS^z*mGV5`B$8(Qc>xc6!Yx6k% z-h!Jq-J>r6pW%<`lHaBr6OgDk-5G~yy#z1nGHxuNH@?mbHIEn{hP6(7b4ubn3GuB_ zG3kFMz8NL)eGKsp!wci19Gd(!m&A7i;%hg;4Syy+?oIIK?`_1#euVK+Rhsx#OMFeB z@%sB>%i3|YzUP0&$6rT@zvFi3GZg8Em+{vt{xlWGa>L)p%ma|=^5R|yZ~m5E!9)L`j7tvGg`0S5mJq!Xx5G+#hv7VWx(HXe4j)we!HO^(? z!xTr6zw42|5#tCqb30NP80&A`vm`24^NObBE1OzYwzfpEQ?IGn^MCpBrO{~Xs%Cr^ zkk^*T*~!k7KATD>Z=>fo@scv|X+;le9eAj97~Gp~x#X>Y7416rCi_#?Yj;nuKHYoZ zi0G`&J+DvQn#3KRs_uEc+>X6r#r|;7r@wn~+rJ(zpEqyJzH<7_wQKFGvj?J8om;Fc zrhSKZ*3}=|Lj2jOzE|(|?LU0d!@k=dIA`iyD_XuTw07E9_P`NM@mKecwgG)NHQh1X z{?T(@`HOGu@Bd>qphqWz2S z{_Z```_@c+*ovNbAh2$@9rUJ0FXH`Gbn#nAi?mA}8Y)qz4_5k9*1X|ckjJX>P8+<- zA2_0?tQ)x)OyI66l{zptI(^G9N~!Zp?k`$<;CnTv22vAK>ux@2$E9ysci-`vH7WMQ zyzUL)NyT@{qX+Ih??B-0h8>GjkDod%RsHJSlL8Mve$g+#+xCKQ-s9(7d}>uIXuek; zsY;d4n>u&Oy6Iz6)~1l&wBdPM4%}%ktQ&si^{V|Byk2!-)!NBB=DxAtp1h@c$9_DA zGt*L;H|`!;nR@rl|9m&JuFyAo)Xl@4k5?dVB_aIBx`^i!)|&D)Ro?>-pP9a{5@pOm zCZ;Osh~th=KYYF1*Y<|h_S{8RefLsGM+Ndd^`Lz3N4~3Gz1w>A5#)M7IdWaTw(US; zRbcJRVXstF-6^~hS#a|6e{cRT2mXJ+f$J8UJ}Y2%q9d8`9T+RSVeviVDV#45c7!iW0s5T1jH zWIKE(r~8q6Bpdz%D1k6HFa*P0(-BGdKHP`GX%x6T+=}~f_>=G-3G?9Jitx|iXF_-< zQk@w7H{`f7oSlm^!Nc!HVRnVDgU`v~Z=jE^4&Mtd)P!5%r#8$5pef-W!Dn5#1+Mks zJ7Dim4L<`5bz1l>O!rO?PXT>Km|IO|hQBxu9ep^06z7B!sGDf`7Nj^gd_Pi|7d{@b z%@1=jc0u?_+#eF2cPKj7@a?GD!SEfp|7rM8Y+t=Ud^}41voN=VJrEv(758BH5|sC$ zFb{73dE|Dac!V9f0oiJ>Biww|Xh#-e9J<7gOn_b0WJkV+3|?YKz5prslpVPW8NJkw zY(pMDV@H0Bj9q3&uE5i0?Fjb_Ty95j_^tIhJF*U0xx$V#!|h5t@+D;HDm(Hf5_-dq z#89|@*pajSJTE!&F%aKGLg3Z`JMuwfY?Ci?1`@i%7r78w{;NN-tK71l_eZ_~A$!3e zIU8}l=#MOeas4-c&COa4eLnDMedQjdCn#UHs4jC<7|IRPoW=8rTXz0N@7w}`qc z5cvUE(jACgh}zEtB9jqWParZ4v8)e7u0wj+K;$k!E)Y2$>E#2F45oGDhlOlhHpnYXhgj;7Xtcg4aE?ra;;f8~%MUe(JheeS*d=A$~ zx=_B8>mx15*+_llAtXCmA9)%+$Lb^8nY6b)av^-~tB<^f6i%s+%tk$&S|52796YT) z(htc!y*{!JRs5m)$P>um8TFC*D8rfc5iY=-RUdg0!OyObJO(fOkq}Zi2LX_YHCIQ5 zkZkPg$mu9w+trabz}Cdokv=dvd3EH&$aU)K$Sd&DesyFHIMH)&iN9cG1sy#;LWw*=SO(+Bq*OM;HCwV@M+#~(fCr{T!;dGhBw@1av5*J zDCBAVxOom0emZZsqm5&Oiac0^vkk3^XHhO6Z$1G|@@18Z%TPZ!F43ykf&vD4(+-&^ z$UNL4j&E&_jQc=I7pYI*YuRPq$wyo|Cl*A?7ggqMlngv|SRa{=@m zU$Lq92bdY)4eA7?z)dSMU&fnm#7timPow?Vyg3&P_wj}+j0|T@_#Gk&4%z-c;<ilDh^catY?-iQAF2k%<=~snLng;(lymAM&_&;x^R4zKIi2=ci0;M)iJZ z;&;J}GbT18n`cd|0UOS?0=pnsWlQ}7h_3Q!MEz^rOgaKLwiV(|#4-|;3-=c)m!K7T znl2s_f8j>cZc|-Q;XGXN4ZCo57seHmbbZ4*jw& z_z2u;ra~e^zpAUJTg`XD>(CQ*6_>!pstSbuSQmZ?x3zabZ-o9_HVi2&pxj=T92^Bo z=#9DxMvZBg(A#z4{fuBWT1V(V>t_52WM6r?H5p%6vqJuQO@QoM)xOYyx*&J%)vRK6 z|D&#+o@*wdp@stW6-Q?HjaiyiKZCUvD4%N8ehnT%vxQ*STeTg`N3>qE%|@JHTYY^njnFk;q~~e% znr)jbvHn%I~$_mx8bRFCaZW;bcVy756uT*vmt;x)#!0T#~A{+^9md4@rD5I z%p!+RFa&UCJ<@YhNnXf z)J~)zj7CLyL3XYsGsX-7-1&D{T%o;&0PcK`wYtv`z@3pfAe>?d;LaHOw9sjW0PY-p z2neSe0=Sc;j}I9FxHIEW5Y8|JaEBZ7LT4HRxbuBx>?}h7cYefV&o%^b=LgK`enS9v z+Sv}yH3ZF_-O=E&D0t1kvyS&fwPrp6woB;4(F*d7iuGgB@MbWq*1rJsPees+&VeAX zAfGgZ*~mA2Tw(~btlC3J_>>{cv}%`-@M%MsVbv~T9G4oxbZ7+n_>3V;gFdH^%M1bf ze2hLmYY5QiXOVEZA=Fv5-=%bY&Jd&l^IORr_m7(H9H>(!%Wnp=%5Q(gI7x3SDamke1h2)7KdSq@|uZ_=|=B zX$epvUT+AHmN)6+%Z31Hd5X>ND~14RnM}f04FS?}GIRPhLx8k=o670yh5%{d2At40 z3<1(|7tFQL4Tb<|xoHsyHyVPCo}L2sZ9|~=1VR@^gJ*#WH9OdNFOKR?^9hRPP0-OEp+;Ywto_O}#-`%UKo){IcyJzxmn6MB<-qrp~qu2F9HNpG?rdNTC$Xa&=v zM)+McoMDU?lTnY0N(rNGpm2W`4URE_Pf=a}MpVkjs0W^mRxoOo`cKjDwT$2+Y*~Mi zGGV+iIi0ma&zmyR_K1d_jRx;ygx%!%bJ3|ZKx-ybG5;-EK^Lo%3H};Cu}hJ_8_{qz zs78gr7ap`J zOtMO{V3pB-CG&8iOPsnt5SkJV-wa(ng*Js4MGK-eKLx338asWWS7=f;S87Y3$6J?CHu7`k?mI zVo(1tjfaz>H5@=JwWm?1ud%1^W8I#wJ+;}>KSxg&L~H(l9472(RBhMV(9=*Sm*y9d-}=r^oWk|hxYU{`1s3c4JXxpWKW~qSib2WA@%p# zlg~H((|mk7T5~cy1$@&e8~c6JKTqn*(VC5*UhA923dJZ(S#S3udy4f(Vdf9_Wh5w< zr;JOT6?%v+BuqFzim2X=`dK>=k6RXoTVR3IeuV=3{e`a5zLA6<7y{I3hJtpxA%Hn( zbvG>xaxZJmE$nx`yHGdmC^8wkV_^k%!!n6`7ltb!TeU~Bk^R_2fOZ@s;U|WGZlHsN zpBe(XfeZ;hGX!Y;4J15Z2+;Z`lJKA*Ae#duJY)#a`X`a_b3=gE{|_1&4;uoMJeHGC zPlf;`A0gqFh5#kc7j{FB8UmF3bP|4L2vG9#NcfE*K!qPp!fy=$Dx5Eeh8{BnXzW`_ zc-#=6vF{?`2}6Kd`Uwe78Ui%-FGzUG5TLPtOTzCB0UG;h5}q~$Xl%Yy8hXYMps~L~ zz5A>oKx2Q4gg+Pp>I@Zo*TNt-^VZzKioHiFHcrd&xrG(1a#rjM3&Uq&_*px^{_Jli z0%+`$NO;K*P}3tMyle=l>C;Gf#Sl=_`$>4!5YXX&goM`&0agDA68>%osQSxDc-;_C z^;eVdh9RKpzeK`63;|XDaW?Tc4FOeu83_jr0aedeb3$(!0;>MYB>aaVpz41Ly%T!d z5YQDrOu{>c5V30cT1n_#LqMfG$$VIgq;a8Ae#!6CmRE9k z?_X5G${@=li^3_`XSF|LFFV0R0G2;OLZu;q<-a4L$`HWvr%9M%2w-_63c?IS0EZ`& zFw+pg;X3Gu&}>5hyJnLx#}L4-v)H(zh5&Z0qK~ifK8v@!A_wt91Fa)%v&yvt! z2xv=RAfeF^P;Fl!VTmE2+CIQuu*ne6mhR%I0YIt&42kCTu#1eBdyr9*2C0cFpTu+9)r_FGx@PD6km`37a7%Mdg( zmM;pPiUQR9ip*Fk%ou=MsC!Wb*<@AKhQ75hd>uSZVMk<5VP6rLLd8-(g|a?j3OQ9} zP1wX>J&XK|aK<}yZ?7z$#9Y`ZIF+xhd=@U@2ar)K+>Rz^hxbF0eBt%zv++3~ekG&4 z-~WAhD!-0>fDX2!vKk@65%g$Q7&{^m>_1=-_^iMq(0Ap#{Vy@V_gF7Fz;I=n0lvfB zhaa5J0JCxL3v>G^(y4*QEkDyg8=lJlfqxS0+{!Tq>p|RBm~W=pR$$cv__@g6ORo#a zKApnHE5A&y#~>mrd^*~#FWenfaUaUKFZb_ffHP?q>i}0)KFk1X5vvvc10q7)e}QxP zm;K*?!_0d?sw)3l)okFb4bW)i->CdK{93c#1*QB3^$?hKCTgkto9dx_)`N%Q;YRf^ z!3yMIbC!S0&mHWu1Lb#wuSd8!PlK`LKb%K)*uH>oP7f-h{JsS&C*~=A(VZhFTjlr9 zWZrDs=bN*YmGoc`4;)(5=%=llqTF8}Q;RxAAbt+|2n z+k-zw%JcZ0-R4(I(5tft4SRe5IS;80cmgQ`l@{}g7@nza_Kw*09XwV(uM)xkt7 z|NV?l!J&K>-y<%6uKq4OOqg{q6aTAvsI=w>ronp|V_6W0v6#>Mnefb?FyZo-s=DDa zYaOJe{Iz=CTeDsx^IorJkO0C@C*BSDD}Tek5ci=x{+0iW!xLR+Z&scMO4z6B>?hzH z_QQO<($|E!vc`mbw&HBlb6t5bNe>OM+uwRZIuJO%2eM)5S?u09V> z<#peJpq4k<)mPwYLfvMJ3d@hwPgQm2vVM|w_04drt$T&C)T7;|)~!a)%8#?F*>B9O zdxX`!Rl7y4L%3Aj1c!yo`7eflDB-ujun?*916x?Yqtq?4tNb%_+P~t@{6MF1VMetJ znYHkfh;8Bh_=kwL89&Uv@&n?X{@h~VQ}-pzZ!4*Nm7ni65B;9V#6pnW8hvRZD2z}Yw06?Esd6hHgwE8($qJ9Bu0 z-9#CpX5+O~W%NdS217#vEo94D#&f0ZZ`m_+BrO@X|1;e>J6yBMAq;iqHSsAK5?p%cFq3+J*A zLPXG+mVKfQc@FP{tKCdeFj|lk;en(R4 z+AlOw>xL09h~JS^zV?evRK9$5;&9R?E&%OsP4|P=kLMHdJ4y+~%St9L#q%dg`zN|H z`zPjy{8rx;#m){!{M+CKi20bu@qElf z_;>6@_}2s%#An$-U+|dAL0EG={>8qHe>Z{Lb`x$gh^7laTya+W7TnkrNc#z0q5(K= zRUTHo0lj8_+$qs5^mX+{v>aWck1t_~&V%36@jJ4Qt?}cVsIY&D=O5#z%k^nht|K5b z^YA-rDV5R}r!$^?cpkzpLG@;TX*yNnO?dt$e#w`kP=-vB#j>vnzJLl%@xGnQbOX4d zv_1lATNMcW&e6~D>o^S&)78g+ASlIh9=&}OF0X^~8mS#8;%NtN{QPJ9eG~pxo&=Zj zAi8AytTg?diW{5%j6daPHr!{@kG1w<{JR1k*V#S3Q}93QkL;(U#93p95QlV~;{sf6LsNrO&Fq6@l-PDLI(kJD5*6lZ!-I1pyItb*v&fF~;N;2iTlOS~&aGMU*@HgTWhb$7EF z1(`)w!CdlODY68f=M4;5VJ)$O7C;EBL#Eh^rfJ4545|uSQ1xU1fi~XwF)dJ@))S1U_1EB`)evk3hJD3cLP1Cz|!RQ7Led@S~4^6NZcf1;6);OB-yqwVtsZ zj-PGy61L#SaOJGAYO}~M>z0=-H(PrCwvyS%&u*nfdA^^`&a|GBg1@F(>25k@I#LAUtczf z{CS9eMPMEItY$}iZDo$0QS4Q7lqrI%_%9dvtBH9-@+sc0#bc4rl^`6Wh>nObpq9D- z?)3E;K|?VZ6}rJK^1M`#9O1=mo9lzPVc|@pFm$F#wONH9tHFEGjcKwamdh^!WYulK zk9B1(7M|to#E-?_fFH|bt|M^6-*Wuc;AgHT+|b_#@Y{l)xk%^lNc<9p2=w~h<)QQT z|0KVz4s%|XgC?K-uS)FB)$jR1a_z>(B_n-HaE9NK(UJZo>it3Mf8a1&q|rCBdr7X1XK&0?TaoP&8+TFi*N#Cwr|F5Up zzk77&=#s?XzMcJpOR~xCWG;)-U1JS9huAS-WN)jf zH7KFK*>*5kGd*aR`A@Nf)BWLSaA9N6_MZ~P4WDq^sPCdJ!G$w}!LqL431xO;u(A>N zOM+p`7qDxC6@;o_lu%~tM|xNutixllY-z9(SRM_A%jN}V;H zgRSs3t1(!9bTCrZ5}b%925tcc%MPhi5!?PqG+5`~$IRYr^Y)>$qHtamtoC2eqD>Dj zRQ`9Ap@hFY%MRv1tVMBa5Sf4H(ZS^?iw`eT*e*}L>w}*uHOf~Mle1p8dz9O_PQRv8 z4Wgbb8F&TrKFGjyWI*xs;O%nP>74mQsLZAoo# z0*Jvf{{&RJVo%a|vlj$c9WLI$8Ra~&%)htM@xW?W<=+Rw98}bjV9*~%`H)k*!Q$cU z4So-c=CN)NnST_eWCRNvk7p6P5O69ObvpUf9K`4pI8Vifw_iN5eH;(L+FDlRZ@>cE z|CKYN!E*oOK1wa`QJBfm;6(qOWY83yB{)D1l_xmgerB{ru{c<^`siSi-pYD$|2xD|O-9!-4YrQzGXJ%3TIhd<2`B=@8F{!8R1XVS*jwRc zE^-tuYqkTv;2i%?f_BhfTf3yp4v^}<<#f_#`2VEnWsRD8#p!lgW7*MmwAAhJGC$mc z;kvR-XlFB2%uA)+`oHSokYdfGXw-*SjXd>m59^`E9{~wMK`jCagv3Wr@FZC24b=KOOC=Q1^4-(Lwh>SR*Fudy~C5&JD$M zii9%})A`NLBL%4|)~(LELm6_8gR0bACZ|%?M^YotD6i@6M|Yk+Xk~knlrO_q36#RI z&8Y573P(|@!>m1}9KZ&MVh+eYS90vz&3>EXSHR zud?sb6#cBoDB3@@VR`EsMi<^DqZ7G3BRK&;O zci+IkNI^u-AwpVr4jHN=h&Zzvg0GJKJxJQJn~KhSH$|4zc~G}ukUBln$sW$XgG$j= zX3oA-m4jnYHA-c*NM*H1WwpqO^eu8EJ&sJ*{#RL}asq5_Y|pTh5aq!=lb#yED`BV^ z@UM{E6i+4-Ua`tS19n5)|H;4 zza3_xmN#1?gQGB@t&NF1YFcH#RUcp8*4j)t0LdwUY6Qtly13;iz2uQ5x7E9ips#;y z=e|A~+lA3Rdq?`wzVh*&tmw22ZLz%4=4nc%Cn~7cu1q#5%Fx=iXK1@R4&2nOoPcfW zRUOuxMo~PCLiA`h*_kZTwH~I$dh;F7Xz92<=DJW&rah%^aJN_YI7eYRtz0SsWr=lm z73=45PWg?+yLviuO~w9u{11 zK0@Bmh4ivRQW`6lj9aQUU5`8;R66-i^xjtPw9)*|{*ww$3F7K3QN^BSj}Wj`WKswV zQE=6}t95u(vpR0PRM1Vv!8!D92kAoNtPZC)>~`unn{3CyyEvSbhX9u}ILdXA<`pKG z81*61CQ6>y%Wk}o>&RsDZl|hf&4sqjIJMjO)yEQRE5xJd~)+BCMb+?!I={i!ki|pOu=q#JDJ*SaeSGEZ$f!YA61E%;MhAf zR@mKls?|H%w|y|BW<*r0GLfxhTf|YS(L-*(hsWa&_y3if;W|b|Xy0a9-BG=*R zcTHo~XNwyXS+TA~_mJ_HX16tGlRe28&Rj+(5BrdPu+qwL7zZYUj&3PYCuwO8o>4?6 zbdPJXnyj?Px^Nt}$%9Q(@HLeN#-CSS@785VZC#qtgha4>IYTV|8vXoAK&(b>iH z@WeK1qwkyGb{vR7e zKd^IbXWuRijs`GV;>;@dhdLo0?Wa|KHW_DHo811Evf}=$!sjk7@dqz&{>KlRv=C^!x+FEtV2Z&8ZSX@y7=ySja z4h5tYc6!ZUt?83pJs8$HGR&rq^c(?DgCUUu)gqKhsAoh>igC_^c>6u$(6JGnReaqz zYLCaVE4|BHK2+eSCmr*n%PNh>BJz~!d_U|3>_ERQ1uAC-fanuC0 z7S)X7p6u-G?TkT!i(9OkD9B?Cz$!MbH3NIQV;j)k*uT0lsY#u7EShK&&v8)7kCRO} z?H#H|*%+>V8_%`H8Xnn6sZ+ydnh@J{&i7%(Y7dqXD2-11tbC_=QGF()BTk?rHs#Fq zq$#7E&d^@;$TK0+1c_!n@=P@Ak!J$a1#NprJsrPVs3;7N>?;fospN~rMazkF3q|%F z=RF{b$Ym<0c?nY;1V{W(9gsegQIEORlg)IbF)x5B?uNOSapxtJ^s&s8z%+&)$3fn7 z|K8ey$T-R*+tl#xpfMg5^mwAHs=_;im+s>HA+?NVn)K2M8OA4C^e{dl!}x>@;}bHB zPslJnfnmHb%`+$D$~G$`2_wm{z>I0Ujn%jbdmv6-7)6+BN9jE=bK=8^EQWcPtYThn zLmX?0UM=F85|z$Lz5dB?1K%D4#UH4M-wY$zai6^2V*=_5;U(&4l%8OiNKOfOPYh;@(*ZSF5=*5f% z^mWowBmd$y>ou`ea-2?+QM{V(D-_T#6ne6#@7y|TVCSe3aHwssq5#Kp>{A@3JNc73 zF}h62i{VDmXhrL8{b~B59>VdhyN2TF1Ebl|^>igH4*5HKWXKQ3x(bM59c#-$v^Bdh zo-ENsRGvz?=QgJE@eUI)YrAOP$f<4`Uzimrv}2BpEx1Eku*t7U3IfSDOZ`F97bX;Z>j(JGf z7EU0=tYVvDoGhiVMC2}RP`Rc$GaET|>fyVmM zHaPq5>1vBK8}k#>gWK2&t(=idWC4p1mL5D=oMltPawCP_Mw?1w+NfwI$Q9pQF5a#t zl)U3m2#I2Xbka%bq?6J~C#924N++F^PC6-b?MX~}n(-PGm0By3KGV#WwYVPK88Y^KXR=)$H3uc0!@3k|zPOk7_SYs2Nk+aHA*&Fw2q9|_tMrVI79SNjfe9XyvIr^khr1qOCX`im zpsQD!84@Rx;NFox+Vt??$k)pHb`tT7de}D9ssVEzm#G=eu()PeTr(`Lt?0PsTU_%kuK5<% ze2cqt=&?4;)_U5zleBTba8T<|l`aI*aM#-)ik3Wu?Y-UWx-%QQ^==|%%&6%bd|uKW zvA1C!35(8ZF5XI~<0Y#G9xYQeEr*>=n6*>`SY=v4SvvXltevUqG1-;4xImVI$}sb) zs>kcvgF!#WFsRcZ&J`g(mNucejHzh#q`91MQtkE5N zM#j{tQ<0_a_U;ZJ&EV8KT46d#cd!uejCJ)usI*o`>P|^i-_W9GNA&1Tw;53!?&J%G z#Y$XEvaufYbDLlc7quG4+BRhYPhoE-yt6{ai87i@s6~D*yPJqr6HCQtDykOdIGAvy z^Y%1+MDx)Y@fxW;+65D?PAuM5($ldSEx)S^>#(v2XELF>G^j}@SiCDyI%T1{m>kSy zwK1e9q&p^*F3`BT-4d6N*o_+(Q##EsOwd5)IY9%^^-?+;=7eC%VBZ{TD0^YNxe|)Hcj)fOtZS`dLj-2VoWuSpAT(jH}%#t3BCN!D!Eejrdsi zIw+AOCX+>`O-+&=#yeJisixe)H>=s5UDUdx$iy0^MQnOc%oAba%*mcRyzaV4cI@4~6}WBJp1!dLY#CpT?LY%0z~{E%eajj~hZ_c(mxIzb(!XOhcF68q*|58j zef8pj(c#70hNBJJqYassXajcGuI@($8n*3*WseEZ25lRzZURZ~HfrEP6P~v19m3N8 zo}q?OOonls#I5SLRN{fbC zDWL|`=7GnobK9^}3P(|=I4#ni<$kOZfh(G$VJp?j!)+R_M4@GvteG|#k6{m0GF4C( zt<`}__skO-&lr`b+c@QG(pCnqEQ}gYdQ>Hu>)*9!)YUdhd*w=ZhM0iDW|JdlszXh0 zzz~mPh~vpOMiAW|lRE8eJ8JQ6J3=4t?2RDbO($;>HK}dPWY>uWq6EvhOHc2v1sex+ z24>MxXV5sLvN3KXaQQCFNv=U_wa4Q}Mh|5Jjg9P%CUp zrMT_ia|IM{FLWs6wtM;UN@Htw5ifqc!d2{EuF`Y)&R4wL%Mahh z{=+5yi(UQrjzKXcqWquWM9Ejj+{+KwV*eAAf4(H9FR$eBWvt2)|CP%BwZ^-8jm>$0 z|Ed!I_|zDjhaE3f&K+<3c&`v&%TX6=(#CUf4*1@od-<)J689RM@20Q)h`@%s_rj;v zO8k2zmg)0lTKDpoypHF$@D%{h<+t$l9M9!fCj+_!zct5wz#YD_Rq{N)i2#iFX|Y4QqR0k({C*pvla|seva#XrRMcOW7D_` zYR2^C_)*`x3nX0OD5YW1M3ZDSRzH|sCHl!ssOcv?^{?;MEQU;lXiC;&Mjt%0s9v`8 zp$gfahxF)*Ai(mi(7M|PUC37MLtx6buT{VJ=|cs8dzPQ38*8akRlLV&-@*Gdb zGgpvba^f@3<0Q5Ut`a;}Fe$iBaJ}G0!4n1h1$PSW5#$%382^U^&k_8H;Kv0o6}&?5 z8bN*qk>PI;{EpzQf_DnuD|o-)F9d%r_=MoIf`1X@fk%x0b-}j;VNfVKKLkbh3c+f@ zX@XI~MS_ij%LI=Wj0>u>wh`ZYdEO*g5ZorXTX0P9LxSfDUL<&l;N^l}5d5;>HwAAN zyj}1f!Ji8LLXcmgVtJnu{G;HDg8cdv-QN;~0#?r1bis23FBJTw;AaItFL=G+4T9elyiM?K!Ji27`&lgKuLYkJd`|EML4H7s{tgJf zD_Dj%Pf4FBSSvU~aGu~{f=z-e1o2556+S80DVP&HPOwjKhv3PArwj5dG3MiAf|m(? zLGY`BHwoS*_(Q=51b-!{&Z0+rf0pN01P=(RGwR_UL5IY2YXoNs9wNvy0Ulp_` zX#drM^97d*CIvSLZWlaN@FKx01#b|%L+~NN=LP>Mh;Lh{eBy&=3Y!FDf?2_S!7;(} z1wSkJRly$!-Y@vL;ERGGjOEFfTEQa(R||Fv76gX{&k_8z;Fkn%5xh_EH-di=JRlgx z;Ew4YBG@9hR`7ViU4mx{enOB(`!W1Yg7*miQt&y!Hw1$iu+V><;3C15f@#6y{ugm? z0v<RXyTDn`p6C^xU!iyxlLBd~2_^^b0i8blJE8%An^5dGs7fU!+!l@F@l5nYnCrWsp zgx5)UyM&KR_>zPlN%)O~WtbMTys;AULyim|E#YzrH%NH9g!fDMwuF3<8T0W~^n`~< z$QRQxe3pb)NO-e^_e=P=gl|ark%T@>Y?%K539BTGNtlvwv4ra-JV(OoCEOw5cM=w0 z;zPO>67sdJ49}Kuv4s5+o+aT`68=m=zHXiQo{;c033p2Pm4tXpqewSG!YT=8NZ2MJ zUkyrneG+bx@Jb1PD&f5nJ}%*_5`HM*mlBqg+VmG%Oe!hOquRv2``Xvi-dPb_>hEulJIQ_cT31`sgh2igrg;# zEa6-UkCSk%gy%?jjf6j!@Bs;*mhf*9ek|d)67s8aEH^A+t%MB{9w*@m65cG~uOz%r z!Y3vClZ1bf@O25_mGBb@xq!=Zvm^{jSSaC032P;sD&dh5@=FHHKU>0i5_U`2BjFke z&yes639ps#MhSl=;Wh~$lkh1CUy$$(33p2Pg@l0-Ha`bQI8wq%62>H4D&c^HXGwUa zgm+5Fx52W0k4yMh2|tjKF9>G5jx`>_VG@p$aFT=(2|FZQCgFMsPnYm)2``iI1_^&D zAwQPQa-NXzWeMMt@Lv*gnUU%8B;@Bv7~U=6w-ScJHh!ptVUBXW#{6@kcXmNe)07CFLO2TmxPM2_|gegMU-o-N9LwFGE zs)Xw#ev=HJBjIL=zm*VU+r2XUh>ZWEgilNSUnTs9#P5{wQ;GjdhQE{07-jQ+03m#h zunZqc2>$r>Z^FqEACcj>gmWZ*K4A!NG?L*y8NXJ-QzZTz8NNWmD+!VBTEg-87PiFy zLc*{4p||mT;-W_sVd;gzF`KlMJ6D;e`^_b|7bhi0TK=;MEPL}`AJ36sgdDH5*|s2a_19*exD4V zBI7qmc!7++RK{hWASNjl`Q{ zKo|81NjO}>u!IK_qTDJ%)aNh>qY~dvi2MsA?3DOr5}qRQ8zekW;xCr)ClY_Fgj*&4 zUI`zU_@^a&QQ|+9a1SB);#UpGM?k_{2@jBvAC_l5MoL&C@slKMAOxK`GTbWRafFcn zN(uP^cZM&N@Hz=^kT3vNXs1jGVG=|b?yrDICLmd6x>^Y*OV~sRJJlxPdG+DbP;rknmFp#kxB1{HOxsb0sX2aHxbe5>Arva0zEfI8(wo67u5< zq_H$1JW4`-RDtm+3Hc2LhPx%?Hxk(I&Xw>I3B|fL@M2vX z@CJ$hsf0h5@Gc4OmQbu?BmK)V{Dy?@NVr47k0ktD!Y?J%(Lu?NAz?_u0tpY5utvhE z5{h+fM7tG9IFu0e z9xh>+5cL}^;n@L%!H@X%2KcxK_bmT;LX=w!1!8$(UjXHN#xUqdxSkEVPa+TL6_LLQ zQooQ_v?s###3N0UjBg_Z{bOZ#5h2Q1DZ{G?QQoOCypa&)3i*THZ49IQ$7K8ygy2KS z6Y)D3rk+;ypR@{(0s{{8*|1yP;gsfpR>fnHTGe7aDpiGpoK-|tsiOuwKO2L$+<1eXcmQlU9$WF`-xsrzZ%LLE z(L`Dm-yn-e`n|c9^>wa7qDZp2s&inVZ^hy@10ef<@kf<_%8PRv%r=QXo<9t`;;#a~ zOo!n~{0&aWIR1^p1-1U)rmI1k!R1~Foccre6Mu)|7h5%=zYwt!9f9;=x`nM}I))o? zdFeeN;{n8#nQPbm-LPsL@$AkaGGKY@roYXUEKq%{jmmXUnpDs zskoK6@yhwEbCCk+ST2^9opLt}qBmzsrk*N#Ja3di?;_h5B0bs^vdVf~K8W7!phuai zKXrTYAbKx>-t)kb9+og2delpmhcsTFiZg6vMEt04`LI4 zr$lgu;2;?QAU$5c9h9!~cukw_CUep~A=9a-Un1RJ6#!IC_!!c8`TGd`U5a?tw^F8~ z{CK_!x(qF`|86IJ`ho{uk)zyfk zi*h!^n;Px!BiNsHUywriDV zb`Nb#iF<#eK5BEf7A{Aq;O^Ev8|!c_-PC>IqMSwL=fB!LWKVtTtVNrgW4g=N-&7adJF4KX-Dh=Itb1T<>n=U-ivQ^0 z+@{u@$>F|TBYmOW;ZWX}zJJB`9va^MS?eX+KkL0DYc|rupn z_1Zhy+pNum4|lab|Dj%q^7A^npIbkE{XKhgHeRmzc5iI({rlmDNA_-fchlbCZv&pW zY43=)FWc+8^qKQE-F5S}CqFwQ^vBQ6$ks1!-Fe~gZPw-frk&>;@yE~f(uSScqq25A zoV~HS^ZEMf^z#o_YrC%8IMCRzM@!znTg%sT!dEwWWZ@XdftBZfKx9H*WGiP-l-#v8EdEE;a>DOMn=x>Xz>)f=raHIdO2Y2kc zMBlP?Z|LpV&OmJRuCGVySC0Jh;yq7(rXAR@Gq3LI56JJ&J~;QhtX-k3K-I===Ju>c zNa^iAotL*Ols9yH)p^^2Yuck7`_S${{?P3OUuExV?H;;)aQa(v|fSH|v`gefn9!#n6V(g`X9iYtAX} z9<^tquYA$4?u!vN=2+dE_G%A*_r6dAjLz61nx_#^G&&$xDhR{0bkFRN+eqGL1T#Gb7?Yh~Ea?aPn>;XmFpI&sqBE2%W z&VLu_qOaU@=3SqD=HFCsc<$_Dw)uBItS9$YXu&45XMF?i+V@u0>$ffGKBoK6ANuR` z%deUFlkUHEgZilQb-ue$3+nj);oo}f%h+}>pqE52M?3OhY_J@HZ#a5-zfaGK!WjBv zu!6=RL#KhZPdCS63gq({!x8k)!}x1VFH17UmmRDJ>VgKKnum4~6)^ZcXaCSjpjyk; z3sm+g+zvC1*+BZt>=&xRNWkFhwtRu?Q84@dxw-I#hZfT9G&bWW>sI{u7r=yOjV@{= zb}O+D@`rc+yJ2;+4lP{B``3=deNE9y+#9bl1r1pC4y>tW2d?DpoV?C#jElGW5ilo? zff+T|a-)luUh|tTqQU`lJyx=USz(8*kbc0G(w5_+(ay; znPGl#)L9By8D1ddmj0q`)=+=1AzdEikvz+nCabViwz z;XPEEO%T{<^K0CXF@F%p*F8-grFWU%L8ecbJP`h*`5btD%Df;;)1EfhhOxzCa`F0E z^Ax0f&MH9LAF5lc!PW%bIvHZB(yfatxFTy=b#xl6dxvAZ(k*;xQoBsI9)QwZf$tFq z@t}cj9S`-nO1F3%>T2D37HaY%-FhEXuF*A3WHc%z)GS$=LW1@C@&eX@*sj#z}f<3Zx2{pChQ1UTwRzKu-3tunjf%^ zMI9CdtQ$ddVZiz)h#eiU?gE3y1gxnj{n&t&gBHFkU~%;VpH;XLEmUk+w*#y!}mji8VzyO^V*i|Nan~tJR0kN+19Utd?nk;gUnvdwk(i- zE!(O`-R}=tZ=wNy6STIX{T>Kf?}6rTgVu3S+ne&O?a<^O=UaD<$EtF^wP2j4{UqP& zM9;h>-?|5S|I>WyF?52TQZY9>UUx( z6-(Yc9OujiuHIbdWPjt*606{T6Elij8cs z)-_<_y2bixl%~bDScjoE$G2E7qx8lt)+>acXDRSuTAc3QteM_9Jgx_u;;@OS2%0@ACo<&pCdn*2oG zj6mK#-fTp(_w(jDa5%u5pP)t7@a8;-aV>9#qV5}~;pQH6`7?OagEVLIW(f3h6K@to zaoCDCyn&Q&9@NXnn_obZe3UNdq%j;@aB~YPh;Ni=ITK-g zvUu|XB!lmaXgRM!k?>&{EoTF?)Z$G6x&S_Xq2=6+n;>sKLaq>Rc0o9jK{rptug^RSzkc%}a2+tYHEo!W;5W;>Z8Y+l zkK)%f&p&E5p!p$wL*_U5%{964oM&>IIp3U)-vaYlw13#lN9V0DkA_@F znLhOAO7m5ScC`5h)NPFUN(H7o<|G)Daps?4u?{wW6vKD&%$w`6C1<9Pa)Nm(y)_(9JZU)=mZ_+hiIaC=6NV(q4}@TFv8~9F!slooAGaoCiVCJ%P6GB<$39&-+quHUrKSqIFkfmve)AicF_4kWzJJQ*#r z-n_aB-OIcXW5&tmHIT+BCXbAtW?l@=Pd5*t@iM=IJ=|!%iPFzBJK53A4}d?*T!s#G zwrMotc#YWt`WKi-qeot3u0}1cGhYCm&E{k1$6L&oVO?%84bZ>QEJJ;7GI#s%u#q_x z9RAY03hi=-c{0qyR`Uw{ZZm(0-(Q=5!0+AWZ=vb;m{Y*>z2*Us$$jQGhhmU04??cr zm@lJ?JYYVHT0Cs>aMAD0ept*$%nR}RsLAcs$IOTD`v;Rp3;$?VqmMpr?f~Wq^UuTR zkLBa|kry6SEmQ{HeJNzq`y0_}y);hBp4ooCi(#%&Y>pd(1Ah=D*F==*6F# z2Dtsgd>#FIulXb>{Kq^JlK;}Y4@1dU=9$p9ugyx->l-tPT6}9xL~DL$wc}UQty4i% z*DY}nLbsk80|TO4e+LM_xdLHBw{}7YvUKZXWHxoH8d9-ztD+7D1RfVa5WX2eNVl3t z!-nWqBNQu7w_XSD`MPy^EzGKJ{Tg71ZWW;^3UzA&KoL>`6zf(Rpai@?ETy`2C2BHM zw~m4Ww&~XN8uTySdI8*a>eg7WyBKi*OLXfl6uVTnZV984=~f(EFGI0V)8$|ZweQxg z6987|*1M3)@w)X5I`;{>bv0=A>efpT&1t&zPk_^P>r7wwHhyvR@AA8p88^49vsxeHvW@o^KGk0?+q`F~a3N7#ZO5E`{Xb@@@s! zaCuJ#gIjd#K`?j&xJI!z>eejuvYT}4M?n5qw+c~}n{{hjF1#w;`Y}e{pX$~bVCiSN zbtr^u=+>kPK09blgXDjSMn%Kjp<8+Am3QjaZ7}P1L3Gf;t-AFI zLfhb|Bm1u*NECZF8g3$bH&P;WpKgsp%KLTe6^QOPy0rpS9?-3~q2|BSt0y2V}Z zCv@vNX!4V~^(YL}QaCE(>5GzU0)7E=$@{W-`C&HpEmj=~%uB{+Lcx4O|d zf7Pw?(TuO_T5vPCHy7ys9u%B?9f%qF7!4{vE^itdGc*Khd}8RI5Mp2GEzs!?y#OOP z5PA|4Toalw1O__v6f|&M=m*GlN+^hqdTQur;O+F#6Cr4r=D!Vg!kXm&JF1jLnz@0T zQ+2-%q37Y%V_MGXdfuxjF<_Ny`Ln@)&IXCdF3|Gu?$w-)G8_nL`5jDfhC-NHUb~ia zrVQ%Ypos7$8OBa%-dru`EEOHl^5$tdXR9C{vX5#xKU6`VmUpz4bB+q?T3(BmbFK=4 z!Gb`}$!J6HeZXS4nYxicWe!-U<(#jFSOG1V2Yt%9z^>bnKwi#En75&I3pYb>IWOx& z4njaH9D-~)ujoT2AXHx%XN6w1<2Dw~MS`5y?6`-EPDVG(`K!#Q7wtlZoY!SWz32t# zLC)V~PQ7Rn$-W`8>O~(xXL8<@d3{AkG4?H)*H<(fjgj-V%dU1Z6v2$S4U zCc-fwgOMT?pUn_hJPaE=rW&;0*8|m%a><8CdWNE5Xjy!E!yrP$Y*sNoE$aft5Fvg< zVGpQiaP$k@3pW3xklC8Cok$k(oJ@~6)BZ0WGY_w}|YjG*#$|f9)zL;O~pAb4Vbc_(zL} zk&S?VgqHs>j9u^#5}~6*q{2WvUOb#a4(MozfSrl$oaC`Ak#+4mdkHC|~ zK^Cs%#)5YgTOZ@LoQ!IP+t6mg-xL@A5&^w%IOqf)C@y>iAzvZYD)`&tLSG?@C?{X_ zcJ;r(t!UIdEsL}aBE(Pd>l);Fy4X)XP@mU}t;xupziS%MZ%A&#pbl+Ax>|*fE;vm<5NZ|cqYb^;(fKCTL$RzMiv9Xy1MBLvcfj42~gFA|YBuxUJ7F$n{ zKokycaJM8-P@v_XQV+zxB!bUTf~9{J8y}P6=N95VmK0l=a8GfNWs%}n#a21E%=gED z|HeZx!d%}e1QLVd7sbX5Brf}!asQDNx3V$yk|4{%5x1aOV(|f+{9jUdIVHm%1ls4z z)ACYBYr&8TXThe;Y14wa5~0J2;f=RiFkhvBrNRqYg9R!~7JR`#iSYyKEoRfD?~uc zzhe>*6$;@86MC??#F&XeuIw80-(YEpt^H53Q7cP=WRG$fUt-;hMES>34G)#Iz&Bd+ ze}v&KSgq=vgL*e>!5URf6OBnqwJL{S%RiBNJyGR=U{c62N#(EwGq%KdojjeuvH6~dNtYl-nIQoN-OadRcbMd*ydg(X3jMT(0`tdB{t3BFcvu_BPIV$DFJ{4MY%g8fo# z>~@=oSfdc67znN^F_x0zcjTv6%5g~}0_#eGEQ=IRFR?Bo#XF_~zflnYMLshUJX0ZT ziYJ#C_mX02I^s^16t5xqvr2+2i(^3~PTuWrSVN(z5=5 zdxHoFYFOABfj*Ld{z1qvB5WH6A8f(TDV>oD;nVWZMuuR8L>9s1T6u685Q?3IR(SVhv^~1T5_c)-RzDFneFJFU(d5G{~B%Kr|@?rQ-`u4I6(( z#mi=prRiaNKsbxEo5MlMjnbJHww^&(%`c-NSr8t^QNu^+yh!`MP$3|lOVMM3M=J!R z^9B3aF$w|c%%+5oRR~Duc4j$FaRur0QWet*0qN9nP+6o9kj@v>y-tOIbegI9ixmRW zIh-Ta5`}sPEiO*2OlGZol^)%XA>9-o~96x&Tq)r=?X#JnF7QHg@AN^K~6U+ z1f&yYKR8n%Z0W2D8~M<&vftDrt~XrDikI!3h`^?BkaDA`zA$VZj0Vl$cogs#hoz4? zQp-P%xh_$N1GW5XnBr1}fS-Fa5tk{%aQH+-T&@tqwEXR)afL#ZYx&PI#gz(C27yL_ zxJn_0YWcgF;%bF}^ZXSNKT?Piba|SiYZRhb%l{7%*D6Gjmj6doEqI+m6l(dU^<);b(ZTS&X{7fOBEt4%EZdC|q%lWMBZ3+QxSw9MhpDP5k ze@&~d` zSo+9IB(>m&s*d>}7!JM@Hm)MUt<;Xchlg_dTJ|)0U+|+aG#>;@Sl~}_i6J$c1?&l1 z?*fs38Ejba^Famt$1Na#D;4M~g+LXCZPbIi!iEWpTlVu1BL5X0I+TH9s7T+0gCh{I zC(=ZVBGcG(!F>sNnBXFZYzzd8!xnwna{3f<20A)icnwem!#U_{dXbojP7K@AQhR|T zI4Nw;OYIen;N)=OU*R?c^x+)E!@5|>2)5dZM(JYdBG?u#ya}=ytqL&JVJ5hsP#Ft?Ne;6*@1`cETaGJK8^x;&|TlAvr zT15UnT=+v!xJ@5Ut$J85da@qa=WYIfuNRGAq8Ds}kLX1QG5BJ*FdM$&WBPFFjpi%D z*8wo~wG;WUFvH+m;X*%{3HXMuMxu?rq6D#@gbP1B08IFXvq7;}CcL*Rz@8BO;aV2u zYY-t~?ocr$TGsW9AtHDV$FA?fezp$OG==h$j>R!@wCtJf#q@`sWhyv_in@UqZw)3IR5+CgNFzfYraAi02dnR{v)KAf8tU z82LMictIgxIi;4JDA<)vpiP)tO81O5J*sTy~`td~kOCiwo`0j`n z{7fOx^wWsgqY!BN8ASYBA<*5ksHcoafG|HD85_}3_i~JvBjebb8>}9s#4k_}> z=uG&>1=$!BdCoYi1a>;Vl5Si`5rD|Y6OpG75IMfTf;Az9fXJs2QLGRU`CKA~DFh_E zfQaD=0STWD8xcHEAt0_F5;0OCAg*WGxxxwoas8MnDii|Z`Z*D!6aqbED-o3n0e9#( zM2uDlxI@1uVyr@->s&%tW}HGm~_o=XB>_uDr;xgF~`|9 z@f{2?!HMI7Y+<(JVdJbycwhN1vLZ(+0#N(kl8G4#0r?fuFh>*u@_URL8dC_={TU+S z3W2)6L`0)PpzePoVx~f%?(Y#XOCeDAkBCSp1nRzrh}jB(x=*IFI7cB+_gh)_CWU|< z3Da3@RtQ@dQ^pyykg@C^RO)F`7-_@>TgC+`CM~xpc;{H_L?kNbK%|v(tO%6Tu$bl4 z^-wt_RR9G*9|*RM^ON9+fN?qi&R4cfz;MU=Ex4o)a^Uljz3<@s3xOK>90t75%)IPd z;h1LYkhd0^o%cFo%x;XTn)!FIt(*UZ&iTxN139kxU-Kc+68~LDlwA~XvUTT$&>hWd zuvwy+l~4}d{0aOE99#K4oY2rJ{|C%)H|E~5oYi?zW;l=@t~mv>58Zqo?BeXEUzAgw zg>0w!hayq-`(Q?9J2S6`*;aGbX`TaPf)g_LB6sLKe=C!YMsAt(qP!cKvkZUGr&{mr~ca!5xy0<3qrRQ429Gx zM!@!kej&Eww2IA09J<}!o2!_Q_6+?}1k8#P8WFfd1VWns*9Jm&`d z?ppZAh$sl%UtmHwO?@fC*I0uSej`VH>F_6`gPfLw_%Q5UD~HbI~_K zJ47H)8yDa?TZ2>%@-Kz{gg*4M;P6h^cr)~I!7Rj7?18p~c9-&At2h7+8~SVrvjmX8 z2++@0ScUfZ!?@3C!B2KW)M>LX@=gcFG%aK{?;DFMYW_ZWW1+A7X+(rCf>$^?^ld>2 z+Od%D&=tnv+&30XrU^7$Q1~M3NIOl-^1)s zLE&VS5{m0X?m%2o;d1y8p*A~iXkmE+LPzUEUPRpRLVp~g#dcg+JD5j<$0K5V4Sx>D z4{CTDWSB+lxWLh@;AC-2c13zJXQvnP85d|&F=W(^p|HlYn~#4SBtdAAN<;QV8X(V7 zNb+rGr05WHt%`ZviFp=xh@qxu5j!sMYy1W)Aen9He1L&;^(Vql9)0XPj4=2t9(OVf@X)rEkeY7pW${ z`r|&qFr+5_YAzaq_-A~>nF0b6j!g}Fg#N5=IQ=siI_)rAwHwgK_2+%%WXE^eK;1vl zhxq3+bwoVwEB*}wWfn5je8eCf4^{^*l-1rtT%`?7nJc&2;PGBzt_IzC0G`K$6biEC%QCwrd z<+#B6_&w|h)JuO;&t+h5>1hq2^~ZEiPLeZ|lP- zj>$kwB=Qq@-}<}u0ffas%p!6Rk$<<5VJOiMTs5DvIo`988-Z9)fI}d{R^{Qg26zqvypsD#7-iqp!y^m$yXkKM`RyHQhl) z0^&bn6n{`<&3COa^)MhS(1%Cjn$n2CblmV2!u*RAP^q8LbM>K+a)Z$2C-iC5<*4Yr zPuc3K#l{_mg!k%0I1=d7oW%F)M=-G#-@|Twp&n#B{}$oWw~WCQ>F_OZU=UTyu_J|o zTXES2<6>PHjP*ba5Gjhh(k}9PAg;w#_c0oA6iE&hBz5aEls@%KVEJ^wc3cw~GbIak z`v*er;%ZzDc98&gIbM3nK*mXYz@qB@C z4SgMby|4}mR)KO z5Xa-1OpSsy(qK*S)1rr_jt7Q&Dwp6w&g%~XzSb>8h1Of-;pN25uLthET6&ug zB77fl=VK_;->-cf)ILFYC$2f7***}Rfp2@x$JNx;*Qe<_hKml>tSqLsi%fiKya+B_ zgEV4gRa=Nx!Dq3n z`q)&;@CKy44%cj<&yRI*bbA=#-{G>^{iDsUU7yEAecngpJGh$32U|?Pi$5;~PXl$q z1`dU2eq1=wj-PUv6OO+F_?_$jOrMK}xOqHs+~jcAMgm(nnA_alR736#1c{-zX48Gs zZ(2w%wT)q1Hbb`whBhI58m?AhZGJAi6FqeV)JVJm=R%O3Q&k8OzY-71{TfO6rt70< z0h!3hA0fwI84)C&!UO&(z?-2bBlV~k8Q?58rn+{k5-yeq3VfJ$zoJ(KK_lF~6`AC`k1?ug)zr;_2X~*1u z7-Le`0pYuU)~iUAqKE3ce<4X|$(NwuzFSKC9Ifmew@hP>_M;K&yUliolPks`fTIN* zUhGs?Otnk=Es1R^@pEXkV>TV-=08W~{}+Vm>n`zg#IsX%PjdO{ZgBbPPT71-Lwoz$ zOZ*)0>>TY==^xvC9V6*pFchg8OZ>FocB;lHOr<4{Dn`td5qDKkYW zu}i~{e6~J}dHigT=uNr6Sb9E>e`=94AW#2`fnk2Oe8ZuTJwkQlR*N0gfY9B6kqr4~ zGVg_GYyZ6g`;cgCC`$H^l<^#l?Dz^9-!Tmw`g8SR{th}hejn~M{Q!MTUSZImH!QEC z^Z>n}6qOjQ1%pQcg)}9aKku;M;lb&_1Oyt8F(?(I0Wn!)1;`HQ{=B1tL8P)%^EK2a zo=(pj4z04p4Mx2jaf6{UDCrtD-H^aT4!MPTFbE33lLB6=rX;R28JBl00)SdU2_@y;kaq6{9BD{(lCg%GO{2pWJTSIBZid$52} zQeZN^(i`teX0)t|$mXKQNP)@BW4)O%PLW5p@j+vuZwD9aWp9ra{(r1*Z1{+s)fIcLve&~-HMAB+Vz-eJ$>3t2*zZxkO(Yz9e1$spx zQAnb7BlOzBq<()xu%mQAaG^0@$Y)|u=N9RtNm?!Vn7mIK7*0k>qIg%Db3g68Gj;R@ z3#?ixN1Jlwp@01{eW0gEpHp9K2v2 zSQuvq=ca`{@Ny6qb!_k!jXv&`42*;~L!!{m63=XbL}5l7G>!nXLX_T;XAb5EBF32R zEu8I;a7aUos394oXUpV5@ubw}NQS+*Cg7+B0!Ne4?3At~M6tHmjYQG5W>5hmZL;E$ z4ZGrVQNBYLHrkuUPLc9*2xIRhi-*{%oMs+Z76xD9kF&^waOql#0OJ`3(-R*)owIQH zHyW@Wm#)!)bN(>IXu_M;QUuItXaj+)N)E>MpAO?{58+x$;c)sCw_#i;(nS)%f;>nS zso?KKbQ{5AxU#j=wYt%#Xrp!@z*oBk@FA+U8+peGxURJk@EtXF1n!v05HnKw@z3({z70(|NFTmx~YHlRFSKMFL&N8ZS`LxU03F~k{ zyaarCQ4Y{q^`r4qaU;WczLwDhyqK#2koDs|Yqmw+6W)Xi$q8=8<)y~(&+KRdR)iG5 zmiXgz1AoBskKC`uMeYg7HRux9Y}DMSSOS_HkrUh!kUTT0Vt@t-@#pv1<&ZuGZ;_0U z63W+3^y9&&Z%5aSHNPvLHd=`7TSVwuk_FqMPXZzS0$dmpe@76|bts)tJMLTE28 zmQ832a2{Fsp=62BmfAd#6+eOp)N62VzTQ@9_4zV4p`Duy$-g9!YwffO#Yf<<;3bgr z6_TU}s*7~$rqi2o1Q6;pH@Jd~v-1POhWm)X9E>_csCm*D)_%UsMvMQbO zR1VH?Ap(L)xH3gRrug??6T!(x5@t5Rx3y<<-57@-X14#>&rl9Qfw)Z(RN=}j5(xaU z;QyN(A*2@z8Cp95tsLA6h(L^Bg@F0?EuW?T*F>}|gA!2*_N4@*mW2y7C)hWU zlJI{`L@NCANQAZAe{t+>@DB)7qPZFEF-W#5QCmhLbZc%TwDUS6ho%$B3!@!= z#h?Az=rHbmTCLOCy6Dd}z|axYf#W9f*tCT#rlrDeFQFr1@*`AT3sALdF@h>fH&Z} z85g|;#;HG*mafUexE{mx46avk?ZBn}yyX`tBp~ZSiLnl}evBK7i&}puF7>Ci+)p#Fsb${QIYWo$FT6K5ts;=tJm0jzrmv>i3`j)O)(bF64?dzJ* z*VWV2-`QV{H&yo$)b$UnS-PUPt*`g^t|bHg)v48;eJ3=o=}EVDujpCcwsK8>IvJVL zJXsa8qGw5U=js*JC>H-LaxsctwPX!STlqg!ZfD=B>S%K+kxEatVKu8#o#i+Id#5+~3!w1S)$?AdL-jz$bJ6H7dS1(_(Bu%=tHR*}zx|+J$bZrfh z6M&r1)7#TEp{sN8iV3wfRTC#Lx(d-5QPq$Hi?7BjJt3<9-`VItsoyJ!|M$)QKSMpe zWZ80RuYgn~Td^{=TB%rH=af~G|7Z9RJ!t>Ry<}DYivH?Y*V+|Jx~h}$mUt?X+Mn|M zzZW@s+W&BM(H90fdzSD;=<@ZnOK4Ug@ig{ws=8^4g#gm%90+1E&A26ay?Sqt9i3j< zwXAc^%7OI2Nvpg1frC{=k6VgYMIr#3C7M@cNTWi)VTdA;u9c(+XMzEAu5{P>C0(lr zR`m9e3JXRzPcKwkb?6o&hk+M9aD>qO*Z6e9 zC^Yn}0}La}9|{}OvUDRDHim}{eTGp!0@zWAE%afAuDjW`ifm;@xt&_C{QjhW^p-Hr z7~}F*ZP*w# z&KOgP)FX^xq7YOVa141q(lE0?@<2h{1lGzL74R7oviujFt_Kjr)@T(FC0YJ+PX`Mn zg~lOBH7aa0RvCv>856`WI1BiVVg7d^9e)v$8~*DzR0-6}0+m%oT3P;Ub)Cfg*PaF* zOGMp=g^h|TMxzNofTXaTE|@{Pg?)HO9qORk`%SxMZ0|At-q|Q{2&FQr5P!u+u0M^O zMJ2{zS^f&$sP-?ZGRCY%e65Mn=x$l1)#wC}74?~_Wn_((5D_9=0hL1e zKo1wG7%KN>a1*Kwgu0OFmJLS;>6MN)^2b9~)eKePrqU=yA`AT@x5Q|`ZDCban8F-? zgwUhV7-Ps(gewY-5m}|ixG6@dzrV@|`E$d@h(i!qODYwGg+^{sA?l$UxmopwRV;))Oydu7GB)p`;E1i^Z(tYy>KG^sbTqvrTrmqUtR6RkX(E>xdub z|B1k7&97b0F-_;>+x9IAu(cfDjG**(UsV=WC_o|Yfa;A$0I!(#KX`f=$dLb0Jsh@G=^?*uz`s5jG>b)- z8Rg#y5e@fm+z^)fw#i_kq5l7zLLLk>zO?UW1$1=7;V}6SMqyT=Q8WQ}6=Os{DM9^N z`%$9S`otQd}g|%CDqZ^*2?&FTVg@HDc#tbY>u>R{R8520QeY=?SZA24D_wk63Myq zJKEwcwRKv&DVmPYLk-fAShOacibh(}@s?P+!Qns@(9qNxos*75+9T7Vl2T|* zI*Hnok(N{=(2)kgg@rj_dON^ngPr znq1h{-ioGZYD%}YCR*C#Ne!QbYK}zH-VZFrnxjxnxX2UhJed`fjgc6Nj<>f{51kJw zt?FIcg~YMuhWSb8p{pO!coa(59*byhW5;62baN}n#Ntp}b_56m+41e9{$*W#X)zB@ zlcd8sbT8e2UKC5DA`ML**~QyuL0oOK7TT(nZc4Pw@f4q!A8Uu6$KuJxrq=lmx%r94 zL^{$Yx=6IOr6nFE3v7>6M>LAg=%iFVb8bhxBc5)A=$t4hRHA*M6J+0Qjl;|n#h!%jT<5W(iA1t7l8#5C>DmUoXE6ptobp;>8t+&lGBe%U(cae4o}Sm* z)Q+C(R9tmP8fqGN*%h3Q(7AMJpXdiD+CjR#16a3m?8bFME zDb#>HP7DD^nqJZ0=Z)upiiYg#>c@hJ2D=FH2(jZ-r44H}b~E%c5RWDspvmY}h(a(P zot5%vfv`vM)gtkQOU^k(;6=T0Wv}!ARdzObGpG<1gC>yt> zp;FTaxgU&#>204+Kf-o?YMe$#KS;H@4jx?|Aw>JPLE|{&v3PQnPsW?#8J>XD5o$oB z10!2Ydm5-4ih~ z3V%-doF1tpqHso&b0>OGu$l0#Fdj8SEOWI;w7G3oswR^rd8D%lL4ut5%b7Q9{2D(#8pIQpKa2snRJ($Pp;dk39A=>$f!7NzK@ zjd$3R6`U?QM6Awhk1)E{rV}x!sxpOb=*6id-5b0uFo8EwsR(5`;p@+A$?)@AQ_!LI zR`@Y$_#T|65wu#9Fbz$S)GXDPJzjW*%}=q<(`qRyQh#7H;GT8Fp*5|IUNdJKRTvjc zKRi-`8MZwK(VJXq@Dr5((*(n)rB3Q^Uje^TNNsf*TPz+TV#s$z?DnOMhz23rXflF6 zE3~8*H;R4Q&DKVgiT>(3R>H)JVKf?TP0xalpea+RGAfBf0bow{@g7t(he8j>!eQcs zV*Tp=zVzD8m20{rPu@gy8oV;51E1l(I93hTa-o)pGIm~G*rLSgASa0Uw_B=2gqH9h?+miKfm4a39fbMO_H|nNvj=q&i{sl?+^igUuC8A~@$!aZX>3 zidn9-0j`A52ooI%MKW8*jc{ko!txF_)h;>kHg%9cYpc%wXSPtf{WMNS4w?r#4Cu{K zcdFqTg5Vq`8f`DdsWs;gG`{=Qh-oOagVRdSl#61BHrN9~`_Ztw-rhl{6;>5YIPNX> zOEPU-G_jx-D-8Jc$WVj@w$5SAo(hT;2KXgn*}; z)oV#IA{rg-ba_)FlTsefbW-RocCFUHWn0y`UhC-ZT;A0vcC7}DPAJ9gb8)AXsc1)x zy|AOIFHO^6$m1;;Zc(C@D?QS2@rp7dqRu0Zj0o?TpAliZ`B6OSpz7xM9m)7i_~1$5 zz$ksen2~m-HBOd{X<_fmr4U5_3F(zxYr9rDY20C;Db^}n31>d#_7aH5?OTHud)x@G zy~@Zjs7>7*?qZLvWyyFnjv-$y*T~M_mF9jTA4W`y)rv&liP2@ty&~m&$Ge2($f|LE zx&ws34#>(x3JI}tUE zr5YehYF47ZFWTF~&zPt1_414spOQw!Tns2+=@9E6^mC)|b8T4b);$?-i$}0_iFq4b zdd{;v*=>c`XRvVT?>B+;YwEnSTO@=<+=r6tCyAz}_{<1=NOujh3H>FN$;-YJ8eC(E z6AEa3?0L%-Kc_X7$1^k1+>AQP<+?#%KF3-iJxt8iyf$$~&$8Z37V7q6)*TayZ^;kf zI8J|hU2osg3|-(*VNVMt!9wAqnHjOd=bYb>&{A#j!3#Gvg9bXve$dpbR;~u^Q{$${ zLav|68YfctazjSbaV^*$qnyPLEEQk?6f4J>6Bp4Z?75ooki^<;OKS%_P?u&5eUxJ@ z*XJ_?iN>*24=*@$lS3&ePkTAq+pVFtQ^f$4k(T55;2~8hkTdDToFdYYXi6My&lOz) z>`eCHiK(h^b{xZ$8t5EY(;r>g1z&4_8N3GH=6N4QcC+m_f$Q41rW?~bcv9{A_PQt* zp`8Xvwd38Ns+JhaF->i1h+r#0&J3dV>ZqfGE4zA@4|I#sQz)92io{$3STBYUTN)EH z)ga_D?&|1dt*xtPX=0G?B z%c+Lykz#28gT(p)6z9Z}56Aaw#&T^#>jEcIWsNpreuSy9cYQjUiil-&tn6c%z@8oN z-_XV45NnIAA)MzqAU6$-c8k?{Xm^opW&Z09Vas|tgD;h~+8t39N zrv{1C;MsxjnCT3)uzX(+a9OvVa16_=!$NIo7fjmXHOsi2AePrLR5f5i?NW}l zij4_W6A?|W$V5kL<_ggBQI^T&)brwBvH zlu6gZbmCPv6QX28&WvOD=lYcsBjz{GDu+vuYHqJN+FgML zzNNRP8NM4;KLLkUc(4v3wI87r8fFVN({V{6&c;w9b|byEQSKsTjMHKO@lMP=GZ(RD z4SSrlSNoiqC71m$T5>njVai=}<&rE04q+v1^~Z0FYU5ZMv2`$@HFvG*?K`Qtvj?vF zs;ll3TPf;e4^qjKMu#B~?Zw`1Qw5yT)ns6%+CQMC2V zSop-699PFO+|XI`u>l^PlhOLH3+|A~6;&*1W%v>q2}IBGE|Ds2Q(K-~i?zpjSEOQg znBkav4YF8#5qp2Bt|e>w_CGrl*3GjMZVv-kSED>ti@OFZ7Kyr8)iE-MDV53H<7EF7 z8)y&$%z4CKuJW`N47J$o<`$O9ZfjXbOJp9#6)q7=k2<=h59g2vFiDx2;Zch%edVEG z7iF-ShAqUNn|Gg47>JoTernJ4oRWqAL`tnKqMf<saGAT|nuz3eh3s?z7nmy1NlxUn{a$hrs!wV`AmjBW)6x_qLlh{+)SgpNd6~p^u zZTwUTr)v#s`u96CrzM;s)-f`>o!#H0Ll9fhFFXS5?PfT<(k}1!fC3HnzOG_MjzM!5 zH%Fr;427-gsrg)<$0F|FqS^ny-_*czrD?r9%^^{)9KCio**YtMtx#-~w_r^i`xZ*r z!d|dRxOkMn%J|Xf;`W}FIA-8>#mpUh?m)4%xdRkwvdy`(gM-;8wxZpva{1mn^^_=Y z1tiL?03F2ruW8AollCnG+u+U_7*)pp%H2=F8RutIUaz~YaQi71y6Kh+HQHN!$%36Jj>VmQqNX}ctF{RCKbp~X#0DQa zuA>U}hzrJ>;jyZ23U$D#5Omc{gBiiLeo|v)l&1KnEgt(T`ju|a=tw(nvA!@ zKkVyT-PJjO12SEmo~pspOxkw}Hr0`_*Cm1Q-3YG|W<+o;5DvSiAGl`%=xnPK0dD2M z19l!^UHhHg?9RRcoLO*}#+4wkm5kFui75O?%&6KTaF5_(;7e#OH8A6@1UGsj*euBf zjat{rC21_P!G(cW1L?=*Zg32fR>zikwrg!i!f8u2w&JJ(PSG@Z3J_y*rZbPKO%pRG z`zU;Rb>G_bQfU-dr~A6RD`iNFp%X@5rd`t8vuuTD{X(o#C_#8veg)G!*dq5>#ju@D z!)Z>pC2?>nHAhorx?)0UlZC78Opmc{Cv|90Dtesakq}1)ROA$$cSo1qC|lK)lsLC= zurEO}HyR?#w zyRwJF6Ij!58KrrQH1I5jeINvzUxUVZDwA+CQ}Ywp@KJ?P^}UW*Bj%6XK@rCZJgO3% z34c&+ryw?xYKMC#v=Ljdna|tU>L4E`t6HLQJ=r_YQ!3#)T3jW;v4-?a9ERbDI4fn3 zh)Y-XLx?K9svIW%9Zhmi#N(;cN~uMb4Bxb=tvQ`)X>G;sHU`)ZIA!iRNo?1tBa<1! z0C!vIYdWzL-P=j-Eq1w-ITOn?T%W*7o5Qkf=vi1o%sf`9>cV9ckC+>=dk;^RrkJvg zV(WUb*1K#Ox`xuFR-WQgBJuVr95_s1DH>}qm>&(=Miq3Ev4!q7bP7k@a2i4$Z&2#s z9$fmLcyK7zwRnvy8>LO$Xm<`q;Cu!|ApCK$KH%;{xIGS*U`oaopwfP7fPKW&nQ3tz z39|{eRIGw?UV-LU;!~~A(Z)snw7oU$X%3V$k%vxHdRJqkjZs@$#Zex6rKoEuA45ZF zD!DXo_T&*hS>0gA&fVzsE{?;ZxDoDjPHaBPIjbuSBz9+_&WeHOlc`Ac}(o#P+aTs_+KpCt6~y^V1pItlWr} z_y*@lvsx+N=WHy;L%FG=*5BMRAP9HotzN+K@f^!`T3fi!^D$S6V-#z3j*z;exBdK~TQW#b_iC4D;LPczn^??#IoK-Y za@yKW)5_^m=6G(8PJ<@;n3HB4b@I4g)Gu+Q45})uJG@!0iDXXZMZfT_>&Ts{L5Iz- zZNRamWghI(pd|}X5XWNDutBu5JO(Y6+cFEXYwelGih^+N1{Mx>f@@%z$JWI{A`hW@ zrXd*vHxGb{nniG~!5*EXD|`FB%PHs?_J+4G!E#m_v1gc3%nWQax4shC`f|lDCgo~% zL9-XU#W5JM|EJo`YqA>?Sn$s{vEW*mR4O{tLp*M;vWGU9TU5tp-!IA$4k`f0Wt>=sgs>a~zg7acOLH#wWusJxTFJ@kR8hl6#GePC*i z2_d@FVxH8jRi?&qScNmv!iO2$;>E5z#s)_Npjzp8B=hhQO(G2oRYo1| z^`5@y>so~e@VzdU;sC3Xu$?iiTzHl=RHX3goq|2ft+YAfaH{Ckav$10Umuk{-ENww zz48>bTPSL`P*fTPxv@0pJQJJTUbfkftxl;!0FXG{Qb(}+ea;3O8!&=c{INU^xT<>;Hija938_hAs+9>i6gNk z;OW8Q;S;eV42^Z#)^nhKkZ#d{+DF3&G0v0pjTlLkk1pKQ=H8wa1HFB={lh>eM-7~Y zvpbg!Y!!)lSB6kQZbRAea+z`pk921&;6jFzy)qQz8my=|bPXGilXu`}KjWL{WR&~Z zgVPjB-{-d`=Sc5UsJ<&&NAIvnncBbDJSR@@D1lry5EEzhG=XrZJ?(|sV4>x|8|Zx# zG|;JnpMfPpcPC3YL8=;qW--DT(K?7NpC<3~NbWpA9GJtPlfcn*4~yK;XcW`G7U#?| z_8<3g-#uBV`=V#`clY)U3_6c4tnU6@+8WoTb>%J^d>?y&SxLs~s4YmjTo~1aiet6C zw{OM3NlqiX(;P>U)#ikEiByd4?vXDgQ?cI7XA>ZHsl@IwYqTlS+=j{X`ZgFv;j*RE z%i#qu>?(`cf34fk{_9ldOiv6pNwku~wLA&o-Bc140n4db8S{0yusO}s6p)L%FX}F` zsQP=Y9-lMgat|JXk>~O=8o`|-L}6DlmZ&0a@Y@$){b|rzCg((04G?o8&$8G)3$hrq z?5$QjedQiTQ*x&@#zUN(j(86Th_R?K!UYYNPuLKwDdDL(E~;a9)3eH<$PK2$Iq*J{ zL*b`;x6ItbvN3p)IG@j1sl9fOEp`tF5I7_?s7I@V;e71GWfn=@(?|Om>7-77??@3c@zgMM5t3ey z9~J_O^PcI6s0*h6;t^mwgFAy4#k&uN4q6g&U4NdT_dW`#+T3=suwRYAh&w(Ro*D|p zK9Td3$8xULikCIN0_+EY*sf>SmlIv(KhFFd$--aCLxV z>r^rIMuSHu`f#q+ems>ji(n3u#9kA1l0Krt47JWZETYO$EbhNNp~jgiiiVypX2~vB z8J5XaF?+Zlv}%B->oS)n?EWTfv`Z0%*akuDg~Cj(#_Nsx-3IZRt+{HoMx^zgd$Nu1 z_s<*mfOjncG0?qc)ndS9D|d*vej!RPv~DgVQK9YU^@GjbRUU#H?5sEVO14pc84tOUwz23)!_-t!xLKT!V~Z! zs3VtvfeFi2b@lVq{RDem<;WVK>*W*_s|apxE0pp&zfJ<6EGBTiQ9$>4Y7P za!0|8-5zz=S31sWgr$$b%^REv$S}Bc3vg0gxCOSCq&Baxg`bfU?fJi`dk-)vsofD-U#sR+D&PghURj=`oS)1`ApvgXLhr^Z=gGEzH*z( z^GH1iI-?k0%y~DVUDD#ySKLH!2c3DymJ0~?rqp+9mYUI1x%HN)<|+Eh2EL-8%hb{7 zyHZZUxIpu1uqu4LYzoBda}Bh22`S+n}@hp$82XqSeA3Z9pxygM{RmNotO_#6JDw)&Rj&q~=N zQ+KD0TsU(RIHi=Mb+ksSr$G0byZWV+`Prs_R|M-Z?@55JrPc6upYiBYzo`*c!CNk~ zl=m*~`0Z!YCI5Bl-#rQX4}kQT>6>+J&`H7`Qti*LPS zHcm=n(e(kmjD9aq2=aCQC9(eNos*&`r=1cxHGEp=^xzo?bzp2nU}bu&e@TXUfvy*& z9w)`pw56Lv#BG9mn3%f$4e7^M-VSe z?Cg&hDEf{d-l5pppD$=m9YMS;v9o{F!V6`SZxHVM4qWCpy-WCXy`S1M@sMufZ%S4} zXYE1szRr?N6TU2&C4bLlda*9yO&3ju4kGo=`uy(-X8fEk{yE9GJPBg7bdH~E@-sOZ z%6oUOD+r=jvwl*Czc*7K-vgXF+!sRo-7wbVJAziB&&BvKPU|~@R&Sq+{(ZW*`*m^m z?cyF_#x0wJCCNp9D+cLixpUFKXg7jx)_gAd(_Fd77&qVL@A}U+?x=Mf=pC%>i}1(z z9OJpra+Ta}dNJ#7a&t`QqP-rKo8vea?Xy*Gj@w-PdmH4@AAdQVMcjQEJZ#c`rPY7l zfB8hx?;fV%vs=Ft;t3nc^o)^Q-lIHny5AlChnsDMF;8sh-2W0MiM%hTk|DTL-02M= zzGtfN?hSge><8m706RY%N91_8(@~+E9Y~HB%6SAvx$?khceDn^x@{Rig|mGEXh_te z6~F|}IW{oNoi78J2orRVaNi6bKv!ZP2n=SuyUZ8aYXbu<)B6I0TsuY#2UR9KUye?9 ziC8JJZ&7}r*e)&>j}lK1PZKW|H;T84&xx;#Uy6L^HPfL1W3rnV7kh}k#R1|_aiqAn zxUX0$R*7|Dvv`o$DlQNgi?oly{Hzs^6HgM)5YH7a7XK*zS-f8StN1tZUh!e^3Gq4c zCGmCf9q}LHKgF-bAH{!*!GN28N6ZrQ#a?1RaZhoiI9}XetPpF&Ch;I~j<`@yLfl*2Po&vx>ZukRMH=6xyj5%$mx@P- z$B662GsN@6OT{b1>%_l^e-rN$w}?-RTgBJJcf=3H&&BV=pGCaO)#RTxzFCfJu|V8I z93Yza{v+IIxhIOnA`I^tJ$2#%;vwQZ@o=$2JW5EEsjpAnUPVs(mi};lIg7~udrueS-k@&gzt@tnTH!&PlyNfwufw;TaPaGl+7srbG zh{a;1SR*!yv&0s$O*~v&F0K}j5l<9P6KNit?RcTMLA+ADPP|#XO}txtP<%{$M%*gC zD$<5H(|KR~MEp|xUi?|K@xptCPZPU|aj}QkTO1$`6-SDDi~EYDVwG4YHj4*|t>OZa zR>zs272;a)IPoO$4Dnp?V)2jSpT+CNzlwho?-d^wpAerDUlLyz-x2>I{!{!~{89Y3 z7{pBz%i)N$eolA3SSa=p2Z_VP(c%Pgf3aMgCQcV;h_sQ;bmoc+#iimZ@hI_l@f7ha z@qF=8@pADR@kVj8c&B*3xJ7(Qd_jC!d{cZ^{7C#<{8s#z_?t+(>MS448x%@i~z;+8ORm@ja17*(v`@{89W>4C4ll{+VK2>?!sU2aChSapJyWnK(^s z5NCPfc)573c(ZuBc(3?~_>}mf_^SA}_z&?j@mujH(eCEf zPgI0Wa8qBqiMxw1eQo5hR&6*+oFGmXE5%x|Sv**rD;_2;7uSf#i6@I^i5G|)#H+;X z#aqNX#RtU4#An5q#5cru#gD}=#UI3fiy>^Yu^(lKxnd77Ar2CY#IfQeu~eKY(#{_B z&J0O?*y#Tl`YAu+c?5IpQ#JqSzqL71xUwiVus=iyw*sYzI?smRKs* zi|yiC@j~$`@gDIRai{@l!E@4MOUjD9#p_h)0VX z#T&%C#ZSeb#Y}7*Qr}>4taymHL_AL1AZ`*L61R%)iQkH$p056UaiF-jI7OT#9wr_o zo+%|MjYsEXoC&kyr@5KPVhG2R<#i8OPu|_;pTq>>;&lRr{ZxbICUlu<~{CFBWeW?-RF) z?~1>Qd3{~I{lrn?6mf>QSiDPoLEIsJEq3eY>gy?v5=+Gb67LqD7C#if6*C67>GcwaiTjCl;%srbc!GGo zc(wR9@p180@ni8{V){Tg-9m9MabIzkIA1(g{DXLfxLJHed`bL3{9cRji2a6NL zsp3K6BJmjUZ1HmO7V%+moA|!?ofyU#jfmaE9^z1Oq`0@ZuUID5 zi*v+wajAHec$Rp+c&T`Wc$4^m_^9}d_^SAU__g?}m@(8XPY=4(8$BAc%mx$Mjw~LR6FN$xApNT(-(P3_W zUKjr;_c$Y;)milV%l(|yEpa^Nc6ir64&P8 zB<8r$;&}O&$vs7^k$jfihlq0|KZ1n5qe#ppr-~OzzCrG*#hXc_yIFjIMEouC-!A!U z;(PM{Nd7w||3&0?-HcyIqI~_xY|Fx1YK?n866uwQm6A8gJwrTL@^-lwiOVHFM(*Rq zlO;b-?u*0?l3yqHjp8km-zWD&;$xC;mHTD!4aq;0`&02t$$ysnH!(EQEq4xydf1&r zx%-F%B_AdCIB_4zE9IUh)=Pe{+_S~Q$ZX46N}|0_lKeFBY{@T{dxLl_iFh~4|1Qbz z6CV?w61R!3i0_by|ADwu@?XU8DEOnij+iU%CiW%~zdwn5kC1$fxUX0&R+9)nU2K)S zOD}>E9~(9pc0Ce_VV;@;Aiy#gD|VNVM~>V#a9K-9sEI zP7uqt%?%5>jYo54J@>O!L6_1ttbh*zKFD9XHBZ>0dEcs^f4#^*sdyDuiiFjMZ zcf}9Io#Ma6*cdmTxniN%TO3HD9`M6?E0BTb0_Coe|8(&H$=k%`lCKhvl>B75PZ!UT zd?Sf_)Eni#Q~vjg4@v&4+%Jl+lZf{=iF*24{7L@5ijlGKM>%py2jf=mVIMu^WkebtiFeJVAA#pA}yv5$`SWbIHFJcakVy5ZB-U_GEHNxOXQ} z4}HXel8=;otXL^|gWLy*Eo6aZ%_EWDm6ER!k0lH6EFX#Vt|asDOsCxUl1TqS@lnZN zkozU^HOb$X`y=r)$$uiDH*LI|PA&<(yNSI?`1cpbOFl`gkbIihBKcf#vE&`%36h^I zo+bI8NR;zF@n!K{@e46+f*USRED|flCULR2RyitS>D7_tx_>zk;UCB{YEMj3xBiw*Y^OT;R%Mw}zg7gvi%iD!!Eh&PhBZv9of zL%c_PLVQMiS$tjGA$}l!A$}v8=lh^P!*7sc~59wbh_cfwHRAQ+E#mFsbK+Lf zJZFdaf0z3o;wR$QqIup9;r=bR9dygzL)={)APy1Db9IQfzuXn#RIybw&(k5?V!4-# zYs90)^`d#M4&g7C`_H0zjt=s_%6*4;kNAlAxcI90rudool^Dc;W`9Z(V`8p2Ks3+G zA)I+$4jd!7c}@=QD!I+`ad00h_X=^fc&vDW_y_TP@ka5l;{D>o;*;XDqIup8>3u5q z*W&l0dCm>~-LOVrIs1wO#WCV|aeuK?JVfZU!{TG2d43J~ zdQt8V#E->aMf2Pm!Z{JQ9Nok|;s9}ixUXoQQ^Wdp2HoJH;v8{}c(iz;c#8N(@k()% zc$2tAd_sI)+$Me~ek%Sb{w(HU?Z60#m_|MjqB@(XrA+e zJ4fz8qIs?h@=USyVU)||O|4xu->%k=Aj36=ZU>R<%3zJFcokF6X>Pd{_nIzhCHi>mF59-0? z#Sp{95Xl>w^q?1Ca~k~#vA<~2#XLTSZqQ4AlH8NUGSTD%;hN+&`GNajxo3;>#AV`2 zagBJic&cdD)zEW}+!u(Kh#SQ##H+;*%um?OE|fal81M_?Eas{6PGQ zM16lJ?i7C!qgAFsv=f#naOwKDv|2EAp5sp8kb3BQ3 zW^f!rKZ00+AsTT)(rm zqjkxGHqn!9u{t@Ze0&F^Skj6irDU{UMJl^qM`tXc`R z|Jw(;w1qB$U#+?a`>p@L?V>sQ;FIBSTV;-};poR>5dNb0`|rZ-g)m*yMK@0#A)Qr% z{%{;W7=p>e3)c#XKU@>sy9&3eOSsu^`^)0#JG)D`3*cs0@9@H%4grR@HCZ0pZ*T@ ztRF9b@8aCA?>p$rgUma;{QVsQzrN3W`eN|&^!l#!5w2+$ z;RbdIcP7HIFL;NSzrG0P&);{x{N*CBmp}eKmFar@dpq>?_mn9do!s~G>-z=zm@eCw z_2cO~So$C`2Y zZ}ZOScXcWDynP+t^E(13{&Hk)x2!ABp_nc%Z^?8|>!R53Z6$8;pU-JpP(@SvT*O&PY_6*QC)Q8J$Qr}+?&Wl5RzfMQH;ri(v zp5F~!^u6`2yVj*XJW7_-cMrlbj@LK)w%|L~3QwEsNB_sVgu4y{dTJ_|(ZO)r6wdSd z4&g@7LkH`H$McZ+%RA;h%mg@KlptU#8z|gj~Kc)$B^4M_$z9UPzQgxdHnLpeI$lsS&vh2%mv(L2qum3jt)c#XnY)^c*F8jsV+uF~Bn?97!Tw@I$ zvGuL?zH4WHdvb2y<@B4<{#N@VYqr_jZk@CIsh|{j-&tkb zrK#?#K;|3mf$!Hft>5|3L+koquzd0wXKMEjXN{HUvFwnYp=k%sURL>9dtmL-Z=c8w zEPw7J>p?5KV6rtiI@u~ME(=z?(S8uZ_T3rJURG&6h?I`E`<;lCO4gLz{ZM;w?VN8< zjt7??4~dmnR{2PKoSNeCq{PHI(~VQQX2so)wCAjy`|Zg&Im>g7H0)rhtbV1lyH_l$ z+|u6DDDm5mzy6jg%bYc*-@Btdc$_KA zYL?~w_BkjuQmG$*Kf;}8o7yc|^Kkpb&FMy0`f}ESl^B0N-ID|9%YXQYt>mUXS!shN zZE*QRAHCNeKhD(7>StNcyEsnj>5dZo( z>yU-)=sTD+ za-s*}(wQ60Lacan392YB`Y0xd{3w6@x?A*I#4U(ki_h-SV^A?YqH{5*dqy8Y+`{Oo z2;VFE9n#t(ngie7(R}1Q5uJ*<>l4jEp8G~8Lw~>MJ(#5WN58?eGa$Y?Hqv;6xq(( zsNvzZ!*66p*v?k8&pEd9C7xS8*LL_ChVyObY2@ny+xZGrccJZEgj6rG9c~F;Y&$QY zelD?{N1^jl+qn!idYSFqfan`+=R}13&UU6k%lEd!XQY3yor{s|kG8`%D(tkKzawKa z1I`Z+-WPDDqe?ywI)|gYp9G!rknE>HhtFL9Gw2M3-)BK*chu?UL8k=5FM`e{B>QF1 zc^?h)RnT!zl&^yhH)pFu&eN!invhchS8d3-3OegTPB&CjeaPYOX{LvqebDp`A&1|7 zHHMsLP_<1V=V%CnALAw-tm4m)Ge zjPHb!mVjeFLbVLY0d=X<)t*|WMpD{nlm0X z|8km>hXMUcnll)}SJRxsP-m~DIa8tf^)x2|Eq7%&dMUmpa&}FYvlbz*&2svqw5P_MCsD1Z#U1|c zBzutaE=rU$$l^m;5>kuIJUq!5?YQca2k=p zbp_7l2zh*g^915e-snUUc>HFg!(ZBzY;>+gQOY(tE0Kxvjm{YuVig-52MJYfbk0Qd z`YjHBdpLcI^E2vY_NUIR=u)kpI{X3ToKKyv5oGSC&iiQTd7nDnk%_iXoyF+F^FMXg zp@S{>G(C(4UzTHA=>w3d!gcVZ4h^<~Cm$omN}l`%MXPv{hQLSgK8+ZJx}N56}*$@MH@LdTt9&RwB#i@#LRq zhVyxHEwX(9PYy-&3we@2p4VbFN_mRDcycXrlg*RWILYD3en=~qC+#R#oG1LTULH@bL2cyok$*o8R2;l#GWjW~}5BLB*B*5fQ|0_*4Jyj~2(?JFxg6!|_cd_DYfjNgxW-5EWH z-|t3#%gdmTmD!HZyYVNjF*_2;cYcH*x2(7v-^t_`Ud80>fR*(k+BTBz32ZCtE>ub+ z!xJz`I}*qb_d;{zY{poMgz^g*J7)^Y7|G1fU_us>i03=w5h#m44U6p7SwU8Q_z)_% zg9>t_fZt6=3i30knhN&Fclb3`){j)sr?Y~d`C)!VmD3F^9_b|ox1c5?ee*M@nhJ*G zJNMu;7jNLSB15Ghhz3Lv2IPm|p@L1!!5}HP4DB8nmY+e@R4^vr$;5EVx(sa{+1twj zDuq9rj*RyN2n>xQ^1~w$IA=7oG)fxZ!Z3(T$j@L})HpfcsiDT>SgR$T0@N53Ov(>; zP{D(&$o-_?0SwhhS$+mpQ$cmUb2%04z;qj_^AsRUA5n0CCvdYgB|rQqHS*U{k*U(S z75z1GNPY&>qQ?38&JJqifQ>Bl6rfs=r8)WGFh*IoLDg3L(d@{# zdCoZqmB%h><*{Fd^4Rp@JhopXkByL)$C`}hvGh(pJAb4iKYk6zavlrREB|q-ZOM;c z2fy9(KVg<<=f@vHh&^^=1|P~Uc!fb$xfv<*z03r{Zw@0zw<sOj@dQ1rtVt9+>j{v}QVO2) z1O-;sR0^K=1iM*TgE<6V^aOdB12B1vE377 zTUjBjA0n@Kf^Jq;CIzp0f=nx`J9WJ72^j$WBjyrVnza`5nGK znu2vuB-2xXDzBp;<_S>c2T+jh2~g#SP>}BlQ04O|DD(uV;lnBDPEp(Pk^z+Um{2L@&p)5)0xUJPk^yBm?4Th z0h(qmK@gDC{N(FV`Na6ZwbiBWYa|lxpU$y#vDB;gDuQ12*&0vaR>rtN z;RB#LCy)Bat1`xM-BLR!gBq+@UgR$Wo#Wu2#|x2_$7@9>j}uEYk9|Eek2RHTWt6if z>IVg>u!p;8;p}a1hAVv#I@#osEX(10|2_^z-#~}4t+W^_GtI7m*0gt}^`=eBrH5U306K44b#8Y! zLfC-`OvFjA&>r~QJ+wbB`!&J0pf1uIl0D93%%)gR++J9DX*04`{t%to{TnFgdm9AyzByqmyRj`a34!g^b_Q#c$7KB38#f|%{W~zK z;WdEOiJCXZfGrfRwF?vZR!TZDKPY`azpEZQx5;(E>!LatlcG!fu9gbV^$F`e= z()GI)oy(q?DikwmZ(IziTd0|Ke-`Qmh@ZfpTc`uwLg8lGa`5LCs?9AF->b?c#V!gp z-wyYOVpFJP2*O9UcU35at427JVSc@HBE#*;LgBw2A8)O}f^|p=b+xUQ!Vo!`?U)<#83wGgbWo zlSm{u21^L0AZ66!{7{N^2@Rh5N zFxcJM(bV;~@cJBoCOdmFuKB=;z22!uV3VER7&Ck< z+|5oAPJ;X}>8y8FBbZ5xZ(tq8U?w{yII;O*f}Q4=AbePS3WHb^4#Wp*$gQ1gOm_GT z`62i-*|-P6Sn9(z+NyE@Uv1on<(&`5|p4 z$j$KPJ_L?lAx>Wt*P!78+d_pww$DEMVKRej)FTWr$vkOvd#E>E!Nu?&Zl1-xBa~_U z_vN7F@e2OzjYp$!gO7#iStRff{sx^62j9xN8~*lVU`(Xw?F{{S##flKP4Eu*F2djb z^q9;z#TVg&u0b1cayk4q;BU|-IG(@>9~?J>owXU{2LzU#Wji_0X&R8vhNt1r9qd@Z zSV4Z68bi1VOq(+p--+5Q8IG3+n;%AB!ggA{aJ=mqWx}zVW-=Tw)46dj?bd=`7Nu2$+3n@?RtAmsXg5`lSDCR zmU?&%x)Ud7Aml0dGnKOr(f~h9Cdb%L5n`Llxd}mTpi(ovug6J{A10FscL2hf%Had; z4>FvY-Y>z4%@3n*n(g-QSK-eWwBjgRgv%8F()Y&}V2(W?7S9OA3S-R$Id(R>a-ct6 z(YIel5Yu2#rwYo{AKQ>TpVRUNTt6ySYv@Ikf%+z%RKjf^YI;Be}E$S%U;Qk;}F7q~ib^-bmvHNgBOjN-kNG4-cm{&M0w zu?(BJAMVd7rW*bvY-Cq`oyv>BpX#Q{H(s3VlcCDS_!Cp0u^AW&xe=y1E?ElIMTT1! zd+$Py%U6coT)=2(ZidHPU4$;+_OL-c+|uG1Pfx^_pX3kW)yTd@Xo60K*)N%(sZM2M zehzysbc-#YS>jV%}Uvt z?j>URikTGtr()V>CEE*eZEHH~n(G;yCY9*~lQWA&U~=wKEQP_dC?*hLR+Ltw=ab^u zCd_o=GW@ZAreDr8H%6y~dFA=Prv}d5Oz-D5=b_7 z4m!yM!UqPncigU%n8;quW3u^lYe}bOEU|xku|y>UV%UQ`H%mTeDNLOLF;f7Dq#PN4Q*5<`vm^%qN3p)t;6T9ST=k`$K2uO z;XiA5`_jd2!&?`%tr@5{f#G;lVI_B=f^a?D4{YxqJp`QflKge?Dmo{bf2SNLn<|6%pBiBZ`9S?$AH zmn|HQE`|T>PIHjv+{G&vt{7g{cErNDZNnSNYs(vp8+X;{|L=>+%=`}*ci|G){#-H_ zzt8xe88d3MT~zDhxvMZj7vVnIJg+;KgV|Jd3%Y+%JLWnIws_~au3EIRW#!ssZ7U$d z<^{&kJUk@{2POk(hxzKoi(zF8RRtOD(Hi!y;D9Ze0w*qOM!S4*59}t^&L2RaZIQsD z*0l(T>4i?@NkJj7!g#0zxxmcxfn|ro@vt4q3CDx+MA!~4PK3h|p2j2aiu4Qb1r|=? zsT~T0dk61`+Tmbc-tdSWVu0Xdt0^xGZa4DCBv*RFYCBRCnPeyYens%Biv-~pb_(J~ z+bw==P9*q@v_0=?V+=@dLyT(VV}un5*^|N*L;@bwM*CB#u*lC{2-{P6&j5QR!abS& zV0t3FJKWI(-pi=?!OSAJP=Dx>jn9;gn_bl`6tb~(HTIF+63K)4D={8nCoi0U`mCaG zf?2CEE+$(P9>{D2a}(i#!6l}8a}wcRklFpiy?P;Qeb4}Snr0|Y`{FbnZbk+J!3T~@ zgb(LgB7i5G5Zr6EZE&d7GJ@R_;ofMteu%t#cm%YDBO|CJfYpUB&T9e23F4O3)cf-Y z=x@cF*Sf9vnUQ;~c;Q+*JOz@ySYbus61U#)d{YPyp|I|G7W{~Dc$Q~8SSN0f;H8L< z8#siHho^&qA>joCDuGDq2qbmj_jmO0bOa(v9f3&PMD0?pAKh}rRIZ!4l*-GA zx(oS=LgJvRvcMs1v1#EUI1NV{OsBfnjbJho2|kVpY%$d>g9ndDbcu`KKKg6?^HeKE zgWWl{+D+r*lxb%~f(wemPOz699)s3T>>eJI2&0dT85zzU3jO`^+?Ki~&DT;$_LVhm zOKmZ7(^8P$zsAOh%?oGl5gyi;pWPxsrzkuO33ZF?D^BY~^ifmNTU|vgDHOf1#%9a* z4*sD_x}PcCn>(eu9qCR*>+V?;E=!Hb>pH1?17TRp{a6QmP{LqKq6k$POrUolE>fMB za0|PxOQJt3(LZ%c^gSrdgu?jXaAt5#f@MX;vGu$%os!A`()kJDk&p?v)C8Q#IL-Ed zSwD@z_{{L)glSd$0uol7XLKxF*=E5qe0jqGtRcdG*Mo9bj1{o>E*5!_W)A;Q;GP}g#`4<6x`w0$Z)5t} z^P?$d3R;?Liw`KSsxF4%d#k3gslH^?C~>sQkt5|EYpqzxYalN@674OH7bmzJIVPET zudZPAx*8V9VS^I(l&flr8>c0Mlr}Xsx0F>CSGH8w6_>%dHkPhU#kHldoLzhX9`q}P z(dAw#jYW zQAuB#d`9{uRn=7o`gA01Os`tv+J{f@M-W~Lr8Q;9ed#n`1U5%Qb8RXJt&Ep9HWpWw zBWPojwZK#+EpN8YO@=C|F0P%{QaYu)beh-7rd39daI1FoNK{6BY0I2sjMD$!0=h9s ztv*xISlNZZEj2Jt4@>B!b+u(Fv+-5`$pm(BS!x*g48^lgHkLP;99v5l z&1+fQy5exyp+2H*Q7WHo=0^0p+Fgu=Mi{9tu5KtVE}PW?^WU{7BpMr~1PQO6Q^TsP zybAeGdZ+_bjA$vF-qcbyrD@ka!RwBl$3n6LmX_9`ZDyDS8-`$uG2n`+!u(d6?NHiK z?#sOW2(EE+HYzou5GMInFRL=RPUOBZ*C}07NxGS6dkaR&7^)@R*b2s z)L#!6?-k_@E#)=!=+_*R{FQaf{G}a>Td@pHs+!(h-dwIwUW%RjOH&=HB9*q&IHhbmhQNDVrt%FuHty`_h$f@3D`daHeRCCLUwM*u? zaHewAh#4xGI{Tf*IQmN?UKecO&fevtMkfP$>Y=o`y2&(X`KYmCs$sogm@3fID(V_) zioL+&le)ZNH?pOv4)bqCMXJ+ww5`BB5v(0^#_`^TP{tdXWNfx(YG71V)U{MJ<1*pZ zrz_PTC1P5XvtDsYT>~%g-qLH~l6h@w zl8Tc(0GG6is>-ffyjs8|-Z$@6G!)l#x-2Cx3G5QH%2PGXVP>kB*Y{+invWaGt5F5M z!k{aaH&pPF;+3MbxS_0N2G%3xSP0d1S*Rp4=O5T^;4Vu(^^%6#%H;YEtDNGRR5}f_ z>MS!YSSplnA>vh60dZmyTmK?t=FWNlYeqOxpdXaWvf=Uv@Tw@XyN>YZ5=Ib zOIqhF@-24#-Jd-LYpWWpF5HD}GDlTa4Hd;L<)x)9BTIZ&ZdNFBsmng5P&0GY)Tg?a zS1qO0%}wZ^rT*EF(Q!p+u12S??c9^hg`%RElN`E=Z$XV|hZB0&uEAV%)lr8O>ngBt z!}TF`N%t~T(^#o%hUpW@qSlmSJ!?wTHH|4Vx~>!5YqWnEp6n{9#zw9sQuX6`nekp- z+}PAoQ;Nki7xJ~uH6`98l+1{lv$=L!ZQYDoxApPDdD9ELgt*XgDwnE{1h$HA?T*B#Vf z%kfHSUb4sgW?VMA>F`)1rP4LG5{zAmymwmTVTwVw+|`8O^}ojEMl3wb%-oD^_clx_ z^IAGj^TqWTvNJKwc3EOHVl`G(TE%IvQ=(W}msjHUQL}@09jkA~GNINagj*?Jp?vj} zDw}S)kP}?c>&jD&mb!1^^jlgzt);TK>h~+3Qe5S57u8~BcWbq|=`}5iTM4iIaaqF6 zkgvr||Kds-qpi82xKy)$GD0eCTtsnC#^xD0&Q}!HcX5f^bKNVdmliIGyz?-P>|GB% zzm!^xyLt@01L~@qa8XO9+t65y6^5xN-ZOW;FGm${xR%c>EiW(gO~T2EESZcuH+EXO zCjF8#e`8~5>Ym*j@s-6jHO0w=B6Rwc5mu_G*0zo%t=L|0=ish0ua_-ME4+iN>YS)n3%r=RgSeqs zED=jZT^M|KA)e+Lbq&+hf6a2!y_CCep5kq}|8}UVqAGbcO3fS%o$glMs`s?JSK(bR z?5fKvxKc{q*O;u9V|#)(z{x82G?lRG8x>~nq<3-;BzaHoHjHVxQSN?4X+tqeF?Z3@ z6{+Qkh9a-86_{PUEufYXd?%Jvj@t(AYm{KF?0SXp)+k=j@Uq!d#dSuq19{#`&YSp> zDVTBCT-(@OUvJhtE%jA1v6j?o+>4!Bqfvpmi%x1tE{7V*E79ZJe%bY^s~Uwm3`+myZ`c3QB{o@pJRhf zSghTuGVM~8jU1IMd1HMQFA@HopH4R%sk)-3vXQAk zbau-)cMyIO6 z)K`w{vuTpjhLTM2ET=U@nO!IrFQ zZ;#eL^ZkB@$YcW-rDQa>i*w!FP~PO5M12cI7CsfhtUs!1yWGS3f}>xW*~%=2tE)H`hH1$~K^1O?-I=tpx$|vY z^5)*mFIw|<+9K(y+nX-Us>H3i5x?uQHC3ezbzZ+s?#3ktP8qhv+^Fg<*aveLvu1nH z^-}j3mD=^f%;8(exyxIIE!CZsyXRJ_yKFa!Qa6QCwB-gZNq<39Zn+@vXdNal_oz`~#^2GT1wJ+;fScC2T zlyNBk6Z{ zaz;U8oqLDq`=-PF#?NA( zw$uJDb`ZT9boXSucBsJUF@3EBD_=HJi8l4h-T9^jdnaDlPW!uVSY5$Jre+>5bN;W6 z7`AlO-d1I8bE0&@1iYTGXmruY1fK&OF@DsT#9+LNx2<(W+mOVt#dDXf+IKD%o^5M} zEgn4@f|c#77S93aFIw8Vau}Wx+!teW9t8+Ff7uaZhpkvPY~ILmkhFHpZQmD<4IVLm z*y5tatqYe7ows7y(D};}!xkil)s0FF!$Vd3&P4`>&0pNMVnyqMwqc9fmMmD=zV8T# z+*Q#q4t==huUay9<-(;)hONK@li&)-xW-GmQ`M4MU+~)_Y#dmXrKJ-SgIV0-j>U=c z#dF%`VK*qzK%NhwK$f2VrYHvq`=v>RXhQLRz8|(*~4)f z9zU$62-83Mi$d1dzxh4+ z?kE4jwDz@X}P2~N{_c;_>LgnSLHu~cw3eK z2;yB;{v&ANmo&a3Xx==V5(GQ-0zQL`_bkAht-?N*i~8nc>2$MC<)S_Z%FRBNi~1WW z_hjQvv-XvneJU6AQw4fQHck$aBM;2sPcyv-B>S(l`p?rHoB86r)8jU{5#qOQxRLYk zB)RAAmvOuL#<0_~67GAB)BCs?2=sEFA`jq|By2UlW1eFqkkAi?@gzNaLjYB53?#rc$m0UJVsnEo*|wmUM$`$ zZV|VOABvxe--tWKU&Rm_mib5*vqfW@4Dw!b^BvC&$M*w~9OvX1aiTa`tPrck263i% zs5nnNOyrN{sh96gCXW{J`!C}@Rm2o!+{VTM!d)i!72>s`v1tJRTjjn>d_a6uY3_;&!CN3A(h{uV1*8|IUmUw}0XkbG8rN#w8JDSubw zO9|=zQv5+Qw$LCCVOpnuhL|fF+h~v{Bkz~3n z#iK<2(w*|t#B)Ucw4L%liPwlXiMNTyRvN-REccV*3*sx{-^CBae~RCT{}TD|H`7fM zjSV%p^X2X(@|R}}x2HH#953!KR){rXlX#FgM_ec_6OD~E=r=ajz>_3DQ#3Z#AiqrR zE5%KsvAG8SJLERD*Wi9s?q|ep;_KoL@gwmIk*}>}d4Cc420yyf#T>D_*jqHV*${4+ z-27cV;~85eV2RxP9X;js;tX-NxKQM8;~DNKalLq!c#(LyxJleB-Xm@ijmTG80v zf}SVkeqH=j{8`Mz!iwqbE*6RVi}hlw*dd-MULam0-XT6Az9xPr@_lqnuZOs&xQ|#Z z9wIIgj}y-kuM}?;w}{)te~3SbX;?fn-R|NLaiTa)Tp+F#&lLYC{zZIHd{KN?{6-97 z5zqAU!~xBT>Mqc!or;CCPco$itZ|Lowz}~TIAcY817b)?^vh%X>qIgckxs4M=_M^ zhR+id;z)6VSRpowv&F^Yk>W?@D&|;*?JiE5rlE`Qi$3op_dbnaJ00 zQ_t<`9$vTN!+;oOZ-*xbjT==iE$F~d&}KV+>3<1kz$49Q^h99 zXNgNB?+}lc{CM#^$uAQBOd{RCl9x`bzv> z@*vWr{%o<3#9CrcxyO=-H$mJ_@+!G�JR^k-Jr#FZpu0SBXcGNaqy!pC|c6B44jg z|EtBjB)?C5T=HkccO-vb{9N*HMBan591*b_3BTP)l)sPU1H>W{>5mpGC7&kpMI`h; zP^2XW>hBPbmi&0}T*)sKH%fjDiS%!g{C4qv`9C7^ouSnKhWLTxpNRjKoUevsxC|2c z%N7%o_ZLTz_?s-&inGNI64#8ANa#CFJWsqxyqrY1t4Y-7?ULUm-Y@wx;&#bj6WEA29DEW4gFVUp`_ay4$SIGm|EHmvw!arLaAo&n+wB)p~z;HE^PZ#-?V9IBU%OzhW z9z&w;ju)|9HuEZ`C_`MH3^Du-vBhQBPaH3r_bFgLE|t4doGvzt?cySFrMN~sO*~8d zlX#VQyLgxQ0*TDNB)%cOEq*M1CVngaDDs7jjGr%>eJZ#Ua_=dceJaSu%1zs1jK_C3 zl6(U+$(LA@FkoP4_MzZjDK}rvNPpVuBKa~#@=9@&X!e^R=Q|QPFK-de{u12J%l!d~ zaclOIK-zht`&-fMAHki;eG@P)7KnYs0pfUZl2|I5{UgLT`$gbv$rp%+iz~#{BHy0K zbk7qn6aOUsRlH5)3lbUrNzv>F!Tq+}--&q(IsRT0jm>+wjm>-TJ;^^5 zKNr6iX^W2We-Zf}Q@YK54#>9?(mhZdCYt>l$j$x@I7#wSu~MuR8^l@SAtK*xNc~5M z$B4&^r;27D2jTcSD~A8Gc!T&C@d?rF*C5Fz6<{TaCVx;o0uz6@9+H{WAO`5ck&E2Mjk$Tt$w{Ri=4af8TL5z_w_k*^%2`!VrV z@lDapuUM1gcEj{DOuc4&Co~@oCNYnWAfbl``y+~Lh@o$YAgTD6C-4=7nMV?0f6>!3 zhHmIH^EGJZYjCpUWn#V9B+e8M7TZbW$IRd0GP;o|GmnF7=th2y7T1x;?0WH366u~P z9*Kfc-w5v0ApSfO@h5RV1@T@X5k8OMacwm9h47|4aGUZVp2zu9S=g_PxrM2Sc@PW)5X?NGTm)B_u}BxdT5}pE`5H_O6!Sfj)?@)QwK2n~guF>FY+;1x=Q9 z7-ZhTa`0dq`oleh{Lxf^cX+2AEpt2mPi&!%9t{hr2_FBwE!356#f9B@!?lGPoA%Hr z*2t6v&Wvf7wfFrh5V&mihIV61w9n-Bw5g?QtTh|#H*XD=mVUJ^7+)5xn7(XTWobhx zI&*ZgwJv*dN<#!1O8gr71&u{f*x6**ggtF0;xbP5-%8uh-)Zg0ch{&FAU zQ?>Kt$jMCY|g0eUKZbJBW|DNKW$}t z&eq5@D^YmlnlA*+V;BTyV3LC& zQeNi5f51nO8*H#aT0y}T_=wzukKkj-A#9M&#(DS-e59@AM~GJe*dV3dk?7YPqETA! zu%jC=oC48WdtyE<HE&5ZEB4MQhj~Js*j~2I*D(j1AIR5W)s&C29yZ zNdJM5utEA8QiToD7g3$CK^lin*dTomI$?t}jv9px(nAm(Hb_51NZ26d!xFGTdIW^9 zL0XDrVS_X~Xl#(~K*nH$l;1bP2I(4932cz|LI;8k(l1dRut92}U&01yHi`oqq+1XY zHb@UeJlG(89Ld54=_d3C*dRR(tpOXPSE15igOtyvzy|5ZhyWX;M?)uUka9B!Hb@K5 zs<1)&DhdW0qzPmYHb^HTyRbppy|1xBO8Y>tL3$#ldDtLbfYQPSX+P9HY>=)*O~3|e zGujR|NDo6kVS{uLY63P$&q0=8gLF5P7B)yPKrvy1l;5ks25A6VV1slmvIHBX4HiqGuR-#6S;;B(xXu!utEAb zG6)-_n=#N}gY+dN3mc>pA%qRmb5WnLK}zePutCaAMA#thgJfZYv==fD8>DlP7uX=> zMj~vGeuAol4brPnOxPg33;hl@NZ&wBzy|4I$Qf*q{sCHGgY*j&1vW?@Mzz8Q=`uuz z4bpk&qOd{Ar!`=M^gLu9Hc0P5CSZd!j7-1=>G#MyY>@UqoxuiaJMsb>q&*M>Hc0nI zEx`uqMpjmVvEm9Fr0bAR*dQH-)M0~kDrz1!NFPS?!v^UR?AO5tX(ciU8>H_b6R<%# z8GR5oNbLc5RCA-#7ukgk(y+;H=&(V0C+ZV6NcpaD z*dRRwRSp}Z6Cs2R(tb!5Hb_??^RPiW7RkZ}DeY9i2I*wf8ElX~fW|R4Nbf@W#s(>E z0~s5nP3V`#1}W`s7#pOMSbS{Gr5}gD#s=wCD3P&2nvW4^Y>>7iTgC<{Z`O?s(tQx! z*dW~<889|TFGr%r2I(hg2V;Y@0R=TSNUue7V}ta1RG_gzx*3HqHb@%~-Pj;~9np;q z()p+fV}tZbR2P>}>8~OTU$~oo6!H_`NiXEk*dVQj#MmI+h7)6h)J92-4bpkYhOt4~ zj2>ickd8t>F*ZowK-C)?q<7=Q*dVBa(qKpmFe?f)4nL`(AXf&K|kWtv+0{r zKx2b+SU;8mk`oZ!*dYCqu@Nf01UWP|NQYu<2Plc6T#RRBa4U#5NS}Z^(~fM2J11c% zb*rpzv?70u7jA&q#$z|#s%s#)Tmsv+VjUQq;IE~TRWMpgSY&{cqw!<&m_&uj=^+uP9Y>Q`6750K7ugAN6MFlsYgGSzrCvJk6 zmq0vc7-+bce8TYBWQ&HVg4GAZw3RotoBeYGa1cg zTAA^!82XX#UH_Ps!LMr~Kg5Gf4D}5Ip2eu@*bWSS8t^pT00ul`SqujQp01#~72AnP zg$6ub0b--5FyJ{Kv9tMII}Lc!FM9Prz^;{V(p9q1D>uR$BJFX5HR5B z3bL)(ofN=;rz_}Y#U7*p20UFsrWNCTA`N)D0>_Gtpa2FuT|v}}ZRc2q0Z&(uX2m8m z1Ppk(f`}EHLIDhTx`MD3tET`4JY7M^it*`T8t`-lcvgNk1u)?03IbMaXb=Jz@N@;3 zLPk>n1D>t`ZH9)00Z%?(ls$$G3j?0?%P!$m0Rx_FayBdsc%Fsc8hZ|NI1PBZ3eb19 zQvd^=t^h6lCIv9y=?c)&?@<5)o~{5bZ4B7LfTt@cv|?W|1Ppk(0yO=P6u^L|D?ro# zN&yUbx&kykO@Y&Zrz=3yXHozIo~{5*pMjjyfTt@!)BlUJ2Ml<+0yMpiQqzE^D?rmb z6u^L|D?rnq#(4n-JY7MC6+4##81Qrj=@=<&dKmC@1!$Bf83G18T>%<}&*ad6rz>!) z90ol3s8seORyhoK(l7fyrVaz1Yz$U840tx<+7~-J0XYnKx(ZO`7g7KNo~{5@zL5eL z@N@;J@;_4m1D>t`Rlb=581QrjsNuUPfB{cefEwm6BWS?W6`;DJ6u^L|D?oL%ad5$a zrz=2pEv5hlJY4~*YZV1B;OPo5Qc9=;20UFsmKD2|-3kUgT|vx>-Nq;|;OPo5blTX` zFyQG5Q01dIIl+LZE5KMfiXmXY(-mMWok#%;c)9|NrP~+<20UE>#?rr;3JiF<0*s|A z83hJBT>+ZydJ15`(-olE%6LtI0Z&(eu{4G?1_Pe1z%oMz20ZzQSauoP5e7WzmmOwI z81Q5ZvmIf;a}N4I?0j|=81Qrzpxa*qe;V*~1*pF@Si;eOrz=4HorzhW20UE>%6z<{SKK-nj9&V~U`SAeqbUf9n!p_84gh}gzD^Z#~9x>A<#eRfW z^xQtUEJoW<Oy8`iy-U4z2C&&#-bGV29Byr`Q+6 z6<686V9oZRJpxX6-Ht=qH%>YXLy)w2SlP8V?L5}V{uMQCX1{?_J?wMP2IK4-Amd_t zDcp0HeGD`_Zy$%=|CuuYuC+{OBSbYb?JRhuw%rAO=wQDCYX{lSLhCep38XHzdE3Pr z`ysgF4SN^tKj2J+|7)Ah6)>s;oU;UiGZuIXQLDO)*Or-asedl~5_|&MGcL=11X_&X zH|XFQm#c&~n1Nk0uE^fVRx&&v@r2<@Phad4>IdsHuF0-@1>9n1Eb+ffL37}cjO+8* zs77!I1>KOxMlyq&U|hzHd2EKX;F*|EGH%M_E?y(--44w2q{9&zH+!x_BK;%$tIHU9 z;f!1TeNfY2Ex03NMPMejjo`KLX~yaRuON7X6;!i6a1Ro8a3$OP*}x_wGJ`u<-&a&I ze{dVS#M^;?Ag7K|k5`>e#b*7n{5J*vV8@kIO*ZV^%gqUDlj>D@s#E2Wf37C)&}4mX zA%{*3d#}>@w8T}Syc_mDsB?Bz<$S>{*`4i?&aANaW&HQ>p5=^pJYSRk4n*CN=mWN0 zanK6$pOI!NQg=waq;Q+1HWr=h_R zG1bjsH!{z469un9U}N5XVP0&8_8?(2ag$5Tu&Ow!%L=8_40sO(n(jo8G5eUcSvj*F zdY)@uAG0UTYpg8l=gK$o521UQ1*pfss)7Y(xvGaUq`(|bIgNwp&t_BEtJ(YTs+nQ> z*ct(1#**JnL%LHb5=r$C{(H;c7?7T+hy-5UY7PjS1E-idE(Isy9`c(*t* z4_a+nf@sTsKZE@d-?k-4v_ftpeA}^DVOKDG;A}F!__XNH;kc=)3NdizQU;-RtFS4- zDpaEISNOJ9Uf$G~ZDbB|jelMle*zk_FTSn+L5uM5?8iTIOSsKp5N-MIVPxNnZ#(7` zX2K3e;{6E>J}sCw@2;|A88~z45cD9|j=S5_j^nYzV0>Gu&UklU_Qms%J{w=xw!6nD z+XlO~tyH!xL+(<1TMvd6Y&=zUbFJ0(To5lKhfg%MorFXNvVUb_BoZeh!Fx~IC9qH7 zrC|7^&kB5tcuTH1M1{UG2NvFk)OVow;M;+%!o#3BoBz%;Ek;DIZkm3Wn=9~DO|uXi z7vS5DWmVIBgw*T!BJddpNo#BX4Bir1xEWg~Vn*fjEJg=9`dn<7EBWsZGh7B|RePJU zrx)Pcj@ioFd>rL9?rKEWW8ZD$dFwDACy7drZ?OkL%!O6W&=Q5rrOhy!+-6wVhRrY! zr7ytOb@JuP$t#e)1K$`GV5l0cw!@F+Vs(lCHDtVmZ^=>2!3U0#rdVvf50!_($l$FQIQroEQx-!{#o+}1SQP415nhl8vIsiXZX86- zRBahJ7@O4u7-@>T~P{m+IMO${cRRdZZWM3Jfv(O4ZW zG$%F2D1LpYE`=o!V}xRzs)LB;CTBC)CmtyA0qPzZ6%@fmtEs3but?xz!ZIB$m(v1q*Ff}S@esYA#h>Ez0XZw;(k3dFMcvKv}M5KgdEpP*HHsMw9 zrpdB&w8~~xVK}kJ@4}Aa`N3*k5@EAN)gBTEG$qz0f{Ru=MD}QvTutGQ2r-J7m>6yh zOp1=36rZ%68zi$ZDST=B6b+auic}^xI;6(gl+dTejI2o;d08#0!)(TMl+Ti?omd9Z zP9;2NP0>R!N{;j)hmL%B*h08O0+$J?Au6Q|t~ys0D*wYmZs7<35$OoU__`q-xy1<; z8H7Yt2Di%bO^RVhUHtr0otTo<2h%q`(sUHJQ91^mPRw9w656B5l}3Kbhx*ax1kUrWAGk$hkU`+scQd%f<2N!0 z)aYhlLw(ZphTwl#JPr%gz#mTVNfPcJEg5U|2;1qtYTH{P1>3nZKUkEw;#^b*UOJ1? z_(d0@ILaVR_g!;IJ1|=67RMkmoA3uLe5|5gL z@imRXLjjk&n^yv^aW}66EOR&UUw!oOaZ^dQP!J6sbeoptrnERWr6sy4R|pQMdP8B7 z?ON!-6rlreOBOotwq&6Lt6V`@6xUr0!5!T^Y^aZ#2h_iR zZWQG}`@c3shXTf}FW7}bxuT*ch!K2$H^KPW&P{M7m$ME%FcM$xL2dl%ZPs1SH`))i zWM@t}$krcBaILY;NeBam&;(Ye@KSe0TY`CC;= zH*u;rk)4K4!kQ;ZqxqD|FO1P*NmD$(ptXF`)Wa`mt%x)j`9O)9!bc)a51}C2cBZ>Y zn2j&0d*N-|nCJ3Z7D|Ii`9zSyTtR4wZ)&wzAATbE{$U~A@Lm+6u|$eOufc!!!(YZB zJB9qC7|@&oIsYZ^k0d`$@r50PUihXO3qn5ZeAt`7qG`rdtgYQ$IC=&)@gi0AVI`UU zhl1gA<$*#VD@dgJByTeQYC0&YWD#P4Dw5;_lKduB3_qoV@Z*~r%T^DWq@vwbA^cN* zB)V1*>27{9T~L!PH)E167bLK{{qQ{&U(Sm|@tue70(>vWS9iy&vCa8gf4Cq0#_zwo zzYQ6zI9){j!|)x8?-}^&4~L}I!vVz6qwQRXZEYtu)n_FBYZ)w?{0SgY2VdQ_=w2={ zs9zsbv8g`U_|FDmdFB`6TaIt?hpo@gU-3K7qCLi2oF)EM%wF82`rj0P6feE|e=&Ri zRp{XV7qj<25FI)x((Qj!U)CD*+k0o=HZyg9_kUmPTnxbnLb zrdsvWJ=qNW*$`WGfgRk4v9Bgaj75ye)es~$^IQw>IKskh zV&O9>7H+JzP%>y?Gei_c99^p}D(&iL{LD1mB*%cR5>KoaO}|5dR4RgNuE`Cx$!#ddg!*6DH1K~D z>~0nQf$P3kuDe261XbE~pF^3BVhq2{N51RoUsZXg;lt`098vz7-u%9lb$tD<;OaNUx-X&r7ZG9cfXIj;#|}UMM+x|Y zsF%ItBPxb=ADr~2c30HD9|Kmsm>F-o=M*@4!psp4;7Q_i14uEMyR|IqsER!IKmktW{jCo)tK@E z>VF zFr#oD@tSz`{%zs94;b97-{6{E7fo^9A4RBD!y)O7?n!SC|IY`h)wQgS$obcz(xP{D z8(h;{({&u$8oOVabU%p`ozyV@Q}JkPG^;43eIx*g8=$tv@`(|c5UcuB^6SR6TT?ra zM5?V(R%}ECCbr+ruKy&AEyN%+l$wg%n7))da6rEkj~&n-L2O1a87=Pi-?2pgQxR>a zPMLVlGBI(L_>HZNh^0dG7>*N1YtlJv>S$xC{rz6|eShysmAycE<9%c`$MLjo#2IgioGNRv*u2mN6F0W(S*66F!BW8!HFjy%85wz=EC;W?mw|^9BP{Pgq zVIW+sF*g5QlW9c6qNK+?E?L#+YhPLouN5pk?j6mc(bb{1C zmQ`WDxYVd>EIB6p-x(xV`z7&2?nn8tapgiAyzRQrKQf>zy2VGr8aVSK{~Ty6cuzaq%WhM%3r7vrap0 z-1MYQ^d|%RPE9@gP;-QYx!0k5YpgQn>Xe!7ug3X3GMew{>JWvu`e2f(c?1@xbeg{! z;y3C1;`f2hYOG<0BaTMe=QW2AN|Ik45*Tv34K7L=+f^&&n&TK%&q+K!RmIynvei=~ z1*=Y%bS8zF?B9tI?2fchOY$pY1-n%ol5{n~orM|du&}WG^il13X?(`?G40j$aQA=V7{gsgRb9NP z8f@IBYhZmNpa)^xCySp3Fs>TM3 zr7Ux`IsYU~t&A64(p}TAa%%QPL)54S=R4~B5mD9DbrVc{>eP@C&uZKOGjqx`rS<*A zD8!JBV<_fi5NLybFr;jkKlSXMKY$qKm*^OXlNNJo$RgJBxv#5VFc(Qhv z%#BAzOqQXY68^mUiY84p{%j~^b^Q6~fs%vq zX1mQ8H*V~Rvv>t&#H^{f^gb>n?6UT0wWAO`8CNJ6{;|d?mK?F{Q+;2Qc%^gbWmAVvuZJpIP^1Um4Pwl{w;~ zTyi9O_prza(DYYT3%X0gs%Wne!UayRE>#6;j^eESpLAAnWb|eon7KwLcSsqhRac!< z%;p+*C`(zt9l1C|sCd;r-EnSPb>)=tJB6(d&MdPdV`~3j5T6;Y!ueZOTUDP%sPX;h z!ZX+C?$Q)@%Nm>Ua?y8sbXOh(TSWH2e~-&zl&Hnq`id%c8|qmHSZ%3OjG3b*kHJ}RaztzX zXmVuW>Kf!H2W6K~)!M(h`A--yxUXD#Rpy61^!_Tfe>S)^`sUzqGiFVk$%{R|zsT|5AK4mpaSx73GlagwA^B%#u7P~L=AMfim}a(ufo{`PTh`0XxbApU<8FPl%!xF6pAU;U{mUN-&E zw5kZ6bxZox6hE8gacjJM()EVIn&N4*{L-pYe8|1}Q&W6xmM^L*Qmu)U2k&HbAMw@& z9Mz81^-ay?;~JD#{ozv#)t~>(@wwTzljC!bh z1iuxm6#Pw)&mPn6T7rJTprDG2g!}?Y^F4hmUnm$8RPnpPmrGj3??$?xq*eTGr1=Iu z?yur^1IJ4G48f^_X9@CkDl9)waG@ZkSH)i^sN#2{+%ie4_}xg~CutSG8|lX+t>Skh z{hXv#d?lo}O8Q;F?Si`mzYzRd@O!~u1o_G;f%g3Sfn3C0AE66`A2TaXXK zQ!d{Hqx>g0PH>{2io=9*=Sun_!G(fX3I1L17Qs6OR|&2aTrc>v;ERG=1m6+dF1TB8 zpWp$(N~RIEpqU>(8wf(3%D1d9aYg2xE<5bP&7L~yvEit7YD<0U;s@GQae z1s4cjA$X18je^SrR|q~JxK5BS-(`I^3BDruhTt~APXtxmCzMxlpMVF2|5*@^NGN%Z zpkFW~m@n8&u&rQJkgx2fJzWHQ2@ViEUQoq*Lb~~Q9JQH!5xBo1-}*iS2AfUb`f<=P81jh})K^4~WD!~ncn+5q=P?q~fkin9et}R#~ z7!~X;I8tzu;KhP}7hECunBdET9|(Ra_={i`7TDCAFR0>rBV8`(L4uP6&lOxF_^jZI zg6|7{BKVo$mx2cbD+Rq+z*B!vuz_F`!S;e(1bYhd6@J`rh~SBWBLv3@o+&s@@NB^g z1TPl6LU6I*^@6tu-XVC8;Ddte1UCq75`01f-ehxEclJ! zFMVflcdiZ_mQJ4u%b9!qS6ejw>lf-1f^%AY4`zAlyW zmI>Z3_>`cEACCO5C5^BQs(hB9iVKc>6%QO(D!hsZjFI5yjqsg zT!{08Uqpm16$c#qt&sdxf~%$66Ow*P@HydMm-JhL+l1dO={w<5Nsn@L_|3iM;zsj7QP1&@&^*pXGci-49TA?I79f01g{kSYQYSZP{kDoe-qQtbDNZ3 zC;96IRUC1YdqL8#O1ZZsy-jd85poVnx>Ar~gve(QVNXLMZwBn z9~O)dQQtzrPJ(>|aoVQlEx1Y{mIn$k9V^5XtLBS#f-%8_;84L~f+GaS2u>25COBJg zj^HJNmkZt^xLk0h;C+J63cet?Met3*-GX}re-=C}=sv_kHOrLe z2-X&?E7(9VBG^)}tsujTaDR1O3)orG-30koX3nSTdKOS!&jPAAZx(!8P+hMAudY`CcMHEy@N2;gUWY-xPcR@D6pRQq6)Y4i z7S!>{%O%bCLQ~#I!P5oRbt&+(B(1JXAw6Hx>bextizThDOCim-N>koLf=>vl>rmid zl=Q2DZwczSoeeU1?vko5^N#ZMlddTl%Trag#8&sj&fAoZ{T=IPZOLa$X9K%+|`0N3EnEm0Ef)K zPw)}J#|8OfZsvb1__^Rd!2^Qd3;rr-^12ZAvjsB+>j;Jg)%7TpYa(gB@SFQ}5$q+{ zPjHCf34$X9#|oY)I7N`J1LwNp62V1+iv{^=aOSTPTr2p9Am0wo{H=o91h)(Fz2MA0 zAjoZg(*^mqZ>Adv@@3xa`%%G;g2xE*#oo*xE;veXoZuuubsY`m_|k8dzfzEa%9y@h zkS_pddX3S~a`{B<>i@3kZbHApN zZb`)cF-a$gu&cYIdl6}uq(>4VSM`&K8`zt68HF>>nKW}09ygmYbGnP;_14UBvu7HG z>K!tLqi4)83P}{YzuBwX0Fnv!W`JZyJ=Uh57E8|PrXT4`kyyo6-yV>>Q}RP{h117P zESx@tmKCPlFrYHVjvGDeblib@+7uYCwnvQ~J$>9+MpEv?DPxk8qo$9Vd^&FZPAc(x zX5xg&`lv}L)Mar0!cjA4PMBFA8Z#s9EHZAJYHka_BBO0 zy$|J;x5l*_)I)!CUgQXQbIz@9H(cVZlE?X<`xJ?Q;l;S-)l5rs^O%3s5#`Q1!3|cV zOR@~VJYEp>=OvU|pc6pWgP-mwlw9BYVBbjatS^=^RrVc+a%lFcpwy?|FkEZY382Kf)uefz&n~@Dh4j=jc$f+Bq_B5WNtZqHK8F_20 zzSmYZFY-+dtV!!z|BT#`MnvWBFv}NI7?IcZrUhQB^cE?uz*FI`s5g?^Q`hD6pSQZr z_*H9e9e?YZ;o~P(T(jnyFFeKqe2vDnr+zp-QZZ!Y>Yi=JpESPyn(M&M$2V>D)Qtrd zU+;1C+v~!8uBlvBRQn9ievik~CU(wM1>3bK)!Us%=q_Pcuw)I<4gq*30zySIC@-p%_sxDiSh;bUtB&B|67+2#s5B$j%)n; zzaHRy!y7rJ(%Tn0o|?a=4))C2$~5+dA6rKP>#v11H?PU=dt=wy?@#SnOR@D7YqZ(B z)dv6hHcyp|sXaZkTD1plrH$oXa}58wOn6__q=~Q3;L4_v+^M;<%{JTD{``i^M=F?W z^$njvbW=veztQzAWhK@bO`ZO3PNd@E%JOn0Pf2a5_Hw-xsYq;OdH*_Jzw0Wy6q#+z ztxA$AX+#!OmKzHyyBOS?`9_;>w$`U6>{GNZ)c=-B|Bhh4)raQ(^5g+4C;U{~in?h{ z7g`7B95-O!$qll)-MO~MzRbFJb@gt|?l-iuu)OK)1#8R$W~Q%SW^bcq_^HMfX+N8_ zd)sS%{^da4NYBkiq~XY-jpg4i_7`pJ1syH%Rc%;0*)-a9Fca(QR%BKrx3=q%R_JrI z(M@^9GrF8x$D(z)6@40+turewUVYU2W_6-^+8lbrwV-Z_?ns5T zx@hCZ%FIYk-#aRMMLyf(x&NlwC(aJf-n`csnzl;W-14!lU+yXY_FBI#>+PF%L%oZc zw^_yu{cSeML2qbmcn+E0dS=t=57+u=^Zr_W%9YIphv3`&rg>3U>kXq#=2J#wz`>WM zPVGtA7`gmFPP@JPyQLLmR@~e7veg*>BNtURh!mW6*?Eg9>qU0qf7rjMvVLULc?EM8 zRpw#4VFbO~-)!~|YmHXr`|p}tf04QWa7ONaf6jpY2rKlIr^V*IX;B0s*njI>qhQRO z&3nBCiz@Sr&RjoWe|o01%DDFSb4HyLImf$dbEWrbx5l$;@M@DeMjK=Q-{yW&*$|bC4rYR0kukF)(KEZ}R@$9d;-R_e1#^039mvm2-(j>leyiDWNP}euyhdPa zgG#f^Y;*99H`e~G>vvnP>Uvzbhq3d^8@kk2&^)ZN+0!e_KdD@~)7T$0mR1@? zAFl1S9-cgKD_Xv{vro1C=45^Jmj5l^)ZtLC<>SU#S0S=TjVYkF0l z3Huh#b$iL+l%9ao@YNf?*gxO3$bdz+?=hNq#djAT9R1*c{dfy2ytQlg^4TM2rzLr- z^T8nxx_h%Hb*kzeqi3g8X*SwW#wV3K<_@bYP%{Q~n2oQiG@t&Y^64Gsq09rrD%%?7 z{-EhWZ$FXs{fYG*uu)Ts4Y^q zb^lR>jI=oH@mdpb`s6t#gu>xmls2rJ@h^P^|8dLn9ge!5rgi!=>k+cglKllI$)2`2 zqyuJRjo>M&GXvY!HvCKfl>fMu(YpiwdAXSL_RT&m0}JbwwUMwNz#7lAx1u7j2X64# zmvurJTgk9_=S8~xHLS_754AyY`ynix9D90GtoZHD@P^M0CE!7u*G#i)Mv2e13$U=t zu}iTM_1j-!fmz%Bsy*&bu*=G@ezl)P`8u`<57xCO;+N*2eSJGbO0%DXPr~+~`dIVX zx0G`w`#d~b-yT$om7qNb((>&JoYgn7X?Vm&h!dl+eQ68a*KPk&!n@vhe`Qm<1DIxZ zN5~&*|AwOD>~gr}C3_H-k}uoKVe>1t1ud`I6XEOEY~GEq+1?Yu{e8}9;M2$1zm9go3g#LB4>C^+c*mM@7!q=KkOZetG)0vM2_!84OANu}o zI{Z21dednExWRN9K=h5Kvm1W8$#hn% z!VMZ8=LUH78;{cqM(p=Ecc4ZGJkAn0u%Fji2+#KSI*(@>#<5;!3fg6W*Le<38R&H; zpcf4CI*(>E#HI5NV2Ibb4(=c7bzVQlFpl#&52M+R_d3_2VkdZ=SCKc&>wF9HM6a_8 zO*h=@TmWyMj100ju$?wV>y%2tLj?LjcB^rmUA~uI>&NWqw&tQoIUX1 zc0j&id}KMDa3b)r<-j|}CzjI;ExW^VUPedUX*sQ-XqV*-K*_Bc&M@S?k>RxKh?CF^ zrxoh{R)(_)2ELu)+=Tt#$#8}O-pz0r&-lFz=Pp!bTZS_a8s5)vPJ(5R`J4st(t4kB zH_mAv_c?iJ@F#rE61Znsj&lMA^YR=ghEuoObDZbl!8>xC^{B(0InGD$*sbGa-Cz*M*bGgaHy@_!tp@n)R6N%2E??Ga~3+o^pIns$c&Kl8Jc5e z$Z6FDKNN+Wdm!_ykTaq=f|!P!O9OCL$SFi^&j~qqL;JZQXD~+dc_HUKD4G*;>SCar zA98xaqzgjMMs&;zLyiGo&kZ>T;gE|$PCew6FLef@3wK%S3`btqrA{Th)P1S58lLE} z)ZwiJ6-yllC3`M)^3l%*ZgR@u>p`2GB6wotK4&BP?x=kZZ;Bbc&*42hWA-`w&?;m1 zIcKA#$L(`Wz-jxOV^NjU_toO%^r^K?qgHF|GL0L&0eLz%E`h6OaAR`>mFLDNIAaz! zc=P{R+^C0*xe08n!}z#}8nQlv;>PJ1w|L3CQEMu?Uj{dR!xUuve4NrZrp;-pU#c( z$_aRGtiSRFHkP1EreVKY@1u8cKg0I|n%z6u^n8bO=3e}p5BFw44HTx&z_vv~{&tl4Dac`(%rGq8Xst})FGNa4$Vfj0+ZG9x!vOLsC*MeC zuw;vb%2}>+vW@h`%psxvsqCk9w%15s%^VUc=L4OSZlu4$91`kZj%n48I4#hx{6AvM zSq&rgSq~HO4*Z?b#jQq~NHhFTp&MI`g+PZfYWuBF#OjB=1AWmEt-MHx9tivcW6LUt z_?QC=K%I;&RjC|=uD4o8oSUffRt!d~trnPJ_^-xnVihK-9E9#@73mUGiFhCp>nWljUB8~)`O zIaX&)WEuWfFqc{7n#eT#zhT^1T{Ph{{A(~PTirC_82-ALM6K?cunqr49M-HJnn2C! zQAUL(=v~Z%R!>b>hW~w5rv# zpgv71i-cM6z)v{bS^XnE`iKH~6}bpLQnzt*rw{VMOw#n84+)C9bfgVApd*95%t zKK*x+Cg2_3YiXUV33%sLc7;>5Rq)Oi80OXpO~5+^Z1<6xfOlqLdbUPs0^Z?`-_~eN zz&pHy(;A}*c;`GEhODugfOjUOff%O=cxNc)SnG66xZW8Yv3^Fy1InbK;+^-{>&8cX z^c%f1E#mNodH*!b*4B(j{TD&2zQaq@)=W*nJ40y1EKR^WBQc>`XK4c7$$>WOY)!yB zyyek4M-%YQ5O$_>H39GJ&l43+vxqg z$HDqrqyeWmui41(XRwQ3rHOpQe+Eljt%-()pO4#Ei#5@}@LxdU8cozU{0m83tBHDs z{~8k4X(A8qqLw9^2pj&pS>o@S2pRr)EOEUif`lj|ph zjh5CrQSo;yaIB{yJ}T$o<;95e1y$6IfPYyZJm8w!dDweZ6X-WMnruRd9kfe8CqoUIw@DCYYHQj&3=Qc)_l;xALc>dF!LBl z(uziM?_%-c`)Vz*FNGw%?Smqc>;=tXxk z%&Bde8D=sH(%lnwgPa?UzA;_B+X5W~bmbaJe*OA=mV3(zZ*`Qc3t0f$l z^~&`}Vf~A3i-gK~RObY7DTp~Fd`-A`I~?(_byP7vN+R7QeG7|`K-XSY?9|19G8Zp# zGORm_Wub%-zLZ1kPEEiP93Yk!TOCn2@OS3jTI?<^CUijJu43O85Xi3hK(Vt5h5TbU zF|RJJK0wstfL@~sjPUj(9?}G6`%)4QYXY?UB-_~LuE5Nzy zy<&$C*W?~Y0Us2*t8otnnATgx)?*Z~hJ)&zVt3*DHBJ|;?ZrNdrhre2owu>+zm`+j z=UM=I0|e|Swtk|3QEid8O9YJJO#Vf&kD}Qj_7^*GINASnG5Bw#{c&@Q|9f;L>!9us zI5;gQ@q-ZQX;6`7eN}9ojJ*S`VY2nL^pGptBk@bIkIHGIC+f_mitV)Bin^8Ly@;^! zaItj@1x$xSEHmm>@ zbA;70RX{=1nnnRCuc-*Qj1AN->Z521h((=6v|uUxV3no{D2iHZDPVGE3*>bc0k3i3_K5l@ngaSq9X`P0f0NBMAXPx` zs1-wApp4b-D*`Z08P=evkD@7HSkxIv0b}5KYj~=Fp;2oV1$@Ve>39*akBO6`K8j}F z8xwW-2#-I;CGfbYI~n=ddDE;BQR@*3;Jv!msHi*ljH46BM|~7c3#LRJD+~ee#KBLC z*1He1iJs+e!ez)TO<>LQ3i^X}wkEK|$>utDwkF&WcV^UT4RL`D5#&vZ1}QFZF}ujQ zQ6H_L&UsO1Javwy(F>&3xKqvl3=3YO2~4Ten}E1f`vrTWcU};+_%u(Th=u2hU!G^v zE{yu9oGPx0I*(IDKAUf`2=Jm7%h-h1rb@gbYJEb9kFgmSiNwBi$aPU4by4EYQ702k z>A#6%_!cbyj=H=A#BG{zZM;5ebwJ_3A=dClk+_X}E{po8ixO8vo&J<~LIV6fT7WyK z?}%E{DPS|tm+le)e2B(c74=ax8~@>`vzh{4MQ^emk;do5vyq4O$AmC3@!ZA!^|%l+ z@vM$o?@+}@>=A3Fdz?xY8=^icr;VGU&H<{xRX)RdKGnvjqE-;a1AO+%dPZz4LTT&8 zsE?v4;Pt384u$;pQ1Bbo0{myw8*d4LTMzw(?51z)5@@PLF%a)*0^-p4uSTuQsq<&f zESp8=e$F7qttl{R|mUA0Q=W;8u3}G#E+uZc1qmC?)`~K9NrR%&!ax- zqQtMGP9-JY$McW`!{I9ta1T}@*0)g~MN_~}QKt-r{0qF`e@+$f zebhRY0(d`?^`i)Qi*5RA)JM@2kREf+rGQg8BJ7xZ1mJW6r=-QK+bCc%UFwawM}S}% z5?L`HMN>eXnDYb${J;hZrV8-KtQ{0EnynlV0qa<>e#}SF6woy0{6YaUi@-M*0ldEy z7DQrJWAxNOhXUjkh=4vvBhfPEqi71~5X(9mh5To7Oh#jkR)97|K)aYTngR;h3hiCt zfsvfNOJX?`O#z)^Sr<^iY4~RylPVw)bMBykEUpzgih$W&kSLGkP&CbK6SE$}W<8ow zkD@5GSIl`EoBkbbQMgZPy}HM&pO6<=z`P2nS7S~*{bD|fqJSYWr!G#m{5#p^$E6Aw z5VJZWFE9X2WepMmSA1q_c_=TSgMI_6{%u$qn;9rIB% z1)Ldk)>A-EG5AT<0{qz=+f#(Vtx*24oYkks>feVQ)vZzR%IPudW2$(R>L-Ybfkz=R zE#{+gsyH{6)d1(X{_b??oNC|uSF&ao2tgG+F)XYLV~vtkoE3ArVDG>Z8aUgvC$O6{ z?A%xml~cu~v8)TJq88nAS(1upI5S+4q~acqqAOEX%#S&DQpG0v=3-G%%&BQnEQiY3 z0cOUm_1LV(s??)0>Rl3Ze#EAq&q!I0f^4>vq@0(J+w>V}sz&sPUgoE!| z@m?ioq?==Y_lT?i6xL=W~;?|gTAyuUF__Rz^bfynh z#(Y#x6%WQ7o>%#AU@u&gq+%%ddMHW7l{`8;oT_3~%-Tg2d>+ucUw1Q1Ue>ypkIH#Q z@Knr+M4;mBR^XqBRiCGPOyXHh;5_9E5}P!E_Qh)ci5RZ$LPgWY$lDlmPdd(EpL;&$ zqjJ__OU#*16&37NTeZo1WgXJ};#q179 zyc6?LIaPcVbB=-u{yDVc6DG>ayaeM1P)OxA=BEe2`s12 zW5qw!1QtoB(fgli0>k6S&LBS51Wbb6@5ii>uqJRrN927dc8_g_#1}CiYec)hi8(ac z|2QjmKnrk>L0`tK|(&D%d`3nhC6SxkU-Wo)jCU9ozC*jcq&Jyd9@M;2QrcFs$n!t6)LK5kk zz;(!F^hbs!aALWNgsll&hkS&DqX}Gxe1=3VP2f7@Yb1P{z;(#?NMvdP*CBV2$kqgw zPZm3ZUlX{7=qC}-1g;_0Cs9We=sV3x)YSy~P6rYpO`vCVB9W&F^o&Q222o!VrWzwZ z#;gfwqQFG9@lP^FwzC`Nm-yJi>0aWaE=ufI;+#Q= zUXJ@?MIsjPG^tmKbrl8FZGgN!B497=8(89_XbKos;;f>8t2s{$7Xh-`7+PX&rGPWx zb?bN$z*iDjrmHEuGeS6%_!tQl`E*TN~(Wi<5U0EIhsHZ^%6~BvRVK$tjjckE;)#U_zF#+OV;I#u}Bjz8fTGH(f+L2%j_G| zOWd=_7mh*VZzVp~nZCNd#0le?kG~J5dh5n&U$M2WEwPS9Uf?}k%dnP+YqB^CE=6;T zfIHFL6c8;1e|NP2|J8KpN=?ut)4C1qPl+Ww)GZf@y>gMbr^H8HG-+*#vw;$yWAi;M z0{AO!IoBuav_wlue4xbINr^+*uUCu2HC>Q+6dgh&K3U>qx4@OA?mdR$r(!K2!^lPS zTU-#+9U@&xe7wYpqA(^62-zSKuk<4ELWz&MXyfJ*XCw-_HoktOja#(}*T$DitcxkJ z9c%rnNaXt*tT#)1)J2K!mpE&&>Du_A7NBkXB-O@uO04%NkweCMPb41VFxXk*qb?pb z_LVqKwS(>$=-9%?trA~JY8vhwIBBQi=1#~V6M-yJF{S)Gyam-=WPjmRs_`g@fT^-Ck4 zf>ysLPN&2Mn!tPjiFHezCn)g%PQt8^t1U1)4T=2H9O|OPW~Es_RY`221)zxrJB%sQjTzv5ucY-D`uK3z0>qJdpT-70Qk|r>& z-sJJ)6iuKzwq}VDn!vbvJ_E!kOp7btdEoPUXVs(o*+uo6fGh zq|`_AILj|Bb?%`NIJdyBN~P`!kjJ(wIqH@P!ISZMRIywWRAE{-lv-P;;_+6QfD7kc(@W-B?8oyL({se)XKp*WZ+q z`*jj8X##fNNaAHp!0z8jyrKzS!K8;@)dcK*9kYS;nkHcPot!2%YXWvZj3&0WXu`Go znNsUQm=t)Ic5f29>&B3Hz0}7V(e8Ikolj_Y7LVWCv;f$BF5UaSCSdn0n)!hyVE1V) zL42qQ*gc$Wwp|nG0dU@%rIxn{Mtn>o-WDVN#$NhysgLH-h|fx$At>Zu$V0&%EdWML zC_>LApEZF7Yr>B9 zizZ+a?Ea?IDuPLYbMlaPK2?J~n_Sa=c3uyuH_dL2ctO?kC0qxGy1niznyX$EJc8_G6)z^gE z(Q3!7Nsu47j7H>&5q!U@)iCa(c{HMF+}S`Q7PB)n*8*U~^l}g_Gyx-evZJ-s1dJHN zU0P|v?P!s>wUas*Q)hwbJP<&lP25LosIxfk%)}|He=g5aVp;%nHa-SKi6)?vPmf!r znt;xY86e`CK*hhy29eMN8mv1Hzh#<0gPm6oL`O}a!KScp9;FGGgpO7i$FEDUJDiEU zBC&fhm34~ySR>lqE$+016I{D{XaU;p3QcIcdul@4-AfbN?%tZvcK6YQw!5z;wB7wQ z;o99fj*H>2yD{zVB6ij!H11qQyI1ne?szQ#c7MZ#)(M(`-J5HHI8hUB zHyRknHBP8lfPdCtQPDvygW^6ar;0IgXD3yhRfa<2v;e4BhU{i2Ep-0?v&) zD=451ua3{r7Qmz>bwOO93Do*=_K=G-f!5l^9Gg~UhWP91nHa2q@0dRJTE{kljz6VIV8N_;7v)dhw8r{ef%y&?j5+l5lG zSxa;)`CQyNjS`n~!hJy`PT@jzOFW0VsCHf4IuD!mXlOmkrkZW>td-bw)qIeo<`j;v z?LuH&P{P}BXEO>1Hg`hayP{?X<_hcMcn)P#;%D)!LzJil?9l?y$CNAfr5e67?li*b zMBrNCzb4UnuB*?&lSr;&o#zmQ5blSCHf82VBhW2A^zm;C_CCC1+aUZRt zP2PkP2j$w7o~S-9E1NPjp>47?p>3)qgtp123y4jbI_=tIB&?I6F3^lUGcDmBb6c`< zSqUGlrA@(vGaH5cJ21SguomEs$Jz<&777?Z0l6aJa0rQd2_HpMK;wk7o&vhjjZG3& zw|TH-8YZldDd0K$vl=Dbdp5r0p}JYZN6{3}HsKtifQ9Vtg{c;_OjwPuxCwkqx3(4w zzUJsGO86+60y-wLu0kRIOPJlQP6-)YnAgtXa6MWRaO+JxKzG&z2FpsW63R7!rmh%* zD{x&j0lyCHj+1SjhCbA)G~qlm4M^lr7uCiRR(%wz$GX;|Y^pf{T?(XsP!0;8 zD9)3E!Vt7SrK-H+#CfAzpx{XfA4O5X7_>hH+(6aiQoTO{?N0&yY4Ru$@Jc--PDlHT zfN5xd3RumKH6vBPB(y&TgmC6&O%Vad@gO$~?Jol6p#3S}4E(b$NUg$bv_B@3z#|<0 z=Zb*OIaSX^`-_0f63$U5OZX_70yZa{=P2Mr9#&tk7T|xDnzm}f?cy&bti6<&;Hu^ok@z)R^38;gx+w93 zgkxdF>+i=Ie!CXnn)GhMYK^?WVtQ(u2;j?&t&bBvil%_i6VBxna3_7cR||lb4zdgH z(*!2evpIOb)C86fUo`;nl_t=3=^QEl&_tSY?5>3MAdToupM5Gu^rn-(N%&|Ujrbwq zOhiOEm7J#;Ugar?20!FOnxyR3%fDxDHgZM=gG@>PlUp3(x@omD2L4M#8cGrVq z#A41fhZ8=UMBk2p%o}+nsCj}>`^{Vz=&rfATl)pBc`%B zvNYiukyd7{rx8my$9l`$gNx5ZBB#tp^Jqk{%;AsH{!SbQVJ!fj2-5p`nxGK@5cM?S z{wxtFvl^5`#g}c7S4UJ#Vm%v_`KX*Knv^+)m*R>M%1-~y@jm4_=oDkZU`Dib#ik3M|V5q+v zC6;Ibu<9QjL6m9&R`tYawBnk8RgF0&5}JTj*A{>%(*&%VNEsb9;ab(c%<2V&fvwPQ zbr7pwVQ=bG=A*r|s#}?J39TB%xvYm40ITZom|md?SjF3xte%>1o1=4?wTddooCauHe{WWNuoeIn-_htHnt+P_6f;y4sQ5CjjgQj=Dt;3ye!M17 z@fnnHf+pOG_baoyKw)5Z6XYE$R=vs&dt#Z7_R^}6WzH$IY90Ij7%c#!5p(6qW!5|j zc$>~TRRk<=j>Nb!A4OBZlrra53aHIFVVVfw5uy&>iFjt2^&BOr%t>XTcbM4fpyaGF z-v^YS9!Mq4=XQ<5CZBPvu#19xu|kI+?}si9si!(RM%CjY(U5wmc{g##Aa4oo6jD!m%yCN{9po*$#{_v-ZRa5G zge?#9?$s_K^~lHluKcbc^{B@Ku5I0eygjv7kav*w38|+(UUsGR4f3YYej)Yf#|N&Z z{X^=Jj}Ki*#|C)|=fIG9?&Ax0uR%fHggH3KJ1K{R)UzLlqq()<*`c9>jo@b^rs_O0 z$Xg{x1$n>Y=+I&2G<0*ugla{Q%8%tP#PMoukT*0=4D!aoNkNXL$wA)9Hzmm1@ur5x za|Dic_na2GrZH0EV#<%xgS_8vW{`KB%?k4Fv9p4_!RzcGYdJe~3(G$0?s-mVB~y>N zd!8G5h^h6lT>h>xCm4Y}3q$j%>BX38(JMnQvBXPm`KyETQR14=Tjbu0sTR97$Qzih z3-WfLC83X*^SxX8??K+-b3pxpb&Q55#+rScZKpd9->lpaf1r3zm_Nqt@Z>T6i8Ze@_ja(Kdh!x1G{02&?H5m&zx4d( z3G=rW!yD%BA*MIXUp3OaVg5+q@rHTL-RlkWs<-70^FnmGH_Yq08Qw52liJ=eFH}0- zFs~if@`iaS&gTvD%2uW~uNxJf5?2k8aH*XX7{My|!&l~0$cRg>IC%N^# zd8boAPC{AGz#HaiWH<~Eo4f8Ch90CAcym{C25PM2O zS%z;^fM-A;BwLiLg!-n{#nJi{$ifx0kxW+L}`v|=x4!#;DN4R8_6W#&A$>^yIt z!*%NXMD77J(E@LnClObB^Vrj@t6Z}ed&4|4xW=2ei|nng)@!|a|6uaAMDC~Pde?cw zT>Y>1hPh;4;|+6Jz1Evo$ucjvf*$gQxmJGIoA(W-IqPkgUFQvRz59qa?-d?!cDU@L z-Y^%jk9osfMy~gUxsZF@8|G5#32&IooekbF*B2YTVII(*^oDuReaai=QSNDP-aC|b zdYN+3Gv2%%OpY&8etg!O_a&1P%5qn6*m%P{uwjBzPo~X=*VL0~j~MAZ3|S;p&NVtG z%SfNc91^~x(HpF@%RD@a;pIzH(2p}7g4hfbwi@ZJvOh#A`z(wl!)^k~w6~#Gr`hM? zNRGhDyd}#mn$bGDYabNagP~~H%h2ad`z8;IGJb%^&PBiX+F|hNcAZw(%f1}7uym_Q!OA;fccs_6eSC6wQ4z8l#7cwBgxCw=vnX`yt~ojM^Ogi`JMK>=R*Pu3aBXi#qn@;Op8e@IPoTLvF}^5C6mV zBQPk>ei8rc+0&q)zWrqhykp-5k2SQP!T)^w5G-kA=b3PUosYrR*lv&i1@=j}F5kpv zgt?~nThP+Xeu2vr`&8`J!oCjwTiV;OZ!3E*{Ecw@2W6uRkaw19YbN%k{zQ=M9{$X*L`O}js~)9mT^@3FVn zXIuI5*;dO7R9jsL%D&aJ0J}A;k4E&^%l&En;TJO#8F%Ee{fvBGxU}!gWz(7YZ=&k< zUAb%!yr<=n9Hj2{Y(^@bJ2v*(4_J$^QLr6m+p8PWB0ld>@FXg1ua&fE6bzw;hjqSL za1|QVenjV+1q;}X9@F`01x0YD{kTqh3Wj4?*c)_t4}uP$fY-h^=OJis`b#--@5^Qj zHSNmnCo^)v8=g~8alC<$CZ@Aw#_Ono`0thMy(y%-g!WKea4%8~LW^0) zW873E)TIqlJ=|2&5Uvy$_Fyxx1tnXC?xV%S-MqF&OTMD+QJB?YBmccbYa4mLhj-G+ zHuCmo&7M`8td=Uj2ODnre_#uRzGfk^jl6H^LbajIEyVU|5keB#*_6zzM&3$Yk~Oa` ziJSruO3`sCIW0~?64_5t2D2J@JL!@aR+YS%TUX;BvZ*v79p@u-F;o*zir z>I3u+^YQ$Z*v79;_%!m;^vsv>?@4^sDgy5~dH~yvyem*3eG@iYwJ67aPd8=}cfZUv z$lH&k-eU)g{Tf8EtwHi`vDWKbgV_=K8m0M4-Zn90nR{xxxov+zCCwQbS;$q91k9zE z4aV_d!t`mR6I@%M1FKIV|FVUK#}7!vdpy*9lMwskI!hv*)R4o{vlDygi(^;4ynA10EdMc8G`&x7@uJJ zvjfMT!LiA#m(jmDbNUq_QQu9JPMtW>FdJm_XP1jBnV4`XGrkcA6tj6oUK{L_7&m>o zVRp~Rp?o-(1=6Xek@s0_maIUVnO~;Yrxed1@bO_>dVQTboG`l^DY{p z%-fXSgXYDjvz1>=&wd1D;}_OOVzVUDDQ1f#ZbTO|Ur%>CX$eo#%=6RTDyI+CGS5%1 zsIKz)>7!ZYxS#dE$lWtu$!5J$55cUN_XLb-&iSU9~NBueDZf)wb@nTCKFT)mpW-{eQpj`#opQ1a6;u@AKUM|9_sm z`J8t-@BaSY^_+n;51fPqIc;zlA7FGFR290^BgC`wRBu< z94EtRI-YZAas(V75iX$>p5^2-aG;)DRX`J1{pX3Aypf9wFR>o(xE1v zb@m}=?v@%jF3QCZO%?HLU*@K=sKCVUT^PR!Wm7rGK3#~s3_=~woJGBX{N#TMp}?eq z@Lv)1g0o;X9d4#V)uPoo3pW~h6NunBmexe`9RHi=4#J6G1is*CSS`Ra^Z6WQR3`Ua zl(L=v#Nbl0E6R}RW?9axj=r*vI&;erT;PWxuP}RI7`XQ5%iU!DFf@mm!yf|7K-pwI z5i*5&9SkmqI<%r154{^QO{v1v=3iUQ>#%(d>TuR`v?^o-|C=m%KQwp@f?03?to{Z! zUqUS?fu;n-Gz2Pkh#q44<1?X|3e$t2l(P_67&`L5$)Vqd1}&k7%-MNxH5aNDS-n@z zu7X*>;s4RR`zSQ%G(4AJ&N{Vg@Xw#6kXKF?*>^phAWH+YDg#SwzvD!i{mky~$gaYP z&eG#gdPcPj=oq--)2Kyrx4=!{x?Gkwz&>#8M=RVczb;h4EN?~hQ&5K)IdWYnPC2s! z2HT))Iqb6Ka6JsJhO&Lb4WV&tne~)WXcbTwA!h@3g^CtD2BRn7@CQ(3G>!iVCLch@ zuV^i#bRCW-g80S`p13<4ehQIV&c>O2Q9c3Mr&ZZ+PFZb@Rw!-$K^7GEdt_TrJE_og$`q; z?11}iQ1hluhyC%P!#G%jIQVH5usw7bhi!qh&7BjJJ8;g`1k}7quuSB_m}kOx;0QO2 zL@3HIo`B;YK-rA14@H^r__+kEI^n>&c&TG!o0aC0G4v;?-S zSQW6bm8*6%j9fudf!gc}1X{a-r4()g4*w75-O-`&&Geep|5kW=GrgVy8@7UPcwX0) z!H6=Wwpw=bv$hoa?Y4fK!P4B;gW&D^K~JW{;UIABZ_y5H2l0Neoca8H1oQ}$&FA-n zG3N7oFnAlvX6bK(M$q&_PgMYQI0qM|yD|Tn{=m>sI02s*90;p};buD2g5l6ac>`th zb0XaunQCOkfuZope2TJSDIB#z8ELA_GYK(b7`ccC`QJP^DHMK)4>Gs9@X*nG&~5a{ z5%XY_aimYr!Kp2oC?mieebY0lqo-C1{~nXl!11{p+YOt*wP$7B96LT}L;`<~@l+_A zW5)-LNO%qgkJHc$ku89-*|@`I;}I~(KsA~%kZaHFg5TF6$+PC96Qy)1BdFnsTk$OyLNXYu^gP*#ML@WpI1AcAS*2HAMG-!TU?Pw@l6Pp93Cf*N& zyXbPlcs#x;U}h|PVDLK{zB&ztM_R)`fAmH$ET3El!)#zQqY}J$dBtb*p+Cbq;=4G* zp(@smf#I2fp{JvG8ex!tvbFsi0oC>fTieff^~v%R;VAGeSDz}M!V&w;uD;a@_XR;C z+`Hj+Gt^>s*B$K$Wup@)!7ue7ldp#P6;NdxU{~?zVen;ma6D%#Ps8+KsEWVPa71uC z#os}Y90x#|YPJW@2OR#VJP8~S99j;~O*Kowq#4Rovvs&xOD9QI&XZXe%zsnw4+;)4 zPn-w`JKQHO#?3eR1Zol6HQUqxXEclT%)pd$7z*1pzpH*Toh^)D?pBK%NJ2U~Coti= za8yQ3JO;bR;OY_Mp=o<(!D-Op{}Mj*3eL@~fuC%nFT>S~P{!T)#!LP;aYZjT#dY@~ z+*)TZt8G>vGIp-jPfy!X`RXp6p;ZGS&%&>=_ zb^IF240}exb)hZ@QaI zE`;l#Gn=lF$)#{@GI=P7%JSNw^O=_tL|n;Gm(MZmMWvQnd?C zuY)qFVxtdYW7wwZb2nA|t%ir8Y^rE&QuPXqeg11bP)#f=D@87ZyMV+0CJ&YdhvK&$t?Np-tnge%Ps1bZ z6t0E6uVYA=j^W}~b_{`8re6s57C6ynR2Gi=?lsO+=sKL}y)dH}Z|8f_V7*8hFKXmP zz=__3SX}}y{%o8tL9bSO2aMd&Bz(jMWE1wGAm6n_IQP*g(la2}8KGZ5XS5kEY-cne zFoUDZMMzgY)M2+EN^rl3E7M&t*Z^faqk* zILJboIqx@c^KVcsob#TF2h4o;1(-Ys1&L?K=WwwHs*E-%#&O9- zxTDNm1UD2ARZg0gG_qQZVUj+BY9yXZFT8M%{A3|6$igT#7YKLYGOdz|O`E#3KH4tpRJhBNjXf zan|&Bn z(Y&I}Bh%n7RMBBYnb;H*FjUd}qSj#$HB; zR7DH$!xuvX2Ne%13KfqlZW}c;Fa!?-Cp$$&hr~2QF*RP{H~BW(Dt)_G!Dx> zG#n3wb6$@?NIvbzL5LLn9_9Cp2BVD)5{55w=OV+8?LdGtdvGEh>4AQHL7;E;>^}^7 zW>SRQWr`-q6O-BW{(!+K2zpbB@^ubW`sI3}-*ql2lScLNb+X?bMyI(F#ZLW*z|=7e zdTQ82cN+D!B&PcdAUGQRxZhwr%JAT7XQ4`)_J@=qV4H_i$6zb7uy*v7b;k3VVPB>P zM?F-BI#yN`XamaSsVPMIf@Mh8m&Rdo8#(v10IDgZ&3UKc*HcDcTnC3${@_YY{#7F! z#ekVs<9E?G%(|K7j|-MP{lTFbL+e!!EXVUa^xU$*f-$bY%$>Zn9p(>H@tv1vhPck} z>xGTW;rj<7!_t9=>%#PMdC`jSGLsIhctqT^*V?p4ke;Y}%L1!|2B%+X9xDRq17t>Z z?#TpwVe6~+f@vFN1A*||%Z#2j@NquU=+6hGY7sL(GR$QDVwN7CNP7O{k^uS4pdsSR z6fv(Rv@ohH_Y^}yCufs%dEJMS?6>!pYGtb@tpKL zlI(pDGLfIDX=_2S*WY)PVDZ270Zq^3kPUwc!^XG@QCWij=CT_RDcpyg{{QAn65Z0+ z=eEE^zK;jN09|2-lb0pXn#-4)4KT=0pWHZ8aD!k7*U=JROl*1oOP^TiRR7W^JHuoM z`#C*M!{mzTULe8Xa2T@`|Amz=C!8SNQlaAGzqtaQVLzwaIo3HSGS&;A&_s`c_V50hk)jHkj{|>xk_gu^?PWx$JfwVR&JjrHR?*wvBL~NP9_h zBls`F4w=cp0q~%}+2&lzvND&wp|A-$5ucZw(Cuwn3e)O7ZlN`oPin+ruSGG6cUh5^BF=)cDdF9P zP$*quH`Kn92nz|tC4L{4?4l3nLm~adZYcVYOFs;JS0V0Exe59MIqml@ZM?h8S`fRT z=-uA+0v7V&f0`t$73gBn%*3<6t8`CZ4}~1Te{%&*K&7}3I9@S04h^P2?bWuOAg#)v zeC}X?`6uB zXJ@r>o9l9d#*|Xm7xMz+%*Hy`nC#m4cZ~-ZcLBQY0cq;XKi7&}Wvz(w(2dy2#=Bdg z@C?EA?|s)owp~;-!Yq>Kioxidt!@1i=NZTe&_&97n5`7 zD?L^vJlq6T;Pm#pw15jhx0~Fg4$phn^SB!VcW8@T(WZC4KF2rC52HpZcvBm_fVSKEiIiUe3^cq7`K1nbXg&%X&Q~4>S zW2(HAx`s^Y&ORw+z+Bw*M>J@nQ(;W8wCY_cm@tF)5m8#L+?Q2>IW=O}i2X%E$5eR{ zbq)6s(EzJW6-r24@Mcn3D;Kp|``Xiwb{qewJdrMza_7?xm#TrG&B~XY3 z9oN}g{5KbWY?ik2ZXbTog}vyGUce{1V?U1DmB0pjyA?Rq-d+S;VsG)^T>OFC;kc6* z&A62p)}H0a%;iN7=^Ok%6<{vmmY~Nr7wP?F)`Garv%t+>*Fc!S2Vw}6^?`Rx6fB5p z&jL5*a-&1d|IUX#CBR@f`mo{C+x)8)T9hime5JF@F5dN83;geM(K6^W#GoWaPW1s|`428s)J$Zn$VC+t(dh&tCItO}EwZOQi zqv6iLY3~GT2R7i}$xhAmX*gdv%yVZOxQ&OuYr%sih(hNpu7P{*gQf;DE`4qAWm>m( zA|2K*x*LGn!%n{6KXWrZTge%_LL|X&Loe6>YK`5o#*VSGZmk|#dj;q}l{p$KL*F>_ zC>c4y0DDBFgC)AR;a*9h6Z1$tZVFM~W^E4a;{768I7u#RRcZ&@o zM+5G~ux3Hcg>wCK?dXiLEQA^WMYpcZU|gvtK-EFHR|#%to`hl?~$D^UfLQRI60yP7w@5MCHoqI8D{`4_k zv}fE(p(aAnuW3+z|NbY>RO4Cqx)nEfLEQtj8_It%ag8{(ej(GO}M6vJg+GoDN{ z)9aRpKYnf*(!c-Cvv6jvO8jTNU>l}#uUg!=Y7y?6q0&(9^*nDNP~5?{-~2^reg*Y8 zR9|~O!`TE?1(bK;p7M|L0oR`72zNBpc&JjSiBJ#*-u2&o#(jX3vB#k}pncBg&mP>H zQ7bZ%14H+s`5&PE4D}V%KcHN9B*&utpaw#5usIxRJd}I=PoH(4n*~2OIHltF&%J0q z8;a+u<4_Gyt~-*W(KOUjD2^$Qf?5aVUjNf)-RDTQ30|y!yjVAR4Y2U!O0V>{^)auI z-fbVQyLmF-EjEaL`E@t8Swl`0s&_E(x8gyVY??_YN+VEKR^HuSzOH9$c~5sod3UyB zeTP%NVauk@^7gLI?d4@%TRPgi%6m4ncXyU|cW&EnOWO z+Ba_QDPP~wk!|nZR353wR%I(IDkIrQ1r2AyaOUPMn>%NAwy)VZGg47jHIvq5u+Fn8 z-?+J>Yunn+@=fg>8#Zq4{Qo){Jv(~*QCPpBJlef>+s4gXVq3a9XL@$BiOrEz z_m-nOJ9>M{Gh5rckE!3bIopb~tWR}q>&d30vzlt$+(u&mZ+$Os-@36JrHen7>>8AC z$EKc*J>~Jv<2H75mZuZViA*$8-e`0E|Mkdh>ez-V*7biM?*DNJsQbO`n>#vtAZplp z$~q{evuiuowQuX{&Gzot+SyaKf!z`s&DxEdd!fO22`w($v1QYyEt|6_D43yfrVp)W z6{%~078~X$vTS$f`i(uko!!~3-CKH5u{Lhm3`_LOv|Qi4W!u&)UJ$fKCV2U_pBtME z?9fn^dpkGfd_~^NoqXy*Ge3sWlzwezSNjgD#V;A*(~A@;q4R=xwQ5*6P&hOkE({fw zhNl&d2nRylxCsp`Jz!#Z+~jaz5;WUO4}gmUhYcGM9#@EG3Mazppaa5zslojqd~!a1 zLEB+tM~3_1razoTz%ldi#AMHCCX6PP!Dtdf9#$GG$n)Wx{%)K?lS|5E_Wc7lzsc;fl}!rQzcF;R@z^Ili7_ zQXU#u79MEsQsELZ5-!;v4kG1@P&f=2_a=vsjL-%|GW1)Pa%d3BWB6DTC8P`a+P}<{ z<-m&YDEL~&(boc9kDmKIjPQ<#2sQeb}QS{jcq*;^RJZxHx%|L+4}H!M7{ zFm%f)cp~(=QyQL#dt`*U?}vNF3WcF1^K8}}9v)SStTE+@FK#uWji40aU@d+T7F-5=$@T{#W4Fd%~(c-^9n-j#*>g}#Z3F*5WgQ_Dh^pR#CJxPf^V`ULf{ zA#@R|O=w3Me*H{l#l{Tnhk5vO2M6|t1;P_Tf8U8pG%_5;vr~}!p??NT!v~}N!>lCq zpGbFjh!cTo@ZRJTy5FKD02j0zW@pHYq$fG@0fT>GMSxorTNr*zoXR z_&IQ5c<=<;v3TJ9HddA*NQL|=@(iOsEHo4)H7N8Al{WMB)t#og+z~>}s({@#*0Uj~ z2&SRDzcVmwbQ6rPF_i(0{_t?Pg%#p;TOrCYP)B?MZU+CgfZ+@u7Ag&l9LCN7)e-qL z1JyndTFNY&Q5LQ&oXX@+2z`^W8X2BZh!Dfk(ALuMjL?u$d)F@nVK*hT)yk40I27Z1R%0M<`1eqbEW|ouure5(1G2EF zELfPA%hy51BhwfIlWS{JV(6z_2?jJaO7_ZQ{z^GwJ z+(Q%%=%xxoPalugTo_u$YBrtS?cw2Zq4(H_j4<~9jv9@g{I_iMv%|%q>$cI;_XeQl zhOWmwhXO4A%EARm8orlUjE;H6gmCes@cswGw!&r&haYTj{RC|1jA$2(K?cr$|kkk7`NEgF)*)Ihdqggh{`o;3*lr)k+s%Oc@rg`v|R zeNn?Pj)PpW11;m2k}ErGOp~&_BFr)3KqJpemLr$G%`Va3aDRG&X}D;6@p+-|?IRBt zp|0G_dKTKjY@Lca0pl;X86kX%ab&J_ zqaC5d&q5V-E5bZDIwJIyFA^Lhu**h+-#E{BxWEt1ojA@d-;R-#s(zqjK;lUYB5%WzcnImqRiR5BThr7NALmRL(Hon7P9 zXHwZjI-SiVVy!LdY&wxlL^FwOeY7!|h&%B_A{A?E^<1@O>av-}m5FT2(nQ)b%_N#L zc($=Qn`w>KH6|NZMq3;4>x`Ypb#CtUTs1Z?jV2r8*`}6w!im={Of);0L^6}E@LViP zB^EL=o{izSlDwq!J&jkPq_H!gG^haOqn($kUY-Lf@< z$ZYG0b#=CP=Ve?aGp;_FMA5dctdAwrP9`2(jEd$Ym&P;jGgsf1HP$y~qbXCg2&viT zLoAiR_9HVJ1?eDfm$ju5&5?@SZ6tSFnY*pZ-B#yrYnoCR929o6wbgj$ENev; zddc<5B9?54EzU+`t&K|)o^33-7=@WlERQ7;ab!}aB^7IG&E#^?tw!sNA^nXzbdJu(K>-`2ubVv6%sL{Qqq--i<4bkR>h;M5&-D(zmSkJa>?d)#v#hPMv)0VZJ z*`7}OgxjjB*s2z$T3JI8wrxEXYCWj2SaMs_-f>KJQ|G2F-8-CkYpi)?n)NEls_vLt z9NW;@ag41Ks3J_IX?v{c?rK-Iqqn;YkC7PqqGT)Q2 zbcB`A+*njPZaHOqe#IM?TB*b68rkDUx2-vzNY^J@mZ1nLQ3Mqz0>b{U$9+p%B*`3c z+iHc=gq(`zT5PVB<{D|Pjp9uwHS$@eKG;%o&1NIH$bQBSV!yH8qz5$*H3#*_jig(Q z=pfpXxxT6)nvO4vrW4uL#-;>XvEzzizo@UQM6Hge>aB3{+e8lS(~H2s#FnXTiM2*m zH{DpoS~G3gcw=;-=^L}Lwlo&PbFp!YD4I+sqVW}3x0sl&#KLq13JUETJ&Y~-o^5Nk z^mN#kh>Fp(aZOjJ>1?Xd*_il3C|X9uO0i0;7Hh;=;-TVfagLXfxg;p|*-T4YI_7J2 z$!Jpwbt}C*j+TZZF!I0_ked&thUfPk$v7let}VLd1@Xh`REG`?BEOQZkp4!DK$^V_ zMkVjeYQ5TBs#X?Z1d!cu0tHXUwk~vzxnx+`;0Du@N~FzrL?aItcBL|}Qkhh#%&9!o z^Cg-}rCXLa;{9X}WhkBFiDYzz8IWYMO^wN9Bf6HB=6J?QWtw8nx{j`6vTHXU=cHR> z(PWeDYbfGOl}7O*zLkiu(-31a-RzRsHob9EDw$|PrD5yUu&gc_ZC(s9lR)1jX|XKc ziVQO2fCzK1ZZYLCLaJnkyA^w7>wEG#kET>xwyrIc%_O7f+R}*_A^>C(>7|KyjU5?f zR%ERBLls_{jpPKJ=@m^$Wz%iV&FtQKI*vg)G5BJ0$$zlgNh7!G9gI8bGd2tMb~M{d zovABsIhk=`rWIN0*~cs691ogtDJ79QSELnrpLF8QO=vr|22s#?d6vjV>oQ(9=v4p= zXEENiT@i*b-Mx4e!vf|;mIa*Fo(T5ZxFr(b*wfBtM*-U0nslOVtu1lnSuTDoHB_z) z3d~9+{Gb*(XU5HqOro^`{SGocfpGEdw34q6;Et~eTDkL^lKx58qg6hk9(#gKaw zao8F4?U$KKjG0ZZZyPG>H7foZQ}bB|lS`3y_BfTWf^*b<qV0Ypkq7*XVZ< znGF|y@B3KRI1oq~$}40KXB6>He~Uw{RF{vg(Tri#v`wO7ElsJGX2?mKn21;2`?5u^ zh|xqf#6&XHlFIeRZr+(3%9xp`TPHpLSoCb-EN0Kpj5V91X2gR?E`>DpHFtCiiG|Um z*U;nWC^H#0g!Iy6POSR|>-8v{q>2S?lzGCjZVQ6sY{Lv^%~a6VSd1+Ztp*9#PE(Gi zF}p*@ZJT>GuHW3bwiH9jZkuSFpldTjs=5`%B-aX1Us`Nmf_b^=Q_>L( z*rRbfGi9kEVsvHZxJG_9VUC4ZW9|kkGdf)8buZ{>F|0ubF$t(=92%?VsjM-T-S!e@ z>PvSa!3WE$Q4C-Yug{TLz^R_eLaMc_HPV_(dB}*0n5m;FM7{ z(#d3i=}mJB5w>;Lx1=Gf-1coJ-k!H^{lSm`t;(DEQ8>bDHu!BlNV@VVu4x3s4(12B z(r~jDk5E3N`+yAN)R#>>(-w=d^7v@e4k?@S5VTknZnPp%4${>{i)Gi7k+V|L_Y zWgrGGtl@4fa}qipjpa=H$VD?wj4o`gYHO}Xa^No-9x@72dMRo}g_(dv(bF_!Dr|Mi zBx7+*9VA5R(^beBwyH*m4KJ9+#&mr&i{Vfq#a2Y03>+xV*x6A{wq=$|tVYq!X>adQ3Tkf;FpWNMjsrFT%l%UvO4d_m#WVedX>P zxLDZSRvMc#r<5n6$|9va6IC(0vbuCycPCbCdOD|<&fL_ob=&-oE#1AH+h=a7s)9l9 zhHabHfa|)pwD-=$fvWisA8Tm&&&0Suknu?$|INC#;T}J#$kTySRhb z_G~?P-PY2X>q}?0RF=-fux5S-A~18^rp}(8_Vt}JyE-?o@7*xJ0!CIk&7^dKZr!%c z=IqJL9(x9*2WD&Ad)qy|$$e$9(C z@;}sgYKH<`xw8+>amPdK*UiMX(sn2{D4O2Rp4^&VBidViePgVV{Zb|s_0O6hfxIa{ z%h}8TS&b7;1J|NZ))g2uyUnV)k|Um0(@-FAn^?I#yPDkXp}E^R@WY*FU;<@URop7) zN-9i(5?XQf$q9-_)>Bu^VHktuRi6Wm(Q_`W%=e8nn4DazH&a5hYST9YQFVr{d9I-s5rVFnfIa#@;NXGz3Eg#i;?WJ2K=cs?BI0y|zm+qhxoD7qS|I>)fK3 zmU}YhG*pbMC=0Q?;wEHCTcRz2d1G`bx*smi_^KMD1HMKKL1x4RvYm5X->NUX!Qv8D zCrs^&rK7%*aYw>fw8VTp8pEQ38QiVe*t@B{2P<(~I<{mHnJrnYCfL07_1Ex7LPo6j zR;*!VyMC@pxC>5sm7)oy!3l>=T0K_b`lQw_v>{QI5PqC;vJ#_AHe-F!bLy5b7HBZD z^Ger0e#s!KIa$WKgZG$eOI*!Eij$4Eh-ne-}|z(YK4J zgm|Ep7O|#ymeUjV=p2VS8GspFmyFjt80c`_Ra+uRB|Ajq zH(G~T_d!@@#VD^@`g&K4a2p!Yt!L}onz5!2am7ifol3beNH5PDuein>QerWp4fVra zrE{%VXOQc@eG%8jECaYg)HU>Ksyo)=C>UoZwWos#5~`T%*feKUST4##Bx6MztN7Wy z=Wee1)|QrRQ?z-7<{BAOxcNP0#4M^(dbkh8uqbM3ynpM58w+Nq3YB0RI7wT6}Cx%SXn%!alg!MyBLeJz$pjZ2~>WLtGZx5 z+0@eP&Gb+oQN=2`yJ$O#4%sf)Xo5 zj6smzh)r)Kw~NC?Fw`QhW81x}3fG4@u7T@CMU`t(?cTT>UKO)klSAE`+3w98GxbJG zqS(lR<77N=x*C%jz*+^ov5l9A#3~c{kf)I&C zZRWc^vZ|V1g1KF3bGs6qZ8~3UPz+_UA+3dCWmN>y&F&v^K*mjnMo1|cxj7thb2u^^ zm6nqZ|8js&Amz;>auaTED-L^PnH4QDtkEG!Zoh>^e(yGtyRFRK;?srd<04pmb#HT{ zM2G;-G&f*GWIfY4thSUl&1Mi{SMIP**Ve?jBQvhbW?WVM|HX;-c;}jJ>y@imEwI^J z>1I8K+cK#_-xR|@Nn+ezZ_E%?tK*O|KCzKEDyJy*>RPT!v;SX_fE+WEb##*Myfwm2 zY~+etncU$DHp~|`bDiF^*~c)*#3{qkHJ7WB*p)XG)XredD54?4%~P)&kYu+=kZA8V zSH9S*;8JUc-DGeVQF6tLy$kQDT=7=U$?x=e@?oz8r5Cp4r6*+%fS?iDnU$UPvno{E zs!*MiSnLv&_mr}}ML+ayeB@Bb=6$>jWM2uwOASUwV;_j3dS6m$7Iq8mo`)N6=Bg2t znPrWwu?9DIZo`<929=O*ZlA{Sk#^g;lWg~8eFJswgSy#P#eEO1(dJBY*oR~>2wiEXW@LY_5pe=!$?SmN~<0h<{}*Oue6JzG1`&2H(=9=D~d7gOYYZ1vUH zyskli+QO9i*MV@*gDV%dZ1Xmvc}~NQWbH<}8OfWyaJ!MVzT3Rnk;@gV{=3nw&WW4q zh^?>c%{&*m45_X*gH~S^t~SGsO0+-Ed2WRWi`4FD&ukI-N39W_EkHNB+0+7d4(OXO zm^8a4_aTl3=PmSq?jnh5pr za&f|ptV|D-Xl`j+*kEStkk1^X+l5zqz{$7Q&!ueF8C-c@x@T&?v0p>VC!U$iro-E z1ii&mtfjJt<=DsGrk7S_Q{mN`D+94pbpuWp(HFoL?kcu;1&(!ER-mH3m#P7B-@ZVj()w zYWLN>C0BSArz~fB4eL!=r*XDVLw6&h{7t;F?^z2N)Nr4+r_+v;F+$$w7Hwj)*`e*& z){WODd-G>4?m87K6MH5*OxGraClz7o&n#5rY^t%DYddBkz;2i3o=5%f+Om0lDO=6b zWf1JGE4kmjuPjP7HZL}#73Fj^9?s7*&+-6|6 zJ?st%x+fh>a}(gL#h}m|GZ1=|$Zj|7I>JNVDM)Xk?XMLPp3Tvi7;AU#v4iZktvIQc z#VS{itsEGh_IWJ7zu=mTfdsM(#F`{&|fJ76q|;OJu;7MPK2pWO0}2HO*fMtW*IW(Sq2WD8db z`UV$EVwQ<@P40i0W}?AR1fwC>tz8aKPs)XI6k^VACce>hj;{M$w#DjWHq$sr;L4<} z!TFoucAd$$7tXCsvw>u@)tq$D7LjkB$8iJJsZDL?>EUiKzH-#yZTC_L<fcBA$CZ)73;8o2Qe}48%2#H~!blO195cZAVJY z00Z^MPLE8rvTMqwqjBTrTUWx0tN#R(QjM7y_PLW;W{--@?)h?5ZZd(xD!0$h_361$ z_be{?X(Q9$swz1iwcr#A*RiZ)eYTnCM&2H<@N@mS)>Xb-bQSo$QA4kC?^M*gEIQj*P>R z37eH!Y|ZPMn#@WuANKdKh>4d7ck$8Il+Bwq;;=2={NCJ-BQO#}c{$-1%s7_q`Qu4- zm7lvDW0uRzArcNX&>OM{bf|_qX=ZbdjU3Zy-`v~|CsGaCw#b_P(%%>7#x4Fbjr2Wy z0t1}OG$*@q0dpmqM@#cYrEcqLOQHIkbD=y?<`2@08BEWLgD0$y{!{PvjEaUFomswU z&tD3&>l3qc!oy^R>8#-cvjmAoPimrK%fJ?3UVGJ2E6dr}Xc<=-gIWnC3Zm zmA?_5_LxY70}`7y3_#ax?Amw&j*{aO1RdtYx7VCFEof|ZS46U{c)J57U`NWR-sp_5 zO~=tW;)l4n&qZn?CI*N4Uk1=Rs%pJU!x_y_u~5K>kG`{ zAGWBtv4NxJcCo;8PI%gEEjs2%rT1t~Cg6$2dMnR7pW}(8jhKz*?M>xQ8dUP6fmz6c z=UFyH^Ja)S=%XWE#=s{y>W1YuGB)Q#JnL@ywqTNt zt}MAs!7W5#m=jqrMG?7g;&?qkZYo#hdF|Cj|Aw{OWz?9}v9)=tW4S4CZU#JuJE^(% zKkzsXlVL#Q#^3a0{s8h$sHydPj&t)|yaVNp#n9S$eg>y>_m&^-sZwrUB(Qykhx{wX znCN*2*I8`tOwSF`KMAXEM0a2g#c~v9YJF~lH?J%)^2~LFSggkhCX#qWkvf+W>4C-qPz_^JJj8KylYQ@p&oObW27n$Pvyp%EGDD|`z5W3 zCi`-T?UH>p-<>$y)!_VBO_Z@-L(K07_*RUYW|R&x7h~u~u7lW(X{^}kV=#7nZ+GX+ z5RVfGZtr3mgFcU&<*qbE%-rT#iF+-~+HI0LJM47Zju$wy*__?7hw*(oKv;4$V@Cfm z25$@2Y#Z|c3+KY#au_D>ZlX*v`;Mexj=da98Ja)3uKeYRY%r4rF9~Mb$~Sy)-|8^O zeR9i;+|0{R`kGO)5qh>isYHK5@#i06xuYxhoF1~t9Gb9;DE7DrJ28B^%8esS(A^a_ z6E`z`+w1h0I~TXBg>mfba77J+UkY1nbDLP>v_6&s+KtHazQ=Q1d)Ky3yYEdw4>95P z)94_vam5!GaX1J&mPT7evudqJnsEg)stM(w?%7vCO><%b7Gi#4a@Qbb@OH5c{tDZga~Sk=%L)HoiOuxfKm;%$b8d=D(feb6DV}3H>~TpFPEr95}gWb~D^UHD%$ev<%ggRPJfiT$GZH zbv&iz4zP@r@|K%4>d%{Y?bWVw?*VAZgJ-+#lf7Hq8KRq8*k|%?bJ>Y~CeJjNot3%O zAZ#fiXR&U@|Mk{)v+#|AuIjr3YhuXv8TuSjaue;=Ev;_y+^KzS(4AR(J!~w-^~hy9 z0m5`?u;-4~y|VSo5za3t6EM=$#(*2LX${<=Gh8Mjhn0AMU-@m)CIxg*hRn|5frGqHq|%O`O^p=~JR@{w@T|b%r=NNf-%X`^_u}VN{d#^@)vxF0RZF4V zD~_9J@sKkL&J3Luyf9E#JbJ}|;vvx@ej?bt_-WN>alg}H?|rtFcKjr3OL4&&fwlpN zMqN=o{wJw#W~}UIhDlyFoPKA}5C12W`59M)e|iB^1UrAY)y8h`XKZ{-9^i@mPcrlK zuYUg~L+@U@aTB$9cVQq=TzcGq;(^hkHuK+~NBm^0`*~SD%TLGF6^}n-zcUNZ3ZGqY zPUu|3G+taAd}u)N_`0Ga&42nm2mjjnSyv}ej@$6;nN4MUK@Yz^x?fZO(13m=1;Ya) z0;58s17iYX1LFeY0~3N117%D^pUZDl;QZ;IertT;&9BAhGkxFWg-wVb)bw2;d`y!+ z5|z6OOr0q84Dhi{-xb1VFZ12=%j*7o#%D2oR|vmkk?$U#+w@%_d~-A39^c^fUHGlG zKKA_`{6efrCF@NPwhX@(%3k@tg`A>3&lef@YhCBC_g^9WD099KgPeomfVs*#9fUo@ zy9&x){2k%k6+-OtpC4@8yPqD$50mB`<1U2H&*!@zYTO^ zhxuI7{}FxMkHBvf+w`!l1YytgtcJ4J2=~S?*OamIbE=VqLD$D5F|e;@bz8~68n)qMXx?hi2bIl}{-E@@b^1I__C zE8O9?&HK17?PEW&kNrevyIinl+h0h`JrZ&z^>IJR`KGKXj{~sxUm^36`J73}d?enl zpPJL)F62z_qi1c+T_I;?PJ_FUL+O*dLQW*7!Cfd%x=~-{+yQge|7lPqkQWa~&-j-> z9y}*K1$znF`y0};KPf@`{!n_>w-U5Bd@I(whTx8$UUx6*tNQ3$`sk1Dqdx(98c`mU zpndT-mZ)c&C_($WMSAubC1^k2m!5611oiu8bgYZvzc2gUxGzC{{=AR<0Ms=aH5mJG z&N%7W7nGoW9_-ace5xI87D&(d40TG~&kc7tlY5=XYqiO+?@cVbsFuHEjkCh$xVE*! z=&%FlhdC4Se>$RUV^4Q`Sw-F+`hW4V(7zZN`vz$C)_2U1?*nN%;@kO`i8<$@r~R)( zYq5D>2d?&c8pd5(-lwHJbH~ela;XRL>w8Mdiyfy=IM=q180JFce6eNkuS3~qd>O&@ zN;eK#(a2>DryF*r<~s2Y>wWRDi^)C%d;H$a$?}h#=Plx)HaWp6+y9aL>4pJK_NOWa zG~>sQne!zsxs)L3A-!kxOiyo&fvvp(igB*{kz;{yYc$n=C#1sR5&N z;jm2w53@fFLH8wc4=1_jp)t?HA7c-9rE+KD<9oiC=7`5|Jx`f4V5$B248~&y_3*EP zgnq8v)slFwUivj8?2jhleyj9M-++VgJ9^}D$9WiJ{A0q7X97x9WJj}~wUoFCkagU%4ktK$!#CCCu*ejkUo-1A?UMoH%{zUwx z_?c*a&JXb!h)YH^*&@@DufZxSD4G~~~b zP=AKVK8gB^#4E&W#hb+2#Cyd1#Ye>5BI^_VdtQ85{Dt_I_#5$e;wK{eG(P{eXntx0 zdj7-+&5K3;%n0>k#REnDbP3JNMgCj}_47skWC-<(MgCL>^((~H;(BqjxJ}$Co-Upz zUMyZE?h@Ia=>Od!$Ai>ADn2g$NPJOzO?*pyU)&>pDt;vfFnyxG{lvlINO6C0vUspq zDb5jV#f4(C*e0$LJH(^KW5w;_DdJh;1>$AmHR4U;?c%-SL*n;bif4)!idTv^h_{RPiI0j;ia!xw72g&=6#pcCC5A95 zWcmh*Bg6^fRIx&wBi4zF#a8i1alLrA_*p+2PPo72NU>5}Ag&j;i|2~Bi1&%liLZ-$ z#J`KhnA|a42Z$A7R7{H6;=hTP zh~E4z%Ho5~qoC#6{u}VwZT5c%isUyjT38__Fw(_)if_x+a~I#Tv0* zTqbT1cZlbS*NAtC-xFUD-xfa+1I0GH5^<7PEhfaJ;(Bqrc&>Q0c>7_!IFh@sA>x z!C0O{#fjqK;$pEw>=n-xZxrtlpB7&eKNUFvXE>w9YB4IV5YH4Z5g!p>7rzk07%0=f zM)4?dlekm7M7&XaNPJp+L;P6mhlvpVogmH>=ZR^tT|8cVTr9w{AD=H3XNn1NskmO; zE}ko1Ej}ndA-*o|5&te054YhRDIP6eFWxCWA-*l{5eqQUV0=f2Q^Y#4MO-hQE?y+w zCjO`Riuh~sD{&+y#0+PWc$m0MTr2JruM%$&zbF1u{6PGNI2OyF^na?jKs-X+Af75- zE8Z^tP<&Z@Py9?Af{7jd-(Rc|>&0bak9ewhm3X`Ol=!mvJMnMgC`|Ym&SY_(xLoWM zPZBQ_cZrXR&x-GeUyJ?mdy@43K(SJciLK&R@g(tb@mBG1@u%W%#n3qG{}6GS7#Ej_ z8^trlOT;_Gr^TO%AB+28;eqiVE*>H_h;8B~@m%o=@d@#5agSJlfCfaaH#7Sbcm=KqW>&5Njx#HF0o#JESPsF#xKZ@LT zV7UzyCyG^Ki?~Yc70(oJ6z>tA7Jn`NQQU8`4QI4iEk?x^;x_R#@oMow@d@#DagW&V zAnX4Kai(~<*dneLj}=c7FBNYV9}u4we=Yt|+;55vZ<1IcHi#?4ZQ^O-)#9DvGvd$1 zF;lI-Q^do?7V#KyyZAlvIq}!xr((f0<%>8)JXCBDSBOW8CyM8b*NOLt&xx;ze-yb5 zW$KeSQLGYM#8qOic&2!xc#rtB_?q~kSTIB3h=+?U;%f0&@ig&L@n-P>@oDij@k6oT zV1*-27w3wL#Z}@a@nrFv;tk?=#K*;-iN6v5A{HKE!yP3~6X%GF#3RHm@g(s=ahG_n z_`LW_@lRrKrVVeHI9aR_mxxD+$BAc)SBdwFKNNo{{zc>uy0dBR(qrM*NFdILG=^C$@;|#nZ)$#M{It#h1j7#PD3j zOPnDdCMLxr#jC|{i$4%w6!(ZcdNCs& zBc3f@Cf+4}PyD6$f%p$`@O&FisW?w;6x+p<#Ph_P#P5nf72gm)6Nemb{oh}#5$nZe z;s$Ytc)56!_=xyp@eT3!;y=W(3v75(#RXzYY!|!5)5TrlUE-7CE8+)Yu-5uNSez=( z78}Kt;xXb*@hb5a@q6M6;@jdUVjyb6D-p}Y!^DiZR@^3DEM6}@C_W?pLi|YlN-U~V z{)yFMQrsYJ6E6_&5FZl%Di+18e`CZsB7T;{$hl481>!a0e~7P$e-rydHc~!L5)Tz| z(A}7?5PQUb6R#0(7he(I69*^k^ZSbjiwndiv0Xe-{HFLH;uGR);>Y5b;-GpP&NvYt zjWF?!i5ta}#hb*3#b?CX3+;0q;tugT@e%PY@o(bL2K!v8SS}{TBgA9Hv&AdKN5mJ! z55($5r9(`M*NJzD-w~e>e(Ppw~F5tex_*e1oVra2VSATJ^I8vM{&Jh=g330KQ z7LO9QipPmN#nZ%d#0$mC#H+;{#9PI?#QVgD#qWzxiqDBJim!@qh`$y;6#pQ8CVnM4 zNtL%aP%IHgixb4j;ta7uoF&c^>%<1JS;UX(n0C2RTrI8>yTopBhj^xVrFfnAE%A2o zKg0*bN5#j*7sS`a55>QTp(Y!@{l%H$e6dM9Qrsk-Bwi?9BYs=FUwle@O?*>)PyC(u zx%dyUsM*GAv{)x*#MR;^@dWW~@iOs7@gDI}@mcW|@jdbHBF}EIe;6emBvy%0u|+&m zJVx9ho-JN3zLK*3{#N`<3@owc#o{<|x>zGd#f-Q@TrGBqCyQr@-w>}9ZzeJ4`Kk18 zkQg(5E`2BsJ;u=eNaVwTW$o_b7CyD3J zll@iVE#h~@r^J`Vx5Y2T!i){4QpAU3Ot@)rt$3_>viJ@0D)CnFVeu*PW$|rskNBmy zU#ksogg8;G5bMMiah14HJWf1I{Dyd)c&GS1@j3Aq;s@fVVxY~&XP8(jmWlJl7V${& z7;%Sqws^UCBRL4?BBg(fM7i%4pOX1Y(!V0UF7w}#MW|oW2bbFC3&kQ5^<}I$U7Rh( zNrcxRHp_gqxJf)wJe%C#ajua5CKAuzD&8schopa0e3Ha-&xvo#{5|nQnSU+v3?|)= zBH{lyu~g<2Vq9DF1PLnlL&v9I6>x<#W^ycFV@L?skln)5lke4G`QVG{0!NW7lG*dG_i z%6z&wTa3%TL2Q=!N^+{>Y?OYR?01MK%ltg)FBC78`7Y_dCEh0U`=x(a{GQBzB>hjs zS4o8b28ne4Ugm!izmmOkgmpK9M0&@F6J#C{qhgzQgt(Q&bG_mYnV&CSF5V(ONFu)< zC&xO@OVYnd!k>4=4`lvl=|30$CiDH!H`0BPIGlukW5sfrSBdk)T5%Bx_bIVc<{QP$ zGCy5BSG->KH;Lbt`NQIm#ka%{Nu>8Pat7Y#InwF}lZgK?akR`QOFvDVDf2nf&ll@t z-Yk7u>=4(BT_nQaDPBY(9#@d47vClkk2}Q&WdEq_pO^WI;xENF#b1-~=VR&rD1IS+ zEryS>;q(`WlZeMyv0Ua=;yjtxiOXbugt%JfJ>u!&mEv{ceI(NNp!fsv3GpW+;_)-_ zLz(Xp|0MHp*19VeCyLWZq<;>HaOR8k;v%tyL^vzNvq_Z8r6l$gZj$~U68_vLJ|y!e zq<=;-AFNNrV$zZT&42i%6J{l75_6D)S0)p3G~-gv^&n-zKh<`O)GD z;(6lL;;m$@7WQAItnj67hUP=I@B_%luE$|3&-m28G>E9JUClQaY#DB`Xq{BWpPAnH|$U2NCNIbVl%!tdxRV2baTHGq0 zDf@H9OT;V08%R8ND~WI(7Jn%Fr^FXXxcj;6-@%)A2m9oD^yqSc%J7oW;%zq&MNaim~|El=5 z_@1~&{6zd434a5fHvEw!^y9?{iTKxuahWd?vogoe-xznBWqzIb9q}FUQ*rn@xR2x9 z78%BSFw!4JBD@7+T;?h1Tg4SJ@05O{*h7wVoU^1qPrOvTQoMnLyIV=*`$IB+RD4SI zKbHL)GJi+>Nc_F{ISGIMDSc=?^hifBiExIKus=xV)5S8G&nDq+vA9ayN|rj#=_LF+ zTf9iTOuUYSyKjm2%lu*Sahbm&{*IjFIDeOYV1xC4fLJV!632;?#c5(htPu|v>%_%k zi+Ci7a63rkN3YDcizmtaEa}e^FBPv8ZxC-5?-su!K1L#($HmuV{<`?S%s&>tmbtSL z&mo`ti-W|G;#hH#I903=tHt?ZRBRwo-;-jixLjNO;xB=IcqJn>TTO0m#E zcvvqQAYv+M^drOrL}ZaMpDoT4W8y*)%Y4QimXQom&CUA8(c-bl^oo4~YLMJ}15)zDw?pcgw{+;wNHZz}gQGhl(S_>EcXrffy5yATj^XitEIq#a?l{ zc#3$sc%68oXx>AFe|Jg$plIGhg!vDpe@c8^d|UiL{GIqW@t_xRw>yvGOLE%PVHsgCoE_=5PdXx`U@ z{T}H*75^#@F0juJ6UT}Z#Dm1?;sP-yn)mbIf3x&!MDt!A%ukU1WYN5T2lLCMzg4_L z{62~K@#Er;#Gi=oiN6*9Ae#5=@LWIi$$WmGI7}QR9xRrNQ86Jd6<3N~qIqu){+>hq z47?{VUMgNG-YDK8-X-2EJ}15)z9Rlod{6wX_y_UNVlf0H!!Hrddvnn5Fa2b3npi2$ z63u&ba37Wa2r(caMvsScJUPPbnzN-m-ub*PVu|qL*ldI^WvN0yW$t(*W%Fq zY@Z56gw~D>uS>k!(wc-uped2@SGvbfMH^q0wPsP8A z#b~P>mzIcQ#Qnvo;=y92I7>{5DRG&2gxD<}C!Qq!oA?d!o8lGX)#Cl)!{To7N%6YMe}|m z;&Hq5PmAU~N0`4P{VU>|;=AI9qInMz?mv_M3y}jAmT!SrBn}o25~qvieMz{lmi{nt zftV6o#dYG*;)&uZ;>F_S;;rHx;$z}&@n!K<(Y$Yo`0SDXA0o#%OxGB3e{q&LSF983 z#pU8Eag%tgc&>PXxJxweXCk}@r2kLxIq?PY9q~8f=i*o5(1AAIBg8|*3b9VC7nh0V zeNKemBmME>x#9()d9M@hz9s!5;`hZ@#9xXZi+>dH88KU5#PMROSSijD7m<+t&0?Fl zLhKT^ipPs5iWiHQi`R-bh>wz(zx_abT6|9Yx%dn5ZSg(v_u`+#FT}6K;l zAigaAQhZbVT>MH5VD7^F42uKBA>vqZf_RWPU5t^X_;#e&ET+X(;%afdc#LS?lg0Dr zN`H}fnRvZ;lX$y$xA=tkjQE21viLi4lH>eA{EPUd7#d>j_Y=p9rQ$U45YfDs3;$+I z-z=uZmEuw2I`L@nWbridT=4?&9`Qc$Rq9^DTvh7hlYCO!yfJoR9yI9W9DgZUxSn|MNB zExm~^^kzK)td)6OH1UQxj$s)8P5hz9Hk;9}7T1ak~Ay$jEVq9zxlVVD26_<;v#MRfP5kD07h@Xg`iC>6c zi;mVY3dDZmKyfr#f%YSoij&0(v09uhnspmIS1Wy7Oo?V42li$i2V5od4PuwLRqPeF zi#tWLu7l^#m;NI0GVuoSX7M)hF7aORe(_=PF>$x}r1-4(y!Z?84e=fEH{yrl9`O_L zGw}=YYtej93h5abviUwl94?x5CD@zqN`cd4euy|*oF~?baj`*6iYc*GTrQgLPQm}x z(ytXah+U%j{uJEpl>SuFtXskS9O=&&FA~jnsbGJV^w)|vh&PM(iua2Ti;s!ViqDHL zia!^BA-*BLBmPGGP~0PaB7P=*A$~3PE3oAB!L7{e6ic?J~%1cEXKP(;KCs3>?5!HWtCf+7wmA_^*A5XE@_#SsTk6h*}d4yY*q zT2*zD4s!2(-~aiZ=llPDQeEe)vuo{r_St8s>Pl5P_n2>|I{TU2bG~u*^SHv|mO^9p2GkDGWM2=?#h^%U4$fMaOyYVKj@SKPy{&v-r# zyLuSd!=9}?AA}wKJlI2j3g@Tp&UyvhVJ9Eu9vt1Ad{6G_Zzn&Jd)PJ6$(M5v`<6O+ zYo3Ok8=U;T+{0dLeucgR%){$E6S$k z63lg;i^>P{#{w}AJ>}D1V~e`RJOj2CZaoRMhS`2-?S&t9TO;M@zrd4YYh?b@qj77b zVjie!J@NJY66XQ0_KOh3vtR#>5T4^YXYTB-Q_JuM)Ebfh(PMaP#BGCOJjut$o?qOx z=CQFCEV3UKd%+^>v9WB=~2hT)}rvTv0k@&e*vO z3FjE+RlFB?dxk|lv26U@$#|vLq!|b(D_uH%d_~#iwqhH>v9a0Giqh$m%bcjQCH{^~ zoq`|a9Y%z$lsjR@v}t%Rb}Z4PiqdHi>O8n#Zt0vk6;sB~odeqc#U}t+bQkNHs632g zLhJ`qwDrltH{}#N`!_k3@q=!Pr(XYeId;$U^)>}2KB|*wi9Lojso2S{`_AU4os{85 zeVwtz^6^}x9yak2e8gkr<{_UXgs>NKbIy}nioE9nayOkPw;K6w7m&LiSZqD+jj0E5 zQIBm%$J+M+^0Y;KgnbVKh~;}2d>qH=7YyCie20*Z)qEG7$F~lAa|D?q$Lz@S_@;u7aY;V@Zcn|; zFFTJf2_33EaPblL-Ebb?9Po+uO@pxDd+6mp#!3lP(`^5#Z^26V(T&Iq$G{Qanu{cCiDi+99^YL{@tkKthP~ihaUNevM3yR1PQGT? z1RtMeERF#zwYm}U%tGfQ%6KnBY`d)n-(L8Td@ZmEKAzi(V@UD+&64yO2Mp&U%6Kju z%Qv)>TpfR{AS?J7yF5n3(%tKEJ-v%yv&&fi)_HQBKF9r&HDVSA<#-M)Y+&(n$nA;& zMAbilT&#Vs!@erWv%YPx3H!c*9QwvgK-Q<*G5fjjA}^@9hiLVu5^@J{PEY`Z{hfSC z*r-$VH6*2hCvaXCbD-d(OJn7B7t7Lb7m%wMJAP_e?u^z!=hG&VR~XI9kB0Jtc==Oa zo0#vy!f-Gc3KtdHqT`Hfy7w)SWucLNYg)^9Nd_&HH2Q?ILmJ))FtdlWM-I;H@ih?E z3E%SL`1VZ1*R?fVERkHQ#+P&{YCL|)kQ6zNcj%}Ou%tzLi3Pd)aOcu~!=Z{RUV(t3 zYP{m4j-uRvjOi3m<14x2ofzE3-^!gF_c`T0;-Trjwt&>*Oy{MHM_RL%VuN(9DEOhZ z^14^?9an*6vOFY#C9)LH>dAd^PH4BFyw2SaR>*yG{>g%Y*y_kl5`CtU7)TtJR!2_4 zeBo*=nPx{*!O*EVNmNlym6XJ`W;?UU?1f2B%auE22p}h;m#>bT99Nvarb~v5(zq}x zB82Nx$CWc!yeRys@vf6<<>8@)^_0T9-~Oo7XxQOYhRDt!I~GY2Uh{YG=sTTP!ay{r{qVb!WlUT#Rd zu&i~hqSjNUPnbG)Vp;2Hr4!1zc>lj_#_TI+^L;Dqa1-dNu@lQCmCl_yXY8CSXO_** zE$09LKTJf-Bg5XS$&v;TzJ6VjHO;5VaXyy}Z`TwYvnO?-fsdLEB5v27ieO;p;0eO ze=W5&7S)2sj-88&M)CSOzKyPHQ4z+Q+|UJIHWzF)ZNkjC9VX1Ez!ia3(?THtbIRvV z8;|{@sWVFFv_c?sfRPgkKyuQ|%L`h~p4n<*n?fL^6%)!kATlnGwwjhZt#r!t787UB zY%ytOu+`*Xs{#4JR`7X;2{545q-kZdXO~VcYc;iO`s6v~9r6Ipo-%oQ*~C`#0dkY( zPM^T{_qCc`X6*Rq`=guBGxN~8@g4W%57ApyNS*^j0^(uSIyBsBFm%}~5np7=k z+m#4fhoW)EPM`6A@Kt~w1ZeDg0GSsbMsIAMqiE+MeEt9A{d1xo+$)l1&A&C6HJwyv z`98YX58o#j`{DcJVn2KzT{cW)yzMn1jqtrT6rhWGN*EkZ>?|eU2BkY-{ z-;-f~_4tGLJynkfwYz;aeEu-O+PN^Nvprpyu4oPSJfGs8=PfQ2W^s?Iw07`9XW!1* z_j2}_8m;5-Z@|_b|6XS8Cpi0A&YtHT8)koE|LB-h8$#eb}=XlXj zn`mB;pZ|W2cdUbDP4zimE8NAhsJza6xk{FO^PfLmtlZJ%_k&f9@G^i3p8Ng1?D=vj zD7Ra?-B-zSSILiAZ-3)zWFu0r4vtbvsv53^lppEJ@>|Zh_j;;ik7BW}>;C&eSKf`= zgJ+VHB%D_+Do>g(;q=eeeLHmf=1W1^Vb1a`UAx^JH?zl*5-IrlH(LJdXOfaGY}0_M zpFC1l*YZWsRcH39-;(ouKW2HAgHj`9TzbjO9?QD;56f9eJ4Wl?zDiXCC73V&uAJ_6 zreWTm(*suQIXz=V*K(sbkGuGc+NaBzMtInpeWcnuHYe?oj!H+^WPkTd*Yb>cax>+? zkB;vKRQ>3At~`B#-lyxCU{as@Yqt-nTvh3-q>aA$Yva$pJK&ddv!x(W)C!-Z9gE6u zb-ZQ!gWl>|{zCZ&Q<$wXMXi; z{JFAX?`c;`aa`)5q@HzpOP3~>BR|#kyXO@4!F|Okk1eTksh<~1!R>#XK3$^~T*Wq5 z@ORg#ACAL6{2Y;sx%+qZd2ZaQGf8_B`=-z9Q@`7pmPu>37eDpf=>hVfN-4OqlI)Bv zxvBert7-ZkDeKfhyQV}lO1?c#?pEJa4KNoh-lqIqsVF~}PYAd=k6S$Mhto;d$&D7D zPFiX#P?}4pwp8x>QE{y*KHPP5-!Z+9l{YH(jq{aXhjOXm;&Ok5fBwGH#pxa&c$auM;4z+yk+qjeeazWz03EF%U#f>U-vWF!D02cZkJj{ z4(>ZWz%{z^&dSWnm55KNMZ?3r7briD>y|9Pyliu0=7^%vSd*epy z!_H*Syj5bPyM7$k#r1P(7Zve7<8)FFFwfj~rm~H1oYd&xH(KY6-fHQ!rLJ*ZOVdk~ zZO?vPwL)%L?|`c%{N8Z?fqlmZ=Em)jSNE+N=qWkj@hmvL??<02zAruM>D_qB@Z&dB zA$uaep8U_Tzb`*K^?37=Eytx|cd-W>+sXQjlZuD-=qx1xt9s(PZ9kk=7ALi<-+Rn< zSSt@clO@&b3)_mjAT{(%qvAu~$jSOV-+Z~*;qCDUe+sU=N~x++UfG^h;j36VJ7>zy z$I7P2kG%2NZC}Sr*JE27*KLo~sKu;JQ<|2v7`Lm(geif?{t0|BwvFY!`G>bFRbItc zp>3;rwxHzraS8S~mi@1Gr>2X!MwQ>d;@QJlB_j(DI*OSkTyoq!O)$I+nh1MHz!x;)-8H;l{XZ7}qbojF777%>ji84ak^hLGfw0hU#)_ z_jceeeim3&`&yezjsLa_#DBp30`ciSE}68o_=>w9UkdLCiEo@zLi91B&su0a(3ZYY zOh1Z6etcdEmqr@r*|^X6#Z>&9e0-^^k#zS-EX6VI>p1JVQ^J_4+&`fzE;nBZpt$+K zRMou=g_?T{Wa8X&VST*&cbMaLkAatT_W;z>aM$aMrH6Y(5uE2P!L*y;c4Kxtecg=eNNm>+TOP`rN}XJEypLTXS7^UsN>J{dF!L|KR3>!qeSHus+Rj zZ-p29Zr&;$aDN!Vj|T2P!B*cr1}mKgZl2Nv-9yn%S?=Ra@d{9Pqt+PX-HkPz2Dlpm zY2sc0{)z7Wu)oZ`26|t17om|~ao-P{Uv=LEEw8zKxEA=jI}H}T;og@eNpI>u18*to zZR%r8lJ%CbE?3sawKpBZLwVv+t})!X2> z(W-tmygf$MpFyNwr0UDC+otMAeFy+ePe3*6YWf%$F;COKfJs+sdb4Ku4?#^YLfd|< z>5rkdpJ@75(D13IUj&iQG@UoNAJOz#2*jhBehJp9pKE$NBoD;v4o=e(AH?fvnUeHjydFVo?lN`03g{_Q z{}K)Gw5jvKzt5O@Q#8N^uiggT`5v!+D>yfL^`0QxDmE)kzbk|*18Mrl2*KHDdM;`-Crv+x z2D!EuT0aMLHm4&Af&EJ)0aSGL7ILkI?B~J9Gzrg zn*Is`^O`h$62h%AP0v6_yEaY#3T4IX^fhRz&g=B8=*wM@gDu_G>3rQx_jUSBu(M>H z{w^eYtkaLd*8`u|=fJW-&+B|r_P7)J!-(C|6Z$vkKI2d5`PfZ3q4OG$ozQ!Am88ih44wha#J@8e2K+mViDwYo6-+z}SI=f*3w$t#i81ikT&u_h2QaY^ ziOMJv*TSf4nHZFfr5h6)VC`ZiCc=|TnCJrMU&q8gc;$K~?n1Y?feF6AWaU^S9#wGn zJrldp{Z=t?6rNno#FsGaHYWJrPFGGqB8pLEJ`=qVR9xK~SD_7YHCQq($M}GYzmoA7 zx}3tqP{fhS#7X#FW1?FS11S?{(Pr^X{0g_bnfM9Ay3T|TPB55A&fzH?5?>Br>rTA?IacH(D`?i9rbEI!tUpD z_Cr`^!VhP$r!1Vu7#0*efB!+O0B6J_WpJWet{ zMYFr7%gRaQn7R53P|Q0M6YX^UAJU4(RE1HH=%iahY$v?_vGZqk&%2q!lkbF<>Xz+ z75k>554b+C%PM{S&?K%8?XtZo`8@6;=QueN@Hi>#EypAe!ZKIr&4{tE5;j8~8#_ z{uJ3NHRTpGwCk9h{2A+XOVh7)V`T%Ieeba_TXNdZ5fAmZi9}kkklRCE21xlj2g5)(BW%8L#D_G3wW$4XOL^ zHAskpgm1jm2v{VSi4vC-H-;qy{#ReA4@1FrK?4OF$w0uW^XsAnj^RIbCb*1zkN!PU ziJf~4m5i{b-m@TZCE+W{W#oFaWDI6?tg<{$I?Mb%AV$Pv9>h^3=;+aN0eQ1AMjFMn z3EFzJAt>`(W$hh;WHhhQ)nk&H1id}_3=({q47_h`f)bCmngmu^Plw=3OcBNak4b7N zK{iHs^i-@zysc=#C{KW`E2H~)KcnDiPk>I5uNoMo4Iq_azLH#>E1__4^kw z)*6=xz$JMx{7c4I0mzbfcryUw1OVnF*%;!{+Q9<|PM2NfF{z7;i#>WL z_{cjW2>d!hfT3;ZfbNp9Q~;<2|4Gic$pKvO+(`O%nE-5^*Lbvvfc>|`qwHEo=U@yD z#&VBIYp8RTN3W#LmotF>vqlBou)?F=M*{vUt+CP}*o-;PxZPutngr_+5Q!k*a~+I( z1OWo#9!%fHMgbro24jjgHVFW=Sc&1#xK98Gh!A?Ou~`79)+iowzX0sUS&R0ELVtwq zf0tubY6zJJJSOd>RogszIfN32bnhz}+Z_TIjQ9|fp0PtP!bH^bVUKn*8Jp7wk2s7& z8BtH7xltk|BpEF|dKHoZc3>&MUg!$2E2+Ng>C!SwPXnat7Nz+NtEJBSVF-1vWn-5VpWPOV+jGPWQ8b+lj5#n2?6U1E)E3s zkCF9WnFhNvgZ4;37vHP_XdnQzq8k&Pk>vnrL@6oBNDFE*g4lmED2$9?8b?cib1XuP zhC!1hQY!!RwGL9w>;jd|gZcmf-YT|sOF@WO>x${p$c<6C4=000o{*qQ*~kuRbEvXT zE0i@2+5<-)hFqJVNktqW+XeM$SnPQ3%TP=2DfaD=!2l;I7roQb2Vj%{;2pj$%or^Ic;`x1WQ+jdopLNhjEe*S z@6@MNmk6ui9Zxp^V+8>3RAmAfCjfYdFIzQA1px0{!(bdQ0C;B>wM-BIypu$Zi2{Ik z?sEYs69BxEhqD7?vH)!F3=V4BP;tLy(on}ccQES8gC_k(@5~D755N!Je=v+^2Ll`s zEbqL+Xq+Pec;`=?%o%e90Pl3b%GmNiu+eEkQN6``VA|8V|h^j8ja!Q189tY1nY6}sLBl_uUrgZg#hYH z-iIl1ivTjw2?(qdKt0L3m%yz82%z5(SS0|zYmPg0!s&7%UhiOhBkG8WGAU>r z4QfM4*p5TT7r}I{AN+j%x$#}lWQmkYg%hzk%L*v?DX8BAz`L4jpI^>X@LP=n?|10N z#vcMe73x*WMpaOI2}k=ij(Den>F+ahFYEAU(EJz~dnH5IQaM(#Rn(%fNKiLUQ;y=`bGds%H*Uk$tl)CDiriR%$$8vY=nc>y31vs1serHA0M2d%9)(S zgR*t@YYec38p_t`t}!s^n~9;Zv7E`tEKjyhbB#-Fp?o=Idm$=tSWSeYqHtdOPJtq?lYm(qQL4dJ5nZWk~Kuc#3I4JIncIu51gSz5w8^RU9Q62mtQ7l@dV#z+HSFr;#N9 zxN9qch5|rOd4fPA0brr@3W3G~z(Q#e1`Z=z0O&f|?2kDDfXnA$;xd{E0DY;FKyv}0 zFD)g|LICJXqsY-x0O(6=DA7s)=u7Jfs zi2%9@0Ck^Dpt}H2_p1n$2mp0oOrVDVQ1^7UV^0B~?tCnl(MtfR`&I(I1%SFgL7S>OBsCyfN`Wm2GCCcwlfNIw5%YUaS@#nb(~Sr9GU((Cfy_@q!^E6>%Acq;6x+^ zI9I3v4lM2fW8D*=r;;R-kHRtr<|tW^#iDFOzP<#h!~p|wRc%wgbBYf;nzPT`D*#Yp zm9{QldjP`z#w@!#-##tAp39y4^34$_VWT{fuluvmDAruKEx%?iY{1xgOaSOyxda{; z00$=mI|RVNiNF&A5Yy*Q0oc>$gZWw~D72@~hx22m&!_TD+DohU=IhVVs_SyVxX&R_ z(4i{{ydVJRyo$h!0>FvRwJ^c42Y_HeKQHN z!@y5D?T>q^y}PkIG=35Rf#G8zfnOXT&Sgc&clp|DR8a|&jgwA$rnLzghO{Fju*w=c1Rt=0T7^tflOP<@&yv9723}a3ATOk4Vd(RB z?ToT~haih%Tr^~ongpFgdIt!36R^xSy4EJ>5YonzKyQY!P7c9gcHHhElhh>W7t$A! zpe3(z45&@eE2M2AK{~75$02~TajiFGl9~h~L;4;PNHlYFZGxd8?HCCRM*nb!0Kbgj zs#nM)HDhl=NSB&`pchZt%0l*FWHNYN#@LY71ZDm@Jf<{ck3E~|#PX0yYFaQOq|YHi zF(YeM$p0{4>j#-Z9RKGEfU^?LV~i^VfPwfN!(*NR5WWbV%R<^6)VU@LWz#~|Z(RQ0 z>BIRUlh#n@qLBVRbzVWEmpHZNuPdV&OV~58gUz)4P zEDf1dP8BOcdb4b(_=6+SN{2v2EgobOuBy$rETr{^uwP~~-s~{G&tYP9$fPbZt_|r| zk?{)l;kyI@Cb>uizfTA;atyn(rJ7SJdHSf>~a7Z1J60ud%k?=hjAoB`>T*i zU1U5N(kGMg&s^YDf*{^9=|o6dPJ%5hQTClfFo@SpPK8WTli;_IzJ&xU7^i>KCipp| zy+MM9*+{=S1dp>#{|uR=CP7?S|Aqu3(QgfR*q#C0D1%d6VJ#6|%-@YJRm1iSu#t0K zLf9lV2~xs(a|n6&uz^x*6C{PT0VH^dt(@!-Y^Go!Y?7J;jl=q7B)FQrB-ASB*Cw<j7cU(gwu zg0Pp=BxoN__?`q~IjwZ8O%M(1$yna``Tqe%TZiDPuE-RJy`-j@Ey7w3gzD3b`lKRj z&#>MVp!a9aguQFmt6NwrC+i(7D{<;|CkLLsVUtuO7!uZ(kl;qP`LNmq1H#$^B-o0k zG6p#W6S^TYB5abH1eb*M{Uo@!9q@6r2}Xyt6C_X=o)otG#w^>6ljPe1z^UY*x&RId07s*FUkz(%7@__5u(Q1G)Z(^$WZn&%R8AG2g!Km@ z;%QzvJ0bw6;Is3LqXNME@s}M8}AeF2mlv09xDcrC;%*G6HKj)ET z0pLnU69Op$KX4600abpnHPQJ*Rb{hn#fKB-7VFp5Wfv#Z=_VUq}olR@wG6l^X4#p)6b3$*4C_FKY@3+%PQ7bXN- z7MRpU#!!J?LdFj`mKQh#xEF(cs&#>O83|r%gt9gc!9Y%dkph#{B>$N8 z1m2r)3B~AA;G9<2Cbcclo+V>07x(QQMjgG==vH7-7a98&=pT~t02hJ%9Y!qRX;RMu z?JpASsE4xN4#5YsZ(xB*Y7&er(EaH7-p9C%8SM}_tBs)rS|^nG55VijaED+&=ZcF9 zOj47etU#Yif*+HCPj(1+tJ+nlhB2jfok|O|m1Mk~!V?_E&Pm8zR$x*W*XwiO<`5Xm zpuxDjpyuX~5N*6t0Ej@Y*^H|MfUEl33;+uS03(iY^1N062)L(l$;wzP01Q^UIJ90b z01Q?OngF;_00_x6cH(6MKuD%=#JE`iumNY0GtvGq+CPLAR20}}kz0z9`A31tI@4Ec z3iKOTGZT5^jv8OFwN@2q50hX$FG<|yxF(LX^g1**N=R@onwtc#aG2j*L*V7}%8e}o zph>uA4DCWa)x1cbx*uLAvQ2qkvwj@vKy3Ig0;*Ka_7To4lhVRxIS3$%@7{ERWW z+hJV89{XZ}NnNz@jRO5GByAhtI^V_vLWOPPD+St5WW0q@^_s(Y6C>yC0+YJP_+f#b zg>Gfrcvuh!8$YXU{5Fl!7W za8dx6BrYNFg8(o|OeRnz08A1y3H&GkOcGZTI3)l~5{n3&762xRWdwc_049mm1b!9( zCJ7}7;8y`)PVf*oBLK_^4G8=$09^TRO5hIxBq9XxQ+a_l1oia$8>8%afxSH0n1IZm z1t#4@XK01`<8+2XBjO8dRzN-ix&Yve00C0~sQW^8jRXOpBK;_lD1cPU2)R)EfJXG> zSfmu%M)YQ1Nh&mH9*xK-OwiCxY$F1N!Os9&cfy!ttS10uP_4R!dUFW-Z($s!+1mVk z0GLs~&`VupY*Ls|Ud@;z2++nBV^aZOWnk5_nE>pCT~?ufGgaKdj@8Ifv4(DJQRt;| z+TknIHX>P{me;2;>J1g@<+#jZ*Q7wWLg+0NfY2Ke0Q}n^2>v1gh&F920F0q+DA7&; z7(-id+-@%b{Jc|<1)zffaGB&P0v!c_U(}vrhwUT)tOWi+iDCg@k&3FdF4S&DE&OM= zvTNfs+Fq=gjV^^IE6u9*Db(|DM(%wm1$aL}fU0gMFhBsP>Qe*;2>?~yOJIlq(63%1 zFiZf5tv3mb5CHnsy97oF0R8G?0%HV#e)R=`iv@siJV9Wr0MM`eT!NPh0E@4N1SSXo z9j!TmG6A5Y@nu%VWC39D)t0~%0budfg}`M3z~ZYnfoTFjI}Ro=LjY*U(FA4*0PQ%Q zz-$4a9k1cCWv&3wj%x_a698t*^#raG04B%#30y4zv@+VUq)_8OFZzdbTIuPu;|!k7 zRu-CUVb0+<7V7*V(YusF%L;4e@RA$=HwyrE-$#j+0)Uwh61Y_WFta;>)rIzLkf;== z+v^Iok7z`9u2OF(w5QvnTt(ehXwp26^6LuqbR6p)imY*Wp}hj++*Vl(V1onjWV|;g zi+cn>6|!-Aq1FLM`+4=ixUPUE%BkXkLVXlfbYiD@$RV(<9LmOhh1xTwC)d{n z0K2zwn0P|~u=^FRgWnW@ZTEA9+DY2|1?_&`vHNHYTho?W`p1VEsZ$j7_kV-jZX_r znnxqPEY$bWhz;F<9~T5LqJm@N*8+eM57PW^1OOwh;UOmkz#fSUxrN$s>O4)IUpP8j zQ1H7#lh#n@=|X*eN9Zif1pc!ifX?O&v|j`OogdK?zX||4ld}Mv5dbRA-=>V;1b_y+ zsWE`x1%L*tVxavY05n)92HIHx*bVkWp|&0-`Nwm0_M>C>aRiw0XQ9a&(QY-O=XZkL z@obK`NX=;+ua_F}0)X8z0k;5P_d5i10l;ove>4mM!0sOyXr=&Q_bvvSM*y(mE<{Fl;hSHvC}Opbtw5tB8d-E|}SPTGAJ11(Juz~9+)Z@K_r_ou8`h5%sq ze%kF90PHr{W&r`%fmSD?eM}=NXoSx(;vZayWkyVzM)~(i-Z_kLX`e=dYO3jj$kq z&dnS<3j_e2_sakZ1;9Xa1BeI!70=`E7f}JA!PL3{iUfcL(*pq73IGkZg0b0705Az1 zBsZeD(Kq~;@VqD%*kLp!oDtDilJR{5_$-IOxs-BQM0=71a}ZF*G>70xhTQCk zNoo?zkLamgL9i7I4r76^045D*ge(*QYTc6&a;*T+S_c^+O9X({;=^l=r2?>Pad|{* z2Y&x2bx=0XF=8o|-4rot9*tNT(MQmTuI%Hh1OWyD#N5phZ2<}RSS4eHL*S#P+ae~Z zNpN>We~kn$a}2&m5WuA82yAo!{_9yD?bswF5HEw+nD+|6Hu{c;Rz;oV9L3f;I#bYy z#^#7gYpC;)h|d47@SbLm-zHSpr{fPsv^FU7f5O@RVTWK9hwkkWlhh=5CX#Ro3BKSM z|F4Ms1COa^WVufdM@InE;7CxN!UilhpF~ehk&Io5w0@lqEJe>KFS+>+XX;X!x%J zK(KG-^74!TV91hm0KYo`0tp+lH!$7J)iHuT>eRoG931&C3y! z*3l+4s&B5gDK1(wFIzUn3qaW97J#tHZ~$SGDFhswJR)z~Bt^B?Xw%Xp*yM`ZbM685 zyM(AoYiUzzR6mZSmuHhkx*)LoW1Xnx=>dWdNZ@k_ZXkg_YLc1+Sy8QhLtjNzVJ+k&Q1?H?o<$slU(SnvmX zXI|7KH3`~A6aFGWDSK!8sMEPHu6<9Sg8<;x*ARn7Cjp?dbl@tXSO941k|DSP*I5AY z>%eX}*%o=|L#+yjZytU65PT0Zdq*$u8V4KkzhT`Zg2?h<(zbL)Fd@6xGk!GOM+jrfUj`~+$e+B zS4Op@-XM6IePESCa6Nu6G1f&*Qj_4msNMlWUcOq~*di=Ie6>{pJSgg9Gu{)`#*=X@ zV|tUrxEVvJ@le#HE;4S9>Kn-D;&`${Fd}?f)BR5f05Sb4TYjhLcc6jMk3_ZoRN>Q6 zw#`v7j&6G@YEn5>?2YP2sp3&CWA+I~)Bps#qgq@a5Ck-o{mUVEoAc=lQIpgpcq6KZ zAmp9SY4xod0x#|h!cVLMutWUis5X*}b%Q8-)nVk%zsB29le)?g;F)f_#~MNOJV zBjSp5r5}tK3HKZBqMEs8KTX#K0M}G9qD%q6h`ZPgJOY3bm#{e!1YjHCD$<&Q-`}SY zWonTA8^DjF5(XQ`qI*NjaB0aOIp;@JX#iX!&l909=lTdA|D08sH6^i?wf zpyD6;0W=qYUGWA*T2_Bpbvdh$$6J~F+EOe&{}fkpZ< z2zjT_m4gKVRGgvFLj(X7BS|w<0I2w#O#loN04jbrD?VHRsQ3(Wj1Yib@xDdcHd-~c zG0OToR=vr99aUt~URpJ-NPnGHea+aPAPCSK5oH$@X+M%+9i4TFLvR!Oep!)8Y7)#S z(h~-P;3V-`4gqI~dU&+PKmo%z1Iz#|2g1o2-3_VXI<&$s@sFww_H?-*P1eYZm*DZtzO z>jijQeK5eg)*Jiy@EzmReCz2BO#-|TJ=@1e?ieR*EGNKw%bNyx`*-sI@8NFY<3o3h zx*^{&C~Xr9Y_>iD-W1x`w~^RKwx#`iTbVm-GxZPf7S4gb zUBte&j~W!?|GJ-3;9;TvqODvGAD(tI*$wRR>{%;?{^&U`;aA>cF6?a zG3M%reRXiu!~kz-oEqRnHZ8!L0H+6dC2dB4x8u$9)#Fq;(LQpPZ#i1PC<|MDtO)Ra zyEy^gaW*%=yT>jM@L6nE1b7eDJl`71?zE4*(zlVhUG|aleOsA(D(w4*fd^g%cth1v z-!5V=g{>A{?t7lOmu>l50=ysUR^OY%-Va+Xwkp6Im{tdPJJ4;u4_WfFE&a~`@9??Z zcZ^uDz_N8+fOm`B9pD`v>jS(^V}nmcTN@<>7TY}m-e|GW=Os3{AbBV3+7#fu6ZiQ( z;&?r_z&9M&<^XSpc+kh2-;HSnmZu-`wPbF3fp5MS?*I+(_J+N_2(epi?fZOPm|I!k zyAd2O1bFIoAi&@H5BmDC`iBdAOCWbBz~AnV1o(UV(ExuV|2)9owZHI{ z@|Z6QeBYt_9n0h|(|eVa(*(~ISnhj4$>dM8FDse+QSx;qlfN(?P*VP)Ot(VcHKbQE z`D5G>CFNoc{fi2HEr1?VQtBecjm3qQ-_9zT{H5nFC6m9kNNOg350TYO{;J_pGx;Nd zqGs}%yQ*gLs<)| zkW@93*AddxOrDjet0_x(!JGu2Fu zdCJ#7O<6&L{HX7CEaZY}CeMP3L4aLn6k-%GE{<9jbO8a-ZfeS%M5jcpDCw@I+{f&t zwor+hvW?lxqQ1Bh7$2ammn2m}8+O;KDbKKQkuAGOO<9MgF&0OC^RZu|X7VKB7B!_+ z8qgKC*(=pdo*CS#rX1p-ciUQ5sVPwkt&jTdKya>BGr9WTre<=<{+OD{W%YJ7* z)J!gScB`3OUp%X3azg)?n#oCbkDAF@Zm*j1AcjC=a*^et=hT!Zm@O}|{J2j|*~{#d zBHuXJ{(_pxiA~b%|EWHX*th;E`$;K|(~w5M`fqC){ zr%F|Q9QLV_g~L+Q@iiZt^Dp`tV-Un@Gw-E<;(u3!5>IjBP9W|=ol0&m;P(qyz{u{8 z@a=N1ge8ik90b3ohjKkcgZnW`cszrW&LETZQYtb-eN0PP58}%+%tt~sYpH?ENb6C6 zZmFTFj6@%#SRggG!JdaG{zR>F#ml$6HXV}&DOh}AC*8MTmNbVm{Nj&N>4qow0 zR?<-rKNE&IqL(ICQnU%YBDv>qAaM6ZHC^t7Cd_tEfFjlX9eTg!KAH~wl5!UYOV5=` zR}!f>%pqEk_z;QeqEvDpZf5C3%_L8yvYes^601cQCwfLf=qC(9k~_iD*%IF__c?^D z;_j43oiAhT*4(dRgp6}HXVu(?&{^H?6Ohr}t1u55lJbrl3T{z$LP2mhL_MBWN&Uc` zbp~Uu=e9JOBxT(|5B)Rk9i-K)HPGZ)>o`@Z0Gnr>l8$47pMt>cS)X(*2@WGlJ@@!{ zjFj~=GaG$$swyc#xYe^s8O3AnLP^lGIVp2A#6}~cJzJ9LP|4P_HQiR)qX;FBq+8X_ zTF6Lv)GG00?M730wtLs&kff}qWMm$#p zAwBDOF-o4XGWDb;O(BrYFT{%qJK~sbsM0*8cXLSYR&IvfaYX=vGcZEtdG;jzj!f2V z$ar2!Zajv@C(4qF*_*43D8JjbkzC+ky|d~aovvSwr4_WWXHQhc|i zAfw31L%@*kdmEj_lO!isAXm?K3%ZEMFDI`-F6g@vE$L}2C+|kCv9Dzua&6?~Bgi%N zy@4?Dw398)mQqeBT#<-^>=b@Az!$2P#99(JW3QVuP(k7DICaPizC`lohO7Is}|a63o)SLh&EL35<;w?t%z-! z{TJFYI~OU)>_d^c8ndvcy{z6e}^={RMiQ;_eG4 z``m8T3iX|6(}clFX9&fAoKSt(@Wf3#EUrEEKZ=M*a)04RW4aSTktZpaqD>PnQs(in zF}~`<#wH%(Vf)d)CHFFn2gUBMaoW>OQp(Vc5+*8-@_7`-I92yQ3$#Aa!j9V@S=yGnk}=>wJ`QXPH^Z++YnG9;-Jd+-UX2q^wD>E8(V0 zb~L+dCM?Uex+a>k3YAnmZ6UB+=>ndna>DKUaU`03P0!vLpt<~4p=KwUU+3g83^bP$ zR^utrI4jaI1SkBn&RW!_#Z=mNm-#G?l7dfmM$HmdBu$4@RzGyAgq3v|7gB&4foXBi;;7KBf$Ymk(u`|Mn95Wy(Ftl%5( z$iybEJ3AK7D4$X>OOoGEtf3ASv_5%x7&7H|lmI0#_~G%t2(3=2rTm^^H3OpvBbwBP zGY(>13PUolEFBV`DVDp&0fc^>Io=N187L0j4ng^p(tu;5Yvo0G*J6s5e^Ij7dRIbn zHn#9Yd=@^+V__&&a16J1E37!Zu(J?40dd?}=dIHi6IVHkG+jjuphr>2m z2ZLwdGz?zk8AqN2igp-0?cM_VG|*iXEBa_EniUCGC1u`Gy0`ll$Xh_(z{auRF}4a_ z(taSSEpJllFmUDm<0PrWkL@g^Ed#b=KKhKjS+QoBj&ISI_bcg)p^g>IY*DPqNa}PY zn`EkzAg?5a<@BjaM{4N6nG!`KsiEWRQDo*QiH|YE8BD&)&Pbh}MYZJ5T?z8YQbF;# ztAmSt>`y2v=UCnGcrh|xx`Gt5P5R1ZwPeR~%sujPCu6nX*G}dWw$C?C=30&bC!7o? zTlqUD!^c9&C!I_w*^=xaDem|*VnohXlC4_oVJ(_EnV}7lX=Z2W+xdu<_7kY^HCHm{ z8hKfDg?GmWu$Lc;9vshHu1Y^6IDA|YuHeichO|il$2r@=L z5PX%p^f45?0_aXaPhjhQ6q&v(ficRYLd3zMb*Qji4sa!fi zI6U6fhAIa^xF1#K)Uo6Taw3)o+5XpU(#ug^fz9^6*YSUkzx&_os%!avEri!#vwbgh zzR?HHH|6TaKVaFiuuRzUrresg?8PCwv6Z+Oh;Pb$xpEM;9FVP8_!8wuvDvn~E8DS< zXLXp5Wvj#R72|Q(@<&3=lM@k4BQ)@QC8x2wSD<7PwxalPxOxK#*HT(@QqF0Y0ptjZ z-oq9l+BO?VM|issTiXyaS0Zr*GsVcPL1GoQ9xlYl63EN^;!0kASjlLY0+cro@5I(N z3z@f&c!QZ-WcU-q=ghQ2<{T1#V&kW<+ONgP$?wW_zntjAv>)|I#};9U<6NsAXlqH{ zz^|X=MpiuvAl8baM6G&UiQFt~Ry}qgv7H&#<836~#Ael_ge?3*udJ!ZPbfY`dDeqZ zBXDE0>d^p+OlDY*wn*^5Z~5sws2&K`*R*;Npu8?TNwoTUIm}ic0r?@=x>!Tydbtl* zk_!OL!`5>qIxa}25tIkpVY$%`g?mtb7dAT-?iZnungq!wQ-O=D3N)T9DsZ)Ib)m)>(t_B!tZ8S-_oS`E z0CdM@TYQae@h1R2#AaK3qhoPRgYTk(8|Aw1LA%wFuzr*N!T}MMhz92j#vqHgy3x(D z)@}-rMiBL3Yj+Vck0NnDwg^SqUJm3Ga^GQVyBHZhIw*h*pU#^aK)~qMLoMCqQ*f=^8r2V5^+a7mYDzhNSswaYw<4(_WP;eNNGd|20Gky=7a=j4nZ@I< z{zHOKua=}Sus%c*7oN@=T+oiz-HI%E~{o| zk^hC*hEAZ_Vl8`kRii1kd^e~|FGb<=oUR_#xKtU0fYFYKE*mftlcUU+zOFfDAu21*0{XIS#)& zARz}?<=tA>%dl8j4{+ea_-e=0bC7%nTRS3rWcmqg5z4oH3P@H0P86`UeG!>)NDOD@ z9b}$HVmmWOkZ~pAO+n0jkIYbH`eSSRJ2Fd=sAML-6tB=h;%#P9km-SCAK$?g%|d2S zF1{8@Sh8bl+ZvfEDB_ED+O|h#5fTfS>4nU*NIZoNp8@^H;q5t070amM9&HtBXhq2{ z5IBL&ijrOk+Le9VID-;5p3=1 zAoB+jKQp5t!{^rKV;gWOGCWSH#Bu7=S{OX-RsbA@(h=C&Ek>pSiK)z7fy_flJb-O5 z*J_DWw}Hpb)2yZ1UX=WcqFk!Ii^MzFAlw|;bjZ2(QurCIT?D{)DEk`QfOSqOUN?u* ze`@#Bj0XVLK@Up67GXi#CxC>J%f~jDr!!>aYgHt5gl3(|^hZf=Z20u=27zJ-xU4TA z>K$6UK>%k#Ur@7^?d_yoGUC8rG-~rMprU z*2ON_)s`j0m$_Nclf7m*7nSO+QKXQD{g8mns#Jxh*hj32*j&@nQL;EyVFTDDi#xJp z#I9y2uut=)VYjqEraV=le{8ApaE-?DE;Smu+P8wkv=rG-{R+=dJ6w%w z1L?}E-5u{YkV&;))6#J`I*yj+WIn?hP)oNn7zWU5w0Jo{)e27~IzE6=Q`2QHAL=1> zTJ1sWEznaH4jLW!A{^xMEkir)fTZ%a8c;Yqb@&kOL@u8ON$q*7tg=IGV43$EdCz45 zc~Z6C3DbUJ5V;0U`O)g~ET??rJ7i0c1IoyF48e*EDM_v)H%auFN@5^!SXv!9DGkOn z#=zeZ5M)wup`xwX&cqMiK6ub6K`pcbiAY?wwTo9}C9$JvLduqwQRZ&Ss~i}cbt{4O zpkXC2h?)+sX7hS1JOO>eCz~c1fRiCH0oR%AY%iZ_CYT;G3O+AjT4fzw11F``I=D{k z!I-l^t<_NbVmU~fQVW2wbz_f@0!WqRUOt+YmW4{U#xdzu0!10&7(aE&Xpa?&Kb8** zs018CJ@sH^j2)R44vP9r;MW$sm;q8j9~^4A00oV41ZHv^E0J%?!_t@t)slmv z@QsUPh+)Zb(;~dGDt%=afQ6ZI8{c4gR~K_w+DLPhHo|gWgd~{U!crSB75z;Hqb7?S z?d`Ohbo*SigdI0@BHk4Nf(}|t1fn0tT80iDdx(8Nu?aIf*LF-VUoF>kiRE+*=^E=U zcBO9Bmh;$}`r$2YPOWQjoEq1ngmZda;BcHaL9C`xAl9qeP(%Q0UCYqk4lBxf36J%0 zJP?cZb&R(#8sG1H?WWy0{V#xH_N+#&hIC{HvT3kDG11Dj3Nz;45R~AB>SwOKh?{TS7mpi)KR^Sv~5VXr;4r>g=cCm99*M!#RKMG+nV#&n_(Fe7e93uQQ zZ&}IRfxig}b^lR_k!^o?CeGQ&CC#qKJ!9R?5NQN=@g1B}N2iqgZM90bBS!;jJ+3Jb5M6?=}q?=HBJGNS#MS$^8)w4;&UoG#dmS<5k zw#e>xSUT6HvXonA$sE5>RqiHX)9hwql6?v#+|fTy2~ySvk&R;6;uwu2YsLLU!qN~D za3jn;8P0cI7hv76xiJR+-E}M##AKL>t+wk*swHAw*B9tWY%m?))-%F(4d(10gTUoWa7z@eess9rARYf>zQCjhIa0P z*mS2GHF8z6i!mmKJq3~%wzDBhK*!xh|5gYE)t@}1WN8q0ZL!6pm*+R0BQ<1(Lx*7j zRx~tZ-j1h1+zrH5EzitQY_amp+mr4f?r2c8Jkr*Owc_VL8h*hjw;gI9&2M`1Kh>r^ z%44njZ?$1~#mfIrY9nl-EipBsYP-Ftl*D$9l>e@onxl-zp|gpDkQ7J6EF8q3%>!6} zb|UWWg9nL&35%m+`xzvyj~m~J9PT{W{vKXzssAbj8S95^FeM?Gg6;226rzV9#9e)C zwS`1b{70b+E;&GDePWLE1Ng7>e;4|X^wdGKQ3LMS)V2zy*bpe-jt;-DZWR2#WcW9R zH3cC%Ejlx~#fNZ=L6oR%kaOh`cx+7JA0)$oxG`9`x5=y5aX_5UP(&c=%iU;fHa%0; z_2!!8ppeHPVjVGvJ8{II^)*LSS3tx89BCc#-*s36l@)egX;#u|8EgMWm3LLTqK&J^ zQx|46JO0?{tR454V8a@J9?F(lx`qL;KQha?q1=HmeiH~{b4hKgsqN{q7-)>BT?t0Q zdse}~a`00Rd`4Bb+ewsJpYz2B)rb$O5wCWUU12-Yc7OoWB6n2fl4jMbIe2i*!POI| zr4Yy13+4)B2^CfYd$n)Uk*hHRbZn89jJJvyyu8_htZU&;zIF4^*rlZNqO{AwI z?Uq&!wc2Stb&!aqIKcYUL;!gfU}Guw( zYc9kfj-ZeD8ISF0Y;m||Pt8pK3!5AHa8|4>LPFRh@(}*pryK}vkFFX zx7kXL;f~^7yf-{&Hq4z}w^`OX01k9Mq$CeIA8B|jl0201ND4uF|5dg4 zup04UHR9C+0uHu5Jb<>+tK6T$20O*UgvHUZj+d<;QM%MN!R9;*hQF}6rCD|Cj>4R3 zi4NxO{~_*8z@sYCzVFlNbaEO(2qefZO#lUf>}-lkraDVvMn| z0#AYC7JY7$=ot$s{awQSx2cvY?GtFuAz4c@X2b7L|CB>7mVmv>B}rX)Xn7_77yf4= zQZ1_D%}oXf`5dmH1|>NZ?Mgl_^{Xe^a+pr{Ix<4;Bo~p7BDM07US)j>a4-|!qw%$_ zlXLU%osX|vE8oTV*5liZZwJ18KavMgovhDz9OU8Kh3`%H-i+_<_}-20z4%I3w$g{g zSh&9a5{G?JgYQa|(R!AX zoRe^G)bU7=PjvVbyGR_Xu|nlaIN(n27mcV>##m@PMUZIzJu}2!dJprA368G zI^Xx&#Q1;fT4~zWC-I)6;D0#2_8T9{%Y$e%###)yRAKV&WTTV`HM{VxX z&i35Sj=J2AXzj8tBe$`wr6ISrxnX7Qvc_C@NB#1q);3RDN5j;PhSrA8+RogDm0cZz zg3hkx^-XP69c`yH)OB^{hTCg9PW3NujYb-qT9;KdFYk%V;XpV# zO*2=b%nh{GH7~Dk_#e8dWUQ&RF1NP5DHmDApJa0hd|T?4Ba6+6_swZ;tE+9!?QEq3FcGkfEZ0x^LzjZC0O`W;k zh80b94Y?s-r7!Fb|KDqD|HIiu8|_!S%G$6-_+U#2Ud+yjl3X= zz63ug5)uhob+ln+T|;|UQ(LQCh{!`T{L<-*OW}k`2yLsYp+z5eM7x?=8jxlc2V|^H zej_Y@m_p&Xb{Pr{`z1*>ha)q~G1&g79Y=Pj%`qj#=9ukrI8u(a*&LDi4o6msEye!S znQ-MG$PmXk1h9>Bj2n$G*$!JuW)fCX;AO?RITq*5|9zaVS#b{2agKM48|4_AgJ{S7 zMzl|>XmMhYW1M}U%aJw8F)l}f+m6H)_EoOKR4l)prjOzmJ5na9fLX5pHWxQY+OvkD zWNwygdzDOCV#&OA7E8vSZp(CxLGrT3ItEJt<|DBqTzyLC{A9$IISlbWiR%*Ll`C=+ zBYx~`Mm)sfmm)vH;kU1LIfm#0%7vFB<+$G{sN2*Xq@e8MBvQF(Ov(_)u*q=b4f%~L z-ceUbE7)!HN)s;V)e6o#he;Z$ig0|sV_LRj+(-n=cZ^pF%63cxO-W<1W2ExRlRLT` zPN}2hB*$U)E7ENadzK@GXQ!svaDSWq-P7cBw*B^Wmt(TaaRPpG98=XVN+#Lv7-_$- zO|C>Jhkb8Gj`Hf(UN(vU%cPv-WXD+hYiGC+qtkw0vMWV=4zs^<2J&^7+$P1oHQA;@ zy?jPaj$}N=z6I!;*43_r3ms!qY_oqmEMDP+GKn?*58%)p>bw8G@o%si|4@fir71P# z(fzep99%m~Le6odtMZ(dWgm!t zZ0*c)OoZE+GFH)%GC}en0qt+EwyFC#Qi>c-BPkhg?ZuDHQ3)i?R$fWN923Qb7_bc^ zIcb`9q5}14i8b;35lPs0lu!zPle}k2=h-jiA)N;W|MOXpF81@1Tw1>L>O}{wUNpo} zgSI+yv}4M6$H-Ag@3>5dsd8d>&dzeo#^D5)BWte`N(Mq!%m+Wwiuz!tGab&4N96jEVE_WUa!6-4Mk9LgC zccdTgI4V!Is}%c{4s`W2oEnf);K)p|r`b?$DI>FRJj5{@jW;ttM{4O_q-&6UYy8f0 z5$*r}ou~ZfoyY4tBgWYf(T>ro6l&}%AlK{zavT%vol+R~ey+a7vEA-UOlcCS(l5pS zquqs)m+GIU<4w1>xE!WEQwn2Z;-zYkvs;&rwEx@ga`kD)*GcQmv}1>mT-a%I%&@0n zz_E9^9J%&1WM-~o)OZ;O#|^PT8jZ1^XNrKzLXXzcV*lylKhnNg`KM5Zd~mw-Dl_G7 z^_wHV%EKjL#ihf`QI-yZ*b3E=9oIS>a)^Og`PdvP41|L?Q5?!w9GH8kjy)Gh!ay!K z%rRb&qQfO&q#Yn``>m2*IT|8AnU3RBsM*>tWvudy|2SOgv=vF7xYQNsRO*aKo;=k< z&;m!#&aw}(Ir7mrhK_ca<4|6+S>@RdYzcE5hXHdct|-q`y{gcWH5sl7XdY+>kcvm8 z*m4~cB?ORSlbRgrI2;!uyUvv3vm6;I8IB|EW8_3>mSaN75UG<~97sFpMb%tBL|-3Z zzekBsb`CaDIUSdzOl0AI(Jn>6CJNTO5UmJdjDE9)Md(Xkaa3yxfqNdPl z0ThjME>1ozCl7N>O|fT7qdwW?7$pkMSo>)%)q~GPD?H3TAAyEgq2&MrA3R3khS}1( zM@c*P+cRfl&_uJex8#Vhu@6Suovh2ueyqfEirh^3i7-QmTDN0)9laLT+Hb64mop}egDdYlIylfVRfJ5nyX9Wf>a4K z%>DzSLZxJ*==6z;aQEqG!l>OTsukl`G*vw~9RYcFm}Af=83)GWSPi|IJec5^qz9d$ zsti=C9e0=v$Ot_a&3uR>Z8VBzqH1W;^7Yt~4ISoiQBCYiZ1%$uwH-?9NPDwVrm|e) zl+Fb)GyuuSSCLh!8yx9!N$WaHbpR;Iw(*WE`<8QZT=*ZGHk-R75{-lcB_+O4)aNbn zMT>)xQbSJ{>YF-XU%(6_+GT`mLVlwn=m~m4(ItjITov_&Lea3#6A6Z*Az!)A9ri{2 z?m)TEYj}OWDo=GJ7OFa291RB+`l7*kzK~H7j#PQ_^T`6TFcv!Os|+K~KxH%>aTf>5 z0}I`e0REv)!-|I1u2`r*7H2T*L0*GZQT*Q`)E|-<2zWeYxCWEWrOS*^7)dKg zsAW%RK~*Fe4SRgiDmM~@%i^Ufm21^|RT$U$V>gmg2%y9RsHugx4W`U(wM(L%4P9L* z!p_7y_{z(x%iW=#wk}ACR#cZ8D1w^mDqm%OUi>gWepnDcEQ}u(#Sf<$mBC81_xxF?L3bpg zA~R|tD6Ck9VX?ZcijI&lfxEDKA4EMSb%`mNw(*RV8Rys%Wi}^0+JgC>?YGqkehUDvvada06NijBBSx>zh{SW*0#z z25P(!Da{5N1$4iXj!=P4TpdCsSC^wRSNTE#Jda#~OsPJv${vL-mEy}Uk_b@|<@3r7 zX_EQV(I!J-Uud4sn=ds~;4@09BGRmI4H_1#eoJbRmX?N=wvJT>(onfDq#H$3Tb;eX19L*503r!;>a zdR)XOy%wcuNiVkR%Ifm+XjL#!Da|@8sX9R=S_-|Q3hm7bUtI0?iQC0QGaA(`{jyf2I8f#ly8=9jX4d__WfTubdfvv{~c&b81aTS_%nKyt2gxpu5 zA;2kBD4Avx!cldl*BA1OL=ti1Db1tku#%-(exg@$*DF=cg?*o2S6uN1n8HS<~$k$rCq`4thily$5x5kZr5(!lJ z(4!5MPhkO?zl81GhiU@eNNKb*P*SSL72LzGMVIs#wM4qAZh=Y<&+|YuYYm~)Bl+!)d;K-RvKYAf;M4vHPkQbY-o;!^A>nTBUBoz2vr$J zbYBmMNb*)zpev|u9M>(R-?)pz7;Uw}8LL33xzIOpJ(K|?R>Wsz1hTt267*sejHga1 zgCXe0Uh8H)1B0pDQMV&WaWq(oF~3w)QyG0@N%lob(b7;LKBy8=jzE1B3#I9XgZ{jz z_k>8)TdGyun0BX!R#XIpk=)cOHFX)95R`tUovV^b)GP56DT*6;6Geq-)qNFmW?nSE zV5Wf%;zdWYbP24FbTt@I2}L%cpIE}hIuI$M#7%(|g*BEL0n8sNkw6iCDAH)Oa$dj_ z^)_{i+=b-kpo9>(3JuqXmK|OYj`%8c+t!0kKKicPn}RjQ2xQ?PhRazZL4?&`PvkXOhDdCV|rI%`p)gYzr3}m^)uZBA`Jk`k& zht4jt+|(9b+SH8k73Ids497H4jUX9Na(ZT=)Hv%#)*VV~L@)P3kw>4hPO8>Ztn^&3 zJK~O3R#y~@OqA|rG}Se0tusMQP;%7AA2u8GKRRD!~tYI~HNY@C>E5~RVm9x5IH1yV7*m6RZGQ*0v z%UN4inZ@S&B9xbP)wM|X78#u&ru3{J;1PYUAc#!JEJmrzDB$7+#`4zAre&=S^)4vB z9lDgH59;ZO3a51{DC-?vQYpm?l&=~NFnia`kLj9vbdXZdN2x~w(2|R*!{fe9OuA0Hm8it-8#%nNb3=%a}7H+Ev^{TNu>wZ_WOX z%3lUhJ(Q}cvv{e|09o~+x%D=Z$fPgmhh|t248`XSR!az1htU?iG2O-}MRWG6Rbgbh zHP%Q_gt1|u0(O?-;CusDA}4Ll_0g8v&Qqh!n94O%MCziJkvMJ<(elP03_(O%5=T$= zV|TIIaJhQ{Im-X#>_#D9B%$q#1hkBM$Rdmg-h9!#)a6LL zo)yY8Qw@W-vAaA1VS$0rnvZA~XCs`9P+jI!gi13fBAkcJvc>@!V?|E7F(8R_nTFdd zkzfQOm2rzs0L{(s4|oDHK!mH@Xh5;tp+m-I-I60Uuaf%mNh8ivYN}RXi$vXlnkXd) z=~W@Lnp)Ac_~DHB;Vi^qspwFTlr6-%v(-s4kwAM^R!`=}6Dr1$7S{=yTEVpGy^<|; zWeEU?U|2bEl@&Xc>39e&N)v{D$!NSYs7aZ!vsf`$>2rHAZ$p>1{Ns(q>r>4|4_wx1 z>#|~)qe~;$IuwoxAf@wRMixLfMRT+ytmNHL1Eg$|Y3;%WIW0$(@~Nd&ptHlHPf5SB ztf$r>gy9>a2r6#eLKREy3Dv%8AFMC#c@Vc^%Z=3ziqopTX)_H^4Z3D|RRt#Ys!4f5 z?u6o0Y6P@OSOYQNb$c-LRw@$OT!mMSWzrfFhAUjl4nf8Zgeor4@%zMO8GUi79zSI^ zZ>e6rDz^fqDhj{On;(|1KH1gAEp)^JbYz)_#Zs3jOE?!oL&Fp*R!bsgr6qv@873tW zDBUU<1+XpZ5bd+FO&jabtt;ZwPSvNx&W4^6A1*zXh1g#ct%fxkI%m8-rsu`#V|qR` zS#P*ltO*qu6ccq9taG?4OE90Sabqs!4lk&HDLaIjMpaFPnvNHW1VYAYAh_h_g=%veh8#C4*0`Y{S?>KTwfB$7+~Y59RwS=XHC zr_$ezay1thB?lE@nfGzBR1D5)dMk<2CqfklmR!O{NoBRmGi#Phc0lIjyJQb!-pqm` z*TjwntX*_AOma+`3>r?#W6@mTCVTQPHLOHK>+WKOQ{Y@fWe-8FTYYih8-H5Gf;j;%uirY>!1 z=ujC%&vM7I6 ziOVWdsG8H9e52A|E>;KB3c9hXKUIM;Ru<^75>=v_WYix(&`?y_fYcOrCW={xPFyd8 z!1RQ>cq+V@d*Bp?V9`;Hu&B3a55?tPtb|oni`|wBC#VP+!q6&cHR{#p5{5w-ZAt?e zexv^CN-PdQrpnY+Pr$6~h35CtH7sw@7hx!ZiMaH*pcdibAPJGE$cK zV5YzXM6Fds^-7jfNIIn)MUKWUfvr_dm=f2KWJyA;aY?8I&0oytG{UJx4QQNFEwCt9 z(McgHTL&yHp@=>U#X{^p>enwSwMabc0vcSnzzJ0att3y|v|-II_Y?;q;9{XYlG>V3 zAR=b=AQ#s})fGDtY8uVUnro@qA=GNAd=X`Rr+kN65HV4$2v){sk7$=%TcC)eHPT%b zku@CmZ~7LCK}TsH5iCG>wfd-6Qu3_zEo)_kgi?h(=j%M@$K{?fTKV18P|O&C6~ipc zqrf^Sv<`}_18X%cZ@T3(!#bF09n4Y_x8GWw6@$7OI?>~hj?g?T5eVXw_qZkwF;ImG zm}Q=k9km!5Rz$VMwF?8kEX`Q;T^U3tL-FZ)R|9Z?v<(r?0l!f#GA&_pM)QeOpcMm` zuelB&Hd9q)el*~4DJsnhrzfjex28Q<8QEktP=*|lQp(r`lL`kFTEk-3OH)=OB+XeZ zSRIe5Rwea?)i(u5q>wcx)8wCMTu}wdbxlZ8y}+q#bI5Q2LXTcnE#+Ialy6B+nfk`E z6kjLqHI0Zymo;=nS7LQo*{S4`@PeQRhC^i1Qlzlb5If9|9~Q(93*(1H@x!?KoFCW9 zkj_|SGvkM|4D>dUU6pF8p_f!)GOVtU>7<@@sB$ax|4(csS4;9NQrHx9*%qipXgs?i z%YyVO#MtLSQ{do`*u0c>Zmsbt{%Aok4`}0v`mQnz2J|=xFG~{`1(X zr&?R?Vy=oL!ciw`|2$zicyh^?(0y9cCW=j-XMQm{(% zWl1wuPbd*5N~(M1t4i-;fe6)e zPi+@Kda>WbfQErBBB~4$h8?W9lqpd~`%_V#WhPW@smPyjQVKp+hB9umDrLYf=2Ucs zOhsi_z*3aJua@i+YDJ1tiQjNdAmS;t;*cdDwK<|diA6m|qKDBMqo!z_8p=8sYNNVR zZ85OQ2L{F1VLt87ai4hc<4tX`aPi_Vj2C|)Otn@Ei-nYZ6OkIfHAnIyWoUg+ltoZY z)ADK>2H>FNLd;TXi$??*m2tX2O@>uT9;(Y36>3vKMQtm@vl4`evQ;Y3AJ$`BtPHRy zVWp@jp53B+-6T08#zMsNTvVh|k4b)U;BeZc>%x;RsWTUOUp;gsAhMYums@0*rKCF+(AeA^lN)W!)STsV_La`7P zQ*x1@zy!jT<0uqC2}&Ctb(|H+L(7Q<%+Mog4| z)_`SIRW`hc6-$)6xE&DLuJV+*<)>JFJo2N~24w*SC0OHw_9#cO)}pp$v1q2pGdMk7 z2-AxU+GX)LlCsTe6Cc)mM9W0UR738{^rb8$)r@7jNXS#B@-b8AV=!fN(8ZC@7~%^`J? zp9g`zvc0n-x}vsuc>^Z+5F4WSSGdDvP^`rUjMCEU^I{>w1RdkN=xzES-k9UblnTtJ zDxVKsUS`q|JXU5SL1=>RO4a6JjEEbtu#3=B>c$?ka@7^Ajf4{2EM1PXu=)pcvtN~M zKDwT0iL3xGv>w(3f+lVGw~~hqS=Pi$8~T||rNA)fZf`zUX4Tx(hdZk(pr)E%5U-?A*bRe<>VJ}M zZ7+klL{Gyhbg=7YMFY$j^-}Y!I zXh!S^+lLtLP+dZ=nds#eBW9CFVzfZ0Qd^y*2t^at`koAI%ESRXnO;SUEzo+f6Voc| znDHy*D+z=lP*r_Wo?3wrLu^}TY|IvQ;J8xLS`=@!1dJjbc#-5|eurAaPU%E7Y*AZNne zQjX#ZR$RY|YZh_EqDX9-TxS)NwNGsoME}KG1+1L`2}@0wgiE2zwqPp{*oZ5eUjo=P z%N@b7Q%t$65K4-*Jyk8<=)EgkIu>!Er#AT#v1)(V4uT;?&)h|tB1b6?LIG&ehXb!)Ot_*2$+)kK$Py90f#9L0Vk{$9^x7V0*-Wi$#)LG>KCbX7B?uZd zbarc{Cs--s2on^w8C5p8CzuiS$X`{;rJ|@BUai{%%FBHvXyCL=T5D{FC{0MO9#oX9 z{jF`O*ip<~scL~yrAF^R?yEU?Wo`fkM>Wt`LbwQ2U4{0pHp7Yl=Vm{(?L4-fQS3iz zY{o`YWLpb&`Cld4-hn}tyFg@bItl_~th$vJEMnAxJduh@=&K1$r!-U+Q_%z1*Ee6% z+DeTM_v@SD5_d&~JGN>C2^fM!Uslx1tGJ>r?G4Qv*TzRiyj6qi(PF^D9aNW^p|m@Q zI%wB=GNU)|dP02i1BL|a{_z$fYgi>A+2+s2qC_bci8Nsnk{xmJ3uS9>pwcp*L?d{P z1!b)jUNqkLJi*#!ul7{3O{mGf4BfJq7Q-8s9c4-YtrTh2i=>|A9eDFb7anpE1>8!n z8~bcRY6@9}M{N?uA89!>sA_E#$wtSN@=`_!5T%Nlp+-S0#)QE{rpL0OMOJeb7|X;e zyFyJqv>C25VUSX7L9O{3y>>;#vaJ-@LwW$FM6nRuy<_Dpq4D7M0lyZQv1G>gN)*Um ziKy&=S3A6wlEAHU$^)Y&Hl>OMNXkcVs?a-+Ws9fyi7JdqI3{P2COrP2TBel@5maiU zg%+$Lo+T^sNf2%Nkl9$JK%>Mi2@-}9?qkPAR(#grCIZ9fjasq+7h-mda6!!M(W=U8 z)CN=>R<^auBB|PD+1jNOr`o=(V5==|2$ZOj`r;eP5-eb{pr#&D!H!P#V3SHwp8%fU z@=UOYTlRv)%?Z|E6}K|QjZE>$ecZw~OZs4Zu7=C8w-3slRX}QiCh-Qb6S2+nqKn1! zMoT+FX+S2){vpW0a8*dHO+shH(vBYskO(g_0b88ZYc}w}9NIzpZW{}0wFy784(vaR`k|(jDs54=zgcNe z3QV}K=3_On0wlu<8SlcH#s#XzPZ|mLW{=78q?D5wig%Q1Pb?WVpo>9Jn?zjTsnyP7#VBQ~wwmc@5EArY*nX9MnYb?{w(8tV0*Taux|e9nQ`MZXg$`>$^I^!~ zoE3%HJ9k=(&zG%#R+%K$FUm(vRbtIVt;r=QGE$dVe~Vo#OPFCXTPg)xNj@1fy?7c_ zk4W;2miDpsMPPfdvLvhe*Qcg2$aGzVZe4`>9M-2~2C07I_qF-}idohx4;d+B&qx4! zMh-b)nF_R#^N`b68^tn~nE#-2bDAF%+pXHFhDYt>xk?!XASh6VO5MY7t>aM>B5T*b zSP=8r)u9_&O__`0IEk$(Ay1LozoZ5pnaQCuP;WrnV*eLaw)d)d0Mg0Ygo1EtYp?W? zPDx%|-|4OQLNSX=O{@57f}t{YWi@@$PtizA#~PzjGp)tiJ`-I8Q3fy=AkpfpQDE3% z5T2*U8$I@kh=GU|dopz{ysQZA&oZ}Qc`$YuH|4;B8}p4Db1*fH`C{Zydvd~R`>u?v zYB!1ch3FQ$2JURNZcL0ZwbNUq%4KC=T9sQrtL(*+opS2-=hhErxiJla71Qd-tYSo| z+G7E%NwP4lcKs!E47pECI$FDVd_3fSV=p#vN>AiU4T^{ z+328t)r|{12_3Xp7iBS{<&AZL7V82n*4zAxdB;P|Y_z`0ZeH~OX{^{{L%7Eyrqmkg z9HNzq5?X_qM`FM0ZHVZ-6)e^o5@nst#zcHU^X9TjulvgKrqanR-}qif)m5ySo)Tkv z_g3sS3Cbu0lzJ9UZRaV6Va8Ze+li@geLajLow_dg|QfNovI!)qME!o+FoWys1Dwz*! z4arBZVDr@iw@}Z`)Z(2dz%3AHrlnjlwKA_efi!)CfPeM4O8%}$scXx&picP-_|b|Zbzdb%FIGMp+i zuRH)F+69Jf_0#}VBCVOlpW4Nx+6xjH^&U#F-)i(0IHGrVRf_) zVDVqxnXuQyDpz!AF>x$(qVk!d#v?>&`JOG zW?B8F+JpGu)k$Zjrwxd`MOogKC~sPpH`!Vrd82HiJFAad&Ly6A^>L5yBFdduSU@#~!DnZHXtKV`jRL-Gao-zQycD^AZ#x~*UO_~QQRKZ;r5FH~`6t#h20 z{5$*k2WLYpIzRSneegWrJM2^ z%=jlceuyJG-ox4ZJl@Nh@Ui2aoW0NE9i0guJ6^`w`@Hr4T67>g-g(^neBwKh<^Ik- z=X-~?^3eyuU`XDC~~Af(*JBYpZKw(S0?to-n~@n%X$a9zRIrt1zS7@yD>WMz>(b; z)5krwk9%An_k=#~Bm20I=;NNm{|cmK)?l>vsR$v(Co*d=+P8E~af{3vjP~rOTk<&= z?N{WBoOda=X)L3AymCA79~ks`5ln;89yib}Wj+|~?@G}6;HB8=P3{t(#5)-6?NLzN zBDV&k^j`q2kA#=EsLOegS%cAj{z13Mr@?3+d*~MVGuRkn{0hn^58pu|MfLk`>kRyp zsqyu{Wo))4iFh7JAF5?G9@FTlPgwhK=}O$^Zbc%mp^=%Ub|-EGqK}#~{TJ#{ED~s~ z`Zz$7aNqqs`fPk#fp#nV14etX{;0RM^s!2IqfC-!>$lk_p(#l}748rouixA+?we7z z!rO%izn<3tMv`0pcL8{;eq(!5ksjNUrs;pglr&wprKB0UcO=chKgN~tGj$un>jBlc zk%WdfQT*|${V78H-{KVEWX6XI6lstIO0N~-fA1PeIfgM-h=D|14}WRXavo7A7Lz4p zHMx*%BwNTc$Tg(2VTtc*auX^4WkCF2B;O?eManzg<$NkRfXpO^lVivUrm@+tCp@@4XM@;&ks@+p1$#co|TMfJr$GAhXDkWHvd8%p+%z$B{m=oD7o-$y&0JY$I2YXOZj3-;*23YsnkQ+sJ## zt>lyBbL30pYvjA+-^qWF|0MU3Ka+Snr0#EI204^GoSZ;TAq&Z)NjHiALapKplJm%u z$a?ZrvV%N>Tt{9+UPazO-cCM1K2API?jYYHKPJB-cauMnc$K$GZ+|k298DfU=8`i> zH#wIKlZ(g(vXwlY>?Svm8_Da)o5_2~hskZ^i{xwM`{d{3cjS-cf5=o!N2DKQki*Gr zaxz&&9!vVkAUU60Lbj3TlIN2bk(ZO#k~fgIkav*}kdKg0k$tx$>h;wfSgY*BhMqRAa|3~G5wPG9GF%KN0YNiKY22_nmnJpfxMr5 zhJ2m;oZLq`prp%v#*#UtpR6I*k(ZHglb@46lcO=cllXGTxnvF5M*g0>hPYd{Si+kw24Z zS^9pX$sF={vWl!FJIJ-<733}C!{lGccgb(a17v?pI3%B=$f@LUWRP4;o<^=AFDGv% zw~{ZA?~r>*`4?!a{g9K$qse(>9eDRke8D;lUvCb$al!E$)Cu6BlUepl2gcI$x1Rxwv*?Q8_CV& zHgX5~1^FYHf(f?db0|5HoJGzhPb8bkv&f6d8_4^~XUNyd&&hqH1LiDMPhuI$m__v$*0J_k$)$5lQtNw8PGP0Argxo|vME;q4oBWFGA)RA& zyc5U*axQry*-V~A?jYYI2W0DbMvw($C3zy*Nv?(RSxKHqc9NHno5+XAo#aR4k7UYZ9q&-Gkeox#C!5IC{ zk=w|f-&u+@i?}+ z{|V&D`*U9h6pUF(OzTbFq8tEr%$VPG%c>#GV`5^f+ z`62mF(pjwUa~PRJ9#5V~Hj>@sCh`vQ8S-`Vb8;W)@UWi99MVrNA=}9F$!o|v$j8aI z$96CKKU(~TB+}oMNT1) zB`e7&*-oBI{*kI^JQVmkg0-lNXYI zAnzrgBzKa#$p4Ushjsh~q@P?!Hj-zO7mzoTTgZ3Gf0BbDI^HA6>EvzX>*UvDTD1;8 ziL4+`A-l;-$m_``$d|}Z$o-^a9^)mCC#%WLvRtyhm(`Zd~zn~CFhZg$R%VW*-Cbi ztI2c8i^vKZE+m(c zUE~__V)8ojc5*BEEcq(=A^8otpR_O3>C7OHCdelxXmgwsvkSkYU_H_X9k?m3*B3eluT;E8pqW@Xs1|j0TQaBv@*Xh2W=N}>;qyLNKoAiH|{FeUzru%2os7JggN2d_? z86rgbhm+Yt-1kT!!WGefCV4FV{dCVI!(a+(nF9!-|f zKS<6e7m*EQ6WKwoAkPt^K7KD8U>JX(`&OR6le~}qPtd)Me1rafr~7kqKmC)IB3|S- zg&ZiveX__2^q)k|5h6Y1!cm5CBHhb){#3G^{%6wNO`b>p%jmw6yjzI)9uT73pQZl` zG;xw$Y%yQoE%L~5F%gs!v2OahwgHouOh4IUrRS$ zuCL-fmHwv-ofwbk-pKP;k=N1x4sxq770;>Ay;F#EzDd4E|1atOhBO-Wbq?|{A+8%i z9w9`23WN?kpGbEF&!0ffqyG}Rmy%}*aorm7a{6CQZWbc`dxeJ?##3~^$n!hM*XaKt z-Jg*Ag}Cl#a$pnONPi}oEyVdF$r8k|h7j%eL!SSN{@;@Ogh@?G*n z@=Nj?@&|H1d62Z9%KQtF@5AZNCMT1*LBqr;x2A{&kWHcP8E4 z+$wkUNFA{w*P{|C0XSkUx<7$%CZ58R5|$(uBBv zkPz38rvF&-C^CnfB}Dk+ga|*E{*`16&oAQnX8O02%jthM-D}9-3lZ<7Jim$lH z`r!W&-Mh(s1Ui9DJ-jyypK{lA)AL@p**kgLgaN%edluDg!z z8^~M9JIU=r=%wm8JWxG{2fj-GFUfDn-Q+$p!>+H-B1e%fGKVZ6k0y^J%SrW|9q!vf z_X@I`Tt{9^ZX~ZI)$???{$9Gbkm@-)_&-JWC*&98_v8=cPvoy;da};nU~)J)npDrj zA^u{z=aQ9VHMxLP&&45p1Kq1g^*kK>ucrGtaxbW(93)8)jJegcYo<*KVZXhouuOK&(Hb8UjqD`P7UH_Kbe~UNOl~CaBOfFmC!Z!?BzKT+lkby1ko(DBNt;vW z+a%M-apaL?E?G#b=kZXk$IOMXcHK<+1hC2jrmbwkMEP8@){xZ?M>un@;34Tax3`~`8V<{@;y>LSBdz(qWc$8UiKpQNhSM}L&)LeQKWkQ z65&svyP7(H~9?tXL1L*lYEE#fZR>)Bh~YsNasPiQy{A) zpZ&|*-fq^FD0)auOn|DA19wCUm#y1)$^uE|J!tb zL4HjprR)5qkm=-L@^CVnJc?A$ry}0zbRSJd$ob@AvYu=v+sXChh2%BlCQ?1;iu>G4 z_v7T#*vMF>*WkJh_A1Nq$EDgZ!C1NDjbUN$PbFsh%^2dlcQ%N%g!j{M~f> z$OYs{WCyu|Tt}`aFCi}{?;`Ibx0BD4Z;|hj-;uk?f0I9xg9hvT3?WC6F0zQ6Nmh~} zashb~c^bK#+(2GLLcKJSj^g`?FzyZ$H^y_95M%X3A!L4@5He$?5N&ae5NR$IV%}OM z#5jiS5o#W>SO~qOQHXMH7iQx}i13(pC_?>Fgt%2y_s4l$s@yJeJgL%y^Hb4IC? zJHR>OkNJR?ROy4eoNg<9i|AfV){`o|2;WS%N;lkHbgv}OB-fJ{l9!TKkT;Syled$1 zlaC6K*(b^E|*-fq^*OM2Lmy%bIHl4Yw|mCH@S~A#4dtzOeRe-jm#jk$YG>G*v+$n?{dXs!t2zm4&`H2v6=?n5}A>_h$@qJxI=0EY0r!8IdUmml`*J_&ulbbEh;uyM6NQMQi0+v}#O0;CREW4Dbk7$e zJ@s@q3UQAvx>pL3zIAl37b2ZE(tWcK>Aj!shlEJ?n{>Y`MEZN^R&vIY8%X~Y=?BP< zk<+=VrK@%c*wvxgXdQLo1Mw5uwq1Q8aZ`sE%J|t6R%p@QQLw*?odTeZ5RG=(URp|i1z>O zN7gyegbdMJDo2pOWaB@yQN8)SZ`@ae|1!4N$7tK8ON#@b9U}Cr` zxLrIau)+m#oEWYh?kowwj}>kS+==1V!JTFW0`h>d_ZWq4R#|n1|JQCxRemvd^ z1X|&4=@U-+cgAmod!|pgFW_GH8{wXUAHAH-WMzJKC4F}^3^*l9(^aN_(1-^BR35TE2%(g*Pvi_d}U6XTO{ zZxPO0A1i(GzRSe;)+MA5;x!iEm_G5zcqQ*|wLVsSBm2a6VM6*Ko@4P9^@;CBL~x-M z8N-P)uTOlN64Ez>;iNwN2$$GDtltx8V8B@O~VUItI%L1AEWWL?t5pS_;OGg-Bx6v6`!mpCdRjD znoZ4_Bt8tEvG|_q6W_gv&t(a(g!mro6WiS-tC3` z+uKXTosnPIGbm4o&&c2TjgcpA+p6of*e03V@YYaQ=3=>4;*#&~t$%59_&3}?^uee7 z&HfAhPk%koIL<%t`Rl=T_&$m6z!x^*_hNkSYMSZ4rsUhEvIjQ#zgJ=JhOdOZ5MSs0 zyPq29|L&`dt?Tdq*IxVDL31;XIdMy7E{Aj_uNmdd!TG4`le8{0IO2pM&Q888TEE#$sbm`&LI&vj55lgS!tF z+FZluChhujTKTRaXI}5O6&eTZKMdZLHn3;slLs#RCA%?wPkQ=udtCO--=^7W2Oub&dTiN3J(qBSwdexgBr!Ow6`_>#?6`*nhmgbK{n>b6;9KU`_i| z6^sAzm9eeo;K6f@yn%B(jZ?qb?MZ8#+jw%5z44;PF$dQ5Z0EPXSqMLhCx;OV6wmo`o__bFXja*~* zecg}rnA=C~Gum7`-}%M}J<`(;Auip%xn~p3q~Z8_+~GXj;fn4*@9keYb>QZntGd_r zY^=I+%jTYIs-E53-!~Y3f2dm9bGZxgoHOFJei!H%x?Ml4JmrC>4_y485$n&rVB?nT z-D8r*6x{S}deX)%gFGX;&s{UCZ2LF%BE$96*Sps~e&(-d9_3lvbF1sXhRr>vF%KgK1GcWi~kL%LB;9vJ9H6P!I-{GkT(tep5oN~bV%WXfWof+J=8RzV74?7k|)r9^98s z7+sduIJ({57(H;|zq59CM=xqz+w*aI*0$ij?$hyIHUxgdww3I*rEWCR-@3^t-Bz;C zI31yXnJ-7n?lji+{CzuocPFK8+Y((PrF+i46YhJ`e>&>W<8_COPi%9f8NE@lBxCKz zBR$3(bB@%j)T%MzrN;j2%bV8J_G>yZY5O;+A^Vv67R|G`k^oTSEkwq$nS)RVFO zt#c3StXsAD+jRSb2iERA(YdB)XWnH$rQ{it$9~XnwSCWG-(XvHoLZK zEBrm1sS-<$MfZ83UWi4SL;NJf6DYbGYN(m2F$hBu30?HFRlFO$2|KC zk7xHB`*mBc@ULAn;VU`DSh7vphH4W+$QspV#l2CaNIFxq4UTJSAh@b ztdPdoadT0|8M@>WLykHm;>XJtJOM!5wqFz2Zz)A&qQ%HapS z(HSt-Z{L$)tex{>quulJ;+GrOq19#h+n^o(X3}$e9gbliLb_LN?72IyZLeWp116oaw#l|J^8qdG^UAgtAwCz{SFs0l z-kn+>yBz8cTYGMFZSA>f`;|R6XKdWkKh^$inkUmc z=D>yj`RkU;4{Y9h>VxP*zdX5T;J`Y+^F!M>`+>B**}LpXx8OR&vi+&Ap4>BXAkJi` z;Z8|t-8sAL>9_RU^vS=zvSr(M+tZT{r2jB>SCVbiBK3dpx%NJ-&*0ZqSO@*(n_|OgIR?i51O++Cma?D&I?NZT zuysuy1{K>#vYE?V@H!2;v}4AwGVw}slr+NY{8QjHYd9Y2f>-KsmGDX`fmg+_)5I&; z@pC7<&W7gY2o7JTyi#{h!Wq*s;%uCG3E6Qp4ZmK_n5mD~BWcMF`A<$s$*I{$m0jMO zm@+JL3IaGD#7~O!DEkUb9a3DG$IJ1*T{s?}6~eLOE&QZ>D!w5+hnO-Yvq3zdsu}jB zNKi^%)=C^Z#8{PLLV-$=Bl|`Vj%H_V#Bu6qD5t5(cgtZ}`c)_cbBk=fG#^8*Y-T7& z(s}&}xX6?@kR+SGE zuA9@3!jmKB75E)!)}U}QOnEMEkSR}*4K_PaGMVP<>97=-Pe6$qVjeRYZvr(}9D#kH z=G};Mn0Yj8al=h{Ti*!ty{U#V(p)qPt0`tK3hi+7Y!u`e^JP@8%N!4tbgcPM7T#HE zPDIS(%pK*h1(@wMhB3h`L|xaL4LTSoc-VU=6 zDS5@5jbi+pQ{I|0#pXO2)iTxQwB^Cf2UoUXXzOg(1 zvd}Pg*`2ay{ad?p8>0Ts?yQ<<82^OJYZ%|#owv@%+`{fm4;sd9yYtFXhOx))yfg!o zkYuMFiLXd@7Qhx&ne6;4YCo9l{2rcF$3&9yLGNIRJ&VAlbPJ)6Rv-&dwI>L`!y_h%U7#+1Y+N?5@eq zS8?|&hqDs3IK<(U7mu!VI3GiOt#UYTTWT1q9Zq>l^h1a9Xq3c94repk+{X^*7?j}O z9nLT+;1h>45BdAl;p|#0d*_^UQFJ>~opmrHy_V{{9(R8|)%i9m;Eh!0;7Uv#Ql0r| zWpAZAe?dcfJJop-j0EqbIzP=ZjCWI=vikg9s`F7Fj2Hc#BT%f5^>;pe7G6W$-zhuw zpXl$r3!XO)bhaF87=Ie*oQD2=(?I8GXBx)lfzBV0z?%m;{{Yu51D%&4fwvBHu0#J? zpXprDWEdMVoxdPS8Am#kklaB>I$y?Z+lM;y5%RR5PI>ov$57|-X@=1`)OqkQShI&Z zC!u35AL^Wm3swwuu0`pdKGeAbePQKLXCczEYN&G$TEXg}&iiW(MhSM$#KDPfuEujZa&UMA8{gz$z#LfbhaWKEYFgD7;!Yp)RIk;&Ay0ILLN6c5s!HnZj(sejE z19@022S1NA@WDYfWSUJ5wximURIc_mP4i?}R>2mN-Bx0Z(Jbs2u5%Sp; zQE913C>O)bOYe`iX384~4KoGfhRqy~-z0Mie(mP*_)RuL_;r{K_)Rfa;y2a&J$_B| zdi*-gBTz8?%xmN>rmSG4ncML@z89)r9%%l8-wd-2a>ZrJ?%lEGsmOh{dG}Nq zE5<;yj5nL`mWv7IK6H{JOh4-UNb@Un`bp+OwC1DC#znA~n5A9}2IgC6EP1B96+Yjb z2uV59JO;nB%q{3d$C&dF+iY`ErU8}k^Z>e*c`1I2O(!bZV`f9vc+F$*>oX@GgN|j^ zqJNZ_tMOZE?g$!2z+77h`;oZ`zh&lo=+Nb+tk6}M@_$?^&3-8Opg9bwtupiRdxBXG zITSMg-2}O8Zh%~knDuD#)n*2c=b3MzloptOLTVS9f5EjUnjhhJk+~PYCz;OWhHW%#W%Yw^3p3?QC5b2EBmz1h?(3it!5gUSf_axN}$Vp0Udq0xpD})vUwT8oNneKB`eL9 zv(dfG?@*ho%~Oto7&C8%$T-U!QU&Q{o{5Hhj`<=QX1BQk<-f)ZK&GxWyU^CwnZHKR z#my?je}Q=wO6>RM7NqRWS#&s@*zx?k`2^}g2op8L#Mg&wujJ_B#xufls@on3_ zocodLIKFE)$8ne4569j152)9Bc3bqxJvRS>%KLWZJS=T?8IB*=)rzpN*`+w{v-$mz zAK6#nxZkc{8H<{I3^UCqc15({r*<)p2kissONZ>=a6D{hVRU?E*T(UPJp<7`YVU7| zmDIirz5PpjK8|16D+k~{r~N#R$Lzg0eq(=+xDQXh65_Fag>5B49h_@i9~ zthNr)c_lFh^hER-?pjh;fFF+-wK#OOf?Qaw5j-zRFPdB5l=bGvb|#w-1D&&yseUfTKGsy# z(dB!a>T&eF;ij67#d(COS`NYpgG=}^(o`)5VvLz;TU`t?Qx&(vC^OaP=n$8i>KBZR zF{V;2G0;r)4Q7)oOvNvG7-y;j7#9=aXH9<0pw7pSIi@N?H@gmzKz!$#>V8!7dQ(Lz zV$_)G`D_duoG=dK##DEsD)UV>98tQ-R1afd-E68V2-X5qT~GtN6;s`VQGTnb_QC98 zQ(fEIFm5x|oQz@IZmOGNST;?y3x=@st=Pxe`4(d!VCS2>%GvoIMvbuLja=z$dHJj4 z*z$gRv9skJ3U?pG#u@cnVX6z!iVvCU2Dr4+RQ=Eu9yS%fvuPEY3f*!w_QB}uYakuQ zuF6#NeE3cVQ{9On@wllrq5;-oi;W5DNmJ!ue6BN99FcemA!vlBE={!xE^RQ?j|k+` zrkc?V1KdIqS$_$sx^MR zg!aRaZRkDt@v^BJcE|8HRXhB6)l`GdSenW)dS-( z3z+J+DVPRKbwv-%1ExBOf%LYi7LUP9V5)ynzjsYlIf%IcR|^ULVwRfN1hWAGQh@0I zS0HGIPfWEeWf%wGHF^&|yU?#G#udflFW9Iw=ivfi{xcND{VfZ=^grY_czBVvC*GmVojL45H zaJ>NA$mx&0o0l|0P(*s3m&Ri%Iem=qjglQOaxOH&^Cjswa@rf=n7m$X82<_Z*HvRHAsEp=Dm_P8vQeTz&p>(<5ziw zKlM&D^BzL*!w0=H&Ag|Xd&oQ0%zKJ~I_#b6%X^WzpLyr{^5X50JmQ_}%iF=+qu#l` zid}o7Sw1&&=h0t(-h0gb!p!9(p+5)m_{2{5OEZ`E4Y0S&=TFwG(mJFgxaEQO`3wjj zE%jjj%ScnMG7I6eD~p*8Mq8l&d-MMbE07y!AJ4lA~<(&${dg~ zmJxiL*#yp^%1W%gSye00oBXeFuyQ?@Aa|0b2po}WlH)Ui5xlnu{{Ij8ufxhX(Snts zlp)CW=_)~01%oiMW)eC}K`?O?WqtSqQIWNnMRhd~VC{%h!#t%^0&FAF0$o8@7Z5Tc zji&(A5D+vX*CS-QrU1)`6ea*_3&7v!4Wb+BIv((uMx=jrfVxrw&P08>V$f;@ALBPB zkyj~LnLfs^!Kl{tf|?K2V#U)opwopA#0Gjkqf@C&73D2y$-&V1fVy`9mz>`bq%^GJ2(< zCkjB2ClX8&fFMsJm@EK6#wuy(DFTo{kS_{a(-E5ZTm(&D>;;)$0;s13HFJ!7#_}e- z^MZ_Ce{E1b3xILd-q5qXUhjvOKVu%$^JEy%f~ltmt&eHpN?N$u8wM$?y?RklQmFVXK^SA(zh z1cLDDO@j3Te2(Jkp!GQwA0C6eM?J-5SV;A=m=KUd#TSBVT4g8>Z34bkTtZ*H8M`UH zO#u38D^8TJ3P3O7Gf8^807RlaOS~okk@%4%b_hTu0#^aNDFBgZ#o6vH0d6Fo3tIQX zrT84IzIu!2_cpfR+d<75(eL+zY7?%DBD1h`=?_GJ6B)sW0yvQo>=VF=jNl^yoX80F z3*baX@UZ}dcLo-7{fPjKu?;M7Kmf+ra|E9XKyy@Ky>O6 zd?o;6tO>yp0T^S&1V;rRek}<;7r^)h^sbMC-0kJCFaF<_dvnpK}{Jp$nQbb znF5mv!T%^P@N3W-PXQbF zmeN*8QJ&~8?8jE+pC5n!P zA~Z$8cqqF*oN)ybB9P-+NQwnlFh8Vvp=|s-2EDQ;*p9=uS|~zOv}%W}%TTC*ZWd6Q zR_cb-T*nI9M4$KHdY9^&A!`j)cQdbcsL~5e%x;B5gOKLmICJ-FoAAzQ$^s+E@)kip zO}%$62NP)~q`n7;v^pOO#UXb?V$(NMHw{@)jNkaqEaVl2-2F%I5lEDTG-bH|XcbZ| zQ7ET(-(J{Ocmmwf^x}-xRzT2EY#y>MrQ#=;ymSjs@kiXS(d|Q;wpjaaA+-{3BVXfc zR(B7b+w2YP2GCOg2E#h|pnH43q|-j#DP-{?E`ArAu}jF^hHV>;M4ynRahezuQhC^> zMVjJbS`YCAY>e4~swhPlPmWQE>yhOf@J@prvO-0J{wctV8=FFa8k))_Ve< zFg%+=n$i^5iuR`ff4@a@ zyxM~Hr&otKN?!21Drktr4zxdV=+(Pu{}jC9UnSSOMF8#3KTodT69BLHcgpo10q|-( z!TSQ>)e3^W0^rpef)50^UcHI-hr#$UdiA#FmBMaQ??d~0UL6dncy)MHiA&F65r9{x za7C?;2!K~dI1PRw05-oN_)-A6>CXgT2|zb38VGPq0LFL@oBA687;g*Mbl(cVy1cb5 zz;^=Bv+uzz1pU1LR1>}6z zvGOgb{zIlqDw_J2khO%08#s=B^QOzYxXS(&(zHcI(^lIYMOyOP?hMYYa79j+K>?%h^@|0u^Y`+@B}cW(bpM*r7 zttm}`0$a5~p-3YNCp`iFJ#YwAvaL}R*vyVt#S<`aqON9ZN>iYYt*)oQ39Ll=Jn_I4 zs9{@=QhSx5^r;QckYL)W!qgt@SEL{>1|N3OaMAi&shL1 z1fVxGoCwfL0OZiLP4KWuP1u|Y7j!e*T~x~IA<@p(^oBOO*{U-NMV{ooxx4M|RygN8 zLeN8itJu-D##6E9FywW%-3`>0?A<+WO)VXL<&P)31~)=w00@-FcNZf}Hwqis!THpB#5g=;||k^-M34S_tg zgB_ttL=l7^^nxTvvz`P;rhZVljW6%hX%}u8C>3 zwUj2FXpg)Zo{72ayVu*A#%W@qt@hAFpYy?QwY^&?Xvqb*{?vB}fQdT@mI&}UwU}>P zCuw3hYksrs+=hzRAC1JFwx)5$@j+XS#{HGZotJ~J@cIV65Fv6iFQisUXTj95nk7~X zz_@O}F7v1WEY;t)26#*WHtfT=&v{$`EAG?FY-W<#hCbvEloxV$^PH_|i;COO+;yNhg7fh!A^^ok z+^}sI;3__k_DA9PSJ>|B7d^%G=OMAf*0jaQ?Xp$3x==(4%ZXGH1Ce`7y+;5-$$qWh z7l8Ez^EQ?f0a#yB1Rn^%T#o^W3p)Xr>zfkn6M(rM5yOR@0F1>p1p5V`W?cwA7JwGq z+y~$j0hmW$AvhoaP1<<`z^4Mxua2|CK>=vvKL`#9KpUHV0S*g*NnDh@X`HJ-0OHw?;12t%!{uGy)-^x~Nwgv6h=W{#21 zSiXmM=i-SE{=Nr@8Xea=o!3fD$))Is!K8160W#x{LUYu?kDa{-s zpYeSd@1#XdU8K}*#xun@m#A~M*bOwkZYjW>!7iD!s;dtS6{a14)^(=Rl%@ysl&Xb7k-1#( z=c{t}X0B6KR|?$J5_#7vcXMNLfGkj&(iFH|sZnPImXsG*q^yM$SWJP%oUS+*Qfx9ShpC>Sb(O#)Er77^3Qpe5;JW*cY5oKke*To;8z#30r z%wQzeDNSh#JgZba6mny*sl34dl+}X*t0?faC$J)k#1^F~O@Wt{8hcjY)$#%_D(f~1 zJVAk%Jb@GJNUtkRX$rif)Y`KGyUGi^p{(~Puz><^c>=T9hxaH=X$tJe{C8I1lkx%| zC@b0+0-GtY&l4ENO~^saf1bb>nEz17jloyt1wO<4M}ch=IO+*B9)`p>nE#MN4~{D} z;jF+fjMhR$-_B+dIA^6kTAlU z(i8}V)$y|eDqOBB`@>cqw(s%lIO|wpw<~WgMj|V$DNTV`ST#i)7kR#;P-0u93InX>|o$_vyD zTl*<+F9pu?1a{y`TQ?1BN>iXDtbRKyP*z?b9kwcCXBB^l0!5y{@Qz5d2y04nLTMjX z85D}-js@=+K0EDlLTMeg22ONt28_z4_ zcP9e$^MG^9#?%*tE#7*L55vtB-NRE%@d98#Sko32FA1wR@HVGkzy5|E;kjfZ4=xQ2 zTYMNU&Tn1S!#sgo8P!X}n$i>)8&)>f0#{&Md4W-3s}b_zgDG&iC$O5`YgBVSS>s&aNU0eqWYS!^*;)%=z?>ug#Z)Z zUV_BjuzsBa&cg%5&gzIK3|Ky&RzExk(fBuqRn0<#{tQRfE#Y%l%hqgwg#xez(FBVG zU<*=#;8p=yh%J_eu+;@}@xkmb^TY18r(PW-ZVPK#X3g#nt7){k{R;49;eywJ`75cB z`Mf=IpI22A6s@%+Y~4@Ace^6*PA^s$@S^bku%<04J`z@cQSln?SJsFCHZY&@`sh&) z;MtZ)*C_yxNeOhZgBHN!08P;@<<7i`8 zHAf-m6Nl%@52FoX>k^(HPT`biys%8;{&aI#Q<;_67FO5dt@{DPD_*DfZk@akwpLPL z-6Wi|HSAuhK72J2+rygDbl{z^;%|IJ4l&-lq+zg~{F-350JNoIJ>C<5wmgGgtM>@N zc5-QRfcFJpJNW>?UIExnj=UJ)0|D4hE*uWH^DHJfAOJftetD<D6SX>1t2u&mv4lvBM43WQuf)m zyaq5YL*h_aGqQ}|S7FrzpVme`x)S`DC%^}&s-iFI9|WLgr#aYv5db&&?P&Ux0N3V` zu+<-O@jYBNKlf~o;XHFXtmzGH2DLgyn_Vvex3xR|cza=7HvsJc6Hcrj50E7#&;ZML zOCusB;MHn&$f%S+c)za&5R(#cGl{OM^P~iV_jf;lN>al0+te2Spn3e-naJ~NcMP95 z3W>^EvqtQ!)wQaJLXrE}f;DxyIX|JT9uzn;1bJ1pJLg{&L!z$Ml%_xvt;SN|Eo>%q zv+@G)KKI#^aR#cN1{k;O5=Gr-Abz$DKMLN-rMK|AE^r9w{0TFqX6wZfac@n zM00H&p<=BW$ZMf1vvB;r%aQ1yHEkKWUz$1=RQ!|Q2|jRSB>1$BFTp2l{0TlL6G-qm z4m-i?-mKWyy>as5U@j-G>;#`5$Vu?i_-KNkpywv|d30WapQ2Vy@T1Upf}dw568v1S zYJ#8frDDtbL!(hB_F@J6T2G9Rs_Dj|*w;`Tp5RAwmnQi6+Q0_(9T` z1V6aBBEb(z#wYk`$CU|wLNO`9j~S*U+NAKfVIq!zO^@*rH+|eyy*j}g&@&U;aJ)9b z8@;m_=*JQjV8v61+TnH1=&7*Z`M3mKXu{c!F0+ zYZJWGSrVsH{sX^fwza8?!SOca8yLkr_+{_$Ga7S`D!EME73GNM!B)E3} zoZxEuYpj@OJm^~ZEy4BhM64~@Q?AO%Sa+t@hn;%=p5S8jM}kYvU$K{%^SWE^@7SA6 z?Fh%F;paa|t|=?cB&WtzX5I(PI}?u8%H@N@NlsoH%)G;-aqTESV6Mt(aSH{s>&`e3qtO8o{9d7>A}H55TC z#v3_-HU5vu2e_$fDkW$VpT?xD$}M0r?*io2gGu1{jRTNqmeMrDHSGM9s(>{&@+Ahm zZkal_hrD+fKq~=Q)T(QM)&j8axDz8sw-JCQAdl+_;0r=FEdjZbqkJi1r}mGO#q^^98-^;E&$Q7xMi9l0MThP z6W|&Fh|aP;05b(3I+KzB*9t&%KE(p6X9+-b<}skN1t2=xuo&w(0uY@enC10#0uY_q zm{Rpz0fZ>Z38;u`dV>1|&&s z3a9`-2$l23o&Bmli7%@QjGptm&OXnR-yddp&Vj#UECTiRp4p;rq) zZ|R>8utorSOP+HzDFD6Y{Q{JDOaOYzXY4JH3qWrvodxiO0Q8m^n|Q4N^p+OW0iG0q z-ttX0z*7QnLDN45@IL|UJ^{TTWj&3k#J3Db-oli-q20i7x*?_6vDke!rxfSY$Y@S1 z&x-)M&xNeW3j)x6cCaE_1z=FX#Iq?YuN_R}b8K(&OoXuQ&@ZPnjdL6SMoP6sp~$hx z;BU#|fzY%a0q~B1ptG91ma;}u(aGE4ttL-dD7ZVNX^S($$0>CK6>pmje!!bjRLGfd zKTKJVQJ@Br`Xg^ji48^KU`kV(wf-ulKA^zt9^l8kI^h>(a=P}#=Vnqzbcbk4A5B?* zP_QGN_##!A`-k{gw%HFU%^V}225l^j&XO9UffFg!5g^i+vH1P}82Iy?fyiY8P~dL? z@VV+-Q~#W@#^LPvr(BeNO;x^@iAh*2^y!qIi-fzAA$Ck&f?tKe`+WLv$2pigH=rw~ z)YlzwQNcZh;a-u{O2z&LiYB?}8)lw!iIGk@TTIjabr_vVIr}u9`};4tC>1M3;eeUs zDxNZ(-+R%$+(I=>=NDac?^NtO?D%S7ABefBsp?`~X_>$}! zbA5Tv{`#j>>>bdRz9btIzgg{U;eJN|ozS0e1Q}n8z{!ciaVIC=2pV{A5$OM2i^G|e zpRMB*E0JO$BUqQk2+(mh)=}5tUF1B@R?pQrH=TDR*dhQE?RDHBz92xMK?8b29cwkt zj@QRQKU2pY@-+t{v9*qF3rG{M)lq{w!^BD|?i2xx@W%+=5P$_@J;9p-ut01gcv}G0 zgRKPb2*7&q8o|2);O5%|y98i8c%NXm0IUbsb28f_0Mq|11n&#L^uL5)uK-N{_Yr&` z0Mq}&1Rn~(^#26GM*=XpKTWV-04Dd+9Dq**U@mV%a6ka&@-76Q3c!Tbo8X`T%;kd! z4hg_qKAhmN0PY$IJ`;esd?$CFM+9Il-^db21z;}UO7OV=v>6)qu8w-A3mSF=I)nZ}1TdG6A^1@MT6!YEPXf@=(+Q3XKugai_*nq9 z0yh%;A^=Ulh~QTNXnOvsAN`vEH2r-9Cj_ABR}!2QfTkbF>G6~RH2oz6e+WR+Urz9+ z05ttXg1-cy>30+SBLIu^M+Bz@;4auqJW?3SDkpD%HBLE>c!vIkM2)RvAQ2;_7At(@l z2Iy)}=M$VK0Apz}L45%jOLr4A5P-3?oS>lqjHNXMjRasUJw?!10Ge$R zK@$OJwwDN+3cy%u#Hp@OfZLA2x)#6IB;JngXxDY;M2nMWx~^smvmKk)RVyz*JI-dv zTZ#a>{qPw8tpy-{V+h&`K>QLMg&hQ-?zIRy3P9Z(5_A%Px@QPF3qajl5OfiMx_2Px zDgbrwPS8yN>fWE=0s*M|zXaU{U>*r_f7?TV8;s(*)(+G&-i^U1^@6eXQY3oT)eMu7 zou}8=Q9q$jf(wz6;93z#aAL6&?CV(xMk>Tb#Xm;}@VF zDfBM!;m3(lD7RVw{lFu0g;oy~jvpV6ycLD+Ww9@X#F|3=Hw4)z>kHL36mr+X4Ta~{ z!lpI~J}m%)tAyZL0T?>12sR4fbqc{I0kV8<7J$);S$1uq^##3hmd|yC|5-ktFVysx zUcFMNM)iPKMq?;$_XK!T`R_&muM2?9-wAdKz=h68UfI4Wpn{RpuKfjAPX*xD$+{A} zD*(S}-HBkg0Ml`EYoW!DN8@SETH8D~Cl5wqPoZW7xa;0us2)Y3oB9Un z9~4^eP+%&@&%Q$Umd#Drn&^Xtn$i^bvQQnv+sKS*;9rY?

    -pw6c0apl(CteeMa2 z;U`Al6lzMdL;PH*x}i{H6$}09wLd?%*wYB$gmef@A1~Dg_}v3|bcQ|TheB&2P1NE= z*-u^%306enpF&OJ^wFPIi)i8~Dy^+_xsMpm6j~c7P}Bff>qZJVd9^%&MZD9}D6J_?flOMh zq(A}3e{p$%rfF*j1$J~rUZE$j9Iorqw5Bu#+NRY}3e>m~ynT6rmT4;phvTO!Ag{G2 zP9n+f96zGvwHBcz>606p$yg=8q)tLe{I3O?Z1a9H}yH8qEngWB;Y9s}=j0GQ3 zUZ8*4T0nuD>Lc$$PhdNC?E0d#rZoHB$h2Bbf%((9;B9X70dII70v?;t?DNR|{}Q+_<#W z5_0k5_y|K!NV^}-R_DYxGp*?jZQhVp*V5)Se()Q;TJu@`*Bb-eBmh(D^;ZDgEOEiv z=$&)Y)=HY_z?jYT;_@2D-h#BIahkY2t#;AGi<7{YcmjNkqVI5kJIgCBN?X5Daq%U{ zTkI)T;EjU2(werY_&{1!>kGxB`QXb%0E^tbDF6=%aDBWtZFNB5_|v>yai6DHeKZm) z)0(!Z_*hyEr{Y+o^%Eixaw_>q+L}*+>A3%(*LVV#VpY;lrZuJ6_#4yeH40#lhifRW z@j3DI&IQ=w0TUC?(=`BI@PIe*Y)D(*(8T62@}BX!$87;5wx%_W)5q7+D$oxmKAj4_ zqr8tVr>*ml7oU!+VEwA+qh_1Fk=B%^z%pVCTWGK};e0{*iIxJ~t4+G>it_+NvN_k$-; zh4ap@X-#Pg{FzqWDbTJe_}}FPPNuEN6xhbLKII9_EI{IPT2q<=!Hil=fj>&X?Totu zU}|Add>QK*3RGkD0vUG&xRR4yc1Ba00(lv=n*ys?h5YgY(Tw#Q1%|UH=6V9Rq6Kw9 zMpK#swK6J#n>dj_>Vens1Q1nvkjhvYm9r;pc@60qH33nI)=BAdKnb%R=!>xGFBG$4)OPABCnHIuK_5nyJs|| zD9|sX>Y-4i_7v~|BJb@m(Nir~_DNTWkGioda&KnLsyu84WjCC6Y z;uOEg6R5|AzBHpLO@VP4^)3ZAaCMk)P9SoUW+!@pj}_f=6~Ls7_nZ;VMpQ1(SijK3 z<(DFFtY_j{E+~^Tn#O5jW+uA{E;=I1*(S5j#XhnM6ThD00h)*rT$ic#I!;8|F)=-( z`s3{Q&}zuL+Vv;inf+sKCPL#hadRenDNW2|^WO3w6MfjL7X8P>$Jlx4Tg#i6mrQx!*UA!$|RSIZ~cJI!pFvf0VD*N8O|B2pZD4_5APxL;8 zr~3Z#(OZ(Sn&9mCkK>Vdrx(5Jp{yUsXd0u5RT(vbCN7)>zWP5V@Jt>a%KDFqxeUr< z{|pI8FR7qxR55rUd-y|Ckt&5Af`NOzcK6y|KKBCo|Sb znrJW*c~5yJR&e#*l+iTKD}t9ZDvcdoqVM)iMxS!y;>~fq_!`kX`ChwWmHehfsv<%f`29gFmVm5dqe=IL z1z?F9d_KSz0#l?mI+&}oa6M#0_ZksJ72nxV$vqK#KLIQAM`3-?B05^tyBTxcxW9VOkumIc`QXK)b0NmKfBghhf z8ynRKas*)ebOk|F0Pb{5BghqiI~{Wg@&usoEF!2V0Db2kf=U9=Gae?WA^<((LxKVU zs5-{Tsf;xXO%&&oHu_I*jNHf#TGb-W7G_7NQ>30?J5J_oU$5xw#bD$Kg8Bmd&XA~4 zWbLM+Q@B=3Ps*yo!Xoeh-~7l*sjRCtZ-dwUSy4+;+PonT6l^}ha=IUNYfS-yBDe1 zRD7JHw5O+t4LpZ=mm+Hw1-h}fck={3n}S5|B28%u3@TFFDA0j?h$rCfHu@J?Ur?Zc zVZP84Sd8=Zup&)q3XCdJ(TgFlc_#Sfo&dknVO|ly*z$E6QDhaNa6HVFX{4vP|2!nd z6=~Yye*G$hnTq`yfKM;-?i}Gx9CmE_!9!=gA5i6@FQZBg-=BJ~~>U*~1TMo)mx7Y%2y zH;JOd+An(!U}C_|m{0y?Pq@b?Fd6 zNAZOss}l;xr?4frdWy-WNbD@qv_&6x6{)Ex@YeP5QxOm!KP&I!z9Q>8D&E5mz28&(tRoUfi!^O<)%dPR?L|}~ z&!b-Y2br$0YHTO?NdOj!cL!OsG)NE{;gMF19wuL*t?fJNds!EXYvNc=%? zLI4&C{sz82DFBPaD1uW0uqIqd@P`1b33Cbl5`gixo3qm20&>t`_^736uZ?V-IHx~6Ah zOeG{56h~;BHH#HnolvNNo)^#)23wtq)nR(z#O`i zt$w}$%%Kkuv=D%gcUDgTXej`IPtX+fCQ@6q}XbPTEy#c zj&9~P+RafU+7)Y7npM4^SbaDORh@|$6VGj*>p9mG^b&xoE+FV509C!6pq~JYt9u9r z2teOjPB2ga#?@+q!2&R@o+KD50ORTzf?)#C9iJz-L;%LsTQvYi2*Bp+eS(n!Fwj0B z7$pD$?I^+J00Dku)SRw#!4kB180B$bffVr#KeGC$PiOcQ$Vrvfc<4>{h z&Bg9=yRt75cNc5A$65ZtVzre{%|mT)xftt!?uP7_ZQtJ5^GknQuNC*a&UH1(QdtH$LJSk)eRk9h(uDj@Mx zv8FTyHWsT*C=|JZ+mPqP1GL5e2sR6V(<8Vq*&+aqvzOp`0ob`L=eqfV0PI}KngP5h z06P~x0{z~*>c0Q~-n;2i<*dkA;4?+Sq5ZLxvYy9B`RAJ{0n1-O2{ zT5K(aOYw^I`!&z+yMjo(SFBkh`u$O{`jvhcvB5qT0rkRloXBPG z_(lMnI7uhI6#yrms}As;0FFr9$St-O(PnMh{KB)jy%!Qc6l;1zo4*ySs%n)hPk6`3b=v0#NbQO#%KCfCg*Be)X3CG}sb?zXhPd^4Tr^5#To1 z@nWkzT#DDtMcyx--^;nRJzcC>Bl;aEQ6JIoJ`@O+oV$#Bksu@het*r5W($Dd$A$wa z0r2}rcC@en_5;-NBHKN}Y zOVrSD@Vg~DS|t%cy#MM1P+0){?$5n@6#?-3L*5;U3xMCxu%i_Sa64Ls5^FB><0W(= z<~i|k8zhn?n(onwS|#c|I`IrUS{)I969w#Obp^nQ)9h&V1i*=H>}cl+a64M6#5zHn zt!cA{XY)Pmw{(LNO>bzkuteRAjbkLx4m=|Qu$kbPEfN5maSNbW0Bm+W51>Q4MP`|e7BG686?Fe}nr02(aCs-7fcV{6fcV`-fcV{2fcV`_fcSlZ0P(xK0N3xE5$!&>yGdg2l7&4Oo^r~Do!j>MJN=h zm;#^d31DevYmF@yYCXZe!$K?KyEAi?&`^qUj!;SW=??rV~H& z-tnCx5OM?-mslyd5|2$m-tC^i9}SVXyF^o(0xL??L==j&W5<731mM!z`T(mu;6s0z zI2qs(DS`g7inGRQ0j|^cl~{Mt<|j$yJ>c2A^C~1BEz$IbHrJP^4Yaw26VnDU;f8)~ ziM5Xcx6MJ`I!~Y>eR-xtQ|(nJ!dsNPoMen4fy$IS#U3oxB9Y%WoCQ8=FD zmg{-fTD%X|LH%k;gtn;oW=VE`D(3Ne?rl$ik6kz>c8Q`}$=6HNHB|fpNxjokEas}Q zyCgzeY`#q;)@^uOKt~IxO*0>tWb=b=*UW+cn7IH{AM^mm1rXaA}M;12w*>ZP%w@>A7{;@hK!g ze6j_IPhk&;Pg)9iK4nST^$CA8l7BNQzN#7A@Rho2?sXha*`=D^(x?1VwFreGV~2xR z76ErWRw%VLP@oBho{o6}|ErBeyi`+~0@X{^yA-&i8+gsqvyXYOWs;@VFBG_yw}Gma zy3cGZMQ_oyOEsk_(6CfxPldp1y}=uo_n=;>RfxR!qdk#V-}B(h21qn5)s&_{^U~~9 z6u5vplNP1k;KIB%8XZEn6o9b)-WQ;?01TE#>H@S8fTr%mud-+>0CDY&Z#HfxY1l)p zic8fSbm}qo!&2AbcvBw|?Mowcmrivn%|1b=p68U&T?F9Ns{}m+xN}ISQdI?0PJCV; zdzb7yY?LQ3yg~P$;l&`|oXn*9z`L{LnOiy407sk10e^20+Qq_|J zV_JbPD(}JkQfn#&E~L?$J%R7garEL+O=-s9?oxF-1wLl?xYrY~k%y=+DYZ6IpwAV^ zyVDc6Y!ng?mTF2APhc4SZ<@e~bq{wGT{ zZBg-=Qq=*4B5~d^*eHtVKHsvFZxVn$eREZS%`)!X9m@JrYb;IlV?{T3CT{3~#Pg+^ z#%bb}QZ=6@sx<@OE{g8R-&$&|r9eA`Sa0(L-r;`d^-@h~3hXLX`zbK;0`T|F2}B}{ z)gA$E7k{(V`iF`&=>OZE;yT80Z>gp&Djq0Rm9Z*C{M<|(6am+zk4mkU$cw+%26-QQ z0=?TJakx}dngU;!Dqajl6joCGtq34WJ?a2_Cjb-bR`#gx1z`Iypb@|i0?>9tSc@M8 zV0fc9d|qm8rxSN^J^IpfVkM(|yj0UYI`Mm{s&O@(IGGRrhX|nUHgc{0O8}f`&ppH6 z0^r1YO8p}MP82l(I4!_+;@48EGxX#9mMne3b7C?RXG%5QqZ7e0^%$MdeZcLqb8F2$ znot4|n#SDJYXNZLRe~%5aAGz(rOp=MI^ip`-lY?x+95Ac<}NNP*q)IxP50xA0o)%@A{?e=VW$He9buah29Yp|Mt*ZjiNdUb1 zir1Z;1-Q-8y3E=}6IVAzUR%$Ejav@7Yni5Tn&@4onp_JL%UJQgA^;P4tav{GY;jh+ zzW`Kx=V*Wd0#NbgtoVfjQ1NeA@qq%|igz!w`omy+iAG*e&#Prj3@+33mtGAoQps~N;0jUI@ab`7)_y8D znG?z?eZ#~f7op^|GW{bJobQPucK*oJ8T=U=o{&$w|Ne*O8X>)`P+fb2{GQ?cg|Q2B zaejio7LetBlgVR+&hHiGxZh;*cwwv$N<N4|4e-2|U4ub1HC-}MuGhP#3LeIpgqv24tr4HJ9{yJ>=tQa4NRdFVp-yGNR* zonLfJyWcu;e%kRTli&l-#qM{HbWS@~OA>sBxirBCk;@W%nz(s_j|8`Hzg=XOTdHM( zkL`zH7#Wk2^@LC&OO-4WUT?l*oI z8K=&}6MR&1M1s#dUh01DN7Bt1>3;7=)l6(h1%8hVA7~t(;Ddt`5_|~o$^@U}o0#C^ zc$3_30=djRbF%wQAfqx)9H%7syxmm^K5;fJ!KcTjC-{KZj0B&-x;o~3GstH5%xhxK zH-c<&&zu=^z5?X=Osq5fo|WJORSROy_kg^Saa#0N=T|uOn{N3#5_}$NX)Js`dg}g+ z(_(if_yE&g2|f;VcdR0FPP(P=@Y{uJ!G)Uzu7`6l({K*Ask9U{8Xd^}ioG&73FQa(iQT3#8T+ z#ag1=hY5ame? zAAgdc^!)2j^0O8rkmTnfW+2H=HGF|2KP2!6lDy|02qbye+X^IkBRUvJ^1f~;kmPMr zJCNj!N)<@*-eEY9Q=4Gt@D8X`N8q<49_Iy;yaAFQNb){Hr9hHb<&^_@6Iu12+%u~LlDy)M z2a>$VEePbzWM-t)@gNaM@-j0SNb+K_Y9Pr=zG{KI>Mc>Gur$`9BPOmul2<`(Ab=lj z19|*VN)Ib_JZJ|2&<=sTcX`U#Qm2=64CL)+@(Q<5r$FB4OpYs!twk$#fi;{n7uK+Y zxjv8=K%DgrZrK|Gc?K8Dd8M&58t%qGk{1zo1oAZL?XKHP0!dyOEDhx4ldf>B-U+{% ze5f?m5*_WXK$5%v4S^)L>`w=h+*Usm$ZNm8(n*vGhcb^O7 z-A;PMrJDmuZeq6tlH5iF0N-B^B)PB|mis%^ix4&ESFfKlf?S3y z0_V4_*GNvb5xko@1bPfS(=*EaT*dHF^vz}JW8g@SIl#A+6>u2|q#%#aKif#92`C(I&%6h`b^QT!2mMHyE2xUSH}FI?7#6oY>x<|es(m6zShDq z+x`XJC&#wYd=a}Ej#0Z9#|rkZK775JU9AK&fxQhAW}f{%CZ~MEe-na{-Pa$ci-p*W zyMf6Wle3pD?o)K}jv93FXkWN!_@8Y83lscL@r0fkIU&+2$3GuMt&4d=tyw(bFXZBc zZkUuJ?fr*&!ZCCt*FvOIPA8tQys8s=j1SYkESo{t+=W5dKb}GO0Iphw|Fd3@=;@E( zgwU7m&r0;knM{e75DUXz(E}2Oe`y009pLZFq7z!5EjlP?6^lOAlSN;JM?Tvg$nP%j zkHt17GR!}lCp-z$o_oV{)J-V*R$HDhvM$}zm3i7U#LaKNHJt8s!4zQGk9A@jO~YIn zvQMB2wml}oHrj_#K0>Z#e~Dwz{uRfNZ49EB92}Lsye7@8!%^EW;+SQ>jbpa`36A)S^EgKA zQ#eNLU@dlqia6%lwQ!8t!*I;A$KzPhz81%Pdm)aM?E7%6Y(I`;6?-#|aeF6@1@=B1 z6ZS9+<3jr)G)g+_LsWZK*7^PMeRx^lqQU1F{)-W($i4oGs92D-3yn!!c^t!ZBqR;n>FRgyUQ_5Jv-liy55=dv5>3 zl_0puZ$U8hWgZUBn2v18xtS);hkJ&-8&*+tGK+5Yk3mL_#pqdP7ogZ!^qa^V`TJO^W@0E3Z|1Xq_-YQUgT!0;9O!|X z!BI%Oo$oYh%?U6ac_+UTEJSPS%aC|CpOvp{_+LR~BfI=B&`yG*F|sGRjCOv?LdIU_ zy;1Y?G9*5T{sWtVnjg@EefiF)thufTiI4I*i>R9Ysv@yJU!%{3Yrce05c$~obGKPF zuMHycN&Z_9h}L|j6o~`*D_|xU)02gBeWtHFJodjzxljEykX7T`G4L>QI6CwesrC`C z+G{zf9L?u2_tnfobRwVUa|ruu{xKSfFY-AU12uocoE!NvpTo_n+2MR7zRKqxV-D7A zf#DeW+DU|JZe-<-5_f8_u zs5Ke|YV&~Fu#tj%p9;`%f3?mi`Gfyy;u!#Sx*^Ju<2f}>qPa4WU!(mNqIx&8MrU$o z%-nmC3dF7$fmB5^cO6o8?AYZEnT0mR(Q%&fay8ivkkdwT7`y*iJB3_i50PvJ)6HgQs?Dm` z9*=h@bB&aF`fQoac!!)d>@%c@2abAKGerLu(|-rUx*a6s$7B}@tV8K&$DD(=qJwm- zfQ0>IiqqLP9DVltI0o!5akTBvb5PPgiDSyPt8+Rlz;Ui>j3cJAw*28!KUKkxfbzxh z!&dqH5moj1Bc)pLM;q0bKjwx<^M_#?;hD}GpAo*zc@r?gFU@3@ZG>AD@J-YR_jTT+ zjPPjZO&cRT72OFkM)*dD7-o2x`^Fc($H_7R;ip|H?+>^>~J7be8(?N@NYG0!d@hb_AO z56FDOe{u*cO!G68p>~+SJkhIjdQ)^h29aSe9m^{Fm!X2uS^j3o2(89@ujt&ICs}mU zL>B$G0hg^A7(+>WF@jsoewfbN127$$_CkzTpFJIZMeQf9=7KmJb91iYFHHj7@4txB zlY7Yu9bKN&^fsJ4rZXkx;b__`aP-+bA?>%{!TW&yHI9~T!er1+;25$?aJ22dI4Zkl zS4_=zYaF#b6vr&PIRcVx-_(vP^b;VFtZ%ww1vUJ8v4lo9_&3vur%W82Wi$G0&U89) zpf;U2fY_OKn@;RCTP_D#pkDRkM-6rVaQtXv_`kED@}j>5&I$1ket1#ZmeciioIeDY zM}|EaN7G(_qtAW_N5B0XjsbfYj@WGA7_|S!F=Suf9L4S27_0IwmWr_bC63zu2gfWs z4;z(iyCIG_b_X0I_C+{G?W=ICVBd;kuDu$^nBB63n~ecDRuj9AmIG#m9+P21o-&gI+5qCoW}D?v3Ox;dkD)`^pt-KvTKaG0x0@dw89-&SjM4+qW>h=ag3Vz=zP)B z39fYL!1tFT^{@Y1oKw#jfq+C!GrATh#dcu}6ZM-3PJu?OGwKozxT!#F3cH16CY)Xn zI{;UrK{K%r1;erG2v#)Yrm|v-nj&Spshrs81X9XPMPs)i7}2nqU@ypxz19RNZ6+AN z81BMgEJU+Re-ggb+Y^RzG-5{kEix>s)!LYfz?YDV|b*}E|0qA9bo8^%8w{OWEh5ZlGP z8g9ytr5hqu)2z(X5I8zp%dE^!5{7XPh}LmaF)R#hFZ}&mz`CaY zGMpa#6o>3u(PpNaz7$Rz?TNg!S&0cF_8K}j6S&8kO7vsJt+T3(DMwMfmu0ra3vw)kPM2x%8D7GD3AX9MgE(}?{ z1oK+7wdwy6zMYruhD2wx@_UQWu}e`OcL13~bKZcDwt-2=u#aG_PVc=bDDGALX1YU7r!;IrZxTnoBE@<3SbtYj6wRnom}6Qw@6}K;~<~AhS{|``}A= z8AhYAQzjeco52WMzHzDp_}jq(<^)&}{~B|jXTB3GcoPt9WT1-~O&*&8xGPwNTRq>B z-cA2N@meU*n6WnZ2c1}R{knz{&%k^0Krok~y9Y0h#KzB~V&+ohR zUPk8hdc(kf%omk0N%4%r2nxK4Ox`bm_VvuhKfm!fL=l>bS3vS{jd(RFqC}85h}eM?6?R@rKf?7W`8|p7(?*JbdCryu7X0= zIu;1gKp8WKAXv@KK0Zv0=ti^9oAgR{9rcD=JhPpXuTybuYfbWzB-PYeT$ddPZqlUq^b|* z@N&Dv?b0O%{U?wq$}J3b+zh+LO#I(KwgGbj$u~|Q(@<=N7yq3Nr0F^arGro^WFWhs zOedCe%;n;Z&p>B0%*8>g7W^+}!ZFv1?ZyI@b3}_cCLL?TpfJ?6R>X!$P{Bagc67Qz zr;v?u6^cw^v9j(s{I_vh)SHa5z1-;a=XnqAV)PbHbZ{wK?E##5H(o8Ids{1~A$WxDt6u4Yh82AvzbbuJ{!> z?YJD6&snZhd)YBJTd7mb;nHBf;N@^-Fkkc%H?r6cFTqv9JYYGiM7#X{NF20s_Q8dY z?UapFmOD#ujC_MJ5~M$=z$JLw{#iQG1wN*i!L7T|F_7xWE1h=PPK$UZZm)`*L2klm z|NI=Jehy@tOL>-4v!4U4&(-XgKx?OF&RHh{Zp|Jahm-#B5}(okKix#fb_>`nX99}N z0;dw4kn9Qh%J+$U&wv{^u2aaml-HE)oLKb^xUq6-da)*CUit!_ra7YQylg=LHHcGhw*Cm62>`8`JAH@2o&j#^6B@G<>yRJ+U#MZw&RW8IR^30 zM8Rn&Sol9=RYswF7Hq|W2bt|0iCEAn)EKFTBt|n1;HXoIM+`3Xd7m}=0mxNER(q6c zi&ra_%R{bvWL-Ftoic-ve<5DYT3`xe8J}}ZuuS8i>PoGy$eMsMe?R^Lk^Tjhpw}XR(Yrsh7&CC=v2N*P!%=;UXDT!;8j>1iD&WV zX`bcP5IqwAcywyG(`Q}spjSh#p*!(%YS@Ow3?9qX@DTDp#mlK7bA3*kINq^_4XDK$ z{)#d`mE}ycGGv@p5X&T%Wv&UGk{6<_s5J3~&)%Mcjc@Mk&)+$>UUCjWlXf_!;mF7c9 zgjY*vnF{;bahaM3Fb=QIy)nx}WGEMYvv1>_j9iw_*+VQv{vCKV{+YYEY_~zy0z8VB z>r%`YaT>CnvlFP|dYz#Q{KwvhGh@Drg&(ZMvV+s!!mDs6636i73nrdNB1<70con0# zkv;;_45>zV;a~R*THicqI_szT6EfR6`^bZ4Emp6sQ>}w$8&<2WQ=Nn6VBXtxojPnf z3!(Ae(bstSvJmOAcuU*_IdZ7D>)V z8X$zVKv_Z{A&{^Y3N$Qb30stb2wS=edL~zIOzm2kF z-!7kXkv$LY*D!az7ckQI#E~wrNM9aB`kvHTjPx#ez5|aN6Yq7gd=3_WZL!=piCAul zV`0Um?)YL9%Ppx^#=;ZyKg84bX}aH%>Z1Uh975{>;I(mhbPR+)?(M#4*SezFjm5~J ztC;J3#SC2r-xtTB7hCA-8T#KhnA7=Wce)X>9Zw(E`l(A&=TmMCcE?!XZK?Aq!A_O> zxb{zFQs+~aohr9lQ{`Mz6@)I~33~s0KO9%ZNj{vy`yCg&%V&61$|%brc;1KSBIBA@ zrLs)pPFUQAr}fMZ1X`V1L#Fl{u=pEVT1Q-yTEitqdSMX!4wkO3wxrfrU+pF<&tDjP z9sg73rNYh`SZ#vuHawmC@G=R*1fCvx>3Sh-UW&ID;puucUj7`0ck$)Tc=-wppXbYa z@Uj$jzW`6yNAa>3hFyHQA1{>c-prS;;pI~>{3V{j@8E@`WEGxIzXPuS0E=J4<=^nw z`ust-VE)FFTGVvW7Ou}Rt&nSfoObsAV>EpwoZmSF>+VG;1fL9EiZJxy>3SAko(;nl zeA$ne7sBv-z8u5L?J(Ser{i}>{&B?CX#ew!_dgoLcfAwQErh=Z;pYJcT8WqM!SG$a zoQ{|E=r(Kdbf15>i=hc3cZ41eS9T7-Y75+Y_|Ud%Cv1lBHh`yVFJ5-TFu|8;yxa)G z4S4Vyx(RV-5rovO>qU5ZGaTNC$9Pk^G?=@M8LT9Jgsd8G`f2$2BqK52v=<)J0smvx zuqDS5^fqHVzX4BQqetUS$KeGlYy9^ynx}t;hab?B{f4)n17F{WSbDDbQ+H6pF=8G5 z8%CONJ~H?X!i?D3ZR9-hmrqkhY1(;mEENjqcGe_^YdTk!rGJf&+mI-jt~ zFlgAsW!E}np$Q*sU_Mjf-~1UO{R>!s48A{%r}HknJPgCP@$}GJ*C%1~8@&ArPuJ)1 zat?^!N<3ZP#>;nLc$hE$gqOx8n3nkRGrZ*SlEu^YTf96QhAZ$4&BMy&O61`zJYDng z@*>ziACI*NUDD=m^@ml}^~j;M$UEWZ?RZ>^>@tu1k7*!C!Q(qv6s{IN0Z$*NM{ALr z=p69BkI_7R4IaKiPxx)((j5Wu>u0^BQ{nh~5ZQKEKL$VF!_#>&Uj7q?U-P8{FH1n- z7vbq%@E52$giQte8G0>v_cmB{!>yCgdb|{2psr)*NqE@@!)`p~w<}~ico{-AelooK z-SF~x*uDbJ+`#Dk6kfQ8@fN;(056|{;S+c&TsAyt$==1l*M_!Y_&S`vO21q&`~ZgU zN9h8t@Sf`2JMbc?333!0~ZBGtgLQf}JbjbU7aUMsI+RU&7F!|L}EN*!gnUz7Rg1kEiPmc)1OR zH@YCMF@9sgS2mzJ8&lyA{v3H>WAG-~58$!J_!0~c@P&=>1PqVkvBvm4LZ^Z)4DB0Z z4LFn2@K|GPp@9z@<9RS#gU1?!A=AM)LZUG)V6tqCx5D`j`e$Q&9EK0^g^lqz48Ou- zjd3C>Ar)N9z-o*|%OPmSV~w#6h88?(j8ovdA$Svgt1-61aT6YE3_3Rk_t5#)@I%ZA z8{Z8#=Y?IX*|{#55e$l z7sNFN#{_<9lrBt#Q}07w*cd;9pP%Bf#z?P#D;{f%Q(-s>k2S^sLZ^ZjhW3qdG2AYs zXO4_A4E&C!HO5si9KvIb!I0@-8$zNnzVKdnVPo6^=hx9c8{^MmcsF0z7*uBaEFNo& zD=pb)Gq4)t5jZ_ezZ@C=3d6tPQDbo6HUuxAZ#72KNwC3VjX~$e;4V7f8eYr_U}KyM z=QHv2(7_sG2yX*;tT7m<35vN0q{iTNKzs1uXN~b1OV#~{FO7^pfsdEtvBr1@3{(c< zubX7*R)h(HA0gIM6Ic&6#HZl?2|U&iUx(qVeBr40Aq^&#cy2=mlv%_a{_TL zFS|<9zMU#`)S`cKQ0;4uq(zNRzU=5S7goSG#;YOYxrD z3tzn}(rjMmtGCAl-s3+QgiFtgG`TqE(sO~OXr=GzvsAXds11#btyHF;ej&VOjzdXd zlcUONwzM8ED^iwN_D_*k!%2F1>@>WrbT7fSZ|uR_aj8?8boy39vhAUudfa!{N-vxj8u_UQGY@K`D$#BGDE8z2BI1A4oed{iGDA}_2GQ1DsfyI*4 z>5H2erWc>Oc=V(tsS`2A8#dtR+{Lg$Bv6iBeEz}<7H(Zw#GKhE7cf%crhqn0XBZsU zm`X3c7$2Q3Hap)bxXn8YfmdO{GT#g#7A$6H!c?btLl^JyX1@qrQgdn{zPNk=>>0!2 zMbOA_uf^tt3m4%d)>{zY39x3aEOcy*o%CejCCR|tz{c093?6ZLe-$rqw(Pf5lHO^!uYQL6|{?ldzX=xXFTk*_tl zo*vFE1Xl1`5QAV{Gpg6hhK67c)+=&r7e=>XdFsrQ>2i8#>6{Ta9Ht&Rx~!iS#iS}e zTRFG7bU8mKS(pY8zjM2TKD8@f&udLxa{6>V0S`5qNWb6$m zeLRcq)mCGN_}UkyMo(hiJ5Eb=G?!BMWJAU|zHnzaW~J>6gN|l}?&^-s-I4#%lbmm` zMYHS}a}SdMon~Mx5g8x$RbGBm3f-T^^IvgO3iRT&S!Cw|XZ?ok$#l7}6;k=S=`zW9FyfQd1KN}f;sWFmAW_GKg_x6iYulvQ zT+=Fj$t2i>{R>g>rA@4w;%TUiWTh`0Lw~w7*^V5;+g%87E%hn6ObsqXMfy00{7VoF zN8Zs_*$ZnjHlmDKKUN)HrV2>fm6CR=Flx$CMO)J&&n!!2mMy03$c`zan^^gFs9KdN zSB5cFtfh?EI_byx*qO{PCc9*|AfRrIdc>J0x1iFlXjP@y_y7sEj*R-ZAD3G@@uY&0 z!+;hvBaG%$^AFRF$^09F>1Ct_+wg?J(Z;6r%NXw3`1N`iZ^lEP#FxcRFxf91yc+1z z!W>xpy92Ke;=xwU*8vYZ863a(_>$MC?&us?UkI4qa$ zi68iNg}jU*AIFmlE~9t1PP#1NSH@2Q?=^pA!k5f=1w((w*%Fv`D!78c)mkbjry+Rl<-~D3jlsXCM&cArQ-W@8%M1pZ9`s6>@0uSMq{xS@OJS_9J?Hli^7JJa6XBP0#>7~j z!PANG@+Lf~xY1Loly%ShVU4}oJBe;Uut@Hgq9vb1IJc?&1z0u&9Z|Em9qdPIy{3%c z+hUf9vB>JLvvk|h?X^A|t-WY@Trd^%Z|FZGO3rOAvzs#O0Q<$Z$xdl|%Ddnp+5duV zu&A?iJH}Z3Bz-oTPg))qOxI_E){LY!6W+Eay}j`EN<1}|&zWuMHg#{V_1PHECoSj5 z1g#l!Z6>^JO?t0^w~yhevAkurrQ3V0qbH5FAxq0SGC^y`T$>4RTazAq*>5raV}uY6 zo3TQ;!P(+};@1T8ALP9ujg<_348VukA@<@)1*3$1vz|FIPAr;YK+O@1G>lzzL2xWs z@+5vYoN_1M&%pyyP1uI#L^yYCIR5b`pM3r)$AW>=*GAnC(O}5|IRze+oUjc~I=FE< z^3&KvD?VW`d_%A*a!93C!ji#}7XI5WjloK5QW+MBNH6n(j_Ckr_)dv}H#RkyPx?*= z^PjvkjxD0dsm5(^<@3~KfTR5qwaz-2O~x8v`;49#RTCaGH{ldKvtxoK3P(?u5xl3% zqO#G}C6?@E=_W=Q+cPr^o9J_m*06MF3VzXi7tsG2=?}j|y7cBIfO=1f5_nJXgy=Hy z2Np9C6DjlTx?p~u(G&BR@U&o7Os>M7!4qTQ&sD)QOjsNnXhg#CcxGoDmasKX1lCic zA3L{Mmhfc1@8CaTCp?PB#ZD82^>Bcx?sp&F(O(FU;&JUplM4||+`cA);66D1At4+c zfoE}R&zvi8{QBJoR2q-K_>{TwA?OLkdlWE7Nza4zr_INev5zZZVLx_X`fzdVcoaq# z#}1h6=gLk$=i@G+!(A{zvfQ9eHl-avxz8_+kkd5 z;;8Q>Eu$_Bif%c%5IJTRh;PD^7%XWhUeBrz4l3tB4R(ek-eMug-U)cWGs2tw8dEGU zBLeCBmv_k40}0~-JWGRX0(^3}|MbnLY`8Ay2AqB;?HA)&0=GIRA3R8P!UH2uWV=(e?yHEa}+s|aplGjdloBzcqJap?{UUx$tPjy zcDx5*S5Dt`78*o zYPcnZHR?qh?&Nzbo<*_Uylrc3jkN{VP2i^aPIDd)rfX*A=Xksm&A-G$c5}hD7p%RL zFK9f>Dpv;=ZI}wSY*=gdv}?rU1Jca)Srq$YQV486?1%>gF!5mr`n{s1+4(?pR13u~ z>5pboRg^MqrR>;nC*MhnL9z(1F=NyZAzXmPr|~o)E2x(!ekOT4o|HYy0_4uz5+XS0^+0m03m|z*#t(W{3)K}8xp00vm_$Y+E3s>?*T;JOIj zQ!KooCw8Z&jp_aJ#1#CGt7ZNekU#Gt9?X)WJ(J|`6bF$%@82_t<8r@2_%KS$9~mb8 zIO*`W%mFwT_w(2y|FX71(T(|G9({hjJCS)H{h*(xbBDA2l75$ZOCZfF@vw}m@c3WS z?i_CkWIRld?q}ffKbq-pn;t;)V>PfmkKlO}kFOsXO*#3~zz6lvj=#tCJOOM#{qR|e zXBnQAc>Hf24DZGBGuZk1rrX_k$OiHGvK~(G{^#AE&YgMs0v?9%+Yr@9)Gzx4GPtcFFXT_TNQV|4Z6Gkg)ge|6O$G21Ixxo}2N!0?(`Qv?S8wc>V~U zd+=}!`u+xE^jjkqb+QC)L{8HZ{?< zclv1C^wjRQsp`a@-9g*_BZns2CJs(s+qQ3iTV`s{u>*&X^DZk(DtJUKlv-8Omc z%oL$>dgj=k14l-tjyz{__sn!#`RK&db9;{+u2%LRIJ|G<;IZjyDbq8!$)|DP@b0#W zqX*iMD*l+_E~I>D_c5e)@P8=XiK#wX53M-q}&@Xs6{ySZ+LgePc5S3{E1YYb+E5crzU|P&ZdBF(dN!u7n@-lme}A+8&%|Ecy>}lwuOYjV z>sYm&+IO+3iJn87{%7)G18DBfz5CGgf$6sVwEyAa zVl2!|9Ns-S4Yg{Lj@I2IDyZ=4?jwf|9XZ^(pZug%K^4OTuh@s7Gc=T)TXoOm-ic!e zXR0&T9i5zp9q1+o+@1r6XYc}wWvy$GRZ$+;HMtlj4>G#r+zZB5b@JNXlSgL`968Kb zm?}njb@!pJF1#Yu(&k=LqHI52!AGLQ&rBY2=BX+oQ|wqtO;thM4o~l$M3F2-vqS0X zUJ;nYJ;W{aWHND`V?!zoo5NJolJxqPFleAu*Zjxe|208rT6Y|*vU#rGa_OCO)I@XIW=^`|{WM4vU! z%q~2n7a(<{nc5KMSB1+jgw^^v68}z3m^CfoYJ@qr1qpSAi&i~FpjY6O4060OT$nDx zv@E?EVVY7c;U+VsceRG|(yLp;bJM$6Z76zEdO518m7bS3hx3reeAGp=)kz1kwLDz( zRHb?Xr$EBy^s-cVW;24r^RoI{dMo2;eu^sm8Y(YrUV(6n!c$L2cGkj}zCIPs>qaKd z3Kt{r%8qdHY5G6E=~>~*rc^6@rk9Uj5}pM2c`fj|KHLCf>aN!M1{5!%{Xkro%PqHy}WI*)miYlKg&S3YO{gTb|e2)Yg=OXQc3>>r#!4;ku^uXP!@+ zbJCy1{RGFiw7_y@Q~DFnM_eo5oN8s2H>Dp~NMEO>e=|FgWR&4Kh`%vhmHy0)E%1MQ z`m-sEaz#`6lQ$xw<>4wc*IpOrgU6?u!=+8>C8*)k!V}X|*3}och9@BR%gzYrtq)H~ zUqj1|a2Z-^DO(D?-?!q*A(XDUp{Zsd{JnJ%I4lVlr;kT>O3yHcbkLq zE61h6o~{-Y>h5dVEiPi-fNjXi=iwGEZ*C43!e%*|g6*(2T(~&w!7yCNVVE<|42#NL z(3HOWMyso}>2IRLU62b0Tf?>K>srHAo6sH@zi3BzT%EoH^^i_4OszmoF}d{LrFg_8 zY&r!)JQc1>pNX-a-pOuodf3*q48=IHC2UI{Wm!NCE=})l30qoWje*vaKH3^yZ~>Zc zSt|mQ2K{g zw}fY=Z=2s5wrvPoPGh?)ULBsjEhK=g8Z?y zePjO{yq(a525oH*&s`gyx5m614GYo5(QG7`={v4QXGQ03L6*~>L*;iM@wN-`*6GSe z2NjiFD?I|Y^gB4jRy4!(Eu3KsPsRv5CH=W;U?e3dHl^>M$5FgEeXq6EMa|2Yt)}$7 zW_=pm;TQDiG*G40;c4v%RDokF!kh!Q7XKa=FAblIh95^(d;W+-_Vv$Cp}F0_%&_Qd z(jNs00SO{?ux|b!&N!ygN6WNsy3kpkn;K8GB&FE>D_1M?hRLfCoDE|rL>KW~@VdG_(8yj_SSQai{AD+88T%KOg3Zk^&LWDm^ z$M$g1@{_{(>`IH^$wF?k{&+g3A~eLCF_>%m;^On?)eN0)z=NBr!?V&D4G4q5eipjT z*co9<`WR!`fcNIL;mGOXS*M1Xu5i_*@C#p<5-@jQ0$!BO)qqW$jXd2jEmU_Qh%vrO=+G)-Cf&+Qk zh2fd&!qZo?bQ&{lLjR6@y3Vp_4Sf9(U9IBY3Oc+feLLC+)2-`F?U+qgq~CaqwFAT5 zoR>~Eo@8xHxSk|-I~rxqAzHVhg;Vww_Ze7}e$B zX-y}9Wo{uS@efU$y+}0Ih2crdFyPbIq3@l&DFkZ(4hURHQ+jVpYs2w1l;~r|uVM;0 z1)jhxG^Ih!ZJd*V+Kvdrwc#ln;kXuE^#^=+qij*rdExvOHqd@W_6{AJWdXHiaavH6 zaHIVP@i1EbJ=A!583Kgqw>-bqtR6C}CQ<`X5Ol^QB8D7T&;`BT$6qXE3jyShW)#4aOD1%W^XezY+rFhs;Q;vCeeJkv6;7- z8)+%{l-7pYS@8q#pji=I9M@3iF)OX%Ht?+In;XI&uJO16t6$0fB^EVdb3?kOZ+~ho z%g@3xUjF>m?3D>Jfl=_bkmX9J|MB`iWckAmn!XpS9jt@Wzn#Wwav5|J800ca!UctK z*268~i6pX@*tEPkeRd1hEMwMwn1att*|=NTYODsi%I&Me`Y`w}u~GE#DI{nsr<+hBtj@lOf}`Td8y;*8M-jHr8scMjShyfRE6xNO zchO;)TCpKKsU5j8HoQHYzYH9~QZT)381*0phrvT&S+R5r-rDE@1AQ# zNvOO<9zn8$z2rOoOpmVC>!T>H8Lt4lGFDcdV5&B1(53ygFum9a&aPX072G zRz!MXtFct%z7~@~B5S{>>0)DSk$=oy&g<4~;Xq5c)q)-06|P(jU+02QGWw2XihO-o zfW;}sC|`Rac_-xK`1D7Pv5%gX{xaAc`fdo(pK^mEx&BOh;IKp3DeMw<3pWXSgqww1 zgj<75zTD9s6b5qD!j8gFrCQDvH&rX+MRVx1|6TUK+x{cM%usJWw>?*??h5*cbHig5 zGnU6H_{eeZK&3DgOzhcHow#~(YGNN`PDhR%o`KD7eD!kQ)RAM5cI^pz%Oll7sZ<>p z9;@yc9;jsc3e~~kd?A>coY)f#?8tYpc(_qh{&JhFN4{<;+M5ilxXGi3BtW-pG_hyO%@XluNIn4E< znX84NOm?7<$Smr;EB5nL4*92Yc*>}HIfToV(m+s}oSvMivKC}DEUW|rBf}#Y$bRHy zhN}5YC4=VA>_7o5rx*`~yw$ulL0uaZbEAy8hN^hGjzpflUFRHjU31uV&tbO-ouG3d zk6}>?@<_C^&=(v#Jbhr_;mJKMkeWy3@B_R2?j6;UTp~n% zFq7-37KaiwhNf# zTm<#Y_F+pTDDND`m@OFzOOTFgT$n)wCds^Pv@lwz76wNuI}=$ej}$wql|qpuK3j}w z$E72MzG`{67mmZk-fF&3DdZ~ZlN@>IbVHTW@IaL>{q5Dvj&ivjJ)^HoYCL`L$kEB_ zp#!_8j$D1@;LJ1}7-m>~R@4tCjzWM@S}wImEsy!C>MLwu7;_YIok#um zR**lE=W7le-gD%dh)RPjD~*m0Z{R!#a@>g!F83f6nLJu_U?A&le9k~HVtQ08<~pk- z%%;d%XWSH|Vdy+00|RJ-YGrh&IMm150-@anf`dKgnJp-hOAVw%2488NUCcUi8YhK` zd#fcih)Ef(HCV2UfKM>!aIncikAuy@_QK9NNd9K@f_jpV>~!=bdLV{cH474vFP2FW z@Ib~$jVXI<*q&CYU*gJhjqK{A6jCyfsETK6nxa;%+dG>H7% zRYC8^v``r>C2BW=1|Ax&poY=$*uOnBD^xItkn_Nx8_e_-bJY=W4uy(iKG07yE?YTQ zZ#h?voGVApl_S?}Sn(u`AfUO~O>1arW=Ad;lhVStqnVDU%-NX9lY1)mM!8j1%DDpiXDKrX5&`PF zd*X2Q(8Tm}tB#G{W!^_h#T{Y>t)6{>6H(M~&5=7PkQIajWoMy6*159}(@*5X&1dKp z)u>5JU@ddi5}5QZlEk`#7OmKB&ZvvUMk9&cAnMjeG`b9?pkR99(9wgF)%`~f?yAro@)@RXTFnn5TEEv)*FwaFvT7{KM>z*^JaBF|xR*F~$ zg3HEtM3BWe0ms~dp(u@m`NCp08n0R|mcVjm$_SVUlPiw5b74PTx6qeuatxU-^P3z% zu`Oi*{pDPcMPD!u&sVK+mzY@->5}v68=#%{2O7wUEnIJ2=>mLV<-7 zLV$G@S6y*oda=6b#Ztd${C*Gk{X9BmKNwJNi0P=~0phv@pNi%Zjkf+o5){Xc*4y$_ z>#o=#S+zAGlI>LE&>NJ8*}EvR0IA2^Zu&vg`>F0ZFg<~eVSTc%G(0*|%~Ty`t7DmB zrP_-buu>}a^Ie zr;x2!Dd$-gph4wQj&;l)Ka0O2_dka<$M781Zc>;P36q<{w;R{9d~cfDH#zP(BH28* zb&}pM8;_$dGL9l2eB2pUS~Cz86i&`_2#53WKIv+C^hi&TnF|R`#kr< zddrnu>8*Z(>}VM?d9eS$zWtNn;GhV~Wmu5wBUNDjLH0R0ltw6n^5x)o?8Vw54>{j7 z)ZCzz<|JceYl1TCnu0}%&73rC@-T-7*nnNf_BtMg;yp*!Xc{bA6AYMNFFJbFizR&`A)DqX^rAA}(WwJhS9e2I_PJo=^SvB;nbFE{z64>a zFA+>}o>2MiQJ#_#g&K!C8WV@8qcO2Vl8&J&HXDP1#W#dh$+kCIiAgZa4hklsJUWQ^ zkp4zA1W-H*Qz5;iEhb!(HPc|iW*SV|OoNG=X)t*+4JOi~!6eQ!n8=w1lR49{)jC9i zb1ia(K#EiuDcN`dF-OG?vRCBB$`mMefLmw>;q+Z8X2c==F$UEOl56XFE9%-UW}_Lr z45^XaB^aK>S*Je)xkmP9`*YK8Z5nRwt+m?{m5}quNU1m4wQ*wZc)@KPBYW%c z5I3GoDicqTbGddJ0|a`&mNB^=7RN^D#O7c^$R3;SH5FV(N2EL6e3z7t8 z#hE&ziq+blvfAR%C`XytT8z4Z9Rn<ClK}%^DgXG?X7Z}w;`J=c~M*RiBPkfr;P-ISAc0jhDcpfXFbJI1o2VIgP)8C;;`EA&itD zM&(d%NB!FH?@p9~`Np0@w&+%K>O%?AV%!9!^@FxV$m9p}f#WCk9Jo5lqKb;al*^5l zGC9pSiFj(H4|Ma`QHzzW?Oalh`e>?2ll@ zUMyoKMwH-WbK44M#|aV!=sAr%6uY7U3ctt<8<* zSw(BF<}a&M^Zk|D=JbtJ8V6yGB~fvlm=3TudwO0G_dwl$Zwf*2X6brKhm`_r-L%-e|Zc4C6`;5`Q^_nB02}H zor}~W!n#?iE8uXn9SD-NIVt%Z6Vx2@6LVV^x#>VuYy=lE6GiQdHAWRnV>Fny*}*kS z@1Yk0rlE>kGMmtow3z#5oz+b{xScm*axAxM#X$>7wvB9*?}|nq1~O%AWI#M(`?W)(gIT}VVfl}!^ zK(%W+Y=_OGK0-DjM9*N?*zciW0Wp;qU3u{{=cjVr)&&MUw=Q}I#tK1S)@B}V5f6?I z1l*;qjI;|WkpP#4Uh2@lQ$j)eE@8J20zb3w5pEW45wZ~>Nx*&_sxB^=Tke?DG|BNN ztUDm9doD=r?x{pD47TnnwxBdRA!^w*Mb!?=16T%!${U2H?%j1a&l8AKi(Xw%k6s;r z7QH&wEP8ePMD*$yvgp-y_2{)OUDw4U*IBEr5v;aiF3eBaSVFk|>;sB3ie78;-&vb~ z2$b2SBhR(@H&!U&TAP0en`^>u35pPmVjyxyf&>?v07nm0ch5{6Of->O1xVAQZXFHo zUk-Ka=-8od9UVKwgUZCQ#i5ub@PmVlZ6;f`dCG}1nEzRFEGjl}9RTGJ$}pX@Y-%#WZDY-TWa_}o zb=IDYM{>(}o0wYyb@V&AgNqh#M^&}6>1pTyG_I8HPSBdFi0k3AS$ zlY^GWAVi0kp-oJSgIxo4*k6{o$JdW<*@4VX>mDU!h{9o~T!T=<17xw2qAX-_v&kN< zO)&P2<-l4?q9QXH%V8#CIm~1%hnY-VWG0grnaKo3W-^J9nYIQt`EuhI^HGuWQKD;lW~bo8`FkAyBk*(8^V+T@050isJ^ zVW6TIo7KX2u29H>EsO0Fnt5ntTgWFeYrUp0T(@c|o4lEggVD=Wy~zLIk;D61YE+sq zHo9!**+ouHe*_|=IICzErvTJDRv4kGLrer}_JUo{8V229s?yVeXBcz+Nd_6+*Rcmi zxOx~L7$7Vt4B~}pW(3KN7twPl#ISmf^>A!6Ba_9}ZO!Hsx^b*<63OUl3bVyn6O+ru z@_`yE$W@l9hDNP`?qZsgwqh`GaZEscKLHno#Y)+xn;Lcq+j2Ec4POvaVB@e_&13Cz z@W?eup*Lk_;1Kp5K7=I{mX&edYldi4HgsT6;F_GGszx!XcnJx7IK=?TL{Z_K5_l`+V%DBMH5 z6zsXJ0Pj_UuOF(JCc;5wn}UXPU$rw}Y&%z?$dnhOpqM`9+DfDHV?A9n1*1;nz-^tG zHUu^ZskViq^;D*fw2{5|v5%Ys8s`9Lrx(KQG9e?yMTHV$t6bg-n#Oq$OFig=poTG# zQ^@NTG~C$0LO*U-6F!?#Cmc=Br7zZ(AG~DD|9Vc%PKnui6IhqN3{oX#v2aREKOhjXaLu#;m{ONZunRlICU5eU0N!J;49zSz zOil0IJDCgMG_)+kWPq1H1d;$Vl{7adD|qW8(S5K0ZO`MC*6cxpBoc7 z$VnVJHJKb_Bylnr+*>RwjIhT=*wbtBMJ`jcYXT9jBb8h>VMr$;Ku5P-$==eqO9m?~ zOAc~phf*f2(Z0dB>zRWrG83C!CN@Kf1*`!SZ;&#@loNZVXQuW|aV~HoJc}LrH&~K` zsb?)WoYWR9ebI>Sr9yf>`xXoAYwA~;RFrkAQQ|m-@&S)|^XN);!NI@dM zG0zM+ogXXNfy@wGf(kFvMNV&v01|^RkVc8mcfg zNo8)bI$oY&OKDmdU!skVVNgZR8r)6k7}X9+oIwm2s6osvAc!661O%}|oq!;Apfb-$ zZm@z86rKFAN&t(%x*l>Kystm_D%pZ+uliHX4^ZF z%xrrno0)CzgiN#TowR1Qy%XEaws-QU+4dCCadVVZJK4B(f~6X_q_QR&G~UgRPa`Fx za&$T&y~t;_R6#0CrQxYmoFwR)m0^%$#y#8qDJontu-X2fqQWH=o9*A0!Ue}ifr-it zP?N?nHl@K}aPrWRsp|$O4&!v4tvEoq4kriZ2sRlgI6&qpS3+2~(4*R}20WB%v2O)U zQT)SnP=abZ{xP3upv?#Y23fldo>NM&2cG)GIvC|LPHd5q)Qn^3OO(KgVUjoTDcH0s z7PCii7aj)+G>TkLfRwxs+YYwT;G^~mIF;dHFatOm;T>$*f)yrCzfcCHC5Q3zeWsyQ zt@30OlnuBo4Hm3Z8h32U{O~BJH!qdaatlj%$TgBncu$~uA^0CI?X31fwB8?Whk>cH zEwgxJV<=BnYqfzQ-z31%VucD0$`aQazEE*RVoNbNIC*&A%znt|!Jh0WcM(0srGea@c0MQ0YeI#FVG%mjS}Oh*Um#DsP< z#B22ESc6~o`z&L~MaH;HkSRyDahaf_9NETYg3vv(jmrd%$+|EWLdaM=7hr~P>KoAa zrqVf8>A861>KJQ1%o3cVwZG=$?P~v@xG&B$y`#KCjXp{)E;2r`8rjB0?uv`t6&JZH zZpJQB*aX3{$r4A((AA(qsHP`D0Hj*~iVN&9S^3D3wyqCHz} z`6VB9vf~ay@k-)^EBWZ;S%~DhAye|QUdHWAPG}A|E8vZ@EQ=ai*e)99D5I_*3agQR-R>guE2hTv+woYMac(kuyv!ymZ z6Ws-^(P?WyKa66zadCKip@0J&?$~uyW_Mm2eM+L~L}VCGj+2%=Haapeh9dA77|!D& z^Nv+_tC9()A`-_QsUnP3M@RZfD6?M=kRo^$Jg-+?&p`WmNISmqus}Jt8k66bEtPXa zF_T{~t=vQ*&@@=oKD`#kY!9YKGG@EWoWgreBo`-d1KajsFhAoE8b>J)OnA{;N3>|e zBnF143L6AXtm6jM-EJw>Lo+{xQkJ?6YMsONNiX}C>2ho;Q z?6am$qYe}wzv$%g3yRoyI)@6KZl?^{b9N!dUmk^o5!+aCkD!E5B}Pf1)s%2U2giL1Pd}_@dr0mbAqMX6 zI1x$A^7`VBjzC+*4mR-ogB#d|Aq?lp7~jzWv0P*u-_il$Tx7c`HcEyDU2Btim9oN| zFfVkPfg-E6CdVAmu?g+!V+C6p8RKNZmPWR5vS2_X+pSLN(*DQ7k9=p|Em};<#$zUf zQ4nyPCP5&-<=ZV@8@MS1irN(V+Epj*?&Pg)S&ZT&x)b405uiGKjLSYA(S}H-Y$t?r z2PaLH3t|;76{*)U$e?3zs)uaDZ6F~d+-`D*{Sy7c<}Au%59~hpT%2LL8XXYYs(s9P z5$cERk6wYnU#Ae2DAs)Dl#8=3Hslkr7dUpIC&)d0U!70@V%LS=5%s$nmL`EsAf(lC#{*&X{()ZnViBE(AJ(c8;_mU z_DIvs_$u29LN7o!Aa??NMmH;Z&C*)U&~DQVgkQmu>) z2m4IO3+W5jbJ!B)URNA_u3)SKgu&R+XO_C8*;m07DGa?h^*>3Jqz&qsnW+oq=HoicIeoe<$vU5o6|A$YEA@ECoJWA2ZT%5oXPfNys5ix6a%F5` zNQWVDj*FUw87qICrK^-W%UG)nGcGT`a2MHda|$cZryf2y?>Jn=E|yc7iK{#2+T9&m z?y4VcLQ-+v?bM4b?Y7y_PZI8S3>>w^`0@;BqR;R~9g0+WZxESdlkOW6rt5uh?$5do zbB(iDeM7wGz%H4I#|1`IQWR>}PAOAxLjBtM!mcr^S7f8G0;7v+Z{+>E!TayPHh22~ zc~V~n%1Q?_L$-)Tb(WDb4=5mR*P(GVB$(cRWNM~XohVM&l*IhZ2o3N9PRPgYbVTBl zu>p(~Wa4}%N`a)%9~@nCDN;X()!_*>ZXBxc5Nkp|fP)Vb?V9~@5Gd^baIsdCsfukJELsIN8Jw@3%w%5B*OK}gw zq~g>==s#9#u!)xwA3SsS2nR0EmN{D{W2$v0glZykj9Jb6fd=le-pkejXXhId8Lipr z#Yq<~uF=m1cqbck;#I!ugfOvwPNaW8-pmQ~<3b_ft+xL=#H&fzRR>L|lpPr>k8zB1 zTh}@GJTbn~D3-gDas^)FJ`pSTH>?3ENylC?1nCJ^l6NwKu@$mb#gim)vVx$>E;PwW z4TQstN9;|3gwr54$*C5EsX*6|RQF9BH4S#mH{eXIi`s4i6dWmz<5E6Hi+niS2xd6j2Bu+CqJ*gEO;lI+sauq& z!b%2*u)#!Q9|1}mvyTOM|56ef#KjRfGj61dOT}KuKg#_z+IrDeKb51Sx|_@ zZu!*oNSg+!tP*9<6sz5xc+eNr6=c{8M!ka?M4JY-zXLvz2MVaHdpT)%hdTokx32VC zk`iZsv0S2tWR;xIWR(=M%F68`I`wN=C2Lz&Ny)UVHqTBmJ`S1OvBaJq)@vHn=r(b2 zI4DcwPMxGia1Bxbg4IQS%uyucn=x5}k?iDPJ#-XD7<`MyXOk!p#Cde5+7|DqC$+A@ z%TT2Y~5q2!Wjs@5_UNqhT$yr=aQAfm5k%F3p6KH9y&R@r%#}3)xT1ca+u9&EGN_b2{ z!&a$?OLKjItIALc$Zx7H5=;$=St1{(*7z>Uq<(IVLsAk`x}zj`*h4TpLN7y#A2lm%36O zauJJ9mkH%{nNVJr3FUQ}P+pe_9 z9eIbJo~UMgt>ti)7LQ5T9SHD&oa6siX=d=|UeDL5i6cCluowGgz~jSiDEA(c_a(@p#?4Pg_4+hjc)*Hy%?MsO`KY)p1am z$$fOm-BX-GvJvFnd11WQ~KHwf5bgR8I(Gry+Zbw)0cqGf{moJiPCi#syoK2GxD==!N*%g+4tU&s}3nKPDf#ewYbIH?0}kW8@aksOmua@2M{3SW`A3G&|u?~=foc1Icg8H|{zL88Ny zlKmwXvzH1LY#8`l`<{X`QtpNpEZ=d{FE*y3R7H6q_{2%xfpov@nf=r)lZi=E7@ zzvG;%JCkm>yF~50hr2x$(ge417t_qa=eP6Om3XK$IS!L`=A?CCJ+QBb6KDRa1G}nH z_Z{Hs9^O|KXB9b2$ZGwmK6iZ)k6F@ZLQF^XL??DYk^Oa(olZ9HMCs_dzTLbMm48p( z{(LR(u(5j!G1ZqVT)#sSU>q&DJDhimVu>dKZinzXcNPM~AIitLBPGaGz{GH^9-mx| z!g3EWzL1pNgi12WlWSf~&GW0`BAk|;Q`kqxb&?`CB1KEVO+~jC`8`)710C3gq8cLm zyX|fwnDh}7Cz^P3W1)Skp?R=3GK zG3D-+#-S&#wP*`5RFO%Jx?rdoyS(FpvO;SJC-?;6v}^0#g{wxsaf=5NHPj0s zKp}u50A=VK8g0pK-P*zr5Vv-;@Ds%CTROX2&YGHp5O{j>?3Rs(b{{=<5x$X%k1=e- zM^a%iv;WwkUBJBuk4(&L#P^FY!bKQ+XaS#lk6yiLeX8| z9%?;=Pa>bYXZq;5dylqk+}E;kxU*#=zTkS%Ze(EN-b1*`7J9oIosQ>4?XYr})o-Nw zE8g}VJG`66VKz?V6Vm*AE9@vKj^5E>!2#LimN=n+%7+-i1`TAxn1*cFplau8M4sdE zlYkB9sMWAkB8{!t=ySLF(h42kcL%Nw?H(;B;jB?Pun7&lKRaZ?XLm*v9mGzu&OXlS zWZk)AQ}`~%3^uEIl#07cEQj#|oTM;|b4wm18#*MI^ffUhdOCVmw+a4C$O*rWQ*>t) z6+jKM&;rFb7uV2;*!3L&3qtQ;>o@{Fd_8ZaSs?GX#$VxN-wBABynF%o?(zn5Xyv##yeP&UZba0vHVisN&73RR zI41##C*wK-5ln@A?fsCm>_>tnuv;+OO~WbCK?VzhJU<;kcZVG!?$0PZ1Q~TZqRFoHLrM;fFk@Q8koCSsK&su9)Q zj?J5Rw7G#+80WlaiUQbt!v2hOPjT;~FTG|uPaxecqIZmMd}MFtuy>M++$>_iPQxvE za6H@_<2Sijjnqvwp*ahoCX!c}P}upWO7KP}KM*Cn|8CsIVKExCdi8 zc#v0U%0;XAQu%s}c10;X!!U8mxZtCwjA_Tdm=6)ju1keJ?5XG~2eBvKQ!M1Lt4MSb z&@m&4%EGLGtM~COiMo|Tf%ntJDMm|c?u11Bk>}9xu_|7TX&Ym1?AhF8GgM5!OkiRw z7!GkG3eXJRbpRK#xZOWnK>56r3cJFL324_W`w8N_H;RRiNVkzW&*`U9&ONPhWwCfxq!7F=8n;RfnB1gL>- zxW^g+2U7ikIZzF#siB~t9>yHF&zj(iODue14TO%xWjIoH-x_lR8Mn0YlTC3tC~Z&e zcX?nFs~gsFld(fxjl~X0sSo;&+x7SDW^@tMhMVg=dt^+IQxu1Q+3ipiahaq4SPPUG zlQ-z0POTe8>H(&KM&UcRLdg~;79T8Q9XYdd*V@%AJd6Rt!lU19vSJknemq{qB`LD$ z&YCEN$3MV-n1&E^;&Cd*ZX-7iG8!LT_gRU{{n(;3S`Kd0R||xRxQqIhf0x9j95z`W6b?-WiF?3}b@BrjPE!M#u4qI33XFMmjN! zVjQ)#fSmviNVXK+^^j51Jb6o0#^gb`vzXA&?L_+3mw|4s1j}1O37|_&Ndy`ej>KmQ$w+ z=ejf{ZSlU2uf>{!(AE_=31X6lFaVP%VxdmAPPy6CiuQBlcmN_~T!=ML9MLHE-?NH7 z(IorsAUi^ypUje@a{dER*!93_4HLGzEnT(icX6EF2|ww_jr$?plwQT^0F0F>d~_lN zng?#i9AmE)DsE_WFYw`tmkU4Yyn_>qx2a4MfU1)Hc8vzQAo?Yu0S^JbOCL?MW0+Jf z>NI(1+%jan-0hWIVL0^}uYXLb??`)=_nD9{;{kuCBSp!VE>?*ue+29c>X0MNF9)0^ z2fyX$FC|48U7NrV=fUO`YIh(D$aw7FmUVO8^M}=*Stm)Q>ts(YO_BSYD+*r1;2i2E zk=P;07uQ798w?#eJP3^>(%9nR8OMO}8b#CI#QfgLxd4*9GL{$kPM@3ayui}d&ScpO zA|(R{pr{WBe{!=Pi%wk;ifaRka7GGQ7J*cC|@u_$8`;)RbV!791{DYAfl#j zZH%5%9jzX+1ISK7WP7!Cb1mA5-&Lq>F3Pbf3yb$wedst}L)hKp^J znjEohEyeTkCiOXDze$yj*fy!v5!>QQGSgpTKNX7%78bRL(*=gOoQIqa`XovH+~Viz|fM@|@H+fn{2pUkHtX%PGR zC9P}vXr$@}9zU1qh)SGAn=WdVtzcz>NPgCkTDDBaZzo5R0B8ho&%eCG4S;BO(QPdb z9dRcW;&jjuSe8dO*&z*6m8|P+pfjki5_k~56o;XV@3)ec@VvQ}xyg93jgnA$;<*^I z)&;3f6tGtEmEncdk=9Eb4HM4bB4BLT*daCwa7@WsGq|5YlKd?er{HhnMo=Aj+Co() z-#&FtS=&NNelHCS9OeUX5SDi^=MJ43NI_~D1*v5eq?S>TT1G)?83jme$r0KfDq_Tk zXLo|g4%V~W$QQpQghA`hYwt*+%6^VU*6PAlE&G8f0ip{y1+|*PR<8BZ6WDQce7z9I>#Q}S`gNO(U_x<~)8mKi^zPolgqEDXQ*%61+;T{|(}1<|yQ{CUoQ%6Z%1UW({Z64aSp34(K2Qkh z;ml-?pE9S8@XX|)qwd@iNP9UEBW9)^a$Ot@CQ!FaCK9r(SZsyeKYUM{D_A=Y?7w$5 zv1jsHd|)>bC**F%a+*{r&OBP(-A3p3piyn{{t9_S-x^T3!PGU7#dl8q5?xF=xNTbj zC+g0+uw4WVeRO}NQXCWZd`xCdu_-E*l*ZjKn#eAyz(EBh_Rf4ci0&B^!1y7vWj?rzI?B?*rjW0>RwBgmM+~O^}7c5?uSr`PXyeHte`I~n$d}J1%HMw{m-d85v zZ!q^0Z*F{X`X%rav?SafP6a`3@v57TdvViC!k0F_Ed6r&2x|PSY6ybt9Db5{_$9(* z7axCf`o#?|Ni`gO@N*9=uBp3aa8K4{(;V+Du=BqbWFq6@W2xF_7A!uV<%Z&55KK&B zQ#MGo!5D7YIM|Bqtf8Q3$#H}8(+lP;ZCsXGo;oSLGIet5l+>xIRjJht>r$;ORNXIW z)foKSlS$`vkaP`#bbv}o{L-*V{?b8XFh6O5_v9}fgmvy=(iyQe)w#2V;$J#AuFn0q z*b%05Ft5&?y&(Rj;aZ!&+P8GDpw6AWJN~7Eg>~*|jKnXE)~$^(+1kwCqB?gs_E^j8 z=M8XA{?ftXI{%A<7I>h4_V)(3pAQ_t<9-~y@h=^mSQq|8^FI@L;b@J2>0n8n|0U-C z(@{5A5_^Uz9W>YZZ#Mt)qHfY$=YM&f|K;ZYN0G1Pk%@+Ma8jNBlj_`8*10D~Jj0(- z=T7Pq|I(l!we7Xa^0P83Z*p`qzSZU)$FMrMNH1*Z6x@@)bg-t*|C*#T;#*tyzP|1~ zNeP+$8FlVw)xDon_kLd8du!eM#=7_R;4;{-`0PnbF@AUJo#k7K@jI<|j_jovuP@U( zN6J!+&o}CwJ!>h(zwchc~s=)X((q96UQlRN46QuNo2dMB-38Y~aC>YcQCDf(Mk@1#6SF@x->c|Rq% zM(-`arRYC4QNV9Eo+W5+H_zjajtzcWp;iW)&^91*1fjRTzInqQw*ZY*^s2brS8P}= zaYUT;f^&dNmR-S|1oW)JnSl})rFqpLR%W!>Elh!pyzk`0X z(Snm5y=>SX1P`DM8-{{_^s1pN2u>uz{-^LqBpF)`65w%%!jnGGoxg_Rz-GCILBzxN zoSWkt@`#V`g&<(xYUp+RNJF3FTN;p=7TOmbzteDO5S+#LY!GnNHjD&8J8>YuC<9{7 z=NN3bnElKlsU_c0q@dx#z^F+B2$IDEdya0pUm)BjM3K$DESwPT70w8+6TVdVYT@gJ zZxen%_z~fkgbxX=K9P^#>D}rN?;BW;z#id+!mO}gI3%nHFBd*rxL0^kI3>JRc%$%U z;VXo%5#B1iL-=;#dxUojKO+33@IK*#!Y>QIDI`r|`MxWBO!#Br&xOAdJ|S#iKSVg| zm%zn(UnV?7*djbbc%HCRxJ7ueFfY7Rc$siqSQYLS9um$7pC`OY_;TTEgl`nSRroI9 z`-Oig{G{-&gR5N;7(BJ33o z3M;~A33mw(2#*S{5#A_#vGA3`*9&hKzD@WZ;Rl2t6MjbcfbegG-xU6x@KNDE3x6j3 z58)HSG$vX0s|CU(!j-}`!ZU;$h26pngjr!xI3gSqUMZXu9u!UsuNS^h_%h+23U3v@ zMfgtP`-C4BenNPk@bkj23jbF49pU$dKNkL*@Nwaj!X_+BSWk&2*9p%SwhK24 zFBTSr1H!WKa^ZwZI$zbE{O@R!2h37fEtWI0a|t`x2no+IoMUMMUGhlFFoXA2Jqr-aWF-Yk5T@QuQE z3O^?NwD5l67ldCGep~p6@KNCpg+CSkLio7w_rgXnEY`ll6NM{;tAy)>X9-({-NN&Q z+l0Ns0bxlvF1%8>NBA7!QQ_6X8-zCrUnYFD@D}0i!n=fjCVao}!@_%n_X-~neo6Rs z;X}gj2)`%%k??22UkZOCIX zmk3`ee4X%3!nX?FDSWT+gTjvqKP|jp_yyrth2IuFB79W%L*Y+_zYsny{JpSop~k=P zMBxhID&aceS;AIfxA1)7Hes)DKv)uv3$GOJ5k5zFRCu-U2H{P@mkD1jyhV7s@Gjw> z3EwaLu<#z?y}}2CUlM*@_>k~B!tV)xB>b81m%`r)8?ZoQKbA^aoZ9^rF^Q^M43!jf>O@Y%wB!o$L2!W)Dy z623zCTH%|7cMAVZ_!q*D2tOsfU-(7g*MxWX5rg~e=hu>@Z-XJg`X3C zS@NY`R#+D95xzk9D&f0?9}|9F_^|N*2!A772tg&&TP55myjVCae75i^;Z4HV z3*RZcPxuw#e+ZXgbAjos7WN2B!m98Z;p>HW3BMqGO!#lY`KP*gHwm-CBf>uszDf9q z@K?e#Wy#3bdBT3-sPK^RM&X|d-zU6B_;ukw34b9>pXTCUBRo%-7mf<|3a=5qOn95{ zqr&@zj|hJvd_uTrwdz^eCfqI@7akS9Qh1y2L&E!o-xdBun8tPr>uZhhJYilqD%>l) zM))$}ZNiTV?-xEI{E6@h;i49mN7yFZE*uvg6~0jTI^jEn9}#{|_>l0Qg^vs8uXX92 zF6aP$3sYygbe0O&3%i8{ z;SS+G;kCk-3*RODu<#M#uY~EdT{@=qBkhlIZnJ}EqDql>>wxJ@`NoDsfIc$@H}!uy4f z2!AC^x4L*w6>b*hg;xl#6~0*b7U3s^4+_64{EhIqHW&XI;RV8e;j@J|2wyIIoA5Kj zFA2XV{Jn5tyNiFl@Dd@^zinRIBRnR2t?;eFZwmiW*xcd5wFoQ13E>-rZx{Zf@aMu* zrwhMS*ebk0SQhRPzCidY;k$$%6MkO!u<-u~!!D&GEC@@&=LlaSe7*2}!cPmoBK)rK zUxie*AYZUVxK4=ghM9d{I4ayLyhivk;cdeA3Lg}HOZXGv6T(HCT>Ptr=L`FURpC+L z3x%%}zC-vC;pc=834bAcQg~92OAlW@vvO?{jtggmFBIM;e6R39;kSe*Zg%lhgu8_I z2p2tOkHobVyxKMNlh&cDQ^cZ%>_;f2C+;iT}7g|8OgDg2=DuZ7(2p*-joHzag)Z<(k_5YLLmKJY&Eb-`?bK@>y~Lxsm*aJWob9v+D=QF66`HGI9&~ z0eOTxPhKUx%^4?|Mm8t&$Wi2f$hqVi@*VOZ8P~$rm8Y&)?R|(GN^{cN4`RCBlnYM$;+gtldW?H znND^j2a%)5=gBqXR`MYE3wec%>TK&bA{&$PlnpEXq2y!aZ1N3qJ9(HqL;gjU>tgHF zCX>n5WN&g1`5$sNxrW?M9w*O`|Bw+~Z9fgj3{t-KZnfhPax^)ETuN>vKPA5+|0E;3 z**aCp0NH}KS<>ij>qn8b$SkrQ znNJpzQ^=*{I`RYZ7yT+=OR^6+jGRi&CpVG1$rI#dGUOrK zPZjb`vK85#9869l=aOs5kI19sZ{!U!?qSt~W($UfwFayogC{F=N>hUVEimB<7#lWa>q zKn^A!C!Zr1lk3Udsm>fnSz0lA?uMDWNWf7Ih=foTtKcNKO_&6zmQ@5 z>4$7YW|5u9Tyi)$iJVO?CwGwt$TQ?$WVr#hzslqtWMi@&`5-x(oI<`#t|NDn2g%dq zKVKTevKiT(l;4-Lj!PdU zXOWA^E#yA(1bL3UMurcub*hnxWLxq+au_**oJp=F-yuIIzb9{y;X`ddb;xY811aBp zv)e;XCFhf?$i3v}IeyWhEWHT~{ z98A7Qt|mVqzaY<(*U8GmZT-4rK3PmoA$OCXl7Ew7BkcOIWDl|rIhLG9zCvyzkC8u+ z*U8F7jElUR>`3O2h2&cD9rAPXd-4VuUTo`Tl0C>iJVyRNUMDM$WW40v zWN)$`Ii6fVzDDjO50bx-SIDSGZT(uLpX@|FNEVYb$d}2@Vg^U@)ej^)` z?Z^koA>?@Sd2$W8l{`qECNGlCv9=!{S(m(*>`3+_N0HOW<>UtPBl1h~Jb9h;JZAf= zPBtc6kvZgJ#`7Ze}S$-V#$cAKlGMAh{E+N;E?~!N8h{tWcs$@FZmh43iCjUdu zA=i=H$+P5NWUcYGelnRwb|rJkV)8k18TlT0lsrfNONKvT>&KIcWNWe~IgXr3ZYDn= zza-mDu=O4#pCQ+i2gpCjh>3RjI;5X$O6HJ5$;spbaus=i{GPl*wwh$?_aqC*_2h@- z_v8gK@=3d1Ju-vrM&^=FkTb}+awoZ${Dl0R{Eajx+i_GQYm;}7Nn{#% z7kMw)itIpkBYTrMWC8gIIh-6tK2APKK1DuH&Lv+WmyzqpUE~Mke)0?QTk;R`Z}K0~ zHO1}+FIkIBAQQ;|*_g~GTan$!0`d`Z1Ua6ZLCzx=lCO|&kh{qb$phpU+lgV_l3E7lvO?D)E zkPndq$;Zfv)xs-f^+(zyrkC5MyzmwNV_cXgbmB`v;GI=-Imb{PbOAaT;lheti zvj zwk5le50S&jk>q3KL~<(mEIFHekz7o^O1@5RB|jz)l1Isto^jHu)mC zn0%F7OTJBhLLMTIk>8N#$iGR~47`C?|N01Z9=g5WR8geW70eP7G zj=VtrONP(1;VpC(@*SCMa!o5^kDZt`pL9OyTU60nCn2Z(kxThht$+#)bbo>v4mHjET9o%W_o zw3!rOP~tyE{zCf& z@(TG6S#FM9-UCY9RX}NPb@C48Co#VX*_QUsO!p@HfKtC7Sp-TvW0*gK>3QT@@-tBS z`xuyL7(bGK(f%*kP@aD>*Jd?P%GU*}$g|Fv&IZMQbFvNXJ(%uIK1}-vQ0k8crTtUL z*|fjN^fGb{DEe=Z+d--S9`nDT{TO+g`9CrL5*aejt`|nef}&fEyo2^6P~ys_y*b&I z`45275BXpvdDI)z<3Z7zL{6oBHq$SV3u%9y+)Dd)ayKZtpECax`73#q412+jqYl}g zyq_FEjwC0M&yx$uRpeXb`{Y6L8}eT=e7@~BmaInx$fjf`@+94@{pWf2I8j)Blhm3v9heQ07@2D0(%>1W^1XlFevuMRuY6K5{Va zh2&V;Cy+B~pGz*GeFeFV_MPND+CL?~rTu&I7uqk9zsaru|p)FY+qsTxk1qld)tC zGMP*#TY(aPJF+|3i|h+Z{Da6RXn&G?hW1(HE405xuBZJi@)O!WBaf3O$upq%J5OFC z9WUGV3S?#S4p8E6M5dFC$(Eq#wI?5;VDEhm|y|f=<`Uv?Y?LRVoj{Fm>ZWvdq%#!^d*g*DwOpj;&ByuY4^T=hiuON5Pz8{P-jIWsfiTUTr3$$Nn z+E^mxrJociarnr1Q0#TcJ7`a1I+JWq`$M4k%?G8Oh0HG|A15c0Pm|A)vq7o1km)7l zN>Ji@hy0K{Or9oxC$E7X8Ly>wy^5f;qY7Dr_C&HV?O9}V+B<`$VdOCV2=j-L#k5ag zdNTPm?ejplVZ6%p2Ig-j-=Y0u@+er&FwQXj2Pko0Ca=;SwoL38Cr}wiZKjhzDeotP zw6`LAk_F^&P|A-aAESLLSko}(F};lWE66ppZ(({Hxr_GwOdlkV(0-cfGvswp{DizB zZyEPUP~wRutCI0#T~Nv;GM!4^MczZUCfk!e$lhchvL88&EF#B|6Ue7PiE{zdi^$h# zUkgfHyP5uwJPt~GPLgNHpUI2lU*rwax!kT7PI}2$P~xaT251kG_mVBhj$~Kz0Z{7a zffDaf+DDM1XrI9JWb#>ZCb@uIM6L!!cMH?o$UU@wOnyuI_vEj%|4D|uDmv0%;bcWn zbgPn$Xip)VfU+L60_zw?Pp0#jUqB9`eI(Ok$nms4#q_h}EZSdYdMUYr_N}1!+W|^H ze#ZPS$dlwL@(d{Deq;I~d5ye5hOLltXg?W4#*($jdSnvmC!2s0R~x1~kUeRCkQ`3? zNb(8Vr;rP1Uqr5?eI2=z_V>wyv>yefoj=ijp1eeskdD{vb}BLgl(>DM)UQcM7S?HkE$= z%AnM*Lwf?5LZ*?~ppp4w2vXj(>|5y>Es+xbQdsx1?{WJx0t`3 z+)w*K@&x%cc@7l43!ud5SS^%xD>8ztK*o_Z$OKU8CxTM{F52%QTa)d{9%OH_4=D8q zfKq=n?c>NPyId*lI7%6|b$`EP0ep8SRR7nvWjM#@Ql zgpwvG^?XcMCToJCTc7!U+B3*z%x^>Xru`wZA32B|1&ZF|p!j>5_UFhK$d}0Fr+Rv_cZ8e{?}^%Fs<-BW-cR-?i^)mk9C8`Cp4>qmB)=gq zkpGh2H*Eja$z<|wvK`rj%m*Xo{1B9R@hJHO`6M};e1UWsQeLiKhmnz_T#~cw4M{0t zrGunQ2`k--Y)AGa?my&YWW7%c+Ev_fGklV=5$)n`gXG-5&B(T-^?M0Yt_Rb-$y~B8`3O0ToIp+{Unkd- zyUD%eQSwXjcd&|K{7GIV|0P31?ELa%b+Q)eCo{;_WP9=Q}T221Zn*af#_JjLm)g$`yb?G@&@U2+I}mNRmhrTT{07t>(qCX z&B@l}!=Oxl>-PqP1DPH|J_*)0jH%>v;5|o#{8pEu{5(0+Rn3)8COllGg7C zNd85pow9<$UpdnH-2h2fWjc{eC7Y40$X?`w~DDpA#8FB_`J&#}dXARTulDo;z$)n^?q1Bi`;mjl;p9m2Y4SO8F8Lz4gj`N;BX^P?lAn;D zlSj#K$nVI%$!nxp&W_W14!^`(k?AUA6Ed4@MYba!Ci{@1Nb9-#qW2urv&aSHB62Ia zo!m=)M1DzrLt;mT>!2>uBqPbXSO?vbumcZ zLpCG3lfB3xU`@jqPL3wWk=FC!CI4xr7n84$*7M*ce;w0X$?fDJ@(6j7JVl-(ebvQ70GI3O)`Z{BU_Md$bRG?ayU7Xe42cYoJ+n)E+Lnb+eqs<>e7!N zGW`kpIeC=)nmkSZOpAFBe>Kw^$j#&jsNbC9K;@t>=ylO{ODB>-pniuf}vLnNHqK-b=P4 zJCS|K0pu{UhjP#N|vJRO*TF+aT z@_we9ldZ{IvM)K9EF_;Kr;^W;v&rS;O7d;;UGg*X3-Sl@EO~|ehm5LVw=agQO2(4` zGDx-|JCOa!N5~Q6qvX@%bL3+36>=N7lRQWsCeM&Rlh;W@&TTL*sjII;#=k8D6@ zkxj{N+&e$k)hiJV#z5Z;;-~c6)qeLo%7Xmux}yB=09j zkdKm6$?4=matXPC+)REzeoTHveoI~;FOlV9C0^P0S-)E#tiW_dvLTsFW{`K0UC18f zgJdo#r@hv3k?fwV^9ylnorlDOa&D3U$}w#+D91`cP~yl2Wt-m`lx`Znidyx;41IWQ-Az4h0CdZM}$Y;nI))eKY5%yNuDBqATN-Y$P)58Y2bRT^p}gYes5RO;Y?R1@!R1j7f;q9 z6Uc^SkZeL`lg&x%dba3T*RzGaXn&B*CHs;C$ibv_om=XSV|oHPnVd#GL(V4`l1s?t z0@nc~bBmIoTSNPr;vJjNxjbd^%D90V+$O)hv ze@rH)f!P0&*5@L!znz1$a6VX5?xQ7_fOTYlOs)jwIOTP6Jt)U3o5-!899(QCcY$*J zvWMIUN`LPst5mrpJVN?mEGX^&36yr1mpW)~eNfu@ z6e#U`IZP<+v3}=N+T+1>EosLKQWx=C=X(;jbsi`27Wu?3aZUpzK7kQ(kK8{5N-R>< zN+*EgBfxYJlz5vn-5SJrGTjRl-+h@L07^TGnH~*FOp}?O21>i;Fg+iX_AO_6B`EFO z&-6i1+WQOB7eHxu81|f=ZZ^(2qSVxXeneGlse-tuZ3`)ODV0tnr{WF8BqA^2?^ZE#jN7x*omx>EU7aNIv^NRC~#6CquMj{M}U32bj-YlnC-r&J~ z^70?)Rv<-6*}LWE4eeH(H{yRar7zm%SB?^GzyD!b)`-8gtyQQ1(tci1R2r!a3s0SgSn@FqgGU~qm; z@rZ%_`xlJJ89Y+P50yvQ`Tec_l1`9N5R$$+l10DIi#{)HRV6b$*$dc-ChoPc*$yL-DmUvR8CgM|KZmQ0lr*h zb7ATDkPc@apv&Da%caY8E|pih+{oL?b(i#i(|h{1a=DWJZ}Ba;tz6;%Qf|X-g6wQE4QRno-E!hcR`j*>n)cw+N@t%FG32HE>|K2u-(@$ zU9P+ol3j(7&5Ue0NkhM+$U8#bC>JL0#M|_+tsW-Y^D8n z7QgTVzq0GO>G$E=^l(gERZn7;6Bzg3rq`=fJ7m{&Q?KYYJsb;Mf&gDSKHTe6I=%s= z;*(w9O}#0%>1~n~&!@#$4#`!wmD?xf&|dx0eqX)KZ(%9Fm8CGsp&rh4zb;RU*eH|82d*y2h6e^Lt7<^ny$nw4;u^wcozC>Fqcw z_n&Gpq1Ma2P4D1Ehp|NRp;u4dT5r^CdP9%Ndih`4QFNPLq1>c*Q2G#h38nO&x=pX8 z+{Cy;u1D*aj&I6sdfC?<*7ZZ^$syg%_~ueCnF20ZDNDv{HM_mgTyk5v>mwXS+grt~ zenGjlx5d|5R{UK$D9J~^;I-N0_$x;sS$sy&<_}-Cnvgs*A9lXLuI*i8lqV-=( zgHrV7tGSfRm3~eYOH+BnFSf6kdwQQLi^lS?4&x;)B5A!Cbz8YGS+PDYKd+uY6rcWV%p9sS)F_`^!-1Ls4It~+D|H3?VTeQ%AhVK@yYM~8Pdnq=8J4I*UFc&D1%o*TkqzsCGpwy+wJ}{WN4kM z5tkM=%{)=JZQXWrn$FqT=|V_&rwh*TKWbGea@49a;({=~-RzR8HT$#(?tHSO>h5ao z92Z8VR2fwB(kTbLjA*fIW7^KxK2M5oykq-BwTo%Hu&FOM^!Oj~M$HSgBHL9iiXBm< zD1thUgV6E5>uI;J=```^2tRPVT)R#ejBxRj^65`@dyLbU)r3PA!i;z$TP9^T+Kc!n zT(}xivbpU=XJ<$4)@|CfU0U+5b6JTiWuv@b+GyN)^^l`xr%OhQP8ZzaP1}E4Qs;Ej zj(bX6r@k$zdb&yLJtg6%mX#P$8*=Y%o09u#Zr!{l9q#V5=V#Tme(sEtdhu#d_mW!i zd;bh6IF}vl&>(k0NpxUB$+BHDN+tx1J3AjVYTwyrV#&n7L`hF9NtN+vl3bvl9F#pg&X znr5TJWKIrAc8-=DiFzd7604PaNXF%TJ@*{#x|PHml9Jb|mU_G5a`dVu`@2=LmZ!?-G+py&a%gFE|txwGc&d;aze^|CwtWpm-5Lv z@7y6rWX?{pgOTGZ*FpBDAz{k;mFTc?J>{sxNvwu?71j-~rb@i7WM3|ffbvLX6Nmkpsj3!9S}qK2)$|!;R1Z zs0Ty2CE{?F&XIs8AqNI4=XISU4i_Q^hX3}@@_^gbEe{b!=*K7sgO!613alKL5sD8H z6bx2Qgbb6F6KaIw5JMICXd8gwlA(~opcc_Z{~lAmgEJb&^x4EI(rr162KtDND^Ay!X@;pmW zzGaHt^CQtu?NdyjsH zqaYCtN>M?{^W{%#a&-oY&tPY3vUTnqx3S<9Hn_Fs=bu;SY_u^5VzT= zMJXm+L2yNidkh3|%Ai)35ll7IsJA^~xGU0H?e9;CehV`pa#jWT|3FGKwn$-- z*2@22O7u3#bNeub!y~O#e?Urwi}3BkEZpV8RNC#se0a}?L4Dtck=YYzZ5NiLR0x-- z_WIDd2O|&3fAxAwg(g>=5INa| zE=*O0QrI&I!7NI(cMIEO=dE5%HLFXGQQoE2rMgecqKR9j)cVw_ABx%Ks9~7JFl^9< z>W29Y3~y>f6~mkj!zOKrHOvJtY}SU#hUrFBTeLyemvEO_ovK1*$@3a!`Rl2b;m~tZ z`dGc4Y9d}lwJX&hLGAf*k)ew8M--ItH#`)d% zLh&pFs+A3?l3(?Mz%X<`ECo_gu!i4+Gz9AT-IE~j0)!LF3e@te*C1f!)uF(%a;Zx- z@|%!`K)~;Q9|AZ!Q|V;|lKtu|1Rlenrc$6WdN1fVAq|0h{ce}+P0Td8Ca0Q}6}a24 z?vOmsOw7G|DDVk-wT0h=Gz2>M-S|3znUAjTR92vkU*RhSo{8A_wWC0NM9{@=LK*_S z{O3I5_m>su?pJFdFa~)&DbQJtHr0cE6VjM_`F=OPU|>Fm)xN-QZ;bGjHSv_Uqh_|lS^s{2KX%j_KQSMS3`O*DA|`(-`W$!UHQ&f(&Dzxx7QJdSm8CIwv5 ziit9P)$Fp0)BP$&wh*2-;O$u|HiP^ezX@MZe97-_Duv8rm~Ag>0qLj*rGQ$j4R(w# z_!YjV;2D99?~7E#oug`r--ItHzUFs73B^7TSfvFdU}@wlezg(;`=!g&s}z_HwKaYd z(ir?re)o?M_z_#~w>bFN@SMd^ZKc5>8=j|Oc!vgVc-H$BzSH2zN2hP(^w=uru4=pA zgmc9BzTaJ63Yjt32ktE!<4(V74}q4*+szmUBE}E>CZr+oncw{q1op{4b?BCW*&88! zL4$k{ZjQk$Ijl>_P`w1HW7;5c(l4L*)h_rPi`jXAJ|9BjxZgxH@Oj$r{uMr_q4U0{ z0OnU6%#t%@6~FeY3bL8<9D=uRsfgCAAN?kLLGd@g8{c~{ha<)dTEHHvbAHtg0?Am> zf1$t^*r;9fn~;XU6~7xBL-R>^xmH%-vR}=Cz)Ec2{-(goSReoKn~;V;Xu!Q50$*UP z!vgjmK;|ntB_yDZK;R<@Te$-E9^g(Kad-kIq#@u7xc`7aB?wn6E8q>NicunPL7J;7 zP{72NFD_t08Ul3!?o=scZibh76yUjMd_dg?fln}%Yf%7qI;(_$326wV1Uy9$z@1FW zAE<%DL4EStDBzwCfzJ?Kk}dA}9h=*KcF^1pdLEr zK?*cRIDG;pq#^J~!2LS}@LfMO6QKg<&zb| z(+%+tq>IBCyx{>8&f#Kgz|&OoX=x>yuYo8e+N z251RgOp}38D+4B+!^Il`_n&Z4O;%U6p_Gf2VpVUJaN!(Cce6?b_Z^qr{uu!o;JvN%0L+2*9Ms~ax}j!pm3DpxnIQ8 zy8-*8V;?5O-hc_`XvL=i_uFtW9$TV=I%wI;{(&C-TpL0Svpm{)SR16a4DZJQ^$lD+ zhq2htR=kEmI})%Ck>KL%fE(ZKFt1}QzSRQaVl8T&(gtyn1H)-;ko`w@bme#2AiJn% zIPXyFF3CS}D4!>gD9`xbafQc3% z?%xCMjflGllm8DbVDE#@2h=eLG=#TbDNqdpe+EoQWB9HG+}Lf}!}pIK968OjhVNf( z(8G5_8|0J^UrJX-8b`dU9I0WIbZA4I9B83Lh&ITX=~Nh;+8}3%GhuLPgPfVZ1cTCs zN^;c(hEQ#&D2JSwjpejKPAqZCrNXqqXP8&8i+5{7v|+k10Ohrzf_!Zg22&fN3=?0V zRpHv;HOznEB|;nI@TmfZ!K)2&;#3WW3fd56m=H8ESyaQW+gtVI{ zgQgoRb^~pYjfJcdwbIldP_zoyNwbd)-oq4Xm}bHk6#Z##kC@EK=!rB6@XB9Ono5;C z&n}F33I)!fF&Swlq#=-%=FWitzTB^}ZwZ)@7@wwTJgu-pYMiDfL$NnRno#i(v8d*0 zCVWA$eVTg-6uYBPM=HtzJlfPcP3?t%^@%}S3S?m8*g4IFGz5C3xlco29CiWsQ-Fsn z-P2U4G{@5c>tas|{D?k(D9wa41PapJeko+;<1Dy81#o7x5FrgL+orrU)eDMv`i#n_ zVj^bRBWWgl;ds4Rx>s&mu9-&!w4YGy3X@Yg}#an%a(VCs6iXd!f#FYWkex&*hV_y*$W9^>hRfO@JBjaM_*)xfpYRI|CE6hSgnwYTstvNfg~~2f zUDF0xon_N|CQVh5x#o$+eEBKOK0G-k^IQFsW}=(W87kd9RtlMwp;#{c))7zw3~p_Z z&PayA)COt0112?s;v8sF1O@xOaV$(hQZw3*U z9{-`3t;@yn@L5$Gq=+cSq`UusVlzyXO13x8MkK1IN5U5r>!y2>q}g_}>T3ZRV@okX z8|28qYUdr=AiW|kYNorpOKr~|BBpB7MGn^XJJTcK9EGCO)j%l}gUDmx41WFT?xc9_ zH%)hi_M5H^+HZz7NdH=6nyC$XOdD&1Y(pb4$aiUjY(sI3shVg*xM6)DqVCoPxlD2r zC9<@kykVY!;T~;}BLRHtSY>O2Y%Qc|N$IM)w8Ddr8dVAhZ5%eGP18*@8cl7N?*6-` zH1!C&zJnH!rs8=Gs*^TIQ}N&i)kPbmslTC0H*Jvh>M{&Hv_a;U3mcjHv_aM@FRl{w z)&^OxD#7r8HpqHa9fpUrL8jvsxXsZ9S+8Eg-XTvLD$7z(sORPp<-;Lz;27Ld4e z&{rq4LE^56xWCi}iMu+ge5DN%cLrw7No{aiv*z=3)mZdB+u`>xgIIy~e3Nb>JOptj z-Tf4TIO!7mPg+2Nz{j}itTspxm(lQ_wLyXy5h8|j+9361rk+k$>)>+_e11=#SI`T; zq??EaKL1R2-&;?7UdBYbtOdkpb=3Mx8^q_^*qi^Y4dT54H9<@f(X+Fi5t(dQEqLJxN{Lid2NumtD!edZIHO_4*Pw?rTvY8TOVT0msA<875kUxMMQhMrHVF4+;?N5#c6{*(V{ZcD+pp7`X!n{OvXr6%PzK9^sV4~I20usa` zG^@TgNDz4LoJ!CJ31Td|<_>MJCt7@ls+1r;C&Ong`oxp))SVe7qJhuU4EJg&WKNT$ z3TOfG*%&>PrVZkAAZA{=Hi*xv(9O^WY506h;-EIjfUSjSrZ&icT?rLKV{MQDy9--} zyR<=y%L_4^94_)R+?5)Li}%sD1zJE{ zT)8@eLtq3p7vppU64D3QdX3ixY4uVVCTfF>)<&%3leIxc>nXH- znl{+2cr-(W+$lkIEC2oFKb%y3tiLMFa+t7dC~a#kyz%}~uC@HPaV zr@$;+TbP?+LK*^#GTgHuQ0x}_QY|1M4S``94IwgLMnmQmT|(wd4mxDHHrPSGn4z}7 zr`&EW*VXB>vc#iSWSEEsKG$Wqzkp9KR<`xph28b5GgJu#wqh>5PJymSY|Jnr4S{VL zp1KW1;8ldQBg6iH${{g+k7=`08{~*c26Ib>yR8)V?1ISKwl_~RQxdx~BH;^)`!YPE zpg0MkeoO(}c44_VpcU;#?#Xa3gkon&st>66I^;jih=eb=-JGE|$YKlvje$1Y9MAB4 zBa611FH5JgG?wW9L{h%8zFGC@+jS`3YWw;8IjP2;+YIjvJ^5cfuFR1%rUDg z&Xo=PbcVYJ6i3Lpo%)`N4dui~ozIAbFSz|YLk*I}7z7#vZMeCV;XWaY(Ouify;OhM zHLbf3BC-Dctqn5S^Rd+~(FO?w&lgo!X^@E|8nR>71ssx=i!#@B+K%BuhWc0BdEUY_ zy2x2jBzfwe3=`2ICRflsBvHo{8oae%wqh!$4LYVUZO}25r$NVL>H>@@T&L}rjG&q& z?mSDe)eZ^T``r2HNl(y3w1}x<(7jFynXh3(S6K_#>tj?WQ1yTS9(k-9FoNcoQOQ9Q(hz7I^z4PeGT560xpK*N4G*YOcWZ-mYa(Rs(FR#r z4q>KdYl94R%WiT7?p|$>e(fwb2hd&ZwSWZm4Qh4J274RQGU#q1g*`uGZnmc4D(pEr1tZ}LZUaHpMGD2BtufGs zoBL!+$)fom^l)!>9(M}eWc(%1W99W==e>dT_JN=YDG21t_(Nb04hjm&_I{3xKLqeV zIF(0%UvYfVU&fyT!)5#-5RC~`R90Y!jDLyv%*1L*hnw4%M@ZV##h5U31qJ1CHe z^=nVigfs*W1l?C5FcWM3XSW2*0Tsk>P#f$izAq?u=!xPyc>9=&XGBPS9yH+#ieCoZ zcS#}h1h&8@wSXPc(V)tO!1Ea8;}qzQYY5*2O-MuF$Dn%`1TIF2{bwy8y_AO$JEsk@ zL46Keq4U}xhYv?EtA5c28N0e@?yuS)^G9aGcR{(yM}oj3+SCsWLR`z$>7a@55X4_W zcZ+}o@jC=cw1AA=08GNG+8{wp_lV(|Hb@W(^X0lWND!Z5&G|>w@%)gaOLJcPVU z4B{#D#Eqbd@DN03ru$l`+G85HwL!XOF>0FHAVK_zAqv+92_hL)JlbFf z5t1n%8%q#g=({rQoy&5pK#`dy!b1=hGu@5SB#1@U&P5AIPb8qrVzohnSdZSXq7AZU zNM~2bR9&UE2hZVFKDuZDe^oP0IERbcneO-D;t&+;Y5{TKN5Oj9ATH{oo%OXrdjES2 zVuChE!%LuXhc-yV@l{OKKpX6a*T__75mjBRzBL)um*}#FnI_^zRQ^nN?{taEh4m** z3rJM)SXa`uL87__Lxwg;RBaGMP#YwwJZ!NuwLzk)j!jWxZLp(C%2eaUq32J?r7)^7 zDA**^M7)TqS*CkCqUweYZJ`Aus%OzxEww?S8i8ZOR@z_>$32;H)kIu0MeTd(qCNbz z$u!{{E;?tryJm=s@@RNhEg&xHpnl$Y z_O~5Yrbgot2wop<^RMc|ZT0a!+_hfE{^r9ssTG!pKwTehM6YLm!{MB5tM9|TcM~`E;g;Ygk$7aj8fTZf+lO0rvwXO#_8uSZgw6Kh z?$vuE55-8SwYGlK$ole`kXmQQ*4&5NQ(OCR2Wi{LyO8sdt=7(mn?l=1c7W|mJJJr3 ze?#djTdAWDw{Uij45=u#vv#d6KHP-a)i+H3cZ>8O=Y~HTKX}tUvNBRez-n`@54TF@ z`Eb8upUB$Csb=ToMe!F5H?l>Fi!`)+#`f!8SC?D>@8Xf7VBxSeQHOEATBem78IX1Eq zQf~*Mu~!`D!wpr_B5T3+VZa*EXCfORwa+d;!-xB!W<>^JI~J&bF`ezh4NP-i)E3Y zqfXbf3b^O~6(8=Mcs25C*mBaM@gqble7GHAb!0N?4oQnfBx@pDA~iHE`ihiz-G|#7 zc18Y+S~G0#??t-ByPBC6-APL9@!>XsgFalZIuwaV!>ToQxz8hOAoY4$G=A9Vun(Wz zpYq}J_R~ImM*f`-pKE^~*#M=!Pm6w2R=*#-_+)yQGioo4H`1)`+vD`&BiemVFFusq z@AM|ci$`Zv7`7bE)1zBJ-s#1Mai^S7cp9vllpbw}^#^CvIV7J2`T> z?XbMdYh8+Sd2wYc+!b{h4j;;}2Eya=;$l>U%Zn>WkuEQ;19@FuT#1QtMHw<8>IJ)K z1(z3>SE5}}cwDVonPEljb9r$Aq@v4<>j;%xUYwOzc17V4w(2*#W~|GLGwv!bFHUmf zTv0WV85y)9sOs|KG_#t^i<8CbE-y~`YPh2C>|2!@jEop0yrme%L|0S> zs!p=YPI5&xMe@mDbhZr9WS18w5i?v-9bkRl4tu7{i!*~+t|;7(q88a+XS<^Ekz5>% zj+RL}$K}P*|9Y1fhwK|%UL00$bVUtCnGbBCH(g#FD{m5cnSSc9ZQbnh;&}Hhk%#q^ zZQbJX;vjab%ZtOvw_RQw$i3t8;!tXv%ZtOE?Jh5lFWz-|u|wbC@^;NIjGZno_Hw%< zI;i!}w7O`w1cKy%OsgN?b486oa$sikx6Zqc!soG@nHyomvyfj*F>;_s0i<9gZ5 ztB11e8xVSWC6S+Hek-*gFeuA?mlTrkY{_>)%hvCgrE*cfw`{!C0M`G&+D2rVP)7Zc zS?k)T$giSC*?9l|Pa8vGVDN z%c#6iCb1EFPYu~@#}-D2Xl#lYoUx%5AXgwlDi)9H3^knC1%{k+!e^CoE*$@bWjN|J zl`SN`rkdR}(x`exX7O2PEPjW>VN}kP32J)_tr>Bj6pZ!BBr{^45miU*C?~wN7K<}> zfc$qE&PH;m5SrkGW@Wc%vT}onC8#_@>Kd`n$%^KP?Jo!6A+hhtvNJZz3iT+~#@JRe z2_)1^*)W9qo%vF&+5{QmkkB;mVM$b3m&M z<+e%o1zE6$B-E%8C6n9nyd&zA*yPf*yyEW?Sx1}D@+gXz91|Ljg>9P2f$&%fMY0;B zgQe@NS1ovUvo}j)l{q&_QAma{!6HV$PL!tz*(= zNBz)xx#Kylc(JQ11${CV)K4$$IE#t;3iVdu-!W zF-}2AYY_H^L|_o`^o|AcZis=kS|CQlu{Wf_YH{!1FV;6D`we-^;fQq139%fL)FF9G z_sx{#AX#w4(0fxp6}P)Gy|5>sUV8VVWYQGOb$~O^;nd zl5L_*(_@C4L8%yCsZ1$(IIb0eRZ4a=qM>eS$gTOea#7ps5&w7?L{ym^F;rkvC=@OE zVYX0d?>?)(2*qGQj)WzeQvNDg%@eiCE{8KB%QPi)yL-_1*aV3Nzm8VL<+wdB&dLjw z{fxCB64jzb!s-y|T~x2mkgd)}V`{Jut&l@xGQ=l3?upe6t{>YbI?7QYG`sQ(O=D5N zrYhALA(gf?m9eZTqmJA^XAO1TM2XJspZc-!R($fim)eA`sb9K8n`paC zLTP`p-Fs@1LuT0Arm-nfqrubi9G;NMGn-0N?yP2{M0a&;ZEE(Y)XVIx?vwU5tme4Q zhGsSTA68kJO-B!DT~a_q*wW;i#n2!vnPLY3@2QD5!$*r`^;WlP2g>$|-57ah)2#-h z|I^{4w0s66`^-d*iyLU2XH$tW}abfX(WMM zk37vP>_(N;Ihi{$VnTQGWhSexwKgzX+-Sucl?Erf*QR;S3#kJc^) zSq`K7EeAKNIh`07>~>P+9bzOe2D9ZYGP*p>VzFKhYiBb}mP`AQjhh3Y%j>-IvVeAF%Ud@@7Ohtw z`QKOG{p3AB-iUpgy!8vy6#CGBu29RlZZ2;OZ)Q_{lR5T(#NuI@+G$emyl01UjNE$F~NP#RBj85u5AnD!_eMb%)I;`2S z5e1D#6bvmW$}38e=Z=p6Qj3a5_8mB^^N3-C3i6AKlDf&0tRHDPa%fKX0RxBj?>u;9 zQBK!;(>tVTPXmYMC*>6mOcLMn_kZIzQ63AKH#n(ifIJyH>897z9NS+~@vvco^9SS& z99oprKR-VwZ^V$Kl;j+LPHJ*$N=`~LjE%(DXy~w^1&s>w`V4H8lAP#ogzQAgE|Zlc zK@A?+w;*XqUcN+KP`dg5e}qvqrl@oX|DTLN{*a=9MM=#I9vzrpkkqwB#}?i0?UvNW z?iabJeCs)#`ItIZ+Ik3k;sC7GIeiQI<&7L%oKrleu%Jk6vZaxc>MPInlY~pIVP~|& zENI$Vl5#MC`ZCvYWG2`G(&XZTA-6L777WfCV`s_NF6BNEOnc{CmqRIMq(g;;I+VjX zJW;uw)#Byiq$AY&FHa_uL`Xm724e6pw34a<#@V(|za(S@z(1uzovqu3#>=<)+A0+j z8lz&Wi7iEP9HGu#Mq5$OX@a6<)WrY@F25lI=(s4hIkvnWcqg6x=RV@ks z;jRkVy)$U5W z+O=g_wj~!}UBISTmSnk6f~8f(YSv0NCMIjy7Pi3+$)*?wOea7>?@lnG20}?7KmsIz zKnMwN=}AbTBoJZ(2@%YrXE<+wlRnDX&>W@PZn%?!CB_&YdO zSB57Ak3YIRTpj!{z=%qNTQ`>@f@)M*=4B$i<_Av*11{_8@N*LRMAVI(|^ z2v<)=kdqR@R3bPP|1*s7B_m451b4>o^1=W3Dm;!bbuYWtRiff0=sEa&9!kcrcs5B z&q_Uk#2Rxjia5-jXEO|SCd6D1u*w}!Th+>XKH z(fq2saaq;>J^b7ZN$rR1chezxi-nkO}%_dfd%8}unnU1V%n%>#V z=4>Uvq<(UEtVsu&y_=h9;W=_Q4(#9aR4veVl=+{{_w}~!2;jw$mC34{?)CvDzhneD z#$n;W#PYl#GPj_%YhkjfqP;8CnO^FoT9S3C^XeBl zb#SU`u5Wa`bXG7rW8bn~Iwg~xRY)m9tzxJPyYRS^tZ8eglbF`_9-i)7w4W-u4^1D|(}y!mm~K-Ll`4qV`qqUt&0P+nrC_`2 z9eCc@i%G+B_qmmujHv4BTWS`iyW5((Qt4EEvc0V?<cK? zcN#molJn}C7a&ufZ8ZaPL$&4apgPneBbAgPGE!I5*fkwB#btwpjL1=+kZe|us#K@5 zu&%4K!AZ4upah)S?o=yGwH*sn3sXqp#`QQf#wUtovZf))3^XKbl1=sXPJ61Wjc=Vbx;4wBxcLK^=o^UuI}}U zlL6M(cO<*JoCZ`DQ&%KymZ-^kYm!M;%G#WccIG5g&D)b*HOZEFX-G0%ZKQ$PX__4> ztkY4`+00*&(rGM7Hq1_M@Wc+;)O9X!jTBLB1M9U3jitgcU@)~Xm26IRKqI4DSgKPs zC<_!;YkOTia$!rbx)R|sy{JPBC0WzK=vz(Mz@I7fRA=2HBLX8)6c}T!YinieMw>B@ zyG=w5tcr!0sV@kJrHsCTF{e$LrMobdc3S}w?X(!7u`!!oXF+XES66ErgL9+9gUDcQ zy@E}lt8r4vnwDe(T20zJ#|;wh)>@mlPA9oA)xdPIe>FhT*;;2bn6m2b>TGpdQ4q<_ z8a&j|Qq|1Tw52?wDswyCbeZ+${|3j_GKOioaZ{UB;OH~mM%2)JoqsWt073{T4UE8?U->=*3 zO!snA?cL4r?q+&-v%I_6Mp`pbU)`q8K?nL!y zEu+06^$XFODf!v(g)Y3lk)4e7U>n##`LMHdx;mlL6!p2XWdX+_Q$z>^HmJ02m51gD zo6Ab?uF9#YtL$#=s;{$hbDOFel}uCMD6_urF#Ij+ORvM3T1-hL#xA!67IvZGus=3g zt3uYgFm~7sx_;0H+YG}(V#1v}l)#47%`|w^QJ7;bFqAFtJ%Z1nJ=V9Gax-`6Rb*G? z-A(uIW_Wiqy}Mc7-E8k}j*%G3i84!eR@iFgASvt`kVkY@NFzEgj&SPnIDprpi=~iE zxjHGc{N@WDGlS?h!-?`Z9ln>ZI&9VQ-ae-eV{Z*R5W|Mt9)p3}Qa3}r>Co6|K`!Wm zTG8#Bt`S3CC0a51+Rge~=&ON`w-W+?W%UnEl@5kkw}b7huSd1F!wNjT55ScqeGm$K4sl(8PR_nM` z(M+#aZc49T*S{f+X&_F1Gj+BC;y`_=XmDCOT2VR(1-gk_n+{0TxDzF2hZ6?VhbB9i z)8^)+9X-(yYB8DRU}yeEFbhmiiE!4Z*Dc%7vuyPtX`J=90q+CNY>(~GO%iO=m{l)N z_x0jdLpGlCN|4W?&Gss}DNHimnOtW4>%>F@v(Oq_Y^>axTj0(c{vig2nv%paIF zj2-K7@}NYNsf4CZcEQzc+%C{pH&rY^74F82!E_Xq8A`%to42Osn~9^>MRNvO)7`~7 z&#DNSSD{(B0pzwojQ3o4Xne=~&y8VW1NvkPedwD|gV9UUzJJ*vXrIf_I!$j~B~CY! zKJ;3yHOCrTqjBp-uW4unGot>eGSeYdW_qN`>WqgO>}^{yU1I&>bQHn4ayGZ>Se<%y zugIvWE3PL@Lfxq-XCCf2Cn5+_CA>Zg7MvoxbA1k;D1@ADz+DNMn(uTZ=hg7PTK<>h ze|2u2y(uW);A?=PpSYo?COht^m#3oPLQ0=ydL1XZmAQ-6Zm9CL8V=*uSuA z#X5*dQEJAak4r5L%U4 z2UF@!T?0cgtsfnv5g^-Srh_tTRdoCsspxZtDT{}=|i4z-IK zq|l_IYL*!$VH{9zS*rdrfge-`jH8+wR?HaW8T(2it0&@&lG(0pL>pyUn(n=$CDoZ^ z4o#LZ({nkX?R8)XuF0*uw5&Bx%yb`|Ip}kB1DU_U-J;fI2(l$v+l~dCH#nOP0dZg<=SIfP92FjQfwPkCwg$A$oSr7tjhPMJ z?x1)uA8s^FvjNMx_73}U0UclmUsNm|UU@<m2oaazch6v)P;reGGT2Ul^Xyxd-v zEz3-V2F`}KAjf+N1FRzP!l(^zqTGstu#No;7c*U;7PBFti*@@i_~Ht^awaOBnNYx@ z4#SXXV5Y10R*Mz3%xuOnpu5?_aPIlaESM`ZE9T0~k{L4b{LaqY&dGjXYNwfK4Nk+t z`i{1FDCeU}=aq8Rl?i=bVZKwZVN& z;ZEn=X{ebVm_Y4B!5C~l@H)Y}&8&kU9nUr+AG9pbHY1;^jC?S5c^)$I!6c|owVPAA z8q6yQ)KjyZa3{KaC5)QQ`s}X%TdMdX+N^}CP_ArS^Gw?^Q&p3P1xb!paMUaCbq8%Y z92*Ae`13IrLzqO^O(@a`tK%Gx&bLrK7z=ua!By=}e~^x zA4HzayZ?4~ou!4l%|>;Fo&DKS&vVI?Zgr+~t23orosmFwMgr9t2~=k!P>pGm>DkQB zCf-PEdg}g_>-sjBm*?()iw=XsEnj@wwFA13>F%)WPD9-4PpM&eFw#Rd+3c&)Ot4!8 z3qlMs{&g`LKbHvZc;*hwkall+P|s$HSD~Le%!@T&gnZdyWi%txE@ouj*9>?~+Kh^w zc_t&l85s%A$VhNTMuIak5}Yx|CpGlxZnbvws|V6#Uw*l-deGf#DQtQV^G28g!o0#v z?O91G=t(c_D08+q2tC=zH!uj1wTvtAb?bZkdbl=EuUWUemkVyUbD!Z&jo}%;J>b_Y zuJGL(Er{{zz%C*Da{(3222Uz8Gm@N{X@xU0b#P{;4$j0oe=JW}@M!t&9NLa|plwa| zhSMN-PR4$<%6+59j?sNx=f2&+dpEuD&xF7=37+7~d~dAItZ`?#!wovY6?#{}cLRd<*{#B1=4YFyge)s@>Xp*=KE%$=r#vkPx_W6kaJ@C%7sVd;ZE%^+E9L3j%Z3sbc0 z^5Nhv{3(3CoN zuyex1)9sqf`WwH2Xl8;rt8F8gMR5EzD^Aajy(?N{XT}$P9Bb=NBRwqez}wNv}Cr48(d z9e!Wy@ys9Bc-F07hS$q%Lbi2z@45WFk^81Y)z$6L%})zWd{2<6si+ESxM;WP_FY;%7HgB6NRwb%Z-#QNxV88!;8 zSeonbX2<;URAuKMZoSJ*oLR0iRQ{~${)U0JXkPR>jmhMmi7BiXHGOLm^=p>)E?E(TDMEjvE{gz$->lY%GH-5*W_Uj1h7g7uqu zUo!{)_4J}vJArAq4bPt1TF&hQPJVGgYcyCG86FxD7#S!HmIX!!#stO&#szlFn-D1H z_RXBjZxwR>{*m7qyBhpPY|S&9={&n2H|zPXAolASL3wr|2j6&Qb{ca(pYIA{LtnQ4 zu<=hBxED73`L3W-kmJ9=_|M3f8@e-B5T}l3haWZmukgHJhpX?Rf{bkcG2?#^PYnLu z?c5wYB*#C$qRU)Crzpq0$b{G8dBL|dzAK0=#M$u=GyXI3;1=V|6~xwM$~SWj_v#>J z5-?kvGp<1gTljrf(82fezAI?9%x5fuS*?Nj#Ya89E0|TY>5k8Kd{@v(_)K))DaSm) z84nwZcM1N6qkilyGwb$q-S*enqiI%G?tf1? z`0r&owu1};UNYQ0E_TJ>U$n?>(7il^&h_2BKW2lDZ`I+-2AjB?1Y|)@BKL3{wi}x7 zlz9>aS%?m(8l-&_34bBD?+AO!nD*Q#pOT@T z`>EnyVy)OHc8iO}9&w$>y1{V1DxM~uDPAR-{J>v6(+^HWH%IO(wusBcE#lY3E5*CT zhs77gcf=BOmkc){&Jo+h<>DssYvQZoUJxvwZxWY?r;8Vf-xL2JZWnQMoOzxK%^A+_ zVp2?ttHl$H5M>De!ogqiTjER#S_G{#P5jriI0i-=*AgNiC8I8&ou2* zVvo2{yiELo_<%SZ6_L+T`7F6WTqYhRo-TeD;M4o2M=dKWWb^^^0iSLUsECgsjPUMluG}nvNb4T-9 z@fh(E@fwlZ&FSw^@pilBpxIlEuJA>C*CeTB0eX6C>CN4$@I31i^UD%iQ;AA4dNT30|hsHzD(Rz z+*6z+e-^n6VthlyoyD0Vbx6>Ce{q#~qIkA=t$2s{Yw^$G z2jUPcs~Fyn;+|roxIsKoJYT$8yj^@id|G^2{6HL%P(0$EVxyQA*NexBXN#AMw}|(N zPlRb2b>bHBEb-go&Emb{lj4hF-UK(kB5|@fTWl5&5DyVg z7S9#GE8ZnOEN&Oy5sN0e@$D|o7CXcqu}?f+JXgF@yj8qk{FC^)7@6e8Gg{nD+)Hc` z4;0sm$B37R*N8tA9~GY$-w;Eni>!|cajIA^E)Z9UM~LT&mx(_Ve<}V>d`0|F9J-4e z-%etM*di_x4;7CS&k?T>e<1!`{I&R!7@F+HQ!MT(?kUa_7mI7euZic2H;6wG9}%Au zKNJh6xbaO8r;BxBw|J0vxOj?qk@y4g9`R}MW$^=X$gXaDJBri9x#E0rjkrlXTfAJn zMSMj3gZP%1znk(UP7@o&W#W4A6!9YQTJa9?LGdN=Epf>1Zalk+GsQMBEv^@j6~8H7 zE8ZjiQG8hp?%{?%LaY$?5xd2M#N)&>#5=`@#J`Gfi$kZn;qN5wB{qpCi5H01h<_IU zE{-X8!`WTjTRcKMQT(R(L-FV0AI0~@f@w;ZxR=-@E)fqEj}y-k9})i`z9r^YxZzF^ zr-_TjBg7NMZ;C$@e=hz}d|xc6RC>j|#3pfxxLN#~c$s*Y_)GD5@eQ%4$_;;Nc%68^_=Nb1_@Ov-mK)zrVue^E9w;6x9w&ZFyiWX? z_^kLhaq4V0{2H-cTqhncUM~Jjd{lfvjLmVw!QL!WuKS9M#5Lkk;u+$1#M{J2#b?CW zo^E)f#d*NUh?k;nz&P{KTID&-x zR1)LO46+!%dx)*%M8`Qm=CsV~W!@t zA-Z+bUgpY-;xhIr*)Jzi|5u9Z#D4K)@ig&UBt4-|VusvTwghl$iUO7m$Vm5tK8O{8W~ znr{<-EZ!qh&nVr0C;mzNi}5eI{xg^TDiA4S3MSrF~F+DQJ#bF|f+W1R|lSCU2mTQ^# z5Kgtsb4k<#Q{UKs$=o7#h+X3T;$m@$XzC}PUn%oy@d$CVxJ5icJViWRJX1VZyinXK zUL$^2yh*%8{Hb`a_zUqt@i!#OSpI5}!NyzI>@m&)6{6KVAUq+yO zMAI%%ex_Z3!)T9k93kG%`hoaQ3xbIEY7+51OCp{m+!%f>+!*dc65&t*v&Km`l9 zq0i+?dxx!!8=P|PC3MP{_V+vGw7}iRZpAIf_Q-5c{%t53*PN{<+6SI-w^3yFBWAm~ z_U2=@jKe2wMR5}~*oKq=&*yGUDPOxT6VY<&dBAR%gVsSV=Dug?(!Soq921Od1En^8 zV^1HyU54-|8`sA`o7L3gCs#<{DPIP4b-mc8>wD^;zMeJkRMXj7-m_st->Rh>Hz3&0 zdX0rgR9UkxhR?8m`7cysbB)LU^oQzeu3Ud~r?Bvcx5OvEA#k(ldlC2k@LoZ9?0f8G!(%_`_qR7H z#9-w{PyTpU`r@U$ZM@^*kLgA*=4!&tINcLA-l>Y$I?>eXK@r8E`?CdkJ zb|#~tPNP6|S+}EbPC$Hlc?CP7CFF&|N5K@lf-dc& zm(X9R;MXI7Nca?V>3NZY>o8J;LScRf1GnXnNU#Z=X|Sw>!&Ufr{1^Nt;ty7g=)!$| zIsOZU=Ea`}3r6$d)?#{c3d+#eh1!fEP;egRW1)6q$SXJ#@rOE$A?QSAVyYDiC5t$n zjBZ8xLJdPX#6`EG5{2d$Y-4D_A#~^rGMX@b7B0nIL1;70^M;;|#K*X=#)_Jq+Xlxwr3uD6>OpN>0;;~n8 zKg66>IW%?^Bv2H40@)rGOCl%5u{dHG9=jdSmc*7o>?2~_Z8kFYC?qf{R)<0=jV;3e zWwDo0GNWV9Aoek_UEpVI?CbC|F4l+ecZ_YrvpdBqk*Y-O1Y~i1tQaYu5aZsoi80Qc zC&iwG9CnU90zb=RV`0-9J0H*fBKBkWe;}5CFn$?ZjqraJD@QIKjNObdABx?HG(Q}# zgU>wzah}^ZH4y(Za!?+K9|(a=3&c;rlNEvZ7zBJ~AU+bZIx7(8BK4d=yb=;RHxSrKY*I=Ce_4Z)=Nd)$CFn%N4 zUJ1rq;q!07_{p$*H5i|dXkQD)w;;^dgK_Tp`+G3{FtXngisvDQ)=>OlJkS=3rx0d) zDBg%XbcEtOCwzV=&doucq4+fTOoie%K(t+<_+pe%cPRcK9#{~H&mWGpNGQIE=?uk} zL8gmBah}U}Kq&qw+`b%&&&C6bL-E}q-J3%3ospyw;rNwE;K*=%48lAj9Dfgw9~qAC z4Vi5U$GLa)_u)9Z!9RrKS0hP(499i)tP#U+!CnC&_pT+Z#>G?m4e-E{1$@X{;gw?Y> zz70ZNx;?%gUY2c-?}x-M-yT04G4yVapNnd9(DwLNWM#$nA^V}g*B1wzAq{Xnls7ey zMjvnXhXne0^D>^;z?*{*&_>>DMSpu3Z+1jlw#>%Ok6?2wZ(c{q9LJkm5YF+u`2`+7 zfj4PHaUyR@5$Q?1IS(Q@nKxfYM$by)CWa)R&6^!ya}IC*2Agwvb1oh~k2k$|{K#dv z;cnhdym=hr;(#}V`~CvFfx>MJ;JA4T#mTRZhWr&NgobNpNIRUuyjhQ8%;(KsNCp&R z;|OdB6UwZeAzwy4iSp(Qh`x|FYjJ}kUz{P2K`e3Jyo^Yp!rmG3Z9FxUH{2au#G6eJ z?l9iq=NEjNfE%73Gn_YJq=yF{4*4f;M)2kzkm^X@Ook0pjZl~i+&l^y=JDok#LjP} zhCGA}hIn%)gaGBV&XAe#p3j@(`51f+`94yJW2c-U+mVYr-ta6eKIaTAMu_3Hf#7Hq zN>K=-?j@)y;Y(1X{OknXYw0BRp8u2Fl=I@Gxne^b0oyEx7$a_$00=Lb$8vX(u zBY%Yw3f#8uM)(QLA9*H37r3p{xOI-44$%f~>oum7GYa!iCvct#4&D&lu?+674DP(d zMJ70>^aW%;us+5SmKSObJl+J4W%twL`q{VQ9@25IVIdCAVY>h4kN9!V_Q}sZr=}qH zoSH}}&WiD$WE1uKK;0YcupFEX?H-mBw+G@3F*gtcx{=JeD=1=~NrSSrN7EGhj~2>9 z#T#xR=ah(hfrymF+*vb7{6)&Y?SHSwXo6 z?ASsut3;fq!a^|Rl{q414_L9ReMM%x(8jg*yU^ARf*j2KU$6{1hvEOc|J0!r|1VBu z`2Wk{5Pog0{}1Gxb-08%Y+}IS5~wzr!zIwUQq6XsMgAPz+w3%at=(94R@+)qra7!mU7j<;Cr<-b8Xl#czLpe0JEvSJ8)HL-G zJIY;p)$;Vxbie0E4@0S7Q+*rsT-J0ox3{GmYMNW1!^%~E(c9POdGFl6w!0zSz5r^T zTG|(S)=<)yf_@qsVO>pEjrnwuFKO{+c0+I9+Md;(Z|Dk0(+iYr*DOFxHMK3!^Q1)Y z*HPcde0UZ%P-wnsf$AE!5Yqg>-t%IfNwqhp+uFO*b@g5K(C+PO;G%q}@40JHw&!Gf zYezeDuXnj3tMXhKLaM8#wz;Jl8uOei9S1gv$=13wb$R*XphP;mT~+RklUZ!7Po-)a z>*1A}dX&A|mYTMCX(-f&qIXHzIwk8{TDn`HS)*ZLy1S#Xvj$qEbG$5UZfLf4D~xUu zTdYg5{9leL-A5IfHpJ!*)QZl!g*Bb^Ml>DNuh5oBj0!)MtWQIoJhYv6nZUj0lU=Fq zG(O93Yin+!_SLNV#;0mpI_qod7Ny&%xh$(l>Zp-bI+T4mKxk*=GM!fNUo zywGf^o2q0p$-3(WWD-}`T+^6_3JwT)p=q6+U1PJexXE`u}_S!8O2 zk!n|GOKF2P*tfA18 zidAf?RV*wLwl-GD`nLA&#wO24mfXL9la}g?>TEAPtjyGDo?6)4m2AqDkS(ePR#?=b zE>;##rH2iqtsP;Y9=am(a+0YhS+ykD0!_cZ_Qh&8u-maQw=}n*F{W$kp!zYDa!gwo zB!(24v}bLf#S`7o;ct^^t#Jkb3bLWS6KdByM_YF*)97zg?F|hBYk+;e0UA)+I~S!J zT53{FJ~b~{9m+wgp!ePzc)VzA7&braaW>ToUzctBiI1zYtS}Aj-EEmJupYfTswGE< zG=-Ik3P(dUp?yOE7N7c<4x+8Qr6t|b-rPnV*SV6)wf9SJn)>ZM zul#q`w;;E^ETC95_LEvKZHCm_lDRd?t=p_u7}{HL zdWSoc@lw^?+}Ti*hQge5Wvy>CqU@PcGl1Emv%*NWbYt{LCfTQ0H$H&Au)764dRuno zGF@at4SN%60rDQG;r-b){RAsKuPSwRN{rO{I~$mk^bGciX(S_JzLL zkUK-Q*>IbUm8idOYOQH(PGZ7_xfP<~v=x0YrX361pDCyd&pw7Ta=KHQTA-NCq$F!D z>pdVJ%q3>Hw$M>C?fDE@P2PKq1#T)hrj?n_&s0l>(TIeaIf_k}tx>6NC?@oE!8ILd zb^AACIKc$l3%$85g(*Wbj`=}fmKBaKLrtCYytdYi=D)x9xX)82jq7`$g*xNKjuy~$ z+|b;ZTR}4Ii=8WUJf$0{Kgj0B78w+Jq3t!e2MBqtrdl9NnB5v0kV*UQf`uaLw=QXfM=}Z)s&W&`bI4Apbi+SY@6BkaJUY%eR)qZ$IWeA*|eaprn?{;->lt6 ziynbmubZ<2*MP>M(F@Q_i|u2kG1{oCWo>73V^bFndgMt-?!0dePWjAqeV#|=Dw9-i zx#%smvh%8H%`v6{eNFDV7E?(s25Zqx2{fU}i4E0L)6r3&ESVyJwEIcy<1>4GCLybE?xXI5=gunl7Xl_9-=dU(6bP%vM{OtxZbI*enB&qyk_NSrhNX{9>qYxH)Ddy_Xe32tCw;P45pV%HK9&<*0rcN zIH}6KwD2rdFVRr3nCi|nN!eTBWX;z6<%kxNHJI2}5$@pMfa$y!)gV?z66n3VYC4%K z)Cjys`h-!xs~u~*nl`gq#T+`*&VBW@A(=g}WY&GCBAC(o>zrFb%u?D2jKa-X0B1sG z14yf;`Hu9mMb7#%_{is%msg!N>&}u8`i^>x2A;&sL^`*?{qf~YZ%y($vnKIb!+r|$ zo%;V}+AXa(%otMBVTNcFLtFNnIj@uS_gMpVeA~cO`#Hz!tnc!5dp-xsK2uVrlWA_t zS%c!-2dvEzhFMzW_J_W}P_>#Hu!gr`rn<8i1Kz69bP8*F4#v>uE%416z;~L4%>~+~ zZwz;5G-j)*^rXAJ{T zI@wa&o|%~1ZrW|S+3TcCLLkrF31?0Zhjp2T&a4TDuZ+-7nc>B>@)n#Kl95DaAi@j6 zCQMbF-Xqp$CMTww@re-2RXdaQ!qA}L&OQgcS@sf(t`cuZ_`>d!gw)X7(4NlfTHHPe z!+1U3k=Ui3YODWLHd}@eMry#j3p*OPudM7uY!Ds2HWX-6g=XF)YDrGRV3FFy#2br#8KGE35H(g#xc++j=JpN;Lsd%u~#1N+VV@&A944qTfraxk5@+3xu{ zI$+Iq3C|04;F|q2o=t(L^A$yett17`G?4dvl4jnw;E!^n*?(a_q~D12ncXLz9d+XR zFY3JYU(|8yzk)fb`*fYN*y-cDf=;Q^2{Sfzm@=nM*kv-a9#AK&*=mA&nkT@FZM?=m z^EZLH_HE3~=xp`<)|<}y*(~b?ko_$!%W~lBD8`WeE2p)|`K^*=z;A(AfBCHu%Z|jR z8AEIgGT#P`Ct*27_ESak?IQfw%G@k=h}|M(#BdK54;7CQPY}-&FB5MN?+||>J}Lf5 zd|muNjG}-T-xzTZu}Z`~G2?E&O@zNXnfDVrMDC?$IE%%l;!1I?xIx?`ZV^us`OOBy zIa|C?{FZoyc&*62<@A56c&B)e$bE2he^`7%d|G@~d{KNwG~YPlxp!s$muS9ugnc0@ zEyEoqjuOX-6T~TExmYc7YZ{-QD>jO4Vz;XB{~^97 zvNLD?3dEt}NO7DvQQS?e6laV3iVb3`*d=~hTq>>-*NcaXM~f$lMkg`ScaF>#ib8j-;cM+$G)#6@a zt=KGfhzrH9h`plGp^R|*W!@wnE1n{rA)YUOQ@l#NQM_HeTl}T?xcGbV1<~kaM*Q!{ z%wduFjEcj>vEn3gsyI_LI-K!blg#tQ1H@(GYH_1@w0N?3rg)L~ZSgws7V$3e=i+~e zzY(7k&2Cww>kXMd5W|?>FrP!kQZXU!DprYmiTrMX&$WsR#I(3lJXG8y9xr}f{FZow zcn66o)RQtlFY^a7M=|}P`%n_`k0i0ncaqFi;#{#!JWyOtBCLLyj}yO6qU^WId^L&9 z>(_~B9>yI;L(byp9~-$1Axn6%Nv2<~g8w4*od1qyH1x zufzZMNVxx!wC>m?Y{G~8B>IPW3JHJJGS5~xpZ^=_0Y4>XzKYJC!MXO?Tg}S#M%VxG z@BhS4j`97NJ4a@@@}gY*7mCAN#Jk2>2Y@Bv-c-}x~6!#JzonK~QIWf;YOX+wCy>!}}@1 zW4ufs`xG1A!??H4;MSRq@bYZs@wxpH_x|u+M|cd2e_T7+@Ses!!?StZ6Q5BWiO+HD zMK}JvAXbI*iW>?SVm#d%U+tpuSoWbRNyE+EB+4gtDJmsH{^1IbxKWKk*Q{SkTQS&CP zY=7MudhsumQzIWG4!{&bU&cA-r zzWwz0_x||-{R}@1e)95yk4GAuDX%^{?5?r~>kHq-^7`e)dp(3G-Es?=Y{xnHEV2?X zz99TiK?$t!am}v{BIDozpRt}wQ(nQnG=;*~z+{d;!e^}Pg7DP$=@JQZffY2XrB$Oh z(j`*BvezfA!At2}F`^w-!MFL}-Xm54;Z3j)@92J?8puz;lwT0qnGeniJPs64sm|Qm zA}6vNZe9vT8{h@s3GrL@&|X0<+YA3htIK!9t$Aq^*vf3ixWWruzW8|920EPh&NMDJ z-S0|TZ5=WSz5>f9(SxnkL!P74@_iUHDxkxJ42|*0gND*y3;y<_-D`Yyg|X{}IZeAc z^taO3T?g~kwEGMG3#>AB4D$innJ(a9W48l>8HvB4zox%KhMoZ|f%z-=E1C_%Gx!_! z72OmEI`X0vYM?l<^U#u5aOl{f-KE8WVVEc2yqH+*OR$1y^)-$8*adl$3wmYLMDv}E zaoKnD-e_F;p}?17u~>7-p0T}P9l*S&zIE=^9o4vF1X8etP$GMa? z<@iIi1pC(_=TN85*)ih>cIIM-#AxX$;4EeV@9o~=e{+THjUfZfb1E*i0V57R(luuPXuWg1>yH}O(|Rdg@M>yetVwy6Ld~S5dZfT)0(Mk*RAcH%H!;&@{C7&aNjhX$(V7P zwrcIN)f<=hPU}Ci-~XM_ij~u9`j%ra-@4?wzTT;Qt`3B0P>$5s(?6}Zs(-`A<*U|p z^sPG>Co=X=OReweJEURb+H}`Sd@<3ndSidOvu0-NjA?y6)9`|ru}te(ziJvb+2UV+ z-?C{KD5tGiwsBg|>ec`4@h)4_zp8&)UGHJ5mi113w>yM?wvU}M zL%#Xc34+|vyJo;=O_!T5lK5Fu@%~xgF#Va|JDE?F;5Z~)6f8-EhXgm4hlfuNM`nbF z2ahZ#hX&V`<146XBSw!37v!)verzz{|Et%nTi>6?fwCJ{_4O_{dst^yW7AV+GrG4Cf%}w9 z^~l+qP>bJV>+12VvDrnLO1I)y*JkXE!0teNLt&?dX%inp{=z;p8MxtNkl(Iz6Km7C z?8s%SdtE{Fq8cyP79ew)tU2&{<)%!wDG9SJLu$#gj{1g#agK4?1nA^O*V>%yY`1Y{ zWXu3r66s~Q$x)!@+kfWn0x{*|eHUW_;q#xojo-Fw|84-54bNTfSNh%gdzuMx{@Z?= z7~<#P^e&oYH=pI8$UEX@J+B`oQyzgkIWNDRJ2{h-DN*h<~_xIWp92* zh5t6$r)19+6vJ66u8=+7LDBv&kvhVd9`pMt>`#^b8M41vX7l?g+^O4({%?@IS^dKP zHky%-pNecfG~=Hkipmh{7(=cu={{9t`P0m4IoTqba)Q~E54cM9M~TOXCyA$uT!Av2 z8^v42ABkLz(wz%W@)_|@;&$;>(Ucqfy)QFY7JSZ>BgmC3&Ev%>qWL`>_S0paB~oV{ z{kMxt#O0!?|5$ONYG>ZN!#}S9@7rN-+6j0**Al2_H0r&@r#SQf-kn4AlkvwQ;Ifz(+kpQK5-adm{rxxLL+DhSb`!VkQ;hl@{*gr5l(x&fW+%voi{P8*$!v6@ewin&_ z_gm5WI|u#Ee%6!R=B?ug)4k#>?w@{Q1*&g)hJChiv-Zz&*0J9x&G=2zO6w z02wDQ(wA&!3H)t=C1uTd0K;Rx8K+NN&a)VgdSGWS8y=FA@9n^6@BYA zVry65p?EL;Y5E+iDrQ&COz`@2eU7iUm{fW1#K++mxx9wFc}^nv?u21@D~@aZ51dJb z^I~l`zdLvS_21w5{m>h~D|q(%!6z5IJEaCOTf6u1zTB7OoS^-nk$SNgz(7u-L=8?oT!qj2x(Y@}i;yzG7!;tn2+Hk&tR zG8pM8YPy69o`LM~;`?Zn3SM@KxUrF2V(e^;pdAuKALfboNdq4gw*uwupr{Mq4yrKMQKC&E1 za3Wtu7=cI-^*S%I+fH~gawYQ~`8!<0k-f*@`AE+Wcs6o6(h!MkL5+<@9>M>Gk-PC! zEYgk%Nj!2bs?Lze(-7LwNIPmxQH1*{hDDl?wc-dQiy@(N1JMRVab6%g9qBkf5S@v@E(k;`AfF2Z(GrAtQ6M@I>AE-&y%UdL5{M?? z^UXjsh@jsJM4yA@+kt2R8Ga`aJqORd3oq#3_RouQ*T|iDQR+9uPZxI~zkdxzpM|it z2czG{b1w&@H^A+cU~~a|{w)~og5|5h=sW1XUkgU(A}g;4qgOzpe-B2tBl|6(=vR^W z)=>0ZJkS=3zKJl~Ls1@`+YyQ$iD>7CqJ79%XDG_OeW_4%CB)ekitdeQyF<}_RGkH( z=+DrBEDS|oKtb#uicW?c7loo*AhQEP(QXv{mqXF_#!}Z}bTP`|rcm@pND^L9^&x>H z!_ixi_anm5rx4$f;pjGmvMC%*!prZ&QEt)tLpb^;B|rOgQ=|+@1|bixAOs z;poGtmCuKx+!XXkLG)%M_tAprp^*Gz1<~^%^2ZCJZyy22%Q3N%ST>K5TOISQL2i z`Xz*NOlhmjU$t`r;}0CGWHi-nU=fYh~E7{m>A zEf&_pGj%N%Rv}XAS}f!N@YJkTj z;eALLbuAV?2B}ilV&NqShp8^y#bgFIw?l^1wOF_SvGa%7!Y?C()U{anH3)&a77I%d zDRnItevePXS78Jxq^`xnvryZqYq9VH)CWH2#2!MPL(sMOD9rH(@m~*eI^-1Ggq{5P zxDV69xEy6&@|^rb=t2wgU;GmIzt}n#IpI@rAHN@#H(JXACwwU_8O6QUvee1H1@~cE z7?(dF2Zm*L2iNpQZC&m~@%7DEH!v5DvbxGTCA-C}r$ z#8{>=keBZi-NN$T$y($&MStT{<7ENg&ah$O(nR3kaxH1uAM9$E>@Lq}N%V_;YKR{Iv?~@qELe2{mIYrN-_XvNgy&j|xKq@~MATS|m{at9)QE7>T11_qU!ih_>#Rk@DY}T!)>{kY z>}AxyaD%mgbbrKH8m&dxDY~BGZn733r|8#=w%J8F6 ze1NrpbnZm=8UC`hfOOheW{a%_q_Y>~9{!3=6{K@7A4yvaNM~PKEU^}l&Z}&cJ=Ox! z`5_V-UTQ5MomnilW!3`H*~nOyTMJ01i}knHT0lBYXyD-$*20xeXCln`P_ao;m!uPC zP%9HL%8k-FG!dPQE~RKb{tNdf#@-5RQ+F0Js~fBZq;nuGHd+fv=X8qeFlzzntY@kY zw-%7jsR%55q_u!_&SpVvvKEj|DWg5gT0lBivGg`u3rJ@!YsOct1*CH?E5gy%0@C@A z(H>(hAe|Rj|F&2QNT-ht<~VENN@qJCy!6WC^u(lD13S% zdJt-N(H-cA!{11ZyC2q}z)nsPl^=)CuogQyMOV<`Olz?Nni?(6vKHfJ+6}1{YY1QBKh@tkf4;i;*Y; zT3lo;MxY$odtGcTN}M9Tb^X|yVhEuwmiY4UuP{)TP|SIueTNfr|3+k z<3?)%!>~~JltlP6luq%F>G{+|8EZ!I5v*r7C1R{ttUk9Tq7Sh8Y+($s_a~xbIiuK}!h66D9uUp3 zeCk)$0zC>wlbHeyw7QfiLPLl9L?V1F z1NaBq$y4f5reh)#{(U0Gpqc9z64C1!z-{ct{-QiZOP%4(olf|#HjnTzED?S#5q^vT zwo{CMN|bSKP`n(iFZ@a(Mi(c}2%pEF8Bz-v!JCQbPDpgo)hxNUb0T;z6G73_%-TP# z1%fWw5(vMZ2-m~D_#-CoABnPV8t$aw!$j-=7~EM3txc3^3~soOGYto4EJth!g-0f$ zKSk3R$vK5H3YF6dPfCX*?uRaw0rc z2TIwe&kdCAPTLb*Pql%v88n`hD0vMjtP7N~YugqmWfi?5P_~M7^6o^*K?vcRKq+h0 zPXlEeX#0qp{<{NZ$I$qw8{j>GGJYZuek@V)A$V_~l=TK1vd*WcKf0ds^2#ow@tH)) zpWrE!SIWAvC9mwew0$*E!ddjTyiyh@W}#;G_6U+^M8B7lPx*#vVO+Lbmr+js({!Ol z>>sSDA0>h;9lYCVgn$a(K^rOv%toO3yA553MiY4o5jv6AFr5iR{sr;mMXpDs3r51| z5JHi=QKR!C9TB9WB{EgJa?+Erm>EXpSq*#Q+j9vKTiLn4>KzQ_q~hNt{J zgAqg!d=W!x{yxPg<9>AL>-c}nh4^nQBX{CQ;s0y!r-|XXZy=Pw9>eLwRWQB-KeGv} zKs|Ka{aIUgL*>}92ARR`!7E{ll$#6vCaMYE%Q=D7Wej}}m?ziSd6wR&&P}mOdicZ$A*n`#`$+g z?mL<)%y;;h?Uj6LN56M%rraqO=*A2z0Vn3gRfX>EvmC!ept7VhaC>d6yLA89qS!(t zazfatEYYJA-JO@HLB36wJ7>qAqb42SkqwAua@Mv_WMN8q!0tz#JUW3$clAGon#YSH zQ#t+uPB+0;9d!En-KBe(-Sc^Q#vlE1!z9}QTMBkY5(#tLMNGh7(Af~U6f_sQ57TT0 zdY1aJPE`kL(*R41{N5GiGUcSpKkZyd0Y^%dz#d z1yAAlq5NPaH*yBC@}81k6pp}oVj{c{zZB)=2Y1Jlyn|O`L3Q?diTq$;dAJ1oIs^M8 zuxTL>s7XS%Oh?7SZYmUqY9FW`tIw$Kt;x~kE&V$KHQ#@db}>ElX&UdLv>j^Oo12qL zj8&}iIW*wgN2oN%Xu2Cr>#EU}1MQPvL>qC{cy}ED%`h3&rB(@y(Wk$lwx)~uOx3q! z)V4|K(I>0ZhmPgeOvwzU@u$jDSwrnH(7rRMQhl5n0F|;`N3QR6pfJ^^Dc`4MABvUS z8et_$rEgTX&uyBGogHZ^e1;C8Km3`1=6Ff-v;+-Qy5F*(uF97lqZ~-; zoth~wxL0Ng_G7f|*EDujCTrXb4Ae>JQ)TsEpo1TZ$WlnNDOR)~E3Zs@_%G1L4pXab(nb4b;bvlJ)ugx6sO;Nv_c#n5zzLP)$fym9D8PQreGx!k0Cb=4Vyi z@2|fL>!9V(oZrEU=MNLzhtVyat$x3=D@jdpZBAQjbGoT#?ef*V8Qo^Kkq@qupS^5T zDyL)nYzq4QDTY$uCTQStkJn($^C$Wf75Mu@Y3=AXN~cpTH9kG@HUl}T{RdWPqXQF> zw`Mg(tIzgxDEH4)h>uaOs&27i5bgiiMxS!nDX?AGG}K3`|ttG9BNuxvy+&mkvL0tv~Pks@E`&#PSKMs zh2m|;&aErFRQsOHoK9e+>P@@{*SDGJzCOpf1ej@0Pu98_v&oqSoqa~G+|SwEcj&^t zRU3M}B!1>I3Qz-m<6^6!4=0w-9R36AMY2OPb??={UN*~`6`<0|hiBanP<^4NGN7lx_-NwyMQ?=hdCzDt^7I8_m4Mq`#!fQqd%esGrOI2YO!w}p zy}KFS-AwNe-MZcm&i3x+IOwJQGg)svFxYtypL8aM$^Pd(3xbOu#_rDBy+Y?Oz(Ti2 zL)aGYO|w7YJP7z{QvYEeQ_qc2^V5%pFt34_BzF?TDaFUkh3tV596`J5+#aiq3Z?O4 z(94N^l{Uzc5rbG68KRKBh*Km`X?+8(Z=R9;R@X68T`&D^rT)*HD`8&YX=33noM&U! zo-@Am9H34hwhidiVvLPvNg^U7g*jt^=T5->cicHsC+C!v7FT66YAX zFKj>gBnwl|(2=i5XTP=RU$?PuS#Li&++-4!f)$bPrsukWeqV}*7q4w~X zr_Rip(e%+Db0~*DY`!(d(2|^|0DRL94c`BEW=Gmo#QzCrcJ!*FF^jLPan(#=yk5>^ zXz;<4?cv|_fDX_UY8V zS;K$%@gCd={1Gnv*uQybd`Q+e>)gY`y*>8gUY?qv!%hgD7(6NO8-agoy)oE!>AONk z#{%=}UYY$*GzYOCBinzz@n0d|?oKGr0RIu=p0VLBsmwJ{j|{er`7Z1t^_dtycUWbv zptpOMp*dI4PZaQLeOx@Yl2%qF0vOHv)lE}kuK+2!QMs!2$J~cW_#*^67IYstU z#l6H@u~F<67mGdOI`J^^tKw*Cwu2Vx$C%6vq`q2dT}jF=FO z4jK42I!M4O+2eac6V8{!I??Eofj@I52e?4?=1dNljV>9`oXG*MmAg5U1LjRKZxM}7 z8Q7mL^V#BsqR}Y>_bX)PhiS~8IgnV&J!zd4fwd|Kvb#TUg_ zL~fO)|93@nOvap#O^LK0B90KpiW9_L#R_qj_$9GkY!Or90b-B1Qd}nDb?pLnFWMLb#jhIpR1RlHohR{WlLyZ96F=ORD-WO|+u zeVP7$YxGsS(xI&q%ZDJ~M1h%3ak;zn_^c)WP3 zc$Rpfc&T`mc)fUwc!zk8_<;C`_-pZx;tS#{;v3@oVgNh5DW8Z~B#shy5GRTJtcU)q z#5v+zu~BRjyG3&b2cBCY^Lp_}@i_4`@m$fIxq;`*nH!)va|1MIZh+Jc!St9jH$Zdd z258RQ0L_^jpgD5`G-qyr9FX{&IdcOvXKsMz%ni_-xdECpH$Zdd258RQ0L_^jpgD5` zG-qyr=FAPyoVfv-GdDnU<_37O;x%V(z--Rk0L_^jpgD5`G-qyr=FAPyoVfv-GdDnU z<_2ia+yKp)8=yIJ12kuDfc(gm`7~#4fac5%Fd_S0MRVo`?DvwnUYv}n0iT~OHjBMt zpLnro&ai-g>gnfmzY$*$KNN@J%Obk(BvyzuVyC!F+#sGPo-bZ4-Yz~MJ}tg2@=JKe zH&)z3+(&E^)8cyZSn+J}a`6`NKJh8>FXFr62+VyL?|5;JxS#lCks3|t@2lcB#7o7S z#Jk1E#6O8|ieXH!7|tlMO59gmD6SNb6i*fTIX|EOu6UP7?HIIwMtofi;4>WB<8u_l ziDI=_FD?*Qh)0ND6E7C86Ymrs68|W^CUOeRc#Fje;&hSvv*_L}9x5I!o-bZ4-Yz~N zJ}15>7UCl@hPR72U7RPb5I2aYi?@sSiGLG^Vq(tlsF{YGE%N&&4CDcf?ysEE?{Rncpr`vBIM=|DJ@bpA}yqk*Bw0eotiH_*?-A_YxA% zm5Sr!zB`G(nIy)X4if&l#6=|jR*D#2O}Gf!5MB-8Y`BM5A#z>DbnGoA#YVAB>=ajs zhlqWmS??g6uhEQjeqB6QyihdjF|;LA8{@BxWMakK^rN{OcjF)a@ZqL0C&WqO6frk{ zW*vy<=F%PMsuP>!zeOzJybbRAk~SVhX3__H6A#Qbp3kK#v9EWvdyvpz%i4^dME?S} zd})7w`Nyqt|A#A2#22OxmRn|R4w$t%X)i1_%rzeW(;te&Tr5lfMK@lP@rNS&RDZ1V zx$&}I*^70L7wZs)Z&PPz-ms4wKHnA45C0e++lD{9I+)p>>}A8-4;KFLHv7V3d$8dx z!M#5pn_-@dKYQ8mj)jHIJKgB-Xf|+N){XBT{PCWEcsYJDAGEjevaQ-@aO=E}u)1s^ z_}uuNpx<8`UI$&v2XtAtOJMfLy8!~&20O-!=)HJvz`cD2x6Zo=kL}A|){Sxa!y7Tr zZI=uW!=xA9-MF{U;MPgt6VLs5qszM81+zcAJrLd&*fBiT2P>Dyac`f&E%a7lK5Q$a z&+R{O?+@?02#?_~JaqS7c+cRT;jtd_qH3!X_^qWby76zjX#L%@=is^+-;qDSTyeat zVn1##TVLLQg+G0FB7F(iF?|rZmp&d9gY2z`mARS_9-{Uxri~Zrs~*k?@V50P=XExq?DPzJv<(GIETf;PGA~t!?UNhmg6VpHYdNhpfwsSj0_Kr2#gGr2Fn7Y17iYX z1LFca=1mBc+h%F1Api4Qgq**BDmTIKwgIXKH_5zOiV=->8Ut|$I>;=ew>PW_nw zafFYNDAS=Vqa$O04m9_-0(4&Nmv|nf`KkXyRr6Q{I2%nhpOSd+z~XM{%_e@9N&w-Sz6qwpMb*SZ-jNCEcbgFqTzqVaXDb zTxb!pEo=ujESnZc99kR*gc6ca0;UsMD5i#h=_T~gA%q@U=m~`Sf1cShclXM6%J=2{ zzwh_{zWbB*?3|f7=ggTi_0FBsy8v*_Y9B7qZ@fs`n6jvMO|QYJ;lJ*CvUhdwip4mn zF=bKTg0+i#mMvY;r{6)_n8IHa_pyQ1b+%3EU9)EO(gkbRApO7b!7!$3m*wDR;5z(|Pb} zoQwbM_#z)2r{{ede-B=`PS78nj`beqdo~!65Bak9*L?TGyUv4GLWPRHiCbfpaT7|8$W-OJUPf7u`5WL89IydR1g8|#~Of~Q#p zA&O|&$14OHuvs`7xB}CD4H%5~+cQ)UQ(wSEEp~R1X?U3JBU_mu8fzio{x(5uAAsOa zWU5a2{wt^~osM^FB_3e$5kMi=)RBG6QQrfM{RoffB+tJa=O4`zw(jXpE|rmcP}IdO zzQem%%9tU}?s$vJR_7P*qo@(%Emiz4i*b!7K1hy#Gc;kCvTP-O0aDSwq<3{+Mb7C~ zqQ`f)Rk3E}%4Haqm#*lqSiEpy4?KBQR8{sQdlHq2s-CJ!B6rDi@Aa?TSFyZzA)I#g zg?};s-yz0-rvtLB&WzxSaZ%p^y=#}P=~;u{)c50x2-Fy=V-Y402%uMx7Pf@lfV?kM zO(1`=@o&t;&|VjY9WNGWKf`}RD;qd$D*|0x1>x@jon9y*c4G2NN?2MLW2_UVRc@yaZ&@+=sm6sW&2xr z;;tIoI(Fvx=3^Hb6U<2uzikeUoD%(LQ*q++g28(^`(G2i)Oh!Y=ANGy6-7QATV#Dv z^i}ygMMfRMtD7PpnUQxMH_sR{Yw#YC@}Z0G`g~nU!5Mo39#axI;}pR4CFEjEaArn6 z+EkGGykM-E+<&L(@PhKU$E~X?;n(CFoE*q`C8{j0 zL7TSkn}C45FL;`E2MSwY^V`&j{Zl-n_W5{P_Vsuc+E*hsX5WRUt$ejOHanw1HoeBX zHosFXvOmN#Zb$LmM6o>r&%yT2cn+~IL$fQlT`(MH)5FPl`wr-Hg1rh|_C)(OXlat& zhi0~&JqBaf_O^v#cL)1y$hM=s8Yy?O=__Fu`xOkIl{VXMmHo*mo;;Zhjy3jf!0%?S z#B-{BIcjaX{T<}3vk$?u-aZ)`YOtRlZy1gCCwMm5tDw$idpl5`VGjejnfCX7 zqI=l;;W^8G2y(XCgHe%f_GCO~+nZ3&?KV#*b=W_~b5ENmGdpcMwdk_>O+mMPH!6FM zJp$ckCzd?6Kd%bAS6AJbUd@)Z7B) zt!ANp8_KfCJ`xi4*?$NA0Q-1wS!@r5qz0GSrZ?I2?PHwa}f%{GNuaWC!y9Xt`#l8WQH`&kNd566M7ILTkBRuc2 zH{f}=y2Y& zKf&|QHvM0`WnYHp+xB-s`5pTt$p5Zg49f4>4@3Wdv3Z*9efuQX@CWuKcz$Sa!t*2h zIXpkM?}VJ6*e)dh)V>uQ|7t%Sg+CxW3TZ#H>%jMOo9EU3ZqqZ+7xs~O|I+S+y?tfx zj&gl%p8#Ip*afhtZ=DHv8m99EfC*1Vu$KbUc?Tc@cSEp@sOdC;uw^=bEJq(=I>(~X z+NN_cfMYu6U=}>cbZ!K2P3JLyBGZ|U>~Z9Sx{FPx5%oOSbXpKM)O5ZJP+~gk5$BoC zc>txRa|=M3>HGm;nCTo3wG20%HL#Kqrn43X*kL-C!#?*nojOR{YdR-E+yxK`sp(u2K}$28eW3CK!4EW7A|F(9r0HA+ z@O{(S(}X7+)8UEObsz>6{1D=z>_?#}Q2o)SLr(<9n9e+8Kh|`%frTAsIy}nsBhxt= z8P=Q5uTUjFhA$|T;U}iUV|XXR7Zlpt+i1SQm zJPLh2LNKQbp-<4f2;Qb3?!_o3lzfTlI6z)%I;$YWWuU_5Y&x?c#1*DPpBPt~&KaO` zmFYZlqS-Gd{$){hugwtJltq;;ghg)wECiP zpi=m>S<-=kQS@^(w!&x3k~s)XFWMDs3!nAl)RUy{59ao+u2_$SF*5dQ>4D12G+7Q`Q7-d7}VL2*k* zr&0K-S#mJtjl`d3>}zJp_YnLr8h;p47QSwl+(%*ISAmcv8?qiR@T$Wi5B@FQ`vT

    x8;^xt1$jp?MaWfEe1%U-z1sz5f53%)&tDv&;+0fxC zh|D>n!Bx=3WN}tG@F7=0-q)DN#=@?GFq*(s(CBB+XL8RZtd*yq7WQiG^GR4TGzoSlCri zX?g6Ga*Lobws~|N2jpbYgsTpSsu7b`7fv7o> zqj6WjK4wd zIafjP4;X~2pu-_yqdAgY+XizaP4q%D{uRyaj&kn_P`K0_Nvqmq#$z<2oU5RC34=LT zLGdvR!d1|E$bYvvl6GSh#3vJ*a}^X%G6+{eD_F>ak+h9<1@URb!c|Z=up0_SvO*0w z?s^DdA1ZJ?Uf?Q-`n8BqF>7@UTm|(phKNC*v3_LsdK!8?v=QQgB876NB7;hWQ3k|u%or#ZhNfu+b3`%p`Op%Db$nPxpn z0w=KPz9$5DWH$EkG?%1F;P2C%4@qD>d)+Vd3H)`MRR(@#oL9#_69RwYQ2O;Wm!wI+ zs&%T6$h(hSZmia?h#@dKNMP1lb4g$nJHAM*ujb!S%}%XL(j+jX)>%ygpRoufLI9rn zNT8_JqEEN7qu3P{3juo8jg{8ABuxUNYn|&zU>cMf8zTg47&-_HueF{ffvJ>Wq!8GR z)1$GqE=iNXcD2r@B+!K-#U|%VFuv9riGIB7GDbkG8z##ysufvYK_1ESxdFmXhh8L9-&F@su7qu-a&m$)rhF!y-OOqYXpwb zCOJ?~(})7Ydx{0A)dXKsn+dV<+mL1dgWFb_;ec=D|?3omI#3&7JfPEUkI$Nb<#-Wm9sJr(K_%=_@G*AZxV=* zK)(>+kIiC-LCuI^5!Tf@2a~{aBydzdfg@_Ivq-=tf$s}}ao`*~rq(5C5;(C|Z5(>7 zlvS0%zq*@UvQL3~EpIhs#LB^~(lB&VY5Ndpz z1C$#1%8f!6*djv3tkf}MjKUtq5HW}z+G3a2MySG3@Iq6#59{dQay-l|1hRK1z6I&* z?P1o2eH$hPru{agD6p?XH;m!-IK)1Pf0@*bJ_VNP>@b*_wjti!$@Wj{4ems7KMhhA zzK-`XV_>Xi+r9Y%Hhn`gg)x*WR_7GdsL%=dy*7L_-aBiK9guLzDq zBI7u`jK`7fZtu4UA+7pMfSQeoJ5uPqhB0CX{KGbl@e7u&G0eRcZUMr3;~$i!<8i)F zTA(OhMhyOqNo(+cWX7Emzf8ry1I(-VH?{*4<4eRnh5zl%4l`*?W)^Ns_(6ZCjS?$W z6&O22??Zwecf~A{|AVHwJ0_5t|ATgezwn{vq+-vF6pt>RGkmBy@P`op^nl~P=QS_i zS)QBkunspA<@>3N=OG|GjzI=~@UlP**6#L(Xm@+~CauM*KvYS--#sr(D{!G#n(ucH zKJx+*P!nN(L8jsPe)r%-&v&#pQv1~#MK^keF*@u8&p-VMKYHQQpJVb<@IdIc`EKoo znk9wPNBp8*IpZ4}PR_*TVFXNzF81huZ#?h=o$O8U{qIc-XA%E;lU$fVNg;D?=eydg z@)+1Y#oCJ=EDZy>`r+ne^ z5_I6-GWw15q;vVoEC~JpLAh@9R^0glSrm-)9rh}L;9Rv~Se|VG@ zhiN+z+8_UP*hjcTy;q$}xJtbz&L!NS-jlifETMt?Y}@E1 z__HAt;O!m}<4+Mt^Z$G7`yb-5uV>)_iz}4RIlu+|t158N*#8q3cm1muDm>*6B~F;PtXQ~g?V`M+-~Xut!vD~R-~U{Pf^b2L!`JAV zHaqu?ZX!7MjaG*0?CD#!5Qo4qabN&-*t2xS0V{pXLg=?=;qqh>LA1=UlR?ZkUiwS&_TwU~m{53>I6%B2KwwMh=-` zSrZHE3Wr<6sx51hHEc8-4Nmmn6tL7vZ*N(VL&^)M(eL1B_!g|R;$_xuakv^RwT4w$ z@xpN)-s9FTlcrk3cCpeG)-E7tz_VcFusy7)d?~j^6TnYl*zce8T7y%V?VgaT}W~c8AvC0rfKTWL-Jxz0)X2YQq9OyN7HtyBJ8+qye zP2Vez8*Ov12_wi**Vs_mqwWQ5n%&q_AByQ}Xi4C9+LjP%Mn`ugF05{Y3lCgey|swO ztwl6#Euwi~L`OsDw(Rgli<>YmQ|Eru`13=u=$HcvWq@mSZ~3Lk`3 z1Ju{m(NZ};4hWnkr{L<^Kosyw_H=_+9x6M4DA-l8PMSOCQ)hHj7^H7(t7}O3^y_lE zf$aFEJxB!gB>XbrK4Sm2&>#|;Xzo%J0$h7XSI?Ze^Lm;ZXAICyWlvpOh%!o$Rt4tm z*u32|prLd@MFuDcm>R%I-Co?;RM#j!DdAP?L58j_=#$C|p&D9Jl%Wgi@2aa5SS2u# zyP#SwW>=+!4TT7Fv}{&w4PZl2xB5#P4uh)KTWG+cPVT``_p8mdtYvDBKFbpQWaGeA5f@{<|BhQIop8NxK zDfBZTjSH$eghD@)K|AW`p2L1d`kOjVu?G#Sp}t9r{_I_f|o8l}I>H9IUauH#t9(k%jfi^P{pDs;BIV26zL){70a{LtG!HaDqSJJwW z734+K8!dJ9c|911g3ZQ9RN$7C8AJ>iAA^Xn#rn1&q?$Q)!#@oL(oU_!m2Xf&_VqCQ zf!*Q!Dh%%}^Q%JT0&Vt2bKo+xvnS^dDxjpsOEt)$8_Dmsk#%#m53r}e&;}GJhzN`& zaQ6~is9){7p3Lu<+B@1iaa+Ec<%A2<5{?MZZ1N(Kq2lL7q(TuWTwn-c3(1QZP<=s; z0i_Kh!qXcy*ydXey4s!&pxVQfF|4BpnlIy?ayt}MP*>y3mbNxd+!|Zj^9zvb!Q3g7 zl0!)T)Q8rE0mNWbJ`)sl@M)TeVet_K*}v92wN36q8RAE zm7m#G3^|c$y|z!v-oXLCz)drvTsgyPlkopVy+|WGhnJ=ujt4u(ZlPmic;@KGe**bl9bT-ZC>F8|lhA)tw_O_nZ zj)tCkxStR4YiMd<(}kzJKseQSIWTShtMVX`T3M+1-#|tUGvJ_6HK+#Eh418;y#{8= zC@luMyb%WlVi&%3RfQ}y+-D+RFmci?e&#^Z=qvtlZEl`mU<+z%s_Vi88Gd)@v^Crn zz%+wCqFxG@ug8HCb5VC=-u#EFmeAh7z_pnc3y2}2+Ml*{&+ZB_X>3>4friAT4x5o`T1{wMi?NZV*DHMo<7yk;d2=9^ zF3WJafF3snR!25h(_1m!j2cJ4j)TAouJ>Uzft+IfTih98v+yIrb(EJQY~**;j0&Gz+Qp~POOzLCC-oX zr|xJ<*gHTQ>#Ad4yn@{Ve7*br^8$^ql%4aN4Qvnh_{}G56RKy)AM`-i-(5pP%-eiI z1gEeq{+7eQ&I7UO0kf{$v=;JVgxFKfxPm2QzICGJg85cp{4iJ)iW?HG9n>~jsdBeU zwdCsqqd`xb_Dcn&$n*}qy7sfE7G3$xsH3f?Yj%74-c6Km4&7xUkzxbW?dq;q+fHEv zQ9~Bz`?++1htR6PMJS9?ZPrw&rw&>QLI?6 z?0TUA+5F=7MS%+P)P@{M3WpYre!mfMdh^Mc-BnMusjbU_J!-IC3@>R=@j-;1S+{_u zS{-k;`K#QzosBOl)3RUw0 zJ)1Cc&UF386VgPJKT~Yltd~hCQS^Qh+FR~5&s$#(8~Be!L(5@8I3wntuhmK4Sr;$`gV&O{6P{mp0U3P zuD%K)l__qyx2%K*Le-0gn+&z-fBhBE@XM3iL-j{Rf7#wu2it?XIFV)Vi7G(l`-4go z3L-@cNei3yzuMa3zJJq-0o(paj@3rqxJr$~O0yxNkT6*31_Mb@gpT&68Q4+cR%Iv~ zn$^H>t6(#j!_4I1u3D9PcIzFq{Hoy)%I3$y=TBrH&*tBjgw>1$Tn-M{VhZFHm2Wj( zeG50Qvn6kLh4VzzA6iPdy$0CutUbVn=j{PDJaZ4Q;kkQ&4bR>KY`7~Au;K5NV7T}K z0CmegW?-KYEdPS~R3oQ2D23ALE;~>ecwp((EE+Ht^F+jozW(0+o~8Y(ad#b7pt!F! zNS|xX^syMi(^Rk&A7Co5!>sCxF{rbybNA8(1R(%SCntcOUE-@hJs-`zZP__JzOY=l zw!e4v;#|5+?hPC8LM5AftHD%8PJZY^AE9zUV*d*>bg3A)^Yn{242*ewxU#7HJqx6& zQ3f8AG0!f8irK=Qd_f++VpNj~kZ5|ren_}C+jH{?mEW4S-dJGsJ<20DTdh`8*eKNk zqDM9`0~tc-aMNHHm{fDR|6Ml-VuK{F!O+lgoJ1Kq_A&C}WbY||jiY9gdSxE2v%H9U z)gStk2fYMGzuAHVGRivH7qnqfrYy^M0UuOJUR4M76(mqy_Eu!z;?v(YsOQSVU%2Jj zJ-4OvZ5#{(I}FbUXVZUoz&9`5RwMlF3YO46ZZhyo478{!)r*La?tngGGO90BOSb{L zW#Mj%wT5A5K=MhEb31B_dtgCCxcAG;F`%45j%MROcO9j=GcoLkmM2;D zX9Hg9ii?hk91E|r4aMaJ^~FX1x!cis@HY7TC+@GrvF^|(s_vgVIfv0d3GflTKb;5m zgOB>XK`zMqE%W1Xm@o8+s9X91#6Q39582}@iU0f$9G>4AU5|c%b&3X zp9nlnkOFnO0sr(hi=PqXK11-fYc7OeAmE+nxcS+H|8XcU4^8v44n&4RKYAwvhbSkm zF>nWGcxPjaGe~`MWQ&n9z5K`f(Oa20sM|yb;fEshb#JH=WnfNJrpSLLsk zIw-&|TJVD%1(C!kKw-xbB9bSx8NZ9b-2~PPoFQ2VifI48jx=tIgSi43s^2;<6AZPgq1&Az&izhzraTXJ}FT7vqid>C9M3}BCPz`0)8xb z<{vA`fwu{~TcGlL3x2!{pZa)O;EMuZ z75J9G_XR5dw@Ckmgwb)S{DlIG1eORKAyE0jMZSp==8v4ow^Cq6;8cOUp@Z?tA1>f* z3G=Rf;`bJ~zrX_oE)%#~;GqJ)FYp+F#|u1J;Limr|G1!kzJxCoc$L770&fwxN#MN# z`Fm{2_k_S_1->Nkb%E~){7~TE1b!uuxA2jUEwET%sX*m77xCp1-cI1o0uutW0;dUV z6u5^#bq^)z%$4xI0v8BeB2f9!MY=T-K3w2BfyW8_iNI3@Du24jcaDTF6nL3H-gL=w z-XQQ+fp-eLU*IDGpA`7Kz?TKSDNy;>1-*|Y{JFqy1V(XwpZo?193oKp*#&+Z36B@J zgTP9G)dG2MF6lH0Y!%ogaBqRV0+$F}Dez!{M+!Vfpz^y5x~EF`41pU2ULx=+f!7PX zRp4C$l^ET8hr3phl=!v$_DaFW2C1ttaVDv-Av zl8*Az3)n8OyD|!%5N{|oFw7X1)eSN0)gsMSfsl~!u%yJ<+xp- z^5cu}!xDZ{;0pp@75KKm4+VZE@Ed{3uP^8nVR}gVo5W5DR85}-wM1_-~$356Znk4 zmju2c@I8T_2>e2zY5Q{70tX8mCUA_vi2`>Lm=L(Dz!?G;3Oq>Q4+Nel@GOD6x0Cv~ zS>XKwdB+LyZwmaYz$kv9P5gL)RRT{Gc@@CEbvBw_X~VZ zATFy`^uH8{9{{WH7=cp+)(Y$p*eh_gz@r78EAR?|cME(<;F|(J6KG@c#qy05$e(aC zyqmyQf%^$uA@BzRPZoHdz~2dcP~fWqKM@$ka*XuL1ShjZ0(mzu@iPR@7r0d5;Q~((c(%YR1>Pp`QGvWL zl=Qw5=wL0x@Hl}9feiwC1TGVJjKI?cUL)`}flmwkSm3t;hl2b z!+iSX0;dXW5!fs6NP))-JYV2#0(mtM<$O)xw*q+w3GovJrUf<&oF{OJz{3O{FYqjZ zR|w>VE~NLIz&8bcBXBU*^o%bTI8|Vaz+Qnz3Orum`2uef_$ffovVTHxOVmf#u;(yI`7 zxWE$xo-FWuftL!rO5jF;zZdv2A!vUg;TSgfxNlNK2tFPm=6vHNTqSUKLi82wgylGag;|hY6f@p>c?jUd%fhmDmfeiv@2wWiW0D%VyTr2Phf$IdGAn>OGFB5o`z#9bK zBJfUu_X>PO;1dGh5%|8qzX|+8AnrC$<-!k#6;%5|&|`^&F)cL;FlK8#AgIy})Dw~@ zJer4sP_u&N0w)TbEO2Lml>)UMr%Sj|;7oz70_O|dSK#|x-$GthKj?ck|9{IzPR@UL zctg_n5WeLv9;d8cNmr3@ApVce!v4$db>P@7>~OMIyOg9{zFW!7FL{G`AAA8QgoGs&p-DMKJ#$JE$1U?jIoXJ!6!q0Xihl#lOgL%W+gu#Qhw^SJ6=O* z?t1FA69DmEdDgY3-R$l$WaG7;f0G>4de*fmT;t#H>7<4U?--Huf%_qH@Ar9h)~XqN zTg73SoBY!WDmMlkiuXt;Y6spNZ;iKYM9%c*LpGgtZNoc75z;&B+6#eW8Z&v;wc`Ov zukuz~$QmY`SlUeNMZ{ji2j3!`Ku5(1(I#Ra!Xx%L9&ARo z-v<`5=~+am7+R=`!R7rQGKPrQ4S3_%OFGXWyjw)5JSiQ6%ls!YhKPUR5!(Q=2kFf4 zBhbryL@2VnMN~1wJ^bHejJj5o;$Ng=qDJBAj3Gkhxn0NLhW_6$h6ok&oQ{bZg%2=> z2&cf>kZ|~g&!F~>Cd0ZQu?^K%V48;eJ=BzSp+*2(RA8N*u+m5z=hn1!PGSTT$B!I} zz(oo7H4rqMsC8As;a4wi1@TuWwxQOexL(xF5OIx0Y-_l)iMUQ9Mj7rLA~tHoNWRwYJ~5g$ZbnGJwEmE=t|Nh` zS%jw&!xO#nj<2)vxIJ|zL}uvo7OfjJnjthW*_ zNz))cOgQ|e#Qh2KSRYIMW4+@}MI*F6)dt}j?ghwT{Y?;sC;%+vy@WLnx#JsH7w?OO z{1ozAUnN{Jr;L%L(@z#RB9CPy{X&}TVodAXgvBpN;-eX7CjCOvfsPeRx+F~k#YyKL z5>OHh5dyd>(cPWeC=moz3W|f0);pwlCLUIiP`r$?dr6nPNO5%1DMW$YM@V2yzDUE9 z7H=Pm52XS|3V~giaBR{gX%g5j>C7O3Z%KG^K7sK`YZ(csxQRmGCXAcbE=iZ9Ng$PU z=uyyBJxC^>KxNXpk_4KIkS8GoHc&&^q)XByP?vNbAb}^bhOip)3GAM<=$I+~L)u=g z5TK7Yt10P{GzqjNok1v->ymJLK7p2`Re`wpQY?I}Swi4MCfqaWk~9g-Pdc+mU>>@B zYwvsl-AQW|2^2GKt`OLr<=Hpsk~D2^Vbb{t3GB{h-P;%4;piNko`xh!@twux*mwwT#Lo}iQJqugnp&H@0 zxC4{cB#?{mPdS$-hml-7#ny9p(xo)yc~sI_NS-SZw2qNdM=ZlVj_Ns1BhaPZiX7ID zv|f-L*7^OUwVo_qCDnDJm(^^O>ys{-lf_Sy&h=#R1E|6}MF>PuibL7VPRplwLehGk z6we{I6NREhMg1)4k{2nSm2_gr>+*1c^(##Pic)@E&eaHC#$P0@osl@6<&bcOP^@M> zY)HD~MT(asotdO~8uj>VO#qQ75?=ne`C_QoCI3fPH&LP zXUDUiRdtgfOmsXmh`2=%((zoKv>qdi2dMOG#XNY~zIAKTC3DJnSJHWpEZ!mOd-7$x zJ!uVv)x>!}s&$9RSiyw%C0&vxfk%_h{z&Bhhz9X^K)~IWBK<)SSk1eQtj{NP3RG1; zNj;+xAP2qtK4~3Go&}WiVd41(Nj;l%DGhnPl60;m&!_OPUK0YeuP@ma-^i!<$D~Dn zLh%d8?N35+N9KGp>5>;IzMphH!K*u!GJdED_*L~z(qb*e6D0ng5Ex1;`8es4Gzt7Y z>76OVT7zm{N|j+zjj5PWdAMbqu8xq^vVZ zfY)SO(Ud;|9Lt39luObiP?~aXz^nTdGFij&2@FYDFOa}*SV<*9pp-q|=#)#+Brq}M zd`1H2kjr*L09vI4GfKT`Vyc1bz= zk-$FGTZKM!fv-6JOiv9aX^Od1 z%DN7(#T28Mq)2sU%6Sy8?w#x^_Q)?+W6Jszaq$OPZOu}ygUF&a<&qQ$bfp}Alcpw4 z)|`9-?I|mbxHykUS$hhB$4Ovb$|Y$M_)f~%lLYQT*xEmzz}_i~-WcMqv)c9*0#S;y zAmx%Y2^^SmHj=lH+JzaDdSRM!S7V8 zgHkS;lf~hw_;6^`{elFJ2z2kxW|R27Ajl%guJ{M3v0)YmryNd(;`F3p9qP*yKa|zD zE;X3U$>K+;_~B&H$5Q+_#Nt9Wj1xjEPG#%=Nj{6CQx3l$j9*W)JyuvWviv8e29r4r zU`@)}h}U8krI^gf_wirvkn zDVNO2;x{ShCbD=2+O)0-vFK+7T^C~U9ahlBd={6dtUr=PIji?dVL>-$*7Yfu%()`C zJ>`r>Ubm4A_>NStPMJ-_of?64%6ua3(g<24{={VwG%I!>fP+>>(2 zoTYdq<$Rwk=CKryX`wO7a&N+VLL&+dcPN$dq(&e&s`tT^bpcuYfOYYZl;Qw>; z*EIr@q?>6&Z)gOX$IC3)n;PNE{ani02c+Z2Qi2ymZksxME9J68l>38}a|q@BEsg&p zO~4<6-c4Ej@;1Idx&1{5j39weQZ7le`o2s#wNSTTeP8R!!7@`--!~eetM6Nlz>;qP zNf~LW@ofyZjZMxd*!jTO&#hmwtLIMmWe3U2-r>?5oHRe2=pvy664br zzZQ?H#1qs0+~8xH(9UU>yht&bcAg+belc#Pg+Kvn0|YA4)@LN}E^E9>2t2~VRHt2% zCV^>bXCm^tyRkh?4+yxsa~e~hmSu%6(ynQ%1&QN}No1-}ypAF@rd{$P#n!abM~VxW zXtq$q1fC+zOk2m3z^h1V?I8r-qRKkbE=iNX{Iqj13Dj~3*jot5bfr6O{hkCqXIq>r z1b$Bf`=woyCV{@R^EnB8Ndk+709QsQQlzE%W$H~^V^D%P_m!-LLUAQ6?ZC84UYxJ5 zftr!XJ(2y&!D-n!!e#5{GS^`m0SjEpcKkh!h#T%G_RHVb2nf-`mheN3fWdJUXC18( z=&Y_F(c?4%omC2ASU=VXm?S+pTPJ7)O!6fXJy9bdG**$TQ2#91c@%ne+FwNuCbN^$ zF3U_^{UYsnun+er>gtR@SFEkm(iRUc#Ftaqr;BQMgvdG@)hz@rM0JzE{UmU4K)~%I z;!=&ENTziz>Yo&O?!Y=vD0*le*00kpc~PWm)6R{gNVmV%Mj-&3cCTkIbG@brMT6p1 zY3oH&ypnNO3&krqaNG!k5Q?{@l>^;DjZNK#wMi3*!PRN|Y;1^WgYcWpEoo~C#EV}* z8E+MeXS3Azrd{%)j1Q-seGu=<_~<|xAJZ&+86QYn>qwEOOswAv#g{k=K9P3Gixi(r zJ6Gb>m+=KnK+E{2d>NlgTThT8&(~Ye2*p3K#lDhu$%~`LJ89<@7@vDQh9T=c-CbeS zIE#q)H3Eagg+zRy5f~({B;rGjz#u`F-_}POfkA>No2-vD0)xc;M0}zV7$hDi;!};l zAn`mAf7J*K5*M=KKhp?|2|T`JeXbE06L^lv`a&bn-spbW`cfm%3efewk+%MXa>nnV zz5F@tPfuJZ!TLJwQcYBbm2udgxUW%&SSFYOeL{qz5m3gLM7SD(vX>GO*9a730ujX; z0R|Al%vg&+KmHzDW+dYaaTi<5D8$H2{FIy!qci0X0j;)+-zCLuGy-2Jf?`?5 zxq%daO+y*(bBnv2b#9v(OkSioDHEqJ8NXQDYXYcaMRBr5U}m7oxr0Xd6T5L4hfadx zr-GO@L0CM;z)qRLWKKD}j5P&`iYa+9nUQZY<9rIF&o`}Aq4{PsLi4TG2QzKB+ zY0T245olLUM9k3$*j6hM^E3kOs*8xdGy?64KXtJ7(FnAwULy9>2$s7HDX zv{q^a>hTsL4$=tJ<8qF_{ThLKJe+pFRwGc4M-g$TMqso&jfn4Q1O`Vg0Ief6g42qq z)ts?jK^4XM^9XCE)Z<$;nsphMHOw*m#~G&%=UiMm3AIkh1Y`K=M4YG*ko$ZhPSFU6 zc?l7xY6Qe=07>g-nbFq(7QlEo+#Z{;4gmf5?wkSqDB};e$5GnTGcLtrFMoE%xsXD9 z!jAi#j6Vb9*fyEdgbjk=V*CTzC9L3^H3Bo2&xp81BQSH}$ztob8iAQhA2oEVMxfyP&}x3C5q`n1 z&RBO+?#DQSUMq6fQ_;6&T$YG(-;;6XpzCy35PzR00J)E$CETwOkeklCtOqm#ayLT+!Qa*h2=N2j@;e%V zrUIU?WUPLWiz~nFuL)23S+m~DxRi!GKgl?S<=}ZMh5oB10G_Qhw7+Qtc)re@pJ@bm zj-*|Et`R8sH$?nhBT!)<(a^ro2vpcIYV%8tK!q(}9eS_e!?j_M8jey)!*c-()!k62qwqB#$Y1)24wcj&Lpmh{iyDSmqE~|DL#zF3S>U+2* z0DU`D%?OQv+>>c&BQ*kYe@;@PGy-yeNgAUy!Z);`)z%Wwk56L}JP~3oD`rf!OYtbg z#A@e83X!H=ZKnx92>v$C+Fm0d1iuloCTj$Q_z~-22aWIzt-RWLkvyBpbG-0;lhW=~ z?NS=@OjJ87$Ajl$1g(@N0G??kOlt&q-bc&JXasoj7XntbMxfv?vngja0u^>JiPmTY zDr^_l!LAyC3gge0t=%*N$zfDqRp6k4+)h@4YpbnRh!j7Ca@UF6n;2-Tc3C3I z-CgY*Pq}AfOTe0|2|(@^#9Q+;0&-tn0K{Gz0Ska?I;ySTkOke*TAjk8ob|9zwM*t? zv9Q{Ckt~j7uiK{yfW@1bp<0VI!WX)y8opvck;l@lUZFUdZF5PrOJ1b7vf3GgL@swv ztb>GrY^5AnZPk-Nk`}mJ2pmpZ>92N4ngkB7cFrdO{+QT0LQ4RVK4S0neT_h=A0pz1 z8iCq6l5PALjX-T3#D4YtlfXIE&O9V?Q*3?bX#x;w7b4CVL;>ujpJXo3 zDPS+Zra~^%2w&(ks;wi)^J!}JEaAzYOIjCKyOf4Juc~%_NuGaZC10&sAP0oLtlIh= z2^>jVxm>$YnD3n~*b-bsqLYXoW!6mP6{25$$7$CAj+ zKDW3@+3%PvOaG=YAxP)5)>*w6LKIQ|qPb z!K6)!Z&b(sN{WiWpEUv4m{P?%`GUVv?Tp$U6w_=puL;HH8F;sPFnLk%C#tOqBr2w$ z#iUI(pH@5P06D0$1!t-L=I2zW4<2B%`b;BW?5o&jKGz5cGM0w)g&<%^pn-u|ComDl zrp#A5?91?BwRIN-y{Hg*KNc(KM4a_?wM*$JQ#9)&CTp1rv%$EmWQu8omdVx#Ez=-D zXqjA{Kx8V?VP7UAYs~|@xXlrvAnT90`%roKwv^IRreRs9ABkKZ*|bJz0?+^yJ2Y$k zk_5J86?#H|4q~lQS(l_qU|iPONCIcm5GQ0uZ2+2zCV??o>p2p*ll{rq>@dc~e?kJ2 zvMx!Jz|L9cuOx6C>tRa11e3GYs2z}}oV~@4BEd-%r!wo3GzsjQjUSIh?gzwA%}V1! zzqTtI*X|ktwI0Mm)@lSA%O+atbd5k&H{+@!t4<@J*N#T)GV3t-p;Vcy^BW5FGzHH3 z0>}SC(hb?c6qiEnk&VAdp*~@0TQva)br*BBX#~s#6q~b-xg#jixI+~Gptb4sud^)Cc|oOLotmB>*ae)JbxE2!I6dneLIO#u{})049I5qFvewxoa4Lu9(}ci1Y*A-tU6Lk&i?YrG zB!H4(OIb?*`)VVn%XFE1isxmm_epVkYWxDB_&AkvdDbN_QoJ_n?7TB5@`uFMMokgs zQ%)AwYXofi5~jFOw>wxNguW_k?TOs+681({3yTwIPd8^>GAD~oS!X#}M5wkqHATPS z-kP;eC4nO-<84CVXa|A2vo1-Kz{6SRb`m&^E&tJgfZM^sJf;!8iQk{KUMIzI~p1bmU6&RUZY7w459*0Vz35fXSQ>yk7HyqR^5C4nMJ z@U|uZE&ZA`_KrrNL*0`G@vcT-`e1NI^PWba?pCt6f6)kVg<@aLT9;9X<4Epx5dy5S zJDqhY9)ry-lQCQ>rltNro1iW1nj5WnH14kpEni!>WH3C8$Kn)jZ z1cdmAjN%&M3sF#GZKM$IQsQWhKe)7@s;t2^F2$n|!)lz5Da2=_I6@PECeWC$e$xmD z@dDfQD2;$YLD?lW)^N;N;*)3%rNV;0B)7Jyamk!4Ce%3Vk;wf%DNfP^*ie{oJBu#J#)y4wuT;oz+N|mf} zwylIzyr0BMYXXp}n{6ed5s>O{L{w`8q?$}2vKj%YwquW7qY;qmEn4cX8sSS-QDZfL zVVuW5ttyeKmVMUL8kh1?s)icphm>jrtEov7fK&&toXr{mskY(VaE3% z36!!vzas<&4MCu<#wBSISXtwoK>}yc6b}*tcsB;)=Yj{;ShtgcidR_o z65b6!6_@;mp-U6qJfs-nU5pglcsy2L?wy3^#FCF#1urE^HX!vRj|b7WEBTVRcYNIT z9?zCf_IUhzM~`Q?cPfEjQyex(dXFQ|&K^%;S9&~3UFGpSbfRQ1<9AJZq?s%k$#a=FVo)W=RBr4Jj+XOM z6PTtk0 zo7hXMmBgjdQf`0@imD-xB>hyTDE|ZNBL=wik2;B@aU{p z1Lns>OSyK<9qjFKAWqaVaij1^ z#t<>=Q?{8yY9buP@bkmB(fJSG8!abhBGxF}q4;UQ5!az_HAZydX^xnHzM^2n<%3}2 zMx+>BU12tIITFRLL7I>8qS!}p7!vOzp8+j%ibp*5w(yDl7LSoNxnzY7-bWpVZqlq8 zPQ0IN^k+zI9)J-CJvjc&vtLBqHtR_4fDDB)JI1sz*HUW};$cJTv+afWp(Q_&5qOy2 zwN62{v3xJT7BOf72HFumA?GJ z{G+9Oi8f$1DOvYN*gTt=CO!vUnoViSx)j)j`1d8AsU$uF;nVRyE+;VpK8F^o4g{3I zw*Yq&Bb2=4AK^pE+hQ$2G9}ETz&(tAV-i_6;svIG$9}%7f5!W3L>SxMj*2UIB04%k zw%b4JhZ36@H+ed%c4KrbLy;YtF(E0qAzH)`NDVb76?<-^cy#fc;X}>W2Y9lRi>~(M7}aGRMQI&|Ah8&%sD!1ssMb&ZwKA;2gr2gfo+;$LxG5 zRWHa8N&O0gQ4~7)8YBDQ4|R zt;y|24mC>(r;qqW{YVnp#tP+U;xT!-hu>I_I@xxNS%qoOP4(`a;q%?SaI}{z^lOXAMD@Ze83u$23d2;yFCgoCUwlK9R(1x$~?MId?IkuOqqOZx} z6fIskl(d7CNm8IsQiiMyzQCwFmxizU17lBRmdZ4VR4pPv^8RIvqWCW`s?KF9eoWPr z>(yJ3Uq$heRS_KoY}rxc6SL!7zU_~H(_o8NA1xGHB84K{AOB{+AF}}<_#Z+>6ar0d zfKaAtu`~U|Z=%Y9hssar^CP4(^rsOoq@qREcn#5@m0EO|aDNGe=^O;PBZj&{ z)%+5z$ixT9@NaI_C;NYeC#==I6}_vMS2VPBwRH8QeOS@3a&=!t%Zi1|)-LJ`Go6B4 zQ+k(G^e^c}ym*JG=u5zL`r1WHS5~Z9xpEntVlQ3MU$J=M!XDDCs_aSjBq|eCJyn%N z?gHd4D^{-P+oi8}!O~r-DyJlOVe}M4=S5X4_1RY}?_IcL>5Bh$G5Qbd4{Kual8U<3 zi{Qj!C3Uq+P8Wx+S>4+YmG~NgGxqPoLt}qM*Q(yt2R5%=(bJ8xEbdsgw!f#dF4LB- zfcg*UU&X>!^sZW3fvU$}|LTPmxE7~k;qv~a{S}RU2QOXNSJBxt8?GR`wp1l!Y{2C2|icdddO~8zv5|Le{6M?3 zw4%_A0$CV2`4AKM(UBixOCnNQIMv5~elWg;DKss656dZ>V2#G>&Qp+lwvU|(>~_{f zV9m(#a%*D5E4TKZVofZ!>dLJVO!!?z^skCp;S>-xBgY>?hP&lO6vWV!13}*m3HqQf zD6{-x3v;4hBci|Ma}m+c0GpiXzL0GYQOPxNiZ!AfLL6!hhwM92&^9H{ zvtdCmIm9e*AlKab?s*L}E8Dx3w=0C;1P1;c<~Gc%YMITK`tJJH#%5zKU7j@24@DKc z4#G=&*X+IF6{n%I%IN5XXDg$TE_+&t z{@+w-x|NGtpA1sd`{BH9O5EPqIhO@OfvcpzZB1?S>RP%DP-F?a;hv!$GAd#apH3BL zlR|fg?-h=I;JUgS+Gls>e668$+U;60X~5Y-!>q=Zx!~8{&|RnBwYCf>uL<0$SO#!w zgj0sO69Rn7LS z$raLn0g2Up{b3zY)_MK}1WS6b}qY}`xL zo>mCWq7e>@U^vhdg%x6AB?&4ir~uI-OcZb0GK^MLN*bQnHykpz%_apD({~kywDs_; zB0@Cn2{kr%)xn6BOAywU|I+M7Bz=(bLD~lyA5{Awn^O&}r@dqEy8nuSqp@$n+QrJY zd`qU3GrL4wyg*#vETE1px^mEd9#nBVjfQz$X!kG4rzSHq=5x zC!KzGv?f|uhq^7K6Gs2i#Vh(2m1F#0ty+4MdNwOZPc$PERecHTeU5Lr9i7+`#{=Dp zY6=Mkl6<73XJKu2)$fI>*0oPN0ein481ORF)zpxvq$MlM$vJUUf@t{yzlnj{#K3D} zCRdK?+*?)^KLhLYn-zOLNWnmpw6QkD5XM!d%36h{i{{iw4R*~#lVUfRMHKp=rWtIg z-JQ531%_AEI+s11(ja2l;+TxKiJ!7)nF9}y38SvDYED~s6I|Q+{U3FoQwVGp<8gn_ znw5Gu_FaCGaW_nxy^oSG0SVciX*nSh(xBtfaswfy#hdCch(R%`R4Y`?7HKgQG|g5j zS8ph;;1apFWbO@KU?nz_d#ld9Wpi&eNr3guijg%Bpn9n@uodbRqHL0MobieKcE3JX$HbJ|3 zFkq#DRww2YG<*#n67?Sr}P3U*WA`d3>U0ee>UNRW}~&E&F{C>fJPo1 z303z5x6fb?r+9iGf-To$uEIe?J&}8^>Vs%Js&IJe!gRtPhx``E(E%-@wV@HVrdl`| zpmU@JbOZYB!3Qv@t`7K3p3&3M+1}mM(B0GC*3;V2(8I=z-nnuvhWt4g2>odU*rB9a z1imWsQ!Z$89T#UEb#uCDebCuJ`f%~ASSMhw4YOE&UsCm^rV&1qdCkxqMgX*SR2e!P zHB&%as+KOTsS`cC>dlgBZh>yV53Q z>gfPyUNA1*L#fiG{6ePC2K2m37F&AI;26!hGJDy*+F?4R4Kk`Tz-u#xXl1UPT|y2- z`IcpL&Tmwm0V=Zr>Q^J;3_at7H(I#=RJ!m%!hn0~#+I&d0+46NqLw9`KBDEI41UW7 zE0w**n2UCvP^*N-W)e^>u~M2m8vrU^I%r0v{UT!qqbJLH-69aJSIvnP`9yWTTXs$` zz?#}py-P=HS7!s6D6SatS1w!Bvm92}vkX4vm(i~*+eo8|&-kn}97ULCF_gS;wMyQv zCK4zxU5%r^V!4~7Ym^bm2MOJ9Wp1jPdVM>l(8gAGh`4RAmBo3eQK*__=Y;Bpn(69q z&g^E2&i-JAvejlxx!d8*+g~7|1uM7n&}tR>1*L+78b~2NJQMm_srF;4{V5}qrzX{k zn{NP^RVzcN638BijYKBZRWhrF=Xf74^Xe*@SXX7K67a`5!tYpA7n*=FyZ2__PoX;q z=3$|v1_~u=5?!9(OL8P*8KlWqq0RdP-Kd4)6rF30tbwcf+Au}Z)WCo=y zdz)D>6jmrlo?J@wufXZCMU@BBR3D~kv zzI`pTbnHunE=xR%I8H{S1+b%G3)qSec&>M_5>%i{^?$SdWi|{2gcLsQgNzSgs5CG1 zJbw3qR5`EkYJ>x#5q+y_I;ywRQz7_%_e+z|CC4Bnm|*pS7Lv;ltY6^uJ%nT0C&0dWUK8djl;7{rCB|PR%-C$)MXjkZT9vq`XK`o%mN_Bj&8@943_Zxp@Ku$; zfP&oq4pP7vIDZ}JPagasMNQ@u3-zYPW@ORwqv7OUg9#@Tl*0xp!YG}?1}aJfDndt} zOAx3CV|Sz2HTQ<?IE7(c^)6}`k|Va- zIa1wb;D6m8oVaJEr;upHNq>;?M`UFzs?=C2`VgZE8ea;XJ?DY`0O1c~(8d<`K*XIT z=M|N*`=~Y+Ld3a@)apqG>PZKS-arrOKs)IWHqcHw&`vtgPCC#|x+bI%^qIaj8M1K+ zQS>f>zf4AVD$5tueAONob%3E+O%7Snl}yBi6mnCov})+JVFnj>!0AaAUNIlRzAqO` z{)?=2Dly>dC6!i1CQwBtu#`+-DVabQ84l}RXe|Cj41+JIop}O(S9f?!X*hNqc4k^316xG`_YgepVy>bn{8ItKGXv>s4 zSa|x=<50WETObDeK*-D4r6LC}?Q7}!7;{Xngs^9-h9m4u$ykkvnyx{NusI*>IUKtt zG@W3-8&fmXNW$;2XL4~9R0s4R1_gUksr)Yj{F*_T{Uti*2Q)IJaH3k(vNdPPAcJ?b z^k4@aD99l-q_=FTci(FDq=oa&md0*^oRCP=SU&^I{bi2qm&1y@tf4t2tjvixn++9p$IF4Tf*A?5x6dY^z-h=2moQN@c`|y3JVdB^l4mR)7Hl?ku zW%mDR?@ZvUD$f3Y&b_%e%S}Q^0tAp4R%3w>R#8z236LO>l!V2~KyN`kVRv`~l$-f1p3eAMEermxhM<7523~QY2k4 zXm8BN%n=WgF2h52yTI#kyub@M_6JDSj~acxF1L>T1(J^QFVkMqp)X6og}v;w_-t>e z;;HE)KIpp7-^{)VNf$OVCj@15?F_g*pT8OXJpwMwuOk93jM)JyAoG|sW8r+xb0o72 z6k>m^0O`0refi(}1Du_|Ips<6lWuA~#<@oS9hXb1h1Uy#=)q?=kSs6O%%{;FNUn=<&@f`75@h#e2nP#FxbP#C|9s)E_3A`9mQul-w$wC|)97CvvoDrZ@9>f-gw^lNigi@%%D_ zdX-|8Xy)5QxS3ZIJW=5niPwn_ia!?3{Fl&wS8^dvL)zb0JV0y|n?;UgO}(?k%f)Yt z95{;czZU;0nt3V_z7H;6j2|l=D$Wy+5jTkEi`R(viI0gdiyw(Gc07dr;o@Q9TydFr zn#hr~seirrkoctds>o{s_4OK?}<6MeK8+1&n3u_e<>d>E)mxBx$S*Y*{tNLnF^qdJ!wbZ6kzZ9X ze2#dOxLQ0}{EEm~aHxNW_>lO#_&bsJc@JH1lD?Z~9Y%L)otyoFG<mgY?tx z`(iFC{gj7@72+Imk;qZPsdt*VO}t6ukcfns6N#aa#p}0caAf6>&F5V*kyZDUwhWMeFj}MKQ@4jNCI9EJUJXYK!UL@Ww zeqVe>d{g{T?8h&ekk2Ub0I^m)Qv8B=qIj-&qj@h@TyKE`5xgT*o8A>xtZa`6=LJn?GrPH~6$GjXT*j@Y-%=2t3C z5oe2w#Z}@7;yL0r@iy^M@fYGB#g9dN-C(wFs5n79LOe=bCvFzEiZ_Tm#Gi<-iMzz? zVKyJm5y<^HTAU`2iDHeoKwK^!FJ2^GE#50WD*j6Rz4(EcS84OxU&K2M zb6rJOM#H$+A)YHragtao zt`xV37mGKGPl@k}856C&QW0I8%=S+go5VHZN#e!gb>dUv3u4YBYo|mUB_1T!ic7@f z#Iwbl#rwsl#aG3*#jMFTpZ;Q{c&NBc+$dfteoNdT;_a&0?xV#n@lx?_@j3BbG4}wQ zZm{?{akjWnTrF-AFA(n*9~WN|$4#|%4;AahOU3Qtt>XRS!{TG&Q{uDYE-`W-?4$0v zFWDbsSCDz0hi(%_o=Rq+T~_h}v6(EycnxAZ3B69T*z-;i&s6+5;>9HNt`Kim__xIS z6uv`zTH(JCpC_@NJIRRWy(Rf0#fJ_;IMyqZgkGWK{^GtQ(v1+ODtwwaOW}u$afP>v z?F#QCxt$8%B%Vbg-%G^n#czoj9^$e6_!$<6FlA&^BMfo-Gek1OL&XNMNnAx@d)mb= zaf7%?{E~Q?c%^u~c$4^D@qY0q;?Km_#NUg55#JS~BsR)y7uKtUGB=ilY_=aX+Yja{ z-07hx8vQa6)ixtnlF*+dqWGHdY2txl8~-v1<7R&jQ2t0~(nB`snR&&!jqP16OTn&A z%azX8)wZF_tKh`)9w(o-Q^GT_qR00q>M&qtneSc8y=Ae}*>`_Ao1Dr%&@1r&_nGVQ zyoX)wV_~_VXdn7IGqAq zWwR~2gW#tQ7Z#U=Sc3Mx3b_f3bI#s;1Y~2Gu88T)NqgJ}&fZ4&Y1eJX>yiQEoV^Pm zF<-ZzdeggEdL}Xc-o)|{FCKDk|J?vNxPA@I*k+s;+}<24ZvDOuze@wJcjv(vNyn{3 zAnuWXpL*rEP;uZE=bZOp1O)Rv?Rbp!f-vTb+f5?hXW@5g;Pu8HX5SgoPv_!zJqp@u z#s!bp5Zdd5#cjv$;CE@@^%lThEj@BB?p4S^dmCV{8DX^77mKs^0sJlvyxx_tx1N!5 zE^Zg(puJzhUID^ruLz5?mxTmO!}3a3SOa;W_4A)`T#C~4ivA64dQ^~edS%jc;myzs zZm(O_eV`Xyzt^#TWk|&JLvcu~-&p9OjCLT%xEo>bASZx`HjWGw4{s;*oV&d@8-GCMl&O^yrcRt#RyMw} za(v)_%9KfEWs@gOskG|NIj7E?JIj7yZ!`DtcG}rxNE25W#o1nq%DpmgUypq|cFTSE z@yEM%b=SNO8Q5cxVY15o8^D1C=`aw?nb?UTKZ`@UV($5CD1|Z)A~GV+0bvf9=g%8B zm+Bdr<~4R!N1xE!!9>Pk5FAC~B!;r1Pkk=S;Nid|DA(tH)u+znm zD}o_g7;lpkSlhq zm1xTFASEzej0I~7=T1K(cpTO;?5)LrD1E$#aVyuhx8d9RwhiO{j}NfW>vs)3j3j_P znH)&~d)#!KS=*lY`e7XgBw%U(*ZMebMci%Y(vEfb9BOqXdjF*bjqe^b;qUheax(i4 zyGpIWRdQj$b#h@70zETRIyWW+^9^q@gC6WFC}>_m6F%)LnY6Of{Ubcv9XYWw>^vHe zC;Ch#S8H9%y3|jH(pG!z@^zIdpGPM@H=xaAujiymBpHvR+Zs5M%htE7#_>*e+B8;Z zpj)!lfuN-=YmPy(G-Juo)qAl|23z()6>uFQn*a zrRis<>1TT%*soq{ASyY5FnmT18v^SW+3jFrNHV?dM|X zJnO7JTLzMj{WMec^E^I#&{=&xMI>F=%TLqK_xNlfVGybl#^^=;+RrC>kORQ5i( zY>zHP$?Mo2Ug*;k?)FVFnb2KblOg7+og$`Rk#&&{UTxj2ZTD}1$sBkav3+c(sIBZk z^|1wcyh9+5OlYd-l}TnB3B&P9#c;A{+R6}KC3&8>P{bpf(LYA)5KkAkh+D}r&%0dm zc5(>Dnw9(=aso!zl>9h39M6N2pC@s-d|C3JNL(IR3+H3AqpMBZKxI{9~ zgV6pMds*@UHA4QJxJU(O4UOS1)W2aDjnS zVlNTBnOfc5lsiMxEt&JAhd_I_^b*m1qmyS&dJ-4YeO+Bl_m$kzZL;pKc|Pwi@A@a>n%&u<2A2ZBsUO~M_()8x`qW4moUPCW>e@oMA>P4>*8xh=&#l7h5m!`L*7rp6edd!onHiT^ich2L-mC9yu5He45@W=&@Kb$8Cn@T@s^h9|~qhrbyP7uB3TBl^pNS+VA<`?6|7 zv$C51{MyHV{pjP|;q%`7ctW_jU{=0V ziqK#d-cERaZQlt9rku^Ho7IXh5p%Om!P#?YWv&T%8=-GviG2=# z%+|{-K`fU@AB<4@-yNMAvr3y0tD~s{FV_{N485G$!;r^W$>!BH`E^By4V*R*8xmoD8DTitV`pvh@z6CMPeQpB9uuy~cN*BR?v9VR7=D<*@EWr%3IaKoSFk?SC z|9~Qr8OMXkO!vWp{md|~?fyxTL3Gr>0f)1v34PqCpbN@TD2Kh1kU_V0?cQ5+KWp*E zz{=w|q_BBzHWyJdd~Ub#aFVcSqyu;uv z!pOMc)i4wF%jnIW7U>hMh!hNq^ce%0DkWxc*`8W8QyNcGgx2+)7&N&nzOt>QBi^=V znHR66Z|3teMY7kk*o-x$qMK-oPBvyI8p`8wQ&Lk}z)ihDM^%U19R3*?S9*=- z%EnR*H-1c<>(_>^Io|B*>VwM4d04AD+skIQFKt`43?q&@G^cDY~`rCZoppq`b^o8KF zn{~;{H)Xa__fd>R)ZE38HI<>KEqYgTLiyw5K{;j>Mr`S|%Lk&8%c?MngHcH&N z1CHO;kA%z{8IKRYr5_!Lr}c?xGAl&RncNc%9+&_%hM7>mmPfik~Q&DmKDdI=FsjKY@HEqdY=1 z`wQ}T$)?>CGLJd+s>M0t5#j>zNRc&T>YplpNjzIL`wj71C0`?6FWxHNAwD4fKzvMm zQvA92oX9#i^WP{w%y@LY* z&fA3WV7|XWzEcs&e0f)J`7VRsrGeLDN2Vv}k#lj!L3Vydof<+vu|R^ttB}a|4ES9dcs-7@QAUrPi~AzvpuMTM{_s9PdoZ1_cPacX4ZPlWV9(qyD8RY6 zufiX+R~xX$>z3OuHwV(d>pcp4IoM|BoV^D$3b+*VTbIlU+Yl7x)O+C@2kBYD}&*Y>+u(C-T5DNg0pQjnZfoLI}cZuYX<7Ii(CiS)%yasglz0ZD&}&Zi!7phi&?(B8ORM5x=XY zvn#%Kc^ngSnex#VU%t9!-O9cA$X#_Ht}*|lW8CqclXUi~?PNR0os)QdvKM?8(*3y@ zmGgjO->0DKJ_cRB`9^>`%(*ZA`3&fsS+|rMnC({c2?wpm;y``(f}N zO7i|on&&OtZ_6a_Csv4)Mf1E1{VK`k1_gPcjUYxxmZ#V3{K-F{w4JfQrYIs{@9=erGeM`Pb@4$ z&bhesXNo37upa50(@TG*=s?+W+rjm5`KCWptcC%8mEfH7vOR$QN=5tzJF?X6OvN#N zoBU4iBV?3bhov6tUctI^ZDjZA&YPjf72)-P6+mtW{oJNt-FY*1ZVkemW1e*Bb>|J( zFL&E0^Y8S`tzmtKd&T>yb?3=bCr{Yjcf8lJkta}h9?X7*_jkBk0)Y1Hs`F5EvR=!uuGW&rP#-C^7~y z$^IXClrl0uPnATUk5)*@XL8;?!++slNfG_F&qoxQ{DFb9@#l~2%gRtD?*VnvM3i z<+JMTA7VmS?en*lBT*m9#)I0PHwhtL!BG5h$=E-yAPXT}{Hd5Y^ncv*qo21QYL=Py zqq!_ML3y^DCOoD4#uh(jdT_Ye%X7Q8CFHS7hwIJ}n8F+P!qh${DLqX3B>RLE^w1|{ z1h(AX$!%eQn7I3JzXhGs2!?keF^>JmIqE z>O#BMQv;1PU2W}lmg7MGj3?PYV*ol$3=R3{{hsW&aR|bT5nd3948sUQp$xy0fBhmc zqE943;B|E}$QVerub4;tm1{e@%2J;C8_jyutwFbnl<@g&oJ_5@WzDkHZJl1*hSqpT z7yAM1b`y?m_Tki?HJaqv8TB0zE|jKX~i?vUh7`Li(;^EMeriY3ukfQO3FCQh44?` z*8)ux0p~9NHi+K~rpEK(Ea}*ng3oA4m#Mb|2!W~Y^B82O>GP>B={~*h1zv;%9KUx9 zx;>xgAb7-hlN(?F-LDSvg`n%U2L#`<-sI`wVs^(||l zmq=CH(zz^EC-s^ixHFimXY!(n8B-HhY^5k?m~E%Y8P1)7Fzi?!i_lQpo)Q|VHpMc# zze4+JD1=h=K|lu%)3p?TW0(#NV3i~u`AuCL)kD*!h(;XNOxae+W5+SG*;YZCHcHU6 zQ6dmon?4TZiXST;EY1+?#0GJZ$TCQ~ZQ?p{gZO3fLXl;R`a4Lh+^PjZB3$_(S* zp{({9%BBwo+E-Xt4}trN`;&+tD^3;<6wQ9Xg@fgf_ONSAdceqL|0A63S+r~R7dSLz zUjl`dC#XoBf9PJ!)$;{X){qyJ=aq<6))LDoptDRU6ut#gEhd7-Mkp zZnNiYvB_>9|A@{a|ETs_o+~I0Dec5O?#?;?ECdAgrb1?UaL(!RoZ#JLx*{IIdB*a^ zvcV!tJ(eeTeMV6-t_J_pt=IfJd;bqo(B3a$uNh&q$D-xzwZqT#3uB?%!arvOUgk-+ z0Son<+X9`cK!EdhK_Qs$RBQwvSD7y#XkEUW;dg1^^&Z7WzDkdri@O-I^E2vpoP0b# zoO5x!76kL1j_VNf`U=Um+N2ngC+40~k=qb~2-&ffRncWL1D zI48<+?%)LC?twpOZv*VP;|p)X-oGnNB}mtXM0IKQnBUV_NT>G=RCIc3$L9SsxPH5! zHx*&daXaXKjU~8#TLRn5>$}_DH{eHE=>UwYL}5P2382f146L@d8hXtL;5~x;5-tO>+A3kDE$K77p4|Z)SxV+i5llx`#l^%ZjTRB@wYfI;NLkkBn zWJv9hIi+>-*AF@TsKMUo%;&ukUn^L!E8}2)(xtO+nDO3!P%~^Sc*Ezt`*BBcUHH#g zA%9}_=%Kp`y=$*pJ>0Wb9A>=#p8`4EtG}peY=RY=e}+j-}xP2R1V%l-UN0 z8J8iGaDB--24zHk3xy0`M#A$3e#r!7W-)zMtj_C<ROEYQ{o^FCerbwuw@1sBjmg z=GeK+A${eXX=5Hk#FPq0~KPzH*xO|pwmYzOi;E8!zEUNh|q7S%0Jfz+Ze-;Bw z%yTXVT_D)QF^d5v<}DW!@v>iG3=IlSQ$WxqppZV`c6$Bj;P0GoTq67jb@Z z8z~Qk--DgLkHKPgXEH@8N+~l-sf&{F&SR=6^vm(p`p8Ya>MVx0XdS>}x?kwNOC@i-!V2caDp)B^J zr|f zHTd^SUV}H}WpMty%%{VgW^TaQR5b~*_Rl|s2@rt)i8va5Ng)D4CG(LOW7=>UJ%3h? zeNEDL2aNcQrUdonVey-+znuveSbr^6&0lE!*D`#O^}o;X#m1k{w=ypxn?YXR?@?t% z!84HhHqpPz`17xT3ZKuQG7542v3>pu3_h1@aEuSHt-|=*CPQf-^G4?wzk*xuH+Vzp zsdk~!dJvlawiURImR`hF9_!~liy(N7+qVYb{q&2lQ-;YzEBr#nvu$P+7H{9B`0J15 z>r$BO7rg?JC94gKH$ zV$Me>Xo5F#3xXblIO;-pexY#GQ}_EV3Q;H)9USI*m6v1pKpM{t_4enpHJ8{7Kl-^B z;8}f8c{n9?3H}?=BrQ{T1mbL&Fn8cXI{6to$O z<;8Mi%)59%idMg%7Rp>6wu5Q|GW>Ady5yPv^!YHH55S`e0 zAsan(2tFX6@83HkMy@kLBO;%wa7LnRl?z-o+4zGxg} zb+*nJ$Q1ikVDs(1+;3o+u~i=21{Bbg7n4|541JUmgn-eh0n{ZOJsjuMQ@22QoT_kwkA zeM{TfGOneweOz^YV_jo>vgNqywViF_>ejTb#@F7#0XYAUkMjC=cs+>SzkFQ>JIar1 z=~y)mulMj<*V)Rh>f?HR*WSZn*^6bN_mydHU5}xDR|kv3-pe=Mx_kw9gdsK^uPy9b zX!FY2?1%V@)>gcf#`)E4tO4Bfl4A|vENeyajkmT>oM`puA26$GO8w*+wGeS8vQsig z##*}uGO7xc-Qa(2$^(psW+Sy4CgHTD>sPJr8oO!@>jKsczw=&~G=qH<$6-tctm-^g z!dkr3;MPGzZ6NSo{r4e`d(f{q9K$>HXpwn0o_x7}A>On{21W`n;z8eV;WP|~umVFJ zgbyr>6oij}FB&eaz_12TiiXR|!r2w!+=}qvX&Ir&;P81lek43FIxWM*zP;X$97x5A zXgGULqzca)k+NvGbWUWHNq$HK>I13jM_@A>FYLq7%E(|tKQfZUxCz9t$Osc!8W~6; zjS=~dKMd=6ez;G?p)@zhj}*b&&|xw+Ei%+hWPxMv*Qi(=QYi&Zi-jWuKs(JO8X&0!=i@yUUg&R%(?UNa^92x zym@YKYj5q?=(X7qjN1~kk_X1bt*NfAYh2`g(rg^n4OM6kX{c|k!vCzsMKevILYZMf z@wl0b@QJAXE+XDAuMwN-DQ8-*UszS`&7avgbN<4aHD23s9O}*XZ5TfV-3+Q57Sz>v z^$TasuQdPTlSMYZioGhZIqNVKv-yT1p1N`9VUg&r;BuJkHCE4vH*M@_OJq95tDaj| zGv8}$s>2pwPsNvdjk6l(do^a;>#E`93IqpCW+Pd$??<991cPVH!j8ZOGWWzsBJ<-7 z^>vNaHsg4_k#Aw_ckSIfe89-W3EcGRMy^(}qeps?nO7g5+fW^!QPtGsRda>oW|zcU zIy+l7no&LKs_Uxe&Ru{AcF$)}JnkV7JAHvyR}-(}L2Il<;i#&ckE58_5Ywr{?pm8D z*pVY88?)zWtG<2~47im?Km+A9O2|FKNOMpdYq?Kx^v%KF!`>k7l8XGW@<%kX^ab9f zBI7D#%;VVD(`Pshvt}MKv&jywVb@@RiuWQ^A#h+iyS#->^PEjqBC2_TT+o4C*yh#P zf>Di=0;3f0rJFKOD4GI#JZz~@nj($ES<94F{F_m^s4h|Z#wUCe626HE-z2XdeMC%g zY3S;-C8m+v?aK23_H5&skX}5@3CZ1n^4#NTICoz4;VNFHz_qSjZ%#gU3>#{Xte;mi zv(l4iyemiMn4=`QQf*Ftom6qN8W>0f{jWM3I@fmL&7+%XJ&rE=8QAKU&7cdp{gf;^uveo9_OF=+p-+D@`k8X1swYgrN&3hJH)Rh zbWqI-IQApT3&?2sN|CyMo0e*w<8}vK_ixeo#xd#kMn9nfm_rMTdG2GsoifP}g6x+w z8g!1jeBt684q2N@hu6Kcr*@-gY~(^`PX9B5>a^6>>9TlBt%c0-%bH)l1wWbT8?# zR^_ghJw|E*H0I?hSjKNFLhe$LQora{KSFKE-qKYma2NBGI)b~m^>C|C34*0=_do2r zLM$Ag2R|L#Pd!gk$5v%>Uo!fp)&hj z7yCS2O?jB-T}KYbxTfR?jf*|f^X{OGM%TN@{XFkpvfT5&0+yn06x&ug9uBX69H)iv zok`Qj3B)RzaepL3&l84k7kOS#-XZ={ z+$rMG%ET9mLq#*557HeeneS0)htuDXr;BFXZOCQ-1n@S6bL<1^Jt}f|PRe|XOTH!g zxH(YfxSHf>@j!95xIkkjRX%Wsx{c94}56 z=ZQy)?czz|IpU!i*52V_i`XGPDE?IZgZMYG5Vs7j*KqMLajv*bTrXZAeog$o_>{O) zt*>af7&p+#kn7@@3-n;+^7s;-lhk#5cq+E}2}v zKH>lp>pn{I6!8!e%UsEeNz^5lh%F=*eizB`lf+F5zfAI#;&z4KD((<}F1{fCSQNEYH_=Gi})?^9`OP32jb)6PsC@%UyCSq zWa<6mgvF(S z*ZVaRZNz=cITyz|iSskA3FpgoPAL#~HvGYSpBR?hUOrj4e6I|of!Eswd*$@Vxx6le z9JIH3xZMVB2cL7Cy*uD{Y2fwB5J?^9T->b)2-@2Wdu0ftE}v|iy&dqoH1K*H7i=C6 zn4F8dA9B#%b+E_l2<@@H=IlKQKhsoVp*s`T=c%rcL1rA6=R~LX01VARm~&3=RRqxQ zTrMhuHBJDTFWt*ng6nrzV0&4QbnEvP{NX@f$_Ciub=WzV7a1rX-nr1b8UcW*N7Ej+ fpLxPw!i_<_nSIxtb6)PFpx!fBzp#r$ob&z{JI#u5 literal 0 HcmV?d00001 diff --git a/tmp/memory_regions.ld b/variants/THINGPLUS_RA6M5/memory_regions.ld similarity index 96% rename from tmp/memory_regions.ld rename to variants/THINGPLUS_RA6M5/memory_regions.ld index 9e19f9d2..ecfabe7c 100644 --- a/tmp/memory_regions.ld +++ b/variants/THINGPLUS_RA6M5/memory_regions.ld @@ -2,7 +2,7 @@ RAM_START = 0x20000000; RAM_LENGTH = 0x80000; FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; +FLASH_LENGTH = 0x180000; DATA_FLASH_START = 0x08000000; DATA_FLASH_LENGTH = 0x2000; OPTION_SETTING_START = 0x0100A100; diff --git a/tmp/pinmux.inc b/variants/THINGPLUS_RA6M5/pinmux.inc similarity index 100% rename from tmp/pinmux.inc rename to variants/THINGPLUS_RA6M5/pinmux.inc diff --git a/tmp/pins_arduino.h b/variants/THINGPLUS_RA6M5/pins_arduino.h similarity index 100% rename from tmp/pins_arduino.h rename to variants/THINGPLUS_RA6M5/pins_arduino.h diff --git a/variants/THINGPLUS_RA6M5/tmp_gen_c_files/common_data.c b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/common_data.c new file mode 100644 index 00000000..758c90b0 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/common_data.c @@ -0,0 +1,49 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +elc_instance_ctrl_t g_elc_ctrl; + +extern const elc_cfg_t g_elc_cfg; + +const elc_instance_t g_elc = +{ .p_ctrl = &g_elc_ctrl, .p_api = &g_elc_on_elc, .p_cfg = &g_elc_cfg }; +const cgc_cfg_t g_cgc0_cfg = +{ .p_callback = NULL, }; +cgc_instance_ctrl_t g_cgc0_ctrl; +const cgc_instance_t g_cgc0 = +{ .p_api = &g_cgc_on_cgc, .p_ctrl = &g_cgc0_ctrl, .p_cfg = &g_cgc0_cfg, }; +sce_instance_ctrl_t sce_ctrl; +const sce_cfg_t sce_cfg = +{ .lifecycle = SCE_SSD }; +#if SCE_USER_SHA_384_ENABLED +uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t * message, uint8_t * digest, uint32_t message_length); +#endif +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = NULL, + /** If NULL then do not add & */ +#if defined(NULL) + .p_context = NULL, +#else + .p_context = &NULL, +#endif + .p_extend = NULL, + .ipl = (12), +#if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, +#else + .irq = FSP_INVALID_VECTOR, +#endif + }; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) +{ +} diff --git a/variants/THINGPLUS_RA6M5/tmp_gen_c_files/main.c b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/main.c new file mode 100644 index 00000000..6f1f9608 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/main.c @@ -0,0 +1,7 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) +{ + hal_entry (); + return 0; +} diff --git a/variants/THINGPLUS_RA6M5/tmp_gen_c_files/pin_data.c b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/pin_data.c new file mode 100644 index 00000000..31882072 --- /dev/null +++ b/variants/THINGPLUS_RA6M5/tmp_gen_c_files/pin_data.c @@ -0,0 +1,118 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = + { + { .pin = BSP_IO_PORT_00_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_00_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_01_PIN_03, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_01_PIN_04, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_09, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_11, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_01_PIN_12, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SPI) }, + { .pin = BSP_IO_PORT_02_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE + | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) }, + { .pin = BSP_IO_PORT_02_PIN_05, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_02_PIN_06, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_DEBUG) }, + { .pin = BSP_IO_PORT_03_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_03_PIN_03, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID + | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_04_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID + | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) }, + { .pin = BSP_IO_PORT_04_PIN_02, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_04_PIN_03, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_04_PIN_04, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_04_PIN_05, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_04_PIN_06, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SSI) }, + { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_USB_FS) }, + { .pin = BSP_IO_PORT_04_PIN_08, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_09, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_04_PIN_10, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SDHI_MMC) }, + { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_QSPI) }, + { .pin = BSP_IO_PORT_05_PIN_02, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_05_PIN_03, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_05_PIN_04, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_05_PIN_05, .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) }, + { .pin = BSP_IO_PORT_06_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, + { .pin = BSP_IO_PORT_06_PIN_02, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN + | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) }, }; + +const ioport_cfg_t g_bsp_pin_cfg = +{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], }; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/tmp/tusb_config.h b/variants/THINGPLUS_RA6M5/tusb_config.h similarity index 100% rename from tmp/tusb_config.h rename to variants/THINGPLUS_RA6M5/tusb_config.h diff --git a/tmp/variant.cpp b/variants/THINGPLUS_RA6M5/variant.cpp similarity index 100% rename from tmp/variant.cpp rename to variants/THINGPLUS_RA6M5/variant.cpp From f7df79ed9a102023b8ffacbeb11fc7bfc14829e5 Mon Sep 17 00:00:00 2001 From: SFE-Brudnerd <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Thu, 1 Feb 2024 13:08:58 -0700 Subject: [PATCH 03/13] Fix miscellaneous packaging things. Recompile after verifying e2studio configuration. --- extras/package.sh | 4 ++-- post_install.sh | 9 +++++++++ variants/THINGPLUS_RA6M5/libs/libfsp.a | Bin 20421610 -> 20421610 bytes 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/extras/package.sh b/extras/package.sh index 77880279..5de2e57a 100755 --- a/extras/package.sh +++ b/extras/package.sh @@ -75,7 +75,7 @@ cat package_renesas_${VERSION}_index.json.tmp | sed "s/%%VERSION%%/${VERSION}/" | sed "s/%%FILENAME_UNO%%/${FILENAME}/" | sed "s/%%CHECKSUM_UNO%%/${CHKSUM}/" | -sed "s/%%SIZE_UNO%%/${SIZE}/" > package_renesas_${VERSION}_index.json +sed "s/%%SIZE_UNO%%/${SIZE}/" > package_renesas_${VERSION}_index.json.tmp # SparkFun Thing Plus RA6M5 @@ -103,7 +103,7 @@ mv ../$FILENAME . CHKSUM=`sha256sum $FILENAME | awk '{ print $1 }'` SIZE=`wc -c $FILENAME | awk '{ print $1 }'` -cat extras.package_index.json.tmp | +cat package_renesas_${VERSION}_index.json.tmp | # sed "s/%%BUILD_NUMBER%%/${BUILD_NUMBER}/" | # sed "s/%%BUILD_NUMBER%%/${CURR_TIME_SED}/" | sed "s/%%VERSION%%/${VERSION}/" | diff --git a/post_install.sh b/post_install.sh index 65e7e679..d355c5f1 100755 --- a/post_install.sh +++ b/post_install.sh @@ -6,6 +6,14 @@ arduino_renesas_core_rules () { echo "" cat < /etc/udev/rules.d/60-arduino-renesas.rules +sparkfun_renesas_core_rules > /etc/udev/rules.d/60-sparkfun-renesas.rules # reload udev rules echo "Reload rules..." diff --git a/variants/THINGPLUS_RA6M5/libs/libfsp.a b/variants/THINGPLUS_RA6M5/libs/libfsp.a index 4260a1e90eaa30ce132ae61891b901b93bec0437..a7e21f6df5f6b8bfe0d72597f5de8590aaf58f9b 100644 GIT binary patch delta 5014 zcmY*ddt8n8AAfx*$-<#H7orupbwB5Ha_Q$JEo)i1tgK>5X4%lJwMqe_vik3zL)0-JT!emo-|8i zXO*+kt;qU^XzrgvQKF6Zyhi^rRcVc47&{#;)KVZ_8$A+I-=b?T={P&|=ny2qk@|iR zsqY_mUJ%o+HiuA~EzYG13bN!&5{TjGB4@VGwlHC|3ZI%8g3PjT2pZ z4C6!ZjN#C`0q*@Nc1CA{H9ga?CCy|*I~|v99SDEXznrBo7!zS?P)tqNMVdAUmVhw& z4;0u{X@osF!StZPFCK76?goGWUBYBGjq7QqX=fjVA&5UL$TiJ3XdxzY;K&KnWfV}7 z%$lx%?}|(_1pq|n3{LQqVX*PC!KPBMBfn`XZ^O>?SvzqzplI&%lLTsPv1 z$Yk4Yl_o`eP#R%2VKrsYT6)%))zMlSlupkaT=yBJ>?=1CWBK#JAb&oj(5_pt7`kLb z_2qP&9lv@UBE@YPDz5F8l3?`}5vZ>WQzP1hQb!WF-3glo2?9c^pEY@$8+~Hb%erPCuY8Z z#Ca3`(h0&}I)B~An>G&@X!DSt{FG;^7~Y%HX>vH7rU<6q5HQzKitUFh!G5^wN~%-E zkch?1%zTv>ejV-#uftVSyagTH3??%$Gv6(;8}ywf!MEDo;8y$87mFwpYkjAI)_1z2 zFs4~E`*Av${W#--UvG6yFK0m0OLx0D0%#SuP=+1c{{s&0Gjn|mOfJkeJQLcmIzjk$qa;iGy7>DF#ODH2tVUh*$X6@ zfA0l;??0;k$lwAeuJ-ZKZ zQF~w_U0K{1QcWo?nzIOs=6vq5h^|ou^>?L7xu2Kj1_jb?A~ddXQdWj|;j`AkaMn5m zsQ+{ZlNm@^xwx}8$aK9~;)Pp_7ej0DlD9P10-el2*PAcYz38NV9-$E8v2+0~6=9Ob zVA7h`OvbO0m%^*$u*dWzaKpNqFwoU3J4qYE4X4?JLz>O5ixG^jX2iiyRr|~mA(?X(!W;p0sU&f2EW>GL=>FL zCkbz|UIm-1SI_XKxvVUICdJhetD!n#P4;Gru@!nLCXqo}bL7xZyLmEvQSmKYRIGK_ z%ol4aCKUvI;dgRcys5&buI?8F>VDCi{t#H&>S)kbuY3EsVeAkCT8H%|iF8btd`7NQU;sN5MmQMiY^%>D2Esc&WMhMjOg$4k_^n` zqf(|Ka)$@r*ZDo{>x_Fw(>iruSxOLY^p1x{?}VH51(}KqcPBvM?kxp994U^i+XAt5 ziDP(-_>*J16>@C1Rj#7`am$wk@66Z+J2R597Vw}mLv{rTp52;69t^Wvw|oAFvU#h` zw#m?JyMtO)Ix&UBM@)Q#ipUfPz7>>CNo6UeWjk#IqdbL%v1Pz6*fJoMhCzf$cgS$+ zyi`b?r&%fpGyIljc2EOm2h$QyadlH>`;o0uhEMtIhEqO!e6j@Z`Q|cj-UH^%>8*V0 z6WjI~rS^LpHVTxg@@EpQiMl4i2gWgQU|i;!wUmiPOeTn!AL7;t zk|b4R!5O?C@&{+N@P`N*Z87$V%>tj;1KSMo@iy9S9DueP2hC#*;wF!z*wX6|SbAm8 z+980%VF{ys@{<~uRc1q3WlkLb8Y-Q!T9OND$zeZ#p6SAn#*yMvUmYe-9-R8>h{Iqy zfpyVG$nzuUqK}rF^O!RxHGsn8V=9_KXReu~*!b=-Fur>{mG4ibGfivZq7zWK=%@DG zRFW%z1QUlq`{X1m_`(oh*5M9$K6J=WJ>d5WB2H`+;~iU1!H%sz3z0iBeB^eOKZ9Lm zft*I}%!HOylE(8bgjnCA-wf8fBWFnDVR*ppA{cPH*s_;N8FR__d%Vj!lN|ojwEiPM7W#wBtxOfJnEq3%2sz!m#$XQmiXG3%as%LR2nXR5DCV zz$N1gQw?b*d%6^l2)FW*I($9H=u!^0;10>dU<+aX9}(w2}Db$tQt zNEcc$QOk7@wcMylr6#$ZM1qah{R&3wZngvoe(0-ig1+jvz&?`Up5+kkdFu;WYvLRy zsjI#Py6OszAW4h0%kg*EI)(`=CBc<3~bsOAOe+=Kw+mv(ON%1Q7 z4_L+CN$LfX6Wg3>5Y4%pwU;t6NdOeq-xJgP%IR^mX-N$62zp&<8+{tZ4zwq+e4f83uyD!S8n4$1twcJXe<7<@e_KAy!AYSG~f)tU^&q8>~g#W>k39laUo4ry&54R!FuOKA)-xQiz1=sUr9eMpP7{7kq zk1n1HMpyAphHazXfNfNVDW!@%w3o?kuoDh zevA4pEE&h{JDXsoHnIG!(GN$|LKF!&_g`O zmEQ(6n;#59?3wXwSF=8|3OVG^gz16&sND=!&B12JkDJ;URz=gzy1vsF^PX#sn zrI@Yta76kj3bEYHIg$1mxn7a;wkFceiDcZ(8Li>3x=IywbE`A@mG1NO4ykF_p8hwomB0qA(>T48eim70NOJW>dQB-{6vSrCils!$D4*f-mhKl=mm{O}m zk^G5Qsk&tEik_MXTrL2U5BhM;)vjn@gfMS)g3QO!0rwe(^_-|eQ6nh8e`R6sxU0}k jy0WV1w;OhozY19iTG^an6*4!t!+!-~Z?9D$>7@Syjxl{w delta 5015 zcmZ8le_V~%AAcQ6vT!Nxy%DX*uS(sgx;2`cv|7u`kCi2a%(9_b`Q0kfk?2P8G@+9D zFtzDA<&d7kq;{rLWI?(3fS`TYKT&gY!-Jb?$MPsm8K zGImnAGfa`q_c8oGXOCiCjQ3UkugZz7Oly$C$Vq6njsoern4ysR23>tY=h@+h2OtHG zGW3EdL+`kAR06A8YpMXV<3=?mBALO(4auQ*v5`SQoINOs?7YzU%#s}US!-2PbJbP2@wB7`3yOv>7n#sCWIxpGW7yhJwso)WjrjlT)x;DzR zUep9cb??3+b!8ecV|;??e#tHYa7^w5fB+rhVm9^bX{Kp=4}>L15X{Oo&6lJQ6*+L| znCW5(AX1jXw?(FzA^@_p|7XPdOPxAJJwS#MN;H@C6Q)hR&=^XlIdM-Rx2h`lsYN1f9+?KYfqVx95c`Q1M_S^p?#-hIdoVK zG?Y=A?D!R<5Xo-SKzU6kmjY`p%RqB^klKY}tj=+b9H+k=1nDmauU$+*EDJRUS*S&U zNR%Bk$rLGZU8)7tr4HG%Uu2E9Sg*io_Cv{#Lz=z9c9E7k-8l;yhU0<;D=26fVP7vSsIdOhNHVNJf9d_XK9m?V zCN@uR&~W>lK7R0VchExX2Nv3o&-VaZ?tKg`_x$rjaF0WV z0_WR&0{J!pu(r$9gSg+m0O+@Gx>cvEd{Dd_r-OInr}k2egD%eq!DSACQ05S1EmC5` znjkQ&nK4(I6Cwz@JadgCiL5K}W3yTC*lf0&L`1?1)*+v9okWGJl=yA#XYe*Rc)$$7 zFc(b95oE0)iL|k}@F`Z}BELCME5C>n z*I6N2b?3f-x^qiEpwSWSV2r;6#yB#gn;oQV10s(+3RuquV)9qC`W^Z)~EzJkD- zuVp>J4K~YRgUyP`5?ERG7ioi$E1)WJW%kA{*D!Gn(i)=%eo8aL5<(@u;PMSza9QQJ zQB0Sia1|H|zh!0!jM)pwsjkGDUeTcG6|>=Ykw{k+1G=i!Z$6jij%z^YxVAV^n7h)J zuRXaIv?tfKEEGUDOqw|v8zA0dBR4=KBt3(q!FD5r*~Si|JwxDD;Eb49$cXtaFG-?I zKCEQRqqceBJ?-DYp7yxEXk1KiD%^r|DABcf0uujXuhy3%o}%sd1HDrt$nv7hl~=3-Sz7! zBcE^uZa=ac+K=o>qzNY~qOU6OzELdf8U_PK?1j$C55BJC%!yLMjo8_@{nVHx`6dDhsgK=^f8Ca z%&96&jDo`CBWfvv!yv-PvUiCiZ~t$#G6Jg(aq} z#%)YKv@s{{)3ZWN{oc0u1Z>;Mo!VVgrhPrOMUx zRN)l#Zj^0ixW`%-SplPdKUcrDs52dRBCc>cB(?Tr@uKA%&UrU?m)1b zmyV}hSkR%w^Quc>UiF2kk_SQ^m4;q~(onAcJ24qK_c_S9ufsI(BB#&jOW-s5@_LC= zxW&{Sy$rQSugK#CPIo>aN<3)X&oF4*)oqmB9h0(zoak$_Xhpiyogizv2C}B>)u|FE ze_b$I{RxUcw^Q+;}{ClV9{nDL{%6Ov0r`_(uX}3Ri9qH0RZf6hvfQSb*zQ-kT z$+e{1>(ra*T(}w-nLPj_v--R>BBM}+R}<^uYNGxwb;AP_iy_CPVL~z`B5#=nX0Y(z zLww3v=QV(J-lJ~|C`yegn)xRb&3ydem807rvjx07|Jp{g?14$SL1o#qjt$~Q<#%+8 z?{jGJHB@X71(Az1=*s`L4eX*xvihgQs?|2J3&EP4R?y_Us1~^hhhZwh^T+%b=8t*# zke>D)!es=9#k_>Dn154fU_JQ#P5Q{If5G_Gt6sEsda(NPx0cv0`Zd@^x0zxwBt)nZ zPk++})8D)qD(qdxiQlVAoZ#OM3I1!q|RWHObs@}-DS%97SUa8PVSsEeoV~n^c%RZ>JH)Wyc zhBjeDAH*e$FhOm5DXxt_Yl67=vwcySP?U_5mVb?LL6iESfd@pn{5h!Ic)uSaKkp%K z<9#!fqM`gk(zK&3`y+0&3_^>kY$pnD zlno|gW#*`Cm#9+kaB-eF;uhywpnbv7Rf5#ddujgB9I zxajziXv$m(CeK=JMa@XWRn%Ccqe~^2Tu!y=-tQwW-P;Bk2~RD?S-7)u#RqNBO>2Qr z#eYB1?!97zviDxGMXxECZT-*%DY(L)ZBd!9!x$CEKe87;pzDGdZAZXp#B~JNp?j0N zWO4r_+o46}RGjK1WwQSMG8;_l99rSR5eRMgDP&gd86pl1jjAJqC?&WNkur9x)H^PEv>4b>_{ zei+0Vs$I|oQ&9yU#5kd&5LUi$xzc1;l>LFY9R9N_8Yu5!VM>iFiV_|yjOwC;8+vLY z(((?NyeCW;`jLb)*SMj+krd*rkCF8_I^jRWaNc9pD0&Frau~KEtwF)v_Ee+oLStnl d2^)gc$XXQ2<;+zhb7~DkcPMvjl^Q9>{SQ_7dm#V- From ff5cd76df9efb9a22d11623daa1c831772528c54 Mon Sep 17 00:00:00 2001 From: SFE-Brudnerd <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Thu, 8 Feb 2024 09:04:29 -0700 Subject: [PATCH 04/13] WIP SD testing. --- libraries/BlockDevices/BlockDevice.cpp | 2 +- variants/THINGPLUS_RA6M5/pinmux.inc | 26 +++++++++++++++ variants/THINGPLUS_RA6M5/pins_arduino.h | 43 +++++++++++++++---------- variants/THINGPLUS_RA6M5/variant.cpp | 43 +++++++++---------------- 4 files changed, 69 insertions(+), 45 deletions(-) diff --git a/libraries/BlockDevices/BlockDevice.cpp b/libraries/BlockDevices/BlockDevice.cpp index 1698dd52..6323b08b 100644 --- a/libraries/BlockDevices/BlockDevice.cpp +++ b/libraries/BlockDevices/BlockDevice.cpp @@ -17,7 +17,7 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifdef ARDUINO_PORTENTA_C33 +#if defined(ARDUINO_PORTENTA_C33) || defined(ARDUINO_THINGPLUS_RA6M5) #include diff --git a/variants/THINGPLUS_RA6M5/pinmux.inc b/variants/THINGPLUS_RA6M5/pinmux.inc index 4f8fe111..4d67b8b5 100644 --- a/variants/THINGPLUS_RA6M5/pinmux.inc +++ b/variants/THINGPLUS_RA6M5/pinmux.inc @@ -404,3 +404,29 @@ const uint16_t P014[] = { PIN_ANALOG|CHANNEL_12|ADC_0|LAST_ITEM_GUARD }; +// pins not yet handled by the script +const uint16_t P208[] = { LAST_ITEM_GUARD }; + +const uint16_t P209[] = { LAST_ITEM_GUARD }; + +const uint16_t P210[] = { + PIN_PWM_AGT|CHANNEL_5|PWM_CHANNEL_B|LAST_ITEM_GUARD, +}; + +const uint16_t P211[] = { LAST_ITEM_GUARD }; + +const uint16_t P214[] = { LAST_ITEM_GUARD }; + + +const uint16_t P015_b[] = { + PIN_DAC|CHANNEL_1, + PIN_ANALOG|CHANNEL_13|ADC_0, + PIN_INTERRUPT|CHANNEL_13|LAST_ITEM_GUARD +}; +#define P015 P015_b + +const uint16_t P014_b[] = { + PIN_DAC|CHANNEL_0, + PIN_ANALOG|CHANNEL_12|ADC_0|LAST_ITEM_GUARD +}; +#define P014 P014_b diff --git a/variants/THINGPLUS_RA6M5/pins_arduino.h b/variants/THINGPLUS_RA6M5/pins_arduino.h index 712a1b7f..a0355a9a 100644 --- a/variants/THINGPLUS_RA6M5/pins_arduino.h +++ b/variants/THINGPLUS_RA6M5/pins_arduino.h @@ -126,26 +126,27 @@ static const uint8_t PICO = PIN_SPI_MOSI; /****** SDCARD CORE DEFINES *******/ #define SDCARD_HOWMANY 1 - -#define EXT_INTERRUPTS_HOWMANY 14 - #define USE_4BIT_SDCARD 1 +/****** USB CORE DEFINES ******/ #define USB_VID (0x1b4f) #define USB_PID (0x0036) #define USB_NAME "SparkFun Thing Plus RA6M5" +/****** FLASH DEFINES ******/ #define ARDUINO_FLASH_TYPE HP_FLASH #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_TOTAL_SIZE 0x2000 #define FLASH_BLOCK_SIZE 0x40 -#define PIN_QSPI_CLK (40u) -#define PIN_QSPI_SS (41u) -#define PIN_QSPI_D0 (42u) -#define PIN_QSPI_D1 (43u) -#define PIN_QSPI_D2 (44u) -#define PIN_QSPI_D3 (45u) +/****** QSPI CORE DEFINES ******/ + +#define PIN_QSPI_CLK (40) +#define PIN_QSPI_SS (41) +#define PIN_QSPI_D0 (42) +#define PIN_QSPI_D1 (43) +#define PIN_QSPI_D2 (44) +#define PIN_QSPI_D3 (45) #define HAS_QSPI @@ -154,15 +155,23 @@ static const uint8_t PICO = PIN_SPI_MOSI; #define QSPI_ERASE_BLOCK_SIZE (0x1000) #define QSPI_WRITE_BLOCK_SIZE (0x1) +/****** MISC GPIO CORE DEFINES ******/ +#define EXT_INTERRUPTS_HOWMANY 14 + +#define SD_NEN (35) +#define BLE_NRST (36) +#define VREF_EN (37) +#define PWR_STAT (38) + #define HAS_SDHI -#define PIN_SDHI_CLK (22u) -#define PIN_SDHI_CMD (23u) -#define PIN_SDHI_D0 (24u) -#define PIN_SDHI_D1 (25u) -#define PIN_SDHI_D2 (26u) -#define PIN_SDHI_D3 (27u) -#define PIN_SDHI_CD (28u) -#define PIN_SDHI_WP (29u) +#define PIN_SDHI_CLK (22) +#define PIN_SDHI_CMD (23) +#define PIN_SDHI_D0 (24) +#define PIN_SDHI_D1 (25) +#define PIN_SDHI_D2 (26) +#define PIN_SDHI_D3 (27) +#define PIN_SDHI_CD (28) +#define PIN_SDHI_WP (29) #define RTC_CLOCK_SOURCE RTC_CLOCK_SOURCE_SUBCLK diff --git a/variants/THINGPLUS_RA6M5/variant.cpp b/variants/THINGPLUS_RA6M5/variant.cpp index 91163193..2328f205 100644 --- a/variants/THINGPLUS_RA6M5/variant.cpp +++ b/variants/THINGPLUS_RA6M5/variant.cpp @@ -1,33 +1,6 @@ #include "Arduino.h" #include "pinmux.inc" -// pins not yet handled by the script -const uint16_t P208[] = { LAST_ITEM_GUARD }; - -const uint16_t P209[] = { LAST_ITEM_GUARD }; - -const uint16_t P210[] = { - PIN_PWM_AGT|CHANNEL_5|PWM_CHANNEL_B|LAST_ITEM_GUARD, -}; - -const uint16_t P211[] = { LAST_ITEM_GUARD }; - -const uint16_t P214[] = { LAST_ITEM_GUARD }; - - -const uint16_t P015_b[] = { - PIN_DAC|CHANNEL_1, - PIN_ANALOG|CHANNEL_13|ADC_0, - PIN_INTERRUPT|CHANNEL_13|LAST_ITEM_GUARD -}; -#define P015 P015_b - -const uint16_t P014_b[] = { - PIN_DAC|CHANNEL_0, - PIN_ANALOG|CHANNEL_12|ADC_0|LAST_ITEM_GUARD -}; -#define P014 P014_b - extern "C" const PinMuxCfg_t g_pin_cfg[] = { // Thing Plus Form Factor @@ -126,6 +99,22 @@ void initVariant() { // bootloader configures LED_BUILTIN as PWM output, deconfigure it to avoid spurious signals pinMode(LED_BUILTIN, INPUT); + // Set internal gpio pins. + // Disable SD Card Power + pinMode(SD_NEN, OUTPUT_OPENDRAIN); + digitalWrite(SD_NEN, HIGH); + + // Turn on VREF. + pinMode(VREF_EN, OUTPUT_OPENDRAIN); + digitalWrite(VREF_EN, HIGH); + + // Configure Battery Power Mode Status Pin + pinMode(PWR_STAT, INPUT_PULLUP); + + // Take BLE out of reset. + pinMode(BLE_NRST, OUTPUT_OPENDRAIN); + digitalWrite(BLE_NRST, HIGH); + // We're using an extenal reference voltage, so set that here. NOTE: AREF = 3.3V analogReference(AR_EXTERNAL); } From b8e109044a4c178f90c21054d91ccdcedb7a6aa7 Mon Sep 17 00:00:00 2001 From: SFE-Brudnerd <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Tue, 13 Feb 2024 13:03:06 -0700 Subject: [PATCH 05/13] SD Working. --- bootloaders/THINGPLUS_RA6M5/README.md | 2 +- .../SparkFun_ThingPlus_RA6M5/.secure_azone | 1 + .../SparkFun_ThingPlus_RA6M5/.secure_xml | 1 + .../com.renesas.cdt.ddsc.settingseditor.prefs | 2 +- .../.settings/language.settings.xml | 4 ++-- .../configuration.xml | 9 ++++++--- .../SparkFun_ThingPlus_RA6M5/ra_cfg.txt | 4 ++-- extras/package_sfe.sh | 5 +++-- variants/THINGPLUS_RA6M5/libs/libfsp.a | Bin 20421610 -> 20421610 bytes .../tmp_gen_c_files/pin_data.c | 2 ++ variants/THINGPLUS_RA6M5/tusb_config.h | 2 +- variants/THINGPLUS_RA6M5/variant.cpp | 2 +- 12 files changed, 21 insertions(+), 13 deletions(-) diff --git a/bootloaders/THINGPLUS_RA6M5/README.md b/bootloaders/THINGPLUS_RA6M5/README.md index 0664431f..9d1def5f 100644 --- a/bootloaders/THINGPLUS_RA6M5/README.md +++ b/bootloaders/THINGPLUS_RA6M5/README.md @@ -21,7 +21,7 @@ The board will enumerate as Renesas RA USB Boot. Then flash the bootloader with [`rfp-cli`](https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui#download) ``` -rfp-cli -device ra -port $portname -p dfu_c33.hex +rfp-cli -device ra -tool e2 -if swd -p dfu.hex ``` Otherwise, the same hex file can be loaded through the SWD port (using a Jlink for example) diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone index 1b5d1ad1..a43d0aad 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_azone @@ -47,6 +47,7 @@ + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml index 2c582d12..a5f857cd 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.secure_xml @@ -93,6 +93,7 @@ + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs index 2e1942fa..3d622471 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/com.renesas.cdt.ddsc.settingseditor.prefs @@ -1,2 +1,2 @@ -com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration eclipse.preferences.version=1 diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml index a3435df3..159e329b 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml index da5d7ba1..99d90ea3 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/configuration.xml @@ -515,7 +515,7 @@ - + @@ -1147,6 +1147,8 @@ + + @@ -1186,8 +1188,9 @@ - - + + + diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt index ebd60f4b..078101c4 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/ra_cfg.txt @@ -161,7 +161,7 @@ FSP Configuration P411 21 - - - - Disabled - - "AGT1: AGTOA1; CTSU0: TS07; ETHERC_MII0: ET0_ERXD1; ETHERC_RMII0: RMII_RXD0; GPT_OPS0: GTOVUP; GPT9: GTIOC9A; ICU0: IRQ04; SCI0: SDA0; SCI0: TXD0; SCI3: CTSRTS3; SDHI0: SD0DAT0; SPI1: MOSIB" - None - - P412 20 - - - - Disabled - - "AGT1: AGTEE1; CTSU0: TS08; ETHERC_MII0: ET0_ETXD0; ETHERC_RMII0: REF50CK; GPT_OPS0: GTOULO; SCI0: SCK0; SCI3: CTS3; SDHI0: SD0CMD; SPI1: RSPCKB" - None - - P413 19 - - - - Disabled - - "AGT3: AGTEE3; CTSU0: TS09; ETHERC_MII0: ET0_ETXD1; ETHERC_RMII0: RMII_TXD0; GPT_OPS0: GTOUUP; SCI0: CTSRTS0; SDHI0: SD0CLK; SPI1: SSLB0" - None - - - P414 18 - - - - Disabled - - "AGT5: AGTIO5; CTSU0: TS10; ETHERC_MII0: ET0_RX_ER; ETHERC_RMII0: RMII_TXD1; GPT0: GTIOC0B; ICU0: IRQ09; IIC2: SDA2; SCI0: CTS0; SDHI0: SD0WP; SPI1: SSLB1" - None - - + P414 18 SDHI0_SD0WP - Low None "Peripheral mode" CMOS None "AGT5: AGTIO5; CTSU0: TS10; ETHERC_MII0: ET0_RX_ER; ETHERC_RMII0: RMII_TXD1; GPT0: GTIOC0B; ICU0: IRQ09; IIC2: SDA2; SCI0: CTS0; SDHI0: SD0WP; SPI1: SSLB1" - IO - - P415 17 - - - - Disabled - - "AGT4: AGTIO4; CTSU0: TS11; ETHERC_MII0: ET0_TX_EN; ETHERC_RMII0: RMII_TXD_EN; GPT0: GTIOC0A; ICU0: IRQ08; IIC2: SCL2; SDHI0: SD0CD; SPI1: SSLB2; USB_FS0: USB_VBUSEN" - None - - P500 76 - - - - Disabled - - "ADC1: AN116; AGT0: AGTOA0; CAC0: CACREF; GPT_OPS0: GTIU; QSPI0: QSPCLK; SCI5: CTS5; USB_FS0: USB_VBUSEN" - None - - P501 77 QSPI0_QSSL - Low None "Peripheral mode" CMOS None "ADC1: AN117; AGT0: AGTOB0; GPT_OPS0: GTIV; ICU0: IRQ11; QSPI0: QSSL; SCI5: SDA5; SCI5: TXD5; USB_FS0: USB_OVRCURA" - IO - - @@ -558,7 +558,7 @@ FSP Configuration Bus Width: 4 Bits Block Size: 512 Card Detection: CD Pin - Write Protection: Not Used + Write Protection: WP Pin Callback: NULL Access Interrupt Priority: Priority 12 Card Interrupt Priority: Disabled diff --git a/extras/package_sfe.sh b/extras/package_sfe.sh index 2386780f..a6e10e2a 100755 --- a/extras/package_sfe.sh +++ b/extras/package_sfe.sh @@ -38,7 +38,7 @@ mv ../$FILENAME . CHKSUM=`sha256sum $FILENAME | awk '{ print $1 }'` SIZE=`wc -c $FILENAME | awk '{ print $1 }'` -cat extras.package_index.json.tmp | +cat extras/package_index.json.template | # sed "s/%%BUILD_NUMBER%%/${BUILD_NUMBER}/" | # sed "s/%%BUILD_NUMBER%%/${CURR_TIME_SED}/" | sed "s/%%VERSION%%/${VERSION}/" | @@ -46,4 +46,5 @@ sed "s/%%FILENAME_THINGPLUS%%/${FILENAME}/" | sed "s/%%CHECKSUM_THINGPLUS%%/${CHKSUM}/" | sed "s/%%SIZE_THINGPLUS%%/${SIZE}/" > package_renesas_${VERSION}_index.json - +git checkout boards.txt +git checkout platform.txt diff --git a/variants/THINGPLUS_RA6M5/libs/libfsp.a b/variants/THINGPLUS_RA6M5/libs/libfsp.a index a7e21f6df5f6b8bfe0d72597f5de8590aaf58f9b..345bc6143bbd6edeb8934728ae8b1451d62803e6 100644 GIT binary patch delta 5449 zcmZ8ld0b8D8~?ntOr{iSy7#7}h?@5OGEFyWN|T9(kjRoDGnA%eOJ#dy=|*wvS7SG& zg?cRMgu#&JVoF1($rO@e_!$!Y-h1wO&+Yo-+|NDV_gTKr@@}UU9vZZgC)+~b$J5=- zOX^c>!z8Q!`+A(LOb)oL#|`*0%Iqc)3>t|dDtRP_O*V(D_vq4VUfxqN<8WUj!U->W zLBfmPsb{GjrgDja2n>JKxvNhh#S2ewWDdPg>a+`(TFm5}&fogfDZ9jAHbh<0QBVYT zU)O=|>$> zLd0-C!QcV)2?Xi&8C6hb6G{#l2D|An$qYf9Gc^bhXDi01GGngqL#MV6cx!7R4pbREw43IXTWfzEdp$zKWdR#MTr&dUaVi*QfakujR$;w_77x7x#HtoZ--g)D&|wyU82^>kRKzQiu;{EG1B5Y2lU2!`|4W!~#r824=Vlf}DO~(?DFvAz-MNm}5fbq}w3Bqqbv03}(~?)Y9_#FqNuMqJIjUh0AP5L78nJ4$)Xr zC7O&u^iQLoegemqj)vIMplU7H9EX1lg7A;u-2O(}h%6`=WI-XNW3*vYc?g)w$DH{D zZu@HtwEY#DC&1gCaz!}b=3B_O2`gRFBmM)p&z>;ovuCVDkN8!|3Tzn*fi2%T2o(sw zIDRs&atenkr*T%Hv;rL|pOO5ej3Z0t*&pD+*}1-&w5dYG9=h|uLpN@#7AMm1VR7&% zZ2rejBgmN#-8nzHea}$Zkn6qRRp&Eym|P7r}YYM8_30;Etk1=qUQxeLSx&omfdhs8{F!iE66y=x_G?@D_{(=Od!zA*|n1*bz( zaK_a!lv?4I3@F^P>O@a5F;2a|3R3T{9w?xg?Afs2Zf*4fjVl$eO}T4fQ|`K*->YG% z8`F4UkO+@{vW`3$Mn72}@HN%o2(;K`LW|vot8|)6nIb|N6UtDXu+fqBj&xo5#9Pp# z8N$GxAv+c%Qgvfy2N*LuS1#rOMq#%`jPs3lLB7%M=7oY$l7$i+nz|c8Q}?XaM9ukX zySfM3uI}xZDoB&a#Mm-uA6Nz{WE%vSTh}XFkIQhmQUT@4{i*!ambzk@C=XUN4zu{CWj|6)~!7P zy0u3)t)}Yg#1~CI21S#PzuZFgxorm%dQjQ=>v?`hlQRCIycFE&kq@071$E&xO@*0< zPvQ-03Sh&U6GA@R)brR;c>)}jg>Ez-Zp@66O477pMUWa+{JVySkPn9BV;0uCRSbH! zN-TQ1wqPoB&qm{Y;*+pXe5#)M$7yk=AT6%co5t#A$XNj+*p1Z8q3dUMQMSFE2z*t=R<4YrrH9;*evoKm_?Qk=QjZ|iMYH@t1E|T zb?0R?9(Q&0qRbNj>8IcUjnfw{k7z>aNxg8hQbOhF)Bv(dUjk_m5tL`$sRC zrStkk+R09g``P~n{p>HV=ht^BRwP{pMbedsL_v<5PbQDAfXU;lwOIm8b~h2$S^PWb zEWXwpMH|24<~8WJc|GzI_1M5Fhz-0kjdlg`u2OHTxdDwe)tjk06LV52!JA$FfXyz- z8$z}T3Na^dR%k-vW`dv3E%5WXZL(hA#K8;L+pvKBbBz{EPNE?-U=mWha~qY$Brj0( z;EowBfQS0%{%Cp~JevMjNgZv<_}o?rF7>_(rQY|lk5E*hnvAgz??LRt`k-GmMlm%novt>S~7ku9lt2RG7Gs;5mtpVNT+caqD}a zVqDYt1Zp~;ZrjPDm>7om+-D_6sZI4&A;7N<0{ot@&!Te5s^_4rYX7*L%BfnBoJ@l| zpe^`C^;!yJa?*gx>X(E0v#OM&oCvP7{I|^V)nHm)HHc;VUx94@>smpZXucSQ@bqE- zgXzQGG>qk~daBR!(aCQhI{Cj$ns`suydlff+y9Q}zJ1GY=TfGj`hx|wOL_-(NuBzb zhR;^Nkl?ZJJ7Mhm_okGbr+PwVgmytj=!eNdk%$RssQzfDrA;(D-4Kq9>^>J6iRb}J zy3zk2V#$N<@b@aI>i#d1d${*PtcQDVWc5S{Lv^Q=CrES<`O!sefDIb43N(Pa%KG>#478p(c!t80djbi=L8N$Y)+sJ>J_6kz@GfY23@!2G4Gtp z9Jzj4=Hd3V@Q#CC_-p*vqu zRh32d-%LBC{74~gx0N@pABNb*^~2GJ96GSAQQw?>KhPdE(b-6|)3w8%6m5qCvj2k$ z^LZOR_e;c%p6iGX@t@=(1I{3r{=xJ4P7zPN=L(1H^eqpPaaZvN1Zz& zKOUqD>O7Hy0X4y@GMsvps*}$pVzxZf3+){tNX+=n3mKWySDx_3dM~t)Ki^BeE1bO1 zQ++DJsy>+Le$LxebdWa@J3!`*^x}Ao9dwMmrSS?rBroP{;BX(5XhtFKD;N8xpAXv5 gU)#{~aX!e38fO(#eNcZ&&PRP>Wp5?=AhG@b0f-0RQw{^R4NRZ?ES4e2(|$c+NU_B&s7{N?%hqcW0%u z!aduDiP8Trm**D6cwMDGnA<5emS8ms1s72$wJ7EbNdAbfyrqa{=8+yqf+Jsdg2>mM zFj7=W zy#nFisS8!mrikW%eWGYD9cFZhQ&JlO1o_-C)|b0P%^fg?U_tOhhUkP~i@3^wL&rt4 zsHlQuUNjGW$rkMtAP}Dup)P!YI)T}+;u7&sA&ox0t~W#t0!A`r37&UE2X0d-f=Hkx zqwCXa6k*cs)=4%*bjy!08@xyWb*1+%H+w)!ui)*E+SUERL@Ktk*vJyQHgpHqh90LK zD5~??Dl=~=ridnC(I6xNvuEagDkw&DC0KP?464gL6>^F)MNYAnIQ3mmNPX99=^VZQ z*gUj1n1@=N7UVQRqeMuGE0ZmtGPzIMenCIMVub{!IDA1qOGt5$4CMPFOHk#71}f=m0$ptOHqMH+>%IHxa&bNVHY;1M^yer8QSoLSQ!GHV9dS5bOZ zm#lErC2OdqzNx|W`?f66rHIlg@fxY&F+~{0% z+p9W6B7CD61aCBh|Jce)V%E_PSjQntziZ=F@>+r?EFS_BmJdBO&Jeb~J`}9454#f} zz*&`L5-hf`2eHMMK8XS>ZVHj$=pA1|^bUtt6Aa;mItNIobIhK^b6^Mu2@V|X1c9T6 zht8nPGBbulX2yt}!Gd-X$1MEq2nc`c9MOSUy_XBrd$}I}o|jfKI%a25T;WWLd8n?hDQh-hB(MRaoF=zvbF9q{j{>v9U!MzXgE^y5-hK^F-g?;kQKMFqCiKNl z9^ZhIho{EBO_;M$k3FFtt0o%Qkl>l+DwtXBRYohQi$%hO{p>v(=i82kd|Pkq*Jg>! zH5r4jpU1rD0Eg#|f$%(^5(C&02Y&W}z|Y^_{npTk%EuQ}K7M&)4PgtlA6Tfzp6dYD z|2-D!|Mt%i;GK?X5`5C;J2+_*khiQ|{0DK@eF4yQ-?+Z*;^&g(T{{lEYrnS_DiC;i z{A6707zo9VK?D401sY?6pfPrQr~nW#2)rD;lmZNqkm09hKfqJ7337^Jl6tV3G_jC+ zb!T2@MM?3ejEV3mBgAYxwQt@O0_IJV*3f0kohjlvA=_^LQw9oWon2f>Z1=E@hVW#!NbRYaYXBs@unf`%Rf>$A9 z(E4GEbz>1$Bu;S+)6#hz=KD^RqA*{4nG_no8UHpnHx)F<@G-C1oReVDd zX>Qt(cp;@WvO8TFzG8^96kn7tfs67ehgCG-#;ho4%=*P;JXPnKkzv9ZN+LHq@U5d5 zv7umde!-T3JS)AFKCU$;TVah!@=JjlS8^Fn9-j=!7nn1?;xC-f5@Rb9m3Tyhsbvrs$-7a=*^?fI4kK0WF;L{&E#$zR%!G;4}F0GRl?7tSpn_ zhsQ3%!(&(aBv5sZuoU+k_B-?(c6B4azALaM`YLFmuLVa5a=IBMes&GS&#spx3ozN; zB-m)_A7Hff#?w%mzsB1)pz-$2kPhnM-o+5^eQO%+3qqAsuP(g>)ukm{sX8+wS1ZF? zhyMv%hih-q05CyeM(*vxwu}%?QtY9;10Kq|;*B(`8q>!zypX*M3)#QcwMV5`>{kk6 zzp~vsc>b=KoC6`N@?IaBeOLX-`^ofjcryL(9R3)sU>2v<$#9#iRrvhYW;E#`nJtxyH5AbuXN=4qfst8NMl413oqKg{6@;K z8}$t4Mm-NQOi^j`b0}?ov12zci-}=aoc1#37`3UtD|mU-gO|svjmcC_Tl@;N#SNcV zQaP@V$+^_G5$b(km#pVuIVSrq6qURgNawp;C%B>izxn-}2GZi{L99w|0#*9kGC`YY zz8;P6^dbL)=|kRC@#lPnTz{Ysi+KlOG5;me#LM-&x$*n|jvBvz&u``mrmEyqUu+ls z0qmliO)(|L9SEd&+{b1Z_wl2J0Xr#9^lyPg|4);JDiIq{Rr1-+P@SkYJ0lzt(t05z z1knSOVzcKV#F7u)+sb>>-w@TVE}anT>e3kvcrFZZw@P)S%m|S`#)yrSnV>hF`7CP! z$yHRQP8?u@*u(**==~mkKplV16tVH=x}clz8|EeGnBC1S+3Ea{16 z9WWeNCGJIxi+iIR+xY?gjaEJ9U~k0EIcS0Q@ON{Co4%pd{o?x|wqN`gXv$x_Uk&G1 zs!j{GL~L5H1bJLDwACn)BDPT?Ls9(wTCkPSAVX|ILtpelOI6g7h5bk_3;Uy|mjtfd z>Z6WM7=YO51S{k*l?rnWX{pv$SRqzhVU3Q=qv_-BqUu!dfrw4@wn3fv+o(c!M`d$= zwLv$nsSWPoNWJHZ4btqnVvGKxFkVVvP=t==&5Zr!zYBq9dx?MIkOoc6Nvpn);GL`llPV!fQBc zh^8QWo4i6K(lwUcLCMiu9qB%TRK(pGE#w~z6iPksbNxooPer(gDb{{mVm% jHqqr=$y-_(q(lR{QA?VsO4O^3p6>aHy%VKG(qaDxqfX Date: Mon, 19 Feb 2024 09:33:04 -0700 Subject: [PATCH 06/13] Typo in header guard. --- libraries/BlockDevices/QSPIFlashBlockDevice.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/BlockDevices/QSPIFlashBlockDevice.h b/libraries/BlockDevices/QSPIFlashBlockDevice.h index 75f8187d..24db21cd 100644 --- a/libraries/BlockDevices/QSPIFlashBlockDevice.h +++ b/libraries/BlockDevices/QSPIFlashBlockDevice.h @@ -17,7 +17,7 @@ License along with this library; if not, write to the Free Software Foundation, Inc.,51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* ########################################################################## */ -#ifndef ARDUINO_QSIP_FLASH_BLOCK_DEVICE +#ifndef ARDUINO_QSPI_FLASH_BLOCK_DEVICE #define ARDUINO_QSPI_FLASH_BLOCK_DEVICE From eb3edbf0b34936bf83ddee31ede4284e657ac812 Mon Sep 17 00:00:00 2001 From: SFE-Brudnerd <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Mon, 26 Feb 2024 10:35:52 -0700 Subject: [PATCH 07/13] Update Project files. --- .../SparkFun_ThingPlus_RA6M5/.cproject | 122 ++++++++++++++++++ .../SparkFun_ThingPlus_RA6M5/.secure_azone | 1 - ....renesas.cdt.ddsc.contentgen.options.prefs | 2 +- ...enesas.cdt.ddsc.packs.componentfiles.prefs | 4 +- .../com.renesas.cdt.ddsc.settingseditor.prefs | 2 +- .../.settings/language.settings.xml | 4 +- .../configuration.xml | 71 ++-------- .../SparkFun_ThingPlus_RA6M5/ra_cfg.txt | 54 -------- 8 files changed, 140 insertions(+), 120 deletions(-) diff --git a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject index bb919db9..b0624fd9 100644 --- a/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject +++ b/extras/e2studioProjects/SparkFun_ThingPlus_RA6M5/.cproject @@ -84,6 +84,7 @@ + @@ -109,6 +110,7 @@ + @@ -134,6 +136,7 @@ + @@ -182,6 +185,64 @@ + + + + @@ -338,6 +400,7 @@ + @@ -363,6 +426,7 @@ + @@ -411,6 +475,64 @@ + + + +

    c^g>Wyd_oN#Ni(kOStEIA3k{{h9Y~ypINNy9B z-qfB-4rfbzr&|E3S=f%cr~^OByfLcI=p<+T!uI@$S9voj6r9Y@TK?O)SMq%hB{@44 z+)Gwl$q%|Ff({JyPyQ$qzD~N`GbgjLXG_VC-n`6d&Ot~VJM9M(PM9>@BKg)xoHSa* zmPQk0d-P^zO{RQ@Plz7C>@o6S%0kKI{Gs~JH0AsTyEN3#0V`hH|;u~ z8{M?Ke*}X$x@lJs-L&K7Jq@Jb-`=zfYREV54-{;F(~h0g3HFnXOpTmeNfm5==Wd>q zU|G`1<)9(oMR;8PM0f5=qdRwGt|K$=e10C{fByCSC@1$e{sfX?w!D(wqMck?#|b1O zZxTOWq_=>1SGGuo!36Y^VRN0_pJa<<{0DyWhERB58VqfP;3UJ)j!$pNcXEfz7RfMM zrl+^~PVQvcA{l1Og7lV{lRHPYNQT*RXL<|IM=X{tl3}Db-ysqHsq`jOP?lop=N+Us z9{|nma-=t(_Gr&~Mkdmm(hJH_q8yI&rm-^8o5spWZyGBjy=knB^ro>g(woN0NN*Y| zBfV*?jP$0lGSZvI%1Cb-D)gu`<$|#>z-<8Y?5cX{?O&rm-^8o5spWZyGBj zy=knB^ro>g(woN0NN*Y|BfV*?jP$0lGSZvI%1Cb-D)gu`<$|#>z-<8p}#= zenwBGr8gx%ExjpYfWAh0bBs^_Ze%ndy(uL;zT$+1^ro>g(woN0NN*a8?~&9S=}lu5 zhE{shSY@G=-ZYk#-kgrFwDhLryYujb^rl3~i3sV<`IHE=NN=tbWESa7VFZcv<};+S zNpF5G$m{xY&)P}>TIo$;WUoPbv#kdC7o|7*gUKenDc*<&>CFR$HH-A-8G@|t#$9O} zkK2>?{VGCX1c~(K^@99U>CJV*lSO({_~Ai%^Bv*IBE88e*~uooDU2YI-Yla;HtEe8 zL5}Uhg`XC+e>c>KRifp&JmtVyE2`N2(tAj6HfGlPSEV-@Ev#{O=PC2;r8mVJ@gTi9Ojxr>ZyqnmR|fKcxvhzn z-V{cVNN=tX`jSm(wn0N zd3-Iez1vz^=}ln-iS*{Ng3Kbld5IviNN)-wNTfG!7Ubd{Jhu~#7@FKjZ$2%^EYh38 z2omYdErQGt&2^-5#Bq*rz=rhZJEXEnZ#ucK&8Lrdklqvy zkVtQqQ6ii4W{n`DJ(1oVPl+4}I7j&Lg!JYD@zlOM zk6cHwFz5VJ>COAZQx@q>;fEFJ&27T^7o|6Ixva@1y(!*cMS8OzCH|`P=Aptmn{(F= z(wpLqRzZ4m8mSx!I7j&Lg!JaEr2eY(<}+ZjNpA{2tVnP2wF2j_N^iCWlTCV4yb(Xr zn-!GEk$`iAA5Tbc%I5(7s`TcC;wg*trtoupg7oHUVYSkmbID}3V5K*WrP9)y#^PN* zk>1=QtX6tc^3&3r;*D65-Ynsc%wLt>tOAowdQ-f?iuC3RVg0`%z4@}lmPL9~VkS1E zH$RiuvPf^{7lF(oy(x_J0MeV2SPDu@Z#L)wq&FM%0MeUL52!Y~@GP3OGSZu7TSj`* zSQ+U}V`Zc_jg^t!G*(7>(^whlO=D%GH;t8%-ZWN5dec}L=}lv0q&JOKke1#wRz`Z$ zSQ+U}V`Zc_jg^t!G*(7>(^whlO=D%GH;rYbH_xYK)6$!g?=I}e({fdz^a;I&^yYGD zdlA+AccnL96dozHgY>5G!-MqZHsQ%4y_w5$ayIErVFZcvW-m(ox%B2J;Yo4M+Ch3# z_~Ai%^JwA8BE5OBAhSqs3L{9QH*XYV7U|9Pg3KblDU2YI-uzsULkF<{n-)mSCcRn6 zGP;{ZdQ1=aai7IZYX|8~xv`Z^dQ%udBE8v} z5`QkeIaqkm3)xY6)7&^S(woN%&!0+f&KI66(wo9hJV z(^whlO=D%GH;rYbH}@j`wDhLryA}Oehp7&w=F|}B&8ww`vsr&bdeb1CwDhL2GSZvI z%1Cb-D)gu`<$|#>z-<8Y?5cX)Io`sN)=A z zQ}WZ&o6;wop^)BmThR9ZLg~%+@MV+Ult?%NBE30AJpM)L&FR9LMS4@b!HV?ed|}NZ zy}445YwMgHr8k8UB+{EbT7q23vEYAPdUH6Qvq^7C%*2ND=F<|}=AE7YdFjp1B(^Nl zn-VjzA-!4GO4^O1)W1l2a~yoxq&FoJJR-fhR6IV$apFHMy}3qw+|q|95v*vSmEIKJ z_&|EIt~EX$Vl@1ZOK*!;FT1 zk@V)#@MV+Ult}Q1^yZ!7@xLU!xlw#%k=_*F_&|Dda1tNwcH%iYD~#zFdCUI+>CL0@ zoK1RDVkS1EH@Bu^`yZFyOtdAoEYh12GqEAPSx1S#D!nN$aAlL;6mPI1y*Wo%o9@Q* zG-=s8Rb0dQ*IJ@NhxF!+!jnaMQ~2RQdh=1?$s)bES&)Ztbl5?9Qy4)az1g!J$bX^q z<_P$*NpDIdctm=0vUtoQy?LP^vq*0WBS@q-pA+PNNqX~3@sUM(Q+(qC>CHrYd>qEv zbqDFqF63vE-V{cVNN)}o|!aEYh38&!|Cq^EpyE z5>$>b!j1Iix1UeM=JbJN^gSuLwYkD@o%Izzl1xR^rpmtcceG>>S(?HC!{yUdq#Rwyzd~rc`V%7 zq&Fohyd%ANHYKu2Z{94(EYh382omYd)q>0-y}3n@S)@0G5hT)^KMOL8^k$1rAhSqs z3L{9QH&3O+e^z=k+)jEk{I}AZSBd*9(wh<%?vdVnT-^6%N$cO0-h5wp+U?4te33Yu zTU*bCSY3heGYFC1{DD-C)Fnq4;YND1pflVevAKiv<}T!Clim~#kVtRtDabvT;O-#3 zd6XctNN)-wNTfGs3o?uJ<_&_(BE2b$Ad%jDM37meH|6+{O?p!pK_b2RgCMg=Z#HFy zkWG417(pVvxeFz-NpFr6W|7_$Z?Gc0dB3op#NhdF zk=}e={AZEgl(_JZ^kyXk>Az2Ub1dxHq&Fol{3E@2k@)Y*DE|x6o1#XQO?p$j!HV=| zUJqC|@bljyy}2{Q*`zlmF8m|Cxrg}ABE5N}Am>qR2kA{=1c~(KEJ1EBy;CGDi zYo#|=N_s{=9!~EYJ}6ity(ziH*JC+>6wVWG>oa*xow)mIpWyr6JlQXAMk2nsi=wQS zXQXq@dy#4JP4lq`#5cRKrBKVW&n>h(728J3)2QvuTap>^O?k|;qj^O#Bfcrmk9OAb zyk{3J&u(@#FH|7Dc|QKSX?YB@r-;{?SE6i(?8Szbd zy0J<-aX#v#<*CCOEl&{EnU^Uu;+yio->zC7(A!PR<8}SCJRG;Xd8sljzG>d2M0``C z>aXPyxItPTSsQHLs?3OQ%Cl&DnKvub;+y7$%8dA?JV!R%yi}PH-;_tfMre7wYovLv z67kJWwB@L{D3xZ!H{~I&L$o}Qb!hx9NYdh)@iCM_d~-E%P1N$()zMlWcsfSQ15C$i zd35MFEf4M-ujN6U6XNYySj&iS$`dwIwLFJ%l9uO6rfGTl;$$t)Fr1?0nS@j0JpiP| zH{(`(vn>&xrse5^bL0Klj`-&JL~vnzJMm3_@>+^ zUlh-yY({)jZr?7}a`SbGmK&){<7I5lh;Pb0(QD)F$U=N`2mxKEtsUMToqyQ_)#MY0=+Db@C zF2i&E#CGDFFiDc{{sY$v`MllgXkKanD&jQD0^SiSRy_-0}(7UG+tl|IOi$uxVWACo!r zEI)A?xMO7f5&lR3o0Se#cL@ndpEebkT1Dey5rCTF76equZE&BS)%n~6L7(`J2(4NEo|9WhI*^QJBEISN?(4}(ryzRwjJKWS z&9mn6=2_gldgkqve>{a7nRm|`nRm|`nRm|`HF)>TtMUd=C~pE$Tu8!1!Q1Gkk#5oC zTtOfIvKx!S-{J3&YT|)9yh20D6n^iC}--(P~2HW~Ou^v~g#cET;u}LF)WH#~LKWRnf zk8Hw@YTg>FJuiA|tjS0kDSB(njoun_qqoM~=&dm~dOwW!^t;00Z)+oM+H@=~^dNpv z-hEvDY^TLS<~oyU^jBbzHditFaL%YvY*3v^UbLS{{zx2`jx@<82JW9Su@`)(3f1sj&w3JITLC$zlp@h?1R1J{u)#aPfQun?Ull z$lDTNuSdBnNWK{**OGiYN^T5o<{pv6h4pYe{q&M$ic( z){-z{EeRvmlBn5}{Wf95S`tRAC9wfttrAA8C1J!`5=N{gF&T!o2_x2$Fk&rlF)OXrL8XId+h{znQ|iuJvWljb0Y~o_hUl4Lb;KIo*PN%xsimP8%gN7k%XRm zH!S~$x%Yt5syP40?=y4Dd*A!E-DTOO?^1+adfUP-3WyCv0Xr%dz>bw*SL_XI>_o-h zV>k8|QDZb}>_!t~4+?4&V~hSjpP9KY?|RPHljP)=^XDAina|8T&pcD^+`0EY`=Alu5jyT4qU;fR>RK4Kty1;~J!Oy3Q}zfwWslHPr^A+ywX#R(sV5=6N-KMWp0Y>i zDSL#TvPbACdxV~{N9ZYggr2g8wJ3Xpp868i&hpi84E=0h*(3CnJwi{7+=)l%spGbV z!;-Jo%)#Fh_{tukr!Jcf=1^bRBlMI#LQmNv^prh9Pi-;_3mnLoV0CSv=1k-MPfgtl z8^A!>BlMI#LQmNv^wf0J@aI6;BlMI#LQmNv^prh9PuU~%)M+sHg-8v+fd4U4ePPRs zk+MhVDSL#T`VQ5;5~(Ml^VLY%BlJ|`OkD1fvPbBt=V8*liLyuNDSL#Tx)B1)i^?9M zr|c1W${wMo>=Am(9-*h~5qioVp{MK-ddeQ5r*_^Hm+D}3F>2VqPT3>$ls!UE*(3DS zbhKenow7&hsWF(%i|dp z>=Am(9-*h~5qhc{8aCxu${wMo>=Am(9-*h~5qioVp{LeGf6n@?%3-$dyiz@drtGp( z*(3CnJwi{}BlMI#LQlPflDn-``(eK9zA{wkc^;t`riZnJ>0vEldRR+16dl7O^g=-| z@UWKf7+jt_LN81YYYFSn7#^V)?u#-!LN81YYYEfCTEg_OmM}f6B}@-%3Dd(`!t}6~ zFg>g#Ob=@b)5BWAMQ9|C&0vG5bEut1=!NNFE#V}X$|Ll`^stsNJ**|X z3U^8#p%g#dI zSW9>VdV@#kh3R1}VR~3gm>$*=riZnJ%W=o#5qe>ISWB25))M|1D>Lpw*yQ1s0T(bY zTpt%RkI)OthqcsI9M)2E0*do&mTs3JB3=~_YsoXgU2VaXtDk~pf0NsJ9LFMG34peH96y&JJzlOR48v4~3e zu>GkYoX;|xeg&3BnN@y#4a=|~o_=q`u<9wMSf1&@q>Y03IYfre#B!%M3HtrT6s)-& z0i)&`z~Lt>QKTL_(l;4dQbUi4W{V&itSoCjtt-JQ#36a2O?-Z-SJliM zCItSpru<%rm}_a%CUa%u{8FwYGaM>moHuNWm!g#32I(6&+3WQ*bna$N#i>X~k8IOa zwK$JqdHf~}OVdDiy*>>z$03pDfwp%@$tyrRIHcuGpdB6Z;!a>Ln8Bm7CEHk zhV!xQa7fFZ$Xo0X$O3>4b|{d8fDUmel-D75s6&w)g1o~V%E+IQceq2b9QP}{&vYm& zrvM%4P$Fjn9pz9?&I3Byp}Z^uTH;VaE(bcsA@;>SP5GP`WRfZXEzn85#4`rQ6C zr4A{1ALufNw0sP-+#wwC4RpCff&2sL3Wq}ZC(xA+Mc@ecysI3_2#@=?+M!r(#?V~j zP*&~)y4ImY?gzTgp`3JJ#k=02ygY`y8yqUg?|^P}h~0mFQ+@zis@X>uHudAZMi*ey zO-(iIBlN``O;vfkik2hLTX#80PmTq;+aZyYfqvtVk~4traY)O#K=(R?zhMKq&!Iq; z1KsaXDAxcz;7}wt0X^tYMs5ds$e~!CKOL`B9Lh=wd5<`h$g9YE)S;ZbjkWwShw}0v z&~F_o$ZDX+9b#YH(v%;GmTGPhZgYLn0c|UqYS>4ZU*|T(8=yqQ$>Bxp7S6cvvJh!J|J zsYs3J{kNK`POFBVq37b()-=E^ilc$vc1WZZ=&uebnF#cbLt54cdeF`^r1r;*#+n$hhkZVrRr}EW#tN>l@29xJXeNPaMk2Z-7=g zRFK=TNnGs^d;j&O{LN^oW*_~jsh?RCZ^2^xX;TgR2z~KYQ`H4E=!^M~{Mt$4FHeEK zaR`TN0DbF_lEpyZIi%$Xpzj@m*EG;S9SY=RpdTCxeMT+@5{F`W z1UMUE7@Ao(rh4yF;9b z#pZY@O6h$t6RVo-?fFa8Ue{ctM)ZC|b5$+g6Usl4+P^uyJ?rbRFLFpE1{&y)k|NL` zhqTlJt>cg{zkxM_9SWou@`gARN+VE{Ly-&yYIZ0i!-0l66w4{FWtc-*ISXjGLy24f zG{T{rTnaSOp}brTG|HiZ+ype*A@+Xn=6ow!s@X?!uZrMUhlI~2+YzByQkXn|9&Kn-9Hp3)Sb$&$R8 zdl45>KjI|LL{yOT>PDQ7nl^8y;GjqJ_RS9>q6gw<$L5A-86S&LnA_a&iv$X4KFi|u zCsNIpwBY4gdcY%kyXJQgiI(99)AvD)q29Uqk3fO!-yCn4Jj{zfwU_aHItftaHj%to~pq_UJVlU$)L)iv;j&&%4p2M1h zqo`*YN*&?!&>!=-X2+)~r!~h{rFzcjqUX#CJts8>Pf*X3u;&z~=N!~^R&zrAu;-%Y zn9P^5QzH%m<$U$V_}~SU(%ZI_x#jfUh`&2NIR)vM zjo_AB))Uq{Zn-5$#Lmre%NbPWmNTf#EoV@fTh5>|x12#`ZaIU>+;Rq$x#bKhbITc2 z=9V+4%q?e7nOn}FGPj&TWo|ix%G`1WmAT~%Ds#&jROXg5sLU;AP?=lKpfb0dL1k_^ zgUZ};29>$x3@UTW8C2$$GpNihXHc12&Y&{4oIz!7IfKgFat8Io3i8qT;6aR}z8Blj zmE-G~t`ET_Kd>d?9KcwETdt`W#@BJnnG$eQ!h8U?oIz!7IfKgFat7s!Q!KZfL8YSO zmNTfn=(yz!>J4iKw*=Esm%gzH_ofzW&6%hP+;X%M7a_Ri=AlHfE4Q34>$U_ZP_lws zPMv2m$jgSPl+$D(pgj>#+=`F#-l&s*E(~et?8gbQtTkZ=={_EUwzS^cGsO=4{ zCyd2oc1yk4XEhJS<7!L7+F%d3<%XlgPq^iL*{da>>xyn4R_2z|YLwxYqee)ATkaQ> z{5ftpUw+XNTtGb)+;aML^y^VA3H3t{xaDr4p03<-*t4|+FHrLDu=jY&{-sx~2Ws4w zgc>0UZn?iva=T`H-fCIihl2a#@ zx#jdq^uU!Z2{l3z+;TfovMaZoFW0pMM^o~Nsdxf&)*iYMoETaXYJ?=XZr*lX|*x%i$o`*5EcuR&dMd9vfn(-kMM&Mi1O_?^E*H5uVrB$^(e8-I5iP zu=TM>@E#LrkVRnzd$?Y$LDT@PBZuQ-y5*MBpTV(baBITaU=O(E`k};6xaGj6(i%*r zWCgdJcHDB*2uX0u9f#O|%q{0jOKWg7>(~QxqRsMA=>u`atlyeUMmp*Mx7_a$`&n)| zUp8(HR-u%x;Fi;8V%s*WHKBg!0k>R$9nw#@<$T$yH5iO^UBNA<9k(1cLK56^>rt{R zx129Kw+6dVvVvPqFCB-MeXR*KLK56^hf=aDw;b4vT7zYjtl*Z@?_o?2X-%jRlHiuR zgOXjj<-k?Z8ko236Wj3u&h^&}^w){42{l3z+;XcZ`9Le)X<0Tj&F$c6twFIr>a5_F z(`(klI@y{~BP78sHy9;;!Y${^g{|=>l&s*E)3;(JTi#lvMo5BNZWl^EH>r|a4({`q zAC#=%meWx14s|a?}V(aLWxqiJx%G`SN6Iya6RExaG9t zmZL_r0NirhAy#0;1?qq{aLXNl*iX3Se0jMw{w31&-W%X6z8jmPF=O6pEm8+0!7XvbDPzSVuTkadge!?y1%O|ZtuYu5Z z2YPR{n?)~U7Jb>8PzNNzEw?#J{2SbIzI@#p96+s~VSRMma{6P;Fx8f@HfRO6+||_j zuXD@ckCNKrC#ki9TTVM}Io1ZP;FkN2TK{!!Is7?NTil0FAggg5b$2XrZ{YsWx2?$9 z(4XLz8;ueL8eE`$)C6w11xWihxaGhT)E1n?nku;EH2=P3SX)B<&FL`=a%zj zbX)uuweE~LFxJ`s8m_F4wjyhTR&dKztplxdu}_`a)(`g)e7lw}P<}&;B$RGI8#%;# z;JR(`SjgxKZaF;{k{h=bSsO}#TW%wiDA3>n^`jr`zrihszgcaIFM*6caSGhM zo&A?jfXh%@k@}$(+;T5a>s}b4U964Z@oUB%d0yH62)l>*ZT+T0KxqH=ZSfb>`s`G^ zHE>!dq5TWmimVMKz%3UIhUql8K>er*+;SaA`!~4deA%-t*by?if?G~skE`jRwuJie zd;)H{v#Hf_%Pm17o<$wEoIz!7IfMA#BjX zkXn~uS9iK?A+&CXUOdwwk!{dpXFJ4RIjJp(p-^9dJHjb#_LauABjIt|masNx1-G2} zL%IJow;b00wt#;)rz^PS^sTrKuWn0dGi(F5+=Gbygj){#>$ZS@IHxPP<@5?j-rAN> zBSrw+a_!g%rrdH%kmyDL+;Rrl5dgQGK}sCAoIz!7IfKgFat4*T|x12#`ZaIU>+;Rq$x#bKhbITc2=9V+4%q?e7nOn}FGPj&TWo|ix%G`1W zmAT~%Ds#&j)ED#g&bDBC^sE-F^mn^?dfp_%Eoc6iF(9|xG3@)Fl3lsw zzZaHupvQDH6_XPpBVyz%ADU7nrf9%q?f^ zS<5Zw%Q@{q2TJJ*ZaID6czp40PpBVjE4bypLy44IZV3{xwr+#r1Gk((Wo|ix%G`1W zmAT~%Ds#&jROXg5sLU;AP?=lKpfb0dL1k_^gUZ};29>$x464Ekc13&82Lq*F#LT#= z-QH;(w;WrJ7J^%DAxfm&az?VuEoV@fTh5>|x12#`ZaITu)c8<)a3*U!pcCJ#U5$=g zj+UTCaLe75)(CDnBk85was~WMHAFWJ7|x12#`ZaIU>+;Rq$x#bKhbITc2=9V+4%q?e7nOn}FGPj&TWo|ix z%G`1WmAT~%>V>}76N2N=vw9IOsbGS=%C5!^e&U3LV}d&rxaD4C-~V^G<$N_|La>H4 z9)=z9)CuU4)2I21k)j-E4bzKp19NQG$CPa&4e~ytfPWkPCITn){Q#AEtlu^^MB1P z2M%wvA2sWjaDV!>YyTa%pWinjq0O)j+;Z2`w*NJ^96r)d2>4-7S8&Ve=dpPIenLW< zVH>#RdSUzjU*eYYBj1iduh;Th1r9+`-gS!7Zn0)}W4r`k@Eha%WOcS8h39hI9nCQF0etZjM_{ z_eOkFM?#H|1h<^vCE0(8Th5oU9l-$T(=Xs>yle9uEd3jGB(wxIf?KYGHFo8e^JQ8` zup=caxaIWxNx08;B-98=aLZjr$^VpF4*Thj;8E65!7Zmx$NgzuN5Z;M2e{>4XB}O+ z<$T$_BlwPzEAZ}YPuH&bi0{{tP$MM4E!T*_{aJ1~Ulw)5>!Xye;FiL##lf3e*VQ;Feo~*w1py z;XJjD_(PP^72I)Cr6saFJ zf?IBVlqk@s0yRQ6xaBTGtoR>t%Rz1}w_LFcx129GWBh5+JgkYgxKaEbJ$PS7LOW19 zxaIob7Hw+(54h!6dzo8~wXfxt!#$@XSP#1OMOgJ7cC~Ma{&*U5$kq;SxouG5C){$l zcXR}YQnG?uPOpIEs~rh7!ftTOolVKE+;TX-ts}UDk`>%?`W#5U(~(dkB*88BdrEfY zmc#RON3e>LCu67mp|f@rX2GhCgc>0UZnXv(a`l{~WiR52Eb&PU@-PmeY<~j`}eP!7cX`Vg*^o={9H? z*qKlxB*87WB_+FZ%i%R~XRw%(72I;V9rI;OXF`pT1h?E7lc$CdrF+;X4}?F^=(l&;{G)5qcC-I<*U^+ON1<#wQ+uH15zxT}gH~|MolLF&FSzA=d9yRPf%RuF zTmS6(@ld?3`dep0yHG#4H(`kT&#cAxbCBg%cCj2Cd+h`!luvzu=a`p+FM@4~@`=cIB2E7VXFBn(I3Ujvv>__TUL=ez>8iPziN8wlnrt@jpf>l=p>!9 zPT48DoOQbfjcMhcHM|8#7C!!P7 z!iY{y`$lvp+ApFr&;Ajea}J2fH>Xp=xrlBziy}Iw{34>W$>NAE83#vnY&ayMqr#yv z3FmamI2X4QEpDqJOWzR@oeoZpNjay%ImcdF8XL#m6WYvQ1)mksf#4joAJFHv8Q1<_ zM*RGLZp07m=fz~5)3@8w=STd6eqo%SgtU}*F5;)%OCx@my)5EK*5z?M^Hbuvh#yR^ zhzBqY%ySQ7E?gP$Q|Q$(ndfxx_L?VP>opNSa^4W%!g4A1Tznr9$mfzAZe0;SUp^9( zd`{13H}*dklYLHa)?V`|bUYsML*ergKl;58|B13G|6Ke55eVp3qTEXnKj*z2@nhUy zBYsMIC*p^&cjM1l3Ji2=Q~Y&YmLIhq(WUQ^2nIU#-s3vU??6xKEI*JuqqF?t@w_fY zlX3k|sCl2tb(S9x-qt0@Kz9=o-_xZo40Kt(=l(%w`SRKGv*vBFpXIAx#3j`?m%1>} zWw|}P+b?xtpv!XScaNXtcI;k1%RSP4ewG`T`~56;8V>;BCiS47<$d=dKg%2C!+w_c zt4I9Og+K!*nm@XE6h;6InrN>M)D8p&x>s@4J?>|DoALttC;b1M?*0hpZm)`Wmpl{9 zB(Fm!nm^CUdsPwQc_!46fliN`$U9SaOF##XuXO|iO9DEX3C(`fe3Z-_1MFoC{aj`< zEFvmn>F4SP4n~w#u0@blk1TRNeSAX|S(6WWTh(?^bJT+qLTeg6n2hT*A%!~My%-`^{KlD+&PLUlOYoay?!a#@^E>?JGk?KvA+rX*MRn*o z&@bvt1S0Bc1WMHX2(+kYU?x1v?_wW``V5JosPLDlMpSPE8Bt>p#GcEkRHe_3^o=PboQ%wW>M!r2tuV!KoBXl z3_(Vz+YrP`y?Z`8ReggXQL1!rkXNb$K|!fm2#QL5h5)+53sIj|y%8v_o?VVK zt;PWPTD=PtX!Q+(P^*oR7-=;ZK}M@Z2x6_Sy$JQ8Iwv*ukJw*`RWe{GQN5bLF}u4T#5R8 zmA?x0`Dy@yoUhsur0?B!T)9$1hMv0ObR94uV3Uu0v1^)Nc`BSYAgU zq52eo3RQrKtV4AyYVbqV3n&QHXar%XHbM}EYRV<3FH}1M#i1H|9qJ3!CJ2&H?Svo~ zs_RfBAF5vf6+(3yf?}vHM}YDF4FZYOvj|kA-bJ7z^$h|)QpM|0ABf8kgpuk%5JhSh zf=r}#M-WHqTm;!j-GCs8)FTLTAW}wdS_YKOsM`=E8TBNBTt>ZxAfHk9p-3U4 zo<~s3sO~qSzE}-IAhDW)K*efX1UgpxBJg8%Jc1xr7b6H`bt{4>R!<w+lsE}3j5EQfOAq*<6 z(T%ZANTTK

    EWEKqu-{1b(8HBM1_8H-a!x&mf2r^$vneqP|8DCu(=B8rei0i6BYT zFA?Mtbv=T7q8>(2NYu*+iivs>3j`K}gRwG5PQ3-Ba_S2NI;UbJ`Z?7PL6B495rjE4 z9YK^+yCBHq)c&}b=#k~3!3j~(85*7$4sC5vig6c$|3u-n3zo7O&5ERts7|pPtjsl7b z>Rbewg1P}gTu_H&)yNjq*$9$?x)wpMpdLh!FQ^w06bkBZ2#N)-?(F5zwzc$~fgK$0 zNb8)q2NJfIo=adzeQ7Bw>8RcY@jlBi!+hLUy>Q*#w?b`?pe`>n-z*q&euX$p4)4H> zGm-Ocq&}Q>vq@3mE;gdW7ch13&kqaGh<`!2J31Tx!tfx>M*NGyZ%;LmOn9h`#Nk6W zk`2$nN{oL=SYs>Ag{9>tB^MrvYaRdc;mfp*k!D+_5U!x*XnA<8O(}*eId!pp4O>n# zk*aVAZ|!)g8}5mf4*zPx4XsqS@DOW!x9~iS6aLkPXWEq7@b9=r@vnP$jZNtu7BE-w zuP!_Y%OU>NhmTsR9^p&2(jMW$HZ-clh9?CZ$g}2MY=Q^$8c*NZ+u^8rCn| z3D+S0_4OL>UyjZXSDt~9X!!Jd^xY?Qizx)`eg6<>-11za;pwFEf0v_F@F}_rSDpjlK-=s^8;h#H$#C@Vi2z2PNae zAFkaRvu*nakQPbxa{yla!Q((hseTv8kDo!0gxzgkCVq*iuT%>v%*8&sEnG*c2LhGi z3r`0cA=OiWy2W>48iXx2uRcDAW~^)TddJ;ZawDl;fRYXI2b`cYrTS!`f$=ZVyWt$0 zHzfWg^XA#SVetvef%dU^qr9F6MA#L>$m&P=quDOI>E%&IkA)-bpn_HoPnO<#En#(5ITy9vapJg5V@oG0p ziyYUr2%%TYGPQdlT6YF!P`FUuV{=YNLgR^Cm!i=t5O3hfMPsei4ZCsO8duE>4FA&z zM%F)t$rFv&mjbNw4LUQLEWIuQ81*WC;$6Dc+>eUBN8D`kK@j)};=P{7^?6VOlLwQy zxuf^CFq`{%Z!npjJBO8V@39!?xJKvqM^f(Z7+8R|r_q1Oq?-Y1b%9-)_{#yhTQE8~ z68hr-x~J)FuXk^ZdHj{iUkDw2Ir#y`ayW7eFrxt`n}WSJpps`){!7-i8WR~{1NLjK zg*nfv4cKkDaRh&G;HB>Xo>LoeT#^o|dqG)~HpMCuzofcRn^#K;ir(AOkegIEVmqk0 zg^jsMjpiImZpGCf->JHxOT46s72Kt|v6xrO%c@6rXkM&1Bk!T?KUvXYwH{}tZP8-2 zooP{TTzAM>XzV%UU4TPXU&xCa#;=yWc(o;_Ri8`6FszY^Ir6>O zInrYiwBKg5-%!?mn{=+#e!FxU?H_Z`eus3Lt~Cw0(}Lt=4)WbjyXoiOI53D7-Q&Pc zoIm$EV9a~KnP+D0iqxV9FT&pg8H+l1NZWguj9c5!hskE9pFceb3J;TA*G{`5ox&Bg z^#rjqEk`3xbimBClf=%ntIkKxDK6(yR2!e_fU)SJ)S~@yRn0OM-C4G1mW*H9N3&$Q z=_7M#&ytqX)B%`EJ76KemoJC~MTpCbBMci#EE z{$Jo`u!0JoP8F^&7WLy|wPGfhDx>8oqs8lg1**J`;eclqz=Phx4-ZISREq{H!3(-9CotNe1?;=8!mp5|Hmy38*&jDxzdxkj6eTIX9#KCC=~-;q zaWi2Fvf=B|J;pNiKBls+!pa7uj_Wa*sn0X@P5ji6>OLY%yys89J;JZyy7vv&y>Gbg z{dabOpuZG165lsm_rBq}_j~V5QNwlb8?JlbaNYZc>)tn9_rBq}_YK#*Z@BJ#!*%Z) zu6y5b-TQ{?-mk$m-OcBAv(`6U_rBq}_YK#*fBR0j|M-UM-e1aD<{Pei-*DagTR^s- zZ@BJ#!*%Z)u6y5b-TQ{?-Y-qZ3rpW{-TRLqzQ8wJ_x`SPJnwhD;kx$?*S&AJ?tQ~` z?;Earv0V3Jx$ebs-Agxg$Vd^(buX)6!dW7g>s~C^y;!b$v0V3Jx$fno&B%2xmg`Nk zbuX6dUS7uVy%mV%x);lJFP7_GEZ4nQu6yy(hUX(W4d%WOiRHQ%%XKf7>s~C^y?lpi zUx~zW-OHw!Vy{KgIFnrWV!7_+d6;x>B9`l3EZ4nQu6wau_hPy3WhL(6R~E%`-HYYA z7t3`omg`s~C^y&Q+7@aQ_RT=!zR?!|K5i{-i(%XKf7 z>s~C^y;!b$v0V4^2DY~|e=C;jUM$zWJcZrxE-S@y-HYYA7t3`omg`; zrO@-_x>qUJz4`!+JCG@VLJu6oNXm7u1ie76dzEtCt1%ejgPD?Y-K%|3hFte5<+@iX z*S$))?p4ZluTrjim2%yyJ<)wjD4ufNtCZ_rrCj$a<+@iHj2OA@Rmyd*oqUJ zy-K<6Rmyd*Qm%WIa^0(x>t6LiZ;qUJy-K<6Rmyd*-oY+`T=!}Qh7HW3o=Umy)nTZM zT=y#Fx>qUJy}ALtL9Tn1a^0(x>t3Z?_bTPOS1H%MO1bV;%5|^)jN26MLY_*w?p4Zl zugYBa-N|+DA1e9-6s?o~xPMDuM1#RK8Q3np@Zr0-VIRz`BDp&bDo(4yB~_eSgDF+q zGKUMQ_ybZ7Er_ zax~QIUQbg_vu)_-7s8k1N;Rgb>npGOYdxU*eeqYJWBVPV!ms5_HtPp$ z9K&y=`mYf7!Y!~j3%|1l_~9q(0DW&!Cj60k|FkIAXA7Kf@Pp96QlIq^|Ix&|g%7io zr>ZZ5^7@dD8Tb%q8ZoX{K-!{VAvq!NiOG~46;7sHV9~g6A>~4g+QQi^ z8CldB4r9rTs=gQXO$vJs0g9Dr&Bh_m*T!c7gEkEZvSgyFUqs27;a{1TQ`M`0b`D#J z^0wq5eb(P{Hr`vaM~(j9=IljN&-QlOvu6y(6~v2WaEh^v3}=%EDm?<1My?b-s^ecE zH+&5+{H?YZUO4?ppvNup`)oaVQ*VXlOwWWz--etgw3$&kulufCl%CXj9CQrthAyb; zTg4iU)t9E#Dla($@hlU}kLjHU(`;PVHzRH?_CKbHk(YgpiR`iu)5JP2c@^<26HJa^ z6*DdE>m{EvhY2R9SDI76S181@Ovp(THO4z4rf1AUL3n#{@xU1@SL_CuIOyvqn47l{ z-s@GRNH+#cAQ#VDfO|?~9gUA4M5#h!!gMbhgx|C9-tgcab6Su_}`u~h1m8(2}BgGH}OMFY@&G%j9=oI#ECPq6)i zp|ZU(VZX5bQ_%hr+P^b(O>OMOGHCxUgc~?0`eIhRp@T~A&6+lHQ0o&2H+In1zoqOn zXGf?HV(xSYBR!vRQwKBppgjO*I2h~8D7%@1S-k<_<_;$MX~LNf=5#x)n&n_#@4%kj z!a>vibI~XjxEuC^b6a+BifJ6jsA+NcWUhQd)xkh5bo@t=rd^aE)FVv z1}omxL9Hhd&U4V$O@s>^4E1M}-Oa&Be@4x_JDAZMafJ79FxJ1O?4Ay0^^26<%fUp? zW$xY%=Jc;AyN`o;y%`Jd>!4}>c4$8u7cWG??HlXZw)h&v_e1;9FWAdPhcw1dVjrkS zvhxmW?9Igq9m98N?(m}2J5FX{AuLlzz?O>os6E1Nu)EiLqF%Cw$ zgSp2#n9;|xg~vG<>&IC5cn7okS;7+>O!S_FCpwtZuMwW)U|zpVc(Q{9y_)b82aEcj z9EMXJEa~~I_cRBq^xL#*se{$}Fcv=D!5V!y=j<5{cGEvl_ACdx>)wQCJ6NadS?@Ux z*6Xb}X1{c>hdzuIo$FvveJKl{=U^|rJ1aWh!QT1`YQDh1KKgFTUgTh3J(9W09ON!I zTGVKcD~`t^XK`aahc@04LchZBV_IQ=PlxyE|lK;w@f^IBuVbT48> zO^BHrQ$*EoH^w_7L7zvv-sz(H{ZzHSp1t>>gZ18sB@(^a7#z>4=0N?Q8|%+yd^X~L zYfLUe+}^>NYO31F%d&LDy02fG*l&rCH#I+W$J;pGh`sPU?s7_vH8pkEN>}ra3GXPL z9u@U#thtNGKAuDkjWt{glzkqF8XIedL&TSA-U=JUY$~G;Td2R72al+;vF1wj$Uqdr z(lJWR{xI6w78)Y~9n+(28f&gYp>ZgL2{uUrx~4}5*g{hzpbvUNkG^0=;p?nzoQw~Ni`?WBNEUBJ$k^}|EL7?JC7c;3LlezF6YrhjWrEu?Bi0+ zNrFu=UC*PZZ6TagORw|j_l-3n3gNkclVOPp=y4vs(OB~d3|_9PIgWVFj<`)Kz&z9Q z9bUrz%`(B{3`uiBd?-Xb%LJ1%CC%yXC1aSwgzj5#Vtm}FIc#pHigk#Tch5&ZE3podVjUu7&;|H>pu{>vigkz->kui{AyTYEq&$mW)>^DXq`V6h zX!!;~sKq)&igkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-TNU;u) zVjUvIIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQvBW}Q=nGx#{Db^uUtV5(& zhe)vwkzySp#X3Zab%+$}5GmFnQmjLyyak>4j97pHigkz->kui{AyTYEq*#YYu?~@99U{d#M9O|QVO@*GIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv z)*(`?L!?-TNU;u)VjUvIIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY z6zdQv)*(`?L!?-TNU;u)VjUvIIz)dI#I6bO4zrxah%SNS6k1BO~RH@UWN}V26>h!2mr$?1KJ*w2{QKe3gDs_5P zsnerMogP){^r%X(6aV1MdcBF{RqFJpQm03iIz6h?=~1Olk1BO~RH@UWN}V26>h!2m zr$?1KJ*w2{QKe3gDs_5PsnerMogP){^r%v&N40RdF}0^kogP){^r%v&N0mA~s?_OG zm7N~z`rld}j%PX=FdQ%328I48{QCYGCLaG9BjV3OyyUMzyusfEzmxp+Zoyti_Jaa! z{{|rmf8Oxf%?NT*yxjzMQobZpS)@TOL3wQcE@R0_@&gl>sArkz3G(k>j*aZfT^jJs zn%%ch0-Z18HTporlS}Y3n$DN;cZK?2Gv#jl)L+jZ?ynl?)|Vaq8E}v7A3$_$ zwK1m$z524_s+j@3YY>bn(5o*yUOx?hKi}Y=A=Ts7>P4)zZzKAJ@5FsL4kO;UF4~_A z>BscOGtm0n_+G5FaUFD4uD#z^h>vYW=j1M{c@tveKJcM+-TVTSuc212KV4xq7djps z&&2y7QN!-3S%H|>pH4_KP4<;tv)L}MKix|g-;-cXckG%Ge;rvpcbgB0 z&nV107Z%|>o27^s@Ueq=MX6$5&;9p1h#!iW)vFg9RFr{M=tH2`Dr|K^u@srt>vOg? zmL7Wpczr*3oO8(3yoD?1+k#%VP0?Rp?}^mfJr6v<`zFutQeL+|VWR#0=rr{Um--KA zegC{P^#hl>3TC`{W19MwOFaa7UwJf5ebuGz1r5J@HBEimrQU_I53EX4AGE3CpG9i! zYU39&;0?qtAGjDbU1*vycmSMecKyX}UhcyFpEV%9&w_msA8I;g;PL3qb47>0xpM~Fa;HP-IE zWcOMZN|7*z30_+U(qSRnJvR_pf=&S#OI5v2pkN_8#grR#Jy2#&EYr-7$?*ROoQnpb1^Wa{`2_zn^SpgCtOD;JplDt- zGX|qBJr?EWH4w&}EAxgOhp67>ex$bTk7(w=`QC1k(VTxb0jubaM%Kvf*jSd^aV#w` zayza^IefIm!!vvJ(B4?fOs`&mX~JH81-;s6dnB}-i$6!21#3dvxuNacjO*NOpsa2( zet2#Uw(X{yGxU~{(LEM1b1pOa6WY$ttZYE$xE@>(>JDeR9gWbA2GA2sv|Zodhf4Ol z@tGa<5_04()%;x#5APzQyQ6<)Cp-fG=w-I-1~6V>UfJU98iMjte-^(06HsKKDZUNf z4QN|ras!LhKpv-iAX8+wg6A#qGG`%4ZK$ZhRK3$(EZBM%i|qazR(d;rwZusA<#=>n zAg>}Nl=^!xkg^!R8CiKJSGeu)o0Y@wz``zPp-fT6Bex`1BE3-_KzgGL$8Uf6Epi9Q z0HhC;S~ke;amIm z7Kr~aX3~xpDE|o9Jl6v44}+$iEb#r_06SX{_+O*aT`UOwmyxrp1(AOs44h{{#_Mwp z%FP#=RZT1EWq;A9AkyQ98cZ}X*7Vq{2p<6xS3Q1@OZgxZ$1O72Q{um-#_w&FTI2Vz zK>QCdE%&uR`G-O2FC^F=BHI5`H~1DvjF_9`!%3cmPIqG&}({|p4|}dru_Z&Hi*>zvjLSI zP+*-!uQmg1{()KMND-rNR)=cBZaIJN_*z8bkD%9Im}A_FUxQA6Uu$yT(MZCVU|fX$ zFN{T*I6;&A#Rg=(EIThVy$(r7>UmTu!JzmPL~5^l6jN?+w;3oPUTyvXpdl7XZGuJx zO%^FH^ESpiXjb6QI}gVaSd$v4c@?G-F=3`e0amD$2!QQ`hhe zTjcfq8ov^E?~A0d2@9&&qw;YE=y(o6i)~!I4D%vrH6Vn zUTy*|6aO}&e_^U0e_96t|9m5GL7KX@R-@I-EpMG8(c955Q!@7q<4q=hZ(5Dl{T`%V zDA~hd?RQ8m90W9qv53_Bf&67zS zA#2e*nMET8AGlzVm)YG`;&q<^4b!cL$E}9x(qfD;)o&@)`$5Q6zinE5_m5!dBrzTI zofVrT9j4+5=%maf*@$&Hu?mdV; zPGd?B8D%C)=_D46Y{4CDLA-x8N|H;_oHfR*KOm>-ATP6K7;_Y_r8VO?FV!)SUo*u- zxrD6Q%tQ}E>Q@aMKy@yoqgk2awe!`6oPdhg)K}XuHMk4~zAgT`d+t z^=D+gxY7CObyfQ)qT88E_3u#g;zA?)b}!F+xte8rapU=lxk$b2Z0H*D87Ipl;bJQK z7K$F}e`2chkxh-xhfv~?os4PMv%mpVA5iCGMrW`m+WA`(%?Dg8epgG)_`<=0)Yg14 zB5(p?CCMzz+lx$hb;mtjebfjz&O|jTx@g)u1P|GVIcRN`x`w7;cqz2ZXWbE0L_H2w9W+yx*2HaMAObKAz}JqJ$rXZ_Q9BpFj)s6D{n?& zjJxXkJ&(Tg?=^FDDRQfJ0~%nK_I}qk;y!cH2u`Tmm~{xyWFk1{#~00D%q!gwOR>2d zPAi^AsfZnhgbld3c%}1UmKtfZKP_jER2$mtgV9N9h#Jr4^upfPN)J(+F}wI7Y*Wq3 z%vd~=@KP-)W6uPZ<%~qaT+T_a^cU=_@F)7lknNaVFD79sE%S!@csfv?8pVyJ&GMAZ z@*YNMZn{6lCDFrdy8n8w-E?of6|OnE+s@eCcE;|uGj_L~cf0NBsG({CelqTlB-}=O z4b}xEyBeZaZUl+db`0ABj&OFYlgxcy(s%2E3PF zi=JhD+=W-G{q_5R-MI-mpuozC;1t0Ec3_t2*aCsWf)7a5xxMjcJD8rlD=o}13b!cq z^S(Js`Mn>*FC5*l_4!3DM>vyk=d;+vv!3~@jXXC#`bf=(r0U$!@h_-vAYKX{V{~}Q z?;1SsSQA$XKkXftrLBH)66B6I@r;*$4FdWE-3j47k+28-_2gGTb>r>>sGAS#LEyCx z0)L7=1{r;C#ZTBTrn09Ht-<8+YMy26a>TsC9}%r(PQTK!S`_uiV%-qT=+Ga+s9I4C zWuZT%4FDt=>~&+NW*cJ{Kj;;#9WMS5da1jMH)2xM*|=92g<1-1c+dUCm@6?$z=PuO^F9v*L>a_Ow;FD}lS-nMbC^jtj%!}Y^X|F883)2Mwt|JQl~ zhs-Nog-4@{GqUBGTH+$zVM>JGqeqX>A*VtX>m7?7p_`4NW}|$B9>Y8@{03Gm zum#s~1sCXkEC~NuShcM-H={W&Z(H4AlpLPHL+-YEI{RK=+O~R*t(Y6bsaA$Aw5)il z9<)|wsve)pOx07ZOb6=eX>EAR$@H`~C{s^QJ(4mxF7*YAe@n^wmpN<~}F$lCp*xnU_@A z(3jMDR%QiSaF;diQzvtmGtS7|Rbkxy&bZPQsOVA^2DURURc1!PD;E8Jq1Dyj++6LW~O`L5~$n9%FS_k`&b*i@Lc50v3ZMK-W=uT6ZhmBTb<{)yp7cW z_K_D)fSkXMGRx*mE^{3i%B3n-n`8yD2vv3mek76EQvfyRC8WLxRTLEw*`PQr<1)=G`rDTS4>8)9Bq|CX3>F z1&Q6(ntit%OS8?Ia*s2W>&TNf?!|Aj&Pyf#K9o(y{+D%LD(jdIF?C)lqu8akqDuvC z*#M@ZO9ej7PWSQ(-8ZGWujPfbRLp!o*y&#C+GFfqDs9wY*4Z;ssYhwiF;?nINGbCS zevI^DQQ33;A{A(jG;3%$|W}=+p zt9Ii!`x~I>r^X2X6%_c)MxR0S@20i>j);C?qvr9&-0QRYVi;T})l`QiYoXU$%*G|F zUx31X(vKGD(@{^O)J#Aj{RH$36thv$J0g9M)S6ub?th0PzjzPiKJ2!aYsiP@Mr#`K z;TY490~hS$`5)S~y?8hZUyyI&Mi8yOU~Q`}7|V;1t-fFb(^M|v7tAWR`htb!R$sKX z)fcaA^{>{p`jWM+UT$0MuSUJUHH~gyqy49Bqy4dH-0ug`9-nP~)->5?lb<&&_Io1w zLb<_9*x;eib#}MyT^r6`+u*a?OdCvt&o%?*6*qzWq50pSu<4US&AlSvfE+rROGw1$ zJpa(yY^cv6IJ}M{;O~#g z*Ga|_qkC7Ydvg??-^a9+x_4izd%p_Z2Rhx2=GDklbJv@L3OHI*8@N^kysu1c;?M@X zUZt;=TER$b-N^$zfyCt0YLwc#=f#XyZ0AdMJ3q?LJc*pqsF3^l!ZrYUlzhqHFOUR9HfDur z^Il!s_v#7XtLyRVIb>Ub$}Y^Yt)o#bv7H80M!d2z1I zi*s#WoNM#qT$>l?+PpZ|=Eb=-FV3}jajwmab8TLnYxCk zAbp@VFV3}jajxx)^W=huVZ&jH^R}Ay*k&9l{V~z>#U-|T7#;53tY&rqBiuP`VZ=X`%PRt61nR zWH;y-Iwm>kPvtpgoCotg{UDw=Mc2SUr9XtpT8C&ZJ~_VzIlV?vhwYQE_g9Me|L4q#dLHgS7Aisho)wH4~zk}?A zNN@WcBtID=p}gMqONd3PxBV7kk?-~7*O1?&O-R3nm?orOLxRe$A*OfmHDoA6bWr&< zB0Ag9VY-_cfHeQJ$m)thf(*V>?9ZxKb6-TOUYpI&kmL z8gZYOBJ%^U_ocX`Ke9*#y~A$e{mml$#m^Yg?~A?_LQNi~*-DA1uxTLH^-sifDH{5o z#9tz{A9Z`dNL;(0+6g4VF?cZlES-)WSOq?}zz-&&@ZT*6y}pNIN&G@sPc>B~m*IN$ z2bM~>oHDieX=uQYJOcf28xKart$^k;Q;>dUO8A*67_C?^;b*2`Y`@JB&#-8+>UJb- z({p{qt5mqZJ`s@`-sr;gGgA%kb>V?o=HMMm$-ZN$%7uH!FCfW$VG0-K7`I=TLidHK z-_A&~UzozmFHB+jg(<^+PWYlFJW})ZeN`zqEDo?n#5-e|3698?5ckX{n}q1V^KTlEjXUOR;b=y;FQE(e`q8Z5dM1C0 zH9DGI;;j+M8BB&Zn9LW@(VP<73GN~YMcW%71G#O9b}#}y1$GWdz8-&!NgVA`;P86! zNnG-G%|C*;?~Tnwo9IcfuklDEZx*pl;||(yH~ei-NXr^~;zqD_Z%&fN$I;XsLmJk| zC*XM@jq%3Avwv#5H&n#@>=tckue^8y*34)l1Ee3V@V%Dr&>hhNQ=eZ=kt)dyif==t zh9Cbj>Bqkse*DX%AOC9j@h?;U_?PhGU#3|dN%{JCWLyio;sY=RtBm;ui0jhqJ7Z*y$o8NkWa z=#IEUKZq7rU&(|YX!(>9n_*^Sc5L_};yS=U|A=1Aw(8NCVl^v(v+dpOC)JwE(L31* z7D>%$=*V_hq-ri?$%$r(!EN=&$AQ+h$gjDMCD*ek@Txkph788>6zWx*_>vVAuUM|WOo*o zoO2ch5m2%O0Toab72%^`L=31PCPYy|5fxDZ5d{OHs2EUCK}AK(g6VnRsypj?e&=_d z=bz_1|9m-z-hNfpy>;tWb#+bmov9|swQobM|KNw7SznlR0X^M!N2a#-MXT}6(3S!> zt_LkVPpCm#P&|_g>HxxzAUpVCHjfg$q}Kz4&#cfkjG=H_=nihy`KysyYl!H97Im-= z4c;1fp(anyR?*dHPw?TuyEVzI*NRSn^McO=zWr}<`0fHEuMeq0}hkUk7Xz7^u$3-cSK&;Xr((SP&9-PyoZI_sty z{n{O2etQ<`uCvy1mUb6rIW%iFZfU_q0sfk@wjBc)ACm$P>f6W%oT}TwXIAJF9IG0P z#UQz=^a##F1Cbg&2KMJf8zqvaQ+AtUbF@I|I-5X)A?3|vv3K_OR$y(BVNFZ zf-F9b>KBW>0wcJbKGaMM#=6jGfsHs-k5GNk`ArUEgw~@roV9_k{M6NaIV33%=4Yvahjk~66#HVfl4F8b?Q(55tNn=fZ>s|^qaeE+}}(~Yx>TLj)rR@XNK#i^Q>fZ z^iE`0ILuG^1Ix6{oj8|UimNRFBNqgQ)Rd2g_)d3OV0=wVcq;1j+L!QTGmlgC$|l^C zAYR8qYplCDl}`xTEP50NE1E)L@W#O7oTs}jnpp=aO9NZ~O?d>yoocc%glMO0&4$ zyqq*iS4a}V-?+q;f>vk|%H>=IS54EEuc@hgnw!*>^U5VW&26dSk1ZNHk7Vt4)M%gi zU+uHf+6$*+z>ISPyKA(La}%tnAr?L1ac&bmtO`Fy+XuUW1ePR9uQ)&5n@Ke$a9ITN~)^1U*|4LOYX`v!Kybf6y@lU4{UD7DlS);H#aw`U`5R-|5sE0y~{rL*R{C zmAq-rb-+b)W2zHwEKkz1A1a zNxNsgxJO^@>z$5#wFm#IY3oz}ZR2Sc!M;cv^L33ei)5s5JWY6!Q_c5I=QC&m^x%=_tl_E_ zIm0!SLIq%&?!_lf&U}VIWTJJA!`n1j0UcBmUhE`w%ic#_rWdc1Zj)ZTKHZCmPdM=c zo)J3%8w)8X`$yDqiBn+aj5cUb$|)GeIl4J1r>zFv(3I1Yiv_zQ8x{ zX%}rHKrU{V;oY{rT!PzCv1-m^M{m>4X?BHfr~ZgA%}z0>-CI#~hFzbFDLo|S+S#mCagbH`5(7bgK54pirk%bp zGg*c}CP1vq7Wk_`AB6Yt(+K(!SXIMOg;3Qq_cNI6aU4tZT-#<#n%NhHWU6(x^Pyz0h zJX;6bL&5K?K;NYs+NStc?#K#(9a{j61awz5Gm3)m*3{fYdMEf5Cu#dmv-7ll(u7fV zj%kAMcss*z?m_N~QKl<8)O5ut)tLL((G`wTec5tn3ST;-)P;IoTzDU>{Ez~BSmshT z@ye|tftU_Of(IZ{-7#mSE%&x zl7#-!!w9;01HxO(y1HpUjN(o7YfW=Dk-l$PO&6mHYpEK&YKGieYNW?9hV^5VWrnqG z^E#?ydP{fhdi-_))?fTDhogBf(~J3~HEJ%S0+tOKIA(Z`X+d5`+yJJ@`B0oskn`=BZAZy@GqiHJoR@9I11mY-it+>G{6duPO&LGK zy5eVX9{!~Xx2pvAq|D7AyXrPH`}H~e^l}asYNlz6JL}}!@o0TUCh35|R>*D0FCdZ7SAViDZVUfq+^E-F z{aN-w%^gRgBCEI?%*ePwXHKcfyuoDVa?B%Myy@H}$aOg85eZ$i;#`h-v?b>8k(zA8 zJeq8dd9)Gp$ajnPYqAmZ$k~cx9&N-t>N`{}2Q^~DAzjn2T$Y0xk2DIX9ExRxc_ZqWH=_6zxdE)fyb*QG8_|Hg z5#^~f%GEjMWoSTNhEC%2GdbP72Mru4$H%)<3a>;`(FL4t-h(>kJtzqETLF3Zc_SA{ zhcaeA%p|WqxjwtYdwl%=eUTZE7n#o>TSwH`-$!8i|IO>PfV@uo3{oXQ(ly|{S$mfJ z|M%W3hhKbLfD)O<>hOz?4v=-NO!MA@LAjacwFd(Qty2Bg;}*jGP~Lj5{@mJcJ#zT1 z$6ll+Sg{p0Z#_D&eAvA7V1KHxdFP>h8#b>z_&i{h@f#2OC$hPgC@aFQWgOKRWF6&) zk>D%&jBOqVFj~Qb$O!(3Lx3N-Ivry%By0D%71cPkzr#WeZzFM>Z`H|hn|YTbHN-cF z=0#kM72*#iCr7@+c__32w)^wveW5RF-ZT>!VzX7%o)D3mH= zoyiW6dJrddc>uJt>V3k+PR+g*NlsoSnz!LqoEqb~td%zo!YlUIB(b3C2l63 z(8F&Ja*b+<8n!FUO5-~7!=TO-I%JCCN4Fr5&yTt8{DSM|PI2!%UArNlA7(8(fn;yobjw}V zfqic^;3rz{4S_6vt~QDFPj}KrPb$+!YbBGqvJ%BT>rNWN9`yLli#ur?x7i;6A#K-% z#x8$MI^hyynz4Gm*cthQd-9AZ*LPn{eP=Y_`rMVsJ2O6(PkCuH+~-s)i=P(uWPx2Z z0zK<+mT6_r?z)wc`EZomF^3EOT~n}Q^M4C=9Lfc?>MmJ*SaoD|9gNgF^wuJEU9@aA zr~|jln}f4Hx>qBspg1(65iGLKLm`#l>WNOj0t)e zHB8UHJX=-hso6@;zrSKE^Za{J1I#&k{vEl~%)fVH{w+20uWROC*UZ1JnSb5?#+LJJ zmC0>&&HNj!HUDOEJKX<Sgo-ZW>F5sX0s%!Py2BKDjgE1l&v#+gq)E8> zlQ{Bs>}?0C{WZ{XbHh=%;hfBQ`i4U~P=j=!2AM#O7>7x$MhRuUF4_TBTFQJ|l+Q_- zAPGKK%EUaiqw56nq-m zvlK-4Nen>D+eO|~zNWaruWK>W;5UrE0=7e`dr|jCdLFh_bDV#y&s~*=^ZoifXyx`p zCw!vo%Vd=?zI#8;&8U6%_G;g~z5m?3^AFK(6wi`d_ho!u`_>)fTX!aAp90p32O0Ss zu)sbfRqNKRYTde3?OS)Q30B}bGFc7w8RZ*ym^Fl-fNR1zr8l51Kyz^(q+L7%(t1dF^b*p;c*f5IzK_jT7>oL6^ufeQVQo== z6e1dkGKx;;lC%LwY^#6@@GWd83easR8KmsjS@mrw@6qL~nj9Q`ilTgkPRDtamf<{u zcH)?6MSsH|d$fH371s$MT!Fu?8CuJUlg+&(w20w+pED@*DKywqbdD2xms>eigKHJC z!&jqF5idZL6@3}T+0$%}P)YW7oR(h0094O{HphH>)~Y-D{8^UMS}ULs|7?R(mB}7e zA^vRcq+;v?JG2G$IBh~@$Zpw+nu7+9tRf+&;8D9BrcQ zX=l~Hkh9y_PeP>=_#M!(IcMix1?}Afqi||-6RfInt-#i(Z*F0}55_at z^=-p^JGiH&q?V5tK%v_wp9{ZSlckk#G=NrT~d!utV6MddXd$b-Tx{Ta_3qZpX~sxGWy@C(Z7oH*QlMpO>PJFgnkZ! zqT{);Y`-2G_8?_(ZN9ExHDz!GQ2HC!H_s@o2;rO;f=H;PbRN}GI`2P9udJ;UKYnkN zHmuK=-&hKCVuiYSV@a=?tYUrx_>OkpRmhBRZSUx3kr8gdJNijvgnjkSNMrm~HohSh zjn(!R^Bcm4!rT|9c_RN%9d2`k;H-zbad=vUzkd4ASzIV^`Buw%R47v1vx_?C13i-JNiRQ zP8+tnD-H-R;@?O~|9Hm~&OC!N`GDU;ZNiyH$}#Vm?-Yh-ak^RjA$khVvKpG@CK54j ztW2{J(sG=tUQ=*!klqN1^hQXeH$tM%M&l}`C2*%hdLty#8zE82D4xIdMo7e=2p$c? zF-&?RB+?rpQ8nz3(v!V;{?;2Ik=_W2^hQYZFwBmV-Ux~GMo6SLLZZffF{zQ>2#NGY zNTfGHqBcD+Inoliu9);jNTfGHBE1n3>5Y&`Z-hjXpdm?mBP7xrA(7q)iS$NDw51om z+D3XKB+?rp(G+OjMS3G7nuJ!oPI@CG3J$icH&7D*$7FQjgXYt2uYcZkkoaM`^HvgBP3-uLQ?IJc+^&ABP8`D zI_8+I%tlDcY=orxp@u%#mK*i;b(Gl%Ntun1)X%7PfTNnB>jygOQj{FzsIPnC4Yi}p zMo7wRgrv+yNXl%4q*lVGXFAGkgrv+yNXl%4q|8Q0%4~$B%tlD+Ea;r=Dzg!iG8-W& zvk{Uq8zCvP5t1?+At|#Fk}?}1DYFrha?pmif@(3$-4j%G`(fo8RAwV2Wi~=mSDuY^ zYEb6f&sQ%FLO@QwG8-YOA7J&&eANqWn3b>0 zMo7wRgrv+yNXl%4q|8Q0%4~$B%tlCxQ2V9%sw*zvdHKq0gru$-$r~Xlvk{Uq8zCvP z5t7OuV_6;UQaNW~y>XYSI|AVXcPX zyb+Rp1?;+rPtqG9+3Agt?5QZj8zI?wFl8>Eq&GscUl{^ta7ub3Bzp*^pvyQVy%Ca~ z-U!K_h_OCDg{<^ONOpQ7BzqP#U&UGJjgaj0Mo9K<)Xp0r+3Agt?DjDArgM;z-U!Kl zYdEF{PDyWsWT!VmveO$O+3Agt?2FM6n3pX(y%Ca~-U!J~Z-iuTMismflAXk8#tp}^ z(;Fe#>5Y)=S8xf2I4ivolAYcN$xd&CWT!VmveO$O+3Agt?9bpj-U!J~Z-iv0H$t-K zV%YLVNcJ!c+-yEcZ-it&3~%s8NOpQ7Bs;wklAYcN$v%X81fE=5c6uWudlrU-%PHxN zknHqENOo)V7t~pHCtMaNVc9hsA?5N$ND3Pvt%AQYPr;fYsHWi5ZgG%frfyouZhU7p z4)p2yC`muz+@`=BzOfbJ=u%T01JnRgL8`_vL@!;zH@4q!3{yMg`ZNf~2#v=vN|)f6 zK{w!-N%!Fxqx~0J_@Tt7r&;*Y-0n$y6IysR9&wU4pJUBBLQj3lLA?#=#u>O7)38|x zho^C{tub{#$tLvN<(Acq4qn1PD&w^i%0h98aV2D=qxE$|;cT zKz(rRNPE%fPV_SLbf!;m>_TtPwXCl6%L2>lMn7DH&keKa#v4kh+{7rJDJ}k z^_z-mpC;hgm*&Ire)K9l(4P+CIDr0vB?IZzOZn>@@57$K)CY^!A#^>o4W$jJp!m2OLLG@GAaIt5O_CQY#$Kp&mGnqH}N@O&8)ghQ>h8xzq~f&!b)!^Nsmb zSUZj?;IZ*^0Ou3vS=cj?cA@+vItevSrZdo%^GU(-DU@2oKR)FmWhVUtsaf{qXa}MAP|~r_O_a=Fk^t%UlYhu1n~9Xr4!J!Sc)KR_MQ++Q6RqG#h%Zq**w> zicTPX0kws;tLa*3xR&mP{>8KewO>a&VEJ;Ijq^L{dRTiGeFOijpm$);O5zR3@1auE z^$7idv9XrcpD=)r)U>!-bi6+ewyOY`3xeL0h)bNE~0Hi*ejeH{$p*{QwO+=uFuB3avrPtJDy+@1*WH?xKFs z^BPUS@pZZa$2Vv>j&IUIjECK{3?uC=T7y>Xp?7EU)1F^(e1~RZjP0c}asDpdgY)<3 zSsdS|g|KrUO@!tTs4nXLh&to=F};Qs?WZqr{Dl6(@l(o!KMznF`1T-G!v4?b3V8Ah z%0ccSnv2nOn3m%BCACJ%SJW5Bujy`RK0@!pli$!1Xuvl|FiO9plW;t$zc%ADh%%{K4Co2ca0xayFp9@FQa< z!+rRnje+>%k(zfIPax`6{P9UWjz1AB4>9WSYokA7aAc5LgHe`AssedgqUp>&pVWIWsen`-24H_uUt)ZYB2|DcAC3L8kT-@@WBfUn z)T_{W9<0_EnaYOM<4^-=JgKkY^$Da1;uFzKjKWEz?$wu?`Ui>ANDYH)=8>9)KbN5f zTsW7L>V%T>K^SOPkeYzDUx|jnaaWOQ29p+$+63{dNgaky7h>5As~3?vgxdc{DjQvL z4XL|f;1W_lp$o1fWx$y-UahO*m9 zU4q*0ATZG@J4Nu7W#_mesa z^Z=>jF!w=H*TUS@uoH<7k*b0b50knDMm$1l9jsnUsy&9=qok6s^D*=vj97;syM*fX zq*h?KK7pYDxhF|2fU`D`@?peA3-EBNy~sr~r# z0^EZ?FG2uAdJC!7Q0-O>8_+g95XPUEAdZG@C-oaf*30M>4D21G5~%MLQd3~WtE4{0 zNZv`R3mmcwiD>j|q*}n1*GYW~pS?lqZM6MOQfES7Hz@^ri`2!i>;qC6=>8AUD{#R_ z_*J_du-+a<_S_(bdjyk+(;}B|x8b8WWKxnZi3Bbkx8a~n9?`{E+Q#*6gz?*uIWw+z zBaG|a2;+kzn6Tq|H^TVt98Aw~y&GZtL>&ydxY>;`B)bv*1N}agITu2$H)v=F{32#o z)Pv^_8O6?0Bo_C^tCf6CEAD;H7^|-1pMzA$GTE)-ftPk;2CSpq6!;pN!b!g_ z(qUFsGBb-^JJ`xGLgWn`WaXQ4E&oloutpkpwf!u6t1*mC#$hmVO!4Au&PPAwO*%Q=r)t(IF}*oB*}vI zddcfpJHe3+MEh~n)I8~Ptd6YDA=a*n@)SPCKK>;s)<$ab8O z@8fs1BoEcKO#aE$1yS88Qr)L}EURtOXERV;m*m(u8q>F{)lFNh@IVe#cNc#srx~b+ zD72kYDC#NXIE1$K5^|k$a0T=h3OM6na$g}B(jj>@>Ip<4-$@La3(ftKJ{t%_h9>_) z0cSMChKZQvypG~$3XwDU4XoXSl=BSQJzU6kHo}P`gd8-di*>f?U)MPoy*E;_0?s1P zIYO{&V6rqDcGZ6y%SEwkDjYN_>9f7CYkZPl2sx+1*oh)$Ik$o)36b*!XtI!U7Q(Lc zg>2^<*fmwibv}i|rVF9+bCb)t^5JOnSgE`fbX}12*(g*#JDHV($~Qx7u83LA->Bdc zA#w`fqDzI8lMR|DWINq)ZCxhhcmsQMu`W+L@?_K+aA4L& zVpbUES0;Tn7iL|PT+C*@3tJb94$Juvv_y!UPeIoSDX&|n4%YQXzwLGI(b>9D?C`qx z>tNknQ}flyN1!;c5Up4wHD3uuOOrlZgqoKplewt*XSm?5bj=?2EWF#OASaxMduX~| zr^kNWN`-7^3*2#!kmGy{S|#K`-p!@!v5^ha)M6H1}7$mogS#M!1-kNbN^!pG*3z4N}{ZFXP0y7Jk`o4CedE3&}$)#;IFG>{XnSBFjvM{dRNnXR1T@C4X#m0Nl37;l?HUgC$PHyJP{=y~tm9Y_b zna!~0Yaw!OM5B%f;lB4-@?%zcBUFANDlfwMw@II?!VXBk)ES+Rdmi7t@DrX{xD7>l z_Eu4zW$h?WeomBU9yiL@c_7LcTrkSxI~3)y=2Z;B&vyhKOcq}NMd2uSbS%mpmlfrX zh)3D4*|B92NbgC;6R0UC%1+CRa%=JtyoMwe*7sFq<*-G$jnT-!(WK4xXPGF6Mo!MP z$co&GLt{Kf=YWUY-!RaEjVS9TB!*Yu&?M;a{W;W$-UZp+G1S_3%(T>bn0~*q=?Pd) zR%j#Y40W^Dp-AB)IQ)SBx_)fcbr9!e)82)?98NAgkpUA5{>>+xm%V;5))S?iT<3X= zzi_wACg|EA^+(;|o&%9iccCvVY6nF`FT?AKTHlhdqj3!4aBoW6ihON4fkV zG+xRtKaI=xfldU_vHezPD!b+ZJAsVsBd{SBe&`yUyEY1iAI_MCqWIBKlnpW7OA}aI;eh+5h}_b{|r77m$L6wN&fs#@oBh}yH6#sfDCVPi;J*O z8;BO~^Or$7xdsM)7}u6(Uk^R8@H1mjB+AxU?nd-pcz^MDq&RMr4gREfNj}D!yN7c= z&p#KXA}+r|4u7Q~!-|{_%3&qVLrL!HuWhb0`)g}%0<72$E|o*^wICL2V4hVq;KAxC_Pq zL|#s8ACH#)Ca)mYkbQC%#mh<%NEJK09W=(|m1Bbtd;+-~Lcs-mxE=>9QU`qz=ETT) zSR1~E&)8O7m@PAfwPzx?r!&|{lfhmJ^1Kn80CmukF2a`UB35K?I*lzhV(c?3@>Mz` z7v`FbBAi(f9>rl!j1UgFA9LrPOZEXau^v)dJcy2rgvU{A8YuSHN~BMq5^jeTd;B`k zL@MF7II$17%O_C@7YtdElUZM5);F2#N4HIqDCP zpI;QP?7JbvQ=Jux$tnv z)Cnbg<%Qh(81MeX5;i$fcjEN(Eq{`hiMnw#%%5DsA5}Bl#SG_b$aI&mwkaB7?jP); zsT#7}=B(|4I&46Wo6RsoLxEdwEa1Xu8|0Lj_Fbf}yK;RI`g1hYvmzWcbaHEy3i82< zus4$jJe&zvL>| zn5z3aWJ~74yVYeZTGAXAb}Hln)G`mVWM(`6AtVR68-u*ivC2<}x;Z?9zQ!3NP%=23 z5A(UmFm73S75sY{7x}uTh|c{Q1IQ}B4bGd%xe7}qqhK5qSfw4&gkS~|6IN*`SHZbQ79N@In=XtzYP&|(}2g=Ih&46Ngy!lTwk2m{?nEeJ*Pia>4^RlV>rf1Xxl3KcwUJY|aq5wBq@GfU=c-m5GmDk6 zj}LrSXy#SDy;wtHjdq8OPN>w;p@NPM6?Al{prbGLM@O_cI-Esl<8adbqBqa#`z z9ns>9Ig7vEts`0-9ns?Gh!#gjv^f7KqUHZYwEUllmj5>+T0-fFmQXsPC6tb638f=i zLg|Q>5Mj>Yh?Y<~q9v4$XbGhwT0&D%h9g=+>4=t4I-(`?$`BLL5=uw3gwhc$p%;eY z0})H5BU(Ze2V=F5*p$%95qMq4C+UcmP&%R|l#XZ#r6XEGyHPtww1m#w`C>_xfN=LMW(h)78bVN%i9nlg>N3?{}5iOx~L`x_g(Gp5Ww1i$6 zh=mY;B27oMgwhc$p>#w`C>_xfN=LMW(h)78bVN%i9nlg>N3?{}5iOx%gRlzYD$)@x zp@-oOj%W#`BU(b~h?Y<~q9v4$XbGhwT0-fFmQXsPC6tb638f=iLg|Q>P)$TjK1Z}T zbBJ%8*@V|+F7cZkx8Z)=*NXMKv|{}(tysTHE7tGQiuJp+V*M_ySiegv*6-4a^}DoU z{VuK8yi3cJcWKu^-O006;CJfj;|}IK(uo-$Ms?9&ir z8)_O1GGWVhF4-d3f#qC7rv#_4T)v2h6#cxN+{=tKs7g6!2L8F3|Oi@#EcD+vc+4Bs=9=SBQkaIFk&ivp#?5&uo zdqHqNQ165K{+N5&rDk)F_5d`d+^s$QHSfuGj+6A z(J*7a!Oki=jIqFAcNIO2WeZjOApZ7N(e0dDWHk3z(MDWRvB@2*q91T>iOC(NqGQ-S zr3Oc+Xdli^7#yXdd$|E+2G3K`YQ}Pd6I65=H@1$!^Hua0#-zdNDms-rrLMtQcr?2j z&f_7F$7?g+it|{@VUJErCz6$M4$kA8@b5vFS(+|`U)8;evpGQ@boLYJY}d-TmvcBl zA98qk%TCqR4#&6r!R#o_8HRsIGad>yV-M6*U*nnx!~$DwuPwSQxDRXXz)Q9si&n7L zE1>O$oO(m?lH_HZM`wvG=e?fl^WURBGOIM7h@^FZAf^NaA zbPk@ppT{|z@c-bDvleRCr-h+*70Yo#4qNnEI>)u*&v7C<{6IP}!^(II=W$NZIVaLN zj+JqQb2tI}Jx(b0#zb*lpV8l%R9wP}$)X)!;oY1N(aPg^Hz%ZM<41_h60+%*LwHjs z$hK|0qzr`YRLLLo1 zjBpd7FpU7+CFIk2pp`-qIv;eeP?TnY9uUf)OF<6_WzquBBSJA+0(wj+i*5m}7mCwe zpbbLVv<>vMP!65{0fI<`a%mUxo)^law?SKk@@W=Iz9dvYA0lsuP$7K=+9^~-M?kL& z71NKP-9jaF0`#^}DJ8$eJ1C(9H3sbyDnn;qSnOVap0xi)XJ0Ix{n>YT=T+?UAmGma ztk^p(3!S~glyUbIws`MR?tsEF1-r+RVYBaLC1xH z^d9I>p%Co{{UhYjMF;TFxx|e8FkJ?6g?w5F3JFE%dXO&^rCUK6LK(CIlqHl&4}x-p zV)Pg&Unq+E!C!n*0qI3u}TquLS z1&t8Oq@O@%3&rRJXrxdU5hl`egyM7z*W@UnY-)tO(Ly=Y0yIV_m#RSL3guB-(0M}n z)CDwFsDOHd#t9YDAkcWBB038+L8zEUgC+`f6$FWaXJHZlTbE|1l=r@ zLt{Zpg>vb9&@DoFG!wK;D4*8ju6~;kcg6G)_dWR8{t?&Rj1qH4?So6>_7b1Fh`VBC ziPtUaRM7oG*tG%lfRIBEgB}!e=`d)uP=NM>9uf-D z;Xf>EjZla_0X-t*(J{FDQK2w>1$tb_r$5nY>xClpHRws9DD}gX@{~{pbpt&ulu6IS zHO~sgXgg?=P!_!gdQK=#Z-X`qWzz?s=Y?|U0O$pwT>299qEH?k1#J<^r|zI_LfjR1 zmbjzgXZv|P@4j2Q;(m1AOC>&c5qHI|67O(6x}r61gRhIIMNL6(2oX&Ly(y$<6lk}Q zOdf`a~#7tI#nAgfi$3&}TxKl=>O>bDI3>(D3=Ckki%A?zl zdo>T?%yS2QT~{w#twr=pSyQG~b@ zP$MBC4^=i6QnVX+O@wS}h`gpk4kbX%gk0(ZI!P!%r-7Oa1?d3BPz#|D?E|$G^5|3C z0ZtJL)BB)GA)m4_C8dNSMJa~K;54BO3W3@RWs>tJo?r;Y$Om;0%0h$$zVRaz zr$SICp=>G#br#B@hM+D&xpWe!t56=b26Yq4r$UVW?uK+%Bum{yF}h;H2|TMQHTRJs z43?gyK6ep!#lTW;P6@iA7E0pVhs7 z%Exukr_{X@p0$VI#@$bxe>Sd_Ii)^#3OoObQjdQXhF1QCFI{Bkx)vm)at4iBNzxVq{z=6r|C=U_~Poq8^}|ggm+zC6@|?X*p<_ zkWW1^+HMny&`w-icL+u4{@?I@4WSIW3v{>S9YFU8Wl?v~Dxo;_1Klf> zO+!KV3FXk)p!$s|I$*oAOYu3g8i3?^IyRI;Gt5VJB6M9c&T>} zio`k%8f>i>Q9P5t9Q>qEh^jFSY!LG3svogVF{HxO66!We9u}9F6Q2>vjP>bkJ!`;; zk%z(doKQZUje?sEsbX0ANU6JxE!}`#cvLLyjf!3<^|=LX>5fwGv@%#aq_g#^RKd{I z+9`w|!21}_ibQLSuG){4h~&lT0ni&l+4M0y@|KjuBLiH9dnB)j4uakmV%xTsx+77s zeKGp|C9&;UoWEP@v(0SV$EDubatz_V7!02nQM_*-jS1&dQRLDZEF(S_3eaz#U>PA4 zjP>i##X2N}yCdd^!-kYcw|szQgyi|O1w-l^p$HYBhHr(U)CqUT??f(x2E&%4hFmxU zpL32$$voPHCDac>`LTW-yI4O870{KKyniyJ3hDF%SUyNzF+B|@9v3R59;okxluW=; z`%2wK@Pa)9HGe3Mx&oh_{wVd?f$S)i@aETnqn4qGZo(`oLbMzd6!K^#$P)_F{UBe+ zr!}CcP=p=>WeP>@MZ!8XkvgjL7zEGSpFis1FvSZx_ z_P0t5sRBBNPD@B$2{{-iWkRKt4JsE(&Im`5?C(G0tAw@CJNkTT|f|?6CR0L`v4HB}c2$$Cop%690BjGcIFz>?| zXBxuKovj3&B@~bKA7~91$f4D+X@rR7Q7=p`=SW@wZNwe%T*)h<0mvIGc_p+Nc@rg% zub`d@cPAQS7r}GArM)3c>XQ>b`+?g#GvSS@2e$^{k_$!DqNRV}CM-l0Mc&0iin2ko zg>1S3-8M%E-xx>UTp^d%;=;YekP6Ux(4~ejFvc9fJw!@I=oQd>p$r&4HQ``#Xzr`b~)feobIMgzNs+gwN?#4l54Tm$wxztGYYk)j3AYo{ZBD;atho9RZqW&!6|m^)gg1gk_ril~YKh*La4%y~PJci|r{Pk0IN`HO z7JVY&-NvF5VCaTgqK_urXIYff9~aSIa6LYi@L45`Zccb_vuImfC@<6!eJ0`l%%YsW zNkn_Y`!6PZR>`8TB)n(?h;H16XW+F&wNVhqCyNK?^)V3?(vq~0yJK=R_(E*sR z_SO=8BjHYBQBL12qAf5^-b?tbl129?ysKEWD-8Rzmgolw_W>5=^p8ZeGd?38NcgOh zMZZdTFRI(6@pA!jpK3DQC zZ2D6wnGcCzna`DTB^hPj9XO@M=-rqRE$7i6E_0t_QBIGPnHxh3jKQojpH;GGL7BIg zMXyGYqFSOkW$v#m%ISF`Iu#Q~ahcC5Su|PZWmZV7^=gSG%G{HYZdYJtE*H`97_#-t zd{)V#P0PHVESf}-lWK`pl)2}#D5p0T(PhDjcOX75?%c7q1{;6cp3 zQpwBci{WKHSI(83Tjp)xN*>01JGQ2hA2H{QH-zsz-ta9Z^)h`!bs}^TnmMVa$|4NI zDN-_rmSP}I6)K>{XxlWAD}gy9%iQH~Ij+$}XaK-wL{0$bq7zW$tEH^dl546GesiP;pP0 z&lRwuhswN0O`vE#tbMpf(IU{JX+?Ao#?d;V5KTa@Jt-8U>7b25IW!ly@n?k!s10bd z5Vz~TGPf7%vTuYB9}si4xcB(nb_-lm>l?hn7Mi z>I?eBP$UMmd&^vo@U_oHd*2ha3qQjQTjq0htoG|NZv~1_H`Mk`joN;o?}UiX0DUi{ z=p4`wLN<*D{UqejG|(?XF15t?{Y@x97bEYuP>?PM{UH>hMWDZgJQ)5(nY)DzuY}hQ zi{XsL6sFFQiwpTwjl3M87>$HybA__#6y)U#70{W;D-bF~qwI2b87#JsVwQ2s z&CGrSuA-uHpBu}KN|t-ioP|G@&f=;kLFyak>ya z)Ltl?E(LWI%Aq8j*jXr-iqNm!gbHXLX2kA7h4kCb%a^(Udu`eQ|R{RyGBUfiFj*Xa}VlKXtU zdY-Nq!n5?6cD7!gUaD7`^Yx-}fnNXpPcP7x=(X03df9Y~UIE>%7c+P1b;&(?iE+PP z13aW}y=(P7Zk@hCZP53HXY|CqImqAl4SrUZeYcM{YkJmwOHW~YgGERQmXv4D!QXv) z1~{OH@E5^%>mX-%c{Z*P>nlAPzqRr+Fp`4Tm$T<}c+&^)uMWQoSQ$HU9_Iv|^HVwp z-=+SXb2tGb`&dKo)m9kUor>_ALJiZC=kQF-br4YXR2x=vy zXgTN4LU^1GN(lw&c~G@bh_-{;2zhjki&ef*m~H}{F67f4 zpmstLS_SGL6s0wwPC^;99@IrBlb!{26N=GRP!FLj+6n3<6sJ9)K0?{_LI7_fgmP#H zXn;^Iy$Kp5lt=tC(L;pt=@ZZyLIrdfbf!=t9R&>+DxzOOXA2e6-=K4ZN+^KN9xYT# ze}K*vN{}7GhYBI?>?RfN`{+q~D>}Pbh3V`|FpS4n_&f->v!_;g_g0~^?Q6pGOcp#KSF(GJkHLUDQ% zv_vSIrsFnry-*I#2Hhx>OY=cD3+2)OK(`3x(~Y28g$n3)(CtEnbPs5`P!T-@x=W~- z)`3^n>{LG9=T!JS2)MH!t?+KB z=FTp~(;^W?XM@%Wp|e5jh0xicCxp=1peKdU*`N(V=xoqaLg;MJMj>=I=xHHzHs~24 zk2Yd-KPwcb6LGxc5yDTzWh44TC_-V-i$YO~gSHA~&ictmV6`?F@ z0oo}Pr%o77uL)(7or4cuLOImj!-p=RT#6%ak5C>}A@3cbd@4iUyFvxj5cIxKA$^7V zJ`gIRQ;_$OP%)hb+AmZ>ok5=pl@k9J%R!+8%?Euh#GSpS!d;J^wD+L1ACb=9j53ER zd>#bc*+(m)m!68wzBqvgR~6-0Xi0Eq2k3x!;fPNCPX({MuA%~WOei3qM z73f!?06hfyO(;l@gMJqZ(MHg5A&>gPZ6}1nw6G9&a3Pg0Ukj5fNrbwuW>S8dL2o=+%$V&*7&{4>h3zgEd1-OF?C1@+Co)CBT zkqU1GdeW|6j+b?25ZEtb1<;^TCJzF9b0pZTQS^K6?88_>G;dVC&2;u!6lx(vbPI0t zCkrY11Rc{#D5!(cPcan214-4Wk(YHEs(cG8%qERWSf9<`;BVb1lTCq9UsbsEQ6iVe zST5I%uWC1YV^cZC!hn z`n`}@r5+P9tJEKa%qsOqA+t*TNyw~He-<*U)L(?mD)m<(vr7F<$gEO-7c#5V6GCQ{ z`lpatrT#5sR;gB{X@gm%Dj~BnN@01h)4Wat=${ZlX{hUr1ih6 z)OwXZ4+8G&CY9b_+}Uqo3^X&Mcyjp~sJW0sJ3uE3g=j0Nl~5$su~RRrwNNb915_nc z5bFx67UG8p4J+NUb};9WMwpW-*om%O$nfM}Cuw$i{LXp@Ih<2$gUX4^6PbaBu zrF#~OevMhVePzB*UxtNtw@RN?vS`0bZzfLZTxc91qPW7SSEaj*MejQut4|UA8?7Hy z>9b0{bcR=YyI8adKH8mKsV^NovQDDK zZh}Q&rO(x|MN=z1w>{M6Hp8OOSVU~mq)N9T((US|SYn7p3RTaj^jRf~&Z+eJvMASj zi4n!al8z+pcdQ9T(FbtuWtBcxz={@Dde^X`RdCk-YT0mQrTYkr z{s@y7i0F5y{Mt&NRkG+!mELw1J+m=laB7KOSLq&RQBJ=>ME7^X%B<37l`Oil()))+ zUqq2rwM6f%bnA40XlG>JEuu%@h5IUfR>`7kE4?--LU9}(t0nqSr8|N}cXY zSn0maqKlEfRYV7-un?;BStSpiH!HnwSo9wZ;kV2H!EEoUU6pRMBShyx^mQ2^U&7n( zRQjxvYyGg&>yIMzDSG+i%A&PM#oD4Hat{dEw5B~Ka3PmgVsL*h#3SInN_PfV(g`yA zD)U%_eGmivP^Hh6b0yzZdaJpT4j35Uo2KCk-;DPEAmq?D5cyG>9faDiE8U%}b_P85 zjWl}^`tqkrpQ~fFCn~*TthNke@=qg*AB`V`tKsijihiwh;}{zD2n@g9MbQUv)IXIz zSHOw_RbDlU&`t17s7hb*a6(TsG%UmxsVa9kD>~W*i4Bk-Yizs zAEG&FMG(!Xa&KkPO<2CiM6?jM#k?w?RdOGeRe7(m=xRKItW%Yq0A6m7FT)tZ1TY9x z-;kaFimTl3SZ#A$-KAA#0$`6ctn#@!w&;dB-qf_kRtj4z1B|hY-$N*9fjCql~wL_T*(9sjg(X} z0|}j~e6E};>0RY*;7TUIGkuLHhQ@qMj{R#X>R#o($BHgN1wBR44HcMVt9-726`fh- zeb0)%hDF0glxMmjRc;pAWlzUAIzvRS#yC2=%4d}+7)2-x+Q-!r9aZJ_X3^i_ zkTD{<1lP%gDxX!d=mk~YSQcG@UYlt|@yXq#DOK(w7JV5vi)kYI1@>wN|US8$h z!=i^VUazPndP$YLjYUs~+vkZW!so1oRX(d^(Hp9~k63gwwBKYzZLW23mHQWqK8m(p zC!)V#gf6Y}StX0!RTa%cGie$wz7|JU z4q(yU?Gf})OZ2`fZzhW_fXW9%Gz%6yQkBUnq5M{O182Ehb1v&(bx)%GIHhxO^*&Xr z5s#z&NVjjsVZAisFb2@mXupVVsfvEYqCHUKwpx~KuJZn3(T~u-FNn%^xHh&|WwJ`H z^)<8~&7w`H^^IDhub}-%w_j?G50xV7B4Ib$&!R4E!e~H3F4vsPI#}HYRnf6HrGuDU zKB}ee-70Sp((TFc-TR{Ma=3PXRVFK8(J!i^_psHnMx(f~c zsw$IJ!jgAzHQ+3lYtCgItnL`bKTc@_YWz{exbU|a|G4(;C*i`Q;?8$5oPNgm7tuef zysjuh`+4R}i_$dCO_|9sK>TKeQpIbLh7EyT`n}4Xz-o_S$~+-zzrj#bDW9uji~Lmd zZdSVm4vVH_sF91QH`5RW=wn>yu~b=&+F;6ik=3q)D$i7I*T-aq14Cu%>$2uP$dxjMARO}ULxB9|@BW&K=L zgOqm;5~&`>P=$ygNFRcYYaDYb227J$j!CB6E4ZpR(XI7T<}UF=BTTX>pDSRsty9sB ztoA5YcU3hlcmS1D*RA!A>KQPW=3jzoWTPi1m-DA7FSc0!3ZzMjdADg&1N(YpPn%9usb@7W7Sd%ektB=$rmh)hc*kSSph%V72F@qPtn` zBy`j08nulvV$Q8m8^rv6UM;o5Q{E4(_6>~bvqf!tcwlTQldD4udZ%2s7mR0%b6G!E zH6`V>K_c~l&C^5-!4r+}wA2s=XDbYY8MV50V#*x>8M`~i{AB6cHISc~^0@;3EOTkf zyNT5*%me$-FDeo&* zJ0I)5>%=~+is8u{gz&B&PP<8nyLM5^4flrH+b|HX5o?EGu-=^VxjI(6Jmp=DB6J!C z(p@!bH$dR-8ntJGRtVuoPvQNQLN=Y#5;q7ThqB@IRYESEg{$OVA$-h+arX(aakr-2 z)ok3|(0;oZw+<2yqflt3voX4Sc*)D3eA(=W9Y) zlm}nFA(TgTK)Z$VsVQiWPytne-WDpPj-b6lCDaG>o=_R zbBv7DW$khAOZnU>+;5+!yoK!ii5OIe()~swG0}f1#Gj@=O}P)TA})1Mda?W@d=oC^ za|NvESjyYVik`)l{i6|8JOI8;xu3IW4CzNj^dPMMIpwoT7X2gTh5JFYFRtLf(xUVr z3jLEZpK;iR-%@TzwDI84IK3BksylSrtD;fq-zgpi69k#)(cE_`5vN4{2 zRhwCUFVsY8?T%>V@9!E)=EF z$m=P@4*;80yZ6H?dmrp*UTr?M? zu%cCRe)`u%gLGpCXFN;nG>vK3BksE~)lz$7!r{ zm%-M&v_-K#{rXy0NOuwxU0m&MVntC{G)ENGN7JsV_PGL9bZxbF5U1LrCI7MLx>^=3 ztaj~zP_zoSrvHhe-dJ4RQ0;RCtmxKiuQ7^fi*EmqMR(P*=;ms-H!Es`p1wsC&A@cD zqT1&Qc&1%l?L`N{q9$5a!y(YvFZZF{a z=PEBi`WC73wN{wAt9>?wt9-9Ix-(tnzUuS~pT++dW$ztkMX|MgcUAY=sdt!}4b04* zAq+tf5XoU?qlkzEML`T0K|#R)f~Y746cEIWV!{As)ML&$pkg}0Ip!>i0rN5E@4i>n z0MGm1$92(FtEyJ0>gwva=LaWmc?lCH`p=;Bmo${bzJ1j>2+u(Nok0aUprQ4Ha_z?Z z*gyF{hBh=C(w=raKPWvEI^pG5`akq$PwI{Pk3j{xLyNV8WG}R6$rxMGK3#n` zDE&vXtN;1#;u~kg{DYV9tpTJTy<~OI{Ol#SXMXWgrMVFM=~pk|Z^JR`qN9T%uq;wd5J%Q`)ZK1-V|smAo2 zy)a@AU?4M%%@g`+Tz6%?WX$%MAbBrYvkomQycC)@Ays)PGQ-ibg_p$qfVx&*N|@gv z)p#jsOb?s^yp%G-aah!QDQ&*QIkJtHGUf+J?Ysoo4y5*8%9;>!s-u^3CWf??m-40v zsf(8irVdh9FIAWhkh*)R(sYB=!%J1>P@HypdZ}pYunT*8sfFnPsh^i>OkYR?y;L$~ zNR3|NZ|A~Bxf~-K&PGqA(H&~nW5*6|jJZ>Ix*Fb?{*r_LGn$NOY(8E60cn(%aP^F} zb&QunQwM1`FS$R&G`6wsDOl5YUqc%uw>Mm#h)c*}jqXI#0RuL!F=i-S2`4nBhoXu3 z087?>je3H|BL6?`LoyqIiK<4NMbu<3cYPb2ujb8D6rc8(c2(QfMxP%f()b z%$*p8Grc6H0#=rI39fMLp5-M5cS@tY#o*Q;xOqOfCov3XH^vN_!Clyx?mB@ZhXGyY zRReP+M&M#E8M6<9yTnU4c6;IW!%LwFuoPV8C0-w%*C@NdUbqr&F7PfZF{_t1#teln zuW3x5N0*P|V7|_)2Br}+_IfWFa{~HxgO{vnfr)mbmqIwXs!{HwlT~oC!aEs;`;S$P zF`d)N9gXSk`@+e?m=Skva*~0<-J6`G(XV?pIVoU9+}rHLbQ*|@buUF`!62Lvy@a=+ z*gX$;2_Ji4_dMt&4*IQ)G6tT*SFxjR^TFMX4m{KtGiV0)WMley2KNh^JndES0s(zq z?ImLlhRbKXWKAEqeAY{$Spk>Nc_}jQ;u3R>m&DY-%JW`In2Ry0FL;T;J=!Q=GPv28 zi;w%@*7n57wlQYV4DLUT>GFOE?h(w0SG_9c2M)^DykyKIjNI#9vW6c}zTqXXR52so z^b%*pzZ>O1*b6^HXV-d{=U}YgZj2cUU4GP6}i!ZA@>sKb&+xPrl#e6qo6@}xz{oAf@>2Awcu0mvFD<-eOrGayFLAHunq)k5 z!XII_(B#(p1DkO6Zi?xSX4^HT=hAE~%(mZTwuqVD(Myc4zDcg6AwDi|;|&eQ!P%)P zrUM%4-ju$NhHl1i^>C_|Cyp*n@+MU$Vc@!Y)q3Q6HpMha)d5ZEtq+814;*cSHpS2i zK{t5`?`yEKZ099w`eNtq;HA(!hL$^diP83HlF_giu0t>Sd6)ZQ3EH_SW+-$yrYSv{ zF6U!<@9tF@?WiU>gQ_1ubr-KXc?eFtO)*VUb-$+c^Hkjh$HIY|V%Q1NK~A!fSq}Ay zzAj;QKzAp3iSg~#Bwy0WDjXa8cqivz@*dI@(>a|S(Ugu3f|DtjU`KhgjPI}}*$U<1 zGuU0zn&U%$MpI0aRGrh5Broyh=j^65vEShvP(IE%2wPy$ zIHjpT2Q;*>DR(gq-GDi^$f@EzI?XQehS-_Yn$i!@&oIMx%Bz~v2hz|sxLsP|4gG-pO-%(lfUEPGWEOHQ8C6SKr13kO(yt&} zL8{!{P7Tj9_QyQE$4kcifmQHcF98mPd2qjzYy`dF0biA<7&j((&KVXupJ(P zS#Z1Gm49LoA8Lvj2;D!~lpZt5yMNlNI`^x+zc10VP9hhs!uXo?vY-T${KeI}ZixmZ?S^Qs)Ge>cf3RJ|DUWvy3z2C8o~#WYFP z_nXqIsoI3q;KL^Wb{?v4H_4||{S1fmyG`z$`%s$Vpv|Do!g*w0^X;dMik zG#m`o#W-X?^Im(R&DTvaO;YujrrfD$Vopc#Z+`CwW)4=o-@Rl^CDi})Qe-03{pBU8 z7>++6^0$`~6}t}${_z3_?1!fGO8UPA`}-#sS2zyFf^vaz(SNd>TSNbYN8lw;*&TX; zxfBW+FY$RvSWa)Gp$^+&Fw1(H37aq;*>Zsn(Bk_h`5U>G>`Y5qr12KzG*MG#9h$as zYL<;F$}$M$Arb(&}FQ>!FP(2beZ^RZ}hnA%i%ELYw(qUe;JI+I+$}vq+bzC{U z9aRYz8Shk6?CY4aOr+}eIEC%*Rqq{&2XN(>CaHRGIlYLgx8W$9;=ST0X|R8o51%XN zfn`}mL+4@NPxOX{qUTe~F&)s*jB@&Y8tQ`{&TJ0fbj9e;@{%!Uqi%M2^Fz@i$`VY0 z*)BU`#rJ0UdDd~|nC@uynL^Ri{cETZW8vYzL%Bi}f zoIaSUy>UFA-K=UJ!0bP#IU*QZSe6Aev_1CNB5!CuuCdN5$8^Hsug(Fxx5_HBvr31rz;L+4DfnGvsbec``|_|SySek?4{6j8iv~m zFGZ#jUAoyzJULulmfo-z?g|Slz01?E>uxQ_423T5E~n?y<$F-Q*Q*95gYmoHOV;$n zs6F7N&?K?9AM{dWcE{{~$V+s2ds(ih%hv|unVxq!8ohj^95WQUe7cm^*dLuHMZLbDX3{k)eVa~oQ|;3c|zyeu_`!DST!d(yjH3)?T1V}?SP|1GC? zMH4fN>$F$JPkS*GuY1Xu07LnPm-zJem9osB*@f7T>%7^W;o_}wOm{TR^sBJR>~b`!*ktxPL{-^r)^r<=wcSgh z8H|1vy%d=Vh`EKA*st_p842s*T+I1+usa_-jW(?Y#|(@Cv>u#3m;qe3GoHvbn}ura zU|B%b^DvR>yz0%E>g@-|G)dL&gVR@1^=K?#J)CL^*W!Uqb{Q;BQkgYf2Uq`x`MHR+ z_u%*qD(jz}XK5GAejo{gDmHIHho5gz+AByVU+*{mXuO`%Umw2NuXsfk3i^R|*8T2q zL%-s4D9XFv8h+ZZcnMlm=$F^^`blm({SvmL{-OWm$o^HgqID_A9jTvK9i?APP1i4#X6RQ!N9#vFGm{a3WKWnqpxfAed_heXE5=T^@EBBq3i~IQF?Ro zcDCy}NcYh#$%iO)8&v!UEpF8}pid;%Qft>i+TW*=pHdn#sJIv{R_m+Awffd@UGg33 zPIc}6ll+v@v_ZxBX!okV4*XEx<$a_t;@0b1w2zbDv(<`0#c4R)KFRWh*b`yyPZmBh zNQZBAnB_a9HDQ*oR$dCTd{weG%q20AlcuqF3eAUEzIpgC%)P_X?Hh}aVE2C#=5Fi` zaY&;^{%4rw6Y{@dh)-mrtUhIqvV3A}qb#4zhEbMJL8Bj4B;v`4lM=W%;}&jOJIN|Q$1BFgd>yj7It{cUxWJ#Zo}s-s*hwz8Uijd!O$qn%l2VWZYWE)D(fuSDawt(c{bVEH5wk}CQ$5BF3!hZ91&%Cy*@9>^4j~f zD0e$fGRf^-+tZ`mLllRUizi^mEr_zb%055JolXn8ly%@Pz~G{EX_PyMrTaOr7e={D zDehk`zK^&sin6>^z9Y)=Lif%n%L~)HqTID?Gv67yJIeB!^PVVo8%r;6rT0czUO?U# zQabQXLVd+#~C-Lc=H5Okl!g>YkRJ(85My^*AW{5cn%jO~I1 zzi`|RN!Hl$NOHy=jwEmFJR}8Uzq|Wtu0&vf7W(FlC!o6N#5GAND9_|hXl40m%?9Y>yg;d zzPtiuq3sPR3hl>`B(%RF0ikFF3X`Ed5J@Vuvyr4jd*fyBhn6ehFSM^f%7%6Wl3Zy2 zK$3?#>I$K4a}E4Owl5MB*-=PrWG5mCBYPZ@D6(fGk;q}eNFuRE zArY~EVmE@aG#^q@>}5z&VsA&17CZ0;_!Bz@Ni6mq?mw|7LCT3;iX<=gCL{&1Pb0x@ zc?*e2*l&^8gq0iNFJVuIhbUorSt|+K3kf(*J0nRZ?9eOWFJTXWlup<_H^E=RjzkhC z>_JGf340To~WCNDZ3m}CS~tL5~u8QNU|yW z9+F(jK7=OulwFIYkg~0Afxoovj>M$xP$V{O_dyb-?Q|qj+AcsMX?r;m(5~)4l1$rY zk)+c0T_owW-R4&KOWPfh#A!PLNj7cAEQi0eodGGIwhNII()Kc}3^;UdM`AMed+ceO zvClvXGxi-MQN||OKO|Tmz|(3CDTxG9Dr5T~NoQ<~wIGwR4M^gQ9e^a8u_IBJ%h+8Z zl+Mh0m$*f%kDVMd6Bgtp& zYe))Ny95gaR-F|{OwQhi#OCZvNWz?5k0i?3Uy(@8=3yGtv5rWRIopUNm9x9kU(ON$ zo5|VENaCCwOn*7M2a;UQPD7H<*;A1ea`tyD5Ln(Sut1o+-3p1#+cJ_cZ^t2t@^&f` z$=mO-Hxqe#3Z!J-UW6o-w>Kk6=j~jq8kxMk07;y;HzLXA?W0I?dHY`^`MmuCNg*Fp zU$6p-dzp)l#@T7=hp?p#+4PWukB75=e~W0MJJxf%>`R0c-GZ%+X8eeNg2K}u!`seb zZ!|6T`F@k`sI#eC{D4|_ehw}0#s5UhG2wJn)I9Vz!by*P3Hg}p@bviNS!f!>WQV8s zEUM@DnmUJ9M9AN&dViN#0W+2ru>x;b#QH|z${2kNrS9>##M^C)nEP7i`0* z&Cj%RGPV-EMmy0CpFlP0@Et;ou0TiA(G0|v2?~#(D1Cm|8RlyK!XULv-_Ys=^l%;m zO5aq)aD(`KXs7>G!yZO)TSSq*t%d=l;?)?-^zB-cjfqB2-&I(SW)*Qq41D@-6)NL3 z6z(a!m%^1s+;Iwo`*T~tO$#@y4^?qkYvTRaqUK>0>Vw`5XprG1sN^1~WL$+yIJ}R9 zi{L%q4F#2NqAFizZU8p<;n)^Si+#I#dLqs0SYE*W)2ZD!;tC!$Rk?7kqn z3WH^$CGXM8b{LT;y7Fs!`3$?GBD(w|UKxLjHbbHZVR@dNhatoj$oh>)to;Kcg|qe& z1ct@`dCcLU!mdZBgLbwZn+&lpVgCj5Qa`W`F{L8b1~y2w)C^$uTWKbR-_2>JB1nzU zOuHa8K{G>w)Zv<$hatTWzB0?g`_QMFUl6LzTzV(E6K7d|dCSjeJ+A%-!t$0J5e&nb z=tbs=a0!|XjWXAzkD7}+g-6ly#+T4og3>#%zKVI1C{2-|LJ=&&K>C#{E&{Ol(eP-ZF{66Mu zO1EOr?`PK5md?arJ*Z7umkx%>hqSy+uw#^2Dd!;GzBd(3aBUTf`-bo1T0DLf-3e;C zb7o|&UV$dsFO1MNZ=$=8hSVz7p#Oe;tbP{-QK<9dUG&C8mv7+VHwIxyGz&J9L7^{? zvlqi#se3%a_PYPBISINQzktW6{ae&+_yciAJ0l-O+rtjlk{Bj3uZ5pecP#99-8aWj z_jH{pZ^43zE=Jx)H)D&n?s4=y^M2S7jfziUzIv^X7EtTUcj)l~7&Fm!sI<{ph&&1k z_an)C7Vb-}Ul4@X+V~K)-dA5m%w`k4j!xKUH*Ddn@l$Ah7oJb8fw17Ue*cbIhoToj zG!^sIM89JGm}oYlwLx_kPNtN37LEG-fTCT|E;i+p(fWlqsIviE{G}xfyN!tJ3Zwqm zM$uSoB{~w@M6?LoWKg|5r(#RW%f7koq_<4{1p`knug^X&Q+8SG7VfsO>%F}tBIz8bHOIp`~_)}Y2ZE% zlP9y~!KOjySn?_Cw#*@>ft^YvmvT-`c2YKZ)!UG!IH@9eD~2a?sFPYGx8saB%rtOc z)+B$!e#%TW4ctq$$;AwLnrYxTmy*|Gh%<+q2F{hbJfyLG>(7$0JRQ4&~Xa zPF--Y_sq;N8&5?Sw`JfnO)IWALGnO`Gs{Ufxe<#|<`~mT7uV!7UqPDfq*SuVx?`P` zO{Qt(I44ykuZDxn@lI-yJe-qluBoDxn&eiPlbKVURG(}|z0*yJ2XedQZuGv;Ne#($ ze?wYi^bFQMIe^2q*hw9dyVK^GMo(xRlQ*(%iIX}dU#0i6Oh|09s4iZM zWzo0aaXj0v;prke9`oHs7hsDcvp3efctqHf?R%iww;z2I+Yi+vqazL-6aDfhwZ4I` zFk1HxDx+U4cjMd zYYYiOEqnq;@qytzXi%)fLg1sA6rBc*d#DlJ%FCCa@CxR0JSF@TEo)ByhgT3&$D&dE zF$~6s>(v!fL>wQXLKJ_Gc^x0=uDjxXun`}nLN+LLhUIvASOEihTB)hS=%wPBXVT(@ z*y-^x-r}ve=80#wV?`8H9)P6qAf`xsYUl@T@e8wNt2wqgq?PkB?&Qk_C0?4l02Ps5B*n}0A}OVpPw~YnWV=o~`p6)@q-r_5RCJv- zYi1B%TE)epGCme|;>)zAD*g;hOnkZ46ocN2U^K%`P{~;H%vLgl!fPL)-SRMreEwo= zYW~40SB|ebbw0|uQpT&QZbUwaKZ()5hpJwH5XC~_xvI}0q~cpKapJeCS}wqable%M zdi+V%KnNA_r>h}+U9}5@7IDMJ5Pqqe0ih+Wujppa&24lrml$p{06_n!!jDx zO#e6thGj?Ye+H~&K0*2DI-VYbnCJZLE_E6}`~eQg?5Si%bcHSud3AdFL?K0X5nVRjD{+Qs|P^mr9I#&2Ln%I>K`mpF~c zvwNw~JsyYkC%d-_J>yq!dd}`s$6of;yQu8Gx+dT^sTis3eyw@zmUT_Y?ypxELxMux z->5nuoCT#}TVbiqPAPF9TX2rmZt`7F8u?)Oi0g0QJdB{$~tH6LyIm+?OWSDVD0Sse@@1ZU4AQetlnPbx4UjJEIx59 z^rFc(V4K?a3T&~5Q+J>1GZ(u|O={G?w8W++xlEW^w^U1_R30YrPf~|nqM1bMnDaD~ zO#Qw@GpW=GE|X3@<}#Vo(v?~jr;5&LHdV1gOR}kxS7|1fdX2H+p+%~zYm-ksbG4S_ zQ#ZPjLTclcT2hhf&x=1C9;q(e3AiOrO~b6izhY{*(`u2LV@ylX}u=)uvu`PHR&~tNn@TKK1BTTGBeT@6A3l z+hy9MDqUc0QwLq3Rc(S|`#U!6j+c6zi5;9d*zJ1swCO?q>uP;l5fuJHAM)RXj5W`;HLK9yRQ~&O zsP_%VIsZc&PH|iiQ24P8D{u`k2}$7r3{w85@KEIQOR?Gd4a|o8AC=d#;AU(pufnG0 zjLTrM(Cb6w^^92PqxX~UBwy&O=VhGa*C3QazwkjcYeDmW;=jI^fw8ZUZ~Fzhab8;% zw`Gs6sH62ZTVYgI)X;dFbJhpJHPQ>ww)+DIXZHA*C#@Y3lw0=O-GPy*Xq!GBEe>HR z4kp~xbJGT!pxq)aen+d;{AR5!PF(HUa&0+6>u>tM^&DGm8MM0#S3udt+Gx$DM&sw9 zUawQyb>`Z)K!K#YHy{Owc=zjzzWbba*uEz1(YaN^GKb6d>=<8;CLAOrNV;1!Jds9KfG1xT^n(DK0LpV2Og4~0q15E`DbKb#EHcd}d zZ1pS_(A>XFQ7c9q{THMQO=53WJ&$utZkf@EH(>I#S;57|9lj0GbNFuA9KA{Z43ky; zhEHF_7X@Z9DmqL$ayGJU+0|fR%^G~vXLwM&*jzW$bYxxqSvU{mW}4otbYadk!?9z7 z`twR!v!@K#So)Zr=XjTWT)8ug^37)Zm{Gj=aAy0M39K13 zV9Kmn!FDFi10V=SCVqy?PDYQ1fq9H)m0`yYZMI%zw$`9WLpfJv`fCWInjVEDCegj! zGk9CS5RJFF^l9Wuy3ZQ>KEYpHe1-k_-RNUqN7K92KHoX+a$E>`ooQQ-v3@bBQS6%f z2W8jgy3hRze}|}9SDx8}-S*yyTe2mY_Dy@_@PayQs;|axn!+9p zU9c2|`=E9G{+;nzZB5uqZT46TlOLFwtau;UmLHhjTCw|2l%6zgDV>k%t*USb+VW{X zKYFbDDhSRstEe{+7i%rgH9b^s+tX0d@|C)6+hgvxTwS;Awy3S@mk7R$_*}(AclAX1 z`G~4@e`|v6F=|ux!L^r3w8ioiS{chE5`o(=#VuYrWU#9Ds2PoX)W~v^!r$Tz(idY| znO?PruzVcLZL%B7H?~80-`e9?6eXWzl1e^;q*Wx-rq5>Kvyjrob-46Zsy+NOC8OOlm6>Ma;_s*d!Q0c+f5=Gz0F%#vFD(44AvH4NV#)_>~r>lbAP9k}x$; zN}A)aO__~2&eLWBwiz?`Zk!6t`Djxx{ZLzBu0?r+c?9JRW*cnVo2OCR!E``*M>7^S zJDIg8?`aISy?i7$yvs=5#Sh>D^Bqom#tcK=n${Rse9DP!WPZT6k78a%K4I_=@jQln z%Jf6awD}hKjCmWnv3Ud~Su+KB(36qRn{jAgFt=h`Vcx^`T{9fDADY{s^{qJ<+rQ0m zX!(zi=fxix$;U5nG!DlxZi1Ssu#-vOXfaA1u&+8B?!Ca071~Af#-4^|TN~~@Yum#~ zH!Y9s1u)!Q^J0t0Z=?ByeHm?fXg+CYBHvSWQ?@(8>81IMeFQdpYd&iiBi~2c=k2Y? z_tkvCwt#Lw%~#lMksqM>%AocTI12}wke!JbdXhmuk4%aarGU=aPFX)2qOPB#!ff** zHfB1u){RBf>vxtv3x^H(kPLbmOmsC62Bix5Rk}c~+ylOTXUobf(DIK5kqhdUBbo~N zxuT2~^;E;m3DHpg3aJ#aJhv?ts)o`%P|#VK*zIVPn)fjXfjJQdu&0MZaUM$5Ylk3W zi`-(=?O$MVlJj~+bN!GY|6ll+n>(LXFdjVITqQwnD6~$=-NGvFsn?sUP7U%;qiS*G zvnZ*$AI`U4iu#`*#k3Jr@tUJ852+#!|M*5^;u_}IERfd7Rl9otl+9jI%zW%8kyO_%62CrgQ{u4t(7{_;Nd`& z$Oy!P_oz4qX65cfn-<4SIubm3?v@tE1hYEd>eY_nO*ITm4rV8r!@uH4xR|;YO8l>J zO&z4hh2z_9|HrTghE}q&p#yi)HDmTMX;mV%XCyhA8A>*!Iy8*t^jxWbNpal9)C-9DsakCZaW|wPR46T0aSgcIxa2 zn1rd>XfCOj(I%0qp9s~|$UV?JmBOA%r}n`%lR9EI?CI2f=twp-Xm`xM)ZM!vsMPmp zSxAl96=9`T?SSSzdQgt24o3UuQ%Aw_3#sSOyBAZ3qZcow4u#E^Q_1lF-^-O~+1<#k2y`1G z2cic(jI_XjY-?mSG`$I2Zj ze8fs049VxAJcRy!5z2EItc{_Z1HCUpX^Fb8P>7aahq65izX|17xcxSi&*130P<}#_ z??c%drgw>CHzd18@(C2iMDjgs?iR_9=)>+v;C5^z+hEs^i{vD<+#`}NM&WbWNVbLB zJtLWqsk2ukKVe+=j^r7}8OhZc(+QCr1}pnUaxBJWzer*z>>tSjjP4zgj6_H+L=HfJ zEk*W)%{d~&FiIzgEW?!|rdnlI6Q21~xw?JVdq|6dZ<@)mWkL8m7Rru0`2H(c^p<|R?ATcVpg?$4~1i@ zWiPvG#P${d<-i)UmOG;^4ljy5MS(+Z)S$jl#za4s{?VT4X%=5d5~GBbN(dY{6~WAJq< zGtk-7cp}f)R!^S8l!Q-A;@$^s3$UWJaz;Y;~;((ZFq{0UxPvX z*^3}QO7PbMgSb6{$N49S??7M)X5K;vlgvDaK}a!k4|4=IT609nArytx5&(J1lEF?n=u+K zwGFBmb-W+6aJd@97hnu6GaKMNWM&0A7%?*&gCNYD2B!&T-iH=j#r+T=uGE5fM;sQG znFWZDdO_=5FmLP$CcFc3ThkskOdD!-eh(+MdQ*q#RX@Bn=2rbBs63{AR3&Cr{jegY zRQ>oY=2QLOC^^3Vl@^#T^^4H*r25|*FhA>Hj5a}~51MbSwnJU@kz z8M()}AUeh9sTYI$Ibw)Tbz(AI*m4%$EZ(KGEx@>K+I|vLc4`hN*fG(h%UjA-(D9 z<|WU?MOO5dt9v5%MIO@IUeDx6#fskXiY9ku6~uSFrpb-MkVo%%Rg-&^Uf%b*HpgGA zL?3uvn|qtOA9`JzE3@_^uWNga1k^cNZ>rvAykU;NR*60~RUbh7F3L@#_=&0F6%i)0 zrtDd9734yYXP2uu9?x$stm4%d&2?s@Z*gP9N^SLBbLoyYX#Hj_Y;Q2pBN*bUC1}da zI5mvR`M=OI&jPLK+*}g|71hY+S)d!O9^PCnK}CPous}Ckx9E&Rw@oEOtU3ytnaxe% zV-j1jK#iQ$Tw{ZZxvXKq|No8JdZXD^HmG=xW>`=)8veg;u7UrLSi=Gxu^9WMd078o zA;-L3b0O$voJ(rGUvpt~P|*qbJPWjDx8|BQLB;m0VS(06Yp%%$6%$y)0^Ml!;^yio zsF=eV7U%{K7+$KChalRqcnSIM+M20|%ifFpE44M;)p-6aFVv=AM3clN*x=Y`O5?(Q zU2RCU$jHaF=?ctPa|e{<)7m;}nb3@;_*re;Xo``Uhv#(ig|AKGu2DXyl|In3y-@Q} zZ8g>GfXDwir=VDV-emeLn*PO$k=dW(Z(ExFwpPwn)2R90n?4=+ z-)m#Kr0KAfzKNzErfDg;sBw%K`KMN1q%vzv$;I_Jl<{jb8pYx!m8J9sWDCRh*ddT& zsa|&`lq1QNB$b2mOehpeHLS4H#RRQNF^y8Wbt&B*O$x(zf^yp}m1|3~6P2qmz;#|Z zhM^9nm`1rPx|Pz?ku`^)ShgwEb9ceh=$$46GN4pP5q~oZyR~ykE}*RoVQcG>+pRaD zM*~YSebCkprSwCzbvbSA_Sma~f@();xITOp1%Vm~{L2>@CM~Zb^=%>DDlJvLDMEFf8YkV!EX1 zi%aRNX!=`@)}_s+ovo|3w6(M(Ptw*~80Cw+t@Rj}t4lF`(AG_*^hVm6!{NHQRCg4L zap80f!@R|dI`^(CNv;C6W})VWQZ?Jz!x7`HrI7Z{Nk&om zXpHmS{_x8ps0T|ijZ*okQhG9#H?mW!OC?=m^w@o@B#Wp#9Q*8vQY%*2W1#$ODW*}* zu2)Lwl~kU^J+;p5WnAfCPrX=@)l_Z?g_r%FdIMc}trXKJmESF;V_fT)Pub`9oiZ*E zm(teyO*7^r)^6~%73Q7)VLpA~YkBD*ZyjKn<+bSJw|-BZf>uA3Vj89LU#0X#R3>3Y{&C9q=0;bEsBVi@;4Ua%b?Fb0E$p$w9)T3Th}F>)ImcPE~>@ zffoAvUHQ|sXsN&4mA_nzRtc`S}b4z`K%XiNN z*WteU3tj0{DxQyM1}32t^{wpcTAY~R;&+n% z?p6+RWv3*#h|Npz$X=kozLoP_%^CXZTRFc}dBcf(O%D{l%?3?E1e>e@!coxc2`^@Q8U;e=jR* zT#MKA_p!5hsB!-&hK{VYZ)fEfSHC{NDfNl|f>x4sI;x*0I5j>`+98-{ zHLh%sFWE8O0{< z4$IrPS!ZyR;>1=bhoi<;Y>mgO&C{$e9y!&;+n}7v1M1QXsQlZuP#(0Ua-TZ6k;<&; z=attY-&7aVC>NI<>(WnB`N1-jcdFA116<4F!eIM4`Gm@>*`dx|7<}6Ucl>oRjneb( zb?ID7DA#p`^0;Qt=G8tB$9qwi$X)8BCmPzr(Z4Z1kcoZqfT%8}kD${~BOU5iqKP|L zI@J~LgAimmDuKzBFpH&^8*ytg>~7@lD`aq8aV?rAOosiaclQ%AvQCeR)<$n2WK>;o zBO0|a8OA#VzrW{^b|><>YfcR+=sV8>t$DGz20QIx*04ZpHZ<2%1QoBbh6SyE8-V!s zsSDXj3~I6=-M1Cu-t`a^ryF!oai@OGp%7y)0*}SooD=c)7QzY%8)R?j*+ZtFrlFcw z(e_ca$~VL;532rz{lk#+*Vb^=sv&(fT}_<~l^Sm>Fe~Y*w8_;obXC9Em656jd5W%n zgR2$|Ztw07rPd8G9dPe45&Db9N(YIyJcEyE9A5?Eg^ozXtv1U$&894SF8IHS#2i zJ9*KV%jtNy7p*yho_6+PXckf&;l;>2P2EvG4*Y?A){gdK(oCkfix*So7+l`Uu3k)= ztEoH2iy5;M#ofFZn-?hV?!~O(pD>cKUd);OIkJ0rQTx9g`j5_8hA_nU{~_2IkN#s^ z*#862f85rZpK1D_2E716|9_!4(Tm2M%b+KD(VBDV_+T%FW(dVYycn6SDNgZX!hA>F zL%oP+6?ldoE%zvqSxEEt{AZw5CV%FS7-6Or2Gh^6zx)-(o z6VQKj&K`w^`!%?Wwi}S2f&OD$c=a=7&G$u{cCwbAD zBE^%v7@F1;Pw`@8I#WE=i(-0Foae=a*@>1<^J3C8vG#N?rpyBNaK0DQ<|#H_;6<!;4w-CdEZw%$biVF7{&Hd_(a}FBZ&S+zm^-SYam9?^#}~G#@gmv%Oel zPGsYAyjV1IIcLxHVhi&(b3fiI=exh#J;tCP;*>^yKx;4r7N)e zF)g_JuWd;G#@)Y+wyyWeIQ$vq4PG>65W~93i+B);cN`5;k7r}nLT{xvy%X}cG{kht z^TXW@>7CHT{KUBK-Lz=W=2+hEMZU$C+Z$vmZL#J~ze-;Wj}JA(^ueQabwm1e+8RMy z&$>e#&zrEsJ<%Z7Q~9E~LGYA6#MdGEH4QP1vXAQ;(l1kaS9<=h>qQz*F~X8Z{5a&lXo#mH?;a$vR2>}@waeZO#mmvCFB)Nb4KcYrSvu1- z8ftRUA7Q(>OX@z3AL z+YQA=l&-KD?nOLc*NfSYF@QSqO+f|6H_rmC`K!4m5mbE58W!kAtLxD(RcsYhWRcIa zp!FV{8(%hr+;`e+$L40qprQ|(u>g}CjN0RnE09qufYkEAk8zM%0i{+&UDkoAy$lVl z$JDaIdQ9!EDCfikrgi}yNE>2m1)SQ2v=x~BxCa2LRndWJ1*BRP9jR7;s#VdUY6YxX z6(ci+rU0u|(ZOm3v|1G%tyX}mRng&U1-x1n9j{gZtX0tgYX!tw6&9N{9k*5hu2s>2YX#(56&<-&fUZ^1p=$-~ zS`{6;RsgS6(ZOp4^jZ}iy;gv)Rng&V1^ikS9lurpuvO6kYy|{c6&=A=fUs53A#4Q< zTNNF{RsgY8(Lrnl6k8P?#a4i^RZ&-YaBOeHuC@!ttWXm>qmqw7SfMlzpBiRa2wkkT5t$<~#Vzw|8&{+Y@R>g_}VYULAt%@}T(rg7d zTNUehh5*lYJNUG>@Sd)}3+p^M1kaY?@(cli*_KAB46^MBR3_P0fVO2Dyy7I}`8ZhHl7dAO}s zyoHel+?GCQ3vk=}Xlo_LO+dG08y5)hwr^4Se~27-TUGvg`+#^`8l^Juwm(pLLRTn* zZ@XC;fZJ9bq0AZpZdKU>ZfTUt0NnOO69wD~2)CP+fw>;-_N@YN9Z>BOKw*t!TW@TV*U#7Ch+^Xj{ z&Firx11U{ zwP4Nwb-Oc_J?d8Hj7QzlC_MvpdoGoUx)rc)N23_4^-vB0V7Dqd*sXwetD>Xb3UIe7 z>ZAbg_D*`*5qjX=vci5eI3Vwq5zrHOw_niH4wx$f;4Qm?mEaMM7l^kiI^wMWd8;F! zFLuDZ&29yAo_Wg(>zTK7Nz-87_Cph8-U^_%Y~!J~0_rVAJ^(NR?Cm~iXg&6p71m>K z>4Ua_y*&+C#oh|Iw`_v}A@^1QzEx3efqZ)%8d^`jWrg+RTl%0akZ&JDR>`*l^ex-C z;{fd2k5FSh`<4~fvu|mXyA|x)+RkWC_N@SZt9vgn&kTVG`YlDg2-|}q@V6A*LIM75 z8G6?9Z&l6nZ|Rb8fq%OfO_P5s0N~QSiwgwY6R7M7xEj}nodObYX_U$!;66d+ia}5Y z0@o><9z!64fvYNxfh&OEYORCd3MjZL>hJ-B`!PLD#f$+4SJh?>!%r#(#EgKRfWggn zfhS^c1sq(q!HgjXR{+A@YzrjZZPC!qMG;82YRi*w>4UaF!W~IlB;g8BxT*|uM!>>7 zlFFWitID2*OQTc<3-=5vSE5n?!`-Y58ty78|GHy98m=mzjYA1ETpFb^Xt+;PnKWDh z4wr3G>KQ!TPpRyAxT@@VxHL*-@NfehFUrFe0C6`fgNWM!HP#bxRe4v8ABea#N@Wmn z2UD3uTmcf7Z9?@7ChkNk|Enn=6IYcz6PHG*3?}Z0RGz`(6HwgE%An$2No7yPRpmQ& z#-tQ7QwDJDj}AP(GzlMhRPu1R&|3i3AqA9?q+2$a{HmidPc4)zknWtkxQct z2aw!RXi`J>H8ewufaFf5#d~m^3n;mpEdrCfh!*e0Z~~L77GJ|0116Vds0>W*<5VUl zSHQ`2%F4+VfO09~W$W9V`yl0xrl^NMP`T@A`a5iZ%2m@Il}nd24ODIk;VUXvz{>Te zWjojcEZ3WUm#YD2xtmP`mpd4G_70p(fy-6X9+yj(G!0ztu{2Fwu7H>8O|QmLECA+u z(+3ZQ2x9JL(?I54O4Hw9?E^AbO}~wK0c0*+a)`mq{TH$|484X<=nu@?4agcYa|O^` z?~l-20X5hAYr?Ao0XBEDKX7wXP_h5U&IUJE{dsOKozOJ6xkJ!Ixw!&xt~X6^u7I5D zO@D~i0(9eK^n6Sx@N?C)=jYNTM+pGk{~}w%&}-;~{s7R8F;NttDLArFwu7IS=rM-rs*U$<5fu#F7vP#kwpme=IqI3l;UGI-9 zT>(sYvp>*ue}kSK(JdfNSN*L*|3TBG6W&pQrrQe>MQOSMobEyt;{qkiYi;m!RdhUE z0Z>;(eQpM#?s(|gFK~7MQI{3g6Lsm5QG=*^HcgYLD?sXMn79(>aR8>SijJu(faDw5y^6?FvY{Dmv1x0JW>4L+uJ!yDB=?t^l^H zqJ!-UXuB#p+O7b%tD?j03V6FJI^M1TxT~TA?h1&zDmvn>0J*E8L+%QgyDB>7t^m5L zqJ!=VsJkjU>aGC0tD?j13b?x}I_|CjysKgx-s#^nP`Y5qt-;{}@-8dvvLOMpn?1{Q2wH=q39F{yxPtacdSfyp5=_p24fiufh-*yfjK>FnGsPc>pd|1Q1@fahHXl@E%WP zPvKSN6;K9+mqw`!3hxRklfo;&@Ujh7A7Xd~9Nx{n0EqW#+S&p70P(6V58|Z{-r)em zI~mu?3gQ)zc&9pBxAIX4P`oM{Mezz)yec{tuK>oYqJ!}YXuK*q8m|DytD?j43V6IK zIv%e8$g83Q@(PH&Dmo&s0LiPOKJ5gPcM$@#p2^D!+XABqCNKNO@c@%|CHrtX2NO_U zHy%7MfXcg?%9r3;3shbm08izmQ7VJV`!$u{rZTX+elUsU6>xb~)TIkx-U{3VSr6t_ zTMy%81u!pt&=$bFgV01VxB@b-w!!CATwj3ZRa-a@7y+Aif7mS&>^g&x- z^DacTKsK)c&a28nfpA^{omY3VzCQt;_a@r%cwV*D38z@#dFg|;fahI@tcweLUTx#! z0-#q-Yg{1o{zzLZak>McSKE0)FMZG!2)#TITwFl(s1wdaF9ne>*yy%F&0;I3jI;5|F>8qk+`U;@F zDmtjIfa|=`wHN` zDmu8YfbOfJqx%Z*zA8GruYm8XqT~At0KY0az_0Z7q9gnY5WiaM5WfP(uZoWGD}el} zSjVXa%I_-}a_cF-tgzSP)&rDZ?k%1RLHX^3D-@;t3NXKV5(*44zXHy$ijMOu0R5^M zD(F{0`c=`9eg&vsiYa|*0M_paShb$@%L?mRzYK_LDpJsZ{zXIH^ih4={@Aq1o-V4hMc)zOVdB1c?)8PF+O4DERt_Q$hwn^w!3W&cSQrQ!K zRe3cIM-YE$l*%Cf9)dMRiN6BmFWcZkgUDY2^H)X3{FP(9=%BxHoEIJSSC03h!~V(~ zFFNk80Q{?_9Qap2{#8-C2=wn62*Eyqy8)noSz$f;m(epypnua?PZj+u3%qim>|a^v zMF;;C(0|o5E>?Mg1N^Uw4*x6Q|ElQtzXAZTiVgrQAONcfNDki+00FF`MhOORcZ6U) z1DF-|NsJO0z>JU@z$%8k zWC0GifWyVEf+ygB)zdIMs{sy}5zrHGz)R6Yalir|uqp?JJYWG3SVeqHgj1q`2&|$t zBm&F5&7MprE`j%X(J_JLelI#Gusq;JM+FvOfz_1m2ylV#Wt5%^%nExqjw*1089k!} z7kD6cpmKo)U|?0o+ZI&IYA-r6usq{MhXxj~fwgg{Y+wN#SVad17SMrJbaY?=9#}<( z2Nv*wRn#Z}2;L7N*x9(`10a|cb}jCe00?IEj1qw0I~nC8oGu^)t1@N}598Oo=n%p3 zx)&WISl;lWg9OW)UexIVOz^98>@mUW*kghj5FG;(TsH)ci3t{Pg1uvMg5?u0I#94| z@S-CH3sAw@Sf>kE!P~)%^{im^f z8hjW^T$G>&tK-0El)wh7=%b9h=%WNUSZjTh2`~C6fezMMA0^nqD*7k^4^~m51U+~O zLa<*VO3;H@VLd(g6CWk$!A~*D`fCPEFHb5VFDuD3k|J@2&*j*5vC8?0z`N;Z4n|Ypa^Rl zJsSZdJe|suuvh>itQ8(3Orul=MtC)qd*E~};0XIbT5&xANLWR@^y2elkc3rqBw+zc zSVe~t7O;d>)TjXy{)~=2Oqdnc!-N?S9Rnt8U{ztl0-CTYYt+CAcSMc#IAK+uJOuZe zO)-s9893o1s7#!&fG4cVp&?IL02Edg2NV_%g|*fZg#}1q6*WvSh0mp@RX8JnDXeOq zDa;7y2~6Re=xGYhI0C4!w$U&_6@HP*o+_*rlQC036{b-tgDU(Zm5KiqV1?DQ!wL(y z!Yb-pW`KpOG2+&Ph1He^3)2T}0W3TOO_cpBAPch%K4VbRKntra?G)I;htQU13#%>9 z7N!rLb^sTigKQ0htD#jo09<$_vd#hM!rsB?A@BpdFh$^np$)$9YBaQ-FRTtcUzk>D z3w+_PX-ky>7*^##0mA~qFh%#a1c>1ZT##9h7*<;zF-#wH2gYzGG^t^5HMB|xU<@xt zVS$Wc0c2P$1_~J#P=-}>m|p>ASVhPA6>x^tO9b6O02hLX8_S9iMgRq`DOrul=b@&-7-^q&+V24?3R2kgi&#Al^XE<<&Sz&vk z6}ZDRN@Z||cR@##J1hVXJ7onA3&_JN8YK@4(8DS^^ssq6#Kg{qL2Jpj|GK|3^&KQ2F)l~KIkC(t9vRF-fWHDXRG?2xw)AX^J z83JapH%(@-09x!#f6Q7?i=AoH19Mw8c+p{t1>9n-b=+bBxL8H)BFM$RF^&`tH;{{2 zVLiE+@i7jNi}|Oqlw2%87ppRU2f)J(>|zxiyI24(R?)$W1@vMS9lcn9FILgviv|2* z6*Ue3j8B6TdoeDS0WfBT^#EhW$2b5mevokxU@RaQt8!pSFcu(;Rdfhr0mE2D9cn;~ z-=%2}F;>$aVoaAb4T$j$V_^D4jDmn->`gCc7lASMrin2YaEzU4(+#NrWUQhC84F0p zDms#}0A;MAb`dP&$#7yl%a|4RXzv?6%Uu%uzPM|G9|}8|u>fYg1ohn${NT4| zf?w|TO7Ih02QwDHjH&Nn#sZiz0rhJm@(};n6Ut6%-Dt{_#Nel1V4FnFk=DC znAS!o_$8x*84F;>EORhp0nC_|#w7R!qJtR=V8(1QHZc-q;}ZNN(7}uaFyjX>vJPe} zfElyh#00|_K^)9j05fLP7bf@x$3+Q#A>m-g0+=ydU!35F z4-RH5fElywiUeP~UzOlh)zt~U`F1d40nC`zRwnoc+rf+lFyo&Q*R=`0n07E@0nGR~ zl--cv`(_6-7Ql?D>tMzLnDNpWC%gpTB0r%pV*$*V-k(Z-+7*W#V8*w>#_9y$(XLJK zWvhc33t+}<=U~PHnDHvKdo{sVs2?Wy^7EqvUt6wE@P(s;84F;>3vsx8lHrTPCmhUJ z05e_!L#x9K->$6*GknkVQkdauBM&ncz>Ke>`7pybFCRLXu>fW~8l@g)EPxp^qCdk7 zUj+OeX82e>h%)*JJ<9N5xQ#M=+8jn1KF*Dz3?Hsal;M-lM3mv9#blJ>v%6H3sT+dN z-=fTuNHS4|&ynIN!v{4UW-Ndib1-vJhR;~?QHGC43Q>j+Ix3fYwrd3gf z&l5b%SO7C-#4Vx>@BLdL#$f^e$Zv+Xsvc%6fEiP>Hp=iuv;<#R-8{@#05fJ~JzS%- zHQFF)6J>a}H0xo;0+=xy zd6=;PW_&gF;)p22tNwYQksw0{A{cq9%I z2QwDHj9Kbo#sZje5^-OIp+}=TF!V_7j555Q^)O=r%$O>7qyMA8R&y|80nC`C_hL9u z>S4wLm@!N5$Bsez|8e);QF0X5`*+`-4%0KUyR$)?cXky}K-yg)q?HiC(kg-yAdzzx z!2*-BWugftm|(!<9BhKgm>i7(6HGSAWCVzu)B8NPZg21R_nz~<=lk!Ea~RF1tM08^ z)z#HCJv;ZgEhunjcY9Fy0{`3*6u9g8dr;sG<<6kM4Z>YPf%oUTg97iR_XGvr%ICME9Lx>r(+xI&$;}BxT`xG&!G3Kzr^Ar8?*m8`T{>JPUugu#{H4kXXIcZ6i zS3aI4JkYTr=2|#$?Hq4f_};O-KY0v?Yi2E+;f0lc_w^VjbJ*M;u0)A{2QIbNe)k>n z>9~Bl`inQI3ue68ZZQovrv4&*(srHxWI1hTEkwGKX@eV{+8-Hyi(s(v(=MA=<)gQi2+dL-K9JAdGeirl>>65lg`jc;II|H^G4-R_$ z{;+Km*p9&(zoFS)*Nq2r{YCnu?RNbM^Y_&(nvM_pI}C1k%l>dv8b5$r#@1#$0So<3 z{Y5&Z@gC?g-U`1m#A8uAO*Qj2@xnbFAv+CD+EVnNt`0=K-OSZctXRM4FR}?Ff%U`2 z{vYu+;%WCHp1&aCnaH~&6jS=^U%|yyia5g4A`aEeh@GD6vbSvBUthZ^ZqEgF#`6md zEAZWnE1^K=;vQa^ZB+9>$Ho|kaG(Ah18ZUa@#y)ct6*IYszb0Nw`4xENS%{Npeg(6- zKD_)1|7$4Qcw^o=5^L_5nqzUOv+!lwMq$lIa3HUmVtLgR%R5c67HWzWrsXbSeWxkL zmjn49}I>pM*`tv_$xW~ix}V)+sO#mUQm^CLzqubN_c z)fCHr`##1dpT}#IS52|J(-do=rdVO)Tn;Weou=5{jA66G=<|t{cpo}VvCuTdTBs>j z*gCffEu5y9MzP%$v`|g4ywenGdGagN+$nb)3WlksSYatM+}2W4tgxGAarA1bDOT8B z0V;uS0`^eI*HTlg@N0#V*D?yR6qe;~go84@3~R&admgQ>?I$d8DRTVc#wm z1YV-x;c>5)!eWI(6!KmRg~bYo=K4{z zI)%jwM^+D0WwF9Bm(rBVVujz=^8|RcJD-gT$JMg{?Ouz2%6vbug(72x<8y}rhN;L{ z;Sb}sfB{9u3MUu%9?DZY0sdGu7ZB7^iM4P>9nJI3@0kjvaTFQ*(^MFg$5CSJEM~~8 zt=;cE)IYn9$Lng}dm8|OF_hFJt+i%UpTzXD4Sew$uY=bz-!`s}mlo=b75<$2JC82F zfnlmMRyeC;3hN}=>!wkIh8h?Y54(f~*wvyb|9LLjf zq;um}(j~As?I|3{Z;mQne(bAUqGrCqCCW*IwNM(YI6HSaDh*qPIWn`jF7xo#QW~r{ zuk9e1d9{=VE6#7@DGF*S4OU#BCHY!PgB2GllxisrR$Qb|uB9|saeak`T1tZzH&AG< zr8HP^LxuL*V{rKt7b|qtQW~tdL}5fNrNN3DDU7bAG+1$Cg>ki%1}ko&Fus=3V8u<_ z*vpA}B^Ni>D|t#SrNN3@bntRpORwbOmL0sTr+F=u1}kordj&>gC=FKJsr4efuR{mD zmFT|SR$_1X&bZ~29;k~x7Z%thIKqL~)PRMtbWp5A^CLXEp*bj?rrmp!bq|U+ z;G9mL{ukmpDBhKz5gif_8norHbKlDmywH_+O*_%Sm65t%v|Z}{%4jXRFYU;>*G0~7 z1D@yW4Q^z_Hyd0+C$~HBnm#4XcP{@v;BtO6pC>b+tWIe`G@r{~@;+TIjOJ_jdF%yC zi=z2l$29y6qCw&BXKiWtXSfot=_bz4KZP2;w|yG^pTgM#6X)!3kdq6-L1XZDSK_ro zUd8)Ez;m|&T^#uwdj5xCI@k4t_tDZx!E`QC32(`zlY{A8tP)k}J0+OTMa#{GKL$D* zyjF^OZLSWF9dNjLFo6zT%`II`?d5iX2I#fEf+1Z)t!@~wS|gaKVMNcvbd6vmUCUb+ zqSwQ<=6?oi4tD`N|Er{toQl!@Hpi~j?vQrv+uWoqlJ9dGvqthu&LW{Q*!^m?-GJ5o zxfvSCft-&I~`Wy8@RXK+U~#>tylnJIMe3ssEoajn;C#+%fItTDi3}-U>rpJGYk3w*zrvO6xdq@lG4$ zuRrxyL=-vK{{erw++_9lFlStlo6LJ(vix=U3v-is4|M+GLH?4|-xORCFZetQCk*&| z!S7Rlk3I;~7yQlicH8b8_sd#Cnuw0Y2f7n3#O}?HfcjY$u z3$%S*YnuF>2(HPNK~1*0Ca3-yPD-!+gqQKY=HW)WihCP+t(2;JRyZ~<548BKxE3dJ zt$0o*Xp2)A{qr(Gd#nq`3$Da9|B_@qepzfHQ>^Z2b#9ecub1T4)jsQdz0^Tz0_`r(>k6jsuNv(B=G6UxoD9El z_tI#WG~nM1x|i-V_+EN|-AkLk<6y7hZZvxj*sU@6MzhA?8_gPnZZvBSzR^sx8x22w zm8K8A>ui0s}ZU#y^my-$8A!E5>l*SQ6Wp7*V2sONn_vc8_B z-CXH*tXtaoF}y5FbWdW})h0>3y78LU=Z&(#g?usnY{UhrAzYo)EBTzWt08nZz!M#8 z&k{YsO=-VJ@Rs^upuv1O5X^(YT)m}^WH1i~n`tjJmzS%Dr#J}mq=?%RU^Ypx>X^rzHyEZOD`^O)j9zA}Y z%p* zhBveeZS>XbZvF3DQ`=zo`sS$P(RbmAXZ$y5Y&sD`8CRs0O>Yf@WY`RpRAdI9a+S`S z1n6?A6{VeVUgMz#r%Xr5WCz&WBZ|0I+SvMG@KRcFEe_O6&2@SB9sO@KQuX&-+i0pF zR$Y%b)IqGeEZ4TyRT%!Nani~5OVl*1>M;!rkGXU3mw3Ug2x7cyc5PkbG`p5=hKCSN zv#Z5vcC|Rot`?`+Ri?HBBnmfzQ~v2EM5Ot`cP&n{t8AKG2e1Zi4qgdYoLAzz7AM?Q zUeN^~6I(E7Uj5-LJf1In*W!e`TAXm#YEHNd2OmaR^Idb%^8nrV{CU5_a0Jt_iSPmy z?g~`6D^TICK!v*k748aDxGQMimZmD)6{v7mpu%0j?u+nAFHqsGK!v*k748aDxGPZM zu0Vym0u}BGRJbcp;jTc1yMk30;^rTya95zhU4aUB1uEPXsBl-H!d<~*XsZ&aa90o@ z@~%LIyMo=|VOXHTU4aUB1?72oW*c0BIy(j`+!d&BSFru&5bOw4xGQ)BgYj6P!d=16 z7~CgQ`_)fUXcfwu%y*T)__)fUXcfwu%6$oro-*>`Yz7y{9 zop6`$gu8qv+~p6!6X%a|z7y{9op6`$gu8qv+~t3TDxc+iC*0*b;V$0^cll1Z%jW~h z^#k7tclq5o^&1Ah6YlaqSPx$f2fh>T@{h!oxN+b+;V%Cn#u@ldxXX9KUA`0U@||#( z?}WSjbvM9g@6dO`UH<0qd0^-};V%CSjM>4V?}WR2C*0*b;V$0^cll1Z%Xh+Ez7y{9 zop6_b0>XVd_J?D#JQMqs4Lt~V`A)dYKLRu2x!C^!gZzB#JK-+h33vHUxXX9KUA`0U z@||#(?}WR2C*0*b;V$0^cll1Z%l{f9acPb3gu8qv+~qsrF5d}v`EO$Ol}GtbxXV8W zo!+a-cfwu16YlbzaF;(1eb~3j|8Q%3C64VcX7m0{z7y{9op6`$gu8qv+~qsrF5d}v z`A)dYcfwu16YlbzaF@?VH@|E0|BI2BcCPP)yL>0ym;}<(PyN>U1#L+%r_P8 z;th9@a2GL7@^hSU7io}imtsTS33m~sId8&UB)=u^guAq;E$@W86x#DnxJ#iU?}WP) zDtRZ|rO=5#o}h5oEr_sgdoO@;*B1!8?f@@+X? z$%_aa(p~q0rq!m>T`XH(n@V@F?B1FWs!v(p# z+H2sy^wW4P-qd*Y>~aIge@@Ia(u10Unv|4wWmRIve0i`)))Mgp+`2A?yr z0Uq}nZpM)=yt6?@QxF^26bJryVgsRy4IILz28j*iOl*J+c#(G?x|3a~WP{jrg zLFaNS@My-w2684gz;R*!AvUlnKCS#;C^mrpLu}v>bS}3K`fp+bITIV;xUl~a8`u;} z&;NyD1L!}*1`a{za)ZPMawaywalw6vVgs9$(f?Fz;CLLyX5klJoDdsO%)|y1GqC~1 zOl&|g6B|&>#0C^Iu>r+QY(Oy+8&J%|1{5=~0mV#gKrs^=P|U;z6f>~_#Y}8KF%uh5 z%)|y1GqC~1Ol&|g6B|&>#0C^Iu>r+QY(Oy+8&J%|1{5=~0mV#gKrs^=P|U;z6nO^^ zAvSO@&TY=b23U|Yu>npCo_>f8{EeqS6&p}vZ$NB7F%uh5^ywO61JBX5i4CZ06B}TY zygxu};Agu2{}vm-Dh;uLp|$WeNNgZyVgqc0S1H5>)X z@CTG@coAPJ_T|EWANVH!Fg1h z+6G$zyl-IJYh(vkT~4`ylj`xkH*dsV?HO3pLdXqVf@-Emr6}4H_!qPS4syb&%IK!G4@QE+(6C$lpCl? zY&4bdxN#gl6L$PJgc z&xWP};Ei@Mn+AYyXc_>4p=kg_hNc0KH#7}^f}v>ulnhM+pxV$h0Lq4@0Z?aX8UPK3 zrUB4sXc_>`hNc0~YG@h&?S`fSP%$(OfG$JR02pRy8UP~=;Td2AeN&!T~{+>PfjFGFhmk1;_8OJoI{*wh+j?- zCm9BEC9%&iliSSybb=NZTLvTx8fF4-+>q93uZB zE;ekG=ZPB`Hpy$mO$?jmUE*ejEwYlhg<-3FP29?`O@1bBW7sYcJ`RW58Ft7I#2pMP zlEX*3a3@2Z4P!@#VKZjHeV7g1qup#cq!TIyql=s+oDIuHC!gXYp`6_g(!y&Sq_(#J=`91M;!zMX}c&1^qoJBm#uthE;o@3Z5R}#-P zY?JGW=Nq=mZNv)=J0KJcyx6cJdE%vpIvaKy4LM`XhDTAdhs}m5SP3p4UF0m`Z20Tw z~LOHv@-V^}41#QO}Z<$JC=4;a=+7fT;9 zEX!!(BZjpyp7^L?oy_30d(5z2at**I3>&1EJBKF?he#bupEhh1B#?*nlwp%}vh+E_ zW*J3%!LUW%XS**Mw#r17{>QLQ)*`-Y*e)}PuN!vAfw;cI{~A_gIq@w+oefuw4u|4m z%RPM{q&e`8?*d~Xvv|`vUD{0$h z*de#$`VNN~R^&e72t%C>D@G^17~b3}UHJOVO_SU`IecwDriQbGpN6`}RPj{HyL?pL zJEm)?n+<V~nj1;B|8krNM}q{fU%c-C`IVIx0wOgo+C zrsBY)F*OW`pZeY(9o~hvO`MBO48e;U!WE;Eck#BsjjdPUh9)TRMwTyd0V@^gwCr`> z$mphw$ z6r^rB&?wB$n2V2d2N_2B8K`=&QHV zN$a|+J{XAUC})kB`ez`hqYZtH;uv%7qBzzl%=hD~gz)!&b1pZG@=KUS=L$pZ=Q-WUS7@Tl-EqPo%0MRk*ri|S@0i|Q6bi|STGjp~~2MA8cc4V?g& zT_%)|o`>zThLPmy>N!L0_&>UnqYy&f;>B?DPwV-j*YVADcMaobn6GwMeSj>q zyzdP)$`8Afdl_Y8y?7s6lxyJ>|Il5-=s9a1?haqZ+a{jpCXQkggJ%4>p5#ls#aLii z!=6?K>@M72y2IuXI44>nJt_^AyRc5YsHaG0w65w&mZ6S(hd~KzdR(3bPu3^a8v1fr z30QBKla=rhHW>!;6S2imJCyWq#0`LBpM#vm?wH zf){LQq@lN!C)t2ezQFNV#~J7JgiPrP_oeYh2x+Pr?}!$s^%Uup#&dd- z^JqMa#_L+ko?OH*=Q#{>Jh?M^!h7lKAL#8Y^HmMM3wnxdgT9vZB;V54Q|!gY1HQK9 z=xt&s@*#0E!;r4m?+M#R!u7x4dP8&Fi7>b5DY8kr-o7VUjw!^*oEMvPc!-PrIYm zu{}kG%YD=-JyoZoicFyKAA35v<-tQo?1fJ3Np7MsOHS%>d!Z7p`O|u8=#<9i^i;h{ z<6k%+=Q?A2fv>Cl`3@zauQPiRZ!~0&ps&9>e8O%LcA?78n2*!*oEVJ!aH!JiKErTUN_MZ4Ib^O zdKPcxMUKK_J)OVCVK;;i^(5b*B*&6RdfHf!I~T1z-cv(gH2!x_)ox>8ycsW>=bSMf z%P;7!zygy{qLyMEG@2J)>n*KlRkE&8WU$RKGamyq?zYdaAai@pmx( z!HjoCt)RD_PC3wT^&|)2ZGrvr3hIZ0@c?cFIMT#3*u*o@L`Q6`syDd?Z{=HFgEhTr zjvmawq&NH*N^&eI_PU$LLac`6-XeX`xT!Z8F&4%RG;VRmn9bKCzOc4i$%3!!zM>SZ|R5v72LhlRHo)KO5WbvAufLqTTOt zt%co&B3Cnv9zWV^kFcx1xT)f@(abn9)&FfVU$mQOM)aR^uG4PQf(b+ftA9o5^s z6p`dM#e|yDTV%Kl>sP%=ZXEXjctYB%7ea`=q!-RM&`)1$_J*TSsctqW*4n))44*p# zj^_0i*#aGH*qdyFI&PLPan|VIN_JrrbLPvp_%su4G1&LQ-tb8Jp3m*y`sRDZj-Izo zZ;_4C_s+e^dGvh-ySUVKF@YmL+`c!wkJd97*^bsl5973ZZ;@_!%J=R~CUwL5MUL0L zy}HdoWb-(h``cNB)-`<}Xy{8TOAj#&()fbjWO5IT1CHLsy-xN@q?7xpOALLt+qyK3ns%A@wOjh!uxZY6YpKSRChrTbHv*o{8DFmf>W^Qzd9Ij~j zs$Q(u+VW~%c#X9@q8GnA?JY7Sw*2?rqzXsyBo)?onYAa&cwX6X_2?oF#&C3tu!0*y|^I!^h}*eO~NOo9}ymg`a!%7TG9$ z|F<_8KOVl1;F!HN;QLGB+XKG4I0)|;ViDr-ziXJ2$t-=(Fpyu^$@dL)_+RY}m!Ofl zbs5O(7RYfp@hf_ZjF5qR)|=eUK-T5C{9@pee44($G!z*{{L0Xm^@v{^=HyJ`H->?{ z#_RW6Lk;BP-tbihvUmvs`J~rC&-=c&$OsvTj8FPkLm)F4NN#-kA!a^DBrp_d z93 zM%N8y?8(<0`yqxRKM@-ZeVNb7O@=vHOl&rUBmu{##SltsENwN6hWQ5 z0;0SE70ct@&2xK1+&;d@=o#h6@lHzXdiHp<86#06ag3qJ-NaQ5eR+sD)-WfJ6UP|_ z@^50dVJI&XdkiD_FR|B9qZ~F~HM??)F%%;#%FD5?jUQiR^o(-K_~bFX6)IMRQ_WbH zyNTn&Pf${~gj2K6tdD#fzwsYmRFy7R&lsPKf}!lg;hW{G@#JSRBbj5)a?;JxxejxB z{rzfuI1hGpOZW_Ly7_KFWb2JDvQaOZ81B}cTsje(oKhFKz=vj1;6oq3z(+W_0zb+J z1%4(E3;b*y75G6nF7Sh7zQ9j}Nr9i`3I%@bDi-*mr&Qplm#PA{#?=Mxq{;1ZhM9^Y8t4Z69&TWM>7x5V}W??4^yZ!=Ent^YN`suXyy=qhm0A6nq@JgmT_ za(ID@+K2)dr&S7EMn)ER4Ua1D0vcWWH_orp_U1=& zb}e3UU5>g7OgPt5`xYnV1b3{rz>_$>z>~3B?E}1Z&37deYFBc5w!qQqUgv&ndg1sS z$G^p84VoC#--eOKFO5cG>22Wq=kdS&#mYEK`SUOib>H=G4D_7lvCm+nHM>x>Ui~DT zhjX7rPl8|JIiv&+J<TOu%c-D_?=-KH4Go0gRh-PYhTsok6QR|3$0M)avx7V1?5G zv*_2kP82tnvsU&xi1pt^9WQtW56L9Rp+!Hq74Ff>5%3%xmRm%t8&F`e9dQY*c2cXY zpM;fH{tU*^aXIF{YknTaR`U=4X3f9CjTfBs96djRS9tytJ^v|p9qYe?&RhL+eq#Lv z@aY9HYQpm}4$Wn`*HO^E0x^`MD=Dd+bjjmA$lHmv}`inw7xdhMW zqQ5GXyz&mDYjX)4ObVhqlRNQd!~%@X{lhpCe%**W(ZoX|*gooX z^y~5A?2+F%Vknw_+8MQu*yT3Qd$xmP@3)WO@5Eo|;OX-#-sB*<1M29QSR10pFBU0! z({mL9e7Q~|Z$Als%F%7ZC*z7@G+uHG&R+Ct+h`mKk}3xLTH75Haq(%+hv=;)ZlO!b z$@tnNdS9X1tDb<`^>k9=%armkp6?HGY`OgdG?9-!-Wdf6a|=YDHSs;N8gQV#sG~*T zRj-bJ$_H~)zs&s#?@PPmrFrfP11IO3b8sNoT_@LGm_s-@SJT}OxkFLV{virRL_e=K z1%GJ8+&@twb(;aa+J{-ILF)Df1+`1=0U<%p8K8XaL8Kn3y9!jQ&Akko>Zn}1JsOE- zN!|S@Yp8vZQ)Ycv)~uO=qRpl59h9|es-S3lSJvgV^7nSLP*AlVUzXs-t9}zhSmMFz z0}yR#5#KRZt<1<=WgVI7tKS&DX+@}xB|lKfqAv{c&J50};^ z+Ev=wm!S3~p7PzKofY$5^*8jlD*f#)xgPWpBdhRNX=UjpV!J3=`!D+ZWvA)#fzJ+dkIG3)epA9MTSM7;RP5i&fP>K)@h%PEPt{z^68w3);1 zCCtncZ`Q1iymB9XZ=U;rCf8z7mUyc^nsC;|+Z6bo%dTdxDv|2>QjV}Ginqa)^o%$xscIIKg!SuaLJBKDn{>fe~ZReGmPgcRD5%1d0-j#ZpODo<@ZK{$w zE?~R2^M@Fw7F<>UvB<}!uaq?g`)Gn4@|B=v;76`C~*NxWaxc$Boe zQP^KE(JsAS>^=p-EIeu0fFZ~r~+ zfL-yC_v4Tou#@Xn;JueTaudqWt7}?|J!ihI_%90iWF>Bi@ojZuQBq2F;V3>-w=STZ zO#Toy&)4k%Xh@i%D}Jl)ctCUV?t_4pYSZqnvFFiB)qnW%4%@4qjn@(nR!`@=H@C$4fG-<=MFsm<##wRSa2@cQBdqt10-&3AlLj6BKgEMugQBg5(L>OjHQH@^vhll)I44bYiMc z%TL*79W=v)7Wt_a4w|RaG{0tr(=^a&nqRBJX`0s)oL^f@O35YkwN8chWu3G6X*Ha) z4LWD@(-ns3oXz(uG$!ZLW>yWyyE)ky_lx}O8n)A(?1L*gKS!Y}d59%*6-Fe7u?OpE z4@M{NVO7b`Qy7zMz-sdqR!x@C!2*S`$-OLDs4z}vVt)PlevDgpaw1DMQ0VDpcBuS@ z3cbl`820>Ph4IOTI4Suh3acf1ai}*^n2;RAGqSP5>UweIH`9x2qGt8UZ$6CI%oM%S z@>}V}wU$@SEpqu#`rJAf<7?UWRpBzqZ+AWie>NN5p~CZxS{LBD%I}yv3MJ!i!!9tt zN9Uh8T>6tq-OLqsdKQJj99(%`um(Of;LiCQKw;P1Eht!X8*D=hmugzIU)H)BM+(<8 zS9ZnOF3b(9%D=)co9jMc{t$pyeITloc)W5yA}ovvt0oOp8WYaZN|j@2|6NeE)j-jA zfffxp1nD3OKLk41US)08J29v_dZ6Bk!A!bv^^m%j)7PtPhprXw%~f4DQ19McKkJPe zqNxmD%C&QOM$K`oc|@-2p93|Ia5cTr{TRjFa-X1J74EI}%yn`C4$^o*<`TdzDo%+ zm~*VKt>49^cnEWj6?XJ>dU<0SI4E6y9k(V;(-8|ZPvO8cu875VZvzbVr*W|>&cQ-l z80Jso!d1k+$tw)^r*Q_kaazT9<23X?IQj1j9j-s%@O|l{LsxT!Xw6YW-aQr`@uc!_ zc*G~FDOk^+RKsHj44;VOSr6`qtWx#&4BPdhK((1&1lp_;uoV0NL*QZr3Kd6CTG za$4lAyKu40;<8#~>a4;gGK4uUtd5tr6Z>TkmVe>)8xkX_Q2*M`H{TJz$8nzLQaBKO~g zIntM%i@DOLVQ?ubtSf!I5oyZ{)0TgSvpZb z;BTDyTl-HOv?q$}R{soq`qiO%Lj4WXN&LjNoWmpa!g*59@<^S}FY9!+Gma+-?u@T9 z&1FO3_H}Fcvur3UIcmc-8_J34(fg*1oixm}NH?9#Rl@n( z-u!94lU36iv-?=X8{WlyC-c*zeQRnf8h_s$^*n|dN{Yx(!uq?T;t*yiDI!A&f6D9q ziWy2u$WT&w>R7C?uS?s>s8f8+!2})6F<+7HlTOmLbis5br3dVHztfn>q=ZZ+EOtf6 zWTKYdKhD521MGtPF^~H+lgT&jE|bY;o8cbgGMTiyOeXCvlS#YFWKvgEz#gKfd3`vo z;euSAjhA+p#H7xWnEaZBo3L;P7P|Z;bt}4HIkDwr7VgW!<$U40c9*}T-Q_Qt?DCi3 z;KL{za@SmJ;DSr>)}MC(1}oJ3C86do2{nI7sQF7m&0iAki|S#h`Afp~ZDAT}{t|qd zhshIa{*rL_MHtIa^OuC0za-TBC86do2^TIvSfS=G2{nI7sQF7m&0i8~{*qAhmxP+X zB-H#Rq2@0MHGfH{`Ab60UlKlswko0KF9|h&NvQctLd{mqadqN#ydEL@s|xg^Cg^Cmqadq zN#ydEL@s|xmqadqN#ydEL@s|xmqadqN#ydEL@s|xmqadqN#ydEL@s|xmqadqNs{I-Nz(i!Nt(YTN%NN^ zY5tN#Fbd3HlBD@dk_lK(n7<@R^Oq#cP>1Ce@T+&FGK5NQ3g1C^l5P{3QfwuD1LoB)_HFCCm)hdw_@RC9L4Jq}fZ@ zhjE&{?JI_x0GftQ9CK6*-O+=N@?~I zwUknty+lo=lx8ncTd04rQDiSsTfdZMFHu{+lx8ncTYpNLz2rH@n=6f}fi1F^ybSy_ zDD6r__LAi&MD~(e{!2d%-1gLXHSBUN$K%25U@bRZbhj!ieS+UIu~2J$m>xy;l9n`k z$*mZ`+M`i5j~$#k#;5;pQL}~z^hJwDrNwwK+Qbqb(30tC37!Y7#u6UTm+=jwFpDbM zcE;FWh}2@gQ1WNBOS9^O@Nf?qA{*4EBA@kr+3_pvPOZYXlWcfdUieYxd7 zz+W5YgvxflMVHZy3sS;vWnnnM*vyFqTEc z(+u;nG4V{pM3%e@Jln7!TN2MTEXt0=3k*xL2k~OVD%qEKnPIgYO1#prMvfw0V_23G ziPsv|%IU-#4C~}v;!TG2azF7_!v@*oCEy)~L*$<_^F^r{}xRGIA8i*SkCh{mJ_$G!0d5XBH zVNqTnZf01L*NB@NR>?cWEexyWBjT2ZHSz^~ypT?|`gbK+9NHrbB2t6{s$ zeHpl$VTbI=(%lU!vOjSTL!AwC+QW%B)&8;%Ja66hrsW>q-;6o)>-HjN31`E;?a3|m zm;k?e3~RPtmj@c=`Sornh-`ZAYzkYP?vB_3=T$nS}V7>4pR@leA^?jRm!7)#%q zz{3sm(nDNsn8@Ql0*^2($b-bA42vS40*^5)$#7~6ortFy4v{^GryDlPKEyK&o8$)ms`5{U zdXn~P4_~UsiTNCt?B4C}cD?`?)LHFCo;;qU3)+({hTtS^^cjpVGGkBX6E8LtIe>VH zp)bpbmm22eM&f0Lfm}_z+%S}PiB}j#@+$F4!&u(^0eF>RUS1kNzXBhTm!h9&ucc%xyJEW+9p-fUPcbBMPZ*2rBPtlJIC@*wdJLu4)?{@t)no*~|8 zST8RT?=ozVH;8u|4w3hW_ZT+HO5(kSO){5wzoDL_Keva6;|%zB;eq>kc9Jf|nSG$W z$dkvD^w0LB(u9*V2{+&HaWnR09PtT5kzI-ZGW2Cz;**9sxsUjiVIa2=pEeBTCE_!N zkvv8Gw_z;PxHvp(n3pNU=M58i_Iu!qh6QPJYG8?-|z1Y~uTd4YGjvf#DEYLR?|kC|eLe zG;ES7+$VqJFxM;zr`<{`ZIk_%0>3cSQ}}RuI34H5e{zNA{liY-^KkiPdy%J>r|^gN zS9Yvlzo}`f-$nQT%@g!~7;WDVSVdoJpF<+k45jQdvS&z7hp)b>kn;Pb1C*tOYfow_K!Z4J_h+7#( zawBnT!&tuJE@NB6yqw6jVtd0x&in=e|274G* z%c{g>hBfjz8`{gTEZ-4-V~D52th~2joy5d_4C|$uxUXS@3?c4kI7Hfs`x`dOaN+@m zO}um#bZ90Me~V&He8#<`OS5tdm8= ziw)~#W8x)-4YC#SQo|v#Bk?lBM%kTsxuKqwLp#D-J8*sMhTa@*XXS3(b*}6vYDN*9 zmFqf^xfMJ!n!z7R-C)LeSi|-GM#H?U!Ik7D!$gk!9C))szaSHMZ@k4yu@&Yzdz)cR z^#c6l>UKwX5}a^S{@t)iwqo5o9r|sYN!N6QyCWd~CY+zYTFmp&-rXHV_JuR);f~~E z#=H?c|HIlL;b+2+8j4JN1)d)>&t*CCRp8@RS|^tgpD?VKS9rRgvdVab!VCCmD{Ynk z5}z^DAn)r4%bf`F0L+UAEXdpO{<)4KgJ+PhbR=WCFx?k&uDs@q@fG=YShm8~%~vQ_ zaXa&tVI<$Y27KEvu3j{K7Pd2nxFvI$dDo$z$m#r;_@0#()x4|K#TGGsC9pMg0ilbHipig13e*9QrM?_8Y)2t+Y*U z<;Z?#*dgn(-S4e(g(vvMj&ME(#@`zuyli9lJA5wup`*w#<=FX^WaFV2yEE9~u+qL9 zhp{C&hZq|sase?hEXbwAqG3_4B32oeVv}K=RC7kR7}i(M*$_`(+a3DN@+r?~#Y)>H;8f}~?2vk5mtjTj=4Ce2 zQ1^{LcZ3IFB>W;OdX;8|>#zO>{&uBO^AhJ zOzbht$q-_%VIZx<@rI%NftS*1hLM~`oM0Hsu3Si0uc$0`E-zxQQX|D;%B89QtLsfVjC~UG@6-b<-9` z4RQtN*_LM7DD${RZDXa)atrUlJ6LI}Y{1f;th8P3Wa+L}s+Zk*mGA-d&2Po^Ip4aU z#~ow$N|D3D?(b7cb{v7Bj=A{nXU3kK_5*N#L;RMPr3V-yBQ)_q!TLf8@NlbKl1GTk4Xe3yEUSdaB0zsOX5e1dhaa%c9Z@N= zZ|uWyxEk1pk9obH;EcQQ4OtK#jq^`qmKUxcy=XRNM|hh zvqf_BJDzu8rAQZyB^lDtXdb$C79J=plRN*IoWF-z_+ zO5;Z=NhhkvEic0O(ZR;|SHgZ8v*bZDeim!vKPyE#rSUVBWJ?-vfVD1scChgimGHMT zX33LgJRWoB`AU&aY5Zy>Ih)3_8TRXgjbEySchZ<8|1sm4_~`parAVhVe!r4DPvd(S z_KLyAZ&kwYXv~s#%(xnt+J}`QoznP=N>V=x##=D#uLc{htb~0i@mcbz8FwLyZz@GP zrSZ>|2Sy_Y5{3-HDW*FlNcBX1pgZir&s5ozi%6XL2pxRxe(JpPH}HsW%c| z`#hl&2_a#8+_#=Lu~TLL{4cTIuGv|nQyS0cOg_Y0spBncmTOtmc%4pU7ld&cCDW|s zZLpHe=`7MIjTdz$8=;C+ar?7@GsX{H=b*W8vH8N+4=ml-O3U&yM|V>z)h80`b%qDB zrT_jHi?+4&5Khe&okd2#mUie&K4ME(bCup{pry~bquIqF(pjAR5pdT|y-5cp*&k;p z+-;!YR!-etTjd5hjn~jJ!)95P1F)yrwsR@nx-+a<6=8K@?cLVG+8+1ry*i5wmth^) znfwt|Bw~*bcD{0+{E<-}W*A6`rOOTTQb#<}5Z|}qY=*}emZh1c#~C)r7~+YB%`%*L zlA%VqPiJ^Dqx=Aax1U9MGA@u)I*W{+QJ&SAyv8WEdjrPjm@&RGC!S{*u*au$hB6ku zK8LR}%vTFO_FULmWE=E#WoNPpIief5B^V~KxFeaVHqsb6oHm!-Tp+-O*qy@7#QS?Xiwu`xJ<^%H&aiIfzT{Ce#>ejW zfsZ+i0{Mv3{y4O>HTH84T1!vj>C@AlMMl7uUhGV!qKY)V z1LK#SG1juh?*U&i%*#UJYYt0gx_-7Z+={MuKjU`ki4cza{=)n3rRT zKN%+M!`q$V&~Egh599c*^+GdKp+W6uF7> zqhyG*46Iybn3Eq_T4R`(TH2Nk6Sq1I9^l&8?sjg;5@1KlouC=Skp0kI;x{|5A=+wr%U5zkfPqrkEG!$9* zE^xG=FU_3PV+?cBNgQh!$o91DHVox%UgYB)`gv*o8aTnQAdleU3@2ITD)|?2vSGEn z&K^!REXzB@wG3;e$e~=vuuk^l?Pi)`y&OvHH*An$9NC$ML!^}#&m6;MIgE?zT*DT* z8cR;Nu0y|7t|zW%s26diE8Ggh=6{Mtx@=@u#bq|XtH=@O$S&?mj^W52g#|a<$Qk2d z!u7;W4E0)C)P)Q!@KwU~vw`_~4WqOf<{^&L*Y=o)UIevghO4-^NDv&JXbMp{vLd_kvHu?c0(~Ct%aXKf>~2{tZ+R z^KW1BG5_YF6!W|8a?CGN8)AN2*BtW;pZ1vFD0IclnL8rpBht|^AIXi2`H*XTJf;g< zl$g&$ro{Z9zgEo8sMBJ8RGS&|!_M58pIYX}{J61W%+C!=V}1bGBj!$iub5l%ePiye z4~)4rpZHpTCc}H#{-sChwG(yS39}ZoAHkxqmu0=0@nkm^+$FW9~Mt zjCphaOU#?+^)YXIH^scm+!pf=aA#iiNZ#zMA6LNNNXA^cpNhHoJ)2iilJ>6pDwMn! zbGdjU=G1;W&p(|Ex9F-r8iV(K%qjYj*HX=yby8Q3Lm#N}*m)S?|DEz!PL;>*g`K~{ zPH;E0iGR}PoAMZsd$l{^^(p+XAKz-&6qLvEtD~uJsb{hur46)Y`IkRXx-VlEgN6)Jn=H;ecfD;T88NnW|Zdj0oES+drl*j3Ll3_`f zv2vebm0Zn+rWn>h6(}4&G#rc0`72NYh88(4>_3#p@_p#? z*L1zjP)!Vp{(nQ<)==am2ECo3FDJ3#?G1A>jktqhAY+I-8AkFcZFe?|%#_Cz zGvzVGOnFQ(Qyx>yl*be^%#_CzGvzVGHra(2$C*Rh6*J{A#Y}ljF;gB>)TgXa9$OXX);Hxb7Wk$-#%aOR z59P7#dHPf3F*U~J&zW_(HJmArX(?n|Re9`ay7n>WE*k1~ptJD)nxRED$weE=W6VhM z|D!yHRT|1;Pt(^RrBELGkiO>f0(jV6;t4+gtMXX&8ZbWn5aidf zCC-$`=#+hg@>n0L3@DGW7YTkdfd{!R}5W^{Eu`tjt@X8u{ZZ^~ml?$xrP zUGcx(m}0ty^4NtqFrYj($TgJ5NKzh99#d@gR$DHw480##{^nQ;UK`r{4Bu~v_s|`C z0q@;kwezSpw2fE8+O=%?z3kw)<W-a)N)u5D(`%ZPQr$6D>X%ZgJ9a#pn<+)EI~Pik^Y2nArMhGD;NeOsa_ZbGrT?ir zR!Vip=o!ctBsY_~^8_(JSxA5*}zt#m9K= zwAx?NYOz;7m(_RxlL@k97p;wxmdcVXM@YC8ZBc_rAxoy1$&x8%vSf;xESX|3AWNp0 z$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={ikU2#VkS$bn8}hUX0l|8 znJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={in=mGmh3^C zYTsnZSm2v1*)5n1oDGmAV-}17Su!>D24u+;Gg&glOqNVBlOe#Y~n=F_R@z%w)+FGg&glOqNVBlOe#Y~n=QD*~W$)3Tf_V2@$4p}l5 z_$EunS;E->S+cvPV>YC+WNPdU$dV~$vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+ zDQ2={ikU2#VkS$bn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|_=ukR?;h zWXTjWSu({;mQ1k)$#k(KLzYZ2lOvX^FIHl(s-YU~Zjk|}1gWQv(AnPMhOrkKf+DQ2={ikU2#VkS$b zn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={ zikU2#VkS$bn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESaLt2FQ~Ah*Rya(xtLwEbvX1 zjI)Fvl^{#D;cU!?RF({%n7E7lOAc!TWXTjWSu({;mP|2|B_r~urYcLeAH4ccVY>`j zG8XtIOU8iskr1+E$D>Lk=VBv6@B)=3yAf|=Zfw1n8=4^IjVvE?0V~CHTJ~B}Su#36 zA6}c3e1Lb=i>NO4-%0MFT(wNavG7epeZcYZq_8vxp=^rJ8?Q`q54d*6`?n?)??q)^ z9Uo0fzL|?5&|US)N$FatyXsF2ZCCxNq3xyhoMeM8$-2Zpw*jtp&Aoj0^yb-~bf z)g?pQRaYC@uDWb!yXrba+f_Fh+OE3M(00|$hPJD2HMCuIyP@r>D~7hK?lQDp^)N%d zI^LfYwyulWz+LroRNX%V@^X_5%hl@=CmS|b&nB*6sNX4#>I<1m$G>Kb=Z)!eVVw+@YxWfxE}xb3 z_a%?vZS_Vpp4F!hxRGre4@cJN3s=(kgUR?r-PgoP?Vo`M@N@c#bV}nzeVPbFc3_wr zm@zI%3Fq~N%w6JNf~#+V8UMVN=Pm9l(kU;sE&7rjP({Y#8GpD{pS!X>88#KTjYA1! zJe~}M+c}JMLD-}(Jch21#&d?v`rMVb>R8X)rLV{)8P~GD6OFp8pwtR>)#-&myO5@x5k`7dn5I(~@ z1{>eh7fz$`)A*oyiy6OwT6gvp>6FF~^d+0)tz3!Rr$$e(L;S|q% zq_0S)oKgSkOa4UTU)F)~Q*O=_aoYXxpMBvSG(HT*kK3GiZ>;D2yRS&6Z29HBL>9pK zbxycf`ces#eh$GKhB>)v8t_fSP%hxaf6GuO#q)jP2)OZQ!0yF96-4m=i;Li$z9J)F zOCR?oTe79;m@DBYu8&v=?i>gF%rKA-VHAFDBcR_Yeb5*Fmag~4@O@|_a4b&m7kx!G zN!Q=^C0EjQCnxKV&N#pyU*J*+e;(}X>%Q^V7$Y0whB3w%Fx`z3AjX(L=)qtJAp`?~gaDxzLkQIn0)!SqOCUgK0YXTqq5j_Y z%*@?g+4;WjdH(->95EY6r&|lGcghqdr{wO@|aoy*ks$-;?!T2w`t@zFs5K-UlT96Lje?dcB1Xj!lPT zO5*Nxa@?LEF2nJfm$k&IlZs5%U`(lhaU7?Z*0>rAeqNse#e5Uf-dwPWEr-WsjHFcv zubt8%HK3#!>Eub2v>ZnAW@=)1%sM1guRovHw6u36d7S_$yBS_TYR4sjbVwQGwIH3m zhrIqyz4kH0k{kCEuM9sLMJ*yjl|nBKe54w}8YCW2!mI5Wfkmyx`k0kyz`h1Qd z{uI7@K{_N;5?`7w{s)PVVtihf9*VBxyq3OuaXMKx3&i)JpOdtgXHYC13U3?dbr?W2)=Bsm0I?1mti~Sh`ey>qy z3Ibw{CK+fGZNoT$$!Wv{#`m*HygwcjdGmd8)6TJcq&~=rtHhzX|EF~)f8V% zHsttHx_BBY)$3!x@z41j|CCN1MvjLev6Tg;D zUPI!4!dKof#E+rJ@1{%1lEzhGK>Uj2T1%{sf*Cv~qq8R-$RrZ*&?byX%A&H?KW5p>mt z^~>;!#!M+i(!^fIYXV9&Rj;NH%4^Fc=c7`!!nM41O^8f(BwcD`WThVXk+*%mm0B|1 z36%FF2D>$*=a_$C{_Mzv6hhV$GR3!&^@m(QrlYQ0O-Wr*S6-v%cjtFyOeXm}Sua7$ zIMbCE5r{pRQi>$&zD#k+-eA3$)7Q?L7pB#Z$!luFx{Bbg29yDqoJo!WUF;M%RIg#Z z7=t)1Q%aGv(x{9#6)4qIy_!NOZ+515E#)0XZ<(Vx!b+#X`@Ff4ydU%eoR{B~nVIAj zly@4&tKZ1G0_K>XDWwpy-Y--95?LS0No)Uz^+@{C0TJs2Cx>PEtoO+zzb5NH!0Y!l ztb1XO12d%*$*#=Ec;$1^3#wjCA(VGSCOI9IYC3g4N)w_hKG!}gH3;7w$N6_v{(v8n z@eT)FY#PGiFf-u40*}?1kV3elIx&;HimYSI9&0mpe_cfIBm*i{O>mt7)Sx#{VZa=FTu+U7*oIFcx*CYTAH-!Upj~y7* z#Butq0pn^JGtj*Tbk#_<-e*8hjVE}&0ev-@-~$FssA&WrG+>}+6MV>kNma${zQusJ z*+E-AY`{>xGXdZu1}swlCipu87OQUvK59UGJf4RCy#Y(r5^{drfaR(h=Jozyz-rY@ z@F@evfU@!bYsPzryomU^8Q~^mqQ7TC${??g zGD)=%yzW9a@cyldW8xkkWV}|i#LCd}p&@=9+JBM>$&|!jWs-Z4cqW7X8%wPCqcGlg z8NKlmMLy4XE6A%4o%)aAH3TMCT_I(VSF$U4CV9;#ao8o(tSgFmUEZ%r+=2y7qD#*h z&w){KS4gHL9@LfO_ui^B=ja+utmpgkF7G`OpVj3!m4^6o5Z8BwWJ=p~8qkaOu8=ag!x__+e1W{K>jv?-E`92VlT(5d z4XD(gIV)xi7*kKs+jWU1`O3cO!rd_SfqBR4@@&) zvD%-lyBSbUJ9p^vzGNR>ghr#f^j4}0fwOy8$iC4YbGnjMi_nMlH0E4u56%nyU0xb3 zu^(e3W*Y<4z_1ItLNX=s{$0r>Bz~F12UuctAi)C-D5+~vmv;(zO-JV!8(zObay+Oj zqzv*psw;Utd3`|Qm6{kIx>?OEu*&elJfOV8y1b{z>oBw&VR$vc#%sDl${?>3x{_a@ zShDjj_+0$=tzIR2>^T#g5Hra5R#xR5+vN@37rct0*Y^ys;ppQjT_I(V*O^_(oq?kD zI=fJ>bMo~%t;;)@ysp4>ce>#<1FM)Hb%m5cUKe#G&qGn`b#b9ym*(qrewTMEd39s_ zHyU26ki;(Q3Mqrx`j=hFlNUp;?I*!Nzv{Bn=sbGNbq0*7o!NT50pn^9g1Qo$odShH3@D+YMNxP9}J#0n5~x z1UDP7oX-NT?DDQ!j1K=1qkmOb?K<=^HW9h#?yiuAV22;pSwyagS_78D!wA(^=2Wjw=6H+ zr?(9#i=S7!l3U375=oWtI(fZtg<>~?s-WLYMcVQCzj{z&yh$#TSG$6k3j^I}Y9HhDk zer>>N)kp9f1Im|Pe9+}x4}D|Hu_*u049DW}IN<6E**SJ8=uQq@iY{&D4k6WT9e+~> zV37fpngZwXN(>lN&k(uHfN}LA!3qPqYATVd4Ctwk*;;KtUwuii)_@76xVo=5V4$Wl zh8hf*RPXlyY&2j>eN3>)fT8+|V2c5ZRGjYEYQSO@5^OVIiK-;nZopDCnBYhQmZ@O` zI}BK^_-j*MrvWR}L7dM<8?aIh<^Yd1V3it1aDoAA)p&v#1J_u&Fyx1PX;!G^QDLn_3ax}ZDxF$MDz4BkH7vXsEQ@hYd; zeKm-k%9osG7aLHfq`kYn>I1-ops4q`ZdHcPv7>qz)TbIysY4kbrx_57RSN#00psdo3O?O{_;p=+;u!|?R2f;F zX+U2k81iQsP_$gz?eP+S>``dB&S?1n%yM>jNbRZR1>MO{spV~4^j~O*9rZKX<01np zHJ@7k*nkLmt{g5lU|c!KBHm97DC^W8b$hi3Lhuz3w!sK4hwuNiJETGsd}ViXKcJ}l zm;$ac#E$BwS6^*FrM|~5{=$GURYgzyr2*qyW?a_ot*4}4LDJ<$(#|_M&ab*dYCuUh zbtk=pAn7-Bms=u9Df-8)k)$NMcv~c?l^sTHXv^3 zaMbQHpbW(I-CjFXh&_h^yuoOBEBbPGcS!B2!{`D9OH)!v7`EEfGq}8YAFRj zY`~ZrN5PL6Fs?4A;NKb0RezZZ@KFPLs+O#NZ$MvNL`y$rK+*EI-QJVbat%E8KBMK+ z*vLNK9a4L0`D}Nx^82`zDO6^ZuK5xL7dWr7xf&t^or@OppKyjBR zyFGsPBK8jY{yy35}TF>VsD6K@(&sYz7pEd$0>1Ks6q z1B$!6((T<$N&keTzZyyRLA`goLux=t|LjhVUk*vb*r$I*lHTDN!oMR)3+O!`N0N@? zsC{B3sizTe-lqn1)ikpD%z&Ocm>J=71N!PNj>{JYl!17^+nWa!VsF5X|1esP!rJ#g z-66H7mQGLdhrpIUWooK4#5g8w2Uul5rAlN`U_fz*;vR24 z=whFMb!m^DK^DWgYkNY9Bq-2(Xf(VgA)JTz zgp@&E9X-i=$?IB;u9{pa;KH8bs>7{-A4dXq?}fadXfW=PdIMYrh_ScPs|$>Pb79+`_LPz`PfSWV@s$&~_b?n!=y zV##bA9C){CLTtSj(Ti_0pi*CL5Ab#a#?)B4$DKxs3tCKjrqM5%jU#}&3?z2^b&uD0 z1XMc!&T*p|->+fQyL&?FLoFUa6az(T@sJ@lT5K_((c)nP8ZCaO!I;+KQPZfk_`QKd zi{B#tsl`u_K<_hJOof3S>j|kHwfH0AA4PS-4(Q&W46&H*NyI;iFM=yQZHONR@e7E5 zL;NZXN#Y(RkJoz4H3{1NW%U0@5Wj=i|4Wa)`EWjn-#`o-;=lJKGeA){GqT>#m;6?b zw-1R=M|8hqB##ExKcF`1srKhR#rKhTJ&FHgoWfDZaTV~T0hKBT1Mh1Cy2@qiHwN@d zrtXDvoNo>2m-OSS1HUtnSnuPWnISnXksPA4O#EEByNH_jfOY_ zMy=V9OiA3CO};?lbLsb^^NB}hy)Q{T9mE}mxC>cnY&IlQ5_e^jRVzTeumi+B`D#zd zdTF%8HX@;?4e=060h6*JnUZ*FHaUyLhwlL5Y59`-vfdgJkAr=8HpCs6&vwg(WJ==M z+2pw-u4C4mqlp9Q^USPwGl{2QGVC|Rw_~xgARCe?iI--RFO!&`aQ6;0lJSibTmc_! zdLb!yan}2WynY0CSYmkf!34{*A!U%)QQ72#mEbjwOYfDo7i#1vfU69s)Y)uZlg&FJ zJ}m3a2VJZk!*PURJ(QU}8&V`$e?ObV56U{~3%c1!mNk9ods**75YA=^7?T$`4xHH zNFVu$mV5FdasywDJrjYOKyhGa_OpJ$V6fTG4y@-M7pbp_XtzcgS>Wsx+z zYYZ4y!?{}cl>uE<&hWq1fHJ>q%6dPh;61?R3M2Sr4CnRPkP1=ot=Z&1DEJi;-)@K< zm7+E8G+<1Ph6%mR28=6yO3=H@fUfFi9N%p~5qx9TD_af0f5KkxW+Qla^!T1^NQEf) zp=|OXpr~=OlQG1OdV{s=w{ zrEEx%Wc^w;IeiUS9}Um&-iTOFpt=4QvHlxd-?Xe%C$rgG2E^yX*!s2sU9|_z^Ns=0Rq}{4JfAmI_vETI{f4pb`*y7J5b)A6jCHv7f(vwM%ItBi=`3k zpR$W(5$mhi#d6D9ZI5i{RTwa?Cb5f^26WW|cCpHU(#7N??*-~{!UV?&C+TVBAz)Qc z3aKCU7&0mOFY0j>L$k@UX4KbB@~Vyj@sHqVgAMVuh=-O*A(@i6V^XpcC~Czx5O-?g zz;VVP;Z5o%EgMEos@b3A6QJ$bN#Q{#>mS}?t^5|*cla$bqL)+Nv3a!}PQrVB!rxBB z-G2GTkryXaZcc$b!JGU=`nyKnnjoJSF45mF^7e$vTY*uQ;QjoD1n*@xC3p?GHQ<$LQ6a1OOwtzp$=IyQPMkIJ?xjn)A#Um5ED7<~ZA7%5_O_c8}=}7Rx@94xq zcpsDC72L4_f0oU=dSWF2XI!v*2qbE&Rm-o{(XUbjJYl?y6v3cJ<4eb zUU}RtkWVy^PfJgCPw*z=j6gotyh~a%-6N2XGf&l=W+r$8u|JT{H1DOUW+ix&aCU-M z0{6lVQS|H3bma{xe9cABN9ZukX-Q&YzvJwmSdI6k0e^wcJ6*RN5X>ju8R^OjP%TUF zmfqnB-itdT!CP)eCU~#xs06Qbtw`{4*2-X511LVzTCGa(&efU(?;;(Y;LW0A61;J9 zY=W0nj!W?B$@hXzQXHKTiyR+x5jrMQ`71~~F~J)orw2Q;?gtsM(%HeDgih7?=OuU% z&vDO6%-r(4n;0=ijgN4MtMPpx-;KhfFgJNR8qU$bA@Ui=42|h62l;D%^ z%Y$0B$Ge2v6$w7UzA_lby3($SXQ9{66MQgzb@1>=)HQTfu0-805`5l#ZEz#;Ms~>< zT^HO+-J3FHUrvH$y%+ygy#_H7oDw z67y||hkUyBXguU|rYGXz8A~8BUX;Lw#8cgsmymrtd+)$3t-H?ajF*oFCbKDJioa?$F4_7@mQCs4MJRT`^LmqULxgn1o%H1Ld z%L{LgMy+r|o+nhgMImbs>=BKt+>m?!YUqf6HEzhQYOPyTO`PjAWt|&xBU%qxM<8Rm zMa^t{LN_)*G-`(c2mcz~kh`U!Zcztu{@GJ`a}N@g8**FG>xSGV?C2Jy*;tN>rn*H72)1V{E546>;D%iFuX97L-%oanZtO(k6pg#y zExMavZ?^J64ABqVkn8mG+@kg5Fe595+W;G*_I$VK9Mi@|-?|~^=X>3dbLo9<$f@jpXvf7*>m)JJ15kwE z@JTvqpaH?QNtMeGSX*FoOgN6GzeeF>_`ZBi!yQf;r=3z($QLXW!=BPo?38`O7FN{F zrjw1I6z8PX5V(^S61$5ZH*Z5>P!*=sgz5)(|F0{6jYm9`)Q@V{>qj~8dhlN4y*CEl z=p6|Y)OyRuf|FD6&p4=9pyjVw8Oh#9QQ)U75E+;pM{1&_xw3h z^UynqIqzGlIStZqoc?ci?o=oq_l|v;hFy+&++%|Qe5Yd0myq_o_zC3mZDl0!#MjBE zvX&BKLq+1{_&xjNy7)uHtbq-UZl~;c5^(PQm=d4CJ1!^VJ?4Fm_qf;i86|!n@1FN3 zO7wPo6Qtg-k2tuO!jMVtD0DdGRNRBAMT?z$*DuW6p}Bp=|Qf_#U8XE(2PS+;ki1FGA8wUQtOBr*ii@09;u~d%8}= zCG{ZrdHfube1masO8#Qcb--HpS72RJL0dXn%CBp+$f4+X@`hUWIjGzM_ekC-Ek%_Z z(7WUGtvHrSQc zDpM7g0%{0Gya2>{RdFAnrl6To)2b@o0Mr_!5m3o7s=`~36$j)fg2 zkzpU-X5h`Kna(boN&TOdFt*6-5 z+oRUIQF3bNU}dbVxx%8n7@@o(DDDD0M&v1}bmX((U2A4*QmJ3y%$Tmw60 zRs48Vm8F0?=<5I2a7m4tj|%UmzXIEP5bw%6@mq$=34dXre2!oZyv*k;pNXgroQl~P zgH$HoKt505iwtzwrFu>zpJf>OUT4sgh-g#4<0Y*B3AkZR0I^6F$A5$P+9ghcGPVxd z7jhHsRX|BiUyW4hwPVn62brmU)-Fj&b(>37lT#JHuD?r;a|-E3SREG{+Z~36ZpS}2RLQ^8}L=9$!{V`um1$X-C39Xm~Buj>9W;{ zImtm%aGhkE6apuimO`16oF;`PWJf9VI>|$&unv)M2V|u#j9-U7HGd9OW2uXOf$mfm zvHp@lEIXAo-vRjPAa-0i4JtOg2$W}_GpS4CCjn!Uo4P7_$Pcjc`0YE6^Gk*~eopMq z5b`UQl|Q5miRoG?C&nJN|AEeREC)jdA#+~OVk|l2P+0T^K`9=x2Pv<^1eUk3 z?3E399_G4DaH@w~{DtG(F6ElBM=d?jxr61}A=kt9cd{6(8*&D0c9)Qo@L{vGVSmX}D| z3@40vyQ1uRQ@{tl8-hjZPw_WNI}3aa?TfpScKs)$eF+?Jrw`?rcP-vA1K)?9r(TUW z0cp^K@Lfao`Z`j*kEp=v2+Z&q5H!ZTv!FS0`JMQedM7@YRG&i$L-pPrqeGO8 z&|B1MIUHMgU%=s%w+8*fPldPB`vMjJ0A$;LjJkdxhUx$kJ%$YGcyHky=O`GVm^T>j zac?5tU2hiNJ@0V5``!=no^a}>&}#>&_%Kj!zy3qb3}2H%X4lE8<_owgp2fn`FzF(T zcuw6e|f5lBtcpjn;pL$p3AD~c1*Z{^*CJQMTgBE!VJ)6rMgD@MNe@cSZI zXL&nT!#3Vu;BkR>GS&l0??=o__`yTvgx-O`FY=zmf~6Qg-lCimF9!Tl?^tjs!#Bq( zr`+2OqAR>(A+ge%gZe6O5b6hcUjVb(>qC8w*9She-bcW!!|&=Ur`{WZ@?ftRoEyCB zq1zDr%&~GBz1N}hP;UcTo1D7az#_G?ieJqx{tLM5;;!l{cJXL{IQ4@-Fuei#r*>EI z)6ufSRbM+!(@fQQI$V|0W~yJ+tpTAE+;|S4S*niHkQ@B`SwOQ@ogfBF;Yq2zG-grI z152mos5&kV%L2~rskur|?!lsG0L@cF7Oq2R2V4}U=Bpu`>l>UJeoJoM*BqJ!Dtv_R1{qHGN1!BR2EzhS4kbDp{igqBk5q(OwXhpJ}A*x=wzB$Cu&8ftLrRxykZSMgpLxQyM}p&eOr z^iituOz1O;imz1Fzh=$~7E_&78j1z)A(y9Ct7^_oZtyTtacYf*f}oOZM{B4kNRrDj z8Y&Amfq&{)4OIn)GW1SR735MIw7muBBn>qLO{80|>X`tWf;}nyR1Gx;&wLB$he{T2 zEkT-QJ6%J=f`0NmL&;jMHTWgl&eYKG;5kY^OSQ6l?ZH?Y<80N+G~D6TG@}1?f2Z-z zLHq)katNLFLRDXbiD}S&2qv9S!d>jKpc|z584JFf-P%HLOPy0?r%VDPYh;*Q!|d^%i@IJg7_nU z!dV9WQ$G*=D__vt2OqlvxlCp)Z10yN1%$uzi;n?KF}F$prchIn_e4H}XElQqm-FGD zeBJkX#EQJR5{e1*qudGPRgX2>|>40z;PK>>D1a^++9n!3>uhrP@YOsXaB9 zoykQEwx>V!TPT*g14A3m_GJ%|T91Jb=h)u7z!CY%EB(xJIYj$*jmvaT%0479$xJYhb&_L8tXE_hlqfm2{y7 zzeJWy?WtF()p*^85vI!xJ%}9M^NOorkyd)cd)}xwk&%i|y&0;#=S`vp#Y}SmW^zaF z41J6?ddVy9v@|byBbmjVp$jBfFYn zB!^2qiRA6xhlZ)Qk)gw9@N?bJ-P!J2R-MJZjrX)CZ&yw&u3**fUbV(*WtGEz&N5Z) zsROCaVTQ=58Aik2LZz;Di;s-@d$rr0>+jX>fzsc#WPZEumD4ty4!6OTz2`X*;RbgW z37w&5vH4`T>h`GVWOs(}{1+{?-kl*j?)Vb%THKI(vidA+@UJ+FLw*F)OEmo}z5{nz zI^;i&OAHS_aMdd3llWj_>S6dgu7^Pkr(7`{13fhA)_(}r4+!fc$@-K(!JH4ovt(V& zSu=bvo?W&MfcVct@htaL#hgLIE%EGrXi14Wk7x~?`c8zvSYdc`r0dxDPQox?_>GJ2 z#QDE?EuCR}d?&7VBvvNGC5W8*cIZ?gEQ-$qqVTVXXN1MYv{Gd}!)0Lc4jiDWc!nm^ zhNw1%Ko=Y0+O-}h($IJvc{w#u*r~q?5%Z52t+XT(@Q>I83J^{H5!;QMLCx}?F>PD0 z{4}Onii3Wx0jK^r4ArB;?S_ckqp|T3w?|{sbKD-waeF$S+q0J2@lf{$;r3C)?S|M` z>AYmv8)7=8Nb0&N$L>zcVLCi}gK!wJ!J2PFY>aUD{T2+|hFJeAk?UNbIXLxGF>r?p z*>Mrsp|Mdy=06XzLt``Uj>rzzWGRW_HKr##_6d)+dc2Oc%NL4PPM&Y|_(F+Ybk_Vr z?ar7GlYgO(U^#UbN9!v!I5(tUE3tp-WTrXnBqeJ~Rw$22R-iu*G8#x8snb9^z7GT> zjWIK))n~E${Iw`_aHP<$l{Sp1{%bW&ln~S2sO6IT?Mjb(iu`_~fp(o|{-7-PU%(B{ z7Veiu+|O2GKkZ28<`{0&JRE$sT{(+|$h*MWXtC;~(KXQ$(|bv(2P+-TE)(%`RWC;R zBQwPz2Ka~?9;yLqzS0VM1|(BO(5OhzRF#)PrfES={UXfBor1X_!tBh)9BnZVhp=kF zJSD=cRvkIzYYk>!(<^X{M>Dz~95v324}9ZwP#Mw(Vc7Pdcpaq zD=o%R<8yi()wd?n#@}En|q_b)CKQK?F=4bYd)KSIcF;+=aH<3UQiv!TXuu8t3V`iD4o|En6j zfl^=9z*u(OY5SDW18OLto5-%>6I48;illkxUtze4I&`yc>NHKx7==Z$quho`kY57w zA%Dc%D*Vmg9@j1L|M-Pi#Jb)gN3Ov!@H5zmJ{{^*v7SbUcE< zpZD%&n7Mo@*MriUXsZTbHRow!WVQ@J+W<4;c>^`EL*+QFM9TF5!#|J;+>mN=1AL+k z@CaI(g4^>1i@w`YU)-L_s}~mAvqIFdhC%#9(whe@2$r5NmlIU zs7NW$0#yW!CPTtCLQ1?bk*x@god`e0(Q&yNUQ!vxO9q$hT~n^g;9}zq9(MFJK9MJ~ zfE%nK`i1*BVpkteayd|^D6r|49wRmPP#NiisF6*H1sN~JPQ0W$?D4w7>6OLdVX#gt zzY2j@>`brBpx&)iVW?3l+^Z=7eO%m%7$JtnWiWKLQAi#`XK&M`%`K?4pfK5kzxzX34RVX#RlK7R?T5%(-YJy-7YR11& zpssEcxTe$zn_cp$6?32M=CKi{GaooY&*?S8XALcDQ^I1Ppv;nJzB z?MBpTt%kw|0gP?5Y7%o{Ae#*;>NT4dYiNTxObi_nwi-S%zK9emFQJhWNF$7J75q1Z z4``XJYY)Ybx67BPl^ZF2jAU$Yx+fJQ>ax<^VO?#{%YUO66kyI>jTOqHG+`{R(k(4QFQIcJOIcTB>Yo*C1g zCUI^f1B)Ow#e14ZGdM9r7TPnBvu98kgGqKOwRNXL8&yT)on4Kqk#TWhKmTWibwIk2 zmLkS>;B?iD;q^Nm3Ao53k&sN4ATkD#lM1_&%ylP4_n>0oAcvSm*7u5S2TBS%hqO~D zl0M09zyYGHNaO0{3Y)@5E09;=0dd=*@A%#QVm>c?`Ix{rsfp0F1XCzzewpf)gLR+K0LXyrU!=tJwNw=BdGun*MnH32Z z$CmlA8hH%7RB-cWWLpQ1k*Q3>G?|{6bFgOz%NO^vg!I3JoxK7*js#`-<`%0~!Vy$E~QmE1T zqSXzDyOCoz75Y|l&bK&M4~XJnG7M(@1$W8^IbOpt)SPsn7Du`b^YnlzXM~+n+U=CG z9e&`UM3!o1E*lwnr1VZttC+P#nY=1TSr#$NG%f`wlAoOPpz9SMa)cRCxE77dnWVW~ z+bJl_LP2JxVchKYzdu5 z0y~yi73ei}Dwh>P?Mp?ne$cau1a7fTaWYTJ1XN-ZS81Uc%j`4)E%IiOa)X7`A#+lN z1eO-ifL=AL!C2*Uhu3BR}~Jzpxhu-7Y1TY;l!Xf1qhSEO#v$E=~o>7!FH|L zpmWub!ek)3fPqdnG#>{$XHFQ+sLR_Kv=ol5_QPRj_A{=9Ny_FOu4W3nw6MbieN>O2 zmoo#tJHlp->6LmR0{6^KiYA4iZm$D9n?V`>`B{{dVn?!M5=Gn4BuPWDLWalj77R zA}7#F>rEqcs}?Ke5No#Wr0^Q;edu+bQ$~|kz}%6WwDhWBFrA>GaMNL{yfjr-)NG9aq6M@?X(uo z=W-#=Y@vIrtk=hKVH7Xyh+7y$o>?d4x@SGY%o@fc?8JkUCJtjXrMNl=2u#IIl89hm z2r((?MJ*k{ju2L|xjrzy#S@q|a8jFVkrUf|uvq(zOg8!`3GrT_EjB`VN|Ix_?q-Ef z8I?94RauA1+w$ZrR}&4To}X$9O&6trBr~GK8!b@JIYg)U!Fp7pT!b?w+Y!B>9kT75 z!_nvTVMkxPX2hn+7*1vm8V)<4Xff3+r;c{Uk@S|+ZJ79K-W1*{27rO|8dkSRE-%;) z=}BaSjhn)p*Dl)T66tn@4mUFATH8bMs9#jPBfr9N3J##y-kGyFj-I%e8=XIqjbWO_ zQB%&S+V0~Ds~8{Fe{+jwV??pBcJcx1ro8;D_h_~Pis5Vcw5Y&(koM->Ude9I^4Ctn zKvs4+Co9Qyk%3(*isBHFJ{;Lf>t|0#p)#3ZxulaV7DyzG(pnLxBy)l}2rh{5V3p*f z>d2=B)RSIrx1zWAwU{0BL8@IUMXpw_2Rk}59=L}$o@=CWTL$SoXqA%`SPti?xg&xo zXof~fRL{~);?d1|4W(VWU^c{)WXmTNMW5a`;z5KJpv{n*7quB|bYfZ@=s0aTeZ@Q@ zYC%ge1#61G8j*x}*R2>4FKH>o`@f>VWQCd{Q7EE~4kJW&CY1>l4+tuynOj5GQ` z1heAJTeWy%Xq-tIM7!g|!Xsf!X_EB7Z8Qckn&M@0i_8+*?h04i-2wYQdtQ#mlz4ig zyB?j4m73uM!=s$RItF0Q$h#^&UR@r_K2$CY%rA>uTeT6Tq4 zEbFa-T?C1<>TdoI$2d9;hsp9p{GH70(T$jeqcWVX(l#(ocxpL9)Qjfe_QC)ov+e90 zFw)Ke1CDFxab_IMNNK-|n8vktMF+xo?p+W{=5Rl9`6z;f!VUu+Q720Ak4XvRZdoHB&jE6^e z`TKkAWteJm69q?pn5i(HsK=Q;9g_jfjj!#6K1Yh`3(sZfhdzfTq5B#{#FgY=bM+`Ve(ljM`xgd&r@e~LS$aXDn#25 zXLdOo>Z)oxQH!EPlm`p?_^H-dQo7Cu3&zO|E=Qr>I+w{ig9}H6DDVmfRKex|zssoQ zH|k8oM!mitYJI559s@ON`h-pYErpqad19FM<*hSIZX00pOLLwBBEb}H+Q$bLdKQe!hdQ;z?TbNFBYMg@H9H7g(cp zV2#laS;m?~Y7`q+m{-R`&%7v_z>z6BB9(-@S; zEIs&@^q(s2zJqiw6r0GZD_ZeMFxY2uH5gw$bJlp`EH-D>*^#TaBZqu!7Y0Ty3I2yu zQSDv!;qKPnHPBbK$};vrolF`W0A}TAK7;eHZg_t5i$mG`Y{E`ff04-~3sLd*C|5~u z$n!Gu0NEhP#)Lt( zjSY$2ibuB#Qrdw+?Le|kmy`XX$VYPr^JeG;Nlu7L2OMqcvjcthX2Op4&VRgY4>u~e zI!2Wo8qdIcsyX?KT_{1g7hfe)REc?!XGCui8<0!q)8T z=xD^%JV!sHikQJ7;3PT92icodPBh4o2WG)9m_He>9n z$X@P>;)Sg^a~l{9PE@JM^G?}K5q6gmD@~}(wlugaENjP?T9NB`aBIjFD=@_P{!V%h=y3)NT1Nz6F;qg zc@#JmI-6n3U2p?U2T7GpmYAm*tJOAVZgu1w4FWt zGuI33t8)?3sMkaEV046DZT#HS)H{$$?+Q+x|I3v}u@y#TyJ$EVaU)GwNS`>Ic3I3ma9gUi!m3!uy2P(J zB;7#=W7Pdl@zmx)>=7<0(#=K{W_Eku5zeP?e&}P%u{K1;i8fe#o1wv@Y^cO#GJ@V@ zE<}Vq{^wGj^^hm`t0tPrX|9Zv$6+0YE#IJ-TvtGsvdc~cEAByB2DY2HUMxL`I)!fr zEKD(zaw%rA&L~rKM(O3WwIjkV?~Y4fVM^JlFn`F^M|sdM{>2G(m;78nRarSTKWFIi z*_CN`T2ybMdU`}{oN2fG3O+C2JtBbvSX0bMMIr7udqgC_aGaTX;j^b1SMVKChnpn$ zW{9oVS$R{m9>M$#K-}03KIrP{)QggUKVX@t*Z$jhco4a=gbHtE%7i7(jPn|uv5Gjd z#X5MojyJ)puQ|%fUa0jZJ_ncSErMAU${qr@8gt7+WH5MX-W^?gH&AaD%B?l4bU+)) z*kcs>Pj$|Jco7>W)(3;K6krI|nNFG^tS|JL!BH+i$B3Rg(V_n}>ftIl10+^c{-{z@ zUcZhKpRO=7jaieJiAE1(bh$xa*Nb!=c#qz$%&^wd+rIxY&!E@bGUn|&at}3y2PPt( zwdEmfJ=^G+gF8g-sl{Ac=`!tKdL;7}6S;fxb{@f4(G=0sA7k_C$TP9?vr5?UmHRQd zVKTlK-QMIQpWKtg!8xyQurrQ6x-}YO$Z|8z&~46wP1>QNHITkHFKeLYYMpjl^1MRN z5CiYdGbS*P6r|xcozEl2xyLy9u7MfEjD!g#rX)R$U=wC6w!P#%99yIFvg*}Oc64Uv zxqumyKh}I)G*(B@xLjVq?7=vgU}u<#g}UqM zAzIHgz|Zhm6S?z)p5z~^ptBrtoo>5zSoP#D&Gg1RTj(GVU2so&+sm~moCYk{qPQBk zTC*|1t@8k9-}>;=#-9D`i5Vh$OGLYT-chxLxN%1sb>LNzf_B(Q-#?4|w^GMpZmm`r zx4AW&Uc=RH)5r6dYq@yHEz-8~Z#**9tI&cEoG{f5EzFw*~5n`Ap*=z$%MzG4QF(^e)DyDl?aa5uHaT$R?IG;%<6Zf_TG9fdB; z@Y^ABc&_RA=@YD%q8SH|NX1J;3r61P!iXA^i>R>%ReXel&lAhM1dcfw-wNFt|%~Y}pCTZinn$ zKI3MUhH*6Bx%)cX3^qJTqO<0G4ov5Sfh!N|xa?%!l%{g0Y^Z;H58%HI^(Qv>NfH*Rurpi`R+n3+u{7RG)$7yFrfe`D-->0s|>?Dj+% zhS6!`c2ePfW^!TBPsw+D-MQZUxZW{Zgqi{C+g70CgJRZ1cFDE#){&iaIzCK94mNlC z%;%-!(F%^w6t`+N_Z13h@;(yAPvr9Edj7}4at2}WB(<%!deUe=+RJpu2{?M(!;iu` zil2W4N+~}Li!1UldW$o`jWid2qT+AAZ` z0fki$2R;SL=}(zE^QPfyBEIX;zI=ScAV41<|M$ncKUe*mq{UPhsab9jt7qwIq)A`! z8-d@{g144Vcg5u=Z6X)P52VfYS31E-^_yI`L(M|>16Dg~FMI(Ra7r{zu-Zuv556N- zZ4&%7pk+5`6t$P@rsAuoZ*o*TAQ^dJx^?`m5uAW^0lo)1<^*jh#$uzXlrGEHLxXO- zFb0+zjLz$;uC78~t5|LNYOpKRY`22dvuT2WxK*M@kVUaw&1UUX6k!raDe8xRj?XIB zDFM@xviKUc$;I~xLqK(W<=Rbdbt5c;?*^GmBoy(3qsvfi(uykoNFgqQ1&XRuE1Yqy z@rKbjOJ#@7L(@pxp-XajP5F3K!rvl|`0h40(UI3%TRlrx=SKDk!52?xRCC;xR*@3C z$m-;3XIy>iJB$}N2Q3)M7LKhG%s>%(QlR6{2jDsrA#vh-Eipz@=xQG$;`;MRrh>)v z1r+1>-aZul*cgnm6I@CLVh@nrB-}JvpPECmJA`Zw$yl^x9|##Rs05vxhVOSvu8EP1 z&fxgnQau{gm#OC!{ync=#5Y>1O~iNnDrugJes5754H@fwsTY?iLF2M#6!`065PK&?iv{w3kQDU{Di$%>vYg|9qG)vZX>Mqxv?ABh_5$?)U^; z#MUe~Xee3X&vO?DsMKE}2ySZyBL$39t;L9{ zV+ghwt0mY_yt|msEL$|q;?f}thy3ETj^e@He*ChE2wlkT+N-2_PJ=kK>@gd zXr@ydMS>fZ_$n5>3|)Y*3pOigv6snuuw(A!e<;%Z#0BoG3)~A_*H5MPx*&EzOhc(u z2xv|O78OO{d>|K96zy%B30Dja^TDC*DFH8V+1S3DcR|3y{3TWz^a$YNPDbr5?&X&N z;ONYAgKD@Y1H|-WnSc4^m_Qsck10z#`;u>?W!o|l*!ovWPdi|biIeemsk%x@sN<_2 z*?g5Ww;(LqGI+~o@pg&2lo29cK%6@Sr$p`TR<+`7FPXX)qhjkD?qt)xzGjI zpa!7^7N*GLVv4hoDIxn_A!2&0Z-GJub+cH<90R;Z1rO2eR@Vwg%zeK9q}2ML4pMll zr~nImFA!e-YtrO`VE#h9Em{mJb%eRu{Fykv(62 zKiW-ts>h(!?*uR2X%R|`_D5;|!qSmEz+>#6L9g(w(+L3@JkkB z)4D)mhoS{hMIA}(3o#|;Uj98oJsxt#&qViTUd%jrvAPT+hOBr6p)1s*gdSCYAoK_1 zNMkt5#xQ9@JT;Bvh-OgA%tUGCMh4kNlF(EGUxu(GTFBn zj1?6u)gsGG?AF=_uZr2esv62vH?Y{y;m6gVwq6E3NEUY5e_Hs-!l5dUUlCWYP6fnN zoVZo>LWo&-A_LXDe2w0U{LtD5^x2!-z7+sgkQPEEv1y#D*vgn&b)p9yhs7WQFU;^5 z1l!EsH^4*s#7*YJS7Z6L=pd+zI2OzSxL9|&O_Sp*l8`wU<@swc3=ClOfO971*Rd!z z#8zTS?MXEkFIbkc+KI39Hi31}4ImnE&@2KRBc2m1Gey+eA_!LH6R;cpnW%BOlyn=h zy4Km6s~26b*Fv?yN@tDJFf7>Q*4lCc<(8& zMkB|KMk1stctuUK&?HRRYMs+>5W>OmC_FVqZW^`F2<&=!Rk_;gzHqx~JI~gWU$L~$iD%D_C zpVh2Zp$0P}xCG--}*mW3kvBI~}QW`o%Fb!5cnU z9lKRRYL?EV_pcQh)!qthwz2DM_Ys;bwRf7T&U0g?P7kqGD&>E9Ck`{9F~rDv@1zHZF5 z&Xd-8x|Qni<-aZBXCROdy@*SeOO@=+q^+Y!hLWQ^qd$hdrGEME2~8jC4?0)z-^J=l z{vUvV-k=@tY{qJ)kR07$>jK>xb;dA9XV^Mlw?>_@t#hPxj&7CRsbkdIxGjZZ(vz9K zESNT7%Cx0*>JDYf&@T9ZJ@YR=;9#w)hTYUl*x%+_A26-3UX$=0ZHClcbxh&l0%Nma z=oO9j&&K8O&*dv}?rCr)!}lh$+N=#gxWud){l|n$0CyX`-6prFR~JM{+g7s1>D|4x zWre(V5NSXSd+;>)#NsP((!`hlwy@mN^>!8QuhTqYV<(&~Si92~9q#tW{TiC{w<`LnK`gFeq$g5g7oT7u?W zj*?z$q)v=+Cy}r&TXLELbecMwdt|_8tMgfLzPeIZ7%Sxe^OuSSe$ng;V%QHay1<=> zZLOce<~IkX>aqC+s2l4Wu=yp{)cJ`ETu^Wyys!ieMsE@h_~*I{7Y(dgw75{nvcvPZ zicbD=QDy{mUVLQkRAG(O2G|S-WiaT%rSKkDll{L^`CooFL=Ogr*O3jdhPeI}gza@3URVjqf4xuSORK-cOi#-Ahf zS+&^hg?}w31GZx?oh!;Du4@g|MxkPixH#w#O`!0lQp=5RYa8C$M`|WZQO&g!SnDD; zvw@f|u}V&YOgw6f@{DNlLE=CfN%7lH`SK4p0v5Rom&8xRdVI-JX$+1L5u&Fqiii_Y z8^igSJ#qvGR&jcs<<7?D0Xzdi%7y1zBVwN0KR13XM9iJ9C$H1ckkq|kvB(5~|Dq5` z1TBLn$A&=b*a^T+b2KnVPDSB7{z1YbMiwLWycH}))kLVQ5>n(*Tih1s(m_`M zp-8Vgl)pS;fZ^q0C~B4s6mear6tYXX#=+v*U}(3~>gsoYqu`E(E@Qi4gzkQn`WKhY{MGeoEtgaTm&tO zM#R4F=w>@~y0HYkDIrq~9aLmxr~hSpt5I<(;J6MSJgN{iZsC#P^RcHr^pydI$|4M2 zRQ9pXNMfMSb`09MEsx5!4IN&GwnpQvx;#M!Q;VAN$i6)S89@7brT%$c(Y)8;B z%{DwHcTOn+^0<{(NMkz=W?MEY^Ki3o=C*1-Q@@UFtNw}Dv)ihNBuouEOIKnZR?=8~ zZjRj@GsZg(4L9ir8-Xrcy|D$?6$N_3mS=+m+c7@&2yR1pO>RrJS;W*J5Nqn=8}2#D zoxK9V0Sl}{Ly_1@7xRRWU6~wF3+J-Drqm#gx{VheWw8clc8TxlWac`lq%Mv@s)HOu zQEMYiV5ne@1T?uELsiJZUIh*$*pK;8qQaO&m$g5!T%JQI=ad28@Y_X?IYu{k?mA`F z#FW^F#)Gtdc0+M7>?4Oy1YG>$oIZaa-)+y|<3fRKr4s`TzZRI0Arw2#nu3n|g&j8( zRkq`VeIvkhUb8Tju3r?#^GmnL%%=As8f?1JdouUUl$wGy2-6?Pp-bx0`1*7tnO?c zR(5(0%P=;4Ye6x#^=R^~1>dXIov}`hHGF?=08j+$poJNEDul_5wbM{+)JgJ~-`FD$VEcCyWI(MBq4SNpLPFXpe-uQ+Yo7~==5TZLR zlroW7$j4fUi2Wh}srPn^W<&DEX=l3+Dl?-j{e;gp>Mu2W`9`NZ{_DNoFOjWj!c zjJwHY1O7u=;D9e4gn*OsgGay!6Ls(|{yTbQ#wwh<0oE^{6|OU01dLBZSh`!vYmVnX zK{7bqA`A5*DjxTP=Ru35q2Vt{=>t^pp$f+4Q53O4$rUNp)C%rjfPfPNtndRCi!@^u zybVAfdsDnm?fD2B`wZ@kv5CNmxE~3H1+7qh(&!V!EF|41DMy#etE4Xmvr6P(&85d+ zF2|r3W=q62%%IOLv}HzN^h!txmdC50L29rfP(9&F!xQdPe0cwq`?Q9ibzk;0srQP9hF84x zfxzp7Qv2h17W=VcmxW`kU7o+X<}pJE!7pCJ$cR zm!TB?eW;#>!@AG9FM9a*ns+H4z`8g1oB40E|F{q9x#uO$!!KIUpfpEdg7`s{3wISQ zH8d7ai~KOQVGc|fbfStIBuqGsY&F#%;)Lbpn0fN%{~M4C|H9((`Ivu#P6HT8)<2Km zTjr^%9uK_xB{&Rl@zl28orW7E3*3#d%ej%e95b~{AHjQMM?n~M3UVPQ<_b55MQ8;U z0rz^g7}ch%c!QNP(&-`oOpzRV@ryk?6%McGnH5;D8fD?3%Xv(6Mbw92HjwdHejn+N zPsqhL`)G~{H1NTxK`K7h!ObmPN~#^rOG*0WFBB4)nA>9;c6JY4ukeq0Y(Yy=In4K6 zef(m*JmSqSGHhwUhqtv9ViIiA3QI9hUxAIfz$^o%UU$cX<1l~{2@)#)wKCc-Vieui zV&}%COTlQIXZt4W`I`mf7C6ekJZW=pk~t#yuZ8jp2ah6Njy^i!tS=LJvhmb9gEDCjjr>P9|9 zze-)J&x%m{hLH5Z{p1<_Y&d#eEf1LS_r3XrT&M)unln_M|P4R z0~n@30s&mU76e|bSo;J0Tq&<|wp3~@P@M&#>ttc&ogakXxKFCDwXe}GQS08)y0>nH zq1hO<`th4OF(VSi7Rkkw1y#TK(?nPkqAD{VF*P3-Q5Lw@;0PSR8|tInBLz!jC`SA7 z=R^d^_HyShvf!d+0GHhYQM&mSvf2v+`;o1(jPOf4BD)OJKA#&dbTdF*D5&<{(B*bscr(eVkNL?0ZxqXh9XPv1p$Wtulf&A91oo9y!U4F3bn&apW4z2Ql3E z<9wiBzDCCy36tc)eIak(#Zq2!O-v>wgO~TupDYsk5p(^sWqYykK$KS;gSX>P_G{F`gwKp!h|6nvoNUqWH5}o!2S9}*aks!d4)b!qdz!*?qJH;WwE^1C zc7LJnCwRYlNWjx^rA!-?p9jH#EjR{Lk42=;v&q-^FPr9IMloCMtI%Xl%x)tV?n@Bk zHI#in{%<)KVvYX@TOH1cZqp<^1)@6Ff*H~c&@880{Wv8;Q6o71vqH;Fs2k&0F4aC3 ze1iHpdN2M3ia268?_@`OSX27rIrU+ho6TF3IGU-5AC1IXVej|(mz#Fn&nmV$`8P+ECV3e~u&cH0;I+L-C>z~WD+&-}l7y+D?&vMtRQ(@+Q_i6Pu z!4K4b20r;P>h=o{x$4wyZ#K`EZA-J~1siY?N$xuzy4KdNJz3?dpHOdbLG!M9kN@6N zpDKe^psc^d$XVoOcU3qhUx~MS6jJLV35eZ`;OuW|!n1WU(!30+k%DffNs)XTTIQKyR{z;f**ay`J$v`<{s8L9AO*&v!g- zlcki{8^Z(lq}lBAZXdstg>k?>)vYEbPS5ePSh+=WX&d}jX>mqotvrJr`oAMK zb^Nb54z6&Rm+5y=<<_0$nZh=!%c@EZwowtA|DlLsSY0kx32Vc+mWOV&^*FB@3%{+$ z8iQ#4`fxrU(f7sjFs_96(1fyIj*)EKZvYfcHqi{{F=6FIxu+GbO6~O zTCREIR}O8eFx>KMn>w~eHT>a0ABf{U!LLV;Q9F^3l0d4RJq%`{R<(z3FSWm0c6w65U*FeJoYJ?`RMw6mO z)5`b_jf}V>4Z3^WT3b3_U4$i$Fu`K;HCvAQU@2pGLVes?zLSFgiH-kTV`7|viFd)o zf5DW~mIxUI!?`HF;cz*$!kz9VUVI&6bIFlXc^r1FXd@dbkPi!ni{B)jI@GFv-0`+_ zx%$h1j#ymj#_@b7PEP%(oys3i<)wXq(gq7#T&NYuMsSf)dC{R#c^u9y&_?3_lcwhn z(9~~}J}t97xdb0hFlFhrZD$YIW_u9TLvyJw(A>0Ql>^;kc!KNtbB*3}mq{gQB8B~# zqD0mzvFe6G9jJ+mbw@vDdZbxw=lL>E#yI!8zOIhN<5Jy(qX`LrEY>wHmVBt>b9H=< z9%nE_)OC)Va(3V3BHMFg4z{lesysZ$jbc3opkB6Tevu-dIAq34FfHN28SZM&M``{( zsM}|0-ZMC`st{}*TzI&t?atmCrM>wfkGV_rgoR&6ZJI1gM*dK0(_|&U)Vty%2OGtXz8nB^ z1Z2!-yL|a;MDHdDXzI-wJZfmcfVT3%?D&b6;x?h+3|n@My=($}U0sO`RM`rhTd(2M zTJ!WQYMkv>g2vq0R(RC#sxafD_O>kEvNPfY zhct5k(+w*4IhJAN8V8cx=}4!YU{u58~<50bmA{Xhk7Fo?+*SGM!rNd2qiu3!4 zSwh*#8k#%}ET+v7Ks4}g5?y5}p8rf%SJz^EYFUjz6@eT-e8lVj@%AS0b)Ds%|G9ea zd#_e+TD;p=@){>vy~GK!6Y1WoNVX&^T5Koda*<`p7TA)JB(~VaY2B<=Fiz?Woc^1=>4D__YD>!NoXwDJVhaOAd&V>5w z1nqSa>;pIO=Z4+@)Edr>m6>Wc55!DV^TXz`gPN4xO4%}eCdH$n71!_sSbc#RI@)9hXng14q0#!iRlw zjpQMnW~IkN6|X19o_>9W0axC?{~o|I1~!@*Ndzd8cB6^OQI>mD&{8sZ5qw<~v^*?5 zRl(C!6(4lr`Gf9hN5RwX^D-TucVCFhzu^8!<^SX!7tZMTIGJw{O#t&D5V|7cI^t;A zp6e=>Dw4W7?{-iZl5(GHHtaLT2)^no?OG;wCaz^79TG|3I1}cYd8N%H9F&_(q;n%g ziByTTDnG@zYhVskNaa6q@8d~%%(SrUm2n?1uQ7R6Q}I})#Q`+5-hLu*t1UBrxfbKwPj1j^Q4pzkY({_5Mz@&A435-;*}omv87?Y6 zwM_owIiIyYrkrxv`&>(4fR@udoW5ue)-sbcL}RHqhO1nR#!_)?0m?8D;MfG_XP7B# zQe3x5Z~k@Xx$7I?&j4q_=~8)s-H1e&XWq9>B&eq0BURt1VgUsG1u5OpSSEnd)fOCJP^x7z1-*E>49X50izL=j>=7zvc!Q!77=Z zXmE>|#s*&Q2z_t11{o>j%svYBFEe6=W_H&3#b`g&?9CP7yF;V_A2PA>;7-sNuC6GdlNy*kR=T-d&K!_5QR zuZcGoD&I**0>eLUk9U{j=l7UqFodWi9X*=OI4ewlC;Ps-_+HF^#Q>L|FArc?U=!Ge zsa&1pMHFu^%8}vc(XFSrp3~vEju#{4Vi5rm;DUmWGZel^FNwaq(u|er=zDyXofX?DEnM((i|1?Jk`~qIjm?;8aSz0esAaIk_w^` zW=NjIaLK*QWqdrZat9dK5DdMA`!yN2sv|y67C*0Jqbp`sm87F5fz%4q&sKi~NRtLv z4gmIFFhFGo-Jc^9|IL`5<$~vp;6`AzNk@+`g|$lme)T(p0@Y7zh}Ia$P!JeI=(N-qwVe0^muWpIQ!3Qjh?2xkWNx%TC_I4C=Vj?m52@4w!|f z>i_(K$?gxcK~S+{cw>B?w2%`+0LH9pGizN9L7=H<5Gcox;Cqj$QvN%}9dAFWE7!^l^3 zPo6{f@a?XZ1^Tl`YQYiR43l;ZGuL@hlYymoggYN|Kp`ygOc zrmI)(GB$mhCtQ}W9x14dO466PC;eph!7`Yv>dRDrgjhc~5z7j`aGAB#CLKKky{%RH zZP~9^zNkmcNnfY!yUXJNfM8g&O9M3Fvo~$<3lBb+Cji>w7e4mw-ZIHIS(A0Bi*+r2 z(VDdE@r%owv{;kO>V@BU-60aRH}|eA=VYr_E&N9M%ChPeE0v*K)(l80`xt{)LUsFH zAZ@6y6DO4s#XA2CN7yarYzKE-A2z6yf_^KYqgGR0(Qnvq5KO@quZwRPBe?~gk5Re| zSs+6t>F9|BN9kw$htSFa|EAX7Zw-dU-=FedkR1}ZzZnL40~XaN9Y6o5J=1`HnP;r0 zUMhdgKjFDN;h*%{M-0_pvT7NqxBH(aB|>TC-%?gSDgo$^U}KhITH1Yb7Amf@)7|BJ zKuhk?nw9qST}G&mN3i>3gbc{tO`WOwnp9I>AEnEW2O6$B_$$%og!z8GWDi z?<=FP+&G}@Jr zMYNTs%PE(6?m7|g6uRQnsU&Fl1_CG)bU+;;p`tS@H=jbh5Kg3lZ;yBM$AH{f@t3I(Hc%R~`arIRL!J~i6;ZL5w z6u0|Ed`(v(RaELD1ov`%1J~vK^a_6q<$5iDH`hPrn&bKnuG_il?R4Q&Z;k8vAlL73 zy_ZEl#kHF^Jk{?ESFQg+u7XqV8SDBO*LC1Y?`>Y>S?@b)T|$oVV{Zj=wfEV$>LsT$ zT=mw{Nv?X`=a0GS-x~h2_fxpqD;-?zy$P<}tHB$HerIFAw;gT;2j|(I>Zkq#Ttz4C z%?h8|Lt7Pu$LK?m;fYI5^YUM=!1dAi`YhK+c>WH15~sK-7k)EWrLy12RoUaaxGJAI z&Q*C(U6s7-;Hqq;)}{R8&0If2`);nv@QrX)#_b$ey!mJZ0x5`B`LkSww^I=5JC)qT z|Agy`Xv<-gsFj?&mbE99TtofXO-a2L{oIS{Utg}5Y-wG|zmG%bMEJazpJ~{$iG29} zRk+WnFj}EcOhvxZ9y00s-<#ruz-K5CPpdGqBE705z4Ht@;6oJ0-^n509Qp9on`%CH z6ZvPYIj>W`Jo5T(44||58u>Z9uV9xu@_z_Plk)KO35L%_{$WsqQcX9ki@aFZpyfV% zqhKdrC`cE+!rUKXS?n35?|DNCHT&@wl)OXlioPfHzEt`nR`&)tCLP_b4*^8}342Jh zEs(zVZ9K;>`15*yVO zf{`t0n9e_I-J84 z>4uZ9eCdcU$wmH0?Qv83QTHee_T%x0Z+CBB_Vf<-m`gvQ4C$AxJiK=jrT2XaSVtQ) z9^3++cAEm=HPYJj2B?v|Kakdo1F&ShT2`hv+@9QL();?-M|ganb!02?Z|l;})jhN_ z{f3nvT?v_!;+LmimwF>ZlnYpWIDbCOsVp5ok9;^seq(y+p2){1w$q~!hE*Dt(8m6v z-IGjN!`D>!YDc>N73n+Rh_|Gku7R9!?Tx*Wf8OpPCqi%_9MnvIAp2&X!V%yI=K*Tk z30HWpHof8_!0<2j%xAiWBd;^4F`}7H!tr)1sZKxV9|F5i+S3hnF@;aW z9)->kL_R(}V0-nEkN4ee^Bk;MH#A>w`Yx%UG)6y^vYDHPd>;f_r}kktoT$#`coBuS&@E@9f`<)w^{8N9M#cc_o$1<>9Ert zRvG`i((VCiXXIs*4DY{}PJgB5lVEMZO3(&iDkMV#_ddBTfKa_E{f?^dRv|=Iz+5nC z$Zdksw#XN@hlZ6PE#xP$9jK`%t^6I?^mnuGuS4$aF-otZ%b&$v2==^EC!}+cEtYNf z6?~$Pk4B;!{4;?-=5^o~NbFKb?H)_mHmd9+#cXS1@}74cv5WV7bSX3dMunh%>b4>oK5YgS}? zXGPYW*Q~j&S#w;o=C)?dY0a9;nl*Q(1FUvrhrSs;s%F zSAZ12GuJe0j%n81(yTe9S#wF__U4Xe%^A&_E1ES&G;3~X)|^msMYuw#ta+fRtT~`r zb3e1@eDd~%ppfJFwu-FzomulbQ(1F5v*vPU&EZUC&EL$Lx0y9xlUDp&lQl;(Yi?%N zoXo6T%;zez=3!>dzg(F$_cCkFW!7BFtQ^aS11-`vR7QVuC$lH{TgX0Yf1l;=BdM%8 zlUZ{mv*t*qvgSu-&5O*wuL2)3YaV3Q{Ku?$k6H5_v*tNw&2P-gYy3<)YffYKS-Ff^ za~M}gnDnwAmkmzdqr<#f9O;{J6{&CY@o#Mh(2D<3`5W6O7N-{$+b7RY-_>?{;nJD8 z>4o;f{M4lj({oFU?YGP>^k9Bpd;!iD*{@2B_q+0*U$p|OFn(*AI5&(AMRw-3xsoxgNu`uiF2+@0;G z7caIiOn#r8FHBu3BW1=0YS%?b)3{R?7H1dR3)6SZPEEIu7Ke*tJ!9=-^OqK;rlYAF zPhAo%PA#X!sWS;JPMw`yI(O;xDQIyjrp2jqcb;OxQ!y1zG1IAqNxLxNDJHb)$@Ay` z@2_T|G&?Ug_SI zi|uD-E`2`(z$yO*u@_1+41TV3?&AL+V=qq4mS(%YuXX>Qz&?BN`zGo9;^g4bd-w846l?-pIy*HL9%m*m%$~oSfw8BHcP}nYU*MiFc5w+HE?o={$X%&C z0b19d&(BZ2YLWW*`Ru~{rHiH6g;!rLT9`gN%ZLl5iwpBh(^E^c^K+px5jCDLEgEfh z9&qB3G=@Fc!e(Y?=4r<|S@s$3h>djzKyynA^XEg!g~?fsja`NLOFGPAqw-!5(7T}gR)o_sD4oA}C*6Bn{%J79;7zr8pJ}GH!~K2*{j8EA_e)eaWLDz{=X^sq zCGCErn^6n(QYT-VN#)vdYP>#0U~$H4On{{{0czaw|ov?Z7|ZML37=iOQ(ICyVe%TCUhGU)VOg2slFl|X50ZX zmjI^$aJ>7inl>wXpA}`au$24a z{izCn8IAIN-OpuhC8^BnoZr-JBo<8|btV_c&3&_9A?j8Nt&N+E82-xJkvIaA3B+vBA|)ov9D?)mAUB+x>n-{aUJ;LsgAc$rUH} zVO4M+t365#htH)y{(3GIC%xCD(XZ7-ZS30X8?SioEI+GrMN2?Nt<54=-@QRy>-~0{ z<*@JPx-IAXbH209H+F-;hBlHmthLViC@^q;BcSVrARrs^)hT~t%2ze|`IWlyj)HpX zz>@LP3hSw0!u_^-Hq=9>t?rv9Fb!#{GwuiPOHt_D|E_=pFwF`^cCWRO~i5SR#4DufX`J>2x8OQ+6kb$#q891h7_6YVN zgY2)v5CO8c-Hw$<3DGv%+ zyGC|D^+2k=p&`A>H@T+)%C8OB-y@VZ2-U09>QM?eEQqs z*>gtcoXvJ~07ykU4UlC386az7KtP&%7Gc@oJ|78Juk_Mf$8sKguWIwFGdIOp>+%g0 z?d$Tp(A0Z;V`jS)zF(i|IAj#OuFb(k>sfc>UccVm!jP^0$iYmGrfz@kg^gi9*3IVY zbN8qG0lQ849$k<4^Sb2txo2x|1LViX-f|`N} zmEK0Lcl&jqG9~%%sL$kN(q%vE!@L##0)4a9*pD~ zU+aF?=bE>gIly#tZ3*=sxF<#R8uuxm^KAZq=N_hLj4f~rpfujV)Y}A;Y>E5dX>%OZ z*ZtBxIh*d&zRhpQv`DE|yI+3|gE!R2BXq#K>zMo=gM24XHZ^}YW!wiD%Y)Y@YrHb! z{_ATPsLgMI8)(l$R;B2HPqA6+-gdR#E9nRaX=pS;#y!KhjXY&Kef?%ScE-TC>Kt%3 z_^n$QyM4wCI!04|8vKWfufSHd;(;x`_Aq}TMm%VNVK4gDK3?pw%tyzmD1$LUnd)|{))wdR6h z4Q`Y&Q0^DRB=z+$!79J0!>6|RO)bFQlE4F;^?v16mUxslu1N@Y7tk5*hX4`?)}uAk ze%k$je2n#O8;X_|{}P3z{}qCN#nSn>L2#0)n*Ey14BKh`M7G`MaWGna7DjdZ%d<PEdr3+%nFZs z!!7f5?tNMdIIFRRhNJ!YE#_nvJ-z$pLYrJL<^1G}R zga8Hw?eYkYsNJt1N)7J!LuGr)?+~|g>GnHmg)6j~r<#Da_aXh_n4c}9?MUF5XA`uo z+2X5auf$yLrBNrIb$BEJW9@#YBtPY=!)2o`w6I69)nRM6zB{a^BSG-OOCcC`K~X4a z>Hg6a1+F$@;dY}}B;0;O&eyheGf1=FnyK@(`Qj-N)r1)FV9n>X>gnEFaI{3r&=% zbw3%g6iCyTHkAC{}^s9rU%^{OZmA zFh<|GRo(R#kh#ATrz_-YazBB$q{f*x{jJxZ2EWEi%<+X`?O~gEO?T#sTA4N0AlAVB zw+F0){-loRkKMh*A2&m-!w;x&_ec+h?iX!zbHZ&L8S{$Ej~X!sPcfyQ+&^m>x@*9I za>-anTTU+BWbQ(R`;Yg9(s&-locpc!SIfQiSnpT8#1MxmOSw15{mLBHI4MDS)s>|( zC#hy>;jee{lsD%B#n$?pUkRd|6b3 zoDcEF;r0fpY+sw3f%{jO8@mN>y@C5wW@k>EA6ygV_uWsYPY|hu+6C%&QPl{mQhwq6cH;k%13HO^CwH_#bL9nkEm;Vo- z+U9=w0aQ*-(#&6MU)2#B{i+%@$p@7dc0WRAgw+#U2iJxEpjO))?nl9>uUA}9=Qr=r z!ZbDkdu1;!giJ;SJR(Rr>L9_T|P{8#%_jOi9U5gxx z4Z_Qhf%H1pLTRJRsGx=f2j7rv>{ucEC*NG*N`wx3~`&LaJvXqsN=2)9^|gxSh3E% z2YvzOr|@{R7RFhF@d-_rj`){xcb!JK$)e*rOgM8K(LkTOFXi5uW+!%aHrW9?gjR>I73Ku>8DM*+2|NISZ)GnR$o5YG;~cnQ>QS z;pNH41k^2SmvT9z8!|E(_Xqc(qB8Dv$ZjgrMcz!)z15LRVF)JM99YvFr8@U2Tp;Sd zfMS+kFRUm^t?%?J-JH@Jjx1Q9>vm&+y3D@#8r(u4%Eeg%VgS^E_BP#@SW7cr+07nt zZtB<$2jjTcxuu-n*I7{|ts1Po_CTF70n*~Dr8W-9E_D07y5#Upu7g7D0)Z&7AsB#- zel-(mkVDCRzIKb>*K)Jpd>{iK@sbDhjf-|V@md?x)rw0og^aorU!@hZkn=BVV~*`S z!m5p_Ol;XVdQKBnXye=cGm9W8jb!*P{F}SM`+h&r;+VEOHn~(XGoMcc+N#sXiva> z46U%b(N{MoHR3vL;=AAFg>Dv1#D~LtsKr;qn?zQvnb=xa824(Y-~CtxO$j_9Z_w48UZAYY^do9jsoQR&qjK;SE2PFk>PKfWIO2y{r3U9tj>DSm zq?kW_Klwg5-~OTkGwx6CGiq()_D|5tDItZX7X7>b9s<^C_gNG&IUMW(gQ_JFYtV>s zE{Svl?gTNLfZ^dYL~t^G!oTHEWDB04TZ8)whKq(WtN2?OBG(3isQyU^B%``ghNA^# zPpoITuzE69gqm8^uU1M91>L$Wyd&&4-M!_uqs@M^tLa9i?8>D#BMHBD7aW7ef#`3~ zqEeCk4&QhyHvqFa(~_~6e1?06d)Y=#>X0WN1T-~Bftu98g!E=m>ujTb;x1{`&F;h5 zoZooZSN*P)ew?{jLZ&y9TcR5NdnyYHheY+V5b|rNKH@|nNIOzpxt!%6;;dVPNtw>e zxX(%;eFrP-BbMFnH}5eicnWSl5~AY*Mx>KM=hn7mPEv*lo@1Fi2|i77F~~}aR6BsL zbN8@_oy+B32Xfq3m&rYLKq;T*tt~dywQV*N>9pe}G1(3haXUfpJxkv2+v}@Qb6_NQ09q@6#ZEA8oDt2RgyM&3XvER7auP2w#>DOOp>LrelD@llBpVjTZS)_|| zNp|!Q$ZX$_=&=U^B5E^D{@BgF_MktuT@J?TO&&L5eY12fe%Ctpd-sDTcK;-v>$$s$ zEBiDV$0r%nTkspcb~lWv+>LiXBQ3MRy@_!%Kj6tX^OFQ>^3@kLk?>@Wd4H6FHqQ7; zEM3OE_ch%xC{bOvU(?~Uhw1CwJMPz@weE{Bd$z-hetLOPr?0)%XS;mu9>03O&Gy#& z;lH0TfZE&m*p03AT?|^^;TyIJ17W(Ky;p%B)3sZ-cikt2bHBwh5q&d%whQQ#1LvcOi_M+~+XMP0hZ35P?6`P0~5#{>$B(oEQ;t(FlKm zQ7=PA%@+4x!Gm|Np3(CE9(Yz~nhyCjjB*$Xdo+k{uosNk%ztq2L*0J;o8;$Irj2b{p9_*_D|AellwSb*Snu$p_|-agD-}8D-Y{4O{5pP+^;|L+lx~V;;QJu|Kh4!m-k3l15`z^Rx z8hZ_+Dnm))PTHlJ)Z)8>GJaudQ9BC_?!BS%|Bzbz1KP@;hI{vbI@?$z{X-7^zV0|h z8|NAyLR}>=D6@q+l2?yTmJ6Mw=SlkSLf+sHzZEfz86op)LywDFPN!2R&TDfQ(N&^QX-73QS%pSiU)w78~ zw?mH@d}UM<*x7pzE5P5Zb8iE_b(sy_I1LH-UzGc09rjwBMG`Ph$ulWbkbzC)9x5%%U3l=2tm`zz~XbjR0vLen652KP(s+kB2isZvSZ&s8WBJmOw911^L zzPwRe02?hrz~^3blGW9@ccrx>!}bLPN^fROY#!}#bDBXoSS=T}9(nr>y8BF?K76|R zfv=mhfUX5N!*D-q!%>fi{)`JyKYp(|FxNBqj|z<4 zTO^?w_m9yLqY%Z}%rbqR;7O4&mAjq?RK9%K3txcMrlk7zrov7Wjg(W`Ucc@)U{hMaV>shjzfF&&bn_w+FgU5ZQK<@ zhP?OO$5+w)fd*gG7=$YGa-OeW_N>Hy58Y7lHD~>1lQ>4IRc4^oy$SigtR+wa&l5m* zHz+SHop301gwTU~*;%M^b85!6qA9!E^uudSKL8t9EZS~sML_) z|4b8p6|T5q!nb(|TdRA6<9Ah{ z+5nn+JY=pM(@J#ch7NtmXRE;l_R5>4A7(y9h3G{#Y~fx4d45|PCY;45U@53@;1 z;~G<{lu)3~dY0utPrQy)=~{AlYR0TThnY$(xi^~!R!@^k_djr&wiAI62+1?P$!A`! zY@ha^JJ1S^91Gj(8=K?5n3qi(JtPl*d(d6`t)CL?UI~YlZvKd`9P-(GuAMyMI-w5b z@tdH$!(cxo)6G9w@07M2sXf;14g(x%u7Ua=Kfu z-niGoR^YG_uKF1{UG>U^W6f!$vd8b&+ShV|DQC~Wa6fvDZ!oeOLJOS><|i~M;G7*| zs~+#LQA8_>*IQuBRs;t((iz|49$aJ7>2Tc>3wBFhndEGa#L?=lKG!UNbakt8dU%$$ zv-mSfyD!pC$9uLguy_A>A&0Y0KlDC0r#=gy~~94Eb2!aKB-Jc$g8Zi zEWTb_a(`s$8v-0{#<^dHk1*{T}tbQ{!HSQBubG`cxcE`J?Q3xE3?IvkS zhGUy=Ae+0*Z|d|1@iUwK!B)RX28-h+Tiu7vc71}3-c}MQZSCy@+wE+uX=`JvbU)eQ zBYrEHvYWM6L(Y5EPGwEDY!_~~C_8^W2c+&z862;J%p1JHK?+PoFh7BFC_DM$Hk7~v zufLz%Er@8R;YO!pTbo=ROw2WR=WT)4Kopd)^A~?E&(uyD)yLbY%PRjWREkjbagH@? z>C!dlewp}y9cXfa2qZtA0dd$>#FMzruj}#Ku7Nl$jZL0ba>dvafmmeOrRcPwWykk) z0~bI;M1(CxC3EC5L%kgZu1;{{?UTz~&E03>j1yZs$!?t*a zu9uhrj9)Rs+_D*VUope8n&DAgbRes6AJ&;qdP99Yo-E7TlRY0v{R;E0s+hE;a$H4i9CeuzDPO(3F z6Uq#Qt=llMup-J;6V$ge`4F)2`P02d}>qw%2KnW}qYea3iNEP!*a~ht}{k*Ngjpn*&oieg>g* zU|ejvO(N0aujP&>URBVcU3>}hb~-awL7}!lE8K-#DBvVv+$NkVQ;X2&kl(Sq2VsL9 z`JoV0bm#5<;!s=p z=Fqus>6kiqktosN)H|o{7r`+$XAAKV3St+8-R9Q@f^Ja`Nkk6%BDr=dW41&56)>rj zjyk90c;<&U((YPAELq8IdfFBWIjbOaW5Y?&$GpM*EhEtlrBExom1-6SFbNXkSm_Ai ziPA~)1r_%u%r>$@LvWl@j9TRg4_c(Gj=Cx&5EY|A1bPsdUH%B8$ek(Jbz5AX)L(f` zHRINC>RU%;Rwylk)bXhl`ml6r0?XW3NpE(s@m#c|dZS;oq zURtICcNto3z3$zY*vGJUhS2vlcA^5p@m`144l6RP)J=zOPU4Ltp9jo=lBU=!1#=A; zPw7COhZp2pQNv%OzTPP|1s-PbQ|SDS`rFd#C!quQYw<1OgwDe^VP(~MP*r0nuY$%6I9wEG?0Q**Ia`)k^LYOB8n zC#%&rcKK_r)w)oX23DpUoqyFu*Kr;?b#u3t{j5gijDFDGgxQBLFAlex$)&HPONbpe znox7jTd~Aucb8Fekxf7dR)_H!{z1QThabL%K0A!7V(JRz?65J2NUK3pBk|T<@I3T( zx%(y_tIob@7nMx#t}c{qi~GYlY13Wqy{mJ}p4Yo~qpolU>}=L&=IDv;NRz96?`kDm z*7{v+HABCkJ*t669!E7=gsT)4!i#x?ob^|9m?|-dM?X&k_>@ZMB$<`T1O9$U>8kk7ZqKbWFMBE@* z6`Ueq5r{&Wf+uxhvK^R4_a6+=wMRI@M-34W3{-oh(`<+mn}WV-k56^w!ciE!c1Wvt z@7)tH%uGFywYXm+vS{=(?0w|?BXY#L{kTGUDmzq3#-h2ISJ8x+T8?m3@F7=Dr6O9e% zhYY(_bxs+48UGYn6Fl_Ow(uv&$->JZ1Y@Eh9p}cw4VKpq+qynG{;Hrs*<^A4D~P+1 z&#Iq|r;_0U%^yMOq}*dfmMci&a8X9ChEX-Xy*dO9_9pSGud-;J0Xy)&LHp|Nq{;x$ zdDU>N)*kJTohPt6J9OIs(slB?!u=kLYtfw&khF`$*r!P<3XbMFRLm0l(mZxVONavN(P~7~|#T)`sD_XAzt?Qtl zyqP*&SCObLeiN%IlMl{nO=i^Bg=2|2N}&TL2kol1C=1uF%os{#pD@DC0%RrEz*~r@ z7h%C#yF<#p93ZRbYt|_#)sp7Y-pE-!*U?QJHPR+~yOQ&cq5GfRYa-I%{x_7u0lNv;n-GItnznF^LND;p0z2RA_ighXvf%9mCk-g6{hT&)N2N;k zTDU?tj4?k^xyz=h>vsEs@1=+*gf<0pflL)|6Px;~?S8`^1PguN74(t&HV`!Oj*Z~x zj19W`2e2+}%Umq?5GHJc4b>z)vR2NT+~3fmkaWVU4e^`$bkm13-e|R7VjD&XGr0li zwj(igdy|gqyE(tdxHjRT`093$ShkYc9Ish2T%#?4Aa#Q|Hc30Ie(1TMY1Pi@Wx6`I zU*NCvjleqO8-L)?&EC(R%($Bk5QqjSAHH;icWhv&jgBoVBA-zFbEGT8>3{AxF=h?5 zh8qM-4y2#7Y_e{5oOzRK$Gh=$9OXat8pSiv3}@6oVY7iY$`!^ZOw4U%!c&z6UP9Zi7c z3~5Fm7hodZo7;A$OwR9QyRle}99Pf__nhkVTXy3`hzGx zgrP0H5%zqZEeT1$!}nB-TG2N5FyJV9alebg*v1Z}0yX%g!QHOXPg?1R9>9yDoK!4B zzaOQzBhz@Onf8B#-?f7`JldMcWV=t@pQ3O(QK^FUDuq*96s6hSVNy>Dk@u1ZX!aXO zd%15idb2E#c0zZcgwPGuzDppbjK0fjQb~@ zJx03LcBX64aPDioOMnW{dv2%{2-;x5!wMLj6Uy#f8+*I!$OqAMnkMCz$@jZuJB?_s$om^{6j0vXoNMdy-3Mj&R_x(~6OsGN?H!Gm!y(-4@-Oe^W|zMmHUZ7M z{25-5;r;pDo>&f^*}2QVk~iKV`ffi4Fs)FHCD^Ul;p3MAZoh~|Wd|Qism%VT*)Cs? z-T$RD0s`inFrH1u{xHg?&>yzL!s%_^Ho}DK%mm)fpSzPV(%M5|1LaAyFs6$WY&fE< zVh;(DL)|AOXw~iwatN5{jrexXoy#FeKViuROW(giqOU!iIDId<rrydxwCSnbcbUkE#WK379p|~Y{`gh+Ew6CpEh&vI^xsF zn8kf*Y&jVb!ryN66#n$7kVhsQ-jUhDf$;0rFzE*OYf=Zm{~fs_FH{8WK@qSUzyb|e zvf?%FJ2)(?Xx(kEyX~y6{2`A2D}7HA`k>^!{-oc!eQR^`w$07$CfI+-u{5OJ-sW*X z59%cCpHF?Hjlm!YyDs7{Ow|@;CTsR9v(FAUvC764CHgm_brC%7*7MPd?Yf~w!wz4w z)i*S=k?YsL%y(Hi4Z5rkHw`;4H`ws9UFxRr2N7@a>ruRH8@JCu#Gkr1)zRK{Z97U- z{@gD;kUDDAIejEU+-0w5Qn4Q2N@(~8qM8^_>p&0wviorkYOQh43xTLkc|+QwM1{8b z8>j@ohuH^x;0Q$xwswxg1cWrYf0p@oKTPU^gGNCoHo9+G;Ts&>*2u`;id}@?_H=vy zYf|ouh|(q1t=4|KUvU_((guE_!kp6Du)Rwfyjjfb-G61r-mk~mUG<8zhkzfj!&R%? zr`XNmWCwi84HX&Np>E9SjqdgC$2}}_o6>9Rc?U@QdFy!r;SeJ__Zy6$HXp0t{A2ww z&);>g^sCPux~bhaVfEoCXv6_l?HD`vBQQ@jo^PX1lYS1Hz%KJ2n7YBQ#M>t|rH$Lb z(qdhuE@Boo|M>AJ;u}io=4kyk&qF+7BKWgY6>s4#b%{R}1)2!TZmus0CGVaD$OM%^lfFL9t)QvU1gRh5G1bqV z#<^J~FSXjV##zZX4U*M`u^uUpMP4FGJ;)#TpW?CpYQ9V}j}`axCne-$msI<6sukAK!j+qjLHdEKf#e0!8|j%W zuS~qEzo9gsOOrcIp4Q}P(I~Ac(}irZ_S@r$Mz1zeMibpi`&GQXsR@&{8$L5nQe%_( zN$M-+`NIeFnO4M4-x`lTaJA8|z6}2$ql9G`+<&f-ja=V5$S;YX%(s$(ok1%krN2s< zKhArX75y>DH(w28W2|K4GS<^GbPnKtO0RGJ7JpI?QY0q5>uO^eV`;3HVyZq~1T-Yq z{z)=+x|_1>&+Cu4t3t4Qahwr2Bid%Vs7;BdGGZt9y1D* z*HYrsikspUUVpU}nm8xeveme2=^ed6LzqmzCLUt(YC{;3#DR~}=T*EXCS<(`(3*eN zuqJqAvSv)?M33w#`lWuGKOD5;@mB8mq!NgGZ#?~zSDU`p1b`R9_JGp_41pjOx`pyY zAg)xQpJ9gR$7qsmqD`d$s}f*NinB)4^P*n0psNvdM5ll=K;u*$e=2^SKN-=nMiN{j zV7>UidLV|l=V}le&fi0KA<1y=F$OVrid!na%wy_0USmql#e>aUZ7`Gn#A1AaE(`ou z9=KX>i3P07NTip+%*IsSttY~?PPRkc`#WX8_I+6@S|t)-|hTw&sED1Ak|ZcZw^v@tX_ zyL{bc0#IH ztHEb-EchfD%jH;jkt`_5;LX5M-}FS zb?|!#<}PK;GW`1h`6)X81T(%EkZx+O4v2^n+(Lsv9F!6VRs4jYF+lzYXmR%QFE9G? zG+#TuaO(6aeW!SC`c6LN+`6xAUt338S4Y?0PW~U4o}y;z)Z)^@?A+Pt%#EiePhH@< zs|WU-x-_-0#D(fpe4X{w$Go~zJap}w%&T85RWCJkV!=91t>*=>x+-}AD9Qk77n?wl_JE0IS zHIj`Z^wC}1b@k#it^sBa50L>TPR_RM2>&WG=>hg8h`gN_O2DNUy9)TXEqtES88`l=0rvvP|6Sa8VRGu+ z?A)|??*B1M!g}YY=UNw+F6m>r|3|*m=ilA+mWP5L{~@YqOQA2%&(EFB*`L|DrRbL7 ziCn((`dkp1T$M<$A;H%>oPQO&eb>&)T_*(brOS9+sR5@S3J~eczH^};ATz;l?B0oBg1Yaq+Hrc7=Bc2i%u{MY< z!+vRQarW%o^qHI%@$VvEkl#~f@t!n5m0*w+flpUuYXMs`QNIy4v=2Y8L8HL8AS?Z>h_txRQ57_FD#q zMh1)j2IXfiUOF^$@s9niix*qZbRJm73scnarR=5YyIT2F_DeCxi~GKqUCu0COjzdZ z*)#CivBfL@6BEr}oSwS?UnTdGQ&ZvL;_NgxQ!}lXzn6VTCV;|4ti}0hDyFAq7x|8M zD__6n6Ww!5p{F=t3LZZ{JE@iw&Rm+a4{o_DSKe+ z>BYrpc(ica*!Wn|WN$}ky0+Q{J zbsg64U@!fmeBVIdF$#gL&>7#ycVoptO2-C^C;B=%;%jGADv4mFQq(&!cA{rsT*HnQ zZ?z%21ZFWh!&l&0ed*lf+?n&!3js<)Z-JJ@$Of3wPa_PD3>Ak9*5C$#Q;Y_N$BV0H!1Hc~1S2YYTSO$-l!*s)^%*l=Mi z>dp7xQjE^hTsU1?n2yFkR1fRV4;>o@i(`Y)*uX8rhX3BqK!@JW&iJ`2zV3~$`{L{V z_pO?Fx)G&_2iEh!GEDtJYF0g2hNefiCb2f2nV@XQ&wUjF0F0qr$-GNFh2gSRB4(ygxb)>59e=3?#~H zzOI0O;jMJ%9nCLk+KeKe_iaLgx*TdT>;@ z08a*gXW%_8r9%=C6=3@OXbc3zK(U!T7cW4Sl?jhjeAOkcN%|%@$?>H3-Y)`l<8N zll(%!k{D-Xa1aKIgXh@Kv?&ASvcks(QrPG%dX+ZpOdEkS~s_&YaUeIq$Ts%L$G#zj+ zF-cHAKB^V;kN4!qqmlmG#zzN+x*)4GF;*fhEq`occs$})RhAA)NsAI4F6WGOZ&X4K(RA!CK&FBD#_vwUB-fR>hWPLl&bx2_V015gfbzvC)&o;h|#& zWpA)P*Bh@Slv_r_==6orKpiu=NsE1DV(gE4`$mi9$Lq^?2ZI!KjLLLenoE335vTJ& zn7iNT)lo7U;vEN(1?S?pk>cn8i`Q*ez`Klxk;ClcKu<3k$Bd+O2`VER92*)vAuqwW z_=Q3{kv|%=cp=|6WaCPL6T5b1b|J!jn!-US!EF2_Ni4jj-ud|;CZ*1?@lx-^;88&@ zW!4e(50CVYAL}VEdT%tbIC*xuZ}QUlrN9@a4Uz?FG5dpNHy((!cpj5iHWvwsO`h_d zL67Gm$T{mVs0d0<4AGnEBWMp;ZgR;@JDGY0p_y5wPAGq?$EA;4wi z;u6RUfnxCI48LT9=-x3oH-+^JhDH7?vL5q40uaUo++|E`@-B~eU~D9)jD3Om21n$0 z271IsFpm*5MPo`gNB}{@^z0qeXUgn-z#J)SM;tLngix-!fnNcdn=+!K)NJUU&SEMd20IZ5z`=`^dLPQ$>JAtO+&M6JX8JB^ zBe4c(zq|k*dN4Xc#T*PmRx0uPTGI=-ad_*7zvV(BbI}W+L2@C@W$5G$;U>UCvC15> zpZu{O1466LE-k`!h^RS906ZoSKG>6kCc&n1g8mE&FkcQbSlZY)vvp{7c+4k({CHtV zj&PZ*UHeO&%O93GYC;^|{5WnxG=yumaQD#U9Li6>mlt%OIj%--W8vuw7nklXv%zJ% zesOYP@{PMQiLR zoo0bi|K*TXvsxTmyb@}HqrQP#CPsV42Z$5;$BMn?d`LGhiRp}n(Lf%VO@!GDnyg4! zA1JCaM`w0!X5PZV(Ksv|?dXgK#)rqkq`^Pyn~*&Ko_&E8BtV5Y&??}4hv#5x3fLOF z;o%@wh1k**I)kMtU}?riNAiTA@(-ilON+~_-9R7K*A!mxU**S-PK;PsI+O=}!THCl z=vgB5aQf2H^kN*cQmI&QnG{eGI2%XOB4r9fq#elE5oD{k2PwY=jnOx765114!PlXM zxixU7R*M};uo=i@=nPdI(E>5@nY-eaT^b>1nL=!i3Ya5_OWY#HMQn=-*dh&71atP= zV~ZE3r_UtZgUL4K&>`){5<*K<>G&8v{ITO5Q3=Hx7vEr1+8b6Tg4r!oE8436ctO&`)C;|@rm$?1rMg$zjcBg>d$xn<5z<@g( zF)){yJ+XN(dB*1!WSd7KEapco@TP0xp__RwCdm--OW_tg8r!QHk$}-JKPqt!@iI3F zy_T*7^-5KD0tG&i2sn|IMd)Zz6yKc-lNVo{flm_d|Cf`jS7cacW)`LiK1q&+1n9pz zV|spR{(H%rCb|q{E!RV((+lKu5(QBf>Gb4c$b1%K0V*Oug%PDv z5*j3~Vu*udPcg4Nijmzs`=B3{7x;3OW->L$6LKc-#W-v##$i)24x5Uxoho9d zl7y?WbaBo@8Qh?8ZYX`>k08=XFZV4<@t6c&U^ad361{C%N6!yjm%s77;P}m!1FK^(tGVwew z2Qag;z9cP`fsb=yV8E=Z<%2a_fu-EZFN$LJ2bIl_P-%hB%xT8~D~^^I2>O#%L4opZ z*X7&G*n$-024p(Q`N`Ov8m7z-i|#x=dH&LLG};eK4HT3$wwTb6frlk1^8qLMfRlWj z4hT5O$H{;=7Z7lgk23)`L`(A|8cV0|mX8$zMcJ1mcL_eO$nBI)!|q8Eo7Lil21w1C znA?a;I53RW7>Z_Ql*3Wdr6U@ipBtK7e3j)F6VD$~E1=MBiSl#$(b>?PEd?SBq` zj$KWX1?#T%~3YWMXFXrn@= zoSYPzTC8*eAKoZG8x*6E;kkrIajVWbTVRko;h=2TwK* z{7h|FM4Tinqlu9b{HCA}LbMUPPfRU;1rH`Dqx`6lDsYX&J#jqJ6UQSxaqg=JuR4yd zmnEE*;j$+VO?t2fh4I1RvLTGQPo5)mwd{tru*~sC!=w8QN|_Y_GBz+VB7bZ+1f3S> zhv0!-#d-qa{w6Y?`U?eG`mRhOZo>v8XRWgGJlp;Z`qq6^{su_ zi})Q=v+R}2{bg5n?08T%g%Me$<6#HTJexj6M`_gjC4u+gpKTe#~MvMqNs@_4QI8JBS z47Mo=Irt&$1>1GdDEvk?3ikhUE;bAw|8zJO+?CHCvN+EAjn4Ynu zdr~tzG*C+JzmGiezy0Iz{OWeQ{T_OIVfv2Qsp)o9ZE>t;tbJ_$(gKf!6Y-CrpDmr6 zCbB7&j*~3qSHq*TY$n3Lw3vF8h4Z7uTS_CN$Ht5K@lyVlJPep0I}weXAp3*QUc{}Q zF6mdkkYgU{8-pR^UkNWw&79Tv17y-j z1CC6v5jS+aj|8Cpc7~rQ*Uz&D-?zlPFsjzV0fVu8Z^*CZ*}r380ECy~*|;m@2Y`D( zKD0)|GqQbT5v>FZvQ5-Omac$4#H%We3=NFsR2IWCS3l}Ngk$nK28p^REG zs7jLy3zK*2R0YXpa5Rt~Kxs@+Ybkijft5m*IHBnV#+X)PpOBkxaeis!7#lhHsAoV~ z_^`^*?}{mG;TmFShz&QcBV5KTNC1b1LTVWO|2=z|IIvAI%(;d@3PQU+cuAc81aS@#1m<8;ze|p!_3!4~EEMq-Ph?wb4#*H~6ghIrQ z8l^{ndOJ=GL_=^nGf%y0WNBe=_5zYC#)CtQ7bVFrB)AAAu2PQdB?)H15FUhfZpmwe z8y$f$$|ro9@Ycu>0|pKYocIE9iMJD8IF-zYobgftYL`q;4vmcr4&W0Qf&nhb;|o#n zqV)_O$0Lhn?c%~6C3bI-tTVHB%$}KEuuVn`|M-b~f5$O0fs8vgm@g11=XK8^l<`XO#M=FW3%2Q1WRKaEB)$lzSitNqxe)5d17!Rguaq#;jmkVVjU90Pb@1hTLwvY7PhMQ?TW zaQ=n?Fs87>arVnQ2Nkt|m%_ktI)nxEMWYAy(VV7%8irhuYWi1^GlO?g%WPem?Svi8 z$@dKR6=Do?(z&!Se<7T%fq4)FBggol0O%W}M^7{aI!|Cf4Ys|Mi+ckhNgKVobjKtC zq?kESvNNXSP;tndA0`(qIE`X!%a7oK*ii?v!`A=YJyEe2EZX{u`Fxj-k>M2?j6H+n zgodMr(J_t>ji9c&B3kL35wHN<_((a_gjk8|vv+TF%gA_wv2y7?(s@Uf+hd3@R>Btq zF`dGcj?MJkGQJn)3D-WZ;{+)Iq09-R0j#*E3rQb4HXBH6qdUwY3w!Qg?1r@}&1+ACCN`^3#QhS*pD@L-HKhEg0E zNN5!^3^*5&;)9F{0XYFHHri_p0n=!te9y?S9?q`~Aj2jgtb534#Emh5twdNcJc5F- zJe?8j868k(h$-+2xJ(GKof?3xZVQYTi;QHDnl6!BVy;DA<}v0HN1$N18^w)BjRe)3 zh*UIaXqNDs>N+mFJ`@t(Ha#6_+pCldUMRy;aN8)MOS}l+9V0x*Tgn=*Mn`m54992S z)o=r|s$y@r?0cbl6!@Wv)P)*eA1(*WE zFNUePK_B%mV^g|l6i9{RGS(*`J%3`X&-fADEVe|zrA<5cvxN>BC&smp zJlHiLS|@z4AIZW>>9Fkny{1pew1U_$kSTn?i+MPVVzie|10+Nr>p4ndX&HY93t}ju zYOm_|#Wq4T6=?At!pZNuUKCfU{8e_$Ma7N?C)x zAjq@=6GO*_tP?BgwDolMnYO(+y)b+6-1Gvete|)mwlhPqAbZ9_#m~n2u@EDnQ0xSX zNE07qEUawt7Li8)iF1RrgHje8AT?_e!Pq4C3?5o@cI;?`&fUj79)L)|P%t`l5By8G zBy;ep5~xkoERF{@zP*%)VGW>SXpL7KEcI>sfE(~!t7azJG<5LeFQF> zM`pSV5nX*SCed87YT8_0c2X!R#kl1z(JHn$VZWB zMJ=aFO32G;T~ex*FkPCNa;$ z)R#aBKRojQTA}{(wUI4DB15RbOa`N!R&pSJ$N{@ zV&VbW0&Ip1QGyVTk}gd0$_Vk|{230P!}P~b;K<1T>C_VKDwQ{O!l;~}o-A5VPvOXj zKtYNbH+CJCi~DkOrgS!^ZOc3(`Yh87%bOk$w4>;OtJEJfvdg)Hl})$-LRQQSqdNB< zW!DH(AeG9hS-(UOC^hi$!2(!74MfXataJC2F3xi}l-E$^Nb!rAJ6OIhXkE0dscO!Q zV8a-$FMo8X|8`ur|Bt-$bk_ei4|snvR54_G+0WC4TGOjlLE6%pn>>Q)s~ zkE?rc^+RswPCdJesn^tFx?2`zuts787>gJj#fG&c&`QLzz)~z?IU&gqi-!R#kjRc$ zB#s~un=Bj{BS5SLOn(3G+xwh-&b{4|S~GyN`pon_wI63czWu%Sx4*r&vq1VHEyDO{ zAtVL0Iwm_wJo}|bVAVK`dKTYwRAx%r?eDBGfq}XKzD7b#om-sEhbYHcj9~Z=xRYvt zI^Vn0=Z`{Xl)Xe-F}y1gJAL@jOI-~tL}MpwokBwiMT#JTn!;bXG6A$yL8Yy73sT3C zF1z>yL}k-8^a4u_j<8!}5zx!@*agsf5%t43j=;dcM2P557x7XK80OkyPuS02v~gUz zD}=Y;#Z5piUI?;Z^BUn5NQ>U+rCwx$CAAL5re-OPX^s;2SDt_@SN4p;CnXY1Sg<76 zzSzAeDv_dy{^{{zeG$p|Q+=7h2xlton7R^}5_aYM&w{04UCv`qi*e7PeF+bx+ESbY z+Wu50LF{Z&zjWFV$}`cPNo$o+Wc@Ou5_q%=ebCJ^LYXM)3Hi9-m0Ar+Bq|(?SkjpB zt8fpWcp3F%?Z#s@{nYh?dm076mo8r%tbnqrcnDD?GceP$a1<@esTKJ__`e9v;yj;U(iot}&QtE?#CE{%$=6b*ZPrK$ft5_@5 z$Xl#EDmYQT@<}B0tlf2;B0_e;SR>r1?}QW#P+*D#2B-ptGa;YQG|uqoltblID@=T7 zo%9pUD7%*zK;D4M#=%LnsfO^;Cpjw5(K=@ukU#!zYz<%wKwV z*39$S1(@uF&(#?@j7loX_zHa5Mnsf=ViJU+l1@8#QFc|DO|$`=%LSk4`^@>I&l1Cg zg+>h!kgy;fJ@P=Uh@Lnb1y{pNizW|#9!)3BI-4nMu!HK2H>6Q8tsRey63w)N%xy$^ zZCGU8Kyb$Ud1mN$&4KTrRVHje%Or&1n6?D~{-oilT%NE|0z6E_(K+#=9yOP_2 zG3P0pc>6>unmS;qS|3UJ;!LpkQox3V8}^|6N+Wlyw1x$$VtoZIjI3up=UJaJF}yZq zw027@V93F$ZnVUl(cYSVh$%_3=pCkvw$P}sJofYs6Ghe+J$%jt7!oB;r%fV?XZ7AL z6>7S}+P|AW&e`m-&4|xpfS1NdF4t15(I=sImy3X+pu${^OD{bz{l>Zv{Q2Gh0;kqY zF2e{^zucx}QUF7(c>fz49SdU1CjWu6h9vq5%+6`BAH#c=Qk^(8ld~bS5wrfX;^^<# zDLhO)A^?UJ#$fC@8UM($o{2Geo^vqjpVwFpRXao_D-E4=4>EOy!8`6E4eeOZ)XcqL+t1z&e{dOvZ=^D)201iJ;PU z4q>9YF4h}LSM6s(AcKbex@l;_{$^(uGgl{IW7neB(lpx4&?cF`PZoVVc|K!x zOD5&815|674Xs*CzhjE|r*VfVo7M^Oq~@siw9JBQ>^6(^Uzbl*f=C^P6lYwWN491%w<@J z7yt^nc|(}uMr0+KxRqHR!awQaR(kVdFp9ek%?AcBiI7i0OzUP{LV);kNU)pX_233v z3a)U2uxzr{ANr*;0#oqDOu@_fA|<)VkP#-r?R2paak{W34VYtR%nB0im<8BR7hpeK zfci?%wW(s9^w*XP>Cd(0Xwz)isKHC+($jVV*G zM`{eh>_Fy0@M$VAWEX|bpik%euwa5)cwgv#W-dQqXfaqP3ZiUi2g8INc{kn zGX*5i6f}PZnx~{5JqZvR9cV^)+7JwY-l|wcI)#K(>ec}rZxw(P) zt`I|l#>@-KVhd*cAr!#aXX7WjmiZ`BqTw5P$|k#_Yb0Uq@-?q8Yb@4!wP@A_-E5(+ z#H;iXQz7wGwAiqcZF-Y&2ucmAi}-H97&KZVa-Y49Gn*HF$?E8>asWLsRoTNP(nCkt3pVAiy!G853Gs1b1kpqUIdMN6|iW5$Y_HOmkxz7WTj zg%;*DUagZt1!7z?$@?2y>bAe|iB^*IkrQXER5Ju|Q)JLg6O)Y_prYpBDSYIk<5;JP zE6eJdS^`zX_e79%(v^M516z*cs@o|H`nH}(8Q8=6jm~AZr}d|6vkKyZp~96AJT3cX z9eoOi0Cv;hi`-xC@8@~K$5`2>IkaL13k4g-`oY=L2Wo9^FVEh&q#Yd#7tlPlA3xTF zrK*bp7As^yw`N$Ob!)k$uI z0Cq!xIza|^&;-ZXRlhh{i7Vq8W^|b!WBGybg%ToZQNbjKfUx5%<`_EeqFwQme)r-G zdm^iSjKkUzUW01A6sP7F_!KPl4&?O|s8m8EBZI~H$L1F<&i89L)8R)Ro7R|RjVu`m zA?P4iijA3-|E#7fHNFaC_S-LUx74_O(A&(YTHZFG|ZWb&`PCAifMZA~ch z;zH-Kfa9eh2|{LWvZigpY(jU|(gJI`(+M)5Xxrox8;m4N0S6?=Or0&!102^tDVmA| zUS_*hh8x;?N0XfNaN7YA5eLme}O&0|B4JCp2v=q8P3AS=QaPljgy zA`)&gI`t;mBZ8G6=b0<)C@_Ey`*h<+#)a}0g$!!Gon0r0CpD=X!;2I@8Bh@lc+6^9 z9=e(Vfb(pJif~EMR49VPp5w4DS4r|*Gc%mp)MrxAAFn53N3BsyOF}C4t1-I>^Y(oX zu{M1GBU_w>YtEPP#Q0mQmeRe;WbGeNCBEe}Z<2VTSXUJs%33X(d3ArGh1vioEaXOP z=v;Rya7V+CyoR|+1flhPdUph z4~7OwyD96i)g0Ra0!E%i3GCn8?lc^BhrZETX4 zW{?j$fg#4u%y*IA_>PNvneG!)l8#Jw9?MD6PnjE%sc7Tw5{s;P4Y|;FB(360L55 zy#le1ux$9S<7ioqq3P=IKO4gVS(R&xP*@uxyRb0ZqoH}Roo)?rY*5w=r`&YlAi|uy z)ZnDCgvSkVF~j8!nCU!@MUuRNFo46gro46CZlh4LBebV#b91!;b;%_tYlV~H7>@{{ z87$RP%=TE!(%B@UQuaGBVU8ILusBeLbL#p%z?SItv08WsNYb3CU?^HBzUh*ad4b+- z(I$4+i_m5|fw06_rV(#!M~tj@ILV;L_7$Dm=sF?0t#*oOWu8$puA(3Lv@)Ndm8r=& z%LS><)kcNUkaTN7uGOhA>`3#;Ivl6Ui=z%u?F7gA0mQrmF*#He`AQBlL;gj`z0IOF za+BSkm(a5+Dr0~hOu?B>{&}G(sbrggYYg*% zTk${6vSb6e1ahGXsLz5jJC4j85v$}JfY?V#9Am%TX&oFAqd8iwMz75ll1B#Ygv^z8}ykhaWaMOrs4NUzy1WSB6X2 z6nr@<2kpKDuy{^r1fc2l)$xyss;{DLTW>n0$wEoJ=%P;*BW|3g){gq?eA!}_vy@>J z9*{*kR%f!8u!JO`BoUm048RQgE0bQzuqjTpJ4s=T#7v9Hag;J~k8%V?K3_A^*;@LR zM3h)RquBr{pARLdoCr+UEI6ldEze*GI-i(eaq!PBCe{G{T6nZ(&G7PKgB|!oV z&K~k1sSJCGMY11jw!UyFZ$)Hbj_KuTO@Zpbv#R)27y{F%AXZ8OJsBg&+E}kq!7R>c zc^is)WVo|KjMi@K7Q)`BG65m8%cxQ2WdzpgTHt^MEN?8F1p<`~>vllWA-(+)={b#t z<89-Nt3u%bpgTZwkzu<1Cn_@$FEuo=(CWz8ILpimz{2st@iPrpY2IqRSGL4pJ)Xm+ zfG_IqOcMmW*3Giz{uFCd6_lx zl33J;!1Q@&go-)T$G}kAR%~LeGsU??Ntv-3Lrt`@HIHS4`l@fC#Vqay&aHiDV0rJ zB(Sj7)y@u#z^pT2qp+1)4lyGQ`u8&A?l;wG>&yk_FLP13Bxvd9Z5>gys4y)?s|NW= zHEN*%7D`FCN@)`x+7jY?3)PhsSk(8)d|)dsa#2HGXOLIjeHSkQz9u;#LAYk(EB21$hQnyY;V~?8KG6Ikqf}I zD!c}pAixVmwb?mOWPcNW!pl0XAP&`-d80Jyo*~BKpkYIx;^`r-Z)%Z^QvM~&(+Sg&ie?dXY#+!WnL5QrN@BPf`qIJ-T*~#(17dh1E;=ChrSs; zhb-(Xa8IA6_j_KPP0QAl4NSRX0jx5b2*6LFsVWQ`DTHbq%f>@NgspPYG{hvPpY}S7 z-QL>~Xr)*RVPZUQg$dUta#eE$!jT+FQw7=v{qqC zpv^QoowlKrs(Pa-=!aTVS*7(N8$=u~$6`e0pZ1b7>YN^7*1iM%>YgERsfRYUHeibZ zB5J+{+fp1z`LQ1T-Sz$J;ebZYt9r@%u(3nqCug}F!0yCo!MJr&{7e#ulkJ$TKQlFJ z_UlOso^2BhUYZ%V>oHTHwA$TB@|F^sw@P5kbKaKH7p-bSyTJ(`i+IJ#x3|k$Kzm#= zLVH8pRo3Fh78O^NiTGmiZ*qoH3oqax+ewpziN#`0@r}_bHto7*$f%EYs$r1~5YF~H zmu5n9xH!UEU?oeNthHw0apM&@VOklph7<)sD5q6L(k9A2+3!(yk&CEvm9nU1Trh8S zE+rY8bG62VmDjE1A~Z<{6cg6&qHN=~l_ubj+F!hIv9Ci^ldoyUSid$`jyYZFk#$m_ zDXO3)rz$m=x-5fElC9gN_yJg)QjIS?N$fodO~~I$8_fNU52J-~nalB$-VKbZpi=2@ z6O7YTK?K2K16RLzQMhLz<8dq4PRrEjR>69{f&yv+R;!+QlsMheP7U%&6Uf;d+>nxW zvRctx>14>RaZb*{-DmHRL(sV1=@1cmQ>VBfNYx%4cu{=AC|A1}iaC?y3Q=d1C}{T# z2Hds|2G4t6Dp|mrY2sH@)W%1rZvT<6q6}W?qZO<(I*Jfa>ntTy_}H0BxwPfkbUpUZ0LWOq%&5*!B561V(qg(nGXKc%&Bh0$BC}u)r3K7P4!jQ}J zr*#UO@;cLRN(pK6DeP>8GdYlk_XzOjJu2Zqkx)U7A|aIq;&Y%`$VD$067!X#BHe^T8NK*q5GB)2dxp@FN_&e@PTM=Pp!J3zZ`0iG}N;sKx zsFZLjNuX85;H9HlN=O-QDWTGjqA1*XP0~v9OsX?cQq}{|0Q;DzX4rgJ02o09v8F<* z+nk=6o0ERgoLNY68dwqW#kUORxeB3ce5IN2Th16_Q{WbPQ^*#vDOjoeOrOeyS+LQh zY=_cq*xJwx?EiC4k83Zp%2`;frggCX@U8<^Y2;<7s`|4P#5Q(!aWR#s^kJ+*c7j?( zKrp{?u2JrdbhQdSc)rMGIIGpQtnzmv#i8F#hx};^0m{Vfh}{bsrg~|7oQ|s_?6K9c z^w`Q+QupmgY%oJg;aX`Q!Yo`@GRtMDZIWwcjSYR!dT%$9l@R*02_2W*HaSRuECRx0 zjWNIY1Wi2AC1$#=P9*8#*=0@$?8SzvAofAk?Nf%5U?haCxwcFpNsSCZwL6qZBW@4T z!3-%x13pySRP=*d&s0#l)Q=&sKv@Z2hh&*h_c3$!_7Bt>;HETqbMz&Tg#Q(09?NFiQI zNYSp8kZKDg6go@6BEuA-)E6X3-|RmH_&`|c{MyFTXm_Jgb|5`vqv4a3hlZ$B!3a^O zlc5SxY~UCupKY&$aYHJ_RyUY$NVV+EF7g2(4WW-h3OdtD%B)!P@u^uYIu_siOq@w- zm^IxJ!-a8f{Z7Ab%$ypWI-JcLR2lsup)&eKLfQq;pUEE-(XEMrZJXI5{Zbw3Txw-& zn;dQ&t}-aPW&~cA2bAar5KavRW^Vf~_XjnrG-c-#X>ApX@!}8O7ufNnG99g&lyd}8Tpfq0m*pApprMFTG&Z_300uz>6EKDDd)ge?(yN? z!lM5GsF*8M7)g;3RWjX(SbR&XPnRtQWjmItt!(;$(&5h%&oC zALoU#*n$G8bHkE3GXdnJs|akCsaW7nRmxK zd6v0^rX^BqJ&_|kbO2k4xQ%(1VQ-i;oKcMRb4F1HT-Ai_jSS*hAP`CVWT#tWS%(-Y zEn=?DD<^4q=t2SvFtTc`CJNoK#IJ)6axVFh`iqIdFyRxvIiGyfUYMK$*|j2)#M1DA z8H5ZPOzDv*LYe`ni&YKK%%EX3280(Qj$cc=qEa=8Zk5uEHqZeAxufjm6^aF)}K;>Yd4UqEFc1g z&~OfYauB>lj|=dYz$ew#Cm$*Jj9J8ll)hyRDi3R*_`zu;2kWGAy_D~k2|j&Le|+Jw zDzrf&mjp#8h(eVGA+@w$ok6E`qH%zsRmQ;$90Tj3G*>g%!ETijQgSOLR61A`)nb}& zN9JyE;naS{fxDb@xkHp+i{Z!hb0R(_SI&3c+n6I;w!^k;)c9c3#9-9PBx=_S zTS*IxacOBWE-fy`o%~Y(3Ehrh(b-#BG2##x= zG|91gxU|VYBrzdV8nwK%{REjRpBAy398F^DKw2be!<6y651X7sGj>}F={lXyUYrD~ z5J!9H#o63?;g&R52&yeh=^Hz`;oQ%p<~lR;+S!0gh~(R*`KJwhi=Q5M{4_h*YnX!T zBr9^7Gt0~Z8;M!9Qq8)kWw2h!i%i8oW!KrYIT3@CX6!|y72;F9PI2GSwtH@=DEg-w z?U#)F?NxBVK7Vtu7QbigSJw+RJLl~8eBQxz-747L+UA6`QcK5}BCr*4>{MoSA6jMk zIF13fKiCD$L}R)8Tvb8A@=1z)A3NtIy8l`=_SDe4+*dWEgtJ3q(Lfi>$w^S`tSxcn zI&~Y^+r&)Dyt8n4uzPsm&>K=R7%?pNv<-|EFtg3~Ryf8|#}S=5Vt-{Tn|tPFss=Ri zEnPW)33b`qNrJ8h#Ldgl0CSKo^V4tuNX~pP%ad+kaS^iPY!>+0dC2~0>`H;}2oBx# zUTQH5Z$4@u$v}^}tqfO0?k_5R5(b*{8rf`TjS|t&HmIe5;KsJ~+KQm;!D5)9spiUv zdEpc|q)NzSSZoD9LJ1sPoMJ+Vt&CTQ#mR7hHl@FCHREu?CDG6O1uJKf&$D(MN2x;Z z9w13$$H#`Dbc{VcH1Am(!1*Pd{bl3FERVcg32hlRwg2#H(qf}-^r);Z>$ zrMe=iRe%-<5OfZsnf7HY^rbRXA+|D9L;D>|sMH$rR)#9XmSGf2s31|uTOs=pd#>E` z5PQB98%Lzvw-{UQTZ}FDBF2_`F@9a-_A>H=h>WKm9-LgH)$L!< zNpj(sz?3)~234X9vE|+dh*$7B#+G3aW6LmzvE`8r{i?Jf#+KUmn=Wj7LwjSpwz9&lobh_P{c9WR$XThzQV~HMdto+F2s52tAq_*ELSSN3 zDA=svUVvBy_hRhOaj)QB%v*+7j4eYf#txJDQnpi!3{a@FEXI~w7Guk8h_U51#8_;R z3*0u5RylTZC=rC%a+NV}8GT}Gxyl$@9{dxjIDqulu&MO z%v(Y1khg-^A-3GNSVFmPG4{Of+1bJE7^`av|1dOT=XEY{n2l^~mlfYKB%=Ox zE;uU&GtBM_bA&EH<0{R~!?nU#aZ785*HWoFYH@4>9GE?`;5#&SKH)q|yBpRe^$gfB zn!*cj(u=<7B!cHe`~&l*+svrmDVsmM31(hN8Y&Bj5Op|KurAKHpdx5=>=y-rztIo) zMLpmbS;#NzaQw1ugI|_R`IQN(qsjchK&3-r(>AqDsN?V%gt&}5)7{LlCSl)jA`e0Hf z8Z&eo-e6CBk8l_ZGjh3A%X==c707<=x*?4l#CFVB=Qk5O^$ZryNg4Q`3X;wXN|stH z3&k&5E$O?&XFFIw3ZWSoSnRM-a8xWR1RBJ5Sq8+s%v{V;E7Sw`wX8zRiVB3U(3q`56G8T*_l_^t*Eh_^tZ&@dcv6UeS zB~+wSh^-7%h%M`6vD~sw7GujgS&Xgdo1xrt-=cY_+_xB8?pus4_btYj`xax%eT%W> zUc}gPFJkPl89N(E22sdG^)1XG-ua4_7XVeol#sXF`Ixud`50U7e2g91`AQo?H!E$3 zvE??z*m4_UY`G0Fw%mrXU;-~AL5wXUL5wZ8A;y;55M#@2h_S=lP)357w~Pcamg&RV zfh|vz$hFdq32q1tOB&8@_REZ+(vAv+RoYXgp3soW;Kf+B-VAWG=45@*FI3Ohk%EDK zDCjCi#8|SMo66k?3RtD{A+|DxA+|DxA-2+x5L<=PF#B;-0xK{JB@83kb`z~dYP~EQ zykyznCCdgcSvGjdvcap|f(p#5lv3`Rv}tK}z7C0yQ-PsM``at@`n)=HB=Vpm@r#bc zZ)NDcSCwW22vk}VW6O<-u@&kF<(7Lpc6O-2BE(ikH^f$I3$c~a4Y8FrgxKM2s1k^` ztTN`IgbLk;*kPE!+_kb4w>c`IEG3r`iI3bB+re zZ^L3MRfoKl5eTuB5eTsrqzkc?5eTsrqzkbXqzkbXqzkdbkj`!VGVu>`>e2*%2mq=h z;?-0sKg13NOBDq}Ug@H7`kh~Y4*#xg7(nNFi&VZ;Sdf1{C(G|owskTIX7Fr+fFJIg5ua2#6tnY9=^Y-c{HjYq1qczoU zb~yUJKgU_RT7OOwZ2lCEDYj{2lI9=b&}a$EJ4@X9EEs4~9x5EaRfY3xatVi!Dle0t zO5?n^<->ymoHF+00+Q5>(|q~k!c{MJ&cEN<*xcOM&$>7Fdm9{zIvsj`V|RbAJY5$M z+A~}$#0^9J{yc}B_VM;;?`>d=Ik=f!zqW=UmXx*arR7bqaqr2@YuH>{4fddwKG&TLO`h!cBDCmf&{mq4fewY{g-R>z7zb1GDGYMiXOK$GpP{Tz83Zn!g3kJ(C6 z5X(@=wP_sCq!YWHU`k`a#T1L}Sfpb-%{bgz%gNEMe2|-_qg=K0K!m!=$bB|7ENK-E z@6Jp&2Y0oIqJcB>oI9TFMofS=3{p_?b)a-k#ts97&nTB=?`7-PRyV(lQ89dDL>S!V z!}V+f_thI%_ZaytZbe(#*a|6fLCdz+uJ^YNSvkp8_cl0dnCqcp-W%(%v*j6`=CZ!D zvNrEF+=Iiuv7gno-Ggf!3An$~-#A#eKh9-4`%9Z%9C)?1JF&X=RMwNFt~sgQcbwP7 z(dnG9-k<3%Fl@Phi3ZOZDSaTAW zbZ1Cc3cz&_mm8Z)`}=sg0elWjq$_Ky9FH^DPO8b9n(@s+UxUCQjD2->pD$^qI0>Z` zjq}N#wSH}z^BD6XBmZj59xHVWAY}Ouf& z0~BJHmZ_odG?gtqwY0G*5tkRK`oY?Kq#Qw(p|Q#B)!iLhqrrAc^VK-P(N0k+AOp5U z#N*gL2#gztbi0=he~fM4)|zPXNuK`>nEw9W$_XJLtfgpp8@KqKm7UGJ-vK~wmw(45 zOIGXsZN}g6-dIOitSLq;$H^4LZqbhY5Wr3juf)c?=wg{|q;Tn7Zciq#s4sM@1)AaE#*Yg8r%Pz*#&RR7DDs^5^e_b_S-`QI=vMai0RnxzNtzCWvF|W-kb}-%{C9T*6 zb4F0sTd7b6g8gd@zi(%1EVM5p5E@po*T%|kfA2=#6&tEs^(2-DNYOcc1YyNbC>*Lv zU|?~DbdBK7Hdb#;Xn>Y>ZIHDgMhb-#2a?JqXWO$WQpHL!pY}EIf~K*-yg3G6+7olG z?Cjp`Z|$s#ljfPclUYO^n=3dpRzU<%s01(eo!VL7eXbE}8igC`YJ_R~R*IUqdow2} z>Q2z#crf};-XL_y9r;WNVh4LWo8b79ha7;+ad%JcJb^ojM0`xl`lbmz$uY;AXeq}OZGdBHb;Mp0aW6G)LUH%LT_V#r_Z-LE7|J$p+RU>*R5`sPTR8y$ZB6B z6|^~twv}aXLD6u=BZE8;s6jy4-`<1pVa%|1%~t5VJBMqBYxH|%4NcMc8XzDl)Eg_% zaD(2vn`=nK{A6FNLrr!mzPq%sC*^=e%+Qu6Q6pTTTwQx=!{}A~#ngHFAmu|k%ihNB z!H(^+WX1n*Z%Okd^%1Pe$E1L`aUV%eMxXX2pV%U+_u@c1x7H80SLlhUMV_-5lGbF+ zP8#Iaxdl!izgT;0lKsTRNW`8?6saxg5ICm#immr%u-wTeXu$ogy`)Uzogi0j1*}a7B z?rrp;tMq<(2l5N3&SB%hsE||Q;kMBtGm@a&#b!$dX53jNMgSq0bmVy=@of^q^^-c8 zH646wvc_}sfUoU?oS<`=TPD2F%ZOx8vd?Q{eFG*_psORQdUm+Aa|rC{(UY1E21K~F zarIgxmlUQe@JLjFq9Ef92TV7hum08ms_YzG15+JE%Hu|bk<&RHn_~@x%IcQkl@Uus z=cUz~B4Wq!gh}jcBC^R2WjJKe(p^P?N$%K;F?^%0T2F!c+AivUh6>c{EO6_JZtv1< zOHf)Fytxu9eK}X5_p{|jO5hjF*N3^OypM_!43{W-zNx*~1;CaM_it9}wlldlN`(gY zfGw`Tdr;hG$bIh|XWmEZ$ftfwaUxR22thc?5o0_XOnt8RGy|Dk+rG*KI~T}?wRyol zU)a*d!Ga4pStPuN12DLA2`3gaHE>3g_Etyq5gE!pAVmtf2K>vy2J(JNIA!gExGErw zoI`uxT@dDj6uD)Ov&#Jvg=Xi1te}2xW)wYZPZfa5rxE4Rx2uPQBH-w@&e&o&&8T3s zzp)>qEm+8gz{7F^6BRADHum-pa%>S`3w{Q($c#E|J`6%{Y-jt2<|A!5AL;={p)sZb z=nEfDU?$`Ofel|-l+x*>ej7XYsU=|Lcl4Ko{WovC~1-*Me^ZmSr z*Ui>qJPXTj#myAM*Du9vw$mBtHEDvYIW^kY2}&? z^U5m4UGUpInM>U8FV2w)A^xsDpZ?3R(|eoj9i`g+rv)k9d~g=iHlw(X8u697hXW&#Q=vyoQIR5y32 zazKRc;hoBG5os)KFYc-a2A?)iyI7X#tyXaOWZ|*ANr#qQ4T1~r4(lGyX{MWsX!tDZ zEh=B}(!wxU9ax9B;L7x*zCjLdKQlL(SCtPCl~vmB7jBhm=h7uklg-wd*IW||V`9fh zUzM!LHoATVy6Oa@0cF?eAhY zkjkho8;bbAHx0EcHo*)|@8K>&yGzQEH%Y@X-pR|3B?cf`!Ie?+V|OZ%T&p;#mS1F5 z&M`S-sf!aOlrPe2wtT(4v$-i8*MzH5M7+&+x$EF>Vt93v$Gx zPd&B~BoG^@E=VQSVrOK*PMqMZ4oIoD&_Ds~^s03-WvNDSvmjg`3%FD+fC{SFTQi+G z9cy2WpI_)Tbs7qz8<^Lc{jCKp%L|c*$|Fb}%?)HO`PAj5WxP~H%#kUsMvjv(#R_=i z{ad(A*kSWB$!|=oXkUs}3*!XZZh;5uV6bT_swfxuOzLMrEBeKUOpUp`rqM9x=hhsy z&x5rMTVyR|GgUr2h|Db*U-BFF)H+k*AoPacx{j&>vc?ZsvVt|}vr?<=+=PqV)I6VN zHZx_?Mk$~6t#@pHg$B|CAr@@((9e+qMdjd_!cDwI{*azik0@*VT!7E*qPJd z%CM|Ax4`Jn)w@OOq0NqK-rN&9&w-@MG#fR2v9JSH#=-2F2@b}zi=gbfUoO$>_S&-u z9F)Dim83x3RzJ?J46X!58SF2sIZP_!NVq={n3=|8c$N5?zBS(Fh#>V13eU4)%9I&6 zADJ`_*@;=a!QqXx@}lhy$;Zci6`Dm0JCki}G<`^$dz9^7!lHH3b74X=%}EhYUiZc} zYIFo}ig9G-w$H~Vxo4@?y{yX)8aTcfCGp!d2bp9LP5U#t%!`(@#!O?bGtO|^+kWvr zA?_p>Y0WTVJ$|U=V!LQ4S_X4IgHh4*uF$ULle8|D6oZwiZ~)7jJsb=yeK7a)rA}e( zxHy^yzQ}HuqMq_`%^M%F%*e{ClSTu&%!$BO54W~%f^8qhi*XVKikl zzsvzl+bJ_Fu-=-TCK)?TN-Ds5Ru>$GJNSH8L&1s4V_Pr*hherQX6xS=8iPMtwc&+L zpPs&RdsLmChP$I4No?<@I@}1 z-~h!9ggXz1BlaF%-q|@YeB3*snVtv{$D#hp$&;GtMUJGXKr1qyPBm(Xzfkc|xQ>qr zu*-W9LL3{(7qPfVOb3OR0QL696%8N?` z{G?hFlrMVXPFeK^A2KrH)C>AEj$!&Cr`=C4fLNSurxW&(5&$UAY0P!PnX4>HNSg%n ze7xda^8*Q;WFX<83rM8LR7pi(BkA3ciR#Go$hoycFWc%z5CVGGHD#laR&)`|`mOvxP&Y^aN366_IIZ=!W$MMear8ju^3wTiaBGlg{9GW}2T z)0hSZ1t?NnBO$S(eOYssEy#Jp3#=3EmlQ#;jA3HHm?@do1&2M{G(EBSKFHq!`=)y4 z4%Vo1sc42rsC(yh7Wu3D*bLr*GN|^)Zk;rK>!gWWC!M@?(y3b~oxXL_nOi5F<@i!e zHYm)j2e?8F@TPjTrVc=lf7G)U%P-Tqr8ry*-E8&iQw#n2Y;FEAo8v+NE^2G7y8W#S z^lB}gDqd@eJZh~LWCj$&@m|e3_uV$A0%&p)Fh_gNOijV~@aS{6x*DsbFDer!6XTrG zn-~x8Q=!c|IdZmVtqnIkL$eEwrkge(Oc(d`dU=ym^%~dKbPs7`7QMkR?QpjS1MK=G z4-N(=UKxIvH1hK4&8%MP;$qr=uc_YR zc2N%atof_%uZF*x{+jex$jP;Z)<%S!^;gOh5ckMNY&hqu8Rmf+IzrD=n=!Si)R_e# z<;=n$MglesvZZ!1xezbouvQ9<$XoNcT%x*g2oQ92zK zs9(%iar(`XCa1*=nJqcjN{DN7GttEG;Zbs$OmX(k|xC!XkdA zy+*6OV84sjDkT-?xuJH!I8J)4Pptl&TCcplkE zRtK_=F^PspYIOt7&pHe42|kyhH+813#u56agx`Y2xYY~VUT_{<0cD$GEt|LrU+A-h zJ=JS+ONovSU??Xz=eyo(ItW{X9jfIWG9Y)do#oYaXCB#ntB&QO?MQB~x`!J6YWi!^ zUoC%4`70Pr^9wVaxpKEHj8+7PHT3FL(CQ%I5=jKNL;{md>f^K9mHj=SgXW*FG0 zdPhr8G@vs4*dte2&a)-%A?Q}X=*%ewf~lLn4a$~GRB3(k!WZGd8DTNZ7qotyn5oL9Ly&!~m1L;g02xX>PlAVfuMc=R_dv@mV7H?6cc z?X)*7wKvB$NF6{3DL4^|bwNuw6gv@$oe0HFgkmQ`u@j-#iBK%kZ0QjHob3`zHEJ&= zF~SMML%&e;iH+cF0P$F3PKL&u#1lN&$ZSO<=QM&Q*LFDdVf$voemM4EfWdKRLtt=I zy6~KDHdY(pkgP6^IYy-BuX?0Mvnz=hx^ogulQX^988klsVDlw{+<<=7tt#Cl;X-2Y_qF${y2?>vfLbnsrC)<_7i zJ*dMLkhEAFY|TNse>Z9|w*KmBQHVora`gc=P7ysR2>D;!_z`uBoK0QRj4LR1W|HtM zXd2;<4ig0V^IgP4bmzKnAi^GEIJC64w{$aPMEh_hAkI|$dvuY7I+D5Nuc*}o6ILxK zZ8XO}7Oy}~<1tII4tHz^rYP52Qk3f`%AR6Y1ytp3!*FB}*5e|eMi0)UU*vTIp*O%k zBZq>^^cv1HFSdmOSY`2)Gi&VrAbxSTlI?Y2zE;OxYD31&BASk)46Z!UmTx*s|D1)3 zo!=U9{*R_yza=@KJ z^8?d^x>ajlSH;{cRi;6Ifxw3aoqBE_?M_X-r7m$QSEfuggWceqjFe?t0bV&#>bc}y zS?}*}VV4Q=x8_QNz3O(Z2-=i|n*PG>t1K;lP5BF3Q9ulTqg91@Sw4Xf&ueH30q5)V zoV)W5^Bw2zgpCdJHa5)L*f4Kn!@P|R^ENij`#gdtOdrA@7@{Dtn*GLEmGN0-SH|pl zhgzJ;6Aq<2lP4TXhsk@PHf2yXFhI=((L?RE=)G}1-s!=|JwMR>;c-+Mqa0(IN#)(f}nyyofGVH_ompt?$7_d;h!>|>g?6D<^PQ{Ji88mBglSSOVq5sb1!79%Haof+CdQr% z^a+39&Lrhar}ue`5t1;=W{-6IHryc0gSrhS_xvC^8n9n};Jz#!=qFYL8o~V-8PKlR zWLY6pC(e(kv`TbgMc-yQc9jbs2tQpb9j3LAL5h^2a&vKGQA?pyOlXaT`x^ydR>kYLPMQEpFICv?4le&T zBamT;WdeRBR9y58^dO3meu5O7)unxo(v)O5)@wXh)m;O~G?$H29Q5+d&1K|`bg%gq zHy_!r3=OVj_*=SiccEwE4Q@VM0>n#>`o#q+j^jbe2{&NX0_K-v5iJ^1z%@8fVOMC< z&6=Hyp5~-gZoGnazex@^A|w%xe@Vnt^%LzX-8nc7ro?%<zklN(p1fuqKcZ1e_#p= zsDUk3%h?eWi;L=$9z4@}U+C4-SKg znG5Bn%f^v&v``$p#mhBp*Ob^?RvCLWJv8aBmcMk|4_UO7k=yUgtTL1xVTUlP#iGP^9I+Ht(!xP2C)j+t>e`;1Cjx4+nlvd3)ETk6 zju>rOlAt;jvqLdx>;R%pi8_0?>k9ivWwX zH`;+21~0WZ&{1jgvKRWBxpR9QGa*ECZF4nFAmum8(nwVdPnyUP5kY0t-_BBOa71qF9@TZ<3`D*5^6F(eQ_K z1Rr&O&uUucgD7W#zz+Pl3%qX{HCtEGRLc=K7m04gaocFyW^59Kh@t|w3k!4$8}=fr zYmgSBtQ@Q~n6*ML&5j#!{i+O!A=+CI)S}!l?ilHNlaUI`1l4QJvOBg|Y0!#-kD_tb zU^H_p0(fHP27hZk!<(pAon>2x5-wZ*$F<#Tvfi7;noILxYp82_sWZk0?G@5c+Z3s( zJ+CQ$O^5FnP5qUnDNOEtH;5Q}0~-QA!aNx@2i~%2Mx|8$c;WOXuYC>L?M6h|V zxo3(h%9BxQOD$I72ixl_`%CuAzPDX%25-q*8)M_j6D_vo3>MEO<`>89Mg}4LZQP<6 z5FuwS(xe)>-A8jR7M|#==34wP@zh+4A1w&y%8I-A*&u}i0|UuT_Opyrehv#<%}i$E zd%CO_ZXurMZ=-3(0rVUqYib-u(?ku|lAa9j{+5FzOad0awY!wBhPJzxRfE}hY1WFL z2b3(jIg@T8A{sZ*Y&9;Co7p5)>Y;R-S=z?0j!%ZK*{@s+*`ln7Mf<&Ap76F>iN?LK zJ{Qey0g;?=%LJF4KFpSo!>iYfi8z%ct4;Kwi=UArC>_~ZmL3wnfTWpG*>up~nprX9 z7nW)nJaFZx%nhOYVi}PtY>Fr=jXLkcP%JgtOwdeN*eT4CpUB6qOB}E04%L=B86n)bbe7mCp;FCRxNAX*sUwh4 z0D`&_r;k(>P{iM^X+R(b8^PqKzezPzWYR5X?lCzh{GFH*(NPbPG*R81xCV z@f6sakU-+k9Y6x1OYYg95|He>!BYan(2@e~gBP*$)|)KQ>DT=^4N;;k&V5effGq`O z)fS@KQf7?*Y8FP(97G7-)SK!EzwE3zJ)EJO?1CWcrR_mGL9g|>;I zg|>;Ig|>;Ig|>;Ig|>;Ig|>;Ig?2HiHvh5yiaC%CQ9XiwNk;*hcwT?E%plYo4rF?v-arxv|)p!F6bPWtG&7dy2OY zImb=jW9-~L*tu~oJKWx2>o$9i!>KkK?LE9A*{F&i+*O^Q#V$=hibGqL>?oz=gs`O2 zE*GI|F^wJdNo;Mg$yw=11Q#OfAU3uSGNoPGoc9yumc0(&(ylH2jdUBoTu*EZwYEQk zfqSI_IZtkZZ9o0#Ne<7LrUAH}uU@dNzDx*O{rN>spInfCgnb^JSlwL;#LzjXITX^8 zt?hkwtxqnnl~YyIjBHt3pY6;sZBHFbKWNU>rsfyeae<0kj7EFBy@dg%uYPoxALhAe$T+hqPk^MJ=|v_E1(sGa8JY>%S%IDcnvZ--MRHC5~*eXvIW z^48p>c3x6rtIKvBGl%evKAvo-s64;aYm<9%sZ?y;w}shBTvmL%&e!z-TuJ@LIrp~c zs=m6a8>2o>)S-BmU4wak`Cxq$_it-njH6eAN2(?-4x8|{y5^LgfQ`j@XQ8>MklO6x zKXjE+?cn9TC&QI7c~|kN^N;Z+aeuO`g}$8tL!;tr#ra1*OUF|{jwN>ZO~8XNHUe?m z+Nn|M;tZUB>RNks!qUw>WE^PPWnkyc?)gwgtAuG1!ZZgKxtLwo*gyyP?QmFv9BIpW zu^cUHMuO>gh}yzgvk69Rfl_&+IQ|yrJ^BDN%$u&?Z_d>PyP5eJW_Q77CX8PGnfW6M zIxY|8Ta$-`bFzW8kW`(^plQ9uQLYrp7z^_Z1sts2=9&FHq=GJZQ-kyIGPj*J>|QEx zizRh^EZ8O^ls6wtu;v2;To7ibxCdQ`mlx)PKfmL?Kwl&W=3uxJY(l*Wt37e;`iZTT z!xLen(uwtOLM|_DRN{P)Kyk^Ru;g{N`Eqoyvj>{*l#ga(+`zxtT3XrLVJU@KKrF<; z8WDgKMpB_!u#*hy3(8ksx2>=i%dB~6?#be&DUYn6Lq6*;`-qPA(*5B%dC!FX8+4ju z0yduFJT!46ja8nfk*w)*MhrUzk?pu#_QAg&gQV7(O4tUS~D%99ycured108?8rH?Ik@Rq-il_}%Mdu2 z;p@doVK1jtM2RBhz6e2ghF!Fv%ADa5p5%33ku^h;(0;RJum!^Wjs z!z33h(d;fR0y6pU^zAqwFOZhn_XsqGR9v@?GZA+V@XMs%84;NzG4ncb+c6nPeBQYs zgyu3rTo*|zrdR@Uv8lxQ8=@)yDGa5lFGTWSA za~UKOn#1!y-(ncemgY4CPcjfYFc@!jv&qo)TG~O!wjBC`0b3=r^RAnhqK%4po!KFf z+e`vdsMzsGe86V8o^Xck{Q8~E=m3zg7~rTLFeQrn^6)c@=iI}H;D%whziMJp$Lf@P{5_t>||A8IN46p z3jTz1a^OpGlmyFiv`txc28&^-;f}h84Ii^Dt8Q&{0S5sEu{zY6X)*g_29R}IU2<7Xk$eGd_N_)%y}W0C%`w_+EK|bfs_t|fRGM$|LW{6hEFZ9s5 z6LOGI>0RvLmj)DLQaA^p1dXsWMnk7kFEuYwOO8Zw?=lDXf%8mulL6IgG(Av$BYr+_ ztAEzZ#v~RIU~C=WHQ^y49w8wfFDxQ@i3#)Kh7>y%feteT*DnKP^dyv`^w=stAZ4Ff ziyv>I&y82`V$XDgZB%R&?FtIuz;3WD0`xh<3)XnWHH1~{X5!bGgA*IoF!^Dx@xoje zOKq$&-ySMJ`27khp2ZiLS$$OalscHbv$(1;!+~N3H6OozXG{^F$wxXZl~0=GAqJO} zc|%8t9)pAZ374LuFe}suM(mwz%?1ZD@uU6W1{da1f$B?K%7!I}niztPRP?os_<>An zTnHHe8Dls0_wAHcSFNJSwxDbB2*W9t+o#k-6p&Z;xXB@+v{ok(2S@5!u& zohdJOd*@(dodXo7IcB2Xp^tM?@9K><$dikcPzv=#%oY;D8)EC^BA;{#i>^=-0R~0z z+p<#iIRa1kFex?J&Z8)1PW^TIY@C&DFKcI1>}ul1ae9mi4Mu1t`L=m&$#=lI%^3I6 zXzg9wT)N45wH)AffD$bmWn2x3&hGd;Yrn06Ikdr^89KzLD-`L zaEpNI2p%8Tw-#)tN>lYqoOygyvSnLrF7__>8|H#!R^ZO$)J#{#H5R<&u7dh%_TO8! zk86e1KJ`hwIK-(p6NAM zPAhHi9Zd6Ot6TPB;*`1}fZQ_6_{0~?VucKa1Y;7Hd_fp?PK2TGMLK=LjUB7kwO*_P zd$DS2<%I%U`>=pAc&JI)X|mopmb<1Qf8!@9_d&Je&dk~@gqez+!V zwB6~WxHm>Co&lV-)s>#_4lSs@VajDB>V01+v88H|(+Rk!-%T72S&=JQjFzLJ@b*9) z6FNDbtNz<&_94{Nxu`w#BAp}{dtDCf_4WnY5ZV9&@YvrC9fHQ}Jrv!|ZDGoo)1D0r z*Ik9#>Ck#~SyFULiF{d17;?42^o{i_Yk}Nhowqvhw};61Nr5kXS|uL|k=uW6xM58( z(}_mRIINxFEpX)iB}2Ox<<5i+;%&3Ase^_Vk_QV#6mQ`4W?>$(*2omThUOG*ZZP-^ zE#3eew@{`qWfLc6s7rRZ3n=^uU@y=-S|mAe7LzO;C;>+Op*z{6vLth*)8 zKj|4kIuVDR@aKGl>JrzZa8%Q6dop1osVw!ymX5w^Eztaad$B7&aK$%#_(aawD$T(q zS3xuja4g966A-}%eQOIrB7F?5dAJHJR?sZ29xSc040hWljho1S2_|N=i%A*3@;keo zz&Dgoj_T-+j}_y4{o00(qD=vQ`%)(iX`H&-WUeBXm??5`!J1t+IeIW_RzcTf94hMzVAIR|BjbEd+&RXe&>$& z58az(_ftj;pCbH*B-|!^oN%o3al*%}&imd)In7T2jQH&~X=y+AD&eOp;dfNRf0MB4 z8Regzzeo5Jyz9qCpSkbdFMrR=zT@6!kG}WFcdGrP%D~fpS(a_`CeOR>d*sJzfC*k_BGZ7i|~FcM5ngLa#jiJTk@Cs@-*@3xVG5J2y zK5gHR#_#W0I(9sVrRsRCr8|#_V{#2Zwu|^naZF;JpCG+w=|!D!d|vsQEPKS$zGtL& z?C6{MThCjG-#jY3e$yalsvVoY=i~Puds8y*AN~sGEAjh}5Eg9?{l0$e(Id|tu>xW{ zHorQ{rm44zCm$z1<$cc)Rvn}K)AL(|kAo+|^FV+1T)Y3+aZo+SN#&y}rLbr?*3F-z zm-uN^csFsQP2!u!?rYzFEK`v=p8UX&v{BOae3rED3-bz}m<1^$_F2+*c{AoIZ&P3JRXAoUiyYC^YP8wYw)P*R6X+k7DOR@YP{vj+?Dzj7R|40FL6-p z^5Mqj>cfkTPVdaAD@%J@4|5sd+QU-jt{hy$pMXVSV?CObAz)nr?0^ zXDe^HvUO$IOR|`UPd#$#k+DZ6#wJdV^MA;9g}f_QSSIIQgf-QW`2`ve^XF4%w;o|d z^erbA_c2?XSlV2>@yPPt;p+C<-ihYU3Re?zwdaYcjf3gK;o+U4 zbN49Y4jL#Q7G2(=qYQH&7i$&+_kF-$UYmQx>)HYhczO?-Q^A>Bp+B7&(+jJST@MP7dJj ztxkG2#A2ZE4O-#eX&sh$=RI&Fd6D7m7#;w!awmn~-g^ujKVcv};oj0GI+OF0-CFlV z*EUm}z>ul!f{gYZ;L(>=b#NbKJVgESnzCyvf&qk~3Msa3bce(CWi{}G`#0V(XaxGb zCF@;|@aifnfa=-~XsfdT?+hWoaL?pYD5mj}jB6(s# zRf>KaJB*#tmBjQ*-ZxRN*SEGQarlx6{Jo_!Tc@pK^wxZM|1`Qcj1T`Q4C3C7Z>_UM zyO)3#Pedn~{TClYIKXg63NDKb{s--kf4)?t9?Q=wx?|iBIqfZ-SYO)O*t|*0(JP@S z!|N|X-@Ss2bW!%@Ho)ZJ{)q$K8MnL1%A(^x69B1*cShFqEy&qBp1r_v1tDwQo#CZ; zmNeWu{@O2)+j2+*{7vPl(VLIbdI) zY2ow|UrknHqIbX5=Yba!6tE53L|Sab{3832T8M71G!}h8e&yYH2}FKT`WHJGUrHx} zC+JI9G~fx9+!-hTLc@@{DZB)uO!3$}Z}%L@SRCN#$so;h#8%|&&ruJvKdCRO976o}{aO z`62i-lGXWRjj-0CV*Y27bmf`u7v-aO8Dn0;eS;L|C>tq_bXwwPyQ1AjAZu_@q2_H zA|k@)^*Nc1WPi1iuJ7ev;m=4mOTW3LYbwkFWeQ z{29r~_lsC&6A|nGT#~N*k?p9&UngRO&d4_;=6`+8hDNeKB>ujnzpoK4P`@}+ ztY1DO{@`Ol`qvW{=TUi$N_e>vR(s@Q;?GF-?WCV3EO^KE%qHm{tfc>BC9Lw~qvFp< z_N%17jj-r5mUksd7cQ?R{nPi4C+UAe`VwK5+wFU$%df?sk?eKAc874J52ee`C8j?_ z`hF!{elIcoQPQth(&Yye(-%qq8>rT-zbE_|A|gEB=VFN%uU~#M{)}WFCja*n zj{HUCe>_S5$D}_9{8f+e`=hdK zzvlMzX&~{`V3F&GYi)D-_e^m+@VM-Igx^F&%>Q~h`S9|iw3 zz7hZA4;8%Refne~9$&P11!=KaiyVBmiJ z{)}YrCHAy+(F8K8*>G}92>7OV4 zpAzmR-`|%{6C6JB3-f0rI}R^=72!uheziybVg8I{Uq|{k5*A;I?RmYJw>=}-H;K2N z&|JZxsqY_3(hYy}X@=J?e=>hYvKhYr5yBL2CrZTIkhN%-G0eyT|0_ff*{C%>vxe)aRCq}MF$`tB!_@>Smz{Nnua z_Q=03hW|O=ZxNm*BEsuKNxJ$czdL_MvR@&88dkde@M8LJlKzu~-%La-@7I%b<(HqH zKO@;6lmFilmfv2?|2z1@#q`%9YkmOvE`F=o-d7X820c7#Vec=0j`EM^X!a246lFeq z_Yk)6NYYh5v^uKX%Kx8`|1#kwp_u>sl62+&fh0Uj{vWL5|4fpu{GUz2%jEx6!jzep zzni;>y1pX+KYvEDC&~ZE!5=Wfqm92?Ojr5x1N89G>}m2J5`L73*#3_s>B=wPKwdmY zv+pPWj}!hdp_m^(xKX7lUHRoF=+8*@Bjmpv{03utel|&0e)$G^{-fDHA^%?|+#@2E z|B)nJ`9GS3{{{I!R>}YQB>lHZM;{**%hLGkd-)Xd;yIeV0$G1A;W0w7zOf`-`Q>ZK zi|1%IM*h=;R|&=Z?@Q8^U%rRDc#dY@O#c6Z@S}v3U+MBc^k*cyLi#Teek&0XKA%t0 z4@rMxBH!Od_~YQO@J;mmKEk8-QQy-Z{`-V~nflsRp5yNu@Fyh5A>$ z_!<$hKi{3CtG%xbxmCmeNd8w5X3X>UeoK-rdO7z-e(Z66A%8~?AI*N5@4uID+P=>u z>8kIuN%(W*|5d`f#K-nE8P8ar^2-O(AGf#ceoYa69lF_Tkr&SqrPhoS{s`~`EeO3L zYZ3l5=^h@*770IyeJ7@W54y>5kRzt|N&g-4kB0J8|Ix4I#~!c0{ZJ9UO8)B zf1mKP2|oT!!jC8N`Mrey8ex^I_Wd2gSCVwae<&$m@ILho{Mh65e}eXV`2Oq%`QF0E zRo?x^&z?p;_%o7yh;)UI5~23}*My%Tj99nu&k+7j!j5lVe)d6<>^YYG8tDrA_s6XK z<4OASq$`}JM|)$Iy*fLB?x?V*zuLY>xeDdKCVLI(3VZr%y!<5nO{5>Mq(7RZzlC&# z)9;%}`W)#Br|Hv4x^#1e)AZRSeV=rN)AYxa^!JdiaGJiFr2l==6;9KyCFws#y25Gt zW|ICtk*;u>{&bT5uSi!oO@CjK{+pyLoTfjQq`yGA!fE;^ll0d@9}1`GKbxd~4e1J} z>A#SqpCeu2H2qP-E&YsSkC86>_j49{g^j<$1bJSOy`6OCNTZIg&hLIP!S5$XS6C!7 z!hfQd&nM|ONmm#W&(j~0a%#^=_AKcNNBY`3C+ryqNdE$?! zYrgGaPnZ1h$I~UBJnZROk4VE>ukgq7KRH^2NBDCu3I8zo8=ts7qP+tCjAS1fl5Wbm zW$^OjdYB}%#`CR7{Xa3}d+jgqN3AIy)vwV1dNsyrR&zIe7an)8!p463a^L0uAF{1{H4L83eW$eUjF`W_{)Pw6~3>#SuXExxD1afyso{YoPIZa z7aooyu20{^huh;rm7ZSr%jNuc!*}74($k+cK2-5_>W|Cgb2t3u!J`V_AN-SYd3VEi z;gRx#FBc!G`1acSalW$0<@eq2U3lEZ2SH#sJveOSiGPX{D2DAr|yQ! z<8v1t|6#$Sir>HS@5}AK8~*bJkLq}R`VY$OyBod>562OgPj~U*E}Nij{YoXQ{jNH1#~3DooB|PolKkoUTf8jFWhsG4r_nbGS^cAy=jrH>ImGW&7Q ze{c3W59i;%B{@>t+NW?BaD^W)rE|VqDg68k->UF)PC?55tf%Mw`7y$2fB%=#_eZmT zO*qA`-?#KQzR$mK4+k5?^L&nTp3hekj`C0VbwURpaRiQjM2~gCfBlVqXQlA7?deJ; z{rMOAgyVS!8lMACUybSSE9K|>qEh(z7d}=A{|gU86<+?Y5l;K_hn4*IbM{|6Km9o8 zyF5tv>3qDOf8i0raes{3S0fxBwg2r3f24r-8sXyGv3QBTkD>#D*z{k}T;Ho|fLrt1GOr9aI-9>L@LOW!~L!jE`3 zPyc77@JRMQ6OQ}mRNlWO9M|&|wgXA*YcKx|5}-Lek7r+NX9-$&to~D^7vul@3v+~{ zeNpAD5RUsF6%J=T=KcL1m7n1I4|~`m)xUqFaKbNtf^hUVQF*^W_*~w;S7*Ob`Th?G z$NkjG|EdSGES|5R@YfK&%=s-JrW(=Ln+c=-ZIX!-zhx7DrEQOC|9m0=N*VE9D z^p_=1SM}8Ys_aRH&smW0z1dB|#rQptJwv#lulusUOSq5^_hla-Jo{1qUhVzIgsH|J z!RzN04v*;b|Mc*vq7?q!Qu^~Ryt*P!-dG7wR>D_2YzV0Owg{*6{9eNUUt?Dj0ghv{@d>M{DezH1VRc(91tKO zkWi4g!7V{32as~$1YC$foXCX}h(zMTW%*vcs_N<KGUK^>Ohf^}j() z{C`3`Xa83y>*EEC&GY57--PEie@}?7^Y{+a_lWowk2Srw#Lv{Y*#B2NPw2|t-oe=X zy%+8OSDLr+<a2n4e@17kVqRmlx z^-%74r*a?dx6V4~PaXFZH?=9r1YN>vb@6c+4dGp(d*6(@Pj{w^@c!K;dQin;%>6-S zlEx3JDB|R}Z;9dqhPn^zX}ZXv3Z?^_=(ezE!L^#_=&7kdVJc^Sc0bd^Rn~U33QVs& zXm_4b53gi0c6MAQ*##O-^S*$e2Y#M2?qt4P<=A{5vgxc+wE4{Y>4SqfFAL@)rW+r< zdP7r=UA-JVuCmTF_S5q2q?nuLKW@EJ%4ibaw^HVwwlW7SqsDScCZjsFxRz(yBsH*6 z1)gPO=W&{@V9gFP;MaE`V0i~WI``*cj6I_G^12_%BvHV+yi8(fY|bcVFphH>!4Sz0 z{Uw@(tIw=87a}Ccj|}Q$e!jR5-BMRMQhc5+rb5EOr|J}LtVhn9!I61odPc1r1)7cF zMEEQ$SW+9gFuxS^K3haFI%LzdGoH*R?r^b;=R!A&k|F#)K&%j}d~w+-6s}F1%^nIi z=4t_*WPIHX$J8o$9%nwZk)?{M_>yc?o5`9*WP>-)Za7`c6s-lphJ*PcpCnh7q5N_} zXBXp`$N36^hlmnLBRk_>V$|Lpg3ogJ?-EfY7%z(b{Z%-HpwO90j?tSN-1yUQHKmq> z?i$r?O~+T&JlUOGUd)t2S(hr(lFgJh&^8gDtE228GFs(VGQ0v2CG?>@I339@COb6e z!QGt`Yhc|6C(1a`rV=)S=zZyjxtSq3U;!DMMlv%hd!(@+>Er>UH&a-Eu(V2jYErK4 zD<@gPGgZD(nI%3)2r|y+Ql+i;0gM%m|JD%2GEk-;tP=EpENE2n(p;tSa(X4+>(mf8ip zMUr3mY22j=L7fDZY)g`ysSbl^%q>tCEGKMTrZJvG`lk>8j^ObYn&mjc8IkM|b`Z-8 zD94Nhy?mimgi+-~b`3bqVi{24ES7MgK^hfmT^e1ntJ!5p)d=p`ZGn_nKwa@l@at`vv~|zRWIs=WraMLMcA1c6LHJL`m6!pfY{>qCa zs{_*vqm_@trVa#2#Tfy;0j@&_M5@4&Ds+h`7>DlO0fQRuS_TnUh60V%bU;fDb2l?E zcQ*rbw=*zzKh1>8Wx+%Vs>qwV=Q1f%_gD>bPt~BNqgP20c4oRoQt(6hts4;=8yTYn zo56$hB;Hcr8qgSJEo=$qfoL#`XE0RsoSaUAQ2Nhc94@bF3yOtEpU-6Zih2u6nC&Eo z9j6F+bY2OdEDa!A3FvAA{psg16;*m>|HdnTMuEx{6=S<8mn+4D^|T_8t(kN~>YC}b zUb+U4OE$}oJ==+_YgU<1vVMx`wtF7J9rqBYA+G#YIXE5l2Pe|&jYj>G1L?^V!0#bQ zP%M`6L5Ac(?bMOa+0p4LlVXv??1E-F=gEddS7xBXOmdXCGMl^_1Bu*ZnV!o`CoMOf zNt@>pKqN{y6j8OX7B}mDRQHiF6@lJqUv_)<`kfxmAnJyLW7$)-;htYNWX}9cbGW9T zr5IAiQ`g8+ywE=d%bmeVcX#-r^o|B2*+1Sr=!t=IT3wzF@5!Uy$-(GQbazL)a{p-8 zJ2Vi9@UI~!UPpSP-Qh^Za^0*stc6=UTN_Dz+sLsZAQd;OVyv$hqj%tq?(TW=XwXq2 zUEATl)@V0cn~fcEn~Gis`<|8=a(;BFeGAG$*}c{d7}_0mj-@AtyT|gxlY4jf_j~XY z5b+fw1%Q?0 z%|TXhPM(rf&^jwJNP1&ybEnnZ-r?ryRG9uTTuD6UyQ%TQW(7?6^Wa zOv57^Cz_0>u&t1=%Nn^BJ*;z7mTGsDRJ+2C6{FY-T5znOs_%x04J?-;gn>l1TP^1b z2llXu)g$xDexWp`&Q@BjuyoCnElVV0Rh}h2?j<7|%<;5&X!Hzf>_7D2Rl3HB0BAqbY2;49voDK)i^*SSp*>{HsFu0p_v^&B+!=Be0 z-s@3x0($^>RBntG%U#^3R8p)6=0t_hN%{cH)Z6V=GYpzQQ~^dsceYTgdFX-U)&Y*r ziqb=7!%$sNu=tb%+a;9~DfEIW)^j9G8CdBc!MS)Ij1CBryf;ChDD)C$`hTkXvz-yPA{NI0sw9c;$|O7?OnspIMo z2CvO&T~uP8Nv&Btp3%*SRfhXvM#iS-!V#OBt<9|@OcammLL9($)btxkyK(JY-k?-; zuneV8zHBW7a%6w#D4wwA*49oKwi~o(Rl@LOCK$3KnklR*rzbgubgfNsz0uxjHltw6 z-tyP_@Z-?;DP$f})+13rXnxpP$l z%Upf`A(i)#Rk4Mtr7HVltilZ_n=eX!tcRe9uaH+uFtQys>q!fVwkjzT=(NvQ_HrY* zrl3^MG%6-es$ny7alWlvtv>g@~#$Y&LOF6z#Md?Jbz2WB+wyi+pKr_;N0ybZ9;5ANNPS zt`22xaC1at<+6^%YSuLtrc$HhK&C8RV^>O@u-u!Cn>S?zSR!51!VMx_nmP7oF`Zm# zWDk{>1x8F-@3HZ@Y{0e#C6jOiDpN+v5w+}UhKPgrJmvQ@^GRK))pm!+HC6bE8r@EV zoXUZ!Mn#FJjpwUcHl}+jnW&XXJsIE{a<^LsDl}X0t0% z!Z+nW`VySNV<2FZ5x3+P|>Kcr0%vJH`*Fk_p^vy3SV@5WqqN;hU0`$*N7 z@&D&9dc1)i_n>}f>V+pA%=3gaR$u(%{VDtaZ}|3Hs;#56XW0B3dhZ;|_%48iqxV0n;+b=&WxVB0c&`JG zXrRA*q33~lzUSc4^K^uV2Po{z@cRQ7@5eXe zy$L+SuX;YIA{WE&FC9F!^$mEx(Rh#GT|Lj{bB{?H(#!Di2YjZz36GxB+ytJP1IT`U zAD;=2e$;+9ockY*qt2!0ZUQ`CLu>TQ?EM%vQhS*R?ALkL%ocOhTENBY{QOaoec3E3 z=ANqHz4iX1qV?Q$yha7@-)QLm0vUyV8NEGQ!8@$q5`ROlQS&l1omTKZ_k~;HQ!g8= zg1(nDUR_UZ;Ey)m{H)o9@n|%z;QjgS+w=&teGv}*pvN!S^3qKF19Kec%7xZSkS=>?`eIew1!$GrYe2-fi(DY@b>Tzj2H0MbV+@Bn?Re2^U8})P#UG7p3K*5gq9e zV1kMQK?g~25O4$$B*8c`8iU|C%BYj(qFhwspf(UkJ0#GX1k&eSI{}^fJkNRl|2zNx zobx;tSbMK`tyQb4-d($P?drWOXS`Do1a|#TWT}kMP77nhab9bVU`%GpaAsm*@bzZB zG(YP)QaSyQPEiQJ-kD7#U?SfWaFG0)|7G}JMkpj6fh01O=qf)P{^9VEko~$`_p_}i zzZJod2KY&SS-z`I6V4{M*wt4U+E0I-tzp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?( z3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk z&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u z;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp z0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n z8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+R zz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zpfg22z>|&;!7RFXfjJ1pZRc-`A zx$Y+$>CY>S)x|QV^knQ6==&hQ{ClwvW4A+kMKG2W`AZMi|93GE`fvV4xDMA$QEes#`lt8ZEGoM$Yxi^`0w zRh*&V3nAHAQk@FztB|!k)hPueDJvjKRuT~ zt$|dcU2Q(Wx>aRE#k`8bxI(n(fM91HW)E{!sQnGbxr*yxi#T(NYPKDY;^TNm1 zs2!QZRRgQ6$!hJFWxc?pt+14$tf7w8r>;glXlDtyvQgd@oq4-;p9tNF5%4ag4&kz*!U%m3&|JBk{-oi+T%mE=y^ ze|w(KV>kOeMz=7`Sm;F-X1Zm9xqNxeI!E3Kt)G_Vuo~U5)rh&(SZH(`_uE{jJYLHw z5A~w%ocdgTfa%YuZ?4V1@VAI!_bsZJE;U66tIO9pditiQ5w^%S{bece_LP0i-es3- zo>$))9_!0=g!=?jD7Yd-xOdh{^_^Lv;G~egS$VU3~;-{)L8`KO$WlV7OJyFEwWBnxRLUTNyC>}isvjO^_-n`>$v zsr4hA>CR8jGcgprc{-5+qJqs@za&fc7EZf9wd&}Iln8veZOGp=b7z!#q*t~Gj^|fuXnIhA6TZ($w{qu zIww{aFEzX40zx!vju$hX-Edbu8FJ=~tj}*{S+6vODagu3)<3@DJMUM1VO=P=^_uYF z&}?(z4}O}*qO7QG?C^=QQ)(BA_o-ptZqB!xS+vnNv|4DsSsbp$+NR0v$HE%(1C7?B zYT))0I(D4B7iDHv!89RjVbY>Irg$nmM?2g1`=@c|d1s0%x2Ushd)4_{`m{aOW?dr% zqNUA_Hed0YO8M&XhMcj^)cQM}&sFCKqQb-5l`COQ;nLkpf2)QYs3&rBqBzPK-(Ui3 ziJ?1lZqxcwypmb1D@|(*foRt5i!uxC%IqCYI^9p+_x&a(^=t%sc1yMsS-#c!rgJ5i zlsUpqhPhaioh7?z=Jkw?uV*G{9L+CV(Eln(${@!6?iO<+iv)8b?Au|JoKl{lB(gdb z>|YlO-dZ;jHqj!wrhA#i_^@Yefezyu*ys%fTk2W8hH>v)st<*pe#}!Vq{sUH{+O5^ z?PJzN=bDmF9uqT+zU7Ya6J0!ZGXwtz;* z7LV41r+rd?bEYj*R)yPN#=T-NT=W_0^tA$*wRhCF-1nSd5dwXrO?Fp!C6k&9v!qK! zS%*}w*;uHr6D(QbEYOFEZ7d+?nKB)!mHqt0!TgNpjp5C3fi)Lqe_SJ9D#~7=vN$Ps z4DRK7RM`~@97ozUXs@A8s7$UFDuq!(MKkiWd0PEwYvVHe&9!C!r5)eQGd`SDnCP5|c5M5Vb{H`4 zymBoR+zEO4+N~~{ql|N69)G`uv5$56$12neLxq}Vf5wr}P@xWDrfPAZ=$mXkx-hD- zLQOUJJQZrXNw~EPN5qXPP;*@t-h`2Ex8Zk!|B;+-K3OPV=-X7Zd9o}c^` z>QMXqYGGiRI+V#ili4_D-NKM5;9tAYI9Eu!;=AN8c5j z_W{=iQJ?}RLUNlRnKdSoF!a9Gzatbw6lt_VpNEM!1 zKeeA(^e*GWn@Z#~(I;6pc|2ovX;*#5lGuP89bX@2(OX*mbkFE(r4k`M%qQhWmM7zm zKO17!NUy%`YdoJ9)ed(JAODs66+A(Wb8p>W0ah*h_5E#m_ZG%JZd}MLuQ=AIGFzi6 zhB9@qX{c}7yvOzlJ6|jk%_obJmI?!PzA|;7X}Y@%{7hzLYAVeexC(t2os3CS8AwBbzC2|0GK?7^gLrg4w2^UEJ%bW7@SwDO1uM zAuXyN;|@6nnhyW!*lYBwPcc*0u-qx*X`U0ZE_e<0))gK*<|E9Csp4rNFBFW!%5XfM zyR@#c=X;&HriQo*b%6b8XFS%sJ)HR$8jO(**Jq%UI_VheYjV>1guQpgKO%3v%GM&@ zG|uV3dbkYQP>iEn3PQmRZQb^>_d5Lal)1ejzjZ}%`ik^tHicb1KF~FN=}X=PElixg z@M|v{JgVW4%Jx#+u!dT-(3U7m$7|K8wxqBD$FA3WN}Kz}VLqGO#xm-Bx~2$;>Yarw zRBNZcT+^?YIj!4)C)lh0S5%WX{h7+JtH<8=(^@&}s?hfpwb1^BzqjXJ&r6=KJ&IMc z*go@riE%>Dfa~jjTW#WmUG4|nRSyj+kp^w77l!Mrw>VOc-aYS#Zfd=RIrUJBoFxs? zolFid!x$d7f7^c1>MFF=Nr5QI*k_7k%9vLF7Kd<@rC;<()@DCtVa*|%9#3YLajv1& zPy7dJg@B}!hD146?$tF6nJ5IJ#6|Apk}%A6mi@}!KwU(&gcbWR_dwSs$7SC>_uUT( znPraVqxpf*FlH5ZetKTCTAadK%wwS%xAbDdJYnPh{qX^PbX2`)m96msFL|iy`2Rj&VlSdrb!L z{^@(6kl{_q88)7|EzW6f=^(Rwa9*^~GbFJj6!hcyO3!4qR$86Cy0T__&C2p^4qDOW zL~U!5qpGrLoi;ls%-Q<{GwGa?Q+95^$}8S^d(s<@bYE=p`kGs-D`1Ip9!y;87~r#J zSJez%ZE^0^R$`~xY^7@5-B_`0cC?>-#Swkd=HBLDO_FW|)(Sru&lytT237$=RAsj;14{EX=GQCj_=%Ggv}q9kf4Qt2^hh#{l7M)XCOa8 zP{(R%wF6A7uUS=I0VWPMImJq2WnyK`OAgt&yQb%f1CJdDkN0`%D$%Qbj`kz}EH}9i zwsgmvsl{*B zSVH%t(L?7kI8TFC)Uq5}UzgdL=pNQ+M$B>DEywYs4#?s~f3Li_k`ub2$Kz09xfJKQ z;12~ywwtQ6=EPMOxlJWtU_@rgxtcP^#UrtZou*4htgy2)nprBIb!}XIa&^TOW_RGtz@C;`Z?~|F z?x)Hfu?;V}BgYBrg}|3ry{7P7VH2&b=?PR`SMH$ovgBjtR=?NO?iX?cej0mK8t<~R z#{}jc?2L34xpx&xA2Rd#(r?P2!pMqnz6K4?-f9=M&vHZ!3_79{j^S$IExR54e=C$) zEtrCS6Grrt9V%A)o$Kk-x*sqyns9$mJ-XU8Dl@H71)DJW65(q7yh?V-@1^MU-;dqcq~S39BcGGAa_5``YBdr$EW9&J9N*lQ4^5Atz(1B`0VVK3B!!5 z{v^j7UpF!H+0Ak{L`we=`CUgQ#bsu$YLs=y<$y;rrL({n-g{3N(w8(?ltIVO>g>%w zdcD*#Q%_yLt(ser?3f_06pgO;`vCwOo z<*F=4Sy9=cs|W?3>-a{AK7Oz3-tniN-KRPWy)->T_hznDc_IZbS^J+R*!PVZ#T z6{gD#aVO+Jp=3|5#2UV{1u}Zy$AydZe)@ zh0L(@fRFV<^uko<(20Mn`I9=!^C#8KC<0O-WJaX7_%>qxNW(m_qCIo96wpbuDGZwQn&2V;5XQN>HZ{KodR22V3|0&wci`es+g(2 zYt$$kt_LL6M(nRqyBX*@NjvqHFpUQxFsl8iKOXfiYrW+SU7pSy`wW$g4VbXP@>&>O zF9Yf}=_>m984I`5JLfYvKLqK4_pW%HUugT&r6@~n+saGWH*>@-JssYwVW4x`xKMDf zy0$vXDzz(Fo63`xo-S8*95pfvYOv^#IT4u?kXd`DwMuQurT!O`uw;Lpiw(M~p+*hc z`&x~0MF0FzOwT=$LOy5w01gn zHR*--b9`Rm#5*}}o?w=FS>Gi7b84RFDbHcgM!)2==CUTeSmBU-QI@$`+X}wGQzY?# zgr`WWf1i5q+WVdf4=fA+xlM1P7uVZGEz&j2TxxP3(e*@|CgIt+Rsy)e5S(h{7JvV^C~$=??vE05fTcXs-wB& z_j{{d%+$-B?%p_d=jx`_t7|H2Qdhr-XUw4{yLi|*IdMZx6;?XRky1xSeYi0^@#&hT z(v6P(C+Du7bNvYuBkd3ZgWH6@=kbh9MUIYOYAD@(4o{kmV_60ZRF!R3yWvehm(DIa z%FdjN3q-OcW|#hme^%C8+A1X*D{GGWH>*)B6ujeVJVyC5809f-n=wB;<=W)g)#V$j z`BuUwwY}_LG5(CIUv4cyxdM7~uzEJA18jJDNh@&f)R%YZsa^I|*hwdQDrVb{Fyc{* zO$ro>g=sOq>+|$UZKcV~)TWN0>zcPqb6%V6x2JXU-S1-QKQ##ERHytJrw#IJsm=~O zFV6T`T0LT7Y~kteoDjB7R;__hGGqUO^hspwWY_sP^j*eI+fUG?B*wya#hsTJdUIaP zw3d8yo(bCiuP54HjHhaZO|W!pju2$b2pg^{;4-$bxa1`V3w-P?E;)pq`e{Mf45nPGW*C|d3A#-dTG_Xs(l4CHkbu=c@Y_5EjgoZ+-nWkzgpm~SZ?z1uHpfBOou5C?`;vZ`6Yg?__(Vz1jEOl2ynfq4fG$*al z^r^R={Jmr3QD%v1tW?DV!m#4(scmH~6{>XL-R4mA^LVS1yhm#`<@|KwuI#&VVotn- z-KMOZ)kiB`8y)?QWR*mwOZ8I8T2nTtYxx&W8%v#O)x_*4y9LzJ{v9%6oLoaj z>=dRgYu&&51-#Q9Y_W@Ir|C7!-(HMoTJO@C{$_NYlW?9K#!Ll}0LJ~Bc;{!OOrRLz zg{9x_d(u6ZoG@r zn*_a=??;}|tslRhi@S~Z9DS{G=B2s#gl_bucVA!e{R_ILW1TJ9@QZAYfOsPt?JazP z*~?%U>kvnUkYktsErZE46o@dW0LRo@$`hSmMAa1+jO)~VuKSq z(brew%Pu|nI(zT&Z%4S2tIcQ~-3`_`G{P3XE@5^boVRi8{BJj0Vc<}AdW)N`*X-Aa zIn#1k;LVP$?z5|hWoKq@E&OMBCEoDPmI@7{2Pd4c&dJpm5f|8 zu9~$u)!gQV?fAE$;Fc>*{u57h1Yf#3?#A0r=T3)CTb;^tlu8;K^eoykw%@mU%srNG z0L%&+iiTeiT&KeO04d?lZ(@%PSVb9L@s^{ zb&IWyGvl)UUPu;Jf6X6C`=KEe478uac%$E9C@=dLYm`}=;;HQjCbY-p##vY&IcVQipyY?K_RM zvq0v1;vl`R-@FH_yDS#FnFSKxi@@)e$1oE_)l2=vek{JE2Bj5C(w*VhZnHx!HwQI?mySWmS7>8~ED>A!9P$q{178j7VSHW2364 zl*nd=tHP|atVc>FH7e$IKYHPde~e{}YLKl7tMR*1`R#de-m#YtEW~vveo=_MP!^Zq zTlm(&?V|Ye-;$Vb^B9HDuzDahc_5&cy72 zxI@og%`ESQ-{ER6vHTHU1(`xYU1;W8%$fk^KNM6krI}!$4)cW z3{qmf4)-UG*-$Y3Z7HJ(E&ZWdhj_~JZ3nXSkIn4}9=hsscQ2%0EcW7e$&TRN?S=`1 zA8~2FT(DHKOm1h^^d(lmX#L2~`u4$?r+w&2kjao4kn3aX`naNT`CM&&t4BQOIym8w zT5j50n0HZ{a$x-Xx!dvkbVo2nt#_SKJ%{S^&ZzUx9y-qs;@#14=)7n)7QK^q=)CgJ zj$m&*MOUbC!^3ghigmAdc;tKWZvR^rKp| zXem<{m_EeuQA9q9Cu6-9v5X=LFNe4L@>}~kwy7P~boaJP-YI1*5#`IqdGm%kV~s4( z(*ESQWqHeTNpEbw+4k{hkjpdqBZ8{MNKW?OU)x z?TdN7-A89yLBnQy81?lvJ+H%aSiW*hK;&?4$W3j!gr&{a5o)2xs=$|CGwfi3O*ocLvRzzF=VKet-m zIUV1kEEj1$(X|PI$!b)J`2rIhI18DD=}kW2#e%#^u9ye#n_aBCIET$+c-_Z`VzEM^%=v&S4LH zTAFuJoJ`k&S+IkTJ&ew)GT3Ew=b^Si<6uQ?vqKqZ!$)4LJ1d6;-tZ#VqO*mmF4nKO zP_Pcjvo79RIJ@YB^I><;w-NLOh}C7BV`;@+WKr^*+(vo^(esSHGhjD8B+&OKEOsel zDHFTXH!J2?yl=v`7|$$3naHmn!Wf;kSR1}epl=hr%>Fj5o4!Fle0yL=d=)U2WlV1$ zQMyPs61KOoj-oy6130sdJ?zYmvV(>S>|j&m)XDh;w6{%PX=wd*XJ2;NjfJ=e#cgh3 z=T|eoD&9Qn)J)7H4r9^uqD@7)m!B8!nYnr9S4F*MZn}T^{n)S1Ov5(>!ibJwL;F^@ zP?_qSGP`27SeXN+R19SjhL*IxCK_k`(|xK?Ff&s}u&&+eo-r;fN3K71UK}>PaJuX6@mYn~TX@8} zgr0?h^{xpk)gHss=icHTH1`m`4Wciaa9;G+7IF3|yU?bz6y!G9pK|=>WPYxAX|YAT zINDOv-h5HIwAdhBj$ zV`LMGrkXn~V~TFe?TRbPzF5!|H)iI@E~_x}rd(GRjpai{BV1Bp`ncf}@QZdEey=d6 zj$?tew)B!vdLJL{!Vdxd<_fb6cAYBSR5}RXH4SoEs|Ssv_1_>@VqyCDK+Uz_@eoV3 z2d0!>UoUok4beZp|HL!u7B6KJ8ajg0L$|s!-A9bYX_ro(P?>#JrhwH-W?@ILXL~Q~ zm9sP!c(U}(OKl6hfhDEbL-OEv>f(>^2Kbf#4pkn7RpHGw-_hD)JB>@s{WQiy`rEOY z9nD6*Av5pS(QHdlViR);@@YLr>$_B(>Ae>vw0D9kU|O%uhcqJBIGig~L;Od&@ME|` zC*cl_`{n)l@`Sngjgc-s5?m1xX@2QIFHhMf&)rQR2D?=IeY z);%R>X+wHRpY%sh*e`~Lp0t0gTX;OCB&mA+70JZX=AXid*W=kONtd3Pk}O(_cDef% z78j;J{((BuYhBnhr?@zM?%878;oi<~r4T=+%=J8eTbb@Qw?#EuE(qfE!n@t{y;Q(r zbx)gXol}M#2P=LDeY(UlhrVr#^R!v4b2dGkS7Mzr-4h9GCCdt!q|-G=AI^KsI>)&1 zFg%+UM?Pkma~d82o+%5hRA!-d&i#31YB%qk$I(l64d2eq%p=_ZeQgM{Px%Mu_2nzn zLEaD4s4Xkh!QK_>5Qxp|HCN&8_)#^PU&8r<`dfUnwC_^evi753cPcYs9>~F*Hgpoc zQs~G!s4@lTDUojMcVz8rX7?>?ePlOz(D!Gta*28dJW4Qxg>lnSp@=40o@rD^nzW%MeT$pa?L z@O>BHcLR)?zSyla6}5zk+i+$U+NaNNy~kl(C0J+|T>HfVzZs$i{MKOfUJEX7pZERt zOKr0-%I$N%$80oH2HM~tyzKJKJy=J2Fh3PP{yqIJy=9fayv8s_zg5#bOXFCZ=do8w zzgo@<;cq_ebkU!qYMseSMG zrZ{eeQ+T&@;W67NP zi%pNtS?o4Vp8e45MMaBDV`e>4^ic8aStjTF*(Gyk&Yx|Xvf%#3j}|SQZ7L`#o>%n1 zY||sN7cQE!;2~3Ijxh^oEt&Js0yf1{v~Zqt$wQ{8?l})VU@DluWRYp|n42byFl9UM zVD_v9vt~Qz7cFv|hS*AMU4KJHrj2wJW!#jRmO0Gz0JCQoEiU>wXk=#;f`-B=Ffm*X zWH9y?g!YAw;d}+c|2PAj0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hC zGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mE zI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwt zfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n8Q=_X z1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@N zXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5S za0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$@6|BiwD*0eE( zT4u^`eIeVBSEH`5ZBa``y`r~m=*e_l( z#03n|`g&#(_j<+(mC4mYr7%jU_`x4940vEJldsSdY| ztV7$-E?aH4@nv(nO|TZ5tm&QxNZH(^Y-wKUOktE%Y;eZzx7FFIg^|a!K3_S`OqbEK z)=qBFw_vU8OmJHEXQ3t3rs^x_OlRks^Cs%!icPNfTgD2Bo+J-5KkG2~8qClJW%!CI z)+Sh{g-d}xlGrA-^vrXpW?NFDX^yaV%Uo8T=mp2ju0$N$GFKQX+P2JWoGaQIXPV{- zBTdC8{KCeuy@fxp)Fxkizf`BRH&Dk0U1<<*@4PbVan`SexTot!{C~q54Yl1}DNlSG z7JmGw>b1|3#p5YYu)ZmaaRuX9BkK#REfVa+J5BqeszX5~WO5qnWapKxJa$W5ZP^^d zIHAJe5{iu;y~XHZmhQPjRna93)2F3)ulO2ZYtVQS!IQYxQ1|nAxOja$bhYVLg_#yy z7&FOGyWqm4N%@yUi*+u?g#$KwYrvl3o#8#1?~N^Fxt5m^-K(1 zj+UJp_vc@@YnaXXSY#+TC={McJr8x5or#uE@H9$?f`_kl_SodCI~OR`?jy8Ut<^cZ zIeWmLrnUFp>R4A!>nAze)N=));NBZ$)H;JDWR4og0>jj?mqQB^0zx!Kz@o(ZIA>U% zF88Q+ByxP%RpVCFct&e4@nSzp z0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7oB_@NXMi)n z8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+Rz!~5Sa0WO7 zoB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG1DpZQ0B3+R zz!~5Sa0WO7oB_@NXMi)n8Q=_X1~>zp0nPwtfHS}u;0$mEI0Kvk&H!hCGr$?(3~&ZG z1DpZQ0B3+Rz!~5Sa0WO7oB__jf1iQSul)V5vQm-%Rm}e_{?N5wA>jW@EFcf^Kpn38T-iaa}z~b*Ca3|>UH1XByE2KE`$unNvN6zll&%3 zooR4B05A}~eh}pofC4Ca1Wo`fhw=m@EOH-XdZZDwBP>jKBXKKEatb_eLwSpgx^Gda zJK_=n2B0$KI~e`}@OOyP41g5uDo$Z(C`h4#c7%lqHO5Og$v4AeL6`}`^uzZumZHVc zF@oaWjFJmry#@Xe5IGy*ZYb2ft`hwbE3(cbO1#xs!h?W^u9sK^WrbEkIdju{6_@SI7AfihVC`sff-2tpndJ!-J%z`qLK!1Q`P#%To zm((zJFBCyL(xni-?Iy2+_0O=@LU7?4US(`P)C{djzlA1$1=D9x4nxAfK%dDkYDW`A zNs=U=g}DXhpCJ0%su_C(O6Rc$&hovIoC|BB#8^B8e^M>dZbVe)5cv_Bd=RElaNi6G ze-A0iFKWj$6cKc&=`hTN@Xvtg&B(b`tBH;##K@zmOr*$#CrT&~m%#QlY((ijKij&gz;xwV_Zf*$@kd9YN*egChPvQ76p6kG zCZT|JA5+U%8^TZzBD+73i1P5Kb{1^!DX`QVumPH)N5pN2zLiQy7tI1IfLR;VRZY;M zJ77X)DH1mTG240hJqVZMV44CYpFkgg5-5uyN;<%1C@&JY8Q||w>Iq~4d;~TRLX>=f z$S~9kQSJuFgOW|)0f3cImO;8bfoiF-Ou83$S2?tJtv~B1;ar#+5%o2MNrTo2tO@~l zX#pcpiF^x8K{#6=N)AAZ4#N#%c(5y&QiJ7OvqJ9f?#Tx47e3xl6It; z5N)9B_rWt6K?M}3r?^JMbsmw8b-zc^V%+fGuO*Z82%?cu0Jl(e6j`FzgG>>Vm+k%*vw1isg+O$YIYOR~A?77~$S_JK*K&^E)G)iD} z)LOT+vvq%m|6?tgH0_eWvf)d`$Puc-^$5HlrhmfwHAGni5C$uQC|-aOP=-QcpKiqk zq^!&aiLMrv7tj`YBh1s_p8|;?kMasEAX@tXnaIEv{0Nl%e&K!8CDkd^>$2kfrF*ATCi!n6Rf z4?^N!gO5gTw;Cwa7$!Ami0myOx_^YK5LF=#64@$*FNZ`&0|=Ak6r6SezY0+X0yIGR z1d@0Yz=udcedu{J0Fox+!TT9(2eqWHMZ((`rpt)`5hB|FM#7pwo?8LRp)4oh1b7=t z4MdqtWuSaZ;9h|0D8_a}lz9M0q5K14`0W5ut4(5Vs;@($hRP4YdI|1kh+GUXup6E; zkQj{JPct;e+BA+0gcYF*fUbXYASpd#;4$31u=dOz>+C$EyXlS37UTod^>LV z(U?lCX6(o$YDc<9Fy+R7L-}gqI*HgXAo4DNAEEpJ=`1xJ!2+YBR!R{fd*VWArKD)M zAX=$JC_NyoM;(Zqua%-BB@!Y8shCO~hiedm(y7#800$I1B%uVMG?b%+N#esePNszc zi!6YdmXRw_8grcVI~E3?v~CtoQz#_C-4$`eJ4q~|^4DV)BaIZjo3XVBoKKCZDx<+- zf~g2K-vLP(1P~^@tuWIcd)^9N8H>Yicy>XQsQ?F|93W5xa1zRKNbK+5VC;3|71$2S zJVHnuK)L?_vw%SpLJW%~?%zU?$PQ4@O+w-%1R05Ujkz9(jHe+Mc?3~(b3P0|&FGJ6 zL_8W#eSHLd4Zu%qfF$Z3IyT~UEZ?DgNtvsn=n^_%8i8~JA@US}bx@W;ltO@bJmE!1 z&j$gNr8s;AbQ+@k9^f*R0D%nvqhgT>(qjSo+ynEepdEWtT^>QXwHqo}1J_E#EQ82i zfEp-!Ac>m*`lApH0HqS(2&@ed7#EgJoLPC0s6JaRb3oXKA)H>RML@<+IsAAD5Gajaizo-3Ru>f(w5HurN3L8%#s`=oFY}VLtTV zT-`sqOJu1?)7gFL4Zx8%;Cw3h4opHpHwUb@05j=T7{&pCYt*$Cw%!u~$3daXK1w_Y9M%fx2lT zJA#-7iZcucszRK=0u)nkdkitg99Uz>&~q|0q)WhQi19gSA09taeWz91 zfNE)V*?H9B4qHB^xNqROikLQvOMHeJi#S|urmO*o!^>$5y`VCw>2Z;LqUF#A4d#aE z7MSRz=vs=zK7-4GIH9TlE;+oH#D<_?IwU#)K$sNQ2PZvdEyV=o4mc)2;?e+2u%@I_ z6ox00)HMC!W^sZ3&pK*Irqs>xLAAein)Tp<;_72tU&&p}eg0*LF}%2b^H2E+RhCVjbFVjGZR zs+OXHQv3_1OK>(rENuXIgVo9|j(@$Y>iD;Av|;QqiJiOAhR-R%RG5;IFybI`5x_Vo z4oJ#F0Mv%Zab60;VhEG=9F{8JI@oRJdd#t^91BZaz67G@fG z0ylIUIxVe2=0vpd0L(&_j&7a`n51Mth_VGB1xgPRVz9T?Av$UddZg@!kWyoCEMjsX zEOrb^^+gDlQPlHAlF~#$6Jahyz;sC8y8%wXOS7&r1K?>`S3}~nQIf_Jvo@orleG#} z%5zK#mpfqEil~<$F=SODQT7v{0}%YhQ`@wT)B6i4-JXI%3@~X4o+KxLQUQdj;plF^ zdY&>fGIfzQH}6nR|WTqyay%=sxd<3zW~gHG98lgA%M7Ue!s0a z>r=NK$ApDe_Pj&7o92Tzfj1+plFEGs@MkEs1l|W|fbtn6hKi(|h9yi=pTfG?at=C6 zrfgX1FyoU#q?YP?1b<7VDHZF*SO)=0l?2ce5<~GlDOFD`2fC1I`5f)DJ>H0u9tDuq&AuPJ#o=8SUc z=N(A72|z`at<;7$0s3N%Y=X$|1B`=`P2g34g;3m(7%H6d87y7=X&HA=Mw1w;WvoZo zJ5-J`HbLa&oO!rP^u}SBA*3V1^;r$jlYC41iep0oCA^$E|A$(xUfdRIMSxfMwn_)b`M1P7r=2SMk zq%+tWjl$Bov-|^?BIO@oYDf4bh|I*9xLz;{s2 z5SR`SYr(w>ktYBQgJOfkPy(eCmI*+)5an5b2cgV^418)QItA*5wNlhFs$&NXE8y`$ za91;YWj-XnJcZMe`56D`=5z<|FU0gsS;8G2IQ*Rd_E# zqTK-47F&W-ZePa6K$PVGE1{GTcn)AIl#K+cD7qhGL4fFq09|9d?@s783Cko@pzHzo zJ)+7W$~yqNpu7TMi5~;eu1*Aiav0zg%*V*Zq!*URtO~wk09agU6AetU{Sgk4-v^is zB@d!}22c)V6(r>}KvzqYbI`ZJSV@jc0OGnri%5I6N_QOp1#=T5`qiJy=#t@RMa}fs zQBbdv0)spNh$Qj?Ty#6q>*B;Jd*8grQ(s?T<uPj*Hyk~C=i|*e7KeVQ-3pPz07gT(9bzO;@8u{mzjH1TY?w*t zi8+9By-%qr#7Kph^eJpB5R40k{31=S=V7`BneL?2UjaM~Wi_PtRs>Sp`oDz(=BNTB zr35i3W~4|ay|x=S6~eY^`8rHU@c~S4p!hb*_YZ&&lq&?j1jxjiAswQe2UrH>K?0Wn zvIa6X8lp&hFi$}#g2;b{XFZg)kb!6WV=;+gB^U(h4VqlrVb}xDYZMv)XoT`PB!Tc2+$^~ z3gt2cf7%{s7;auY740D>tf7X`9%ytrMjzxCd!Y2=SZq(Za}P8VzCkzq$VB^a$IuAM zB*Y5wXDAbG0o{wJ84ztZZV{A+A#C7dV15fS3UPuo!i0)e!XWR&p&b5IRA4i}D^Ol0 zunyp_P!2(2sGw2{%hy0BAU*2=x?1u5^;Yy0B4;DB){4jsEW;sMD@;&&LpodWHnk#A zP~Ji8&#f2%e06{| zgrqM5n2GR=Wl#pK!69-w!fDHLD$F!tBk$maWV=4e_oYG&=))U`P!>~}K~NxZlqEpD z^Fp}=mYX4oly(L(P`8w40Vcva9)dqBweSfzF#<5T#Jw(bGg1p9S5W~sW9K`Yp-5lq zmLuHh&VVMXt9-_Mduov}pM|~aW zzS0CkF+4>O7QY8B8s;Fg6g9h1ejMskRsobD;&DjgI)GUSq=`>i5AY7G`yugeSZVMh z=w;Yf0aCJ*tpMV>S;^E7FLK7slf$(>G@#UH5Umg2L;02f^`RZg6-W%l_oP11pOn%= z(iEy&sOmu5JtEXz|X_=zD3DbU**#}V$0Q?KeS%|y?V8l>R4H=T2j~~}ilEzm2v|bOOsGI{^ zKAaOE@+g4&q0EA?Aq7AeV>*{b@kP4B6uttspb^T~ zkc6u-H#(w7RoXp@Ux^lnVH%49N3>#K1E^PLQG=0M%%pxerouT(>*VWL8_8o}x{7=% zM4mwYVF-uF(*T}=vWmb6fZb4bL9`zKCbp}`3wlqZJk;aA!TDE+*5j|BoQANzvr%>< zuH|CHDRTi@VGfW>w;Je?SnMePtcBb56bymWW!@(-q+qAZoUjpb!k zIDZDiCy<0Uk(VgMTu93#TI~G}V6t!%_@#=oP@R#AU|YYZ$lgW#IP_MissN?RKA6rS z&-W0++uQJF0>8laB0~39$%~MFe}$FBkY(r*QdziNIRhnxBJGeKx4#O$Pz*n2;z;96 zI4bErr*7uK)n_-ysVX_V;Ge^F6p9DQPu)iKB6W-lpz4K zp%hcGq>(i^#$h~D{Ao#XQ~V4Vm%;rzh+F{hJd_Fo*#Nts?1ZGa0mOCV6X?e)dNk1U zZ{7I*Rp=_sd|K|b>$$&`ln<`wejlalDIMkh0?Kg$l>1*$njklF(@$K#lDo$vyD+%n z>pT`v>my`cA*~?G;F3nb08!QgBthv3N!bh_uFFn-uNpMdmHPlIh<^fP!aEcqe-7Y+ zGM2z$fCr(>gTzpL%8#&6kKaViopV2Wtc{d)*)&o{QiEd0pqgP-sfHxaK}D%l_!wIF3cyFOeh86Y1o#@tmju@Q5|jd5 zParS(g(rqGrBuU0ZU4)!Gm6&ge!y6K4{oe`Sg&-nsTqb=RCEy%?%auqT%(+hcqe2+ z4_PNqfjJzvhz_C@0`!5>i@<{bw?MfWqFV}Z4CQ*DoSt$&4#Pxv#zVCJ7Eph0!_E)& z*A46a5UsyYLV1D!^>+i5^#rKDJE6QvfckqqEQT`O=z*&kbpGo0Cgq< z^fbd{z8Q=_}lV=D6wNR9rE6AIu*3=R;y>0!TRk%k|F#K83EF!eJBK8zDXYWNF3W4WQi+Mc9o& z2IU|``$k}kR*MO_gnS{F5vYA9(D~zZEWMF@ zucfk6s=EZ;aY{w+B@wrvi4g7mWH^*z1nA9R5|jx9=*{49D33v6?m`0X&0r(YdPvus zLBe~;Pp`BzZ7-#18=q73*U|brs_W7w(Wk=C;_A>kL&y=6;;=L|(pSPP_8r`OpKBM+ zLoJ*r#_bx6s!ziFS5$HcB7XvK3d#vc423D*!_o?L5z?~-Kw+H zP=AOr0ALK1Q4sB8g0E4hz~~r7je0>ytV5%;j|m<^%zTLUF+mxWQb^~=1Q)bU(9uAp z{vb##REj<(*o>e`Dn%a?)Iiy*m7;e@Js9dd>Z#NwAt?!c{Lkw&SG!L1(TVV~p!*%M zK-cLrq&ZA^={-_~a+v^Kr-V`HE=0RdW1!ql21=k^r`bUFL9Sn?j2qXfKwkImGTL-e zq7rfQ{n{lPNb}$hYRgnnvEq)@=7#l1w-%z!4LhLxi2%(F??HK&0L=|Yq4)^U+;BZC zhO*t58$JMqzcx1{RKY=?+t7OvPSmzR2)3a_Gu(KGWLYWtpQq~}@( zl&b{jxfXvL1{vhWbL}RS|CO3!XJLkL!iO1zy8WXR{w}RUABH&tu94gqa~+X6s~Yvm&t z9)fE=xs%#KKW&H#M{QE~yUKnX%peoMu#uK*~)t77L0AnrFP4AE8qgP;r`Kr4V5P^Lp-0*Jr9 z0*L$(4W;XM-%zcwzgYJq{07bYpDqs2hxiX;F{1QPXoaYK=s1Ah5w{|hkzNLwc?&+B z(f7n8t3wm3QnKLq3rxn{IK=%82l^5^j}`--cBg5LOQ>Xya|N`Mn{^qV|NJM zODP3?ANd}F-i2u2M;?XpKRA02@T!U}?t8b%$;rvdISEN92@oLEgep>`NEZ>2qKFlw zsYnw+0SjQ^+Qr_mcfBGO?7d>g3YKf{yt(jR< zc0I3aYHQ?im-@_On64$l5*wo!nJP*vVTq=I`(=B&Q zOudMi=bfpCk?=ho)jKj(fn3FUfd9KGiCa@;Zx0JRRwPvXKoc~|1i1n3xpJN=fO6U0G@{Rq}W!+ zXxQ=7VvQCCM&|*|q{B-!8P16;O#buI2xXfCd_=kTNTw4+NNf3|%G>BIiTd^!QJ~Sv zpt+$?^a!jbk|BBJry^vpB2xG}i_9S+${|i7 zvw~!8&a9U2I!3bDK5V(f*}M*!Ye-(@gi)xlf;w8k4q?lyB{&_{0|?zG!LkKVbFHA> zIB3){Z263YmH}@-;3WyAdg8;s5fah4H}hd%fZ*&==@A2ChHu#@@EY|GTSj{We~R$O zq-Z+CpJaX~nZqG+!|8vLIS!&Dnf4@HIUTZ~xf=9JxiT^=ZAUvr7XuGNVh}019^w!( zGfAZqGk1a<3w1QfJPL6kne$0)>aJx3ppQrAq;H@x(Qu%(@Yax`J`m54d4g0b5i=g- zYp5?tW->&{2vm@2XG8pe$S2g^%z@|vT2JyaWtd=2@&1OzfVGe0jth>4QwvAeFv_S# z%<(EFf_>vR(DJVACA_`}oHqv2IJ#R{dZsG=4)6p_j3Y%~K+GmHi&QEx^9#rdsAVJ* zaKHLeG8dC7u0_{(*xk+>f(lEk*xbl)Z!GWiD#sd3r$g`NZ)> zMDa@cUr}74vSLd6B97y@t*Twa*<-27H@kDmkJ4OzR#h$wGL`Juqu+s_L-l&8Pwhsq ze}@q5>2-r$Jr;m)@@mf|(}#ll3%w{tE4-!+SBu;wfKg~UP;6LN(wb8S&<4{0KE%NL zq}urqW6|WZFEooFeg)l3DhsdYKsf?QF5VO5e$WOx51ieF1%Om4j%g0EBUBx!wgbd+ zQ0>f3M~I_Ak0Q0X9`sW`PHd%~o&GdGsSE=(av5Y-h zfn{NnizQ&s!rJH^O+BmTd-uxe6T)iyg627BKa*r%(7cPxT9W={njoxLeh(dS&wCZU zz+5a7BE-fZ5KZlggxBVZq3jO;nN6_M=*b`#Jp}Y7YG0L|wGh9P*-R>xNaN=~%tj6^ zcBLXD^9jU6GUEmG;aN~AjE^$fXhFE=5%hAik+8f*5$nYlX^I&#CsX7&k|~3Dfy{al zEg`-k^OcBt2tz#m1Ce?NVk+9Tz`m@=c^IH4+#V#ab~04H2qOx&=@4UpN0ZFq5HrXe zL`t0vQPa%xYADmKKiqQw{srd*Qj^OPF5}5FmqXkDdL0R~Ygz@~AWHHYVi9H@2-BZY zKDr6)-1T{7Mi5~U*Vy4G( zVGT3H(d5VL>3FY6UurxFChmD=AjD0myn$5Jo;7C>aHD^P`KS-X!=Mk6N`;!?+aQ$H zzp{IV1m4XkL!}D79%QNp(Gcr_-=W|ur05NZHf+VJNTm`pAAuYWbpXkH5AhF~?@3Kx zVBub4^`Y&hu!C648Rc81|78sojFg`55ZJrr-EP z?-{_Sk&5;sM7L0wQ$~Bl%Eqv(S9=yhCsSgIO00so0qN^VnS!c#@|y@p?a3@#uE!4B z9fFcn3q%W{)Qe}RY#V?FDR)1qaW{zaa@akr@a~X$sIoP}A4_;Vz#9m@Ofr)p%oqk1 z$&RvGM5&BD;%5}Kd5c2vC@b#?JWyJj97DN*P{%`<6%bV@Xi92x4iA5e!^Ei0sfv0; zYk+#g+kq5a4KbO_-lS5AnEOF4g*u;PBL$3-Yz&xie1Y9)o3LqTiH!F-!PCFgeXL34%mL#eUK)hfhXH!+ zL1&T7^AP)x*^6X%eG>I;frtW){t2q)QOE|~5@e1d#ar8nR`6c6cv+Y|PeNMU&qCk~ z38glndI~}X5NlvpzXhPxx4a#wUE+I@*>;JK7x&D*tl1N(*te8w7~A&s5rt*NjWp0> z&12TtW7}m~FfO$$)V{%PaRUy0GlZJG4RJe;TthOSLo{RGP)IVHA?_q|1F38VJBBSN zW8bK%v<@=+QaU;VI5Q4mQgksyKQg^VtbmwCW*-rYAZ{dcEvfb%hz=QoXfWj-gm?k; zX;S$hD)e1IY|O=1-41&ek#-M|!EyT(j|p|A1$CEBwGoKD-K{tk(j%xG8&nq4e=T*K{0`&QR^Fm>Cm-GAC9ZCa)c{*yS$ z`@mGKQInw6GD_Ob{U22AH&VR0e@?aWrbwu1(CS(VX>(sf+!ZVK8u^?*E{1IaGHroc zky1H`%Q0Jm$XgULd4St*fn%nIq&dAPhMQPv9W8uz5xbHwY9@^_ zw0%kc`(`2oB=ZMpfw@x3w72uutjnOcaY zWEP0%4)F+?2T0{VQ7R}Svn9!7iaC!M--ss&(2|U=@;umsSS+t3Be%+H$f%9H@J`pCcpD;%mno9@9AYOjy+mw=m`P?Tsq7?N9Ao=5 zU(Cw3EImS}htc`K7r;M{S{6Xetk{9-eT1e3wZBd_difDJB zc6-s~q-bA=kz|I6I2d9cnL|m{3n6%rq;>^=yHU5tFl&y7xEk(7B(G9$J*`1GO9jVr zpr(;Y|0e(R>eCkpeL}LYK9x*l7?C(vL{=T?g;QzCi>T^i2)@&z6P|fMLlGN5sy+t7 z-^-lBpTnW&k<0}U=a4y(RH@d#90k5T7RZ5z(<2U3E!6{GBJ(-PtG$L&BdLVWxy-c? z-rnr8U}YYrxLWiYIO-C;usP1}sl~XPmwgVdI?OAV8TDcLjbzkceLo=65#%jfa$Hb2 zNYnKKM1F#!kjq9jNk4|ap2j;X%shk8<*)9|JQk&B%UaxMLCTdw@ThPr{!D}(OEO&` zR+2fMR6d5n3T!W2gR1?Z)W81flcnkrpqr4ojugEB@e-NmNY!sa1ZOX7@)>{UQ%Li# z`5fXmxZjgdxCC-7JWag*>W8FoB~TB>cNbE0F2vqsCXjMhLTC~?=u`$Wg$}WW{#Ky{ zK*u1nnACb1gjan!N6eT1jiepCg-ptE=MO^BNT{8xf>SubipBw5PT@;P=0J$&$UG?G zFo@RsFdj&mv6PaRqbZY&`^qwiOgpr~<*eRt6k5wHCwa2iAL*4Zg%M8-FY&xm zzQ*(VTUQE4G36DW5_(ezn2L6OQLZUOLHNnZyl4;&BHs@$b|ghRKpaPADJj>^O1)Qz zRH=$q@4mHI>wU?4E&5cgNHrl=e*rqyV}=&!yP^HCF^>rr|o$+U%do6M^s zdO(!!i#bx}N=oTc>U7Fjo&A$rHSvRm1HH`kNT{tA#}ZnMGi$&Uf#)}1w3R7dbrs_% zb2m&i*BZ;*rnw%35jWQ*bSh6()=aVf9=03)-U8GCk7`NLy%3|wj1ch@#5^*Gk<6`8it`3r0Cxe{aF|KkfM7bR**S>RQn{v zVtTXvXuNz1qEgSr6|~Y`Lq~0aD%<;QE8sWNgKzdxxM>HlWhB{$9a) zq}0O@cc7#mB|6`1{0P8K2eX3{s@+aSf8SJ|%LCeX0r1TmjvWLK^m7kUAi5S-(PYjQ zNYTR(wPae0xE-QDnLZ@*Jj84=vqWrySV`tYQln2H)>Ciu6`9LHE+JLCiyaNfh5@U9 z(w10V-^vH*%z3~EPGQ`TY=4Lwz^&Nd4{ZfUI^aM* zEPH^@gN+B^Uly5zebZ5Xz5smG6wg~kDiz1PwGCoEgE$-3S)}r*(ub$z3zH04*|1F` z-P<=!`SKc;;vDHzGCIMWjYYak&zjn^O#7-u=JAAkO3c+6oK8V4vwQ>0x}g|)J5iST zhKxqxGY#UlzxY;FO*~TDt!tN*ZqW;;^k`&a6xe4T>&84Z*3)crBY&bYpj)P}LX)DF z5dR^wQA9mN?jX8=)VME%8Np#VR6mlL0I`zHiKGmlma=o=2vjC>VrC+kHUWnu*pYC? zMMrr9+RD=flsXUz&G#oYlu~7iyV?1ECQQwjms{pIyZ;%l<#9HQc)nl5+O-^t$fY`S z$KmuNK$qds#iZy3h)2jgAmS~EPsn^gGM_<|P9>xCGsFR8_9JCZN1tZ*Jla%~qiFpr z6N{O<$Y@#9={rml?zG*qHpt6tKtffT)KGkDl`42D^M95ABwOvej;BvrqcE*nd^HW* z!yb$w?#B_7JOsM`o&>1!W-P3QI69wHxj$ciyO*N8;=r+)&oqAVRM zm6uK6ML^g*OTlqDP~m;PDW$`zZ-T}9$c@+WxArj(SK`!pQt>pz2^3#OYP133UO46z zGS`D#O)~$1c!|t<5|#cMasxuQsrU~Nsp(w(7ccc+sQ0if2VW9<3&1Y0cP4q6rLa`T zk6@|t)G>1=m;%|yO<`xxra_XoKKgqV(&n0A2gJW<6N|UC;^TCBSiTudYeu=+ThWqH zBgxQiiBdJD+GHC|JiW&yh|PeJeR(lG)RgKa#(uj3AHuw5#*tY*o%OoDs&3C@m3o*XzsL3q{7h*x|n1Ow;)qZYOKN)#cg?(%-DwH0$69PGK8To~;EdM^TZlL{+;=W!F5;Z~7T!l*syOR!%cMLi+DAoH1s!4R&n83Pf_WE8+@ zydOm4Lv&cA!|^(trNe3tY1!GSt-R8)h`+g|yeKZ+^=RlsY9_1Jz%ZyGq{cE}qTuo~ zrZA83a2zC$4BsK#8~8K?P9a6pA+95H4apo1@d%lRL>ve47MYDAPJ{TK%(o&gf=C@o zM(H|;He{NMxC3G@GUG_qk3cY!nHTtbB)~#a>MaO)vjzu8>OA#5fHUEoN^1Jyl9(H* zy01jWAkp|IK(Fc39IvOKV|9QPy#{z21#cyJog^~4-BuCHehStTVtZv>F*O@LG0&i_ zYG%wFDd`XVHWHg8Ra-_A&WC-CoNElR8Tcns#myAe7cVqHvn~9Y$==xS5zu|-!P6VZ zFH;JBShU+{&EW0}bKAasoOu;leeqy(EQ_vqvTqkmmqvZ3z{|Xy2sI@ZV}laH>^4Fb zA0AKe0qBj2O<}#xzvqCqM4~yVR1C8eq#smoTP}YHo5yYx<4bue_D(o| ze~K*uoq@nKQnV6c8JS~ArIIq|f?Nu9A<0|`@f4XSNa?93a#Co$(D7!xX?izRJ_7h1 z_;0Dea)>|3{4C-Oh#s>EMv}P%VmXE>3~y7R?iYLN0IEm{HB$m_mx#u$O%)$yW#!v?Mu)zkvW}IDu($LEfnywC^<0)fQeoE) zu>>wAa?LLZqd}m(VD}_3`Zr+aA`HAhaq|kqMDQ`BM(;wbg=79h=4_BNNU5(NdZMm` z!uPAp*8sP}xsBvibb+NCTpFN9%0SuIH}D8pCuP^G9@qQfB31r(;O8mwEU8o+V{YWp zMX2{l9e-HMqo|<%vq3mm@`bna1`C`&NYNI!rSn(>Nu?4q<*?gBwIvb71JJ&2ow7O> z@z?*G_jX1B?~KF%l6^aEFESHs5ig@g(w6i>%;En3;ceyCNX$iIjgz=iH#sW~!NfPL zH59V9={3rZP7f&vLvl{VBRQ?)>yUE-oVlBiAWS%3Lhaf&7 z^MQ!xAWG)rJ*h&2Kxh57eKls7<9*!{)`^bYPHn~!#uZ2H04g31T24W|wo|nzXif6+ zAM5i<9p&Ifd1M|BFFlBGU;idw!vl?v-RO|UOpWPX5HKxRIv z@fH|7u zz4VW-F*(8a?Qww=rP=)a4crrn9;7J4M~udh8BH=xAPyljla$FbL>m)S|H5#5A;+tz zPOyZQm6p2SI|`i53`hA=@pMt%ZiFqWckwHp4c?Id>a}B0el*D|n90<5jFr)mA>>uO zlv>H2B3c0FTx8BBnd2aCA#;<6Qz0HD^RS2uwjokiL+Aq;j0S?hj{QalNj; zVdrkgKG5`5%SHHlIP7^6>95Pe_ahNNR7?x|>u&pluEg}P|98-jI(kO9!)W9;IC@SP z?F0QUG@WD(X0#d6ymJ$l?A)foy4}>18ANG)EbX~iBuKB;rY*g^UEApdVjr(UK_UUo zUFplkEUa-%ylk(}V*NqkX8PEb*Ir+_Dx_#LeZk6WuW$1xD4XfCIbO|<8$&P#f1NOW zWX-E?#KkKUE@lf^J-LRHyl_fA=yIE#uIyDdJ4@NjITG-=x>w!UX7kFnvDu!=c8vwD zCfhF-P<9ua9i;38n;oX?WSbqS>|r)LTG^v)c8anm*z9y=&$8J=l)cnuXDfSy%`R8= zPMck&>?1b&sIt%7?32oFwAuB_er&TZDEr<5E?0+xXvpfP`YT(_J+|uOXc!YNWSyx# zqf*(Poe`K+#$**P@1iW@(uC&;Er^@%Qe+S2PFs9Iv3eobZzy&O=!d03b?>hF+c?Xt zUHym6zAJPx7t~ESmg~ROlXh2D9{{KxQ>|im@%_5$l{Pz;2fC_f+3XMUp@+@xFCTub zlI(J2`&$iqcBpznTp^*$Hp`v0DmI~)vfbp_mQ~6w7W$6Ob`ZK_rO;!f;UC*N_e#T# zwwkmPckiv<)e=}~vs%Qf-?!N&s?e)8%Nxlx)je$XT~+8to9!d?cH5})6>_KArXDSH zfz9fRebu)-pqRW!=*3o6*JP@%v)Mr^R%-j=TA{{fwG>uQw^@Dft$M!A>cpsey6r5T zzE{t;**-!~yGADT{#kX8yOjL^f%e*X?0ztkYpvvLB)#_9QOpteyah+9_$HhE0IS}B zqb^_6bxdZ(j_7*O>=}!@OkJ>O`rH`{x(=H+ZPA<=a~B@bb(cdIj$Aag z>)-{`7aclx-q3jqW^`UKWA2P24mzUijKvEV@MqznbC)bSVrthT7EJ3pf8K(H2Th$l zqpOoy0H;US>C>i9wz)3Tya5%LH=4g--n1D<95H$Rq4Q^So4k1Dj0N6++~rw`)U+B< zGiI;RqrHKX80SiDTBQe0=C4wlmTA2cW#1sEIidN$iR6`Pj%_h8#b2eGlba9ZkNwxC zV|w7zK9__^H5WA+$dw#Vsm0|5181U7sdiAc_sl5Gzf(hw{z|ao5!^V@PY<;p%e)$y zL+38!E=EB*!#*Q0H!wTecMAOuO=K#J%-vc36q?)l6WzClNw7;3+TJsxITUa$!z)lO z^b1p{h(E*Kz3C~Em@DQ|9h3`$)Pyt=lh>l7XVY6Gu}aLO8C8q$5sAkvL7=cgA|fT!>ZjM*BDbT2JyfE3uz!%m=4ca_zKQ1Ksj(8zTkb_) z0Rr2G`p-$YIxpd`XmCG$Y_Z(94kS#^uAxflMlET9^oQ6gNY_%oRQhz*mBRGf z9_3tI{W1YC=9T!tr+%2mo7~P^!3nNY%gIZ4Hp!N=lh<|xCttW zjPl~}u=H1em3QBZz?@>`y~=;?fS4P%VP5JBDhK0dxTs<&?83?!bZvN~C5rGuO%@$b zwZdb=>ybw5vh+^0b>&9{MYzH$@+wc1Psdv#sQeh~;R!`@JF3(h{o#q0DDshpWxkfK=6pb_bC8WxBI24V~YjyxGjP@~G1n;G3 zYTvx->s8kN46&aj{Km6q%;m*!TOd+_DW(ShD$`FOb5O~2s^V4t#vqKQW^I+dCWXJ?HtWGFUP80!o40}Dr{WLun4J=u z@!y0W<_SMWviap4n(aA$xMv2~xT3ktj%l4}<)z7Myyy5ax&vZWdC{ZljX}1kkq{v}QhEJaAncY&QpwcwXERv?tbdwn$m!uWt z?3nO;mBf=h;*w)jazaY_9GJM4 zGbN#my^7YVpXM3eEnPV`uw0RN;*|`vH4qN50)QGS}p?&f)cOd1zA`c(|(pmeelH`lhD-bbw$mw z37z&Tri;HUDUT9tFA8gLxv73C%N*HUnwxHrhs#s)Nw!y-osg(_kGM4dN^~**QTBvz zf0f-!bv`jEOO4DaDd|+%v&^q5`;7ct6_*Y1bDrAooTUBek98}d&rN9j{ze|0m(cjV zkNWHUgr+~9tbx8Dq3MqWG_kobp$oi<@0f1PMG0-ZiXG(D#R*L-rgyCm@`+#G&Jw&`Fs*DZ}#!)q=L()D<%komRg-C{ivd-RNKKiS~X zbLn~{D%)r*JfC>9Lc|MOJ$fd!i?pnfmi4hmQY()hGY62%%KM{lMs5$jHw*cf{>p1IU)YVhd2^utJ0c9z8ZiAVpS-+ZvuqjyqoNy{rW!0*N$ zNv%A3!+cLJF9*E5G+B>c4U5p%RK09oi#?JC^~slJA*_mz*qfNI8hX59;7-urB+)~3 zUaq3wC3MPbvHOs{xw;n9LFBa zcWWzmoMsx&Pss_dC@?ACoPsp)uRM!5eoXI)~_G7(j z&|TsHe$>h~N6rCk&}@6;9e@WVT&m{l19*_ruk0D)$8MHu=#}!LlyKx`W8eHCH*KRd z@f%ttV_T(J0{Fc8W1FSQnZTxPmud&ZHp~661#y`xQ_EB&HubSL)7($V8`*5*8$Co4 zH%)D#prL8nIgPGqIwU|t({ywau4y_sz%@;s16uX6+`%_G--w&0=l?cMum5eD-p+(;nm!JQZFcj+zNpKcA~W3+o9nS<`uZt(Bbz(> z<^|cT)LJ#zDM)#l0qVCQ4&aoc85>bE)B%PMwyMZ52M|U*Br)6pwAGb_rWxS?x^zEP ze-{Vf_hji9>44bp{(ktQ{GKh|fW+^18biDKDb+}R@8O&4b>cK#^Y>V%Am?S?)bcpq z0U16?tzekofFduGm79AyAnj#RoQ;`@4xsLX6ij2l^@1Sv8yC8{H7el&bnOodRmcl`A$Z z4k+<5Cuqey!~t0z!;{TJ9l+2(4xMI}189t?j0kg>189sl)ULA~Kx6b)>&$ULp_kc5 ztuxmFv`#38=Q#i$82VHFQ0Kk5zM9#mB{h3Nf`|Jl)mb$=$~XI>EYnA=$**o{Nez5z zwugdpi36zF`3jt+4xnaLa`R{hP_tdttH(Hin(e7RJJtcztiQtkI0sO(E((=p4xnbC zx?#Bks98=E^9l#VHCyP1%Wyh3OQE|cso4zeVo&f>s=}7=x&x@$_bPIR1E|^8>Y_6pK+PVNS7$kZn$>frXI43Yn!T(pI@Au$s5_^XF~U&RWkZbJ9D#B zKx-bW=(@!LwC3+}{ZX!u z#DmHvCVM~#5j96)2}?ApBH0O}smz~)T{Q1=5B2%8*0RadF*Z#jUfj#B%* z;{a;*f*gC-0ddWq_e1r5Zj1E4kksrM_1=H{lKN_n89- zzNghApF4nl-=uN*g#+mKBQ(){=>QtT*EIH(189uLG-$qd0FCjb`s^DA5E%>AI^Q~g z*7-<%_MHRbq5PpA)>4n$+v0tc)J#9EX@2lis^e2x9}b{q*Gcc64xnatYnu441E|?jZ)GVzA{o4W5Y?NZ^9|usg zDQZwJNY;h8W?X~&TQ%#f8FzD1vyXM676d8PSv4!Zu?GfN86P60KmM!*y~fSTzu zS0>{CYWAlFO|b*0*%Zz5SqD%v{fe$BaR4>@NIjBs05v;G?&KXn%_gXIN*zGWisVO` z1LB&QAl!sExvy&A6$J5axvg}U2PxHAHER}_N`fe}L4i{h#JlATqkoJ{G$xNZ5gCwTqfEE<`9{9Sti;gCNzz$Q~Y$;USsPZJVP3v zk;XQO#&y!zF-XalGG-?}xkM%+LzBF3l&WXk)8t^@X zlx#_3zrYluEc2PVuYaPTke2ooR0A9k*Sb#-c1Jk(s9L0NqVYqG`GG-7wxn@bV0M?r z8`Lv=wR9=4e%nAU4GzKuQm}@D8ImaIt-(DaNJ+I6j1J71Qt*`Kx81i_uxk+BDFqiR zmPWZcDcr{dDXEr%Jp=Qy6wFdx_u5{;xFFmt1qUeV$0rK*(5Rdkq@-F3_76-CqM+rl zUB|P5OceM;>`$75r#OIC`awP(6X1OyPS9N|6>T@EwJx2sQV_l&1(vrmQP4<{a9WVEUn)VtIf2=m0LTnd=$*S&LEPi# zIUik*U*G`O;}<%Bmbh0_<3$c&P3ErWnNTw-K1_x%arGm%m2yBPn{SfM3sU83<+wbz3|O17l&@xb&UAmc!OB2l0~wsHHEix(HS zPdmWH?K94%i`(@Mptru%sCm`_^w!4;!si^ImQZiK;FP*Re$hz~$P4Hm^OBQrf&8)q zs6|Pcc_auApcc8!Quk=kc#epBHPALNQ}NfUS;|3htNX|la!yOWM(uO_R*?31J234S zv6(Crta-=z!5aLlCZBg5Km*OAPt1QDKp)(u*nH0ctiiwP6zF{i5Z~V_Kt6B)ZCaz1 zdg?#3Y84IgudYKGdBbZl2e>1RPo)ltWO7np-pk;$5` zzjr3+5F+F2AUs_P9;$)&O`_m^MaGXoN~)#ckHFj~1vjZp|JupHfi%9i(JS8ck@bv6z{xW=MtcVii#9=^Ao{3BZDyDW?)9odA)BTsixU za4@BF!&K2QY&=dxH_bJfFf|b(?qk8WkJDTTB3~oFW^M(GA|CrN>i{yf@~=_YbhXEA zF25ybqyowv(89}Hp%$)iKy%hv0hJD*vq~b93&Xcjm-|Dt$cOeiZf=AIU6U{+%c^_J z(ELg^lM~)5shJ-)UUe8&5j(k4G?_FH<1N&s5^NKuq*@C20h-C| z?k@!+nX*m$M8R1grgNB*YANU$n(xVGCJEosDIl`%Qi%0(0FnJ~Oq$*fAhJIc(8mEp z_6Z8Az78O=Kh-JiP7WZlN5~2v)?9{h-LlK{RZk6YKpe>3!?3(He&44q?UDE$X-w=K zrc@*OJt8zGA(Yvq=H11az;Au@$c#*Y05=~}MRs)(xM@#VM$xP z@kt3z4^y%wjk7{?nKbGmh&jypNW1JLKjt`qX85TFV6L;tG<=w5yZH`49X1aR!^dTF znS>8XZ0@5LJv>aw8`)eEn%1@0>@T6Ei2|)BT{Uu!b^uOXuBq-=XM)aoLS7x00P38# zG=DBjfH3ZyBg1eP^yj{i@KK2qt=Z?96=6#5$%%i3<^qITP8heBXHE{AY3>hnpQzlXce??u@hKDcIDiniz6Rhv2jD~t z1?K$@z=_V90UvZR!K`tshV(-Yh-ZyE!f+G@bBAi6+?jO8k12>p!j$}#S5JlJD0wwO zE%CHdfL9$gy*%Rp>=D_Ihv8~zY%B9mBpUY<@oboqEw%nDp&8U3jpt~Qc-6HntHwFn zD!k?ZRt^0IuzAA))huV~$TuBOMU;*0#>(v)I|r~kz*`QWt$tT{z2gAd>LYdfyAGhO zBK5<24v0JK#W0+KkGVqDJo9px(#n>5LN)#XBB{t{p=s8Eiu_ps{<-sticD7jeBl5p zGE9y7l>-R0o@$e?9YCP9Qy+Zm00QlEZC}54UeVsisRw^>05$8RQT>wxs9BYY{OkZ~ z)=0oF4v1^^aTxB5)43`c{3Hp*cSZabrc`IIbzx-oN$Up^^Lh}&%j*$`Ag_lNqP!j( zD9GzPs<3jU9Js7XD^pQk_tlFl|5D@LV4;%AMQVl{t26}jdEMGB&+B$_le})>R_AqJ zwkEGTqOFVXQ+ouym95R|zGa8JZVPtG>qcFDUiZPeaOGcye zy1X(vuPY#9^15m&xchnBRbn}qbbOX+Gqf?MAj%shr+QtUcUXK@HYbf z=TLJGgI%p|1$j|YKMiV2uW%sW4?0{01z66dj#J_loFWq-A~tbW=#K$ zOzKU)tRI9|{4=ttjegl6s6oXC(59(PF>iVCu>sUuG4IjZB@CO?+etaUR+B;Mour^& zo5ioxyGcpER*%f2{*x5-Yu98T-%H8{wR(Id^?p(|sMP>ZeUOw5YCDVjVNy2eu>&9Y)@o)+ee9R%hcthPYX1=ViC?DH=U$NQ1=Y;&$IbrTB)NPI+UL+sA0NDedND`YJz}e9i0)BA-3*Yquesur~$gKi?a{vp-T>^f0KvQ-N0{(CSE6U>n{&YZN zE}#kcuLCOCx-jYsw>Y4JyG~3*g?~GsoO@dWybeiS8gZ*uK;VEfFSECR$N{CSjsglC zkoPj0TM7#uz{<8*5=9PRWm_(w*a4i7bWo8J2eAK~E+Fp!ZNmhVIe@iqp@4D+=qihV zN(Zn_ezpdni38Xpy(OTT1GvhfUlT5@b^xc-=L=}z0Cv{Tg#a}UV84Gpt7Kto2XNWt zTS?S9fXgnw2x#X3VxlA}{HDEmolwc`%Fv3Z+ALt91Bj>p3RvU-;wfOkDLm2v#8XX#CHUTF)fOxt`z^M)(o*of!x&w%(gR%f;I)HdORKO|+5Ko5-IL86R(-Hya zIe>UtA>aZB5KpHFxX1y-)7b(paRBjjv4GVMAfB!gaJd7Br<(*^=>XzMpJOPz+5yDV zMFOsMKpaoAI+%roN^T#;)9fUk=CNxoyuL$5k*0XMwL|)fUWzAm+igyP;z__-2PmEd z-0lFylYl!Mpm-8+rvnsE0`78v;;9;7odXn40`7Kz;z__g4p2M^xYq&1)72VW_c?%g z+LN6{;R6m(JPCNn0mRdE0gpIh@&aRBjjxq$Z_Ks>$5_OkFp2M|wh3;5UpaXj7B!8}Q* z1nG_WM4>)1&IPA3E5rn%zG=Bj85|5Kp?RQ}~kuh^IFM z{OkbY>0JSv9Y8#NEZ`Rh5KmtT_|*Z#(~kmva{%%5yMW&vKs@~;;1357Pwmv?e>#A8 zdWloY!YvLUp57Gjw*!c$_XKzylgbfK*Q-GT2M|vW2#6d&JZ%tA-~i(3FXZVsURj?&Jn zy8~#y_MDa%?%)9Go{9i^CIIK+T>L8R*fD*voOq1$k;1x;)k}eMOB5qJcFf5=?exCr zVAharuE=gKcf6wV!mrw=Helnu4s9(A>{K_(CpKQ?`!qn&fJ_ha zkr#DiPg^uFkeV9F4kOijoo}QKigvH+3soLvMuhr>p%ydda|%!*Em2_;uf@!nUS?!W z`WPrL&J0f9hFs&Ri{K0`*<{UaBycjrvU63c^78v3hFhW_KNeYDI@7P)XLhp|$}h@{ zO}__R$-~xOW_(_Gud(b-$b3hBu~#Dt%Gy)5v{y4)iu)zBpPa}=zp&6{_6#3Du**k; ze`aDM2_Pw~XE*uj{Ka{B&4wGyHCPvkRhyY;?bw*($R> z%!||G&?CBO`)^;l+TnO1M{vO{DnAiPe(hln4;w}0kCGSOJStId_3SZs5sXezr5OAx zjb5+gs|bULAimpN;P-bX*M$1n8n2t)dV{mWR{LwiQfq(O!UbOD_OMcA6213_)}Yib zrEu5JrS_VzVAlq<*M!Zts=X%cETV_ibX}~e$NWR5Gj7AO>*07i{#uEK3&H{orF9Kj zE(lv~)p9}DT|_U%!Uf?7E7hXP7Mq|hk6Z1Mq}A~GvanF{ZQ($EFo-{E>8&CmM6q*>2+<+ z{vtCkEO@BF(7d?mdK}6IFf6t)(cSj(Lf3aY)~MII#dV)E(AB+LQuh|kEO)Rtv4=fl z4`VeuCVp6Vdu{7(@0jSWSA#Qs63(3Y1m{i(VJk8;A#6qVOoC$C%!4_xcmCRb8@9FI zuHv#!*8`bwGHt_xOBy_G8@FjM-p+*4Nqz2heT>N_(=sf0yg{sGEEdo6w2%+o=^4GpZPgT`CE zT_4yfqi6TqTOjvp5Wm9d^`47+2FB?pQgFXuJxG#n#)v*)% zu%Jw3;*m5wu*0hR7cZl2L|~@}W&+Lgy>Hjr&@0I120IJAf(~12*e6kHi}sC+_Uvv= z^a~ov1a}0=*j{JqgRDYup7hv>ygsP6Q~Xt$tm=bas&YKv)(5-ELN`0L)Cc=+5@Dy7 z`rt54Ej{e;>Jq!{_4!- zlV`S1KJ%@wNgRFeCvjBsA)=D9i+7nbnWQWm%ezC;78hJX1oHZYMeL6Kk$*Q;+?w2AP zFsu9yYKAzpSNXkdXxnO?jFv$wT8Cy5c;(MN7;Z1J|nmN;W)X+|3r8#}MT z*eJiFjKv)`I_|I@wr0C;tACF~rLEc6ZHZhJxz%}$nI%oJz<5$TcLk6ZI<{4DR8>)`v3&*Lh7pv-8YITi@zHYw^~I^XlsN1 zo%$W6C1y+ZZ;1XjuC{cOivzH=Ww1>3x2CpCkfr|C(w3<*)WsV5Ya2V>wsykAPQQoP z$7X)WjvL_&{9q@d0XEWp=%YZ3P5dxgCI;AW{9!)@6(5=7VLNT51}>Pvn*UpcwBY(A zj{Ul5XR;xCZ-e3uc3y}TZ|J*K@rK>ED&DZa6n9xtMcLQw3N&!$%s!l=Th(1^Xtd0S zWzvb6sWNkB0nk(BA2*nJs+VmbJM}#^TkNd2EqG#O3>Rm5cA(vngmZ2)6O#g?xiT{Z?|Rt-o<)v`)Q4xZwA`A|28`T_Z(<< zf_K<$_dx64oyit_=kW&B*VJh0y|2OUHGQ`_c+E(u9%z^2>#8K@?OfTELYG*7K58g* ziFI~>Re#CQxK@ABMVX^ZMf4kqvvyZ^bgk$eN&p73j4#W_t9XlqJ}IHQB=pHK-BYq> z#(8hh{!KUun%Sve4^E$o4(hbOl&e*W4jQIb@%kOi9;WDkPKz2C2MmoFS$eW)&ra7j zF!mg7+p(F&$7}KJa?H=j>=mC}^zO|-NX<)EK1PXdSJhaehi+ziy&o)u+BIGIZUbxA zba%@dJPgN**M?PtC$RS@zAmilcOCH_eb{N}u8FJBhjw|j9T2fH5K%U@iGGWanL|b@pN_G#p^S zVyM9?GGGb0-IeqDG@%`Wd|;*Y3q;*crWC+|I`#1Sq-dZZ6WCM8Rj}={2rxu7?WJ)6 zv4;q+PYV{BpdgmLO{#YOzyfhd4gCeD`A%#%eQhabc|pwbDuJjl!!-Gn)n~MhK4q2J zlQRGRK4qo3EctfT|9qfofjIxCFH$8Rph`YJ#rsA5(i&<7x~vlPFP=%>E6`{)88=PU$;c zL0t79{uoyjw=Uq9SndL&rtL=J_0Ib2UlAHw0EoLAJj z4HA>`YKFq1Y7qz4SfWs4Q8m^_)V-XSdXzuKZ6tAgE8*EArF=|5_CWm|P~hpCXpy%o zQ$rF9AJoP*?m7{HBo<gcdZW6bkL?qxm^^oNwoqGQsxY&H$_9VMRB`bHeu^{T1VNJd;-R8ALl9M- z87xUo5e8wPNoJiWKd`*oOr5A8raEMvmW42;>NDqviejo;<_SrfnChANUY-@iRG-ZA zl1#-^|I8Xm76xVeVsB99h;~rvz}9GFX0yr_#nkA`^^(j4WebrUo0%r6I4I+@*4~uN zGm^~4l8cLn?n#YGV(OSop(JxLwLG(rB=fQL6EiDBmB!S`nP(+g7E`BZ^i)aEC@9l~ z(^XkL`Vo}JJWT1KlAt0ey9QXDP6X;5}2 zWk(0u5whAW);u=I>XDP6D(3DPWcL%dI_6FavNuXq^O)Q}$i64CMNCc!vWwKTEn{+e zkku2bK}}2^5@hvoaL_6yX9w9cM7EB}`9XGp$Tl&#ke_)~U@8c5DDg5};wE461o^!j z$Zt^$CtoPQa^^V>AMKqijsVL!#c_<6ULuZw5(Tvy(3;pUrqw8xE{W+U98IV`+y)nG zgK$0NO0S@<1uaUYqbvxgnzSB`$o#}mNgYXDJVAn_E=;6v8%3MEi-A#md;u|W;& zwRiy~x5DY}IMkpO`9c9@yu;ineF(Wm&86>%PE~3gpBH=@wG*(=0Rbb(4`+8WXCPd$ zRJ^&J8cVohg@_|NW%|L9#^XAr@0Z4ZQKxW)Q{eMcG}J3R-T?@sacL*>zBKMB;bRhw zFN!#!Q%1I=@w86qV&gQP=@dAPXE`9&_^(c;JHi!j*P`T4Y)RwAozlBY z<3BCIFHIEic(z^gCoL)pp!EVL*k8JC#*K z`IV}Dn9(Dj;Ypp!)Gbk^{5P3JHDKp-YSasf0y_-Db2~MXL`kLm$;G{VMW+^DL*==9 zf}pZ4RAn>&U-@!nr%+xtK9$x_`GaI+V@Ydj(Bwc6uSv+!Z*o{Iapk3MYYY3`@GljZ zLg~1G=~%Ll3hV^pHIWIw$yF2!ntYCY$j7llL}m+XiH5R|Ha%;`|tjr1pvP zYo&JIIR7u<``LWSY;@m47+~{ka;$Q1= z?FjrPVO8}T=qA%W#^2hH=J6srELlPI5T|xi{r90Y{y*#)_CR^0HQo&8knA49WbIQ6 zL@dR;VH3NPot!*R=APkX-ps$wvZgdA`UPbNI~fKjH}Z|8TH{N4vtsypyAH0`%QYlfI5z zX6G){ZGov$>)7vZ?$!g~2vapm06!y`Ii1!E7C8y-Z+EW*eiAiDuWg zhd0+Wmb&cc10fch%tQ$l1;H$n{*r8o40}0^%wVZ0vxdBU?_rQfn^0;ZiQ(j_CdGXeCf1}>~LX+C4@Wjin%2Pd0m63%v0_0BfA|H>p9FEZIf zrEv#oyd+V;{!9waGwCy>VDJEV7bFUfQtelpoK#EbM8gZBj1u`(Dpk^YgUN0noB2@I zZraAr2ZsRMvb~?zuxcQjJ)kGN>k>0ZX>e%@};y#m;YWaDU;bkXWlwYM%C9O}I?8#)yMvm|91y66|=Q7oDeF6l5S2lKc zFL*AY`2?smK5EjpQn=Chk!*AxPs~<#rr--ECtI@cn#n#(Hgk6e@He*i`(=~<4qkS5 z`Ta_w;3oCtMw63jS$UXO1tVORpQTbItsj{zKVQg=sg4MLvW?%Z)Zm|P^;;U=GwHn$ z&hD(H`yeqhfq)D?=Y2gm()gXp9xjbL$p0U<_wy^0zCa2l$j@&Q1xKnvKbf3V%gVdP z+(Ncgew9j>G;&(@c|B6fcir3GF0{oo-dPf%xzZvrv!r9hb*9rbGl{Q}M z<&R&Gk#1g52$q}lQsV~8@uuu72(Lt88sxN$1y{raC@fJ(L^&;E!GkeoO4Qs1IlHHP z+mx-LY^p?6E6Ule0)sN z{J$Ua*QzO^f>3pjUP0bYQ$IURCA??!Ez^D*PGjlHCi=f+gt}>gY!14xH z#WUq2>h@i#GEyxM##W_Uv0i3oD(c2>^&oSjf_hH}AVQr+SJ}^xX4k2{V-lBos!kKD zGP1=FzWYI&s`S0c$J1`xszxtDcok|W_C+?7x>q$i7%K29RQt%cZ^Hxwsv3QcXn|j$ zDpmXTTam%8RgDxM&3*f!#$Z%cBfZet!mp6qgV+#A(|Yo@>y~*&wj%+S^O55e@xF*S z0xV~XB ztk#zk9S~2Ti|fpHc#wTt(XzBI9`LCS5G(64yTFl~tLm~vT-eCiMd+NmmcxP7v(X7}#S7G#bvCTBc7ZytE+^GeaA{q3e<`qQ=4FY3hBfnw1W4A*3+vJ=r13GibaA4w zy`uK2x}0pu?5TC;0k^Is41sv4E+<>^^ZGh75TR1}RVv*w zv%W67ugus*=eh0ue6lXBH*wFGqPU65X=%Sn|KyjGWekZinWzOjv;cFo+F0B+5E zE1{D$^X0nqhq5r5ZVX;YEc~hVeWxxb+w%MII`b>pQu$dbTQd7uUABx<_KaPGzS!RH zkLuF;_C>rveUfOk3)EM2IjNF@AM3Icq~Ip4ML#DBk~!$xy7Xcx=-(0E_lbhL6~n*O z<)m6}eNbo4AX_RoN~KC#|E^2lPc~kOz4~}&Q*_ytI7k3mLmK|9Gy1YX_OecB-clD& zb!`SinEH%#OJlY^UCd4}UNdvsXtZl)X#yl`X1d;VM>u<~e9hFy8fPjf%Ih<-rOC6p zK7AlUW&3EC)1p3}|Md#+d`Xf{-M@wZ)c1PA{C&}(N+8vJC z-tl4e>0_nU@T@zK$A{D#J^5BDM@wZ)cBj>6OG~i(z9#1x+dDqFKHUpm*76QYw02fR z99*B1Dk+#-pFI(wc-YS0#&J7r4^IF$Y!^7cT@M`LfY`@b_34{rvYp29?8M}E9UvCg z=j4nkazMR#m~5#WFO_lmv8+D(HrdQ>oe^G>`&fMP5mGx=8K#{#g1N-De;}`W1XVvFqOMWh?H!~3`m0zXO zEi;$Y|3B2d2b2`W_CMa;)3w_*Jw3y2GrJ2*8nUpf$imL<&Z002h=58mU;+`rfPti- zB1kY`7En~4h#=;SqKFAFCrp?F3X1WW(=+@&pRTTD7MFKC{@?qa_vajDyFXR+xwmdr zSKq!Jt~VQ-igigtJufSh*OPS$kCDY8>j69^FD*-uiUcdmysg+&E5i*TLH){bV+hdT z!4$u_q2kw;NxsSM&E$Bm2t{1Mom|_8k83?6p@=6npmch;Os=PhgQ)AH zp@_@qr9D-apl~XFXPI~%n*~&~fWo*;y;A0VhfSsUrm{AHn~IMPaaGz_CY#|gBJb;N zAbLrySl*jFaNaCSkctGG%RGK+M6Gilh6MHN+!hTe#&^o(abz5u2FZINCxDiu(T0#cDRS}sokSlDOpeu&AJ zt1}V&xxzXEo(A%8ElVJ-0r+!6xmF}JV53IA;fT+NfUSh)m5U|R>>^$TI_2tAQ^!#* zD0it2m1tHjck?lK_DKRS)r@c|XTb-tT4(@HB`ZPKvsO7CR37y*^My*SN_L%nBm0q#)lvPaZ=*K)~M zDco0CshcK%-VRR`-8G;XyOaw);_oe_CCWm^?{>vbMY&5^oQ#=rxsHtOc>?KG-r%Au zT`oQ*!7rT6)#d6O>+&4ir#yIjfCK}|Wuz&_b6Ed6!x|V8aHeBk_AM8kQRc;Hk^UjU zr?kdC<-wZ*?9+&HxjzZ|^c{#RpRfygFx%|l;vod!nQ%%CDHr^jjyIM*{9T3R z$LV`H>Jt1Xg~>R*s;IgI&o2vPxN-VLu|#lhrbuC4oSscQPIsV5f*%yHdaIIxIM1|& z34ScVIz(Z9oF}cO34RX1Iz?g0I8P8oiJr}XU8=C+IM?2i1Yh;HZdX{dIG45NiLpH6 zJ*%+NIG2zXxXFb}y~O@xh?ED{fvppK+269ugDc23aUPj%6UPzr%Y)vui}OHfpE#LV zC)KJ$f-m`7omH!jaZbt3i6D(YPt|IdI44z?IA=y#oWr|og0KBshm^M%h(Xyc!599m zL(5wnkAdoz2*QttmA7DencfM$_-`Fv-l8xMFX2O=TWauZY&T(cVrz7Hgfj^fuy=)g3~=FoefkQ9^>j6|$%p$Iu#1^L@7y6b?Gju=Wf0aRp4m z0Tm*Hx?WIsU`V*M2O18ka4Cv}2Up1PB>bT>@I!YXJggz%0TtqW5(ae-3JJ&Yh&a5$ zr6>}PtB^O4@NjB=bV$IPGtg*Eg?Nqx>Fy{S8xm}zH*;)-OKK8KtdO6O;7w{YdAmj= zIKD!}OF-~2r`(Al!EAccQ!89jli>6U89eJ4<9d2VLxO1)f=_yT&sCu8)R3SPjXA5r zB{d1ou8_`e78t8gibgjZKczK7)2aWTH80bzGsh&N=svO-j#vKLfd5;C4f z#%n8F$|B=U6>>i^?!ha~TedUO$}20x6cT*T)%=E#z@X^cDqK>N;NA*(F*emyzONy{ zT@~UU5^UngtO^MRa%o>v;gZ^jzG2l=$VoW*;yfV2rL%uUArj{qW}I`}R?*9075;<3 zL}CmV^Whafh8|1f)Hc`~QQ@ycnT&G^$5a$^bVcFWp!MRMg^$EJl^%_AKCFv#P}j#f zG8@#=y11fn8R|Y3r*Su`rFBI`;S=C|F;4TmqL$V>Dhm0T_gCZW@#`w?IU5awL;WtK zzrnUmAP9Lb(ItpnozD^iO?pFbYi&h@hQYb)-JbG&z=it_f#=)4dBfz?9_ZK?q{Qg09_(f}Mlewo24 z(EuDkewo2)t^qiJ{4#^pLIZFB`DF&Hl?LF+@XHKV8x3GS@#zAqtp+eBVz#xdr`R7; z#p9P5tWSHE%mnQ5%M4cgN|!T@^Qmj4e2w#I1?O3LND$#{A+VbUF!Wav*j)n{$3+Ax zG*Dm^X6ptSR!D#YIdp=zf#Q~cvZ7YrBd@qa%U=Cc7W?p zwo;a0{0jFcLBC3MN)2O|dsK>EDDxhyM4R4~>XbU1>(E}6E~!bdU!@$0N^Y9OLp1>o zcdUeiD#aNjXvfQqeL{jWxMU8mbV5`fR(<|kEsH8MFEhG?_Ko9fOH6sK<&v$C2;B@vL2;7B3CC6)3;609Kcf`$Ya zREi%+5R_dM5*$NEd~u~qY7#81l!a|T5T&t}H6*yIQlwGlJw&1Z2nl-9ddn+aQj_48 zN;#YaSMLe@wuS^ZRElXN7{pW9O(B6#gWOT+l9~kfRmz1V7{Y$8X-KfDQru61p*1MG zHza6F4c1n=q$a`oO8F`Yn(^fDSVMw`E5$D)aM^`NLxPTJ>^xEFlA3ex`AS)o0>R8) zz&D07%jM*?tfwnQ24&uFEPFPbS>37X%atyvsll6-ay|*}=G1(m%}Lk0?rtlZA*unT zqm>r-l5sXq=5|^wJcS%ce3F{7$XJ+`FOji537TpGbx_CC;ztr(NEft8NN_9JiqbBr zIry#9vS&LG@Ow>GD!qN-8A|K73jr=X&rx)T5C|8Z(zG}jt-U{J^p9I~ zoL>f4?ja2s2c*RjWK6IZ14G6)J7Q;O+6|uE0^`WEoI%E8sN*4;Kn>OYX>lzHzT$j5 zFeKQ>`FL2`B{fwVo0boe;JUuR$2BAvofaRGU@p5cCL|cm-at;eYtji)li>Qa#|PuwLpb<1HY8Y{mYq@Ny+HEoLV`;; zBsZrMq~`3oEG>GWQUTQ{AQf5fPRo&Gt>BsPo`(IpJuS{4Ygs>(-5K_4Qg7_6PP?Qc z!6Rw!N)jxj=yeU%TAP*+lb|D4jfXhB-_#nQd6y$)8ZCv7Ep}>Qjztm zv}6dz9ncq*zfmpCa29-?7GI#u+p{;yz6{NMFm?Pc?UITFzounZ99{06!AicJz?J<` z(WnYnW}H24;vryGh0m!eoqkG-A!zMoI9R`gB97urwW?eSrwF&oyO1Idrk%a2`kCs^ z68#;88dwBEL%BO%YwlDwRIo&s>WNsuC1V5hYdL*A(#qLj=up zL=53!*CI#6m%RbBY$&2>l`O)H@=l z1JM1BW7Rn{7R>MN!PZ@JtmksZb!}+9wpHRn%Dt9TqJ5P*uhoLuDywoSj3RngdCyYB z2|W7JIbEB|d0(B=wXRg6reW81uaaL=#LXO_im+=3ab3w&B`BOCvQ^%0D0jQ_)Y&&= z;XHC7-3-LY`!YgmP1~(m_=T3ZsZoRbCXG zaNpuud_<0jn>hE5%n@-m=ibr=j0eqOp@^om(ot0j3TM{_SBbu;RKTtj zP#EPNUnOT#?yFo}PgE^=T)IPXP*@W~fOGyi9%qvpPK;x!#PyWB0M@dO3nxZT8f9{o zOJTgCJiSWt0>*ubQ|*kZ?GcK%3Cz?0zokWBmIhivYulPuC8C%>UJvSXYL&Vg97!|J zu5u}yy*RH*4nQS$1g&?0RvH)ETdB)M8oEiqBD@Kv#wHko+zop*GHK6pqtV(o%O5Q{YTpa2>i!HCKa@iy5eM^<>L%q|SeYa_X z{Gj7ER0)1c)SJ(~-V_onBEcP1E~zu}__=UCQG1-tN_M z2_~@Hl>=8%U4H}BEhA8=0nEUgc^p@101?g6JiBEy043h$k+6pbFyZLrSiLoX#p)`m zQl|kdR&R0j>aPJz$!9oU2510Nax-fT)Bu!56r#LZJPKLfLDX@#YIT{p4L!03RlDpn zZ8f4=zQdlipsfzrZYz$~kZNJU)$=~!XblTZa}HO*kr-~YBEb(P)@?~rm_U$(US6P|>k0b1}-@dpc(-R^uU_7N-{6xk}spIsJ z@iO*$PPI!})Ny{b>;R`->3IH*I$oefC>_tL76Vb)EAI`Gb3(=zJd!V}b}5UDmsQJC zP)X^ySQBU+mo(Jz(rU4UjPp2C7KV)dIccx1b}5Tzjq9uBTtM#4^j2=H-hR@*maT5q z08SDcSmPEA;3V-Jfm=0zlf+Rx-fq(XP7<3~<8}?;B=H`BJ2Zfk#5MwVY5*sRuL<0x z0h}a0=D@Gg0L}?t5x7SKI47741+CTq?jS@7+^2y!2F$jutrj<;pWgADFDt5*d$Nv; z-kNHcW}-3HRZEF;fg7QS4VnO_P@ll#8h|lM2|TF*^nDW#wx>0Kjtpi;p3y*2pu|Jf zVps5cU$gQfp%P0mw$^jiF4dzFo2tD->XmrCy3I_$!Hpu9GT+cZtAO#PYB`IHuff5x zUQyD#12}8ms!mWA89%7@9;#>Dq6yHgfN`q^;28w{{73`Jv3s{#en=5pc|vE*?=%4W24nhz2K1Qzr~#~@ zJ_q?H4PXszLEvW%;I7d11b)!~!fbaC_?HH7SLl8MziI%Uz&ZlIX}}4(_Ib7V5WVp3 z<{9YAaL~GA##n#gzznM^N&`4Kt|d^T0lF2o6{!(7V~D)IT=zwdS^+w6 zz7bMLSkm+EnqA6X-Laqf2Ej60-8IY&IVO`@A{SP1Z1 z?|H5rhiiZ$Ol$udv4A4FU}{7k5V0xD-wi<7(vX6j8~u_R%3h5P8O9AT{C@ z67-`H$A$!pdB7iAKN^ zqTaJ>WNY-xy@U8%O#r;uHdF>a~h^MH;RLZ?1RN@l$=c*c)>QRYnYh(#} zd|m>ofo*erCs4Y5+=%qC0WD26#l`v6&jt3-!DilzB}kb0e*AV~tB~ zDD#dQxiOGQrSH-Nkohhr+T9v}%th?@Dh)s;Pg~YK8bHT?=0v+!0~j!y##^lc4A|!c z?$ZDUY#_(@ehsJryQM~aPrXObJhz2<|IQAssd3pO>iuYqy399F*OkD)_O-Yp!K#jp!F6S(0b=-K1CASp)uzXDbz4xH4nrZ-g zzf0$~NCRpbc^NUCBBqlykx^&4cd^J@B^j5(DWXkAuB3=7Xxp}$03sIf2y3qaRK{x5 zA|swbWiOw{R;!S)fX8Nsj7wQ$EX&A`vFV=5Ik9U<5Qb7ZXG9F+?)BvK=n@iq#Z{_X z#w9fg(iu4cmE5HyuGShrrE7UKWi)_Z&mgde1~6Kyc#QYa07k2heeb6M@S_(M8F2}f z7)n$043*fG$KhTXm+Dc8eKYb_Dlwc#(-2LN9}o=8h?ht(iUfnTVL3*_GA^k}a7ad` zpq|@?N8jO^04g;jFe(J_s)$=kn$fxj=1Y>+IYI+U=>syNKj^&iJR}baWgf;O9mZxZG_{; zy_<}uYrqW5FeM}3AmdOno~)#K+i1r#G6~8eSK4K?|s80l6t=QN}yIUd-h=Vjg4bD?%Wm7%s_3 z1|__4?B#+`%orN|s!W31WV|-xJxs=cV1*{Y91BcweM7~s&d4ofe1ZqYH6h~#ypFyh zlb|dreo;pJjLiZnT0m}!xice=hRa$wjPGyUty%_4({r5tt2BVg-k+}SJsN-_d7MbA zLxArb4ci+hW?ca$F}I z-~bGC+Mofg(_HSRoV?rF6H#1^6 z2_|DoS#M{;uN08rgN#dR5`2=850hXXC(36HHQ1UFTS#yaSBsBB4Qy8YBIA;p1V3iH z5#V$WApWzSKrri1oQJZ_6)O!Mpj}@y;P!`30oe}S2vw(dqAUDM{t(CuG(>;t9E>bP|B^EYlQY%t>fi);A ztX1c!<~)U$)Vic1L7Q6H3zghrE_rQ3g7Epl7PVpw39g}9twMqgRI7chOKKAAS}V^W z!5AJj-5L^fsTIpf@DvHkLW29b#-M7lj0ebjHqA_$FUSu)J38HxLAO@wi^831FpiTH<;QU_sr4}1R{TsQ_Gj6hp%RzT5^HN+sz)W(*UFKD zpu`H!z{fNJlo-Ql@VEwGnp@cNNew`Wce((0N&`@0S2lTC14@a9YsDGh_dcS=kA_MN z;Q{n)txNT&#LKmEEtOz~Nb6Ni03|FA{3Z=RiSudw*EApkW4}-2%G=PpjM2?R& zpgR6`tvCe&z1P{NcSEf<&}5&~y406ieN`*BQL9B9;BPbmv^t8*?6(?#RwwY_`A!4S zsvVX1UIWnT4tiQYXaHKJxD@@U0j1UFwZhv6T8$&!m!VeYvf|IRF7>5WMlU%CmE1q* zq~O~uJXHlg(P8XoL<7*urc7G{YB+wa6(>=|`)vJtC}K7Hlh@0oaEkDH$;}jTRXOm4 zCP2rJW5p&KfQTv7v_J#s_`}q;Py^`rYAWGt03H7Vew5Wz1FGY)m&n@}S}}i+<@Qo1 zxdTa6)XSy5)T(7K*%p=DJ#f;q+Gqkhm}Sj+iM>cLisM-t5_I9A)wY*QY7&(7l1GxD zFBjWgLjnh7B`{>?UgBIb1chCC6<^7n@2PzEUhYyd@Vd?*-0W&>{DDs@vq3)P-jRbg zHS(=ZJ!Q-N^;=J`_w>^yTEzK6P)xn`w6$mOnq*wP=k!rezdLF)iSq@Y7ID6o(I(Ef z9@?vSp7yQ`UZCs{=Zg#-)w@mmE38wT?nelSHY?OCq$?`}eR{-)qei8Ah4d~ZAst@`tSbI0eyihr8oegY zN6Kr}OQj#HTD{_Y`epUU1d&L^pR$NBVgAN87PNjl)qsuxU~r32mi#`$>jfH2TF*Xq*r64vX_i+~Mjq z(__#?n;}16_GW12eR0m^pbD}@@ zx>oyTd4_RIoR2d+k|<@XeX4{0u1oCBy?v|wcIfYhI3Ekx80WqH7Zc;z_Gne_rNkue z9aHVMLcLewyjTBzocGr^$9YfugE;SFf0&rTTGv$j-Ep{WN%BtgBaxzW2(GOT%(o$u z?Gs3`F4_FQO8a) zFe&XMV}(&W8HC>KBqLcdyXZ{(v6^Rsf$;3)O6Hz>A~yb3R|i>_szn^ntZc9K`v&Fv&FYD?{+ zTUq$5Dr{jVd0E-gPV(Zgm7U}zUTeGPKGykX#?NB$Y-1;R)zcdU_|wNOTF=7fwSfj% z5bR|beeI&>iFT|FW=TK0=uPy&>ZB_5w~MxNw{xvO7^64<($HoWq~Xt*cF|0ph4xf+ zXWK>dx!b$eZ)zIGTsz5&hKuc@I67(#t_=)#iJjz?z@>IkGoptmsSE6)_S`+R*6$3x z7urdB`*+w$y6AV>NxIQ@*+sjt&KyN_x1FSKyvi=BA$o~I@3E8gZ|}8>`VswyLRZ^K zI<5EFNxF^q+etcZYwRRlrw8mL-J7*`lK#Ylc9JLXhwLOzvJcxyp4A?)i&|oItoFSE z6Fq7db>?n|Uh1f^iz>L=v6ugoz+q!2c_K4}kv|uI%3-zORn>b9!PAaSASl^Omw1Lq zvxGpCcRBTY^osDTg}dx6vhq~G___x^yU;3If9sj|JWH}-DayPHd!kA6th(pfln!E> zta~_0NYE)O*N}jpZP=w@`*vCJ9^3Cm-=ss>{!y*~U9&Ek*}i*L{=)VMM_N6?_Esw% z57w?((fRh^+jT?Ssz-9NAETL$e}vAPC|(F<6I(1lF$DIV$Ut zngkQFavxN3gS)~fY$pg_NIx;$&o2o~dURGyBB9M=?%0rU885XaW?hOx21d&&%F1W4 z9p}t2;v8N(&Ovh2*8{7v{!ko$u{aIiJ5KBMjnf7Llz($@*58cggOltRzF1D}Y<%mO z)Aem^2h(+eAt=Kp(4-@6GC3QeZsB+P!w>d1zYSxTZ|;Ytk@w|Nq_k*EfUQ5t-jxpY}a67fZph|wb7 zz8WP?o%tH7wd^5aqHF@|XBz`)E=yxgA=zmD3{MI{uS6>Dj0DqqXl#^rhXQ8laXj;s zehDN}8pm|CjfljlMRbmkvw4%w^^Lp4hqCd>=mS)$V&i?#L#uQ;wj-s#gU&9!4Tvb+ zh@}&~l2}SaMWiX3wf==`f#}&}9(LMXkM4?eEAkm_{sCKxs#es@G$MS$NmNG;!(RSm z6feU@Fo=0ZDvHA)ufi(01X$ZAK%Vz_eqOs3V9vWYKg!x4qNM$8U&%2)Wno{WH zc{Rb#ORz)U;&5jI1}*Q3yc#xYe-`_2rP_gRn2kn<6&QxRIeB?clIPfTuu~Rvvh5b` z-E8OWat75n)b@69so+}?uR}Z9YH=iQ&qL5Eu+!p5TefOH0UixX0+rieMME!+^riGv zi{98-76~kvI)OI3F5C%vwlWeAde-3{%*?#Wk-YKb4(KLFItAPT-Q-BMsyBoEbRv1P zQ7`p4Ef7_FMu*{u(Dwe%$+cH2Nza_eOOi__%k&tRVUe z-eXbR@Vnij!FRj!+QG-LtwFJMsF;7iVAS5HAkZF$aXy6a9K0Xw?CV%u|1hW8P7SD|LYEkN&@xD(Km0{3_vPlfJkwDsLhn5s?P&A^lH z7pPO@cEws-?DocQi8~dtnz^q)dUJO_)G2kJMx7S!h2U@H7GaoLyHDV^jr$poYquPl zw{?esznyz7MyI`dAMDV<9S6y*ImunYcSDnW^4jlb~9slp!&sT>|)sJ5;K+sxWJ5^ ziasqgV^>0@MQ9E^E;C~{L$%Az*b%VLVly@ZoL88!Q=r$CX6#rrzsijDLCx>X*hsK^ zZ^q^T{K1T+A@)Zzwg}))sEK)TkQJK@aIF>l0c6`Eu^H&^Cz05E80*tWYzW$Y7Ky!% zvd;mc<`D&0_T2q zY&H5Y1b-lQs2%$X5{B8a_RwXx9lHeP9AU@4ISlDB>{x%;i$SHPBGv{9CPmBw=QI(^hw{@!>>$|eR1sT* zx$w4#(KmfZ#Nv?fu82L4!Ff-_+M)UTBDMqrwpqj`;Lisl_5}L3F+a914vrV|V;_O# zrTo}t)OzLp+2G+p|IJ? zMC>WlJjaiH3$vc<$F4*3CY@qeqelguVp&KysW>(p%1uRn_3)u6E#mRjy($VoKhTn4Mv_;9BW5o6~`V#k4`O)9RejzD~@e|^wW!D5|*D) z92^UUJd3bgCJB=#mO(Pv4FC;04=*heVqyCfC|OTQ(t zCaBVXNo*xp_F5AA2bvFAA2ZSEq3dHSF>OYF8aofhI^xsVQW$y6r?F2_<;YKCH=yrh zKaF`1d(@|~(=lzveH!ZyaQvs4f2WHXb)>l;>Ojmz+`T`j22V4u>ozS za-%Pfx0AW?J>;FjjW=P@Y24Tygwwe(0z9X3;~{8x8aL*{LZ@?MHq@KJjS{pvgBxc; z)=X}cL5*3#26{QG3dk79I+GhQjNNQ*+y&-2+_(dZ&E>}TXf=-;mqPkk+(@A7XLBQh z=9i4Z#ylXGa$^CEx_}$wVdRC}=mN_u;>P<_{zzX_VE3_^<= zTQE@~+?WZ(=EhcR2yPsN36jT+CFo#2H|E0#4mVCgFC;fk#-K*Iu|GCkZd9Ohj2pus z)Z@l7w2E`%I+!lOjV2g^Cfw+b0WaW2TgWQpMk)01xgnu^Q*IoO?j*U<3q{o0`<@;z zH(r1Zk!#8DZh-U%H;zOHZEmDTvlrOt3!!=3mxG;N8DNwL-c}Q3q;I$A&QMUsz!}xb1^F z5)UeL)fMXKnxn$U15n}6j>MaO0@cJWdDF2STv*$ydu{_s@(9cbd-a}^z?+ooxjihv zpJFdpAH{8>XdxQgi}EgIV}Wt87qxkl1;zhDuk4dto|128;TY(aQVf^pNHN~8st%yhGHgc{3hCYU+IZdHITXmf|g z&dax_5UexT;7`83^lf!Nzvcw~niKeIPT;ROfxqSi{+bi`Yfj*=If1|C1pb;6 z_-jt!uQ`Fg<^=wl6ZmUR;IBD>zvcw~niKeIPT;ROfxqSi{+bi`Yfj*=If1|C1pb;6 z_-jt!uQ`Fg<^=wl6ZmUR;IBD>zvcw~niKeIPT;ROfxjk|zb2KxCY8S?mA@vHzb2Kx zCNIX|USdk+uSw;vN#(Ce<*!NQuSw;vN#(Ce<*&(O(fle?Dt}EXe@)H-_=72xzb2Kx zCY8S?mA@vHzb2KxCY8S?hoIeO5vlw&sr)r*0sJx|mA@vHzb2KxCY8S?mA@vHzb2Kx zCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S? zmA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCY8S?mA@vHzb2KxCLe-bHswp@ zuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;v zN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce<*!NQuSw;vN#(Ce z<*!NQugN!Ii9SoD^4FyD*QD~-r1ICK^4FyD*QD~-r1ICK^4FyD*QD~-r1ICK^4FyD z*QD~-qS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvgEvo&ssP@;Q+Fy%me=Vy0 zwW#*jqS{}Jmf_?@e=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q+Fy%me=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q+Fy%me=Vy0wW#*jqS{}JYJV-N{k5p}*P_~Ai)w!@s{OU7_Sd4?UyEvg zEvo&ssP@;Q_5PYmf6aowcAbF}{apN9gcF*_lN%D0&BV4%ASk&}moUK(O9%u%v3{t} zd@e!5gkdwmOKc{+k*S5QL6K&p zFeUONq)1k7nhG9pD44*VmMNElkWDbsDJB0vrNmLxYnN0D@WB5`7>RKNx@aJ7Brb$& z80o43&q#bjnPnP?8HxJ|lxx5>5}OF@rU7XrCXu6?1{@;RfOUJY z?-d#lM&cuK^w5B9BsNk?PYpzj#2IW-sR0Z~mQAWOKzqW!zA5!q9IZ2vKtBz@I#*MP{u+RFPNSjs(g3Wph`<01z&bCJ zW1!Xw)|tZ^gERo^Od&8>1F+83w9Y;nfOT#s$G#eXb@nH)p9Wx^Hwg^U0IbuCnhw_7dvNE(luNte z26|*#N}h`Ai^QH(^VC%REzU%OjHhX!m62#h;B*bNG!pFy%+Np!7=yqW8YndqX#z7f z(A-G$Auvk=%`g!t_Dl_w7>PlwF1gV4o(3>mrg4#8S+Rf;7ucP6ao(3&v9V zl9bDd#p$y=CEwxnxsLdCnxM6j_?aSBY5>z`Z>o8N23iIpmZpT2fQUl2UKWbjpF20F zTngtI?e3J^4V4lYn(%D)XAXm1wtWY*0rVQz=W0jg4W z6VLQx_rR2YH!Afoi%HzuEMZEA$V62sYnCvZLu69QZwYaI&0;QX*Ov69`Iv z*Coi^_a#dR1SKWtQqZOd(GyyefO{Zk$Y-et$F1SR0r`{0BhD4vMz_o2D^S^Sff&x) zXkt3Wm^qenFlVJR3%KpH#c!T-Gmv~|BI-EKT-1?H1~Vt>EX1$t3`d=qvj}xOrxZxS zh%81WyEf7b0wS9M*?kJuV!N5W4!_Nx!%r!N8?ig^`wspGok$oho&bv|D`bt978;82 zc})=TYV{4bj|uK;w{COHq=|-@P!cd0sfQp-?C&zjRE?@_gVOzXWof$}L0N{fjrOa_ zk?~Z8%xM_4M1OFo6(FfO?#YX7@%TH|p^#L4m45PtsMZPbQil6NO0T8Eg; zaam~O&&E%rgKs>H)zCI(Z`W%i79Z-h30?Ykdi|e<`Iemym8}WvZ@0LIneO~P4?E6X zr*JwwbR2N!C2U8Wt@yQ_pYSUjcN!;^K(l3XEuJDIBOBMZR1>a0&bx?$zw6-&bMeXM$K|3dm2_1XW-Fz+SiEysdAP=!)oU(7(3(qir-r2 z0%+CSS%$WKoHh8(I(=psMxE0g+kKru`0eN1IUV<#oH1bD%h@>9Fa|iwAaQT!i{tUE zu9F8n2RS!G&%w^FK=yI=!tcJ$0E=pjCH!eGDkT#%)#9)XAz`~clLqiM>~H&`Y}!#__2-$iN`sW=*t9W05m_| zx$Z1H(d%r1!s zgzc-Gf1&0Q=ODDb+PMq-OPwDkVL5ev#rDn4Mre48(-PxytJD8PJgn%9!tY(qH2mJ} zT!Ppz~-$$MEFhkZkEAYGC zc@V!FoK5(B%-INr$DJzZ{DkvQAWu4Zkp7g@3BOM}Yr*r3^D2Iyb-u*!b58!*xJ~ao z0xP}XOupCnd9#y*{vSA_VaYAdw~)Kl`55E%kz>HZ zA3IG^bDL9+-%p&=!ThPS3giBna~wwGbLVrk`oi%rSHE<+qwPPPLHPa38H?Yqof-K3 z#&MwMx6V-fe&;*^iQhY2(dq~1C20GjGa7Awa;D?=XJ;R1@{6+s+y8Pd#C-eJnT4MI z=4^wk-<{vk_7B+#^U5&gdi*g>*$MOAGG%Z4iI{RE{@AAUF%g6*Q((w5<<)0k`7q_f z_#;jEDGto2DI?f(P1yo}Vy3(dv(7W+%b4_WQx;*I6Q*2*ngyo37k>&(*#tx3n{pTY zX^J2_{v=I#2>ukAatX{*Y|1+Hr^J+pVge2^2bn3qf%I{ZfW7giJOEZd+LR~Y&oQWpS$M1|&*Y(I$_d~+(Ugy&V>3+oHvXIe z2{?#mnzAiw&NAhXFu|Fod=-6|jgDdX=a_ObRGJH8q4_*h4#!+M%aq@O^K4UYK!bCj z1e%{~$|(A9zA0bA5L{r&BQOsxH03n(;UZHuMe|Ed`3B@IFy&~dyAWnYgGHuXgPND2 z3dk0lavP*yVanIg;7U`@#vj~S*a{_5c_ zc^>3FVamIq#FM7n8=AEz9D8qu?M!bfY2FGOnx0pP z-M7P*rbjp1ekW{ddbhdQeK%}tdGzD$_rkW8*Mn`}58EQmAWJugZLRp;Lxvgl2WH_w z>KpOs-rFCVh5KRmE8F{-yIagctPMDLjRgO)XHBlg212Opasn1Ms<(sua=k&i0#^Db z-aBGpP;0bC>ntPMrUcwuO`A@90@gNWXb#g5$79@zqla)ZOL4uZqe(D7uTQWzXgGB_*{9H!l9 z9R!CbV&U-_92PmjVV}WakrN#D85|Zz=m@K4_zVt1!N2oB%T1lD12SmXqUeFld`PH@;~a9HF7hy8X0a)QG? zgTo>xIP5bxEOLUwK7+#|CphdgI4p94!#;z@zqla)QG? zgTo>xIP7mDkP{sC85|Zl!C{}lVUZIY_8A-&Il*C{!C{dT9QGL;7CFITpTS{~6CCy# z92PmjVV}WakrN#D85|Zl!C}8M#pVQueFld`PH@;~a9HF7hkXWzMNV+oXK+~L1c!YF zheb|s*k^E905FCCLGb731un2?0Nd|`ng2S9xoIcA_(l5aDVQ^UF z1c!YFheb|s*k^E9R-bv`#WOES9O@aFW4cf#5KO^Nfbz@KF@O;IPOE4*LuM zi`?Ka&L#*B&nIJ076ylt3=RtfhbfCI!iJPwNk#^TMQ(5y2MvP5&yaw@VG#z0lMD_E z1cyn@UL!dCBMBHB7CFJ;A_Rv;Zg9A18-d_(3;0Y)28RWL!}I`>3=Rtfhgo7ID6kA$ zp<@66@2BK30DK0AMNV)y5Relb_8A-&xxwM$S*Ad6_#%pAa9AKXyp%f(4hsZ_gE(2> zix3V(A~?+Y3F@$FJLt}`g_)Akrnpq1PhrFu92N);w+7Ut8Bh9#=`lDg>Vw09uPN$- z!+~=t5FD;X6WeUYvv?aba4M0%D~KSsH3KhFAUOO8+>Q2TGoH-4nSu8x>Vv}`&vpXA z;m1&^huMs4dT-NXa9Gp_hdl;|1%kuFA+E34j7!@!W;0IF6{g4Fut0ElB^Yinn{ie> zVtNb?i~8WO$KbH24-R__4hsZ_k3cUsn9VqE49jD1SkwoHJqCvbg2Q{El5I8P+?Zu~ z3=Rtfhs%LpV>RP|A~+m)Z_Q~yINR98z#=2tXvM*e-Cc7n7931IDha&0B32SmEm8DYY}|*E4&-n5|_%hn3)w%qIL4O zlTdc1dOI$8A1>I$xmouplu*PaS(%rFh#!vyzCaVSHvB&bEYtu*i?c3;Q^eA&+>0XK!v&;R782Mk0v)f)iU}lW#$Bok5-dIjWjBTdMclbP>ynxT_h#i&B>0qS-q(=euB`Zy z1i#Qqt3rZ%Xr(n-m((O!mzB{X5WJ6zL$M(wXoBeoGe49SyP+)k^zkTrBqVs1BldXK zB{d12%gR9{*v2lr&`^V?vf?BXJjp?QCM39&Y%gYAQj_5ItUR9t^QHrTGbC_unFI}9 z$%;Eku$65#g#_+Y?7W?INlk(ev+_9-e9NV9YeNm*%ZhJE@D(-K91=XsQTRCPl9~ix zX61dwAXt1d@UJyN0&YB8eX9XDT3@o0-)SIb_zzRD?=|2W{sh|bM-Ai~{u{V@6hCPo z&+tE{0e{heZTN4K^j{i?82&DtpucLsGW<#^{F??$!;jKdziR-!fUQ2wig(b99V#CkQ1rXOjk>Ss0-xC^08va@AND~b-HT<7u11Qjdj~AUtTBw0S!;f?J`Wh$* zx@y&lC((v@&B=qI<;~?~?b4g8t+B$hX35Ib}?V)X;mWQf3@hl1U=Wy4A1W$1W_pWnEO@h7Z z;64ccR522alVI=4m5=0SK6NBnpQj=gro!kYL{C%j|0U<$naPC(p_9ek5 z(@-`vBp5pnI|tRdq$a`WI(aM!&LY8>h8i4FCoUqvCeDh(LV~+F@5a`-q$a_HI(ah* z4kms=Lk*6u6B|j;mt8nEBzR^Hb|%)jq$a`iI{7&X4xI)3w1yf?trG>MAh5V9o)Qx5 z$%-@TTvC%@UY#sQCI5oyz|U?-aAuttMuJ|PNOMAh15d-w{5qG^hHK}E8CiK$3wS3y z<%QnKd0GDjiIZaq&rwZEcp7OM3tW`zvi>rZl$7wy(5-~adym-EHlSRa^=G4`s)Q?c z?-DM%eM`7@4k+OQIJktX*pLz);3Hy;mWkpze+gO~RKg?Sq!Lc&DJ7hf(_)O5iOM?v zR48_OGfp$ZY{toAhknjJb^h;Y>zK_r1G<^bIF3C+cV}FkzYqTi$#!3cIx=-s)Nmetuov zE!b}TBIa!V0r6n_QIO@2Yql16n~U(1I>yK!>0=o-+O{6J0cD35aVIqfLFxQa!8U3x z4Qq}MY8q|XYNFa!!A0@~x>!a#8_O-i{=HxqV;KCb@YeF|voVb=+@CudeKqqW2Hvv7 z_2`ua2g0KP#GUx_mu}(WNHgpM@FU>RVM)M`W#tdYsOz_RFJuiY3Ap%Wp`HJcNfG&* z@h7jrd%gMRqQV;dcb4M^LwXbb*aU)-S9A&DpD+;OmMp;~j`5`~L7R73LLg}4KuExb zc<4_oA@CP|f}HVuSxBqWlkEruw0QMQl^}|_A4>=XCDV0@jo1iF2m~bybO}7R% zl-#OI^5Ge>gn$gv(Qm<4^slC)ml)K>)6uU64L)DPbo4!JtU)>*Jx8QLI(h{lVZ~xB z5KKp}03@u?>F5=Zla5{iNLXF5=Zla5{iIqB#XkduyH0XgaD6@bJKvs!V|R)(F+Nk^}0F5=Zla5{i_;%YHZNPza^a{YY+jKg51>oClizo%@=oNr( zx9N2B3c$D97UiP`($OmbUq1dK0s!gg6@afZ>vZ%Az?{HGT#$}_q>cHc)6ui6J{>)0 z8s`(z(Z7XC_37vXg4}fU3c%3obo2_yNk^}M0wbEOQ|agx;2BY!j$Q%6i0X9o3c!?x znn*`)2x#_0C-e#F=vn3+*%LcRN6!x6hOC8j^es>+x|4MDeMrz~I(kx*0O{xt!{*M? z(a$D9qv_~L%|jXK=pP}$-%dxrl_DBVM^E9@5$Wj7Jc!`O$QnsU-w|bvr=uq|36PF{ zI0@_u5d4L7^wY@LXgYezA|uk#FC^orZeaX#I{N!b(5nl|c1%Z4Y7!tF{i`I{Njmyp zNYH3HdQy`B>FA3v{dbm*K7+Ex)6tWf1V~4JAPKJC6KeiB9sTJf7*vO{9n;a1ngmEk zznBC=*v~(wqkoVDLu*jBV>)_LlK|=H-yp$G($W7;0(TD(?3j+8)SP=rM<3ju-AOw7 zJ>kJLo{pZ>)Bx$|FGQvPU^@D{DYMaZ^wfqjk&gar$~?aldiHnH(HFr5X*?Z0g;NC5 z(bu8UUrtAVG#MLBM^9N~L^}FKWc;h?=+}^Oc3<>x$8_|RMMk8f-$cfpq@({A2^vjD zPihW6($QB(LGZWJ(I1Z1ji;lhaO#M3^ruq9PSVjYB|)R<=t)fiq@(|m1pm2o^gevr z#?#SL8_GmF`rfGYm($T7MaD+c(Nh)~k&gaMGVUZD{YnyiRgJOUF&#arNq}_p>qxMZ zbo3vSU~U!!JEo&2H3^W8K7y;fou#AijIzel(UY14NJrn71UpGbe+&s4O-D~^5+EJ@ zJQ7@72{r$mj{YVRG@6c{)FePU`o~GIlXUc-k)Y9Z^rR*M($VMR+GS_y=*v*ncshDg z^Q+@XN8bmP;#4C}DzYLS{b6L?Njm!3WG(B5KJS>0o>U}2I{K?gu#

    q*dPI(kx* z0O{!8Bf(D6(c8Fx(0Dp}QnO!3N8b#U;#4C}DzYLSeNTWpOGke&S^wbKZO3%FA%u=FZa5e~mJ4&)!gL$8_|hA_3CT z^AY;LpN^idQ#78Ap28^t>F6(|h`*hVelv~D~dJ%!VHNJoD>D#h8AIE7Iz($U{cxtVfw?eC3GanvR~r zctweH^q)|KPDdYH>zO*AInvQ901*nEj$Q!>d*Nyj>FDD=MD(E7h;;NU^K?3T3TH2n zj(#vI{rzF9TXN{y$ZXOE~i($V*$-aAQ0e=G?a zO-D~^4jF5=Zla5{i2r%h%^a?! z9lZi_($Omb0j9RyFlyWJEgpYsk2hbo7srpwV>nq$UB< z(etk5Urt9~jGG^gr=zDVG9n#)1uE?<9sNNhXfz!?sY!rz^ixQ%lXUb~kie~i1$RtG zPihh%9sT1Z_^avYKO^J$yMS@Wbo7+P>pi5SzXoyG|KFvfe+)`Do{pY>`^z+H$9830H} zuYjC%^a{X9;;1UrKstH_;3T2b(JKHa37w8!0XgaD6@Zh3PDihRoOJXG$Vo@9fSh#n z3ec&`k&a#gxM+ZTf^_t^qM!BY=vn5i<0U=P(bG&kg(4ljhkJ4L>F5;!jN#X!BGS<- z0LIYi=oNsz>vZ%AKt~4CTu4W+04#e@0_o_xgTFoY8Ff1PfKjKTrz|oe9sRm`#x0saGj7#@P7D8$29#rmbo3ungic2v zh|uZiDV%yB9X;>O#;JLn!YCK%=+}XxJ{^6-o**5)0<>JDqgMdztJBddK#wWX(JKIF zah;A{0XgaD6_AsTUIDl(q|?zWASWHY0&>#PD*(YtbPeg~KSnR=)6uic)9L8hX?7Lq z=;z~ZP<=XjMF11)bo2^9S9Lmi1)!_T$}mxoj$Q#d>F5=Jx%CXEDbmp^0LPV1N3Q@J zS2`WN0&>#PD*)3`r=wRuPC9x8~foS3piWdIjX9qgOyqI(h}jGGPCEL_DWcJI^b}4JNJoD+ zMO1c%h(D*Jf1L!4rlTh{36PHdxD+RRcM$x~q@%wWDm9*to;{-8NJrnUE%d%)SLppe zla77>RBAjOJ$ppGk&gZb>iu6#NBF9r^-i@ZCXOE~i($Sya9=7`5N=JVuRBAjOJ$ppGk&eEg1N8nc zrlYR}f8*)ssUDR;I{JB3;y;&;{wB(7G#x#)p-iNs@6{19PhbG+ejDGJRLo$Nq}_pC!x}RGadaRDlxPgz1T4wJ=LQU zNJoDsmDou-`b{KgG#x#uNq}_p9dLd4A52F-5Oj^Fqo+2MiFEYiD03(2=+7fTqv_~L zO#-B&zmEiiXqvx}j{Y4oHkyu}vdD;Z^ilX|e>olfZm8UNI(o`t>>ugq`=U~uipI%J zF-S*0v0ltyNJoDe#f)PwcT7i5ZZaYr{dzL~)pYdR$oK>gj2+X_Qx+9RI{M$R8KCfrtJ3yS*p*M`TV>)_jOP!F8z7HzxEFJwg5*%9rf*sS*lbQrbM?aecJ4r`>Jqadf zL9k;wdQy`B>F9Y;xwCZi+epx8I(kx*0O{yi{+~!kAKft>eYEj(^fMr@@pSZ5mr5ZW z{Y_Nruco7afsD&*VW%C_(Nh+uInvQ@!DgI&jgy;VkdEHK<;2d?(RV;uoR0o_5;U5Qp422jI{Nh_xDH22BkAb3 zk>F^0;5(+HCp8I>j^5r41UpGbzYEG5Pe)H`5+EIYKN4KQAmX3X(H~2KM$^%gngmEk ze>n+$hJW!_($TLa<0y>4pVHA&78#L_p7*`}emeTrh&MN$j-J9P0_o@(l-^l7`q3n4 zG#x#uNq}_p7m(nurlY@$jPp6lJEo(jEHWY;{qtnpNjmy(NziCIdQy`B>F9@J9{xAe z(N6<^ZARYZ9 zR3eK-@o%N0-%1gUrlY5Dia_c6`?l#ZUlDFW%}w^GDaT-^ST($Pop+<)Wg=&3KYLOS}6 zsI;?m^n*yyXgYdQlK|=H$CKbs>F5)9?+NMXFCc?XM}IYUzUQ;qNJqb%47{#02sc@d zjX&^NC^pEa+*LVf0X}Dmbo42B0flG9&>rdNyW#e|;q!%{SRr2wv~)W9!l`YrhjjE^ zQP$-DvG?9#QWWdkaCcYt%+&Pk%x=%@?kv08yF=b3NZbrA2!eh(*9XS@ej%}6n}7*@$^H2^=Xuw?dSt?95`k>`YZ$H8v-&MIA%NgEMwrCvJ7Nz z&N3RkCCiZVwt&P3j@gbr%aHGpSw>}Von<6-dzR79qXIG@IA%NgfXoLDwxd52wvEX$ zym@?<5y%q)k{~!{JNhhxiYEqSLU7D>^Z^+V9J3vLmLb5C1JWQkW;^;UgLrq!G7@*^ zfK&($wxjP2&+ZZ|X3lI!pJk}+{#nM$P7f}lMP@tt;1brucJz1z85~9hqey-oh+H(T>V8YU}7MBe0GM z=CXy^jy^b=Ic!H?fSrr744_&PnCPB`eU^b0R|jT0`U$Y>nk-`_t_#d|^gqC^ z>$41hxH;HjJNjVTtzj#+qdx(yZp|{BVM9<^2h40oADHdvt59QOmSF)eXZdaam0*kQ z=mWDIeL3pAmgTql53>Be{$ZBi#5ZU89s8reY)9XK)9vFNzeH~krDi*Nx^JV%@ssS+ zBFB%A&x;(tD84L8&35$o`6;%e&++5i2cmR#J50rP^lzc%$D;K6dSpAcqt9h(xgC9O zJ`ym;-HpU{bNq_oxH*0l5N?j|*j+crx7?naQ`*h(jZwzU@x4#6o8z0861Vg$R_)l1KF8N7S-12O zq8;1O=lH^-%+2w=LAjgbQ+VDjy_$78wxiGS3A-C+P=8P=W3zh}c5FwV<6~vDo8!Y_ z=;ru{SL2r6$2!=K{x0~g*3I#$ryT+Y;&gXQA7^35cJw(umyB^sUnJVG9ewHBqmb>` zj=t1vM?V>(I3C*2<|JrCve+#>kyoLP?dVIFGK=l#i=g~eH^+yDbKTM{x1-PTN#K09 zbj$7NOMCJO7TeKZil!I3Io|Ex>E?KgzQ)b*Hu^5Nbj$7NbG$dc$1UA*JNg{&Z`Zk{ zTW&|6<4x;*ZjQH&>)jl0-0pXCymflO&GGi;K{vX9<%kAh(hi(Jgu^s(P*uK%t@j`}QxT)Wu4u;p%Z(Xq+Juf>h0adcSDZzI1tt=r> zwu$E`wxj1&YfB>O^3Gpai@NmXsGL{7u+FPrSm#$`$~t-d3u|%M8JO@*;xJT-Plqx0 z;y_s;EcXT+SM0k43I}G1$LFBJKRYXUPvf{-EhM;u%ZXPG;PI?jdIT(P(c~4rXR-Y$z*DV1u#4J1dRXm8$nbf%m>$ISIAG19gT}(3rVB(B6C0u3@gW zCl)d9aXY1oz`6=?Ru(I0^h@hB77zZ?dgLMK^Z)Qm>;D6Zw==9_4`}%RO5*(^G}@=` zvNM{-%9i4I`R?lYQ{w0Ctd0fowR@=JRvtgJw>rLzbso|9Z9INdA8+9C1rL zZ{hL#>ew1}Al*Ez)6F}ar`!{>R_4 z|99)bUVB>Lpe`Lx4(k7IJ&3KM|GV{I{J&cd{&(v^>%UtMS|HQ@|HsyYU|jis*?JJX z3@hTeTypEd)NEWXAIE{(U!462jni|yrwgK?F0V)A(w}U1AFaY)hJLYo8_|pK` z6Kwr*0Dnh-gZ;erycB@tX|)cv?;6WYL+jp&54Ztx#F|_OewZZ_{zRO9Yh8F>z z;Ded?&XwFkFSwh%_`y}YY{3OrA(QYj+-RGdMU{IM51>*;^}WLD&pT+f^`Po|H?RL} z1*D_CSDG3{QQxZ#;75HA4UmlbUSj}k2&Vd8hyVwhd8xj4HvsnTQho1XnqcoP)%TtT zfH5VG$a`hu!SuRqAa6U6JuhxE)iL@4iHd*Ml9ga_p?beYb{q z6^A8F$A@|S@Yct&ZS1?HIzHU%H$efhsN)T$h8K0b$p9kic(Vb}3pMC12EZ+Si7f_t zr58bAFyJ=WGsx>hg~63qBGcwo(o#HOi#o65F;vR(<(%jj8J#_{7P}Q&5_GG{;}-F1W(i=<4(dKICytYF2Yg9TZXbd zJ-t;Y986#A?0KtE7WC!Gv8$(c#SE@oiOk-fzaL7h^3!dxqo;n%u19c+7yOe2c?vzv zwo((2c@@VMXog)QERV0-Tq6F*xS1DIJwYArd-#KiKHZZE%!KUsJh^6iInEhW9f?Ot zaeybjVO3U8a_ezmmYHrib_u9IYOUGM6oa~{nI#0&`ZU9o;Dp|pB?MHP<4p-jo#wKH zfGWAflz`Of43-d3C2LFxNS#)*gaAfwLS514IMU0}#5%olfM8Rf#XA@P{lhHTwoVom z!PjG#p{L{P^fGWEeLblz^8m!qJGrSO#7tu$KX_alu;z_BH_a z1$>{tJ_f+PfS(YUY5?pD_yvJ!2Ee-T9f5rffOX+N1okrkHVXWc!2SlnSt)qdOg8}d z-WtyVFv9@YC~zc!nFhexGM2yr1_1l)L;|x6fYWqm0<#T(#bz%82O5C>bHvVdMLWPX zfm$JVts`x<6@0i96%VS*(zEp6VRa=3X5haWT&d?90o+%Sz!3(3|K<`{U;y|pe+hsi z4FLbmXN`phfd7snaFhYyzeNO&HURuLjxvrh0Q|R@HI6j^{5O#`jxzxK_uUl$78wBk z`wxNR4FLcBN#Fznz<+{g`H2RA|0IEv3;_RS2rM>$_TQYkqUCT+H+Ait7y0k}3JGV{Nxv8aHj%S`SzRS72TQr!omZEkY>wV#btSz^An{$E6<5@$ONF`!ZYFT0 z0Wf->6If{gjNaD-t}*~d??(cw41m%5jlgOHVDv0%zuEv8y%>RO41m!~5xCX>7`=eN zbq2ubt>gG!Zvc$mLj-Ox07h>kfg25g(YuLbbCUrude5=O%?7~e{e!?Q2B7~OadBPI z_Ha$0e0ynK4X>iXB6jK4x-30Q|J_|zG7H}eG6&PiYmETR{=*2YGXVUzkifkLfd3W| zxX%Fa-^m2l8vy=WLg0P_z<*~Gc)$Sg--QGoGywc}8G(lk0ROEb@UQ{kzlWCtc*Fqk z-(NhTHy8l^dxA9{H30lKiPx&f3;_S_O5kw=z<>J?*k}OlzdP!RmcccFx~o_d`LB+$ zpQy{yvz*Zv*2$|;DaT1@<>*Q^`_HKJ?!|E_XL~87uL)=q|8G5&g}n-b(O3f;GL*OF=VD#=K@Ua0fdJhr!!~ht*#|eCD0F2%<1U@qW zM(-s8pBn(9cP0nxUk1SFolD@~2EgcDLf{JnVDwfJ_|gCvz3T{kWdMv`Etk8m4M6`n z;;p)(?Q(FL^6fiyHEQj@kJqMe>az4K{r7WS$;?vt?;jlgUyK0E{(lnq)d29{CIY`1 z0RH=!!0!ft|Nc$j4+Fq|-xB!K0Px?>1pYDr{PzcezYPHYIqZm4AB`jYmmpvp0R9`p zrNA)&{I@*;VF37VCjzbk;J-Zycm{y~_9GB80Q@(bK->V@f8W;?oe9?jYO?+q`ESrU zsFE&Fo_Uj9yRH=xYFsUOj<217P$95vVr+Mz4WDKLcR& z&Sww$8vvuXg1`U+VDwfI7-#^D-VFq{G5|*Jb^?P8fYDn^V6Xw`KSxy67mb5!0_EGV zUf=oTc_|uFpQUH%zvlXq>3R51-UhtY2*B*m5NI<1{8vg~gaP2cN&+Jd0RI&TY;6Ge zuMdHC1HgY5aqSvq0Qj$wHAWi%{u@DH8w0?9+YlII0Qj$(w?bnL0RQzQu&n{$zkUS9 z836tpLSVcB;J;=9+Zh1x<5SYXUV{8zcW6dlo8gU!SFCIitJP%ay2< z<0Q0lbfud8MfKj@I4imZYB_}OSTESL za)S_i*DFr)U^Xg=sr9uL_--AvaRjH;*Z$jwl+@n%OISVbq%D_3NsY%!G``JiiDw%DM&daJ&=Sw6_lBZ!@HRe?i!&pMzf<+O^*(h`;);5?BPIS_1N`zx zfD=pF*83D~rTdD5>*aem%+Ytzn~9_AgRN3{^^jxlg?{iq ztv;B53T}?}d;0PJ{QB&Hs29sJ5=UH6uQsGk=afDAq4ui!@GI0Wwo;|2!b3HtJ|2N_ z?Eg+%R@DnyiSu^TaM`~SwMh&tJ{(@9uln%Li(^o4vjJcRR)V*Ods9$3=sz4~?+(wa z>)_VRd^Ftu8v;3#K@7a88r~r>u=skoT5i>Av@dW|FTODVHcKZlumCYIZ%16a+RBg^ zSbS%ID(vY_;Clm9S{V`p3lIbACU~z#Vqo#30q|ap#K7Vw1LUpDV+4LSKsjzK2>izY zWme`&j^i%|D77+MhX8&v0N%}wBk+d-vQ}nC0)H6*FY9(EU^PUB;bq-#1RMk4v1C29 zxCX$=crZxH}7u$F<9k;K3vZvd=}BnB2B2G%vOGLjfrR2cy0JBfh>h=Fwt ztc)ZE79a-J0Or$A1iBjlBaSOGh=EsQsstnk7XKcuHd_exP9oE@!RJild;&3W4>%@s zE$7*QNC1d|GglGV$^aO85(A6D2EaI8L|~`^O0441+iY)%;Re9VOA-T%Mg!ob9*KcP zvjJ>nCWwK@!-9aszyid;>{CEuU;$!ac7Tflh=FIKQZb2v#n=YD6bcHk#mENlObQ?| zuxM}4E8ort+7RO!e2S(35CdO_!%QOuPcZ^KC1Cpo?^y~UF|gPn5^zE*GCMc;6wOl^ z#K4If2p}=AnA)IEWxNs2T-^j<-w3cVYe>s0_K$!VS7*HXY48T1bwFZZv1fxmw~wqt zW_E*5<+KsRz}ry;iGjsok&V&Iyn`FOc@%JJJ<8@pHvWUQ%x~~1ngT!!d^rUu3%U>k zXCB!K6_1Z3!Xmou$Odl%C6X9e92H6I*%z4;8hq-aL=XeNONk@~7F~&fA>iZ&&#r|4 z5(A5f7&w?c5}Bn9K1EXih=Hq7DMRvKalw{-THfG|rT|rTPGrGBqfznF2H!>r1%McM z8V)l_I&1Zo0xoaxPC;4lFqK{z2^dcAUDM!GGzEYd_$mrmxi#>v#K7pnjSb#L3Lr7C zh=_rMEFE%ZgHO>E0Ak<|D1gMkqAM{l1l-erT`VDh#K0mV1`fK@f(ILXilzV%0~b&! zLtka3@l!bW|r@%ne}V~HlBlk zKUwyCG_!`#)K?pPilzl127ZGA?&j2dx1rkv!0J8xi*(8d2Ef`goWN!SV5vERC(K6% zu+`Lgqrv-~I$vVte>Rj+T(CdSo=+NlT0@;625#;Sog@YpU5J4*ak}Tb$PGA$Gl#I{ z_r@=14afeg!JCHG!S~H5`@+n3PNE+gd@8335Cboxif?!x{1FLo(ThGj&Hma_;?E7< zos>voVDU>NaZh^f?*^Z`C=tZK?@=O&fkmRR<9&K2q#Ke3&^9`ap3?&oPv*ruA_fiu z4y51cQx_$I7&t_w42gk7&IrJQj!vc zLSyH`Glkyo5dmCyUZCn;5fCjrm5tu@RPi^RUfrk{o<*aO>C@;_Ic)?n@MBa#Vqh_7 zOB?GOz0W9s#K59|WaBZkaY&<2(G&n;;D(+MKw@Cg)+r!!BTX6^0S+#9hjXmAHZ?F* zPg2xq13(=7($MJb4ROJb>|s-+^FO1J*{0E_HPi`W;3d@AM(0h61PG|Wo@bVryrsnP zjoxjPNMc|yA(HrZZ)B!4`qV{=tiHSDFDR4XHfu&fyLr21svDtt)T!C1B>G$0so*mr#Jc( zO#vVVet`l=3@o}51H*!4jo$YZKw@CAJQ8pyNBDw9pQ0%M#K39zHA7-xv9hsdEMObM z!Y*9eD2JjfAThAGOj{RB;G|pCn4xG205R~66tFi3|E4VkT+=8QP{2zReqAKsJPye% zjTwrj77zoUiNjKwQA$yi3S!{vaF`)6uvi;8CNk@eM(VJXch zr6@`TF>nqiM`k?FgzvX>_m_=cGs=Rk+ffz~0|$H2#vdDfilP7z10O{JYt%~KDIg=a zMMbMATA6Y6;O{Dh-BihokZt1+Z2G0qyMiiOIat3%GxY$@RHwtr}6yHL;yr)_Th?B+*H$5MZ8J=O%)^t7E;?2{K~bcq$xw?Q~_e(5ttJh5(A4a z#K4)!JngEwsQ9`aK=qa?a!qnNS_kuZhglY>xS7)@Y|2nMy9#39qfn`oT`8q9>IE_I zTI&6gW7Riu7T3m+Y+c{Qdp>7ezb(Djy~%rCbQ-;c^0>r?_Q3Z*C#h6GU zFYhBMaoa8`_NAC{2GEWf2_8$TDCZPxk5qim%=o4ZmD775240K9Qg)@3%BUB_z(3$H zLtviRhRWGB5Cfl!!%}vol**_V z#K14&FhgQsaj0&|)j2Z-=bbn_0yyVi;CVKG%ZYJNllKE!2P6g-heQ)&IGu7tlTT%Q zq69JUU`&AwiGjrlP0=$d0)5^k0Ak=1QO~vUhJwVv;v@r9!)jN67?^}~0f~VHh=Ex- zATh8wxyh$;_5#Gf7gEJ8^xkq~G#<7;X$NqQ0r0T>G;5q^0JMf<&S>)1Qw52EMMMl7 z^yPVQev?n-Q~_e(i5ULOgB-Xki~y)u!d6!r04fF(SZM&bavX>7Dg$7;4&~Xu$^dwt z|BTDTY6IXVyPlr7+5qtW548Il18BQ1Zt@O?Nx|V%cxmMQli2dQCZ9c`-5>^DPP<7A zEN(Xf;;Q2}HhFhZ0EvOc&5?kMDB#W}pQ1T@AO_wQkRCn|1MAT;!v|vEEr$=pz#70S zgKsJ7Ap_tA)3-F@VFTa=6Muan9x(u3Fp(HoY%l=cGLRTpJZb>EV9FDC%m8@7L}Fk8 zVqmQnFPK*FEZArOyqH)`e?MUWykL5O{(jN`c)|1}fu{_B7fi1Zc-jDX!SpVHXAFQB zOg~b~a|Xb3KZ$|G3kJZupq~i5WB|MivN%w$7yxsJ#J~c?z}j@o9TEeJ*9?G}L1JJ5 zVqjeZGlRsy;-3b<@ufqsoSpnNlK34* z#cuYgixNQ$d>keArvSfM-xS~qp)QQg-YN#JA|7DG|gtTsBL01yK|NC6}U z7UhwE=(ez=+53YjBq=KCiQOKqEBJ7 z$F(3JF|de;frD?^r@qZTb@6!*#K50ZVm}Vt&}RL-XXA}#e*z5#zzn>F=W&w(@J4e# zUfo&^03+VznK04-m~gzw5$y)RVs$x9*~S1^tlr`3wXFd#C7bJtgswX777ST}+7s+96~~B(aKT@;S{ubx|USfgi`Awy_H_u(q))F);jiezW&EC6X9eM8v?s zww$ypn|85nxpj#SBNNRSv<++hG*BuES_?lb@{5}y-TV*p$vNDM6QG5{_TpK;*tF#xU!-x64B z09+GDA}j7S0M5500T2UgJJJ|1SAZD!C-gIz%lUF`v%WofjEf$Kf$1hX1H{0);#!aq zRI$+rfHO!8EIr>t0F3ad6U4w82$e(-13yoRBnB3*X>9>-g~U6}8S0`$5CbQ% zsOfHj7d2@!!>0S^6k3pqUT3$+J z)C*$ZBu)vf_j}_C(-RN_Z>bl=z(%hg)1M7s#uUWBx(3!z5(A5041hJXiomZ1z*nIg z2>fOMyk;XYu=w2o_$suXz#j&{oxo!R{xm>Bbq&P8TcH=h-Mj*Q9Ss_ZfyLiAF{7@6 z82BHU{h1|neX=Do6I~@Sut*sI_s%2+7HI?EyjsmBAO_Yw!+CWhfxrNmThDQtf*4rW zz zXVMS@U>r#dEQT8ZS4$EDizWl$;z(j((P9AJR=5Jh!2iJz1!K7Gdo6keATh8Q(c*K2 zc?}0K@b0)0W=ISyx)1|ro+B`!CAz4??oSC!G62l{g20XjfSGaV6;oO&r$e-Zxx~xu z=oW7gEe0hZF|e2!3AmIe z{J||gMNSdn>;fX7?W_ZyO~#>f;yooN8reJ+JAH2~~B zgY#{f0kqvGw0P&DVXzDBJ}I*MB6{tt7N0$$-5>`3mUfdESX^WTVD4Abs*4Q(yWgYT zmlyzcU&p(iOAP?KU*njqFo3>mKc~ejg|PvNfki|N9Gu7gT;Af-JQ@LF;F+kDAu+JH z)(C(RNzVQ23;-j3Wyh~K0F2m|w-YxQfM=vFRLqq`6TXEt%7-EAa7=SA%JJqCczk2ulR8UP*tl@o290We@Lop-MRFkoL2xX%C> zun8RF^#;%bc590_3MK_41{SwRcK^i=-rwT0N30buv5 zob68-0CwL^Bc3z>?B?VZPZLLi}x$-9>cl+ zNM!daJmZPyT7341c7qt0Z*4Lp1{SXw0kHdTUjJV=0POyh{(i#%u=_Snv^Na^yWi%R z{nG$?qP^JSodEg4Z2INp$cX(pFmJc`G>=Ar7?|J0G9(5T9~l8KBFk=lYycQhLNh-x z0F0Q;aro2#dZNA8;(bq@BnB4mM>;Q{wV${6w1zrC41C(w&`Dxo(S;Z|b1yygy^#o= z12|uQFaUJ^!twdh0O+3|J$_;6DbyfHkA*;uizx0sErGyBQ`0 zv-yi-PqlQ7+BjaTBEClvD-C(vD-6%u{&k}V|UyD#_ogx zjNQ@z+U`GEyy-A0IE;4x71{kDGs#w;J)+$p2400qnM(9SWQ_of@kshAX8_o}i8r@p z2GG-}sMULdDo6}0B4XfR6E037-|A0C2~~g?_g_=R!#O?bBLUxXl^WFQ zQ#1vD82CO4xQc?CjRi32YMxE420*WmCos|g7_EDFj*l_`Mr#}PeXId=FNU^y@6iYn z1B-|lI2g$Da9pcT^JoN!fq$hDBnB3fjexjv!-Q5Zgyw+6z+z(5i%lG(omzd0rT`EF z&qbw7EziDbMgUBzAh2%)IG8V$6tkbHf%#HO@9b{?ZS-!f-ucuyo2TR+kdmKw@CAP-_c5ryoyf%}^I5f*6=@@-yG{27X2)0KYHQDwZ0F zx|54rZ0Kw1|Ew_r8KmZvZ)5d!1v&=n8d*1ZZqbX>@RTk-(vtw_HB8qyVd|O zB*uw!ZvK?W|&rh<(;UdpUDd2PdOt=?NSbSS6M9nmZpM|a=f>eD*f1Y+Rv=!mwd z3o)>^X`_*7Yf(+ z>U~22M_|&5h!{BNPXU`-eTt?45Ci*wGN*B(e6ghkpR{^|P!^C3S9}(^)n&!6T78P9 z01yMOqJZ6q|7s=>hWZ!I!`}=5w|>Y@{$T)|ET^)@p9a8ClNeb1WdMvdh=Il5CJ%k+ z)eo(b@o&M;yxjk!4Gy}~LaQx9b7>Tafxo9wBnB3;Ejqzr)JJTUG(b#A6m7D693+w$ zSVY9Y!Bbf9M5--AT~rHV;Qpvo%D$FTHr0R_cs#(&RC>6qOuEfCT z!lX9uE(#zqu$UYP7)2lK+2&I;1%Md%eF`8kusFb2fce!xO|wm(P#F@ZwR!G#kVs-+ zv0o(dF*@bIHlMmE5yZfwQ7IE=#}79WF@1hxtN8}NoZgQ$7PM{g&ESwWZ#GrjLp$e2 zDz4%+Xuna4K(7dc9gA-jCh`-eruag^JoN!for#i5o@>}tu+ELcDvRA zxYqzM!lHZcGXRWuhYus`4FDrv=9zQ90kjc!w0UD8KOix%SQ8m>F+K5Mn@{s-1c-sJ zqY>9~20mc~z=-Lb22UCQuDO*hpEdxDc&{G7GX{VW1KH$R185^2Y4e_?5ueiHMr?Hi7;X`$Lw_@07f_*_%{pyBhI4t-!y=yoc&UpHvp{z5(A4@A{CYF z&s%Lil~Verb&3l|y{gZv#6j`;AF8f!TPkU(vM(RxCCWp<)3oEinK({s^rN41kW`OCz!dK*ztr4W7suKzCe@@Nhe31td%q{s?`M z+nu7yM)r>yP(q4#Dufj!28n^$AVs}@bV19lxBxNm zLA#otAb}Xzqm~?h5R}qCK{CX^`o~8g2DVV6IL9COROR@yjM^N3_0UuQ9LW#^=lDa0 z-dPd@3quT?<8KrC=J@l0`rPIC+b>IEU;$#_Q=znfj#2!Ba@Dn#H8?j7e}`mA3@i*W zaF)ct!Vm-Ju0oB5EQx`IAqLKU0IVs;K=$SwqtRP(3@LBRk{DPRV&EJ@zDMR5mA!S2 zk<{%uMn8|rk{DPRV&E)^fdzt1{Q`GILA=i{d0_$ot`Bz zurS2HSrP*a5CdO`Rx@)9h@F#T;OX2PgGlG)CgQ|CG{@M;!*YysJUmNcU}1=Xa|~Tv zkYn)PkvRt9EzB_#?Wi21wvNs*0_&J8iGhV72F{WgSb!M#XJ}lMV*u5XEQx`|sZGjD zXJttYEDSMlj`2_DXGsh!E^JaiWV;~8fTas_4F9<(yMndvYRb-rhcC`CqUX{qiGjs? z8oMIL=#Z5;Ms!@2V_3$jEQx`IXjalz=NMRVb(X}yBGViUOMw_T$5@H$vLpr;Rn6I_ zVe9odhCke#B{8t5Z&p8;yCq9vU;$#_lhNwd9K#tlWJwGx3^8z)#K2-wbM`yP*qCEj zz{@#)+kYiXVqkG#v$FgjSrP+_gPOBnqTXvceyjf=$M5SO=J-u~bB^D!Kgu4@TB|@r zjMMGoJikP55LF}w77sQn_iYq;ev*A!*o2E+jH}L z@f>sWe2*J<^L#CuaPxdIDcwBZ6(-&M2x#=({3;|Vw`wuTzehIh=G7Y`H_!Jz z#crN&UP|1mvskr*7&y<@DOtDb5~3Z%z$`4paatFC694r1UupRl{R zc|O!ux>dKau!9&l&&SGYH_wN|(9QD^ug0yqk99x{ybgn0>*o2?(+&YhM!8jwv#^60 zIM3&jF>ck1L_3Iqt4ItiI*5U*NDM6cg0UB)I3C*2<|JqvZ-E%N>O@|JI*5U*NDM4M z47@pRffzW?hlX?ADiQ;WiEU~IpXcWJByhf4RY7#`HZ?adaH~iREIZtro99jI zeQut&jqBY!Z`|&8^SpI>z|Hga=0P{l`-z9#JTKr6yLnz@A93@%s%>zqNDM4`j!?!v z>Q<2$So9j9&W6X_DiQ+=5Cczw?Hk=ZFJzWyDITL^;5GGIR1gF6vf~m^B^Q_y5CfmW z5(54vPJIvq^QyHaF>t(-7}%{#e}u}3mL5=)P{hEA)mQ?ZgeC@#=dZ@3ws)i%!_v-f zsC3`itoq4SI4$sKw;Tmcf->T-F2x^b4y%q%pUJ9kT!)P8a|Qm|@)Kqp`Q&X#gxrCk zE4}NHcrwQ%CVMc6%Y9gukVBZ0^1&OBB;|8VeEBw$lq_C`q)7gYxisFG+zKf>i!_wR zFJ0AP#%}4pQz7Y=b5JYsDE``sH}Tg=e1*RvAPxdi$gIU9-Z z$m5Zu9C-nfB1hhYB<;vYkYpS=?NaCyasd*AHe;U_!1!&K2@YYBHNK!Fbwi5bc@&x44F?k`9 zOibR41gF&oBz9cBfy9Z+FOi72bZ&yaxXdH*;&LF8SX_=l5|7KhkR;;rFeEZAuSAlJ z%e#^Iarq3AR9wD~q$nKh9AwNY@l#n-~N;)AQMv_U$np>bx z%Hc?CDYr+0xxPOVA>~m>Tq&0$@ua*4NleQ1Na9kygd`#5CrG4}4Yxv{loOHoQcg#b z!s2r|^htR%a%m~gMv{^846F>OdL)D8 z%gsoHFMmPe`Z9eX^!c(Ul9(@Bki>mC8A-yIvyez%zK$g6%P)}lzO=C8 zkfeRN4U&v6hhu?2=RZMWr{wlXoRr)jiAc$#khm$i9Eq2b*C2_d>}9{iBlw7kcc8V z8HrmYXCd*5H5+^OkA`xl1Hxf534@csq<@+4Jv^)d3cv@bGB$1YPBavx& zDi)7qT3&|4Ps=-zq|)+9Bt>cYE|PRwevc%BUCl3B1!=qC3(amwc}c2XGaE;H+ucrt zCE~AT(9#;9(28G+DHeA*;IWbEkETK4Gf-zG=5ozQKFup5tWK`R{89&}>Vtf8XI@v) zljOnrKqR-u)WAPCSq_=_=Otgqkl77@FI5ML)cEHo z7i*=dWW_3lq>`uObjQD<q7vNtyS&GF9|1!xv*csf?CVQfr_*as= z7;^#tg5>U4?C>v}+)=m6B^PVsb4j7=lqN6LNNMtSoTm6!mb^nFWywXD%J^5FT!a-7 z|MJPLbgPQwXsxs&xp0*#>X!UWYp+T^sf((UGq9H6Uv=_$eGn#3)Xi&>FW@x9zt9Rd zu7dMp|1S3T#Xa%#-{HJ3%a34L?O_MavtnPBb2wc~90CW#z7`xYk9EVlpe7Ofu6PU^ z{s;Yw{Sb15t(q&C`7vaHYZcsbq~dx`fuBSbj=c%^)BOnyL+tl-I1gfm#r`VpvmgAl z_-TM~JD7rumCbKNE@KC?kaM%I!z-~eU6#nc$6RO!r=cvBErRP}z3t#;P*vk*50kqE*P0=}f=+(jvv`P1)?}^u(9Hqe_L|Cris<%$^vC0ZTEKiE-MP z`#Ovn=d{xp?Yi+!yK>zS3f|6XSFU>*r)6S-&eSXY6T9l)A<8J5CwH}Zm#$9TFLLUD zci5dkn=xdj@k!u}==4e8?5=!rJ$({5b9pk=x6+JUq-@a-$dq=~obRf+s;lN6M)LqV zO(zo1$$RHp}>Fiaos3PgCsem7mnPKE>X* z(@#_E1#0fAKJU`izflBr@_CL*T8n(4LuA?>+Uel5y@PV_5>Dr|Jwr`rWq*klX$`!UE6HXxGkedrtgX~K zv3Uq(3{s2V=7|(BXvVDBsJ9oFzCKFACu&yqxr|nPQ^rN7&wD)nwv0Cd*1$h-HAp<6 z1n=D;_z7j)R%$JKV)C|7qJ=%JgjoY`Vc&05jZW=obmL%JqbuGVRczp7U8X9o@2I$J z5G!iw%Xa9LzFarz`}@VXFs-r6UPFs|?#kq?vpv0-FMwk2JiF|hj-rdBqQUD{q3A$c zT^`a0Myn@)R{F*2%e|T;_G+p_QQd($Geij;!o8X#_G)6To_jS(?A4@-thcLq;VUY~ zU;A_icProBj$1<ukS#Xq%?B)l~!aT4(lk#k+|pm_^e_Jt~QcYr;fE2`F@ z%D^;5iAo;ND#rAs4aKlQZDSQ#tbe#GWR1UxRzrb%B?&UE#Ohk;2dNwW_DLTMn`CU98y2Q5LZr z{&vWp66L`O<4>_-r80(X?qLNnewyWf7Jqi!wz;u#wz&% z9*Mna2YVscUNW^Ca{tt2CzTuz>9MzT*@oblG;(i8?d;%4ig_n$Xa_~`e(c?-rL8vj zjJ+2%wS(I+Nn)F#wvO8BGxmPe)(M8O?FUg?M{V>O`!H(jWVf4)VcBd4$I)J)w)u>G zWCtf9`>h-NN~=D$15O;g0L?LF&q{G+K&(QHUCz-V2X}%w&Q6LeW2J9wE5<@q>pX*Q zgILU3+;PP|vE6;(hvK81*e|w>#o)7xdjS8<4qUk0D*2eX-?as9$?{&v{h@P-lEpY9 zVt?vfs(j~d(38J(uDE;~=Kj{XT*)Zbw49&}3i2gunX?_$tDYtOm~(WlZ^@I?Aat&O z$@$E=Iyb1~an|&7Zdl1Tv@E7`O(oB?>Zvsi0C zwS*r+V=C?%}uKSg8}7fI{^83d$+dI@+D! zYG%uIc8nAJi`l%+j*sS5g%g~OwiBITTWam5B~NzrysFftyEp-4=pAi)L}`Q6axZX~_dzKOPtQ{442>Gb^@H=iKt$MoqM0 zPv~5ta5@1fN{J-B1ot0XF!B0OvZ7HfGRoGl!R9NV3rV2CHxj1c_Dr(O9&+Gc)TFr z#ZhX?bX=%pq4FtMYa?tib=Ls^d;>UE>RHw(iU2MWMa6MZ@azPFDUO(lGOtk1K2$u) zis^#S5-Yb7PzjEd@(fj$737WpQb*4~y}S_^w^D1UvRfCG&rnj8sX>)?JScbzs8X_W zu24>cE9Nj$UGS+0pFQGz3UV%P7E%Y$uDU`MuhHDCAT^6Xy#dlz>g-tn`Wc|eN_|hA z{SAQY;d%lC4B%U-HwbKH0BNP>Q^p_zB&^iF)H2ur=-I^C0EQR<-W|ri4>bV30e(su z!wleBsh6o`xB-NfI)P0Z41fU{%_dC-pm&^jkAinTI$m)y%X$^^?0Cf^%rqB#`i1n0C?vP%9vyTcxP7vI~oAqd7Hpw1Hd~YXz3IKz&mp|20I%- zduL?9yAvI+P$soU-g%ayb}9Ju8@)5NAaBBgoQhGvzJnlJ0>>Mm3eF&Kf&nV6R3m{C4baU> zjUsT80V*&NsCKad@>Xhl);QS!xW8S(zMo=%GAs2DHaXP*rB>=a0;d@uXQhrIaJm7q zR_b#CXBZ%`Qa=z_Vt^7W^%sFN4FEprA_7YdfR*Mz+Of<4m@P+hl+H2$X3J7eyyXVK zY`LDkKHC78Eos&`*8rF;qLvE`fZ4K?4!Y0)m@T)n$wdah zY&oB5FE#*X%k|W9i2*QMCQ;}L17KsRp{#Ma0XTi!_=190g!|TtMwTrsWhV z1)md()90Fk+#Z!u*Ac(Y2*C9Dl`5_`0H)7&H1kFS;8_VOt}1wkQANPkt0NV=GILA8 zr*d9i?k>nHsp41KvDREX;F?qE&3g?HQ&*Ea3f^OssLIwvSCi|h`u>7XU0e}17UU*M zoJfgJMoWr}s|9yM!4nw>_~}@bJr*q~2hpQX7kr9luU{!hZZ@BqN()|%`h@uF|p0XI;K*A%kPGp8T9;d`yaIfhCId}(gGjD;~v{QT*$6~){S-*=MC=g8TA-{R#(C^4+9?K z&lR#KqLS-Wac-RC1PpeJzg@^40Cbg8#R0X1zI)pV<|)^=T5SK~RoqRrio2;+aW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z z9d{GzxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$C zZbBV*6Y98|P{-YbI_@UaaW|oky9ssNO{n8;!Z+Y%AwnH@6Ml)DCqf-}6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCbX{QiWcg)n^4EyggWjf)NwbVj=KqU+)b$CZo*;L;XLp{9d{GzxSLSN-Gn;s zCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98| zP{-YbI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{Gz zxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV* z6Y98|P{-YbI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z z9d{GzxSLSN-Gn;sCe(2^p^m!=b=*y;<8DG7cN6Nkn^4EyggWjf)NwbVj=KqU+)b$C zZbBV*6Y98|P{-YbI_@UaaW~;hc$=R{g*xsg)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zI_@UaaW|oky9ssNO{n8;LLGM#>bRRw$K8ZF?k3c6H=&NZ33c2}sN-%z9d{GzxSLSN z-Gn;sCe(2^;n-`io~1(_cN6Nkn^4EyggWjf)NwbVj=KqU+)b$CZbBV*6Y98|P{-Yb zQQS@DGOUgX#N9m2>ywVG;j2$MGW`p#q}3|2rdmbT)R@Sc8WUMlV;XQ)41)YD{EJjft$OF_ASj6)+V4QZ**Bre+h|f`3IdCbFi+ zMAp=p$eJ1xSyN*oYidknO^u1HsWFi?H72sA#zfZCn8=zM6IoMZB5P_)WKE5Utf?`P zH8m!(re@(PWns4(6IoMZB5P_)WKE5Utf?`PH8mZPHHjs76Bc*Xcs!rxPa&$mSObaG zhv2VU{WMCg>OXJ89bolYK#Hq3-Hsc*>UR8XufFUK+z*A{vW^>80J0L{$Ea(i!b*H+ zLGmJH6^A#oN^STH>RW@tGg-4eY-ZU>HGNrT;XPID##Im?|6P0wtSB(ZM}Aq(mvUBj ze)yALmGgEc3i6R(3mO||-C7moBfl&Dm<<`^BYy~AVZ#E0eB_TI3tX#*doNNIex;hZk>C$ z4?tOt(sxD`bpz;H@ojM2YX~~)_pKq`>tE=9YIx<(sMl+M^gh*GQxClNm2g4osw^MG z`fO&MGTS>1nd?#57jMFlFJ|8AQ_5Bugpa~sn@nlOE@5fk!wx-yg_SI{EmWWqk^m0;=$Omj)I4DLH|cta9xr^FyKWVuZ|6T zh26PSdF5#|*lPNbvyku3k=bg_0rPO&PxW-5M|J0`ir;lqJU<-KQStmfy5by4K1*py z(s)px|xB|SGeKFLri94rB#oX z_~eIq7k%9wgCXbF-SQ(jiDMEEThXW7=v!^{VOD)xwFlh(CN>yWh&kT=C_z8)0?rci60B#%-oFP$GZ^D$eTV;v ztyy(OE%TCNFJ|;VnfRLz5N|pZ$MN|yEio(3Dpu@zA3uwjs@nIqP5Y^Z&h}G>DqOXn zx;5M5OLKozO(w$ zIGsFs9gvv(6n_!tejggkktmh&c(^(#m)?yzu527m>W>Rk~^S@4e`z%wmcBy=^ug%inEuUYDcN% z5661p?5%UQ|0!miGgapt|5;e)Ow&2x9}98LzB=dn2Q#;y&Ut0T8Q^!~}JY zFaTS}or7#yj^WWAJ47prIyOh=Z2upq;LOuG$A1k2?Hp-)$3lSchv$$x%1&`ky8b^f zA)KRiO}wET=OTNIwl79CpkN#*+i{Rlr_rF&gU}2OhoGBcuv3Q;_a*pT46WG%$Hgw| zx@q)U?A~o6j?<2Nn79xJC3n=Im1kx$@5cx3< zGV3rm+_@WO>SY{N@;UkqQlC*`Eo?M1M$BR{zYJ0up zAat>$+oPDFeR2~~fx9=AEPoLBzEM7ga&*tDi}D@>48$ON_0G?blC`~o;$TS0eSnU8 zTV<#w_X8yi(#MZrCV7L^v6aqy{pD+@ota2=u%ktWa{tb~S%RQZKMmaRC*gX=1UG@sP5xdk* za-FG1HxN*b>>wWI=~!f%Z$Mf8VK^3<39MLg3FO2svs27K5{)k_MgL<*X-P*%l8&;6 zQ&PoFEIUTesBRUUCkPTzv!)_<8 z?V4dvp(&N~4_IKuW@|mL>uFS|DyxJ$V%uv`q|h>RN2csyOey;} zt!}r~bZddW>bL303SD?| zR9Ip6R8o~W74{&Wc~Hs5;(P9UrNV z=keGI_o1poT3Rv4N`aTNHNFLo_5hY5V*KE_K(dS?%NAuVxld*5ha&JtsVMzrOR`d=%RJUpyyF zfC9G}f1-y46@`hr-PwRVo{j39HzA_Y-R`L@ve@b9kC6c>f@|;yLq^EK~On(IZD9);$OK4gWIbD}(wQa4uvT&x6H$x~_5$tvR{KZ0wW zQ<68Jx|@8MZBJF11bCl9|QJpHE5M5M0sWaIb2<#P4MXpfy94H&YGQ_;G%LnM1B{%s+B;gAu?3D0@)0Yx-v#%Xxl$G0-ir;dS^G=DHz2&s1W<38; zHpVD^%h^>s-~sA-O*gtPYV?|;tyPU)b2_Yj&DmNvx`5KwY6HKC8m)~CRE^elHSmGR zz)bfC(QKs?OJG5zS5`V|vRS#;DeqD(uUAxfsW!sO4P&=X&=!u43Qus<*(IlDY42gqJ)=hCE=Ku?(a+X03|_9te5N&W;VWLPwbTNl0AbG z^c;KL?s9Iw5oK!Oae=^Xip}qaKY?0cKCp9~k5-=F<%4Ib{|~!NLD3w|Inf+VxnpVL zLb_m`w(+OP#&x#trJAYh?2cZpv$s<=s#R{Ct!7V&TIJT+vpTI`XP->#_4;#PWUyLt zp3)hsyp@)%w2R(`2|LH5nPB%;o>5v?+JorZ5~XUTy^WHtRIRjkVMa?|)m8efM*5MQ zN@v;XBv=|rKP&2!5_p!~L>YR8KHD^F;5x8aH(Q5hCA>xfsAS#ZgJvGhOh0C<@{z1N zO}ov8&;}G|J5vxdDS=U(KpJHs#|&d ztvaVG z&$5D@Wl?YirS-IPyqgK$W3^s(sk+DDb@W)E6*saApXC_E$c}xcF5J3fpAAtRn}5I@ z;QD${aR{qlQnWAb<5>NYE`GRVD9=~=;gYec?`qw@WJ;$WE}7fuhZSA?a9I~WT+zi3 zS9bBkD(#1=ec6l0l^d#+8=lr)sIuAD=X%kyD&>S1ln<(u4_;O-sQR2ve5KO^C(;A2 zv*CHU3!^Tb*TngvxFrh$nF|G zvg9C=MG#Sv2#SIT5)=ef%os7Ef*3I8gbBeMQ4|zWF(WEQFyno{tNX0%=llCT&%J-$ z%k$9N^{T2G1X`Z>(q>Q!Zb?2f}#^=iDykYEl+F0kb z5*jBxj-$6Q=+#ryWoZ*GG))5~&r8rw&}b=(P4JJzopB&`LR%UwXl_Ei(aAJ1A!wp0 z%TFpdT{le}w@(w(_ibWk*hIxr4r4EK1-%8$(3ZU_xx}Q*^{H2Dnm%PFc`tLDlj1FH zv{&HO=8mP;kz1*4<{S)&Q)st&9dhzdgl8hro7J1}LxM;QH{B{(i4HrS-GQlZ8_Ih2 zAoj|2TKYdUbu%I4zCT=>i8;p{Ln%j%v)0c#=dPQ#~x%}>Ltq4GC#al`t5|2??# zM-$u_k1V?ex;DHMS7t9xhp)zS8eWa>L?O?-8u!eranHOO_Zq(%-+)3=rMq1M7x2tG zZ_m8*_8PzQ-m_2PW9<7_*u3-h%sX$-yz}Y%sX$- zyz}Y%sX$-yz}LXpj zr&nP$FP+aZ*oj9J+grfL5$_g|s5h;Weo_c`bG=WBQP*pZfsK0?;weRWTXC+vNpXnt zF3f`fuRms7ZiDb;b~g(D>?sPr1xMR!u^z%33M{uLv%v4`Sm05(knJtSKu0_m#i9+x zuD35@vD>knTHamgiS0d#DiLov7ubekpU2j)*l8$G=~Y5beM8pw_Pfj)f{x(3cuY6{ z!L3rndj`r!z2`t2%eetHBfBG%BIEO${TC~mO#(02B*+aNC*QXDM#jrLOQEZwknJ76 zo5L#74? zDL2uXC5Hs5Si-!W9~z|M3FkTF4GU8E;meaTmXYChlnTbE0+hkd#(}sS3zU(ajX)XM z*+?|n*+?|n*+?|n*+?|n*+?|n*+?|n*+?|r*~pWfjr*w@74pr_#`!qQ|L>iR{QutB z$p0TZ8@}1u_`0EEva=C%Om;RBjdnJIvBS>BKvat+8trT(8t-i6$<7A#i?JDBMQ*V5 zsqmg)Bv;yAy@h{4gR6p+op_#}usTRZ5<{Lt>gFI7P2596-WsHw#AK#!3sP=k6zi=C zQnAEwwBsE?3STWdfJN`b?|4!fs?dZ@UyYLju5@`E%P(zrGeG_&l_>j_ZFUoE{FXuf z?R?9$BLoq=>l|EUTam9rV55Ga9r*&nQM;&H3Waytamp?##uXy+ZLpoh{(o-kUYO{` zY{yDW<{OLe1J|&lS&LEQOOtO}7IgOrnKhw_o1f)u{Ab}}x*k)MMGV-)C|i!~zJ zJbwbtl`{p$rl;Ugf>(%mRN#it^++cFYeOi>DW@N zXO7jBsD$dE7cA;r4Kun6BY!a4M<3lqsXpM!>40On)Wo{jS0Uwf$EaA|Aqg%g+c;oe zbDwL}%~aC6x`a#d*|=SfdDo*jKHgOcLEfRb1=3cj9UJKKJ2T77Tk6A#cxi*qPHd?A zJaJ3dDmE;Cet=bMw9BtMEi>=LkIb(pE@PZPY>Y|RDf3qTC{w|)N>yx}TZXpF^ahj} zpP-?vvR`qjh)wWmCC5suSpVoalqvs?cu<_3syJo(WGgm2M%BviK-Xd;(=>Sbz36Og zY>c{<|3s&r7^6Z~CfAAe(igBPZjinoH@J`LnuqtSNNj{D zRZU(WWH@Dv2vW6qCm^B9s-MTPF7FZ~a?3g~aX=nlQs<}Gdv##mD@YVsOkcH?@=Qk9pM|KI5$R3Iu<(w>q*rX939C+O;G4@u@mB?yJ zErP6&t_5)3$H=IIqMxDTv5f$sQ|d0UJxF==Se5?4!0OuQICxs}7o_z8O$R~&?t>zTZcrRU3wrAEvB>o^V}FcrvmqMEjg0_T2Nlgb1O|^ z0CTFYXT1fkc>&aF($txjUKk{*|3n*A+_ln++-P%@wW<@WVbJ0bwGNU?!X&!6$2jg% z6mQXzgE>7=gWS$0apF3Y=tb|Zp54&QDUF+%CC#*{q1Q}yV|O)( zo$OXnQd>OpA)~EXgWDwNY$M#*-wnk^1jT~ZN4OnWCm4h=`wqfUK_cwlC~3FFnH@BaSledms?3WfzV!Vr+3uY@k{{{Kp--B&`L zNZ7>wXWiI~4HB~Zb}YMZ$6D?yp;aiMMLu1rH0X(sbvfussayW99;I&kfAvW3E2Uhd zjG?Ff?if#7)*$6~C;P9I-yLJ(wzy8BWM5ON0{0k5jG(!L(f`}o#|8HWiRy)r7&ut8 zu_F|^uJK6t8!x;q_Hsbq3DjtsC!Kl6*{3t_IHof#c}IYv^}Ho$Y4mu<8Tzjt@9nF{ z`=K5&hz#`j#0jQC=omjZp&l(hqd{H{G??0;!OPA*j`6ayk7K;PZ#!=Ui7M{s>NlMt z3P9JmM74OBtI!jH;PnlHpKy$~2Ojr?vyU6E-&gR4eFZ-k3T{!k4kGUlMCRjC9hm<9 zaJ0 zM2A4gbYs_nL1GaTty@jC^m&d~jw-FIOz$pmvZi+*HT3SH(2${Bmx*0zhM}m~<^rx| zr#Z1EP0(=HA5Ee(SY&=;pX;2`DaCII7cqer=2LPYm6Oa&&%FoewFzc$ju=q6;@z1`+^PPQ*<0GG8@jfiR23JI#a+=bP=d3K@nb9%J89;I8Fn}F%jIwq>RQ_Y#t7A#g}ykmZ}kW#A{?V(Q#64g(z zQFF06B`TA4@j4VZBkCJD3{%k;N2_?-Rke~rFN>NNlvO=A=$8k@s-tY?d}f~&ZF>O{ zR&`S%BYIghSOBVL5gChK8O_q7Rfn^KR|f-F-LIj>RpB5Sx4b`EOjTM}{kRT=AB-l4 znv@a!NYo34kNJi?A2vqkxGT!znYj09*PnhgHDX+(qF9D*YOvKGxX9GV2)ao1n+DPi+LFV2euepwwUlD=LZ(Lt4BB4d(UB8By+VpR`lKzBt< zC#nx5;j@Td8!_+or5Ddd@+`4KmP17`LZfv1R0wYjm?k!qHgW{jin$=rJbOxg8DluErxKy`aIxhJ-doQ2R=*E$eJ^Y47kVm%p{PpO2@=U6{Dyypx3A!0I4=<1egXS6JxpB6#FQ|Rpbq20#O>_y z7%8?6iIHLA2i6%HCQ4aspq+phTOE&LVs~41u@|1!JGExJyAPp`S!4QNGt9F(ZbVD& z+BUT4coy7^wZdK7k2mjD$Fb{>xZPyl*N}O8UuJgVo~(QOk%sf?;@*BNg=Cjt61ev& z<04rOuKRE>PFN%!fsp+={sG5yZ!l7SYmj=wfPbalF!DjP-sveyy5U%QULbX~k!p2J zP_3&wvqCW%=yVY5?p{5TZ!@gUeb|A^+H_!s>C9z)OlLZu%4RQU)3+hxf?g)0-6#x1 zPM&STl_n#%E%z({2C;8eM;}9(b4mMpoS(_M{Y|=unS>qxKx;V{o6MCBnHL9{?e>kh zdIq^ICF05mZntm5)kh84h`0)}CE|+Llboc~M#L4ft0dyeT*KP!8&cJpWxH+1b7?G$ zo9ZGVRopQMvMdRy%3|GitO3n%48B-z96W`aC_iG{{|`1%xL&&)qyPFG!Bp~53*|`u!axbZb zR{Ol{%;n3@=#GD1cINVBXLR3}oxUB#%g)uPo#4yPC|-85wFF;wM&)Ivr=ob-`7L-J z+d(7<)}W}o?9AuO&M01Xa*!kWeAyYr%TA`8e7@|A;$5G^O4oq4F&hN-6a6BZOJ@5~wM}8ZehlA@@+eaX!$2^a+x+#u}5MAW9 z*EfMS<+a7_SjN_@rhMda_sexzxv7tmZfB!gZqv`0=wcFyraRGw+qJ9{isf5Q9kXhp zY@;Oc0?z9)lx)^xhFB%(CEcvDfh>1W;aVUkRmH@u_(D0$Vr+lfgt*_@ydFig1v3)Y{l^Sx<_Zd09=jMBm6K=Sv^#riHJeXvn%WxuX9o(F|JguJ3v>)Suqf0xJC#iy z;j?eu8k#(!C7UdHiTxN|Fp1}8_{MnTR%#s4JJg?`HH z^(wR1tIS@nGJCzs?DZ6Q8?ZVYZCoD?WS+S`sMU~bD|3BN!Sx~dG}i_c`G4ip zTvXSkLijY-M%(R*Wx*f+GREUA*@cVa3*%n|cv}EI-qo5VHVJSo|3!j#1mN>tsaFBs z4FM)AKCu*e(~k1HQ}fI|@n$>DjexwDFt(BR!ks*f&nvd(K5Q^PuLXN};fKOr4|nwP zsb$1FoLYSlT+X6ijHzuw%Jn|NjEsC3r0^w8Wo+c5pm~?#(OX=o@!sF^d7<8SSJMCQ zT}l6c>`J09xKOu5?L66)+`x`C+Lg>PyOPsUD4*?EUZY(}Pj)4_YDGNRm1N5CWLJ_Y ze3XqBYVJz1L6-u<3w0A`BSx@^b2?DyoY6M+y-2BL@LOBGi6g%jGPrrEN$gCf{N=4KSEUSt^ z9OdKORp+BjObtS#aWxSFmHG|2T5ZQMM;(i!r%po2Ty+D^eYFSY3DpMYd6qK@f1=}~ zz0p`fEIL*1#Yv%0c!F1tj#-5}P&_)#V+OW4AU}Gd$#Dv=V?R$a2{*VEO2qKA!8?rz zZhu&BdUPG?H67?Uo%J$g7QPGW1fPMkO2$u{WjS4q0K1SM(ROO{IHr+8zGiUh@;L_4 z!lh`(IZ!Re@HmB6eTm~i!OdFXmQo}RHVIX_0OQ~sQo&}N+&~}m^`pU^Px6fyz`I4u zm|b=!%l7EV{M5lbf5G-CpWhN{Zi4_?u>a=zjKsiY$W0p^U$Dnh$+Xe&1$#D?OuvXB zL$RgizGyckzGNpk99F6)8(tO2pVlCMmA#*le@u|u{olq`*~hW5it=xnbt?iE(LlLr z;5IwK1|YOA4B;#Ygg)CKbiuwt7ufpDAl6{5Z`=tY+nRhtQ$J#M|p;*wpW9^ny z4BzX(E^Uf&j4Bmw!Fa3aY^r8vGt-4lb>^J+Z_cKpgAUAMrB-&?B$PtEITXJphtv0~ z1{rIb)g#^PBNkoL_gu(t#t)u3YmQ{OvLDys{BConQ}#6L-(%dRjIZmQ`;6tw^2s-} zpvQ|a*b*%YARR5Y-k(QykrlKDCR*O8^sh6MP^RtWRXLgEv$u0T(3^0fZNMkTT ztJJ;^!{b5H@-S>lrS^RoUeu6{hv6Vw9)|Bi7XJse@i5Hna(NhL4jMG~j#p-(oi(`y zj=?S4CAcl*W&D!`n1%lvpA{MmS>~fOZf~6Z*9V5CF>@piE)W0pfuS>qd z@yCSXNA$&l=3K#IhbE@Pv938sA))p^f-CLihk>hG#$kO>gE6R%N}#-}EirO-qy{~atB*)!4P${^)%G%gf9a?@k?xd3C8MD z{0t)C<+h%WK3!q!YoXF|REHi{+WJnYc9pHiV|=c*^$5tk#@2J7*R^<_NA>G$-5n)= z!S5zQ%5Gbq3AhKb259zITQ3Lv4JC);aWbM$0emu|_dwW=s9u2nevMx|#9-}=>LIB2 zO;o>!yl(+f@;m%wA>gj4u0ylmNA(>r%nwoh7)JERsNR6?4|Mde_;Z+}Z$pJaj(!L- z2Rr&v^kE48pxL30{sAovb98g)GThOZVmL=Q`lqq@IG>~YU|dEz`Z0{_5sp5WdOCUn z#&oo!+d#^Zj;_PFjB)fEsBn~{`(kwOb963LDsput6fAai1TyEkIu7OMxq1}FY`&|P z!xy%>n!iQ*p{o;U;UibSf$AT-x(d~|yLtr-_KB;f;m@b8ei8lK7}tZ2!4LVy^_P(H zc3gjglAGds2dcjl*S#_F@5c4hXm)d4pAWbtuJbS;@5S}!5dD5!e*`Iyd3r8Xdfd}# zD8JUzM`3uL@bpQjurg0~gXmRx`dxJMraXN&imcAlk7Fcm&eLB)>s#{lP>k8FdHQ9P zJhxE)jA1>mP~U>;`K|N~=uwkax(8aAQKFYX`IAd@CnzzqL_Y*2PASm|^kG(sz6WDA zyF_nA$x}=8vlyN^C3*`6d2WfW;$W5Nr_iJMC3*~$IIToKht^Lo(HbMaphO>vk_$_8 zA4oZ)L{EZ(i%PVOl8a09&8SzuLT|-LbYG#jphAxo`b*^XTA>q=(tCx@N0B}&^sSK6 zcZI$l)rV}*yu%y1LEj3u8MjkkfWaESQ{RX|p0HEzM3IR*^&0ej(oXH8*<*L=)8RIg zck0f7$L-8{9vz#}1m8BX4Z=_6Nppn^0pGPo6`a**xim`F1K#cB8#H zJlTp7oy(K`AaEW}MnKMdo;(c=Pvgn?7@^a7vIOca;0eEbWFb!$qpdS|(hh1YGAHQe zqB@WXXlpS~a$&nAJb3_;&*aH{Q0y$8>_)A#d2$(AU&@m_bp0HjL{a_HV{mdd$Ynga z9D{l}PmaSNU%`_$7@6ff*-qsr;^aHDKA$HC!bPwcTRG>U48P$a=V}Oy@Z@tiN|YyO zfH*w)0w*p{M!`X1JXwJb#(8o+20`&;4tk+^aw?3P!;`~t;_;*l3g_}<7#j6?vI?~l zJh=r!m&cQQm>{1goni1MJjtT10-mIxPa#hH&N41#@&djJp~&#Y7=y8qwYb;wyGK>+p8X@;ku#* zOu;^dih|Us8=>I=>Vx^Xw^4uLc(A$%TGgvnsM}qw#j%I#zQD42s?Ip?r4Gfhx4M5G zrmUI($$izv*_PE$twM|a)psXa)&LcQo`^(l@M6n{8pqFRZ*Oj2zyGRLYlXJUa+%hAel>M&?NMg4=;r>a`; zJQd;aTbm=sa6hVGK`IXJVY^sO{+KT=f?8 zpQqYD+I;mjB%G$YLc#)dFEn4MqL6=vNI<~KL=DIJnd&(3vs5|8{A~3rB%H4n zL;eNoZPdL;bwMw#RZrvmI`t;_XhO<Xr8zffPn zUSBE;Bm9*rLdhMfJ&s?i(;<1MdI)y^Mx6kQe5<}it?!f%U)`lTqwe?WP#k|ylW_b| zEx_?7rJ(1}YABAss29=VZq*jG_Ncd^?XPMa>i(wY;rP2c44V9*R^a?kwG96Dms*6L z{;hVPt-b1R)cr?Sz^}05vH^eaquH(C@A%Q|di=qUW{<`n{AhL|905O?-3$`&quDns z#PVV5XYdEVmc0`b6Tg-nMGC)`oyH&hTK1LjI{aGpCOAEQExRe~j9<%Mj*?Am{RsXP z*g7AkD8#RG<4+OpEAgk;)?@IesjXLFSW0Z&6a7If>QQjOA-JJLy>a;EZkT+$t3$!Gzo<7_<=qdo;c*^NK=Zltd8!sBhdm{Se+xR5#B z*3YA33v9g&e-@$zOrkSvokht-w*D1Eu-Mk`q7O^ZF_`~MTb}}z&ca}!`q{P~4qsVn z>z^U>99ut!3g6_33+~a0jUksVI*m^S5z17xJG03;!`@sO$*m?n!xC0%75_j6V97^0} z>kQoOZq$R6dtg5(ai6U}hf4RO0$k_;?3tn7gSMWC-adqmL5W9fJsYVTn1}SUtAc1;M+WJ=fdCJyL;?L6<9{hO*72wkAY<&lseb(0JBDEgwhCdr@eKk7v zoUJ#*w$H;VQ2qs5Ux4;rwDp5f;w4-6hcmov>*g2`yzm@|PQPmFJm~ToJQ*clw{IK&pyyUwFU1gifFHcN1=>eP+0of?{GEq-PN!mCZrz<4fu8}coFJZ|InEsd zsQ70y{T9xecpFjc?`A2MHQ%>2aTCB^0nqUU%KfKVFb1}ZUc3rmWkcXtO?tD0Eg)(o zdJY_H#UcVCR+F795fxxtiT*wDdumz$+Qz{C+RWVpm5Tp-1BHKYW`?$S8f)fcy+e>g zy_;n9Bv>*r9KWwtB=uufVi<v%2FE-hVO|}f1%rMb0>rojtS(DXA6~KB=y$xO`0^nh9ybf@H z09fw|mN-xVv^s_0;1EQiM4Qb3|B(`b5}mW|V#qIU&vy3@mDt7sIwb2+Ju1;Vt0RTz z_nxx=_i*Yx zMga8QMbA7+033Z#AGq;Y0nqzF`o_@$p!XJnV*~_x56ikAQ}66s$Qu#rJ)fgHF6*&J z)cd%s9#RCo-=GpxMF8|}%?=(f0D8|MI6(mPZpJFp1VHa+srN|&pymWR-V6bORui-C zY&2NBngexgsMTQ{lasR^^`%yGvsx8Ht8Nr9Uj#s_YuM�-)6)9NyCfK&t}?76^b= zuTsWB0T|6;{V|$n2!NW$vBV+)ST;tm#9{$~-m|i9d#F@Akb0jQ>OG8!C0UO>qTc6a z^$pZ}3diaK5dghUB)Cuj^qxs@kpQeDeS6{>uuK4^aj*Wptk@+2u$1&0j1rd#2(&so z>u#V{m$BF9gjy9-_T^cR`ckWFv-=Qjy}YhJ(-t7V=BYG0Xk=R>37Tj`othiaE{FmKL! z>=4zyE32^GS+U0( z3wRLg9|cUKfQLf?b2&gyWIc+efc05jT7rQq=YT#J3J9;yPiNi#Ag|cutqTQ=VZrCI zc7+07%j(e-a5?+=Mz+jc{z3sSW!;4oVDetcHf3IMoOXOO>rpf{*pk&BQNRW4+WRu9 zaHxEO4+Oxgk2oCb<2C^>#7}JVLjmyWBMygGe9q@ZwTl$+0u(La6~HOr3hNedy^0lZeTWxuwy6Sow{AMT zJANGU)@*N>E{!I#K#DW4^qOfFXE^5D(EjR!z6%}xBn-;KlC01buh?UKa z40b4~kvE?!>#l5+eF(qjxYTi)Ch=0=slu@={F*Ya8$2oA+HO(~=(fcn73@yUp9GKNov#=`KY9$;J@2Z-jo<1@987uhzwlgEqjTL@EAxj+&x3Sd?&;~#C z3!!M|75vc)qD3ea?*%o&c9tZLXSI_}wJXsYUW?5_ZGB$!P!?_ZuSypsu4B>NAeL$Z zl_F{Yj*$H^WnUFNl@%7D(NOlai5FPmY}1Ep*>!v+8b|1s=xxZTSOAo-*W?$au<>#z zO6fZir$D%sxeGb^PLpsl{h^z_%Oq50`er2VHi=v-+L5VyqHjZ5rK6wJ*FsXW(Hx-l zSq_ICaU#tIQ`qy(*-zV!MzZ|gaQ$+cy4iLl(riC!|5_D0XX903v#HeNEvX-E*7Y%@ z-zld(P(0eK=SN6yDW_RcK8mlS*K6G;(Q@-^Dd|10lIIUo>#YT*KNT-PWWIhZ-$}#! zsic+J3m?@VrgA`>%npwDN2yYJN+!wnKP#DlQn?v!o9i7Wk${`$u{fo)h<0E%zmBru ziaa!?^mqBakdrwNM$tc(@Z8Ewp&CCIunImR>g3~Z^Z_>TOEishcK{CYA`D|_vtJYQ zLDYlL&Qd4Byf7^&QnH{V0*z#x@hatvD0z3qbAkylhw$#EGHj^<#rPY!u=q%)Eo+|Qg+T~nUQ1?A27B%L0T zLq&re4pu8JE3J-$NC-Mg%20h%25^x;>K#<%&>?5JyU zL_4~an!W>4y&6`{)syY~Oa+ECwi5YM>@@p>PrqM;)KojoE;%KeY5(KxGz%&S{DcB$ za`a9>3@;LH3*^L~!uk@demUI|$AaX%1^-yN6mQdaLBb*gS>$|yT3iqDWobCe=@qSI z%>?WjctuX%#3gK{j{cxJa9OdUC&1Zr4vn77qMx%7v)<(lN<7P=m!J__-Hu~K{eTKs zCBBEeoZ-1|=0lPCL%}J;-Ct|R3rl#4G+}2ZP zOtW&1H+B4s4Q+BxNb}7?BGZzIX(o}E*+yw6nnZr4Ck32j5=}C5m^ir^6)4J#VPd99 zlxFsygv4xr2XfLu-%d62uhLA$oOveE92V;gP1<~lVy$=p;AkYBEl5NU=IG9k`Z#xY z;gEFxFh_Q>Vl(Ve@Ab$(x*0l5ukdh&vRPHtu; z1bF=mSwBB>4HEqt=iknLhw(EZr1OEsZLQN*aH{^@3dbNarR;B9zifiIf zV&Scz>)eJCacGEpDgI7Gq_nUe3B86GK4`^xW_~3i(!A(MW^Evat6ApfAtIfMW|6*6 z`UMX>3l}5TVQqZ2g1Se$Cx+SZ9}{KhnJ7cgL>YP}%Fr`WhMtKs^h}hYXQB)}6J_X` zC_^uZG8BPB63U^9e+b##_#w+{Ei>Q@AyIdjvvJD_(A-RAH?tYLHv#%#P9e){Ei>Q@AyIdjvvJD z_!EXQe#Z~ucl;oJ#}DFn{2+eE58`+HN+?+D`a%4TAH?tYLHv%td@$p8{2+eEPmE^# zjvvJD_(A-Rzhan$_#Hop-|>U^9Y2WQ@q_psKZxJ)gZLdkh~M#_Mzfpaeh|Oo=fTC^ zi~B+RjvvJD_(A-RAH?tYLHv$?5|mh(=LhjSeh|Oo2k|?85WnLG@jHGHzvBn-JAM$q z;|K9Oeh|Oo2k|?85WnLG@jHGHzvBn-JAM$q;|K9Oeh|Oo2k|?85WnLG@jHGHzvBn- zJAM$q_??8r?<6FCCn51W35nlHNc>J>F-*?*orJ{iB-&xD7{8N{_??8r z?<6FCCn51W35nlHNc>Jh;&&1fzmt&oorJ{iBqV+(A@Mtj?Z*W1I|+&3Nl5%oLgIH4 z62Fs>_??8r?<6FCCn51W35nlHNc>Jh;&&1fzmqr|^NR6135nlHNc>Jh;&&1fzmt&o zorJ{iBqV+(A@Ms2iQh>`{7ypRcM=l6laTnGgv9S8Bz`AR3m0VkPD0{$5)!|YkocX1 z#P1{;;&<{GzvCc&hnLRWRh5uoA7J6wD)9rZZ24yAFyHJP=9`_ve6w?ye?tLcJ@U=Y zVZPZp%r`rS`DW)Z|60gdm>=vMItMp_xc#HoL0pr$kr?7ACwaKzxv~m3a(~zbJJFg| z@Hta|+6BC2a0)JJfz)3?N);?_j?~{lDz|WWPrNMK8>I3JdouM;kSZ$Z&XRcbHVX}u z7Cg+99WgSS7qn#xznaVzstaCV3(+9euHZ7JoFLVyU;|6KL2Cbk@2OcVNYxd*%98OQ zb#TEwEU6*|%g|nZ!6_|~(h<|6eg(g0aT0>FgLGq|b(ML>H1j%ucqS+kU zOpu%uDSCo+D}&^eNYNk`ZWbh`MT#zBG8-gkM2coISrsH_MXX}ps?rIX@-EG@jK>wz z)6Nr!k9W<(xhDAcV9MMrWujL6dS(-tgUNnPvRy0wBy$MNq4<5Yz(F<5jRKO zO{omA&#)dr@fXPXT5?=G0}yi1_X;m7McAz)1p9Rx<7Y%t)n- zP?e7t;ZA%~%6$~=r4IWQd6QG6%u7xC42hX3FN+*1H7}(<&BMEeJ6Y&7kqE6GAXq2> zT0Ks%SOBzIM{t$^X!Rn&IRc>78wBSID8u*F5nLo7X(hK2Tq2;s;Ct~1ZV}MLN}fuvMnJxmTu5-I zfINI*HNias@FI2@!Tkb!D|scsLjrQGPuspl;)9e&PoqD5n$n$d8BI>u3;wwXfIm$o z_(}l$X$HYg0r00e1m6jOKP@EqK>+;eY=WN!z@IK8*dqY`bUDHA0^m>A68t3q{E13m_bq{I0Lf9g))3V=WLCr|?5PeTbj0r02M1PKA~r||?$1i+uB5)=u5Kb=fa zA^`q0kDyEd{An>kxd8anB?OfM;7?Z*R0)7Ttt4nE0RFUwptS(_(|rW(1i+sjBj_jq z{Li*G8 z(4W5g3yEH7kDf+0*Kf0^m=7QNM)(;7`90ED`{J>h>qV5&`h1T7t6#z@MtV2Uscq{*)p(R{;FU;#L2A z0rV&8aiIYC(}_|qJM%LTxn77|<` z0RD6~!Eyocr&-$ot`Y#7;leW`?Jk1NQcJl|%uEM2GWnc$SEoIioQAzIt@kg5Vdwk+ zzDfkZuqP4RBmjoJhG4Y-81@o^n+3qI?-JZ10ET^y;8p=Jtojk)HUTi~KP<6E01P|u z4}jYRz_7gt?i2vS7O=|Q0$|u2f_nvUq4)&gegQD-(*zF+fMM5jxqMgv47--#Q2{XQ zA`a-|0$|v42-XVVjSRsP0$|wX1WyWpVOJ15B>;w9P4Kh;81@c=X9U2o_Yjeacy)NyJhRssvVbdaheQ4N6=n@;!9!*ZezLM4*%V5}!ywiA11i-K@30@Zf!%if4 zLjVkWB*B{kVAv-JHVS}YA0T*301Uf{;B5gg>?;JD1i-MlT%6t!0K+;2n+3qIeSQac zPXG*i2*FkXFl@{30JaH$VJiqe5&**b`-%50Wj<_1YZk)VJ8#p6ad4XNbrpS7&gUck#9qQ5ZGi}u0Fe@ z1lIRe#{v8-ATa$4X?FyyntJ(bM{eg|d$lJ@8nH2t4xtns(d6W~t5e=-)%b9?O+2Q|{5^G;GUq%~*xxfo!5$B*L)!5wsQn!#+mPMgR=E zkf5yq7jdouz_7m%bPxc;enZev01O+Uew_rsuz%2pI}3ne*YgUxzW^9^ zEkTU{7m=T-gp50K=9M93lXQJ)YNydI2!($pqa6z_4=(dI*4F z&mib20ES&k&`SUedl5lz0WjWL1@@)xf`p1VYku?nwJMx z;ScGW1Ij&`oQ54%u5Zu4u*JLw8zB;5*j$3c1;DVq2#yc{!yZI1N&pOd48f5CVAzoa zV+6pk&l8Ll0K?u*aI^pz_7&dej1vIEPUmVhK>!SU-o02nrp zV734lwkg4>0$|v3f;j?|nV^T2yKlfmsZyG5aA?O9Ig{s=d$cg^xVT)O+zfUspbwuZ z0$|6#{{%Qo0PNU~C6)?+9jge=5db^RCOA(3>^P0!d;zfI{R9^ZfF19n|6L>ic0A=5 zfQtpdj$;Te6#zS~V3o@Sz>ZfCEEfPf-bXLLN&xJ5)mDIO1i+4m?g6+?0PNV4;CcbD zV?VBHHwu6q2NSFm06UH(SS0{<97}MM0N8O7!D<1p;|T;e3xFMG65JvHcAQ6WtAN0c zr9F6>q09fpLHv6prc>I5O^YNX?fP?e5o#VSg z;KDf<@JagzsRCbojyJ?V3Q$n22Ne5B0A2xH!OPmuA&6l7td9YHkrKEgoKGA4E&vbs zJ*meZQU!yDJBjzo-8mS%R5PlyH5}ny+mZOQ+~e4Dgd-JtbqkE}#T*Q`BD@pB=v+Y% z7XW|0hCmCzaNR)Q3BYizCh!GdxYiKl3BYh|p?#YOzyk3hL4g2_-#NUKC=`GN;v=qY z#RA}v_x=q~A^;Bg<7WU#0l8Lb-(lDxNQVF)u1Y>gU#O50ctP?$y(J?6rTP=qj6NbX81fbs?m-yM)N;SH zKk|0w2mu(syEuNMLlD8}+)r?%01U>EVYtnbG%iOcP~W3O1eSo_TrrQ45^&J_;1uzR zQUWvnP?k7WN?^1eVTq|y!Zs6pK!rOB{Z8$m%?E~q)0CIG6Dm9o8wcl<3hlRsKVHWX zoGk+2kH7y8aH;_K<0_VzBLMz*8^K%w7@XbogLwkrk9V`gd;##ssa$JL3qb_#cLu@f zA)x!U;99m&s$h{gpJ0)ICZ=a6Rk)p@bgGCwn-TWxL@KR+MrN zGnL|6bY+Fd9IKcOJcs{guhON!>nrqjfMkZla^t=No%l5suG7=h2B8{o!EuljRowgaQ$`=VDf$l1(Z?MUn@L{rhvT_ z`Y04C9nlN72397#W?<6JpaFaxjSbt)PC23J6dnGJtbxQp55o7D5Ku+53A z8P9mshHWM?`g)uuuct@khXN{*hv}4)ao1CT$;-_ISH3O07&Xaw6ior88T}CjTtxw8 zjRh2C+-Q3UFnLWw0sHYTCYA9hngX&Jok5{MgXWC|RAk&<6fl6-6$H=oDw>)@?{AUu zD4GJ=W%M`-=*2=E8Vjh-xMx#<$!ik|c$W)W$BakO6i}Pdt8iL6eDH89en2L;oJH_V zhcW1!abKW-@?TMB|4hkFYVa7B_JcAWMN>e}jQ$j-$t*SN9csXUa|k#jbXo8VZ00$q%@u3>S%f;9!Z7QUceZDD5#yO2kc@12XPu zZ1d*r$Qu~8IgO&mWISraHYaBE-)u9Vqj9WAM4QKQy*n-h4p#H?z5$q;32r7F+&dgV z6CN*Bpv3pQH#$+O;8n;)-vXQ@0Qas3?gE%DGN1v5=ID%@?Fcnj^Zt5VsOBCH^o)$h z4p7ax8T~K{C9gFXols&F*QwulVOSslH$f{|Vvzt`bZ#X$QvmKee_>ab3cwxBT`X~) z09>P=BDhchF3FD)EE5o1fltY}TdDV59NyWX-sf?aU6S$GBkFy1M#nor@8-PFT`K~h z_jv@@3rL!gxIE*wL*dlJl(;;U*p^R@D>EM3qQo^BeGesm$zI$c0wD1_g1ZG^Bns)D z_X)sAzna2g7;{yqv6cBWLb;jL9HTQ7nZwb|G!`7e4c4f&^QRxdM9+&kDr4hLm( z*u+4(^!AL$#@WQz8GTG=G%=M;ebbK+vj{umHL?% zCbu%Uc2se7DXa82D(riRJUd@XP%8jy*lLd7fdVi(w-X#J z0Hd>oLw<+=OsjKf@OlAwce9M3hXA~;_>wYu3Bbe4MRb_H0x-h$T=M$~z{AVUT<`ja zAc7VC4uSy!BF6tJDqW{5Y!KnlRE9Pf$eBE_(xY`~gW;8WKNL#t`3?N=Pyk=|WVy^7 zA;2>d2UofyDe-BJ%g|8bl^n*=l^)xo#0i!9;TlMMWDEGDPym;MCkZACfK}HMOc4O9 zzC>`m09f@6f@uPv)jI?y34m1-TvBETz+5dRm?;2rwZnG+vjkvP{D%gZ6M_h?s1NcI zJ6B4;s=Ig-IbQ&*`U}D70$|lY2o?%}RUfB}MFL<|MgLnO09LKzR5(ijR{d@SO9kM% zJ)1**t^nBm;>`dTgaAh6b$e{3yA{KmTE`XVn9v4~@DB9CN{`mDN`8n>Na>Ds`1l=z zH?1_IC7m>5+*F#8Nx5mpljNrvd{C6;PIYOTo0jP`cepCk+zx4;=F9ZzG+)KGOY=o$ zr!?OS?w{tntGYB_xE!43JAnE$A9j1C`C!;D&8NG8X+DxoO7ppDN}3Nx)6#sxnUUsW z%B(b>HRh)Iz;Jq+cm0dfymdb-&HL|j)4U_TFwNWAOVYeIy&}yU%&XJ9OI(rWt=`Hs z@7Hcl^A2iFnl~tSrFpr(FU?EzLupfg2gn*_km0x&bKW{F<}U}oG% zuv-9T#;pW<1Yl;|P4KG#%#4Q!eiMM1@dUx|0x&by6Z|0nGvj4~KLuckydItq|4RU_ z7u|4U9^WefYi3^p_z52l92@Tz1`|XCU=clnz!88&^bdlV0L;I~*@_Z?`8Ss(as*)h zEh5MjfcaO=DhUCYf0GFE1z`S7BPbAn`8SK8NC4*F=>$y$VE(;KyO#>U{Cl6EOaRv1 zi&!Ns05@vO2`U6&A$}zaP$>W};g;j6Af6R~*Gk{9L~{Xn@41_xr2vd0X8E_R+;wo3 zRDVp}_^wvL^>Yk8wz}GzQHMhCr;gS7n}gv`&n3b469HIhUnS@)0RHqgK^Fn=r}qi= z7XW|SPS8~V{OK!#8UgU9T?DlP;7_{=>IA@_{vtR)0Q@P6r6qo#0Ql2v7vLZP@TUa? z{}BLxI-8)I0Ql2I1lYNC5ol zDuN{f;7>OaoFxGMbQ{4^0r01L3CQ5nL?*{&Xq9wF2Nz*AT1_0DoFVaDxE&)9nN+1;C#! z;l=1C0r01*32qh;_|x&#?l`zgYBc?6TIf&HaaR$)wc4Yn(VyYgPXzZ1pg$2jAb|cv@Sp(t6Tw3Q=ufzVi9alW{zUMI0QwWbqXOtp1dj=TKi$O1 z^|%1|(+J!&#h(yBe?SIe{{3t;ncq!$T(6aasEgWx9t@TYePeii_K z+D7n;0Ql2q1iJ;mpLP=L5deSsk>FPW@TcDheiHzH`iJ0m0r01m9P&Q|z@OeI0r*P* z{An}6UIFkYexX?0Y8`eC{&Xt`G$H{0^aOz;0RFU*ASM9*^fzTF0q`f6H+DG!;7?z% zO0EF-)0Zrf5CDJLMUXE5{eIM9o6o&I4!4Vms1_9q$s|#mEM5U zG#?kNG;i{pG%w96%>^|#O|kh_-sRM@u62|G(4UXG>c4STI(P`SFh1#O+Kbp2p*KL| zp9)~Rk@(iGZnih{X@^Ii__nU4M!9ZGeAd<5hzgu>-*(l9^~DI8Czf4Z|Lck6djXhn z=85G80hn>-iRDKDm~rNb-iDkC{%sBJJvPS@BoOxpT zRRCt3d1CoZ0A`$dV);V=W}JCq`AYz1oOxo|D*!XjJh50cVQ(?x%o9sQ0A`$dVsQk( zW6TpvOaMH_Jh3PN@EG&Nk|O{!&OEW?3c!prPb>)mm~rNbC0_t$oOxm?5CE?;Pb@_O zFyr2@gaMlhz>G6bETsZ4T^)1^kIu9PzO=!Bl4C!%cMn z$ArL!*En4O#)lw=mqeJ`N7T4`*~IA1$QxY~%4<_0LSSB7 z+40#m?xmFYd>`b^2_-hKMq*)&$F?YOX^p;{5|80UQ zzs93z3b?dJ@1lU4Dfsfn0xqg?`QAtXbQNoMt4M^WKL`FRgDE) zSL5ZX#>8tv4Dqa+|3j)6qkkgBcXsSHF&bdqi71)P@{jMfF$Nz{Q1TL zo~dz54ut@ZU3fMW(6SbZ7i&CNrLO1g1K?)_sNoexN@d5enEye;ixu zQ8Wcis?{G*z%A_4KiEF61H+_C;+2M4KAp4H&8%(E_N4%0;bc#m)Cj}O#v%v{f{YNEtjAhYBRx= zIuLMmt#*b$z$NVVwSn-|06N{u+B}M;fZJ;QN)$?tq495TEMRr5?o9!2Qur;QfJmG^Ia;i~IQIz^%tv(f}$u1pH_~FL=y0_N74tc3|bdLMOe$A{$;?Y`< zq9|ZptiktQ0j1w{fD)A6h#4_*ZLPzz+E)>myHE%uhkDxzy^BLr=fsit|U8Z^C+5XZK`!& z#%Vd#D5oe&{h?NWfzxC^&V-+Wns(?$-`2W0!yvU=J@R&i!+j)m{H4~TC<^$iR`)}p z)A z`FFC3BRS4~U4y44&*uEk3jv?jj^c`vUzgdpiFlpf$R^rQst)u?{m!+hNnIWrXA`A$ zequP9_;f$;vVEEu!fBV@r-@zl0OgIFD5}$4P&;)J?=YK&P255Esi@0i;~ajs&h3Xn z-5t9McJ2zIZ?FHb|+m)I-O32WSFHBAQ^^51Z8Jt5^!V_0g+WeRAdto z1(8Km5D*naToDC9WEa5=H^c=|_z?FUP!Vwf6h*-u{nUF-RSMy|f9~aZNOhg6I`3O= zRabR)I&*0EXO30Fe6YASwqxr?$3@TKj63Fur$k=)i=+|=*6o6oTJTPV*Jg)?|)*~dQ{lopmj3NO}1y=ZiZ1BP!Xds zniyQ+Hs}WvpKvW6a-4~^oO{ELGck*EZ}^EO236SI(K^|iC(ZeJ6NQY@h>94EvuoWe z#1K@f#jez%G1|SX!oDAer5|!}9jjXMye#d-tF&=>fOGy$o@ZB_I59?5h^=UyoX2%; zbbeyAVo=6cI5fsP$|)7L?;MzTk5ld1ihrL_>?SZx1AN9zV7dls!E3zVRv{Xob+RS> zxw=B#4Gv_Oud8rqoV~cY!X7~reHp!5w9~js+ecq+(*SO^x3k6_8bE6VW>$rmLldK0 zqwJ=9FBDq#4 z|56R$cI-e)0LwIhi|j^>#BvQF`ajX{6&g@}-(4Zv!=>an8eEX~dpcXLs&LpN`u$La zeF6P$!`b(UCQ#QfYbwM{63k&=*X9Z4li;xmhtwRtXDaOa1NHDds|N>P5y;_tP6K-Q zp4R{#85}0n3mU)!ro(h%lLqjB=?~U;Q3H6uWO3WttN}b_h!S{719-qxLf~Z$-~m$^ zfh`)q1Ez&M3$|(i4wLN1m(@-7rMS?mP{j&YvSOp3$FFI2>V4gfA=X$sEUTIDz;5I}u9vaFsov z0lz#YKC2M-kx^FuJU=rIb0Pnx!l5lP9Tz zEi&4bc6Ty1CV^9_E(+vNjj=ISig6^kj2l<5Qte`OxKX&34yj2{v(mnW1n=@1pg2#E zzfP%9DIO<*!|gYbC-|1`c$E&RNl;d4e@21>>{EH3fH#a+(WUy8C-kXyrLYEpaV|;H zdB(%+Q^QJ!ws^nStkT|yN~I@P0&h{7e`bs)nvDsx)&OSUI-bWB8o(1xKCBLAH2^1e z^Gs-`0Zh0$>}RzGuvjgkD;+d|#p)BTUY#|7DfxO8fG!%ql>D4Ex@rJU<0(XwO0kDM z8$cgVtyH&}U-L}uR_U%_hdRB@$=Yil0j#lq{XlA!TW*~+; zPcQ_-jY_2xNHFYQg3^E3tq~faOJ?vqj6WGa<#fFu&zPm}7gaj6MVH1_+DpiIBN@l# z2{5NiJJ9zlG^3D=qbtQ0GGChG#@2<4(!lCkUfhN#CE{u=3wce>q#N(*QP!t*r5o2CzxIN#J1(V3QcZ^X(B0V3XLv8jorKo5W`X z9@79eiLVK)*8nz&BLp7T05*vOIRH;;0DHn=0#9iGdxF^(zy=NAdKyGJa9%esYZQD@}lINydE|z?FgQ=Y9>;k|y?4 z+Qx-2v5yHSkfxgcVTJsjj{DTt{{bN@{RrZRZ=;~~SK3w(hX*8Z|LPP`T z>eU3I8bDWl$pN z0gU4c0*y7my^z2u8o)SKasO?q0gU4!o=MF$fN@+wpp^!&TRuskLIcmIZC@qM0)H~V3+#?nYP(&*y|;IjL-)AK53I6prW1`g z;|5i!izDuBSMW07{5-&Wy|=h_T%ZA(FoXT7#A7tkh*!1!tJLLFTV@7VIW$fa7ggDB z&_rwQ+85^u1V z;PhJVI1@F1!P!k;CTRdyEj!@ovZ;|x$NW4a+L*&NR z4Z!abIx$-V@Vgl!c9RC+_w6K|qXGCmi}USf4Jf~_trA1vQnD}oo}Tx6KBG3b%3+V_ z_q;0mCHg&^<1k+n!0%f0>TV6d?@#IXJsN=Dt9aG3Km+jm1CH534fy4(xvfgJa_AnN_`J$q zLMIk*qJ60e;6#Gm`bqTu(^Q|`cVV0*@W};Ck?>n?;M|>HGqzv$4UH)1~6drNcyV=Fko#s z2ESKZJK>IB;p#2VLK>Hokfc8720qwV~0p<69t3(U9l)RjN|DE^yd1k^{hdrX-HL~_N z`kibCJfR5??{!`1tV828kjkC5j8jM$SPMne_$UjPHm=!0X zEZK_FqfwsVFjuLjS%=glXp^;XBEkJ6uGAjDrR6-EvKm0IrxIwV0gTp@JjYMh07k0= z``$?dsuwM?;t@L0i=k+hcj6SDhi7CRx<@B^WbN1JL?50_JvBj4F3MfA;s+88CP8-{ zSdLNetV3!N49eQ=E(JlFXWs>y04|jh7@P-um@i4vT&QbczSLxNhG;-JeNI*k16^_? zPsss!o9FWk8J2bE4Q-Cj+S6!rA5XT+w26RpdSq6tB*AI)b5x$-D~|futV3!NOwPLR zlAs%1x+bf>HZtMk6J(sC0aG$g$lAY>u@@O9DQn5E8OLk0G1?;I4OzGDWner~ANZ_1 z0bkpZCgx~H)yWxIy9+8O8*zHi%rmwi{mt1JZSmsmimW&vm1@z^TI8mg`B`_)F*ElZ zXXZa_y)X~pydc9JS^H6%xrn`-mp3z%L0^=Ok(-Rmv+iy(N`jS|0CP-+;(-$#Uy`-W zF<^X!C&tn|<1L+$S(A;?7R}z46-B62i;mVJH_fci+BX0!p~`pg3Dr`*z49h!|C1WP zWal672tK6&I1=DQ+K>k@k-&kCSy#Z{+v$ymG8=VX`S5U7tfiwZIE^07&w?`;?q{|4Q_@_=g4%*3a3=|7rjy%k`}Bmj*D@o%!eL z{?-8E+7o~G?H`?oJQ`>}zbJ>3W%SU<#po`b3g+A`bZRGiYv=N3Je>NH zt-=}zNJf9o{+f&{xXg;2+((nIa3hc8VzfoGN3!BC9M)oAYmu8~3UhYpIG8z~5iU|K z&HScNkQ41tmXu}joZ6>6Zs8?4hg2j;=j?MyP<#sTvOEEHc3Mp3#558trCYW01Y7A= zdCnm<2~Nq`i%2lE8Sthj5;V$*%_Ml01da0q8@c2)&pD(fL1oU~O@dWC53?tBp;b

    -WCPD9< zeE|s;a%=9JCkUYoG3b#KGfD7%N0jx<6P(T%49q#CCc)60{TK<3)(1X9dw}`XnwCcD zJ}Jfva^gcW4(5!xFwgihgK}}sp)E3w&DoSoEe$pYK29@Y`uxFGS7-op`a;&2kUQZ! zgV8xrf!4_<>E~s66ZdmZnv`>BoF=B`?7lS7fpMRv8P&*Nl@nKyfWOuaUXv#{+5(vw zIfv9Fn3J@VWmIlvc1aw`f33@f&jDbu!MOwOM(_w;CXGTh5^^GTxK350G(Y zGvEs~fpTeHPDCbvpan;Hex6`ZLu3}^98!~DMb5qyl}aDydA(W_AWBUbi3c=*1$774 z!8IDd<->Z;ss}ZIvD?=Iz*-IXA~^IO-4O9J)s*p2*op=*0S# zz@O3t7`uL)gc~#fCk%%784bXRPk1x3Q3G(|9iBPQYCt*hXigMOgcJQ(wm$E~-HgQZ zIfw4ii7h#M5-OFhlkp2p024MVeyIVNIEDTEN&|@gvz!zAG=PqOM~?j( zK*u+co-lLp|` z7@j;oYXDx=r4zqs0A4-DE3IEO0IxD!ihk38^6I;sXas}Fi%9o<-m9Bf@o3JWzx2vz zYhO&S{%H!_*Y@Arwe#6ezXsryMVpoe)NuSaCvKsMy=?t=-oys>C(zcRahh=3+JDo; zB6d8c3DEJ;tXQA{n3zCMYiIx+f05qCHGqz9pc4rVpyP*l(^04a)p5J6s5=>6oz0WY zX{$E5{-i2u>(F0%RjaLi8Y-2x>kK@t2`o9wO52LzBpA%`Oy&t1@zg47>yVlRjoaGO zNzjpt?J0SJ5Xx#BzF@<)Vl^3LVWYOi8<_cp&NpxCJWqz2PvV1comx2f$24p;N_VH6} zXqV4yuDL=6Sq%%5=$;=lXxs*7=7b2m>aE_E==)N+aW2wFFQ1TFFl&AN`}Sn zVZEE$Bo-h7!&7`A_RWUO!U7V2O z%X<@3d=YO_im#$wnc`bplT&;H>#F!=Y%#GyM&#=FWacJSB-X*tDJi}{H9J0&*!2}M zN^|44GIxWje|w7WKiwIh!kKwjg^bp`6kk}nE5+A;=EoPZ_T#Gd-6_7&vmic;wLewZ z;uPNwS(4%#9rvgBTE^1&ohpx?*2c5E7Hw21$7o%=Gjk_bCTh9-OCWrmVRJmmR%cbp{=OV<#$1oe#AQD14+3o(caiL+n;ZJ{pLvOE6v9#39IlPq9d}><3cOV2OdRMn$Hc2tu*h# zORU1>tg}wFEVa_S!}hE+Z)%fP;lnI^Llvg1G;b?wS!v!J*0$2T#j9f#KEpacWD}z+ zuuxfP-t|<2U>r_&t8fboy`1!*JqUnyvV;XY;?<`SbY zid|q0ZKlH-k{MRvv?eG#P1U{5DxAY?buPib6>zu8=7rm{R+^Vi&sk|+-aK!mc|GxhmF5P% z$x3sRebGvDSKDkA*6IMZ^0qQWFIj~RnXT7Woi$cr3uf!LP55zQZMD+e$PA(W#!Xj5 zP5$+pr}3R7j%@-p52C_wUE*S@u!KNt&uO4)+1AfpE3#lIGCs^xBXmwQdLt&|y4#R( zUc#s8?8K+fIfPHY0SUZV7e2K1Wk7i zl91^xMPi$-aVspDZV?j4bQ>dyKrbDMYq|rFL``=Ll9=fZoDX|GcPtXq=iY$C=W`b! z@%!BMNGzZG3KHRSKSdJoxj!KZ`ds^N*z>t{kk~%A*FCW3b4Ma^eC|{v5uZB`iR*J8 zL=yG6FCvNg+zS@Kp5L8-#Pqv!kof%Wj-|l-?o#9|zxy3>!teT)!JglJ8eq`xzJVm< zcfUYl``w!N!X9d(isN_NA{X(yeUP|*cNCH+nlFbvzuN$bVYzLQn3mfIiO+IJA@N)8 zG$fYg&PO6FcO8;|<-UX@Xt_I)ge>MOHWE{~Es^+y+ZBmlxECU^ggXg|5bi+?V?elbkqZiUIg*fYpFv^^_w?1U zC*1x>9O1so@e}S1$hpE@gd{55^+;mEeFKRRaKAue2Hf9~_yTV90oV(;m&1Y;aLbVs z0k;ZCAmH{y5)8PH-3NOC_afx%fSX$bdjYpM5+~qZj3g3piza-T)wgxq(KL_+R^^~|~-Tz4Ik zi0i(D#C6@BNTRNL2uaL!{VQNE>Xsrgqwc9ld{MU(5`WYkgv5%vdrzg z77ckeS`#f?XZ$ej{2R{vH`;(&zlV?H~tv6+V5=jGy3=VJ-LqRnPDzQ8m)<@Ug~S zqgS%=j!)Ta-2pT+tUvxh)gJx;uNAZ(=d(8fABTxYg^Iplz!x z#3loxAE6**SoeL4+(7?K6h-EIe9YD*QF9ioy!Kz(diE$?{OJf??6Lj0PRHE}v@l#NGo`{5Gy z&MG?HOf9_=E>OM5N>|US`J5M zgBzP|7=`@HAu;`g}2ZQ^(e+-U;HBl<83_c?b z5h@j)@Tt*JK%DXDg5lhNPt*AUG50xVe!{@m2vx}WOa`eEqZ2YBEirug#-~STv++n& zHJk;%$q8}jPXw!zpRAEI_#oeg((swl^KU|>pLen948+KE&e}~o76M^8_k2e?_rp$s zbN*h$)_D(gs-0P&p6)J3kqV45D+KBd%2h~P&xICDS`rBbEJl}s8 zI+ZyBSAF3H1$Ur7Wv8&<-kS8tDEkESKfI_WV}diI`(ET0`$wT#JuAG@o;3##9yaU; z_&|}I9r&}P^*@A(@PjIEmKyb&V~&N_=JO>+gRw(K7~ysKe6dk~0Y)zTkjg`FrhXGd zIQ&SyJZ{tW{@3g*T|YPZ;%QBEI2``Es98ezvH7(%`Ueo_U9>Qq9yr-eXX;lxYioc| zIIXY{1r4h+PtVu=ud=a&{^Td;ThTT*qgm~*+4y@HFr9gz@Hq+0LCYxv5tg5~=-P+= z0IEiYfhga2S9A;;--UD0aNY-n>8!!A&v_o7SRpqu4tx9^*sRrmk2U)|x{A#2MFT;3Qmm#%F9tQBSj!6UB(%2PoXj zEUiBqt>a7IMXtA5%8H@*1cWEtN7anP&*x0;YnF0LDu{EP44-4Fg))BeJIM7nYjHs= ziGQ#VxdCRa#W0Y<5_oC_uL0m{c%bQDOOLu?tx1Q^GYew3!Uy9w6kT9u)<}<Ui=lV6_=P9 z&YfiZajcZ#(JGfRVwZA)UTXSt2wjlfI{90;&@?>OEU0}OI=LK!5FTe1aTPP-jp)!7 zD(8!T^&N8K%_6SYR{X_pk(;1$p}5Pki7FR~Pa(@Bl`Du3!Bh-iW5&r+ z61Oo)!_!nQ6`#j;*O?wq?{qv#>o=%eCO)6Dc9to3!?O4vJU?fvT-|sfId3xM=2#xT zgh8F7a`oc((E810IlI>|ZZI5k&2p|XjWOscgdld5@w>(JXOIb&qh2J1Ii=1DCmS6E z#3}v*0db}r7mRl{327Es7^j6y z7h|$G6a7orayepC;7l$s?m)|L5DMq&ns1=MD6`q}8ks?OUSMvDe;0}xSFqnRqnXW^ zAR*_*f*jlO8q}Gc;1H;*Q|Bgmb&6#z*$nT^-g%j_0xGU z{ymP3vIiXW@!5EM9$kDOjLa+XX2^ufCNpv$#VsWN|OL@*5H#GEPob9DB*b+Bq}UElat=;IacW_9`Wo(F#?QlS!K=t z=$eeE>J}HGayd(d^@A>EP*pLfZ2599l)sH5u<_`n1cSI&Q6CaUstek4m ziBv~7195CD1h^anZaP6Mfj;N1opQ~*?swGh?4OTHnGTq09V2HJY?zNZ{TVWmZrme~ z;q^hJdr~@4wj8HwYqo z4#Lqz%Vd!gouQ0IqNPhE5{cgUpgeG+d*~aSk1kMkqS3eRmq;{P^FDbHiw;;K4+^5? zxVFN-8qvEK$%A;bKYEORiRjs?Rbh07a=tL?S9NMe7bv7=^v`v&a#8eAg%m}nU<~lD zI6CD4c~BBPRkbROwpT_=qm!1(A}@MCSx-f`siIoZVQXbkt>{#BP&+zJHLnwWlczSn zh>y&E?AUm`5xtw^@$Gt)IHU1tIonZcIDf$*)0qpTz}fQ%uELyZd{#U6K8h;`_b}^N zZYdz#Vt+;FBX06>nY=}=0(UK|q}|_9-)QRI#G2J^CCjEq8?p>n6-H+3QV!I?f=%$E zZ0Mhu4&N2aGr7s-qsAD~L&f~M1Uv9(j79W&Kb;M-Zsu|HI21in@EaTchEPX;s?GUs zlr3iF=h`gb1;cAhS0hl-U;J<5IQSPnGCwaw^H{Tj)=1?R8EYYLMb*w9Ybp0?*li8F zu~vRQ2&_q_-Z+ro1A(YLj+>napWWN)5N}5R-Ni{8$4!Tzr|!}c@;B{+P19X2%Hdt} z;O{uzXa<&}phb_M$xPjk=y>x6So+*`X5a-BwR|1tn)|SskVUP&B=bBou#ZJsuqwIp zP3dpz;iIlF+`G*hTn~)qv%W{sOfz8It0`_YBZ_?t*{7I+B#PP$!S`s$)RC}Oz+?p@qGNxFaY)3UU+^dvjzW8{Px$SvZS{2geB`fWdana3U?j@K)SzC`BN zK)X5&`QgB6zkh)A32EtkRIWbDhy1%{vwv9c^`La<^f&%OW~G~(_$|_YftSfzX=8Bv z)udO=9%SW9bf2s`xp1|6RhF6-FQ#hLe*KiRQQ5e`=Qlbw3i$3cldSp)O9#fSA|rkP~# zbnYzVJ~NYzS#+_=G?zu4>%xnIm&`iMbwhE>@}B@~$xo$DucMa*x0=a|*zyhRDaf26 zTb^+Zi{4J2F%_qM!Pev%TToh~Rlqo6@ofC#WPF-8B7%``@YBdR4mQBB&kWcO5}$Y= zg~Sq1qaVJISdYZN5i5szN=a9^VpZb9XNH2P>>mRQX0y_v#Cs9<1^d{*2V-q9Tb52F zWCizQk@1CspCb{L7&T@B!EcfC*Lepe?-tKty^wWQF+yl@%>;h|_~miH;(8SfnzZg8 zY@UgRp`}m3K&aIQwwsPmf9QN5R%k0Gnh31|5(w?bXE4<98B`CoL#Z8_`Xu(&(3~f* zw1zG~X)NSNX+h|D;F-|tz%!v9_$&+EfzrC6Gk}+e?f_@K&}YD#hRW~>vDv&ctIgeX z=75i%AN)g?{>HH{WFoNs(6_v23+=?G2n_@h2<=0iV5lpOL!p=OX@{=CXE?M8xD$E@ zZ6l$RaO{Q_<2V{>jkdAS?f5JRy@b!*p)gAKhN{r&hmeQQzeD3t^Pgiby>9+SXF9&d zn6%msmkc}ZuV>oZFwWu8SS2GzVtLoUT} ziUIe=u0?80>!rT(h`Q`npA@1TjCX^N&%Md)_a34}ho0Bu8&-l!gWy(d?^Bt|bBI;97fm#ff|Na(*fc0-f8;aV*8Bx=S& zHM(;RytE&taOkpgFzG@Y&^8g;aV|n1`W$%8&>_?*3Y~m520K)Z&yvtY*eVTu0P9}p zY}84HUPGN!=vMI84iyc;T~X*2e5OO+!p}^o2|OMwhn!}H~O?w?&yT`PL zAU+FByDvBwn)a3O>t55o1kD$j_UWkkvuO_m%P*!q6X36=-3DfVGwt~Re@D$ehB3fr zj|cd?&;Au;U;FK;=?Wgmux-j-bsU;0=!|2B1B z%l;9kUq8$4jJTX*+0P)Z{VjVo{j}_%i0MGfZUmNdExQ778D!aSp}~2UeFmcYm}N)c zQlYTZaImJZec+rd>>!-KO4tJsv#W(YA9G>1u=$s$KNWTq7WN4HEj0g3*mco-udo+m zz&;oDrAWRI_ABV$J3+h0V7v$!wD*JMy`cR$YQ7(|zee*9f_5iF{==ZX31)W$?KuE< z2JILEvMXqR1?rE2_8zc2{Un?iUu;LwhY7{@BZ%3=V*6v%oK$STgz#KhZ0|&nCl}jw8LVRa1@!3Z zVtWvrxTe_N3hPsfZ5xrFT5NYi&1;M8&S05VY!8Qn(~E5rHD?stE77icvHdY3ar$C= zCmOV0Z0|=|$HjIOES(nH1*p<_vAr5BXDqhwL-U?nY!jXCwZ&eIX>;L0`(^}d$U*yl z1bOH|`yi?eJ7}*#--jQxU6>tl(4K;6bJ0P&Ilz$z!~a3YF0X;>lHDL5$AfZ2;|d-u zK?KJ0;C-~1z=N%5Gm!@!alTFB!7s3PB@aGEL?`p083?c90sr9m)jZe)53k|D97Jde z53YlIQ+ZH=R@d@i25e2^L1VZvT^^v9(<^`sg{>Jph+yols9;Mny%_yw(Q z;K7}+ej^WJ==v-k_|g21!8o`9$elcxhoH{m!AJ!8E*>;OWajf=FP$HTgF~=>H4myV zMR;Kqz6o`>cZU~%(8q(XFj4$GmJ(}ZBaz8!@qQ9FL3ZSV(8<+8d&%9U>G`R@u1Cx>;(=w!f1d8lVOXs!oOpf za6yKb&Tv}zcyIolve}m|rAo^8Ziuo0}A&JQqX_LXs ziac9@X%$%#$DE3EieN%T#?-)Uikwu4`4ZWNno}b8g6G;uSs1g!@aItMZ|T1Ybb_3& zWlb^t4}=h-GyC*5tZU8aWLUK9Vk1^}Jr1Vjfgs){IHQwcP0#18h!H!56=rAv?;Z3t ztn2bw{2(QICh{}$d3@0x?PXZk>tejFaE@W!ptHDq>|j_o>MY)BIM=Xd=`618dl=Si zorQx1mUXphZ-?JCh8osQruYG!sd1%Y%`qeFfZ<&G7@WIV^(}5itq)9lla0~+I}Ln? z8Gj2IBk>c$V(m2J?;}^8INw8Vmnxf{n2M_&>myaRx$vqeav$g0nS~Qc^GUv;S?FR2 ztljyRW?>d%VSSo!Y8F1?AiF2u)>p_MYFMA;+xiMyvhCh{TVEl6reS@aZ|kdhW={;u z7iRot`s**`k2I_=&G=Dd4_k#tnf=O)^I{3pyof1#R=frWF~ee)ix`kE{{@S9VMe+V zR{8-qT`ZKf!U%^%JNOJIT>|cXru8ABTyztvHbAK)#`R(`14lrXoUTj!hG@nT0`fx^ zU#N?PA$qcefcz-EzaFM~?HY8k=u&*#tgFJtHLOKIlC07tK10lB34#Cr56N{zb43jC zIcW$Kb%lKg(bs+alO+UX#Omo1gtaC?#u|U&Nma)?8;uAuPG@Vd*bt}T*dicHM(L8; zh8V~a0>d!wNm>4DkazB1Kq3>Lh-w$el~PX@nxyq9CJ1{o~`zmCfUj~EhF|9zHk!< zN|TI@Y5I*=A3XmP-{=}Z3rz7@spyZ^_@ibh`@FQ6t-YasWDb@(Khq#g{8Vbsr-=uN z|EdXKq6cmMrU96!L*S?el!+fo1%EB&y-$CRKXRCBdJJQZi5QF#A*2b4bl$I@z<=;xJa9 zR+@MzjwJ=JqTMs|v-1_6LtA7#-LwBo#`DS8 z;eQ#sp2*nN6B#Ti-gYvcmS^n1PImJg+9G2g&+dUrv0-HF_rHwioyd5$C&rWU9WwUH zGfo!BobNfb#juU=>_IUwj>gTVxY$ebEVA(KSgZ>xUZMePO6Sn#Xblt@v7P|{mujG< z5qpgNzf1##Mr=8OF&aqVOG3IbRs(S(_C0~iHBiHdy^b?qjMD&Qyv||>#(OE{m}A5a zk#s_SfX%QGyNa$))HQ4)_C6h(qydZ==FkvNOh-Sxx7mwfUNPys{;W9J!`lNYywf~; z6N7Ob8E5<(-q;)hvowJHR?dmJC&v34Pkc!eUC25$AMa7LcZ=uHI7jeq&o02FL+o+l z3pAsiWlK(Eywek{P}#G{cvqhBONQ)z&!H_cuJP=lWW0po<;6Wd9!h@)n?1SodrL^L&2vc2S^2hS*F&Y)BlPUu z{A@_zB)~|%?uo7>sAiit^CP*7{rS*yNKJy>p1qI+2Z-;<6F8WoZ;|nf6MXxQU$+ zNr$$`=qBxJQ7PKz^gdWQlWI+aQkG(@c_O2o6f4NMojy8AwWfW_9v3AY+A`el#3!Zp zTwLNNC><_7ElqUB`D!G&gB2tw8ZN#oP-As)u@@^ z)tLB8)hJ4G|0qfD8cf)pnoEQ|$>AmV!&u>Xi3gCTlH4wuCb{OfOz`KiqMnyn z3lA!iT*f;l_+wa6rP_8*@JFvA>m`=K`7TK=%aarQ>8m(P)wnvzg>_1TKYA5|6?Scs zOXKt;*M#d6{OPN>O_ki3;7?!0?OuZG$m}Ff>A4C1^i?cVHEvBzVs5#Y=mwu|Px2I9 zn&6LK#UrZ5^2EKg|EQOE4nD0+@|1fgaSv-er~3bHfG1#dcNW z!vue`HRx?@n?q?oIHAtKv6R{za10>#GERzAA!A8P)wsPLQt?{Q0UV zQP@FsVYC=-$qO>a5FB%hfV?JpT9<^eh_Hl!vxX;RY0}S0gt>Qe(*6c;?3_kmZjzsS z*iYs5nH15Qm}-L>pzNglRJ*YSGN&e;H_?g&ZIX5)REoWN3h>Gk30fq@*(8u71lPTSmOSDe5NezD4@{sh3QQ zLdHljP=;A3PoQRM5PW8ey|>g2k7%1r%tY0InPQhx>PAPLnUp6=EmPjvh_1=ReW+C1 zOwsLXQ(f2(2PDUF8hpmFML=HiU#m+nj$>FtK$a}fB?X3<%@P96o2}8C0ZBjmiTDOH z_94KrUPA%f85Ljrm7Lh)BLFxWz`Mh*v4)!m@Ku6QP$2vn5idr(#t%oC$Q1J`-+PG_ zqZx-KM$w~SFT;`aK1P#88TvB|?wuS65#W#aWT=^bbCRWhY?4VpAXJR@$PNt=}m zGiuN;Wu{ifp&<@>gN%JG?!RIq=+{Y^W7mPPiwHE*0Dcy8>qP)g)_`loex%LD8o+(} zMgmPVfQy$M1Wwfeu2rreM^g=8*B(qO%`||Xb;ot5Xs!W7wb_LHNf25?>f z4z0A(0Iut=Ws}w#z<{)8lL`$mIzCZ1BUYf}-gPXimr?8gi_BDJ9L9~&X`itdV~L7g zPR5QIwI$)Kj*TPGNdt(^5<1aY1BlKw4D=ZqKy>C4=%N8c=Y4W?)m|YwGg+gX26#C6aUssTjj0=hm%11dTLGvYIJ+~XHZVo*k1SGHqjY{p^Scu_VvV;@Z+I;YXit262z z&#Ys_Vr0BV1GSA0^lr8BrV0TfH_co0L&^_`_*^amL}q;`CXOvCl)L*ec?y zGy$g1QJPq-0ZgAW>E;>@pbbpipAj=?BF@&!@+SH*vo7P%IJcK4GWH`hag=^Mr8f_R z=6XhRg9ZX}H+eK8-Y26hTc6)eR@3ye8HcvGB5cjrKajCI8Moz^6gwyv+|3zLSQ`Yt zT#d4q^GnJoMs$0|AvJsbZpN-grP%rO;Qf4`@Q^rqW^df_=sxnYDlOj3h!G_0!hpP; zDd96R?{_xbm2p^N6w%;B{Fhs5kOuZQ++e+|SovTFx4fG*UUZi?L* zu?wxeOK4?JrsQj8hBEU_#yNzHdRj+VnjDPByf`kR4}bj&#;04t%-DU>xS8NJMg9h( zAd|QlP(g~DzP>=JlaUuaX8y`3osk!^zWgOoCX=`hO)N9TT|Aw?GRmq-Wu|<{D{`5{ zqqrEBxZK;{!6kTZ+%KMFnGl@&Uu*OVrR&6#5JMfiCr>IH34~Ltd;8 zgL^XcS?p;zwg||Qsk$V9$2Ke>AU|aBVqIK>wTC4Hoc^39-)8(AJXvjvt`@`t0ahb` znGeDBKX4SK;JSd|I_5Q=r(pr0;JSd|x&naW+5>{?b@084N5ORg!F85-6kHb&Tz?ZZ zoT(68?^+i#m4fR6g6r1@tx`5!i z0;oXD7Y>lxUK-~9~4{{5L{OP_74iK3ka?&0Q(08*98RE6@dL?BdtJi zT>;oXD7Y>lxUK-~AJYjya9sh|KPb2^Ah@mo>>m_d7Z6-m0QL_Gt_ujRD*%t#D7Y>l zxUK+fC=^^55L{OPHk4N}P6C4K3c#xQ5djFUD*zh`1=j@x*A;*bg@Wq>g6j&vhVq&p z00h?+fDL6n78(J;bp>EUIm8+eTvq_*69v}=1lJXSIf2z4g6m^3RlGB?FbW8+v&xNm8VIf{pay>L z+o2mSxi#Qoc_skCbyWl3!BKEsKyY0FxCw%r5L_=Rhi4RA7Z6-$nKz8aAh^yBa8rWd zdUI5YQgB^BaJ>^?DY%Y18VIiUCjkZ51q9bw=Jjcc3xw|Y z15-e7eE|t5xGo^LE(s{OE+Dv0YM#mvT;D+g3a$$XuFEqQkC9@_D*!-nT>>U%4du=S z1lJ`H@X2!n!uid6y5tb=o2$1lQN%FgBRsgy1?W@oycI0D|jpqs*h=x`5z1%e;~8kb&SjsYw9A z^>1+)TS;OFuCtORfZ%#TeYBBf5L}l8quQe)1lLJT0tl`*Mx_`9*98REk0*fOI$ziI zD7Y>lxGo7=F?tYOCp8HmxPBQ4mYfD0g6qc0D|kJCIJN3e;`3AN(BVhk0*fOdSL?)P;gy9 za9t8ma9u!foz$Fr5L|DHO0j8efkSY8Bw!x}*Rg9raJ?T1D7Y>lxXv=KIbDU|I;rUa z1lL#MFh;?30m1dIfH?{=3a*R28o=5^!F2(_byWjP4F%T)1lJY7Q`Qs^Tz{1|DYz~m zxXv@}V|#exhE1lJXS#fyUL0)p!jfCZX>;Cf@U z_I|8H83fl^=2386KyaPLX##@l18L$1o(B+Imjo7iLBVwa!S&-AA-H}m85?sdLvUR( z4rJ6IxK3MSgy8x*GE#6|KyY0VAW#%s7Z6-Oo)LoUl-%~N>xeQ4u1iJ=t_ujR(-s*a zxc(g(%SiyibUCvB>@H31q9bg&B2G@`q`)y<6Dseg6ksz`?&B> za9u!fT>@NqD7Y>lxGsVG!UMte2{b{$bpgS3mU&Z7M+SoHG)^BOxPCiL9O?`lg6qfo z2*LHINI=1L0l{_YBL&w51lLJT0tl{KjX*Gi6BmN(njl8ObpgS33E(Y^7zNh_1lLs! z4AnMLL2z9GphH|BxPB7oJPNK02(Gitqu{!L;5xmbO$e^@v1*Kh>jHx7l7REe;K~ib z_2U^KxPA>8DYz~mxGotfxGo^LPFrMz;QBpe97P`?xUL9-(j^G4KTiS*t_ujRO9Bp& zfZ#f*NdUq1T_jk=K0$E(cmfEn|3!l9*$oJ;O9Be63ka^0ngkGBFU3H`#&E15xGo7o zC__*nxK5#AZy~oi2(C*43a$$Xu9KPs5L`c(1Qc8s5L`c=0D|k&NI=1L0l{@iK*4nZ z!F5uT0D|j_NN_u?KyY0WlxGo7OxGo^LPHGZBaD6ukD7Y>lxPCkV z1lP^RAh?~~hTys+=*me4!F5uT0D|kaP$@QugAc*=;|U=!D+Jdm$>KEzC?L2lS+A%@27>FPA^`-~ zpCrLuG!4P^;|UlxPCk<1lNP;r*~R4${@HdSt+lxPHt81=j@x z*N>T?;JSd|dRH`rN!e`(uD?kW6kHb&T$d&&xGo^LPUAEI!F7rk#J*?-9D?h|O!VYw z2f_7YCcdu*0KxU+O+awHDO!7Dc!deUb!mcv>jHx7G|uotaJ>_t+U!bg8lznZuFu3_ zjDqU|g6qfZwqt7ut{=1OpqYT+`tf!lxV{GUJPNK02(C-JIj(gOT&FRbfZ#d>vttxo z7Z6-OW?~{{rhwr3F%u`#2?(wqZvukr4rZ*kt`W*0xGqf$;JO0AbsDD$2(F)rN-+wq z3ka@DMsDw1tONwtkC~w0x`5!i0#slixITs^ia7-#xGqgla9u!foyHkG2(Hh>VQqG$ zHjU9P1lM1}VT^+70)p$3l{-tk8UO^>kJ+W*x`5#N@m+)9`hK+bD7Y>lxGwEx7$pd< z(-=)aaJ?LJB1XY=0m1cSCMdWrAh>?a#4OG|2(BM*Vo-&BCR%&FdD1{|U79FllpwfH zswD;2V-#E$5L`cI_f4K>5L`drE(F(KqTP91 z=ODN)?Y3f2Ah=FryrYER`ad*5!F2(__3Hu4CltF0KyY0FctXLTi|HDu1+VdZyh4=Y zl=oWF9|*3qvPZ#n0l{?|XD=YQJ`|N=eHlFnt}CZ;mA0=Mz-=19&GvTIfZ)2Sfz}8N z1lMQL1O?Xx1lMIR8uC1V;5v=d1O(STtdz0mIdBkMKW1V!TS0JL0Wd+qbpgS31t64X za0nr|t^iC|3a$$Xt}6hyV-#E$%QS$CYznRm2(GIdSk!)^-w<3^fbtuH>!-mbkAmw0 zg6k~vrn4mk*V!Zb4Z-z6^qYd~0)p#`KwZN?aD6%n=CH32T$cnCTo({rCpCu;g6nlL zlhp7*aQ(#LgW&p!!w1221>lhZ1=j@x*A;*VOcY!f5L{OP9xzdGT|jVM0eHYf!F91& z19-|1B>=&7RRa&0D7Y>lxUK*^U@9X3!F2`T0nqTsrK z;JO0vfN2{62(Bvt518I10Ks(y-~kf_*98RE6@Uj!Khp{X*A;-v?}I$wAh@moJPV@W zx`5!i0{B%F2MU7g3c&QF;JSd|x&knFD7Y>lxUK-q3<|Cb2(BvtGlPQb0)p!bz}|y% z1cK{bV9TT6x`5z1%RCCM3ka@rggFr)xIU5N_zfp81lRRMi0$Dj3&C{-_~j`9!F4{~ z@nmHPuFIK0!F2(_b=o2$1lOM?BL&w51lJ`21z~VbL2&&O5>RkmKyY0WJjKpHaGlg7 z__M;sk0kN+5SJDRu4{rA1=j@x*VS61T!P?w6Tlt?*98RECF2o}3Ix|_i;NIlKa-4& zNdUoh$%q|-E$JuDJqWHpjY_eTIdBkM9|@T6V8$r8E+DwB0L;L3JdYu`t^hpIq~N-M;JO0f#BQDm z5L{OPCLH$_0l{?zV6j?6S0K2q04!D%To({rR{*9Y1=j@x*A;*%`8jJqa9siL4o@K< zxX!K28$cf+xXv<+CaQ1;O>-*fR>Q3ka_3SaGxjHx7njrQMy9L2@1<)l^KyaNGPTr@St`J<8j1*iK5L~A%GD2{D z5g94CE+Dur3HbU(2l@`db;T$oBLvqslQGLO2(C-U!@Nj<;5u!Q5rXT7a2TcFx`5!i zBEatvD7Y>lxUMEdKr&ugDdLEjcPD*>;JRd_;JSd|I&F~=g6pTDlJXIP>yq)9j}Tl} zCWK^!;QDYfHmL>)1lJ{Fif1we*J+E45M1X?lkyRQ>xw}82*LH^eT3lp(`2OJx`5!i zWbDjI3&C~T;;sR~^(B}mF$%5=2(GK;3SUc5a9u!fT>;o6wz38U*A;+Gf`aP;g6j&v zCPBe<0l{?zV3VNWx`5!i0;o6D7Y>lxUK+f5)@n)5L{OPHi-iqcnGd5 z0DA%j*98RE6@Wc~;@kp)>k7d6M!|If!F2^h5nf9`aD5B<>0QS80>O2bc`tL(gWx*D z#9%;hy)Nv>D7Y>lxUL8gj06D)t}6h+py0ZI;JO0PcM7fx2(Bvt9iia5fZ)0Uilh?| zT<-$dqu{!L;5y5^`*8svAh=HV=mZ4UCmwSGg6oO^PEa0QKyY0FwIw42*Y73cPF`3; za9uKfNzC15`f^k0&pcj!F2(_bp_!0 z4Y~%w^}o;y?+NZe5L{=ON5ORg!F6_;U4`KKQe5lCD7Y>lxULA$)$v>tAh@moTsvP) z0D|iZKv$Qs2?W;_fb)ui>msfJ%q&`JW)gtlx&mqs9E}Clq z<4D1E0l{@u1G^;!*98RE6@bl=g6jf;>k6>sI6`op`jQ?6*98RES?1N_fJ1PdBg{P< zg6s8gJr?8B3<1G)wN=9J*9kyyT>)(@rg6jf; z>ylsrPk0EflbQq&T%S?R2~Q6oxUM|FSWs|XKyY0FaGHYaVxk5xIJ@b~Bn{xog@Wti zN)6!3g@Ws1vIcPFLcw(b!F5H7j(6a!f#A9VRL3E>z8Wrh6kHb&TxXd_!F2(_b@qsU zLvXzk z0KX}?F6L+eep7H=KyY2vP<}&j{Q|h;QE**AaGhn|d`1m|>+BKzhT!@p`aPTDFkchE zZwju9yEOp6Kc(OIXaIgwa9u3W0Q{!lx`5!i_M5W?g6m(>iHWoe!FA~b1=j@x*XbUe zfZ%#_u*WF4E>>y+I1%RDU!?&!LBVwa!F6Q1Y7K?4}D?+84j0Sp)g*98RE6)9YT-w<4n;kwVG;JSd|I?KGj*+B@dvq$tBg6qps zDMrC{TzdTLHwD+lRt>=K_c`1DqXGE+1f783y0QtsDYz~mxUK;BJqbqwg6j%^-wQ|z z!F2_|?~6DhuW3N}4Z-zS=yylXeF(0zvbU6X_7GfWkLWi9*BfA&iBWJ}KyY0#BHk2S z7awW>e(z_zcW3~9Q*d4E)ByaZ;JVnQ0ly3$1lPNR-y6xeKyY0;LBVwa!F9SvCm^`K zh)(bkynx{PF()XvF22$LoS@*k*rx$FLBVwa!FAO{O*9CuZ>CKOt_ujROPllPEda9siD_<5Yfzi0phM!|LQ zs|GM&6kHd-X#fLO$(7-E4ZtN#GzhLw2B$X?VG$5qC%;F*bpgS3_K1E%aNWU0t@0a! z>&giXnDiTh>k80*LvURI+Hd^mKmpos2(BwY`whW$1!%t^xUK;0Hw4!ep!|m5dQ-UM zQE**AaGhly1=j@x*V!Zb4Z-y>^qYd~0)p#`0DiY)tRT3q0QkL!7q<{xSAbuJ27>GJ zXyPieLU5gB9tGD01lMVtCLp-JnI;x8wh&xDW?~-CFbJ+I0F@DJ2(IrVV-TQ#;JRd_ z;JSd|I&F~=g6rlPV7!`h0)p$309!K&Ah=#1WnL>z4+ySHg2P;;Ah=Fy5}^`3a*Pz8c@A};QBf`(Tkyg;JS2z zg6jf;>vWG!KydvPIzhp80l{_c1bYF&_3ub9m;?}9mjrt_Mi5*lH3=ZNp6vnx3a$$X zt}6n#R7wDX>k@z_bu3952(GIdm@hRMogo@fPD610LeTvm_TD@?s-kQA?x~VK=_DPJ z7?M7nPSOMjLU+Q{%n-sn&oYT9$RvY+D4>Xdh=7PVpg5o)h^XK^fFt5OB8q@Gp`aqS zpa`O(;(J|HXD8ua>t5geJ?s7FU5~D1==xRFu3c68)EWA8T_FmtD+sRZHYvESAh=F% z*d_$mxq(KIg6j%`>!t}a^blNMO9K>KR}fs+1}M0$Ah=G`GyuW%_i3O9U4r1caS1+B zWn4jU-2k_qObD(Yr$q{`D+sP@i-$Ol5L{voUu4{miphXC-bK{`U z8-NOe>)PV=h-U@Cb+*Mq5M1Yrtr0pJp=~w;!Sw}z=@eX75L`D_5$qHKydwjG#6^jFoNJZ^Fm!X+z?#X zuie5Y2(IV!5T78pZVZS|5L`Dve0oiQ_yoaqT|#_<;JT^d_yoaqlQup(9g6qaWvL09nuFs)?i@1o3p%1=ke>*O?ch;JSj~I!)661lK>Ifom8j5L~bB0R-1i z(*On66$IC{2NYaa5L~Be8i3&Xl%6m^!F2_}buke9jd2LUbptT0U$K)ATsHs*%R-ib z;JN{rY6`9^2(BA|afRTzg5bJIqdmkM1lMmydm#$0D+sPLFGRt01;KT?OQ#^XzKu>% za9u%g-59`JQ*d2DaNU3;Z4rX&-_Rlj*A)cUwZ%7hB8T8Q+hVg2Tt9`65%x7g+iV7c z>p8v93`Nxy1lP4y=cE9^^;XCW={yLoYpWDoR}fsMDH?#_`d}KM;JSj~x^c_QKLpq3 z&;SM36$IC{fmi7k1lMVr1|Yb;iUvmUsDa>mbpsGwe}M+xq5%l5YXe)kz~j71=ke>*R=ts3lLmCO#|b(`ay7A8=&C2g5Ww$(*Ok5L%m_3bpvn+u2=T}g6r*& z7n;jahv2$4K*4nd!F8IZ0SK-SrvVDCD+sP@1AgRT)FHS&j|M)%C69vOx;D_BV*tT* znx+8=u5YFR3a%>%t{V>!Uld$d5M0;5V=O{&{X<$D8ABcf*R@3ot}6(xvn^VL;Ce0AiYg>k5MF=D0IgC=gt4irOIxt}6(x>n85uISGR6Y@AI% zaJ?U!py0ZK;JP%yUPEx5I~9f2vNZ^*A2kjeZ%fT zaNPh*9-M&S`f@t)NjdT$xX!%LyPS0huG2j_0m1d7bmB3tM-W^$1~7Mn7=#d9Hvmq! zIJ^*CHvmpha9u%g-2ga2!F2_}bpwnO5M0mdhjuBrt{}M1ywI&22?(y!Jvsrw^-EAF zNWpal!F6K*PEc@NL2%sw1kfhdgy6aXaN=`L5d_x_fD;s4R}fq`z&HWH^;L9&g6j%` z>&y#La9u%go$k>I2(Is@6MX+leJlpx1O?X>1lNs4I6=X61;KR#lpbsduK&R%hBibV z1lM&F6kJyjTxa8K0)p$@crLh&79qH944?@Lt}6(x8-OM#xUL|$ZU9FAS;hne*9}0& zDY&j6xNZPC{vvHaaNPjYaR{#8hz3J@*(V6DGcWWihYW)2^p{>iaNRQiUQuveL2%s| zfL9b;R}fq`0A5jWT|sc&0C+{gbp^q71K=y@KHS7fZ+O4HbKF4 z1;KUZg($eLAh^!P*#rdF|6mh$vf~h3HwMteL>7eLx&df{g6j%`>jt3X6kJyjTsHt6 zr{KDR;JN|m_z~W8Kycjv({Tu{7Y>9Y6kJyjTxVWrFik;lo&M4*2(GtApPR$9=zF%j#Xs{Y3QRjiQ1cHgc>GhN9Fg6qwO%g?wVxc*rR>f5IZv6-6L zCjx@&lYr9AJ`oUH--8kvHhT=5GM%n_VOzxV{AW4Q#%}UuN@F{DwB)r*CBTm4M(n>o+$0NjVVX>03veuQzwK`37=#v-bo9*J-VX&6kRMnq4O#xK7r~>^cF# zbz16e^A+H}X4eS_uCqixn=kS9xA`XS0J8%H1lK=Iak&PXy(b{J&T{A5eAV^>oA1kx zGW$?KaGg1$%?=b0TyKC{7utLwc9PA7Z?esoNT=9*S@U9>??z6w`JUr6vr7d8*Xh-C zo3Ad;u=(=dr8Zy0yUgaRXftiTwKdD;8(6c=9u^Q>XN}9v9u^Q>e-ACrvH1ekVzX}r z1lKuA%gl}y5L{<@?4^O|y~*rY0l{^8eY4FMmTs~6`p?R&+e4TY2(GjAtv282S(SAy z;~0YLWOvzoJLGPgZ*<&a^Rk5MF+~Iqj&37g4%c9`A zg5dfJ_`1R7>kkiRQE**BaGiA@%IeG%1lKpA)+U>;Gi=MUSqp;eY<+uHL#80O{w8d^ zYV);#4{Uz7zcY)1>k5MFEcap7bfzG<{tC+NviV*8ew*K~e`WJK@vm)uk9{DEg6j%` z>pgL}9SrlE=xs)DT|sc2!}qE;%&%nM^oIE*=4!F77{r#H-Rc20Z4{BFhN3-kLAw=X=u9B*m(!u(Re>kIQ4yU!QqQ*H=l z@xgPFFU;q-$-Xcji~4vgPOiD@4_9ybp^q7 z*39#Td50bHg?Ur!2(Bv#t}`?23-h)z-xuc1VZ;~aEuJH|t{}MnW+4_TUzm42IkkY2(HttBe=4!FAGSd|_U+Zt;bA*|^mg z=7rm{zA!JHp7VuydGow4%l<5nNXgT&J~{jo`Y1;5xg# z-3YEL2(DirKur6>Jdxp6RsROH3r0=<#`S63Ug5KkK<8W_IcfMJkvRkb3a%>%uJf#g zub#sd)-Ay4oqBh`4Pu4!oo4}KP32aot;h>4=Qkmt3iF+3HZKqhD+05SLj!dytX(wF z8TIR(S-)0=`knPld2LeLssD04BAlC2H8~Z$!pXor$3UxURw7}7(S~~{%@&cfuB0$qL(5=E+ zNduixzsH&NJ5{J>S^r)fiK>fJ|1^$Z)vF>v%d9`J!upu?JD~nKXLg`(g*wIhzc)aY z{!aa?m>5zKpk>y-pu)--f%<*g<2l9XGaWd$LbXC(D7`-FoaY$u;4GuYR0L?61}0Tl z<4`E5zZITRWgxxBU_8Ne(#g4cNXJ*GWi;sHh4V#@!L_{AnpP2DQ?5+EN99yl-{P~) z$Z*-5UZ2fL@|(S{npb3p}bKuKuj$TKbW6;%H-wdnB`UBN_hS@KdCrs~r9ut%& z@mYuKBwVMH69npTOfISL(l%CmVk*!~f2&@$>p#jjHv6V}X*x z$E6XgRr>uPeyv~V*ZPHiqhIK4`6(9fa_<6GF#3h`%Ic85mlgIMqgPtL&~Nk$z0@zX zx_X~r1*2c6EA&W@jYLtcU+CBRg?_DH=-2v%{(JVZV?Td~G4XrwH_5N{3;jmF&`bS7 z>m2Vv8a4Wb)9A&}^z&)-^CL_&{SAM&S^H7cHP7Wu`Vs6rZwnMiHu{Cyj|Am z=r{U>Ug{TGW4x1)QKuw&C2M<>fi50?&W7O!&O8PL+c8i@VmS(Fg3?p4_UP+VrX5RUZ_P3twkBv zv#u7>UYx~wa24&k9VM1zF@sI7!oP}%Vz2*mQFqc#N%tyP)a54lDW1r4p+bxvl{ z+Xs-iL+51S6;Q2{Q6~o5b@>PW-44@=pQFAg{(4vKM}<4R_Yt=RDAc-!*4-H;qu|{9 zH<9~5W`BHk6;apFdN%ViBz#5GHMHKyT#1Cgh`NT>Cz-Dzky=DuL+fDX_ef+EQP_JGnyp$nK>FnKzLWLc^#u*}|TgKZs zPKqc)n9{?Zg?3y;tFK3*r_Cwz72S)2Ev1*v@fT5sFr~Lnq!v+zFr|-9WE4?`Fr}|f zWEW9}Fr}YPZ5A`j2!A=p|U;wk6m^LQ_Jc_~AfGQ#^MD&ph8W zDFgc>#c1N}04shQVx4-Mu>oe_Xl^ce{fXGEGVn`uD9W!`>vBhZ3(=w)fMkQ+um^F_ ztk^+pQy8d7$>d?Q208JhHOQ$*>AeAoQc8yfI;I4fTeg>`yQb8n6~qH)PO(bEA#6W2 zCGALM{nV5SZA|OJrlt(xnp(EvFIY}bvAI^2DO}43GE?+`xf(U1=_jqEwqudCiRPZM z^g>#uEj(-KRk>6vzCLdSxk8p{M_;rG*-&HS>AO}9c!jHTX5J+=RhS+7r0 zPcC4_|9(l;{J+#`O#8pmgY3=q zz5wU2^LUQJE{x^%zV=+&<2<7VmiyXsVT$wg9Js;Po(oi*$6jECuRRwk6Bal5bXd5W zq~qik7-mdfRcUgVuMtg}vgewzrmq+Hw3n_X+vrORQ}Ln7iY_-p&D*rfp;KP%ym9Dnuj9~MhTwKnadc(H z?cNUBp;qkYE8Y%V)Z?=lFRyw#aB(-yzh2$sJ7RJor}|D~@`g&2cY3Q0&T3Q9)ucE5 zo^Hy%Sy^_vw{4Z*GpaXonKV+u!D($O+80TOTYFn;zoEJ23bgUI)^XTsKSs5!Nf^J& ztDCG4ld1H@YfMh5H0kv=(1#~CrXd*_L%1Nk#&!!S=EuX#?!3o$Xe@Z#v{x4 zvd&X&rq_G)OgAnYzz#g)$)fGXWt8>`Z1L2j3H%q;npRC}aTTa(e7L#NhngNeb>`@< z>FK3?&k73kROwLf-(L-V0uuSLtWl{KjNp}&`2tM!5Mk-t~ffwIfriwBB1 z-1hjjl`_4&oiqtoESu4BuQB;UrOA8!-Ly#^!|VLrbjNiJuQ!RZ5gdgLe!bQi`wvvN z|CHE&k_X~6a}usSnH{Ig)2g3@FR6YKp6Q%~V|Q}ITA1_FO_dc}B$sQ)^m(a8_487T z>gT0a)z3@i&UuM9Zh`jIPf{b~B<1EPOfrl7JC%)1Qe8ISjAFVs#aZO_@XdAB_1L`} zhEArUZ;EuUQ}we$m+BSIaVj=!#i_i+pVoqv&gURq;%}=%N{{&^{sB6n$NUoicpbH| z>v(wfvh@7VuWYTC)mM*6%;a9cvSn|)jn4M5^c9VBqz$&Rv>8{d7Nb4ec>M2?c`nqz^;%{>PUiA&t-O%2= z>YJin(-&K>`;2R)6L2v3#IXf*EZI!@fJ&3e$=$R`J%P!|!>UXsCts|)6g$ZdbTwf- z9Tm+LT~EKcqKi$XGbJYb#>(sllKm<>dD1ldc4f0CliP4yO|Sh=5@SF)nS7HvP-@hZ54{TyE(u~)F{vB-&W5`|2_rZ1l z_MG!7Gq$&6MvG@3!~Mwit~A$zmkj>xLutU({0%Ht{)cm}uB`BIb5^LAe;S1z*9WYt z`3}sne|64Xm4#L}GtGTYUzX;)T$!=7ZB^~%PVM$=;^Lg2D+^uRq{^p@E2@0Dc!2R~ z1+5OrsfkB7rguY{@gmjuG|I91*duVTb52=hq0R{way2hvbBUZml^Kavx;fqLL>Jve zOaIw;bo978C-w{mIw|4~(Tnw{5`VZoaw6^ye3(`?sRTQ?Qjx-F@#n+k2+Rl6a<`{5jPhfh<#-bKU&!4Kgb{s~{Ey0ym$3wIzqInB z;-`O;e_X{9SF*$s{^6(pLjG|xi}gsKkKy=7{_!9A$1eDi`XBknf8-zkk$?P0{_+1s z`Nt=5I!j(#i1VMwKOVrD?f;_u<8qi&v}xoYH{q(GQvQ*r+%x1KHAt?Kf7I#f@{a~o z%0KEPeh4G-k2>wClz%kYmGX}!StOH!u zb2uP}s-S*-j^=V%i1Lrj)TM$c4y`W#xDO+kgG)dcU&Ydfq2d_EXCHyiq5P80fiz=+ zIRyHTZj3MSh)09)S-W|;Kqx12dva~)27ypcyb7Ov1Ulyd$$@g>?aU$2IeafkTZeMu z6U-sNTZYhup?2f{ToB6jIlht)$@Cj#XZmeN?n*Q z(eb>i@k~HDx-fa73&U~a=s*`{Z#qWjf1@tUU+8#VbzPV|(S_l-;Y3JXn3^>(I_>!V z8gyZn0P9`zL>I;Y?EE3RFa}`fk6Ijc=)xF)oj+m((1kGoJAX7IfG&&y*!iP90d!#u zz|J3{3u6Fw{^-FH(1kGoJAW+Z>H}RE1F-Xl=)xF)oj*hu#sKX6A-XUIVCN6fg)yL- zE{p-ybYTprrVC>LcF-74KcEX^0Cvz2T^Iwf^M~ld7=SG`HjG0R=)xF)Ej7})LP8hD zfNHuh22|69F#zwp^ZP&Q!We*e-bEM20KD@qx-bUdop;fNF#zwpi!O`-_{FH`!We*G zwTdo`0SE!SdSpJOE)4VXL>GpE#qfbH%;gLp(Si?t*(+GKa z)pcR=CU7F53q#ZFHFROlqXE%{(S53>3uF2iL>~*O3v)FMiY^SV0P=ogAV3#}Ij$Tw zcr*Ujr&Q5}`2e6&7v_uxzL97^REjQ)X%Ux$A)^a(61DS07bYnSiBW74x-bDG%(V!y zZW6jMET2Ok>?-K!!c5BsF3cjJj4)67E=M@;|5F!c4XXGc`GQ5c@IUIpP_D5U zk}p`B{CzV-A7N zc}j9133DHF2r4CEIB$r|pXyq_;;E;RY5BRXvuxma)G{r{1>ksGm5X>dAppy{mTCD# z0G4wt({fS(mh;W5@~Z$W=US%aHvw4AwM@(J0u$*g|mJ9({&b3TSrT~#?$rd0oEja>2rX^PZ*7r{e(c6#!tnXT;B`g5zyOwE* z2*CQTWm*aaV0~YS<6cDtV0}O01t=DP^jBVXej{kbg2SpB>?esB|#ejh^K1^+6h2BT~E+n z0ODySK?ebdr_}_V1R$R7Bj_Rk@wAzsn*hYqQv^K(Af8?z=p_L0^k5P|9|4G`#|iog zKs-H5FhBq|cq14j0P*xT!C(Q1rw<8+3P3#VBN#3K@$@yp2my$v!vrG*AfA3ExIh5n z=_3Z%XaR_)PYK2dF!5BsL`}l%)+H0f?tR2rdzaU0f?vB1h)u4Jk2M# zRRH2?3Bf7>h^HF~?ht@@x}D%I0f?uy1a}KSJUu|LMgZbz1C4+l8ZI6fn#uLG#0vJyOj|pHr5j-w{ z@kH>10LBx+lL8n|VSuLuFrEmW7QlESct!x@iC~KW#M8YzxV8#FJPpKkfqG5=;%Njf zDb#xc5KqY#zzzY3r%5caQvl*A$Pyn3Ks?Q6iH`*!p5_zm5rBBAAoxT8;%Pa-rvea9 zw-S6V0P%D;!IuIMPaooJrM?n?c-lvBK!Ay-2TD{bR-?QN7*7v5@$@$fep3=)q%oe3 zmZUW+L_BTdwEa|4Xs)XfPj3($6M%SnpWtT!h^LPUjtf9MeMWFX0OIKY!7l<3PlpLk z3P3y^BluMS;^{Yn-vl6@{wDZc0OF|*hy0WP#MAp&YSo_t5Kp@aP76RheL>)==X4J7 zw1ETa5rBAlj=(1X@$>;fk^schU$o&DfOt~8I7|_Mc>0c2QUxHMzGaDY0f?ug1Q`Ml zPbUd71t6YI6J!fOJSFk`pCbVAlunQ<0P(c(EP#*z#M8~V%vWInh^LoWA|e3s6r+to z0f?teb}lLa@f0E`7GUD(aEWy;LM3lMPjNq(Sj)SIS6+4M1sQ3))r{3kd!F&Ms0h5Y zUg0=ky{Yyx7AzBh@tcXe1l3Rg#;-2cHPu)E`mQ(RY~lbsp5}&}_3Bw)!G7M$xEE9P z>*?J)^JX(fn$`=_JznV@Dp4o#F`tp0Pj_5t+3Ijzi&}g(Zx>uPFYzU z70P9}0yopo=JmWZfSd8@v9t$KE4@Px{Mc+pte_JryFE$RWx6j;y-pgt1O!t*L%quc z;ERvGy>RB0G`{(uGUY5u{b0Mn~GV%7+>Ut>TAbl@(h z>+@To?TxV@-KUd}#L_;mbn-FBK&6w9i$!tr2?36iPfFTx@+nD+lTQl}C!Y~uoO~!| zd5SSV?lcU+X2;37oS!YRAl>Kutct0cD3s6P%%{8bd|S+F446K!Bf7W!%=vjfriLJ| zhR%D@nV(Ix`bsQ7Q#9~yEbU+T7#zr^-xs&I+c{Kt)Q*@Vt%3;~yc>h|fdG7I*tZkf z+$mKs7M%$`6o54gdrad@D*$WO#UI1QE&*7xt|RzZfa&O)F)O1sr)&Vsz3q%f<`*cq zI~HV*==bNbv>Q<SL+ZUVbe=ygVR4ygVpCy!=K0=d5FA{OnQyyj;S5d?&zo z`AN)r8V=-r!?69-@iNE*>`*L7|LNtAv9xY=WOR>-0U6!nu}F86bGv19fBE;(Jtjt>#jSdE zF(eh_!MNFBgqt(oUIUs0Q2%2OEeZ>{Eoy`QVINC%Dh6y?>D%bHjM|^Bl_JsZbeZjSjfR^>lpAVJ!j41 zxYvh)yXjy{$3R^+T^HP8Mg+VjYDYwwz*JOiI3=3E4DOG0IypH;Lx8hfI&!83j|gYgaa7)k7fb?{VSO!bWi~*I zI`56R&AhykZ1LTAkoIWcqj=iQC=~3#4H>cjibuNxbE=G& zM+7)t{v>Jf@|Xbe@@E0!<#7Sx0~eHYhf+`O-uI2q5P|Mc>& zc#X^HWovr*w`0JW{@>$i_t3y@*7?IR@Cf6?SDHoBoQwl;>uG$n*;kiMTYCCmiQ|e1 zlg^pW=WONE6kALywSK_IV0$hx!BTS?bXv4ZaUMjAIxkRaPGPsPU`Ah!C&^>m$Ua3{H6iZlV+;h|~)rY^naeSHQt(XAZI9|(&aRIn-{GBCA1>nZ}CYEUE z03Yro!;I_30@x46SyKV@(xYmZs@8CzMrU5$*Dcjr4|z6Yuz6{K{?p5LrPdgFi6ZSw z^}*y(0bDaf%1M%5ZLL+Qq5x@)&b+v3Q(AKp>gNriwH~DbwnJEEe%#pgnJnhYK)G^e$CL*hEiW-1c>vI5iptN0tWIIGY$-YFT*MKRBH|9`E!R zhc3;WTtt>B$y=t zrIwmfmQ4h61mKL>fc?Bu0K%shLvyYGc!2PkQmQ_N2YIiv3sar&Ig9RGRT^Li z=;oqQi`t9n?YSB4V#fe3XVTku$1X2R#3GLU_5)F3sg%HNRC_8&T_+_>n+r-6_YlkL z#by>dZGOrV$+FS_ysqCN`H^ zy&7R$DmvrJ;1Mx^WBV!k@~8l`*`Hl~%mE%8B$y^UJwK5)-zlYUXnJs><+}`$u`Y8_(}3)sZljsfQq>eW(}(^&i17~6QtK(Tl4Vlo{AAC+1I zQ7Gu)xO`k?AXq`LTL1>?E)LXQ0X!DnYDcM>%_jPC@!07!(V{JU+*cZ4XQtL3A z=){;fAO8?EnuktWOAlS4Zj9F9P7z&2-|V0C@E!!LI_~ z)pLyO-vk)1j+CnV=+%IM@ao4>b8q*>5Af<#X@LIHD|eZd(-dAUqgURts(ZU2$I2%F zUOmpCQ3BxAOtzUM0A9Vt63GJKmCdp83ou^&RjOK{!Ms;l_-|*dW-^gd7NEcMDznUb zpI+s&iEJ@|8C=eSX9<8;D+zK0z^i(!Qd0oDDkI1h0IyDQ@bUy;b!^5GApuw&C$sOi z0Jwz6OD|K$>Gwhw&L}fy_)}~>Toz!D=y#nmYf%Dz58(`!hynOLlAxXd_&t{3Yyt3l zGC_R-@OuV90|D^+3WAsb_`QH2E&zTnAt)7K{En8Xhu~6P1zjz6{Qi+4S5_8akLY*v zGV2Zc-2(@yYAFWH3frVi{eZk00~y>2$H3SFDA>9zK+`nPq0BnF84NtnvF+p-;N!R* zY_^M7M7K`R$F2^*kMcOS?aEXi)UGj*&tKa+O^l+C-OB=O+?CcuT@Wlmud4tEz9PWQnt-2ksO;>5VafidVZPZpYY*S?Ogb=m4BGlE_)4;FU{Ix&W${L*p3TrdJL@?P zRK&3QS^bzQFsTMv*YId9G^v=)kc($+V9+))tkmXomf4(>hFPgB-P7bW$~wer%U&kc z*cIr{rhAupIRVZNWf7n6d5pBPO<4{<@5BGjJ6#3bUCgQ%d>g26$cGr{F6qf7J7xcz zr0(f?EimGxAE7V)?fC2VZ~uU{+u|?w&-oQ+l%&z#qo|%d{N2iGzlI)QD+N|}1tn+*fCd`Zt+pW#FCP!7=cD2K!C@p+2-(AaCm z?5Er9_2?bBlHLl_H@Dm4DQ-yb->t>YxjimV@dSFZQ|fz*n{GjRS3c(h#l6Mcej;g4 zKBpDsy{5CrXh<{Gsxwk{oftuq`DmA(%7l}hUk?tz-ox|d^qWGttH_pC(?`7*nLA2;k zI+Af6a-!VKBKOf){ebMwKS=WtdVFXsgpaCx}Disg&dr|CNDROyObpjb7!8_ zhTD&Eo3f-)Ca=(S_IxbMlToSuCHylNf6&8kF_73zpC4DVgR}HUx~t36Ia6MbPl<1d zS&6*+Xs`Al-CGiq`&@Ci8#cSTy_JBdPp zV$Q^9w^u8r+Tab=VOCR<#=0}cB9)c22KnRNVfM$B#T_$}Cb+}wk}qpF=l>#im<9bX zSb~28(>Zz*-QE}yY7+h=zko$1*|!<>liQ_l0!i74_*k>Z?MgWc3-dxru9R<3tGptJ z&=`hK$sN6OSu-8;X`&*zOZpxVe{;rzKhCwq<(-I#PwwH}f(*snMdk0h|ny&-eDn=c2W+QIb45 zqjx*h8~hdOjSb^aM&fN+9~b8M_@bE{gz@1kk>QU{#uOz_2(yQ&F>ddde37n`7Ink( z^hlxo#5sZFDYm;>%BiexmrszbC=u9T2714q0=x`>c>qKsp+aV=insyO# z!e$&U(?@NgK7^BJ>qIf;c{V(Wk3_Nh`~$#|Q~X@w8;HN&)|{Bjy-SIw0u;W36I=4U z^rAwXISZ4o&iEV94BHKv^~%}({ZFFG>dYZX_@dlEFnN2tjh?%sF%4Z1hpNYmg;fs!EohCY=T;5I0 zYU=%t?Tkn8m;0M%JYRu!xFq;nMmT&f9k>2g5yq`g$F0A0L?5?$vi)szPHJ=wjkS%i zeufTWe|eBWoUMb{-(Dxq(n0L6(21Pr?X1%&$Z^k&j@p4l=OEh&M^EDD_IJ^V!st%s zbk&LCXfC_ZU3Z}*dJt=kzlToLi;iHio;q=M^cW5F(uw-fcbU^$CmQIe^!Lr0jX{q^ zS23rbPQ+u}$IjnhCrYEAazqE{L|L>H)8Zef6AhzVa3uH#=|rPwCr-&ZI?-4kZT_M9 zXloMXeq;V&Q656g^`YkvQ_R+}~xtz);FVxeXu3jHh%}Y3HIuBc2kF=s5}r__rNp6f+v$11D4Jsk8-^ zrRrgyOqOc+0S)}_OM9>~>vx~dYTO%p&!qg}(*y2mxQOMJ`O-eDEVs zFDVy$3mAuulh&Y%Q@sW3maFNlEH}uTG_JDTxz)>!aLP5ji_ZJJX$vZw@_DuMu7*=M zs@pwj&s1h@_jIDajd=VZXA+mC#)~jdDX)4WEQX=w3^#nAt#9z8?X9f3!DB|XX$h^K z=Sd3TUd2qyd7gx}st4gb&)_@^LSt@|m~y_Skjr#qZj+dDp-0D>tJyJ5S)nIWU&v@H zI2HiPxl}fKatjhgp7H@qOnefFsHdE3S))GLs8`EV&R8;|Roi1mtN9k1Jme10$-A~zJs(w{jb%(p9_J(_=A@^LagvQQJW5?Be zG0qVwYfQx^ojDln#u|4gU6CiYl(p_oTxJ{b1fO!RyAzk&MtYCUb?#1Fc8$sV#N=Z% zIoFuHw$kKWcL!~fC+L)`+#U2_@C2PQ&)tCwys@&tSV?e|NLlC(ax7fU6^^!)F~;N* zl_tkjADMB|{5Y2FY|18eksft6WgGGOJ*A5~Q8h7L-3jdr7patP?gYIY!4r5^V8w854- zu-`kMaos9u4UF&5lio_l_&y!tP5>m~%Uq0)%hj4&GFdxvdFA^$?6uMR7w>5EV=^+^ za!V#_d(N+w8QWVjqb0XwvbJ}niI$vQYx__daJA)bOV;X~jILs7bu(j$yDeEubDCCW zEN#n-R@|$}TCVT!Ty44Al67&;*vdi|H>qmw;)<%~E*@Z-<8DjVkeur(D-3DI#l%=0 zCs@eUmb)!kiJZ48GZL+IbGk=~F1m?k+#V@_?U7jJ5K1=Y_DBJ2 zkHifFTZacLbgWMz<=`n6rYcaB3b{8;JAK8udUP-UGQ+0N^Y@@`K z$-*{DI?FX`Ezat$;wJcOwoz)7XSPx5a}zInldJ&#@u>U5_{XQ7PQyQb^%(x~ZiScb zcrMQ=Rof`xkw!9Vc&A`Q+zs<4G4mY!QKRtZ-!@NL&df`gc@_Wg(|@sf(mEFFkv|7@Pr<)6)y2Dx1SY@YPb=1Ko-p7j6X=1C9Ybe6of5a&PHJn0jh+5RtXp0p6= z6m6Q#lkUYeMdjv6JmsFTd6EXzHc!&&>YFDSP`P=MPP*~tQn!IF-_`DPovzwE$zziKYn)s+UI_2t@-31izAGQ*@?9%QyvESm0=pHstdJBoF&6D0os%rBj=2dN;#JsA_lXShR&69M+s?C#h&8p3l zbk(ZOlXTsx&69N9s?C#h-Kx!#bls}WlYXSXRhuWBK(gBANxWEcVe=&ZOFK1rMTE_h z*yS7!$QM;m?`K4Fxh(V}Hcw)vE~Qc&T7C1R4={o`3sE$RTx}TNU1j34k3j#?+3h9U zi}#b5L!fi`J7ir^;RPY)5a>U7_tZwHM{3Z;oN@TGNQ$D3%UFs)8(AYc*q~_za|r%_ z{n6jWenbaa|s?2fY;v^5j-pa@BA$% zcuWA^`MZ_iNdb80?|Fh}1mMSZ&G!O4D*!*XdzB?#5P)~;-X+*30Ivy_v&t(1@OH#5 zmUvwN-WvFf;4J}oJK`Y0y8`eU!4CvG1mNw669gX$z}pewZvj3QfVU%x3HAy=s34v$ zwbcTIO6Vre$V?}mKKlWQPwfCBjq&ugZEZ&Q1xMjlT^$qyh^Gkz-w8lGO(i%i0P!@F z;D`Xk(_Dg|1R$QSAvi7o@wANKqyWUz%>=&-Ks?<+@TUO8(^`VR1t6YUdPHX|fOr~8kS+l6bOAvP0f?sw1la-*Ptyo$3P3!~CI|^YJk2M_ z7l3$LK~N|F@wAGdmH@=l8iG0k5KkKk>IpzRJxb6(0ODy2L8$=5(>8)e0uWDc5;PTn zc=~{#xd6n|UV>Hv5KsC00on>cJk=&>FTljp7qrgq%od) zgss0a5l?Hs0Phtx3!EGAbU#6F0f?u~1bqY`o}M7+D**Adm7t#h#M4Uz{RJSNULzPF z0P*w=!9W3sr=0|Y1R$RF5S$|b@$?E0oxuVSPj3?p5rBBwNib9Z;%P6zFae0CFA0VV zKs052qyWUz^IS^K7l3%G#S_m30uWDU6O0mocxp&6 zS^(myIl+Yj5Krw0#t1+>btV`q0P)m|V4MKN(?Ejp0uWEb2_^_YJY|0ZaFGDS(*%~7 zC;;&^m0*$p6Hi^jDw>6O8h;3R-NH4m0uIgEkHq9~fRV;{nh~~kXCt1nzXrcd0uu4$ zBA6)v@zj!FmH@<4KEZ4Oh^MgxmkU5VjUc!}0ODx_!5jgIryB^a6o7d8lm5*WfOtAV zFi!yDsofs{3j`pZnh`7%fOx9)Bfug7h$ow1u>i!Ai)a0%0vJ#9W0?TN)4-nrmJ2{U z4JWuk0ODyB!3qJ0rwIf%3P3zfCAdid;%O$q%>ocla|vz{fOxuwV5I=W(~QpmZWDkx z!-;2VSp9)H3oYV8F+FT9WHNZ%tqKP?<($}i!qy`>nAn*=fv*(XU}D!1yeI$@`yjzf0x+?U5o{BHi472J7hop#&am2rISVbp z7q4oyGqF!IBwh&zIOUw!x5L(hxtQ2eUTM551~9R82;LKbi5*Swz5q<@FoGQdFtN`O zd>{Z5`#8Z)0hrj22tE{miG7>kBLSG$R4z`t1Ylx)1iJ-bVmtp1uvY*kwk^Rv0hri2 zM*uz(fQgL|d?5f6JB~BGUjQa{B*E7LFtOc_0~{29iJko^z&8RgvGWMN6@ZED$12|m zz{CzAI3xfQJCfjg0hrja1cwD+VkZ;)O8_R;=Do-d4#2M)g7vxj9F-DS-`9=>wDzA=}i40+CC8uFeo_ne}t{8Lzw#edA<6V7{JuuO>kNOre5)6_qPB{ z{huu1%6G2nF!fDY!Yu$(-+;g)08>Acz$*Y#KbF8J08{@U2NaiNJhS-RnEHDOk_BMu zJ8_A!1Yqjh5CjBZ>iZoANE3jm??w<5fT=&qm92&VF4hED0xfT>?jkRt$7 zzmlM)08IT|1i1n*_3H@o1YqhPBnSz>)IUaG3&7OdzX5~=VCug=3XtyrpHDB=zlPOD z%voqRBl>q|V#jc0E65LU$~m!h@~v~jnAnzVqC_lWVjB|F6M%``LU6VKOzd2O`T{Vq zy9pWyz{I{s5EFojJwXr`fQkJVL8$;ttcU)U3BbgjVhlGDfQjACGiVb5nAm3t5&|%> zi~a;?E&vldm!PEpOl*`ZTWbNB*bqTm0hri}c#bF+fQg+(&|Uy0b{0W}08H#v1RVrm zViyr~6o84no}iNeOzbTLodsZG?{+}98z>erv8e=u1Ylx25)2lAiETwNL;xmsB*8ENnAmd&h6}*N zzD6)Y048=b!Fd8Ov2XJ_=X?Q}*o(PZjS_%~9d;VvLIGT?3C0S*#OCo_KVASPwg$mP z0x+=+xY$e*fQc<8m?8iZ`vaSuDgYCEoM4&&OzbIw=>jmZZrZp+04CN?Fhc+)Hb`)( z08DHS!DRw4vH1iu1^D#=+ACjm!xV*bzd&9eXC5c>NS>V^;0$vf=jU5L6kr}R8N*kL z0nFoHe*i2LfO%}d5{m?29%~U?D**F&DZvr}n8!&3O9fyaA0t>M0Q2}L-*h+$#X{cpm`c)hF!7>zvWePCw3L<1gk1*hBW?^?Yk$5&AI*Exai$7BG#C0p1dTa7^bJ`5kEi z^U?V;fOn+?=3_j;djjC)ZVuoFQU!Ock8si0DJ9_c(*z$1@M*VS&c`m&aQkyc)hmwM z4R~~XoF8C^==Nv%)_YMLMt|{y^MzwT;Sl(UL-(av#367oFYgWrz#;JL=Ku!<#AY4KF^9hz$g|m&e3W z2jFMK!7F*E{gYHdEWXMM;$s5v{ZXF^IQFvuJOa3dr?uk_z*k5?*Ove%qy(-AFXtTm zE&w<99q7j?se-}7ZQtH}^)m)9R798dIV0S0KN5fB2RQZ|VNb-06k~*M;9#go)uq`j z1jzyr&$km;0x(>669fccxYiM*3BYh|BnS$?aP8sz))0UN;&Xyb0T{n)c_oo001Lzy zT-(kPfPj4DFMyf?5Rk`sl;jCW#THln@eM)P0sLXu6O4t3l)wX$PZ%u)0x*7u2nq$@ z0m)h#EfQb`^mM-JfUyegXJJ>woWW1>G!TshIMf`_dJ&5|;sm$;0$yJXV8wWmpn(7! zYOfH)1YqTVlOQetEB|{0r2-K49}<)aK-drG;o49D!u|q+Mgp+%U%_ReaU{GD?)ki! zw)+`f%^cvykbl7;Z!T3ZG)w~CJV0dqeA5rRf|U@0J<06!ldAOJ)D?H<@3Bmk?#vC{y9 z1z`L(ar}llz=P3wj9{1m3`Sr4vT(ShaXOkvf6o;YSOPk6#T+Rm5TK9pI%Bkyz!Ber zCB{ezjMmdEF+obW^#R^JqCP^uLx(u$J)ObH;i+z7B%t?d!r)vIu@=`wJl@F>yi^Pz z9)JHG;4%S-$F(dmQvl-eeu7y7FgU+34rU8LJZ@%*%LO1FCvdH~!T}zH-&F*29Ki6a z&9!W4d}dU9RtsCkz5uD&@>I)9I;YLU?BfH@RijKf(vbh%B z8VNARmBR+w;gj2dj#9*!iLVf)A4BhK@?mQ3D68Zx<6vw zMFU;_0Ds_21M4E#E)@oJ-hGaNt9YnB7zxlc4LlyPKBs|E?9!8G8rU4c{+KYJ^B!>w zoZ|BER3t#tH1Ism2PhP5&ZG0iGYxEss17us^PY7Kgg8YnMFKQU18+pEku-z3Ldajf?Z!IGP;;A4aS-G*E{Z4ZF@X@Loi{Mgux;hhyMNUL5R>1ZbKb zd>*mBqJeUD;mb1(d=gPfXTyNb`_wVemd`2nM*=iW1BW736orD#t0eZtW z(+jNJ`fz$RBO=2wP>4KSN~9F1HpmO+cEGl7qrrX08P_CvjQuOLg@qgV9SaY1?F_-!My;+pizNp zPXqbCqE3?nEddde+JD0AIJ!K-&VffCdVgSMGQ)^e_@# z3Ia4u1APjtoivb4-p?@r4}za^O&K5-dBedH=ST^hhrFDRAyOh)x7ocwon)Kq_am>T z)8-_a8eR~fH*9lsfi)|JHZwRHW5gob9K-c)oCADV&6oTOU_ybpnDF7+p#`V#BB=r= ze&n^$WT}EjA=m!^Fhu~aU0bsI7mE#efT20BK&^%cp>@2zKHqWkBnNtGL4X~go3je6 zvN+tlL!WdUi(Z_ke&dPZN&&bCTEi0a1mL8zf#7NZxb8f`t}YUQE1FF#u|xpQ(Jv4z z6M$3lGX%>8m^1Jt1!@pn3T@)>Uh4S0gh$zmf&hC&zgHDl3+Q(-Pjq*P0rMbzlq6M*BVE5R2INcHI^b`_}Fs2xh-pzL;<=*f`Y zUl3s9Y~uR@Yag4Kz^4Bt7SY5sf+GTO{LCi!Q2;tVpWv7PTv06{I4%I|`Hcj>2*7$? zaTMTJ0hrR;S>ksAI4IW={2>56dw}3C0Xe#72Mg5S?AZgnviR2N*_B);U4;SmnLYCt zTDu#fXRkAAQVOe1I|n#}0RiaQES5+WfS#rEGC55EdbW)vf&$>x=d_U_0FyqQC29yj zZ2D;nv^abC_6faT_XmZ&KJ_Z=>l$Q57$$6KiWK(|82d16w9=Im9A zt4pXbz)@k}qlMP6#^`$s22QaUz^t|-s3QP<@5)Q@5&`J@**rk%2|(W)64V!fS?xp{ zF#(v>{%pO>0UiuSJ{Rvs0?_xR`vICt72G@DNYG3G*06OPzm@_pIu8)E7J$*&!y#`g z0EgAJobYl1cy_a#ph5s1SA0tw9R=X#<$4B87XcXIaxVE@1>ojoJ=eQ#4&WwJ4-#}2 z;L-6HDO6WsctaizO`$UfJ%2)?XJLS|!#NmGXl>#gocs-ZkYj+4d!k%s1`7yii+u{! zPFj4CNucq@l-XkmbD(c-8=tE?$3KD`J0LdO7?gXamx3c##xCm1gPv-&2%MFKFZ z?-NWC0IzltOc8)tP3Mv_RRE6Fvk0aOz_A)X0x&}Wj*2#%fSC@!29Lofc#54RB`~W; zc@cTJ0L(tEUL&3c##xrHy$4FspvX-vR-c)#f}D77D%j!J=HSblE}L&l z`fR@A=C}D~QmW1ONiuA{e2{JPo9bMfUs{H3e#2F0^Xrgen-9}V>?aFdt_C(AWR}@{ zF4)B8v#aJdAGox(`3#`k=FM(Ln>U7CZQkAWw0TQ*q0RfM@iuRcCfU5hnQHSkWrodr zjafEt80Of#>Yr!x(tV-L>+i)juZWk~ysTYe^V;+ln-`d?Y+fbaW%E*Rjm_(|^)|1d zHrl*E*<|x{|ESGV^piHvfLm;ylb$!*_k3ND)j7rG+Gg`4@`23-cURV5ASzs#RTuy6 zwYd=Ow|OWW%(@hPR>KRk7Gm%Y*$n0%T!DRzyyb;n4nB57f?(<|7~%i9U}~rtCQ$@a z`9^R^1XG#g%6SIXxxbI|qA;3-VCr~)|G8l5^=z`bU}{JNQ`r!=IfP*9qULBq1XD)= z>+K`QUWneGT@*F|N5t~60QCjni1-;jzu;L>Cu@+&`AJB=WaUDSpY`oiZK9P z1YmSl5_A=S(fNorx{FsBovT@*hX9Pu41%5lFgka0bb1NE=sZFjy#-)&1`+fTfYI4U z&{qIPrwu*rCxFigIR^s-n9*rlq~1cuL)s+>rs~lV!BmbLM+btb+goCEl4xLLk=`d* zk4`ed`2sjP?8pTIFgiEUiBSSDIvoi{3&7~a2*wD&=q%<$jTL~=aj}(g0x&vXvcz}+ z7@fyyV}byT&P0~DNB~A>6iZALfYIs95uPLfqjMfzpCZ7F&d?(D9XcKo!Bo_7g+wrw zn%i)}(M)c~9oMKIL>oE1ed)c~9oMKIL> zoE1ed)c~9oMKIL>oE1ed)c{-`iD0S$xK+}B7&&~AX-E))c}0OA%dv}FnqLNY8^yI zNCZ=v7ZSl#1{T8yf~glWd_*wS7{Eo92&Ni<@DagO1M+nf5KLXdCNddGYm3a)xCo}Q zah}m2nEEuE_-_SMKc&U$f~lbm9Morv0&I&b0t8ckrNy2c{nwo(#o07>TagO4g#i&v zMG;qM0uMI`rqVQf4Z+l|C{!t!s{2$;FxB)ih&~olFqIqAghVivzo!X_V5;7-CWj4P ziU0K}RRmL?Wdpa^rikOsby@IX|GV5(^`8P`hl-0HI;wVzFjVCqjyjN%Fl!PH-n zFhAlU)=fe%mF08jgKAd^9l_M$<+xPiHAR(R>QtbNe4g}O|4}fNtBuF}5KI*nWi3S& zpF5vt@xm&>R2GW5vtt+&)w(F_K3wt?yYqQ6t0tJrLXF(ntyySrQPzVf)Wn_7HNCt_ zFqMTW+}XQuNvWn6Wj%oAI=b_@w5@UHGeoNircwreqdT8bwe3F&rqbYcclMw>7<{oP zYc^Vc)t%3{aa9SXvXIA5$K$2Bqs?^k(fiE|LE-Xk`2|=TbM&oshY~k)5YGAV##=EfW-(9xX@E|bwFHQ zmkWoXr)t6mhpXtR8i2!9^i&PNYA<@K24J-pJyip++KZm50a)!tPt^dd_M)e109Jd^ zQ#Amq{abVlda4FswHG~A1F+hQo~i*@?Yl%!#Z}@|!D=shs-^^1`@t;XlM-0%PZ2;* z)s(<$zqJ4Wda4HCxDq{81F+i9V-@JB8i3Va^i&PNYJXt?N)bqNmEd5P!C)pr`tAIZ}ux=&3^Zs!C7Q7(hI|!y^KE zssNx`Pt^d#)0G6!Q#AnbBzmd_Af7}|)d0lPN>=G0RS-|B381HHN+6y@Pt^d#ljx}$ zfOvX}RiLM80OIKd0_dq4fOvW^2>^Pk1|XguCxD)+0f;BjQ#Anbw4EiOr)mJ=>1_h& zsTzQI`j7y6ssj8;^}9C3j`pZL{HU}Ksi2!=41~8ropr>j8;|WixsHbWGp6=zr1wB;*5KjZ~V2paI1~8ropr>j8;z{&W4M04Jo~i+e zC(%da4E>o}m`VEktC$_sj`24MW^<^w=a z)d2Ke^i(zQ(+RDodYDeUj9U=usWLA#n}G*CRl3I;edwwFjgJvVc7*P@jGk&qFWmU? zcEM%yBF|^@)afpP`_&GJeI`>z26aSel39QdepwA z>RJ>IHNcZ=^;uK%^sXHf2bu<&B8NxZ4^6Gd`(T9h9m~;`AMhM*xmEeaGSxfFn-d zu_OsV#OON~zW_vxzGF!dfFn-dv7`#X5vT81(gom%(|0Tx0&v9XJC;lVh&p}8k}Uv7 zoW5hp5r893-?8Khz!9hKSV97D#OXVhumBu!`i>=#mJ~G!67gSfAo!uo(^a69c%% zfbK<)gmU$Rfm*GR*UK?5w-pit5&@d#p*%ccwMC)eANT@GjYyb7neVvX+ZUlcoBH5W9Ut+=Fnzoz zq1MyD!n2V#$?@?+`Z7HcplKSIov?P&fcD@D$ACfry;O>VS2_S5(c+~Eb&?ie>x{ga zj>X~O5bC9KT;usD*#x%f<%79>>xH#i0+RG{FhM1ZDg;GTqa3k{@ju-2Yw;Le2FN&_#l(bbNDrX0O> zi2zO0z@~)tF%8_^4*cOW4Qx!PQ#8;6tGas7F_6Upc{CBAX&Ts)uyO{#KwtLr*)t71 znNY2e7wU(nZ|Z5sK$IRlp9s)24ZM=D2Gc+u&Kl~qGY!0yP;+P?z%IP(7^s6MiRz6+ zfTkIH?WHq9zA0+}bO%L`Ztki)p@I+(q z&k|LtX76)Q_6xw;)0E(A0a$7-;Q@0%01sKW+MQ4hVJ@_Th4&`(HcFujc=UXe2+$k0 zc_d+7%r=+txc<@UHGjmL%;7mE0E^c|*8Ew<1+~${_X%|ioA|i}^8V$F%ZCi2(P@TL7Kx*;wEZDT0yWWZc;1{d>4T2DNs?8rnqL0v>FO~=}ZSWAF10nmfG zDD9j~fD7tSSKXE}9##TI5KtW7y-^?GiJH~ zGdLcPNGAwQfaB7!(+O}a`+B|$5JerFa!lH}kpP#DLfsq}U@aL>N+$?SfYZ{k^#oYQ z0dRT{;FPrU0Rh&eQTJ;X;6<8qb~-_50$iAmg{K2x8MQ2T0pL|yaDLk9kGhJ%oa}z< z0?c6#uSh2dO@J%Xg%b#{j#JQ8>0WTSWxD{Y)3GB7u#C;VOoLbK!JxZ3T})^K+>|an zivatx^M4lvxGo*Lg#dph_zf<=a(2n@)5V0QnXA&yBPdqUj4DDA^{#a64HSzmv$~ev5IC?5sIj< zr3>#uvG{JzYHtKl|C)}yin@xQxVpXKqE4po-%J-1iU9AX3%?@3t?cmkg8-Y;u^#&Y z;BiLN+b%#?&LkhEiwRA${*rcvfT@aRR1u1(Thg&TKrG&kBVntSlqmQl?aU$S*e29{ z=DK@7+W1vEK_~)jOUG^_z#VEP_W_Dy3>UoEq~glP>TwH)fSqywnxwYr+qCl{RW!1* zzIRm|#z+li5>!qViA-V1{!p`kR?W`O#7088 zVjxjt+MbHlxGU(Q^niEK(8=VG;`SXG*o=n1VUv{MOh}cnktUXpst&% z;ueNaRi>EA>3%2U+=gNmn^Hw()Y~r;`xwRIuh>`pU1xD_97E}WhW8STxE+Ju>z#2* z4uIZk84|S_y{=_B*A2=fsEjH`W(xNPQ}MC&pr?(d9nZM0H=4F1jc5oqZCEBYpDKRO z4jSP$ZF&P98Z*UIP8H)ag?CWJ@R6WTa1pt@k0IhjL&d>_*;NSIF=H~Zm#Kn({lRH+ zRcz(MZkb{#r}uWsI3J@}#imqI8TGbi3I`kry^V~lHW!uND{TT{s;EI={K(Fq7Hrzy znb_Wtt|;Xq+wAJCp_is-im8k$4$c%VrHVH=7yrsoaZ472Lktz?G=gwwP{sb4*d0{S z%0Y9WtD=lvIxJI6l`h~aar8LUD|OjfieFq z$JxAKU>uoo20*%E1?Rb=+`t$~r_9eJsEjAdQ!}wyRPiE1ZBfR*q1Z&iX+q!~GYN}@ zPzkH?{!PYNN)>gqXJJO42KOCDrYOs&%~aliZ*)hw_-GQY46dN3x$Bg_LJmT zE(A!!G3R8Q&#B@lhWEK{EBbRBT$D*rIaOSiiJfsUR6NLzyFvh(Xf3*;B9Q%ON#5F>|CVL<~ajg*G{V!?vbwbc~ugW+#!K8}gsBpDw z_hL%kkV&vbwENaf>~Y$iX7sHQ0KJE~Ipcgtfb-baTU>yP32=KRL1=d0eVN$#zmo1- zC!K=}Ce?ip2tm5e}PD{A?Z5OD7Qh~w>9A>c0PpCtTQ2)GNf*ikPC0kM-H;YA@JcDj-9 zk`NFXH6*+&1VqLm90#uo!B%5rZN|ABT~slN!|)z=j1-T>!yB0ddzgXnPA2vy`;mX~ z(0R`fgyOe2%YGn)uo@D7%Q&H#Kvc|scOzp9C-Q$}64XV+Etyyqn2N{H6I)#X{0=$C z)F&BdJOQrYy7rk1a5o$CRVG1b0{klzn@fNXIko)Y0~9YL<4+m)SgK9>CgWU8#NV=! z-?@liuvhH*1a%QHRv){Ah=T}_sMnhUtPnKGsdxA$YsE2Kxbo}uD%Oh&MPYq{&;;mO zAL9$L#V>FV(A@=acdK3Mo$iMKAi?D~=>mLAb1Lc+geE}m`q%_86@S1s)w%#YFrG}4 z`qc;8R8{XBNyMcDsdf>!uuc8z6V%1?-mv;u)uBM#ksUXp-n}!%jpiT{MhO8C_99*=wQ@5R!jlyzC|fgyi4J zv4;>~G;SdV*E{23bj5VqxKq78W`4+#x@UcYZKki<>SKI!xVR^MHP!bOd#kzLIgIxG%aJH3aw-x|;wC2yloGQ2Y~{b(j!nlI(6i^tRUd4lLD#G~q+{$Q?XWZf~+ecU80KtQ;Nr_{&z#$M3` z{+ab(3jn_Se6M}>#*s_{B2OWnSnn((;zhLaWEXK2Tm75*1a;BI^Xg+ap{Q+Knrq{4 zMTMgf&#rf#A>!aBfGlwl`AWWXVSR$Sh`6dg_8p4a#?=BKHeM05@uGUC>Tn>Q#YkD{ zB2Hw`UR9r2|Qok1h7KshyxK#*PB-EduyiEvLBo5#8-)O8q)2#D2x$Au9BfYu0S)2bX?6Z2gl@`+hwGi&X~Y*~e$+Lhod>07>k~AO zM!Z~K_@-yXtM&dzvkB^aO$b#A@x}UB=m;Rb!j1JyT3f|bM$H@b#neT_x9ba=z@(e? zt^lA}3h_N5U}vD(`MwbJ#_p~9*kM%h-VQ+B?5b$y{PbacF_qK3&tp8GSVhaLsEm5I z)W@2R6un!;6{7b`A&B0ugaH4lKK)t<(x=}D0dr`Qo&2p3Fo*Ue;X5JVQ=ywk_+ALO zX1kq)e+dDf3f)h_HX&dqu%3h;gb-Ct`=s7E46UfRi!0D)Zl?|BVf-fyOt-1ghFJ6{ zG<6AGA8+u7(R|Jc1wuem7m`pU1T^&;ij)We(~xVFuk0K$PTfoHwvICmT*1gfx|DGg57qoHCTceT?R z^!8~q9}aFvP&ri`-VhrGrs7fkK|jI;P&d!EGqb^&N`PJH#6w+x)g17%8xn*jz;O++ ze-K~^EtoGBpf6tG$XFl*7<~&@oa2Rn&e=p;P7nfiE?e2-Ckg>Omme6cCkX*Nm-o1` zoGb)1d_1FOp%8S#k7;m|RFD^MnAq&tbfsF9dD(q6TLp z?QWypi(R`frq`A>B-kR_y`mx3?^ybq{cy1W!0t*~wMq!E`%T(?i4b7-4czst76R;k ziG6md5W*^IE^Ki21b)Tw)Vtg@VmaG$c|(Hc(THmsVwcf~3kQLIy#T<7_+Suj5CV+& zjt#$22rz=bnCRRj1dd4CxvIf=ggSpsomaa$pQjgo*N~t!)OmYDtaT1`(&#${06O1d zpxq?|=)9N>Un>OYe20N{w-C_q?-*$J2mu`yq4Vw)0y^vy67CZMI&2U2@%=)8NwE9Y z2IoYWRMAHFta0uBkqunekYI~w_hSvQ_*~e1BAFf+0NA~ruGt_2*!>qq`yYh>yYHeA z8-)P7t7*g&LV(>T>;l4*LV(??3Hp=}VE5tdk*9^A?S81i*$F09Oc;W?M_jwF=E?p~ z4GFf0cE8vVyO4G-W1zhx0I>TfuK#}(0_=XD{(e~qu=_R!+ABhU-LJFHUKN54wC5U} zwKQTD{qnqP#IM*fuQw!U9*y{WLo9q8j9AS;dq)6ZM3T*VR|qho3(b5_2ryz6`{8{d z=sd$=+{C(ho#vE-v|L6R?nH?TOsHU`?$f`OuJ|Cl<}!+_XE5y z_^u(r7SV32F*bjm*d1!rs|63T%I>fb#O{a?#BN6jVt1Yp#O{0{h}}^kh}|(EXuG#H zIICe&#a!C`qigqre26zD*dp59r7`w0?M{sWJt+XNdklS5CIs01){Y=_6M_z-!bay` zRBdAr%hA**1ho3sB#aRPdTTAm_|8H=Z;fZ$cM*ba#fU~Hxd2AA&=n(HBZdse!>)}9 znnxq{Zj9{&rsByQP0a$3uO_!W8l5%*987>o;#l@kYh!}Y1lYeZb{zq#hk<^O0KlXk zBpmD#LWq|XVP*&i;-zaH2)`17HhOBK^CWf7;*gx~>O7Dm7ZFbtg00-J zpfR>T5nG6Og4R~?A^o_hv6#AucvfTK5+Z)l5A<_f0KT@PRGcS>x{;?h#%?3xK!*2k zT*MKCKfkeT>q2`a2zSJdPTo7S-W3221s5zXi zT;ZyjS%-(q8;gle#A_Q1cLr0j0=QlP5M#;}Hw6v9sxfvr5uf0|xY|YhEzi+6Hx^SD z)n3@>oPuH%4Xq+J)!fk-`v}FN*4^M&~-()VB#{JmT84nVx*QF+po-(_b26kDyq* zCzrdw3Vm&dqI4x~%^j;HU&%EB~^hI68 ze9kAE8udFrg9z|;V}j5G_(x-GX9AqXK>0Xm!F!F);RKk@+2RA&f(RKuZA=iF0N*qg zzD$6rq<<#?1h;<6IQ(7+aO>aM$ZbNvU^$Zd--=E|e`p~K` z8)N^XQD1Yp|ED&%qBkwHvc)u)M&)M<`=1P>USVrvS$D+4sCOt87ebyw3}<6|fw|&3 zPP0x{t)mrBa3L?q7E>41e$nX61XC5;T19NCDa*zdQO$w$a5pV!yNg0e*13+Ts;)Gv z*Qp9F;pN!`p$Jf&jXgqu?ws;^y8sv`)YvoYyi0(qX;zgBuz_aPW)p-az>sXrS_pud z95q9O00Xm5U({7RMSwvr!2O)^hG!FmCO~~Qwle{4;5cjyHeqDeIh+7TaP~{P0Ka2f zM`sg+CcwmO>aud0<>mhj}ze14CrkxfI2l} zy~;Wt65ua9|2De-JJSdIW)p-az|3r{>nQ;Et{>=!i3NzSQPea`+5~2J^`NZN0OpE= z88I_lME)kOb3`^lT|}Idjh#fqd^Y?zK}7g`PpNrAKupgd$AWC&GlQeD&XrWLmUbTF zs%Yn$bV4>kp{O!0N|y;^u$d<@414|7Y=Y*|h`X|}slSF1cW^$sTL92^Qy7Hz z3IRq~bnksafDvzu0^xokz=-FwAgmLDHsTLi=M>;qOkv#}t`V!~i3hU@nnxoZ&&J-M z5!W*U|0n=3VkX02qY&VlTPgXZ5Macc?4qZH03(J_1}LhSgLg#aU#()+In!BNisbJjV8D)wbGyx^)xu|2Qh z_t;TG6`QlMm#E@VBEBsEP!S{JJ3@epA#CTnLV)+zF(%#<0vi4aG2Ryf8vZabJ`jR# z_@=D$9j$tmZFK2?191 zp%MQS0<5}y3n5$cQxL3hWtth1FWHdFdXSH-<-Pu}PRl~YCG=-45Pq2h8jyjTFx z@T16BA_S;dKufy_0S$kI)|LtZ4ZoL0B!z&6f67BgnGkftW22oVP*|}K2U}vaUgV|` zs@v!U?WI+fqhr_8sxcEmuNHuain1P~ou>$JF#9v*0u1EP>ODF^XaWox9ea-e_`YkL zyUvrsr~hataXJuG<-pP1d-8!_5#bCUov6Ws{>!i=mtTjcpYX?WDbS62ha1#V zE8lr}WUT!h`I?AVMDgF+?j!E?;5{pNv zZ^s&x;#>SfQ+ySFSc>n{4^Q4-1o<0AC5bsAslH9(#!k{=@j3A z&!qSwdwq&;qc^1ZN_jS^zGC77%{4m3SH8!j_*VAV6yKz7O7ZRIos%Pb0INK$@W&;G z#PHN3t!$f+;_J=3rT7N&9?3&Fm)E6LOZQCirQ%7+DU{tMtt{OuIfG9VHPYTGz5?8w zR9`qTSxdE~_!4hxif`ghPM$#S+3Dny@N8T1bUq!Wk!Ga$s_m~*d|!5E@-kYqMAsaW zyo7w`rjvspb!dt%gEi>Jq=_!8-{sWbMqtT`#Z8#y<{_Z*K)&a8mM*V?LiDZaY6 zAjOyWj!*GLyc1G<745_n-`YAU#W%1{P98&v<1@-53zH}D>4Z%3acDd>#TTfSB!5HN znHlA!rO6BUbe85{mg4(Q7bQ<+WUkC8Z>>o2g{74#zW#G@@=|i&skv9B_(sp_Pi zQ`4?U@$HbSQhcMMJ;m2Du1;RW`f$BMyC%gKE3QpmNm_Az=_j!3x)k4)xFK1>wXbJ= z@_f*4O!4)HTat}qK^s`F`snw`iG13zKDinZbZd&QGd!A1QEIPx)!y~VVSL)VKKU>( zHl+Ak!1F17w*NwM7G;mnd@m;F@#)C=ddd`rlLhO#JN>KgWJ2`D=1r zU7uWw;r4DNKZ$-cT(*S72kVvlHiRqrk?fP~Tqlh2_ScZ0TtmbDn#kewbWJ8dv3$7GU1G?zUNF@&q%OYh( z<3OF1RgPO8spLuEqDWZ}Quo(dS47Hc`FKD!c_EBh8L8xM|Mo~Fx9E37D!GlmGg7t_ zd48jT?ut}$Z@e~A)pbEgwb`4LV@RTi{@E%2XQ26CHDfashAZCTX{~oM+ zhc7}!^`akOXso4VD;{cIx)c>{NtUgeRTZ`so06pNNKKR?(~B^?tf5;|#SSSNb}nRW)L7AmUN-d~Sq8RQ;ZjuOpZB_F>g=M0 zWPN%Ym8|=YE&TEews5z%(8B2W*XZ8oKzE{5@Isyy-uNwapBx@dpj`p#>O8gR1_I40 zr_S57&hsmwb8+}=vhDy+x~#t`$~zBC&u^v9ckt7WevO}@XpCNs_W37uo`IiE^cL!j z*1iMT=q{gwJ-Q0+j73lX3bT|IehZ}7vhW>HP+ic~hErFR>j;#V&W98h#4q#;ypLLZ*6OG$tBrFFAz(kIe$xHA%`?HRs=hhij8`YQzd3 zk%G*1;mMSF5dlygyRoGE`CuClm&I-_r9&;P=eBaKbSE@Ewx(P)yXJiaO6(7+rl4jT z8W_8?xE>-UHKWk}*j?(OOU>(iSX=yBzGaox)L|ux-CH;qYRYuPtSevw=)8S>P6_Dp|M9wzQRMz=})5esnV*Y zG`=E&hZjpn;2~0Tavbe_Lp?-mo_`oM@2ZD_nz4`I;ZyZcQuF6m@$j{JC`;z`fK1pf z-3tii$*%NRiCua$o_Z!jFN3kdE?thN>g3mSK&@SR51wk1!#={(FuU}1JoQhOZ@^Qd ztuO~!JDdntL{ZVNh(CJZ2bva#w;fV@N5-NZPEr-wB*o7rD1Ow}qO6FtN`tVgP*X28 zw9v2V=T=Xa>a)G-r6@s=!RCnK`+bYP>enA7 z@H~jB#GLMMS=J6uV4F6BlHVWWP7k2?PDMNY7Ot3&c(bBs;inz_90NEM-Te&?ofrmF zH2OC+jOsDeqgMDv#Cbdu-b$cjt7Oo|8;jZqv=0KI$;z+8eB)}^xoAEsW&zKNuKq^N zV4waAV{Vr)B^=h~S3`4tHDb;;>yPt6ckT-KFktL6>N+VRV~vgtOy1R~U}0HTvNgLp-FUvTt~ z#IKJny3n!)-1|O=H+55EA76<*;IGgW|DAredsqX8W7>+};y#yK1LyqeFf0Ch_qn?@ zU^Tireye`QA3GZ`7>6Z-CPpYyE&bI?`sd-XGZCvw1V;O6-KZhgoaFpK)ux%F_xj*<8^&edq? zpf8ee|8=Eo>7b27c_6Wp&Z_<%aTkfVm#hU>icW#Aj(r6T4}~e1zv)LW);1J<0ZQ}* zNLbOm)e`jUcflU*0zfA^602yw6`sf$|4-pZDV#ui+(3PH(J9MUN2h+0O`Av4wym z@G}yv{Td)v;!^O&tL*R!3OZqa5{mv4b5uCG2@Q`# z-@sPKiGGfGEH8R-HwZ`ja_x=|s>Y-leTQ>h^hNL|qW6QpAbJJ(3!~3~zbHBt{Ke5- zup*U2w_uynC3+Rqmqw>RV=~$s^s?xqpm&W<0=-+b8uaebRlq5aP5^R`=pZ0hL{C9& zD*6U&>lxh>$d%E*gR?3+5}duF@1eFD`jN#a*x_f`%tyQpT6|Z#=r3&Mc#y26U2^aW9H6*3$D8dQ^Wjb_c_n6`c#GYGOI;*+^$U1vwR?~; znp}YBici*@1<3>9^LU%xgWJ)PBsUT9skYulB#(F=Pt)v5?hwk8+=a%c+m+l@^u!{> zZ-Gw~p!?$c+TqQ#Xiv=8)$s%Dl3iB92J0JC9c0(kD~pEn>0rBtn-x2GB!}t@yM}`+ zlx)PniT}#3;g|_0yO49HUBgiuNiO+2o({2V*sf@D3PyVTQ2kVpoc$V}4%1I1$;pVD z_~H7gEO|R(K0eE?VYrtkzeFU*kFaYP!#$E`GqjGhYZ!nP$tOO?(`>tjLob!Q6YEX< zDE-vaN*vAceY72(2iG}l){u{3!qE5}yQJ-6H1b+>Li{+p+Y(M`$$>Ozo_-1?-^Dr+ zpKo{Lx)(`4!Wn*neu^dwS$DjCDoCD6loRw*NpdFV@)Pw_S#k)5XZ#fGlYmm5jA7u$ zPt#95lPf59hF!tgu{xQe_OtX;P4Z%ns?N8*y?u$M7r665mohRuU) zB9ostdjmHBxMt8jgII5>~!i<#-KQ4XG#c3Lk=0ng=#KjHT6D>oX?AiyESi$BD#W^Ry>M zok+dQ@(K$s0Ycu@s9Khnp+y>QS>E0}0H%5VL(M@P9d*ml*5E~ceL+9=%qvp+ zvypYTGNkHs9XpyKII0UFK5_~VqFNOeA2~a{hj}W!?haV@ku#b$q&ffLVQ*d!po?ki zYfjtu<;G+p!^1cp9*D)rQD8{PL_ zbsXM_nT{IX4Wo!(hHy!|fIlq>1FeSLNqUJfQ0M4yZa9FXk4W0nQ9C@VVGc>p(U~nS zX=L4a4&I|&A^3Jb`u0j%bwi|Z9RzfPZ-_Mb4Zb0Am}>A7M88`%%gUTgFD;L#^Y3e( z;POZd1+7tkV>PbV?8^l6^vEQIxs0wlBQi-frExHQ)jN{lp)k9QPWU3M9*&`)8dP6| z2lJ$;$N!gMHJC>nHgBGl_$r*DobHNkVciwVd3HoOPYwBmYjXBM`rXbb)sV8Xr?TCp8s#t#r8JyTC}}z@8P0J3m@a2um4!2E z#Hpd(&GiUpx1M1gXHSun zYeK`7Bh>7>CZuN@)%M#B#Crv#JH5VKgZ$P5SsoguK>qPKI&*obnTLAa&=nfQ%3jFM zoUH{ndxEn=J1N0)87#9ylXzvI1&`K(b!vz&a2v#nsl@SO%ROw+x3+Tn@mGqAzO|K$ z^u+qDy(cGD-2>m+$MB)<1j_x(PWj!u%~st}H;CPcqpg}))vVDaq-G5j>s?(d)I`%m zKa8yF%28hxa#z0W`J9q&(?-4Q8Fibj9i$p?o4uQ|LwWfRTD4Mex2+@LLt;FjA4clA z=viA7e9ypGsudJnC9Pg+D@SVIU0`6Y)G$`|9k%TtEw|8@dvoR;t9s!{ z)&FBv!~db$JyuP1U#pqUYC1I!JGMWUbLBe%U^{b>jQ)8v*GOyJ>$v=juJ3lKSFyf< z6=S$~M%V8~$Bp6I8C}1xS~|x)5re>*ZV!6`YcdoVTlpiH?o=^gjr(&1OjmY$#bdfM zt<}9rTh8mY&8s+Xj4yqGE4?#S%;`4xYB6?Boo~~ealTD+CTp9P5p{aER!?Ahnv1!% zX{L*M#~)ze#BN7YIOwXN>)C{wv>RKQvfJ_0#ZFQ2KY>!WXblKSyZG^_ zWm)5Ygpz^>!m05S3h@EL?I=v{hQbZu)TsT=LE&$9YR7A!`w0CooEof5A6QWEnB9v{ zd!V|m_Dc{Rw+mGDgvZg71%q_8t{UQ2S#}q@Z&5N4E=mE6XI>5lVUt(8cO0SSk> zA@;D6E_P{NQ~4$1de}*vgB)vENvQk15YS1Wr2I`e*K(Acyz}+}Pve~@TbQLv~uhPBN zn}|KZ(Z{paS68bW$hP*SJ>=_0*A7c6*X}?#*7owaENXUPM?N=3p!NUis&Dv3VArhkx7MubQ%s~K|zGPhNP~MC?XbCFfK-Uj`ACf zuiio{p&`RcpI&dcm^clrHe1seR|IUBj2h+n(W4NEm?wu=V|!$K99tAFYDhFD>fuRq zgqfoYqdn{ov`9BgM0ST}XQag}ub;~Di!mTEdLs6iL?W?!QbW_iSbvDIzv4+dkpSJP zS23F?)Npv*J()-pCJGW6a21$j5(-_liVwr4djO@_WXISkgf*1vLVIXmX;*s(H7g_? zWoVge1sYE4y1MdsG_B}nl8M(Hgs5(mR#5KR;o|f#1#shIvh&IZMlZ41dY8Ya=}gpM zAklP;Ayd+KOD~t4MVra4lWGX>8AdsdP)ya`cN3CBrpPYR0U85)gYqqOI&`iFy3&hWs)$ghS+0!C?4q0 zT{P4&LP8BLsi$X#L!MorT7c1&uxVLc!p3L{VriG)+iOk!^boXHi)(Eelb}WFY2xn5 zI#}B<60K--Sqs-B|E#1$^+Qu^n=dv zL9_nb(HRW$Jh%6iWsK*137jZ)g8|4g#ypj$|)G1L6>ZAF5yaT z#ypm3cWS{buS+2`Fc``ijgsiwzz4i8a4^Bv%stx3y?xibkbWy-JWSV)102k zI+zqRKB{NGm^PGC8wZ^`S^`rWz0FC@3tbWlb4O#5G__dTQxcr_x&)iY0afbuv8y#{ zV)`>jS#ZLX3C|rxnCSF;*1faopj_te9)1vDa%0G(yf{$7%c0oQjRY6E(&JE(LXIl8 z5iUnBJ%p=4^}K_v0Y`Lia};d9>pF=l-7${tm^?qm%!t=hWoJy)g;%I41jeL81tHmaGj1 zQr{pC_4Jbo0~^2Ktlr-wXt)8vS$2EVKqs-JgUIoN2#26xgY$D6jL+JF95IsvyP(dz zo)E7Wh-VAM*G0i;pjgjNCDQ)Dw16o=rjevfBW0fR)F?d1R-2)&!AZMYkcl4d9wcc` z{sPzeKEn}AX5rnFdU46?7+m?%;HbF3-#7+Mp>>I%{T&x2Q|JF?`sl3Rw5=Fp+E$D{ z{QYR`cCj5w1pBQ(I;K!MrYJbo1SSiA7AOf$HC^0bQiB`ajYn^e@P(4W5#Q<50i%Oc z2MCxt^rTX5s^O&4L*flDvFV*qN^hre4m3L#+t`ksC9}So6mTx&{4R68OT%%{T&s1o z^+qSNbuLezV4v5z16_snf78W&gyxx(l#bARbHV!sVZYtg=VyjbFlrLPNx$RSD7T-m z_V@w8jw_b9E0MVCBJ=JZFaQxwdXs@uk`Ay6J&mP;(Zfv*0!p@<2&P~? zHW0x$;Z)GeO_=vCdL z=;JQIDB+~w9(1(Vv6Ik+GI4)k6R36(!MOX6o5A3iuLyR5zco~2lbs}6Lw6`+k`NR1 zY*OWpZFgSlW!Cf5!Rf+l(=QtA9hdN+vHy!$_?ct-f4wwx9${UAD@Gt1a8sBY96Ba2 z`KukJUKG3~g`3vy!RXRsnM;DqBXZZ__FXC%rMScLdyb(dV_LE6$+jwYSH;^7_jXE0 zF87t*aHdr?GM0P0k&DQ}26#4%8rp~gss?&>;9IiWy zTD_0K{ZA*CbzW5Xvsqw4^2vq45DY9zn8t#0O-V4m0y`Y`bRd8kK!Jl131u=Dca^!g zo5W_v!;sngI{M`5&h5>LVEm?J@-l5D5Rb1Z%Nw~ZVqWIx#;K=nI zP&o7?oISNU!OZv`5gc80X1KF{WbnT17fjYU(NBZ&I%@+qdZsU;!4Vn@j?g&!XnRKF zTqF7O5_SJiZ_7C>3WB33a0lU!L^))j59m%gWT+k@ihqtY1J#$u;B)s7?vQqYuxj{$ zsc+G}Kp?Jvpfsk$?!h=McU|p{J6tjO3k5EjIMH%{=uJD=MbQ0$y@QU!oL!+N_6l}g zwX01v9qWgy&3(j&Pi7SOw-Tt=JCs_PWctb^(@*a-}1?DNXN_KiBBY{w1->cbpk$%G`k6BP`{b#=wLo_qu~W* zhogfVB&KevtTt8tyRQ2$M!UE^rZ2g16O{Y$i+>Mf)WK=AtkCUw_mPXLwN<0f8EqQgUueO@@K;N%^sJtG@JX38Lk39hQp>?4%d0n9 zMg-Mue;WGtvFzTYyPHRM8ZzQjrXra=%(!-gmG>A%jQ#v=qZi?7?b1^iKI0YtXhN6Z zQdlbEEa^u=nGV{n!Jw53Fcq{6M!XOqo>nm~gGHZpzz{g;s&LCW?CM_4J?`o#sbZAi zXlvedsW~S&tJUQ0z2vhH)v;PZA9lFhfO(OFS0jAS{BOFuV?X{U79dcE4o`Jlr*A_oOeNUlH?0X(^BpgxuWCj*~v=hS?jN4ybUwv6wV4B7w*K&Nx~QM_p>sz%VZr4+=+E| z4`L!R8p`!lXk3k}&#qI(us~1I{T(mK{XjwtO@7d&z>;bNOl^9!(cR%&&#KWYq$YPDljlRLbxEve!zJPSGp=L( zNTn+STP|K`bd})L_ZVQ|C7coLoSeL1_q$p)VQQ}N$-L1pgt-OtW@QAY91Y|JBybxa z7x$8@6kNe!xrKE#UTnCIW8irazy_&nI0imG$mNvXHyFSDOn%?Y9o$B#xbVsSgYnBi z^pqhC1GiXiuE{(OSkcDVr$WqL@A za06cT171;b1>DEL%S!apDAaqsiT7rMvol^(GV%3NfO!S4D0w5tMQ$_+{B%9*$-=4H zHomfC_)onJC_+A^6Vp+SGyHPfK zqDjztb`7pmzhF)3c+D?!Kz_&h*x$kghm{=B{m`BWy+P7+spiT zQx3#R92-Un2>*6DIQ`-P%+Bbg_ZmOrep$l4k2&S(yXD+@ub(X8vgrHs;DBH_%7-9s zL-4YvS;(F-!iy0vn1j7L3b;b?2lft)??`X^@A zAYBiWk$OTJWo{&Njm)g>V38L<)fgaVeQ<8X{3;(&l+^mV>3VNGCH!dK}rUi_CNI*yj$Sj+v4g##zB2hn3JcNfxe z40pa0@rIxpM!Ja&!GY9h&K7D{B94+%a_)=N=GdhN#s-ICQ_#5ozgYb*hN9U?dN6Hw zu?h}Tb#UOx;J;t2I7DjA6|1kTO}MMzXxYJEn{YN&#~H*MLnCk?@CWC>&d2PI!7)21 zIA#ZTcA6NHJ5Xgfs@2LnB$xwIUOZPzMdwF^-~yO?MBo^e1x$gkrCh#@HB^=_Rj@_8v@4!o)H2& z1w?`R7s786A=y?lvpS@R^`+g6U&l25fm))NT9^q_OOQ$7)GD^-e#rXkA~P*9_v+I; ziLgSa$^xW33%`JRT17j{J&|l{GBb+h!i8(gDok(nM6(Zq^KrUsKHP1@-js8^8 z&L>(DBZel40CTFSMuIkG!W8TnGVP|ATA2w`t7n5&rg0{V4Q!{jpjFEk5Ta-BzR7SYWLS#<9c}Vahv(-pJhp{e)X=w*0YB&MZCFHgyGb2;Tnj0~d5&bH~ z(#-4`qz=lI2?o>p4opP67SubDpo|%ra+MMNFN&p^+4o36WyJBBT1=*3DBv50A^f_= zV)m6Pwtb6?uz?ud48r?JF>Agxq9Xni1{4+Pe?u_hnvrbF>ls!Y0MbE<+{|nVQb$wC zG*dCPFcT)ah4{$aT4o4y6s)0Z`V z(^tvoebYDfjir9H(=sZq?Ax0TF$9STHwH!!~3?g6(=cxW*@*C%s7wY zA1$C)^R)YwhmX)Q%-F+GX_Xg5@qlQF7X7C0H-pf7-wdkqx~YrXO-7Z3O{stybqZDe zSO&FMC@Z{}A)TZb6}g$&S4hDa4PkO3)3r!+2y=27ezR;6nG9lB5pD)CWDWD0Y2)j> z`5oQ?R;nQ6_lkLFJM&SPVQj0-v)?9>$smRm0ruvo7z#>Vjy!-SfYhqU&CHHQcN<_} z2!*Ugs92+U@By0Drg)l}O+^Y@b8W9F;IgKB>}_Q42nn7&z+?%Y0OC;js#d{6OoEA8ad;SsD+n$ z_W_Xm&z_4~CZn0GItipxHJRB;q~M@}IiTI4Sp<#wJs>@*$;_TZ%9Yei_bH}UX2N9d zVelpAsCiN|J?%0D_99vTIGvXdHD?H%aC%~C{`1pOjWlq>!ym+ zm<`obX2h_qY0Q>rDl?60#4|B{i&|-sYsI0y72f94Z$X2?oXm`T^w{KfUm`H!akJ(B zqj40=w^l@2Rzy}r_%H@3ZcSbhS`kt-J~JgqYcq&VAQt$<=_?|nOjOh*J@^i*S4k{?TVpja!d!Ah}b4DBbPDVU@le8 zZUQ;a+B%WT=VFxEEAlL8l|>{$_foog-kct!&2^1M79GqvXy7*;@Qab`0@Zl7Q2E0 zXn4USdXt}R?FX(IiqjJ}iQX`>RVXbCVw%L9A+3GGxVlQoG&8$Z6{j(KK~tH1q^Zn4 z*HmWPG*x_z8PFqo3m^WFgGcn*gblkQ6B>JG%$C&x?LG>otqdZrG0%mRBI07n6HYUy zVMFm{MUY`ONfq0eU8bqb)@v%W4VudARZTU~f@Na&R7@?*`l;d+W_6m%EUT%^sFgEc zOFK(TRYeQ4b*eap8Ew!!ENK(GDTB@m{u2`tI7Vcvl>2(Oi!ll7c%LX{1vtgP0H>H* zKvO+XF*zVF#s}o389{kzPJq>K%nYx!`}stcPC~`QNSLdb5vDu#ODEyKrafzWFH}DV z>Lb1A0Iz^(ml1@v#tk>|`AS9ey+nYga%h627o~2frGK&c5I1AkigS&f4%x|U1fPxy zZ{+HTAu-RoDzfEMYqPJa4OF@$0O%9F^Grx_%?)yzM1zxDbOdG$Q6xFz?0r?$%S;q#&v=MHN#EGhy8YxWe(KM@kZ}LXn%9^+)PxLo=u|H50REI$?_7CepH2DW;YyTqdL2 zsEZu8D2`TU0^?iB)tgL*B89BuLd?nKa0vGChP~R?;tb@o4s9pvu}IiLoPlhaE;3t* zgbPCdJcMP>{g(@Hf|6<`z-nD&OK#Q0wa7N=qR89U)gIAXE+dw3q6wZZM_IQB?72}M zR>oeWkUfyFLu4kyhoK0OnQ+bKc%kH2_kl#ya-nJGbD)2Mgdk(KMHi(7YQF?mlItZT zhA8v*k)oI-7Fa#|MBDjfQt}mrP(F_!GH1;)TEeNmX7-^f8cPUyNc>jwFe}GR6?UD>da7bh3w`z$Vb>=65;-P+0@Qp3HJLmWy2y+Q zU~-0L=zjx2$tZ>#wX7bBiZ)d_c{;Lry0`$@1-f_m4MBBJRwJo9(1Ov>~ z2levr{}MffC3_RFw<`R}o$4=wK^=_3vI-HS1y5@Pu}h!L$a6MQ*oyts&H~$tb}*xW zqKimKk)Bf=#CK2p?tv>Q2KZu{_sCnk2j- zYq-(E;f7%*&rpLWxV6*GBU&3$7~XGZVLB4L%IroYG@;~t{3!+$X`o^g>(qmIiTNa# zOUxEVdG3t&-!((<7(s&7Su|KpV@0d9C@}D5^ldyE(c0tL*CaD?E(h9d)S|ZgNgQl5C;SA<1 zO44!+TRsXW^9GQqNOs_4Wqak>bJbXCsh*MB>JPd7d)PJ0aLg<_r+?tncrs#2+db z#6ZmhW{u`J6EaH`STnP0RB?XSelvTm9RLKS(z#} zGaIg{%rctFY!6K}(KOz-3a^D3foN7sJ4;%k!-`HD-c~ZL%tWSD$&6E4TA5Kicccfk z)04Mi%VR)bC&y%w~F&SQH_#b!HbEuDaP_WhhQk-ZBZ8jDGg z*;lGKS-fP7U0ZcAU57BpuQ9@aTL`+IF2g#oCqhK2rA~Pkv&gIeB%)Q#X}9N1G*XG@C>=4@wv;b-FkTnYPF1`j=n}!y{miPxNl$ zG#6XOSu5u?J6*Y1!L(3?9%IJ1l<{JGM5FynL@hXtf=x(a>qNVq1&w0Nw(o;k$EeX@ zpJ*5>!;UZ1bTF2cTeY!%d>h7!aEH?c2eKAyrr>VMSiE_}0tZAu;A=2P6wz?EPYi5; zCxNd`12DTCDLD7y5(TeE2phMa7Tb=-|< zwJ&P{X3;J=VIe3q?{&r3!fX?go|0MmQdcmG06QJfW zyfI+slgMOvJ8Td=$J*Ar;L`RO@nYFj`IZ8hycrp}jQK6xnHVpze6$vVeubo4Cw|eA zqz6WmRI?!sNU)pPI8|(8HeFMht=Cj$FKMcXYhkhnePm#DWW^DvJZc`@)OA9eupo&wNoq!a!j_S^x=jfqXb3ym+jVKCkI>M6sn)kL3zf3xmM>EkoCKjGVrb6FP|o}++~~Ah1GfgOpj3`#A>({{MZR%` zN~f?1Ly^!O%$BO6F`fF3)4Zb;LkqJ5RBFQm>ug?uryy+Fr%W5kwR-G zDyCLu!sG{stqdj|e!sh4!0%&R;gGce?~lkoq2>fbGni?)3`p92sPQb~%&G1!B>0Hg zIwYE&^Sd#M?N-Is!i=npMpMN9NKNAtd9@O0Wu`@bt#Z-gw_QxRObJY8CQSaou$394 z!$G5W2smgXs81 z$}iMhe&~VjGNj;iE}TB2q|cVP&-=jB6wd#GUjqDsxC;!+pxFXnxK6?)wGY)e<Ds`D{cKtZv=R2J9SICS=K{Hoyolq`bXQT z^Y!DGC4hYulDcRc(*7<)C>rQ*_>-zwCk-bL`$e7wGHhM#*4Wm*Lc}J>BYHQ|{G63! zHUO(4Z)L@1_ff>{Ffo~OwGo3tpBZ&qQSQt#TXE7Q`FLF}uskzf445*`jRuT*_Kfjh za;(%0#HTeFUPSm7N&OlI3p$RCdHiMgosJFMRSU6WTcxJcSVC`mXolnQw{%<;p5wKl zWvJLu>278=1PQa=gQv|#LEGdRYO4SwykV$M>}V)izYns9lzAj}WXJU=l%9Yjb&Fgh zAIs4FnQO`b%uM!<4Y=J3}yi`Q9u%#u>*+}XgG8VLtjEQay+NLKQ zb9wQp=1fWI?+Im)P&t_`dzRi@U zwC38b&Eas~P;hCR+I;hjxql++b;lWVRc{a}7-)!3G#cU)4a`vx&1tf2lSm7KUbX2u zk_}b(d(`+xB8@`@17wvhu13b7G}-gWsxdqx!b&!$Vfw8sg8oOZ(*pj}IG&p|5o^7Q z1V*_Lv|(l0H6Y@UIZ0UYYa5_EltWcb6c+uUA{lrc{uPwt;}Rr*R?aZ0*IV7_oNMY;L)7n|kSO@r62M8APh2S_FDGwV@dXVMo zkxHzSty8V46RqBTqCwws0$SusVK|FG+z=22wqnd_0meF{HL+DVxmJ<`w)98WWNIB}q zJ=o&G*x`x_c@}&>7YXzLncEcne#~Yd@o2#Oa80Iit#v;iL3gZcVyAX(1F#nJW(8Lq zc$C0!V73w|Y@KYkvp|8cb&~nfCq2TL?zr0Ifw>gPSW2j&3?yxsa@eYl9MvH8SLDfA zkJ*S7sgGKxgjU+~aY&Pfvoo6@!cKvEKj()W^bZ>%&%(=Gc+pm2GiCu@@7n5%QONbI z5KX;Ufqbk$AW(>w!680}7w)(fK;7A@-iu#NSgMEy)^reNDxx7iqa#soJ!$1FsQg8n zjaO4N)EfkPuG2W%+jQkYL`}Hd&QLx$`--!S{C3Z($&`sBVWcxlD)D)Cdo>CJHJ#ZA zp^rgfcTMM(>2O_S#w}CWf++V)>ouL(pM-805GbzotZAk-Gyz>j1E>{6>YS*H%%~o_ zkXGtHNt2nmTeeoJr_Mn9uYnG>IzS|W$_--3+6ICJ@s88PGob43F?zoY#Gbj@*gO*1 z1{}@%A?uF>$OAYN)uGHb8G3zw{+6Wgp6Os?J0aSPbv`iS2;usojXbUcj9sP1A>Yq; zpRb#xJs`^+GABRgdn3W@TanSvffgL?5sg)TE{Inn;qqhI>6STzX+=a@i-h=NwoVmW znLUhz_dQN)XF)47CL^5Uu|=##!jXYlUnFyHO89=D4OJ}7%=Cf8JI~ry8Hj{2db$@Qa#wUVzztFeckoD9>W;IAaYpz4Sn%KnNU8+6knM)Rcp>eVZjkd955#!U*wjVpN(XU7~5hTv5OH$q6fbp z2Ljz|5Lqc+1OPqwa1hI}t^$Ex&fO4%Rn*Yl+!}Zf)NC)R%4vnR#;~=s&)fe4Qz)#K z!D<`_s(DIaJ{`$GB?8I)6?yV-WD|8!W5Y6lkb?=Y>RWpnFgX+5X0Uvwq??%yv8ieb zvpS>>4ZzE0*e9W;D-vvCh8+L5F~j#RRP$x=xky8Y=x<>ljab1J*xf+trOA|J3UJJZ zhZiX?8y4>kLbD=zi;3PfutIZBWp=veIRn{hRSX38RFDorlH&{6&NH4pH=;n^IY==K z!-A%{Tdaz9K{ZI8M3{y!1=@mFEz!I--9%;!kUIEQG3}w4T9^q_?&}wIsGF+TTBjpB zTos#-KsH+!#Tw=WIYX0~;Y&l|X2YYJW0m4)VMY#`maCOOXDPN;W?!q~lx@fg6s9*8 z+;!Ntt;x~jM|%! za=I2c?!W6%xlu8+F?&k$K8@^EO=b2sO{F@knqY0r!m8Lz#d$8((*JCwm(V$S9|mc? zCX2l}99Uz~HG8SAvW{Z%pmp-kXg)=nW^`goMx~HbWPg9jc0L%#P7id^u+I$-2mFu__v_UkHL$?9G;1WAAEwB8F68h2L6YRlBe1 zk2Y=bHq&3zDr^}61)fO_80WM=rTNq~7hK~A5eML1|!u*-d>R+Gtp z(M_z^y2-u?iEUv1ITG5y>}yqQ!*^p==P6^FnN_J`8?zlWbs#crt^vmhB`mGf70j;kDp-10S1{Y?Rj~ADUBT>muY#rbbp^A} zyb6{|YLs$jJ(09>mhRIP%!+zT1xrJaU@o&!UIk0L>I!BHy$Y6Y))kiVkL{j{gw=={ zIXd>Z!QW|-AcrHNE0~?Fic^@KtBTFc#HFq6EM2B5rZBrw6`PrfcU#+8x?NSYGFz{T zQ;i|1un2l7$W@h53)^?T-RTWd1iKANEeMfmiBV^?P zAAj}^8>R38<}0|mCW)Gmb$rNj|M^tR1TEnAEAX)bn9oGgJ-h^^66n`Y!e_e$;l(f| z<8~WM1Y;;u+!t-5=tW35+ntj@q9GxxuKhgZOBG9t*nl4Mh{nO$l=4}Hn$un^*}!0T zqrhlg)cJi9}(nV(TRMGI>(H=3d^srs$E8b>iAF5*D?%wBU5e_;c*esu^ z)nxKp;xzz*Q^5rwQ2|AnuMe`2^(v6ARpeG?_aHeqqK))FM%Teez8l@jeJa{nT!VxugPDk- zM)bpU{<9uL^^-`nf%%K7JglAh>#97wo%vU)?7vel&3_B@w^iNHcIKZT!H>+gBB|!H zKzYNz_^f`QWxaw_f}4T7rU|vZDw=k$9bkT-j9)5%P(fccSzN(8Y%xAi({z4d&bE{k zI}B5ds$-a~-O+y*l+bqZ12rA+DNn1)kudGAcCZosrZ2y@o_}Sao#YB6w3gXGB=ycG z3qz3dta)X5eauVg{%%dk8tXL?m-j9;@J&`>YZS;6kj!Z^;!&l|(nh}q7g>3}(g+xc z^mF`VTMe$xAO=27@5C0L+qBT927XP+C-a`oH_xY=1K6ixf~XGuqE#zQIReR4swoRW zgRv~fx&f5KOU};lL&_GnCP#+U_wh?iuxV0Ivr+S?X)VVZ z>s*_Zlwnf<#kQ7g2R~2~zz4D~v)I(^*O-2_75}x6$!$ZRCP&9*;MXz**6MEl$L+`Q4fTT0kbp;@Lo=OmNdC)QHtI-rt(x<9wGJ@ptiRWAt$VosGJy71Gdl<~Jg7 z_HC+dXK@3Pu_qIWbs*DQ%%4^)#u`YXHqPHIv3uFj8<8l;{7@xmY^zDUMKKIBtegb4 z<{&G+ml}jcNV%N@08nWGwkx!j|3WGjD|YC}?$^LK)q8tdX)fdU=R{+8yXbyR5Z$Mn z5vLYwSMRsb4Vhkhx3g3R%dvN4)(z?Zu=gf_b!K(l|GhamxBHr;`*M?Z+RoB!O*^fm zok{M!Y0_q!dy_81$R$maHcXp@EHl$#78sBhQTc=N2Sr4L5d{$eSCm~uL=;2?MaAK- zuZr?VK;cC|d_Ujcd7hh_w4LRpGl1_r?aA{zXFtF5+s}Ej%EsUIIo0 zsKj}a9v~ptbbH8hPOG3EUmRXlP>-)9@SATY9A^{kuAkFbLVXv=p!U}!rr!6W!~9;) zt?jF#pXiCZwVI^Lc`0!ZSMka0yo9)qp&yS>?>uFrlL(EwBGFwotYgI7K0j+R5l6}s z-hJK8a~e~{yrjh!F+ZJ+tg#fxOnBssyj|Uwj)4xR> z$Iy3#5JH>hp!dv24&F&`f0R6EH>6e*=*=Fqo6?AqFO2ezjyq z3!yA)g+*++!U*Q2Ea>OksbsOWStiZ%M92UtpY~+pK4JtQbd=U|9pw|meTp!Tr71%8 z)4WI|98oVKsAkqsAVW0?oSf)+J#v|lxk3Ix`zhKYE$IHmZ7}1w-NJB z0zcO`*YIx;@!OWQ9K|%YKeMbQ+gm?oC+rmAtrPVGT zOLvx*LJbIh5IM0Yy7zNm%KIJMRnJSfS95U(_G>^`u!}_1^bmN<-f<{W#_J+ zH(Jg8VeTur>o<(pDque@^Fi+V;g1X4^=lG;&0WX&tDVZlp{U*Ot=DnaG3k4_>k#st+;y_I?mA3c@X?{y1Kf2|wcfWdm~U~{ z$;v1OlyMJfHNGI{S zh_*}c;L_d>)t%0Ae{FPsguCk1CX+k3w8=1 zN8!=Zbwc^q2si~3m4x_I^0>a8#OWOF`26oU{#N3$gtrpjO?WRsv=m?Q`Q0j~Gq&UF zA9(&J!WR_>jm6hCo?8e92nPv2Kxiezm(H?&v~=aYl@K33{eGTB!|`<_N{>%$UYH&q zfxIw&igGiA_^jfE>G7ep@nN-bdw0MubS!Rsu55g;YMdUQxw`B_NlWh^nz#)FeGR^c&`2oHw-Q{^#&?CA*n6s=@5~gc zk@?y_s?DX^c`6+szE)FiEuosA?_>4tu0Gg}ukv(#vmIZ09wnS7=qu}m<>IfM7skh* z2``K*BgH!`C{_Dln`HE=lL6Yrw^3`eS)~K9(~prU;3PIVY)sTjIU;%<9X~ai&q^p z1brr0-Y_Xy$tBj`K6`1+cj`P%5)Y{l26`S{YudisVh{<^L_ULW2qjNd@q7DAeE z!xhpMzlWd??DPp%e8pdz#h;qR@%n-+ZsYa(a3i`D-%HRJU2%FZ=>vrFdsjBr=(C3M{Q6WQ{^Ubx@ug1^ z6iyNJX+nIpGB3hu&7nRHD5uj8meFaP?rzd5+UxgPrnv!UqZ3CmhHB8hN#2RhwhAD>lB?rlAkQPJ(Qb z_wRvTaMCI0<{j}X2{t=m^#p+3cF_rY>Po)BMJhF5qwLCfLs_2WEiS^hNyt)R!3@_dx=F@l!H<4a?Z zZ!Y%1$`2a{x&9R5G0Ll^pk>AQ(wcI-uB^4$_}apXW6?j>lwC%%4? z=hqOlMx_;>-y&$$C%&|Nv6HZiprwZRDvy&tI=DL%(nksM ze#e*U`~u;N1bHUoD~^j{_gL_gi>w@O<>lpXR=WJ&@l`?GmEz^Aj^qECGVvArtyPb_ z)$#QOp1(+tW4W68*Ae6bj<51`xtHThZ3qwI`B&e{`>*tDlzxJHe0A`wa?c{1A)FO1{PA;yXP~pNhh3 zxhp&p1^M1oMm{$^%Lk_*-<#rArx_2=^1&&{2d5w(oPvCC3i7=vZ#O~D^1&%I;&W4+ zxM6U5WNNx$=)%Z7^=GDL z&yJ5wHDo7-XD^P7&rCNQ9h>Q#J=4%Ob#``ad?GV3HL`bVWPD_LXu4tKo|!3bGh^eI zW~a|IOiv9rOioPA44t_!(h%pFBBeQT?Hd}NxOj15{2Et$VeCvprl-(VDDDsU2939& zYkc^^?AeiP+}QcM8_rBmHcSm&`+6@9&z2@&)Y@p!O%tRhhc8Z#O*dpm?iw2&X~^e# zbA`4-Lt$ceYWPVQ<5l`HHa^@iG&$B#U$6gh&y;!S!iA?CBHxX6r;1|}BA07CSb_4a zP3;q@cqou}Oxk4<>E1<$BQq$vP6vG#Wrl%Xuj?P}=x}mD8V4MImRUD<= z^TqR%PjR!;!(+v<=4%be#~SRp$tMH5CZ>n3HHBV#91Gkv(Qtm^;)sd1hI7Ni3VVm9 zF76$l7$4a?GIVBaZ&PFazP-(j%}w=9jScgX8embz_7i7^&lXLN)ek3-{xgWQ;>@MV zk?H#L2^2hg5ArBPSl;5)5N~83MuZfHFYepNE2^F`-y$6eucJd3$1Yr=Vzj;KOVcwW z7kNgbo1Ph(nwgypFEH(5sR7hFd%rL-eCIUjsCRllJ91%2^+d1drY2@5i(^yIor{_p zIX6ZFQ^m=tiJ6h%nX!rSkQj3!-q7V#+1LcViyBfL_G0549UGk>AHxO;XL&-e&=dU| zpP8Dt5MnM4jj3)lJt&;6Nz(9+wg(ZYSH)rAVHpI>vm?{PQ)81e6H^)xrRM0Acl5xi zVnjf^q6SVC!E7GU0LwsQV;6E3HNEs1MUbiEfj+A9lt34>ep}p`3D_QyD1tWV7+BLY zQ)A=jD2FC!W1GBdCe)Jf$%N;WQ8cQzCX?P(`Sq!!-%#sUZ}%?MP+8&kx=&Y-P@PIv zCR6Us_a}WSm8|zZRZC){`{Pm~QSKci@1lb0?S5CSuWlu-!Ebh>szBvb%r8$R)Aea( z-Z%$~2QJb6ZeMqV;^`{ioT{gr?bUus+Pjvx zXNOglU#cc*DO0Vc?oL-aU+-?TF|vcYzB1{TxdH1@RYj#5ybegn7IH73w5zJD^f$QA z+-n7HNF`gnOILcoF6I7Z4UNUaX{_>l$$nef@2&SY*894&zflc02wsfl*QcZ5?4ovA zSnh`|tNq6E+J9_qdF^GD*HOP}K3=L-RPdZrrLeYy!WQky9!s-87wN7Su1mGD*0cW^st7%M&Hc%A#UjCPmBCMb5`G&7_^ktAE9?D= z6g_2FVuA2s-|p6=Tm7b#n@D;<=zY3A<$n6XWL0%_jUg>5J0O1=+y%B zZ36yg_YnqeaJI;IJqRxpoa+suk^oEK2)g^!KEK88w^%{2kaG1@mUPFGe1g5oZ-T&> z*OxOS(PA={O!ZkezFgJ~5T(2u&kfz!Q{IcyQ71$cJAB$2y*2bpQM;@^W&N`Ltd05u zzFw?v?8_SHnSH2d9Yo_tMer*WE%sm8%P^u>ei$`=@50J0bq!hm!$4y!mIt@UYm%Mk`wJI_v;S=Gh(#XD)Q|?>$BFSnZ-J_1wnnN_zq-+v#?!TyqZm2f*j(gMAz{h<( z)Kw>5ztp|=d9+qt1x{_E?R(TwRU^{4C2H&z63LXR!y8d#; zE}iD5Am4n_j{wY&@K1^4?bK4`m+vKC5cAU4l=+qOGBcw8Kao5xDih>)*zg|~e5-A) zSB$Eyr2DITlL8H+_z%cSqhO}0-9J?(_ohvN+Z@YL>wZadTqP;F+HYy}$!&g19aYyw z!;<<39&Kk($I0W?*-$RF`Zex{=o;-pa`be>{h$*AjqZ}CeTME!!c=1O#rRF zl`3le_S6c2VM#p+F#VlDriUuDAmAR+5UVP|3HPh_nJO*PNz=-~l>3-80;n1Uu5fd0 zYZbwLbFrnNAA7%}-ltZlwn^QuPt^o|2V0_>ru2Tzy2<24ifviaw=GHNe|g%M78FCg zQ=^tA+=nEPQ6FJjt9|VeX;jv~kVPvO?xzB5lw}PdxFx8xA%m7Q+#4-Jc{#0cxL>sB znyTt55Z5@E+ruPPAQcb#FQdTfsxz1!^h5OchN%F3?ykD#jrz)e83$Xc&^B6>c^iMJ;6T# zW$mt0^;VS)1Gw8uwO^+DP2m;#*W1nz=_G6{SDpUWi2C$k+OQ>*TDM&8cOJAB^e6eK z5OHBPa@55OY71l+po?)S+Si7Cg?^G?@zaH>$6i ztls_nrTSnFcbGXWTX@uX-}~vvI(Lpj>ky^eDSOX~PW(ZL_lr5)~9 zA58n&wCJ6`u#6?g$n=}av`%6`4h;7r6o#BV7Jg8lC=Z0S9O!b$7=Haj>v$%!()NBkbhY#YSId{yIL~2Sqvp2m#fj; z#;L211|xKn4NhyDrkccqt9!J;X;ABHCDUu&uH-FO98Xs~p3s06P2HbUE*Lo;JFeUB z(K}wJHGYHp3P2y9j{6Ea;(WUDc6#go-a#r4X_iq*Q8GCeu_Mu()Q7b(v#B-Tj|0MMqIU>huUbK-Ct0JOe(C=0B|9i3|Q-D9d)_g!oSmM!tKUL zA&sYXX^q%daU;dOl~VNi{U}{>t1)qSha?fnI&;iFgQuHR!!1_#3Ir={U~;6~r|(a? zSId)vr$ji2a8o};^Rl71%cyq$1W;DEufX%jC|!dA;$_+>Ew#>|soX-9C8=8kd2EWPbq<|2hIygR=A(nD66r%h-U!c zzSImbYx(Fp>DM0Ffu1XKr>-@8~1K4zZ zK;X@&7`{TgH{9o8s*CYDV+0%tAgi*u(UuPPr%M2t+5{O=ZW$w5Ue&J|b9D9cb8oMDlu7gI|m}bR_lAjJov(2PmkL{8Z_0Xz_br=>7TB zL)5{fd<7T#ng&&{NDx|k#INe{YmfV-J1`W2(;+}Y`&QgHmT9o~pYXtMZ^U=3xd10& zjf-2v$68wa@@>AQ?pD8ipWoWV;FhNjXr8v$?c{~w*RW>b&cJf(nW4R4!ZVoo7Wo2} zV{>m&&AYIacA%V%q~obr##Cs-jQd}VhGhhb`DRe<5(K>8ch&iw+kHRdhWMM9!@qF!~zppY*z8G@XtSx`0-?!g)T<_cV`DYB---FD~V!E@N zaXr(o#ae2X-L$yLH&8R6xovxcW!d7Z_xoM+eJ7|nkq-7rwXdeX+Subh06SZ{&ac^y z4VoGi+F`1YsNFv94@7N1WlJ4W{4lQJCckuVs?|`;uupq|+>cd|3v+yV%6-G9Yq!_> znp*JdJ@?Y;b%&aO;!VtlkY$B?*Ml# zmQCfhs{NFC3r5@v9|TF~BP295g~5q9(tbowGH>R5|#kzdhtc~ zDmXcaShY>S+1|{g($}rKxnI&;`|8bp>n=)c!yj_5&{_3uNV$KQSPn5q(ji)^RmT_O%1T=I%Bi&ZPTq~H(b@4aif&m9hnUv5P2gjq24#@CAGzz zRM1LL?oDUcxH}=xCCSsLDX;aBij|tq;P28VE%zEQa|0>pymAq&-HAWx;ZWJEy%%c1f`sTH6e#g-u|Rm!US{d>grwz_vMLUB6cm;9{7euzfsda6B@o*@~O zdp~VCm!q7kji{~69RIQ=t*S}@LSJ*u=`=0{+2%IHYNILbn{%HM<@rX2*a6qx>9^is zPN?^T$j3yXDVK%iHxcPryh)uR4lV0EZ;jzYJYn>*sIe}EfyOA2WsBT%!G9)c1AmudTlgEH&A^al z5c>*k_;bH!{BR@uaC1XLEx^LH?Kf}r8yo%7Ccp6}zZ3vO-i1YeC&jcs5ZNj~p$Fr_ zJq&;w_CtZJ)&P{{sdc{ZR==jpqwXvhhlN@;){3{HCvI>beE^8DGAkn8$kQ#{Swc&> z-+~&pu>kgEh}<>E>E}*Ms%>(wpxV?A`a|`8cfDo#{AF20JE=bJk5kd+Q3)_0`nKoc zD8xYwi(A`>M5C;8uX{k1E_a^;?-w;%)X$Vh;q1N9FQV%=_%-{jwO2oY1U+pXYN&TB z#VJ|ZrqZfLEnNeE(A>}6SC2%bxdtot=KIrX$-BQq>(Rh|;eH0z;+$B-Mc`Bb?*1kJE|JN{KKty*OTrSE~#w{XDCM%{_Q0sblfpg zwz*%SLhqhCs?q-|-C2`bci6A3m5ASrzYi(TL#-Z`xA`jEY_;f&xisRsp@Dffj|7<< zcE?gm?cI)llO(_S2G+Cp`;~WCyMJ=uL#%roms+wkDJS6~EyKQ?MmL~&0D!}u?U|PK zeduyYpLQQ`Vdma<-)PypbML?JSlX|`@!U|ajH}$+83CPt_w$ZHAnUD;S3jVnW$yFn zhZ?rMyDzdRzs>#l1E)|V8a_paE$%~<-RORrac^<|ll2kmc{MK^Q|s{6G`sga7@#hL zZB3(i-9J2Vj3O!Xh51@vd)WK!zOj~8oO>lYE9#E>LNt3XyB{S4YvLxqy(yZ&71rXC zRs_ys_j;Hq4gN0ZEe@^)1%4z`#WlP4Ln;a*CGm^qKe(nAZrS>q#ZM(WX{cv z*A{6nb%~osVZ)J^7OM>lHd>UC-liBW_uvzsdI&}0;|ymx=&%79(OR$Qx6pMBeS`ZH z^t7%XpaHH=qTdKy8^KqK>~XKeu-M4L7+S48ZyB_9*SLQ%0LhkmWikm=VS$YMBgEFn zKK^Lj?~47^OThg(A3p>3?lv2(3>(>dF7-@W1_Lf1&S4vlPn`~f!ctn{eo`xGe#rqF z&*$iQ7|+k5C$2;7Pf4B!&0d?Q-Cr7Sb*Ze@Vr3*ElN@_uB&n9MPey|9hLn33h{b9r zs5VBAYEb3SanTD>?#DsE4Yo8S(-Ua@opkwXn^dgChcWjrU#!{z+<_sQ`={xl=9ZP3 zXw)!ucQycA3Bm}u2ci`&GGh2z0oj#wV6{3#nL)dQ31JZm1F_oumd%IXO-|(VZn~nC zi>2-(Nke$4odTha`P0uEWk4(3n=7?Sg%?!wx0Ug*T6TjB+A!=jfEU;-cJHICPh}{x z37~%^xDf=lhfC#CsRBWA0>ZubbKHLHtQGupBvWX>+kjF>#F z8V^$=`L|GVo!mIox5@p#Hb+}YsfXWy`dei?%5$-gdY7cm`2*2?{`(l+`mABJb?Ys- zOPDU41=4hwkxw~@V5R#;ax|G7Mc7`Sa&MyR%c@V49~$}i{jE{Xm$@W-ltx(8NVZm6 zbw6j-Q4@OiXI<#&8}3s9rs}ikg_?NxDm)D|_0_~NbC40eDD`4A0QI{OqS@#NbXOcgwwY&Gvy+Px{6Y!#z$f5Tj>hD9v!EL;4r_2%2Q(y8U7!*x`% z-95juo`fy#KUukiGgWDhh4${-jx{$q{g$K-^LH8g(k||Bjb-p4_eXpyAmEB1$^DyP zwPtS_$S6+|ir5O=AmTx*)7YK3Z?u|g`U22J`rd#xi_ETZYcRSRL8wW13rp~U46ZXZ z6Z7MP3_{CYt5OX|)E&71*O@16Rq7TQKfeU|Zh%k!2Vzz$xbD^D-l3VV+Ua-PfMDIw z>TW*v5ON{qeg!a#6N{tDMI;`Q!gmnX;MUeQ_%+6$ZI!?l4H%yavV=igqjt6kXD#mA zU?4t4HjOb-F_ju5lxX-kGWpd(6%WWzt4W3lq})HEiK}5i9g5U(zp?bH=&%MC?r5FB z>{T-QQpv?@8DO>hH>x;@&cY<$*z6Y}wHuE4rFDwi=r$sN(EzvlWjp+?SwR#>b$#V_ zu+sfMbZISuesP^J$h+sOPmAT}Z)0rh;c>*f&s5a&wi*;iwu@r_timc->^_2eQ`7BN zH2K5zqgLW?fxv3id#jEmnAY?uA;WJ+bGA(WfAJ%T2A3hjCUGXMS^GL9btqL0X5Z#M zaLHP7?t{Qp5%0TXRXX>%I|XO;AIyhlUD?0D@WQOR|z0vz^>*f@45%J7i(8Y1z09e$z)pLg3(>A+Y#bqtKM zE8Q2Y6N}w{-h*CxL_!=K0b`dmrdu1%og4L=*Li=7U&r1(zpa(K-<)ReBV`x4{}6HR zR@eN>9y1=^dVdlZ;{jHfYK)$irJlw6&1LWMb+rL2`17*V3#nvzy)l4SK)Q1b0Q&wC z=5A}XJl!Jq!^vY<2s~q*h%j$Wj@mjqahHtrUudKsAo!n^ff2p%d1$*vHN-?z6_zTX zH)f4iR%=f7y3d0=^IHE&AJ)=7YZM_yqnar2a}lZFoerd8v2W&QXz1#ZRuHGz{rUZ) zA@iFnU}21af?@d>2X?Ymv&RH}*W2@A#HEp}}-0&A6v}LmgEyCY6 zTnziIggpITu8LJ|0;bmE7iH27tn6)&poQyv5Rf-Aie=DA+D_A!Bu{ExmDIjge*_9- zZ_+8qhc2=PClF$!Qzd$fBoHkil`7UsUku&{eQ4)i$ZP|>MZooErCe1h5y?(2#k~PD zhz-|lpGw>NFFgQns}Z_<&h*apa75Kdqsv2%*I6whD55u-#cOJO6B~i+-1AxGr8#Zz zdw9woz58q2nQ6o+{>F5zR%_Pmm1A6ceU$HK<9weZADfmIZ=+)GzIri@VwZBiY;;N| zZDvyIgNLiumI!Sp#NS9avfVya(Q;*3;@^ctxoN5*$6Z*=q-fgx>MAIthO!$#fTX(% z#SAAba``5|q0R5O9s;SWVcjQKE5Mpg;71RuH%%f>aRHpWwwo3hofatzTDC_8GEZsi zZCG_d?uGodbDlsOg+6$6AETpTq0Dc?JF;2cYpK#&Efb|{xo;UbVRyM;aPim*&1zh< z&(Zu$m93{<7p(lbRtGViHM20U|X>sgIn=U#j_ zZD{X;M!_QO52Sr9o@?QPHgQ#@S*8aKevf5V$qk&FT5Z*=?hux;2E!9?3`;wtkQg{* zw1cXGNG-)xxQi@v*aK>G$P@NhDMxre%qI$=gzd9od%5jQAstAv9%dRf8!DRxUvwg3 zpW7P2ci)xZy9W3gWcBGTelR9h#JbAYG5$bZ((7%_x={j%D#I2A6unjME~81NK|YBU z^1s|_U=tG#;M)U+FQsUxz@{ z`;I6+PM?2I)*_|ZHLQIX5;JV`s1e&+AGV(EvEC)Ms%X)2Rm)3*WE3GR*!m%BOWWlc zX$z0=(DE%HU<#2o(s&C9BXw_?eTdd2sNkNIfW057O+R zx2(xRaSRxW7F(g&hxoYLvGXjd(GOpz8Ru`^UOxoHfmEHZ6aQ#Batqa{!`-@TabicQ z!enY=tD%oR7B?*_uCPu$EWywigS(rt%E-rrtCuqg-Yev_nz?B#lG;&Eee%|5XlFIF zM!>Ss->8+TRjg3+#OAUM`$=imSe0c=4{7|IHbi}|?mmVRVc&+V@z*!_Cnl?zQ0kbKR_0qBlS=L2n5APgR7* zFcDX{X9@w_@?-2Kqmn9Z^U60FZ4}&42RrIUQy$6M_ z#*gA!PWx8^fu*f}K&BaqjY?$mPi?JiEac&GmOm@_O%3f>Oj4IlNpOFP!6d5EmJSD^ z;kiW|*$o=4V1bCkhj_r%7;Y(x25$6G{LKsO&y1AyTUbf5O}2P%SY~l@gi0DGv3PMR zoUsu9HNhx(TMT-20Xsnx)w`wTmp z*lG1zDwTIcTPjucPTj%FeNlGS{emgAEOmrI0r)k?;v{SPlsaIWD(%(&%)Q!%(`rDy z)cW~R#$_8b<G` zjqw!;@KAS?4N&h=Jt|0P`kq7!`UmZhSMe=p zjW|H~fKun7Xp($&M$m}Rxnxj;9ND-K>a%gUl*+VHhCRlNc(7Szc!Huo% zr*W=J>ylO} z`N6}tazAC88F$d{Eyn>zYwmZZlc@tX_3vPVn|I66t3VS} z9iQ6YXsnp|WdOKKQ9Q7jNjS&AZysgfwtTe4O&W%*t`GY{0afK<_s;41BWih5(9mmT ze72ggRLA~8jHNpE8Iq`O?Q~09Ybxb)d#P;6_3hCFJiF?4Rk2yQR%BUA6s*l39xV!SpI_yOYZ4{gg9^6P)_ z5owM45??bd0sy}Zo8eP7O}>P#d`0f{u(nmOn(LSbpV~C;H)B6H){`G5^Xz0LMBv`N zUgdfJ(0N6ybnjh13KRBg+kAuji|4_k+%Mw5(KG&L-riD~Y>29O51Upn7n9b=SF92C zXr`_gwCa+l;A)H9YcX@EZV^5p7B62=!8%4*q?AKcWaA(Z^nhck1n(w}YxOlB_jR*k zZ&aK<@Z$M7GfTB^cx{p1OByuNar!49v+6}l()|Ne0H{+-zGc0Bw z_Ij<~w8K*?cG7ilBp8L0igCRguUEw=#VvAk>~O#MAUyXkNNU>Cz$@hi#8+ zn(@02A3p{H{NY_-ETCeIjx{pF+zs6lzU-;2&g$#*#n<_pTMqMS#d<~WYGgAa5`G6u zwL!{!6WlV$f10I2)~*maRqpdhNCEEEu+|p5Yq5mZ7x-1U&L9_!r%L_@JvA|}?rX60 z?U35~CO$A_U)h)0Yz{vN`=x7{(`r+pSGsd)2Z6BBYo$960B&#_a4Aq=gt@P-iZjv? zL^b;DQgZx{S-Kk{80UWf16xo9>wRmp-O`df8wH~Et^QdpKArZ@0zq(M?)J}W2 zkHa2Q?ms~XS6yS(e3h8+{aUFulsxSkk)wXO99WJyiJs7y#4&sYULEMSqLEHBFAz1X zk|jqzXyv^Ul9pXoiD1Xy!KZbt$O>519pa?$NI=Xkwd*j|DsEg$yPMp5#2y&Jw*cs6 zjG-YghV^PiA86tA-UK`Q777f5+Hm@Xr%#{ri+_kUGVSkP4+f)}`YLw)?A%^kyW_^% z1|#rKChJA@_VI`NdB7*C|EuJ0*HaragNIyrh7{W-C*rdG+EUE&<|eQh*A9Q-$&evW z8#&a05414i!Gi1jvhBXQR=Zy|KEpR#JQj(N>)s9Q*0C?PS-b# zGLb)hU$U{G`NjsgDjs|Hjt7&+ZHCSqOJR)JCx#>}LD>=<{!J^vfrD-UKB&^}Wo#>2 z>%Jri!b<~BHPF@jLnH#=BP?q@cnoODrSIGqD-0mV5Fh_b%7Ob~H(Jl;kH8yi+}ADg zB@T?Mq2~XH6o}vR6np3MlJ0YC+L~3`8m+4Ol}AuBt>T9(So4wcY|C{xk86d{-u()T zyI%V5>SuEnN{#z9+e5J$R|o6m8r2(lAR*;ge$-B#jqYWvLTx^6Ku0^!!plY$bq`aW zbMK?L@_e9zEofDJp1&KO#p{RpVD6g{{G#B_Is1xW4g zk=o9dEiCd?T7L^TE!-``Vbhi$;e?0E#Ao;mL;c!U=ARSzgicY?DSDi5wBR%)9kf*6 zR611Y+MWn_^@Fgke9qhzPr!T9j`_RFfn--BWt9p-x(RQqE^o#ZUZfyT^GV z-BpgR!--uBkN@JZg}Gy~&gii%}(Ql@2E3wftx?YMOs8 z8C^@@iGs!x{QW+paZUc?oue`^0mJYX9iTQWs3z7KBvyZaLgMP&PA~#v9`%IJ%Mg0* zs5wDqiOB)?v>bTKPKbOe<-m7_I@eZcKZZ=Y3{T4$CEV-^jIwk_BG@a&d8HE%jg3Yp zEgFX{ow^8TEa#wNm@k7ODibf^@Ao0Yy!u>U8RP!1Q;Mz*pqP)w%GhPN_?;l1Fq4Xl z9Df`%07VSP$9aN<<=CmTaI~i(ZsLStWdAk5$SWUq`os=Q{a#e{pGv;{l(qHf2njZD zzIX91j&awauIHuXDI)O01&C$`r*rBl{EZ`+N2YYNDSA-iR>Q0xxCWT@y@(YH4jO-& z*XiW>d8fi(mDep`L36Le!n1N_mH4>f&>uXFLr)oFxUwjZ=knSrY*&|;Q7@jdQ9n96 zgqvN){lL^K$n3dOvQ4@QwdbOYMJ9g2EX5!D?`A1}Z{W>i&ZB0;4kL%9M9;%=nk0V6 z%+v?}JDRECCo%YY1qMAebl~Ftr;N<5j3iIX&a2AKYs+t+sDUg38M&Yz7Ko@tR>s&k z2liV`x&4fPvYZ`0s=W;BG}5!<@zEON7gIA6e`O;7&z~0g-({+Nszv@n*8SZ@{c>cE zkpHUAAK~wn5>1_5=mA=8;$M#Q|5hHLg|ipjWfK=mfYA?e0LX=lABlf8x%>J5j&k?% zpQCzO(v>9LQ?22vy|HnYCdP+Hrk^s_Dzb=w4d)s+`b35Kyh@U&8v*#u+%ue$QPfv<69-6!M!;pp$|12Ze6`L1NEBW^8mESwg zjVF`!Jr);YtzmR%_QFi*_svjzO3&y6#h?%bgQDy=(4bF9u)B?7*8BSW1OfReyqz_TlsIMso~NulYotzrGYiLG4WEaJtk|TuYZ|l+Q^63o;|MmTe%4M^AWuT4f7Y9o) zDB7#pCYJ+(V=4i}x1L7x%YK*nN!vAN^mFBjTY&A%VT`?VQ(8_2q=wCNF+I#9fU+NA zB;9_*(LBMIW5In!4tG6`1y{p@%ciSbY#2PtrtWgMm;KadJX0m1D|U3j;6M6(4F4zT zw}~H<)x}^3to&|jV0!a@Ks6Esb4m_56Tb}MR3?6bzu%vl%%j*P->XX@sOZ;N7kNzc z1Fxl?XM||~U%4V1gzuHRqu^8JToE3qQsy!zC+u(RVu|-rW%$kc z@MTYN6j+{*_@bqSi1U;1KltRup|Np{b^9Uvu?c;&Ql2-&gq#a}?Pk{4Z__8b&6e%p z?{~^1zdQb^C&c5FdFaB0YfRWrHr79Jr_^I%eL(QJZ_Tc1n1P{z03x(4H^4w5sAqb3 zYHV_5VoD3SplD(c`gGA-XF{B#8G>BoeG&rAnkt?$QcIlonP#NQlQClycgOBTOXC7g1MSrcM>(G-C`4Si`SS2aDYdc_MpcrDh|^#Qx`_YS(QFp zW^@!MX3k?gPfw1FoYivC=-9d0sUaPDQ5-(AFmG@k6rVdgbYX0CjAEB(IWsY>*w&$` z8L|wI4P7{rINCdyKHAmO-1arDB((9GVU zGh>I(V|^)Na`y1(ldJ3n4mKIGdn&#c5Zy+Y?|{> z?Cg<|vy(H8Yze}V%=}DToV+kH!#=)?<1-Dz4TF4JI*nC7a!>u4sjJZH)$QTL#gU8C zBQv@UPhPV1UVJEg3(cko`gLw(Mt#c{a`_XvY?C2Frs?KK#e^qmn&-{&=;+kQh$e+I zV>AU%c+M`&Ogx^MOZ0d3=WcG#_4FtDyPGlt`R=CTnZ(KLK(?!p$QOGG1O3H;OOqoB zJ!SGa5(fqg?Zs?YzSz~980^UR^bYnYHdh$v>B}mEvbHrJOq|J$pPigwj@!CYd}osLdgxj1ol_QHtpVrnLFW_I*oLLCh? zWINiryA!#-j$A%(gE*ktb75DDycR{U&{{9fB(j07obdXAn7xo%<$-MNz;jg8U0DN!tnDvHHK`(WW@Ti1Z9&F5~jDx1~K zoMASjFP>)>FN{ouUK*&gI*2#&C*1FHk%s&DH8dUIgQTn695+rr+YJ< z#g2SiPcG3mFp%j?fVKVE#L4bl@6mzI#0jP@XZS!xnt8R?9N;gw74IGzn<J2x!d_(3&HlK_8-%_U1#0Y`n+`Fp-Fb~0m{?z%0-mYcjl%v!76i}a+o;R%83M`np%7igw290N6S5qZJT?;M$(w1REwVrc?xo-%zBmjg^}qi99_ zDWAWAuAW@q;6NB)MCI*JdD}of*WV*t%yb-O*n@?9v)~@s|HYwu<{`NaK~wbvcQvR>r8-UJpmNf>8?UwrZeBy+c#J! z8)qRmFxU@5W^!E!hD3YUQBi27peX=e8i3&5WZa`z>^;$yDdxt9&RiJj%HNjg>KZta zIMX#gGctA85Z#D#2Bu(`96DGS1XER~vJ?mMVXh;j%7RRW&4vD4E?eyGJ88)|aF8(s ziPaPnTUp<`dQY@Au5SyV<4|Vbq=&;1`_?9rw8&~Jw;xQ(odZ%VVW@;p=+3)CZn+_+~Uo#awE1LgozEws>~%iM2l#nM$U=OLjF{) zx2Ml~*&c+>&4xBHV9Ta6QJSq`)Xc=0i}^4|CWGVrEu|^hpJ?yM=Sr_Pm!1v=@@mXW ze$0-e%t_%gM%Hv7^rX{>s4?hgW8)DmGXp}!{#?EbQ0TEa%z`9{O^yl4uC{hqkx5E1 z8F)#eyU>$ADYe1Sdm%LsW{w9|p3QXhSiK_cSh$@Xn@XUl@`=uL5tN&qjPa=0J~0vK zr`S{&D7FuFA6M_iJ|b;xL&=Y-J*`m5IbwCK6kjNNi;yv6YF$RtA|cr_a*`5jjI- zxFz)|LLXDS1o}q9c@uVxiQK8Kn5oN>fCV8M$}vKcFicBOHH$rM1*TpyBLn7{$czC4 z^yVOgP?sJ7xFhrgKSL=xREA?loYG3W3jKk;TLNx$_e(hp;EIG-2H|B~!8l_;P^_mB zOo+23>^oq}j^)Gj8OKyAB^|=y&Q32u0S;tUw>2dSoddmX#}kEtu6(IuC4^1%oa#rB zgOkA4)c>Y@u>%2xMqtPiYtoVE$p#FN?1{KtbZ?LDndqJkwKW4nG@{()g0wg~I!6wg z(m6fBByy+WU81`Qe5E^Rn&QPh85`XJo8!B?#?Ox2BW9t=7fzH0z)KsFA#i|$fd&NG zax4}%Z>MX4l$eaU{zz{@phK<^59^VpY|0BADoBeC%>AGdkWqYKUxEK*N{T*RFAPw3 zqk50ldWxQ%$o5DXElpeV{$f-4OPK;Cz@SkNAifhls7zCrdWOc~J@Oz00cFagO{aD# z7e_8m&Ri-@^PF&<9GV)s7!QIz1XCcF=sY=ys-yvk6~kf?>2q*U^VwV>lke&u=*uU> z>w=jkGQ?6*Mes`lldc)o zt-W`kyEGP!v9WlD0VX=4r=m5+?Dd}C9hYoNCfst+1c$DkN5Ew_Y87b#>TvnGrF8{Pv`&%)Hv zM|%T-WFwZIZ3-+s3rjEL`!g7P($Es^v(sh3>gqtunal_pq%`ULV80oGJsAKM)NjOh z+YH{6GqW>%dm0Qx5@mUnVK*@Whf(FsE+rz^wPC^<1C_M5L9a)l{f@3v%rbTi7#wn# zHUS=Lv@q-#Zed~!a3QHNF$JZay(h}qtQrEp$VPlW3*Q%EL^&c@L`**m(^o|~AZL1H zaLYw_f^0N0Zxo+m2q7m-aiD+}-FKofQH0Q==tDM3`@+aHVfIMVvUiY$3+&pSu1p>) zBN(@Z6B$(dh{$?|?&&wfxFEY&HAO53Xv@r_BbiKpw{hj^iBX&aCMa$0Bv@po6b8Yb z-fT|^aKisNM-(2isAEAjGJUAT(jtFIz`t1WHhCRj7)g*U5+pO2R|f;^(0HVG%XT#x zFK}h@X3vr*)__fB=3*a%5F>jO9RYPUWFjWOOzhHt*VzNd!bj4UABZp|0hi0kl7y)Y zw)gjuAeP>XK4D-8UGMBV+Nqoa(vf?6+D$xIGp2Z{L_l$ySFmgj{Y@zg(FbFX5Twy<#4pb&gR0cfcxCSJz8B9>KR9@gj~p++=-pfa1Wn;3;#j-Y+dO633sbXG8sS#LDQ z5I|`f$Gw0$)P*{fhm+<+eFZX|iS%ikoJ?M{8q851P)3ba&&==Ye2#SzK0FvxFV>0~ zz%WDj*WFV?lQAh%T{#&R&rIP!i0PvwX@bdJ;&0Y`f-kX)XNIPO%Pkk-PY(Ra_RE&f z$X2(po01qffPpLaIE~E&-R$hdtdzotDa*2n(G4y#D9fy~E1wvboo?@m)ZBs7Oo~bu z)n;H8f!*X_z07Biw7S^6K;O;6HZ#bCswwpovjGdt`w`jJrlQRx+VVZcOiwY}nJMHW zO?mSCCG-rSb0%`1sd-cS5`*Xvi4iM07I+lq1<RMY69c@8!v;}LREf@oB!4_x> zoo@@4K-;0o z3I=LBR8mgl5sRYTT{3N$h8N^wFk(xM?SI0B^Dsp9y!Dg;iE^9n$x$(&e9&fF*$W3 z*9#CZ(P1t|wU%WlceAS;+14!waRSl~=w&)4`a~{Y8X(}0N5u@39-HSL=b*(@lrms9 zm)u~H%rHoqvXQv^#L$J=kwm@|OzO(Y5otz>K>;;Fz03rdWCBbwk#QMdl8H>q$g&JD z$wYSLp~TDt{;cAeOHw3)T_fHayU2jYJWoOK3|JofMHwwhRp_a4Rnv{od%Akzo;``t zQF#Pp!Z#**C&qh*rtdU2R;$_vViF;m^&EoS8k> zGXa(1HZ>F6rYDS_^%Z*y89~jVxjpxiHRL7-uewGZ)603**d%apuA}b77phL-X9I9c^9mf=jsJ>wr}YsZOG@ z+FTw8%2Oaj`kw1&A?As!nLUp6ZS97;@=^H>8vT@9VXWo`5zp+GJAq?eNRwf_M6A%< zAEr4-5y*7s+RzpwGs?J@*^jX=E-~2OkIE9*QPAik&4uwALFF}-0*$@4MFOWS5;$#< z|E3LvH8MfVoF--S))r~~ZHS)iKzDCR6^L+NXP<#h8goflClDuaTkams*~CFRX92Cm#p8#7ByBLTeq0y$@MSBT5&@R{eySuw$y&p`ESCKjfdo#t1 z767y6OvvWR#flQ70i(D$HcodU0g)IRFOE%5MH~xi@1@}q29|hxNlU_StF^;P^qJu? z7SW|=vXWRh5x7~lUt;e>ShbRe15KUo2k%1S z3~(@_Madn=_jM=o1DW8&H8IM_G^iAP=Iok6&9BD_L(Ml{ool*=Qhir6ANu2To_8dG8{(1GiSmLbgsCl#> z*l55Eox&9kgFRO~KZ0#hES|ut$X0wJv_(XVT*G&owVcl#E%xX826CB!V&-TD%*+%{ zCi+j}M!{gnp~sIDwS!068-|H?geXs!GUZQVERnCj4bN(SM**Z%5*{bqW&MLJB=wx= zz)_~ZSRqkLk@~<)^^sNZLZ&@9pfW5xQ40-&JWQVYX4Wm*@LOeJYba*L z{+_NvCaNG)Pz_=Q<%8<$DdL7I;sqH12dSoLx;!5#P7PhsT0ibo2HTbCf-MY^YHnrX z=^T*^W>C#_6=+sY15zf#*_!~-WYosE6CzNoLzoylS>XY|Y- zhk*#uDc{t60%6iVz#}pMUwTuQWLO9I*`Mz^fr5n1$jV1oZ?UhCNt~c;7s@sTGd*~V z5{2H|(W5e=N+O%Paz{gA9)E12YhQ*nH_{UwnKoSgSnQTP*Naa9-`8!8WEaS-l|s~5 zXJ4i-kvVQ_`pUGQOnHn0psL<0e_{5F;Q$kRX6yofx0CFXQ12W2=sbO-XJJsd?I_g_ zdueWCdx!Q}4QRqourAxwEei&?WV=pKAPk@*kw4HvcCv<9UN^% zFWzWv71?<8+~QqB7?YyiFq2KuO!nk@Oi!V4%>^4EY;2i+v;|vAXNlFypT9SeYX^!p z{#+*0tX)bdFxJPm?g7liyg{_U?v#G`PIH1>+Qvd(=-fbm$?RmZVl8FgzQob~ff!hGT2l9k_2loNYlmJlL1kvcMu%{W?E%fzk5)Fd{ zq(PQ;I}*KpIP@}&*vTi4Gl{d4P+-}BGnuvyq)(Xdrf9xx)i=R_vO?UfM%I)NjtTnY z#iGXNttGlb7cz#JfMXr{Ffzk|ej{O1MQO%VCYS5a;J57n8w?pDz-qFf3)bHccHW-o z$q0%O>f0`#1C62wmgdWlo;_czM;&KB+lgX}fujs}OVCc_vu&pZ;X+?Fe@W{6(I~T*Ca*zkI2V4oobNTZrEZT)?1Y>(=KhK)cN zcaO~x4~7Ib65+AI5fFsoX$x9gzDtFlYF#GUNiMx+?q_JgD8VS(+avB|i{jw+>45za z-HH*A(kz@4uMwo@5S;-FE#Y!Jw z$%v@|^vuaZhYoAzX}%`yp?HqjtmY-)Br6k1v1? z6`9nbdl4apS_}cjSm_e{2O*uu(^W=fL5vxQNZP0LmPk-(PBk^%*^UV3iHOlcv`YU1 z+Xx(s^|;>KtwFZz%6qQ?9RRbCIvAA3MdT?5e1V&g3rO_z^;jWB(q!Xl>M)i+Il{-S z>@df-7P!BpH!b9{5~>VTL}m0BaT3@BGj0i+B#^wdOJ z0>sAKX#F8K8>EgWVEipSqoHUDs0u`9-UI&PL=YX_S;Y5yL5jQ42HD%PO@loH+Cmw` zp30U$1}cmGq?k-j4Nny(rpC^R=dc>ARXKH+l^m0w28iYk5EJV!9yNL9h8;(0mLk~l z6tgxPoFSA^w(+e1MRxPD{vWFwHfQJ|ImREyHJ6_Dm7eyOo>(=ERF#`cPprpAafb|e z@Cu;Sl)*3wcTC+p>lkbb&SYSJ*3mF`%{;Sr(pa=%f*6pdN(9u1q*|!m4w`6-hAj0U z((drZ4P@FxnRW+dMR|h%0+mgzMYBgyo4g27Oa(GlW~zf4&v)dpr=c;x2<9cn$OTI8bPE(s-smn3409c-i2mlWfek`rgy zWG%JzBpQ_zu_g`C?qYj|lQz>a_;IqewPla>t1D14^+q~OImwsHRr%Q2XPa>7^<@(VYbfu!2OH zu6O?4;^YLoAlYy?&bosTx{=}Q2Iqy-8oOp+26Bw*Ix@$5I&VjZ3~Z3GNS!fWIw!3K zwRU`Yl6v-+5rJz>FzasiV57TJ(`0dC7~2R62l$!^b+u=(yEH{5mc$lvR_?=Y%n0g~ z59$XGC4p-ekG|^&Ly567Odkqz&`0OQV?NQ*f~pi%DKd%lC7w!J4bV~p3;H^Zzfl86 z!c4LnA8WnARG7n3gCi{0*aY;_*?0o99z+i^t|KroF)>8+7{t631g5!da6s746Mbxw z5)I+?h3c9imrx1vUj~-&3ZzAW4Yi)cwv&Ddb5pmJhP|c4>ESye%i$@b@SMb=2@IAe z`%e~5ib|xhq6mk0vA-C}dDK{%aom}1-Ke2Nj0v}M>2Z#&;e0N|?icg!K@AihO2?+U z0BC#EAVKUzPJbD+Aymjje{$9_&q*2h? zwEt%2ZvpoR7NAj2qCa!IO@G?;hb>-I0AD(N^6~~i-Gz7vQI*luzA$V1-~$o3n&-fU z@3|B^2QJn>OR;n8KkPzb1K2=D711H-TWq~tFb*4X%;7a{rW`c$M5Ta_zY_B{5j_LI zf!%7^W2)9_HS!i~kCmKQ#!@6E^hAFl=oK+!n~gQXjf#PgB9|7JB7p&_fZ=!snq^NK z9<>Chv~)xk7`>B@BGa~Tx)0=yaM?IGiDvT%AA_}}`T|;)mMv;gFm~!q9pg=iQqpaiQGPKzy4IDHP8R;A0W=Z0K zk>NwFMj!yFQ|3^2ro9i&hXC!J6W7pywTelKv=_WhYr?#MnS-lfgEW=F-VSJS0VoQC zXhPceV2t#rS?j^@iTxw6Kdpb1jU_Owxsn1l?ADM8ZB-g{KvL^iL;nX5v}D#lrFa;2bx+$Hud}%mpzJNdes>6VKKR^{#zwx<`f`ONHV6pa~nee{6%B z^b&s=xLxW_XP(Ui!Dn*Nti66_yc_4bv^#PIjlw#;584be3{aGaWV$4Cr9;k`E@Hz6 z{**U>z*S{=CGZ@zpYEq;Qr4nY*^F*1uQ3ua<}rx4V3fpIf!RS#_HlNTQfr`9Szb0} zHe)tkmJP!_9u)g9Lqr4^mI)&d(Z2Yhl=VOyQ_6ENj$so^r<8Hpj*3V3rs&=r-H{8{ zNzFK>Joya~QK<^qHoQo|!HP~CzAG^K4omtH0mIW z&1q`jjo5P&{5dj2fo=pMEG=mp%(Su|3V3%2P#Qj%dJwBRY~h7@+TSonbm-^-tTR17 z7e~aP0?(o>F{t!)fiO`+7blKtSL-)}Kn4x_8~jPl_RJSVSek)=jeCn;=b62C%6Dyo zMZ0=!*sx+q9lagVui{0T&y~FgsQ{%gT@{d?MQ_PdSxu!%*dV7 zhGLHg3PN*XWyWTGt8|x$YP@%6qmSn>=7(IHVa`Rc@+yg zX)~n^b3@%XxA$w`+^F}>je6gq1nXS#NeBPGIpZ_(%y-^h<*w4iKis^qXC+<8hT^~wHyL5PJmRwSs~mBUT7tm=#^g|Ca^DvUg^7okykzV zzrw@-CJ}WDgry@6br^cIo)Y=I42|S`rQ!vgAzF7CDPFN;U<#)DHJa{M;*r!8#D|(ZZku4ygrIS?M0BlZIjJ3SQ0;WI&hj^&i@B9d5( zi)l3`+Q?aoY9?mfjLt|GIu6J!5On{Df8xBOZCky}L`MRcz%f=ERVu;{#HV#{Z(K5e_#fiybe8`eCk+UI2qcVu4Aj4EQ?^k;#MAaf}bV+bQP8Eq<<>_D3tMRl8h2jySrV+%Zey_(mKeL@Ig zg3eMJZ`{-1!HbG$O-O|Tsm6`Ub`WnxB6VePyaYE=tXYH<3WYfexTl5}tkTQq1gh}S z=1A^Iiw=tycw_>`25*Bw-mc zBfC)sGK!>`s_Hk7mAQ|)RmIffs%};Hj4XWSR@JTUV(K-ws`?@1DQ7;Iq^TaIN%ut*{XSdoK>Wh@*_P{3LZ4oJ zPknpuvmf97Ui;gxF<&*&vYj9_8aM%xz+Jq z6#Li+C$>+NT4co5oHZue8?!k|!A>)fRRL+D;9@PbydrNj*`$s@wVM~cZv@^4ko(hVNkda!#8KbaMAr>ZLM`#W%(U~MH)=VgmE!t}{wXiA$ z;INjXFXkVZQynF?6K&3L)C8NYzM#|d`@6gQdn^Ep)f`I_VsZ(dymw`u&4+bF#~$y9 zS?I<#bQxorOkkj-!s)lT|M{R#%rUTumfC)^&7cGzT4QA4qAZGq zUUSFZtC2JCYilj6pa3M%n{s+n)H%XmZ>8!E-vQOZ;$a$OdO zdTK9q*)*LgloER>*@W6BSxgu^SfWb}GlDHbLyK2t*Z|Q>Dosb$v@(kq+W8ff-%MQI zn7PnuF1q8g;v-Q8$U8pSkx#aQ1$I7JYhU3NzE9arG(muEm7iQK{N62)jSAX zVoO%UOG>695tR8NXIQ!IQly%n=YXP|F+@JqOf-^eqncLqS8P{nVGRx9`yFCw`T#+; zwt(nfs?v$cw@xGFdso-mVxU5N`)5%l$wY~+Iy#iJo;Snse7S=~fg~)ISFGq_Z#GCr zqmZJ6#Tj&@wXI&p+?Bck!FB7r7? zSgr@hW>h)DaEI)#iPE&Y7aOyjmBeE6$1z;Yu0^)Reh^_(*6_Vjo zHFoPM)ObwbNFxw(g~^NLq6^~#?9I|zHR{#3wozGjaI8-xytw->hBvynHJ_MAKj=_{ z7&^by!-Qb*xulnwMKLC6$lS`~1xxzjX=4(Vbv)=Zr&^RySRPKKb$Th;P~wykR6fhp zR`GT0LB@~tSH~9s7qLbqGznAK1Xz_e=wFQQq;D*_3`AIu(;Zqt>KECSb!oG$Ahr>a zjU09wt?Dt1V4Z1aeK?}43PTbO>%wH0mlsy4Xp!wouYo!?ENduKtvYxRW6nI$;!v$b z#*IiZqvaJS(`6j8rI9TOO0Su+`qWXo4UTVjXBVv!vXNqfFVp_sy~f|s5wGW2GPH*wcq zfj85!g+<0Zjd^1|VqkNHlLS_m7)2G0WJA_|IsPmXYA{x|qZoe{W49_dxn#L4`@LSN z&>PZj9oV%#hDID|;Mqjt)MatB0qTw51UryeG$2NYf}&h0P-eux2D^8eCP#0w1N8~) zteVLfaEDNEp;LTbT1v{<#%4ua!QyO&q2HZ4>WtoCi_c1>XRSsvw;N8E%;tmJVBTWX`i+-0aZqU)_Pj00{b|2Vdh zP3Tg{r6r&?3(IU-GEYS;k|PLW8>Mkf{PyN_a7PU0u&@TLHaAHT7^o9AXC%fM6)|xL zkC>=fi)p99ClxIfJt1yn*x5QU%P~QQ0Mvp`9-&oqKeFWx9kaU32(htb!(z z*=bcZRylry9x#j*clc0SRK7Nn5v`2ZuqpZq zQV!OA1!3_>%%Uo?>+Ag=BUN6_+P2oLR0azb^P-16Rra_^nnu?OpyEqaXIddr#&LKc z7TH)UGpmV6NFpj4!6nED&T!N+=p_#u;?$dyWJXWScNiQ;Efe=DM`RS^HDjIK{x>J8 z#M&9%259-BDDeJdgPRAXvNx_wP{`;qT9ic|L3FwmIO2vYDvM-+LFGuh6OwcuZC+tL=h1MI zYaDUaI2;7@MtCj?O!xoP9bD>~m}$Ldte@q91!3W&+(^#qtjf66TCZe@FMF!MO^IJ7 z5^SJ7V(eOBg*3IHLMcq6`50tU^fSfUBz?>XW^SHQHppATk&}#L3gV0i@gX16_H|`h zRNLw_USx`DW%9?&3hFC9jxlRpc~Wz?#md;iCorA*1fsGMA{Lg%7{KV**(JF(ikz7J zh{*JDXvB)GpO3&;-&U+*V`Y{jk&--PHOBghOPMcojiHC1>T-OT?H%Ul&vIzXA?Ls9 zcV~b9K*#SsbG$v|h)JE0cm6DHa$CCj1@#>J{i_=`HRKCPt;W=C;}$0`d!;#4m|EMa z4R%7tRU=zRH&~e3*6LF=n571}ePgZ7H#lh_&O&lho2BKwVEZxy%$dzrQGU~+Si2bpq?!>W zQWM8Ik1b=fKpxK_P;2LUp>^r!4A$BH7A$F0BEzOi_N?MHuTO8GfiIQ>i*|^YA%q`I zeyTytbW#yTQ7UKxfn-DszpB?Lieko`!zyQqiq_}qva7>=PVD7`huluHCr4r^h#52` z0TX4)kZv7<+1s^)IYOpShxg z$;*r<%RgO%v;4CBkn=@C?D^uai5!74r-uBZb}MZ{fZc#VFvf-8y?a-;HTsiN2*FVf(2EQ+PAwis{2$CRSNYPA>p zqPJO!E#YWu^?Zl@)uGXLrBLg3!{J(}q;eD;Sd7=ZI7lQv*gCus4rSzQt}i4xaO>_y zHnYG{{C3+!2hp#?*yoclmI_bW>^P&tcHT^4Sd%vms?)?Q9-lNDPIK|BW-4;7M6_=g z!EW#IUv%mb-4>^mtg*INE0lXoM|7v8WwaZ`7yMe-gLEudJJYd@1_>APl_%yyb-1R%YG66bplx&(kc?9`JmKA$w2G7& zLDuI~L{ca6K9jGKcbSTyi?zHcWlA{jtUQqYmqfls40t}CTD9Un8hxiQj)CKBl{6toK=Zhw59## z{$^RE!7Ror2!~=v(5>p$YSM-jG>j0XG7-UTC!Q5+yinP!d)Q0!6x!?Uy;SQPRRNFI zsx3ruhN7Or{u$G+*&;%PoOK3USzVc1sG=zj-eS$r@R+M>xHjq-jd&{@$D#V@5RUR2 z&|hz2$mV>KDg<3ff?&h*ICr}`hr4KfC1)XTzRlvKvNS$Ad*_eTT~+kT)U1(%5qQLS zT4p7pCScCj@}(~4?pT+x3DQiB1aDIfni(h}{lbwJB5FbnY=#I9pD=+`?cK_^tnaoY zIsvWMh^iq3rWm1rr;WHgeOjidsVFo3rV^1>pUf`QM1~`2e2YMD(V_|slo2)JC?ira zEdc~6)dkuUQz(=9C)k)>Ff6qZD{{FB7C|wqRK}asu96p@jFM#9XipFtQmb#-%V~Y* zmo*m=6k%GuN<=DXDiLRr22~=?CK1%C?7XyBD-o$AtVGn>QD();U{irI;F97@##a?I zhE$IGYM#A)C4$i)Fl(wkdhNOS#YHLp_WW{^($I?TEx)BRFV+}c{VS7!-)h1Tnj*JM zn_{*MP0>o>=W_}dWg$kByd6t-5Nl%-u)WYFJ?n!RBrYIgHA+MDhj$aS%CN0sRmESZ z5w?lDD{HB$qYaZawiDKB3WD*COO0x4WJJ~Y!P7-4!&$O!{#3scD~|ncE~HOu2vVl+ z#O$8YIGafQ<9uB2VGphMrH9t~lCtmIW1|UD4%aOF7-8W?jCnOHb(3DJno<~Q)_S{` zt3uG{OzF7hHiJGvvKR<=Hje)C6HMg9mYDCkIg!LmW>+O4xR)5Jqu4uDH!m4ULXj}G zhR*VABqh=T_2!TxmAErTM-!wN4fIg2Q`rtmJzpc~N;}4M2l1DRc8-Y`Gu2H!_I3$d zcnQj)jlrrqz|2cCRUB(N-KPA2f+Zhs-S#mRgyoNyyVODGgE|Bc^+`pu2=#hNAsrFM{FkOQSa5Ef{pN^(q~*;CttdqVF;t9 z5(NZZsI$|u^%?}LA-KrZNO%SszUu4Y&9?P}51CuiDIPmIRx`-lI*KnAy>}b3Id3dQ zaT=ee#(JPRH|vDodm%-g zStV6btby|Ef+i%(?|q2O=rN3%ZcE{!ICpHPU$^GZjt(6z6cwuVei>2g{W2nL0_4x& z5029xCmOl7_#a{;1(I6^9f@^D@;Gwj6+M_r)b`;81|Px3s*> zieVaO_rbBV-+TfoF`4?1L2#c?{bKU`$Ei7 zSE<{jYTZoFRVjNJaZod%%t@qFu0X2eZYpu6#{UGFmm+7GMOBHykM)si#p{_Ma>fl7 zcKp;Fb!TgN(pwllcQz766QtUn`kt*(T}7tWNT3w9HQ821q!OyC^v(ZecuduVdD2|W z6|+bQE~wz8I*#SntRmOzd}l;Z#aaRlz0i;?6uYX$B`Fnx!PQt1d_l*i`iyd?G+Hdb zlO_zZ0{P4=eG(_LzQL}v)TJpajoU(zDoe%k+%h*2g8MSv)m#%PlpqT|DS`@>7U>w9 zhWK-;Fp?n7b|haHa-8+Ty(FBk&`~w)rTjWJL6ga!H61isl@b~x$;kFd&MVQ$a24h@ zL0ZMVQPOxpF_{;FqKde>r`szTj0K@UEa^k9UW2(BLS#Zo(7LRgq2i$l2{NF_x>K7V zEY*ta4i?eHLnI2h0_BAOAbOH_^U z%&40-l?~KaLj)h)jHe}8F1L+0r@QTZNvbZRg$hFPDYuoODR-5jsl8Z+rWRuvn%azI zXlgZahR4!D0VU_g~nB#X85m zB!PkhwVEvn7aib@uh9W?cd;fMDG)j+3dA_rI6h?mT69BIdC{!93f+<=3ZWwRtRJhR zM^arHC8v@aO6qpGRnx|f6(iQN>1MD-TRs&oZyZ(2;9Udg+masW_EpSPbD!b(TrVH- z+a$p$`H7F}E*13y^O3cF2m|D5VW#lMwWku{)(z|`e~geJGF-&A97S*0;u5_T^vTfn zp-_rG6BaQds@)nmesoaFDMG1UucW(egb!xa9-p7AD{Y9#H9^@3f-q|#NHc4T zxvJ68jrswBR_h0Mw~S1mQeBOsN1IiNNZG9tQEOnCRR^boo#(sD^<1nbuuYFEgR9%D zv>JB(LXU6roh^BuZnhdUp19bRn6SR91Y;v))<_aYL?)e3fbBzw)mQVrb|u+CyTyf>4h zK~tka)1yIWlAr_6Y$MGqhNZd1ur#|EcIFG)7hojz$05DoOIk`iRhkxBo3<oXQT?^xD>rOxm+(6U5#dfZOxSb_P(x5^Ao$dea_YbZNrHK@@?Bz z-;I3BibU>BYOmnF!XKd1!$@iCapsrVbIl~4O4g+~qvc9rWy=1#-9Fgmlo8H*vKN&W z#HV_l<@TsOUzet=XrD^7UlQ`S7r`9}{LNit{GPX8-3HlSxoE$aiUw}!63FiE9_P_j zYC6dngToHW4z`N~hTN$%~$&ugV_b=ba( zN$_VUMf<0*DJ8w5xpb3!rN+!ddapqwBQ540BNkfX^r?IjI-1il*_UXQ64OvOxTVD4 z_MWxcvLNr#Y#1V{)tapd<~QnjA;cG4$Nnv=^+8udnxybQ+Itm2#?;tT1V1^1~oW zD4z*H4+FDnI&?=5% z4mBbQX=`jBLN8WZ9zriwLSv6q+ZIEsZHuARR>aV1E2hqlBl?)O+KL!jt#1q+TVHzq z&(f6RrX-VNkH$YR8Ach26^*P*< z7U$)jGt`@pY(nTufW-xENaP zxENZ)@7T6Yh0tm%VraD$F|^u>7+P&b46U{zhE`hTqY`nV=w$hg78!772@zj3W5^bBEfcz_5#Lgv=>9i_Ir)?V%jRkVrUg( zF?5{GA!9$K$bf}f&0=V^W-+u{hZtI|Lkz_kyUaZxX_1p>#xg+&tri*6R>>!ZR*Q_G z)y|Kh)y|KhH4+|Mv#GH)i=ow;#n2jxLJrmX#24!B=I{k*wDq>=u zV-ZuQ$&f>pKtf|{rNz){X)$zsX=AyCb*o%B+cJ!p<0`wnFopRvMrCn<0Q(sm-8pXA z^?{fV=`{k-u&mb2E*GgcN5_nHEiBH%s$ zDbAiL&YmgGo+-|rDbAiL&K|<6?BX~omqM+zVR9<^4JzbQcOX>JjVTjoE{sP>K11GP znyT4|F~K_RQ2yjI`MLZ;E-DWh%Ii2LJ;TImdx9H=J^?-a+6a@L(BJeKzjPVD<0zsv zvqokzqs;%y(zj#-D$)))0x*rvF3S6@{n^xG&H`$n6n3E zXm26Te$n0hjq2tX&CM@rieKgk`DKF(zf9-yEAP~bybmKdOtEAmD%D)Q>Qx^_hWtKr zz05i^B&r!6!Flf9L&^-jE?-mR74tR~b>R+x!$C?v^5ys`+#`L_W&?hd=k6@A(;}P( z^ZhLqaY#v~0HU8m*9eZb#5YHWT3L#I4o%uF&DIT$ky4)pe8mPEb48tB$WI>gXw9b#y;4l%S^hsod_uM$BFtr9^Dt=1uiR_hQ$t96K>|&TW#&+g|WVb5L)Zq5LzoOgw}dDgx2a1 zLdVyk&LCd1TAzm;YJ3|)$58^q%GxZEC$1wngpO@8bW`E1kald7>zozR)|wpVq-snR zLThyhp%=$+eRsCOS+L`V4jxksFc~G(hn1df9StFLY!&Kg2x+-ws+e)cM$&*9Td8K% zRq*FSY%bs%7g{Siq^E1;3gzFo!L_nltbLpWG(q&b42OK)FryD-mdJ6CZ$Z$Bb5@dchub(>j&5Z)t_^Uq5~E5_ zou}4zPXYmhz5e>v+gY<|9hd+3;y?%0(?W9=P3(io_0| zs&u$F_{?+doBtdhp4#!N^5Zrv%_1gv)s*(=+eT&Cj#*r zcQ}|*$3@$rGHLzfQVXQ4tCk{Bq#lwAF9g&Z&WtQs@iusx-r3*UqUw+;7bjgGY)+Pc z7JRFW8k}glOg-$5gQB>Wd*RGEWZso}6}beAGo*AvS>V=e?)>&7gdo2bU|?x5f% zR+Kt*`T9(uGR?tpv@+kjEsDzW=a)FnJv*?D%(ctbx-6-0kN_Mp9&p8qP%arCW?R=b zcm8x(%IFw&q6^lKx3X>4*51VTNB`_{QC)v~H^gY|TDCX1k?$Te<&kZ2&mz>tSTe8|-1&NRoExQX4i1j4alYf>M!tQtmF*w)cRVBdeQ+?nIlP{&%7fRQ z(e6PG4&z{Y&acnsd&_iA+pcW!g~v-eyR%H&>JhxunV;oUemmB4{npW7D%0<@{ho;x z9I}78k3X;cmR(`oM}j{r=Y;X)*1TshI1nPNx#ArTX;h_SyQpuO0fqa)*GX7X`7sqQ z5!5?gZ|!hZ7|Y;5GUrKxs=+453B`IEjt&RA{ex@!TzI}Y5RX*KF6y6=(NV4*;5f}( zZ9gPC>Ml7z*5y||4zwl>_Bg|`=r0v-!ADwz7wh5#P<|c{PvvCcm?U(+@$=_b<{u6> z9#tzK&awu}tFxlfYx{>Hoc!=$P-$O@l3M-TA6g6Kkj7&z21Y}cC4?R&^8-#^92^-X zT)P3K3qKdL^~Me~zSln*pn8sUvl+P>>b9^;3P5YQ6RO!ig5r0W#E6N*-`3>`4y_jx zX_m9ZQIWnZOsn+wH}-dmx`sx%L;fv0Oe1aOd-Rr*dV#Pr<3BKQ zQWjX{@wAq!Pj+XLnl+bu^$bm2msxSkfDTqK18Dz9SUAuAjcd5|J32RUw|~>R&!vM4 zu#!1By0*W$IZQG|%X2)E3o);J5*c!5AD~_1#|3P$gYipm=kO4BfWk8l%pE*vwJ}XcrZd?Lt>@B2|;Sg;l?mOI2x)bxP5gG38IiQ z)67612u-X@q7b@Ue8X9|Xr-9LKB{1AXa5FW3)AMuOq5}{QiLjSaJ;jV?`6ZAR$B3m zGh~r~ximzWA@RnrPst|4wl{B1E1&-6b(=o-`tM=Z9v@Oq1Casfn`*u}MstxNH!)I! z8~ejeNyVg@Rt4I5w0pp>Fz2OO1st8Rg|Pxo&BjZpJForWHM-XKLbaB=PqOd1Wtol7 z!TKR)z?5n}yjj#;GQ&&Q-rL$Qf$`Uge~pJx+95`M$(>N7!aRYlqhD;Oa%HXwj%BZ_(nSAnKM)!sr%_p#Nu zX>-x0a2h40;V;bG7U*%Ln{W>C2ee z=MK2G$t25Jv`7PYQ)XfTIs=DT>5ct_VI!ez?1u`m!D(NssMLc;!~Gp_@XRp>Qga^R z_5G(=U?Q6$MrOGg5zlbMG-n8-N;loazyRH00OS&h4W#)>tBWZwkyQ%|%Fq;9IP4IN zSWZC=+23AjunA*=;WeAg^C}z~syv-k4xu&+@LX(0zM`be9ubU!P_n<5JI zU^+qg=*%?i%th|zTjq@RD~-oz*vp)Y3qm8k<9*)M2Mi_V;@2~6u*#*ks|o5&uhG@V z3{R1m^g0)$%81eCuO!{};eJjV_BXf_*?b1!Om+@SpE~d992+!2tPpx*yF;tgTr!Tf zYZVQl5PFntL;)Y(6>ec#g^sBbsv@Bfsaf_CVJLgyj?K@%!RL*7R2_;WuzuyZ^e}!e z==pfhD4JnIu&H8OWxawCrg%|2C?p*(pJ;j;DR2X)PKHf;R=pwuIo>(q>w*l7Eec)h zr1A_KwYImmk^UvoIk}Z^G~u7os4aB%we73dB0;ANuz^@X-%EHV%%+^~r1`nKe+19%-%+m^-G6$m|@?L6dLw4ET_2a`^ zwX*G)us6nrZnDza`8ZIJ7 zYbU$Q@B-UWf~<0^xnJJUUb!r1qTkmUCGg;S+2X?fu6Cncd8EFEboO+97yV+xZG~-a zAI4yTCKjVe>u=slItc-fCt$s^Jv=-rI$lU)4{m;=|MY+p@*!K}qcDOjiUb4J+aLxm zvum+cTIFL$joI~XEgO@v1cS@OWZ`m~gqWQ{ShaaN@w+4?D_&|g2{S>8NW5MQdL-bD z7}@jO<}z|s#_a3JX(mq@>kYRLj<}9To-$E#i6X{A3Cp?qh8dNJm)tvCda=2IwzWNM z(V4ow*uUA8P)e%D_44>6ViiOz!|SxNf}H&D_`p=D5t7@$<-n^YCjL_}%o0f~;*qg| zM84T)ETOThVLgOPlN3aZL3gk-fGjrFtBI_4Hgq+D7ByKWrXgFaD+^He*u-N3qgfzd zpD|jQ3I4szmp{=5R|mN&Tg}1M7I-{5d`mUP#cQm3ymtXt!#*BL?^3;DuIjO(_1@t} zHpW*grFGH-3L_xj9qevk#~o(Ah1P=GowaxtmfzW%DTJ%TIN%EAw;RLRhtH+Ekvw<% zd)r$Q@1oN{Y*w>B1tKuR?$OPyWBtd=A^Qs|5TKH^p!ufc?#3pyzU)_=Vz}S*iVZBG z?C8K@H&%!Jy+g3klQ%JKdV5KC=~jZcpVY7784eD1ZmG4QvD`=MhhE=k503g9*H%%M ztQWM8*SdBmuW1k?IPEH5+b(>^KnnaWkT>^HncN0}PRMPFui<%TWv z%>3d^T8!G@myA_P;-V=|$xWJIX2lkxgKG>Vk#{4z^*L;ZOAhUls-x&i8wr9crQy&HMP$6E^K2M(uK7?#_9G?X!<->HVmk zS|FD`&Zu@*m;!UU%b4)tparFi{F<%b=R|nPIQN6Kbpnbpl#3AiThl(47IF@SN0d4R8p>Ej9gN}4{TtTPsSK=P zGhPP9>H|C7UViQE=?(3?(7af@TF0)Whmeq`X)J~&7XZ!ZXIT^D<%bL>x%{TpTA5}+ zPiGPD^SO!a3+QSt<5LUG-nYG;-mEZ6cY;IVO_&G-S+J}{|1tJK;~CSVJM z-Ntf->!X*_kIZ41)KxZU^kdM#!wo7*OOVetytA3*qC_;H+}SLO$5lq#m~ETM(4aD% zG=SC^`sQ}oq%`v)ld{_2v}i5YlVUB~W#q+G_J=!tTmdx25E<{p>K$qcK7nnOw~-&je3Q(J zWcU*0fGv6^jYFXo74Vt=b{ViT)5YbH!?9f6?DxI@#3V(qxhNw-Q;H%n zSBySB!+lJR-jljTp~X58;~0M1ww@%-$d)&>7FVX|%z3@-m!%o}eTM6`=IM`Be#rAm zw?q<(oq?NSz}jo(7Y+8RjBgqP42Eq!&nL>8lJHUImC5aP)wA9=MO!1K7;9L^Mu}V_4dZtk(`;weWJYLY%h~Yv$U&&vJ zk7{R@oa;!-b|n%08>2-CMw1-8@H*2Hq|t4p1l8YL z=is?!86NA&_TLcBn|#Ci{{E3k|KX#Wz*0+KseI$i8Air&MxQ8g~rn3HYSCWTvawYP5WEd*flyj zw7by}pEWui_!TUM!>ig&F1~G11lZ)DT~5xNpPfbfvc$~s>ZYWk{$C~H;9r&|tWHmb z_t{Wq9n83}YPAhlJ;VIVt#)Q(a5&txH?3aZ;mo+!wSn#sZ7rbpjna+}8c5Eb-{|0I za48^f0^_sXG!0+&ZuAc_U5z+(3382S-H_+lq#E;vU9LcFw!7Fh{LV1x#;mDT!>|x; z*0y6WTikN7(ww6$dM{YM)0eW1{=pI4j2l6|dh0h_D(&9v>dI`R6aT<6$MX@!OyIR4 zLmc-Q%WQj3E-rGJJBvZPR~8XG7{F$Sp&c*}SwI)^Xm+^#lOr-4{%ZQG<*&BCX8aXW zazCI|1I6c%47Vbj_J*D!#09_zFd+iPa|fm)+~az`OB*b@p~k!hO9jJbu$IhCtDOxlXOvb@Gh$<F@rpU(T80on38n6N&bt z)1lLxp50t+JKj2@t!NajFwCxG`|F!qE;F*FP7^0V*9qTVO@~_kYWr)(UmbtV`fDy= zKk6`-sayk#d=;PJ3cPw1S~?0XW{QgA7FhVMpM_-xf$f65S&ewG6Y{IrihLcXJLz-0 zdYeq3+5GMp8Y^*h{w&yM#HDY8u_mujTAo&Wi2gEjXf9CX(>ax7_g$R*(viJqXA0`FKz6LaO@ z2J3vmgoOO0i+UH#_It*D&)V-f`#o>J7wq?<{azBSE?H~fon{Ad;_n5uZV9zZJC~cL zpKik#?)l_aQJkHHfN~F-aSNMX{B4SGxyx1~hpC^qX^I-!n>yN?TH2d>+MAl%n*#@A z1)zHbPKRt=zXFGBr$e^WA=~MY?R3a?I%GQ?vPFsYk6C%LSCON}?d70HG+}h;>u8?d z4zu@=zg6Z;sLUBwF9-LO%>)$UMcCvr4Cg+)%WO3d8}>(}8aE*XsWz)S%K2t{vjq+H zus>Ui^hm>B&B%}D;t@0S7NxFc=2sWyG4%Wo%(~U(1$3Y^jnqmp1BJd(*+xtVu3n>w zPS)B{&UJZH#ue(O@BIxm)P-*|_jU8PSM4~E65Vcc1xs?ZtJ}kja+zD*$)2M1hUWp@$A7SlVj`g_rwvAIvTk3tyslN%WbcG;*hBZ|McStD8?h2XlTFk57jqpJRJ*uNDLVxzb%5aqjnkHxawL_v4_6>Xp3 zi)sYxjq3Qvk{+5}!W%|UTQ}f!FpIg_k;UA^V)hvGM_@DeT1GO4`eR##G8XewVzAaK zl1slR@fJ#PM7~A|h7?+DxlFy%6@B0^WsR6QN>R*p;^TfL+qA)Wu!(EaI*|K3G~Dko ztN3(R3#OU3B0eqqt(YAyL`VfCGWKvg%5KcNiVHQUEsT&D*3mZCM}uH}6a6t1#FI zf8ghW4;%Iy$6zL&8H<^Y;2lbF-2fbNcijLSaz{6KrZ)OeF$hwP9I;vLwdSpH@xQW) z`1kanC;SnH7c06mNn6Q5)GEFt&ENKSSG24#?!)sBU~3~%%&icB=nmFR(P6emEOc13 zG{V@>+-muuhJG^m`u4jH>KO)t1-(GIUf@D6P@xz2)(dp&1wQlw*?L{9s74JlTZ>$@ z=O!XbiZPVZNh9m!`3u*AJb!6pL7u(u;|W4 z!u-MfhYcwcS$~cuRgF5=JsUV;52ZuPxX46S>9%76n%Cdnd4Znks2xF#R3s(R?sFxNp znjb_o69xK-1wlp#MS2FZTWvFm5Q>v}K)qTax;-Md5s}@i!Uv*HH)h8fJ0y_(Wu)Bh z&FeV$iX6Q?PPN03Pgjj8SDVH5Pusd^OklNbVoO)7@1PwJ9eZ2rSZL9>p-~KeO|ttN zqhUeW>$gdq5K1eR*}*<5(rq9iHxhFM{7TojejI5*)GT>I6dX>aU41gJ`JJ70)R0WJr4H8+*{^&SZi@I@CU$Rm)wCWoG+r^p8;A1pwiBoEU>Jq# zs2WvsDTJbN)Tf|pw4=hV$E2AJJ0mz|;Y2~Iw7`bz?4 z>nXH{a{uTYloH4AQrnoeG-oOpKG-f&c;*m^7>_FgWVmRatO;8jGA$kTwO=^0*z0CY z0dDO;5=qT8(28bl+W$c)EMqHnnBQjiOw2CYe3I_1C>g>ZQSt|Sa0R+FW@8ye;ezm_ zh==fpxU;#?8K)l_z9co^V0!*?wd(SR6cR0DhivhDjoLL5b`Z`8f2fW~M`~~CBR0$3 zKIJf_uqukB8yY;wTVm~YqL%s2r4>?)_(FnV;&yAWKAUb^*h^e$ULAY29h&i1$6q@0 zh9q<2MG`Iyqv#gOu8hAv-`LV`&HgkVegpre* zf+_|)BTe?luKS({9ri z&Q%(PV4h?pjrJIZ4ow{zG+jdj`5^tx(7Zc^ z>k;Or&{aD%uQWgPoF#Qi%H!{hyV>}nhbBcv2yt{Pw~6^U?2;oA5$P$R+VF>L3Ga1(FKATfov0NBL2US`4XmqaHEgy@ zBQ+=KLUp>62o)vjuCfHjE8r$yW3mtCqF0rI`3iG>=%t}`E6##NMPiP!aaLVW;NsoT z&#Z}Aor!#C6FUV1t#%e>1GSnfRPz$vYli0FgL97rbYWv=e`{96tEg9#S!Blwi?95T zYX{j(b9DjdFx5x2VaDmD#+WR$SBS%$Q=t3;yk`A17rtLJvsjL+;2H4U8WQ*|91#47 z(sXb{L~M|JwuEzp6|uEPxN|h<>}b%%qAxXxA$1zOPL%7UB>%d6$GUu5`iHhqKfMAp z(-xRhuq5Lc_U$ajUzqRYN$+)NJyR z-kF+YK!tvQko4oUb>LCxbycY<`|6^ZAjNpFo!&r5B!Qe3BR zG%f=rGJ0p0rov~w<rgnPa`FM7&dC8#E%9@U@m+g zxVmu5FMzz_P!L3oIl&~1bj>X+EJ5UNV>B=Y&5RNF4GunOV>4^6PR@0IYyBadi=5p( z054&pv)g-8C72(VYHj%0GRbUOlqWWPl;I}(Vu6bAtCM_@EcUBqdu&@(z?%JDHrv6b zB(a5;w-%$HEcC0hPL<@7gK*hCa(wlgv9Z%>GJQmadn_<=dZE_)>(c!33z&+rjt$iO ztuYT{aS@HCvx8iW2GtnOD<=af!Uk{hpQ!PU^K!z_#%ShT!h>KwCV%0F5ENWK!LJnD zO2O|FoJzs#b1B34V?-iRCSSFTHk=S_Ok}I({;|#?I%1c*O(NNxH0IB0*JfwUI^?J= z*2#^rE8VK(qFzoB!u8;*=5=C>b!i!^ro z6yIk#QxRO1K2Xv`6rV~Q&x^k``BT_S&ey(1hd3s_p>7DfCRvP78ZIJT(kY~g!b8CZ z^&f|A6cq@--)=MA)}g6+3&%RbQ^N>HV^}kxp_8rfuv(=~m$44lI4CwX9$7oc5(}#? zMX1hKI7%0qQnKMFg&@6QDW-L&s#OcsGWDm?U=Zjm1NXy$WiiT<^!Gx=+$o#YcKv9t zCRQgJvE?te*9c-!zFu0NVA|4Nb15gWK1@PJBe7y0-p+pr#}F7bWA4%QO-=4$cea@? zaIpqcN~$5yB|KQ6XoKruqCz%Mr4ty6qqq`5Yt_bU>mx z17k+$VA+-$V)=U^$b$Mj5;g60rKXs&2$|sPgW62(_H;B{rAjD={nBkYrE61D^QY-?5pz#ekhcdiig6g*NQwVOh+m;VgPLTj9 z9wk?3W~S48k_d|@5G;cvV}nB5l|B&-q=;kOpc!pbTg-<$WNK@q_pMc9?4>>0 zzj-k`-rHsmH5-KE$uZp_t0CF`X&#SaGcV?nFCO(REjV>pA9s~$IqhKd(T&X2(j#95=>&W$4^ISIKV14oV`};I=>(7y?T=I;q9cOO+xP=b0x>(rel@0l5KsmQ|Sn z7wSi8=rjd~{pPkKzJd(cGIR`e@-j`uvGAc34|? z_%?K1RlL0!wrUprSR88<55Vv(y0j>%ukQmaF&Y|MoRN?wH7cm_OvsbQZCqpRlkGQ8 zz9~9cb7y5QuPucxWGI*f>%8UY$;dgZ!;HznO|JaJUt%g*3ZhkdtYKL%6J{2r3tf=q%1?4<#jbdhF&gKMCLHj9H+>z) zu+kpB^UIF8vh3qsxCIjYx-?(I(NlR%6*ozFoJm9WjE95vUq9N~xf+U#VYEv4NU^#$ zZdlyu+2Z*GZOrDoq%Jg)?0q*|LQ~1rjwT*H6E0OLn#$Te|Clu@zHTk+Fi=R4pDhB%d@mV%T=_}lC>MY+|Bz&DDGN4)k{6r8W*4XaKpw?3H|hnbvKSQ?S`=PQ-|J_ z(RX1M5TqB7MJhQBTk|@A16u-O+C%+@p?kT+YL2`d_x+*3mnveU8%BfYH+cGeF!Z?SFca0vak z9&hl?5F=%uE%2#CN~#YPcGZW@bl_a)xpF|s{;@2PY7-gX`YA9z=7+jE2%+$v%5L;&fvbc_-joVyV9O;GBtoFpHt|`(Ww9)=PNb4} zaWAVzI0cQhu#c18NTsBcU1#CSj8)YUp|dj#G|p)S4r-@)G~-SO5nJ58fJdz$O~*bB zD{9dW8z6#QGU~oEBUwYS-u_Z7ZU2c(j)8|0t5e-NqZBsIC(bO&;a)*7li8QKB~s zl+ZCj8zkMctkbOM2)SV-SoxEcK}mv^9e^WVMsc=Gqav!!Z{?~f(?X=&4i)ke!L?;b zdWcfmpvkHzZVTWSkBSRO5=oO6g|hz0bTi>)dsE}v1&ix0sZJ~a3G1|~&2le|%Uy0B zWS=-Ya3nK(^S%p~{cntcIdCECu+waAfgJFY<=QU??!$7>R%ddtwSeP*<+dF&9lAJ+ zds%O(V|jHK^=dudWuH0s^kGs+Vz7{sMmJ~MizUfTSXe z?1?D$Upcd&dY1tnAelipv(YXTG%vXF#ArF12Paurgz@@eH-#Pm~1b zz?A1&FvCdQlvF3S82uVmsd?;j!~e|$Vi)Tr`6g^ScBE(>GmJgoVIa&PE9-T7eD?%n zX>L+mUIFE0H5=NPWZ8)(m9=V0ts|=xdsm@*PA|ce18q|K73D0B6U+n!MI(e3RgT6A zWeKkIdp}pAj`8rd^qHv<5wtZe)c3~WWY<;u z4GXOqygneu8pLbbA<+us8nQ!td9jBxJ~q18o2#DlD-@JHGiLInI~nmQW#A%VPFh69I+J+@ zLF}$@As9J@bi{)zE%CE7gs_$eO13I>@aou~=!!)$vrLUSrDRCfZs|Cvmay$TQ=alt zk%&e&MZZb-=%h%WfQk*1Uy}?`u!+dtag;#|l%&gf{a(8fjC(9KpC>MoR8$c1tu zD~d~yI)M|do0_b4 zIXB60kEsO~;n=>xzHdMFnE+PnMj!rQr+-2+kT<8%9jrJ@Hmo@gSWl5`efd+ zm0C8hwK6k1-;)QESxT+yVHjXu{oB@$8-rCpwMlck)p_ZIB+`SZy5~t zT{dv2X`DETo3K<4Ymql}mIE%NVoBYdyKCBd+t<*PH_m8IJD{_%xv}cobxQ%@Hf`kZ zL!Y^_wFmTt^Kx0fyM7$A;#`s#TSt%Tosl>xa&kIX`FBigUHCaT(mxNQXpoM*z%RCf z`9aEd2mGbuC6n>%LB`*?DMma-I&^i!^tO(m!!r}I?iJ%gB`mn!2!h+af~#R{Il7c7 zE>()kL7D(TVPxb-D=@QK>A{o!tkIu>r)Nj-y>kL?ar!B#sv2^(`R++<<+8e5zp zJnpVdam@a9aI8xU5Msk@OGhP#6#zQlDXeb8UCRzxW@@`ki=b0=_toKN zGOoINGQ!4Iu)xP9;X_I4s(mtN{L7M{)og!vlbZ*^mc)2l?VYo=j&Ll8(I28OsNmbG zqBHiDuqDp1!xvq=QFgL?EgZ~s$7W4iH!DeVt)r98I?J>r@2>T9bdthb-k0iHZuYQ+ zRE3eGft6Rju%Mt4r-0pE^qVY3g!%C%h~eyg%dnl2=>bjXZ!$r8$68LAadO8b)~8BQ z@1Cj2vV(41+uqP^9SM@|T=2B@y0fbKFsuxdKz4-Ds9-t6QzFJ^k?P(%R|9aQF1g?)qSp!w65W?(gr|0i36&CLcNT zhUv-asYj+JUu)1KQ>O(_UYtIA`r&Xv!E3X|g)GbZgZ}zEIzWxVV&8F zU-6Q~m!7!q-Y+@%%84(V_=*z`Onl|UUzm7s;xC?j&BP-UBz+nGU*MU@?s@B}m%ZFz zg0k$MEIZ5V0R#9O_#%HdPTl{ulW#xq9rt|iM3HufxYrY>y!5;$eEX1t*@uB2;cveE z_LFZr@piuL-S^xtf9QWWl{LSJ@c5mQlk~RmzbEo!8h;|o9!}tgYj79%z9jz5z-c|- z0sKnh^fuG>rICbya)V|pEPZ8d=@Rxb*`8&3)O@$r?k z=ZoL*qVGES-6#Hf1xGKc*5xMfgX9z2{%+v=fn%9J27JoOy!YG5r~MqrifR82aVZ}D z9bQ-4`1Jv9oI3foiNz18JFU<4eu}uWyc?$;aGJV&->H{1zNm&ydztgg4P0s^l@S2iZm1$iLzBtRigmf{_w*jjj);Et=`{pN!`%#N~;M-qZ z=9--*OwR(1+T@+c!j0#C<(Dm!nE%g{=80;W;`@7Fk!2sYxYGsh{&K)wfp_9n-$;9> z`CHFN_;!`I%BH1Ppo?bc!lG>t^I@%iMSuQR#69BQfA7TVsgti)raT`YeD0+9Y;>APJV^Up!og0z<&hq-{$+rPW;9R%OJMzQ-6{2C^ynoq!HDHY7{gh zSo|Eni7xVu%(k@xrsxJKv!k@D6qOE3E5R@&P2Hyze1mABi@I6=j zb^s!yGZFI-{1eb zEc;6S?gaW1-KOaTKSsLeNQVfx<8vZI`1x~MuM?(?EFi!b9(n?yoG{L?5H*GLD0+Vm z^g3ajg1&o^i<%P|49WAJ0>0Pan}0pVQ&FCqKNMkEOTd3C!U%JJ?86hWx8LU#KanB8 zdCnFv!dOoMBS`i9XiQ(l$cYSLmOLj+;*|j>vM((G{yI@mmj|E7zN{Ai+VqJ?}~4m0sf#e*nZ);N@!wj5m7m5={!C==BmM_~C23-QKa#{Ny~bAlOk}@6 z`X2|DUn2cC z)Y88>iT__~@sb5;dgZ6FXUy+QAnZPH)E|o1*fYkzj`$w{UL_#n>-Um)rPo;0p9zy4 zp8!tt(^xdduae)Zfj>h)%7a^M)R`aY1vE4{|a{!C<_R{6jhH^=fH3T9X2e~p)8`Y%QHoCCf_ zKurIhBwqPz4DHWEc9HZy4EzxSV)|>rjEnheEFIJT71BQg%<$3DD?g2`{h2UX|90Sq z2#ERpSQ4-F8gKhEk$pe;{S@$z5}@>o*Ld5XiR@>IUj*JHAm;ZYNxaf)?CsA)_D@Lv z3&2rdDqiF77%$oUQs5605c7K=iC6ju6IlK8s|l=ljmiC)$o>ua{WIW{Urq}-_IP_V zK9BH=5LB-PPTTX2BwqPz%pTLfn)KfT{0IRNKN`Eo__M_SBVdi?V|%U@X0n(6Yyum9 z6lSx>Yiu9$TOhv|0h3)(p2qqyzEAv1fi?Dz<-IM5SN-3e!20uNq%7_6@;;KlivLJq zmV5js6Ik&dEX;I||4afa{sS^5>E-i?=|4sKW8j}8Af~?`A47~+dig*6naJ*ij{YX_O#)(l?mZo%Gw(0?JUrw? z_T{91HSl8u#QdK~;+4OAA-s4_WUnXvHvy;k`LQHk>E#Wf5pEyiC-jMaEyNvnDNMIl^fFw2ITSY8K0as5cp}*3w|X5N`D>rmw?|B zV3jAB7mt76eQ^nY3+WA>D9h`O*N;(-_VI@agCN&NQ`FZi(#|HHr^1D4+*rWXvz z>?cSsIJW<913w7-LE_{0f-QOY{$mOJ->W>}dy@1<@AiS0_dD+>znASU zIHvz!fIkjAk$f-MJ`d&nUIPC%=>@lw^bdbmnf~{Q7tE`u|6~&X?}!i_+pGRLo5a6D zwlVOtR7mZA82J6)otfu~3>_%UK5{w@Z8p3-ZqAULhxV@Z66c)@A> zToV76i5HyKe<6wACSLIAr2L&Een`CF^!tM({;v`*IE{a}px+bOcM~rdla2PBu(1a= z>1ohqu<-e{N%|ipz2KN$@e4`(2Z$H^aQOaLfRBJtOGSSC8J>ykw}>}?C>c)R)lh!X zUy7xZY3yUL#lO_zqrWxFUXuMG@q%S?OaSZq`+t-_?YTeuH1UGH{r6k^JCpcRjEw}R z@sB0(4-qdojc+IM7l;>}#?K}3-$=aRG=3q8|0d!Er|}<5;tz-yoW_4BiT`%u1*h@9 zn#BJg@q*L%4=3?IMZDlN{{Htx{JlK;0P%u7{^f?hEQx=Pc)^wUB>#V*_*(wYCh?yn zUT|9eQ%U>@#*%{5_{}8#D~K1I#$QX~Uq`&)G=3+E|1XIboW@80y1Z09;styBsjLtD zNu(*GRr zv%ng1s62iD?&SM_K)hg=FCPEiB>q>47o5ibSQ7tR#0z$P=imQQ692ywFZhE=`8PEf zvWFTm))t)R|7;R}ig>}3q>uIg`6OOrd%-RrLitJj2UR|Bn*Rrr_({GOd^*Yh<4OEQ z;sv|B^87!U#Lp8iIPIS}KO--z@cq>5`LSmrdy@2mogOB#tH7JUvHoub{$}7d>0^8U z{%QZ(LugL|{|(Z|C(eIp&dZ;P?8nE%YpyHC|J<1P-$~+QO1+i8-rsUfzj}NieHV6Y z+{MRTdJrXiq4^6f<0HmK{5|#l7~=T53x96-h^Zq!SAH>uI6m*f zcg9DIjre=_2V#ih?=E~7AC7_X^boNV>E{_uM%m-(@4}y7eAMy%`md_ye;2+pKI-^8 zeoZy~UHEguM;)IZVnWCt=l?(Na2-Ey)}k|e96xvAJL98{zrVCvO@9~u-0)Gy=XbrU z`u(4GxQ?Gset#7|cj3GEa2j#>eU~1p^ib!YbAM8ezYE{RN6J6{U+JMvZ(sT<&35T= z{=5r+ZuoHAmGd!;udIH57ru)RrxE9`&y^nP^!0ULUB%~J_%1$D`ug)u4|RT-pQ_Tw zUHC3OQhvEh5C8wBhq^rY-fyh7_b&W}#Yeq=-oIR}&t3RGZG6=G@9LA)`rd{AZ1GX= zkBPTd%fAcX#fQ^~k4OJgr-wQ{Kl^}IYwPj)--W-h`0&0c{a?qguGZ%+d>0>1BhIgP z>ESLt{8`dNT|Vu9Ulsp%;k)=q>G3W-+?gKg{Pg!eT1|f!zKf5PpYGDbU3$0^J*4vF zAF=X)W0U=)O8=PzzE1iH@SCR3YWRLx0>6v&uc)QJ zKZ#fV4<_*6CjD2{(w|P^mHzb!{2b}0YUwAFc%}dP1pa-}H)`o0OX8J&A%Q1Oah_c* zeK(0$`Zp)=Ye^r^Gq|7g40Kl5Z-o8l_k*M_|`9Xv4J?-%G zFZ^^R{`nVvQE)-e&%f|t;I#bz6FBat7ybWR;P(W1b3eQKf44Ym%<*xOgAUT~AM~@< z3j97Mxaf~B&fetls-EF<-{Av?U!46wE&gYL)BOLT$3NxiPiDVX`~Fk4?@#K8*!LOcsB=z5+l0!Ue$}bdFK_rpFiUxdt59U#LI+DsWoA_j!6%&*wUt65L=k@to;CSBl{haSG2mEY7PtU*bS8C~R2>zL}|Go|QgP{PG z|A&U(GX7n}M|(v0`)_Lb{j}hsyq9OcT#28^eiJz5_dftW3g`KVUp`ey&k5vymSCWF z=&?9k(A)cP4ZZ*z_g@KLU5^j){bkuI@-_43SpW4szM$842rl^jRQBHqewP0{!pDzP z(xaaoF5;i7z!Ta3R)L>?;ok}_@bkslDHLklFQNMWw>s#@P6P4sUPpY{pU=P027c=O zRvd>?y&}6Jh3v<1Qok2xyAD64K+*HJIV{lX|Gk0}dHF-Y7mNCw%HCf~|0}@19_%I2 z|F2nmDKGyIPha%U%Q$Ex{}cz=>Ofd_@A!8C$fJG{1_QN z3(d;Dc+TUki2FI1^>+kcG|=$z`@khW@5`PCF6o)W=#bZOzp3#1<-nype@XVANuDSC z@pTpXej;0T__RtCe{59ZpMT-6)!^^1!M_L`*Wal8U#`V}%;7-K&%f|*fKz^YDT+A7 z|9@VbWvTkymz@XxU{U{xtnKkn#rj@$xZsDq%J(a=5UE zUT*wt$*q204IKA>2!EF<@h7s!f#d#p#rJ_z{Qk8{`sZKxu^Rjfz;S<@zW<2F7yR}| z4j1+Nj}903f5ofmtuSA%@4pH-&Q}P&0L&BUIbXydAL$Gg7Icd!GldM zuH)v*ot>;b*y7tsib*e`Jzt z?e3g{3$t%=b?9zue>mXo){Upv4!ELvkgXqb&moug9qw-(*@eNIcG2|CK9@uu-pCWk zOX!7kb{}-Mv^ZbX+T&LSSM7?@uHO$B?z9^l7ccf5=G*%R``i$Iz`f(#Sh%;feUecOyrwh~^ zAFgk48|&oOHh14%3$zsirz(N{&FlR=?p)mFR>7O2R-TbBntNxA#0r1g;La zp&5FBa<})c?>{}rHy|0q>Cte1C!;IQvm_3t*f`A;PJ8Q(a|)jy?6By$n}s* zTlWv(!S$>AWy#yq8!m||Nyc1cT8XdUZCQ!5?lWnn4zEPnJ)~o9ey$`My^}PJeuQTB zX@!vlSKvY!$i18WjiVSN9ME2oQb-hIOzzrE_Xj3+q0<=U{Cqs@>pt*6UPrB`k$pThK^AE;oxBBmhK1^Wgj2LYB;x{2?oRAG4j63g;4$R?w|-% zLy!80Pv?W1M~@tEaVcnt1h6?cLIUR->sditP?atnB{jTKgdXai-2_r?;73GF8S31& zwPE<6W=3koH-lmSaFDM{T9===b`w%E`);^-%PF+@4E=!YA-DbEVfkIPAGjL6AJAWZ zXOcJel%;Uo4~~wLmK2<{5jd&LV5^d)*VL*Xd!c{4;aAI+^;+-mJ)Ixk=qDwRu{AxB zJCW>6(xtfXZ)^;Za5oT``!{mQuA(|YybY;+Zmn70-#@CW!7T3|97Lg+{0*TW?;T~i z-BhenA;gVMeg=mdP@_Pk!N$?eEH}2abhIsin}h4&uV>BoVoaF<#5;DwRkK{OUIZO%9o|5?`+ddSLJVW=4G#N>Uje zQW@<(*tVu*rf4ny;;&Tm9USjKayPa&kFGt!rR!X$YiZ#n^z-f^d~j%HM1F*RJ4~7u z{v2LYwp4Tsxf#vw<`Rq>TUWE)Jjz(=iUGt&yZ!Awu{!jAHNQ51CdjC`{To2m%5Z-- z7ttIJkV1ovv7y3Vk@f&tHrSXP4HCj@sisGR&Wr@@jOMj7n%B-~UOQ=Co5y`{oz`@J z>oCn3aH`hA5R`s&us+(p7?xHlhNZQNVQIA>qO8@svf7$^)#-KT^Y+Z;d2XSfvbwA+FXl5w z6KR%{vE<$U%`!i$lH+|t)`u!Y&QHvDX<%!4sohw4GVd)cujccMjoFzjEsbm9xz>DP zW@&bHE^9Yd8+m7;(VL4QISML-EcIG>Z?&)iF7JsZ?EmzP%?&4roJFD^E+H;Nd%7m~iQtUPons9u$H=KR+5bpHY+ zRp}%p1nbtBrFNQg?8z#v3)lHIw7FCE;Z^erY!9EIsOhP}=DBm{``)NtTR80jY#wdw z7N)t8bQRlP(!6zqkxw0U1y!jo*aHdgg?emJqg)KUu)T|64N<~wUPTeym^RoKRg6^0 zRSng*waP#ZJrT0Xh=lLtA^cU5Ji^}v2h=_d+?8us06km9$qT+ux>^D#t?*Q2b#G@W zWT>K(YQS5q1w~=oMZb7kofQHDQ?~U|tmT5l{`6|JGXxJ691gI_6g~qIlFQ0(&iNDg*#j>HP#5^X0;zi zbCD0H&aL+^PELvbYk252%C2llD$eg&lU=ALBGa)W>(5+V%5>xWxvj}Fm$DUej6~nu zd^>L~w`Zc@sHy_xQuYy=yuf~>Q{j-z2h$g(x27%*GUw&xmHF9u^}W@oN~1wxq~dxi zmL4sb-QE2?a^0A`aAD)pxl37hW%(OtTB{QLYb!`Hyk`pyiR_h`-ptD78Hqu9o&e~4 zTqMTC^A!y0y?&@%#(V&aA{^a!f)L`p8<+SBv z=$H#>=Jx8>`!wxu@~<_J=G8Q9tV4=zWeS-O=YNdT3aWqzcAc$%hvwY!& zTA@Wl((>wZ-my_7x{9K%ejJe}3aOZRJ%$k1&E&+zw7w(e5s9j!0}bd?ba2V5{JFQE z@P&GuVVTQ-3zKKp&z{*jQzqj3k%mVB64)bY*E95>&N3ogzvt zN;hpnZT*e)txHn_HM?L4Pvo7R7^CB;Ak;+tZ;D)bHcOOQGsfcdOrnSt zpZ4HnVrh`l4Vg^73xr3$apnwdncmpAaB1`6Me|d+`A_J@jdPQmXD^8NRJ%K9N;6l$ z_r}xF!l5MBd6J2dEQ;zTxKTWb#ZapG7&Rg)lBpAPXeo2OWAs&>J0byA5K&kpmBGiz zr>bO1=#!D+eBc}Fn2c9~SX-E1oL`-32MJQJB8^L$TeLCAfJ$BJ>gxY#?D}1!2%_*K zB6pWwt03n;Fy@jo#}x_z8v{lVw6HMj=6)FPE@AHuj9R1-1g(Q;A(}=j{|Fnw<~kb@ zYr(==3%~EpyuH~wSA3A$`SIDf$pSVY{nwL{BR}T4^_fGFTY9X=CGJv>k%b-Syoy%n;!XzSu^r*L)b_dGhxmS2FSXBC_E* zw#}}hh3cdj0zI4B7#@-hwtM&WMh06XN>Ai5vB4P8o?S=6m}( z7Ll7*iosYyTd;3oad>|ar-nr20OM?@GZ_pH#bKW@*r7EoZ*~>8f1sNbuqljb7lO5I zA&lm+dE9U@2q7Kr@?!Y+_RXE7X$HG+h=EQ$=&O?f4(?1Yrtea~>3!th;6TiRDBD0}E5?ySFo&~rlOpb*40j(m=7C=qkkj+% z^eH_D9$uA@tQ^5-IC6W4`|{Xh_-i-@8IBxh;y_}^#mf6M#=R`ZJqM0u;-7MmO3Hf@ z;oz*6mG^zXY3-83^?FIqxk9jtmE!|^Op`crA)CNi9D(Nk47cS^Icg>O`yOzbF1a=6 zFHR#o-*=0&euFB2PTuQI#6*@*M8h*NW^MFQ&T{aH}Ee_M|G?b<^V0qVMJ$?kx^P zzdBQ=c_Qu(e$eBTtHbD@z;QU45JMRTeclKD>TxYPlYQ2{#7EU2&tBE!TZ-=y5Wa_T n%$8yI#*uBkXvOKg%#F_ICQ*G#7 diff --git a/bootloaders/THINGPLUS_RA6M5/dfu.hex b/bootloaders/THINGPLUS_RA6M5/dfu.hex index 47049a1a..11e20df2 100644 --- a/bootloaders/THINGPLUS_RA6M5/dfu.hex +++ b/bootloaders/THINGPLUS_RA6M5/dfu.hex @@ -1,10 +1,10 @@ -:1000000078AB0020A922000089030000FB02000059 -:10001000FB020000FB020000FB020000FB020000EC -:10002000000000000000000000000000FB020000D3 -:10003000FB02000000000000FB020000950500002C -:10004000BD12000005170000A5050000B305000063 -:10005000000000000000000000000000991F0000E8 -:100060003D1F00001D0A0000190B000000000000E9 +:10000000B8AB00205D22000045030000F1020000B3 +:10001000F1020000F1020000F1020000F102000014 +:10002000000000000000000000000000F1020000DD +:10003000F102000000000000F10200005105000084 +:100040003D110000A9150000610500006F050000CA +:1000500073050000770500007B050000591F0000B4 +:10006000FD1E0000810900007D0A00000000000064 :100070000000000000000000000000000000000080 :100080000000000000000000000000000000000070 :100090000000000000000000000000000000000060 @@ -30,815 +30,842 @@ :1001D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F :1001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F :1001F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F -:100200000A4BCAB253F8300011F07F030BD00849F3 -:10021000D20901EB0211194491F878301BB1373340 -:1002200000EB430070476030704700BFE02E0000D5 -:10023000B805002070B50C4C5D08A042104623F0B4 -:10024000010404BF033002320C44A14207D16FF015 -:10025000010202FB05330BB10B78037070BD31F85E -:10026000026B1680F1E700BF00101140084B03EB52 -:10027000C000426853B2002B08DB012102F01F02CC -:1002800001FA02F203495B0941F82320704700BFDD -:10029000E02E000000E100E00A4B03EBC0004268E2 -:1002A00053B2002B0DDB012102F01F0201FA02F212 -:1002B0005B090549203341F82320BFF34F8FBFF37B -:1002C0006F8F7047E02E000000E100E038B5054672 -:1002D000FFF796FF044678B12846FFF7DDFF238835 -:1002E000284603F0030343F0020323800223238004 -:1002F000BDE83840FFF7BABF38BD00BE7047FFFF0A -:100300000123074AA2F80431B2F804319BB2002B52 -:10031000FAD10123A2F80031024A936013607047BA -:1003200000C0014000700040064B93F826101A6A86 -:10033000054BC2F3026253F82130D340034A1360E5 -:10034000704700BF00E001407C05002098050020B8 -:10035000A0F101000028FBD17047FFFF48434FF494 -:100360007A71074BA0FB01011B680649B1FBF3F151 -:10037000B0FBF1F0800801D0FFF7EABF704700BF83 -:100380009805002000CA9A3B034AB2F840319BB25C -:10039000A2F83031704700BF0060004010B5EFF3A5 -:1003A0001081012383F310880F4A32F810309BB27A -:1003B0002BB132F81030013B9BB222F8103032F8EA -:1003C00010309BB263B9094A094CB2F8FE3334F8D5 -:1003D00010009BB243F4254323EA0003A2F8FE3346 -:1003E00081F3108810BD00BF2889002000E0014083 -:1003F000782E000030B5EFF31084012383F31088CA -:100400000D4A32F810309BB263B90C490C4DB1F86B -:10041000FE3335F810509BB22B4343F425439BB277 -:10042000A1F8FE3332F8103001339BB222F81030BD -:1004300084F3108830BD00BF2889002000E001400F -:10044000782E00002DE9F84F044600274FF0010BED -:10045000414D23889F422AD3EFF31080012383F379 -:1004600010883E4B196819B93D4AD1704021D170AE -:100470001A6801321A6080F310880020394D2188F3 -:1004800082B291424AD8EFF31081012282F31088A0 -:100490001A6812B11A68013A1A601A681AB9304B10 -:1004A000DA708022DA7081F31088BDE8F88F4FF09F -:1004B0000008DFF8B4904FEAC70A636839F8022BE6 -:1004C00003EB0A018988914217D153F80A300BFADD -:1004D00008F603F0B853B3F1807FF6B295F8BB3459 -:1004E00012D1334209D10120FFF784FF95F8BB34C4 -:1004F0001E4385F8BB64FFF751FF08F10108B8F10E -:10050000030FDAD10137A4E73342F6D00120FFF719 -:1005100071FF95F8BB3423EA0606EAE7666882B203 -:1005200006EBC201898856F832600A0A16F4803F49 -:10053000C9B24FEA02120AD0571855F827C06FF314 -:10054000104C45F827C026F4803C45F827C00A44E3 -:1005500045F82260013092E700E001403089002038 -:10056000000D084000080840B02E0000EFF30380A3 -:10057000103840B27047FFFF054BC03053F82020C1 -:100580006FF3104243F8202053F82030704700BF2B -:1005900000600040024A136801331360704700BFD7 -:1005A000708B002008B5FFF7E1FFBDE80840FFF7BA -:1005B000E3BFFFF7F7BF0A4492B291424FEA40000F -:1005C00001D8824201DB121A92B2104670472DE91F -:1005D000F341B1F808C04C891FFA8CFCA4B2B1F801 -:1005E00004E0A44536BFC4EB4E05ACEB04056544FE -:1005F000ADB2AE450F461E4608D27546F4452CBF37 -:10060000ACEB0E040CEB0E04A4B24C813DB92C46AD -:10061000A846294614E0ACEB0E0C1FFA8CFCE6450C -:10062000F9D9A6452CD9D7F80080A44508EB0401D8 -:100630002AD8A5EB0E05AEEB04032C44A4B29DB260 -:10064000B54228BF35462B46CDE90002FFF7F2FD43 -:10065000DDE90002731B9BB243B19C4228BF1C46DC -:1006600041462346FFF7E6FD2544ADB279892A4687 -:10067000B88889B2FFF79FFF788102B0BDE8F081AA -:10068000A4EB0E04A4B2CCE74FF000084446D7E731 -:100690002DE9F341184C0746E5883DB90120257046 -:1006A0006570A570E57002B0BDE8F081B0F85E80BD -:1006B0002E4608F07F08454528BF46464EB1637A6E -:1006C000216813F0010F00F1140233460DD0FFF73B -:1006D0007EFF464538BF4FF40043A5EB06054FF0BB -:1006E000000038BF7B84E580DDE70191FFF7A2FDC4 -:1006F000019931442160ECE7B80500200C232DE975 -:10070000F347344E044603FB0163B3F806800D46FD -:10071000B8F1000F1AD131B101F1370234F81230BB -:100720005904FBD406E04FF0E023D3F8F03DD8079E -:1007300000D500BE0C21002301204D4372197355D2 -:1007400053709370D37002B0BDE8F0878BB243F45E -:1007500080620285A0F86430B0F86CA01FFA8AFAB3 -:10076000238D03F00F039D42FAD1638D9B04FCD5CA -:10077000D045474628BF57468FB14FF00C0909FBBB -:1007800005F906EB09035B7A56F8091013F0010F1F -:1007900004F118023B4614D02046FFF718FF5745D6 -:1007A0003CBF4FF40043638500232385208D10F068 -:1007B0000F00FBD10C2101FB0565A8EB0707EF80BB -:1007C000C1E720460191FFF735FD0199394446F80C -:1007D0000910E4E7B8050020074B1B78834206D9CF -:1007E000064B00EB40001B6803EBC000704714BFD2 -:1007F00000200348704700BFA00500209C05002092 -:100800001C2D0000CB6802490B610121184700BF75 -:10081000A40500200346034A10780BB1FFF726BD5C -:10082000FFF73ABD380500200222024B5A80002211 -:100830001A717047500700200022024B1A80FFF700 -:10084000F3BF00BF500700200020FFF7F5BFFFFFF8 -:100850008B7970B5012B12D1CB79022B0FD10023EC -:1008600018468D78CC79022C1AD1824209D84FF0E3 -:10087000E023D3F8F00D10F0010024D000BE0020DA -:1008800021E08C78AC42F2D1CE78DCB2A642EED137 -:100890000C780133214420448C7980B2012CE1D0C2 -:1008A0004B78212BE3D1084B8A7809301A70B1F8C4 -:1008B000053080B2402B06D94FF0E023D3F8F03D4D -:1008C000DB0700D500BE70BD50070020704710B593 -:1008D00001F1080400F00F02D3B2092ACCBF37336C -:1008E000303304F8013DA1424FEA1010F2D110BD9F -:1008F00008B50146FFF740FEBFF35F8F012201F00C -:100900001F039A404B099B0003F1604303F56143C9 -:10091000C3F880211A6008BD0122430900F01F00BE -:1009200002FA00F0044A203342F82300BFF34F8F4D -:10093000BFF36F8F704700BF00E100E010B4090102 -:1009400000F16044C9B204F5614484F8001303491E -:1009500041F820205DF8044BFFF7CABF348900201E -:1009600037B5C36B04460A466D468BB193E8030066 -:1009700085E803001A70226C18465A60A26B9047F3 -:10098000E36B1BB195E8030083E8030003B030BDBF -:100990002B46EFE74FF4964313B5019343680446A3 -:1009A0001A7842B193F91100FFF7A2FF636893F937 -:1009B0001300FFF79DFF4AF680230A4AA2F884300D -:1009C000B2F884309BB2802B02D1002002B010BD5F -:1009D000019B1BB1019B013B0193F1E74FF4FA70BE -:1009E000F4E700BF00E07F4037B5836B04460A465A -:1009F0006D468BB193E8030085E80300E16B1A7143 -:100A000019601846626B9047A36B1BB195E8030011 -:100A100083E8030003B030BD2B46EFE710B5FFF7C6 -:100A2000A5FDFFF7A9FDFFF7A1FD3A4B53F82030D4 -:100A30001A69117BC1F30000C9074FD493F82C1039 -:100A400093F82A408C4215D093F82D0020B102294A -:100A500002D15223D3720CE093F82810D17093F88E -:100A60002B20013A83F82B2093F82C20013283F8B5 -:100A70002C2010BD196A41B393F82D404CB95A6A25 -:100A800098690139805C013219625A621B69D87019 -:100A9000EFE793F831406CB1012983F8310004D1BC -:100AA00020211A699172FF20F0E790721A6A012AD8 -:100AB000F9D1F5E7507999695A6A88541A6A013A66 -:100AC0001A625A6A01325A62F0E793F82E1081B125 -:100AD0005221D172012283F83020CAE793F82D10F9 -:100AE00011B193F8311031B100211962012183F85D -:100AF0002F105423AEE7507999695A6A88541A6ABC -:100B000093F82E10013A1A625A6A01325A621A692F -:100B1000DDE700BF3489002010B5FFF727FD2D4B1E -:100B200053F820000269D37A6FF3C303D37290F8AD -:100B30002F2002F0FF0332B1F02201210369DA72A3 -:100B4000FFF752FF1BE090F82A1090F82C209142FA -:100B500029D0D2B901290CBF90F8283090F829305B -:100B600000210269D1720269D37090F82B30013BE9 -:100B700080F82B3090F82C30013380F82C30FFF7C0 -:100B8000F5FCBDE81040FFF7F7BC90F82D1001F020 -:100B9000FF0431B1022AE3D190F8293043F0010378 -:100BA000DEE72346DCE7026A002AE8D190F82D3020 -:100BB00090F83040002B14BF0221032103690CB1CF -:100BC000DA72BDE7F022DA720269937803F0CF039C -:100BD0009370B5E7348900200022084B1A719A7887 -:100BE000042A02D103229A707047072AFCD11A788E -:100BF00012F0040F14BF06220822F4E75007002069 -:100C000008B50378012B06D103490B881BB1FFF708 -:100C1000E3FF00230B8008BDDE88002073B5344B52 -:100C2000344CDD68A54209D11A6A3AB993F83020EC -:100C300022B90826304A5E60127B1A720022A54251 -:100C40008DF804008DF8051083F82E2031D1596BF2 -:100C500079B301A999610221D961197A012907D1D2 -:100C600083F829205A6883F82A10520083F8282034 -:100C70000022022183F82D2083F82F2083F83120D1 -:100C800083F8332083F82C205A62196293F82D20C0 -:100C900093F82A1083F82B1012B1012283F8312027 -:100CA000B4211A69917093F830204AB951221B6916 -:100CB000DA724FF47A710520FFF750FB02B070BD75 -:100CC000002283F8302093F82A201969012A0CBFEA -:100CD00093F8282093F82920CA7093F82B20013A22 -:100CE00083F82B2093F82C20013283F82C20E0E7A6 -:100CF000F88A0020433249534C050020030143EA9F -:100D0000801040F4847040F001007047002802DB3E -:100D1000014AFFF713BE70474C8B00202DE9F84FB6 -:100D2000404F804607EBD01393F827408B4614F0D2 -:100D3000010416464FEAD01A0BD04FF0E023D3F847 -:100D4000F03DD90703D400242046BDE8F88F00BE4B -:100D5000F9E7354A92F8009093F82720484642F088 -:100D6000010283F82720314B53F83950FFF794FAEA -:100D70000DB900BEFEE7B8F1000F3DD04FF484631B -:100D80002B842B8C9A06FCD5294B5A7A9E806FF3C4 -:100D900000025A72DE80002E3BD0C3F800B0B8F1DA -:100DA000000F32D0B5F86030180403D5B5F85430D0 -:100DB000190627D44FF0E023D3F8F03DDA0700D529 -:100DC00000BE4846FFF752FA002CBDD107EB0A03DC -:100DD00093F8272064F3000283F8272093F8272054 -:100DE00064F3820283F827204FF0E023D3F8F03D2C -:100DF000DB07A8D500BEA7E7A5F820802B8C9B06B3 -:100E0000FCD4C1E72846FFF743FC0124A5F8604065 -:100E1000D7E71E705E709E70DE7005230124A5F872 -:100E20006030CEE7DC07002038050020E02E00000F -:100E3000B805002030B5184DAB686D689C6E2D78F4 -:100E4000032D98BF013408B1A0421CD35B6BD207BD -:100E500054BF03F01F03C3F30443032D07D91B0939 -:100E600083F0010348B9A3B902234B6030BD03F0FE -:100E70000C031A1F53425341F4E7A04201D3002B45 -:100E8000F2D10323F1E7032D98BF00F1FF30086092 -:100E9000ECE7002CE8D0F4E74C8B0020F0B501F033 -:100EA0000307032F0C4685B007D02F4E01F00C022C -:100EB00073681B78062B02D122B905B0F0BD0AB1C8 -:100EC000032BFAD13268294B9A42F6D1B3685B6E94 -:100ED00001338342F1D34FF0FF32002302A9CDE961 -:100EE000022322460190FFF7A5FFB2680399156B14 -:100EF0000198B9B914F0080F0CBF0223042314F0B1 -:100F0000020F08BFDB19DDF808C00BBF123302EB7C -:100F1000830302EB8303C3F84CC00CBFC3F804C0C7 -:100F2000C3F850C0630642BF136C43F480031364DC -:100F3000012F15D025F44035022C45EA01450AD190 -:100F400019B1012202A9FFF775FF039B25F0407537 -:100F500045EA036501E0002FF7D1B3681D63ACE7F4 -:100F6000022CEDD0F1E700BF4C8B0020545047001D -:100F7000002210F0800F11460CBF80201046FFF7B2 -:100F8000CDBEFFFF10B40346064C006822465968E8 -:100F900003C20022C4E902225DF8044B1878FFF76F -:100FA000E7BF00BFA4050020F8B5038944899BB2C0 -:100FB000A4B28588A34236BFC4EB450CA3EB040C56 -:100FC0009C441FFA8CFC654506461ED80020074647 -:100FD00003460446944228BF14463D19AF422BD124 -:100FE000121B92B23AB1934228BF1346C2189042E4 -:100FF00027D123449CB231892246B08889B2FFF7B9 -:10100000DAFA3081F8BD5B1B9BB29D42FBD9A54249 -:101010000FD93068A34200EB030735BF0020EC1A5C -:10102000E31AA3EB0C0335BF9CB2A4B203469BB2F8 -:10103000D0E7641BA4B2EAE791F800C007F801CB3F -:10104000CCE70D7800F8015BD1E7FFFF70B50546EE -:101050000024134EE0B2FFF7BFFB38B94FF0E02396 -:10106000D3F8F03DDB0700D500BE70BD43682846CD -:10107000984701343278E3B29A42EBD23B22002106 -:10108000084801F0A4FD1022FF21074801F09FFD50 -:10109000BDE870401422FF21044801F098BD00BF54 -:1010A000A0050020DC070020DF070020EF0700205C -:1010B00070B50589038942899BB292B286889342B2 -:1010C00036BFC2EB46029B1A9B189BB29E42044657 -:1010D000ADB217D8C079C00914D170BD9B1B9BB2AB -:1010E000B342FBD2E2882068C2F30E0202FB030087 -:1010F00001F060FD01222946A088FFF75CFA2081FB -:101100000120EAE72B46EBE77FB543780446023B34 -:10111000032B12D8DFE803F00255151D00212A4BDE -:101120001A786FF300021A701A786FF341021A707E -:1011300059701A7861F382021A70244B214618689C -:1011400032E0214B1A78D50739D51A7842F00402DB -:10115000F2E71D4A1378D80731D513786FF382036D -:101160001370EAE7FFF738FB20B1436913B16168F8 -:101170002078984701353378E8B28342F2D2124A98 -:10118000137859071BD5137801A96FF382031370E5 -:101190000023CDE90133039323788DF80430052330 -:1011A0008DF80530094B18680430FFF781FF30B91E -:1011B0004FF0E023D3F8F03DDB0700D500BE04B0CC -:1011C00070BD0025024ED6E7DC070020180800207D -:1011D000A005002013B5124B9889D98993F90040D6 -:1011E000421A92B2402A28BF4022002C0EDA8842CE -:1011F00012D099680B48019201F0DCFC802009496B -:10120000019A02B0BDE81040FFF788BD88424FF058 -:10121000000003D10021F4E78020FBE70149F0E75B -:10122000A40500209C07002070B50446164D0068F8 -:101230002E460B466168AB6003C60021E981E18858 -:101240008A4228BF0A46AA81E18881B152B14BB9CE -:101250004FF0E022D2F8F02DD20701D4002070BD6B -:1012600000BEFBE7FFF7B6FF28B10120F7E72078C3 -:10127000FFF77EFEF8E74FF0E023D3F8F03DDB0701 -:10128000ECD500BEEBE700BFA405002007B58DF844 -:1012900000208DF801301A0A1B0C8DF80330002352 -:1012A0008DF802208DF80410062269468DF805306D -:1012B000FFF7BAFF03B05DF804FBFFFF2DE9F04F25 -:1012C00089B0FFF753F9FFF757F9A74BB3F8401070 -:1012D000CA4362F4784292B2A3F840200A048CB266 -:1012E0000CD5B3F8402012F0800FC2F3C0111A8859 -:1012F00014BF42F0100261F304121A8067040ED585 -:101300000025052305A8CDE9055507958DF815306D -:10131000FFF7FAFE944B1A8E65F34D321A86A60437 -:1013200011D5914E338E9D040DD50025032305A8BC -:10133000CDE9055507958DF81530FFF7E5FE338E9D -:1013400065F34D333386E00407D504F07003202B9A -:1013500000F0D7805ED8102B75D022052DD5E3077D -:1013600040F1EE80804BB3F84020170725D54FF4AD -:1013700080425A84B3F8542003A9ADF80C20B3F886 -:10138000562006A8ADF80E20B3F85820ADF810206E -:10139000B3F85A20ADF812204FF6F772A3F84020A8 -:1013A0000023CDE905330793062308228DF8153075 -:1013B00001F000FC05A8FFF7A7FE660515D5002281 -:1013C0006948B0F84A30A0F84A20DD070DD5FFF78C -:1013D0005FF950B14FF4E0608022644B9B88CDE907 -:1013E000050205A80793FFF78FFEE1050FD55E4BB9 -:1013F0005E4CDA8EB3F84660DFF880A1B6B21640D4 -:10140000F24392B2A3F84620002E40F0B98009B012 -:10141000BDE8F08F602B04D013D804F06003402B9C -:101420009BD10023CDE905330793042305A88DF84C -:101430001530FFF769FE4C4A138E43F400531386B0 -:101440008BE7702BECE70122474B5A87DA864FF483 -:1014500080425A8400221A851A8D12F00F02FBD1A5 -:101460009A859A8D12F00F02FBD1012394464FF416 -:1014700000774FF480763E4D3E493B481FFA83FE8D -:10148000A0F864E0A0F868C021F8137021F81320D8 -:1014900025F823600133062BF0D100254FF40072AC -:1014A0002846314E9FB2A6F86470A6F8680021F86D -:1014B000132021F8135001330A2BF3D19822002175 -:1014C0002A4801F084FB338903F00703013B9BB2F8 -:1014D000022B0DD8284ACDE90555D35C012207958A -:1014E0008DF815208DF8183005A8FFF70DFE34E7AC -:1014F0004FF0E023D3F8F03DD9077FF52EAF00BEC3 -:101500002BE7194BB3F8503013F07F023FF425AFAF -:1015100000230521CDE905338DF80C30ADF81030EE -:10152000ADF81230079306238DF80D10ADF80E209C -:1015300003A9082206A88DF8153001F03BFBD3E77C -:1015400014F007037FF439AF074A0721128CCDE965 -:10155000053312F0200F14BF802200228DF81510E1 -:101560008DF81820079325E700000940B8050020F2 -:101570008C0009406E000940162D0000140009403F -:1015800096FAA6F50C22B5FA85F502FB0542137A08 -:10159000DB091DD029465948FFF7B0F890B10C235C -:1015A00003FB05439A88197ADB8805A8D31A002221 -:1015B000CDE9052207228DF818108DF81520079324 -:1015C000FFF7A2FD012303FA05F526EA05061BE74E -:1015D0004A4B002D58D0B2F806B0AAB21A85A3F82B -:1015E0006420B3F86C901FFA89F91A8D02F00F028B -:1015F0009542FAD15A8D9204FCD55F8D0C23C7F326 -:101600000B074F4528BF4F46BB45D84628BFB846B5 -:101610006B43E058E218B8F1000F08D0537ADB07AB -:1016200023D5424636490190FFF7BEFC0198C145DB -:1016300088BF4FF48042314B88BF5A8500221A85FB -:101640001A8D1107FCD10C2303FB0542ABEB0801FB -:10165000C145D18001D8BB45B4D800226B43E11805 -:10166000E2544A708A70CA7098E70346234900EB37 -:101670000802934203D10C226A43A350D7E791F8A2 -:1016800018C003F801CBF4E7B3F85E905F8C09F063 -:101690007F09C7F30B074F4528BF4F46B4F806B084 -:1016A000BB45D84628BFB846B8F1000F07D0627ACC -:1016B0002068D20717D542465146FFF775FCC14551 -:1016C00082BF4FF480420D4B5A84ABEB0803C145F7 -:1016D000E38002D8BB453FF675AF002323706370EB -:1016E000A370E3705BE700EB0802904201D1206039 -:1016F000E5E7197D00F8011BF7E700BF000009408E -:1017000018000940FFF7DABD2DE9F04F87B0B14B63 -:1017100000201D682B689847A989EB8989B29BB284 -:101720002889994236BFC3EB4002CA1A521894B2B4 -:101730009CB1A04205D281422CBF091A09188BB274 -:10174000EB81984226D96A896968C2F30E0202FBCE -:10175000031103A801F02EFA0124E9892246288901 -:1017600089B2FEF728FF2B68E88101209847002CFA -:1017700000F09C839DF80D30013B072B00F2428363 -:10178000DFE813F00B00190040039F039F032300C1 -:101790001E03A2031B1A9BB2D3E79DF80C00FFF7B0 -:1017A00055FC142200218C4801F011FA9DF81020FC -:1017B0008A4B9A70ABE79DF80C00FFF747FC1422A8 -:1017C0000021854801F003FAA1E7844CDFF8088284 -:1017D00023789DF80C5043F00103237094F82730D0 -:1017E0006FF3000384F8273094F827306FF38203F7 -:1017F00084F8273094F828306FF3000384F82830F9 -:1018000094F828306FF3820384F828300023C8F856 -:1018100010309DF8103003F06002602A11D14FF0B3 -:10182000E023D3F8F03DD90700D500BE00219DF894 -:101830000C00FEF74BFD80219DF80C00FEF746FDE5 -:1018400065E7402A0DD1664B002BEFD001212846D9 -:1018500004AAC8F8103000E000BF00287FF457AF9A -:10186000E4E703F01F07012F00F0D481022F00F0FE -:10187000FA81002FD3D1202A0FD19DF814300F2BDD -:10188000D4D82344D878FEF7A7FF01460028CDD04E -:1018900004AA2846FEF7B6FFDFE7002ABFD19DF86D -:1018A0001130092BBBD801A252F823F0FF1B000016 -:1018B000ED1B00001F180000D91B00001F180000BE -:1018C000D5180000AB1A00001F180000EF18000028 -:1018D0000319000006AB13E903000023C8E9023333 -:1018E0002378C8E9000143F0020323700FE763780F -:1018F0008DF80A3001220DF10A0104A8FFF794FCCB -:1019000005E79DF8126063789E4200F0C980637815 -:10191000C3B12846FEF7C0FC4FF00C094FF00A0C8B -:101920004FF0010E4FF000082E4FBCF1010C21D1F9 -:101930002846FEF79BFC94F802802846FFF786FBBA -:1019400084F80280002E00F0AB804FF0010A23786B -:10195000DFF898B023F0300323709BF80130042B9C -:1019600046D04FF0E023D3F8F03DDA077FF557AFCC -:1019700000BE54E709FB0C731B7A002BD5D01A4A22 -:1019800003F07F0ADB0952F83520190107EB031336 -:10199000534493F87830D08E0EFA03FB80B220EADD -:1019A0000B00D0869BB103F1370002EB4000A0F89A -:1019B000008098B209FB037339448A44A2F864009A -:1019C000A2F8688083F808808AF87880ADE702F191 -:1019D0006000ECE718080020A4050020DC070020C8 -:1019E00000000000B8050020E02E0000652D00007A -:1019F0004FF00009B14BA3EB0B0297B25FFA89F8E5 -:101A00004046FEF7E9FE0028ABD083683A465946C7 -:101A10002846984708283AD9874238D300220CE054 -:101A20009BF802C00132634454FA83F393F803C075 -:101A3000BCF1FF0F95D183F80380D3B29A45EFD85C -:101A40005844584511D89E4B1B78434589D39B4B2E -:101A5000984225D243780B2B03BF037890F803A05C -:101A6000C0184FF0010A834677E79BF80130052B39 -:101A700009D19BF8022002F07F0304EB430303EB40 -:101A8000D21383F813809BF800309B44D9E78C4B2A -:101A900009F1010918785FFA89F39842AED260E73C -:101AA000667004A8FFF76EFA31E6BDF81200030A6B -:101AB0005A1EC0B20E2A3FF6B9AE01A151F822F06B -:101AC000FD1A0000211B00003F1B00002D18000024 -:101AD0002D180000C11B0000211B00002D18000064 -:101AE0002D1800002D1800002D1800002D180000E2 -:101AF0002D1800002D180000091B0000122271494A -:101B000004A8FFF791FBA8E66F4B002B3FF48EAEC5 -:101B100000E000BF014600283FF481AE4A88EFE7AD -:101B2000022B01D16949F9E7694B002B3FF47EAEE6 -:101B300000E000BF00283FF472AE0146EEE770B946 -:101B400002226449644801F035F801204000821CFB -:101B5000624942F440730B8002F0FE02D0E7052890 -:101B60003FF664AE5E4B5F4C53F820602378BBB900 -:101B70005D4D2146D5F89000FEF7A9FED5F89400FA -:101B800004F10801FEF7A3FED5F8980004F1100156 -:101B9000FEF79DFED5F89C0004F11801FEF797FEB4 -:101BA000304601F01CF800234C49C0B2DAB2904232 -:101BB00003F10103CAD9541CB25C21F81420F5E7E3 -:101BC0004A4B002B3FF432AE00E000BF0146002834 -:101BD0003FF42CAE027893E7BDF81230012B7FF46E -:101BE00025AE237843F0080323705AE7BDF812307E -:101BF000012B7FF41BAE23786FF3C303F4E7237844 -:101C0000C3F340129B0803F002031343ADF80A30FC -:101C1000022270E69DF814200F2A3FF607AE2244F8 -:101C2000D078FEF7D9FD014600283FF4FFAD2846E5 -:101C300004AAFEF7E7FD00287FF469AD9DF81020A7 -:101C400012F060027FF4F2AD9DF81110A1F10A00CC -:101C500001283FF6EBAD0A29C8F810207FF421AF28 -:101C60008DF80A2046E69DF814B00BF07F06092E89 -:101C70003FF6D5AD730004EB460606EBDB16F07CB1 -:101C80000093FEF7A9FD4FEADB1A81462AB100282E -:101C90003FF4CCAD014604AAFBE59DF8112002F00B -:101CA000FD00012824D0002A7FF4B9AD96F8272042 -:101CB000C2F34002ADF80A20AAE700BF802D000061 -:101CC000A0050020802D0000000000005C2D000019 -:101CD00000000000192D00005206002050060020D0 -:101CE000F02E0000B48A00200081000100000000F6 -:101CF000BDF81230002B3DD1774B012A06F12006AA -:101D00001F78F27948D1930734D559463846FEF703 -:101D100077FA0646F8B1714A384652F837200192F0 -:101D2000FEF7BAFA4FF48070019A3080BAF1000FD2 -:101D300002D0012232800BE06949594491F87810B1 -:101D4000A2F86410B2F86820C2F38132012AF0D1FF -:101D50003846FEF78BFA009B2344534493F8272020 -:101D60006FF3410283F8272093F827206FF30002D6 -:101D700083F82720B9F1000F3FF4C9AC4946284643 -:101D800004AAFEF73FFD0023C8F8103094F828306D -:101D9000D8073FF5BCAC84E69607EBD459463846E5 -:101DA000FEF794FA009B2344534493F8272042F013 -:101DB000020283F8272093F8272042F00102D7E798 -:101DC0009DF81010474B01F07F0403EB440303EB35 -:101DD000D11393F827004FEAD11C6FF3000083F86A -:101DE000270093F827006FF3820083F82700002C68 -:101DF00051D13D4C9DF80C502378059EBCEBD31F70 -:101E000018D046B14FF0E023D3F8F03DDB077FF563 -:101E10007EAC00BE7BE4354B1BB12146284600E07A -:101E200000BF2369002B3FF472AC032128462E4AE1 -:101E300098476CE494F90030002B07DBA068002879 -:101E40003FF465AC32462A4900F0B4FEA268E3894B -:101E500032443344A260E2889BB29A42E38101D0CB -:101E60003F2E15D8236933B92078FFF781F8002871 -:101E70007FF44DACC6E7022128461B4A984701462D -:101E80000028F1D12846FEF721FA80212846D5E422 -:101E9000FFF7A0F9EBE7D87CFEF79EFC48B94FF0BE -:101EA000E023D3F8F03DDA0700D500BE07B0BDE867 -:101EB000F08F0469059B9DF811209DF80C00A04748 -:101EC00025E4084B1B7822E4049B002B3FF41FAC55 -:101ED000059898471BE400BF38050020E02E00005D -:101EE000B8050020DC070020A40500200000000049 -:101EF0009C07002008B50D4C0D4E256832782368EC -:101F00005B1B632B0CD9BFF34F8F0A490A4BCA687E -:101F100002F4E0621343CB60BFF34F8F00BFFDE7D5 -:101F2000FF2AECD0FFF7F0FBE8E700BF708B002042 -:101F30003805002000ED00E00400FA0570B5FEF75A -:101F400015FB1349134B0A7C53F820600546100714 -:101F5000D1F88010D3B214D41A0614D4DB0614D5E9 -:101F600011F4405F14BF07240624304600F060FEE1 -:101F70002846FEF701FB21463046BDE87040FEF7DB -:101F8000EFBC0424F1E70524EFE70724EDE700BFE9 -:101F900000E07F403489002038B5FEF7E7FA1A4B9D -:101FA00053F82040FEF7E8FA94F83450012D0CD194 -:101FB000236BE3B100220421204600F019FE08B390 -:101FC0002046BDE8384000F033BE022D08D1256B15 -:101FD0006DB12046BDE838400022402100F018BE17 -:101FE0000A4B93F8D430012B0CBF0325022500F0D7 -:101FF00017FE002384F8343029462046BDE83840D7 -:10200000FEF7AEBC38BD00BF3489002000E07F4041 -:10201000094B0A481A880A4B03EA8213094A03F556 -:102020008033128852080263074AC0E90A2300235A -:1020300080F8343000F0E4BDDC080020E4880020A3 -:102040000080FFFFDE880020DE08002070B51378D6 -:102050000C4603F01F010129154640F0108113F0D2 -:1020600060031CD152780A2A0FD00B2A40F0078156 -:10207000012C40F0CE806A88824B5A70FEF7D4FB68 -:102080002846BDE87040FEF77DBF012C40F0C180BE -:1020900022467D492846BDE87040FFF7C5B8202B91 -:1020A00040F0ED805378062B00F2E980DFE803F082 -:1020B00004361F5610161000012C04D12846FEF7D6 -:1020C00061FF204670BD032C40F0A380FFF712FF94 -:1020D000012C40F09E80FEF7A7FBEFE7012C40F0BB -:1020E0009880224628466949FFF79EF8E9E7012CC7 -:1020F00040F08F80634E347814F00204E1D0EC8815 -:10210000402C00F2BC8069882246614306F10C0035 -:1021100000F050FD224606F10C01BBE7012C78D1FE -:10212000584B1C7814F00104CBD09A78022A02D0C4 -:10213000052A40F0A480EA88402A00F2A08001220B -:102140001A716A88DA80EA881A81EA881AB103214A -:1021500099704F499EE706229A7091E7494A917813 -:10216000032905D0062956D0012C52D1002309E0BD -:10217000012C0BD113793BB153780421002B0CBFF8 -:1021800000236423D27851E00521FBE7032C40D1E2 -:102190001479002C3BD0042315899370D3883D4AD1 -:1021A000138047F6C07203F58063990112EA831326 -:1021B00015D172B6384A384882F8343021F4001309 -:1021C000B3F5803F38BF21F4FF514FF0010234BF17 -:1021D00021F01F0101F4FF0100F032FD62B62F4E25 -:1021E0002F4833882A461844294900F0E3FC3388F5 -:1021F0001D44ADB2B5F5004F358005D172B6FFF77D -:1022000007FF62B600233380FEF7E6FC59E705239B -:102210009370012455E7012C0DD11379D278002B4E -:1022200008BF02214FF0000318BF07212846BDE870 -:102230007040FFF72BB8032CEBD11479ECB10723D6 -:10224000937072B6FFF7E4FE62B600261249FEF7FD -:10225000C3FC4B680E6093F91100B04201DBFEF73E -:102260005BFB104D2E764B6893F91300002801DBC1 -:10227000FEF752FB00232B7523E70223C8E7002457 -:102280001FE700BF50070020510700205207002021 -:102290005C070020DC080020E4880020DE880020A5 -:1022A000DE08002000E07F408FB54FF47002C24B83 -:1022B000C24DC3F888209D604AF20353C04CC14907 -:1022C000A4F8FE33FEF71CF8BF4BDFF870C3BF4A1B -:1022D000DFF86CE3C3E900C24FF40042C3E9022116 -:1022E0001A61BB4AC3E905E2FEF71EF8002384F831 -:1022F0001334092384F8A23094F8803433B90121CF -:1023000040F2C44084F88014FEF728F80023AC485B -:1023100084F8813484F8803484F8323090F83C308A -:102320001F07FBD542F2017343F20212A0F84830B6 -:10233000002380F84A30028580F82A3090F83C303B -:102340009E06FBD50322A34B83F81C21A24B0362FC -:10235000052380F82630FDF7E7FF012380F83030B1 -:1023600080F8523090F8743043F0400380F87430B5 -:10237000934B93F87420D209FBD00622462183F8B0 -:102380006C2083F8741083F8742093F87420D209B9 -:10239000FBD193F8772042F0400283F87720884BF6 -:1023A00093F87720D209FBD0022283F86F20C6224F -:1023B00083F8772093F8772002F0BF0283F8772024 -:1023C0007F4B93F87760F609FBD14FF42542A3F8D1 -:1023D000FE232B68A3F5805383F30A887F48804A45 -:1023E0003146121A00F0F3FB7E487F4A7F49121AE9 -:1023F00000F0E0FB37467E4D7E4C641BA410BC42CF -:1024000000F3458200257C4CFDF78EFFC82001219A -:1024100084F82850FDF7A2FF84F8245094F8243063 -:10242000002BFBD194F8243043F0020384F82430CD -:10243000714B93F824209507C2F34004F9D401208E -:1024400083F82240FDF7D6FF5D4B83F8BB44FDF7D0 -:10245000A5FF0320FDF7CEFF23464FF6FF70674A26 -:1024600003F108010133092B22F81100F8D10320F0 -:10247000FDF794FF0320FDF7BDFF6FF0FF02604BF7 -:10248000604C9A64FF210C2201A800F0A0FB2546B5 -:102490000023012735F8022B6AB104A95A0901EB80 -:1024A000820203F01F0107FA01F052F80C1C21EA26 -:1024B000000142F80C1C0133602BEBD10199504A0A -:1024C000514B1167C3F88012029903205167C3F87A -:1024D000841203999167C3F88812FDF75FFF002308 -:1024E0004A4A03F1C00134F8020B0133602B42F871 -:1024F0002100F6D162B6464CDFF8489123684B457F -:1025000004D04448C4F80090FDF79CFF4FF47A7261 -:10251000414F3B68B3FBF2F3013BB3F1807F0AD23A -:102520004FF0E022F0215361234B83F82310002366 -:1025300093610723136123684B4502BF4FF4800268 -:10254000364B9A621E4B364AD3F80015914240F042 -:10255000CD814AF20252A3F8FE230022C3F80025DF -:102560004FF42542A3F8FE232E4B1A684A4504D0A7 -:102570002D48C3F80090FDF765FF2C4CDFF8C880AC -:102580002368434500F0AF804FF48073E360284B2D -:10259000002563600123274A2374A2606561C4E9B2 -:1025A0000655EFF3108183F31088234B1A6922F448 -:1025B00000021A611B6949E000ED00E00000000024 -:1025C00000E0014000366E017C05002000127A0018 -:1025D000001C4E0E00C00140211201209805002071 -:1025E000748B0020000000207C050020082F0000D4 -:1025F0007C0500207C05002000300840000D0840CC -:1026000000800040B82D000000E100E000600040C4 -:10261000408B00209C2D0000980500200000084001 -:1026200035817307388B0020B82E00004C8B0020BA -:10263000C02E00000098164000400840002D3101D7 -:1026400000C2EB0B54524F505450470081F3108896 -:102650004FF42542A36844F64B401A604FF4000241 -:10266000A36801A9DD62DD639D64DA624FF0004278 -:102670001A615A619A6149F695025D629D62DD6157 -:102680001D629A665A664FF0FF332A46CDE901353E -:10269000FEF7D0FBA268019B284653659365029B19 -:1026A000190641EA0341FEF729FB4FF4AA0395639B -:1026B000C2F888501364E3680004D36041F0030358 -:1026C00041F001015063136328461163FF21FEF7B7 -:1026D0001DFB29462846FEF719FB29462846FEF72A -:1026E00015FBC4F8008044F61F6344F6206261685D -:1026F0000878032898BF1A46A3689A66097819B91A -:1027000042F20F7159659965D96ACD0705D45A66A9 -:102710004FF4AA021A64E268DA6001210020FEF791 -:10272000BDFB23685C48434504BFD4E902325A60CC -:102730005A4B5B4C436000232376237580F834307A -:102740000123584D85F816342B6A39682D6AC3F376 -:10275000026201FA02F2C3F30273C5F30265DA40C2 -:1027600001FA05F35049EB408A423ED94F4902F540 -:10277000742202F23F22B2FBF1F203F5742303F25A -:102780003F23B3FBF1F343F6B85102F5F05292B296 -:10279000A4F8E42006225943B1FBF2F1816040F62F -:1027A000D8615943B1FBF2F1C1605900B1FBF2F1BC -:1027B000016154215943B1FBF2F141613C49594354 -:1027C000B1FBF2F1816144F250615943B1FBF2F186 -:1027D000416238495943B1FBF2F1016236494B433A -:1027E000B3FBF2F3C361354B03602B48344D00F06B -:1027F0001FFA01220221284800F02AFA2B78FF2B29 -:102800001FD13B2200212F4800F0E1F900222E4B7E -:10281000DA819A812D4A13602D4B23B12D4800E0B7 -:1028200000BF2D4B18602B4CF0B2FDF7D5FF0028F0 -:1028300040F053814FF0E023D3F8F03DD80700D5A6 -:1028400000BE264F264EDFF8A0802B78FF2B01D04C -:10285000FEF75AFF3A683368D21A632AF5D9D8F8D6 -:1028600000406433012120463360FEF717FB1D4B07 -:102870001A78002A00F07E81B4F5FA6F80F0758135 -:1028800000221A704FF4FA63C8F80030DDE755F8FB -:10289000043B98470137B2E5E4880020A42D0000EE -:1028A00000E07F4000E00140FF083D0040420F0093 -:1028B00038AF040080DE0F00A0F703004E45504FF4 -:1028C00038050020DC07002028050020180800201B -:1028D00000000000A00500209C050020708B002057 -:1028E0006C8B0020E0880020488B002093F81014A7 -:1028F000C80709D44AF20251A3F8FE13C3F8002511 -:102900004FF42542A3F8FE23A14D6A6A002A00F085 -:1029100093806B689F498B4203D09F498B4240F064 -:102920008B8095F90F30002BC0F2868095F910301E -:10293000002BC0F28180994CDFF874A2E368534504 -:102940007AD02B781F2B77D840F2FF31D940C907B6 -:1029500072D5117819B192F90320002A6CDA4FF080 -:10296000000803F5800303F58C531B022361AB6859 -:10297000256063602B7BC4F838802372EB69636346 -:102980002B6AE363EFF31080012383F310884FF089 -:102990000041834B95F800C05A6821FA0CF122EAF5 -:1029A00001025A605B6880F31088F0222368596A3C -:1029B000236983F802802369DA728B78226903F035 -:1029C00003031370FA2223699A714A7823695A70B3 -:1029D0000B7822699B0043F02003DBB2D3714A7964 -:1029E00023691A72CA7823699A740B792269DB0009 -:1029F00043F00103DBB25372232223699A722369E5 -:102A0000664A83F80D80697B95F90F00FDF796FF04 -:102A1000624A697B95F91000FDF790FFC4E90688CA -:102A2000C4E9088884F82D80C4F80CA084F82E80AE -:102A300084F82F8084F8308080219C20FEF7EEF807 -:102A400020219E20FEF7EAF8564A1368B3F5FA7F74 -:102A5000FBD34AF2025400204FF425454FF4803155 -:102A6000514AA2F8FE43C2F80005A2F8FE530B68D3 -:102A700003F07F43B3F1005F7FF476ADA2F8FE432D -:102A8000EFF3108E4FF0010C8CF31088444B5C6810 -:102A900044F400645C605C688EF31088EFF3108E81 -:102AA0008CF310885C6844F480545C605B688EF33F -:102AB0001088A2F8FE5380F30A8872B6BFF34F8FD6 -:102AC000BFF36F8F4FF0E0231861C3F8081D0B6848 -:102AD00083F308884B68984746E5036898470136B2 -:102AE0002278F3B29A42BFF49FAE00232C4A2B7097 -:102AF000536823F4006353602C4B1A8842F48062BD -:102B00001A801A885105FCD51A8840216FF34512A6 -:102B10001A801A8800206FF386121A801A8842F0F1 -:102B200001021A800522C3F8F020D3F800246FF3C5 -:102B30000412C3F80024B3F85E2061F30602A3F880 -:102B40005E200022A3F840204FF45D421A86012245 -:102B50005A87DA86B3F84020120642BF1A8842F03C -:102B600010021A80FDF782FB6BE6A4F5FA64C8F840 -:102B700000406AE644F61F6204F5FA649442C8F81D -:102B800000407FF662AE01221A7044F620637BE6B5 -:102B90004C050020A0860100801A0600F88A00205B -:102BA00000400840708B002000E001400000094018 -:102BB000433249530A44431E914200D1704710B535 -:102BC00011F8014B914203F8014FF9D110BD0244B5 -:102BD0000346934200D1704703F8011BF9E703460F -:102BE00013F8012B002AFBD1181A01387047FFFF98 -:102BF00001B40248844601BC604700BF7501002053 -:102C000001B40248844601BC604700BF490300206C -:102C100001B40248844601BC604700BF3501002072 -:102C200001B40248844601BC604700BF0100002097 -:102C300001B40248844601BC604700BFE1000020A7 -:102C400001B40248844601BC604700BFD1030020A4 -:102C500001B40248844601BC604700BF81040020E3 -:102C600000000504342E352E30004275696C742046 -:102C7000776974682052656E65736173204164766C -:102C8000616E63656420466C657869626C6520538B -:102C90006F667477617265205061636B6167652050 -:102CA00076657273696F6E20342E352E3000417256 -:102CB0006475696E6F00537061726B46756E205457 -:102CC00068696E6720506C7573205241364D35200F -:102CD0004446550040436F6465466C617368202F1D -:102CE000307830303030303030302F382A384B6147 -:102CF0002C36332A33324B67004044617461466C92 -:102D0000617368202F307830383030303030302FD9 -:102D1000382A314B67000100020904FF490800000E -:102D200039080000510800004D200000000000009C -:102D30000000000004000000060100000000000088 -:102D400008040000000C011307040000000C01132C -:102D500000050000000C0113010500000902240019 -:102D600001010080320904000000FE010204090490 -:102D7000000100FE010205092107E80340000101EE -:102D800012010002000000404F1B3600000101024A -:102D90000301FFFF00000103060100000500000021 -:102DA000342D000000000000010C000000000000B5 -:102DB00000000000020702086D006E006B006C004E -:102DC0000000000000003100300093019401000079 -:102DD00000000000000000000000000000000000F3 -:102DE00000000000000000000000000000000000E3 -:102DF00000000000000000000000000000000000D3 +:100200000A4B53F83000CBB211F07F010BD0DA0962 +:10021000074B03EB02130B4493F878301BB13733D1 +:1002200000EB430070476030704700BF183000009B +:10023000208B002030B50A4CA042104623F0010468 +:1002400004BF033002320C44A14204D1DB0744BF97 +:100250000B78037030BD31F8025B1580F4E700BF06 +:1002600000101140084B03EBC00393F90430002B3E +:1002700008DB0122590903F01F0302FA03F3034AC2 +:1002800042F82130704700BF1830000000E100E064 +:100290000A4B03EBC00393F90430002B0DDB012163 +:1002A0005A0903F01F03994002F12003044A42F85F +:1002B0002310BFF34F8FBFF36F8F704718300000CC +:1002C00000E100E038B50546FFF79AFF044670B13B +:1002D0002846FFF7DDFF238803F0030343F0020302 +:1002E000238002232380BDE83840FFF7BBBF38BD21 +:1002F00000BE70470123074AA2F80431B2F8043166 +:100300009BB2002BFAD10123A2F80031024A93607C +:100310001360704700C0014000700040064B93F826 +:1003200026101A6A054BC2F3026253F82130D340FB +:10033000034A1360704700BF00E00140C40500207D +:10034000A88A0020034AB2F840319BB2A2F83031AB +:10035000704700BF0060004010B5EFF3108101232B +:1003600083F310880F4A32F810309BB22BB132F869 +:100370001030013B9BB222F8103032F810309BB2A3 +:1003800063B9094A094CB2F8FE3334F810009BB245 +:1003900043F4254323EA0003A2F8FE3381F31088D7 +:1003A00010BD00BF0C8A002000E001400A2F0000B1 +:1003B00030B5EFF31084012383F310880D4A32F82F +:1003C00010309BB263B90C490C4DB1F8FE3335F8CF +:1003D00010509BB22B4343F425439BB2A1F8FE334C +:1003E00032F8103001339BB222F8103084F31088B9 +:1003F00030BD00BF0C8A002000E001400A2F000041 +:100400002DE9F84F044600274FF0010B414D23889A +:100410009F422AD3EFF31080012383F310883E4BD1 +:10042000196819B93D4AD1704021D1701A6801325A +:100430001A6080F310880020394D218882B29142E1 +:100440004AD8EFF31081012282F310881A6812B1A2 +:100450001A68013A1A601A681AB9304BDA708022A9 +:10046000DA7081F31088BDE8F88F4FF00008DFF8EC +:10047000B4904FEAC70A636839F8022B03EB0A010C +:100480008988914217D153F80A300BFA08F603F025 +:10049000B853B3F1807FF6B295F8BB3412D1334232 +:1004A00009D10120FFF784FF95F8BB34334385F869 +:1004B000BB34FFF751FF08F10108B8F1030FDAD19F +:1004C0000137A4E73342F6D00120FFF771FF95F81A +:1004D000BB3423EA0603EAE7666882B206EBC20190 +:1004E000898856F832600A0A16F4803FC9B24FEA8A +:1004F00002120AD0571855F827C06FF3104C45F870 +:1005000027C026F4803C45F827C00A4445F82260FD +:10051000013092E700E00140088A0020000D084009 +:1005200000080840042F0000EFF30380103840B2A9 +:100530007047FFFF054BC03053F820206FF3104287 +:1005400043F8202053F82030704700BF006000407F +:10055000024A136801331360704700BF648A0020A9 +:1005600008B5FFF7E1FFBDE80840FFF7E3BFFFF77D +:10057000F7BFFFF7F5BFFFF7F3BFFFF7F1BF0A447F +:1005800092B291424FEA400001D8824201DB121A36 +:1005900092B2104670472DE9F0471F460B894C89EF +:1005A0009BB2A4B292468A88A34236BFC4EB4205EE +:1005B0001D1BED18ADB2AA4281460E4605D29342EC +:1005C0000AD315469C1AA4B24C81002D37D09A420A +:1005D00006D89B1A9BB2FAE715469C18A4B24C8128 +:1005E000A24229D9D6F80080A34208EB04012AD8F8 +:1005F000AD1A131B2C44A4B29DB2BD4228BF3D4688 +:100600007F1B2B4652464846BFB2FFF713FE57B139 +:10061000BC4228BF3C465246234641464846FFF767 +:1006200009FE2C44A5B271892A46B08889B2FFF729 +:10063000A6FF7081BDE8F087A41AA4B2D0E72C46CB +:10064000A8462946D9E74FF000084446D5E7FFFF02 +:100650002DE9F843184C0746E58835B90120257087 +:100660006570A570E570BDE8F883B0F85E902E4621 +:1006700009F07F094D4528BF4E465EB1637AD4F834 +:10068000008013F0010F4146334600F114020DD0F3 +:10069000FFF781FF4E4538BF4FF40043A5EB060539 +:1006A0004FF0000038BF7B84E580DCE7B044FFF703 +:1006B000C1FDC4F80080EDE7208B00202DE9F84F44 +:1006C0000C23334E044603FB0163B3F806800D464A +:1006D000B8F1000F19D131B101F1370234F81230FD +:1006E0005904FBD406E04FF0E023D3F8F03DD807DF +:1006F00000D500BE0C22002301206A43B118B35478 +:100700004B708B70CB70BDE8F88F8BB243F4806276 +:100710000285A0F86430B0F86CB01FFA8BFB238D13 +:1007200003F00F039D42FAD1638D9B04FCD5D8459D +:10073000474628BF5F4697B14FF00C0909FB05F902 +:1007400006EB09035B7A56F809A013F0010F514636 +:100750003B46204604F1180214D0FFF71CFF5F450A +:100760003CBF4FF40043638500232385208D10F0A8 +:100770000F00FBD10C2303FB0566A8EB0708A6F8C6 +:100780000680C0E7BA44FFF755FD46F809A0E6E742 +:10079000208B0020074B1B78834206D9064B00EBC9 +:1007A00040001B6803EBC000704714BF00200348E3 +:1007B000704700BF188A0020148A0020E82E00002D +:1007C000CB6802490B610121184700BFF489002062 +:1007D0000346034A10780BB1FFF744BDFFF758BD3D +:1007E000980500200222024B5A8000221A7170479D +:1007F000248800200022024B1A80FFF7F3BF00BFBD +:10080000248800200020FFF7F5BFFFFF8B7970B52B +:10081000012B35D1CB79022B32D1002318468D78AC +:100820008C79012C20D04B78212B22D1154B8A7842 +:100830001A70B1F80530402B06D94FF0E023D3F8F9 +:10084000F03DDB0700D500BE093080B219E08C789E +:10085000AC420ED1CE78DCB2A6420AD10C7801337C +:10086000204480B22144DBE7CC79022CDBD19042DA +:10087000EDD34FF0E023D3F8F03DDA0700D500BE0A +:10088000002070BD24880020704710B501F10804D5 +:1008900000F00F02D3B2092A8CBF3733303304F88B +:1008A000013D8C424FEA1010F2D110BD08B501464F +:1008B000FFF740FEBFF35F8F012201F01F039A4054 +:1008C0004B099B0003F1604303F56143C3F88021AA +:1008D0001A6008BD01220649430900F01F0082404A +:1008E000203341F82320BFF34F8FBFF36F8F704742 +:1008F00000E100E010B4090100F16044C9B204F560 +:10090000614484F80013034941F820205DF8044B4A +:10091000FFF7CCBFA006002037B5C36B04460A46DC +:100920006D468BB193E8030085E803001A70226CD2 +:1009300018465A60A26B9047E36B1BB195E8030021 +:1009400083E8030003B030BD2B46EFE737B5836B78 +:1009500004460A466D468BB193E8030085E8030020 +:10096000E16B1A7119601846626B9047A36B1BB15B +:1009700095E8030083E8030003B030BD2B46EFE7A2 +:1009800010B5FFF7D1FDFFF7D5FDFFF7CDFD3A4BD1 +:1009900053F820301A69117BC1F30000C9074FD406 +:1009A00093F82C1093F82A408C4215D093F82D0020 +:1009B00020B1022902D15223D3720CE093F82810FF +:1009C000D17093F82B20013A83F82B2093F82C2038 +:1009D000013283F82C2010BD196A41B393F82D40E1 +:1009E0004CB95A6A98690139805C013219625A62BD +:1009F0001B69D870EFE793F831406CB1012983F897 +:100A0000310004D120211A699172FF20F0E7907221 +:100A10001A6A012AF9D1F5E7507999695A6A885416 +:100A20001A6A013A1A625A6A01325A62F0E793F876 +:100A30002E1081B15221D172012283F83020CAE7F1 +:100A400093F82D1011B193F8311031B100211962D2 +:100A5000012183F82F105423AEE7507999695A6A1F +:100A600088541A6A93F82E10013A1A625A6A0132AF +:100A70005A621A69DDE700BFA006002010B5FFF733 +:100A800053FD2D4B53F820000269D37A6FF3C30353 +:100A9000D37290F82F2002F0FF0332B1F02201212F +:100AA0000369DA72FFF752FF1BE090F82A1090F802 +:100AB0002C20914229D0D2B901290CBF90F82830BE +:100AC00090F8293000210269D1720269D37090F840 +:100AD0002B30013B80F82B3090F82C30013380F81C +:100AE0002C30FFF721FDBDE81040FFF723BD90F843 +:100AF0002D1001F0FF0431B1022AE3D190F8293022 +:100B000043F00103DEE72346DCE7026A002AE8D16E +:100B100090F82D1090F83040C1F103010369C9B27B +:100B20000CB1DA72BEE7F022DA720269937803F050 +:100B3000CF039370B6E700BFA00600200022084B49 +:100B40001A719A78042A02D103229A707047072AF0 +:100B5000FCD11A7812F0040F0CBF08220622F4E729 +:100B60002488002008B50378012B06D103490B889F +:100B70001BB1FFF7E3FF00230B8008BD2088002096 +:100B8000030143EA801040F4847040F00100704794 +:100B9000002802DB014AFFF7ADBE7047F88A00204B +:100BA0002DE9F047404B414E1F7806EBD013154618 +:100BB00093F827208046D20789464FEAD01A08D5F5 +:100BC0004FF0E023D3F8F03DDB0700D500BE002056 +:100BD00055E093F82720384642F0010283F8272099 +:100BE000334B53F83740FFF753FB0CB900BEFEE719 +:100BF000B8F1000F2CD04FF484632384238C9B0620 +:100C0000FCD52C4B5A7A9D806FF300025A72DD801E +:100C1000002D40D0C3F80090B4F86030180430D4F0 +:100C20004FF0E023D3F8F03DDA0732D43846FFF72F +:100C300019FB06EB0A0393F827206FF3000283F8F1 +:100C4000272093F827206FF3820283F82720B7E745 +:100C5000A4F82080238C13F02002FBD1154B597A85 +:100C60009D8062F300015972DD80A5B1C3F8009048 +:100C700001233846A4F86030FFF7F4FA0120BDE8FC +:100C8000F087B4F854301906CAD52046FFF7E0FCC7 +:100C9000EEE700BECAE70022064B1A705A709A703F +:100CA000DA700523E5E700BF98050020208A0020C0 +:100CB00018300000208B002030B51A4DAB686D68ED +:100CC0009C6E2D78032D06D8013490B1844210D942 +:100CD0000138086024E008B18442FAD85B6BD5077C +:100CE00054BF03F01F03C3F304431B0983F0010344 +:100CF0000BE05B6BD20754BF03F01F03C3F3044345 +:100D000003F00C031A1F5342534118B933B12CB1ED +:100D1000032304E0A042FBD3002BF9D002234B6055 +:100D200030BD00BFF88A00202DE9F34101F0030730 +:100D3000032F80460D4607D02F4B01F00C015A6857 +:100D40001278062A03D129B902B0BDE8F08109B1B1 +:100D5000032AF9D11968294A9142F5D19E68736E28 +:100D600001334345F0D34FF0FF3400232A46694650 +:100D70004046CDE90043FFF79FFF019A346B92B9DB +:100D800015F0080F0CBF02230423A80758BFDB1976 +:100D9000009955BF123306EB830306EB8303D96436 +:100DA00054BF596019656B060BD5336C012F43F4A2 +:100DB0008003336411D1019B24F0407444EA03643E +:100DC00011E0012F11D1022DF5D1002AF3D001221B +:100DD00069464046FFF770FFEDE724F4403444EAEB +:100DE0000244002FE7D13463AEE724F44034022DEF +:100DF00044EA0244E9D0F4E7F88A0020545047005E +:100E0000C043002200F080001146FFF7C9BEFFFF7B +:100E100010B40346064C00682246596803C20022FB +:100E2000C4E9022218785DF8044BFFF7E9BF00BF60 +:100E3000F4890020F8B5038944899BB2A4B2054621 +:100E40008088A34236BFC4EB400EA3EB040E9E4441 +:100E50001FFA8EFE704516461ED80027BC463B463C +:100E60003A46B24228BF32460CEB020084452AD1F2 +:100E7000B61AB6B23EB1B34228BF3346F81887421D +:100E800025D113449AB22989A88889B2FFF777FB44 +:100E90002881F8BD1B1A9BB29842FBD9A0420FD9FA +:100EA0002F68A34207EB030C35BF0027C01AE41AD2 +:100EB000A3EB0E0339BF3B46A2B282B29BB2D0E78E +:100EC000241AA4B2EAE70C780CF8014BCEE70C78B0 +:100ED00007F8014BD3E7FFFF70B505460024134E1A +:100EE000E0B2FFF757FC38B94FF0E023D3F8F03DFC +:100EF000DB0700D500BE70BD436828469847013423 +:100F00003278E3B29A42EBD23B220021084801F04A +:100F100023FE1022FF21074801F01EFEBDE87040AD +:100F20001422FF21044801F017BE00BF188A0020D8 +:100F3000208A0020238A0020338A002070B505898A +:100F4000038942899BB292B28688934236BFC2EB34 +:100F500046029B1A9B189BB29E420446ADB217D81C +:100F6000C079C00914D170BD801B80B2B042FBD2E1 +:100F7000E2882368C2F30E0202FB003001F040FE5B +:100F800001222946A088FFF7FAFA20810120EAE72A +:100F90002846EBE77FB543780446023B032B12D883 +:100FA000DFE803F00226151D00212C4B1A786FF3A1 +:100FB00000021A701A786FF341021A7059701A7889 +:100FC00061F382021A70264B2146186838E0234BE1 +:100FD0001A78D5073FD51A7842F00402F2E71F4A83 +:100FE0001378D80737D513786FF382031370EAE7C5 +:100FF00000251C4EE8B2FFF7CDFB20B1436913B1C9 +:1010000061682078984732780135EBB29A42F1D284 +:10101000124A137859071ED5137801A96FF382037A +:1010200013700023CDF80630CDF80A30ADF80E303D +:1010300023788DF8043005238DF80530084B1868A7 +:101040000430FFF77BFF30B94FF0E023D3F8F03DD9 +:10105000DB0700D500BE04B070BD00BF208A0020B1 +:101060001C8A0020188A002010B5114B9989DA8952 +:1010700093F900008C1AA4B2402C28BF4024002809 +:101080000DDA914211D0224699680A4801F0B8FD64 +:10109000802008492246BDE81040FFF781BD9142FB +:1010A0004FF00000F5D10146F4E780200021F1E780 +:1010B000F48900207088002070B50346124D006846 +:1010C0002E460C465968AC6003C60021E981D988D8 +:1010D0008A4228BF0A46AA81D98881B14AB144B957 +:1010E0004FF0E023D3F8F03DDB0700D500BE002031 +:1010F00004E0FFF7B9FF0028F2D0012070BD187896 +:10110000FFF77EFEF7E700BFF489002007B58DF8F2 +:1011100000208DF801301A0A1B0C8DF803300023D3 +:101120008DF802208DF80410062269468DF80530EE +:10113000FFF7C2FF03B05DF804FBFFFF2DE9F04F9E +:1011400089B0FFF7F1F9FFF7F5F9B24BB3F84010AA +:10115000CA4362F478428CB292B20904A3F84020E8 +:101160000CD5B3F8402012F0800FC2F3C0111A88DA +:1011700014BF42F0100261F304121A80620413D506 +:101180000025052305A88DF81530CDF81650CDF8AB +:101190001A50ADF81E508DF81450FFF7FBFE9D4B12 +:1011A0001A8E65F34D321A86A30416D5994E338EE6 +:1011B0009F0412D50025032305A88DF81530CDF81E +:1011C0001650CDF81A50ADF81E508DF81450FFF798 +:1011D000E1FE338E65F34D333386E60407D504F024 +:1011E0007003202B00F0E48061D8102B7DD0200507 +:1011F00032D5E10740F1FC80864BB3F8402012075E +:101200002AD54FF480425A84B3F8542003A9ADF88C +:101210000C20B3F8562006A8ADF80E20B3F85820DD +:10122000ADF81020B3F85A20ADF812204FF6F7723F +:10123000A3F840200023CDF81630CDF81A30ADF8D1 +:101240001E308DF81430062308228DF8153001F079 +:10125000D7FC05A8FFF79EFE670515D500226D484F +:10126000B0F84A30A0F84A20DE070DD5FFF7F0F9B4 +:1012700050B14FF4E0658022674B05A89B88CDE90B +:1012800005520793FFF786FEE4050DD5614D624CCC +:10129000EB8EB5F84670BFB21F40FB439BB2A5F87A +:1012A0004630002F40F0C08009B0BDE8F08F602BC1 +:1012B00004D018D804F06003402B98D10023CDF857 +:1012C0001630CDF81A30ADF81E308DF814300423E6 +:1012D00005A88DF81530FFF75DFE4E4A138E43F4D6 +:1012E0000053138683E7702BE7E70122494B5A87A7 +:1012F000DA864FF480425A8400221A851A8D12F041 +:101300000F02FBD19A859A8D12F00F02FBD10123B7 +:1013100094464FF400774FF48076404D40493D4865 +:101320001FFA83FEA0F864E0A0F868C021F81370EB +:1013300021F8132025F823600133062BF0D1002576 +:101340004FF400722846334E9FB2A6F86470A6F898 +:10135000680021F8132021F8135001330A2BF3D130 +:10136000982200212C4801F0F7FB338903F0070392 +:10137000013B9BB2022B12D82A4ACDF81650D35CFF +:101380000122CDF81A50ADF81E508DF814508DF88A +:1013900015208DF8183005A8FFF7FCFD27E74FF062 +:1013A000E023D3F8F03DDD077FF521AF00BE1EE757 +:1013B000184BB3F8503013F07F033FF418AFADF87B +:1013C0000E3000234FF4A0620493CDF81630CDF810 +:1013D0001A30ADF81E308DF814300623ADF80C200D +:1013E00003A9082206A88DF8153001F009FCD2E700 +:1013F00014F007027FF430AF4FF4E061054B1B8C13 +:10140000CDE90512C3F34013DB018DF818300792C4 +:101410001FE700BF00000940208B00208C0009401E +:101420006E000940002F000097FAA7F60C23B6FAC9 +:1014300086F603FB06431A7AD2091BD031462846AA +:10144000FFF73CF988B10C2303FB06439A88197A0D +:10145000DB884FF4E060D31A0022CDE9050205A82D +:101460008DF818100793FFF795FD0123B34027EA85 +:10147000030716E7002E57D0B3F806B0B3B22B859A +:10148000A5F86430B5F86CA01FFA8AFA2B8D03F02A +:101490000F039E42FAD16B8D9804FCD5B5F82A80D3 +:1014A0000C23C8F30B08D04528BFD046C345D94606 +:1014B00028BFC1467343E058E218B9F1000F08D0C5 +:1014C000537AD90721D54A4634490190FFF7B2FC37 +:1014D0000198CA4584BF4FF480436B8500232B8558 +:1014E0002B8D1A07FCD10C2303FB0642ABEB090141 +:1014F000CA45D18001D8C345B7D800227343E1184B +:10150000E2544A708A70CA709CE70346DFF894C0C0 +:1015100000EB09029CF8181003F8011B9342F9D163 +:101520000C227243A350D4E7B5F85EA0B5F8228030 +:101530000AF07F0AC8F30B08D04528BFD046B4F89C +:1015400006B0C146D84528BFD946B9F1000F07D02B +:10155000637A2068DB0712D54A461149FFF76AFC17 +:10156000ABEB0903CA459BB213D8D845E380FFF41F +:101570007CAF002323706370A370E37063E70949B5 +:1015800000EB09030A7D00F8012B9842FAD1206094 +:10159000E6E74FF480426A84E380EAE718000940F6 +:1015A0001400094000000940FFF7C8BD2DE9F04FC5 +:1015B000B44C87B0B44B00201E6833689847B38999 +:1015C000F1899BB289B230898B4236BFC1EB4002B0 +:1015D0005A1AD21895B29DB1A84205D283422CBFA7 +:1015E0001B1A1B1899B2F181884226D97289736837 +:1015F000C2F30E0202FB013103A801F001FB012539 +:10160000F1892A46308989B2FEF7B9FF3368F08143 +:1016100001209847002D00F08C839DF80D30013B90 +:10162000072B00F23283DFE813F00B0018003003C1 +:101630008F038F0322000F039103091A89B2D3E7A6 +:101640009DF80C00FFF748FC142200218F4801F0A0 +:1016500083FA9DF81030A370ACE79DF80C00FFF7FB +:101660003BFC14220021894801F076FAA2E7237896 +:101670009DF8107043F00103237094F82730DFF8D1 +:101680000C826FF3000384F8273094F8273007F0BA +:1016900060016FF3820384F8273094F828306029C2 +:1016A0006FF3000384F8283094F828309DF80C502C +:1016B0006FF3820384F828304FF00003C8F810302D +:1016C00011D14FF0E023D3F8F03DD90700D500BE8B +:1016D00000219DF80C00FEF7F5FD80219DF80C001F +:1016E000FEF7F0FD66E740290DD1694B002BEFD0E6 +:1016F0000121284604AAC8F81030AFF30080002862 +:101700007FF458AFE4E707F01F07012F00F0C68110 +:10171000022F00F0EA81002FD3D120290FD19DF8AC +:1017200014300F2BD4D82344D878FFF733F8014670 +:101730000028CDD004AA2846FFF742F8DFE70029A9 +:10174000BFD19DF81120092ABBD801A151F822F080 +:10175000871A0000751A0000C3160000611A000005 +:10176000C31600007917000039190000C3160000E5 +:1017700093170000A71700000023C8E9023323785D +:1017800006AA43F0020312E903002370C8E900012E +:1017900010E7637801228DF80A300DF10A0104A8E0 +:1017A000FFF78AFC06E79DF812B063789B4500F0CE +:1017B000A6806378002B3ED02846FEF769FD0926F7 +:1017C0004FF00C0E4FF001094FF0000C314F0EFBA3 +:1017D00006731B7A33B3304A03F07F08DB0952F8F3 +:1017E0003520190107EB0313434493F87830D08E6A +:1017F00009FA03FA80B220EA0A00D086002B3CD016 +:1018000003F1370002EB4000A0F800C0A2F86430FA +:101810000EFB037339444144A2F868C083F808C042 +:1018200081F878C0013ED2D12846FEF71BFDA6788C +:10183000FFF752FBA670BBF1000F60D02378DFF8F2 +:101840005C9023F03003237099F801300B2B02BF1A +:1018500099F8003099F803A0994499F8013018BF1D +:101860004FF0010A042B1BD04FF0E023D3F8F03DDA +:10187000D9077FF526AF00BE23E702F16000C3E77A +:101880008146E1E7208A00201C8A0020F48900209C +:1018900000000000208B002018300000B92E00004E +:1018A0000027B84BA3EB09081FFA88F8FEB23046B0 +:1018B000FEF770FF0028D7D0836842464946284685 +:1018C0009847082831D980452FD3002209E099F89C +:1018D000027001323B4454FA83F3DF78FF2FC3D107 +:1018E000DE70D3B29A45F2D8A74F484448450CD889 +:1018F000A64B1B78B342B7D3A24B9842C0D384F80F +:1019000001B004A8FFF784FA54E699F80130052BDA +:1019100007D199F8023003F07F0207EB4202DB099E +:10192000D65499F800309944E0E7984B01371A787B +:10193000FBB29A42BAD297E7BDF812301A0AD8B26F +:10194000531E0E2B3FF6C4AE01A151F823F000BF89 +:101950008D190000AF190000C7190000D116000052 +:10196000D1160000491A0000AF190000D11600007E +:10197000D1160000D1160000D1160000D1160000CB +:10198000D1160000D11600009919000012228049DA +:1019900004A8FFF791FBB2E67E4B002B3FF498AE14 +:1019A000AFF30080014600283FF48BAE02E0022A2C +:1019B00002D179494A88EBE7784B002B3FF488AE97 +:1019C000AFF30080EEE770B902227549754801F067 +:1019D00017F901204000821C734942F440730B80C8 +:1019E00002F0FE02D4E705283FF672AE6F4B704D51 +:1019F00053F820702B78BBB96E4E2946D6F890006C +:101A0000FEF743FFD6F8940005F10801FEF73DFF0D +:101A1000D6F8980005F11001FEF737FFD6F89C00C4 +:101A200005F11801FEF731FF384601F05FF9002299 +:101A30005D49C0B2D3B2984202F10102CAD95D1C1D +:101A4000FB5C21F81530F5E75B4B002B3FF440AE13 +:101A5000AFF30080014600283FF43AAE027897E7E2 +:101A6000BDF81230012B7FF433AE237843F0080326 +:101A7000237046E7BDF81230012B7FF429AE23789E +:101A80006FF3C303F4E72378C3F340129B0803F01A +:101A9000020313430222ADF80A307EE69DF81430AB +:101AA0000F2B3FF615AE2344D878FEF773FE0146A0 +:101AB00000283FF40DAE284604AAFEF781FE002858 +:101AC0007FF478AD9DF8103013F060037FF400AE22 +:101AD0009DF81120A2F10A0101293FF6F9AD0A2A69 +:101AE000C8F810307FF40DAF54E69DF814B00BF039 +:101AF0007F02092A3FF6E5AD560004EB420202EBF5 +:101B0000DB12D07CFEF746FE4FEADB1A814629B194 +:101B100000283FF4DDAD014604AA0CE69DF8113023 +:101B200003F0FD01012907D0002B7FF4CAAD92F824 +:101B30002730C3F34003ADE7BDF8121000295ED192 +:101B40001E49012B02F120020F78D37969D19A073F +:101B500055D559463846FEF753FB0190002840D032 +:101B6000174A384652F837200092FEF791FB4FF49F +:101B70008071019B009A1980BAF1000F22D00122D6 +:101B80001A802BE0D42E0000338A0020188A00200F +:101B9000D42E000000000000B02E00000000000065 +:101BA000CE2D0000F4880020F2880020982E00003E +:101BB000B08800200081000100000000980500208E +:101BC000183000006549594491F87810A2F8641063 +:101BD000B2F86820C2F38132012AD0D13846FEF72C +:101BE00041FB2644564496F827306FF3410386F8AC +:101BF000273096F827306FF3000386F82730B9F1C5 +:101C0000000F3FF4D7AC4946284604AAFEF7D8FD9A +:101C10000023C8F8103094F82830D8073FF5CAAC34 +:101C20006FE69B07EBD42644564459463846FEF7E8 +:101C300049FB96F8273043F0020386F8273096F8E0 +:101C4000273043F00103D8E79DF8101001F07F051D +:101C500004EB450303EBD11393F827004FEAD11CA3 +:101C60006FF3000083F8270093F827006FF38200DA +:101C700083F82700002D51D1394D9DF80C602B7849 +:101C8000059FBCEBD31F18D047B14FF0E023D3F82A +:101C9000F03DDB077FF58EAC00BE8BE4314B1BB112 +:101CA00029463046AFF300802B69002B3FF482AC0D +:101CB000032130462A4A98477CE495F90030A86809 +:101CC000002B06DB00283FF475AC3A46264900F0AD +:101CD00097FFAA68EB893A443B44AA60EA889BB222 +:101CE0009A42EB8101D03F2F15D82B6933B9287860 +:101CF000FFF786F800287FF45DACC6E70221304686 +:101D0000174A984701460028F1D13046FEF7DAFA23 +:101D100080213046E4E4FFF7A7F9EBE7D87CFEF733 +:101D200039FD48B94FF0E023D3F8F03DDA0700D58C +:101D300000BE07B0BDE8F08F0569059B9DF8112036 +:101D40009DF80C00A84735E4237833E4049B002B6E +:101D50003FF430AC059898472CE400BF208B00205E +:101D6000F4890020000000007088002008B50D4CA8 +:101D70000D4E2568327823685B1B632B0CD9BFF3AB +:101D80004F8F0A490A4BCA6802F4E0621343CB60E2 +:101D9000BFF34F8F00BFFDE7FF2AECD0FFF706FC33 +:101DA000E8E700BF648A00209805002000ED00E00D +:101DB0000400FA05A0F101000028FBD17047FFFFE5 +:101DC0004FF47A734843A0FB0303064B1A68064B93 +:101DD000B3FBF2F3B0FBF3F0800801D0FFF7EABFEA +:101DE000704700BFA88A002000CA9A3B73B5404BD9 +:101DF000404A1E7B404BDC68944253D11A6A002A49 +:101E000043D193F8304004F0FF05002C45D108225F +:101E10001E725A608DF804008DF8051083F82E505C +:101E20005A6B002A45D001AA9A610222197ADA6116 +:101E3000012908D1002283F829205A6883F82A1042 +:101E4000520083F828200022022183F82D2083F8F5 +:101E50002F2083F8312083F8332083F82C205A6216 +:101E6000196293F82D2093F82A1083F82B1012B1E1 +:101E7000012283F83120B4211A69917093F830203F +:101E8000F2B951221B69DA7213E000228DF80400C6 +:101E90008DF8051083F82E20C2E78DF804008DF828 +:101EA0000510F7E700228DF804008DF8051083F87F +:101EB0002E204FF47A710520FFF782FF02B070BD2B +:101EC000002283F8302093F82A201969012A0CBFD8 +:101ED00093F8282093F82920CA7093F82B20013A10 +:101EE00083F82B2093F82C20013283F82C20E0E794 +:101EF0009C05002043324953688A002070B5FEF7E4 +:101F000013FB1349134B0A7C53F820600546100756 +:101F1000D1F88010D3B214D41A0614D4DB0614D529 +:101F200011F4405F0CBF06240724304600F018FF70 +:101F30002846FEF7FFFA21463046BDE87040FEF71E +:101F4000EBBC0424F1E70524EFE70724EDE700BF2D +:101F500000E07F40A006002038B5FEF7E5FA1A4BF6 +:101F600053F82040FEF7E6FA94F83450012D0CD1D6 +:101F7000236BE3B100220421204600F0E5FE08B304 +:101F80002046BDE8384000F0EBBE022D08D1256B9D +:101F90006DB12046BDE838400022402100F0E4BE8B +:101FA0000A4B93F8D430012B14BF0225032500F00F +:101FB000CFFE002384F8343029462046BDE838405F +:101FC000FEF7AABC38BD00BFA006002000E07F409D +:101FD000094B0A481A880A4B03EA8213094A03F597 +:101FE0008033128852080263074AC0E90A2300239B +:101FF00080F8343000F0C0BE22880020B48A00206F +:102000000080FFFF208800202008002070B5137892 +:10201000144603F01F02012A0D4640F00A8113F016 +:10202000600019D163780A2B0DD00B2B27D1012921 +:1020300024D16288804B5A70FEF7D4FB2046BDE85D +:102040007040FEF7E5BE012918D10A467B492046BB +:10205000BDE87040FFF730B8202840F0EA80637890 +:10206000062B00F2E680DFE803F004321C520F1466 +:102070000F00012904D12046FEF7CAFE012070BDE1 +:102080000329FBD1FFF772FE0129F7D1FEF7AAFB66 +:10209000F1E70129F2D10A4620466949FFF70CF819 +:1020A000ECE70129EAD1644E337813F00200E6D060 +:1020B000E588402D00F2BD8061882A46694306F11B +:1020C0000C0000F09DFD2A4606F10C01BFE7012936 +:1020D000D4D159490B7813F00100D0D08B78022B62 +:1020E00002D0052B40F0A580E388402B00F2A180B0 +:1020F00001230B716388CB80E3880B81E2881AB1DE +:1021000003238B704F49A2E706238B7096E74A4A58 +:102110009178032905D0062956D0012DAED1002390 +:1021200009E0012D0BD113793BB153780421002B29 +:1021300014BF64230023D27851E00521FBE7032D6F +:102140009CD11379002B3CD0042314899370D3883D +:102150003D4A138047F6C07203F5806312EA83128A +:102160004FEA831115D172B6384B384883F83420C2 +:1021700021F40013B3F5803FB8BF21F4FF514FF0B5 +:102180000102B4BF21F01F0101F4FF0100F0F0FDD6 +:1021900062B62F4D2F482B8822461844294900F05B +:1021A0002FFD2B881C44A4B2B4F5004F2C8005D120 +:1021B00072B6FFF70DFF62B600232B80FEF7BEFC60 +:1021C0005CE70523937059E7012D0DD11379D2787F +:1021D000002B18BF07214FF0000308BF0221204643 +:1021E000BDE87040FEF792BF032D7FF447AF13792F +:1021F000EBB10723937072B6FFF7EAFE62B60026D2 +:10220000124CFEF79BFC6368266093F91100B04204 +:1022100001DBFEF75FFB104D2E76636893F9130028 +:10222000002801DBFEF756FB00232B7526E702236F +:10223000C8E7002023E700BF24880020258800206D +:10224000268800203088002022880020B48A0020C0 +:10225000208800202008002000E07F408FB54FF448 +:102260007002C34BC34DC3F888209D604AF20353EC +:10227000C14CC24FA4F8FE33FEF73CF8C04BC14A34 +:10228000C149C3E900724FF40042DFF868C3C3E9F3 +:1022900002211A61BD4AC3E905C2FEF73FF80023D7 +:1022A00084F81334092384F8A23094F8803433B9C5 +:1022B000012140F2C44084F88014FFF781FD00231F +:1022C000AD4884F8813484F8803484F8323090F852 +:1022D0003C301E07FBD542F2017343F20212A0F814 +:1022E0004830002380F84A30028580F82A3090F880 +:1022F0003C309C06FBD50322A54B83F81C21A54B43 +:102300000362052380F82630FEF708F8012380F8E1 +:10231000303080F8523090F8743043F0400380F849 +:102320007430954B93F87420D209FBD006224621D5 +:1023300083F86C2083F8741083F8742093F8742069 +:10234000D209FBD193F8772042F0400283F877203E +:10235000894B93F87720D209FBD0022283F86F20B3 +:10236000C62283F8772093F8772002F0BF0283F823 +:102370007720814B93F87770FF09FBD14FF425420A +:10238000A3F8FE232B68A3F5805383F30A888248C1 +:10239000824A3946121A00F0DFFB8148814A82499D +:1023A000121A00F02DFC3E46804D814C641BA41097 +:1023B000B44200F3478200257E4CFDF7AFFFC820F2 +:1023C000012184F82850FFF7FBFC84F8245094F88E +:1023D0002430002BFBD194F82430764A43F00203DA +:1023E00084F8243092F824309807C3F34005F9D4D8 +:1023F00082F822500120FDF7DBFF5F4B83F8BB54CE +:10240000FDF7AAFF0320FDF7D3FF2B464FF6FF7021 +:10241000694A03F108010133092B22F81100F8D1B0 +:102420000320FDF799FF0320FDF7C2FF6FF0FF02C5 +:10243000624B634C9A64FF210C2201A800F08CFBD4 +:1024400025460023012635F8022B6AB104A95A0952 +:1024500001EB820252F80C1C03F01F0006FA00F098 +:1024600021EA000142F80C1C0133602BEBD10199E9 +:10247000524A544B1167C3F88012029903205167E6 +:10248000C3F8841203999167C3F88812FDF764FFBB +:1024900000234D4A03F1C00134F8020B0133602BD5 +:1024A00042F82100F6D162B6484CDFF84C9123681F +:1024B0004B4504D04648C4F80090FDF7A1FF4FF407 +:1024C0007A72DFF83881D8F80030B3FBF2F3013BC1 +:1024D000B3F1807F0AD24FF0E022F0215361244B08 +:1024E00083F82310002393610723136123684B456E +:1024F00002BF4FF48002374B9A621F4B364AD3F823 +:102500000015914240F0CE814AF20252A3F8FE2318 +:102510000022C3F800254FF42542A3F8FE232F4BD9 +:102520001A684A4504D02E48C3F80090FDF768FFAA +:102530002C4EDFF8CC9033684B4500F0AF804FF461 +:102540008073F360284B002573600123274A33749E +:10255000B2607561C6E90655EFF3108183F3108808 +:10256000234B1A6922F400021A611B694AE000BF7A +:1025700000ED00E00000000000E00140002D31010E +:10258000C405002000127A0000366E01001C4E0EB9 +:1025900000C0014021120120E0050020B88B00207E +:1025A00000000020C40500205C300000C4050020AD +:1025B000C405002000300840000D084000800040A5 +:1025C000122F000000E100E000600040AC8A002013 +:1025D000D42F00000000084035817307188B0020BD +:1025E00010300000F88A0020F02F000000981640FC +:1025F0000040084000C2EB0B54524F50A88A002004 +:102600005450470081F310884FF42542B36844F6D4 +:102610004B401A604FF40003B4682A46E562E56354 +:10262000A564E3624FF0004323616361A36149F64F +:1026300095036562A562E5612562A36663664FF056 +:10264000FF3301A9CDE90135FEF736FB019B284692 +:102650006365A365029BFF211A0642EA0342FEF767 +:102660008FFA4FF4AA03A563C4F888502364F36873 +:102670000004E36042F0030342F00102606323635D +:1026800028462263FEF784FA29462846FEF780FA98 +:1026900029462846FEF77CFAC6F8009044F61F63E8 +:1026A00044F6206271680878032898BF1A46B36818 +:1026B0009A66097819B942F20F7159659965D96A14 +:1026C000CC0705D45A664FF4AA021A64F268DA609D +:1026D00001210020FEF728FB33685D494B4504BF0C +:1026E000D6E902325A605B4B5B484B6000230376AD +:1026F000037581F834300123584D85F816342C6A5F +:10270000D8F80030C4F3026203FA02F2C4F3027490 +:10271000E2402C6AC4F30264A340E340504CA2425E +:102720003ED9504C02F5742202F23F22B2FBF4F281 +:1027300003F5742302F5F05292B203F23F23A0F89E +:10274000E420B3FBF4F343F6B85006225843B0FB41 +:10275000F2F0886040F6D8605843B0FBF2F0C860F1 +:102760005800B0FBF2F0086154205843B0FBF2F07F +:1027700048613D485843B0FBF2F0886144F2506034 +:102780005843B0FBF2F0486238485843B0FBF2F0CF +:10279000086237484343B3FBF2F3CB61354B0B6020 +:1027A0002B48354D00F0DCFA01220221284800F0C8 +:1027B000D3FA2B78FF2B1FD13B2200212F4800F0AA +:1027C000CBF900222E4BDA819A812E4A13602E4BD0 +:1027D00023B12E48AFF300802D4B18602B4CF8B27C +:1027E000FDF7D8FF002840F04A814FF0E023D3F8EE +:1027F000F03DD80700D500BE264F274EDFF8A08059 +:102800002B78FF2B01D0FEF7D1FE3A683368D21A3D +:10281000632AF5D9D8F8004064330121204633609B +:10282000FEF782FA1D4B1A78002A00F07581B4F584 +:10283000FA6F80F06C8100221A704FF4FA63C8F8C6 +:102840000030DDE755F8043B98470136B0E500BF9E +:10285000B48A0020DC2F000000E07F4000E001404F +:10286000FF083D0040420F0038AF040080DE0F003B +:10287000A0F703004E45504F98050020208A002005 +:10288000880500201C8A002000000000188A002013 +:10289000148A0020648A0020608A00205B8A00205D +:1028A0005C8A002093F81014C90709D44AF2025137 +:1028B000A3F8FE13C3F800254FF42542A3F8FE2326 +:1028C0009C4D6A6A002A00F08A806B689A498B42A4 +:1028D00003D09A498B4240F08280EB7B297C0B43EA +:1028E0001B067CD4964CDFF86CA2E368534576D087 +:1028F0002B781F2B73D840F2FF31D940CE076ED50D +:10290000117819B192F90320002A68DA002603F53C +:10291000800303F58C531B022361AB682560636061 +:102920002B7BA6632372EB6963632B6AE363EFF38C +:102930001080012383F310884FF00041814B95F8FC +:1029400000C05A6821FA0CF122EA01025A605B6861 +:1029500080F31088F0222368596A23699E702369E6 +:10296000DA728B78226903F003031370FA22236969 +:102970009A714A7823695A700B7822699B0043F058 +:102980002003DBB2D3714A7923691A72CA782369AA +:102990009A740B792269DB0043F00103DBB25372B6 +:1029A000232223699A722369654A5E73697B95F9CC +:1029B0000F00FDF79FFF624A697B95F91000FDF754 +:1029C00099FFC4E90666C4E9086684F82D60C4F876 +:1029D0000CA084F82E6084F82F6084F83060802189 +:1029E0009C20FFF703FA20219E20FFF7FFF9564AAB +:1029F0001368B3F5FA7FFBD34AF2025400204FF478 +:102A000025454FF48031514AA2F8FE43C2F8000533 +:102A1000A2F8FE530B6803F07F43B3F1005F7FF42D +:102A20007EADA2F8FE43EFF3108C012686F31088EA +:102A3000444B5C6844F400645C605C688CF3108810 +:102A4000EFF3108C86F310885C6844F480545C606B +:102A50005B688CF31088A2F8FE5380F30A8872B684 +:102A6000BFF34F8FBFF36F8F4FF0E0231861C3F8B0 +:102A7000081D0B6883F308884B6898474FE5036887 +:102A8000984701372278FBB29A42BFF4A8AE0023E0 +:102A90002C4A2B70536823F4006353602C4B1A8824 +:102AA00042F480621A801A885105FCD51A884021A8 +:102AB0006FF345121A801A8800206FF386121A806D +:102AC0001A8842F001021A800522C3F8F020D3F8D8 +:102AD00000246FF30412C3F80024B3F85E2061F3FE +:102AE0000602A3F85E200022A3F840204FF45D42C6 +:102AF0001A8601225A87DA86B3F84020120642BFAE +:102B00001A8842F010021A80FDF7ACFB74E6A4F5B7 +:102B1000FA64C8F8004073E644F61F6204F5FA64EC +:102B20009442C8F800407FF66BAE01221A7044F65A +:102B3000206384E69C050020A0860100801A060020 +:102B4000688A002000400840648A002000E00140BC +:102B5000000009404332495370B586074AD0541EDD +:102B6000002A41D0CAB2034601E0013C3CD303F83D +:102B7000012B9D07F9D1032C2FD9CDB20F2C05EBDA +:102B8000052505EB054538D9A4F1100C03F1100E0D +:102B90001A462CF00F064FEA1C1CB6441560103282 +:102BA00042F80C5C42F8085C42F8045C7245F5D1CE +:102BB0000CF1010214F00C0F04F00F0C03EB0212E5 +:102BC00013D0ACF1040323F003030433134442F89D +:102BD000045B9A42FBD10CF003042CB1C9B21C4433 +:102BE00003F8011B9C42FBD170BD64461346002CC8 +:102BF000F4D1F9E703461446BDE71A46A446E0E7D8 +:102C0000844641EA000313F0030349D1403A23D339 +:102C10000B6803604B6843608B688360CB68C3605C +:102C20000B6903614B6943618B698361CB69C36144 +:102C30000B6A03624B6A43628B6A8362CB6AC3622C +:102C40000B6B03634B6B43638B6B8363CB6BC36314 +:102C500040304031403ADBD230320BD30B68036056 +:102C60004B6843608B688360CB68C3601030103161 +:102C7000103AF3D20C3205D351F8043B40F8043B30 +:102C8000043AF9D2043208D0D2071CBF11F8013B34 +:102C900000F8013B01D30B8803806046704700BFFA +:102CA000082A13D38B07B1D010F00303AED0C3F1C1 +:102CB0000403D21ADB071CBF11F8013B00F8013BEB +:102CC000A4D331F8023B20F8023B9FE7043AD9D362 +:102CD000013A11F8013B00F8013BF9D20B7803707F +:102CE0004B7843708B7883706046704720F0030107 +:102CF00010F00300C0F1000051F8043B00F1040C97 +:102D00004FEACC0C6FF000021CBF22FA0CF2134306 +:102D10004FF0010C4CEA0C2C4CEA0C4CA3EB0C02CF +:102D200022EA030212EACC1204BF51F8043B043039 +:102D3000F4D0C2F1000102EA0102B2FA82F2C2F159 +:102D40001F0200EBD20070475FF800F0B5010020D1 +:102D50005FF800F0010000205FF800F0E1040020BF +:102D60005FF800F0E10000205FF800F0750100203E +:102D70005FF800F0290400205FF800F099030020BC +:102D800000000504342E352E30004275696C742025 +:102D9000776974682052656E65736173204164764B +:102DA000616E63656420466C657869626C6520536A +:102DB0006F667477617265205061636B616765202F +:102DC00076657273696F6E20342E352E30000904DB +:102DD00004000000060100000000000008040000DC +:102DE000000C011307040000000C01130005000093 +:102DF000000C0113010500000000010000000000AC :102E000000000000000000000000000000000000C2 :102E100000000000000000000000000000000000B2 -:102E200000000000000000000000000000000000A2 -:102E30000000000000000000000000000000000092 -:102E40000000000000000000000000000000000082 -:102E50000000000000000000000000000000000072 -:102E60000000000000000000000000000000000062 -:102E70000000000000000000010002000800100037 -:102E80000000010000000000000000000000000041 -:102E90000000000000000000000000000000000032 -:102EA0000000000000000000000000000000000022 -:102EB000020403040404FFFF01000000942D00003D -:102EC0000200000096980000010000004B4C00003A -:102ED00008FF00000000000000000000802E00003D -:102EE0000000094000000000001011400400000034 -:102EF000192D0000AE2C0000B62C0000B48A002072 -:082F0000D42C0000F92C0000A4 -:102F08004FF42A4110B500204FF49644104AB2F805 -:102F18008430A2F884109BB2B2F8841089B241B907 -:102F2800012B0CD14DF60113A2F8443000F064FADD -:102F380010BD002C08BF4FF4FA70013CECE7802B61 -:102F4800F6D10122034B5A605A68002AFCD1EFE7F8 -:102F580000E07F40007000404FF49643B32282B0F7 -:102F680001930C4B1A700C4AD2F880301B0408D518 -:102F7800137C40F2F51013F0100F08BF002002B0C8 -:102F88007047019B1BB1019B013B0193ECE71420A7 -:102F9800F5E700BF00007E4000E07F404FF4964315 -:102FA800502282B001930C4B1A700C4AD2F8803030 -:102FB8001B0408D5137C40F2F51013F0100F08BF5E -:102FC800002002B07047019B1BB1019B013B01939C -:102FD800ECE71420F5E700BF00007E4000E07F40EA -:102FE80038B5436805461A7842B193F9110000F0E4 -:102FF800FBF96B6893F9130000F0F6F90C4BB3F882 -:1030080084309BB213B9284600F0FEF9FFF7A4FFFD -:103018000446FFF7C3FF002C08BF0446FFF770FF04 -:1030280000239C4218BF204685F8343038BD00BFC5 -:1030380000E07F4030B50D4C836A0D4D236320239B -:103048002B70D0232B70836A1944036B8162013B78 -:103058000363104612B930BD30B10138D4F880305E -:103068001B04F9D50020F6E71420F4E700E07F40C0 -:1030780000007E40F7B50446154622B9436893F927 -:10308800110000F0B1F9E820E36A214A4E08136301 -:10309800204BC1F347011870197000218E4210D1DE -:1030A800D0211970002D2CD1636893F911300122B9 -:1030B800590903F01F0302FA03F3174A42F82130B3 -:1030C80019E020690190A06A00881880D2F8800071 -:1030D80040050AD4A06A01310230A062E06A0230D9 -:1030E800E062206B01382063D8E70198471E0197FA -:1030F8000028EBD11425284603B0F0BD002DF9D0E7 -:10310800013DD2F880301B04F8D50025F3E700BF55 -:1031180000E07F4000007E4000E100E010B50E4B6B -:103128001C7CE40609D5D3F88040640402D51C7CD5 -:1031380000241C7440F2F51400E00024D3F8803019 -:103148000B4218BF144620B90CB1FFF705FF204603 -:1031580010BD0446F9E700BF00E07F40402213B5E8 -:10316800836910480193104B01631A7008221A7082 -:1031780000220E4931F8024B0132082A1C80F9D18D -:10318800D0221A70D0F880301B0402D5002002B07B -:1031980010BD019B1BB1019B013B0193F2E7142079 -:1031A800F5E700BF00E07F4000007E403A050020C0 -:1031B8006FEA415110B56FEA51514FF6FF74074B52 -:1031C80042EAC03040F4F0401C805C80D88099808E -:1031D8001C815C819C81DC8110BD00BF3A05002008 -:1031E8004FF4964307B500220193154B01461A6028 -:1031F80043681A7842B193F9110000F0F5F84B686A -:1032080093F9130000F0F0F84FF459430D4AA2F86F -:1032180044304AF60123A2F88430B2F884309BB2D5 -:10322800012B03D1002003B05DF804FB019B1BB107 -:10323800019B013B0193F0E74FF4FA70F3E700BFFD -:103248000070004000E07F4038B50546FFF7C8FF32 -:10325800044668B1204638BD6CB98021AA68284662 -:10326800FFF708FF18224FF4A041FFF757FF044665 -:103278002B6B002BF0D1FFF743FE002C08BF044650 -:10328800E8E710B50F4B0446D3F890310E4803F029 -:103298000703DB430E2220F8023BFF2100F0BCF8B5 -:1032A8002046FFF79DFF20460849FFF757FF1822E1 -:1032B8000021FFF733FF0446FFF722FE002C18BF5A -:1032C800204610BD00A000013A05002090A1000191 -:1032D80038B5816202630546FFF782FF044650B99C -:1032E8000122124BA3F8E0202B6B33B9FFF708FE3D -:1032F800002C08BF0446204638BD002CF6D1D5E97D -:103308000712AB6A284623F40013B3F5803F36BF93 -:103318000A464FF400414FF40051FFF78BFE192283 -:103328004FF4C041FFF7FAFE0446DDE700E07F40B6 -:103338002DE9F041104B0546D3F8DC600F46904666 -:10334800FFF74EFFF60F044698B94FEA5832304659 -:10335800790BFFF72DFF09492846FFF7FFFE2146A5 -:103368001822FFF7DBFE0446FFF7CAFD002C08BF52 -:1033780004462046BDE8F08100E07F4030A100010E -:10338800F8B507460D461646FFF72AFF044650B91A -:103398005EB1124B45F4CC45A3F8E850FFF7B0FDF9 -:1033A800002C08BF04462046F8BD1022FF210C4817 -:1033B80000F032F847F6FF7215F0010F4FF6FF7371 -:1033C80018BF1346064A0749D3803846FFF7C6FE9A -:1033D80021461822FFF7A2FE0446DFE700E07F40FF -:1033E8003A05002030A1000101B40248844601BC1E -:1033F800604700BF1909000001B40248844601BCB7 -:10340800604700BF0103000001B40248844601BCC4 -:10341800604700BF9509000001B40248844601BC1A -:10342800604700BFCF2B0000150800001C080020D3 -:1034380010000C0000000000FF00FFFF000000006B -:103448000000000000000000000000000300000071 -:10345800A086010000000000010C00090A0000001D -:103468000000000000000000CD0800004C0500200E -:0C34780074050020000E00FF0F01000092 +:102E20000000000000000000000001030601000097 +:102E300041726475696E6F00537061726B46756E96 +:102E4000205468696E6720506C7573205241364D6E +:102E500035204446550040436F6465466C61736895 +:102E6000202F307830303030303030302F382A3822 +:102E70004B612C36332A33324B6700404461746116 +:102E8000466C617368202F30783038303030303005 +:102E9000302F382A314B6700CE2D0000302E000035 +:102EA000382E0000B0880020562E00007B2E000037 +:102EB0000902240001010080320904000000FE0123 +:102EC00002040904000100FE010205092107E803CC +:102ED000400001011201000200000040412368038C +:102EE000000101020301FFFF05080000F5070000D3 +:102EF0000D0800000D200000000000000000000090 +:102F0000010002FF0204030404040100020008009F +:102F100010006D006E006B006C007F017D017E0172 +:102F20003100300093019401000000000000000017 +:102F30000000000000000000000000000000000091 +:102F40000000000000000000000000000000000081 +:102F50000000000000000000000000000000000071 +:102F60000000000000000000000000000000000061 +:102F70000000000000000000000000000000000051 +:102F80000000000000000000000000000000000041 +:102F90000000000000000000000000000000000031 +:102FA0000000000000000000000000000000000021 +:102FB0000000000000000000000000000000000011 +:102FC0000000000000000000000000000000000001 +:102FD0000000FFFF05000000D02D000000000000F1 +:102FE000650B00000000000000000000020702085E +:102FF0000200000096980000010000004B4C000009 +:1030000008FF00000000000000000000F82D000094 +:1030100001000000282E0000000009400000000010 +:10302000001011400400000010000000000000002B +:10303000017A5200027C0E011B0C0D0014000000EE +:1030400018000000BCFBFFFFEC00000000024D0A6E +:04305000430B00002E +:08305400ACFBFF7F010000004E +:10305C004FF42A4110B500204FF49644104AB2F8B0 +:10306C008430A2F884109BB2B2F8841089B241B9B2 +:10307C00012B0CD14DF60113A2F8443000F094FA58 +:10308C0010BD002C08BF4FF4FA70013CECE7802B0C +:10309C00F6D10122034B5A605A68002AFCD1EFE7A3 +:1030AC0000E07F40007000404FF49643B32282B0A2 +:1030BC0001930C4B1A700C4AD2F880301B0408D5C3 +:1030CC00137C40F2F51013F0100F08BF002002B073 +:1030DC007047019B1BB1019B013B0193ECE7142052 +:1030EC00F5E700BF00007E4000E07F404FF49643C0 +:1030FC00502282B001930C4B1A700C4AD2F88030DB +:10310C001B0408D5137C40F2F51013F0100F08BF08 +:10311C00002002B07047019B1BB1019B013B019346 +:10312C00ECE71420F5E700BF00007E4000E07F4094 +:10313C0073B5436805461A7842B193F9110000F053 +:10314C002FFA6B6893F9130000F02AFA1C4CB4F8B0 +:10315C0084309BB27BB1FFF7A7FF0646FFF7C6FF93 +:10316C0004463EB3FFF774FF34460023204685F82F +:10317C00343002B070BD4FF4964301936B681A78EB +:10318C0042B193F9110000F017FA6B6893F9130030 +:10319C0000F012FA4AF68023A4F88430B4F8843094 +:1031AC009BB2802BD7D0019B002BD4D0019B013B31 +:1031BC000193F3E7FFF74CFF002C08BF0446D4E75C +:1031CC0000E07F4030B52025836A0C4C23630C4B08 +:1031DC001D70D0251D70836A0B448362036B013B09 +:1031EC000363104612B930BD30B10138D4F88030C9 +:1031FC001B04F9D50020F6E71420F4E700E07F402B +:10320C0000007E40F7B504460E46154622B94368C9 +:10321C0093F9110000F0C4F9E821E36A204A770819 +:10322C001363204BC6F34706197000211E708F42A2 +:10323C0010D1D0211970002D2BD1636893F9113066 +:10324C000122590903F01F0302FA03F3164A42F84C +:10325C00213022E020690190A06A00881880D2F801 +:10326C00800040050AD4A06A01310230A062E06AF5 +:10327C000230E062206B01382063D8E70198461ECB +:10328C0001960028EBD1142003B0F0BD002DFAD02C +:10329C00013DD2F880301B04F8D50020F4E700BFC4 +:1032AC0000E07F4000007E4000E100E010B5134BD1 +:1032BC0014461A7CD20606D4D3F88030194214D1A5 +:1032CC0050B9002010BDD3F88020520409D4D3F893 +:1032DC008030194209D168B10446FFF7E5FE20465B +:1032EC00F0E71A7C00221A74F1E70028F4D1002CC4 +:1032FC00F3D1E6E740F2F514EFE700BF00E07F40C2 +:10330C00402213B5836910480193104B01631A7066 +:10331C0008221A7000220E4931F8024B0132082A99 +:10332C001C80F9D1D0221A70D0F880301B0402D541 +:10333C00002002B010BD019B1BB1019B013B01930E +:10334C00F2E71420F5E700BF00E07F4000007E406C +:10335C00760500206FEA415110B56FEA51514FF6D6 +:10336C00FF74074B42EAC03242F4F0421C805C808E +:10337C00DA8099801C815C819C81DC8110BD00BF4E +:10338C00760500204FF49643002213B50193144B9D +:10339C0004461A6043681A7842B193F9110000F0A0 +:1033AC00FFF8636893F9130000F0FAF84FF45943EF +:1033BC000C4AA2F844304AF60123A2F88430B2F841 +:1033CC0084309BB2012B02D1002002B010BD019BB6 +:1033DC001BB1019B013B0193F1E74FF4FA70F4E749 +:1033EC000070004000E07F4038B50546FFF7CAFF8B +:1033FC00044660B1204638BD8021AA682846FFF7F4 +:10340C0001FF18224FF4A041FFF750FF04462B6B2D +:10341C002BB9FFF71DFE002C08BF0446EAE7002C71 +:10342C00EAD0FFF715FEE5E710B5104B0446D3F8CC +:10343C0090310F4803F00703DB430E2220F8023BC8 +:10344C00FF2100F0B5F82046FFF79CFF2046094904 +:10345C00FFF756FF18220021FFF728FF0446FFF75D +:10346C00F7FD002C18BF204610BD00BF00A00001C6 +:10347C007605002090A1000138B5816202630546F3 +:10348C00FFF780FF044650B90122144BA3F8E0204B +:10349C002B6BEBB9FFF7DCFD002C08BF0446204674 +:1034AC0038BDAB6AD5E9072123F40013B3F5803F8F +:1034BC002ABF0A464FF400514FF400412846FFF74B +:1034CC0081FE19224FF4C041FFF7F0FE0446DFE7FE +:1034DC00002CE6D0FFF7BCFDE1E700BF00E07F4029 +:1034EC002DE9F041104B0546D3F8DC600F469046B1 +:1034FC00FFF748FFF60F044698B94FEA58323046AA +:10350C00790BFFF727FF09492846FFF7F9FE2146FB +:10351C001822FFF7CBFE0446FFF79AFD002C08BFDC +:10352C0004462046BDE8F08100E07F4030A1000158 +:10353C00F8B506460D461746FFF724FF044630BB88 +:10354C003FB1144B45F4CC45A3F8E850BDE8F84026 +:10355C007EE51022FF21104800F02AF84FF6FF728A +:10356C0015F0010F47F6FF7308BF13460A4A0B49C3 +:10357C003046D380FFF7C4FE21461822FFF796FE93 +:10358C000546FFF765FD002D14BF2C46044620466A +:10359C00F8BD00BF00E07F407605002030A100019F +:1035AC005FF800F0D50800005FF800F0F5020000AD +:1035BC005FF800F0592B00005FF800F0AD08000038 +:1035CC00000E00FF0F01FFFF0000000000000000D4 +:1035DC000000000000000000D1070000E005002002 +:1035EC0010000C0000000000FF00000003000000B1 +:1035FC00A086010000000000010C00090A00000078 +:10360C000000000000000000890800009C0500205C +:04361C007005002015 :020000040100F9 :10A10000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F :04A11000FFFFFFFF4F @@ -856,5 +883,5 @@ :10A2A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE :10A2B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAE :10A2C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9E -:04000003000022A92E +:040000030000225D7A :00000001FF diff --git a/variants/THINGPLUS_RA6M5/pins_arduino.h b/variants/THINGPLUS_RA6M5/pins_arduino.h index f6b080b8..56c4b842 100644 --- a/variants/THINGPLUS_RA6M5/pins_arduino.h +++ b/variants/THINGPLUS_RA6M5/pins_arduino.h @@ -132,8 +132,8 @@ static const uint8_t PICO = PIN_SPI_MOSI; #define USE_4BIT_SDCARD 1 /****** USB CORE DEFINES ******/ -#define USB_VID (0x1b4f) -#define USB_PID (0x0036) +#define USB_VID (0x2341) +#define USB_PID (0x0068) #define USB_NAME "SparkFun Thing Plus RA6M5" /****** FLASH DEFINES ******/ From de980967ca2cc013ce3f777e23ec618cb64c6aba Mon Sep 17 00:00:00 2001 From: Alex Brudner <101155592+SFE-Brudnerd@users.noreply.github.com> Date: Mon, 8 Apr 2024 15:50:08 -0600 Subject: [PATCH 13/13] Update RA6M5 for proper VID/PID. Add signed inf/cat file. Update dfu hex/elf for VID/PID. Fix package script for thing plus. Delete package_sfe script. --- boards.txt | 20 +- bootloaders/THINGPLUS_RA6M5/README.md | 9 +- bootloaders/THINGPLUS_RA6M5/dfu.elf | Bin 483328 -> 482476 bytes bootloaders/THINGPLUS_RA6M5/dfu.hex | 1561 +++++++++++------------ drivers/sferenesas.cat | Bin 0 -> 9039 bytes drivers/sferenesas.inf | 63 + extras/package.sh | 2 + extras/package_sfe.sh | 50 - variants/THINGPLUS_RA6M5/pins_arduino.h | 4 +- 9 files changed, 863 insertions(+), 846 deletions(-) create mode 100644 drivers/sferenesas.cat create mode 100644 drivers/sferenesas.inf delete mode 100755 extras/package_sfe.sh diff --git a/boards.txt b/boards.txt index 8889fb32..f29a247d 100644 --- a/boards.txt +++ b/boards.txt @@ -220,14 +220,14 @@ thingplus_ra6m5.build.float-abi=-mfloat-abi=hard thingplus_ra6m5.build.board=THINGPLUS_RA6M5 thingplus_ra6m5.build.defines=-DF_CPU=200000000 -thingplus_ra6m5.vid.0=0x2341 -thingplus_ra6m5.pid.0=0x0068 -thingplus_ra6m5.vid.1=0x2341 -thingplus_ra6m5.pid.1=0x0368 -thingplus_ra6m5.upload_port.0.vid=0x2341 -thingplus_ra6m5.upload_port.0.pid=0x0068 -thingplus_ra6m5.upload_port.1.vid=0x2341 -thingplus_ra6m5.upload_port.1.pid=0x0368 +thingplus_ra6m5.vid.0=0x1b4f +thingplus_ra6m5.pid.0=0x0037 +thingplus_ra6m5.vid.1=0x1b4f +thingplus_ra6m5.pid.1=0x0036 +thingplus_ra6m5.upload_port.0.vid=0x1b4f +thingplus_ra6m5.upload_port.0.pid=0x0037 +thingplus_ra6m5.upload_port.1.vid=0x1b4f +thingplus_ra6m5.upload_port.1.pid=0x0036 thingplus_ra6m5.compiler.fsp.defines={build.variant.path}/defines.txt thingplus_ra6m5.compiler.fsp.ldflags={build.variant.path}/ldflags.txt @@ -243,8 +243,8 @@ thingplus_ra6m5.upload.tool=dfu-util thingplus_ra6m5.upload.tool.default=dfu-util thingplus_ra6m5.upload.protocol= thingplus_ra6m5.upload.transport= -thingplus_ra6m5.upload.vid=0x2341 -thingplus_ra6m5.upload.pid=0x0368 +thingplus_ra6m5.upload.vid=0x1b4f +thingplus_ra6m5.upload.pid=0x0036 thingplus_ra6m5.upload.address=0x00010000 thingplus_ra6m5.upload.interface=0 thingplus_ra6m5.upload.use_1200bps_touch=false diff --git a/bootloaders/THINGPLUS_RA6M5/README.md b/bootloaders/THINGPLUS_RA6M5/README.md index 9d1def5f..658295cb 100644 --- a/bootloaders/THINGPLUS_RA6M5/README.md +++ b/bootloaders/THINGPLUS_RA6M5/README.md @@ -16,12 +16,15 @@ TINYUSB_ROOT=$PWD/../tinyusb make -f Makefile.thingplus :rocket: `How to load bootloader` ==================================== -Hold the boot button down and plug in the Thing Plus RA6M5. +Pull the boot test point low and plug in the Thing Plus RA6M5. The board will enumerate as Renesas RA USB Boot. Then flash the bootloader with [`rfp-cli`](https://www.renesas.com/us/en/software-tool/renesas-flash-programmer-programming-gui#download) ``` -rfp-cli -device ra -tool e2 -if swd -p dfu.hex +rfp-cli -device ra -port COM# -p dfu.hex ``` -Otherwise, the same hex file can be loaded through the SWD port (using a Jlink for example) +Otherwise, the same hex file can be loaded through the SWD port (using a Jlink or E2 Emulator for example) +``` +rfp-cli -device ra -tool e2 -if swd -p dfu.hex +``` diff --git a/bootloaders/THINGPLUS_RA6M5/dfu.elf b/bootloaders/THINGPLUS_RA6M5/dfu.elf index b805b0a4c0f05471bfdae172fd46a98fde4c97ad..473b709a520127aa98d9e305715b793bf865ae50 100644 GIT binary patch literal 482476 zcmeFa33yah_Ak2kIW;Dgq%we^!ceJV$Osj}q^J~0C?EwS3=W`T2EYUmiU1PPmI{d& z1Qf)9Au2M7G$08Cr8NeDwiSm?5zqh*L4<r|q4|NGwe-goc!-n;iB zy7pPWwbovHJbOCl6w5}9vvJN@=byl07@>(K#s=ZK=K(ci3Z@*yj7$xkk@X_IW1N+- zaTY&mU`M3rAd1iQ6!`z9z>Y{s5OP_cDeH_RKMn=azv#1}e+#Cd2(U!tzccxEi5iEjt)f5u>Nz_TTLqxLpIcYv6Vb+^&J!HE_EI zZr8x=8n|5pw`<^b4cxAQ|Fde~{l79J?e#~Aj5P`WmHu4XPCdzppNI{6QYd4ucVR3W z{Cs%>|3{4Ry!xs{!Bt$iLQySRgn_!Ww^9_YbLzC} zz(UbssY;TBhq^dh+^m}EL#-P4JR+{Yp|G%c%{gwGsuexGM4?q|7SmIt=-+*_^Q=DL zPqsnlc=R;ccB55jGKvaVoAuSr8822h&wtS|n({+&hE*zUKJO-_4M*`k`&b1R)4?RuUW#q-a}Vpr>c*EN#$ZXGiF8uQ%jSx=Adyo{_NQ0^ zf0lpqmv}|WP}o?%3=a<+Io@3QW=dQwQgHfHxYyn-uiN2!(p?T~w98@0;{y#@PIzI) zJI6O!LdNISpG(SiO*Jd>Q zBOo{LPDzLt8w2>t(se0!xF$;hmcUlcb~sUhc!x?m~Ka9#8i7ks0uzsq}fz`>HN$(Elz} z`@G)jfV7uTZy60%#_N`+@N;2?mn!r&$LPc>p3%K*fh)(Y++4A};w9VjrQ1@5R3C3l zQTB-XC30`Y?vx^1uuXY#eM&%W7h9QOd&RgSmN>L#Q;Mo?vte^Zs~gftl5S0jJ@d81 zoZC_~jS3!Dx7QFJm5{c*;`NHEl$h#!Y|EnJZIf(cY}FM$Z@2ab%0GnkZb;0wk&ybl zA?*oiJ1Q2ejI-@8T?w0=K1Wg2WzTclk!FoM!M4j5Ydhnn_Dr*#cKdwjL#dJD)V7PI zgAa3KAID6`4#!0Y+PrwbG<|J8BhD{w8hfa}>deU#6gIJq=N^z$ z&LG?SO)R9FE2*3}4HX7SVV0?iwo|J53{SneR`T3ar)H-QTbK~sP^2h^I?2c8A z&nbT|uEPE1%n_d5BF(Vum*(#8)w-(9yhikdh_9!#x^mZSR@^*YH)^ykrutFaYvmap zomShXyrF8;iVrQlU(#-&a!j-hw;64Urbrnz;d5Ay~^jEUbO+^l3)_-)11s?Sl}4l8}};% zHaLCW=4w_gW85#-s(rpyPdX}j{9xDTPYUq^UCbP5TT{6DNuFS=u@^?in_OM&&legT z<&x53jaQxNtkZLHooX%4if;9*3-_c1yS^&?wqj>WfJ;}%lZ|Q4is-a+?k}Dc63)5S zruLeDZ8?au?LWlPV@&ww zmd|?*RD0_#%)myAAwTq~kDD3$Or3FRy_BF|FU46`r*x@VFC{W#xezP3CYfssboJ|{ z7`@A}UWzyJyNVIQ*2o7IBh*)Qn?3RX?5*PtPn*3VpWo?xm=ElhGc6}7zs~WSd%cuo zom5*2TsfJAYOlc zQTe23R{=K_OBUk^ND}p-{_18Qop3Xg%5HE>b8K>)btugjQQtI<8Brg9tUC?k|C;xBUfI0FLNQTQ z#|Nz~FG701jm09-nHf{6r)G7VIY$+EI(aT1fEh|mo)PNe zn|ph#i_#jz8KL!jK&VSdyyjwY%{AOaDfqk&-!JaoE!IJ44MG|l;C2nl-6vxqktA1Y zTHI8oDVbQ_rZN-rI9VuSefE*hr#~p#RO48l$u>1lJjzVRuL!2dLjTBk1@i^XF;bfrS?;Hl;M49ByLKnlapCZr7W9(Q0r#+p8`+tPwy8pgTVD z&%4wI&7fou(pV|3OhHY&RI#FTJyvK(8*KvCUy++D-bhi{_Ey|ccjU<<+6b4U${FRX z*q_pN^2bth-qGe@L1<$Z?y<-EDcudmB5rJO$JiR(%PLa~6*ghG7#~*m!)4JU z^zG7vMJLz|g>=su9CRIt>r`;r&C9{{wMW|`^M=)%VRKqN;lJ-vsD0zg zvn$u%U~Dzo%$g8WZSBosg3hi>39T{NHs%GOmfyeSG-}40Z2s}Os0wRitpBdLxUI$Q zG_vR>H}yXUtrsdqTiAG(*Wac?Pu-Ixe!`-!6rCx39z83-wi{egd3t%;zvYV=74<&v zVIPaRid}-EDzeb$eWu-u@rC@VE7wTOxJKd@LqL>njU-wa$|*pi(5rA~QJH<-qdsvz z?uRy7>v}R)?#DX*hR@q}qr!ebvg%Ky=Cl;1tVWN}Dz-^hqwX}M#xRdF8pG6ar!!idDbq?0NK=gBJ9{Oa@ql!{QMC(g4emkXUP+JZG+e`s8P~l9R3_>X zU6Ee{dPGkP@@i3;H6|(p_k43xxy$E$qx~^um($Gj_?Z1tx@C)$Zv0*yblT_j+{i4? zXsMs+G(Bcl?%G`X5^?ILoMf*?6pwrpobH+8kP$}6Q)fK(0ZP>N$kZcwc!`MqRL4)`VfT+2-2x?4}Nmn_sqJ=dlDfPguuW$KErhS8H)Qb_DfXq`V{1Qn&+T z>?4`8c(N+q<6?baT@YhSp73VHPHBc?rUvyDdFe3eQ=!24;e1fqHhNo?7^oTikrW+OI)WcXhM=57c0{w*Npy{Iff-+p3i2 zZt2zfd~3YC+j;}LtvPEpV7FB%#W{86Pn!cZHP|uM*p7`lgWcE1wuPzn5B?Z=7%Le~ z&E%zL)X}HYZG*=0wLWjfO}^p8s1oeCoT+oL=Zb$eevLtWQ{Hi@QvTYgATI*3wyY^y`=&e$kF>YCi8#=LXtFytt7tj|09Cejp7jM`igURO8jg45UX z^t;#zI&vM`92Xq9ZtYm4CkFh5Nj!c7%5BWL3gPN<-(4+hbM`Ag!e-Zt>xb=0MXKi!r>Cg<9 zH7lWcqIIj=TnMd$*4$>t%Thnf50Y*<<}|ScJYlsbi_@&*$1#?ySid#~+87Jc%Jgev zEEygqeu|VrU7h#H8UKDVnsU_cZM)^{;I7}A<+jEKx$^BS{6)ToX7ppL&aQ8Ia+GBB18dao;E_jOz!zk{*FZhqNw;5UPq`O_;xvbj*T zn@%Rfu87R+`1A_ndUtLi$5RQVLQ<^^r5*y^k> zHUzMm6)gVl8nJ086L89~MPf&`;$94H6Bpi@HZpB1#=BxkbEHTrJi_li>7w+aZ|y`a zOlsTd_yB!9tHxaTgY@uPv&Vwg+=y8-FkYzMC^5@MN!+qAjU^X|@d0?omw8Tnk9*7@ZacUZso?b{l)nqIA?QhS93xo}|i{-&ll zFU2+%G_iDG=H>4b?Es^+ss^gN@DVHd}%6PR4J}js`LEV@loYQ_iMJ`cVy?cY5 z4>c6FVU_f^ldrj}aJFO!sH>RVGdO<4_2c`f_01kuU4(Yt2KoT>ck}_Gd(aO^)`|bq zbq(}kCg)hn&APUVOV6OUj%eAik9sNfx)Cj__6hX@cA8I)O)qV97s~olS^ulsaab@d z9=jNK*&R2y(aM&0UpO|U#kw%iDR|n2Q*LFidE}S^?NcXmf zqcQJab3Y{K$NH!I-nCCC^w$%QU)GYm&s>=5(V(Z;kh&_23{+r35YbpICar4c6_Yl3AhY#-f?TXE;` z*b&!n>EM6 zp_fi=<7-)rwdRiWVYW%qP$PS(-TPV_#`Xn#Guzb7`8V7_ChXS?&iMK-(9dZ2FuZ^^-)rkBar~RnS_<_T$Qm7$+Or6VrV%bL`Z#byA@o_piP}$}=8qE*i+=YFw0$ z(QSRx?oWFa`Np0>T!E{fXEIN7)`*sG_RyU~HClHI;}U9&M%y~|h-)YI%)hi*-FS+8 z_{){iM)7IP>hwjUc^yV5Jx*4ZDHV;QM6uBoj#B}a(ctQi@tfh4fDy*nE%PjKqU+A_ z7^k!13zctv*jU>uvSu_+RQ+q6b6D%Vu!nuL>Zc@oRC%n;VxxN?KA-M~<$J_vi!CmF z!|11fdgTVQ?8;;Ds&mw4i}&1R>pPZtUi0nFYg~C(+VHg9Sq-I|X>V7=Yeo#{QWu|} zd^iT<*9wVx%_Dn0aSQNu2YgYlYI4!oQs3%??5Cf6-nVZwy6ez0?z}bT_dSIF#8NG< zM3wo<&D7Uuw%Ij$@K5H#~-|TQvb|pb6DJ{8oql| zwqWYE^lUbd)wmeW{$h>O@``aHHwi5oLnq2O_e(V5><^R#N(Lnur{#3Z!3iPGh~nTa zULRIY=Y~nfgLLAElS_;7>fwo|D4g+y*E7s|zo%h46?o&AdjC0?L3`n=110_`&4 z&qDr<-ST;yt{P{eK(WRX|M6V3-d%=zOdU9Oavti$QQ7Y8))qcC+#c{W#>Fh9O|N!I zPJL}f#3_R+;?y}+#Ocr$>!Z4ARd01~i;a0qKAH!WZPDnJbUM)PZTwKtyUDHW{hM3e z`xja}*Dtfu+2%0#ZfrHs*(R)hZhcuAl*toyF7uoV<;T3vc%#!1I29j?*0%@GUfAB zN?U6W7-J~KlhcOf;o5ZZnlm}9bdpBMRi_`h5@2R#C*m^CzK=}kj|Zt=IDI}khcs%a zKEewlY&b6ycwCUp>Io>qsLHyzatj0EgK7ff`?+{*Z&yyK(>~47?mg8;IiNbY_z{nd zbOqR+8ta$%yq5QkF;-6l)+#EjA1^uS6hkqv`=pSF5XNJ1;*456(M~&XF}BU+^A@!8 zSg#9ZX=`%x*sJhmwB=*{tdo8QZg9<*kX#t<5!j`gi>1~?cD2fxU5eARR8^CXG0*F_ z;%wk}HEd70rj8ASEoU_~s|tm9p+*^R_3Ut7D77LdZ{b;H;DX%J&w&Grek?WMyl<5w zW9(M93fEWN>FMhV#aLyHD)#;wp12P?Ol>_+40MG*IlO#wp(2{09cG{wPZmzBS4OwF z#l$k`XdR_6N32}$s4cxGJ={6^`jGt8{rsdNOFH0 z(p%iuEto%b`AER(r>kNJWEyK?8B>f48Nly6tqzRlYFwst~qC8iW0@6K4>@ zvrZ{a)|aW;PK%};_F}1f^bWh2qlCV%rQI7Wac~xkQ>IVTr42b3-!vpoGyTbO})erPKiQYe$r)EnZBS#~ zqP%fxxn#=Z##?v}{U~bSgDJPX`+Xwt8DG3D1#I`;*JWK667*FtLmn+_xrsa*xg-MdGJ4O+vYGt122F6o> zd2&{Kql<5xls?5C`WT+ng$Wx)<3w;JVdBPhxR!?9^3KMSk@3jE5k5!~0x1sO31Qb= zIfurK`#~DF&YWi-rKquu!872sx4duD>{sxEG_0r&yAGQ9_;7k-AmAj{5++ad$BD7@N9}L(Aj`6)V?XFmwiZjt;D*lOR;*sDoVd9Oro}6COoCUsgA#824GH2 zM~eN&(6ftM-g&-+2|q|*tWAa|=6Tl%UkjVFV(hHX!Ypp?m!7<+B5QH>Cs$PW(VGzT zz6VZZ^Gz){wat#oPp`-PfH|DjZuDLOOHAVOH%DPh85=T>v+fgu>3x&vFm9~JJoP@- z53rQKOX~PG%Kwd$1@9uz`v^{E4ZwRK^h}f9H`s&m{0qWNV;x+yP#uZ*8mtfLtp75} zH*~c!E8-n(44g74Ba_wz^bCOB%AgV-$V4z98iHZQ)x5J= zJenEXy)kXcd5?@mU#b53iZF0m)x*k-+8%^bHi<=!)yri!+ftKzjqX5pG=(n}TM)e+_` z(oe<%Z7t2I*Wb@nnI25t-*(kgnq|FSm*wX_&3cfLOp`su=$DMizGqB_U3S{l%nrLT zIm0@nnw+6yQd6lff1W+q9+(wBX7G5-3#}Y0te7#(^JQy%p)bCdi=I~u0R9|%vi|n7 zMVpHH<87q=c5`|EF|=Mzv`1#ekCQ5HdF!xWwtCWwI@j0!cOd#^^g~bH;v{dprX7>- zT{uxXX~>Pcb_R7~osrBjdn9MIdzZKNz*7Yl$2^OR4qj`W@AS+q!s)3aqopf=7mJ*T;ZoPVSqXkw2pYk6ibX;ALfyzdH>EzSOLURn#A z@o?6|d8>g*LvoTjr#y@rASroqVm>Q4)cNKG^}fjLW0IyvU|w;vrqqtp%Z!U6LO#?a zpQ=>1?Api73F+~U$$91$mOD8MPrOP~@J^1wX(*kjym{JCYK@-XJPJ=v3|Mi@Z(bpD zG?EycN{rhcBgXUI^YLs2J*4*mX}U4HStV@4m6_v`Q3Nd;#4{Qb@dIGm@weXmlYui%0^`$ z(5PW&wm0c@Vv|1DU`z0Xs4^P5cR!TYB}+dLbLYb;k_M!BxM0*Zmk#GH5guKL!V{vy z+nHhEHG7&Aq8a^5ksO`|tA{qF;0+^>s7NUPtfG4wonx0l;;5Qo3%9X^7S|1&bVt~# z+y>irTfMu)HWF_bh9mx1m-Q}lE!sZIo|l@nDz7-}^SonOf%#&#JwG*jReo{y=lRF7 z180jl_Sva9t7aGHd_MbFPT(9d*FGmTch#KY+|TD6%e7jpN!Gj0owN)L{4c)r7JZWb zuI7`vfy&y67&ELO#a%Z}Dh6t5PO7_Che~`nPQr)t+Q3rLnT7Y@ShXfDympnkyhe{4 z?yEV5vYs@Y`;+bV+9XLBZUnvQR@`-_mfzLs<;F>R|I}WX>R44+>>zJOkI3PN9cf~W z(q~NyT}Hzfy7?X^bgwqG>aK>TVnwbS*Pu%Pjoa3!6HE=F5Z3TTn4+3uC@d{CN1GTI zaJN^qF28!Tsh7YSPvX4|diC~EiFwW|n31jp z;QkhtvN(V4BIA<$MR~?aGw01*n7zf(c^Kxg-FxuwMEX>cDJJUFM{;WkyvI}M! zGqZE&WIs03_{7YDh57U68T~%A3i`HL1;_LkLO{pE)g4#)!)jnIzn|S6DIVV-e- zrO?vxH(*%YFne~wkmR`Jf%eCkH7$El_8&&W{8lhZf|Aa@VsPeV={WbAfa^k#R_M(* zZoh$ADpWfc6ks?pN^P|IvWT}Sc^GGSE1g+0qJ}U)LF7K)4Sc?S1;p`zIyXYw@ds0% zpb!-b1x3;@J$szZV{_Qt4t)}{u=V`q|EHDJ>HhzNE8a^*s-L3%=x=JE|4N~t7Bo~b zuWmpc;A$U-)uN9y{yz`mklcuRrsqx+(tF!f(|Q>|zjP84o(|?wx*+*m{7A^($Mf)? zNiU2KNJV$9XlHI=Cu7TS%aJvR>*TC%>xLpIcYv6Vb+^&J!HE_EIZr8x= z8u&lI1~OXWM(Qi+RQT02J-%Zuv22w}^qVWd=~q^aJj~;DuJPA-_*N+m?+|Qg)mO0u z4W6g9I{4i`yPfgZUECzvr)5pcWB3m0H+(ybX8`zi8varbn3nJ7>vj05N0)w5a$2Gk zn$zJ=Td!WzhkNuP8hqP`w>d`h%~9oiGfn{4|Ll%1UZeLZ*fV&JuuS%m`9JAnVP$Hb z(uQv%%IR4*^9*mDc^$@(sc>PNVHv zJU5~@PN+0|{hYi%{Dl1OC!jU`y3@QJp8VdN@!!zoDVxC*V&EJ%y=C&gRkkS zZc#VhN(H_I?qV|?PDNR$R5dp)M_-t2Okbi2&o$aVX&$ZW=3vo19WSQnT{Y3*6XRX< zY(LcU=dbU(%3t4`>W%q)?UvcBG}4JyVpe6qsV%d4l3>}AQ$Jg<)aMxI@L|T>Iyc{7 z>&ahbF^#SWqqyHw#S&X<_&xrXm5@vMd;g9+%HLd8hT9`-hNn-eRHtfDmToB#uFS)D zf2|70I7y-HkZN6dWtVXUo0l5

    #P3gV^=%-SVumez`6eX zhLIEXmGc`WPQ=sjMQVFW!;yh0EuNI_&WD|6og1Cqiykg2EBdwweZQLQsW&j>gRhUU zD{O|W)Iar$z#AR!PhP2$&60kd;}-@>EOdWuuE5)au7A&06W#%Db)W`u z?@&AYf79Ru`ePQ}4jNYFjNXl}mwaCCi!|Zg|B*g#CUo(0;t%`0J=*=f3t##qG~f-e zF6|fH`bs_WRx7Pd3K>J+Ae>7LHqnW>4{sRlmFT;>GM~|=#rrn*!y}9Kd1K%Y-?iLg z36a%C8TM}Fre4qxWr+44ltNXmavdpG3&2=eb~SJ?12b;2d&_`_T0JK7iTyN}e{mB{(G zSs}Kyh%v@@Jw##Ka5$sk!GRXrlY#iQ)2AIvzHYSR3n-J%`#C(}_aA=G1AUc8b!b7p zrAigP-Ma(&-pIG*gAwHs_E9ZgjM^q$&cqks)@Lr#w_kcZRW(Uy{emv|qI>jp-$G4w zxGf+(aID2v>-2e#cck=cJJrCAQem8hPO7S$7_N9X(F;~AstTR3y3>opv{ z()BZ77R-DhIG6tSndR>|qo(KodZv?AWFUg*nG^kS9n%KLoIm&re9<#02k1}Y+wAQc zxLpIcYv6Vb+^&J!HE_EIZr8x=8n|5p|AQL%Pd}gcKQNb76zBiS=6@Hx@78~+f&cep zlJvhet^Zx>{r@ld{QNQccQ-h_>cf(i*r@g>!nSh+=tb;EJO2_DpMXu&e27rF{jUgN zIS3bC_8|7B{2)a1rV#C2`4NDAV9X%l3jiyay9m?)JPhVRP`I=YZy~`=X9)efk#7NV z?YnsA3(Nvi232dH!K->yY2j*)~M~uF(6_`H+cgP>(0@UY0a*W@= z`~pHPo!X5WLJYi%k6LP^TB?WWCZI&3p8>)l4IzyL5C?|J#}z2j2r&161U*1Hm@x#p z1KbB@GJ$>od0?i4BJxq0_sb=skXlptDTptHbPd$2K**9|J7Y7TPN4M5GQjEkK*Tdc z|B2F)Mvy}z^nxgg{2as^5cgF|V$fd3=E24v;uB}4oG$W_knVu`EjbCM0y(>MfYq!HvWj?z#gjiV4BLFA7pjc)L^Nlt@8Bc+ie^1hIM3H4_nQwBf4i9@`YkjoWC;MgEE_$Whe6Z;XO}>{7XXL;7J!fdU;u~! z3Bv%AzzhJXzd$e$F7Ac{k!K2vA^RFKs>aMeWIcZcrq(7K2kgxgZUW&Ca-^?Z_P&fd z;3~w_uZD9W) z`$jTIhKMpaUN(5Ikh2FNeo!`e5y|k6A$l0f2SLIY01Ls)2Sqk_7>n{v9XwW<0{Z|R zq6+Lu&Q`#t1cXjp2g~VjE6O4LBRa62P2Mj;vkpctl3@hdmBG#*QXzvMQOY*2L%&&e zrhFAf`(cy`H7`p<3+lH(gv$IYF1um06C~%3%tU!u2%fF1r`$y%lAOCL*nA*6lyi4T zwxm$b-E5@>e&v)uh0!NuDCh2HSa3$6oV%s|+?|5{r0h)jNG;kDx)@w|SuRFMJ{uzH z=HG#YB>)nbs{~2_?trgwQ1IH5oTkSGi7nB~#!|MVd{P*|@vK=BY{cBt~lI++S&c1*R^+BesgJC4}XbOZ>!DKia z48I7~H!wO)hM{CQ5GMXm_V^A*6+?Uh2It9$X^R1=tNFv;5QQ8OlonLAuof!3$}KmL zoIkQt$kwvA_qg(WXZ}QTK~gz?HgF=NP|hC=1E}pN>0k(TWGLq^2OMVs?vDU0hXe2|a5?~-_QIU@JY*Q$;Itiu=kX97hs{SIJ`~_5Fy9gw3803t z2;$=bx`T-X2~z=5z*q>(1ULrfV*(2RYQTH}iaZb?$f=1e73m4>q8I>ApF#Q))b$|# z5rBr;9~2;4eGN$hP+ySnBY+)DDuG`C=7V_*6xa$Nr~(D{BG4+3wj4#o={x=?q?!)< zR17QBB9(8UdJ8shg7`lH_JG+<;3&X*U@Ac@_`MK;RUop!rcv~-#NaB5UJLPY7#yJ( zp90i@IRy$JGoc=mpMfre80+;5;4F&%gV^OfMGr(80^0N@^tyIvSr@V?Ae(xzi>&Vf z{T(2`9;GS8GT~P_D-@DvG zeVJN-_(6=s=MbAlxF==RQiPMqK-INF->I7@6#mI#5nL#Z?=Y4Iv$+7g>~tW)B#4|y zbrDE$FMvvw2j>=`QJU>^At z`F;&ze2d4v2C-nO_dFP(=aSJ79=QWXI;wNIt}npqJXxwsVMVv)=g?DWmLTjb&5{Tz z?-RJQcfyM5gDEHO!mow^)dBFb`-2eXKy(w%eg^UR03+dVFi3bBU@4e9P+%#5@G^p5 zfqn)FTL5l=@eX`e!gPaqX8hxnm?hF{`QuErXHZ-nYz*bD>l)c_BGnGEW_ z6W}Z&$xZ(@Kt808f#7gDsz*inlS6r}@dWR7lpHRF>Pc8F0r7bNC193QH0_;0VTdKj zA&r8<5-#F5IxuEI^&*VcP^?h^o4{<4V^QUs?_q=Ln*k zJlqMD4K`^YHi&vA`V4*qj877`@kvP46pNt-V*h$^A{vDEhiEeFGeE(l|3dctD*1g% zp&AVv9oh7(f&9;_+^AC!WYD;8&ZK`D0)G@@I=bs$;8XCRPlJfoyZ8T#%A91yXa_eP z^H?{)%fG`air5Dto*8u&(&vGhG86&{2>l6ZorkPvJK#nz)JhJrnJ@x5LDSK8k(Z^x zJAVYC*(l;H5YGcB0`nIF3jsEQSqBoH0jL6Vn7~SaZ^4`-@G^iV5Z@sYcoQH2APyw# z1{exvFev;l$esa7<7cF)gW<31aj_%>>AV09eKIo=#KP|c>I(}lhqB!X(;l)*hh_q7 z#*tmn4LI))J1YCqq)#ax)*AIk3woH{oSK56a0= zDBD$AVyI%?f#wO=ECLCK0E)mYqe$H=k<=`hQ`*Ac09Hf%JgJ!SP_Dq9hR)yQkHVAw zBZ$z(N}X3=&p>5@9WUEUi9|y51|n_(>CFIqq9Fm7t>ifo%poZDfeb?c_CXpr6b$~9 zUt#;U1>Rx+c-b_(`oilVYJl-2Q20PBl($3A<8YW*n%GkSnsYFy?Y7XQfivClJ!_WhsTS^pKJ% zorrlEg5I*{xnYR*JVXoN=y4E#1)vm634tvDZ-Utjic}$E6jNY-L)_5g${dQ^7t(`J zSCD-az{g;!2w$?%@2{e~Pp0C6bps~}L1J^=E##4eMc5lSr|2$31OXizBWW8ecf0Ya)_!x&|d zY||h51Q7nTYhYG`?BF+X5KbbqJz`K0WoZ*s!(lcQB)knkL%*Hk$<9r31}UVjhF{C^ zJD&@K*<{2tOW~2KP4f(xDa6o3OcK`Z>9onCKvo{2NU%p7^(rLY`#}u77Q*i0K9B5GS!b^lw@5HXL6NJ7BS^_nE4)r zv42lj1!KKio)jZUGYc9_P6%;_u`Y2c9Vu0_A)smu`GiVrfvPL{{sPGFS6Q8`kcV!% z*?5@_XLS5Khzytly3%yf05AYdBFN|k(CTXtszmywkT;p~>>vdzK`Q?ESrp$5ksaov zK)e|sA51Pt&jwRW>3J-Td%l23WR4XE78et-#!$){bcjpC@vldp>npIAVH1gZ;AQ); z&*WZ+R>DsaIac(;W(dq~0-*pdFkgaAS%UA>am} z>17ImF98a{6o3L`Z^4N8GSFI3mu~@NsYTH7R)F9AN5B0i{}BMc`&R?}?*A9W`B(o# zp?(*>-vQmB2<6nHW$CA$sdF$7D-2g^fLjl=qFod=-8<;-;Ey92s-aXQB76eDd$6hmvF0MQL-n?QUsKqO{_2$1kLKs=aOkm4XfM{b0V!4HRU zFe$zQ5Y}ZG&*931O9*E|{3u9Y1khQ6X7G!Ua$m{@(iK`DSO%-7KukRkDymisR8-rv zPyS=89g+oc#|^FeqQmsx%y`nDtyouTnOTUYqk3e@E<*&?f|zuh^0G?G!95VYgw)r9 zcoM)4Fxv?90jLCX0Mt`Jl$rjagR4h0W$#9Yb;Kd7SQma=i**W2K-S7 z(x9=D=@fvOU>*ep$YygP`3ulfAfXW8c`z$Lfh7QeYY_-#2+APZ1nM;x=RqY%AS^)9 zC6^L-4T86!*#Y9u15|+7Pv9>AG!uOQ3ZOW`c1TVD(R>p_M_xlvG1Qa8rf`FN(DfZO z=Rop7*JUu52+%=SGngh2{_da?s8U3w*(|K9qRT4E2%S_hwChb6{pqA?EoJr&h5w|g zEA)C$=SkHav}wN|o-m*=A&f_SN1kZAo(QXWkbG`349pM^>-7w3zKn_z&c$T3rS5qM z_&x-w(2t}DTLJC|Gl{^f0C`|$fdb@+e}iNR&;n54F#wc@azRTWDvxjn56q=rLb+HA zqZdGOE;fVN2=eD*7v&<7D-ZumE_On{ogz>!4uh#AK)LuF%x9ngIU?oaEYK-XM=oLp zpb5mS0PSFIf>b3i`{Vo!_Fbu)D{*3@qwdI*1Nvhf0iziJ zc=FT>;av~~;zz61puwX7ronv3Brrp>5U9_>oDP=8K}=)8B8*g5AtQb<+^{f;bP&aU z8y3PCfZlM`6J#JS$EZRkgSi)yyFuN_?YHoN|Cx{tFc#9$ApG^99Nr`i`zIoX@8Ll@ z%As0?6#?b(P^@LbNvHWe+Qw` z(%}4I*wV677zJ<=@*0qQ*O5lP>-vg!a3j*8yY2^Q&w>1Rm3Dg=p8CqEQHW&=3yT$% z_mTB+sG4B;8;BnUXb00u;9Y=lOcJO4@ z9GY=I0LjJq49q_WP;pLyISC3N`#>rV{V6AV{0wD*mj#*-=0J22mggzzJb;^EBmz$X zbiraJgjPkR07+ozC+St>%ims^bQFl@p}UtUKfnz5FmjzKyRV0P;Twq35ho2K{0Q(E zm`6eUbAXj#o&!aX#Y9VsY3gecQ+q6;oaI8c5z5!ddMdz9Fxx>adLGbHm|E`T`?QkB3*M?sV#{n~P8QKDXghE@%%D;4TD zB%q@VGv#=Md!U>G9WQ&$jPNmtd~nx9{ucra#=;;8#Fqh#1v84kLjcpkJPeWxd=zfv z0?+R`ll)MD=RrA_tf|0D!4!g6P#NN$f;siU64(lFLGUb8#iZ6WKt-*ok-+$uC6v#d zu+&kqOnK!Vgjj3$m$TgqYaFh|-tRR;Uk~CD0Q%s1?;8Q!&e+N`_4mC?EHvI{gM@}%fda^0@gpQuVjD)Dxt%4Jd&;^r>M6r0L&1+x-mplPz1qfBs2;X`V_Y3v|03r zkT9XELd{Ddo&=N$5?%qA4(4G3Zvo5$GZz%J7ho1*(_qw$>Jaup@FX-#KyrEM{TtzK zK`EDaC8W=R8Quz}9+K}tJ$j-{eIpqDo+DiX zswWl7=XHhgoyw{!3-ww2*6}8b^`eTv}CRX-9fMS#UT|W z!Guvlw@=ViI(oB@1%HQ5G*`~Ro0NeGLiodRNUjaylZaXa;=clX59V7?fNZAOg-#Ci z3n(xGKrkYpb+HHvOd!cH1ff77AR!IF2*v=CpH?nHnw(K6FT-Euk&akM=xODhuo()H zpH`-UNdftvRyyTEP>As!70kt*6pNl#;@2bDB#K2(D<1{(h#ZTy99v-T4>c5P6Yur~ zV#$w-{ZA>iwB2ck6@C{FA@w-nEw1iQH9;Gn`Ed0(`KAp}5tzRapsmMSVBRD^TaR)u z?}7x{bsPcnH;{kVp*jw~A-In*S18tfxJ-q~LaC#FvxsKiCs~LOHTip=>P2_+9%_#% zg7Q=x+|wO>2Hw5_$vylcmf)w8Xs5+kRUjQ%shM+Gry+MI(BvHSEsRw8P zNC*eG7tCEC`4RsRIg$6Nh#5R`dOQ-KNBj>$e?Q3ok^~v47=;?j$wVGm0>giAw*uJ} zg>s*GkgG3|J8HK)xS9o$+ifYBCkRlxZ344_0JYn0FuOo*VL{TMaS9!$6)YKy2UX|_CzB$88B6mcLYwzlz$o65*o)VrE1?fR6xKQw>QsNVgOt+R4jxj6dpoA z0kYHyNe`eXkgysc5llQtu>qiS?*EY-yp7+*q`ChdXorL3xqm#E(FADj&jT|H6hQW! zbHAF->F91t>+kO&f2?>^KSDJZD(X1v{(V`1GHC9?iiO@e)6m-REikMrZ3CZ!D;@3k zSl^|1t6>W|=@BS-nRf)j^$;yWHVP-v;xCY5}pcYW%5R2a*o@GJTW2=}p z0FkVaauXU3Cb4vGhVs&JWTYj?e~u>LUulH-wy;o2-41CO%mYB&3NRE*G6~2^co32a zK;uBc4~5`itXzP>(1m><1mA#Tz7FDtpnm|wO91A9nM+^^z%npP2+Rf82Ifsr067re zfaC+9_dvpKfUm%O0g_)``%q4a!eCTc*cKj^OsUZ!!x`9o1Cmelegg9&0Xos6Ey6D# zrlnWcY7iOE77^0K7q*KBKS3_&^|e+QNfe7-UsIY$RXtl{|t%t9cun)sGdcPVvu$ec5!#Zj>};H*;R4zP1vby5dS^^wBVmZ z!vNqv=}tp;rbx6P@h3F_2)za&hH4gmoogcob|ke9$-LN^6dh=C`B;-$hms0_ohl3B z|9(;wNlq&GP&_utvWuxAq6Z2g-`xX;ry%|ZlGqI5{{UFs8jbN^T0?14_0*M#s8c6sO zK!ZK13KV*13u89;^M`A34Zl~Z>%U==6=yE})$tAqe1oFo!^@zVJmK z3;auF&@JfxQOM~~s6v**9}q+KQCigh|ADxF2Qjq;eU{!PJlc`(#puU3(M_lyt0*oh z$vdqeCU(3LyDk$&iG-iI@@?^VYQ@)uz@Q;;Z-TfMu3h9ls4qJ83K-EswI9@qcnHv; za0m_N8$_H;(uIDhY6DC=PL4X~{dC+;cS3y;wh!Ee^4|;aBbfk8j0R0q&3-?uzjDgpdoc;e`;>Ap%~eU;(5No`u8&)D;x=B7h#!D)P4$AQRGY zpdNt$C*Y5>o)qf|QOV5^6+*WN#Jd8#0%jd3KsK>J@>ig@LBibtAA_kPFb3coFtr4x z0NezFf7^};SpfPNWFMrJ_TfRVoFs+xCp;rY&Oz36^hF!f(*BiHN;#AbmWh$8$w1!4 z_Mq?5JTSmFA(ZK2vAg_HS`T>d29iH98wjR9i2l?SFs5$of)8qS2YP`CW8}YdV^s_! zG_d>o1uEy6I6TXM5OWgJ2|q4`@G^+T!fh(0^CG}wV6s60WFou+$+JMqK*Aw_Ltyq0 zI0kST%vq2&74PYhV^Iz%i{S<0lzGEY!in?>pW(uPQfDz=D)ie3D8-*@db!+7ht&*fq5 z`QC4RwQ{c=XKhILr@=!Ynm5GtJd*keUsn)`9_+Q_%Y@K$hi+m zrBwqE_U}WqoMTQxoa{z(u@ZU$y#Mo5GmquNzu+dU>Qk_;&9O|PnD3}qoXd!Nk@XCm zY(bKb0UQBwh+dxusEMoI1d@6kUquFTafz*lE~wE zzj>v|8@l8OMR>;Ff$XO#k~j#Hiy?vv5w%Z-wNJs=i>w!sYL7(^Wv;MCcsih)VCqAM zTmh94)HomDeMlcb@~?t4=f8o-VNGD7jr1K`_Q3=WOO41~`ITEak;k=6(mpROC!S^8Z8*-wnPPIXpSd0M9{f zk+-TEFWvGsoZxxImS^=u;x|~X4JQ7J{dDy^7)#*hA|y{ zTosmF&96=H{xuf~i2nwhkyb#nKfro)Rdov(YhmyXB()x3D~K&fX2nNQX%yI@vi?;? zquIaN=k`M8MWk?9`<4-WkQJV(6PHqmr}cLs@HT}aYaw7x;g5o-ehMGVJ|+C0F^j}H zOZlOq7UchC_j@*WDrg^>R>Jn@OwT@Xp`1c9j~xdVUEO1KshjsJwe zQ^;i5=HfU=Hs`$&6wh;NoLEg^LK6NO$ky#F#Nq1l6m87=VWow&;_pG$)Kc8r zGTG=9l@AipZ@e_Ph+%9dzrn%W4l_&m&NL@@MCtG#T-6%EI^q)kEEI1fQn-Zg4iTIb zSdj&))*=dV2|oz}6Dd^q0jfUcLg*lfIbh8|N_-8F57%iBc??SG8!&jc& ze#Qg{4t~}EPREM=$dT2EDv^RYkd;kFKWO@#L2JXvbh!bS)a%tas$LzY|M`| zKgAg15t1V3av9C|jQrA9a+1g~Xk-V#;A$ysT=FzZMMzJ1syJbsp zA6QXH$~Co6xby*FN&JFgB>p~zEDlt;W&^V1II4L~u#2cv+qa&=^E* zq$rhDJ8&ifjYcviu|cFLEX7M}G`RxYtC5V!%^)@s(Bw-Xb`j9zVGti8MX4O4$(-(p zZW&FTh6jd&0CI3`n}JmI&)ZyrB_w(c<~rF5171hJW*0xwg@XpoiX_+McgOKhuv$X5 zDN?%bio2VG($n~7uy7x-;+_%jNAc&tIu)Y5DEh;L^{Gv|AHDGr_;o(~Z*2 zP*P378ViL{NTuzWulnG40pKhoH4I=mh|7`q;mT5KiGt;0@e_iVMr#36rR2yp+wjME zA1t+UfpG5!v8F2T9p-JX%=-$&r^vg(=-t?ZMFnduT-<@AT=;wz#1?`KfbT(kffO7c zhFM99QcPJm;xr-(oJcT=7LxcKN?I$-m`JJ^pa4W3l2ZnN@fJA=D*T~Kq`M_V2 zb_Q6-Dv2oa)*#vlhH@#36v0dJrL5n`BufbQHCQ}~W<1jrpifVDd=IR8@K%TJzXWIs zqA|fw0G&XzBRCFlI*1_zG3@p*7sO1YwDBmXs)>S#8_<6W76sTt7-%-wtC4>bl8F2c zr*!A@2^cH20w6qT3cnmYzEs}H^5$TQY7HKLdn5`zV2e#hHP1#dI-9_k(!nKQt%vcu zkvBmnvVhfR+)c|s+T8}@s1K)aum!{T&^(dq^ zA<2gU_JY`r|gdrr<%K(Rv`ymnxjskQv_SglGYd(a*^vPghikpi+ zZd-7fmI4%m$VU?HDcF{zC6vY+r5b%8FcPd5$ZUdCI*HqsIJ0qt`^aEOnz4GOC4^fa z=2ioBHU=J{fi__Ef^s(`)g53mh~WeS0qz8GJCc7Fv>4^N&|#C!0q;@p*o>D}@i059 z$YS9?jU0BZJ4}vkCfQp=_8`N|4f`!2+<&m>+J!c2Z(?eC3eGQoA>tkAIXU%ZG(B<_ z&)WPZ>z%R*=uHUcJ|tNi;3E+4BcwRpnPoHVd`za$*fjynaE(h33myCD+8Kj z;@xm6;=LZME{LcDlDrFGD2PD>4*^UCF$qa+2e=NzB7!{t&w<#16nh&$eTu^?KzosV z{K&yXJ_7b_b4PmH82p(aI0%=g2j6x zVDsftoOt@+r9(b=#hnAhkvmvsFYE_nBfuU8LxYjzY=GGyrV^Y3a5IRNNQp}To`W{e zF}qlXC19xQaM*C3yp-VT9nNOfo9VuUiNK#_B%)O8nt zakP>#O6s)N@UZJ|W94U#rE{b^hH-uf_FhqZ7g<9i6a0bU?c@2^-#Fj z_h6XTAlI};d+7$3V+uPH3~Wb*V;O{VI?7}gYvU$l9e}BKX?rsOZ#;cTunyoi5I-TQ zX8`g#Ko3d14A1~XJ*2|@%t1Y=gCJUg(+tU520xs>%v8kblBd&VaBO-8b4_sFq#K5N zPbH_1bdAUZm5fuR>)!;x(J&qnbAr-M%{?abW_5&;rVH@hga3AcNK+_rGlOO)f#6M? zdyNG%c+8y~zLP8b={9#)n2V|LL}p|GG8=YAUt0!(#{3&Va1<)c6da&t#o+4tHmErw zc~>3e&~(X%2#T*7LoOV#?su5~amUln@n3SbIR;i=R9jCZ8DQ$00%ANtF2EHamLSFI zaAs_Z!vjEfA*uENuYlN#Y`!ruWI zo&;W~(laN4rsgED2bny19yFPQOj!r>h?-*)|Br2f+FmF};H% zw*vTB?Q0~t3!nroj~iR2Ed5}ORXi7KDdmP9{Wu7o>*j@- zuErHyDQEr4AD#GRV6aFxR;gDj5;i+BMcQOCE6)fhQfp+GBGn)A2+js*;bRdN>EJl5 zd2ZbnvXrQU-X87jZoo<|N?L6|);vT#8!7l8kYY4DhdJ^$xk0*gcX6)%3|Z5WB}FT! z#dkVx6R;zzz~WO~5qt}QZ;dXGxnRW~aNQvk66iyr&?OLR3lzS;!TC5o)^qQHkh~gM zS0jk4kmPEBH6U&!xCdY(hzAHZ18f8F1d@m_qFdqKdlW>iE@4-V?s8CL9IZ=bm{h(QITC)1uYd~1X5f_qlrOSa zf50%-f!iL6&5?2*0k|KTUMDQNUIADJ?h+)q17HP+YmpFD8$iBVgFA;fa-A1hiVZu# zy&VF#A!VoS4@EFLR*KxLWesreNA|r)vK-(^5L*e_08}cg?f`qi-Hj9*1P~j=!?`@n zsR^gCAKZoD}gAT_i{w6QN-8I_&8rp}E;`C}9{0{UhQj8814J!;nfu!gl4Md!P zj*37O5YS;m5Df_ExJrxxv;wyU68~lG{Sm*CGQsf3*2;O(EgX*Gy@Q+{5bH)!(=FJ! zFbZ+Zq}}Rf20>;3l4;p7AkIcI-C`Dq^N~!qFuk+NKxMaBh3pkbMtLoWyO6?e zQ5U|dx&?2DF_eWTJAxU~9H&Zz@~-YR0*q^r^C*-zBgtC;c7k{wNv#Li58^F?M*w~U z@e9E-0A5!NCZwQ6Ye%$&Y5X<^$87v9($ejAI?Q!ORu*J3kYqoAIv{ExsSyAzKr}-V z8QoerqOXaL$IcQaTx^^;5bSOc=z=8A0vG~fFp`=AFag9kf(roVf|yOP3}6X}#RMw> zR)Dyc;0}PbAl48(2=E+;r;(g(0GKb;Zv1^4j5m=IZvilx%?R+cGoW$+jL(qs5mMgr z4q>jt;=bv)>5z!60aN5n$8jJOE3;Z4OD+WSHz@vsB+4lAXEhO%ExTcQXEt62fh)er zgr6;7oE8WyZDn#;zL6w_&aMr~_?a(;PWM+pB zOqQLI$Da*;04?O}=&5}<1y^p0SN%8m{sPEy50HODS=b6^>*O!SB6sc({xU067o90| zNFlhbCgkxwCtCV{5AK0Ak&7$fz`hXR+2)(L@Vx%ag)FN=20X0HWR|5!~WfM|pyGHB0hz+&^rdAwk=SI^k$ z41tc+psl_jP9dPJ;UI<*(AHQGqmlS8|DzFF++fUozWHpNVIQ&xbY^4D8!R>iHzi_rg*st4EC0+l`=8>EU09X3Gv5}vKPlf39L@7T#Z|`TmkML zWbZ=4+2U^4&4<%%P*-aKJ^=q6q{58=^^v0<0`V6(zab^I1AGi~JWX$)&Qo9{dZI5O z3GY2*@rf@-;01J$*5V!^t|%wj62`JNNIiyy>j-uYs1zYZnWIhxry)=Sq?%uE#Bd{b zuhNYuFCM~!1LU+plD{Ii2Z(M+Q6m;d_8_1ENNE3+>+r)4<5iy(b*mwmH{J&&vmx zS`fMjZ>l#-DnwGbdy&ZIGwfesU7I6Iob!;I%}3bex>Z~}#x}oEn2%Clh-7}fa0Q6V zkRpsPe2y)$u0dyJAI54EM`Q6L{Vhs@4ec--Aij$F_XFGmVlBZF0GmNcc7WJU zun*uP5C@Sw_H|yZR}Br!<>qw>UXhq}&t0Ytc;sY|vqNQ$hIy`gzJYqF7AS#c=KN5EVF#fy+c8AZB7q*B{tUxBR4m@P8S#`D(R z$d~3gjfMg&bf$uRJtS5l$qND2fw&tnx zyqxH<8QT-Torv&TS%>n^AGrjdPzUQE*osyy$Z+#!@cdHL1l6zCR)y z?-9<2+m?$`=gCY7a$X~F-#6p}l7AU;3CUF#Qb6FgoO8P&(@EZE$d)9xgaT_p?g#}) z?loj*lJ6L@JIPNB*_-6IhU`o7H$#plDK4V7@g!r0oJ2C$kW)$4GUQ^CDMR8Fap|-% zUy!oU%qc)vOYLfgEH{hI`#*&;)viaYP;UyOS*>A}` zO7hk3NtQMS`46r@P<^*Sb_!lD2=4?szjdM7T^_gtjan(5#5p5F5;tj`iH59AGKrlR zTwRysPc4jNl8x|oma8|D9B0U%N%l763Odd-Ho!lH6}B@YOmeJ1h{n6W(Gt z$4C}6AQ{0K*jYZ0q{6KUXNn=?MGpq_-&!r0BGY8-9gQsSpE#!& zawEA5O!d7(?hHfn2EX&NA-UP1^R6Lz4dfg!jm1lC=W|2mv#-~@lP>s!OsB*&VLAkI zxdiEU4kW(^;p)-Q7r9(qj3YC0l*}_}G{=x5ncw{MJBD>Tsmah;6K2k8GG^+8d5y=; zoHKsfgqcmcpFeKSc@w71p4Ft+U?#`!L<^&m&zU;&g<~)=tweiDU#X>4@ATp!0sgp@C$i zx~Z%Kc5sMyY=TY!ECsD`DpA3BTvY!nvd+NLN4HY{JE74|4yDGv+SIr?LXDY5qcI!_f#}uV^}CZqU@dNl;!WoWpH(zF`SeE(cq<8 z=qMjtJn&q7#6Kppn6MhK}pZj50?i(PvdX z^n!drlg1OhM**gV6{l(1OZo`WnUlj|6-lO}W}UePL`5E}DQh4K zgG!g`W3Uu< zVz-6l&mID9(2s{A=;|^!idsYgx^Cf&a77RJ}|F);gObC`ndxP#o6$^I21!5y5=xdH5mdxrZD*+uB$?uc~L z4U>y8(A|*+$i`DAOcU;zM!})NXtyTfOAg%$nK5ZoP!f^68UxE6n=mEDvv9YMo&cG| z60-aIYv7=K*7*~Kdz#145;ZY8++oFR;lwT!+&#-arNv@Fg~4Js-!8ejr$Ua=oc{WwM%C|k&$Rkj3Mu&5CtMb zd9C#qkgB&9hw>qVdkC+C=~AdKuT{XswWbx(c*x-X0?z_y279tCM00qZjcPW9;I60J z21MwtcL94+rMo^MGVZ$R;gBkapYC~-DerOiSmB-OXMjs9gIsR)F@^%7v|40pZJMRX85DRutfA? z^e1n0h;;OI-1qdxgvg0T8OYcWxzRr`>b-Fx@*4F%4aFEAB0qWu`lB}?M3Lw;dN?OU zQ5Il?9t<~$x7mY7nj$2QpwoJj{U;bRVmsfR0*NT!SMa7AP4oh2PSu>F6L`!lyz@fM zk8vjOW}44MP;;L9AvJeW^TL{oVNQwYDvTTNB7>xg&O{@63qs^ZzhR$P7$Pr<7o>!@ zDAY@%$2s~qJ+8ySn_GkS5{0zA*k>g4c$u4vf<*5@xAQI!?U-1X>bBq~_}O@GS*Xdq z+Py1%TBPQ6?sL?L)_FWP|Zabt-5XlZSr zn?e+cUWSVFZVpip?SYxZTOFckv@4^yB}6fn@oN1!BXu!Ay=%f+9Y9aF`78k=UF-6s z5d`EF`$O*apiCS>(-MC7 z=Xeije)J=eWEDM_#|2P5TA-~L{C&(?#;l!TMBHlM+f^0O%fYXZNH%8=f5k?$g5cE? z5xwXqG2JE>(8^0;L^R8Yo_FgZ%LE`aEt!aR=+0Dl78AMmY#0$OFrxkbSZ2LI7YD+K zUSx~CR~6C6!DWz0wx`4=Hlkv1yiZR=bkM(>RvNJ%d>BSVvyA9ncPl6pfY7vLB6>^n z%NmJgXesaQFd|xDn|$MPWA*4Y99!So_KrSsGSHE*-?-5|RQn-Bkw*Qx4j0~0gH*K9 z;2uCfhk0qyyLv+Mmk=dc-ott@tS8#h!dGFh`I}?lSDyjV|KBe6E|0!}6QuW#85waA z{Ti9x{|u6e=&9^Q$18ozEdu(tnvXy9R{A)`9`mR1p;mF$5Yne};V93SZbLM@G^LD4 zqm0d~O~Ilel#wEqEFL0!HwmjG;U#QlT(06UNwY9f#BwJsN|UDC=@ur1t30f{`op98 zh_Sme4C_q}o($+3cS!y3|O6!cX`x+!$XunOvi>XlVc-&zZ+pe#g{RnX98+A1iwFsyAe1^|UY{YhkhM^|CNc)}n523r(H0mwEz1P>q?>!Nz$W`+gtkvjmKDfONU@uB^qt z23mEzF3t`)*g{9%$Vg7J(3RT=hgj&zHJssxSs0P;vTF>tFp$@9c0a?ynB=~!-Utih zax@*CX zb1andW}dw!S*YY-`kHK^mcOtCr&#DnetyL}*Fsn3mI6+-(39LK$ve+NU;e-vm}X%_ z<}tkUEetqB$4dPZOEHEKjkBfrlwvca&+@Sp7f6@eoyy(-zt%!We#A(wv(S}a)8h&YJ;_}Vy_FXFay*N?%EE|Ltjy~zG^Myq z>V*hUamQlsa$Abu*coobbO~*i;x@cT$5L=FbnkXMIXJQlecfTLx$-KM*}Kz1Pp;%h zySvgg+kLgv-_TbkPfE8~U%hyCUnhM=L0|ZI=2@^S=dpi2VAXM}pMB*)3#A;w)_KT6 zEobxs+!R9P$l>h0n=On;KIHcvwZbuZ6~lhaLNl!Jm~jc1>Z(%Y+-n2NrIE*_&yX3| zQ_}5%R+Kpm`020`@KcQ$tdnP~H7#qh?RMB)M|NOCKWl5um+fftISV859Ogc6VIW^& zpCAoC!icbFUQlXwiNtCiT9E8 zSw5EHkaS;TDO$3&zqIN?e!wa^Y@w88T>pM$p^`N@b$o51mQ6WPe`BE|do%Z23th=i zv3TEE=t+;W&=Cu=%tBZG#n%6yg`VW+ zGQ8s!`tlQ&@m~ug@@aNXp~89ClmhpSw!yplg%jYfwiJKx(nKkrXGdPP@>xEXqENZq<4b0+dW%%e#bC#T%%<@g z)>@k6t|eZHg{HgaDSeQ}ucF(0Yn&e#_G&7hZfU%pavjVmGM&cjhsH6nl(YWJs#~kA zbVCTLD`~BcwYHbm8Y-WDXswBI2h-XTwsq6cnlI#1R%!FlnvQTbPAPo>tr@{a*4i~3 zo-LJ6KeTqTa_^$Gb!?#ap?Ugt1(UPARcbU4_m|IHd3rhFQv`kBgo5@b>L zK7+-mP+L0k9FE%27W&em?J*XbiaA5+k7=9NtKJA}JDr_vobu_FwkIpsM-9tMX>CfV zjz$~Ep+7Z*PMq~LQEA@1P}5n>=U8jK*i+6^KK;S*9%Q9V|+(HP+W8_~MT0nr@+J#yTi$G8L>97! zR$Cazo($v`3!`!)gTF0=Dvfbnr}P2F^$P2Kg^lYd!5ZZ=Vis$ya?Lk=PUVnZ7ph}? zEn#O_A3`@uYj-ML4`V}}&K`1?wI(=@?o~eh(Aq=F<>qivr2OVa`gz?^*NQdp5R}u0`@7Ndz6dJ z`8bfBvmFFJC{OuJR>bxbOceYB<@SX)`7$jXv=ImyWe@$(LMdCZV}4|zk{Rr5A6tkw zmpR{lVxc2%;eh+pLRY@R7Wv#lU!Fo!U)aLn`in(9WT83b9Z-4(m}(&>k@swS^<|ek ztb7K~_WD7&%Nh2stmPlAaWmk)Q+hMi3pj}#vFbmtxqnhV4O9Iu<-Sk#i7fTsmFlu9 z8|heOsO;FkD}9{Sn$pi7*4lKI=(zIfht^!}wnnLBBX)RSn-hofWPOgBNCNX3yrkAgU`D;j$kVmCBd88?+~jMY9$DI& z+VxNrc@O!u!t(Ihpz?~fu0W1D&T(5qhl`b_jG>P9X_)Hx&P@-h*W+AMVb#r)RA1{U zR8K=2dkw7mcWlN++NWWvx768R#siei%=zadK0eyu&o+%+gPY%2g0@%YROLn zdhIN9GcQcZMXaH|`m9=3k*Xh=pnJ5Qq{VlC=M+5IPYi$h+ zIYRsNLu;e8n}zEFS(gK1j8zwsUn%s)hLJ1WBgMldt=mFSy}=3?Wv!jTB8=BQ{m|MJ z?JlCVZ1T^wu?cwzBRH=r)c$OdX_cYMMOQAE=6CJ{>$*6$yWr>pfIGlDo7%A5Ijv%JA;CQ_u*CJ*<7k$ohO-yYDcP)to7w zuwxVFFdE-#p_B^J-jfzOatpiYb_-p(jFZ&UwxJ_(7DwVU7MfxHsMdcml8?Ej*)M`;3v1?AC7Wx`-r)Rl3Kj;}ucP1}|D@hQkY5_ky5WK({-swS5G8wNF2+;WxE= zfYv%t{ViLELJnYedfP%N-(?ql*Fr5nr|bO|Iz`|T67P8abYglQ?H(BWWia31IHJ?gmYhGF9Yd(D| z)_kN^s`+56cDym8QPRlP)qD(9rfI%h^Lb24^YKSx%?A@rHE;VjkDp3Uqor}xQu8Ky zYt5U`Z8dM=o}_sbw7ur-$&Q-$0y}HoE$bQ|O1)1)z3!U#o_cEDyXmcY@8cBBdk1|r zFY^0qUYrk%_hD?UmGLxK^AdZA=B4p4%`4o~H7`_0XkKrgsd;5MO7n_tbo?K7)TN=` zSj{V<@$q4tqOJ*f6E!b$CgBBjY)`3qF)&qg5kF0H@jX3W1loHmlwA_9PxQ7bdIjyW zEZ%^2-ciLr09cn)s??v>DDhe9nCnTDS#a;1-Y2%kr zVo&@mO8lx!3%sPc9(*-k#u-IuQ}Wj}S9Sa1EyzpgqIcozkmfq;XuKnNg}R74@cx?5 z^^lPHT-PXB(1&?VbWt66c4R)6E1hM*5OTYOmb=RQ3rg{Nv&`R(KRsnWPpQ3SKF@`x z$bwSNRI_!??XcQc=JTvIQ0DUtg2z0Kn7LBtw1xE{GN04^XqnH6dA!W$tT;*Lb4r>b z3(ls?S9H-}h)$LHoLYpF&%uffUNYH9`86N2w8T5??Ecwg{GSe)k6@+1S~r4@$o>Sh z(RN_hF!2KOuT&(%0=#(Ai{UvOEmiddw~(lVS9$WZolkJAlq6BQ=Tb^H(@{ zPyQb&!IcPI_zlvYM0Tl%>=~t}qS+mvP9yJyd5h!MYM}SSyypt|+49H-R!BNsxWHZx9{awlJhFwuU z!my8gDV^P@LB|P>HVA%BVI*)r-r(m3#cXg~hKxo8!7mm{Ih47-TBszy?HBxJp_bza zf49()QwaaC(3LX?|FqDP{L)|WmxaDuMEJLb5qTNmKNbe^<5Iw57DnY|7?;6u3uE$H zLQxjR9G5o{Dhm_x4noJmGx$$IFhLB56gvK3*Wg$43;3Kv^gDEAYVSXd-K zM%N8WEi9JL;9M8fwy=i8i~b_0Yhj5D26g(9Eg}xstHCg;K62Y+<32cM`U=P|FR3tt@opLxim@bme1& zZ7lTUQ-p0T^yLeL?JSJQy@V%O7|1JKz>_VE%9Vs2ER4xp2s>FAmv<9(u`nU;C+ucn zntX(?hlNS`Bw;TL)8+GoeJsq7dkIgqFjKxs*w4Z&xdXFpFu=lWxrcC&g*ozd!qY6w zmHP>YT9_w4CLC^IzC28LhJ^+42f~pS7RuiV&$6&c9w$88!eZ&MKa8=khWv+coP{M4 z_vl41!9vp?D$3jjXlk{G{h?7=*dH!n&p)Ru#-76dFs&@eY=-`D2PV;Ax>d)|VhLwh zC?)p|4rW@Yz7-Yhkv0op6PPIdVVYDhqSv$AmXnm?sYt-eh6E{DE+_ zg$43=!dopYl*b9zSXd-IoXmndEG(93gm+n3L%M9{wHB7h1mQgvn*K1Q%x#0FR zs_hRQu!amal*QOn*dHD$3u?Duf553Zc-X3=KM-!V5dDGh5ev~D2p_c&{ef_ch3F52 zk6DQRK=`-4>?HMuaa~m?2vc?zJ#ec4NnT#lkEZ!D1$O&BAQi zBmjKFLcHX~+&3-Em2H^&wuO1JE_2_tFkkXnZg9ZD0{K1tzHecnY{%S#78c1agdbU0 zEc+0CVqp!r5Z4pIXBL*oO9{WQ(DaA<%iLZq&>!}*KRjsr!}ApTvMk1)!v63>S)zF> z^oIplV+TjeN^b`n>xZR;KUpZ{RfIoVsN_n*Uo6yeHQ}!oI+9;l41TlFl^Y0ux6qRh z5&mJJFCQcP)53^+itsNB1KFRI`L~5pxg2Ys;FyImc|GBA3*+)OLeVfRLP8E=b>SwF zDN&l7Na$FYl=BHa3)3aPA`nC@%#be-MlH;gt0)||FiURaA}7tlZ21^rx`jFNX~Ikk zbLB3=Yzy<`tAx20=F4{o^DQipQ*d1v6k1p)%h>;mEi96kFt^0QV)+YoOD(J+ci`GE zsBK}1+(TH`Len3?ydr5;SUSsb1rO}G%TGT z_J@rWYigmCH*nR_%t9rogwH&Kh7E(a=z1Sk(LqJSVp>(5sMV@r zl0k8O^L3f~707z*kM$UYaI%AM8wBaCvBc&gSA;*((>$R?G^eq+rrC6n+QRtSHqb5Hs~6vSyS5byWQzmPy$wkUEPlyHOFbenks`(wulty$wX83DZTqR~oHE zM5BolMZC8GGJ@Z(#JdDPLZ~wQr+#>HN znxKN;HgsO}945D zbaS{1rbXWEXvyZMz(_3`$!m*T66xqh)<^|EDDOP)HD=z4&?=rp^*MXI9#w1;Rk!oe z2htjP6UqLw%95dY5EZ#N4%auM&{pb% z>C?o;I@2`R_{lTHB1^Ny7F(Kiwlu6WQQQp6nDg};RUXa{>&TxhX6X2Kl&&zs7Mxw# zHcfh?otv7%&N{iWuuW}Y4;7(&O?4OMn6O%gVHp#xtb2yox>|^BLOQ}9MYgs4^QOCqPRm6^ONTGui+rd(S>YIBa~Mu^dJYIj<>HAO6t-op^QqQ zUvR35>gH8K(Qr6=-=m%5QQeptqIe+&r>9S?lJY_+QG6a+Lh12U87hoc6ekKW%+<|R z8GDrZEux9=C1r+rVdPJA)3;RklQmKQ15T+ossumP6Bg@6)vzk!n?oh;gfCXBOil)o ze9W)6snQ9Y;p$(M0rin8F`z@G`bgEFO8u-*-3-sk%8YS;_RI-lN=QfebHl|doj*4$ zYYGeKZc|m9v!f{M9OAhaha>Jf<%c7#{z44wco&tpx5{ys&~aUM6y&sJuQes_W(&cy zPj{6`4WEOehcZ1YGI$?uuPQUH@nvDmm-Tz{_8qVT8s{ zR#`MIM9IB0kWvZuuD%^nHJoU{NSP`4oEir3#<86kQ|eTj_sqFQ1vYPp0vYPp0vYPp0vYPp0@`U;0^2CJkuccX;c-xs1 zi7BF^GFZeiZqI4vK&8Stu+X1ATNJ1o3$o^s)zlJL01do4tam+L&zh$8S z2f_j@tt!9)+2}<59FY7*yRDxCvhRudIUq-#sGkFJD(k2FPSpSPuw>w*-87m;{!YgDO(}mfy zR>`p2&YW?RDY7B`nD*%#wvW%^^s8oi zfHlYB46Np6P&GG$E8Q%?$~;~Xy4hIerXs9DgX;sa1>uRRkRGOZ^S*@-4yjZpF9 z28>}3iM)(?1HTO8;xn=sEs+`i%-vK}PDqQq0kGYp))6xYBpwEcnc3x7Q$|-4evWma zo0xHP>@<3b8864i(n%dUiU03}6H(2HwoYojg=JU#XhL+WG=J1gE;Y?nz|pqsQK5sQ zed(YkdtLnKNcNuE)5Y)Rck{JpPB=&WkwY6I?+hGj4a2G-zArJM%IZEd;zO(Z+MTev zuipu)`_81*I-NLczGF@zwI^Z){H`%v2Ycs;_-C0kDe}hA$y&@X@!i?iRXN$++SH6W zG3@R^W1`{v>^;wButK&~2|nB6gy6GXL%})>dAkvOw@Pq(OA3mHDn_p|aZDxJEY znKPtmH21TSCV=T%D03b!qhe-vgU^;3{$p_IezwvCc4Yxx-1s8N{R2d;90caRS6)hU-w=j2lhv$H=WY52y=eYhDPdA1P6iLIvn_Wu*QGDen-pz!=4A08ugut4tkJ z=3=d3FMEaqqbrM8m!kk+0D&kugmJFDP_{Q@JuW`M2>Vely!|V^w>~P+~ zyMo+QM}|A+sKeB0Sul$^;Z`{^+$slX51HX^IMCuYIFX1tIoJla=FOV+@pC{5-35_V z-l|bEO5v}gx(OK$CEq{_M3lE`RKKEKmF(|8#4f=>ia14dS@uEvNi>Ho-PCj0=jyT& zU0QG10u)atVWqr;N{N_C`N>vF-T+wozpV|D-RP`$!3jC57IL zKWSgl*pgc0dwj7$&GnLByoo8l?FjX?R zUf55@p-M`^BE-18k=&ox3|5@5I8N9zoUnPFu&*K$w@UU7zx^ah}63nr7h zlU#O)TJx0tQwBvEk^hW3)PKv&cfc327YeBVk(rco9M-crlMDdK%x(yb` zCFRmHx`F=J(Alz(Qn(bTfbo2JEs<2lUR~)BsSuUP#tndUh*I)v<~bp1D%TLXA!;dK zVpLv;+R7Hx^F!2LUQWq~%IpDuon^EPC{U&}z2$4vi-xGLTtvy3$~+sA17&-nxXQc` zXtXS+WFnNDm(dNMLr7Dskp=QI<|Mtg27pon zCMk6#BB*7+RHeQFsBOS>r3Rqd>liQ_TS2ZvN!Y|5`#oMjXJ68+vCfrDiQDR+T{2A0 zh{_x-f>W47hRK;-nd9PXYs?`-?}Rm0l5sII#H;{=(?Yzd5@QWqi!D`Gafti;B)wmf zK@(|etosqfej|*{DqjaV>BR2mLFB&U{7fJAf?BAQm7N0Dd=8fI>JtTy;CadG(- zG;yG=5SN5nUc4<#ED3>+t@g|BqlxPvvA~*Wioz}}kI^(tEH8frgfVe#braWBnYg_C zJDRu;QCw+F%z}><}n-CTCT7Rt+G}3>4@3 z@+?ZE;WH*Y6`7{Gv%CbG3E~-u{sxUeva++$XXZQgVC60oU~U6csF@BAyn?L6Zz!2a z%*RnCx}(JS%2FPH`=REm7P+_84W+$?|5ADmAimfOb28BphE(Eg2;(D#F8<(6{{s-J zy&WM$I!68PVJXnisKjPNkRg+G<-rRf8J z{DAbOhSr?;7ltA{V@0k>@>j%J!{8|>^KJtjp$K-~M$oa3y{w1uH+pjHaptfzB8xjs zN886Br%s`HB0<3#KC($f zc&jB8EN~#-!m0aAeQ;isUMI*DahVIyn5`h{-OUp0^5!6?KCetPJX54WV{h4?oL{W-v?mf z8J=V_!n12ecv{6~VYHZOS7-x4M^C~bttSo{;rTezZh&|mGlw&C95chybLQbvbc&W{ zcf{yyW-exCc(%?6&(^iVWdN9ake9d=hbNGdcjADLSZu(bC>bUPONB7U6=}~ghm6{s ztRf{DbdZ>Y!|zCy`iDVB$uRoqSPGaNg_rL@N6GmAa4^dKDwX3RtpoMQaO8A1xCMmV z-2^W`y4-dg<3+xPRpBhR=u{x7_lrs3yvzti6%|8aGLckXYur7lR5IMnD^g>RvZ-4=8y~Qz7oJimFa`As(z2 z)jBuW11a@MD_lNW+xJ6blbfVP*m>Mdd`vrITjG-})uMXD4KU{jwH;Ayv6_v#;7ZF) z(jua|+jX-c5ipE^HehX+o9G2zq&L1By{9UwpHZ5ZLZqC?z<&6Cps7ZQw~^&@C_Yr` z4DLNxs28lKwTBQ!ro`5oAP9v$yfYkNJq(pPSh7GdWH zH^FnRd=jx9trpd{uGutE@k>!htY#4+{~7NUK_0e0blv`-0)`RL2CV(#2D54HXlo(< z7iyuGbwX!69wNN8sO2B7dlRJ8jaWPU<>s1R_9*;g9|T&&DQ&SE;9Fr~r(WV_@_Z>= z)4x2P`|b?;xpvvO_)$hJ-0TfmuFJagJT4SJa5FnY(RX=AFY0lD_**Cya~WmaX)|jq1!3HziL_ZX zL57*8_|)3uVC%+fm_vrq*;*~;!8+EvqRQRKGrAWeQNt63lP$we_*L^F3Q3izWt zxe*Q6qsYu|sC6wn6`Ac275QC?!a1u4x@51S7%jr*z@p$rYR1r&23Pu&=qy9F6Cm=JdD8{`KMSfRVr>M4XJ4n5vtTv#9&w9Z9RQ8Z&MOmEm6Kl|rcoA&G`fwF zVVbLNWlmJ2wPy|)CTC)0PP#}N#vC%T2jJ@d^dc6{wCVCnAy1^urw|z?XMJUkFVb#g z4jGPIP!SYizLmdp$4l}RW`f4+S6B7I%kmaUIjOS{i!D;}DEh@E7HRn>YH^80j^v%X zr53qzC#Lje7I99SSK)SmFEtu%e^Es^OgEx8T~-l$7{MT#6%~o0jE0l`s*0LD!35Ou z>Wbh3YLb6#MR@k($>4^HBrQVowu;2<)a2>t_E6KFj_wSRIUU_x5j;yfy%51I*3PZy zTX$C^X&;`hs&KhQWxy~3T7>P56^ZXaNlyBkszr5QMUV(!jr<3!HJ%JMS0rfznp-Op zEg)e|M^9Eo#naJK)uP%`5e%iBYZ?jhxV1A8GS5^bX&+H-sBpPGY``!AT7>PFDiW7~ zlAPvWt`^muMo>UJ>*J-<%5$ zS!+BOd|Q#E4QT#Ukr+iye*F5EP}58Z-&X{SsrebCf3%uhDE?NFq(#K>X@zUv4x{6M zHel^|MX()|Ik$5DKo_)p5Gx; zY7yd5`6+iQ?YPZxA0ZV^xR)TFx~UlLBc4X7#4=E_23A*1QYVH>!&I<=n&em55*8qu zW~n4CLbGiu@c}hCTuur#?Ql6cMB0h;=-*Ye50P0wwoC=bX!S$XTWf1|Dh5)ARFd9M zgAGzHpQZ*3DxiIM>YYlIfhSMHz&NE^jNMTO;4AWbT5HeY(MR7@k~W}uS}JidHMy1> zS`{M)&#?c*IJ{bn15&|VwAvddra{(f=Z2UfQ)aJG#Mm|EJ_d<^K?SrAPvcUFS3${U zy@i-iEylA`!4Kdo^2bhY%op`EsaeX=NOr(-@4T-Z-?gY397-2wXaJwj#SO`kKiAByOp*745TFy@e zcY?3TUudnZO<_(>C20eiSEUlWsmXzLb*QO@iR#*FQC*e_zM`Fh6S<( z;pxJZ`wysqVFa`Y+qb3?S!t*YcAPcUqPi&+v;tqn(UDhMYwyATov9>kKyyPXF&PqO zfZi8s+5vihh)|8R`e3yf*QNsgq*T3$x$Pcn^*hiTQ%QP5j5nm*J3$2uDxiIM+L}si z1!b%~SuMsbso;I^)oygh$E~&VQTnG*;!tyEDv?McMlMBnSH;M|zsE)u#`sdT7@tiA zO`xM5KwQsTtNA!%?oB1>4KY5Fa=SqyU{C?=V|sWel^6-i#JE3I%9R#dSM5s$3u$c@ z>hY~`qEL&_xj#rHX#<*{r4s9?$%*BQP}5EJ_g zL*n(6`#z|EVFa{@nmd|Ga1%ij)z8&x?no-gN{6+vn3{gDWnA43Q!>gJY931^Dj;Dr z|E*R#f2M+d)VvOZ^>3^B112QVC`pT`oo`d_7*GKn2eg4WqK$$_Kt;Or=^^6(2YcrM zCPlIC{jTn=nd$A>z%J~PVGxllu&}dXz-1Q@5s@T<0Z~!Gh=`a06Jl0GMMcDf9>tt6 z1EM14EJnm|OviA{9>e#0t82!EJJ0cY@44UozWZFBhuM0o>;He>3f)~@9sa${!JOrc zMyx_>sl;fkB5S$oFZ5BdwY&#`@28R``ZKO?8ESMaRxTuh09y?&qdr+ewI1bIATuBKOX5}HX*5AGET zBgo;sf}oV98#}Dg84)1~&2xwJ(mlv`&jC5iBKM@WJM{{Mk=V!g3dRU>@Q@MCgeY1* z)$7ZQHnLoqHIDA3j}V?G8=2wT*!y#|oYX56e#f6TyGI~zE@+v^MwfUCdPM6M+RXOM zCEhhrmZxQ^6CL!`cTVkAQ_Xj z{qiWQP|JzENXv<`BqpzK*GC(gX*n;I#^lZH-J`5BEl2+5F?sd+s3@z2mcwp&Ox~(q z7-dyxIm)$+O(4cwqO4Y04l1o`(1u@=~?e%Up(Zh{-$EelK(N z(oxHv(tOYAX~@eMe42*q>Gl})ioyXQ4fe9-L#C9?pk`i zr=3zUXtW3@m_65(IecpWwv3K0apVmXb6LbSiu7oKWE8%q97o`03m8SU;@bGRB(87?3n8D??!fd3?ugO(Y+{( zlvckmGEA$VQ>o_)jTAc1(%jIW1;WZu=%HC!8C)wgA5rOLO=$W#S2p3fv{K6lk6bCW z#Pa+C&sCM7@WXRMW$=#h+{O`WMV5!gTVBa0yg^RmIC;HAUJJ|3m7y?#yt^`JMF}(T zRyIN2Ua9K@*_-aY(;}bi%g4DYLt%9M4YifQ7o@a|+vqqptg>_j16^qukiI#Njjb%( znJgW9xz2IMRhDrK;6Np-5#uY%#EJYbr}8LHN9umUzh==5DPlolMrtTB`V3w8ZrrNwXW? z?i5M<1(IP_w^~7Hwy>BHkS>sn=Ayg!K&7;W@4h`C7*Aee=g~u*cLzkLog&qR5}T~W zqXF*g1N3Z4xi?oi&YJ_GlhA6??+plhlg}Of&jtkb95c;p=${X0JC98J7Wx;~ie5th z(pu3w=wDeYdIkOO){5Rh|Jqv73+UfiD|-L@TWdwHpMPhq=r)E(QD_vwW7DqW7djZI!{ zR`i~ECu?=!*@BM-=zZu(^OpH116oQ?nwQKwSB0~qzV1;KJR^PGCCyARLh=>B6xO!Z z@>N@`zSiQ4b6AzuN+uc_cXS3=t0b`lR@z!E6T`4-tksriwyDxzN;H>o7VB0OMe_k8 zudXVTDB0Z`s)7V3zr-#ehgO;Mj9F?LRHeIDilWcn%%1cd4pb^$PskUDzn#cGpI$ap`3uXGHOE=H(K# zN`E8BZk$~Xw((5F^USJH7(pIW6|`;(QhXj4A-M@Sl-iyUS!N=4WR=cP%B>jAe8=)U zLA%bW3WXn@`Bi~@Gevz5azT>_PO8$g1-XfMPqE029DvWL3WX8m`BlL=g4}^a@dZtg zXIJT41u6OGTI6#~Bo{N9BIFfSfxJPkZlT1LO^}yW=}!ciu4h5fBI{|HtE)m`#OI2t zz-wFZw_;poi-j?7qe^tTl!g?g5_2&r5$!N0EcW75SN3hQ?4k$sxP z(><*}6y$1R=xO75o?7)whr$T5HXU^B2-0I#n#m$niUdEXFhhJi#JC$3AsG`#WSC?(;TfLR3x($Z_(xct zxm*W~Nr%D@&!lv4gYdjbJiA+@9M^V9>!$>{FXLxdi#(F?vu8RKMvzm}!TW;zg}U$G z1UV(GV=0iIawOTuA~$jDo0blR5#-_NpgkqjH}uyL5i%h@4@v8KLAGJvJj^0%x8+hM z9SS4Jx#?h{AT#it*aUf8S|2OOKD77=7Fk1k%}fdC>ELrgmeK>4MvU$fj%3Ty#li^k zx^!Wz6Ua67+;4A!yqfVrzB>!XYc0~p|BdNlVI-=H(mF$lKpY3c0oxtvKy(z;z3i`d zHL1ZZX+2xm=FrEt*&1vZ%$@mkC>$VHr3=pyWDWk-G>PMZba1O6pQK+OvT7bf?cUMNztCsC$dibq$v2cKVKV3Llkn-;EhfR9OVb#Sn-UJX+a`F4-v2-&Qj&9hT>}1y>QMN(7CpW? zsG@|L$f%lA-F6279gH>4T0E!gA6=~{3hM@ZA6wm0FzySC`;)3e@kXp? zRtIMZ>nn_=vu$*a8c8djYb~Wl&|>FXOM3ORYJIb?{*CLO(`~FbGfEd$hvE&^ORM>K z7p&Vdf|lf13-EDyj`a@EOReRq``Bl%u$HIp;yAa=TE3c2i(hFit!`!SxXM~FwLh_4 zZ7qrIqG~+?&+gZ-FSfDClcU#GhY~Zft*8$6k=T|}$D1uudh+^eeTpDU;J?8l+km{a zIuu5FU}bgiHanW>f%`V=f%`Y>fd{fZpk{-A&|03_l_SVQ*5aWCwmobuM1`7CWu;Z*8=#n0V#oGz&6Tvr`RpU`XXRR>+zsPA zF7H(9;ld-O-nD%=o1@6b)uHgi^JR4~MR=}dkN$gvbfxz{tJWt8(j)(Ki%c_Kzo`y| z5#&FrgX;xZJDg|6vPjNr%;>A5s~3sj`)a*jc>1v)|7dxRpmkMEDE#mQHNhs~xfx_w zW6piPM4)T556CTLW4tChuCFDduqG5nkS%J0wq&TSw&%7@g!Ba2tVRzKeGK)Nq zjMg=wFoNt<6HFCk4Y7BQkQ_VyK?GfDeviF)D>7&)>5i3`%ksCT(y$1RA()u3>cq-tQDxkhjCW0R)MO=MWeNNuZ-jJ zFl!~%Ao_W@wF=dEwvDistmE~f{zTfWiU!G}sI9{uRYIK4Vs=J!}LoCm1j;yn4Lg9z! zxSF6hB@#o1j(1MT#*^4-=TXjywkPE_!cjGPwDA1MXg?ZNduhENzXAx(j1(xS3GS00Dg&&@aYJ!JInRpg&7SEC<@hq&-8-=Gk-Lc5> ztYh}Sv?dgOj;+_#1k2b_ReM_PFE!b-+xC>d(ORxbvu%a7JSE?LxXD_+dX3uMY%Qd^ z*mjGxVrnebt=5XG-LY=7Rzgk1y4_lV+KrKQr?o=0FV)%%sO3kU^nwp?gCb+ZlxYiO(>Dz@s*mw-Lf8EtLZq8O!oRY_}E}A z#)|(!O>n&M>`9m}Mf~oYq~EA17Jhg()fC>E<#~TIo)5A-rXC+!OJ*K#*90#J>lqyB zH(J&g*e5@#DHd;(c&o|96n4N{oU3ziuh}5DdXuIYq_RZzOz=; zE8knInVL@@{a~$9buQMA)+$r2nFal1t>$VgtbbUmh3bj*v$e|A0IXlERYBaJ)#w$( z=uTvZ{M@$towWOJHKEjpS|nYsqp@0AE3S6MYHck<9@rz=T8p~|oDthwt3Z8-)zMm^`W&m1 zwUX*Ptj^XdRKH?%u~w0aG1j_Tt5_9bb+=ZDD#z++t!An{R&Q&Sss}jJ^s!c%Dq;lo zvsQCejy1qqE!8$y)z)gQw#BNoRvX&htJPg;S$91()wM0>(cJE0`gLG!D1E{iYFKS> zw6y(5x?*^3_6#)!YlO9!C1Z`U7MhA!J6p>)A9)*7+h$+L_{N*(Hq`1%#p5B&7KhYE z=azEXWNd9Hk#Gc@R2w`a9-rk{wR^2OpL1ki&zWG)$YQoXn(;B&T5`VFrB;6_tSdOX z?phn2>mMe)S8XWXVBNnqNN}=LZ?OMNi;yun*Y8uSyOZy(qr7G;6WugvSNe^3^r8!Rgl0%7f($YsJ)0SZ7*GVw+Q|<)sVveqx(vW2>MQ&Z-S1 zW@5XbHn?44E5N+aA{})e^}onkN(~{li><|8OM@@AmZv5FzQkHG6Fj$8za$>Nr{&ML z9(~61WwoJ1g2$_BgK{>i7L4X=EE11c*IJ9QN3VBPY!BAz8F+TrGddr( zv2|h2^(5^U#r8sNuu5VpWi-5Gk&e2Cz42vhDYX-$;T3DSYFkFbtJY#hNPE9#Eg22Z z)ap&*@pbC@ob~t~E&Y0JD3Q<_@74yL$x!Wy^*xJp)FoK&TT7`6@bQ7QT$Q9XKeU#N zhPP_Oc3r+s1h&RSYMNLzkyt(aOt`~P4qY4J~~zr^+oZT2@CTPJ3fKh}m4GqE{!!5$1Y z6PsHXtqD3xV)Lw}l*Hy+%T*Gaww7mNi&-m*EpDwSwuH5!*aB-wY(LlPIe2zoCAME} zY+G^s=G97xnb?}u1-DCV=P(y2vq(q1$E9g=YbiCAIa9f{q{j>E^h?6J5!T|m=omkS z5!FUEI!%X0y+t?NSJho@&<(4P{@ zp{;sHNLS7kUF-A&LEb~Fb+^cwr2Eu`!U!^57c3WKil3TX1OXA(S&REE932K(i(?-B zI@nsCx`C2IttGKm*6DTPaV>QiU_IW-9<+U3D3RcCR9&!9JZ@lIkG4pObwr(Z0l6>m zGtwe=t>-*j7YZZD-RpuOY*beSEzb%#&#WsJeoD-&(?ci`NKk<=!hK;~;elE1i*wwA>N#&k zmdA@~>ioLkEaBb&@&e2KJ}r4!U9m92b5&j8?ZP9-Yb=uICaCLmO=4VH7rZ1qt+*mu zW_jKreSKZA@Z;&+I{gu;K!OT{5$@aQWrz}EdDQlf2*owa&J2M&t)4QaKT=zqA~d+GmMY%hLB3*J{3N*s7!T^Fp$dVj4k!PoBi~!*5`ai!QbjaVFdYoUEvpke2v^6 zZNKxB2Mzg?wUjyl^v~7;!HD|BS~@Xo+<50#YsC_yhd94kLmKPrx}X_H8uv1~`r9Zh z_j<^jOtFN8`*@}>O$pU)ID;n>?Qo7-K=}e|$wG*i2_^|oIX^lRP0oAM7|Ber@KfTe zI(-PKKAOz^NEFXyn* zDMBhiw$12w1zE;VdyDJ=OXo}|j39ewf*%F>KEt_B6J+;{Zo{7KX4u%%B74&7{W762 zf~?5|m6T8;xFD@-677JD-bIj~Z~#tQWC;iCftgSkK@Q6VhX`^F18#T|pA8v(t{}If zHHTQ_Nt|m&WI|yCIW`kqC&(mSIzB=sq@JTP`Uyey;AA!0BCluCFewuXBglO+!54yD z%8s|6^~s|vupeM!mjmVGjBZvB&jEU zT1stV+pNs*3!DdK^Z~-!hL%6XvX(+OI}?gGSWn0VbA|OIYCbp1N<7D8^p%1Xy@BH_ z@;CScEPi8sN$&k;K%>Ot32@ zR2NPNk6NUoUWVr}YbiAb#5!wv>LgnF32XW4N=mM`mUw(PqvejFJB_$jTaS;x{ZuBD zNbvY#Cb&sFu9JhZMLOy_+Tj&zDfKnu=~ZjVGVZe({j9LQ!M^;wWxX5^8#1AIgLPvj z=mkjaN8fMCv7Skp_j0T+vhDpWt4dM)18Z@TX4{9>;-PdR{;Rd5R&QqX&J=ei)Any$ z|I=xQk29gfh5s+9mH2PNc>cRZI_gubudSujH;m+OtmUe8)c9L#d8%7IQ-5pmpdORu z@2w^NKcoKQ|1%gqxBlOy%#WE+;=;c(FpxVf>O@+|9hjZ$zeD{!YbkXUd!}zKY1N-I zdTTK5K45;etOM~78yJc=SPKURCktzedKBkazrrfXvHk?2S(a7FF}&1Tp6Wxb%Bwp7;K6 zKv^Z*OSC-s+*Zpou^qKMi`v;d`@KVzdBJ0AEf1M?G0%AK5@l_p<>}F`TAudouI0(i z9_D%Pc~xbn;;*NchcNqSd7!edmWLzznP7`ZLL^VXq18~E&Jg_#xy!z5VZ7R5pMKS7N@4;+d)C`I=c;oYl)Vdw@bC$ zdc8u+ZPaD4kj-9=p}JDb9nq^|rmO>{Uea=(ZljjFZ0~BhN481J9j^Cc?^9@5P1#&_r1#@;vuc%>{DQm( zYD{~rMJSmg%{nhGYo1Seak-Q6oR|EGBC58mwQzfJxiPTOOFlE00a{!3vICcwycm!5 zwI<@9y|}Dj|LVnMQQ7h1W);|v%aX3^$7S`@^W(Bm$#(-~^-yE+C+5dxEiLZHW!Wm> z$7L-kz~WDVAD5MtkdpjK`pJ**-nz~-eW4$hHHacVE=vf-eq7cAO8mH7q&M@EUsG~? zRI=2M%k_7epZt}~{pw7(&HcDsFqivrxgM?X<8sN@(oY5r+_;Nyt-xjQ=f~yJs*Rs) z&bFtbZEgLyT=BH?<8t}Z-jB<*NC!XJfg)ejmE92M*yG1#24C;TWlBESPj+Wp>x}W< z;KyaQJ;YBAAhS!xjESLsa&V*LY!ek3<|jvDbtK308fktc7AH@Z&NyKF?1c34CP6G}ifkTxPus{p36{caQvC;3v<-+9OkT9^o$X z<1)Ry)sGLQ-*5BdbNO?-pS*}7Cr2!I`0>Zdywgu!N#^-c=3RbVrhRw&$rWT?9%bI+ z$7M#h(vQnD>s~)DbD#VCxJ*dy_v12ycmRt(5BhOApFZTrx8| z?XucWo{P2hz-Z6#lb2$38CbS}U1zNym(!1f7XiuMyGv4+j+1m8M7@L^n2vHB@D>c4J{?#J&i%u zu_62m`5?Dx2!0YIFMM`u0^F)Ww;f60+Zd)>Tj2gZ*y|fYAq3d3A*iH8qOsBG9|2wQ z*ttT2yp1Aafs>s9&2rbK39-ua&FC72(V*)D*{T=IVivi8alBtcD2yNvZV0B3QgRFH z&@573fjcZR;&K;wT7y1GXbz&#ftIE@`|{xpq0l=m6K;9KYoxUFuA`-=d~KTD%qprI z%Er>qNi7XpucdK@XsPLNGsD=eq3myfN5-WNjvJSNd^Z|XACWer?O>-!JQPSq^A)|g zebpc_HH$u_$~W8OW2og0Z95tg@13EeIH;NRw=hGdA2xC*N`$@nO@{RxK1;&A**98- z50P%`lzSKk`RQCi{>*`r4_gnXX~MOPN;kZfQ<)dmP;Eav4i+5_pbuhB>65gI_l+kG z%?AX9#qV~9u$T`Bh97M$Ean4(Ve|pPQu%JN;j>iO4L>98g@>C;_MzH3oWO9Qk~260#45e+z`E@{ zn4+-(C5tfH713^KVRPDbpe3s%B;}O0m(xy-Hv_A178`FRVfr!VlDJMG)g;W&8o!?u$>(HyAXWF5$@zzPjSMz zkP&sG-)1Wu$M^6H+ng;Sz2OzM*ud)LVsEc80HiS%dz}PO@;SY+*fSB9d`;^w_T+5s zl$}hwTP7v zZlW{1+f})9b%H_ZD1T5P^Ahv1$J03qZ0E7iPb+1=sBAx_9DVH3esnouKlW&jP{Nw~ z?sB|`BKi+IGI0C1+E2D@_SNO$=sS*NKE}3^BRMAc?vBa(G2$(7zLN0bP_AbamRW>uBBY* zUvL-qk0t5tSS0efUN&3`v;g#aI+#3zH!rPDEmfod%vG;mic3>y+W`S+veL>r__3pq|d#`Q}_Au`=emi<4 z)I8;}{O)w}j)H9~?`ayKv-k4|&f(sfL_XDPAZI`C39#$D5tM(zn*{TE?+$ABq&JpY zJmrmo?P>1|Vtz)QO39vR^bu$;r8ZK7-aJM_6K$*1tswg-^)kiJQ|d0->UJ zuAokflzNz^yHKe+@OqI_&k@?i6rp_>&DAG4N4V}0VOBf)*@sb6sP8K3N+ z3&~JT)E8FS&aQ{42iA0rf~<)$wO19s>a|iuXU@+}T%eQisv}!R;6x z2c_%B`f3^_$NB1Ins&UeDsa0CH?nA#3BG!ZcHI@JV~LZu=xNhQydVn8Zob-+cG=xm zUr%Q4>Z^lk-CKRtmynukHIx8bXf+JZqqXWu@W*I%0&RAzR`)R$-qdPWn&&O8D)I2P zR$l{uN2}q$H)^$-4trOt^ZBz$tNGOLxwtxlaG#H>kdiONRg73(jH^O|cqy(9q~%|Z ztM_pGN?hFn=c{qmp9Xm?t^)jRh^xzCSsAJa2Irc5OVn?) z#NZ|BX8;XLRLHmWg-VZkME$_dGvyOCg2vkW z6SbB~@AHW&hGpMR)YH^`>L;onZuk2{tzy{h|B2d_%mY4gKcQkXnkk2efvC15rct?> zl6Zs`I6@K?G|VhXd<^DDNlYiM*^;;ue@98;HwNm_l9&MDF_Kse&#{ttj|h*G#4WVY z@shZX@J^7#Ku~ieu^eA>B{7CN&NB&WIgj-!_cVN+D2cxG-AR)84(5|3@eNfuMG~zE z{!~fagZKH8=uhjMCW)@V&)2YtS3^ybl_dy7G&dYHFBINZB$GwIe-iUGB0)poR=D15}F+M%xxT~pPToSj? z2nn-^S_G1~j7}|(#IYnoNlc`0QW8huv``X{fs#-Dy6cIjSP}#1f)YubLWeh##Qyjy zl|(%Qw@ebf39Pv!7Sb9mB(V>hBx-kiP}tm$qT~4ExKHDqFZVm{0xIZBVhulvUF!-Z9GiQtW8v-rToB2Kq%#ZsF_v1Sb>9 z$iAOaD9L=l`Hj57V@YU7e<9nK!aT8yWSi|B5_Wr|ql-xgJ*e&;T_n4O=w0e=F%gxF z71FHt40s1vY(Bkk&vr+^8QbL%l4DKo=Tz^W{Uqs>e>j{FFO1C-V0VBQc6?s)D>@RJ zKO>Yg@ett-Mjp2RR zk>dSZ(Oa;^SM$dk43kQ?IzY0bFHOgy8HyDTF`u~i+cz6-3iyKvB`YKn_m3pgZB+O3 zC&*rE6l`{>;mM_jyS;Z2MUwC1%e%V0RLq}E`kJxA>J-Yf+?yKnN02wQv*h_bB{@)t z-MvZfFPZLWQU{pSbW+nysvoK8Ce@16fhN_7)IscX{Cloh)O5AQj8M~b4^dT_;gxbo zD2P7iT@cOi3ZfZaK|%|%xXI_d_=&mb#4 zOE%7vjZuRaM2*}cYGg9aG*ISc=EBY0@o*Z$H?uO|%*uQ-EA!2)%r~<#-^|KxEAz6mGMR_0}AWnOkx z=4EGPUUpXIWoKnxc2?$1;J75SGA}zT^RlxtFFPyqva>QTJ1g_DvobF`EAz&1vXWVu zmz|Y)*;$#Fot1gnS(%rem3jBzU1nuoc2?$PXJuY?R_0}AWnOkx=4EGPUUpXIWoKnx zc2?$PXJuY?R_0}AWnOkx=4EGPUUpXIWoKnxc2?#sv9mHSJ1g_DvobF`EAz6mGA}zT z^RlxtFFPyqva>QTJ1g_DvobF`EAz6mGA}zT^RlxtFFPyqva>QTJ1g_DvobF`EAz6m zGA}zT^RlxtFE=Y|CbKg47`2>JUgA`K&gOg;TtPxR;R&SUl3})7m)(MH%EhupGR#jx zPPLC^Hy6vg9GH1zzLCw0JMkwaQ(SzR&8%?3jilp}VYU<`tn>Cx_>*jr46~(kc1w{H zHYXjIjHHUE_U5nKm(zKWiXP%}-1+-+4!4%?-oUoP$YOD(u*6H91VnGoT8~auNYwgD ziWH?n$#)XH`CZ6=(+I`*C{I0#>5iPrN{8j)8z=Z^o%8V*2-^PcLzSjJ1ft)yg4N4fzI!*; zw$_Td4}t4rt+-nWXJ2b2+{FiQZ{1pfo1jLO)+%uOv8}(gLibiU2UsiVj-_OkwF=#H z@K9~7VyDpED)kbT(a(^*b;`U5qeIAQQlYd0wQWdUSwL-vz%nFd-k{+UV<^^8YbkdQ z{)Sl#Q7Ndlx0dHl#~N-e-@Ojp2#- z%)L@=h(Ru>-oTn-E#=MxytlPncP9S!v6km{#@g3fzFUa3pS5D{OW^jmR@{9F&I7EK zaC^|?)2tP^3&BmdR)KpDxC5<)Y$DqZvR2Yv2<~8O6}tT>d8oCdwv$q~QW-slLc6Cb zq%!&p(ubu&X$5W>ADud=klL2fO2?+!&WmdM9@cTzQtscdj<=TUevfs6wLDkhZ;rKm zH^iE2E$z0znrE$;+YQ`_){46w*mjb&67Do=bh5PqcR3|bu~vb58`i1T3f-Ns=36W2 zK7e(awF=$Gu@+dX$bA9pbZZs6@6y(1SgXVxj=wXl)y!Q>EN5A()SXPpv#nL;?oN}P zW3A@yCUECjtK4<4&bL;D`!l$O)@te2(8w29tCc$$4~wkT+C7QLF0@t~cY8csWUaRD zd^j(*Ry+4naFwJK5F!QN-oOXz7W3{MIAV$JB)Q+PR(PxQ`qt8)G}dMM9j~oTFU85KSkl! zQlaEK3E{t$|K{uvhjC--9ZdHaBH7fG@dLx?o=w<)we8c=DW9jjH&fc<>Q)be_U%;5 zGD%mF{x}u3BpsbMCD*vvi#2@G3GvzW_soiUzNb>bWUkg*${EmUB@b|UC8@F_$SNt4 zGnS*w4b~1R&hWD8AfN2)m}0cBmS-N=N~O-Gu&;{bT+~sSC${QLflj>7$q>k-R?q;Q zRgoON`zZ5J)&x_apE3_+?V7rc0{vBy9P#Rvc`EC0Q=mbar>|zFuEWI;RU`+AWvWQV z(>2OGb9GZ{A=v9xk&K5`$~=1YfQfarGLKt5Xo%J*^Pts3scuwhEpLcY+HuYER_jdx z*ELUCJ(-f#AKxvK4xZS(-lgK21rt6h!M;EH}uV=#p({Wi=X~e$O7PX!yGxAn6Av zul!HxYu8`S0Q39-l=J;V*&6e|CnxTYp-jS`$fybYVoDbH)A$YjD=3rn-=$2U{{>}= zQ4pk%pYa|el;XQ6_{yQgVSjtzVt4kEOtCh(K6Y(OK;h@Rl;nl6W31XGlinA z&}^^UHUeMB23ZcE(PC3c zlf|Y)Zn3E-T5Kw5ve=Z!EjATJi%lgTb|mmfJ1&u1Y~mrS)dW=(EjG1_YC`5?WL6|k zAofE@xqXrez|-fGRyQ8aj~ah4+3HEsNM-ShkO{w9`NuG%)MadqtDE^vsLM`d0H|mA zEl?F~4OI_*lWIGD`REJ3Md|>4i`8-bmZ-Z}EbORy9_BbHb>o5Du2YjwrMK0)bLnQ) z8lJ7yXGb|s7d34rPcA6ASKdtxBDU_T6(xJ93n_*gVT~F~ zew{jk-;DYJwtAHWJ6LVaZ-ZJvog3BV@C;FR^E*`Cz#8x{_4FxB4Am2}nGmW=@wkIJ z`B0{VY6-tPs=)^_{ZngctDV$a{Ekw45c$q(AnDO+0>5L_8`HTrrj{Mgq)y#JJmb|G zI(-+lKWr1!S$LVG?xzKIQ+J%ioJT#u?;h$Me)m-0@;h0DjGw(!ir*b$6+& zi1}`{iT=GueS-IuY9^?A)lc;DeQG*vtJE3%u2w1PvPRYN`-mFH?^<;*zmKXXV0cXR zCFaM~spPCvztL__sE)+2UTs5*J*n#XeM(K@_h~hg-)GbW;(1mb!bp2gok%U7S2q#= z3+fquUsR*<{*vlT`ek)A=~vYG{JyFt(*m!l!7y)7|DeU*P;K%4rmCk#Z>dTAzO82R z`;I!3-;Ju2wtZI>5&tIj9rb-*osQoR)L2H>hw31H|Eg{v=Ogt9zaOh3Vg5wjMEsws zsqlZMPNMz)rmp7qbG42!{Dpd#-!Iiq{C=g%K>b}Q;`~~T;P)HV50Brf)%f~O4J6v{ z)puZjP{ox0Q4J%KpHx56|4={DgFmZJY3*OsyZHK5O#}OzcRIh0@_N%HN_ia_?=BzJ zpH&wM!AVOulhrT9|{3tdsByiWXSuDm+_v{2r7{*){4LYk#Qc{dYMOXdBYfjnAy z4>LZeDDN8%9D6J86QbTnc`ilvRo*f-z&93IX3g=qDcQpuFw*GY1b0s<}K&LCJaCoT3R%R9-!GKZ%Ob{U<}swo{b1 z5csLedx)_zUwNOwd7APb1h7DP3+R&5m3Jfoo~68LbivumdyP?hj`E7|aIW&^0$-@S z!>Hc{%9}*Ei)dEb`a}f z-EoET+K{4Q-KM9z@b|d#b|8p#%Da;>@r3f)(ID%Uw}~L0RNl4Vo>JagNss;${PUSS>?S>hd-yhor!FN@;)Ta*Xb3S;0>NxTT1lqMCC1K_b7QEoY$v?oNmKb z{51EA{FhW|z`)+E6Z^<3s6~Q~FjbxIa*ScN#FD>7C=U9Lfm~BAt*7vqhwB zj7t_BPn9i_@%xV{b8of`%a4DN&62Ujj|pv4wjlApK-!?c&t?Wr_*Vf+hN*6|0_!`@ zVUDyZ-X)vK5@k8*gk+d4_1P^fQTCB7l3}*&mfgY<fl|6HAmamMGiGKxwi>>DwhrVRrcDWa?uI{Et|o zjJaE-3S^gRvP9|IB}!=pYTJ-{l>+}GmMCK^QT`ycZL&n^FP&Xg=@fYypqG*|1MG5WvKsumMCK^QLd3QRFfr2-!4%~pVPNj zr@ocG{r4|X##o{(FM+ek5~XjKD8&~?>^o9*6!@o0lrfel_YjsQOO(D{q7-)av9&2# zirZp|GR6|+BEdCTqV(+&rSMUs=TmnHZnGuImcK7i##o|!MHuW7rJTNeyF@AZP9Xdr z^52{t;xKMZwP+@7v~QCoN@2{qMA>1U(kxNdfbi`SrK~6Uc8PKn>FB&ExyHp_PC`lt z;&bxvna$_&Ple$_b07rCW3O)g4miJtP%Pi*(17c@YWe zW0?o(RH|%~OmS3FPDmY?lLziJ;(~CnP@yhc&6o9!Ibt*NQT++R(1<3m`}?V z$uL{K&u(D_^RKc+GD>9yQ-7NBq}#NAa>L*<;(Lwx-l^HQf!v`px!SRoaxY`He44df z7A@yC>;uIA?r^S}qIZM*t+=8&y&)_jAI|d|E)>qQ58|RH$9W;vq8#VtSQjrK?>OF)v$$3ixw;_~K5#cS z=;q*_oyTQPHWqN#HFP1{?|mSjJg~SG)AuBQG5@88SPO8+QT7#!^I0f( zvmq2daPKv=qkwxL4fjD4fA2I565Pl5d)MO9wC7(NLg54VdBeMcJD)M}mBp2~lPUhS zwMyMd)ZrUzmAShR!nf9H?!L-3+V|FK=?wv6-_q~J)+%s+Awr zkuhL3V@Eco7i2lU@S~P}IH|o%?@hz!?!%os6 z!gZ8>Z`Js#;JVOUZ7gm_I-p}?D16|yX>3tpaow8WwrZ>*+fNqvc>(zLu;JSg^*5XcKy!3Ajg%4b&@l?S*NWTw?a7yB=Zd@+7QPi*2;?^9+ z;khvsK5*MNJ}9{HwC4^@aE*;`3vL3qp%!-}9k*j+D16|?H-0O)l>{*%!kPVH=f?7u z;5M#!rZo1Vfcq7=eVX{&y>XP_29v#~#qGe*nA#W$AGm`X_Y>Tg z9Jmf`;%{2xe8CMQ&I2v3ih*)?V<>#!j%mDHaF5U961j=LBO4zQ+#!tDqb%+Qik#3G z3Lm&r8($XOd`9GHO>ieRekZsW86ziK+%pWmGa5tTV=W`5PiRQAX5h-<-kz7wY$$s= z097c5>ykn_z&0;7C+BM$%C2Bb%R)JL_9>J@VgF)TzR(Xel+9yHb)g*Q>I>zdHKb4u zLBk8>fHJaB4iBRXWd|E?)Ub6$W7(x3CKk$oolz*mZ&slUrlX5xQA1ZXmbD|W%Qmk&D0ww)Tweg>Q1giLN9m6T5EZ%_35HfjcdDc`pA(BtkS)nFC)JKlD22`rBtPhp2)1URfBbuya0BVB zt~rX0ecDNW^yXzj8xBI^*y%iiaKe<~?k>6Fq}gJ&G@B~hqc<~abLF>wi^zk<*iv%J z4`3&lP-K!l8Q1%_x|!V8C-YM_-I-K23w)dMQ`Ry$ESGfIKGSD8dzmD~7DmMmFvXlU zAP$d`(SnjtnTonj7k?gTr(YF~%dNk&8KLDDG7{Q7&5FO=O_T?zi=&%%#nDYWUf$C{ zivR6RyP%eQ^Zr2b<~QxwNu6L<*|@L#NUC`AJ9p)wG`4dQn+46FBi*}Na$`;8eoW{==*)3q+ku8#8FaiB!*jy+1 zqim6kf5%VZjual21w&gUILR=yQ?gr%oaAWPA{l1OvDq!YlRQwiNQT+6D7z)*Bu|ko zl3}*ooZZ6n5ldx@WEknqw@HM5D80$4jMr)C=Pjf+SAyntIntZ!>F%ubru2ex)D&jv zNN*Y|C%tK`ob;x#a?+c|%1Lh;D<{2ateo_wv2xOz#>z==8Y?HgX{?;|rm=F;o5spX zZyGBny=knR^ro@6gOZ}QRZ)#{(wk;mPI}W=Iq6Mf<)k-_m6P5yR!(};SUKrUW96hb zjg^z$G*(V}(^xs_O=IPxH;t8(-ZWNDdec}r=}lu<>CMmR$*lCI0c|oDJ48dS?Nt<<)k-_m6P5yRx)g8G}4>KDhaLhrmW0Az<=JZ;ChKL3(o!Va+4GIY*Frq&I~TB+{GL2=Wi5Hy;z8Jkp!O4-e9t zZwpTz=}k__PCn^PVFZcvW=l%slisWq1(`>BbCw{}_5VhC zQy4)ay?K@(^CNTBlSg_}_~Ai%^C98MBfYs%ka?sxg^}Jvdb2sR);}w~$!OuR^j=JeHkaNM zZ^VQ2<|tv!BfU98kgJC|TS{*VBS@q-Zx`f$N_tbCjm{^%DZcT6^yW|E;}4}b+ZMo+ zM|#sddu^mQ`%@yH^yUOX=8@hMMj}9Z^H4$Nk={H{ke@bkHE5*4zZmNN)-wNTfIA##KJ)%|U|9BfTk%Ad%jj zAjmw@n@0<>bN~+>SlP!V+jA|IE*3_RNN=7e$TjsWlr<5IM0)dfLC)&Q^9B~_b5uim zQy4i)BE9(-sRD6aARMqEz4CKju$S1v7E669i^N@j!!%A-o zBS@q-#|pBfFHZ+FsR7cPvjo|y4^I?Wq?O(jMrwfc<^oa$;#BE9*E zu>MKu%_NsK`J^|+8>~og)>GooN^kBXtcML{wrb_-M$lJCZ;Cfs1?kP%qzWY90^!FK z(wjGs`m@rTPl3rNy(#>#BE8Ai3Y!aS(wo&_@=0%sH&~J0yj@uTTckH%lGyS{Z%WL>hVz==8Y?HgX{?;|rm=F;o5spXZyGBny=knR^ro?L(woN0NpBh}C%tK` zob;x#a?+c|%1Lh;%SvyaLCa>PHznU)P|wqH)uHqWy@vGWt_>?|mfjpMJb9!yg&!WIHxCw`Jkp!z2r`fK zrZ9p;dULrT^GI*56J#FgO<@Fy^ycS+{6p!@k{0mv<$Sw^^rrB0y@2%Qa!UNaC%w5& z;?5(zDfOZLNN;YGxbsMF%8jjj(wo8v66wvZl=x%m%@M*gU?@w^R$B6A)>)9=G&jzS z^yUoVd5wAQKb78GC_H(jH-(>gkltKLD%?zZGt48s`MU7rk=_)3c#z(7SkeAt>CH}* z$|t=k{O};XIh+zEo}BciiDwJx%>#v}J0oig=}qD1*oyRKckW?ir8muy!BN{&9_dYE z<)k-_Z#MCS z^kx%JNN+}-veKKz%1Lh;D<{2ateo_wv2xOz#>z==8Y?HgX{?;|rm?K_W)(4Jr8gzt zy|X_z`fEa|54Avg^Sn0H!b)!%B&%}O+{dZS*5YR@q&LmBob;x#a?+c|%1Lh;D<{2a zteo_wv2xOz#>z==8Y?HgX{?;|rm=F;o5spXZyGBny=knR^ro?L(woN0NpBh}C%tK` zob;x#a?+c|%1Lh;D<{2ateo_wv8?pw?X+xGdQCIz>HIMYBc!L$`&4t36M|$&4L9Wa=TS{*VBS@q-d$$8wz?l5M zF141;_7U|8&c+MxiDKQfp(wnbIZ2v9Nn?Ffx zd89WbW@1Bnb3{jCD`hnNi=;OXhA*G=rbL2Aq&IICkL`Oq|8eQf=fuY*jtyH#Z;Eex zAiX()TfP51(whh4IiK{V#7t~RZ+@7K?f<&;W}*|Zy~=!T3+YXXnb?rt%uwRbN^edU z){U@kA-yTyU`2ZK6k$zn$MZB<**g{Ed66xoHx+N^g#ZFQ4?LM1n`8HxCq#d89Yb5@a6fO<@Fy^yV{y z{7*@5ekneF>&tUtwmsh4me)M%Lh+3cq&E|t@iCD-Xbb7h?&Rl_-V{cVNN>Y^!OIio5Bwd(wmEg=MSYf?-QOp(woB1x+Kz@&yXsRpbCT$ZlpKAA!WG#sq|*~ z)^O*M-V{c7klxHt;*X^_Cksy==}qA$Mx-}qk}8m(3WO1Eq&J@-75)dMH^Kcby&3YA z$t|Qezl1xV^rpmtcceE*cCp_71Jaw~Jtw^>-nWq6JQQv>kMyQQg?FSk=Tjn|^yc+~ z{EQjh7Sfx-2omYdRf5bTy}3z{d89Xm5hT)^KM69A^k&;_K)%h{Xbb60VFZcv<}sA` zk4kTbn@MkmqyLTc=4ImkG8O=~klvKAaF6unYH|OE(wpxIPaf$_;b#ycz4<+<0;x-Z zFv5-WW^q@z^GI*@B|o3^rf`5ndUFRs=8@h!NRWA?H-!--(wip>GLQ7;wSvqey(x?! zk=}ezka?sx-w|XU=}ln-iS*|8g3Kem*{U1JJkp!O2omYdzLdx(y*W;hJ%;f(u9e5L z(wo8v66wuj1i2KVe=5CsnegP1-V}a#kluV&c>bjH=2ya+M|xAd!HV=|z&+i3(wjZV z&nLYpj3ANT93#j-l-@i-c=AYZ3O_tZZ=NYUd89XQ5@a6fO<@Fy^yV*u{1-}Zc3}5& z^GI(>BzQ!6^Ds*ME2THj7mw=(@*w~_daU%OM1n`8H{TVH|3c|auO}Y!NN-9cctmCNrMe;(=0 z>4MB7y(x?!k={H}kef?ywseg2=Cy*g(wlcm`p|kFP9GTFD_A4FDY<3WU^#&lE);L; za(S(sxckb0;5()dad|Tm@y))9vRa;zPMY^3v*MfPV-bjN_GC+mmS>;aYI!QQqn4*p zJDay8bK;xwm}wXDieyfFQ=T8~s^xjl?)n;jdzcq05Z^ole?7H4hS^8UBb9x%JRaH4 zygQi{-!yMd=EOJUA;>E8+GI|AQ=V?D)=r#{I%#?8uvW_xgc`x~v^>Lbw3cTQj)_+S$ck^qt@vgqB0OHp(*+CSR($geA~-9)nfRtWC$KQS znfRvM1M$tdKvrnEJGm;psymN3Tk*~K zD;S7xwqyHREq4K*({e}e`S>#cv*Mfa4H$@TwxrZcTJF?s)N-HgT`hOXHfg!X^edu$n&Ir>}LK1SScp9eoWR@LP~NOp7awR4d&6NtoUY3Rw0V~m@Fa` z`!QJ&DDh)*ncmD#d`-!m_-0J5z{~u^X5yPMxnwT)V{%1W;m72nuce>ZOnfsY*L1D@ zm|R@7@e`YgZ^q=Br=1^@3z+tPOs+;c_z5e%d57ZI3cQa;#EY$m=Lllk@# zKe3tkW@2!oBYnc&{)$7Ftbn;(-2BnTEb*~?j+0T7`Or|9F`!ShAJb=aN=RrRvXVi!M zn4AJ1_G5A;TIDA;6W>g1Ccc@l;+y*s^;$nBCm;v$%`^BDqp8fxKX*GxId24#VYYP4 zZYgw{r2@?fxqaRPY?UV(K`rc)dUw8-wZu-4I@^aFpXP(BXr9!fs zi^AXjZr?`W@A#brmD? z?#Sq8upR25)T>nou{zHC8sia_G@JPDpR}U#$F*QbHE)d_eR}lP*izmabECJ$+~}<_ zH+pN#joun_qxZvjPrnBo{)ZiI)lqT)$w#8(aFUNk$%koy z$0r%sizJ_jl7A)nWR&~|$)}@a0WO}6V3j0ajl3N}felgae3EZO$xBGS6(v`Ye8(i6 z>n2BydIgQz%{1z7*GG-|E{$3qHEMa(sO3?kmPd`+vdQ-|ja*{0VKhs5)YL7Td_S{r zSMr<5uq%%`prv$x{eEWQEZI0uHb%Wr9`!=^=q)@lr5D<5A=Z*GVl4?H){-z{Es6De zGb$2BtR*pJIF(8mv6h5Cg}o$U#99(YtR*4u7#1XqSWCi)wIoub8TJVy){-z{EeRvm zk}zT|2_x2$cykN~=!6k#Nf@z~MCmAkP8hM4gb`~=7_pXw5o<{pv6h4pYe^WfmV^;& zNf@z~gb`~=u#n|+N*qP|Y?Ux#EeRvmk}zT|2_x2$Fk&r<5xX%G5=N{gVZ>SzMyw@a z#99(xjN=n&ZX}`SE+Wug%H23pB=p>$CyIogd+QGJx~&^Y=(&-Eo;#n+3zQp4=(&-E zo*PN%xsimP8%gN7k%XQbN$9zegq|Bo=(&-Eo_js*|DAFp2|afM)ITWqT!!&P*Nr6f z+(<&t{XfjT2ap}b^*ubdd%~MHFYT^YyGk2S+!YAL%>qdX2@pXNB8iLwIfFn%kqroB zauOgin4Clgfk_6ND1*Tm111{*Ho;)9`JdC>^Yld3N7*j_T%W4+x=(lC+qc8?^vv8n zeI?rakyf|v3?fCX>=Am(9-*h~5qioVp{MK-ddeQ5r|c1Wsurp@^;I{5&3t8#&{OuX z7G;mnQ*WT!8NRB;(9iUhJwi|Yb`#uhePxf(Q}zfwWslHP_6R*?kI+;02t8$w&{OsZ zJ!Oy3Q}zfwwINzt8>lJJd3d1g5qj!q4CfJnx*xOYjX>EW^prh9PkpfkkI+;02t8$w z&{OsZJ!Oy3QwPJ`7bBIR-pj zJ!Oy3Q}zfwWslHPo8ao$^RE5p%;FPhVcl!Fg>g# zOb=@b)5BWA^stsNJ**{64{HhULVY|!FH8?>3Actq9@Y|Gh)&`WdSQB4OPC(k5~hc> zgy~@|VR~3gm>$*=riZnJ>0vEldRR-C9@Y|miKg%fy)ZqjCAgaPIukI)O#!&<`hu$C}AtR+kjYYEfCTEg_OmM}f6B}@-% z3Dd(`!t}6~Fg>g#Ob=@b)5BWA^stsNJ**{64{Hh2!&<`hu$J&d+zWVwUYH)%5>CKs z$s_c_5txuXLN7cUy}={&!t}6~a4MugBI1SVVJ%^LSWB25))MZ3PT&!GVR~3gm>$*= zriZnJ>0vEl`LLF{4ve=utfl584||9RR$PvVcvU>CCC>zt!?RgTPT*DXu$DX%46V|m zX%1w_-kxWIks;f?kx^b14{OOY;a~U({IC4{{TW!X>NHTg_)Uw9MIxtTA@`j#T5+YSzxeSRuvni58^7@T(_;PAWq3rxA%aNv0#z6E zIVg5*>JzNZJqTR;*`~h1+ItX*X;VL!XWKNuA={<~hisb~9kOj|w#c<B2JJM268S{Sa Q0#*@Z4Dps`!c|=1V1A6%3@QUc{y-FObne zpHkMfYHYwS0%@zp1;eKi*;ci=Jlm=chit1l9kQ+Jawx6}h>u4s zq7puAf9410vka$Sfu&Jql^S%f-rUn02aSI; z1#9j=z^J(faQF$!)V%@o^(MhRi09wM56-s@;ykRE4^H#E?E-V?kiZn#G6>dXt4_o8 z-6}Ar{^%br1&4T$d<8*o;K{N@usKTDp_vg>&js+ZRCbbhh5~J8#0T+$2BSh1%jTI< zH{~qo-O;Ge?}>y!?H0smBNET+LC)Nu7bgM=E*}awFF1md%r{E!L?m4$u3`=o%#XS3 zUrMtJUe#mFVS-sIK1p+Me)Sv7VSdqXIZQA)O=(W(Rh1CWGr{EWPw9+I z?8EW0WDR>W5JUrmf@&gC+W#EKnFV{ z@;uNX4kO}LxH>rbhtyI+yJ?S4&j()eD?VS>$Qi620bh_eHW0-_2NYH~~PJfa28y#iIB7rJ%FxqD3bkvu68IRhX7sUP%QPh zIbQ2fRvLk>b10D^K-W8zlLVL54G!gH9pwGOp@NJBy3rwa|M@NXfoQ2_A6?ke$a{@` z6Y@8;)Uc1x7k9Q)<*U#ao1(Ywc9NdV1X}Kp$hJWDID~Vif$nuk%Uq!Q90FSl(ESbt zasbc+4u!G+=s|}fISS|@hca?J(8CVJvg{1JQgJ9NZ{gBe;ZP#iA@5O#a&jBi^2Z#? z%RNB9bf_Q?13m5#`{LG?{JLnV<`&_0*B1%2J<(FbKEnJuwXB_d7^FJiZFCZ5s~ zY=>xpQ?Eb`DEUH5{#e9h_H}rmYiV4BM9jpNYjJvkL!61fZi%lzDLoD~KG)KZrSuWY z@It$#NR86gpIpUjao9u`mAGlD`iv)to(Fy1uB! zO(fG=!#=|NdbK5f9wj194liQ2a3(&}68s6#0;gVq8c?#PH6Qna$?xH+u5C?k&u^j? zy&d9AEVjnOQA+njp?d)^OdphF^u01a{o zwrQxj9dsb+@V;$#9Ue1p{#rd zw2niGD3l!GP)=f?bsfq}323B41*roX0-EAbB4+?ibtot20&V0_UM>OJ*r9@43ABkr z?2B=&`3-ubFF1SJU0>|57$l9YHS8nIufDDEb|?{Xa(EHDg)=eV8tjW`fm5$Q4PH>1 z)DkaYN#4x8hzqG7aS~@DD#&?t|Ab<_MJojduh84KK7@#F!OxDZO}}CMGK|7btxbm} zP*C%E7O%pQYPO^WFVE5gSLp3p-$5k01V5O*XW+`xyR^OpgxgJP+^Y`5cHU6zqgw68 z->N#@_JxeO|oYERRNj>x}Jk{wr7HrMU>JN+;aNSHr(OH zC8r`Cvk}~K=Ig^oeQ|dg*MAWbv2)u6TN!Z68C2$$GpNihXHc12&Y&{4oIz!7IfKgF zat4*T|x12#`ZaIU>+;Rq$x#bKhbITc2=9V+4%q?e7 znOn}FGPj&TWo|ix%G`1WmAT~%Ds#&jROXg5sLU;AP?=lKpfb0dL1k_^gUZ};1~p;@ z`EXqD5C%~{jIsN8Ts_nE;ke`nwI!Sb7;A9Lwe-XII&L{r!V||WXHc12&Y&{4oI$zb zB+D&lP^sv+Q|~)@ut+ zqGScPoOaxD)Cfs%%Uz1tkGSQ0nbsCOLdgnlIqkURs1a8UxaGc}^ zpStj{YmtDbZ7d#dEebPO(YI*}YWqX$@5kUVyUm>TtNRYe<7!*N+F%d3<<>!oA92g! zYG@0#pkxKNoZc2SAJmpmBP78scPJ%)id)W?L)(H2sHcKkPX7x1dQ4kF{m=t$xm&4c zO>Q~-rCVF@A|>B}y(e1EHT~B5o_AVXLXD6Fx7aLesT$zWn7x13LIxnn6= z!7ZofO@$LfTSASH1h?D;lw6Zr&IcPza33WrxaG9tmZL^Uf?MuIN?wZAKT*-nN7{lf zD0vLhA9X!+eFr`&w><@TrK zf66WA%PVccS*)XiTTZVWkEf8fgmt41aLYZxI_MAbuW`%4+rBOMfLiBul@;hX&ILEN$bN=s6C;6=mEFf66#r#TMh@gwg;bo2BTD>;Th5o(_Fy6lZi-29pILG7O|h?mh)w!_FxrC=?ZQ+eJr+ZGujjCho0@);{ZFPA92h1 zvQ>L96zRHxTTUN}`LkntLXD6Fx7_-a{0G`T-|~wIH(0y02fI?Tf?G~IZaHd%B)H`k zQu0fT*TGg2FS@~I)E-6|o<2%lUF^d+;LCbp^Maer+P&J+&v)0ZDMneMHGl)c0709S^q0$v{Xxi*a?_ za@ujrQ6nV5EjJJ)e#9;33%KPrq+|uRoOaxD)QA>VPD;5-%G#NSb5ZRk&M%Z);b0u3%uKWYNE+&rZH8{Beu z*U=H2!kQ|$<@DRQzpdSoP(QSSTkZjB{nxqWd>Pdd|AAVkW2TRB_CJd|V0TB6wLvSm z<*M+^_-}B_VYk{5kAaM?;Fi;lTaLA%SHLYd6(tHZxIq1=3EXl=vZhC|%FQZs`z^%W z+S(!s<**5!w@pXmGzbXqwwrgvm$IgXli=>{>^~Pf*KIqB)DNxTmV1#}cf<(oTGl!M zcjP%`t$**qCz%SZ+jqoYQ0sk@v3@(P=VPwS>nO4|)C+F82v5%i8eE`$)C6w1ZlwJi z+;YC`*%9mr8C}6GrI$IfzyeSJzt5aU*;SGD66 zLWg~&aSQG?XLls54O+o1XZ}#`f6Xn2^}i$FAI|9tZaE#|I=rSMq0O)j+;Vg){t>qv z_SYQ&|8P!MaLeg_ki4xUp+<}VxaB&r;HTVji;(C>0Nip0*%1J@oIxt(mNTf#EoYFQ za?2T1=9V+4%q?e7nOn}FGPj&TWo|ix%G`1WmAT~%Ds#&jROXg5sLU;AP?=lKpfb0d zL1k_^gUZ};29>$x3@UTW8C2$$GpNihXHWy?>0KSc_UKvt7yK;msAszV*#x|~??}ua zGX~_AJC1!%*0}e|^K=HT*AE=>F*E37r$qH^c{c|Mr?M$c5$yZ~;w!*GN6{}s2Kuhv2PVU@1nmeYHU##`mi zgzZ85!7XD5>R=e%cVx&V7+;ZPi^2w>VPjou(4w(To z&mpdeJ9Gy9uzAwsHY{_?X~!)`{m`?2XFL%lev(@b+y2dht-I-87)>d%K zeTNb$x7;EmVr_NYat4*T+;Rq$x#bKhbITc2=9V+4%q?e7nOn}F zGPj&TWo|ixs<47x*%=JLKZsm zm3nr>K&-TuXvZx_{m}DHXFkEJj+9%jLJzp*te%ux&LHkQz%929WVGX!W4dgLK>er*+;Z=wHT~7~inSQra?~MWY67>MK`P~zGpNihXHc12&Y&{4oIz!7 zIfKgFat4*T$x3@UTW8C2$$GpNihXHc12&Y&{4oIz!7IfKgFat4*Tn4mG7Kewls$-{F??)ugWAE7rI#cEppr?ECHB*j>!*N@xjIKyb^o z;ML#1!7Yb(L|wr&$mpAJcipDT?w}t*eCMu&wL$Cru6Pc${vJtbp%UyyJ z|8s6RUykVt9-?g(+;X}OJ-)arq0O)j+;Vx`lKxBFayXNrD_9r$^xyDvmg@~4tNkTi z2`xd5;Fdd(HU6jEa`@QX6`aF5D!Aoz`v!Pt)|Ies)B$d}Jev7G=avJ9H`fwujxx#fI$s4IAuwpDP;=^zWkvpxPo<5aLeghEGHj!C9E5D zfLo5Qi2vu@a=!c-?MKb}IqZp6x%RJxUFEl332laL;Fh~5we5e&Er)Y2x`NkeTLrhA z9*CWMwmYHCunpXDd2FBm4Q@FQU33TQLPl3`%jp@obJTYytPNVhEw>f5{uH+yzBzXX zhfz-jx12r)3I=y4)DJ!2mRmwSYjVr^GORneost#Ya@ujrQ6nV5Ehl(MCjT97IbX(f z2Lqu`KaQVqmc32ihNXXMcS1{0Be>u}Aa=vWR9qdTS3T`>Q%>>+MyAx`JB)H`+ zr{sUiE$7SD-NB=*qk>ybJ8n7FjXJ-V3T`?5M?4)}-(94B*a&X94N#&$qYBgr-QbqH9I@hm$SnuC)!cH$ zHMr$`xf$b6i|)fpf2$kCPw;B*{_cc!pmuP}4Ztnh)czlE%dz${w;XF<%`Jy}PIs_A zbn6OkIXxQv@eJmWtsUHQ+n~gcxaDx~=nfWAvVvPq-ww%FyAx`J-Qboxi;`<{%i;XC z?%+;JR&dMdV<7oXcS4Pj1h?F?lw6Zr&X@PPgH@EQ;Fi-TV-~FHPN)%*;FjA2Tkrpr zTdueUw;cZ5!~3DTaSAk>*ZE&`$NNCJz62Wv$1SI?=W}#Vk!GQKaLb*|>VJw`&KKPi z-$gwY+;VyZHb}XiBK2buf?Mus#0qRnff}J3+;VRr_9JdNUrIfJ!d0fpIah7Duk<++ zu%!1S)B#Cw%k@QxA92fJ5$_3lC|SWRr-wt!pq_*pAqj4|S(IFpTMi%1dx8a&tl*Z@ zYh%8Q?n$T-lHis*lagz4%i)Njp5Qi0R&dMd5^lfadlG7dB)H|CrsSI3ayUk)C-|6> z72I8}f zIbU|_3HG6$3T`<)4z1p!C!v1m0k_;T>iO5Xj7PjB zJqh(g54h!apq@3k<5`CsCe z!w31EU^nQ~72I;#am&#X)Cg|5J6Pj?hg;5<@uhV6*9VlTTWk!8eZ#3SR1s0TkdDn`hUSK=gS*C!7o^U1-G2u6R)d2 z>Pcu9>Ib)627~{9!Yzl7DQG{m>re1L>{HjPZ(~FKZBIhGP(Qfk=#}$taLZwv-V-dM z)(UPpJsvfL;}g~ft>Bh>lUn~TxaDvt(D;BSIq4U1oh0M!OPgDf(0hDByHG#4rYjVpC_SCTPhfvZn%bmpdeiN|zk55jc zWDW0_Of`Qc`h$3R7O!D#msF$<^rBbBt(ulPWrJK!W4ZPsI!WiOQ+CQOXWg+uFZa&~ z&ejp#pZiC2jBSeOkUGdZXs7&g5nWA(#G@0~l@iQFbRr!V(dn}_q66pfxQF>*m^%rT zt{u@Cb7Vxv%25%WBuB?1ipWnX=Hh8AopQ`YbcSq;w_;jKG8fU!u_L0(VrNA6!>)*~ zgy40ho|I)SqU+y!5nc7xkLYMOA)=ey#P~b3NvAY(@zyaAc;;x^bMX+Olxi+|7A2;~qnMU*%|&z(n;FsFYsiU9t9w=mfQIM5m_xBDxdpAJLiT zfQZgH2gc-^(<$LxM7NtmB08rW8qwKgK}45~!y-C193Ih8VPQvlPqi8&m%ezoE?*NPM_OhT>H<7`1$|bh#%U|i^)2t z@35uMkN64w!q}UDw3K%);-}rqB7T^?JmN>zWpTp%lz1-U2h%I#-b@4Y+(VcPS4I33 zdQD8`Io-dr=1JIkZN!h9zlg77xs-b@zL^N*b4d=ju85y6SHvWr(<%F0{0b51=RSju z$0L3yd?DgTzZc`@D4X)n#jg>8fbL_ITN&|l-dhnr#=RZ!Q`$QbKZN}$ewU@dK&Ljv zU&m$nQEP=ReTGCZ&~c7EuCx3O^t8_M1Ie#-mR~$x(51hl2pH(zqjH_)2ZXnDi8u81 zyJ~Ji;=8(Z0gNg$&}I3a`=2_?m(QM`HE)akEMNU9Kg+kQ+RyTZrtfF@mN5Xri>A=e z@||1cXZd<7<7fHKDF(vrDeGtX1|~sC+yZlcX$=OtEZ_Sb(=pO@8xItJlWgN^0~Fn&+^f*-Y>1eK$qo{Utd4VN3ec= zsn;ZQkLADX?`QdBG{DdDF{i=L@|mU4FF6Lf^>bLB{496+6Z|ZiDGb%ICl^g?Ie~jBkewLf@MShk$>*M^=8Vq!$62=bt{DXk=y+2G6c8#+1C-=;g{B6pv!Vcd6!?h z0(O=e=(5}%F851oFwkW=QSSA#+>YJnXSqkZ-_LU6@_?V^PUAr!+@v1zv%K#<>}PqS ze8kW4ezn3ct-(N7T7!YE`S{RRd0qO9oHbP zPQ3)bqNW<4PQ4ijR8maz)$U9T)B*;fI*CD~9%f!fol6v}hU*Yy)jA9k)x#jC{)(Es zyqZQ-@am7h30k()7tx5n!!B#Y*0*j6J!dRInaoxAmCSwkRhj4Ut26K6*Ux;1-yl=< zb5x%hir*+R9>1B)miUb`+nj}}GyCE<$((@ST;?MD<}MI0!rIHI!pHj^Tib}0O0Nt-35UoBzptR~(hBQ=oA?nj= zbD%)0xd=k7>X8^}H3C6KtH}srtq!{g^`RuDQli!6Ksl}MMv&L)Sp)@$Bd@5{sR+=B z%MpmL?na<|^(+GItG5yOzWN)2z*qSzQJ=2{B8Ys|i6G;vEfB=M+U+XT=c~gJB)&Qm zLC#lKBgp&eegp+yy?~(TtG%v9eSunpKmv6>0u`v65a>WXhQJTh?+^rm`ZWe84AiGU zQJ{QG&rG2DB8UTZ6@qM_?n96S>PC)VpgsV~2kIXP3W2J*7WD;c1Og1pWCRkb*$7mq z4nUwoH4`=Xp*k5T2-Q*qVW{pv5QVDxQq&i!r-9;7U51&T4b@!;l2AQ^AQ!5`Q6wL# zw}1+v`WitoRJrR>U!>MTAd%`opdz(70v)Nj2>eJLfgp&~&k=-?x)wncsRt2cBJ~o2 zI8wXZfche}06`L|#Rzhdx)MP?QuiV#MCv&N#Ynx202A%+2qdFE#TB43YCChuDSt8Q z%c%X$MW^}#g&8#xL6lLYUqCFQrU1nmwL4HYqmD+9WYjqbav604f_z4uh9ZTGT85yQ zQSTrTGx{3@605?Es4rH75a?KSA@E~09YGMQ`3S;T9fcr@)!7I#vAP~X9II~;WMfsl z3H8NlFoGPG9xO!pSakyxVl@LnF;;tGWx%C#ECR`@M={bWtIh+`S#=`@y z^j!o)>fbsYm2_8cgZO~mF~fY6_QLgc-wL%2hjuUXJeCiz4lKnlOb$=LbTX0oHc}t< zzS*Rxa2*@b;T4!V_~(bOV_M^15VoVU@h=QFz_o{eQTWVhCXxv^wvjkI(?+u4KbD!S zB>WTa#AsT0B&}lPLo5gQmk%eFWpYV6qp1$F)Z0-HSVYaRT;Sekq_%|S&U?UCT+g7|WTo>0M{xx{bLzbcQ z!;jCzNHp#EJ^JpGxf;S)#(FldfBf!Zps7+l4<(!8ms3I)vcYFpA=HqqvC!&?0t*1;dIc4}JWgf)v0dbKQ5 zyBDH$v)Re}%DZgN8Axc}n(IIuY~IC9Y#Yjsl_GNQ57%)szJgJ9kI3o&`3ar!cV zA-_UrMiZsqMF1mT#ZSCzubKx?(f5d(O+E+$KS8`-H}*dVH!*oAiJQCoZws@zpZA86 z>A7d^GVZT2&T);-AAqFXW0(Q}9nYZuk{sqrT&oN0(qw-OUEJG(QOSqPfClQmrnkNR zpWu3qzgGDRp`(G5A7BiJBliMkG{8htu>WmT@@tjXWVhum zCwR_*N#6lHuQuekB-c{ii^`hRpS7-3y{OHrB?U$QVVHdJO)4bkXzo}x<|Z|Yb0}Ga z%QwDD^+K0;$+@iHZqYjw)zB<(O@@g^1|rt(cIE8olkWAOA!gJ)It<}R)` z`;12`tBn!&myM`a<5zb_wc5sXM}{L(t@h=Wl?2o8r-)^-3 zqOARP=~=D)4(T!4x5gbczEgTk*P4dhWkIqnhkv=#ZuLg8h3J5o<5R= zjMCFLD=R(2mhZpg`PlH?F1@=@JR!+{uv`MWLcfB}4bGC@Ta~lUcUhzBaq$Fuh*|Rw zLAF^IkM=Rp#v*uHk;+ z*xRr_9#QB*V&NFZ=a=?n0sHQ&un0+N)2fBc{-6o_{bBW{C`s}4i2A`u&tl8&B`D_= z_(4XG>NAF^_cN7s72a<`>exOLnfd}#-@s2TsqP~mL+JU_?uhW)V&aDD-oJNqRO=hA zd*5)~`-bb@zZ+#j-`|CzhU?xpT=%}=y7#x-0?K{Eb?-M%MGbgeZzI{bMI5@8?JlbaNYZc>)tn9_rBq}_YK#*Z@BLLJ5g7I-;MR4(KlT8 zzTvv}4cEPIxbA(!b?<+_3H;%F!*%aZnufQ|zTvv}4cEPIxbA(!b?+Old*5)~`=4Q~ zpOceN%i8!(J_9>w5zBQimg`<_+ZbCO5zBQimg`e(P|kqMi7A(3$v)DPJtty;!b$ z`2rW@4xqn6@7{(#FGlb73S>hVSPQ=s4As~C^y;!b$`4g&rB@)YZFP7_GEZ4nQu6ub9 zCf%2a<+>NkbuX6dUM$zWSgw1qT=()OdgAJ$Sgw0nfbO}rD3XCP9jaaUGc?VOY zYN(uy8V;xv%XKf7>s~C^y^KK{4yluu(PxL&Ndp8H)XDqkp2Os~C^y;!b$8G@3>)yc1LRZmzdKcFWjE)~mlF9|NK$xFp@-OD%> znX*)##h^}IDvzNJ(|;+J>s~C^y=;Q(d)JS}a@~vNx|iRe?Q=gC%XKf7>t41&;_e@- zkI^u4-GjyxUnUtzx$f03F|7|~O3HPwK7!1lOi8)!Rmyd*e!xUMoLO5#A-V3=h3F)5 z-K&)AUZq_3D&@LYDc8M9x$afUb+1ycdzEtCtCZ_rrCj$a<+@iX*S)$2wUg^!jYaQ} z>t3Z?_bTPOSNEdB&)FGSi!mzaGO`8QejXzMdY@ePD&@LYDc8Na1!eFDZ=OoI?p2I& z&`e3W?p4Zlua;seh0IF1?p4ZluTrjim2%yylqUJy-K<6)i?|Rm_sH>VO6R=v6>t3Z?_v&o)2D$E4%5|?&u6vbo-K&)AUZq_3Y6o-zx$afUb+4Ym zZHjGGDc8M9x$ae&>%Lb9#@k;g`h66w{YNu&NCTq5(3%WhXNCPRy^7NYfIg~t&RUpQ z#Vx9ENfkG)!IUb_%He`4>S|n1#g)Bqdpb?*3!y_bq3lGr4=w;dDi2cDc09|5)F~XZ|ypdp`&&10z)0ApXQ#VjvuRrvG?)SuB zg^q1JT!r7r5;p6vc&!osU8>)PFy2LBZx()M4e-O?3<3JyqD(lO=pPp425gD*4gM)K zury!;#D6gHUSVIB!g_Eyl-Gx65{WVm8Wj3O%A#T6h@n8*qP4>hnde(HGF(a&STr_# znpWYv3~TEM$51Y^s3$yyB{Qn}KGZiM%nk#Jm1)gJ;cqCHwP@4uSe8sw^~)$ZJ?tUM zsp?fgyM(PQnYSemAF#o!nRsu_9yuy}n>j_BvnV{5y;ZVxpBTPKRAtf6!Yiq<+M>mw znKL!2`ft$xb33rTY#vrkGi7R3b(F^vpn`9xr?;(Rf(rggSZCp66>Lfi>Mh*JO{hMq zx(>3Ns-Tgz_O+U)D?6e3+1yzw7|Y!LHg{VU%w+cruy6+zOr+)p3wKe$-7MT_;anA* zOW0)L9x6DMRyA9=j|x5_T+6}(RImjHWuS$JD9=nvP60DX6EDlT7O_X~N)yFPu0}k| z1e5bznxpYB#T+J>oDb8Sz)OC|9443_GtJqHrk?HXv}ey4j4Oy2%g_{K8EIyd2Pr)Q zmqxA>KC0tGksJOFF#M&q7hbr}lR%GKpo`>wJa&s%ofWjmGNB(rT5LoQZgr3FgQ2&O>Q7uIrl-Hy8U$X=3DMA7diB?1MD1 z&P!fJJj(==BUr^uOB=l8FU(_|b5JmD?#IPL;Vv*A zFmce=zhG|OLU^xNl_K37EP`A-bsp|1&2=rQh zccMtt(%k<^B#WoJ2wNQ#{W@zJ?x4~yv8J^h)cPXAbsY5da>8{T4E4j59qC}C$58Vq z2Q&J@-2q2C80!pMIL5)O9?jgb4kr3GY98lcPS0fFHV5K4K+98B~rgwq|&=>fEA zhJ$%MfjzsWgQorKq5WuFOcN%!_Fo1av(SF@3){aV+K9Z-jkArzVnuYgs(6oO$v>%O&XQ1Hr&2?;Bd>Z2Wqy6X??B$}v zo8zaj57ag6yd#?Xb8*7>|B3KO2Su+UJjy|(|3-MUgIWtKKE^>`Cxpj380cEUMGl6# zg|f#v80kjl9`9gA@4*(H;9#t;W#JPY%<9_-PjWEPn-QMuU`{_sc#4C0{S@KP94zRU z2v2pesNd!=oaSIjZ^U{}cd$x7POBC>Sgm(r;WHep(c5#*p6OsO{SIY+?qF~25uW8> zo&KJ(XFFK0J2__OIM_$;#EQ;!u&+LzMxN(jKRuNdo$p|OeKIv);NSp#F=a1uutC=_ z_Yw!W3yuzHHpdmmb;w!JT+gA6J0P?a!;fjf;lHXmUJILky^y-Dal*L#Y2~#JiXK3- zu6Gb0wEXDu=3qm}#qT5M3a7dSI&N%EctSE4?K_*}{iymi+I4q%(cYH*agT#IxksW~ zn}f5ci#fNuRr(0%y}vnO9lS~(Z;o%IE*>ovJ!vm-Y)!Gmt!NIOqwqdQdfsF162BYP zKi!;ADcksBbNn@hN3rIYZ7X6tz0CBY-?}!HysD8nHy6?)o(S&yC6X?q+RcfXK#FylT#rIyQ3w-kf&_F;j}EkjCP_da^yr}GnyIL6 zvQ%^BStiw-fmcgF*YoJ+=9<5v8P`iSC(jBA=z<J`lYlPg(ZkI( zO=#@nQq4(%O)*{1qi1X(oK#D%^XS>;nh=HXT)@e&2)kdVzTRB(2@GDQsyU8$&W^ZE zD!@F`^W9#;{>?JMNfXYzHvScgcl4v}IVBE>pHigkz->kui{AyTYE zq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-TNU;u)VjUvIIz-AR7hslX=~#v?gvaNF z=wL0I0|hul2SJEG|3YE}x)}r+E!H7YtV5(&he)vwkzySp#X3Zab%+$}5GmFnQmjLy zScgcl4v}IVBE>pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-T zNU;u)^1G|izCf%)q*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-TNU;u)VjUvIIz)pHigkz- z>kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-TNU;u)VjUvIIz)pH zigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!`{O39o-*u?~@99U{d# zM2dBY6zdQv)*(`?L!?-TNU;u)VjUvIIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBYlqKh4-A=?hM2dBY6zdQv zH=l>=Jtx*7QmjLyScgan&d2qh6YCHu)*(`?L!?-TNSTA>BFTw$h?Ipu`J7mXNVx{6 zm=o&|Db^uUtV5(&he)vwkzySp#X3Zab%+$}5GmFnQmjLyScgcl4v}IVBE>pHigk#T zc~_!83t}B2#X3Zab%+$}5GmFnQmjLyScgcl4v}IVBE>pHigkz->kui{AyTYEq&SDj zUUZ1eY%ThPI^3S<^Ju@F#_N&S+&4~-zHxd~snerMogP){^r%v&N0mA~s?_OGrB073 zb$V2()1ykA9#!h}s8Xj#^$#r8_?M{E=~1Olk1BO~RH@UWN}V26>h!2mr$?1KJ*w2{ zQKe3gDs_5PsnerMogP){^r%v&N0mA~s?_OGrB073b$V2()1ykA9#!h}s8Xj#l{!7D z)ag;BPLC>edQ@en$J)nlEf2@9yPGf^``?aE@t?a5KmOV#zT#%={`}97Qt~gj1)Dry z<9CApHhve$mPp6;?+p~fpEq2`ASdThFeft^lw=r-G|Bp?3Y)))5X1IvDH9i|{h8z1k*3tPg z{-WW25C7`ud>Mb)zzpB(y)S|SoiF3B^g)Oxm*Qs>oiF3>3cYV(%5wblzJWj7Up3LK zFFWdU;5vHsWye$-bL!~TmmOQp4Cws|!RP|L`m*EnGXVJW4gMKYZ`?4wh_yB}qhI(= z+=t^Z;>};7i;`iDOm7~E*5}6cW3A1PqeF6?jb9@^hA+f&H`nl~YwY_zw2sfuL-`tN z_12;*%oak&gASIJvC1t=B-61r0FL6sx`COE^jTmmuzgZA1Y_BpkPA_tQmw| zGvcoytA74mKzv4F-r=xlfJBQCFW_Sb^9D#2^Xd=S|6s)XF{{r*7~I?d8Dxb{g~B?k zu-ysONs)PdmSAe+>ZH%!0A2%qT&r!tEnUHCThQyf1WG>M6RG|7Jm^60&v|~A^7{5g zMeiP)roQJ=Gtm0#d1>nJTa#X=-2OE6PUF=v@F>J@9aN8+t~Jen4~6^h zcIbRBckNmn>Hho7+Yj;KrdfmbKwm5~GcTW2^C{mcxdoHVB%L`N5Ow$K% zkL+TV^dmX}xx*HtWU)qy{A}e7z8lts?YX`$09=XeK5N;8(M<3IX7PI; zz!<9PGZ38zFv*k~JQb+4wlorb#9HX-QySqugmpd+HKoVL-6e-Y!oQB9zUUV^$D$yPloO|GNOJP)KfPRKh^vRt&dQKUO6(V z&mqj*iJANft;pO)OFm zc~7oFrpVp}tZ!cCJS3?pcw%t6cD|bhue^&z&Rxz*|A=2LT}bieGt7oS{Ci-xY>3}T zuEK9d`XM)#)9%DNBRAcF1wwbZ z;v;1=az|N4TXGYT=lS0az#Bjd#Qz+fvZDpc z{{U9)WP$cCfTo=-z+syJyI6q3s8RK<7U0_&s@lzh$iE6Xb1cYs173x3bA@JA(~5dI zK=i4I^wGWW69c<$8%a8Vy`0dpAy{%Gf{5}?l|Gvf_c3YtQ zV{7mUTY~K&qW!l}!(o!+?DGA;V~7v8#X@hu_CA~ogmzR@eJ^~qi8D|XFT#yRkF4E` zorI4v=nFkc{RKrbBQPp@Ok)#DWmz=SfR^cP`u0M+m+}wL+aOZ=Z4)Xxu)sQtUhODo z^AE~0M~WDIa~r89?3MHPj;})`uDus!_RTSlzhQz-e?Mz-!zd($anv74hZ>7AaS2WG z7Z{NBvh2Lf^g1LRt>;jw1cT#G5UH(x6jN?!ugy?EyxO)0fQDHlwLKW0pv5BPWu{?N zgI0Af#0KIej&4HN^j#l~U6<DJdX-zdnvOwk!ew1@d+QO(hFg{I>A32$Y z_M*xcd9`Ft6EofO#av&YGbEr0Rh@#L-rJycbF8W}tg1OOYPCgkWCBOXS~N#y(1@W2 z%{#=)>~1UZdLID|)2xQat%hmRW{fe_&ywo>A>^vxHm$yQEyN~>>7ehd*aYb|74MBs z%1n@{tjmc_5pAt5U5fdY8E)n3up2`c4ws>n^Gffs+xpnN2{x~f3^F>6DSc$5nJA@u zSunB%cd!NVp3f*ro`qds8MB^4PSwF)=Bu@tqj)WSHJ0;I-2wTpCYdOgkgqm3(HoKa zbrT0rJ;CTGR;GCEd_9E|Q1P1jdK;z&FQC9TrNKzWn-q-M%VyTqVi8nDlzMsU`RH|Z z>P0C1x7*e+|)K352ffZKg%QS$S1tN4NjS%w@`r zu}SIwU7B#KO~@PByDMauJ6SLL3D%!vGORzv*t03^xf88DWvGd+L~Bo3k6qr66Zp)+ zPVD_G*W=_qNF8jXj!&fy9$c0>xQ9{!udSo3RI(3d$=oWA!7~)t`zgQ?gjMtQo9kuf zZeWJ;bd12<>1O=SVsvK{y@1jE81<5c&^g=aiLfOzdS+MXnY~)i?A3Z^8$Dj~EqZvm z5$;Tdr?0cxi0PBcMoizrR(A~AIo`B$79>nRtZ(lQ$we5G5hm+EWaZ5$jCNODqrhbU zJ~KxbBe!Zk&_J`aH}ZKWK5qmk)a}eV9B3jDoWSGrHe<{y4M8)pxm$-;yns>>I}8aM za&hrWPr)p;uFd|eoV~7^Vzb|&^e{D!&FP1|uazFAHfMIR9=54gWo9gP&%9Ji%GlGz zvYe4f*okuzO9b{+_)~CW$ac)G7n3lVmU+Yd9FV6*a${+;JY}=IN8F}+1TKj_X474` z&u+R;oP}%7?zS^_x1F)O?TquNcf0LrsG+J0KN;tY?>5?dAgR|(X7VTFeDmLL!bLW= z&q>VWl~Tp!Fk^Sy8N1u=Yj^rcd=h#2Q}NiKUa8~NnXw!2ets>c2FV6x`124Z$O85!sge-0K zlf{rb(Zn-eekBC-NxBEZ10rD$`s>S5pt>E=`#8iH)`KW&3k3coeH=0xZo^O57*pBP zh}Pgr^=f{@*cFI*g_jVmWlm#hSuKkCW3X=Elei!H!x&Z1R6|+lPwD{BY-7eZW@@%E zcJa4=i?zeW|BOqgw~KF%9;>r)uP_p|6xi_6ebD)szSPz9m>#;irpNTea!pU@)iph7 zKjQS?qDPoU?dSQo=q?VKSGoa@Mi*)BrrFku z^tx$@i*&as5e`Nt9;HK0g)G)P7CTC}8bi%S`6xY_dH8cz)I84?9O4Sj(~T_Xh4&(F zTWxMevt8b{y4xsu52tkd+v;iTdx2@&>e;qpZVV?|8MmjOYMIG;Tq-kJPqs39 zpq{?ghCeu&zSah1>glW3rA&@XeFKO{V4E4sMqNDz@vLT74$;I5{zVc^f`fjF^|FddXE&pdVjPge4Q)SG7?=32Q zO_{zr*$KU-x{Q!{>Ud2}PAh#)ZDrfdJ@85^bH9^WsjQ(!W~C|{x>BugW&Vn$-ffNh z%*ovCj59KKR~YwzGp_V3D!NRCf$faTl$lXpI2OHeq1CmP%e&Cl?}gm^A7gD>&*dGX z%uM&f8=!6vKa?PG25!iSJI+vY8Bd9#(9Pu!DlWObhH@-|Wf*+*VH2Xg)pWtPpA zE^~-ldvym6QEh1l4pCFt8R|nTvlG`4e9tF(UW|r)unXn5KQHST4Q3iWFXPjx_q=Sn zTEp`)hZ@Y3`mL9G~28x z_c~L#jyz@Kc)(?cTqgPVpll-czpV2z8Dcub)OneVWS82CE)%%_0+@;}6ZpSOl8aaQUoNGaZjkkF4sWzV^X6AUN7 zc7vDdPPWIsE|=X&hOI8UldVI2-xrI~PBMi#TF`2|5@9^6uY!{KZlt{UWmZ4aR^N^N zhpm35G_$bng_$zS0MiRIWs*_J2M#>?n9+?NV#_C6C5M!iOqKzwl}wg(Rx6n->k)Xx ztzgTld@ zqu-+JUrlTM(-8f_M$O}kxz}g)Q!uzrs;Lf3*1leUF&mex{yVfZN+T`O%TZ6W)O4Yc z{sMXiiP@;=laW4HYR#?z_do7iif=>igI;^NhJ0Xdw5A~+j5ZB9Xx=`a|AAfGi&vxY z1^E_k1kvgXR=4_sF}xVr>I*hBP30nf!HjaNFW9%->Wfyl`r_5CUb?!~m#%L0GTUmu z4u=2IG`fk6_Mf(m_IE+!o*hhke75;FrpZ2={DNt*KNZmz%MD({2G2qp&g!+jYr|Qq z8+=xWX@hC-S!Tez;sVGo%-@5;rcV}{dquzjSvZkPNW|wneNgaQ8}uyA9{Km}+*LU@S4ZceA<=N8z~xOiQVI z_tm=huh4yv)7@-djZ8Loz1gUMqcypSYem5O%49w#`}^?2xzebMs(8=6&ye;^I8rD;q214cWDWCYO_<+71%&USbM`6LpYH-eoM z9gdi}O-Bn6+l*b-N^$ziNs_{HA-#W z_hQB?w(}*soge9Eoe{|nPxxM4k5kX1kQJCH z{4Su)YjbU0n``^pJmG6|Jw;(d?TYR!%URUCIM?RIxi&A(wRv%_&5LtwUYu+5;#`{- z=i0nD*XG5!HZRV#d2z1Ii*s#Woaw5)}RrY|qC^`r2ZAbK&M-gH+L67oKTy+2_f8X8&acv**G%(XaiI zHIGFh?FwBgr?b$^2Uw_xX(sws2q?WCQqn^2hF7!Do6ymu4~C8jPWm%>o*8E~QTnk4 zO4qaP@a*gpA2zNDD>zM$>*g<)orltlV!(0)B35Kz@;gXS`5h#v z{0vo-$8;kzJoN_?;uNINj0tL%kLmNBhue~2gy(L&|6-A`z6F8)!%*# zvB>xO@@vRFX%o_~A*KoG*N~v{Yl!I`d<_{65gk;14GGrx8q#3DhR~X7s_&b*3w3ncg}2KOopRB+Mb^w+d+`Gb2fKG#~{2Ri{=XF(900-5VA2!kIm z`F~+SFGc1DUjOIuUgtxLRM3B) z8u31|2!B~JTJ(FOZ-Y=vfNA!zL{!)^2zYNP57B9*rx9Wh*zob0DUqdHN4S<>1U=I z-s{4HvdqCdmXdwPQk4t$j$cHQ`N9-(xwa6}wnjfhXhG7}t?Eg|liPc}#AUqJ!iYhsen7BDL!nvBGS7#ySCK}w>~ zIl-cS>mWT-iyyPBL}TPg#Py!&Nl%}L_XwgtM^`F+Y90xCFN}n*x9S5?eKU5qp?(6z zBYiaH0{%h(yPBA8@gURqZllcNV znq6W$F)CjGY;S-J; zqAB*ui`U1R8BH}n8fk^^wRudNXX^8-DN-ew!SU^g)bQh9CjIzV!;gQN^y6O*KmKLP zAO8}5{L8eeqbXk>uN&9GuJ|%c!FX&DS1ZD!F?#X1ViPiaLt+-U6*mCL#8a5lUYrk* zi#I3eD4q&X8pKA&oyE%ldSU(}u-|zzR6lqps9i5j6BA>Sml=Y~A8kMp&YoS%ML0M@ z=w*IDXJs}@i?BAM+5YgBCT4&$dn2cb_1heqcqVZ29J(X!(hs4<)mJfLC~k7`#1flf zW@C0t_%h;pf3*Jx^lG+UkHQqISr-GJ?d)wosn#UO&30KNHM7zBY_~;`7kReUe&+c4P}?bq>e zED6~u2?cB7(UjS!=0bp>cHv~yES$0V6>k8i#VtQhO;%zF&TgXEy85H3f73oJG=P-q zucW2XO;57Gqv*Hnwu6~&yXnv2-x1dzV6wr>;P(i!pAHSNx@IU}-$3P`)o|?079kr; zI2^fp1u}l{)H~Fd6;r@0_ZuP8*!zgr`aQID0Jm<2^@8h!ItrtdElPbeK(-dfMvv5R zmY6L)D-p)L%ww2C+1;T#deG!wht!HGVkTNX#y&JUKYX~HXI88Hb!boYi}1JQWa{0-6 z7Y6v}u-bMj%#S<+EA%jOfJ1dT_{<6&#Id5@ZuotE@i#aR^=F%hprQLSGs5Vl`JZut zDLCIkg?~n+`3tl_-Bi3)@0wR|f0g&5sX zF2#v7?C?~y4}Y50u&_FZ@KmVv$LUf(oC-A^NOBOa7JpG@v^hK*ToHIF6^%=q3o}Lw z9ZrR6A=-?xm|BV+OG501z#r8KbQ5Vb8|}3=c|3CIek%L~XLGl1fekoRw@`i1@r}}9 zcO7cYQS121uUyTSLy`hvewG?|Qdh!oj@FgH7FfwKT-e2#(HmI#ZJC#Iv~Iao?cvgJ zUDC!c`)_`yI>l%@atf{stp85}D|tTG(oLCReo7ixt8?C)${9EN@MUDE4n6iCK`H5M z7#Gpd8;OAtQs%qgxGv_cD!E^8HEA3F0V zsxzPLCUxdKa|us&TWA=|nNM~*4QK85R%@U3U+vRV+Vk&y1rRn50JEgH(4UK1;b1Q!tE`gSA;Gt^ymTsL>@-5xdPsvx*kgrV1_d;7wx`D&h z^2wSdO4cki&Cx?3_%$#a{WGNGu3isF=t)o4(EI_zNn z6o^srr&FU&|8#Vn*2g-i@SjdszAT(Cicr6QIs>_Wjl)kkr&`*-<~(=@6qP4+@ zOSQfi9o>{oeZ1(@Xrx_g;bYVl^NHmSv1QniTn3ANFG%y9xXCQ{D)pOMELC(ra5u^P-? z`OuDT)_L8*bjU8{8#9=8j8imXZNJzV4u+s?wz~!ZC%9H}>|Ayt6#T&o^eA25Hpv_DRZu3- zY%`#NfUc@0Mp5vC>YN)%?F7H#AZ=e8J4f3m^)k}VGDQ#`XQvs?4)f(a(o{wJ>Z%y2 z8nStg&Typa&6YcN^QALV&Cv7W{3xvahyr_9<|tnlA5qa9meIY(N7RHb{($Kxzn~26 zCxe@j*pxL_s_rf>UY>w1YrX;LXzD9{qbg>XsZ{flfWA`0SaeeXO`FZUy7A>`#hd7O zb#XS49=EK<>rjMMRE7DQX>zNmfo{ua)~hK)pPJfwmTH;W(p9?#zmdoMi~q~w)x2}{ zWPWkAnz@w6vcd5PF^%C4lB*Y*?5*Ur8$S!49_wp$XSJ6ZL*wi#`$VNI4&bQVx~#MVs-!O3oXhBj_jR%aFb&rTq%)3XgD4{aYh0S5YBe2ae`;_FG%F zJWp5j?ka)tMHu7fG2e1_0^G2bmho&UMJx`F@$eK z)43VAPmED#w(y0LR` zZqz-Z)meqFvvEsWu)tAPFaTBTE*ZqnEv+U`z(seQsMdQ&7hQ%XB`;dmjafxVt&4VJ zCmozU4yDKMQ1yaA-a4*6zkozQZ+&N7I1c_xyGhTv`m*e9%^mc0RyYM_q}`|^FRqTf z(L`qRnn%2N)3G-p*5Nge2StBN~u5qTD4%+vDJvm!Sc989I@}&*O0O z9yD;Y6t{P$=UCBqLH9(ztT6c%1t+~JvfGf_{|=_^|%uf+49zd^=H?7>ygE8J>ExXf)(R; zj~Lp1H23Xc^U{O;slw)+hxTpQyz=1lfK|e8JnUm8mnbX3?pVC4GuR&SrAHCqD;UFM z4vbdtFd~A#;1J+Pu1@<{48hucZdnyh?V+zDncWD-dDwu%ZQ@;p&=3z0O$#_1yfT2t zn@7IKc_@@bx)u>ODH2+T^OpKNEtG@vRt4D*jah+8fLm^}diNciSC+8OWP3=hz)5Xx z0B2csdUCQeGVex^lar3(t$P!vr%GVuEJTWBpH>Iz62W1bb9|$!A(tO!-SroOy$h#cF+_XzJ$|gh=G_{| z;OA-+S^pF#W%R_7_DErrOzgr+6xXaf@f`M`$8TQTi5GI2{eBSAcFiz$`4^-D<`~nA z)$_#8$ONv*bEBN!Bh~qxTaWW|w{62q#rRl0<*Ct7^L8bJpB8p!ft}R?-D{mPuzNRM z%E&{kxkDBw{I@z`ho+|zb{ND7wd&3py^xC)d88Iv>RoyZi`p(qb~&g$m&==lvtGJZ zBU_<3G^GJ7vc@2hx)QxkXv!Jv3N>5Db>rsZO`AFz;lsGSDE)JjDdTlBs-NnAxwk6Q zU9*+ye~+UrbN~B7UGzD+|2?tO^uN4yOR?#HUDN-%rvG(K|LgvDZ8`T=>0DO#ziZ1U zayXa6{qM5!s}YpoX6Ksz*ERhwi2GmH^tmMtwAF({gREYSpcXj)|M_Q>#*{1RW;R7H z{vf^hgY@DL(u+Un&04rxX<#Y4Lofayz4(Ll;t$e`KS(eBAiem5%;FED`Yw8oRsXyh zMJBzvgY@bSGOIgGq6g?hPNY|NkY3$E&p<$tS>0h0?V_JJ(S{x9HR(nS{v?k41AC}} zYW@tg)C@QZ15R^}(*q9a0f+QL4KfQgV!TY^aimb@=c4UlrKQZTMfseRStP;d*tihA z)^OcT*~%=D;BZHo6%u^zDziX>&+&cM4g5P%J`XChJc7?d*huI(G=6PaI%giEcd?Bh z_b7Ycw5&a*BgBqmDC2tu$h#jgdkrYB3O;z>fbHFkCjNm2$FXvE>mE0QSBmVT;PcR) zQ5&NBWeq^g+ezLfd`)qI-_l~Hz;7FUd2EMLuc6(3tovbG^~L!o`rK6&IR8|i2d(TW zFz}$xFP&A!c=UdTi}778Ubeu6b+J=UjnUit&*+`|CGAG?3>muT@_EgnJH|tII(nZx z)`}a;-0GoQ)fl=}jiFoB9J;g3Vg=44oz-AJOCGqxY*_d?xF%eHP~E!hhSVG9WWkw4 z?Qz7XSM{8wJncG;cn4+0YY`Nm=zF+dQD21EG#t)#=u(8cbO7B~K*ZXoz0YEs5Mj~3 zNJ_L5NfmiG+B98@Sy1HCa^x1EUN{fZx7-8Ldyw+zZiI)e=&vl$%VsN#MSatHxzN{0 zTU1*cTvuBZ!_lUNI68C{q+I#~iUPC|DT8zrDMK_7N00imYWffI?m3yM1yPT zy(b<=q5__PC@Z>-i!|Bh6)MS|j?==cAAstv(B_z5&sw!dO`2{wt+WCP@dpN+igfm< z3h}+UQyF6)*rCJ7$7vlZL5vgf|A*rldSVm^-N|>BZ8U`Hd<#D~Z4;agh7WBIuQt*4 zoMqL$o1@RN*FvQe$cM@fO*uN}QJi)QjKrzUZN|!3frK3c^HKpe4+XYHJ-CH=9E>+* z*S8JxaIm~OrIwFZL803#mlMBU9i^4TZWr-^@7AEdpZ# zTv$6Ov34`2Wo(BwAw0N_TR8R~n^dA)NC>5CJumUP(2SUilxTSJzaEkE|P| z^}C>ooUs(>$O?7w#*&^jVRLEtZ?AUWHHeIGZhQ5!$Oso;uYM94VPEYXZj3*|#@DBU zvD)53enYr2%yrSm6Zw_3xXh6xoVBtmFHehhC7?JJ@S+5qmI~NrYmrQy ze3t>d*+VxOz7nd+_?4yeNT9*4E%#p z5#Q@0pf>{^s^Zu$kPpF@bgZ|C1C>O^TZf2+8sIvV%wI=V^fw~Bm?8A;r;bCjR@ zog&BZLP%U9nECZDL&kdMH)NNY`JFL{`(FL=4l+|dGE+V>Q$AO2xw}9Mnb{th$sL)w z9GSVCZ)T4OM15PX+)__qDKouut~VNZhKF61d8Bb#BPhV%TIq5D&My|+Bf+jH!8n&gzQe!JXls0kv#^4{V?-Sh=ZN~q%RUF`MwBvo{JobE zjjzF}&2#1vl~ZsUnmWcB71Wxey?p#mV~Cd3azkoW%MEGC7HGL4XR#a}^VKq5O>clZ z9PQQHU>ZNqxE@~3FkZznzkVj7V=|M0y(| z(%Tr3-o}XZHb$hkF~U#a@$`Z8Hb$hkF`}{XKpyFBj7V=|MAPBALekq9(OTq{Aia$d z>1~V%8#~}vAbJ}knh9;SNpE9BdK)9s+Zd7F#)x)6_D$-J^gHOhv(Yh--o}Xdrw4D5 z-o}XZHb%;9W2DSBM#^ksq|7!(%4}n#J{X3Nj+0ssU)@g1Y-6O%Hb%;9W2DSBM#^ks zq!!?YY6&T`jgd0j7^zz!en0jO?_pWLl6n9}{YGjf0*{kA-Viav&Y-6O%Hb%;9W2DSBM#^ksq|7!(Y9V}j9yaPmPdCI- zW*Z}AwlPv>8zW`5F;bmjV79BwHb%;9W2DSBM#^ksq|SwVK6RDZ#z-AQHGbwQvyG85 z+ZZXcjgeXapS>GY(_rqNpfcMSsQ_%*8&qZ+BW1QRQlBH+eL-cmF;b_aiR}+64{h&2 zP?>Fvl-b5enQe@e*~UnjZH&~I-j?-Hy7~*MA5K?h8zW`5F;Zq5BW1QRQf3Z>%DzlA|GTRubqi94kbCub~NOc3v%2j3? zBQiMjFj2N zNVUR+-({)Vg~r!)sWRIbsd^}Mzt@!6#z>iMjFj2NNSSSnl-b5enQe@e*~UnjZH(-1 zP%z%c2)6?G891M$wlT6(+ZfrYZH(;HHb!=88zXxis(2<#rM5A$2SFikV`MKuJK=4N z?9XB096m{HV`QhcF|t$J7}=?9jO^4lMs`1xa$Y5*Qrj5Wscnqx)HX);uechogH9C-62#c4`|VJGG6Go!Z98PHkgkPlAP*DIlLp)VIPm zMh}70BbbQ=6_1d1v%|a+ZNdVa(^Hq@Km#WsCGEnwO$Tvw=w}@9(XClLu-%W?Ag#tR zMEB2!vuHPtVai3UPmOSl&{;S}X#kFCG!DmfnuBAE*3Yo;nZw4Dc@TPPB5u!UI0oX{ zboeS>!B+r1b?LjAm<`bQsXYB?HXT1Qpti8BA@Ro*8qs2;Y(g*0;ZJoP8jlCqbO}N# zX$dT>qW%a!gQnrwhW>!Ib`*hZd#a0L2U>+fcccfPrxR_!u`@k68&@p7eJw6n+Ho1~ z#^^recs5;g37%roQXG3w`-}Mf+&1{C7k!FjZyE;6`_P#_;C@;5p**EBHq; z&%mC6v~`MQokJHw+aS6LxtvEY!UIES?bZB7a0iaV=rbJ8r{8cKPCjN;Bd8XRBdG$% zQPc~^3+O}W8BIRYjG@}_%vj2VwHJ~#53@Jgi1YDu7wnlp4(GOq{~nvms1<~XBKTnS!UA_XqZF0py5hd z3CriwCD4BrJp+5@QD5k}ntI}P=Nfts;nz|Qv|UFRK*J4`3;j3Jc=+vRS_aGSqk%ZT zpDu*8OX)TEXBj;O{SVTQ({K|@zv28T+5rn!(eevxa`d@i|IEj%%qtj_W9a zR=1uWhRqx32X1Dd~~r(yrM zGzR*=qpRWn@97a7f1o$fhJU2PIQ~R`;rKIULh2VH*m;b)Zi1b=)|3-Kp{IUHIYz7_fw z8hsk6`Kae~QWoMeNY%ohIJBTDGD#)zCyUe>_>)a)ApYc#x(jZ}CAAtR<&pXY4Y@C= zSJ6I4lKK@L$0$bJ5sqv_Sn@R0QtG$I(8gjUm)Kw6_gVbb{ zZ!xL!VD6o8D|~$y?h#?`-K3&WhPm_rIYKThgfq+CfV6Gl8qY7&fi3dY0g zRhaX`>ZeKl1-aFzKN#^WsZU|j8d8^`2|Y*ZYRIi6^(V4jN9uDJxPg?9vOiDiBBb1i z8v)3@fP%s5O{5kDkA5I~dO3}2&_Z$YyGZ6$RN{=A0vi5#|( z+Ksw>9kl}Ex8u$M`Mp8vY#8w-sdZ=*J4hA7Av;MOff2h%JqEeANNq#Pw@E#TvcE&B z6$EyZ`Un;NE~!4S>;S2wu=69-3S96pz7@C(*4u;0o*hJU{{nJOvuqx2!@R9s`iWY6 zNhEOTxb^v`igCS{U|jDd7+;)3haJ~@3C8tag7JY7bl7n_jt)Dn_Y#cjy#(WWFTwa( zVcttHBzp;-gnpk&oEcE-4H(oO-x=+Kd_uUE3Z2CWEa-_BR=FHj&~wBER&B>0fl$aa zbhfcfmjPB|ErJ{R=6f*aI)$8=$SDV%CWIf^)^m=qx^t{DQFjj1HFJE<1h201o!@a1 zWjm}WYlc^{KR_SQ!m(K}i=*>;AT~dSfA?`7R@lRN76~5IJk0?_@1wpK|u?LYkx@+i8Y45^}tbJ^NTHsSDydA0Wz>sDO8N$Ig~#qJmc1 z@3l4|*Fe>7^nkUrn*!$|c{u6UMmWsMNTz47YX@3cMu@!r1FT$guDk(#@l{!!52m4r zNEmRvUXUm;5O4^tEKQn1A=7BGDRc(TLZ<0Slj-*;Os%BP#vs$OB=L?qYS-7Awnn01CT_Ka}$b=xkAFJBy*HyO85dM%j7@xz12rNIiuD&L=Rrw-5|z zpS%wF1g?R6M=|6pXzr8r*+3XFD0u=2oDU&3Si~%czwvvX5IKk6!rVsD4vN#+I^Wc<>+C`84VS2Z^BZV{5bWxoEY5^o_roaz#jY=q>Bywd_QI}l$=OKY zJb~OMh?wO#DELGnJdXrjB&3{w-ova<$aYS?gL$8j>-0i9nIeSDMJ{yJ1FHdGUgCCs6@!Afo1*D3~=p*&MkBX2Yz@#H@KZzdGr&xiD){@@u3NO@g5wzqCE`fab%*`2K0#15}ppZ3-r)j406dP%X7KxtgW!gVcJF8i3NinDkj2q_!qs$BFX?0=F51c|3U~ z`6Y{S=w=ZsM-{xD^jRIm-b((%ViA<#on%1|gt6G0$)X&Hap=xu4u=Lh!}+_DKC6S+ zhsg;@;QR)|4~Tm#XEx|#A;&xSoG#WU#{aH!5j1_8@*|=;TL(=P+ST6VBF^k@NPi$U z#^C7Bl0F-O%#J2s;>@Pu8u-fCh*72m?D<-VoPSZkZ-g-J9Z7z|Dg(HDzYvw*LH&10 zpR>XXgx_k7%Eg$+qZdAmimryD+pT$U3oaPt_8p3HTl2~W z;G-yk70JR&p(q^XijGCO;xeLK5%DPdH8XY><^_R0$#?=eWkuO(IZ-Z6u9fE?h=ujI zioIpoqUh*2G9*f$g>#V_e>F?BK#yqAh!0qbKRS=^HP6GJ@Wu9UPQTz(E>kvg`eBH) z@JU@xKMR&9stc9KSMGTi{3|GaK;D-hZot~IAy0(_S_uL zM|5pC*rI=+Kv64L1?!7Q9yh=mJ&G-=Tv<7?_dJmhq+U^Dgjh*mI-rqRM zc@4$inq*I?cuqrTdcBS=U{(|U*nW6Nkv1wjrw_{YR&6ek%E`G0+3ztz1vz&`h z7wpr*aR_nTIc)I3!kf^DLT*=%`JDIRvm!3Pm=AxYAKIxBQks1Rk*TV!|?UktEfr*o<-imw7WG5#z-xHiRigF>-~ znNFkl=b%XJ(gUE@hGMb($RymE;{PBnE7qG^OJ5V07rTpf4xxBS5tgUL`fdYVVB$)x zTz-3X6@-G<^5GU7tVk`?MVJF4Yq)TW_>67UiP&37sy8|Ipb0-RY9ZpC2^j1Ugl{n`Da$v(s;)JN@*+pcR1H#jBNdFl9 zq3PNDv(_TOehDpN`2swa9S8Y&1p&*>gc01;;S=f*_dD6VJ}CW9q%#e{@A@eMXbsX6 zdE8Z4p+#ueeh>RqM1(muT~%NIe(!iOQqF-qwm85MPg@~`>;G!hp+CU>0qHZJK~Tsa z)EP-#-c!XNoW~x=%VGSm%|9=XbvRb&QJC)!u@fLX8PO|{`r$l_51FqbvdkY{7dM&i z$-_u^VNq+Su-va$YFrVQ7vEsvLX9utD=*~UkFxp`irC~x?FmyRS^h*V6Lqggm*Zcg zzp9hw60GwlX-IefVr>^|h`E=tf=e`HxQ{VhT8jT<_5T~Ib?BUt=1qcYAg@9VUaP|80B7JclJ{N~b z4?Y{kXI$#=ML5gsgHp7Mba6G9Umi9uVbAr9#XfH&%B-jffm#^JOw@i+S zxcQKeoSn(?F*nZ8Go2M@xo;u+NUwBGmgn*(BqO~w6uD=h?}_x$Q0g9InSN2WsE&I+ zH|G8t>bh^Rf&m)pxu39tfg0+&<*eWw4Q1{hYXRqGo{w@ja23Z4*3hu_*r`+T`*017 zTo2xk4AIco?aIl9YG~pfh2tW_G@R!C4^1v|zJ{hQvCMD{&2$Y#M(G+l-F=T0T#)2C zsMOUJ8LMlkjTO0!d*Q9`BmP2r2D^A2+EXCfq-80*`Y+T+n?|`cT5cUQnrJg!4D2g` zRMF-dluK|*w1o!S-36yaTWWCJjx2M!1{Ys6;dHI+{qTO~aug#F9d#aO^Aal?o!~5C zOg0=D9b=ybD&h4v%>$f&;m@$Kvi4h$E&K}Jttw&B!Utes$9!%;EppIHrk~}nL~xL+ zF~}1gt8^{AGK+iAT^unCDT7n^FprZA=8}~@jU4B4lCP_i=-98(fUMFe3N(#l6{bo? z!G%y@6>a1`Aq|1WR?$LO7br02kHaRno;jb5B0DYgd4jk4i6#nG!`F$>8npHVZ`~7a zIR$CFfq`p~s?Nh6Sp)O9dDWddcAPb^fo^I1alV1&d|JrA0UG3UT1zKej59q$BkS}l zV5!$P(5fvfY!R(HYU((vMQeTKS+Cpzqbw{@X^i`RyX0C}({_}5J^37t6e6zeG->lBSZ&)y?WbrNh$E?X{>ol7Q%D@v~ z>nw=z4HQMddIwDg?FSm5`a!W@qw{-M!OGhuabo6pdM=!T@ z^m0o_FSm5`a!bc7w-kMS)7G%QMsGm5qt{qEdX1%{*H}7wjisa4SUP%*rK8taI(m(z zqt{qEdX1%{*H}7wjinRYiMHYBHI|N9W0`5zuW*exJ@~Ukj$Xgw==Cd(Ucch#^(&5E zzvAfiD~?{j;y5GGG9A5s#nJ0m9KC+U(d$sK7Te#O!2R~)^5#nJ0m z9KC+U(d$sK7Te#O!2R~)^5#nJ0m9KC+U(d$sK7Te#O!2R~)^5 z#nJ0m9KC+U(d$sK7Te#O!2R~)^5#nJ0m9KC+U(d$>7|FeGO|Eyp6KkHYP z{(rcBCG-ut5njI%O08cBrPi;6UK@l#k)u-US3;@vE1}f-l~8K^N+`8{B{T>MdHqT# zwSFa(TE7xXtzQYH)~|$8>sLal^(&#&`jt>>{YogcekGJzzYsLal^(&#%U>L7o3Ecs2@cNZdYW+$mwSFa(TE7xXtzQYH)~|$8 z>sLal^(&#&`jt>>{YogcekD}BekGUJuQ;=a2hL3M=8WI3xb;89xK^m&oE7RfXNCIB zSz(_HEOjWd*xfN!n;OPnrNrz6f!>hr8%0jI(P zl_5}`7rcdul-5@#=rAcmWx>iNn45|2ZKVL>Q~D~t1S$Il+b~5`{CUvGU_(wBH7PHz z(-EJJPgCrXD}skPCf&r$3*O1zikZBx4enveFm!$JVb&NobW^Z<1eB@bTcH28=q2f( zEE9((q%9B_$X4+^`0J?XAFL z0;9RFik`+96`I(ADtbD{7Ma+=D$2{d1H}f1sc3uFoG>_2Mb~rU5`$w@^iIZ7gX2|n z5nENu;3O6OnlWi`ii-B(N~vvdIv&J64(D+b$lcPd@MYp_IGO|WK}SEAigvBEhdG7=^dXC(&;ra=SbW ze8WBg{aJ4y!4T-u8KbD&9O4|HOE5hZgXipHIEDlMUmUVlLG7B9Fw{Q8avYGw7VS#K zxK{i{4rGTPN(H7_Y474Z&H*~+uT+dLh$#9e-oyzhs`D|{VF}r!zQlVuA&2<$#Zw9kwZlUAedm}$_gW~o>;HlECxv+& zZvXzdWlb&g9fWiKvkJXFXvTCMlFSiB7TpAzD@3#yG+#*3eV}WFY^q5c@ zeFIu4luo~Zo)U`DU!c`Oc+Pbc6)hB}Fle1nCN%>+FO)?e?Z=W4p=_!|+{;2a)DE;+ zD3^{PR7fL1yM>BqJm@{4V!93Vflz{$fc6WOpt5Ha zx|gCR?Md+EOsVX?-{TEeq0fzgEBi>H*9IdQMNZ;9lZaZB3HqN9J{Au8Mo3XD(Dy<% zm4SW|a;Pcjn2<~5pyNUTIurD#P>?!-{t*gM570>=kG}W}x6VbT<%j7zkSpZVub_}n zg#H2fLQ!%K;SO6UjUu27p>)auWeLTo2$U<7L3Ka{LUC#gDi+G5GeD(6S=13!TPT}) zfa(e5&;U>ap4HE58KM-~6GtaF9J)D|>Y z2unCX=LtoqCuoQe7XN~V3Z>By&@iEN8U;FEC`RK!!-XfRp(wqKE@iz?8m$LCFO*J=;F=eNV$=e(NhpJ=Kraf#sU7Ggp-k!udRZuodV^jO z%BFKbuL|YRFwkb9T-xvn-XIHcRoq|Xj)I@4E!fa%B5DQm|{at9;)K^B6l(TY@hxECTCI=YtR>z z6#HC7Tov_-y?+Ye%}>x~%S4eydqE9^h-MzZlVxXu@4nir`U`m*Q2p?FZQ{LxGMS=d$WpA6^k(H4-`cf%>$hyM6?lf zu8^W~p2C^XC_P z$BW_oC|cAtB5Khe|6mRyL{uMf3xpIUKnsOzngUuRx4Y|8Le%-Ar+?O z7_2r(9442z#5M}0$9i?LUNGRqXeJu>i$b}y3!VH+hEyReeX7{q%9bYaUixXVbQ3aq zrP${Zu%+9Jy*4GV^qfxCo00`X7i)(Q(Q4GiF3}pJpFhD&MB?I<`6*^1LYdSZHTtfk z#3KU~aF4_lP#@5HLTuZXVs|()w!cKZzb3ZTN9+8c*k_yBwoi(^v88CjFQKD7XhiY8 zeK)-EnJ9887t@H(g#tA8Af^#Q!C0U6ovkm0Fgl{Tjv7+c>O)`B|~g4rE8Egg37i9A%@3 zZo*6|ux~afDCAKT8Ab3t?skY9gd)F6cBN zo2~&h6>{i$P%|Ny{>FvTTqr<<3!{ZlkUm6*&@xeknzif@*|?r73=#H<#3fiMDPyz} z{dQ}i4Eg|>JZg>>)lqa7(Hu;)O!fvaZa1X#I_GGmB`r@`As;g_lXLqvOdMCWcYolA}(5ac#S45ebTm6Ix)WYg7 zq(CjL0YWxizaN9V5PlbZ5`(-D`h7U#JVW?oTog1!C?4zE-x?~AMcJ@vn26=j3uu-j zBrcEYU>-bL;tJ?h#Eq4>B5H`Z2@=OwQ1^tp1BJ1#M-BCq@?M5(^`eB&e&F&>OL!ye zz^yajk{Ke3#fYek%Y=yLAa16RqWPf9g={*3l(U2!T8OyWLM|1cnanYy0#pLJ!Vnt9 zyJ)R*C1r$K9m3NGp)?qNNy5DvR@v(yGer!a@E4v*Bz!Iq8@?#v-Oq*(g$HglqNV5r zoa++q%Ph*_3q`c)w-~k)KC5KW#R+d8i{6e-?5a9R8Syeu_)w$%M};S@gMtcMps1gQ4qch(4Wg`J0qBhd(2tqcH@o zPx!2oMPEvI@3H7ATqv*95Z#z?e`Qe)-z1`&;Qdzirs`ZztS|EXv`#MRXau`+W(YRkG-(3GW&f zT?fNHt08(I;XcNq9R9J0K6ey1+6kXkvglXXu98KYz_4#>h<=`M53wkRe<`9@pt*dT z@L45`9!q$Cvgi&N_FE0n9};e1eTZ`SPa=8?EciX)vq~2IH{lIOlGwmbozbD2G0CED zQ6)+U&m+(jY$2CgB5zlS-~IfRaOZI*9WfyOBboewSwyhJ=gc{iv=Z-LoYJ4@ZDU5X zlv{te#C?%PIXqHg28Ly5gBc}0t7Or<67PK$J%%I&HAJ&Y+~X|D;W;Au2|A9#5}#GF zXtKmhFOyvB)DTUSxXlr6-;MsgR75{OldW6gvq~0iT;g?S(c6&Zv>KviCGI2^odP;m&$)Xh{-gP*Q4d^ofOEvWjww*f@wAh@3q#U8usk=FoG zgeT;P8zgZtnuIHDu*C5_d-oEzD>T@B4x{&#Oj<&IXo=66b0(upymg#O9!fm6I+Ky; zbH*8R96Eu{YeI=0P@M>Uff|`uo#pjth8Ii9EPOE%H)le5v;<|FEOJFKXLyObkIlIS zlf02)&bxo0e=YIZOg88860cuFm@}QbaifSAp1`;(g&dlVxOqY$ng_Z@2(NjNa)D5c z79ehsP!`<-x=ARHZU@~W#Kui4ai<|?`&{^Hh8TC^YdjP#@!4oLZb^xE9~-wDBgcIr ziubLDa8D%UK+)n7_a#;|5{m8;MGG;~E-&#p16H)M#B0z9ihh8#PgX1X4fJ$M5v8FW zJu4KVeYk?w3dQIkXoFA|eTCV`3qpCc67-S~m+O%dw+HgF|Ha_-n3&T7IlWrqvzctp z8ztT?Y))NF%y)<=?pObZdk;hSeee*ph_@vUADjIOy`{uuA(O2o?z5c9TbPw@lT6OU z`JNJ=Gv`e9mv~=tCfA|k`N)XkjnbB*cxWjUqL)Ai4Mk#5`+kYbD}3!eDDOT|`zzdf zsKn>&Snby(-ZCVi^>|$MZME8$LEj4zy$)U=b=q-3Q zTPTAbMqI8?9=(CMJfVCP$}V;9g2nbQ^fGR#>Df==Txv*TQWU06DG!$wZ#)>*3 zYSB(mJt3l(zQof(Aw>(&TpI}4bTg=tkVEf6u8ELKjnPvyGo(Va07kSB3R5dIidK>` zN^L+DLTS_s#cwSXqXD2cLK!p*Zfh$Pr_WJC?SwMv8&C(KEV>PHorJRKdem!Ip*;E) zJz_VZe9HRqo#1;FMnbp zZ$xqLoxt^bt`J`veM;ThNM+APVf%@qo~W_&N`20N6zrTej)#Zr2x?%2II$r*{hLaCcCHopDR@Dl_i}UGzw<&HOD}hE z^g4);enB45Z%$+SrCpYOUzDd`M-=HN;idW^Y#seHuuMOeYOEjmG}8}PPS;NkD)mir z8-35$PTvW2(zg}e^c_M^J-HvF=jr41lzWn%Jx|dS;puu#d%2#TUZH22^YozCo@a+ykxnaVmzwn04w#-yGoC7&*}kcogNo9>W=%RApg2I zc%&rr0UvMHbg%oa?!w*=79b>8RGK*pfA{Mi;E-;@Uj+BmLd?)oepY3DrCZ~7R_+yO zNx@r6+4FjN(*gKbFTV;{X*+Np=KvjZEER)aPJhlZ9DtVnQ+@BvmT1}C3h)J?`l-%y zWIFnCA)<2-_p6YiVW8iHY#I$ZE`;R?px=dDx)k(>P=GE6{V5crt3ZDVp$`K6E#%R` zQp}Zw!nB|SFQ9~cx&>sF89O6%H%JLZX&J~7N~1HNB_NbeHry8yiqWe`85YVQ{@GVV zC{7a~mnM`+kAY%BS@bk0E|g8{L0LjM^fD+%D3|Ic(d7%}Q7ce^P(Hnbltn@Xv=5XJ zDx`xpdNZLSdO3*aKtjd%P7B5Yp#*uLdP4j_gSb71Z4i_06Dic^J+r^G~3z zxw4ya#c2L-*UsC2hT!G47R)q0IL@jy@bg2;0D$rCRMf}6jX+kz_0!c&<={mLYDQP?T1H zt`n6HEkarJ4(K+aY}yC9Lnwz1 zg6Xvd_%L`W)sBF-)La1!e8X;6R=s6)& zHfXI7DjT#;2$c<5FNDelZ4g3bgPs>cWrH>fd9(qo`vsveos8opkC0EnOsqZ;icmV} zRiP;5g0={y(Mj|cuL-47UBtaE6r(1fH-s{%6=;W0oI0X8?GnnQP!?{wgtDlqhnp^; zY|2I49-$nnK-^xTT&jb(4}|ilG3Y~~eEJ^w9S|y@D#U#(R7mYXp9&Sx*`Uvais{O1 z%Q`HSpzA=N3vp#XQRc2eP1^fV*-uGjZ$X+b%Y1GGT-iUAMXxvmm3>7553b5eF$chn zJzWF(S%~Nc&@V!YZU-F`vS|tES0RTU1pOxD(hAUVp#VJ%`duhU>p*`9h3G}lpF$q> zhTHxU3e%1G7{P^n;#cYa3PtFC5N=eo)lupP*C?Shx)9_D;rpVXfKZG!K`tbeL0ds# zp*Y=vlo6p!T7}s}not(41I2{0=_OEHD2KLzvV?N!El`e79`Pp)@`UnfVh%=dp#myH zV=fXZr1^+T2o=#W$dw8e(<^xx!G#jE9aKk%EBl)=Zy9RRu2qVcb*2&6uVMyJuR%ID z0{n6$*rY-9N3QH6m_jsdP`VYNsO(ip)JzDU8^AE%Tu9O9sF;>QLA@CLbVDILkW>vC zco}Vw<-3?+Hfm7B`fUE4bgKsGYzmC}s?4p66xrOyvN>-nkQMx<7k)XIGXsqEF| zc!JR?Pg}GF=byLohaj9={CBOqOWLB~JWKtdRn1xIk3wda`je2ErT#2rW~sjjnOW*F zAu~(;RmjXze-kpZ)Z;>CmioJpnWg?AWM-*<37J{yKSE}f`md0grCQ~t3}%+9gv>0} z5i+yXfRLG`hJ?&4H7sOisSzPFOHC6pv(%W7nWe^s%q%ra$jnl6gv=~8Psq$t3xv!p zwMfX!QWHXEmRc%gW~oUbZt-8Wa&JRT>RIYHtxnBS>y-Q42)MEvm3t?+vg@I{Yhpz4 z|wPMip9 zC5!ec_om^LUVz4aB8n@FdX&3&vFP1rV)iMbKcn;m%6(SJm(I{~Zzqe+$F1G@<@(aW zBkSzem@pb5hZdZU38SF^U)txEyWg?ek6U5_T5c|+f<~AWmiwF?TXade=eC2|i<)3k zXe=VOXkxirAK`X`#+YJ=MT3#`)N-FyvgoXGuQ!Wwu5*ki9;S3giLW%I0#G!g+?~RT za=T$pD2jH#xpT{X&VUsyDEAhzqTeBUeGMC~E_a_|(IYVVS`j^j%x@_7StX0!UhZvU z(X$(34NeWwo6Fs!EXv`xis-u?F*7UoStW};Sni!<(Pxn4p&Fw1m%FvvL$m^s4~S?x zc;}IFpH;Hxs&cP2l8}qT>KdXe%iUot`dlYGd=}BMT`}b<_gN*2ZY=j^u;_0n)214t z>&o4GSach@*9{`t1i8Lc?z2i3eXZPkmPH?c3tq1w`f9oR9*fRJ_!bdei8lB~xz8%O z@w`*+eaoW1pb5Wg8i=1?)60yYSjvzae2Wi zgkrd9h1f$vHZ5(34qV8k-?*z5;uf&4+?~pqltX5Jc@Ar^-$z6LvfSs)Ig{_py~jC| z=4co{nxf$fkE8rQ3psQUBELwngHZc*xx0haj)lj*m156CT^=jp^doyP;6iuU2G8vA5juk#<&YASA@YZoAub}<)Hlk=6 z)6hBgt)Zw}g}aXxjY9_AMbTAd=wvH=&VUu2SKB6U6t6Pim&)w{k%A)Z0`5pK`LVT}~x02_+)n)TK>m4M>sAIcKvDR(GHx$|C?(w7}h94Rs$>cnewGx$xbGqV5A!^rsc+tb|3s zsE96S(bG_gM{9^4s_?e5XlEopBBG@z#8(yRtP+;&#nphbY|c5Gb+Edh(Ef2s+@^jJ zF;4s)+CQ#+dj(whgSc}Gn$xdn|04QNh1Ug1s3mgzHzi6#IkwVth5>4Z#!Hoj+`AKB z+J98I<5}$?beVsN+Jk6ns?z7|*do6&`T(n41&2i|rK!;$xIWVj5uPsKLXTCJRI3eE zdattDN1)0xncH*FX=YTWb9SsYuQK{8s~v-WzMxv|^SDNfs@0x@PO!L!+N?@1=WM7w zjB6@K)HXv4NK~eCb|{Zq={7`)Y_>R?^>bGBD!ma1q}gzPnTX*P9hykPYRB9T$26+p zm}I3ppR=liYOPagMv21>(8*T%oB^wCRTIJs;IHs#5&^Sxb z45rqo+6k5JFv!@IX!93I)h>nnv`U{d;Cq=XD!toT?O-&nxs|CK*9$;b2@y>K%@b0% zC%L@RUCU|@AoJOk=APs|wEwFsea?=py|L2!iq-BzqqU56yp6b)%!p2JP%-&K9oBmS^FaD<%UP{#hT?Pd& z3)yroI+Is~9GZu?SA|@<0kl~tKzD++2nA^wXsb|&R)Ss=!spy@g>4fGQ*Cr!uM7Ef zCOo%YC_>#pZwTQxxS%(M(r7qnhfq54RAQG<22Fx5-xkWDnV{W5xpXyXk5C@n40=x} zA45MD_6ZfyBcOdk#T06QNxcxi_FY%$j(}(FpBv&nM%wE2?J)LL`dleoZ=Y9s3)uO? z(5Svl)f@H0W&1xNzMKB6(p|}lIMrdP#mi2^FX1YE&VUvDROxMDMUUai{>6wYZUEm^ zx}USCjqo2tv;uAR*GivNvgqHHUbqiLTjL5okrJhUP_&bk<{pP__`T9?j8t}uMtHI* zil)KARONF9tjMeKI8u*&rE+n^>|<+Dl_&93t1v1o0K zqq#;@Ptr1~+=p3oE-r~o5xotf1yw$)WYJ`m$DclXiA3D)(Df z)EvU4qG&42FRSu71HP$fUgcfg7mAjlpKV!X9>`hrAgEjjyIRr#!vMMqV6fqoF( z4$;vmQR)X8E5sepuqw9iE$rGxjz>1#GJFx#(QPt+F(JNFGto6PVWqz z#6oQS>%7@F`{4V>-~!#D#p{D*5?VB8jLm7Eu6`Jt{;SE=|M~6)hB5!-C8Mr>_L9|^ z`PEBqW`6ThxtWi7`rS(v=3+>Hc&TVgxHkIJOU+DsNPl^$x#rZI(aE?l2~tDyi_oGNZq_tW?De%;iYoZ8d6U$RhTDm z+Uez`qRC@I`*^9DX#uIfm#R!>NQ1moGTTF{^AdkMm#C9#FtUjk(Nn2&huT$`*dcW> zCxxf0;dSY6IQY9^{~S@*bh;W3X_S|6^$cl@ml9?=q_JLde~4*(UCpzwrq8~1u9Mtk zxI6}zkVEU-iKYbxWkOxdP`DHBU6} zv1gr3q1hD!@C~QVo&29h{=mAJ?r8R~y7Xx@`(GSHM>y3auNw}jlN+e|2!?oyS1t9$ ztAlkhO;UAwUAnXvR5S2;g7+Gjy|M4k^pY_>;O#^&;Sb0R#M>EO0>&7tbGDa4b39hk z950F43uoMuyo5gug`qgvOYGM%b;XE&iNx;fNFD1>Nkk0oKgFC%W zK45Taxb0y11C3nCj;^Ql^saO#YHaRh;48p~_mqJ`;;DqQUF$ZFL9`RDrJc;Rf)Jq)n6?HNOo)iDUME%PL zcQZQhSY6DZ8QjXc^a~7b1DZVNRRhx>eO~1yJgSAue|yQAPH_3WmlEbuxcrZoLbDo| zn5(@cCWe(4yp%K>F{&?miNQTtC*Lr*7qLX2_Q7@PjgxI%%%Ba$0 zH89I?P`=|OWAM}D;9W0SvprVCdtOSI{V?M1dxSBgM zm!H(7m(pcxMEjXn4b0V$KKBy-vKySN_mVYP4CohL;)?jFPM)KaPvPWa@1!|Tz;!X5 z)5-UB=^gfilOlTZ;}$1F(E0z{;^c0ukDsyN1H<4FUNVNk zgbgx)cXz$NHEKXsAbh`XL$$FkC&Is^y8JOTD~L z)rT=~-Ms1y+r$oD!uE&B-N{P{a|c=u z^Ae-&TQ8$wFR==}=?OuGsb0RJlYcN&dwD0H zVeuYXAJaLV995qV4}_Dwu)vP-W*Oh%_0kFDiAOM9)0*N#{CaF57KDRqnpF#|$ z)a%`ABc>A!o$4h%{G3^zK8}X??0%MWkT?>X#_9D1I-sF>^|>o(=nAZ{bDb)lqtom{ zZ-|{avp)R@4ZVg|XL~~{VD$X@0v({mjCy$)x#oN2kyXm@YjCd%vU(+AK{HNGz0 z=nZ|0{B89GI)JN->tzOV%^6j5TBPxN>(j3xTSkW5{Z0+{Gsa?_KHw!|zQHc|pqH#! zfOYV&lWYjR;1OSyEW;m;f7A;cxV!4*N7zn0idAs8pURCG#K-Dm2155M>(gTn_U@na zs?Pl?FFE)B_L6h|A168Yt9_Naf58iM|75)!58H_gum?Wv-S@$WyjUMIEV_TIK7AgV zm^ZMkyyI0lRIk>{omAb3_42w`y%(zQ)yFhR)wT8MRaCtMms{)V{nL4!tP(sIJ8!`=$3fA8X;;`j{rE`dfYO z3^XzCqxcU$`*?)}JKmpOGUjloZ}L)Te#64r>?J81jz1vsx0jM-8@j^BVw$At;D+>Ss*b{!*7|J%?%yCAsLJ=h2YS^qY~e#1Vw$At@P>3^ z3RIuP${Vqb*PR=rBgzx)F{DGi>RC7sjcSN#lByFL(mPO<(4C1+HO0P;X^?}c+8w8` zabESdopA%MA*M;H9@3CLm#Wv}D4goOhUO92Kir4Uo%4VOxt)gAW9|>~hWexDM>NEA zKtsnhq}S5WdFbKvrtr;NjQ$KS8S^RXW;SfSDSA|c1XE$QW*6-E-fYE=*qj?;x}(|C z8q(EhV!lG}&uB7>h)!ydda8DYgHycfDL4eq#Gj)^IaL=nqz|F$0vwMQG^v_9ab#TB z6cG%~YmjqjXnV}qx!%wTxW>A;A*KTwy0RgC9SsS>zq-i~R4;9ir>XiVX6$mW8sJ{% zwGA;%QuXGBblG80?Fg^So4lIKFbB7K$(ka zdx=I^Sn6F)$JDK8h#3l9-rtZun=boeFL}_b2If!1^{|)lb41MJBVJ0F{W05*dMPx! zV0Ay{CAz%3L2jYT)kAPk&%3OLwI>>4hC-LmHKc!~%TE02;8g?j4h%i-C1dz|=ha?H zn6oh2FL)_5OVRR0FVW@G4N`SDTpoeIR(hAu!S>4yF+-utw;IyBqlsC~ecG!AhQBF) z*GtCygk|-fmw5O0wFWtkX8()h`VDXPI=J|tA*MT;UDuF)m1d`61$?^2?D=T)*%q^J zq3-i0v!)hK)_W;oEo52QUpI@pVJYz!<;}4e7B* zAb=XI>;Lnrf%yi~PhK+SXDsNSy=2X5^!XPrB}~^wd_C||Xigf2uLoXY02>=*I;=3v}4vFcGW^+T*ou|QUEqYSeV)jQ!Wn0Yt36=6Dv!-%5_I58NOfU4S=%vsML(I** z#D1lR$VgaEyn(|d9^%diccV>h7zo%18;aWVfQI{dIlFF>JeM>MOZz^-b6g`iK6bkpn7Lpmj%m#kEt!zwaOI>B>6myQ^LFRnu_SV-j`$YUJ{?RQ1inQ4`8qL7xHzaY}dnepl)b|z}qLH-orE4`rUo+f6-wNDOU+HVq_wja${wkqW)j+ksb2KRp zsd}KsHdJ4`8=-H>jfx(^3W@p+)Siyk*WY%FYHCn6Y@kNEd(?^2aA#?ZzPmOq>dmq} zoYr`K4Q+zHQMO0az?vfm78he=Cq}zcI?7o(NM9T~Sl{~5 zV+5w?t6oRzD^|zo8&k*Xn@Y#&TSCX{OFz@2E-j()tBY!ezRfdJ-*`DuUtpP~FL}(? z7bWKCdk-f?eW`KcARUpDqa7&C8dSUxah|HLFf52hvh18eI!YHr6DiGe?HB3W2#cd% zaL`7V4bsuNR9_{yOrP0b9v#Tm_qo*K(6`Yi7geGvDlK1KU1`kbw999*1+!|n4dABa7Z$bHYkCkE^Atx9D13~6;D%SS6O zC$fB0@_HioC)=31;^{P>$nwd>FAsA+vFSwDv;sa*S`2f4 zvvg{`M%*mS@+)|YFw5_^m0|XPgK$wD=F+&_i0*Wn)nWEEl$OFQzo*rNxn`_<*;Td- zv;6whD$Me$Q0p+uuQhGLTpPCezP|W7zWB8bv-~d57-o5Gzf+j&#>!HIMzC|3qN3=4BR;XE64c8!LIx!ovsX(*nJSsW2&dA&Y2%<|g%%rGZ7twcMzwr7R8 zGK!52#gi~`=Y&~aWiJYIC(^=h4LWd_U~o~oILysu>AueErD5)Tiu*Mb*COuA!YnV9 z?+LTK(7iXz^1}4KFvqudqqCi%`@<}+IUfjfOIdn}D}6A`@&fXqFt>uG*SXS%!z`~2 z9|^O(UVAjm@*3)~Fw5(j$HOeIL!Jn;yc&2i%<`Q4RG8&C^lA7&@=TaJXDF<77@|Y8 zGR$2}vEvYT)P%WfD0UiBT#s(ALIltW#QorW3Pw$TivCcL=V_;c1^QF;)0=8?LH=0Q zu%L3-PB7JP2+vu?KW{+ZVnqh2Nu6e6?Ou2>^5M<+G~uK8wBc*`OoZ$48HRu1Q^N8^ zT-KfO8HGdenF{y7XF8mG377OS_>9A|@tF;;#%C_P8=v{`-}o%pk&9v9*aMLmV^2h4 zjXfU;&>l<9hYw@tT?i+}K7&HgecnY98M_fl%2<0T92xs5nq-Xq9Z76#{v!A?wgZx! zv2{rD#*RZ$F!u4w;LqAOkU;xOB-Yx^ND|f-FNZ&CyCM;5cSHhy(4I&lYmY*bvi3|Q zX>0Gl0{*Oh0ZDA_$4Ii){(>ZDZG0vCSzC*wVC^$VVEbJpCSf-su?aiqMwG$fRq&Uv zV<1VwPC)`fQ56cKgzbqWm9RsRq!V`b)$oUwOW`kJZ-A6d*awm1680q|d8nhVkg(?= zK__lNVnX{M5*yl=kR(F;36e0hzabHTfNtWf+4e}H&<;kD3hh`V>Chf>GiT1uK@x}d zA|%<+E<=(F?PEytp?w`mA+$#>gFmrzkr=U8AhBXsAW4XQ7D*`feIz3GWlRnzOW#3? z#D=%PpV$(TwAh=GWW+v-Bo=!o=TGdHkaA)-Bgu;`E{8v{J&|Bqh9WUZyAKkZw8tY! zB<%!v2$Oa`BuUyONWgKr4@m@^({=Edw5uVdllJ;s;V)?)KoTeIi%7CbI|og2NxKeG zK52hNQb^kDZSWV_c1TQQ2O+VM9fKqh*(pfy*E3H>B9UE$1f;0tNTSF-fg}~#H<6?x zd(iFh7ui`z;>ccrBpcbAkmMr!2$FncUqw=g?B__Z(EdbXQuaF>0XAj#<{_7|;RW!Q zvd8hDOW6`6u&8<=iBh)g4ydKc)37t(&^ZH%$=H>cX`8W^LrP@qok+rreGi3# z1QK{!-$IIzKuTq70-HuUWB-dJld(S{i8D6BUXab$YDl?^Z3QWxv3-#gGWH@&Dvr@A z>=P!oJ(1Yh4n>lP?LJ7t*dC8WVmluRh+RvNM6taONh-Fhk)&fg5F11$w!0&VV|yr) zY-~?Ll8f!dNb<401xX>cS7L*}X0R*v0+Y3OL9$u<9Fj!Vet;y*+V7D_)(V<{308w7 z%G%yYQd!%GgE^hGyJMfoWbL6y;;jAmH87dACqc?(?Zrs)S$hkTLe}ns4FbE)@kmV0 z&PQT%b_tS1&fbS4%-PjQBxlzm0d?$WBvH<0;3$=|ZRsy(KS7eo+24@FIh&)uoNbRJ zm$QSBd*)hd zwfPEK*r+$5<(R~=sHp1lH^NDee;N6hr112_;`wMA#3Y5M_bjUCxa=>~?3I5R6{(<5 zz7f*iiL0Q~wev5?A5`r2-z^T0teFE>|K3c85B_#I+_kY`WXWs6uMzB(u)$EVXo>ZG-{h(-r^+m@H+&QzO91c2Jzn#Q;)qpC2LItu@)0AoTQo1sv=_S-cpLr0-XuJRSgN=?4lQrEsMY6HuOh zIM)eonz>i7z)BQq>Pqs5mnL{ZocwV9EppNuwFe8863&*|lNXxVTDMkEa5 zZ|P-Ecqt20C}|t+k2Z~AXSA7XzrzgR3S`^{B-T#DNa3vgJH{28|3Iwapv;a#r-Qck zqOXxO+B(c%FgJBD>#$-|Gc;p^)Y+N=y8bfFq=M8fnkfrX4{4@tkou2i8iUmPnwg6s z?SMhZT%LFceX5#@P;KU_d(oZvWWsnXeh;EN!$HeGrjL-{Xl zk}JK4WqY@l=S#g|@;>IJtTYtiJfLk_l#-Z@2Q^>W_c&aMKg4`hsq_)1ZE>qy9u+!_;~neotUtC0qxaQBb&v$JtAX71Uk-+ZNqd zt4@X1Voqha2)O{Lu{JMO940V6N0TzV2qMIfR zQE9^}d}6QL4l60MHqil%ioG^((fZ^ZYVEDj{)3h#T(OB-e_$TMpwJQSGhZh5q1Mz7 zwrFj5j9R;)eGs0BwQItm7<(H&iLSucZRl|3hr}XkEr%f=;h#TH>uvNR2;W6GCOizo zX2MU=UmH|j!Nrs^&!bWQgV6!*gN1Z+JX~JXiX~XmInFyERGYp@`r-W

    Rhi>yt6I+qhvE1#;TibEmWX3eg32_uuuN++0*yLW zY{H?H8Dsv05S{ZlD#n>=E{Y&J<3dQ|O*QwFFsgnN(gah@hNNlWepXot$7==;j*r-3V!>lTy){lumR~HkwT}_^#0$FPB9gHJLfXNiCy`sCSkr@jz}HJxTBLoKzd_NWF87p26Bhw|oR? zfs@)tPqFSiqbIZuQFC-Cv(QN$qn+vfeA9v5>k{3F<1KT6>A>xzM^OIt>6q`yobLWAO6N+6dy4jjpFez7$2!uS3&&# zItWLp5XJ{$UB^ee>#q3be;^#ALN+K|j+GN1n<#^UJgronhmNJ<>F3d+*^G}9yu}iZ zw|Hh-R)j(M{zwX)v8Tl+CJv$A9T=9fc+N`dosU6?Pi}q@@ zRb9_vm(Q*`3geTC=l?}bUM|K9iX3`(AsL^i7n0a^@8^&%OuUU|RsEsTEWYs6vrx30 zRxZw94v=y~i5KTCK}Dz+N%7@+k(AQQr}zpLvfZW~e{>LES#d2?%DPRPF+GT{s^Df( z9)I=)3|y@>74e=p1mbJ7rWo`&7e+Ju2+A32p4oDSP}t=Yw7WJDA)mhjA63U-Ei}Z} zpK&(Ixl_isSKNwx5RZw`zsD+Ggb>EZWgz^g;wuQLxWqC0prZLXxR8!7e;2~%6@ws@ z#p6~%__ks<2+iV)KZWpH#c>d-qQ|%r5=Jewj8dOL${TIiHtNop+M9|i(XvBy+Eb8v zxVkRUyVUFFq#jXsdLC{n9z@Gt(VmpXy1IVREm(>1zCcQ&ZcxzbG>p-u2sd*TKW@TD zQ2q+Xf`#QbvH#aG$Bt`bcGNXS+(Bl`M^L_^sR_IP|1=58Uu&w3;rRcl&6J@mDDN;A z-dJ7!ZByf(TN?M(CR~hp7M7Rrp#gCe)gB(KHI+?mD$5*+9BvF#jfLgoo0?p>rO9IE z*1&gAelI@qtSO(_)Q)55!sTw`7G?R8rdp1otK|aCEP{UK0_1}7$52x_cMS%6e{(BJ z@*km~V;`KyvhhKt(>&}4N8EtgLrgV?+MRLZLrpb@8-FtV4b)9B)ohr;-brg|PUKYc z9rF3^C@-$Uk?nSsY~x`l2v@^j5MKQu_qO{!=H4~{J1BO=QEU#u6Y@1LCkZ0cDEW0Al@AZWOjG0NyT?i7^6Zq-i*UDJ646VcmnpG>^K#g z#UIhjconMRUDiXGphC;|XB>ptJyd8LzkuUDJ5hxW@i6R2**#V063<5D*-0w&h@Zj! zlbx(WuXqSf&)L0d*vo#pCuH~0Jz-GHYmDr^t$6G<=$??>Pp>cv_pjuTwSM_; z{93KZBct`LI9cpiH4x@I>)qnqsOW1n37^=ASCi~Cbmpss-3^E4s&vq%J;rccIY+wn z2%L6KFa31}vR_~V&METiTbq@zc0tR3PQ%0=z5)}gU$62zEL#AJ-EW3o_}VS_Om$m= zPt0)Y?2CNnFqf%HwYW=5Y-&4~Nu-u8){-!_=1$E>YT%WcNv3wWSTj-T#f6$lrAE3; zI(3oDWKx@N)T%i38OIDGm^uZERx@ASrkPx-k+I>XMe0x2CZFo%+T>HSU8sfBW7lb$ zvQ&~6e>gl+zh9%7iqv4NI{Yi9?!8_!%~C^M@Xbbnd;(vwMuomL$z9^8eOJ!>Jz8lCbj(~ zTGblI+1*>F>`VIq#>MiIVx4?e;kntulInDBd)l!aIRE5P^M1U?(XPw+X{?tyZA zv;B}kr|hjvvi5Q+X6*zfWwr~Ow6#0JRnW`s1T}o!UBbe-spD9P3x%Mn(~U5Y->@fw zi1)`T%5SXXiVC_NKke8c|81o{tq2OQU?%e4B^Ya-ZL6B0zp4C>7gBF;j7I*a)?DJa zy@87S&#hU3Yk-516c%8R^1mbwLq5M4A6;+7YRLapelrX1z(@J@_^6t6HB1(IuR~tX zh=soTebSxe3;p!GjFbFT2&K?J@hF-#qxntvug_&*Y$Nh*CZih{w_$M`_Gn2Bt+!r< zp5ItS>s?looswHqTQmf{&>TZl{<^g;J!;ZsBEAF0QPrD!gCMLK1 zR<_`wy!9g(e(D>jDoZ|yx?O_-IV{LN-E*sOORM)AY_0>P12JG3>iW0cd_U^CCRy}t zlf9t(@YPraegEE4Q2Pm{=22650lpBfk4%tz)U>Cmp!N$4_noE}DmwMU2AaFe6t!Z+ zTC9=Wr6xI{(O^F{n|%g#2W=>0V>)b zeDq9Y+o-~z!T-TaeTE0cOHFmtO$XMs`~&BK+;r22l`hQbX83m$E-Puxo_Z|RE`y25 z=CdaC$)=r)WjSK$YkFPiUG{b5&MeBen(b>w@#4do?Q8aC&ESDkXUqt8FlinDK`?SA zN28@N*1Jq*3fX>u;1T%k}vB8~hpKii=?F zCj3Q#J)1LXdUe~Uu?u*ns?dfzrgG4{30BT38B#DsdMp`e1Zx9u~69C2|Q1jMr+b z61~-C&)Z<~V>6u<4Spv8X0#e~-R4f30TwRsTY|s%HD^P+QSI8GIA+z6!3ldZGMsMAd4UF~N=)weKe5 z+RG%{V0%hf8P6mXf!joipLpbu!LHu3YBcg;9m`Fs68CRiNg#H!X2Pm8J6+dLGERdNp(U| z$hOqe>9gywrJCo$o}Xl;h!Gcq^hGi7Q}n>Gt^ zv}eqU`*12SPeQ9;4nb|1c^l=m=3A84ngj6J&isJd_GTi=JD4Y6v!gM{_cDD@+uKL7 z{6j`ED#6bKaN0BGK5G!q`54!PIT4?sIT)W}>QSCF$DvJRdLW-NH{&yH_Qz+&j6iv8 zy1`D?y!8)OtSKO$H_xEFU`nu1W=7-lL-PP?*O`{k`rd3p$=~L4 z#`*t2HmIsdbTsK(Ek>ye=Bl&d>;?9(R=8l)ys_WIWLGnR#dZ-?x@&o8|AFBiniqQ} z^4n=XY3t#(r{*L3G1~W1-ITos<-IkZvE5MKNAp?xEA02x_IX=Ec|Xk;>{-b7*L<11 z4*7waFAu8UfV0FPlVE2;h8{8K7m!JDp%l<^RGtt048^z!%!X_XRuC zZN4ocT$G_|Hgm$v8Nv1Cbkh0=Xk=yvOWU4|463FDE6R1D!NUP4kr9Ze4gRK5kercw z2yL3pI{0Yt=s7LTP6%dnUg6bF;FoF`m=es4n8Ux~3=H%UuS1FdHLfEDt8xAvz@Y6s zM3CIMoRzhgaFVVuT{Vn*j)G%schmdek7ej~H!JD3yM6Y;B)jdd#%*^sZo8{-+g-Ka z?)HTJJYAL1QyFtLZsV)=8{Z7J*pHP*u+r^*)qeN8jFr5qDVxU+=4#w#SmQRsUT!l) zAveP|w~xT=hPNYYN1qyD*>v3>`PANs)}$U8gW}YS2jkFA&D|!OAa2ZbRX(Mt+6c-;8{K!r#$yA}$cD^uZ`RVWkE`@>N1^ zLVv$b$lVyM4GB3Bdfy~uGaPM9$VjyOHX)r+_+3KwhuiNHG7UC=NXSP}|1lxWVS2Yv z>XGao%3)9#6Uqm$IX09J(T8zJ;C6f{%`x>8LOB90_Xy=34DG~FD&cm|P>#a5ObX>A zjO*l3?qZywoQpBtJCw1ovQH@cV_fzPqBFB9CD$d?+#*!}F0yUwBw6@)OiQ78wEcbs{SG|>tN-PSe`&g zkH)eS^d5_)2E+4sESEyz#)3>ifJ+PVCrsZ|kT=of=7OxnNGvNzjL2>&$Se%c@`8Ma zmJ5nfg}U>K@*>pBI?Jc%QF&*X4-dyz%B=`~dZp}%AZAp`2Z;KFO6iL}%&e5RFlHxK zN^2<0s+2DRnMNm7PnIq7-8O%I~5jcUFN({_QX1<2biOftxT(g*Y0RCn(^A8s4 z9A+lL;7QC}1v@7*^BE#Mg_*lCLZ>owE5bXCnIX_RotfqEbp|uz(Z{)(K`-YHLdm)C zbtW^tF?VM%^D8W$&CJi}$~nxG5d1u59)|b%%=E+PoXboXs9$m*GIyY4F*A=~z%OOy z0u0Y(%#4Nl<;)01|D;2asX(YFGjkx82sYy&{ukQt6dykcgZQ%-c#R4X;xG9H@iLU~ zOc!SmJkCEsyaXebWM(Bg7%_7<1|g+Y=tY{DYcZ+30*OyXCT3+#FbhQcgJC2nK>E}QV)MZ60>4YGKqU2 zx7l0^8>Th2I)8){Tgzk(mRHNst+2LQUfK=|tL4~otg4nHi&#=ECuXspS|%#6m|DKw z49lhE1!#F{%U@yU^p-njusCp$2!%wy#Cb4RMw?+6o@x?{QW%+$drSzz(~X{bF}U*) zLwJT0qjX`{VL>?8Ng%3U!pbwf*sL%y2+wkYsVat!E|Px!8>cmP5WmBoqg!I0vn;Tt(i>&YiSNBZr zyF8>dUeDy-z~F`d^@=8U6Gk`u&}*99C=7Y{kykajC+TIa*R?tRVkP|8>)PDM)LrLw zZLWc}pLku{dnBOF;islz4dYGZ_-mE$GgI*~#2>=ku@pZy6}%$CV%C&BE8Y&d5aikA z3XaDMTMH|A^+j`?+30(GF=C~*`k|?G7aO$ts2aA{oA3z?am7M3`+HQCArW&fcW7F3Le{~w!b;QtfWus}yF#=JBQ>t8J7n73^z1l^2l zNv-#9Dy$63IwGHEf!2&|s%agR?Z_GyXw9^yntV{UH)~j+A6mVjsX7eG=CFnZ`hgn^ zFIUTB5bfi52>EJt)e(rxw!zcM*Q%>H)wusGFIJ~tLX+f`_`tDoO9~hEZ&W9!78?1i zI$eepYf4a(FRE*(W$;%uVNbrSt{F`+G#hZAPQLcFQIIh5akcb?p1l?|pH%ZlZGpW7 zUuiZ}$M4e-O#f7!K8mI{qF8?2V)_@F{>_V_d7k1Q+nWBqS}s!4sQJ;G-iZ94)iGVt zbfT2Lji$SXP?nO58pnu{f2!prDznCvTwGnzH~iX+MzOg`c`3af*~0KWb_%3eYN?Y6 z!GC#j;(gC8rCXMi1LNkb$KdiujvRnAXlExrDYh!&cXlo7NTxWKb!l z58B$Plzxo1LQdQ+|7&a1wzh_p(QCFzQWb}(#>_qHAv6YO7#>4O6_wUqviw%$e)Iiggv5XJcWRp+CX9O=cB*~}3* z%8P09JHAfJ(O%4$pSWU<@nUS&Q#{s-S<{V{kMm;AOs06e7xU&T9G^1Xiv_a?J(Uwm zEj5g0rWeJTZrV(9^C@*t^tCO_kzD4pyjaNN?Ni1AlNyjm;=GV zJEN4IfF|Y}+B&mo@XSvX&-G&D=Jc(wj~M2i zUevX>tR%TI*!mDP%S)APXNO>5R+M7;;NkaRDcu=O%%!yT@V1BFy(Jk%<+Yfy`~Bf} zGN%5~QcR;%ezugJLgk6<)T&ZRw-`NkpDM|@RDJ-H^h~J*E9@swe!djbC|B2OrSwuN z593U|;bs|EI+&@KO0tT|XG7r?KT|tlmAzAnX_U$zmeMh17>(ebO zW;AQp``R)y^8c`&zV@}e^pN*U(i3LvZ1i!B_p}%`Hk4vUz`_2plpaA(!qNSyY2tWf ze_N8HsJsKh{NB&hR~W`$N->R6d2=a!8I?(xk$;>r-nr3TBCOeFm-wS357X8o(ErQZ z>dfeCV)~%1Tupi%vV}c%+9QxcjqW&jxk_y{-_};TMtGTMW5gBLxE-f0=AlJROdmnG zQT|(<-iWc*-}1^w)x{n-(t;$<9(a=ud%kR}E^^Mw^|!q8ZFP}rry|LdKr{XQu55BG zn(HrjWwUG1BFVkHN`I{@>5|&0*5BqzrldAX`rBNIOT`P}r)84ccdsP(;ePrHUFldV zEhE!-&gl-<-`z@msc3KkJR-?WbB_M{R(5wSPEK<3J5_&oD+ju=)05o9 z<|cV$pQFFNm5W`?eEs#UEGiYb87xTh0KGteeJe{{i;MIZw{lad*c&k|O7gI~QGa(U z|8gyE(%;(3-KAm;Vp^8u!SuTR;#MAa{eMG$O)F2h_HQP6#JsJ)mzCA7#XI_YS$V;= zcsI$z;{7Do_lHTYy>K92ajj!|ZYO_*oB z;E97W&Uu~%dNtAl0c%YrC`%%rXF;oPuxg~bCc!0yRoA^Hy(@~%U)`}PwsWh_;3&n3 ztwxSSjSafu_NrfIss6a-R1fl8G(7MOW-Rodd}cDic0)s>NoT6vbPK7y-ewQhDBq1382 zrUTAyXPB;p>A{SqYpuWdGIbQYdC{0P^wiyp*1SniJ-nDOS5w^1i=lal;`Uxlny0AS z%ZrieOUu2zm@-!#4zZ6H(Z1H70s7tzrmFXADN zmGU)w|5fP!P}&+=tLG71BM+lE%!|gHPRGN&Xw6u9 z+SQ8*GmYX1FNWq;>W=bpB+X>jj`m_?Mo`?%iz%}QE^lRbFQ(1e)E(o+jOj{otQTYR zFN)*5m^G~!)p#%FOe05j4=-x}cR>HqIm-|legChAjfv<##)bXgAN|MITC;|x53JP- zAoTyg6c6&EF*6wS!Ctgx1|1*b#f0fV@lY?~kfk`)i%Ih~br17mWZtIb!@Za?-8sWY zcrk4jQ+JvdGv;CH9_hu{?9AGuyqGnMse7~+bB2GQMvnEO_J42mADy$~(Qw~dchR;G z`Qy-kj0>-R=G3OI$IT*BRK!@i|`1n0qPC^I~jvr#Rn>S@Q(N zbG?`||Dm|Ri+S@V#q+#aFrRQ57J9MFjG*81y;yEmF{%r^SYZxe;|sl5H2ZSRUgX7Q z=2Pk}@?r~oBY=2`7c0#s>Mr(Tl^M)AyVQ%-<^Vdn%!?&+7K6Opi#29fI=aG(EzNvd zzS4`W%r(@#+Ka7Ck+s))Q7=hn*2+rEt>s@Hm{se(xDJBS5==jq1*iY!+Vmfs{*!3y z7O#xMpHVLNqA{%))@@$IjmS`LsFjwuH)g*;%~Ef=D{S0Z8`CAv5BJxmhoOo2fN?#z zWz*h^g=hL?qcAOiEseKDKeUm&5`)i7_ z+TvFzD$DSE*>p|OrdF>LjK7#@TdNm()?Y=`))s9W&RB*g!nXcmqTV%XXY}@?G}IO^ z$7O2=G{VNw%jj)KndBPvF}cwgESX$eyatW>p%Io>qsi^b(&?_z&L+n{h$AyHYqm(5s!MGi*oEaVDg)CwTAyz%29wE{}5in^@>Q+qWUT92t^h4q-)-BHek2~6!d zxFM~WS^=ka9&H8YAkF|lwJJJLt$_lC6rN zX-N?%TNNG3R=~1VFHUD1MtP`#Y5N0}&*ZmBKyCF93KVK9pxWx8 z=BTy;tS!Z)e#HaVw%8t~J=a#%JlB>k85g*=+o6eaZ3SRk#>H>BMnJY5N9C^geh9KH zE37Bm(kPWdwmpf;^ZOw#pl#U(k2r^+>jJi|sw8O(aN8xc<>9tk;o-LQL0f>^K15rD z+Y0EmY~um}-u443d%UeGd%P`;QW<#LpQucXt$=U4RT+TW79F7M0k^9B`Yw3CV?a!! zR0iO-7n&&GRzSGjstm;K9#kIKsEAutZrlzp5DbWEl*&Nd9z$i>37)~Y-Kq@8?IJ4Q zHx$35_T%Rvw=_y+KyL4#G9kAD%I#KVU~XTbvd7%2XOFq1Q7Qv-`z4i$xfO73w<-g4 zo9PH;54u%l54xpMt|)+RJD`bzZUv-UE)ASoaD@WY?XFbzs9Rk#?;$>*ZfTUBfx5kj z%0%4?Shu55jNO{7TLJ7=MF+bT&~8<9v|9o0Rz+PD;N9L!Po8(n3i~z=0`P7b0X>0t z`!zlF#!)E%-m)v$2?)Fu5N}m<#9IOKR!2Y|?0|Wj?F4h4dCLkr8*2m1Te_raFmL;# zi85~m&|9{_b9zE=1=L%Lya9lhdj`l}XlU=l!UXn~753#F@D~FI#PmU1z}}vTtYUBR zI~AuKDEC$XzNLz@1@i4OG_-4mL2sb5H4pO#@-2PP7Ra|x(H6j4S&?I%?B z>|0h?&%UKmPAk~A)t#YC_N@SZtFsrFM;al5eoGM#!iG}>{+6QKD8RpMfS&dITUGP? zTe@Ui;NMQ7=^aNv830_mcgH6PxF=EB6L2*yPr#*7DuaOg43!gup$r7BQ#Q4Y5W&Dz z70198KybCzL2v~WTorXHfWiHYo;(Iu)jS555zrGbxY;i7L=3KggUdEpG34M1K)73N zfrPs~8rs8A1QM>=@+4gPpe>MaN75EaxB?WeD(h5$g?luWJquTrJqwpcsSFnGd@2+A zDuCf`RR#_Bb}D~^Z3r}6RrWMo8l^I5xX)3UG+Y4=mu*t&89dxCs9b|n4S2Y!?0L8} zN@ehHd1q32xB?*VR%H-z+oQ(z!Zd)0tIC6i;-#2@F^y6gMBE`%CJ|SF#ATa=dIl5s zAS&NjACQTw%ASc!qf`bH_hc#`h*O3Din~=ARNU*RT!Co;6<3v)?22pIfdv|+GN`x@ zQ~B9OCn}&Tf*lyRT)L!b;Brr-Y2tDPyj*YkVI0K*V6Hb!V6K3eyVW$1xmVG&N9L+& zkIbb@4l$UycOhHF(5vW#{=m##kE}9t1<+jYkI-BJHP`ziHCKSm-RckA+!SWedTy@z z`vi*`+*~@LX>fCS8Kc}>0XWy2COB6>&h@5A&K00@x0(h!_fVSl>|8bN*|~H{(_rUb zi>$J91@K(9!D)3QZGoQaO@|0XfX`J?=NA0jr)b*qbJeux=h7ud2>{)xh(*Wt7N7IjD)dQrfrmw(S0!WuG*%gp2CE0n(iOavxB-TO;`PSnl7F28x?4}y|GY~rYped z&OZ)jzsVji$s;CnVs_xx1?WwvNwWsRRB~62>+Xt)NY>zXJ0ITaw6RRuW>Uz`U z>I%TRDmt*PfUK*cBkKy#x+*%fu7ItpqGRg{;JPY0xUPV%tD;5;yzZU|!Fs$dE3C)s zGI~Y{yzX&~l6YMKUssiNmI2sZOl1$)Rb>y@rBO}{0K3u$%ETNC2)o-(3=q59P7D~k zZeotD-~h z3YfbpI_9nbx~rmt?h2^8Dmv<}0K2QA!|n>WyDB>Ft^mBNVrzcWe_)Vw!H`=|-erYd z&=`=s%h}?Tg1kGPvqGk>0KMy`RMEQv_O6Qh#UJq9nY88MyE?9?c>uqAFO@xhS1Sf$Z3Dkcqf`cdcMX;6c+i8t>y(whD**879-x8zHb^$p zRv+vEAnqSF0;s&JsC+K2wLs<70q|5_8l^I*yx&rpR9*p=*AM1+is169s9P7n zyk)rBwjRu@wmg`ZK4=SI-oa?17+e9FSK9h~=haEp=O@7P-bP!0;D7+0S8aJbFMZG!@Vsvz>*4~R zSKIiw0O(cI8W#w?Khu^c^lCd#=%o+Z0-?7RPQETKAbM5V#|1|3*0=!aZA3%c4T}$u zUbVFvMgZxh5AN20^yaZ>71Ar9^y;P(7*cu#m|hhfrdPn}RWYHQUID0AMF;8?ka|^g zq+S84S4D^F6|j0$bgW(htXD+`>lM&?Rdlpo0j^g?hwByadR271UIDOIMTdnI5PMZD z=SB!*Z*TO*K8>XVWG^dhS4;|!y&MR37|7mp+2L8deg?Bwm2tn1BA~r0I%uze+N+|Y z_6o4QDmrYhfZMBLnvMbPy@QUY;L-`;URKyzEJ=WS84w)<-22uR#~}Bra-bAk`M`@< zO`(9@`zvjEcCXs<>|XkyEwFp}#m995@ZN20f!?d4aeV^5S4F+}0l#-V^z1@hJcHk> zraixxF6kWr-^0+Pim_JF3H<@!+X9!2&L0TA+xi2-cUym8_&R^e@D)IORrIq3im!@} z;w!-Ts^~Dj0*4cZP`(0|uZsG5C}6(CIK=V~)+_yxv0OzZs!}$t$zA8GNuK?()q67L$g%=&sSAg`@ zT8H!%Fnv{YOkV-iS49W)6;ORubW~pf)>lP`^%Zb^Rdifm0oYeX2lf?^eN}X1Ujf=z zMThnkuzgi@Y+nJ~S49W+70`WEbaY<<-d9D3_Z9GcRdjq`0pM3f2l$mfUUYGS(K>2+QLvB6gmlf7iemPq_7lQIjc9Bwk1(;tw2?b_6E=&cS zUlkqaR{;7|(Sd#iq+b;s=~saIrRZMU2J3eOtXj|dWrg*uUk1cI6|CR6bWGN-0QReU zWuUNM0qs|}SV#L6;C@xqQxbT;H`BD|{i>Sh{n8~(gZKL+P5&1ModEdDHc7oo0r7Vo zl^?;b0phPJd*UyRQW?bGLs6^5Ujg!$ZE&GM@yfV4!|#>z zyy)P+0{X9-cJyBX{#QkZ{}u3mRdoDc0RUJ<2LKijfK_w^U;zSHMU4^+;2sFUK927! zU;wkidIm6~XOv(7pT#K20G7+Wa-a}kxx$N%0xVa0(P4n)Dla+?umA+Cj`cbfB;Z@< z*pq zmWRFQpuqBo7abK?fCW}lIuYOkKgcLO7nl{+bAcH>qXZXt5FQaI7gzuWR%JYGLA9*% zq9X&#zrE>=2xf)# zfM7wzj@J7 zdF6L6>O=q<{5hk16_;s%2Ggi*hg)5M1~Ym_325-)C~;AO8mx{3r3MSI!7BPFLofO$ z0S?w$A7#>uK1!g2wbn-ocCd;*O2C6v)F?p@UWgFvdx#SBU{=`n!|>*Cef+tP67=9_ z871k#0(`J4<2}AE5Wx>t(eZ-?0AUq%L4Y8n~ufC#HC4-uvh+5$v)G;I+gET9N$8$BBVBYZ5CJw{k7W?-!VZscEjsX)k*t8TTET9RivPKP@a0k>_j}unq$&L7~Ss&9Vm4OpJipn?Po4&?t zvH`F#eb5%b!i{L6>|X&{m~HSHgPI0fSZ!&iz!pA~wme%{ZLL6DU<=a+Pdk7M&q20| z!Bx>J9RM!86j|p0bYbs+hpYfEOfezU248p;8d}d6RtKMBRe>)|tF#5a@VB(3$^Z+kovp^#J0OPD*2l;LF-#wH2gYzmG^t{6RkTV6U<@xnVS$Wc z0c2P$;+G6u#h?tUXp}N6zznPCIKKkUuzCrh8wfzdTA3{1FMbF}!z$@G0yTUmL-VL% zRoaL{AE;r*!zh3n&ZFE#0oJf8`zTg<(MJK=u-5u0fE!kWE(-95wbDfa;IK*>1&G7F zAz4oxRwYjyW^{}K#Np8>SK_b$IjqV$bYKo2OXZDNN?;DF^1T>cFo$WB%3uyJKvtQ< zxO8>58dMq7;XA49sl&VnVLf%2MyU+y@V}`{>aYMi%wnU;;0}L9<+V7&fji6!>$$@; zN@Z||cS9`79TtFxow9<51>|8B9eG%Q9#+wzhXw3m6$L*m#eE#WhgD1##tp^KxV)sJ z2mJ7H@L{jTcL3mr+01(UFvDXQzz<)=FuIOFAHW}0Q-Sh_1ps0d^_CC_#E;XKClITx zo;ZL&Af^v4RUn98N4ARns-jgo0D^b}vWg%UFo;!An*&0egIBu>RsbQ^ic1@z+7QzW zl>s5{j3x>p7Ep*a990H}codaAhFF!m!w@jUG)iS)h^J7Q7-9j3c&jo%#OG4kgNRkR z2M$hvh-s9{01+>x@+dw91BqDMsAr&vS5euch_#{&$0bn2G)iTlh}Tk?C}IJNc&lf? zh|NeSdl<1Qdl)f|QW-Gf8Z=QDv4BR*HYxQC9PtiR_Bdiy_Bdi1r802Dhg13bF7ON< zv3hnqVmaLRLbqHHi5JqAClaeIPb8)f+5(aIS=u6zSb!u}TY(~p1x#WU9g|o9CFTKQ z^!yJh@p_uB!E}I1tfoDcm@a7=RN{YVnp9!|me`r*8UmNN-6$w~F0m?mE-{T#8C>Gg zXrf$V0hrh+E0|b7CRS0GEYQTq($@BvL!gP(mPZrQ2WvDP|1u>er4q5~8Q2*oPu`2~pL z4zOxHqL>xdBZ?Ui9RpE(G9439EMOF?a-fW20i;+(2Pqa%idA%!VgaUDMTaRCaEet_ z#{d;yN5>vi%nDoI4Syi1A!a~y3{de;bWBjOfK;r?fs%>^sA3fzs#w4(R?)GF1+Zcj z9jsVDD^^h*16SN)H#qaSVpiDa-~qT|21Lie6^}s^#T5&9#i|@AuUG&qR?z{A1;k<% z_2x5>#nWlpBa79vM;6m1O#@l{E=^DEiavo^>`jwdEPxh!(}WfasKw5-sm0nBV2f3B z*kS>t1bN6 znfDJqQe&p_{Az}8~_-f2`6?Vo}vL@%nIuP#*B|~ z0ATzm<2aMsCJ4r=92gRe1qfpm9l}_^Fji5A8W7_TY5EZ80b;DCJ;azUX&MmYoyNd) zE&BwDu{TYMu>fQ2O%r1*;21m8$}tvzj8$|XV*$xnMMp9gpo~@2E`nvuKPP4RbOJ16 zR#?w6W_*kTEaTG|$0D3&1TbS~nnyio#!IQ}X~wGTX~r~4WzdWtr!twv0-Q11V1Mq8 zzt%Y9BkFpXG5=DPJ+={Nl_Bv@)YZT6!BYL3DF5JZqOf@d{e@$;L6L(Q3t+}iqD5Jf@8{zW^|T9uwn@GQ?O?_Nm@yBdj!C}V z>|n+Mm@&&bC;8HHmn7dW?v~_>!VYFEfEh1DeUBtx`0bVCo4dV}dN}XR z0A|d1`X%|Et%Dg0V8(1QFv-_v2POF)?BFC{Xst`~%~S_77Ql?zYDkjrknWJ=>z+F% z&%|eAlCM}gn6Ut6O#2RIEPxp^wxLPBM>!(NR~{YASO7Dowb4nw$>?Cl0+=z&9L!h% zGp406Nxp&TV8#NNFjn07E@0nB(7%9bbjyxGBw1u$dkI+(El zX1q8Kf)zpt z$w#Q`l6?62Ns=4Gr%66={4Dys5eG3~#`AEveV*Zi!)F}KSO7C#2t%t989rTGoyhPx z)60nr9~*g?u>fYgjOG&=K6zQ^V8#NN@o1EKn6Ut6%!oE6GQ3XsJCWgS`5?^bE%Y$M zo8dOh@NRP=%bhZ)`;DTEo`=qL*_yzSs&#sZizn^uGw-cRr_V*$*V5jP7n{O;cZ zF%AvzM}9N>s_J3J0+=y1tHTVxh?d}MIR8|p!i)tlV^+3=Ym~M^8zim648JXTn6Ut6 zJOUe9+c3kg6^&tr-x55`SO7C-1VEti^54UZ1u$cp^)O=r%$SWl%vb<3z5%m1BFylr ze=cZbNIc9~05fJ=4>K0PjBmgcofBqwo$g`A0+=!FUxG0niGw6mn6Ut6%u)|C7Ql=n z#C;it9*yq7&?C7w%P#sZiz zyZx+#84F;>C&XCO7<1_0{)zs0Y%WGke`EGgP{z|vo(2COckdk?N0qhx)~@cV>gsM~ zS;3N8a=-ywl5voYNwyrp32YNgFu|DUAtw_&CWB!}0|N}n#DO8_oD4(GIS)DKWHR@8 z_SvP<``xwfUGKjiYtgP>owN7ZC)BCxZuNe&@>pCxZQX_Iah}G5yW?mx7*B=m z(B8HKx`Q=Q;9rlcZVj{DX&7!#-39uj?a1zU5^X2JcC@qgwcU>HU?j!n+zoAOVX@?#!qRWPyiJVJ9F|NDj z4P0EskRv=HS_MB&DJU`E{vc6k!MHJ{-T;f%-jdGr7xeDD1 z_U+Cvutw$|4_~Uk0=7*q|M@AQF@FHPY(SHwtWo{>a8=6}er?a_9IL_rd z@LJ4Gz`GEhTJ_kZuS}%Ah}KSab^RURd?a#O#H8*Z0ilZ^GNKuLo1HOsaB^c z#y0ZnJd6`L)fCIArdZBtiZ#CWI!Y&GE@pkFDW>%&t!91I6w9fmSk7sRHBwV7KRxq2 z>pM*`tv_SN0@T0mOZMTkw=sFS#lK<1a;hnoQ%$j)YKrAlQ!J;NVmYTN)<{jU{AQU9 zT(mk(v3(fxg2U)@9r_HMrdV(SYI@7P#<^did|_sDS~yKHjbi(M(Ly!Fa!ymMk(y%p z#hK$#&|fvh^1FPG<0@*3<#*F8jt~$<#QEJ7vQ^X+%P&#LRZ&wc{}+X#*GNsV{2rMb z;h>UU`m3f`e(&L1!Xq`s^81=cYKrCeYhyvytMl+rY`C~4jDV4?Y$JKBGyeice zJidknX!jcYQ_17ejT9NnugDw*=s)Hy+%ofj8@?3`E~Cej^E^hL=EZ>1%BBOdRa9cl zpHWToob&q+h2n6EjGZ|i29?7pF?QCQ5p1g{FqS{Nn&+#lHhmuefiaZSAg#4#R3EcG z{MPctt7H1zN*>mY!b{_%cToMD%$+15+ov}Q0#+HDb&R8BgV=Qwz zV|nO|oeUc1m6&;ZBQ#b!hc658;??cXUh`z#0(8A{K9AUOt;~+P$|s|4ZO@BWw8k&CY3;)}=hbmbsAO>+v&w2~AM{lIRI6}pR`O)svq=?pOI!2mzE93I zC+BMW;mE7wWmw6RbveAK=gB=)Hsld6ZLe-)yi~HJZdg)}W9T}=9jI2R@g+Lp=uI#gu+~f<|;~q73L|lRZ$wOFkfL{6{W!n zn<@;cqBK}xGlk(*lm;tot}vo%z14s%n%K+HdLO<+iR~$%U<3 zcv(-tEsDOk$-Duhp_B$IEbeBsW}RwGGT@$J%jsMmE74L|Hln*nwB8}Q5-GK@* zh2(Hz_Pu~Ul#7|1uV7(uA{(BbuV*7(9jCRD2JK%lxO{fI#I~64R!7`Yi^cpF+*6C= z|G-OmzKL5_ky0$h>b#Dn*KzQ3cxH|_fqii#?#ablW8FxLYJW$pdvYIck$1%v+zN{t z;XQF1TN$V!J`vY5M9=H^7q+Z};`8WC?GNo`e^^|T+W*zr7f)dHhsW;b^q&B5gafaB z8E0c@q(k!?Ji4J-8copdZOnmN8g0Tg9Z!1-4K9s#C1^y4M7;)WdF0%m&F-yqC0_mW zZ0zz--Ot%RaesNZF5MTOV%=*)XLv8?`8tCZmfUPm#VBrf;MFfA&2%pB>~T3WoXN?I zDXUYQ70%@L7jMSpH9MTC;lED1IpIw1V;cS@VXyG_x3)C=GhB&R-=E>18EE+44oUcD z22*<$&e=gPCl>_0#^6p@;`QAPefe9KbGHdyeDeZ&{_|FvHMe#(wU^sxH9)WLRD`j% zT3z2`wRU#2hOys^FkL&lsqW={@4~PR(3-FJ)EwXfcK+8$BKZ}g{Zocrt6G$F?WfF` zG?HI38nZ_7XT~CFdkt^j)N1=4t5umv8p*p{j}K(@sWSeWtKh-RB<}65<%fFtdpz-X z#?SbsTK%2S!{KbjC%V6`e&sjL3$KT6-m--upCz|5R{sO(-_T3K8MCWVG5DU*O#q)jF zvR*kC_+!&6XQfY>MK9JX=R$uhuN)V~#eO=im-srZ1B?IQ)po02L)Qa~N3r4C{Cax8 ze|6*W(wD+=_1gYnJ?+=~I#ce-t@meX`?}ZE`-=&#$;Mty_H|8;{|m34nYb|(NBEkD z8|^CYW9apzRNV{0v3aeh#TUf2cs}=v7iFZjcp0OANk(dqb>n#1mAK|#m9)pNi7jM` z)g7(QTXsr@^JrO12VS*7kCx5(2bSmr*C+ixjpOxTR)hJzCzuDb)Ag2m z3WIqtyFh!P!91AVLnG6trH8UEvOc?dFJ+Uka*QH!v)#UH(!D6!P(A9@MbVb2$0*uU zJ5;|dugU3d_0EK$dm@{eb5CUTn=+Omu6XyJ;^9eg#Qy&1n!UKE*&n0zII7y`oGt1y zwo^zJ_4XW^8=c+9u+yry+N#s4w;Alip}IY)Nc(@MTY}y?HJFO{=>|T0W_QE;LO#wt zz1}AnZLi-&h^|%jCr>8-@^{-k$Q?K6$)V*eIQums1tUKUgJX^*$ z=*8*vt40v#?UK|uZ>(!$KeWGMMRIn<`l;PXX7_J&de2*u8heiJiDJ+0o+$R5=b{)4 zZ(F>Q)ZJn%pDJAxJD9hhuE7V@UnVuCcCm)nZw1=us@UE7-?fgm!R~cUQ^!ND#wVW9 z4N_PC3wjZiq%WIZ2!puKB$Sk75ku5S=qqtonabedg_PP41gX?9go+W``Vo5E=g?|H?k zeBn`})9k7=&8`Dk12+fU9r(hdMkm}=`C%J;jBdoBc{R&exPmV{YIMR~jZV00EhpTC zlMkV+!3lSv`<_4Ja12LwC>|obtO|E!Rk$nr*!KK1S%tf@D%_R58Fj*Jb~_AOR)xE= zD%_P-;jXL-cV$($E33j?SrzWes&H3Ug}bsU+?7?~uB-}oWmUKI#`Yn z-wAj5PPofI1}Fb6z7y{9op6_bBU=53_)fUXcfwu16YlcQMO^=i?)B-yb;(--r0V6YlbzaF>5A2J6#|?}WR2C*0*b;VyqL zoPC+`op6`GD|~*P@tts&?}WSjbidZTQQP?}WR2C*0*b;V$0^cll1Z%Xh+Ez7y{9`9~2KR`^c1 z%Xh+Ez7y{9op6`$gu8qv+~qsrF5d}v`R`(BR1Nl>aF_3dyL>0y0ypfx-wAj5PPof=!d<=-?(zqr=Hd1JqgaCz z&h?#em+yqTd?(!HJK-*W45~~$*LT8Qz7y{92Vp!ndBAtVUH(Q`Qrmy(JK-+B0u#RI zQ{M@9`A)dYzYhy+r%(OOv0irmH2M@Bqi|Q02zNz^a98xeW=^;(N`$+jM7S$Tgu9|d zxGPG8yQ0nDkiuQjSr}CccSVVCSCj~MMTu}%ln8f4iEvkx2zN!B;1Z*7S9C1)SqgVW ziEvl+BRo^MEBYQ?p>S7}2zN!dqIC*)MTu}%ln8f4iEvkx2zNz^a91>Ep%d8&J3_N`$+jM7S$Tgu9|dxGPG8yP`z6D@ugBqC~hWN`$+jbFo$_+!ZClT~Q+3 z6(z!5Q6k(GJ%q`na95NFcSVVCS9H{LELs*N!d+1!+!ZClUD0V64GMQfiEvjm4OSHH ziW1?jC=u?865*~W5$=i-;jZX0Sm7?@MTu}%Gz=Fr{@%)qdW5@L$6;0|+;uamHuM(m zdKWjgCKc{#n$dzkFKJTYt|k@kYEt2@rujwukx3KN=^xmn!d*=&+|{JQT}>O{28|@| z&sHIZ(V3Iru1KG_2ST{(j2u4mO@zC6!|f&9MU3LyG$-6e>LuKzSetXgT?A>!nQ#}$ zZ_GL2E-h-xIpHpa=A0AmQfSFJ;Vy+z&IxxZwBnB^DBN`mBCOuQ%R;&9JA_?*pqGVo z7pr)!iF6lxv8GCQT^VCu6X~uy0nj8bAaF=`-3OXbl}LB7Y56VF6=+V2DZSvmH!LH2GD|Nr~M2GD57=EI9oT8@PefpNI{pvDYIupqPpc zDEf2_v4I!q`a`Uf3;Q*w>!G;HAU41zd4GV|z#nw||1CCvT^eEo{rG^?OKc!xVgqc0 zS1H5>)tKPKr<#b!1G=$8@e6;>y0U*YlsbejT1d$1HD{BY{0qh5gSl!@J20{;EjGk zEgl&&CO0sU$6W{yasxwg?C#(^t4(c-M*$qyvhB6glWVHnz)3au-kUdKuj&l!X#wO0 zF2Y`Hqj@jphs>%ADJjOFbb^< zL?vt;BSasSQn`VOL~dXlDvd@ZEU*bu@jvATDmKLP6y*k9Mst&;g*(qmY2gaIL@E-w zfkt?^Tw1tz?vskm@XVCT4OHBMr>j(MpdyhQxDGZCN(&c>=U4nsxq*sAZr~rNl=WM< z7?$HfunC?ZH*hGF zxQZn_(V8d?aN4k5z8)OE&wP(*Rg) zXc_=N8JY&b&xWP}@Qa~o0Q_ob8UVi;ng+lhhNc1F4RJA>27qs98UR^C(*Ot!O#>ij zXc_={L(>2#8kz<`xuIzQR2rHFK((Q10Mr_q20)#mX#g}Bng&2$L(>3gHZ%=@lA&n; zv>BQPKz~Ei02pX!8UTX~b@TmvaIhLvouLN6mxJ97c@UP`kRgRnurjzBI)}vX;sat? z!Iij{8RNIK#F2&~XAwsk`f>qrv|&arBaSi5%GJa!!$58#jx`MBPU1MjNLCToHq6PR z#PNo)93KGJG0e-U#PtjdayD@T!=hYBoM>1kR}d!|mdo|TDTWntJ8_y}rQA>4(6CA# zCC)IcmS>5x3~S_`5ID!MRvsd5V%SHXBF;0clb48_8rI8O#LW#G%R!Uv4DsYnYKci2E64<$mJ+hJidn zJisuNr-=s|M)DHzAj6!zNnC0e%b~ot9Bi1EqlkwZ7UU@Qf0vN|ulzwg*RV;bLm8ZJ*evD5m4+=6@Gf_eVM)q}ml*15 z*lh^pjIkP?LdgLKwTxE|$veC`xnYsOd&#On;P8i>~$Vl@zN zFvMyg-e`!`K)lHitATj4AyxzN7DKEC;;n{Q4aD0FW4VP_!|jH7`4e}y;7-GWMA+Yg zyA6v{LA=+nOzMgE8tdKQW`X9qeX(v8xSS4eKj~Z6XBrdzh4QnJ<3w+YB zRyz6Q@U&qcsb}f4hIN7j@^~6Fte1f-ebKN%h7(^lY?Lq9?yH7!>n9D{J}7g%ZNW3hH^D=wP7ST z5q~nw$(_WX4P%+jq5Q=#FDGCZ3w|>!$lr;77#8ImqBqoap-eX6VEKmSvJ)|DSRscH zL&HkBgSI)tDxqRpkT;{o_~X}JY)Yz6+5qP>FAG0-LLK|fTf z=jhZk9FEp$?eRJ|nd`=P%)#l-kk1$roYWp{i;`+BIi+2HuAP}(Dc%|Fg?=cY_4(~( z&*BhcjUij<;(;ve+!x{DLJQBAZOS1He34-$Hy3p;G0NuVgDy1+a+)^hGQ%)8pILPN zWvKo9XM6kuTCAQo3Gtq59sPb?ysvAoV7QFx+V--Y`z29b@2r!kZZKyS)s2QOs+){l zR5u%0RJRyfRJR&xR9CjgE6`%*q@s9NTTnAG`nR=LFj@}hS?%~}0|U?Ts%LnN^uG4^ zc1AjXGJ3PB_vqi%9=wT?YAw0PM*m>Ae4xERKeT?Ly=*&NsPYb44W6=ixYE0EcWQSz z^+kSu3GF{)h($I9O+9OsGr6h6=L{hR#Ho7TFpw>2`+{L82M}L0)Q&&W9v_7es^`sv zo5!r@cfW;iuG=dZKf`>py=*n=@M6t+k=LIm=i6LjyjfPLbMTf6zGiB zWgYPzs3Y5AP=bmMmuJC~TX1;?RffKNgg@^KY78?nA3lP5!>lYKHX3S&;*Q`{c+K1m zyF!QCF@|7qHgyyj5gYE`5!bGPhL7i(9caeL9>SIe8Hy~R>mi1|>_HrAn2`ar9cGx7 z>+wfTLAzlf-_q4uhM~N~6+OyOqbzj$|qo>8vb5pTjM*W>W4 z?~F4#A>%rN{b+nALK<(zPoc#L9R)h2@wATkJQ`og!Q9YVM!s?eGQ(kz;p9&02=1e= z4)~g4zV^fMtd0WPps)EI@lW*C#U;L3kFUo#0-GD+V;zpb0>gl=H|_|U2Ep}cxSMOP zk4KnWbrjenUGLBlFGm&Gk$v2;$Mx9^b8(OBQ#qPD8TwMe$~zlE44Dn@>d;5Z4~Dgy zVaPZZb_5qQj`4_NJBy=veR35xh;~5*pph)^RtE z59lb+DUA>7i02Q+!k;$}H;TVnTzGzA)XNPeH)|fQ)58t1oY;vY3^Tb|Q?Z*IX_%Ea zXnV9_D2v&rV+?iuEbRymM4OpY(fLEHPcOpg*p33j<#W_29c8DYikwSdr**XQISL;- z;#ug#j`$`Tv*e@>_bjvzCim|h6?97De|D6;N#iFtAm=(`e1WgK{P_+grmuf=#NH72 zItRYa>d+*_nZ4ob!j1~I!SVTbN7YbNkvq8-uj=SO6{qodufDD|M2Q5Kb(GDduRqY; z%R5S}m%$$-dN*{`unqdUy`yR;`nsRK?sUdEov52T%8sXT79(=28LviA_jJ_IDLZvZ zN4ye;c}C;q)epO{q9eEiXX-gx_3U*$9ns*?j_r-4v?Y{V}q1|!5Gqn5S_lA1?eb7-h08M7L!OVQrp?9^+o;d!oqlVEk zs^2@R)?-u)7}cN7IH%M4b4S^BG+qRQU(NUlOn$brhE6%q?{&ln;xNyCd3p82!FT{S z0-UMm4Ayfd>gkBBm378f;!qZ1LkKE5lN>!*fpKT>6iPBIDRjD<$4xk{>@3h1jq5w( zfx}?TKcNa5oiSE(U&I$Q8D?bkCy2h;Fe}2!CBsnmC$<^t^<2{#P=g@zFuK;q8omZI z*T1vCfY{BUo$(#0lADUh?qQvJ)uP?)cpGn~%=_=L1mFN6Tk zl8}lr(05odq^Z-#c~2=h62L?BXu2i!mJe!493l{j{FM z$ab_Y?uL=yy|X~Kobr7-<1y{9UY}R;ex3T5gUD`1t>6HgMdZBV;2vb?<1<9yA%oYNU>1-t4=b4Pf=dFK0TT+Eks7T6|zU)>pBk2<;TskrrCn*=8Fx$Lhq z6dA#JyWXMi%YAJ51}n|VVd!gcqeJ9yMax%oV!zgw*YbiZt>uF|@w?N`0z+cUcXq~Q zI3sz^`rT&j$qQ`xUTZ3wn>!yj{re1cGrYAE7ohqciO(3#_g9a5-u;~gHcH=*bjCC2 zyMn$SbJp%@*qV;f6@9Gz3(K}*u&uLB}0+jSo(@# zmc4$uGkBc7H|E9utogoS1N_{pv%p5_`<>2s#0dEQoMZN0kMD(C-0%1JK88(wVCc)A zocIq7GjbkFKQe@#7d!c}p$`9>oxyxGQoSJq`L6}C6dU-bodrh7K)&gWZ)YIaaxTB? zxg^JOfqri&@;5g1gP||i5q~ty$Zy2ehFQ6iVg6*Ofqc;!yvac3%|{?#b-Fh(bH9Le zVP}C6G7uRNcdvy&u3#XU5j}5WI6zrLk>woiz|fbS*;HtlkuzBu8D`~jj%LnK1Npr( zSd2z8r=jAXHXu`QoF7qOfQ+MhMEo)1_&0~M){LQlMb~`{MHUh341KwUmFo>NayPNT zFe~*O%tpgN9%N}>!%%7&Ws{+9S>+>w!bn89A9`0g!reR{L4(aB3XGmn4jSR4wCXtY zL(JHd7UEDtk%7cD4Sg9#9A=o2k;LJKSy`LdZWzb}VuxWU(}q#Tx z!7!9p+4K}=jZc2giPT(Z=(7BE9PLM5d}8tg`ig&o{bJo^K>`dA=iz^L#It z&+~0pAg=hWo+&{3P`J-#l_8+1dSx6;0O-V&Sh zyaTnkzs)$QQ`1S6^1N5H<+{gTD2kwYvqWGY4!Tkw0Z$;;ac4m#^Lc9=D%y0oW}FF=UH>WldSn0 z9QfHWFRJG{JMc>qWNc?QQv{5-|BfUv~cYG z=7Id3_{%MvKELFR&4zbC9UTkn5m>)c*o=p*Xz;aajl4OFU@ODh28_iO#b~^EI6L-c z(-54=#)rHFc&q7-(YW|D=R^2jJs+Wq@#*;5B>Y&R+$$f6+BI}iHAOM@3)&FG0 zcXTp8#2UinG%&nhGl!y}d3%@+4F6bb9RARXxqre~suuvfs?n@fE7kjevQ>xO144qH zGeEhji%1<(eFdmkwfC!_@s291UO^+_6scZ?vf8TITrwNGvIfl*6mBWiAE2yRQw4=P zxUx2{FMn@01qEdr@nt?(N z;0|7rDvVsKAbVYMjuAUEj+s|}O;YfBPr=(b^2)iCi#%EWFkV{ca`+cX<}!x(DbB3j zj4>#NJ4xl3wK0#o`XR8F?CE&*vya0F+shGLTk|qE z(TH`Luf_RXv{~hNEKdGPHQJ(q!|uh*tP(9~P)A6O#XfAA`Gh95*pwyOri&(Ab{Ufl4PPqv!p+ zimp<~#anRTZmS-Kl4ATU;Xl0X zGY-`O<8uzw_F4>gJWx59Afn3ic${4c5TcK8NEd@UoEScO$g-rZ7uB6;3 zg={>DHlq~+uW}968#+=Se?eb+}bOlXlCU*e#7x=eHHl(EX1w4@j}(%1SW+E?nD%}uD_nyu9}o13W6N7rnwTcIwlrp=TJj(0=+1aBl$E7(qR z{0^?<+%$!@cpcnsa?=$C#^2FqBkjSEcpLU@hQiSJVLF(pux9)Q9n4Y~7I)FXY=z;v z5_22ZbYtAwW1l6PD0Fl(J5+A2LT4P~s>#h$7!luvNy*JuSS$VzYd^QC!pQg|&d6p8 zqx9m+EzpZ=v}X0mZP}mK%s9Q$a@**|wXRprN94*6>2qNwS`YnQ3727R`|~;YcX1{c zl{nw1)rXzhF>@43h98Zmz}%A7b2waY;Zf6VnEAyopfGzit~@Ur;uUw!m+?=2*UT*_ zSm!_3!}6DCTD3pd{Ws3!uWTqijoHpm56UX>_PM})A272Iz$-rpRf;@c8jd$q`JqAC zn4U^QgK1i+^absI&X#S{Q}lCIi~4+kWCHnLvpU#b>0;J9FkaP1-8uhirkUF_YW{;k9g!)c*p7?*2v^e^avMf*x6D^4 zScA`2duCd>0Q+e7_R6%fPu`GYU%=0uGqn?}($>8zZDW;6w=?W)rmPdyTqD_xhV7M3 z;Bc<;%XaK3TIEk+qy=6zC|SY{sL#cipZtS)h=rQl0R8+4-0TVmVI$7>_a|`UDlDmi-2i_ASCAX0HGDTt{ieX>$3ll2_c;7m zy6Di={8Y5&;6C>p3y=7uav4109o0qH+@Ds%V|xsrmhl=1QxxT&maVzzIWNyTFJ8Y+ zTn;PM?3Es~l`=)mGzH~_GKJe|fw%7bMKXokYJsV<@)ye#Zm-VarHR9&-8hN!-Pqk0YFqHMk)hB^4Y5uitxEqKnnv+#Y|6dk@IY zNy|6F;Z&`8QBTdOu4aMH-}!0MmCnU<>C!N`73DXSF5ZZ=<=IKgv(fSZ_4jR$zX38v zd%{Qf{6HC#`ddTBr2YoUm>z$_&EI-u*fsM{7TB%sNqG0GL-VBi>#vLW$?dp?2kC|L zw9fJ%UC*!Sa<&=ACkbxG*SBmae0*I9f0hm9OODzA&4zMfa(2~tp6$*Qc z&$XiYPHHEczb(dcmvH`eFn^lwWX+_;)GpTW257#MnaSC%b+i?YziXO$9?A?Q1!O2; z{oPTq4>Ob$kfDS><@GjThLR#Ol$0(%7JKY}rRikUDcs^kp$3CE%6erY9LLl;a} zQhdOE_d9`^Op3^4!eUp1OeSjSJ#q#K%Vg5* zGMO~HOeWQ3c|1dOG;9o~72J?3r{bmAB{8YCBqo1h;pQw{#6p+9r24})SdMNynT7kY za5-Oi)a>$?G`svIV_p6doO}pneO&&MOK|AVI1qysX#SEw^Oppgza-H7C4uHI2{eC6 zp!rLJ>~?te3p9U8p!rJz&0i8|{*plRmjs%>B+&dNf#xp>G=E8;`AY)LUlM5kl0fs9 z1e(7j(EKHV<}V2}e@USEO9IVb5@`OCK=YRbn!hB_{3U_rF9|e%Nuc>l0?l6%X#SEw z^Oppgza;3M;dzS#&0i8|{*qw9hR9zMX#SEw^Opp(w}wb{p!rKem%k)*`AfpLXX4Gh zgf4$c=<=6@E`Ler@|T1ze@W=_mxL~VN$B#Igf4$c=<=6@E`Ler@|T1sZ;z~c61w~) zq03(qUXGJLO6c;Jgs&pfpCokoOG1~wBy{;pLYKcJboom{m%k)*`Ab5Vza(_|OG1~w zBy{;pLYKcJboom{m%k)*`Ab5Vza(_|OG1~wB(0mxL~VN$B#Igf4$c=<=6@`y$+DqtN9q3B$R}UlO|fC85h-626CK zUy4GPza(_|OG1~wBy{;pLYKcJboom{m%k+ZJAznQ5xV>(q03(qy8I=f%U==}Hi2eE zMR>rr_(G~8boom{m%k)*`Afogu^_7khsU7Pd)0?7e@W=_mxL~VNjM69*snf(9%HtD zeaP>|52z1a{*ut;F9}`#lF;QZ30?k@(B&@)UH+2L z;v|1boa8Twll&#|ZCiQX-?v4bB!5Xf2h(~6&jeV9%wG~G`Agy?e@T1|>hMiPoa8Tw zll&!dlD{NQ@|VO({*pM!UlJ$zOX4JdNu1;_iIe;#agx6zPV$$;4`Jw-za&obm&8f_ zk~qm<67Pg%Tg^I2{*t(3KHhKg%xM@6<}Znp{3UUcza&obm&8f_k~qm<5-0gf;v|1b z{Md94|7E;5$zKvD`Agy@h!AhM@KI2bzvN1ApWgXPUcrs6r1?uqn!lu^`AbTgzoex3 zOG=u*q@?*vN}9iiD z%a-So>?JI_ub5;nQ9CI<+YkMHU8>bkib?howUlC#y+lo=m}DB%ZSc+uUOtn`(56)eFj~(Np3stsNeMm=T8kw-p)VtT7=%?+(#ETHK^sews%T?t*5V0ua!gW!4{Hx# z2~Yg5UaD|s@t#cFpaDvPRq%uk$wx^E#_eUET#o9$B_|`V;`8KW6{biBBJe5%#~R2ap3ssBNl6J`3A2PJv}DVqq#TL(S;7D@%9+LM6L2#UJ6Q zd~^J2VYjAc#);i?^v8I{-Q7^6>}TK-Lth5I4*ZK@M*I(edl+WjZ$6{T?$U6^=yP3}b0i{6iUaClZ$#LbIHBxS=oq zBpzj$kqe2(8sckz;tIn+t|k7>FqB(}rx-?ZH}UU=IeC!y55rhiv4>|H=H)TsxrPOK zj(CA#QC=fnWLPHe5-&9@mrse88&=4-#48OeV89fo~m982#utdj}E`wZ*lT~>a;utBD?^dZAW*_imKVPDyT_=I7TY)5?BuvvB? zK4;h>rx0H>EXi5KR}8t+2KzS!4dqw?OEAU<+G^PN3(tGKslZjj)$ndpoT_nehyx7!$PD5j!#bHq9BNoETM>sFHpn7kr(vV)P8@02SN0{2 zF>I1Uh~o^KhAr|4aec#*JVTslsH@?vreF}J+TRJQ;cZ(D@BZ$2lbZ`%C0q?N zn&YZ!4E0P7<*eqW_{kZ4Hrh=2hT!hBa~~OSdq4>S~co_LTU{xFNU)G#A| z5)U@a%8$fD3OG95`+^hGt9}k#N~#ujQ0jrQAw9*|19PA)aDbE&m~&YFHyr5Kl9# zmFJ0nH|!&?5l=U)lXr+`7}iVco4_*-b&~dK4qn9!_}k%<-KV)hC+W_&pj_Ep;N)?V zE@+Oo>Vrvo;Agg{k{QSYM7M<;$?<`%qRZKFq9d@ z%MBx$|10nc!<@_{UTKJT&}`^x!@O)pyw@ovLfnN7UMu#ap?yw|W!wkF7>wW5ZkJuDW{@(MxZ!U0ZIfcJA#}71M3Y++p^}88+NJt6%!%$=?@lQiv z_9A*M?)fDnR}jT8D=Ue_!B zegd5C&`nbRmf(cGn5365n*&=KxLW<=u%b3Bj}f;r3}kJFwT)pY{fG+xQ}7A z>`&a+utp9g?q^slM-ulp>?13P2N>4Lsl)>f>v`$SYSBz4{sVY+m}9f@I4+~5Ed|aN zXXWsg`1BTBI%QmUN1CxGKm7(g%1~r5OOG-1r9?c|Fe7^rk2lQ9&cqdlfm}sA(J+*O z+=c#T7|GMvZiABzb8;*3RKr**S^4jVdC3vaFf7PzT$N`U7G><~z_Sg@q84TxPQ}9R0q$rJxx_Fe}%##M4Xo%xDsSD0RIVcYv`Ml|TWTge^;FNu4Sd`<~(C3C_ay@(ah1r(NDn|9C!vLehcW+-?FmgM7_f!*>q-M!Ax=^Y5*+N!H-V{%qJHx3b+|ta6DH{7OqO69ePFjSyb5 zvHR+6&-=Bdz%k|6`K5R>e2^{~b~q?CFUM&-lH`byVJv0D*f1~E#DZZ#>WO8BMQJ8h z7?#O%+;yr9%jFefwPA%k&)aH^VWqtKJFt&ol`QxJSZ`P@hjK+X8rGCgn~P6hn;rTM zvXC=cveIVRhx6TP*dm7$+YC!GoUZyA>T}~CEx}TZgufIOy;1`Q!oLs$-oI4fAabyV zmf{QhV|@1f5yr#J*pvN;!wvD=NNhLsWf`%_4o zFp`(Kk&Y^bTLpi$?uN;7lrF$}dR=Kem6Y*QeO$-G%5+67j`at~NaGqgCj(Y`hY-*U3 zbN&QwZixE|M`wXUzf#JGTN+lEZ;W3zZDmv|eYnoHHq$z}ohx`-D{YX0e0pDGrG4dI zmM*r^W?7S^yIQGUb{my~2hcbFILzKm>;3__&UY^rI4tb`zNL7_ff(xjxs&W~#-0c# z=>S8KLs)vCp)ZFM4>HWi@2tGkFe}Hh^kBn4`f?>5;?NJJm3XK_ES+b#lPt5!MH%xp zaJgYQw~jqZ!LbO?zX^7GSs!-&1>aDY3hW#Ea6GOC_F*fI#|h534d0MugQGG3G-k=M zX59Ii=bcz8&?$}oUW(tM@u}Pn&q$3Mf|E;utN~+|oLXw&H$8qGwuOI`3Ow&s(RCG$ z?E4=$JFgTE!wLD27t;l)vutp7DVR-XEIG#_`R;wsTUjd51ta-aDc*&~-Q1Y2=xuy) zDL8?~EVsr}PHEiG8n34DcQo$X+qkwh=sN@kEU7c&H?YMtwHD}< z#{FC4(Wv5D9@yKs)QY66F#ZQ_5^ZMuBG&R6tpz%z@$lAoZyKM%`$$J`;~}j`=?P<& ztZBw?{)#XATMKkbjDBD)}rm!V{WwfrPTep+jRPH8-+HQp3e&!9i?k&O6w&t))@$u~ln<5wN92t?}n< zsR3ON7WcHY9iLftc8GKqzhk2dc5T(0bhaq(V}^p=dKx~COZP8UxfV(PfqNJ>$XOhK zJkr%nFSW2nqQQGx3k;WGJ=_}qmtn2JcMFf2G2V861bp0Kn3XNLT%NSjN|BF&Pg`j% z2Vhle;15SjPvFt`L2GF}96#GyU<7RGmDYGXs>spYtzL7+*vsz!5cq~+PVOSU<*-;u z*DtgN+tBs1==@9O`g@G?+pPsQN!OpW#(&WD&HT*nvmV!X6TdJN`490cLtmaGeq)%C z7m42)X5~%d4~BuP*FNnVy=Hv(B?}jn^@P2F1uN{531b5{Rtq-qa zV}hIw`^G-x+TyoSMfTzf$hRe1{n4D4f}u!%mKF_txs6z6n33Ix6^1$aD{U(cV`*k- zm0@0PAXXa|~x^-#l%{EaxwFe}f{w%st0 z;n-w?5e|K1v1cqJ4f8SvizXOjmCIyZ;#k9SnZ@B4Z&)ewi0c|w$x;sG`i9l=9&a}j z3~S_5Vz*(foI=~lhJEBXOnNZQut7fK<~rT5Q5rr4Zs^eOD<$GahI$c~+JbE`Z2m%Y zz0F4UEL>VM+X@_Uj_ka)_!y4tw?D&pQ)i416H2)3gUt=~TAI^_3@z|=F#5iU`I?Ej zT!3|m^Ypa?*5L^F+Ts-$@92zinJy&mWGJ#DaTh~hb|da)h|l4OOANDe0C5k)K#t%g zzL#Mr#}oH4jN~NVUG_7~$?+W810DM1GWc`gK~`ER$8!D;Hms7r5f3%2mcJ918P-TU zZI>I?%7rXF!my8=&S#gS4C~|^;xUHxvNwnFI77VGd>MFxL;Ttu>wg=p|Ftl(Ma;~$ zHnMBtZgOHroM(KaY#} zYwMtl%j8S#ncl88?mmq)z0UlsA@d0oWY-c1qjGPgy% z1KgEUJ(71@Yli3XHh>141~Tg}lJ zypJO;(a*icL%Fg}YRhowv#LCH9!B_or#zNX<+1x<=TBPvlu-Qr@FQdw1!(iw4QXcb7d5jG} zh9npa*Q4QjZALS+Uo(7oxB|x$*EAG)jV%o`^yN9WG~6&FXA|2EvvLcu(=e2KXgk6% zl2P=$mSIlL+8H>~FqRy9ILZ)z=fKj@h6TBfp2rv#WiBgs8J5XOY-pTeg_lv~v0><( zZ^~n^_Iy(wR`1OHfhDAAz zwo44lWF#x^VW|Cw^4KtR&Nt;T_RTltF^&uGKu{iw#-YnK9K3`3H7|Gle~$>|F~wAQ zOfgj+Q%se|6jS9f#Z-ArF;yN@OqItJQ{^$mRC!D>RUT7JmB$oQRUT7JmB$oQ@vA6Xh{A#^ukIby?5!w{SIFZV1^{RUSK< zu0KS{h5g(Us40)JN!}lzJjRS9|3AuO*rlO7_AGt%QXcaUhTl8-71#!^QYepoMqk5u z0X*a`@fh#_Re7v@Z5W&K7|K2WW<>u;zXF}Ik5C@#LX{rnvE?`&<2MudfcHh~6Q0-F zs64iSu1?2w^mM-l{#m*I1g_Rs`W1NIt71dD;(xs{MRX12v6VQ{qdeBjHI&ClQrV+C zrr6-EwOrolw+dFi>5e_eW78db8OQFg+IdzR+SaRJ?JBnXQF?Ot@@yde)?EirH@ppd z?miFQu}yHQvcUVLCq=!*_vnu4Pa>#0raOWA4Fq+^c83YBTiyuUM1T80-7!|`FZyE# z>W-a&@fe6o*f>Ur{>Xv4W2`h%iiz&nDX26Wm9V@fNHNhJW2J5>Cc0xQ(A;DxaNk)e z1+KqKq?qWA&47o?rNE_gpA`S6?pX1bshIz}U8}34nCOmeiwBtprNAYEhr&TksPve1 z(l4$>e7s-H6jaLk1uli<_z4HkLU(K!&aU(eoJB9={^EZo!qbso$E)P{R`7)WvHwm< zN$6E>#uA>;7cD+IDX#M>_h$)DG$!I>oI9;{RZ=bTD$iv#p1@*)EZK$YVbZ4K5tOoI z%MlW8McY*XAxoy1%91IjvSf;>ESX{|OQx90k}0OLWQwUQnPMtSrkKi-DWESX{|OQx90k}0OLWQwUQnPMtSrkKi- zDW_JSmZ?a@8@J*KN7Ayv?2FQ{z3r3GDnHuBk zkS44K$dW0hvSf;>ESX{|OQx90k}0OLWQwUQnPMtSrkKi-DWESX{|OQx90k}0OLWQwUQnPMtSrkKi-DWESX{|OQx90k}0OLWQwUQnPMtSrkKi-DWESX{|OQx90k}0OL zWQwUQnPMtSrkKi-DWESX{| zOQx90k}0OLWQw{PAWQZorrI}IG8XtIOU6~g)c{$tSEpb#B(h{`?Dfc!DWESX{|OQx90k}0OLWQwUQnPMtSrkKi- zDWESX{|OQx90k}0OLWQwUQ znWC-+$ddhrsrLJ|;S)J`q5CFF##O?%N{}U+i>KrsS+Yeqji<;&mP|2~B~wgg$rMvr zG9rI!sezyWGwJEz(=BxC1XH*O9)xA6{u3jwOGdxysXNS-H5}854K*!2byfe z8(A*m23Cydw9;!#WXb3NeRyk3{0WZA=TKejoiXl1xpEnVbHTfY`T@slV}jx|gmMku zZ@e+4LBqNq$M20P+=t4%IzAs0ubz$}(5LDz$0U2DK2?8ZXiwE&8`@L#H-`39{jH%r zRext_Pu1TW+EeuphW1qbqoF-juQs%&>YohlsrnZ~d#e7;(4MOQFtn#?ugmqwo~nIA zd#cVF+EaCCXiwESLwl;u8`@KK(a@f%%MIWQNai{;&uATKw@u(EtZ;#k9m@~OnN4fQ*v!Ck@i z4C|bso;S41h4ldz={j8nhRe@Ny1U}Xaag`7ji+?!2i(ZEjSolG?+U)8@do4Yj=D>e zmHVIJ1NdoO1v;hioUS;x5&CpHd{l5y?P6|bc0-SK5Zu$PNVG_Kvcf(K|k6kkRxvADKC0Q+o^@AJ;pOBf0`; z1$zFwi2NusejA(Aimn2k()iS_cqbZfxF(GM-rM+ZUBU4*X35EB{0w%rv$_g&O5+Q< z;)`i~EsZbiZG28w@DPp1PQdTT%yf){foznQKuJ~;l2iPxzYkC`B-W6nK!uW>C z_**kGUW^rfT~~olX?$B(+=43d!!Q`%(cAc@u3!R$@&=qe< zWvYFdlVE;Lx={!DEQV! zK)+M^q$~IY=3qY*am%tW8?4X>u}CvZfx?^*GhIdZ>VwkV}ttH@bwyQzuB>FqtJAl zV+(A9zN*J+4k5XW#NuFvb`#`{oU^#ux|$2oMa0 z5JE5zAPzD6PT1oR0=z&7VM{{HmJmXC5Ozc0_kFjjdwOK&y?4(4uX8k0x9V)u;S z*UU6$gG6y(AHWeBM535ZaHIxxq8OTWZYArpcd@KtS)C}}oQi9|S)U@QS7$c)8?xRN zA?$QT^%|XZ-Xrm2(51uZ^*eNMT-GO368B`2^$M$!_5*R-rp4Jc_=HhDTFJxt%6t%>0=tB_Eg{wS{* zS?43+ zNxUqZ{DQ>)h9#WCqQpzHPD4M4|A91gup#Dmk{^-v$&|z^vdKw6Q6G1Lc$FshMDnp& zXFn1TMLZvGi1|?Xq^wV-BtAWxTt(tM=Yun%#HVJR%SqgYVfeNo?uPx&$@*kU;_qjZ zw~@FK{GIihI4+XEmvw$m;%m_73k~r*ND`N3eKIBSRoRk%l9<2j;9Q*@4%6bimcDyM zHd#Ig#FZG9D>c{HRY-={WXs5u#6QiJj0TE&ybr`bixU4NoBS4uSA*>hhS-J{KhKtt zDfwTXbq+?cn&PX;h8*wACQn0A@rNOtyQ6)%HS26dOKdGPyxsKW6*$$sS)Xi3{Ajl1 zeiC=HFONsnc`%#g_YuaP#(+O;)VU0Svn5+brX+qkTkTg18Pk z{l*Y~2rZt?mXRs@@<7(<1WGlbZ&497oU z=>ME8BO4OGl`T1&#GM?}zeb6-W|Nypyax#0FvLyh%RAXJGNn4d&pHpGSWWTOWJ8W0 zWRowUsIH-R|4S3(}6cv7AqlWbNllE+p&CFsW0LGajfu zX9SmNP~oJ6*`Pe9e^6FfCvwT#$oeN>m((i6PDP%r$dyqfS=Z)D-XZH{<3U^>vc4Bl z>@-t2V5=;1`X#GK!>$ot)DIlxnJ8O(B%mmP-zxQk{a~ zaN0E?GT9b7^XSk@>uIH(qgHCkIj2%yD+aqYr{|d0F@JXCdUBw1gXOWpt!H3lx` zTotlTQPPh?)^~E_ceMdy>H&uOMgzvx-QxgWV?g{s*d&108qiUHL5WWcyu$PDzb0d2L8t&bScQRfqU)PSzq zK=3gGCe+mgA2*<?UUrnYhpD(|1LEs_2tH}R zQniHOZwy$bW|8yL2CPuWz`V|X8L(RMcUhcg4OpYjB=|c6)~X8$K5xJ}bp^o}4A`K4 zLhwZc4pSa?4lf%}?j_!pbAAMq$3DdLeUI_!bNld7mz>Yh;*h?XOK#z)ET-eV9So_O z!%+X50cGR=mz?uA@*?8vW`x%u6a78sQwDi`kV~pX;B^DCf%7j-9256=FXyzPB^F1^ z`-V6R-~Kq~lPQV6%q71?;vNS5zXM|R75n&2PH((KkTx_-=jbXsL|^CmB$wv5f1S0dXmu-qveCPc5MzPcdLpt>9Xr z&wwe_2jR{%1Nv$<)BSVS5|91rXEDTBO@?@n$eua`-@LKEX$={L**D-AEq1IjtN z+j*9}9z)BqhSwS->($*pWsujY-O0~UEZuz%d@lamfnKHG+GjR4A!d*jd7aqp3_Sq6 zzJS}GYUB=Hb2xczz;t)6;dLFB8sG2sDTBN& z?@nHfqSot*V!f`4>UBxCb0>L?#`teAyq=tBSyy-al)-HM)9&OMOQ2WdWEkjY-3{wd z4M*m$*E&BpU`%D%y4iqn)kpAV1KR3kbk(`VfcWiJw%%$$SIs4On*kGQe}cCg&{N9@ z-eEwb6*}Kt2K3b-1n)LrTCFB{uK~-|w+Y^7zzRMKxUSo|ehE7K2uA<B zfo`9MV22;?PHqE=T0_BG3^C682tHxJn7WAIlLoXEe{jcn%7C7Fgy7Q#l+S)V-0ciI z5W<$B=ytwA-gb6#Qa$$#kG-!7q0=Q8`$8EhW8TKzI{A1KFKClDrPUsK20v z#Q2kef9x)!4Dx!TyX4xC*IUKB-VS)_KK<2zviNzeJGq6d&&L$9)v$gZk^D|~8AVe1 zbKTA>C{|O~Y6_ve54w}*Ee&-4m+83C{UZY^E$?Fk#`I`?YCtnupBb=1ox{QV+<=wp z`vku*U`EyN3UHeNtJDaBUm9?T>LB=)0jt$Sg8w$4eCfq|-Ogs{8ymo){CzVVcVRfb z>Gs(zU%MBP;odhclXsdDXG^fgd zhy%7(8_-q#1ZxeLPzwpx8_-kTjG+bt;`vN3z(xb6)L#iU8PHen6KpYHT762e)qo}H zYl3YCELAR@wcUVas+8bp1D305f*l5|P>lpT4OpojF%TuZ}Zdm8vE<(SWsT z6v3PU>(v;7JqDC-%!v0mQ(^MhQ|x+A?K%uZ>4y(FOAIJe()=E$`Vg?*j5&Q_k6vgzg7Seq zK1GuCVLiz%pr}7`-FAc~c4d`vaF4SuiSL8eml@)E%;ZP)_+(1r6+OupNt~kORYtO< z_CpqTRvS>M4oGxPFd)7xlf$;gfN`~&PJE&PZMB@Pc9H=dHNbVo$p*w1>C$^nF`#tu z*dFH#YI!HDcf8T^d6@jv9-rD%%QJhDr!9k)lekFvjv=;GCxiNI11hzE@o|m;@x4A2 z{9Oaa)%Pg)Tm#zbdV1n{26R-Mtj;%}tF{sRo&iP6wLQ*8s1W-Fv|MMjtbtiB=<%sN zwY;<^`3bd5aj|rnA-2@Tw8!NJRBCr>`2zzYpW0K)=X;W^heOLsy2}fO*izRsjQ?OjrSR28 z*qj+KrpC}+UNT@@E#^49Y(R0B-}X3rf@|zm^!+&__)QGJt35syqTttik{3~MBej0h z5L@bp1m7|szC4?f-Zo%NrRgqzHK4f5pL?9!Dd`PJ`iqe?gp+-bPYo#Pzk8Asj)0^L z`}AQbX);&K{|Y7XhisjXLP0tHIgyJ zmU^=tV3h&!nM$4-RvSY5zZrfeaaxOj^5`@?YW@vVYiX<5Wy#~ZXFQ%6%21EwsnD1u5xVnkRdl*o(9^dOM0@v6U z^kevp&t9JjQSj{EZ%{m=?^lXsJWomQAb14H?Z7*k@P0q`;cCr8c@>F zy~&|KQ3DK-V-0Ij^YC703W@K-5FQz*iSqHiKADpEq~4OlN&GMsIki^~`jw;F$m=u% z%2Vdmy~*>*>nYH$F+z?)qFLKpMj7OFc5lg@Wtpxi{$kz z5YIBaHiPf?ddnz-)6U9X=N~9mQ@Lt#rGU$NORA0u1pFWrFr^RjeyG8?L+bT#86d`9 zL9Z?~0^Wjcf7Dw>uH2-!FAcHLVv7Nd z7QZr}(c;${jA<>NG>uw|-xx@=cnI-NEiOO;eZ*)n4hDLv*Qa*W;`fMu6xHu`LHGV( zh{bfjMf{WaJ-E_yhWK_6zl8WV#IM1SBwo*T-qv1oO@elR75zUB#IGXu|J18*KCA`t z8;D^;{P*5u4k#+Y#p*wzlHcxi_9yXci0;1`$>+dF{t2~FPqjbmEqR2*FEcE^FiwFx zK3oNCGoVt3gMssv0d4geBkA7;bV{f5`whP~pj+CHuMYgiKw`a*dXsNJM(js$gio}7 zu}$D;<;$oZ)kx$^{NtgV4I$uT^ zG}(u}&NQG@vtQNZN&!{*yQ0LS^UgLB=Rw?Ih&vFR zLRFjYxG4HIi+0A6LMKn_fuDU6ObHO+LVR@I830{uD2C%$!@820J?~Q_S${j9TuIjN(9KQ{ zSks42&O4Wpcod|ZYKTuoh@6r4$&|$B=aUbU_}nfKUl0(hpEGhU4D=$ev-8gDWq#S1cYZ*@ePDB~5xfG! zxjFAsAqu`TpZq5Uk7we!+Yno78`N{|H6Xr(1ViiGXTZ2RfIe`)0c|ynar}S*Mewb8 zr+gIzKZ(8G?M84fSU#BdsSpMKGM_vQD5_0%GKSbve;}_X45-u`>hYujLccu zmkcO};?L%tx5)aBM@k@ z^)Ew=Z%rfkkpY$Zm`?w(0b}Y(8sHNH#??-J06#ULtxm>*-ucXcqQ`rA=VR*e9@xBZ z^mrXuU*vu2M?I{`$&M4C#~Co06Pp}tPX0oB#0`jV14lqRwgJV|U*(;BKo>h0bYC0R zlOe{P>{BFJmrPFHMb^#iQ(4IRLxSZY>uu~}MZj8dVsI)A7*}2FV#a{B+JjxJGN5!Z zIoWxMdi-vpW%-l!v~nx3swex@k9rK7ocxe_T+GmH3RpAh>n1x@Ye4)q{A{Qp{xRaA zWwKAEB<`4;>;#H>VmydDHL+)5_YrHK+)r9IjGkO`5X;9w+i{cq!%)^gyv5ql*8}nU61)c8>hZ_foSBm<_XdNJ3EpmQ^Z1i&&U{@rD#1(3?Frs59-ZJt;hjDH zD4Vlxl6+@LM}ilAyAp@tb!>uHaL0N4SvKc}Nf`jvcyDhX(2bKsp9zVrsGQ`<$CdBU z60!+ipUou};k7%#3#~l~-b~GV@+s!OX{^Z!-XWcm;C0Vk6TGO|m*CGd?&itInQODc zf2t=RW3J1JZo4OVk8(zWS04BBD9J@Rr^&3Eqo4Ho;qN$0c~L?Dzz)b1hHsa@Gp3y#W-TYOPi# zc;{+$f_ITlNbqLSngnm$oS5Kcm6H;@dUCQio)jnK#3HA7QwXieWqt;UrzLoU%Nl{D_!8tBXqXLzc|5*AeVTbFnl-U#9Egoc!Og@f;S{C^A05T9UA-c1TQ{Z;aPpC z`?IdQD#6F@S10(ud}D%7zOV6ow#U1L+qDTk!M@I`W?fl#<@3<%CkZ~7zQMbDH0m0< zGb>PcV}j3{Z}P4q-so-_qn~>>6WX~uvld>pIl-sMk9v=i>Ra8?-^aZd3C-@#Tn`>w z5`0GcT!IfiJFTg8O1xp8i1xz`h>Q{HwUn2LWHleICnOwl7EMw$H=xnC^}R9>CAQBqmQvg2 z@kp8N^Pr>L_Id13VW&SL>O75FY5P1+$k^$xS$k-&Xk2Cc-1}EUN4(Y8KDVm1b~-r~ zI6v2vb+*rqXgy>di;QWftJwIAZft;P)D8m<-WqM6yQSfFdN^_ZyEk)tFA|mQb6e48 z``jh$W~WE9u|6*vOtpP3|97|36It7q7cbevPVdI)ca%n&Zl`AvY|m#Zzm0rg`&{*} zvwg1L&#=?Z7&PvxanH2VLeycljhY>e7V?DRU;?ysd@ zYNx+PaB)7f9C~kn>49_`Opn#z?Y7VL>>YOca^jq&8QqEgqxLR4eJyL(>)N|v4%FUb zr#G|q$GY}j49rS=*OcvZWp}^rbDi~o?Q_-h3)|-kiM?sO~-Nuibx1lh^!jzg&{owBYWjV0% zu!xfKsK&RCqU_;m9DLR38wYQ64uT14orh6wuqyZSl;yq?p8&Foo$+!3{>?Xcbp7Hi zknU7=8mfl8_?JLNvhPV$IQjpkjK(+k8vh68W~UCXG3U=8A*ig%v2P+`_KaUa+G{@u zY4`dUY0r3#RKwo^l~o!03YfFwFQB2h{cEV1oWq}y&&ZF`&&$Y9%4g22!w=!k&rq_R zDgP1_1Em-j%d=|oKrSa%Pi4h>XxK0QHL!X|eS-4R(jf~$sg097bD z-B^|9WWe|E_#8A08U4pl&7HPU)BqytKG>o0RIQ~!YZ{Dd& z!JL<#0oIw*heGaUHB`vTWYLhkyoMIEGhcJ4eq_v9IjI&+SH-^tn&vg=iI?1X7wOj^ z=_Rktki^Q|b2otNGPI{{RqhXqCVvvYkR(TgSyS@Hebxc%{nvoCsgky|w3M4`wa5$6 z@#HPF?6a2{_aT5=r6ryD2KG$eQ3iLl$}^Xs^T|5}sK`u0|B`o=@yCNJGaiz4^4^kV z5L2Z+<$+52KyBvvXVLNt0UE6QA|TZA#j2T%=5iKms9dE(UwJV8C{!pv5*5w!Ffd)o zM|L^`%6{h;X#7p(9F(n0rw!ow%0mIznI$Ro^^XF0nQuRgmbU~*XRaggPXWp^E8rr@ zPX(y*R?(z!Rk;=%YCVtEDp!?P0c!9rdl88Bs`3#)P2Tr0w#imi`39g??}m2)ja8M- znOH7*{aXO_D&g5-jW`i@m`sLK`7#SHR?SRyk(D(kphx9kH%Yza`3Xi2HT3cN5ac3+x;9dVR>#ADb*@>`{AorlY7zM@z&?| zAl$8W$%EKt!A2{k5VMkJNx`;~8>HY_$s43lZYA%LLX(yJwG{fSzoID$Co0>{iKrB<5z(27ykY1aPyV)q}0Z%fRbRp z(B1Nv(cOpQq#AP0H=(a=c^MVX3gF{=PF{c)QMNzk@fC9q?!eM%Q*usteo9p`2 zAA&giEdDq#Z-hvLxvlyf;JkqT;%o_uOC;JCulUq1USrOAc#S*PrEidWb91g{CJ?&hsvHbliofO_W-;P7OI zZzm_SI$6~mhLFVP#qf$r7h&sIbxF)vDSZFUauWR>sfk3*>eTO|_4}Awaf}5&!YM2A zOw73t2_^2lk1pHJZ?OPzoEwpIT<53geZrZ_Y1MfX>w%=x&%A_R)>M}7JPrJ`^L^l# z;CHQ*Rq7l8{4ytp8Kd0!Dex&SC6;U?kau*yLbn*U>EmP z*RzY00OCRm1cGT5^iS=r;^(4emr8g~(`?mwE?kwrsX8tW%RSERsRc?;?%wmy0a~brEn0^`^0+8W4X9z9 z>l>^ZeoJoMQ5>56RQz_T^WvLOXR)d{4+^~c85)+T<{nWe4Tnt~sG7NeP~NZL%BiKQ znK2aeCLumj2dQSpM%?=c=?+%Sj7{6?dIQiQs+pa_O)#XW)G`gFz4WVq4%JY(S5Lab zG*snnhIgk9SIzY7TJLZ;ZR!ZsOqZ?mK84q%j#SO`xq2_d?jNO^8Dm4exkwwSqczlE z)omr=F)H2%1DCT~yIc+xx{gkvX*Q0hM+&G^EEWmn@Z{5Q?2Y? zyLS!pRO$lN$~4?z)ik32bqhJ(7b1QE?D{P8$z`g(hBI;#99$<9e~*Je?>qoc#cmS5 z9>ed1G66Lo3HSH>ea}U6W`7X-^JV30Wljc`zd!)w!4JX8Ul=EsAt%E54cq3Hg| za4f$)F_aBf&3KM4ixby^_yc$1_YC?cZUp^HSJ2ysp12&jOlB=?@1KGI|JQEG8qkz* zs{~+IYAW)ci86RzGe~hc@BhKoeII@lMEV!ICBGtrBQ~PxVmC)+G`EZ0+1z=RaN~uR zB@BgB4+hb{#2w0Yb!zl%0GGQGrB>UkH08l=1@Zg~K*&^piast=OSqH(aKMcivJ_`u z|4^+*>NgyZBaBjQAFw0)XfC^xix_Mlcly^*EY*P2<?QOQ+u4G!m6?tKom;Ohef!d5NO`?Mx$D>+&Oyv%YqwNzdA;hHZ2jN@i&{#br?H6*!My zqJf>B2A$Tw!j+Loy+AWIxTUgWYENyXRugm^Mwl)){7G_n*D0xjMOx_%?>b}NLPjbX zaXVCd*O^QWN|@#V%;t{V8s0@kUvWx01DaQy(ad7j@Oql)DW_y6TC{nda{9!dhEHQB zw%8>TE()5q*i*#_G8kLzV>uWpZkPOD+x0|C&7^W)+2Rzbe_=ZC|80P0*|WH#Th8Ka zHPQewfNci2g~r;&X=GPZjAZ{{M&^3;TP6-BalA4fdhZ-?u35 zZrv-Z?RzxRdRz9M7lwrE?Kvd0hJVQBGwiCn!=^LrS;BK)TIx)Dmgu67 ze;sV_VVuQb--qcXnm&y0!d;dQ`H$if!$S{UxzhSLK9rbx7`}?@VGzS9TMWlQ_l>&s zx55mM3G3s?`okAs&d1_;vM%AQ=|3LNFIxvd{O6bPJoi*3oI(99@%({kNr^g7Xbr6T z4KVdMVR(C}>$vzdVfY*R*7*1|&i^HEv4<1l)41M|SeY1?AhPN&LU${LMajiL6#kX* zoUqu&G0DVpTn3iB&q1q-=V&r*h-za9bg?0>UF!l;43F25msJCWt$G*9?VmAPX=y0n zpRtJ)Ae#I$wih>pn&p4Tv~9uilbB{H4*Hn}toqk5q)!UBTS9J6#wLW^o{Y^baC@r2 z?YSto=L2rNQ1=$$_Cd()me@Gyykyv0VmhTr>bkAK?%sey3RYe(97e4V%(p%^Ryd5` zf`MBf>;H4;I+tn=R{drS+)+YyQb=}GY>bet{sYL4ip_c;Bs)fvr6h`1o1XC4$3G#^ zV;`(tK3BAI@{&N0&z0CkXU)&m-i!$``RD3bmQ%AhT3@Q6g(3Y)iTzV=GCr`Al&mRP zp&}+(f&M(iXdro{P6O?!&zWKxV`fgPzX_@OW>M(yP@$WZHjJo#vzj4Fh-q)ta>@N} zrN{kg^81Ab+I61!FBNc4!=En@?pKA}FHmAX?MN3D7;ex!tokeAiA#jYxiqlR64gng zYoev5_mWf(S2~)H;zV_Xsuv@5Gmefl!0n8PqclLxR|JBxaMI}_XiO+*x{9Qb8CsB4 z{}i@sor1Yvh}jv%>?$?Q3xj?^hbFh|PV z@x*MV(otggCuO`xNss?79Udj=>r=^I*0f9l%dKZ?Igz~wW=)*(o}J7Y&uY02XK9bu zZ!oow_po*(=RxoB8MM|&rZMmF{bUww=>qmG`2hQt9I;3J8fyvf4jFK(rP5K>kLLy$ zKhA0?tD(X9tApC}rxfTeGITfL6TQb@7hoJep`gd{Q&)$29KWyDV-)xeYzeRjvYd&v z9tRtKpWk9x(_alRrcaW&y5)RGneQsNDn9NDV*E3L4RaB@sz2T!NZ13!?v|i zP2-_{>ivlTnv8S55C>|r0nXYDEm`9{ZTsH}s6q{;)Puk!bph0IGpg(+4}Iy}%~jSf z;+;P$!Gn}|XLF5Z-4GwX>AN_0|BD*Bo>K48z&Li@YU92m{g@g~=r*!j_Yo?7snXKC z`<@uCbcb%%O`WF68mq8Kwv^p48S+a(KJ52+S&9EyJL9?~-s6j~h_#&~k6Ued=RJpw z*o!sYs8)933BGv_UhyW6JCt&VgP~F$Qj4Wx&K!A5?94aYAu8w|6N1EpcuU%G?5;@A z29(rZc!@VBPe)ZCUR^Z?mHx4oYAa*C>bDQEM!9V$9y`Ob4#&TJoYkJ(1r@q_s;qweFjVM-cdThTI1;SFAwQAprMhRXOC0sid^40iJ{Z*fOh2 z$UXq@F8-}JDXcO0r_p{7qp276$ETiQtM}CYAf@H5$Gch=yA5w+`R!Qmskn8&A^8#{ zF|qT*2K(_On(()NG1zN6+yB4Y*%;WN1znpaPuvUn@twqOTRSWZ(k*qBw+av2RCWlq z7}m(WaCm}$)H~ML@>tEiQ{jlQ359ZerWLDQTZ<8pN)((b|KCNe2A=oP|CSQofoGQ9ilCb15Az?;F;{!1;)woL^I* zE1PMpQyD5$E*hgy5h4~u;FOTO=GTx@W-x-Ub*S1wJ+_&w4MgG*FuO}GHLNd4U{!6% zK=2LQx=!g#y;cC5Kic9mSzRF>6Bq(Toc{DY~$4XLIuz^BOokD{e1xIH3R^xcX2;`U6WURdnR3Q;F8 z42}&#>CHp-^A|S9afH%p`TmsVL>$r5NmlIUm{2Lu0#yWcks;w4Atm0}&{l-TO@g1| z=(s|SEY0}w(xIjEYbsPZTx^2D!;YTDC-Ni~aD&xHzi>ZC?CRo4E(hu?1vWj>W2EL@ zDkFUmHS#I3AmgRPikJ5Iy-v43GgIOp4eP|BRS3KiYi1^gdOM?hU!zjEQ&R-GxVRNE zLJUp7!BDTor( zqT_DVq79vD*Setl&F(1i#$n<#7-ED=rwVL0s!nS)95(P^Y@=0^m>-~;UnXVNTKo)8U=wg!YEt8e|`9XmdUzyU;KEds6?&YXz61pV`tMnsTft4 zm+o~Kvl_v>L`k%tbw;Z=P-6z0NlWX>iq2zYL}2D|0a^*H)10Kmw8-(D;$!77ee=*! zbqJY46fuG(8jE{~91JHUVqvVUn4=G!tLWaaBYWQ+bqlm0n1JIH5PEG4+7!RoW_g2y zUX#gW(?u~t4!Tc~aYT&nDh1T^H6sdliw@eZu%Knh?*~sSw(NJ6G4AffpP88eygjgt zv!+YWjs0=RUhGc{^MbR*q8*d)rf0^qr%9X#k%2`Jo8rCAT?|glkj3^)6zu60$6%73 z!l#49$;2^rr~DwQ(i5ybjjNGyNpU~_XN7e@+M$*rCg{Mqsu{!Uc3Ki}p+_PinJPhK z3?e5LcPClsPKxe9#rz=_G1GzXl>{9qE$$rBPO(V(B)b6z2(u!MtCK5i3LmXRUWEtX zH>0$p+l4`LbQW?0aZIP=6R{;$v(zxD&7sq1vmNAHzj%~&4wdHSp+TZA339N`pt?0l zzb!+qY*szG#$io)Fbht0jJrbehq9=~{Cs zCDqV(YKyH&TVgp^^wR+QAuD@;!}5iu(nG^uI(fdwF^si{vEr?2yvV=Lha#oX4QjWlI8=E!Eyv7WgUVTBeLd zVCRa0O9x&eE(|9TlN2zk#EC>z?L|X^p(V3m()^E3ql2MVhD$RMN3IK)xST668rm7* zHi4SWC3=X4niML-hy||nsQDYL?uKb23Wr9$6vBs~wJ!#`;cz!}?51MhYA*N|=juUG zJVJ)StiRw+QIO+>r$I95KrN1R8|LXjQ_iShN@)+Kl$|o@oh;R0Yf_C4JyLq7vkhi# zQ6^GlsenZ+U>cVK6p1D$J?MJHha6!>6s|?1awci6(01~Qvrtlxc}QWBmYI8yZ9^NT z0|zT4++wSi6|7o5xVu>C75Be#M^kmM?nD2Xw5oL62VQ4p4$QbTAU03Y`Gi$9#Z}s- zMf0rgY@Fu6T#cwLHijL{uEu=WSO!aeE>_$^2X~bGxAz0RqQ=r96%1k_fQxmd`a76$ z1G2~z13_?Z6+9V>sHJ$n@Hv05@m!#Fo%`#0$m}s{*~IP8G6(uYD;k>jyon zNZ^*}6eshfOhBbU;wmdPV|g%*K#RyMQem)=I%H0&l)%yg8qlj|b#ycKOc@LU<^?D4 z;i}?67*ZI7>f%7GDV`YgrT}45yeU9MJ^hNqKQvftHt1Y6tT-9SE?}^e4Ughr=gbMC z8Fi7JK}+%2YCjxdW}SH^uGIg$|sm zu;<#*Vkhu;v-%B|AOGLiGA6BP-wBo@7(A|JWaiPsi2+Dz=fDI*AMv%Fi`F`6op=f> znZSL5nFagu!A=q6zDhm3;XIZpEEcLvILfpbtXhWXR3GA37mr>|A-rmf2dgf0Fqy~e z!=$D&%8sTru5=>QM=E5zd%`j_3vLupQ?djy|W4VDzKM#8lHLlsjSydrOyR9!02oNGVReh-@}ljKo*%h3uw9rKcc9|%OLqz&;Xe+H> za5@T=$pp(Kooul{BB|b;gwhYZYXqA%`SPti?g(HG6XoiPLRL{~);?d1|4W(VWXg0)? zw6jQ%e&_7{{1!!fB0Rg)i-)0JCU}O#F`MT0jgoO_;kA#U3_zCpy?cdE%#i z*AE6?#0LYKE;d4Nwd%nymGu7fw&o@x~Wm231|#xoJ0{7h);9g4usCEN+c_|T_bxXMPTxs1j((HD*Z zp7?RhhKavuYS~y}y{T8%!8$_5TX*w+I0@0NJVIu8aV#2=PeVKT16do@IIZg zNF1crV9BCggGUsS^@C)u9cPF>v8~pgAxOb-KuxgDs?}amS3E7(7pCQ*dY~HuFTtv0 z@BvnkwM~8rLTfn3o@>#F@$mF3x<%GrhHPEPwH)~orowol9%tGqCIeU)-=G)zC?>2g zKH8ukx*V2-?yDCXJ6L3f!;~7Vo}M)ZpT+CJN% zN)^R9B1kCPr;2cYB2yb?T5UrddlhV`tEz*!P821goXzVKoLXZ^={nEmjguK%jzWFl zTqf@fEglu3z$+L~MeA$)w4s*Ys51>4^%8k_;6qKpNlLS(PXzNsOL3-Po*1EhdHc*# zSV;%@r8(k&NHE2zp}lB4OqX^l(jVunVwL7pZ}Ua5Zl>{Fp+WF;6xBKa^#FH>Idr8t zg5E_}@i3}+w2t1+;=meH2&^t0SY!2big6~98pXyJ=hX?&GZIA;IWk2LJ10f+i9GDg zGWv3%J;9e}=bW>H2$ZTISbK{7ClYeSF1y3yWNo$Z49<-zgRl$Z&1~}xBI7byoLkL# zvbaoI&q}@yT1?+Tj2!ZDurM%kN$@`$ENbrxo{w(tU4wmPyDSqt>yk->;mfQX&S!8Q zS@K1rUmPmP&nE0-^%t59gQGKLdzh=FH}YULx>jK4Mi*~5b~f3=3~&cip3cGImU_x7 zIxN@w5V&KJC)i*dQXb^7-G7|4d$tq6_6lAx8$EAuR-!DWy z4l}oVq{B##L{)G|QFxN0-LUAQl3w{lLc}~kHb}CoBHtbCrh=__c)K8_z2Dc~FWYoE z*-wYoDjdukzZE1oAu8M90fRn!GdY9K5`DZJ9ByQ`JFp6_bQNbgv#!OLB{S>k3|~`N z71Ra+Qx^mbw@9X!k|uX>0;dCthiT2O9_eAYg@>LStSdAgoQ9MBuow8}0@+cxQh3J#EaEu^{Y{mvly5MqG80>7tncLt{o)8Up z9!Esxcly1yk-3MU7176YI4?2h%;6=4!r7dts?XUd7q{F+b)#hQBPdu$A2+**)L?0v z(iwse9Kys#JK_q3K2L+sON+KJlnHK7ghMR8rBCRB6F;qgMHo1hIu+x*py&pgK833a z92biW#%guozuO%-hl2ojm6P3IEdeJp=K*xG=IS6kh6XXlqqxZAJ**HmjoPc}!RQFR z+W5JtDR{XV;UFajTf1g_^?0~X4G!WM^7^D%2LzvQA{2=#=F-diqO-t}VeddHy(>C( z{ts6k#a0-VoxGPd%YQaaI>}1@cqD4259DJ;;DT&`n$~mL7zi!Z!mJrEpz;8^TWaRB{2n&LEmFrWNN8x%wy%`o+Jv8rUP63-lz*E0K|$p~q)W=HeM)y@_i4 zB92Ke#+mktR`7ZG-XRGbATY(OR2bs;J^7FX7?w3#uiEx8;|ji`>Tr_;-wd(+A~7;W z>k*9ZUgE}X@IhNor%spz+(Bzxy>Z#W!-LS3B~*ATQ)V%7W*j!@jFsldmgwN+Cd34< zzUC;~5~0>75Cyng?{CbKRyIJm)mT{5B7?z8BX@LzyMcPAQxRCRN(Z!&j15w;|5O+J zhZnJ7VtuM9O96&Zo#~_*!un#L85-sSbd2bQ<0$%HqaLoJ159EyMMssI^7?g{_;iJt zY0R3$Of-5R!^;i&x?ZU3;CuAJ$_#5Qy)XF>^9*{;{ca@h79MH}4@^WnD2yO%KilY; zgWKEi^i(TduKi1oWMnZ>xF;XXBN!{1Vu*I6@R3gB>Cg6FF8h$eFd5&AJoZ7B2}5gW z!Rs4>8AqQx8#80b3Ny~|9nOMH+M&WVkiIvsA6ZuGwA&K#3Oz#%zB|vDz&uivhTC*L z4;dF8<3wEpGl&@p6H3fedK$rc-gxQGlJ~H=N9SeLtDo%X%+AZf7;$qZL@Nh36)}V8 z+$@!5ni*3ZFkOX!85**m}&osc#@L3bN^Mjs5 z&xFufhJ{YIJvyvs5Qr|iC%xn4S{P1)mTO^L4PLDUF~NQRAZOqH=NR}9ck3TS4E22VIzJ2EcD-uj>E!QtvGHAYc{=xtKFfGN0)1b zcqlB=w)1a1GS#clq7R%f)eSGspF4;i?Q*h=2m`gnq$3l~`rN%J#`F$9m@o9ej?{@m zj*6K`f_0hUg3Hl`=Q;X()cAPORcY->qX$Lj&cOn%qu7NRe!GMY&ov!CeS-B;IOE_E zsd$NK!N}_>j;OJPh#F^5#YZ^!JZ_CFU?%7QlVeuBQlW__MFnU}WQ(V%9D}es95t{f zT~82|z0of5qf`0leTB(8TBJTqQ(;1*txJlhK-|&a!O)*t(7And5N z*=_KAAi9g$#kjXdk$o9{u#)=9Y$hMu(xF(GCvh*Qpn$&LFm~|Nsbf-4o!qbLO%bQi%jLsl#Cl~K$rW6PL zu2IL=o$HIn^={!J)C}0v9R)f*C>EF~SW@r4ePkD$j!#0d3ov*3%;%-!=!(7r!3Uz- zHJi&8#WazRgz*!(yty9zSXjXz44$O6)pn0bgOBzy-EjgApH=aru$JQIUx8A_Ps8Gh zJd7Tr%j{Y=6WfH!G92ji0tXv*7_npdJooz zGPf4az|};2*J1GI;u{75;)gkHcY^&B)xS|%Om$k#vD2)cqpOi7UBPbzep3rxS~~6J z*POnQTrAg>!MP+EME@|x(UJ;itTDHYp0_KlUPboKfGBkt8A+jOiRn-tJOxk zTm)3dSFGJ=S2w~k_->E|L_#s9yk#ghX+@QLoDipBfpm3hxi!8uUe$%ORCefMG>r~A zbY%grDT+rW+%3|G?{2db9g*G!)pK-pVPu~XeDQ=vHP3Eo6)E1!tWK`7#@DC5!FYkQ z*MgC3;n-ToAbU^9fI%hb+%$Z@UAieoGCG6h_DFRXs;^crD!jd@ zUdA_Cs*S|A+$w2afPQaL8w?riU8xtBDMjP5=M`9zqR_^Ed8KNhG%iGgw+09Ys{wIV z!8}K}*#0W(6syJEXGSaiKAl))>0-J$z1nsQO;h$Pf_cd@(9otdTZTq?wNwP71aq($ zm}4BJv6^I4wP+!0*T$bNWMX_41G0mKOh)yuD2`SOsJrD7un}8xY_FkoxkWD+-wJ(O zMxa4?9Y}FhLU1PluqoWO8v>v64nw8>3PEsNDHthWq-q04Uz69F16=eYF}#GZYs6!rLjw68cL;nK=VQ{oesePAg3$S z^Mhu>mBalgIJ`Y2;H5Sj+xK!V^;j5K8c2g4-p5cNr{;@$xiM^TIXVk%uNtn&05Sbo z=3a9RCJ;-^W6ILbzC>-bY)2*nTlaG5X$R~vX$oGhQr9a9b$s^+o4$u%vKW`u1qxe&7DN?w zB(W>Rlvwz4ZxiYXkTYR6x;Og@=D{n})fh2k#cK&&tDYqEr1~#H|AicB3>UC5Oqvi+ zO`|!YIh1m9j(D)Bu~YZSgo$nr*`xCGYKnz;mRt3FlG#;zZgD(GR)-Zuil z!u)fe5(~QMr(2FLm+N^vY^aCL@cpRbysrYa)VDhpw<($MXcqXiwfg4)si*sYLR6o_Q2W(uZr2esv62vH?Y{y;l{Ui;^%X8C+-qv zNi-+RBPm!{WBRpiRtL+V0DG>+*2|!K$Re2bw+KI3I8;UW;hX27b0x%7p0-`}B8XXZ z8Uxk*xf;C{`Jr_x(C2Qnr!EJuoU{-siB02F#a6`Zs?!|kI3flS_`?j3K?s`J`v!Q( zRB@Ae@l{xUEj|qDB8~-f5H8kTcGHyj@+4#~KzU#_hJgW$9&paY{Mv?MLu>_>)Q(hh z@q%S3tF8D7XCqj9odCiS2TecV81XD`z!Xs%6hUxUlz`oE*P_PeQqpe3>RM-Ou3mJ# zUJKQFE3DO4!w7GqT^p1WD7S?5WM#S62rpUxwQKuBk?T>3*riUJQLIg@ux7N*Xv11r zd0S9HeQi?=+l1Yd!cHdcCe2Q4ZmJW@H6J_G;8s4huBGuw;tPZ>_ zz@DqIG4O~CR@P$r7l9f>2)R-KVTd7vwhhQGkkLb33>F4%8s7+JBij1y@-F1KE+j&# zg1@k74w{51TLb5G%Y|?#JPJ=uk(;_=%k!Gha{K->)1Ya`On2X&X%0-iGf|J#tKrW# z_gq13h3NLFc-egkUJl-Zx!8U}y~8OPeI*$}P;8`W|93J>oY)klXq9R(tIumzhoJ^D zBe;0&C~|qv^yfY&Y6#|B)G;E%+R}LP8>DkdN^@D}sI-u^X0!%Hs;B?l)7WCsDOwic z<*>Uj+pre_noejtMuS>aII?IEF9z3}gjWaH(jpXMrHfVXq}Juugx2O%QZ<`Jq2+!@2qcfD#Ix-b^S2Qlw9c`U zY@M@_t$|B{=?0;e)H6;~kIS(SSHuJ|Y$Ax5aK~Y>J8mXY=gcc&W`Z|-usXJ@gw!mZ zN$*}QGOC^B*lc6h+3q4VS!(YzRh<{bOr0KLtyIe0b}tSypfSYAdgLxJsthJG)4>;n z`CLqc%dzI0k7cIJ{DI=GZcjqn3S{F*|LfuMr z_~*VV;%6a{kGh;omaCNP&7`dpa~myHm@kwP8mJeJUEyc4fh|5mRPR zTBq(&rVQ=8t;BP$IplDys)p^dm7*MEtrSdd zil!{X%MoV=t7vz%<`Ekw=|D2~$Eb=WIe&JI&bG=q2&+onZ4cLT&4w&w;9m-?g}65F zSzwij!>nQG>@YLA0-G(Z?zZI6aK+ayxN;_f4RPqtx_Tb^JZ~w64=HLXnhQBfdaaQ< zF~*%l!n$nfISSA@>H_YO0biglVZ|ltI$dF`5PfqOhz4$Y?xiv8hZkRJFT}RiO=0s} z08{nY`~uXC^$pnk5^MTE;!+zF+y^fz1%s}Q!U1o#y=d{^n#D_sg)BQJ!c}x~7mG5Z zp!1UB3a1K3NUev>uvZR)E;<9%C$v2>;To)&y*i^}I{ z5;9;r_R@u-OyauMP@OAOj1e0L9ij;ozF2Cx@ojCxOZ#ZeWC5zVmI7;CPEjdgaNFynJ`zin2rAEMFd(qPPX;_ahJy;sOqeO)0sf!|FIcj4#9}A8g z!GTqrp6A$ev3USbPml`XxzdPOX!kFOp9m2P2K3~03L28S7c8bt0JzTxfke^u;J#Tq)Q8fuFtArGJ)D{nl3+SNBfRNVf4&^Qm z8DMz17z&$Z14UfhDue7Yu5qwnoFhWm1O8tvbTD%mcrB86u zeL}s!n1|_LoCiSQ8Lg$Pok)sKyy1MSiC8`5baHy5mq#(&FrmV7-w~OWh?&aj_zBwP z@1u?<8zATcfo&v6Sv!IhLkVC*US=s*8K@Ul%Sk4y&7LD{NFgDlO3=3wwwiU6;Z=fw zk?P<~5J{fOU>Q2kZWs>ACK!ow<~y!aw;C0D0LOLsSne#LxPwQAFUFp8&{qZ+D$^LeuheSxOkD;Ia5hD7ba{NFUh{nqIE#!7DMw_qSB5g62qD`V zhVUNN7+=4;aMBotQwCQ>0!}PPIDHJ*ORuuLrux3tu1>B*P{G=E(+6GFdJjO7uP4Z* zDDs$zCXjN3=`ytG+~ggGVs&K2x)N~8aMoqbndPL+OrBIryg-w4h+jMG+ zieKdFWZzb0S)aymUMgEwLbjEIcJ|ay<(VL(!8O&G>QOrg*J#g{pd;v*X6vshoKuQ` z2)Bw#X>7;AY|92^9&S#Zy`$Ps)y=UT)jtz^en<6?gsCAXU5Rl4jn(IUu?J$tc*mgO zHvM43)8#;KY{7L!k>0T7I*?#H#>XDsCX`nfwq%<{Obr6Drar#@!PD)z%Ml!~z-lz4 z#a6l)5khw5azrhh%Og!+qp3Q86_2u5gEPCt$vT-~L7mjau}F20V<>8a2oo48m?HsA zF2_)na5MC;2Unk5b80{=w>firvf!GB~C))VcI@Z zP+S80$l((K8^1WG&)+BX1n2K@p};wkP7E;oN??YDkdCvasN-&N#|=eQ&~d`95nwv6 zS(r-OO~>*462CC5C&$|m4MDom9;|$-Q7yuOBYG`3bo(f?yV{IPAW?d8n;}5#5{oxXzgmVuD z>UzL^OkY8{&}r``wAn6lBCa!#{lkFUG*4>n61J^crdqpp1k&z^wjk|lRI$2u4My_O zGIyKRr?(Jcg(DSoE%z4jjz#V^sk7IqbFk+y?UYr(>5H$QwbAaIh7g^$NXkTJA&RvK z$&K|4%b15-Bshti&()p?l3+Dl?-0p(;gsJMTz8!-<B5r zR6Oo_Pk|OoL&IN^(pFUQp$f+4K@_n}UD#{#pAu4L@(c>S$8u&kh>??40Qde5QA{ z2i9kMZ)o@p?=8Y_c`u}-{e{#^Tu#4~y4WYI`;b6?Bb^C4fz^KJbiB;w!HfMWl)~Hl z>Nz;9{k;9MgSV~DRd@hv-{RiKxBJ|uU0Bb)IB_w4(Sio0IXn}@_n=(7tEjG_v3OeK z`my!%U_!42Rooz9!l`7dseS_|EU(7QlQ;LTfNb~|7MCx^+*5TLz(}(G#h7y{PgV7J z;MI-cFu=xB+kSfnZjkI}Z-`yPjodYusb%``UL!jS!l+Y_4LLDexLGVhE3ojm*9(ea zZ7L9Nuu?`kJ;a?Vl6@zRC-P0UznN!NV8LpXg@-OjnCObI58iYj_JfvMNsaqk!mphSX%ihH$;_RAPWdu!~XxOB;D z#d)@CvYxwHFxJ469_Qok`4|=0k^lHJt!}Ib*OjVc-8eTt2D$W@$sFJEh|u^LabT1I#ql=M@k*QW$e?v}Kr3Ml9`MCwL9M896$q|b^_ z`=XFch5N}f`nhoQNG%VT@#KEMVyZB>;^Os{1@@vr;HB;x!mtf-AV+qRAiqLgg9HM& zd>{zCSh4my`ngi1a;{WrEl}MBi`rHmR^I(__>KKr^_BKD+9hnAFRk-+D-6xXu+@!k z>cosll%Pm1rYxxX#m$SbCPYWGK4a_%k8`Wc%6! zivw`+GJwnOfGFL32U+clf&Cz;3K&_2Q#q!6J~v!s=YYCMP=k9z8$`QVQ0aViML`#L zwb6RO?pTW>=kt00Xdq+^I|K*|?9R3DtMfVd3+$V4T}ckGcws5NMxTOA1+TO$)4f?J z>c>CcVid#0406XN!Ri+o?mYl(UKX^ESR+eBNPJxC=!WLt++&UBogCYsR$jwCWJ70mR8tdE_KFx-cK8r;%$gAH;CukMn{4b2U2F zNSNXl9RPU;ERpikO);623|{2T9VZg{5p(@>WqYycP?VRi!OJOUb22>_$KH6mKwYY& zeUthX;qzmc;qqF9Q&4pIyBD_A59tGk;N>{nEwE3*yxeb}qwt)l-@Zt#hxT*r8`Yx( zA635;@LXIe(+2GV2OQXfqet~vMCx2ezQ%vqGy^k=*=k>bCUau8iCDNVL5vqrcHQ{D zOu=>eWp4aX70D2Q-3A+p88_& zlMkcr?!rT^I`srMn`g}pN^=)_>v0iD?mHi~HmF^DhALD)qu$_x<{kAe-`-W9D1%m{ ztUJ%hS#0O`R5&JIftLprQtM*mn&%ZBHu1^r%j#`Yl$itFUL$l~Y&~wijpS=?AG`|h zppEy;t}HyrVq4e*Dmh#ODIPx0f+=Q!-eeHN8*xs0J>!A)H4({!Si7>GuXx-hODVB8 zh6nCRvjxw)-D*5L(Kj!uiHXzmTGWJ#G%VoO0zI0@jzD`KVp(*(OUPX~nH#yu3`KOq za40>TcT(o?lojG}0|bAjwcLqsLJqUb<&d@mL5fX! zTeP;RV|!G?A0D(-9Pb&X=)Fmz4mDH#Kt@jS3G`jI4IMar(o>rwPmXqoafQAFq5KUl>CPj^=m2t}(8F9xM zbo->WLFp28IhHuW1dGkBK{@P0KpDdm>XX*;l@xp@Hr}_##5e;JuY!qp!IaaM5E%u- zIUQerj2v3wPWMtLzK*fE^f;+J3Azw zr|^|H1@*&rDt`)N?9# zS$l7^k?pxLXV3|%JUqvZVm$?*Ubbg$T9Hp2GUKI~mT=(=ceMvl8rUCo`yU*61_xI7 zy>npm;KIR8ZF}x~l;-n89t#fE6Bd3QwP}hh8Tmu0O;eyWM0t(F`6(YcD2SoRFgJ%i z1Z}Ge0=ve8*@V5!tmvks!3*|*9TQB+k`112txK-3(tXQ6u&`0=m|6f}4v&oaY?puT zYSFt10-E{?1`iurFrck`FgsyVKyjB);3U{C-xORn0lu!zAOmGup>yjdKCLxR&%(yJ zb_O)&&bGp%hS!7{AGNpT@sghvUx5|cEd7)kTtAR@*~?Zs_$0`P3fVRU^>|1l_dji~ zlAmK4QL#Y^ssFLN)vif z%FE;E15v_t0$B-?0~QKG?5-3#I_UJdMO@v*F*-&qT59XXz;^vu0AnXQJYfFcn`UL0qlk$Y}Q#3SX z23X9PCxB?+-X^-rQat)hR#(?zd}>*ZK^1`zz}I!vcm6(|cka{bO^bK?NnYbb ztCu)Ib|SqeMY1JXk>o9Pd6Bi)0$VbYoP8ruhSFsMO@XENvG?tC=5`A<`z}3NAonMr8v-22Cv|#KA<^=Ss!|=2zMOnuM@P_Nw5#xz@Hns z15j%?H&$Y*-8>L8QOysVCk|?{>{iN_;j>sg5{kiRalQnsR2-UAYu;)*Bdzl$dwLnY z_Xu}KM!7p71~1$mV3}n4RbdysZ#h_6s*dr37nB8*I>~a{zcHH=64* z5FQ5RsF_;~4~zHmaIX&I)9gMHg14q0!A^(g*B4)~`kkb}GGw>%8p*>t%}S4l%U(r} zJ^iXO1Fp1x|L*|L7}#iLBoUxU+KnbAM_KMsK}*TNCGd4g(DJbO(K4PsTJ}B{p5N!5 zauht}zAV%6W%re&{44GsRsN6eEy5Wc-$LdaL=(Wg1B9-KU0V_@+jC9XVp*}S#=9NV zg{0hv8V&o5F^sSJ61$d&9VfL+q(dU<8>hou(=V}^go9F(p1F_-t%VB zjpe_YGkgFQ+Lc-zPp_K?D6333ev6G?UAE66ciVMoqbNyJs8)4MRc`ksux<9db>>j3 zAvZmAE1Yrbd=b~IMGbCB`Y?nZvD)g(3slxwIm&99G>HUI>kOqOY!si%+64i9R4d`& zaObYoZcj;Ca2bYFu(+U~(5mN=Va8zv{_~}cON~kW? zVtf0Dz^%5#_@!EmZy&iqt3^SilCc^6NgLf_A~QHr4`%;%TxYl_|I9M^Pv(5u`j~Rc zV(+s}fdQJ%@^JQ&Jy^@Q*bt4S;smZzF&az70CeTQ_!*nP{0uW?4T|eF>CL~+9Cy9_ z{ORXRINi$mjfIjfkDu5k5>(Rg(TeX>umFPogOnYNtM7a|#bKJI=eaAM%Q}|o$_^y# zeV2_ESD9B9S4OKgS@@{L7?=xlaVq>om@K?JXGi;fU>$>1GCNV{7BG!$ZEebOrn|7%Rx(axy$!N(YaMGi{hK}+qZ7GxqtgL$>u`&<8&l2{7h@I zyPQ0~!!&~-L?!9y@l5QjF#Y|^yK0hqG5-|P>8C3{2&BaZR}KL7pEW@FcDg@9 zCjPq#Jxc}OFoGL_)g~Q1$`sZr{n^U5GDYYCj0dTHiXpz$oB$aL5+vxMuGpH@CeLAb zdgrMx=TyWS8xT_f9N_t*%K<7D6agx=D9y(YlSg+1bzE-uoL>kB%)(RU&%Uv!YGVDc zOEG@TB1$)N`hy@Xaa}|0K0r_J%bTNEK23+6T8p7Vz!aU|XF^W5d{|}4^xxGzI-G^B zqa&m%q3HzANU+xU2)Fx+RmEpsZW~HwQGGgkt4o@s|19&NiehsZ`HJqv=g__QB!EqQ ziJ8N2YtoflhcKvi*uKpzd_Cedv~^5Mad9Wct%l`D4{n|_8T zT$ZpNDX3T_=_T$-Kbd)`1SYHcW2!$$tRI|+Wd(n*#9C^Tj=l=LtyTJsnQxarr$@p` ze@WZ7m&OAC!4U7#01f!;4IBLYLl5N$fVTMg-~L{AiR7!S$vV`2e ztVz6j{v)qEM1uC_?v&ooJN%?oU z*ZF5S!frWdJFw&Wut8lc=(7UJ0b^8_^%?fd1yiua)yXYm6mLQ2qm(W~7RXRZI(njr zqx4t(`_ak)|EAWSv<5@s@6Y(J$PNkI_l1F8jYTy|C(l1=&otm)`~~Z&m&)JlpYU9s z@K1W}BZlgytXc-@G5-ssL?|u)DrKcCJfOcC8?%_u((a3Ap^`c~-Ceo|wBkKlv)rD( z%?Opr2zFl_AqKh3R%xof_@IWM>2XyQu~2-L-7nqa$OS`Yi+H?*zAyTBmC#pe98mV= z-O_5+`(M70F?;e}p5Fu)hx{o9rC7iR2S934@LNc9Xu&2$vBh%=LKnmOcNmtwaCiBO zz56I*1$3{wM&&YQ=@r`M6S{X&7AI;bulk^C`nWA-YPIC#xj0Gr5cM2I(g@FRyD33$ z1E@ZezPU5#(epg%bQ6tcxz+By{>2-3D5}FP;gyRmYMOx2rt0K1jd z+goZ|K4irK(VAIrdA<*gv;5OSnwRru1bw_8WIiUDT@p=2_c`Q6fYHL#1c&+(#F{#{ zD4(o>`-UxcfBq$GgDEe}<@LIZad|vtb&o4%v6q9x363kG-sA;zy|mh}!90--v)n(N zdbRfZwV7*$KdDbrj4}h;T%+M579(jJc$n7?0a~vD>0i2q!*Av6h`&zL>qgbOF$T3J zO)Y#?0OzbSm0~l34#Wm(&c(*k`5sP$I+vEj^REPPx+%}}`MjIwn4K=Xw4^d0wD(|edhFJLjpNDnX0Mxa#vik{UI};6?lfhi(1rb>>tT=f>Z@TRxJbzS88eXf@(@v6AC@g}GGo#Lu> zE^-x|dY@R=N4c&8A9_FY63=?CQR}jI1i9MVe_ZXoHLiM@X_BknPCCU^ul4)^SN&VV zfA$^n~rf+zEf8vDciUzE2(uU z&v-M}kI}x9t1@}RT$Ncn&sE4DhCm9|RsJ+r;cXZqeZQQW(u4RqI zO0J>)dxwkl-=Y4Q=hU~{RIGm*q-b5mfA5CQMIrNIa;9N#Ci3AsSK&TZVYEV@l8St} zJ;dn;-kIVgz~?CmUoGO;$BOi-ru5E9Wc~dVC*Q*%uN?XCb(=~)YZLk8b2jNyFOIyv z4+CgyvPS-_-IuYO9r;f{(qeh|$^^q_BmYWJgYrz*t&4p4hSK-EI)ys@*t1IBq<2E!k$P7u{Xwg{4~|Jkx9Nrd$iLAZ(xm^>_q~zl6;r@)q$@|plY36+m2WdDB_gRX=d(G9n&>Zwfr?}>c!dLl1KJ?hWa6 zTO$AcWGH@J%<~adhFzE5LOI`z=YB=Ht}gN)vimrF*H1I|idCv8;|)t1AzX5*(_b(9 zYB>b4$1;vt!6FEynpIY(clSoV*B;~alkSUd`P187`kn6GF8zKh*UL3zE%>4lUyO_V zL-x2S{kVG^275Re@iF(H@ox`%7p%I4Yw8V}I(Jo4eZ_>Jksdm^8l%ubI$n21BZ!cv+(lXg$iWDQ?U;p-gf zzT4Axz!9%cJyiucliC}*BmZ@~hnxt(9y{w;o_=rUbv%WmzI<(w74EZ>tnglSdc_BU z;s4k(pW_;eyv~{?h-Nwo$4^^HW%?QaFxY*}p1vZ&z7BeYlco=Fg6C5Vl$<+Fp5ALs zCy|VgQuls)Do?MuJ^jAahbTzSV(QRknI108QofXz~o~o#x{=je+r@vA8 z_Nw%Us=iR2eyaK#Oi?UeY&78Nqg}FLCeyt@D}`z7Km5Ixm0@iBOqRVHKE(CR6DH77Q$QH}C`!YVo$HyVj zjmaYphyQGHUoDjoV%#8`uiq7>Uxgj`is!RYzEpC8f@ct!&s&pC>9@#^`6P->znK^o z9^DhVr+26K+_mfx%sgY=5SW4V>*J>xClo*-6z{jJl5dM{l1kX#mwsLR6*ajgSVZ){LxnS@PFB){Ob98S_>%=BsARQ_Yy4ni1LFT9z>`899{ClxNJJ%$PU1GGoqU z#$3saIg%N1uZeuEAUSr05#*BH4 z8S@u2<}GH-SIn5Fm@z*wV_srLKH}%o8FLXcPs>5fn0vT7!hn~&woGv8b`0^taD*vk zx9fX+(pyP>TJc{hcVp}Eg{k?4*6|BdceR|IzdSiRHQ$<_o49;&YIbp<^_H2%zRPD@ z7iVVgzPxa@bzy#@_0rt@;`rGMQ?2t;vr`M>3$63ibVUDwktXIYUYwhKp*=6moNdhw zj`oih_J?b0Zf<_6wSRWv!sW@S7dqPcJ6q2#Txy*k{||J$IB~gzglQY3RTm*iV@_OL zm|1AePu(#yG1WTKGt@KMHQG8lcX@tdDw??Q%w^&I%yPV+nJnV{%(`a33Gt6>ke%vlhc81BUdi=tL|J+r~7iQ)}?iV_$FfeKB{`dAApP#%uGdtIu ztg!j)+}z@Yx$#Muk-`4Gqbz6Bi3{Tk3$2sWmtSaSIO2y8cD^vpz~>9+Fa2kayD%|R znCW=IYyG#tJ$LCpM83I&@fXZY{{cz`@goi%pI@Aro|%{#zi=4U6irS{7EG_SOh`{H zqGAe*cVC)XXgM!4XwN}?gaT_@m>=hf<`XD{!ooH9;(#o0tfX)8iLsF5Jz) zSipt57Z#^3a*xqlSOkd6m%;-wRVYn>=CtPva}zIJpgws%H$QjzQekHPWlKf#Q|D$F zalUYAer|DUVsU0}HdGcxi6_j1Mw^)foMa@8VGp*j>6z&{+ObZSJ;@zbQ+EI~yEs30 zA(UJkpV8PvvoLufh#Sv@sBn>>DolU?Yar}RPAyE#&s{;y2?z2> zre?kX=Wt81W*IJQ?c$BX?A+`WFcVWkD{g>Mz|#W@WN=%V`c6(=7#F^^*f}JfTOv!t zK@oSjejZ0mXH_D{D}dhB`n7S&ugZECxB7K)D(!r8?7mb+K^;%z#ou;+ijU)_TD*@N zscmzgEu)`RQsjP}>biKf-`SY;b)A&7`i*W{E!0b$e07}4wq(_KeTvFStMv6&?o$+! z?MN|~fhNbxecnK;tF8BB^zUZ=UB0P}0kXBeBW?lK?mE8$5ce&g!&e%Nbg9!^cV^RR z-{N-JBH12pVS*}m%0Q|uONSYEfDAc#?&ZMhYSZ5DaesV|b=jkm&UEbALjRl9Oj=w} zTP-L``KGMDHS3#O{I#0)kdVb2wCH zeP|JI>Hx>P|5?>yMenkrSPM(JuRV||^Gj%yx9Wa5V=GC;tFwMnqmfuNfz)v}kemBP zze3b47g`&Ad8h}8wca)RRBIVI=~TMhlR{!h2K{kplX8`*P*D;1Nfn=T;I_8D&Q;MM zt_}5-RxeN4eKw+gEme)7s>-V5K9jGoD)^7}9wmapbJ8DwJ(sdm-s@8D*Xp7+cJ21{ zS3I|up4GXmDWId;W|4dDUahXRe!ICtA$cq-FHo7>e5ul?&bHV zD0J>$%OC=5vx1S`E39y%dp(#yxH?1W-`tn-jSOFY#8<@I{6=oC6Sob8(oRZu+Inuw z`t4cY)#A6e_;q5Mml%gU97b!=#O`12ONHeHAQhjuzg!07mzD$hmITPJE(h|71jv5~ z8Xy7kC(!^UAOkpq2F|)=;Fy}(BiIKGvcCvJ1jrt{Kb6I`2lFcpe=-^F9UlBOfUp%U zoHDcB`|UEZohdJSb%C8rl8)gQ?oOy7VgF;GO~~zcyfhk5F1CRIgI2 zTZR6O?o%w?Fl~h&crfLwgy|N;sgz;`BBHC0_xeqCy~#QruzoEJmU2f@*(^YBhvA?s z?|pcG%;x{QW%I)$%jbVtn1A>3=}#xKXN}HTo9*TRkcxI1Aj<$UK-MIHfHe0s!m`1A zITEg3;-$NeWj**_)#6vjHzio>@O2dJ>+rkK)q8w>yj?2auaDaf83nIvad6Rk)?L5X zuXndFWV1hVFwWA{?aw~DG3>{>*%*E1fs{XBw<+JH>k)rJmn=WUYz=OJJi2S}>#d;P zm+QLOck0rvKiN=pts!6>s4C(+p>>@<-fR>&8K*k^(b)aQgDK2OS(UgYXb{EL?zKXF zZJ_tM627ZM@2QmGBh|<@Ae~klizyU$pD^wham79_@z=DN;xb7t_nXjoiq+ja%^LZY z0F^o# z5DcNTFWR}&uLB(^$#7e3oRwjg6|4MUu&*rUVxY&IRS#kB)fs3*G&3iC) zYkal)w9htfHKmRL=GqkM-+PZhSmQq9v!2cM@881|^@$yA0+jk2n0lLFl0|U;nl|&V zzV6rW$=Y3-{82Cu74Mreco)-m}#2Ki2&Y-;{)irxDd%Y&N+YrHac zzjiMJwfHSil=duSRf-;X2Aj3+ZO_+xB^}`c4UJUC?yHPj&r{s)Yd6!eJpsm5W`VQL zZ{5P!P23t<8)2)JSr)|V9swEh5`Gr(A4&Ns@E zK>l}8>YN1D05>dg)&j)%-2k={NjRk`Q|`-#{tdDFCuB8Qc%A!$bgF4<*41X4v%xq9 zXGpmq_us`NwY4z8D!-}Cr?&V_O~Bq%gaR4qp1RI=kk<)v0LoYc?}%yLknfR-eO7X!aQx)$K3ME`7ZI zCSTbql_K2B9*UXqxoGR|$f8?neP%0aWp#XolcFS-`|D-P+syK=^P8IlAh+=fkBY*% z@-^;VS_|W>Z*1|0see&Rr|JC9LnujRbt^cK|9MDA*rdkpT#Mf;iqvYnMiBC8)(S!Z zgMwCB^&@Kc8;DY!`)sIeP5B+-RxX`>C#`U2HuF>!(Dp7QSRC^UCA1w09P{-e+SY9G z6*E_2E_-#uD<@c>Zb#hFwq;N*}s^ zFhzmG%vdV=2vg_hcVpF zt?I0`u*&_7I9-8LgZmjg9yN|z^tV=j>iiljG3OPAwTEruHQl-2)=G3|jWviha36Wl zI_OX8i2m5!RsOhXY8|$`%H1P97`k7w(an*zab%FomL4@?0-hp6J-Pp@W$3OBBgiGT zj<%d^y1`6-nfovIhtgyoMUMNe_cu$u^;qjyU1f;Fl%?FO@hPfV zTKMaoyxq;&K(V#{CYV9FaMvz^L96%&0TW)+%- z;kXBbHs|-u8rht$yeGtue_JeqeIL0ek=!t&JZB|(x9A<@dsR6&rooPwz=LVZi8yn^w6lZJt zVY6wLwYW^c<94QQy6Ob|S5BZk6ZeOLPODkriAe^`;*$pf*X!K3Srv6nax69oFFys+ zYg`kh_2#qSaF;8NYxmbMOtt*?L36b6+_PCsRXau~<+r#`I382(5kkV%vD=rGK32H5 z8m+DMuZ~aadWtrEDNu-an>E8l@Lv-*S%lyl>isI(T9nh|cW_G@W$iY z9<7CO)?j=>)5RnHMciGd5pJ>ww+0i=97i*W{X{*frH60V`@0PO?=>DhAru&a3Y}_^W!lL6#YJMHXJ3d_q9o zvUVw#L%JcW61(5K9~Bk5S0cNqxP$DMrh9`UAHon!wmGn-IZ8F|rMN)Ue+9)Xzg}2T zq*>eUSGrlHC>*)0K-cZY05$Qx#U^_uk2=zI5)Iyhl6q4 zYusYi?`toskX8-WUb~S_(Y&Rt3V)dLPra_KkK))`4wAyd6QpzlP}*Xso&&CsqJj^scpX89R+eI zxzAT`@%x%?_L~pH@DVRjK;NWjrxUNWFkQ8{6jR8kJMmSTF$-D$q88@Z&LgZ^pNbR9 zzR`1vr%YSW?*Fm~Qp-q&@4&yg8@%uL{Y`%RRzKWo;?>T|{s?VWfic5A-An@Xkl%8~ z`@??Ajo!EUT368`HCWF4B3$*4_`SP)?=`+_hkwzy{oMluZ)LIR9LBzi&lA+bO+!nt3(k&i%f6I|VPLZ-=6S^7fGKuJfEnDAU%t`F5-8ePv^@ zMqH=uboXgqm}bF5d^pU9ntUa^No3U=C)T>mxL14b?x)IVO5h10|Jf7yH^OFA$L_~0 z;;eVyC*Y6Whrws{jvLzJP7DYtO>Nu<9#mj|o%^*9goE2#-I^q>6rz7&OrD;d=$-780v)Iot&s zO53>CqaR`I+AY3rzu(#c3jyfnU4U~>i{I1?JNV5k2_@;idXEG|bFPcscZkCp7$jt; zbQiq45P|3zf_q1ZPEg+)q~@@P8(L9*O{ToihUQ_)d3;_E(@oQFSJ7v_+kD;NhqriT zugc<0euJ*&^a5o~+=r-Dq)wlvqcZ7bE0$6}Iu*guI?O6HICpX!)@&zD{J96n*}?ht z7Zn)0Kf2$jwT;_9L@TF+6q;J}@BUW^SS#HZQOM+Qum=pPmPD*UBPO{d(hay1#B2hF zhtCti$@mHXmP3&(c!F+q?i&~`8p^EVZ()dB3k0J2=OB=b>Pi`oCX_v~p5?P@$ygC; zYEi#gE;$r*>$dO?uHSU`meWTY{bpCyiAvd(O>agLK71D(gT{gAk7ZD)NPe5Izm*$+ z*&H{;7L!kN?{F_$$VnaYTCEznXmWIZY%x@iFg@GSJ3pUyh-R-8=8?gg*)D zI{lh9pE*ol=ic;y2Ca5qgV!@{R`d(Yi`sqlwLa6~tM~ZT`)#&2JOKOsq5;&}!nb5> zt#4z{+BRReRTv1<{nCAk`p8_We`cKKSYMhJJ&00?*hc{nIujZ}U zL#px{*&9F#_WKoQZ06s)@8M3r{O81fbrm4@m z-*%7i?A%B1LtFaz#~?meRRv3vXht+I;rc%b$hj6AWPRj}3l+ymLx zPtjzP`xsr6d4oRy?>Tu!^pV^pE`r|{;>jx#?GXPZ8xeBaRH6WdH17PvXsge$ zkZOp&u8D{rrU5xr@o`dF1`F8UN+cl^t%oCNyxTpBE54o`qL$=-({Y<|wfh@GilPs` z=2VMrYjGc=D5Rp3g?_l0Q>}onm5RonG;ko&ts=aS_xSawo=pt89eO0-E1_D1oelJ` z0^H3S_eS7b7jNjqXDEXIHDWT+P5XQbv&aD^8QI2QC&DI<&L_Gr7B_K1WT4ZE?vG5Z zu62Jwc&j}~p>#LKxK@!DR>*OLLbj<&$0~TnQ~!XNt*(y41~bf8k8g)xi(3@C*O6;o z$F@U*WfAsf6_fH8=KFK&V|2&WdP376c?S1Ywr#$|qExAzZfJy(cawoQOTDyebf7gP zthB2lcOYRah6yU&al5YMZ>xw!_*LiLZ?yBfXt_D7-9(%O#fI)vDU%2}qqYF{S%iQu z-Fu4F)ws8%wIRdq1q4cOW=-rJ?Qyf3K{!|~54IM0`v~2AoTCq4hJNtd=BuDjYqbIR zH>|9pmcfqDt?sC-uKR)CK)8ta-?9+7=q;pWPTse_A8n%!st#M9&6G zmpEpS@A0z_D%QS9I|$6N!M*N&g-Lte{~^O$!B)!wAqzLQ#UF4#XKjzFEoFa6*${{;5iNmztL`VodEnERqblvcQZPGwW6X$I}pEk_|^a4*FMJfch=>sRMI;757nbv3tEFGK!3qrpKSS@v^B8XdozuakAq^x@~mFkqfaeo3oXoO6> z-&d7CVT=2L?F-_F)HX57R`*c4h4M}AU+xv!x4KuPv&pk&(Q~OD_*!elA`&6@1IK<; z1&=&zw**oZ#%e21t(K7N6g?!kwEazxF49-Q)k^f>%+-*kkgDU1(|Jl)YMa#j4^WRa zuarNx2Oa5Fpy^S)?vmVHTyV;zRi$vGMB}xhl@!IAMs~7HLn|k4d1_1Rb6ASpIAv`* z<3VdyK-mvqFA{U40e~b!e{5?8V=X;Frpvt{c-%oKEqP%M@L%CyX>M&)X;xk9<60iB zOYVzhXjnADOIe79++of&mi2caiZ-rR#*J;tpb8ZYmZ4i2-=s|0f5!(~hwb_&B0S-G zoBL^+*KYUQ_8^1RovdUnx(fz!e~eq>$ge(mKV}?$a(~XEYLp^Vg2P?k@-Wstc7M!S zEtpI!SLgoTf7>6-;<#fauHEi4hkUm6h_7t&2W1h~AMsT9c2Txe=k{~I04nPil`G-;GSX1-Cy0yxrG5= z)9!Ik$W0zXgJ?y63h1j^Or30YY)7=5(pVpT0MV;)-{tR6T!$Ro>OOpTOSV?ab?)Pg z398uUy{l|zLR$7N+*>m2TqCicjO>V8rOToB1`sK?5s7e%r$Vp4x=RZnWOTK$OI!nm+3iBe#t^9uKj!BFo0yXc0BuR7;9o5V3vwGso(?x&FNB`tvx_zv-NXPwg0(g}xBM+iN* zmz{+wH>aj;Cz`UmO+UQC^aHSwME;j_&{nUwH!DP8?I;ne5;n$;?K4gI7jVTD6F%-G zY|ZYgCTvnb>P&}UN~DnNagahQeOno{y)Hg1PVR7jc)zR#jo(&=Y6EEQ@sPQ4(kj&{ zu#l^Yc!w#En)p$a#;XD9nt1&Yv&a7g{7QGPB#Ddo{Vmb+8uwZp#Y*lw{jQxn{sfP! z85SFZldwS|^7nYGa*)_y1~n3D3H~~MF^I!Ba${~LaYPBaqFg$L&OBw}ZqwdqqVm7h z5jJ8mqO(yT^3BW_z`T`RR}i|Ah(*Tdw}RRsS1fTw zU;IxL&OzoPhYO>>>Y9+HQ@UFfd;)=&9$uYAKwH+RIB5Bf|l+e#X7oluAJ_#IH*X0RWU>E@rT zcS<{s)E?{fhY>4I^PB>U0Lu24utyAE1&fij;DH&?+-22E*>1f9<6Z$R07- z)hZQE0teNtvUfe8wXb!b1XX(ezys(tK5-bk-=~ER_woys6mV1yu~mzA*eIeE#p`JX zg2adI>DV{9ht}A1Iv@AMyxo#kCO4ZUZ?t+VX+`;?tDBY5!?U!F#a}G8`x@21zVgjD$K`+E76luq-*w|F*hig!VGJbhh;_D?@7gNA+NI5lK6Um$o;-$ZwPR- z7w6ssA7RwRB*kaWVmzw-u-eVkRJl)D&Gqj4*d6blLLqRvwUeAB8IEnfj%4mOzp33H z#LsN>2b=vS87xklY;_+1iZ$+&B=okr|B-5GZ6(-lWnWD@8(XFONe&QMD}+#Ol41=zy3}Ufdx#I% zfF>1)K=RuZ5Qj}gJc;Z4x-P%%8i>Azi2F}+tn0C@|iv7`>P-Zaf+=hvT z9RaXAWtw|;*d#3BY`<1y+kwA|jbyvC2*j#*mDmwP>fJo|9aKZI%q=?v&RPxMp5QTT z?FzyWkRG-psvbjVBA#N4R`!ils)nzDQi=g;?Ie!2(h zOZ75BdAnAZU{$E=VEXz5m;>AW+D()N(xUvf=qxJ12Q9XQbVMcYk#QmVfsCgm)rdYFR=6Z48$2l*h(`OJ$XTHUz+awZA z{#x#M;(Y_1yTz9vZ>J+;WfW=$w9H-1h5`-}CT+r@GPMYO4*4C+dk{9*i6830CA!HX zCC;FB$b4=HM7DQW&;?>&HjAa3e8rcC=!8}dg)SypJiNptd1?jK`n?orb>6jXK zi73(F)XSglSHUqhXAAKV3St+8-R9Q@f^Ja`Nkk6%qIhjr#%zc9D_~Lw9d%5}@yzd9 zq}{cKShAAa^t3G$a#TU+#)gxkPk4jvTSlTAN}*bIE7d3rU=k$6iP90mi%KWWhfCaR zG26%r4Z(3rF=~Y)JZO@#I_fHrKvawd5$Hi+cKIWWB6lWl*KJ98vHr?ysu8!2gWEbO zBj=?40Mjg>+jL?kC>VRLw_R;Kr6t{fUMfluZHG*G`uI$8U9Kjowa**YdwH1(++}FB z^}4rTW*@^|{6XJW*?|fO$Ez7yJFLjGQa5e7IfXZld>$|dN}6J`6wEbXJf-t^9$t`Z zMGb$A`g*z76nL1yPoVQR>TgrCABPU$ugN!w6WR~ogq2n20bQkLw-rZYto7{p!1a1f z*u6*eO$KZd#3js{mQe&-rG0WTk}bZ4w)Muc8u=QYw6+9HEx@PpTIw`GGt;lz<*#*Y zfUG0PW4qSYPrxdj1p=~!B4N3gOv;ushc~s?58y<$LxdlCd@v(v^d;uCYQdFE+KZ@XhO{~Z^aUu z-Cah>1@-_TSPjN!=;eOp4nK4aeRddECDawl*}b~KXX%OVNRz96=V~Qe*7{xSG(*3j zJt~1m9!DiwgsT)4!i#3kkSz|d>3wteUXF&cDJx4Zr?q~U zR$_C%*5;N#b^<3l@Bge$?Xy=|>?}}7$<`Q0O9$U(8kk7ZqKbWFMBD&b6`Ueq5r{&W zf+uxhvK^R4_albr>LZ-sqlO3w2C6>NZZ<@TO+jC=$EP~7;Uo-RJEZ-X0Dl68nXU!0 zCih_?i+VrJ-bdCyDo3o-k13?5vQ3p_EE*empG=6U<^)F>-$~_gs`+D4mazy#@G2#L z9HE5o*kHiy*#$x61gw9|cFl<#^h{u9#a1R_Z41tgus@gti0vjC8_*9iyHzz#8GIT4 z6j>8I^s~0`C&L+(v_E#7 z!0znKZ5>G0!S6EnyDY9rcS=C&YNrpTL9yn?3wRIS;H&QC&Cat*vlh{S{r@CR{qkDTtOfjw;U~DpN0@fe~Dn7d&7eS&Fi6-Dax%DpRaVk9Vt@# z2(+$tnCguj)pKo~#8Ja7vbQTa?ijlN@qH#Db?#rG6b=Ahl;iERN|ZhNqVhWF8%^`$ z9I{bl{7+HVp1;pdC$GA=S0O}>NTOY*ryKNMTGrud0L~+ zrjv!g1?n43WtRgkIFDB4o@NuG{4mGq!t#HC%~62hY!G2%z57W(&bV&^!FmMdzhy|f zku`Atz?QQi;=8^DtszTUw?%nGX(f*1;uY!vp4Nk}ZVMojN`ffv^}K>wFX<02ed zdpGB|cv%DLP*c?sj#2!aBBpxfU>g0tZN5zwyp`aj4kfjp!)ETNRLNcoSLlW@<`*D$ z*)%nsZeQ@d6!C=6CT}i~sp4&7Q(v*&Z`gxiq3=6_K62j!f_h%D5ghG_L3e)-)}?Kk zi{&1|gl({)8l*?o%2|{98(QRxo$zWy{H8vg^x=p%TJ6`_h7rO{ZUDOFNCMs7V#oEJ z9N%MHoA6L_bvsBbTggn8HzgUa-j+a+y1^WqVmqvU=((S1)z0aCxEi-#;IH%bz&hyb zfArAJ-p`zh-OUCFL<5u$Tt31pHZasi$Cee5PbmIn(iP(LKXDuwvxZv34FV<$(ob17 zS+_e+p_FU=&aIwwg#0C(>y27%O(z5=`}px{a=DD){>MTpK447n>m1(n>X&u6PjY8J7-3bA1uf0tpY}V+jbiiW&E}5ws%LNk4 zNclCxgAH4_ZM5V0ut&4s-^!`@Bc9(?!YkNJuE)IkBp6)-!VbFFQksmgV&gw8Xb~ zMU2hw@b1-GBllNe5#=M@ub|CVqGz&T*~c4Z{YK?fTWF7xnM#pO+~9t5t@`u)>GK>L ziOJf1U@d87G+38!bx-l~-x~K;vV^*4qk^Zmr&F!T7{7BKt*6|-X8F3!qP*8N=zY#^ zpF&?{ba+I=Wk@uF!>jo6!a{#z5uh;3zclhh~9b&U!t%`TH`CVi$4su*JB&Ipck^)l<@g+8( z*;K{e)VgnC5`{i2F&`=O+c;2aW=Nk5Am6YS?VyF#D#4*UPT0ooA9eH?=~~;Ku0q4P zzvEQ`RDfP{L#05_Itw0Fz~CHEcIR8z+g(RKh^A9CDYYz~oNr(sNYTa~^9Hcfi1vz{ zzY#|P<=x4-whrHUPthH5OqZp98CyBu))H8d(a_*hD1_CLpV`FiaBucr|Z(AI$Q zY%unRQ9gtIupJf-Z}YMdCR}GG@OJ*hor00p9ts;MPojk}U7TRU5oHy7NRS-rJS9P^ zl+{L-){^7K4RPnQ2-443vcb~#ug0)0Pv1-Kke1J(2ic^930z&h4fBfS`wC$+oGkXY zcny>FC^_cbIXP3h!!e58?Yv+`wg{0eV@pP4)2;%C`m~vQ*Absa#w_kjW6Q~i5dL|8nYsEer-h zzQ$ni7p7{9GLu#NmDy*9n^cOAR)>XqUPv{6WN<{CX5G+s3Wa5b@{lOSQFjT-%Bgl|T3E52lV9buJx= ziM#9#O)A#w{TtBm_e3=bp4NdL{AKsk9MoFlz9j^rI^_*%ixL&u;%}f5{2pc>^uZ$( z)!EuP4igYk@BXjMzx#1g7aTMSI6E@|*aF|&8S#*V#TkF&e#_Oyq9@3q5KtK4VU&EaH6?0%UW zDq{Cq620|Vz0keh{j`T=PAk2(o>zdhpSPa(4-PS+b01*@wfXHb&Og>3^ZZ@+62JQV zp_^KL16Ci7f<_!*)sC@qKLPVp;`!G5H0kHC3GCt@Vd^@+5^tZ>ls0YyON(`tx=2{q z{NuMo5g$TIM~`tukN)GgulQD6Dz&xZXZSY9UcRt&n(H6(pT3{+GqnCV|J8E;2L3Bc zZ7r)>!v|!e=rugXmHKltjmuW1`Ew(8?&Z{`EBI6Xb^hpUpiyR*9zRGgelwUqTlnK& zPGA2$%E|}n#!sy?K%PfI*~#^)P&z>=$OM%^litY822GhJNKNsW>f=u1+^mwTtv0Q3 z{)VQ-)rGMZOJjXa!<_Q0=f5Un{g>w(t6XDM#bG>Q@Tyo_`DzB^=Li5ysPjS&JP-bU zKt*O;e>7kG5Bw<`Vz`u$lgV?JxmUHqT3WbrQwc~v`g|aHfpi-^KTeA)h*$9*N&~ty zxzprnO`aBw(wZ_|ohh#UHXen?5w2IoW2}iDr2XglPZJi`ZupGXQ)-j>&Ai-Mb}fHW z^OWH>G0&~Z=>5+(`tvWtcQRC1hQa-_8rjJ8?+5v+_=$h1IIuHlg`{*PZ(RC+rlPDb z0r}?V1KAj>IC4p3(%TpzfV)9&Z{EkB)I$^rxpzI^SjJcy>uOB(V+>(PuKw%d*y*Ra z%M9{@U`E_kCfL0=&IlZfwsDTylz1u@JGp-!wu&%3hnwOv3}@>yRnAnSR!j| zGADXuj_`U}>NJ1KOy+Ll&S?edcP7(6`Fzt?O8~w`dnte-7y>~m^qrI!1>y=RTr){c zl&4ANN$$$E)CvKH_rXx2o)`5h1znY(bAm4YNBl|s0)NWdd50?&9jhe4RRY$F|0`z` zh^LR0$SQwG zvFDr7WI{6*abYuM9Pdd5-Vu+6Ne)qFrXVHuEc=OM=vO@7&>5lsO>|nmpev?X*@)hqAqCTAk3QdEl_J!4Xu4cZH1L;s_oyfvC7rhFE=mIz znp8-!RYeC8rt%^@&3 z7JORpayb@~CCf!>7GX6WZWv@PGwKy4!a{cZymEY#-fVhI(EXb3-lDso;ZJHwz{LXP z*Q-o~$_T+_qFZbNem+^n?Od;Fj!hi2iXv+ip)OgX@((k3z^q8<#UoB&mr0Lscz}@w zL|Q#%og{)+oy#1?BBtu;cQq?zSXz0JTAR~wlPWofX(OcIFej*73d|gyav>-s1eJZ9 zzCjlYEdOH(Soc34SXbDCFC<`z(XJp|%{8?NNZ#y$Kr*9gAjM*)l$a?cJ}NUG>>+xX zyOc4@@WKH3NjhKEFxC9&4+X@0Lvsra260eI98}i9k0J!L{BJ;a_Nyz;`2;kdBEER$ z>=}JXcy{VezOLN7uVr6LTT4e<$KH1SpOl`VX5!4k;{43)xoGmnGvjA2^6}II`_5dR zm|x^V^_g=M6KBTfFE;Djpv_a`XJ^i|ceHf0w4Iq*`Z)7oYqxzN`KoiZhSFBe)mrQn zU7WhOFr{yivWSJn$w|&?+E-u$Fx~GkM zeIz z$4ORgu>hKnw5`&ILe`PXU)AAjuJ!AhNey)9jq)n?)3xQyrl4Q7l4zXtXMBKyRqnQ| z?G})AvvX|KRXI&kv#e^rg#( zrZ3&Gzj@(O^JM#hWxOy!4WGMSoVu%-?_FPwIiB11x$H8zaH+^L=gv*SW5*V*{7+0Y zcWG+&B79Z6AD@^A50_@9xS5!4Ui#?uA(;RQ7qAu=rl^>jm|5Us*v)*xn(u7SE{2}s zfC+f~!pyi@QaF8i*1nqEyb!*g4II;x9-5cgx@ZJ zt)K7H@>hO!d}Op|vjSRFG&PFHmWBLBkXrwSWIyPJw z<5T33?s6kNR37gg85}x3$lX}a=-A+~yb4v_)p0O7+cP_PX%43Bf~}_(7NVh%{OQrL z(PERmZK3Jj_Go%$cCv73hOvi7j`p06!dJ~N&P`svFjcV6lSgMSPali~To@tW+chu{ z^&IQ%85uFa4`}qB@PTxF^1CpV%wAZG^10!`u2aL&u@fUh(ecsl?wnTFX8jI!(=W>P z_V*s65ZLnV$$fG++A~1u=s?fO-nO>n+8z}OB3Pjibsrx++0{R$VMlsywIMqMW=}N9 zr`%b6;r#gQ>lx}6{ueJ7rY0{f z7A}oXymV@@urPDaRCMRS)a<#%^HKNca3S9_&~>_Se5fD9j`rk^4dq9p?p)t3J<&Ou z3#W_oQ_(1h>SF!5!DB;UadaRW?Z0Kn@Za4Y=+NEXo;-IX*S*PgUvk}_Tn{AI>yzuj z3Ie|~s$B-hgx zoq~{sk)F}x17n5JF=$H@@ngWgP-$40xG=XcRS?edJtw;Id8Qc7=X=IrifH6yk5)GZ zB^c?}!szLtTwkGgq-(Gz>KYr%^+oyqk>PxFa-e7Ema)F*1f=UReqbO`Uh{PX{0nb| zJI7}h3)6G+h54!R$-8Zl`69A95~Ot`Nb5+D){!8sBSBh6g0zkVX&njDkPpd8cgGD; zepu9QL&QYS(YfixJICjz^7?jsGvNI9`M57=6)I_KMOfYbvc!UcFT_}c^T zX(?@zh$s)!=SI31-*_CM$q$YUAGZN=?Hx<#x}|5VAV5ZXyK+6z=;=|WX)`9CpSs95 z{Xxe|r!HTzj$Hz~L{y_)?wC~h7{qRq{0N@qG#%?7>^XLPEG#;a{B9(_Yiy)vcu@SA z>%9e393LI&5G_RQw!+2nyRKk-TY`o@koufTt$A@99Tu(pxGV1QXMN*p^ z6$!wX79hO0n?@-VhEDY73O%#>$(a6;TciH|u@lkR{#kw`;SPRcqSP`d3ghko;OKF< zS7WM4VQeJOI$^Xt3}zfYI^5HfFAN+zY1KXOC2I(ZyuB!Z%V6&xI?*-IpD+G^g#DZX zeEqV^Qwxh|NRXoLV*zD%@Dn(NvzHfWK>V>Z@WEx(cTG>t>xUvPU6@*&3b>b;6j47m zq80Rwb>+sQ;l9&jBmILNkX4!(D-o8KJ9d0%EaK-+77t2EixO=KUHTB#+;9=2Hw4`t zXa#THy)ZU2@zMfVon5BRHM~)CFi{T6mLH}HhO3K)-N$=J`)>^GgFcP6G! zz?Rs{w2pW*(4^f2Yo6bF=qUa&h4g!{Dz-EmvM1`50P+JB!LjQb9XZuAG<-rF zdgGNM<(APfI(u;>P{&MevBka;G4@B@y(2xP$LmXX2ZI!~jmUIdo-O*8B2N2(Fn6EP ztF2%(#5)cm3(m!H!#yMYEMB)A0q-&%Mh>%&{axK?95a&AC8&&OV03Wgq`U;<;%5u( z@!Zj%#q+t|K^s>RT(oPGGxHJd(*zDe0cPWOMH1mHbkEHNF)6fVmCQvE#U@X=_Mpde z?Lm*{+Jhd?fx<9C(BrxGpvQBl;($dIY|t>^5byR_Z?DAa(&BvK0+<#c`+|y=>FXal ziei@Ia2)^Xh5oRPer@RLKT6dq)-?ttNYk9x2U~EW8*(9IhDKO$Nryw@#OspFGC8v# zwS||HAMG}G!bUO1FKYOJhr|x%67`fz>|idjgSo^G<`O%YOYC4Sv4gq94(2c@s0mO7 z+DaZ+!iMI%X%%fIEoLv0b4SI={;a$$OUN$5oIC8xv8d!O-PG|-Mz01mFKbo^k>IPidRz@7cG zlT&v|C5bh}F{K6Y(1qm*dgfq|v_gSj#G0DNm&0W@{4M8k*^F)g4dM%FmY|bMgs%V( zC3CsTfA`?{EE-V1UKbRgd9OxpW8tZbmlp3X zvB8pYzcfBSezCX+U{;{FaFllhodXLK}0MEX_3KF1v5^d#i!NYSf zIC%^XF7Z$ht9)W^^6kOg+M)uAHz~#jL8ZN6Wu;rDR>*~& zepa|W*q<9A&Qf*quCfCwF{A z00!LQje)tM*%O-wlV^Nxk+wMy!eVa3qHnqu-E=e0J;jWO_$7Y}ZVf(lXhcasrL?W# zv~LjgMnrFyE3?m>(I64;J%RNZe4*kbDPO9icsR2!2DjN8Ads2g|fxqU%ap#{jrN+>A7k6V%GgXIn#PYnss`5eu@Z` z3|Yv6zTmX!g~hplPx7>=%Rtt0JybY5PhzL2AW8-}q&-S%-+aJ`UpOqB9bX9P&z?kp zdJv%eu<|KI8Wdf{5DX`tVou2vBfB}`K|dO&6w`z=i$yk4yQp6Em%^L?TG>mwy1~T zr+Y97O2$sZgX&$-oI!mC1>A!%f_(?&I~Q|4z;0;|3tG+jun=tSa$tH(NhJvnb9EP^ zu93k)Zm^K=%Z-jC5y++Ucat~;BWII5r=~aOIXaH76-`;!nV_`^20=eC2(+%SfUaOm zyF%>N6+*YJ5V>^);JZTH)^$Tj4faIrY$&CwY()D35JM0*a4dH;tT>5sdXgxoCy8=; zk|?Jqu~R+RsbbbusX7#d5+6$A290w=$(vKYM#+_6Ftot^<}ntdP)Ja^T?+cKW~I^t zOSjh>f%b;*qSWAq1f62sMX3>aaApHcshGPZuu!db2~5x(P}m(%*d0*Von$eSBxXQi zcap-qfnUAE^IQsGW@LTITq+HpB*wsiSyf94YqmT~xs%@p#q19#r5~Zv0-u@Fjsw;+ zQd%JBFRls-lx{ngZkMnHDM}4Uca)Npi8(b)nI9J2d1Cy+<*8_-50>iBD|Ku!p&GvNvEHW z4b9nCAi_}60Yf*`bIUO@@cF5;m(LB(A#NnPEu&`S3F~K5$ezOb^NEWZ)}IgS&xiHr z!}{}K{dv}(>|4yTb&Kb$C5X&t^QE6-4T&v)?I@UjA-iO3V{tpha+Ite)*pNoL2oOi zn<&Kh4B7v-w4Ov;^dxF8tga`lt|zRnC#&kP}*Zx5{7goVMte! z_v*r#PJ-%XX`y8(>`Ee%E{s5aY+$Hl{}QH?!w5MosiEyF^Y>Bgs5}Es)jvKE~N+Z0^VucaMDm}&&&Rm>!)m+eJ9H&7WE=r0B; zbSmz~^&TI}6>{20&0EeSKSC>Z=3rgK_u|Yf048cXnwc%kERge(+ChE>hM2g-mL-i_ za$-n(YY+Ak?#9Fn`{eR^*^wPR5p+y`SjOl?*!?qyrdL5xNRmV+kHQoIt+1h`n){OH z{kCOjDol_GL-_0`fjTd@9r#18&GIkHJq=|%bY6q47xPP&ZB{5F)yHo6vQWCDSCZ(1 zpgw_B#I*egBdbNh0S_k0xZGnS#|EO2v0TWAn{i`hqO;7sl$(-*A=TA~?o?2MbcQ15FfR-$&^c5vn(Gefv>bbO3=DwqP%;~L z`CLD6_seD0XdVBb5nTN3`0m~=a({W$ExuY|c(8vomw=rc72MK8%Ta!8us|xWK+cH0 zj$VK-*y0Q0^Yi0(>%aynYe>qjRYr`8htl!Foq!Q^pG*FVa%8vCSz2g@E5hL5pF zl#9ChmD>-<4E?T{!tkph1_#;8<2uY`)ItwPWt5_Z(T6y=5b#de)(d|r>QaN_2|t|V zpwy_S6`fE5Gzd&?Zhk5!njXIdkEX~XlFCAW-ADFp_h>FW#2V*>m?6c7>bcuzO|GFyLEYKlX(bg;|CbNfi=kD zvoZ3V-E-(< zEMZ#4X&*R&Rq7t&7GuKRLwmoBVK2NkJkoyx_luB_eIz!Mj*aG`6ZGxJm!@NGkc3z? zI&>ReS`P8fQ`phpb4#ckAwM1U@6E9jN`2Iu>tbt!$lRLu43SJA)pTnc%|#!ZWi*+r z?^y0wlsjq%D%5B{jYcrSkU-F@{pjVh#&vMT*_jJu98Yp^MbNh$19)Hrval!;mh|dI zXLWRO-i84%pm4_t_Q%@?6rg~YeE$hLga!0QBM0`;oTh;qhFp+ps#ZZVgLhENY#o~I zq#eb{bq)3A6AW{*xiCL>F`TA>myio1$Jl@X=pCR(S2PGZPhv9-w!M^#nFAro5WTE$ z$2hT~cso$CJ)z`a&!9OxOfFh*`oz|j8^-OhqYWg2t^fIZqMmNBXzTCE>3y&3LG(vj&fXR7#-3P(MsovfCb>jhD%W;#45Twd-q1S438BtRw~^`=I*G{cnlH7 zD)I&KO1m(nV=`U0jO~Sa!nK#{81YCzD09MS04wh4K=4P84U34zK|<1THr#uop=0DM zb8UpdCyzqJ%cgXe7M#m<^sSjO}m!ejsLXaOcH>@##MNuSbpS0C>CD2d&SK*hS*pD@L-HK zijExaFVZSu7;r8kB?lLa1mwi4*l4dYMDE5`J8aoHeqrjamb3GhCugVTTT6#6Tf>FR(`sYYN_6*YL3}PQ~@3DNGE(?x1l3H^yp)FX7&( z1)>8Ib@H%lq+gw386hE$Lx!rbvj{Nn>A>EJU`o=d=@3&%nFy6joXlL}JJc9=BLoO2 ztDx_Tf*TDOF{NTmL7tFF9}F3Eo1Tue?N$y4|CZq?I6Xp8lq>>xM+rP~mIKFc(!n1V z!=W4`BHSPns@NMY`<|_Y1%9X^7ovvOhs(hd(b?lUHhddrL?j)|-^;nLW7;haGn*_1 zrJ)&#M8nkFp!NEe2?JfU3NFSLXqOyJqeCrW%0z2{^xVnOUgLT!fS4aOBAwm7pFMfV zczjG7(*qs-qIHqm_9MU8LLI@~zt^-jsap^m1~Rh(c!{KhQH=J|oPdOa!DNq+sahsQ z!A=>9sM@RgeTgL!O+}i4d~d>T6cpJ)!U%jpF9emuR^!lZHX-MPwdy}_ zCX@pQeL-E&3QP(}S3-apdh)WGEL8k#te>a~ z^Z*n)iMrFo2N?@n-gAq{BY?!YL8pLH791con-#&>WD5-*T5}@pXoP0p$31?ANWf4q zI&=^GOCTnr^U?yj+Y5>TOg3oVm2W>jIHp6Z!LF%q31zUdL|LB4rTK~Z!rc7KIVlyk zzvXZVTy~?(KpG-CdSOiB#Nw)Hv$X7Dp{SJLmb;?vvc(xgnPi*F2w3F&GzTJz{)EvC zN27=J7t1RN57GmDCCM&+^AKZbCV_ z8sQQqG5^NYnE3^oW~6t7qrb=(C`4ijr1f{1i(k|XUf{fU#fOY*YXwM4s0<&B;+Di={t zey*!4e`HvoAjOQEI4H}-eYw$8ew;JBC7uy|mT89NO%Dj#5%j?G)E_jm%Y}rMO}GI< zw$jY6I(Hvs8wyh(mCCAFzeEryHSmdnJXk;tM9Unx^Y;`k&2i+Ems@7pGY~Vkv3y<7 zx@cKb)f_^>hA~`k?&x6OZ8(TQ1+o_TDyB!5jHIyEO)^jx&;GI^xT+mRJ-~@~9CJpx zRQP}Fy$g_S*ID1WTldPACHqxl}(u7shEmAF$^_8l}KzL12JUABz93#WfGVngvlVv zB!+QD^ZS3_T6?d(&$-u@EG1;Bw{*|$_1Nq2t#5s=^{usbR?wQ5-2h)Bp{C9)&gMgu z<1FSi91`61H9(#3UAEwloNt@Xq75G2m57}_d`Q18Y!qsE4a}HhZ#miWUojRK%cS1t`!Kv`8hWKtz_>XeV#Dd<1| z*F*s>jMsT=0WQ`q^Vov)yK@cxZ@q>JqCt|i@OG{A!@3-4xrWUIg9(kL#0UL~#oIv4 z^?(Ded(H1wu~w>0Z;|#W;6(n)Cvl=@?XJrd5wa6T8lgsgpGd*>1g3~#fGS`(YX5|k zMZ=@h4wcibpkC2B$tTiVyH^%K-hj(S!AUfQM)>Hel*)6o&WQ%o9|t-%9I&yVbJ_Ow zxZQy1Vlp>&aQ1QZw^#%;!1;@HjP{}&rmf#piwa6LVgfdw@O#npoe-a*A5QZCg_Ut3 zy9foGaCIH9VrEiNHt8Xv1}>o~QbXWaN;>0xM-o+OrfbtHC)%#-yYhU>6~&-U(5M0I z))1wjB@a^xz7Q2s5Gg2IGmcXeR*RPa2*w%?TSNkj{8w5HS2@Ng{ed%b`@85ddgf zy3cH*z5uC%W6l@+8Kk#bQT<@=g0~4o=n_zGkdxt;XtFrpV)9i$(OpFJk&}W^&MDKq zUCW8q4(OehMUuWag(|)ju%WMpJ&2|fmmMpuVFBe?RzXA}>p9PP&h;6F*Yr7Sw`exD z9E|FQ=qPmdmTn-5A+oP`(C2J@QDOP#=^eBc_4csiM|4}^BU~O@s*`ipPW*&Y{+cHtiLQY`a5*5!#urnLrJ^fgX=Tkb~9!kIUZWgr6T z7$b*|i=T_+$n0fkAv?VUDhcqgF*hU`NuFT%$ZkDrjh}TaMNiSF0uMJhb{1@>h|4>c z^&%^Qw$YbTkxpV;aPQ0ioDh-*9u*m!M3y{5(Xms7bJnS%kEe=0p1P2+>Ljaj*z~ED z%Z3&%rr$Y*a%j|H%5*Lvo@5a9o|gG40_3>E2G?$Ha?Yh5%Z1%#w!MJEHwxA;Eh0jI zxwRopNJyhe7F2rPsPtN;Fp$_^&IP=c3$8$g#VxN<8g;N zI*pw?ep-O;bOE~41?Wx}pgWEHQ!M8Q^AIAz*f=C^Q3hy|WN49T&C>cK27p3tdl06$ z9a%}nZe^Kg;-7MME1`BV*u~wz}LwF zpSh4g7zFYOlXWD;hh-QV77b}OOUEJ0T~~yS_L!+yfSZ8cOO_Y%jVV(w7HSNF=q}qG z_%sy=vQg$UxgacH;Qig0k;3nPIG-5Dm|#;tKyt%2eKg(pN zg#tNL#bxHmoAlNsiIQ8Kt8vl>YbfHF2=D}QB28$WmG18XexR0E=cwD(9~U8v)Qlg%RQ~rt~X|Etc_z z#vT)#jh`m8j5=`&8lsV>Y)C7*MiMqCU+)UKT(Qop1+y-AW{Z3!BBhVefkaFZU&Erd z2~0*BC^g6|BDeu#5M^z4yG}WdjxGF>{kPmWf-BgAW$O#ZgNQN7h`0gJjQN^`B{k2eu%c$oUW05e#IePig?Wuv>y%J|7#B(M z{>GNNMJ{}z^&NfWvocmH)j(tv<}=g8km6>cC^C2oANlAw)~VvklDc$CpbFof2rN!Q zvM)qnVR2k_>w!Vv))FZLD^zFE|F{k4N*gH@}soR}J_lK}7 z^kWWR$=cK;StV!&z}IJM^N;sgHpE*ZfHEdECUNbVh3>R2^%vVy@Q=xAmP>48i*eVC zPsXv+aZdQr`B`kS#F;ij-)Z6uG-=RiYocmdsEi)n#$=zfWjG{-os$5)NbhwQ`=ICi z{0t7qL%ynUHbSj=rN1CmI;J-#@S+s90sR?HU&#}~$h5}#&9^f&)4kzC6i3xiCH7Ca znHR){phecfYg2s~fSvRpkpW~xS&glb_d~x{XPZ1c`WhR)%zV^k*N?aKOFgeRq7t0UR zQ3IukCfuCl7!J03#T-LNLo-UVyx+Yv!-m9aA0x0^!Zr|~myY!O0-u6A-hsTHVt`A- zYsk4c|M>jErTKmhpEI1eW78V5tS2P{A+#B!6|ph1@?w?qock&pZs$c6wc9xrv4;39 zD9%YadF~j^Q9ukqYoUXZo+n0x9PdLU*)!HE#_pAMZrIt{+S$grq1t#3n89c6O20K* z>rQj_69)}cvqYe9{LS9Agjh%7aVKOJzO*=2q!^P)=sH+wGgS~Ts>0D~nn{n=r?2in zHRjp7i*upvC@enp!&C<1^U2{xHoD0{G5J^C61?k%wk8yLX`%CYm`SC94-95*vZkHC z>@#<=(gHWT(+SEUU7JRU;YD1ffCJoPrp~VC0cvZY)Xa@!q)c+F#5S~3d%KIS>5!## zN)@C_puK{lUmRf3CUwlFMIIY^+?iy1LpNzO16g6T_!cz#m*8%b(UCXF9;ZPGa-O+D z^a7dbuoX9cWV9}CQOKa?+ZlC&cv6$PF}z4otpV|%fXA#B%9*`00C1iiPZ2IDnhHhW z)^i-{<>E-5Yi5SinffRM{qcIja?~2Nw8WrdzZ$cPun6DN5Np#1kjuqcX!Cp-PmGGT zYAJPbeyqI$s>FAd=1mgi6@jdRLs_e3qfGY~T8IqL+k!jAhR$`T0u43{$!nOKgb7;T zs&!0Xs!Ax%Z-$9g0%%ukaS&2QAfZLQ{#*l&E5VFCIx>P9*~l9ba3T=@YIN*Id1e^w z;4l?}oeuY0ZHj}U@F0I2$;3oeNI0^~MHg6Q4vOQ3-zjI7<-yP(Nj7EqwVFenN2-lD z0wR|td7fQ(VeML#mg!;Yh6K8BR5 zL;h?G2Y6L3DKf*_OtOm$vppJ`7u)I9VEP7SX*cDj0|!ma$;%B+6iaB_02MP_?tqz2 z<5(HVD+mKPTsF&F*X=e60Xsr_sx~)Q8xYEzgR($48BXem5Sqa}J%y&n3YLx^(JW^w^=I^BG<8WM|b*p;G1=CpxOzJ?*oW=2V!!lDAJW2WQP2UO!qb`+3-y^cwR=%stBe5b`S+8 zI{D{?q@<@qCw;k?jE;A9G{|JaqcksvaXIHr z-mhvSQX1cynT4XJc!)EydY!82Vx_rYJEZ6NJc6L$uY=aUu&77r!O`hGyG9Ddm2FpD;5d_|KHt_uWZ3wwC^4!b+^4(KrE@&xaCJP8g<3 z7Mw@8mS->oolgusxk;@$QVChlzqZjE3cZ|W8HQEmlE485wTFC2D#KnPk?g~otuI{8 zTMt1b~hmDFy4M?>iHZE$Jj=Vt1`m@KzCryMS|&8 zrYOurywuRdLaQTV<17;^01L+i$ImoaCB4;puWX62dOU|s0bkYzOwk??cCE6UnwqLm z5Ys3=2AUM@OtCe|7^A^V&!A-kym<^ci5`<9X9S3=d@QTqL^ zBQbTf!r9Z^yHy!;vGXI>HH+OoH~9j`y;4P*zUxdJ5s*I{>$qP}x#N0t;$g?X$ql%=!}c30tA% zj55-g`(B3p`=&Z=ovncGG8Y9)f|h>4)(=&S3ezIAYLH`8qZSHafs}Nsls569EgjCc z5L;P^<*aFID8Fe{I7$XxQtOi>Y5^BX2Ul`>INc3BNaA1yzs6Rb5-xsq`D2Q&bUf=J<4Z5aehESN)JW!q5I`dq_wZEuHT zhdEQBZ>RB7A}LhFik7m_`yyw^w+!xWZ`pwup;fGn3&6B0yat;fzzamR**Q;Sw-Gx5 zmvuTp9I7#MKWWrGLyW~E!-hb`(?fjS)FK>|W^@k(4V=6{{fye8U9j{&O%30W1q0gB+D0oU6HPJNpWeKULxS@80A*Pf>LdtOvc%hi+( zOu0t^tg<-~fS*EBRTwr>2-P^2jfa8=Tjiu_h)GO8?R6Hry?4OOO0g7zQao>k3D-DV zu7rv1r?QXJ0gh=p=1}L73VGVBblSMdO({-aN~7^I$F55&Mr5?Z3X5cbaIW9EJQJG3r4ZHvD_Ig`tu+g6 z8?V3#bIO=Cq$r39az<4oZKCW`{T^i(xrjPnDT`Xh1@l(ta+0w*S8GgIdEHvhI+Juj zF=6d4$~G!nX#$?7{l$xy`Z^mm`I=^o^=otGm@}0gStkXWq6%7ax>AFQ$TH$2*}7ed zAArSa)hNd&?Z5UnUW69LcP&R8svQ8gnptq!;o7$sOCyH+Xf3=IDn6pW)5OpqzVp5&On%dSu+k9NDDO-yhAhSX26K_3kOg`KOA3)h>~fi zJwxb7rM<-{r|q3tknuk-!nAp%gp|;f5>6!@DkYpw5@=O1ciT7N~rXsC!S~S7?b)NKy&E<%}UV9ls)PI(S8FI&xHgwom0kUMO`^whzQzDCf`&Z1Qtvf*UWI zBCrMW(#T+9)wQggsI#c$!V1-=lLQb zsVu*%OMo+w;VPcoY$4NzXggv%8mL6LfOX|M+hz({)iHKI# zhtMOJlgv_CYMWSRSz1FDwBFlIVV|>kp15*kTAZw0dqQ-b%e1a67h$}N)mspZ? zv4t|R1@@wJRS^52>Q*U3NiY)HA^lqBkEBKhpxPZuq!D+A=wOBvq5&VOZ7TXft!FDJ zUFye>;UN7&-p?WFnoLz`lD$=e7N&%vYMWqXHe(X3Nka}b9Vk zmmoouwGmSyqg;U!UqxSr9Zd(ttN;N~=c?0b!A1>)mAyddYADQUniwPs@!3xzWW7j- zXKdau-W|~9tW7DZlQALH2LjHy_K@dAbqp>6yO74rB-OmPNUt8hS-7hl#GT?QW_efQW+*hok@l&M6p?8pnUeW4#o|s z6#Lv@z9H4J0lUZtgfxUc3MuGJ@F|mG>EctfT4XG~cP$(RH7I6x#BgDpTfEb+8#AW| zwUcvsgDRt6BveMfNJzT?`lDYmBf2#aux&G0q+hB-oy)CkZIgqG!|en`*KC59`2i)m z@q@!cftlO8%l$#jDyi#yBEhgSEzeX4bS}x!Pz)q*Ps(J33OS>|;i8=!Ys=zI@Y1KR zZnjHGU}Jp0JHN1i4=zR9y>sktH>E!vN+aH)Tfy2zwLZ>lgU8w{&)k!!z8# zVb-@&+b)#bW}KyrOAAcEiqK+~ALVkAT~?-P#Hq@RBg#wOFCRXkk>x`JsXDpo;(g1l9zNs*A!gfg2oqn5!jCCp|X zbHb7@?j*3FffuSUma(!7TyOK;0YMWh8KmsMlNzv6HH(`(N(h7futaJCS4%kv^^QwF zE4~x&3G@Mq$Xa)jCPBK!=B?CDDY=N7NTDS2xsz*Anh?Palx{z+kP&K-Oq^6fg9;gN zh!jEk88sM65Eny|uXD>Wogl6`PS(meGIvjs{ZGUNB*Fo6z$2#1+ zz}tKV$|o#|7am|@uiycAcfLX#sSrHKD`fF+<#3-}VA1eXo{J_=mGG7#VF)F&6Val*sW4RI^9YMl@1m~wNUfz(Aq8TklN2U@|Ke(cZl+< zFZ@`3PQJ(F$_cA`8*^mKcG!Zg{QXU|q|H~>#!ZVh@aWo$O=1H-Ht&94x2(l>#a16~ z$95Mh|90OZ`>29{h0dX0#*qvw#@Jxg_+Zq;VAQE3YS#-}Nehc{X=yPoEiT5TRLIg~Nm0 z!vlxjkdncOVXebm5A#jvXhjz|T%1_D^G13VerQ=-T#Di&=2Y6draEhsCJk+4wiFQD*tT9<5tKbx44Rp0u8f!$PJu(JWSR_%t>8x} zfg^)cObD@+@d~jx6b{Ty$t~QnIDF!g=qK%hm9y~WSvzv0RH1hdkfgEWW5ZB7#-16P z_neLKjpd~SoesmbCR|^nR*6;^wKDo)AyF$rqE@_^(RvN*96D#It~k{yKnoKPbPl7L z_GK*er7~0@wlY*h`yETD)Ee?uhAPCCVH8WKAW_I$nf4*}e7WZ#_ChH(j!3z0F}B>d z7+dZ|j4k(K{PZxSk9o_zh_U7N#@M0lW#k7D8Sgy2HMza2+rOw|;=&n#>Ev)2R3}}C zE%!D+yn@#;whV(9TZTc5EstdASEUUxw%mpoJ9KVUNOH_ut}QaF^7zKsa&0lTTw9DC z265#2vHnE=bpLF>Jb3Y=@<7Mf3c5ON8XI0hW%xtha>K_%Y`NhvwmeiZwmeiZwhX)& zTkb`SE%zeEmU|InFAPD~u;XZMW(M-rk+>qs%YH@PIucj-6>;lGT;UgSgWE%zeEmU|In%e{!P02?1`FHD z(B9att*mgj^OhkNW6KbWvBP-2gzXd~0~9JPi?QXF#n^HiVr;n$F%}!-0{1+mRgRq+ItfB- zxyqQgj6N~8TxEEj4ih;##TTSN+`EC=B*%h$Xh||5L@nB zETP=D7<)lC-0a}djI}j|e;Asv3p(^SXd@fj_&IN{u;qb^j3nrpy{7b802!E)iuXg5 zB5!IHe?x2;FtN;`fT`kSD4~oXp|h3RVr;p#7(2YSp|b@CNpAjZ7(~o6lwF)1M|>K> zvN$iE9d)(#G?%QpBIGKyByg!km0@>A_j8sqF5>A_jLcEG0j#{x8YNZcj<56!fp-)wTFM}IV zCg5Dq2gyE3*+aT2Bm9tP9mpp$>Z$&j{<*%eJQOIi-jMvLY32R|GYDe>c=$C9kCD*d zj2XWS8Nb6YqA|HhVG^VLGWuvMSlC_Lc320HJIqz8vk7}iUNJTyUB4eLy7%IMZ_mr* z-byzSunCF#!nLu^EiL`}6&cKhOl8C#3;O%{toW88(d=L6YO!K4gLYq-BXso`S7mM< zt`)|LJ6b!umP*}Giet;)fcDHn@6g!!gz_xyZdjMpGhoAL3NKP~7AZdI_`_4p@{yDw z#pGAkp^o(I0T`xGGL1@Y z)2MpW2Z15G%XBxh0S%cdf=9d}TK2jL>I|bEdrdFxdflQe9RI$*7SPe~N469{k9lA$ zn(W?=^xTaVcGQ65AO=@~eV;xU1BiA8T@g3f6W^*E#=`7RZgBFR3v2}*UcYJM>9(pJ zv!nSP!H(F2g>zU1E}?>?Pt%eS)yhI9iv~sdF3#2thKYio1=;zcP0MXDyTG zm=~qOjHp6A&{8WMw5%9`HX$>Z6;rCf6w*reJZOp&98nh|H%4bnXrv{@-a}>?<=GP& zQW?A$%Wjwfiq@R0FZx~P`4UgCoeu?F#l9Cyc1uvX8$mXzbUwsZ#xTTI#xTTI8WLiw zP#R|1jq+IqW}$>(Q?}hiYLUb(qXRD)9eBy;z)MC4UNSoHDz~5l^Xg0~cTIw>gf3qq zgvqJEP^JCt6?%PM9WoMmkdgRBM&h?J^xmsVGXexEt%Xu|u0s1w+Wo1x8U#L{iYZOY z4uLcU(7dx;{0C9ArYc2W8l`@v=9>=%zoMz;L&2{WCCnnsuNEa-qm*67?8Wvg8Y{bu zenn%=F5?;w*V!m6YAf4}ezA9;i1_W@gRsMiYZ$W2w`&NbiRO%*0bWe>umvrmD~NMS zZHf3Sv<_u8T2uXIhm-94a~zGUW#%Nobg^*iu&JO)ntz19q9rWvEOD)}x+?`g$u`e+ zm2iA$cDTQc&a^tVzOlZ;Jj*f5;z+Z@#NmpN$(-7YyURxep~$mhA6lGX+XTA zElxbtImC8&N*u}5L{h@lFf0a7LmOPq)}CbKcGlOK^`O%J+TM+|)v@Bwd|s)b8s}jy zP??>OpCeAg&2VNNGV@9bUYY&4;f$k|bk4TVixT{~PGYegi*#(K8HZbIIkwwH4RW@0 zbgPyg=9(@aayLi~Nm_+Nsx#Bg0aY!cXyD8|r-f&`h6PEkFmXAzIs;P6hwIq}exbLp z(E-LSt`=L`*a|7~@yfQ>ZuYkhS(?aJ_cl1RmphhX-dpRMz%x3DWqoO7ZT@g;nTUhK zz9HM{+U~)14)NPx>2DmY+aKq%o&BXvFOET4+nre5yOH%|Z);9!TN{U8aRxa@mG@`5 z3qZ1Iw{y66?7WU?Eb=zGM9;TorZ|AzPH>F%?yYStf!bUGzkK^(ZQOn*?Dte`_#PWw zm$1hbrLmcb%P6pC^*LU8p)un{uI&my1_sR#j`>q(Vt?sDQ2@>HQ;(Clq&q{pQUI=d zxZK!W+TX{G4B&IbAzfKpBT*7~(= zPEgE;jQp!Hd#uzkfRN=skRw}BQamq{!(?OrfH*b@V{tyt`;5fy^&PIzUR~3qEQ(p^ zO$qI;bFn#C(BI!(E48=i;*0cZ-QQa|DG)$xD$V0azeD-3!eEMKgc0L|)iS_o(=I3X ztsU6d7wLxa*KaZfmTQ}!{Wd2K!9Na!Z4qMYaQr+VU*-g1b`C)QP1YY`=J2r_mZ_odvoTw`v9z%%UX>TA`oZ^nj2*R>nVpl{tGhe2Mrh)5)ECM$0(N#% z0U7WtqAaK9F*UhbNSABr493{@Z7o+8pXB+As@wRQ@2u=><}D9hbj$iXH(3u_?{72q zj`Kz~!b(U1^Bf;jAh}ICwnSY%HM|lVv7(V>l9BeTccnd<^rpVhtrlo(yeNwE>2)M` z5dq8w;=)PjZ(qcw-_lWnTT8bL0i3i{=Lv_NF0HQaC56KMIp@b|qBlNC45hR8&2D(( zZmx(T7^OF`_pfD4t(AU3!76>oCmL?6muOudmf$$SfdKu}+kvWhG-PH)G-*jBL+cGU zaos;C2!5ad{X?$9+qkw3O;XIM36>wAqQ)ykqln#7JAJfGOp2i$_{;j{&P~vPncP2Q zl?;L3;ms(tnF9xM~D- zwy}C^LW8rkYXhtuCK4nhFpyL(IoqC15h_-S@w2Z%7bJ~{<;^kJ(w>-eWoP$xe`{w| zbTH54oy;QIn8@zXSOp0{pAx*-$Z3aV_qm6wX|vlO< zKkRoJZO+ctdgRcz0=IPeK7pkfAM4AwIYuxw>{^!{(}Ji%Hh>K|+UQmA#GKgB{zp$Wr>@ z-jdW7^%1Pe$E1Kbr%Eqzfve!oSZeh>equ|c-irfmg<3z{UZE!@4tdUENLrIMI~|Z~ z+ZH&!`%>-kNjB&fBN2NpHl((sL*SU|>#g3K!Ez^?paGYk_L4GtP=byu&6U_YJWKNo71?tHr_G9U=JXKIsrXY9P@@9W&N8= zPp%#AW*aS_CCF1%l$gul4b>utu=(d8#TJ(mt+Lpk2sdl@AuWgTB(p?Jn{7eJ?A}Hn zx=QbtcbI+w)j6>{==S+cJlwXqh$a#wv)F8jzI2y0UYHL|Nr#gs+}@NAZi&<}r|IBZ zlQo{32YhWG%YKB}QBh&{LS8{jC99+c~%nsymLA2c8y3Qt5=i zTwa*zEN&TM+H8ySVQKZYsDMwBq&@r6U^dw^42cawy303E*&S0g!#9GJfr?>U+eP}% zke_;;1@1l3{aL#2h^bm0pF)O3T+Suv{cO3BQizM@g@aNnzo4Q7Lq^J;Z)$gR0kGx6 z{o9qg?UbyIQlWvqU_L7*4s*m+>%MpHAX|>pE7uv9q8?I4DM2_gBBNXzXg)W4Qb1GV-pq8wH?p9i%+^cKMG` z1RUMgsaFiAStE>iZ0yHq3l_{JP||#cY8o!LHum-pa%>S`3xWu>$!vO?A`L=sY-jt2 z=Dlnx=nEfDV99h63$hFepF@{I?NkGX5+!_2xOz)cJ$EmNxS_O`L7;=b z3oNxpN+3$&j4Q;^$_K&loW0FWZsU#<+IT_^rc8E2%?9++K17$6>pXtA}nwSv68 zpZNw^L&s)oF&--A*U4sz;Z`e7iefg}ZPjdU=RVko6kAK%8|xy|!j3S+R;$5Y)Ma(; zU}*(igGscqN^uwcT1<3^TmHowG;42Zd!MFtWsOW5(VW+XtEDI|vGn^|_SSYWs#9;M zR+Z^bxlP{!vce5(z|KwBKN>Af;9^TZ%=u>1n$?5H;X7y*EVk`(SEJiDQ_OG^T4sZz zmZ@$oA?2h6U0^$v;n>kw+FsmM4U89UpmtFjlUJ?a@X5mCd6Nz;yBY-X+#S|ET*^!) z6|VDHlvh-~;w61yW;(DAaWj<3M}31FM0#d!GOsEhAS$c0-*2ia)y{229Lt)mqt9Fy z!)E=$`aOhcVa~@Z_E7flJHT8DmQB%V)7f{lagWe7+P)m@4h#iMAPVDcZ`AhIq z2W-H77@LMD)e5j(ck=J!SE1YXaRsh^;!Guy8w4lSx=So$Iqqew4RNx8^2HgJE#GYK zY;FoGr5aU=h!@u`cU=RhBpU>(-vB)>+-$ZV=kg53Ek_ml)WefLfyzL2f&8l$J01!G z;8Vov0Qq|h4J55juUaR{MKy{`^q99<82xeqR8Y;{n(55x(D-URmkl*_5C|g}$jzGl ztyLh)%d`xYN02&V8pxc*sLM;sc!O&CMKZP;X+%QCD&UP*O}zwuVaoMMD%L;ff)rdB zhA$UV{m{`%S5v}}1E!^&62kD{KX)59< zSLsaZXF+T3#fRwETqDzHnE!KY4&&*;+J-Hdma>^RpB+R>87w&YJ$C|}335=4hTnaT zxWYV&AJBd1j6N&1+D;&`^2;lQDhL7Oi8X z^fNICkdKZ_;oRCe&vBv3G#jOU zQPKleyP1456C7JYD`^8U$zfWwrwO)t zxV3c~9Fk}jBv-62o!Wetb4fYCC6bL6mk&3yZnHKcIHJ)M75E7yhQt6UkJo?z`@Afh zeqmtkf?X4&OURNFN#x?4z1sj-jS$c;E!s4t>Q>EzS-p-J;wcGc*{-89UikFOx)*Eb z^>d-pByYOJ4! zP*9@s*cL><(@n7QN!JS9K0eFur@9Z2HKJJ~Ac}x=#XQ2Md zsZ;RM0+)yib48ZesYVSp7%CnL*YPm{c6l#Ch(jIuA`-Yb$G6w>^k!2O7{U#@B^*wU zNl@FCex@@P7a_iblY8FOd3e(wmY8mE}JWc z9nfz?#^wNX-rh~5Jy|c1VOpfBwI#a9*OY>sF_YD5U9QTj zb;tEHq0%PGG!@B=s~-uR@4oBqVeK(3NEhQq7jRxpoyu|en@GyFa4%&_KfM4# zapIiLy@xvhpggA$)d?r6vMRx45{&cliZ{LwBy^I2gmx~#i5^!a6-Et*cVi}^Bf6GT zX@_36)sG+!+@U1)r9=lBNyBp_H|7wfF>$~a90S9Lt-!1m9W02E`ySX(7sVvlBWm76 zA;6Lh>q#XaHzsQ-ZhdD8uC`@zpZKN`3#=2&L{W=mY8CCvnzL*W&Kq7}o#uQ=00hez zCI$>8&ZI3U>*1!!hsF1S?-tlM)id|5MxE_VgIb`mD0vw3>G zyvdn&jq7W=5wtOjykMAixLbn&cKzxF2ZK*uS&`6Z`^GT%vU_uBH`6_c;}<~J2-X!e zf_)=KEEu=B(6rucBMnJ+)Y5Jl!_heG;#D#2SY4_j| zf35Wmtt!~K$u!iR>UE}St@sDp09K@+w*l9hgntZxcoBE6%*}C=I&QV?OLNc*gl?1H zAo2*DD6@=_cXAqogT%zewEtdHy~RDB9J^WbSKVI?e>MFz>93HJiv+EWFgNS3geD;F zk&W1JPCqlu12uHOou@WqYE!8*3qs17g+Yu2Y#L-s?PPKXUdH3&Ng2Xq;r1!ODS#++ z8nx~;cV9!SX9}OznTtJ;_F}J>0c?mqGzVLbE2eB8fXUaU15yq!tAQP~rzkF>+ zz64M-E$GJ5!pf%V)ebOiWbQ01;!oOZwAu^yyJ)RaQgPZEYUFG~vxpa!@pVARsU8?J z)kG~c2Ve%)ans+knW)DK&XbLUZ4RAm;`V#7&pP;2ugTpZ+St!fPH_5mz1MUQwgx*?%R6L1?qoa5 ztLsiYviVjWi$&X!++KALHT>1|*QCE%{+jYvu)yZmSU7RzmRSg`CLE^KYu7-lgMdpc zk8y4V4*vR?T|nb(=JOn1(cR53uu*Pbwt$@+l(+mVEo4yUg zmaJ!Kee$T+#DOwGV$c(`hMeQ7SaakK5*pmt=^pc#X)-t^wDgxS70z7puJAqg zPMa>)M3;K~Q;0}N+*Ba=r22QIaK>h;*Tn;VnK$eN$7`puep_$0y}rbPP@EYXQcIz( zra>jtFrWJEMb2(Z`W;G1CXL8U;7?&1Sxg- zVkbhe6QS6NP%PYR=@2KM?Gj0~*0>@1Xfxu1a>T$l=SZ#nqvbHql7?GO4>Ty1rJxP4mItE0giZFbrA?^eB4K!TohwBO$!@pw3%>(_(3`lxl+MsuqMcn&TgfR=}rmxusa2?br-VP_DNmDAy5`J;kgE zh|1lD;m9DY$2EZ(Tx4&*@aqOlZ-9PA3I&zvHJoN%Y6}Ih#^P>gR@nVP{NlzV+q;6k zR>w|iL&kj{QpXVnSDtLkJ)Px$PO3%DpAK)xkJL0c#{j}M^8(wbY7AY6a^bAH>RjHA z@E2SK+$bzg)DLtRw4Cd@6p|_j-1IX)pdQq%T65hhbhA{L2K@yB9~NZlxp|~JHT90N z#OYj^GSLijgLgArmYoH7=0vXNoOfltzrTfDCh*^y3k~+F+tDIOQx&A67iubls(}DX7eo%V*P{2v z>3F9H9ryfzC;Sm~f{rdv(&l;q)x)Txh3%!Sj@A<6ZbJWn8Ee>x+!P`@g9B#%X<@*k z$N;(6J2=Ezgu2(?mog{GZOML@0X<9}DCp(PUJzFZQ0N7`^#a^_0S~(K0Qdv5~aZ%D42p48dt`Z;{arkxE5_oBv1#)LG)l!LC}M`4U~I+ z;2aIeFF#OUmJIY0D*}z6evAxg*K4wz5ULa9hgDi7x<;aJT8>??!Uw`nmr938Eo6`& zWvJZj&gg*p62ZJPOts^XPkS~gd-Z&4tZmq|Nnow5BNUg!=)eXb9oy^6h+0ufp;IWd zM#BA#05GfK^;;)R0Hv2IY?(;UE8FBiM&dWg;YNfc z!tpPOn5upgD3k$f$H@JjgVNC16GnQPPzKVkMJk#jMV>*k^G&GG@P) zWUkxJSPWd>1SOKDN@I#5YC8UbC@dfbwpb-M$NrteJ$4F2aZc2|5h+9XBU1h#>UF?N zn`}6eBJwhXelFCJIt&ylpJA)u(@5KQf8hAybANHeC5nXY6?$m=DinOvR5qP<7XC&64`OY zQdCI_2d#X<=IW|TdvclxsL5*5q%2TpMeaHxv}I0$=u~KjBGA|YG&{xW?A@*_>>rs0 z8GEw11K4uy*d0@bn(D=sj2kUFwJs5kEBM`L6J{8^)Z#!#CC$rT=x=oA_BdujCe8KD z)u=$qZ?R>35j|)rwkOUE0X2=9Z zN3-jVrM(R~|2guJ(2n#W{Gqw0<~XWw1!BknHSiok*^Xq=>^VUnNvTua$hLpNj1Pa9 z6x^vTws3VgxZSt4_NX_>QV8kuoZx8qLo$Moy1!?omiZvcNg$8|Ke__1n?}vnm85Dp z0_QBztvGHQZJWj>MhGh^aJvw#TG+4`SzTjlG0MupN`qM|^pbYmi0fBnNDPtQ0;AT< z4dafHzBd_XVR=IJTC;4gEmj(|qTr)wlr96n32ohTF>w%>Q!gi)}e%}mj7{m zH=C^YX0hhde8?K&nqKOR(LsBKG{iPVO10-T<*(`R{i2D#vNQ$d-gktEus5(F@FUFA z!5RtC5ZyCp)q$yrOg%7L2cu38MxD>c7VjH&9#N^;i-howTC$DH*sJ@k#b@XX?b9oS zCOst9WBs((bcW}e3_9``d@|JQxDkY1@#nIj>I;_TxCtAwa-8f&2ml6~q>WPZB?i)R zl}#QlGLNP#JWHo%P#LgcR|SLI-aa_@BxaaK$ZOFUQ)Qv+0Pf}l$JtpflZJR0smb00 zqcc8+;skd9k@V~99+g#^Cg#n)zLaA)9;ljUQ7Up0?Ytd3xMQbFtdK*ON4kq_|DJEE z%bJ2JK*|{Kk)%60KOR2wEwjetWl02^2b+7gsG_WlQd?@V5nU)f)>UpCL}YBzaH zuHP6NSDtLKHD|DRc0s>9?lv+A;b-F(&436wagij|$n8GTwODwfv(mNrLGhHX#g7(* zb793@`)rUxfq{VJCi_{&DL+>Qs%9oL(LG(E3$+l<^S8}u#sTyk!fR?AF4IH|*OHzL z@BWr!Bt!xdzqPxRuZFg}S5$-9cxl#(pY4+@x;c? zS0^Y#*X&m=h3s=y#G?IPG`D(NtwiEpSf7h#w}41Kamy1fIe?h0EQi;w8xiqYlB_n- zhc5m_j-Yg8XIXMc{DLWsMrG=tzol8B@e50}3?8U*6y}D^`(hc9DojO`l}4TSVJMaw zO%pT|7Iq4=Wcdr!R45phg7qpGuYz?cn683t=|YC!iQXeZD(kicMob+U;!A&Z=TOH( z9dN*atjQ^!O=`J}?m|P6&U$TI=rvK5Bgyd0bA&7jxh~>zQ7|VxVex=WNDSrl812NZ zEIa@#t#HDHWa4ysQCg;DB1>~Zp{?Qk^CEB>CLn9Z zy!vPBQXbk1iJ>QuD`6eI9`Z z5&npa%;m|D1>xA`g6Pp8T|_WuT}uZ`noTkmgj68WR~n(eX9I1hu2j*|ZdZk*%E}O1c;#}1>6TO zVdt$kS)kLe`*RwiL|dHuoW=oL3c{)_M71T%82yzNM$sH92;S72>IlDV`Z?tAmE2_) zl*6JFuCQ%u{mK!LrKP%@q(zXj(a}NF~+7v~o_%`kJpHVZRUfg$ia^o6n-c zx*|1=G_(*cXd4@1S=>X$h8Eh!h8Eh!h8Eh!h8Eh!h8Eh!h8Eh!h8Eg|Qf>ZY{S|W{ z8zOoH`N;JlrzEjAj{O-zBQA0E$Wi1U@1E1Pwb!=^UgCheS=^1Vg4kyHS?&GM0d1bF zSZ;e~Nx8AunZb34eVe3a+#bAr$RTj@9%J|J!OpGo+2QsE+qcVs&>Z5JM-C=1@pWwzl`#xjwnTzED+7GqPoEf3{=CwAXbk{h&Eho0?x> zrv)NzF&gdZD_zul=4%nBEx4VFoS=u6Sj0}xaOLf49DtWcNRJy&{oEB@3!GHQhQe8z z2D_iv=~WF*zbZ9-ZieO8B)?W;lOVTJPvO-WU@ZI)F-miA*mB=C@t1%Mc?$zhU;XSc zKbUjTka1>Jo&ZTb(~Bq$1(@`Z1NEV>wK&yQzFv)XX4T-Omb z+JK%U<%7lw*~V(vOPi!G&IcHx1V#%+pVLW9NL#zbC8Mp{r8&+=%o9tv=xdJV_ki?@ zhlO@vv5#rF$RBQAj%RfG#*B5ey#DofVp7+>Fj-Ms^@i4<+U(fuXd`D$zUe5ao#vHn zkD~WD#Ak1BhaHPj75i`>>=A&xH8-hEq14#wvQ5X#A$+5cCmSj%&oA-X_+DHp6xwO19EZtfxDK+`S*J3DsIhca3vOp*|$ zIk3ouc3orR9N@QOS_yJIEho2f$g3F%rr)XA7EXOlFlq~w${WQ|wm9$62cTizbp3vF zt}fWk%+H|R1)rHPdiiJOk0|IkKl~ag8XGxpL$*$`H+E~~@MPHRb8C; zU~lp#o#lDPVZdDk`gF!x!2c!!PULaNBJ)YfMqLI!a;v}FN1{+ZJ>WSe@CBV@(6`HUVZzOC6C~vzI2VsorxP@?k+k{YIDq&9sbq+^`_@iMtT6 zA?L{E;HG1FE1F>+L!e%Uua_o;y&QKDxrqe(BE)ns?4ku#!VG=zBqw^dBV61H=9Sk- zzXM68Uos&GC-_s|HO|=@#?qPTS&iMSDfUle|) z4`dRz%BI0p|5dD zL)K!K)buPR#O=-n>2I{g<{Gmoxwx9Pj6Jt8hIX^=e9Ove&*{~8yv+u0F8hORYf9l( zNT=&l%{eQ3mMkr!U-XTd2u@<4M*VAzH6~dtq(!HQtkEBd*n`1L!R(E%V~F~CthKpl#E^6)W> z=hZ`qpoU?GziMJZ$By2&Q5nNfh)!*Pqm*i(P)hY;5`5>$#eGiXIk~jCcI(mQy~EY* zwY`(gofVEW=M>?SQyT}fadt#(m!U-1#Z{n3haLfY4gMTc z3{2Pf0T?#Os=fH|PSR2SggA3JO>t5MtA13YtU52oCW4`-AjlE{R$&(P+K3tsWeQ^P zsWsC=xkSOpx~(p`E~B4vi`znnF)SKY(^(<*u~1nBsa>=&&aiyDCewwJQm}r2(zLas zk~L8k#z;@qkfu4+BQd_~OR*7qDO^5c*3U@{2^t<2=cj9(b~nsw%VKl1HEuJR2`j`G zYG}O)9tgO4mpb^P(Y=@y&OInKGwg^FOjYXT=4EQh2P*DW=FmRy9VIt`v{s?%f%4nL z=kvDuXT5ApVhN%1)&X7<9um?K64LR)5~7y~FfZ;dv11VEFsiqHft<}HjWwmmR{5DN z`)DhEtcgB1I>C!Q(hasxu|c#eC@?s?!KMh%=WM`O+ZDyoaI=evUndMc(WnNchdss% zb6qU7vC4c~r~u)2B&c{6U1VPMQQ=eSKx=1FRbz(Z#0=s+{`^jqBBGIxbXqE3G|NK_ zYXI|xCro$@4fZD#dXB=ZP{U-AcCs}aoa)4n_JbQ-(4oSNFHtBPmK>(@Q8B@+Q{X!9GL|@*&cu_9CE#u%R%O4Z zvKscKyxi@bgN=0#Pn>20Oua)N=Oo(I8*Pv$XCWP>wBxKUY*2y(K=@OP)p(M-5>ED&1bzj;Pqx#C_w;7>W#TXDIi!X>G}OzPha# zx6)|kUE5r`&0)73+;)HfE!$*V1&L1X_&Vf^DU-9cE84>W8=UH&XGarQ=(h3vRyaY} zqXKY?fa(aI9yhlZY==ry^^28xd=#){Q*18wuJjw`dSuq$&g9fgS4K4!y5y#U=xTP~ zJGPI@e$_tpNy~%f)z01I1e>DCrhF74_90iW+`fAyr>vH12mAYbmQf2ls6uU~1P9IZ z8Z4ugw)GCC`Eu1AdogiZ-4H;v?wZ-LLmGKedjL?Xdl=k`saTTZT4w3Ow z0$=#FIy1$e?*6%-gdUQz>&MG4DDWIX%jYxcg?~+5gJ-BH4Gn-b242v z3#*g0M%MK;gtBm(gu!QM@dn_yD>H>D`=WuVZZd!>?Pcpa;5V%F>YSh8SB0eyHw~8f z+L-0xjJkUYdUki9O&H9t9juCKL>B{OilGgRAR51*{wqtBL67y(DsctrWjkA|+*uH| zy2a~a?_R6{9`Y5~=pEU~DbEPfX>!=1fli{RF7ajxr#{`aClfZ3%2Ho!=@hNj0?qHY z7rSyTSA4^VPt%!;HOyxwmu{qBI2Poh4~XD{zO@C9lBfqkK3oMBGT2@_SXyOe?XFE4 zH)-OoS!~RdqYD1vc^>>-1Q;0(m&W;*$)@d zM-C2#*?mI*MI9d`J$J8k{Hu#LHblFyi8f2BPT?@mI7&dlXQPIR`bVQgYnSsmxN-*xyVY=pf{L29{c{&ABG z90HL=Gp<4~(S^Hy>oc{{_|DOXr{)*mIyye_=)|LJN;;Qi+0xq5@er$)Z%*h3@VJn}6gZyNcw<8K~$bmX<hW-A5Ow=I#v!h3BQqa{nK-q@MYe$ z6Zbu%9>l(Vg7~(@7k!IuSA`GL+4_lx-+lixuX)dX?|t?AUiIv~??3*7$3CDkA`BkB zH_Ps)j2J#m_)ST;P542=vCbz5pRhXbdpG4YKMOG8x7(zp{oEt0??(Bj=LZS@H1GO} z(P!>^&#T}2s`uUd?D6*>`$4s5R2g`hugbDb-sE}reb2o5J+FH2z3)5z?6LPNPwd+# z$n$y2bN9YI`|9%eeu}XA65IP}!h&%O^XFa1v6}w*N_oFi34fU|P0eAK-IrzWB3wW5 z;4{bHbL_q8IJ}FrVK@|V;QL8`Gv7uWi18mG{$Y>Tc;tQgCE`bkkK^_`gayCaiQ~_V z%zauzXydH+YhUAYrgq{X$MTE!pLlKUfjs@OJEX@p9FYDM%86|g{^;2Sv7X}{;&0sl zS?XoxM0k%eiPZL3&Sk>-mi(o@91x$5+cP0NN?tubO!y(g^+CLf{r@x%`1_7M3oIAzKk-m$o_~pa0$eQfIDs6dvt^h*OxllHeGk3+RnOe} zp5yO5_CAfzC~%O3*)HNQ$1#a@ew_54r5AO^@yXthWsiE=Um5A0IQ};N)-y)@=5gWm zTLvjj?ZoswpSu6VTat1A@Sk!z5x@Tk;pdnuL%*+|cG-G5m~UcK~`l zX88(!FiKd@r%3x4?;5l>$Hsf=_n&xU?Sb=_BgLjel-2NC*pUpuOA}) zF{>|cYd&V5rXSx$TCC&qfl*IPmIfF`(Ro1?*ZZC1h>+<2o=ISGhjZW|E z>8ne7TaR!d;MyaS&8{9?$7}HFjq{IeJ*qt@-?6@XRVw>cRKd-SBm8;e+}5LAD+tFJ>OWlBI~Zuj z#`enQAxEC?;jA*z-&=b0`rsGTarN5DN~HrXZeEQA$T<#A7oCSk84A$^{2*4ioL7g! z5$O()A$3)zVg7!ROMkTGBnPU@bo*!geX_x|uP0|p-O!Txi!WLZIl9?JXB_4ZI|i4N zx>d;j!p5|sYi3urIG&dy2G6x>XXnn;r}^8i$8g!5(Eh`LK=Equ7rKfo%GJFkdkLuk>(!O5{f+&retdtPFOCAYH*s98 z*Uy&dM;NwOq77;y){qxFcz1@dZjqs(21AXW(8W61_a3}REKx;16q=H@v|NUNzO;PR zmzKfpJDtk>Qab6Q0ZKG~U^pX}DU zC%d-S;Uq>u?dD?|yvY81UDXE9KAflmI~FCH2y<_=zy0#vCM zGnl-bwLnf!$^!VZHJbwQ?a~z*d;5;B3OTX_mie;PCE`~Fk#pNucpR>=Z4(D$aM$NT z5%!6@@e=6Zi^Df+fI+|992Z=J37_3MV{>zDQ!Mor9jyX{RBbM^uXK&WXzDABEqgn@ zd(9THUe3uY{O1tA9lNFPWg91vgy`Y&vaex!WAj!6jo5)e9AfY#;ej)jlj}=c8=JQ& z8`;#RqI8U}t{Pk=i?gDyr*h+E`zH@{pWE)Hu0OL0h1Mat??sLhBm5FRv5U^>zUu7n z-jJ01;_E%ByCwaCN$GNwVKS@S#aS+WX+=64DBZ*U5*p?*XL_$Ltx0bBdP%*_?+kk> zph{Wx!lgf>dL1*1 zJAVY@>#>Z5LVskQC0!PHdt^2x%whr0r|)&s{xL1A@q954W8~!d=?}zotqKtSTQMx_ zJmJ3=!?LQ{V+9?{Sm@F7QSZnxTlHa$EDy8zQc8c&!#^7HvmlZ@$8060h&YygV-eu5 zW4X20qmN}Qh$PRk>_1CF%KuH3aI}hh^s($uSJJ<^68@G-I9lC3`gry{>*_q%zx^4p z5gH+U+M-9S1#e5zRl|dfw;(aXf0(1QQQ-d}3%|wyqqTT{Mr=*~3}HT@8ZYmOBwh7u zecqputj-^6gteX%^FN!UE5Fw7{Ta#L&L4k`aN6FVP12QL>-+wUWJ~<<8N#uArEA^Z zpAlO-e4en@hE)I4ywmVsuY~_jCHzyB@c&W?|FcT?|Ez@nZ6&Ps$&bLFk?cMq{*ds) zL`3+!F`s55*`KSV>wEbf_%o8t67j8s)9=qG>C2>Rz6n#PE!!ddu^-Gv1&@);$5(y} z{)}WlK>8$Mtz*RY^pbRv&95Qm{{RtJNWYxq|FIeB>Oeg8AzdroFH^M!9J zPyP`8jAXw^#3u>2iHP-oDM?rUNOn}>ZxJy8V|!+k^p953f4&k{dGg)x zXC(Vg(%(*4^D~xrHAxpPuO|J|_wx1dXC(W7Nnaw&vbBA$boqPuGm?EHu-zdX=ZDhe z{}Iz4CVii8OhF){sF>2O+-wWFGx&(ob*Y;n;~5k@Z(9k%9CG+KO=@q zpCtTwB4U4^akfE>*DwDNe@3!(%6~uMIR91t$CC7?NPh_Us2<_py9vKBf!ALp{6+9V z{fqb@e-nR3vJaE~lY~?FKbNEnSHJZBY*h0l&L{b&#P5HW^v@7Z=hNqs^nXnHhnSz< zzT=cZ-;?xzM*0^Br}h6S(f{u`v%D(UjWiQoS& z>4${BLPTueri($uIDF-we;t1qKj!K<;fINc`Flya z+ADt^e@3!L$$y1#O3!wa^gmDfDEO!Gjrb?OpZI;9^h3fCe^tKxfMWVG>F-I>g-;($ z(tm*TFEd|9iI3&WZ^)mK>{-(P24VRT#r}NwwMF{hA$^qZ|2$Fgd-)XkGm`xT=|4eu zmx%cNLqUv;@ROfW%>TcV|62*C^y&AKboEdEMlt`F$^VChQ~E3aqnQ2;OtgCmzlDfc z|67uDl_#Ghe@3#mk^ilPf0PL2SGs(X{29rnNdG5B|4%B&_jkYq0GZ$==8JZ%XK`^2?XWpONgZlK#Df z+eF0je=JG=ang6eug6Hw$1h3$Dbjy}a4-4(D@nTQlmC-HBiU!kKSKCXA|m|c2NlzQ zoAhzQ@{5Y?xlhE~o{{X|lm2BshD;jtRsNfjbi?0V4e;@i-;_Ti*{h+gf15DH=k?2v zDyF}Q^p6r2kBRkvTdqcUd5~%9GEUaxW16g-6tO53dsb1IAAkY5cYce~|pDQu)81@Fz&G zS=i;#pH9kGeQo@|{PFh4k1U4Y$M;Kwr-_L0`cRUt{>i`0pONfG$e)IlE`PI_{^O+o zB;mIa5zG60lCJ#nNAqVS`x)~8CSm!f#r(g8-&aikr=))v{w{heZR|G)UuQl%W?}Cy ze~$8x=XmyikWNwNt9B1z>wl82`kAYv%B}ogA^#P^O+qpM4=3r$|KTKjKfLd6SMq;8 zNmu?aCgD-?|0ZF|%*)@+-636Gk)NACBiTvvKOg+wB0QS-b;Wd*FMl@=AJ6^*`40&{ zMnr7?$CGsBmk%5-p5s}U{69(fV}xRU{Jln%s&wU-Kb$`!*){Ud1^>9%o}W$9m0vz^ zp8t4uNdE67+#@2E|M4VU`9G0_KS2IZR`P#2N&gAbZ!rEMNg98BFW)&{Jjb(NB>i5( zV}xRTV@bO5%cqVP&++WvkpB$fRYEcU2a|N=myaDUp5vKhn;#+k7$N0Xy8P_?8Ogqx z^v@9fE+Qg)elJNsMf#f){w~?&Q{b=gP4ju4FgP-rJ?-Jkgug(2Z7a|5_f7cC5#;gu z<-cb^!cUU_t%R==5&QFBC+TW$%&i*!68T3)p$QO}*xv6W>`$<7ytxSLd-?Tw%<=4R z^8H^UoVM@tNxJfXF$w>VW$1oClO?DjF?N>B1 zXC(V}@_&x}Vo}OHP8gXf$H(s?{6xZ^rwD%!Vf9PxnWumEkaP#q9bcW^{ZfM8ZzWw} zO_>q?(|q~;B>f!e3Nyv?^ikv^e@3zv=?cgBukWKhJj)))dZb&}=GOyOzW9xQ@9p^r z`mBdvW9bl=av1uari3@$!}@c> zmi^Ado?rGue>}hJiyrp$xV|8$30|VV{&@Zv62z4*dyvQZ_p%qIVd*bvSoG7w4qxe) zX}aiV8W#Ob!=kroSoXU#EP2txUcThTH2q_hu=s~R-XHN74|{(^|NZfF@ox`%y7-Ad zo-Tdc!=5hw zk1^ifqwtG^N6a1JIsJ(kpKd+ICxay`9Hm}{QXh*>w`xXz90B6 z%Hn(q_oPHF3aqy_Z^9%Lz_ebHc4<1$czW#Q(yrXa#9#wd)zO$Tu6h4B7 z9YK@b=|9~?IFsq*#g3vVpr%Tf3U9_jo!!iWEV;X`%)KR#aW-%iisk zeE+QWmwVXv13z5ZAFcCz{PFxck0%Z5yrML$^X5E!JkwcNoG-|ha6jKdo(!Bnn5U~f zy(Ijzq84e$FS%zyEdebN*nde9kA#)0KZU3F`>gjY|IONxJfHCgE=;e+_tf z`?bTK^A;-bYbN13`DZHmr;~J*KbwTVm;7(9I6P|4y${Ba*EdQy`g5zkMkT#l32!Kzm;d|=-|y+yRqBJ; ztF!-xa9od2c{+Q|8gJ>(zwmQ}qd%F_f0b}tk5c%z3I8Gc@qdr}8sFa|%%kHp48Hg1 zY_+EqQuuiGdcx^=eMcpHTKPG$L_g~PBw;%o$-*Pq_Y#i#RaE~C<2$N%{k z{w(2m-p_-a_fsbv`Kj=+XZa((-J4w_{Ps8d-HpQMLr+(shL6v9cr}JUQc54mK2-`o z|H98#!vDL6ZI-CNe?T~G|7-HI0KL9%CLGT@7d}5s_~{%Uo`2ylRPtX^_~QjUmkB=? zDo}mj>h+Jt_CG~>lt%=Q@2`~ig9_*Moyh+CQu;{tNy6!T{w2Z%|9DOIxl(@4w<8?= zy@d~d?CAl&o`2y)ezu|a|4o(fcX&9^^VenHML6!SQh9GR`f1&>@tXJiIX)dKoX_vq zXMb1Wr}@Vt`20{Q|MM?=)WdoD&y>QPS4}wj-?PB`vQRQUG@$Mp?`zd|^kr=jp0 z#DK%2`X5m^hxdcoXLazZNjKiUNzw~^c>aa&^Y8Qi9eDT&eI@?&eh({X{rejVC-m}1 z37^mFdwupZmHhvN@Er90V|=Fh@HtB_=;y!j{Q3BO<3m|#zK#=4@pXo9eAM6X^KedI z{<4Sj`SG_Z>7Oixk7vI?_%RB68XT8A^6Q>%RXm6=`P&Mgx1hn}{~}z#?}6;ggbVz? zFMBogx}e|pWp5PyPUg?sO7#4A_Lzr9RfEx!Qu^~R>{i0>u7v+?CH!+94*3223!f#N z&adAkoYKSlk}Cp4AHIq3b9s9?|IO2%i0wP);T&HUO5Z>K!uJr4{z1aeeZtY+sPMCd z)A~P7IIg!V{T~r7_~8TDuMv*xVM_nkgbVuoy6npqR-EAXy6jbc_Gjq->#~PDJnHH9 zWdFH`pYZU#*4-iXrgxA{Aor~erX`-E11$32|OOW*C`JpXbjd^|fK zoWlRF|9_2L&5tWb5pO|W!U=KWN+RW$7=NtSHirG1~yp!j~D$Ax{wo0(AP+8afQ%rIkax)AXqO(B zP_9x;mqDHi(V(aTyB_3w3{|k3pKsPV;8Lw4?>Zlzq9;;$^;8~tm-2Y&r#A!iRaPUG zrnV%VpvzaSF1`$-A-o54wOdhV;=ytgKEK+cuagpU-49d7iF#2*5f|sIN5P_uLh3wTTp(TGO;MUaS}HaI;lwVOlE55K$W- z(#0;@+;FpF2AgSyUpSr#q|H^ifLx`&d*9CQp1Y+aN<;r;P3pguU;q75c>wsN9*v06+ zSn$aDGEyaKyL^y{Hgf%4YPr)9jYv^RvV*y7qz}9w%m$~mgRV&gh>P7y<eJ_3vB2uQfWx)DWugP)B9UuZnZ@!jpPzFGVzzBYhIM1tl}SBN{{^{5sS!U2n(dU zHfE?kG7Lm|2ehUCAeWoX)`Wn!iL*ODQA3&#)F6;`Thio;8wa9&v_MtgF0^;q)@~BT zn^FKILd56LGy@4|M7l%TK_)JsI%mY_Obeqzj~qk!8c3Qd8Bp0Pmgr*wSyb@4Bzn-H zmM=r0MQX-w8x*tx>Z(^lUSG?J+EmiKp3?hM;g&blT-h;Afj}v8=g0^@M4E;+!k87} z5RVNp&5o9V1+(6SxYv@(^=<{8G$Q$?z!cmQ>M8aM{PlC0-uVu3&}4l%85nGHz;VHV z^>bbLVW^P(?@)I(cbw?+DU;%BCgdumuvjFuhS=_w@PfNVl-<;tSaqWyHWn8xu*)L^ zI>kc;80;3ysF*^pPDx#ZH*s1ArX5B*AH+F-i!7)@cke)h z8tz&RBB?9~2CLIW?}Ab7UpheVeWoL2v^ENh!T|9Te@^LD@&KG0l8ESsO8vI zQifgGo{E(GaCkNiSFMlCae!JOg3KiTB!2Eda~w+HOK=ZlgOysrQPJygxd=k(zm0LY zeW-0H7ovQ=oo2fLvl4E*$l%8bQXbJO0oc<3(wm{5`dZOZO6Dg6ebT5-96x!SZ&Xo> z6HGDl@<`i*hrrhPB4;q)!p8ibRZi~QGg~ClJ(K#J_n4ZS=8I*g2*)GjX(%pxUrsJ( zWuj%i-vHJQ!h1VrDuymm_usmt5U)wes&> zS_|qxU-P40(CQt=RswB+kZK-3<4W5rs$HkrxsdH-Z2Tn6g$a(XS# zMi(cuQ!(t%`tta!@10tRL;*063vVF3S${gS6f4T$99dOaeZR`Q6K{5PRE5eO-J1x4NpQH{Yi$i3&Iaew6Vv{=yzu1F)$#ENAqDc^ zvyyVMGmoV985Ax7O$YUE+-}vo0xMa8a&mkOZxUDDsLI}jCn^kEl~oL1hvB)kGYE9l z!C|Kv1z6aoFl$Z9;WT+ zSeMnKq2zRBS92YQ-C%Svboa4h;DpJiI^F-5)Gu$)KOG@3Pd2E}+BpxRxKsCI1fY(n z6y=m$-y4zzJPe{NT$N*^Y#U8)%w}V!tEx5kMdAq6+~rCWjWu5(oz+sPxm&NdyR9Zg z3?+!O#R^A5s2q{57m)Mrkq`S&6LjpL!dL~Zwhz3r_R66^N};_fEW>>~3KF7egG&1o z>6%&CZ9ygWyS)R|ZdRx~%079(RdzGMY+CQua1V9Z>GjCFbjUCzj9?GPQK~M{u-QlJ zrpSp9L;Jt6Kt)PJ9aSy2u-1p$cexe?s?mz;vCx5O(h4|YFQ`cVD2e2flePF182h-g zpr;SxmzrsKCX2~LNI=pQE?FwkWxUcbQIW^%7iJq!b{(&oNu95`c<9utrJVAGguV0| z59MGo9N8RGE;h8FP^+sj&Ak*lSSQo*$(XojVr5q|CCJU_4NL8EI(ct2m{AS5nj%x- zcI&K9*?T(jM$_vNWkRSM0FMqZv(2`TdrMYWMF(1S$V^-sw9n>tHbxs@r75b?Lt(^_ zA91x>IFR!tmF+2~g9VNZ?8dl6vd9s9WMZuVOaZHRbx}0L-T)$un!R4H;rBYFa@R0U zYYk)58j&@&BFaO0I6vk`tq~mwk=_;?3eEVi7k27&Xe%dxC(jSqxFRiNEwNP3Gg%(T zd7-iF(E&kg2p%61BkfKUH`^U%jUS%@RDQdCh$}3io5I&Req9B1zr$A&305|N)DHcq z6CEBt5`im#@uz*cixdIhLHpY(C^g4#wOSpdam31b6oQmiwURF|J8oTr&RONmL>>Fd@f^;5LaziL3* zu-$6bdktm+ao5RjItF-A8viJBA01Dk!Cf&WLi;6A6Cd+_?spA?~VP&&v3Q=^t{IB zR8gbrG^n(k@@jkyTAQzTwRBE*DygWIS-qIxxw1bjgYlqk!P-EghI53d@y#8WLAJ#2 z46D_HsNttWbGON~^tGp`ZMJ;nk2{`>uC{Sw^$126b5*?cV-O$_{cek+YrL`F{UAv2 z%ZHi4Gs|+3W;v#x`0KgKhsk(fs67Lm1x20#IKymBG_fc`Z)1d`2t!D zuSxi)^#ALB=+y&y)q{GE@ds};*mwD8%s=Ae?;H3ByzPhhOY>*%>N)e8h~OXpF^AV2 zcs~Pw{ht8<&d1^(0Y={q-Pgq>zeAH_TDqqOkJr&VIB>ku#}K{(kZ{cYH&r|X=N|G7 z-u5ZHpJ6ZJf&ME6dbj6qO82kEkUv)5UtwhN=$#+J`}F4q34bi!ZyY>&w~g@dazp;H z^8VJv`~A~+9|OEsxFkO1bCcwKiw8nhw-mhUJ-pfv4zt6vGXNx)dzxj9Z zKL7X?k-lRW6?1P?@P7K)E28_}W4uNM@1wV#iFe5<%*Wd8-3s2P-+m_kjy|3CV|lu) z;Qg`pOnmeci&gOVV}n;WQ@!6k6VJY7chPt>npg1NK{IRTbzRm4;i2Cy`SR9Mx&)qi zrHw&^L!S@KetLvHpTHYBa#)T3+TdCKKKbjb;yccJs;>;C|UjTkrp literal 483328 zcmeFa33OD&_Agv@PS5EiodF0PhE6v_CZI_`P*9pqXdn$H3=ZIw0W<-WmO+Agr9(i2 zpn{;6Au2M7T&4t~qJ|)Fy^6z46VNcIL4=0Hp+f?FNFe=w`*fn-`@ipf-?!ddZ+-7A zqPu$k_TIItYFC{)Rdr4`i$;xeaL!rBpTOc7p@+cGm-o#6h!}`&w>7Jn1Z6g5|RIo{DYt$ z1RYUFxqsHPT-a_xeo!@7qCe}~%QWHB1Ql!E%9x5610}cqZbjf$1a3v(Rs?QE;8p}~ zMc`HhZbjf$1a3v(Rs?QE;Qy`&eDF7BqP_kok+DYMztW#u+o2~J@e{CNzcYfdcRMkb z1AaDWE@%Ph8PJrTjNRTQl4NCHlt=g$@sR4%TD4Pb z5TZiTS4)M~*s>w1tRaoLMrT`Hqgho9&T34{naNtA8@JJJa9Dg?p{NqALW(~9ZM(vA zMx9<2QYgBtl>;T=fllsbFRNmP2%82z4~eU_q%U) zj@9Y@WE*;h$4!-O*V%+dlc<2T#Zc9h`ASvO>{nc)sXmlvXob=d@UIUj9Imo>aNh+i zC8AFh(|m$xaSIlUyYkXdTfqNO)zC_I&^4M{)ES#3#lUjVhH{qF;^CG}5*sLFtj>c^KM$6(2jg>ur!%ZBo|A(2Z= z4VJhB{;dDzuis@UQ{iBJGkrW{ty^`r;njfV7 zD>Li=q07s^T@sSS1|45kvdZ4YGfC1}Ls~S~MBfLK_BFZ}T`PZ0`e;z3C)KX?a8tm) zBtSSdZ7I@#e?mah$Tc4{is7d{e8?7Ws{L9uSv@IRS?X0{z4y`l#pSAo!|;Evl#;E} zb#8W#_`E!`UWn9H-xqU_)c4TrCd0T<`0Uf{9!{US^ih&In_FM?Qmi!;^H7bAX*4zk z;{IEc=r#mk z`Ko~554s9!0yS3Y(qBakGwW@P*Dkj6Gm*wu%MA|K=zf=dqkB3+mW^Asp?pjEtBw~- zHrsEjI@(}Yc8~ofW>@(Rdyyl|p*+6YuB++fC^c>=A6LZs4XIvlSJiGXZYXc@LK;KT zP4@8Uan{5GCQROAy3tLcTwKv(Z-I3rp<)yw&cbxPF0vJze zG2_&Z3nhaOa8qyBbk|nb1sD3ic(3&E%Ki?mZ;^KVsQ9Y89S@h~J$(W-i}LaCk&aXc zYm62`s{{U`z}=&UR%JG`w5<&)B|NjCRnIKB;6Cf!n;!6ga`Pzi{Nkl~h{mqol6tqo zA-3|oeUi!@>iD3Mg?IG~EaQzsgh5iIb&8_(gsLvnS7)h_e0SEW*-3U#Z)O&5nvqr( zvv0D~wcPau)$f(%xc1z+!qSb>H0xez*4~~i%UdlkiN0|04SS0x@1+fj8z*Z=jdsLW zJ>vLlS*A~~)wU|Hs~WW815e*8X*W_kCOC#UOb$h3j1Y~MbPGH(YPj5zyrs-yS!#O8 z;0tH19=%0uRX)1CL9N+_Iv?_Wh<4p`(*YkB<#wr^v4zEU)hU&eHP~2eK4wqM!O>Ni zX~xL&Fve9h=u&^izQ`BGhUD9f?04*bu+W^ zN!RFJxON$^(M@BJRmm9F4#s3)`9fC(Pa5p`Vxf?f;$fB;$4iAP7V>0MwX-lT$?WOm ze6i5zDwC8}TaxNjM@-MiG1Xe#YBw;kF*{AXnv-@!a>p67HI>|~8k?qNzMgEc&6GM)vY7t3 zXVCq^uwTnrV|M!I<%+90=}ROQC5|15>-Zr_;SBh{tlFqzrXdwaW-1&y$K#IWWvefV zY$?d-GS7-}OwHajbLHssGh@qMgRB@N?zL7XIezmFsVM$0dCtu=KG`)p#*vFWoBu-| z1LgwwpnF7p;#Ko6dqHYv0&AlfXU}wImbAICtmkl^=2(xS1@%($z1@RX^! zKIH3fC@Py6=b6LJ#gf%@43d6^h%)#y3@l@DU2}O{u{6Li*|Pgj9w^rzUW^6bVO>Bm zrnXPI*^k=Hgo2u*B2@h1&?T6?{bY+C*JTF3nP7saDA1=tTH!yX>4mM#6q5=@`z(YN@8(k zo)0ifh+9)>f==XV^=^Z$d5O#B%oLRCX`R42!3 zsjtcHIIdpi$gHn6YEE`sO~I>>neM@;=xZA4u=}`B3@#PX9fGz`YSkZL2iv?fKPFda zHZRGuEU~QEpt^A~**W#;H{7$Em@swDcW&0tR((WbEB8y;))XZ{harJd= zRW;~DDuZ%R2|<3b%)js5BAMKl6;VEu(2DtD3OwgFF+K&Jx0aD#ZW-#>0^b3Da|<`o zon*f>+1gcg?4$|a>u&t&We1OWnOWsDx~96;yH2~5mJ5hC&0{9SB`=pUE2U5$D%S4N!Zlk@mh9zCE7A($eS}z6rp=l)diE43x+Y#zeR}XMgk%Fkg>{s)$?Zl+$VTy+9)69yucu4NpuuAY>uxkv$TN! ztpHy?Xy&U2I{7phD}qH~*{;67>P%O*?w+d1R8>Q|~usZEo!u+&XsX6AFV2;}jVd1az>xZ77Iwy@0&im*4+d$zpX<{H)6(W932{TO${I~?U$QKUHZ4FX#- zD$(X2eyu=n;vrLQkfShihWT`XvgFOn)_v4UA^Z#}iq9)4;-{${(n zLDUbfVto%8e==@v2orCw8s^wkzPNk?Rv^8w4ypI*3-uCrevMBxK5MWJabZuudPUt` zhc(N6H-;YQ7{|fu#8sJ=AMaQ@nh#1TJYT-v-f(=FnZ;?waG#~kU=GBo!S!gXyyUV) z11W&I9K`+yF{3eP0i}Xa#xil49g%po{P~jASfL$ma0pm`#cU{l)2?vrD(_NzXyGAk zw8vHHj&+yswYMJsvBZ*pxG78!TA7vmY;D|};MiCa@VB&>inyuX8}DfFE~-c?R5*lT zVp3%750^xr(5F*(7MJWa7Sc6mbkXNXd`K z;%2CbaIRZ+dfDphjIBVQ*^=X{Y`s`~=;>AVh-$NAUA_)c{@|wDq#0{=1n29bO012s z{=4eoj%Kgh#NrygH2z$)UZ@Zqk>go@e}^6;b!WEtDT}*YbgJYH_`)0TzD+I|f%}Oku$PT$>;B3;9)7yd*KxOA@ylb+P)FB+<&yP5}~yL4_-e z+8pp74v2ekJ+#tV*O$3$FV^wbv3|Ny&63TeKMAQR(&r98 z+;k|ySQ1@j_ZftoCPk#tovVmC$$Bd-%Iz;noe<&9Szk%UtX)!%te2$dtbo6@?G2~# z<>^i1Q;g4VR&+kO?(Wo=-%>;(kNDrsbFM9wa-^m{e^H@6sqnc(Qxfz2kn@ zq)a(^PHk(v;eMWKYl>7Sp3H1^+ovwsCrvhq@9vWHrhU@ACe?QIHMsjtyCefXr{Xix zlzGiRhuTCVqBH7i#E9r&MP02bi^fcC;J$BfD7OdvZ?-+A>~xZuA0M+<%CK&fGECpA zLr(_$zUx_Knay?6-R8%f%IzCUzPhZOs9qiLKi~F~GW2B5_}p;~FIPwoS5&$1Q6d*m*2~%~Q7Vwy}4P>Df};h8;oO zMk)VLoD}5(nR-i>Y@Vu0@_ATqSkH-fq~85j`8H{qYnznM$O4qbQ*}vAp0$`)k}kxT-ai8|aac{IwEi7ub?m;i)D4nq@ z&;yZ2nru;LIF+k@wI{9x#(l)!U#jggt*S)h>}W1t>>?IySEv-PbP)t$Yp|9#cit?k`c zp0so;c3TzFtc^WeUTjH{cUx~_w>9&nwb*S{NQrK}<+G*`O*M9m)s7>hPGR@;iDPbB z-Tgnt9KcFOQ$6YFQ|h>r8ID0?`O1L5{03ipY}69$x!h?pvFA!!n)H%UeM8=HsqBAi z(DGxWJZ@flWYqh$%se;kT+EM?Gh8paj=4&`qT>f?%^}vH6-rTOQR13LIubRC7#r}BEIj^4Md5qF% z;y0vFtfkdS>`F@U50|2RAuNVj#aHm3nT3n1M6GdId5!lCNzVfQF*l+y&R@YeFK&4Q zXIqYo@&|TwG=|@qBXb0wMOb|{Xx<%#yw430-mtim(A&}6U6b>?1Z2; z9@=;-%E}6Apucw+1V7^a_1f=yvY(S02lo0ND19Mw=(urD2dM)l0sS8|Q{N1MOkrnV2xA;NHWr$s#U12e-~RdZvXPTgnC5Pgd@XS5Tg!KSVp>!+wR`9!z+ zWo?Vt;x0GU>sa;kENOVP*f@j7>TerDB!dTC)wiNy#J-E{1v!XZG;jS5yBvh@Fn01{bZd{j6l9(#gO{YkT zt^T8z7G3Rwnatu98nf9EZ;|7iw_}|^_h3XuK4YeJ{sEkCu)ZHSH#cZCJzGkowsI?K z;lkbf+v?(cyJIZopS7bk@dHn}M-8Z9W^LU%NpSI$Vd;}wikp5Y3=BBp`QBAizJAn| z+IKR?q>mY;uib{Tm3{X2Yc@I8+7Hz%k@#MU@sgIw7pcC=B((=VtcaeVZmo2=IoyBbdASe+m%%K(SaxK zPH=o9t;Cg*7WhV5!<3C0-sZm({95n^@I%0tf{y_|Ffi1?eUDsc=7+`}DzCxnTxjIN zu~QFqYke>d_x-Eh2ju$L{#4&Pb_<2UIPs)K&8fRBg=szwMv6m@9mx_Pqdk8!<^|k? zA~$HT*2Pd2%)2oDpSu{m`bJ#qw41KKHvinVU?f6!(>2`YFKVOfw{REDI8j&=ENW)E z>1y1BD~BhHxORP)E|ISEMa`jmCX=_lA?R0a;)rV(cHPSq=wG4XOl0-5ZGJ~vX8jps zkt3muBK_Si4*z=Oh`>m=318}JhWZ}c^(y8l)KuI>Z7{Hehdn*U@+3T)5W)*<78ZEc ztM55E#W574bW$r{$>MF*T{4C`CQ3t0?A12(E9Ukm`3APWtNTM-L1ygNjP9hm6By^T zpP+Rz@$|R1{qyU7csCX6-7BEAknP1MD`K2%XirSn$@H;P(pO1^23)^}aw*?*xTz?G zCsuo?9wS@(q~DwVI_ix*gZMl?gFKUYx@V1O{&pu_NfgoAo0yjnF`8{_)g!JR+d2E< z26e*;@)2y;*jCC6l*2fJsJ!7gz<3u&M);WW<&dWR5!R0>kZyojEviFj`@8L z5j?R}%PUc3fpPrUm`wWE`N!u|(qsE#>}_AHu;&~c%6 z_s&l#wB$b!o0p_NMdy;bu{!6me4)86H!AImY?835o8Ca;&(#6H>c%Ck$LKi%^)>s2 z)hSqua$_U9KfcvN&muCLpPoA=ZDXq_;>09h<=oeLrD<<#lh3W;$X{PY=f(7liXB@& zY;J|kY0K#GjLmsAe~o>T$A}ZJG|y_Bb}4)TB}*RV(U^P8nVOCL4#Qr@P%QP&nmUsu zj;iK6*5?T3u1}xN;RzZK!`WYgX=;8kPUI${N8{;48RvfeOgQ@k4Fsivl1)={yXNAA z5NAY*@RnqVEaS*K(6paU9C31KHC;I{!5oV-zNk8eyWa2RnhtwA5O!z(qCtzFRGI?* z#Q}kKneb;N|E8`5JW*eTGf|)f)3N_}E?Va;MI6&o#!kvdOk5Rh{;1Zdu~AOlvzQmN zl@5d2Be@MV<kpNQ#Zy~f~TnUi=(s|;#GHQWXVL0kf+W#bXjL%7B})T-=TwMjK}>nF5H0t zokN;56pyIFXa~;A1fCe`u=#XFm{nOIiKge&l6aui_wte1WUuJ=s4JGC&%C$Njv7fNjX*p*6mP6{#=Ds&z{D3h@C1yuVdIILN0XLIMy5V`< z{;MoA*{y`9fIl>l`yTc-?l%9y8xMMwmesB)UfwShH93y8VN8`ej#kH-DgmP`*h8;Y ziTxHekKPltu%S#1d-77>1}}Xg$F=!4+{nxClfC+S1lx;ekZt})S`Fj-Kb4oi`g#=R z8Is)Fit^_7@d}pDyg2{DIHz;%-k?4pE2v{Ub&Mq%i?38vNNuT zlRg=DICBf0OSk!lONX4FWPCFA$YnMMyJ-6lQvQ)6mxVZEPG!cC%gV!T{t*(5^{7Ew zq?>S0at}&9z~gLJj@p(;?r1zI#NBGwm?cutAYf1mPW^{ld#GDa+OP1rX;*~EjnWwG zkKH(f5SF^7L|I>|YCS2Mw>pcZZgE?kVy+VUKGrtBM&jVCR<|?}cJpwLvx#nezJ@Ds zp6R%@wOVC%V3wPOnQb0svw4_jWI1Ng1tz=Ch7<4wre&~RAX^KVnP!_lMY;f%3-C;% zO13B>3s*qf>d9>GZQm@lS(5TMUv*C^Zqk)39@K;r@VoIIZ329Rt>HAeX;?6!|n`w>`mGx4XmW-IKUT zZmPq5>I1AFU@3n`sr`FW!S5?s@m>PGo8V@)NSw{kGfjH;U?=AD6NH(@Hn?c6ItKX- zSRc|^zmMc=JKLBI`3^UPOrDsTMe72320(9UP>c8Fr(bj0jM=yv#r^q-jtjXL^0rPp zpNrWf&61OsvpHw%wb#Vyxm$BD6}^`gDa|4K_{^A2%q-chL}%QCGgpDE5~+wpD=J)g?Xv*g7)%z16teR#ab`1%_>?%m2zNkkxqtjpsq>)Z z88mW^;_V)>MYw{`c|Y2cXW(<%X4`pN*0@dfyG~_|6RyrP3s**%%UheTh*#%XgsZ-Z zua=8fMp!mVKbiKmHaDeR`yfkYzCUem>lI%~w(VMNc98!p`+i0;P0nOfP%^V4sDlea)*pbOQW&;Mb2PnNOsbg!Q+|lYzxN+d{Ww7#f6-c0K6w3PK9L+j;!&Y0|^aZ>qBe=YXQHeW_j$ND<>4n&{Kz8J|H z-Q3fb@l=5>27{a0INyM42YaC+*> zY;MW>4AJ|}dyk|ThE?=!doQpmT2q{*v4;7d#&|$;C$rhZ+0Z=-=KemMZS;%m?onBp z9nbShFwW^20dg?f|Im94wBF4IJpg(Tv|2Jmf3DV^z%@Dn*J#wAuh7!*Gq8$fz8Bpy z^Vg4EZWpU5wfPpi8=gscHY6=p_3Vk)F?Y<`bUuI5sHduv3VSBat+ibV3_NA~TK&Yy zh{CRAuU;2TEHVEy>w~+tC|+GLDORxL{4KwCc3yVUGu!eka~cZr@{(qp&%;&S{$>=e ziIGLl*KlewH9xLJ-)OGq0>)WBy&dHHqf4ZI*+(V)#wAk!>?P6wkTu&KSBjOg*kX!%6Q6~11I2pxVE&z5>w)HQb<0|KhpL!vPTv*KevlCX!i=< z=Xta(-T7dCdNZ5$VD^LgD}YHua+10yKZppBl)SicKb!Mj$D0>4`eJg9NSf{;`Nd6| z5+_bCGcSlp`4F>ws#4XweK)ftXC%2Mm`!n9qC7#mE6+>4ldauq;p?1UFxo4Ff%br)u%yd@WD z53%ui&fG>7qkRO;sWfKgIUQ%Uw7+mwJg?5Ep4@{aj;uabE;@J}A3nSWr^-ohsIPm( zF?Di2RqHYj_8Mh!i+rO}`l8x3JbN3t(mm091d+k5GqvJEM?cRpyBG$6%;b4FeD z=yC26?bC-VeBpY$sTmnny|YmvS}?v8sZr^$dSJaBZy5PRMRM8a<=xWh9J>?}SLHNE zl!GNVd#>Z8JK9m{H9EF9>by%FBk{Ij6!MSt*zT~@pzpJt`Dxk9^NX{;$Ul-DQXu9y z3(|6y7Zm4wQE((DWQLgQoROBhd`5BZ7c-9JhRhW6oHNt%md`BC`(oyiJe$=v(00d} zds{z_CDR^<9|_4;JcxXlfE!CWs2k@a6j zDyk@l!rEMYxRG%IS9^KO;wy(6dkU=KINsZML}I=Q&P?>lanGjDbBgxQc09jbpU^H} zC(^v9R1E4rxWARz=NHVHXIfA&FW)qA`V-UV=FByXoc2`C6M568nH;mG7Z&8snr@mj z`_Xv|a^_4oW##0}%z13O>8a^+<`&F;!W8tORnT{wRj2^{;cY6$^gK%4{waUK8kpnV zY{uG+i2Z-{$3^lxa?Z5*1y9UolUzA-W;*6SVVay@@Wf-LtXcEtnkJ6CZTw(Uy5k;Z zOPf7yx?@((+eh@dfp( z_$qrSK0{4^G#I73d*Em2KG36g3V;J*dqQH{v033tZX%3^Zzwie-!Y)okLqu zW;NnRf73&PpOgw}K|_IgeQmJ!o#QY@0)OZw{Abb&<8^5$Z)a;@(f>gKYj4@Dk6RJA6@gn3xD|n05x5nBTM@Vw zfm;!{6@gn3xD|n05%|A10-4Q;BMlXF68w6)0pDX@V%;PyF>ELYXING~@&HfLd&Xbm zQJbW6yf?6>#ZbwTHF$>B;^M=9_PUdYu&QrmOT01$z$9 z4i?Eivi>K1%&kbvS32;0h%$PbA^8$nLT+`%Oif2XimI<|nub!Fzho3IL`-yDHxaPKOfv2E1cha}jc*iU01X5~M zlQ-ZW7oeyq94F-XSSw7ui)ZM^S@QJG?yl5Den9XQ^o>KRG!KCY13#`R~L)x z;d;ex@Kncv@0aAE=lK!VKY#nav;6IQbDgPxuiQ9;mBhHwOU$O!o!B^o4-~8$bL(aZ z*1BBNOg_|59{=R>E9p&#?Rzx|Y9mZ#m zt5hdy(3Y;hGEG!y+of7hewhN%ztCoK_`Jqv@pNfkqnE`udsuRl=b{%Q zCK@A4ez(SEj;bgwFpS}=4NjhCbZKxZ&&*+CaSH6@DVoG??(3dv$g1Vo38cFsF+_?^@mdI%|3fK_k-@!?se{NMGqF07M(4^ z*smgc8VwBf;H#sZ3WqT}?N8$(Aho|Y;cJmHo2R7d@nj|4nsJTe7Y3GC>H6AGjyDE9 z|6Z>~y!YMWLIiQ`P(KHM)8H7!V>aFh8d~X&+ktN^1^he^W5)abBLn^{=#pk89SHcl zw*^NRzTJ~tkGH-$wO#NUDh#MwjkI!L_!#=$!I`u$Go6wL@K#ZUMBlY54VWBSykm1O zJhHfeKOX+@{q&nGIi||wptiD&j8l78;x{&jRutt5dGtFAZrEiV;O1!OW~t7UG_wIU zIE!2~zNw~vn{o28Iu1{8@ogMDPo4l8N%b#k>x%jxLj8Sh3J2bxPQHj5e|+;? zd;j7c_mKvt5;Z@Y9qw3(9Ag64!WE9S2QusLPq8`{h6Mb51KP3V>v|i$^<)nCzknzF z{=@Hepl{+)46UfQRH4H6^}0ac3-z{sG@>lpIjZ@~QJbYpS@_ns?YRr|eJ=x^q$Wz} z{W+cRE$-3R0&_K0Q4U>3$XKhR#vSk&nZd4&s~tSFct{MdGx>EQ9L-Crf2>Jrk7P@AcE*Q6a8^L)9Pd{m@I=Y zdJg3R{YiX_y%m955x5nBTM@Vwfm;!{6@gn3xD|n05%?cO;6MF*-v7W{R#Be+C!7CM z^nsiIDFXldWRmp1wyghC;{N}adj9h<`gb=tz2d`CmDsR$FT%ES1n3p)NIU-eDLw_; zPxCQS<@UcJh2gXF+-t{2>re2dD+}4X8awAJ_^kn1XvR znBzRu=Rk6f-@yC=LX>KEAVSE2_wNy<28z;85ZwTjNaO>Ef;5~oHvkgBQ2V$BO&S5_ zPLL1{kO5{40TaMIU?ver0>}sRFev(Q1oK|GMU+x+3O|MN=OBFv>g6C*smB(^ra_%d z<(FoHGbBL7vm$EHTG9w|YJy%6MUnpi@ml14or)N`i?JtQ6HM{7W~O{tiWHF_(c)pfigj0sRjc$c38Gx7OU}W>o5Y@xkMG&_D zaOiIW2spxFMu2FLFdSeYm;oU5mq=3JVmKU#JWH4l**B0;7_7c-i2iLeB1o_fYoIMYlB_Isqv#@*^Zbdnze?$k?Gsyd8XjZ}K6*7z_yHeN% zQ)*<`LrU4^4d^$>&Xnt6v=>HMQ1jA$=t094h!D&@_}BrXZ6LXJWG2efLf8yt9n~%d zndI74!sa8{pL*fLYA7mCj0+ll+m#)I z5pQ*Fs^u&iVx^q+p~@T(lq(S!VGmRXkgWow^|#w;WIJSFhQD&jXsH484qQfB6lc8L{ zTyUIGN+QEo?e#MPQR`q;i{M|BSxRXd3$GNk{0hXqA+Uh>1psPke-I*l05d>5xr;Q*8yIJ1Mn=Q1prPhxTn1i874P4ZA0Vv0Emvl z<{*d<1NaHdSpuT~)G!u7d;&l>FfkzEApkoVD}e%lBVaxuFdv{A%$J~;OuZnNCbBe? zC$x#84xXk%`V-W3AU+j9L;VlZ$yRe9Ne1cz5}pHaf=MIrBEW1gkAXs72M{(Pc?D=W zNIO1KVB6u7$tguT@-s2AP>WIup?VuOZ-MwsfSq7=5O^5ieJ~Xu7B&e{ItUj6n@ZWg z7Q-qj`)r7h!r&0)mQE4nPd zfSy{j0BJ{S7DQ8fpTd=0-rioOyk|RO9|P4QGcUb26zQW7-GH;7L3}R2NcbBJ65Ie! zgUJVltN;+!BKZ~QXOOT3;5ryTfxQ44Ef|n?5nB8WO5t*fANptb^&RC3tP%JdP~8Qa zp&-5z;65;uK;3o#Ttp_h>;DE&0O?~OILt+OBB_3IDz7!3;$07u!{?w{2&)AkJ_le4 zn8lP$dnZs2PAa*YL84`!{Li-O-@&P6HO#)LxNwGV}g zI$$e|HiPsu=$V?vBz3?z=&1wd$sIsLZK5zQhB{yYoV*At8jwu+nN?tGfRX`t=@Rl< z3(U4MZcf^~2PZz1bnA)+ZP00Z6%Uh8wjQ!Nc+WY z0;5|3lT*y3EGkzJz2xB}R1VmrgV>;BFv6I@4}bBA;$}V(r5;QaST)4K_2L9{2tNkV zB-m$y!bnep71KEReMX@g4I4e#^f(LopI5oDbr8@>lUcSm(g$@19F{6y{TKKQJQzwL zqV?|Xe^FV!8i~moZrbl-6@bmZ!%E8d2}C?Awhhu3fthj_1T-;VJfW;}koC|3t^-58 z5^FYExfFdx9C{woya6Sj-RJL$0zzT?8 zBo$MJVeeQ1U9ig^fhR*}h|tH%X@1OZP?=%JOLtKrE{NVl#`Pe>GXQ*oaS1*)k>{mg z-h*N{$oMkAZb(C30fRqfA1s7-!dpB5FP(~4U$_;bdKg~>MZE~H7kca=keXl>u~8XM zW^14cz~m-Kcng5GG8$0t33(#hFXy3@q89P6Qbj!Zr(yIYWYNQsry4?BGja;E%}VZo zG!|aEf`kbGeZcerL9`Q4sX%f98BCDy(gReLFon!e*q`~vxI;I@D`X2pqPhI zCgl{^hsYaoRGCYepM!Ki)a7J97vK{xl?3tuz5#Or6nz*#MU#@8(uEhXNXfs2^c>Vb zko}hcKZB_UVVxNbYwCE`XYGC1Bme~u2lh~@n;~k2-BrrC7oaodE(1tW2_US>7mnd` z5Cr`}2=5k=jr-lj6>`x9qAVygK)e^gOfb_yih%&+;x2qHgP<71lnXYC%ncWG6oX?B zOn<^+h~9?sEs*dszgHm8tN|(;;qv!8uUarcENV(Uc({D;eJxwcnDXJrGCWx(Wq#{|mqz*l>1<{ESd) z`HK))po;@VkbV&Kh$2#ouyKqsRJQ34eKH7t+6yo{E7zOSiDb4@3=O3!U4d#C%!Yu3 z002$>PRb`c?=M%7QW|Rbg`A-CSumJEMojZOJW|*+FM^p&3`K|}tm}z)MAo$wiE<)Z z{w%y4f|!?%>4d@_f@lGJ%m)bt0MCPQgXAzThB0T9%3*ei>3gWU6y`T!Qwm~Xp~zJN z6U_U#(HiH9%4B%vMu>O8;2lt8Uw{Z`{m3rF1Nusz@5u$mk)IPH zei{^_DEhN7J{RqOJhUz9a{9-#3`zsiV08_qV6WDM}F7W`obUrH8w-h4Q zi4^_dt@CuQ(#s;I9DD^cFpPtHx=I)uMnJ@~qDeCc8YZW>NLi;um7bI;nwTk!;h$2A ztx$C)-(La+{VKZ*QZP5H=wjogdYsYm!4Mg73+PO@3p>C7F#SNLOaQGR9;r&CUk7=M zDN_b3*vjAYXH)(W5IJE!3dEfN1z_?(hWi0jBK@|=TRmthCv&VYu(+6jHHK2wU_jh8 z9RGUsf_Q;#giQ?MfTb<=nS3=w%iyPo9B%|D2eX5~E&vahuRx{`0hsU)q`v@OApP?I zJx_q)br3*#_lGQm7;zwHS2o_ZbIV+apg8F zNHFEc(6lc>GaSrq1R4P7_A;4(2cQtl9FR`-7Kw~&fL4M!)d9#-tDxs?0Kfb1{m!5K z#{m59KLp@+|BcA=ul|QYy$8PE1$EIx;mivmq|046#l>`LM>K@rLVFU#djfdDTmb14 z0r+4fSAm*9EOIp5O-B?SK~7-|fEw4BNY|NaC1xmEB?TAFkU&YdYg#M50Q2@`nmPq` zw4mJZhfMWsyR2g=hfz!esS+l78U#%FI!5mYuyVmIFP(+o(Byj|NrxA zgy~tR(*Xnls!t(43=+Zt&Vu=d?3nV{?F#(jdB?WwJ|n7o5u)qRHiCE)Kn(5((I6oJ zkOU?Hq|o2-du@cS;DX}E8O;2%T%CaHo zE?lE@nex&Ks=+CUUPb9ELHsL#tzb42_ynK=%sx<$Fl3n?oLaaQ6AMjzoypzjA z$(|`+L~4L>FS!U73rAbX3{H-a*R=rW!JGrd(yfxJ$2wECa2V@J&y)w=#nb`iCfUoi z?#NgJ(N$z>Bro3s=rQ4|=+@K#Fc3^{kRSmp05hF{Vh8#L6Egz|1^^?NXb}ID@_-ot z>UkkVU{BKYVc_B}+zfat1nJP&$kYcg9n2#joouGTsmNb|o&gEb055`h9u#5%2uVgF z3`J53(Rxr%O(g!=1r!jeQ*_Fs0#YG(2b!%Q-Upx@%w7Ur0q9Qj5lBaQ1REsBfarb` zPe)#M1cpX(Nu(DLYwwnc*2Cjgh(F!9eJYddOuhtf#h?Op;N?itpdU#YwgKD=W+H+00Qq1Z1?l9B2O(Ji^dup;O;Y^PepaOHu2sl_(vw@?PE#Q`uC1gI8Y zfcYGxlQU8+P6M3)wbvrvgMOy<6DA(~d6@q3MQ+I2(5MhPNDMk9{ zJ7{{-1ZX<3u^x#X7Nn&g;{8LLjsm-WiHFO|jiFfI!SH@aaH}yP-3!qJsNa1c{t>`@ zFf&2IX8>=4Sx?{uKpB`lps=iPfjta2oSi{CBIEEgjTG%{h(Ct@Lr{0R)W}9;Ub1;Y z(CO(^Sx=|Q^2PNJSp6M@pw+>7K5S{(DVzg14tX_5zUoLLUv+)NF5HB2=&Jhx+B2Zw zRfV6J7nn;fjZ!RISY(2zyoao_p=yNXZy)DmU^`KoB-s{Xy~~ zB!3Jz3iCkt?fL=&*{2rgM{A%z0SPbN8He;Ih!Wwc8>nw10Ph(#5QCX|dX7RJLN>QS z@Bs8vKs*uPF)-5!^Z=Lx#s$(*9>ESt5zrz~=-mKg&@38O44#Bc2v$JzB8X`mP{pGQ zVA+O}ub^faO6(r86qC@6uv!o577EY|Elq$z7(h9sdqJueNa<4eedu@V4s{GUhOMFp zfUs&>Cu$PI|4}m)TDduN8~q3*H|KLO{~$okIRWN4NJsV|)ExR#{*9gv0KNfpf`Ad=JeYGJ)k^qiZ-`QK zmC%J7Y)b5#(9o)Zb*4uBh640dVWzx{Q_&BgoD3Z={i_A32t@$y8p(e+z+fy427-7j z0R4FTC<1=ud>G7wAi2R`!;ReF**&I{A8POuP|hN2YVgxw3PCJ%C{P{DX$&rbt#Bs< zOQ9+zwdNXB)SDUwmeavy3Dt8OEcH|@Q!X8W>mSPgaM+Nss zaeB&v!&E#;q)o;w1zeXFqB=q|L=o^si>R2ajo4yA&l&DNO!IefI!yXL04WaKAQ_rZ zEYsSAd0=`VixH%KZ8I)kWW&29NGYg7ji~;Fnz<3GRM-pz>0;qR*agW5pgTdx>jHdA z&Pyo`ZsDY;_EX+xpvr{Rc#u#6@Bo-8l&y<(H)C$t)3q*~5tWmA!+tV^Goda3@i71k zz|1Ew9H1CX5lE2@AgmgvdK3AdGzG8wRpY{o`onNwyYKxSzJC&xdpdl-g4{2WJMz5& z%sK+(`yDV_LBIPx{-1qo-^A_;Kg^0hN~coobqci;>w5k-sP@4}8A$j5pbAVSIXwy> ztV-|n-Y#?oh43hr3#S483GG)P{x!gNU``P@4A2PXH;|6(6&E3)7Ei>?GpnP;@<>^g zP9tR~RVZvG)eVbetP`k^P=#927w!rnz6n>YLhpGDu$l$?bg&%xVJE-nYTLMS$A76U+_*)ZPv= z9eMh_y(Ry>_NrXawC~B4SUqZOs9NO8jTrmL-y1;?RskG<`}aY@27oWYdk!yXF)pIOurq29OxHNNDP3`3kj`@MNo*9B*T$J0EL5uF#skoMv(lp(v31X zqf}mozs_S^36Rj!%G+Tx1SCJLOb25J1)o-~kQ+fMCVnRTm5bXb7d@@SFGjM7lxr-& zBVZnqbJ3P#C+vf%hH|avUB5&w`EhaZDW#USJ38#AxSZ066W-?P{uBw?_{@f@$H_Ns zfQrEUg#c|m-Ujm)0or<$f!PBRXxDKF%!i=hu0vIgI)vjo#=SzZ>f=Q!+$@xO`ge-x z&byF>2N22M$5ck+KqI^n%x?r}gx>(uLV!ki zhnbGN{XW8HpfdmIiq=-5o8sj-Q0k^QWZ@q*$H?YiL#4%XPYF_-0qA(T?*%V3A?X86 zFHlH;Bq7)z4Fnnh61o7~1?CQr{D|K!7xDo$F_XtUoP+}C5&!+r-wO)9Btb?hMyZBs zGJ(e|f#JXR+jFujO64(eKUZHQchqnBaP=ri?zgAGJVk)|Z9SN^1gPJ3fY}a``>hhp z`=IuI%ZA@zzoEbA-<0|f{iRArJn0pP;5wGp0Z*aA_>=FJA7j=)e=y;?s4b#U(%tej zil_z2ceIOOej-43v@2ln8{mK3(N6#8`6%q&Etn*r!}6En_^YUWyB~bK2Qf2Y9KeT8 z)*OMPDpMm)l6xsw3hFg-A;T}XYn*>1(G#(HO6*0Zs z1+^KV8%h;45PT2SSyFdt!q9sfYD{5FcvTQ{sA65vxXVy`K|BPYqc9$T`Bg}pKne>q zxb3jeD7btRPN<1)DkB;Kj_pMNW=u5$D%!vz=-9mCMH7nqe87oUl4p&E0jUS@!$V2VM;;Q)!Zg z$YBp*hx8$GqXZEftP4Eku7Sw36ymkWu!cM=1o#-tegcmJ{0QcIkdE>Qt01`s)C`I_ z4nY3!EDO5so5b`1$aEG`Zbrw!B;g>bc^1dWiup1O?{WbP_?H=BzBw|2O7}t<33DBY zp9L5KCY1zaB{V~FH_$jxnBRcshH?W2Ll^mx5Oy7odA|s3dZE7$#7zKCfSE-g3SbeK z1q3tzo58#V(vbt<4oE%%dLJY>0KNwEB}jgC?K8O~O2ZJc$c;QQl}e*ShEuTl79^kO z{RHMm0(7GH8<<}}OiQn>okeCYr*z|s+|I+EA{VovYJrhNx#;yZr3GOE$#1Sjf-!(t z7##^-f(r#3DI)t$-f25!r{jq@7{r1&y}mXS%xxeRkr{=3407PnGE%yjBKKg8I2+uMG(*P!d8Ao6$z~f+Mf>dqD^ZN)Lhs;bxkH`Myj3Rh!mGsd-oFkKtjTh0GTSWeM zNS=n5LQq09RMhY2VT7U_1JFhiIi*_RpB~Y^OWj`y)l%dr25HaThC>M0aXHnIT_qRa zf}M&E9)F(z=${M11Q0ywPRDSjOtc^g7Bv+JCviwIRkNsTTpOLzUeqcS^GZiixv;=% ztVpSMs3;xmRI?!X?-xbpa#3Lu`(cwTyO<&(dx#MJ-JNjgg7_aOVgrch0j%hSpn$^Y zH6+S_$GenarXbFsdeJLL-#~u?#6rL7k9U<|L}P9l)WX*g{0LPYsbwENs0CI`KIRF^ zZ7|Z44;H!-rP0wL4mOw~6-KW?(2RUOknlEux;JVM(rQwIrd-aTK!&L2h3+j>pBShj zVPgO>O@H{KV;dIvFe>s23cWNK&hh|yz@QsQZ~-KPi6`(EfOIf+0xtqg1v3#OmsyX! zw7@8p%j_%md;%4f%X|hl3qee~6E*l%Hl$QGj2C<#4H0OH{Q z+rexD3Ecqpfhi-90B{7%Cm>YiHo&`43TN+9RmO-B-4Q2lhxi06szE#xpaINfkdDlR z2O;qTT?GjR02=I3RiKCuHzI2A7fe^;GwLp-k{^dS2Kvq*{&#>rV9X%l2Y@@l3?tA0 zFa^vcP^cf^Ik%SqQ0%`{2E&4`AA?*Dr7Bc8>OL`iH{~yTvcMwz4K{>rmc(}dZ^D&M! zs5gyc73C!*d8ZY`g!VULS7o6o`{Ab$xjFkg_2L^sNa$@q2O+M3YY({(J&X(KRT$Ai zwJ+3)e?Wi%h37{YS>Gb#B$9>)hnZ>%On<{nPX)H$_cL%gokXS!u)XgNwEr}~k8u7y zDAEhi3{CS8XnqFpLwXey_T(nUK7czEhpQs$eIfijZ1}Sf(;)%_=}03igTxHf85Fr1 zzyN6_`C9{!1?f0Y_i%u3;19C^<$6j~^1cuiLN^b@jR3EKSq0L`CW9dP8_+u-!3OXN zm`VcU0KNrNL*RaZ8({G7*)d@nfFT~$2WfBY#@$jbl2ZB;o)cqcqH22jMjO-8{*_cp zIh73-i7_k4K;Ff6r|+fRfC0V}LX|ESyUAZl>kjW-LGoA3Qo!^F(VzMtjA~8;vU8vvl%$Z%*uYTX}m5c6i~qo#L532%qUDP02XA#}JDM2A**X%b0Y3~&^Pp#;|fOa*Zg!EFE+gE$*0 zwHaUt!sa>cclcBfg0T&fEl34RF*S~5an94(av8wW;68~ICs*B2j|2NuSM+NgBWdW@%>*J*2?+7m~k_%8RTN zXEa9@1LRa;!H$I9veieO!BU(B4ESLkw!l!4r@?LsjmAjw89+Y}y$Rk17zJV^!HWRn zL5xL;(}DUPoEbo;BB?(C&IYjrDc1||{1+;JFg_pPYH+VWa;h#0F}LBCcMPD>OIfl8 z_zp-mAgMd*0my^Rh?aBAL5P#xXdYHVPk|S8sRL8Z0x0ue*Z~hcy1~0PM}9Ar_qs|X zxs0fR=uu>HKavau_zuKp%=LJHM!4!tA*m?@@+>h8N(U!B3c zAJTh~@EQxyA+;(m>4x7?g=hT7Abx}@srhhu5mZniPLqS-?MyIsLG&zAlZVhlDaE{Q zj>zdP-4;_H8hs^9M$;kz@HVvHLJC$vkMrM9NLUk?Xk$l}qB?uQN$OfSzXlrYu1lbi zxB-mBojAn!7$n;$?F1x(7v~LT@B$d0!TBdh>K%aZLHrNN46gg2idQtv5%IZh)8}Cn z4X)UBunXw5{5RO`09pp1_5=I{2Y(*0KY?urM$D1(i$+PLNWy@a8WaSH+V55 z>@lZ-mu-2M*W;C2-mM3Cex>DEJ0~?5p4)(l|IVAtY6uw1kj)uLm;@>66}8HIGG0Yk zQ!5O^(?6R>MZ-MJUzyN`#z%A&isxuht;P3_{)f-?di2ISuijS)J zm=Q;IsJwqw*;w{(_PJfqc@`;J)_!0V?_`DN>eM+@;%WU2D7;3c*hVOrQ}|;b>Yu`g zvrjnzpX4Wc;o~Wo)(tuHEe&>p34grp_|Tnpl2q^wSeY*{(1otGGJ6P0MstMSobzXJL5NOBUu|3G|AFa#jh z2Dg+6`T(>BXoZw}Ho$jqvilHZvI2nj4h}(zeTD*YAr$$Bq!JaXU%%yEtLBDRBf{j5IhRq}TjZ<)e=q5*5wl+dGl7CS=Vy`sXJR0_8 zajZwZ0r}!=1}hFtS=|_g%N_xi;0uNm@%IUcI8bHvtq{q{)J9mFkYpCX3m~3FQi}k- z1@Sq-c>w%^faC{xC*0_PtoHrXj1ULc2a3uE|0Cm~amb>sb)^6-A+Ubo79XYEH6lVZk0j0}m zbw0p)5H}H=39u2wT}W{nxU0bNHGkpi#)|czol5%Jk1%lNcS;va!nk_~2HWU??w$j& zlYs8t0Pz}9f}Rq_1gk)T90&y1sUG4<2oq#UC0P!AD zoW=>dELe@#*_YGR2s|*n9iRZ$wmC?3|NKW9VhM>}gSk#RW5U$&uh_+>|AW4Rf9&>HxZ`!S>b_AQO!Yos9Rbw=R399vA7j)jCKzpRK0Y(S zzlvjw(bX_gE5I5LgA`ccK5UcBCuTz#=D?1d#N6gOHUDXfPL%~{yEN(zj#{)bL;(mh30RIE= zDN=YeJ~qLg2^E;KaKvfEDRE=r3G{F>L|L6NVJE zX5SN_9f&prhXEW4qC3IS0LOqhieLi3JP@;xvK~P>vl^iw&XwptB}+o=Aq=z|>}w!j zg@pZBpup^cb|6@()d0~+(+RqO$Ct_vwY<5QqWXYm9*&oEn1B}BIaWJ!P>fzC@Uxl0 z+hE-S=Qkl`e*u6~_)qxr81ObE$D0SV8Acn7QN;ilod?!i5Wa>aR|4z>!P|3k6F{O1 zB1CdG0^rrE+=uaZJxcWvGE|QMG=sDp$qD)0);>7LtwJ30!76dRu#lPX>V;%J z-Z~D%F|>;9gf837@%Er``8;m{0N%O6*-w26*4a>7gyil6kdf+d{8jOOENfrso&}ZrAYrd7+YZ9Cpw}K1 zhgS$Hjxt3(8by^pVEMSYupeP$9|?fQI}U%kgIA5DCIg%fg10$hm%x~P8?RZNh!64V zT-`=je}Z)%v^FA10JB{no955uxs65B(|AkpcC5xftefLw1nf0_yM0FqRo1knA#nV^UJW~ zF`UqI3R*}!dn|yj`8%vP%6XtSBAg9Kat6TrAl^pGo@TTvV$h1y)V=b6S;bADorb?7 z6V@5R_l!Se=y?56$~_2XsLB2#WG|z@`VCHhKvEL{ct0hLq-Fwi0?`2}_!U-s`fw3! zjL!wwyV%r#c@g&zC)f`SR@&M~gKs4UuIp5=D?VDsgNc`1c@qXykc5!+_NEcmtG8ST zSZ|K^4qCSo=oAz0tw$ien=hB*#Pd1c9NgKM`MrZU3WrPnqQP+XE7(WF(QtasMqqP5OeN3& zSA)0=Db)aAH>`6J=XRE%AsDI}hm8>5h2-SyMO=J#i#z=|q8B=a4@)3_fc+2@wjnj! zjVl65QGrguaiW{O4#xgk#tEXcnvcf7LF9OMfn(`p@y0REPGIkXhi8%El&IeIIBE#M z+Yr5l6f1C@4_LBlhDiR>BY}BK5bQ~iPe76x0H=YNfdmsDaHuii5q;Dtyc!i+1@>}i@D7gT0Nes%JwaE1%^>b0 zXaMjeh)0o9eF69~K?Y8mqi~6SV3^h*SAkp5L%i@qOuBsUK+Lg{>_a4-$J*En(OYo! z27SjcHSxyN=LCO2@(YL`kW>LAMLl7Mq?!P<1koI+v<)SwC)E)|XK>mh`74ndr?0x{ zji=N0$k_A@N=AFS%Q!;3U>yKQ!$d^P2}-v!_n6G<$T4b~F7O11 z|8{{`4;XPXgZBMF@Fvb}#)Ek?+uX_FJGq!6taN)M#ngB}7+V2ht6u19D?!j%uoeVI zp~6hT0cutZo^D}-n(L(3Hid+)8-9hL_^L7Vq7m!WU{1sxPdmqd&e`TDum+*p`Xk9W zfGHp*5=;kJ0b&_aVj+N9fx{g@YmwBI0MCQig%sQjr<~x=vSIP8xCJ~e5N@%&nXEr| zzSFZg8pK_Izj)389i9Z9sLSHW4o_M?-a5)2mUsyg#}MZ#uBrbru&u=b3AB6Wel6sg5A z_u}#ZExbR*BE35SYn~gnMJ(ksMQ@My@@~aSE>2qA0nq|PJqIcLAjF*-b`EpoH@RW9 zc-zff4bhnpiPITo$){bfE!eRez~WO~C)^8#UyUt~gnPoFlV5K{9rh9LYv%Pn*gN3hDLTpB3N#pEcLV}^1mH8UKcXn>{g^n9 z!5&L=+FvE!F;EJg1BZrc19Tne?oAni=k`<=vKbl43FKkQDjW1XORPUbYm6G zXO=s`_!rsz#w^3}eQ=2hF*XRnaVc33iZ=!g=1zwQmy?Op@i%ul4%|rS1G+dLpyE(m z*&vl(4loZAbp?pd;P5uBx&h!w5Qib5(02kZgVG-~-vlrR{Hc_s9s*iv11v_q>R~Xh zgXnUKgA7D0V+JA?9%T%AfyZ8bgymf}^+1>Iff*Iz+A8P>_3KbgRG(qghnX#MIMHyP zjIqAiTLM-RGrHqPDespAm#ZJe=JNa6yl1aS!xqFMyS z?~E@Vxz39%)^Z-WYoKsFQhx56kqWLgYgNwI(iq&^A-)Ys+5kKVVk^PH0JX+yAiyqg zpFv8D1W1hMVFnLp@^C&6t8mC+K73OL7vVU@@i%=2?yk}ISFrv9Dal+-2EPLRjFeyo zijEZqp@XEDK^BN40W&HCQ9{5BTY+dvz>MqE7(i!mJ0kI4USli^W9T%f4;|A(-0LNVFy{2!W9=pXb=p2b;T6P?W6Ol}}m4g0 zX%J5$slNf<1o0|Ch^P3!fcS}^0Ko5q!GsiE*u^z3H96*(kKD?%cs0ks-8B&9K_>@E zZUJZtqA`-X51=E6_DD|7^_^Yk7!w_jy#y{iY@E0O>>4QaMv?~rjsh_pNj(KH3B&|~ zmjLF0m_zU$z%md^3BCqc3E~ohUjf#ESWTdj{}Uh{L2|PJFkh+$`1=|duOOwW02s|C z1UTYYn6w4sV@TddD*Ci%Bz0NbS6nX}8i}95bc%N3cpMCCMI9lMH^BS_hCd-Wl~i$C z98fW0sloJ4v6HnFp*Dj&+Ul>Y)bke5$;DtNp%q7Rawj03CozmSGPqL!%E2y0^2ft; zcR@7kVxjig1k7Y+hYn1ZgCOH)gYUo!6Nio;F^E%e?WTD3zrhbyK$kB${u}Ay7DO~# zr++dYxpRjTth7qa(3v>RM@q=Ho|1o!Rr-HYKo1>*{RCD+4JULQJE4RHZ|Z;9L#IH} z66I=+B=Z5fg6NE-mIDj`QG=AY3?Q)@hn!khcou72mEDcWf__ed=0qgpXC8<-G^HO! z`{h8(kQDvkH@cilkjifd;M-SNC}AN4@FKXok?^nhER2#p5aK;HA2ILIUBLR5}o#1tjV)5PyL4 z3sUN6fN$WAr|Da1GYX7UfAl3J$Nvl>KJn!UoX-rhy55ZU+N(%*g0s9^MUP|Q`heX4 zCS^!*O4O0yv;u00)abjrFx<%9rF3iRyLa<3GVbpn$?uT%15tw%H)`1s4+A<93GIK? zdfbOFnexc?SO4HS)LO7lgvRkm=JU)`K}JCo~~%|kayticHARe*!59O~VV=fPxk z0Sj-F;~2x=f-A)Ln*mHMiK;casop-V5J~OsMc5V^cZv8Jw>C$XxZrLtpO3J~_3F5I zj4gbOy%4279m#yXumZ%nNHNA2J;%n!3AkazK8)2Sj>hBr`Wuu)eum^qs9#QdL7%@F z#5#g3fK4DaBB?Tf$3Q$pPzmrphv3w*F9gu!Iwx*o<9*=DnUccu^~?91yAYA$HC+bJSU|jI#N=Ey`C-r_YYY9h9s*1 z;sa1*B()Bp3`7Z1Vk1DE2b{j)haO5_NEiXaF2r2atK$}*$ z1BOsD2ueK+#wn0YL@FxU5J_D~OMP4iqIii)FrA|Pw`udnp>IV=7)uDznJ_#9$*H6Y z-$AUkHsTc!olCKkvvs{T?du=QQJL1J$wf=6nX9sAJU1~SuXUjbX=Z_#c zc^_dGY*Ix_9x<0X1uq8kCqVBTNS=evP9*gUz#b595^%5bPeFW4kf;Yzg#az!2lu3$ zE5<`w2F5<9eTUTeN-Jeu6&$07Lm_bscuwPmI99=q6%EN8NaS4b^gs|uP8BtJK*QP^ zX&RCgrB13P#JwQq(maXiRV5hZkQF1Dj43t7$Li<*n{nR*lK<6a+!ki7>DpvG{D6kZ z_+Uu7Q|dGxk9p4LOM9ABG%D(mjK@O(coS zNsy@#d56h1zr*G$#2G zZos+kjVC#iWS2jg@yjfH(YNIOPO{lvl9g>h{);ORRNwW`ed=gDsWf*2-9LKMY^@LO zhHt1_fhTe9{Sk?qwC-buY(nzRL#WV<Oh8a(Z z6i9Y3 zywr9NGGsCPdea-31wY7io0ujnhC(5iAT=jLvmXdgkA=Nc$i>A3GRGR`adbM(kYgzC zaNG@}YYu8Va`vQIv)hiFI%z?h@w4VmoIYt*+rBd<%$+uA`kdKq2TYzbaPIiFbEeH~ zJ7@Cr)920}-*)z_32kT2m^EkI_^FfH&YCoR((G}w+s=ZdL)(cHCZ1?0%upTDH>5~c zH11h3WaOYhSYBg#=1=;x(^wm>EWi4heBLUI)$VfV5vphRX9ON`;rT&F@wT| zJdkRjf@*4fQvr=mC0JcL`Ik|+h6hp&+~7(6i3N{DXa^+^;gEL$?zqU&rH0OX1yk;u zMWh?V+(Y2Ai`(vVB8lNe9jEX+&_zGt&{7zwZYNE_4nO2woAA&Op2GGxov4s|sr~EZ zanDZOS^a&$qPvWw#p_LIadnIq(~QNaJgCn8`5_kq9($gcPlKf6u z&&88GnCaxZtl#;PWG`@&f1*0|f=JVMGGlPQ(Wgg|6*3zH`h|EHr;hAHt>`Z$%?#0r zZ`cg@RRnRN;p6Q{{dEK-z)N8IbJ1zUp&W+xjRg0>iE5Sr_%13BzVXzb3E#+p974SD ziVD`>*Oua}a-e-tq$+tZ8cY9B8+R`Z0sUiy5cfj#BmGm9Az#*Uie})@^$Z-c*%|Sx zQ|?T?7BK#I1xj^V7K@+82gVNr&5BbZY4lmu9Q`0G>7E+$CU^QPJQ;AOB}qH!J@)}j zk19^nwVzf9(VbhsVHHa!P_ynl1L95*t10gY6v$nqv3RA^B_VEcIO%5W0%sXNPI^}b zz%m0=`bT8$o*iezZu&ghE;k_N0Cvnf*87X>LUeI&bhhb+>D-?I#uy-NrcRpfc*hw7mj+|K zMu;!{?bFa1mo)_?ank2uV0q(Hro>K8%sWg^f=+4?*+YWW$e?QWjFa$cjnB|h+%MNV zx|}VX+Kz&I$NP*e<-^FE;4>hnThjIVhAWxX+f|15oI^9ggvP?yTc-6va8XfpjCx@ z`W8{As^5v@9sh_R2V8m?=J7XC;sxk4{%~W5;es%SX#O%v6=FCtvKvCX5dpn1);{4a zpfp2pG+iJ_A1&&SG=}+wzOsjENBn;_J{K{Yepu#V0d|lOq&o0Y>ZL$R_m~d+-=jgw&VlwEpB^ z3u8uXGrTF#h@U_|GmRyB0W7C#&e176YIgi-k>%Ss6Zo?NdZgt7k3W_Wf0mY~H(ClN z?qXbwapRw1kf``9G@^fIguM9I>=TP3TGoT#ti4uL1p~8q)XD zfRQlAbGrdGSHa`N|0S@g{7Kt0IKwdQE^Kh#=JJN zd=2B+za^kY`ra7uhe=YiIo9qeTL@-q9_w;b>9L^cdrLST8tKCs)z&7sDFqNT1=v1AgW5#2JPC%xtn znE)J3PbQ+rbT1lA#zgKv9z{eCjOfi^JVj42i?^bPo??sbsf*}?@LXu5x#PM2p^c~< z9RH&O5xpDSL@({x58jI+qFYAvhPM@z3Bb|xWFmT1ze z99!Sm_KrVxFwl2VzwzQbXtp;(vDSn8jB@;a2B~=K;r)PqjAU8y&HbVIQ-sni?-zPF zyr;U;!HdL}Bgb;K`AI@iMF;@vdT6 zrtrmLOE0GMr4f{rnBte!oWUO%sV(GM{%?%L=V*t}M87&efAQ82Hj;$_ewqbg_? znb%f93+pYag31WhRzWK(v{g`LVN?ax7TGGuSZJ!CLi8}?sJ>-`H@0Ej#+GR<0Rv`O z9mTtbVVNrE^xrDz^4}`xT9=opf^PNmYA5ei)DX+g;`Qg+kqCE zI_V*L5<*a|DCueA1MYYWO(_P6u7-)) z#0hAyEkzSroge|r$5KoZZ#PTvB5V63YmTdD%#!}e7K&WWv)3sWDjCeYCR?b5zY*b2 zvCtL%1dD&Fg`SjF08X{gm-kr%(<}_+Yu3PY3u98m@Mc&Ta)^!>{R2xejuB0;rTB%>IoQ`f?FR+D)}tv)!)|&Ay>>c~ZL8=GBL1_w^Dm z3g(3$&^#V~WdZx=9oF2D%h^}%v{2+2w$9xaYB^^B;Km3lSBA6qZn7{Y0VBE3DktO| zhP~NBGpz8aaT%EEk_t#}vw_WGUwS|ShRnbo7Oyv2QL-8EBT*&bbB(F2lSi#LEv0O` z$E?(qo^0sHZH)!Oefa$+ER4y?ls;);C@-;4Pgxk3-VFQcy0F{Q^L7i9!k>EapRq6{ zm$OcHSePX%SdwQgG-cc-`Xq#}cCtr2Xv=sp%I5EsfTd>{U&MRA$VRw@zWjNcH2@+XRm%=0+x@Z_)NSPScf-i61MyA7K$9fD*D4hB|ov<|FlpG zcVzYdve1-J^7if|F?y{6tnXGu`rN#SjK-XjL8%1oQ{g-VN(j+H`<2W)m~13 zKig9L#!C~W0+x@Zh$-(_w6Q!#^U#{(B`>yn+(MD*oa7T0Dp?C-KWQP}-eU$S3thQ@ zHIQYYC%>|`(-z|V%K)-13?!d5kYiy?USqzw7MfCcN-qXe9nJuK6|EQf{K(H&0n5iy zlqzovOHsh;EmMt_f}OyfFFJ2vy=4h^F7X>$Xu4~W((lswIn1`$I_HlJ`;Anw9aWbSo&T<@DCndfP>BtyI8#=&h~thSS?3wspJ6Tj0oI zR%wUGn~rfd&M3_*D`ga0TW=S0cy>|&^P#tcmA97OZeRoTh|FUsIJ-(u3yrsKN^}2y z^*ZaIyY+S+N9iFdU_SKLS9#p3UuNRqW4qghV55`>rnk~AMzNZ~sQXy+y*#z`R{}VCxG0l%t-h&{^`W`miIU%wZSH^SHj!uz_`3uCl*k;7Hk3nuY6RUR>**w=Gf-4BSNqK?u>|zU3!re&yB^GAMAuQ8Un~@nLGnM8Od36voIn9=7GpE$E zRKU`*Oe>UE3MJW3{`rwN)B&pG9HkGXxsjY}&0De^E>wYe)DQE^m3JS_e`5<@QEP76 z@=6<;ZOc^_+P1vfLKK=cbd80f^k*Q~S{Rqx82t4SR9TGcQl;NwT>Li5Uuom|mSD9C z7%_{rPI=~cefo1quaC?zzLv4G+!8@APH#6V-5g^>jbIO1YrXwNtJ_q-eCX|N<(X~m zOgGvXnPZwV-Dpz;qi%GE(zEHU1<#OoT5sR5gWRhE=0k5=mA4wC{KEF!7MWvS8qW57 zD1u@-6LNJI z+w}=mbPIv50C-si+^5{hU5EqO1rLG1kIGX&mlg5Q0VWFmj`9W}H{mZo`0v^X9Er1s zzGtCGJ9f=t50oVVv@_EerBOL z<-Mi!X<({FoJ986_8P=4_k{`=Jlkup@-Af9-?Ns#x6aLg`&Q{qG;hF3>^p0|m(Bfy z3h0>Te<<&5nvY|t|Ex8aK5V4@wV|?O|Elyq^j6J$ezV?AWr_Y#0rR0ZPkUWZDyig& zBhco=p?qn~{vV5=j>*wnq=gZ56ONbfE3L=CPK{&Xv@SZ8pf77ap@W$KQ7e*dS}}C; zsh`V;mL6cbuAi&DXTgx?xSY+?C2L@d%h6W}^DPwN!xq25LM0Cq7FvimC0swP^>=Wi zxNE4Nt<4=l^(Mznu@0CcOWR0$eB3EFlHWKg51$Pxzg+8TNYo!3w+(c(SgB?VO?5!W zG{FJN~IUHOyei-Rom)Z;& z`6ipKgN^eJ_K8Dvz!EUd{@R-lCAo@KIlwx1hxUYVR3F@+Pw$Rp;$!mg^Yn z%}kWTwf=_Q2BQf62Uu2yJl7&G1#Sugk ze8rm`OCqRErOng25yDfgsW{(e{VC3P{#iO;P|W%~?eT_9*@$5yofW#2Q#0rMo zAc7K<4edMJxiCU1hI9W2=i&%O87E$I|sR zy3snYC0{nOv97hSK)5-xf4zl89Qapg{W+bV$a(Tg-GFwAzt`li(E+oi^Yz+0934%% z()lfR-f(3Fo!@GqC%@471`7kZkW=a%b&)J&26xs)QbXmt>qoLy>lw&IadUnDCOZX< zq}n|?V2rHK2ekJ(BjIm#_*?AQ#Oz1sTP+mf_uu}57P_*LUGyOfJz2s@>Ji(}F`3Sh z_^5?unBS-MAB^N}u4(SK6<)&PJgx)A$Vi^iUXx~sgd14;=r6Rlra6Mn;?nucx}YEDF#D=5=&6)`QyZn6%aVUNAuaU(tM8WYChZbHJ{VQ(tIrAuPIv!ow()$(PX-mo$fZn%1Xb% zLT@PJ@X6MEDw(f&WmT;C^sQX;ky?f3gRLgXR*Xi8(QT&r7^+g!eU;|(n2hG*k2abQ zCfaG<_V189f;o*9lT|0po9JCMZ$fv|yoq~|=1tHZnzttp(YzPfOY?47pX5l|eHhvG z)x7uAU-RD0K+Ss}hil$D7^HcTKScB5d}y*SW9y*^%9N%`2jb$)h<%T^#XF(!9($1uv;P&J@jyfvK8{`01L9 z@0rO$(Eh8D?y_WKqSsW}^Jtgl$(HoMFG}l@ClHJKG)n(j;_vd1+ha4&9x<*M!U&`9*vZlz{m0~VedP&KVOd*xx$tl)DdS8vM;EMt*FjRuv(`{4<{1Q!c`7NqOc!*6_oJkk z)BRW}=EOWvia9HuBE_7Nrbx+XX8F7>8xGZ}Qp~Bvaf>-vvB^s=J1KwB$1E+CQ^@Y0 zPsac0kb5sy3aoXb=sNiyf;QGJ{2C@+V*Z(iWEe@qT1l2um<2kYj9iw7VcQ(@E6HRS zgKL>LJB2+#=aZ3{!1nng8oUP!%IOJ0cY>B#4?*${Oa+Y`x_CNI%IZ%48xO1{QmjlE;-q=b_}>|JXp zC2KG+WA9l@DdF1=vG=X1lsw8@KCrf`gl`_iKD4%~gumqy`^eg=621ix``Fs5o`($` z?!-Qk+|L-VF5%1)`&4qj2HfYC@CU?WpNXk`Co5_Nmdvz5+R0~;b1#GCYX_LQ#{$z` z`-eb$FHSy%M(fX7ZVh%u*@Iyp`&`^-P=l@;?rRzTn88S>!6*-ZY+23*$7RSEL=gUD zp~z55f3{Ewf0jA?#X>Fo$-nSd3tgE+_?v~E@VEZL-!1fIHsK!@2Ercz4F9w+CT9`; zWnn0vQ~>U`FfQE2EBwd8gj`POR7No;g}?L@DhpGxj?lF*OAe(g-@>#6Xz4I!VYWO? z<+z18@;qVE!d#g~+bj$7+Y5_Y#RCff-QvM`kMJ-~x4jLT(&JuOVgwS2+X-td%#wQv`&pQl2MGsQm@Q8d9%f;V>>@nE!d!WUaIl4W@)%~@@JI{u zWe4Ff3k$FpIp7Ej3*}A1kro!o2ZW<6ES4__kF~Hw_7aYf<1-(VR~hl+aCSl zT1=whOl$7QTEf#T6uFIXmW4_-63(_z%L9aSEOg}&!nqcD@-*Q*3w?QxaK43syh6CZ z!kFwKJl(=j&cuuyo?&5JmJ^<7VM3O(1{PbGlp82rYGF!lC0u4obi*1lytOjHp2GfccV);OT;*Dvn!|gnIr;BfpD{h=nsSsScv{WxWz*B2g0ouqCXIBvoMq`91#y%7?(eB4h|o-Fd+)djPOwl zlM*L<+`^RP5l%<59T4?&i?Umkuj_41sus_^s`@H-Oc{+1s67LTU9KK`ompR zYiFUzm0WeSw@}FkY_*OS22#eQOQ#6N_{=kG)hc|IS-*@`bXeW0oL<#IwCda{&7iox z`Kr?U5@d7s$L0*ear47(T87zOu*Bvf*U?8ba)@yQk=XkxQdSt&<&uH6-yi(o(3Y#pE^(UNL~hW zC*7|pK+lA!7bkCS1<)aCFw}CXy8@|~)B71zL}GB+BA_fc*$Oh5Y?O(n5LV;Vs6+mM8(!8xVdGBq&9HNy@UMV4+Z-6TQ?w6F zPINx^Y;+^*r1~W^p!=lXhOz^pRc}W1xjX!Rb!-z=%@p*3 ztXBR>WdC00$xu9C8-JV!(uXD%QGv~w%^u~He}U5M(4T zVDjvC&U4y)u2T6Z8ME$my*8(fx+!z=3sL4I1a;YN(m5vE33FyS_v%7gL>?c~CL=iHm@7|XLS3)t z)j3?R8ys-BUbiL)=;W5jNicKrL}!D}y$yV)?V4i8S!KTddcV%YD&6>ihgG^gK{Iyx zRk}Z$!2b|SK7bMIC8mn5vsE<9S)*fY+R|8n0dTF>^vZ_Dq3vEQWG^&%^*E@u_!sK( z19@GjGY0U}vgC#O5Pn-0Wp<%HvM#fW>oQvzW#*LMhHku2-%#guVf{K-7}bFZbdjyp zNi(NAi*>GPu!)mrIZG_f7F%j**4f!nojK+0v5c9aU#iPtMpQ?^Wal)UdfNH#ntUrBeL4o~T$?saACnUmY27H+<(BmCMN> zR*d=edQ~xrGhB^nL@j#rjrH1<*@fZ^bDfq`4DO4(mb<2O*HoZ#`VD2bV-;XVxV zOl$?Fr0)a1&j0+xXvb&!=($qInrpV}C70FZG@Qt=r$l*vQ)II@=Gq|4X zBdt3YXK1}_hSkevcx^Vzurg0pN7>v}mrZq4g(jQU^|EPGFPqNwTz9GGx@)cLv7FT^ zBG+Hkxvr452WqN9da}i%F4kD=LZHRjnAwwAk~+LkZMn0o71kG7(#xzbMr=1q!;R9t zm;)gh#~u=U2J;5K4CCT6HtJ#Yo9HulQ&9yG?Gzme-~AeYY36{`Jpc(ayXb$;eMttP; znk{!j-y{=zrOo{=++OU-zGen-cm+2rxo9zOkQVVxuDMGIumFkQ}pX#unxf zd`LyExRMK-5m!C{Mw7|T5_5^-RBn&pITpSa!4(lKh2kX<>GaP>?unDC8uw1&@3<1>_Tu<)!}u5qxzZpYh(Dsc?xYhFqi*~Vy0`an z)u*+YdLNrJq-iwo<1r?HLpM`r8ZV;~W_N>+mmB`J#^hgS0^3=F7dJjlbN>LRaW(?; z_Ec5$hXKp(?TMVWccHXrg6Z|fc+ZRj#_w3;>lx9@)!eNwGJbiW$&G6y@8#pUMoJjt zmnR=Ee$^UJM=f}}s;;Xu-ers%O~SR1x9bG%77-cmI^}@z^O14GlQ9%>($a=w;X!z4 zHVxA<7(;k%>$JKJ#m%|aNI!tI(E^~})NOP+sKKP1h8a|V&Q?b2Z)o{n!3vBMcn#n* zJQk}=olxdttkT3~K6_J$CvZiG@hC#|~ck;T}5@?Xjc2tpFYEu_MtQI}&4K zI?C>`!+A@hO?4#NIY)g%n@%OODT%hqk!Y(NpdDmJyWzl!+u+1v>fmr2*qS$MdL&N< z>1f`osl8RBc&kPoqEuFQWIe^OoGOSkhq z_PJ)PM33G(bp*xJNmMC2Q7JJ~DPP%2xdfH+e_tD%+y3usV>l)Msg3{EKxixZKNS&o z&xcvU)`xlu`K#7BXM?9XxLouX=YFK*Tpa$z%X)K~;RTZHbwJ((kSA1-bl2eUHd2ae zX-DtEpR6g6t7VPJ_ur%Ad478CoA}#}zntp$w}Yo!rGnk~J0#eQV^8ONR0aFVrI;-m zm?|02BI+maph_A>MM!XaBYCr^J-oP4aonh9xKZ=EQAcv4+Hj-(>LU9KUG;g9=rs5oN7~STJUNx!u8~GCnwduWDIEUZgL+amwixm zDw#~~)8w*4G+vQ%h~_|lNiMZq`3}X^`y&*Se<}MrLdl#F zHN%~MgnHRIHK6}BbiO=JEnEsz!+EiEqz6&PUo*L#G8Lgp8Qc;`M<^o!ksG0Q(wlZ( zggVJI+W8UcCc~*2M5u>ks2Nka{g7WTDXjzwl_||YnMJ#Jga%17Y9`Dt17X$pF=a`W zdphjKN*AJ3q`4rc20w|ArC1|p%DI%JBgs-(%i7A0@?I|Q6Xir`g*-|Bxe>ZZ_)3P( zQ@M-bf2HDk6Zwj@3K#>7`l{yBX*nojb@hy!Kbpvb$ zDYYGvQsZr?QhY>TO8MjpP`m#-lPC7;v0YgCS{Xz*wbTN2rYqn5a~DfC>Xn zQR*rbsj&f5mHGvsi2*Z}nvQC3YQP+92e}?4VH5l8_jm!FeMz&%det%ox79&=WEjcl zT8VbT!zm%dNaoZ^JSUt;2^soncw;4*EXG8b6<}~ygg4e=tbtpjgu0pH5D)SZY|t== zF0#~k?|rDrEZn+qCwloD7f^o#D()n22Si4$H-P(3tv^J+ml87cV~`ZPHfKa11MQKK zB{Qq~;cs#?oXxIU4?S^{{N4FE5%8S!)T&9)h`)eZo?cZ%m3SL8%)F{Z6Y$|;aTUL! zOn%zTan6dY{NyOOSQdc*+wE6vpo{CFai(?A1BE@iDnZw9abeZ-AdHJk>btnK&c%6E z-_pgih~j+f;&SA%vMNE>aB*#wcyMuIW8AedRtl5nRaK3_jK9&$!EcX8vDYBuHB||E zbFwO@RIPwQHtPVdr=!ce3#xK8kYuw^cncl<);*^xmzC>gGfGe1KpyVpRe247d^1qo zE2{FSk%gZ!;iN=E9QeQ(2zqHf^zgRg1#gnnl`vtAD9|7NC>57 zsmVhKA$CYSNP-s|Wja={gY+>Gy&LASVCqAGp~7Qh46PRxD(`%eRlSd zK*2_;pJQmviGNX~G6iA9E>80+;=H-YDQw|i4?0E_r}%3~6Ce0_58`k9;KT!zuryBI zSI~|3NIYA|DLDZd40nrvXo1W+rAp1y3VQjODyM^p{Xq&^n3wqKMm{A?OU)ArDmDlp zCK2PUmPoNA8~PpHX79BC=UMR&g-#ilxd3h03QlvLQ)AoxxsbHrRcdUBq%MS@Nom(LUmTJq!(q(e)%weii0qd@Gh8+!%4% zP%J#7lWb0OcFl=StJo}z9&_yq4QfvOARMy#Md1VrqtkQlHx=j< zoy_it@i`POr7${M=R{}g#?dkW%pH)W&cR^|Qu;<5@Iw~2;!m6mBf*`(Na8tJPf$We z6HZpKhB?e2bqWr@BGuY|0Xj~GvCqa*z(^Ecz5^X65=F0JX@FHY{@U4!Psh;;RJg7yjFvWRA z#>2E;j%490nc&UN(b3goC7g@$Q zC0*%-Q)v0*A$aCvEq_D5SnZ|h5gN-qZ!xHlVTAO7sBZI8H-nO#c8+sw5$&HhO7#gr5hz)CcsF?1Z0XsTb9~UWhrzQO_c(`>o|cy>X@G zrRfn--Q;=s&r&i&I+v>&mk{8|#zIp*MzG5xY1M%~DUfS%{ zhmDdwZyPj11{Kl=ynTWagOX;|cn!2J#$jly&ue2uSRbJLE_|Pgj`xxE&8y5Wy)-?- z&t5OZbFNH4to!Ok^^IpXO;oQTs_(32H6s7fOVcBKzvp>FK!pq=qz`!e%M0hw+jU(W z=kLf0y=(+J<3AC?TZ>wL^So8iQtPmG_`@qSz3e#Tk9`p65vR1JUYNu*V>Py`3x1ZbOC<7^Nnn=B`5 zHeHZmrl~cx5^UXgF(qUeo2~UEw^2fdtE$UFe$Ot63~qy!l}|t+FjBQ@S?2u(zRJe@ z(W0ZyWW0}|4hc@}0t>w$04=zj4BbvFUEaXRb z@*oC8D)M`mMRV5oXxIT|33^1HL(9UeXjz7?G`u!Xc^%#JD2rl< zeNdUVl@UxqnTFU1#v=Bk%M#ox(JAgDP0O0#d}lgH^Rm3Ipq+sAfH{CYqp_vHKVXczyWG$o;8AftTtt4== zuA+ntSI(>s%P`+c&<`)kSDOhMuV39Tz;TvXBr>;`<1DoZU;3dA&$37hfAD*mMfeUF zUe312lb122FSm$u+Jb7YC-PEpOtoiJN5k|H^rmyG6Zaq(M6r+@dmM7$H5v_g&SgZ$Sws{f+ga+E5*)LU<$p4(p94gH6?G`hexu z>QqN)nA6dNby4wj^l-hX?yn9<(ofgcj`M)^a|U!CtxnTFqPn%(ToG7e}MM)*0Kp=`lUKekBH-=YR|kK z#*9PyfVY3D!-qhbbDNVf-3Oh6=Qb4~#k0tt)!uv1Qp3@~_g6=g&DDKyp2#HV5q?sc zP+?4)vr)Rv56?z95i)0^FynD|Wc4rjiA>~Y6`D3blc0Z0TIHGWaA?Gi#d@G&#!Rt@ zXDxIpEJ8f0IO9#FpL=leUYdy}T>eg1vrK~i5l`z(YB?yW!s@DR=D=`il?iX9CHd91 zg#2}(_L($2!m?W?^$smLTn>sX?Ql6bLfVb>8`8(=5h1gH?34-j)9bmYw=ULeA%=3# zOq#i&23ux4K1~f7R7n5GX<#N*37(9_z&N~KjD1lD;4AX`TW>Gm(Z`@nnm%ATB9mH7 zORnWc*2T!dbM${=991vIBQxPzdi@d8(lG0lKR0qr#_TnU82e@#uGE)Uhoz96uj9lpRVl>tf_kIxRxcP?}{!^i8GC zwur0pDVfl0jd&3{@l>0|`YPO+$fTJyG>*@BlaNKo2t#IuY?owGi$KXjoD0v2ykTb0 zvM>|g2)-hJk@a?826J*IO&_qlAd`BAmK<0YMV8tzQC(6ms&g~pm-I8X8q0R;rx-pj z&7|ocIh~&I{sI*;jF2AT`?^djFAJ5yjx$0)?^-8zDO?G9{%ndQ#oAGL(5i+Qd{xLngo=NfhDHG$HnF_A7*t+WF zOt^^N8g#%rKhZ>?E=A{lCzGZRSbm&It*0d?mQN!~JF$Fb5hs@SGvPDzvl5r)A6h@< ztsUo!Oq%|o@nXi~H_)N^jEf#obNezWZX#%+`mtWkeU}NjMX#EHscEk*<1O7WC8Lay z<^D{Hn`s!!f9uuG@0oBgExY3~>`!a?7bYa9b($VgJKtoyaiBtG9MT8kh_?>!1r_Uk zSU)G(+DzuSol*0Du=gHdRutRXe^+~jp+HD5*AM^59?^0<62ltsVR(#mez9BNNUu|TAuobvEJHRzS>0Z zC9S2^KFmJaSu19~*3{lwa&&0YT_1;M_ZN-`r8c(PIJ9->9!ku_)}wo{P+~iuvD(uj zIjr~NQPl=KUApW0g{Luf>}Gk|_he2S+2|)hj-UgglAJdGkhESAdZ$}yNAN>_%o+<4XPV+o|cJh zG=o34YqV~m&1}zH;$0tQd0M7g(IwvMC`)UZ+C-Ol??hQ~EwhY-xy1W1$_lhhA#%(m zUc8&354Fq&a$~Z#UlL{IX*sdyYdKLC#^m+we$j?TTFy&FF?lolfGDe2%aOlvtUvIR zqpT)c4!b3>@0&6Ijj~F$9OcSlqlxjZD66TKgG#g5)3m}fQC4#;dvpse`%|l!yj1OV zH(jg`^S4Q%V_aczw$u7+LzdS_x?_*+#V(vPIcva4f*cxoECR2k9POv9IpD8hw>0Q z$i2#gk4UMly|`FRBNIdRbM}smI06}JP`M78KqG|)Tbd2*^~1|Up@(Mw@}LJL)NSm$ z2R5WRr~%FBay?vVq|g{k^CE|B~K~CUwGSMQh zp-z*_LtzAYLV0klAm_n7B^?0BW6JfDg6zOS?l_D5m08tE<)JWwJgq!@@4&Ypjg(ej7#XJ3FD}<-3XK%H#L|o+n9IvUp@(L1d2oZ!{79vjHlXR{ zENj4XWx0Mzc%;6_!&i1OmS$O7*$?8iYe`Zh3jpII>>R zQpHWt64&n}&2G5D$(Q(ZB*Uz3HHFY@VKE~hog*2IZzSZ0%cU)R_nkh$DDo0}4l5_jm}y=^|GZC& znPl3x(7&)&^b-1)){5Ri|H@j?E9hTaD|!R{8*4=`pnq$v=>7BWtQEa}{=K!Lx6gmD zR`l}ukJgIbJ^$HS(W~dbSSxz-{5NYwFP=LUQ5~Z9&RuIoubunWirzYpSu1+!JYlWq zo%0-PMX#LaS}S_vJl|T;3+IK_irzObvR3rEd1GruZ=07`D|*?y%v#aA=FO}Xy=vaV zTG5;4t*jNjXx_$J(R=1?t<{=m3qJ0n52Yu~TjtyPlu1vTm(1H&gwvwF?phH%Cw;w< z5zswC@)f`hSUX$GSL?8Lu~tGoj#X~0+(fE=h||Yfg^4|}Dy>zP7>HGEtrkSnsX~7# z(cH#aY^RDSnt8C*R)i8IyL+l4NO1B?>jPPA$QeEV3W9NC9d=!t^7j;Ziai~Nnl(8!8V7};wMs0bDbvMWc>gDT8k z!_AHpf$co7l=zbM?m9Wm`d@;5n+K0My^Bv3cI_-K!MJW96oLv!&5}swW)42^IIIBWW6Xe&#JI5mb!2$UEiclCqURn`c zEXc7OiZ5$`yr@Di7o_CRv&grZNG@VDMaU%;!FoYHMu}w&kXKdcZG!CIj|D}G+(rvr zR}l&$K5wrG+?F7VxMaMu0rKVw-JX1R9p}_rE%H>(waY6)VFdX=MNlV54d1E;$dwg( zoFHGQ<@TgSzDAjcD?(ue`9wu9O^~-z`?U>_k5%YJg1mtI$1QS1mE$~B5eg$?=DCVM zK3=GPXDx1HG%lEmdhXK|`b9yW4)Pg0Evj(`fa(nJl|L7mxbp*M%|B==k;BAcC8{5exi$220shWrL;?;(#|E-U}~9TEs4ji z)Gb=W^Z5WUmC+tQpH>YkL*a*~s50nH2{jyK<1`P*{7NmKigZ`?;i|zRn{o~;sSJgY z-fLYM$j3|6O+C1HtW59mYx{BW7+LJ`Be6O}mf7Q*SL)k^b!YbHmX*;S|0S1hohn1| zMm#+#gC~V`Bzt7f2Jv*M)LRAl3NduE@q9?FdR2zP2(qR!=-dWmA+yrDG*a~-f?Xqv zFCBhGf9+};m7(~?$6l4e@#13=tuib^GA3r$ zG0ASgGpJI}7oHjL54Jq>xDME-G8BGz##RQm3eP9RbAUz4ac$p9{fr=wXZ-AEk#iY8 z2UUi`2y$X&@PQy3!F_lGhjL7q?plOn*&@kO}d5 zOr`E8$hDjmjD2yP_tPI8oax0^BRs-aWNu5RL4L(ZaeMrXcd|cHqd_sH#A`!CF?8Cy#ond}3{uVSTcmm5>bUp(&1j4Okmj1#5)$ zbM~VW%lZa=->RxWyiprnrC%i#NWg*cFRe9ru^>b!!m6`Z&z(;i^{>}7tO@sJ%sS3^# z*74+*+xR!JXVq2}h&NbMReARb>p0q~f5gLC?;FYw%&<1b+QVAXgS%D*n}l`t0A{O} zbsT*)sH#A`QDWyR{TZo10uF>9Pa~@G+H}OzQH+OC5gV;?He+ja#?zdB99j724B4K^DKgVy& z+K>7lR#hP0h<~pteLJZ@0uF>9PsdaRn@OoXiTJn(Mf@@P=!D2(RF-pYJh4Hq9$BT` zPIwx`SU<}4>Mh`>RE5INwdiS8fjq~kT#f-}RHd&)bFt2}mQp2HGp)sQy8bCudW^7s z!kKG&RoP64+;6u}iHby?RcSzEfDQ zU<96LV;#dNonIA-H(0N%;^SSg)-i&v&akee{52WYgRmA`%T-U&@=L7cse@UFS!yj` z71QF&tfkfd>>bxyi|b}$yUtn?+vQbyFrM9OU|(coTMpues!(Dkw%e-$c{W`F>Pfg?q z@~E|Z)rD=3Sxc+lSgWlSQ@dh4ZmqZ)gtf+63B^4a=Lu^Cs__8MI@Zcj&(dydtraTy zYREck<*Ki-p0ZY+`W0)vwenSh7XG`n3eLX1#6Y5 zN~{;H)l{XhUba>XH5BVrYqeBmG~*^~wPKvEtkMprQdcqh@3Z4{VL#4wRiX3=z4m@p z(2)}ANJi9$>0VRgIJSReExGCPZj~M+JW}dC+lOs9ihNQP3O_twRt4jQ=Rx-9uOp-@ zz5iL2K1+~=agl7m479D*d$Zq^QYH zmPfwEqN+pThbO2Gwg}G{kYTks_xTcmuGT&vw=Emv)zNYNWis-rLtzBjq&jFphN|3y z+cpu>6J(=my{jNEU|%S<$faa7s}6+`WZUXsq9BJ7d;18;Xb;EcMf zwE{JFAZG<@<*4DfsJB+A4&b;v&|0}lzHczdT6yXawhgwHtmAd3{zT<&B95J_qbrie z>IF=fd5Au-eV6hNUGM6n=QluMVb>GVxrvT|5^xi0ABTy-0YLaV9#~^6W*%yy{T+;kmpzc$Ach zXVG@?T-_j^`PF)}@YK*93oOrx9Dx>Bhr-XX^``1zsZ9U6(rULn`r?F3dTwNgED6z3xZzUB-h=K6q>C5Wid``KhjlQ;Z zjUxWWT72Y__`kK5YkK8-Yel{CgS8r|%jlyYtyQG1#`?)x#i|ptpr5VPSoOsEr?r}> zYOG(ZRiaW@zgnx5xIe4bw-ci~i5>ED+wSAI=K8%ll=@JML`@K*s_Fq+F{dUymX|QY z%C(kKyD>KMt>vm0C|PJNPi?{~vX-v~QnInNwEBi^CDw|mpRvlU6<3OGZ)UB88ps~e z!dij)lrv&0YvrhKu-aHFRR6?kYpq=6F`n96D^G=39j%qGim^Idt3Wl!>SC=z)efth zwHm3eSUs#&qz>my)6-hTsyRK_%UX?9JFGs|DpS3&s;t#a)nV0Gt2u4&)#%Q&tUHyO z>YB2dG`D*L{o1!Cls@4MHLxZ)McV#*N(`z=pP~MVHP~9rlIf;l*78(yti7$}n~%Kh zQ`39`WPIbzb5k|?O7S?I*<$~i=-kqd_8L(WN+cWs$JPYTiN|+2Rvl1d&gUH2-{Hu6 zP-HRN|C#-AoVDb9v2Tt3QdmcGcHOTgI@cdb`rw*Syuo^SO&}*r^(p($qzD<4bN!(; zx(oU4TH1G_MLr2+a!n|VAWx_Xt{3D=ex_KTj`BF#PPLX&uVS5KEmtMzooUwcR4c~m z$=34K>5QUNtfkdqoMBJ3R!luXJ50Bh)asZTy-s3VOLu2#~F3oX)7*HHh&1-2k_slB{RW!HTq@oxC}3sT91tw&sWui5(yr!tqDrls2*c4zTP4oRl``l!CFe4 zO090Rma7^w#%{8fhmXZIx(WvO7JimmAN{$?xTPi(-}qQgt;EMeRB}beM-Ex{WPAkF zYGuYp0i)sGv=7yR(Qu!&P{gD)?za|qFzK5Iti=~m>6-_wB`tnC^_SRQrkC!tvE4)b zt7<}tnb;n$35Lnk_yG8Z;{j#ur3u{4bbc`Rzh%KuP#T%?`YJ;DJwJEG^Gpxmo@%Gk|=vvh3 z7VHG>6vlTe%hMNFhuTp1;ptWz^rnQmmA2{;Aze9FbgtE-1$hXq*2N-QknUL<3M0tM z+Tcb(_TZ;F6F~_P*IJAFEgVmFwU(=T)33W*i#NU~Ilx*HYk93+FCJf@4t=c0{W(*5>6iNYsstt#cwI_q>Jme9I#>nN=I~q?9WH8nZ3WgK%C@TOjg3YlD}Cr#n|fOD)egq;IY*5Pm$(tJNQq3M8mN7~#H~UZ&9! zBe;~lCqi+}av(!srL~m$C&#^et>vm-jDY(szYorNz;22qMhtTvw1%|W9rQok?gaY( zF58R0(1NRKLx}_LkJkok(%zr2$jJMX){4BZwN~W)smS7Ca=fp%n~e9rTSL4*Qma1@ z?|5hw=wGbmE1zw@T1zJejvVFu zX02Facz@@2Ye-{#QyVnmNaNl{SAQ3U<&J>NsVk7Ma38PBtE7bLJBYzk7wvG4T15FA zYso^0R~L*Go_74`x@dAq21!*`qG_ zNst#aoO?DvcB#|N*|Xg}+1Sk@tLgP#b)hhVtgZ{nDWUe~g0!|lw0-LIzJgr90l3m4 zTXMkeTNer=$bogiF@ijr0XL|D&s3eBC&+SIv%f`l<6JYiE)+(PBkF>i1lg2>#Ha|F zka`ZQ(|;G_Zk()!Tjae=8phUz!U*!vy5I{z-pP)4nDt36>_^zxq&K?@WXRlT`+(Ws+`)Lkd9q-q1{ikmQok8ZED>g3!F#Q=_7=-GcA9NWo-@J zw7O8d!FqaKaHg>SNX^eovl7p#b$Xc~Um%_t7TJM;KdUYjMv&*%1y2dG7rWqvX{369 zA%9Ui9(d-~=}&}bH~Q)v%QKs4)V#V-_~E&tE>IjH)Lo2&zomIVURI~uk?&5RuNGQl zA2%Ome8tt=5tg!ICT@s2tkvervg^CoT4XwLBH4pC7cAuZA;# zS6NFu-c_gLICEcNU%cCT96}u*t_vj+JU&qu>_-VDAJbcFk&fB|&pK-{EeEmQTArFu zOaI+kNcU0lX={nc$LjQ{;<1Rh9=9Gh!u?ELD3RdtrMln_@pz&flr7Rx_tOrqT1zR1 zc6`lRvW)wDoqk?e=hBBSSk^u8@OoV+-eBEa7j$P3s*~vZEg9B6lzBhH`aat}NVBRQ z6#vj#d=7wZTdn1*p+x+VwWL;W)#<${?j~sacdY+YX@^hhLWv9iUs5aazm^hTTco2F zviE#rEu|JSlE1ZTH^mR>M#B;hv9SU|2xY3R2NEI z_;>mS9*w5D(n4hD=gsX6SKzO|%Pf2q?lVBK6WzggCgh&a|a6mPKR^$lhV z>jr97kYT-wGKCq|>xrpRnpJh>I8|gVPxYl%#nxhBhlm?nOKKJL)i;R$8I1O@Z*=s3 zf-)t2Lx~IjE&B$Ki2v)^%i5$_K{oBHh@f@*w zM92hFe7+aexvy@H6IZr$>08=G(ldy&SKn}F(oP;Va3r_I5)w|16wVWGyJqsrocODK zCJ(U>e{bqjT%{$bYo{4RvFD&Nz2otowYpe*+t8fn_bQG-ZLwT=i;xMmWMEVYI&e?7cCD* z_A<|Y-%w%RC@D9uwcJ=?BI&K=5y%SjTFZ)vo#%SUs?zeDVzriM4r{bLKUim8bonSM z)K|;ne!FUUJa0EG57+h6@@U-d=GB+7N<*G9FTFIaG*R`}@&Mc*Ef1^>Hm|<)t~3=K zqC2kuuEV;yQvf5i+o(%pWo-7U4b?I&cSNs^wIi#b zx~QY(p1zjVjT>TX+0df8_@55vG%fcqZ;jnWsV>!~M{bL)!suFE{4kK)wcMLr9oq&yX__CJ!bepx@WqVJ{ zJ+duY?r^;y`-(zKtBcQMNBSTxH>*~AxxbM2aJ6Z#ClN~KNVDFH%Z-m`ytv%S*y!cP zcW1w@DQ+g*UR-VrZ1!^BBy+c#;#VBFyxg1c*ssP!{EHWt_3PifxGX9=e%!1A`*B&) zb^W-ko_c;<7ApB}psXHhEdIp&xU8kc{kSY!CH%OoB?Vag$?@Z|vJz5~Ke>MHcX)4B zYnndKkINcFz8{w*gaSV<>j8y+TrScZ@fl4{7o(z*MSfhazl;6ckj%qsO}LHyxLh!o z_;I-&E%oDa$yes*mQduj2-g%`9sc~dTv|2vbCYa)Cfe4*kINNLOFu4`FRlEzT#K~! zbGuRGi`wE_;~abZxXj@D`Ei+&@9yVTvaMO2@t*SIGTZL&=cdT)SZBt>06%var-M#W zk%4~hSgg)<#ebvU2KjNBWY6^DGGm_Q=iWs(?iQ6i%g31AbhlSr7Vgnft8r<1!(6 z$dAhm;$bZQJmSaYeEO&#mlNP)eq7E&tBH(1?faT`d7L1yI`ob947_7?>|1;;yUvq- zTuwiZjy~!!ou)D`*xbjrGfC%2hWXsbg7lU=Cx4D?k&MP8h^}{EIpO$zi&XG9dAyZd z@3cy_m@00JYVt6)7l}Wz4fI-$K72ZNV$WE!?XF>A9=S~fP?NYkMUKBon zVcNk0r*&noPlZAVuvaQ5r$nN@-sv3yUGdl>rS}!!vGhkz3p}77rHHCEO-j!bQcLi8K(iz<#*5N6wh63D)5jesE@8YO4CKU=Hz(Z0&Q%ackza}(rd0`50FCr zDI9*Ba5$NMIGi-9NBri7+gRi&43A~sC<`ZXC~e`C6k-_Ur)LWCMp+XNOX(^V9?N0U z4Oeq2^TL5t+Yir$MThSaMa(JMM5}n;dg9Q0Ku}oxo$e8qS?z_zd_XWX9}o+}!crfeR1>sy|z@Vur0CN7q5{HES9()i02E+Y4Ru~=fwv~nN|cgFWy_y z#nXFoOpfR8CuLeoZJLRA$A0nSq~PHkM)r&M6oSHEX{i0;d(y-lT8@Ar{!pw?tiMUg zDNG|CiuIC`#ZvN-Se_}_Y}wA-5sbYeW%}dlidc(yt+9|$-c3I|`Mk>CN;c|mbOD%5n@=Yz8OlIIu@n#FB z@J#VK8BXDu;#Egw%; z-tau=b}>B7KEPPuzMsxt;8vRa=8w=B-U?OXT$f-_I?CTQk9mpt*yCspHoJLTannla zFDlzlDMufBv>#ng*pEF@oW}$B$$WP?-c=F(wl)mh-c1jaE!%x{xgh$EBbn>iR(KxA z1m7K!`w&L_G7dpQO^ERcqvXK>GF7~c5w*7@-S~uq*yAMWIgLIaFUb0WcQJGN?awo8 z`C}#7fspoz&mzf3G0Aa9ctWnFT+t)Ai~G|_dPDL>KG)kFO2<2444%A=40YGratImT zg+P68D&@8JEM;O|i}7H+Jx5C4Bt|gh^TzO-;~m9N554>Lcrh2AZrIkYdJSnYZF#_Fk`MPj({j zLa@!fIAvOR8}QZ28ws|x=Mz;MuQN4IdXw4O)|&@gJ8uZy+k1sHLkI6V%1rcDlRnIQ z5A1sHP|E+^I|k;by{D+%25&O8c*Z*%&S$+i&HkLahLYWsx}89~D>aT9^iZlX4YIRR zPlD{J)ITVGiBiwfR+lPuC7G8gb^ig3H>F;qH@-jA+Flt z=*75dMJzAHRR@B2Ij+v4cm+D4J<3e@+s#PtQL9g*Eopf0AiHx{TEL7ZEx zda~`jVzmW$VJ9`7erVK5U5SU|OVwkroKUKcA&3)8m7JcYl&T@rVQQ)RbR5^%rK%TA zFs)SmM)RCpsv7g>lu|Wb8mmKw^TD=d;9#^Y3 zfDeB{?Mi#@^MuM}FpS@(WX^cVHuV;658b9Z;da6{^&xeixJ?bl?P1&0%alBPn>von zBeuCNEq^@H2yRoho*;>>RPIDcyh#g8kwjM-W~w9 zlEj|$@>!CY3iE79BnWJdBzh72TuD5S_p>Fj7xA1UiGIK@J($EAa^_27BMp9;B(A4< z7D(a<;0q$5qQ^B|-o}v*Fl2}PC0!iFMr{+jvK8a8g$5S|067z7HCy94J$tQo^ zEyPnGiJ^2`p(GY@v}`1a>G&#=#25x{u_Oi(SYt`tN^3MRW!NN9y9a<`gX3OG8}i3- zKg2s?&^vd#9^3A?@C z(FLS~-Kg$?9VNSo=w0faVj?OT>p-*K-{)OmvBmVl{ku(pGxq5dBuALs7!7y-VUl!8 zejY@K3u7|{m;$)4%?pxWT19OB@u8fFua<2~u#c}=M$!r2i3c<)4|)Uo%bF zg`HNWDZLrj+iPZQuamL8HioyY4aIvmrMF;ePHD@jc@sq07` z#XiTsjg6wFt0`cFnx=b$s!G$HN7Lm*pYzU%W_UT#3@<041zFJGbKdb9GC~avT>$tj2b*AYUCzSBa>;Sfif>M7jEv5 z6KD+I%*uQ-EA!2)%r~<#-^|K)5# zS($HUWxkn}`DRw;n^~D}W@WyamHB2?=9^iWZ)Rn_nU(owR_2>onQvxgtOPPE^UbWx zH?uO|%*uQ-EA!2)%r~<#-^|Kv zi1S&ngoJj&(@DoA!)&=Jy#?KrD`bmgn4g54YS*PV7s$FCn3-h0na+$m@ePtGF1}1> zmO9~P(s9W!TXGWCc`GOUS++=q+0s6}CEp1fla5P9u8JoQ;jcTC(|M4L9^!J`YY*of zZY|$k$F{u4;w}HYLN9q15Iupl9-Sli5eo28l3a`FPMXL{ zhvjkHW%y{8@v#rvA=Zk!6S4NPR>GY!iIoy-1@01X!>pC#4#3*mTA}+i)^Ka(y4A$8kG1mL18KpL z){@%pnp{I=v^ef(Yr6{gsAMRuKy437&I_sS_hcTNY)%Z)w?ANwx0Z4*27HLMT=!!9 z9cnGl?T0nNTE4pz)?wC)xnF`i+*)z>OE{0PR>IwbCZA-jz`YaPk=Dv_UjjGTTA@3R zZAV!v*S!tJs}ElU;1B#_n(6F0odLEBpPW)+%+&@HgLD zW$wN-@@3X)>Q2YQ0&6vM7gKVfwVJy};Nfy>wQ#S6^9pOVbngTAH*2+WcV^pF)@tqK z`BRe@(sjC=>}km|={h|Mz}3l6`kcPKF8P@B?LsndusHTxBD>LA%B?1ro2|uNJAX-X zvv9gVmRZgLq;E@x;)|o{JxR@FvHKlP@68-dr_yHkTMNYsbyu>ZTsuql-S+r-IgVB( zLt$qhdotNqSO&qeF4{NQ_wwA;$#H^PFoVw`*nRT_!d;&Xg^wD&kd%vZcPPX!MNtP% z(ViomSCTW??&P(3Hn~(7mJ{>y$uc>8>5nPADH%$>lMw#p{5NNZIEQ?U$?K{b`Vo8r6{Yf$`BORSLCD*t(m^FOT3Gvza zkId4UzNeDGIIh;qtipUbV>!y)U~Qe`3@@t=^2yFNNk$9nbmoDr zWbz^k`zl|~MQxOMVyo5^XsgWgS#`O_dZQZ zx8y|YSu8imo#?_nXk|4VpMJNltZ4XCj*#>w%Ck(vh;aQi3^32%mvX*;K3ijcF~4#D z7|JC4sgw!)u8fKte-6K){}5Yq{a-=l`5`$4PQkep^6R{Hgi`PVS^n;g>T%Z0-;>|w zqxfkd&iQ~GzZ3ayXEZH$hD&!Vk`k>%^i&@ayMlD%Ki?W4rcdQ?0mm+TSD;wRvWH?amQ+Asb{ltOF%nv!=6{YRj6= zNBfw8*;*EtNf9=*G^*qkDjACQE7Y+5C7Nik-U| zLlW350&8IcyZfjpuyR>ejTW2oqrmc`#ismdv8k}ZVpAfs*u>XTT1xLXSZqpU7Mt>; z#iqh-Z3sNlj!R?~n|R3Tae~T^7Mof|H6e2ynWeo?C-!4Vxjl0efG<6pw0h|je$=~1 zldZlX&5MPn(k`kgzgl(UH>Ns*imPgV6Y7as3;^{5zd33*wuWjXzq#rNe)H4}e)H8l zehbuf{1&RWSuAX$?my0PlIr=%+^$n+&!x9jFq3XpDR?@l#`x{1E;*4W7t|Okvy(cU z*t)3QDcMy$bf(;odyivrPvsxUG*n$qPL)~>s#;AazgAtvZ=Gs$mK;5LgWX*X{Slp1;hH^$V(u#HwL@iJDuPYdj?-Xy96 z)K~l-sAS9>q+0SjPL=a}u-cQ~@#z8h-$6}P_Y(6-Y7MP4OJ-vfsf&sBYV|4Yvsk@EJWG^3g0WP!#Mf==E5^p{ zYB~LKhdP3I?p8DTU7`NQ?>%Y-zbn-(jLdu0)5LtA%7OWQRRre)>Pk=#s z)oKO5kE;RHWsMrg?-S}|exFpA@Vi!h1;aWumYAPXw~(`5b;A4K)gXSKR(r#J`@eUsT`o`;t0^G4`?=OZpYHl=Q3WL4IFT zXA|cpbtKHMt9JN(Q}yTfEwzCfy{$gr_Z{^szwfFN+H5w&6~wtF8 zp_=kSe!o^b5$8ARM1H?j`{VIDwHLm=SBDYp4{8?JAJvuo{-lm2lAqNhr2naswDT{j zn0o!H0&4M_x&-X+-rf8<${WoN%$@8(jCWUghwz72qNel5SKf^fYvrw^zhcVUh2~2r zZv=k=<(+#vCoAt-v#WW(lX;x-#?UmUEAKe|oPh^+ zoHLbIPsy2B476Fwn?&8uqGB}MY~^()q&do41$?gZw$i3&E3Yw8pQF4F@qVuIis_Q` zly?mQUZ}ip=z@!s=Mc-q%IifP<|*$c;PaJt8U8L)-YmjhK(o@;3zavNl9%%-2FMmE zZwB7~ro72i^GfA4;m=jdTS5?56E#&?ti0KD#}ei3M&?rGbtUR$%DWGiYnAsiv0Sgb z9#}Uh?7PE!K^{A=u3p>&EM3>w6aKw%T*}2*=-|iUvu%URqqnU#VHn5)uVYLaH3lz)s~KnZZD8p=%Lh>4apMEh24WT(ammSGGvTA3vtdgXuCXKi(pnC1Zyl6WW$^LE?Xr zv_b!n&J3LJBLPZ=scxej>pRY2jF`da0WeMqoWSA}e(py-f>?vC$!))0DwhrX$5MVO1?&c|0k9xV=Phr zD79^{MCsclN@)dZdr)$19<}{{VTm%v66IDZ<2P8M^z9O*w1T5qqFlyd?thmk?K0H= zf0ig?EK#nJGgN~mO5ZL~N}toW*CoG`zWt9cQN~!JEGdMu!4jo!mng*-N9=o&wG{Yw zmndT_Q64BP4VEZ|;+RWhrilCCV5}lnVscV2RSVOO(P#jb2FJE4b~JD9ip> zqKvUb`KmD3B}zGc`F4p?@|{5VxANbd9pW%5_|>hG<~<}8O^bA!q0_A(>148ai%fA;uAGqCC^P@jwNatAeC|Og>XOBe za-M9ja^*PQQ<;g59vv0xrQ)KDruR!0KS811DpwAF{ZxEk$vq(|lu~gKM$;!Ii+{mg zf0ZjojioAA2H5o~{(Unx-jOW69)_D$t_+dYDlRH%`r#=4$5mVu()1${;TjbeT{Qh@ zviM*s`=rX10pYlDS-aFvM}=HBF5+l@PC>4q?IG3cJ70wg6lvx(xd|5!f zD)qVG9+<&fau&BcMXpPQ!UyiQlx_^}hnZaFq+r7`{)owZ^1$LY9?5rLQlapH zyD!yOaN#jr-!#CjNR1O*bLzg*;s#OoRjE+;z^zH0B)BPDwLBT&=-Qb7XzFsoeabcB zYK!}RD%UruQ24+-o4P}AGq@^yzJb5Lr=AnsC-~c7areOSLMjwKaGO#e3hqX(WZsBy z%)Dd%%c)osaIxc9=&-nMTu;4~3WX2c`>B=`aOcx-A2#s!ZfaM-HJZXAhs7OCdw!G( zg%8~4srLl;AYAY zzWLTdst2|LYvs5dXu3jch3*BckuX4)ketnsQ z=syIYNqs1FqYf?W-C<`(xV9nhve6h3gB>YJ2W+)fQ} z?dmJY_V>hJ2a7vr8q2!%q40s*rG97{SKa{Ez5ZCi?E`LSi@Tjl_pT3x4_saST)}-v zzwc`6CvjHQ-zd0g44fK^+jcUC=lW3i!0l20h~Q3RKiabauD<>q!JPqafW=)y#|^0u zg%8}Q`tJm{nIJ|-II}CkNQZ1?J>@L#lWQTgvj};Mp@z4u!o7Wcflr zoGPBlma05C%=OEYgI51MIRp*LlLN|Ld2)Cdo+mrlD5Hk0OY4iT1TiL02JG>9GW@3I z$zVFAKo&K0MSXEg0y`~N28yF{rQhX)PO@!ieeo|~6P%FA?WuC5lX}||{o(b+l>n<$ zu5`gtd%mAiU%Vd3^(t2yc)2~_pIKi#g0d@Bt~8$$i%yVbWSNs{8z+>;Nl1n{b@obc zY3hV+Ws78(Ekj9|MUWy^H0orN

    c^g>Wyd_oN#Ni(kOStEIA3k{{h9Y~ypINNy9B z-qfB-4rfbzr&|E3S=f%cr~^OByfLcI=p<+T!uI@$S9voj6r9Y@TK?O)SMq%hB{@44 z+)Gwl$q%|Ff({JyPyQ$qzD~N`GbgjLXG_VC-n`6d&Ot~VJM9M(PM9>@BKg)xoHSa* zmPQk0d-P^zO{RQ@Plz7C>@o6S%0kKI{Gs~JH0AsTyEN3#0V`hH|;u~ z8{M?Ke*}X$x@lJs-L&K7Jq@Jb-`=zfYREV54-{;F(~h0g3HFnXOpTmeNfm5==Wd>q zU|G`1<)9(oMR;8PM0f5=qdRwGt|K$=e10C{fByCSC@1$e{sfX?w!D(wqMck?#|b1O zZxTOWq_=>1SGGuo!36Y^VRN0_pJa<<{0DyWhERB58VqfP;3UJ)j!$pNcXEfz7RfMM zrl+^~PVQvcA{l1Og7lV{lRHPYNQT*RXL<|IM=X{tl3}Db-ysqHsq`jOP?lop=N+Us z9{|nma-=t(_Gr&~Mkdmm(hJH_q8yI&rm-^8o5spWZyGBjy=knB^ro>g(woN0NN*Y| zBfV*?jP$0lGSZvI%1Cb-D)gu`<$|#>z-<8Y?5cX{?O&rm-^8o5spWZyGBj zy=knB^ro>g(woN0NN*Y|BfV*?jP$0lGSZvI%1Cb-D)gu`<$|#>z-<8p}#= zenwBGr8gx%ExjpYfWAh0bBs^_Ze%ndy(uL;zT$+1^ro>g(woN0NN*a8?~&9S=}lu5 zhE{shSY@G=-ZYk#-kgrFwDhLryYujb^rl3~i3sV<`IHE=NN=tbWESa7VFZcv<};+S zNpF5G$m{xY&)P}>TIo$;WUoPbv#kdC7o|7*gUKenDc*<&>CFR$HH-A-8G@|t#$9O} zkK2>?{VGCX1c~(K^@99U>CJV*lSO({_~Ai%^Bv*IBE88e*~uooDU2YI-Yla;HtEe8 zL5}Uhg`XC+e>c>KRifp&JmtVyE2`N2(tAj6HfGlPSEV-@Ev#{O=PC2;r8mVJ@gTi9Ojxr>ZyqnmR|fKcxvhzn z-V{cVNN=tX`jSm(wn0N zd3-Iez1vz^=}ln-iS*{Ng3Kbld5IviNN)-wNTfG!7Ubd{Jhu~#7@FKjZ$2%^EYh38 z2omYdErQGt&2^-5#Bq*rz=rhZJEXEnZ#ucK&8Lrdklqvy zkVtQqQ6ii4W{n`DJ(1oVPl+4}I7j&Lg!JYD@zlOM zk6cHwFz5VJ>COAZQx@q>;fEFJ&27T^7o|6Ixva@1y(!*cMS8OzCH|`P=Aptmn{(F= z(wpLqRzZ4m8mSx!I7j&Lg!JaEr2eY(<}+ZjNpA{2tVnP2wF2j_N^iCWlTCV4yb(Xr zn-!GEk$`iAA5Tbc%I5(7s`TcC;wg*trtoupg7oHUVYSkmbID}3V5K*WrP9)y#^PN* zk>1=QtX6tc^3&3r;*D65-Ynsc%wLt>tOAowdQ-f?iuC3RVg0`%z4@}lmPL9~VkS1E zH$RiuvPf^{7lF(oy(x_J0MeV2SPDu@Z#L)wq&FM%0MeUL52!Y~@GP3OGSZu7TSj`* zSQ+U}V`Zc_jg^t!G*(7>(^whlO=D%GH;t8%-ZWN5dec}L=}lv0q&JOKke1#wRz`Z$ zSQ+U}V`Zc_jg^t!G*(7>(^whlO=D%GH;rYbH_xYK)6$!g?=I}e({fdz^a;I&^yYGD zdlA+AccnL96dozHgY>5G!-MqZHsQ%4y_w5$ayIErVFZcvW-m(ox%B2J;Yo4M+Ch3# z_~Ai%^JwA8BE5OBAhSqs3L{9QH*XYV7U|9Pg3KblDU2YI-uzsULkF<{n-)mSCcRn6 zGP;{ZdQ1=aai7IZYX|8~xv`Z^dQ%udBE8v} z5`QkeIaqkm3)xY6)7&^S(woN%&!0+f&KI66(wo9hJV z(^whlO=D%GH;rYbH}@j`wDhLryA}Oehp7&w=F|}B&8ww`vsr&bdeb1CwDhL2GSZvI z%1Cb-D)gu`<$|#>z-<8Y?5cX)Io`sN)=A z zQ}WZ&o6;wop^)BmThR9ZLg~%+@MV+Ult?%NBE30AJpM)L&FR9LMS4@b!HV?ed|}NZ zy}445YwMgHr8k8UB+{EbT7q23vEYAPdUH6Qvq^7C%*2ND=F<|}=AE7YdFjp1B(^Nl zn-VjzA-!4GO4^O1)W1l2a~yoxq&FoJJR-fhR6IV$apFHMy}3qw+|q|95v*vSmEIKJ z_&|EIt~EX$Vl@1ZOK*!;FT1 zk@V)#@MV+Ult}Q1^yZ!7@xLU!xlw#%k=_*F_&|Dda1tNwcH%iYD~#zFdCUI+>CL0@ zoK1RDVkS1EH@Bu^`yZFyOtdAoEYh12GqEAPSx1S#D!nN$aAlL;6mPI1y*Wo%o9@Q* zG-=s8Rb0dQ*IJ@NhxF!+!jnaMQ~2RQdh=1?$s)bES&)Ztbl5?9Qy4)az1g!J$bX^q z<_P$*NpDIdctm=0vUtoQy?LP^vq*0WBS@q-pA+PNNqX~3@sUM(Q+(qC>CHrYd>qEv zbqDFqF63vE-V{cVNN)}o|!aEYh38&!|Cq^EpyE z5>$>b!j1Iix1UeM=JbJN^gSuLwYkD@o%Izzl1xR^rpmtcceG>>S(?HC!{yUdq#Rwyzd~rc`V%7 zq&Fohyd%ANHYKu2Z{94(EYh382omYd)q>0-y}3n@S)@0G5hT)^KMOL8^k$1rAhSqs z3L{9QH&3O+e^z=k+)jEk{I}AZSBd*9(wh<%?vdVnT-^6%N$cO0-h5wp+U?4te33Yu zTU*bCSY3heGYFC1{DD-C)Fnq4;YND1pflVevAKiv<}T!Clim~#kVtRtDabvT;O-#3 zd6XctNN)-wNTfGs3o?uJ<_&_(BE2b$Ad%jDM37meH|6+{O?p!pK_b2RgCMg=Z#HFy zkWG417(pVvxeFz-NpFr6W|7_$Z?Gc0dB3op#NhdF zk=}e={AZEgl(_JZ^kyXk>Az2Ub1dxHq&Fol{3E@2k@)Y*DE|x6o1#XQO?p$j!HV=| zUJqC|@bljyy}2{Q*`zlmF8m|Cxrg}ABE5N}Am>qR2kA{=1c~(KEJ1EBy;CGDi zYo#|=N_s{=9!~EYJ}6ity(ziH*JC+>6wVWG>oa*xow)mIpWyr6JlQXAMk2nsi=wQS zXQXq@dy#4JP4lq`#5cRKrBKVW&n>h(728J3)2QvuTap>^O?k|;qj^O#Bfcrmk9OAb zyk{3J&u(@#FH|7Dc|QKSX?YB@r-;{?SE6i(?8Szbd zy0J<-aX#v#<*CCOEl&{EnU^Uu;+yio->zC7(A!PR<8}SCJRG;Xd8sljzG>d2M0``C z>aXPyxItPTSsQHLs?3OQ%Cl&DnKvub;+y7$%8dA?JV!R%yi}PH-;_tfMre7wYovLv z67kJWwB@L{D3xZ!H{~I&L$o}Qb!hx9NYdh)@iCM_d~-E%P1N$()zMlWcsfSQ15C$i zd35MFEf4M-ujN6U6XNYySj&iS$`dwIwLFJ%l9uO6rfGTl;$$t)Fr1?0nS@j0JpiP| zH{(`(vn>&xrse5^bL0Klj`-&JL~vnzJMm3_@>+^ zUlh-yY({)jZr?7}a`SbGmK&){<7I5lh;Pb0(QD)F$U=N`2mxKEtsUMToqyQ_)#MY0=+Db@C zF2i&E#CGDFFiDc{{sY$v`MllgXkKanD&jQD0^SiSRy_-0}(7UG+tl|IOi$uxVWACo!r zEI)A?xMO7f5&lR3o0Se#cL@ndpEebkT1Dey5rCTF76equZE&BS)%n~6L7(`J2(4NEo|9WhI*^QJBEISN?(4}(ryzRwjJKWS z&9mn6=2_gldgkqve>{a7nRm|`nRm|`nRm|`HF)>TtMUd=C~pE$Tu8!1!Q1Gkk#5oC zTtOfIvKx!S-{J3&YT|)9yh20D6n^iC}--(P~2HW~Ou^v~g#cET;u}LF)WH#~LKWRnf zk8Hw@YTg>FJuiA|tjS0kDSB(njoun_qqoM~=&dm~dOwW!^t;00Z)+oM+H@=~^dNpv z-hEvDY^TLS<~oyU^jBbzHditFaL%YvY*3v^UbLS{{zx2`jx@<82JW9Su@`)(3f1sj&w3JITLC$zlp@h?1R1J{u)#aPfQun?Ull z$lDTNuSdBnNWK{**OGiYN^T5o<{pv6h4pYe{q&M$ic( z){-z{EeRvmlBn5}{Wf95S`tRAC9wfttrAA8C1J!`5=N{gF&T!o2_x2$Fk&rlF)OXrL8XId+h{znQ|iuJvWljb0Y~o_hUl4Lb;KIo*PN%xsimP8%gN7k%XRm zH!S~$x%Yt5syP40?=y4Dd*A!E-DTOO?^1+adfUP-3WyCv0Xr%dz>bw*SL_XI>_o-h zV>k8|QDZb}>_!t~4+?4&V~hSjpP9KY?|RPHljP)=^XDAina|8T&pcD^+`0EY`=Alu5jyT4qU;fR>RK4Kty1;~J!Oy3Q}zfwWslHPr^A+ywX#R(sV5=6N-KMWp0Y>i zDSL#TvPbACdxV~{N9ZYggr2g8wJ3Xpp868i&hpi84E=0h*(3CnJwi{7+=)l%spGbV z!;-Jo%)#Fh_{tukr!Jcf=1^bRBlMI#LQmNv^prh9Pi-;_3mnLoV0CSv=1k-MPfgtl z8^A!>BlMI#LQmNv^wf0J@aI6;BlMI#LQmNv^prh9PuU~%)M+sHg-8v+fd4U4ePPRs zk+MhVDSL#T`VQ5;5~(Ml^VLY%BlJ|`OkD1fvPbBt=V8*liLyuNDSL#Tx)B1)i^?9M zr|c1W${wMo>=Am(9-*h~5qioVp{MK-ddeQ5r*_^Hm+D}3F>2VqPT3>$ls!UE*(3DS zbhKenow7&hsWF(%i|dp z>=Am(9-*h~5qhc{8aCxu${wMo>=Am(9-*h~5qioVp{LeGf6n@?%3-$dyiz@drtGp( z*(3CnJwi{}BlMI#LQlPflDn-``(eK9zA{wkc^;t`riZnJ>0vEldRR+16dl7O^g=-| z@UWKf7+jt_LN81YYYFSn7#^V)?u#-!LN81YYYEfCTEg_OmM}f6B}@-%3Dd(`!t}6~ zFg>g#Ob=@b)5BWAMQ9|C&0vG5bEut1=!NNFE#V}X$|Ll`^stsNJ**|X z3U^8#p%g#dI zSW9>VdV@#kh3R1}VR~3gm>$*=riZnJ%W=o#5qe>ISWB25))M|1D>Lpw*yQ1s0T(bY zTpt%RkI)OthqcsI9M)2E0*do&mTs3JB3=~_YsoXgU2VaXtDk~pf0NsJ9LFMG34peH96y&JJzlOR48v4~3e zu>GkYoX;|xeg&3BnN@y#4a=|~o_=q`u<9wMSf1&@q>Y03IYfre#B!%M3HtrT6s)-& z0i)&`z~Lt>QKTL_(l;4dQbUi4W{V&itSoCjtt-JQ#36a2O?-Z-SJliM zCItSpru<%rm}_a%CUa%u{8FwYGaM>moHuNWm!g#32I(6&+3WQ*bna$N#i>X~k8IOa zwK$JqdHf~}OVdDiy*>>z$03pDfwp%@$tyrRIHcuGpdB6Z;!a>Ln8Bm7CEHk zhV!xQa7fFZ$Xo0X$O3>4b|{d8fDUmel-D75s6&w)g1o~V%E+IQceq2b9QP}{&vYm& zrvM%4P$Fjn9pz9?&I3Byp}Z^uTH;VaE(bcsA@;>SP5GP`WRfZXEzn85#4`rQ6C zr4A{1ALufNw0sP-+#wwC4RpCff&2sL3Wq}ZC(xA+Mc@ecysI3_2#@=?+M!r(#?V~j zP*&~)y4ImY?gzTgp`3JJ#k=02ygY`y8yqUg?|^P}h~0mFQ+@zis@X>uHudAZMi*ey zO-(iIBlN``O;vfkik2hLTX#80PmTq;+aZyYfqvtVk~4traY)O#K=(R?zhMKq&!Iq; z1KsaXDAxcz;7}wt0X^tYMs5ds$e~!CKOL`B9Lh=wd5<`h$g9YE)S;ZbjkWwShw}0v z&~F_o$ZDX+9b#YH(v%;GmTGPhZgYLn0c|UqYS>4ZU*|T(8=yqQ$>Bxp7S6cvvJh!J|J zsYs3J{kNK`POFBVq37b()-=E^ilc$vc1WZZ=&uebnF#cbLt54cdeF`^r1r;*#+n$hhkZVrRr}EW#tN>l@29xJXeNPaMk2Z-7=g zRFK=TNnGs^d;j&O{LN^oW*_~jsh?RCZ^2^xX;TgR2z~KYQ`H4E=!^M~{Mt$4FHeEK zaR`TN0DbF_lEpyZIi%$Xpzj@m*EG;S9SY=RpdTCxeMT+@5{F`W z1UMUE7@Ao(rh4yF;9b z#pZY@O6h$t6RVo-?fFa8Ue{ctM)ZC|b5$+g6Usl4+P^uyJ?rbRFLFpE1{&y)k|NL` zhqTlJt>cg{zkxM_9SWou@`gARN+VE{Ly-&yYIZ0i!-0l66w4{FWtc-*ISXjGLy24f zG{T{rTnaSOp}brTG|HiZ+ype*A@+Xn=6ow!s@X?!uZrMUhlI~2+YzByQkXn|9&Kn-9Hp3)Sb$&$R8 zdl45>KjI|LL{yOT>PDQ7nl^8y;GjqJ_RS9>q6gw<$L5A-86S&LnA_a&iv$X4KFi|u zCsNIpwBY4gdcY%kyXJQgiI(99)AvD)q29Uqk3fO!-yCn4Jj{zfwU_aHItftaHj%to~pq_UJVlU$)L)iv;j&&%4p2M1h zqo`*YN*&?!&>!=-X2+)~r!~h{rFzcjqUX#CJts8>Pf*X3u;&z~=N!~^R&zrAu;-%Y zn9P^5QzH%m<$U$V_}~SU(%ZI_x#jfUh`&2NIR)vM zjo_AB))Uq{Zn-5$#Lmre%NbPWmNTf#EoV@fTh5>|x12#`ZaIU>+;Rq$x#bKhbITc2 z=9V+4%q?e7nOn}FGPj&TWo|ix%G`1WmAT~%Ds#&jROXg5sLU;AP?=lKpfb0dL1k_^ zgUZ};29>$x3@UTW8C2$$GpNihXHc12&Y&{4oIz!7IfKgFat8Io3i8qT;6aR}z8Blj zmE-G~t`ET_Kd>d?9KcwETdt`W#@BJnnG$eQ!h8U?oIz!7IfKgFat7s!Q!KZfL8YSO zmNTfn=(yz!>J4iKw*=Esm%gzH_ofzW&6%hP+;X%M7a_Ri=AlHfE4Q34>$U_ZP_lws zPMv2m$jgSPl+$D(pgj>#+=`F#-l&s*E(~et?8gbQtTkZ=={_EUwzS^cGsO=4{ zCyd2oc1yk4XEhJS<7!L7+F%d3<%XlgPq^iL*{da>>xyn4R_2z|YLwxYqee)ATkaQ> z{5ftpUw+XNTtGb)+;aML^y^VA3H3t{xaDr4p03<-*t4|+FHrLDu=jY&{-sx~2Ws4w zgc>0UZn?iva=T`H-fCIihl2a#@ zx#jdq^uU!Z2{l3z+;TfovMaZoFW0pMM^o~Nsdxf&)*iYMoETaXYJ?=XZr*lX|*x%i$o`*5EcuR&dMd9vfn(-kMM&Mi1O_?^E*H5uVrB$^(e8-I5iP zu=TM>@E#LrkVRnzd$?Y$LDT@PBZuQ-y5*MBpTV(baBITaU=O(E`k};6xaGj6(i%*r zWCgdJcHDB*2uX0u9f#O|%q{0jOKWg7>(~QxqRsMA=>u`atlyeUMmp*Mx7_a$`&n)| zUp8(HR-u%x;Fi;8V%s*WHKBg!0k>R$9nw#@<$T$yH5iO^UBNA<9k(1cLK56^>rt{R zx129Kw+6dVvVvPqFCB-MeXR*KLK56^hf=aDw;b4vT7zYjtl*Z@?_o?2X-%jRlHiuR zgOXjj<-k?Z8ko236Wj3u&h^&}^w){42{l3z+;XcZ`9Le)X<0Tj&F$c6twFIr>a5_F z(`(klI@y{~BP78sHy9;;!Y${^g{|=>l&s*E)3;(JTi#lvMo5BNZWl^EH>r|a4({`q zAC#=%meWx14s|a?}V(aLWxqiJx%G`SN6Iya6RExaG9t zmZL_r0NirhAy#0;1?qq{aLXNl*iX3Se0jMw{w31&-W%X6z8jmPF=O6pEm8+0!7XvbDPzSVuTkadge!?y1%O|ZtuYu5Z z2YPR{n?)~U7Jb>8PzNNzEw?#J{2SbIzI@#p96+s~VSRMma{6P;Fx8f@HfRO6+||_j zuXD@ckCNKrC#ki9TTVM}Io1ZP;FkN2TK{!!Is7?NTil0FAggg5b$2XrZ{YsWx2?$9 z(4XLz8;ueL8eE`$)C6w11xWihxaGhT)E1n?nku;EH2=P3SX)B<&FL`=a%zj zbX)uuweE~LFxJ`s8m_F4wjyhTR&dKztplxdu}_`a)(`g)e7lw}P<}&;B$RGI8#%;# z;JR(`SjgxKZaF;{k{h=bSsO}#TW%wiDA3>n^`jr`zrihszgcaIFM*6caSGhM zo&A?jfXh%@k@}$(+;T5a>s}b4U964Z@oUB%d0yH62)l>*ZT+T0KxqH=ZSfb>`s`G^ zHE>!dq5TWmimVMKz%3UIhUql8K>er*+;SaA`!~4deA%-t*by?if?G~skE`jRwuJie zd;)H{v#Hf_%Pm17o<$wEoIz!7IfMA#BjX zkXn~uS9iK?A+&CXUOdwwk!{dpXFJ4RIjJp(p-^9dJHjb#_LauABjIt|masNx1-G2} zL%IJow;b00wt#;)rz^PS^sTrKuWn0dGi(F5+=Gbygj){#>$ZS@IHxPP<@5?j-rAN> zBSrw+a_!g%rrdH%kmyDL+;Rrl5dgQGK}sCAoIz!7IfKgFat4*T|x12#`ZaIU>+;Rq$x#bKhbITc2=9V+4%q?e7nOn}FGPj&TWo|ix%G`1W zmAT~%Ds#&j)ED#g&bDBC^sE-F^mn^?dfp_%Eoc6iF(9|xG3@)Fl3lsw zzZaHupvQDH6_XPpBVyz%ADU7nrf9%q?f^ zS<5Zw%Q@{q2TJJ*ZaID6czp40PpBVjE4bypLy44IZV3{xwr+#r1Gk((Wo|ix%G`1W zmAT~%Ds#&jROXg5sLU;AP?=lKpfb0dL1k_^gUZ};29>$x464Ekc13&82Lq*F#LT#= z-QH;(w;WrJ7J^%DAxfm&az?VuEoV@fTh5>|x12#`ZaITu)c8<)a3*U!pcCJ#U5$=g zj+UTCaLe75)(CDnBk85was~WMHAFWJ7|x12#`ZaIU>+;Rq$x#bKhbITc2=9V+4%q?e7nOn}FGPj&TWo|ix z%G`1WmAT~%>V>}76N2N=vw9IOsbGS=%C5!^e&U3LV}d&rxaD4C-~V^G<$N_|La>H4 z9)=z9)CuU4)2I21k)j-E4bzKp19NQG$CPa&4e~ytfPWkPCITn){Q#AEtlu^^MB1P z2M%wvA2sWjaDV!>YyTa%pWinjq0O)j+;Z2`w*NJ^96r)d2>4-7S8&Ve=dpPIenLW< zVH>#RdSUzjU*eYYBj1iduh;Th1r9+`-gS!7Zn0)}W4r`k@Eha%WOcS8h39hI9nCQF0etZjM_{ z_eOkFM?#H|1h<^vCE0(8Th5oU9l-$T(=Xs>yle9uEd3jGB(wxIf?KYGHFo8e^JQ8` zup=caxaIWxNx08;B-98=aLZjr$^VpF4*Thj;8E65!7Zmx$NgzuN5Z;M2e{>4XB}O+ z<$T$_BlwPzEAZ}YPuH&bi0{{tP$MM4E!T*_{aJ1~Ulw)5>!Xye;FiL##lf3e*VQ;Feo~*w1py z;XJjD_(PP^72I)Cr6saFJ zf?IBVlqk@s0yRQ6xaBTGtoR>t%Rz1}w_LFcx129GWBh5+JgkYgxKaEbJ$PS7LOW19 zxaIob7Hw+(54h!6dzo8~wXfxt!#$@XSP#1OMOgJ7cC~Ma{&*U5$kq;SxouG5C){$l zcXR}YQnG?uPOpIEs~rh7!ftTOolVKE+;TX-ts}UDk`>%?`W#5U(~(dkB*88BdrEfY zmc#RON3e>LCu67mp|f@rX2GhCgc>0UZnXv(a`l{~WiR52Eb&PU@-PmeY<~j`}eP!7cX`Vg*^o={9H? z*qKlxB*87WB_+FZ%i%R~XRw%(72I;V9rI;OXF`pT1h?E7lc$CdrF+;X4}?F^=(l&;{G)5qcC-I<*U^+ON1<#wQ+uH15zxT}gH~|MolLF&FSzA=d9yRPf%RuF zTmS6(@ld?3`dep0yHG#4H(`kT&#cAxbCBg%cCj2Cd+h`!luvzu=a`p+FM@4~@`=cIB2E7VXFBn(I3Ujvv>__TUL=ez>8iPziN8wlnrt@jpf>l=p>!9 zPT48DoOQbfjcMhcHM|8#7C!!P7 z!iY{y`$lvp+ApFr&;Ajea}J2fH>Xp=xrlBziy}Iw{34>W$>NAE83#vnY&ayMqr#yv z3FmamI2X4QEpDqJOWzR@oeoZpNjay%ImcdF8XL#m6WYvQ1)mksf#4joAJFHv8Q1<_ zM*RGLZp07m=fz~5)3@8w=STd6eqo%SgtU}*F5;)%OCx@my)5EK*5z?M^Hbuvh#yR^ zhzBqY%ySQ7E?gP$Q|Q$(ndfxx_L?VP>opNSa^4W%!g4A1Tznr9$mfzAZe0;SUp^9( zd`{13H}*dklYLHa)?V`|bUYsML*ergKl;58|B13G|6Ke55eVp3qTEXnKj*z2@nhUy zBYsMIC*p^&cjM1l3Ji2=Q~Y&YmLIhq(WUQ^2nIU#-s3vU??6xKEI*JuqqF?t@w_fY zlX3k|sCl2tb(S9x-qt0@Kz9=o-_xZo40Kt(=l(%w`SRKGv*vBFpXIAx#3j`?m%1>} zWw|}P+b?xtpv!XScaNXtcI;k1%RSP4ewG`T`~56;8V>;BCiS47<$d=dKg%2C!+w_c zt4I9Og+K!*nm@XE6h;6InrN>M)D8p&x>s@4J?>|DoALttC;b1M?*0hpZm)`Wmpl{9 zB(Fm!nm^CUdsPwQc_!46fliN`$U9SaOF##XuXO|iO9DEX3C(`fe3Z-_1MFoC{aj`< zEFvmn>F4SP4n~w#u0@blk1TRNeSAX|S(6WWTh(?^bJT+qLTeg6n2hT*A%!~My%-`^{KlD+&PLUlOYoay?!a#@^E>?JGk?KvA+rX*MRn*o z&@bvt1S0Bc1WMHX2(+kYU?x1v?_wW``V5JosPLDlMpSPE8Bt>p#GcEkRHe_3^o=PboQ%wW>M!r2tuV!KoBXl z3_(Vz+YrP`y?Z`8ReggXQL1!rkXNb$K|!fm2#QL5h5)+53sIj|y%8v_o?VVK zt;PWPTD=PtX!Q+(P^*oR7-=;ZK}M@Z2x6_Sy$JQ8Iwv*ukJw*`RWe{GQN5bLF}u4T#5R8 zmA?x0`Dy@yoUhsur0?B!T)9$1hMv0ObR94uV3Uu0v1^)Nc`BSYAgU zq52eo3RQrKtV4AyYVbqV3n&QHXar%XHbM}EYRV<3FH}1M#i1H|9qJ3!CJ2&H?Svo~ zs_RfBAF5vf6+(3yf?}vHM}YDF4FZYOvj|kA-bJ7z^$h|)QpM|0ABf8kgpuk%5JhSh zf=r}#M-WHqTm;!j-GCs8)FTLTAW}wdS_YKOsM`=E8TBNBTt>ZxAfHk9p-3U4 zo<~s3sO~qSzE}-IAhDW)K*efX1UgpxBJg8%Jc1xr7b6H`bt{4>R!<w+lsE}3j5EQfOAq*<6 z(T%ZANTTK

    EWEKqu-{1b(8HBM1_8H-a!x&mf2r^$vneqP|8DCu(=B8rei0i6BYT zFA?Mtbv=T7q8>(2NYu*+iivs>3j`K}gRwG5PQ3-Ba_S2NI;UbJ`Z?7PL6B495rjE4 z9YK^+yCBHq)c&}b=#k~3!3j~(85*7$4sC5vig6c$|3u-n3zo7O&5ERts7|pPtjsl7b z>Rbewg1P}gTu_H&)yNjq*$9$?x)wpMpdLh!FQ^w06bkBZ2#N)-?(F5zwzc$~fgK$0 zNb8)q2NJfIo=adzeQ7Bw>8RcY@jlBi!+hLUy>Q*#w?b`?pe`>n-z*q&euX$p4)4H> zGm-Ocq&}Q>vq@3mE;gdW7ch13&kqaGh<`!2J31Tx!tfx>M*NGyZ%;LmOn9h`#Nk6W zk`2$nN{oL=SYs>Ag{9>tB^MrvYaRdc;mfp*k!D+_5U!x*XnA<8O(}*eId!pp4O>n# zk*aVAZ|!)g8}5mf4*zPx4XsqS@DOW!x9~iS6aLkPXWEq7@b9=r@vnP$jZNtu7BE-w zuP!_Y%OU>NhmTsR9^p&2(jMW$HZ-clh9?CZ$g}2MY=Q^$8c*NZ+u^8rCn| z3D+S0_4OL>UyjZXSDt~9X!!Jd^xY?Qizx)`eg6<>-11za;pwFEf0v_F@F}_rSDpjlK-=s^8;h#H$#C@Vi2z2PNae zAFkaRvu*nakQPbxa{yla!Q((hseTv8kDo!0gxzgkCVq*iuT%>v%*8&sEnG*c2LhGi z3r`0cA=OiWy2W>48iXx2uRcDAW~^)TddJ;ZawDl;fRYXI2b`cYrTS!`f$=ZVyWt$0 zHzfWg^XA#SVetvef%dU^qr9F6MA#L>$m&P=quDOI>E%&IkA)-bpn_HoPnO<#En#(5ITy9vapJg5V@oG0p ziyYUr2%%TYGPQdlT6YF!P`FUuV{=YNLgR^Cm!i=t5O3hfMPsei4ZCsO8duE>4FA&z zM%F)t$rFv&mjbNw4LUQLEWIuQ81*WC;$6Dc+>eUBN8D`kK@j)};=P{7^?6VOlLwQy zxuf^CFq`{%Z!npjJBO8V@39!?xJKvqM^f(Z7+8R|r_q1Oq?-Y1b%9-)_{#yhTQE8~ z68hr-x~J)FuXk^ZdHj{iUkDw2Ir#y`ayW7eFrxt`n}WSJpps`){!7-i8WR~{1NLjK zg*nfv4cKkDaRh&G;HB>Xo>LoeT#^o|dqG)~HpMCuzofcRn^#K;ir(AOkegIEVmqk0 zg^jsMjpiImZpGCf->JHxOT46s72Kt|v6xrO%c@6rXkM&1Bk!T?KUvXYwH{}tZP8-2 zooP{TTzAM>XzV%UU4TPXU&xCa#;=yWc(o;_Ri8`6FszY^Ir6>O zInrYiwBKg5-%!?mn{=+#e!FxU?H_Z`eus3Lt~Cw0(}Lt=4)WbjyXoiOI53D7-Q&Pc zoIm$EV9a~KnP+D0iqxV9FT&pg8H+l1NZWguj9c5!hskE9pFceb3J;TA*G{`5ox&Bg z^#rjqEk`3xbimBClf=%ntIkKxDK6(yR2!e_fU)SJ)S~@yRn0OM-C4G1mW*H9N3&$Q z=_7M#&ytqX)B%`EJ76KemoJC~MTpCbBMci#EE z{$Jo`u!0JoP8F^&7WLy|wPGfhDx>8oqs8lg1**J`;eclqz=Phx4-ZISREq{H!3(-9CotNe1?;=8!mp5|Hmy38*&jDxzdxkj6eTIX9#KCC=~-;q zaWi2Fvf=B|J;pNiKBls+!pa7uj_Wa*sn0X@P5ji6>OLY%yys89J;JZyy7vv&y>Gbg z{dabOpuZG165lsm_rBq}_j~V5QNwlb8?JlbaNYZc>)tn9_rBq}_YK#*Z@BJ#!*%Z) zu6y5b-TQ{?-mk$m-OcBAv(`6U_rBq}_YK#*fBR0j|M-UM-e1aD<{Pei-*DagTR^s- zZ@BJ#!*%Z)u6y5b-TQ{?-Y-qZ3rpW{-TRLqzQ8wJ_x`SPJnwhD;kx$?*S&AJ?tQ~` z?;Earv0V3Jx$ebs-Agxg$Vd^(buX)6!dW7g>s~C^y;!b$v0V3Jx$fno&B%2xmg`Nk zbuX6dUS7uVy%mV%x);lJFP7_GEZ4nQu6yy(hUX(W4d%WOiRHQ%%XKf7>s~C^y?lpi zUx~zW-OHw!Vy{KgIFnrWV!7_+d6;x>B9`l3EZ4nQu6wau_hPy3WhL(6R~E%`-HYYA z7t3`omg`s~C^y&Q+7@aQ_RT=!zR?!|K5i{-i(%XKf7 z>s~C^y;!b$v0V4^2DY~|e=C;jUM$zWJcZrxE-S@y-HYYA7t3`omg`; zrO@-_x>qUJz4`!+JCG@VLJu6oNXm7u1ie76dzEtCt1%ejgPD?Y-K%|3hFte5<+@iX z*S$))?p4ZluTrjim2%yyJ<)wjD4ufNtCZ_rrCj$a<+@iHj2OA@Rmyd*oqUJ zy-K<6Rmyd*Qm%WIa^0(x>t6LiZ;qUJy-K<6Rmyd*-oY+`T=!}Qh7HW3o=Umy)nTZM zT=y#Fx>qUJy}ALtL9Tn1a^0(x>t3Z?_bTPOS1H%MO1bV;%5|^)jN26MLY_*w?p4Zl zugYBa-N|+DA1e9-6s?o~xPMDuM1#RK8Q3np@Zr0-VIRz`BDp&bDo(4yB~_eSgDF+q zGKUMQ_ybZ7Er_ zax~QIUQbg_vu)_-7s8k1N;Rgb>npGOYdxU*eeqYJWBVPV!ms5_HtPp$ z9K&y=`mYf7!Y!~j3%|1l_~9q(0DW&!Cj60k|FkIAXA7Kf@Pp96QlIq^|Ix&|g%7io zr>ZZ5^7@dD8Tb%q8ZoX{K-!{VAvq!NiOG~46;7sHV9~g6A>~4g+QQi^ z8CldB4r9rTs=gQXO$vJs0g9Dr&Bh_m*T!c7gEkEZvSgyFUqs27;a{1TQ`M`0b`D#J z^0wq5eb(P{Hr`vaM~(j9=IljN&-QlOvu6y(6~v2WaEh^v3}=%EDm?<1My?b-s^ecE zH+&5+{H?YZUO4?ppvNup`)oaVQ*VXlOwWWz--etgw3$&kulufCl%CXj9CQrthAyb; zTg4iU)t9E#Dla($@hlU}kLjHU(`;PVHzRH?_CKbHk(YgpiR`iu)5JP2c@^<26HJa^ z6*DdE>m{EvhY2R9SDI76S181@Ovp(THO4z4rf1AUL3n#{@xU1@SL_CuIOyvqn47l{ z-s@GRNH+#cAQ#VDfO|?~9gUA4M5#h!!gMbhgx|C9-tgcab6Su_}`u~h1m8(2}BgGH}OMFY@&G%j9=oI#ECPq6)i zp|ZU(VZX5bQ_%hr+P^b(O>OMOGHCxUgc~?0`eIhRp@T~A&6+lHQ0o&2H+In1zoqOn zXGf?HV(xSYBR!vRQwKBppgjO*I2h~8D7%@1S-k<_<_;$MX~LNf=5#x)n&n_#@4%kj z!a>vibI~XjxEuC^b6a+BifJ6jsA+NcWUhQd)xkh5bo@t=rd^aE)FVv z1}omxL9Hhd&U4V$O@s>^4E1M}-Oa&Be@4x_JDAZMafJ79FxJ1O?4Ay0^^26<%fUp? zW$xY%=Jc;AyN`o;y%`Jd>!4}>c4$8u7cWG??HlXZw)h&v_e1;9FWAdPhcw1dVjrkS zvhxmW?9Igq9m98N?(m}2J5FX{AuLlzz?O>os6E1Nu)EiLqF%Cw$ zgSp2#n9;|xg~vG<>&IC5cn7okS;7+>O!S_FCpwtZuMwW)U|zpVc(Q{9y_)b82aEcj z9EMXJEa~~I_cRBq^xL#*se{$}Fcv=D!5V!y=j<5{cGEvl_ACdx>)wQCJ6NadS?@Ux z*6Xb}X1{c>hdzuIo$FvveJKl{=U^|rJ1aWh!QT1`YQDh1KKgFTUgTh3J(9W09ON!I zTGVKcD~`t^XK`aahc@04LchZBV_IQ=PlxyE|lK;w@f^IBuVbT48> zO^BHrQ$*EoH^w_7L7zvv-sz(H{ZzHSp1t>>gZ18sB@(^a7#z>4=0N?Q8|%+yd^X~L zYfLUe+}^>NYO31F%d&LDy02fG*l&rCH#I+W$J;pGh`sPU?s7_vH8pkEN>}ra3GXPL z9u@U#thtNGKAuDkjWt{glzkqF8XIedL&TSA-U=JUY$~G;Td2R72al+;vF1wj$Uqdr z(lJWR{xI6w78)Y~9n+(28f&gYp>ZgL2{uUrx~4}5*g{hzpbvUNkG^0=;p?nzoQw~Ni`?WBNEUBJ$k^}|EL7?JC7c;3LlezF6YrhjWrEu?Bi0+ zNrFu=UC*PZZ6TagORw|j_l-3n3gNkclVOPp=y4vs(OB~d3|_9PIgWVFj<`)Kz&z9Q z9bUrz%`(B{3`uiBd?-Xb%LJ1%CC%yXC1aSwgzj5#Vtm}FIc#pHigk#Tch5&ZE3podVjUu7&;|H>pu{>vigkz->kui{AyTYEq&$mW)>^DXq`V6h zX!!;~sKq)&igkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv)*(`?L!?-TNU;u) zVjUvIIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQvBW}Q=nGx#{Db^uUtV5(& zhe)vwkzySp#X3Zab%+$}5GmFnQmjLyyak>4j97pHigkz->kui{AyTYEq*#YYu?~@99U{d#M9O|QVO@*GIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY6zdQv z)*(`?L!?-TNU;u)VjUvIIz)pHigkz->kui{AyTYEq*#YYu?~@99U{d#M2dBY z6zdQv)*(`?L!?-TNU;u)VjUvIIz)dI#I6bO4zrxah%SNS6k1BO~RH@UWN}V26>h!2mr$?1KJ*w2{QKe3gDs_5P zsnerMogP){^r%X(6aV1MdcBF{RqFJpQm03iIz6h?=~1Olk1BO~RH@UWN}V26>h!2m zr$?1KJ*w2{QKe3gDs_5PsnerMogP){^r%v&N40RdF}0^kogP){^r%v&N0mA~s?_OG zm7N~z`rld}j%PX=FdQ%328I48{QCYGCLaG9BjV3OyyUMzyusfEzmxp+Zoyti_Jaa! z{{|rmf8Oxf%?NT*yxjzMQobZpS)@TOL3wQcE@R0_@&gl>sArkz3G(k>j*aZfT^jJs zn%%ch0-Z18HTporlS}Y3n$DN;cZK?2Gv#jl)L+jZ?ynl?)|Vaq8E}v7A3$_$ zwK1m$z524_s+j@3YY>bn(5o*yUOx?hKi}Y=A=Ts7>P4)zZzKAJ@5FsL4kO;UF4~_A z>BscOGtm0n_+G5FaUFD4uD#z^h>vYW=j1M{c@tveKJcM+-TVTSuc212KV4xq7djps z&&2y7QN!-3S%H|>pH4_KP4<;tv)L}MKix|g-;-cXckG%Ge;rvpcbgB0 z&nV107Z%|>o27^s@Ueq=MX6$5&;9p1h#!iW)vFg9RFr{M=tH2`Dr|K^u@srt>vOg? zmL7Wpczr*3oO8(3yoD?1+k#%VP0?Rp?}^mfJr6v<`zFutQeL+|VWR#0=rr{Um--KA zegC{P^#hl>3TC`{W19MwOFaa7UwJf5ebuGz1r5J@HBEimrQU_I53EX4AGE3CpG9i! zYU39&;0?qtAGjDbU1*vycmSMecKyX}UhcyFpEV%9&w_msA8I;g;PL3qb47>0xpM~Fa;HP-IE zWcOMZN|7*z30_+U(qSRnJvR_pf=&S#OI5v2pkN_8#grR#Jy2#&EYr-7$?*ROoQnpb1^Wa{`2_zn^SpgCtOD;JplDt- zGX|qBJr?EWH4w&}EAxgOhp67>ex$bTk7(w=`QC1k(VTxb0jubaM%Kvf*jSd^aV#w` zayza^IefIm!!vvJ(B4?fOs`&mX~JH81-;s6dnB}-i$6!21#3dvxuNacjO*NOpsa2( zet2#Uw(X{yGxU~{(LEM1b1pOa6WY$ttZYE$xE@>(>JDeR9gWbA2GA2sv|Zodhf4Ol z@tGa<5_04()%;x#5APzQyQ6<)Cp-fG=w-I-1~6V>UfJU98iMjte-^(06HsKKDZUNf z4QN|ras!LhKpv-iAX8+wg6A#qGG`%4ZK$ZhRK3$(EZBM%i|qazR(d;rwZusA<#=>n zAg>}Nl=^!xkg^!R8CiKJSGeu)o0Y@wz``zPp-fT6Bex`1BE3-_KzgGL$8Uf6Epi9Q z0HhC;S~ke;amIm z7Kr~aX3~xpDE|o9Jl6v44}+$iEb#r_06SX{_+O*aT`UOwmyxrp1(AOs44h{{#_Mwp z%FP#=RZT1EWq;A9AkyQ98cZ}X*7Vq{2p<6xS3Q1@OZgxZ$1O72Q{um-#_w&FTI2Vz zK>QCdE%&uR`G-O2FC^F=BHI5`H~1DvjF_9`!%3cmPIqG&}({|p4|}dru_Z&Hi*>zvjLSI zP+*-!uQmg1{()KMND-rNR)=cBZaIJN_*z8bkD%9Im}A_FUxQA6Uu$yT(MZCVU|fX$ zFN{T*I6;&A#Rg=(EIThVy$(r7>UmTu!JzmPL~5^l6jN?+w;3oPUTyvXpdl7XZGuJx zO%^FH^ESpiXjb6QI}gVaSd$v4c@?G-F=3`e0amD$2!QQ`hhe zTjcfq8ov^E?~A0d2@9&&qw;YE=y(o6i)~!I4D%vrH6Vn zUTy*|6aO}&e_^U0e_96t|9m5GL7KX@R-@I-EpMG8(c955Q!@7q<4q=hZ(5Dl{T`%V zDA~hd?RQ8m90W9qv53_Bf&67zS zA#2e*nMET8AGlzVm)YG`;&q<^4b!cL$E}9x(qfD;)o&@)`$5Q6zinE5_m5!dBrzTI zofVrT9j4+5=%maf*@$&Hu?mdV; zPGd?B8D%C)=_D46Y{4CDLA-x8N|H;_oHfR*KOm>-ATP6K7;_Y_r8VO?FV!)SUo*u- zxrD6Q%tQ}E>Q@aMKy@yoqgk2awe!`6oPdhg)K}XuHMk4~zAgT`d+t z^=D+gxY7CObyfQ)qT88E_3u#g;zA?)b}!F+xte8rapU=lxk$b2Z0H*D87Ipl;bJQK z7K$F}e`2chkxh-xhfv~?os4PMv%mpVA5iCGMrW`m+WA`(%?Dg8epgG)_`<=0)Yg14 zB5(p?CCMzz+lx$hb;mtjebfjz&O|jTx@g)u1P|GVIcRN`x`w7;cqz2ZXWbE0L_H2w9W+yx*2HaMAObKAz}JqJ$rXZ_Q9BpFj)s6D{n?& zjJxXkJ&(Tg?=^FDDRQfJ0~%nK_I}qk;y!cH2u`Tmm~{xyWFk1{#~00D%q!gwOR>2d zPAi^AsfZnhgbld3c%}1UmKtfZKP_jER2$mtgV9N9h#Jr4^upfPN)J(+F}wI7Y*Wq3 z%vd~=@KP-)W6uPZ<%~qaT+T_a^cU=_@F)7lknNaVFD79sE%S!@csfv?8pVyJ&GMAZ z@*YNMZn{6lCDFrdy8n8w-E?of6|OnE+s@eCcE;|uGj_L~cf0NBsG({CelqTlB-}=O z4b}xEyBeZaZUl+db`0ABj&OFYlgxcy(s%2E3PF zi=JhD+=W-G{q_5R-MI-mpuozC;1t0Ec3_t2*aCsWf)7a5xxMjcJD8rlD=o}13b!cq z^S(Js`Mn>*FC5*l_4!3DM>vyk=d;+vv!3~@jXXC#`bf=(r0U$!@h_-vAYKX{V{~}Q z?;1SsSQA$XKkXftrLBH)66B6I@r;*$4FdWE-3j47k+28-_2gGTb>r>>sGAS#LEyCx z0)L7=1{r;C#ZTBTrn09Ht-<8+YMy26a>TsC9}%r(PQTK!S`_uiV%-qT=+Ga+s9I4C zWuZT%4FDt=>~&+NW*cJ{Kj;;#9WMS5da1jMH)2xM*|=92g<1-1c+dUCm@6?$z=PuO^F9v*L>a_Ow;FD}lS-nMbC^jtj%!}Y^X|F883)2Mwt|JQl~ zhs-Nog-4@{GqUBGTH+$zVM>JGqeqX>A*VtX>m7?7p_`4NW}|$B9>Y8@{03Gm zum#s~1sCXkEC~NuShcM-H={W&Z(H4AlpLPHL+-YEI{RK=+O~R*t(Y6bsaA$Aw5)il z9<)|wsve)pOx07ZOb6=eX>EAR$@H`~C{s^QJ(4mxF7*YAe@n^wmpN<~}F$lCp*xnU_@A z(3jMDR%QiSaF;diQzvtmGtS7|Rbkxy&bZPQsOVA^2DURURc1!PD;E8Jq1Dyj++6LW~O`L5~$n9%FS_k`&b*i@Lc50v3ZMK-W=uT6ZhmBTb<{)yp7cW z_K_D)fSkXMGRx*mE^{3i%B3n-n`8yD2vv3mek76EQvfyRC8WLxRTLEw*`PQr<1)=G`rDTS4>8)9Bq|CX3>F z1&Q6(ntit%OS8?Ia*s2W>&TNf?!|Aj&Pyf#K9o(y{+D%LD(jdIF?C)lqu8akqDuvC z*#M@ZO9ej7PWSQ(-8ZGWujPfbRLp!o*y&#C+GFfqDs9wY*4Z;ssYhwiF;?nINGbCS zevI^DQQ33;A{A(jG;3%$|W}=+p zt9Ii!`x~I>r^X2X6%_c)MxR0S@20i>j);C?qvr9&-0QRYVi;T})l`QiYoXU$%*G|F zUx31X(vKGD(@{^O)J#Aj{RH$36thv$J0g9M)S6ub?th0PzjzPiKJ2!aYsiP@Mr#`K z;TY490~hS$`5)S~y?8hZUyyI&Mi8yOU~Q`}7|V;1t-fFb(^M|v7tAWR`htb!R$sKX z)fcaA^{>{p`jWM+UT$0MuSUJUHH~gyqy49Bqy4dH-0ug`9-nP~)->5?lb<&&_Io1w zLb<_9*x;eib#}MyT^r6`+u*a?OdCvt&o%?*6*qzWq50pSu<4US&AlSvfE+rROGw1$ zJpa(yY^cv6IJ}M{;O~#g z*Ga|_qkC7Ydvg??-^a9+x_4izd%p_Z2Rhx2=GDklbJv@L3OHI*8@N^kysu1c;?M@X zUZt;=TER$b-N^$zfyCt0YLwc#=f#XyZ0AdMJ3q?LJc*pqsF3^l!ZrYUlzhqHFOUR9HfDur z^Il!s_v#7XtLyRVIb>Ub$}Y^Yt)o#bv7H80M!d2z1I zi*s#WoNM#qT$>l?+PpZ|=Eb=-FV3}jajwmab8TLnYxCk zAbp@VFV3}jajxx)^W=huVZ&jH^R}Ay*k&9l{V~z>#U-|T7#;53tY&rqBiuP`VZ=X`%PRt61nR zWH;y-Iwm>kPvtpgoCotg{UDw=Mc2SUr9XtpT8C&ZJ~_VzIlV?vhwYQE_g9Me|L4q#dLHgS7Aisho)wH4~zk}?A zNN@WcBtID=p}gMqONd3PxBV7kk?-~7*O1?&O-R3nm?orOLxRe$A*OfmHDoA6bWr&< zB0Ag9VY-_cfHeQJ$m)thf(*V>?9ZxKb6-TOUYpI&kmL z8gZYOBJ%^U_ocX`Ke9*#y~A$e{mml$#m^Yg?~A?_LQNi~*-DA1uxTLH^-sifDH{5o z#9tz{A9Z`dNL;(0+6g4VF?cZlES-)WSOq?}zz-&&@ZT*6y}pNIN&G@sPc>B~m*IN$ z2bM~>oHDieX=uQYJOcf28xKart$^k;Q;>dUO8A*67_C?^;b*2`Y`@JB&#-8+>UJb- z({p{qt5mqZJ`s@`-sr;gGgA%kb>V?o=HMMm$-ZN$%7uH!FCfW$VG0-K7`I=TLidHK z-_A&~UzozmFHB+jg(<^+PWYlFJW})ZeN`zqEDo?n#5-e|3698?5ckX{n}q1V^KTlEjXUOR;b=y;FQE(e`q8Z5dM1C0 zH9DGI;;j+M8BB&Zn9LW@(VP<73GN~YMcW%71G#O9b}#}y1$GWdz8-&!NgVA`;P86! zNnG-G%|C*;?~Tnwo9IcfuklDEZx*pl;||(yH~ei-NXr^~;zqD_Z%&fN$I;XsLmJk| zC*XM@jq%3Avwv#5H&n#@>=tckue^8y*34)l1Ee3V@V%Dr&>hhNQ=eZ=kt)dyif==t zh9Cbj>Bqkse*DX%AOC9j@h?;U_?PhGU#3|dN%{JCWLyio;sY=RtBm;ui0jhqJ7Z*y$o8NkWa z=#IEUKZq7rU&(|YX!(>9n_*^Sc5L_};yS=U|A=1Aw(8NCVl^v(v+dpOC)JwE(L31* z7D>%$=*V_hq-ri?$%$r(!EN=&$AQ+h$gjDMCD*ek@Txkph788>6zWx*_>vVAuUM|WOo*o zoO2ch5m2%O0Toab72%^`L=31PCPYy|5fxDZ5d{OHs2EUCK}AK(g6VnRsypj?e&=_d z=bz_1|9m-z-hNfpy>;tWb#+bmov9|swQobM|KNw7SznlR0X^M!N2a#-MXT}6(3S!> zt_LkVPpCm#P&|_g>HxxzAUpVCHjfg$q}Kz4&#cfkjG=H_=nihy`KysyYl!H97Im-= z4c;1fp(anyR?*dHPw?TuyEVzI*NRSn^McO=zWr}<`0fHEuMeq0}hkUk7Xz7^u$3-cSK&;Xr((SP&9-PyoZI_sty z{n{O2etQ<`uCvy1mUb6rIW%iFZfU_q0sfk@wjBc)ACm$P>f6W%oT}TwXIAJF9IG0P z#UQz=^a##F1Cbg&2KMJf8zqvaQ+AtUbF@I|I-5X)A?3|vv3K_OR$y(BVNFZ zf-F9b>KBW>0wcJbKGaMM#=6jGfsHs-k5GNk`ArUEgw~@roV9_k{M6NaIV33%=4Yvahjk~66#HVfl4F8b?Q(55tNn=fZ>s|^qaeE+}}(~Yx>TLj)rR@XNK#i^Q>fZ z^iE`0ILuG^1Ix6{oj8|UimNRFBNqgQ)Rd2g_)d3OV0=wVcq;1j+L!QTGmlgC$|l^C zAYR8qYplCDl}`xTEP50NE1E)L@W#O7oTs}jnpp=aO9NZ~O?d>yoocc%glMO0&4$ zyqq*iS4a}V-?+q;f>vk|%H>=IS54EEuc@hgnw!*>^U5VW&26dSk1ZNHk7Vt4)M%gi zU+uHf+6$*+z>ISPyKA(La}%tnAr?L1ac&bmtO`Fy+XuUW1ePR9uQ)&5n@Ke$a9ITN~)^1U*|4LOYX`v!Kybf6y@lU4{UD7DlS);H#aw`U`5R-|5sE0y~{rL*R{C zmAq-rb-+b)W2zHwEKkz1A1a zNxNsgxJO^@>z$5#wFm#IY3oz}ZR2Sc!M;cv^L33ei)5s5JWY6!Q_c5I=QC&m^x%=_tl_E_ zIm0!SLIq%&?!_lf&U}VIWTJJA!`n1j0UcBmUhE`w%ic#_rWdc1Zj)ZTKHZCmPdM=c zo)J3%8w)8X`$yDqiBn+aj5cUb$|)GeIl4J1r>zFv(3I1Yiv_zQ8x{ zX%}rHKrU{V;oY{rT!PzCv1-m^M{m>4X?BHfr~ZgA%}z0>-CI#~hFzbFDLo|S+S#mCagbH`5(7bgK54pirk%bp zGg*c}CP1vq7Wk_`AB6Yt(+K(!SXIMOg;3Qq_cNI6aU4tZT-#<#n%NhHWU6(x^Pyz0h zJX;6bL&5K?K;NYs+NStc?#K#(9a{j61awz5Gm3)m*3{fYdMEf5Cu#dmv-7ll(u7fV zj%kAMcss*z?m_N~QKl<8)O5ut)tLL((G`wTec5tn3ST;-)P;IoTzDU>{Ez~BSmshT z@ye|tftU_Of(IZ{-7#mSE%&x zl7#-!!w9;01HxO(y1HpUjN(o7YfW=Dk-l$PO&6mHYpEK&YKGieYNW?9hV^5VWrnqG z^E#?ydP{fhdi-_))?fTDhogBf(~J3~HEJ%S0+tOKIA(Z`X+d5`+yJJ@`B0oskn`=BZAZy@GqiHJoR@9I11mY-it+>G{6duPO&LGK zy5eVX9{!~Xx2pvAq|D7AyXrPH`}H~e^l}asYNlz6JL}}!@o0TUCh35|R>*D0FCdZ7SAViDZVUfq+^E-F z{aN-w%^gRgBCEI?%*ePwXHKcfyuoDVa?B%Myy@H}$aOg85eZ$i;#`h-v?b>8k(zA8 zJeq8dd9)Gp$ajnPYqAmZ$k~cx9&N-t>N`{}2Q^~DAzjn2T$Y0xk2DIX9ExRxc_ZqWH=_6zxdE)fyb*QG8_|Hg z5#^~f%GEjMWoSTNhEC%2GdbP72Mru4$H%)<3a>;`(FL4t-h(>kJtzqETLF3Zc_SA{ zhcaeA%p|WqxjwtYdwl%=eUTZE7n#o>TSwH`-$!8i|IO>PfV@uo3{oXQ(ly|{S$mfJ z|M%W3hhKbLfD)O<>hOz?4v=-NO!MA@LAjacwFd(Qty2Bg;}*jGP~Lj5{@mJcJ#zT1 z$6ll+Sg{p0Z#_D&eAvA7V1KHxdFP>h8#b>z_&i{h@f#2OC$hPgC@aFQWgOKRWF6&) zk>D%&jBOqVFj~Qb$O!(3Lx3N-Ivry%By0D%71cPkzr#WeZzFM>Z`H|hn|YTbHN-cF z=0#kM72*#iCr7@+c__32w)^wveW5RF-ZT>!VzX7%o)D3mH= zoyiW6dJrddc>uJt>V3k+PR+g*NlsoSnz!LqoEqb~td%zo!YlUIB(b3C2l63 z(8F&Ja*b+<8n!FUO5-~7!=TO-I%JCCN4Fr5&yTt8{DSM|PI2!%UArNlA7(8(fn;yobjw}V zfqic^;3rz{4S_6vt~QDFPj}KrPb$+!YbBGqvJ%BT>rNWN9`yLli#ur?x7i;6A#K-% z#x8$MI^hyynz4Gm*cthQd-9AZ*LPn{eP=Y_`rMVsJ2O6(PkCuH+~-s)i=P(uWPx2Z z0zK<+mT6_r?z)wc`EZomF^3EOT~n}Q^M4C=9Lfc?>MmJ*SaoD|9gNgF^wuJEU9@aA zr~|jln}f4Hx>qBspg1(65iGLKLm`#l>WNOj0t)e zHB8UHJX=-hso6@;zrSKE^Za{J1I#&k{vEl~%)fVH{w+20uWROC*UZ1JnSb5?#+LJJ zmC0>&&HNj!HUDOEJKX<Sgo-ZW>F5sX0s%!Py2BKDjgE1l&v#+gq)E8> zlQ{Bs>}?0C{WZ{XbHh=%;hfBQ`i4U~P=j=!2AM#O7>7x$MhRuUF4_TBTFQJ|l+Q_- zAPGKK%EUaiqw56nq-m zvlK-4Nen>D+eO|~zNWaruWK>W;5UrE0=7e`dr|jCdLFh_bDV#y&s~*=^ZoifXyx`p zCw!vo%Vd=?zI#8;&8U6%_G;g~z5m?3^AFK(6wi`d_ho!u`_>)fTX!aAp90p32O0Ss zu)sbfRqNKRYTde3?OS)Q30B}bGFc7w8RZ*ym^Fl-fNR1zr8l51Kyz^(q+L7%(t1dF^b*p;c*f5IzK_jT7>oL6^ufeQVQo== z6e1dkGKx;;lC%LwY^#6@@GWd83easR8KmsjS@mrw@6qL~nj9Q`ilTgkPRDtamf<{u zcH)?6MSsH|d$fH371s$MT!Fu?8CuJUlg+&(w20w+pED@*DKywqbdD2xms>eigKHJC z!&jqF5idZL6@3}T+0$%}P)YW7oR(h0094O{HphH>)~Y-D{8^UMS}ULs|7?R(mB}7e zA^vRcq+;v?JG2G$IBh~@$Zpw+nu7+9tRf+&;8D9BrcQ zX=l~Hkh9y_PeP>=_#M!(IcMix1?}Afqi||-6RfInt-#i(Z*F0}55_at z^=-p^JGiH&q?V5tK%v_wp9{ZSlckk#G=NrT~d!utV6MddXd$b-Tx{Ta_3qZpX~sxGWy@C(Z7oH*QlMpO>PJFgnkZ! zqT{);Y`-2G_8?_(ZN9ExHDz!GQ2HC!H_s@o2;rO;f=H;PbRN}GI`2P9udJ;UKYnkN zHmuK=-&hKCVuiYSV@a=?tYUrx_>OkpRmhBRZSUx3kr8gdJNijvgnjkSNMrm~HohSh zjn(!R^Bcm4!rT|9c_RN%9d2`k;H-zbad=vUzkd4ASzIV^`Buw%R47v1vx_?C13i-JNiRQ zP8+tnD-H-R;@?O~|9Hm~&OC!N`GDU;ZNiyH$}#Vm?-Yh-ak^RjA$khVvKpG@CK54j ztW2{J(sG=tUQ=*!klqN1^hQXeH$tM%M&l}`C2*%hdLty#8zE82D4xIdMo7e=2p$c? zF-&?RB+?rpQ8nz3(v!V;{?;2Ik=_W2^hQYZFwBmV-Ux~GMo6SLLZZffF{zQ>2#NGY zNTfGHqBcD+Inoliu9);jNTfGHBE1n3>5Y&`Z-hjXpdm?mBP7xrA(7q)iS$NDw51om z+D3XKB+?rp(G+OjMS3G7nuJ!oPI@CG3J$icH&7D*$7FQjgXYt2uYcZkkoaM`^HvgBP3-uLQ?IJc+^&ABP8`D zI_8+I%tlDcY=orxp@u%#mK*i;b(Gl%Ntun1)X%7PfTNnB>jygOQj{FzsIPnC4Yi}p zMo7wRgrv+yNXl%4q*lVGXFAGkgrv+yNXl%4q|8Q0%4~$B%tlD+Ea;r=Dzg!iG8-W& zvk{Uq8zCvP5t1?+At|#Fk}?}1DYFrha?pmif@(3$-4j%G`(fo8RAwV2Wi~=mSDuY^ zYEb6f&sQ%FLO@QwG8-YOA7J&&eANqWn3b>0 zMo7wRgrv+yNXl%4q|8Q0%4~$B%tlCxQ2V9%sw*zvdHKq0gru$-$r~Xlvk{Uq8zCvP z5t7OuV_6;UQaNW~y>XYSI|AVXcPX zyb+Rp1?;+rPtqG9+3Agt?5QZj8zI?wFl8>Eq&GscUl{^ta7ub3Bzp*^pvyQVy%Ca~ z-U!K_h_OCDg{<^ONOpQ7BzqP#U&UGJjgaj0Mo9K<)Xp0r+3Agt?DjDArgM;z-U!Kl zYdEF{PDyWsWT!VmveO$O+3Agt?2FM6n3pX(y%Ca~-U!J~Z-iuTMismflAXk8#tp}^ z(;Fe#>5Y)=S8xf2I4ivolAYcN$xd&CWT!VmveO$O+3Agt?9bpj-U!J~Z-iv0H$t-K zV%YLVNcJ!c+-yEcZ-it&3~%s8NOpQ7Bs;wklAYcN$v%X81fE=5c6uWudlrU-%PHxN zknHqENOo)V7t~pHCtMaNVc9hsA?5N$ND3Pvt%AQYPr;fYsHWi5ZgG%frfyouZhU7p z4)p2yC`muz+@`=BzOfbJ=u%T01JnRgL8`_vL@!;zH@4q!3{yMg`ZNf~2#v=vN|)f6 zK{w!-N%!Fxqx~0J_@Tt7r&;*Y-0n$y6IysR9&wU4pJUBBLQj3lLA?#=#u>O7)38|x zho^C{tub{#$tLvN<(Acq4qn1PD&w^i%0h98aV2D=qxE$|;cT zKz(rRNPE%fPV_SLbf!;m>_TtPwXCl6%L2>lMn7DH&keKa#v4kh+{7rJDJ}k z^_z-mpC;hgm*&Ire)K9l(4P+CIDr0vB?IZzOZn>@@57$K)CY^!A#^>o4W$jJp!m2OLLG@GAaIt5O_CQY#$Kp&mGnqH}N@O&8)ghQ>h8xzq~f&!b)!^Nsmb zSUZj?;IZ*^0Ou3vS=cj?cA@+vItevSrZdo%^GU(-DU@2oKR)FmWhVUtsaf{qXa}MAP|~r_O_a=Fk^t%UlYhu1n~9Xr4!J!Sc)KR_MQ++Q6RqG#h%Zq**w> zicTPX0kws;tLa*3xR&mP{>8KewO>a&VEJ;Ijq^L{dRTiGeFOijpm$);O5zR3@1auE z^$7idv9XrcpD=)r)U>!-bi6+ewyOY`3xeL0h)bNE~0Hi*ejeH{$p*{QwO+=uFuB3avrPtJDy+@1*WH?xKFs z^BPUS@pZZa$2Vv>j&IUIjECK{3?uC=T7y>Xp?7EU)1F^(e1~RZjP0c}asDpdgY)<3 zSsdS|g|KrUO@!tTs4nXLh&to=F};Qs?WZqr{Dl6(@l(o!KMznF`1T-G!v4?b3V8Ah z%0ccSnv2nOn3m%BCACJ%SJW5Bujy`RK0@!pli$!1Xuvl|FiO9plW;t$zc%ADh%%{K4Co2ca0xayFp9@FQa< z!+rRnje+>%k(zfIPax`6{P9UWjz1AB4>9WSYokA7aAc5LgHe`AssedgqUp>&pVWIWsen`-24H_uUt)ZYB2|DcAC3L8kT-@@WBfUn z)T_{W9<0_EnaYOM<4^-=JgKkY^$Da1;uFzKjKWEz?$wu?`Ui>ANDYH)=8>9)KbN5f zTsW7L>V%T>K^SOPkeYzDUx|jnaaWOQ29p+$+63{dNgaky7h>5As~3?vgxdc{DjQvL z4XL|f;1W_lp$o1fWx$y-UahO*m9 zU4q*0ATZG@J4Nu7W#_mesa z^Z=>jF!w=H*TUS@uoH<7k*b0b50knDMm$1l9jsnUsy&9=qok6s^D*=vj97;syM*fX zq*h?KK7pYDxhF|2fU`D`@?peA3-EBNy~sr~r# z0^EZ?FG2uAdJC!7Q0-O>8_+g95XPUEAdZG@C-oaf*30M>4D21G5~%MLQd3~WtE4{0 zNZv`R3mmcwiD>j|q*}n1*GYW~pS?lqZM6MOQfES7Hz@^ri`2!i>;qC6=>8AUD{#R_ z_*J_du-+a<_S_(bdjyk+(;}B|x8b8WWKxnZi3Bbkx8a~n9?`{E+Q#*6gz?*uIWw+z zBaG|a2;+kzn6Tq|H^TVt98Aw~y&GZtL>&ydxY>;`B)bv*1N}agITu2$H)v=F{32#o z)Pv^_8O6?0Bo_C^tCf6CEAD;H7^|-1pMzA$GTE)-ftPk;2CSpq6!;pN!b!g_ z(qUFsGBb-^JJ`xGLgWn`WaXQ4E&oloutpkpwf!u6t1*mC#$hmVO!4Au&PPAwO*%Q=r)t(IF}*oB*}vI zddcfpJHe3+MEh~n)I8~Ptd6YDA=a*n@)SPCKK>;s)<$ab8O z@8fs1BoEcKO#aE$1yS88Qr)L}EURtOXERV;m*m(u8q>F{)lFNh@IVe#cNc#srx~b+ zD72kYDC#NXIE1$K5^|k$a0T=h3OM6na$g}B(jj>@>Ip<4-$@La3(ftKJ{t%_h9>_) z0cSMChKZQvypG~$3XwDU4XoXSl=BSQJzU6kHo}P`gd8-di*>f?U)MPoy*E;_0?s1P zIYO{&V6rqDcGZ6y%SEwkDjYN_>9f7CYkZPl2sx+1*oh)$Ik$o)36b*!XtI!U7Q(Lc zg>2^<*fmwibv}i|rVF9+bCb)t^5JOnSgE`fbX}12*(g*#JDHV($~Qx7u83LA->Bdc zA#w`fqDzI8lMR|DWINq)ZCxhhcmsQMu`W+L@?_K+aA4L& zVpbUES0;Tn7iL|PT+C*@3tJb94$Juvv_y!UPeIoSDX&|n4%YQXzwLGI(b>9D?C`qx z>tNknQ}flyN1!;c5Up4wHD3uuOOrlZgqoKplewt*XSm?5bj=?2EWF#OASaxMduX~| zr^kNWN`-7^3*2#!kmGy{S|#K`-p!@!v5^ha)M6H1}7$mogS#M!1-kNbN^!pG*3z4N}{ZFXP0y7Jk`o4CedE3&}$)#;IFG>{XnSBFjvM{dRNnXR1T@C4X#m0Nl37;l?HUgC$PHyJP{=y~tm9Y_b zna!~0Yaw!OM5B%f;lB4-@?%zcBUFANDlfwMw@II?!VXBk)ES+Rdmi7t@DrX{xD7>l z_Eu4zW$h?WeomBU9yiL@c_7LcTrkSxI~3)y=2Z;B&vyhKOcq}NMd2uSbS%mpmlfrX zh)3D4*|B92NbgC;6R0UC%1+CRa%=JtyoMwe*7sFq<*-G$jnT-!(WK4xXPGF6Mo!MP z$co&GLt{Kf=YWUY-!RaEjVS9TB!*Yu&?M;a{W;W$-UZp+G1S_3%(T>bn0~*q=?Pd) zR%j#Y40W^Dp-AB)IQ)SBx_)fcbr9!e)82)?98NAgkpUA5{>>+xm%V;5))S?iT<3X= zzi_wACg|EA^+(;|o&%9iccCvVY6nF`FT?AKTHlhdqj3!4aBoW6ihON4fkV zG+xRtKaI=xfldU_vHezPD!b+ZJAsVsBd{SBe&`yUyEY1iAI_MCqWIBKlnpW7OA}aI;eh+5h}_b{|r77m$L6wN&fs#@oBh}yH6#sfDCVPi;J*O z8;BO~^Or$7xdsM)7}u6(Uk^R8@H1mjB+AxU?nd-pcz^MDq&RMr4gREfNj}D!yN7c= z&p#KXA}+r|4u7Q~!-|{_%3&qVLrL!HuWhb0`)g}%0<72$E|o*^wICL2V4hVq;KAxC_Pq zL|#s8ACH#)Ca)mYkbQC%#mh<%NEJK09W=(|m1Bbtd;+-~Lcs-mxE=>9QU`qz=ETT) zSR1~E&)8O7m@PAfwPzx?r!&|{lfhmJ^1Kn80CmukF2a`UB35K?I*lzhV(c?3@>Mz` z7v`FbBAi(f9>rl!j1UgFA9LrPOZEXau^v)dJcy2rgvU{A8YuSHN~BMq5^jeTd;B`k zL@MF7II$17%O_C@7YtdElUZM5);F2#N4HIqDCP zpI;QP?7JbvQ=Jux$tnv z)Cnbg<%Qh(81MeX5;i$fcjEN(Eq{`hiMnw#%%5DsA5}Bl#SG_b$aI&mwkaB7?jP); zsT#7}=B(|4I&46Wo6RsoLxEdwEa1Xu8|0Lj_Fbf}yK;RI`g1hYvmzWcbaHEy3i82< zus4$jJe&zvL>| zn5z3aWJ~74yVYeZTGAXAb}Hln)G`mVWM(`6AtVR68-u*ivC2<}x;Z?9zQ!3NP%=23 z5A(UmFm73S75sY{7x}uTh|c{Q1IQ}B4bGd%xe7}qqhK5qSfw4&gkS~|6IN*`SHZbQ79N@In=XtzYP&|(}2g=Ih&46Ngy!lTwk2m{?nEeJ*Pia>4^RlV>rf1Xxl3KcwUJY|aq5wBq@GfU=c-m5GmDk6 zj}LrSXy#SDy;wtHjdq8OPN>w;p@NPM6?Al{prbGLM@O_cI-Esl<8adbqBqa#`z z9ns>9Ig7vEts`0-9ns?Gh!#gjv^f7KqUHZYwEUllmj5>+T0-fFmQXsPC6tb638f=i zLg|Q>5Mj>Yh?Y<~q9v4$XbGhwT0&D%h9g=+>4=t4I-(`?$`BLL5=uw3gwhc$p%;eY z0})H5BU(Ze2V=F5*p$%95qMq4C+UcmP&%R|l#XZ#r6XEGyHPtww1m#w`C>_xfN=LMW(h)78bVN%i9nlg>N3?{}5iOx~L`x_g(Gp5Ww1i$6 zh=mY;B27oMgwhc$p>#w`C>_xfN=LMW(h)78bVN%i9nlg>N3?{}5iOx%gRlzYD$)@x zp@-oOj%W#`BU(b~h?Y<~q9v4$XbGhwT0-fFmQXsPC6tb638f=iLg|Q>P)$TjK1Z}T zbBJ%8*@V|+F7cZkx8Z)=*NXMKv|{}(tysTHE7tGQiuJp+V*M_ySiegv*6-4a^}DoU z{VuK8yi3cJcWKu^-O006;CJfj;|}IK(uo-$Ms?9&ir z8)_O1GGWVhF4-d3f#qC7rv#_4T)v2h6#cxN+{=tKs7g6!2L8F3|Oi@#EcD+vc+4Bs=9=SBQkaIFk&ivp#?5&uo zdqHqNQ165K{+N5&rDk)F_5d`d+^s$QHSfuGj+6A z(J*7a!Oki=jIqFAcNIO2WeZjOApZ7N(e0dDWHk3z(MDWRvB@2*q91T>iOC(NqGQ-S zr3Oc+Xdli^7#yXdd$|E+2G3K`YQ}Pd6I65=H@1$!^Hua0#-zdNDms-rrLMtQcr?2j z&f_7F$7?g+it|{@VUJErCz6$M4$kA8@b5vFS(+|`U)8;evpGQ@boLYJY}d-TmvcBl zA98qk%TCqR4#&6r!R#o_8HRsIGad>yV-M6*U*nnx!~$DwuPwSQxDRXXz)Q9si&n7L zE1>O$oO(m?lH_HZM`wvG=e?fl^WURBGOIM7h@^FZAf^NaA zbPk@ppT{|z@c-bDvleRCr-h+*70Yo#4qNnEI>)u*&v7C<{6IP}!^(II=W$NZIVaLN zj+JqQb2tI}Jx(b0#zb*lpV8l%R9wP}$)X)!;oY1N(aPg^Hz%ZM<41_h60+%*LwHjs z$hK|0qzr`YRLLLo1 zjBpd7FpU7+CFIk2pp`-qIv;eeP?TnY9uUf)OF<6_WzquBBSJA+0(wj+i*5m}7mCwe zpbbLVv<>vMP!65{0fI<`a%mUxo)^law?SKk@@W=Iz9dvYA0lsuP$7K=+9^~-M?kL& z71NKP-9jaF0`#^}DJ8$eJ1C(9H3sbyDnn;qSnOVap0xi)XJ0Ix{n>YT=T+?UAmGma ztk^p(3!S~glyUbIws`MR?tsEF1-r+RVYBaLC1xH z^d9I>p%Co{{UhYjMF;TFxx|e8FkJ?6g?w5F3JFE%dXO&^rCUK6LK(CIlqHl&4}x-p zV)Pg&Unq+E!C!n*0qI3u}TquLS z1&t8Oq@O@%3&rRJXrxdU5hl`egyM7z*W@UnY-)tO(Ly=Y0yIV_m#RSL3guB-(0M}n z)CDwFsDOHd#t9YDAkcWBB038+L8zEUgC+`f6$FWaXJHZlTbE|1l=r@ zLt{Zpg>vb9&@DoFG!wK;D4*8ju6~;kcg6G)_dWR8{t?&Rj1qH4?So6>_7b1Fh`VBC ziPtUaRM7oG*tG%lfRIBEgB}!e=`d)uP=NM>9uf-D z;Xf>EjZla_0X-t*(J{FDQK2w>1$tb_r$5nY>xClpHRws9DD}gX@{~{pbpt&ulu6IS zHO~sgXgg?=P!_!gdQK=#Z-X`qWzz?s=Y?|U0O$pwT>299qEH?k1#J<^r|zI_LfjR1 zmbjzgXZv|P@4j2Q;(m1AOC>&c5qHI|67O(6x}r61gRhIIMNL6(2oX&Ly(y$<6lk}Q zOdf`a~#7tI#nAgfi$3&}TxKl=>O>bDI3>(D3=Ckki%A?zl zdo>T?%yS2QT~{w#twr=pSyQG~b@ zP$MBC4^=i6QnVX+O@wS}h`gpk4kbX%gk0(ZI!P!%r-7Oa1?d3BPz#|D?E|$G^5|3C z0ZtJL)BB)GA)m4_C8dNSMJa~K;54BO3W3@RWs>tJo?r;Y$Om;0%0h$$zVRaz zr$SICp=>G#br#B@hM+D&xpWe!t56=b26Yq4r$UVW?uK+%Bum{yF}h;H2|TMQHTRJs z43?gyK6ep!#lTW;P6@iA7E0pVhs7 z%Exukr_{X@p0$VI#@$bxe>Sd_Ii)^#3OoObQjdQXhF1QCFI{Bkx)vm)at4iBNzxVq{z=6r|C=U_~Poq8^}|ggm+zC6@|?X*p<_ zkWW1^+HMny&`w-icL+u4{@?I@4WSIW3v{>S9YFU8Wl?v~Dxo;_1Klf> zO+!KV3FXk)p!$s|I$*oAOYu3g8i3?^IyRI;Gt5VJB6M9c&T>} zio`k%8f>i>Q9P5t9Q>qEh^jFSY!LG3svogVF{HxO66!We9u}9F6Q2>vjP>bkJ!`;; zk%z(doKQZUje?sEsbX0ANU6JxE!}`#cvLLyjf!3<^|=LX>5fwGv@%#aq_g#^RKd{I z+9`w|!21}_ibQLSuG){4h~&lT0ni&l+4M0y@|KjuBLiH9dnB)j4uakmV%xTsx+77s zeKGp|C9&;UoWEP@v(0SV$EDubatz_V7!02nQM_*-jS1&dQRLDZEF(S_3eaz#U>PA4 zjP>i##X2N}yCdd^!-kYcw|szQgyi|O1w-l^p$HYBhHr(U)CqUT??f(x2E&%4hFmxU zpL32$$voPHCDac>`LTW-yI4O870{KKyniyJ3hDF%SUyNzF+B|@9v3R59;okxluW=; z`%2wK@Pa)9HGe3Mx&oh_{wVd?f$S)i@aETnqn4qGZo(`oLbMzd6!K^#$P)_F{UBe+ zr!}CcP=p=>WeP>@MZ!8XkvgjL7zEGSpFis1FvSZx_ z_P0t5sRBBNPD@B$2{{-iWkRKt4JsE(&Im`5?C(G0tAw@CJNkTT|f|?6CR0L`v4HB}c2$$Cop%690BjGcIFz>?| zXBxuKovj3&B@~bKA7~91$f4D+X@rR7Q7=p`=SW@wZNwe%T*)h<0mvIGc_p+Nc@rg% zub`d@cPAQS7r}GArM)3c>XQ>b`+?g#GvSS@2e$^{k_$!DqNRV}CM-l0Mc&0iin2ko zg>1S3-8M%E-xx>UTp^d%;=;YekP6Ux(4~ejFvc9fJw!@I=oQd>p$r&4HQ``#Xzr`b~)feobIMgzNs+gwN?#4l54Tm$wxztGYYk)j3AYo{ZBD;atho9RZqW&!6|m^)gg1gk_ril~YKh*La4%y~PJci|r{Pk0IN`HO z7JVY&-NvF5VCaTgqK_urXIYff9~aSIa6LYi@L45`Zccb_vuImfC@<6!eJ0`l%%YsW zNkn_Y`!6PZR>`8TB)n(?h;H16XW+F&wNVhqCyNK?^)V3?(vq~0yJK=R_(E*sR z_SO=8BjHYBQBL12qAf5^-b?tbl129?ysKEWD-8Rzmgolw_W>5=^p8ZeGd?38NcgOh zMZZdTFRI(6@pA!jpK3DQC zZ2D6wnGcCzna`DTB^hPj9XO@M=-rqRE$7i6E_0t_QBIGPnHxh3jKQojpH;GGL7BIg zMXyGYqFSOkW$v#m%ISF`Iu#Q~ahcC5Su|PZWmZV7^=gSG%G{HYZdYJtE*H`97_#-t zd{)V#P0PHVESf}-lWK`pl)2}#D5p0T(PhDjcOX75?%c7q1{;6cp3 zQpwBci{WKHSI(83Tjp)xN*>01JGQ2hA2H{QH-zsz-ta9Z^)h`!bs}^TnmMVa$|4NI zDN-_rmSP}I6)K>{XxlWAD}gy9%iQH~Ij+$}XaK-wL{0$bq7zW$tEH^dl546GesiP;pP0 z&lRwuhswN0O`vE#tbMpf(IU{JX+?Ao#?d;V5KTa@Jt-8U>7b25IW!ly@n?k!s10bd z5Vz~TGPf7%vTuYB9}si4xcB(nb_-lm>l?hn7Mi z>I?eBP$UMmd&^vo@U_oHd*2ha3qQjQTjq0htoG|NZv~1_H`Mk`joN;o?}UiX0DUi{ z=p4`wLN<*D{UqejG|(?XF15t?{Y@x97bEYuP>?PM{UH>hMWDZgJQ)5(nY)DzuY}hQ zi{XsL6sFFQiwpTwjl3M87>$HybA__#6y)U#70{W;D-bF~qwI2b87#JsVwQ2s z&CGrSuA-uHpBu}KN|t-ioP|G@&f=;kLFyak>ya z)Ltl?E(LWI%Aq8j*jXr-iqNm!gbHXLX2kA7h4kCb%a^(Udu`eQ|R{RyGBUfiFj*Xa}VlKXtU zdY-Nq!n5?6cD7!gUaD7`^Yx-}fnNXpPcP7x=(X03df9Y~UIE>%7c+P1b;&(?iE+PP z13aW}y=(P7Zk@hCZP53HXY|CqImqAl4SrUZeYcM{YkJmwOHW~YgGERQmXv4D!QXv) z1~{OH@E5^%>mX-%c{Z*P>nlAPzqRr+Fp`4Tm$T<}c+&^)uMWQoSQ$HU9_Iv|^HVwp z-=+SXb2tGb`&dKo)m9kUor>_ALJiZC=kQF-br4YXR2x=vy zXgTN4LU^1GN(lw&c~G@bh_-{;2zhjki&ef*m~H}{F67f4 zpmstLS_SGL6s0wwPC^;99@IrBlb!{26N=GRP!FLj+6n3<6sJ9)K0?{_LI7_fgmP#H zXn;^Iy$Kp5lt=tC(L;pt=@ZZyLIrdfbf!=t9R&>+DxzOOXA2e6-=K4ZN+^KN9xYT# ze}K*vN{}7GhYBI?>?RfN`{+q~D>}Pbh3V`|FpS4n_&f->v!_;g_g0~^?Q6pGOcp#KSF(GJkHLUDQ% zv_vSIrsFnry-*I#2Hhx>OY=cD3+2)OK(`3x(~Y28g$n3)(CtEnbPs5`P!T-@x=W~- z)`3^n>{LG9=T!JS2)MH!t?+KB z=FTp~(;^W?XM@%Wp|e5jh0xicCxp=1peKdU*`N(V=xoqaLg;MJMj>=I=xHHzHs~24 zk2Yd-KPwcb6LGxc5yDTzWh44TC_-V-i$YO~gSHA~&ictmV6`?F@ z0oo}Pr%o77uL)(7or4cuLOImj!-p=RT#6%ak5C>}A@3cbd@4iUyFvxj5cIxKA$^7V zJ`gIRQ;_$OP%)hb+AmZ>ok5=pl@k9J%R!+8%?Euh#GSpS!d;J^wD+L1ACb=9j53ER zd>#bc*+(m)m!68wzBqvgR~6-0Xi0Eq2k3x!;fPNCPX({MuA%~WOei3qM z73f!?06hfyO(;l@gMJqZ(MHg5A&>gPZ6}1nw6G9&a3Pg0Ukj5fNrbwuW>S8dL2o=+%$V&*7&{4>h3zgEd1-OF?C1@+Co)CBT zkqU1GdeW|6j+b?25ZEtb1<;^TCJzF9b0pZTQS^K6?88_>G;dVC&2;u!6lx(vbPI0t zCkrY11Rc{#D5!(cPcan214-4Wk(YHEs(cG8%qERWSf9<`;BVb1lTCq9UsbsEQ6iVe zST5I%uWC1YV^cZC!hn z`n`}@r5+P9tJEKa%qsOqA+t*TNyw~He-<*U)L(?mD)m<(vr7F<$gEO-7c#5V6GCQ{ z`lpatrT#5sR;gB{X@gm%Dj~BnN@01h)4Wat=${ZlX{hUr1ih6 z)OwXZ4+8G&CY9b_+}Uqo3^X&Mcyjp~sJW0sJ3uE3g=j0Nl~5$su~RRrwNNb915_nc z5bFx67UG8p4J+NUb};9WMwpW-*om%O$nfM}Cuw$i{LXp@Ih<2$gUX4^6PbaBu zrF#~OevMhVePzB*UxtNtw@RN?vS`0bZzfLZTxc91qPW7SSEaj*MejQut4|UA8?7Hy z>9b0{bcR=YyI8adKH8mKsV^NovQDDK zZh}Q&rO(x|MN=z1w>{M6Hp8OOSVU~mq)N9T((US|SYn7p3RTaj^jRf~&Z+eJvMASj zi4n!al8z+pcdQ9T(FbtuWtBcxz={@Dde^X`RdCk-YT0mQrTYkr z{s@y7i0F5y{Mt&NRkG+!mELw1J+m=laB7KOSLq&RQBJ=>ME7^X%B<37l`Oil()))+ zUqq2rwM6f%bnA40XlG>JEuu%@h5IUfR>`7kE4?--LU9}(t0nqSr8|N}cXY zSn0maqKlEfRYV7-un?;BStSpiH!HnwSo9wZ;kV2H!EEoUU6pRMBShyx^mQ2^U&7n( zRQjxvYyGg&>yIMzDSG+i%A&PM#oD4Hat{dEw5B~Ka3PmgVsL*h#3SInN_PfV(g`yA zD)U%_eGmivP^Hh6b0yzZdaJpT4j35Uo2KCk-;DPEAmq?D5cyG>9faDiE8U%}b_P85 zjWl}^`tqkrpQ~fFCn~*TthNke@=qg*AB`V`tKsijihiwh;}{zD2n@g9MbQUv)IXIz zSHOw_RbDlU&`t17s7hb*a6(TsG%UmxsVa9kD>~W*i4Bk-Yizs zAEG&FMG(!Xa&KkPO<2CiM6?jM#k?w?RdOGeRe7(m=xRKItW%Yq0A6m7FT)tZ1TY9x z-;kaFimTl3SZ#A$-KAA#0$`6ctn#@!w&;dB-qf_kRtj4z1B|hY-$N*9fjCql~wL_T*(9sjg(X} z0|}j~e6E};>0RY*;7TUIGkuLHhQ@qMj{R#X>R#o($BHgN1wBR44HcMVt9-726`fh- zeb0)%hDF0glxMmjRc;pAWlzUAIzvRS#yC2=%4d}+7)2-x+Q-!r9aZJ_X3^i_ zkTD{<1lP%gDxX!d=mk~YSQcG@UYlt|@yXq#DOK(w7JV5vi)kYI1@>wN|US8$h z!=i^VUazPndP$YLjYUs~+vkZW!so1oRX(d^(Hp9~k63gwwBKYzZLW23mHQWqK8m(p zC!)V#gf6Y}StX0!RTa%cGie$wz7|JU z4q(yU?Gf})OZ2`fZzhW_fXW9%Gz%6yQkBUnq5M{O182Ehb1v&(bx)%GIHhxO^*&Xr z5s#z&NVjjsVZAisFb2@mXupVVsfvEYqCHUKwpx~KuJZn3(T~u-FNn%^xHh&|WwJ`H z^)<8~&7w`H^^IDhub}-%w_j?G50xV7B4Ib$&!R4E!e~H3F4vsPI#}HYRnf6HrGuDU zKB}ee-70Sp((TFc-TR{Ma=3PXRVFK8(J!i^_psHnMx(f~c zsw$IJ!jgAzHQ+3lYtCgItnL`bKTc@_YWz{exbU|a|G4(;C*i`Q;?8$5oPNgm7tuef zysjuh`+4R}i_$dCO_|9sK>TKeQpIbLh7EyT`n}4Xz-o_S$~+-zzrj#bDW9uji~Lmd zZdSVm4vVH_sF91QH`5RW=wn>yu~b=&+F;6ik=3q)D$i7I*T-aq14Cu%>$2uP$dxjMARO}ULxB9|@BW&K=L zgOqm;5~&`>P=$ygNFRcYYaDYb227J$j!CB6E4ZpR(XI7T<}UF=BTTX>pDSRsty9sB ztoA5YcU3hlcmS1D*RA!A>KQPW=3jzoWTPi1m-DA7FSc0!3ZzMjdADg&1N(YpPn%9usb@7W7Sd%ektB=$rmh)hc*kSSph%V72F@qPtn` zBy`j08nulvV$Q8m8^rv6UM;o5Q{E4(_6>~bvqf!tcwlTQldD4udZ%2s7mR0%b6G!E zH6`V>K_c~l&C^5-!4r+}wA2s=XDbYY8MV50V#*x>8M`~i{AB6cHISc~^0@;3EOTkf zyNT5*%me$-FDeo&* zJ0I)5>%=~+is8u{gz&B&PP<8nyLM5^4flrH+b|HX5o?EGu-=^VxjI(6Jmp=DB6J!C z(p@!bH$dR-8ntJGRtVuoPvQNQLN=Y#5;q7ThqB@IRYESEg{$OVA$-h+arX(aakr-2 z)ok3|(0;oZw+<2yqflt3voX4Sc*)D3eA(=W9Y) zlm}nFA(TgTK)Z$VsVQiWPytne-WDpPj-b6lCDaG>o=_R zbBv7DW$khAOZnU>+;5+!yoK!ii5OIe()~swG0}f1#Gj@=O}P)TA})1Mda?W@d=oC^ za|NvESjyYVik`)l{i6|8JOI8;xu3IW4CzNj^dPMMIpwoT7X2gTh5JFYFRtLf(xUVr z3jLEZpK;iR-%@TzwDI84IK3BksylSrtD;fq-zgpi69k#)(cE_`5vN4{2 zRhwCUFVsY8?T%>V@9!E)=EF z$m=P@4*;80yZ6H?dmrp*UTr?M? zu%cCRe)`u%gLGpCXFN;nG>vK3BksE~)lz$7!r{ zm%-M&v_-K#{rXy0NOuwxU0m&MVntC{G)ENGN7JsV_PGL9bZxbF5U1LrCI7MLx>^=3 ztaj~zP_zoSrvHhe-dJ4RQ0;RCtmxKiuQ7^fi*EmqMR(P*=;ms-H!Es`p1wsC&A@cD zqT1&Qc&1%l?L`N{q9$5a!y(YvFZZF{a z=PEBi`WC73wN{wAt9>?wt9-9Ix-(tnzUuS~pT++dW$ztkMX|MgcUAY=sdt!}4b04* zAq+tf5XoU?qlkzEML`T0K|#R)f~Y746cEIWV!{As)ML&$pkg}0Ip!>i0rN5E@4i>n z0MGm1$92(FtEyJ0>gwva=LaWmc?lCH`p=;Bmo${bzJ1j>2+u(Nok0aUprQ4Ha_z?Z z*gyF{hBh=C(w=raKPWvEI^pG5`akq$PwI{Pk3j{xLyNV8WG}R6$rxMGK3#n` zDE&vXtN;1#;u~kg{DYV9tpTJTy<~OI{Ol#SXMXWgrMVFM=~pk|Z^JR`qN9T%uq;wd5J%Q`)ZK1-V|smAo2 zy)a@AU?4M%%@g`+Tz6%?WX$%MAbBrYvkomQycC)@Ays)PGQ-ibg_p$qfVx&*N|@gv z)p#jsOb?s^yp%G-aah!QDQ&*QIkJtHGUf+J?Ysoo4y5*8%9;>!s-u^3CWf??m-40v zsf(8irVdh9FIAWhkh*)R(sYB=!%J1>P@HypdZ}pYunT*8sfFnPsh^i>OkYR?y;L$~ zNR3|NZ|A~Bxf~-K&PGqA(H&~nW5*6|jJZ>Ix*Fb?{*r_LGn$NOY(8E60cn(%aP^F} zb&QunQwM1`FS$R&G`6wsDOl5YUqc%uw>Mm#h)c*}jqXI#0RuL!F=i-S2`4nBhoXu3 z087?>je3H|BL6?`LoyqIiK<4NMbu<3cYPb2ujb8D6rc8(c2(QfMxP%f()b z%$*p8Grc6H0#=rI39fMLp5-M5cS@tY#o*Q;xOqOfCov3XH^vN_!Clyx?mB@ZhXGyY zRReP+M&M#E8M6<9yTnU4c6;IW!%LwFuoPV8C0-w%*C@NdUbqr&F7PfZF{_t1#teln zuW3x5N0*P|V7|_)2Br}+_IfWFa{~HxgO{vnfr)mbmqIwXs!{HwlT~oC!aEs;`;S$P zF`d)N9gXSk`@+e?m=Skva*~0<-J6`G(XV?pIVoU9+}rHLbQ*|@buUF`!62Lvy@a=+ z*gX$;2_Ji4_dMt&4*IQ)G6tT*SFxjR^TFMX4m{KtGiV0)WMley2KNh^JndES0s(zq z?ImLlhRbKXWKAEqeAY{$Spk>Nc_}jQ;u3R>m&DY-%JW`In2Ry0FL;T;J=!Q=GPv28 zi;w%@*7n57wlQYV4DLUT>GFOE?h(w0SG_9c2M)^DykyKIjNI#9vW6c}zTqXXR52so z^b%*pzZ>O1*b6^HXV-d{=U}YgZj2cUU4GP6}i!ZA@>sKb&+xPrl#e6qo6@}xz{oAf@>2Awcu0mvFD<-eOrGayFLAHunq)k5 z!XII_(B#(p1DkO6Zi?xSX4^HT=hAE~%(mZTwuqVD(Myc4zDcg6AwDi|;|&eQ!P%)P zrUM%4-ju$NhHl1i^>C_|Cyp*n@+MU$Vc@!Y)q3Q6HpMha)d5ZEtq+814;*cSHpS2i zK{t5`?`yEKZ099w`eNtq;HA(!hL$^diP83HlF_giu0t>Sd6)ZQ3EH_SW+-$yrYSv{ zF6U!<@9tF@?WiU>gQ_1ubr-KXc?eFtO)*VUb-$+c^Hkjh$HIY|V%Q1NK~A!fSq}Ay zzAj;QKzAp3iSg~#Bwy0WDjXa8cqivz@*dI@(>a|S(Ugu3f|DtjU`KhgjPI}}*$U<1 zGuU0zn&U%$MpI0aRGrh5Broyh=j^65vEShvP(IE%2wPy$ zIHjpT2Q;*>DR(gq-GDi^$f@EzI?XQehS-_Yn$i!@&oIMx%Bz~v2hz|sxLsP|4gG-pO-%(lfUEPGWEOHQ8C6SKr13kO(yt&} zL8{!{P7Tj9_QyQE$4kcifmQHcF98mPd2qjzYy`dF0biA<7&j((&KVXupJ(P zS#Z1Gm49LoA8Lvj2;D!~lpZt5yMNlNI`^x+zc10VP9hhs!uXo?vY-T${KeI}ZixmZ?S^Qs)Ge>cf3RJ|DUWvy3z2C8o~#WYFP z_nXqIsoI3q;KL^Wb{?v4H_4||{S1fmyG`z$`%s$Vpv|Do!g*w0^X;dMik zG#m`o#W-X?^Im(R&DTvaO;YujrrfD$Vopc#Z+`CwW)4=o-@Rl^CDi})Qe-03{pBU8 z7>++6^0$`~6}t}${_z3_?1!fGO8UPA`}-#sS2zyFf^vaz(SNd>TSNbYN8lw;*&TX; zxfBW+FY$RvSWa)Gp$^+&Fw1(H37aq;*>Zsn(Bk_h`5U>G>`Y5qr12KzG*MG#9h$as zYL<;F$}$M$Arb(&}FQ>!FP(2beZ^RZ}hnA%i%ELYw(qUe;JI+I+$}vq+bzC{U z9aRYz8Shk6?CY4aOr+}eIEC%*Rqq{&2XN(>CaHRGIlYLgx8W$9;=ST0X|R8o51%XN zfn`}mL+4@NPxOX{qUTe~F&)s*jB@&Y8tQ`{&TJ0fbj9e;@{%!Uqi%M2^Fz@i$`VY0 z*)BU`#rJ0UdDd~|nC@uynL^Ri{cETZW8vYzL%Bi}f zoIaSUy>UFA-K=UJ!0bP#IU*QZSe6Aev_1CNB5!CuuCdN5$8^Hsug(Fxx5_HBvr31rz;L+4DfnGvsbec``|_|SySek?4{6j8iv~m zFGZ#jUAoyzJULulmfo-z?g|Slz01?E>uxQ_423T5E~n?y<$F-Q*Q*95gYmoHOV;$n zs6F7N&?K?9AM{dWcE{{~$V+s2ds(ih%hv|unVxq!8ohj^95WQUe7cm^*dLuHMZLbDX3{k)eVa~oQ|;3c|zyeu_`!DST!d(yjH3)?T1V}?SP|1GC? zMH4fN>$F$JPkS*GuY1Xu07LnPm-zJem9osB*@f7T>%7^W;o_}wOm{TR^sBJR>~b`!*ktxPL{-^r)^r<=wcSgh z8H|1vy%d=Vh`EKA*st_p842s*T+I1+usa_-jW(?Y#|(@Cv>u#3m;qe3GoHvbn}ura zU|B%b^DvR>yz0%E>g@-|G)dL&gVR@1^=K?#J)CL^*W!Uqb{Q;BQkgYf2Uq`x`MHR+ z_u%*qD(jz}XK5GAejo{gDmHIHho5gz+AByVU+*{mXuO`%Umw2NuXsfk3i^R|*8T2q zL%-s4D9XFv8h+ZZcnMlm=$F^^`blm({SvmL{-OWm$o^HgqID_A9jTvK9i?APP1i4#X6RQ!N9#vFGm{a3WKWnqpxfAed_heXE5=T^@EBBq3i~IQF?Ro zcDCy}NcYh#$%iO)8&v!UEpF8}pid;%Qft>i+TW*=pHdn#sJIv{R_m+Awffd@UGg33 zPIc}6ll+v@v_ZxBX!okV4*XEx<$a_t;@0b1w2zbDv(<`0#c4R)KFRWh*b`yyPZmBh zNQZBAnB_a9HDQ*oR$dCTd{weG%q20AlcuqF3eAUEzIpgC%)P_X?Hh}aVE2C#=5Fi` zaY&;^{%4rw6Y{@dh)-mrtUhIqvV3A}qb#4zhEbMJL8Bj4B;v`4lM=W%;}&jOJIN|Q$1BFgd>yj7It{cUxWJ#Zo}s-s*hwz8Uijd!O$qn%l2VWZYWE)D(fuSDawt(c{bVEH5wk}CQ$5BF3!hZ91&%Cy*@9>^4j~f zD0e$fGRf^-+tZ`mLllRUizi^mEr_zb%055JolXn8ly%@Pz~G{EX_PyMrTaOr7e={D zDehk`zK^&sin6>^z9Y)=Lif%n%L~)HqTID?Gv67yJIeB!^PVVo8%r;6rT0czUO?U# zQabQXLVd+#~C-Lc=H5Okl!g>YkRJ(85My^*AW{5cn%jO~I1 zzi`|RN!Hl$NOHy=jwEmFJR}8Uzq|Wtu0&vf7W(FlC!o6N#5GAND9_|hXl40m%?9Y>yg;d zzPtiuq3sPR3hl>`B(%RF0ikFF3X`Ed5J@Vuvyr4jd*fyBhn6ehFSM^f%7%6Wl3Zy2 zK$3?#>I$K4a}E4Owl5MB*-=PrWG5mCBYPZ@D6(fGk;q}eNFuRE zArY~EVmE@aG#^q@>}5z&VsA&17CZ0;_!Bz@Ni6mq?mw|7LCT3;iX<=gCL{&1Pb0x@ zc?*e2*l&^8gq0iNFJVuIhbUorSt|+K3kf(*J0nRZ?9eOWFJTXWlup<_H^E=RjzkhC z>_JGf340To~WCNDZ3m}CS~tL5~u8QNU|yW z9+F(jK7=OulwFIYkg~0Afxoovj>M$xP$V{O_dyb-?Q|qj+AcsMX?r;m(5~)4l1$rY zk)+c0T_owW-R4&KOWPfh#A!PLNj7cAEQi0eodGGIwhNII()Kc}3^;UdM`AMed+ceO zvClvXGxi-MQN||OKO|Tmz|(3CDTxG9Dr5T~NoQ<~wIGwR4M^gQ9e^a8u_IBJ%h+8Z zl+Mh0m$*f%kDVMd6Bgtp& zYe))Ny95gaR-F|{OwQhi#OCZvNWz?5k0i?3Uy(@8=3yGtv5rWRIopUNm9x9kU(ON$ zo5|VENaCCwOn*7M2a;UQPD7H<*;A1ea`tyD5Ln(Sut1o+-3p1#+cJ_cZ^t2t@^&f` z$=mO-Hxqe#3Z!J-UW6o-w>Kk6=j~jq8kxMk07;y;HzLXA?W0I?dHY`^`MmuCNg*Fp zU$6p-dzp)l#@T7=hp?p#+4PWukB75=e~W0MJJxf%>`R0c-GZ%+X8eeNg2K}u!`seb zZ!|6T`F@k`sI#eC{D4|_ehw}0#s5UhG2wJn)I9Vz!by*P3Hg}p@bviNS!f!>WQV8s zEUM@DnmUJ9M9AN&dViN#0W+2ru>x;b#QH|z${2kNrS9>##M^C)nEP7i`0* z&Cj%RGPV-EMmy0CpFlP0@Et;ou0TiA(G0|v2?~#(D1Cm|8RlyK!XULv-_Ys=^l%;m zO5aq)aD(`KXs7>G!yZO)TSSq*t%d=l;?)?-^zB-cjfqB2-&I(SW)*Qq41D@-6)NL3 z6z(a!m%^1s+;Iwo`*T~tO$#@y4^?qkYvTRaqUK>0>Vw`5XprG1sN^1~WL$+yIJ}R9 zi{L%q4F#2NqAFizZU8p<;n)^Si+#I#dLqs0SYE*W)2ZD!;tC!$Rk?7kqn z3WH^$CGXM8b{LT;y7Fs!`3$?GBD(w|UKxLjHbbHZVR@dNhatoj$oh>)to;Kcg|qe& z1ct@`dCcLU!mdZBgLbwZn+&lpVgCj5Qa`W`F{L8b1~y2w)C^$uTWKbR-_2>JB1nzU zOuHa8K{G>w)Zv<$hatTWzB0?g`_QMFUl6LzTzV(E6K7d|dCSjeJ+A%-!t$0J5e&nb z=tbs=a0!|XjWXAzkD7}+g-6ly#+T4og3>#%zKVI1C{2-|LJ=&&K>C#{E&{Ol(eP-ZF{66Mu zO1EOr?`PK5md?arJ*Z7umkx%>hqSy+uw#^2Dd!;GzBd(3aBUTf`-bo1T0DLf-3e;C zb7o|&UV$dsFO1MNZ=$=8hSVz7p#Oe;tbP{-QK<9dUG&C8mv7+VHwIxyGz&J9L7^{? zvlqi#se3%a_PYPBISINQzktW6{ae&+_yciAJ0l-O+rtjlk{Bj3uZ5pecP#99-8aWj z_jH{pZ^43zE=Jx)H)D&n?s4=y^M2S7jfziUzIv^X7EtTUcj)l~7&Fm!sI<{ph&&1k z_an)C7Vb-}Ul4@X+V~K)-dA5m%w`k4j!xKUH*Ddn@l$Ah7oJb8fw17Ue*cbIhoToj zG!^sIM89JGm}oYlwLx_kPNtN37LEG-fTCT|E;i+p(fWlqsIviE{G}xfyN!tJ3Zwqm zM$uSoB{~w@M6?LoWKg|5r(#RW%f7koq_<4{1p`knug^X&Q+8SG7VfsO>%F}tBIz8bHOIp`~_)}Y2ZE% zlP9y~!KOjySn?_Cw#*@>ft^YvmvT-`c2YKZ)!UG!IH@9eD~2a?sFPYGx8saB%rtOc z)+B$!e#%TW4ctq$$;AwLnrYxTmy*|Gh%<+q2F{hbJfyLG>(7$0JRQ4&~Xa zPF--Y_sq;N8&5?Sw`JfnO)IWALGnO`Gs{Ufxe<#|<`~mT7uV!7UqPDfq*SuVx?`P` zO{Qt(I44ykuZDxn@lI-yJe-qluBoDxn&eiPlbKVURG(}|z0*yJ2XedQZuGv;Ne#($ ze?wYi^bFQMIe^2q*hw9dyVK^GMo(xRlQ*(%iIX}dU#0i6Oh|09s4iZM zWzo0aaXj0v;prke9`oHs7hsDcvp3efctqHf?R%iww;z2I+Yi+vqazL-6aDfhwZ4I` zFk1HxDx+U4cjMd zYYYiOEqnq;@qytzXi%)fLg1sA6rBc*d#DlJ%FCCa@CxR0JSF@TEo)ByhgT3&$D&dE zF$~6s>(v!fL>wQXLKJ_Gc^x0=uDjxXun`}nLN+LLhUIvASOEihTB)hS=%wPBXVT(@ z*y-^x-r}ve=80#wV?`8H9)P6qAf`xsYUl@T@e8wNt2wqgq?PkB?&Qk_C0?4l02Ps5B*n}0A}OVpPw~YnWV=o~`p6)@q-r_5RCJv- zYi1B%TE)epGCme|;>)zAD*g;hOnkZ46ocN2U^K%`P{~;H%vLgl!fPL)-SRMreEwo= zYW~40SB|ebbw0|uQpT&QZbUwaKZ()5hpJwH5XC~_xvI}0q~cpKapJeCS}wqable%M zdi+V%KnNA_r>h}+U9}5@7IDMJ5Pqqe0ih+Wujppa&24lrml$p{06_n!!jDx zO#e6thGj?Ye+H~&K0*2DI-VYbnCJZLE_E6}`~eQg?5Si%bcHSud3AdFL?K0X5nVRjD{+Qs|P^mr9I#&2Ln%I>K`mpF~c zvwNw~JsyYkC%d-_J>yq!dd}`s$6of;yQu8Gx+dT^sTis3eyw@zmUT_Y?ypxELxMux z->5nuoCT#}TVbiqPAPF9TX2rmZt`7F8u?)Oi0g0QJdB{$~tH6LyIm+?OWSDVD0Sse@@1ZU4AQetlnPbx4UjJEIx59 z^rFc(V4K?a3T&~5Q+J>1GZ(u|O={G?w8W++xlEW^w^U1_R30YrPf~|nqM1bMnDaD~ zO#Qw@GpW=GE|X3@<}#Vo(v?~jr;5&LHdV1gOR}kxS7|1fdX2H+p+%~zYm-ksbG4S_ zQ#ZPjLTclcT2hhf&x=1C9;q(e3AiOrO~b6izhY{*(`u2LV@ylX}u=)uvu`PHR&~tNn@TKK1BTTGBeT@6A3l z+hy9MDqUc0QwLq3Rc(S|`#U!6j+c6zi5;9d*zJ1swCO?q>uP;l5fuJHAM)RXj5W`;HLK9yRQ~&O zsP_%VIsZc&PH|iiQ24P8D{u`k2}$7r3{w85@KEIQOR?Gd4a|o8AC=d#;AU(pufnG0 zjLTrM(Cb6w^^92PqxX~UBwy&O=VhGa*C3QazwkjcYeDmW;=jI^fw8ZUZ~Fzhab8;% zw`Gs6sH62ZTVYgI)X;dFbJhpJHPQ>ww)+DIXZHA*C#@Y3lw0=O-GPy*Xq!GBEe>HR z4kp~xbJGT!pxq)aen+d;{AR5!PF(HUa&0+6>u>tM^&DGm8MM0#S3udt+Gx$DM&sw9 zUawQyb>`Z)K!K#YHy{Owc=zjzzWbba*uEz1(YaN^GKb6d>=<8;CLAOrNV;1!Jds9KfG1xT^n(DK0LpV2Og4~0q15E`DbKb#EHcd}d zZ1pS_(A>XFQ7c9q{THMQO=53WJ&$utZkf@EH(>I#S;57|9lj0GbNFuA9KA{Z43ky; zhEHF_7X@Z9DmqL$ayGJU+0|fR%^G~vXLwM&*jzW$bYxxqSvU{mW}4otbYadk!?9z7 z`twR!v!@K#So)Zr=XjTWT)8ug^37)Zm{Gj=aAy0M39K13 zV9Kmn!FDFi10V=SCVqy?PDYQ1fq9H)m0`yYZMI%zw$`9WLpfJv`fCWInjVEDCegj! zGk9CS5RJFF^l9Wuy3ZQ>KEYpHe1-k_-RNUqN7K92KHoX+a$E>`ooQQ-v3@bBQS6%f z2W8jgy3hRze}|}9SDx8}-S*yyTe2mY_Dy@_@PayQs;|axn!+9p zU9c2|`=E9G{+;nzZB5uqZT46TlOLFwtau;UmLHhjTCw|2l%6zgDV>k%t*USb+VW{X zKYFbDDhSRstEe{+7i%rgH9b^s+tX0d@|C)6+hgvxTwS;Awy3S@mk7R$_*}(AclAX1 z`G~4@e`|v6F=|ux!L^r3w8ioiS{chE5`o(=#VuYrWU#9Ds2PoX)W~v^!r$Tz(idY| znO?PruzVcLZL%B7H?~80-`e9?6eXWzl1e^;q*Wx-rq5>Kvyjrob-46Zsy+NOC8OOlm6>Ma;_s*d!Q0c+f5=Gz0F%#vFD(44AvH4NV#)_>~r>lbAP9k}x$; zN}A)aO__~2&eLWBwiz?`Zk!6t`Djxx{ZLzBu0?r+c?9JRW*cnVo2OCR!E``*M>7^S zJDIg8?`aISy?i7$yvs=5#Sh>D^Bqom#tcK=n${Rse9DP!WPZT6k78a%K4I_=@jQln z%Jf6awD}hKjCmWnv3Ud~Su+KB(36qRn{jAgFt=h`Vcx^`T{9fDADY{s^{qJ<+rQ0m zX!(zi=fxix$;U5nG!DlxZi1Ssu#-vOXfaA1u&+8B?!Ca071~Af#-4^|TN~~@Yum#~ zH!Y9s1u)!Q^J0t0Z=?ByeHm?fXg+CYBHvSWQ?@(8>81IMeFQdpYd&iiBi~2c=k2Y? z_tkvCwt#Lw%~#lMksqM>%AocTI12}wke!JbdXhmuk4%aarGU=aPFX)2qOPB#!ff** zHfB1u){RBf>vxtv3x^H(kPLbmOmsC62Bix5Rk}c~+ylOTXUobf(DIK5kqhdUBbo~N zxuT2~^;E;m3DHpg3aJ#aJhv?ts)o`%P|#VK*zIVPn)fjXfjJQdu&0MZaUM$5Ylk3W zi`-(=?O$MVlJj~+bN!GY|6ll+n>(LXFdjVITqQwnD6~$=-NGvFsn?sUP7U%;qiS*G zvnZ*$AI`U4iu#`*#k3Jr@tUJ852+#!|M*5^;u_}IERfd7Rl9otl+9jI%zW%8kyO_%62CrgQ{u4t(7{_;Nd`& z$Oy!P_oz4qX65cfn-<4SIubm3?v@tE1hYEd>eY_nO*ITm4rV8r!@uH4xR|;YO8l>J zO&z4hh2z_9|HrTghE}q&p#yi)HDmTMX;mV%XCyhA8A>*!Iy8*t^jxWbNpal9)C-9DsakCZaW|wPR46T0aSgcIxa2 zn1rd>XfCOj(I%0qp9s~|$UV?JmBOA%r}n`%lR9EI?CI2f=twp-Xm`xM)ZM!vsMPmp zSxAl96=9`T?SSSzdQgt24o3UuQ%Aw_3#sSOyBAZ3qZcow4u#E^Q_1lF-^-O~+1<#k2y`1G z2cic(jI_XjY-?mSG`$I2Zj ze8fs049VxAJcRy!5z2EItc{_Z1HCUpX^Fb8P>7aahq65izX|17xcxSi&*130P<}#_ z??c%drgw>CHzd18@(C2iMDjgs?iR_9=)>+v;C5^z+hEs^i{vD<+#`}NM&WbWNVbLB zJtLWqsk2ukKVe+=j^r7}8OhZc(+QCr1}pnUaxBJWzer*z>>tSjjP4zgj6_H+L=HfJ zEk*W)%{d~&FiIzgEW?!|rdnlI6Q21~xw?JVdq|6dZ<@)mWkL8m7Rru0`2H(c^p<|R?ATcVpg?$4~1i@ zWiPvG#P${d<-i)UmOG;^4ljy5MS(+Z)S$jl#za4s{?VT4X%=5d5~GBbN(dY{6~WAJq< zGtk-7cp}f)R!^S8l!Q-A;@$^s3$UWJaz;Y;~;((ZFq{0UxPvX z*^3}QO7PbMgSb6{$N49S??7M)X5K;vlgvDaK}a!k4|4=IT609nArytx5&(J1lEF?n=u+K zwGFBmb-W+6aJd@97hnu6GaKMNWM&0A7%?*&gCNYD2B!&T-iH=j#r+T=uGE5fM;sQG znFWZDdO_=5FmLP$CcFc3ThkskOdD!-eh(+MdQ*q#RX@Bn=2rbBs63{AR3&Cr{jegY zRQ>oY=2QLOC^^3Vl@^#T^^4H*r25|*FhA>Hj5a}~51MbSwnJU@kz z8M()}AUeh9sTYI$Ibw)Tbz(AI*m4%$EZ(KGEx@>K+I|vLc4`hN*fG(h%UjA-(D9 z<|WU?MOO5dt9v5%MIO@IUeDx6#fskXiY9ku6~uSFrpb-MkVo%%Rg-&^Uf%b*HpgGA zL?3uvn|qtOA9`JzE3@_^uWNga1k^cNZ>rvAykU;NR*60~RUbh7F3L@#_=&0F6%i)0 zrtDd9734yYXP2uu9?x$stm4%d&2?s@Z*gP9N^SLBbLoyYX#Hj_Y;Q2pBN*bUC1}da zI5mvR`M=OI&jPLK+*}g|71hY+S)d!O9^PCnK}CPous}Ckx9E&Rw@oEOtU3ytnaxe% zV-j1jK#iQ$Tw{ZZxvXKq|No8JdZXD^HmG=xW>`=)8veg;u7UrLSi=Gxu^9WMd078o zA;-L3b0O$voJ(rGUvpt~P|*qbJPWjDx8|BQLB;m0VS(06Yp%%$6%$y)0^Ml!;^yio zsF=eV7U%{K7+$KChalRqcnSIM+M20|%ifFpE44M;)p-6aFVv=AM3clN*x=Y`O5?(Q zU2RCU$jHaF=?ctPa|e{<)7m;}nb3@;_*re;Xo``Uhv#(ig|AKGu2DXyl|In3y-@Q} zZ8g>GfXDwir=VDV-emeLn*PO$k=dW(Z(ExFwpPwn)2R90n?4=+ z-)m#Kr0KAfzKNzErfDg;sBw%K`KMN1q%vzv$;I_Jl<{jb8pYx!m8J9sWDCRh*ddT& zsa|&`lq1QNB$b2mOehpeHLS4H#RRQNF^y8Wbt&B*O$x(zf^yp}m1|3~6P2qmz;#|Z zhM^9nm`1rPx|Pz?ku`^)ShgwEb9ceh=$$46GN4pP5q~oZyR~ykE}*RoVQcG>+pRaD zM*~YSebCkprSwCzbvbSA_Sma~f@();xITOp1%Vm~{L2>@CM~Zb^=%>DDlJvLDMEFf8YkV!EX1 zi%aRNX!=`@)}_s+ovo|3w6(M(Ptw*~80Cw+t@Rj}t4lF`(AG_*^hVm6!{NHQRCg4L zap80f!@R|dI`^(CNv;C6W})VWQZ?Jz!x7`HrI7Z{Nk&om zXpHmS{_x8ps0T|ijZ*okQhG9#H?mW!OC?=m^w@o@B#Wp#9Q*8vQY%*2W1#$ODW*}* zu2)Lwl~kU^J+;p5WnAfCPrX=@)l_Z?g_r%FdIMc}trXKJmESF;V_fT)Pub`9oiZ*E zm(teyO*7^r)^6~%73Q7)VLpA~YkBD*ZyjKn<+bSJw|-BZf>uA3Vj89LU#0X#R3>3Y{&C9q=0;bEsBVi@;4Ua%b?Fb0E$p$w9)T3Th}F>)ImcPE~>@ zffoAvUHQ|sXsN&4mA_nzRtc`S}b4z`K%XiNN z*WteU3tj0{DxQyM1}32t^{wpcTAY~R;&+n% z?p6+RWv3*#h|Npz$X=kozLoP_%^CXZTRFc}dBcf(O%D{l%?3?E1e>e@!coxc2`^@Q8U;e=jR* zT#MKA_p!5hsB!-&hK{VYZ)fEfSHC{NDfNl|f>x4sI;x*0I5j>`+98-{ zHLh%sFWE8O0{< z4$IrPS!ZyR;>1=bhoi<;Y>mgO&C{$e9y!&;+n}7v1M1QXsQlZuP#(0Ua-TZ6k;<&; z=attY-&7aVC>NI<>(WnB`N1-jcdFA116<4F!eIM4`Gm@>*`dx|7<}6Ucl>oRjneb( zb?ID7DA#p`^0;Qt=G8tB$9qwi$X)8BCmPzr(Z4Z1kcoZqfT%8}kD${~BOU5iqKP|L zI@J~LgAimmDuKzBFpH&^8*ytg>~7@lD`aq8aV?rAOosiaclQ%AvQCeR)<$n2WK>;o zBO0|a8OA#VzrW{^b|><>YfcR+=sV8>t$DGz20QIx*04ZpHZ<2%1QoBbh6SyE8-V!s zsSDXj3~I6=-M1Cu-t`a^ryF!oai@OGp%7y)0*}SooD=c)7QzY%8)R?j*+ZtFrlFcw z(e_ca$~VL;532rz{lk#+*Vb^=sv&(fT}_<~l^Sm>Fe~Y*w8_;obXC9Em656jd5W%n zgR2$|Ztw07rPd8G9dPe45&Db9N(YIyJcEyE9A5?Eg^ozXtv1U$&894SF8IHS#2i zJ9*KV%jtNy7p*yho_6+PXckf&;l;>2P2EvG4*Y?A){gdK(oCkfix*So7+l`Uu3k)= ztEoH2iy5;M#ofFZn-?hV?!~O(pD>cKUd);OIkJ0rQTx9g`j5_8hA_nU{~_2IkN#s^ z*#862f85rZpK1D_2E716|9_!4(Tm2M%b+KD(VBDV_+T%FW(dVYycn6SDNgZX!hA>F zL%oP+6?ldoE%zvqSxEEt{AZw5CV%FS7-6Or2Gh^6zx)-(o z6VQKj&K`w^`!%?Wwi}S2f&OD$c=a=7&G$u{cCwbAD zBE^%v7@F1;Pw`@8I#WE=i(-0Foae=a*@>1<^J3C8vG#N?rpyBNaK0DQ<|#H_;6<!;4w-CdEZw%$biVF7{&Hd_(a}FBZ&S+zm^-SYam9?^#}~G#@gmv%Oel zPGsYAyjV1IIcLxHVhi&(b3fiI=exh#J;tCP;*>^yKx;4r7N)e zF)g_JuWd;G#@)Y+wyyWeIQ$vq4PG>65W~93i+B);cN`5;k7r}nLT{xvy%X}cG{kht z^TXW@>7CHT{KUBK-Lz=W=2+hEMZU$C+Z$vmZL#J~ze-;Wj}JA(^ueQabwm1e+8RMy z&$>e#&zrEsJ<%Z7Q~9E~LGYA6#MdGEH4QP1vXAQ;(l1kaS9<=h>qQz*F~X8Z{5a&lXo#mH?;a$vR2>}@waeZO#mmvCFB)Nb4KcYrSvu1- z8ftRUA7Q(>OX@z3AL z+YQA=l&-KD?nOLc*NfSYF@QSqO+f|6H_rmC`K!4m5mbE58W!kAtLxD(RcsYhWRcIa zp!FV{8(%hr+;`e+$L40qprQ|(u>g}CjN0RnE09qufYkEAk8zM%0i{+&UDkoAy$lVl z$JDaIdQ9!EDCfikrgi}yNE>2m1)SQ2v=x~BxCa2LRndWJ1*BRP9jR7;s#VdUY6YxX z6(ci+rU0u|(ZOm3v|1G%tyX}mRng&U1-x1n9j{gZtX0tgYX!tw6&9N{9k*5hu2s>2YX#(56&<-&fUZ^1p=$-~ zS`{6;RsgS6(ZOp4^jZ}iy;gv)Rng&V1^ikS9lurpuvO6kYy|{c6&=A=fUs53A#4Q< zTNNF{RsgY8(Lrnl6k8P?#a4i^RZ&-YaBOeHuC@!ttWXm>qmqw7SfMlzpBiRa2wkkT5t$<~#Vzw|8&{+Y@R>g_}VYULAt%@}T(rg7d zTNUehh5*lYJNUG>@Sd)}3+p^M1kaY?@(cli*_KAB46^MBR3_P0fVO2Dyy7I}`8ZhHl7dAO}s zyoHel+?GCQ3vk=}Xlo_LO+dG08y5)hwr^4Se~27-TUGvg`+#^`8l^Juwm(pLLRTn* zZ@XC;fZJ9bq0AZpZdKU>ZfTUt0NnOO69wD~2)CP+fw>;-_N@YN9Z>BOKw*t!TW@TV*U#7Ch+^Xj{ z&Firx11U{ zwP4Nwb-Oc_J?d8Hj7QzlC_MvpdoGoUx)rc)N23_4^-vB0V7Dqd*sXwetD>Xb3UIe7 z>ZAbg_D*`*5qjX=vci5eI3Vwq5zrHOw_niH4wx$f;4Qm?mEaMM7l^kiI^wMWd8;F! zFLuDZ&29yAo_Wg(>zTK7Nz-87_Cph8-U^_%Y~!J~0_rVAJ^(NR?Cm~iXg&6p71m>K z>4Ua_y*&+C#oh|Iw`_v}A@^1QzEx3efqZ)%8d^`jWrg+RTl%0akZ&JDR>`*l^ex-C z;{fd2k5FSh`<4~fvu|mXyA|x)+RkWC_N@SZt9vgn&kTVG`YlDg2-|}q@V6A*LIM75 z8G6?9Z&l6nZ|Rb8fq%OfO_P5s0N~QSiwgwY6R7M7xEj}nodObYX_U$!;66d+ia}5Y z0@o><9z!64fvYNxfh&OEYORCd3MjZL>hJ-B`!PLD#f$+4SJh?>!%r#(#EgKRfWggn zfhS^c1sq(q!HgjXR{+A@YzrjZZPC!qMG;82YRi*w>4UaF!W~IlB;g8BxT*|uM!>>7 zlFFWitID2*OQTc<3-=5vSE5n?!`-Y58ty78|GHy98m=mzjYA1ETpFb^Xt+;PnKWDh z4wr3G>KQ!TPpRyAxT@@VxHL*-@NfehFUrFe0C6`fgNWM!HP#bxRe4v8ABea#N@Wmn z2UD3uTmcf7Z9?@7ChkNk|Enn=6IYcz6PHG*3?}Z0RGz`(6HwgE%An$2No7yPRpmQ& z#-tQ7QwDJDj}AP(GzlMhRPu1R&|3i3AqA9?q+2$a{HmidPc4)zknWtkxQct z2aw!RXi`J>H8ewufaFf5#d~m^3n;mpEdrCfh!*e0Z~~L77GJ|0116Vds0>W*<5VUl zSHQ`2%F4+VfO09~W$W9V`yl0xrl^NMP`T@A`a5iZ%2m@Il}nd24ODIk;VUXvz{>Te zWjojcEZ3WUm#YD2xtmP`mpd4G_70p(fy-6X9+yj(G!0ztu{2Fwu7H>8O|QmLECA+u z(+3ZQ2x9JL(?I54O4Hw9?E^AbO}~wK0c0*+a)`mq{TH$|484X<=nu@?4agcYa|O^` z?~l-20X5hAYr?Ao0XBEDKX7wXP_h5U&IUJE{dsOKozOJ6xkJ!Ixw!&xt~X6^u7I5D zO@D~i0(9eK^n6Sx@N?C)=jYNTM+pGk{~}w%&}-;~{s7R8F;NttDLArFwu7IS=rM-rs*U$<5fu#F7vP#kwpme=IqI3l;UGI-9 zT>(sYvp>*ue}kSK(JdfNSN*L*|3TBG6W&pQrrQe>MQOSMobEyt;{qkiYi;m!RdhUE z0Z>;(eQpM#?s(|gFK~7MQI{3g6Lsm5QG=*^HcgYLD?sXMn79(>aR8>SijJu(faDw5y^6?FvY{Dmv1x0JW>4L+uJ!yDB=?t^l^H zqJ!-UXuB#p+O7b%tD?j03V6FJI^M1TxT~TA?h1&zDmvn>0J*E8L+%QgyDB>7t^m5L zqJ!=VsJkjU>aGC0tD?j13b?x}I_|CjysKgx-s#^nP`Y5qt-;{}@-8dvvLOMpn?1{Q2wH=q39F{yxPtacdSfyp5=_p24fiufh-*yfjK>FnGsPc>pd|1Q1@fahHXl@E%WP zPvKSN6;K9+mqw`!3hxRklfo;&@Ujh7A7Xd~9Nx{n0EqW#+S&p70P(6V58|Z{-r)em zI~mu?3gQ)zc&9pBxAIX4P`oM{Mezz)yec{tuK>oYqJ!}YXuK*q8m|DytD?j43V6IK zIv%e8$g83Q@(PH&Dmo&s0LiPOKJ5gPcM$@#p2^D!+XABqCNKNO@c@%|CHrtX2NO_U zHy%7MfXcg?%9r3;3shbm08izmQ7VJV`!$u{rZTX+elUsU6>xb~)TIkx-U{3VSr6t_ zTMy%81u!pt&=$bFgV01VxB@b-w!!CATwj3ZRa-a@7y+Aif7mS&>^g&x- z^DacTKsK)c&a28nfpA^{omY3VzCQt;_a@r%cwV*D38z@#dFg|;fahI@tcweLUTx#! z0-#q-Yg{1o{zzLZak>McSKE0)FMZG!2)#TITwFl(s1wdaF9ne>*yy%F&0;I3jI;5|F>8qk+`U;@F zDmtjIfa|=`wHN` zDmu8YfbOfJqx%Z*zA8GruYm8XqT~At0KY0az_0Z7q9gnY5WiaM5WfP(uZoWGD}el} zSjVXa%I_-}a_cF-tgzSP)&rDZ?k%1RLHX^3D-@;t3NXKV5(*44zXHy$ijMOu0R5^M zD(F{0`c=`9eg&vsiYa|*0M_paShb$@%L?mRzYK_LDpJsZ{zXIH^ih4={@Aq1o-V4hMc)zOVdB1c?)8PF+O4DERt_Q$hwn^w!3W&cSQrQ!K zRe3cIM-YE$l*%Cf9)dMRiN6BmFWcZkgUDY2^H)X3{FP(9=%BxHoEIJSSC03h!~V(~ zFFNk80Q{?_9Qap2{#8-C2=wn62*Eyqy8)noSz$f;m(epypnua?PZj+u3%qim>|a^v zMF;;C(0|o5E>?Mg1N^Uw4*x6Q|ElQtzXAZTiVgrQAONcfNDki+00FF`MhOORcZ6U) z1DF-|NsJO0z>JU@z$%8k zWC0GifWyVEf+ygB)zdIMs{sy}5zrHGz)R6Yalir|uqp?JJYWG3SVeqHgj1q`2&|$t zBm&F5&7MprE`j%X(J_JLelI#Gusq;JM+FvOfz_1m2ylV#Wt5%^%nExqjw*1089k!} z7kD6cpmKo)U|?0o+ZI&IYA-r6usq{MhXxj~fwgg{Y+wN#SVad17SMrJbaY?=9#}<( z2Nv*wRn#Z}2;L7N*x9(`10a|cb}jCe00?IEj1qw0I~nC8oGu^)t1@N}598Oo=n%p3 zx)&WISl;lWg9OW)UexIVOz^98>@mUW*kghj5FG;(TsH)ci3t{Pg1uvMg5?u0I#94| z@S-CH3sAw@Sf>kE!P~)%^{im^f z8hjW^T$G>&tK-0El)wh7=%b9h=%WNUSZjTh2`~C6fezMMA0^nqD*7k^4^~m51U+~O zLa<*VO3;H@VLd(g6CWk$!A~*D`fCPEFHb5VFDuD3k|J@2&*j*5vC8?0z`N;Z4n|Ypa^Rl zJsSZdJe|suuvh>itQ8(3Orul=MtC)qd*E~};0XIbT5&xANLWR@^y2elkc3rqBw+zc zSVe~t7O;d>)TjXy{)~=2Oqdnc!-N?S9Rnt8U{ztl0-CTYYt+CAcSMc#IAK+uJOuZe zO)-s9893o1s7#!&fG4cVp&?IL02Edg2NV_%g|*fZg#}1q6*WvSh0mp@RX8JnDXeOq zDa;7y2~6Re=xGYhI0C4!w$U&_6@HP*o+_*rlQC036{b-tgDU(Zm5KiqV1?DQ!wL(y z!Yb-pW`KpOG2+&Ph1He^3)2T}0W3TOO_cpBAPch%K4VbRKntra?G)I;htQU13#%>9 z7N!rLb^sTigKQ0htD#jo09<$_vd#hM!rsB?A@BpdFh$^np$)$9YBaQ-FRTtcUzk>D z3w+_PX-ky>7*^##0mA~qFh%#a1c>1ZT##9h7*<;zF-#wH2gYzGG^t^5HMB|xU<@xt zVS$Wc0c2P$1_~J#P=-}>m|p>ASVhPA6>x^tO9b6O02hLX8_S9iMgRq`DOrul=b@&-7-^q&+V24?3R2kgi&#Al^XE<<&Sz&vk z6}ZDRN@Z||cR@##J1hVXJ7onA3&_JN8YK@4(8DS^^ssq6#Kg{qL2Jpj|GK|3^&KQ2F)l~KIkC(t9vRF-fWHDXRG?2xw)AX^J z83JapH%(@-09x!#f6Q7?i=AoH19Mw8c+p{t1>9n-b=+bBxL8H)BFM$RF^&`tH;{{2 zVLiE+@i7jNi}|Oqlw2%87ppRU2f)J(>|zxiyI24(R?)$W1@vMS9lcn9FILgviv|2* z6*Ue3j8B6TdoeDS0WfBT^#EhW$2b5mevokxU@RaQt8!pSFcu(;Rdfhr0mE2D9cn;~ z-=%2}F;>$aVoaAb4T$j$V_^D4jDmn->`gCc7lASMrin2YaEzU4(+#NrWUQhC84F0p zDms#}0A;MAb`dP&$#7yl%a|4RXzv?6%Uu%uzPM|G9|}8|u>fYg1ohn${NT4| zf?w|TO7Ih02QwDHjH&Nn#sZiz0rhJm@(};n6Ut6%-Dt{_#Nel1V4FnFk=DC znAS!o_$8x*84F;>EORhp0nC_|#w7R!qJtR=V8(1QHZc-q;}ZNN(7}uaFyjX>vJPe} zfElyh#00|_K^)9j05fLP7bf@x$3+Q#A>m-g0+=ydU!35F z4-RH5fElywiUeP~UzOlh)zt~U`F1d40nC`zRwnoc+rf+lFyo&Q*R=`0n07E@0nGR~ zl--cv`(_6-7Ql?D>tMzLnDNpWC%gpTB0r%pV*$*V-k(Z-+7*W#V8*w>#_9y$(XLJK zWvhc33t+}<=U~PHnDHvKdo{sVs2?Wy^7EqvUt6wE@P(s;84F;>3vsx8lHrTPCmhUJ z05e_!L#x9K->$6*GknkVQkdauBM&ncz>Ke>`7pybFCRLXu>fW~8l@g)EPxp^qCdk7 zUj+OeX82e>h%)*JJ<9N5xQ#M=+8jn1KF*Dz3?Hsal;M-lM3mv9#blJ>v%6H3sT+dN z-=fTuNHS4|&ynIN!v{4UW-Ndib1-vJhR;~?QHGC43Q>j+Ix3fYwrd3gf z&l5b%SO7C-#4Vx>@BLdL#$f^e$Zv+Xsvc%6fEiP>Hp=iuv;<#R-8{@#05fJ~JzS%- zHQFF)6J>a}H0xo;0+=xy zd6=;PW_&gF;)p22tNwYQksw0{A{cq9%I z2QwDHj9Kbo#sZje5^-OIp+}=TF!V_7j555Q^)O=r%$O>7qyMA8R&y|80nC`C_hL9u z>S4wLm@!N5$Bsez|8e);QF0X5`*+`-4%0KUyR$)?cXky}K-yg)q?HiC(kg-yAdzzx z!2*-BWugftm|(!<9BhKgm>i7(6HGSAWCVzu)B8NPZg21R_nz~<=lk!Ea~RF1tM08^ z)z#HCJv;ZgEhunjcY9Fy0{`3*6u9g8dr;sG<<6kM4Z>YPf%oUTg97iR_XGvr%ICME9Lx>r(+xI&$;}BxT`xG&!G3Kzr^Ar8?*m8`T{>JPUugu#{H4kXXIcZ6i zS3aI4JkYTr=2|#$?Hq4f_};O-KY0v?Yi2E+;f0lc_w^VjbJ*M;u0)A{2QIbNe)k>n z>9~Bl`inQI3ue68ZZQovrv4&*(srHxWI1hTEkwGKX@eV{+8-Hyi(s(v(=MA=<)gQi2+dL-K9JAdGeirl>>65lg`jc;II|H^G4-R_$ z{;+Km*p9&(zoFS)*Nq2r{YCnu?RNbM^Y_&(nvM_pI}C1k%l>dv8b5$r#@1#$0So<3 z{Y5&Z@gC?g-U`1m#A8uAO*Qj2@xnbFAv+CD+EVnNt`0=K-OSZctXRM4FR}?Ff%U`2 z{vYu+;%WCHp1&aCnaH~&6jS=^U%|yyia5g4A`aEeh@GD6vbSvBUthZ^ZqEgF#`6md zEAZWnE1^K=;vQa^ZB+9>$Ho|kaG(Ah18ZUa@#y)ct6*IYszb0Nw`4xENS%{Npeg(6- zKD_)1|7$4Qcw^o=5^L_5nqzUOv+!lwMq$lIa3HUmVtLgR%R5c67HWzWrsXbSeWxkL zmjn49}I>pM*`tv_$xW~ix}V)+sO#mUQm^CLzqubN_c z)fCHr`##1dpT}#IS52|J(-do=rdVO)Tn;Weou=5{jA66G=<|t{cpo}VvCuTdTBs>j z*gCffEu5y9MzP%$v`|g4ywenGdGagN+$nb)3WlksSYatM+}2W4tgxGAarA1bDOT8B z0V;uS0`^eI*HTlg@N0#V*D?yR6qe;~go84@3~R&admgQ>?I$d8DRTVc#wm z1YV-x;c>5)!eWI(6!KmRg~bYo=K4{z zI)%jwM^+D0WwF9Bm(rBVVujz=^8|RcJD-gT$JMg{?Ouz2%6vbug(72x<8y}rhN;L{ z;Sb}sfB{9u3MUu%9?DZY0sdGu7ZB7^iM4P>9nJI3@0kjvaTFQ*(^MFg$5CSJEM~~8 zt=;cE)IYn9$Lng}dm8|OF_hFJt+i%UpTzXD4Sew$uY=bz-!`s}mlo=b75<$2JC82F zfnlmMRyeC;3hN}=>!wkIh8h?Y54(f~*wvyb|9LLjf zq;um}(j~As?I|3{Z;mQne(bAUqGrCqCCW*IwNM(YI6HSaDh*qPIWn`jF7xo#QW~r{ zuk9e1d9{=VE6#7@DGF*S4OU#BCHY!PgB2GllxisrR$Qb|uB9|saeak`T1tZzH&AG< zr8HP^LxuL*V{rKt7b|qtQW~tdL}5fNrNN3DDU7bAG+1$Cg>ki%1}ko&Fus=3V8u<_ z*vpA}B^Ni>D|t#SrNN3@bntRpORwbOmL0sTr+F=u1}kordj&>gC=FKJsr4efuR{mD zmFT|SR$_1X&bZ~29;k~x7Z%thIKqL~)PRMtbWp5A^CLXEp*bj?rrmp!bq|U+ z;G9mL{ukmpDBhKz5gif_8norHbKlDmywH_+O*_%Sm65t%v|Z}{%4jXRFYU;>*G0~7 z1D@yW4Q^z_Hyd0+C$~HBnm#4XcP{@v;BtO6pC>b+tWIe`G@r{~@;+TIjOJ_jdF%yC zi=z2l$29y6qCw&BXKiWtXSfot=_bz4KZP2;w|yG^pTgM#6X)!3kdq6-L1XZDSK_ro zUd8)Ez;m|&T^#uwdj5xCI@k4t_tDZx!E`QC32(`zlY{A8tP)k}J0+OTMa#{GKL$D* zyjF^OZLSWF9dNjLFo6zT%`II`?d5iX2I#fEf+1Z)t!@~wS|gaKVMNcvbd6vmUCUb+ zqSwQ<=6?oi4tD`N|Er{toQl!@Hpi~j?vQrv+uWoqlJ9dGvqthu&LW{Q*!^m?-GJ5o zxfvSCft-&I~`Wy8@RXK+U~#>tylnJIMe3ssEoajn;C#+%fItTDi3}-U>rpJGYk3w*zrvO6xdq@lG4$ zuRrxyL=-vK{{erw++_9lFlStlo6LJ(vix=U3v-is4|M+GLH?4|-xORCFZetQCk*&| z!S7Rlk3I;~7yQlicH8b8_sd#Cnuw0Y2f7n3#O}?HfcjY$u z3$%S*YnuF>2(HPNK~1*0Ca3-yPD-!+gqQKY=HW)WihCP+t(2;JRyZ~<548BKxE3dJ zt$0o*Xp2)A{qr(Gd#nq`3$Da9|B_@qepzfHQ>^Z2b#9ecub1T4)jsQdz0^Tz0_`r(>k6jsuNv(B=G6UxoD9El z_tI#WG~nM1x|i-V_+EN|-AkLk<6y7hZZvxj*sU@6MzhA?8_gPnZZvBSzR^sx8x22w zm8K8A>ui0s}ZU#y^my-$8A!E5>l*SQ6Wp7*V2sONn_vc8_B z-CXH*tXtaoF}y5FbWdW})h0>3y78LU=Z&(#g?usnY{UhrAzYo)EBTzWt08nZz!M#8 z&k{YsO=-VJ@Rs^upuv1O5X^(YT)m}^WH1i~n`tjJmzS%Dr#J}mq=?%RU^Ypx>X^rzHyEZOD`^O)j9zA}Y z%p* zhBveeZS>XbZvF3DQ`=zo`sS$P(RbmAXZ$y5Y&sD`8CRs0O>Yf@WY`RpRAdI9a+S`S z1n6?A6{VeVUgMz#r%Xr5WCz&WBZ|0I+SvMG@KRcFEe_O6&2@SB9sO@KQuX&-+i0pF zR$Y%b)IqGeEZ4TyRT%!Nani~5OVl*1>M;!rkGXU3mw3Ug2x7cyc5PkbG`p5=hKCSN zv#Z5vcC|Rot`?`+Ri?HBBnmfzQ~v2EM5Ot`cP&n{t8AKG2e1Zi4qgdYoLAzz7AM?Q zUeN^~6I(E7Uj5-LJf1In*W!e`TAXm#YEHNd2OmaR^Idb%^8nrV{CU5_a0Jt_iSPmy z?g~`6D^TICK!v*k748aDxGQMimZmD)6{v7mpu%0j?u+nAFHqsGK!v*k748aDxGPZM zu0Vym0u}BGRJbcp;jTc1yMk30;^rTya95zhU4aUB1uEPXsBl-H!d<~*XsZ&aa90o@ z@~%LIyMo=|VOXHTU4aUB1?72oW*c0BIy(j`+!d&BSFru&5bOw4xGQ)BgYj6P!d=16 z7~CgQ`_)fUXcfwu%y*T)__)fUXcfwu%6$oro-*>`Yz7y{9 zop6`$gu8qv+~p6!6X%a|z7y{9op6`$gu8qv+~t3TDxc+iC*0*b;V$0^cll1Z%jW~h z^#k7tclq5o^&1Ah6YlaqSPx$f2fh>T@{h!oxN+b+;V%Cn#u@ldxXX9KUA`0U@||#( z?}WSjbvM9g@6dO`UH<0qd0^-};V%CSjM>4V?}WR2C*0*b;V$0^cll1Z%Xh+Ez7y{9 zop6_b0>XVd_J?D#JQMqs4Lt~V`A)dYKLRu2x!C^!gZzB#JK-+h33vHUxXX9KUA`0U z@||#(?}WR2C*0*b;V$0^cll1Z%l{f9acPb3gu8qv+~qsrF5d}v`EO$Ol}GtbxXV8W zo!+a-cfwu16YlbzaF;(1eb~3j|8Q%3C64VcX7m0{z7y{9op6`$gu8qv+~qsrF5d}v z`A)dYcfwu16YlbzaF@?VH@|E0|BI2BcCPP)yL>0ym;}<(PyN>U1#L+%r_P8 z;th9@a2GL7@^hSU7io}imtsTS33m~sId8&UB)=u^guAq;E$@W86x#DnxJ#iU?}WP) zDtRZ|rO=5#o}h5oEr_sgdoO@;*B1!8?f@@+X? z$%_aa(p~q0rq!m>T`XH(n@V@F?B1FWs!v(p# z+H2sy^wW4P-qd*Y>~aIge@@Ia(u10Unv|4wWmRIve0i`)))Mgp+`2A?yr z0Uq}nZpM)=yt6?@QxF^26bJryVgsRy4IILz28j*iOl*J+c#(G?x|3a~WP{jrg zLFaNS@My-w2684gz;R*!AvUlnKCS#;C^mrpLu}v>bS}3K`fp+bITIV;xUl~a8`u;} z&;NyD1L!}*1`a{za)ZPMawaywalw6vVgs9$(f?Fz;CLLyX5klJoDdsO%)|y1GqC~1 zOl&|g6B|&>#0C^Iu>r+QY(Oy+8&J%|1{5=~0mV#gKrs^=P|U;z6f>~_#Y}8KF%uh5 z%)|y1GqC~1Ol&|g6B|&>#0C^Iu>r+QY(Oy+8&J%|1{5=~0mV#gKrs^=P|U;z6nO^^ zAvSO@&TY=b23U|Yu>npCo_>f8{EeqS6&p}vZ$NB7F%uh5^ywO61JBX5i4CZ06B}TY zygxu};Agu2{}vm-Dh;uLp|$WeNNgZyVgqc0S1H5>)X z@CTG@coAPJ_T|EWANVH!Fg1h z+6G$zyl-IJYh(vkT~4`ylj`xkH*dsV?HO3pLdXqVf@-Emr6}4H_!qPS4syb&%IK!G4@QE+(6C$lpCl? zY&4bdxN#gl6L$PJgc z&xWP};Ei@Mn+AYyXc_>4p=kg_hNc0KH#7}^f}v>ulnhM+pxV$h0Lq4@0Z?aX8UPK3 zrUB4sXc_>`hNc0~YG@h&?S`fSP%$(OfG$JR02pRy8UP~=;Td2AeN&!T~{+>PfjFGFhmk1;_8OJoI{*wh+j?- zCm9BEC9%&iliSSybb=NZTLvTx8fF4-+>q93uZB zE;ekG=ZPB`Hpy$mO$?jmUE*ejEwYlhg<-3FP29?`O@1bBW7sYcJ`RW58Ft7I#2pMP zlEX*3a3@2Z4P!@#VKZjHeV7g1qup#cq!TIyql=s+oDIuHC!gXYp`6_g(!y&Sq_(#J=`91M;!zMX}c&1^qoJBm#uthE;o@3Z5R}#-P zY?JGW=Nq=mZNv)=J0KJcyx6cJdE%vpIvaKy4LM`XhDTAdhs}m5SP3p4UF0m`Z20Tw z~LOHv@-V^}41#QO}Z<$JC=4;a=+7fT;9 zEX!!(BZjpyp7^L?oy_30d(5z2at**I3>&1EJBKF?he#bupEhh1B#?*nlwp%}vh+E_ zW*J3%!LUW%XS**Mw#r17{>QLQ)*`-Y*e)}PuN!vAfw;cI{~A_gIq@w+oefuw4u|4m z%RPM{q&e`8?*d~Xvv|`vUD{0$h z*de#$`VNN~R^&e72t%C>D@G^17~b3}UHJOVO_SU`IecwDriQbGpN6`}RPj{HyL?pL zJEm)?n+<V~nj1;B|8krNM}q{fU%c-C`IVIx0wOgo+C zrsBY)F*OW`pZeY(9o~hvO`MBO48e;U!WE;Eck#BsjjdPUh9)TRMwTyd0V@^gwCr`> z$mphw$ z6r^rB&?wB$n2V2d2N_2B8K`=&QHV zN$a|+J{XAUC})kB`ez`hqYZtH;uv%7qBzzl%=hD~gz)!&b1pZG@=KUS=L$pZ=Q-WUS7@Tl-EqPo%0MRk*ri|S@0i|Q6bi|STGjp~~2MA8cc4V?g& zT_%)|o`>zThLPmy>N!L0_&>UnqYy&f;>B?DPwV-j*YVADcMaobn6GwMeSj>q zyzdP)$`8Afdl_Y8y?7s6lxyJ>|Il5-=s9a1?haqZ+a{jpCXQkggJ%4>p5#ls#aLii z!=6?K>@M72y2IuXI44>nJt_^AyRc5YsHaG0w65w&mZ6S(hd~KzdR(3bPu3^a8v1fr z30QBKla=rhHW>!;6S2imJCyWq#0`LBpM#vm?wH zf){LQq@lN!C)t2ezQFNV#~J7JgiPrP_oeYh2x+Pr?}!$s^%Uup#&dd- z^JqMa#_L+ko?OH*=Q#{>Jh?M^!h7lKAL#8Y^HmMM3wnxdgT9vZB;V54Q|!gY1HQK9 z=xt&s@*#0E!;r4m?+M#R!u7x4dP8&Fi7>b5DY8kr-o7VUjw!^*oEMvPc!-PrIYm zu{}kG%YD=-JyoZoicFyKAA35v<-tQo?1fJ3Np7MsOHS%>d!Z7p`O|u8=#<9i^i;h{ z<6k%+=Q?A2fv>Cl`3@zauQPiRZ!~0&ps&9>e8O%LcA?78n2*!*oEVJ!aH!JiKErTUN_MZ4Ib^O zdKPcxMUKK_J)OVCVK;;i^(5b*B*&6RdfHf!I~T1z-cv(gH2!x_)ox>8ycsW>=bSMf z%P;7!zygy{qLyMEG@2J)>n*KlRkE&8WU$RKGamyq?zYdaAai@pmx( z!HjoCt)RD_PC3wT^&|)2ZGrvr3hIZ0@c?cFIMT#3*u*o@L`Q6`syDd?Z{=HFgEhTr zjvmawq&NH*N^&eI_PU$LLac`6-XeX`xT!Z8F&4%RG;VRmn9bKCzOc4i$%3!!zM>SZ|R5v72LhlRHo)KO5WbvAufLqTTOt zt%co&B3Cnv9zWV^kFcx1xT)f@(abn9)&FfVU$mQOM)aR^uG4PQf(b+ftA9o5^s z6p`dM#e|yDTV%Kl>sP%=ZXEXjctYB%7ea`=q!-RM&`)1$_J*TSsctqW*4n))44*p# zj^_0i*#aGH*qdyFI&PLPan|VIN_JrrbLPvp_%su4G1&LQ-tb8Jp3m*y`sRDZj-Izo zZ;_4C_s+e^dGvh-ySUVKF@YmL+`c!wkJd97*^bsl5973ZZ;@_!%J=R~CUwL5MUL0L zy}HdoWb-(h``cNB)-`<}Xy{8TOAj#&()fbjWO5IT1CHLsy-xN@q?7xpOALLt+qyK3ns%A@wOjh!uxZY6YpKSRChrTbHv*o{8DFmf>W^Qzd9Ij~j zs$Q(u+VW~%c#X9@q8GnA?JY7Sw*2?rqzXsyBo)?onYAa&cwX6X_2?oF#&C3tu!0*y|^I!^h}*eO~NOo9}ymg`a!%7TG9$ z|F<_8KOVl1;F!HN;QLGB+XKG4I0)|;ViDr-ziXJ2$t-=(Fpyu^$@dL)_+RY}m!Ofl zbs5O(7RYfp@hf_ZjF5qR)|=eUK-T5C{9@pee44($G!z*{{L0Xm^@v{^=HyJ`H->?{ z#_RW6Lk;BP-tbihvUmvs`J~rC&-=c&$OsvTj8FPkLm)F4NN#-kA!a^DBrp_d z93 zM%N8y?8(<0`yqxRKM@-ZeVNb7O@=vHOl&rUBmu{##SltsENwN6hWQ5 z0;0SE70ct@&2xK1+&;d@=o#h6@lHzXdiHp<86#06ag3qJ-NaQ5eR+sD)-WfJ6UP|_ z@^50dVJI&XdkiD_FR|B9qZ~F~HM??)F%%;#%FD5?jUQiR^o(-K_~bFX6)IMRQ_WbH zyNTn&Pf${~gj2K6tdD#fzwsYmRFy7R&lsPKf}!lg;hW{G@#JSRBbj5)a?;JxxejxB z{rzfuI1hGpOZW_Ly7_KFWb2JDvQaOZ81B}cTsje(oKhFKz=vj1;6oq3z(+W_0zb+J z1%4(E3;b*y75G6nF7Sh7zQ9j}Nr9i`3I%@bDi-*mr&Qplm#PA{#?=Mxq{;1ZhM9^Y8t4Z69&TWM>7x5V}W??4^yZ!=Ent^YN`suXyy=qhm0A6nq@JgmT_ za(ID@+K2)dr&S7EMn)ER4Ua1D0vcWWH_orp_U1=& zb}e3UU5>g7OgPt5`xYnV1b3{rz>_$>z>~3B?E}1Z&37deYFBc5w!qQqUgv&ndg1sS z$G^p84VoC#--eOKFO5cG>22Wq=kdS&#mYEK`SUOib>H=G4D_7lvCm+nHM>x>Ui~DT zhjX7rPl8|JIiv&+J<TOu%c-D_?=-KH4Go0gRh-PYhTsok6QR|3$0M)avx7V1?5G zv*_2kP82tnvsU&xi1pt^9WQtW56L9Rp+!Hq74Ff>5%3%xmRm%t8&F`e9dQY*c2cXY zpM;fH{tU*^aXIF{YknTaR`U=4X3f9CjTfBs96djRS9tytJ^v|p9qYe?&RhL+eq#Lv z@aY9HYQpm}4$Wn`*HO^E0x^`MD=Dd+bjjmA$lHmv}`inw7xdhMW zqQ5GXyz&mDYjX)4ObVhqlRNQd!~%@X{lhpCe%**W(ZoX|*gooX z^y~5A?2+F%Vknw_+8MQu*yT3Qd$xmP@3)WO@5Eo|;OX-#-sB*<1M29QSR10pFBU0! z({mL9e7Q~|Z$Als%F%7ZC*z7@G+uHG&R+Ct+h`mKk}3xLTH75Haq(%+hv=;)ZlO!b z$@tnNdS9X1tDb<`^>k9=%armkp6?HGY`OgdG?9-!-Wdf6a|=YDHSs;N8gQV#sG~*T zRj-bJ$_H~)zs&s#?@PPmrFrfP11IO3b8sNoT_@LGm_s-@SJT}OxkFLV{virRL_e=K z1%GJ8+&@twb(;aa+J{-ILF)Df1+`1=0U<%p8K8XaL8Kn3y9!jQ&Akko>Zn}1JsOE- zN!|S@Yp8vZQ)Ycv)~uO=qRpl59h9|es-S3lSJvgV^7nSLP*AlVUzXs-t9}zhSmMFz z0}yR#5#KRZt<1<=WgVI7tKS&DX+@}xB|lKfqAv{c&J50};^ z+Ev=wm!S3~p7PzKofY$5^*8jlD*f#)xgPWpBdhRNX=UjpV!J3=`!D+ZWvA)#fzJ+dkIG3)epA9MTSM7;RP5i&fP>K)@h%PEPt{z^68w3);1 zCCtncZ`Q1iymB9XZ=U;rCf8z7mUyc^nsC;|+Z6bo%dTdxDv|2>QjV}Ginqa)^o%$xscIIKg!SuaLJBKDn{>fe~ZReGmPgcRD5%1d0-j#ZpODo<@ZK{$w zE?~R2^M@Fw7F<>UvB<}!uaq?g`)Gn4@|B=v;76`C~*NxWaxc$Boe zQP^KE(JsAS>^=p-EIeu0fFZ~r~+ zfL-yC_v4Tou#@Xn;JueTaudqWt7}?|J!ihI_%90iWF>Bi@ojZuQBq2F;V3>-w=STZ zO#Toy&)4k%Xh@i%D}Jl)ctCUV?t_4pYSZqnvFFiB)qnW%4%@4qjn@(nR!`@=H@C$4fG-<=MFsm<##wRSa2@cQBdqt10-&3AlLj6BKgEMugQBg5(L>OjHQH@^vhll)I44bYiMc z%TL*79W=v)7Wt_a4w|RaG{0tr(=^a&nqRBJX`0s)oL^f@O35YkwN8chWu3G6X*Ha) z4LWD@(-ns3oXz(uG$!ZLW>yWyyE)ky_lx}O8n)A(?1L*gKS!Y}d59%*6-Fe7u?OpE z4@M{NVO7b`Qy7zMz-sdqR!x@C!2*S`$-OLDs4z}vVt)PlevDgpaw1DMQ0VDpcBuS@ z3cbl`820>Ph4IOTI4Suh3acf1ai}*^n2;RAGqSP5>UweIH`9x2qGt8UZ$6CI%oM%S z@>}V}wU$@SEpqu#`rJAf<7?UWRpBzqZ+AWie>NN5p~CZxS{LBD%I}yv3MJ!i!!9tt zN9Uh8T>6tq-OLqsdKQJj99(%`um(Of;LiCQKw;P1Eht!X8*D=hmugzIU)H)BM+(<8 zS9ZnOF3b(9%D=)co9jMc{t$pyeITloc)W5yA}ovvt0oOp8WYaZN|j@2|6NeE)j-jA zfffxp1nD3OKLk41US)08J29v_dZ6Bk!A!bv^^m%j)7PtPhprXw%~f4DQ19McKkJPe zqNxmD%C&QOM$K`oc|@-2p93|Ia5cTr{TRjFa-X1J74EI}%yn`C4$^o*<`TdzDo%+ zm~*VKt>49^cnEWj6?XJ>dU<0SI4E6y9k(V;(-8|ZPvO8cu875VZvzbVr*W|>&cQ-l z80Jso!d1k+$tw)^r*Q_kaazT9<23X?IQj1j9j-s%@O|l{LsxT!Xw6YW-aQr`@uc!_ zc*G~FDOk^+RKsHj44;VOSr6`qtWx#&4BPdhK((1&1lp_;uoV0NL*QZr3Kd6CTG za$4lAyKu40;<8#~>a4;gGK4uUtd5tr6Z>TkmVe>)8xkX_Q2*M`H{TJz$8nzLQaBKO~g zIntM%i@DOLVQ?ubtSf!I5oyZ{)0TgSvpZb z;BTDyTl-HOv?q$}R{soq`qiO%Lj4WXN&LjNoWmpa!g*59@<^S}FY9!+Gma+-?u@T9 z&1FO3_H}Fcvur3UIcmc-8_J34(fg*1oixm}NH?9#Rl@n( z-u!94lU36iv-?=X8{WlyC-c*zeQRnf8h_s$^*n|dN{Yx(!uq?T;t*yiDI!A&f6D9q ziWy2u$WT&w>R7C?uS?s>s8f8+!2})6F<+7HlTOmLbis5br3dVHztfn>q=ZZ+EOtf6 zWTKYdKhD521MGtPF^~H+lgT&jE|bY;o8cbgGMTiyOeXCvlS#YFWKvgEz#gKfd3`vo z;euSAjhA+p#H7xWnEaZBo3L;P7P|Z;bt}4HIkDwr7VgW!<$U40c9*}T-Q_Qt?DCi3 z;KL{za@SmJ;DSr>)}MC(1}oJ3C86do2{nI7sQF7m&0iAki|S#h`Afp~ZDAT}{t|qd zhshIa{*rL_MHtIa^OuC0za-TBC86do2^TIvSfS=G2{nI7sQF7m&0i8~{*qAhmxP+X zB-H#Rq2@0MHGfH{`Ab60UlKlswko0KF9|h&NvQctLd{mqadqN#ydEL@s|xg^Cg^Cmqadq zN#ydEL@s|xmqadqN#ydEL@s|xmqadqN#ydEL@s|xmqadqN#ydEL@s|xmqadqNs{I-Nz(i!Nt(YTN%NN^ zY5tN#Fbd3HlBD@dk_lK(n7<@R^Oq#cP>1Ce@T+&FGK5NQ3g1C^l5P{3QfwuD1LoB)_HFCCm)hdw_@RC9L4Jq}fZ@ zhjE&{?JI_x0GftQ9CK6*-O+=N@?~I zwUknty+lo=lx8ncTd04rQDiSsTfdZMFHu{+lx8ncTYpNLz2rH@n=6f}fi1F^ybSy_ zDD6r__LAi&MD~(e{!2d%-1gLXHSBUN$K%25U@bRZbhj!ieS+UIu~2J$m>xy;l9n`k z$*mZ`+M`i5j~$#k#;5;pQL}~z^hJwDrNwwK+Qbqb(30tC37!Y7#u6UTm+=jwFpDbM zcE;FWh}2@gQ1WNBOS9^O@Nf?qA{*4EBA@kr+3_pvPOZYXlWcfdUieYxd7 zz+W5YgvxflMVHZy3sS;vWnnnM*vyFqTEc z(+u;nG4V{pM3%e@Jln7!TN2MTEXt0=3k*xL2k~OVD%qEKnPIgYO1#prMvfw0V_23G ziPsv|%IU-#4C~}v;!TG2azF7_!v@*oCEy)~L*$<_^F^r{}xRGIA8i*SkCh{mJ_$G!0d5XBH zVNqTnZf01L*NB@NR>?cWEexyWBjT2ZHSz^~ypT?|`gbK+9NHrbB2t6{s$ zeHpl$VTbI=(%lU!vOjSTL!AwC+QW%B)&8;%Ja66hrsW>q-;6o)>-HjN31`E;?a3|m zm;k?e3~RPtmj@c=`Sornh-`ZAYzkYP?vB_3=T$nS}V7>4pR@leA^?jRm!7)#%q zz{3sm(nDNsn8@Ql0*^2($b-bA42vS40*^5)$#7~6ortFy4v{^GryDlPKEyK&o8$)ms`5{U zdXn~P4_~UsiTNCt?B4C}cD?`?)LHFCo;;qU3)+({hTtS^^cjpVGGkBX6E8LtIe>VH zp)bpbmm22eM&f0Lfm}_z+%S}PiB}j#@+$F4!&u(^0eF>RUS1kNzXBhTm!h9&ucc%xyJEW+9p-fUPcbBMPZ*2rBPtlJIC@*wdJLu4)?{@t)no*~|8 zST8RT?=ozVH;8u|4w3hW_ZT+HO5(kSO){5wzoDL_Keva6;|%zB;eq>kc9Jf|nSG$W z$dkvD^w0LB(u9*V2{+&HaWnR09PtT5kzI-ZGW2Cz;**9sxsUjiVIa2=pEeBTCE_!N zkvv8Gw_z;PxHvp(n3pNU=M58i_Iu!qh6QPJYG8?-|z1Y~uTd4YGjvf#DEYLR?|kC|eLe zG;ES7+$VqJFxM;zr`<{`ZIk_%0>3cSQ}}RuI34H5e{zNA{liY-^KkiPdy%J>r|^gN zS9Yvlzo}`f-$nQT%@g!~7;WDVSVdoJpF<+k45jQdvS&z7hp)b>kn;Pb1C*tOYfow_K!Z4J_h+7#( zawBnT!&tuJE@NB6yqw6jVtd0x&in=e|274G* z%c{g>hBfjz8`{gTEZ-4-V~D52th~2joy5d_4C|$uxUXS@3?c4kI7Hfs`x`dOaN+@m zO}um#bZ90Me~V&He8#<`OS5tdm8= ziw)~#W8x)-4YC#SQo|v#Bk?lBM%kTsxuKqwLp#D-J8*sMhTa@*XXS3(b*}6vYDN*9 zmFqf^xfMJ!n!z7R-C)LeSi|-GM#H?U!Ik7D!$gk!9C))szaSHMZ@k4yu@&Yzdz)cR z^#c6l>UKwX5}a^S{@t)iwqo5o9r|sYN!N6QyCWd~CY+zYTFmp&-rXHV_JuR);f~~E z#=H?c|HIlL;b+2+8j4JN1)d)>&t*CCRp8@RS|^tgpD?VKS9rRgvdVab!VCCmD{Ynk z5}z^DAn)r4%bf`F0L+UAEXdpO{<)4KgJ+PhbR=WCFx?k&uDs@q@fG=YShm8~%~vQ_ zaXa&tVI<$Y27KEvu3j{K7Pd2nxFvI$dDo$z$m#r;_@0#()x4|K#TGGsC9pMg0ilbHipig13e*9QrM?_8Y)2t+Y*U z<;Z?#*dgn(-S4e(g(vvMj&ME(#@`zuyli9lJA5wup`*w#<=FX^WaFV2yEE9~u+qL9 zhp{C&hZq|sase?hEXbwAqG3_4B32oeVv}K=RC7kR7}i(M*$_`(+a3DN@+r?~#Y)>H;8f}~?2vk5mtjTj=4Ce2 zQ1^{LcZ3IFB>W;OdX;8|>#zO>{&uBO^AhJ zOzbht$q-_%VIZx<@rI%NftS*1hLM~`oM0Hsu3Si0uc$0`E-zxQQX|D;%B89QtLsfVjC~UG@6-b<-9` z4RQtN*_LM7DD${RZDXa)atrUlJ6LI}Y{1f;th8P3Wa+L}s+Zk*mGA-d&2Po^Ip4aU z#~ow$N|D3D?(b7cb{v7Bj=A{nXU3kK_5*N#L;RMPr3V-yBQ)_q!TLf8@NlbKl1GTk4Xe3yEUSdaB0zsOX5e1dhaa%c9Z@N= zZ|uWyxEk1pk9obH;EcQQ4OtK#jq^`qmKUxcy=XRNM|hh zvqf_BJDzu8rAQZyB^lDtXdb$C79J=plRN*IoWF-z_+ zO5;Z=NhhkvEic0O(ZR;|SHgZ8v*bZDeim!vKPyE#rSUVBWJ?-vfVD1scChgimGHMT zX33LgJRWoB`AU&aY5Zy>Ih)3_8TRXgjbEySchZ<8|1sm4_~`parAVhVe!r4DPvd(S z_KLyAZ&kwYXv~s#%(xnt+J}`QoznP=N>V=x##=D#uLc{htb~0i@mcbz8FwLyZz@GP zrSZ>|2Sy_Y5{3-HDW*FlNcBX1pgZir&s5ozi%6XL2pxRxe(JpPH}HsW%c| z`#hl&2_a#8+_#=Lu~TLL{4cTIuGv|nQyS0cOg_Y0spBncmTOtmc%4pU7ld&cCDW|s zZLpHe=`7MIjTdz$8=;C+ar?7@GsX{H=b*W8vH8N+4=ml-O3U&yM|V>z)h80`b%qDB zrT_jHi?+4&5Khe&okd2#mUie&K4ME(bCup{pry~bquIqF(pjAR5pdT|y-5cp*&k;p z+-;!YR!-etTjd5hjn~jJ!)95P1F)yrwsR@nx-+a<6=8K@?cLVG+8+1ry*i5wmth^) znfwt|Bw~*bcD{0+{E<-}W*A6`rOOTTQb#<}5Z|}qY=*}emZh1c#~C)r7~+YB%`%*L zlA%VqPiJ^Dqx=Aax1U9MGA@u)I*W{+QJ&SAyv8WEdjrPjm@&RGC!S{*u*au$hB6ku zK8LR}%vTFO_FULmWE=E#WoNPpIief5B^V~KxFeaVHqsb6oHm!-Tp+-O*qy@7#QS?Xiwu`xJ<^%H&aiIfzT{Ce#>ejW zfsZ+i0{Mv3{y4O>HTH84T1!vj>C@AlMMl7uUhGV!qKY)V z1LK#SG1juh?*U&i%*#UJYYt0gx_-7Z+={MuKjU`ki4cza{=)n3rRT zKN%+M!`q$V&~Egh599c*^+GdKp+W6uF7> zqhyG*46Iybn3Eq_T4R`(TH2Nk6Sq1I9^l&8?sjg;5@1KlouC=Skp0kI;x{|5A=+wr%U5zkfPqrkEG!$9* zE^xG=FU_3PV+?cBNgQh!$o91DHVox%UgYB)`gv*o8aTnQAdleU3@2ITD)|?2vSGEn z&K^!REXzB@wG3;e$e~=vuuk^l?Pi)`y&OvHH*An$9NC$ML!^}#&m6;MIgE?zT*DT* z8cR;Nu0y|7t|zW%s26diE8Ggh=6{Mtx@=@u#bq|XtH=@O$S&?mj^W52g#|a<$Qk2d z!u7;W4E0)C)P)Q!@KwU~vw`_~4WqOf<{^&L*Y=o)UIevghO4-^NDv&JXbMp{vLd_kvHu?c0(~Ct%aXKf>~2{tZ+R z^KW1BG5_YF6!W|8a?CGN8)AN2*BtW;pZ1vFD0IclnL8rpBht|^AIXi2`H*XTJf;g< zl$g&$ro{Z9zgEo8sMBJ8RGS&|!_M58pIYX}{J61W%+C!=V}1bGBj!$iub5l%ePiye z4~)4rpZHpTCc}H#{-sChwG(yS39}ZoAHkxqmu0=0@nkm^+$FW9~Mt zjCphaOU#?+^)YXIH^scm+!pf=aA#iiNZ#zMA6LNNNXA^cpNhHoJ)2iilJ>6pDwMn! zbGdjU=G1;W&p(|Ex9F-r8iV(K%qjYj*HX=yby8Q3Lm#N}*m)S?|DEz!PL;>*g`K~{ zPH;E0iGR}PoAMZsd$l{^^(p+XAKz-&6qLvEtD~uJsb{hur46)Y`IkRXx-VlEgN6)Jn=H;ecfD;T88NnW|Zdj0oES+drl*j3Ll3_`f zv2vebm0Zn+rWn>h6(}4&G#rc0`72NYh88(4>_3#p@_p#? z*L1zjP)!Vp{(nQ<)==am2ECo3FDJ3#?G1A>jktqhAY+I-8AkFcZFe?|%#_Cz zGvzVGOnFQ(Qyx>yl*be^%#_CzGvzVGHra(2$C*Rh6*J{A#Y}ljF;gB>)TgXa9$OXX);Hxb7Wk$-#%aOR z59P7#dHPf3F*U~J&zW_(HJmArX(?n|Re9`ay7n>WE*k1~ptJD)nxRED$weE=W6VhM z|D!yHRT|1;Pt(^RrBELGkiO>f0(jV6;t4+gtMXX&8ZbWn5aidf zCC-$`=#+hg@>n0L3@DGW7YTkdfd{!R}5W^{Eu`tjt@X8u{ZZ^~ml?$xrP zUGcx(m}0ty^4NtqFrYj($TgJ5NKzh99#d@gR$DHw480##{^nQ;UK`r{4Bu~v_s|`C z0q@;kwezSpw2fE8+O=%?z3kw)<W-a)N)u5D(`%ZPQr$6D>X%ZgJ9a#pn<+)EI~Pik^Y2nArMhGD;NeOsa_ZbGrT?ir zR!Vip=o!ctBsY_~^8_(JSxA5*}zt#m9K= zwAx?NYOz;7m(_RxlL@k97p;wxmdcVXM@YC8ZBc_rAxoy1$&x8%vSf;xESX|3AWNp0 z$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={ikU2#VkS$bn8}hUX0l|8 znJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={in=mGmh3^C zYTsnZSm2v1*)5n1oDGmAV-}17Su!>D24u+;Gg&glOqNVBlOe#Y~n=F_R@z%w)+FGg&glOqNVBlOe#Y~n=QD*~W$)3Tf_V2@$4p}l5 z_$EunS;E->S+cvPV>YC+WNPdU$dV~$vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+ zDQ2={ikU2#VkS$bn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|_=ukR?;h zWXTjWSu({;mQ1k)$#k(KLzYZ2lOvX^FIHl(s-YU~Zjk|}1gWQv(AnPMhOrkKf+DQ2={ikU2#VkS$b zn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESX{^OQx8~k|}1gWQv(AnPMhOrkKf+DQ2={ zikU2#VkS$bn8}hUX0l|8nJk%NCQGK6$&x8%vSf;xESaLt2FQ~Ah*Rya(xtLwEbvX1 zjI)Fvl^{#D;cU!?RF({%n7E7lOAc!TWXTjWSu({;mP|2|B_r~urYcLeAH4ccVY>`j zG8XtIOU8iskr1+E$D>Lk=VBv6@B)=3yAf|=Zfw1n8=4^IjVvE?0V~CHTJ~B}Su#36 zA6}c3e1Lb=i>NO4-%0MFT(wNavG7epeZcYZq_8vxp=^rJ8?Q`q54d*6`?n?)??q)^ z9Uo0fzL|?5&|US)N$FatyXsF2ZCCxNq3xyhoMeM8$-2Zpw*jtp&Aoj0^yb-~bf z)g?pQRaYC@uDWb!yXrba+f_Fh+OE3M(00|$hPJD2HMCuIyP@r>D~7hK?lQDp^)N%d zI^LfYwyulWz+LroRNX%V@^X_5%hl@=CmS|b&nB*6sNX4#>I<1m$G>Kb=Z)!eVVw+@YxWfxE}xb3 z_a%?vZS_Vpp4F!hxRGre4@cJN3s=(kgUR?r-PgoP?Vo`M@N@c#bV}nzeVPbFc3_wr zm@zI%3Fq~N%w6JNf~#+V8UMVN=Pm9l(kU;sE&7rjP({Y#8GpD{pS!X>88#KTjYA1! zJe~}M+c}JMLD-}(Jch21#&d?v`rMVb>R8X)rLV{)8P~GD6OFp8pwtR>)#-&myO5@x5k`7dn5I(~@ z1{>eh7fz$`)A*oyiy6OwT6gvp>6FF~^d+0)tz3!Rr$$e(L;S|q% zq_0S)oKgSkOa4UTU)F)~Q*O=_aoYXxpMBvSG(HT*kK3GiZ>;D2yRS&6Z29HBL>9pK zbxycf`ces#eh$GKhB>)v8t_fSP%hxaf6GuO#q)jP2)OZQ!0yF96-4m=i;Li$z9J)F zOCR?oTe79;m@DBYu8&v=?i>gF%rKA-VHAFDBcR_Yeb5*Fmag~4@O@|_a4b&m7kx!G zN!Q=^C0EjQCnxKV&N#pyU*J*+e;(}X>%Q^V7$Y0whB3w%Fx`z3AjX(L=)qtJAp`?~gaDxzLkQIn0)!SqOCUgK0YXTqq5j_Y z%*@?g+4;WjdH(->95EY6r&|lGcghqdr{wO@|aoy*ks$-;?!T2w`t@zFs5K-UlT96Lje?dcB1Xj!lPT zO5*Nxa@?LEF2nJfm$k&IlZs5%U`(lhaU7?Z*0>rAeqNse#e5Uf-dwPWEr-WsjHFcv zubt8%HK3#!>Eub2v>ZnAW@=)1%sM1guRovHw6u36d7S_$yBS_TYR4sjbVwQGwIH3m zhrIqyz4kH0k{kCEuM9sLMJ*yjl|nBKe54w}8YCW2!mI5Wfkmyx`k0kyz`h1Qd z{uI7@K{_N;5?`7w{s)PVVtihf9*VBxyq3OuaXMKx3&i)JpOdtgXHYC13U3?dbr?W2)=Bsm0I?1mti~Sh`ey>qy z3Ibw{CK+fGZNoT$$!Wv{#`m*HygwcjdGmd8)6TJcq&~=rtHhzX|EF~)f8V% zHsttHx_BBY)$3!x@z41j|CCN1MvjLev6Tg;D zUPI!4!dKof#E+rJ@1{%1lEzhGK>Uj2T1%{sf*Cv~qq8R-$RrZ*&?byX%A&H?KW5p>mt z^~>;!#!M+i(!^fIYXV9&Rj;NH%4^Fc=c7`!!nM41O^8f(BwcD`WThVXk+*%mm0B|1 z36%FF2D>$*=a_$C{_Mzv6hhV$GR3!&^@m(QrlYQ0O-Wr*S6-v%cjtFyOeXm}Sua7$ zIMbCE5r{pRQi>$&zD#k+-eA3$)7Q?L7pB#Z$!luFx{Bbg29yDqoJo!WUF;M%RIg#Z z7=t)1Q%aGv(x{9#6)4qIy_!NOZ+515E#)0XZ<(Vx!b+#X`@Ff4ydU%eoR{B~nVIAj zly@4&tKZ1G0_K>XDWwpy-Y--95?LS0No)Uz^+@{C0TJs2Cx>PEtoO+zzb5NH!0Y!l ztb1XO12d%*$*#=Ec;$1^3#wjCA(VGSCOI9IYC3g4N)w_hKG!}gH3;7w$N6_v{(v8n z@eT)FY#PGiFf-u40*}?1kV3elIx&;HimYSI9&0mpe_cfIBm*i{O>mt7)Sx#{VZa=FTu+U7*oIFcx*CYTAH-!Upj~y7* z#Butq0pn^JGtj*Tbk#_<-e*8hjVE}&0ev-@-~$FssA&WrG+>}+6MV>kNma${zQusJ z*+E-AY`{>xGXdZu1}swlCipu87OQUvK59UGJf4RCy#Y(r5^{drfaR(h=Jozyz-rY@ z@F@evfU@!bYsPzryomU^8Q~^mqQ7TC${??g zGD)=%yzW9a@cyldW8xkkWV}|i#LCd}p&@=9+JBM>$&|!jWs-Z4cqW7X8%wPCqcGlg z8NKlmMLy4XE6A%4o%)aAH3TMCT_I(VSF$U4CV9;#ao8o(tSgFmUEZ%r+=2y7qD#*h z&w){KS4gHL9@LfO_ui^B=ja+utmpgkF7G`OpVj3!m4^6o5Z8BwWJ=p~8qkaOu8=ag!x__+e1W{K>jv?-E`92VlT(5d z4XD(gIV)xi7*kKs+jWU1`O3cO!rd_SfqBR4@@&) zvD%-lyBSbUJ9p^vzGNR>ghr#f^j4}0fwOy8$iC4YbGnjMi_nMlH0E4u56%nyU0xb3 zu^(e3W*Y<4z_1ItLNX=s{$0r>Bz~F12UuctAi)C-D5+~vmv;(zO-JV!8(zObay+Oj zqzv*psw;Utd3`|Qm6{kIx>?OEu*&elJfOV8y1b{z>oBw&VR$vc#%sDl${?>3x{_a@ zShDjj_+0$=tzIR2>^T#g5Hra5R#xR5+vN@37rct0*Y^ys;ppQjT_I(V*O^_(oq?kD zI=fJ>bMo~%t;;)@ysp4>ce>#<1FM)Hb%m5cUKe#G&qGn`b#b9ym*(qrewTMEd39s_ zHyU26ki;(Q3Mqrx`j=hFlNUp;?I*!Nzv{Bn=sbGNbq0*7o!NT50pn^9g1Qo$odShH3@D+YMNxP9}J#0n5~x z1UDP7oX-NT?DDQ!j1K=1qkmOb?K<=^HW9h#?yiuAV22;pSwyagS_78D!wA(^=2Wjw=6H+ zr?(9#i=S7!l3U375=oWtI(fZtg<>~?s-WLYMcVQCzj{z&yh$#TSG$6k3j^I}Y9HhDk zer>>N)kp9f1Im|Pe9+}x4}D|Hu_*u049DW}IN<6E**SJ8=uQq@iY{&D4k6WT9e+~> zV37fpngZwXN(>lN&k(uHfN}LA!3qPqYATVd4Ctwk*;;KtUwuii)_@76xVo=5V4$Wl zh8hf*RPXlyY&2j>eN3>)fT8+|V2c5ZRGjYEYQSO@5^OVIiK-;nZopDCnBYhQmZ@O` zI}BK^_-j*MrvWR}L7dM<8?aIh<^Yd1V3it1aDoAA)p&v#1J_u&Fyx1PX;!G^QDLn_3ax}ZDxF$MDz4BkH7vXsEQ@hYd; zeKm-k%9osG7aLHfq`kYn>I1-ops4q`ZdHcPv7>qz)TbIysY4kbrx_57RSN#00psdo3O?O{_;p=+;u!|?R2f;F zX+U2k81iQsP_$gz?eP+S>``dB&S?1n%yM>jNbRZR1>MO{spV~4^j~O*9rZKX<01np zHJ@7k*nkLmt{g5lU|c!KBHm97DC^W8b$hi3Lhuz3w!sK4hwuNiJETGsd}ViXKcJ}l zm;$ac#E$BwS6^*FrM|~5{=$GURYgzyr2*qyW?a_ot*4}4LDJ<$(#|_M&ab*dYCuUh zbtk=pAn7-Bms=u9Df-8)k)$NMcv~c?l^sTHXv^3 zaMbQHpbW(I-CjFXh&_h^yuoOBEBbPGcS!B2!{`D9OH)!v7`EEfGq}8YAFRj zY`~ZrN5PL6Fs?4A;NKb0RezZZ@KFPLs+O#NZ$MvNL`y$rK+*EI-QJVbat%E8KBMK+ z*vLNK9a4L0`D}Nx^82`zDO6^ZuK5xL7dWr7xf&t^or@OppKyjBR zyFGsPBK8jY{yy35}TF>VsD6K@(&sYz7pEd$0>1Ks6q z1B$!6((T<$N&keTzZyyRLA`goLux=t|LjhVUk*vb*r$I*lHTDN!oMR)3+O!`N0N@? zsC{B3sizTe-lqn1)ikpD%z&Ocm>J=71N!PNj>{JYl!17^+nWa!VsF5X|1esP!rJ#g z-66H7mQGLdhrpIUWooK4#5g8w2Uul5rAlN`U_fz*;vR24 z=whFMb!m^DK^DWgYkNY9Bq-2(Xf(VgA)JTz zgp@&E9X-i=$?IB;u9{pa;KH8bs>7{-A4dXq?}fadXfW=PdIMYrh_ScPs|$>Pb79+`_LPz`PfSWV@s$&~_b?n!=y zV##bA9C){CLTtSj(Ti_0pi*CL5Ab#a#?)B4$DKxs3tCKjrqM5%jU#}&3?z2^b&uD0 z1XMc!&T*p|->+fQyL&?FLoFUa6az(T@sJ@lT5K_((c)nP8ZCaO!I;+KQPZfk_`QKd zi{B#tsl`u_K<_hJOof3S>j|kHwfH0AA4PS-4(Q&W46&H*NyI;iFM=yQZHONR@e7E5 zL;NZXN#Y(RkJoz4H3{1NW%U0@5Wj=i|4Wa)`EWjn-#`o-;=lJKGeA){GqT>#m;6?b zw-1R=M|8hqB##ExKcF`1srKhR#rKhTJ&FHgoWfDZaTV~T0hKBT1Mh1Cy2@qiHwN@d zrtXDvoNo>2m-OSS1HUtnSnuPWnISnXksPA4O#EEByNH_jfOY_ zMy=V9OiA3CO};?lbLsb^^NB}hy)Q{T9mE}mxC>cnY&IlQ5_e^jRVzTeumi+B`D#zd zdTF%8HX@;?4e=060h6*JnUZ*FHaUyLhwlL5Y59`-vfdgJkAr=8HpCs6&vwg(WJ==M z+2pw-u4C4mqlp9Q^USPwGl{2QGVC|Rw_~xgARCe?iI--RFO!&`aQ6;0lJSibTmc_! zdLb!yan}2WynY0CSYmkf!34{*A!U%)QQ72#mEbjwOYfDo7i#1vfU69s)Y)uZlg&FJ zJ}m3a2VJZk!*PURJ(QU}8&V`$e?ObV56U{~3%c1!mNk9ods**75YA=^7?T$`4xHH zNFVu$mV5FdasywDJrjYOKyhGa_OpJ$V6fTG4y@-M7pbp_XtzcgS>Wsx+z zYYZ4y!?{}cl>uE<&hWq1fHJ>q%6dPh;61?R3M2Sr4CnRPkP1=ot=Z&1DEJi;-)@K< zm7+E8G+<1Ph6%mR28=6yO3=H@fUfFi9N%p~5qx9TD_af0f5KkxW+Qla^!T1^NQEf) zp=|OXpr~=OlQG1OdV{s=w{ zrEEx%Wc^w;IeiUS9}Um&-iTOFpt=4QvHlxd-?Xe%C$rgG2E^yX*!s2sU9|_z^Ns=0Rq}{4JfAmI_vETI{f4pb`*y7J5b)A6jCHv7f(vwM%ItBi=`3k zpR$W(5$mhi#d6D9ZI5i{RTwa?Cb5f^26WW|cCpHU(#7N??*-~{!UV?&C+TVBAz)Qc z3aKCU7&0mOFY0j>L$k@UX4KbB@~Vyj@sHqVgAMVuh=-O*A(@i6V^XpcC~Czx5O-?g zz;VVP;Z5o%EgMEos@b3A6QJ$bN#Q{#>mS}?t^5|*cla$bqL)+Nv3a!}PQrVB!rxBB z-G2GTkryXaZcc$b!JGU=`nyKnnjoJSF45mF^7e$vTY*uQ;QjoD1n*@xC3p?GHQ<$LQ6a1OOwtzp$=IyQPMkIJ?xjn)A#Um5ED7<~ZA7%5_O_c8}=}7Rx@94xq zcpsDC72L4_f0oU=dSWF2XI!v*2qbE&Rm-o{(XUbjJYl?y6v3cJ<4eb zUU}RtkWVy^PfJgCPw*z=j6gotyh~a%-6N2XGf&l=W+r$8u|JT{H1DOUW+ix&aCU-M z0{6lVQS|H3bma{xe9cABN9ZukX-Q&YzvJwmSdI6k0e^wcJ6*RN5X>ju8R^OjP%TUF zmfqnB-itdT!CP)eCU~#xs06Qbtw`{4*2-X511LVzTCGa(&efU(?;;(Y;LW0A61;J9 zY=W0nj!W?B$@hXzQXHKTiyR+x5jrMQ`71~~F~J)orw2Q;?gtsM(%HeDgih7?=OuU% z&vDO6%-r(4n;0=ijgN4MtMPpx-;KhfFgJNR8qU$bA@Ui=42|h62l;D%^ z%Y$0B$Ge2v6$w7UzA_lby3($SXQ9{66MQgzb@1>=)HQTfu0-805`5l#ZEz#;Ms~>< zT^HO+-J3FHUrvH$y%+ygy#_H7oDw z67y||hkUyBXguU|rYGXz8A~8BUX;Lw#8cgsmymrtd+)$3t-H?ajF*oFCbKDJioa?$F4_7@mQCs4MJRT`^LmqULxgn1o%H1Ld z%L{LgMy+r|o+nhgMImbs>=BKt+>m?!YUqf6HEzhQYOPyTO`PjAWt|&xBU%qxM<8Rm zMa^t{LN_)*G-`(c2mcz~kh`U!Zcztu{@GJ`a}N@g8**FG>xSGV?C2Jy*;tN>rn*H72)1V{E546>;D%iFuX97L-%oanZtO(k6pg#y zExMavZ?^J64ABqVkn8mG+@kg5Fe595+W;G*_I$VK9Mi@|-?|~^=X>3dbLo9<$f@jpXvf7*>m)JJ15kwE z@JTvqpaH?QNtMeGSX*FoOgN6GzeeF>_`ZBi!yQf;r=3z($QLXW!=BPo?38`O7FN{F zrjw1I6z8PX5V(^S61$5ZH*Z5>P!*=sgz5)(|F0{6jYm9`)Q@V{>qj~8dhlN4y*CEl z=p6|Y)OyRuf|FD6&p4=9pyjVw8Oh#9QQ)U75E+;pM{1&_xw3h z^UynqIqzGlIStZqoc?ci?o=oq_l|v;hFy+&++%|Qe5Yd0myq_o_zC3mZDl0!#MjBE zvX&BKLq+1{_&xjNy7)uHtbq-UZl~;c5^(PQm=d4CJ1!^VJ?4Fm_qf;i86|!n@1FN3 zO7wPo6Qtg-k2tuO!jMVtD0DdGRNRBAMT?z$*DuW6p}Bp=|Qf_#U8XE(2PS+;ki1FGA8wUQtOBr*ii@09;u~d%8}= zCG{ZrdHfube1masO8#Qcb--HpS72RJL0dXn%CBp+$f4+X@`hUWIjGzM_ekC-Ek%_Z z(7WUGtvHrSQc zDpM7g0%{0Gya2>{RdFAnrl6To)2b@o0Mr_!5m3o7s=`~36$j)fg2 zkzpU-X5h`Kna(boN&TOdFt*6-5 z+oRUIQF3bNU}dbVxx%8n7@@o(DDDD0M&v1}bmX((U2A4*QmJ3y%$Tmw60 zRs48Vm8F0?=<5I2a7m4tj|%UmzXIEP5bw%6@mq$=34dXre2!oZyv*k;pNXgroQl~P zgH$HoKt505iwtzwrFu>zpJf>OUT4sgh-g#4<0Y*B3AkZR0I^6F$A5$P+9ghcGPVxd z7jhHsRX|BiUyW4hwPVn62brmU)-Fj&b(>37lT#JHuD?r;a|-E3SREG{+Z~36ZpS}2RLQ^8}L=9$!{V`um1$X-C39Xm~Buj>9W;{ zImtm%aGhkE6apuimO`16oF;`PWJf9VI>|$&unv)M2V|u#j9-U7HGd9OW2uXOf$mfm zvHp@lEIXAo-vRjPAa-0i4JtOg2$W}_GpS4CCjn!Uo4P7_$Pcjc`0YE6^Gk*~eopMq z5b`UQl|Q5miRoG?C&nJN|AEeREC)jdA#+~OVk|l2P+0T^K`9=x2Pv<^1eUk3 z?3E399_G4DaH@w~{DtG(F6ElBM=d?jxr61}A=kt9cd{6(8*&D0c9)Qo@L{vGVSmX}D| z3@40vyQ1uRQ@{tl8-hjZPw_WNI}3aa?TfpScKs)$eF+?Jrw`?rcP-vA1K)?9r(TUW z0cp^K@Lfao`Z`j*kEp=v2+Z&q5H!ZTv!FS0`JMQedM7@YRG&i$L-pPrqeGO8 z&|B1MIUHMgU%=s%w+8*fPldPB`vMjJ0A$;LjJkdxhUx$kJ%$YGcyHky=O`GVm^T>j zac?5tU2hiNJ@0V5``!=no^a}>&}#>&_%Kj!zy3qb3}2H%X4lE8<_owgp2fn`FzF(T zcuw6e|f5lBtcpjn;pL$p3AD~c1*Z{^*CJQMTgBE!VJ)6rMgD@MNe@cSZI zXL&nT!#3Vu;BkR>GS&l0??=o__`yTvgx-O`FY=zmf~6Qg-lCimF9!Tl?^tjs!#Bq( zr`+2OqAR>(A+ge%gZe6O5b6hcUjVb(>qC8w*9She-bcW!!|&=Ur`{WZ@?ftRoEyCB zq1zDr%&~GBz1N}hP;UcTo1D7az#_G?ieJqx{tLM5;;!l{cJXL{IQ4@-Fuei#r*>EI z)6ufSRbM+!(@fQQI$V|0W~yJ+tpTAE+;|S4S*niHkQ@B`SwOQ@ogfBF;Yq2zG-grI z152mos5&kV%L2~rskur|?!lsG0L@cF7Oq2R2V4}U=Bpu`>l>UJeoJoM*BqJ!Dtv_R1{qHGN1!BR2EzhS4kbDp{igqBk5q(OwXhpJ}A*x=wzB$Cu&8ftLrRxykZSMgpLxQyM}p&eOr z^iituOz1O;imz1Fzh=$~7E_&78j1z)A(y9Ct7^_oZtyTtacYf*f}oOZM{B4kNRrDj z8Y&Amfq&{)4OIn)GW1SR735MIw7muBBn>qLO{80|>X`tWf;}nyR1Gx;&wLB$he{T2 zEkT-QJ6%J=f`0NmL&;jMHTWgl&eYKG;5kY^OSQ6l?ZH?Y<80N+G~D6TG@}1?f2Z-z zLHq)katNLFLRDXbiD}S&2qv9S!d>jKpc|z584JFf-P%HLOPy0?r%VDPYh;*Q!|d^%i@IJg7_nU z!dV9WQ$G*=D__vt2OqlvxlCp)Z10yN1%$uzi;n?KF}F$prchIn_e4H}XElQqm-FGD zeBJkX#EQJR5{e1*qudGPRgX2>|>40z;PK>>D1a^++9n!3>uhrP@YOsXaB9 zoykQEwx>V!TPT*g14A3m_GJ%|T91Jb=h)u7z!CY%EB(xJIYj$*jmvaT%0479$xJYhb&_L8tXE_hlqfm2{y7 zzeJWy?WtF()p*^85vI!xJ%}9M^NOorkyd)cd)}xwk&%i|y&0;#=S`vp#Y}SmW^zaF z41J6?ddVy9v@|byBbmjVp$jBfFYn zB!^2qiRA6xhlZ)Qk)gw9@N?bJ-P!J2R-MJZjrX)CZ&yw&u3**fUbV(*WtGEz&N5Z) zsROCaVTQ=58Aik2LZz;Di;s-@d$rr0>+jX>fzsc#WPZEumD4ty4!6OTz2`X*;RbgW z37w&5vH4`T>h`GVWOs(}{1+{?-kl*j?)Vb%THKI(vidA+@UJ+FLw*F)OEmo}z5{nz zI^;i&OAHS_aMdd3llWj_>S6dgu7^Pkr(7`{13fhA)_(}r4+!fc$@-K(!JH4ovt(V& zSu=bvo?W&MfcVct@htaL#hgLIE%EGrXi14Wk7x~?`c8zvSYdc`r0dxDPQox?_>GJ2 z#QDE?EuCR}d?&7VBvvNGC5W8*cIZ?gEQ-$qqVTVXXN1MYv{Gd}!)0Lc4jiDWc!nm^ zhNw1%Ko=Y0+O-}h($IJvc{w#u*r~q?5%Z52t+XT(@Q>I83J^{H5!;QMLCx}?F>PD0 z{4}Onii3Wx0jK^r4ArB;?S_ckqp|T3w?|{sbKD-waeF$S+q0J2@lf{$;r3C)?S|M` z>AYmv8)7=8Nb0&N$L>zcVLCi}gK!wJ!J2PFY>aUD{T2+|hFJeAk?UNbIXLxGF>r?p z*>Mrsp|Mdy=06XzLt``Uj>rzzWGRW_HKr##_6d)+dc2Oc%NL4PPM&Y|_(F+Ybk_Vr z?ar7GlYgO(U^#UbN9!v!I5(tUE3tp-WTrXnBqeJ~Rw$22R-iu*G8#x8snb9^z7GT> zjWIK))n~E${Iw`_aHP<$l{Sp1{%bW&ln~S2sO6IT?Mjb(iu`_~fp(o|{-7-PU%(B{ z7Veiu+|O2GKkZ28<`{0&JRE$sT{(+|$h*MWXtC;~(KXQ$(|bv(2P+-TE)(%`RWC;R zBQwPz2Ka~?9;yLqzS0VM1|(BO(5OhzRF#)PrfES={UXfBor1X_!tBh)9BnZVhp=kF zJSD=cRvkIzYYk>!(<^X{M>Dz~95v324}9ZwP#Mw(Vc7Pdcpaq zD=o%R<8yi()wd?n#@}En|q_b)CKQK?F=4bYd)KSIcF;+=aH<3UQiv!TXuu8t3V`iD4o|En6j zfl^=9z*u(OY5SDW18OLto5-%>6I48;illkxUtze4I&`yc>NHKx7==Z$quho`kY57w zA%Dc%D*Vmg9@j1L|M-Pi#Jb)gN3Ov!@H5zmJ{{^*v7SbUcE< zpZD%&n7Mo@*MriUXsZTbHRow!WVQ@J+W<4;c>^`EL*+QFM9TF5!#|J;+>mN=1AL+k z@CaI(g4^>1i@w`YU)-L_s}~mAvqIFdhC%#9(whe@2$r5NmlIU zs7NW$0#yW!CPTtCLQ1?bk*x@god`e0(Q&yNUQ!vxO9q$hT~n^g;9}zq9(MFJK9MJ~ zfE%nK`i1*BVpkteayd|^D6r|49wRmPP#NiisF6*H1sN~JPQ0W$?D4w7>6OLdVX#gt zzY2j@>`brBpx&)iVW?3l+^Z=7eO%m%7$JtnWiWKLQAi#`XK&M`%`K?4pfK5kzxzX34RVX#RlK7R?T5%(-YJy-7YR11& zpssEcxTe$zn_cp$6?32M=CKi{GaooY&*?S8XALcDQ^I1Ppv;nJzB z?MBpTt%kw|0gP?5Y7%o{Ae#*;>NT4dYiNTxObi_nwi-S%zK9emFQJhWNF$7J75q1Z z4``XJYY)Ybx67BPl^ZF2jAU$Yx+fJQ>ax<^VO?#{%YUO66kyI>jTOqHG+`{R(k(4QFQIcJOIcTB>Yo*C1g zCUI^f1B)Ow#e14ZGdM9r7TPnBvu98kgGqKOwRNXL8&yT)on4Kqk#TWhKmTWibwIk2 zmLkS>;B?iD;q^Nm3Ao53k&sN4ATkD#lM1_&%ylP4_n>0oAcvSm*7u5S2TBS%hqO~D zl0M09zyYGHNaO0{3Y)@5E09;=0dd=*@A%#QVm>c?`Ix{rsfp0F1XCzzewpf)gLR+K0LXyrU!=tJwNw=BdGun*MnH32Z z$CmlA8hH%7RB-cWWLpQ1k*Q3>G?|{6bFgOz%NO^vg!I3JoxK7*js#`-<`%0~!Vy$E~QmE1T zqSXzDyOCoz75Y|l&bK&M4~XJnG7M(@1$W8^IbOpt)SPsn7Du`b^YnlzXM~+n+U=CG z9e&`UM3!o1E*lwnr1VZttC+P#nY=1TSr#$NG%f`wlAoOPpz9SMa)cRCxE77dnWVW~ z+bJl_LP2JxVchKYzdu5 z0y~yi73ei}Dwh>P?Mp?ne$cau1a7fTaWYTJ1XN-ZS81Uc%j`4)E%IiOa)X7`A#+lN z1eO-ifL=AL!C2*Uhu3BR}~Jzpxhu-7Y1TY;l!Xf1qhSEO#v$E=~o>7!FH|L zpmWub!ek)3fPqdnG#>{$XHFQ+sLR_Kv=ol5_QPRj_A{=9Ny_FOu4W3nw6MbieN>O2 zmoo#tJHlp->6LmR0{6^KiYA4iZm$D9n?V`>`B{{dVn?!M5=Gn4BuPWDLWalj77R zA}7#F>rEqcs}?Ke5No#Wr0^Q;edu+bQ$~|kz}%6WwDhWBFrA>GaMNL{yfjr-)NG9aq6M@?X(uo z=W-#=Y@vIrtk=hKVH7Xyh+7y$o>?d4x@SGY%o@fc?8JkUCJtjXrMNl=2u#IIl89hm z2r((?MJ*k{ju2L|xjrzy#S@q|a8jFVkrUf|uvq(zOg8!`3GrT_EjB`VN|Ix_?q-Ef z8I?94RauA1+w$ZrR}&4To}X$9O&6trBr~GK8!b@JIYg)U!Fp7pT!b?w+Y!B>9kT75 z!_nvTVMkxPX2hn+7*1vm8V)<4Xff3+r;c{Uk@S|+ZJ79K-W1*{27rO|8dkSRE-%;) z=}BaSjhn)p*Dl)T66tn@4mUFATH8bMs9#jPBfr9N3J##y-kGyFj-I%e8=XIqjbWO_ zQB%&S+V0~Ds~8{Fe{+jwV??pBcJcx1ro8;D_h_~Pis5Vcw5Y&(koM->Ude9I^4Ctn zKvs4+Co9Qyk%3(*isBHFJ{;Lf>t|0#p)#3ZxulaV7DyzG(pnLxBy)l}2rh{5V3p*f z>d2=B)RSIrx1zWAwU{0BL8@IUMXpw_2Rk}59=L}$o@=CWTL$SoXqA%`SPti?xg&xo zXof~fRL{~);?d1|4W(VWU^c{)WXmTNMW5a`;z5KJpv{n*7quB|bYfZ@=s0aTeZ@Q@ zYC%ge1#61G8j*x}*R2>4FKH>o`@f>VWQCd{Q7EE~4kJW&CY1>l4+tuynOj5GQ` z1heAJTeWy%Xq-tIM7!g|!Xsf!X_EB7Z8Qckn&M@0i_8+*?h04i-2wYQdtQ#mlz4ig zyB?j4m73uM!=s$RItF0Q$h#^&UR@r_K2$CY%rA>uTeT6Tq4 zEbFa-T?C1<>TdoI$2d9;hsp9p{GH70(T$jeqcWVX(l#(ocxpL9)Qjfe_QC)ov+e90 zFw)Ke1CDFxab_IMNNK-|n8vktMF+xo?p+W{=5Rl9`6z;f!VUu+Q720Ak4XvRZdoHB&jE6^e z`TKkAWteJm69q?pn5i(HsK=Q;9g_jfjj!#6K1Yh`3(sZfhdzfTq5B#{#FgY=bM+`Ve(ljM`xgd&r@e~LS$aXDn#25 zXLdOo>Z)oxQH!EPlm`p?_^H-dQo7Cu3&zO|E=Qr>I+w{ig9}H6DDVmfRKex|zssoQ zH|k8oM!mitYJI559s@ON`h-pYErpqad19FM<*hSIZX00pOLLwBBEb}H+Q$bLdKQe!hdQ;z?TbNFBYMg@H9H7g(cp zV2#laS;m?~Y7`q+m{-R`&%7v_z>z6BB9(-@S; zEIs&@^q(s2zJqiw6r0GZD_ZeMFxY2uH5gw$bJlp`EH-D>*^#TaBZqu!7Y0Ty3I2yu zQSDv!;qKPnHPBbK$};vrolF`W0A}TAK7;eHZg_t5i$mG`Y{E`ff04-~3sLd*C|5~u z$n!Gu0NEhP#)Lt( zjSY$2ibuB#Qrdw+?Le|kmy`XX$VYPr^JeG;Nlu7L2OMqcvjcthX2Op4&VRgY4>u~e zI!2Wo8qdIcsyX?KT_{1g7hfe)REc?!XGCui8<0!q)8T z=xD^%JV!sHikQJ7;3PT92icodPBh4o2WG)9m_He>9n z$X@P>;)Sg^a~l{9PE@JM^G?}K5q6gmD@~}(wlugaENjP?T9NB`aBIjFD=@_P{!V%h=y3)NT1Nz6F;qg zc@#JmI-6n3U2p?U2T7GpmYAm*tJOAVZgu1w4FWt zGuI33t8)?3sMkaEV046DZT#HS)H{$$?+Q+x|I3v}u@y#TyJ$EVaU)GwNS`>Ic3I3ma9gUi!m3!uy2P(J zB;7#=W7Pdl@zmx)>=7<0(#=K{W_Eku5zeP?e&}P%u{K1;i8fe#o1wv@Y^cO#GJ@V@ zE<}Vq{^wGj^^hm`t0tPrX|9Zv$6+0YE#IJ-TvtGsvdc~cEAByB2DY2HUMxL`I)!fr zEKD(zaw%rA&L~rKM(O3WwIjkV?~Y4fVM^JlFn`F^M|sdM{>2G(m;78nRarSTKWFIi z*_CN`T2ybMdU`}{oN2fG3O+C2JtBbvSX0bMMIr7udqgC_aGaTX;j^b1SMVKChnpn$ zW{9oVS$R{m9>M$#K-}03KIrP{)QggUKVX@t*Z$jhco4a=gbHtE%7i7(jPn|uv5Gjd z#X5MojyJ)puQ|%fUa0jZJ_ncSErMAU${qr@8gt7+WH5MX-W^?gH&AaD%B?l4bU+)) z*kcs>Pj$|Jco7>W)(3;K6krI|nNFG^tS|JL!BH+i$B3Rg(V_n}>ftIl10+^c{-{z@ zUcZhKpRO=7jaieJiAE1(bh$xa*Nb!=c#qz$%&^wd+rIxY&!E@bGUn|&at}3y2PPt( zwdEmfJ=^G+gF8g-sl{Ac=`!tKdL;7}6S;fxb{@f4(G=0sA7k_C$TP9?vr5?UmHRQd zVKTlK-QMIQpWKtg!8xyQurrQ6x-}YO$Z|8z&~46wP1>QNHITkHFKeLYYMpjl^1MRN z5CiYdGbS*P6r|xcozEl2xyLy9u7MfEjD!g#rX)R$U=wC6w!P#%99yIFvg*}Oc64Uv zxqumyKh}I)G*(B@xLjVq?7=vgU}u<#g}UqM zAzIHgz|Zhm6S?z)p5z~^ptBrtoo>5zSoP#D&Gg1RTj(GVU2so&+sm~moCYk{qPQBk zTC*|1t@8k9-}>;=#-9D`i5Vh$OGLYT-chxLxN%1sb>LNzf_B(Q-#?4|w^GMpZmm`r zx4AW&Uc=RH)5r6dYq@yHEz-8~Z#**9tI&cEoG{f5EzFw*~5n`Ap*=z$%MzG4QF(^e)DyDl?aa5uHaT$R?IG;%<6Zf_TG9fdB; z@Y^ABc&_RA=@YD%q8SH|NX1J;3r61P!iXA^i>R>%ReXel&lAhM1dcfw-wNFt|%~Y}pCTZinn$ zKI3MUhH*6Bx%)cX3^qJTqO<0G4ov5Sfh!N|xa?%!l%{g0Y^Z;H58%HI^(Qv>NfH*Rurpi`R+n3+u{7RG)$7yFrfe`D-->0s|>?Dj+% zhS6!`c2ePfW^!TBPsw+D-MQZUxZW{Zgqi{C+g70CgJRZ1cFDE#){&iaIzCK94mNlC z%;%-!(F%^w6t`+N_Z13h@;(yAPvr9Edj7}4at2}WB(<%!deUe=+RJpu2{?M(!;iu` zil2W4N+~}Li!1UldW$o`jWid2qT+AAZ` z0fki$2R;SL=}(zE^QPfyBEIX;zI=ScAV41<|M$ncKUe*mq{UPhsab9jt7qwIq)A`! z8-d@{g144Vcg5u=Z6X)P52VfYS31E-^_yI`L(M|>16Dg~FMI(Ra7r{zu-Zuv556N- zZ4&%7pk+5`6t$P@rsAuoZ*o*TAQ^dJx^?`m5uAW^0lo)1<^*jh#$uzXlrGEHLxXO- zFb0+zjLz$;uC78~t5|LNYOpKRY`22dvuT2WxK*M@kVUaw&1UUX6k!raDe8xRj?XIB zDFM@xviKUc$;I~xLqK(W<=Rbdbt5c;?*^GmBoy(3qsvfi(uykoNFgqQ1&XRuE1Yqy z@rKbjOJ#@7L(@pxp-XajP5F3K!rvl|`0h40(UI3%TRlrx=SKDk!52?xRCC;xR*@3C z$m-;3XIy>iJB$}N2Q3)M7LKhG%s>%(QlR6{2jDsrA#vh-Eipz@=xQG$;`;MRrh>)v z1r+1>-aZul*cgnm6I@CLVh@nrB-}JvpPECmJA`Zw$yl^x9|##Rs05vxhVOSvu8EP1 z&fxgnQau{gm#OC!{ync=#5Y>1O~iNnDrugJes5754H@fwsTY?iLF2M#6!`065PK&?iv{w3kQDU{Di$%>vYg|9qG)vZX>Mqxv?ABh_5$?)U^; z#MUe~Xee3X&vO?DsMKE}2ySZyBL$39t;L9{ zV+ghwt0mY_yt|msEL$|q;?f}thy3ETj^e@He*ChE2wlkT+N-2_PJ=kK>@gd zXr@ydMS>fZ_$n5>3|)Y*3pOigv6snuuw(A!e<;%Z#0BoG3)~A_*H5MPx*&EzOhc(u z2xv|O78OO{d>|K96zy%B30Dja^TDC*DFH8V+1S3DcR|3y{3TWz^a$YNPDbr5?&X&N z;ONYAgKD@Y1H|-WnSc4^m_Qsck10z#`;u>?W!o|l*!ovWPdi|biIeemsk%x@sN<_2 z*?g5Ww;(LqGI+~o@pg&2lo29cK%6@Sr$p`TR<+`7FPXX)qhjkD?qt)xzGjI zpa!7^7N*GLVv4hoDIxn_A!2&0Z-GJub+cH<90R;Z1rO2eR@Vwg%zeK9q}2ML4pMll zr~nImFA!e-YtrO`VE#h9Em{mJb%eRu{Fykv(62 zKiW-ts>h(!?*uR2X%R|`_D5;|!qSmEz+>#6L9g(w(+L3@JkkB z)4D)mhoS{hMIA}(3o#|;Uj98oJsxt#&qViTUd%jrvAPT+hOBr6p)1s*gdSCYAoK_1 zNMkt5#xQ9@JT;Bvh-OgA%tUGCMh4kNlF(EGUxu(GTFBn zj1?6u)gsGG?AF=_uZr2esv62vH?Y{y;m6gVwq6E3NEUY5e_Hs-!l5dUUlCWYP6fnN zoVZo>LWo&-A_LXDe2w0U{LtD5^x2!-z7+sgkQPEEv1y#D*vgn&b)p9yhs7WQFU;^5 z1l!EsH^4*s#7*YJS7Z6L=pd+zI2OzSxL9|&O_Sp*l8`wU<@swc3=ClOfO971*Rd!z z#8zTS?MXEkFIbkc+KI39Hi31}4ImnE&@2KRBc2m1Gey+eA_!LH6R;cpnW%BOlyn=h zy4Km6s~26b*Fv?yN@tDJFf7>Q*4lCc<(8& zMkB|KMk1stctuUK&?HRRYMs+>5W>OmC_FVqZW^`F2<&=!Rk_;gzHqx~JI~gWU$L~$iD%D_C zpVh2Zp$0P}xCG--}*mW3kvBI~}QW`o%Fb!5cnU z9lKRRYL?EV_pcQh)!qthwz2DM_Ys;bwRf7T&U0g?P7kqGD&>E9Ck`{9F~rDv@1zHZF5 z&Xd-8x|Qni<-aZBXCROdy@*SeOO@=+q^+Y!hLWQ^qd$hdrGEME2~8jC4?0)z-^J=l z{vUvV-k=@tY{qJ)kR07$>jK>xb;dA9XV^Mlw?>_@t#hPxj&7CRsbkdIxGjZZ(vz9K zESNT7%Cx0*>JDYf&@T9ZJ@YR=;9#w)hTYUl*x%+_A26-3UX$=0ZHClcbxh&l0%Nma z=oO9j&&K8O&*dv}?rCr)!}lh$+N=#gxWud){l|n$0CyX`-6prFR~JM{+g7s1>D|4x zWre(V5NSXSd+;>)#NsP((!`hlwy@mN^>!8QuhTqYV<(&~Si92~9q#tW{TiC{w<`LnK`gFeq$g5g7oT7u?W zj*?z$q)v=+Cy}r&TXLELbecMwdt|_8tMgfLzPeIZ7%Sxe^OuSSe$ng;V%QHay1<=> zZLOce<~IkX>aqC+s2l4Wu=yp{)cJ`ETu^Wyys!ieMsE@h_~*I{7Y(dgw75{nvcvPZ zicbD=QDy{mUVLQkRAG(O2G|S-WiaT%rSKkDll{L^`CooFL=Ogr*O3jdhPeI}gza@3URVjqf4xuSORK-cOi#-Ahf zS+&^hg?}w31GZx?oh!;Du4@g|MxkPixH#w#O`!0lQp=5RYa8C$M`|WZQO&g!SnDD; zvw@f|u}V&YOgw6f@{DNlLE=CfN%7lH`SK4p0v5Rom&8xRdVI-JX$+1L5u&Fqiii_Y z8^igSJ#qvGR&jcs<<7?D0Xzdi%7y1zBVwN0KR13XM9iJ9C$H1ckkq|kvB(5~|Dq5` z1TBLn$A&=b*a^T+b2KnVPDSB7{z1YbMiwLWycH}))kLVQ5>n(*Tih1s(m_`M zp-8Vgl)pS;fZ^q0C~B4s6mear6tYXX#=+v*U}(3~>gsoYqu`E(E@Qi4gzkQn`WKhY{MGeoEtgaTm&tO zM#R4F=w>@~y0HYkDIrq~9aLmxr~hSpt5I<(;J6MSJgN{iZsC#P^RcHr^pydI$|4M2 zRQ9pXNMfMSb`09MEsx5!4IN&GwnpQvx;#M!Q;VAN$i6)S89@7brT%$c(Y)8;B z%{DwHcTOn+^0<{(NMkz=W?MEY^Ki3o=C*1-Q@@UFtNw}Dv)ihNBuouEOIKnZR?=8~ zZjRj@GsZg(4L9ir8-Xrcy|D$?6$N_3mS=+m+c7@&2yR1pO>RrJS;W*J5Nqn=8}2#D zoxK9V0Sl}{Ly_1@7xRRWU6~wF3+J-Drqm#gx{VheWw8clc8TxlWac`lq%Mv@s)HOu zQEMYiV5ne@1T?uELsiJZUIh*$*pK;8qQaO&m$g5!T%JQI=ad28@Y_X?IYu{k?mA`F z#FW^F#)Gtdc0+M7>?4Oy1YG>$oIZaa-)+y|<3fRKr4s`TzZRI0Arw2#nu3n|g&j8( zRkq`VeIvkhUb8Tju3r?#^GmnL%%=As8f?1JdouUUl$wGy2-6?Pp-bx0`1*7tnO?c zR(5(0%P=;4Ye6x#^=R^~1>dXIov}`hHGF?=08j+$poJNEDul_5wbM{+)JgJ~-`FD$VEcCyWI(MBq4SNpLPFXpe-uQ+Yo7~==5TZLR zlroW7$j4fUi2Wh}srPn^W<&DEX=l3+Dl?-j{e;gp>Mu2W`9`NZ{_DNoFOjWj!c zjJwHY1O7u=;D9e4gn*OsgGay!6Ls(|{yTbQ#wwh<0oE^{6|OU01dLBZSh`!vYmVnX zK{7bqA`A5*DjxTP=Ru35q2Vt{=>t^pp$f+4Q53O4$rUNp)C%rjfPfPNtndRCi!@^u zybVAfdsDnm?fD2B`wZ@kv5CNmxE~3H1+7qh(&!V!EF|41DMy#etE4Xmvr6P(&85d+ zF2|r3W=q62%%IOLv}HzN^h!txmdC50L29rfP(9&F!xQdPe0cwq`?Q9ibzk;0srQP9hF84x zfxzp7Qv2h17W=VcmxW`kU7o+X<}pJE!7pCJ$cR zm!TB?eW;#>!@AG9FM9a*ns+H4z`8g1oB40E|F{q9x#uO$!!KIUpfpEdg7`s{3wISQ zH8d7ai~KOQVGc|fbfStIBuqGsY&F#%;)Lbpn0fN%{~M4C|H9((`Ivu#P6HT8)<2Km zTjr^%9uK_xB{&Rl@zl28orW7E3*3#d%ej%e95b~{AHjQMM?n~M3UVPQ<_b55MQ8;U z0rz^g7}ch%c!QNP(&-`oOpzRV@ryk?6%McGnH5;D8fD?3%Xv(6Mbw92HjwdHejn+N zPsqhL`)G~{H1NTxK`K7h!ObmPN~#^rOG*0WFBB4)nA>9;c6JY4ukeq0Y(Yy=In4K6 zef(m*JmSqSGHhwUhqtv9ViIiA3QI9hUxAIfz$^o%UU$cX<1l~{2@)#)wKCc-Vieui zV&}%COTlQIXZt4W`I`mf7C6ekJZW=pk~t#yuZ8jp2ah6Njy^i!tS=LJvhmb9gEDCjjr>P9|9 zze-)J&x%m{hLH5Z{p1<_Y&d#eEf1LS_r3XrT&M)unln_M|P4R z0~n@30s&mU76e|bSo;J0Tq&<|wp3~@P@M&#>ttc&ogakXxKFCDwXe}GQS08)y0>nH zq1hO<`th4OF(VSi7Rkkw1y#TK(?nPkqAD{VF*P3-Q5Lw@;0PSR8|tInBLz!jC`SA7 z=R^d^_HyShvf!d+0GHhYQM&mSvf2v+`;o1(jPOf4BD)OJKA#&dbTdF*D5&<{(B*bscr(eVkNL?0ZxqXh9XPv1p$Wtulf&A91oo9y!U4F3bn&apW4z2Ql3E z<9wiBzDCCy36tc)eIak(#Zq2!O-v>wgO~TupDYsk5p(^sWqYykK$KS;gSX>P_G{F`gwKp!h|6nvoNUqWH5}o!2S9}*aks!d4)b!qdz!*?qJH;WwE^1C zc7LJnCwRYlNWjx^rA!-?p9jH#EjR{Lk42=;v&q-^FPr9IMloCMtI%Xl%x)tV?n@Bk zHI#in{%<)KVvYX@TOH1cZqp<^1)@6Ff*H~c&@880{Wv8;Q6o71vqH;Fs2k&0F4aC3 ze1iHpdN2M3ia268?_@`OSX27rIrU+ho6TF3IGU-5AC1IXVej|(mz#Fn&nmV$`8P+ECV3e~u&cH0;I+L-C>z~WD+&-}l7y+D?&vMtRQ(@+Q_i6Pu z!4K4b20r;P>h=o{x$4wyZ#K`EZA-J~1siY?N$xuzy4KdNJz3?dpHOdbLG!M9kN@6N zpDKe^psc^d$XVoOcU3qhUx~MS6jJLV35eZ`;OuW|!n1WU(!30+k%DffNs)XTTIQKyR{z;f**ay`J$v`<{s8L9AO*&v!g- zlcki{8^Z(lq}lBAZXdstg>k?>)vYEbPS5ePSh+=WX&d}jX>mqotvrJr`oAMK zb^Nb54z6&Rm+5y=<<_0$nZh=!%c@EZwowtA|DlLsSY0kx32Vc+mWOV&^*FB@3%{+$ z8iQ#4`fxrU(f7sjFs_96(1fyIj*)EKZvYfcHqi{{F=6FIxu+GbO6~O zTCREIR}O8eFx>KMn>w~eHT>a0ABf{U!LLV;Q9F^3l0d4RJq%`{R<(z3FSWm0c6w65U*FeJoYJ?`RMw6mO z)5`b_jf}V>4Z3^WT3b3_U4$i$Fu`K;HCvAQU@2pGLVes?zLSFgiH-kTV`7|viFd)o zf5DW~mIxUI!?`HF;cz*$!kz9VUVI&6bIFlXc^r1FXd@dbkPi!ni{B)jI@GFv-0`+_ zx%$h1j#ymj#_@b7PEP%(oys3i<)wXq(gq7#T&NYuMsSf)dC{R#c^u9y&_?3_lcwhn z(9~~}J}t97xdb0hFlFhrZD$YIW_u9TLvyJw(A>0Ql>^;kc!KNtbB*3}mq{gQB8B~# zqD0mzvFe6G9jJ+mbw@vDdZbxw=lL>E#yI!8zOIhN<5Jy(qX`LrEY>wHmVBt>b9H=< z9%nE_)OC)Va(3V3BHMFg4z{lesysZ$jbc3opkB6Tevu-dIAq34FfHN28SZM&M``{( zsM}|0-ZMC`st{}*TzI&t?atmCrM>wfkGV_rgoR&6ZJI1gM*dK0(_|&U)Vty%2OGtXz8nB^ z1Z2!-yL|a;MDHdDXzI-wJZfmcfVT3%?D&b6;x?h+3|n@My=($}U0sO`RM`rhTd(2M zTJ!WQYMkv>g2vq0R(RC#sxafD_O>kEvNPfY zhct5k(+w*4IhJAN8V8cx=}4!YU{u58~<50bmA{Xhk7Fo?+*SGM!rNd2qiu3!4 zSwh*#8k#%}ET+v7Ks4}g5?y5}p8rf%SJz^EYFUjz6@eT-e8lVj@%AS0b)Ds%|G9ea zd#_e+TD;p=@){>vy~GK!6Y1WoNVX&^T5Koda*<`p7TA)JB(~VaY2B<=Fiz?Woc^1=>4D__YD>!NoXwDJVhaOAd&V>5w z1nqSa>;pIO=Z4+@)Edr>m6>Wc55!DV^TXz`gPN4xO4%}eCdH$n71!_sSbc#RI@)9hXng14q0#!iRlw zjpQMnW~IkN6|X19o_>9W0axC?{~o|I1~!@*Ndzd8cB6^OQI>mD&{8sZ5qw<~v^*?5 zRl(C!6(4lr`Gf9hN5RwX^D-TucVCFhzu^8!<^SX!7tZMTIGJw{O#t&D5V|7cI^t;A zp6e=>Dw4W7?{-iZl5(GHHtaLT2)^no?OG;wCaz^79TG|3I1}cYd8N%H9F&_(q;n%g ziByTTDnG@zYhVskNaa6q@8d~%%(SrUm2n?1uQ7R6Q}I})#Q`+5-hLu*t1UBrxfbKwPj1j^Q4pzkY({_5Mz@&A435-;*}omv87?Y6 zwM_owIiIyYrkrxv`&>(4fR@udoW5ue)-sbcL}RHqhO1nR#!_)?0m?8D;MfG_XP7B# zQe3x5Z~k@Xx$7I?&j4q_=~8)s-H1e&XWq9>B&eq0BURt1VgUsG1u5OpSSEnd)fOCJP^x7z1-*E>49X50izL=j>=7zvc!Q!77=Z zXmE>|#s*&Q2z_t11{o>j%svYBFEe6=W_H&3#b`g&?9CP7yF;V_A2PA>;7-sNuC6GdlNy*kR=T-d&K!_5QR zuZcGoD&I**0>eLUk9U{j=l7UqFodWi9X*=OI4ewlC;Ps-_+HF^#Q>L|FArc?U=!Ge zsa&1pMHFu^%8}vc(XFSrp3~vEju#{4Vi5rm;DUmWGZel^FNwaq(u|er=zDyXofX?DEnM((i|1?Jk`~qIjm?;8aSz0esAaIk_w^` zW=NjIaLK*QWqdrZat9dK5DdMA`!yN2sv|y67C*0Jqbp`sm87F5fz%4q&sKi~NRtLv z4gmIFFhFGo-Jc^9|IL`5<$~vp;6`AzNk@+`g|$lme)T(p0@Y7zh}Ia$P!JeI=(N-qwVe0^muWpIQ!3Qjh?2xkWNx%TC_I4C=Vj?m52@4w!|f z>i_(K$?gxcK~S+{cw>B?w2%`+0LH9pGizN9L7=H<5Gcox;Cqj$QvN%}9dAFWE7!^l^3 zPo6{f@a?XZ1^Tl`YQYiR43l;ZGuL@hlYymoggYN|Kp`ygOc zrmI)(GB$mhCtQ}W9x14dO466PC;eph!7`Yv>dRDrgjhc~5z7j`aGAB#CLKKky{%RH zZP~9^zNkmcNnfY!yUXJNfM8g&O9M3Fvo~$<3lBb+Cji>w7e4mw-ZIHIS(A0Bi*+r2 z(VDdE@r%owv{;kO>V@BU-60aRH}|eA=VYr_E&N9M%ChPeE0v*K)(l80`xt{)LUsFH zAZ@6y6DO4s#XA2CN7yarYzKE-A2z6yf_^KYqgGR0(Qnvq5KO@quZwRPBe?~gk5Re| zSs+6t>F9|BN9kw$htSFa|EAX7Zw-dU-=FedkR1}ZzZnL40~XaN9Y6o5J=1`HnP;r0 zUMhdgKjFDN;h*%{M-0_pvT7NqxBH(aB|>TC-%?gSDgo$^U}KhITH1Yb7Amf@)7|BJ zKuhk?nw9qST}G&mN3i>3gbc{tO`WOwnp9I>AEnEW2O6$B_$$%og!z8GWDi z?<=FP+&G}@Jr zMYNTs%PE(6?m7|g6uRQnsU&Fl1_CG)bU+;;p`tS@H=jbh5Kg3lZ;yBM$AH{f@t3I(Hc%R~`arIRL!J~i6;ZL5w z6u0|Ed`(v(RaELD1ov`%1J~vK^a_6q<$5iDH`hPrn&bKnuG_il?R4Q&Z;k8vAlL73 zy_ZEl#kHF^Jk{?ESFQg+u7XqV8SDBO*LC1Y?`>Y>S?@b)T|$oVV{Zj=wfEV$>LsT$ zT=mw{Nv?X`=a0GS-x~h2_fxpqD;-?zy$P<}tHB$HerIFAw;gT;2j|(I>Zkq#Ttz4C z%?h8|Lt7Pu$LK?m;fYI5^YUM=!1dAi`YhK+c>WH15~sK-7k)EWrLy12RoUaaxGJAI z&Q*C(U6s7-;Hqq;)}{R8&0If2`);nv@QrX)#_b$ey!mJZ0x5`B`LkSww^I=5JC)qT z|Agy`Xv<-gsFj?&mbE99TtofXO-a2L{oIS{Utg}5Y-wG|zmG%bMEJazpJ~{$iG29} zRk+WnFj}EcOhvxZ9y00s-<#ruz-K5CPpdGqBE705z4Ht@;6oJ0-^n509Qp9on`%CH z6ZvPYIj>W`Jo5T(44||58u>Z9uV9xu@_z_Plk)KO35L%_{$WsqQcX9ki@aFZpyfV% zqhKdrC`cE+!rUKXS?n35?|DNCHT&@wl)OXlioPfHzEt`nR`&)tCLP_b4*^8}342Jh zEs(zVZ9K;>`15*yVO zf{`t0n9e_I-J84 z>4uZ9eCdcU$wmH0?Qv83QTHee_T%x0Z+CBB_Vf<-m`gvQ4C$AxJiK=jrT2XaSVtQ) z9^3++cAEm=HPYJj2B?v|Kakdo1F&ShT2`hv+@9QL();?-M|ganb!02?Z|l;})jhN_ z{f3nvT?v_!;+LmimwF>ZlnYpWIDbCOsVp5ok9;^seq(y+p2){1w$q~!hE*Dt(8m6v z-IGjN!`D>!YDc>N73n+Rh_|Gku7R9!?Tx*Wf8OpPCqi%_9MnvIAp2&X!V%yI=K*Tk z30HWpHof8_!0<2j%xAiWBd;^4F`}7H!tr)1sZKxV9|F5i+S3hnF@;aW z9)->kL_R(}V0-nEkN4ee^Bk;MH#A>w`Yx%UG)6y^vYDHPd>;f_r}kktoT$#`coBuS&@E@9f`<)w^{8N9M#cc_o$1<>9Ert zRvG`i((VCiXXIs*4DY{}PJgB5lVEMZO3(&iDkMV#_ddBTfKa_E{f?^dRv|=Iz+5nC z$Zdksw#XN@hlZ6PE#xP$9jK`%t^6I?^mnuGuS4$aF-otZ%b&$v2==^EC!}+cEtYNf z6?~$Pk4B;!{4;?-=5^o~NbFKb?H)_mHmd9+#cXS1@}74cv5WV7bSX3dMunh%>b4>oK5YgS}? zXGPYW*Q~j&S#w;o=C)?dY0a9;nl*Q(1FUvrhrSs;s%F zSAZ12GuJe0j%n81(yTe9S#wF__U4Xe%^A&_E1ES&G;3~X)|^msMYuw#ta+fRtT~`r zb3e1@eDd~%ppfJFwu-FzomulbQ(1F5v*vPU&EZUC&EL$Lx0y9xlUDp&lQl;(Yi?%N zoXo6T%;zez=3!>dzg(F$_cCkFW!7BFtQ^aS11-`vR7QVuC$lH{TgX0Yf1l;=BdM%8 zlUZ{mv*t*qvgSu-&5O*wuL2)3YaV3Q{Ku?$k6H5_v*tNw&2P-gYy3<)YffYKS-Ff^ za~M}gnDnwAmkmzdqr<#f9O;{J6{&CY@o#Mh(2D<3`5W6O7N-{$+b7RY-_>?{;nJD8 z>4o;f{M4lj({oFU?YGP>^k9Bpd;!iD*{@2B_q+0*U$p|OFn(*AI5&(AMRw-3xsoxgNu`uiF2+@0;G z7caIiOn#r8FHBu3BW1=0YS%?b)3{R?7H1dR3)6SZPEEIu7Ke*tJ!9=-^OqK;rlYAF zPhAo%PA#X!sWS;JPMw`yI(O;xDQIyjrp2jqcb;OxQ!y1zG1IAqNxLxNDJHb)$@Ay` z@2_T|G&?Ug_SI zi|uD-E`2`(z$yO*u@_1+41TV3?&AL+V=qq4mS(%YuXX>Qz&?BN`zGo9;^g4bd-w846l?-pIy*HL9%m*m%$~oSfw8BHcP}nYU*MiFc5w+HE?o={$X%&C z0b19d&(BZ2YLWW*`Ru~{rHiH6g;!rLT9`gN%ZLl5iwpBh(^E^c^K+px5jCDLEgEfh z9&qB3G=@Fc!e(Y?=4r<|S@s$3h>djzKyynA^XEg!g~?fsja`NLOFGPAqw-!5(7T}gR)o_sD4oA}C*6Bn{%J79;7zr8pJ}GH!~K2*{j8EA_e)eaWLDz{=X^sq zCGCErn^6n(QYT-VN#)vdYP>#0U~$H4On{{{0czaw|ov?Z7|ZML37=iOQ(ICyVe%TCUhGU)VOg2slFl|X50ZX zmjI^$aJ>7inl>wXpA}`au$24a z{izCn8IAIN-OpuhC8^BnoZr-JBo<8|btV_c&3&_9A?j8Nt&N+E82-xJkvIaA3B+vBA|)ov9D?)mAUB+x>n-{aUJ;LsgAc$rUH} zVO4M+t365#htH)y{(3GIC%xCD(XZ7-ZS30X8?SioEI+GrMN2?Nt<54=-@QRy>-~0{ z<*@JPx-IAXbH209H+F-;hBlHmthLViC@^q;BcSVrARrs^)hT~t%2ze|`IWlyj)HpX zz>@LP3hSw0!u_^-Hq=9>t?rv9Fb!#{GwuiPOHt_D|E_=pFwF`^cCWRO~i5SR#4DufX`J>2x8OQ+6kb$#q891h7_6YVN zgY2)v5CO8c-Hw$<3DGv%+ zyGC|D^+2k=p&`A>H@T+)%C8OB-y@VZ2-U09>QM?eEQqs z*>gtcoXvJ~07ykU4UlC386az7KtP&%7Gc@oJ|78Juk_Mf$8sKguWIwFGdIOp>+%g0 z?d$Tp(A0Z;V`jS)zF(i|IAj#OuFb(k>sfc>UccVm!jP^0$iYmGrfz@kg^gi9*3IVY zbN8qG0lQ849$k<4^Sb2txo2x|1LViX-f|`N} zmEK0Lcl&jqG9~%%sL$kN(q%vE!@L##0)4a9*pD~ zU+aF?=bE>gIly#tZ3*=sxF<#R8uuxm^KAZq=N_hLj4f~rpfujV)Y}A;Y>E5dX>%OZ z*ZtBxIh*d&zRhpQv`DE|yI+3|gE!R2BXq#K>zMo=gM24XHZ^}YW!wiD%Y)Y@YrHb! z{_ATPsLgMI8)(l$R;B2HPqA6+-gdR#E9nRaX=pS;#y!KhjXY&Kef?%ScE-TC>Kt%3 z_^n$QyM4wCI!04|8vKWfufSHd;(;x`_Aq}TMm%VNVK4gDK3?pw%tyzmD1$LUnd)|{))wdR6h z4Q`Y&Q0^DRB=z+$!79J0!>6|RO)bFQlE4F;^?v16mUxslu1N@Y7tk5*hX4`?)}uAk ze%k$je2n#O8;X_|{}P3z{}qCN#nSn>L2#0)n*Ey14BKh`M7G`MaWGna7DjdZ%d<PEdr3+%nFZs z!!7f5?tNMdIIFRRhNJ!YE#_nvJ-z$pLYrJL<^1G}R zga8Hw?eYkYsNJt1N)7J!LuGr)?+~|g>GnHmg)6j~r<#Da_aXh_n4c}9?MUF5XA`uo z+2X5auf$yLrBNrIb$BEJW9@#YBtPY=!)2o`w6I69)nRM6zB{a^BSG-OOCcC`K~X4a z>Hg6a1+F$@;dY}}B;0;O&eyheGf1=FnyK@(`Qj-N)r1)FV9n>X>gnEFaI{3r&=% zbw3%g6iCyTHkAC{}^s9rU%^{OZmA zFh<|GRo(R#kh#ATrz_-YazBB$q{f*x{jJxZ2EWEi%<+X`?O~gEO?T#sTA4N0AlAVB zw+F0){-loRkKMh*A2&m-!w;x&_ec+h?iX!zbHZ&L8S{$Ej~X!sPcfyQ+&^m>x@*9I za>-anTTU+BWbQ(R`;Yg9(s&-locpc!SIfQiSnpT8#1MxmOSw15{mLBHI4MDS)s>|( zC#hy>;jee{lsD%B#n$?pUkRd|6b3 zoDcEF;r0fpY+sw3f%{jO8@mN>y@C5wW@k>EA6ygV_uWsYPY|hu+6C%&QPl{mQhwq6cH;k%13HO^CwH_#bL9nkEm;Vo- z+U9=w0aQ*-(#&6MU)2#B{i+%@$p@7dc0WRAgw+#U2iJxEpjO))?nl9>uUA}9=Qr=r z!ZbDkdu1;!giJ;SJR(Rr>L9_T|P{8#%_jOi9U5gxx z4Z_Qhf%H1pLTRJRsGx=f2j7rv>{ucEC*NG*N`wx3~`&LaJvXqsN=2)9^|gxSh3E% z2YvzOr|@{R7RFhF@d-_rj`){xcb!JK$)e*rOgM8K(LkTOFXi5uW+!%aHrW9?gjR>I73Ku>8DM*+2|NISZ)GnR$o5YG;~cnQ>QS z;pNH41k^2SmvT9z8!|E(_Xqc(qB8Dv$ZjgrMcz!)z15LRVF)JM99YvFr8@U2Tp;Sd zfMS+kFRUm^t?%?J-JH@Jjx1Q9>vm&+y3D@#8r(u4%Eeg%VgS^E_BP#@SW7cr+07nt zZtB<$2jjTcxuu-n*I7{|ts1Po_CTF70n*~Dr8W-9E_D07y5#Upu7g7D0)Z&7AsB#- zel-(mkVDCRzIKb>*K)Jpd>{iK@sbDhjf-|V@md?x)rw0og^aorU!@hZkn=BVV~*`S z!m5p_Ol;XVdQKBnXye=cGm9W8jb!*P{F}SM`+h&r;+VEOHn~(XGoMcc+N#sXiva> z46U%b(N{MoHR3vL;=AAFg>Dv1#D~LtsKr;qn?zQvnb=xa824(Y-~CtxO$j_9Z_w48UZAYY^do9jsoQR&qjK;SE2PFk>PKfWIO2y{r3U9tj>DSm zq?kW_Klwg5-~OTkGwx6CGiq()_D|5tDItZX7X7>b9s<^C_gNG&IUMW(gQ_JFYtV>s zE{Svl?gTNLfZ^dYL~t^G!oTHEWDB04TZ8)whKq(WtN2?OBG(3isQyU^B%``ghNA^# zPpoITuzE69gqm8^uU1M91>L$Wyd&&4-M!_uqs@M^tLa9i?8>D#BMHBD7aW7ef#`3~ zqEeCk4&QhyHvqFa(~_~6e1?06d)Y=#>X0WN1T-~Bftu98g!E=m>ujTb;x1{`&F;h5 zoZooZSN*P)ew?{jLZ&y9TcR5NdnyYHheY+V5b|rNKH@|nNIOzpxt!%6;;dVPNtw>e zxX(%;eFrP-BbMFnH}5eicnWSl5~AY*Mx>KM=hn7mPEv*lo@1Fi2|i77F~~}aR6BsL zbN8@_oy+B32Xfq3m&rYLKq;T*tt~dywQV*N>9pe}G1(3haXUfpJxkv2+v}@Qb6_NQ09q@6#ZEA8oDt2RgyM&3XvER7auP2w#>DOOp>LrelD@llBpVjTZS)_|| zNp|!Q$ZX$_=&=U^B5E^D{@BgF_MktuT@J?TO&&L5eY12fe%Ctpd-sDTcK;-v>$$s$ zEBiDV$0r%nTkspcb~lWv+>LiXBQ3MRy@_!%Kj6tX^OFQ>^3@kLk?>@Wd4H6FHqQ7; zEM3OE_ch%xC{bOvU(?~Uhw1CwJMPz@weE{Bd$z-hetLOPr?0)%XS;mu9>03O&Gy#& z;lH0TfZE&m*p03AT?|^^;TyIJ17W(Ky;p%B)3sZ-cikt2bHBwh5q&d%whQQ#1LvcOi_M+~+XMP0hZ35P?6`P0~5#{>$B(oEQ;t(FlKm zQ7=PA%@+4x!Gm|Np3(CE9(Yz~nhyCjjB*$Xdo+k{uosNk%ztq2L*0J;o8;$Irj2b{p9_*_D|AellwSb*Snu$p_|-agD-}8D-Y{4O{5pP+^;|L+lx~V;;QJu|Kh4!m-k3l15`z^Rx z8hZ_+Dnm))PTHlJ)Z)8>GJaudQ9BC_?!BS%|Bzbz1KP@;hI{vbI@?$z{X-7^zV0|h z8|NAyLR}>=D6@q+l2?yTmJ6Mw=SlkSLf+sHzZEfz86op)LywDFPN!2R&TDfQ(N&^QX-73QS%pSiU)w78~ zw?mH@d}UM<*x7pzE5P5Zb8iE_b(sy_I1LH-UzGc09rjwBMG`Ph$ulWbkbzC)9x5%%U3l=2tm`zz~XbjR0vLen652KP(s+kB2isZvSZ&s8WBJmOw911^L zzPwRe02?hrz~^3blGW9@ccrx>!}bLPN^fROY#!}#bDBXoSS=T}9(nr>y8BF?K76|R zfv=mhfUX5N!*D-q!%>fi{)`JyKYp(|FxNBqj|z<4 zTO^?w_m9yLqY%Z}%rbqR;7O4&mAjq?RK9%K3txcMrlk7zrov7Wjg(W`Ucc@)U{hMaV>shjzfF&&bn_w+FgU5ZQK<@ zhP?OO$5+w)fd*gG7=$YGa-OeW_N>Hy58Y7lHD~>1lQ>4IRc4^oy$SigtR+wa&l5m* zHz+SHop301gwTU~*;%M^b85!6qA9!E^uudSKL8t9EZS~sML_) z|4b8p6|T5q!nb(|TdRA6<9Ah{ z+5nn+JY=pM(@J#ch7NtmXRE;l_R5>4A7(y9h3G{#Y~fx4d45|PCY;45U@53@;1 z;~G<{lu)3~dY0utPrQy)=~{AlYR0TThnY$(xi^~!R!@^k_djr&wiAI62+1?P$!A`! zY@ha^JJ1S^91Gj(8=K?5n3qi(JtPl*d(d6`t)CL?UI~YlZvKd`9P-(GuAMyMI-w5b z@tdH$!(cxo)6G9w@07M2sXf;14g(x%u7Ua=Kfu z-niGoR^YG_uKF1{UG>U^W6f!$vd8b&+ShV|DQC~Wa6fvDZ!oeOLJOS><|i~M;G7*| zs~+#LQA8_>*IQuBRs;t((iz|49$aJ7>2Tc>3wBFhndEGa#L?=lKG!UNbakt8dU%$$ zv-mSfyD!pC$9uLguy_A>A&0Y0KlDC0r#=gy~~94Eb2!aKB-Jc$g8Zi zEWTb_a(`s$8v-0{#<^dHk1*{T}tbQ{!HSQBubG`cxcE`J?Q3xE3?IvkS zhGUy=Ae+0*Z|d|1@iUwK!B)RX28-h+Tiu7vc71}3-c}MQZSCy@+wE+uX=`JvbU)eQ zBYrEHvYWM6L(Y5EPGwEDY!_~~C_8^W2c+&z862;J%p1JHK?+PoFh7BFC_DM$Hk7~v zufLz%Er@8R;YO!pTbo=ROw2WR=WT)4Kopd)^A~?E&(uyD)yLbY%PRjWREkjbagH@? z>C!dlewp}y9cXfa2qZtA0dd$>#FMzruj}#Ku7Nl$jZL0ba>dvafmmeOrRcPwWykk) z0~bI;M1(CxC3EC5L%kgZu1;{{?UTz~&E03>j1yZs$!?t*a zu9uhrj9)Rs+_D*VUope8n&DAgbRes6AJ&;qdP99Yo-E7TlRY0v{R;E0s+hE;a$H4i9CeuzDPO(3F z6Uq#Qt=llMup-J;6V$ge`4F)2`P02d}>qw%2KnW}qYea3iNEP!*a~ht}{k*Ngjpn*&oieg>g* zU|ejvO(N0aujP&>URBVcU3>}hb~-awL7}!lE8K-#DBvVv+$NkVQ;X2&kl(Sq2VsL9 z`JoV0bm#5<;!s=p z=Fqus>6kiqktosN)H|o{7r`+$XAAKV3St+8-R9Q@f^Ja`Nkk6%BDr=dW41&56)>rj zjyk90c;<&U((YPAELq8IdfFBWIjbOaW5Y?&$GpM*EhEtlrBExom1-6SFbNXkSm_Ai ziPA~)1r_%u%r>$@LvWl@j9TRg4_c(Gj=Cx&5EY|A1bPsdUH%B8$ek(Jbz5AX)L(f` zHRINC>RU%;Rwylk)bXhl`ml6r0?XW3NpE(s@m#c|dZS;oq zURtICcNto3z3$zY*vGJUhS2vlcA^5p@m`144l6RP)J=zOPU4Ltp9jo=lBU=!1#=A; zPw7COhZp2pQNv%OzTPP|1s-PbQ|SDS`rFd#C!quQYw<1OgwDe^VP(~MP*r0nuY$%6I9wEG?0Q**Ia`)k^LYOB8n zC#%&rcKK_r)w)oX23DpUoqyFu*Kr;?b#u3t{j5gijDFDGgxQBLFAlex$)&HPONbpe znox7jTd~Aucb8Fekxf7dR)_H!{z1QThabL%K0A!7V(JRz?65J2NUK3pBk|T<@I3T( zx%(y_tIob@7nMx#t}c{qi~GYlY13Wqy{mJ}p4Yo~qpolU>}=L&=IDv;NRz96?`kDm z*7{v+HABCkJ*t669!E7=gsT)4!i#x?ob^|9m?|-dM?X&k_>@ZMB$<`T1O9$U>8kk7ZqKbWFMBE@* z6`Ueq5r{&Wf+uxhvK^R4_a6+=wMRI@M-34W3{-oh(`<+mn}WV-k56^w!ciE!c1Wvt z@7)tH%uGFywYXm+vS{=(?0w|?BXY#L{kTGUDmzq3#-h2ISJ8x+T8?m3@F7=Dr6O9e% zhYY(_bxs+48UGYn6Fl_Ow(uv&$->JZ1Y@Eh9p}cw4VKpq+qynG{;Hrs*<^A4D~P+1 z&#Iq|r;_0U%^yMOq}*dfmMci&a8X9ChEX-Xy*dO9_9pSGud-;J0Xy)&LHp|Nq{;x$ zdDU>N)*kJTohPt6J9OIs(slB?!u=kLYtfw&khF`$*r!P<3XbMFRLm0l(mZxVONavN(P~7~|#T)`sD_XAzt?Qtl zyqP*&SCObLeiN%IlMl{nO=i^Bg=2|2N}&TL2kol1C=1uF%os{#pD@DC0%RrEz*~r@ z7h%C#yF<#p93ZRbYt|_#)sp7Y-pE-!*U?QJHPR+~yOQ&cq5GfRYa-I%{x_7u0lNv;n-GItnznF^LND;p0z2RA_ighXvf%9mCk-g6{hT&)N2N;k zTDU?tj4?k^xyz=h>vsEs@1=+*gf<0pflL)|6Px;~?S8`^1PguN74(t&HV`!Oj*Z~x zj19W`2e2+}%Umq?5GHJc4b>z)vR2NT+~3fmkaWVU4e^`$bkm13-e|R7VjD&XGr0li zwj(igdy|gqyE(tdxHjRT`093$ShkYc9Ish2T%#?4Aa#Q|Hc30Ie(1TMY1Pi@Wx6`I zU*NCvjleqO8-L)?&EC(R%($Bk5QqjSAHH;icWhv&jgBoVBA-zFbEGT8>3{AxF=h?5 zh8qM-4y2#7Y_e{5oOzRK$Gh=$9OXat8pSiv3}@6oVY7iY$`!^ZOw4U%!c&z6UP9Zi7c z3~5Fm7hodZo7;A$OwR9QyRle}99Pf__nhkVTXy3`hzGx zgrP0H5%zqZEeT1$!}nB-TG2N5FyJV9alebg*v1Z}0yX%g!QHOXPg?1R9>9yDoK!4B zzaOQzBhz@Onf8B#-?f7`JldMcWV=t@pQ3O(QK^FUDuq*96s6hSVNy>Dk@u1ZX!aXO zd%15idb2E#c0zZcgwPGuzDppbjK0fjQb~@ zJx03LcBX64aPDioOMnW{dv2%{2-;x5!wMLj6Uy#f8+*I!$OqAMnkMCz$@jZuJB?_s$om^{6j0vXoNMdy-3Mj&R_x(~6OsGN?H!Gm!y(-4@-Oe^W|zMmHUZ7M z{25-5;r;pDo>&f^*}2QVk~iKV`ffi4Fs)FHCD^Ul;p3MAZoh~|Wd|Qism%VT*)Cs? z-T$RD0s`inFrH1u{xHg?&>yzL!s%_^Ho}DK%mm)fpSzPV(%M5|1LaAyFs6$WY&fE< zVh;(DL)|AOXw~iwatN5{jrexXoy#FeKViuROW(giqOU!iIDId<rrydxwCSnbcbUkE#WK379p|~Y{`gh+Ew6CpEh&vI^xsF zn8kf*Y&jVb!ryN66#n$7kVhsQ-jUhDf$;0rFzE*OYf=Zm{~fs_FH{8WK@qSUzyb|e zvf?%FJ2)(?Xx(kEyX~y6{2`A2D}7HA`k>^!{-oc!eQR^`w$07$CfI+-u{5OJ-sW*X z59%cCpHF?Hjlm!YyDs7{Ow|@;CTsR9v(FAUvC764CHgm_brC%7*7MPd?Yf~w!wz4w z)i*S=k?YsL%y(Hi4Z5rkHw`;4H`ws9UFxRr2N7@a>ruRH8@JCu#Gkr1)zRK{Z97U- z{@gD;kUDDAIejEU+-0w5Qn4Q2N@(~8qM8^_>p&0wviorkYOQh43xTLkc|+QwM1{8b z8>j@ohuH^x;0Q$xwswxg1cWrYf0p@oKTPU^gGNCoHo9+G;Ts&>*2u`;id}@?_H=vy zYf|ouh|(q1t=4|KUvU_((guE_!kp6Du)Rwfyjjfb-G61r-mk~mUG<8zhkzfj!&R%? zr`XNmWCwi84HX&Np>E9SjqdgC$2}}_o6>9Rc?U@QdFy!r;SeJ__Zy6$HXp0t{A2ww z&);>g^sCPux~bhaVfEoCXv6_l?HD`vBQQ@jo^PX1lYS1Hz%KJ2n7YBQ#M>t|rH$Lb z(qdhuE@Boo|M>AJ;u}io=4kyk&qF+7BKWgY6>s4#b%{R}1)2!TZmus0CGVaD$OM%^lfFL9t)QvU1gRh5G1bqV z#<^J~FSXjV##zZX4U*M`u^uUpMP4FGJ;)#TpW?CpYQ9V}j}`axCne-$msI<6sukAK!j+qjLHdEKf#e0!8|j%W zuS~qEzo9gsOOrcIp4Q}P(I~Ac(}irZ_S@r$Mz1zeMibpi`&GQXsR@&{8$L5nQe%_( zN$M-+`NIeFnO4M4-x`lTaJA8|z6}2$ql9G`+<&f-ja=V5$S;YX%(s$(ok1%krN2s< zKhArX75y>DH(w28W2|K4GS<^GbPnKtO0RGJ7JpI?QY0q5>uO^eV`;3HVyZq~1T-Yq z{z)=+x|_1>&+Cu4t3t4Qahwr2Bid%Vs7;BdGGZt9y1D* z*HYrsikspUUVpU}nm8xeveme2=^ed6LzqmzCLUt(YC{;3#DR~}=T*EXCS<(`(3*eN zuqJqAvSv)?M33w#`lWuGKOD5;@mB8mq!NgGZ#?~zSDU`p1b`R9_JGp_41pjOx`pyY zAg)xQpJ9gR$7qsmqD`d$s}f*NinB)4^P*n0psNvdM5ll=K;u*$e=2^SKN-=nMiN{j zV7>UidLV|l=V}le&fi0KA<1y=F$OVrid!na%wy_0USmql#e>aUZ7`Gn#A1AaE(`ou z9=KX>i3P07NTip+%*IsSttY~?PPRkc`#WX8_I+6@S|t)-|hTw&sED1Ak|ZcZw^v@tX_ zyL{bc0#IH ztHEb-EchfD%jH;jkt`_5;LX5M-}FS zb?|!#<}PK;GW`1h`6)X81T(%EkZx+O4v2^n+(Lsv9F!6VRs4jYF+lzYXmR%QFE9G? zG+#TuaO(6aeW!SC`c6LN+`6xAUt338S4Y?0PW~U4o}y;z)Z)^@?A+Pt%#EiePhH@< zs|WU-x-_-0#D(fpe4X{w$Go~zJap}w%&T85RWCJkV!=91t>*=>x+-}AD9Qk77n?wl_JE0IS zHIj`Z^wC}1b@k#it^sBa50L>TPR_RM2>&WG=>hg8h`gN_O2DNUy9)TXEqtES88`l=0rvvP|6Sa8VRGu+ z?A)|??*B1M!g}YY=UNw+F6m>r|3|*m=ilA+mWP5L{~@YqOQA2%&(EFB*`L|DrRbL7 ziCn((`dkp1T$M<$A;H%>oPQO&eb>&)T_*(brOS9+sR5@S3J~eczH^};ATz;l?B0oBg1Yaq+Hrc7=Bc2i%u{MY< z!+vRQarW%o^qHI%@$VvEkl#~f@t!n5m0*w+flpUuYXMs`QNIy4v=2Y8L8HL8AS?Z>h_txRQ57_FD#q zMh1)j2IXfiUOF^$@s9niix*qZbRJm73scnarR=5YyIT2F_DeCxi~GKqUCu0COjzdZ z*)#CivBfL@6BEr}oSwS?UnTdGQ&ZvL;_NgxQ!}lXzn6VTCV;|4ti}0hDyFAq7x|8M zD__6n6Ww!5p{F=t3LZZ{JE@iw&Rm+a4{o_DSKe+ z>BYrpc(ica*!Wn|WN$}ky0+Q{J zbsg64U@!fmeBVIdF$#gL&>7#ycVoptO2-C^C;B=%;%jGADv4mFQq(&!cA{rsT*HnQ zZ?z%21ZFWh!&l&0ed*lf+?n&!3js<)Z-JJ@$Of3wPa_PD3>Ak9*5C$#Q;Y_N$BV0H!1Hc~1S2YYTSO$-l!*s)^%*l=Mi z>dp7xQjE^hTsU1?n2yFkR1fRV4;>o@i(`Y)*uX8rhX3BqK!@JW&iJ`2zV3~$`{L{V z_pO?Fx)G&_2iEh!GEDtJYF0g2hNefiCb2f2nV@XQ&wUjF0F0qr$-GNFh2gSRB4(ygxb)>59e=3?#~H zzOI0O;jMJ%9nCLk+KeKe_iaLgx*TdT>;@ z08a*gXW%_8r9%=C6=3@OXbc3zK(U!T7cW4Sl?jhjeAOkcN%|%@$?>H3-Y)`l<8N zll(%!k{D-Xa1aKIgXh@Kv?&ASvcks(QrPG%dX+ZpOdEkS~s_&YaUeIq$Ts%L$G#zj+ zF-cHAKB^V;kN4!qqmlmG#zzN+x*)4GF;*fhEq`occs$})RhAA)NsAI4F6WGOZ&X4K(RA!CK&FBD#_vwUB-fR>hWPLl&bx2_V015gfbzvC)&o;h|#& zWpA)P*Bh@Slv_r_==6orKpiu=NsE1DV(gE4`$mi9$Lq^?2ZI!KjLLLenoE335vTJ& zn7iNT)lo7U;vEN(1?S?pk>cn8i`Q*ez`Klxk;ClcKu<3k$Bd+O2`VER92*)vAuqwW z_=Q3{kv|%=cp=|6WaCPL6T5b1b|J!jn!-US!EF2_Ni4jj-ud|;CZ*1?@lx-^;88&@ zW!4e(50CVYAL}VEdT%tbIC*xuZ}QUlrN9@a4Uz?FG5dpNHy((!cpj5iHWvwsO`h_d zL67Gm$T{mVs0d0<4AGnEBWMp;ZgR;@JDGY0p_y5wPAGq?$EA;4wi z;u6RUfnxCI48LT9=-x3oH-+^JhDH7?vL5q40uaUo++|E`@-B~eU~D9)jD3Om21n$0 z271IsFpm*5MPo`gNB}{@^z0qeXUgn-z#J)SM;tLngix-!fnNcdn=+!K)NJUU&SEMd20IZ5z`=`^dLPQ$>JAtO+&M6JX8JB^ zBe4c(zq|k*dN4Xc#T*PmRx0uPTGI=-ad_*7zvV(BbI}W+L2@C@W$5G$;U>UCvC15> zpZu{O1466LE-k`!h^RS906ZoSKG>6kCc&n1g8mE&FkcQbSlZY)vvp{7c+4k({CHtV zj&PZ*UHeO&%O93GYC;^|{5WnxG=yumaQD#U9Li6>mlt%OIj%--W8vuw7nklXv%zJ% zesOYP@{PMQiLR zoo0bi|K*TXvsxTmyb@}HqrQP#CPsV42Z$5;$BMn?d`LGhiRp}n(Lf%VO@!GDnyg4! zA1JCaM`w0!X5PZV(Ksv|?dXgK#)rqkq`^Pyn~*&Ko_&E8BtV5Y&??}4hv#5x3fLOF z;o%@wh1k**I)kMtU}?riNAiTA@(-ilON+~_-9R7K*A!mxU**S-PK;PsI+O=}!THCl z=vgB5aQf2H^kN*cQmI&QnG{eGI2%XOB4r9fq#elE5oD{k2PwY=jnOx765114!PlXM zxixU7R*M};uo=i@=nPdI(E>5@nY-eaT^b>1nL=!i3Ya5_OWY#HMQn=-*dh&71atP= zV~ZE3r_UtZgUL4K&>`){5<*K<>G&8v{ITO5Q3=Hx7vEr1+8b6Tg4r!oE8436ctO&`)C;|@rm$?1rMg$zjcBg>d$xn<5z<@g( zF)){yJ+XN(dB*1!WSd7KEapco@TP0xp__RwCdm--OW_tg8r!QHk$}-JKPqt!@iI3F zy_T*7^-5KD0tG&i2sn|IMd)Zz6yKc-lNVo{flm_d|Cf`jS7cacW)`LiK1q&+1n9pz zV|spR{(H%rCb|q{E!RV((+lKu5(QBf>Gb4c$b1%K0V*Oug%PDv z5*j3~Vu*udPcg4Nijmzs`=B3{7x;3OW->L$6LKc-#W-v##$i)24x5Uxoho9d zl7y?WbaBo@8Qh?8ZYX`>k08=XFZV4<@t6c&U^ad361{C%N6!yjm%s77;P}m!1FK^(tGVwew z2Qag;z9cP`fsb=yV8E=Z<%2a_fu-EZFN$LJ2bIl_P-%hB%xT8~D~^^I2>O#%L4opZ z*X7&G*n$-024p(Q`N`Ov8m7z-i|#x=dH&LLG};eK4HT3$wwTb6frlk1^8qLMfRlWj z4hT5O$H{;=7Z7lgk23)`L`(A|8cV0|mX8$zMcJ1mcL_eO$nBI)!|q8Eo7Lil21w1C znA?a;I53RW7>Z_Ql*3Wdr6U@ipBtK7e3j)F6VD$~E1=MBiSl#$(b>?PEd?SBq` zj$KWX1?#T%~3YWMXFXrn@= zoSYPzTC8*eAKoZG8x*6E;kkrIajVWbTVRko;h=2TwK* z{7h|FM4Tinqlu9b{HCA}LbMUPPfRU;1rH`Dqx`6lDsYX&J#jqJ6UQSxaqg=JuR4yd zmnEE*;j$+VO?t2fh4I1RvLTGQPo5)mwd{tru*~sC!=w8QN|_Y_GBz+VB7bZ+1f3S> zhv0!-#d-qa{w6Y?`U?eG`mRhOZo>v8XRWgGJlp;Z`qq6^{su_ zi})Q=v+R}2{bg5n?08T%g%Me$<6#HTJexj6M`_gjC4u+gpKTe#~MvMqNs@_4QI8JBS z47Mo=Irt&$1>1GdDEvk?3ikhUE;bAw|8zJO+?CHCvN+EAjn4Ynu zdr~tzG*C+JzmGiezy0Iz{OWeQ{T_OIVfv2Qsp)o9ZE>t;tbJ_$(gKf!6Y-CrpDmr6 zCbB7&j*~3qSHq*TY$n3Lw3vF8h4Z7uTS_CN$Ht5K@lyVlJPep0I}weXAp3*QUc{}Q zF6mdkkYgU{8-pR^UkNWw&79Tv17y-j z1CC6v5jS+aj|8Cpc7~rQ*Uz&D-?zlPFsjzV0fVu8Z^*CZ*}r380ECy~*|;m@2Y`D( zKD0)|GqQbT5v>FZvQ5-Omac$4#H%We3=NFsR2IWCS3l}Ngk$nK28p^REG zs7jLy3zK*2R0YXpa5Rt~Kxs@+Ybkijft5m*IHBnV#+X)PpOBkxaeis!7#lhHsAoV~ z_^`^*?}{mG;TmFShz&QcBV5KTNC1b1LTVWO|2=z|IIvAI%(;d@3PQU+cuAc81aS@#1m<8;ze|p!_3!4~EEMq-Ph?wb4#*H~6ghIrQ z8l^{ndOJ=GL_=^nGf%y0WNBe=_5zYC#)CtQ7bVFrB)AAAu2PQdB?)H15FUhfZpmwe z8y$f$$|ro9@Ycu>0|pKYocIE9iMJD8IF-zYobgftYL`q;4vmcr4&W0Qf&nhb;|o#n zqV)_O$0Lhn?c%~6C3bI-tTVHB%$}KEuuVn`|M-b~f5$O0fs8vgm@g11=XK8^l<`XO#M=FW3%2Q1WRKaEB)$lzSitNqxe)5d17!Rguaq#;jmkVVjU90Pb@1hTLwvY7PhMQ?TW zaQ=n?Fs87>arVnQ2Nkt|m%_ktI)nxEMWYAy(VV7%8irhuYWi1^GlO?g%WPem?Svi8 z$@dKR6=Do?(z&!Se<7T%fq4)FBggol0O%W}M^7{aI!|Cf4Ys|Mi+ckhNgKVobjKtC zq?kESvNNXSP;tndA0`(qIE`X!%a7oK*ii?v!`A=YJyEe2EZX{u`Fxj-k>M2?j6H+n zgodMr(J_t>ji9c&B3kL35wHN<_((a_gjk8|vv+TF%gA_wv2y7?(s@Uf+hd3@R>Btq zF`dGcj?MJkGQJn)3D-WZ;{+)Iq09-R0j#*E3rQb4HXBH6qdUwY3w!Qg?1r@}&1+ACCN`^3#QhS*pD@L-HKhEg0E zNN5!^3^*5&;)9F{0XYFHHri_p0n=!te9y?S9?q`~Aj2jgtb534#Emh5twdNcJc5F- zJe?8j868k(h$-+2xJ(GKof?3xZVQYTi;QHDnl6!BVy;DA<}v0HN1$N18^w)BjRe)3 zh*UIaXqNDs>N+mFJ`@t(Ha#6_+pCldUMRy;aN8)MOS}l+9V0x*Tgn=*Mn`m54992S z)o=r|s$y@r?0cbl6!@Wv)P)*eA1(*WE zFNUePK_B%mV^g|l6i9{RGS(*`J%3`X&-fADEVe|zrA<5cvxN>BC&smp zJlHiLS|@z4AIZW>>9Fkny{1pew1U_$kSTn?i+MPVVzie|10+Nr>p4ndX&HY93t}ju zYOm_|#Wq4T6=?At!pZNuUKCfU{8e_$Ma7N?C)x zAjq@=6GO*_tP?BgwDolMnYO(+y)b+6-1Gvete|)mwlhPqAbZ9_#m~n2u@EDnQ0xSX zNE07qEUawt7Li8)iF1RrgHje8AT?_e!Pq4C3?5o@cI;?`&fUj79)L)|P%t`l5By8G zBy;ep5~xkoERF{@zP*%)VGW>SXpL7KEcI>sfE(~!t7azJG<5LeFQF> zM`pSV5nX*SCed87YT8_0c2X!R#kl1z(JHn$VZWB zMJ=aFO32G;T~ex*FkPCNa;$ z)R#aBKRojQTA}{(wUI4DB15RbOa`N!R&pSJ$N{@ zV&VbW0&Ip1QGyVTk}gd0$_Vk|{230P!}P~b;K<1T>C_VKDwQ{O!l;~}o-A5VPvOXj zKtYNbH+CJCi~DkOrgS!^ZOc3(`Yh87%bOk$w4>;OtJEJfvdg)Hl})$-LRQQSqdNB< zW!DH(AeG9hS-(UOC^hi$!2(!74MfXataJC2F3xi}l-E$^Nb!rAJ6OIhXkE0dscO!Q zV8a-$FMo8X|8`ur|Bt-$bk_ei4|snvR54_G+0WC4TGOjlLE6%pn>>Q)s~ zkE?rc^+RswPCdJesn^tFx?2`zuts787>gJj#fG&c&`QLzz)~z?IU&gqi-!R#kjRc$ zB#s~un=Bj{BS5SLOn(3G+xwh-&b{4|S~GyN`pon_wI63czWu%Sx4*r&vq1VHEyDO{ zAtVL0Iwm_wJo}|bVAVK`dKTYwRAx%r?eDBGfq}XKzD7b#om-sEhbYHcj9~Z=xRYvt zI^Vn0=Z`{Xl)Xe-F}y1gJAL@jOI-~tL}MpwokBwiMT#JTn!;bXG6A$yL8Yy73sT3C zF1z>yL}k-8^a4u_j<8!}5zx!@*agsf5%t43j=;dcM2P557x7XK80OkyPuS02v~gUz zD}=Y;#Z5piUI?;Z^BUn5NQ>U+rCwx$CAAL5re-OPX^s;2SDt_@SN4p;CnXY1Sg<76 zzSzAeDv_dy{^{{zeG$p|Q+=7h2xlton7R^}5_aYM&w{04UCv`qi*e7PeF+bx+ESbY z+Wu50LF{Z&zjWFV$}`cPNo$o+Wc@Ou5_q%=ebCJ^LYXM)3Hi9-m0Ar+Bq|(?SkjpB zt8fpWcp3F%?Z#s@{nYh?dm076mo8r%tbnqrcnDD?GceP$a1<@esTKJ__`e9v;yj;U(iot}&QtE?#CE{%$=6b*ZPrK$ft5_@5 z$Xl#EDmYQT@<}B0tlf2;B0_e;SR>r1?}QW#P+*D#2B-ptGa;YQG|uqoltblID@=T7 zo%9pUD7%*zK;D4M#=%LnsfO^;Cpjw5(K=@ukU#!zYz<%wKwV z*39$S1(@uF&(#?@j7loX_zHa5Mnsf=ViJU+l1@8#QFc|DO|$`=%LSk4`^@>I&l1Cg zg+>h!kgy;fJ@P=Uh@Lnb1y{pNizW|#9!)3BI-4nMu!HK2H>6Q8tsRey63w)N%xy$^ zZCGU8Kyb$Ud1mN$&4KTrRVHje%Or&1n6?D~{-oilT%NE|0z6E_(K+#=9yOP_2 zG3P0pc>6>unmS;qS|3UJ;!LpkQox3V8}^|6N+Wlyw1x$$VtoZIjI3up=UJaJF}yZq zw027@V93F$ZnVUl(cYSVh$%_3=pCkvw$P}sJofYs6Ghe+J$%jt7!oB;r%fV?XZ7AL z6>7S}+P|AW&e`m-&4|xpfS1NdF4t15(I=sImy3X+pu${^OD{bz{l>Zv{Q2Gh0;kqY zF2e{^zucx}QUF7(c>fz49SdU1CjWu6h9vq5%+6`BAH#c=Qk^(8ld~bS5wrfX;^^<# zDLhO)A^?UJ#$fC@8UM($o{2Geo^vqjpVwFpRXao_D-E4=4>EOy!8`6E4eeOZ)XcqL+t1z&e{dOvZ=^D)201iJ;PU z4q>9YF4h}LSM6s(AcKbex@l;_{$^(uGgl{IW7neB(lpx4&?cF`PZoVVc|K!x zOD5&815|674Xs*CzhjE|r*VfVo7M^Oq~@siw9JBQ>^6(^Uzbl*f=C^P6lYwWN491%w<@J z7yt^nc|(}uMr0+KxRqHR!awQaR(kVdFp9ek%?AcBiI7i0OzUP{LV);kNU)pX_233v z3a)U2uxzr{ANr*;0#oqDOu@_fA|<)VkP#-r?R2paak{W34VYtR%nB0im<8BR7hpeK zfci?%wW(s9^w*XP>Cd(0Xwz)isKHC+($jVV*G zM`{eh>_Fy0@M$VAWEX|bpik%euwa5)cwgv#W-dQqXfaqP3ZiUi2g8INc{kn zGX*5i6f}PZnx~{5JqZvR9cV^)+7JwY-l|wcI)#K(>ec}rZxw(P) zt`I|l#>@-KVhd*cAr!#aXX7WjmiZ`BqTw5P$|k#_Yb0Uq@-?q8Yb@4!wP@A_-E5(+ z#H;iXQz7wGwAiqcZF-Y&2ucmAi}-H97&KZVa-Y49Gn*HF$?E8>asWLsRoTNP(nCkt3pVAiy!G853Gs1b1kpqUIdMN6|iW5$Y_HOmkxz7WTj zg%;*DUagZt1!7z?$@?2y>bAe|iB^*IkrQXER5Ju|Q)JLg6O)Y_prYpBDSYIk<5;JP zE6eJdS^`zX_e79%(v^M516z*cs@o|H`nH}(8Q8=6jm~AZr}d|6vkKyZp~96AJT3cX z9eoOi0Cv;hi`-xC@8@~K$5`2>IkaL13k4g-`oY=L2Wo9^FVEh&q#Yd#7tlPlA3xTF zrK*bp7As^yw`N$Ob!)k$uI z0Cq!xIza|^&;-ZXRlhh{i7Vq8W^|b!WBGybg%ToZQNbjKfUx5%<`_EeqFwQme)r-G zdm^iSjKkUzUW01A6sP7F_!KPl4&?O|s8m8EBZI~H$L1F<&i89L)8R)Ro7R|RjVu`m zA?P4iijA3-|E#7fHNFaC_S-LUx74_O(A&(YTHZFG|ZWb&`PCAifMZA~ch z;zH-Kfa9eh2|{LWvZigpY(jU|(gJI`(+M)5Xxrox8;m4N0S6?=Or0&!102^tDVmA| zUS_*hh8x;?N0XfNaN7YA5eLme}O&0|B4JCp2v=q8P3AS=QaPljgy zA`)&gI`t;mBZ8G6=b0<)C@_Ey`*h<+#)a}0g$!!Gon0r0CpD=X!;2I@8Bh@lc+6^9 z9=e(Vfb(pJif~EMR49VPp5w4DS4r|*Gc%mp)MrxAAFn53N3BsyOF}C4t1-I>^Y(oX zu{M1GBU_w>YtEPP#Q0mQmeRe;WbGeNCBEe}Z<2VTSXUJs%33X(d3ArGh1vioEaXOP z=v;Rya7V+CyoR|+1flhPdUph z4~7OwyD96i)g0Ra0!E%i3GCn8?lc^BhrZETX4 zW{?j$fg#4u%y*IA_>PNvneG!)l8#Jw9?MD6PnjE%sc7Tw5{s;P4Y|;FB(360L55 zy#le1ux$9S<7ioqq3P=IKO4gVS(R&xP*@uxyRb0ZqoH}Roo)?rY*5w=r`&YlAi|uy z)ZnDCgvSkVF~j8!nCU!@MUuRNFo46gro46CZlh4LBebV#b91!;b;%_tYlV~H7>@{{ z87$RP%=TE!(%B@UQuaGBVU8ILusBeLbL#p%z?SItv08WsNYb3CU?^HBzUh*ad4b+- z(I$4+i_m5|fw06_rV(#!M~tj@ILV;L_7$Dm=sF?0t#*oOWu8$puA(3Lv@)Ndm8r=& z%LS><)kcNUkaTN7uGOhA>`3#;Ivl6Ui=z%u?F7gA0mQrmF*#He`AQBlL;gj`z0IOF za+BSkm(a5+Dr0~hOu?B>{&}G(sbrggYYg*% zTk${6vSb6e1ahGXsLz5jJC4j85v$}JfY?V#9Am%TX&oFAqd8iwMz75ll1B#Ygv^z8}ykhaWaMOrs4NUzy1WSB6X2 z6nr@<2kpKDuy{^r1fc2l)$xyss;{DLTW>n0$wEoJ=%P;*BW|3g){gq?eA!}_vy@>J z9*{*kR%f!8u!JO`BoUm048RQgE0bQzuqjTpJ4s=T#7v9Hag;J~k8%V?K3_A^*;@LR zM3h)RquBr{pARLdoCr+UEI6ldEze*GI-i(eaq!PBCe{G{T6nZ(&G7PKgB|!oV z&K~k1sSJCGMY11jw!UyFZ$)Hbj_KuTO@Zpbv#R)27y{F%AXZ8OJsBg&+E}kq!7R>c zc^is)WVo|KjMi@K7Q)`BG65m8%cxQ2WdzpgTHt^MEN?8F1p<`~>vllWA-(+)={b#t z<89-Nt3u%bpgTZwkzu<1Cn_@$FEuo=(CWz8ILpimz{2st@iPrpY2IqRSGL4pJ)Xm+ zfG_IqOcMmW*3Giz{uFCd6_lx zl33J;!1Q@&go-)T$G}kAR%~LeGsU??Ntv-3Lrt`@HIHS4`l@fC#Vqay&aHiDV0rJ zB(Sj7)y@u#z^pT2qp+1)4lyGQ`u8&A?l;wG>&yk_FLP13Bxvd9Z5>gys4y)?s|NW= zHEN*%7D`FCN@)`x+7jY?3)PhsSk(8)d|)dsa#2HGXOLIjeHSkQz9u;#LAYk(EB21$hQnyY;V~?8KG6Ikqf}I zD!c}pAixVmwb?mOWPcNW!pl0XAP&`-d80Jyo*~BKpkYIx;^`r-Z)%Z^QvM~&(+Sg&ie?dXY#+!WnL5QrN@BPf`qIJ-T*~#(17dh1E;=ChrSs; zhb-(Xa8IA6_j_KPP0QAl4NSRX0jx5b2*6LFsVWQ`DTHbq%f>@NgspPYG{hvPpY}S7 z-QL>~Xr)*RVPZUQg$dUta#eE$!jT+FQw7=v{qqC zpv^QoowlKrs(Pa-=!aTVS*7(N8$=u~$6`e0pZ1b7>YN^7*1iM%>YgERsfRYUHeibZ zB5J+{+fp1z`LQ1T-Sz$J;ebZYt9r@%u(3nqCug}F!0yCo!MJr&{7e#ulkJ$TKQlFJ z_UlOso^2BhUYZ%V>oHTHwA$TB@|F^sw@P5kbKaKH7p-bSyTJ(`i+IJ#x3|k$Kzm#= zLVH8pRo3Fh78O^NiTGmiZ*qoH3oqax+ewpziN#`0@r}_bHto7*$f%EYs$r1~5YF~H zmu5n9xH!UEU?oeNthHw0apM&@VOklph7<)sD5q6L(k9A2+3!(yk&CEvm9nU1Trh8S zE+rY8bG62VmDjE1A~Z<{6cg6&qHN=~l_ubj+F!hIv9Ci^ldoyUSid$`jyYZFk#$m_ zDXO3)rz$m=x-5fElC9gN_yJg)QjIS?N$fodO~~I$8_fNU52J-~nalB$-VKbZpi=2@ z6O7YTK?K2K16RLzQMhLz<8dq4PRrEjR>69{f&yv+R;!+QlsMheP7U%&6Uf;d+>nxW zvRctx>14>RaZb*{-DmHRL(sV1=@1cmQ>VBfNYx%4cu{=AC|A1}iaC?y3Q=d1C}{T# z2Hds|2G4t6Dp|mrY2sH@)W%1rZvT<6q6}W?qZO<(I*Jfa>ntTy_}H0BxwPfkbUpUZ0LWOq%&5*!B561V(qg(nGXKc%&Bh0$BC}u)r3K7P4!jQ}J zr*#UO@;cLRN(pK6DeP>8GdYlk_XzOjJu2Zqkx)U7A|aIq;&Y%`$VD$067!X#BHe^T8NK*q5GB)2dxp@FN_&e@PTM=Pp!J3zZ`0iG}N;sKx zsFZLjNuX85;H9HlN=O-QDWTGjqA1*XP0~v9OsX?cQq}{|0Q;DzX4rgJ02o09v8F<* z+nk=6o0ERgoLNY68dwqW#kUORxeB3ce5IN2Th16_Q{WbPQ^*#vDOjoeOrOeyS+LQh zY=_cq*xJwx?EiC4k83Zp%2`;frggCX@U8<^Y2;<7s`|4P#5Q(!aWR#s^kJ+*c7j?( zKrp{?u2JrdbhQdSc)rMGIIGpQtnzmv#i8F#hx};^0m{Vfh}{bsrg~|7oQ|s_?6K9c z^w`Q+QupmgY%oJg;aX`Q!Yo`@GRtMDZIWwcjSYR!dT%$9l@R*02_2W*HaSRuECRx0 zjWNIY1Wi2AC1$#=P9*8#*=0@$?8SzvAofAk?Nf%5U?haCxwcFpNsSCZwL6qZBW@4T z!3-%x13pySRP=*d&s0#l)Q=&sKv@Z2hh&*h_c3$!_7Bt>;HETqbMz&Tg#Q(09?NFiQI zNYSp8kZKDg6go@6BEuA-)E6X3-|RmH_&`|c{MyFTXm_Jgb|5`vqv4a3hlZ$B!3a^O zlc5SxY~UCupKY&$aYHJ_RyUY$NVV+EF7g2(4WW-h3OdtD%B)!P@u^uYIu_siOq@w- zm^IxJ!-a8f{Z7Ab%$ypWI-JcLR2lsup)&eKLfQq;pUEE-(XEMrZJXI5{Zbw3Txw-& zn;dQ&t}-aPW&~cA2bAar5KavRW^Vf~_XjnrG-c-#X>ApX@!}8O7ufNnG99g&lyd}8Tpfq0m*pApprMFTG&Z_300uz>6EKDDd)ge?(yN? z!lM5GsF*8M7)g;3RWjX(SbR&XPnRtQWjmItt!(;$(&5h%&oC zALoU#*n$G8bHkE3GXdnJs|akCsaW7nRmxK zd6v0^rX^BqJ&_|kbO2k4xQ%(1VQ-i;oKcMRb4F1HT-Ai_jSS*hAP`CVWT#tWS%(-Y zEn=?DD<^4q=t2SvFtTc`CJNoK#IJ)6axVFh`iqIdFyRxvIiGyfUYMK$*|j2)#M1DA z8H5ZPOzDv*LYe`ni&YKK%%EX3280(Qj$cc=qEa=8Zk5uEHqZeAxufjm6^aF)}K;>Yd4UqEFc1g z&~OfYauB>lj|=dYz$ew#Cm$*Jj9J8ll)hyRDi3R*_`zu;2kWGAy_D~k2|j&Le|+Jw zDzrf&mjp#8h(eVGA+@w$ok6E`qH%zsRmQ;$90Tj3G*>g%!ETijQgSOLR61A`)nb}& zN9JyE;naS{fxDb@xkHp+i{Z!hb0R(_SI&3c+n6I;w!^k;)c9c3#9-9PBx=_S zTS*IxacOBWE-fy`o%~Y(3Ehrh(b-#BG2##x= zG|91gxU|VYBrzdV8nwK%{REjRpBAy398F^DKw2be!<6y651X7sGj>}F={lXyUYrD~ z5J!9H#o63?;g&R52&yeh=^Hz`;oQ%p<~lR;+S!0gh~(R*`KJwhi=Q5M{4_h*YnX!T zBr9^7Gt0~Z8;M!9Qq8)kWw2h!i%i8oW!KrYIT3@CX6!|y72;F9PI2GSwtH@=DEg-w z?U#)F?NxBVK7Vtu7QbigSJw+RJLl~8eBQxz-747L+UA6`QcK5}BCr*4>{MoSA6jMk zIF13fKiCD$L}R)8Tvb8A@=1z)A3NtIy8l`=_SDe4+*dWEgtJ3q(Lfi>$w^S`tSxcn zI&~Y^+r&)Dyt8n4uzPsm&>K=R7%?pNv<-|EFtg3~Ryf8|#}S=5Vt-{Tn|tPFss=Ri zEnPW)33b`qNrJ8h#Ldgl0CSKo^V4tuNX~pP%ad+kaS^iPY!>+0dC2~0>`H;}2oBx# zUTQH5Z$4@u$v}^}tqfO0?k_5R5(b*{8rf`TjS|t&HmIe5;KsJ~+KQm;!D5)9spiUv zdEpc|q)NzSSZoD9LJ1sPoMJ+Vt&CTQ#mR7hHl@FCHREu?CDG6O1uJKf&$D(MN2x;Z z9w13$$H#`Dbc{VcH1Am(!1*Pd{bl3FERVcg32hlRwg2#H(qf}-^r);Z>$ zrMe=iRe%-<5OfZsnf7HY^rbRXA+|D9L;D>|sMH$rR)#9XmSGf2s31|uTOs=pd#>E` z5PQB98%Lzvw-{UQTZ}FDBF2_`F@9a-_A>H=h>WKm9-LgH)$L!< zNpj(sz?3)~234X9vE|+dh*$7B#+G3aW6LmzvE`8r{i?Jf#+KUmn=Wj7LwjSpwz9&lobh_P{c9WR$XThzQV~HMdto+F2s52tAq_*ELSSN3 zDA=svUVvBy_hRhOaj)QB%v*+7j4eYf#txJDQnpi!3{a@FEXI~w7Guk8h_U51#8_;R z3*0u5RylTZC=rC%a+NV}8GT}Gxyl$@9{dxjIDqulu&MO z%v(Y1khg-^A-3GNSVFmPG4{Of+1bJE7^`av|1dOT=XEY{n2l^~mlfYKB%=Ox zE;uU&GtBM_bA&EH<0{R~!?nU#aZ785*HWoFYH@4>9GE?`;5#&SKH)q|yBpRe^$gfB zn!*cj(u=<7B!cHe`~&l*+svrmDVsmM31(hN8Y&Bj5Op|KurAKHpdx5=>=y-rztIo) zMLpmbS;#NzaQw1ugI|_R`IQN(qsjchK&3-r(>AqDsN?V%gt&}5)7{LlCSl)jA`e0Hf z8Z&eo-e6CBk8l_ZGjh3A%X==c707<=x*?4l#CFVB=Qk5O^$ZryNg4Q`3X;wXN|stH z3&k&5E$O?&XFFIw3ZWSoSnRM-a8xWR1RBJ5Sq8+s%v{V;E7Sw`wX8zRiVB3U(3q`56G8T*_l_^t*Eh_^tZ&@dcv6UeS zB~+wSh^-7%h%M`6vD~sw7GujgS&Xgdo1xrt-=cY_+_xB8?pus4_btYj`xax%eT%W> zUc}gPFJkPl89N(E22sdG^)1XG-ua4_7XVeol#sXF`Ixud`50U7e2g91`AQo?H!E$3 zvE??z*m4_UY`G0Fw%mrXU;-~AL5wXUL5wZ8A;y;55M#@2h_S=lP)357w~Pcamg&RV zfh|vz$hFdq32q1tOB&8@_REZ+(vAv+RoYXgp3soW;Kf+B-VAWG=45@*FI3Ohk%EDK zDCjCi#8|SMo66k?3RtD{A+|DxA+|DxA-2+x5L<=PF#B;-0xK{JB@83kb`z~dYP~EQ zykyznCCdgcSvGjdvcap|f(p#5lv3`Rv}tK}z7C0yQ-PsM``at@`n)=HB=Vpm@r#bc zZ)NDcSCwW22vk}VW6O<-u@&kF<(7Lpc6O-2BE(ikH^f$I3$c~a4Y8FrgxKM2s1k^` ztTN`IgbLk;*kPE!+_kb4w>c`IEG3r`iI3bB+re zZ^L3MRfoKl5eTuB5eTsrqzkc?5eTsrqzkbXqzkbXqzkdbkj`!VGVu>`>e2*%2mq=h z;?-0sKg13NOBDq}Ug@H7`kh~Y4*#xg7(nNFi&VZ;Sdf1{C(G|owskTIX7Fr+fFJIg5ua2#6tnY9=^Y-c{HjYq1qczoU zb~yUJKgU_RT7OOwZ2lCEDYj{2lI9=b&}a$EJ4@X9EEs4~9x5EaRfY3xatVi!Dle0t zO5?n^<->ymoHF+00+Q5>(|q~k!c{MJ&cEN<*xcOM&$>7Fdm9{zIvsj`V|RbAJY5$M z+A~}$#0^9J{yc}B_VM;;?`>d=Ik=f!zqW=UmXx*arR7bqaqr2@YuH>{4fddwKG&TLO`h!cBDCmf&{mq4fewY{g-R>z7zb1GDGYMiXOK$GpP{Tz83Zn!g3kJ(C6 z5X(@=wP_sCq!YWHU`k`a#T1L}Sfpb-%{bgz%gNEMe2|-_qg=K0K!m!=$bB|7ENK-E z@6Jp&2Y0oIqJcB>oI9TFMofS=3{p_?b)a-k#ts97&nTB=?`7-PRyV(lQ89dDL>S!V z!}V+f_thI%_ZaytZbe(#*a|6fLCdz+uJ^YNSvkp8_cl0dnCqcp-W%(%v*j6`=CZ!D zvNrEF+=Iiuv7gno-Ggf!3An$~-#A#eKh9-4`%9Z%9C)?1JF&X=RMwNFt~sgQcbwP7 z(dnG9-k<3%Fl@Phi3ZOZDSaTAW zbZ1Cc3cz&_mm8Z)`}=sg0elWjq$_Ky9FH^DPO8b9n(@s+UxUCQjD2->pD$^qI0>Z` zjq}N#wSH}z^BD6XBmZj59xHVWAY}Ouf& z0~BJHmZ_odG?gtqwY0G*5tkRK`oY?Kq#Qw(p|Q#B)!iLhqrrAc^VK-P(N0k+AOp5U z#N*gL2#gztbi0=he~fM4)|zPXNuK`>nEw9W$_XJLtfgpp8@KqKm7UGJ-vK~wmw(45 zOIGXsZN}g6-dIOitSLq;$H^4LZqbhY5Wr3juf)c?=wg{|q;Tn7Zciq#s4sM@1)AaE#*Yg8r%Pz*#&RR7DDs^5^e_b_S-`QI=vMai0RnxzNtzCWvF|W-kb}-%{C9T*6 zb4F0sTd7b6g8gd@zi(%1EVM5p5E@po*T%|kfA2=#6&tEs^(2-DNYOcc1YyNbC>*Lv zU|?~DbdBK7Hdb#;Xn>Y>ZIHDgMhb-#2a?JqXWO$WQpHL!pY}EIf~K*-yg3G6+7olG z?Cjp`Z|$s#ljfPclUYO^n=3dpRzU<%s01(eo!VL7eXbE}8igC`YJ_R~R*IUqdow2} z>Q2z#crf};-XL_y9r;WNVh4LWo8b79ha7;+ad%JcJb^ojM0`xl`lbmz$uY;AXeq}OZGdBHb;Mp0aW6G)LUH%LT_V#r_Z-LE7|J$p+RU>*R5`sPTR8y$ZB6B z6|^~twv}aXLD6u=BZE8;s6jy4-`<1pVa%|1%~t5VJBMqBYxH|%4NcMc8XzDl)Eg_% zaD(2vn`=nK{A6FNLrr!mzPq%sC*^=e%+Qu6Q6pTTTwQx=!{}A~#ngHFAmu|k%ihNB z!H(^+WX1n*Z%Okd^%1Pe$E1L`aUV%eMxXX2pV%U+_u@c1x7H80SLlhUMV_-5lGbF+ zP8#Iaxdl!izgT;0lKsTRNW`8?6saxg5ICm#immr%u-wTeXu$ogy`)Uzogi0j1*}a7B z?rrp;tMq<(2l5N3&SB%hsE||Q;kMBtGm@a&#b!$dX53jNMgSq0bmVy=@of^q^^-c8 zH646wvc_}sfUoU?oS<`=TPD2F%ZOx8vd?Q{eFG*_psORQdUm+Aa|rC{(UY1E21K~F zarIgxmlUQe@JLjFq9Ef92TV7hum08ms_YzG15+JE%Hu|bk<&RHn_~@x%IcQkl@Uus z=cUz~B4Wq!gh}jcBC^R2WjJKe(p^P?N$%K;F?^%0T2F!c+AivUh6>c{EO6_JZtv1< zOHf)Fytxu9eK}X5_p{|jO5hjF*N3^OypM_!43{W-zNx*~1;CaM_it9}wlldlN`(gY zfGw`Tdr;hG$bIh|XWmEZ$ftfwaUxR22thc?5o0_XOnt8RGy|Dk+rG*KI~T}?wRyol zU)a*d!Ga4pStPuN12DLA2`3gaHE>3g_Etyq5gE!pAVmtf2K>vy2J(JNIA!gExGErw zoI`uxT@dDj6uD)Ov&#Jvg=Xi1te}2xW)wYZPZfa5rxE4Rx2uPQBH-w@&e&o&&8T3s zzp)>qEm+8gz{7F^6BRADHum-pa%>S`3w{Q($c#E|J`6%{Y-jt2<|A!5AL;={p)sZb z=nEfDU?$`Ofel|-l+x*>ej7XYsU=|Lcl4Ko{WovC~1-*Me^ZmSr z*Ui>qJPXTj#myAM*Du9vw$mBtHEDvYIW^kY2}&? z^U5m4UGUpInM>U8FV2w)A^xsDpZ?3R(|eoj9i`g+rv)k9d~g=iHlw(X8u697hXW&#Q=vyoQIR5y32 zazKRc;hoBG5os)KFYc-a2A?)iyI7X#tyXaOWZ|*ANr#qQ4T1~r4(lGyX{MWsX!tDZ zEh=B}(!wxU9ax9B;L7x*zCjLdKQlL(SCtPCl~vmB7jBhm=h7uklg-wd*IW||V`9fh zUzM!LHoATVy6Oa@0cF?eAhY zkjkho8;bbAHx0EcHo*)|@8K>&yGzQEH%Y@X-pR|3B?cf`!Ie?+V|OZ%T&p;#mS1F5 z&M`S-sf!aOlrPe2wtT(4v$-i8*MzH5M7+&+x$EF>Vt93v$Gx zPd&B~BoG^@E=VQSVrOK*PMqMZ4oIoD&_Ds~^s03-WvNDSvmjg`3%FD+fC{SFTQi+G z9cy2WpI_)Tbs7qz8<^Lc{jCKp%L|c*$|Fb}%?)HO`PAj5WxP~H%#kUsMvjv(#R_=i z{ad(A*kSWB$!|=oXkUs}3*!XZZh;5uV6bT_swfxuOzLMrEBeKUOpUp`rqM9x=hhsy z&x5rMTVyR|GgUr2h|Db*U-BFF)H+k*AoPacx{j&>vc?ZsvVt|}vr?<=+=PqV)I6VN zHZx_?Mk$~6t#@pHg$B|CAr@@((9e+qMdjd_!cDwI{*azik0@*VT!7E*qPJd z%CM|Ax4`Jn)w@OOq0NqK-rN&9&w-@MG#fR2v9JSH#=-2F2@b}zi=gbfUoO$>_S&-u z9F)Dim83x3RzJ?J46X!58SF2sIZP_!NVq={n3=|8c$N5?zBS(Fh#>V13eU4)%9I&6 zADJ`_*@;=a!QqXx@}lhy$;Zci6`Dm0JCki}G<`^$dz9^7!lHH3b74X=%}EhYUiZc} zYIFo}ig9G-w$H~Vxo4@?y{yX)8aTcfCGp!d2bp9LP5U#t%!`(@#!O?bGtO|^+kWvr zA?_p>Y0WTVJ$|U=V!LQ4S_X4IgHh4*uF$ULle8|D6oZwiZ~)7jJsb=yeK7a)rA}e( zxHy^yzQ}HuqMq_`%^M%F%*e{ClSTu&%!$BO54W~%f^8qhi*XVKikl zzsvzl+bJ_Fu-=-TCK)?TN-Ds5Ru>$GJNSH8L&1s4V_Pr*hherQX6xS=8iPMtwc&+L zpPs&RdsLmChP$I4No?<@I@}1 z-~h!9ggXz1BlaF%-q|@YeB3*snVtv{$D#hp$&;GtMUJGXKr1qyPBm(Xzfkc|xQ>qr zu*-W9LL3{(7qPfVOb3OR0QL696%8N?` z{G?hFlrMVXPFeK^A2KrH)C>AEj$!&Cr`=C4fLNSurxW&(5&$UAY0P!PnX4>HNSg%n ze7xda^8*Q;WFX<83rM8LR7pi(BkA3ciR#Go$hoycFWc%z5CVGGHD#laR&)`|`mOvxP&Y^aN366_IIZ=!W$MMear8ju^3wTiaBGlg{9GW}2T z)0hSZ1t?NnBO$S(eOYssEy#Jp3#=3EmlQ#;jA3HHm?@do1&2M{G(EBSKFHq!`=)y4 z4%Vo1sc42rsC(yh7Wu3D*bLr*GN|^)Zk;rK>!gWWC!M@?(y3b~oxXL_nOi5F<@i!e zHYm)j2e?8F@TPjTrVc=lf7G)U%P-Tqr8ry*-E8&iQw#n2Y;FEAo8v+NE^2G7y8W#S z^lB}gDqd@eJZh~LWCj$&@m|e3_uV$A0%&p)Fh_gNOijV~@aS{6x*DsbFDer!6XTrG zn-~x8Q=!c|IdZmVtqnIkL$eEwrkge(Oc(d`dU=ym^%~dKbPs7`7QMkR?QpjS1MK=G z4-N(=UKxIvH1hK4&8%MP;$qr=uc_YR zc2N%atof_%uZF*x{+jex$jP;Z)<%S!^;gOh5ckMNY&hqu8Rmf+IzrD=n=!Si)R_e# z<;=n$MglesvZZ!1xezbouvQ9<$XoNcT%x*g2oQ92zK zs9(%iar(`XCa1*=nJqcjN{DN7GttEG;Zbs$OmX(k|xC!XkdA zy+*6OV84sjDkT-?xuJH!I8J)4Pptl&TCcplkE zRtK_=F^PspYIOt7&pHe42|kyhH+813#u56agx`Y2xYY~VUT_{<0cD$GEt|LrU+A-h zJ=JS+ONovSU??Xz=eyo(ItW{X9jfIWG9Y)do#oYaXCB#ntB&QO?MQB~x`!J6YWi!^ zUoC%4`70Pr^9wVaxpKEHj8+7PHT3FL(CQ%I5=jKNL;{md>f^K9mHj=SgXW*FG0 zdPhr8G@vs4*dte2&a)-%A?Q}X=*%ewf~lLn4a$~GRB3(k!WZGd8DTNZ7qotyn5oL9Ly&!~m1L;g02xX>PlAVfuMc=R_dv@mV7H?6cc z?X)*7wKvB$NF6{3DL4^|bwNuw6gv@$oe0HFgkmQ`u@j-#iBK%kZ0QjHob3`zHEJ&= zF~SMML%&e;iH+cF0P$F3PKL&u#1lN&$ZSO<=QM&Q*LFDdVf$voemM4EfWdKRLtt=I zy6~KDHdY(pkgP6^IYy-BuX?0Mvnz=hx^ogulQX^988klsVDlw{+<<=7tt#Cl;X-2Y_qF${y2?>vfLbnsrC)<_7i zJ*dMLkhEAFY|TNse>Z9|w*KmBQHVora`gc=P7ysR2>D;!_z`uBoK0QRj4LR1W|HtM zXd2;<4ig0V^IgP4bmzKnAi^GEIJC64w{$aPMEh_hAkI|$dvuY7I+D5Nuc*}o6ILxK zZ8XO}7Oy}~<1tII4tHz^rYP52Qk3f`%AR6Y1ytp3!*FB}*5e|eMi0)UU*vTIp*O%k zBZq>^^cv1HFSdmOSY`2)Gi&VrAbxSTlI?Y2zE;OxYD31&BASk)46Z!UmTx*s|D1)3 zo!=U9{*R_yza=@KJ z^8?d^x>ajlSH;{cRi;6Ifxw3aoqBE_?M_X-r7m$QSEfuggWceqjFe?t0bV&#>bc}y zS?}*}VV4Q=x8_QNz3O(Z2-=i|n*PG>t1K;lP5BF3Q9ulTqg91@Sw4Xf&ueH30q5)V zoV)W5^Bw2zgpCdJHa5)L*f4Kn!@P|R^ENij`#gdtOdrA@7@{Dtn*GLEmGN0-SH|pl zhgzJ;6Aq<2lP4TXhsk@PHf2yXFhI=((L?RE=)G}1-s!=|JwMR>;c-+Mqa0(IN#)(f}nyyofGVH_ompt?$7_d;h!>|>g?6D<^PQ{Ji88mBglSSOVq5sb1!79%Haof+CdQr% z^a+39&Lrhar}ue`5t1;=W{-6IHryc0gSrhS_xvC^8n9n};Jz#!=qFYL8o~V-8PKlR zWLY6pC(e(kv`TbgMc-yQc9jbs2tQpb9j3LAL5h^2a&vKGQA?pyOlXaT`x^ydR>kYLPMQEpFICv?4le&T zBamT;WdeRBR9y58^dO3meu5O7)unxo(v)O5)@wXh)m;O~G?$H29Q5+d&1K|`bg%gq zHy_!r3=OVj_*=SiccEwE4Q@VM0>n#>`o#q+j^jbe2{&NX0_K-v5iJ^1z%@8fVOMC< z&6=Hyp5~-gZoGnazex@^A|w%xe@Vnt^%LzX-8nc7ro?%<zklN(p1fuqKcZ1e_#p= zsDUk3%h?eWi;L=$9z4@}U+C4-SKg znG5Bn%f^v&v``$p#mhBp*Ob^?RvCLWJv8aBmcMk|4_UO7k=yUgtTL1xVTUlP#iGP^9I+Ht(!xP2C)j+t>e`;1Cjx4+nlvd3)ETk6 zju>rOlAt;jvqLdx>;R%pi8_0?>k9ivWwX zH`;+21~0WZ&{1jgvKRWBxpR9QGa*ECZF4nFAmum8(nwVdPnyUP5kY0t-_BBOa71qF9@TZ<3`D*5^6F(eQ_K z1Rr&O&uUucgD7W#zz+Pl3%qX{HCtEGRLc=K7m04gaocFyW^59Kh@t|w3k!4$8}=fr zYmgSBtQ@Q~n6*ML&5j#!{i+O!A=+CI)S}!l?ilHNlaUI`1l4QJvOBg|Y0!#-kD_tb zU^H_p0(fHP27hZk!<(pAon>2x5-wZ*$F<#Tvfi7;noILxYp82_sWZk0?G@5c+Z3s( zJ+CQ$O^5FnP5qUnDNOEtH;5Q}0~-QA!aNx@2i~%2Mx|8$c;WOXuYC>L?M6h|V zxo3(h%9BxQOD$I72ixl_`%CuAzPDX%25-q*8)M_j6D_vo3>MEO<`>89Mg}4LZQP<6 z5FuwS(xe)>-A8jR7M|#==34wP@zh+4A1w&y%8I-A*&u}i0|UuT_Opyrehv#<%}i$E zd%CO_ZXurMZ=-3(0rVUqYib-u(?ku|lAa9j{+5FzOad0awY!wBhPJzxRfE}hY1WFL z2b3(jIg@T8A{sZ*Y&9;Co7p5)>Y;R-S=z?0j!%ZK*{@s+*`ln7Mf<&Ap76F>iN?LK zJ{Qey0g;?=%LJF4KFpSo!>iYfi8z%ct4;Kwi=UArC>_~ZmL3wnfTWpG*>up~nprX9 z7nW)nJaFZx%nhOYVi}PtY>Fr=jXLkcP%JgtOwdeN*eT4CpUB6qOB}E04%L=B86n)bbe7mCp;FCRxNAX*sUwh4 z0D`&_r;k(>P{iM^X+R(b8^PqKzezPzWYR5X?lCzh{GFH*(NPbPG*R81xCV z@f6sakU-+k9Y6x1OYYg95|He>!BYan(2@e~gBP*$)|)KQ>DT=^4N;;k&V5effGq`O z)fS@KQf7?*Y8FP(97G7-)SK!EzwE3zJ)EJO?1CWcrR_mGL9g|>;I zg|>;Ig|>;Ig|>;Ig|>;Ig|>;Ig?2HiHvh5yiaC%CQ9XiwNk;*hcwT?E%plYo4rF?v-arxv|)p!F6bPWtG&7dy2OY zImb=jW9-~L*tu~oJKWx2>o$9i!>KkK?LE9A*{F&i+*O^Q#V$=hibGqL>?oz=gs`O2 zE*GI|F^wJdNo;Mg$yw=11Q#OfAU3uSGNoPGoc9yumc0(&(ylH2jdUBoTu*EZwYEQk zfqSI_IZtkZZ9o0#Ne<7LrUAH}uU@dNzDx*O{rN>spInfCgnb^JSlwL;#LzjXITX^8 zt?hkwtxqnnl~YyIjBHt3pY6;sZBHFbKWNU>rsfyeae<0kj7EFBy@dg%uYPoxALhAe$T+hqPk^MJ=|v_E1(sGa8JY>%S%IDcnvZ--MRHC5~*eXvIW z^48p>c3x6rtIKvBGl%evKAvo-s64;aYm<9%sZ?y;w}shBTvmL%&e!z-TuJ@LIrp~c zs=m6a8>2o>)S-BmU4wak`Cxq$_it-njH6eAN2(?-4x8|{y5^LgfQ`j@XQ8>MklO6x zKXjE+?cn9TC&QI7c~|kN^N;Z+aeuO`g}$8tL!;tr#ra1*OUF|{jwN>ZO~8XNHUe?m z+Nn|M;tZUB>RNks!qUw>WE^PPWnkyc?)gwgtAuG1!ZZgKxtLwo*gyyP?QmFv9BIpW zu^cUHMuO>gh}yzgvk69Rfl_&+IQ|yrJ^BDN%$u&?Z_d>PyP5eJW_Q77CX8PGnfW6M zIxY|8Ta$-`bFzW8kW`(^plQ9uQLYrp7z^_Z1sts2=9&FHq=GJZQ-kyIGPj*J>|QEx zizRh^EZ8O^ls6wtu;v2;To7ibxCdQ`mlx)PKfmL?Kwl&W=3uxJY(l*Wt37e;`iZTT z!xLen(uwtOLM|_DRN{P)Kyk^Ru;g{N`Eqoyvj>{*l#ga(+`zxtT3XrLVJU@KKrF<; z8WDgKMpB_!u#*hy3(8ksx2>=i%dB~6?#be&DUYn6Lq6*;`-qPA(*5B%dC!FX8+4ju z0yduFJT!46ja8nfk*w)*MhrUzk?pu#_QAg&gQV7(O4tUS~D%99ycured108?8rH?Ik@Rq-il_}%Mdu2 z;p@doVK1jtM2RBhz6e2ghF!Fv%ADa5p5%33ku^h;(0;RJum!^Wjs z!z33h(d;fR0y6pU^zAqwFOZhn_XsqGR9v@?GZA+V@XMs%84;NzG4ncb+c6nPeBQYs zgyu3rTo*|zrdR@Uv8lxQ8=@)yDGa5lFGTWSA za~UKOn#1!y-(ncemgY4CPcjfYFc@!jv&qo)TG~O!wjBC`0b3=r^RAnhqK%4po!KFf z+e`vdsMzsGe86V8o^Xck{Q8~E=m3zg7~rTLFeQrn^6)c@=iI}H;D%whziMJp$Lf@P{5_t>||A8IN46p z3jTz1a^OpGlmyFiv`txc28&^-;f}h84Ii^Dt8Q&{0S5sEu{zY6X)*g_29R}IU2<7Xk$eGd_N_)%y}W0C%`w_+EK|bfs_t|fRGM$|LW{6hEFZ9s5 z6LOGI>0RvLmj)DLQaA^p1dXsWMnk7kFEuYwOO8Zw?=lDXf%8mulL6IgG(Av$BYr+_ ztAEzZ#v~RIU~C=WHQ^y49w8wfFDxQ@i3#)Kh7>y%feteT*DnKP^dyv`^w=stAZ4Ff ziyv>I&y82`V$XDgZB%R&?FtIuz;3WD0`xh<3)XnWHH1~{X5!bGgA*IoF!^Dx@xoje zOKq$&-ySMJ`27khp2ZiLS$$OalscHbv$(1;!+~N3H6OozXG{^F$wxXZl~0=GAqJO} zc|%8t9)pAZ374LuFe}suM(mwz%?1ZD@uU6W1{da1f$B?K%7!I}niztPRP?os_<>An zTnHHe8Dls0_wAHcSFNJSwxDbB2*W9t+o#k-6p&Z;xXB@+v{ok(2S@5!u& zohdJOd*@(dodXo7IcB2Xp^tM?@9K><$dikcPzv=#%oY;D8)EC^BA;{#i>^=-0R~0z z+p<#iIRa1kFex?J&Z8)1PW^TIY@C&DFKcI1>}ul1ae9mi4Mu1t`L=m&$#=lI%^3I6 zXzg9wT)N45wH)AffD$bmWn2x3&hGd;Yrn06Ikdr^89KzLD-`L zaEpNI2p%8Tw-#)tN>lYqoOygyvSnLrF7__>8|H#!R^ZO$)J#{#H5R<&u7dh%_TO8! zk86e1KJ`hwIK-(p6NAM zPAhHi9Zd6Ot6TPB;*`1}fZQ_6_{0~?VucKa1Y;7Hd_fp?PK2TGMLK=LjUB7kwO*_P zd$DS2<%I%U`>=pAc&JI)X|mopmb<1Qf8!@9_d&Je&dk~@gqez+!V zwB6~WxHm>Co&lV-)s>#_4lSs@VajDB>V01+v88H|(+Rk!-%T72S&=JQjFzLJ@b*9) z6FNDbtNz<&_94{Nxu`w#BAp}{dtDCf_4WnY5ZV9&@YvrC9fHQ}Jrv!|ZDGoo)1D0r z*Ik9#>Ck#~SyFULiF{d17;?42^o{i_Yk}Nhowqvhw};61Nr5kXS|uL|k=uW6xM58( z(}_mRIINxFEpX)iB}2Ox<<5i+;%&3Ase^_Vk_QV#6mQ`4W?>$(*2omThUOG*ZZP-^ zE#3eew@{`qWfLc6s7rRZ3n=^uU@y=-S|mAe7LzO;C;>+Op*z{6vLth*)8 zKj|4kIuVDR@aKGl>JrzZa8%Q6dop1osVw!ymX5w^Eztaad$B7&aK$%#_(aawD$T(q zS3xuja4g966A-}%eQOIrB7F?5dAJHJR?sZ29xSc040hWljho1S2_|N=i%A*3@;keo zz&Dgoj_T-+j}_y4{o00(qD=vQ`%)(iX`H&-WUeBXm??5`!J1t+IeIW_RzcTf94hMzVAIR|BjbEd+&RXe&>$& z58az(_ftj;pCbH*B-|!^oN%o3al*%}&imd)In7T2jQH&~X=y+AD&eOp;dfNRf0MB4 z8Regzzeo5Jyz9qCpSkbdFMrR=zT@6!kG}WFcdGrP%D~fpS(a_`CeOR>d*sJzfC*k_BGZ7i|~FcM5ngLa#jiJTk@Cs@-*@3xVG5J2y zK5gHR#_#W0I(9sVrRsRCr8|#_V{#2Zwu|^naZF;JpCG+w=|!D!d|vsQEPKS$zGtL& z?C6{MThCjG-#jY3e$yalsvVoY=i~Puds8y*AN~sGEAjh}5Eg9?{l0$e(Id|tu>xW{ zHorQ{rm44zCm$z1<$cc)Rvn}K)AL(|kAo+|^FV+1T)Y3+aZo+SN#&y}rLbr?*3F-z zm-uN^csFsQP2!u!?rYzFEK`v=p8UX&v{BOae3rED3-bz}m<1^$_F2+*c{AoIZ&P3JRXAoUiyYC^YP8wYw)P*R6X+k7DOR@YP{vj+?Dzj7R|40FL6-p z^5Mqj>cfkTPVdaAD@%J@4|5sd+QU-jt{hy$pMXVSV?CObAz)nr?0^ zXDe^HvUO$IOR|`UPd#$#k+DZ6#wJdV^MA;9g}f_QSSIIQgf-QW`2`ve^XF4%w;o|d z^erbA_c2?XSlV2>@yPPt;p+C<-ihYU3Re?zwdaYcjf3gK;o+U4 zbN49Y4jL#Q7G2(=qYQH&7i$&+_kF-$UYmQx>)HYhczO?-Q^A>Bp+B7&(+jJST@MP7dJj ztxkG2#A2ZE4O-#eX&sh$=RI&Fd6D7m7#;w!awmn~-g^ujKVcv};oj0GI+OF0-CFlV z*EUm}z>ul!f{gYZ;L(>=b#NbKJVgESnzCyvf&qk~3Msa3bce(CWi{}G`#0V(XaxGb zCF@;|@aifnfa=-~XsfdT?+hWoaL?pYD5mj}jB6(s# zRf>KaJB*#tmBjQ*-ZxRN*SEGQarlx6{Jo_!Tc@pK^wxZM|1`Qcj1T`Q4C3C7Z>_UM zyO)3#Pedn~{TClYIKXg63NDKb{s--kf4)?t9?Q=wx?|iBIqfZ-SYO)O*t|*0(JP@S z!|N|X-@Ss2bW!%@Ho)ZJ{)q$K8MnL1%A(^x69B1*cShFqEy&qBp1r_v1tDwQo#CZ; zmNeWu{@O2)+j2+*{7vPl(VLIbdI) zY2ow|UrknHqIbX5=Yba!6tE53L|Sab{3832T8M71G!}h8e&yYH2}FKT`WHJGUrHx} zC+JI9G~fx9+!-hTLc@@{DZB)uO!3$}Z}%L@SRCN#$so;h#8%|&&ruJvKdCRO976o}{aO z`62i-lGXWRjj-0CV*Y27bmf`u7v-aO8Dn0;eS;L|C>tq_bXwwPyQ1AjAZu_@q2_H zA|k@)^*Nc1WPi1iuJ7ev;m=4mOTW3LYbwkFWeQ z{29r~_lsC&6A|nGT#~N*k?p9&UngRO&d4_;=6`+8hDNeKB>ujnzpoK4P`@}+ ztY1DO{@`Ol`qvW{=TUi$N_e>vR(s@Q;?GF-?WCV3EO^KE%qHm{tfc>BC9Lw~qvFp< z_N%17jj-r5mUksd7cQ?R{nPi4C+UAe`VwK5+wFU$%df?sk?eKAc874J52ee`C8j?_ z`hF!{elIcoQPQth(&Yye(-%qq8>rT-zbE_|A|gEB=VFN%uU~#M{)}WFCja*n zj{HUCe>_S5$D}_9{8f+e`=hdK zzvlMzX&~{`V3F&GYi)D-_e^m+@VM-Igx^F&%>Q~h`S9|iw3 zz7hZA4;8%Refne~9$&P11!=KaiyVBmiJ z{)}YrCHAy+(F8K8*>G}92>7OV4 zpAzmR-`|%{6C6JB3-f0rI}R^=72!uheziybVg8I{Uq|{k5*A;I?RmYJw>=}-H;K2N z&|JZxsqY_3(hYy}X@=J?e=>hYvKhYr5yBL2CrZTIkhN%-G0eyT|0_ff*{C%>vxe)aRCq}MF$`tB!_@>Smz{Nnua z_Q=03hW|O=ZxNm*BEsuKNxJ$czdL_MvR@&88dkde@M8LJlKzu~-%La-@7I%b<(HqH zKO@;6lmFilmfv2?|2z1@#q`%9YkmOvE`F=o-d7X820c7#Vec=0j`EM^X!a246lFeq z_Yk)6NYYh5v^uKX%Kx8`|1#kwp_u>sl62+&fh0Uj{vWL5|4fpu{GUz2%jEx6!jzep zzni;>y1pX+KYvEDC&~ZE!5=Wfqm92?Ojr5x1N89G>}m2J5`L73*#3_s>B=wPKwdmY zv+pPWj}!hdp_m^(xKX7lUHRoF=+8*@Bjmpv{03utel|&0e)$G^{-fDHA^%?|+#@2E z|B)nJ`9GS3{{{I!R>}YQB>lHZM;{**%hLGkd-)Xd;yIeV0$G1A;W0w7zOf`-`Q>ZK zi|1%IM*h=;R|&=Z?@Q8^U%rRDc#dY@O#c6Z@S}v3U+MBc^k*cyLi#Teek&0XKA%t0 z4@rMxBH!Od_~YQO@J;mmKEk8-QQy-Z{`-V~nflsRp5yNu@Fyh5A>$ z_!<$hKi{3CtG%xbxmCmeNd8w5X3X>UeoK-rdO7z-e(Z66A%8~?AI*N5@4uID+P=>u z>8kIuN%(W*|5d`f#K-nE8P8ar^2-O(AGf#ceoYa69lF_Tkr&SqrPhoS{s`~`EeO3L zYZ3l5=^h@*770IyeJ7@W54y>5kRzt|N&g-4kB0J8|Ix4I#~!c0{ZJ9UO8)B zf1mKP2|oT!!jC8N`Mrey8ex^I_Wd2gSCVwae<&$m@ILho{Mh65e}eXV`2Oq%`QF0E zRo?x^&z?p;_%o7yh;)UI5~23}*My%Tj99nu&k+7j!j5lVe)d6<>^YYG8tDrA_s6XK z<4OASq$`}JM|)$Iy*fLB?x?V*zuLY>xeDdKCVLI(3VZr%y!<5nO{5>Mq(7RZzlC&# z)9;%}`W)#Br|Hv4x^#1e)AZRSeV=rN)AYxa^!JdiaGJiFr2l==6;9KyCFws#y25Gt zW|ICtk*;u>{&bT5uSi!oO@CjK{+pyLoTfjQq`yGA!fE;^ll0d@9}1`GKbxd~4e1J} z>A#SqpCeu2H2qP-E&YsSkC86>_j49{g^j<$1bJSOy`6OCNTZIg&hLIP!S5$XS6C!7 z!hfQd&nM|ONmm#W&(j~0a%#^=_AKcNNBY`3C+ryqNdE$?! zYrgGaPnZ1h$I~UBJnZROk4VE>ukgq7KRH^2NBDCu3I8zo8=ts7qP+tCjAS1fl5Wbm zW$^OjdYB}%#`CR7{Xa3}d+jgqN3AIy)vwV1dNsyrR&zIe7an)8!p463a^L0uAF{1{H4L83eW$eUjF`W_{)Pw6~3>#SuXExxD1afyso{YoPIZa z7aooyu20{^huh;rm7ZSr%jNuc!*}74($k+cK2-5_>W|Cgb2t3u!J`V_AN-SYd3VEi z;gRx#FBc!G`1acSalW$0<@eq2U3lEZ2SH#sJveOSiGPX{D2DAr|yQ! z<8v1t|6#$Sir>HS@5}AK8~*bJkLq}R`VY$OyBod>562OgPj~U*E}Nij{YoXQ{jNH1#~3DooB|PolKkoUTf8jFWhsG4r_nbGS^cAy=jrH>ImGW&7Q ze{c3W59i;%B{@>t+NW?BaD^W)rE|VqDg68k->UF)PC?55tf%Mw`7y$2fB%=#_eZmT zO*qA`-?#KQzR$mK4+k5?^L&nTp3hekj`C0VbwURpaRiQjM2~gCfBlVqXQlA7?deJ; z{rMOAgyVS!8lMACUybSSE9K|>qEh(z7d}=A{|gU86<+?Y5l;K_hn4*IbM{|6Km9o8 zyF5tv>3qDOf8i0raes{3S0fxBwg2r3f24r-8sXyGv3QBTkD>#D*z{k}T;Ho|fLrt1GOr9aI-9>L@LOW!~L!jE`3 zPyc77@JRMQ6OQ}mRNlWO9M|&|wgXA*YcKx|5}-Lek7r+NX9-$&to~D^7vul@3v+~{ zeNpAD5RUsF6%J=T=KcL1m7n1I4|~`m)xUqFaKbNtf^hUVQF*^W_*~w;S7*Ob`Th?G z$NkjG|EdSGES|5R@YfK&%=s-JrW(=Ln+c=-ZIX!-zhx7DrEQOC|9m0=N*VE9D z^p_=1SM}8Ys_aRH&smW0z1dB|#rQptJwv#lulusUOSq5^_hla-Jo{1qUhVzIgsH|J z!RzN04v*;b|Mc*vq7?q!Qu^~Ryt*P!-dG7wR>D_2YzV0Owg{*6{9eNUUt?Dj0ghv{@d>M{DezH1VRc(91tKO zkWi4g!7V{32as~$1YC$foXCX}h(zMTW%*vcs_N<KGUK^>Ohf^}j() z{C`3`Xa83y>*EEC&GY57--PEie@}?7^Y{+a_lWowk2Srw#Lv{Y*#B2NPw2|t-oe=X zy%+8OSDLr+<a2n4e@17kVqRmlx z^-%74r*a?dx6V4~PaXFZH?=9r1YN>vb@6c+4dGp(d*6(@Pj{w^@c!K;dQin;%>6-S zlEx3JDB|R}Z;9dqhPn^zX}ZXv3Z?^_=(ezE!L^#_=&7kdVJc^Sc0bd^Rn~U33QVs& zXm_4b53gi0c6MAQ*##O-^S*$e2Y#M2?qt4P<=A{5vgxc+wE4{Y>4SqfFAL@)rW+r< zdP7r=UA-JVuCmTF_S5q2q?nuLKW@EJ%4ibaw^HVwwlW7SqsDScCZjsFxRz(yBsH*6 z1)gPO=W&{@V9gFP;MaE`V0i~WI``*cj6I_G^12_%BvHV+yi8(fY|bcVFphH>!4Sz0 z{Uw@(tIw=87a}Ccj|}Q$e!jR5-BMRMQhc5+rb5EOr|J}LtVhn9!I61odPc1r1)7cF zMEEQ$SW+9gFuxS^K3haFI%LzdGoH*R?r^b;=R!A&k|F#)K&%j}d~w+-6s}F1%^nIi z=4t_*WPIHX$J8o$9%nwZk)?{M_>yc?o5`9*WP>-)Za7`c6s-lphJ*PcpCnh7q5N_} zXBXp`$N36^hlmnLBRk_>V$|Lpg3ogJ?-EfY7%z(b{Z%-HpwO90j?tSN-1yUQHKmq> z?i$r?O~+T&JlUOGUd)t2S(hr(lFgJh&^8gDtE228GFs(VGQ0v2CG?>@I339@COb6e z!QGt`Yhc|6C(1a`rV=)S=zZyjxtSq3U;!DMMlv%hd!(@+>Er>UH&a-Eu(V2jYErK4 zD<@gPGgZD(nI%3)2r|y+Ql+i;0gM%m|JD%2GEk-;tP=EpENE2n(p;tSa(X4+>(mf8ip zMUr3mY22j=L7fDZY)g`ysSbl^%q>tCEGKMTrZJvG`lk>8j^ObYn&mjc8IkM|b`Z-8 zD94Nhy?mimgi+-~b`3bqVi{24ES7MgK^hfmT^e1ntJ!5p)d=p`ZGn_nKwa@l@at`vv~|zRWIs=WraMLMcA1c6LHJL`m6!pfY{>qCa zs{_*vqm_@trVa#2#Tfy;0j@&_M5@4&Ds+h`7>DlO0fQRuS_TnUh60V%bU;fDb2l?E zcQ*rbw=*zzKh1>8Wx+%Vs>qwV=Q1f%_gD>bPt~BNqgP20c4oRoQt(6hts4;=8yTYn zo56$hB;Hcr8qgSJEo=$qfoL#`XE0RsoSaUAQ2Nhc94@bF3yOtEpU-6Zih2u6nC&Eo z9j6F+bY2OdEDa!A3FvAA{psg16;*m>|HdnTMuEx{6=S<8mn+4D^|T_8t(kN~>YC}b zUb+U4OE$}oJ==+_YgU<1vVMx`wtF7J9rqBYA+G#YIXE5l2Pe|&jYj>G1L?^V!0#bQ zP%M`6L5Ac(?bMOa+0p4LlVXv??1E-F=gEddS7xBXOmdXCGMl^_1Bu*ZnV!o`CoMOf zNt@>pKqN{y6j8OX7B}mDRQHiF6@lJqUv_)<`kfxmAnJyLW7$)-;htYNWX}9cbGW9T zr5IAiQ`g8+ywE=d%bmeVcX#-r^o|B2*+1Sr=!t=IT3wzF@5!Uy$-(GQbazL)a{p-8 zJ2Vi9@UI~!UPpSP-Qh^Za^0*stc6=UTN_Dz+sLsZAQd;OVyv$hqj%tq?(TW=XwXq2 zUEATl)@V0cn~fcEn~Gis`<|8=a(;BFeGAG$*}c{d7}_0mj-@AtyT|gxlY4jf_j~XY z5b+fw1%Q?0 z%|TXhPM(rf&^jwJNP1&ybEnnZ-r?ryRG9uTTuD6UyQ%TQW(7?6^Wa zOv57^Cz_0>u&t1=%Nn^BJ*;z7mTGsDRJ+2C6{FY-T5znOs_%x04J?-;gn>l1TP^1b z2llXu)g$xDexWp`&Q@BjuyoCnElVV0Rh}h2?j<7|%<;5&X!Hzf>_7D2Rl3HB0BAqbY2;49voDK)i^*SSp*>{HsFu0p_v^&B+!=Be0 z-s@3x0($^>RBntG%U#^3R8p)6=0t_hN%{cH)Z6V=GYpzQQ~^dsceYTgdFX-U)&Y*r ziqb=7!%$sNu=tb%+a;9~DfEIW)^j9G8CdBc!MS)Ij1CBryf;ChDD)C$`hTkXvz-yPA{NI0sw9c;$|O7?OnspIMo z2CvO&T~uP8Nv&Btp3%*SRfhXvM#iS-!V#OBt<9|@OcammLL9($)btxkyK(JY-k?-; zuneV8zHBW7a%6w#D4wwA*49oKwi~o(Rl@LOCK$3KnklR*rzbgubgfNsz0uxjHltw6 z-tyP_@Z-?;DP$f})+13rXnxpP$l z%Upf`A(i)#Rk4Mtr7HVltilZ_n=eX!tcRe9uaH+uFtQys>q!fVwkjzT=(NvQ_HrY* zrl3^MG%6-es$ny7alWlvtv>g@~#$Y&LOF6z#Md?Jbz2WB+wyi+pKr_;N0ybZ9;5ANNPS zt`22xaC1at<+6^%YSuLtrc$HhK&C8RV^>O@u-u!Cn>S?zSR!51!VMx_nmP7oF`Zm# zWDk{>1x8F-@3HZ@Y{0e#C6jOiDpN+v5w+}UhKPgrJmvQ@^GRK))pm!+HC6bE8r@EV zoXUZ!Mn#FJjpwUcHl}+jnW&XXJsIE{a<^LsDl}X0t0% z!Z+nW`VySNV<2FZ5x3+P|>Kcr0%vJH`*Fk_p^vy3SV@5WqqN;hU0`$*N7 z@&D&9dc1)i_n>}f>V+pA%=3gaR$u(%{VDtaZ}|3Hs;#56XW0B3dhZ;|_%48iqxV0n;+b=&WxVB0c&`JG zXrRA*q33~lzUSc4^K^uV2Po{z@cRQ7@5eXe zy$L+SuX;YIA{WE&FC9F!^$mEx(Rh#GT|Lj{bB{?H(#!Di2YjZz36GxB+ytJP1IT`U zAD;=2e$;+9ockY*qt2!0ZUQ`CLu>TQ?EM%vQhS*R?ALkL%ocOhTENBY{QOaoec3E3 z=ANqHz4iX1qV?Q$yha7@-)QLm0vUyV8NEGQ!8@$q5`ROlQS&l1omTKZ_k~;HQ!g8= zg1(nDUR_UZ;Ey)m{H)o9@n|%z;QjgS+w=&teGv}*pvN!S^3qKF19Kec%7xZSkS=>?`eIew1!$GrYe2-fi(DY@b>Tzj2H0_y2nq`%ab!V^73;#@HkKma;D?#?EBlmn0@1+Eh|Pma(suh-3++O^LEA zR76E3ilp?rV<~->@2CIsf1c0G^M2;ubMHO(-1oWXba~(dG(}9Hang zg0D7slptM58BlZ~MNn3NaNw)3`YQ*@a-dZa)a5}BInYBH(t`BBI2g3aLwLXgg0Lh6 z0oM3A9}Al#XAzNeZlgz<$YRE@^N&G{ zNF>%0HWx64_Cq?$^2ZO_5Ljo}QGgLLfh+*;VDJrGU9b@jQUSwc0DEb`Vx^2*Eh_*zyso^~ zheBWLg9SY(y&#B8Lc{>|MZvKJ>!(J?rogeu0%*$QtCPmY*+Qm}?XohZ!7rt(0G1&Q zS%X&{1jKXt(Yl_p(ns+}8>O^DQ~E)plvZd2C={%U@{**XpJl>oJ5c6&Eg;YoEzm;- zkPT!A-ZXAiRP_)bk2ACv@FGI4fDabb@L)5DL;kB2$_$k4D!#mJLO~yRbzU%s?=P>y z5q4NN2X;*dzdMKG-^?Kn`2aa6bK;hD!21MP;%=CP93i8S2qcn~rM5`p8fPNPOuJ$C zz_f-WOixVJUAM+HQft7(-td>_(WI zLT2D#4GRmCaRp5-ph?EX&j*Wv1t?7@4(=Z#^u7I@oxCyTety9ieK}YFSUncT@o0*3zEIO)ouqEVcUb^w%w%_1CHjgk`_&Yi@jD<>}~k4&UN#5g_uFx2Fxm zg4D>(GqTgmOR|tUJA-;%R@jvgDm&qtoh5Jf^`?t_c<9*YusjmN2H1oJ%noGd=RhF7 zqiJDk@PkA^Fh7OHjOIdbI8UfhsLQ0jxKX09nJnCV?3hy6TUe0NEQ02Nxned{Ju%2% z$hp;jQ9<(on+wrdvSG(<0H2@(3xy{ds5*XGcl=^#Mv8_33{z3j01bz(l>s2{gFRu< zwK|N5=kW{<_E(XW^>YdG|3$3;DOWkb$awr}FBd0@)`NcOD7&VM6;)7lt}iF!5*Q3? zQG^pjtHR2#B3Yg+7mr{;?ufwtw{x9$^9G~Bi`eNVo0MLVh*M+vd&-bZuV}tn7up>isxqw{n)%`$oYl$Y z0+Y}Iz`*8Ljf;+M%jAyY3L~%b+%%yDtAp!>`j2)t#l9$B6}U6X2iO-5*cXglv#;18 zECUzWm~5h^*SPwgI3$m+b__`)ep-L^MN;yW?|f58b}Ov3UV3O~t_g=EP&=aPo>+_*W}tgIOpXXxA}i2GIc^(Qr`hB8K?|V})T1 zrB2VW(Zb&;&TA|Zl-+0fgme2w()eqNPzog=S zB1ZTnoN%;C;J|s-GN;0C65M{O0bykqLhDbZJ#Yk;Jp(NJ-7jYPw|4x~%=v>($+qNg zudR#8JVj_zN=oSuzXPj*w*WRdMQ6CRO)d#btQjB@!Ns>~Ie!LUS#48`UqOH-=I=ou zwu~}~AUZY=jwQpp$i`%&c!S@xM}0X8xUOO=fYudcr2s3yRbcAgf8~e&U-td){9;e6 zEgoQ2Y%F~6H$ls0Z5RNp9c!!mchLGbfr6JkBtHil2|WEe=eY_x&X(P2No*N|8fn$# zbES8~K7C4N^bShm>9*>wymdvaTrr{9J3w}?qpg)t|F^mi>;QBQUz3H?u=fM*$K1X+ zVOu}G)yR<9fmNe-$fWyxl3yH?O-(8N_K-yh|BlkTkA!2*VG>m$0G^Ol&|yB$b7G-$ z>%{vfrY~qUc3QXLYk$C8xL0X33#!Uk?$R*=N^XNMRM!IDTiHmlRpbNoySj7-FBGT z!`m=HaS4u0gT8jZLfeB`pi{stzPoGxFQhN%G>53hxN!QsZ72SO1 z%3~*=Nx6YrBRkO0g9Dq+-aI)kR9VS(wf^8t&vAcgO~=y9E<8GCc|)C}=VB@rU%3{_ zJvu`3yz%O|c0NySVHn~$%Na%?{z^+pu_N9una$1ggRhI1*Jy?eN0t*3x8G~%(qv=b z^ODtc5__vHkV}|uB+58syUUaip%r81<#)L({+P*)UR^>a=4+0?t>%-tm!s*$(>{$6 zWmEaLei|sL9uDS{H#$^^KAq2iUtBkH~mzpQuZ{ zxQWH&7iia=%)RvS^nDU`tJ$%lBB9J#pSvu-f-i``BGwQH0GAK!^_#e*y*3Kqmg4W= z)~YcY>QKx;TXQ+y(p^D#br{6SWF@k~&#>(uh7-2EyG{7T6ZjboG*tX(~ng;bay<`);X^& zG?@~ZV{j$yex^wgHHsrlLZ^G;;H%xm(@nArg|BDu+otAGcM^&p8*6No*V{+5tfQtE3XcTGVjobej-~xMhEN@@e=;dUTe8kBD!B?V7ewD<=dV|d&_xl?#vFliYUpp zDRtQV;@TOQM12tea>^c!iT!z*rJ}+$@5feEccLF5nXW z4UTWe%TpUxwWtLenpxcuL$%H%DVCfw%jtc5=uwt&t`E85!J!4aIkp@fPAx+I;aSfw z2WB&lFdWPj%wmxfH059r4@&X*Y*UOp@J;(l+#uVBpvzV7q+;TZ3iFIi4yv_sA1vD_ zrLOhV?wdr2#?upG?C%Z0JhfD}kyCt5H>>8LNjtrbi(1Z3r(a}8eG-{tsQ$pd%U7?&- z;{K`P2g$tp80}GQmzez_z7k@mQdN}Ls^;dh##Q%B#SRN^7$9xAbGnH^kqWO z&il-a`B^q8+hC2&WkK2xM~redc`4nJoNX&j3DWY+uFJ!_iI-PWe{l*i!U z27Je3!{1K!sqI9H-am-3($p5mD%fsyl~93r9*6nnBy$pJ$!9{*8yg4)XS>w3cdE2*(;6l zvD}sR%WH6K58!zBznqEdxCVT7{vjJA8JaE|a(o}=WY%53Ul93kA^SJZ#I$hO8sGw$ z_JWDO3DcTuqX10H{|-#A1}n>lV*D~lYp;MbfM^&%G#MX{TjTSOApK`1-pj`(a9{xE zw;zXLB+RgqpN;?KO@sIo{D6oE0Ug+VqB*(7FSSHR7!mE>+b^W`yn;uDbtgv$Z1J#( zXYr1y{fixvi~dKMN+pS3i7g%cG_Tbi@Afmi+`FgGC*eyRMhuVjXs=;U@oP0TcIIcK zB^7fumRNUi1|=ed#U7p|Zr2Z63=H1T_r1*IsB~o6AMM(Nw~jTXCQ0sD(pk@rmcRUV zyunpG!TWS$W>lv?eboEnh7glFyZI8NfabIxtVx}0^BH#EocimZd^&yq8DAgZ5qn8;XEg&H+{=|=Szre<03bo1I<1^f8yW9My6`N9_ z5e%1!#G<1ISB`t#kX5saWPC*`S?cXs&8sRsoT=C=&U7sFjj;n9OHKKYW^D!<&|gTy zxDoV`X{g=)#zLpaL5N{26e&J1?G~z4D49T~FExIUH~$Zouc;|>R+dtNF<+Wzn5AC! zE|$pZa2ic;F!MiARN~E%ntR(D^%Z!m8^B|gu6isgolCQ4GHI0yo1SbZymaFF)0Tn% z6K_FrS#q!<7XQ;_;Xxt+_^_4CpuumttiQ=YQXEqd#W7JbfO7xpm+~xh6Zj9E*i)`< zStatUBfIbA;|cp5X1b@c26^WqRkvh#Jay)@Z7E4+D{3#T+&9E3c~rpJh1g}AAs^7B za&GdB>B&u)H+RxiWmDWoi4(-7JvV!$Fq>M=ow-tA8avZ*pQaG@Y&)bi`1K&2=$U*H z@8G_=e$_Vn;f*|hEb6{ta`Mhx3UFwpPTw|tOD2Ma&)t0VZm&9FP`fMcQ|FyIgRKs_ zAt@nCL##P`hgxdK&Cgcr_k~L;dp!%^eQs1o%Bbh;!}qk@Z%D2?zl)5v#lO3fFXZY! z+4GV-=u#!~n(AHYoaiV1hVz>$uM$S4--RB)rn%``Wg3afmP?(xo;~($e~>!vojHE7 zyMD5pER8=uI_&GZkwy`b#ImW{ti9CO{m@}g=lTXszVMAcV*@PDY&94AFH1i+yL9CO zC-sIm&a@m|M1d&RotZ2n4<9)kFD*0WyjRuM(ATQ!sgqZrs`V}Cz`G&(?-6*`=)%49 zw#Jb9AH1*{8s(U4fPnA`9d81PF8 zzee>Sr9#PDtsEOD82~OyO^lLtU7u*B{S8=NpV0kV@AflOR8aGtW8!^#r)y4+b%`4` zZ@6dF5Vl+K9u}|}Y(m~i-Vty3yWT?|zZ$r$#BJ-tw&ml4HynFv&AU-@E{EXQnBVk@ zwrk^nS2SLe=YJ(#Rvp^Ei4^=NNLuz{vAn&*$RK;vjqatH}YN(0zHS-%a znMx(G6F!=Ij}sqVlWM)aza!&I_={xT&|G3jm+6=e`*jRcR*6pM=a+_Iw01(bu5_fH z<+ZH4*3d%SSl7Wdb4U^ITcIgFG;DXyL@u#AG3-EyZcc%%_&${G@PKKx>G4a}jmEd0 z>)qPibzwpq@*jSXnziu=>P>f&;`^QEv-cc@TCMfp4zleyj=Ony-1bGy6ZHi`g;wv$ zQSPKirOj5O@lE9t(wd#=az@1p-PZzBqR&Mr84%iTJXOPug!C$S*d6&iS9Is4iTpOG z@p{G2W8ujQ9)QMatz!34UEwj8d)0A&YYp?}^uAbjDM;m&q2AS=gAZzyn)|0VeX7Z+)s`OFWqd%u z)4w^4z8m>$uVek@?@BMt?Rv|(g++FKoa*9UH1+yU6DAmNPDk@ztzMTmF3MKcL*MNs zUr1o2VCj%Ew#pqm$Vbwf}C83Lf7t2Q?5ODZ^lV3-&{w2r%>s>f` z|1WpIj93at@chWg(V?&)Hv4f^4(>G8uE>!H1}r5h{r%l;gP#tNe`7Srv4PmLNB zIY``JGuw(hBNfAMJexU_Tp#Du{(Q7H3&eeEw_4z`*%NjL*~RWfh+DNeB~vPjYbl)H z<%aZJ@ubb$4yV0Q`scNBt&KTf#T$A{JqnP!bngJqNY73%ArJ~KDtxFLSiTHXbuU50kT}}K(hW_6tnJM3S{D6^st&H1u^nE*{QHBt9K}re{-VfI1U>#7&xrHaoi z3orT|saR;1p&E##KOLR%V8-~tjpX%U1(J|x5)$%Mh!K4A<U|#OpST&9ew+`*FQP z(h4$@7nZE3_I_P>Fts;h^d3^2W3Vr$Z{)~pxBwO&Np>_iKfl#YwP{a9=Bz_a`fhiz zvQBBuCC;Z!l23MA?-H!8Y`RAnaY82riY^ft2KQ zJc~}`j^aC|SG7R663jU!tSDXjrfR`K2VHi|&T8SLg8@UMD-|tSbuoWvA}a0Ow7wzp zy%Uww<>A+=7rY*`q1-IE(+>}jK9AW5q0n0X4PLLFPqS2@-+4!bCprn_Y9p|b@P={U z&TLB>2enJ=TGDCG=W}sG56|q`QuIV^GQk#_e+{v8vsrUmH=p4dU2mLY)!nBA+W z!i9HJ^{$ package_renesas_${VERSION}_index.json - -git checkout boards.txt -git checkout platform.txt diff --git a/variants/THINGPLUS_RA6M5/pins_arduino.h b/variants/THINGPLUS_RA6M5/pins_arduino.h index 56c4b842..5cbaeeec 100644 --- a/variants/THINGPLUS_RA6M5/pins_arduino.h +++ b/variants/THINGPLUS_RA6M5/pins_arduino.h @@ -132,8 +132,8 @@ static const uint8_t PICO = PIN_SPI_MOSI; #define USE_4BIT_SDCARD 1 /****** USB CORE DEFINES ******/ -#define USB_VID (0x2341) -#define USB_PID (0x0068) +#define USB_VID (0x1b4f) +#define USB_PID (0x0037) #define USB_NAME "SparkFun Thing Plus RA6M5" /****** FLASH DEFINES ******/

    6&J>*|x=3`H=qk~5qBn`&A$p(aqoPlVJ}>%;=q}OsML!k& zO7x)U&!WdgO>`aS<7gt^p*S^ zUm^NDjRiPmMN2yA_*~I7@jAX)bZ?@LzY&e=s^cWlaWuf-{OU#Tr7;}G zPl_I)F%!psiDuG3gyTHXOVV_FrRa_f9ltHwj0P;cy-l<!c^w{}2HhZ-WtkmihU0AK-t3_X~ z(eb;Yk+nK*FIqlP$CaWtOxE$8qWh-m_y^Ih7w9-cbaK6p>AUmQaXma!>vN(F7wXt@ zk=DU;w7NtW&(rZL(N{0g@%y4t3v}F3bl4&tSBq}AOviVLez8QyKZ$l*rsF=MQi8Pb*RRv@hoaFp=(v;Uhz&Zf5#30?F2ecW zBl_hg9Um6$ajTB|iB7*=#}|t}ey5IK5dHlw9XGvOYxccb-J(nH*YR4>Hy_mTN20AB z(Q&-!sK<0XUUbtFI=)ZzYZ~Zt`F|Ge^|X%ri`G4><4Z-iY}4^h(LbNpaq}0n=I+!w zRCL)(I=)VH*DE^yM6}K8I!+WF{icp5h~BbG#}9~p`;Lx(5lwzq$7hSqcwfg0M7MsZ z9~vN`QPYxlIU#*bo`L$ci-#ySJBiT zbv#IP)*&4)5`FrJj$aWC`9;SqMGJn_afRrL-*miQbPr9i_-Y`P zu(Na=BU;p5$0J1_rr%-a{GStjP4qohi(z~v@gY__-LDY+P5jU#?Kcr^!AkkrCGH>^ zFMcnHQ$_oTpCxgws8jr5qSd0)MK2azCVHLdZK4l}J}dePE0zBZ(RalEjFpZvI$3MJ zs9SWQ=(VD+itZK-r=J|<^zB3wMTd({6s;G%L-a|}A4E;`vz(kyAJM_07lUW){1TryUiD_Sf%RCJW+`J&@RCyCAwy-0L{=w+fSL|2Qh7rjYz zv*^8|O$_R{ss18FV?=GD@uFQsdx@rs7K)aLR)~%itri_GI#skzbe-r1Q5wFe^4uwU zzv#oFPm697eM$5+(RW1O6IJ&M>G(dEm@bbh|DQyUi5?fF%aK~&M3jGDo9ljPk8fsbsvv3Q{sW5Iif>EOGL{=)%`q5cfQ0l z9X3MRsN4D~Uka7dZ4afN%XW18+X$h#CtWJ^cFFa#r_89VGLq|O)M>5768%rw3?rHU z3Cu{Ys;@Va>EG6p*-X|CY5w-ZqH5!@{83-}Jo30{l#g1jtg5Q3nWeMR4*kGcU|3nl z|D!28(_5VEOy-{_lN_nEMl%2ERSo@HbiiK6)m2WRjT~jg$(1u^)J>?GIfJr2-51@u zrxBKV+@q58Zj_L!Q@!HpFK=hoq0x9dUdOMq=*@k?KW)eD|D^qLry(yspZwzfqA9(z z=*_Qh?=-1rUW5QWRn>3a-+A;#8EDbyO?f>=eH30;;(jGCzl-Q+-n$VjoFB8rd2)Ue z=#4bAXdG~xjGqDwEY5AT-3LQW#uQXqz`6@*IdH$5o;4ZMX*=F8``9l{7lZbjS8g)m z$ioZ!y_}4|{G#YaeH3||UvqjRzZ+>8X=u@?q5OC|ys++iG6M693&@Xd8Ts;ifR>Sl z^O#Bb-PxU&^b70mp)fGNRLYO*mCM(X-YDNww9ILk2Yz+9#AJNhSugWnUdQhjMX}xS zTTBLDJMhAGyUE~XymIM5Mu2qIY2VG6Rm6uVE9m}hnilZ4Z{OY&rKhI#&g3n}G`lpfC}01wqt2LGf-hfoCcmxr zV$p5A8$I*08%YNaxgRK6^x&R`EtRYD+Z>7wF|9III}VLs+$rCEB*bIM-_fu*b+dD` zYez$q_{{~I3;+7{&%bID?<~BfYDYt8+8yNYOWi|DM$Z#_d)B&-Ce7Q?V5E)d>OR^# z$9;6x%=vLyN5ZOZbna+47^VMi;N?_$Z=?4ZSuQ0tD6gohF;^B<*Pd(q{_dUz!^C@A zkiV*Um1}k3YUectI~$CZ>=oqm-<7VFg{z#a3V1o|*k2h1M>5hmzb=Va(LVM?C5*YK zaDP=y?MBn@d)!C2d3IO2j_j*{p0>zJq;1o9DKT+j!SfCK4C|QPRZ|LMYB!v;?R?+1 zof9wgZCgd#uJdi{K5A5ZsxNSPszw)jCSD)%`<{?QPxVySh$2r_^~4(}p6vRpp?txu zRb1AIu8D<{oRd_!%M!UBCr~}^Nc}+S(TL-%7U$QvY6{0W#}&NXU~Ff{eRN;-*pinU zcBRI}XCGOVnssDhVtW2(4fk#zT=a6oj%~D^@p412sFxc;Q^O9=H~H!@Eh;^`A!;Di zXxg&u?1l)nl-3pyN^hy!-mpBiPhnqI zUnd`9!I51#%?qombSicms!WBW_8HF^QEjqXE$Cmi zb>e`O+iL3Cq}4q_vw6Q6>M;D!(!^heFPxYf@!OWAr7ON| z8aH?3R%6$ox#!3HHKVYTv3&lnb;kT%OO5#^<0fPDy^clm`oA!7ey^_Ex9)6LwK$@Q z$(B6$zE>Chb>Grwb|zH4e2BYlEL}71j^7{Ol5+1GO^vL@;U~UuebcbH zb)R$ca+-MW=oS@XJk-{RdTz9O1oat&MDkqImbEI zHCL6wpHIEwbV?&4s2qv4iicnp97nn(da5evobl04p!0XWv<`j#&XqG;cx1cTQ#D-9 zE!wF2=%#wK()h%43*1F$r-{CnH>_~Db9ll2%Hb}>j_MV%j)j=3tIdb!C%&1H?IVd@ zPjv~EVUX-<=(1&A4;pCvP0Mzx_)uKfUW-V?HzdT-)28Zt}>~R#$bH z*`fEF&F|#%#l7zQ#GGRpA-vQo@mlGB*Q);4-%sj#T`48LnvVJ^TITXzMa#=*+26V^ zr^w$*E_W>qY9)(YiwYMz7YDSGg~a%`3r^iiViM~?`QNmXI?Ca;Q|FLajr0MnWIVN! z@y_wC+D5HpjA|vrPSHw+o}!gx9qUG{x#VbFR1XET%-m@baw*~(%2y;fDB?PDAHARG zWtO>)vX0Sz11pyO>6m3sr&|}Z%<1?#N$1JL*S=PXy?ocRoG4I&(*>%Ud%{F}&f7d(H zndzLlzl{BS^UQnNM}L{pHv83>cC~ACk5{(0GV9o<=`S=KjLSNf9m4855|_;ynxLck zDxz^josKst{Y99F1K*Kx45gg$S;Lmq^j=8shr5jl z-8V}0Sf+t3b`|D3@~?GW>m#X0?HZS<#~SC_f`e~!Pqm`ZBiF>NBda{iWL)vW&sigm z6AKNV{gv*cp)t#d$YsteU014n+(+k|_gC&{*tKB)gmXiT!?!Itxvj<|E|B`2soLt_ zjeoiYjDIEu@q#nG%{Nx+o;caZmY24@-Zxglwp2P_|K26B(zmsTwgwlw>8xB=nZ@9eMYIhfaEAFuJQ|D3O|llW>Td{MuD3ckk9|Eyu`gY;h6ZA`y? z^UXBwp|KZUPmRAPa?+SC_QCy{TQjr%++DW5`293nqY>9YKG6h z+)3wQsk*M~e(+7|`4-C=~!F;oxU({&bl0VTkiAMF43us(Cl#d;6_t7^!qg8ozPt7G9 zAtlsfhA~87xs>u`j@u=U^p&oVN_V5LB{icthKJJTQChBxp|qS$%e)`mHxCZlPa&=6 z@ebF9-ZQtWT^XLL-sEzvaE=bzibp$~<3L*G(T+dI9u#qF(CPcpdLHd?jwrbr2dEZk zPwe3l zTCshTF`xPG)l9R$eT*@`R}*9Y_AFz*f3&Gb)Z80y@Q*8rI6Z#9A%uG4Ad=S*$!nZz zTx(BB^7o6G#N23Mm2si$rrdL z29exUNS^GPTsXx!#U)zchHP`7+pm+ z9nLbnBXim2wNcc@jI^ON>s*knmzoUJ8mjcb+s>f#O}Qt=jOm!TyDFy;xnxX^>dR^B zCta@ccw`bsKdZk7-|kQ8{nwWq*Yh-M?d?m;^VM?-b~Vh8qBPcB4U0vWiY`~0>7-Oq zF=M(?UjC~OkAu>ktE%*vXCs{#o`rU#n&&f?Ov^li=kul8TN{eFt?1Tq7OjsaN3I@p z&55Ll+e#d@vp8DYjAG6;SB>p>rmOp=UWuM6Gew+pE85N|?72^kc`mO$_u&o?S8aak z>-p=BY{~`C*CwUUoqWO)*)+Yy`mIGF(I(?+HeZa zwWsPbia1B+S&!#8p44hCp;mK=^HSHPC$*aMXbjVPk^5+`>Uv*)s%v^Cm13&w34IIC zAJJb#B~JCVi?KmxShqSarB%nKt{;34N1X>1abL|xr(0bGMSOI@t!}t4_u?QHT}MuC zb;YjSpjKyLY2lP>}_ZgMUHiELxgCQXe&{>Xa~_a(axgXM0+V6 zRo%X@g>zJu3vFPG-PN?PpxPxP*N`~+$rEQOao|$-#LO;Jp{puE?&0v5BQ)u+c^Bus zn=^LDgHOKn)x6iAr+%3GWpG};=jql(L(co@k5NDGY}@gDQ;iOz0v~ee?qN1LU>pDKs`bT%b(|(S9r1WV!n&1?#*C?kaOhE zoSkZXv6E6<;F?^t^AzKY>8=Y3FL2iR_{ceu(S>u!I#xBNvu5MEQ+y(}?IukRxweq=+ zSLd3~Eca3!)jDpiS;u70VF}cq$sd2_8%XR5%qTREO-I;u(H0;+wpRG-}cFnC9 zF1-D~4`G)s|77hGOAdwPMXWShne$GxefNzv^R8Z2vF!UJza&NIaR`q==s`r5?n6W3 zE^%ENP#4^b&MkITO(NE*e#_M;dNj=g+stz9Z0N9UR^cq?g#|zQ>iPT1oejGj-%l7F za`B!zS6yMfvtISFJrlByq-WF?eOEP!?%R&k_if{+xCV@&JGJqXopY2hD(d_juKL>bXG=wVyAls>e*K9YuS2m(q`L4X9=v?wq4^ zSix4M$JO5fV|m>i^>?fKdtCh;P@{bHcdPn)yrw|yBP+3Q;m(FFY1d5nDD?L|#yazZ z&wP96YWE>ijByR3b6n>XW;wIev1cXrknKO9?FYL2TMclXU3j*0pllUS?TT~#n6~=< zn|?I=%f#$2v7M~@gw}oXO>bA9!amNvk}gKpeM;-z`X9&89>`Ez2 zai+>Ti>%{P^`cT;{|&RnV}KpctZd(9*u^`mZjE|2!8`P|$R|D@KWNX~!mnRgHEmhn z<}Dt1s7Kf4}sZ zKX~sC?+v_v^B><`vwQV@V?VMkzVhP5lRv&V^4gWR{5yR=}*`NHxFyIwp3R_AK5<^T)E~95@At9CzTeF1cCC~%2r|C~f zvAvkK4+*tgM-Oz(&FN`gh`a3=WraV{j-n=(cs84accLgX)WToW77`j>LK&IgGtr-3 zF%H_?Y{b)_)K=xRY`L2Lgk4HcF2h6T(PF48GA5jYZ6Oqde@fYz!ei-~T?mip@22N?Vd3Fa+VJqpDf=ejYshaJevqCAHVYp?IW!MXYDI4d;TO}#8KT2~qC&-l-%i`K3P1AyP<599R#xpEhnd;) z@a$n=Vv`mE0=6R9iP+tWiei9W2qI#4CpOsK-QC#TohTM|>sjmF_x0g?Iq&}ebj>_7 za|yF!=A>t4dzMqvzuBw&D?O9nyS!zd^pb~irF46?@|^UUo4x!X-JYX-C4DC6EZ0tN zzi&AxUBlevN9mvTD+i~y*1tS2y_W%Hb8Dwg^OVb{S4<2n4@tKNm5UDS)M-rlb^4@^ zE$>RVr+FW=UFp+yPDAzP^j6Mos2-Ir<-CUKHtC<8-%!0UUDDKs>U-%O{oGLPls>p$ z8mfbnpkEuRyQcVCL-n=v@%`RV-6vhx$j0i*=^fqQSp6|w@|TtBkLj!bRi%1Ddb)gO zrFuL=+I&(NZP--3HeJ$2P1Tn4v2WZ|oj?80CQa3$>HTfm zRBcNKHfyS`o{VnZR6RR=ZMSHu4o|>FHdVh#8n$ez-jLqdR!!Bl(^q-xrs~LsPMtJcLR41j6sAo~#Bz-0(71j09XX${V`dxZslZ)!`6yGbVucf#7eoX+%?e7UTSPsd*=tLeYV zPOp~LU(=WTwX*ttx}?|3>gDM(@kUvFF2y&?>WuUey;WA9PsiUbtM{hMy}PA4DLJ~Q zr8+gev3pypd#3krUrTjDVta90b=joolD6u->EbVKtDclD>9V%!n(51Nd0Vw_dYf0Y zRX0c z$-S#Z`YavTyIM)tc~I}_%jsh{xOa8-bb*KTu8vQ~5A9t&BmFCf^{)0w@8R&?)o0U1 z44+mVliuyh)2eTzH#TBg^}FH*HsC2nI%&d-0CU%@zeIUJuF*B=ElDe@ot81o@VW*kZ z;pwV(p4nVYpR9d48ag!(N}rN(`9_(}?wfC{p33-qV@x_fA>Zho819#EoRU6`6Z4Hj z(pxz!eMy_IOaF3y?O*fL>63CqzHwvvL>!rKESN+em2bS5zOMOofz9bz&Q8bV8=s_W zIX2&THht1hADwP2nr@ttZ>*E9c1pf+d-}-E%s0MFANN`L#z{N zl-^E$4MTJOaju4ZW7G6;<-b>&pG;qY{0lLfYx$4Rd?WuTRFQ8ykl1w2H?~b*i89~V zB$aBuaZP$(&H2V%=?l>%-&iQU<(7P-f0C3Q-0##pSNdFc%Qvn_fBLlM8#B`9yDi_C zp8n+N+^*aoR1XrvEb}eNDR_ly1zO{toQ?a(d6*nsRS#Dh3xTBx7wO zhIA_C?KL&EriQuGT&zFSn_-I{m0yk%l{%R61)va!3SJv3e4 za}5>@Iny>sujqbKdFtR*YTEJ6+#OvCF*E^$m~RIq!6RE5|PKPS-agc2nNz z`c{dZegnyfq3QZojop~`uylQ^#cs$uUEk`l)7QGasTf!poxc7Z=O#|YpdJ}O$9CyI z^J0xM|9zB&tW%6m#QrB_-8dRT){7ZJ){hxNHi#KQHjEiUHi{WSHjWuWHi;QRHjNoV zHj7Ef=CKLcA~qo-V-vDvY(ln*O~}@<2^kfekZocUvTbZaM#m;(yV!(mADfUJViU4s zY(mDwCS+`ELUxKx$j-3|*(Ek1yT&GDx7dX29=k4Nt;*r)>)(-oDMhh%T}UPU*gQ&;Nvsi=!cA-D&6`PQwV-s>rY(kEWO~`Sv2{}GC zAt%Hpq63VAf1ZS%Pc1g zIjguV{q_4lA!oc$gj^6agj^Uigj^Jpkc(pz za!G7LE{#pdWw8mlJT@U$#3tm**o0gan~qY(j30O~`Gr3AsHsA$P>C3z<@RB7OZkc1hpr6ld0jES0`BD()<^oGj$t z;)(Q4)Bl9r7e_<1q<&A~qpU z#wO&c*n~`vO~})+33(X>)-Kg`X;uxr!Hik^zCo)Zkgp|As-eq z(*1`23Hd0FhLDeAhLBHUhLBHVhLF!D%&Vdycfzx8+^z+0#znmbcim zrJcSl?`ro+JAGT;&F-Cc`nJ5)?v-}FU(+V^%pqN2yU-(tbcr28_Z-qS)`VIP=_0!e z9XX_{>>;%0kS?>Q(3V5G&R#-m4(URB3*B-^SK3GDnnJ#ZGn>$oL%P!0g)TXyE1g4V z&LLgtoI*8+bft3%We({|`wE?NNLM z(v=Pr5|ExvMPox{!vv(ZV!n%0X{akYI6c%*3~DGdudHbPhGJZLG~|DZ7H~ckEog_L zh3rtYupNpPu|v_Kb|@NRhoZ&oP&CvIMZ;{078fX5LZE0#fuf}Zik22AT1KE~S%ISE z1d5gyC|W_FXhngdl>~~03lyy^P&7iIXcd8?RRxMx6DV3;plA(&qBRAI))MN9=545) zoq*Jq&JQxp7m7|xkE#@FHy>`*k>4n+srq39qx6di0+ zbcjIFp#nvR2^1YJP;`Vq(UAg0M+p=iEl_lfK+&-RMaKyg9WPLHf$Xq z2^3u|P;`wz(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw>0!6n86x}XRbcaCEodQL7 z2^8He)D@lGP}wB`sqLG;FFGd_y_yx>(@dIq3Cft6g^>wq9^T8^ps7}bb+F$1&W>#D0)_)=sAI+=LL#h5GZ<4py(xm zqL&4VUJ)pIRiNlKfuh$1irx??dQ+h2ErFu91&ZDgD0)|*=skg=_l3Hm`x+`YCLpyd zGo1TF(V^*Svf_h=GW*JkK4~akOb-M7Ptm8&hoaByQ1rPSioUQz(F{8jeQAfHuk27X z(+)*n+o9+io1$+8ioO#l`d*-DmO#-D0!2Rx6#XPn^s_+GF9Jos3Kab&Q1rV%(H{au ze+m@+B~bLYK+!(}MgIyE{U=bAe)C5CX+??}1d1Akx}uL7DnBP6wQJIoy2Zz#=;r+V zRHd=ZzOtgSvFJHC6jhxMMa_07>SBkY7CRJmwL?)iI~29rp{UIcMeTMd>aZ!Q2^4h~ zDC!|l)Kj3Smq1Z(fucSFMY9PM%`Q+hhd|Ms0!4EP6!jG-np>c#pFmN6fuaEdMe_(0 z4HPIEBv3S1plDv9uBd3NESrGThNUOOi_VSpd-~6%*Bcb`HI~^|Rr6S+M#He9f}sWL(vj;C|c5{XeoiBr3H$X5hz+#plCUPqU8mO zRuCv!QJ`ogfui98MJo#wjSwhWMWAR^fuhv}idGjWT0@{{O@X4d1d7%cC|XCLXkDSM zXo1GcVF^g>o%Gt1V!=@KczQs(Sg*0nzOtf?8jDL72t^w^ABr}yL(!&oDB8>pMVs59 zXbU?OjkH72mUbxG$__%=2^4KFP_%Mw|yJS>?P**gevC?(nr0C-OsN;U2XvO>o(>aZ0_LUV) zZ7ddEG!#v9J``PGhoTGZP;`+UiY~T8(Is{$y3`Ium)W7{ayt}VVN-OaK+#nKMOOr59w?okrb|`w%4ni6`!rXOA?7Oa%nS5~xWrC4q0P&CB( zP_&pGiiX;uXqX*}7Pmvu5_TwB(hfyS*`a7@I}|NrQ?#r=(Q*Ps%L^2(AW*cTK+#G9 zMZ*P(Ru(84AyBl6K+&oKMXL!Etu9cshCtDp0!3>H6s;{#w2na0x&lS(2^6g_P_%(i zSF~`YvReXD+c*DNv`8pgxRS<(l`{LviZ-njCoUU`Hgi4{ZElC6E$mP<(hfyi+M#GG zI}~kghoVt-DB8vjMcdjGjTR`{PM~OefubD*igpwz8Y56NR-kAnfufxSigpnw+Et)v zH-Vzv1&a0%DB4q?XfJ`Hy#fub`6ilzt@ zoheXsmO#RGw11`YYXVZcCVxXcDHN@r6`fxxv#+e^!b;J5rBHN{ z^P%WsI}}}FhoVdEP;{9ciY~W9(G_+my3!6sSJ|QHYMY{K1d6T|D7sFd=z4*o8w84O z6ezk$py+0SqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^9 z6zYnmRVvFTAhj>^v#}S1qQ3poc&JilUs=&(m13KfL(${ThoUF!Q1ql7ik`AV(R4c$ zJ#B}gXY5e)tR0G;vqRDIHbpN86ul@=^pZf)%K}BO2o$|4Q1qHW(dz<5ZwM5`ko`?Th zP0>#RML!D^{UT8Gt3c6j0!6WaRoRHi2&wcYaTi)Q$~C_e+z+*D>?Sy8v9;;Yp{ zQLFQzsLc*V?RF^YutQPJ4n^JVP}IW?MLq3M)XNSjGP&s5RKKTxXa2d=MViX&D=QkB?(DA_iiSBKiWav+(GqqjTG9?h zOWC1lX*(1xV~3(;?NGFw9g3E>DOy3GXhngdl>~~03lyy^P&7iIXcd8?RRxMx6DV3; zplA(&qBRAI))FXMTcBtifueNwy5hxlfP_&ak(ar)zy9gBRDp0hWK+*03MSBPo?I}>Smq5|p0!8}> z6pa%o+E<`xyg<`-*59f}UKL($=OC_2IpMMv79=qNiB9c_oAV{D3!6(~ARpy+skq7wv) zP829QNucOtfud6cicS?MI!&PHbb+EX1d65z6rCwhbe2HT*#br92o#+wP;{O^(fI;J zQw55q33Wx2n<^hAAhkczEDj7slk*=;7c`aGS5|aMQ_-+ND7w`7P;{9ciY~W9(G_+m zy3!6sSJ|QHYC9BNV~3(^?ND@`P0{rNMK=f(-6&9WlR(kU0!6n76x}LNbellY?E*!2 z2o&8ZP;{3-(cJ!nV27d? z?NIcRP0`B&MXv}Hy(&=jnn2O(0!42K6ul`>^p-%;+X6-J2o$|5Q1qTa(fa~L9|#nE zC{Xl~K+(qnMV|;1eJW7&nLyF!0!3d4bw!UiRrW|gYGd+WVo!vkWxA#@qp8fkvZAk> zijy}9Mc+6dioUf&(RX$z`rZyjv+PjxgB^-~v_sKPb}0JU4n@D%6#Xht^qWA@?*c`C z2o(J(Q1q8T(cc0^{|FTQD^T>GKvDX!?D~u3DQXZXY7{7{2oyC56cqwRodt?YfugEF zQL{i%7lEP{p|0qwrpm1eNNvabaP`bkv}3-f-?b>SudJxOC|=zx6m>WsifVQ!>TZXk z9(E||X@{a-b|~s?hoU}qD4NXL*atU!Z7!K+!w` zMFRzj1_=}m7ATrmplCjUqWJ}i77!>}P@rfbfue;4iWU(lT2!EDh)`G5T2y{dKx*sd z7pAop^?Ul=^UG%!E6VIED_Wu`W*ZrbmUKQ8EoFzIrR`9(j2()WwL{Tzb|_lj4n-^2 zp=d=r6s=@aG+dx)Wr3m*0!6C`6s;;yw3Hj)IBD^Rqa zK+*aFMH>hdZ75K*kwDSL0!5n$6m2R{w3$#>G_0tsn1IxN&TtkFMHBObN1GRA_LUWF zRTQJQ3PoExABslVp=cXB6m4sVqS1CJ+RhF|+uNaN2Rjt)XosRPHbr9vigpqx+F77z z7lEQ(1&VePDB4}1Xb*v+Jq3#P5-8eRplBa~qHzL6`wA3|7buz_P_&;w(L{lw{RN69 z2^1Y5P&8SnD;il;j!HmkL-Omcw+uyR`{^RGeP_%J=2IPsN%)YXs zr;B2-?L*Ns&WECB?NIcb9g3c}L(vO%D0iry0_dS9UE1A(Fs1&TfrDEe5S=o5jWPX&rT6Dayzpy&&M zq8S23UkVg`CDau?Ra7=lKx*yzrPk9!QA0x-GmA3&%8I@#iv4#CMc+Fgie}lN=m$F# z{b+}xpX^ZdvmJ_lu|v_Xb}0JI4n@D)6#XGk^rt}4Ujjvc3l#k$Q1q`r(SHI(ojS+e zc8VGViW&uqDgs4K0!4*DQD=doQlO|RP}D3?)J34EMWCpwKv6e=qE?}<=$oQ4EdiP*>E^x$;Q@Qv1DMf>Y~Uzo&n8{u^!a&SmzM z6)oMlsO%DomT^85Eo+COGutU*`b|_lO4n@Q5P_(igibmKJts+pgszA|d z0!6C}6s;jpw5CAOS^`CD3lyy*P_(W<(RukAZZAW*cSK+#45MH>qgZ6Z*#sX)l3$u|v_Zb|^Z|4n@b? zq38rV6rE^?qLXZjP8KLSMWE`zIy)3yZ-=5A>`-*09g1$UL($E4D7wX_=vINE z+XRYk7bv#}^6Cm7!?*+-XejTxMTc(Q}=PImU&e=baBl zFW8~zMLQI|WQU@c?NIcJ9g1GHL(yw?D0N(Z>Qsp9mCvDp2&9K+)#{MPCRM%@8R1QlRK7fuflLMPCaPeIwKr zJ=3`|JOQaq$09E=Cni6Ty`kxYlot_?NHRurl`L_ z(Ex#>c?60E3KR_zC>ktKG_OF>d;&%D3luFNP_&>x(Lw@63kwu2B2cubK+zC^qQwM? zh6)r76DV3-plAt!q9uj8q8?@CxdfzkSbm78XIa0e|4RNFZK?GC<23ooik2&jZ}$&H z%R3*6RB9qSb7QRu?E*L!f9)fugkpiq;k= zT1TL0U4f$Y1d7%dDB3`vXhVUbjRcA|7AV?8plDNpqRj+~HWw(`LZE1*K+%>0MOz6J zZ7tLlEmKx%laiuk@}EV^hN4~jr7@~3v#+dZyRsNIITUU0d??z%4n;fKp=gX9ipJWZ zXeT=q?QDmlUF=Y_s~w7VvnkqLplA<)qCEwQ_7W)CTcBtkfueB&Mf(aAjTb1IAW*cQ zK+!~jqWuMmCJ7WBAW$?}py)t>qJspA4i+dnM4;$Ufuh5Nx}t5%%E$zy_E~-&ZFDHw zt$!Mamu2>q6&+m`2OJcNj&VK|9czc88utU*_b|^Z@4n-&1q39Gl6rE~Q zbecfX=>kP(2oy~bC^}Q1=q!PvvjvLI5hyxWpy)h-qVolcrV12I6DYbspy)z@qKgEI zE*2=dM4;$WfuhRn1Iw?&JPhC6^cgX$F8p|%j_#Fy0$DHIwTZb z=X@x--VQ}K*rDh~I~3hyhoYP9P;`qOif*+-(QS4py4|Me4uPUO1&ZzxD7ssq=pKQh zdj*Q_6DYc0py&aCq6YeSfJ<;fuctRiXIavdR(CB34x*~1&W>$D4H%%^t3?H zGeTX_)n({#j+2ePu;Im&H0qhN54b4@JM)q3Aa|6#Z_8qCf0V^rsz){<1^S-*zba#|}mR z+7$gKP}Hd!ciSmy5GZOCD5?k)H3<|I0!5t#ib{c^sz6b*Kv5Tgq85Rot^!5f1d3V( zirNH<+69U_1d3_`McoC8dI)tzKbDn!5|G+;`Of`Mp{P%Og1=|A%)YXs*{a3qM~9-> zoexEG*r8}nI~2`jhoZiAD4N?2Mg8nh)ZY$81ME;Vk4@1)fucbIMS}&3<`pQKPoQXi zfuaQjiWU?oT1cR1VS%DW1d0|FC>kPAw3tBAP=TUh0!51p6fGf8w4^}MQUXOw3luFQ z)D`uvR_;tdYEKPJaQam1_w)znpCnqgT4rBa(TdgL&0|B+O3sI(;dUrm*$zb`>`=6d z9g0@9L(yt>C|cbPMQhlhXib};`w0|H6e!wXplFgn(E$QQlLd+n6ev1Kpy*(M zqC*6V4izXmOrYp+fubV>ijEZOingy-MkFA$nX@N2JA|UYv!bJ_W%iX79ak-OJSh|% z?|dja!45?y+M(zqI~1L4hoV#LP;{yticYgb(dl+5I>V-Dia^ns0!3#D6rC+lbdEsL zxdKJ!2^5_#P&8GbXqrIL1p-AE3KU%=P;{|C(Io;!mkJbJCQx*_K+zQfMOO+GT_sR- zwNO`dOto@c0#fUfAFe(&6z!3JCDt|7GW*JkZm1U5oDzy|bUqZ_WQU@g?ND@!9g1$X zL(y$^D7xJaMR(Yt=uSHn-DOjBw?NT70!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyy zj|vn$CQ$UaK+zKdMNbM8Jta^yU7+Y`fud&wik=lHdQPC|d7-Z8x@zTx1f;e{HNm+) z6n&n5tmuVmnSEtNuT+cgPYXq_Iv z-m@usU!dp%fuauuiaru3`dFao6M>>n1&TfsDEeHW=nH|O83ILL3KV@MP&8AZ=xc$Z zZv=|I6)5^npy+#nqFDk(KL`~4DAX0bRIT(lJt_J*-z|GN6b;A^WdBqxv#+e^w`#G( zlu-1$^P%VuI~4tChoZmiQ1rJQivF=f(Z6;m`p*tUotoo*dnjtKDQXlbst6P{2^19q zMV$qTN`a!PKvAD74>N@v#+dZ&gSC4vqI5a&WEDDb|{+L4n_U!P}JWJ zMFZ?mG>;vM2HK%$kR6H!+Z4?!P&A)F(fk5M3kVb~C{VPJK+(biMT-a&EhWXG>u3Vge)OzJ#w?9X7 z{hs~>9cir4TxMTc(aO!mBj<#o5zdFARqRl-svU|}vqRD9b|_lI4n=F)p=d2T6s>KC zqIGPF))gpPPoQXhfuaoriZ&D|+DM>iV}YVg1d28lDB4V*Xmf$0Ed+{23KVTAP_&gm z(bfV*qXde!5h&VLplGx}(RKnw+Y5C?D>YZXNI+^G`H!FBp=hi0&x#$I%j_#F+NrrH z&ksdAJ0FU6u|v_Wb|~7-4n@1$p=b{~6zyq;qP^@;w6`6K_OU4%Cs4GnK+$-Cq6q>; z`w0|H6e!wXplFgn(E$QQlLd+n6ev1Kpy*(MqC*6V4izXmOrYp+fubV>ijEX0I!d7E zXn~?*gu0?J&6R}`klK>@p8nWS^lv70Y;&1?Wkn}87wb(6MJG8QicYpe(J6K)I@JzE zr`e(CbUPHCVTYnAb|^a24n=3#6rC+lbdEsLxdKJ!2^5_#P&8GbXqrIL1p-AE3KU%= zP;{|C(Io;!mkJbJCQx*_K+zQfMOO+GT_sR-wLsA|0!7yf6kR9O6&>GP**5{Ht(Jdy z=!8(TMt)BJ`sOnG%8G7oE~Z=<6g??W^prr+bb+F$ z1&W>#D0)_)=sAI+=LL#h5GZ<4py(x`uIR?*%H0V_txta4^-ZDZ;;iW9<}&-rie7In z-o7{#z2ST)deaU?Z`q;fZ95dbV~3)5?NIcd9g5z!L(vCzDEiQ*=p%umj|GZ85h(gp zpy)G!qR$12z7QyyAyD+CK+#tMMKcA8z7{C@Mxf|hfuipOioO>pnk7*5gFw-b0!2Rw z6#Xnv^ovke^lEeE-vp%gQhvDlwNSKB{u}Mr<}&-rivDaa=DsWx{pEZp`r8gg|Jb4E zUpo~2XNRIrUE-d5C~B}nQKKD-Dt0JpvMDMAiaHAvl>$Xofud%CqAmhOEdoVd1&X=} z6txNzwFwlp3lwz-6x9TZx(gKb5Gd*?P}EDHsJB2-AAzFT1d3)C>WY4EuB@7X)UM7C zH2x8adgWh3Ge?&)`^t*u?oy1sA{6y=J{0x0L(u>`6wPCYqJefO8f1r}!FDK`*A7MV z*`a8Do1z5-iWU?oT1cR1VS%DW1d0|FC>kPAw3tBAP=TUh0!51p6fGf8w4^}MQUXOw z3luFQP_(Q-(Q*Ps%L^2(AW*cTK+#G zSfFSVfuckwLw4FfF_5wva z2o&uoP&7uUD;m+I@=^j)+cy6twn`}4IlnSwY?m_o%8GXFQv7gDDB8{WP_(-piuSNW z(VliF+RF|_d)uLCA3GF{vqRCob|@NeQ#3)KXg`6Xi2_CY3lvQfC^|r(XtF@jfdWMb z2^1YHP;`hu(V+rGhY1uNE>LuYK+%x`MMnt~9W79Fj6l(`0!7CO6dflg*I)S3=1&VGED7sOoD>|u5WmE!ETPnZq`s7eFD1Vc5QH6UON=sXNRKu?NIc9P0@n_MGpxS zJuFc4h(OV!0!5Dr6g@6b^n^gslLAFg2^38iD0*6;=ox{cX9bF$6DWFKpy&mGq89~< zUJ@vJS)k|@fudK1x}saUR4z?GY7gf-_qT?kld_`Mx|G>hR`gbv;<1}U(c8|4qIc|2 z^sXI>-m^o|`*tY$zz#(p+M(zpI~09vhoVnxiar%6`b?ncbAh5S1d3(|6n!aB^p!x- zOo5`W1&Y2ADEd~Q=sSU;?*)ox2^9SxQ1qif(N6+JKMNH7B2e_JK+$gkMZXJmMQ?Pe ze3^jMo@hvL-V8-U%QXJzQf6OS(LY^^=G#Kizs`rE|LjoIsU_~YhoS~M6gAqRsA7kr zCOZ@rb|~s>hoaJ^s47s@EKt-%pr}QlsH;FxH-Vy7fuc5nqIQ9z4uPVYKv8#rq8;gq|2o%jJP&AiNSM*nx$|4C!?a6r(oWDcS6ZyfTzAa_; zl@$$WDK@wx6wTv&C>m&oqCs{j8f=H6dF@a%pB;+kw?okab|_lV4n+&u6fG=Jw1_~_ zq5?%j1d0|DC>knIG)$mqae<;G1d5gvC|XLOXla3>Wdw?r6)0LxplEr4q7?*+Rum{& zNuX%BK+(zqMI(f|qJAxv2?HC|c9`P_&jE ziq^J6(K>c0TGtLm>)D}beLECwV27d&?NGFlP0_{zMVkl|Z7NW-nLyFz0!3R06pa)p z+ESosD}kb|1&T%q6m26=w5>qVXn~^b1d6s7DB3}wXh(sfF#<(n1&VeODB4-5D_X6k za&H1s`!D|_(dwaSO8$Y6U0TZQD=XTgrFi$AP_(D>p=d8V6zy$?qJ8X8G|mo1``V#s zyd8=r*r8}YI}}Z{DcWD4Xp%tD0Rlyn1&R(7C^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~ zjua?5N}%XyfudssijEa1I!>VIc!8o51d2`+C^|`~E84B4(&^r$=;*!)&hDY;mGsYw zlUvH{D=Rv^rRaZuC_2OWP&CC3MQ7Tf=qx)Foo$DrbL>!bt{sZbvqRDOb|{)^Q#4JW z=mLSF3k8ZU5-7S@py(2TqDuveE)yuaT%hO*fubt~imnnUx>}&<8iAr~1&Xc{D7s#t z=mvqJ8wHAP5-7S^py(E%uISX3%IXP7?Xmm~^=bYr%HJ2=+EQj;S<#&>#m*0gqPv_A zMR(hw=pH*1-D`)U`|MD3za5GmutU*B#w*p1q2^4)VP&7-R z=m&wK9|ekj5-9pvpy(HYqF)7yeiJDAU7+X>fucVJivAMnir#Liypn*_w(FPRyc3GL z4n^nMq3Aq26rFE}qN#Q$nr4Th3+zyIp-s_60!0@K6kQ@vbg4km zWdcQ)3lv=;P;{k0(NzLPR|^zfBT#g$K+$yqMb`@y-5^kOqd?J30!23q6x||FbgMwo zZ30EN3w1?jbgc|YKx*Ui>#nDSqU-Wgvv+hYv#+e^p0344FNC6doexF#*`eruI}|-& zhoT4VQ1p-;iXOH@(Ia*!deja@kJ%JGE>QG@K+%%|MNbJ7O&2J7TA=6|fud&xik=fF zdS0OD1%aX$1&Ur0D0*3-=oNvYR|Se*6DWFJpy&;OqBjMK-V!K!Tc|6#t7~Oq0#fV9 zzhn09P;`ENI^>`?Tn9g04)L(%7UDEh(< zMKkPB^rcPFR{}*d1&Y2FDEdaA=v#rJ?*xjz7buz~Q1pX9(T@T}KM555EKu}|K+&%P zMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N%zd~KndtEE{Cm^-f{HWvmq3E>kY5do<%)YXs zO1I+u^mulU5koo^P2K+gJ^jKCMV;+XRNA4aYKNj`I}~-XLs5$zin`jNsGChut3Xkk zKvBCuQHMZLO`xc|Kv55YqMiapy#$JS3l#McD4I>6Xm)|3IRuL46eyZYps24v(cA(> z{RE2o3lt3yD4Iv8D{AOgX?!&)+A_b?y0KgRKH8=|(iqsS%)YXs`MMSJydH|?cRv0s zTEGrP3)-P*Av+W;Y=@#n>`=6*9g2q7p=dEX6b-d08YWP*xIobo0!2#-6fGrCw6s9c zG6F@*3KT6TP_(>2(Fy`ZD+&~?Bv3S5plD@*q7ec`s|XaWDp0hVK+);~MQaEYttr$M z4enN1GXbexp6}ex8;ah~iq`5@W?xy+dfkd$-wZ|TJ0FTRutU*?b|~7&4n-T=p=c93 z6m4pUqRs43w7DIMwy-H0DNwYfK+#qLMOzCLjS?u@Mxbb0fuhj@McWA!Z7)!?gFw-a z0!3p4ipB~Q?IcjNvp~@<0!6zD6zwKZw7Wpj9s)&s3Ux*6bgP__fYkcr-*>%kDC(TQ zN!qJhnSEtN`*tgCdOH-2cRmzNutU*)b|{)?hob%MP&CO7MF-fSXtEuO4zxqjK{iDP z3ltq9P;{t3(P08bhYJ)PAy9OrK+#bGMMn!19V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD z3lyCqP;{z5(P;ujrwbIFA=DM^)2;Ga0#cit|M(dfiWX{3V@kI&`^t*W=~n#mZYVm} z`A~G89g5DkL(x<_6iu^3(FJxWy3h_q7ulicVmlOFVpDXfK+$CaMVAW{T_I3(r9jbD z0!3E~6kQ`wbge+qbpl1#3l!ZTP;{d}(M2|E-$X;bu+K+$x8qNfFlo)IW|R-ouPfuiRHie3;XdQqV0C4r)s z1&Uq~D0)?(=rw_&*9D5+5GZ<6py(}uqPGQ#-VrEzSD@%Up|0rOZk6p4klL{PDz*DU z(dYT;koUWl*;iKdakt{|k3!KW&WEB;?NIcY9g04;L(vy@D4Jo1qA%@G^pzcoX4;|X zYn!5P1d6^DDEdyI=zD>pSpr2r2o(J&Q1p{P(a!=!zX%llDp2&BK+*34MSlns{V7oN zmq5|q0!9A_6#Xku^q)Xcr`EV*PEmtUSM*`G%9RO7ZE${h<42+BmH}xrwwBpfR@Aw* zckVC zG+3xBYHF=~lYrDt$S+JQTI=`px6i*Sbl%o7`^t(IY%RKd9*P!nJ`^o%hoVL7P_(EW ziiX&sXfZn!4YfnjFgp}2Zik{JY>Ji?C|XLOXla3>Wdw?r6)0LxplEr4q7?*+Rum{& zNuX%BK+(zqMI!`?RuL##RiJ1!fuhv~iq;S)T2r8CErFu71&Y=Y>Wb!Xtqe^-YAfa6 zg0(;>8j+t4S+}*!zOteXTZ>I*grbd{4@Dc>p=c936m4pUqRs43w7DIMwy;CdNIMj5 zX@{b%Y>KuPC>kYDw2eT~wgN??1&X#4DB512Xa|9!9R-TU2o#MKDB4M&XlH?bV+D$i6DT@fpy&jFq7wy*P7)|OS)k|?fud6dicS+KI$faX41uC4 z0!3#E6rCm16^(DLJeYvg=FESIO$bF#{_hT3YngpzMd!B`AATK*raB*rrrDwB0y`94 zXosSU>`-*E9f~foL(!#nD7wrJMVH$YT_I3(r9jbD0!3E~6kQ`wbge+qbpl1#3l!ZT zP;{d}(M<>6@fz zvHZI0^Fq<8jcMH1T4rBa(L=4ppzlJ_!_J4IN9<7as2z$PvqRD2b|`wn4nDK+*F8MK1^xy(m!hl0ebR0!6O~6ul}?^qN4?>jFh@2o$|3 zQ1q5S(c1z=?+6sVD^T>FK+*dGMIQ(heJIowJFHkf~py&sI zq8|l{eiA79S)k|_fudgpihdI)`dy&t4}qdT1&aO>DEeEV=pTWie+7#E6DaD`7I)hz zY7i)D6ey|)6g3HTMW3`*PD?;)XXV#je;SHL=9jD$ZDsbA6*adNxBM82x;P(-TI^8N z)ec47>`>HdhoUw+6t&x-sKX9LH9Hh_w<+o&P}EbPsFy%dZ-Jsd0!6b46wNMBG>1UZ zoB~C22^94eD4JWKsGmSle}SR_0!8x(6b%$88YECOSfFTLfui{Yisl#UipsXi8wp5l z@BGwRwXJ?n|C9U>REp=hWbiiX*tXmL9fEn$bE zCGAkOlpTtewkcXhplDfvqU8jNmKP{mL7-?wfufZJiiQgmtt?P9LZE0BfudCfidGXS zT3w)M4S}LH1&Y=ZC|X;fXdQu~bp?vn6DV3=s4H5itup5?NzuUkaP`8W=m*pqAl%Ew3Qu-wzfmjC_5BwV^g%PK+$M{ zqU{8VwihVcL7-?yfub=2MPmhub`mJsS)gbafudanigpty+FhV%4}qdR1&a0(DB4?~ zXdi*1aRNpA3KWeO>WVgMtL%_~)TZVarfnRGPRV!sC$yE>S5`EstvK?JP;`Lvp=h!l ziVn0x(Lr`7I@k_HhuER$P&*VIW{0A~?ND@tP0^78MMnt~9W79Fj6l(`0!7CO6df;6 zbb>(9i2_9@2^5_yP;`nw(WwGOrwJ6DE>LuaK+zO|qB8}G&Jrj(TcGG1fueJTx}u3~ zm8%nw+S~arvHe5Q{Q2k6&TA{PudL{Tw&Ll(LeYiJhoXz@P;{{!iY~E3(WQ1My37tm zm)oJ}3Of{CX@{b#Y>KWHD7r?V=vslI>ja9f7bvb|`wr4n@z}q3AiAqUQyQ zUJxjHQK0B0fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww*`vc5h!|Bpy)k;qW1-g zJ`gDSP@w1|fufHEiartQiXLvOES`YWzRu61JratB=U0Y&+E!*?S<#HPVzW;94W!py zf9ZTE`pOPPGwo3HwH=DSu|v_fb}0JJ4n^PFp=g#Jihi&u`ca_hCxN1$1&V$VDEd{P z=r@6)-vx^P5GeXnpy)4wqQ3=-{t+npSD@%Wfuc_BakrhK27#hRfuf2)QIkMXAyCv= zpr{n;iau|vOin;*9djf&UxcEyW=o^mUS?leQP=ijYGWws=6on>wL?*x9g5oRP}E_E zqM99wy4#_shaHM~+M%eIO;K-wqCNsevk4TJXwK+&86MRN%h^%W?ZTcD_)Kv92z zq5%R$^9U3T6et=bP&8PeXkLM$`2>pQ7bsdlplCsXqJ@OIqAu-~hZB%mzx=IGOMCsE zevkar?85D3_LUVa)?R$v6pDsAABu+Ap=fbC6fI$gq9yH6w3Ho+mbOFDGIl6h)(%C> z*%U1=P_%+T(TV~^D+v@07bsd;plF0Z(JBH(s|pmYCQ!7xK+zfkMQaKattC*jwm{K3 z0!8Zz6s;#vw7x*m1_DJJ3KVT5)D{j4rs5Ok$}`D^iOam zhoXnGqG|1A_LUV~++N()5{fQyJ``PQhoZ~uP;|K+imtFj(Uo>6y2=hkSKFcJ8aotS zYg2TcK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellY?E*!22o&8ZP;{3-(cJq(UJKFLLO-^v#+e^iT2`; zZlUN&=R?s`b|{)|hoYzLQ1px)ik`JY(Q|evdfpC2FW8~zMVq3R1d3i3D0)Sp=v9HD z*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>WiryC}`aq!QLxG}?1d2WuDEdU8=u?5B z&jgA-7wU>0Yp?WeO^RmAKh^knC^|7e8~a6jnSEtNGuw-m+C$OT&WECJ>`?Tr9g4oQ zL(%tkD4J!5q95!~^rIb$ezHT+&o)KB2o(J)Q1qKX(eDC9e+U%)DNyv6K+)dMKw*w?I)pfujBbMFRwi<`F0wC{Q#=plGl_ z(Yyjh^9dBqFHp3AK+%E%MGFZOEi6#9h(OVzLS0d}j>@$ONbRa3!D;QN-_swPA9Wnk zQD$FR(c&G&vpqu563&OBCGAkOlpTtewnNb}b|_lb4n@n^p=fzK6s=%~q7`k5RuU*0 zE>N_xK+y<+qE!TnRuw2(O`vFXfuc18iq;e;T1%j4ZGob71d7%bC|XaTXnldA4Frld z6e!wAplD-(qD=&fHWliMhIUkDB_Opm^PT%)p=gQx49I33W%iX7ZP`(D^bSQ^IUkC) zwnNbOMcdh-XnQ*p?O=zZ9c_xn2o#MKDB4M&XlH?8aW`1$sJ|(l@%S*QEV|=C_2>nP;{6biVn9!(GhkiI?@hBN7kP(2oy~bC^}Q1 z=q!PvvjvLI5hyxWpy)h-qVolcrV12I6DYbspy)!OuIQkS%0UT8?XUd%iw+J&v+}s8 zqs+dtqRTpp3+4z#mpdPduCPPVm3An)$__2C$ zCV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%Vfuj2biXIRsdQhO~ zA%UWY1&SUKD0)<&=rN(L=#q}gqX|fDNY@1C(ol48ejxktjxzhoil%oIpUxGEo_0PI zJ!6NWXYEk*oE?guw?okjb|`w$4n;57q3C5h6un|o^r}G7YXU{D3lzN}Q1qri(OUvV zZwnN?BT)3NK+$^wMehp~eIQWup+M0`0!1GS6n!F4^r=A6X97i^3lx1JP&7lJ=u4rl z=*f;swQo{%Mt(N-sZcaI|5W2w9cA{F6@A-L%-=5*edl~A`rZyjv+PjxgB^-~v_sKP zb}0JU4n@D%q3BmT6#ZsX^t(XO9|A>x3Kab%Q1rJz(LVx3{|XfSCs5R>7I#)DY7i)D z6ey|)6g3GH6#_+_1&T_6qN+eqvp`W7fua_HqOJl(-GsWLuRAL1Cm^-2Iue|3LQ#=l zG22=zv#+eERx9=%5Q@4xABuX|p{S=Fih9|hsJ9)8`q-gpHair}Zik{d>`*kPP0?He zMSTT|<`yXGCs5R1plEvP02uI~1*KQ#3-LXcd8?RRxMx6DV3;plA(& zqBRAI))FXMTcBtifueN>r+c+PJwzWgiXgd^bXNRKg?NGFX z9g23eL(v#J6pgh*(M~o+I|~%;B2cueK+$djMY{_W?IBRKr$EtO0!4cZ6zwBWG)|ys zUxA|W0!0%9iuMyInkZ1Tzd+F>fuaKhiY5yb9Vk$AkWg2&Rjtx*-lXW){JQI{L(%m7 zQ;i4L%IqsEI=oh_Jbx%U!ue2iq#cTmvP03)b|^Z=4n@b>q3Ad}6diAeq7&>;bfQhs zNdiSD3lyCqP;{#Bf9!n+cvRKa_Bk^-nE^sc0!)BF8VCaEp{ZaxnM@j)gswvpLX&0! zN*5FbMG+Jf6%~6|?ATGjUQqGc5wBfQ5fO9MtN*+9Uh8Bg;=RQ0^Z)K&@-XwBcb#3< z-uvD43^Sslbz%?|trvr+=pr$QiY^v|sAz*2L`56LAS${<45Fe-#ULu$BnDB@WnvH& zT`mSu(G_A46>S!SsOU;Dh>ETfgQ)0gF^Gz`h(T0zjTp3w&WLhOfk2|J2ep>7ibj#7 zu8ne$zKpJh!%Av%_dwI|49BY5@C5L6v|*kVcuL~-T!)D;!m|sDs!pEIFr0Pv48VVE zi}9R_6kFgAJ8YYbzv=kz+m*y4Gt-Y~BBIHwuL%^vRz z!?@jZ;Y`EW>Um?fVch5GajIc#^VBpN#-pB_<{QR#&)26L#!gS>BExvrvv7%Fyy$si znPKeqSSt);kH>eGVZ7y8f3{(~=XrCLVeIqtJkKyb_SBtk7@vD?S!)>kJ>RY~j02uQ z7aPVQ&*F`S(d2pZQp5Nq#&tRB-;62UOi!3%F1`vaV8*D`bIa+DP(AU(gHe={}M$R{5=!+uOnKAS~{Wq8~^k20%nKAT#Z8w`S^q(cSm@)Lf z-L5xd=)Wu7Y{t<4H@V%6q5m+j)r_G}eBWor&_{N+nKAU4%SX)^`q12VGlo9(w9|~C zkF7jw#?a>uUNmFq!SQZ0hMxTGF=Ob_&0A&+oxQ(j#?ayEJ~M_+zdkl&==kDuGluq` z`^^~IKpZe*Xa#u4jG-yK$&8^f_!rY?J0Bgzx?Xp=ZZD(ngl9#@y9}e4jY0yZS_qfb_+VD znORM?F|a}SMr<}VI%eivvaJWdfNbyJ1I=dUd1OPQ8+YN=b3iO?gF28mT};D34H~`X zc7ScLvKhTjCo+V|?da;}&<+qZg589onZx+btGz&uV{!}mdpwh^L{4CmP3{k8vNj21 zgeE=1uo^N?ROEd)@+MxrzQ&khX6pcPgOMjyL2`--X;)Yg*Vi|6jW2{gj3L5#R<9Cf-x{l~V|6)NhPGtwed)YVBpj6u}!$h#kU z@60odIP?Q!6XGt_Q5*{mBkp-l<}OJl`nP$-Dw*BG7oV(>Sv>AxI0p~be%>bDNH`6p zxPd%46Bp$Ceu?_${QE`_H+c87A@ZMYJT)x1F+l)Bm{%<;tnP$Y@ z$;o7;syYad{QJ5c4=zwHtbS})B9aM@e16rh-!4+=T>4(q7mJLzuBchcd#Xfw;Je2^ zM2JyVwdWh z=^^hIUjFDA%G-+QGU&ttBVmJ+%fAH|s{9gr=LH|`Bgexde_ej>l?#;7n1KnBkEdpWeKgvVeoH zY}>Y2Rn9*jx%Tx%MnZqYQY}=-Db8w6@nuf&T1oN!D{lHxr+E1DD}T^Vci4ARtV-~T zwby;R*ofPMNcX^v2XrJQoKG$7+Lw~heVgyvMhRIF7sSp-bZFOo@9fShohR;H_sL=- z;bHU?<=E4>pmOz1XWhFlST<1=>mQfge>>_Bkr&sw>Qv-&o_zKDrAFMxh(pzLoQ{L) zNpPdrtMrb+1>GBM--|1OiLzKDStQ)@+FX^zo+m!I?+jIQk6nD>7U&c`i+`Am^sI<(xz9%%2{WU(O zyXJ+Z%8kN?uR9nClMq1_;#ypgKm9Vf=)XMi#AYgbc;qz?{(K{~e|Y4X7v20Y3Wmmc z?X^t@p~7NJ3FOiVI+nxzgAq3oHuA1PQo8xZ`@hqD@YA2xK7{y4sp?ZPIvU3JxQLsH3vz9{PSA?jbZ|?)s;YZp@4@JXM(%e`-2|1| z%|Bkg3S(O5PTH^6brf?L`YlZ4R(KZc`{5Etlq%o3AK&+u?qoB6w)DtwNpc4IMt?+6 zKBeG-e2Tj^O1n~`6A6!e=7sM+f?UyTOAFq}Q@(^H|E2}}@#-Bfp^nar*1iOE95V+) zE==Uh21(|!hkv<1SN1>ef9WnnM-{!e_J^OSvaN`!J&$%V61E@`c@sCYi%#%v9a~lU zGT11^kG0K;s0jaYxGLS@R~}wZUCWBt5LJGfN^gsGX@-$-CZb?TW+a@0i}tvPyOk4e zJ4jWLN*Fn-giqAA@W|gb9ljH_g%aQJ#n<7=(+$t;y%-IQ#{A&6^X^_~BN=7EA2&-hAOMc!StWE&Xvm(B5oX}QfGperXIF-#87oS{f#5u4QqA1HG%Ih~>d4aBgl)n$@qOy7HvdjOb zt8dQ@w?6~*_Txx*>qu6_&8Obrq--L;d~NGU$|myb^Y3azHsO(XU2@Sm3yrvZj`FGG zbNB0yKR}AIBG>MJ4NDFb=b~qB{hlf%;@hXebtqu+l61bCACwcY1|~Il~Pz((KbA zx}CE_j}FzINV5}k?C5Q@Yc~QWB+%7xb~vux@$H7S^P(e%@f}QH)*yo{;bEq;!-#h6 za9am6VRZFFtXO2{Ru`Dx+o%i7yKOl^ODEXQG`-OjB_aXIr6NlEj>w!+?htLZYuB7+ z$M%NPEuOS%*S=juyP*i)$rBPP5}|_pjbh5VMRSs%lxJs7Qr&G%vI{54p}HcH)$E6- zJshQ+W7Gx8)-5Y2&l9_y0NHd`rNO-(DdvgY#G}65ywQOt=jXU>D6AhQHsxJOKte+h*>vPf16L7~fYbWKPrFPG7FxjD~>y_(2sZCIfUL~aZYu@{w`kJSl9 zC#2Pn9i2#-Ht6U?W(0>Ajh;ImFN%H@aErRmzWQ^_QS>6aR4QF--|6Io%0++o;YD`{ z=fN}67y>=C#TjmESx)U4jJm|C(m!FZw$Ie;SqXR>fDCuv!>6RepB;G7DVfQ1I|a8xZlzA2 zT{m<7hhEwHjK<7&*_wvHW~Pjf0pVC&P>y?qW|d6GQ*uyO{&KUz$*;>jJAeUf++AM6dKo?&%D zs19Q-E79suMA=2B4xdV1qz&ZEJNLo`IYfm^K&qXsC^98dT6Q^)kg|>;F@2Om;vXcc zgC4ER|C|0yiPbFFDk;aO9c9zTB3Dleb#;%1ezB(RP6rl21U-p;00Yt=~Mn{86J0hwKuM+^C@m{PFmd8q(uhnLRaA zbk8739bK*v9<_DCxX{cod9+5+!+)21tAtFs9o-!9XC&6Tv|ATi%_YGTRD5qMD!5}O za0frS`ao+OPpvUr23?KuBaX78>*|rnf4*m1uRkp4=S|{4pg>IcEJi;91D)IkMk(+4` zd$gMbo)%4hHONMU{f5PI5oAa6@i~ZY}4C{h*j@&qJzD>n(j(M_Ah_XPmgLARdM5+Pmr+I zRXK2h?Y)F;mh-4y2<9eNo$XJsx`MR9Bn-qUOdISvyN2Uvrw!^&-%7B0<7lTVnRwa! z2gd<83eYhm=D$o-2Terce9VBI`hP~k7;TPN4gVF7rAkWvRC&`{73(jn_7SaeqjgTV zF74KY?wxjY;+;zB{VUpDwFe~C5=9d&?ZSiaV1b)>nH<`iRi2l zCzt&Qa92?Zo}mJ_$4N&&n5jl+@$`R4Xo$2u#_8@fPPfN6P33Nnw$+%}sv=2jAIBbU z^-!s4`>~0-Hu?05>*v_u+DuWk*^?sqtR7zS41X%MzqBpH@w8SIR}~ZU+<$xh=@Pfc zvaB_NYF+5oiS^G_ki;r!RXP4|Dg9q2kH0qI-~pjuZ>u|oYBfFt4-1a8&eU!H{g8;G z^HvX}N7d8SAdF|Fj9hheI>IKe& zyoXZkXbt3HNl^-(VNu{n4DtgB)$Jtf|B%pV(?~R8FB;?{G05wpBrqnnsz?&s$FYZ7 zajIgpJvmX=CJ*vlKgq$hnWAcw9;!w9tT-=uMuU7Do^|(1O-t>eT-9lk%T(!tl4pXI z9^TdJ6^mO5R-B1Yk!saph7VF(Dl}j^XGsqNp%AquK_d>y}~_K-(#&f?3*Eu zzK9b?vihS-ts<$%*6STB=4KJLE_zz4I#=sLw{9$w;{TO-NJsrE^JrbEgFSJibosZP zu63#Z=Y$R}=f59X{!{!us>xT)#qql3sF(M)XCBqBp}9C%G1p5sm&v0)#)Zxpxzt=w zySubBE3p?i&-H3<=xC|A3U?Ky;2CNw*aZ_MMe2fecp4!O+y5?>k78lQ?SkPbk!IZH zgc3Nx#8xFJZj5MEtpAYEe?>*88dlYsq}oSUPdORtCS*=n)E^iBL&cxImmbB2}idEsW07Nc*T4Rj2=T)O|-w zK8@SvXgXf1MWK7b7rVPq&+8(~og;VGgg+HaMWP<+=)*gjf8D!VGl2Z>Ek`Rxwm(-@ zf1)^~q(rRM6Rjj_PTkWmoQ5>#5j2{Ftw2_smEPORinWqRl@vAFN{VYuDlNLXoVaKX;Odv-C5&ft>Yp^L1w8FZRBFz)@oJBxw<&!n13i3DerdE#IlB2S3H6FGG#&cu zp~|R-52?8>Fv^Q~J&@2C*cT1RWh@rCG=H0_SX0dv&z3sM&B=Q3{?x=L`u}R-$!G zPtXK)>~M6kRHUQLqE-IafkP-?2x z4JTvNfTTn>dN znL35$%i*e6$tvBWED=RkCCZc%X$wk}DJ9Ytlqge5)SRXD7hMjw2EenSiPnH#C=QRm zM{XF?31>SwKW`|e|Esd8eLU5%^NBM~n0oYSbaHOOX_@J~(MQc5#FwKd8fy|C)seBz_FzeW`PBgd_Le_zcGc{71J!e?_36vNGT; z8=X_)%@5>Mj;t;%D62B$MrncHpEI%`P*q+YC@C)+X;c=B45a7e71<&3s{GZ6pI2U5 zQBqKakkw^g4p*306sT)%R+ss!D=NzAMxeqwwxA?X zSYBD0Q>Al6QlY_fOUmLI!m7}~;ht3=toN-xsz+au~&#UxOu)^}{ zvV0Y6$j~B%!$RDwEbv#9!$X}?7Q#qfknaVRIsPEerQS;YBLlhBg@s7p?;T%YNBLdJ zyroo|Dh$!ftg=uwLqS;%XueTi=nv%N>tqJ0(BxTRP{9kTillx66-DC$XzNn6 za$ZiAx4cZ((=asN3Jhl4#1$A$g2z);BtMj350V*nh2;iS4mD77)>`jDx6u%&l0d=Oyn=%K zAeXs9Fv3>lV1)1$j0+Uzc&V358*&Kx|D$lNyt)z>=wpQ?-n`~fU#XM^GrQ{2GwcqI zuC6;E`rqXFvt}){(^lP~pxhhUZM?JdYv$Di^5!?3R$qnx;%W!SxLjIZN$o=er%p3N z^_ZD+W>1aBD5h*#l3zM5q!_4Fe|ht~Me~4tj|bw)f|3F?SX1p4gbGVHJyil)*ITG- zNqaCjC>J#lQESnVr=~adGDJu+3IuZU@~SIy@_0azaM?;Gv><2um-po02YV zH(41F13G;*&wp^UIRG-vt<1q3&zhnf(K^9>3RNZJZ%MhId-YH|Lo|b~!Cbj0Pz~NV zed_G`$?^CZo;SzL)W&udiE22 z!{X@+D^k+q=_@PJhGt~N_iL!1Szpswe{6j6th%}Lhu6(%m{-3bc~)j74D+VVpH&N- zGILJNykvae#c&K1lgWUPQ|6vFD7kTN^5pcvu+%ivO&g9cz&LGa@~o6u_zH~ylN;v_ zm@+p$d1`!ec}9FPzFA>-9UMrWGONC^v1V$0^33|#Q|C<^o(7Zdh{>cPFsko))91`i zZp3#_02^VOjJeF_sv3rbh*ar9&p@=wSB+dyR$h&9N{KXdJ#J59SkmR>dP}_Ho7dE7 zkTcJnzWRmU*^}!Rs3aispr&pf9;lDm@@!T)rX&m;Ral>>2hLzi0#bb860Idjtu1sT8dC1e&4 zSuK|$rQGtdzl)Jqf=L3?E)8Oo4Hl-PQoFaLr)7jN^c{psA7YQ!XbwBk<~pM_Uw|u4 z$H2s@F3{N8fWa=P6;!J?@9kPF*?G7Oon5k!Qhk8F+oQgrL8pnW-VvP9V|!&m9(jd@ ztX;UYj3I#rl#j}-yz%3^P@0#aG*LCL->})`{!5#8RSUQXsjRdigVhb%YpVcQjcY@5 zqo>)!fWDHkIA~d^7Q@&x@rn-JUZ;iv2h~_m1X`tHpi^>DL7O*|_AYoZr=s_NlB=Ep z3Q8-2Hg$P)%n&@^P*H;Sq(x(Jl9A`bn5znjZWiR0bPHPM*li)k;0^b`*xD6(3(G_I zoz2S1&&gBY-4e18w$~=V?>E?n!@EL;G;FB(J^f$a)e=m{4v^%8+HT(Xh3@A_k#;8#NBkAu z0Po8wuIwXo?9?znNW!#o;ykb@=Bsq<8EpT8YM`RByvU24C7PlPi)oxxNR~<>c zi&gD-h#?Tbmk>3do1|k|jttaJ#NLib0yM@2OHAw{l){{R9P+f-Ju4AVt|Os!d$rTN zugd3XH61$;DH>|Q_FC4}!J=0R&Qnz-K9FxMru`g09k|(NHRwZjqV`TNCs!T4**AhJ zva+D+hzoEvO3Id;JkgssislkcGFske98i-f2lKaFvGkOld1sA6QZ8`oMlJs6J>aq)ko0KgL^yJ3;fRZ2Z!j zj}g)_G8>K4uzs?)(6r4{8DOeb7qqP-gWi3qTR|NP%kJhHqT^k4219EVoI39m^(X+6Ul0NsR%i!a4wYh9DGBvMW^9%l9{YnxVSD-iAvcn7=U8s9tc~pS&5*+91 zg`)C<&cfA&KH)FT85_tetK#X34!G4#I?R-^C?9`63+uh01hP*ARrKZ~^K=~G1^3$K zLnbPc_Px+sf<<8PaYgeo$nVeNM@b|*C>04*ANz#Fu+!nu&DTPz8FFDUUG<0_^--azov9@&%W z4UXg}F|hK5w)3&(30e%vP5YUYOv-wPqeTYy)t*haIGq4X+QBUz@(_oMSzYEUD<7k4 zK{iqJ6oAszdlE@07iZphqNkp=gj9c82uoK{Y4;=%gO(~GCqBVVI7oY*j%buK?X*VZj9QgbNo!T~CajD8sK*8!C`$qKX)qHcaz z9*8tQI#7dS@UmAq95fSf0KIs#Phs^2i^9q#PM%e!>%(J}44u`g3%&3cS84PQo!IOi z{(Dc5gc>013d}3XDXj=PT+{7BPaP@U=ErZ%TbFd4|M7q-oiLqFW3_7`gH=uib{J!^ z=@02nLGI~#(A`wZBfX8f3LbQ~Jb+cJyuzH|C6vUFpyWx=jtDa>`>SUkx~;b^l4XV7 z58%|%t`{XNj83*8uQWeoQ;dGXsWxv$f|c1klG7=C@Y6AIR~K7Vn;fZz?o*nRzyn-+ zSs8S=F;osW=rOA8sdAl;Tw6SBY3}TpnSut4^t9&9D<1swvpn*P_Ez?mPb!Pn5^733 z()OA}L#mT4Bc)P^RQ!RWf}9H5MX3UPgd6lJ2EEHsbrQUGR@>1rcrs1T=F9nEvpA$5 zBG8k`mh%fumh>!N#yoizEHQISa>{(@=mj{+Yq9L2g0u|Y+#V(6c=m{42PeZhWkE-V zG%kc5?&!^x-fM(R$Eu9YN5=a3h&a}~=nL6OQS#7#HHsy^Q8Icfq^@MF)+erkfb7>L z;h>42sM3d~(ml|NW^X<^9Fv110U2^z#H5obnwNF`G#}d1@uwZsK3k{F=g3Oh>bI!g zknJw1Nev&gEt5pVwY;1>)O2A$tt$-5UOtH-JGFFu+)L#T-j->(1g&jo1E@zSI?|-z zdSs9sRlo7Kd^Rh0x#q+zd)=jXQIuLboqS4gH5ZlTG=H#y+OB0KR0Qk?pH!bMXBo+B zOnIe`XGnVqlCIBjB|D5S@{A^QTUUtlPT9E7$3cvdd3ndh_oHVFISsSo3ue{UPo9kD zidFJ`+Ul``d{6eVfBX=FzA7BwU2gn_KYS;|k`58=jiEu`A5LE%p4*}K$~I@a&vC5^ zUu~TmcAj&MW38FnA{ZH)@JLr_ z8)sX0R9I)Ti|KL3nBC0oW)Cyg?Bz%_@k>y@`wKRO8Q=XD9KcCmC>`|Yh0 zcHwk?pZ$IP9G@y%{ps|d#Sb+Ir}(|`Qxn1|{_XfFGU0STjJ{uA{pt9tJ2!K>|6&lQ z_(k|x0{y4+zd4Aj^zn-aa$l|porYadWp)~NL7CeHWo{RgxvC9yO>a)aE*Rgp3&tEj zdl2;JH0*-%{VoQDpjIbMMxnii1cj%v6tv)DTkz>E_~|Y9(iVJW3%;=hzpe$py9Ixu z1%Igpf42qyq6Po41;zJUh*umH=Gi0$sTg~8mp&_w{vE#LP3`|dMg6`p=u+8WZn1O#r z+a&zv0%33cOA5pvCf>&|p62@vsLQs;;3s?taeosb!r#g~3gZIV(+FW-%X~l3(bq8Y zok09b#yTLSvzZX#A0|Zjy=?!5d19EpPrv0x;d2QQ?s>NFCOp|UhkJ?; zd>r+b=?QCHpjVQwnz`VSmH8h>?DGtnC29c!v<-a?yPW zpCzPpF-}qVv5fRHUljf-LWCZ^PEYYR5h5P_jupk5hTqX3`yxWv>DQ>* zrlOpLY4|-4zQ2v{ZzoJgIQ%>mrTZzyK|%+9Y=m$IzjMa>Fj58Qd zWjup%CF45AYZ&ike29_8CdzLY;|q+hGQP?9KI2D>Uod{l_ygn5jP!#dlrDaaR3UzV zRADqDer;6oIL1DV0~qnsc`CEp#ymzZV>x3r;{?VU#;J_67#kTEGM>SBHscz` z^^BJ?UdebJ<1LJLG2YMk2;-BC&oI8s_y*&9j2|(6$@m>(6C)O5s{G+J-k?6)Gj?X| z!I;Q+EF+Cq6n+Tf2*v`&5=KAcc*YvWX^e9iPh(ulxRP-VBmH%J2aKOGe$9A@@n=SdQ|I4?u@j?*u@_?>#(|8PjK?wNFcvYEGmd6F ziE%RHDU1z_3mKO)u3}uvxRH_O397H_7;j~~n{gZC6O2zYzQnkP@m)sx-B3#J3&sPC zKQjKxXocx;5scA{-5C=Y`!S|64rUzAn9t~AtYjR=IEis8<7~$Hj7u2LVmyy=J>w?E zs~K-(yo2#R#zz>RVtkH~=25DTHyQUbe!{q)@q5Of7){K(6wl4rk+CadPsZMi$&7;; zPh>1&9K|@Ev5s*j<9x0J#^pCI34RA;`15TU>!sJQpP*5jv@XK<13ip ziNDME9o8kp|H(KQ>kQ&~j7zYdAbu|6Q`o~0e}&PFH39K1jAe0}Phi}Tp!qe7?<8sd z8Dso0nkO?(!2*NQYh=6~Yb4?iF&@MkiuiAgL$MGcUck64UGp`JJ2N$Zm9Z@rEEL|u zSTR)dlNc{KPV?&+-#bC`FBlU~)I61OT8`%P8Sl)~{1L`O1)7_M8jmZ|h))|TKb9A3 zynylP63t&{j40Q<8)M}t%>#^^{F>juxEBj9D&JR(y~k>v&NySd=BG1mov8U^jE7Iw z+!@e#LXAc*@v5sdzm4(ZEt-GF*#A1shcM2)LGz`I58R~r4#r<@(Y(#A8gp;gSkAcm zPR%zmzPwfQcNsh1t9b(B`1>`V%DCl0&F^6R6bpT-pYIt5KC1aJ#)ii=KZ9}GcFlJ& z{`!>W?RIF)-=%RB<9W|$ektSb=QMwxvFnSPCoxWZS@Y?P*Y4K*F2>Ja)BFdZ3X+DN= zU6kfmGXAZz<{vS}dNe?dKZe@Ik@oPpSRmU5|IE`^J<5tFp7{6vT(saBwjIoTBj1w4VGhWB|AmdkzhZy_e z;DG!;o-vfljNdaJi=Tm~_`?|+ z8J94g&A68FNya^lF8r!G#qY$}jj@z*65~e3s~GQL{Dkov#vd8m4btgmGkO`9Fy77h z5u*pc?oECaGoHbC594Qy-G}IK<&0+#qJN*ocs}Dg#>*J5WW15_R>pf7A7tFlxRdcE z##b5NVcg638RJ)shZvg}P5eSS`DZb9V2ony!5GKbk8vPlTLWVQ>ZJo?7shUk@r=D0 zQy4QChcT-2KBO~-`2@yV#wm=m8566bH@FQT}+)HhHsT`0;4+5LwPW)C_B27!V!$QjOC1e#z~Bm8D}!iWn9X*f^jY5 zMT}Q7s&hKze;f0=7$0O*=XAKggZVRz?=ybL_yyzFjE5MT7{jR^V$eUiJ^-qmI8IRb zp+h4*j&ooShoH)Cq%tr6Ekqe1m^Bo7$BA2IAEQuWY>N?=6UG0i41XA5SCoi}E`eFYy7F z#yZTqgD`H$pInWHAvnE?hfU)^v`&xoMQKucGw_l)xHNWEng;1m{^W8A4028P9;-49 zw^UltJ#6tp^38r3vA7)MkL0^1C=M=-U87ASo-X)L@>&HRT#oGBrs@||FYWM>^sd6S z#KEQU3DTqfBY$%5au|Zss|ZRD$1!$#TX8LMD2*SG-p@FXkUzP1I}E|;O+tE9ujF4x zyu`mpaZPbZ5A=870@HY7Qoi)J z8?RvhrUjK3aEFUq$QUX-Ww4O|*K zA25w*Nd#OjBU^-90RO(D2>d7E$6xx8w82BuGKOYm;5scWJ?MS#;4HB8 zp+o3ieEg)gXB3na>R+SRiJEvqCh3yp;};aeSGv((KcgE))Z{Ok%5N;$)3mLo>w#Y3 zIR~ygE3UBopjo$~aA(uXwDyHteCrCgc&{nGrf6rAyXLnafBkJ*($&S+*6wTyOTWsu zvuR)29$Xm%etzfeCL^uLit|(kpvdXu*c(wOjcw($0 zTTvmsmmf0fo^Q%ZTj`ru{CrdIH2;jt9KY-#tG{l!&tE&I*gxY6Sh^&=UYmV*YUWe$ zcZTovrmzH~|IhCnH?32`jwT~v(KLF;{fupNWj3kzq0{MlfqLJj-ka3>&>70E-nXgu zCiVVy?GB_{*_`?*zJvRgQOb)>DL=Gj30)N(%uMf{xa|~5p-H_DovBh&@7vUSlX@RI zOWD=?Huc`5-hD+oP-l2;-_f+s=r-w{+QG%q)2=qD)Z6{9*Ni;4+v%@ON4Ynl+(id> z=lN@s!Khw_qel93jU12bzPP>`_MF4lMEh%da~xfJS-2m^@rn*pDzO~1{LnXke{BrM zEj;)n^6O&9eHr&6IbQa`^AVu#U^>VlF=hgk=?5!`X zyXD1wKkuGtEZ_a8u{_Q=e|f)74&&}_MyDsY8_Pu@!MT&qTf|G{^Ofvn&cXH3{@Tmf zvrwPcBG$#YLp4i2uPgW0E}n6@W5@T|<9|YHH2Hs48sGUvTCvNWKi53d zwELQ$r%!O0-({Xze&}WYisHq!y2W(qmj?gdhJZ;Vw0^4-@)xFbVL$`8;kd_^y$93a)eHMlY8;uc=B*%;bdQZ zalLm+(KAiPlVqV+oo{mSWN$r};TwOI@|eo56;Q!GW*;t&7H^W0#@pT$g{U<9@IWXk z4{=DPqoB2HTvKXVi^Dm!d{yFMU{vDrLsaL3IhM{hgX47y>fy%oxKM%NWnto3S6`K!xL#-l=`!P!3XibDwI*zUr29v9INa zVp;DLt4x*AC{9p%f4|e;etiD5lU58VKQ?{%gjb76zgwX9f~*5SUEFhB+@LLKFF04{ zjU2LL?CxYoRPK!zENk0sOOG4dA{=R4=k8AO*Uf=9H2yV@1E+BQGjL}bt||9vxUR=_ zv(L30M~?$FxPKDIb0F1|edAf@7+usDoPF5g81Jj{E~;Bx>r-jMVvP1x6c^R`plYqv z?32q6WJf?5X?>FLzoWfS;Xb^!Lw|ESL9OjXs})o`ImOS`P+U?(5$b2S*N?O>2g^Cw z&pE7^?veMy;2r5fyw6nOsKivOsVW?$K_fBx$r4g#LQ;CsvCzGpzv?Z=PrID@%7L&B zzJtq4FqY26YeM$ny~kxA&TZp67?0i%yY-o-{af%_hu3nv_TjZ1FT;0m%Ur_4@${a3 zcyn4eU-x3V?&j^T`b;-p1o*zR?1Qel#gqKgCK$iG@fy!>$m#SCnu^xpwH&W4@ss-P z+r7tFPUBzj*tNR^W7=xGZa0=wdy_Uczuu;1;(+t7-F?UYStZ}>-MQRpu2?yt&$u4f zo;y2s?C>1FY9sT+_Pc$BxrLj&o0K=yqm!mxQfv;m#CvJc{#ShmvqxnoZ7fEubiylb zgD>xJrb%N%_aqui>=_2F^NoLvcXti72h}r;SF6f>GV+ZL9{J9~$aj`^rEg{E$hU$< zKI6NctMU(qC?0c9^ko-kdvij@Tu0&vUs_PV zqS0`m?Hl!zV{PBa(>`{Y+zDyE#G+9cW%5+7p_skAd3OICnAF`)r?1arr$VD|XFC;& z)v38=4&zr|>{#7=Z9`&(<4*s5#uJ@>eCE@ySA7=$QlGA$3@QDw=)v2Kmr2La>xxB> zK9W21qt&badG!ZBOj|W*1L=47G((MV83W#R{+Rs3ach_FIk10ZA9H(qWBK+-gU2-L z!{p7GA>J&ry;6zTf@`yGqV36e-#9xJs?BOU6^d1{z{hNg=V~LSn@R=T#SD$MX2Pgv5#p ziPb^fqjo7jbf>?ax<@%vZ*{4AYFx*NAExfnDB(bx8O4^GD`~#N=Ms5MM`gLgPLam{ zTkI4a2{-v}87z5H?yIR|T(GEdnMA}bc724?;gcGk%nMNMprry6&?*pcjWlXUhLh;+w`&a6Hzzhme-W*~^-oeax zmCg*B<&E^OREPnm&~>Mzkh$KUQ~W}Wowf>bn|l9By$_g4afUXht@v%~{VVl8U>1c) zZ4NQZ&V5#Yox2J#U^a#8!MXFiF){mK?U3>V%d?9P-rv{@Z5WGjJnYmbn|2#d2G`2$ zzAB~LR2pBY_uPZgN&V(TmLgTmk~=#^PZ}@{>;9=%m^A-wpBU?lE$Ug^)4L04Qk!D! z;ryy*SJUoOznVT4b6?d;j6_b;dx{z}X?)z?##sL3a%1^E!&Kwp*sOg^ufJkt>}U7f z_wYNXCm*+W%`LBvylqm&mh8^w*PZaz4Z1a&_-Y)dSZ0m#TZZKNyo1`4;l}jmBO_!s)*G+<$m% zaGt9A5A~*5zS(w4luPqCO1U(TqtuV;>>f(}tj-tUTqsp{{3PE5?st?f^|Uc|%8vMP zSY_&7DPE5Dl?Qtn@5eYA+;5FZ<-UmJ@%wZfvcWp`Ni z#kVa!1#8T4p=-?fA2d}hk1ogiy7)=Sn5$|0B<($!jWy-@(BC9I=ZY3-4t{b=^IEg< zi<3&nUlw)3+nY{ab=++|rqWt-+1|?Z`fhKmt{#+I>eFk@;q7-)oT4X5$6J)jW}V7-M*oCqjzJ`XX^Bc zdeKKUJDYZo`e^z|=tZl}L@SM1-iOwz-IFdTT2+iQq`7!i;2g=W1K=FxBhK#|e?xIykf(Ew=;<8g>73#@-noC^=_&AZ-|5*Z z|EQ#?MJN5Sr&ZK1CPC?YYP6E6XHcD0sGdOmf_fFcjSsVv?z=Dhz3Sd(+@ty|uzNDG zTy>9nF|85xiha2M!E2n_bYM!wQGksabS>8c(RyRr%;7H8y#d&M%>ey@Q+dXWrX$Fq5y(T}KSE26s z-o8lg)#NwDY+i@bimr`a7d?Em4$XqLH~%zw%~Kby`}^2mCrpnId*|%OH_pC=w7z@a zpc{_g{Ou`IdNi#G8?|*YtxF$!cGkl${Ns`H0_*NATojj#$4%$2pmnM2y?0MMch<7g z#*U0nxxeJB@{>LeU7J#^)2MfW?LT>Vu3hUi(x0R5k@qWoXQ?~Xjuh(*+jok!#I6yF zwZKjhqpzJF#cHtAqgZJaU;LcDtE0!qh_?PGH5M@(?KV`;+xymdoavdY?p#|>-Z8? z+@le@z?UCVitLb53|IHmC{XbeN|HSWr3mYsbVBK1DFt><`zkuC(*h|4DJLbU6gh|2 zNB6hOfm1m2r?5`6kvz+tM$d{%+VWd(sLY`@HGG@&jg9ebv?1wb^DtFWuhtn&Ph<&yJckX8a9f-xyGL*M=B(-)FZ>tzWe|=C>bi zO>VsC(@qba^tuD5{Yk#w#l5|KIJe%M+gr%(na>h@iN%TDB)-=ZYe4e(J=}ZfvtGWq z;y7Or(&)!dYl;M>k#b%`P>2GdJoB&u2?(|a=?g4uJb!1jO%MSYPo*Kv!rlW zD!g^M&O!2S*Q2nvaeawrO>JGvkwQDyb9fFO;o2FG|Ip(40iU7h;EIaFLpay{_$Wpv zmkTLJy6C@0MY&!{FpOx|O9<21^(&tGb#X03$gZwS@RZo&TAzeR>aKTC%5JWWsJZU0 zg|PQAnC?eBpH8f=97mI^C}#&99v9zR=x%r#l((zIM7d zqB6d5x*tVteCu=?lvfUWth7!z#rxwh5V|*+(QtdI?O#A8XXG z=5h~3wy(R~^#6tSxZLlAH^Yj{w(qbQdDc8#=o8 zKxj91bkl#IS{?1)1%aL$?S3E8JN0$nkB$@B*S#L4o$GPe!k1G$?&INEgU3A>**1FI zZBfbdJnq*}S@S*a4rqtdJZ=*We!9nf5}JR3$Ne~JaG}S2ER?&*<94E!7JJ+uq1~5w z-0!0dOFixwIJnH?9);*p5(TUM(tQCc zx$aAMEy^(YOZU}KUHzBtxhTVwFWn>H_0%uhT#tKmBTb{tt!TPa=^_CBs_`_sSb|iRqeE;L zML$UW9J*+WGOVJD=TPbE1Gq@W#YJ>62Hsvw7aLH(4RrB2%Ds^;5|PEiI$WHDs#`=C z15qY=j@~8;Rb!}x#{8- zthMBt8eaR7lk(M27?MAF4vG%w9j zZFZr?qUqv9SUS_iGic;4bPrI9@tz9dvORWv6&X+mnz`*lg3e1-#vbcuPZVL@dDte%8kf zKY*OuhmpNQn01Ub9PQIFH_fp6cD(|&Ff$G`-LU#G?FE`)SjRH$37TnG{h7vsW*OE1 zraeFh8P-6i-9ZN%Rx;CWphFBRg=q}vP{T@P>H!^QSZPeVf~Lc*bmm=%!>jPQ>Bd5au0;!@Hr(I}nF^!Vnn|U~K_?N@nA`bs@nTHXFe|gODtq{2x z@Gqaa13VM{6)-o6!@ol2XzNa4R&Qqj?H_qPYk5I<8^NEK67NHtSY$Y|!GkTJ|fA!C_~ zLdG!{g^Xt|3YoxM6f%*yDC8vOqL7oBi$Vg-MIn=zi$ZFci$ZFdi$dy{i$W$d7lqU_ z7llk=E()2-Tof{mxhP~hb5Y0)=Aw{Om}`Z2oixNmo{tgCD%J}5kQ6f0Mam(C%(YfP zK1v~{a#U7G15;K=BU4t$Jf^IW`Ak_Mr!i%PoX(ULvVbWoWFb>l$Rehqkj2bJAxoHx zLY6WYg)Cz(3OR$hC}cTvQOFABqL4G0i$cy~E(%%6ToiIPb5Y1S%taxqn2SPIGZ%%N z%Ul$49&=I18s?&q^O=i6E?_PSS<74$av^h3$U5d)A+w#=q5UJbV&!Aa(F$3Q+2304 zBIS@mHd@zV`c(?Kgrl-TE@jFJ*~F9;av4)r$mL8~Ay+VEg=}WZ3b~RgE95GstdOgj zibA$97lmBIToiIGb5Y23%tayBGZ%&2z+4n^BXd#6P0U3hH!~N7+`?QGaw~ID$ZgC; zA-6LZh1|hh6mlnXQOI4)MIl?6i$d;ZE(*DaxhUjb=Aw}Mn2SR0XRZ};v2z#NKe7l5 z8*77B$RI3@tOs1A98$=`7A=~TLLT9$tdK{UvO*qX$_ja$DJ$d&rmT?dOj#jMGG&E4 z#grAYgDERyCsR?#F6N?;rV|kms3;LSA4l3VD&aDC8yPqL7!F zi$Y#uE(+PrTom#ub5Y1^%taxuGZ%&IVJ-@JgSjZ=Z_Gs@Z!#B!yv1A;@-}l($UDrn zLbf?SL;FWQhefRQkXFbOSl(Ojx=1;skPocSuy0Tb*~d{?As;ejh5Vfj7lkx27lr(TxhUi(=Aw|FnTtYxVJ-^! zCv#EAugpauzcJSedEeO<;)ooFO_8-%DI}_fu5pS+(lMgLtS}QB5$w2VH)EL`I}RMn z-f-c)z_BcM3GWGxWw~2;EI5|sZG`s#$FjVw@b2JPmbVk$4IInz2;ni{SeCaJ?g7WL zyo2zr;IyylD26U%fQOyL(3uQyF;WcCWPp!RVu&IGoQxJjBpKjkXEAgl1KjK)hK^)_ zpIyb!fedieBZl^5fTuBHh=751INik1jtua$yBOM%0iN~{LmM){(^xUM$pBA#iorz& zc-l)0;befPabmE@08it^5Jm=gnji)z8Q^K67#uLrUMEQmCK=#qZ!th1UBWDf>8yZ2 zqITfe!*ZHhMKL&Pz|YmYNM59(V@>N+3_VIk{UtuDXn=55(Lmv>qGaK$q7>n*qEz9m zqBP;GqIBV`q731zqDT5bLfk2`r;V{PP$12)}Qx&V&bdkPDMP;V-AcUn9kNK~ywR45Ffw#2_j< zSq!40fEYwYlf)n@su6>zs8$T3qB=2%iYALeR8%hpQPC7Jh>E6)K~ywN45FgxVh|P0 z5QC`b6fua3W{N>nG)oMkqS<25Dk?FZ??E6@Q*l~nm9mPKV2NYRFFeFe^gQ(~NF^G!Ria}I#p%_F(>%<@`S}z7s(M4hq6C6%gQ(~>F^Gz87lWwi z4l#&|?i7Ql=q@pcinfYDRCKo(L`CG0XB9muoK^Ic za8}U{;jE&a!dXSTgtLmC7S1YqM!2ZxSuu!;o)d$p=y@@Sie3BhkgQ)0b zF^Gy@5re2`w-`i4uZlrb^qLq%MX!rNRJ2D7qM|p%AS(Ks7(_*Hia}KLmKa1uZ;L@x z^o|%rMemA1RP>%0L`Cn5L96Hy(|IQZ5_LTZ=TTPCO?cpC?KNGbFH+IpP3sjL11S}K zB=K2A9}8y{eIlGy^r>)G(PzS0MV||26@4L`RrIBBR?%0&Sw;JWi;BJ$gQ(~mF^G!3 z6@#egfEYwY--$s~bWjYUqVL5ZDmo+vQPB@#5EUI3gQ)07F^Gzq#2_mAhZsafKZ!w9 z^s^X5MZbtaRP;|Vh>Cs{gQ(~?F^Gx`hrP?!do)uFq9TVFw2Jnb&O;DL)VX*rYJJEm zdX%0|IUO$27pchQu(}+>DsoGFR#6+_tfIEUSw-!Hvx*{wvx?daXBBl2&MN9CoK@6G zIIAd9xTq*f45FfFF^Gyfi$PS>MGT^%u3``sdBh+piV=gTsGAr>Mcu_9D(WEyQBkZI zL`6NtAS&u522oL*7(_+!Vh|N2h(T18CLUgji;fY4sHm?Pw2CZ; z^Ee13Y62dJTj379(|-$}H?aCST%<2j(Ljeap&zR#S>m&bQiQXLQiZdM(uA{$(uK2% zGK8~=GKI5>vV^mW1_@^s4Hhmc8X^W!(NHmniiU|nRCJseL`BDoK~!{t7(_+G#ULsg zAqG*=iDD2HWs5;nlp_XFQLY$7MR{Tn73GUTR8$}aQBk27L`5UTASx;ngQ&iS~#m{v~X6@7~!mwQBgn)qM}J+ z5Ea#kK~z*L22oL+7(_*r#ULuG7lWv1iWo#iQ^g=EnkEKO(R4A0ie`vGRCJ0ML`5^j zAS#+A22s&$F^G!hh(S~|R}7+}Q^lZFRPJy-4S_^Gf)5H=6|AB&XnJdKxJX~5qSGAK zX9HP9r%QZR(E{PDqJ_d)MT>;9iWUoJ6)h3YDq1R>RkTbvtLO~jtfJ+@MMW#bASyaj z45Fg5#2_kKDF#u|*BidKt3RCKNwL`CO`K~%Ix45Fg*#ULuWKn$Xy zwPFwzT_^@o(K<1Riq?xkRCJLTL`4^iK~%Is45FfqVh|NwA_lFZc@AepGF0>|ojT5E z6-~j1;;c&@F47mN=n99GoXRTNEb&=IR|;npT_v1VbhU6+(H7yXqHBb+imnyTD!NWM ztLS>+tfCu)i;8X(gQ(~xF^Gz87K5nh7BPs5ZWV*5=r%Ekif$K!sOSzch>GqMgQ(~( zF^Gz`ia}I#w-`i4_lQAMbgvjhMfZt8RCK=>L`4sXK~(gh7(_+e#2_kqNDQK)hs7W& zdPEFbMVC38l@Lf&GCrAMUCt`<()9MI!$tZc6>WD|jp?kSCnY|s=qcf>q8-9nMLUJF zigpQS6+JDSRrHK-R?)MJ(S5R z`c&exiarz0D*9YFtLO{itfDW4vx>eF&MMk3oK^I-a8}Vb!dXS%3Kta}5QC`bJ28lg z4vIlk^t~8FMTf*7D*8bTqN2lM5EcC>22oLy7(_+?5QC`bCozbMeinnM=oc}FivB4E zQPHnr5EcC<22qjWLkyy#STTr-dWu0*)JqJaqBt># zisHo}DoPN8s3=hkqM{@*h>CiPK~&U745FfA#2_l_D+WOkDN*B&5$`H;f$`sBj$`Z~h8YG-m zG*~#RXozrD(NN*6qG7^CMaPLjRCK%;L`5fvK~ywc45FeDVh|ObCNMFnCI6%~p>R5VfyqM{-(h>E;o5ET`RK~&@ugQ%!P45Fe^F^G!F z#2_jv7lT$&veP*O0*Pu*!%qsUsM-lq;dGI{NJUjnYt3=2qH2lHDjF@ERWwF8t7xon zR?#@&tfKM4Sw$0svx+7PXBC|!oKB*2K~!{#7(_)g#ULu0B?eK^Y%z$6=7>R5G*=9w zqEp2nDryjesHjm4qM~_X&?>5QI=4a~QPucQOO~HiR7XdU^PMiz7pZ8W(|Yv;R?#Af z&nj9hoK>_$IIC!>a8}VW;jE%FgtLm43uhIr5Y8$(Q#h;WEa9S}m0}PToh=4Y(K%ue z6|EA3sA#nqL`CO{K~!{}7(_*D#2_j3V6|ED4sA#Reh-FJKj&Mk>18 z=^}lRimq~6o)cL`S4(_W(H7yXqHBb+imnyTD!NWMtLS>+tfCu)vx;sM&MLY|IIHMp z;i95j#2_lVRScq{+r%I$x?K#SqC3POD!Nk)qN2ORAS&7_22s)7Vh|PGBL-2?yzvt_ zV>yRmjInPsW2caP-v=QX`<5*`p(IN}gvwHsC8AOh6_Sz`Nn}@vvP9A%iuC_}&h>e9 z>#pv*>Aw5l_x=C>?#H8hykE|B&Y5$bb7szLP_&7FqRj*pZ6Uad7TI<+1H^w)z8d?8 zD!OXE3hTUL`^1+hdd+rjt)+@y=Xh1Lovn)AV5_1XY*q9oTNS; zir!_TXcqxR?-5Y6n}DMC2`Jh_K+#?TiasEqXdeMZ`w1vIKtRz!0*Ve1P;{7pq9X(p z9VMXXLjsCEBB1DF0*a0iQ1l4_MaKy!Izez1y=vQc8zBA>@~zg}R8f2RQ2SHcC%#0{ zY1>&^M-`pncvbW{TNRyUtDRxJ zfTHgRD7r*I(PaXPz9*pQ2Lg(&5KwfLfTAA>D7r>K(N6>vS>gJ$9Yr1jioysevI!^( zC!ok7pvX%=k&l3)2!gBVq;0=xfcP8A_ZOW~MM?4%kjQYK_!332;m(pr{Z5MTH3{DndX}Q38sJ5l~c|fT9uv6qO{Ps1yN3r3ol1LvR&E zhud-WjiR^Yhx=o~-Dmpi*{Y}t zTNPDhtD+m&s^~_xDyqgtQFQ`}Y7kI#69Gjv2`H*XKv8W1is}$hRF{CFdIS{JC!nYS z0Ywc7C~8DNQDXv%nh;Rblz^gU1QazVpr{1_MJ)*^YDGX%Yl5pNBiwFdfcRI-_g$A& zMTKN!hWo^qD7rb^8QxeGwdZ(M)Pb#vIP|pW4+4sM5>V8OfTG?66!jsXs4oFU{Rk+!jew&51QZP*plBcgMS}<^8caaZ z?F1AJA)sg|0Y$?IC>l;c(Fg*HMiN{_ZNu#a28iFAV&Jq>MT11qsBoY75=CRfotK-c zqH!FripH~5(Vc8nbQfC{O<=2{yVCMK+!w`iXJ4O=ph1%9wwk@J^@7w z2q;=eK+z(Ct7uHPearyye{ZI9hbqb?pMrcO+$X+7(PQC`r-dqdoa0r|Qno5u##Tkk z*{Wy-TNORQRz)k>s%RBk6+OvTMXT8;T0=n5Qv?(}O+e8z1Qe|$py*iwik>5&=y?K) z))7#&o`9kk2q@Y>K+#45ie4n3=p_P*UM8Su69Gk=2`Jh^K+!7%6m2D-=v9KNXmPk* z)By39iZ^hUsG_Fw9kbiQed0?Ly%Fv-Xr+pFaJ(vdldX#0VymLJ*{bLrwkq1mRz>f! zRnacCDteEtigvS6^gaPadk84nOF+>F1QhKfplCk*js^}ZGD*BeKiY~HI z^c?|3mk21jOhD211Qh*1K+zQfimnn+^dkX9*9a*3iGU*WW7!MM4IJ)4k%xeyFanBf z0*b;3C~^oW@)A(wBcLdPfTBnOilPW8iYB;<&V<{~86f`qL85Zpot;doWliLHumWvimjY*m!SRz+Rds;Dbl z6?J2)qV8-})Ps$po&*&2BA}=@0Y!ZXDC$cLkK7uN|fOA<>K_j!%4vqGgVAwzDc) z&he^f1zQz8!B#~p*{Wz2TNORYRz<7Xs%Q;c6+OjPMNhL)^b7$-YY8ZNmVlz?2q=1< zfTDE-6s;$q=mi3bHV{y>k$|EX2`GArfTEWPDB46o(PjdQwh&PC3IRo12`GA%fTC># z6um}3(dz_P(c_MtkYyAtkcXe8s;H%W1!TM96JMg}EypR_RTaI>@v7(@wkq1mRz>f! zRnacCDteEtigvSA(fe#ww1=&V_Oem*0Rct(2q@Z5K+ypLiVhM`bcleW!vqu^A)x3e z0Yx7YQ1lT2MIRGTbc}$aPY5VFPC(HK0*XE*py)FKicS(xbc%qY(*zWqA-IZmICeV& z#6M3y(fFn+@_5Yn-0_JoQFPvMMs`<4Uvj)Ey1-UNU$Iru*KAev4OBRz;WDDEgj&q8|t-xQl(fTH3A6qO*Ls3ZYJr3ff0O+Zl@0*cZIC`u=w zD1(5avIG>BBcP}}!Bv##wT~Mh{{1Nij^FD()1NEv(JFX-;!6}&@j7-NRaBMZRnZM> zRdgd;6;)%aqUvl_RD-RGZepvVnru~6i>-=kvr$xsfTFqt6xAc3s6GKj4G1V|NI+2| z0*V?FP}GEgqNW5CH6x&?IRQm22qV8RfTEiTC~8k| z6;<-u#SIYuE_o+bSrz%^H_vqN`oxzgy4CA6>Zgi2bG$0bVymJqY*o~it%|y_RZ(}g zD(b;jMLpT7s25um^=6}}4*^Ae2`K7EK+$ak6!j;dXaE640|_V^L_pDC0*Y=YplApI zMMDWF8b(0TZ~}@(5KuIdfTB?Z6pbdJXbb^GcMwoCmVlyh1Xs~5UVESc;y*86N9&}D z`pT~g9q;vtFHv;2*SWvHDw@dgs^}iJDw@PrMU&a8XbM{uO=YX1d)caJ8e0|J$5utt z*(jPpK+#MBitZ<%XchrQvk54AfPkVo1Qg9BplBWeMGq2C^bi3>4--%{pMatT1QabK zplA^RMUN0r^e6#EiwP)NLO{`D1Qb0^a24Iq@D0;%{ z>>H?xR&u;5TE$jHPqJ0fYPKp`!&XI4u~pI2Y*q9OTNSNktD{(7y(6}5KwfSfT9xw6n#oS(Psn{og|>>6ahu22`D;4K+)#}6rClY=p4aS z^tRWoX@K}&man6|ql(tpW_;oGi7!#~mDlMyR26;A@v7(>wkrCTt%@$PRnd2BRdk81 ziY~KN(f4ds^aEQJU16i>Dgi}55>RxFfTEuWD6)L|v>inr0*b;2D6$DC3MZh*A)v@h zK#`Atq6h+tA_*vpBA_UmfT9=zied>UiX)&Xo`9kR0*Vp|uA(o!_GAOZKg0ZLYv+P0 zdR~6S(eLw#FHw}+=R7f76$Ln66$RO!yI z5KvT>fTD5)6qP5Sr~&~+6$vP+L~s@5^w~QN5dTW~6j3gp`%HhWyhp2S{*6=POBCJc zbG{gxPGwb-htHd__dVXLCLY*kc`jiUMl6g42As38GG zjR+`eOh8c+0*aavP}GcoqUHn?wIHCVB>_dP2qlUO(Le%<1`$v+n1G_&2`Cyu zK+#YFiiQzTG@O8<5d;*CB%o*%0Y#$;C>ldR(H#U7jU}LH905h+2`IXgfTFtyuA=6F>!g{_LFvQ^Q&Y*jRkt%~krtD@;_ zRWyUGie|D^(fw=`%_5*^HUUKs5KuISfTFns6wM=`=s^OC9wMOVVFHTg6Hv5(fTD#2 z6fGj4=n(>n9wne?F#$zO2q=1tfTG66Mgoh28h3%e2VBERn$>F zcfG>r6JMg}NuTq|cvZBT<5kfbwkmpxt%{yztDgQ1l`JMK2Lh^fCcOn+Pb{OhC~V0*YQCplB-rMXwT2w2gqG*9a(j zoq(e41QfkNK+z5Yiryrk=q&<@-X^$;R{HEu4G{ko`7KzhRMAKB`J#7xKJg`r-t#%m z1XZ+~<5ki7Y*n;}t%~-tRnZ4*RkV+-iuSWr(E+w9I>=T^8^%qNpKat>$6K5ApXfY44hr6sFM6V+6A9ae2JoOeNK~!s^}uetD^7Ns^}71 z6}%C<-T_$RVJ} zOF)s2fT9QjiXsUpiXxyWnt-Ah0*Yb@D2gMXD4u|#1Okc@2`KUtP?Up!qMQU*(bqnE zumR$488mRdQAN*-qFfO^@g<7#L^!i2siM3buZoh`swf{@73F8EqGYxzD!^7nDQs0# zkgbYR*{Y}z8%2c)C@MlgQBeYliV;v$oPeSd1QeAdpr{l9MWqQSDnmd~8UaP=1QcZu zP*j$HqH+Wjl_#L60s%!82`H*WKv87^imDJ$RF&W=3Pjj17$E*93L7}V2=|$OJ^4wZ z8zOw-OBB_Ja1KmSMK^K0Dyqp=MYY(fs5V;_)nTimx@=WckFAR8vsF<8wkm4KMo}XI ziW(D8)P#VdrUVo0*cxaP}GiqqMHdQYEM8> z2Lg&Z5>Rvt0Y#k%D7uw^qRs?YQMCyBssZBvB$t6xT@`hZkrm++U!tgcgp+@oD(b=U zs;DPh74>4PqTXy()Q7E#`m$9~Kej5mjjf9MvsKXmHi`xkP&9~uqQL|d-A+K!5CV#Z z5>PaZfTH096pbLDXe0qeqX;M(O+e8Y0*dY+plB=sMdJu48c#scodgu!ML^L60*dY? zplBk&Rn#@Yu5Ez$C*?J8x~ZZcMA1DFKJg`rrbam3r>mlSIbIb_W2>V3*s5qcTNTY< ztD>1~RdhdF70qI+qS)0*W3apy(k2iXJAQXg&c&3kWD$NI=md z0*W3Xpy*KoiWU=4w1j}7#|S8ToPeUG1QabJplCS(MJos>dV+wWl>}GO^Ss^|b)6&+-&qC;#|beOG*j<8kHQ8tP`B%tUc z0*XE+py(I@MV}B*bew>q69g1}Nh$R?mDoPZ*SfFdse zMLq(GA_ypoB%mmYfTCyuied;TiY1^Zj)0S+jfTG+4 z6a@&bqKgrBM+3y4ub_eRohn)_ih_|o@g<7#MLKuPQ$_hXUKJ&?RZ#)9DoSCiqJnHy zl*(2`h1ja7Fk2NBVXLB|Y!nqEpr|+jMI{I*DoH?5DFTX06Hru!fTA=4iqZ)v${?Vq zECEI32q-E~Kv4w(iYgLNREdD1$^;ZuA)u%#0Yx_uP;?^!Mb!wdqP&sz5(C6vLw?eEeI%TNkCC60*YD_P?SkPQ5yn^+7eLIj)0<@2`Fk$Kv4$* ziaHWdbPEARod_tpm4Kqo1QcZvP}GHhqOJs2(M^%|Ndv?mFAqO8RZ&OtcTTrRpZF3* zy&@go0#($T<5f`~wkqn&Rz>~Ts^~VhD(cTxMFZHXXdqh^4PvXJ!E6-WPC(HR0*Zzb zP&AByqTvJ-jUb?CBmqUE2q+p&K+zZiitZqwXejV^S zC!pvJ0*ZDJQ1m7NMQ;&M^fm!S?+{S5lYpXk2`Jh{K+$^y6zwLsik^;>QB%tU50YzUCQ1mqcMc)um^eq8J7YVMSy^;1c1H`{eK3)BRDk>@O(Y}lHi7!#~ zL!?t+sVcg{@v7)5TNVAtRz=s?s^}-SDzc*VnY$|TuvJkQTNT-CRTR!fkwZX{mw+N4 z0Ywo66h#tH6h%N$Gyz311Qf**P!vZ%Q9J=f2?P`+5>VtPpeP3cML7v5%0)m?ZUTw| z1QZ1cD9S@XQC@Ql*fTHpQ6jdOgs3HMHl?W)ROh8c;0*a~(UMK=;qRE>b5>I4+kAfV_bf~zQh zls(M=@z)eM$x-ez{Sz{3M)|~-D5@LftbRfj)#G?oRG+Pi8n9JSL$)ev#8yR(*{Y}s zTNO2BtD)#+C!nYU0Yx1N zD7uA!qD}-9-AX`FX99|{2q@}8Kv7o$inuq? z2q+p(K+y;SibfJpG>U+t(F7EYA)x3E0*b~GP&AH!qVWV2-AO>vT?7Rw6!Bx~d%Fg|yQ8YN8fzwA7eI-9hG%d;}zC_W?D5vro zRdhectD;$KRWzHeiXLFAqB(3;G?%T4=CM`LgKSmw5L*>J%tq0C0*V$8P_&SMqD2H0 zJwiayqXZN!CZK2u0Y#4yQ1mzfMN0`NT1G(8asrB05K#040YxhbC|X58(USxettOyo z4FN?@5m59r!BsRp%I;)<`0L2`UC&TO&E$imXQF)KOB6jH<&1k;6|LiVRkWV1ie6x= zq77_Sw2`ffUSzAHm)NT4Wwt8X#8yR{*(lmVK+!7%6m2D-=v4xWwh>VD8UaPG6Hv6B zfTA}DDB3|l(VGMmy+uIL+XNK7LqO3^0*c-xplBBXMeh+%w3~pU_X#N4LqO49f~)A+ zDEn~(#J@$J+&`y^)`_AIqI}{@6djCmUR$e*4spCHI?Pr@N7$<9C|ebM$W}!ku~pH> zY*loOt%^QjtD@s<6rCWT=u-lUJ|m#$BmqUI2q-#DK+zcjiasZx=qv$6=LjhJf`Fp) z1QdNqK+y#PioPPC=xYLsz9FFKTLOwM5>WIV0Y#SxD7s8=7446*Pa7cq?H&W?fGX-J z-x>0Kluvw#q93E2$mdnjHI7$BKe1Jj6|K+QRgs6Sio)2c$Y!geaJDLP*s93ORz*HG ziXsRoiX@;Yih!bM0*Yb?D2gSZD2{-lcmj$N2q;PFTNRaHtD=%@RaAQl$fTGF-6jdRhs44+PHxN*CBLPL#2q>yfKv4|>if$sHs3rkL zwFoGxO>h;ZMBBp*5PxC$&X9u9?lb-ILaI)*Pkf1@2GP#E4XUUi$E%`7Y*o~lt%{nk zRZ&y6Dr&}7Ma|i&s0CXUwPdTJR%{ftCZH&jfTA`86tyLws2u@CHxp3Qo`9kb1Qc~7 zpy(C?iaHTcbSnWxoe3z)BA}=X0YzO2DC$N)QFj80dJs_5lYpXL1QhiqxQgmU+b5=H%^og*)*q5&MQiUzV((IB=e8q8Kjx3g8z5Vk5B%2q|g z*s5qaTNRC9qi7@nMWYBP8cjga7y^p!AfRY00Y&2oC>l>d(VYYo-9PaafTH^dD4I@i74?g@t(T0V?(%)tx2d8%=I@*t z(LV7die^VU1vjap2RL38&0(vexolN5kFAOxWUHcw*sADZwkn#>Rz(Zgs%Rk_MT-b1 zdW3+YM+qoeOhC~R0*W3Zpy+V|ik1>kw2XkFVjs=v4xWwh>VD8UaPG6Hv6B zfTA}DDB3|l(VGMmy+uIL+XNK7LqO3^0*c-xplBBXMeh+%w3~pU_X#N4LqO490*XE$ zplBZfMf(Y^qIJ>sbOXe{S$-ULy((%i4@?K5ed0?L9f@|H+Nz3;>QB%tU50YzUCQ1mqcMc)um^eq8J7YQi(j)0;|1QcB+py+!7ihdxV=nBDAbST>1 zV}ST;q!>7dRnb{dbT!&1zC@7~<9xGC6?tOxnY=0rW2+*Yt%}0gs>orhA}?DN`Pix` zf~|@o*{UdtjiP7*ied;TiY1^Zj)0S+jfTG+46a@$< z3KCG1hk&BI1QaC^P?V2=qWlCDB@<9ofPkVDf~)9Sv>klSD9R_FFZxLpEtIc-6pZnS zFHuw^#;Lkp6&2-pRaA_vii)#UQ3yZKv5+EiYgOORE2<|sst3>KtR!r1Qb;xpr|?lMKuU0x`}|IngkTp zBA}=?0Y!BPD5^_9Q9XjIs8EdE*#Pkmlizn;IL3XZ-&4LcTR+ApzC=;u80XF%s;CLa ztD>fCRn&~Fikh=kQ46*zYROhbt=OulHCq*BvQ<$VHj3I3P}GiqqMHdQYEM8>2Lg&Z z5>Rvt0Y#k%D7uw^qRs>qWf4%+g@B^21Qc~6pr|_mMLh^8>PbLRF9M2s6HwHLfTF$x z6!jyxiWCFK+$9Zilz`yG?jp&dkH9-MnKVh1QbmtplAjGMKcK~x}V@G8W3ZDZh-jb z$oE|jR7JPRCy!>u_{5henj7Op?^H$eI9?S!$W}!Uu~pH-Y*jR$t%??~RnbDWDq6%= zMUSvm(W7h>EheC72?0fq5m59v0Yys*C|X89(Q*QcRuEA11OY`W2`E}cK+%%~6s;zp zXbk~HPZ3b`Gyz4=5Ky$1fTCv!D0+^7qUQ-HT1RjdJrHAO7$E-n@_pBHRM9H=((L*e zpZF3*FUB~ncB!J5I9?UK%vMF4*s5qVTNQ0#tD;xfs%R@)6}`$s0*c-vplCM%Meh?(w1lB+r`aevLqO5z1QeYmpy(U{MPCq5 zbe@2sF9|5RKtRz~1QdNuK+!h@6n#rT(M1A^z9XRM5&=b*2`KuWfTAA=D7r#G(NzM9 zek7pi8o^a`G{)X!fcPuPXB|IOMKg1l@l%XXe2F4E*7?wUK09aa49f|R{pB-#hpmdd zY*plAtD*?DDvD&QqA0d1ie{^#7`7^kWuqvLfTDN;iV_GYN+h7jPe4%)0*Z1HP?U>+ zqTB=&1qdh#5>S+ffTFwv6eST*l#hU-`~(yw6HruufT9!viV6}?luAHRA%d&O6KjX< zHHt>bw_1nAy3f&C=QN{mtWSK2qT;bmp?#{T1jp-RQAxHcD#cbsrP->e3|keYu~ktz zTNP!nRZ&^CDk{fDQF#K2DiBaqk$|E~1Qb;!pr{G~MO6tXx`BYA8wn_?MnF+@0*Y!7 zP;?UkMKuX1szpFiZ32qw5KvT?fTDT?6xAo7r~v^*4GFHIqOo>E1H}KhJh?BXijIh) zMzKEeC5oEGI(-kQqUId0idwK$QA@TeYQU!Y*jRZt%^pnRnaK6DjLmJMPt~i=nl3j8p}q}I0A~s6Hs&~0Y!HaP&9#n zqPqzwnn*y=Jp>d@BA{q80Yy^?D4I$@(Y*u|O(US_J_3rS6HqjRfTEcM6x~li(JTUr zW)o2K0Kru>IM)8a0P&BKho9S3QI$9|=EVBMmneED*132@6+O)Hs%So26)j+^qJ?Z# zw1};W9$~AZN7<@qFvudr3oR<~^n5m0oPfTAM=6dfhFie8GfyBHw;g8>8QWmR-Sz8vyl ztWSK2qEBL-3CC2?agJ9-C)ld!Q?@GljID}JvQ^P3wkkT!Rz+vns_1jJDmu$X(K!N& zz969JJOM>t5>Rx3fTFJmDEgX!qHhQ&`j&vAiv$#XM?ldf0*WpZQ1m?kML!TwbcKMT zs{|DNNI=mw0*Zbjpva2TC*~;f5L`tc$J#3l5WiQxz44eTnw@G!Se#FMi6U>Dv*Wlb z@^QQ>ieRgvNVY19VymKPwknEYtD;!8DvD#PqIk9{N?@ZXk$@sU0Yy0oD9TAdQ7!_C zauZM#AfPBnKv5n7it-Xrlte&LJ_3sJ6Ht^)Kv4k#ic$zDDo8+4Dgi}>2q-E{Kv59_ zii#3kMd5MwIRnH$RlYIJiF2Rn-z&c=v{;-^e2Jn`aZc=Ks;D%_tD-V&Rg}h7Md@r+ zl)+X-W!b8z99tEYXRD$LY*kc|jiO2f6jdgms0sl^RS77%fquXL_pE41Qc~9peT!gqAmm!btRyv8v#Y#2`K78Kv7Quih2=H)SG~! zJ_Ho?C7`Gu0Y$eFP}HA*q5%XH4J4pw5CKJl39h2%arP(!#J?ihz-gh1n#xx|ZjbYc zFHtl+&Y6Ek6^-C{RWy>VibkSJBWody4_$uPg7whN+?^p(ku{KJg`r7Q{IppH)Q*IbIbl zVymJ@*sADJwklf8Rz*wLs^~GcDter)ik7lf(K0rQmJ?94f`FnY2q;=fK+!4!ik>8( zXf**vYX~TMih!c02`GAofTFbo6g^8o(Q^b8Jx@TD@C%#0{D{)Sd^Qveo$E%`O*{Wz8TNS;=RzRxFfTEuWD6-=9X*-HM1Qdl4P-GKO6i#pz9gnkT86f_7@_pAQRMB1XEo)A^ zPkf1@$av@3uT@bL$E%`fwknEYtD;!8DvD#PqIk9{N?@y^M7An2-@~%dT&r-8D$2n| zQBDGiauHCJn}DJK0YyOqit-Rpl$U^_Bm#=^5m1z$fTCmqiV6@=ltMsJK>~_W2`DN= zKv7`=ii!|WRFr_CVgwWwC!nYV!BymoxAz+${sHo(vxs>2nf?^{j@gp&KJg`r(&C*< z->RZ?j#ot)Y*kd2t%}OARZ)4iDyqO%MHShqs1jQhRc5QADr^*0C7|dA0*Y=Vpr{%F zMb!x?szE@}O#~FxB%r7k0Y$Y5D5^t1QC$Lx>Jd;>pMatU1QazSpr{c6MU4q4YC=F! zQv!;b5m3~e;3_H|Z|A#c6s5|itIMdO&hpW9i+G>-5=EKuPW4Nws13)fqPA>R)Q+u+ zZf2{Z_H0$ufvt)~gY5%ZzpZF3*qvD;3->ah09IuMTuvO6=Y*jRtt%}C6Rnd61D!P-c zitb{oq6utObT=DC6A37~hk&9<1QbmsplAvKMN&2{wvW z5>T{?fTAY}C|XTG(Ha7Zo+6;=X#$F#A)sh20Y%ReQ1l!DMb8sZw2pwH^#l~XKtRz3 z0*W>gQ1l`JMK2Lh^fCcOn+Pb{OmGz~jJMAlApUY@I*U}%ck=FSOT15fiK1=sPW&}h z^cu&jqSx7~XggaKy}?#RJJ_n|O|~j}i>->@W~-ui*s5qJ8%6IDP_&DHqW1_W+D$;w z`ves2A)sh40Yx7WP_&PLqWuIE9U!3SAOS^(2q-#CK+zEbijERc^dSL79}!UWF#$!# z2q^l5fTH6BSJBpZyMh7YKOWIV0Y#SxD7s8Q z(f0%t{Xjs`6#|N`5>WIb0Y%pcDEf(jA}c|kvZBaCKv5V0MK%FN;RF;p1QdA*DDn|p zMW4mnV+;`gn!ENs5HS<6qR6aH9-8=IG=>8qH-LsipsN9Q3bXts>oJFmDsANGFuf@VXLC5Y*lmvTNT~N zMo~2aimDS(RD*z`n+PbXNkCC80*Y!AP*jJ2qPheW)gz#&J^@7y2qGq3mZjU2`K7DKv8!Bih2-G z)RTasUIY~NCZMPf0Y!ZYDC$Q*(QO12^(UZc00Bh<2`CywK+#|Vif$*MXb1sCLkTDv zMnKVU0*XcuTt#gX?4|~Ye}a7Xep^+PQ=ayZOz?>>QFKRwGaynGjpcY%G>)x`#zeF9Ai<2q?ObfTHOH6wM%@ zXeI$g_Y+Vwi-4lp1Qb0$K+zlmislkfG>?Fy2MH*8h=8Jp2`HLRK+ysMiWU-FMWYk! z2MiE@n}P<;7*(`I6fH{di7!#KB*A$;S`|IU@v7)?wklf6Rz=I$s%SY|6|G>aq9@p@ zXeC<}tzxU9C)p@kO+e8a0*am@py+7=ik=~$Xe|Ln&k|7d905ho6Hv5{fTHyT6um$| z(FOvFHWERxFfTEuWD6$guX*-HM1Qdl4P-GKO6iz^qLqL(2fFd6O zMG*uPMG{aHMQ|0JPOy6zApU3M_ZOW}MWbWQh)(p0FHsbq=uGmfq6CgtMTu-x~_W z2`DN=Kv7`=ii!|WRFr_CVgwWwC!nYV0YxPVC@MujQE38-$`DYLMnF+I!BrHSXg_Iy z_}_C3oVY~ynf~qaS;ve-pZF3*6%w6ya;l<=9IuKhu~kuJwkoQ^Rz+3Ws^|u`D!P%a zimI_yQFXQ|s=-FlO#~FxB%r7k0Y$Y5D5^t1QC$Lx>Jd;>pMatU1QazSpr{c6MU4q4 zYC=F!Qv!;b5m3~efT9)z6tyIvs1*T4tqCZ~B%r7b!Btc)(Y|1S_y^0A`|_%&ynF?u zZK6+niJ}gPPGUe6b>w(ebPHP*bz-ZcTiL3pGg}p9u~ktQwkqn%Rz=;|s;D~~MLh^8 z>PbLRF9M2s6HwHLfTF$x6!jyZ=r#h1`V&wzfPkWb1QZP-plC1wMYj`BG=zYnp#&5S zBcNzF0YxJSC>lvX(I^6nMiX2`Hz(Sa3=sdv^3ipBRa7O_j4_Em@g<7JCptIhQAKxh zyehhjt%@eFRngsSRWy;Uitb^nqDgF3G?}f6rm$7fR5pt4C7@^;0Y&!_P&A!@q8S7f z%_N}cegcYS5l}RnfT9NoD4Ih+(Od$G<`GczAOS@W5m59n0Y&o(C|W>3(Lw@>77dYXWuX9y@-OF+@H1Qb0-K+*FA6s;qmXgvW%FAz|) zfq(h1=c?c*9BcRA8peUSxB8Pw?F9Ah90*WFC zD2gPYD2jlhXab622q=mrxQfmu+RY6R|EWX+=bS2-=svsF=mt%`zdRg{OVit@5mQ4(7fQl%fTGd_6qO;MD2;%kbOMSp2q-E`Kv6k@ zt0=*5&ow~&Q{-t`qThX{|ER&^l=u6@mnf?2ch(nHMO8Rn6;)-cq8r$%=tj0Gs>W7D z)!C}323r-~#8yQ$*{Y}(8%4DVD5^t1QC$Lx>Jd;>pMatU1QazSpr{c6MU4q4YC=F! zQv!;b5m3~efT9)z6tyIvs1*T4tqCZ~B%r7b0Yz;IC~8MQ(ai)`QANLf*Z}dLmoJ@F zQbiwxp0N3S;!6~D@;g_Gs-jytUKMp_tD-EnD(b>kMP1pds2f`qb!V%h9&A4Ew-Hd(pMatP1QZPQMS}?_x}AWcAp{f+C7@^+0Y$?J zC>lXP(MSS{MiEdnnt-A)1QgvtK+#x&tEi*jPAO&-EtGFeyG0dUke_NC=l6*(Q8dBt z)GDEh?&f$^G?A@}?qRE#f2N8MH+ z%ltap@W2G~Rg#FnQuB^5Ca~RnP?ZokWggCQ21=P9Yzqc%Hz@N3HkfaqObPsGKFTT_ zsAGO2pm^Zkf|gY}@Sgc{OGY49QOl|jxTUydRS7&+(z2=rPL;N-nt?LumQ^<}w5(+{ z47^z0vYG~ds%Tj)1NEv{R-3?mH&|Bt!28uKt5YCwlVx=Y+*-@BdIXl%v8+CUGxaR1 ze;~b~WepAtZ){n^0xvhUtWg0^3(FcCXwb^C?h4Gvw5)pqd)r#p)Igs0mNh+))zPwM z1(tWRths@+oh|F(K-sRAwJ0#MyJam2Z0>1U%K~;E%UT&|)X%ck1n%!|S!)CP23pp- zK+^4&wK33jsAX*mJTcs|wg$c!X<4ra%8#+EHv^-`TGr0ME8{I|cfgroSsw(NOth?n zf!UKR>uBJ>6w5jm$Un`pJ`HrAZds=Tt7cl(xxkmREbBs`;vCERHgLy0%eowR^&!i; z8uTqNx4$RYY?1s_XK>D=<{t0_4=piwfhSmCsksk4!Jf;_o!|+se!|=fp5Rxj%-!G# zR$gQ72TxG`HT%Mzp!{>>#XUj!_oPdEg7OanXLy40FS=In1m&OPtl|mEzo}Tw6O?}x zucjv`|EgJCPf-3@s)nAR{JTO;Jwf@0VOn~E@-KU|@dV|cW@zsT%J0_ij}y)$-2uEl;3i6 zk0&U-qD8FZ9x+f^VC}Nf;C_m{x*AtW<)qdC$l%KU-tyU`Pr@44LM3CcIkZS@4@yPjV61m)XS-t+|J z`wn(`g7Ssq-JYO)j}!c@XMZ{JO*F&SW!dG8;Y~ceUr3)f(i-!&=PBPo+O4J;+g8%{eA0$VGk1yg zvb1h7(q>94>#;0(YtHwEc^d7h7?MVX565oZeBBP)X_vnH64BA>Q~n>u#g!w+>x)eyvjF)Muz!gar0mP z2jumx>7F22eiTG*f`l}WRlw8Ii8-`kM7;u@R!&U!Io)~`@U(Vf)?J#~zJMpwiCMBc z<7O*mr8%O2IU?Ec4ISE44^3P(e`1z7)SEczlcy(-mSYna%$?aJbnNa{yYg7c+sq-Q z&9PnFL&8Q|R`M|0J)5~)gX*`u-#BzOZ!f$h$@G&c0A%*j8ifSgU@_S0L&z$F=IBp?7lufzH;s9JFVntk?!@l;vVFwZ6z-_mMy#|U+DbWS2#A#N_oH>GQb>?@}T*{81skZO?t-5 zt~=vhdd7#`=1n|tdF?fG>zH$1GU5GW?kn72b(faroV|%3J+xwmIqN;=$a`%orc(Gwz=$Z}~J$Pj3nvPCwWNhy?Z@6;E zE$$&s%nhrPdWWvUp=W=1$-N34=liRL4jFpp)@D}9Ide$pu5ageZs^%`^h6lz!&aq5FQV`GZ`I6I_k(R%^{IYmPkm z!m*Ftt8wF^FK-Lo61!hLuxgBzl9Izb-peh~(fmOUPAR8%_?QA^!py-=OxCRD>xVA& zoo~L}Czt9?+&p{3-aD-1cILav>?af=Kc`Ml6>D~cWN`G@m$W8Hpdli;(73Q@m6A`-pZ|}cvtGNrzYyR$`!&Bu= z$o%QTm5Js$)HMe^W-jmm7dUm-lF8;2@-X(y++gSem$%m=&6%$t#fbUhp!zt;9k(Fw;y?Zl$Cr`kE-n+<;0|(Jv%IP&^zlU&XBhV zZ{pLtADClqadYifOxbmAw3U2W4;sNi{a*ROy`<$U7Os&8N^jz>uMaFX&DbSpK#QnRo||0 z*|tCVp%Xgj*zuR<$t4-nvmTx^#wyrc4+=f}4}at%b3Yp`2aldQ=e|Y8ul5cJoqqEp zkIlTpvQk&3nD_nWKW~`rP5sfl!OMT%B6d{jv*yi4{_~y)^QOLFP9pz#ZF92q=KYoY z=Z!OCpsDho_fvDS3g&&P{O64|f3w4U*em~ePno~*B$#(p=0ERGX6!Rn{_~zTqnkOs z{O2{_xSx95yf2miyy3Rj@+5kS#N~*#f!n~=Hb$*Xi4#gd+fLx(b49w-IIAt^c6QpE@8wcyr-$&T%94E@2pZh0zPcbPZk zsg}olTLcqr;!)(0igRA=2XA)zoMpltXA@(wt?-j+R6*gvQ_9T zyM@lOmAp7-{*$w8wOIaC*j#`)LSArLtrq{z1({qtbXl$CMVfh6?y=g-3ofhmb(hup z`paq^x~z!MWwnh9OKXc7uLf6+_8_f&(J9$~sTn~@c z;kOPqnWN1kjX6U8XFg8U|H-X#{r|4t@+8`}_LxJ$JXhjk&5iW)&6SpxKBQ}Uuc3p} zhYsnUJ|t^s_nujUhYT9lv-_}~J<_`m89jK|APL=j_82~-=g{l^PEK!5T{V61kiG-@ z4(mIjry&K79xN$FIiF(L=AlC3^QsuQjB{@V)~F)fqIT zXPKXGi&4Xdgl-b|7HK(TP(O2<4^7V;+;zxp^@k74YGYoP-YxqNADY#=R;6YYxtq)@ z`xl=3zk*;y*I_;7zOXE1)T>fjcX^x4>d~`T*Wvw#WepoWxaZKcK4RBE=+SrJFf+{4 zEyFLX`=9{>1`W*WI=HWChIMA0dRgX1>0T$)O*8Kb;MrF$%1xH}IVLCcwqTd{I8Kh= z`=8_S+PytaE;~<}6H(1^yqz4s*OO-cP~BUwT8fjSfcay3x|743!|{jyZ2oA@(3>u& zGcRjcVd0)!PPDv;cM8f2(?e6vrJPg5On-SNM+rSBSDA9@srJY;C&i9Vas2jhIT`0x z-JEOC9+Pri;;;Vb%hX?7p_E@=p#*b<;@Ue-suR~xE+J3+SE?!Ef!;`iFI9`oAUL*&)?*RLtBvEQ3h?zG=i zQc&-$)NI{L+_yEdbyW6Fojo_%J9YN139s#6c^TQeM*pj)=9c8;pMO2VO8@-W`n!)M zTnaD${H6W#$F1z0H`j=l**Q8T!+jY32ao3|PUtpC`P;jj!oPe_Hjf7KKC57dpR@aL zk?tg$hpLDaC(=9`RdaHiQ8>fNoou#VT)aGv$2*1f-A8E3$;*XK9OZARC z^3+Y_8fBC=*Dc-r$vg-~nnzW6jUv4T^<`?dt}I7~&Ny^#fzY|Ry-2EiJL!8zea(wp ze>FK>g*X6IfmH&!cAbWRmMz(I{?49?2&#BWLS3}d#2X=q= z2JjmUiWvq05y64N%8oM89wFHX3F-RRU%KYAXZ`;R_gPrsT+Tmx0Fs9Wc|`atU*GJV zclJ)5J^ws{W$!ZF+o-TUzWuZJ1EI@EcjV;x%?gC_}RJ3vUS$kIdS^G{ie>Ho^FpxGw%jV{l;C! zUH8vk{_P!d=#AN&yo{Win+q3m?@7)?pO^ps14B;pfZ%WJ#FlMop0k;!<6=0M$B8w7 z!@OZd@;U`Vf3inab8^X_47N}(pZyIFOL1boslC&4I|=5W^NKC(B;*VIe@SyLMdhI; zy@2@>Z-$|(R4{a1&EJ{NC}jK14SKjVp z&D*=2!LMHy)c!{<-+Vr&c&d}v+-K%Kch8QOf8_AL?sffNJmCGW?f(uqYq< zx*r}V$u;6R(LenlILUk!yL17kL}4dMp8UvhIh>>d**S~9`#745HXm7sJ|3?gdOjr| zx0e=4zxY7u4}4Vq_h%vxe}CvqlFS9Chn_GbC52v{Up_tHYW~yn;tKrs%NkCJUw;hq z8?V-HA6;Ev{iYPn_<^mCkQog@U11A(78U{lhC?@J}7}^Ue9kUgiJ0G5;~PZ20+e z_t*cMHvZgYrKg%NaFj0WB+DawqIu^mZ?wODnH}2ce>>07|L8oqtn8h)e3c+{egEC( zojX0l9xY!jC~LlG@EbP)SND&;tnS{F=HzAM+?tq~L;h6VDQzBuLl27o^sP9bxij)M zc5;=iZ9XMwzFZ)WG5O6m4jR_x%LOI#I>kbNk}ntJmp_@iE)?|31-aZW7X;0h3vv~9 zg84%KU(%dQQN5d+np2z4oBzW{sz3Ia6M8&PanDJvrx9hoAmJpMS6?3f)6Iu`$v4XN z=jN;K6i{g;&C8rAPOi}V4D%`e5TA^~PO6a1Wk|}W{eS(kpmx0xljK#2cS0X)nbU`+ z99~XN=8_DZr(yH!^ZNVC$j*72v#ahNpON9DCY$+3u95SHP8@n|QruT2&78BjQRG(5 zWiC%HNN&~C8_gfgt?J%L)ty3mW2Kpw!4&fiA@aR8=G}7WR;^IjDJr*W9&@Y8yXs%R zET~;y2l;Z8xm7F33v>F=l*7w~&NAJpkm?l8XEulN@{b(uRLF3OCYyu*@5FNd$OGHI z{r)Lt?vR2`MRPB?cRTmb-|l|-R*}Ck(5EVTw^zLWZchu{?ebJ4PZOtDBRR-?xN5F> z!H|OdCUEZmLwD$Z-<3D_mAp}eRn|}V|HC)I|C+ZUz1IIj_k2k0fBxa;uXwu;smT5t zWVY_ZY@Ik85A^Q)lBFTJhDCyUq9R0g*w=tjl*&l8WkPq+8XGRLhhyQvBzx_NTDBrehPYg4+ zg50|1L&{?Eu&l@Y=DWYJ4D(}y^)p*$)oa~4t5NfIwVF1nn^miIgSO4;HE(0_7tQKr zX4Yy@FRM+97FkVOG;d(FuGb)|Y^^#Ce?CQ>HkobB@pW1>YuU738*|FG%^T_I>ep$Q z)$MO5tkt@1R`V8Z%!xDWwQf_d?$3YIxTQJMw#_r!wrtr#{vxYoqxSWhX4P-ex>>C@ z?j@SD`sK-MH*Ha;NmkujZE9sTZ`-VPz1H%2v}o;~x_p)EFSvP&tjxBxGwZZ&Bqyui zqHXiKp_5gv(lGS0>MyQl>w1|jTbOI;o>K*L8g2`@?)6&N%DnEHbGtRmY>-vEZT^jW+Y-qclL;CjW+r8_szJms44)12QsGpfttFC)-6+`DLuR;Cm zZlHQ?8gf5mwQSfS%a~|pG}NiprcsOL?(JFi=L5^ux$ekDty^W)HWuqP%5<+3x4C+u*=1qRSb#HD|zfo4LmZ8_CPK)Nv>(voeA))mv$PF9%V_l__*|ts{qxt_~ z?LDBQD8v5k-E20y0i*;Fun`C-C}2WIL=!?nHibY!7Yzv==|uq%1EMI{5NwEwz4wM) z5EVNr*b9mkJ0iyZ-OtSL+HBDG|DNxhH|M}TziVe^pP9MlnU?Ivr$+4|!}5mZRpi?m zjlVQFrz|#fR6IKQOL7K{(k8B*g|~UjOUu0$3^4oS4d~&$KTDzU^0RC|swgkb&#$O6 za#o)@W9Q}!su)_9GpM{IHq@JQSzgY7QQpGzuOoI@d5+Dd}yhy z(>&9bZSD46+hhs5Wx{?JUtn35Q|!HSMd{$YLGjm6zJFP4V8PHqwni(;^M(#}`#f)* zpIcnyHMd)Le-G>7y`#4^GC|%>=OI&F+p4!-%(B%NpIavcf`VmSjVN{0;{JZxyi@Y3R;wx7jk!CvD!AJwtXmJ z1!-a@v#n&;3Apu-4mV2V1w3 z*zbCaRBk53JJYW571lpt<+u%0`_{hi2`}4*uvJo#H!?RbZ$LtmwM^C%56!Wjq$qDx zMSf1q^#*K1jp4cmYg*~BG8?dcEWbFGTYGfyEOnh;eAQ)jjql*LtNS~k?SJFvPoKUp zK5uV#$SaN2-ECqs22{?gtjL`|=adOU?GKCNqg(%7Qd;J=kLzIld3N>om}xU-OiH)j z&STwqzbqSIF>Ixlm)0KN-0>p*nmX*Vyy85sQ+I1GudY~rZ|hcqZQWSDzn1(K^h|gc zuOo6>%XN9)VNk8CBNDwpMNV$+u(F(7^=a|;6xacBM2;=!&{#>HZ8mQnz2lobH{lHj z+eRxd%Qdlba)-u-`v-9ONC*JvX}9C~hF9&QT$;tElb5vhw1a(hbI& z8Q&iU*-k%9$4P5u?Fja!{mXLfTtH5_ceJgOxKG)tqW>)}E!SS%JN|~Y8T>WapMgAY zgU_{t(}eNq_DKVC;&0~!FU_~vnIyG+c5R=Kn_F5@V0~450@h7Q=>Wg=cDfLMF*mQc zcvx{xnOQ$DR&Ij3V;2j8RdfP=8#8TkZxQSC;={`Od&l{T@&Y@l@yE3Ojh-&yElcvO z@6y>0@8sr}W!Dux(?7WvMg`V0JAlrLym9YT<@$&&e&R< zF=;}@gc;+fRL-by`%-*nvEt&qfjPz6c0@>FyD+UZ1S}~x&Kakfw>i0|-U;R{x^+dzUyyKJC zIp*66DKALqmT|W@XOuhF)PdJOg_}5k#<0dr|xQP9W~>Q@3*Ge>IrAd#kLRB zZg<{&U`|O%PVKv!iFT63>aac4dsBaJR<9mEt5kbDO$H7cmY&ty#dy=g#UpKC7pZ$~ogE_p^@{Ii+{!>0PGVhm#yNe(tQJCeBLlJSn|% zY1j15_L&v^##sY8PnO3H+msJLC7ZXx^aGVb&LU0@pn^j~}Y+v@NH9tT;Bh_PjaM`d_Wd zq6rIQGsaI?;LW02onE!J3vl~U+{Id@?XY8=!%#Z~b;tAg2y9mGnyPkd+s>A2X9xXr z>_SVutG5f#CHJb`1?;HrFH+qL8h5$jP8wo%o#3Bd_{;6tIHh>z%vo6huXO!aTk0IC z>zomn*qr*8j{MgYxy5!MutTfssNCDw$){7&ySi~(FDtXF-^O0?Uf4E3d^WXf$(_kn zXjS=B*x}L}u+8fO>%tOxE^j;6UfJz;BCbxb?lGgg&1ph~`<#>sbLRN-va3p3UcI~* z+?BRBf}LagpmsB7#`ki6h#ofKWYIgtwJRZ=r)AOC+X5%7v4jcSxu^AGo*>@))m|dT zuYr4NF8);=@9OvKc_o7rF4c0~O@_pyh+CAzE6sutb{`|R$huT-A#KM>XcjwyJ9&w3 z3t-~q_W$F8EkBlDTK8(Q)~o?Jx!&jC)H%J4_s0L;Q~WEnliiLIZ;rpz!v^IHxBb9f zEXQ9-SgAR~>{8s$&k`@a-8mJj&bMlyUB>t)IPn)emEB2f=^)opct`E5|L3dPsqDH= zhSgrq)xAn{M#gsn8d5$uR-vnHw>`Kz%!$v{M4nS#~85Z(qV17+h9b z5VPw=+Z2QB6xr@S@Rpt;t|3m7n4PPRHW?}^>;s)@@0w)U$+o?LcYP7R$Y2JpS4&h3 zjwty#1MC*he%HjF1nyl2n(Og%nA)qQ0Xk}C*>werW@{ndYR;AurT2GJZ&lF-*S7tR z>N(}^c3b=ojO|15nZ~c*a{7BW-r_GLtjMywq5pYW?e&seXuFp9mt?99fNfi~Gy zrd_$ka%0}1XK;=kdAzag_~8%O{#j>q|6XKnfnELP6?>!D#czCe@%<%#M8z<>8D=X} zGt~U-Rv2s0It~rG%QdyKc20IlU+#LzS})xw|9K9}#;tREug>Xo{Pdg)QvdpiwV+j6 zch6*7dF#VYnEdr&S7{0B!yWwGrAkHlh}ckjCE-ZQ`-pj*Ob9E;nfvH|6=-TQow-_by+Q9Ct#&WGQvCe&{ zx5DCMmD@$F-2~8uJ}WTc!|ndBKGJQ#gsS0XC_u=KXLe{fKx$7b2ju+^CzftYkIM6}a=E;#+X*;}?JOqGZdTa6RR0XlYlpjG?G5<1;Y)Hx zR^$#Es-sHc-DR(7|2{_g7h)`D{4Sg~%i7!2HsrsH-8@U&w`yc3y z)4%$iEO)iw&D-5iW!{NR&W{z_8Cv2Ug4%PG^733g<*BnCkQgcL9;i+oX8PyxUg_!| zGV3&n2E_aA_zFwt$=pRFBk~r$@bM$5w?yvVXYDy~x6E$wsrG{4MTox-##?Enerji57F%prS#gBmA|%6^^^{ z?&j-XFfgb7cAMEAws{XY>a70S>$Ze5hC26E5;s;4zl~Ws{J0AqZyDU3O>e-z`|1YW zVZuX+H#PMh?v8rC?Hk-w(uHx!+(`o_&7HU3;?w77=S;X=TK9^CGa&CxZ5zdBllK=1v)Hzp>Mk|7qV$xLeBt__tc!Z2c=P)~Vh7*BOp?_Obs10M3@nhn3sYhT8k` zUN4w<_USb^p{Lgf{yCI)i}U~TBVqYOS?{Aj-CO$?P;Q8eG@e9e`L}$%_PIN(-hh8% z&pL32jk-s~cqj4iMYLIXeN24IJ~XSnG|B27?~2)vv)nyY zziD;)yPUyx1u@bt>g(*03C;6Yu)n9XJnXP;Z?nhP``Jtsf>B*d60Ugc z(5&-U|G4E|_AgC%%fbHnzTGs8uNTi)>)_%bw`4$_i(cCSHP_mUjYQ>Z4+ieudEzrI zn(HsNx7uu#dh5^52NOHQ_&JF^c8#AlCfvN}&CLt<@H5_0uj%fN>3)w$YI_koxFz&J zS(&vLr}kK1PvBg;+_h8ul8%+-PC~q+>VI86J87JCToSsu_%I>k*oy&9&EyI zDfrhh-dagKJN7O(N7xf(_w2n?4~c1#fAilxQQZF^<&L=SSv}n;&v2Qte{s&BBI`r) z?DpJ#XKZd!_8+}=qZXIiGehgq?AC71poH6iuFI)=`^LX~@~@m?cJ%ZhaHji1M4`S)gd zJL_S1$Wr&hE#K~Fa?Rs@jUzBHH}{zI4(_=@&YbD#dDE*Vj2~~$1BdeI^iC;Wu$L$>XEW)gmq1NPk(fero# z%iECu`rd@>Ucbmbhui=0U*DdP-RtY^6YLXTcb~macCQcR3#~N&TN1K+{c*RVy&r%6 zTNAQ-{T%zc1OLZ={ey(;UJuyE@cTdh>+Zw*$?o+J?2BE)cwAQ(0*GZ6o@aFH&rNL z-$;<~6AIY3Q6&6?Y8Tw2p+IwQ3}=P&GtJg_--Pkqvc&ewWA@9__setl%S-pm7w(rg z?3eG_FF(FtesRD2&VKoe{W2d2@10$?n-^#|UdQ_X{kPNVo+13lqwU%e^yI{UUQ&zQ zxkPPpmzK3Dv#Wo;5c(s5YR5ppeJxo%`$m%PuG;JUP1|}$ z*_ZX%e(LgaS8e<+T($A{sk(3es@EwHm}*+P@y<4#-FTO~YU8=@=5q60U^|uLD_u42 zzGJIi=Rm-HaaKKR{6<&p^%q^W*WFiT)jQh0pF@12Y47I$vgz*XSFYOlWwsx?@vBtb z*HO9l+~KN?cZlr{^)l^?I$X6}X8XCDZoI2Do%;?b*S>bPKfBknUCpxPQGG{suWDo4 zXWZ+ZR0~y8Y&|F0*Xg-#DJebR?Uk;&Zp2mldYV9zeNA2)S6kcq7Pm$8Uhk>ePqn}5 zVAWx&<5Z`r&Q?7`b-C(As@JOCulk7UQ>xFZzNGrP>f5Rxs_s(#TJ;CjUsV54b>AT3 zme;;b(W~|aie7E1YTuUV<<_e0RgY4&uLJX5@1@#LHCHvJTBo$cs;g8lR=q;i zohP{WzghJz)dy7{SA9nHMb+0;-%= z-BgcJ%~35-Ema+^dZOxh)st1{s4i5kR$ZZbf$Aly>s7B;y-oFA)s3o8sXnLrit2V% z`w~NMJ$$PAwW|Bl=OkM{zpDPN8n%Aj@dm0*RS!~aqw0`mO5Es=uoS z!~SwdRU4@usCuYsJJrsrJynlaEl?ezI$Cv{>NM5)s!LQ?sJioLxBjnCy-xLZ)dy6c zP<>AIHPv@iKT+MS`m^evs$n}|x%X+P+Cnv5wWDfR)xN3&R7+Hct5&GG?|60dovpe^ z^-NXw6}Im6OH{8`y;=1h)kjn}tG=YVUG+oNFI0a}tx*lyd5L?UdaBJ-yQvOL^wDS*_A5nd+iJ#wB{mITR-0Od-_Ovg{bvajcv7INle6H$d z`;tMIUsH`9>gVRFgX|o^y?%n~+BSZ^R`tCMKYyv3ez>1It4_2N3^)B;)jRAQ$K^*< z_t-g-%m1kMwi6MT^Hi5)`FWM!$hnX4RcD{QRBj;j{hRO?BE_Kiij(dF{M!zF(hG ztvS`t;RSv@ZjoP$RF^OI^J>)>m-zW@)y7Nxe5mU1GyObHb^Td>zE$ZKeMeUNHG7R;OH|Lk#LsI~U%t%G@2aM)^K)y}k?Z|D zLG|jZ{d~LXXB+(dlj@Pz`?;6utQ-A&y6QtW`}rBwKX3JO>TQ1Qe}`X7RnNK0&zGpa zdXJyqS8aB`pWCR8e$da8R5v{A=Q~xuuoHc^etuT%^thk^?s{Xy% z&-I`2>wstdIz)Bl^M1Zeb=wPm{!sP6m;IcfI_6bBPf@*Yo1gDi{pt-r|DxJuhoAeZ z&U@R>OI06z*U!(Z20rlf0jl{Q`MF&6yq$i&LiLSL{rs_N%g_DXUiG9e{d}_O4PX2D zUe(>-`1x1W%ne3j~3&HTJe^^g{R?x*VLBR9{kk%hhlo@VWAjt{xHy>{b0uJh`*a zqpAnEYRl77`4H7M;+>Q;ReOkMD-TeOi4RvDr#egZbk&urm#N;Mdavq}sxP=|?SDn} z4e^g%wdHJLHN%>bRc};%Pj#2-KGlwPBf-sYjOql{g{n8J-lO`N>UXMb>?^w6 z^xah_sm@ZpQS}|whW1s~Zv0%;Q&sO&{ZzH7eOb2iq=jm_YCF}=s#&VXs2-;}P_;;P zsOm`7O4SLfGgRlOo~C++>N%?Csa~Rbh3a*xH>uVOSifV-*-*8)YAe-r)pn{~RJ*G7 zQT6U~*?dk^w$mbSzIM9f)oH48RZms5(+ltQvsBMhy-3v#=icjAtKO)3tEwHIyw_h* z-LCqM>c^_PRKHXGNwr4xPt}y5KfijaO;nq!noi#P^-w)lHCuI{YLV(N)lsTrRmZEY zRJ}m;Qq^^;H>=*Rx>5CU)fZG>QQe{XuId-6yH$Tx{X;eC?z`A_YoO}gkFwlS*}MN_ zxx4bQs@bXoRf|-;`%pIi2xYr`3nU$6-!QKAYsGs%yG-}$CmPRg+Xj-_*!zkHy3AcT zeO_gi)p>LLI+-E+tDkv+F7D540$r-+&JA?2KMd;PU>E-$`v3k|z?)*c`?XAanmlo) z&CDCFtg4zb;S_&O{TdoC)OOT$$>8JJ8vi0pQ9$c>%=*g z(`}@jvXU;9^XAQ&QZ;{`&G!GtkKLLM*d~lWjq1MNw6He$8+;=KS$WV zsQvrj#>=#E_J3dZ+=(BzUENP7`Ow{N)l)wh4l z?>ZZ18XF8WF7wB8!|sRIT)&t&zby&#vs)eU`8|*@jSU9UZGN%dZpi;(e)m{RoZohv zpIfi4eU0oN?R(mW-89Yz_cLW>FmQJ}f7t!+UUUCmQf0iBcLxK7#`s~pcMP~;e#YB) z3C;7~*S)sg{w22WgM{U6YOm40&u!RTo@K@RS#R?@hG3QVay4PI2i~#q(rv;P#@*t$ z`8BqG?mgKzY%oxBUof!O4d{pYHL;vH-nZ61yCjJJFdpBX-KWdUqtoptt5;^v-u67P zTb2!HW+wjMvuAf>Sv~BJ=-rrO>z$ETobP|NyFc5YJ$+)nj%gr6!PdS5fJYV;gL#`8M;8qSC#m z%y&c8>7{$S=VtFosk$Zhan0goj@iGR_U~y854IYxIX12u`%X=A=IFp5JKm`Y1l@Zk z=dUkWUvyRBRk5oJI*oNCJ>UI*WzqV=^|7l8+;H~3f4UXy>DG0t&AENX6|t>0r>!-C z^fL>$)^y5jI{C`rpW93KK3)E1Wzn9Ub2r;q*%>x|mK(~*IKNNakrpAJ?p3y|t!8rfb#0qJ@QvVvD>M zmSt?Ub+w>qYt5F-ceU06>29ptJx$v-$@sWt{L&X}iS1wd3)W^g=XD8lc4JO0np${r z?Bs;`jkovfWbgMM^RziOW{%$6uH0{Kql-=`JRvqFVQxcgZXaCqKh14Rwc6*+?ehKR z<}Y8iw|pPhTwZNk(KCZ(te=r?+aeIOf3`iYh_B=9J@qr1j%{V@y>=Uw?tQhqysBAY z`P9pk{@k9uXSJm!maec=yk}FWyy^f;S6WKWSW{WJCncl2Dz$LUl#$_Qey(owyKRk! z%2!vGS0!t#>^;lIl~)A{b9V+BADF%J@xtfBBfA%@n9+RA(jV@AJ{VXP$PNXoM>h)e zPWSfG;8M4T{BYY3e;qLU((51k>gT10fBa?s3v-$_Pg}eEwR>J!aqooI%WrNSIIlVw zI6qL@zST#IuP9&E@zvlhH3$CIczJ_BuxZyTXHDDD^OMmFd!6vo^H=qK@67RsEq?Kl zX#JO-D=G>1I?`XV!abX9S=MXGO80J7T9>RZP=~%Q*3yKrpeiNZPW6qlQm80 z-oUu>aWn1piJGp!o98%9nX{*ZEpvsY9dF}}(UkstMro=+ww;F;msgGR-fv9NiG?S| zPV$z@?ZK|ssLsgU*Dc8nHOm+obA3nKv9ZEkRf&7BzXSs`&jNe592<5^kZ;4s*|1w` z|DBJqbNgOSQBGn1Sbyy;t_RGvy=7zd7TfpscfD!brWr>R%l35F z17%EJC*yZjy18{N>Q>k-);(cvoo#ND|9fs3&6tzB7= zMyyY-yZ<%KNGi1cIhZlF_s+mmZa;ATo4KO8y>UmjzD#X#z}#DTLl_# zdOA>@9NqKL_Uhxex0&8z_wARRwAsdAI(x_Eoz9uMF6-Md*S2e0y5R!ndZSj4ef8DA zw6FiXtW)d87qqF_TJ&Seq9>~V4s;s7rQ?k932y&tI(dEV9>1@HS>^0-YkPui2j_-c z&;E9BZg^YB+tZyLZX1>Ey~}!mk(w%dpZ%d?)v!9#4bgOk-gJXBojWp^CqdWKH_IrD z??L%>dV1dz=Z0%Xf4SjW(a(naYF>W(dReOVq_@4^P1A8~sXbm~WMswPv16S+PDd>7 z2-GIyi1=9PMF&k@>#wV__bRjZebn`tns3vy_w`S5wP;Uze^-;+`l;GWc4V95=M7%{ z&3iR_-+F)AJ&~%$v1e@m7(F&xSU!1V;Ljaz=-6sg&ilBg!$tP5+Wy_sVQfpUk8}>W z?d^PUE;v`JL&2pFZfkLHMcN@f-|o5QjM3gvIC$&<+lunD^Vb%xjXAU3zauAKTogR= z;@FykZ(lFn`+fPvh2>TLnst5o1>SzOF6o({vq!qVx~6w`1ny=kwaUWL75y}k9!nUm{B z+hlas`rK93{{O(k$iF;1L>}7l`#(G!X&#O=4@a7ZnLC@cee1hkm;L!y$LHoZxp&e> zLvJa$d0w*?mT-@qcz>mI^d;@ z8s}}7T>~G#Y-i7v&6=%PdqUjX!u*{44MiKg_29fcYVy^E!K1E@T_bO=uH)@GZ~d9I z!>&w9^mbQe=%-C~^lg~2rXaMhbJL3p*LZtE+~6U*ri?U$KU^NOt#EE^TvgH3bzYD5 zYWZ1(MYdp38?#kL+u{Rl-5;{k*8kIWw}E;gZ)|g5zT2mpXB=2i&uxjF3G2kJIJ(%ec-pGd z?-=yKxC^&^d2YkPjirIn2bZ*Wo>wi{a?aupk|xf-z4~_N_Xayh9pB}x*FGFqHSLfS zTTjaG+q2E44PM{8v{OCb{Y_&7)!WVqRCkI7syAf^s^6^2V4Yhp>u=HT%kTEKs9QJA zy4(K;uWz#c_@>y+MK{;&kIm*2&F0}}I-A#fHv31zSIe)6uX8uwOXBO?rHkX+)7gAM z+@e~WFDO2DKby5Coz3%{%`1wkOJs9)qRl&WuG7r3d3pYlqGxLYn@%rW5?d1Ax81TY zE?Qi8dhGN#E6aG+rd(8Xa`Cfv&Q$k|sbEheV}9Xy>kk7#JGV^F7#p{DaQ2=?87CEP zt*k#bzQ+yC-Lo@$WSf(UMwV=^{I9n8d)o5+%A(4`s#sNlYhmJ^mb>Tg+-I#19_h8I zxG3M+^zZ$2Skdsp;js~Q_S2!Z4-ShB_m*l{kvVGD+}kpT+ST`lS?*l0|GsXaA%$IS zNxtPO+glo)N!rqM%{bDQrf6*WlL8>|0qrd5m5^toXD_ zZw&AMKfM3@R*m!e^zAlf&%)EHTUK;2 z8nJ=>B|XAW$6-=JPo#vQe8-|pKkx$1{G+g5#5e$Rkyeg1keJnDtP zb~7mZ;T1dWS9;G|S~las7sifU^v{{C!%64dld?AMz>w@cX&JW{zg}5BcHHFAwx-+~ zxTWy4ajxDRd(5jh75w4VYfJi$zrkA**L!zT?C!|8abr)Oe1c84!^Xd+@S50$g1%!n zc;onM?CPR5W<_$F|F-qA!t?6bdX3*}dA6PZSA0=3im$}k17j_78EXwE%a>dZ&$i)GfuVZl5Oek z|1Ie!6t)@buHdxidu|SoZL>96%Pwt@8f=+55lS_}V?DeevA!ZjZU&`~PR}|85iFdrX^tMRO*&RvjC= z&#Qe4_IR~LN!N*eympnfvHhZd!M-g`ZLewK*4e-J9A{uX+a`hF$>yM2BW|8Y7R{OH zYRA}pUhPn@$EzjYzBFm(mYI+4&3pXx)KH%X{yFfdkbi-|hv6^*PPU!GxLC2D=lRA1!?)Hriwk39^yFJA1S+<9?X;;*BY`d6U|9UQE zXB=uh#m1~PQ{GRuvx)pCzN)#f^vB>q{?MUChZP+RFhWxaoR_?D?l z+P>fR?mnGR;b%iA4r?DL@m?klcn7rObJU;ga2DtSoH`?Dr~opjJA zZD(w}<+NWnj@`B|$-1ZP-ob#ozifAzgVhb}8Qkc$fj~2N=Q-ggDVVa}Zonr6qgU8H z=%l3Z=k|y;DJin6jooN|&Th*mm9#9e@spCnx7&k|Pz$>Yo>bautcN01_UJ7s8t&|1 zH1eW7)lE(gyHBD?N{)=S8HL`mUNY3FX^xE^TAyzJWi}gX!(sP4Bjt3v;~zEDm;ZDJ5JA1Rv!RTrm zt4lDt!k$eX9gO~CEz1l>-?Va3Fq&s;e04B7-kP!|7B8PJ!HQ<8;tI@bZId9 zlC8GOg3)_yE|&+RZLKL+1f#R*c#p z^iEqD--n`i+1mIa6fL*S{9`B@vUm6?6kTQSP@Ek7%w}DZ9PMST9+VtiVq3p7IXc8< zHaIz&Z*v)v9BpCCUX~o~VWm7dI^N!IXmYfXO)xAuI@%l^o*eCJ+jc~9^f(i2WODQ} z^Kw*j^iG@E=;Y`~+sY?cvCTFnIoikExhFX~&l=Gz99?cp)I1y=W@}o9Bn&=<&89KMF^Wv{`=~j?S^R>lN1w5^^l3PHuC--b zB>Ja~`FbQe-zI+}619CY@Ma`xJ7{2gB>JH>X-6b_kFANfBGH!(z8#6SvUT=OB>IU> z{%$1d{?ch<{b&y}`jPt4yKQEV){oY=4fk06=sBkChDOoP&B<#UMYmbwuWJ;|wkBQQ zDEhON8yZCqvw7awDEf_wc2lG1Y)j`fjh<nZDR*UE? zYs>5w(Z1HQIW3}t>}}_^h#qPyd0va?leV(vw}`%Mo9dJn(I&RRPi+xB**5=z7ST&> z4K8dEwJ*O3ENT%A*;+cSMf6%*6N_6!U$bR6y+!nJYv7U=(MGlz&u9_7$VRDd5#3=< zENu~e+ZvI*K04msHfMeGEt^^Y_0ivLwGLPxJ=o@ww?5j)R!IK(sQrdnVBq@b6k8L6 zpNaOi*M>Y3z0u}5c6anP+XE_hM`ziBRqc*WFek?CjxMrg7{5EZ+N_(fJ37XeVdCy+ zv9)^A?$pQawOLJqfz(a5>1MlugKgS5Zs1cRbKO828)u#yILb7f?*=Zg)p&{%s{I9_5Gk5h}zb7 z$AHwWW{Ufx-qgdaJ;`n$WJ?it1Cz~(6gM!&wnW4Y{B0sd-N3E(Ua4;2VcQV(+(0Lr zbA31PvQ6bqep5Tzx<0@S47RBnx`8ikeK&FgTW#dVZeX^J)5HxdvCW(22Hvza*3=D@ z7-{APcGyO4?gsYSd%0Gp=GrE(UwaCqCfTY>asw^wE!>|XrzW*?OJM`He6|!e;QnGJ z#SJ`bdbqJt&o2*K)vZUqvRRE&<4x(FSP$MZEZAIYyaw-0yKE?fI@l*2At`}!*< zyKL>tRkpu^?%&ngH$XYbayM&Vo^sG-YhS*yZR^I#;dY@4+x|^%GM&Qhn>hiR{Aqnc zcwnTTN#hJD3Rjq7o*~7WRECr&%8)^dGNe>dh74AeAwv{pNSUGxDOZ#sLltGnFhvX* zu8biglrdzaGKP#&#*op<7;=I#hKy0hkQ0?LB<WWQP{xpIWei!Wj3LXEG2~2T3|X#>A!jLL$l1ymvO*a{&QZpYbCoeEGURGS8FGyxhHOyAkZYAO40%}@LtatFkXMy4PMtv0$19D5t zc3OS_xrJprEpJFZ(6YO(X#{BQfVHqOpqT^K#3q2I4pVpv?ZW{0e6Md3Q*qxYw1CNdJb4i4+f+ zdMF^`fVK26K#Bv_($;{m1J=@XK(YhY(l&sQ1J=^EfFuL%S|bPYx#q zLxW9_wD;U4PAKSG)WL2wgxd!rPA_Ls$6$E2bv>R%M>4%EI*KfdI+0~jXR<8nLY75G zlVwpRSr%oHWl>kMEb2zaqV51J>H)x_o&YTB1;C=-04(YQz@lRSSkxDQMaKfLs2>1} zjssxP@c=B!24GPR0E_wquqYRRMFRj>ln20~d;k^=1Yl7C0E=P(-=ZUep-WAWv|_s% z6Ye03Zm_#5;lg0V`Q02Yk_V9|*HEIJ8*MHK)n8VkUpN&psB0kCKs0E@;0uxJ7R zizWiFXc7R6CIhf&3IL0y0rqSMJ( zv;=@fX8^FM8h}Mh0a&yQfJJ8luxL2|i_QXI(b)hjS^>bKa{yR$E&z*G0*I$+BoYSr%PImPJ>SWzjWcS+s#Hi>@WhqU*?5bUgrzZUA7> zjQ}jV34ld61F+~802bW}z@pm#Sadr8i|znm(VYM+x(k3scLT8K9sm~I3&5iL09bTC z0E->~V9|pBEP4olMGph8Xd}S4=+aJEP4rm zMK1%e=oJ7Ky$Zmh*8o_w4S+?j1F+}~02aLoz@qH{EZPCUqPGB8^fmyC-T`3Iy8tYD z4}eAQ1F+}=02X}+@GW{Q7`n>@NxRR9^SCTJ!yc1`KMF>iU(TXWgW=cgHjro0E~b}7 zpOIzJ=VV#*1z8q-NtQ)lk!8`>WLdPEEQ`J&%c5_|So9qLi@pb7(GLJD`VoLdKLN04 z4*-jP24K-%02ciMz@mKsEcz9IMKu5{`VD|ZzXP!74*(YZ3BaPi09f=l0E_+sU{N3` zewFWEqXhw2lmzfC+8GS(H9^t_+C$y&C$i`+_k1dp6mfnziy}$k=7-CoDAUWLRI)6p zN0vqP$+D;cSr#2YmPHN8vZxVR7Bwczq9$Z4N&{d~Qven<17J~e02Unxz@ioaENThB zqE-MbItYM82LrI^5C9e(3c#Yn09e!-fJNy5ENTP5qP74m$^c+dI{+572hbNC4#1)# z0KP@xq|h-YNLn|0ARbOh@~`w?wBI)fcSwpjznn##lENo+kVT!DUKVvB%c7&nvM7@* zi?YbFs4H0(btB87?qpfigDi`BlCh{40E>D9u&56Ji;e+cQC|QS9SgvsegG^w4uD0+ z1F$F?fJHd~Eb0%yqFewL4FF(K9srB-0a!E;fJFrWEQ$fJs1SffMF1=+2KW{onG~uv zLDIgr-#rN*C5txO4e4-6QpEY?EE z34leD0a!EzfJIXQSadP~i>3jvXgUCkW&p5gCIE|O0kCK`z_+M0DfFBPlJ{ zsG5vLO95E441h&v0@QfqU*`B=mxSZx{-`UHvzEd zW&jr50>GkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO-2=d)djVK<9{`K)2Vl_y04#bC zfJF}hu;^g`7HtGz(IWsXdK7>~j{$s(u1E@%nILJ|_L~{ub+V|3{UT5J@uZ0J%USev zQh08bEZW5MvS>3|7Cl3jMO(NCA8YCx7n z2ash^L$WMtM3zO3$+D;kSr(;{Wl>YIENVu^qUHcBIuL+GEdW^55`aam09bSo0E-R= zV9_A}EIJf`MTY^fs5JnK(g9f127pCv0a%m)z@l~lENTzHqQe1LbOZp4IsmY!BLItz z1o#$3L!ov(&7!vM;yyLxU+KG#VhkS@ia5WVMMsCidA(&(CezEJEV3->N|r_4$g-$A zSr+vm%c7oSS=5Uxi+Yn~Q6DlE9Rt9kz5pyb7Jx5v;u%d=K!$iTmTlW1YprB02ZAGz@qa3SabmZi!KCU(M13(S`EOWivd`) z27pCt0a$bi0E;dKV9{j&EV>+kMOOfPi%t!N_L(4Qx4RSS1+r+6vuIr?;{0+JT^$Oy zI9?WA!}PLf16dYbOO{2~k!8{KWLb0rSr*+$mPI#_Wzo%KS#%2-i*5yA(QN=Mx*dQ; zcL1>HP5>6&1;C=a0a$bo0E_MgV9|X5EV>_nMGpY5=s^G$Jp{m_hXGi$5r9RH0I=v$ z02Vz4z@odsZhlEc02XZnVA1OUEP4Zg zMQ;MIXgdIlb^x&GEdUn14Zxyz09f=c0E^xOVA1;kEcyU|MIQpN=pz6YeGI^&od7KQ z1b{`K0mYX8;!M1z^!H04&-Ez@lFPSX2YRqTc{m z^g95H{s3Unp8zcS3xGv`1F+~H02T$3b=i(ZK>!vd0k9|pz@lUT7KH&=lmft_2mp(s z0NYIENVuUMa{{w=s>b8YC*=LmH;ej1;C<%09bS|0E-R*V9}ufEIJH;MXdo?ln%h6 zHUKPY3&5fb02Z|aU{QMj799@2q9XuU)B%7+9RXN$Bmj$!0$@=m02Xxy_!iYq4mHd- ziym};+}|MCztZ3A{w}pka>V)NEb3|(`vtP78`I08?qpfigDi`Bl4VgZvMlONmPLKY zvgjDHEb2>^MaPn{s2>1}jssxP@c=B!24GPR0E_wquqYRRMFRj>ln20~d;k^=1Yl7C z0E=P(EGh(GQ4s)(iUC+u0>Gj{04yp6V9{Uz77YPlQ5nFuC^I=U)C5U;%>CYVmMrS# zLV0q;`Qx0>GlF04zEgfJM^)STr4gMKb_cG!uYDvjA8$ z8-PV~09Z5^fJO5FSTrAiMW+C;=v07j(XiyuIuj&qi#wqnE{o1^7A;7QIKP}li<85T z70aU2nO+txAMUMVAAx z=n4Q9tpi}ul>jVS5AZEolpNY=f~5UsF?^aVYVU4AUX>hiemRS-O%4Z3Wzls^FN>}x z%c2{|vgk&#EV_v-i*6>%qFcza=vJ~Ux{WN0ZYN{W9RMu46M#i`0kG(902bW?z@mEr zSacr%i|z+t(E|W1dJup`4*{^~VE`6w1Ypr404#bGfJKi1u;_6B7CiyLq9*}Z^b`P# zo(5piCV+3zHOZmFO^~#s8ksm7WYHk^8?&2}BhD{p(R0b+fkR}`^Gq*`wvuJh3uIaJ zB3Tx_M3zM_lV#B>WLfkoSr)xUmPOmhSoAsoi{1cW(VGA)+77^?9RMtP3xGv$1F+~F z02aLqz@qm6SoA&si#`Bg(T4ym`UrqU9|N#xCjg5+0btRm04&-Cz@pCpSoApni@pH( z7HvrmO*28#8o7hmv$E*q1{S_djyS)ZMc*Wc&o7rn-!i={`i?A%z9-9~AIP%kN3tyX zi7boukY&-&WLdPAEQ@|2W6?eU7X1pqq8b1e{RY6I-vL}-*s#djyS)ZMUBJZH;2ihCQL7j(#W!?DOnaZBg>-ZWLb0|Sr)Y* z%c7QKS=5Rwiw+`V(ZK*LIs|}4hXSzZFaQ>{24GP-0E^lHu&6Bni!uOM)DD0}?EzSH zH~@=|0ANuE02XxwV9}8PEIJB+MV$ax)ER(9T>w~gGysb-0lq~I!=V}zB(2i@Vp^lH zf2H5r{rYTHIO6^&-on-eg(Shb)VZA)G6FaV2&0I;YGfJNm1EE)>HqG15vqHf{PaVAKb`{KQDcUiR3-8>o|jyS)Z zMWe&viqW#@1g4ioW5}}TM6xV8i7bmM$g*fGSr%22WlCvWzjOSEIN}ci+kMOOf@XdM8Ht^{DwdH@z( z1;C=K0a$bmz_;l1aOg!7ByEiQz3U~isDBd+8^RIim$T@GaQK^(WYLXGFN%c7gf zvgj7FEV`8}i*6&!qT9)`=nk?hx|1x6?jmE+-2g1Q2Y^NQ0l02bX3z@i5LSo9zO ziyi`C(Zc{N+6cg+M*vv#C;*Ed17OkP04#a}fJILNu;?iO7CjBXqD=rS+6=&=X8>5V z1>jqBT{zUZ!YsPQbwAh3qLbVckY~dY=a;kSg>X2lQWm|)^s?wBvMhR;EQ?+t%c57w zvgkFkEZRnvMX!@((Hmr0^d=dLwga$e2LOxS0$|bG04#b3fJN^Du;@Ji7QGL^q7MLA z^dSI?J_2CT#{ewa3BaOH09f=X0E>13u;?=Y7JUxDqAvhg^d$g`z5-y;*8tz5=fk1l zCP><2?ndKQSriOf*d2~Iznn$ihr_3ilSMx;y)62XEQ@|3%c4DGS@bhm7VRa=qF>0e zXdhV?{YsWaHDoOM4S+?z1F+~102ciTz@onZSoAjli~a#%Q6NQ^?N}59U{MkPi$VY_ zN(Nw27=T4704$0CuqX<^qErAD)dOHreE=3U0ASGp04!<<@Gbf_99nOJq&0UIeJ6`{ zy0hy>DG}$Fv#4oG_=yR!s2S7CqUK~-bRbz4wIIu)mSkDfiY$u`BFmzK$+GAWvMf53 zj75h5u&6Zvi_!sD)CPb>Z2?%60l=bm04!<`z@ozeSabvci#hEiH-K+Zla$b>CP>=abQ32n#lOYeq>p699b3}PnJd5WLcC$mPP%^SdR^JTz3L8Py=2jDcMEbizbn=XfgncrU0;LDgcX424K-N02WOL zV9^W!7R>};(JTNK%?4o68~_&01z^!U02a*$V9_Z6EIJi{MGF8}v=D$rivU=38UTwH z1F-0HfN#+WDWMrANZR-AIocRmRPFvAZAnVR`Q1EM!vMf4_EQ`)2 z%c2!zS#%Cr7M)9$MJvg&Xcbu&okzx^^8r|N0RW3G1Yprc04!P!z@m!*ShNO!MQZ_A zbO`{9E(KuGWdJO?9Dqev0I+Bs0E?~!V9|O27F`9vqN@Q|bPWKDHUO~bS^ySZ2kbbU(1`Q1ENaWLb0@Sr*++mPL1vWzn5v zS#%d!7TryjMfZ?p(Y<6Wx(|Rw_XDu#0RR>~2*9F;09f=e0E;#Pu;>v07Cj2UqQ?MO z^f&;Eo&aFclK?Dw3V=mV1F&cl0E;#Qu;>{87Ht7w(X#+7dJcd^&jWmmZcGXNZi1wp z8#Zxnl11a)FB@%5i8#NUMK7m>51uWHUSWD!^eR~vy+)Qr+sLx$b+RmagDi{QB+H`h zWLdO>EQ{VEW6|3HEP4lkMehQz=sf@yy$`^m4**#7Apna$0$|a{04&-Gz@kq8SoA3X zi*^C9=raHoeGb5)F92BdB>;=Q0$|bC04&-Kz@l#eSoAHxx9G)`P__w@cC&kq_L3}G z97JwgD2rZlf8v-Hi8#NU zMF&R0H_w+vEtp;wwIs`;R%BUp5Lp%-OqNB5kY&-KWLb0=Sr)Y>%c68L7PSFjQCk2O zWdN|K9RQ2k1F-0D02Unqz@iQSEb0irq9XxVbQA!KIsve#GXRUa0I=w202XBeuqX?F zMO^_{)D3_|-2qtC1As+60lr1eBB7T}khHb#7E$wvf2BXe9npH(cbuAE&Z54N@OP)m zqGOp}7WE^`qT|T2=yJUZ&9B}C~bjRl;`@QV`Nb{-NKki#QEhc8XF0BTO^ArnO+uEk!8_1vMd@; zmPHfDvS=b%7EL0{qRC`gG=(gSrjoJfWB?XT17Oi~02a*vV9`tf7R>@+(QE(~%>iK1 zTmTl$17Oj702ZABz@k$DShN6uMGFB~v02ZAAz@ln^Z_!DS z&`1*`?ML?+gMl{i8#NUMQ26A3m40xvzcBNtsu*ybI7vjT(T@$NtQ*c$g=1> zvMf5EEQ>B6%c2X(SacBpi&g`$=wbjCtpQ-sS^ySZ0>Gk60a$by0E;dMV9^x-ELsP^ zqALMdv>t#(R{^l-Y5*2p1HhsU04%x|fJN5qi z<+5n9yLWw4B;x#X7Tp#JKea>_-Olu~=nk?hx|1x6?jp;gyUDWX9-u z$+GAHG8R1uz@mo$SoAOei#7tV=n()GJqp00#{gLLH~@>D0ASIR04#b6fJILOuxJwi zi#7wW=otVOZ2@4>vj8l54uD0^1F&c-0E=D#V9|>J-=bS0q0dZ^v_IVE7u_n0K63Yq zUW!DVU(TY}BH{2-S+tGmWzp+oS@Z^37QIQ9Mcc`;Xa`vqy+xKqZWDgcY>0kEh(0E-#`u;>5)7BvK5Q6m5r zH3nc&695*a0kEhk0E?Ode2ex(LbFVew81%9ZHr(hmmDbYqBg#C(EKXWLeafEQ>P8Skw-HMePAtbT|NujsRd$2LKjz z1YpsT04zERfJL1ESkxJSMO^?`bTj~qG67hW1;C=N04(YTz@qK|Eb0NkqMiUO>IJ}} z-T*A>1Mn?s5e+?Lf~39B&ctaM^{@0ty1yhkCK_>mIg5^qhTmQxi;ib{S(HtdMLA?y z)SoPia>=r209h90k!4XnSr!c>%c24@7R3NqR0zPLA^;W@1F)zBfJK7nJuxK~{i$(yjXe0oOMgg#BGyscE0ASG=02ZAHz@n1?zD37I zLw}keX+JbKar()kNiI}GBhD{p(YR>%(3P@iJk!gf31nF`kt~ZQk!8_jvMicHmPJ#^ zvgl;8ESg4^MbpVxGy{M|GXYpM3xGwl0a!E#fJJiwSTqlSMe_kzbP52AP6c4m0ss~* z1Ypr302ZAFz@o(fEIJ*4MN0r!bOr#6ssUKE6o5s`09bS;z_+L}8tQL?q+N25iBlzu zqVDF=@@T~Q?J=(RBbUx*mW<6DBXP|)~(Tq z^UGOuXEc241+wTark6!`lV#C8WLb1CSr*+#mPPlIWzhpK<7QG0-qL%xMW6_5IEcyt5MIQsO zXeR)RJ^^6SrvNP41;C=u09f=n0E@l=V9}QVEcyz7MPCE3Xg2_hz5!s-w*V~q4uD19 z1F+}^02ciSz@nc3ShNS=TeK}2YPQ-ey2kz9_3N^zi@TBib2Q@oau)p>4fj|hi)xr& z7X3z+MZc3}(H~@4^e0&s{Y92Vf0Jd=KV(@HNY!<_EDDmbC<%Z?ApjO71F$Fzz@iiY z7DWJ96a`>WDgcY>0kEh(0E-#`u;>5)7BvK5Q6m5rH3nc&695*a0kEhk0E?Odu&6lz ziw*=}Q44@?(J#@^XcHvuy>t_2pDcRBS=2H$;{0+J9g-S8?GjmZDAUWL!^pCzHCYy= zlVwpGvMg##mPHw4S=5d!i`tWA(cxq)Is$-29ROI=5r9QU0P02XxuU{PlP7Igt& z(a``b$^>9h766O70dIPYi4*-jf0bo&I02Un!@GUwh zHMGG5NjuPe-2TC-{+0f%O)T_FjX1xYMLDVAO_#}{{!A~6a>=r209h90k!4XnSr!c> z%c26ZEQ*n3Q6X6t6_K&17=T4304y2=z@kzB77Yeq(GUO@l>xA*9Dqeb0a!E)fJMUr zSTq8FMI!-NGzx%4qXAfS0sxD~0I=vp02ZADz@iEO7L5g9Q6<2)==jvo7bZyBp|1PM zmPMoOwQyBx#QEhcnwT1ntdm8Pm|hl5Cd;BJWLY$oEQ?Mi%c5yySu~w2i)N5z(M+-| znnlK<*#In>1HhuW04$mZz@qs8EII{%MW+I=XaN9=76Pzn5de!$17Oi&02ZANz@jAp zEII>#Mb!W-S_;6TWdJNX6M#j_0a$bv0E^BB_!f;%4Rta>(mrvQWfNpkJ=YhlNR2qZ zoJFfr!zJrw(RoZSi_Ry@q6^5f=t8nAx`-@`R+DAX#bjBuhAfNLl4a2)WGuQAfJK)9 zu;_9C7F_|rqICc)x)Ojz>j7AF6#$E_24K-O04&-7z@lpbSacl#i>?P?(G37Bx)Fdy zHvzEdW&jr50>GkM0a$b!0E=!1_!ga;8k%E*q~*Ck9$G1j%H1>lJ5nRgFK5v`so^zO z%c6UkUKZU)mPPlIWzhpbyy1WD`Ue((BjS#*c9==Icy^UGPZBQ^Z)23hp~arYnK zQB-f^K0cde5=c)d8(IieKtd8a3TjA!NJv78fGtu&QJN4G5ET@A!``s>-g{Tklv*-MdvuG{3S@aIMS@bTsS@a$`7Oewd(fa@_`T&4M9|ExGBLEhC48WpK09f=X z0E^ZGuxJASi#`Kj(dPgx`T~GOUjne`D*zUK4Zxy}04(|jfJNT|u;@Dg7JU!Eq8|Xx zqL*8Re-}YA*Xo-dub4%{^djlURtf5tTJ%dRzsn_N(XW&@i#C&+MZb}oMZc4qMSqZ+ zMP8!K+|8m8xmgrPZWe{f&7v0MSmXn+C?0@C2>>i=3BaOO04z!bU{MkPi;@9Ylmft_ zQ~(yG0k9|?fJGSqEXo96QELDewE0E_wouqYRRMg0L-ln20~d;k^|0I+BP0E-3!uxJnfiv|O* zXb1p{h61o?7yyfg1F&cZ02b{Cz@iZVEE);GqMZO(v@^h2)HyMHtO$}>qvB*Ix|#lu zn(UI8pnj=E#fknkSC~a5lsAh?$<3nCWu&7ul& zEUE-xQ567-#sjdZ8h}ML04%BnU{M_ai*^HG(F6b%O$1=kBmfre4#1*409dpq0E_kl zVA0+HEUE`!(LMkynhe0ADF7^*3c#Xi0B6yt#PACuNantJ5-T!`7U^GxG$badUuw~; zME{$s%%XiMZx-!GZWhfZH;d+wn?-ZU&7yhaX3>0dvuJ;EvuFXiS+tNGiy8q~vKmZmk24K+=02VC;V9`MUELsM@qJsfgbO->84h3M*asU>s0ASH!04zEjfJG|- zSabvci;e_f(NO>_IvRjQ#{ir~GZMq?t`>{V=p^FIG>dM~|0Fs#F+u%Oi%v}RhhA$I zokV%FXcf6xbTYYFbPBmybSk-7bQ-x?bUL|NbOyOubSAl3bQU=loejXEa{yR$E&z*G z1F+~k02ZAOz@iHPSacx(i!K6S(Zv8Px&(klmjbZpG5{7`4#1)-09bS-0E?~yVA0h8 zEV>4OMb`qb=sExvT@P>;9iJH9Qv}HztbccXf?3p4FOqIZOi;hnqFWOEgReJ>Zl%0g zbQ`%@bUV3ObO*UvbSJr4bQif~AOMRV0$|a@ z04#b0fJJKnSoA0Wiyi}D(c=ItdIEq&PXe&$DF7Bd4Zxyj09f=a0E?ajVA1mcEP4Te zMK1!d=p_Iay$o;`-IN%Gwa{v~70l=a!0a)}E0E@l`V9`bZ7JUQ2qHh6M^c?_;z6W5@4*)Fs5r9QM z0kCKjz*+QKVtBm>lKH6q+sEr>QE7rCKPM)rUuw~BiGHhF%%a~ZZx;PQZWeh-Hgh+N zLgZ#q9JyH(CO3;(kefw5xmgrXZWbkwV^K>07PSIkQ6d0~k^oqg48Wok02ZYJuqX|H zMd<)6$^c+dCIE|C1F)zK0E^lJu&5mXiy{Cl$^u|fdjJ-70ANu^02XxuU{Pm)v*_2v zaDNdb^NH>v&StadMZI~Hos^({sYTtA{L0(RqVAM8i+YfoMLo&QqF&@?(RSo!QEzgy zs1LbW)R){W+Me7j>PL=6xd1Hc55S^402bu~u&4llMFRj>G!TGAg8*1G7=T4X09Z5> zfJMUqSTr1fMLPhnXh#4RjR0WLNB|b?1i+%50a&yP0E-F%STqXYEXqj=H;N#cALNKQ zU6b5Q|3X!&C@DexQj10>`KRAu7LB32SyV=D7VS!I7L6r0i^|E(qH*MAQ3bhKR7q|Y zRgs%T-Si%OEhcZ(pIC+fSgrDoCT`VS#9 zlM>V~wP<#d|Mp#G(HzQ~MRUo`qIu+I(R^~VXn%6EXaTudw2<5^Y9u#{7Ll7p2asdY zfdDL848Wo#04!Pxz@mcyShNg)MF#`0=nw!F9SXprT? z799z|qN4ydSO4uD0+1Dr+sCWXDb#iFkIch~!wMK8%~{s~D5>X%w{ za+2TmUbE;F%9}-}lAA@Rk())Qlbc0nkefwklAA?mk()(llbc27kefy4l4H?o02ZAG zz@qa3SabmZi!KCU(M13(x)^{(mjJNnQUDfR2Ed}r0a$be0E?~!V9`|oEV>$iMb`kZ z=vn|4T?fFT>j7AF0|1L|1Yprk0B6xjN#RlvB=dE>pk8GbU7*)RHzy^iUux0qN&bxc z&7wOfZx-E2ZWi4|ZWi55ZWi4`ZWi53ZWi4~ZWi57ZWcX2ZWcXAjztdvu;^g`7Ci#M zqBQ_4dK7>~j{&ggaR3%Q0l=as0a)}D0E?amV9_%GEP57zMb81S=y?DZy#Tq!afms<38l7HQUX3<*8 zn?>)Cn?>)En?>)Dn?>u$&7$|o&7u#;&7u#<&7zOU&7zOVvFH;37JUl9qV)hQ+5o_! z&j48TIRJ~k0ASIV04(|nfJI*euxKLyi@pJ1(YF9B`VN3a-vhAd2LKlR2*9GB09dpM zfJHw8u;>>67X1ov7QLAien|w$+^n~&-!hA?Qj0bxC8%F&k(ca$_pn(MO17E2SrkWZ z7KO>pq88+4kxyRu&5&di#h?Ys51bIvH@7s1%O34 z0B6zfN#U$V#G+1mzvvIMXp$<`H90~3Qj2;f`@zNSX2UV7IjY!?=6C4 zHtOeH_egd#{e}A0Y-w_W`lS}_n(QC?xLGuo@@7#vxmh%h+$^dfH;XFC&7vxDvuHfI zSyWAK7S)iOMYZHuR0qJK-2hlL0f0pl0a!E%fJM6luxJke7VQbZqP+lEv^M~Y>H%1^ z4*-iM1F&cc0E?yquxJ_piy8n}G#!9NGXPjL6M#jt09dpyz*#gVIee)IlG#IV5tW%m z-|7d5?3bLNeyK(ClKn@YG>hg_-YnXm+$>r^ZWb*hH;Wp{&7wu*X3+uUX3>G=zMZ4 zx&VMh7Xq;8A^;X$48WpG09bS>0E;dIVA16OEV=@KMOOl_=qdmfT@ApZYXDeuEdYzI z17Okh04%xzfJHX~u;?ZL7TpZMqFVr1bSuDFbV_nKUj)fKLjUgiRI}&~eQWl%Ro=zVgt=mT=I=tFX|=p%Bo=wouT=o50Y=u>jDXgxU=Z2(}=X8$ns*N86{3Bt23R)GxKDcZ%QrRkNrM12V9|~MEE)m8qLBbB+6jO~I|Hz27XTI&0zMSX2zaq7ncWl>)G6 zGysdn0Gvg=Qo>_Ikjxu(a=)Efv_UN@OG!|_)S_`I{;b!{q6*5JMU~`cQ5CsaG@jfn zswOv!YRJu^T5_|fj@&HTjod7nK#oNd0a!E%fJM6luxJke7VQbZqP+lEv^M~Y>H%1^ z4*-iM1F&cc0E?yquxJ_piy8n}G#!9NGXPjL6M#jt09dpy0E_kmV9{&<7R>=Ti^ise zPZU8iAJMs6ZWf(KZWf(SZWdiY zZWdigZWdicjzt#(u;>y17F`O!qRRkSbU6Tvt^i=sl>jWd3V=md1F+~C02W;fz@qB_ zSadxAi*5j5(TxBsx(R?qHv_Qf762CA3c#Y<09bT80E_MbIEzkC33pg47WL83-ao@E z+Nc)YnUbJ>sYUmu_&dI97TrgAv*>g02VzDz@irbSo9(Qi(Ud?(aQiV zdIf+*uL7{>H2@a94#1)}09f=U0E^xNVA0zEELsb27Tui^-bVz<+!zsY?lFr#)VD+4 zNl8$@)S~xO{1xlWq7Nu<7JW!=7JWo+7JW=^7JWi)7JW)?7Of{Yi#Cv(MW2zIMW2&n z(H8(L`VxReUjeY_YXBB)1YprO04(|zfJNT{u;_aL7X1Lgq8|ZR^b-J!HUY5cX8;!c z0>GkQ0a&ydfJMInu;_OH7X1OhA}`e@=2#R0IE&s(312RPWcJoSZ(L^I}f5YycK@0bo%M0E@Z; zu&5gVi@F1_s0RRxdIGSh7rSp?j^rJ$zOHEL})S~TE{gjW* zqJES&i*m`$qW*fc1z^!=02Yk_ zU{M(Wi*^NI(O7`9s84EmfC!TLnZ9+_*DTsi-wr8HO;EqoqN-HC=2Nq1Jmt-zYI3uv zhTJTwB{z%e$jzeN$jzb&xmmP3ITq~!z@j|?ShN=ai}nU!Q9S^Q_5ong zWB?XT0btQo02WOHU{M1Ai>3pxXa)d_W&*Hi766O(1z^#B04$mfz@j+-ESd|zqIm!; znh$UmRiuU&iy)cPvPGOqvuK#U1G0Z=g8HQvElTyz-e49TKzXz1KytHaF}Yc^gxoAz zN^TY%L~a%>BR7iH;7M%#dqLTnvvR02W;hz@lpaSadA_i>?D;(e(f< zx&eSiHv+KeCIA-Q48WpW09bS@0E=z|VA1UWEV=`LMRx+Q=q>;j-3@RSos}AH@r78l zR{!q$Y_q61PLg|46VxxY=z&zf=T~OYgOoRm9wIl39ws-79w9f2){vV;kCK~3kCB^2 zkCU54Pmr5MPm*KNQvfV_8h}O50I=v;02Vz5z@p~?So8t_i(Uj^(Mtd&e zX3_3pN!Fz%s9$Q)N2&gP8_lARDQ^~iLT(m)N^TadCpU{WkefxHk())Ilbc0fkefwc zlAA?ekz>)<04&-Fz@l#eSoAFbi@pP3(f0r>`T>ANKLW7mCjb_00$|b404(|ifJMIo zuxK*?i+%%O(eD5(`U8MPUYbqYu_y$p5W>E&YS(Hg`7PThF zqBa05Y74-kb^t7j0I(0h9KG21sSLH$yT z`ltCneQy@!QQj=dCpU`<$jzbw*fc1z^!=02Yk_U{M(W zi*^NI(O3W$l>@M78~}?d0M4R*Y2i*kh(+D>c6F{ZE0OaKZ{ZK#8MTY~hXe9uPjsRfMkpL_@3V=mN1F+~A z02Un!z@p;-Sadu9i%tMw(TM;oIthS9s{mMZG60KC0btRo04zEUfJLVRu;>f`7M%&e zqO$jFye9D_e7m%Ap7m}Mr7m=Gq z7n7Ssmynx9my(-Bmyw%Amy?@CSCC`Tl>jWd3V=md1F+~C02W;fz@qB_SadxAi*5j5 z(TxBsx(R?qHv_Qf762CA3c#Y<09bT80E_MbV9}ibEV>JTMRx!IL%M{-7I>9@@CN*aO02XZmVA0P2Ecyk2MZW^D zXfptdegk09?*J_N1As+dx=q`$CUuqYdVMO^?`lmoz`t^h3R2Ed~3 z04(YOz@nZ2Eb0ZoqU``!)Ej_BeE?Y07l1|E1F)zcz*&@-9)3^+$-GxDg_6?UO#cCW zYc@AMLH$yT3ex@eTbM-yC~p=GBsYr&k()(>$<3l650B2ENdN|$}i;mX!(ellr27NcSIz2)CQj2y= z_qR(hizZOsESgAe7EK~Ii*_eBi}oNli}oZpi}oTni}ofri|WbEqJ7A*XfgncrU0;L zDgcY70kEh6fJM^*STqBGMKb|dGz)-5`vS0NKL8fZ24K+~02a*!V9`7P7R?7>(f$A| zS^&VJg#avS1Ypr302Unpa2D03hs#Bf%q#S-_v_4}ZaVEhFg-#2Qi~2s_vf@Si z3&5h|09bT90E*nssaf=lTC_SnLH$yTE=>1tNivHrqP$sjF}YcE z3AtHxDY;p68M#?>Ik{PM1-V&tCAnF26}ee-H8~bt1Hhtd0a$b$0E?~%V9^Z#EV>bZ zMK=Mk=w<*G-2%X(TLD;f8vu)L2Vl`104%x_fJJu!u;^|87Tp8DqI&^YbRPhV?gwDe z0{|>~5a292KRx`02$ET;Z{uHJ7M-O35b{uZg8HQvJ(}+SoMIL|MtQU7adNZh339XO zNpiF3DRQ&uX>zmZ8FI7eS#q=JIdZe;d2%dz0f0p>0M02aLrz@k?GSoA6Yi(Ug@ z(dz&#dINw(ZvwFBEdUn14Zxzc04#b3fJN^Du;@Ji7Oewd(fa@_`T&4M9|ExGBLEhC z3~&}bk{-@Z6^nZ6e>JW#i;mNGV?RkxP`}io&(i&!)6JsKDQ^~iL2ed(Np2Q>MQ#>- zO>P!#BsYt`AvcS@B{z${BR7k_C&!{609f=R0E>PCV9_Q37X1vsqF(@5^eX_1HUqHe zHvks>4#1*609fQ@*t8vsLI5m^17J}YfJH3;SmXn+C?0@C2>>i=3BaOO04z!bIE&V& zho^}knJ?<+7i}<$4oZ>H@%`8~_$|1z=G(02XxzU{MbM z7WD*RQ7-@%Z3n=j-T*A>1Hhub04&-bfJOZPSdqIV8cuE&?Lcl8?MQAGjUYFR zMv|LFJCS42&Hyah1%O3`04y2>z@j1m78L`qs04sTr2s4%4Zxx?04yp4V9~AsEE)^I zqH+KhjRRm&1ptdG0a#Q8z@qU0EUE@zQ4Ii#Y5~ro0U6=*(Odu)%>!W3d;k{h55S@Y04!Pv zz@kO~7A*o`(E$J~IuL+Givd`)1mG;1kP#jtf@I#ISJxBGq940TvNR(>{Zfk#$?zw% zH;WFXyjirI+$>r_ZWbLzZWbL*ZWgU1H;axSH;axWH;axUH;axY$D(5ZSad7^i;e?e z(eVH*Ist%1CjzkOBmfqz0$|a}04zEMfJLVQu;?@Z7M%{jqB8(kbS40c&H`Z3*#Im$ z2Y^NA0&UU_dH@#P0KlRf0a$bs0E=!0 zV9_lAEV>ndMYjR4=ym`W-2uR&I{{d97XXXy24K-W04%x}fJOHKu;_jO7CivKq6Yz3 z^bi1x9tL31BLHX7MH%6TMUc!X$s*3hX3@!N(VC0|^-C>!BE$c%vsv^c<;|j}$jzds z$<3l?$jzc>$<3nY$jzeX$<3k{$jzb`$<3md$g${U02aLhz@k?HSo9hIi(Us{(Hj6P zdJ}*}Zvn9AZ2%Un1z^!T04#bJfJN^CuxK3si{1xd(FXu5`VfFc9|5rFV*nO?0>GkA z0a&yi;4FG9Biu4uEE=i*1M;|8bfW%OD8u&5UR zi?#z`QEvbi^#Nc}UjP0B{ziXNFG`K{Aih zX<0_5o9Uk~^7sQY6VxxYXlSN?TMx5n80F2P;pAq~4&-Lhj^t+12y(M%B)M6%6S-Nm zGr3u`3%OZTNRCCL09aH6z@lOR7L@?7s1$%jqXAen27pCn04&-SfJI{gSX2(cqHzE$ zssLb7B>;=609Z60fJM~+EUE!uQ7r(A>Ht`@8vu(Y0GvgGGsAC*Aeo!>t+OF!(Y3*Z zEi*y=Qj7M?^ndMT7VSlOvuJN}v#6fjEZT?MESgMi7EK{Hi>8vBMbpU5q6TuaXgWC- z%>ZE0OaKpXrAAm&{0I=vn02W;Ya26e!8J;eJWL_$%zuYWJRi!S@Oi;hPc3zy{z12 zZj8J-*Yj?Tbll(b?u<-c=y~@>u2|%G4@SN`(DT+r1}^oyCn8IhdEPUT2M+PP7b5-& z&wC{@_HfU8BXaT)p0_sg`ca;@F4Fl}&-*Ac^?1))AGzv8&-)_s^(xQX7#V!3=Y1bJ z=ycE96nW@O&)b}paE|nUC~Mqm*#V)fQ_q(@5XyST27^W(erQhsP8_LqJW|$bt($Ci4 zGnAztj=oPQOF!LuS}03Do_J;`OFv(Bb|_0fAas5xOF!YUF_fhr(YH91rJu33ER>}m zlC?aPrJr)NGL)qsQ*(4EOFw7i_)wO9P{gWGmj0*zX`w9rSM9SxS^B@Wt3z4(&yp90 zvh=^*E)8YrzbjoC%F_Qgxi*xg|1fZ4C`kp0p)CEI%X>pv`bTpQhO+dp zp4No2^v_nF2xaNt9Xu1t(l?G@2xaLzf3JkH^sSpWLRot6eQhX9Z=S9TW$E3ok3v~` z`(k}4OXr_ogtBx3u`!gTSAgG#vh)+G@%X594)>hKh%ZG-%j*I2{2|rJ#gQ$E}`*$vOjUqm@c8}_>808dG)L%T|zbS8OQ#7_1(+7 z938VxkV4tFTj>$~gVKI-ulGJJmBR5Ex4-!ONsEKhCw%bc>ZMZJ&-nV)`{#MtVz_sX z6s~e*;u<|K`w6S(2*=_xKE8j|y;4Xjy7Al#jz1`<=#(o@*(@!q@spoi(7LUcv$t%_ z721k@<%w>?BeY^uyPwm8!dI<6>OrYSwqf(l&z&Oek!^VXsgE`u>}9W%Lb?sFxk90Q zFXwtHyxS_w%(KmU`tkF24EkjEB}4ZJ>igpAw~sj_XiVz?=g#-C->~X>x*}Sgc<0*J zQg(v2Zy%}~=MU{0RG0MhV`HT{KY7_xceM;^d+Tud_@C@vQbHTIu&K6P1qE9>(_T9% z`daq8VYh;ZSwUvc)E$Bj`0|AN&y;4$8cvva`K(|K>0PEB=w*K-MQ+v2cSVA|aI5?k zhqg00-(0xnhF?xm7veK6dh4ARw4V5kS62Lf(ZNASu3YuRPX~KBeSK@#5P71-$58y@ z^H=;JeJ(0}vFAlSf>s>8?>PlQEB1f&tbSg0trXGi+`|>oURz9cE3LY-+-rWus?|pp z2DNQIvtO5>E$dHu@(JAu@fj!G{Kcb(c-a?Qeb+SA_aOB>WA%M%^(FV2ThkD1-10Y8 zT_T%V?PvV*%VCW{^PU*HG2Y8wZ`J+MRGrt-)E^~J9+IX<3beDT;|>yytBn;0tSWA? zyfWU;xa0b7=LPLOZOt2BX?x?A$Z26WS@=1rAp0D7qW!kQm6GFa;{y-L@h1HiH}+1~ z>sM}CbDVQOJLSt7FFQ_#BrS8RE8}OJaK=g6InooCKX;WLcz*Km>y8YLyX0Gr>pR=a zIa-PY2kkHNL|gu1P_`y$d7@leDEospJa^|wzv{jVwxL=Y9CY&+XZ-l#QZFY}mJXV} zr##VSj2K|Xe6aE4$Fx{{#t*L@wpI^4aeHmt^q^C7H(a%kmmQz%+EL}o#I^j{%gz#} zt3TW^Ke=?rAzgzW=(Jat89^=YOr0`2Xv0Tq-}qg|piWZcZ7GtIBTv@rlW*n1=m&X{ zt)FYGt$K-8t@!o5!=x?RJHLN$La?ioSI=G5Cumh|oAY~k*{?_$?VXQZnNYEp{fQuL zRQrK83ha}5XL8V}(>8bM5bV%!}<#@a3kBfU;cWFJd=@adD_@gFXwkD6CCRuZlI>;54<0E^%p_3d6 zy6-Sy+R}$v$1n5FC<$76>iw(s4!SSy$P3*r{PvOG?>yAYIZ}$m4U=9wR-UBElkDrQ z;`K2VKWG(q8f5$TvsYjHLe-4V`0%y$w;mc)eRIW7H?oX>q+OPmvqs8v(h6UYC%Wa6 zTwyt(OnR~^DEq>9-@oqm!upyUi-W!T^~VpryV%QKn(oS+K$*k4_;I==8S8G`;5zH2 zwXZ&_heCYD(eIyg;Sw+V3@M|XbfGJwowQO;qPpr=sOI2S;o-rm@7{3c2U?GxJY(J( zIVz=^TmLxs)@5Gyl~yKxuuQDyT~fyGrm~=?0RR^ zDJQ&exfnG_3I#iAm^|sD{ko@BeKJ+|_Oj<%)oUE{lMBtIo^5)(Xw0&~3kddZV;S z3LSsg+3Vz)6uReuv+j4h_vt@AeNa~Qf|SzEJ=B%b&b?gzXjNN$3oUNweYaeyNIg$( z{Cur+pVaf+WvdR8zLjHY?@O=V)ysZL$_$b2`-GL>@ZF6+%it=V|MeYL?ki>d z-7P5cLFHk?yzK9-NC#P!TpRhxDI*>a2PNKLwo=b$@foilw&DcWt2aG;`PtIiEV+Qx z)l|AN@fj;Ge)DYCF+cqL{F|<0EQCg;RG(+A(Q(Qkm@k7WRsqDgD8olK2*(aOzG;N%FE= zEF>_Yx0LE6>uwo5k+XNJ;E7xwCt8KRt1u}PDr>DplDkTEc~T@LO;)Zor?w6yB{kKV zmg0q5(vqa4l%(XOVX}C7q}fs#vQ$iaGcC2XwYDlH)pfS9DuY*>s%&dj+EVSLkl)mf zNQyL6*PInRk!@=~C}y2Iw;$17rZfFRJGZAH+qExioe|26-zDqJQSEiT9sQUBagjSl zNuPI$t;AU8Sf<^XeavAY*k>H>ZCk^IOq8gy3XUXZ2!^yncZ40<1w(RaZjW9PLteFpw`3R(c@s3ylu>XQ0m z>Kq}S#(DV{Xw>V(1TS%UsL|_mfhNTctO$T6Q(~7mM=s93mme*zQ7_h_#WmUNfGe&^ z2kGAE5^T8^r;W+cmfb8!U(uK-7yBWv_OA-aF)oYgLzc0J_F?QJHovL29I)O?QY0?) zYif%0M6^%(_s?4}IdA&H`FRT$OwC(Rzi?_p{rm;<8XKlIHcZQ#x?sut#(4^+HcVTz zpkZOmYr4EFJv?vzf?0EBHO@Mq!ONRDZ%#wrIHZGbrYhGUCym_;y&YV1J?!vqoQ>WHXUN9%GAisWK{eb)d1@#5_3UdYK z&Yd^6A-7@jlv%k2`TYmx>dXD*CuYpd zD_k&b(X6@iismh7$c^^J;>HC*m$)9OS}<>4>GOqoHS;Gg*spZa-1=JCmKjyE7cH!> zE*vs$FuO@M_Ft_1el>HMZ&=uWrn)O4 zOq(^gQ4*QwihlJ|=gpZjZ*KkM`Ll$H)-^>X_0lO*ivli822}K%rK@ttlYi0kgJU5) zFy#BK|L)<3;=?mSe%o;S{(j35erAR5&y4TaI=*#Ij^DbA@5krm`I7mW!E<>kmBr`z znL*sii)#^T>nCYQ^Sf#g9;E$cu>pQhNi%!+t@~1_NAy|GKE@&)2j}`Z-Tln)fm(>V zw>5Ta)|Q++wm7wHU&Aa_&rCn{&Zc@4QW6;L#bYHV3Z&k%PJ^ajQe@aWD)&G5i-EMJvFKDRW zwU_k#(xB(_X4w8^Q~u-rZL9ltr1Vv{n0+iQVdwor*EMU&7HjU>&Ck>hY+n2?{BrB} zbMpPx+y5V0?Uvo_ca7>$fDZq>wVk(aYyV24o&GENwyo5^xioHV%{qc(DyL~gk^?5b zb*}VX^ibKR&WK%QTxoRR``aTocKLrk&fDY` z&)Mm}8rt&z>)!h3t=DtP*7ubzy=^VowxzeNC3Nh+xsGjX(ZAOc8E1nt;y;{ggApe< zugYHf$5UbS{Q942+v5ECZ+6DN*L7T3$eD7hy6}H?Ms#Q7PO=LaEs4!fsee0ijr^aj zKR6@*H|MA=R;$B8)44G^h;042F>c2;e?LP0&(DtkrZ3y(`TxnK|N7E9dT!gMvkl|$ zwspj|?Z9nYdfQq;`?qZ!|2V?B%l!Xhvhi>17kA-d=LF6T64~ypc|Evvqrlc~S1|9} z)o)c$<)^wSW>-HWAuhgUwcjy#5?(yQ&(LRXUKST0(j>=k72j<}UOPWozL2d| z4?nq6@LMNcGHud}_V{vHu4xYZHv{TcojCvMVpZ2*8!RKZ&cVA*ik=UdjAu(jT540n zDI@%LlC+XDuSA)IwvrP-yLg$|wvuYxOI`gQGP7-`$j-cJx(R814-HZ}NVU2FR)UiM zSgEVLn^f-lHWc68)%5?oVzK!zyWxM*V!EXKzuMmXZ7TJzb^A`+)QoLw^tRQ#Elc;v z-#U3`sJ;Kjz7O_?D79t8i7h#K?CUa;H64*#d(gCzLo0JvKSf5e;AUAXnZ~va`6)V5 z#mD7#@Vf-hbSP`9&lu!vC`)leS-K2mDLwr3PQmZK(vDtsoZC?L&%?o1bpHscbIY+~ z@q<6mGAzN}AmRjq0l;-!=Ag>0gE%hO;X7yqltLz%IM2>}MOSYv&LE(Qz+5fVK z{;Pg&nFIwl4zdp*GaU6ZyqE22O!$Ekf>W(XDy$wTz_$;^O|BZ2S zgjDTDU|EH0k*uhT9zc_ zOX+Ru6~BwD#C3}HFlE^gTCi1{pj}a>&DXP?>Xso_bpLgS#MCxJYm>Q`?V9Mbwn3Nu zr5ZHgU+TL4vUPn_g0BAGKb1qX&sH6pT1CHsejm37{=ULsjsJ0rw0y<@zmJ;K)z8zc z!0+qK2(o;?uQtoQmOIez8?1L^u&cy{F1d8H#I4%#*&}6#%hq=JtAmt15x1+|IQ+*U zDyS!Wn=}r#X@K8%>$X?=neBCox??pX-rk!1`_={hn&DJ+0L!& zvHw3j+M7laH-`O}gQ<-mdd#=U(~e~ajr9A)xAnKp4cW#2g;BZgcWBsq5 z{>S6-f4??4x_dj@11AgoKJI`CG8=Sa2PW;o|5tsfZTjCG+x~ZJYZ@v4Q(xu|^82_8 zhpvp3G6+P^O4~dHh|e-)#tt3-QKg`X(V_i6HMn2g_=ufU)Bw3d(sVHW$5pAd88T*r)5E78Fv1Uoziib%xKdqxaQ_)wUqO2Kq=WlQ>6iTe za@Qk##nKToe7(WZqnjVmTdX#|{`EZ-x%F{rNDAm&T_(gGbtY*A{_^HW-1hP(ilsGG z^(EES^<@>i6_%G3*B4fgt{YcUQS0%-xRRQh!qFx5wUw3i<&_nqz3P(D^#z4RW1>qG z)z;KW`J&2kRplkMvSeLFnJrgZG^Tz^(}IQ7#q|}HwX$$cNp)>WarBj4tEAGpikiBr zs!DyKzN&0uNqK!~W%aniTDL~2s`=uh$}5Y;))yDn7S>nPjT==`t=myq?Uo)mEOx~e zmGw1sqiTw(%XG2Q%DRf;V6maY#sqPAvu0M8)KpbU3tdfvWEuKG+g?&#SQFE7`fXgz z==xE0rKM7TP1)`x(IS7^va)g7o53>LlcVxu8(LOTU&o4vTjL5!n=MjQJ*ld;QZ~7~ zyuPZktfIEWHhF+8Uno)j=5OGD`o>@jiklT5RW5(#N30s+WB|PWEz9VQpDuh3lu`(SijT2^0J6|}ObvZA7-NNowsD;=aA7CbFBC2H!5ip0`rX_Osb zS5j9}Un)HneW|Ljx~z6mG*zj`6;@2LUDs4au-j@XYl0ROi`CHv3=Y=MR@ic-1#*1U z*Ho64);C+YV0g2oiwZ01YpV+@YQ~k-1~pfg6c$ekHfB^aVXJEjrJ`V0O9z|Sth2JF zsJ^DQQu?$+bhLfw`leYWF~?JMgUz18@?g#Nl~pAb(brIURCU?tF|`%aqxCfyVSPzaQGLOvGCRzR znjMP4&{AAhIJ&;FuC}VKwtlzD@>)55qE&D-=%Av*j}BciM`v-#Ze{WpuA}N|TrbP9 z5j!5aLrGnnFFsV*(AoUr9et1CuFhfVRSa9nhOvML$OY!_F_ za1uM72AfnPCPW9x0nrW{71KGogPKCR>Nd2wPhyBgEK} zN%f_LWqOpe4{Ztk%U@|)WnHyAkz=g1ysW5c)DJAx!7SQ!1p}f7xE$(U<)X&o$&Hii zs}@Ze+pwf;?zD!*?x2)oa@wLfbCyKc7aSrbm1WHjrLws}@uEcw4rr*AKUj_~E@Sn$ z%4*$bI+(gT2Lwma?0Iu%pi>Iu37aMzT~pa~F4J>E^feott4qpDf&p9$ zmo%5n>7X4Wd%UdF^_*MFkeIaugOlz-9R`C_p0%=>T#O9$g+)bm)rCbi&PCfZMoxwk z3S~oU%f^++t_j}ysVi3!c(iD4?B?qda*BvHym&ydoj0pX zDvHI{m_a(agNuSIBy&c3aqf(U`i8mFW=)=3ug6lfva<5>lF^0bcF4)4K(P!AP3OYE z_vmRWW-k{EYi7KuGDd2Oxe_a8vt;LP;Y68^kz0&Tu~!;06a zFepb)M5cnik6`r_Ni@*swTv&cJ~J8fPw=GezR`+4Ckh=F0yqjg%o`ngUsJ z`uqb1=PsO|JFQ@dkjV?C&KxQK$aKK4+&TT{$iG5uKW*Xs?WfPr$(@mtTR9*nSN=n0 zFM&^w9;_Yr!n4X=lnIS0vXBqY7neWn-+aQ)UIOxkH-_m+Jw? znonVLf}xiaWio?s7andq1KDPk&zm>Dzzf2FKeeUV`MTM)@;Iq!ROQ4!l_)Bg(}A2| zb+`)p#tpf_(XD%{Ab&uN`33oM9LUxb42_P=(*4m&oBB+z`0C}XtsUn|$SE{`FUiJ)YMR~|C80QV1cVsCVGF-7&nSnmlSEMP*q(yrc7p;vMVa&B3kZR zu*yIYZHQ`8CRek&iwyPk@~@;#_fQJta$Hsr%s`^k5Gv3SFIF))qLdaE%MG6`X3~KK zy4KO+dh{x%X^vHFC(Htwd9Z2H3(;0{Jsm53U~o~;RkT6dw#5m(utsmbMep0lF%+#d zI_oPO72Jl4z7W%q)g`rmdEp(5nM}{MC2rCdv`H>%WE*Ic%uQu(S5{OOoR+Ez<*XDe zCFd6RM2^p9i@Q6MMPp>nTv8q^B2(sQb+~*Ift{VOUugT8ZGuNLeo`B zO-+%#>(i_skQW){-l<(Y%yU=yK^Wjpn$4O-1EM2$w8LV?GMzE9AggeqN6)1}Z|ObL zrfb-Na*0nVHyTH8nt_8ia5&U~x-YBi+(@S5F5E_G*^$lf#m3Bo2fLORNHJZrPK$yq(|e-96L;TMpX%u&K(V(&Z5?`lzEqAFZb#7s*9#0ec8tc{ zS#3Tw;Zi7Ai|nfCmIQ~UoZ)Hj=BQ9 zE9#ooY;-EDk}Lj+G9_CQ6xvYSe<$|`q#F8BAM{St^J!%-9zjVo?8NtFY`YHgYv#G2VObnD&l*mtgI zuG{RO+oVf_{%byOXsSZqT#a7lHQg#0FpOId`W9!jr9sp6=H?b}dNd8taw>`$Aqw)F zCX@1}yuHt+?b5kUbP7gi>7_z&4*aX>u1cfUF@@7wN^Ro`I}b;% zYzpKuIOcjvMls%VX+DK3m3yAde)JDQywOEPJLL4%_Z12k%*iR4Go@kLG9 z-fG}8&iefQ8xQiKi1JBqf5=1r<84`La*C%Pt;a(@_-#~b@52*UwmPEakqJk|AMGF0 z;@I$UaVLhn!r`*iWc@rfFO(-w{b9M|`peX&!i&#H7}qMC*fO(4n^4!*IjJi_vcU-IF=F^?9Wd?=;2 z(S6FDJaexvjuvyTZ;}rMa}W3WO!**5axLFRKDm!v>(|fwBiGkg%g6JP>+AY~e&qW4 z%4nlp{p(_Kef?Jb6+GPQ#q!C7u^VwVEOSj0EZ;_w8MIQaQMB!TBbz8iC&ldTUTjcr~|2(w( z$0QOp|89#s`k{>WdRmOqx;&po7mWNp8oeIV?DFA1zIogHn&U6t{%%@;cT%F)H~LPI zdp9L^A$QFavye=0qS?S^7dAQ%jeV{8k}|=GmfPaZ+2-%T43f8Mo0c3Z@5n?meQQe| z{p2UHt9<>0#%`V$e5R%3cWT~Uz6iu#-(C7OQ3kN-8s+un8fE#bjo)tk72}(X>o+Ip z^4&Db@}(N3o@th6$ygEBQ$93QqAs^iqkM|!jdG}I-b=;~U4DQ@$*VLuFLw zZ_z0A9UupT##1y(eamHN(fm@2`mx=*zBL-<^$s$$XzZs^)~6r3t?Sdz(N4^h?YGzW zwb%8Nvvqw-HA=ndGE`~2(&953rM`=0Y*qf4#(X(tb!3f`57w1#^y1`` zRHa!#)S*~&`IKHSPCj2*s`BFGYeHm~1YDXH#32?(S{!Au%3__xsTTLOxWC0iEv~e< z%Hl;9Z?Sln#Rn`tYVm1{FIv=bP22sB#SblRu=usbA1wZAQO7qeC*SlEMEP=;Ahx!s z-$JXecd^*h;`SEhiwJ_(<#V)yIMQN~#WIVP7V9kTVR5p>85ZYQTxfBL#X~I~VevSN zCtEzz;&~P?v3Qlm8!X;t@g9p0S$y2$a~5B#YZeYW${IeZ&-ZK;wKirwD`TnUoFPT_^a)0Wij1i#A3F^o)-IA9B6R| zi-i`)Sgf?To5j5>PP4e5#RV3ZSX^%LD2pdrJl*1Iic;lWfzt7^2d%HYb@8XEbE|yt5 zY^uvoviL-U%U`vaI@9GHE!OVq^2rv@neFl`EUugD@-Hp++TY~^EzVx(a`_bbV7qQ! z6M#g)rkezL`<4srSG7SmU_ytBpK4tM!fi>r@t`BfG_ILhT; zTkL(T%LiMWd%VjJvUux>E`P}4FLHsa`zPUK7k4?;#c>voJl*A|T72eAm%nK-^Bk9V zu{d$H%Ns17f4BNjJbcnyEy7v7b`6u zeZ9+1xA@$RE`Qr%n_FDo)#C2AxqODj3-56GbrwI73w`aM?=1Ga*X6@4F1X+2hg!Vz zL6<*j@%M*ap7e-|#gDo;-r}*3yZlUxFFfh;cPzGh#^v2D?)jX{XIZ@X1()Aoas5j! z|G{GaS6#lN#m3iNzQW?&Z@T<(i{4t7r&ug~*X1=9k6-8Vvn{^#fy>{snDw#Cds^K4 zQvJq#E?>N<`7IW|kZ<7B{AY^;WP+yo&K4KTcXDce zgvI-lT>iAh7O5`Ju()fw%O_Y|mFe>HEWXyp`)zF74*>qbxqy!{yIfjNi`Xtu2=Karq>RH_P|y>iQnA__W2>H2QKM z&+?5Lv*aGG#h;D0kT1?u-qK=7#oIJWd+xG$zwxIv%Jz72vt45=iz6+Lw|Jz*lPs>W_`1b)7F){~M`}I2Eaq99 zY_ZYe!4_9pe8l4G7E|QA6}6sr7RxN|X|ciL*%q(0c$>xb7Js$aLT(&reOVSuELK=N z%;Iep@3;7pMNhr}Fz6qPBQ1`%xYFVY7SFJFfyI|CeqynMe4U=w*WF@2i~CrdWpSCs zRTdwy_>9F@EpD*bd628Om&M&Jo@ntRi?3Qt80?l$x7gj{P>ZuIF0y!t#ZxRkYVkRX zaq>NCx?Mvp&at@M;;j}xwb*f}TfWNT3XO7{9AWW9i>FvT*Wv{hue5lr#oH|2W$|H) zk6C=);>#A-T3lywgT*f`{%G+Ri(&Z^H*H^n#dM2pEOxfo)nZ?Z{Vfi)xTD2HIrOx@ zQZ2T%*xq7}#U2*>TO43V+2UCiS6htNcFG(r-P$W5s8?um6;V3%&mGzg_(m_IGb* z{KvO)f&$a@PiW=ue5cQox`OAEr%YMUaDc1M5&1f-*mUv&{hvo$pQt^xeimTNIQo4IW+P zw=NfUskh~F`kFqrlb@FI^PiT>mu0qGZ|oPA=|0s*Kly1TKfB0}KFTi*d1pzZL<4yT z(*5ZACd&_Pkf+`ga_|)EsaLc5 zR^J;6jti|XNq(sBB6&_3dFnkb_381$gV)Xz5Zk_MW9pOJD$)96O4F>q*QLJOdQ)4| zYdR*y)_1Ser~Rt!OOqek_kcXtHmDE!IDV;o>v0eFTz~6p`ty`UmfP!skhiNa9xNwQ zj%MwV%xVSW_w%9Yqakpc`h!`mk>PGNqswzNYwS}LnFtE=AAB- zewKm}d7dLbTA%j2u9IU!o_hV{%?i0}jy`yrAtZLWSEPO4N0(|^Z{Fbif}EH~!O;96 z!}13V8z@x%o-OwGkRgL|a)u2Xra>P2BpzB)Uh2LF&{Z6gce+@=l3^2q%y-9nZ+TxV z%gf!cu`twi%(n?~l^a9tE-Jrh?8W2OY#LT@(bzSck|!5^+tTYf`TZFe&sei*P{AKR z{r-nvTJ&v}r_VyAy-PKApXqJC`E4nku9^Ovv}?`WEPwMWyL=ldY}s?w*t+Sf#+*F; z<>~sGUwYygjavGMa((8?hjR3}{*3wd9zWE5mv6gdtgJkuV)>Y5yIwNo)2W|KTeE3- z{+dn4SFPD}n)l(1i)Pf!Z7=I+*)`IA{PbmGP7P{rQM%M>&k5Q#XV=z2>*9O8w`uc= z#>!dcP3zeuSi&zI7R2UT6WZys7vp>FRsPef&h4OU@4idv z)L_kjSI@c^!@b5zJu6r27E{ldACHr5to+^^m5?*O?7dCBAJTe9Jm|LZ#`HCtUXY(l zbJlEHBR|JieK_MnSz||CW4B26Dbsf;z2qO)`s9m2A9vev?8Q@bAAUGh^A<7t&h<}E z`lm#!xGvt-n{;@lxojtJuvD>GeJ+pza+ohd7wUuMHq@6vtL9uIT zXHRaG*wwVNXE!)@bK2R{8xp&1+S&6P8oMdm{j=w{YV0;?XU}i7*p;-i=Qk{NW7^sC zTRnC|+S&6P9=n`&_WVY~Zk=}a{MLwFN;`XgYsN07ojt#iu?uNu&u^{Rt+G8Jdwy%j z&UCIhAbWo6#LnK<4aH)Q!c*DXzcGDsvA9f!1fcP<@92}dFLt+zhXlz0bi%rPku?aaM zHX$=&6LMs1LT1J$Y-~b~i%rP!u?aaLHX$d*CS+D@LQaZJ$jPw@ zIVCnBr^c=e*`v@lyJR#@%iiG>_pA$9I$cjrD^ExA>`bc zA>_Q6A>{m+A>@LXA!K&U5OQJ65OPt>5HcqwAs5FctYjfeQZK*h)u|iu?e{;HX%31CghgbgxngN zklSL{g`837lfC^LUrX1JGwVXuPw!=JFDE%k$lawr*+pfckbB~22)Q?A2)Qq22)RFI z2zel82zfAO2ze-G2zfYW2zexC2zfLnA&qJQ16aCu0-xRBS??j!noju?cxL zHX+Z&Cgl0pguD=&kQZYU@=|OBxVTt zG-e3-EM^G#JZ1>_B4!BrGG++*DkdRc$0p>P*o4fFO~|*g3HdHIA>YR)iA~6_u?hJtHX*;qCghLUg!~zskiTLR@^@@P{)tVgOer6yyJtIl+1uJ)JlomJ z^0K{HwzHSz4fdkh&R&)`+TF69y)3WTU9+9NEN^2klI`qed6V5G+u6(Vwsz-iXD`c} z?M~TF_cc|aV+z?btO*@b$ev=0&_0FiIkpqprI0WY4s_P)Z?trb`IL6tZW!q)mf>G*F;uWr3nW0!6C`6b%+A8X{0MRG?^8fuhv}iiQaktu9bBT%c%# zK+zfkMQaKajT9(aOQ2|NfueN;iq;h?T;4B}CTGD%~4f5sW zD=FGIUs^Kz48cN0n>ZheM%$rij2((LwL{TZI~0wxL(yh-DB9c(MO)aRXuM6)mI6gv z2^4KDP&7fHXd8i|Z3T)Z3KVT8P&7%PXnTR89R!Ld3l!}rP_&ak(ar)zQv`~35h&VK zplCONqNxH!y9*TUA=DL($`{tjfK=|wW^toXbVMSxXZEG7?dpp5$(MG{KKZdw(Z0@y zqW$bpw7(sS4zNSfbUPFsXosSM>`-*D9f}UIL(!o&MTZF#9WGFGgh0^@fubV?ie?HF z9VJk7v_R1@0!7CP6dfl}bi6>(2?9kY3KY!}C^|`?=wyMSQv`}m6(~AQpy+ggqBDfL zqG|cUtPDtH|Ljh?xOXV}W#N5RzMOoeYtgy+(skLVwHGQn&-qYvz8#7#utU*oI}}}L zhoXz@P&CI5MHkzl=n^{=U20QwnLyFy0!3E{6kRD$bd^BST!Esi1&Xc_D7sdlXr4gP zbpl1#3l!ZTP;{d}(MQ8G9Z-;(hKTy zLeZT`(Ovm+@|6_bmoNR?H5A?Nd?U4f$agu0@8@`WzhSB6y5cM28n4MhXed$jlS<>V_V`Z!-2 zvREkk#Q9M4sU3LO6Ih(J+S zfue2#MT-g)EhbR3xIj^Nfubb@ik1{8T1ud3X@R010!7OR6fG-Iw46{^RBBbYJOfgB zA$>rxb*uWFe$RzBY^}=4S5mZMtI}gjhN9lihoY72P}Ii`MSbm1)Xxq@{q0aRzz#(N z?NGF`9f}6o6s;mqG+3Z$h(OU$fudCfidGXS8YWP*xqD>kLR`_w+%>6+%%{`ry$`*k`4nY(}cRBOF9q3BRM6dh)VqQmV_bc9XO41uB}1&U@06dff{bhJRxF#<)$3KShD zP;|UN(Fp=YCkhnJ5-2)Jpy*_QqEiHlP8BFRO`zy>fub`6ip~@$I!mDFY@x1b-&TeF zGa!`{(mS#JLeYYBEjp)FIr&P8E@)LcXZcVx+xbv*p&g1YvP01vI}}}PhoVdDP;{vs ziY~K5(dBk1y27UDN`a!Q1d8Sg6kRP)bd5mKwE{)+1d6T`D7s#t=mvqJ8wHAP5-7S^ zpy(EXqFV)uZWAcFU7+X=fucJFitZ99x?7;=9-*%2yjF#KGa!}o@)?}-L(%2wT6Ax# za`KfFJ=m)BUawH}kn^GFVLKE(Vuzwf?NIcX9f}^eL(vmY6e#*jpy+RbqJIR6{uL-%AW-z5KvAv`x9t?=1&Ue;6cq%DiULI? zp|0qYR)zI4AeCLxwdm7O^k*8a3+3c1DXJ7oyYvY~ZJZB9O?D`1Ylos{I}}yzP*k%+ zQHvdl+S#F~y&Z}=*c5dXDC#6o)LEdYi$KvL0!3W~in<9DEhL`AUlV6iPSr3q^gM4@Ld#P}JWJMFZ?mG|&!3E8C%HkR6Ivu|v^dI}{DEDHkzMG(wt1nmp`3grMdJ#kUk8Mu&72QK zo7`-*59f}UKL($=O zC_2IpMKkPBbfg`MX4(`TB~WyT$ur>%t(qZ3`NJM@j#)Rd?iJX6iQEI-WiryC}`aq!QLxG}?1d2Wu zDEdUGD|)C2KOBmVOxL1M3+3c1Df+TdYC9|xedT;8`q~af-`JsOz8#9b zwL{T&b}0JZ4n;rMq3B0D6#ZmV^s_+GF9Jos3Kab&Q1rV%(H{aue+m@+B~bLYK+!(} zMgIyEEf6UBPoOCK`tJH?+bPNm6txm4DhL!61&T@nMXd#j$^u0VLS514g+l)fNM)7u zY5Xrj(NXEubz`xdd?iI~i>0x{Ls7Hyp{QzyqM99wTI^8N&JIQG?NHRg4n-a9P}Io| zMV)Pmx(F04B2d&-ps1Tb(V_xHiwP7hE>P56plAt!q9p~2mJ%phTA-+hK+!S+Mav2l zEhkX4yg*S;fuddlMJosttte2`Tc|5)Q!Gr+fK)C>*P^Ck{Z9X$^y+%0VmbLriuxBz z=dBTn1~?yz2HK%$WjhoNvP01-b|@NbhoT{NC>m;qqE+osw3H6s;{#w2na0x&lS(2^6g_P_%(S(S`y=qXddJ5-8eOplB0;qR|3H zV+4ve73zxm77O=hKq|AcS?m{zK1n}inbRh+CiXbvOv*}0!2Fs6zwcfG)16j7lEQ(1&VeP zD4Hrzw7Wpj9s)&s3KZ=nP&7@TXm5d{eFTd36)4(IplE-Aq637wqRonh;#!%aG3hfP zn}?#C(zR%Mv7CG*MTZni%d8WM4s|{h9cG83!|hOXgdK`z*rDi1I~2{dL(x%oC_35> zMaS3_9V<|DoIug>0!1eX6rCtgG)ti9B!Qxn1&U4)C^}W3=rn<%(*=so5GXoRpy(`t zqO%2x&Jid&SD@%Tfui#TiY^c+nl0279aJoAkO8UekzN-a9EwI}-|$+zuvkvMlA=qB zrQOyGMVC4siY~K5(dBk1y21`cSK6WIDmxU-wL{U>b||{W4n^166wMPTx=x_zdV!)F z1d47HD7s0Y=w^YUTLg-36)3t*py+miqB{hN?i47xOQ7g(fuef^itZICx=*0!eu1I~ z1d1LMD0)b!E1FX*oSFft^h(#Fi$hWN6Vb98wqiN?N{SvYmTuZ06g}a5D0lD=GS>So(cbD4OqlDEih8Mc>(>=zBX9{a}ZpAMH@|lO2kF zwnNb`b}0JQrsy|;qTdCI{tzhoQ=sTCfug?!ivAHO`d6T6fk4rJ0!6t}+_qDc7bt2a zP*e~oDhd>p1d3V<6qN;v8U%_O1&S&HMQwz-qOXdDMK{V6eVg8+eI1H6O7GE{O6BA$ zDXNu9!!`*;EzXCcc6KOgZ-=4|b|~s-hoVk)DC%s7qAqqQTEq@TU2TfG2^1|VP_&pp z(c%I{-35x45GYzwplB(9qNN3jdI%IPBT%%gK+$pnMav5m^%N-TB~Y}2K+%c=s4HqN6}HcSRJKlEcU>*T_vxn#Q@>I<`AUjbE|q4E2}OgP4@Ilkp=huj ziiX&sXs8{ER<%RXYIZ0ZW{0BH?NBt_rf7sf(Ha6pYYG&N6ewCtplEG@qICp{))gpP zPoQXhfuaoriZ&D|8YNJ)kwDSL0!5n$6pa=r8Y57&sX)499Ctpd?R;AKYV?)u_&WEB2b|~7$4n^DAp=hEVing;u(Ih(*ZEuI7 z9qdpv*`{bmfufxRigp$#nj%oNi$Kw?0!6zC6ipQ<+FhV%4}qdR1&a0(D4Hfvw6{Rf zJ_1Gi3KZ=pP_(~5(E$QQ(*=qS6ev1Ks4E&@Dtwm#sVqn@g|-YuSEXyw!KHHYl@uLb zDpfZRMMpRvie}iM=tw&h&9p<&QFbUg+73m>*rDiHI}{yfhoa+cicSzHI#Hl#mO#-- z0!1ea6rCbabgDqnX#z#33lyCpP;{n1(OCjTXA2aaBT#g%K+$;uMdu3?T_8|2TcGGd zfuf59islG)MTeFO12Z6%N$Ixiuu#-Dy)L@AR8GEb||{W4n^16p=h2RimtOm(e*Y(HwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS z6x}IMbeBNU-2z4T2o&8bP;{R_(ftBN4+s=JC{Xl}K+(ejMUMy+Ju1`{U0Ny}lmV$c zlkW5{3q>zxe^z{~R8GE{p zP}JEDMP2Mrw1^#wy4s`Nr9rJ1d5gxDC!|lw2VN} zvI0fR2^1|aP}EbPsFy&|3Iatd3KaDgC|XINsEm}nrMfj?d(uA$qq%^+o5O&I}}Z}L(z_QDB8&mMLXLRO%W*CMWAR` zfuh|6ilzz_?JiKXhd|Mu0!4cX6ipK-+FPJ#AAzEM1&a0)DB543=m3GD=>kOu3KShA zP;{_B(IEmwhYEE?TemK}nE|Q%lCDJ)LeVGb1KEeQE+=0}(UGl7f9@EHW;!2=jV_Vx~g?)_>@pI*ZEL%wH=DCu|v_db|{)>hobB3P;|W= zif*t&(T#Q}y2+;KW`Uwx1d47ID7sCc=yrjkI|PdE6ezk&py+OaqI(32?iDDyPoU_2 zfuaWliXIdwdPtz?VS%DY1d1LND0)nw=y8FfCxp79D_R#OXFw_w(+lb=L(yC5TJ&V= za`KfFJ=?l;^sb@kIp;&s^L8kD!45?)+M(zrI~2WahoV>PQ1q%Die9rr(d#xvZwM5< zDNyv5K+)R*Mehg{y(>`ko|5GZOCD5?k)wGk+45-4gbP}D3?R23+y2^6&mbw%H| zF8q)Isq{_Pq8~!h--T?nE0>e6q^MK5)UszN>g;?d>SBkYMeI=2)ec47>`=6*9f}sS zL($@PDC%y9q9tsKmJ}#jN}ym*pqP6T$w6;yrIs!%O z3KXp;P_({4(FOuV8wwPS5-8e8plD-(qD=&fMhg^;5h&VJplGZ>(Kvyk%>;@z7bx07 zplG~6(Ut;5TL~0xEz}haDHjgOfK0!0rC6g?tP^r%45V**8w z3lu#eQ1qlg(Nh9NPYZQLbIXN|Ga!|2>7Cfsq3Ee}EqbP0PQH?&7s{nQ4+=#uIviry0_dS9UE1A(Fs z1&TfrDEe5S=o5jWPX&rT6Dayzpy&&MqAvxCz7i<RFp=dEX6fJItqV9GmTEY%ROWL7mDLWJ`ZBx`kplBI^ zqGbh&mJ=viUZAL_Kv6G&q7?*+Rum}eEl{+QKv5roqP_w}{RE2o3lt3yC>khGw6Z|a zAc3M)1d0X=6b%vTiaIwGmN-09G$(xqq)S8nPXE~S9&KntIr&P8R&OY+F(VWWcRm!2 zutU)rb|_lY4n-sFP_&jEiq^J6(K>c0TGtLm>)8~oFHp3BK+%Q*MWY0YHWDb>SfFSV zfuhj@MPmetHWeruD^N5}plCCJqRj=0wh$;9FHp3lK+#qLMOzCLO%N#BMxbb0p{{7P zhQdx6kjixl&ahDQR=O5VY$zvRNzo1srDJD?qRGyOq8;r}w38i*cD6&&6gw2{Vuzw# z?NGFv9g3#fp=fuTqCEtP_7o`EOQ2|)K+)a;Mf(U8?JH2UpFq+60!0T16ipW>I#8hK zAc3NT1&R(4C^}T2=rDnz!v%_t5Ga}gtAa@|6@_*HCJITqwHU`A~F& z9g1$WL(xrkD7x7WMYq_Y=vF%v-DZcP+wD+vhfUF)0!4QT6x}UQbdNyMy#ht|2^8Hg zQ1pO6(Srg-4+#`KEKu}_K+&TDMUM#-JuXo6gh0`g0!2>=6g@3a^o&5!vjRoW33Wx+ zHWUVDKq^~gvp6pljZN>-o^L28UrEu+4W%tl2t}_rABtYJL(yw?D0XZ{bz@wTw~m~hoZbq zQ7eI>fNP}EkSs9B(>Do|7tC~6TXY9~g(sB2@P za!RJ?z1A6=ZjJRj{g#C{Y>nmQD=Au|v9!Wzp=eF#L(xb(6s={4qP6W%w2mE$*0n>? zdUhyU-ws6^*r8}co1#$yMH>keZ7fi$tw7O4fuijMiY5tlMZ+5lqcb3t^V8*LL@3%};SF13 zIr&P8c4{n5J0leB?0hJiVuzw#>`=6;9g23dL(x<_6zy(@qCM%Qt{Zva`KfFo!D5q<6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9DAW~Q-&k1c+)UB0>7~#Op{R2y z8!t7Mldq)cwZ_uO^Fz_=&WEBm>`?Tk9g5zvL($uID0;^ZMeo|7=si0Wy>Ex24{VA) z6e#*gpy*?PqE7^hJ{2hXOrYpMGO~ z{n1#sJ_AxYBfT#AGZf8C*P?Efa`KfFb+43OxF{4Y;e04s(hfyS*`a7@I~4V>L(wvJ zC|cGIMa$WtXn8vn^|UGKB~Y}2K+%c=ps1ffQGbD=0Rlw>1&US{ zC>kVCw2DB{V1c3`0!2dwidGdUT1}v6m_X6$0!71xx}wD@gkeFw3$HB<^n}q2o#MMDB4n>Xe)uDtp$oE2o!B2P_(T;(L{lw z?F5P@2^4KFP_%bV+D$i6DT@fs4LpJ zQaB<5QfWz-pDCfJDZNKKp;Au1lA@C74zo)n6DraS!` zD&^!WDY~Un`r@ikbgT2B=r%hP-EN1XJM2(&ryYv!vP03`b||{X4n_Ccq3AxFqWcAk z9uO#cP@w1`fue^6iXIUtdQ_n3F@d7T1&W>!D0)($=qZ7srv-|h5h!|Apy)Y)qUQyQ zUJxjHQK0B0fuffMie3@wif*bDn&xJT3av6YH;1Bpx)!}!DJNe^(VLZ0?`uNQTh51~ zx9w2$jvb2LwL{T+b|`w^4n-f>q3A<96n$ieqK|EgJ`pJTRG{cHfuhd^ioOsi`ck0i zD}kb~1&Y2AD4H)&^sPYAcLGJ<3l#kzQ1qif(N6+JKMNH7B2e_JK+$gkMZXIa{UOv9 zyK*`cUl zhoYh#ib{4UYHf$2vQ1HgKvAPWQAMDrjX+V8Kv7$PqGo}jsz6aqpr}QlsGUGjdx4@3 z0!1AKiaH4tbrvY-tc%wDX~;haHNRu|v_ab|_lT4n@n`p{S=Fih9|hXazeIt!Pu!TcBtq zfucSFMSTT|`Uw>E7bqGaP&81WXk~$-K>|gq2owz#C>kPAG*qByRe_?_1d4_U6s;~$ zG+dx)gh0_60!3>Ibwx|GDZHNnsVtd3>bPW^`knsI=~^_hO*#2Wiq>sY`tQb2w4U>! zXni{rZD5C@4ed}g$__;v*`a7-I}~kVhoaGTC>mo^w5dSRSb?H(0!5n%6m2e0w1q&? zc!8oV1&X#3DB4<}Xo5h|HUdT43KUHgDB4b-Xp%tD_5wva2oy~gDB4k=XeWW9orSuh zwc8YW+>|MrkUj&lPAEDv`?KPdHs$0iDVo}*wDv8bXm{sB(H?dv+S3k2d)c9AnjMPv zwnNcAb|~7{4n_Ofp=f`bq5}kqrVA7uC{T2eK+(YhMTZC!9V$?Cm_X6t0!2p%6wMGQ zI#Qr$ra;kA0!2p)6dfZ_bgV$paRNoh3lyCoP;{a|(JY~^XxBD{T{9q+ThgcTcMC-i zrVG7_eD z(H+i*qC4$SbeA29?zThGJ$5L%*A7MZ*`eruI}|-&hoT2^tnLM7Xn3J3KV@MQ1rDx(KiA`^972&6)5^npy+#n zq8|i`eiSJBNucOwfudgoihdO+`c0tdcY&fm1d9F?DEdpF=x?E}=&d$|)iNNJo=q8? zw?ol|iPS%B%E?z!lxr$&b8jfhH^rTNC~9SgqJkZYigqX}*`cVl9g50!C~B}nQKKD- zDmF!J1d5sjirNYkH479~1&V3{MJ)nF?F5S23lwz_DC#Is)JdSIvp`W7fucnOinoW5fAzfjaa`?KPbP37b(DO#qfblLr( zXj$h&(QUaA4rLj&^Ir&P8HfSn+^mpjqD}2kG}aD9<7|pH6DZnTplAz$qVWPnTM86yB~Y}rK+yz&qHP3WnWE$Xq2^7s0D7spp=o*2dYXyqt2^3u?P;|XO(G3DcHwqNpBv5p-K+!D% zMYjrdMW;6v&d-2UZcBIiXN01`3vbw(%E?z!bXQa9o+m=l-Oh)id+bnjuN{i+vqRDS zb|`wl4n+^zq39ty6g_N*qDO3s9u+8hOrYp-fubh_ik=iGdP<<^X@R0=1d5&&D0)ty z=y`#n7X*r46exO0py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP}G)x}&M^VFsjfOuGEs z8HyIq{;c?RQ#tucir#N3<)02kA2=V1KD0y8M|LRs*bYUX*rDiCI~09phoaBzQ1pcz zioUcd`bwbaYk{I~1d8Sh6n!gD^qoM__X0&f2o(J&Q1p{P(a!=!zX%llDp2&BK+*34 zMSlns{V7oNmq5|q0!9A_6#Xkuv_PmUdbg>tYzCxKNMCpTUMM;}U5ox}Dkon_QK4;V z-Dg8lvF-nVr(d!|QENLCmF-Z}V27ecI}}yyP}If_MNM`nYHL%}EKpPxD5?n*wFnfo z6DVpgP}D)7sG~qpCxN2Q0!3W}iWU(l>MBswO`vE|fuh9(iWV0r>Ml^Ugh0`f0!2#+ z6fG^(73JF&re;7Y4e4tgTeYpG@F9)A_g-^|C|J3U(-3 z(GEqu?NGFm9g6zcp{TDNiu&21sJ~6o0D+=`0!1qe6b%w6T1B8}ut3oefuf-TMXL%F zttL=3OrU6Wfui98MI!`?)(|LKQ=n+1K+#$PMQaNbts_vhu0YXxLS50aZ3{PNKq@^G zoaI8%r1b7>{kG-gD=FHjZRwTlcgZ%b**90**!fVji5-eY+o5QT9f~%!L(y0}6pgb( z(Pnli+T0FBTi6th7bx0NplB#nDTqEphf=!~}I$Xq2^7s0 zD7spp=o*2dYXyqt2^3u?P;|XO(G3DcHwqNpBv5p-K+!D%MYjqR-6l|UyFk$$LS4~W zZ3{U7@b%?zV-eGa!|vN*SDcLeV-+ z*?6yQIr&P8K5AR~=B-flvGbwm6FU@rYKNlF>`?T%9g4oNL(!LZDEi6{MPJ*Y=o_1& z`2t1X3KV@OQ1rb((GLPeKMEB6BvACTK+!J(MZXFZ{U%WKyFk$&0!4oc6#XSo^tV9K zKLSPn3KT66DEd#JDAyb}<`m_Hx}p!-7HV&2iXKSUq7Nxb@6lQ{my@rgsC9Fx-@Box z?0hI{utQO!9f~S;C~9Meq9!{OwY5W0vmJ`6b||XZ6txHxwG$|6FHqD$ps1rjQ73_- z&H_bU1d0|BDC#Ou)J>phQGuex1d0|HDC#ayw1hy>k^)6b2^1|YP}D=9Xc>W`Wrez; zVsl~h3`nJv;FOx{cly~owCskhxtx3@MJqIy4tPHlt>}Cx>TQRjmF!T|#|}k(?NHRu z4n_U#P&B{}MFZ_nw6aanAc3M)1d0X=6b%t58Y)nrB@DB9ExMPuzyG|mo1o7tggb2}7mVTYpeb|~7?4n-w?ol^b|^Z?4n+ssq394h6dh`ZqQmS^bhu5?5duXs1d5InD4Hoybd*5R(E>%s z2oxPFP;{I?(eVOBCkPasC{Q#@py(ulqLT%RP7x?NRiNlJfuhp|ip~%yI#ZzNETOJw zpXS2y8Ia0n=`$evx)!BZ*Jn4Eldq)c{N~d7pM|0eoDW5_?ND@~9f~fpL(v>N6kTkG zqD$;hbg3PRF0(_??dS3w1^3HW&8DfK(n&H}~g-qONJ& z(_BuzlA;HiOQ(DhiXL=66g^~zqKEBJ^oSjb9<@W!V|FNd+zv%g*rDi2I}|--Q}nbz z(K7-?&k7VhCs6dfK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1Q1rGy z(K`Y~?+O&XCs6dhK+y+6UD18bg&JeJ@b-gFw-b0!2Rw6#Xnv^ou~z zuL4EC2^9S=KpLv`JN=K-4-n~9 zEhk?|(Mr|Qr0+seALm0+Upo}_vqMpTI}{DDL(xDx6s>HBqCs{jTEz}UgKdh22owz! zC|XsZXf=VNVFE>~3lt3(C>kM9w1z;@ngT^51&Y=ZC|X;fXdQu~bp?vn6DV3=plAbu zq74O#MhO&cBv7=mP*=2KwQx)Zq|zxV>K%&KO=FX4Ir&P8##T#L{Sb=AIUkBPvqRD5 zb|~7y4n^bbP_(5Ting*t(bje-nqY^bZET9R6)2i0P_&&u(IkPQ?FEW<5Ga}~P_&~! z(M|$II|~#|5h&V4plDZtqTK|FrV148E>N_GK+&E8MSBSpO%o{ETcBtkp{{65weV~P zq%tji?0VBsG%j6>_N|taucT;twe;;zq3A&8L(xHYC_2~(9i2_Bl1d2`)C^}i7=oEpX zQw54n6DT@epy&*NqB8}G&Jrj(TcGG1fueJTx}yE7g?2w@irz^dXgnYk{ZY!sdDU|A zl@wiAEe-fJ6kX(eD4Ju3qKoZNbcr2`F116^Wp*gK+zv%o*rDi3I}}}IQ#4ng=xTwY zYXpj}6)2h~P;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-6~LYn?TX+0!4QS6x}IMbeBNU z-2z4T2o&8bP;{SAS9C$OFg^oP8J4a^vqRAn=|hnBSIfy)QuJ`Obl~ry=n>~b(W7=K zddv<*kK3W>2|E-$X@{bx>`?Ty9g3c@L(#J~Mb8NoJugu7f7XQY|N6NzoV8(gS~nqA#5fMPJ#W=xaL^ePf5B`F1G!)(%DA z*`errI~4t3hoT>CihdF(`dOgp7lEQ*1&V$XDEeKX=nsLSKLv{Z5-9pxpy(fgqJIU7 z76=smCs35D#cex9d4Zx<0!0OZqM|@iNua2;Kv7w!EBdTj_%s7jIXk@*`#cogo32F- zwQ};66gAaKrGG+ETjxVjvmJ`6b||XZp{T_UMeXcR)ZPw79qdrl(GEqOY>GMy6m=0O zT123zt3XjVfucnPiWU6s>Agw3H6s;{#w2na0x&lS(2^6g_P_%(S(S`y=qXddJ5-8eOplB0;qR|3HV}!b*KDEML z8Ia1l=~~n`6n&eN_GK+&E8MSBSpO%o{ETcBtkfuel{iuMyI+Fz(E8dodao&l*WNT0^vEEIK0clrm^ z%E?z!ba1WoMypVCi1VT7P&*VIW{0A~?ND@t9g1eyq3B3E6wS0l(NT6NI@+e_7=fZ= z1&WRnC^}xC=mdeH69tN92^5_qP;|0D(J2B&rwSCECQx*`K+zcjMP~{Woh49owm{K2 z0!8Nv6rCqfbiP2*1wviXfwjUv8Ia0#=>v@ig`$tswP<#&oO~rk7uQOQl|s=a&WEB) z?ND@?9f~fuL(vs>D7w-PMOWFOXs#WKuC_zbH8w@p3KY!~D7sFd=z4*o8w84O6ezk$ zpy+0SqFV%tZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^96zYmD zsukAEfK--Dm!CPIsCBw9Jya_vUrEtpwbBmdQ1rO-q38)a6g_E&qNnUo^t2s{p0PvG zvvw$Y&JIP-+o9+Mo1zy5ie3^ZdRd_86@j8x1&Ur1D0*F>=na9QHwB8`5-56Gpy(Ze zqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>n1&Tfs>WUtz6^_e*R1QejqDMo~y!7h& z^IAFiN{YU&m9B0KMc+6dissv)=vzA!eP@TF@9j|ZgB^-~v_sKPb}0JU4n@D%6#Xht z^qWA@?*c`C2o(J(Q1q8T(cc0^{|FTQD^RpRpy)q=qFhVdwo{ZBC~758R1hdC3KW$D zidqX4l?93#1d193iYh`~(U-Nt^BIuJ^lTQt3Pp1l-mtZlldq(x+EV(yO(?24ABtM+ zP}I&2MeXfS)WHr#9qmxm$qq%G?NHRk4n>RD6m=CS>LyUMs6f$T0!51p6m=IUT0)>` zNr9rJ1d5gxDC!|lw2VN}vI0fR2^1|aP}EbPsFy&|3Iatd3KaDgC|XINsE<%r)V8J2 zp(#_;KYa$Ixut%me@VI)^=&C9UrEuxmeR`EkI7nikG8V&p=gjDidL~h(O^3i4Y5Pf zP&*W@YKNlL>`*k!4n?cm6b%kP(2o#+uP;{0+(b)n;=Li&?D^PTvK+*XEMHdJZ%@!!SP@w1{ zp|0qVmcr*5kjg>n@^fe?dLxZFE#>4ZDY~qsRPGpxE_Xf@U15i!EA3Epl^u%a+M(!b zI}}}GhoWokP&CgDMc3IBT`y2{gFw-Z0!23o6x}RPbc;aItpY{22^8HfP;`et(VYTC zcL@~TEl_liK+(MdMfV95-7iq|fI!iM0!0rA6g@0Z^oUSbbV*BL#SBPg<7^f$4Mi)Z zYtf@E<>V_Vda|XoQRh(fl=GqJX*(1>V~3(=?NIcb9g3c}L(vO%D0`?Tx9g2RjL(#8xDEiF~MZen={UK2Fr$EtP0!4od6#XMm z^shkC0)e9c1d4L);U zR;VlbrloLa2BflA`sShep=fe?kJj9-oO~rk?b?;z>K2OHJ0FTV*rBMS9f~^Hp{TPR zin`dLXc0RUb+toLH#-z9YE!hBK+)m?McoC8mJldfQlMxlfuf}aih2kXEhA90tU%Fn z0!7OU6!jD+>LpOLfLXCpSD>h$Kv938uBg_oupk3c`6j&+YiU=% z(?2;~iw3kSCtpd?D(y<$7Y{{)oexDr>`*k+4n?clp=dQb6b-XO(du?68g7T85q2nA z!=`9WfufNDMQaHZtu0WrjzH160!8Zy6s<2%w1Gg;h5|*S1d28iDB4({XcK{=(E>$d z1d28lC>kqJG)|ysGl8Pb1&X#1>WWrwS6C|pQW==w3<^bCrfbpocID(NDVor(wBr(? zXdCB4(YAIdnrMfj?d(uA$qq%^+o5O&I}}Z}L(z_QDB8)UXlH?(L(vI#C_2%mXqG_HNdiSD3lyCqP;{z5(P;ujrwbIFAy9OtK+#zO zMP~~Xog+|mu0YXw0!8Nw6kQ-tG+UtPLV==-1d8Se6kRM(bcs+`ba=bMiy4s0_t`8S z5sLmuowT=lB#Q?|M4Qwd!4o9wG<8>(#^voBt&_Q^g8SF4U` zo6B{mo>k4|x>Vn3$>kQUF4-ZMTcWyir(CW_^|~&(-160*yXJB$R);K>%k`}u-aVHa zSbc2CTyAi+O^;k|wd$BJ9yJxpCEB z2jp_&tE&#mA%<5+2bGdV? z7i^Ww&8~hlA(y+jy4=KE?(*vHlXAJa)mwJR<>poY+%cECu{wN8E_ZA7=v{NUJFCx3 z&E@W`w(Ob9Jy_jhS}yl!^}>B}xhJci?3c?uTkSbLmwU0g=RvvLtJT{M$>rXx{(V?3 z_ilBK8M)kt)njMoa-UY8J35#9vfBQ*TyB1K%M)_BAF6X^<#NANKRY>>`=h$TX}R1# zwP|N$|Nir}JI>190QuU#=VWhzd~M|U*_$9=JAQWdHptgrxF~xg|xZ5Jwb%-7Oa zJw2MQr7v4~GG9wyckpb!mOgR(V!oC>^Y?1LmOgd!X1Z4=d zY^3MWa|-|Wf%7Jv2o|9kYmvb6BgGfWE~ zy=nP{{{~uRPr746v?Zb)khS#T)AXzdMoa%vvbpf=y7iWx^-5V<__*uEpG}UxpB{H~ zwCT~(plCuuJfLkYqOrYzf&^Fd@`AYti8;=lhjqs?sD}i)&{tnZlE*IE^}rR&TOMI=a)IN z184Tunb(y$vp;9L|AM1?n~w%(`mv`L8T;y^Esu6@cB0PTQ|8K(IkQ-29w~F?JkGpW zXQtWB*yn}QUVWv`4ApqkPPxB+V=twKyNB+t|3gAzjeG3vyTAUoHXgSV?yrB?#>sXO z_t*cS?JR zQ~Oo6ryQMQpZI>;kSmFm!>Osk1;RF?X(2C(%crKMrN&Y_*r$I|^?zI{*)CP)R#P2;DrZ;nOYcYdG`n~1Emw%2@I#@BdQbF5DrJPb*5pn! ztywW#DY09P>wDC6Z?STlGIuYb`eQxpV^XDTt8F)2_0lC_``BewcGsx3a!ELpP-9Jx z8um!p86kIuec{Xqb*&U^tJ;?*yPeEi+_9Qn z$Pcxf8>)SaJ6R(>+q>yb)-FA_k)0f0I^D^f_>5oJot#v9?hHG*H$Gdtn{p@Ljn6i2 zx|1mmP$+(`JLx{z>~0j>x$dOxb*)59- z^I8^8D9X#9FuSmzI6tpAe^Sf5!uhj{3tY&{pERd1zo^W4?(%l&jxA>wPMbNcc-q|j zP|K+WGxJ;K&d8tFGGj(TUha&RMN@MN^II0?&&n^#EozzHYC=)*oJrFPS{4@+%*dOX zJ8f1`%PDzz6LJe@w#>?$(0W3v%vM&B~iGXHtI4nYnpWr_K8R{caS^FDm6x_rghYrp+qIE-1`zQSz~vS6mqX zkOUu*p@jw0?PFfla>VT1!gG4hnKfagy)RRS&X`j)VR-j;gWCR|c$ntq7U#Q`%@xzJUl(1jPtDRBbuY5`izfz`OxvuXg zw)86}R;%q!Bv$h)oopxS`;`*yrpg>E$9K!k_8nums-Nl(<^6PburuN_-7ep1s-NyI z81D`L^Tq7uE4OIi-gf=ODt@K-iIO*&p192S>n3Kp8~J~DQ)BE3)lP2eEy$?f&`)n< z@7HXjKUcX-a9#{4&#ZPSbAH1{4*?yzb{p7?tWAvdb z@7_*%zmYrGhblhP{dzVN5}W%~+%fn7CM4Pyut-9>U(HL)@RPmd^h9rN=P`aYyH>J2 zX8%0u?*I3Q?lV8~$H=tA4mqMnX&b zIybymp9#G)`-a>xt3zhr2@`{p?b?)_Y@1zjvRwyVvP}nCcdne-M(6d?iC)*N>Td@_K_{Q<&rnjhPTnP^n+m^0$tGVa`0ia zTM15-xeM*Ns(tX{XW9o=*K1pHV|IUdqpfuL)}{9&yW|>K+3rnEa9`dg&zY5%+14Jv zGOP7JR-53y*t_U%JASbd`7gq}t>EkB@QYKUNlRT<>eiTkI9T z#p&)-FMd|0Zq_~%bnkkU+)ww(AHPudlB;L+1XgRES0XKbhvH8eB{!8-iWz*^%PQ4v z@0s2-;^Ma4P1*BI@D7wx%`&S&%jC>by;;3^xJuFT2--UlT#pm(p^87pl|J0|w5Pk0 zW%q@XS*0J5G7oxtU7ZIe@Z@f=L+OXhKA6GVXvG^V1(8)MBC8AudxV0kls@=84p}|) zzVj$_EV;k-@zvceebVD0YFm1Lf`>o;UY9=NS!EvbG7oh-yCeT6ztz!qN@ZR^m&)e} zISY^Ojk~*P$C8IZ2^98JsIyv^JV5qg=HjKS5CfPJBpvM0DJc0=D1F3BzHS*r-JD&A z8}0x=d$aNTXdh>tSNg?}VsF#Vb5D~a?K_0vfwiw=!3lfR<0l-Y_*cW=i=chA)a}{h ztW%};1WERh(s?Cf?12t$xKyA$TiK=JHy%IB1nFA#MM|ei-XYT+T;HDO-ScK)@X^T% z4*CjRYA&l3U5WEjYxXL@Zog=1L1A&p*IOgay$GK6N*?!;R|fXU7{7>nY#ac-^k$Wj zQ2NMcl|J-YrH?%iOqSi(_>J%p=L4Q)pCs`!+!KaA3R$HOqrGjSz32%pXiowlTr%RrF!1Cv{nAy6uh2p7mW=^!@y|kGO1|xDU)ZXx0sUNVo0m>7WQpvmpr=zEhf**FDlBN zlHX!R{;Vm*Q@dnZ3SJnsa1XjI_a(h}TEVOqMfUx*9gD0@$}P?<*};dxUR(qxO2xV_ z5PG+r#{cwXEl^qJOK%B1qZ_}?(pQ@fV_ZVXEtkI3%nE$Fv$O0eUw5nY5ekr(d|i#3 zo-pB`U-WscTl!KLHtsdqklrIozL;n6%C_{yY3Xay(wC(6;ub!^CxN?ryadkT*9zAT*G*^;cK;Ui?>}WzB=qCoWzYBAkB-Xx@${2PlIMPMROXLoKQ*dU zX1kwZR<(Ui{3k~4jMATJy5)u9|7___#{YOB`=^C6f4q?WUO<^YUda6nz4VV4vfmXb z^T!L7FSFe3SNzwuAIq2dkLwy0hZ;@#Pv3sn=goilE}_i#Gxi-!ne|^@YnM6i-`@wFYWFL}K0NJo zJl!4b7cT~CyZ1B29!&TCxXanUyTy+exuadqe%Bzr-9MbV%h|u($M@Sh?srGKoc*hM zyt{t_b(gb$NssS{QFFKJ{u^rUa`unH@ooPI7Qb9i?SVRubVs|~EN%BslcAn93k9{h;eL%;b?HzDC zY`<6Fj@9jbamR)_x_|z1yO)k*?R{{2ijEuXQ`hbLb^O9U0B--J3HBK}UO6n->vY^ZBG{kkc+#j~H`Os`bg*aYc*j}6en`i|X9xRN9a~KZ zc2^ze`Qdqc0sUT*D-Nnuq*30aB;B5=y=uAVBezS z`^$snC#?+jxjNo+d9WYT@yM0I{!_H`((%4c!G1!=qjv`TZyh__6YO3( zUUXluFVk`7=3u|2W6IWGSJ!dqL%|-W<8_Y&`!*dvd@R^s>)7DQV7Jt9>eIoVqvPgh zgZ-3_$F>DK{Csfiv?Dn7(Q(nPU|*r*3oizHkB+fdf?ZR`;jaaIf{r)55$sJme!M%_ z-|EO*&(m?sd%=E2$K&?9bk4uGKR9;&FgW(pammNQUZvwp2ZQ~Nj^z#o zyOxe4KM!`Uj%&XR_MJK&{5sg*>Dc6Ouv_ame+0XZj-&nxcAkzm*{ec#`MY)eG$GhO=-ABuWz?PD zR>xV~>$4hj)M#qghZr1TB9beM%9UVV)M|-=!=oqtK zp>sQ3$2K~4(Q%}X=jgal$E$Q)r{jYGzYbHY^-B*9b4(xPRFh~X6ram$Dulo(Q%xP-9q+x zXYX%M9S7<-RL8M8+L!(K<)-U6OUL;-UZ|se`HNrfaviVNah;BL=y;EgkLdV>jyrXH zNk@D7jNhI;O~#L(>iC6@Kk8^tJMr`F=^}n~-`}|RtGtetb+k{vc(+fp__2kKSvq#s zv73$qbR44NSvtDk=yJC|O~;u!&eQP%9WT-GG99nh@p>I^)$tA;x9a$aj@xwHspFeE zy8jh*_x3;5@lzeY)A2_g|IpF>D8XGmRmbu=Cc2MXQt-XCJKz0r$B2&Z`zN>U+kj9) zdHcLj4`me1pIMwc(T>H1!Eq|5?B|rlp$zwf!BED;qM}fS{U|fT#f<;(k9_e9OmhD$ zXa9&gxxlU)Kb<>qVqyN=;OarK--IeVa|_*f=XwLdCH`xf;eL-vw`lh;l#yq@bCYlX z(p%=OPA<%yX&34~d{9PiadF|aiF1nWX8)&u>{}kkuH>gH_ASLf{@8~w{-?hEr@NdN zO!qCwKmNG$+@GfQ*B+Ap?d3ALxZneeg)+^axcYE&R?%t-|Udf-Bd0tVnN^h^CwX&BR zY4`85|K@Tn+h%o4FZ0KK7T>NzW~&aZv(oLS$eCsTvt7G3>FFI?WwyzTUp^;gVXuL` zgI@s+Za8c|DdPQcWkX(k`N8LUvrtWY25s^6ks+J=J}~fs0bBZS>9=9x(k)y1{{72e ze@7aJ(uW)yd~WvfsCQrgO}ROF8}oLaIGElrr{UBa!hh@?a%|g(jr|YhUOjD$zvHJx z>A&q=-*0v9fa&`a+<7^ZvyV0$nUr3s;rc;0^nWAwiixqDzEfVESb6HY;JRmaJ6_-K zdvs}Ldc#$NuN%0k-+Q^&P27Is@X+li4tA@Mvu9%J)LVi}jv8<@z1N~feUDCPeMR5p zc3aQerR;CF=T96ArRG$gx<0tv&`Snf*l%}k<($;1H>)fiFu(sxx$ZJImAS2hjV|iD za6nZ%glP0}q_Y*=m0`zT@7b3ida%+tHDQk%krPe==p~iAeptDSJ;uvO=f) zzQ0fWvGsb7?!EIwD9b(0p8Xq7>FMrePIoPHx=WeUreadf7{a(u4at z!l7nrAaOe{AzhO~0bi<re`77QV)2wOlBXB`G^=x`pNDK(IK14j%cuJ5 z?%lVv-XgoL<(sEGRrB?OWAh5ec;>ywZ+pX64LP=D_@}wywFwO;PDyIe<7nma-HtCG z*yDKR#J)!>H{Ug6SKk-nLgWdmVP7imf z!|4?ogimqDZb!N<8FH-E@W+1)C%L`wSosIcTgbd6_dTA|x8O)W`_I+(chP|p$F8#DmIEh_EV1Lk11AnYXvdKK-FCA*s)y}< z9?raJ;E*Hf&T-6aM|&Jk&klDnQ(Nq>eWn~pziaI8V*9&wXy5Fk=?O#K?V9$(8|>Pv-Sg|(;MrxwAyW`q)R5=Q z@jZ^`3><5pakUTj?BCPfgKh5iTTczQf2v29zVE-^=Xf~#JyW~N4OZL}2`XT#UA;Z02nHl{u;`c10Kks1! z_x`2l<>bZRzrA|@GIQ+9%#lTlV)p($yy3u!+gBervBivSS(HA+-apUXmR--@yU^+( z2mPdoeH~o3*#0hZpSO$bbFX2uP^SCbbDv}X-RECT`@E~%?EYQ#ez{}LPk(N1x$IVd ziTnI^U(=dR-f&&{q)^hh=N>r`TC?`+E#Iu0QusyD;#HUZzUbPioev-1bXVOH!7R@aA=nwBX;L}|9Xy_}}_yZ?u zKOcPbd-U$u+dU(eeEi$q+v8IA(eKf5fITlqvX3t5*8k|D?%kT$GkAKl#=VZGCbS-M zz@G0<zuy&AzT~ z8D(Er&q!)isbO9F`ZaV))tr%2+}BEd#T!24Sna$TeP78PFfn`jP4<wsfqPwKua3fBO7I6}#2aiE@J_AV-JO2KUch;oRYuxr zf0g}5qWh06_BVQg{fGT7d^qv*sC~N;i8S#av&$yC|MiQe`u}KD&t_IA(oD0i%~qjE zbIm$7TigHQs%CAQZ9yPVs0_d05)xo!8alXlE@E4zQEX{Wkv_ph^diraSox@af6ZTIhV?IgGD{&m%k zx^4Hbn|7kxcK^C-`)=F)>!BTS+wNbsw*B5fk5+d7dTJ-wZf*Ckmv-1~yMMj44MIvJ z(#YFqkALb*&Qs&~|4*LO#U>-tC;FIOzzG@P?=#wQAp><)2^pj*A%is~WQeAO4Aqp7 zVVV*$TvI|uXiCUPO$j+e6CtCt5pt$BLPl#NWQ;aK&eBH6SZ#!yt&Naz+6Wo1jgSf2 z2+7e#NUkDmZ6M>`PG&->jT|J2Xy zi6_!O5VFFau_7~~PL2~Y+yC9pj0-teSCx=LO$jN|l#pUg37MlQA#*h)H)%@9&6*OjUQ#pM#!z&2)RugA-8KIWRo^R?$Acao!SVwOB*3~Ya`?yZG_ybjgb4a5pusaLN;q7 zKHbNfJ4uo9ob+yMo^(prpa!nwlsrxGPXw=DZLZ0-y z+LKCL$WywiggmV&AoGY}1sG=QSl{yQYNf(3Fs!nh4pYjgS|#5%Quo zLSE8F$jjOYc|{u`uWBRYHEo2vu8oj4v=Q>AHbQo5Bjhb@guJbdkUiQ6*{h9^ceD}m zt~Ns6(?-bq+6dXFjgbA?fsn_&TzmXe+u94?$P=-2|3{B+K+GJLJsPx z67q?rgnX(gA%`?2D(c zAwOs%Yec+6ehs8zINF5%P;RLQZHS4Ft z9YWLvyQg&ti7wbZtw-=(uzQ+Lh`3<)v_8Re!R~1TLV^YNy-q_y*af?%jR*#$e8m2n z-`*<*B=)R(dE$iwMGf4m*~a0h?0*dkoD4Ik-Q9c1hlL;uALO{_} z0*a;)P&A!@qH_o+nn6I(Oah8#5duX6!`>(Z5_{HWWRMi)J5mMVsPp9%6@~rt>>rxr z&qc*tUyA0irD!f&iq2z8(LA;k&1Xx|0=5*L&z7PK*iv*M8$}lpP_&SMqD2H0EheC7 z2?0e*2`E}dK+$pniY_Lg=n?{oRuE8hDFH<*2`IXZfTGI@D7u1xqALj~T17z7Y66PZ z5Kwd#0Yz660!8PBy_*b3>~8x`J5ne``{Undg`>`wQ*=Yvf5v`gD6Z&6t}jJv*;2HQ zEk!r6rRZk16s>1V(JgE#+Q62gjch5pm5rj?2q?OpfTB$V6x~5U(VYYo-9%!ir1|&A$y`a8ciq<6qSpy1dV_$XHwh@(O+e9G1QfkZ zK+zroiuMvv^bP?_MagU_N?}V;DqD(TY$-}(OHnzt6qRR7Q3bXXRb->65&=b(2`H*U zKv7i!imDM%RGomL8Uz&8B%tUd0*Y!8P*j_MqB;Z=)g_>)9sxz^1QgXLpr`=>MGXlk zYD7R$V*<}bO$aDzN(dDB3Esm7B=)fTfns7p@SVQOw%#=>!yYC7`Gq0Y%*jDC$8#Q8ocZJqal4MLw=Mn-%LlV4h1|)WydoCI( zMc245Z-og_=gTRYo8ad*k)rdsz7)-4OVNC`6fIy&(fMpCx_~W37qX@3BDNGQWJ}Q^ zHi{M#P_%@AqNM~BEhC_4IRQl%6Hs&s0YxhaD7ut@qLl;`T}D9B$u+Y>pJY;GT=FPl!5SPSLsq z|ITJobQ9N?qMO-Lw4NWIY0YwiHQ1mbXMUN0r^e6#Ej}cJx zH~~dZ5K#0a0Yy&{0!23_c&{0d*xIncSt~^=-E+~?2~p?EDcY9ce|NGJJi(9}rOVApu1n5m59o0YwK0C^|?8 z6g`{ZRXW8KRd@d##pk4Gsr&t(PZFZems9k4g5SD@6n(+Kv6XUimDS(RD*z`ngkS`L_kq30*Y!AP*jJ2qPheW)gz!N zoq(eH1QazOpr|1MMU4n3YD_>;69S5w5>V8PfTHFE6rD^66eW4ydIJ)>+5NguvKM@( zA8{{|PVu77ms8Zz^PkI-qD-zYMOkbqYQ>hK)@&(i!Cwr!2}cyAq0wAc;06QB=(SdDU=~aN8EGKP%r9yIYlEq-~Cre zfTChTplG<~ooqm2&D~3(5mHpqk(%R0oiC?ozUL2UCq)amz7(C$mZA&TQgk6( ziY{VH(L%NqEn-X2Vzv}5VN20cHj0)JP_&$YqKgSAx`cqD6$BJrNi(bEJJJwrgzvxGp=O`i9t0f|jz3`p!r_kw!66iso@MW1<5=gTSj%Jb`Vk)p4; zz7&1KmZERjQgoOtMc=Wd=zF#l{lJ!@BWx-9ku60>*(mynfTCjr6#Yy<(QyKbej%Xf z1OY|A5>WIT0Y$$PQ1k}@MSl`d^cMj|e-lt-zuz5v+m50z0YwP}6nO*`MF=SJ2`EY= zpeRZ}Q4%3g^o8g3Fd(sZ?#I<%O3`xn>N+_Rb-tXUw1}VARf@`SeJLu>mZA!5DXPep zqDpKjs?3(6Dr_mL%9f&PY$>YFMo|p{ifR&2bP@qYwFoGxO+Zl{0*dMqP*jhAqI3d^ z>Jw1ZfPkWg1QazQpr|ncMNJ4OYDz#+GXjd56Hs(A0Y#?}P;@E*MJ)({qST1D!hpmU zx#yx-B=}DMZ}%g}j7Ze^a*A3-{JXnLQERR*MQzwp)Rrwp?buS(o-IWk*izJyEk&K! zQgj+yiaN7V)P;be(+Mc*NQ6w?00N2z5>PaVfTFs;{~=q7Mss~B8pD>Nv)EEJmMukRv!!SpTZ+cBrDy_MigMUel*>lZL;{NP2q>CF zKv6ycMUx3AnnFO)R04{o5l}RpfTD8&~ zT}eREDgugD6Hv5V>j)^io`9ko2q?OdfTFbo6s;qm=q5s- zXhFm~%YeiNx?gWRUy7R9f8jN9b0q3~IYk>I{`q~S=vJ;TMYpk~=ytXgZDLE&9c(GO zlPyJev8Cv4wiMmNmZE#vD7ue;qWcLb+Dt&v0|XRpA)sh00YwiIQ1lQ1MGq5D^aue( zj}lPy7y(6(6HxR70Yy&|Q1lc5MNbn@^b7$-&k|7d905h!2q=1<5GcAO;%zV>v2pIX zXoD1;@4ljKk3^j>r|5-<|9pQbdXei((MxP8dYLUnudt=)Rkjqp#+IVj*;4cdTZ-Of zOVMsNiryli=xqXu_7G6Cmw=*o2q=1&fTH&ZD0-iOqJ0Du?I)n<0|JUZB%tUc0*XE+ zpy&VrMF$Be`hK_k{t8z3sk;?UJH>?mPW2BT?te zDf%|zM+ZsKVXiMl-?63Wd$tt)z?PyTY$^JYEk#G!QuGsBijJ|R=w~*HjuTMy3jswZ z2q^lMfTG_BDEgg%qCW^I`jdd7zX&M$n}DK_uW#E?6egf3fq){9fT9QiMLq#Vi3Aiy z2`EY;peUJuq7(v(QVD^guOr^61|;^X`-=9B6t!|+(PDno`ErUX`2L_FQdE)aOHn1Z z6xsjybnp`mDXPMjqN;2us>YV0>TD^h!Iq+$Y$-a4jiOov6xAl6s15-|bqOe{M?jJN zkB$fL6^iVCmOBV2YCu3yLjsB#5m3~afTAV@6g4HFs2Kr8%?T(vnSi2G2q-$0fT9)z z6lD-lWd9@O!F!9MOhTZjobMGHkk|nCd)MXt;5+@r?ujYOk2+sYQCr`?dYBZoplApIMMDWF8b(0TZ~}@(5KuIdfTA-9 zfuh#F_qYLx4EoDp5GPV>gXG_t=Y$>{gEk!HXQgkUBMJov? zx{QFL%LypDf`Fnc2`E}cK+$Rfiq;TNbQJ+bR})Zl4FN^h5>Rv<0Y%pnP;>(UMK=;q zw3dLPbp#aML_pEa1Qe|&py(Dtpy)#1>uEq@6WzCE7fDf7_qu3{%Ek*aRrRZL^6y3*`qWjrWw3&^f2M8$ILO{`00*W3apy(k2 ziXJAQ=n(>n9wngYF#?JnC!pvF0*am_py(+Aik>E*=otcvo+Y5@IRc8d5m59z0Y%#h zDB3|l(N033=vLobX+UCsx$pFElcKlmyvQy;>U=pxFZ=$zXGzg3TwjV_WlPa(Y$(1QfkXK+$^y6unPC(LMr-_7hO_0RcrH z5>WIJ0Yx7ZP;`KRqJsn!eL_IdrvwxoBB1Cq0*XE-py&$%ioPVE=qmz>z9s~UUi7`) z1|(L)Jr}(sMd!J%Xy5oz=gTSj-uHhzTZ(?*`cia+Ek!@FrRXSIihg2C(J{6Z{mho4 z<7_GVg)K!V*eLpyfTG_BDEgg%qCW^I`jdd7zX&M$n}DKFqP~qmQJ8?D1OkdY0*WF8 z6!`=cB@$2+C7>vYfTCmqic$zDN+qBuMnF*-0Y&8qfuh5{S8bdra{ulc`A&-JyI0rc z6Qj+t4YHTU0&X%GYY$>YAmZFo`QdEmAMYY*dRELeCx&#!} zBcLdqfTH>Y6g42As38GGjR+`eOh8c+0*aavP}GcoqUHn?olHQ{DFhUqNRJSp*cdBA}=>Ay8B?(L39K#J+W}t}7)5-|3HV-}bjjj5=RVQHMnT!dxlp z$n~YD6I+T-V@pwIwiIduy;9&8k46HwHXfTCUm6!j*cs1E@} zeF-S)M?g`30*VF@P&AN$qCo@{4JM#y2mwVy2`CyyK+$jlibfDnG?IX#GYBXeML^M+ z1Qd-X1d7@vdbb*oSfcwP)?SJ>+If*NiBadvDH@mP@5qy)@mybuCa|R_hb=|9Y$=+^ zmZChi6is4FQ9fIWCbOkz3L8aJ2`HLIK+$vpiq0XRXa)gAGYKe~MLvFUCfrEOW0Dhf-OatvZZJxTZ%4Y zOVQj@~jfq43jswN2q@Y}K+&y)K+&Q^FT;Su3fyziVkx>M{ta7V)cJCX z?o9NDOqHU$xV{wK&6c8j*iv*aTZ-;uOVRyoDca1Iq6gSgw1q82TiGajkbt6x2q=1( zfTBkTD0-BDqQ?j*dYpiwCkQBdl7OP82q=1*fTCvzD0-HFqUQ)G+D1Up^8^%aC!lBt z0Yy6rDB49p(F+6=y+{ZYZA$ct4M?nudqI7N6g}pii(X2MI$uuFYl;4~)1~Njt}jJz zu%+ltwiNAVOVL|wDSDeNMSIv%w3jVK@35ulT{eo|BcSMg0*dw#P_&IRQmq5K#0b0YzUCQ1mqcMc)um^eq8J zhY5kAR}#G^4M;4>y`X+oitK-<)4pL#j5=RV(T|D#2Q#GTDA$*wpV(4#j4ee!v!&=b zTZ(>ROVJ6o6#dGUqTkq3^gA0xe-KdgCjmu&5m59u0Y#yxzHLWQn1G@L0*X8WiXsFQ z`2-Z%w=coJaiSRexnYOtlKCR>V5VoOmiwiMN7OHm!R6xC%* zQ9ZU4rL$2~pMatU1QazSpr{c6MU4q4YC=F!Qv!;b5m3~efTEKLC_06JqEiVdYC%9z z1_4Da2`I`WpeT!gqE-YHwI-mb4FN@M2`Fku2ozO`dc6%u>|FPqe${C3oql)s#MC|- zb-tXU)1v;AbET*=*O#I$Y$-aOEk#|~Qq+wtMcvs_)PpTW*=#B5$(EvCY!vk-pr{W4 zMSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&YzXb1sCLkTDvMnKVU0*XcuP&AT&qB9668bv_S znFJJ#CZK2x0YzsKP&AehDC!vXE;k^tuWUv-NzrciTy%Cc>U=pxIZ^-qA}Pw{`cgEJ zEk${3DVoHVqI|X#O=e5c6t)yiWlPaCwiHcgqv#w0ie?Z{G?Rd$Sp*an5KuImfTD8= zC@LhNsEB}~Vgich5KuIifTHsVD4It=(R>1m77$Q$J^@7+5Kwd>0Yw)PP_&SMqD6#2 z(fFwMwgHK4b>EgvkfH+j>UwcB>U=px%cK5JbEN2Et}jKGu%&1PTZ%4aOVLWU6kW!a zqRZJ*bOl?Au4GHmDmIE%6Hv5V>j)^io`9ko2q?OdfTFbo z6s;qm=q3V+ZYH2;Jpo0x5Ky#%fTE2A6x~Wd(QO12-A+K!CPJWSY1FGR*A(4rGqOyI zzI8u5x+5BOzMP_aqJGDDQgkoZm!kXFQglCCiZ-*Q=mEAAZDC8%R<;y9$d;mq*i!T` z8%2*0Q1mDPMUN3s^f&=UPY_V_BmqTF5m59r0Y%RcQ1mPTMb8mXw2gqG=Lsmn@KS@zzN2+R4)cJCXY9{%q3#I5Jt}jKk*iuxREk$+MQdE~M zMfKQHl+Ko-`fMp`z?PzhY!o#jpr|ncMNJ4OYDz#+GXjd56Hs(A0Y#?}P;@E*MJ)&@ z${?VqB>_d51QcZvP}GWmqSgcywIQIWEdfRC2qO6isGJ(G<26O=U~bG`18?XG_sJY$=+-mZF(#6wM-_sDOZ?*#s1w zOF&T}0Yyaw6crOtG>3qqxdarQM?ld$0*dAnP_%%6qVowTx`2S93kfK?h=8Jn1QabI zplC4xMN0@MT1p5Mj@~jg@B?B1Qcx~py*Ztif$vI=yn2%HW5&C2LVNQ5>Rv(Ay9O2 zl9zC?DSF)f)7d3bG~AK8J1OdXIYsv;`3+Y{(PpkMMGvs0XbW44wz8$@LADe<#FnCm z*;4cfTZ$fKOVML&6g^Hr(Gvs|JxM^(Qv?(}O+e8z1Qb0>K+$sq6m27*=y?K)wi8ga zgMgx)1QhKepy&kxie4n3=p_P*UM8UE6#|N0C7|dv0*YQI1d8rW^7&HtJzQUk_Ohku9kvv`%a)?|*i!U9TZ;CvrD#7}iauaV(T8jl zeMCUf#{?7|AfV_V0Y#q>Q1mGQMTZC|`iy|0&j~2{f`Fng2`KuCfTFJnDEfwgqHhT( zI!r*(cLWrDPe9QR1QZ=1py)>eijEQjMZ1%{D-DSK!nI1p!4F1QfL- zpeU1oqAUW6S`kpxnt-A<1QfL;pr{=IMePYF>OeqIM*@mE5m0m*0Y#k&fufU=y^~g% zq8*6_r&eJU5KuIffTCdp6b&b!XaoU8BMB%vgMgw@1QeY~K+$Ld zipCI7bQS?cV+klan}DKm1Qd-YplAXCML7f%5qH_r-DkPw& zh=8JE0*dAkP&Ai-qVotSnnysDGXX{G2`IXSfT9fq6m2A+=vD%XZX=-Rb^?kv5m0mo0Y!HbP;?goMRyZWbPoYV z_Ywj{mnM6M4M?n)&B#hA8s@(3zb`rJd^ts1lKr$Bq-ZPGm!b#RQuGj8iXLW5(Iadr zdXz0ikFllbakdma!Iq*Y*(iF7fTE`fD0+r~qGt&xdX9jiZ3GlOPe9Rj0*ZDJP_&bP zqFn?Oy+AE%3^|@0 zb-tXU-;(_sZ<3OHn9A-?>Xsm@P#KY$@{CQWRmM$S0sE zk$|Eo0Yym!6eSZ-ltMsJDgi|?0*cZIC@M!lQF#K2DiBaqk$|E~1Qb;!pr{G~MO6tX zszyLjbpncN5KvT;fTEKKfua-1-m?ZIHs8H2`c;Zvbk9Y#Qlie6Q&ca-Kd@ek(z(7A z)n`jl1GW@3WJ^&awiGpHOHmWH6g6c_Q8Ts_HD{yfWCDs#A)x3~0*YD?P?SMHQA+}f zG6^WkBA}=h0Y$9|C~8AMQCk9v+7VFHo`9kb1Qc~7pr{i8MW+!^)R};yE(8>vPC!vt zLZGNliWj-X6xDN2KXp@r@AUt6zb4WxCF*=RMLkpe#v7%m7uT1f-fSuA!l;c(Fg*HMiNkT1_4E*2q-#}fTGa^ z6pbOE=qv(?#u89;HUUNB2q+p)K+yyOigE}j$|ay^A^}Bt1Qbmo1d4j3c>N7X%>92V zieyXCLvG}!M4d0EXj+PY&TUdOo$E`{IczDK!Iq+#Y$=+>mZAc-6wPK!(Yb6XDr8Gh z5gSFt1Qg97plB`uMduMvG>?Fy`2-X#AfV`c0*Wpmpy)yZiY_9cXdwYbiwG!MOhC~R z0*aOrP_&GIqU8h>T}(jHB?J_$AfV_{LZE0$inrQ;#E!eCpQ%zb)O|%;nG$uroT4jJ z{H>d$XcgC&qSb6ETEmv2tJqR>HCu|VVN21qY$>{qEk)O}rRWAWif$yJXe|Ln>j)^i ziGZS;2`E}mK+!D(6m1}&Xd?kdw-Qiv8v#YP6Hv5?fTBAHD7uq?qPqwvx|@Kadk84H zmw=-C2q?OrfTGQWK+)wX-n#}QcAon|;}ueLvinZ|ft0B8WIS0Y$G9Q1k`?MQ;*Nw3~pUw+JYDn}DJ{ zgh0{O6tDJOrYPcmd;dWx`q`1%n-X=toTB$r{4V!M(LSy(Mf=%O^Z{FnK4eSLM{Ftj zm@P#I*iv+mEk&QOrRY;OiVhJ_^cev~pA%5@1p!505>WIN0YzUEQ1lG}Mc)!obeMpm z?+7URo`9ks2q-#2K+%r`6dfg?=qCb-juBAwGXX`%2`Ku7fT9zGK+(G?-b4cuyT*MH zdryjPa9`ejO^G^RPSKw!{?hxT=r67>MSruUD3q%2+@&bYmZAi<6nShZim;`~XG>8c zTZ*D=6eST*luSTT3IRo_1Qf*xC`u!ss2l-B(Lw@>77U=q3V+ZYH2;Jpo0x5Ky#%fTE2A6x~Wd(QO12-A+K!CIX7?AfV_@0*dY;py+M_ zitZtx=w1Sf?jxY+egcX%6HxR30YzH~DB4O06s=12wi%FEihC|vEk#$juV@dZMx8IG z=+RXFlgFg!F|IE~kF%xd3APkH$(Ew0*i!T~TZ*1xOVP7zDSD1AMcddYdY*uy?F1C< zAfRX`0Y$qAD0+c_q8AA$dWnFdmkB6(g@B@02`GAvfTGt4D0+i{qBjXB+D$;wTLcun zO+e8e0*dw$Q1lJ~Meh;q(+@DrzjNjXFe@O;h4UYm!br=6nShZim;`~XG>8c zTZ*D=DN15XQ8HVKQrIX;C7>uqKv5b2Mdb)6Do;RB1pQl$fTGF-6jdRhs44+P z)d(o6PC!u&0*Y!9P;?RjMYRYhs!c#q9RiB#5>Ql+fTDClpy;nu?*#s2zB%r7lAyCvX=Dlw~VinwTQKOjtd-`tljzyg>r>K9-|8<)b z4dD7xG>|PtgV<6um@P#^*itlR6A38FBcNy!0Y&))6ip_eXbJ&EQwb=V zMnKVYLZGN`%&YsnDJt)N>ex?;=Gl3Xb7E2F%PA^|`CWHN(QK|SMdz}msE{p1MQkZ5 zW=qi=wiL}}OVN33DVoQYqWNqTEg+!id;*FtAfV_%0*WpoplBfhMT-b1T1-IE5(0{r z5>T{^fTHCD6kSX}(Io^FtstQ2QUZ!r5>Rv*0Y#S+P;>7a{# zEk*0uD7uA!q74KTZ6u)RRsxD{BcSMZ0*W>fP;>_YMRyWVbQb|dcN0)_4*^B@5>Rv> z0Y&!{P_&tVq6Y{l+Co6lRsxD1B%tUa0*W3c1d6VTdG{EQ*wyYk{i~&@TKpTfSk(D) zik^u1uf8ZnPjY=JdWtPYPqU@y8MYKX%a)?&*iy8OEk)0>rD!`_igvJ3w3C3MT?7=p zKtR!p1QfkQK+($t6um+~(W?X$y+%OM>jV_NK|s-)1QhKipy(|EiryxmXb%BJdkH9d zhk&AY2`GAxfTH&aDB4E|6g?L6ju?>G6YlBfaVe^6=SB9%qRy97^l{9u_=*%A;QCT@ zkS#@@u%+lzwiF#=OVMX+Df*l(MPIO`=u5T~eZ@x6*8~)OLqO5D1QZ=6py)dSioPeH z=m!Fdju24vBLPK62`KuBfTCjr6#Yy<(QyKbej%Xf1OY|A5>WIT0Y$$PQ1k}@MSl`d z^cNve^kK|vXFy_o-0xj~Bt_@B=c2!3QRmAk^3wb>Uz4Ip+CRV3_t{dE$d;lgTZ)p{ zQk2Y=q7=3irLv_c#+ITqHj2s-P*k3Pq6!2QRV1LO5&=b(2`H*UKv7i!imDM%RGomL z8Uz&8B%tUd0*Y!8P*j_MqB;Z=)g_>)9sxz^1QgXLpr`=>MGXmoqHvmbfdPqq=inry z1>d7pw(}y5(xT3nQ`9WYzxfR*YR>ibTy!#9icVom(Wz`HYQdJG47L=tWJ^&dTZ*#S zQq+o#qSgcywIQIWEdfRC2qP|pW4+4s^2`K7GKv6FOih2`J)Q5ngzJx$glQeI;0f{wtaGFZdHSWt>zqF|HPaefTBDCiY5_Ilutm>WCDt&5KuIgfTC#x6ip|f z=o|uyW)M&`lMpBxkme=5Wr}vX=c0j9^nxQbD=q4LIYotOe)Bz2RK)eAsF*E9bJ$We zmn}u-v88ApTZ-nhrDy?Liq22`IXRfT9%y6kSR{(Mke}E+e4masrC3AfV_<0*Y1)cJCXu21s|-jSjkxV{wK$d;nDY$;mDmZF>3Qgkz0iq^BG z=oYpVZD32$MmCCWC7|dw0*Y=YplA~TMRyQTbSD8tcM(u@HvvWW5Kwe40Y&!_P;@^5 zMVkpIdVqkUEd&&8C7|d*0*W3Ypy*)&iXI`L=urZS9wP*bu1)iy4yI$uuF(`o)A?@7@!TwjWwWlPa>Y$@8tmZIm`QnZ~dMLXD1w397GyVz3n0vkmy z5>WIK0YxtpQ1l7`MXwT2^cn$0uM<%81_4EH5>T|8fTFhuD0-WKqCEr@?Iob-9RiBp zC7|d%0*c-zplBZfMf(XT`hb9<4+(*yC)2$B1|&Aw{WJbkQq<1<3&=-lQRmAk`XtT& zeV-J4%Jrq_5L=2qV@uKJY$^JJEk$3lrRXcR6n)K>qHowz^uNfv@9-$fzy15OnVl?< zCCM(mCxD1T8of&Iy(uaRA%vnpFbN2V3W|z~ioKy??~1)ED)xrGEB1zpfQbEfeRj@w z61~6mcihkO{PE-f~FiZ8@EJYb) zDTQkVo0R@U0QlO|21&SI|pr{E2ikecO zs2K%{np2>t1qF&)QlO|61&VSgP?Sr7qSh2BYD0mdwiGDZivmUMC_+WiOnsY1$ox{2N0y>|vJ@4NrKpfBMMY#O>O_{J&SWX- zLYAVgWE6FyKv8!J6!oA$QBMjK^`bygZweIkp+Hez3KZ=}fuepCDC$pvq5%{r8c2bn zK@=z&Oo5^y6et=>fudm)C>lcVO4h4$lQlMxa1&R)%K+)k8 zD4I`!q6HKvT1bJSG71zeq6ig@&GdITAn`-%I5^{^XuXj-A~R;bOwr=Zpx!4^w1oMk z=t!~@EhS6QGO`pcCri;$WGPxfmZGD{QgjSiijF0tXe9-TR#BknI0_UUPl2M<6ev1@ z0!1fMpy(tD6s@5^(a97jI)ws7r&6G3Ed`2Bqd?K=6ev1_0!8a6P;@2*iq4`y(b*Iz zI)?&9=Td}1`=uHX~y+whdw<%Ec4h4$dr9jbp6exP10!1HCpy)%2P|-t~{$>XxUSLPp z4@=RH_DlO)Gh^n<6n&Z*eD;+Tea8G!^f_6Iz937{mt-mWiY!H6lcnezvJ`D2OVPJv zDf*6#qVFkCw4DM)KTx1(2L+0DQlMxT1&V&8K+$dr6#YbjqCFHS`k4Ynzfhp)R|*vU zMuDQ=DNytW1&aQpK#`ZFr|l?;P@pJ{0!2OrilP*uqK`BEI$t|QTMW)8QgpMC3bJD6 z%M{hl3Oa0)qB_hkMHyr%ij$?NE?J5)$x@U>mZEI36eY+~lq5@0Ju-^wQ=q5;1&SI{ zpr{cAiW*a(s0js%no^*s83l@(Q=q5?1&Ufypr{oEigGAWluLo4))XjeLxG~U6e!w@ z0!8g8P_#D%irQ14XdjADQ7p?J?|{UgwO2rDWrff5Z!l8(X2r~xDay|Zj`&WB3YcGt z3dvGbM3$mXWGU)QmZC0XDe6j=qHbg<>Q0uT9%K~tq(D(G3KaFGKv5qG6!oP*(S8&t z>PLa1{uC%0K!Kux6et=*fug|_C>lb6qM;Nh8b*Pl;S?wuL4l%?6et=+fuhkAC>le7 zqOlaAqK;Yqc@9YYS9^|@Cq*5N)VQpe`7%Y5vVwcIOVMQJm!c_TDcYYbMF)_jXewEX z4kSy_L1Za9m@Gxp$Wn9&8AXRuplCV;ie^xtsF(spGbvD1LV==L6eudCK+$Xp6wRSP z(Oe1?&7(lkVH7AjoB~DjDNwY40!0fcP*g^NqD2%aI)Va4OB$nxKFK;q^0 zv+Idc)WP;em02NR*{MaNU1Xf*|jPM|>1i4-V0i2_AyC{T1V1&U6gK+&lbC|XN_qSGi)bUFo!&Y(ci zItmn>Nr9rXC{T1Z1&Yq0K+(ArC_0Y4oG}I+ZU~uqMPjD?cuDL`7%Y1Wd$ey zBt?%izZ7jIOVJZ#DSDDDMNg5X=xMSPJwukFXUS6Z99fEE3KYFafuffvP_%^t zMK4pJ=oJbSy-I~mVb)_5?^gk%N~`Y>ug{2Nmk5!nW8VUf|q`lqA!_WioPOC z(br@t`i3k;+sIP%Em?}bBTLcuWGUKCmZBfXDB3}RqMZ~d+C_n)A1P3@n*v2YQJ`oK z1&V&AK+!K0DEgHGMZZy?=ywVf{Xv1EKPgb;W$S4>iXs#!N~1uLPl2K+1&RU+6s1$3 zC`J(~`Yg-e<$%QBu}8GerRZ|o7uCv+nJ-fm&kh>=CPj6bUy3rxQj|rOqHMAhCCE~g zBuh~}vJ}-POHl)|6g4EHs1XH<8dIRC2?dIpQlO|A1&W$epr{1}ids^js1*f@awt%g zOM#-+6ewy#fugn)DB6nxMeQh1v^NEc+Ebut9|{!hOM#*e6e#LQ5h|*a?e}s(;&lv8 zMt1m2{~3FD%gc_LFH=;M9UT0J6m?>LDe6p?qAp}9>PnWPZe%IyPL`q`WGU)NmZDx{ zDe6r|Q6CBv^`$`3eiSI`M}eaL6et=%fueyFC>lh8qQMj>8bX1hp%f?@MuDQ?6et=& zfufNVC>lk9qR|v68bg7iu@op8M}ea86eyZN5h^Ok_E$O}@l$PIR47G7_J}qyJ7&I2 z(f--N<(^$Yp%*=X`K4$oS&9xMOVL4ODLR-eMbpSqbO>3B4kb&`bg~r9Afu?50!1?^ zP*g&JqFEFuDy2ZtYzh?3p+M1G3KY$wK+$0oC_0=1Me`|8w15Id3n@@kMuDP56ev1^ z0!8H%D5{`9Q6&Y67E_>T2}P)Aa<>1Z0}_AFUOJm1MUCv4{*l=+^JR*T$_~CrlcE*O zFGWX_rRW&46dg;JqLpMRT1A$kDpy*5r6rDwZqO&PbbPffI&ZR)nc@!u*p8`b}P@w2S z3KU&Lfuf5kLPg86{kZQGon=30TrNfJY+tlKJ7&I2(T40GFOZ_knO};oAWPAeWGT9e zEJat7rRW;66kSV}qU*>~bUj&$ZXl!RMhX<&M1i84DNu9^1&VH^K+#4D6x~LFqT4A@ zbO!~B?xaA`T@)y~n*v4mP@w2u3KZQ(fuj2O==$^QnE5hAUuOsR)s~`fm|u#vk)`NcvJ`zsmZI;;QnZ~cML&?GXa`w}c9NxN z7a2uAQlMxz1&V&6K+zrw6#YzrqF*Rb^eY95expFq?-VHdg91f=QlQ97=xIBOA`~b} zqd<{Qfubk{iUJB0rBk3NMuDPQ6ey}qfucGTp`tId{SO?Fc$tgQucYX-)DyNu%zT-m ztVHlt z1qF&)QlO|61&VSgP?Sr7qSh2BYD0mdwiGDZivmUMC{VOF1&Z2JplBZo6zxlaq7D=& z>PUg2JPH)$Q=q7TB2-j2;kS)DMWyyu>&!&>O#ceo7ZoOA=F1dyNd!YOrKl_OOHntn z6m=&{Q4g{d^(0GCFR~Q%CQDHtvJ~|tOVNI06!oJ(QGW^)4WK~LKnfHMqCnAL3KR{Y zK+#YN6b++5(QpbBji5l$ND35yOwoaf;M8m>I*9qD=wPxGO(RRuA!I2!lq^Nl z$x<|fEJej+DVj-^q7pKSW>KK1lmbPwDNrnKokCIyPlqCnBv6ev1}0!8Oipy)gb z6rE3jq6;WcbRh+bE}}ru#S|!7Pl2LKC{T1MMW|>+!r$$H#2>cZ&(TuU%$}oNmWY`z zQ*>n_Xw*Q8u3~;Ex|%FS*N~;?TCx;fN0y@N$x?I!S&D8XOVLeaDY}`AqFX3XbSnjl zHd3JIHVPEoPJyC3C{T1K1&Z#XK+)Y4D7uFNMfXym=spS*-A{p{2PjbVAO(sZqCnBZ z6exOx0!5oBQ1mDTiXNjt(c=`MqRSJ09|t79(B8d&g%s7ZebMGb%zT-mrxU>;jil%q z=9i*p$x`$jS&E(~OVJBtDSDACMK6)1XbV}2UM5S?D`XVCN`a!+C{Xk|1&ZFFK+&5N zD0+(mMQ>A}=p70ay-R_j_b5>GJ_U+Cpg_@w6e!wCfufHnQ1meciaw!0(WewB`iufa zpHrad3kno{Nf9b~GT|TRfW%wdFAqH>MNx+*`c)!kzD&`#iQvj6QuH13OVRgaDcVk! zq94dow1X@~JIPYCi!4PylBH-jS&Dulqi7EWihia*(JvGz`jrAjzfqv*cM25!L4l$_ zDNy7k^|T#D5egKgQJ~1DKv9$eMF9nh(kW0Bqd-wD3KZ3*Kv5kE6lGALC{BT*x)hx-O@X5J z6e!w<0!8~$pr``{iaJuDD31a~`4lKBpg>U}1&WF&P}GScRFs|cGn+d_TkJtBkqn>d zpJDr=&dHehGDY2!K|xC?>cRX{)RQbly~tA3n=D0r$WqjoEJgc~rKlfSiu#kKXaE^S z11V56hyq1}DNr zNYNq8FGYuvrD!@?ie`|dsF*B8Gs#j^LYAUgWGN~oOVMmHisn$DXf6ec=24*NFbWhM zPJyEN6ewCifue;JC@P~s(IN^I9YKMjatahxP@t%i0!51{P_%>sMMqMgXekAXmQkQ+ zIR%Q2qCn9Kicrx(N&g}TB>uHM(?3{>Ua*I^qmwc7Wr|iMg9lnm(Q(W#MaPq+Xf;`i zP9RIsiDW4{i7Z8H$WnANS&B{}OVO!h6s@H|(P~3C0j4?wt-9h>V6tfE7791 zdv8+0KF%*YQC!#a>L;$w^1Q~0ZxWu@JW*8N^KueLHuSuj!w=qQv)uJg+j*b*Sep zO&m4c^HwAt9qD;16R|O#w>mLqoae1coISzw)+XMb{mwVo8i6>Tg-dl-`V?FP^#DrCzw>5G8 z@t*f-;{6jm@5@A+HJ-OEG4B-5+n%^}t>^7Z{CK+O?Md`L)AN2yt~%ST|48zwbKM4r zB8~=_0oYBFPKayKN9jet4%U z+Xw#^@#+=X&-Skh?{f9$*7CfdOJalDrVV=dZo_tVcPY1ST^(6}^F9%;;cag6NY~6W zTbypiZG!G$X!w|2Mvu(n-2@N0Z?{3cMz6YiW~8U4e$8Eeq?f|i zHfwK%A1w4ym=w0!5nK3?O-s?QAT^u+yNKXSuzuW?)T*D?9A6Ei1xjSE$8V)C^wpZnG_ zuW=vsZ!-CfZy(>vYdl=_H({OT?!ArIs*AKw-OOnJQElCnH>s^3wvj@w@%^gy2`j&j zbI|xKx8t;%);}zRczBC1RXsJV(-SAWf9bnNd5v#SU&iF&t-f3JNldO=Z6Bj*mwqXe zhqwAg)ps+wZuL9rUtsd^R)4PgQ|cx!Y(3a(JTwTmZ)0}_Zu_PuRzGpxx}~WNyz}>4 z3fu+`;;nwVX0hA8>4~$q+rK19Jlf5gcBIP_)0VpbQ`g}&-`6dReFtfNdh_$$Rt$r@=PJ+h8+v|buZ-RqJu^nsbN6VS zWB2E-o;B%_$cTCocOsVSa)G-O)~XlD$Ovb#zII*Duf-)~WYo=wXY_DW)oJvXsWRMD zHLfSF7=%|_R~PA`U1X*%GIehCMP}(DHC48oDX3nKL|wOhcFoDu33v1B>9*-g>UXKJ z2>qJ$Y2tQP`H_B2SgyUBBqGW5{*BKc*u)m1Va>_Y8r?I{t++-tyXNk?8lQYz#I4|> z)Ea7X%5f1dt?`)y-7ci5JHxXxJg*tkxCgL&&#ri3X6icKa=Cp?TAJHz5w{1?|EW`! zyf@s*G_UY78#lV0SKxJD>NUU2PTrY{-7F>@^ZM@FrnIr0`%d?2eYn`2XQvm1`2)-L z0inmZZ=2S}=iPV2J7BPrcc}Ze+QyN#5A~+Ba|&!1uIo)Lllw17i=?H63!JK0%$aVP z?AtEI#;a1x*r~!@ubq4=6+2tBlZ)I{2VUppwv_HV+NZ83buQP_+?{Z%#(lY4pf6jT znqM{ZbqUAWD|NG^MSgXJBJRsg>%JrT`32?01+yy_6;za$6qHY|C@G!3sJyJQw4}0h zRzXSmvPG3;R+N;^T3lXQQR6(D-c8-JU{U$J1@kKBEh+U1=9VoeEhwH}y0jpFepyNJ z{DO+P#pR_1<)sTtD~c-$N;^%js9Zd2URgn9S=s!OxyADqRus%BDVbhezM!C}aC+zI zoeDb@O)o06GS8KH3(FRk=9L!DoR?QrnBO_i&dzsd|K+TLc?(PCFP>Feu%NhP?!1Nn zpD#wmvWl8(V$R%x0p+t6&s$hFsI0s+uWDT^tt?Nil5mZTFE2aHt@Db4NsEfh4H5F1nU)k+mfG6#yl_KTES|Zjyri&meu-I_KC5(g@#6WF z(<_%PDy_($YsB34nl*1>r3((`q(MWbyX7nyRJLG2*+SPjeTbQ7mmOA~JH!f7JpIm* zAgK4xzJf@)KPM6-{U-TAP!J@02SIwSm9yPke$$-vzCkiQlABwY*CKU}3;$qrGp731 z?ioy^L6BiXR*++Z>r*ku&DJS3Sx#Y)Z0XX!oH#XaPB^Puvh=n=PI~?SU_M<*VL@(- zAZIUkyO!G(=W6->+4wIPg^MgKXx=)=Y3nX?*+05W)&V2e^`BgJK|$-hAg9gW7nh6r z`}iMSWRTN3NY>nF{}0Ypkei#jy1%aNzb`iVKU$FR0-M*^c>mSx|5vxZD7Rx#L1CwY z)&>3%`K{blbCotW+DAoGf2nPM&SN{1|JB$qygfPTP5!RvU(IFrxWa#b&#K?Dpde`2 zFKFV|>SVf4<#s{^!y)hy=Ck2aVF}1q};Y2DRPoXyoprHa1L++B#X`eRwb3hf^`% zP1Y%Bk{%fqG-{Qa#hvc^zjWFyPC;(as6~xM$<-n;{&msX)?Bol)S@*^ub*cN#ti@X zHvNMcQ>!DKGh7>5-~Vzg1P$GK$n98TfmxUT$=q())0$ z6?1~BEzwqMXOxY()i=9o+pdM({Dt|BLHnSgKi^hOZqOtW)U6*hb=OtbZR&8;V%7^c zb$hMPRLpUcb<$+Hf18cjwK@LV+5h#mx`jxyYfg=J(P?=>-BfUkks94CNR4hWlxy4Q z&&ml4zj;nz>nbhXpOqgpu~W`>IB8h7%nurdIS6d@uRT_c|F)N(dfaj|TiL+QcK5$< z>U95IceZ<|E3kW-A9tty#X0V=#?9T{-P8QCaL3Rv-LDgIaY@bngjrN=cg$3*Z&Ri2 zrxqK#usl33d^okTYEMzUhj91chUpDbH_1p+)Au| z7|@+Thd#OPBB~C3Y?F2h8rW{LUihfuPWSy^I_;LJz#i=C*+OB&Eoo}u{<={A_;@Uw zUAHNm?Z244UO~sA+rohom9d{IPz*gWMYm%uOZp&9MJkqfv6BhU1E@rm7 zHJKw*b2$8gOW8R=!`8V4-GbWP(*1>f+#MoPRP&+3?mGYcQSEPgR(n(nC-1BAuRHL+ zPwqCZ?W430u~ZQ5V8VM-ntNDHO;V8h-#yUU=yvvD8SHIi>TaJZB0-*wIpNMG-R(2N z+QI8%+p%8U)p%4)oAfUq*R=Kvsvp5>vn2ocfiPT;|Lywk{kQeMz}+qX z&H8VU+S&IjDCl6%S8NS8YU>~Q*F7|Q>gusR6W4doL8_7evkmlbSGryD|K)QgH>-Pe z`Ui*R+{6Dq{wE9Lb~o-B+<*Jb;y=3ydam{V##Ok3-@hLoM{@h*q$S-?W+o09HhpN} zaL>k~9)-iF&kRp?>r!>H>!7NW-Fj%sEwG}Tz$Qrs;+lH)wK<(ap79jPR!b^YWkk3=@&1om^Wu(>8u?0 z6NS_j57H7A4dqhY32yL^s_Q6nirGzJHEJAl? zb*nLTrd!3DuWQwXx#i(XJ8AmP)ypxcYL22oT$NjJ&0!X5`~>cQ>*r2`OJ^>g#KMdBqE-&o5gzC%l1flenvQKi#UaO|)oTs+ZPn|8VlEn+LhV>RZ>d>XsBa z&EBXX2TmU_cw%Zkw`p}F9cG;x{FgbsiPP=JQg5TIr7o+QRZ$IB)%)h6ZthyEv9s58Yb#tBJKHYEjk@L{ z=RZ}k9o_y;XLYVxg>FSKd9?&KGTXRnyY_JFudM1G;lOBK9-VAYrpnF31v`@A`f^vB zI^os?=T%=sYLQZRd-oG-P0x&Od!!oM$f*at@Ud=4)!c3i=n|`!fNkv7kj|^xmTnV- z*HCT4?ZezusS8h?<+iQna*sedRdqw0yKsKD6Suu-dAL@J!a)zj)f$SbIaCR(R^T4v z-Q`!zEi13AdN5_vnXuGGuiD;K2LSGVlUfGbCX?LD3S+`0a_b~KQ3FEthA*n#@2*=a&^%=DC-e`nruX%L+H;>_tnu=2a}pn^n}!HO1v6bNjm2o|g2; zTadrNy?WJQR>h(Yvlr#$&B@6d*C{8@y;{<@#4SMH>;oKrcsZ=tKg zgP%Ox_Ac3etI|Ct?1Q#Z@_67485cJW&m|s9LU}{AUkjAQDFE>!rK5^VRn2)JjI{M;b&L`Hdq@ zB26RBBF!T$(^^OJ?X~Q`ebua@-VcA)JlnSyJ8OLTdM%yGx7RvreEIHm&SZ^juevvI zc~kfjygL=1UsyF;c>W^yeu3~SJU`pLcYtj3cdUBFzWP;sJKuM2QmFamdsP#rYTtA3 z$E@+?d-i6D>M!4O@6oLB<$GB*l3l)gJ3x&u-*a!psPX0h?biD4*4kUYY^~XLOuE}U zsK)f!?(~Gee7}duSZ2agE07G~TW8bhjz(axT(%jmFzGKCJOsjc;iD zSfjl+$(HX>8{OqRY@>TSPFqL9`u%Kl{ex~yYwEHyW#^liG`HF9KIndoklMmFnll^S zBwm`^P`Ng`&EHNaJpI8!h|p z+r~a_!`nDQ<8kh-mX^=Z__SN6mS5MH>E6O@xtYev?#;}Wi#1-yb6VP2;3cDDg+`bRYG**DBVhj834FC0f{T0V}rx7|Ilz8 zqw&PyVLn^q^CQFjw#MX`Ft^e;bzGQBHC{R)%r|QMbW)gq(75mZVeYPR(bO;>t?}-I z!u+_#-=>AR_95XoaC$h7)3~NM%;#!+(LuM{_pZkJv%{RL@u0b3o}+PtyF=LYH*5TS zewcS^>{u4&o*K)K2=lQT@2v>)6B_?m9OjHA;W&6{I8M-b%JMLuuW`$YFu$*{;jv+E zqjB1*FwfI?#qnXjRpXZ@g!xB}`D?=5TVv%ZVP2*2{X4;`Ptf@A!(o0-WAxE5Cp3(2R%m->b>w_>~ zrtz(qhJsP*WUlp+J^Sj1w+rm6ZKyM-u>!=pF{d$At#TsvMzvp220gb!dFFaUwhuo>Lm;22J%fmFT%n9>p8lP+(=2ta# zbiY|-)A!UkMB`{11J65HdA5z2o_CnWGW9Doo~-d4oqvJGOVr<>@g9wvHNLFz1C8Hk z+@mpY@Bg>u=%I0(#uAOoHJ+vMdX0~2d`sgtjcM+k^>%p;H14Z$fW`wgF4DM0<7FD} z(fFdq&onl1Z+^GSZLM*H#$z;|r12IT-TJ;=;{zHW(fG8+=QTF8<1}}e|py?px_kC#8QqQc8}Kb6Y2GXKAL?IJbP zEPF}Dy$&|J%w1mUbn(oY<)ur)iwqn0{_C2txZGa9(Upc%{Lf~-y?a`h=$6{cFLCem zEp;!})wtH#<;4r!L<1&{$uF*~ET1=XaizQ1|MbfpPP;u|_HK)7IE#Dp{ zawF3fbnV1v#r#IC&{cw%b57sz+e~r`kR-GQTW5dDjG9%-* zFRByG8MR~Uft&Yi+vvVGxbJoD+e^!d?=@)mn8w3*_is6Fd$&GAcE@7lc5T{!;Er1- zTsrESku&BzzGvG?_r2A9Z+d*s)|^%|8qZxF`R%nx-w%pim;K$#!*heqN4Vu)bfUYB+h*A1_TLdJIetXN$jy7UW|z#EH1|O7x7S~B^V@kJ?x}y=(+w9aD`yJ%2Hx8UL{Jpo_Egv#@)VS?_EqA-e585&Ipo7P_HF@Cs#pAYn z{Ri#dHgVkc8Sz28ziHss{h@A}4eooL`(F9sp0%q+?U*syPP=bgyPo^bao?NV_xR{u z?*IOFYT)j}8rV2!$EYcTchnhRr-$wMe#(b?Mn5`kd#wzYZH{c~-M7u-4IDmf_xFwL z)X3favsbpWQ|^1C`?l#8x$hje2GV+taHnRtt(x6*M$@_HyS322wXN}yJ2oBAfA`G| zhV0JpipF*t-ONqb+^!`xXE@KE95;@4^Y(8%BV+ER;ToKj82McBq_RW&$9Jym|BKst z8xI(?qs^3BZL{0tj;%A|&EoNM&YRg_#^gD#&div*KAdNKc)v&+{dDo8&dsPfy|;SV z4g1?KoStyYoCoYTNqhY`?rQrL(Y14fi|uzmo48-}>>r7&@^WT)H_uD+-nl-#Z=1GD z-+dwXs>^%-UiiTVcixnZ*JovTt5$upU`-_M#upd(?y)FsRm8KSGtayFhY9T$Etz)w z%4qugIc~2p(w)yea+U6pE358F{?KD;oL*7m^zs^~m)1DFq{ivWs?-0`J+gK6J#t#j zd*qaoQL{$;k9%ac-6L1Jbs6cEx<`($zDFK7;(*a^E9oA|tsA#}TGc&rT4D7*$NGPq zhPZo*7pXV*l5mSn95~ zd;dQ^-C?wwBEoWdIm}nRR9;T?>2bUIFCw)_E#aiHsU~kgO5Xm%ceEK_t4)(J4M)FG zJYmjbd$x|xo-t`o)xCX6{ZaKtHW<-h_-Dm-J;QcK20Ht`yPxNLQvA@Dd(QA4`F94* zDGuY_nw8$EPoDOBZjX%CZ%#k^n!IOrt=KoB$IfVEANL>@e=X(?7HdA@If!YI^fmVL z;7F~j+#yw3T5!LcC@n2^jw}6!?!hE&Ok?-+MfXn2pp!co@Nc)N#x z58Y9GTCLbn_vjam2KG8$S~T{uo5b(!Ch$Af8(^nzbXV;c)}QQ72lm_~-TvF?zGLiqrix=&n z*v!SQUbLfPQy05=(LBW_E_U~#`HGEQ?BPWV6dSqN(~A}=HgvJbEmo0o1Iuo?Iw{w; z>=vxEay`p#$+{>fExSeQs+_RwmaUs|wq>_)-IcQ}yQS-)oN3uDUQgw^mfiC8QjWXa z$t_=RDoV&WMF|R~aGmlo4{6GC~el4uy>He|6hGqryG^i;fJ1EOvXW==_+;F(Hcr`{13F zkRvp!gp?~vNQI(=R4PiyVnqpAq9`FpDoV&wMG0A^C?U%g5pt9=LRKgv=a*{Ga)+i(7WMzb$qKuGJl@YR586l@B zBjj{tgq)#_kafzTkcEB=x68;Fu24qEmC6XYN*N(nDAPbl$AsJ;*avo{ggl^GCFDUx33*6SLLOF>kVh0H zWRs$VJgO)mk10yXOLY`Gd$aBgFd0rVIFDN7A zMP-D%q>PX)$_RN`86mGIBjiDSN zA-k0k@{=+`_9!FdXJv%^qKuGVl@aorGD3b=M#vw^2>DYv6!N~m+HL=gZ|&IQgOrf? zO|}p5A~B<5pDY=T1olyXslPcIL^QWPSu&lhPnL|4^~sX8$ogc-+GKsQWF4|TSu%sH zPnL|6^~sWT$@*l;OfsJ=nMJ`TOJ-B>$&v{QK3OtJ!6!@Bqu`Sz>r?Q_k_{;MWXXmU ze6nOC3O-q~F$JG2*@S{mmTXGFCrdV?;FBerQ}D@>EhzY8$(9s+vScd?K3Ot{f=`yr zrQnk#TT}4Kl5HsXWXZM^4oFti{ersxtOF9i(+*GkNT|sD^vFH;iNuVTDcUCz*hfXC z6z$9WQq+MgMIFgflt-4Le6kc3kfo@QEJa0RDe6R)qRwO#b)i5}R|*t$qd-x23KaFA zKv7Q$6!oG&QEv(q^`SsfUkViMM}eY#6e#LXfuaEvC>ltCqCpfW8cczrArvSYN`azb z6et=_fua!Cpy*@@ z6rDnWqEjhQw3Y%zr%|BjbP5!mL4l%m6ev2A0!3$0py+IhP|*<)f4u_|@8OEx|#w-*HED7S_%|hM}ea2DNu9+1&VH@K+#PUD7u*fMYm9(=vE38ZKOca zZ4@ZFodQL7P@w2e3KZQ%fug%9P;?IkiteQd6`dFHKXyRkwe0EF`BIc;itdZV%$F&8 zC=%F5Wv3K9%=}XH2w93Yk)`NSvJ^c=mZHbWQnZ;YMNg2W=t;5^Jw-;*(-bIrh5|*; zQlRKL3KTt0fua{EQ1l`Nie92X(H066y-b0kS13^QDg}yOqd?K?6exOw0!439py(|M z6unJ>qIW1z^ezR8-lIU#`xK#~2O@rZ2PEFi_C*g$k^5jm_k1l9Ghe3Y<49m1wVqP+ z3G++Qr(`Mmj4VZ;lcnejvJ`zumZGo7QuH-hioPLB(Ka%QzNJ9XcN8f4o&rVNDNytS z1&Vf1plBxrigr<;=tl|^?WRD{PZTKHLxG~7DNyta1&V&9K+$g$DEgfOMSoDB=uZk1 zd1+P8@-tJfM@1-5ltvLM+8Xf}Iw0{2+$){YkEG}d+ZXw1G4o}LVrhYWRDViQE#{Y^ z+GHuJLzbcpvJ}P1QdE~LMVVwN$|6fqHd%@iWE3SSP*jfsMfE9A)PMp-4JlC6hyq28 zDNxje0!2+JP}Gb9Ma?Nt)Pe#hCreQQS&9nD zQdC5iqE2Kf>P(iRE@Ua{N|vH-WE6F$Kv5406!oM)Q7;M<^`<~k9|{!pr9jbs6e#LP zfujBtC>lV4qJb1B8bpDj!4xPOLV=>86et=-fui9QC>lY5qLCCR8byJk(G;PgebfA3 z9FX`(_nymW2PyLHnf{oxnE5hA6Vd|vQz0ou6PaI%CXuCRGFghIkfmsUvJ@RamZGU- zDLRlWMF)|k=wLF6rct2i5DF9>N`a#36eyZOfudpx6wRbSQ3(Z#W>KK1lmbPwDNr(FzrO<#UuXNG@lw>r z9?{CvV&=;fElCTC+ey)p%r8Yt$x^h8EJe%7QgjqqidK-N=xDMO9YdC)W64sql8mBN z6ev250!7DDplCG(icX+F(TNl&I*9^BYba23G6jlGp+M286ewCtfuhqWP;@#4iq4=w z(K-qgok@YBvnWt>HU)~#p+M2O6ev26B2-kF=AY<*#HZN-^dDY`f< zus>Cl+83>7ekr$W@DNuA91&VH`K+zo(D7upZMR!r4=xz!W z-9v$*dnr(K9|el;r$EsI6rrLE)BNWhkodZYgL9D-HL-osgK07IWr{YX1@@<|Qi>jB zekpp4EJcr#rD!u*ik=`#(UW8;dWtMXPm`tS8L|{TOGeRi6exP00!1%Spy)*k6um@& zqAe6CdYJ-6uTY@qRSFcnMuDQ&DNytV1&ZFJK+#(iD0-U$Mek6c=v@jFy+?tf_bE{H z0R@Uaq(ISDicrzRX@0VUQ)HhP5q(687TMADM`OxlIBl!K;koOU-YRIZMTr_$IO>0s^bUtr}k2cGMHbA;$$hROO~Qc zvJ_>Jr6`*$MG3MLCCO4$k1R#?$tY?-fue>KC~8E3qQ(>`YC?gcrW7b@MuDQ{6ewyz zfufcaC~8H4q8tho=P@t$S1&a2fKv6pi6zxrcqV^Oh+J^!~`%;98YWe=9 z4oG~ZyqC?11bSN1` z(cVO4h4$lQlMxa1&R)%K+)k8D4I`!q6HKv zT1bJSG71zeqCn9R6eudEKv4w+iYh5WMH790Uk4=K&~`tQq-cZvAbYVNGhe1?nIG7n zicKk6&iqnz6j_Q^kfrEovJ@RdmZD?HQnZpRMXShCbR1cVjwhpNH3f=Jpg_@y6ev20 z0!3>mP;@c{icX< zT~3ywE67rGC0UBDB1_TLWGT9aEJfFnrRX{`ims=vlH9Jx7+J=gCs^0vSawQlRK13KVUjK+($-D0+ngMXyqz=rsxyy-tCmHz-i_ zCIyP#qCnBx6exO!0!8mqpy)jc6unP@q7Nug^dSX`wo;(zBMKCKOo5_LC_+V#`u=YY zNc>v+spDf(G}-n=pZYQLWs1J^1N&3wDMeo~zZ88Q0uT9%L!%NtU8sWGU)RmZCmn6!oP*(S8&t>PLa1{uC%0 zK!Kux6et=*fug|_C>lb6qM;Nh8b*Pl;S?wuL4l%?6et=+fuhkAC>le7qOlYx8b^Vm z@f0YUK!Ku(6rrNRsQ;n^5Xpt1XXZxZ_(U|!%MF&KK?*~cIROXkW1Ibc!5Lt>2 zCQH#YvJ@RcmZC$+QZ$_`MKj1!R7^(EObQg0P@rfQ1&T^3P&AtYMRO=nG?xNJ^C(bs z7zK(Br$Ets3KT7%K+!@96qQk+Xb}a9j-WtMIR%O;C{R>Mfuh9}C|W{+q9Z9nMN^`F z{lQLAJ$nUYe<@mR`=X`MnE5hAE22Typ;B}-^Gne&WGOn9EJZ8HQnZRJMaPk)=y2nC8ZQK0BiicryIQGbI265nR8fNYSWBkU3Fv1rVE znW877!J{Lk=qcuxqNmAH^bA>wo+V4sb7U!co-9Q#kfrEFvJ|~UmZB|W6unG=qE{$T z^eP34UZX(K>l7$@g91fwQlRK93KYFffueUPQ1mVZir%9@(fbrA`hWsOA5x%bD+P)^ zqCnBd6e#+H0!5!vpy)FS6n#z+D%u?NKX*Xl#r7cfgcLn#&-A~D#>|%~`X(C0#z@gN z=9i*x$x`$kS&F_VOVM_+6#YP!q8(%@+DVq8U1TZxk&L3<6e#+M0!4c$Q1mkeihiL$ z(XSLJ`i%lbzf+*-4+<3hNr56S(9?DlxxZT-zWk1&Gzt{?6ex;PpeUd~Q91>RViYK< zMS-H)6ey}gfuanGP|;UWzoP>ZKgfQQ=xZrzWshj_AZETyQFaiF87D;v=9i)*S&H1> z1P<4P6xAn7Q3J9RH6%+>BeE1VCQDHhvJ^EXqo^4LikefPs09UzT2i3M{ps=WMxe<3 zP3Evbk^Ae~VS%F76ewy#fg<-;?Za76v=;@6+EJirZweH-KYJfu28#BfK+(PwDC$6g zqK*_O%A-J$`^)O#wV=rT_2;laQ6WXBC^PWO9guhrd*5|d5I)n-wjEPZ5HnwlnAqTv)M8bN`gkrXI$f22CRttc8zfub=KC>l$FqHz=` z8c%_u2^1)rNP(hB6eyZZfuboCp`y-#f3E`)A5+W0=^{m2EbJe|%$F%TC3KY$!K+ysU6fLAcQ5gk_7Ez$+2nrOHQ=q7V0!5V+C|XQ`q9qh4I+6lKODRya zi~>c=DMCe41OE>PB)-KCg$|UW<+d+6Du|gcQ*>+)wAx>aRx-a7ts+a&abzhvo-9SH z$x?IzS&B|1OVLSWDOy98qLaxeI)ws7r&6G3Ed`2Bqd?K=6ev1_0!8a6P;@2*iq4`y z(b*IzI)?&9=Te~PJPH(@Pl2KfC{T1E1&S`BK+(k%C|XZ}qDv@HbSVXjE~5w)9Ub_C z9gz4`ds=pk6s6g5(S{&qzD&_oK~OqXimqmUDY}L%Mc0z0=sL0#T~C&x8^}_0BUy@W zB1_TDWGT9ZjG|j9P_&T(MYmC)=ynPe-9dq(J1J0f7X^y$ra;j>6ezlv0!8;xpy+-I z6g@zJq6aBZ^biG#9;QIiBNQmwM1i75DNytn1&SW0K+$H3P|+2Ee~JSVKh1vXc%>9Q z<<5&f5yZ@wDS9RdZaheeo@IV1dX6kb&y%I-1+o;qNS30P$WpY0EJZJqrRWv16unAD z(Q6badYuAAZ&0Ak(N`3qqNf6XivtpOe|*V{J}pJ*_K5a%5Hnw< z=(`~JVVV?u&-_xfoh(H^kfmq`S&DX&rDzvfihd+Z(QdL7{X~|cJ!BO9Oo5_bC{Xk( z1&V&7K+*3MDEfl}MSoJD$V=CeF^VD-C`zM1kxzl5CWa0!4KxP?Sj#D%uwK4G(dO>~+`Zw^Fpxp7v*@$IO>0s+S&gpDso9nO}+; zkfo?0S&ABwrKmAkikgt6s3}>BnvtcbIa!KYkWti<0!6JTP?SS~qFf3TwWdH(8wwP) zr9jbM6ewy(fug-BP}H6RMf*^oXkQ8xb)Y~|M+y|>QJ^TF0!0NBC@Q2tQ4s}-I#Hmg zGexK$;OGQSk{B1=(kvJ~|pOHp64 z6zxZrqJCs4>Q9!U0c0r}NJh~h3KR{dK+zBi6b+?7(J%@W4W~fS2nrO9q(IRq3KWf| zK+zZq6pf`o(Kreeji*4-1PT;Qq(IRm3KUJIK+zNm6zxxeq5~*UG?gM$)Ggh=!U2h& zYsW?1rD%)29CBcK%zT-mL(+rCOQh&f=9i-BWGR|KmZD;^6wM?{Q3+X!W|5_+lq^NF z$x<|jjH0;|D4IusqQfXqbT|cy=2M_(0R@T{QlO}e0!51`P;>+ZipnWaR6&8FN(vM$ zra;jW3KShlfuf}pC|X8=qU97QI*I~CD=1KOG)1WB;B@~>2PFQay}xLh6pgn>v}4j^ z=F1cvmmbufEk(yOzZ9(|OVJ5rDLRoXMJJJ^XboA4P9{syDP$=+l`KVT$tXIF0!61& zpy&(=6s@B`(U}w|I*S5DXH%f)910YjOM#;EC{T1h1&S`9K+%O1D7uIOMHf?`Xgvjr zE}=ltr4%T-i~>a)C{T1c1&Xeq2o@Dw~cUQ=sSz3KV@wfugS{Q1mqgioT&h(Kd=u z(X;9P{SHX{M|(tjPKx^4)BbPMW9G{g{g58KJ70=+FuxS-BumjQvK0MDmZIHcDf)>l zMSI9n^fOtCej!WIuVfVcMuDQ=DNytW1&aQpK#>>I({>a^C{UC}fg+y*MNtYA1r#W9 zPhY~9%}^AhKv69U6xF6cQ5^~tWl*3fPJyDj6e!B1Kv5P2in1wCl%NO|eV^`o3!I`$ zZ1=NWiXO6~>trluzD!ZWSdd#LMU9wWiW-xps0mq$nv$ic8Ci;&lclHyS&CYcrKlBI zigL&(%B4V2YYG&#p+Hev3KZ={fueR4DB7C>MeQk2v=0S}_N72k2MQE*q(D&~1&Z=1 zP*gyHqCyH36;Yt569tMoQ=q5|1&X>-pr{)~sHlF-AL@X_54C6d4PxOl{d{|--#r#H zU#6&cESPhI6!l?#De6m>qW#EH)Q>Dh{mD`^fGkA=$x<|kEJcIKQZ$5&qM;Nh8b*Pl z;S?wuL4l%?6et=+fuhkAC>le7qOlYx8b^Vm@f0YUK!Ku(6eyZRfuhM2D4IfnqWvjQ zbN~g4rc$8jKnfHcM1i7%DMCd(WBytPB>sVm(Oyz?hwY1|#bV~m6wQbQH&;keG4o5& zOtKV}kfmrAS&B-@QZ$<^MRUkfG?y$z^T<+k7#T%}Q=n)*1&S6>plBflipnTZw1@&l zM^K=soB~A^6ey~sK+$3f6fL1Z(UBA=T1tVUWfUk{PJyDMC{VP50!2qtpy(J16dg-} zqLmb(qC;c;D-KA!zdbFRE=7N&yRa%2Ghe3Ygjle1u@s%i{8DrhS&G(>rRZd`6rDnr zqEpFIw3aMIr;(-Tbg~qkK}OL!3KX45fugf0P;@p0iq4@x(YX{TI*$TH=To5Q0tyse zNP(h@C{T1U1&Y>Fpy(0`6kSSzqRS{yw1EOems6nV3JMfmNr9rPC{T1YMX2cbnBRDb zQ*^nD(bZD)mK|ze6N{NIQ*=Wt=($viZe)Hbx``}BHt7WGVWcEJc5iQS>JTio9BS zLXDyb1&Y!rP~=mfC`y5%fC5G76ex;Opr{rFifU7!s15~+GAK|Kr$A9%3KV5hpeTz1 zMcEW6N>HFENr9qz6ey}s5h~gd^S^dL;@8`oWOqtYXCu|1R?K{vq9(P1jANy!Df3HF zGqMylCreQavJ|x>OHnJb6y=bmD3>fnt;tfnWFt_1rt_DQ9tIFqW)wl8bFq!fn+Hf zM3$n#WGNa#mZG6#DH=wWqTyr|ji5l$ND35H&t^+gJ z;0!VY3=BFjxVyUz41D+9=lZwhoU_l_?^c%XJqL@+Coq(cf0*ZPN zP}Gxvq8I{-VhJdUBcP}k0Y$wDDC$E%QC|Xz`VmmnpMaw82q+prK+!+~iUtu-G?;** zAp{hCPe9R70*ZzaOhw_zt-BQvM|S;EsGTT!q@Rn1C%0=~TG8m_wyPsV(HOQDMPr#o z(Ku#NG@e-$O<)#96PZQPBxX@GnOPJ~VHQPGnNc*2fTHOH6wM%@XeI$gvj`}fO+e8c z0*dAmP&AK#qWJ_AEg+z1Apu2;2q;=iK+zHcik1>kw2XkF~+F(&|Mu{T*50<;FNp9D^w4(LNZP`YPq77^>ihg7kML#i%qK(X=XcMz2 z+RQA9wlIsLt<0k6XJ%2fjTuGT2`Jh@K+#SDigpoDw3~pUJp>f(C7|dR0*dw#P_&RxFfTHUJ6x|@8=q3S0w+JY@O+e8d0*dYuP;`%gqWc6CJs_ayApu2? z2q=0?K+zKdik=cs^o)R_=L8hJAfV_a0Y$F}rlM2HtrHax^@}qF=d>s~tbdUGI=Nl@ z(u&?ExBWO?6n$WOQS^~n6#dOCias%mqR-5t=pSZL^o3azePtF!hKIaw7ey9k6eS~| z$Vxzw8v#W&0*c%TD6$h!l$?Mf4+4rj2`KU+pvXZ$kv9QFJ_Ho`5>VtvK#`MxA{PNg zDF`S^NkCC50*X=-P?UyXDtepTdR75(jMh&-??h2%J@|XrwJ)tGgNN0 zW>J)xSri2@i=r&dq9`k~D9Xkxin23{q8!YkC?_+DauHCJn}DJ`1Qg{ZpeP>!MfnLR z3M8N?h=8JC0*XQiC<-N@r~m;)1qmoBL_kqt0*Z zFcqcqu%?@&6gAKOOQFcp>cu(nk|96j{Y zPdQOkIQ|Wrhh6*9iaL1MzMm$FIclLHIx~x+F3h5+E3+u-#w?1Wm_<={W>FN) zEQ)$Cqo^kVMKJ^v#S%~yM?g_80*ZPQP}GNjqP_$a^&_CDKLJJG5l}RMfTDo}6b&Mv zXfOdqLkKAPo`9mE1QZP;plCP&MI#6(8c8q}wfC^DR6rb0^-momMNx?Uu+bCMK+!w`islngw19x3g#;8WBA{q70Yys)C|XKD(J}&xmJ?94f`Fox1Qe|z zplCG#MQaEsT1!CDI)bTajED7!0^+EwMz^t|sH%S3|AU8J`_hVj^00Z&7DXG`UKDL& z7DbzxMbQ>!QM8p=6#dLBincL}qV3G0Xa}<>+R2QfT?7>ECZK2!0Y!TWDEftfqJ0Du z?I)n<00Bh@2`KuNfTG_BC^|$y(P09Lju24vI{`&U2`D;7K+zur6dfm^=mY^pCkZGz zMKBd@@URw8KpgG#&#r$IMUV7*w9_7T?Mo{<=V5C&R}}rl_M+%Kvnaa2EQ&5Ni=s=+ zqUbWSD7wNdimoz?qHD~e=sGisZV*s(lYpXI1QgvSpy&<(MRy4(x<^3KeFBOe5K#1x zfTBkP6g?)O=m`NuPYEb`MnKVX0*YP`Q1p_3qE`eIy(XaO4FN@O38tbyJ*<5d5J#kj zb5<0+*T0&5=V8~rw4%Q~Y;)#|qEBouias-oqJNl0(HCY>^p#l@8J_aaT@+cEMNu+l zQDkKnMQ+R}vJp_^PC${JfTH9C6nPL(*D2kfs7fIJ)bSrp}D7Dc(3MNw{MQIv-nMR^G*%11y^ zegcXD2`CC8peUGtq7VX#LJ24;KtNGJ0*VR|P*j+Jq9Ozo6(yjk7y(7a2`DN-Kv78o zib@esRGNUIG6WQrC76mbdRpBUDMb$bR~BXRG~ekz(a%NYJnh<-R#eH;mSc%1s?7GH zs0y&>isxgbA>dd032D2!t$t;R$F^i(w%%Z3cGm7dGP*jhAqWT0BH6WmuJ}%w4#Zgwv8)9(ImDPMU$CD(G+G;G?iHtO=A{C)0sul3}#U@lUWqa zVirZSnNc){fTFns6wM=`Xg&c&3kWD$NI=md0*V$BP_%@AqNM~BEhC_4IRQm02q;=f zK+!4!idGX)w1$A9wFDHcBcSL90*clXP_%(yDjM%;{YwFHwAVjqoFIw<^gI0@J?+|; zRY0|XQuB%tV50*Zbkpy&_*MTZF}Izm9v?*tSbC7|dS0Y!fhP;{Jtq7wuZ zog|>>6ahu22`D;4K+&HBQ_)6GYlhWI(cc=*CQ)=tlRE2Z*S@r(3!b*pYemsTwiiX0 zm_^ZLW>Iv7SrlDm7Dd;XMbUL;QFMb@6y0PNMYotyben*pI|LNnC7|dY0Y&!-D0)CZ z(L(}?9uZLVn1G@u1Qb0bpy(L^Mb8N+dO<+ZO9F~s5m5A+fTA}96ul*&=p6w??+GaS zKrj{kG_F9Ah<1Qa<5 zC~^@{l!Abwlmrx|BA_TW0YzyDDDo$uC@ld+=?ExFPe4%y0*W#cOhunOt*aFf$DjJS z=(8xAsZMjtC!3L&57qT0-&s1CCzs>>{j>M@I=`phV5KtNGL z0*V?DP}G=!q9z0sH6@^^839Gj2`FkoKv7Eqidqp+)S7^zHUt!f5m3~YfTC~$irNuS z6hS~ydjg6g2`K77Kv746si?A-wU7eh_+9_hv5F`fr%rS04E{Rt@gj)0;8 z1QZPQMS}?_8bUzP_XHFTC7@^+0Y$?JC>lXP(MSS{MiEdnnt-A)1Qd-WplBQc zMdJykqAp(6{tAd=g#I;tS5Y)nztf-KW!Jv6qA6asd0R!%RJIpI)0jokbY@XBgIN^K zWEMrUm_^ZSW>GYUSrpA>7De-zQ8b@`q6GvLEhM055dlSu2`E}ZK+#eHik1;jw48vV z6$BKmB%o*&0Y$3`C|W~6(OLqE))7$j0|7K`8SrqMI7DaoR zMbR(JqG%s8iuMywbbx@Og9H@)N}AWfQxsicdr@?iSrlDk7Dd;YMbQmrQFN186y0JLMYown(H&+{be9=L_XsGu zPe9QF0*W3IQ1pm^qQ?XjJt3gzDFH>#2q=0^K+y{Vie3^>^ooF@*8~*3A)x3j0Y&c! zD0)vo(FX#GJ`zy$HvvVT2&SToUe;O)h{N5X;9L?#(VEm}FT3`o6&Vg&)NWB^amYJ) zQIw2X6j_-?ksGrpvN4MycVW&(-= z2&SShUe>7!h~u69J43#Tq5|qPw=533_N5i&aM(8Q6-7DOUKHhG7Dc(4MNuARQIwZi z6y;+UMfsUUQ6RG@3St&T!OSQMA)qLffT98f6cr?(s1N}~g$XDsLO@Yb0*ZP>jeeG@sIv- zb#{mOPQQVEVyfb>YhPMX4TtUHK2cPY?L|>7W>Hj|SrpY_7DaWLMNvIwQBffTBnOiaHQb)RBOqP6QNnCZMPb!BkYuVa>E(DYEIGI#w4&ebs4hT^)Aq zODl?Y*vcLhMLpPF6!l~lMKR2xD3)0i#W9PbUd*DXH?t_}!z_yWGK->q%qZ$lK+$&u z6b&GtXdnSag9s=ZOhC~P0*byTplB!oMZ*Xv8csmb2m*>m5>PaXfTGa^6pbOEXer# zSrpA;7Dcm}MbR8)Q8brX6wPB6Me~_O(E?^sw2&D^iwG!MOhC~R0*aOrP_&GIqU8h> ztstOiB>_dN2q;=jK+zfkiq;ZPw2pwH9|$N~Pe9QI0*Zblpy($8iZ&8Zw26SC%>)!} zA()D$I;?9I5Jy)1x$9}7XoViOI_%n)REG#J6-Dj!JN>T?yY{6O zS-ovd{}4rP-rv5{w=s(%cVG_F9Ah< z1Qa<5C~^@{l!Abwlmrx|BA_TW0YzyDDDo$uC@ld+=?ExFPe4%y0*W#cP?U*)qRa#o z1rSh_g@B^01QcZ>n2Idk)&UBLJ)%Sri2_i=rTAQ54K9ib9x0Q7E%0D!`1Qf&>&5BA}=+0Yya!C@M-oQ85CF ziW5*&f`Fou1QeAbpr|wfMP&#mDoa37IRc8x6HruvfTD^76jdUis4@XXRR}1mNe@nnMF|(W>M6X8AZ(qC~8hXQ40c!S`tvyih!cl1QfL)peT%hqP7GSg%eQJ zj)0;F0*cxbP!vf(Q3nEwIucOSiGZTc1Qc~4pr|VWMcoJ}iXxbbYI<9fpH_-C>gS?b zqDcRk$gR7#UHj6CV!Um6{uD*AY%hx9m_<=9W>M6eSrqkQ7DauTMNvOyQPiJV6n)1m ziUu&FXdnSag9s=ZOhC~P0*byTplB!oMZ*Xv8csmb2m*>m5>PaXfTGa^6pbOEXeiGZSw1Qcx|plCAz zMOz3c+Dbst&jb{0BbbV2cw46{AdaK@r;am4(Nz6Tf4jF``_hVbd)v027e#y6UKH(R z7Dc}>i=utZqG&&}C_2C_iViZ1qF21BFfH>ajr=MNCF4DgNx$14#zOQgn*)_1Qb0Zpy)XPMK1^_dPzXhD*}pM6HxSqfTFhq z6ul#$=sf{N9|$P=NI=ow1QdNDpy)FJMgI^`^o4+;uLKksKJvyKMHYgo=(@Kx;F41G zvwkkRA&Qb~QptSm+Lu=3?qe%|MHJcDUKAx~7DXP+qR5k36nQa=A_uc5@@5uAKFp%X zmsu3~F{8*yK#_}pq7(!ar6iyz6#+%52`EZKK#@NIMQI5rN=HCZdIE|v5KxqnfTBzU z6lEr$D1d;XECdu~C7>u90Y%vfD9S-VQBH!X$j!&vK>=|b)}On!`IztY)hliFhRw&W zeQ8Dcd~BnxiK6^$FNy-0MNts5C<ESy2q-E_ zKv6LQii#6ZRDyt_k^~f$BA}==0Yzm9C@M=pQ8@yN$`epjfqkkTuW3v9NV_s48k0w>i$F6;8MfH4a$8U(D`fM+X z8Ze8ZhRmX<5wj?2%q)tUFpHw5%%Z3nvnXoLEQ(q%qo^eTMXd-ZYE3{<8v=^L2qP$dU7Xpg95>V8QfTAb@inNVMfvor>z+P#?Mo}_p>liUu-^qCw1}XfQL1h7eHnJpn~S2`CyyK+$jlibfDnG?IX#Q3Mo?CZK2x z0Yzg8C>lpV(Rc!iCJ<0Gk$|E}1QbmsplAvKMNUYoq(bp1QhKgn2KimSO+N}j@kOBj&nrODE(Zt%g3&L zX+^*I*cROvMf=!Z6zyjgMF*Hg(LrWW^eeL{`i)r>9by(mhnYpu5oS^JJ2Q%o5>RxE zfTBMLC^}9+(Fp>IP7+Xbih!ci1QeYipy*Emip~;HbdG?czX&KgPe9QH0*WpYP;`la zqRRvnT_K?8Dgi~;2q?NvFct0bvHq%nI7;i6LVHEgWBu{j8$NdJODnqLW4rrM6y0Te zQFM=46y0YQMGu%o(L-iY^oUs$J!Td~Pnbo~Q)W^0j2T7G2`G9&K+#JAie3>=^qPR8 zHv|;DC7|dX0Y&c#DEdG^(MJM`{wAR469Gk^2`Ku9fTAx16n!P2$ncf7?I^MkP?U^- zA}aw!ZUj@&Eg!4rBc7DWY^MNvU!QB;Uo6cuI`MMaoJ zQBh`5RE!x##R(`XK|oPS0*XozP*j?LqA~;&l_j94905h;2`H*SKv6{kiYgIMRGEOH zDg+c&C7`Gp0Y%jbD5^m~QB4AhY7tOWn}DJ^1XEFdU+YW-#PLACM++21X*H?3zIN?P zD{AO#+x9{fHDY^F)RM6d8AWXfC<-H> zs4W3S;RF=5BcLdPfTH#U6h#tH)PaDajsz5SBA}=<0YzO1DC$Z;Q8xmLq6jGJPC!vK z0YyCsDC$W-Q49e^u>@05eP8Pp1;o)w|LnSfD9WOri{gCk+Lu<;*Vp#XD^b*s?L|?4 zW>NGVvnU$CEQ$s)i=siyqG&L)C>p{nioRzSMMIfUG>m|v;RFl*b z(HH`X#u898j)0=^1QbmmplBiiMUx09noK~^6atE-5>PaafTHOH6wM%@XeI$gvj`}f zO)wSp_O)hxtrRWLzx3!MijL_IKF;yAYhPN?0$*Fjx1wkv+l!(_%%W&9vnX1^EQ*#g zi=t)BqG&m@C|bcRidHgT{`fTAA=C|XZI(FOvFek7piCjyE# z5>T{>fTGO=6m21(Xe$9lKNC>2jew%<1QhKcplBxnMY{+n+D$;w9)hW8p0Bl&0^%s7 zpNr;;qB;88+g@M0_N5ga@U@M3FNzMby(s#XSrq-oEQ$^>i=xBKqUZ>-DEggQ6dh$2 zMaP&$(I3nxI!-{*2?B~v5>RxCfTGg`6rCZU=uZNQ&Js{`j)0=S2q-#FK+y#PiY^jR zbcukX%LEi%A)x3g0Y%pcD7sES(G3EMZW2&*i(o3+=WE@dfH*qpw`Kc9QBnOP$lJbl z?Mo}V?`u2xQ4~F3dr|a|Srk2D7DbPlMbQ&xQS_8q6g^`WMbDW<(FnWG9%4?)qBaC?Jl``kUB2Q8ZCM7bW+zYhPNC!_SuLvncXr zdr{=WEQ)-YMUfw~C~`83A{VnLO2I6OQZkF8RLr6%H8YCR5K!b#Kv7x(iqa8Kl%9a1 z3wiiVOnMF|{W>Hj_ zSripv7DYvwMNu(kQB<5+6qR5WMJ1V0REmJ2(gYNhA)u%%0Y&8qC@N1tQ3V2uDiTms ziGZTY1Qb;vpr|SVMb!u>s!l*r4FZa45>Ql&fTG$26xAW1s4f9T^#~}cPcRh)`&ox5 zAdYnUxhO;w?bAa8KfCs&6*cj*Eiv>3gcxp3*M6VSroNm7DcU@ zMNu1OQ5423irO-xD4c+zb_5hf5Kz>ffTBnOiaHQb)RBOqP6QNnCZMPb0YzO2DC$N) zQ4|41-3cg)CZMPX0YyCtD2gGVD3*YtI0A}#5m3~dU@B_lXFa5VIJ)Xzoi!Fk-uj(> zA3wYHr4@bWXS<(F6b)c|Q8bWQ6b)h)MT40|(GX@)^gXjE8pPaXfTGa^6pbOEXeCPK+y~W zie?f}G>d?u*#s2LA)sh30Y&o&rlNj+R)mNJW?Wz3>zIkPBQ!7PeaGK->B%%W&DvnX1_EQ;1Lqi7ugML!Tww4Q*X z4FnYZNI=m~1Qcx~plA~TMVkpI+Co6lRsxECCZK2=0Y%#hDB3|l(M|%2b`emtn}DJ{ z1QhKhpy(F@iuMsqMGO6`4HOWEzkd2zB#OS%@6q=A*|jgN=r=!GtX&ixVtY|^m{}AZ zVHQQdGmE05%%bQRvncw5Sri>-7DXqRMbSxS6rCcV=rjREX9y_zlYpYL1QeYkpy)3G zip~>Ibb)}Piv$#1BB1Cp0Yz5`D7s2O(KP~!t`ksngMgx&1QgvOpy)OMMRy1&x=Sz> z9rUx#RzMup^>fj$qG*|Zb$!pzu6=1mkNj*qJVeoBwiiWDm_^Z3W>NHvSrk2I7DX?Z zMbS%UQS^#g6uo8^MQ@l<^p=34cLWr@C!pv90Yx7PDEga#qE7@AeI}sj9|DTL5K#1$ zfFi>wZ`)C1A)qK30Yz28 zWkyjt0*cZTP?UjyqKpI-Wg?&`GXX^b1QcZS+jfTG+4 z6y+hHC@%p;`3NY=Pe4&10YyOs6a^DZMcz(pc85~*M*q~&$7#OPpRJ#ZLY#K(ODihm zv{m*IMTOa36cu3>MMarKQ88vwRGe89m0%V{C7DH0DP~brnpqT;VMb9|0*cBJP*k3P zq6!2QRV1LO5&=b(2`H*UKv7i!imDM%RGomL8Uz&8B%r7k0Y$Y5D5^t1QC$Lx>Jd;> zpMatU1QazSpr{eSR8+ue?V^A<&ghpy1w~N>{pz~0)2@AKMa`YIaektx1>1|Fmdv84 z6|*R6%`A%AFpHuvW>M6ZSrmmci=uYSq9}qHMePYFiX@<@0|7-H2`K7BKv8D`inO(+LUjmBy5llr* zoz|Ze5XU9`T+~bydFk(H{hfC0ODh`Ww4HW|qQPu0iiR+YqVJhS(NJblG>lmk4QCcb zBbY_eNM=zqidhtmW=7E%0*b~GP&AH!qVWV2O(39XA^}B{2q>CNK+zNeil!1!G>w3w z=>!zbAfRX_0Y$S2D4I<`(HsJb<`PgekAR~21QabGplBh%R5ZY8eW!ppYU`(;fud-w z9u_(6+Lu%7w zQS>|8i=v~P;`}mqH6>cT_>RE1_4Dk2`IWnK+$aiitZ3lbeDjl zdju5SC!pv7!Blj}X&tJ7IDGYgJakwT{jE-Od+4-lUs};qr)^nUQS^-MMbUF+QS^dY z6uo2?MX#7e(Q9T=^oCg!y=4|f@0dl=du9}UAfV_Y0Y!fkQ1pp_qR#{r{X;;}7XpgD z5>RBg~(MK%J8+zBYM6Ht_#fFch9iaZG@@*<$fK|ql=!Bq6v zX+5HVI7;g0q9>xLsQ!-Tg%%Uhgvna~IjG~ML6lEfyC^G>?0R$9fA)qKL0Y%veD9TPiQ4Ru%auQIKi-4ls z1Qg{VpeQc^MfnIQ%1=O1AOS@|1QZ1mP!vKyQ78dL1qh}hKbO@fgHp6de-m@M%y;@D z6dt#NF1z-n6%}>af-{MtVr(ypiZhF%63n8gB(o?g#Vm?SGmD}!%%Z3)vnVRZEQ-oA zqo@J_MHLAsszg9hWde$-5KvT=fTC&y6jdjns0IN=H3=xHML!BA7){duCA-$t;RGFr%m=0Y#k%DC$f=Q5OP= zx)M;-jew#k0*bm5P!vr-Q4a!&dJ<3+LqJh10Yz~H6!jvYs5b#ceF!M(OF&US0*d+* zQ1l%EMFR+?q82XeTm{6@Pk-*Zr6}5|zr77~*|jgN=zEuKS5{FplGYnSrm<77DZ#3MbS8B6pbgKXaWI66A37qL_pDG0*a;(P&Ac*qG<#a zO(&pe1_4Dg2`HLHK+$XhisledG?##)c?1;AC!lBn0YwW5C|X27(P9FMmJm!ugI(4e z3W(#L8r_D7qUU;8>auHJhM$qlEt^NaoEF2mP5sK&a9-5loS)Q>DU&-hst>n0oMqK7 z;ryK8-iDFVxx&{l{GE@ThLOP;n$j==oPAOoMt0{Of5XV_w5B(V{Lbnb4I{)kDYIb| za-Pd#7{#3Fvl~V!XLwG-DCb<2+b}9QpXN1;YR-azhEdDeFW4~ZIe!T?j7CmdA;W0q ztXae`S~;f_GmN&*^Cb+Uy)$EJ!|3FUC~FwqoNLM(Mi1xniiQ#AEL_Df`Z~X>W*7sU z`)e4+5U0JiVGMWHu4@>hozv`_#;?xx zv4(NP`MQ^3{NXIF{z;5e&cXc+^SxV&epJz#M)oU3+$ z#WiQX+6NZb^@VCDSX?=lsJ&oubzP=*gT=LRh1w4mm;Tr6vs+yHpCiw0ap`|gI={uG z|3Tmoi%b8Du7xZv{ZDchv$*uXsaVS5(*G!4Ig3mGt7erfF8$9^RkOJCzbjPB;`+Ex z?GuYj|H~eYEH3>|Gc>cf^xv)D%Hq<0IeJ@*OaJZG?JX|-*AsWLxb)vI+s)$Ae?e#u zi%b6vk8u{4{wwAxgvh{dJ8H^`N87S|G~gd7MK3S z_ZEvwe`I&N#ic)Ux!dB>ADY`|ap_Mz{c3UPkF6ZBxb)`^{;;_8FOE-HT>3YEXDu%M ztD6fJm;TxN6^l#%@breorGNT$$KujIzIb49>Gz*cEH3>9;)TVfUje?cxb(O14;Ghx z4*qO0QtVR?8n@-#WiE@6)>6;r=y=bgi{T$4Ilr0R zog=O;y!@TvUrKsK&K~o+dnv1$8z@Z zr)ON~XZUxMzJ#-{yErVf;jbQj@t3}xoc8#QmWIEZ`f~M6KS?g44u-$}xs=ZLzRhY! z#^-;&%|Vh==9aJDypUEZN2&{{Zf1AquD=hy9GKQp-`#oq;N%JY(^?w1JC_}~aapy7 zHpitk?xl@%edV(J|4>I_)YdWaTh~w4Pu;Z*lJ!^r-!R#C>Vf^U+Bfs_qPX8i3bso6~%sbsveV5Re z9!NIt^qG#k|xGc6Sb$Iro_&n_+@_PSAgBIjo);cBn5||FI>rx@S18 zj_5x&tJU4GI4wDRQg~T?()%<{d8k= z(N8^v4PD$Vmg*@i>WDpynuFETM)DLEFE4Ww-95YwYjQ5Z%gfu#;Z;nX%QMY4=kikL zN^(688Exj(ddo$sQD3BwTx9&Ii5KZB7b)lRQybY5Z->)c-9CNIuJ|MB?o1(Hn_NlC zLP>5y*|eq7s^`@pOWCyCu3TxI7MFWD|5+8%>KlDiN|*;YZ_acPpa4C=c4#|*Wo zJ2*7{9!fiQsKrR;Kc#}dVWd+h82SXmNY8oHJ_|DR6?gZEzfN_#)H6@AWcs;XJ)#Xu z{4sUJP~S<7WJbs$z5b>C*o;!Wj0}tP(JS#|Nj(lx8%L(+Mky4_YIQf-pV@=5J1 zi#n+D>Z=b53XTa6?hxA}I5s9CI3_GMA~LK;OmtjiL|kP1;E0%hJ>sHuh=^?8D<(2F z$!Yrh>fFVHd&G2(>Kxa(ccc;ADLN`LIJ{eA-{7Eb(GlU@f@3>{$3zClM0Ssi4UY|u zED#nO*Q&=4I1RSfJN-90ie zGQ3^qz|fGOf`R(vAa(LLCk1!z9?`8=`^ey^@Q6;GyZ`@wGh+M2CcP&*b_y;Z)4o^d z?$H&aVke_`69Io z|8MN3-r;eP`rcCCjpBE7Y_E1bVj@Bc1x08JVeKP3g!k$e7Z%sAM`UbJCrwQ4ulAk0 z$EiVmS7=zVa+tcE5f!7OqN2O2rt~4Ev%YLI8R~VHEuN>fpv7iO@vjaxi@UX>#pbf6 z4YH-kVpA`%Y&Q2`TMBozky>5xYgYAc#gfYAr59gY7QLt*KL)9@6|kjpx74(y$Q-|k zI$rvJ>A1Q%wiJPKLsEof&Y$EqaofIKQ-=lzhZG97_6o|TzNY>GYJ)7cR2G{@N?U4m zlReaz^xv=YrTUs*YIgZjWqFV_~oTH`FX)cTm!!AV)npsq>ZNy*%;u|c*} z`k1;mzN}H>MzD@2aY_9lys_$d99|F{k&6woIe#_#&xJ*BF z6+Si87B%%gu&F6^R-1>_E5O~_D^BeQb(tRSrDc!&TlakY{q3&4VYnp=PWZq0`#PWO zo%rmY%G?ndzlq9#-X_yGF@+g36K%QldGwBxJ!T8kLH47&y0i4?u6JZ9eW#VnEB8o> zz^vM*dJMUz2@VdeW&+^bRAB}8SQ(t`ukBOA|3tRjB+n1X? z;no#Q|8L%wl!4~s``a7wKN@hkr_2;wAS7?Lcs|xXS{q-%|LOW~T$x3ScWLqe?V01T z1|&X(W!Lv*XmFN{wtyV!iKCzS#9@A^dXMUz_^;Og_KM`8WlN#H)?izftmea=hdFmZ zvN9=^s{iQ$|Now1)dTPU_NQ1|K!Sm9S^c|=vMAsBSr|j#KC}PV-<;LAivRJOvrS#_ zfAOv2zrMi#hGN3^p?~jt&%byiX0ipS$0XmuzrCk;)bN1(x9&Nc+N!#~+v2wl=2eBo zX33H)n|d+cpmNo)Dk0Sjy@nPGsTS7GJX)ks!qLJN6OI-sCg&_vj8>kFLkgLvRjw%K z2~}tATq`=dN2pP|e6z5Mbs7~gFS`<(6i&FlqNIX}*IOXrdMhTmNV$Op*q}(lxr)c% zre57+J9q3J**-wMbd0~cigLR`t8gjm2w!I9gs&r1-I)0E7guKs3sYMcED&a1La4ej zHmJg-m6uDaka!8|9#Cg%-zzGrpLt1g-a=e)c?m@mZh*Q&6D~R7N(ylul@jj^br;AP z)lD|vD4VJ~FaAVz$I5nv6D~~M92oWEe=?WmZrMQBB?O5JeTLJLUp zR_lN34MwHNcD*_p>Rnm)j*(%J-P?B#?;h4Ix_d|S3sk#AUA=l6lVqRBO)HdmYt{ZY z&z|t*0WBo)t1F)Hm4qt8MuRZ@#-dTT*sAJnVvKql(XdxL^*^I#<>q1KD>aC}JhjW^ zi&wPeSfy_+(a<+FApZaU6Ti^J8(2Yv0a5MV_$xqOf-O_Ben?i1-@1!_6vdx4L@q+1 zmRnLG;Wp`qZ~U3cC*HV97%3>HC7|KTLyIL`RA{109Kk3w5vuws zM0KHxo!LS-F%e>D6?R#oKlY;fBFybL62H6jvy|-e_&wL5SNDj}kdXLus;4o1!;_eoJ0+wi5x1ct~TM0V#kD5kUN9j zQas@->JFECHSr0JeO5T}_Lv^xpR5xJgeEbNWZxH2HzW}zPlxK>GH;(gSznM^<(fm4 z)%e7IR8K^5Qo)3~P~8!nJy8NXnSGqFUyG^xFFHZ50wde<%|buLNK)Hy!HT4L7pkj` zKcemlPD{Lq_?r~}@KrxEkn^*l+8^;n@8tOJLFTuf$_ZPmJs_8ucnjFa>K>BQ685Fq z1?Dv*+E7m}>Rj;`9)FVBx3ZP`)*#0cz7XZk++IDq>ZiFF^Ii!x7x})Js3A0wLxR9W z1?pR_y8PHq(J^re-{shKTG;>Q&(-9|a!Gz#6Hh8ZQ^I$9^{9;h3iTdusD5lz+x&Xf zJ#HRJ!Yq+hXrimoL|E+gP<4mIZ>(Mv#INktQ1uuwFEt68L?h}Z$o(IxUdEVbRL=o& zBw;s&Dy?$9B;OT6WeX)IaVM%{RqHeks93ysfc{xvP-uYuX<$gP0)+x{$3%9E43CY> z6A%~`(W6)C2(?!t`vyi8ET}?Ur(RL*)Y_q2ba-5#`cYzOwd>pKpw8K$NAJRcu{{FY zhZa#KJSL)3Y4x+k-o*l=f}+$RAg*y zc*n@VZjs$P#&s$kqLTTVCs4~$lYUl=>m1!ZFjoCoPpz@4wGWRAPngZSLcMM2{0J&L-d&qnw zC45hff8d0LefvUySFedLUSXqOZq=>QFyR|{D6dr$Uw0{yiLV($6Q6nUov`y0UY#bq>`ZutndE_#_;5&keaOB}e07+x56zdDM%9WH zO9bTB51sNcQ2~{s+C{c+uU?ur;wSL&k0ySyp66dbw)8I-9O}K|h#Iat+?uw6-J{R@>;Y7R*_n|b=`B(pw!d%`bU5`O`sFUD%b|H@w~!D{#>ne^p5|HG_)UzOxw{SRM_Red$;ms|1o zirzmi_4Vmr<#W)VLa4}~Rz27M53~M&0tbEifBxM;_BbPZ`+xZ|UOk-t(;JE;uMgGh z#w1gyeBV-66QKThsyjQsti@!lBx^lcTglo<);L-97p=EfpY(`d_2)44tbS)3zc$lr zYW=Adb3US1^*clTSHLGzciJYk>htfF^{A|W$$CrHXR`h+tGgnhx0@>KVp%uHx?5KD zOTGB>Ib`*hHM^|EWUVA?Jz3kxx>&F3_G@v;6eIoEOr~~_7NS>m6XI9(Yf~ec`pt0` zy(&(*rR&F`K3@@8)#t6^=L)jw`&XadSk?$xyU5y8*1@t4mvyqNn`Pavf9JHGeRXwov zS}LWvR+n|Cy3cf*#QEo+0ZA1zn&2vaBgPm~$3cTXZt#j7*%$$Fe^}z^pek*IxXmc(pYus3K{$AFd-cHrJV(|uGtBwAtp2mjIftxm=9+U?S(nc@=Z&&HQlE&__wRdILzb9xX<2(O zGv{Hl?p|Tezss6zwK@CBT5YX4HqL{athJDeKz%=DbbT7wV&<+QUDx7I|XM6=fap%$&!_ zdfakBpEVa}&z^;Ca#gg$>7S?j46IC^d^>rC~TRy{A1 z^@{ocq@EwjnpJ(uRnNh)c2XaA)pIXdH>l6O>Uo!}Z`221^{if!$FC*SCt>wmRn{Q^ z<~%{xLs`xFPg(P;PnzrV7nilNthMxNGmMrpchIZDFuKSZEq#EjV`QBv>oQq?l68-) zM`b-P>m6BN%KAmG>UvYD4}R)3P}WMawvshg)^V~fm34=#r)0e^>lay5sn1jD%dH`6 zLs?^G9V_cnS$D{KTGj`$8tOBN`f}398YF9FSzE~(E9+QU7t6X?)?3UuWEm_mbHVdU1W`wwU4aotnu5cmsjy?23Z4SRWEDed$6n}WGy4Bdf5ZeC>Mv(q-jS@EHB>NUp&=$A2!}^rzb764gyKf+Ex>up-s(){`P*DFq4?Ek?*z1&sLQ0Dsyy_tGB`OQJyjq!&p>i_lmtmgQi&Zke) zhg|AUa`oqbI$wx7&wspL{a%%W-jDi_U;R;U35;^;k3MXvZBhT(gZkX3I=&djRTjbK0yA>1 z95`*Unv-7MXLWgcKk3`&tNw6#KdIw-n-KL!9~PFe7_HU!0}lE${b!e~obOW&i=m%8 zIB>orD(K@Js@1d@#TeA8uU8*_RezG+KDQQ$_g@Ni8n;iq+|ibMs3ra|L|vYKF5|#; z>6OQdK5e%;-((fjsN?!MNMD|x`lGLt$A&s;)KZ=!^$|I6dFmUc;<(*G|~q)G|kX!wX!Ou9ct?&9mi$}aE_@&>mH}1)1n^$mu9Tr zVsDV5=lxiw);`T-@9gQbh$x5s=Sjwj=XkYNsFFus|GCZ+_TQ4Y3Dx# z`#N$rji`TgN0ZfGpWJviXz1%&6~Y?5JA3tI-cILRG!kcsw~HA~K(E0EIXP0^8i_k3u6W8t`!huS{vShMA`M*j1!f43&QaJ%g3Mn6ka z=%(-a-`71k{_ZDxqpiUUoXLkha(lI_?ZPQR4R6IvK0oTWyKSHJ%B)ROTCXV^YIzo#qSmv}->L?^Y}~SX_WG5>{2EkFIU-x=*=65{oc+)^_%`bDdwoL!mfta0l>UVuU z+F12rYUX_R-}h=$u1Mw_OZtR6pa1jc@NU0n8`iV9|BVylT9v*ZE@MLwAq+GS7U0z(S*tiH0wm5#3tKDsk<&BQ~CT9&W8q(P&? zD+V2FSo*hqPhY=E^>F9LOs!)Z|Ne81JnnHXu5_EWepuCfC06HM@wv?DRufilywH$QuRv)IM3_?eVM|JG6TdeIxlVsZZ?svG}d~ zC(@p{vt-G}G`HK%`k`Rj&PDsaDO+L0nxeHzTpjvlN5KiriWciIxLBzu0? zYw?gVk1G{FKjy^jw6zOYT778s%}3WSEI+aB=)kde3RVk>%98PrSIkcL_T`Fx+I^`{ z-P~yxU3yl#S&DKWul3n*`fSivpWzK3P0KL;x97``Hhq_B_M7W&*NPt>TIN|;=-<=d zy&p5V-T0K_cXVI9Vae3m&tkLQYFIs;XMypR+qJzq=fkkpryVKgZf}(J+U5RRIxq44 z$-n>Yey27M3#xBj(O^Q@+0lbaJ;>RjW5(O|8{Jn|d>1v>?bD&q3T1b7X+0xq&%xbc z)O8;*jql^ z{AOA8GmGCI^o@xa=C!Kz=082VoyxI!*w_W-qaE*it>2y@%ZCvSR?PMBd{pQ1$8@V- z?_GN8cdv)EQU3eJ3-d0nR+i!X0l`YG<0THC&685>yFclGTrtG-MgKlD`W z=K(uLd>0$FAYabEWa&$bU)g>6kDv%LzgliodO?B4fJo9zym zy>w-rpxk4!=U@AKy(%gC8Lo&U8;-yFkbPy}-u{hSyG`z&>!5x1yTQxb`Tmh-)Ca32 zYE9-s`D>pWdBK(D^}v$Lj1QYC=KrzN53iH8>YJS1NceSDLNEmVMu9*3|TcR=U^QbmPVLRB=&t+W0n4@&3=0m7FhM{@Oa~ z%8sdZ8(m%bu=dMVIdiW3`Hnr)p@Q`yPv=a<;P_R!7}>nX}Hj-0iOQ&oboc#tt7_*6vVa%;I_{ zsw7W$|4iW>T}O-_wsg(>E+ zH{!`Jy^rk-*wbj)_^lllwq5z^)9rFTy)sUGIkW%IrAK6Ha=!9G`vlv)a&GVH-+iCu z%Ee+4e?))2KBG?hCVjqsdHm#Ox4%w5THoeu$A4naY+SPHQ1ag{4?TDH*}B0ED)oO< z^LT_`)uF!QcTKwZVEdtN*+1v(Q~qe4Lhm+ho>=bq*bjGe8t;}g9bYq5mM-7-*;)0? zyN7F!`ak))yJ)R)_ZwBKdMUQ2SB6O&i{C$UF5TTfwr0MzeBgs)u>k{*94I>077^k< zcx;u0<+H_({65{pltF8%=X^HsUHf$NcfZ_lc(u=}ZjCeL{JgzeWVy$^D;+uORiIk4sV?`u6Pzw3|LOD4`O{KXg|c+`X(pT+;z z$*l^W$T2(Tl;Xu+w4PL}K=iB~pITg-^h3kAUQhar-ZZL+=aWlwE$>6}G_tlCWbv+- zGOpQ=dDDhJ-S=Hp@5ruM_D-C?#WCyttA&?GeaZRQ<3Pm<_lD(gzwRp2WYhfuIXpLp zzWY?FTOGe;5p7C^--tL{IOFqIx7ye3v?_4!uodIa4Bs&D$?X-r`ajNAeSe8x-j*v@ zG_Oy}AJe?pvvlY2g=g!8)jJ#Ua?bcwb)&QW9Jsaks9)3he;(<%`C1^UALCmL$-EY*0E)cVdY;9|0imnPyM1byH7t*s@h*y zQvUt2ZniojCq4DO)N|_FS54+OIQZ!CuI?}U_i%`p8H>-@o@WYl@y=VSSGF=)PNa#={iNgM!fwHX-`t*W z|FCCzP>qB4bIj=SLpPr;zyFe{>5k5g&mUY+rSz_lVNI%ToR!h{>dYJWyqXl= z+1-i3r8-_{-8Mz)-flMk-+meOA=>*>)0D5*_F39+WXQScx3|UaSX*=W&_ZM8Zg~|t z@^*@U9yOhqC-a6oEiyN6l&e+k^&cAtG|U)vsYUkOjS9Reo#M|4H|J!1+Trc1+s!+# zs8F_eNcI8mN1WK6fA_h=jk8SNwy@q`orbt?`Q<|F{Z$or3}11jN>u7uDJnnQ+cId{ zu6#|7ox4}G*Dt@fu{s}|>+oc2b;tfuOiL+y24Q z_7RbH^A;)mG<)Ge7jxyy*)`X(v-uiabvX~ekkO^R1vzJF5BvoG`aJ+Wb4gNa>V8)=Sq z|B&fzvpN0O70eOy%c9;f^K*=9?v=`W{F+{svv1wBuV97W;u`H5xMAt@qAwpzikM%| zvH5zdQf|vDoT}u0wBQrB-BINRPYNB9*T`9OS+;Yv+jZLSecQWVzAD#lR7hJq*gkkr zeQUL~hm%cz)-h!Br!QeWo~P+OY<)z&;K?}~joR3^bXo5zw|6&elyPm*-2=-0x!_Gq zks}j_92q{VZ$poXKaHEyXZ`04aqau}nANIu-s=r7wYBVeP&dWO2Km1RO)U0Pm)UQ| z4eB$X;n~UeraoNQ{zBVZg=Xw|nQvE*4+FgGj~{l|e@~a8Hz#*(lD^@LTt988I5pGm z*EzS8X;iz#zJ?oz4f)w)!y)^NHpiEAOtH1e=gtj_c;|0bGOEjyyX#Mexee(YwX$~0 z+GE_OA3N>yazNLgnm#+#u0q!43tCO=*lyvKbB)(r{8Ikb#b=fuZ{8Sk;q-x8AGd^l z$=&GFy7Ox-%lFUOSi9${Q%`1g=^s8~d&lz=yXUh`j0l>3`P|j~<=#Krk|xvNwk!RQ zoO-l6-P9)kA9-H_9!2r=J;%;wXOC=>4Y`5I1!O}mj(`v#2MHvEB;cz`Gx1QiewL{Y>O44fn^~ z9^LMf?6l`!U7G)=7`x*0AHNx3J=ATxpMRgpO}=_>_TGZa!Q*Jl)eplG`cMC>7w{6$2W_$BVv%ETaKmWk4 zsoc=-&aLTqZAICrqwhViIx+wBCoi6B_om;BS6?!W{dM9g+qU;#y8TQKd~|Vg@#?wa zs|NQuGyXL6*>vvAbTdO?1Pi+mZ zedAiiyd^y!$sG9nB<{$b&7ZgRo;9lK)x(Q_smc7rTwC{i>NG>nxJ7?|(6jQhgU-&O z&)>gn$+Y&vzwTZWU!0%$bz6JTqsJEQQC^K1`PQ0usl8Xd7VyOC^z8z3X>eA?)Z$A?9WzGQIA!}sn?^rpcxb~-w@9)dIdiJfZiOEm>W8(GARfW?}nbR{K`0JBA>E&-ePMC1ENx-X*jj8nM(s9Z+ z>wgu0ymrwvCGqi*?VA2Rf5FDyI~J9E-fF|hcTTRD^xn*pfQ;aYC0F~ul+x|Y$nUrG zsw$j0BRXNqki1hdEt`hE^x@3>dBxp-TV?lr{*Tj@UEbWj@8rNsqw_8g-!r`Y zlaC7bbt@dXzR#zI=~XrI6R*7O?e*Hl?~B7$U)^3haC^l|n*v&zYhzR7FF&3BT++hQ zy3c!!?3~-sI9+Ep- zUim2DQg+{0eUE-;>^Z%|>d}>}zI!}#OL51CFHMgN>eG79oNw|M^j&p+OY(_#noqiQ zW&YL^vwqk==33#Ay-A)+BKz&?AD;2tnM;qKoqMLJbl|a9Umktzw{@S*-FR~QC*|_= zzP;NN?mPU5m#MILNBNeh?23TuxK|JNsd)FTgwwN!1$sPqc?o8u(q4Cl1-R zyfo_6;ct($u-&S@eEW3y7mJ#GW)dg*b^891&K=G*|7lFbnw-7wT^-w}HuKMZqq5fg z6n63Yv^URQxZ$^}=+P%jU9oR-7hOd0X)g`l*mwhMk; zF<{KPunz{LKVRN|WQ5PMo{y!x{qdNa2@jMkh}*OElJJG;;4crK^m%9W$-PbHl{5>P zlGd!%rERgr>o0!Qj^Cm$Dqiqi+Ano*m2Zo zuP;tM{qWT$-~Af=_l_6WWc_A0?f7}a-XFSeisa6A*!u9MtCJ5tBYd}ct?}Tj=KgPN zpZxVh)7P&)9sm2{ZC55w{ISo}!E?ITL|iGKo-(XO-K}GbJleF2*(_~8^-Iiw-1`>& z_D-eO{4d{qMcGt#ZRhZ(AKFwou;NzLzBkYBTefM+R{xT=h34HGFJD{u!K%}B``dl7 z&G3BF;nrK`uexow&!4e=*(Teyhw7$$@r&)R`wWko`;AOK9a+}l)aPGTJ+(Oa(1(_- z{nreb;d!=IC)&?Yk8hp7Y3$A(MZ(+Bq`p z)_RZEtFoT?%-MAGx%jr{W)83ER@pPT;?V)~7F|jc*G!#S*2Zs1`&D}qsy-YU{^YXB zC2Ko)rFH$rocQ+m)se4P#(r}BlbROQAFqF+YWvA2I)1dK?W;9^@3&Z;KC`YCd|}x; zBcbhEZ|^$3CNSXqi=STlVZ+JYlb7$}u2kf|_}OD&mg1MM)%@z8Iy18B@d=%8pFXhI z*^b+v{pMQ%{f};O{L-k2Ver(8*EUuD`n2Wfu*2S7Z}z$QlW^P z-s(JG+BZLO_pGO+jYp0~ZfzQ~`|%wfe{48)v-2kp|M}+dJ_lyCuFl^#B00bO4bK+s z{V#3ZzjJ&r4$nS9X?4s4Q%i+qhc{hZ^7-((RogxtIbG=R*r3y=AN=ExhdFRSz?cPn zu0QwY_CLS-kDLby&`(<5rmggPWfhWW2Gj#)BjI#A(JekI4 zt?Uwb<8BlM-ZYysK{~)PkIj@Br1i+?tHd}yH!vHSVDMlc7n<1TK!V951weyAqStVN z^F&QtPEF%|lTnt&;sy~*05a0&A$XO9^C-h@zQjq3keiy}CdPUZLQI-7Kt#+eYdvx0cku^V>Mw{;TW%^Dof&PyYYJJ-*rk z#;^Zs3w&DR`tW23`>ch%bI)$%aSh%AcYF1{pd=$ZrJ#GOd%U7w&!9o$|F`~u!OdI$ zv;TwWvKf07pWR&lZ{Ql0d%U54_Y3?qeE&&TigR<6|J2g1Z> zzLsy$^6ivkrDA%KS^it^n~bHGPhwr2b9>R_-@jhsdY?pl+vH!qIr2Y#QG_ki=nnOZ zF7-2EwM=*Yv+q!p5oTSVUEfJZIJ#&Y$V>Fk!v7UrOVCgooj=i$Pw1Dr_u#k`0Ce7j z>k68kI*}U=uRAyR-2Wh6T%zp(Z7#^Gi67~O*OVLZ`yKpB0n;yCRtW%lnQ%q;z@N4O z`laLg1K|F?!GOl99Fj}&bh%?t*4v=SjRrsZK}7x1i_-z1a=eD{f}=<3M$&MEU!awB zy0#d|d%ZXDB>h84m)7yd)ejA_Z)`8E;N_) zOYiUalJOIV=r1|o?FH9+4z2F}o#Cgc6?5O3%zfPo@|Ce|b^zk}97m-@#=mAQvw7Ssb z<=4Hn7Pf!gA~dzk11-FjG|1(`@2@lT5C;WhjO)h5o07R7xbLZR?R(U|9yIg4tAd}g zW}#82wF^Q`hH>4@kcU^)`F+2lE}&}7EMWbst_qC^E7dHJJZctsaJBd)hf{eZ3!hdFZIxAe@T%Y=)XWnMwRVG{Ce?84s^E1Lu>BXf2Rv)- zp4M9Y@&~m7jb}|VXRS#U7MDIT=*Xa;nVj<8)heI4brH%sXh@|M;A)j)Ze3J-?LO+Skda?z=;1S!Q_SO5z~%=qay`bWws<6iQ;uFR zv^rX6^#bJG_OGXvg=Ga#HDuT_=GC=;rQ4s#{eAjFLzUZq-nt!D)bIPv1*f(7LZY+B0?9lFn)k#C$JZXTIwwF2{`a@5v)-1w~hK0fpv zChvoDq`&F)lroaeDW-if7ix3U${x*FaoyW%{!T8c>Pp3&fjx4odj%KNMaRS6%;A5T z{|c(*%_xif3gtvGB!|VTGQ!}kVeu6nH$LaXa%(wres)ztVO?lmZuR5h*sEUYT~X%O zikAnaiGP%)J(hf+Zcb>>AW)hzdd#Ua&Dk)u@wAQ8LZ+{%Gs8cuRbM^IPrp`qvGR81 zPn9KqJ$b9-uP6RqUdctBKapD<;?390uZ7#j&boL}paWx1?a9#2k%eO)tBgB-L@8 zi&#(>o4g8%YkA`YFjfB9gRUAv7NE2e>F8B1HefUQPFU1i22Mn|l4kH_TVaKeBo(*a<&Z z;HScTHBib_Dwe|Bi^qx&EQvw zD>vQnd|=ZJuF<9&=CVyU48EIgSpE35n{Mzvxz(pJqI3D}H7PvGa!R%AeYkS%xZLV5 z8GIXqe`!joHUS>^&~+10zg&~zd6|`V)TCH1u+lR%DcnUFaGGh{ zyLGP{GEQ8;7Z`>gM1&|E^!=dl@#WX;dFB~hO!;-&_m-LE*S)JOXBN-!&*gaO@}P{W zO5-1;84K$;v0Gha@;mT0^BJ$6KD_7ULCK$1a(|R2&#B|W)8P?sGh8rly*w!OOr`Kg zY3jT>uC>%7t*&LVl0mwOJvb$NP#yH3Se;gw&xK(1q4_J;+QqbL-f^aq;toM})i|2| zg=i8M??5y$pyy%nGCMTQA_-UazH<&EL7=x~+;d_ddgi&B@NK9^kOnHnl3Pg}M zBT9;ATr^jEevW18q^wOhMB%uJ;{9_q$>OJ`v}(aIq;|G=rgBN0NBq-Bqq~>aMJi`1 z#fhAgt35KuGOg?%v>Jp~&CqH-YqevJWqQAV&?+CToFr=!$$D~*Wma1498uS#2e8eF zC$KY)TV`bZ1CE{1rUh}F%sB@hw~V+ii*HSD3H?{Sj?XHui{j2yu9(cV=yJTri0G`L z9a%e{6U_Uct4YzURd1>AtQGTD%pP?0L&u6KH0r9itG;jsV;<7Odbx@(s0-!zFpPFG z_6;1T(0Hv!L~d%;N1Vn@jq&168uM}8U;*yqbGR!z&+*}8k7cYjf!#~lJ&o@1k>@D( z(cIB}r1tgsJAb<>KGLX%SJKeRg1U&j-^$+IHL@&v1oke#jdw|KV+6n*M;!z(+W7ejJYtei3%9YuwJZc(_Ra zzbVo`s~V#N+JiTqW!}WG56?2c4g%&=1(^E+>Fskt@YoOq(DG=2dIk(5kU{zwO+|Xr zXv__q%0M1R@P4sil0LRm=3#FNMO@D~zsELSTx7;`%m4=+eWdlc8Mojj4#jKO9udA7 z1l>i@eFTleV0*N5^rf-|{qTtQ9Yqu;iQ+rlJeFcx?qOJoqN#`H0H|XUM5=VccAPia zaZncM0D`ZFZVKTB(;-NgOwF*7H=1nds)y-mY{E^Z-hj)dPkizJ$EK%n(y*BP@P4q> z^fk8oHd8Z5@iZ-r#7V#;;_hYo0hHdROVH29^af}grc>yFujyz6PUj{A?CNKF4p@KF zY4kL}6smAspy_3tCxT210S`7U#hD?*6xE#LnwapKKG)RL1Q5m4wgtB5rl-Is%(M~* zh;Y+cz#~lGpd4u$j@}G49l|IKGqu2R^^mD3jN=ZQqR{IjrY#uWk4(>^*GEm)VS$fL zT_F9KdNULFa>iUm0Ug5DP7PoVO7QGOAla6y!_VbE$(4u!lLQLck4{VK{m zVV8@d+#ftIiE@As-u4$|6Nai*l$SxmWl`P)T(&{J3D!Lg@@i{qh1zo`M4!I{r^HGQV3z~a1mnYJ6XfE4~IAr_Fz2Hj^`O9>|9`7&bL+k{9c^Hg5(O({g zA)e$f+tJO*{_)Uj)~*$@j0WiyvK{u!sF3k* zfn2u=xf}zKcR+r*1$^Rw9Dr<4wY(USue4f@M#lzM%WuM-L#pNZ=)=%z`3962RxRIx zV-ByDQ=#<()#fX}jq~O?^BWlChp4a@79LN98bBscArLeZsn8s4CQ*UDI$$ytW&$#& zJqj;IpchnF2&2rSLOTq@d@6*%!yci+N{qn*Dm)AGFQmeG*mDsToUmGX2?~AT3CpSQ z3bb88g>&fHN-DgDPOV}z=;X8^fJ}nvrc>c%^obt2n7_vu@>FOGmlvo|fhkVkLSlXr zA`Dcxh7L+pmu&u}p;m41}2q@1S5|1<+Wj@CrJJuWske zF&GI?Dh$Fn*%=Mg@S;K;XuPRl$ME`4A<2YzONE!3AyC!D|I7tR!l*<1CrrXd1(d z7f|;&j}{V-!QkZPp6|fBtd$tOhph9U+IZ_?jN1fj92B2ueG)oOveNGzOt!93;P%#0 zPiPnj+tcmL2D~C%FM&CoaKE!gHD|2+l<=&$orf| zwbtOf6y9XOukd^aB;4GOa^mB^5(PUaQJ4M5AP4G!ep^r{b^%268@_&?kc_HYho%Xf z!P~99W z1(SGQFmm=2Ft<5Q3f@5gUgGTdpE%B(pi>AKX5QRFl2)K~ApLrT*(v!`>%ddgvbAK1 z2Zpl==4O&yiDD4R;T)g9DCV}3597;OE;dIsQ4)!bL}bt@U9w$9$^I0^&D>3D!blAU z&fW}j%$%tKMCbz*QY6_AV-&av;m@2V1rc#zQ!6UjlKmiw1jho&)(S-SZxN5pMH&NG zju_-havx%F1Qs>-(im`95Y2rgJFzCBE|N3~#bDAam{<|l!IEt)iuT@c3iD7mJ&T$F zFub9j110$#5C@hb?wbc`Vp=;;86nw;H*p*%*}fuS>bz>- z8In91jlJ``=X2(VHL>%f&~TAtCs`!nNy)YxMf+GRo91N=^?po}cLNu=TmkM0jX?^6 zv3a>NfS{F zCcT1*6>)t-lAlG<9)VDA-lMkU$zSJ@bHAwpc-RIUDkbRy5C{5_E50WA?EsHJyavXZ z-U=+S0*OK75(WnaJo6M4CIykXjSdQP z=2eokAO)~PI?$gp?m<~10K=Ts zF-%X|xWkB?|{C{?zZlIGSH!iiI$o zUkBV@Lej!NL^>6@1_1lV#JH#e)teeOJVjHhhkVxL#Op&~>?gh@r&D=s! zgKr^uZ-QbWK@@yDDzXf9?Tv|JCnaPbzyfdQ?9GX=vkvg&>_f5pFn7@b_^|p<>=Dh$ zIsjXWmK1(dbby7k?;(dz(*ZJP{{cHHb5|W;;_MYfk*)*Kvn|;Cm@{+$)|oFT)OFJV zSZ8{YV%>EBX3+-`0A%U_e2?5f(lkp4U_fZvn6q^NSw}FpQ>0jQ96ziC+Ht_LitIO72f#Yfw9F0B0kF;h>e5gh z0P7qf)raW-SZ6U@(foi8P_2`%NZIIkAXBMOv(AHL*D}RIb|dRNq{!)5pzJS^BTP_& zXYi@o*ksrZ;+DEnk{7EH*0-J$v3U4I9QXSBQ zv%eDsz%m`sn6ob=igFzg!r7M*V7U$m=IrYTutEm}arVswSg8X7IeQS9Yn2WN;OvKp zVzmyy5#dt;Jf#Et;E)uK*64snoV}C)YjuDxXCFm?bvnSo*{2X-y$Hv64F8S~?Iso2sn@0Ls9RP1B#Hq`?Ne94N=9>W6 ztOMXJ;WX0E>i~Gm6ry-R2f$m_l9O)H0q_O6~;4O_5 z0JiG@c+1Bv0eDFV@ECpS+$%Z&F5qP_FIJ=%;TeJJX}&+E1dwM0K1S;7R4n9JI~pMF|-)$)d6syGzv~{>i}RO;#EbmLi@n|WVzQh5k0XvHNUG^NI0!% zA1d;FAhM^D{~gvB516KuWPYRrFkVd9CYpaQaCdVXw3x;7>>O$ysS>r~edB5K@Sx&|22mTn zF~#&`-nRom7pO$3yl+>kE>s*gOueprV+w80@QukuH}k&q1(D|cio*&HTlvQ1RaLw% zK6v8H$5s9J^S=9t=!DAfJ>K^aRXa|GWD1ihpPGPU>Fk=XBa=uSVtHFShk0Q z)on$j(ZQ5>Buai3V0#U%-V3AHX_3d{5c|NE04&l0h!*E57A)2Qh!(vmu05&)5G|IX zW9G+n0HVdW%>j5^2OwI6kQ+Ur12E|@&*nr)A3%e^T$g-|ve9Qyc6Q1=&`{5PQ8JGhuAYG3 z)fli7@cU7AVoiF!93}aID46sLCRW7tc$BRGK=lOtshghc1pJu>&`-dpw7PZzJ{l!Y zC9%6Hj2_d(9;7J!Wt5#{k%aG}Y%5W;FINEnp`qSqqU1M;0mFTxF<>X)AEWHVn)E&r zB^^UCnDh)LR>bvEl&u;?dphQYxmM#UN~}S3lx)YwEU+(~j(^p-hLMg}qU^+q7+jCC zMT5xB4z)KLs`W>doJR~8?oW*YJMi9&vJ-1k>wJ_n48>qlBbZnbSG?Y`97XkDZgQ$e zB|7l3gSlA)&_f|`5S-F(5C=w57&SQ6W6DhO0h`l8yoqBYr~DIfWJhR!H;(KG9jF1c zBeb_ul41V9S+v1%XdLPLv&`zlV%&8t0degb1rPD&PNXNEL+gcRWN!iYM$E0kp0Wc{&({oaB=FkApi_DPV zl;0r{^u)v5TJ2C^e+mK}oOTjUB2t{TuSi5YSlgVYG0s7D$7le3+K$!r)<$lgOz~ z+W-*RKaK%>y2d~ofr(CeE-_%Z$r^(nX#{3E?ZlcoGR!HhMlqNa4<=T`b&=C{07Z2k zKdN!XJXSsB@rHWNcgp8M94O;vUZ9ED0{zTSIPJunIIeKo3<@}2qa|ilLp_%|3ZUm45s)&9e~zg`Ib}eht`2lk*@nR zxgD@}nBRBWNf?PZ>ap$L&Xm{<@LniEbTUqXbf&3PMc3S?Zld-yy=v7q8Lny z1`{g^Q(rr6-=L_5sc)UiK7a*RnEFl!sA1|$yjF+_7PuJO8}nCc2n)PUarFnMop=++ z^G;h65UF}rYYa>(gP)vo8Zl@^d-Pv42K0ut`I6I4tSK0ta!SQ029sXF#EN=f=d?{k zQRRB0q4|Dy%4>lOe1T32*RJiUl9W*MO;2w z-NBqh^fH^G?ZleQcf~2uX+D_L2qsp<)hAlch0Q%vGSfM;uiBFKbDn7gXru#-c(hFb zKOKPm+){el;jaVmkyl=N0cQ@-09aH>sAse^5&Q#FF-y!|(dy#0k2DL6wvalcL};|^ z0nP2ZX^w{L9I>gK2n(7cbO1J$hbZ(!>HsKFOiDD<0a!sZu}?KO*8$j6t|CB`4#1}J zEi7>6XdQqfXccrdx6}cu-i@QBmQX3M8|mFt)BAl|bYr3|)FaY6FK9dv-ou~oD*i#TQz$2J)Ob=$#qg_uM$*sCXOYahc zj^ukO(drsY-z;y=jJ6PKVvrXtpFzX1sSHF)~Dq(pGu=GB#X1n zG0%#U;}PS7=-i+kD19qfQNTZJ_Wq6Naw!OnH-RG5FzS-=7u>{Pc~g#`vtSPOEnqupmJEI5cl zNJtRP*d`8k%CkhXGi*}_JKb5M*%4L=qL~@yU`M>*Xx78N>M2GCapu{UXj;Vwj9vu>lMJ1z2S{|N-Mu&_ADvx8I6eOdlJwGtgKuZMhdlx5NYR@nN zCuI@vQ3N<@sRK(;w)7?bWziyeQd9g!wJ{h}esh6Zr<0a&%21SrDEni`Le&@7JlpXf zp=O>ULd#S;C!bU3WhhfFf;-QJO&rZdSRzgI`cwEC9P2I3J(fTc7yb+SVQIlChVYAk zSfW_P6dr@Iw>VkF8onNJ!xGIZUg4_|cPuSg#W#E)HHNNce7&6UQnF z=TU^=^WfVT5#dd zpo`Y-K7=rEk%sNajZ|qSHpPC@nki02#p4)uF`B4s&o2Nmy-g=K(=G6YC>iUrHBa0_ zq%9CyG|~c30sS()4105?{pc@9zr}gd+DH76NJn9QXr%o-TNCLe3MHmf9w0S+2>@R4 zcmYJ#644Vi4?m!_27^5ZQiGNh1Wb9@41)Io%wp?su?vy*N6genM|dtJQVHJ4nd0Gl zyy*~31m4qOPwNx6I;!G(7ul_!Q16F&SM>~^e^!bw{p zyfyk{ovgmI!HJWxqFSej>wz*77mqDKYdTE#?1YCgrXOKbqv>OKkcY{DnQJnYVi0B1 zZd!~@B~Za)>IidLO%tGj%`{#@s5I?T5VARODO}#VP`pI^iJSNbjqsxm^3sTj(U^PI zC%ldW5w2kBTc7mGL75A$fF-O;86qM)9>Zo`#wwBF??3}bvdgv4_^WM zSXZ!0i}2wvnRO+rM1@yiMX|186(^p83DZ%RNT}GISg#iQp&Stcy#?!9FE3~neu7+V zeE_))7e0e36#?WJ7_mj@ne}P$JhhpJK~${Iczxh%vq@|70(IxPfRku%2tS6F*3Gd; zL1hZx0f(?YZ(k3LHM|4$;060T@E%)uEDhQghVcx4l-g`%7<>4))aw@+#w+|fOm5xA zFy7%8F>|fkZRfz+SDhF;*u)43zXGSWzQigam?alz2uRQ7U*pz-Zh-DU2aQyYG@QU) z%!CoFFN+~48!zG(b&)3CYn~BbgRrG_x7Q1pHsQ2=vR3&VN0|%1L=)+d&(FvV;Y}>4 z9A_0%_yrn~uYAlfk~O>+Ejd53idXn5ES%PhK5@YKhJQfazQ!s6;TLH{Zu`*3G9ivn z;AmEv_ZdQFc1Tdc+KBgAgj$575wx=^yw48QT5wK!Uw1E5Xi-JCk8nemZc#S~8fmyr z#rIi}y1?j3WkwJDDIIuQ2e!b^%Tr78NFzZb4K+GZ1PNu5oGQ`RL`2X?gBR|MJ@r8) z$^;gewmOFTqhiP*uAvN3`p|D=Xr=)ym#;bRA4eEF%8kr5M*iu^dN(j)M5G5o_) zFijvR&#w5dp%Fhz3MPu?0D(1^uqjo=iu6NKXcA!qwiQ)czXnvBvl^aBAXbu@_ig(- zph>87P#Y&KOo3@p7RrdrEGa1gToRuGv=^YcMAdFE+92X`{2Zd0FG-1G0T~X+P{L!B zXc&y7UHfQ?DZSKgl>x_B%!FsofbcffH~%y#~vdNpj*fKt2RyKT_faRQ^EWGEyrd=_n?kPvwK!dLa+Qv~?ii zs<#>)2>9MoL^_(bq6)KGJD1hI2Z$`ziVDnZ>0ptjvf-HBJi$|kEuW@M=PM?lf+ZU{Q0GS@P-!f&<*##o zC@M`Pw)}PG$OKI#w)}NIZbLe$$?YA6PN2VfpdGqzyP^NrE5PM63QUMOXtZ45KDml(sk-|Ywnmj6<) zP@JZVoPn=+6NGBdz7#r8JgtUizaVv|b&WqQbf7TE_v%htKK?7A0|i7rzdMB^{*2Ip zLL*-gKiq=s8-Y!DGt5V?@^js4$^Ng`i}Yb4o43|QzAm&Uk)a@NjFilr>vdrSIadY% zsYoj8-74z`0eAo@os{>3jWVBrQ;JvlUXa!XhYNmvy)-O$=-^D3wDm#^Nn3{YPat*o zr9odWbf*~3_fq9Nt;%^F_+3a`x9@_1oL0}2raoWsP8+=o)6_0}1>#dk$-U4=&<~;o z=QaR0kW|()RMrt#2o$8OVdKYh{9M7##-sB-j5@w}m=vMs*hwX;?&vxQ&M0-y=(O7y8h;&i6{mh()9(Ms%}M z+XA6+Bw8mH14IA&6M@9_B)aZ|E)*Ik0i8r>E`h-72wX7jK@Za-tMI!9C3z#p#;4`GQ`%t-s!e2 z;0}pP8IJxY1Hf*~RnPI>2Z{YuVB!$@V~|w3$wWstMt6nx{#B==pO8#-(d{5Qx-q(& zyti*VjbC5T^l{PMB09P;I$yy%Nv9hFno&fTK>FbyDsY3!e5l|(NTNpO$TDMve#7IF+*7j}cI6NxetX^2Jw7?5KO>622`>%#|R20x9`51XR%H z(XRY60FEK49=TNYNE59rNUBG!<<-y@-!&ZV)~o+XkO4HU!wK&pw9stE13QKdt)tF= z1}Oc&s}0f$#02p(um@ z*#pfsJ~C0K84dh{E*gq_+)kp|&PVpsY3P4X7Px3O5Dh)r;CJwmvvisY;McimHWAJD zMDq$Cu}P=d1^g>6n$1L0M>Lgu93qDzkx}fs{a7MVbd<3$n^^UZTSe+a_)T`WYlOhJ~TPbtjq;yk7*-P<-73 z{2MNsI*{<=h-Mt`*IlRi82FD|G|P!*E73g2`;F3RegvN0R##>HPBh1fW;E}&7&J*F zOT|qmTpi&?@_sw?_H}4WpG&GVwM65EwVWTt`yFc7{%^u{C)@2NrXjs@6QV>g)xw!hFJL#k(coUvWnMRx#+k0!PY(0Zb*nVAYl1c2SZh~oozc|5US1xymSbwEmd6qS4w@{m-W1`sXXLa5M~ zmrv+Am4Svf{7k2ZQJ8_mbQ(vbbaU5fA_3{9>y$t`%>+Q5q)m8PfLWP7YrttW64U2p z6m}q~`aFpOPdBDdI4_q{BeKy!(7cDl^f`^f7f4K>P1J^N?)tnyK)UJrv?G1C0U*Q^ zDuS1pF294z6(pvM8E$1F*W&We(1v!uYa_Re+EmbEi2}Bt-R~s7Xb##?qylz8+@D3~ z!#-3;DrBdn18f&J3-zf;MeI0mP~F7!rlV{#;v0n9Kq~w!O@f4^!9XO^Z3o(HLrN?{ zWj_ka$i1M0bki`LW3M8LVn{ZTWP`E%9e^fjW?IfgZvP2RwSPYjH zrb^5ZA;1J7F+(Jv5Qn5m%OGO9vAH@%l#Ni6Ny`9HS87Gl=#`khR3T}TP?&(kq!kl` zXWXPc2Fzk2C70ZY!qZ5I?$o!zL`*j(ZGtE>Nw0yRl3I|Y!zg@66_WHL3O^v_QNL(W z=ILfc()(5i>@^}MX*SGN3(Z$Vgju+05kVm5?UMkR!utVpn`1iDN>faah=lh$9l>US z>)TTScC(*I+Yc49xjkX}%?DQ4sy^=MI~8Lhtnd?QlcrLwXs5PcjVETpd_R$Tsbc1L zu5Z6cYrhuC31xm_l8dUW4N>)fGJ+7PCn2mqoz#W00#cOgy9Vc1q0mnp>}pZijvm#i zdiB@%cJu~ShM!1gQl)1k5*62%{*6XR^b?tH8f>-I(>AGAx@zN^*>89 zoX`SKHG;*AuCS9RpfrFU)6w+^5??_NOxmsmh`!x{-u`d<0xCr)^rFhEsL;PcO`u8@ zDrCu3RQVW{w@}!Plt@n#&Y*A_DTylF{i*O4O7<@JZ)a~l($irPJ%c@q{Jr^q{;j-i z)oA)pEf!0rql2ZR;Su3*Mq(M8#MNIZ%m&x^A@R|wZokUG4*W# zfU?*w)eCPAfFI9iI!G=5Q1m?xZ30*Us6h9|EV5)eh-t8mSt$gXxyf!!P~wPx)^ig9 z`lfb{7DT1tHybAfBJdjcJMA0h;6)QNmuB#AO$$_2@e!c#bf<_U{$%lH&EN>l8}ZEp zsY7^LOF;Y&53?)U<6KNgwZGAAxNh3G(w8i^j0IQKl0>1f!N!qT2NJ8;SiVc34rq@5 zZSpZD2RxO^q{X3ku2B{Icc=Pe3#0XzIfMpFXv`-#^7%cfmLmUROJAuE6V%GW)3-df zZo?%&P8$~uiBPF90|=>cNtEi#?OfD4M;xN>rRi!_)BD^trCkL?lf61J{xC%nF~FP-t|Rd1G1fIa%>xw-Z?}fs&U7?Ts(S;az$%m2CO8<|EO)EW{O;jWmzmX~4pjDC zP(0Eim~MOOQI5Nr$hmUw>>{{fv2*d#I?kZI&_9kkjvb7vJ8)j|$_CxRH$3Q$ovHgp zp(dG47R~NOTF)4ade-|Ma!Ktz+Hh*Z)FCg16!L4<8taTZjY`qaT_%<_ceSusA8xR2 zF^r1Cq7G@)$p)7ZHJ;0(j7H4B;Q)9SZ)|5sQ_6IrUM?a5P`dsbobrfM2-4l+h?^?z z-w=U@>xu-$DVvFOHzxqqV+7Z$nHy2P;zU66;`S)f`X7sMk+>v zcT+YT$-s?sn{d>@WTgL+C{H8uz}~%kME7PJb$%w|#~`3!mw|Dl1`w;kTv-GI=TUYZ z=?+5)G;C@b&zWWiHRudbxH6DnY05mIy~=<}>?uCpIlJqch?xt2q3k>owdl2xN@|N< zdIRv#u74^6JlF$$avpdyWzCQzd_rKvrbfF&Jvd_z&+5Y{NH}`l&Ys0_1(YpBGLwzMeT}A}A+8}1 z*zA)r>rkX)vs%D0TwLw9(Z$G>4^U~Rs? zXFKY(e(gj7{zO?eh*f{05e}|{)&DorVchS^+lC|hdnckv)e%E^!9s~c6 zWs-Y2ktA+9mk_j(imezkS~}DV(n%R#BcRJqQA!YDgQaFKDAaxb$jgoo^tC3T}603pG zuQe!AGICQmQx~@|BCG?HlKToOYyf}~&mQogfJ@kf8zuK;O4tklCAY{Xh~y$;kOZ#Y zaPH9h?Q7_7LqI%Z@kh#Ra_P6HJ9yVaRm&31?P`Wx1=hPf zd%~Lxgj+b_888Vz1Uk=^yy*<;?jxDbcCC^G;YfYd-90ke>d*qb$! zR!=?{q(@`#dDhvVSRE}D@PEK-r+A4EY+P{f^GB$Oz~PHtk{ zqC3r3qDW>G1@$~!CsC53GB$F5(Su6Yy7&a(YPZP!)a$sGpV#sbEvJY=*Ge^GGO0)# z3A#vex+uES<)dcI;i))NtJ9vAt}-=aXKby=PBJ8ilA;5VPer0IO*|GN>DM+Cb|Afs zv_}Ubk3edH)Dj8(W#{Mi$o1=9I2t8dcPZ%?`7A98cftn&HVTRK(ffrWHx6l{2AhMN zY_b?>jh2wHi)g4%bC7fz8jCyWtbkD>do)9$xJ><_cM6I%JEO|BCZuZ)5_ztEbw_~` z!3XO=pCM z+e=7)YY7>tMm zb~>Fq|2!RtoW7W{4N`j~I#1}=NR&q*(E*Z9jr#R6%6g*H+(9Hdz)|`hNxz839q$g` z1KeH>ufz4+fPx9hjO3{U-EtkTgWPHLxJfuaB(ixwq%tJ^3P2$UsR@#T)C}ofbO5_H z7FMcgmk~M1B$$^5qm0VFNF+B5$^AO6RnBX9h?eX9TdCD`IseIZ;TS%b5IOo_=dK@_ zyz}?)@N-Js|H4oCjW3NGK4Dzkh%rOrO2>_egH-%Y7(XO#FrcG{Oo}TVHR^v!Zt3{Z zacMmZG7C!Ds(D=6*zv>SGRF)VHEHNDccK5E|H|h7>ae@p`9JmhkpI@HhK!ytVnSTk zVUtG;85WnHo|9gXQt*Gtp#SgN;(uAfh%pl;mW~-RYy!4R><8F}U~|o3Dwp6rjo32U z6EpLdJTPPks@P%=!IUc*GP-qZwMwKz#*Q96c8p40GIZGR(n+HxmQ0*BZrB9C5aH{8 zk`-|a!9#0Mg7^UfgkWNV$z3vR>X2dMCXN_8h8jY2e!Gm6#GY+ayQ7K+1`|h&9)=R) zHPcmVj~D1v)yrs=Ayz|&jVhg{a-b@Ll12)a_@;6WKLUhHTp;k0{U+BgrP-6hYTW3N#`!=HUCEI~KE|cxwhP1)$hekxa3YY>YPu zlApL_Ht75uQVcNBu~L{KWhhjLVRs2sq7*Ei#cOh+FB(YV)3ak4=oAAPV+}lbiN3tl z(#R7>qqt#~0+v!JI0h?HXe^OHzaOAWQ^4GWFLD>I{EvkPk>F6HSTT!-sFvbSyrOEd z=H8l|yIYgF{~1jbW&&~fEHWxtfUF}{GkrqE)lkRXA{U`YFf77{OTqY^Yh#$i8y$*( zZ{-I}ANNCKy}(9N0uhRn6)Ay+-ODJxZ-kkBr7nP5W2Nvosj;|cTC9{17aAHT#V1Hz z#41pP_mHeHbZ;!a32aCksbhlFv#}JUXas6o&@>hgfS@Z=v5UA5ZFRPL0q+8Nv7p&I zEeo2)NnYXs2!{M{qeHT00`vB?thkt_K!yVO9z%-zrtzrkXBFHUGk|0a2k;#YXoOfI zddpRRAN54kcu`iQL~)8DH6aI&W56a!tk@R#yNlFHgSr*l>CkwxFMe&t-Ms51^uhsz zH~6+-B9cO-CQT(iLTVDidXq%$sn=|L?r49;)n1Imco@a$iqyi`ND8F^jc>#x;>Q`> z2J~gHgWY(em*fnSycNl*NccB8?|3w5C7FQ5+%(1#vqa42UZB>e^HlKBr*kxqSO6UC zqUH%~cE`m_0ZjnS);J|g{zhM^Q4=r?lNzxG5n6DV!3hR@Q5xN(Zs;FHkCb|8t);+V zFv=y}jbi&On&tx)qoUw92MDG+=o>6Bi55mS5$#2*V(iR1jvu3NBV0m}$r0Fy`Yul3 zrBKlpi$R`%7$Mpe{OC}SQ9Ndkr9i`YJvRjPo0k_mD^iH~%Iw(Kc~C?2;aRXmcr0dNw-b*BBhdgsG}?%n&P%amQ*k5g z5=o^v{LTzAV`IF}j@(zplMW0Vr&1Z&NQ6rF5inGRg{tKU$`YhBHEZlfAWlLkpt@14 z^?;SA=*#LlcX8=dO$`XtNPqhmq{~3c#MhHv`WK|-cXPe?FG!c)P5P?`Om`1mSAmpu zwqAh?|AKT4NSQ(ENq@Oh0h?->wIEeTfJYcR2ZpYg7bLEl8Y`tyEUfWJs)q-QYXI*_ zewU00EB@qxAPd)vqhQ(v4E|M_1!B+yi_5{Fi+IV!HCS9SH8wP?Y0J3y7`P}@kc?ev zmSn+o6UCS9u~~2(%(0K)&^GaX)p2chtRHq>_1<`O9%qveXBm0)Tozx_ocIDcas4_T zlO#ox_Wxx0hEwmQc?wn3wa2DU?KNgF_4So(Mo*~;EjyC2z~N}5g_c&@oJvOHHV6-m zq{gHY7NVx;M-Mhsu{ATR^?^AtdXrAYA^lLGYjSb`cQpg_4O$D%YbkhuL>84Ip#!k)G+()Bo^zv77|k8` zSg8mQNWncxDoTf*eCAwX?nw(zBefEMlbI^4lp(2_`_D;e9u)GOUh&6X<7)aPJocoz-tv@8L?Bjh%a zue0@2^yK|OB8~omgt)q>%PhMVT}SMTC}|tVqg< z^Q5HVa3L=;JL!sbkT!?nZR|3nK(?raiaju&#kN?8*z$rq97N6n6TAUun@ULW?8|K!_ZAT(OH^ zV6~ErC6a?&v$N!AiCVnw=z7}OkJ+!F2!loT|OD4hwh?gdV zr=JvNjbaV2%}BHikRcP9m7?5v;UFz+!d~fyW`fgR+dBm`&VCHul9HN{#O= zBu_M#j6E3}S}=(nlvN~uaTHr3e3dXa8MJX>L$H-u-cS5$66hOA7^8U@k^rOl0?a@r z_7W>+#wvG&h`I(gdhBi+HLwVdPe$=~*7-2;@MPs~%Usbc^WmMA*)5aFLX6_!Nz7QG z;%0?)$F0hiKjLkg|;samsRUq(S*NqT;MNoG#(lNDI@ux-eOJ>D@|-atey_@^T4Ll9ySW zo?ViWo8L2~UR_3&nw^{0qoiv}VM<9(QP0%$eClFuJ~wf6N!i#*<6SIsa!U$|QVY`Z zGl?c6wNwE)$?+p376k9HwV2g8O#-?2UwIz4CjNq{2nJ zW)`HRX1jTV+MF7)p)JYI%<17WP@l|<%#xHm=10&cCq0cENquTNVc5iyA*03)d9Y*x zTw%yC)~KK;Ee(F|VxT*HucGv#^pXr1+J(wX$#EYU=$Vq!R~yZG7R(U~atoLe zT`@734$P8ic^vCgdUi@*cywlAfo8V?EvO3sri}Rx)qh*5g!@PA;TX4OI<&Gno=;M*ho_nZb&oLJ!qg`*>H}M1kDLt?YpM;&P+>( zV-@@#;@$*4s_OjzzjwCG5VDX25@Z`7KmueXY%0oRG9iI%WD+))AsY}4NlXGlMMXtL zYbz>NTT!f9tJb!-YwN!6Me0`fwJKV{wb*L?eV%ha=gv)n_WS?8e&7FpUb*wW=Q-y- zXMfIeZ|=mKTm3RvjacoHNPT%#?NU1^qpGi2U>kC@(@?b?pt4RiG}S=r#2&+dOIs{r zuMRIlD(uiIlToxRWyveU_-Rd@sd8u)lTf*|tidu@^{RtLyH@p`*woWjCO1Ef@;MbN zj5gH*@h{R{J+Y?Nhj@mnmXsAq2Y?+ZGJ4xu1{e+0DT+N7 zSr(2&${f~!`Nx>i5Q0%$6j>fC4^=wt1w%wppvZo0V?9n_8p^9G!wp6(wywRiZ;qqx zRF4wttV+MWEVNu2b5C0@?kyR}dK4oL5+j9XnU$8V&QL8*& z_-GI+!nfs!mP3bZjFzgAQ8f+wdTkG5p>VjdJ`|?)xBV+H zdsrGmfizTBN6=D?8eK~mojVQu07aoOutC}v*P-P^>oJhmgu)G#OEBIRp%v={>4L#5 zX+cfD8IseST2}sl;RbkFTl2crc4AoKXuues8zZVK&p^Adx?D@wI`lIRZ!&R#k977K z7eZVWUQGJUf~sQ!7@X|Tj$lmX>{h2w_1TD2=MN7e zWtB@}rORVQv-EJHhCIx?ISG%S6&dR~d)rrcwzURZ)-?6lA!gWTC2F!S(edJ0_StOv zY>s_47jt7+QyA3-ht()6F5?^x4^Na~w#+qzqxsoAD6A&#y8CIPQB@UL5UQe)!@RQ$ z$%z-Wn(Wy#po5$J3S4e20nnfwvt5Vf!jM{7ZVek;yMzbKnC;p}XQ{-jP1lOd-NU7p z`Lbrb2AU?8I2gp#yh|E4>H}suTwj9H4A(_aKC#lSt`56dJEz02>dO4KHf`)$bz)oF z@f-zZ%yrHVF(HOQFIU5ep2qcW?b;0Lq&w!bx=LpnjlE5)+sf5b6RNwb6$_H78U@no zu;2ZrZ~wIomgpv^qmOs|sAy!slO@;?emu2cy-xyzDaM-KHh}KxIrf8}-%TdA63Yo3x zwJRnGWzkY3OEOd0+Y|1>Fu$QsEv3{_S2veX2c9KaAS#Y_S`& zHPVQ6F2q#KC@*mgIkv4D(5NffAslPhD%i59HU7sZ0V-Lw-EEz+@Lk*92{UAyYMm-= zFBgQWt3$Rm{eh|5+Acijrj{_0*81}L3i+zSYz@1=B5XhVaO6}O{Hs(Q3$8nQBGp5SR_G7IV9jj!uJl0|DX^^zD(#opJ71n~(DiJ)b)VHqJune5tLZeC=?!Y3~z$ZAZROKX?ep8C>o6^3%mx}27`J{rOjQrS=$ zL@fi`)700dW*N4McxI*Z#h7C?Hy$__Vi583Le_RK*JoLZ}@Alr--gq6yBeBL1 z^fQTVx!TW(cXt_=)s()BGwHQ3vNW$UDEAwtkqnXPK7(h(R`-e(hjoW}WNXCURV-F1 zmH}eNn5GgW?Q;PZ*{a}mwOR?ZXPGr!oz+df$E)6eX&Yx;vOxgjXZ4brE~|0b8m!Wg z#f)0!VRwO(e|toiRRFrXTK@mwf|GNF;+ghj;UF={VhVj&wKJo-ZEaW2#_Fa{3>j)Q zr;@9$lG3HELQkuW7!51RVYOvZ2S`7!a;{#i(I`?~hy9fL+B#WG$z@S{uS%Ix>B$m{ zwU<~|Ek7rtBUGCe&aqf~R4m12Wq6Tee9#RUGrow!5XRQ395HdWVjWs0#$d9Af?B+VioM)pe8UP)Of9GB`jY5yMGe?epwR%1ETd zuj}c-vKnng#vGkatBozd)2h}C*Y;56Rnm?zOvA5{hYOZXk#JX+;nv1m+Fryg#T$UegYLtqt>S$Um zB~UFT;E2?kZLLN3H9}~Y5!KZD*PB@CgSAjq5sv*d>=DT}yR{n(U3F^E?&?(2NG|LS zvNCc`i7>BG8#cPo^@^@vKU0%}h^#$A_MVJ$uw>E6b}VeVu1H5mk_-))kc6VLS1)Bd za9>k~_F8LGIBGdu`hEjqWTR8YBa-;fW~bH z=DuvdeH&fBFuT}XmHnBjI_}S48p+{OHWt+K28$AF`_mc`xv{DvkmeF9joKSaSXa{| zS-WMp*@0xm(<3_(Si8rfODh|~6*?u{yXPij3>$GUJ5t@2q2q=gCd9HQER97vYVVq^ zo<6l7CS4b^GTnb*EbB2%k!G)~i)C6WXj&>{mq;gHmoU}=ja3aY5QSw3vy75+s)i{X zCyeMT2&U>EitN*(_-S$cbVmHNBz`*6vHX!~WgX^g?Va(Kp;IN(!-G$xWU4N671iDA z)Rt>|izDAUf6j&p1BAIby1*g~_i6)0he8i-z~&%#{&c12dkma%tND>VcFTPxwF;6c zx4Kgn!nR9wzuRQGZHSez?!M^=bq33^7l5s!Sb0?_TA}tMr5e@dy-`tLTw>Q#+#-a_ zvA$4uAh0w+RcV#%ZPs)HQ<7rXlR+&AU8h#v>$5LYBR=h&TIq-S_w4u#zbx_tb9~9( z@<_uEY>3-2$pk_#5A`%${xM;-wU0b#u8i6Z*UN4j?(bmzh!f1P&|jr(&an3NRWrq| zAJ;}5UA^(0FqN_XGY)GV=O{C=uIfeub{6Jw<2@%I;WQQhg7Y&!Fj`IfpUv z8gxTg6_r}P%Ka+L-qqq+ef2Y(ayz2Xvg^`nRHv%MZ6VdbQ3+BL#cF%UE*odZDzC(j znA-T#jWOO_qtWmJ`yzYAZ;ugrI?Zheq@rGI9|ut_Mcn!{zI#_x5|_fD=m7CWVo`h( zuPDBYS2S1dMi+$#v~zVkTlajnCvK40({y`9T-M$z>ltYy-_Y z`)n{-QYXbmw5?@bk8@WFsy2$MA8I{zqp@aiYQIfX6{&VJcwSP4EfaOK8aG}4+q7Yp zy_1Dym6{vk#vC>?WEkpM-_}|fKSg`A?r-ri3A9z!$W$uC>cDTE-4=nmDGbf|D9n9IL``vKoe66u&QBCdA_%y8)H}~)yhPwG}R91#LhfpR> zXW22;>$khuCHq#Y0+EkZJ#8n*zio9l;lIDsq&tS4dBJ%y)?p$4{L8AY}-pZ`(Epk7d7g_f% z)G#j{V9>UhHIc?`X)ItHF{`zjG57sYCmj6;4NEeEwYEMH=)ZO?dp@p)hHl&%?rHCf zk1&I02DXWGW*gNCyR0*)JBoS?2;EzmYrQ?I=OuQf*_VZ@Le;XPyrB*qNfooqms@cY zy00tN+|sHtGpLx;u3YVS%|C=3C-Wdvp+?nDm9A zIxJV0VI`}Dy-mI9VHZ3qAa@SXfz)QQ z?5@Pu8+!L7+K4udC#mGWRjuGUX)57zk7K|+a3n>_zW=jL#W4DkkYbe(D}mPFpc*)D zDCr$eSrEy_v7;hnQmW=n&YdTn6lvYk4fW=Umg_RIZUFEJJ-rZeEQ!=iTRMgIi?4>_ ziy^#*o2#i=cGX)qN97i+o{{Jl?wA zyPkTf2boYLsvD?V5bsX|c;~Te_zC(Ll zCw7!&vLkmBtQBm(si=CGi&K6(uf+yT#f(C<7MNqThj37nj`cA{dOU07cnm~O3voAC zPj192#Oq|Xv7n|g7@j*fSX7ulBfltETv%LGIH$NInA3xs^G&^Nxxu`(E#2$p;eWHy zu=DWG*%0)tS+}+sT-DLl)R))P+&&NYm|I1FkgK}a&&=!X&TB221xZs+%bIz(wX=Rs z-rD@NP3@i2T6?>vt?CZutq$hZ76z9!pkS3-Q@rY2Of#EvepW(hJARa5(ZH$SD;U^^Sp zgmkmPz<}<#zOAQE{bRWlzJ4-d(6}f&7TC2!$#Ue3ZB1Q_D)JAZfh;$GZ%KQmWHs^sb_Hm6v$4#OuePsMrzb8HL=*%L{D0`({_l#sdWqQ#OuUck210^BZF80i-}YAP=`?_H9GKtEbYtU z*Xg!5u&gZ-WnIyKWz$K`{;(mi-emJVKKR$1P02%()bE+_g*57| zN8x187Sna~!}7Ko{pK3+m$%uJCTDE%p6NNueYWf8cnySlD~|ZdN5bki+K5}Om$&ce zkG%CJl$?5oXA54efUD*0Ir<~lg_8Yeh`dk>L3uMyX>#_Kz?uHD63+H*^`7H7*Zot3 ziX<1hE+3MdU78q6&hDSiEtak=t~1T!hCG67gcAF`IZfVtbWok8$#Y!iDxLk(CT|(i zX>*pxHYLwG!{;awXMQ)qzf{U{ohnKr2)F*oo83a(-hD08$q)-}P*mr5M)af&>~XWu)$-SYAe$Hy%%;c$H1@&XXY$Bnmp$nRIhKOU9# zhi!q!K9dtSUiQ&HyibLH&kiN;V~T&=cydLB=qVbO#?*{1~9`6cqeBAKu z?;pUAz03Oqt+&9r;45ua>fZYF5A8M*2V9TJa(vuI(g6P?OP^h=_8U6YRc`d6{xKx0 zH&{vVEjV28m-KALVSV&FrYx5msqcS%iV9z7$7jE7R9)aUh7Abc|COF@{4jlged$Wy zR>qFsSGLdO#BB^85PrA{-)Dy!Zl77nR0N%hKG$kNdN8XO@~aeh1w@fUlZhW>Us-D2C)(4VAj zi@&s_H1wCNK>d;HZ^t42((cmG-k+jdY;_vi_uF)folQgg`zPIEN7K;0QX$8miYE>2 zWfa|FFVoOodP9u^IMGUJ|nx8 zL%D3oI_FLlA8ZPkkAHV)%EvCQwN_N~ksnwe_TRU#m$sJJ-hI}a8|n#MwSYUw^Z0gb z&L?>L>(~1tgQb>IHL)3d+t>=O9x}5|>jvLz>aWt?E&hS^l$waz&&>C`Nr*al8i(r$ z>#ck8vs>rFE%XS{2&SUGhM=18E+)mFP%bt^u3Je;&k(nKTnnu0UHF|pzqrFz`*TIC zH}Sd3the#GDy=z({P3N$XIF(`1cl|+n@(LJ>n)eA`PN%8T_x0m@l!0F3lxha6ieWm zZ5ZQ)b9f!(dGtSwMAlSzBvDb`1uWOgn+S!{ZiQ>flgQJ_bI41`9pugAbIv$Xap5+GqqMQ=RG;$;vB&U%1WsrVDg3~~%PnJggZkRfs*86}S)k0Upcr;}UBpOf3kUy)am*OE7qHW5|u< zS>!e3E#zOwx5#hF0G6tvZ#+4VTu7csZY8fFZz7){-zViaennp)77D_4@-*^tQhsh% z{9htJBt2LPiyXh9shCSf$a?ZravOOgc^CN{`9Ap#nS=$7=pRqcBu^$ISQ?A}5^^

    x*32)w*au{Rsa^=2Ed}*0a$bg z0E_MfV9{LwEV>(jMfU)(=w1L8-3M?Mo!>6_l?W0ZBr$Y>S@fnJ-tKRgpnj=E8{382 z{b3e8OnbBF5wcnIDA_D}jBFM?PBx1+k>1f%?gi_uD0?Uux0E?LxJljzB(l z{R!>OqEE?Y(Pw0{=yS4J^aa^0`jTuGeML5lz9ySR+sJ0oH)JgO7Jx=w|>H{Q|(EUjbP38vu)b2Vl`304(|wfJI)qUAALU0Dwht04xdu zu&50Hi$VY_iU(j(0>D}HVY}eLB1rh!E+WoHX3>{=cx#)Upnj=EDe0l}O{t(2mp&R0a(--fJI#ZSkx7OMcn{c z)E$6DSpY2R0l=bc02cKGU{Nms7WD>TQ6B&n^#x$jP5><08GuFo09e!?fJM6iuxM8R z77YM6i;~iV4~ih+X?iM@obIml_v$2JV0wc3r55Ft77e1kSu~hz77ZbrMMKGE z(J-=EG@NV}jUbyvBgtmbZe+7)cQO`@0$|Z-02b{5z@j|?STqKJMFjvX8VkUpLI4&O z0kEhTfJG$$EE)&EqVWJMDg|KC1OOII1Yl7a0E;F8u&5k>MHK)nssv!sWPr0MH$501 z5{nMj_tEmqqN)0BY*l)K`lS|4Ne}IuU=~fKy;(GkY!*!?n?*CoX3<_`vuJO!S+oz? zEZUcB7S)l>qW#ENR1d(SnE))B1;C=&04!<%V9^`^7R?1<(L4Ya%?Du7{s1gG0Dwgc z09dpTfJKV{ShN^`MN0r!bRYnW8Ua|;1i+$Z02VC;V9_#wv#2ILSSEsm57JM})|y3e zdf9(adV>0;79ElvT9{}St)#tKbST*@I*e=<9ZoijR*}u3Bgkgakz}*zD6(0!nrs#w zO~#^Q09bS^0E>#MP~xA=qvyhoejXEa{yR$E&z+p17Okl0B6yP^x$bCNI0#hh;y)6v_UPpAU#3- zQj6B5hi*wWi!PzPS#&AcEV_(r7F|v@i>@G>MOTu|qN~Ve(bZ(LXg%31x`vEJ*8;F; z0|1Mz17Okh04%xzfJHX~u;?ZL7TpZMqFVr1bSnUhZUbP^?Eoyg1As+$0V02bX1 zz@mEqSadG{i|zwp(ft4{dH{e$4+5M;7o`WciXh<%eH;H`vuLq?A>^U-1ocZTdNe)s zbE;YN812oX$H`{VCbC(ynQRt4K{kt?B%4KB$Y#+~WV7gLvRU*D8H=6;V9|2`EP5V* zMK1ub=tTe)y#&CbmjPJx3IL0?0+02aLlz@paySo8(}i{1oa(OUp4dK-X6?*Opq zT>uun2f(8D0a)|_0E<2ZIEx-m4`!u_Mceci(IaNjiTZBrN9hUbms<2$dT7sdv*>f$ zn?+xc&7v>KX3HGS+tF87JWlDi@qhBMcPFV9{>?EczXQMSlRW=uZF^c^P)ujzs|g7R3RuC|j8pQHz8iy+~P^wayFnnnAkN=VK~P`}iob{V0g!)8%B?aiVLvRM=+ zn?>!(W>E*SS=5ni7Ih+-Dlu0&=I+L-e3jm9{01}`U9|N7XTLR3c#WP04y2^z@i)g7Ucq* zMX4FVYebOnRUr{4EyG>uSLt2Hyo?0(OD!6b5qh$NSu~XPX3;RRSu~t%7L6dAMI*^( z(Qah3Xm_$%G>U8%jV7B#dyuhcPXHE;0bo%90E@-~u&5A#MMVHCDh6Ot2>^@60kCL1 z0E`-(R=_F?GM1B0{~dG0Dwgc0a&yMfJKV|ShNIy zMF#?~s1blgO#m!v24K-r02VC+V9`MUELsl0q7?vV(bSCKFcBnthn`(eGmGMTNjNwo zLH$yT4$BBl?Q9kuPJ6Rx71=C0f@~HYNj8g)BAZ34$!5{fWV7fPvRQO2*(^Gaj77%- zu;>H;7M%#dqBQ_4IthS9Cj+qP6aW^j1z^#s04zEUfJLVRu;>f`7M%&eqO$;4bT$Bs z&H-T2xd1FW4}eAI1F+}<02W;cz@m!)&Z3nW!IdINIG}eO4>gN^)E_gtI3q#*Qj0Fj z2wm9KEV`WbX3-U7v*=2)S#%ZIEV`O(7Of|nMc0tcqHD=!(FU?vbR8Lst_NVz4FD{< z5r9QE0kG(102bW>z@l3LSacfzi*5&C(H#IRx)Xp!cLA{IZU7eD1Hhtt0a$b&0E_Mi zV9^5rEP4=tMGpb6Xd?iN9tJpzF3AXP6hXp;DI(6LX3X%xyDI@fLce7|S z?aiVm$Y#-#WV2`s*(`dBY!*FDHjADin?=u(&7$YXX3_IxEP4TeMK1!d=p_Iay$ryj zR{&VF6@W#r0c02aLtz@j$*So9_Ui{1iY(c1tldIx|-?*g#sJpdNH55S@i09f=P z0E<2XVA00_EcyiCEP5;>*fvWn8m`{~dE6{orQd4&G$TR%Qj5OK2=&i4i@u`0S@bp8 zEZRmki@qV7Mco}7X1mpA}?&0?N}55U{M?Zi-G_wY6HNc5CDtf0a%m(z@oMQEJ_4mQ4#=)k^xwh z0>GkFfV1fHj9|G45`Hj4#Q6e?^zD$eaDw`!7KOv1#l6g;_Ov&PI*`qxj%2f_6WJ_^ zkjGgX7Ig<;Q5FD;dH}E}8-PVU0a(-vfJMClSkwoAMSTHS zv=ab}b_QTkKL8f>2Vl`I04&-SfJFlUSTqoTML7U0$^~Fi9srB-0a!E$;4DfH2hR{e z!prosEFX%wHJRG{Mk6AQ=_GZyYvRSkn*(}`i5JOCEW2Vl|u04zEHfJF-cShNs;MT-Dfv>1RzO8{7OAOMRR0a(-oz@laV7A*x} z(J}xQ9R$FlFSY21 zaHycaS#%`r&7z~oX3=W0S#&hnEINj479C4Ai;g3kMaPrPq7%qw(TQX%S_8nMlK@zB zG60KC0btQu02ZAJz@pOtSado7i_QRG(U|}&ItzeBX9KY48~_%b3&5iD09bTB0E;dF zV9|vDEV>AQMHd6GXdM8HE&(`;4i5+Ch#=w1C5Bd+MIY%;VqF?eP`|uRURJTvRmX1`2b~h zJurHFW>fy9N*LP21K5bw_EZe9e47)A(6fMdESV~CA)ausL00yJa0^7V6NvC zMVj(GZ+zsg!JbzZ`E#h}RYr~Z$Tt?yyq>6ES=za&5?V`Ja2gSlP}+Q=1qd)^t5&-eAbb0Ycmo_9gypjn=`E^=Rk=UpBN&hxyhBc=O$-iF923q0?} z$V-bn@774y13mA~NPUy%-5a@TspmZy`SKvodn7XWV9(nWS+UadwnQE{%=4a&gpTmM z7b6po^1Q8)Q;+t%HzKbb>v``)x}V^AA4F!Y@w`tW>reK)FCt&B^}KD7p{IM^_mM-+ z^t|nnhtBrA-!c=-^|BfQnZq~8dI)6dzh>Vjkg5M1dA~rW{(I5`0-5>`0_O!X^W`!E7s%9Kx1Jry)SoAw7s%A#mt7FZ)E@|463EnFcx(=2>QD474`k|ZtgQ@W z>W^ft3S{c99IXyy>d(|17s%A#8Ces^)E|mi8_3je`kxWV)URrv6Ufx>+FlUI)Gte} z3uNlI-7XJg>erR74rJ>0O*RBF^$PvU;NJpXQkiThq08MS*ZCINcH)O*WG8rD zm#%V$HZVB3y*$^)-YF6v~T&eP!5ic}4D=_>Zpl%D*um7(7i`m5{OW*Y#%k z-d14n!O9+&e2=mVWoruzK3AFkYf*alx9h^NvOAScms~A>-JX?8>%h>oQ>4x5l8=_Z z?)#((8|E{w`)m!vEu1G?cwj`Dcr1e*CQB3;X|E(^N!ZOoVHXLzTbQ6>l!Y-m`=c%F z(_6wG7TUx~*wez1vJVN2aUo01*Z#=P33xpMmGK!bzx@4%gL?!f$7j6w$jf&x?-8hq z&-n4KZ;v~qN1!^Ca_5?H30_vFEXaA%XozbR*Y*Q1YZqZx37h9wDCP6(GJE>td1%w0 z*RAx&^Yzc?+<&M)o)4359O_TgyH(m`RY_x=iz{gS&f6DcOXE<=%_-Lp@!OvD<+?|7 z9^x}Tee2ramwQ=f*i78TOyqf4SK3T`V@yzG%Tj7uB z+MB-k{a`Qq8fo;9&c$l!C0&F8xz-mKzx>S>nP2IPHMiYzw@h97;>Pcey4x+ornOB= zy{zk{kwBIFP-kDJ9&)@kQx=iwWwH@u+#%DZv+NBpB?l0Ys z>#kgPnBRK%H@{W-OLtApknUdgZ!|6!9kn}`+k`XzSbzC=f5M-veyXG2bm$SUi6hc6 zQ*w^o&C9Nm7XEaPw5GQ+-J_qr>1XMGS&tWN*>f*x8=vvowi~xPAzpv_g!5!Q9z*NX zcWTiHP<>g`Zm+aX?77h$?^(;SP>xPH|+FH3)jE4RLN^o1gr%;MTtKYm0eC(HNw zadTF9*;&%a_kDjG<5I?$?`5sDF<$LhC}nBK^V<3&Jo$!`kCRT9xqc%3_}>2bUfQtF zU@v=>H1W+{BTsaRKcMZWS&dWuw%0uQ`5h{5D5d}C&(i$1FSj38?q%i3Ifpih3^FY~ zdE2YyszJ6`#0Cl^s**M6YYmxTodh@D{U(-Y_G-sJoFj9KG*NT1+RTO$Df5C*1vzO?18pO z6P@k7T$A{Wo3DED80Wy}_n-ca>-Hx{1?KtFE37G=@Adr3+W3>$ZB}-BfA&sz>A9QT zuJ(@WuD?QeFYy_#pZ39~m7dotG28R>FFr09-|KbhDgBG@8%*jI5vqUjL3w3wId9az z_;2Fkdu^7f=wJLN63&qQz5c~NFX1^k;^<#|NZLFsPxLRoO)%aIWCZ%AwNDPFbxo^{ zWCYS9o)_20OHSTHkmm(EdBL>Zl6OxYnOxdlPLu2v@h&vfQxe}M5KP-6IaywIg9QX8 z^pjTIWJcQhPh`)K=s%GSG|5I7awAL*1WMa$la!t^x?E|J+D;~}V@_)yNKS4UXS-A{ z*p@j-PEJiuNgg4Cr$<^1l_5jL%x~DDO|89+Qld_?gN@REwPlnYZIm`tCutOFnU6@S z%&1N|(|;n%)_F+GH23U0ss>V`Uv@%L|^q;CVe6MjXoVbaob{`Ew$R zvl?v+1zL5rR`xff#E2ISD`9`rX@41`06CqLF;#0BB=2QOKJV_Qa&O6o9 zs!ig&L;b1^l=G0jkx~1dXgztJ%z2!bcd^!MzIHrD6PX4&T3q-qZRQIi)JlYI=dlvVg0Om^B4VpJ{wIdnqqrm?!4TB#@S2fFIrr< zxUpeiv@e!7H~L-TdZe;(@&3~1O}W)e>KhLzS-PmMMwVr6<$|S6byWq!CJkjZ$-@30 z9Q*%7f@Ss14Z1Eo&opWnk~2%TJFjkb!<_o13!3YiS1f60%9*F`iU_mkFKU(`XS||c z-K@n67cO2@SHEPwFwwfYu((b-Wmcijg~=v?p7V854teq&oshpR1P2E~q4t0G2nFJU za|5A{!Ol6MKyYrhKFii;Iia@lEGHC-9}^142lUD4Q2TfpSA4Dlse5>FZ2}!b$y(Zl zdTJ5wM;&~S4Bjc!WtUL6Z>W9OnD&fkbf}9A-#*(PW$RJrg?j2F{89G)FQ%}o3>EGb zYM*Hxi8l8wbCD$@X`3BNj1Q)c3PmI& z#!n1&lG?Xds8g1tJh!0j+=BMC1@&W&ygVqBD+5P#40)lx+TP~-?;E(O?D2nS==MEA zefxwW-DHMxZGm$A1xjR{{r#ME*7=_pij->OTy56AXU|pr2b-TdY7Q}0k$*W){OWn!60fgHBCF!TD@lKF9zxHHHNF2earP2WMOT$B=t zWGmIFb;%9&&tvj#L2N_)`xP$sh&w&}`IqOia`bszWqb8X(m-Ajb$jFw4E2-c3m&XJ z&-(hi+N+go|9ZvchWh0>Lwj1!|C3gst}@M@q5i!>U9{tS?y%wflVuKd6=7s!(f;b{ zFN|AVJ1)$>9ao<8dso%GWy5o0(v4j8{!diuGAPtl_X=)Ynp(ul8p;OcUd;-onBTg`nLIZ4}`MfJM;@>#0QsW%hP~7%e89D7}53BE;PVA^ka4? zLt>n`sQaO~_~1b@9(@)}%GT6T2cM`wqDyUyCS!)Y>WK+twjdw-LiFO?WEg6%gWCRCd-Tlm&TG*B~6a_D1l6AoB%z?Mmt^NFGaw!2j!pj7;p>An|GK(;5B>a)<}~(v z&+Oy`XtbOFiC!wwKbq%ISMjz-FaK!zcL(*lEQuY!%X?OGt`6)lNlOAX+ z<%M?A73xy|!J(b}rErHYvCYoX{u9+li>h+&WhXzbB??mi?R-nK|HfYDf4sErZ1q1{ zT7Ow%uY~^XvgsO@b<)?Z6F=pL`nq-EC%Lk9>qL`t$*mCC^>x)(T5riaoB#)gj*>xw z$E=JimL1RkYZriShq2@775V?ymyvGPTb*^tiuzB^;#2?O1z~!8@YBQQ$gQR4+T`d_ zJb3n@IdlCJ-G5|IdhnjZ^cK~%ZTvemPaiUBu79_oPp?qqulHzLU0!C#4U${CCDoO6 z#Z^^xrR7r!%1Vps3aZA{PAV?1@pxfUadmaUxZ=8+ii*0jit=$@Rq?pG{DQ*q(IE&UvbMa`hASx?UpKR5z=Eoxy7Gz|8MwN*s;0Oo`pSe#8EI{Kb!}y3 zg}zW%Svsw_tgfV@YEnUso1%=W_26U6Dhemo6&2JJ)Rosx8e3eY%TZC~h8{d3cEaTq zb=9?Fs|%}2b+D3(+VUcQu;C-d`*mci*{mwAuB?zbbYmJK!_XHx@5NOG)iHBUzfGzh zS2wn{q(sJFT{@#U+T<@wRys+0(;r5Aa%^7gjFy(y)iU9cHgowUtp+KqnqFB`A&XpA zR##b3T3%CZi#*7NFOVwtN(T?BYxb9*s8#c^Wpbmms>ELn#pMMOi@b`G>bim=H=3dT z&^l)&F$-Q?GoJpfs~kVQPS*7#S<8h5HKi5huAfFm8|D|rv@ETfTsKx6D=Mva6QeKP zD0O81YO5UWE2{lDC=#oqGceSjK1*T4mE_Cz zQCD42Qc~Ay;QW!ThAu29udAslD6gJWTH}wos<@zNy1y`ETM1iLT_7X!SG9DoiOn=C zstfC?YbvBqi$zCUhkl31DvR0NVz#H~0-HSrW&V`wDk_W1qpzXz*s9WT<7>*LN9(GK zYie{`X3`~vWfT3`9X!NsIYa#^`V-Fs`5TjuL}6Q3BkaX|>AvXLN=vIs3hIgr3+wX7 zmfB`s*lJVscP&Mw1>@=}YHKQMYwD&{l-0=g6CDLxgYHyx_oKV6n60y@cuJ|fGcdNc z+V!$*8!;VZja6ppWZk&6KVq6!O_NQ!u3}1YRY_UJ)Ey^URX#4d+Z3+~CPfD*t(2Xa zt>Q}Aoy6`>{Y9!46QVoGLD3Ey8`C+uf?6i+e2;lqR)lm(UGcQS;^Ly1S+-@8J#0;Z z>>(x=Pp>N}DAlc;b!bEAJ0>z~6}46JM7FV#veLqqy}oa$?#!ZHmp>@Ffy<`uHbB|_ zW-nd1a7A?7{^n3zQQCU5Val=_o>Wn#t3&sbZWM$34P?RMMRT)dr{%LDj6PqU&{q1e zx}xPUrMrEvbWu@#bG^Lp(=e&Nskx!Cx?xshLvyr=?T)L8%ZmM7w)SChYrWjQRJ%gf zacPO`D>q}qVkYkIj&z;rj?X{H+03`niG4v`L1AHSRY9Tc*`o6^UJid#3uO6gN+%V| z%JauDBD(SmV!`esr^ zk(+xt8Hm1ESX@?CTUJmd?vE?27R~ht#)2Rly8<_ldD7fp#8&(A+Ul|XQM|5tyqvPQ zA!RSe{w`*clZs^zX6G_YNynEjJ5SfH*!O7ZqS(dPA>^PCo$;bUMRugDDlRV)TVr<1 z(G^_ipA(rg(u<4cHqRxe&{ZZ_>h3p~xE!*#&=$4T`wAF~%d{|pChxu0G z{L6z}i#KIO75@G;dQ7o(>{f~Fdu&za=i9MMj^)t~WLwXxE1FzWS2W%o&RZY*hs6wU zyRS*IC#tRTk5c|FvP3$hdVI{z8F$MHrt6vH4u@aYRaM1>#j;O`t~}dA)ah<)&eBD* z@`entWoRXA)chU#9~WZIkjrGtXt9BL8dorBQbBZ{w7290j82m6*Pm$1HlCmFyE3l4 zHoI`-$ZY*YMoxaVekLPt#GoPB{TdqtK3pNSN!V;T#6+{dh{Idi=$qgUHF{F-uh!!7idxwr$qHnZ3?1oKN$ZpG z=s``+=L*J_mX*$EIib#zU9$G^;8r`LqKtd=8>>>q06TvQM2(E(V8{zX&E zs+H}nP)-xZ7RZ&9?O=79auMKWcX-QIAcud)T3@l~^@N^1l*$EzJI~M&Bw_M2WaDHxk#nuOrAu^_hI{oNM zLt~>Gr(Dt3sX_ z(o1L`$w{{V#9dkXC@(scdlp?UEvHESIj&p^*_oSc-fnENXfb^gb9$*KpRx<{#qbAh zxkij$+zzv`xXU`G>UQbHlPY7b)e80QLF@rU=R5XNbNp1fK~XqS_NH!$T5ULN0D9gM z?R8-6b@YF6#a2>UQqlTyvc;jIf{{-T8ojD380+6=i@p%kkyXVt|ME23-$`=$ zt#jh8-28cxGaXq5=1HzSeRTju$$RA1$Chm!Bw5Dhp^Z;&e9?olH?gOB`DSz3GA6muuhyMqi>x}xzdWa9<+i$+ z*Xr~-db-YatGk|}7pzNLZ?3E>zdz(u$@Pa^wZ-&@9tri*rLKBvX^p%Rb6Dl_F2CiL zLB8y+y{36`@)W&(){8lR0&=AGpXkM#0(Xt&zZA1U$;ov~59zI3|9*>}n#etdx^V@i z?gpQD7afewk&A}fvX-+D)twU=_QI|2Yqi|*8N?kQy#l1q7_Xj_c>DYNMx9%|0ArBY zs|C4}T3RUk7}@97_+1tqs#-2{c(t}tCD;1|+(_TyQYyNd3QG!GR#Cp*&t^(?_ro1S z{dMkc#_QAAd)ofB-VVEvmb1*F;=ei1)O9_**j@K>!Pj~>pdNFn!U>%}A9{n@f8uVt zPb!#JS6E(S2OGWX?9Q8O7Br2MPl7kfhj*)&&XoV6i{{VrUk|D7l8xn$-nH{5)pA=q zUv9F+Zfz~+H`)nqJ889lieBjJ7^CwL>tXat+4|hSupy?9XrP*rDbv+7kdk#GdN6G70B@^w8>eR_rZO--Ca3 zWOn=M=*=_6>%Vow&H$)uwW`+b<8+Sf9?|OVi$8n$b{Nv@9v|o( zPydO#E2~er(#em#*=b|d`|TyNMR2ppZvR#{ET}7-zhs`=|6Mx2x#i@Wa~yvP($mqI z^tUlNbk!78=}Dn%2yz1QH``i%%>7xL{d{+GRY&VCtyp-u>u={U{`mzr{{894?3m43 zchVERM=6^uXD((H@8{*aTdV$P^iHNNcHx5g4U3wq>KDykywLTcJBem)bO+t~*c09U zVmBE#cQRUk^NsdVVOhbX%9#67&L4fZPRHBwwpGiuLH>~FPLAy&U+-V~6KMUuOF^Za ztxuEd=T?Tt%%1BTx8<-rYyfJnyg|Iv4BP(3jn1 z0F$hA=hkw=F4`}?JF>%wg2G8ft*$yna@J#XjmFB?vY*xa*0Jv@F}rTD{ce*k_4}{& zIe*J2>3E(dsTr%SEERZ*Fge>Fnv{ zO7tp<>FZJ7KWxQb#{Td8+8EzD^S>^{R8>l~n#((#y%OuZe7S=bU0rmtyT2Oq`2u%M z;`e&&nXZ5FI91*=)_2V->}_DC>Tc}odxkq6RP%C1z<{t&i3tB!Wq3dqPPN=MlzJsa#$?>ga z9B%DQt*Dx4C&JN_m3%qJm4#+d+3oSJOY7^l61lUqE;a)G3pTHn%`xN;OFwZW2 zpym6-8iQVR#Qv+n=r8T~QC^o{GKhHuJ^4y@%p<+nhhb&)DjXreQ4~!=H2?BY3_zwB#9rA@c z;U;Ohw?mq7b^N@iM~zf-b!#RW=C(= z+bzTTZ>2f0>xI7|ML*BeEbFh> zXr7=yJ0Y*@57THq%(DL4jOLTI%5>L=|4G^MV^>;bI&I`vF0^*iD($;ymF1aZe7SM` z1s7e8@Cybd?Z z>i$;Mb>)X!U2S!()l012V)ZVo4_JNF>XTNVvnoGe=8yMHtM6O=)aut(f3W(iRs9tL zoge)d^0dkijQO>_RsAJ&J3(JvwDx!hpaws^=YdwS$)Im`&K`*`i<4? zR^;Pft+qPDYQ5EYRu@}cX7y03`g>e{ ze_7R^6489F)pb^{vZ_DDrLW&+^3Rz13f>#>sw0$De35 z-D<>Ymesyi2Us0!bvLU8R>xbdusX%+K2~R2J-}+C)fHA(Sv}V3$yU#_dV$r;tX^aF zCaZT^eZcBtR-dx^qSe=}zGwAQtJ|#pWL1BCO#3G!rvX}1thTq>#cEHh{jBC%9cFd3 z)gr4CtyWo`ZgoGabFD72y431Qt4CQq!Ro12&#`*3)hn%DXZ2RA_gK{*VA18;Z1q{I zuULJ{>W5apu=<_VU#te?c%QbwR zSv}V3TC3+;z0~TpR&TX>pVh~#K4W#O)pxCaX7xL(`b%)W4|2fLnr1a(HQQ=`tAniW zZnenjB&$=b)>)lr^+2l!TRqC^8mnhoy~yfSR&TU=m(`6{pS1d-)iS6gVpJ?@w!7e{%HAzlbbohwX$`LN_ zWA&`vT)xce8>3wQ)M~FiUCy;SufXM{R39R?n$+`3kFV$qAP(-{)5QOmjKk>i#oaKFI2gd%Jv})gSkD zIaufFsCrjRtsXhcX_4Aon-ZxGhII2>Xx%z ze${IDJePY|opyoC4OTC@$mMITez4BvZ>;WenajhiF1fh8n^rq*ak;nEy`Oe@zST>gb@>LX zpFHpK4_0$ta(Q>F&9At8gw?xWb@_3t-Wx8bS}l3YV9%xN?%`S^~yMxZ?XD?{0g+b{O zZT0?Sm!GuSCe7sxs}s^)o@#Y%*yRhYzAQH!bbRky?Iyn_t+~I|nQ|ehd9l^2<@cpE z-)8lz?k@jobx5|$1y&F4YN}QlU#8`5R(l#BU^&m~P~&4P7g;SeUSoNh)qRZb zZ}lLntF4}D^&+d+TD{ZiqgJ1{`nJ_Cw94}K%yD(7)%jK%tzK#MZmVBg-EMWD{JOD@ zXFsb4Sv}e66;|)I`n1)6{2s8jOR~C$)p1r=SUu9}9abN-`n}cPt)|Nj1RY-=tJAH{ zw7SgddaE~E{m^Qr{7kL3-_`2ARu8m#h1I*Peqr?otNrA6XSMy_R!`O{UYut2e5)5* zz1r#qtG8Lb%j!m}k6C@j>I+uiu=3e*M=kvU-Kp^;YHZ;=lf+RXIHP z`DLsA{V7?#cP-2A*njU^sQT3u@ObgTaTB^m$4mi_xnlCQUXv(@{o`uCOO_05)_vbxo( ze_u&n|Jd^9R^@WYi%WC&!F4(Hp;az>{raxnN0BUwdT||P|7G0EXpFiZ*uP0p_eHUfO4o#&y{YOvvzYZ64vDJGTiu5&o>@0t}jsCmgbbH)!y0O0p ztLsxAy8R}~-x&GR$EG9Y=l`W)CwZ>J=$}q+FZp90cK)`-EUz9@n7_B=xwyPU zivPG##bGk4SDLNh|k&wJQ!bwfY{-@a|527 zibo#|$M4t<%~_nAEsy-+dBaBJ4H_{xU!LdX#r}WTupz>R3?HgBJA1#R!;8yG+|Mk# z(FWvQ9LB3;^(cRdLT;bX&+9Bp^7i%x4-fowd&L{u?|rv>N!GR=!Q_imE-KjO9o?a% z{M)#y<4U${U!A>Wd)xd?6Sr)CB=3#wZSuWce|@cD+q|?#CO%r)W#QY~2b{iTyVrBZ zLjC`F{{LUs|L1Sn-sasc+uuol)!GE-we7iCc*XboR~f&w{A~Ke|!6Wr%Bt4jWVvYCT^6m zGUp#=>%6QkIc?%;6HYHZUFOq!NQwSU{PvwfU6yIRPoD7h_UudLdA82kF%xyZUbFdP z49847cEYix$Blm?W(;F~oH_Uj8Sbcw%O^as{n@-DCq5xP-7^2_{@iZe-oa|7)oy-0 zAi5M=w`bcceXRDgI>4{{O?+W{o1We-zrMDlXT|qJ#*F`V@PMt`^Rge7^|p2U5UV4s zj`HinvTo!rec#f_6CRdzDZ@V4e%`r(-(IZv{=w=O>c@OLbFlVT#kN(28)e?de|uZg z#{b3MeMdK0|9>A(nqIxqL4lM#OUsgFOOZXwZj!S15XzFh_byxZRHlGzWGW~qB11qB zR1ic_Mim6vP^O@8e?C{<&z35Fzy5xI+~?fq+~0GceLW>KNgqkBq%B`{?rWx;t7^$% z>e`LXps(2<9@mh!aq>1^UF$az^?$4FR;SAlmY_d_i|n7@i|zWm^)ae>4y(_4Rd+RS zwKzoRa`^G_**{nw{O(>#j7@GBb6A~^*oPAwht-?)d99J}Q*`tMWMsJeWq@``rRx1{dY?;EV&uUo%wO>tDDtGd3b zYCqk&IxR2nb&X3li|TT%s}j;uzgH}x`a_4ida^yvV_m!cAzIY(I_mfEcihW7`yMCN z-}l(IHMq-Sb-mil?t7eT`9AgE)UR3USEBlrq<-zac0!%+{`<7H`-$qU(x%S;bandF z^Bmb_vT|gL?qHqMmDcYUt=~_G24?|v4qs8{t+_f^)zrDFtIk!te|Th9CGlN#KB7Bx z)xWQ_e!tjtV7y)f-3J~gEkE$sHY?J1E-M{)oGbBwx*Y0PxcZf(e(hDiY}ZbBlf&z( z>!o#gq&InQ^Vo;eGSta;;qf1{)qkC(ep!FIy+^$lrGDwt=(o1E-nMb-ZKC?6Zf)GV zRC^d+UH^&Lhuy>UTW@k=BmH)Hr2f5UWMfYgbeE(#80ohtvVlI= z86pxcwyz%VJKy?NtNu>U#dhj%%&yLx{#%#p^QqqIa~BmJS;JG)U6bB(=M zhe+!@M5g?CeIDjSrcXH!_V@}(>QUah9fqs7_8#j0y6jiKu@5$7%yGGFNd3VRy2l(& z8kOnW@>eS@yS#eD`C6m zeO<=8Is0pVyK>*Veypcit5sx3z2NW1Jicrnxpw_e0n^^>;`+?iBbzNU<$m+OUHYA# zo$ilQF8z*_OY={ceyeAz`~8$Zza{0*Z}x8XY;kX~?*H^P;fmapa!qWEkLa@hUTlXs z_9yy&wn0Ed_2jdjdUyN->)r8l)_xdJSJjZ8+pUaS>Avvz(gz0~7v8F^s9!b_kU_oG zUiA)Fzx38`lhkcv?*a9AeX(oUozeAdcRm|;v8&_G=<3_xthqbsa0wsD|WQs zouVm!a&PadcQz$X@J{qhbWgG_!9;J>s($@fxfD5;Hn(u=`ZI z{f}4K!V-M*M% zD^J5X>m!E;Cpfw+@%@(uvB|As;ywG?In=q4$I_O5OW~hSU6QENa)0KwuA4*ZaZ2Cr8%7>dy{5NR{2_I(cuM|^&AQjuk7-rh zCDc8S&93hkB2%x6`mxDozCzyP?J_3h=<>GjBetoYT&;EWX+^F$Nm}B(Lp#LuYvXP%vuG#1wDn_g_KNNU+&Qgc;nS$ zD;=J8SEEw;J2){Q7LE;qWkxve)h!WetwCGe*R+& zXMk#^Emq&o6J7T4AvSx0&5@`df4g1`Nd7GMTi=v^a=ml5>($5o)F-ccrFNMu_4X2* z+`tw4aD4Sm?oD--e9mY$9LZMp-+bU~GQR>tkI;cz4I^|Ne@C2*fJY_fWq`B0K8pO|4A1U=Rws4~R#CSB|9mgM9eCVj|M7MZ{a z(Vmj-l4))SQQjy|v^&~5*O|Opn^G1P=5?t{c0fJeACS-3%d7?d&04s(YEskbb$T~G zx9o%6XViDE*cE$qd)YB5$xpj4G40@n%PU^{Wc;qHmBYF&b>!aO`}m>(9?k!t3H+tsULq*IskGpQT=x$@n z72sGabYW$0kQSb=Qk=(n zTdwXD>+P5A%X`XOM@|j@rTC(M6EF9+miR~!-!|nV=l2F_fBkvPvUSs_ zw?fVZ?CDtIX~D5Wme}s*ufP03QQI2tTF+Yd@`v*>=zE3c>Il+5dX;*Huw<;h9q|m| zUF#$2=RLm16aB2}9q&8w`k4Xu@2QU`3*7V5+>YeF&w6I4pBc^cy!dQMJ)$&HkCsvD zQAOU4m$$2}x6Q3*E#tjo7M37tHt_fYNQD_Hlm z!>!+US-(G3_qzJ?rSI`Ndn#D>v2VDCTW>qX?XuoJZQsE<_G)Ndx4wJb15x_9vA%7` z$8(9~`jh+JT5=5@upW_Ld~WTEtP-#9bGaw1Y2QmwYKPVLe`J z^E_rx3OKvPy|!n=W3PPg{$X$9k>yLSIFjSYk6nsRd#zK#h8?H%eV)F*`+Z@xdv_-G z9^dqSn@3wRxBqj$d-r>1yTrbFp~HvmW?g&QPv1ryi9J`ZeN<#spu6n53n$O^w`XwJ zQ;x-yiGL?`qjzH(sio!qew}xnXT5uUn)~~;>ejc;y$-1{Yt^-KJbaD%{XqC)k3JSl z73ov@mQpH@z$r>+y`Xe@e2gWtzxDez>-T#vD4peru~g1<_qX28h}&kpz1M#FOOy`# zi%zAscIuIVK3Y-dw~sys(&sg;((Y-L4)VlUDhImzTW<%%ZL{9q>(D<%Xy}b| z|EljLTX!_+Gvb=jMC2=+Q*Q>ik(pPK}cEv9G>OdGco-v7~0@vA^}tGIHhX zRsHgPfBJb~zn``QwB6qB%Cq|Wxh<_Yb8~CXji2VCCb>qpb9+i#*R<#_vY*p~JW-9>NyaeIA{lec#j zO;>zX)uTJkWqhOFZ`<;F{nmV_ZnF;}zS{B8{32I7XKr=wVlmh7fBOi&_HU2i9DVC! z*5z^?alf5z(GodYUMxq;94jyIF0`(p1>U(@X38;Z>XG<#>k(Yv6Z?+LCtHu;*iE-+ zf_2QAdUQNV9kWh~o8)~{j#(#pNBqs`xU@zi621NZ!!henPmeT4Q=d7Qk)6b-+%8{Y zw7a+UzcN}@j3#&!Jnh`=(il~*QF#*F32BVB@zm0fxZ0?7%aL1&dOlMjCRWbXi*75V zb*ql&>Ux8;(|mQ}Jl5Nib*ETwzij96c>YJnbNTRh_=vk{#Wi#ET zW$vOk%H7V>zwdEo=%==zCPgn%OMkLj&!^pvNp2+^JO2E?zpz*@swjw zbxfH~9aEoHrs68Eyl?ASDq+5dcG=}CFa_8nQ4{0~Q#MPG7cDbL%Y%c~>H z^6JRa_Xy`RlIt%=mcFmlq&>3C{2z`i)5~S_y_S`F{KS!E^`!IXCcWvI+9Eb6ChM^N zTdQ=nZf7q!wmkiC_JY6`eX7Nuc;~0BtGn(wQ+ww1E%Tloia7Y4_rTUIfADyixoVfq zKW2XL?x)#49a!swnh|+^fA46EN;7X3dS~C+JU4r+(6{Zzn;x8uKk)F_?)$@wtSB(F zhws=j^+@jD9b2yVu1|Ap87s$@tG%n$Ep1JjW6M?ERi4%E)z+;~JqwCirLLFb;Vaee z2f`Ov$Cjzj%Y4U{bJE;;^lMLz5~izTOYY&O{KK&&pUvrVY&lJiEvKd&TTXe2)4_jt znsRK}2d62=mM?xDU6EZZr}7*;y1yJ-_LF1FzA49+eNvqEQh#GocuUJE&#;?X$Cg~W zM%J+1aIxXJ#M$Q{#)8(%jVun|8Q*C&{HPOp$ ztR5lF$S8S)l+Vvg9=8j53;nCd?W*#)UDjLHQ_fv3&Es|%ZyEJ^S6S;^=k|u_$LpwE zUZo?dT5@E}Utfg`R_7_r>v0Rsm%b+BQIBsNPgW20tDkY?>d=whBYTCknzFlgkslI^ zZFSmW>pgnDWZTEhxc%IkdZg>yPpW+|qH*`_4Rbj!R+~QcerCUzUlv7O475GmmP6lu zW>5UC((ayfj{bT)^T7P4J}PG2W)tlxkBxh(jDP=r`^K%mKa*+l@VxIHb+yfZDSyM> z6-P$rcV6r{z^_9Wl%`v>QI7XE$noBLbvfcww=e6+?B5<~F8SNBg*dfdE1D7O9%=GgQM!d=(!5rbZsEu@uN9?RG}JoM)Ry(pe!4{? z)sg1NxKZ9wa-=!Z+xKr`ho%)9G05BHKOAZHQAc_I^lYf5h?PtK60z;P4gQtbY9h9& zx0$DzyLlS1O}tG#P2J6`bFGawQP96^u-m)UB zTb5SL^U2VKMPI5opnK0bsx+9Xz0S+mRz0_ zg)Yo)$whYP!pzpIobnk_N2D%wMC$Um++o(|`T3&{KgsA#-La8@>U$IPQR!KARGPky z?`YJv=W>_*GwQ}aiLG<2XfJ&|=<8|B{`sE8^-A=Z)UnXRW@p+L*#AMd3lMm><`)z1yqIZ6BK=UVT&e>g^6>3&yT52;^G`|E34 zi`1iR>MJGx?s0#ncUqdq{pxazI>kH1Gu1s+-%3(m{haKb?3v=8!mUKT`uV25Z_l8A z*T<;CtYg#{A5Zn;{D2o;L+blqUg;bpuXGNSS2_ozywd4=Ehp_Ooo)X9IG=Jn+Dxvg z0!SPj2O4GVA$lxKV|!}Rf#d-F$1=rz4B1s zwl>FXZ% z|9&8RlXd_7;%!B%T=&A!=j#7*^tn`yKHrg}&m}2GpNn2{^f~+QDpQU=r^sh4^_9&R zZ!NCKv1yJz$IH>@I63+pn{xD-n4)sD`WutN2c$Xr?3?E3vuB#4&u(dsKKrPn&pz(H z-o8GS5q-Sv|Mpnk!}@P&k3PG2oBzYnX9th|E+FeZ%6ff91X@R*UU@8+&&5j~%Nu*E z{j10Fn(|n#Zcpkp8*iG&@;I;C<97RQXS}jm+g(hHNO@)R#Ye{i^601^SA0h}mE@Jp zit@^4?vz(H%X-WGkB;I(|MIxpSlzCg-mP9}mu=OcWud)4?b1GAfL~a~71K&ZUrZh{ z`Mt(hCr5L8(T_9zZ{6uLuGIFhs^weX>r^XeFMqRImsxLJocwn7WA>Ha4{Pb$OpzRO zcYd0?*5XM`j#k;Wr&vqtcAA*>wVgqCE|nn<;d^Ny2hFB}tQtB&?E9F>sg&ga0q`S{5se(T}GouWhCtUq;5%mUAVyC+l;fUOuqCM?zk2R!5XgKX3;KlZcjsq=6}%UwpsvdwwZeDWi*K5RskN#+o@6L>|@d^Ek<}Fux&BCIaziz)WZe!LwgIX-?#$(y3rY`^6 z&L+3I-7H)n=iD}7)y5=O`S?h9-@;Eb7Ce}4r+UotAJcs7$S22s{PRWBU-z58E| z{T9iw-$FU|Taa?>_x4MU{igqiW50>&9HsrLcG_dVQE86-66M%$v>f}5N;&o$k#g)e z+`2#Qljhj3XPRTbu4#__-bi!o*Fzoq^>Fv}_O!0K<`F%-ZT|MC+Qs^BDUYhwcYAj9 zHvWfWzqZ!nSL(4}>f@Ig`IpD9mprQ0_g4N_kE(8YRITZ)rM?zeJI$kN4X^rMa!)Pm zTo?8h(T}E4h5qrC#|ZV9n)a2)-2d>JP3o~>lpOWEDn~sT>vG&v)LZN?$A%4(0@mbi zwl{L{uuT{F$0VI_VJoa+&=WNUii?fS(7vDERyTTS08`# zW0m`_-znm~lc)doBZH%sZ)vc$mA;LX%-uLC%yr&4QL1`g@3YOftlQ-auT|>TU~)N^ z9J;gpo7m&G!=r0l&eiBruL{T4wD|dO%RB*J-#niy_Rr*1&&OYky_h*qiGqVd``l5t zlmGBtnrr@Y1e^A#aOvNU3Kz@kkcR*luC;jE9aNJ*x z3MZ(e!U=H`)pu-LkFpUHyu<(IcT8Hp5u?2Q{=-q>5Kp&%JSyz?UylmAdRzS~zxBm$ z8}-%gw(6_f>Rut`yE0z)w(+!a`@WY%-n~I36B7Rd}b1eT4 zep8PSy>gu9k>j)yDX%%!^3?tx9U-24;`d5{^uHQG| z-lhWq**awQ4zq3}e|eqK^bGG={Ob8LlP2`-;(ojFZcnGpubk~U;%2QIr`9iC{na3D zm-oAk{=CJ3H9wTjeQH)ziST99>Xo}wyvY3buH<)DT3-EJ{EM&mrng>glxH>S)y5EY zoEqXu=T2uCeD-M6&Jb_vj*WDvpCr_;HvXVqZG86Vi{1M2-1QtEnY~h*LHQ>&`S_Q> z73XfZa~!mX6g8h7d9<-vv!+2U>e%IHQ2p&6tDjL0nPb>&gY{2|zVJUkd%y|x!?J#M z=huPijh|6p{n)IZpSd)`W^-hYRPWcxR!9ALKYt@h{m`;wc$j*>UiJhlna^^lW$ZW3uhG4UGc6D*hSJVegXJ!dj|5TgVC$IWpU^7hpp1~Zd{$xh;wEE}5TxKbC zIm66bLF&i&%^~WC{WF{2t3Q*)9G6S|K&=^+U;Rj}Ia~eYdUi8|y5@42Z>XNrOjhsb zGAD-HYOAB%Tc{Flc2yrSpZQ%Ln=Qhess6S|vvoH04{DhH>gSLPm~X1Tt)p2( zU8$YS3YPQ{ox{|dS$5}Eb&b!qJHJt%!MS$l33c7gvpYAatLrVh zGq1Xi-nKh!>VnR4xa)I4>PF?tg>Tgkha*^HnNS(dKc4szqsqWjI71f&uc4t9< z^~3FU=W6xQAK9JR)d?Qkok!FeYwqXVsXoxBe$Mvly!_^HmQ!cqs>69fUES9l&Sdp> zUUxYAD|a^>&N=FOx#@6bP*=t+hqJW0Hf}qdJCvF`4yQwXgu4!BQT6fS{hbxmnW*FM zEThhKU4Q2&o6T0wU;TsCHd}pv=S}rT8u&YhtB=>v-?>n|Y2@$hr#@a|e`k7if+qgX z^M@*K0F>=OOihn)^Fl%4G|Gr~Y~Jmj2G!>C}(#`#YPfPg`q$XD@ZVZ1r~z zP-h~O;k>IZQD(!rQJsk)hO@4^u7?`V+UnCe%y2GL@vPx&sL-A>oCB1<^M-S^f_A}h zo>u22$#5Q1XYgmkIZ9nizZlNX)Ok5>I-}K9e!_GfQz!q{be2^g_N3{2s6OSVOy@au zmcBEcnbfEFwE80|es4M(s_X0r)0stG=rg7>Rx#Qc>|CI(x{rgMm(+*-B-nXKeS}@X z&fV&-UY_20QJH)76sxgHHczFD0W)H&;y)%m{qu>G?-i>i|k$m+bO zuB?GsojugW9F*0$NqvODS)KZy^Ba=Yxm=xzp;?`a)kPVW)j3sN^TV?`TdVUqBCE5R zx(p+;I%lhEcT`sA7IpH`S)JL`6`7dTSyp|7G3w)~za@5wv!nX3RhKyRKS5b-iL;G5 zFEy4p_bWX$mpHqs>$BDpr}|fwY_*p-m#S-`{^!mM>c2Jk+!?RlBwTZ5Rv)3=HRoz| z!P;MQc2XufTyvgNAEDzlXLfa#I$d+lR+r(8YtF6e<8{6kSVmo0eKOi@f$fyuzWSZ| z>a_jzJH6DWy}y2EygK~={Z4}Vj11K8%urY3ApOoQ^|vIdPif#4^@qpkcQUBIXRLlF zkGe6A)9;K|HwRbk_0A9K6FyA8Q%7AUb(d)i)c?e!UB5FP8Zv-?^l&8B@RWhx!~k^*ig;#|qT%>{OqKApMU1 zM>~V{JImFn)DKhG0_UjQtfnoh$14POsmIP-i29e&?+EGa22n=8M12a>KmB71Y@yD)pMK{vb*<`uEYOOQGJ;|4M9te&>n$p!!b*-c~noyMAYdQtPMR>8;L&KAkPdqt2^;FS}#8+QBo` zZ&B*n2pOT?$*Ud%12U>pr1RH3)ZZv*R8pUx^wpwlMxiW=Rr9y!RWsUV6qcDs&5}0b z6`8r!jIkL-Wad({l+7qAGpCxb*^FW`bEsL`W)zp1UClB!qlCMbugc7-W;vS? zB{Pef(dukP%g(H~I$tGaXVP1pu^8E5daH9*O14XHb=F>!ol$Rf-b%~Pptm}6Wn`z< zTb;YIvP1P&XRn;>bb71vS6+6A+9lQbs~|gAZ*~4E$_~<7oxe)51NBztud-~X-s=2S zk!|X&&R?wT0KL`ut18>jTb;jZviOc63r zrU)4%Q-lnbDME(G6d^-pijZM45i(phLPp3&$Vk};86_Jbqh%u`Q8q%x$VSLm*$5dY z8zJLmBV>YXgiMr;kV&!;@}_KrOqPw1DY6kVRW?GV$wtU@*$9~-8zD1gBV?9rpO9XT zmFn}Kv8Z~aHhTMn+}1*7n_7+*@|LkuJ^Wfi-jtT0WFus=Y=mr)jgYOf5%RulgnS?yA=_jlWV>vHd??!|WUk|&`uu0y zrw(m z$bOk3YVG z$Z^>SIUyS%-^xbFN!bWFB^x2%$wtU&*$DYwHbQ=ojgT|45%QyKpOBr7E9&!~v4T2? zH9qzUX{Zi=jh{>{M+>=NTu}$nmXIVlsR;R5rU>~(rU$~PW(>QWI|AQA!}36O zPPNrxc@R5?+Ul@8n4Mj1byyz4&Zf3HEKkSIsY&bLCPD@s)Y;5TNUwuBpIHc@I;b<6m5@#cbxyMpLR8St zaIzDEbx`Lt2O&rYbxv~<0(DU5G#A0CgF2_V38oI}oaP|}=%CJNUV@>6I;Y_Te;w30 z%|~$Ppw4Lo!A}MKTqlxX*Fl}r`~(Fgv%leIcj%XXU2o{8I1al{(E;^RgHgb4YF=8= zD|Vx=dNssSRD{!uqM~e3RE#Z(inB#g3AQMDl`V>**rF(!Es9FAMNteJMWqNRdX0dh z(gYNhA)u%%0Y&8qC@N1tQ3V2uDiTmsiGZTY1Qb;vpeUArqN)TGRU@FNIsrvB2q>ya zKv69MifR*36h}ajo8VJa$nJPs0ddVyFUA;!MbR1cdXC|-o7$IFRM&3oP_QgT^*FsK zs?Qch4cMZnAzKtRVvC~2Y*EyNEsC15MNu=hC~D3|Q40c!S`tvyih!cl1QfkaKv5e4 zirNxTlt4gHI|7Q@6HwHFfTE5B6m=q?=nVpjIulUTg@B^21Qc~6pr|_mMLh^8>PbLR zFM>}|yxnnD0dX}}uhtoLMA0pEh-37&o7$IF)ZcFWss6jAXaJ`dMFZKQXb@Wz4Q7j? zA#71Jlr4&eu|?5vwkR6G7DXf3C>ljT(P#pS5(y|8LqO430*b~FP&A%^q6q{PO(dXb z5&=bT5>PamfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P&Au>qB#T<%_aC0^|d=9)Qi=w z&icT)pD6l7J(3yo?56gm6)mtE)zuSnOVL73FNzkiMbTomC|bf6Mendh(NeZ3TE-Sd z%h{snUA8D%!A8+a0*Y1>6ahuw5m0oRfTHgS zDEfhbqB8^({YXI3PXrX5C7|dW!KY}K-LY8#ab?kPJ{3iY>T7DodAq57X+^)-jc?S; zK$fD5oL&@NVvC|**`nw&TNGVki=yAyqUb7H6kTJBqU&r?bc2nen*WI90Y!fjQ1py|qUQt@ z+5A$T<@=ta*$F7}Blr|0*&X*45SO2RvG8Y6R9b(1%Hd~fUs{prXJjrYikzHY6a}(H zQ4m`c1+zs_2wN1TV~e6twkS%^7DXA@q9`L9MJ@u0!U!nJL_kqy0*bN_P?VK`qHF{d zWhbC02LVMn2`I`%Kv8Z2it-Rpl$U^_Z~}_*5l|FCKv5(CMfnLRDnQ`As2~AFg$O=H zhM%Ln0^*8MUl2C}{Cv;!8>*KQjlzDW_N5gS^D|l%7DdH5y(lWd7DcbJMNt%66h*T| zQAxHaieZbQQfyK58e0^VW}~PK0YzmAC@M!lQF#K2DiBaqk$|E~1Qb;!pr{G~MX>}F zRVARP8UaPs2`H*TKv7KsifR#1RGWaJI0A~?1QdA)DDo0e6i@IeD&przR6tyj>MNZ_ zQBhP)f90Z%pQ(LmMGgFncZ-OkhMZm$HDZgR#%xj4ge{7ivPDrdwkT@O7DX-CqNpWX z6t!Zbs5JpauM<$zhJd2B1QaC@P}GiqqV@z7bs(UqBLPL72q=1kfTGR>6m=n>s4D?Q z-3Tb^PC!u)0*ZPPP}GZnqTU1)^&z0BFTtm%o}c580^%yAUK%p$i=xNsyT*)uex~-N z6%Fz;t`rkRgE_q@8p0MuL)oHe7+Vw#XN#f{Y*93lEs935MbT)sC`x3bXbb^GV+kl4 zM?led0*WROP&AQ%qDcf4y-7gPWCDt&5KuIgfTC#x6ip|fXa)gAGYKe~ML^MP0*dAk zP&Ai-qIm=qy+uIL+XSDY0e+5<;!4p~{i@?YQ8Y79Q z-eHTPrEF2Oj4g_mvqjOnY*Dm=Es9pMMbRp@C|b=%(Ha7Z))G*(j)0=|1QfkTK+y&Q ziZ&8Zw26SC%>)!}A)sh00Y&cDnMMnuJIz~XzR|FJ&O+e8%1QZ=7py&hvMc)!obdrFg zQv?)!M?leO0*byTpy&qzip~&F^dkX9KM_!LmVlyj1QeYopy&btMM(soqR;#s3ltES z{(mhu_K2cr^=+%h&wi%%r4{|^XM7wZiY{|{QFMhZihg5@qN{9Cbd4>FuCqna4Ynw{ z$reSo*rMn*8%1{rD7s5PQ8EEV_XsGuPe9QF0*W3IQ1pm^qQ?Xj{Z2s969S5!5>WI9 z0Y!fjQ1py|qUQt@*&On;9YuBmiu?#Dau87DPe74D@F}|J=Qyu`xT>ia7>!G!sJ#Aa zY=FbmzOvrfTDZ^6h#nF6iGl)egcXL z5KvT*fTBVK6cr|*=oJEriV%E?oDN6+(n`^L`X!=3hwqtwi2C6Lqo~8wzOs!l*r4FZa45>Ql&fTG$26vYuxOw$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq0*d+(P}HA*q5%Y-qJ|E~Rt3a$ zTz@NcBT-aAzXUnZVQODm(NKqRqM|4o#_2`TaJDEK!4^d$*`jC^TNI6Ei=srfC>p~S zMPu2bXdD|w;|VC5KtRz%0*WRPQ1m7NMUx3AnnFO)R04{o5l}RpfT9@$6wM@{XchrQ zvk54gLqO470*dAlQ1li7MQ;;OG@pQ?1q2i=B={5!b~qj?ATB?BKs`hh)zyj?IZW+K zD_ZI>vQ`mA%Q(F#TFw?l@3KYF3brU($reSc*rI4PTNJHfi=wq`QM8VYqV)t6y+=UN z1_FvU5>T{>fTGO=6m21(Xe$9l?-Nk;0RctZ2q@Z4K+%T;6n#WM(GCKNb`ntZF#$!N z5Ky#>fTB+cDB4Xx(Pspoq9qPTMFqswR)0129Z}RWT#Y>rQ~T12K6e2q@}EKv5?Giryfgs51dY zT?i=ZNd{-*Y&6^-yWcEyXLk(^!>jbe+U(QHwa$QDIo*rI4G zTNI6Bi=y#tQ8a-qiYBsAG>L$sHwh@3OhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q>CO zK+zlmislkfG>?Fyw+JYDn}DME1QabGplBfhMT-b1T1-IE5`s_BFn>pq0^<5zO=Gwy ziqtPbzTi=rcJQS>ES6dh%YqGN1P^c7naea#j{->^l|aW;xh5K#0j0YxVX zC^|(z(RTzCohG2@djg7nAfV_B0YyI&Q1lZ4MP~^pI!8d!c>;vW8WoL_`9BdTjB%ml40Y$k9D9S@XQCw2aRQ1;5K#0g0Yy;+pQ2F1@mK+Iy{*47 zExqA;rawi$kR5H9+Lu=Jnqg#bE{aNXdQnt{EsDyrMNv7nC@RkuMHSehs3KbwRbq>x z%4|_og^i+E0*a~yeKv5h4MQ#F$JOmVZ2`Gvupr{T3 zMRf@%sz*RkeFBOa5Kz>RfTBhO6g4KGs0qQRD8_J9RzO_c_4i$u5=DFTi$_fjQ~T12 zS{g>%mZGQ?rx!)7*`nxmwkT@D7Da8@q9}nairTS7QG2#1>cAF79oZ=AL_pCS1Qc~9 zpr{K0MO_If>PA3OcLIuf5Kz>UfTCUm6!j*cs1E@}eF-S)M?g`30*VF@P&AN$qCo@{ z4JM#y2mwVy2`Cyy@F{9;IL0d=t||Kau3LyAzl>@OH%#qID;jMWt6PhrL{2Y?#;`@v zShgq{#}-B7*`jCyTNF)Xi=s(vQS>HT6isHMXbJ&EQwb=VMnKVY0*Yo3P&AW(qFDqK z%_g8|4gp1T2`HLJK+#(S6unJA(R>1m77$Rhkbt5^1QabMplAsJMeh($w3L9NWdxt1 zk%r?-1;o`&f8X^eQM5)YT5g!ymsYgOFs`=|MXNczC|bi7MQhojXdPP=t!Im(_t>In z16verWQ(FrY*DnCjiN0C6m2D-=zRi;J|LiI8v#Yz2`KuIfTE8GDB3|l(M|%2J|>{( z69S5M5m59g0Y$qBDEf?mqCEr@?IoaS9|1-C2`KuUfT9BgpQ06pBSTxIC`7|qDT?;% zf0^^3VQODm(GkOlZYPSq5d?k0-baC%YHmMw}B*rKQ%TNJfti=qx}QPhzwiaN1H(Hm@0)R~QH zC7`Gq0Y%*jDC$8#QBMMjdJ$06n}DJ|1Qhippr{`KMg0jV8bCnNKmv*e5l}RkfTAG; z6b&VyXcz%S!wD!FK|s++f=^Ma07owc#MMjx0}ri5Q6>E?Yoh{8?Mo{f8(_@rA&SOv zdQmiXdR~)MeEt3=smV5+Q1e? z8`+|06I&E*W{aXNY*Dn8EsEY}qv!(yinb9@w4H#W4+$vxh=8IU1QhKgpy*=)iasHr zXcqxRpAt~Cn}DLv2q@Y^K+#?TiuMsuw4Z>Y&j~0xKtRz!0*Ve1Q1k`Cr)YJ6B$>??}C;`E~EYqlu*hAoPYvqjMfwkZ0REs9REMbRm? zDEf{qicYgp^gRJZKM+uKhJd0U2`KuBfTFVm6rCfW=sW>M7YHayBB1DJ0*Zbipy(n2 zMVAOD`jvp9%LEi%A)x3t0*bB@P;`xeqU!_{-5~fBeHq}0RX|*4_1DpkilXrjHEsr& z+Lu;zH^6AuUlb*CdQo(bEsE~5MbQJcD0;{iMUU8`=rLOq{mvFePuQa9DH}z95K#0d z0Y%RUD0)snk)c?n+@}(73FpZmoMNvggFN!L$MNwt8 zD5}C1MX_vARFy4?s$)FRduSG-8H{qIR5K6t!oIq7H0P)R8TUI zplApIMMDWF8b(0TZ~}@(5KuIdfTB?Z6pbdJD3Rb()W&o)S3q2i_1DqbilQz0CCD+R zseNfh6HH_12vIbV(~F`>Y*F+kTNF)Zi=ruPQ8bk;il(te(R8*bn!y%DGubGbML^MP z0*dAkP&Ai-qIm=qy+uIL+XNKNC!lBn0YwW5C|X27(P9FMmJm?%4gp0=2`E}dK+$pn ziryulXaxa9D+wrCML^MNf=|&n)3Ho1*sEs7#@sd2|NwJ)vczG-;JiJ}LbUKBlKi=sztQS_KCihgH{q9<%o^pq`%{$Puu zKiQ(_85>2<2`I8T<(Vyt>;x3~5m4kHpva$qB7=aU00N5C|4F^?2{nqG1QZ1lP!vQ! zQ7{2TAp{hqBcLdhfTHvS6lEZwC?f$yE&__e2q?-#@F_|*9eorK*HQiC{+=k>rxj&( zn%b9El-+5}o*;^HaC%XclP!vJu|-jCwkXQO7Daj4q9~j#it@2VQ3P8QMY2(ppMatQ z1QZn{pr{Z5MTH3{dWC?ZA_No_C7`Gn0Y$|LC@Mif(W?X$MG;UGO+Zme0*Yb?C@Muj z(Q5=0l_sF53;{)D2`DN@@F~jbbbO?MxWWr4IN6-OXZo}CPZE`Pn%b9ERM}~KKS>l- z;q;;?mMw~^vPDrfwkWF37DYAKqNpZY6xCvjqS|ax6vsx9n}8w@0YzQ{isA_^^g5l~d0fT9Kj6g4EEs1X50jR`1fLO@Yd0*aauP}H1&q80=cwIraZ6#+%92`GA< zfTA`8pQ4IR#~%uatEGOXUr7{wn^}#vPE-5RiaI!r+*3qRM@}z_I{3jSka9(PU09il(qd(Nwl5n#LAI)7heE23r)(WQ(F%Y*93u zEsEx_Q8br;qIm=qy+uIL+XNKNC!lBn0YwW5C|X27(P9FMmJm?%4gp0=2`E}dK+$pn ziryulXaxa9D+wrCML^MN0*clUP_&kSqICqHqKQt&n+k}lab5*yk|oEG+QJq^TiK%MeYPn2fGvu)u|?5#wkZ0LEs8#3i=rKD6zwFS=wkwk zJ|UoJ7Xd||5>T|8fTGU`DB43n(Ov?I_7PCDpMavz2`D;1K+!=0iVhJ_^aTM$hY2V; zLO{`%1QZ=5py(I@MPCtoiZ(bMUn?N45A`?6ZWKi&^p``vcADCkR`jjYxIIf0o#gbQ z=oDKNea99>r`e+Dd$uV0fh~&8utm|2Y*F+RTNIsTqv#v~Mdt}9x*np>}(YI5m4kHpva$qB7=aU00N3k0*agj6a^Ac6huH# zFabp&1QewspeU4pqVxn5Wgws^BLPJ&0*b;2D9S`YQDy>)vJg;|mEcqK!0BkIfVjrw zQ*a)NqTKq+A=v^=?Mo}l6=)29OBChi^r9#aTNLGGi=uG0D9XncMGDs0|JT~5>V8LfTG3(6g45Bs3`$O%?K!JPC!u$0*YD^P}GWmqSgcy zy-q+;8v=^j5>S*tKv6q_Pf?XX$7Kb?HAX*(#fl>RBe6#NKvVnDirxq`%tfN8Gp83t zUD%?iD_azGV~e8hY*EyMEsA=wMNu!dDC*4?MSa*P>PtXTKLU#S6HqjOfTDo}6b&Mv zXfOdqLkK7uNqQQ8bOyi=ydlQ8a@sie|D!(JZzo zn#~qPbJ(J2E?X4MV~e7<*eH6NfTH;X6fGd2XdwYbiwG!MOhC~R0*c-tplB%pMau{% zT24UGy95-iAfRX^0Y$3_C|XTG(Ha7Z))G*(j)0=|1QfkTK+y(*PtoK+M?VF`Ra5`) z&=gU$LqDQz3^cVbt!QhYF?XpbdY{vaq7T@jXd7D;ZD)(3580yVBep2o!4^e3*`nxU zwkZ09jiOxy6n#oS(QX2YJ|m!L4*^Ac2`Jh}K+%2ziasZx=l}sl2MH)TL_pCO1QZ=6 zpy&tzMPCw7bd-RiV+0g^ML^Nl1QdNkK+$o6PtoQ;$4&*r)lPrk^%hZ-L4RrXM4+jC zX+_@!8fTV^qSKsS6n)PYML)1b(HXWV`jIV)eqxKFvusgxjxCDLvqjMbHj0u6DEgUz zqF)Fox=29LB?5|mC7|ds0Yz5`DEf_nqN@ZHT_d3AIsrvD2q?NqK+!D%if$87bccYV zy95*^6Hs)IfTH^Z6g?pL6rBuoJX1hiwe`!@r$o^beUS7p(A2)Pq9=hy-j$;0DW?}j zf3QW-pKMX|j4g_uvqh0DNS?WiB0F0Y`LRWjgDr~u*(fpyC<-8;$Rwc1NkCB`0YyOs z6a^Dd6hc5zIs%G92`EZWKv4z)iZT*VfTD5)6qP5Sr~&~+6$vP+L_kqx0*a~-e2Q`hIi@Heu67zu zo*>^d{a5wZ^kaie?Mo}F5oBywD~f7zdQnu1EsAQhMNu4E6uH@=$io&zUbZNTXN#gb zY*AE~jiP!46xAo7r~v^*4GAb}L_kqv0*aatP}G!wqGkjXH7B5`1p!4Z2`FksKv8P~ zie4w6s0{%{Z3!q!AfTun0Y&WzDC$5!QAdJLQMDk)aRtQnwSEw*E{Zm5MV*37?Mo}_ z8f4sEFN(TxdQsG!EsA=uMNv<-DC)%)MZMXgs1I8d^<|5qer!?HpN*mc1QZPQ zMS}?_8bUzPPy&jE5l}RofT9ru6pbXHXcPfOqX{TVB%o*v0Yzg8C>lpV(Rc!iCJ<0G zk$|E}1QfkVK+$A^Pf_O}N0#@LqHg*tAYDXJy>K%%&E)i=Xck)( z&1Q?DIc!lhmo19su|?5aY*F+!TNKS_i=qW=6fGp6Xb}NLiwP)NLO{_w1QabLplBHZ zMau~&dY6Er6$BKmB%o*&0Y$3`C|W~6(OLqE))7#&o`9nF2q@Y>K+#45iZ&5Yw3*;j zG%d){S^;tG4pnfbi=xr`AZbgGseNfh+k%Xdn?=!fPA`f+WQ(GY*rI3$TNLeNi=vO& zqUaO0DB8sqMW3=o(QY=1J|m!L4*^Ac2`Jh}K+%2ziasZx=l}sl2MH)TL_pCO1QZ=6 zpy&tzMPCw7bd-RiV+0g^ML^Nl1QdNkK+$mmicSzv^eq8JCkZ}9?*}b{P(WOH^D8)ih@y)6#iKmIruL;3MFbo5J`_cfoL&^=XN#f& zY*AE@Es6@UMNwh4D0+o0ii)sBQBk%iD#k`paRQ1;5K#0g0Yy;+6h#wIRFZ(A7y^n) z5m59R0Y#+=C@MohQCR|t$`Mdho`9kX1Qb;ypr{f7MU@FCszN|fECEGT2`H*Y@F@xp zb_`HJT$A;8hU5$OJ=1>_sYdl+Q~T12Y6lx{?GQzAoL&^U*`mn97DZmRD2iu`qB?9* zRF^G^>aj&peYPlSz(!F+0*V?DP}G=!q9z0sH6@^^839Gj2`FkoKv7Eqidqp+)S7^z z*9jT{^ zfTHCD6unD8(Fy{JRuWLOih!ck1Qe|yplB@tMe7JCT2DaHdju41AfRX?0Y#e#DB4Uw z(G~)Vwh~bEKEbDGX0W4{0^$nM-*-Jr6b0$yq7Q;i?Mo~ADA?%ynJC)9=|#~_wkZ0T zEs8#2i=tg@QS>QW6zyh=nw%#Ul34q zn1G@q1QdNqK+#bGijEOb^c4X`UlUOD4FN^R2`D;2K+(4Z6rCiX=oA4(-w{xBn&4Bk zJ=if#0dXD8rQm!hidN`5rtgDI?Mo~ADcIPwR}`J)^rGk-TNIsVi=qo`QIy0MML)Ae z(JyRKbdfEJF0ncT_>RE1_4Dk2`IWnK+$aiitZ3l zbeDjlWCDur5m0oWfT9Nk6g?!M=n(-$j|nLHoq(bz1Qb0b_!ON9c6_UVxR!(~I6sOa zxBjuBKY~r|ODnR4829#zB72BDlNUvPY*FN3iz0uvC^FchD1a@BOtvU;vPDrKTNDMc zQ4~x-Q3wG==?EwaC7>uh0Yw=ID9T7ck&A$$FanA)5m1zwfTAn}6lEo#C>sGq*$F7h zK|oPX0*Z1GP?Vd1qC5l?im^peakeNb!4^fYvQZR8Kv6USMI{L+iXot= z6ahuA5m5Ah*gF$Ao9h4npF7vNGq|(dvD|B$g;BOKGj>AmYz(uR#g@7TlO={`h7e^7 zMJ0qJQj#qcsc4lJrCqeBR8mS=LPg8}{r-I3ue*pZ>AU`a=JA-v`@CQ0yg%#ne9q_d zId|r^f&hwILjXl>Ab_H_5I|8o2%zW+2%xAv1W?og0x0ST0Tf*c0TgwD0E*lYKv6OT zP?Q1z6s1A{MQIQ;MfL2~YY33YU->`J#M$*qe-FQ!O}7U#UrbR~yLs~~LQyxw3q_gm zg`zC@LQyt+p(qEwP?QT_DC!PhD9VE`6y?JgiVEO^qCyCus0Rd4)Dr?I>IDH5^@ae7 z`al3hS3v+peIbCNt091*YaoCk4+K!u4+1DEf&hy8LjXksAb_HQ5I|8e1W1W+^x z0w@{`0Tc~^0E&h}&=hsCTbC0ckvH-dQHD@7oc}iVI(snl#T1ROn=kDUibf({D7qfL zP*e(EC@O<56qUmliblZ~iblg1if(`}6peu|6pe)sipD_zMK?kKMdKlWq6rW{(M=FQ z(ajJ*(L@NKXc7caG#LUYngRh7O@#o8Zh-)bra=Hj(;M zt?-4Sr{N1l&%hUoo`o+IJqKSXdLF(|^a6aLXd8T?=tcOTXgdT@^b!P6^fClc^a=z} z^eO~Uv;zVtdJO_7dL05N+6e&^y#WCfy$Jyny#)ajy$t~ry#oOhy$b;py$1ml?ScS` z-iH8+c0&L~dmw2%zXR1W@!V1W@!F1W@!l1WnOiyY*=TB(f*J#{WbpGOCjEhdr42Vv4Mx<|nkD zT{St;Fe`)xuJld#LXi!=P!tSbC<=iu6jg*T6jg#R6jg>V6xrbmMWOIPQ5XbJ6b=Ct zML+;W4hWzq5&|fy0s$0Ng#e1GK>$V7A%G$$1W@FH0E%ir07W$+fTCIuKv8W7pr{T6 zP!t6L6h%V-MKKUSQ7i;dR2Kp$ss}++WC^tfy+;(?!=Jkj3e{`0?MzWzXfX4|6g3Dn z>%A`&HAK9OMUCJKMUCMLMNQxfMe*>3qNebLq6GLtQ6hYyC<(q$)C@i-Y7PMuwSWMM zT0#IttssD+)(}8Z8wjANEd)^14gx5;0s<&%4*?W)fB=d*LI6cqLI6dbAb=t_1W=R= z0TiV`07a<~Kv5b5P?Qb<6m^CGin>716kQf-?LvS=R^>m3y<8|Ns76jkXfX4|6lH~) zL-q(o*@zd4a^MR^x$uRe?(l`8JorLUK76650KQOE2wy1b0beNU2_F>of&hwoLjXm6 zAb_H)Ab_I25J1t@5J1s25I~U!0x0SS0TdNM07d;FfT95qK+!-5pr{xED7qE`C>jI- z6b*&|iiSV{MMEKgqU#`lqG1p~(QpWwqHdwqI|z`-1^l_|OrdB3Pm)SPgPAX;s5I1E z|DjM+hIpZ<9KKLA3cgS@8op3;1AL)q41A$zEPSD89DJeZM)*R}c=(`b0t8TW69iCn zGXzjH5dtWh1OXIHh5(ADKmbKkA%LP=Ab_H25J1s%2%u;N1W<96s?2+idI1YMXMozqBRge(OL+g=n)8@XdMJlv>pN|+5iC* zJqiI7Jq7_3ZG-@dHbDSIk3#@On<0RrCm?8w?hduq+)ET4;IU}FP&9@&vY!kMX1Z$kh@??3=W??M1Y??C`XyC8s~ z_aT6y-4H<09tfc50|=n#LkOVgBM6}AV+f#VF9c1|mQZUy0wgk@|KIgip=bcV0r?~} znE7IgJ`Xh~?GuW=K)g`&C48Z1KYXF+EBHdu0r*1E*YJg+Z{Q0>2jL4v-@+G)zJm{n z4nY7#-$MXJKR^IQharHXBM?B*Q3#;u7z9xCBLq-%90Djh0Ra@9gaC?uf&hwsh5(9w zfdGn5K>$UkA%LP^A%LRaAb_IZA%LPkAb=txOcv&#$O1uA^jWBN1pyLyGk?5spHNhZ zUxx&R1v6hvkuA)8)ssjNO zML_^X(GWmU3g#e1`K>$T@5I|9V2%zXP2%4e_Vb((gNTh`))Ml7o>96LG ztX&=!%zQCLjl;~)uY{r|h!=|D;R{7g;R{6x@P(p8_(D+pr|7RP;?~(P}B(mC~`vpMad9A zQ3?c5lnMb9r9l8i=@39sX9%FE3j|P<0Ra?sg#e1WLC_R646`;PKq9B{=dK$GMKk$z zNM=|t^Tib9hMD7z9u>90DjRfdGm|KmbJ}A!v%S!>nTnkjM)Bk)j--XgI$C zxjrnI`C^Jjg_-vp6pBV8UMRW&zECs_bP;@5*P&69?D7p&*D4GKS6wQSIisnH8MR!Bc6qSWppCv#di}@i|E)+#a zkuyImnE7Ig7KNFgeJ2#%i+G`EF?^xuKKMe>68J*VQuspA{qTjNW$=Zf2jB}u55gCU zmcs`{4?zG$DdEf~II;n6<(oqUa<3-1R*| zQECu5Tf>5xFQ(|ZFth#-LecYx7m8khFBENqFBH89UntrRUnqJBzEJcse4*$S_(IXE z@P(os@IldQ5J1uE5J1sR2%zW<2%zXq2%zXK2%zX~2%zX42%zX)2%zXa2%u;e1W@!o z1W>da0w~%80Tg`z0Tg`*0Tg`%0Tg`<0Tk_p0E#|=0E#|^0E#|?pecGL%-WRziQFGU z;5;i7^|6w(FD#h(Vv6>Mnb#c=ioQa;P;>ykQ1mr?q39d4~h;$07XY2fTE)iK+!P>py)>kpy)URP;>$UC^`uN6#WDN6#WbV6#W7L z6rF+qicUiSMZZD-MZZA+MZZG;MSnm5MMk(R+d+{90w@ZC0E(;-Kv4wDC`yDc6eYnIikiU}ikib0idw)Iidw=K zidw-Jidw@LirT;jMQtH~qIM8K(G?ItQF{oWr~?F0)DZ$Gx)K5?>I4B4xgmg}WC)-r z1p+8ag#e1uAb_HD2%xAl1W?ok0w~IW0E)Uo07cy(fTBzYpePFhD9VPQDQXgKt$l(h zTFoy#;)SASJiE>b4`#lYqWo~P!%sp{0pf+CLij>a5BNe+PxwMnFZe=HZ}>t{ANWGi zRq%zPzVL;jtKoy9YaoCk4+K!u4+1DEf&hy8LjXksAb_HQ5I|8e1W1W+^x0w@{` z0Tc~^0E&h}07ch907b(ffTH0LKv4+jX?6kQJi6qP~%MP(2)Mcu=#{RxoB z%KSDqPbhkgDJl;SX1$V5A%LP85J1tb5J1sw5J1sP2%u;d1W

    31ZCbXGb>Voq13M@f8=zAuaOe?{T}i63(` zYufjsPjL*RFM5*ryZFKMeK_n}C5CgP{2Zd&NQ@J|yXYi|y~R(Jm@jdR#EBATOT1p< z8i`vaJ|yuuiTgNG`G1$#ofb$~mr9%@aiPSu68B0xDDjBIX7qh8oW8BZLW#>HZj^XX z;w6br`r;R^kKPgoOH7sMk(e)Wq{J~2DoSS4|`#KjV?muS_fJy1F6k{B^YqFrK~ z#7+{sOH7iOEiq4GvBXgl%OsAMI74EM#FY|nmUx@QjS}yYNVf~4e7hu4cWmf=65o<| zNaA6MAsn017r}_8V5FnzixH0nso0ElG;t`t)}wmv)SA*ViZxX#R$`0ZHD06jFy4mP zqpZ4G>p^cU@4;pdwcPfv3w_2;vf!_7yk+Pp=vaKm>1s9q~t&L&^vgd# zRqEOriZqSjZ^JNt`FPAH%0QdiDtd7hwFUfOYZw`U`OTTAYqi7&=f_NOo}6DP{UQx* zYL4Ez_FI5~O|EHd^M01T^c`!wAwPI+I_bdU*3YA_WFwD{%RY{K9c?2GZE7bdzgXUo zAH24RbYOm;&ex5$!1>XX&7a?T+D01M)I$5I{dk*y@EQ#p8|C*?Kz=mk^XGSeKpNWA zT2p@Gxghd`{J32Qmam@j<9g-tMban>QAsy8=|K78 ze3u;A#t-&8Kni8x7sAHtjh-Fwarx&>`VA}}eVw1b{VtEDy<7Xh{cNGLh z9E&5`3coyu_B%u-_qW^!aeh(s%g039piM1{c;3nz@`L;c$wvD{QTcwtP86{pzEq~H z$MnQl`f>K9M+QmB{gV6Bc2bfv;BTKky+|b|^`+0u&`(Lz#Thx7>N}5A#yYLSBVTrQ zerPDO>Jz$XEvXkx__;p+<(#m)4%ff9#Br*<)pe?QZM)2j^FckY%WR&xuYPILF3-Mt z>ymx-`;rdV2RpTH7e7xqza_ac_M7_jb@aRUv-*Ohef662v-%>5BPEV8;=cNmvHR+S z^?mh6_Uy<(9{Fb-ZSqgmhK5$&oz1DYdG2=8o=K+DP1ClY`!Z&GU51xZJiaAsUwxZB zmoEH$DgSJ(=~$^2zpws~^Vr0zgS69MEU%1TpM6gmy ztJk7mBWJbeHF^!lzB-okTbjAjb7S_6?wjZc+N0F|? zW>MmUZHupDSAW3x`;+mv%M|3@i}K#$&pV~A ztS8qlUB|T7>JKGl)jd=F8lBCR{v1>5V&W%q>gWfJzdsv)yG~`Nx108jiYaMNd2W+zxS-h>q)AbK(mUFaJUH?%*`ssq}N5*^Vj?66S&@F2lQE-y# z(qPTmg_v!)-m3O1JH&f}bEW3v`1SN7+ACUAi)cU!0JvMOeZ-4x# zYs;xW*K4<#^xCY~pI_X1?`i$u8^gQwdo$hr#b0aJ6wldyvG|#5-#$0xjj_R2>J3a< z%JLOQf-=I^XuY0~-7~(+x_y6dJnp=|WcL?KzOapZuNQr~><{nEp>u*4>Dnz?du>T= z3gyl1GM3^;!q(^YT2gI?*Xg=Y3yFE!{dCsrbY8F5ABla+eWLWK?58|j8{8I7P+NGN z+QJE=E&R6ZQO~2nzL}H_nRSF(1ahFOj`EngxytVrVYI6T>ia_ z3nPZDsx;s6@MqVzZ~4vjla&Q z(T!B2OFT=muXA5#)Ml-5FQ_GF$z@J0IZKRvsC}20moN5I`L7W>-tq+=Z`ssruW^-f z&mT(jmQ5tJm5z{A$7(#OEu^YxzjE50mIDTDenP**jLH4?dBh5r$925AfcWtSc?lUU4l)AOvEaOb~o=GXb zBZ&8?_Z}}D3Y*E+`i_poCVN7DT}_J#saLH02BFyoxvRH{D4 z`KnTJsdK2*PL%BIyIyZuf|QJp>MgsH6rZC~S4fGn>t3aEh$qE4@i{ymzplJJox?S9 z4(WBTnfM%9Np4x^!ze`y$u0Z*AyP4to0VEeH!4S@!nCI+qJ?n>mb>+_CYi@jaiQ92-Q{~p2^g9o{aa+HGmKLT1k8OH& z{^$v9zPnUk*|J&2O?^im+C?m`&}yw~g0xrnXthaEPHpv1AFZv9nKEP3J2id2?*3f2 zYf3%ghihMNxpl**H$OCe^h1Y=C`|$V)@Zfr`edFDEBBVIlhTt)^OmiV(krz}O0U#P zDZNU!j1)5yOy_bvoy!u^T&s$=MWnbE7SSv7X`Aan@ivc~+2n9NsQRoXg`8^W)#;=; zCsm)5NpVh@M%`DEQuWC+jw7W=ZbN5MN{aL0Yd+TCZgUWm7s%bQQq$>2X&l)re*5{u zX``}7yGNs4`3d9^q;*-bXL$B-_Xv4aqgGe!$ucP9<8#kgNM%j;mw*{e2`GWLY!E3v z55-`AQhXkY!9JuoA7*eDF_;|Cj#BD^(}=Q1ScX09i7zwYYcyLEH_SZrjxv(lE!BQL(2cQ9T>Uyc!N zJ5Rgp_U`sH=J@A`m`4&LX*?0^jPWEIJRdsTz$P>I$db^aZ9886b<>%n%l^{(fA!3O z=ZZ3y4!?M@bF&1aUnQ0g&CqJYR%x~Ev=vLj9@T0w#_H0$*<%+vADj8?kl%wp*W-_D zqdQ8&2+n5ondZzbo-Ns1-COxyJB)i2{-sf9HH}<5@L1guzky~EhoboJzNii*w`3nH z!^pYX7*9WC{5@m*?a3o&=MDZEsy6gf#@{o>-=4-ec_Gzy!>H*$je2YR`S7TB=A;>P zN7kaB;2fe)8-JZVnvS07R^#6I%FQ})TfyA!@lMG;RyxH!)id>9IX$r~|LmjQs|_yi zq$_NV9p@S8E}+)nF=(SUS5oTnW@nXq=$>wn8#~sMFMBW(Os6NuLwERpww59~c9FZ- zQ~a;T9&mkuXBhR;g~qGhI;7Nf=-EH_Xjys50I-EI86Sni}z2G1ZZ<)(9)@us>R)uOoA^aA)mG+9Kh@vDefEjS`}Tjef5-=KOt+QgJ?)uG6Y7-b zmY*`l`41*OJHA)1$sbSkKK$73)dMevPa(E*wAwvQwAxDpnze2*{_k~vzO$j^t=79f z+w^1mhyETI|A6F^8J+5|>W-PI^-!{|P%E-jhcWrz59H?^0jD@!_LpC}6) zyQkEpmbW9~jzoD&Lhopu-Lk#u^g!)DkG)I&!`NG^j-XslCWU83cp{9k_oWLdFXYqz zG@$D0K%3v9T+50#Y!ChX=wBZf>}{{DF~)EdmpD3=-PY^0b?fmz^ywe;S-512XDhYh zJB7AhsVQ|K<#)L6<{4b<3ZP(Gfp2xQ6!PijV$oDaI58-jt&7LL3orCWqH_`mQeytiMuk@^> z6@eR#oYcs5g)wr)%-=ueqcQJHn&E3Y{l@OE@1Df1neTmjXyn6Xn(tYVy}-RNAg9@M zoHewLu+P7a;Lk07Eb^j!Fn13eKTj}9QS^_oXJ~x>zl=Ro>O$jVO5D_IVP5?qjmF-k zPu8z3^OmJiP2m3NEgM3L?_N2^n2BZ@{`*yST}ZsQtZ%>_EC1}X#>g*O(xlW~M?FxY zq{*f+Rd@f0x3gzR_V%(NZkk6Jb-<(5j>c8tW2@0atmMOYyta~y8a?#(wDjksu5sX6 z030W+4kR17tMPJ@C(M5YHC|4joGsZSY2NYG*WX9p^znzrG`FkD8}nlQCvb^og4HkF~x(X`7{r6{@f+=E0_};qA{3G|GPzA_n#Lo z+BYEh#^fQJw~P+{i{}PEfB)|N8#-(nUU%x9UAHXX^y^{Ank!D+e)P`d>)Kt|@_=VK z#&FYi{9ar>fefaBbJLf+=Y@BOE*F*Ov+sAgibtcAq>Z+(QK96{KOrdIx zNAXPdHFRz~hF4VcXn7Pl!^tsf*cjt`N%7THWBhzloR1pg=a9nKB!|ZMS&go=8si7D zl44wue~$47(-?nn_F&JDe;MPaoPMyD=L=5%by1@v9>uG2)zcak&lHkqM^@Y zkI6ku7kc$bY(#c>iMMi;T6u^L-x%-FOX9OTx;q+qock``(~(ps$+%zST|Bz!k;QSr2kC3{wN0MQ*_+*W7-i&H(B)Zj-Ca?cQ6qmJ~(--m;rXHS_>C%C%4<)*DE1PM9@aM^uctY}T|;a#ORWd6JtN z<@1=IuPo1fW>Gn+BtJFE=P^Gsr{+mK=I2r=#bbUh6{oDElsxL^oYXv|gcO%c%~7r) z#rY^TiWKLg6k33h&R~{vp*d)Fv3s~tXWT!l-rZ~TtM1GC)vP*8e6Bm4u05~P9*N?a zeZy*4N?j!Nt^*s5z|-o|y?l2ZNq5g+=MYbC8fPEzuascD`6>^MY1{)Fjjrilo~B0D zeX~2$nD=BXkFXOxfumoQ-kh08Eh33pMBwPRhbJ*R(Vb+RS882+@|E#Dj1h2xjDT%4 z0uH$xxJQ!Ksp^xj?`zQ1*eW}+o z%zxnga`Lx})@$PnA3xkVr*zl&+b45BNDLcmrp?-Q?)%B31y|p+s(Y^&R<}NVs@Iw6 zR%^mbtLNT%``MU{Z`Qghd+sgBe`f!#Pv_j9d)IY`6RH-fvDJ~F^2)2Jee(D&eDh$p zx0JUAWvw&fhsNKSGOo*p>zHzWDXrM=OX_>smCQd?n~`B7MmntPgOw{W*G_D_koNN>Y^+%G?BuPpR_(6Mgx zfz-U-kGxmcHTQr~|FkxBdSv{~Q@8#$Z0lG3_5QB24?O$ll)WE?u6*g-^1r$UpMUS+ zngi{9W3Jvj=0cyoUAHH_e#Ax<+k2pHJhP%FSNars6G2!^2l}5y_-R(aPmmsRBdxRr z>DJ}+Tq`KZ972!xf`Tj+7ELo9q69&?j$GP5DA;@hJzO>QqbF-Y`7KKf%d)W*DXTe; zO{+yC6&!5luRaM1w#;u%yMIiNpG@6jT(rCCU@ZMfYF0$s=3D4b$P@Gw(Gt9XHiJD8 z{Qpo{_VDvJODH{U(=8r)eilR~C9>=$C)n~P71V6`ke7SjJA}}+fr?om*O-n z#&SRH)6DWEJtb{!DQQoSI4$-z^x)5OD4rf0TZYmT_Li32R57hAf6#Vo%T}tzHkL@r zznz6Y?$O>7Oirw&j+{8lSUO4v%Nfco-eRGWbhK1PXj&&rUPt<$mn@g4QY$P!()L@H zZFH3VmLI9iZ(EwvTRjd~KBuxBw5+1@eaBKpM}OCP1#NfNt+`aJ1l_up_UfTqAFyd! zqHY~SrAgAQNfg%T*6~#1Yjx`~D(E`hdLz}{ZMyYgs;>3A^;1%}>(=L~+BWFc$0?VM zx^*KJWs`2rq1QI+)_18$cj(r;=|E?7>+2NG>DDXgImdb3+Jn>u-FgqzR=sXrN(CDk zWSvF_dNIh_p33r*$@(E({hv+N&GhK{xXJo3<$1znbr5$aP1e?w?iZ7FH&xQFChPlD z8^4*XHAKxRlhs5=IBl{%O-INHw(3-f++b^8Ds^74brD_t{9tQ$%B&#RI-6>DSg^Gp z9j`FhI-G(x*qTbmD+;zoQi9@OYbG%|JlHyyuI-3mYZU=DGT8cJOHCUUY<+|>8y##- zr|WWcuyrI|wlTrh&cx2+!PXioL^HE>3!PDOv$cu}F~@AprCOS6w!Tl9%`;nlWPWM3 zM$#kTugum2s>rX+)=bL!8?$vCmF0-pT1*A})@(gPXM5Ca9YR!jZ>8iP zSgiD{UHi~tJx`bXu*Lcn73m|3^?j;|k1bZZ(`%nttQY8vKDAh1q~xDjtUIWp$oS=)H<86-49g6q_rzujvbNKc9iG6 zk=A57hx;O}GfAz8vF;>5SH@VMqvTPYt>4iZMR&GNq_dr2x2~nK%(PnvP|2$7)-iP0 zYPZ>JiZYqyRhTIboVS5VE*w_D$* znpj}B?xu5CNC~Kbi|p2ZR7;EP)_t@~t=)Qzm{?-B)>9!;wpho}VO?9SA5&(jTdb|A zEa_XU9?B(Si#3ueBy)?E-o2*{-C`X<)mpIET1l@B+iU%Z@+>)SJwPp>^tg2_6}RlT zwSt%^KW@F5&SBhf>wQFB#c^vkox}L!)~QtL3CEj!O0Ug`*0m-V>11Z|MiWX~#T%hi zN!7fONc+_MKUCd!bd*)U_u-jLZiWO1WB?OX5EMHqhy@h|QS6GnqNrF<5xZEhAlMuB zhKgdt-g{RRd+)vX-XGi9+xcDZTJQPetoeQ(w~pj8nR{lEvCO1?2H{l_vj-*_*5T#wE-x~4zBWAcrU(|tKM z-}pWKi=H+n-58y2oSttio9^uy`NmP{U+~O)1$wz1Jj4POJnXWjm1Jm z{^g@xM+__#3&(G*pD)cprDBnoebQXIR4f{^cbbDs#bPn%O>>!2v3SgR(pv0L&^cW;H*UGh%%Z^hW1(_T8= zzm;Nl$~)b^p|P9uPWNx+*iCt-`?pH$j(Mm1H!OBF?{xo$$L^4Kx__(2F7i(IZ$#|$ zz0)I>PWNxM*y+2OM=YK0-|Dd&(jJ`d-^keIywm+#BX;`ucWW&ASH`4|f9vUqQ?cNG zzjwWL!StVbv1WDUgeD7Fx5&Sk_CF!(#nBM5e#{WELCg>`DrN}TFlGqZC}s%RIA#dh zBxVTNG-e3dEG8kF$0lTp*o15un~<$y6S8$|Lbi!b$mrOFY#W=9?P3!$CN?44$0lTl z*o5pDn~<@w3E3$&Av?z=WS7{4>>8Vpaj^;6EjA&$$0lTt*mWUmS0<;Af9pNzGgz@s zUC5j)WPCNt$wKxn@-Hp^Psl!TG=%IMGlc9HGlc9PGlU!vGlU!%GlWcx8A1+<8A1+@ z8A1+;NywqG37Hg|ki%jVa(HY)j)+ajk+BJx9Gj4%ViPhYHX&1E6LNHHLXL?|$g!~r zIW9IK$Hyk*gxG|f7@LrjViR(5Y(h?nO~|RS37HnVE@VPwX8QQIzM3BS6noW$9F)HL z7pGOToGj$5BL70`|Ad?!M?=UtF+<3?F+<3CF+<4tF+<1&F+<4om?7lCm?7k%m?7li zn1sxTO~@s&3Ar>jAv0qWa#?IbE{{#f6|o7qGBzPs#U^A{Y(lP%O~^H|3Ar{lA=kww zniFAv>jqM#b&b zEGG-OyO^CGH2o*!o;Vsp?u{8j?u!{h?vEKl9*7x29*h}69*P-49*!A89*G%39*s%J z?AU}n7MqaAV-qqbHX%>MCgjQ3ggh0Skf&o4@=R<(o{de&bFm3|J~kmQ#3tm$*o3?k zn~;}d6Y@%ILSBtc$ZN3)c|A5EZ^S0#&DeDzcUC@2AOF_h(*yY8uDXz)(&N4Iv-I3?U!J3?U!I3?U!K3?ZMy3?ZM!3?ZMz3?ZM#3?W~{B;?E3 zgnSj7kgsDC@=a_)zKu=Dcd-fiJ~kmg#3tm&*o6EPn~Crshyl}r)SYJol^J4 zqOqJVMA8*kzM3h@aeBVA)5G2lcAvD0x=ZJ$Ksa zVRGryLSqi;p7s+eIi!0!ztE6E zzSdblDCdywX@4OB>DgE`lq(x1Ahk+<09z^76>XQEYA6;gS2M4yXwh=9Px{pJpQ6Q_ z4@HaHp=f{|ik7fL(UNv3TFMSZ1MN^W$PPtI+o5Q%P0=y}Mav2lEhkX4yg<H6s;}P z6)jw@oSlHwhU6!i770bCr{{Bub;{N3D=XTdT-=dh{ikS@^Py-%I}~kXhoX(`P_&61 ziZ-=F(Pnli+T0FBTiBs!OPivt1d6s6DB4D#XtY4lwgN@l2^5VHDB512Xa|9!9R-TU z3KZ=mP_(l^(Jlf-y9yMI6DZnEplEl2qCEtP#tRhfDNr;)s4H5pTzNYIsePWFtt-|K zMc1T`-)=P0`^3MMnq}9Vt*WS)k}Bfubn_MN?<^hyaGkN1&aCz6wN14)K{RW zpFq+40!0f56!jM40#X~CUJx%jG}N#3ze(>mC>Cj`W?xy+ zfQDk5MMBXM&WEBU?NGFo9f}6pp=gjDik7xR(O^3iEn|nGW$jS3oK4a40!2dvidGOP zT2Y{AC4r)$0!1qe6s;mqG)$mqxIodW0!1SPidGXST3w)Mq(IRc0!3>I6s;vtw6;Le zIs!%O3KXp;)Dfuh|6igp($+C!jdyg<>O0!0%9iuMvH+FPJ#AEB;jR72&l z1f=$5en7opD7qzodE2+4ntf$O2R0O+r5_^n-{Yc*&WECd>`-*D9f}UIL(!pjD4Jx4 zqQmS^bhsUgj<7?~kv2t>1&WRmD4HTrG*zJJXn~?*1d5IoC^}A{=y-vm69kG*6ev1L zpy*_QqEiHlP8BGcCQx*mK+)*}MP~>UoheXsmO#k1UDCs4G$ zK+y&QMWckeq9rPo-4l@7Dfx5JlA&mcN*Wths@Ydov}vU{am7%yne(A&b2}7mVTYnE z?NGFp9g4QLL(w*NC>m{tqHXO^w4F`S7=fbg1&VeMDB4k=XskfdP690jV9D zzGEcvC^_eQZzGtXL8ZGv3{lhQU1QvB^#^RS5~xiy4YVU6b*Jh6fI+i zqGjz+w45D^mbXLE5IYpDV27d=?NGFm9g2q96s;^!w2DB{FoB}s0!6C|6paulT1}v6 zb%COh0!3>G6s;*xw3a~8+5$!E2o$X=P_&*v(fR^K8weDQ5-8eGplBn3qK$>RqJfQ- zO%ssXfPAGtC=^Z0Z^GWBv6_8lMO!o$2doo{wsbxeZDog|t?f{>jU9?c+o5P%I}~ka zhoUidDB9i*MLXCO?I=(*R-kAnfufxSigpnw+Et)voIufT0!6zE6zw5UG+v-+Pl2Kd z0!4cX6zwfgw2wg1z5+%22^8%wP;`Jm(SZU*6NS2>%^EA`Cm^+N@&oG4L(%tH(Ls&X z>?yL(!3TD4J}CqND6kG{p`@Q|(Z6v>l3$u_-!Mpy)V( zqT>aMP7o+MQK0A~fufTIicS$II#r-(nn2NM0!60_6rCYZbf!SjSpr383lyCrP;{<9 z(Rl(z=L-~FAW$@2s4F_8vGRTbQu`y#;?PiZcK*b4VPiG>%8D*&EXt!o(WTCZqM3Fm zy37tmm)oJ}3Of{CX@{b#>`*kz4n=y; z7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1wU!dp#fuaWmiXIZ`iY{)f zER=xM#&k_^W`v>@^E+lAZmecsS^n@LXp0q>JQ+6nN+73m} z*rDiII}|-Xiaro1`cRSEAioR+rPTnLGeeHZG`o<1L-`b(*J3AD8Z-=5E>`?Th9g2RkL($K6DEh^w=vRTF z-vo+&7byBepy+=BMSltu{UuQJw?NT90!9A{6s2#=z99VpH09 zfuarqMOA^KjsitZ0!7UNMV*AYqAwaNHzy#qvH9uhFGJD9e5K#HsAgYTQMaOaX|qt& z>U=1w*`cVr9g2F`p{S=FisrIIQJWo#+U-!(%ML|z+Z4?sP&BVVQE!2wJ_1Ga2^94e zDC#FrG`~R60s=+-1&S6FC|XFMXkme(MFff#6)0LvplES{q5%R$O9&J#DNwYOK+!;< zuBfG`{GNc+M&&oAbuH>w`or@R*@KE|_LUVaTNJ&v3`NU1ABvW@L(vdB6s=%~q805> zw2~c)hT5TMWjhqDVuzw(Hbuh)idGdU8X-`$nn2O&0!1SQiq;S)T2r8CErFu71&Y=Y zC|XybXgz_V^#zJH5GWcYP_&^y(MAGA8w(U|B2cucK+$GGUD4p8vPuF{>zBSIzgQ*| z9h9Fu+PtV{Us=)CMKNaUP_&Knp=h)ning^w(ROwy8e@l|?d?#sgB^-?v_sKYI~46? zQ?#={(Jlf-y9yMI6DZnEplEl2qCEtP#tRhfDNr;)plC0FqP+!*_7N!BSD0!0T46dfYe6>V8mrY0b@f%$#cTZN(r@=vciw5VoZSq3Ad}6di9(9i2_9@2^5_yP;`nw z(WwGO(*%l66DT@epy&*NqB8}G&Jrj(TcGG1fueH-ip~=#I$xmZ0)e9G0!0@J6kQ}x zbg@uZbXZY&G6AWrnBRAOcqkg%n#PQxntf$OmlefV+l8XboexD<*rDi3I}}}IhoV__ zD7xAXMc3G&=vq4zU1x`)>uri|5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ37x>KO& zE`g%E1&ZzwD7sgm=stm>`vr;~5GZ<3py(liqK5^F9uX*dRH!Suw5W6&lN3FXKmE)M zMMvaUKxP-!>?5@q}Gt%YCR_umCI>-SyZ#HtmxaKm^d~R zedl~A`rZyjKiHw@M>`b#WQU@k?NIcK9g2RnL(y+`DEi%|=nsLS{|OZRDNyv6K+)d< zMgIsC{VPyZ>JXRh6qN;v8U%_e0!57iMd_DQ)SnBWsDnUJRiLP&Kv9!GQL{i%CxN2Q z0!3W}iduxaqOXg}^aP}KOn$ohn^5#@estZnLpA%#in@0w?%O#O^>98E^|V9LTy`jG zvqMq49g2F{p=fS96wPCYqIvC5)Z3=0k3i9U0!4iViuwr@%`Z^2fIv}yfuaQkiWU+m zT3DcH5rLvb1&S6EC|X>gXn;V`5&}g_3KT6RP&81WXplhB(gH<;g}S2F4wVlRklLet z6P#Ly`j!48`77Eo9je(^Ry3qTQ5hGCR&YKPt!Rg$mF!S7)DA@}+o5O`I}{DGL(yB9q7gPls|ggXE>JX5plA(&qBRAI))FXMTcBtifueNw6Q?ZCIUs93KVT7P_(%~(G~(lTMBhW%XO$Ml7Q5n&0oZp4@F<*ry#fLP|d!w zqHQ}AYwsS4wsSrdjj=<~_I4=R!45?`+M#Hy9g23cL($H5DB8siMZ4M*jT0!^O`vFZ zfucPGipC2R?I}<+L7-?afug+yiuMsG+E<`xKY^nC1&R(3C^}G}Xre&TK>|ew3ltq9 zP;{t3(IkPQ!-Tq`Z8}sYBp|iL^P}t0q3H4aAnEW9)$A)PI;ul)>iAGJ#raS))ec2R z+o9+fI}{yjhoa-`P;|TkP(2o#+u zP;{0+(b)n;=Li&?D^PTvK+*XEMHdJZO&2J-P@w1{fuf5Aie?BDT_R9)sZdvRWQWSF z2}teg1rnUep=eV6#5A)*HT%knuIx~}G9eUQ<$NfbWrw1x?ND@$9g42CL(z41D7xMb zMK{=?=tesf-DFdAvp~@;0!6n96x}9Jbh|*&9Rfvn3KZQXP;|FI(LDl1_X-rQG_K+&55MQ;fdy)97mjzH170!8l$6umD{^npOphXO?(2^4)SQ1ppF(We4Mp9vIw zE>QG^K+%^1MPCUNeJ#`#J=vi$JOQblm0w4DDilqvr14FMYW9^C{m`M>`?Tp9g2RlL(%VcDEh+=MgOxy(VsR&e+d-*El~82K+(SfMWt$7VN+BV zC~6QWst6P{3KSIrMI8i+sscqF1&W#kikbzAItdhY7AWc>P}Cw&)K#FUn?O;kP*?O_ zhsrStNbQ#VI@jEDC%X0qPgu*G>;vM=Cwmn zZ#xwAu|v^(b|~s=Q`AqOXnujB1q6!v3luFVP_&Rh(ZT{niwG1gDp0hTK+)m?MFRwi zmJldfQlMxlfuex|MS}#2mKG=)EKszJK+&=SMav0wMLnvOrxTFcQTZvNp4Ix5{yF(8 z+VbgloF-pc(Mr|gn~9-lsPmy{WjhqDVuzw(b|@NdhoV*OP&C30MXTANXmvXjjkGCR zL!f9)fugkpiq;k=T1TL0U4f$Y1d7%dDB3`vXp}(Fh5|(!2^4KCP_&6a(WU}Ln+X(c zE>N_EK+%>0MOz6JZ7oo=jZjy#LbXymC@I<{e=b@v6fM~|jnUO=_LUWFUo8e75{h}Mb96Tu$9pii`I@S(F$JwFicsmrGV27d; z?ND@*9g0r2L(wUAC_2@qXqrILX#z#33lyCpP;{n1(OCjTXA2aaBT#g%K+$;uMdu3? zT_8|2U7+Yffuf59iY^u?njuhhi9pe%0!1?giY^lLubK+&B7MRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el2^2jnQ1pmE(W3%I zvjvJC6DWFIplFUj(GvniPYQKKS5+$?Cm^*x`Q7`oLeabV`J$())$A)Pdaha&lS9$- z&WEBG>`?Tg9g1GEL($82D0;;XMX%bS=rubOy>5r1H*AXD6exO2py+LZqIU#}-W4c% zPoU_1fuautiar!5`bePYV}YVi1d2WtDEdsG=yQRhF9eFd6e#*ipy+FXqHhF>z7;6? zPN*w-rdnAn0jb^AJ;8Z46y1^E%Kv?}ntf$OKUa%&r-Y(koDW66+M(z-I~4tHhoV31 zQ1m}L6#Z$3qQC4=^tT;~{;?_gSD>iWF)rIFDhm`f2ozNWiW&uq3W1^y0!3AUqK*PZ zO#(&D0!5t!iaHAvbrC3P5h&^^P}EJJs8yh-CQ#H}ps0sXSM+1GvUdVfJG4E)`6(1F zlV9NP*|C~^WktO@7N;E@isp7c6wPCYqIvC5)Y}e4ee6&)pB;+&+M%eQ9g60+L(u{@ zMg0Ye78EF2NT6t8fucnOiWU_pT1=p5ae<-%0!2#*6fG%Gw3I;6K!Kt`0!2#;6b%+A zT1KE~S%ISE1d5gyC>kPAw1QAq)Yh?bdjeAXt$%{k-m!kAzg+%Kq7^$zw4OlG z`T|882o#MHDB4hkXpBVrN440I<99LV>(u|udHZn$D;QMp=c-PL($H5DB8siMZ4Oe zXq+92cC$m#?sh2J!wyB`?NGF*P0<8_qP+x)_7*7GN1$k5fuj8ciuM;MIzXW4K!Ku( z0!0T26df#3bcjIFp#nvd1d0w5C^}rA=m>$LBL#{k3ltqCP&7rTE83xBWkdo}dur|k zXU9;qXeKqaV>SEAijM18j6Eq79q)W7I>8P_C)%OtBs&zHY=@##>`-*79g3#eq3AR_ z6rFBUbcR6DnF2*;2^5_zP;`z!(YXRe=Lr;@FHm%WK+$x8q6-CzE)poZSfFTzK+z=v zMVAT`%@ioQOrYp;fubt}imntWx=N@kI;LagxCEs3PM-wl*ibYy|46J^9jn<_R&-s* zV%904=z8Zv(G7Mey3r0rH`$@+W;+z!Vuzwz?ND@^9g1$ZL(v^JMRy7m-6c?Tw?NT7 z0!8-<6x}CKbiY8+0|G@43KTsgQ1q}s(IWyyj|vpc7ASg5py+XdqB#OZPY4t}DNyv3 zK+)3zMb8LzMb~t!Jez>jCUi`2t_?*m=Wi=|wqrH>%8Fj>SbR4v6usnpD0aBh8>FDv_sKbb|`w=rsy4kqIU&~-V-Q#U!dp%fuauuiaru3`dFao z6M>>n1&TfsDEeHW=nH|OF9nLe5-9pwpy(TcqHhI?z7r_=UZCg)fubLUx}xVhR(hP4 z6n&a6%U%dYqw-tUe(G4wzOtg^p72i z{F8j9Y`irSm1*;iIH zZ&PvTS)r)6^P#AZ9g60&Ls4Hl6!o)1(foEOTEGrP{q0b+pdE@9vME|vplA_+qD2LY z78591T%c%xK+zHcMN0}4EhSJiP@rg#K+)0yMS}&3mJujgR-kA(fuiLFiiQXjtsqde zqCn9~0!2fGx}v$8Dl-z0+Fbd^?a$LxztVp)zo@oyQ#Jd_idJnZ9y%u!jc`5`t!9U! z)$LF;(hfyy*r8}mI~1*DhoZIZP_&L6iq^F$T2G*8eSxA41d2up6m2L_w2?s3#sWo~ z2o!B9P_&sq(dGh0TL=_wDNwYPK+)C$McW7zjTR`{R-kA*fub=2McWG$?I6?@4Qr}= znt;?+$)A3PhoY_1|5ohSRL#D!qFtJb>iMB)SLZ{~I6D;WW{0BP?NGFb9g4==p=eJ# z6iu*0(Oz~a+S{gRAAzEM1&a0)DB543=m3GD0|kmE3KShAP;{_B(IEmwhYA!;5-2)M zpy+Ucq9X)~jua@GEKqcmK+zO|qNxH!M++1kBh(e`)KnRefYjRZmHy75Xz~2H=-8%e z_LUW#*i@`PJrtefd?-5E4n?Qfq3BdQ6iu^3(P?%lI^7OMXV{_WOgj{vWm9yvK+!n@ zMdu0>ohMLqzCh6h0!7mWiY^o=x=5htVu7L=0!5by6kRG%G*h7HGJ&GY1&Xc^D7sRh z=qiDtSpr2@3lv==)D<1yRM|HHsg2CvJaj@R+CRUhe{EAW`^t)LY%0#UC=}h~d?>ov z4n?=vq3BjS6y0WrqTB6IbcY>^?zBVEU3MtC+otFqfuef_itZCAx?iB^0fC|i1&SUL zD0*0+=n;XUM+J&z3lu#jQ1rM!(Hw!ICj^R~6exO1py+9VqGtq(o)sv1PN3*{p|0rq zrplcONNw)?zUv!8(KA`m3r*GRD=T`Xsd!^XD0=K@7v2o!xOQ1q2R z(bob+-v|_aD^T>EK+*RCML!4>{U}iMlR(kW0!6~HQE#v z0!1AJimC!d9R-S-1d5skiaH4tbrvYTE`AW z>)N4cJv$VwZ-=4{Y>Gw+6m2L_w2?s3#sWo~2o!B9P_&sq(dGh0TL=_wDNwYPK+)C$ zMcW7zjTR`{R-kA*fub=2McWG$?I2LJqd?JEfufy+x}p)ymFE+X+KKs#*lM9@ll;z* zotvxKS5~xJbMeEhP_(=Ap=b{~6pgn-(VliFnqY^bz3fo5w;hW1u|v_mb|~7XNucO3fuh3&ijEK{I#Qr$vOv*M0!32^?zBVE zU3MtC+YUwd*rDiNI~3h#Q*^&T(E|cS4+<1LBvACQK+z)tMUM&;%@!znOrYp-fucDA zMNbG6Jt?M{W#7Z#W-{-n2u}TXraV+YUwV*rDiMI~2WVhoblGQ1pQviaxX{ z`bePYV}YVi1d2WtDEdsG=yQRhF9eFd6e#*ipy+FXqHhF>z7;6?PN3*}fubJ-ihdL* z`bnVZXMv($1d4tYDEdvH=y##6=+)-R=Ltw{b~(X$Efn>urtwE}HT%kn{%$UsZV5&I zI3J4swL?*LF0nQ=n)rfuc5nqIQ9zUIImP3lz;GP&BVVQE#EH z=+EZLk_kxdlLZo-ze3TE`N^X`ovPVaRy2R7V$^M+XaVO#QGYuWEog_Lh3rtYupNpP zu|v_Kb|_lR4n>RGp=f|j(GmhhO9~V%B~Ua_plFal(b57%g9VC~5hz+#plCUPqU8mO zh6og`AW*cTK+#G9MMDLORu(8)MWASyK+$l4qE!WoMhJC9eLGe5Pe5w5{LYYmo$6Qm z_hnM6b*g4xS<#xEinHzrMQb@9iq^J6(K>c0TGtLm>)D}beLECwV27enb|~7=4n-T; z6m2X}w245`rUFHq2^4KEP_%_W(Ut;5TL~0xEl{+LK+$M{qHP6=wi75CBT%%xK+z5Y zMLP-epIe$aQxK7pVD=Qk`sd($I zP_(D>p=g2~iuSTY(cX3_+Q$w>``V#sKRXodZ-=4->`-)|P0>VwqJspA4i+dnM4;$U zfuczQMTZF#9WGFGgh0`e0!5PrijEQ}nj%m%RiNl-fudssijEa1I!>VIc!8o51d2`+ zC^|`~E84wNrF3^vv`&8C^&X+<#q_@wCwHo5Us=&*S5|a;r()OpL(v`1hoU>}P;{3aite^U(LHu3y4Max_t~N7emfLB zV27dyZHgWeD0*0+=n;XUM+J&z3lu#jQ1rM!(Hw!ICj^R~6exO1py+9VqGtq(o)sv1 zPN3*{fua`#ie3~bdP$(@Wr3ns1d3i2>WXgdR5>XDsjZTqb-XPU4a=XHUh7oNzOtgX zIu+MF7>eF@J`}xUhoX1wQ1qT1ir%+F(Fb-Y`p^zVAK9VkV>=XmVpH^~K+$IcMV|{4 zeIZcvr9jbF0!3d76n!I5^sPYAcLGJ<3l#kzQ1qif(N6+JKMNH7B2e_JK+$gkMZXIa z{UK2FKY^k@g}S0QI#pgwKxzy2O>o}y6)h|Jt5Y@m%8E*zi=Q42Mdi+MB_E0!>`+v( zLs6q0iV8avb+AKG)ec1+?NHQYhoWYiqD}%uodt@z2o$vl6m=CS>LyUsDo|7tDC#ay z)I*@Cr$EtM0!3{CMePDby#$Kp7ATrWplDu!qTT{UeFTc;6DaB{)D`{HsnY&PQZ#RV zzUbdjbX0x?q+jQ1_LUVa*tu9?b|_lN`B1d59f}sQL(!skC|b-8MT^^^Xn-Axmas$7 zl6ELs%BEL7-?wfufZJiiQdltt?Qq zia^mYfui98MXL%FjSwhWO`vFXfufN@UC{!aE88U?wX5<^p6TDYex-kAera}%&eiNI zD_W;>am3@HXkF(+(Ry|$THg*u8`z;}lpTsTv_sKGb|~7|4n>>Tp=eW^qRj+~HWw(` zLZE0%fugMhinbOg+D4#gv_R3e0!7;i6paxm+Fqb&2Z5p;1&YQB6zwEXw6j3bE&@fn z3KWeKDB4Y+Xm_EmXsynb%My^XNucO3fuh3&ijEK{I#Qr$ zvOv*M0!32(9i2_9@2^5_yP;`nw(WydR(Vm?v zUnU^6J@WgmCxoJNvZ867tJzmpbY|zG)6=2oEayYf*>)&8#|}m3+M(z?I~1L7hoTGY zP&C~RMHkwk=pvh76SB6Oh_|`F+=Cgre8;OS89i zu4Z3Z(OsR3jh+ofcRL@7?y*DBy>=+N&kjZR+o9+II}|-=hoXntf`>If4n`rsH;FxH-Vy7fufo~QFno&9s)%@1&ZbpC~6ZZ zY8NQ#B~UcCK+!w`Me_<2^%f}VBTzJ-Kv7?TqJ9EJ^9vL$Ak-C=yHpxpN{V*NZ?$gd zQolx<+#`+tU8>nvR`=6{P0?V1qGbe%mK7*kPM~OcfubP-MJosttte2ml0eZ=fufZKidGRQ8YWOQT%c%G zfua!tMXL!Etu9bBQlMxJfuc19iq;b9iWcfpSt|jly^t^N7Y;?u`4y10yHvBUtZ4l% z#cr>Kq79r6MWgIcw4oh}HnKy}#&#&$#12K9+M#GOI}~khhoUWPinbIe+Df2kYk{I| z1d2ur6m2U|w4FfF7=fbg1&VeMDB4k=XskfdP69nvRBI%DuJR|0!3E~6kQ`wbge+qbpl1#3l!ZT zP;{d}(M_uEO)-uZLU*`cU=ej@wMF4gQS zE4sH!vC_Mt=sxE|(fxKPdcY1v589#VAv+X3Y=@#p>`?Tm9g1e#q3AK2qQ?b_<_Hu$ zAyD+BK+#hIMNbP9JtI)`tU%Fo0!7aY6ulr&^rAq~O9DkN3lzN~Q1q%m(Q5)luL~5t zAyD+DK+#(QMQ;mrMR#|pY@dMC{%K2a?g>SG^Mj;!x>U2TtmuO-#pL%x(TC25qL1uQ z^sya^KCwg5r*`>Iz4n^H;idqGVY63;w1&VqI6!jD+noFRlO`xb^9U5pD^S#1 zps0^P(R>0$eFcj82^7sQP_%$RQGbD=1qF&066%T?TPj~CAhkR4Wm(ZuztSI@e^ltg zE!FHRD_Xpz=<-P@8sK~=TEY%ROWL7mDLWJmv_sJ#I}|N#hoZrDC|br2Ma$Y0EhkX4 zyg<H6s;{#w2na0xCZC0(jhqif z8{4616FU@bYKNlD>`=719g4QFL(!IYDB8*nMO)hxZ6i=LTA*lKfuijMipB^OZ7)!? zgFw-a0!3p5igpqx+F77z7lEQ(1&YQA6zwKZw7Wpj9s)(<1&a0*D4HNpw3k59-a=i` z1}&9?5|G--eG;5ep=hD}3dlY!)$A)PI-sRE?~71$p!1<FB zp=gpFiVm|w(cyL|I>M&tNP(is0!2p&6ipE*nkrCqv_R1@0!7CP6dfl}bi6>(2?9kY z3KX3rP;|0D(J2B&rwSBJ6DT@Opy+ggqB8`F&J-v*OQm)N1`QacpQv_sKlHbs{U z6kQ=ubfrMiRRTq`1d6T}D7r?V=vslI>ja9f7bvWa>7sWg6_6s@1%cYU6(XboxH(^Ad8vZ4oCiUq$7MGrb3 ziXO5<(ZhBqdc+PzkJ_PVwjGKdvqRD2b|{)-hoUEJik=iGdP<<^X@R0=1d5&&D0)ty z=y`#n7X*r46exO0py*|RqE`fpUKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)w* zE4r_xvQ7e0+p}+ibAKq>x{}8GE!FHREBd&l*yH<9^ojGK=ui@5tzYTioWD_av98tZD=S*EYw_F9 zp=c@RL(xDx6b-UN(b9G(8f=H6W$aM2tR0G$vqRDHb|@NRQ?!CW(TV~^D+v@06)0L+ zplB6=qG19>!v%^~6(|}ZP_&vr(dq(4BL#}q5GYzxplB_DqO}Ez))6RLSD?E9_8orA^UQ0!6a~imnzYx<;Vr zT7jbL1d6T~D7rzQ=thB}n*@q(7AU$!py*bCqT2+DZWk!JL!jtRfug$vitZLDx<{bs zUV)&x>mkTKx#{;SxgT_gY&Dg_jj#kUs=(^U5l>&grY~B4@HmKp=h=piXO8= z(c^X~nq!BeC+tx4q#cT$vP03+Hbu_}6g?|Y^qfG^^8!UL2o$|2Q1p^O(aQowuLu;q zDp2&AK+)?0MQ;ccy(v)imO#Y|leb=8mABw)PL(!LZDEi6{MPJ*Y=o>o}eQSrJ z@9a?Yy&Z~vuqpacpy(%oqMrqdei118RiNlMfui39ivAEN`kz42p8`dH2^9S;Q1p*L z(Z2#krEYQAPElE)s6n8pB2d&QP*eyMbr2}33Ux)FbgdkcfYg4>ucLh$ihA`*qhq&f z_LUWN?p9pT5Q@4uABtM+P}J29McwRB)M|&K^m~slNdJ_^awzI<^hyaGkN1&aCz6wN14)K{RWpFq+40!0f56!jM9A%UWW z1&S6CC|XpYXfc7J#RZB62z5ox-6{_zAhl2OL!nOH>R0-|WJODKt7czW(V%X{2aTa< zY3D=HU^^5oV~3(;?NGFw9g3E>L(vdB6s=%~q805>w31EHP=TVA1&US?C>kbEG+dx) zRe_=r0!6C{6s;~$G*X~w4S}LH1&Y=ZC|X;fXdQu~bp?vn6DV3=plAbuqEP}x8wwO{ zB-9lx)veN@NQw^3ucHkNMVsVTV>j+r&Azgt&ASx~S3}Vj&WEBc?NGFp9g4QLL(w*N zC>m{tqHXO^w4EJ_#@L}~dz+#i1d4VPC>kqJw39&5&H_cd2o&uqP&7`UXg7hP-35yF z5GWciP_(B&(FB2_y#$K(7AV?BplDx#qWuJl_7^BRK%nSAp{{7tZk6>CklMHTb+pYw z(Q5g!e`2?4_LUVK+O62LDHKg|J`^2hhoZynP;`VHijK5H(PTRm9c722DRwBDYKNku zZHkT&C^}Z4=s1C*;{}RN5GXoPpy(ulqLT%RP7x?NRiJ2^K+$OeMW+iCogq+kra;kI z0!3#F6rCebbgn?rc>+b}3lv=-)D<1vt#Wz-QXA1P!8s%peUlYU?^eyevZ5K?id#B` zqD!0)MVH#4Xr>*CF0(_?<#s5#!VX1O+M(zwI~2{bL($bXMb`)vT`N#@oj}p`0!23n z6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07cL)^SDNuBmK+)X-MfV64-78RZpFq+50!0r9 z6g?=^6`#n7<+9p>EaeD=V7at@xu$D0l3`u|v_bb|`wzrs#Qrq89{;UKA*LNucOufudIgie42cdQG6{b%CNc z1d84iD0)kv=xu?bcLa*w6)1X7py+*pq7MX$J`^bWNTBFrfuc`@x}rzARr<6fMQh}z zh#n0^C+1gUKkZh{zOte(yA{K_g`%&V4@FWV(^R@o^5sePM&e$f}9XxA=jbZV_;Us+Mt z*5c?|DC*{XC~CDsQOyoT-R)4+!wy9~?NBtA9g5oQP}FXRqFy#da|;yBBTzK2Kv8dj zqCNse^9dC76)5T_P&B_l(EsR`t^0STuTdUbuR9g4QIL(v#J6m4&Zq8;o| zw4)u0#@ZC^Bv7=oK+!G&MY{?VjT0!^O`vFZfucPGipC2R?I}<+L7-?afug+yiuMsG z+E<`xKY^nC1&R(3C^}G}Xre&TK>|ew3w1?Xv{sf&Kx%j7N7q}1qVe;maY$=5`^t(A zZ!Nay6^f2JK-C^|u)=tO~{ zlLU%R7AQJJpy*VAqGLuaK+%~3MP~^Voh?vwjzH150!8Nu6rC?nbb&z8 zbb+D^1&S^b>WU_{RwgANwZE$g&S9bG$2=}>t!7_Y(ahH3!g)f`WzL79%k5Bfg&m5n zv_sKVb|{)?dS3l!ZWP;{?A(R~6%_X`v~AW-z6K+!`2MGp%UJtEWyZTFt()qB*U_N4-PQ6V8XCC+$%5lpTtmwnNb~b|`w*4n@z|q3C%# z6un@Fq8Dw7UJ@vJS)k|@fudIhie3{adR?IC4S}LJ1&ZDhD0*9<=pBKgcLj>x6DWFL zpy&gEq7Ma%J`yPUSfJ<=fuc_Ziarx4`dp|hdaSk5u}@NT{yYiJ|5Gbk$6g3JI6#_*a1d6HxMI8l-ngoiP z1&TTe6m=FT>LSz?ebrjoAOWe(RZDQb4n@D^mqS`=)$A)Ps@00U<_|^PoexDl>`>Ix z4n=d>p{UIcMeTMd>Sc$bx$RIij~$BUwJGW?P}E1DXg-0Wz5+%41d8StC|W?EsJ}qb zf&xVg2^1|XP_&3Z(V_xHiwP7hE>JW;plAt!q9p~2mJ%o$C{Q#=plE5KuBcnBa%KWj zyC+|kwbtra`WGcU#o$^s`^t)zuNAlT4@E#uTGr6S+o5Pxo1zf{MXL!Etu9bBQlMxJfuc19iq;Y+T3euK9f6{C1&Y=aC|X~jXaj+w zQ36F93KVT5P_(f?(Ix^#n+g%L(y?|C_3H_MJL#y=tP^MlLU%R7AQJJpy*VAqGLua zK+%~3MP~^Voh?vwjzH150!8Nu6rC?nbb&z8bb+D^1&S^bD7sjnXof)1B|=@%5w*%L z2}td-G>aoc(Y%?|rL}7IRhp~RP%O}N(|~fRZRPZ+yVN!&{W#jjw#n&Ll8$XN(-*?d zZL?cTrEYDXrFR1KXj?qJ^|rljpY(T_x9yJf2Fku|f2T)T{o7VczoBN4w&VMiN(0)S zOE0$!Z0osDskBVnHj9)>L)tD`tW+A>_St|^X?WWbOO;Bix9vBmR9dU;uEC|!dTswM zTPkhXHgZU*v}xOkE0#)Iw!JX4R2tpZHmp?IzHQr8OQoIKX0BE$jcfa2WT`a1ZK<_N zrM=q@Sf^ClzwMs&N~MF^%A-o9No{LxR4N_WcJd~r($uz>HY=5mYwNXTsdQ4?n5|2t zX>FH}E|tz~`)a#V>D;zKJCsV(+a``Jm1eZvw{xj{BY;*|x)erP94^R~}F*J=pfm#8TVG5-S)uYrPA|l z#pF`y<+gRFluEC+opyAo^mf~8$CgU(xAi`uRQkAW>`A54=WVl2DV4r%`)*pP^nKg1 zXOv1mw;g&`sq}l>L+6xAf3;W7Pk;X9_VuUd_lCBgaZ&mRl-u8!kv;_F_W5R}k3qS8 z=gZRvq1=AWmFc5UZvSCc`Y@E+m%lcB9Lnwax7qhEx949+zDT(}|32vf<@Wpwfd`h` z^KW!rrre%?CFhWGd;Xn@L(A>?m*NdCx98t#wtBfe|5~cG%I*303awXe&%YRE!*YB6 z%^sVU+w-qx*s|Q7f42VUa(n*a=-Zdu^G~%gXKf+m)^=x99ISxwhP%zhU6Ua(jNq_pRmj z{FdE2%kB9+m-m+2^PA=#EVt)(Jv~}(&u?3qQ*O`iJ9xU>o?keAzTBQ)`FpwCo?p6o zz1*Ikdw;v!o}WB@zucam{rb4vo}a$>yxg9zKff-w=L?AM%kB9Q;Lqju{3ZPNa(n(9 z{8zcud};a*rMRsApIon|ZlzL(Wm@}IOQpFFYe^s2!JWFN+xh?gkG=N*kE+_chtJI9 zWCjQ&2@q;Xp(sKsRf>cZGD%263QcqfA&?+V5)>2#5p1A>s3@Y?3o3dQdjmwQDE6*c zt^zhh#Mr;}JNvgLlZf}i{lEABz2EbE!!xY2);YVcz0cnJOlJ1rW1_D0mkx1Ro$pJO zGs6es46boro!@RQTA65YpH+i*=l%HWKUex}(a@CEoub`@C9^AirD({bC7;mgd~$?n zcZ#+de4}VDIPq;4&5dbDy=WUH3+W$-Rtzl%@6P{3Z+E5tEZTM8m*d@KR2OLdTV0Cu z4uOA)ch`whngNbxb*&IGP{}Tg4z5A1&kJ}U_EnXEXeUnF6sm_M9FF)LzRrc zH>$gaDY;SVX1F0;!jQ7-1cxm3Sk`HHcYOlGkZXjwAa*0tlq#)Ea#`J6#o>`ZfArN; zXLoaru_H1bzGrARS4nu}eGe|%y0Dw8G(7U)n#(R-WX1l1KgeS z?GB^a5rdx1@;mXov}5csh{ulT{Pg!OL}N$fKJ&<8D^8vPK8O%;vH|}z4q}hTfyDa? zb7mUwo32zxRKAcG*HJt{7os z!fqz8E5(Xkj~bDDmKiBL@{3(B-Hd1u;pPKN&yfhjBX8UK&4*_>S^eXxeW_OL?Fb~b zbRIJ?YC)K(q?x~zp6V3tm3~!yoe<}|A2rpA-G>lTl&c$3eh`%}k-W^558V0SCZvLt zmp``rQPeO}e)F>1FFM1CXXnF-J}dSu4TRxH+Q*K#r2020z8x_mZEZIv<)Ym;EpS3S zRJwhb75gMU?;!8K6!lavyzM*k-Hf?YUHbG#_xXFxe1V$1$_eSts>^w-4LbEjOrRS{qWVbQxTi0*=0EU5e z-g@-TPaNw+zVO`63@dg40{w(QT}>dTn9DSxF^uTS^X~csfsohB2fgHV;@STArUy-4 zudcqfz>2*HVZw&Gtg4WBuGDze8qJQ#UNLaI6HR?}$F_*Zj{NfBRi?JC-g@RlbVY1& zOA%gR%9p(Q_9doFjXdu9r0_gwody+?zrH+iB5IH3jj8M}D~G&($(ug-3q1;i{dBthj9m;|zgUVoEB7%hbS; zk6n9Uf>R%x_uO?q!k|9xNPcjd6Zo53@BSUVFA8@j33Iv$6CU~8L%VmHk?P8qe%^qz z5$Mk$Z95~79r4@FwUe#b6b*AX!)*O!(|*Zic;xHfzOYvk3XlBb=apN%&bt7S-!FVeE)6)0Rd$nS1fgb6=AJq5pjQ(*YczMAKr= zt*~M@BaGC-*-Yp6yPsZXI^9ic_gpDf3Xj}+(OWWdBhZUozH5UK3iB5+!Tk)h`O};B zNan&LuX^DE8HW+*wQmltFk|VyUtDug3kW1BeZfFqzOdnSM?@1I`RcRZJq+)*!c4^(|2pA7 zvVV(aA#(i#tE-(NU-Zx4q-Bu(v$qdH4?y+{`$+%khak@QXM)K1H=fZ=)#wf}FPC2W z#X+f!@W=z7JhVe@M|Q;8gsaConc4f|V^6|JOEtn~1D$G+2(M>^kL$S}!E>?I*zuMu zPc%|^~o2Sei7q4Df7njLX+_scL+pc!}F zk{06>d1}VEW1U#;I&(Abg~iw?lOl8(qz!*u$;iP@EnRxet>?r1sHKB%22OTL@bm7S z&!U#DL>O`B7!wAbeD%4XOw~TQY4z_gx484xLvNx2klhFCFFw|ay%m9^?<{9RC%^jT z5GQMk?%CGK33Acer!GRfz#G?HvHU0W(HAt#BMfuW&!?d>(1dTkxA`SA>a;v{Y!@fY zHP5|$5j^pQ7U*k+Id)@vcm`oUc>eaMOqdRzUfSKs+P6QQ(ZPys)y|YBey|P&Tfe{K zD^vSVzq$$sD9&9!{qTi!HnhV%&-{SdYZnBP@{DDmKew&Yo9VC5eEGG6vLiow_U<`O zpf|31;$qA&@0iwj`i3Vq!YNy@8j&!cG0cI9FOGC->8#S%(AH?d1Fvs> z4@o1zm-lV{9WD3~!pP`x$b^x~nTVB{R77vQor-v5>8sBgCtUmCV3(8htZTm;<3#iQ zKQ7*jDeMe{5hDZ`X4%(IePqJ?c>eF`Ye@UewKsolTIj)_@4se|6@QTiauT`elgrOD zd`8?g{M{LR^>5~t~O{(cXz8ri{X$g z%hTTSv^u`UkQRem_@gm==^4z>?EaQ0;bAUMtKltL;Iz5S1<`v9LUlprea->q*v*^+ zOm&-Ugtm#Wh0EoSmLL)Fh%OmHTDC^w5_79)SBn-6akg%0d3?-Cixw?gM6?)$%iF{> zx+)S^h2%F%siqdKQG!aEZ8b{gY(tdoG)ldyJp$Pc`G{$Wj7rKKoCB1tW519zPv|%l ztayG&R*yulh{Fj>PFPkvuYn1ZEXmI7R!&Y(9P4ne;~~1NVu3F34sMPD@>|GZ z)(@`Y4RSOb^8}m_$Z`&g1?uoN*T|8xPh(9yToNmtB*q9x6cT34204;&xGgcbIdQlc zL>q*+%PJ9&)x66p7hr@XArY2Hgx5K7mkUVNB<_+85|6%I*d#d2s}nSrRVr{V=Fqrb z2(UUzL#kt}B%SM|QYs*cN-CurP- zcaHmQ5Nz+%>>#I+>Ll;zy@?%gEnkN^PL8h$u(yKr71;c;t{Zd z6_O`0u3Y;$h7U>8WBHai2|emGXUYb_ThW_gawkp1?_9&k9m3eL>xkIo)zCnagV0wf zFG-QuUXwhyer?qf8FR8GSxibwo>!4Pt#)p5?Yzq5d4bx>s=(ZNbLy%p>#C+ESI%2F zw{DIIl~q&c&#S5pIVacS>cPo#=he)rsjE4y%1W-DGpj1OVrJEX|qBglIEl^uGe`?K~!{L)Xc6;o?clQsF*h^IW;Aa9!N_`OAVx^ zh}aim-`R6!SM{x`m{QX>H6Qo7 z!ql4Cbs*UIg#7}Qb7sw&GdoZ*w+0$)U7DF4K&4b>IyyA;9NM!+k}{Hozu&f?2by=+&wXS&O7=joVayFAn5V}ta>mJJ6^7LB2WC6X|?NX zC-$-J?sjyShD;{fQC)?Fx3#0DItS5qlv4;MFiaC1X2&8SU!2`6+;d6TP&)?2ZQl(n z8HX+h+XH(f*zIG%wD7G>;d^M|9h!vGX-@d#y4gLt+c91K5=*o2;S!=9X0A@<9VUE7 zNi^S%@k?O5Y)QQt+QH;zn8PJEeW3o^+%$>pFOeKkktC8BB%B;C)ezJ9FvVgv|80g? zio@e@yN8t4snx`PQAzE?+oO3TBg2A4Y8s=dw|K3;1iSlRW9}Z>eByvKz4}P=(KOA* z{77T@ZVV#hE?ZP6_g?e<+mGsqDo zo(;eT8D=LScto7tGTf6ebh_OMtR=d-!C?*_lW2G93Kiq2b5?s;v>8B-Q3pFz;z-baD^7w`XCJ z-Dz~H-C6D!lJP#_p5`vQljk%kn3TUMN)A~sf5omYJ5mzsV8;lww)<$(4vlk8x=~?C zklo0)Ry9Y<9*ohZadCp*m_ zti$elqH){)ZB3a9Khi)*i}xPM`w`Dp9MGzj-xBp(DxvzwQ4=GvpkB!-m3CoIh$kBfHMjWc~B;!KI+%nV275#4dy#;v9$W|-#weRMOS|7Il|O|crL zcK^*B9bMdq%fEYQyMH^oJi1i=zk2oIYUkh2ypOK5N75l0oMYzYM?0%Ox*YxADD~0h z=)ZUM5slf08;@k+!p0bOw~kB0Y_obwwtHfR(gq8ZaF5&_WPd6Wmkahuuw!Gv^e*u? z3me>rOdzv*j>LSWk3=GKs_?|WTMh+74gde>)kjlWXDt|Ksv-#$+8s59yF?`J5~k{i zM^|-6lZ8lA;aGu0Vg(W_D-bqwLpBnQsx6F3Omt$JBh7rb5Q{}(2HN+pZt3fo2OEKc zQe$a$H*9S5>t^@uZg=bAl)*&9I?xRm_2^;3%MNd3zTM3)fn}@H)I5}s?DTb~wKbmC zeS{;9&xs~B)$VqjleyS%EV&yhm{k>Tr((N0RtgYr$746VgWb6`G?(2u$!>>I4#Hs~ z_Qugh|MC#K6{jUh45`?oYKLz2e;5toYkA~-c9>RLey|cvWfmM^TgHaR*xin``}DHA z$--YO#8zmECSum#zZ{7U*UL~Qv~)MA?+Kb&WxhU8%l)UznC?#*n%$q35CT~Y`X!14;Pm_91Ma9k>hSb&Z;PZj*`@P5 zSmzrrdoj*?--SJkmvcTQo|uiFQ=3#1Wkw+y*+jZ8lxUAI&yI(@lY+ z+Hva9({3-j;dngKWQXqvpCle`Z!eg8<4JuK`L`R9!sU5Btl`p5Dg)eX@;q zG*RCFiyMlP+R^OU1-G+Vw?}GAvln@Ei5=b5%+ZmA`XAjgJGweNf(^Ei2ejC_57}5d zy0Aytv`4bl_@DOi|HgK-`^4aLqrdIaN8*KsG9BI3|4DuQZ`x2ly3(?D9Z9MGM|;;1 zc>X`zkRI;rMjX-3M#IL^(QUEl90b!Ec~BaUDcbkGy6MjRsb7NKD;85Hy-6H?n%dU$ z<|6sT(hnZl-}Rig2%99bb#hFC-TAK%oSQr%?;7s;*nkFu^1_ueAMPJpL^+wt2zzuYvUt6oxA8dFZ3fVIv^eCqrju9H)b}!QRa{MGdq&^ zmI&*Yd}Hg5AC2jZ^)QC@WAW6@6p4G<<^tUl{QJ)WHHlXi!)=r0^H0n#@jqJwOZ6UU zJ;|a!KFL0&haKM;!ORW{gugp<57$qN{e6RJlr6j4@lrb`%9g2iyp-^75@_5&EyD|r z#$ChEH1Kg}DF7R(DgM`N*52;fTWU~}mTiy(Q+J0yH2&Z-+W*c?u9@c#Ybie|)A;j& zP3FpN(y*cC*<$BSw`Fq;`-+LO3#oVa!|p=5d*g2ia!QK>*(D_bf8p4S0)JK@qhwV1 z=BPU%Mm`aXmoKwb{VcLFZAnm zIhnbEDGe89lw<`8i^_0uX?96jc2@9AUNIsqFDxxDE-sQ2fnxvo?1Df}QOW3xGLs^r zYJB;~f}+g)KvqUsMxd~K^vLWIDMwL>xjKDNXu^d>fztAkrI{suxh$usyfDkTY~Y|= z2M0IGW=VEwaS?K8V(N!$SQnD_?2?SqkesvLMwgBXj4aQ|LHwouiP^y*e<_)NwA7|^ zjnw4Gl+cX&3j^g$c(7(JHK)-fnI#j7%ZgCsf`UMCk-xAkTZ^2g*Jl9nq5Sl;K%G;9 ztVY2{7T^>4B{@zrWEWfSztkkgx-?NrWKOdM3jBrn!CD*V&+!K`ik)0$78Mp| zXNp@K=jHU13Udy#)DorTnVE2DFf=VYraZemJCK8#3Z5#?DDjs~2vRZi=#0V%+H?(3 zIL%gCRO;j)3$6}kpudwoOQF~0q@sTWN{e!G0*x+C9o*>Z%#6Z7SxH7=>1cnM6LU#+ zM%DzUFe4iowxl!z5jjnb3RYt?&7#uGKxtVK>NFd6)HXDA(r067`Ldoe&jsy#9TMg2a zsi?kSY<_=9PDUU*Gc%An(y!e-vr$)chL$XU#;8D1d0BCJSzv5YK^gi_Fbeht8B}EW zk)bQ3cV=ae_2W-aMwXYFT1MXp9gj>`5;LQcrE^Ptgaj`ck1ic38k=2`Q&2RnX`&^C zqk_XGe3daec!9qdgPAsQF@}@S@zg0&DVz`-B-4TwHZr7gq=6ceHhvE|jfOy#1hU6x zW@l%GWLYZ&BWzg)Mu`0E34xppzw~mppnuDwrm6zZEeJrQIpV=_#J1&*MELe4^ zX~7PTu5LOY`rp*~vt}&}#_e>6>>_{TZo`x@4391-$b(nOKwbdZ^IW>1g9pyg=& z7=0=Z7#4L{TGVixl3_o1PRHGn?1F4(Y?jK(ZtNq|(o$wLra#A2ipjx%kW`#;M;b>) zIOlGrxoqSccKSd@W@dRwMy3v7!TjXnJ~u7{1ugTB&PFR)wbgUx)y2)9U0XAKcGc8i zK?emJJ~Jc_#b~zDl1x}DBeTpu*4%~$gxvkuPjSB8%Bl9%%VUpMyp@|*3IamER%ao1cE0svkMB! z3o=UJ`%(TpFSg2qFXFBsC^$en!J-sSW zHG67J#q5A|uV4UwK|%JYi~{Y2xbbIU7-+cjIb9%llL~3&)Ip6pfm$UOF@?;#vREuM zZWB-VWkhT;7KP3$FgiHB+Nqvk&q(dxC?fVKwpPe3zG!}3Rz+P!U@HEz{Ii{7d@WcR z{#-Fw_QT%y8thb%Rpbo0!P|^By=f^7N7}-vsd_uZ?L8PbM}?F?)|j$DR<60jH=Yg* z2)SNIw9y!|%1fLZmosYSpq@%|L&j@bx*%hMOfL0~9Ab@r>7mx>*H3fX$gx4|H)#Nx zA!K@7fUePC2c|wMWAx~ZhSXtD%)VG1=)g{*4V^qS)iH}U!zon@12t2vQHAAknS%$% z$zK5{rN+tM0jCT~>lb&-ysDX16}45z#`T?5Id}fBN{p6O3;NDVPlr%fJ%82|;Ix@@ zD(d>;kBEn1fS4)*uADaawElf-=k}eNIsi(=yvpif_^aa62KAklGz)*1eB9L9xyMbL z8`pPwT;HO!xW4#v)nS#$K;LPzs%mR1rdRcySv7llUG=aONM`)$D;*F_I$d4OoY{SA z@dv%YT4>^|Aa@Epu#q_(2bi0Y%z(28JHl2bo zS%RcD8dCgQ%=WvH3f6#%uTf%Nc&4(Ojmctx2&17YBT55 zR?Qkyby_LzkQH_KBlS`EYx8*(QuC$rLsyU?6X?-Ma%9o?Q1cHM^p}J(3vds?jatSy zr%KH@9UNIxQ$k19)D(0kR6^>&;Bbys3r5;d)iNmzXnmUyxbKE$C9Qv8UaE5jCNWoF za10p}9k(>B2AfRsb$D%jH|mF&ssi$d)>ZT7nK-dHJWTG)y`UsJQ?fb1;?RiU&_8=> z)dCX~t6t~8td&dg7wQc&Sh>SBO#QG<)~+t=ey4tLppq=i9SKu+=fJF29VsPvl{w3k65hKUVj4XLb<05YY;DCjuOxwK*B8C)_C&{)i3k*S)SMfT|8kQHF2 z>`8>)nk3($3)tLo*!IZG$AD}~)Tl?YXUU8x*bEdySLgp?9hl?KDQdh(ZE#suMyB&O z^o?#}!Lj_WT@Pz^RN5)h^Mctir7kbb7>oWQYw+NikV?%c#|j^lzR(rDOw?F)#!#cM zIx@4S;0edYGFdJvl#$1o3Z(wav*>Qp!LVFZ12wD?8!!IEgF*i@Bc;XufG*-C8ZJ6B zg0bP2!iZ&(rDaRl=hQUk>$MY(<~L(vq4n0I4agGo9Tk&K8<{Fnewgc$+> zd>KT;CQB-2@JPT}#{?HMj6jCTP>WHgQF1b}up`uDsqL6RQXK`a2PZ}ii?A%c=cZ!) z!lI!Tg1P1tJk<0~#b-KI#XLyfn#>6@N@aI0xUqvi6pS>uEX)|`?9&BLgj8fncG+R) z>duJC^}FQ6Ed883VP1qXFi%*#Vuk3>^gH*m;tbr%oU3p{G6(3NjV?D^mzlX(RA(1B zmtajDj4s$;a>fP9v3G{b)Ce^`?3}R%F>vUiEDJT44KZP-pj5`i24Bi0hn*O+aU1Oh zHkzXc=lopwnnf9FL94WJ&tzLU^?~V@sShmuLh3`7ud@CLl#cV4;Y`S_nQO$V3Q&+D#LGf2;sZnWvm>m zJjx3iW-?-TPKH8fz`=c@H0~40+L0B-$Ye5O&2Yv($)YUXcuD9w1N*Q3OpGBI)61NC z3SL!;1v2&+bRU8B7V>>K|5M)rlT|fk{&c5CWf{m!N>|JnX}o3jsCkAZ%)#mo3*kUc zK}KmqIG!yp7H7+*1GnFsEW(0qlbMs*&@QR63(k~uE5+O+orX4B_;MJ!6Yi`Mn~WO` z)6=Z%znP#)15d~DvbXKz%Iw&W&KMuaEG*MI zifmXrCuMVz1#&X_*Bhl-%kiS%4xbaeVGBGJ8*-r?t6>*Oif+0@qoF9cF(5Gp^API3 z;L2KS+S#3Ul0~K!IT)F(W)WrG$VpsqiX4pJxd+1%uyZDQ-(R1I1Sh*GDZyE3s@ZXF zxMTfgI7;OzBvp2ASy!Qj$?+Fp;ug9=+%R=1EzQ(tMU85RCZ}n!y~PqX|4_0Dm z;>_BHxnKxPbkR?;FvSU(`|xD&c@^)$W-Vh3iy}FzJnfnxB@8u7qX#@%^zy>|!lH4e zW}NjCye>}&Bwn-VU@k{uKO9f{oF_5PX;};LWXSBJ(GHK3y;Qw<$x6u)WV6*dFnh#u z$fZzf=sv5)D%<=y=u_P1Vxp#O9Hz88hiut4Uchj|01YPNeNTC*f$_V5fsCq&L9>dvR#Tb3$S^WjTXDFhiLI8Ka9s<^!hY z<WypY$LnUS~s9DzWiHpp0V7{KsP*-pKbM*)#QE`V-5;ZXuq= z)9R*ssLt#wCnI!f!w|ewvJ|pX!M#;$*W7aCv{_Ox$zn54$5vsmUL5OSXbB3Lqq7<< zR$+a%S+Mm&z1J{W%SL+WBQ9pw6x*pkRH;*ujn@wiQQ#>or+dsZS8%1}rFgKWE9k%M znaXx)lP4(+yPLQPh3u-NrZlWA@ep61%SrZR=@VR$F@2dwIJd*Yt$xKjVm_|uB$ga4 zV=6Y@g0;%JFdMKTpGh#w5T|lNC%4XeaU7mA%aisZeRRw$nFj*$oU!R$Lhg+6WS%1! zpX@T^$byW*eDvvTY}YlJc}Y>4Uf$3!1x0w0h!F<+x*3Hb+k(gRv*+a&pA zl+L#ZIyKd>ZET*Huy_qO+eRxU$t1c{IVy)GlxWO~$2sC?ZuVjW0WQlKamdXfwhst9BW?VCS#8MTZ3o+xrkeQJz`Ah)W(3H!~ zn8U=K!KC!>9^GmsGKaxgn^{0fY^k!%$;h1hSYbxP=Pslfo7P8hAo!qEs+M=ChB!<^ zjVmh2*Sl+Q7Ltl7zKm=k6We~W-O8{S%J>YY@e(fwo19!7$;U^mQJI;?#~mY2CNk#D zip!ogrE2O_Jfbb*SDQKyEBKYA$Nv4J3w#$gzPR;IyzuqTi&{mrw7Q3Uk*j=<>&RBe zoZEa^v*o_?yyu5sU|$$^k!OYb5|@=R7#CK^*P~jlWE|Rq`i@S*s;AHjkMxdi=4tMW z3Tx|X=Zf)kaCLNba&>lfamBh5T=?0gzq~@FFzfq2Loe{iw|IuUJo@dklsxh!o*^#} zzQ7Y-t{d_Sv+(`4@+GwTGUqP{;c|X1zAxOo%=r}j`V6_8ug15VlS}*`gm5`ODEOVg zCj3<)T+Yik44aoZFW)juF6ZT&hRG#<`Ln?>d}}YcoR@D2 zCYST_(}Lu3{_+qm=hp|n!?)pkedT(O6|5Mc;ElgZ*<%GOLeDq;=5J4v*6>)tg6sA8 z<&2P*#|joq&j$;xyq$A}xI+9Hh4vmA5?;!Z*My(cgrCxcFKoikZ^Ex=!mnw6qN z);xI$xjw}i%Nhjdp;SY3x`uBM^iflYfE|$_Yy5yK1&_$^CDnL0?}6XD6YMEJ!U*go zzrqMSMt+77c&ugNM_rurxq4oH->rFX`7uPJUxhF2m2fu;BEByK5#JJw3GU-8>pr09 zuPHu?E+Ne2__-G%Fh$TAbgqfYIIS#?mWeP_`xdSK6Fh7F*Zs3odkQ~tNsO1 zfAULF%~S9N^m_hLJug2FCG~e11`Y||3P08$*hg`Z;^&HC=;F;&@tyX9xNZPCrKGb+ z5d3yQq%U7QE_{n%AN*ja^5z&4q(0gU;(UrAt}j!4vg&86zFzf*l~2WxA>nQoOhP`C zKPZTL+NQh!->xp#T_%Y9-6)ufc2@jU&o{?dD(5>0;{4-+2)7@ zPE%YUDCHJRgMU?jSata&6sgze1QE~U7?TCx6GS{?F}_LoX@W@iJjHPM-;JM`M6+1# zIQ*!WBC_RhTxPlPvySnC-7E`D>*y%Dg98+YDUMVuRxDSnRGguBs^VhBWs0j5Z&18n z@e#$R6rWL)@lf*ps^Z&lcLrydpCDt1;(P&`&KMRB0waK&uJ z0>x6riHa49)rxZzPg6Wgahc)@#mf}0R=i&EHpNYf4=6sa__X2+imxiZqxi9++y|um z-zXkb{8iEIG3T2pwo!~xj8*KR*hev4@p#1y#azWA#j%PfDNa>9MRA_uLd7MD=PO>K zc!lD6#hVm2D*i+9Va2BucPQ>ud_(bl#ZMLYD(+YON%0Rw8}~;y>M=qwTCtO2yy7v6 z$%+FMhbd+$<|~#cPEeezI9+kJ;(WzLisvd`q_|q~D#ZC)bwn3j_YsL18T@|}4_EnVmgoHmqF;{Vn;zY$t#hHrp70*^Y zUvZV<)rvPN-l@1*@d?EpimxcXqxgy9KE)pte^az^!;*ZrQjAfQ`HtwvDyAt8QOr^t ztvFUOpjfSVs^S@n=PIsLyh8Ch#oH9`ReVHoo8pU#Zzz7K_=VzkiuH;vuPH}!#kPv+ zileYZl5&#j5WPQ}l! zH~f3W-ZvROP;u@phM%SQ;BAIKt@zs=hBw=2aO7PEixe-|WcU?|FW+nU`-*MvH#}Z( z;sb_HSG@iq!|zu70uz0ypC1(aJZ|`4#d%K}zF6_$Ervg%_{TQGTRd$r>luS%6fb(# z@U@D&o;UnM#r7{5o~StKWy5O}Z`@`0J&Jo?GyF%zq&E#8qFDE~;pZqm`mW*6Dq0^H z-cm8=Bg0D-SME0aYQ@(+HT+}64*xW~hvLa!8h(o6&3g_1hvL4k4F5?n^a7li}rxm;7w_HHvRwfhFzviDIWe4DY2l8GEvFewN~`Zo}_a z{5s6=pB2-vK$GiFP+ZW=@a2k6wlMrf#jsX}M=IuFV@JY|Q(P5g__c~}wKe=R#V#?1 zAFDV83qc7#NAdQ~hCiVAZCAs8RqPjMc!uH`35K7qxTU+{I~Buw86K@zaIE1I6z}U} z_*056D!wIXTh>37?-%TX{RG9IRS)ZHbf02NL6oP1@-B+;s`pWzqS#;c5z4a^{i>HK zAFp_l>eb3;DxRwPBIQdIm#e-?`Q?gNtA4BE{fb)@cPhT8_@&}OMR`~tpqVmv~|oOBAOmUZwb=;-8A?`2BYY zH%;*j#Z8J2DQ;1GUD1nQQkQUT6tff;C~i{xRIz=3bA6uTV#UphUn=fbOuz=N#6LiB zhGMPat%{E*Zd3e8vH3s~K3cJ-;)#lL6mL>|NO7-XSNuA(q+glJ@fwDE(-lAmUZQHt#qyD26r_EAhxY-Qno zgZhb5?5K$4ilcW|JVr515z7PT{4m7~MNHcry+CoS;zUJETb=Xs6&EQkQN%RSIe&@b z6^d6YKBV}VBBnFW^*a=ID!!`tzT(G2S-P@bP)D+ zFhen0u|Tm{ah&3bidBj=igOj~6wg*%s(7K|#fobcuTk8r_^{#@#qEkODeh8yNAUy2 z&lUG5y4|K+&i*8P(MoxgVkgB|#h!}271I<4C>AT0DNa(Htmy1ZBAuDa>l7C#E>U#$ zCvn|%%5PNMsOaoR;{1ckA649@xI^(}Mdw#ias46XzbHEUj?lwBrXE@;Mk#huboL){ zT~Fn`71I<4C=OQ~shFo&sOaoNBA$uLrzlQST&j4UqOn~G&jp7Ey+Z69qyif5# zMQ8sJ;h$C>F23)C`-}P?;P@KbXAXX%^@7JUmOCEvAl0p;+J&>~Dy9JI<{7N!5&kr@ z&PsCr$~I|AZLO7rzurs|G08l0Jc2*xbAn8j55eQpI@9JLHs`ov%9MFkrT`KrQzh9G}s8;8NDs`?yb2zW2*GU}m>V>xt?|*k)3a)9IZs>0WOS{Ue58lo2 z9)Y*KE`QKv`4D+~9LqKGmh>v|W*%^8b%9p~IVGA-C-vc;i7>Oen z@r{+n)ECeF13Wao^@vZ}N%GekZB>uxeMR^r zT$h4?F*uguNPJT7l4giKtd$SAtZ+txb3BY}a@}U+?+`S;cpZP+xH4%@avWZ%1M#_t zl(a!s)@5}$G+v~%&Zm-|n=6=L#LU^i+_D^ml=a$6f zAJ|e`9e;1$$Mw}~w%30hw+Tm6pO&M$^YDKP-mCE5t;bt{7GjJcvEoq6Do%;%BP z_{8UN^{V^}3!XTafy>_3w+;?a3fwc!>{jsP#=b}S*ah?`xGM_oK)ZDgelo_ zX78)h@}jG+cK!B7(ZMaHuUCvXFeP0|RDY*w8sNIHkI4M{QBM(HQ9%4Tw8w_G4*FBjX>UW^<7c|{y_d@r;J4hmv}^Z zu6|d>J3!2tzJF%U1|+wu=*om5B7*pTb+aQa`JifV6fj%RI0DK z`5)J>T7odB&#-ueNqMJ9yPlALLf#1f2;`@sUD>wCBidGS)-gY-QO=Uo73ul?^7{Gv z=SmB+ZPW78^V0qOoO%e$Z<~kOU$kyY=7Gfc$b>1ot*5Lu?MJli)GAIo&9YHq~z{CpWG zMm%)>es^=1gxZWQB?WV!U&l>XTT@S2m{_QtU4L)nzf))G6%}dAV zvE-}CQ#MU(Z4IhjedxhG3rpuL+S_B*(CJ+lcQ2?P_;yNuiz3`XH-9p-u$TZ|1Zw}$JdCmCg`>^YgWNWR_bFl^8c^S|3hZTaf|A8 z#W{K!O@3yWmfqs zr{vFA=l<=D+ylEZEAsNEl+L&YtS0|te<{vvz;V$*Yx1=GiFvt|a&|owPh4gGSbuS) zTyd4dC+C;w`K!T49P-6v9!hkzNj$NjAa`5+*K;xMjEJ24`Vv$%?U%HqtRt|n7?|Hv(~{Ih>6ag`Ws=mx;!t~~UGpxeSW&sAW|IB% z4@=^umPbrJE`N1JOi1aA4t`r2?bMu8_5-U+TNjj0shsij4Cl?(I>k^Be z-DP*zyjXuMdR5aF>L>ljWxOx_NW9mDD}jobLvr;pt?`RiGeH?M6owfiT}w|{9& z?}?+9r%pW4x5{m8-C`~A?Xi~Z$^}{%oU^MK$8+(%0Pnl-zT8?8k+^1V`J`s2Kelnx z$%FR&(dM(70NgO)+-vi%%e&6M!Eu8hHFRxWrM7UPh96OcMf_~nfY^Dp$@SaD(QMR_ugc;YY2KR2(Uk|{~s zEe@uXcW9SqQ7|Q6{Nnrt+KQ4^)}e^RI;Rz-&A>dTI@d~j37b_^I^|5qp^{Qb!rc6t zf@jfppAES)Th92Fd%&AG!(Sm|uM1;mo5ab{)mIrejTv#EHGKPOMfBuE+-cB?(z|rL zMlYLKwBPOfxc;iuXv6C#qD{YEH9_vmOD3S-?cP29Fm3x;4LK{D9_cfl1c*dAq>2cp}wNxU)dr3&BV7jdnQN1_+|64(3R zsAw~}bb7F6O0o~^@?2T)0>-IIXH?2RuzS&(B6w%Zn*23+m-{b=cfOu0HIMolGd^KO z!D{hW@D9&%#p^x#qWl$kEBq@P-J>%P{E6AYx%rDE-eAbLb#AcK2^p5NB!5ZXIsS8U zpRKntBt3aA&R?9j#J|KD4MrYFMEjoYe-^Vg`G0$xYX9+*e?=?nU95P-frP|L8FMF> zR-b77_U3EwOrYSD$%1z}|9|EDe_TanbpYqzzr&K#V zq9g(C&NMTc?J3N)aVGj;R_>u^BIO>Korj#ekh>9*w;_#sZ&cziIIVPYW%UG2w9YiiyP`|XXCoG13|Ki{-dFU-Z39d<4jr!6%ke@Na?|IkKrF|>ZBnTHL`i^Lr4 z>o}Q@wapKmCq`=cl>C&uRDWutmQK!3&P(y9IC=Z?r-6@|`B%*Oce}by$r<%d+AXhd zyr8aZ``GN>GWSZK@!o_RR*g$<{>byo{Y4%3Oq<&2lO?&4&0@BH_}a4D`|f-G(#S{B zSH@hoGe2U=hH(pu&An*1`}@He(U}HewZ_(>(1}@ z&iUbzw;ovZOwD(lQwMMSeA443X-V^9Blg|h>9>wW`(5o#ol38Wb$UhD{8-#Ay9Iki z?H671&HYpSIwG+vT1?vGL$pWdLKC`Ee&@W-{w~^L?J#?nE8f8s9rTKr{FuBB{tkLY zgvRkMuK4Cl>#3rjSDu>mYlkVYpk^l_&PZXQ4LkI@fx#IqQ){tk0p z7=h0M4#JKLe*LP^%k2u^g^dEY%eND2Ww+bj+fKl{KOXbp=?OR<-C;CBxWnv^5!}-m zt95r#$H|W5osVrFx6e)$(dYdTPYJ@pZ22}2cbNBNMC5r3BdDiObOtW>+!2TWQrec` z*uE71g#$`M=52`_+TPc(o)7mH z;n?dv57GO)AD{ruyuV?+-`tDIrq#lG5c`o4-b>@~fn;wa_Gemo--^XXh<73WZ{zKV zm?OQz@GK+ByAI`y_I}(Pe*)nB89OiSyu-R-+r)biJ9RPMNr~7J@^;5@NAGpmOX=i& z8^@i!OHhklykFzWSZ@#Hp_}(hoQ?Cof)wMuLy$^>w+)`5BzpJZ%I@CfIPT$<4{=TP zUWrPr^44OP;yLeGc$E6Q_eHQg3zU*s;<3285ZzR^& zRi%Xc;sI_UD<2>8+E>j?)Pa`{?-{p9j3 zMs3x*e4SB{@owK3B=or3=SE)kczpN53wu4jXHebyJihM{=T{zICVcm`$5)Sf`NreB z4wdmOE8(_%s$NM;i4N_`?ezUH@5bbB1<>5_J!lhn_K(jfy^zfeXUW3 zTU+~11-l^HcOeXVVYKf%1aH&J_bfV2WG`P0N;@~kSBJcu8si&+oXv~zO+vD@F}|Lt z1brB*wP`o;WAQ_dYT)V!dxFlFeA}dkc|`T<`k>)ta^5 zcMM|5Uhiv-`pjAH!zWa%QR{uzq5+DZ_GRPTn5TXBAY1kfV$<=_%j<7v(TVp)PFZ8jP;dX5~Nk9d~K!IP+nbLHSIwAC^>XpVMWE(c%Z zVtJt5tT)PVz8t)dN?#qo!3j9HOb$wr+ck0!Kmjk819=p8g&brfiG`IokUw%cLk~zz;!^x4e`Ff52nYB9 zCRg}rXzG?>qPGgOd)mX$KCMTlSaz@W*FXz%bpuVc>|>P1f~Hyau}ZswrdxJzrCmV# zS@v;CJA?MO>^@36fex_jzDhfS4z%nfr5!*AS$4A07|_9%ouafoXezRms=S?WmeTBX0wgw-Jua4OHG*IC3{gc`M<_-eBb|g(H8*D~|wA zL;i*+Zy_A{8>+myaO7{8@@B%3zv0S#!jZodlzW9Ee>h2!0Fm-1UG^yNFqlRh zl5YoKF~=bV8dM!JTB$muP^mhkNU1ucSgAT>j8b(-iBfe)sZw=FnNoE~xl%f0ta3VJ zoN_v3ymC5Zf^s@!qH;RqMCEkIB;|C-Ny_PvlapJ%igG%nQaK$m zRXH6}rJN3#rkoC$uAC03R!)c1D5pbaD5pbCQEnXK_nd?FkGu{en4M=Fa*H@*rdOOJ z4w-A81N%4*IaPzIL*^+}htw)nhtw%mhs;;14mnM!I^=Yv>W~FW)gcR&szc6DN{5`O zoDNx}oDMllIURDgayn$Oayn#*aysN3<#fnW<#foo%IT10%IT2h%IT2vl+z*SE2l#) zP)>(jsGJVDNI4y{LOC6>QaK%Rv2r@(66JKrrON4$RmzP+W_xZz`$s;4nU6ikIHVl2 zCwsM5oFfjo!oCT&U&kR=YEX5^TBYictCXrku2!lJS*KJTa*a}T$abjVH0>5!Y1(;>Ggr$cU4PKVs4oDR8NIURC`ayn$AaysNr z<#fnh%IT21mD3@cl+z*iD5pd2RZfTeLpdFCpK?0ne&uw?X61Cq1Imp<)_9&l`$tA& zVq;%!95M=1Bl|(GI7b}vsQnBkO^!nz)1c~*$Cau>o=~a|c~Yr55%7@(;+V?r$b&;PKUgtoDSKkoDO+e zIUVwfayn#}aysNy<#fnv%IT2TmD3?_D5pc-R8EJyrJN3VTR9!_j&eHWUFCGhd&-SN z9`<~R_K$oY6L|X( zL;k5$9rA@zb;y@W)ggP7szdfFr9<{9r$fF{PKSK0oDTU$IUVw?aysNY<#fn?<#fpR z%IS~;%IT0Fl+z&xmD3?VDyKsZDW^kzQcj1|E2l$#R!)cfqMQ!-RXH8}OND9#+AdgWLqC`L@qbWp+fLykv&_)DgvmJ%jA|RjbDYOy+ z8I7UPQUv6*1BD0(vcl;|p@j&@X(tNJML@f18FAg2iw+z@1~lSsiO0&?1&0u0hF%yzpx#V|^ z5NtKrJzQR~m$>LymwhUR9>+z!8D3p<9J#uv54pOiFS)uXiCkTjOs+0UAy*frlB^zrO{3R|bblDHVSdNQ|7+zgeOs*~(L#{3=Ay*fblBx ziFyXRb@pg=(IuGT*mGQ7@t3%$)@A>Wy-3GJbqudAnoq7SI*nXibUL}ZXaTvpXd$_} z=nQgo(V67xqDAEDqO-{9qO&Q`MT;rWMN25qMdwhUi75&G71?b>!-zYsl3_>&ewc z*OIG?t|M0$Z6H?{T~Dqqx`A9>bR#)kbQ1--=w=FZ(Jd6{qFX7@MYmC)i*Bbt7u`XD zF4{GD*=AW>~)V{fgx=rd<6=JJZa#6?fI>e4svzTv*dKqa}?;J=PA%dFHoS1UZg-5y+na7 z+DU;fdYJ-U^a=&KXcq;#=v4}I(Q6dwqSq1`i{7L_7rjM+E_#~+UGxqGy69aB zbkTbh=%V*2&_y3mpo>1FU|jT=%OlT1qaGCFJgzQUjK^g5M=r1UOI-A+%YFshK#q$( zV|aDZ=j7_5f0C<!hUcR8C+ebyR&nZqM;BNK`r=h}+?Av(o7p0J^i&DweMQP;fqI7a~Q9p8ZQGarE(ExI~ zXdnf;Xb=UuXfOr3=y(cr(GUuB(NGF>(J%^h(QpcM(Fqjjq7fA6q6`Xj(MSq(Q6>et zD2oDJludyy%Ar6PjiNvoY`7v zA#IO#d&OVkqA_m!hTiI;5{6e7m6EHA%E;A4<>cz3vE=HaapdZv@#N~F3FPXciR9{{ z6UphKNfhX!lPJ(dCsUw{0u<Y~#bUR|_+TwSz~TwQbqxw_~~a&^%na&^&JHjt}}t|wO)-9WA`x{+L6 zbQ8I{=w@O8^d<$m=q(C#(c2X0qIW3JMekCei{7I^7rjq`F8Y81UGyOZy67VcbkWBY z=%U>ejEkOhd#-{(qMFMi`lr-I=gOx$K5=`+U*e*Fy6s2O)kR-0yt?R1a&^%ja&^&O za&^%@a&^&H*r$85dPk}BvK!Gm$fdXB0kOE!wBL%wX z5CyvECkk{?Jq5bxX9{%DFBIsaUn$TKNwdQhN?dQzZ^ zdQqT@j-fyo9ZP{O>P^A8$mj8N9{?8}CyV=L9<$PqaDyD@@ru91MadpJdyu*)h2hmj zspRUSG;(!OI=Q;2AGx}yKe@VS0J*woAi26|5V^W&FgaaxJO#RF2nD)mCRZyUdrcj`Z zDk;!KQz_6zRTSu=X%y(9=@jUqY6^5w4F$Sr1_iq46bf|FObT?-EDChdYzlPI913*N zTncp2sTAmXrae`b*Q@N z42D-1ok^}PT12icI*VLgbT+xVXfe6EXbHKx=p1r&(Nc1C(YfSw(J~5j(Q*oO(Rmc; zqVp-xMHf(@i!P)<7hObwE?Pl>E?P-}F1nZkU33Wry6930bkQmbbkS-GbkSuL=%O_g z=%ULh&_!2Jpo^}gKo_m0Ko?y_fiAk5f^pI59?u~dB&tj%)C<%_h2o-h9Z04o)kU|H(?xespo=zA zpo{LLKo{LbfiAk60$sF;0$p?u1-j^73UtvwD9}asQJ{1(Rz<(C=3!+FHd8yRTpi+Q&{^c zk5~L9E_&KypOm34+RpImqG!m}MLWpVMbDC}i=HD_7d=m|E_#7nUGyTky67cxbXphIfDN|jvm*Le#`^eQrUy-Yez9v@}eM7D;`j%W>^c}gnXg|5S z=zDT?(E)P0=m!dP(LoAy(T^19qC*tuqMsi+-g*7yU+oF8ZAU zUGxV9y68^|bdeRN%XYfRMS(7IQ=p4H6zHNb3UrZ8fi4QCKo@x_&_zB9#zkLvJkP-( zQ4#X_qA%4&U*K83-7L&2{t_3p472xUtBYDOyt=40xw@zgxwR~N;Q(?uO9&_x|7&_$gn&_$go&_!J+&_!J-&_%Hn=%Q{E=%P3ZbWuD7 zx+sAHU6e?HF6vH!F6u#nF6v2vF6u>rE;@z+U34r3x~Mk=y689xbWtA)bWvXl#zif{ zJgsuzqP_CR{SjeirN2Y|E;T94EB+D}rD3t3t1e1scy&=fa&=LEa&^%Fa&^%_a&^%l za&^&Qa&^)11-dAU0$r3% zfiB9SKo^aoKo{jwpo{zz=%PFdbWuJ9x~PBxT{M~kT~tVcE-Iox7Zp>Wi^fo(i%KXM z7o~)G%3zSFX0p;xRTs^Y4`G*vdBtDiqH$sN{5*Bhc!pOOO(0hnO(a(rok*@OnnbQH zI*D9ebTYZRC_t_*noO=PsvxI}rcj`ZDk;!KQz_6zRTSu=X%y(9=@jUqY6^5w4F$Sr z1_iq46bf|FObT?-EDChdYzlPI913*NTncp2sTAm?nY{t_203bP+8P#2xW@am$o$<;-R$<;+m$kj#X zkgJQ9lBC(@L5iS&A~qC7 zRP0z#P*fC9Y+yk}u%M!z-?P?phv2*4ce_33J?DS+b+ME0ovf*!nN$!(w-Zow2LVMZ z39h1<)x3udkiaiy+Ot$qg*-9cSW9-No^$XdPP>t!JyEyVY*{Wz0TNT~QRz>%*QM8$WqWcLb+Co6l0|XR3NI=m;1Qb0?K+z)v6m2D-=urZS z9wVS=8v#X+6HxR70Y%#hD0-5Bq8$VjJw-s#(*zVfLqO3^0*am`xQbR+^ENR+0^Q>b zoHeRwfc(bnbJhIfOBB6S&F;}p6}`;ys%RHm6}`e%MX$0|(Q9l~^g3G=?PjZ@H`uD^ zO|~l9!$#3w0*c-upy+J^iuMsu^bP?fT9lwC^|qu(Ln-=4iQlF zApu1n5m0oPfTE8HDEfqeqE87Z`iy|0&j~0xLU0wmP|Z8m014#D2eB7b(d1||j#l%F zFH!V$HT$|ERdkHwRna$WRrD=e6@AB6MaS8y=zF#*I>A;&C)uj#2evBuk&U9C2q^lQ zfTB|b6#YU#(XRv){YF61X#$FVC!pvL0*d}5pve5S>^sa2T+M?b4*^AC1QdA*D5^$4 zkxf96kANaS0Y%{i6h#nF6iGl)6v0*WWi{`^21uYxzFqy5DvFigb&R(C;!708+xFWf zswjcuRZ)PgiW1qXs5)B})nKclnru}RWUHbOTNTw}tD@R$6xAW1s4f9T^#~|RBA}=~ z0Y%9K6r~VQ)PR7Zh6EHfBA}=-0Yyy+C_0CLqNW5CH6x&?IRQoI5>V8FfTC0aidqs- zltw^NI>A*GYkN-_Ac33Z7t`Ww_bdH|^6Rr1wqJaSqPDhOYoID>$MLGDJzEuZV5_2z zY*lm~TNRzpRz;oIs;Dzt6?I{&qONQdbt9lClYpY`1QcZvP?SwTQ4Rq`xdasTAfTux z0Y!NP6kR|-Q7;0D@(C#FO+Zl}0*VRUCdTRrEFDn30oBnWvilL zY*kdoRz<_vC@LqQXaoU8BMB%PML^ML0*b~EP;@B)MPmsl8b?6Ucmj$h5KuIcfTGI? zD4Ik-Q3U}-lL;uALO{_}0*a;)P&A!@q8S7f%_O*r2HM{F21p=Xe(!paD!NPl^{QF6 zUwnz8D{TAjA*yID$E%`wY*ln6TNPc!Rz>sKs%QaQ6)?*tV6K|s-;1Qc05{jwcJ9s-KO2q^LrP*jb8 zBAb9B9|1*v0*b;3D2gDUD3XApC<2P22`GvopeUB$DmrF+R~jIJGEwx6DylAjA1%)3 z7hj?%(PuwZu8OL2yeg`}Rz)@0swl`-MIp8-s>N1Cwb`nu4qFw~WvilkY!oFCP*k6Q zqGSS!QV1w&KtNGL0*V?DP}G=!q9z0sokKuTQv!;b5m3~efTD8=C~84KQ7QpNEeR+} zBcLdqfT9cnidqp+)SBQbO7M92TNQOWE+@E(F7$cF8z6yL`Rsa# zDq1gpA8n4$FTO<4l|K81v8w1Qj#owV*{Wy(TNPc+Rz=saRnbDWDq6%=MT^<0=vuZa zTEa%rbp#Y$Pe9QP1QabLpy);dif$sHXc+-T%LypDnSi2O2q;=XK+&xP6x~KZ(d`5j z-9bRnN&<@RB%o*&0Y$3`C|W~6(OLqE?jpE~=K8!_4Uj-)Ljz}?Dw-`%OzV7p@g<5j z`0RJatD=n@uZlLYRnfg{RdgR)6>Vm#qWjsZXbW2vJ-}8)53*I!Lu?d1OhC~i1Qcy0 zpy*KoiXJ1NXd3}Vj}uVz1OY|c2`GA!fTA4)6g@>i(bEJJJwrgzP6CRaC7|dz0*am| zpy&kxie4n3=p_P*UM9GT?)G_qH9!K3Yy;;WRWwF^*=U!~FTO<4>pr{AWvXa5$E%_@ z*sADFwkq1gRz-W+s^~4YDteo(iuSQp(K~Ea^e!7k?-5Y6pMawG2`Ku2fT9Bg6dfd> z=nw%#9}-aX5dlSq2`KuQfTB+bDEgFuqR$8@`ka8GBLoy3C7|dF0*byQpy(?CioPbG z=orCO^s3L>%>W4;ke{Qyri$i!&G^RW7hj_2d!IeDLKU6hcvW5Kt6GK#`Y#qG|*b z*#s2%2q^LsP!vu;Q3L@+kpvV)5l|FOKv4_}F#Su^xPe4%u!BzB~&wI5261YWv zj&@uX?U29X81VbWmnf>~w>L~tML~{NMIp8-s>N1Cwb`nu4qFw~WvilkY*m!RRz>yM zswkO_q7(v(8W2#_kbt5_1QazUpr{D}MduJu)RcgtW&{*9C!pwD0*YD?P?SnQQA+}f z(g-L@C!i>UfTC6e6tyOxs0{%{Z3!r9M{pHY_j_MAKmxnu2e38#?pOMgPbLR9sxxc5Kz>MfTDZ?ih2`J)Q5ng0s@Nq5>V8SfTBVIii!v*Dkh+)gn**{1QZP* zplBcgMS}<^8caaZg#=eoN53~P-6+bF=c4meQB<-SL;Qa6C5kTb+pTA+qM;nGiiWXO zQ5jnm4QH#Oa<(cO!B#~h*{Wz1TNRCFtD-S%6kSR{(O3eC#t~37o`9kW1Qbmqpy)CJ ziY5_IR6#(|WCDt&5KuIgfTC#x6ip|fXa)gAGYKe~ML^MP0*WptplA*OMOP3|G?(Bi zy4dd>Xn+KMkgxPhRZ)!;Gv@jI;!6}Q@Y^$HtD>tpUKL%#Rz(Zhs%Q~g6)k3~qHEcz zXbD>tUB^~M*Rxg84Qv!GC7|d=0*Y=TplBHZMau~&x|x8YTL>sxK|s;11QgvyK+)|4 z6x~5U(Mke}?j)dS6#+%72`E}aK+#$PitZwyXdMAX>j@~jo8T(C%I{refCO%oZxPK` zMPucA*Z27S;!70W>$jhoql)h1cvZBSt%~kvtD-GzRrCN`6+OsSMGvu6(Zg(2^axuO zZDphAQ38q{BcNy-0Y#4!Q1k==McWA|dXj*m9Rw6TML^Nh1Qb0(K+#SDik>B)=s5z4 zo+qH_1p^Rs^}fIDtec#ir!WIR0Y#q^P;`WVqN4;9eL+Ccmjo1jML^Nl z1QZ=3py(R{ioPYF=sSX|Xt&?n+yDvOnrPs>p^BEvuks)F`^A?i`oVAax=I!O$nmP^ zC$=j3nXQUWu~pG8Y*q9tTNVArRz;`Ts_1vND*A(sqCW{JvcmPtb`*ICC<-H>$V)&` zH3Euk0*ZVD6!{4#3MZf_f`Fn(0*aytD2gVaD29NdSOSXT2q=mtpeTWWq5uI!i3Ai? zC%B4E_`MSikie{vfpbz7CCCr>YlQp7mnfV8PfTHFE6rD>zQ40c!QVA$( zNkCB=0Y&Kq6lD-l)QW(j)&vx_A)u%&0Y&WyC~8kYQ3nEwIucw(!EoH46y*_6bO8ZHy$C4EC!nY|0Y!ZXC@LVJs4oFU{Rk*3B%r8>fTCgoib@D5>Q6w? z00N2z5>PaVfTF=NRWy!`qVWV2O(39XA^}C0 z5l}RVfT9WliY60KG=+eosRR^FBcNzH0Yx(iD4Iz?(JTUrW)o0!IRQm;2q?OOfTFns z6wM=`=t=^Lt|GXKhK75)8z6y=wGEtMswi5%c{D%VFTO<4!f?B6i7Hye@v3MsTNPc) zRz*wLs^~hlD!QJnif&-5qNQwAbR%08-NZ)GG6IU06Hs(B0Y$eEP_%-8qFV_lx{ZLM z+X*PTgMgxy1Qgv#K+!4!idGX)w1$A9wFDI1ML^Ly0*clXP;@r|MfVU;w1I%4jRaTG z)#2WS21sCgl7VxLDrznNB-W;IzxWbG_lMh?u2)4{I9?S!z*a>MvQ^PTY*q9yTNORR zRz+Lcs_0R+Dte5qing&)^f&=UPY_VFoq(bz2`Jh@K+#hK6g^Eq(K7@T?IfV+Sptfl zBcSMc0*YQBpy)*cie4h1=w$+mb`enY3IRp05>WIS0Y$G9P_&!iD!MP+`-TA$*ebsy zyIB>b%8x_d2=|LGQS?^0{oPVk^ft$j6on%E;!70Ojj(6ktcvP!yedj! ztD^dBRg}zDMJa4m)PSvu8nRVUBep7P%vMEB*eE)OfTE@Z6g4BDs5t>e=MqrVf`Fn_ z0*YD^P?SbMQ91!d83YuyBA}=>0Yz;HC~8YUQ9A;P+7nRJfq*NJey(!W2!jLs2$@g<5fBkX5asG{y1uZptRswkVSigMVhD3`5@ zdazYdPqr$`W2>SI*s7=(8%6m96!j*cs1E@}1q2lJC7`Gu0Y!xb6crIrR7^lo2?0g@ z2`CysK+!+~iUtu-G?;**3kfJ1LO{_)1QcCNKv5|HMVAmzG?d^f>KfraVt@ovCFKv4w&MUx3AnnFO)R04{o5l}RpfT9@$6wM@{XchrQvk54=oPeS^1QcCC zK+#+RislhebR_{rR}oM&pMatT1QcCOa1{-Y@U}2O0zb%?W#y_UR-TKliSUarQFLvD z-Fu}fTEg+F=sLD4x}L3yZeXjTrEFDnBU=^S#8ySi*s5qbTNT~RM$s(<6s;hj=vD%X zZX=-Rb^?m-AfRX^0Y!HbP_&AGqSXWxts$UjEdfP$5m2;_fTHyT6x~fg(LDqdZ6Kg% zBLPL52q?OjfTH^duA)T|-bn^XAV>c4&|+0IKz^pbIl?c#MA3s0_Oex~=pl|*MGv!8 z(IaeCw3V%j9%ZYd$JnZ98(S4U&Q?WFuvO7^Hj17kplAmHMNbh>^fUoQ&k#_wlYpXU z2`GAwfTHIKD0+c_q8AA$dWnFdmkB7^ML^Lj1QfkWK+$Ui6unMB(QX2Y-XNgpO#+Jc z5L`uDBD{|qAc0Hd_pTpMMGuOiy%B!#C5qmOu-{*!ir(dTRrDTP742uMqW9UV=mWMY zI>1&%2idCV5L*>}$W}!ku~BrGfTE8HDEfqeqE87Z`iy|0&j~0xLO{_`0*byMpy*2i zioPPC=xYLsjuBAw4FN^p5>WIV0Y%3NDEgj&q7wuZog|>>2Lg(IB)E#+j`03rfCLW9 z4?Xs&qE7Nj(oYe7@g<6Wjj-#lQ$@dVyec})Rz<(FRnZ@8RrDuY67JKtNG| zfTBbKimDS(RD*z`ngkRD2`CB?P*jV6qS^#k(WwY;wgD12F8_YfFRG}Y{4+FlBK_h^ z6xENk%kNf2$sDhWQrN1f0b3O{WUHb^Y*o~lt%{nkRna+YRn(NNikh)e)SQ5#a|tMF zK|oO|0YxndC`u!sD4l?!3<8Q;5m3~cfTA`86tyLws2u@C?FlIAKtNGP0*cNfpy+%8 ziaHTc)R};yE(8>HCAf;}MS2$-Ab}wQCn?hXO8-w8-6H+sOB7{C+V^cxML8U=igMYi zs0UjW^<=A}Jhm#jfUSypu~kt%TNU+YtD-(^6crFq)R%ywegqU15>Qk`Kv6LPMI{6j z^(UZc00Bh<2`CywK+#|ViY_FeXb1sC7ZFf&F#$!T1QcCDK+#YFiiQzTR7OD2aDuC- zd!%=d0TLK5AH=d$(H!~Bkn%{s_!32=NRWy#RipH~5(FC?C zn#fi~m$6mRB(^H5V54X<0Yy^?D4I$@(KG^zrV~&!gMgx$1Qg98plCJ$MVAv$G>3qq zD+nl>OF+>)0*bCApy(cBRdgd;72U*EMa$T#XgOOI-ON@+x3E>w3brb` zm5rj?2q?OpfTBAHC|XHC(VYYotsjV_-CZOmI0*c-w zplA;PMSBS-dW(Rfw+XJIha$aq86bf@^2Pnbs%W1m+85~;U!rJ#r2YJZs_1==S4AJN zRnY;qDmutkMTgj`=tH(D`iQNH4zpF!$81&f2^&S95>WIR0Y#q^P;`WVqN4;9eL+Cc zmjo1jML^Nl1QZ=3py(R{ioPYF=sN<6juTMyJpn~02q-#9K+z8b6#Ym*(N6>v{Y*g7 zDT1r$-AL~j21wvV`D-8VsiK+kn<2kM`o)(h`aRN)ctjQb!SSl-Pqr$uqVy|wRpeo- zqA<29^0HM?HMT0U*{aCLRz-d`ioyvfiXfmUl7ONp0*ayuD2gGVD3*YtI0A~|2`EY+ zpeR5GTNRzl zRz)q?C`u)us3ieKX#^Cd6Ht^vKv63Kidqv;)P{hfwgeQlBcP}~0Yx1MDC$T+(Rl1Oq5`%m>dRI|{n#ifB%r8>fTCgo zib@D5>Q6w?00N2z5>PaVfTFvuQ8YHnKJbJp8prXfXgpgL zO<=2{iELGL8Cw-iVymJGwkn#;Rz*|Ts%R=3MbiiPaYfTGz16kSe0 z(HsJbt{|XjE&)aJ2q?OefTF7iD4I_|(ET{=fTG0&6kSU|(Gr5I zXiSvX+HMq`BfocjsVaKQyv@EY$}he|(T!1d$_`a@6UVEfWo%WnoUMv(W~-uG*s5p+ zTNT~PRzFZH zQdP80J}-JW$}he|(PL5e$fs4&HjYB)=s5z4o+qH_1pGuMtr6Isrwy2`GAl zfTA}EDB43n(Ov?I-XfsrZ32q+5m59F0Y&c;Tt!=>yh{v_Kppw6sV$Mb+4<$Y!e|A6pgq*{Ud(W2q>yWKv8W1is}$hRF{CFdIS_D5l~d0fTCoA ztLTp?Z|HfWsIGj!=ucHtDn9{9iS~;xQPeov?)aiAYQpiV=p42xYRXnc&Dg4_Ia?K- z%T`4#*s3U%t%_Q*RZ$unMd<_-We`x*ih!cl1QfL)pr|bYMePVEYEM8>2Lg&Z5>Rv= z0Y&E%P}GTlqRs>qbs?arD*;8_2q?-Vpr|_mMOg$CWfM@8LvR%}jP_n^fCR3Ue|e@+ zwELC*H2KkNZnR%~iJ}Xl?JHhZMZGv)73H&4QE#>?>cdt=1#DH+m#vEWu~ktaTNM?t zRZ%e;MI{6j^(UZc00Bh<2`CywK+#|ViY_FeXb1sC7ZFf&F#$!T1QcCDK+#YFiiQzT zR7OD2Z~}_T2`CytK+#A7ibfGoG@5{-F$7mp&uH&@10=9p{v)4xs>qfv`!9|5i!V_$ zA=-ZN6;(8m<5kgRY*jRgt%@qxs%SD>6-{BQqN!|EG>xr_rn6Pi3^s~p5>PaYfTGz1 z6kSe0(HsJbt{|XjE&)aJ2q?OefTF7iD4I_|(ET{=fTG0&6kSU| z(GmiRt|Or6dIE}WAh?RgMSH(8KmwP_?_G~qMc0d>rO|%zC5o0u+flEpqMJEh72U#C zMJw2<=vKBWx{a-hZfC2aJJ_mdC0iBU$yPj)@XPe9S# z1QgvvK+y&QiZ&8Zw26SCdkHAIkAR}h1Qgv*K+zTgiXI@K=s^OC9wMOVVFHRCA)sh0 z!Buoqv^U)V2|OXccfCv%Jt;q$eKguHzC_Uz(RRN#RMB>hS4B^i(?-N`_+oHWw4Uj;J z{4*hstD=38W_%Fs7hj_2!)SZO9#!-a$E%{lY*q9zTNQo6Rz;t(Rncc`RrEPq6&+!# zqN8k8^aUG5UlLIC6#+$G6Hs)FfTC{*DEgLwqVEVOI!-{*_XHH3AfV_Z0YyI$Q1l}K zML!Wx^fLiPrwAzeg@B@82`KuFfTGg`6#Y&>(H{g?(ZOi%4g)06Uw({#NENL~G~>@` zzxWbG-WdCk`F?iw?&+3YE#~a6^li2(^08HspRJ0**{Udlt%@Sqswj%BilW)7D29!q zSOSXT2q=mtpeTWWq5uI!i3Ai?C!nYX0YxMGXnAB2SDr>}{iHx%{eiSd9BM+VJXTG>Y+yFHzJq#%}nI zDr&~@`drkUt%}ZNtD+WcRg}tBMJ?H?D2=U((%GsggRP2Mu~F2TfTA`86tyLws2u@C z?FlIAKtNGP0*cNfpy+%8iaHTc)R};yE(8>HC7`Gq0Y#Yv6m=({D2sriYyygM2q?-W zpr{7{MLh|wq9!rko(4!@t9)^Pjw<>_6y?SE#g{1R9b=DvPZjmycvV!uRz-c;s;D1Z z6&12oQ4w1e6|+@Q30oEQXRD$CY!nS7plA>QMS}?_x{!dPAp{g%L_pES1QeALP;?0a zMMDWF8b&}-839GZ2`DNjplAdEMI#9)8bv_SXab7H5Kwd}0Yzg8C>lp_74?eoUT=T| zj>=C!@>Nky`6Ow4j9+|-qDe9K1MjP%3XWGrli8|h3R@LTWvilTY*jR!t%_!_Rnbhg zDw@SsMYGu`x}1QbIRq44K|s-50*dAlP;?~$MOP6}G@pQ?1q2jbO+e8#1QabKplA^R zMT-e2x|V>VB?J^*M?lf_1QgvsK+#eHif$yJ=q7@zXkv_ap8*nBEKfg|siM}gW-N>G zi!V{MBF6slfGWC`<5kgZY*lnSTNT~GRz)k>s_0I(Dq6)>MXTAWXboExt!1O=E&__y z5m2Rv>0Y#e$D7v43qAdgzJwQOwg9H>kL_pEQ z1Qb0&K+#qLiXJ7P=rIC{wh>%KH^+EuA2f=3%fG#Uiz@QVH?kj(@ry4}v?Ino|3g*u z6vwNgr`f9L8MZ3g$yPB$|p&OV*KJu6nz|H&pWJ&KH+#(^eI~vea2Qr zpR-lb5wioPMB=vxAcz9XRMH~~f96Hs)5fTEKG z6#YOz(T@Za{X{^~&jb{mBB1CO0*Zbmpy)ROicS+y^g97Xe-KdgCjmuPtbSpRA`ih; z^ihoW9s?w>SAI$MuqqlNKMo0t^@}f2BfTD&36g48Cs4)RWO$e@{YO&s921wv``NcFl*8NI< zll;osIkA56C5q0CwPQY4MJ+g96{WIOQA@TeN@J^{bhawWV5_25Y*o~nt%};PRZ&|u zirNuS)SiH%4g?f+B%tU#0*cNjpr{i8MV$#K>Ow$KR|1N<5m1y#Kv8!Bin0hO$|j&F zhk&A70*ZPNP}GxvqC5hME+C+&7r|B3EY{n~015mqKRRo!iWbX{L-J$&;!70ujkSx8 zs-k`zuZjxUs;G#qii+8)sD!PG`ml*b(HH`XE+wF7ECEI12q+p) zK+yyOiY5|VMSWtu(+!Zom?Q(IKowmqKLNQc)-S$9(Ue&Gwl7uDRE}3g)7YwLI$IUZ zV5_2;Y*jRit%_!|Rng^aRWygKimqUzXf6Ro^9U%ql7OPC2q>CQK+ysMimoQ0=o$iw z77|djh=8KS1QcCMK+zHcimoG|=z0Q*ZXlp&DFH<{5>Rv#0Y%FQC|XWH(ai)`QAMox zX#*rMTt0|RRz+7kU$Djc#g{0$J=Xr{YgKdy$E%{1Y*ln8TNSNhtD@CxRkVh!iq^7K z(Oqm+w2rNc*0WJ`HvvWW5Ky#%fTE2A6m24)=w1Sf?jxXRGXX{S6Hv5;fT9NoD0+~9 zqK615dYFKsM+hj|NvQ^O+Y*q9nTNQo9Rz+X4RnalFD*A@4ioRu|=sN<6juTMyJpn~0 z2q-#9K+z8b6#Ym*(N6>v{Y*g7DFTXqA)x420*Zbkpy)IKMZXhJ^alY&e-cn+#p##r zDDn_c6h=Uimw=*b1Xs}~vEHQyNZ@Aqz3Wd^(Lni?H9O8PzC=+(oc+)VRTRnbswj%B zilW)7D2ARfTBhO6g4KGs0jf@=MYfTlz^gU1Xqzi z&ik$b5_n&}T^%0hex?7g{3rLC$N9yVC~6sJ|NMh0O5=D{l+IQ~8EjS5imi%TvsFaDs;E6%6?I^vs3QSI=MhkJJ^@9Y2q@}IKv5S0inzSMZE|p$|sPaZfTA)2iiQ(VR8BzA2m*>m5>PaXfTGa^6pbOE=u!fT#u898 zj)0=^1QbmmplBiiMVAp!G>L$s3WBSsUz~TC0TQ@Rele|36{X9U{gdPT;!6}wkF&4( zMHS89cvUo$t%_!`Rncs=D!QDlisrCY(G_e}G?%T4=CM`Lm24DUML^Mf0*V$8P;@l` zMb{8ew2*+JMFbQrCZOnA0*aOpP;?yuMb{HhbOQlJO9?2tk$|F`2q;=cK+$pnif$&L z=oSKsRuE8hE5TJXHO{-y010f84`S0)(QBgUwm84|5=D2$*{}SjidJ#FDq77}MQhlq zXf0b6-NjZ#>)5JjJzEvs%~nPCuvO6pHi|Y9P_&7FqI(G_x{rXO%>)$PPe9QY0*W3W zpy)vYiXI}M=wSki9wDG;D*;815>WIQ0Y%#gD0-ZLq9+I_+D<^xlLQp)AfV_ef~)9` zIPbRxNT8LO_DWS$Q+^uzbevy&iK6G??6^Nv(eoUyie6x=q8Hh!=q0u)dYP??cCl5_ zD{NKtDq9u3##TkIvr)90fTA}DD0-8CqCEr@?Iob-Edq+(CZK2^0Y&c+Q1mVVMeh+% zw4Z>Y_X#NafPkU{1QZ=4py&_*MIRDS^br9?hY2Y9n1G^B2(F@?ao#otNZ>d5Ioh+T zsE7Q1(Wh~K@g<6m#@Qv7oPhbg>n}K76@AH8MPIR1(bsHMbd0TvzG17PZ`rEoJGLr1 z&Q?X=vr%+{fTEKG6#YOz(T@Za{X{^~&jb{mBB1CO0*Zbmpy)ROicS+y^g97Xe-Kdg zCjmuPynfk^A`byYVFVO;2`H*YK#@&Ak&l2PKfzV>d7O8q0TOt#wt;g*6~)UB)xzWb z;!6}o$J=*=siGK;S4FXGRTRfoMe%G^l)zR+0k$eiWUHd;Y*kc)t%_>0Q4}PgC`3R} zEdq*a6Hru#fTFqt6xAc3D2afg`UDgu6Ht^wKv4q%iW(A7)QEth#sm~KA)x3S0*aav zP}GcoqUHn?ol8Jb3xcaCGTyt>00}%Np9)3AyI<+QC5lqx{o+d$WyISbS5rl;I9?UC zW~-t$Y*o~jt%};QRZ)AkD(b*iMIG6y=sdP6I-iZAP6QNnCZMPb0YzO2DC$N)Q6>RJ z-3chlBA_UnfTA1%igF1k>OnwJPXdba2q?OMfTCUm6y+08)SG~!J_HmM5Kz>YfTDf` zS5aEL*Jm3=JLKnR>8j{j`DtunykC5YqW+DFhTvCAf-;X3Ia-M- zY9e3uPmA}9FHtlr-X0gBie_`XD!QDlisrCY(G_e}G?%T4=CM`Lm26dX66fGp6Xb}NLiwP*YmVlxq1QcCIK+*LC6x~2T(NY46ZX}@SCIX6<5m2<8 zfTEiTD7uA!q7?)b-AX{wZ3GnEPC(He1Xt0Fc<)UHNT7a-fiqJT?GZ&Q$YdKyO-NjZ#>)5JjJzEvs%~nPCuvO6pwkq1lRz;iGs_0%eitZzzXfpvt_Y+XG zg@B?52q=1xfTD*8D0-NHqDKfQ+DbstqXZN^MnKUv0*W3dpy&w#inbF_^dtdAI|wLx zih!c02`GAofTEoQSJA3??|uU$P#{0XU#*Ik$zKS0Hr_A3MA3`!_AfE2=p~LW7eL_IdrvwyzMnKW$ z1Xt1X@!q6Zqo|pDi|7SDFOr|e9*OshFH!VWyxlck6@AU|s^}P76@9~2Mc=Yj(RXZB zbeyeQl+fTAP_cg1Xoc^g7;nnB(T9YaAFhOuk^>tcOBCc{NhU# zwMnpFtFDULa=a>P$5ut{*{Y}mTNQO=tD^JRs_1;SD(b{mMV;BIs0$lKT?r`aMnF*} z0Y%*jD9R$BD4T$y90H1R2`K78Kv7Quit-33x`2S9UIY~76HwHffTBJG6crFq)R%yw zegqU15>Qk`Kv6NlRn#iMd)xpCTq$4Nw^l_L$Pf5S68z#z6b(wS6N0K}FvqK+3)!k@ z2wN3h#8yQYvsF*qANIF70qRuvO7Uwkq1hRz>%+RndKHRkWF{itcBl zXbS;F4-ioFAOS@W5m59n0Y#4xP_&hRqDKiRdW?XgZ3GlOPC(HU1Qcy2py){gigplC z^b`R_PZLn|3;{(u2`GA&fTHIJD0-gYDq5T1ea-+0TpDfQ+@*?M6h$v2_{Enf+Ld5` zT2B?d!ttu;RkkX6jjf7aXRD&!Y*q9ITNS;@Rz-W*s%S4;6}`nq(c1(R?IWP*9RiBp zC7|d%0*dw%Q1m_lMIR7Qbbx@Og9H>EBB1C)0*XE&py)6GMIRGT^a%k)pAt~?839F~ z6Hs)7fTE)W6n#N(6}^<;4No$PrqwZUURFiV$=_=HGQlstMA0`1cC%zv^exA$qVL$M z=r~&yea}`!C)ld!BwH2zz*a>+vQ^PfY*q9#8%3uGDEftfqF)Ip`i+31(*zX#PC(Hg z1Qh*AK#>*DFWXV%A)qLXfFdseMb!u>vI!{i5m4kOpeUSxq6h+tA_*vpBA_UmfT9?J ztLWgcSb+#(1!B#~z*{UeWRz)GU zDyqd+MYY+gs192d)n%io9sxy31QgXLpeUJuq7(v(8W2#_kbt5_1QazUpr{D}MduJu z)RcgtW&{*9C!pwD0*YD?P?SnQQA+}f(g-L@C!i>UfTC6eS5bVxyW9W?tdcLw5(4g5 z`l}2cyLG@XzC=;`fc##TjTY*jRzt%}Oos%QioMI#9)8bv_SXab7H5Kwd} z0Yzg8C>lpV(Rc!iCJ<0Gk$|Gh2q>CFKv4w&MUx3AnnFO)R04{o5l}RpfT9@$6wM@{ zXchrQvk9)E!2xgbIY!Y-@_W}8s-j);w;C@G_{EnfnisG$o2jBJIbIcA#a2c0*{Wy( zTNPc+Rz=saRnbDWDq6%=MT^<0=vp?4mJm>M9RWqx6Hs&m0Yys*D7uk=qMHaPT1G(8 zasrBOCZOmR0*Y1;P;@H+MYj=9bUOh>cMwptl7ON+2`E}cK+$Rfiq;TNw3gs1x+35m zVSohIn`zHgMSsdaiFH@NFTSjrR+!x|;-MBEE7;k5)@=n#%|Az5EjZ8olq5X3&U_$@ z4!&qUsfrICHNOc^J$SD9Hz7m8%M8l8!ENRjD3gP~o6oWu1+&b5p{8kYQHo`?2)=24 z+>#!w(ZsUa1TSoASsj9Fn_E_=;L#SA)h(EsW?9+6iVVx@8GNF(W#tF|Y-?G4gE<{6 zt2lV=d6qRWxVMvK4G9LjTGl1Oi!v>1cyL{oWsM4cnPXXFgK0f2YhrN91(r2A_+-9i zO%HksENgbKM?cG&8@#T_vgQZhF0rhI!CC_?Ye}$luw^X`-aW*!mIuGS*s^X7W(>8g zmBDFcmbE7MRJmoX4|+#g*2ZAo7|YrmykV?mJs5mvyk%_-*162G9uE$!u&f=y4O1*@ zXYiY8mi0og^-Rm!6`V2KvR)59Gsm*_1nqg2wJ+G~D$Cj*ym5hL9SpvAjb$AU)>~{@ zp9Ra7Sk@Q8P1jr2vEX-0E$eu&?J~>yAvo)1%Q_W&c7=?sgv#$WcY-H$-v)CpctYQAGIxU~)PA$MA3P!Xuh}>9gycU* z-qaJ4|DJRUPe}fQ!0Dcl{1;u@ctY}@H6}b?f1tko@z+qdXz` z_hrX=Lh=uUPV|K2UwEAC3CTavH{BDGe`9U7CnWz!)?80W{*|Noo{;=AH48l<`FBQ^ zctY|IMJ)A%f_k`rHYTxP!$=|hI=?TeSmR#cr$=`Nc?+M9YSK8IuoO>^|-Z$?sh5@Py=-=5~5Q@>@?YctY}PE4w@)`MrbJJt6tQ@g7e| ze)6}^6Otd@?DvG^d+!H5A^GO%VNXcD`}LV8B;UUH!V{9OKaY7r@&&|kPe?uk{J|5F z58+-)&v1YEky{*Tp z6J{Q5p4P3}o41(noH+lhv)lYlKTqp?Y5AsfH-GBPHD4ZkT91*o*6bUl?K0=!X}w5V zO^;<#AamziB={?wZ$XV=bYR=qhg+Ut14JeoZnVvSkzZrjYI_jJ^^ zR3w>ko{o{V%{X7jcp05^+~zZ*vyP4p&FJEey4B1lJf5!3c;8%z-Eu*mlAEEM`wmG5 z&3VdAa3a-X)%Wxb3m;-7nS0;bU|N%wPV*(acl72PX4d!gv!gF>^JmBUoyohdR9&_+FXS<%qv^DG}}M;X3^!&rRm>rrR^O3)XoD( zrkkVf=z-sE>1ZXj(_@ZuhQ|j?YHbejCHy}B(*x!`%{BP;n`g{bF^6n^bV;O@)X5xj zz?{u*T<*D6(o8*>^fc#&u%o}2Q8d9hnUi;Yux*xe)?Yun=%jnWPrtQd-V7^gt2sz+ zfNb|5=LUGmG`Rt$azg#yZ8h7u3h$-&N^mYtqx@6tor}|HWW6h_T^2SWnFATIgJ?wR^8^;vBsH_niF44M`&WE?xs~*;9yHZG$c|o+G5A8~n2(noIBd?* z9MiA);2zHPUlBjNk(D&qke2h=$RQoR`Xk=CVo%rux*A^G+ zw}-3Oc22M1oLm*M;CuiQMxN*bugEa#Xdr(b`}y$sE}_X~55Io;s`xf|^0t|=Fn zSxFC@L*$${oH^%Xnzo-wr!?(8ld73dF66+&XHvYTlV{S?ntZLCTSczetD0(^N$+ZE zaVCADshgX^!p(zdQlx9N!fkf+3;lDNJNM+h3nv#lcgz0Im)~h_By;uZ4a@CeCEa2U zkxO|ECzE0&ZPb%_(rvzkS5|$#bB=TWElV`VxM; z_2WaX^p)Fw{oNeZ%^W4?9@oaXiNeB@t)xQJK-*{-_ z0`r==A8L**>S!hRH^(^l!(2VVQukm_rj>M)p5Ag!Z}fL{GMv+U_v;h)xfkrqk9Pm; zUa+sWZ@u0;JKkara_)w^^yobteShuK=22^|)`=Yt?lJeKxes>~wrc5In2z^;W zZr8yB@(A@M9Ne;Hqj_I*&?_UGm~%GQ`QBzHo0um`J!Uj#bLW^IW1O@3dHR#)$M8NZlQl0QD%9P_n#MgI7zd3}~A!P7W4G0GcTC$=P*;E4~K zXU0ZWR8$v}EX!Nd^2VMQb$(RGsJuk;*|fgJJS*94Eh)Zg9&c=ys3`Mh_uV`u`kR`g z>Y57@?!01KR)q74d3ul36SUnEjPiK$66KKS6mxQE=8%{;bLMi&v5B6js57S-7h`$D zxg=3hF;US`9n8DO2hV!11oK{1E^k1mo?D`xq?vM_)%7Hux1Kr48hVoYUNy}@_L<8O zj4>Bf&N<|~Vy;`QHdW5EYpqV^uP)VY>FHXF3vy1ayu<`gz}GFbqI)el-#T`c1Hyva zx|`d)Zq*afRt4~yuq?kcpsyyr6m_< ze5`Xx%+;~Z{@+A1Jyu_NG2FndW}Wo(T`jMTF@MY(yu)J+kQcSh6NOxq!qxJc zoP~LVyl_vyP+n{{f86(x*IqJz%=^d-&bYAZ8Oxbgp1HXh%{v##3-`23&YX6Uoc1c` z)Jo(9XH&FVUUR+*u}b9B2ev6H9ZU*zd=E{3owoIEeG;Ku1#I%Y@WoeU2 zE6U1CCr+9$xx8$0`S7%|Ni!x+o*<#DeE5_}`K&jk zjUHb%cFOSbv~ferMvWf-|M|tJm{C#nmKZrIEpyWFDWk_v$eJ*zJhk$+m_B)ubCbBY zNZ&~l#+ci@BCTlR&`Fo(P8nZXY_7}5zGJ6Ulon>T>)n>S$z0k0#Z&*kgJ9~=$>nli zSe7zsTh_8nkd+QEA2D>w*vX}nXG|=wXgNyk8VJKjkDqLY`9jI?D=nKaZrp_Nr9&r< zHqEdu%E~D>A!$E$#45 zw(T2Y2YjBE=9OONl|(zSzIioGnt7RSg;n#^u%qNfoSh;sOn0Un(aKKr)wF9jw*!ss z#5&2&fr-w6oy}Y11UlQb&CA59Z>l_PJ4N2bIn9Ru!&x*m?#Igvy=kdf}4Dfg~SIZe*PJ#Eh8 zzxEWnhR1H~t6@htcT871PF}{@jh*RnXG`a;Vdnln*W@sB20?jAPWy*hEQEQdwscR; z8=35g3-d{;A#ZcJ$oVCEW6b?*n#WgZC)t_GQxvpP#b6ZRa$E2+|8L&g0bkJN#~pO` z%j8N0?#Xi#H;~Iy`QSP0(zUdmnSAD<)X2ST=5BKD#>$Jz-Iru8dbqiTecqT(c1<%P z((Rf(%}z^9>ud)l7&!8V#trP6NoFaW|K<)fw@yu8^)$Q1xpqV&J6Kmv$vxeMcFlUS zeAVrmEzV>E)tpVDU9-MvoMW2Zz?@@rvK`~|*6ZXv*z2U(wNvb74di(t#++sy^A7S- zo(N*NP>FKe#M#aCE^}r}^X67|J$biYcAY#qNFE#Rai%!OyH6-`>Pi3L)a-~+&UFl$ ztD0)AMv7TA(!$E)QtY7IWO@tymzVN>as#K>waldp*@@<&n~>;U~Ug3XhMh>f4=|z^g$U(Wta_gO8Sltea9arR;8&)3^YVt3a)tSkaPcgnm z?yYVvW1gHkm-S!Si|I7dfzmYHg`wx8%$inZCO2-YfAG#q?(dv(n%&gAcRh1PDa!Zn z9F_9_;!){oNp{mlcI`TjTK6HwL+wAg%;uV!Tl_!0rvL2rNo$}Nng__)7yJM8i|^c0 z@}%{5Ed0Y;=${JuPwqqK!IW%QK4lw4zC?4+2==DtiS0ku@E_eUf9IV$nakol!qe;+ zqe3oPn)$$0`+Ru?CY|*IN?3d*8`$;b-bvGYM?WsB!_=w{<^E{pd?uUJCDm@x(5_#%%7L7~ z-+^pC88qzwISO-GYos+#PZbzx<_p6l=Yp801m`s6^GWA1C6C3V`tm+pxX#YimTTMG zT>a|Fb`4*)^ND4R6uZIsW~FqN*&x+UZ)i8DE5UuUIYK`Ftij{7j{7)uZY|TDDW}#- z-pzb=mTotwSLJBEQU2$nQtXE2+*0febFh5msZn{RTnO_X&V}H@=$)k}o1u4>GtCz= z=E5{K@7|!Zb9oxdwc$Wc@NZo%xma?Us@@!2lD~5adf5%@JLhdKP3QmSb-O`Yin*8# z?1pvz#l`&3F77|M@$H6b&UJL}H1}2xYh7J#(Hic(8)yIP+xKr?J45iV*Y2O)8UN(k zxo7^DJMcg7>|FMLe)vCoI5=j^Be+4HBO<{(V;If#%|p3<1Nn&QK849k=?Q$n_dh># zCG@iE=Q+;^?qPCr&Xb_~6jJ&0@Xte?!+{uY@MY*^C?ZtC$I`hS`d{9ammJ@yxq! zPD|$lO zo7J;)*qL|CEX*$LQ&4Q)xhSWwI48UEEf@4PCtA{{sHAV-0(nDe-@Ji2`K7r9g}pP2 z-E%Z2b@sb=&o9X8RhpeyoLSnZq<8n6Lb)CVh3`c^_^Ix$HTGnMGADIk#Kyq8_E)OLB9~=@;b< z&Z#`)zg)At-g0X??<2Ql_w=e4G_Ox-31{3Z@FZ- zRjznWaZhgF(!M} z$tlSx%{8}F<(v9u7UmTXs+@wlcV?eKde@yf3FmGrDkyR;LAFs{c>&rw=g+m!_sh*N zkB`!#g52EFv)(zQ<5};WmD#7XxG=L%QSZEB=adU`GP4IcSEl<}U<->f%?UYowYh;6 zHs@JTlvP?(Twrd~9K%uXL-)2h>qM$No+_`f>dDM^&bhRpZ%&`ew?VmkVP21(#eK{z zT3VD-Tr7`e&N??Mzn61yTeoo^Ic=SDbk01T}!0shQ?yYPd8&#i=+=r52HaD_7xaIb!a(LlD^N=nr=$})Vn_n>CuV-4=r$^<} zrg4?oyYe0K`kE&*y^H&rr<1DBr_NO>G7>7EBwJP9VBM?SIC2M_IcwK@l{cF^!rUaK zIRmqDa>;$ zQ7TVnl{Z~RtI7wsd8k|ePyWcC-xzRy)azVR^S~ZHW!$(Kl^5E1oaGeco&9*^Dw*f^ z-UWqnKg$!a`{dBddE||qFn(mRc{X%f8*{mxlg}`(aICp=iVDtr{F9F-m2cB0^unC{ z9Op@24$e6ns7pw0Ors<(*S)pfb7@!QT%0E~x!2{X)A=x|m+~x-Je!neW@VKWW@hPg zW98-PX+D4s$TU~9IInk(x%-{d=upWgtI8SnHFthdVU_`!nN^(E-~C|LuFA(y9_{9% zevdxRM||g|X>Hy`UdcS`qej)IoHI{_899|Ccd9-%%}vGgcz!{VK09=%JVSFgxVK<;UdeIp@QTqR$CnRJHoq1!sq*aP zfl`obPR<}X^W1;txg{&BptPrX&Z|6t+opFxwtMN#rxTTL%*x5nFUij=G>@Jhc}3=d zA|C^}BBlod3tGfzv9yDp6(|D zXMg6*+UTV{ zi)E$nzue~B|5ZMd&Nu$g2;kg%WcKczdFI@WLi33lH-~wYI%j(3k(`m?_~_B6Bsr^N z$7J~xt(F0CBp(&X~#spDF=HevFpDdUEj zmm|hb7&C^k@$ zCUz7>u^@H@3nF6d=YD4Yu4LeS-|u{XoV8BYO78u;W_F!xm*?3t6L(m#eLD``BS8VeXNa>1AgnyVA>TU)ZH^ zVELtXwjFBSC@qgTV0LKHL08glhbdF7+*muK^t1~RyGnJZ{IVzTswJ9JaLoxR!>yt|+voL~sQXtY<>DFW)u|EfpM9%Z`IN*)5W$kdtkDg{@mo zo3ewiy%=Q^E#HFfLU4#SV=#uDB@+YoQU}0}V@Zdv#A{yO;5+I%UPr|jk(UOeTEjLm5HyE-*_!~%FH+s< zr~K;9n!?&eUDH0XIcz}4wY?L_uFew!L6bCrvdf+o3~_`_y39;m99tVoS7x@q2UD|k zP1;yVBe<(pJ9;I&Nj$Z@aaqV?Lp=m9M?N`?Vi-g%X8fh$!8I_+{ta!f_~Ps zkym5~(qN5_*spNXU9Ob948Y_D`2V4)mtUA)d}KScT&fPad5O0v9&z$1I|l#f4rI-8 z+h`ZM{ikekg0=3`Ew``j9rE*3S7qK5BcH+n=mOD1piwf=9ORoP%Zlvmm{?7YqHB5OstAoy!Io6V3 z)od%2Ej8E2$ls@ImdVbRbD@>e`y64&nDe){jtpo$Me;)Dlpm#E_ zz}n3nyCj}s&E~SnmF+M2{f6|h?lIe#nxLjwHPEz_9PxQnxH|8iLIbbdgPwTYn9j@c9|4x4{MhtZ4Y-&bd8fCz4{gQ zwnvgqur%Ou%DWYE?8qFNJlZat%9_Hixt5rLowE}Iu6gD_(27btl(a+H#dP@=a^1a& zJ{fnBV*L<9I^`Ayoq*CPoh@|9~@S5OPOf?UIn4aLOVB}wRl z#IesUqH9<2l;kFXb+H!a*)hb9>Ae%%sq9(3to3TGeYNP>Zb=_G`2XsS_8mqJn>s47 zMO_<>g><`OZu`Kkpc|S;Si^j4h*>LjNPd^xUghKQXrJ!RY}fp!hyAGbQrT;hm!DVu zy5zWyZsw#;jo=)ac%g${dN-Kd*_~+6Ay(qjsl(WdCg+WxJo2KvlCi_5jz>sWpFKOr^=&5>Iq0$P zn%jR!Ubo&l-6VHdCl>xcPo6=$j4e^tv6q-+dCzx_^}{9aY~_7CZgT{?$q|RAvX;D? zV%dgHHnOZ?tgWBulupc+V|@A9E$Cr(54tvB;z_Q%m8DLcj?E4;JI{8+|9<}?=uR#_ zSN+FedZVj#r|Mc_d~m&=C@q3> z=n;#=0+b!d%QhGW+U9U=N1n(mf?c8P)SB2@$=#?45&qkmx!hK36?HgjMH5{jWnE{? zGjZ#OV+PQ@$C}}_o4fwF&A48MERw=o%{b&K~~xh zpmu&!BSE)$XoUrh7?y%D>=M`Zh7NXdlXTU?gJn0PIQs^zm_Sckr9>-D`(4r+Cd+cf z-5afXpKe9niu(myhK7>s{&&+2nj0)-d+Y4BTX~7wEQyC*D~Jb^t~-wClSwRIj!s*y zjg$bc4>U0l^wYXQ8bLY9-JhDO>%-5tU5L&oW*V#;#~|&rNj<4YHeI+>O3c_^fU;#z z?5lPL?48@wU0d4zWY;nOYoAT($kkfq1ii3svO!~v#j_g>x)e%Wrf`n|nWhdq!X?+> zVodE1!R1t0|E3)bxF*sOmb-~LLAPvT&0H^NVj#E_XOixqe&orlY%fmU@e*U&byO&E z5GY%qye_$2yC+=<1Y6$S7j)Atzd=^sn8;~WcC2)JP-41?eoos=?hKK%-{f|;YySS$ z0zbn0q{R!iL$E)wKI|6GX}cADbVq06x+_07`J#p~c&b~Zq&AA3Rkd}46N`H|XiPB6 z?!gthb?%jImxMZYXek4ET{|4nOf~g+&B|WAWcSLC)~``IQ)dhj(Ux;l$=5pOSjSn}R%KfRU8YHII0zabiH(zdS(|7n_OqMF z?lyX{?hCU>K|j5_iFou`!kro2ZFi1f+_q)R_FZzj71=)B(Yo7o#^WKkDn~!P{DtXK zY_|#R2xC35x!sbw_1vp-WWP($?g^R!N1S^T>sa1J8{C3m?&YV+BU(9b^0p)NvDISP z++>1QN@9rPaL@}nWC%@ZCY*FwFX&lhFIKQC7TOEnzwFiNmuszcj;=?I={kwr*)`Zc zzt{h|+o>(bVwGKF1udP#tLge9nONeq z(=E6BJrM4-J9;B@A5wO2(QQvoDCN@#UY&l$J&SZQEW2pPv5Ql;(q+A?+1agzOe)`% z?a0GTk|Wz<`PLgrGseA@Bh)D`@AS+j?nXfFq>C~;UNmgvh!J)#uQwm_PTU*dhzdeG~S<^ndNgzCz*3N)?X@WhQ;7-F>FLeWlFVu{r)VsdK$+qt`{|rQ8$_<(_6w zDsdkZ4~0*$L9cDIuFb9W(Jho()$f`XNsq;&)x$Ny8IfAy+Tl9kW5adB^->y!?dz!i z<0lzKLqGqU{Dg@6G;`8VM4!S3Mcjv(lYS!hL1z23f6`AhRK-%0vZn=)f1i}y2S zID((x@f}IoJ>K2EJtX<@HA&e${-E24iJxG6_mu-=_xSfonMYiWgvw@=!1kpB$q(D( zWi!&_M}BifVqYnn{1XY)NIb)Bb@$rGZF^=X zJ;AL@-ch;7QF+Kw`J$up6-VV8j>@+kl^;ARuRbboI4bj@^~5_Q8chi`8lnB|e>BPe z%Wd59{WB*!CwXtR`zPg(WxIQVWqb0G=V$HLRiPp=<*{e`P-UCs=JE*4+o zs*ShFRhypsD!23op^*E6w)BQJeOK*qw_CZ#-B+@?=~hwBwwjV<-+yG^7vQG{-pY=>Yu9a+gsdny8j64>M^R-RBNl&S3O?!WL5jN zx5RjDRL@e)Q!P|2R_&uYNVPs!LSwP+h6IO7$_-b*k%C zUs8Qp^-b0HR6kbzLUo_&&#I-Wb`no)hg92-6WdX>y6Um24OLH6%~oxrdbVmu)h?>N zR0pb-sE$@0uj-CBZvI!P&Q`r%^%m7-s&}bApt@Rho$3bF&8qHr<);6(>IbTys(!8d zgX$sGKUGuQam>a~Q+3BTmorrBsUEM|RJEn*>8iP^1**lWeO1p@9ie)m>Lk_6RA;Ep zRlP}dk?L~Qm8uV^KCb$V>Wiw|RNqj2SM?*+&sD!uJ)ruV>OZQU9pBw{si;~_wT@~7 z)h4Q^sJ2!;OEvNJPBxt)<({eoREMgLQXQu{RrN~MS*r6?7pN{(y;Jpm)kjs``O2-w zdeu#;uc+=&eP4Bt>Q}1YtNx<;hicfqBgaiQrdnCGrs{F3jZ~YdwpKkywLrCp>Oj@u zs$*5Bs!mg#t2$qGnd&{N534?@`n>8k)wfhXQ2k7GpXx8Ff2n$Q!gA|dNi{aG{ubcU$9>u;AQs$Q--OZ5iTMXD=QA5dMR`mE|E)z?(tRsBTuYt^4r zOI5>mo#K`wUA4MuOVv(xz2P43r8>s06I`CEdcB?3U0$O4s9lb`{H*F*c7k{LBh{bn za@^&=Ra@Jz%Xz9-+IO(Ie4Xkh`=Vr*-%^d)HHgbKRJ++VjLU;mZ*36dyH!8T3i3Cq znT> z8{~6U7u&bzx#_J`{rJovf2Z2;oFJc~IyyJVQ&m^z1$n*dp^iZg=Lhxlf}q+P$rAIK z(K)C$s&4BNUw>X{`$EmXaFc#v;a-99qN@2OTA9pqzGdtVUb64l$r2KfQiz2k!XgKFc6 zL2ju!c5;yI3)T|rwRUPyUsNrJuTXvRrXath`iEWMy4S~F5Y%=HgW6T~nngig zsQUVnAn#U<-xlQhs{NM-d8F!!6+wPj^~<}0{IlvwD}&rdb;5l?zDo6}2ZFp=^{-Vy zPJ1Y*?H>thvFf#}gS<%f%{4*(NVWPCL2jTra9xl`sowQ;kRMh3+Aj3n_W4D%>4qSm zraI|`AWv6)W@C`Is{XSn$Q3pRwZqn+_E4Soa*&s(?sz50pQzS+J;+(AgWnAD7}a}r z1o<)5Z{G>>ud2=83-TGNQ{E5qOx5Rh2l-{y(8obOMm2v=kb9}#us6udRNwhL$e*g# z`YOoBtDg5wkS|od_q!lJuDWl3kbhIn{xQgBsa|{_$g@;891QX+swuw)xw2}(Z$a*( zdeiSgzFqZQYhbz8^E1^t{{;C2)uGnE<{rOD^?v(j2QELM`h7IWzpJ*e2AX^P9Mwzh z{~)+LNA(5!hX^jerW&mjU`_SaL>O(byxKuf1z5}{(FLZ{6y7Z)(~`g zyy}DY{}fzar~0G)V+EK0RBe?RPG88anFB4HT8rbS5xhBVvq-@uC*`n zch7%O^)=O9u6m)+SIP%mjoUxtQ2kvz+AQEP)ni<>>D5xMtJ*-ksdBdJsp9RFJE#_l z_f;LPIzja+)p@E*RPR-NT=fOjS6sE_e?#>h@lRc~_54Nk1nbasIa{@Z>ZPhPRoAJ0 ztNNE}j(yd?8^5FKC8{%2uT#B4^&QoZR4d!ps8-W{Y>?cs&8Mt?xt5qwV7(J>J-&$RX3<^Ro$&x$-cqdO(#RONOhX(0@ZD* zf2mfnZwODUw`y0_p{k2iSE#r|gr-K4rr^)1z% zsvoQFRsBx&2i3!>f2c<6`^eq=ebp+e)m395J8s!_s;F8`HAA(5>hY>gRkKyQsCHNF zr#eV=nCkhe6I7?DUZFZ&^={SsR3A}Yqx!V!deyC}cA879#}3tZRXa(iPtL|3)MD;7x?^F+}9#;KFH6A5Tzi$8je|uiGJ?H58CV%I)doA6M+xOG# zx1IgEpG@nd-D@M-;l+K;apKp_&m99;1{(}bsAT_6$c{JsFx1OH^7KL`eG@wXx#>Bt z+%(Hoa9g%s6fuAK3JE)pkR{50ANHY4Y^0wduL->Xxsv{j$F6Y}k$Cd~iRjhlNAe zHwuQ`U-y{%-Kfg*PMd50;KUd|JnszyZkV6h_Pk_Q-F)58EB2ebeDjmm*K{abz7K8K zT%KSh@$-yL?{tDy=H+VA%N{yp&l_sM4nLtf_Uq>Bw!51r`-TmMdd~}oUUdWdVR}_9 zCqM5lTfTif$tus|yTV5_AAd@w{p7UCZrwJ!McWo_Z8$qSC+TnN)~#GRt>vjL+%t!! zPw&_zKluy&ZBHnhuA5c62NHAfg6-ENRNIcE&AvNOys_J?HM>eTO#Gy@)%=VD_0vBo zZ95}8zukcz*VN7LcsQlkG5HJgx0TM$e!6H|Y3%N8rCYLhl}2+yC;$23=!Q=eJy}ru zqHU$2ssj>#mnHswAbXXX~D~-p%TV#cW~I`m+g7C7R~Pba_Nrjg+(vhny^$Cj%s$cMcoZx!UO4!+*V7d}w2@oh3HE zmTnD;56sBhWb-RHxNh<$o8!o`DYidYEo+P$yXvaM-|rHCPrPt&SI5Q{+Ow-v8+!8S zJHwlQX?Ok~iRq3i*k3ZL^XQ_{g>Joy56y_|FWFkUqh$Y>{wblK+g($9=*h`jZLTFn zMV+@MZS}0gI^~zmdvsQbBZ=3bU*a`5r|hwhN<-Q04lmEK$8)M?Z7Th~%FaasWVVyH^ZcE{AIlp`)^S8ZxX{Z?uvwG zH2R^(@hzViy5N~#`ei=xNu8^Tf4^bkpo`-zV-IZmqux2Y>MyQ4=Q|sr-P3aqq;#w} zKXgj??F&Av^5N_=zUVoASIhI>3#FvY*lW`n^>x|>b5@U9Kk1ioXP*9R@qN>KR_bxX zXz%uich9O{`;EPW4!^eN*PE91J*&sAxi<_fe6(X8R}me8fli+YV3sU77e> z(7D(6b0coLYwTF^r0s>#oQk)9P~UHoyW7vobyKMtI`PjBKO57omD|$2OEc?MvEz*! zs#|wf`(UV6-Jn)it)f~{HKrO()CP$oLU3HTJ2CuO;%@`DL{&=?fA3EGeQ{@|E#KgX zZLeH+Tw2r1j*h)|mc%lvWc3(j%UZQoVfCTiN9`O|Vf4~q8}zA~X-AMr(X4ovH%hjT zddbcUMWf!ewQ@(1Iy#EfF4$6b6v-$XKFRh^w=b@4pZV{*mo3`9WcA|DeqVg+b#9-X zJGy_Zn{Iz=aO(bcpFVf?Q#;ug?W%8v+aDLK*tBTC)^KTqt~=}>R;0{K-VY=BYs=;l z$zPK+ygF(4k)+{=%7#<2Y)QkzM>$WN5t&){c5X2A3$sB!_voE`Y_X%{7h{H)>y>9sE1KSUdf|-3Yv7hIIrnThy~viY!4^9fupYrO798}mE-O6W z=H}L7Z+wGh)%8qqWJ0tBao72q1*6{L&6%Fe=yl}YN`enzf(G7-n?&OxO zs?9xfr!8aXq(46lFSFxd``GA#g_~`;Hru&tK;eu`SNk{U*QI~A{#|X@<)QZ5UBm5q zcd?;%F7@o(!VPD3=xl#On{DcwZR)H!%QK^~TM|1j)#y}I(7B*6I19RM=d#=WoeB$V z+4c_Y^k2980Nd_cX66>P@7%sHFR|U*AI$0zv;Ep$m&|tdcS~j!^J(~~vTfR@-NByO zb~el{IJ~u5T9@~nSz)`bup{1<>@j=)+d0MUAJdjKIq=$F&lX?ZddtAKCN27Xxt&wi z-`R29LzVxy|K7K1wrze&&bo2e&ggMP+Qr{|ysY`j6VB|?F#Utbz+0Z4IP9g1AG&6C z#ZcIt3+;EN+Xwe_SwHTc(_VV+tNSlMrS7`dHg7bxv1KSbGvtSs74Dc*v@!prc6O!P z&i+Bo^f6yNm38G)zrDQX!WTE6`Oxb1jUVl>$L4?A$77#a(dG7wpPJYA<@zb#e{lPq z`}U4K5U+H~)tSp*p84rH!9Kh|Ub>1ka(YC!Jy91v^W6 zjH;SAMpW%wHL-;xm0$)oc0poWB--yD+Ei zLtWRMcBqRx2Mi7s|KK0Lz%CB2f`W5vr>|c=b>*`5vPquxn zqg`+GjAivM=u>F>Wp~>vLk(@8tT6hvvg2H}UfnuxFR5V1K3(}Av7dH2YCrwIH9DMR zbi=GuZSHpbA6hheh#Bbo%rVQNGBc)HQMHPhdY(*eVy0G4c-h!YttC_ICTf;VBeP1w z#CBZub{|K{4YStq@Ad*zioe_Gvh-Q2w? z?)B=v@3ucFU2Ao<=ch!yY1U~Jx!HOQQi^L2O(6fEwf9qE z-b)U~{DGFDQO|u0J|*h^Si_#a%bL}Zrqy!o>5(ro?N4^~-Zt#rY=2T?)=S_=ue8Bv zQ6=~P!2OLW7W`?|t)b!HWBmdt25lt2xlJqTKWPi<`8%zzAk{x?!@hrwO+Mz&vf(s; zf;~Uox29gGfSc)U>#{S{7dYaHT~SW)}i4q&ay65e~$GW*7lp*maF5t|0#Z~U*Gy!>-vpt z`t^L*bzR@T#2(G`(`;%D{HZpVhQ8~T%kteDU>f;f+3@jxb?fXI;qS1GI?`Wm!`uB= zZECOh-`Fz0>esOD-q-vbyLt7x|F3OWgk#HX zDoew$F}5hn!m$qa*lpq1EL)`8!?9;8{aO8(Zpb(bzP5^^2piMmDkT(b$c) zy?aDsH{1MrMq`g!=@pH&vibFn#wyzgeWJ0m&C$Nm*h+hC`$c1~*o^u|V<(uG18fAF z*uZG)G}{XXMPvQ#Wg8rgRX2CmL}OEIA*y?^%JwSO@M3LkOI+&3hT6uu%!~bL6T94t z9dGbsFLu63`-vB;V~_3eV$YdqpL(%(4%7K0+yWb}ET!mOqo5T7FvFWDmU6o@q%%Zz1$9mYp-%~lZ!xm{}<=8A+>3b{3 z>e)2!s~j6_>u`VN*hEX$R*P*mL9eS8+i0U#IU#n2+Z|4b^)V+VWW=JjEE6+gXV{WW z%82c;*-p-g{b0|Wk`Y^G8*6GttfH;v#Tl`?Z4Q@Y#J;f6FU^Q8wk>#BM(i~k{ql_1 zO}6E)$cTMwulto5v9`7jS7pSWGhe1<#ENb7=^3$OZ9~q;h>f&4%rt0IX}3H!!e*Ph zJm&sYdHdzDNoGig<*{Klm5$3}f7$}(FOS(B`cS9ku@1H+x^Iq6x5s*Hj(u;_9J()d zw#}hrUu={u?y!Bak>u~D^1Y{4#f1Hah*;reFMcG)HhyMd*)UiME+Lun72Del8aX=`m3 zQ8%#5*1~fG-(uHuz8P~XmhsXJ}X$3z{k z6!jW=XPIM_+h>Qo6KdXWEE=wFF(>3TQLJaNMaVl*@i>buL*7Y>buG3Ec_%9#Yw^^O z*Hp2N#nvIOnPP2=Z9-mi#ab5IhP+c0Gc2AK^0F0cTFkM<%2BT2vMpB&mlD@R?n<;zpH zPnWfCVawM+ImL2ITfUCU_P^EJx3uNUSGL!>O4Mr<8Dg)0)qhPV@A&FYfU0NOZtivR z&vN^l8B*j8F~t&wbkV3Xq^qI~>82<{iWOx@cSRY}Ls5qGRFomT6lF+nMH$jZ5kvYa zV@N+`4C$|oAp?{#WS}yJ3{u9B!O9qNt}=$4r;H&(lrdzeGKQ2WW5_UN3>mJBAtRJA zWTY~NoUe=_qm(gZv@(W_QO1x9lriK&<-m}_$V_|vtH$jJ=5-DX`P3OQ)_3MOLne4L zO`n7z6E&&~nWQK~CM(L2DT*>=s-g_JSW$*tq9{WyRg@u@Daw$`6*1%rWemAe8AGm8 z#*k^s7&2WMLuM#r$V_Dnxmp=RW+`LHY-J3Yql_WfC}YT6WemAi8AGm9#*lf+7;?Qb zhTNcxAvY>x$W6)^a;`={I4> zVvQ<8mMF@QrHV3SnW7B2O;Lv2t|&v6E6R{N6lKT?MHzCZB8J?hj3IX`W5_+q7_w3s zL+(|^ko%M| zhOAY_kSCNepH85noT^e~$`OX|?$aCISyI4&avRyqKF||l`&+SGKRdYj3L{VG2|6x z40%-k@D`Uv_${6y4GKT!9j3GZM zW5@wz4Eb3ZLk=oq$S=wma!46NepSYh!^#-)n=*!!Dr3m+${6y8GKT!Aj3Iw1W60mi z81j!YhWx7>81hLZ-CB25e|J{wNf;6jTO-k0dA?I8R4wX7!`2Y77ME+ycwvoQ-?Cly zrjqMfw##y#e4J&wERT`vTDHsbH1e^Q?Xo70I`k;zhlE8ZF}^H1nJkN%l4VgdvMg#&mPMzKWl=U+7Uhs- zQ46vxYDvbTRsbwI6@W#p0a(-qfJJQqSaccyi%th%(HQ_NIun3JX92M2YycLW1Hhto z04&M{U{QMj7Uco3r~?3tIs&jLAAm)j09aH2z@kDxV9^QT$YK*Dp6xoBn#iKttyjhC z9QK`G&Z2H%?`ab&VNo&T%cAaNS=56pi+Yk}Q7^JA>P?nKeaNz?FIg7#Bg>-xWGos0 zz@mWwEE)vBqQL+xIv0RN=K-*22mp(Q0SWMe_hybUgrzZUA7>jQ}jV34ld6 z1F&d50E-p?u;>;57A*t>7EKIC8d_&{e7?JIo+OL*Ig4%$`_3(Q>jZx`Ql>R*+@Uon%>b7g-kFO_oLXkg;eb0E_MgV9|X5EV>_nMGpY5 z=s^G$tpZ@tLjWv#7=T5O0I=v$02ZwVV9{d$ELsD=qQ?PPv=)FxPXMs!NdOkD17Oip z04#bMfJM&$0*e-hBcn}_csF-lv_uw7PPE0szVpjj^nBR6&hFDBEP8?QWzmadS+tQX zi(VqjqD^F3w3#f6wvc7fR94@q8!F23d5W-6r$)gnj3iv*`1%_m*`7B`o@a@nzAMWLfkTSr&awmPOx? zWzn}}S@a!Q7VRU;qWxr9^gS7iegI(6j{q$C34lch09f=h0E-R+u;>>6799d$(XRk3 zIt;*~-vC%t3c#Y@0a)}00E_+vV9{RyEczROMgIV>=wAR9*(XPX+lp8e24GPNAh2j} zIC97YiQi=RMZM2tQHI?q_97|1^UGP}r+76Q%c2pU zN@Q77nJkN{kY!O-G8V-FSX2#wMb!aVR0DuTH33+Z0l=bK04%Bvz@j<;EIJl|MRfsK zbQ}PS>H)B*J^+g{0a(-kfJF@fSd<08qDBBLIv#*UjR9D60wA!+ONpFrg2Y?e4RJ3u zC1~mQv93g~Ns90MauzjB@dh=KMa>vr7Bwf!qEpDSD4Q&ca>%l%1z8rgB+H^!WLb17 zSr)Y>V^JFb7PSRn(P;oIIvs#TX8^G1OaK<01;C=S0a$bn0E^lIuqYRRMePAtln20~ z4gf6b2*9Fz02XxuU{L`8iwXf))ER(9MF1@70thTRDJ3$)1c|?5?_u#ymPLKtor|t1 zzVpjj)FZ{a`y^S^lksIyFS0D^O_oJ{$g-#}Sr+vp%cA~dSu}twiw2Tq(I7Gw4F+J* zxd1FW4}e8O09Z5>fJG$$EE)#DqTv868UetfkpL_@AAm)p09Z5{fJI{fSabmZi!KCU z(O3W$T?D|QaR4kD55S@c04$ma2rMd2iEJ}L;^$h|kk?%n&331^Nh!Yb%UN`Biua9u zI684%bP40jqD#rL=rXb_x|}SFt{}^zE6K9xDzYq^MwUg>$+Bn$8H;8Du;^+47R>@+ z(QE(~%>iK1H2^G{3&5gl0a$b$0E^}Uu;_XK7To~Aq8kBNbQ1uJZU$h{d;k_L0ASHA z04!Pvz@l3LShNU$MT-G}MN?8D6`Pqwb6v0FR9V!_9hjD+_|7k9(d{W-vr}Zza>kcM zcaUY#3bHJ^lPrtwBFmz?$+GAkvMgFjmPPlHWzl_PEV>_nMGpY5=s^G$tpZ@tLjWv# z7=T5O0I=v$02ZwVV9{d$ELsD=qQ?PPv=)FxPXMs!NdOkD17Oip04#bMfJM&$u;^I; z7Ci^RqV<5lqGc(Oo+e1VioG+#yG<5Vu{ZK~8&Z7dm$PVNiZ?k&7QMvyvS<@o7HuZW zqAg@uw3RH2wvlDg%Vb%!oh*x9A13u;_gN7JUG~qTK*2`VfFc9|5rFV*nO?0>Gj@04(|xfJJ)& zfkiK*M3$N$@m1DM?Y$_Ao_Fu=_$W02ciXz@mQuSoALdi$W1K+p#DNz@iiY7DWJ96a`?B2M8?sA|i`k zQJgG`s*z<;but#!0ANu~02XBcu&5RQi)sU~s15*&js;**T>usx2f(6w04%Bxz@kh5 z7Bv81Q9}S0WdX3L5de#h2VhZS02ZA9z@jDqEIJW@MJE9Qi(-*Tqt<58^{$I3EfTc! zE2daDIpRCNoJFTZypC;UQ8wetq8zd;YC)DoEy=Q|6)6s4S+?(fWV?=k;nxmNcES`jchR0J1C^NR~x|$g*fKSr(m3mPO~0v1kYYi-rQQs04sT z!vI(`9Dqe509Z51Hhtd09Z5^fJN5=u;@Af z7R>`-(e(f^?h z0l-i?%SnEZRzzMcc@-=w-4j+D?{5uaITY zt7KX98d(;-PL@S)kg@1Z02aLkz@i-hEP5M&MehKxXeR)R-UVRMdjKrj1;C>B0a)|_ z0E>15u;@bo7JUT3qK^Ss^a%iq_5iTxQveq21z^!<04(|(fJI*b0*hXXM6NbL;x+B9 zMBXM@WZxWU4Yr8y{Bjn38}U}=$)fKVUl#2n%cA{cS@bys*+_f02b8)U{QSl7G(mkr~v?r8UnB=3xGw909bT90E-#}u;>H; z7BvB2(TM;oIthS9Cj+pkDFBO_0RoFEL?e~*&7%4C$z-o$G-&CcZXXKrnn!)-m$Rsa zHTDZ+QA@^`MXkuP=v1;SYE70!ZOF2yEm;&WVA0tCEIJ2( zMeP7slncP3_5du(17J}H02XxwU{O8*i#h?Yr~rUPg#aw-48Woy02XxtU{O~97Igz) zQ856Ex&yGN2LOwD0s@P&qmkYwNW8CW>F3CzH|@I@yk1e?`Qwg zMV9~qi~2+(x0xXEXr_tNR~FTAN?jWDonOwPE2G}}F0$w<#+OCY$g*fUSr*M8%c7ZN zS#&j77R@5dqS<6wG>0sUt|4R5TmTkb3&5i509Z5+fJN5>u;>N=7TpNIqMHC%bTa^p z<^!;30RW3`0btQW02bW}z@kL}ELse}q9p(N~%jMR!NNaIq}9hw)|6O0q1vmn@6!Bg>-u$+GAHvMhR#EQ?l= zWzj=qS@bX&iyi@B(W3w?S`EOW#{gKg27pD61F&c<0E?agV9}ERELsP^qNe~@^fUmA zo&jLdvj8l54uD1L0a&yFfJM&(u;>K<7QG0-qKyD7dI=C%bZ0cu*aV3`RoTS3OBU6$ z57v8|qQ3LXS+p(cb?PCDUS@n*w4E%AULnh(SIM&IHL@&voh*yqAj_gR$+GAzvMky` z#-g_YSo976i*^FA=v@F7y$8UeT>vb4AAm(40I+B`0E<2ZV9`eaEczILMV|n$Xb%93 zJ_TUWUH}$-2Ed}v0a)|}0E@l^V9{3qEczM{ShOV?8Eb;XA99yMTV>H16)k)d^_^eN zqWw|t#$K}Md&ZYVKage7k7QZ&6Im7=Aj_hk$+GAmSr+|5mPLoivglVb799p)(Qg1O zDg|KC?*J_N1As+;0W02ciXz@mQuSoALdi|k|B!JFir~)9c=(}iStqBqz?z*e@$)W<+(y!?G&M#+C70=t* zM;29Od|4DH%c5#zSyY`Yi)xT%QBATe${@?4T4Y&Nn=Fg!kg@1k02b8+V9{{^EUE{< zqWS9h0{|8^1Yl7X0E-#{u;_RI7BvQ7(Fp)7Y68Hb69HIs5&(-%24GQB02Va^ zU{P}b$D&gJSdE7PV%4S=5Fs zi`tT9(P?B^bUIlUok5mGXOd;nS!7vsHdz*(L&lShWzitUmqmlgvglm0EIN-Yi-wS8 z(NMB1Dk00FVPsh}oGgn*kg;ea0E^BCV9_W57L5jA(HH<0T>!wM3jtU(7Jx+;0kCKs z0E@;0uxJ7RizWiFXc7R6CIhf&3IL0y0}02W;Wz@ke5SacZxi!KKQ7WMZcvrUkA zSNB220kWuORSQ>mzVpjjG~M&=8!U@vFup9BNtQ)dlV#B?vMicSmPK>OvgjJJESgJ} zMc0yL(RE}jng_t5>j7AF0|1L|1Yprk04%y0fJO5GShN6uMYjO3XdwWLZUtb`A^;XG z24K+=02VC;V9_!F7TpHGqT2yjv>bp%cL1v;=Q z0$|bC04(|jfJNT|u;@ELVA0E7q^}7QZ|dG^yEc%Tsi%Q8@^g95H{s3Unp8zcS3xGv`1F+~H z02ciVz@kv9TE|!v24GPN0E;33EQ$iK$OB+eDgcXo02ajnSd<39qI3WjRRCa7MF18Z z1Hht6fWV^fy~uJCB)-OVSN|Z3*1N0g%BjBd%UM({)q8%VEUM1H;7BvB2(TM;oIthS9Cj+pkDFBO_0kEh!0EFVO7)#z&Z4%dUSzZ^I*svV(dlGabOu=#ok^BOXOU&m*<@LC z4p|npBg>*(vMg#(#-cm`7Igq%QAYq4Ei zHvkqD1F)z&0E>D6u&5^hi+TaDs5bzM`T($~F93`B0kEh)Ah4))YNUw?5`WX3#M;QB zeXa{~K&tQjau%JN>J?rfi_T+wSu}(!i-wYAQ3+WV4I|5<;bd7ff-H+hl4a5PWLY$d zj76gXSTqKJMHc|D=t2M%jRj!QMF1=s2f(8704$mSz@mu&ESdzsqR9X(ngYP0sQ@gx z7=T5W0I=v%02W;az@p0mSabydi>?G<(N%!JqCu&VaVALoYWD>XgJsdr?jmVgs_*=A z7G0g{-8@zn&0>66G@C4o=8$F4HDp;dmn@5}CCj4g$g*f2Sr%PSmPI#^vFJts7TpBE zqMHF&G#`LP3jkPj3jm820-02VC*V9{a#7A*l_(NX{wEdyZDZ2&B~9e_p40a$bg z0E<=tu;@+z7TpEFqPqcDbPph~Xhv$}NfRV~MV5&(Qx;w64ooXkedm|6=z&!4y>YVW zLB^LwtH`qGA+jubm@JDPAi}5v z6ab5!24K-M04#bIfJM&%uxLF1i#7nT=y?DZy#Tb-j-F%c6VTyZ5)J`pz$B(d((+u@hy{8;mcD-XzPS zx5%<+2U!-qO_oLPkY&+MvMhR+EQ{VF%c5OmEP5Y+MIQjLXg2_hJ_KOVM*uAP7=T5e z0I+Be0E<2aV9{Ox7JUZ5qR#? zEQ{)sWl<&>iy8p1s38E0vH)1r2!KV$1F)zu0E z832o#1F+~602XBfuqX$BMJ)hW)DnP2tpHebDgcXG0|JYx`;pg8kob7lMO4ENTKcQq z8Lf@|k5lu@S#*Z){cwpaI+O8b(OG0!bT(NQokNyI?Z~nymn@6glVwpJSr&C5%c72C zEXoI9Q6~Tv6#%fP5P(IU0a#Q7z@jbyEb0otqHX{zDh6OtcK{ak0ANv102cKEU{P-X z7WDyOQC|QS^#fp0e*hK@0ASHT02U1b1Qwm7MZ4WS{nKSp$4m=@ec$=zEE?*2 zEiacvC5$hNhLL5_aI!2KL6$`$$+GBtvMd@!mPMnGk60a$by0E;dMV9^x-EV>ea zMOOi^Xc_>ErUS5O1|YELJU`Ok1c{G!_tA#PqT&V?X8OMK%ULwX_b$6q7G1;mvS=<@ z7F|o0Mc0vK(LAy&x}GeHZXnB|8_BZhCbBHLnT$pA0a&yEfJL_euxKFwi*5yA(INmA zEe2rG5z^!K02bW_z@pm$ShO5~MRx$OXaxX^?gU`bT>vb)8-PXk0I+B!0E_Mg zV9|Ymz@k}xWQ7S5-{ZQ7X3L_z?r!Y;zVG~U7Cq#9FHVz14>P_jdW0;C9wp17)nr-p z7+DsrAGj@04(|xfJJ)&So9eHi#`Wn(H8(L`VxRe zUjeY_YXBB~1Hhth0a)}M0E_kkuxLL3i@pb7(GLJD`VoLdKLG-Z-tZ$QnIQ2d?q7er zDT_XHZ{VWqet5m@JEaBg>*vvMlF(Z2vJ3dPiH$D%L*i&6ks6aipS6o5q@0E^77F7aZQDp!YRRLg8RR9*n0a#QGfJM~-fkg-X$OIE4Ug{e6zsREV+ztL3G2i*+ zEUF#z7R-@Fbr@e39ZQx)b;+{mII=9NN0vqP$+9SuEQ=bDWl=-2EXpEdQ6m5r9S^{w z#sDlj0f0qK09bS)0EK1pBA%c8MlS#%K@i^c)4XgmOmCIGN#A^?jf0kCK?0E?youxKg( zi!KIW(Io&Zx)gv#mjSToasU=x0l=aw0a$bu0E?ypuxL5}i)H|@XeI!Qt_EPyEI?pU zNi5Rd1c@K-E`^54qUBDh*)iYwhbMRx(P=xzWO-2=d)l>jWd7l1|g0kG(P02Vy}z@i5MfkoHEBG;NA@k8}Y zoVl`Sjr$g?RWaZBI(7OiG{S@alL7Of%6qQ}XyXf0V5JwcX5Pm*QPIGkI0a)}J0E=D+V9^_Zz@mp^kvC0{_@J1H^N1{Z-Tga< zH)Fo@%USeJ%=>A+EZWKVvglp1EP9VDi*}J^(feds^Z{8G?Iz2j56QCVBeE>|n2bfA z0I+Be0E<2aV9{Ox7JUZ5qR#Wl<^P%c9@Ovgi-8Ec%lyi~b_ZqQA+q=pV8y`j;$=LTPHZ%c3wDi&6ks6aipS z6o5q@0E^77F7aZQDp!YRRLg8RR9*n0a#QG zfJM~-SX2XmMKu9flmQ4V`ZX3AXoAEWG%#@v%c2~2JET^c@BDHW)lKuRSR{*%V|-au zk1UJolVwpRSr#=Q%c6#4S(HVVMUBX^=yL02ZALz@nxA zENTY8qUHcBIt745*#Ioc0bo%J02Z|bU{Nao7M%*fqSgQ`Y6HNcwg4zU zl4VgoSr&C7%c26ZEGi_+qRwPlR7A$2E&wd*3c#Xn04yp7U{QAf7WDvNQBMFC^#Wi~ zZvYnc0bo&I02cKFU{QYn77YMk(Lewe4FX`%U;q}K3&5iD09Z5xfJH+ASX2TCEIKDG z^0f&PU*t|=?PSqFd(0b_<~zTfMdzn^{%x{o6ywXH(PUXPhAfLNAj_f)$+BoHSr%PH zmPO;pvS>V67EK^y(L?|iO#)!iWB?XT0btQo02W;gz@ke4Sac}>i!K9T(d7Uvx&nYj zR|2r;DgYKu17Oi~02a*vV9`tf7F`X%qFDeenhn6BIRGrW1`t>@A}!L?1c^_qW8#dI zMOV8s+T1kX`Q6&1;C=a0a$bo0E<=v zu;^X@7TpKHqWb|@^Z)>h9t2>~DgYKe1i+$)0f9x=r9~#0An}gw!$b3A(QEFE_DGuV z{BjnpN%I!2kVTI(zARcxmPJpHWzmylS+tHUi=HCOqNmBS=ozvsdX_AUo+D$?dH@z} z0ASJc04#a|fJH9?uxKLyi(Ud?(Ix;EZ3bY`762A)1z^!O02aLrz@qH{EP4fiMXv&| z=rsTqy$-;lHvm}lCIE}x0$|Y&Kw#18w8%3iNZfbtyM9a-HL7Oe?KI!{fi*}P`(T8MN^buJWeN2``pO9tI9!y00>Gj}04(|y5LmP`E%J{E5})9@tKXGHYurWB;WXd*d&ys44)9;s7kF2Ed}~04%Bjz@nM}EXn|2Q7r%#)dpZu z9YA1FXZf}n?~_HDj4z8CkY!OrvMkCX%c4eP zS#&&E7Bwczq7%rns0mpXok+%_lK@zBG60L30&37G(plC_ELb5FCOqNAOWLeaO zEQ`95Wl=XW78L`qs5=0QdH}GfCjg6j0kEhy0E_wnu&6Hpi~0eus6POU1^}>VAOMR7 z0kCK=0E^BAV9|L1EE)p9qM-mRDgj{8FaQ<}2Vl_%Kwwe(^vDhqB>uTOiRH7F|S^MdQe_XgpaKO(4sniDX$ci7bmIld)(D z0E?yqu;^j{7F`0sqDui-bQu7PE(c)I6#y){5`aZl0kCKq0E?yruxJJVi)I3_=xP8K z%>rQ2YycL`0btQJ04$mdz@lpbSacmAuxM0zq~=3rk?-z+jFv?|xla3Cd;BFWLdP7j77@;Sacfzi*5&C z(Q*J5-2uR&6#y){6M#i`0kG(902bW?z@n7^EV>tfMfU-)=zaheJpjO>2LV{L3V=lq z0kG&{02Vz0z@kS1ShN}tSad^rWUvVmUs1`#xltBXbr(sGrTfk=XVDYs-c_q*(UXiX zi`J24(Nknu^fXx(Jwuj7&yr=)b7Wbxo-B(tkY&;HWGs3CfJH9?uxKLyi(Ud?(Ix;E zZ3bY`762A)1z^!O02aLrz@qH{EP4fiMXv&|=rsTqy$-;lHvm}lCIE}x0$|Y&02aLs zz@m2mShN!mSoC;$} zOqNBTkY&*xvMli@pG0(U$-$`U-$WUjwk{8vqu43&5i909dpS zfJOTOSoA#ri+%uL(T@Nu`U!wV2LM>~GXRSY0802UnrV9~DtEIJIpqTc{mR0;?z z+La#p)&z-f4VyUc%c9!8h2PVC=a;kS?{qKi30d?Hs{EJ`KIBA<*!F#r~&0k9|?fJGGmSX2>!MaKZJs1g8+Dg&^n3IL0$0X02b8&V9~JvEUF8@qT>L8MSrG8nwuc;hqFwa zzhu!!*LhU0g75rt7B#Hk6|a*;S&T1>8j)qu@nl)lm@JDWy7BvH4QF8zmodUq3YycMJ0I;Y90E=1zu&5OPi%tb#QELDewE9uQcRSs^mT1c{&M-Wk%MLeSEm<&?^+ z;5)yZMV%^mi=LK61&l9?3dyplGg%fDk!4XAvMlOKmPOsjvZ$CWi@K9#Q4cZ}^#ov1 zF8~(x24GPi02cKHU{OB+7WD^U(EtDz4Fq7(AOIE(24K;-04zEWfJH+9STq!XMI`_% z8V10k;Q%Ze0l=b>04zEmfJLJKfkhoFM4mH2;`Q9!*nC-Zsrx|4=nB5`%ULwGg7?w0 zvgjhlmqp{qvS>V67EK__qKRZ#G>I&WCX;2+6tXOuN|r?zld?4*(Ukx!x(a|r(*RgB9e_nM09Z5=fJIjWuxJ(li)I6`Xbu32t^r`tTmTkb3&5i5 z09Z5+fJN5>u;>OrV9^B?BBAHZq7wJM>kDPkJNB4&V+G&&-O$yl@;fJJuzuxJGUi|zzq(Om#6x*LE+ z_W-bHB>;==1z^#A04%y6fJF}gu;@Vm7Oetc(L(?%dKiF3j{vafQ2-XL24K-+04!Pq zz@o8^{`R`8u)&Z4I(c%xpBMNc!nEP944i=HLRqUXr6 zXgygLZ6M2{=gG3@1+px9kt~ZglCkI|02XZmV9{m(7Ht7w(N+K!{Xfi|2Y3`!`}SwD zne2x24X{gqkkC<5HlZqQvq@k{C55g_NJ3Evkc28ARS-}?=^`Lt7klp_78Df~5U^oI zQ4|F=SnzwEInTY>M15c1_xpd>|I2kH&)oOSIdkTm-<&yTW;6Q|3{dnk3{dn63{bQW z1}J(J1}J(B1}NGO0~Eau0~Eah0~Eap0~8&A0gB#&0gB#+0gB#%0g4X707ZvjfTF`N z6h#k(SymAs_6e;BoQH*?q1-XO8)jv`n4jNQ)(MeifMQ1k(`Q1l_RQ1lVBP;?wx zDEb&$DEb6iDEbsyDEbUqDEb^46ny~$6rF$pioS#aioSvYicZ1+MPI`JMc=>xMW|)p(qquC~5)?io#%kqHq|XC;|p3ii81*qF{icXc(X<1_mgy!vICG zFhEgL7@(*b3{cb@1}JjC07Xt1pr{25P!tCP6t#o_idw+{MXh0gqIejfs0|EIlmJ6f zbUw`De1Rxx#rKQ;5Q;YO6OhDkEAzz^bqF_lzbF)SM0%m96SPp&8Codn0xc9>04)?< z2rU$Kg%*mEpoOAjXrU+t8Wg3%07WhspePLnC`yL`in_r7McrY5q8>0nQBN44s22=S z)EfpUx(Eg+x)=s1>H`B5^@Rb7`oRE2{b7Kj0Wd(38wM!KfB}j;FhEfz3{aE>Ls8T& z+;S-aV*i8RJkvg0&Gf(KN3+@CR_2Q-8XRt1`La-ygY-gCF0@dT2Q3ukLkmR(&_Yom zv`{nzS|}=l7K)0Yg`yH@P*e&76b*#|iiW`eMZ;l$q7g7a(MTAeXcP=kG#Umdx&#I& zx)cT|^1%Q_V_<-yG8mv}EDTUo4g(ZbzyL*+FhJ2b7@%l83{W%y1}K^c0~B2bLs2v+ z+_H-Rv0M2Tkyj{M#Qz(6dAODNVv44O8!zq?il!pHP&5r%D5{1QifW*RqFQL7Xgah| zGy_^Fnh7lw&4Lz+W9F-2>`jj;Vf(K@6Tiq=C5MH`@nqK(i((I#l2Xfw1> zbR)D-v;|ryx(Qk++6oPdw!r{J+hKsBn_+;W9WX%AP8gtQ7YtBz3k*p*7X~Q04+bc@9|kCT00t;}5C$lE2!^8Q z`fy7s0b-xapS!+6C`#c+vk!+`nJ=d3@o;0v8$!_&NG}vU2`v;o1uYak4J{Ns11%Ii z3oR5q2Q3sm4=oh!ffkBhfCfc-VSu6+VSu8SV1S~RVSu7nV1S~1FhJ3(FhJ33FhJ3M z7@+8N7@+747@+7)7@+6?3{dnI3{dno3{dnA3{Z3s1}HiN0~8&G0gB#*0g8^m07XY( zD2g5px6B|w?Dz96qQ``yTbhtK7H(y}n4%BEjSUBcqK}YXC^`-;6nzXW6nz3M6nzRU z6nzFQ6nzdY6nz0L6rF$;ioS#fMPI=HMJHi^qOW0qqHkb;qEj$H(YG)_(RVOF(P-qi&w=!Q$ktM?TfbM5E%}CXZ;E0AZeFIu33V{}i ztk6P{4O%D)g%*mMKnq1-&_Yo-v``cQ4T>URfTAcEpePy!D2jmritI2zQ7jBl)D#9N zY6b%oHHQI;956tU69y=10Rt4p!2m@qVSu7mFhEgj7@#N~1}JI+0~95|07Z!~Kv7#5 zpr{=TMUft133`Vp8pR*A4vJ87w6jc6`v@!Z#T0dpFxnjwin<`Z^hFmy3q=<~3q@U_ zg`y;Ap(q(zC`y4Aic+D4A{Vq!lm-oo(qVw2ZZJSmcNn0k2Mkcu69y>i1p^fIh5?E$ zf&q#yh5?HDzyL*kVSu83FhEg%7@%kX3{d2T0g5tUfFchJP?QM+6lK8xMcFVw(LflW zXb=oVQO5|&AOghRng1QOlTb9T83}KMmHA?d@*<3h?+QivNG}u>Knq2M&_dA=XrZVG zS|}=p7K%!sg`!eup=c{q8g+ZifW;SqUq2=(F|yzXeP8! zGz(fNnhh-!&4Ct*u7DPb=0by_c`!iHd>EkUN*JJM0Sr*I5C$k(1OpT;h5?F}zyL){ zVSu8mV1S}!FhJ3A7@+8C7@%kc3{bQZ1}Itu0~B2Y0~B2g0~B2c0~D=>0gBeZ07cis zP!vs#upA^n>~Y-vOcRQ3h$L}Cgq8VXiZ(93`x)E9^+5#;U z-2^QZZG{$!wm}O;+o6S`o1sC`4j79R?`60|qF% z69y={3kE2<8wM!a4FeS20|OM@3j-A02Llw{4+9iE00R^~2m=&71OpU33_Zs^TiZB6=7Wbp-}WR(hEh;Knq3BLJLLDK?_CC zLkmTFpoO9rpoOBn&_dCR&_dBm(4gpL7@+7C7@%k$3{dnc3{dnM3{bQm1}J(R1}J(1 z1}J(H1}HiJ0~Eal0~Eat0~Eaj0~8&E0g4X607ZvkfTDL{fTANXK+#bcpy(J3Q1l)Q zQ1m_wMbQ%xmN5i~eF4Ak`bnW^CO-lBAi~OgF-0Fo7z>XJMV}zOQ1mIZQ1ltJQ1m&p zQ1k_~P;>%XDEbmwDEbOoC^`u(6nza1ioSsXicY}*Mc={zMc=^yMW7TtVk~u*`S4@P-vm3 z3A9iY1}zkYLkmR_&_Yopv``cUEfhsVgQ6H1pvVpb6ve^-MNMIVqGm8aQF9oe$N>Ws zIbndJ7BE0j91Kv@5(X%01p^edh5?G=VSu7GFhEfP3{aE^0~ED|0gBqe07dO#fT9jC zKv72+ilX31%Qpmw{Q@3P8>fT>IN+ob%zE;Jz#*Mo-jaBFBqVxHw;j85e!gtF$_@D2L>qW z3j-AOg8_>A!vIACV1Obw3{aE-0~C2+fTBzopePFlD9VNbiUz^}MT1~~A}Jn*5BS7qP_|e$~LXnFfhvY_DnJ=cOFw!VKAruWkdZDNYS|}=p7K%!sg`!eu zp=cjne6peruibg_%qERqF(P$W;=n@#9=u#M<$Oi)yje!A*%3y$^u`obU zISf!#0Rt3O!T?3%V1T0WFhJ1+7@%k(3{Z3#3{Z4A3{W%)1}K^g0~A%k07X+^fTF1| z6h--wmRSUdeOEkzQy>(j@Dq?}kyhr5DViQ>Z2C$lnt}8}(M)KeXcn|kG#gqdngcBq zT>&i=&4m_<=0OWZ^Pz>JE1^Nr0vMoZAq-Ho2nHxx358CodX0WB2mgcgc+L4%@OV1S}qVSu9BV1T0AVSu7LV1S}KVSu8$V1S~#VSu9D zFhJ2gFhJ40FhJ3LFhJ4$FhJ1*FhJ3RFhJ2mFhJ46FhJ2GFhJ3xFhJ2`FhJ4cFhJ20 zFcd`_BQ3$-5JfZjbJv@MqRb!?PexjqFQ(|(NTb8ILeXzN3q>zM3q>zO3q`L$3q|{&LD8!)K+$V3K+%2}py+iNpy&-4py*8)py&V$Q1liI zQ1mtoQ1lKAP;?LmC^`fK6di^Eir$3*ijKelMMq(PqGK>X(R(mJ(fcq!(FZU<(T6ZV z(MK>8MNdas1`{CmB?$!1GeXfw3yI^AR_2Q-`Yh78{IpQ?InoP7UqA~*C!mF*FQJ8^ zub_pZlh8uZ*U&=IH_$@SDQKbSTWC=99Sl%(8U`r(9tJ4-0R|{K0|OMDg#n6wgaL|v zf&q$th5?G|V1S}?FhJ2SFhJ3-FhJ37FhJ4oFhJ3H7@+767@$atl4(0A(qVw2AQ+&? z0s|BU!%!4`5@}gYfY{gZ=dM2$iiYz?){H1C^TiZ}Mj7}2AQUx0dZ8!`S||#K7K$RE zg`!Akp(qMkD2j#_iejLJB0IED6blWCn!*4@&0v6{<}g5!0|qE^!T?1rV1S}H7@(*n z3{cbx1}JI`0~E!>07Y$JfT9E#pePXrC~6A>6t#l^irT{fMIB&(qK+^?Q70Ins51;u z)CGp3$QoriOn}()_(r2GO3n0B_!F}iL|K_HrYJee`1!0*l!Ej^Q7W`hr0WB2ugcgc=L4%^+FhJ2oFhJ48FhEfs7@(*x3{cb$1}N$e0~8H_ z0gBu(Kv4z^P~?FDiZWqsVS8VCav4T1rRyf8q~U>Kk%2L>q0g#n84V1S~0 z7>c5jba6b*wGiiSfA zMI)evqLI)-(I{x4Xf(7?bO|&lx)cT|^1%Q_V_<-yG8mv}EDTUo4g(ZbzyL*+FhJ2b z7@%l83{W%y1}K^c0~B2b0~B2j0~Aey0g5KW07X?WK+zN!plB)#P&5q&D5{15ifUje ziiSj4#u6a*i}@o(MMBYKJngTIvNB&x(X1$A@j0PrHqr}4bD)KyE1-p5P8gu*E*PNbZWy3wHw;j84-8OrFAPw0 z9}G}*KMYXx01Qy{APi9S5DZZCFbq)i2n-2jZv0w2@rc4Nn?vpw1Njo&qP_7FQ#Zulo54aD0%_ug`&OCLeY!RLeWdmLeb06 zLeVSGLeV~Gq3Bg;q3AVep=dueD0&?RD0%}1D0&kHC^`TG6ukul6uk`t6ukoj6di;C ziVnd5MTcR4qIY3{q9ZUs(NP$n=ok!8^d1aQ^gaww^Z^V|^dSsT^brhDbQ}gK`WOZ% z`UHle=(#9MHv+`IlAohJFBILzpD+3}%F28(MJJ++QjIg9&s~3s^g_{B&_dBkXrbt9 zXrbsEXrbs7v{3Xdv{3XNv`};!S}6J+8WjBi0~DQs0gBGT07XB-07XB+07XB;07Z2$ zK+!oEpy(GEpy*c^py)Rkpy+oPpy)gdQ1k~3P^3l6v>g=bFhEfd3{Yf&0g8fQfFc71 zC<=iAimWgcMW07m<`5wE+?E8+7ediBe0j4)TbVDWC_LJ@F-RziKzgAl5?UyVf)V1T0bFhEfU7@(*l3{cbw1}N$b0~B?E0g5hw0g5h! z0gAf9P!u(Zwme6G*ni^zby&2T=@;;$*`#PI^TiaoqK%J(g`za17mCuMg`#fILQ!{U zp{NJ6P}CDzDCz|*6!nG{iY|f{iY|r*MSWm^qP{RdQ9l@D>c88ASR z2L>q0gaL}OV1S}*7@%k%3{W%(1}O5v07ZjgfTA22pePpxD9VEYit=HAq5>G8s1ODy z8UjO6loD+TF^HmaevXzZ6piMmu|?5V=8GvB8f|p43Pr<^UMLz4EfkG_7K%nf3q_-# zg`&~WLeVAALeZtrLXi(zC>jF|ippSsqOmYQQ8^4yQ~?7NRl)#8<6wZI@i0Kq1Q?)b zA`DP;84OT#ISf!V2?i*d3K+$Fxpy);z zilW)kmg@-+`-nsWXO2)bhHoBiiMBFdOwsmeo2_2}SMrA3~mwwlZH#(TmZ>xd@@?C8QUMUWOKmUV#>h_CX6p zuR;q&uR#k%`=N!R*P(@?H=u>0H=#k%0T`g@Ef}EaZ5W{F9T=eKAPi7+2nHxR3!py($Upy+29pr{T8C^`oN6#W7N6#WVV z6#WJR6#WhZ6rG0wivEBBinJJ+wu2%a1}F-G0g5azKv6IZP-MUWMIkUikrf6gvcUjF zp)f#E6Bvr3FQY9L1c?11et*$dLeaqp5@9h`=8GwciZPbjg`#Mr7m8w_g(5q&P!tO- z6g7nwikd+SMa`jwA_ufkih4o|MZKVf zqTbL#(M8Zg(Z$e0Q6Ffbs4uio)DIdI^@jn92EYJCZWy2_0|qGazyL*=FhEfj3{aE} z0~8H}0g48}07YIHplC1*P?Q4$6y?GIMR_nlQ9cY%Q~(1M6~X{TLtucSA{d~k7zQXR zfuSf$i?N(0K3KizylrW5hUwqLD~16pexwibg{VMVCMeMVCSg zMLuYuXbiMaR0b^+jfED9%Ar9~1q@JB2?G?3g8_=h!vIASV1S~DFhJ2|FhJ4eFhJ2H z7@%k}3{X@B0~Aex0g9%=07cVafTC&`pr{50D5`}4il)N=MKfT4qM0y2(JUCCXf_N* z(Xbdx4+6ygD37j(3q^g~l9&@?WxklA`7y?@7DCaLNG}vEfEJ1tLJLKUpoOBv&_dA? zXrX8+v`};vv{1ARS}0l$4T`RY0g6_@07WZdfTC3}K+!cYK+&}@K+$zDK+$R#plA&Y zP;@;EP;>(fP_z~XC|U;t6s?B=iZ;LiMH^v&qD?SB(PkK+=tdZzXbTKbbQ26vv=xS; zXl{&UE&*acX(e#x2}K{V*cM}DzL=t&F~&_Tg`!}lZy&JLky65q()8)Id@n4(u=j89t&Mf;FmD0&rID0&TADB2G#6uk~D z6ukj06uk*86diyTir#`2ir$6>Meo1>MF(MkqC+r1(P0>%=v^3~=m-o@bQA_CItBw2 zy$1sny$=HveEK7|2_K7#>@K8FE{zJLLWPQU;~ zU&2rny%b}y#S=wG_-X9RLeWzGug0%ptjrfvbSlQ^k{}d)i}XU#chEx7X=tJ7duXBP z2WX+_475;m7FsC!5n3qv30f%n85$JT!2m_)V1S}uV1S}uVSu9FV1T0EVSu9ZFhJ2C zFhG%JmuWjF(qVw2AQ+&?0s|BU!vIAF3{VsT0~A?dfFc_VP!tLS6g7bXio#%kqHq|X zC<2C}=<66uJ^^B%Y$tHO5sDJ|aY&@y%6u_JcDpg9txyz;^g>ZnXrZVXv{2L>S}1Zr z3q?+7p{ND4P!tC(6t#pFidsQ~qSi1#Q9KM#)CLA9N`L{15@CR%wlF|ZI~bs-Jq%FP z0R|}Q2m=&#f&q#;!vIBHV1S|vV1S|vVSu8pFhEff3{aE|0~Dpe07a=VK#>auC`yB& zD2ldQ))F9gJKuGTv8$Q>R)WV!w_BMnrl_agc(}b#)C=i_qTbL#(M8Zg(Z$e0Q6Ffb zs4uio)DK!H>JKdx4S*Jk+|ZyX0|qGazyL*=FhEfj3{aE}0~8H}0g48}07YIHplC1* zP?Q4$6y?GIMR_nlQ9cY%Q~(1M6~X{TLtucSA{d~k7zQXRfdPt2VSu8cFhJ2T7>c6q zcFQpW#J-vzo%Ilk?lvcEb}RG66pgkUzjhRgEA6xF~0MYS+M(R3J~Xa)>WG!q6Wngs(C&4vMr=D+|&SHJ*8b73foM%pb2 zoroe2e=u#7Q1lA_SK~apmHA?d7TOJW7olho(hEh4p@pI)&_dBtXrbsTXrX8sv{1Ah zS}3|2S}0lpEflSU21To2fTC+)fTC+*fTHVQfTGnfK+zf)py+xSpy&n|plB@&P_zyP zC|VB#6m5V3iZ;RkMVnxNqRlWs(Ty-b(H0n>=q4DTXe$g*v<(I*+71I0-3&ufbfw)g zjsUUmB55qZ6^&nswZm>@zO?3AkkKym{;s;_=u4w+&Ecch(FQvf(o+(fV<+9840pUp zuNIAVoS@H>G<94^AH8)trcn;99FNkc-4YzX(?4&wcX;SO0y;acPSmunjyLIXORA$; zM@{SI7}Z(RdO2>sK-2m-PIT3@0gj{;P0MuDxHN5$=I;IcSv|7iLxtcc1p%-Y{ zT*ts6nzq1kO|hmealBKiY0DighHKg?hi{~&t#;fpTGQ4#zP?n`Hac8onzqF;vs}}* zJD#r8v|SF%1Wmi$;k``L?si-^Nz?9g9IDc^ha4@ZY1(6svKmc$%5mFtO?%F9YNn>` zb)?VHv{xLn=W5!1$FuV_?SR8rsA&fsIg2&zh-1xCO?%(*?lMg~?r6P2(>`;QuhO(H z9d}%-Y2P@$TdirQ9o=uxw6l&Y)@fRu^`PD`7@VK=}!L8+;h5< zKlQX%ck;(pUeTTWxr6<>lOG%((4G9`@1XAFM>j`wC*OO2Uw87&)8o36?|yxzJNfp- zm%5YZpWo`5B^Qpnw+B(#n`1zxfWxhH7%rDOoCO@;zrZi zq^F0)(lY-%7fEtUSPxxm`3oOO_FBmJEzeWdf~xAnVRmL8_3wf>MrPZ1t2QLjkioi@9W=3RPkS+hHy#6==Liz9Kd zh_6}n5z&i_)mKDKI}-gw1k;}N{vs}-3!pwgiTJg&Gp@Hz$-34?FATC>qQ&1zo|C+h z$}_?r{2*>#8-0io{@9se32pSEkeCO*ShR9>8@<>FZ+~h?2QA@FO45On#2=LWW(MT< zh2(dq@-A&N*8A4Dm-}^DB!YhiLJO#ID8WtKM37 zWVRN6t@tak`CUgBx6$G^i@gJOi`S2j(&Aqwn-BLe?2+ExUh{C@x_jGabdW_x__Z5{ z_NAi@iTP>6ulHQ3#Xn?GhkH_`F`Muu^0*1xq{^|L+x_-_N>25*;e%tVsPd`a4xTx* zcP`gk%sopN&ejrMr9`=uDE_SE*hi%{a}1%+ig1ook>eA;AGwLC2#LAs@Zw*%C8%gO zzB$@#h-DLoJGF!+l*VkuAVVG2Zk5;wPs}?IMrnH;P?{GD-{Y5kSKN*{=7VahX64+)7CuEX6jt{F=*6&p7g9qfaCoa~D z`-pP&R4sm&Sg$F|(nPap@vo4{&2e6Gk9qU+L%Cd|;fs3g9cebkYrj2SU{>h)2X-tZ zPEJ!2W-BdCYGK!#&3l;*c;~h+ADv^i!jsRgzw-*S1@G_CrLz_vO?RI;%{Ziae^c^> zW}08GKk_7FWQ12OUogbn&pjXRz2gckp(&-Q;Ui3t#5+{tkeKIB-SIF(XoO$?=(MqB z;wDEdR9fmsruNBgtHobLNw|(5R!Pjm7i*ugf@}-5_(#a&qyHT_Z#j9-RzjI_{`}TC zDdwT0_7RuPj=j$X&&bb=WhQ| z)y>Nv-}5VH7!tFy?&#B3Y6*pu$i#aBEpRPeqf&>&Y+G{Q%Y1Ga;ahWWoM9Gc^WzV` zpi)1w?${G^wfN9jr4+~bYU-nneP7Jp|GRrG@@ z4Oh=2Vx6eB_K5XMz4eAzk=@iWU!iI7qiI~q$DE-&Bj(7yJMzo|e1H1bt9;Bx__F;a zRGW0jKRmYib?W>kP?`mlW`?8*f4KKqg`KO{os^h*mEU&n*rrb8tzVqIca|2vmeO#W zUaivb`TGoAnt9jHC@Uo9{RK~*R9A%Z`;O$8`FwKb_Rmy>EqnF-U3Bnqbam!h{sH@b z=ev7~%<{hW=rbEt8@<11#p|lkmp{<%0xfT`& zV~&32Vg7jCmfHvwIs>{bzM@cz??q|2hL0i519ivt(IHVk`{Z4pJwQuT$M+mNwS#-^ zkeJ)Azx9dvTHVp5D1{jJf^!SI2q zU}@6!$plT~-w=x>r0s=Kn#R8&KL>@heT>?Ue?z_`v70vG-;f~M>`rp|H{=AZxg}Q9 z_&4Mbi3e$ce?tzFm`pkGZ-_x@e6+y7A;FdqO^?w#M8<|$B3nk5I%4!_8vO*d*TTa3 zk)>&t=9(q)qOgm@dWU%_uV7h2=djUTV<#k7w?y^}3!~L)Go4IpXG+zIN@X(_=)w_d zE>Qp9L^3o~hGDwyjpZcaiIiOmC5eclopa8Sv3gioeV$Pfn#G2agoQ_EP7Tp5&*}p{} z8rQ`o>-}4xAe~xxV`FrC$N=Ytj267#mPSB=AjhK_ROhV%GZC+KpvTo2fAu1r+RJ6u zSeq4#bS=oaCWGdz3A94v6`GcaZHTU9jf+ziX_kZzNBi?nCRw^x$l*Ea4T7{aB^+O( zU$Qyu7n@@+osL1;yb_K)*yqjvoF_Zk^s8$_IIO3!qpp>5;H-nSGy0Hi<`U&X+aNQw zf)oGM&j2!Yt%$=`8lCCdC=ST5C?LZk&ajY5#~BuF<0W%qqK%@o|MI6jt<|++4v$g8 z>RJhh`BZP5Rq-}nilalI6&$eh;((nO^UiIu^Wts1)RulJ1qYO>IG|L2QGs2l093W+ z4y5|cX5hT3`v3A6xNMXrn4_c#4rsDq)G}}LR~blpTR?hSKzdt1dOG{nPmr$Dk!k8L zOzm!}vmh;X8%M6cAg$-N9(3xP^CGR7cMwUn$D45En&eG3Qrt|x)Bu2kH$e^ZGMbW? zu{)aEQF8vNKP+zUz@I>!Oj9+B_BJI6(tnMNpu$t}d9RwDoSaf!mNKqpYD!IYc}lgf zro7TOwR%czWqEC7MM`<~?5VX=*eI{8m|k636R?iAr>%RZOs$?cd1CFv8I@Yfgej9N zQ_3b)&Pqw1G^M<3QcBH)vg*o|>dLChnzEXd$~0e1?evO?Q&MWDOqo02@|XS*NagzyC$$E#!pCbS657*ST)5nrMfc7Ul+4#tIaA=HBwkTFb+{hA_wwK$tlu|*bs*i*V3@JH{x0uu?c3RFK%G>YXmA4u1F~^AYa^e&m zCK+_(b~9i5|46>7SX`sJk=V|#w>As=4-2Uh_m%2t9Q#pq(LtDP(e7U~jXk7!iV@qA zcHB6JdaVkSD6QSrNceNk34x8y4V)%hBNug$3LkFH+<#m?hY{Q5Z;O}UZ(>!*z9?ja zCT>(ZQzp~{+Fm81c4n#*M>HyWiV;r-Y)ddgLo5+}36LM(4;eTIsB ztre?UtBbUjDU)e+8YPM~Qrj3^XsHz$DUwT2VXT=?M2Petf1g8Z-ffQ2(#y%I2jSgE z5Hu?G{qKs^I8$|OD$_3QjJVcjS=BE7Z3&V1uVb!BY=mI?_s1DWJ$uV8=Ar#{M)ilR z%GK8B%vI4ainU$>8cmC6QZnGfEOj&OUrSX!PbA1kG#@O-yzWp}^{9m!VnN?-E zEZH0%2B|ZETcsX>5(YN(FsGBjd*1#;{TH~ zhR#yjJjFr`r!<$4JFwla3kTBF7Ezlr=2S7APpy8AnFkqaJ z5-?7P=rcZLyxC>PB^oW;n3oCFqyO8H0$-Bj`Xw2i+hM4n65@(4jqumk5xLH#7@bqq z#XC{1AO9p(s<~5|Pel-%|KUz~eACe!-_W_k7sWU-{__J59N_R}lxmNLSS;i_U#u-X`-~^Fo2Kx2 zhzoUJ>dBfJ|J5lSPa{q`H>C$tr!~e8h(VK^{$KQAfjt%XNPGfw;gS2l?R+lau0P%A zz@2Q0!Kwp~d;WUyUvvvJi4|0i7rZO*3y4F@qJiU|4d z#^e8V{H;zd5dU|v-+whH=xeklgs3?pk_~6Fk<_m7D5CM8+8lwT89Yklfd|h)%;8`g zUg%_|4k7@tzK6M@&A_nHwFA(vH6S+ z3gO{kYhIGppjPS3!$GcEJ*3@#HvMunyoT}+L9Qp!A(oBvhtrMCTa4rc9!FSKU1_^} zH;*DyQ{s)TG@ex5kQz{-5Btx?jno7FKkKU-_J57JR+GiQ8*To7*i+Z{t=w-@-`YX- zt&Oe%F)2m|vv0M0IBzgFmJvgB%)>;!uEtBZYq>!mz8jq>bMtqzc6$5QJigEUWH8^7 zvpjRf;PK}Dul8*X$Di-vwKoye)g8Kopd@-elwDlt%PK1JdGm+5bG?~9chSJoysZ2Z z4J-1pii_O?vwS551-{&Z{DE3g)4gHlB6}gK8N{)KVD<0^}D9z5M{ENLKv;0Z^bY$KZU;^0q2wdfQ24+uDNGlL19+De;rWH zDDn;*RFY3M>MPDFDdBS&yUzCH=9tAz@21Y2?&coNou|SwPbSkMgr%)|$x0VhpFcOR zw`%dffwk1*Ij0r6s91)QCk zSwp?_crl~2Sk*F}8-e|iI+Yk^s$@R7xjq7t7Y(OV+E*|%t0+6SU|8dw7Ud80cbmkO zJI|~cIuGhM&rX_Cb z4RW$Z__EzzKBLiIvIRe4rCzO|w1^hye9F%Cdg^<4lSuBk{MF=2Gf!r3Rc2XjnXkBP zQf*GQ1_cxP{hr^{iDhv%{(zCO{p56 zK%JH8b)%XykKGkeg~eI<#Rc`3C+_b3dzJpSC@VM1?2|chRzrSN3-j?)BYLw{1*yIC z2-u6+-*7{5&t_i5q?8SK!O8A(dpxB@ZjW?b{_+f>>)S9l9cYO+FN<1C%X1I+dFWco z1?%N+c~8KO3#r|Ti#)`U+f(8ls;)Ub0xoqpDe2-oFyFi|n^lxfoA83WLFXRWGt~E3 zuB`g5nHK%U6*!0oI>$@pa!19i-+*?SQRJpex?sh7q*e+%g{aEV-R2e)%SqhJze8#c zRg)Q5$TAzgX5#p&%8CT~WJtAtcg%P}Hf2Y!)OXSKU4X|^;2T6;lRp9KCa)kGccgT;w4Z@5@C!s9MM}S({!JST(!_T^albm6?_)m&>B8 z{7fP`pl|j!zQ-IG2~SkRRpTptl~olJ%c^{QzWFor=H_M%bmz)xNh5$vDp&m_&^#yn zSE~R5T)i5c6@t+q$|+y~mWjinhHu1+m+PTXM-@20pzgvv&CTlZpEa)T4Kl(hhL#Mt z);ECaFRygsYG!XoXjnuIzcX=ay8E?{&)_g5hLgH&JUkP=_!AazY|H~{Do zu)XwUdDL5#7MYhSv%k!y3Mn2G&})P1T=xhbPRccymZ%#WH@&JnwOhItsJcmM8({0_ zzfn!2)dL2^xpaQiw>$Pe(4Cj(uHQS6NaHP32c5;{PV3Kfm&>GLV18+Wr+4oJ{uEcT zD}g`9mD($15PSm_B(d#c`9Sl+`BD zhrs$$zfi#jZ8>i0jP6M_QK2f-*PHI(zwZ$H8o}9E0ZQwR*kQn&^MJVb#5gwA*8r2YbQ>rN~)m`WKpak zuY#_4er+CNPxGkdT3A?CQBhfuS5to$nGmQe5fAFk7R|~pD5ZW%wNd7z$u*uSHI#Z})YS&`uqKc7lgvhQ2kERa)>RpFqns*z{Mo$9>S|@tobxXV zqpmDPSspIc2(4gxtvNt!K#hwg(`FuO3SLYfYRvOz#n;mMQ6^2lr9a`@31)TBf>=D? zH!YeGmHW_YG=cIC@V-2XRfCM~xrmogx$=tMlLhGN2 z_mEuF929$1m!7P=!hngThi`QRUg)^of%D=)!{}~`Cx?1{bwmx$H890vFMr*^44m}; zi|J*yH@l$W+_xU8Ot;7U*kwcJF<|=hNkz8;sM0RybIM;Fb=0N#?xA#g@YLSFCZJN? zrF7$fhL?di3V29}s#8D>q)C?=pZQmq6!TcTAfNjbb70~6muuAwx--mMgZ>o(m0Xln@|QCPv-89)11^c0b(&?Off*eG%0zQ$ znw)w)Uh@i8=%x#pxfNZ8)B>Hm4K`PIOFe^VZl9HFZbDOge|GhQuVKDYx?M+=DH%$B zbh8dMNS%r-@{CkUS)UW#oG9i#vz}SrAJyjnx0S%}RzFzVy%vU_jTS99BF36avy6SIzxTx3GY9`PK&_DO*d8xSry2hIe zJP&0vZ?c&8hx zSX)}ip!4kyJOF4k`|~%IC)-osOfJ3;k3Gpv9d$W1+g&|G;Kjgu@#gfjQ8!XQM$OFn zn^7va_lPVt_r@HxVOPK`(-0?%?#9r)VHx_-&Ru+C-7JuLTp%}ho{QMM7Na8YNiYK zpOL~rQ13?l+W6Uu|gS(Rf9kal! z20s212^dhj~IiyS7DK-y-Z_JttYCw%Wb7$P}I^#bD1J4>WC5?DA^9=UahbPya zR~T^3R@KZ;6gl7eM{D&{0#`SGM~73x#kW^g(Hit7?m`;552tx_1IPo4r|LnSJUAYl z0}L=d#BO{?)f^#Zy90+GNP$hcBmpxGy5LFes;dI8R#O7(vQUks>3*WWUQAA?&+r?b zyvzoZP2wDF=5M_~(CWKdzU3bH@a+o zk#R2Ba*QszCFb7|>O$S64fv>nnktx;6F2}h=X=BG@iRYwFOVn7D3W?~z>gmrcmI4@ z;|KQWuJFJYDKm22`8jj~XVHzcM#CXKl*XIaH%x8;J#?h*gl_)2^8;?!aqBd^d!lA2 zYQWy$!f763{as=8R0IX9AB;7ak8t*MB9zi$p=_LunopQZ=ycVMSDz0PVq_f9hYu>s zp~h0DqL&(exW9FVxoOUguC!4~zSYB*O;tbYRxK65#Wx@Qo8oRrHqYP&7V&(!QS~;M zGcr%+dBAfUWP+l3+#agwY@d1A*Le5%xCN#=OqQIJfpZ&$OTZ|EXHlxV;@gE>U8;+~ z9?f&V`0pOXO3k5I{t=RzlbEf^cNLMDd5y_;*ME9~+pcjX6#D#+J-I${^{CH7wa&1D zq8z#M`9}yYb&nLAQb&WwFbyY3*>npL6AJ#!hc?jTxhSDCKWcDSPfp01JhqbW$|scI zf6dLO5BMMQE`R?lg8nt0{wH7igMR336LTZOBeXsN|60%gS)UQveo5$3+f~+OA`y;|R&%6n>N721Js(R}BVF7`mo?H;8tK4yUvPel z8?9f{Nc&$CK|XK4yV3e58)^Joz4?%+eXZ8MLaw2I`-tir%VX zLrMQ#OTJpG2Lbh7qlcJ(y02Nkr7Jb?aVI}Vp`X?C+oYwY?chkS$+(pxy*mDY_@9XX z1xI?d;S5}%Rys>I=Rx^nsojvc5yInwq|P=CRGbLuBJ zzgZl~Um|g}#4Qqo=v?IOTS@H3k@6cZk*ZM(qEnr_p&)tCHkM z$?PmX_uaf*4~cyxW=JfQSSqnx;$;%2NxV|x5{b+$=X>%+%iS!CUbA3;VeI;3ZS4iadX>s{BO57&#R*AbM zJ|yu;iF+jOlXyVlyAnT?__@SyB%YD@i$tBSkGy}I#3+f)CAOB>USg8O9uoUY93*jw z#E}xqB~Fq!UE+L+%OtLrxJlv;iFZkSNaE8HUy}Hy#3K?vmUvR)8HvA1H0XlG#~Ufp zAu&N>7l~;SFP4}oF;C)9i9U%FBudQFCEh0SK8cS@+#~Tdi3cTq zAn^-{-$|^KsMGj^_tQiozXz9fy2ODreqdcJaUzWiSWlO@lCJx#H%Qz~!+O?_OMH_q z@T}jH_&p8lS^qAv2Q9PqNSsSA7-W65#69!|HP&xRw9%M{bu)?iG$vs^O5)l?rEiva ztew&)BqnrJI!WR<8enkx8i{vbp!DMsf9R_89};`fK!mr?k~rU`^h$|))0KWpVv`<9 zJ0uqNQu-2!>n~Dzr^NUBDE*bhw*8e(kvPGv^mK{$c$9up;@K>v^=uU{8l)n9{LL)) zg25_YBk`qNrQeYlUZ8XfiA6({_DS4Wtn@7sKcoQ{*T>fq+YeXTCGoP6O3##d-)Ns{j?l9V$%nePLw$EVWr1Q-2SN2yCr@>1AVTaGZMQ#rF3tJ)z2t> zrNqacQ~E`T=l3Wb_JWF;FRD01;)<7*-XQV7KBYg9*nGdz?IezVL+ObUcN|dqUWs46 zt@Mu)lMg9TZuf!Rrm0m3IsUMWyCo$+prK2Pc`dR5xiPxS}`bLQd zX@bS=`LV>f^GbJ;IEL=i@%qUUZ>2B0VEv%PZ|GYuSf7)aMiVsF{Uy$#@4;ZbRN^!A zg&3?~lNcPSbd1Eo(Mk`KxZ1AtO%e|`Rr*tjt?1h`IKM6u$I?WQ^%RM>w^aIJiQm!} zYw-GCC3Z_t+AVQTTcwvte6GFHuS*Q+q;#yr+%8IwkoW+7rw!--ti;zO9_DCh+UKHA zbF|Z!u}C~8esGfVZ4x6mQhrX+tt2Lj-&J&~#O~q`5S=N}D}IUS;Sw(qe}d>q5~qnj zSM&mjOU1ul;x>tQOMG17OA_CacwFKsiN8p+(v4$2zNQ?hemYAWC9y){EQxnXd`RM# z6916spf7mfe3B(*OT0wlbcw4Z?v(hh#IGeL(AOhyK3ydCl{ih}9EtZxd{pAA5V z=X5P47D^l;@mh&{Bp#CZrNmz)M$wDrIUkS2nG#n>d{*Kai6Pz9_AMlKmDpe6G>NxJ zd{1I{4@yUzL`!TTv9-jG5-*ULF0rS?0TMGM=1CkPaiqjcC61SPxx`wDvm`E*xKv`e zM*Sw$L$pMPM7s57`t2lkl9((pP2xoo`$?qXsF`lC#0rTtY%~2S5^E&VaLV-OOI$8- zl|&l8nCmx4d|2Y+5}%W}SK@0D-;_v~Lo>a3-;R#+Gtpm4q|1-F{wIml{hFG(Su;}i zX~xbH=`=GnVPwX>65SF9Nz9cvRN_d9=KVM-N2TZ~5^E&RkvL!Ca*3-X-YoGJiMu7< zFY$4SPfI)`@u@BgcME-6hPG2tZ za*5{sH1cPPzCt2@)ediel|=rE9oFW3HH!S*I;{CU?Hq5Bc!$LMC7SowX#LZopO+ZI z?M$$Pcamm4blby>AIo-hYg!AUlffyzmRvJ?a%~y?_fSo3wTct4ME_7#t0nV)FlotS zYihJ)`k$+0Hj~xEl)rtGgLOpp?7@;%Cc(y=R(<$ z+Tzd7Bz{x3)m3~9%cL4qJ&**D( ztuqyhx?_F;w)xBZ8$rJ)11)N2BQ@<>>L2lgrBX5i^ILMAuH7E1@?)+zPtLEBevyV2 zwMALF_FaI1#hHz^n>J84@B4BZ{=s(KB7ytuN;lt6%W<%e{azK2h8DGq!Mc{f3-W{f z7Lg9juhp%(c|LHxgwZeZ+eFJqLyOv2%8$<*{9xTWG6M7K8jv5|F7oGh7cC13n85O71{^Qp;4dFdy_n^x6wIHqlpkL&@q>MFq~`Sh zq^{7lF=SBpqjB}{exvD^_la|Z7PZxMQP{@|@`L~tGr!0C?`w#m-^DX3<7_TIWBse9{e zL;m>r{2v3d`ES8lXY+#73&IP|c8n}I9UA8O;j=jfr;X6vIUm)HS-iLI8`}Px`}Woy ze{OGGtK+o1oqiY4?`rnGC~M!5_0AmnJ7&iq_I3>3;pJ^r?h7oRmhG)OFyzyT!-KT% zA6V%5VViqG+Z%KAt&}2qZ(VRArAa+l7wpn5{Po!Ib|2M!vq)cmq>jEnlD5!jZLn)K z<$gSMc`mk^lAy2W+?Qmp%vm{jm3I~GS9_iv{>}N}xQFsiEjYWNhU4&doX3@PJjd5? zp2t&<%HEJqaQ3{Md4uPB=MUOfr@4{O+?=_C=XvK1Vm;u8u{HZB)fGA82JfpokUEFT zzprj@>f4gjk-Feief^#~&2^;Cma1=6OW~<1Mw@Z?U~KLFA-3I-x~9=)ikKsH&gdbz zv?VRIiZ;{IQbII4W!^n?yP{*qw41P5|LtJG+2@M&^_L9(wCob^B{`RxCF8tC59Z_A zmC%21yD_m7ZuD>YP8pRueGiq9TG+FP%01|ZhiiBbdsDmlOOs)iroF#3o&9C#YL?+h zU8)%~sVsY`EFA~OPS~RMQ8+wNU*A6`F<0Mupp5ntvnQY}QM*gBds6#p&-WbM)7#4| zbMNf%&H6^J*X}vp2lp7%!^_KBJ8H3@PnZ^$qUGuZt{m6kG;f-;K}fl4a7aG2U_$wr znh7Jd-wqw7Itt&|HAf#a`ndM27TtV+c6&m%b1w}%zHLMF!8S?H_1n9&YQS+#U$EVx zFF2d_!jhKny>j!l>3dFB?Z5G}xI@1knebx&1*e)f=~~_9_C42(FMla`#`m4F@B3oN ztWCf6q?2vHqsvYQ88(|X`;QWjcX;oC*~e};^5Vv|HyO52Eh~J1wt(^ty5jIPx9$FZ z@O?Mm{7&=EH79o1T{k|Gf6u$|C%$|0_S;(g9I-B@qw~8t*%yyXI`HUK(KH;_7p|?F zcKre>E1$q|gIjuAs$*;yH~6Kxr(8Eod@uO7gPpT2_dWgP>FWwk>&>tno6~e~Q*Sfb zI%@Do3z}CcI}8O>=S2 z8SoRNhs>l4NRV!;r9Lz$$Y@5FlAs{#$BEQY4sT1#dColAJ}B6@iZ0}qp45v66|@** zTGlJ64-T>!d2HIOCt6U49BlAEas>rjS2Ux|4^vlX=^E>%%`Mv!=uc|X5?VH{qdy^! z&=t!XJeL-Ob0YaWO|8#yUvG_TN>yzgOnr3_nUu)-DmlT{hp3>2^&RTJL##j1vekMO zWpA@CrsYtpleTYSrS3`#v!181X}EQ10)42!+KjH-k=8x&bb+*1(%)!nciJ+>+J_#W z*sZJSIAg7+sAig4d(z;hnKhjrqcpdkp%I+JI=mfq*VZIjZee|uDkjc)n3h{w@1|O8 zW&MPQNYt5(J+F6@ZN!nXqpydwM!<1Wvbs1G^rS;PG z^g%W2+*X>l&w7H&{HnDX4ar}#9;LGFx86v{`?~ccZTW_+J1uwBZ3(oqB;B@#wo2A* zx6ys36y26VrAgIo%_*$bZPTg7*XXvjRL~oA+f1svwYu#ts;+gq?L|`Sb=$4f$QyLq zeU!^a%9D1mNw?+Fy3M*Ri;8q3aX>pdtJ^kG_))iY4A!)tbem4T1v)a zX{46N+NKkrSI63Zr{vL{Y@gB*#dNYwq@$hcux+QZOmo;Srjk`VY?sq+YaF%ewZ9UcCY=><;(K^Rr>q9kvg~PUsc$w?4HKzuj z=dcZ>0?v2X!l;(6blCRMCJP+4ABc&C4%^REhyhz{6|`IT7TaOUEMto;j>?j`#THMw zWNooUQH5l0vC&;-ZQvGLCe=jY3$}}C-H;b-w^N>DPTG#q8Bli8wu=sI>`7ZCF;RZf zwtUU-?>Y6&k~K<&De7mm=z zSMkDIRF-ADV5N=M_-J7i9r5+Nu$oGH122@)0j}kRFX_0~@j?OZVs<$#Tu)UuhZoLJ z!Kllmol+a}SA>OjAPD%H5IUCj&L7MT&8J-i^TLNzjRr4lB5dgU2({34)Dl)+$RWqZ z3wO}ILV4j)YKSJh(3NryWWFPxzIj^c$^Xya&JxS6(z z;f1Z#ymnqVLp2u53zNxd$_qczxzmgn&eFcP)S>azd~|D23*AD658{Q9v_29T#sE`Z}F4IxpNz)CTcFH!23F)0#X%83kAAmhGg&uA@Jx zRCVEVX@S0nMGuLl6cNGfM+O@m4gMngsEkz2=+yj1@`9-sjLL9nMrV=nB-1pbi^$d_ z(>3D)k*!E}(~Jv6wj|kIGrEe5BiTbUl0>#3*;6x;MLJ3L(u@?54wAh!BUNN`k}fKi zOLQ~VRIW79O<7aH(nZIzrjm6NZD&nI>n=KmHI=Q0=xEkdxSpb;SX1eGiH>AV#p^9P zf;E-zBGKWb)2MtGiwOVTMu-L>BSnLdQKCV}Xwe|#644;!Qqds9CmMu|5e-7hM1zpA zqCrTxXb@5%8iZ7e1|j1_gOKr}LC6HrAY`Iw5b}Shx)0ze%l+@eyKJ5;C4^)F6FS&M zP!tslDvDUKi*oF}V!?`t1r<~T1Q9_+MX~qZyI@7d-g{TjNcF5 zVIh~vKD(Rb(Ab0=7P~5Bi_+Nq{onXN{t+zOvMOY1{;@q9QBHD_kfXA(IiDp$M#j+) za&*iPa!kw+a%{{Ha$L+1a(v7Xaze}yGAd>WIWcAk86A_5lVTGxCN?1_$0p>I*o2%K zn~>9D6EZe7A*aVCXM6LLpvLhg)B z$X&4sxjS}M$h6YD{Qcipli#t)E~pCGFTZP)-BV6-l8^_odHJ2DB|;vIqaoy>m?7lh zm?7kmm?7lRm?7k`m?7lxm?7kem?7lJm?30tOhV?xCgiEugghOakY{2O@@#BEo{LS$ z^RWq;ADfUDViWRWY(id&O~``SguEP^kXK?8@@i~CUW-l0>#+%WBQ_y##wO&g*o3?t zn~-;6SB2bH`Z9n2H;cViWRvY(oBsO~~Tdg!~zskiTLR@^@@P{)tV35x0lLyx~^#_bW9ntM_Q^;@WvO*4|V@=kg zSlTWJQkkDFaZ1Iiq9OT14cT(Va^jT~tyIiL<{x^NDC+HeC|cPLMSbj0)YlG0tJtAv zRXY^*vqRBpb|_li4n_TKiq;S)T2r8CErFr|0!3>J6s;prw5~wWdICiQ1&Y=eDB3`v zXhVUbK>|e^2^4KCP&8PeXcK{=Ap%943KVT7P_(%~(H25g(F(=Vg*lK)`q}f@ilOMO z{PCP@%VIhCN{Y5AX7}c>mMGfR`B1c-9g4QML(vX)DB95uMLXG{XqX*}cD6&&E_Nsy zZd3F>fudanigpty+FhV%4}qdR1&a0(DB4?~Xdi*1eFcj46DZnWpy&XBq5}nr4iYFj zSfJ<-fuchNiVhPf8X-`0xIobnLRHbwV(GmcNM&yRXkE5-D0(2ji<2E$EGJ({(J{sB zpZu}NC5n!9J`^2ihoa-{P;`PFibmO?=tMgdjkZJ4Np>h2V~3)XZHi72C^}W3=rn<% zu>wV>3lyCpP;{n1(Kvyk@d8C>2^5_zP;`z!(FB2_a|Mbf3KUHeD4Hx#be=%b6oI0t z0!8Nw6ipMVibfVoOXr`=Dt*!&=c7Z>`1~_jc0sY6d?iIQi`n4(f_#ahi<}Qd7u%ue z5<3*lvP03Ob||{c4n>#Sp=h=pimtFj(Umqua|DX65-7S_py(QbqH6_;t`jJ_UZCg( zfub7)if$4px>=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h~qtE-aP~ z&Vf`4>4Ci&p{U)GYq4TE`AUi&E@tQC&(kbX^oaAJ=utZqJ!XfZ$L&z`gdK{Wv_sKc zI~2{cL(x-qD0M zO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zXE8=)q#?mK;dsll0-|p-^;c{xn(k zL9v{CB}JbUvzPLRftD!x)cH{KnH`Egw?okvb}0JN4n<$tq3CNn6n$fdqHpa`w9uyL zJAtC_1&V$UDEd*L=qG`qp9PA35hz+DQ1q)n(Qg7pzY7%oAyBkfpy*G5qQ3-+{uU_u zN1*6mfujEeit?|1s6MSoQBk0%g-})WQL(fr2T~c5KQEen9EyHT&rg+Fl#{QdsGPrs zXZcXn()m!-$__=X?NHRl4n=i#C~9kmqIx?NwX;J}gB^+*ZHg)aMePNOItUbX6ewCs zpr}cps9B(>lR!~tfub$~MO_7ox(O6@7bxl>P}EbPsFy&|(gH=x2oxK{0Z@_wngnf z4H78YNT6tAfug|zMVkl|4G}2XRG?@xfuhX?inb6a+ESosD}kb+LRC@k7Nyg2AeCqH z*RW(OhoYMF%*EC%%E?z!w0(>0ir%4U2j@f4j&>;8$qq%s>`=6`9g23bL(yZCjL{%7IiCr#sZ!g`)M+r?;b9l#{Qd z==c`dmwiIf3C@S2QFbUg(GEqU?ND@*9g4=-q3C2g6rEy+qEqcqbec`kSb?I`1&YoP zC^}Q1Xq-UNc!8p`1d7fUC^|==Xo5h|xdKHK1&SsK6ipT=I!~Zzia^m+fui#Tilzw^ zT_8|2U7+Yfp{nTE7NxqrxuWyZqmIXgqQ2<^(~K77K+%T+MIQ-OMUS*7&CG#R)=E#&KN^ZoO|S0w zxJ5bnN{T*jk=@@v6n)`*DEiV4MPJ#W=xaL^ePf5BZ|zXD&<;i4*`errI~4t3Q}m-i z(N6+JKMNH7B2ctQpy*eDqTd9HeitbEL!fA}K+&H9MSlqt{Vh=Rk3iAC0!9A`6ctKw z*-lYWps0mFQAwbvMxZDYs){~sQTiYUQkj}R!;yU!idIig&DNI6$yZX;x|IF5W+-ao zd?>23Ls45h6xG|IsGS{(8thQiXosST9g5o9p{RpRQAdHIr38wa1d5skiaH4tbrvY< zB2d&-ps1TbQFno&9s)%@1&VqJ6fG@Kw2VN}vI0fR2^1|aP_%+T(TV~^D+v_!7OIL` zmP*U6l`A?V|6+oyRjGQVU)LfZE0@a2S5mZUDI2nODC*~YC|b=9MXTGPsJ|VG*04j- znsz8!%ML{Y>`=6}9g5bmDOy*cXgz_VfdWPA3lwc2P_&^y(IA1MjRcA|7AP7lP_&6a z(GY>6O$CZJ6DZnTplAz$qAdlAwh|~BDp0hwK+!e=McWEhMSV-9LvtXNL(|8iRYFnU zQa-jTm6NZeXs1$k?z*99nDe1%XFC+_VuzyPb}0Iv9g23fL(y(_DB9f)MSIwxXiuA> zy#$K(7AV?BplDx#qWuJl_7^BRK%nSAfue&1iVhYiIz*u8P=TVu1d2uo6df*5bc8_B zkpe|W2^5VKC^}l8=oo>bV}+`s9ZIF!av+rn`4=r^JBFh5(nFBPmCDIiQgmV|dwF0e z8tr^2I>`=2W9(3LvK@*}u|v_Rb|^Z{4n!b zl^u$%wnNc1b||{m4n^156kRV+bb~LubK+&B7 zMRy4l-7Qdbk3iAA0!8-;6x}aS^ngIog91el2^2jnQ1pmURWz$q8khsAESny6yfhTu zlRpcaJz6R!UrEuErEHIlLeX63L(x1t6g_2!qNnXp^o$*fp0z{Kb9N|t-VR0c?NIcB zP0@=2MK1{yEf6SrS)k|@fudIhie3{adR?IC4S}LJ1&ZDhD0*9<=pBKgcLj>x6DWFL zpy&gEq7Ma%J`yPUSfJ<=fuc`^s-nkBrPFgDl{x99)=z|@N$Ilxvr;+vN{YTJWpf6H zqOY9~Mc>$==vzA!Ewn??cXlZH-VQ}S*rDi0I~4t7hoYZtihdC&S|m{Pt3c6j0!6k!{zw=1UxuPL^XKxjRyF11D=BJQlYKoT6xBN)irU$ssKE|Jjdm!i z*rBMs9f~^Gp{S!Bik7lNQIkzkvp`WNfuha=MO_4nx(XC^6DaB~P}D=9sHZ?tFM*<^ z1&WptC|XvaXgPtR=cRLjAVTYnU?NGFr9g6n0L(x7qMf(aA?I%#Qzd+Fe z0!0T36dfc`bg)3tAp%8*3KShCP&7iI=x~9eBLs?$6ev1MplGB((a{1$#|RW1D^PTt zK+*96MJEVVMZ;=J7w14KkEJ`*JBOnANztg9a`KfFjj72V92$yFc0LrHVuzwr?ND@@ z9g4=;=L!@}6eyY`P&8Sf=sba< zDFQ`P1&YoWD4Hfvbb&z8bb+D^1&U?}6wMSUx=5htVu7Md1d3(}RYjv~N+0DwDvR@( zofL|WP9K;qttls8NzoNGS#jG?bfxp5XpS9VWb`Y&DS*Jb78D=BKovR8+NqDJRKQN<2L?d?$1!45?o?NGFo9g3RlP}FRP zqE2=w>TFZgMWCpwKv6e=qV57kJp_t+3KaDcC|X*eXc>W`Wd(|s6DV3V_V zS~JT!4G%?YIUkA!*r8}`I~1*BhoW`uP_&*MiU!)DXni{rZD5C@4Q+}B2^4K4P_(f? z(O`k1O$3UD2o!B9P_&sq(dGh0TL=_wDNwYPK+#ZvqOAprwh<`WR-kA*fuijNigpkv z+EJirCxN12LRC@!th7N6q|z_{lKgCqP;@|g@M!0(oO~rkyJp#5yN06OoDW62+o5O= zI~46{hoZggP_(xliuSQX(Y|&l+RqL}``Z*9AW(FmK+!=0MF$HM9U@S4s6f$S0!1SP ziVhbjIzpi6NP(iG1d2uq6df&4bc{gJu>wWM2^1YKP;`Po(I|nU69tM!3sptKv(lM4 zkV?Pwy6gXiqDRu#fSi<-ldq)c)GWJt_fT}2^Py<09g0r3L(v&_C_2*)MdR#HG~NzH zXW60XY&#U4V^cIipy*tIqKN`UlLU$;3lyCvP&7rLXsSTb`2t1L1d1*YD4H%%bfG}e z41uDV0!0@I6kRM(bcsOGEP<6g??WG*_r9x-u&@?3F8eCVlvs6N*kr&w$L!%E?z!^lX-`wofQ}&iPREyd8?> z+o9+MI~2WWhoYD4P_)1fMK9Z-=oLE@y=qhRnn2O(0!42K6ul`>^p-%;+X6-J2o$|5 zQ1qTa(fa~L9|#nEC{Xl~K+(qnMV|;1eJW7&nLyF!0!3d46n!aB^p!x-*Fsg%(^+Zf z97yGZ^g!b?p{Q8Q$2VCy`AUku&$1Kt3q?OTABujoL(xxmDEiqBMZeggXptR?ezil< zZ+0m9-3~>6*c2@mDEd>N=r4hyzXgi^5h(gspy)q=qC#z4wo_CTC~6^4R1zqv5h%(8 zifRRl$^u0#1&Ue;6txy8Y9mloCs5Q@pr~G`Dq5J8X5~OC`zA%-g`x-3z3XV_V zYG0c@d_XAb;Cv|RXosSu>`>HXhoWXX6m_ygQD-|8b+JQHS34ASvnlE>P}D=9sHZ?t zFM*<^1&WptC|XvaXgPtRm?9=|7P^qpeX}PQH?&wQIA|!J%j!=R?uDb|_lU z4n+g)P_(`siZ-xA(S~*?8f1r}jqFggu}#rnfucI|~%;B2YA3s47~kwzOgn zr1E0=BsL%veUl!7{9kQ3`AUlRsLi%GG!*UWd??z>4n=$0p=cjF6zyw=qW$bpw7(sS z4zNSffp#c5$foFEfuchMiVhVhI!vHwgh0{Z0!2p%6dfs0bd*5RNP(iG1&WRlC^}Z4 z=s1C*;{}RN5GWcYP;{a|(P)99lLU&!2o#+xR2A)3TRI{KQt6%UUGE->=A@Ubol;v) zzLKKTYqRr4grYN?4@GC%p=g{PipJZa=qx)Foo$DrbL>zw!45^|+M#HoP0=KQqR9e9 z=Lr-|5h$7}P;|aP(KLag3j~U$3lv=_P&7lJXr@5XMFK?^3lv=BUCR)RvR4q-cI^)@5WUdcpZn^r9V#Ua~{c0y`AFY=@#(>`?To z9g1GFL(%JYD0;)D=uLs5w*-pb7ASg0py*wJqW1)f-WMqPK%nSDfufHDiar)7`b41U zQ-Pw-1d2WvDEdO6=u3g3uLO#|7AX2gpy*qHqJ=_L(Q~z>K{=4h>FIg2=R?t%rF?u> zTTZ@`qMvHBeU1r5KRX|aez8N*B0CiQYKNlV>`?T(9g6<2L(yV86#Z$3qQ7j4{uU_u zN1*6mfujEeiVEepY^SIwP}D-8s3cHSBT$qH6x9k8l?94g3KX>xC~7TG)JCAFPN1l* zKvBIwQ9FU627#hRp{nSI+S2$ONacz2Jlc<;=&ST4j+Jsb`AUkGDreUo7mAvk4@J#( zDC%T~qRw_G>SBkYu68KuW{0Bgb|~s$hoYV~MZE-ymKG?=f2d{k6&VyQD^RqYK+*C7 zMJosttte2ml0Z>!fufZKiuwo?^%W>uMWAR^fueo_MXL!Etu9d1U!Z6Wfuc19iq;aU ziaL}_^K&4TBhy1f9m~}#{X^4dv;q0gIL&<}MeCKb?@kCs1Dy{=>)WAd13MILXosRf zb|~7&4n-T=p=hujiZ-!B(GZ)WO$CZJ6DZnTplAz$qAdlAwh|~BDp0hwK+!e=McWD# zZ6{E)y+F|p0!2Ft6zwEXG)$mqXMv(!1d4_W6#Y-2Xjg%v-Gr*5b;_m6s9e!;>0{Bl zp{Uq1AG?>!$yZXecRA}nIuz~Wd??!24n_Ofp=f_Q6dhoPq66(vbdVj24z@$lA$BM_ z)TZb#fua!tMTZL%9U)M3q(IS80!1SQijEd2I!2)ASb?JB1d5IqC^|u)Xp}(Fi2_BV z1&U4*C>kSBbh1FvDFQ{O3KX3tR2A)6E)CCtR2tF~uzQ7~HofvOwp>oWlA>|t?8Gsl zXuR{G=qx)Foo$DrbL>zw!45^|+M#Ho9f~H|p=h!liq5ksnj%m%RiNm6fud;wMHdJZ zO&2J-P@rgrK+#NrqKgEIE*2=dM4)JvK+&ZFMVAQ_T`o{GTcGF)fubt~islFuT_sR- zwNO=bM!9rZ4x}R-mX}ps1ZdQG-BHqd-wbps2k- zQ3s)_=;w0js2oUTTyqZRmr&G@p5X7;vYdP+MV(q^Q^$p(&d!ITE_NvDYKNk3b|~s@ zhoT;KDC%j4qF#0=TG|dp%h(hxD^RqYK+*C7MJosttte2ml0Z>!fufZKiuwo?^%W>u zMWAR^fueo_MXL!Etu9d1U!Z6Wfuc19iq;Y+8X!=#wm{K3LRC>y%hEkLkjfFu=5U%@ zRdDB95ZP&CL6MH|_nXk$AR4YotkCUz(qVuzwl?NGFt z9f~%$DcVAyXiI^jtptjO3KVTEP_&Ie(Y69b+X)nHFHp3DK+%o@MLP);4HGEZS)gba zfui98MgJ2h+Et)vH-Vzv1&a0%DB4q~DjL|b^mh)V(j#5zuTN3OeC*Y-oO~rk`?buv zO$bH%J0FS;utU*-b|^Z?4n+ssq394h6dh`ZqQmS^G{O!=huah#Ay9OrK+#bGMI!}@ zjut37Mxf|efuiFCijEg3Izgallt9sm0!5<*icS(J8Y572vOv)(0!60^6rCneG*+PK zbb+EXgsP%_T9!7>fmH73oWt2S6s?^|o!PRSd?iI^x6JmN7>dquJ`_!`L(#c*D4J-8 zqDgirnrw%n^XyPG#STSN?ND^SP0=)gq6-9yrVA8ZC{Q#*plGH*(M1A97Yh_!B2Y9- zpy*P8qRRw|E*B`8El_lYK+%-~MRNp-t`aD^TA=6}fud^#imnr?ipIArot*=zT+=;= zb5sywSucYYamf7`_L(whHhoW2UP;{Feif*?<(H(Xuy3-CtciExnZaWm+ zV~3)9ZHn#_D7s&u=mCME2L*~A5-56Dpy&~SqDKXa9up{fT%hO)fubh`islLw%@Zhk zN}%Xzfud&wik=lHdQPC|d4Zz&0!1$fRYfv}+Ee z@_x@8&TpaU?WCx=RXO=ein_MSPMRKyx;Y<;y4#_shaHM~+M%eI9g3E=L(wvJC|cGI zMa$WtXnC8W6$FY_6ewCrps2S%(aHiveFTd73KXp(P_(K*Q9psA)dY%G7bxm4P_%|X z(V7B9YY7w$5GYz(plBU|qICs|))OciC{z`7ZdIC{1F0;PzTJM8R@E#0XVa5v>$fT= zUrEtMt+K~wgrbd|4@HCRP_&61iiX&sXj3~BZDxm}&FxUMg&m5vv_sKWHbp}PinbOg z+D4#gTY;kO1d6s7DB3}wXh(sfodk-82^8%tP_&Cc(QtvH{|OZBDp0hWK+*03MSBPo z?I}>Smq5|p0!8}>RYe=NDt(aysjQzq{0s_3yXL=^?c1uHd?iH(w#v#EhoXa=4@C#t zq394h6dh`ZqQmS^G{O!=hufj(2s;!VX@{btY>Gw-6df&4bc{gJu>wWM2^1YKP;`Po z(I|nU69tM!3lyCsP&7uM=wyMSQv`}m6(~AQplGZ>(dhz3X9yIXDNr;{plG~MRkVMr zQlA`1<==E!c0efVojw+w)vBC)B}M19%C?>riY7WAiYD2iXtEuO&a*?&6gw16wL{VQ zb|{)=hoTGYP&D19=t6;_83IK!1&S^bD7sjn=n{dVSpr3u3KU%?P;|LK(QJXDD+G$J z6eyY_P;`|*(bWP)*9a6{D^PTuK+*LAMK=f(-6&KQoztpxbPl94Bz^JFgiv%$dQShQ zR^{X?DY~syHtn)dbi4DR=ngv+-D!uSyX;VOw;hV^u|v_lb||{f4n_Cdq38jdq6YeSfJ<;fuctRiXIavdR(CB34x*~1&Zbh6wMPTdP<<^X@R0=1d5&&D0)ty=y`#n z`2s~R2o$|2Q1p^O(E_2W=$2Nc`*I+aa(dnMt)XasQuK1Ga`KfFz1}K&dv+*#!}(D3 zrX7mjvP03^b|`ws4n^A33lx1KQ1q!l(Psihp9>Uy zAyD+CK+#tMMPCaPeIroxtw7O2fuipOioO>p`az)RM}eZB1d4tZDEdX9XpunCuR>MP ztF21^=0GZS>EY_vLecPaC+W9V<>V_V`m95 zapfM0igqY!VTYoU9g1pfiZX$sT7janKv7G9qE-S$tp$qO2o%)`6txv7suw6~Cs5QN zP}C?;R1qj@FHqD$ps1rj(NY3MO#(&D0!5t!iaHBbMSrv^ZIT12%t#M3E)GS*(zl`M z(z={{B}F}2X9rvzih4R9ih9|hXlXkXEn|nGW$jS3oE?gmw?okib|_lW4n-^36!jJ; zT3Mi|k3dmhfudCeidGdU>L*aNnn2O&0!94=iq;S)T2r8CErFr|0!3>J6s;prw5~wW zdICiQ1&Y=eDB3`vXhWf@s9WpOgd9j^?*ylN>*|$$DLtn@sC7B{N{TjVo!xkCC>r8? zDB9ExMVr~7XmdLhZDEI^E$vXWl^u$P+M#G`I}~kWQ?#u>(RKnw+Y1!!AW*cUK+#SD zMZ*M&b`~hwMWAT7K+*pMigpz!+D)KncY&fk1d8?)DB4S)Xm5d{eFTd36)4(IplE-g zs%YcZr3E>V%7pYuY;Y)gC@DIibvgM;iVkU={d9dOI@I}4beJ8AM%ba~a61$oVTYn4 z?ND@-9g0TUq3CEk6dhwzbgV$paRNoh3lyCoP&7)Q=tO~{(E>#$2^5VHC^}i7=oEpX zQw54n6DS%hP;|OL(HR0oX9^UJ6DS%lP;{0+(b)n;=Ll6r2emFObwjS`{;oNkgG14c z=_`pQv@R!KNzvri*?^lu(Rt2?qA7MLnrerl^X*VH%??Eu*r8~;9f~frL(vR76wS0L zx=5htVu7Md1d3(}6kRG%beTZWs1&Xc^D7sRhXpTV9RRTp<3lv==P;{+8(RBhv z*9#QgAW(FpK+#PCMK=o+-6B*KO>AA-JqJ=5Q=h|`6pEHhcam;xT~5A|qB~n>C*Kl^ z?s7g9-ED`Wd+bnjuN{i+vqRDSb|`wl4n+^zq39ty6g_NH^oT&wqXI>b2^2jpQ1paA z(USs2a|Md#2^2jgQ1rAw(K7-?&k7VhCs6dfK+$}Gq89{;UKA*LNuX$fK+($rMXv}H zy(&}{-QK!%We%jWFkRf=5sFSqie777PQH?&w_0aU-WH19c0LrnV~3)5?NIcd9g5z! zL(vCzDEiP2MIYIr=wmw+ePUDesX)}I}~MhD5|wX zQQ4-br9e?Dfuhy|MQsF%>I90~3KZ1~6txp5Y7i)D6ey|)6tx#9>L5_mQJ`okfubgX zqGo}jP69=p1&X=|6m=CS>Lyeb{nfg(N)DuQ_%b=1ze7Iy&4E-t@0r8t)uwu-KO~VF+@_p-B}JRH$)?{MiZ*vX6m4OLqAl%Ew3Qu- zhT5TMYdaKeV~3(`?NGFx9g4QMDcV7xXh(sfodk-82^8%tP_&Cc(QtvH{|OZBDp0hW zK+*03MSBPo?I}>Smq5|p0!8}>6zwZew4XrH{sKh@2oxPCP;`(`RWzhc>46+b<;L`E z?53e;-Sh<^2e&CFUrEu3Hrc!PhoZxs4@F1Vq3B3E6dh%UqLFqeI@%6J$Jn9hSUVIQ zXNRKWZHi71C>kYDbfQ4fXn~@W1d7H86rC(kbc#UHsRBi(2^5VLC^}uB=nR3PGX;vq z2^5VNC^}1^=xl+aa|DVe2o#+wP&84fDmt`HsqjFqsC|0f^S5h>! zP1ft7P;|cYp=g>NiY~B2(R4c$U1*1*8Fna|X@{bV>`-*E9f~foDVilvbg4kmWdcQ) z3lz;3D7r$R=t_a2IRZsj2^3u|P;`wz(X|3a*9jC|FHm%YK+%l?MK=i)-7HXai$Kw> z0!6n86x}XV6`j|nv}q2ca!0yDJtY*q)G;4-v?(WFNzpxRvV$H8MfW-%ite*R(fxKP zdcY1v589#VAv+X3Y=@#p>`?Tm9f}^aDSBL>=m~+MCk2Y;3KY!~D0)hu=xKqXX9S9# z6)1X6py+vlqWJt-W`fsrVmVSwkaoHNzuD)vYQ_ZMejKuir%+F(Fb-Y`p^zVAK9VkV>=XmVuzwn z?NIcY9g04;Df&X7=u3g3uLO#|7AX2gpy*qHqJ;uQ-w70bFHrP@K+%r^ML!7?{VY)Q zi$KvLfudgpihdI)`dy&t4}qe^0!4oc6#XSs6}{c2^hyq-@<)2O`khd8NmBH8n{x7% z6cy^SU!Dj>#k#nX4@E8PP*k!*QH>pnGCLI2+M%dyhoY8tC~9SgqSiJ=Z3K$y1d7@U z6x9n9wG$|65GZOCD9T?IQT+yO6tx#9>L5_mQJ`okfubgXqGo}jP69=p1&X=|6m=CS z>LyUsU7)CkKv7Sjs_5S~rRFDdMP1Y5MgN7OVTn|)x^nWB6fIYmturqaE$@6NTEPxQ zE83xGB|8-LwnNd%b|~s&hoZiAC|bo1MXTBr^%E#sO`vFXfujBbMQaEYttn8nmO#+} zfugkqiq;V*T34WGJ%OTu0!8Z!6m1|-w4p%JAc3Nd1d28mC>ktKw245`5TUAQnYz-R zIgrZD={wIXTUWi(pO&7Q-L$Tpd?iI&)@7$Y9g4PcJ`@eLL($fDDB8vjMcdk;XgfO; zZEuI79qdrFqaBKNvMCxSP_(l^(Jlf-!v%`|Cs4GjK+$djMY{_W?IBRKr$EtO0!4cZ z6zwBWw68$XegZ}N3ltq7P;{U`(Ln-52MZJ(B2aXwP*t>fUFoVENac~Gb2wXsqIT)B z|FF7p@|6@FS(nXwHWVG@d?*@ehoYnHP;`tPijK8I(Q$StI^GUNC)lBAlpTsrv?&@b zP;`<&(HMcElLd-S5hyxUpy)J#qOk%+rwbIFAy9OtK+!mXqVWPnX9*OYEl_lhK+yz& zqH_g`CJGcy5-6H1P;{P9Rdje=>6;u#<*@X+>mx$Z%%o^aT{-zmiY}D#+M(zoI}}}PhoVdDP&CU9MVH#4=rWt4%LR&N3lv=;P;{k0(Hw!Is|1R! z7AU$#py*nGqU!{Tt`{h}L7?bHfufrPif$Gtx<#PqR)M111d47KD7r(S=uUy6yM(Hu z^Xp3eav+tx)9bFMg`zjpQ?qy1m6NZe=>EEF`xise1I~w{2klVwkR6I1wnNb)b|`w( z4n>dIq3Cft6g^>wq9<*N<_Z+e6DWF0py+9VqGtq(o)sv1PN3*{fui{WMK1^xy(m!h zl0eY{fuffMie3>YdR3t4HG!hn1&ZDfD0)+%=q-Vww}q;rd+SQa=Rhi3r>D;D3q_x_ z&c{1-<>V_V`k*eGu^<$E=zJ*p$PPsx+o9+aI~09thoaByQ1rPSioUQz(U*28`pTy0 zYk{I~1d6^DC|W2`^qoM__X0&f2o(J&Q1p{P(a!=!zX%j95-9prpy)S&qTdCI{tzfy zEKu~PK+#_UMSlwv{UcEHuTWL=UR~*-97yG#^kR_rL(%;9`S`D{oO~rkrMB7o`QzCg zHttu*YTEw)SNfS9ifZjpRJKD=OFI;`vO`g8I~29CLs6X_irU%~)e9806DVpBC~6ca zst6Rd7bxl=P}EVNXeoiBCV`@6fuc?VMV$qTx(F0?6)5T^P}E(ZsE0sNPl2Ld0!2#; z6fGlE6&2f-TD+PonwegA-J)&v8f{94d@S3xoO~rkE4Iy+c|8=ZTQRjmF-Z} z#|}k(?NGFe9g0@9Ls36F6s=~5qSbAR`U@1TAyBlYK+#$PMFRwi))pvQN1$k3fui*U ziUtZ4tuIitfk4rQ0!4!aiZ&7`+E}1yut3o!0!2dviZ&G}+DxEmbD^qe`L?Cab0C!k z>EeEcP}C_s1F}Wia`KfFZQV9Imym zqMhwfw2MvAaDk%#2^8%rP_&ys(e468dk7TmDNwYRK+)a;Mf(U8?JH2UpFq+60!0T1 z6dfo~bdW&N!2(5x2oxPEP;{6;(FlQ}!-cA%t=g6*=Rhi7q-Q{ehN6wrounh$mXoif z=;*fDt#5~-W1J5~$J(LjI6D*_Z-=52>`*ky4n-&0p=h)nicYda(HNVelLd-S5hyxU zpy)J#qOk%+rwbIFAy9OtK+!mXqVWPnX9*OYEl_lhK+yz&qH_g`CJGcy5-6H1P;{O^ z(G-EAsRBjk3spr&wJp7t1F77TK8cMCMI-C;F|BPm`AUjrw9S5fHx$iuJ``PKhoXz^ zP;`kMie}lN=u$frU1o=(%k5A!+YUun*c4qUP&7xN=qiDts|AX#5h%J=py)b*qU!~U zZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w5h%J>s4AM?w$%B( zT+z_V_V`nYX2_M=eriSwc8Q#%xWW{0BB?NIcE9g4oRL(x}uDEitCMc>$==v$kjg#tz2 z2^4)VQ1pX9(T@T}KM555EKu}|K+z(BqF)7yeiJDAU7+X>fuh9%MSltu{UuQJw?NT9 z0!9A{6#XYqRH%;&bBc;WRndoSOV{K;DleoL$$k`ywoXrnw5Ts9UrAAIefIPxp{VS9 zC~9ekqE>b&YHf$2Hg+hgvqMo^I~3L1p{Si5iW+Q+8U>0f0!8fwiaH1sbrdLCN}#Ao zpr~1(sFOfZXMv(F0!3W~in<9Dbr&e=AyCv)ps1HX(b57%%Lo)LD^RqYK+*C-RZ&fS zX<-he@>IGk%j&CF`rD;%6}m!wIr&P8R<6(5ejbYYI3J4o+M#F_I~1*IhoXLVC|b=9 zMXTGPsJ|VG*04j-nl?pi2^0+wC|X;fXdQu~bp?vn6DS%eP_({4(FOuV8wwN+5-8e8 zplD-(qQL@1n+OyQ5h&VJplCCJqRj=0wh$=VQlMxnp{i)5`qJt-kV?684ySi0S}i>t zGPJ&&d?iKO)n_|?8H%=dJ{0X>hoT+rP_&aBiiX*tXlFYV?P7=wN}OLj;Nr6(~AP zplF0Z(cuC`M+g)hDNuBjP*t=|eQ8t4n?EvP;{alibmU^=p;K7jj=<~$#y6@#STTM+7z88P&8Jc=yZXiGX#px6et=e zP&8hk=q!PvvjvLI5h$7D7w-PMRV*>bd^of)dEG=2ozl_P;{L@(e(mFHwYBnC{T2hK+(+tMYjkP-6~LY zn?TX+0!4QS6x}IMbeBNU-2z4T2o&8bP;{R_(ftBN4+vF7GwVw=3v)#)rAHkv3Pqc= z$j5{A<>V_VdbB=U?)y;mnDe3NaXS<}VTYn8?NBt=4n_0qQ1p}?ik`MZ(KB`^de)}s zIf0_*1&Zbi6ulr&^rAq~O9Dj;1d3i3D0)Sp=v9HD*93}Q7bto|py*A3qPGN!-WDi& zN1*6kfui>WiryC}`aq!QL!qkZ;rh~+IgrYro;jRHLeZ|Je0)@2PQH?&&+4^8#$25U+LlMmhGxn z`VXatAbYnfCtpd?D($l07loo#oexF*>`=6t9g0@BLs5S_6s=*0qBZSMw3Z!;2H2r! zZJVNX1d7%bC|XaTXrMsR`T|882o!B7P&7!OXd{85jRlGZ3lwc4P&7oKXj6fr%>;@z z7bx07plC~hqOAmqh6)sIEl{+LP*v2YU8(D@xuV^YqQ0SMX1aI1ZM$;vl@#sRE?fWi zP_&ctp=g*Ligva`(Jpo<8g7T8|Jk8vS34B#W{0BP?NGFbP0^kLMSBSp?JZEWk3iAB z0!8}?6zwlibbvt7fdWMb2^1YHP;`hu(V+rGhY1vo5GXoapy&vJq9X;0juI#uDNuB@ zK+!QmRnhkCO8e$ODsQG2rtJ`lx~9wiW80OJucT;HyX=g`q3A^CL(ynE6rE&;qA_+T zI@u0Ir`VzBR67)%W{0A&b|^aCrsxcTqB8}G#t9US7brSQpy+IYqH_d_CI}RrD^N61 zplFgn(PV+5^8|{f2oy~fC^}!DXqrIL1p-CW1&S^dD4HQqG*hT5I=)@$x*SO5&h$y_ zgiv&EQgl(fa`KfFUD_^t_ODQMne(COayt~wwnNbsb||{i4n=e9P;`|YimtXp(KU7` zy4I%XI)S3=1&VGED7sOg=q7=pn+1w)5h%Jum+K7pe91&SUJD0)z!=plikhlQ%5OWKvb&w*4{&u2C(6s?|~jeVqDIr&P8o@ke~ z`!^Il>3k@fYlotFb|`wv4nT^t>I4=Gzp#AW-z8K+#JAMGFLq zUKS{NMWE`?Tr9f}s(q3An16n$@pq95!~^rIb$ezGb0S)k|_fucnMMZXFZ{U%WKyFk$&0!51j zivAQR`b(hbZ-JtJ1d9F@DEd#JsL&9X?GzOSidqO1l>~}v1d1|&qFRBXvQSm@dAri+ z97ttRdLHeIP}I3oK3X=Eldq(xt|7amMJQ_Pd?>27Ls2_B6gAkPsL>8Z6+0BQw?k0} zI}~-aL(x(;MNI-l%>qT81d2Kf6m=0O>MBswO`xc|Kv55YqMiapy#$Ju7ARUqplDfv zqU8jNmKP{mL7-?wfufZJih2tatt?Q~N2n@l-B5Zg2U58u-4$xnP`%QBFDdHVP)@#* zqSYF*k848F>duFv{&px@!wyAj+M#GII}{DDL($rHC|bu3MeEw3Xg!;vfdWPA3lwc2 zP_&^y(IA1MjRcA|7AP7lP_&6a(GY>6O$CZJ6DZnTplAz$qAdlAwh|~BDp0hwK+!e= zMcWD#Z6{E)y--!OYD1|u%N6aHo=58!iY`je#_rHiPQH?&og1DViWGddLgofOS#C?{V@ z(d>ro&NiXw3g<)7m3AnaV~3)v>`-*I9g428L(#Q%D7wxLMc3P*=mwjj8wHAP5-7S^ zpy(EXqFV)uZWAcFU7+X=fucJFitZ99x?7;=9)Y5J1&ZzyD7s&u=mCME2L*~A5-56D zpy&~SqDKXa9uumHE^8>gl>@14o1VtMJQO{ez98iBhH~x6DWFLpy&gEq7Ma%J`yPUSfJ<=fuc_Ziarx4`dp|gda|L^ zy*^hoBt1klHx!+lo{jyYp`3grMc*`J8#aWZZ=DZC3++(!ogIq4w?oknb}0JM4n;rN zq3CBj6#Zg{qD3}EzX}xnCQ$UdK+zupMT-TB{uC(sOQ7g)fuer|ivATS`cI&!&={BP z6cq)ES_l-C1d3_|iZX$sT7janKv7G9qE-S$t%a(huNq4G=RhjQr&sTP9g3c4n~ye) z<>V_VYS);JtAwHk=R;AW9f~S;C~9wqq7HT_>S%|erR-4DWQU?=I}~-YDe5dx)J34E zt3XjVfuimLMLh(HdI}Wv5-3_)plBI^qGbh&mJ=viUZ7|Nfua=!idGUR>Mc;TvOrNE zfug?6PH>5`$`!$x6ucT;=#_ahHp=eF#L(y7x zC>mggqP6W%w2mE$*0n>?dUhxpXosTp?NGFVP0@w|MS}#2HWDb>SfFUIK+z@wMMDIN zHWet^OrU6Ufub!0inbIe+Df2ks6f%y0!7;h6m2U|w4FfF_5wva2o&uoP_&a!RkV6z z>Bk&MWlFlZ?;narq$l`?HI|dFr09Q*Sz}Wu+SU0`w3{7@cDF;(9(E|&(+)*@*`a7} zI~46>hoXJ$P_&;-(f$HO2M81$C{T2eK+(YhMTZC!9V$?Cm_X48fuh3&ijEK{I#QtM zD1oAp0!2p)6dfZ_bgV$paRNoh3lyCoP&7)Q=tQBaXqU#)S~-x)z3JZd@KCgPqB{kO?h+`v zTcGG3fuef_itZCAx?iB^0fC|i1&SULD0*0+=n;XUM+J%=6DWFIpy&yKq9=u_qAMCp zPvk%`?Tg9g1GE zL(u{|6uoSRqE~E+UKJ>MO`zy?fuc7Airy3`dP|__ZGob91d84jD0)wz=zW2r4+M%n z6e#*gpy*?PqE7^hJ{2hXOrYp8l#Q zZY(EXNzr$W*-AY_(f7`Wq95!~^rIb$ezHT+&vq#K#STS_>`?Tp9g2RlL(%UxMSlns zEfy&HQ=sTCfug?!ivAHO`d6UnKY^k`B`(`3Dhd>}5GX1M6x9e6WdcRD0!3wkqLutCI?dKSjpim3`MV|r$g#1<>V_Vs#LNgmkvekoexDF z>`>Iv4n<4Zp{U6YMa_07>STwa&UPs3VuzxxHbvb8int87+UrEt`N_O|Mp=fRAL(w{RC|cJJMeEt2XrLX6*0)2^ z26iag&<;g|>`=6kP0_{zMS}&3HW4TqB2cucK+$FbMVkv0Z6Q#!r9jbE0!2dwinbOg z+D4#gTY;kO1d6s7DB3}wXh(sfodk-82^8%tP_&CsRkUWM^iB?>(kDIXu~sO$X~_j! zrJQ^vMY~tBzm^Y0dpIA8_OwIMUUn$j+YUwh*r8}&I~46_hob%MP;`JDiVn0XI!K`C zV1c4T1d0w7C^}4_XoNt~;Q~cR2oxPDP;`_)(MW-!qXmkN5hyxVpy)V(qT>aMP7o*> zB~WytK+$M{qLT!Q#t2nKyH-j)SI8ADNUyuzEfhVIzN+!$N;&yTipEy5jaCXpr#l~t z&agw#nRX}|XNRKkb|^Z_4n=3%q39et6iu*0(YZE769tMU2^38hC^}D|Xo^75RDq)N z1&XE#6kQ-tG+m(RLV=%s-5`m&w0!5b!6kR4zbh$v$Y=NRHgsP%b zE2RT-AeF1~nVlAjR!*d@tdx_l!cv76*)pwe?^7%^t)JiPE;Q|xe>>Wmrm^|6BrTif zDQyQ$OgLSbUl zUb_|wQ<|>cy->KI>DxUEg_%vO?NcbsYC2)RLSc5(!v_=!S2dLmE)=e7+Tzec;ijhZ zMidISHNAdBp>S7Imyw0SeNFouQz$&tbnS74!edR}olq#uZR$U|P4#4&}!{H8}w zDHIkoWn&A4*P6CEqfmIOY3jH_;k~9e&ngr?YU(zjQ24BAzlnvyS54PXE)*6v{V=6a z__1ltX@$a~rjw=@3V$>`KBG|hySaRE{`X&O-g;L44k$KHyDWbX6r10koxcl;%{}Ji z?}K9V0axemgktlJ*XHkqV)IYe=kJDM^MIT3_d~Hc{WSY!i_PiBk*`>6PCrk&Pq8`u zK;VAG=JXR?*C;lpAIZ6Pu{r%r#ev1<^h5Cm6`RvfHQS`voPI3T=EdgpbA^T$o6`@5 z*{;}}ezM0-#pd**8HN{|)A!cjz1W<-Ir`qk=JegI_b)c5Z%=%1u{nKz*%8I&^bJCf zDmJI@@OW&oIem-1QN`x;J=Vq)o6|SRI<458zRS^>#pd*FYR)b;r|&Z|vDloxQN)yD zbNWjE3yRI@OSNYfo730Y&MG#iFP5BLY))V8c2%)CeYw(g#pd+&CN~wE(-#cfR%}kM z_`a*yoL;hfU$Hs8=JKIpb9&L-W5wq5s;9Zd=Jc|aXNt|~bqDi{&FP8b1;ys{%-?Ip z=JeFfTgB$|*!z3M=Jep{N5$s!=+|e(=JfEzSHMv|6+^%&rNOBVxh2d{{ODabj{nE_2=ckUg&yveLmKT@lYBAVtknYr(ImT zJ_nrtYp>>il;S$^D|@9Ixo(V+>CduWj8SO}j4>$xcId_RWAsjchz(-YJ^DVjLHFX0wT+7>U4Hs0g>DP;Gauz=hQ-@yd1Rqm z?xpZu-p=)QzMuKSRj1@{r?zqOmuHVZHGf03jhEarXY%MJZ)wrz6R#On=#jfB{F$HX zwnqLB=}lhu|Gddf^OoM^``+ZwkIbGvX30(aZmHINmb}HUCj2*c)RMP&@eRK`eR844 zmieLbYWZ8-Isb?B2kVr-zw*C98>7_ zV;tGKdZe~--tDg}JaNgHErzeN*^)CS{!rCT7rLFFzYEe0-=}(}Mf$tA zDsSnAU+C>zxM2Q+)xV3|o*aK^{21+*kc8zUR{WAI^V+ z{GD~>)pOrIvC!?EIMpjZx#aKR-ti6j`yfB`;QYJCR&Pu552H8D&t!FNr#CKN==Mmd zQ0SH4l${(Y{qbRbTXPbNkAGmql3PDx^fH?)`CTsf>FH_t@3JtCoKrng+xW&k^M1?U zG5K%v(VxG5mj8zNyZ_t|raznib>_d%?gwtxzRS>1ra zNAJAkH|f02)NPjh>nm(}*ueZ>{XgQ~0z8WI{omcqX0p2p7A#mHSW8=o;Iz;Zg_IZ( ztg;Odq{SMfP}v=5z1JJ2Usl zJ1gyAhraul@nu>@|2{V0{$*^murN0ia{n^YA{qT3wd<|>moYe!*?(W7?q5d4UisXv z!R}wi=QhpHHsJncd|~17{&r~Czl=>5dfUP7{$->`GD6|(@Zb(zvLYRNcWBJX4tL54 zh0+Fvva)tE6bePUhaw$z$l5V$TvmmhHq!NqopZcVAxARO!;ua?M9f3~QCdi9OCN?&+4>+e?`sE$5D6+va^z zXW};9R>vL|wtZ9RZ=Jr!9TpCy^;lbM=fHmULdd;fS8v8KdGbPT(Mvk`OSPtl+Wu{8 zF&wIOWrMk#9;;t{j3vH(*1@oBdO11q9hi16K?56s&`@o;wR9BeY z)C-uwmNl4Rohy&qzqHWW23MJ5UCJEm+#J)@z`6_Ekek1oWXrj_Y?m%;U%e}CZsE{$ zSAxdX(>SAU+|)lemd(?jNb^s=>}F;s8~d{b>(7mo`j?vX>?nzZUbacn!hdvV9}3%_ zjcfnHd3pIQP5JYdFUw!vGAF+!v3yQ*Vp+@570q*2G|$bS)3RpSilq+BX`Z{XrFnVE zYi@iSdtCmqmW7KKu2{ILIh4O(>Eh=6rbW%G^Ya!hozt`^fBAx@mgfAH<|WO`o0jJ{ z4^J##v2yOhrTHtCE?qQdLDRw|%k$^YnUiR0S)5;3kQk8|UNF2cQCQ&MFoVOEEM3w( zths6S!eNC4c_W6om-Fo9HZSEbTry|T%DK(?i<{;wSh(c>_hu|#vpjW6%wLdS)G~MF z!X-;fmbNqxOKywRD_Za8eKJt z-DE5K|KZ&K-$<~kX+^W!7om_e8a*#>j*~1gw|QRE%0(*@E7mM)UY@tWxoaZKUASb0 z1@qkWOUzlic=6IDiKb->jhV~!C1nZQD051DZp_Ya=(*4>DnKFoa)9R_3y~3F&+GEv z{=9HTWPaG|7U`Mig(LHG-B7L@%JX7w$jhkqI%nkO*}w#^ONPxVBR_wFpw^74lk z7FZd)t)s^LSN|W@{x)5ger`q?-Mr3Q`2$_O&VBuXE?(zhZh(a(o8tAgg~oEdct)iC zc(1#KoP4i)|Dgu*y&Q|KIvmd^2&JWmyLla5>F5o1#ke2yyqpnUZa*7oyq9Zm@Nh4u z&wrT3PTpWQD}T~~|7A`+huegCUQajT1TUw;&Bodtv|&oJ25p<*=fMNK?yki<{ZB3Y z&-0zHl?-M)c%avPE5F@tac;JKE&Y!xp6i-BKDnvduDwe+dHxKOg9ZPKZO}au&+~G( z^}3I+X?wSs`Jjs~8uwY{a8z-JIpv`6(l)B?`z3zVdGrD-) z-R|o@(>7?AVcwwRh8UF5HP{OOi@9j$^l!6G;~Cnv1=^bbXV-tr&5J3?mG=hyTe*L4 z182S40JcGFh5bG6c0H@YT>nQE;u*sOZD)EpZeIB_XF9#KY0YKV5Zi47thUSb+Pgz; zzSqlb?;!)dURxQ-w-~mnjoroVtB&3f?J_^Q35R=I+i3msy!QRQ{{0N3CA!S?dK()u z!0X-DfExOrXAmCcb&9-p&@OhGx;mWaw`8`pyR+T#VgJPO?LoV67_~hD z+ivExzIK05USFFitE)>?R8K3atSC(s)lF)wDywb?@j_KueSOiSvP45oO`@`Mw`B*rmD8Gtii@?tgg^_L(?N8_UaW{`D2J%94}(Yt1UE+}8BRaa*#uAhn?t)rm$HJWh=(EN?SP zN!`rah8kPt%F0A-O+|G>nO1qY#xJsJ7u*rU6D#~RC~Y%&aiv{t>&pGzP*z=Ju{2au zUY{r`4Q4aSAKSI8JY~hp8YZ)S6Sb3PCTw3<*8O1eY@0SSNjaX9D=d48D*YuVYHG`>ldqw2ab3lv$qm)E zMHBU94Gr#CX3^y(l~erYju;snIivg~`U@`r`3IAaOkwS-v3jx4HeYgX6%}>mMTxSK zl0;!~g%0zQHix2rYALNKnv|$%Y^ZH)NKC7#Y_Q`eISY;kcT#buA9w0XIXX+rrd8PO zWpQJDu$ArDNIf3~hmw=oHnKao-S$YCyl#da(utaBWp(A1HPg3TXkGQBGTjR-CeN+zx78bl`i+%eEtIlO)P!l$4c~rZia_ z#Lln{MRtamQZ_SDUR2?Za`vIdaJSvow3@~`8?a-nyt1OC^{nq(>P}|KO;)iArThWG!sxsS4{yfGe_i{gu~O?ChUxc^fvPngiI^^ssUuwsE>t)XOJ$Xe+*~^7v+ZZoZCfl5Xo2>tnPm_2U zFn$!M+ytY>~0{rXE=!zBub|?BuXa-Hw10(9!95(uM=REo#Gnn z{Og>5k}bClQa?H6^v*$1Sv1q#i|PVyLw4?)w{ppxf{`OascB?jrZv&EHf6N2ZPK`8 z!;=Tr7JC8JQtq@X?Z9i5jh0O+s;VkVwv2t?4m1BMYByWKwZU%h*noD@@S7Q&Sn6E| zqG7li?u$C9x-qw8+_+r#@G!41*F8Qg7(0Aq?vR$|Ma@mio43s!ws_96l@sPHZCTO0 zdf4I-BMhuquyXNitMe8uZCWwRo;^;m)6rZ9Y|MGfR*f3AeA%$Mg`iPUR~YjQOSqPO!lmwK;0A-`yi6 zcK|T8bN)Yc1IsJQYuffvTXiZeD)AqWH`wF!8g8?~s>I{0=QnA)Ltw{C2@K&466ISTHhk}vrFx_jlCYIk<^nHw_RF>-BD|(&^jE+_N8or z+Pa#_71j&2T~Td!;`UU7Mf!@khB!?s?3Q?z$&g6c`#i1BSPJc)-WK3@W0HLtX5da` zsftxB@sGobCCmK-GPxkcDK9Fu2Si)+ynQKLD<+xy$vd3ZK3S=*kcHNrVO4FbBxlY| zdg?*o8(rdWy41FAaa}K}cMt25&w1>aO3pOdODrn(AKN8gNZGJ;WexxFZr(pt(w%oL z33`Hlo9w>F)`2$J#ojuM6(tq^^{2MTEJ%746dX6LqfIN0Vc zKG`dv9~^Ys*b3UDZI9G8*G9WJ3bu!J4pX*=y8^l%Qlfr(MT5PPayg|JS=jmrqR`IN zq2&wgHYwR3cYQ{GgWDC_A8>s{2ZFAg|5C~UX1Cg{TPS(|;BHCmnMGn!QAO~;(7a2I z#>TO}Nn>T}-G|ei8<^BP+~i}U;XF2Sy-PL}Gjlf}p}qWbp=+Y++%ZaOhru4lR+QK| z#m?~!{&q@^Rc~Erd*qRz2RHhJbUGQe~Y?~B8_yXjiTbft>BS0uds&Y z*8j7va-zJlsJ?YNUTv&(X1iw)JdNL?H2~nUvY<~*pRet)@8q>Rm@<1bVh?JAyEnfb?kTrF5InoD zDw>ffsisem`smtk+P^QALGO(9Og`fCXW9A;ywIM=r5;MHkCEKU1_wc#lTY$tftzD; zGp72M>}_k?`j4mm#c~F3y_N;fn%#@8C+Lsl9=y_O|Ke-=-n=cb+w}kZPDt=zx%JBQ zuhUE+J%U2_kd}F;Ho3f_()whn&mmfGQR?eU^p;SY?SQ<Q|l-m7E%8d;#Cf|$Vf*N#D0w--n{BD*Gwv_csHKfg( zH(KGw>M7MV(}V3nFUURpck>N;6tuF~o^{(hdH%aB{>!e5!;2}m5^WyG_{}TSmB@8~ zeBhp~`UAo9UpGh(r!e)gs^;n*;g{QS!(%NL8mt>99v!JEPiWirPPqH=7i>Eq*>?W` zwToIqQJuSew1dce{BH+p$^&ApRblXS*UdKQZ_zw^e?fOQ{+$PJG5E_*IeSa%;220g zB(=kxdm5cXdFQY&c(&`$#yv{)2ZCE`mh8^hZ7)X2<23d730h*a@DKCk_9&?=s;W)7 zk_VgFy$9&#+xli$Yv-WQ9;d0b?jZ5!>mHT{O>1+?DXO)5_!-uhZX$lQC*u-dLMRuRLg^lh z-xxcOBtc14X`2qH8PDEJ?#EQ+TF=bxae3;yRx~%*0R9H#S!LTkKhXfwUC z`o?;DuS~t-e?8Z9k2JSf{*~@O z^=O?%PD6TWZZ73Id_W`F{x6{3OUZZz|X;Sdm z-@SFXKwNoVa+imMM!Xi>jyCpn0t$EOS3GU_FTw?vzYkj&JyqQ6pT5sFhbXDAbw_~8u)`(`g*#un; ze~2@0@Zd6$pnuGaQ%>ZQ>!#R#3XaDL+vlxMKkh0TY?{_*pYEw* za#Y^+@jG{u>ReZPi!IxxJLy#NHOP82NMKLgbNx3^HW5ouxawkqhkxVaU&CymU^ zzvfgIwSNA=?Zz#)M{OechNauITuoZ%5$vexHFZ;TB~0Ei6x!{mosJmQPB*+4(zYvA zZtsrM3vr*?2u&&}*&%m`dum_QvN*SF@$BZgbM5`W20kt9Kgj1(z}x=!$NKgue*1j$ zKlW!IRzILayY`{6DW8pYAB`^VFzAT*k+GwqM`s-49h-h!;JcCoK4*1K7||#=i8t+c34%Obvvp<8QIaQcqB8{IlXJRTR11uBiu9GE8IKW zC)_t}K-j)b^RK^Dlpgy2pVSc|?!&Sve-VAi8x(P$l}-7J*ym*JTaGDz>7h=R{tP}F zZbQNAw;ZtxsOc>uz1`+bYRFm+d>1$v>B8B$ItZ z!-n_XBCpvZAH7AkZ#O3Y-1L_xQ!u~lx5#`(*?-q^(2CF?I}QBz9!bgxdgPXGthK)8 zu8jZT&D_)x3RBPZ|9&fP%j-b$t+M0`?!AnyZCx_E*|#oTweQl|_dY|J_KlD)T($3e z{O+oKr^I~&Ez`a?XWu~bd9ka;-Pg!6?Q4E@uG(~8tDa;&y6G=;)yBKpRr?OZ?XKE* zuc_W>o~GIVB=Bylnf8snFI3yvzIWN#nP$qlV>``uhO^04YqDQ$)}gcx_6-zQO}!!F z?wEDsjaHqYTC7^D+Ne55buZO@R1a1?LiH5Yi&Sq>y-W20)yGtyQGH4Eb=7xOKUV!x z^*hy{RqYF-{(87CZ@BfbZ-@HTz7XoyE~@UAtK94TR0pfN?@~H$Uj*~(7}W`?C8`yw zHL8uOyQ(&+&R1Qmx?FXQ>cOfQGH1D3DxISUsZia z^<&kIs^6<_R<(R+Q z>Vc|9s2;ECzWM0dcebiKj$FP%)qSDS<=a&6ReePDY1Nlh-%x#D^)uCPRDV+aLp9Bg zLpT4pYA4kk)xN5ORfnpMP~AbbNOiJmjp{Vj-BstR?ycIQx<>U7)uUBUQeCIIUiA{y zt5t7Oy;Jo8)yGwzQ}w@kW$XL4@<*y)s%}#KRrPOG&(2eBJGt|ft6fxksrFYLqMENd zT6KbIsp=HfI@Ot~d#cV?U81^D^#IkwRgY6$t9q8|1*(^;UZ;Ai>OHCtt3IXrqU!6a z@2P&O`nBqhs=up-?JGQPyTnvGs&-f1N_CLxFxAnjJF8AsovJ!Zb&l#H)s?CTsUEF* zit5>_7pq>QdaLSvs*kI_p!$aDhpHP@e^mWb)w2thTi*_OQLbsUEI+g6cZe^Hr}Gg^4cmA0-TGy!c2ymr zI>~Mq-Rt$L3+>wN@=Dd??dH|xGgYs%YqraGslH$rc$eQ+{oZaDUH(gTwB4h)T%vk_ z-D9|Xtm?ydkK*zRsxiB_aJidmb-y6*s(O0=AYY{V*1#Ztu9~}bkcX+xvl|RIzvZge z+HV24e3$AEb|dBTKdNKxM#SYZ)q@Iye7x$TBZB;rYNp+=xbbsTYsUt8chxg?2=XPW z@7T?-8~;ny0XqjdUv)uIkXNc+UlQbdRDUW9a=1LGJ4_C$eVWLh?;*Pc^+eUjD}(%s zYP*^s_f)N$8svoPS@l7_O!Ymx;d1T$N_EhTAQ!6cH7m&bs@}L;kndCdWse|75Z(T4iEAi)%8aP`6|_q zjt=s7szZ(o@+j3MCj@za)mu*r@pAzKg+MrH6EvQwhN39F;X{yhj8RR!rJD(He zeyTIp2f11G{PTl+jp`>C2Kjr{?Jf!O7}aH$1^GbL+ph@nBdUL173BEUK`p*Es5Pp` zTp#3hs?XmTKFAAIFMct|H>iGLzjx!> z`?G4^t3lpTb;avJK2-JYH-r3yYUrIHw^uEHFUa+(Cwvg(vsGXID9G=t_V_f&gH`wV zJji>iUixK_Z&Ka(RgiyGE%-Lb6I54i3i9Eq_u8-Rxb=HVHSOmhcT}DHYmggNPx>v$ z=c;b74wjq#L)Bh?2YDOSJ?;67dwsF$<@Td0F5ja1wf$<3%fG1(w+@=iJFBj?-|=zz zNY(r82Yp^T^vC6oRr}bl|G2!Z>TK%>y1Z2N zO8Y$^mv2-3)_xes;o~e4X{U(@kUdV=aY)vHwBQ~g}E zm;DTlo4#6gw(6Oxcd34-I=~*xxbYiRk5j$dRoi~|t3ILnjOqr}H&j1V{Z#c^)gM&< zQ2j?WW)BwJ{M)H^Q|+lbKy_=?SjdhqYp3mEzjjg0QSGlfSaqmsfoi2{t?G2uT~%kR z&Qo2cxfQ@u#_O4VysZ&kfh)lT1jyB}A5PW2_#w^iR)wbPD2zMWqDYNrjq zW~jDT%~tK9+DFxPuRs0>)g4uLR?Tqp%?zGPy6x)zT($0(Uq4I>YFC%D?Klz-O@E}h?&C}LcF(+}HoZUG zG<$YS^QvGL0kIzmNsUb{?i(vwNHE5~$s+d?ADW}JGL+|jIilIVB$l$&c`Z$gZKR^Q zs=THZD_R!LUb(_%`@j9`Z6n$yO+F1Dxy6LG8U4Th_Fp$%B#5Cc$8)c_zisTFbN&Br zJm>Y6%T4_m7q=hXpF0lX_HUy7bAMwOhC>%xwQi8VuibcVd5!juHrQb37<(b#jy?Vu znra|*es9?PUNk@4{G3zFugQj)#s))oj0%U|P5}(MEzPhS@6<8jP)!P8aH+kPy4)-G zx1ay97u|9lXSs*jFw@vz=)K^ z3&wN9?vK~j+HmUpVh6U)&%N(L`>sft#s)*#HoxI+2k4LaU1B+Pem!h{ZZy}vj`olF z+3ly_2IqtOD=7+xRt*Y<-GANu+`s!(8Sk#zBg>xTz02Z|F72Ow*$c{>+34VihKD48*h_AcYb&0AUD5G_RlSoW5WhR z2Q08(KXe27V}7P&oAC;)eP1w=RmRiL#Eco9w=_T3{tCwwj2>GseC+VCHe66pnDXDz zqetfEjvHM#Vz?VIchAg&%PPx*Uq=dN9JY56n6D%2-9v7B3otm=hlG0CS#;Q!n@g5d zZrFTpQ}<2%GA3?%>5#3;C;bo}_~_;%3L@X<)?e~-x5y$M@j)$69jZD+b&zVVY9G}es$Eq(skT#%siyn&jyL*GnYFYw^6-y` z6#c$o=KPwUZmfM|b9(l~9|qRN`uD1QqiN>+S$ob|Fe~)us~c=f^qR8Wp04(+*vqdy zCSUE>jsAbPYjUsc<^T6;|GyiXvUhRYc;dk5E{|@$xA3%uZ>Rscp`iS}FE$@uvnkv? z7z#ZQ>ePMWS(6ukG`*nH)~`<6-aYn??K3>>@ZDyNd49^Shwc?Vuzol9tBuZAvo?Hl zJG*DuU>DkU&g7K8v~b21c0i|vW0#uKX=&c3ZmvX^_BU}qv;U-3^{BG()6%``?Zg@x zU`JJ2P0u}j6rI(}Qp_9cU@ZD@Pg_*F=RWnFmL6@k8AV<*^&&&N6xryJA-VRSg02lV z?44}?$#DOP-fX9lX!-#*m_DULkEpH37w!Oz{cQ6L$41!!l;)q8BC*Tt08Ed4V#$mB zVFzDEY-?+BG``mmv$0jSzR$&0+nCSC zJK6BiaQqHy*06B=E*mQ^96zBH& z!|_*a=Ig@opDmqXW7=jrGaPr%gwG1cueX&yI~-qOubmT)y9bEphT~bbRzHQ~`Br`o z$E!`FU&8UTZ0Wy- z`Bfyo$mIJv65rRR`z8{<%r?fik@)wvHNK0)_psf(DH7k_mhgQf-q)5_nI3Ovji^eG zC#==g>G6X?p-@eFyuoHxn;!qbMwyx(A7IO?OOH>qQlB0_$(GlU9v@>9G^WRwn5fgz zcx+; zHR|TYPqs#^_Tuh|{2DJ_ZM$2VEe^r{3jdprD*&HoBZWy+-?R!uSDbSO{fjg_`BAmSEKQJY)iam zW2S{duSerkY@59ijela3zZs4HVa>fWD?ZGOzAGz!x6SPCtoWI>gnP2$hnTh(c8q^v z7F^UZ{-ibj;*RmL)}%{1#=o+1X~%fE&GWL3@pPN#R`HmYjIGEp~ZMe3EVC6*=*zY-6p=i6?9|SLMXx zw!`<$iLWwaSLej<@ljqwfE zh~|y)`L+)8HpZu0tLJabywzS?W<8k9`)psk(suiDH_+3@S>XoqOv9CK zzEV2y45qufB) z*5PP3@R6Q;>TeH*Mz!$dO>)gP0wum)zY+$i%y8Yb1KwBqw zLy_6pHc{9O*p=RHW^7=S?E&{moy={mJ?U;B!`8xc12uM#*zcHzGS}Lkh`NEWk(e8} z%9a&(1Ml08$aDh@W=EDAxYfpK=LSaFwzeN<3}x1vejVIEM;p1L8`xwccX9&<*f`m4 z;8@$eo!!8Dw#B-*ff+`+x`7Yu*y-j5`q)&i)tNimF0j72t*LFgG&j)87U4c$l<9uv zINc4{`q^68!0on^Gu*(Fw(f4M%%|*#3A=&&&Du0K(9xRVrVC{)vl*o?2}droY}dbG zHb%SjlP$DQ_qO(i+y3ZKToCfM(f`V)pT)wEH$<_o#o-}uTg9y`jtF_%DfY2AGURQq z*xTZ$kT+DZm&MT`Z~68pnpLRW&1GxXaOJKp zTf;^ucX8QTHd48>%ht3}%GoYk+eRyQa@iU;M!BQQ*1ECE9bC5NjZ<##vbApq<#v{b zTl;oY&T`q>H(oi@WozFA<+#h%zMYg~E?fI{R*t%C?VG5a;j*=_NZE7Q+E=Wc?y|M7 zL^E577gYExLUz$GNVE=zc)9GY8ti4Im;daP4 zL#B8QCX8=Lr6!djRf;mCT2Y47D9VspMHw?Xf+qv9Z6m{k}Lza1~OdsEn zeKe^IX;G9R%N1qF3Pl;RQc;GiQj{V4D$0=6iZW!4q72zj5kvM@#*hP)G2}pH3^_;{ zLk?EPkVBL)qKHlriL3Wehn^8AFa&#*h<~ zG2}#L3^_>|Lrzx4kW-WcLzYC&vi;xbLA%rOmIj7==uj)_G^y<<>Xk3{5IS z&Qz2kXDP~%vlV5?If^pmTtykOUQvderzk_tSCk31hFq?UAy+74$d$?%a+NZMT&;{D*C=DiwaOTBoic`8uZ$r#C}YTt${2E!GKSo& zj3KuuW5}(_7;>9(V905ayKVn>I@NA%ywd|is_jFC_^4llpzl)%8-W?Wyr&dGUO3O8SA&)C#$P>yK@}x3`Jf(~w zPb*`{Gs+n9tTKi?r;H)bD`UtD${6yZGKRdQj3F;8W5_GY7_vbbLta(Jkk^zk$ot+q)=%&a`9PD(kPj7Q z$VZAYUnt6uFBLIlqcVnkrHmn8D`Utv${6ykGKPGo zj3JwpG30w?4EaGBLw;1oke`$>G`N#HurzYzJdGGm#WG{5Xp>Wix6Y8AqrH8#-y9jl0y%{g8sry;B z+ujUvU(0q|9wl#O*>1~Y51G+e1ZR`x_?0_}03n1G8Yh_nJCkL#V-2fdO zuy%F_ba22LngeL>fVH#-pq&BN!|4gga=^A_FF>XP*3#a9xC7SGK7g15*3zv2Q3tH0 zeE}H`SWEi>JO`|$xqx&Btfl<{_N^4Zt1|$QX2A7z1_HtkSW5>1OpvbWURpR(W`bld zc3qrEIIt+!9xZr-!%?S~vuN9}H_uKzzD3(Hy)4?EEQ^McWzjIQEXpIxqI|L}Dj>_E zLb5CxPL@R@$XGNIfJLJKSTq`dMPmS1G!}qG;{aH+0|1M51Yps402WOEV9`zhEZP}> zMH2y7R0P1HVgMGE0I;YOfJJ2hEGh?J(IfyCO$K051t73!8~eR(6C`_2d-&oFkwxq6 z`Hid3OFo-B(R$g-%BEQ_X*Wzlr9ESf>a zqL~0Jngzh3T>)6M8vu)T2Vl`204z!XuxL*J7BvB|Xf^(KP02Un$z@lRSSad7^i;e?e(eVH*Ist%1CjzkO zBmfqj48WpO09dpZfJLVQu;?^EV9`F|NRD01vZMC2*K3hQP3|uG^l;SqW_nq44p|nROO{3J$+GA?vMf5EEQ>B6%c2X(vgjhREV`JCMVA1u=u!X{T?W9S z%K=z)1pte#1Yprs04%y1fJN5;u;^L<7F`FxqU!-zbOQj3ZUkV_O#m#q8GuE%0I=v* z02bW_z@pm$Sab&fi|zyj7M&4}>~4Z&U*ztK&Xh$P{k~W@>ilvR-52%_vNu+Ii|%K7 zS@Zx|7ClIoMGui>(Zgg}^axoNJxZ2EkCA23<78R%1R0B-1Yprq04#bMfJM&$u;^I; z7Ci^RqUQlv^a22jUIbv#O8_i-8GuEv0I+BS0E=D)V9{#;EP5S)MQ;GG=uH3?y#>Ic zw*gr64gibZ1q2q|6OLSBf@I(4#JN`%U14u?EczXQMSlRW=uZF^{RP0HzX4eE4*-ioX~|xG z&_@dcuqX`>SoA?S@}&uq{fepNeJG2*ckfR{(xT2UXHhiG%iLNP#h6|e#mTZLlPrs} z$g-#%Sr)Y?%c2fsS=5m%i#m~IQ8pQiIs>q%3jm9{0dR@2f(5o09dpm0E@;0uxJ7Ri*^EF(ar!Ynh3z6 zA^;W@1F)zBfJLPMEGh$FQ8@sMCIPT$G60Jz09dpO0E?you&5FcShQVQWTgp`{hNK( z#M@pLedjEyN{c$boJCX9yfe0wMRiOsi|Wa;sDUht8p*O~8d(-iC(EK4WLY$mEQ@B5 zWznu=EZPl#MY{vAXb%7uB>-5oCjg6@09Z5|fJJivSTq-aMa=*#ng_t5`2Z|h0KlS! z04&-IfJJ))uxJqgixva0XbAv|mIAP7832p+0R$G+q($yAL9#cvK3c6TddgkiTGFD< zFK5xJH1D0EvS?qXmqn||vSCCjK^UGOuZkjhB zUly%rdRcTHSr(m7mPHqkWzmIXS#%Lu7F|r1MVF9e(WPWrbQu|oE(c)I6#y){5`aZl z0kG(502W;Xz@lpbSacl#i>?P?(G37Bx)FdyHvzEdW&jr50>GkM0a$b!0E=!1V9^}_ zEV>hbMRx(P=xzWO-2(_LIy)^g$pp#X%RZUmog<4T+6Q^Od()!MFK5w%Y2JcDS@aOo z%c6(Lvgi@AEP9kIiykA(qQ}Xy=n1kcdXg-Qo+8Vlr^#6K3;>Is1z^#004#bQfJH9= zu;@hq7QF<(qL%?!^a=orHUO~bRR9*f2Ed}%0a)|~0E^xPV9{FuEP5M&MehKx=v@F7 zy$8Ue_W@Y+0U)sG{`S9{?7GBI>qdQ5b+lX#gyW0I(<> zfJGi4u;}Bo$SWpD_9T0U!}~-Qz2ZVfBIT4~?f@*x0bo%N02cKGU{Nms7WD>TQ6B&nZ3V!h zz5p!h2f(6S02cKJV9@{o77YYo(I5a84F+J*)&MNp27pCF09dpw0E@N*1Qx|2k)ET? zqGtQ@fESMhJ^hjPWd(2hNYwe|EXt2~JB*b@1xzoC3dyo)I9V2rAj_hWWLY$dEQ>~y zWziV2EE-FeMdQd=v;zQ(b_8J2cmNhn0ASHh04&-WfJGAlSX2bSqGA9Rl>o4)6o5r# z04yp8V9_K17EK0VQ3U{tb^&0~6aW@g0qY$)d)H zh1y8e`QA@d z09dpq0E?OcSTq}eMRNdHG#7wH%>XQ#2f(8F04!Pnz@mi!EZPfzMSBCVXb}L576Y(o z2>^?h0M5_Nt#i`GQE z$H&W}{g_@B?N63P2asjafn-^95Lp%-OqNB5kY&-KWLb0=Sr#2m#-bwtSac)+i;eRNR z2f(5;09bS;0E^B7VA0utz@mL4k*`dU>{r~!rB}qeMb`na z=z0Ja-2lL%8v$5!699{D24K-G04%x{fJL_fu;_LG7Tp2BqB{XtbQb`N?gn7dJpe4a z7l1|g0kG(PKw#1ONTkpN$^OT^8+)ECsi|jid@0H1-4ookLI+A5kC$cQcCd;DEWLeaOEQ`95 zWl=Y>Eb2~{MLA?F>H)x_o&YTB1;C=-04(YQz@n`HSkxDQMg0I+lncP3{s1f*0KlSw z04y2=z@otbEZQ1?McV+dXb1p{wgq6(b^t8e9)Lwd0a!E)5LlFz9*LBjMGv|!^S4V6 zdiu|~@1^FYN1b2JqT%+P=E<^X1k=l+kz`pkiY$vplV#BuvMd@)mPO;pvSb^>70&HyZ$2*9Eu02UPku&4xpMWp~NDg$6qIRJ|$0kCK?0E;RBShNcO zi>3gus1krhRRAoi24GPQ0E=n?STq%YMRkC{qJs2Dg$a^0ni!7SK^s;CsSr*MA%c5P$vS>H5EZUtci}oPPq6AqM?MaqJO=K*Z4Zxx~04$md zz@laV7R>`-(R=_FEdXHALI4)+1;C=c0a&yMfJKV|ShNIyMN0u#v)4 zAhIkvm@JD9A799=1qGJG9bSwaijssxP@c=A3 z0f0p(0L02ZALz@k$CShN;^MW+I==rjNpoesdFbpR|n1As+m0T02ZAMz@l>i zSadD`i`D}Ii}p*8ylR4E|7OwKUlt8)T|$;cmy%`C zWn@`&IawB6L6${Vl4a3VWLb1ISr%PG#-eKhSacl#i>?P?(G37Bx)FdyHvzEdW&jr5 z0>GkM0a$b!0E=!1V9^}_EV>hbMRx(P=xzWO-2=d)djVK<9{`K)2Vl_y04#bCfJF}h z0*fw4kMyoFi}vhj;#??;4soBDeK%l%2U!;N zB+H^+WGw0pz@k0?EZPcyMSTHS)DM6~xd1Hc55S@U04y2^z@k9_EE){JqOAc~v<(1@ zh5)c=TL2bq2f(830a!E?fJMUqSd<6AqI>`r6#xQ@I(U(9OpxqF?t^I^y`ZPRo%{G~ zp%-<2Ig3VlUWXa7Xf)HyqA_GyG?pxj#*t;w4rE!hBUu)WC(EJu&5CbSTw?mj4(m6v+OJR-bh)r&OJPu=0%-f&Z1eK*Dy;K z?aK7BXg9Jf+MO(m_8`lm1X&jCNtQ)TWLY$uEQ{ulWzk$R7BvH~XdVEI<^!;30RW2@ z0>iQ5r9P}0kG&~02ZAB zz@oJPEIJi{MW+F<=yU)Utpi}u82~Ig6M#i$0kG(702ZACz@l>jShOC1Mdtyq=zIVc zT>uCyI?#(eV1i^H<*_K-!FF}*ChoGgp3Aj_gF$+GAw zvMjoqEQ_uo%c5(^vgkUpEV`bIMK=Jj=tck*-2}j*n*msK3jm951z^!_04%y4fJJuz zu;@+z7TpEFqPqcDbPoWF?ge1ceE=-FAAm&<0I=vm02Vz2z@mo%So8=0iyj387G3N` zyo6bFi#z>XB8wKfcR(KVqRua8(Nmtcb(1W5n(1ZHGh|uxELj#kN0vp;lV#BhWLfkg zSr)xSmPId&8vrbN6M#i;0kG(802aLiz@m2nSo9tM zi{1xd(FXu5`VfFc9|5rFV*nO?0>GkA0a)}I0E<2cV9^%-K$b;2k!8`&WLY$kEQ^ZBvZ$DhMI`_%Dg|Is832pQ0a!E% zfJKu5SX2SPqFn%3GzEY~l>jWN0$@=!0E=n>SX2wZqNxBZssmtAJphXu09e!rz@ljY zESe6$q8Wg|qR|aTixvQ|XdwWL_5xth-T*9G1i+%j04!Ppz@nu9 zELsM@qJ02Z)B?bwyPA_6K0m0RSvI5D-|j zYer;_36kB--Cge{i%Q)`)(*;uI=`Gnhh=z2ERscsGrcT2f-H-UB+H_s$g=2YvMf4= zEQ^jM%cA4RvgmlSEINUVMJEEV=p+CZoeaRDQvg`B7Jx;k0b02ZANz@l{kEII># zMP~xA=qvyhoejXEa{yR$E&z+x1F+~k02ZAOz@iHPSacx(i!K6S(ZztkqC+wwSD7H$ z54un9A1aINe{*OZwv4Fr%UN_qhWGRmS#%}S%c85uvgm5EEV_m)i>@WhqU*@A=z6j& zx`8Zl|7TpQJqPqZCbTzbZVL5p{k!i=NH!I_)Eio@07h^gLM>y+D>lFOp@^OJrH}GFcYALY74v$g=2F zvMhRyj76^lu;>i{7QG3;qPGB8^fmyC-T`3Iy8tYD4}eAQ1F+}=02X}+z@m=;SoARf zi#`Eh(Wd|``V4?Yp98Sy3jh{<3BaO_04(|nfJI*e0*ju`h>S8pvTt_pqdg;wu8mmu zCL`+nau$7`;Z0jEi+*5wS@a`W7X3t)ML&~e(Jy3K^eb5wZ6?d2-^jA)cd{({gN#Lg z0W02ciXz@mQuSQLt?+m1zH02ZYIuqXn+qI3Wjc>pZR0ANuRfJHF?7R3QrlnKD1 zEC3d@17J~m02XxsU{OZ^7Igw(Q8pm3=(~)_{w7HFdG39*O|s|__Z7#^(WvvwS=2r1 ztzRjNa+qEg^&rclo@80ni!6(JlVwpKvMkz)EQ|V*Wl=w}EXpNgQGWmy4FF)#KmZmE z0$|Z#02XZxz@lvcSTqEHMcV?fXgdHFZ4bbrp#Urz2Ed{`02bu~u&4llMTGz?8VVw6820&-Air z0$CRAM3zN6lV#CFvMeeh%c5ekEGi+(qEfOfDkEc2IRJ|$0kCK?0E;RBShNcOi>3gu zs1krhRRAoi24GPQ0E=n?STq%YMRfoyss~_E0|1K}0a!E*fJM^*STqBGMKb|dGz)-5 zy8;4>#ziC1)n-wxI~VOBi_UTu?G}wXznn#TM!g~X$)YBvmqoM5vSilvR9U1kO93YF1VtQG0G+7oMLzYFyl4a3xWLb1PSr(l@mPIF$ zWzk7wS#&ZPi%tPx(OLi&oeIFB(*Rg>Isl8-0kG%{02ZAIz@oDNSadc3i_QUH(YXLD zS`WaY^8i?MJ^+g@0ASID04%x)fJGMru;>y17F`O!qRRk*MTbWtrP~de1#CdL|lm zemRR?hMwUgtlV#B#WLfklSr+|8mPLP)vFINF7KLK!wqsEk zfJJElEQ$cIC>?-B9sr9n09X_SU{MT!MR5QYWdg7$3xGxK09e!>fJGeuSkw`KMV$ax zlnub5&Hyax0>GlKfWV?3qLF43Bzw;uCeDwt=y7LJw^-Eq zi~5jd(N<(x)R!!a`jKT(E?E}!C(EJ%WLY$jj75V0STq=bMOy=~Xd3_)4FO=$wg4>J z4uD151F&c)0E>nJuqY3JMfm_MDgaO?E=7}DF7_01Yl7W0E?;tSX2YRqFMkJO$A_4 z9RQ2!0a(-kz@kO~7EJ?S(R2V7%>ZE0OaKl5RvglZ*mqo{sWzq3uS#$zf7M)0zMJJJE(aB_4bP8D(ttHE%Q^{C# z8UTw<2Vl`U02ZAAz@jq&SacQui_QjM(K!GtIv0RN>j7AF9srBZ2Vl_!04%x?fJGMp zu;^j{7F`0sqDui-bQu7PE(c)I6#y){5)fE)R4j6!36edjuZeTCEb8HY66>m1)cNHs zx-RCOf08V^p6O-L4P;q#BUu*RM3zN2lV#B@WLb18Sr*+!mPNOdWzijEEV>hbMRx(P z=xzWO-2=d)djVK<9{`K)2Vl_y04#bCfJF}hu;^g`7Ci#MqDKK(^cVn(9tU92696oF z5`aZd0kG(402Vz1z@ldXSo9nqu;`jtEXmT$nnkPK=dNFpMdRFq>>p!M=a;kS*O<56X|iZD)61gY z$g=2nvMl<8EQ|gm%c8%?vgmKJEc%Bmi$Zbr+htLhj74bxEQ$cIC>?-B9sr9n09X_S zU{MT!MR5QYWdg7$3xGxK09e!>fJGeuSkw`KMV$axlnub5&Hyax0>GlK04(YTz@qK| zEXn}{7X2KH)R-XI^Kwm`Uu4mv&Y~XisPoHN)F16V9|I$U{SAlWSt3; zy_5U7{oe7Qr+;gd)wR0F`GS^ySJ1z=Gf0E_AYSkwT(qDBA~O#@)jbO093 z0ASHf02a*xV9~AsEZPl#MY{vAXb%7uB>-5oCjg6@0D(n2$0Ki>AlXCQ>1U!Wnq{wf zv*S_cm$PVI-23xvSu~&NWzhn%ELupGMSGED(cWZPw1_N=7L#Ss60$5>N|r^-$XK)w z0E=1xShO5~MJoVUv=V?ts{mNEF93^H1F&cf0E_kmVA1{nEII&yMF#?~=pX65S#*5d zD_$>)PGEXjbRt<6okW&JCzEB-DP&o+mMn`-CCj4I$g=2kvMgFh#-cL-Sac=;i_QXI z(b)hjItPG7=K`>3JphZ&17Okl04%xyfJGMqu;?NH7F`U$qDuf+bSVIfE(2iER02W;hz@lpafkns0BlAs=?8WZ)i;j~;d${-XuZ>5YU(TW%Q02VzBz@ldWSoACai=G2u z(enT-dI5k%F9HIKu8&8qGeNS)xX)eRAdBvB7QGaYI=`Gnug1OSFO)^EF}*B$oh*yq zAj_gR$+GAzvMhR=EQ{VD%c6J5vgkdsEP9`eMIQjL=tBS&eFVUwj{#Wp2>^>e1z^!< z04(|(fJI*bu;@zw7HtGz(N_R0`Wk>m-vF@aTL2b)2f(6D04(|*fJHw5u;@ns7X1Xk zqMreQMX$soKbj!fpSw3bHprq9ca!u>JnH;%7X2Rgx?UoS{$P4p^e0&s{Y92Vf0Jd= zKV(@H%2dx?7KO>OD2*(OB4k;VPR1e+fJGSqEQ$iKC0a%m;z@l~lENTzH zq7DEo>IlH1P5>;*24GQV02XxtU{O~97Igz)QFj0q75yMemRT!WqPwNlSR2qFN^wv}gH4d^1D!a1GlQP~ z5ci(`#LTGk%UM*K>0Nk*EGlDqSyWDzMU%*~XfjzARgh)TE@W9Wg)ECI$+D=5EQ_ki zSX2YRqFMkJO$A_49RQ2!0a(-kz@kO~7EJ?S(R2V7%>ZE0OaKB+KcIB(cWZPw1_N=7L#Ss60$5>N|r^-$g*f3vMg#L%cA9EELs7;qLlzFS_QzO zeF0ds8h}M>09dpi0E_kqV9@~pEIJT?MF#<}=wJXA9Rk3jLjhQH7yye72Vl_=04zEZ zfJH|Eu;^$2799h?qGJJpMe{QwSy!7yOWivl3uIBT`wqx)nNjDLv*@HuZ|JqM=wzms zMW>Ku(OR-BI+ZMoP9w{r)5)@E9a$EgL6${ll4a3ZWGp%xfJNs3u;^R>7Oe+h(RlzY zIv;>V7XYy6LI4(B1i+$;0a$bi0E;dKV9{j&EV>+kMOOf@=t=+I02VzAz@kS0SoA0W ziyi}D(c=ItdIEq&PXe&$DF7Bd4Zxyj09f=a0E?ajVA1mcEP4TeMK1!d=p_Iay$ryj zR{()UH)Tf7G(oaocb)s2Wzi+hq79i*=a;kSjZE*(8)ea(OfQSxBFmz;$+GAjvMhR+ zEQ{VF%cA$mvgiY{Ec%cvi#{S_(Z>KR`UHSQp8~MxGXNHS4#1)>09f=T0E;#Pu;?oQ z7JUuCqHh3L^eq63z5`&PCVA0P2Ecyk2MZW^DXfq(N=(Wtq zyCz8XWA1Aougju}sD>Tp)B>>Wl@+ci_*xlC_10{tk!4W^Sr$dfSQGIuN2UH~lW4Zxy404&-H5Lom_W@O+kX3-}1 z%QJtD=a;i+K$cf}n=Bg0^s;CWSr!c@%c8BxvS=H!EE+tRgz^<6};(JTNK?Fzu6-2hm$I{=IJ0ANu9fJJ)(u&4=u zMY91|GzWl1a{*Y?48Wp!04$mh2rMegirip=WFO_;jV+f&FATJ>AS>$pauzMh^8PRO z-a9;svW?rG$!6Jw)TLx;LTFY9N$7$~Dg@F<5wL{-p-E3b>|jMjMX`&BiUlk7uBg}> zDi#zKyJAB{#r|H`%yn)y_&jepzV|!6f4&??xaN26lzV2*DfjGV+5DhcG>7TUqPb+V zXdc-tnol;17Ld)Ng=Dj+k!%(KqbUXlyP5@xh zi2y7*34lc>1F&c*0E?CZu;>&37M%*fqSF9abUFZw&H!N1nE)(W4#1+b09bT30E^B6 zV9^SIZ_%uzz|SH`!Z!0*X6a~xk(}QOD(z}DVXtyS#%-On?7 zS#$~6EV`6z7F|X*i!LXdMOTo`qAST*v>Jd#R{^kS4FHR-24K-z02W;Xz@lpbSacl# zi`D_K=z0Ja-2lL%8v$5!699|W1F-0302bW>z@l3LSacfzi*5&C(H#IR+5o_!I|05$ z=O+b*iy)DY^@e(-S#-1B7u}Tu;^s~7QF(%qE`V}v>AX!uK}>=bpRH<0l=ay04#bFfJJWse2eZ$3M>;r zBAfNkVed7I*6WGs?WB*MNo z&7u+AB>b5aQoqz9Cpq}#lV*{dZ2eWUD1mGi1;}PmBH1holFg!4WV0wlHjBb!v#2%M zENVl>q9gzoB?GW11%O4V04z!aU{N{%iy{ClY74-kb^t7D55S@h04&M?U{Mr+MI8ZH z)Cqt^odHXRJIdfF`7o9WG>eaL3fzGSm#KeAc0KiMogfNU1^C7VV4$YxO%*(~Z$#-eNh7Ucl2 zC>MZ50{~bw5P(I409Z5_fJH+9STq!XMZ*ACbRYnWh6Au@1OST;0$|a>04zELfJGw# zSd<6AqI>`r6#%fP5P(HR0N4yj*i(U|05)3avL zSf)3NO37wX8QClRO6 z0l=b}04$mX@GTmh9JpKriInOiq7t)chkk*`(a9n8OD&q09DL|`vuHlkn?(!AX3;{j zS=2~2i<-!0(IT>0w3uub9YZ#YmXOV&W64-_8~}@s2Vl_&04zEYfJG+(u;^p}7A*x} z(J}xQodUq3Qvq0X8UTw<2Vl_|04zEafJMszSacQui_QjM(K!GtS^>bKa{*X%9srBZ z2ly7vNe+A{f<#v7=dS0PMUDFKXk~Ip{ZflAN)9?NnMD^fy;*b#*(|!0Y!+QcHj6GN zn?+ZU&7v#GX3=W0S#%ZIELuaxqN@Q|v=)Fx*8s5SS^ySZ2f(6r04%y5fJHX|u;@kr z7TpBEqV)hQx*32)w*au{Rsa^=2Ed}*0a$bg0E;#Nu;@+z7TpEFqPqcDbPvF{=)&Yc z9}y(7Qa^XS$}DGkI0a&ydfJLtXu;_IF7QF$$qAdU{dJ}*}Zvn9AZ2%U%1HhuK0NCK|;WV7favRU*o*(~~mY!-b=Hj6$Zn?;|K z&7v>JX3>{qEcyz7MLPgk^fdsBz5!s-w*V~q4uD191F&c(0E>PAV9}2NEcyw6MY{l4 z^fLg9egR<7uK+CC4Zxz`09f=p0E_+rV9}odEcy$8MSlZ)i?$^P?i4{Hee|j0`)1LN z?Iiq@98$m3qCiUUb$OoMEWV0xl zY!;=Eu_zUQMQH#mN(W$31b{_t0a(-yfJN;ASkwW4MHv7riUP2xBLIs!0kEhu0E@Z+ zu&65li}nIwQ8xeD7e2d(az^@`m zG!TGAg8*1G7=T4X09Z5>fJMUqSacu&i-rTRXaoR@4gz4&!2m2e1b{^&0a%m=z@mHr z78L-ns1SffMF1=+24K-B02Yk~_!jM*5;#Z%i9D>G`+dx!U20KDN=W@ui^@`hN4;$p zl{39rR6#b2D#>QiII>w(MK+77$!1Xv*(|Chn?;9`&7$#SESdnoqKN=3It+kChXb(a z2mlrx3BaPG09aH9z@kY2EUE`!(PRJ?O#xuhQ~(w=0I+Bp0E?yruxJJVi)I3_XchpA zjs{@SYycL`0r(b;O$nSTf<$i7&s~?AMSJN@(%h7g`lS{vObM>rY8Evzy;;;mHj5UK z&7#F*v*;MIS+s;~79C4Ai;g3kMaPrPq7%qibRqzYP6A-j$p9=`3c#Xe04zEMfJLVQ zu;?@Z7M%{jqB8(kbS40cmIJWpEC3dr4Zxyv09dpFfJNs5u;@Gh7M%~kqLlzFx&VMh z7Xo~X=BEUn7eOKy=;>#HSu`hA!m5;z`lS|KniAaco>_Dm)0;(?lg*+l$Y#-%WV2{B z*(|z>Y!;57TpTKqT2vibUOfx?f_uX1^^b_3BaPe09bT40E_McV9~t*EV>VXMfU@Ii!M$H zq-_(6zSVQlC1z0{eUSY?N=W@uiylb{W`AH7J<9ZE(PLz@=y9@Hw2^EUJwY~$o+O(^ zPm#@{O=Pp^X|h@L3>k}_1z^#004#bQfJH9=u;@hq7QF<(qL%?!^a=orUIk#$W&jqw z2Ed}%0a)|~0E@N&u;@(y7QF?)qPGE9^bP=vwgRx|T>uun2f(6j0NJX3>{qv*;_b zS+s*}7JW^|qHh3L^eq63z5`&<_W&%~3BaNs09f=R0E>PCV9_oB7X1vsqF(@5^eX_1 zb_1~JHvks>4#1*609f=V0E_+tVA0@FfEws_w<+QSB37A8dAU1 zq61Qc37?roeVN`Y>PI$qLBbB$^&3gJ^+gf09aHAz@j1m78L`q zXcPd8Mgy>@1b{_j09Z5@;9Im`YG5A`B=WJob+*4*RIhJ`l%|H%FSV#LH8}bUvuGUC zn?+S*v#6SE7S)i=qFS<9bST*@8c#NhCXmgdiDa|rFftY$4#1)#09bS+0E>{w4XIyh(W2Dgd0&}Di<#amI)-c(Eg_pl z$CAyW(jMfU)(=w1L8-3P#;`vF+=004^~1Ypra0NIcw*gr64gia`0^02aLmz@lvcEP5Y+MIQjL=tF>S(W9w>Lqw3s+xofd z$IPNr0ur{ThSV>$=+o5Tq@8BbXH0JveNHxuz95@LUy{wDugGT64zgMFHQ6lshHMsn zOE!zXBV*C`04&-Gz@i@jSo9+Ri+%!N(JlZM{S3gOUjSJ2D*%gj1F+~f02ciYz@k3@ zSo9|Vi~a&&(cb_p`UikTPMUSwvB(8rQ33#q0st&Z1o#$xoEkV?1c_X%pS%9VELy4` zSqr9x)GxKDbz1O-AI+jROm7w?kFg1EJ`PvMG>-D)Rt@(wIgFu zdjJ-70ANuD0E?mkEb0irqD}xT>I}f5E&wd*3c#Yh09e!wfJNN_SdIuN2 zUH~lW4Zxy404&-YfJOTNuxMWZ7VQV{EefRtUKBwhpX=l5aGKxKzf?alyMJ0p{Zfmv z(t_XYGK=~%y;+n^Hj8q|W>GHLEE+&Iiw2U-qCsS{XfW9<8bUUUhLW*p7yye71Ypr{ z02Yk^V9`MUEIJr~MTY>eXe0oO@&H(r55S@V02UPju&4-tMa2Lt8U?_j(Euze0btP> z02Yk}U{NUmi^>34R1WYh>YEmb{45rYSBv_YMZ>%fTUto{Qj4n7g1Nt%MKw%s7S)o? zqC?4M(Ri|1G=XduO(dH|hmp;q!^vjR5oELINHP{31;C;@02WOGU{O5)izWlGXbJ#} zrUJ020f0r*09Z5~fJHL^STqxWMY8}{bTj~qW&^Nj4gibh0G%hVLUIdBUr5{YIGK(Hni<;6x>X%xyBrUk)H?!zirZ#&7xDtSad1?i%tVz(dhszIs<@3X9BQjIRJ~!0$|bE04zEO zfJG|+SadD`i_QaJ(fI%@S_#0S3jkPjApnb30kG&I02W;gz@ke4Sac}>i!KBB7A;N- zTqS};&eMz7F=o*O{d=^_(?aT(T69%f@UcJ4qBTr!7F|s?i`J6OqHD-z(Y0i==sL1l zw2o{RT~9WPZXlaQHjev*;x<7QGC>qE`S|^eO<0HUqHeH2@a94#1)}09dpIfJJWtu;?uS7QGF?qIUpT zv=x9w?*g#sJpdMM17Okn04(|dfJGkyuxL8~i#`Hi(Z>MaqK#>R{X~#Rf_^aV3A1RK ze!l3Fw2=Cx7JZQx9OLK=K{kuNCYwdykj}M#-bkqSo9MBi*^C9=w|>H{Q|(EUjbOO8-PW>0kG(I02ciLz@k3^So9YFi~a^+ z(LVqza?-8ajzum2ixL1>6aZjRA^?km04!<+z@iYqx9GF9z&sHoa*zJMv7ehoKkMZ! zoE}oY)S~3{;K~HED23_GqExb3ltwm-(#d8~glrbIC7VU<$YxP{vRTxDY!+pZu_y|_ zqK*J8>IA@|&Hyax0>GlK04&-IfJNN^SkxVWMVSCB>H)x_o&YTB1;C=-04(YQz@ohY zShNoSi}nRz(S86d+8=;L2LQ0BFTl5`O?u#75hPNfw?awjeoy~?eQUN~dPx0Ji*nL~ zZzY;VxlC^s4IrCE1IcF5AhKCBm~0jeA)7@*$!5_ovRQN>*(@4P#-b4bEIJ5)MF#`0 z=nw!FjRas(9srB-0a#Q3z@kC`78L=os2G4nqX1Ym8h}M504y2 z$^lqZ0l=b402Yk{_!jj~5Bwp5L{{nhXxV1bk@{|IReDJMQi~2v4|WZiMdO*?ESf+z zizbrIqQl5$(cxsX=m@e|bR^jE zrUS5O1^|m@0=*(Odu)%>!W3d;k_L0ASHV02Va@u&4=uMT-Df zv>4!9RFfXa6G0;9>nCPw&7ywV?LQ_xq<*PI$EVBxxn~xg!1QL(iDa|rB(hm_GTAIz zN;Zp@k&UV9}WXELsl0qO$;4bT$Bs&H-T23IGB+7F`IyqE!Gax(I+p7Xz^95&#xm3c#Yv09bT60E?~wV9}KT-=bsF z180gLku{kj&T(eZ+iKD3^pN_c7OhPW-jrk(UBmQd(Y0i==sL1lw2o{RT~9WPZXlaQ zHl|7Ht4v(VYM+x(k3scLT8K9sm~I z3&5iL09bTC0E->~V9|pBEP4olMGph8=n()GJqp00#{gLLH~@<_0(^_sqz7IWK_bWK z+xS@Z_!iffp)24QMNuJ+GG~p zt?$Nuo*q)a)S?~f!GY;!(br6G7JWlDi@qhBMcGkQ0a&yffJMInu;_OH7X1OhqCWvx^cMh&{sv&tKL9LpBGzrkA{T%~ z2>>h#0I(<#fJH$77PSIkQ3!xVVE`7j24GPefN#;4>4AwNNaVMkBFbs(EX8Dz64N;Zo+lFgz{WGw0oz@jby zEb0otqP+lE)D3_|-2qsX3BaNr04(YWz@lCNEb0xwqCNmD+8cmH`v9E2f(8J z0a$bZ0E_wpu&5sZi?RS%)F0qmloAPCErLW|4T?Ca5x=K@gFbc4j)c@NwP;`@xUs!i zG>GZVqQPXdXb9OX8cH^chLO#p1IcF5aI#r6f@~HYL^g{KCS%bd04y2_z@j_=7Ucu5 zr~rUPg#aun0$@=w0EOclMndYBS~M{dY!x+&4r6+==y0-GbOhNf zI+AP_9Yr>a>d0o%B(hmlPd1Atlg*+jWGtErz@i2K7EJ?S(R2V7%>ZE0OaKjwq z@sYp*B1q&zy}O=Z7M;>V!f}z1`lS|~6bY7gGK)@Tdb4OL*(_Q{Hj7Rnn?B+7F`Iy zqE!Gax(I+p7Xz^95&#xm3c#Yv09bT60E?~wV9}KTELsh~qN@N{v_& z)~Ajqnnh_Eu8xG%FSY2pNbtfgX3;vPH;b+(n?*N}&7vF0X3Gk20a)}H0E-?6V9`bZ7CiyLq9*}Z^c29i=$c62ei0;cQL>10ty#2M zE!q?bsb6Z*bCKXXdznSgGrd{#0@*Bjk!%*dL^g|FCYwdCkj^>e1z^!<04(|(fJI*bu;@#GZ_zW6z+WOrWTgHL$g^hA<@#5RUqwRd zms<2~B-ky}Ec%Y=&7$wgX3!xD0$@=H zfJI>d7PSUoQ5ygjB>}J~8GuD80NGt)H;dYn&7uxuvnYdX7DdTsQAe^_)QM~sbtaodUC3rpS27mu1;CI z04&M|U{MYLi*ffOY3uj&*N8m90c}I-ms&KWZSdyaX3zMSX2zaqEP@W z8V$gr5&#yB0btQs02Y-3u&4}xMdbi2ssLb7B>;=Y0kEhFfJM~+EUE!uQ7r(A4h3M* zcz|!wptgZmMUY5H-}D%47H#o5Y;8m8ms)g0+u+W<&7vcj-YhzbY!=m#&7w(Uv#6eI z7ELCbMN`OT(NwZo)Ic_irjfB|Isl7i0I+B#0E=b;u;^$27R?4=(HsC4%>`i5JOCEW z2Vl_x02VC-U{NCgi<$sfvIk0I=v-02Unwz@p;;Sabrwx9G68fe!nK zMYre&(+)R_cIsa>p4c{|eyK&v+6D*jXBM5p^k&hiWV7frvRQOG*(^GPY!;nKHj9>% z&7!l&X3^PXv*;W$7Oena(YXLDIuC$F=L4{4B>;;q0ASID04!Psz@m!)SadM}i!K3R z(WL+^x(t9tmjkfq3IG;e3BaP&04%x+fJJKnSadZ2i`D|L=o)};(aCKChl?PQbrOS1 z&7xMS)U|Cx>X*~ONeK38eM4W@$;g$vZYQHgzK%9AW3jwT63)0xE`-S$4@Dd&J!6}E z5}t$p#BnBNROLC&)Qrmt9A`$x2StuEJEQk#$C;loYmDPGWo#&QoFy5*lsnD| z86(Cy&eDuisvYOFjOS_{XL&~I1jkvCQFEB%tjxIL2*dJRQT=~~ zO5Ldb$1s&{RR3p>8aJx{HNylqs^6`Dgd5c_N1x5al;u&sKzh8E?8`Uoe zo$p5V8y=h7sD4G?5;wYdyX+n}s$Y_|)Q#%59G&Jy^=oRDyHWj~kri%KzbIm*8`Zz` zzsQa1pK4#`M)hxPSG!UDW68B{RR7v-og39ZSGviK>ff8(>PGbs1~#}+{lxb@Zd5S>c3)sL+_=SKB&2QRr%edBnu8`XFIwzyG!>*gIds?XlH zxlw(1y4{WH)2~n6s6M{<(v52W^BXs+9f+N7RPO+Hxlz4@?{=el4*t`1l2%0Iz*^@Y zavc-piti3c>KKxpDnFmfvF5Jso#i^6mUh)w3UpYWmUus%&X(iN9WX^%kq|N8>2$74 z>JB(BGI9JJU=dIFpb_b=NFT=8hoo({l<<3-LgFWVSc|gMu z3lGT=><Pi3^nq{Z$qd&TJ{;Xn(ea&WuDEmUh5VPQrq2?tqtpr?d`E%en@KE%Sc za*l9E`l0IxS=j!vZa?*NoxR-3VC2o)ZkxE5JFZpavJ38Ab<$pLRWNyccKY6Xxz)ks z0ke&bjOCB*%4^|$W#X=K;%w~=1RbZ1Hy~Ro z$>tmM=bM}+OVrt=v~!b^n&*(3;snAhJ}D_BDLHAV%r7n4Vytu-E3T0di#G4JHcN@x zsCG6>@73m6wzpZ@SRG`dU~@Y%Qe-W4$x&}W)}&*Wdq^jix=*K)b`iI2tC1Zq&F`cO z=@g7>Q9|_oeA%j<2mYINiD$Z{x}J54D|;lToz7*ivrloIgpL>Fi!=;ND5ulo1svfaE1sJn7U|TLu1@)I=+lOtpEIl zGv~}~nz^{a=|5xMoQD4Ovm2K5&ze1NO8xBqjWg;OHuPWEFt?$xzOjEpZe3&3qNy|I z^>3OtZ}yZK^)u%-_MbjwN?rZJIsJ38>ju>2X6NSA=`;H0Eu6Y&=G=J&^Ae8(Z!4A*44+0vv6ee0%7ZlaWMwwFJaba>!LeH7HC?7dNSH6@}#SaW{gTZ$H?I-BA3QTu{ z9Ri)Qg5eRtV5=j7ZCklnGSI(OyEU1?cHMQbzd{`dw)5&(%h^ssqT3;uq$MrbLyNrb zMV&>ijNUoeE3ic7lV>5$M9oWZS?;m@;pZEHbEdTYv|9ah@{up~b&^q&9V|X)W!Ob)N|8Z7u zA8#iFW@QDXqm`Iodqeh0W}s81w`<&1z3?ehMv3{98T4Xivt7MS!X8rF1>5!W{A}B* zeZOF4uVCA*67>}oh1yeR7}Ir+*{iPIb@ai(&T6bq=H)?>MVD9}DEYYN+*!@`NB!R% zJjgo?GJ6Kwb(2Y39z%OH${i3)58QR~h@cyI#mUOdN@yn+sp9I&x}vJ8x{~rk^GZt! z>+-5b)s_{N*EqaTR#aV`H>#+vrlO**w4!{JQ&lvoE+?;GbZm@*n(A7azM!J4vb3m1 z#;h$bvGIxvM%PVl9x<<~u&%tKMnZ3ClKI*34J|3Jt7XB%tZ_NTEk-G*npjy=A*)XE(hQ_AqMU$P1;_AA*LVt0Cyt(Qc6vu6#qMFg{hq}tq6YIo@GO?i`ucoA; z+~1zVViV>R#7$XJHLfmSTr4c9_8Y}E_h+dy^LB4tX-WCm*w!6iQe0A(SLv-yK}C6a zQGr_J8CpD0H>@{UXzEng78Hohv8hpeTy0TpQC+cY(b!9sc~vDf6Jt^3FUu>RXuG(1 z7T)fyuBi4}P$>4t8ZgLPK5Jp)73autR99V5TwK>;Ybs=$7Kyg(Ydv~pm&F~HamQV3h0U_O zQg6w16_rKhvDZ*Ozp7-^=$dlbqIK0pH8pz7v*_Z2(y?B12MqL&utDAuy}gkQ@(wx= ziR!kmhT4lcviV|jD=Dce&Z{dbD5%THFR{}>L5oAyI|UV%M$T<;QIt-9gQZ z_I;0gS$2eMlDeV^1w}=LaZR>$k~48lo}5X>7EP=x&MVQg0sGL#&{Kmnt)jL{2ILqk zE-fi&zB+i8>PauQ>2h*o2e=&S{sAb*-_%8O<{TTFw|6)cRg|MwJCUXNRNZ_kC@83? z8!e}(*aU2wvWh~#^>UXGd$FLXw6wM~uS#SeRZ=Zp>m`d7!7h${zm3^4xwncfPTsZE z`QGKdu6nfG%lKo;X^j(H+#<`0r8z@eXl`DN zmN~`Uffce2vM2WtphVAkdz@|J?;Pa#_l{d{Tf`27oIx#S#4*Fl#9hSyZ$59~agEo{ zZlT|Qyf!x5S6W!%ot9&lA~VI`v2w~XA#!r;k|(zSv3<&!BfG9}Tuoi!X#XytVShE72J19(Aafr9pC36eqmAcCMsZ$%KmNiaqDT9CQ(r$ydXN$@!YURx49U(1m z@M9N1x%bP$$%E;(dNxZbz8jV_Zpqc-;)W1Zu{HW$CU$5Q=^ zK~Y&{TpzALpFYH2dbHi~UC`0v*SUFw#Yt-T(L3X{piEVFSd_Vku(vvGLDXwVQ z&1|-(Ft5OS99tugZ)5Y1-IM(LXz;smN9(~58{J>)+VZ?Z#dYmP$6krssCl*0N0&Re z_&&Mbb+PGub4E%3#=ixMz2NDpx4RYPdNS}X^*R63SM9)&4xb6s+|O&-eNzWxqSKJ- z%91+khU@;I+n5)do1FHUvEDJ+GUR61hH|9O5NluD7O1SM7+oSAN!br=-l*rxeVIo6aoxHEm{5T~?ZpUQ-UQZ;}9bpD~=89Jgjwr=>h4P?fkISwnfi88F zxE{OlY3@c9+LbUzdLXQtY=u~>xu1@g-ZQws+f=kc+qTD*I5hy-}oB9GhM2cqtxVS1V7+WMkS4ZGQ5Mj4dc94ja^towc%g zPSV$}*7IVsmpaOSyzyn{ws`K>;)XkR15el0?_seOY?HP;GTB$&_K=$(e|tzjE^d41 z1x`CNb=BibYUGu;t0f)2oaUznIdW!p8fVCDQLGEC-8*jqasl=Rv^%H3?{#@E#T`&` z2j0Ae^r^4+$VKls%Eo%@sc`_tHyo?M>vXh)C@ z#mw~n!kOir`?QJL4`Y=0euO+}Eh&(5h@8`FyzLYlt6F-y@|3`y1hC!W-dg>?^@d_$ z!{kNNy)CMJIvS~mVqU)Qmj5)GS6IVh>8eSuwywA|uey0UUahTEv-Pn758C(WWX1MP zL2*Ize#z12-7Lu-hWOV=Z%6wN>vb^xnYY&q+~d5_e8*T=^k427bq7x@^1Huu1zR5b zDldHvZqB@R=mTtTz<(@n4@K-^692T>Yudjrjeg&X^^850^Jdxn*g8iZqQxId%};)G zW&MMo#mOhuuh%)oHe zJB4}vt+`in{VQaPCeeV{X*#yS;!a%J?_)$3;fo%-aC%!S{u!tz!hgE%`e)(T!!qXU zy@$h557gaSRqLO@^n44qv$O2emXBHE`Z4mD#@mH*rT({4tc0BI6Zqj_OgJj21+}gzN{1$Je*lO06k1ekl?{5YA zFZwKA=j(S4*e?0<qUT?|VnN5e*&-UA^ z4?MjQ{fDzUNZ%zV{#mCjM4zu0%MlX)_^D-|f_oTmrn0SL&GZg4xir<}Rq0Ki913!S z@!t-&xF@o<0y+NURGqEgOJeoq!M@$2c=r!H+xM0qcMdjh{hONDQ%N~!xic}Zcxx}m zf0*jcMxR}J1O5#$OV;yl%S%e^Xp28U{FcZpyn{8iJqk+m$|~co$G$E4=9|v9`CX{y zTl$=Vv2z+nL5@D1^qbb=#F1Aicit1E!`s5=xaRrW!9Pw|A9Pn&<$d8jpHX^uKgD_R zw-!vnsM?aao`PK4Z0q_L0DalNrDu_q{(Z7MNQ-S3&l5R4#6Uq=VT;b9D9t{L?Y(%> zn$N2GR671mBAV;3wzt`2lX}~)<^6l}EaZJmZntPNJ*ev1YI$qQda(a`qNooO_joVD zfA80S(2*TmJ$ZxN-pkSkX=fwW2V#kO`Sz|$|Ea&Jwy19Op>!_AwpKav^eMI=*4}?0 z8TWp_f8+0Mj`-V2uZK2X-ka5Tu`BHDR+{8LPuKV6_B^-iHA~<1=3K;4d^4{+?%9~`kCx9n{Qic2``zNI=&fV(gHQjh z0vgtQr`4i&p|cnDYh|@)o6g4X9e6{WLj7lpb#-)MnQ`0+dUVxT*;)Rx zJn1EK^4w!eeK@1nM1T7X!;NO5ea8hLBWBU`|9)cyoGZzi{?yj&_~gk zHGGcLd*sgNL-+gd58$0-`KaJO@*^KSJ|Q(Z#mUsq4%&}?W;Q=H^VINZq0?KP5j-<- zdEl&s^IRuyn2b=bA47Fq`7;(LIJ93`mh=nComP=hS?fTXaNET8ZU;9S=;(HGJG))n zu5P!4p00e1{a-)vDAD=hpZF01u@3_KG+>|dWt@P1STgP>ARm;JKOl(vNp#XBZHz6X z`SZa#QoxZ90>}LXVt!+@iI3e@})a9V!!ISc71I1ORL{m-DUN6tGZKk z{8mLpfnziPX$wR)4)+pX&7?Dcj1`vI+b3~7DF>PuGNu==jmkF0)a^?R$oSpCbY z{#}sHFUe|KtDUT7THVKLmeoO4M_4VeI>zcas}ro&S)FEej@2fs$6Gzc>RDD-TD{cj z8mre^z18a7Rv)tZgw^M)zH0R?tM6O=)aut(f3*6WRXw%o_6b={wc5dISF63O?r$~6 z>QJkPSS_|%X0^uZ;Z`SGooRKx)nlxlWc75bE3B@vdWF?%tlnhx4y*TBebnkEt1nu8 z-Rf4W+pT_K^*gISTm92&Ku+npo!VH9SnX)FyVbp|_Om+B>Ts+1R!gi_S{-loD60)t zXIpKwdYsi|R+n2n-|8h+ud=$%>Md69vihLajaHwv`ij*zt!}gWiParef3UjS>OWRn z$=?g;c1p3@-f9=CJ+1C%HP`BJtA$p}tR8B$&gu-S3#=Yz^;D}XtX^z&jnx~iZm{~G z)hDgKXmyL#_pN?z^?R$kt-5ld@_ew`&T3byeXM3#9b$E))e@^!Ru8v2)#@Cpi>;n) zb-C3GtX^UDI;*!@z1QkvR-d)H+3HrSA6xy}>MpB)S#2eM`l#!fX0?;meXWj=Yqh>U z+Uikq>!Nv<)unQc*1W>%wQ}pC`F5+DH_%-FU==e zyKF`^Pbj%?tZPbdR7lVUt;yuUVh$YwZqaR z{(ipQ>KA?eyvu4oxe?Lv5475tivAM z)nlgk`82DKHu(7ktAQDQPPbYz%g={eJ%6^JS6h8^uAe`)+GT;C_qAHz=;ygsZ(QW( zd#rwYjGuqEI^Z}zkFff2}f`BSTV zo$crStxj3t=lNFGpXcZMtbQ*yxVnG-v^r>&pYyFAf3csJTYchEKfhu%bcLVWTP<7d z=fkY7TI1)nR=2M8^XFE(U+3q(RvWJO^Fph)-00^Atp2dx&wpDTa;u*Ut)6(hpU<}X z)CNCqw%Yn`KWA92xYy4|SiSguKVNJ0y$AjLrPUsf_&Lk!^vC?%Wc9Xi=)n`BU^A@WqpZU47)#@+&Jjv?i zU-|h4s~>*t=Wnd``OeR|R*&B4=OtF}{L#;kS^ZTyP}<(apZ$8!uYMh4_0-?|ywd9P z@ml;Z2%1Z+o-Q3d%@^z#W;@0AXvj{l_9Kjb?XG>7HeOSI<6moI27w|Zk= zKi^~ZajikedByTpt!*6VeXAcE|JL#kR(~<>%2yWX_(7{}w94{2Sng!CoALcD_p_R7 z{1B_9Rwr7WX0_4kQmf}$y~65^R`0R;gjQLvT~-f}hfLb8{#J)t9bq->h*vUxvekB0 zqgK0F?P+yCtNpANSuL?zX|=}c;a2OcHd$R_^<=B3T9wOz*PipNUT<~1)eTnfvHGyp z$E`kN^#!YPxO?;a-0F8$<*@X)9By9y%W5mFvQg44OYvTpZi81pO7LrY&1wGM^Xv9= zvKo(_(^NlMYSTi$&R|GB%iH8+>4#^XtjUdyPL_P!H%nob|B&f_{pV}m6jSvB8S*rI z+B}(=H(Wn?^1_D2{``C*e^wtK>lfC~l|O-tNB<_X^^f9hj?!c&OaIooLH<%DZmH82 z*3XfV@~XYJJt&YZlcNoM&yLul@}5OYC3Stlm!#`B%pa`0-!k>1+D4 zkNm2;|Euw`Wt=^i`zbS#*L1(?Pha_MEx#k>SAR~MPyB>F&nw`=Bs4$$zBTj+izc|lYC1`zpr*yIDIyjp1Pr7 zdbeWt!j$50&w?L&jZ5zpDt>tM+Q~g8O`iVA0x z-HADgy{1gRvvi9LIS2gl?uOC-{QCDlf#N$xZ`$qT_`|ow4c`(sygqLD#<=0@pY8o>@}d*q|9Ec#(Xll-Ha=(U2oLa^g6HfNofhKso3d^)bU65tk`vP zG8`MKBHonQ>ANMv1@5{#m=Q|Dt2}3B*S56pG74f?jCqoldQ)#8{{`# zelr)2Sy-Y~ezO;hT`gVmD(DqOE>M_yx^0W@-+E}gO3;rM)Y5_DHSRwRdvG&cxQzwvO(VhgWo& zarl^Lq|JwoerESK^A8&<|E`=^^33k-BcG9_E0f>tmN#mvoL;g{2|w09vwL&SPhQIg zE*tsFKiQ*y>{S)+HMXRGg-qed6zRE>8mA9u&m19JXIf^@{9m>=?LD?&bV13pySr|D zcK0`v+ykGI@#QyNen8EgFgTq9!y z290iCvZemX-RqoolagkvwpT{}SU*2|Y|5CI>Yv!1=svM~UH0p?1@@b9z}P2uJCT_) zTFKsXBI{@9zh8O(%3QL?YV>+O|~cKkV0#?QPdbKuucC%xXk;GrweoO9docXIw&+1**b^rHiu5#2{PZG+)N z`R1(U%Yxyc6HH#|6v?mLC=SKs{b!Dnz3=pxIkQ-7k@nBjf4`hrARakxfp^sTd*|bN z@g_&TN#Ant*n`I$QgVp*>d0OP%ao7gteW{=;-6cb%)o|6zubBLfn$e{8D28N#u#j4 zY?U#Fj`qhGGIq$Ap(R6YjDB%r^dJ507X!u)95b+FkoRi1=g1#>Rre{IJblWfqi57P zf4=#qw7CD++(}X+Sz{J>wcqGFz50XqZ%)0ww!r)MPVe6z>id*<$84{*W1jZfyG>ei z!xufq_88N%q^GqbNzB!C(Uz|N!g;*+n*5s0>o=V>ZB5oS?bdJF@7I?PKJ%6<25$ZJ zo8z;i&ux82_w8F3K2d!C?zhu(-+gY$>hD(^tzY(({m;FLV?RCrogXSzW|R#tPP^!s z$?dzWzj4ED+aLYC)w>7Jj*cAj!sOfU8&Xk}yEx^{S#OQqb>+$@4|{OH+5sIut9Q2b z`AO~}{OeDmJ6dk+lUH?>j+R~#<9-s{R;S8^GQkZmm1{*pLh!r}T0$rHkPE^u@=rop z$1)i|Au)KNTz3OE%GD*IqSGV~g}Qf^6b`w4bbEyUZ|;T<6d@;ax&~Jw_}B^}>TADL%E=ua7bF7&I+?fK9b(&iUJJ*4~aVyHx}#4m-~%lf_? zS}tS0624BhMqfAltTd~i8@@`$%5uX|+2Z{LO3Sj{@Rd?ly5a9+steq3iZo@F8$MOG z-9>Kr7TH`EyW!U)UE+rClFfFh8-7IQa+w=`OjiDKH#|XJyTT2BB2Bu|4R?{X+U151 zk@B+});EZLal<#s(tmZssWQQCH+-`+Y(hf#7umy)B!thCCVv?SA100XDiA(FZU=V+ z!s}$7UkAea-uE|w@R_n*z72#6WMh062rrhc@qHltgRH~OKv>_Z`XLa`lI4{qhWC+1 zlqH6TNUO^e!zan!uSg6Jm6=s0hIh&+;}XL+%JQlb!%s`8P7L>!<<%sH(`16$#IU|U zacE+=mF$7>iQ(O{pb3fL;o{}Q#PDr0v%?a@nX+FFPYh3x-FAc|ac4tfc&Rj^eK6cx zHeH8c_%dn4l3;kEY^7s^;iF_`#|6Wu3)~hApCr=09}Mp;8}fr-c%z8+VKAH^tFk>9 zepMRyQ7~L5Tj}Fqc)qk{b13|YjQLt9{D4gUdMK>l+4e>#{EO`JEurxH(xf*-;d0r< zZ-v4y34A*g{z%s7oly8WnS5&~tnWxXkQ9DVHr<0s;Y(y@4<&_flqEcz6rLyAu1yQy zCKg?j7M>=JzcwxWmNe2+!0ZZgm7)52HCJa0$~FOamnU3hQVn`gBPZ;;8; z_X$_);jmA5k*w|fXgF2cvLG5BE-hOa4Sy<&ZH$KBmob~7;p=5%EsBQc$!ac+hF_5- z91{)yA(JnOhOd<^cx*KMrc8cZH2kP+`QxMEgQT4&M8lWLI-D2{zbd|*6b;`clb;+7 zkC6?zG#Wlymar@uo-T74xjH;m7Mr&^{ISd|e|7k5*{p@D!}n)O=W2Dhi)@hM)nWbr z9Y?JWSIU;Cd@8&}UK{sRI8Vx?9pP$OLj8{LcxmqB9pMIXV#p*95aH;Il);nb6Wjc@}^EpKarpUo~stz>tly0OBJTLp;bR9TLHvbtq@V>O=OdVJx zTkV268Q3aoe4!3Rq_wMb;5%8fi*!IgI&iTLd@tMm*eNoQBn>-G2mXYu1Ujud%2cU3pl?d2>43f~nXUt!Wq(9;AXPSZTOF7p zTTH&SN!DE!+Fl15WR*MUfV4_}5}eli%Px?|RZi;zrSS%t{Ye@SuTA~$&!*1&zF## z7~DJ9Pn=50&vt_Q*nf`EU1E+C+}C0^iMdX2KZ|=w9N+}^x7bzUKqq*B#V!&DIl;ab zJ4+la&j~Gdk~qW(W?Aegai|mQZ!s!ynEV%l7BeK~NV9S*chD^D%C+2Hvovgg<#w8- zWdkj@)htaLWI3W)+BVp7x@KwI5X)(rrFBCsr)rkw4YQo0S=x7?|eFs|(YnJvMVmYK)+Bed2E6virJj+4N(!PAl^7*#>Txnl{W%&eJ zey+5y&~k$00n)xA%ks=5e}J^F*s|>Z)Wl%#K!xo8w7H^Bu#flOJEUDLhjnmNsGlBR zV#wHFg(&42QfiZ$A!QcLkaCM=NQFf+q|%}pGR~qIQf1K$skUf_)L1k_YAs^Op_VaZ zyk!iTU>QRuTE>vWEMv&wmNDcA%NTN`WehpWGKSPy#*j&tF{IuyhD^4MAyX`4$W+T1 z(qI`wrdh_2>6S5MhGh(yX&FOiS;ml~E&GO)1Qy8tPupM4Siv#AA^CDH56%v$IcmuK z-~!RdGh~5HYKAPdXofUeG((y!njwoUnjwoVnjyznG((nHG((QHXoehT5kro*j3Fmj z#*h;&W5`LCG2~>+7_!tdhAgv;A*WczkW(#V$Z3`_$@(p=IK=8hhnxlq1 z6ueh%k~~8mwn@#9M=Y8lk6JWC9*z^0Z|P zdB!q^JZl+4p0kW0&s)Zj7c67QiEn~<|%NX*5WeoYzGKTzQ8AEni#*m*aW5_R-G2~av z7_!?khWut3Lw>i6A%9rLkUuSB$X}K*%l=RMN3Hn4GbBAE9U|$~ zg;X6Uk{C>MgI(kz)K+^lLD#14E?I7STamj-mfP|Wc`wOwTOKBNl`OaAt;t;^%WZiZ za%ahMTb@MjBw23DlgS+=%WZiIIVxFh%Tvi2lC@ux2I!zbT9^)KuRxj@0kl&fZEOo@ zt3Vpr4j}){pVzr*4@g%a&Flb3Qy}fk0Hi9AhDHG?3Z$hS0m%Zihtmm=q(EBQ8PG<7 zw6qJLwE}5rS3p>Sv~({(NP%q6Zh%$_q@~>fK?Ty%OhBRnX=x9D{IQJJ)#(XH5TJdX zUI15tw6r%s1ZkHTOmG7uMUeCpwTlyQeTzO*i~6`B)k`hf&kfd#WS&L)Grd`K0NE_+ zOE!!8knJu;@Sl z77Yhr(Fgz*9R$Flg8^7{2mp&l0 zZ_z$(;0zHYy-*)2?Q0gDBTrR=W89GXr52UD!5ifPj%QH?)0;(=WV2`-*(|Cen?==R zv#5q_7S)o?qC?4M(Ri|1G=Ypo69HIs7yye72Vl_=04zEZfJH|Eu&54zMUwznR1d(S z$p9>x0>GlF04!<%V9_)H7EK3W(F_0<%>-c4EC3cA4Zxz=04$mVz@oVT-=b1C@RA6U zeuzAs3znHh`^q^eIL{5KUusdK8}#0?(JNXL)0;($$Y#-EvRQNt*(_Q@Hj9oWn?=Ww z&7$MUX3+^`v*<)J7M%pZqLTqwv=o3v%K%t(3IK~v1z^!>04zEkfJJ8ju;@$x7A*&0 z(OCd2IvapR=K!#11ptfA1z^#604zEmfJG|-SabmZi!KCU(JFv%(E>NnRxW1g*Xxb* zLbGU>T6B>cQoq!q%iQ1qdH=yX7hTTuX3-U7v*=2)S+tsL7F|U)i`J0MqN~Yf(OR-u zbPd@ox|WPZ*8#9-9RQ222Vl_+04%x@fJHX}uxLF1i*5#B(JcThx)p#$w*j!|b^sRL z0l=aS04%x_fJJu!u;^|87Tp8DqI&^YbRPhV?gwDe0|4KmOWeQ&5hVRiy)U}dEL!gM z#oUnkr4~Kv29K4uwmgd-V|ugbak5#ok!%({K{kt?B%4J~k7^4 zMIXDt$L0Mj&!SJ5-Yoi*Y!-b+Hj6$dn?+xc&7v>KX37D0KlRj0a)}C0E>13u;^z17X1RiqF(`6v>Sj$zX7o5cK{as0l=a^ z0a)}G0E_+xV9`GSEOHWJy?noq<^r%N0pMG--3@#yf~0>UDg{3>i}XKV4F(cI>X%v+ zN(ct`HjBbcZx*#Cn?-HNW>FH^EJ`MuMJZ&nD3xp$rIF2|bh23#A!AWn02Z|aU{QMj z7Igq%Q3e2uq5v%F2*9FF04(YZz@jbyEb0otqP+lE)D3_|-2qsX3BaNr04(YWz@lCN zEb0xwqCNo5MSBCVXdi%YQ7|E}zX*~(K;8fkwo34O`WMRQ3xfM5gw!v!sBc1W?7n7E zKc+W}vdCspf3jJWO*V^i$YxP4*(@4BHj4(5&7whMvuH3Gi-rKOXea=Sh5@kXKmZmE z2Vl_%02Untz@mczSab*gi$(&lC=Y-|`2Z{`0ANue0E>zMSX2zaqEP@W8V$gr5&#yB z0btQs02Y-3e2ex^2+S8j(%+QNtOO4*i<=x{O?9Ra|iBLP@+6ab6r09Z5$fJOBHESe0! zqA36@nhL<81^^aK17Oi~02a*vV9`tf7R>@+(a``bnhn6BIRGr03&5gz04$mhz@h~J z-=d0yz@Zq9tUr=vcB@bR5|% zI-YD6oj^8=P9&Q}Cy~vflgVb$QZg1T17Oi904zEcfJLVPu;_FE7M%gWqB8+lv>bp% zX92M2YycLW1Hhsc04zEefJNs4u;_dM7Oeze(FFi3x)6Xxs{mMZ5de!W24K-80Nvb)8-PXk0I=v@02bW`z@qyBSo8n@iyj1E(L(?%dKlnaba_G`Uj#|l zuP+N;VHS0j5Ap;bNeHQ5YSG4o;FKJ*=n1Abi=HH#MNg5ydLMvA9{{lELjV?S2ly5}mJnDjf~4OeAI1$n zZWiq&ch$j<5<=>iTJ%{$aQy(Y=yRqwi@qS6MPHK5qOZti(GId%^flQm`i5*4eM>fr zz9XAO-;=RuCjg6n0ASIN04(|mfJM6iSoAXhi+%xM(XRk3+6};>-vC(jI{=IR0ASId z04(|ofJJ`;u;?EE7C8aywqud|KZv^z=%~tvZTEZF*_rfA0yC6QLN5Xdy$c~E5D5vS z&_p67(t9r=3Wy>qMMMDs6%`b_h`pj>M{KC5*n2OapnlIY`@RtV@B5zfee0aFj%&Hd zeP#B{Wac-MN+6)93IRnf0Yxzc6nO++(I-{hR}7F)lKJUs?^7wd)Q(s;Xnk2l39k1; z2PsPAcqvL^OHndgic;88l**Q(5L=4U*iw|vmZGX`DXPXsQJ8?D2mwXa2`H*TKv7Ks zifR#1ltDmIZ32qw5KvT?fTDT?6lD@nRG)yN1_Tr}B%r7f0Y!}oC~87LQBwknnh{Xc zoPeSh1Yc2{>sIS%6n$;KL=^A(pXn!6G2;w3Xnk2lS+3WivlL}>ycD%zOHo_46t!bZ zQG2!&bznP|pW4+4tLB%r7#0Y$wCD9RzAs5b#c zxdasTA)qLafTDZ?iuw{z)Q^Co0s@N8BA}>00Y!xb6b&GtsEB}~VuG)zmFo^SKti9{ z@5Z*4qE@aM1KptYWfhgV-lDEjRL=2IG?*<#L)cO@lr2TW*itl{Ek$RurDz0Oiq2t6 z(MUFmDhMb#mw=*C1Qd-XplA#MMPmslswAN3JOYZw5l}RqfT9Tm6ipDY}p?MHjK9Xc-$t%Lyo2K|s;P1Qe|# zpy(0;iY_IfXcYlPml063nt-Cq2`IXPfTAl2C|W~6(OLqE))7#&o`9mO2q@Y>K+)9% z6m2A+=o$iwt|j=2=DF_Y21w|8`{UB{rD(WSw8;%xUslmp*9-QPqHP>6Mcdg@bUj;& zZeUB%jch5}!Iq+%*iv*eTZ(RBOVLg?igpoDbSnWxw-HdZn}DL*2`IXQfTBAID7uS) zqPqzwx`%+GdkHAIkAR{*1Qgv*K+#?TiXI@K=s^OC9wMOVVFHRCA)x3{0*W3Z_=>i; zZc76sbe;Wf>~&Ifj`=RE_qZFhzO16BU2i~+6z$`9DSC!2MbEOO=sC6&?Pp8T^K2=4 zfh|QZvZd%HwiLb0M$sz-6unA7(E$RAUL&CBAOS_M6HxR90Yz^TQ1li7MQ;;ObcleW zcL*qYmw=-82q-#CK+*dI6n#KI(T4;S9U-9TBLa#(CZOmOg0JXF*PUsAgj(1il6^{w zV$Dydd7rvL>&q(o()HHoO3_ywFGXLorRW>B6n)E}F1qmpMBlwCwcijgJkkBss^F?1s(H#37kocIO^<@<$ z$9V7LNl^;NOHnFYib8BDN@Gh=I$MgWvZbgRTZ+PLDT=VAs5%=(H3%rGNkCC80*W#S zD5_0BQ5^z`>Jm^?kAR{~0*dMrP}G2cqJ{(%H6oy>F#$zQ2q32iZdGucau@jufqv41bMbxhFuvWnWqc=h^8Q9F*8qV{Yl z>cEzwj%+FF#FnDYY$@u(mZGj~DeA_SqV8-I^&p_=Oah8}5>V8OfTA1%ih2`JluJNS z9|DT<2q?-Ypr|haMg0gUDj=ZfECP!96Hru0K+ymKii!v*Dkh+4AOS^#2q-Ec_=>V) z+&%_KXqo*?zl{_fH$N%smBs|EFRN%sj8}P<6bqTy^QI-4y;BiK@O4qJ*w zvZbhkEk)P?*QuLiwbX`o)`m&0ykMVvglA;?p zUW#sHOVJLt6y3y@qMO-LbPHRGcCw{t7h8&MWlPa*Y!vM#py+l2itZqw=uQHP?joS* zZUTz#A)x490*dYw3mRQ2M8#7kbt6x2q=1(fTBkTD0-BDqQ?j*dYpiw zCkQBdlHe=a7UM>WjiS%&k2h|YqKN%=$Wt*v>&q&7Hpc5TNQ$20cq!V?mZIm`QuG2_ zie6+((MxP8dYLUnudt=)RkjozV58_Y0*Ve2Q1m(hMQ;#L^dF>8+$Zq2WtuL#ngXhH$ zm7dJ|BTOF&T{ z0*dkoD9R_Gs4oFU{Rk*3AfV_h0*d+*P*g}j(EtL9iU=qwCZK2_0Y!rdC@LYKsFZ-B zG6IUq3BICsp4-|03GK2!cimo!X4o$t4fcZ8msK>}^NNQ{(b*g?MI+c!bPijJMzW=- zf-ObovZZJgTZ%@rrDzOWipH{0R7pV5c?1-VBcNzJ0YwuCD4Iw>(If(jCKFIJg@B@| z1QbmpplCV)MKcH}nn^&>ECPyV6HqjVfTFns6wM=`Xg&c&3kWD$NbnU6_1xJ8NT|F0 zx$9w4)Y|-NPj8VIw7#sO3p{Vb2q{|1@ltdlTZ%4XOVKj66fI{<(F(Q{UCfrEm24@x zge^svvQe~(fTGI?C|XTG(d7gbT|q$6l>`*6A)sh20Y&QwC|XZI(NzQ#Z6KiNY66Nj z5>Rvv0Y%pmP_&7FqRj*pZ6ToOIs%He5>T{_;43=cb00E5LbdJBT`!TMgI3XYFKB&P zMLRt2y^&IM6UR%@&1@;Ug)K!p*;2HNEk(DorRX-c6zyh9(d}$0x`U0PI|(Sdi-4lL z2`IXUfTDW|D7ue;qCEr@-A_Q#UIL09AfV_$0*W3Ypy*)&iXI`L=urZS9wVUWaRQ2- zAfV_;0*am@py+7=iuMtFMK^e^Q(+W!ws3BgqVLnpc*YA_Usloco>zaA6urRlQuHEQ zie6$%(aUTpdW9`Tud=1+09%S)V@uINwiLb2M$sDt6un76(OU!*y-h&TAp(ltA)x48 z0*c-vpy)6GMeh?(^Z@}y9}-Y>gn*)t2q^lPfTB+bDEgFuqR$8@`ka8GF9<05l7OPG z2)?4{JU8C}2@R`l;Ov*8K){Tzy`c4F6@Bk{ zTZ(>TOVRIaDLTrQqGN0n{Xsy{p9B;gC!pvA0Y!fiQ1mweMgI^`fP~(+U#|X6 zik`C{U8lwdtuL#nYOHsAr4&`;cqt0Ar6|IdqUvlZs==0`nrtbm#g?KBwiMN7OHmy* zis}+jRF8n7OahAP6HwHEfTD&36g48Cs4)RWO$aDzNOIb>Vm^>dKa)Zfq&)&X%GcY$-aEEk!-qQq+qrMLBFK>di(`E&)Y-2q?-UpeUb! zqP_$a^&_CDfPkX22q@}LKv5w9MFR*ZDk7k$n1G^z1QZP-ps0j^qEZ5i$_OYbC!lCB z0YyUyC>l!e6?KetYm7IFUa{}QI!V#*_Dhh%VuRL~Rdi0Q*JYvGW#QIOJal8msNC8targ=DO$$yQnZ{cMJw1+bTM0sR{oEk&!@D7u`0qALg}x{`pRH3Sr`C7@^>0Y&QxD7uP(q74KTT}?pIMgoeiA)x45 z0*W>fP_&tVqAdgzT}MFCRsxE)5m2<9fTHUOD7t~*D_R=s?l3??2kcMpUnoV3?Gw|D zu|ez0D!L`sduFN>?c{hV+QpWlTiH@{8(WHYv!&>EwiMmLmZCe^Qgjzvitc8k=pF)! z?j@k;J_3sN5KweK0Y!TWD0+Z^q6Y~mdWe9chY2Wpgn*()2`GAufTG6K+$sqU(rpm?$-uLXoF|q+$=>w`@=^2V}sV0RrFGWIW z0Y!%iD0-iOq7Mit`jCL4BLozEL_pEU1QdNjK+&fJ6n#cO(dPsdeL+Ccmjo1jML^Nl z1QdNkK+(4ZU(pM(Zngmuy25@R?L{eC?wavkY|#3$ihhdq2F;S9pE+KNeql?|uWTv$ zjV(pLv!&=LTZ)dcrRWc~6#dDTqT_57ogkp-F9M4GCZOma0*aiVK5a))fPkVZ1QfXh z6qz51@V{e^B9DNgSOSWI1Qf*)P!vxD~{>Gp!H=HMS|YOIZ{-eo@^=V#g?KRwiNYdOHnRciu$mn zD36Vzd;*I45>V8SfT98diq0aSs6PQkg#;80AfTv-fTCgoiUtx;G>Cwr5(0`!2`DNf zps1XHqQL|d4I!XtC;>&o2q+p(K+)L*Us0E!TV=jc^u7I_epe~lX%&qK2CXlv=-i;! zaG?~9;&>?<&6c7uY$+PcmZD0w6rIPGqH$~~8qb!Z32Z5v$VSm50*WRRP&9>rqNxNF zO(URaIsrv92q>CKK+!A$ie?i~G>3qqxdar=BcNzL0YwW4C|XEB(INth786i(J^@8b z2q?OMfTE=YU(v{*+s^vimoD{XafO7R})aQk$|FW z2q?OifTB$V6m2G;XbS;F*AY;(m4Kpc1Qcy2py+x6if$mF=tcsHb`Vf>6Tw%sEa+Zg zfP`}Fmxz{2(Xli$ZVm>mFRSR*pm*mIDY}j0rD!)>if(61(H(3lx|1zMcd@1DZnhNN z!kL_pEQ1Qb0&K+&TF6g@^j(c=UZJwZUx zlLQn!ML^Nh1QhKfpy(L_ik>B)=s5z4_7hO_JOM>75PU^DgYFv!NNA7!>HS?&^nv|) z(Tl;L^<@>k8uWf!Dn$o4UW#60OVL5L6ur)tqBq!5^d?)1-eOD9+iWR1#FnCW*eH6J zfTH&ZC^}3)(fb4xeLz6bhXfQIA)x3Z0*XE+py(35n*A{tw7#sOUxQw^ zWm5DT$4k-gY$-a*mZD>9Df)vgMSrrT=r~)7POzouFSZo@%|_8b1Qa=O`n(lI0RoDu z5K!b2P!vNzkw-vLECEG90*c}YD2gYbD1m^YL;{ME2q;P>peTiaqErHkLIf105m1y) zKv7i!imDNOML!4Ka}AKt-}aOHU!>?Vt0){7w7#sOnsMHRE2O9v$4gNLTZ(G4rKk>D zit4hZs2*F2GTBm8pDjfV*izJxjiN>b6g4KGs0jf@O$jJ!MnF+>0*YD?P;>?XMJ)*^ zYDGX%YXXY02q?-Xpr{Q2MQsTvYDYj(djg6&5Kz>SfTB(W6m=$`s0+bYR6WkU*#HS8 zH8OB&#QC4;XWG9>)HN<>eOX0k#(B@Jl%k#-FGaoBQk27%qTXyN%4JJYAGQ?bv85=V zEk%9VQq+%)q5=Yn&LW_wKLJIB1QZP*ps0v|qGAGy1`<#-h=8IJ0*XorC@LeMsGNYJ z!2}cyA)sg|0Y$?IC>l;c(b)tPjUb@t90H0)5`0D7uGyNV?6tbftE@*vO zMPuT;1m77$Rhkbt5^1QabMpy+%8ik1*ibO8ZH zO9?2tkbt6#2q;=c@D+`UbK4pqp^{n#&S)vR+bUWf7qq^tqD$hu($!LQDaT9EDz+3| z#+IVhY$>{&Ek#$brRYkw6s=)P(OR|?tz)BTJpn~m5m2;&fTF7jDB4Is(KQ4VT}wdG zCIX5!6Hv5;fTHUNDB4Ou(KZ5#wi8fvJpn~G5Kwd@0Yy6qD7uM&qMHdQx`lwEodjRe z#c}R@10*!0u7R^sitevr#;&-a^<@>^9_L+qg%sVv@ltdrTZ-;tOVQnIDY}O(Mfb9$ z=sva-?O{vN{cI`P%SO=y1Qb0;K+!`46g^Bp(IW&DJxV~)V+0gEPC(HU1Qb0yZIvD4DxJHUz=Xfc4gDpjGvZd%PwiLb1mZC#!DSC%3Menku=smU+ z9cH8GeFBO;AfV_&0*a0hQ1lT2MIRGT^a%k)pAt~?839F~6HxR80YzUDQ1lf6MPCz8 z^bG+;-x5&t9RWq(6HxR60YyI&Q1lZ4ML!dKMF-;Cn6*Yx5Bt;muSwBk_D9x!i3?g^ zR?*Qoukm^*I>zx*^aopt{$xwhakdnlU`x?oY$^JiEk*yZrO1ib=j~DyV56uC0YxqW zMKJ^vc?1;25>ON*peT-jqId#|5(p?tB%mmXfTCmqic$zDN+qBuL_kp*0Y&Kq6jddl zs2Tx9VFHRG1Qb;#_=oZqFWzhb1Otuu&XG>87wiGpFOHm`X6g6f`Q4=7lAfTut0Y#k%DC$f=Q5OP=x)M;-jew%=1Yc3D zcz2Bf5{lSgx1SO3f2QBXeg~vSe9-!`igMz;yEjTvZ;qFuT(%VTVM|dSTZ;18Qq-3% zMg7=PRKS*^v)EG9pN*nI0*VF@P*g-fQ858U0|_V^L_kpq0Y#+*6qONBR8BzAU;>JU z5KuIffTCdp6b&b!=xhRtMi5YR4gp0Y2`H){py*rzibfH9MLpx)w+xWb?e?8mFDV*s zUgwRD4_aSV(RuOS(QBn>9LG!1c(xQxU`x?NwiHcbOVMPu6is1E(Nwk+O=C;ZbT*1+ z5KuIefTCFh6wM}}Xbu5Ia|tM#M?leh0*V$8P_&SMqD2H0EheDod;*G=5Kwdh0Yys* zD7uhlXdFRSRXc(2D6 zDO%0(Qgk_6imqTw(Uoi|TEmv2wQMO`$Cje?Y$>{mEkzsHD7u<}qKyO;T|+?8wFDGx zBA{q90YzH~D7ub-qOAlJZ6ly)I{`)46Hs&m0Yx_wP_%=9qMHaPx|x8YTL>uHNkGvq z0*Y=Wpy)P&ujtZvceDW#8f5?S&?+hV#J)${9Urv5tfIT(y=7aa=x&aeqI=jn9wngYF#?JnC!pvF0*am_py(+A zik>E*XdeMZ&k#`bECEH&5m2;mcLWrDPe9QR1Qh*9K+#VG6#Yy<(JurP{YpU5Zv+$aQ21say{c`mi zQncTGko0?e(E759{*3ohZOVK}UDRL6@nY$DP*iux5Ek!O{ zielI(@(3u3C7>usKv5h4Mezg_B@j@QNI+2%0Y%9K6r~VQluAHRh=8Ir0*cZJD5^?8 zQ8faJ!UPmW2q>yfKv4|>ifR&2REyv%Iu`G?H$Xx++AlQzAw_Za*U)4n1g$Tts9u6s zev=esa=aAPXG>87wiGpFOHm`X6g6f`Q4_WlHDyatGqw~pXQQYE0YzsJP}GuuqE-YH zwI-k_i-4kR0*cxYP}G)yqILunwI`sc0|7-H2`K7BKv8D`in+^jK3j_VvZbgW zTZ#(UQgjwuiu$vqsE{p11K3hj#70pu0Yw7|C>lgSQ3(M>r34g}5l~c4K+#|ViiQwS zG?aj%VFVNnC!pwT0*XcuP;?FfMI#9)svw}~Tmp(l5l}RmfTA%36pbbLih3uwPZ%Jf zKkYlQTq)|2WJYB|(E759CM0+t?UJI294|$a*itl^Ek#q?Fy`2-X#AfRX=0Y!@lC|XQF(fI@vEg_)j0s@Mb5>Rv@ z0Yw)PP_&GIqU8h>tstQ2Vgia*5>Rvr0Y#S*d`06D+}K-gfqJP*@rwiGpIOHm896rI7AqLyqFwIZOXH33Cg z1QcZxP}GKiqP7GSwIiUYJpn}>2q@}EKv5?GiaHZe)P;bet^^cyBcP}|0YyCsC_0mX zqMig4^&+4shk&Bq1Yc2RqC3_A2`$MqaOx-epXq;Mf0fBW0*XorC@LeMsGNYJ!2}cyA)sg| z0Y$?IC>l;c(b)tPjUb@t90H0)5>Qk@K+(Ab6pbRFXfy#uV+bf3OF&U20Y&E#P&AI< zE6PiBZ#6(dZS8ks^QGvJePSA)7_`2uqRENgiw{cC6pojoscb2l#+IV#Y$=+-mZF(# zDVoKWqS@W~ z(LwV%@AAZ;^<@>UP4vUYoq(e22`IXOfT9}-DB3|l(M<#t-Aq8yEd&(pB%o*)0Y$eG zP;?ssMY{Fvaz^<@>km*`#hgcKd-cqw|H zEkz%&rRYPp6dhqp(MN14`j{<6pRlFqQ??X+#zxWS1QdNiK+%^36n#ZN(bohNeM3Oe zw*(Y@M?lf{1Qh*1K+%r`6#Ya%(a!`F{X#&|uLKnRMnKW;1QZ=5py(I@MSl=b^d|vD z#|gfocM{#F43N+^`{n9)rKqs387C5h)|XY}Bzd1aB}IWGeI_qORoGJGvZW}7Ekzz% zielMP6l6Jm^?kAR{~g0JZBL^tkfqo}t1deJ{p zbiyjCpA@vdtfIzAUh`+9s0qhQQB$@QHDgOrbG8(%Y$l&a(GUWPh7wRT zjDVuy1QeZ3K+y;Siq0XRXe0qe6$BKWOF+>m0*XcxP&9^sqOk-NRT5Bi9sxz;2q+p) zK+yyOiY5|#Mg5Z8s|=9P2>T_X0x7!0{@vI~NkQw&Dw>w$?Rj2`rgOX$&0tH>Otuuw zVoT9%wiL}_OVM1m6wPBx(R{WPEnuT)Apu2;2q;=iK+*XG6fGg3=mG+YmJ(2OApu1f z5m2;@fTHCD6s;hj=wbqjRuWKj2?0fy5>T{?fTGI?C|XTG(d7gbT|q$6l>}eWlqC0E z10*!h{@nFcDXM3`c(f)dXnk2lS0#DJUzDN^94|#zv!!SwTZ*n>OVPD#DcZ!AqRnh6 z+QOEi>)2AXm5rip1Qcy2py+x6if$mF=tcsHb`Vf>69Gjx6Hs&u0Yy6rDB49p(X9j& z-9|vsZUTyKC!pvK0*dY=py)0FitZ+$=pF)!?j@k;K7y}kU6Pyml2J6-{@nF?De7y# zHM=J%Xnk2l4<>mzuSn5D94|!=v!&<}wiG?emZHblQuH`mik@Ig(UWW`dWtPYPqR_9 zkAR|Q2q=1%fTHIJDB4dz(enfpy+A(E759K1lLb z9+09BIbMp6u%+lDwiJELmZDGCQuHZXiaujY(dTR_`hqP*U$Rm36#+$G6HxRG0Y%>u zQ1l%EMc)%p^aBA!KN3*%69Gj(6HxRE0Y$$OQ1lxCMZXhJbd-RiV+0iaK|s-;1QZ=7 zpy&hvMSl@c^f$p*bU4Y~ZGeR0?N=S&m!hs!&G;uNXnk2lZnF2X`FeJG?`+45Nk08E zeUB|gv1};{vZW}FEk*HcDN0~VQ6gK4lGsv|%tlcP0Y#|<6om*VN+X~soq(dM1Qb;x zpeRg0QG|e^>I4+kAfTuw0Y$Y4D9Rw9s5SvbbqFY`OF&UQ0*W#TD5_6DQ3C>s8WMa( zfn@h*10>Yn{-|}8WdC!tc>6D*H%bm#Ush4GWUuO*Qq-K|^<30~Ek$RrrKlxaidwOy zs5M)Pve;6T&6c7zY$Pm0*XcxP&9^sqOk-NRT5Bi9sxz; z2q+p)K+yyOiY5|JG>L$s$pjQlA^3{=C%a1wkkBambJvAZ^sxOPX=-xN`m%~5A)x3|0*Y1Fs6>UuRK6_7!uHkqox|S_Po7hsc znJq_^?k1q<9s-K)C7|d&0*dw!P;@^5MSBUpq7BJz z!eOK6FZ*0{wG`c&V#Wi>LF>yZdL-F9;{z#rl;fr7F}4&v&X%Gl*i!T)TZ*1yOVQJ8 zDcZ-DqG#Ar^eh`i&k<0xpMaw02`GAjfT9-(D0+#2qL&FMdWC?ZR|zOOKtR!J1QZ=4 zpy+i1iryfg=uHBO-XfsrZ32o85m59F0Y&c;Q1l)FMTZH#qKA^*fd)wE;_3#@!%}pm z{dUOv$wBMOD*7ndn{h;nKIV8S`h+b-pR%RsGqx0c&X%Gt*i!T*TZ+D7OVQVCDf)(u zqHhT(`i_92?+GaSfqNthso~M21sa<{qe>lQuIxIGpeKntuL!6 zHpScfu@nV4UW($_QWVdYq6D@SC95s6#Dzs@z(E759&Peh8`c#Tqa=a9^VoOnL zwiIQtr6`*%MQzwp)Rrwp?buS(o-IWk*eL2qKv5?GiaHZe)P;bet^^cyBcP}|0YyCs zC_0mXqMig4^&+4shk&Bq1Qg{GP}GNjqC5hM@(C#FOF&US0*VRl#ZQ6&LI=Mhje zj)0=^1QbmmplBiiMUx09noK~^6atE-5>PaafTHOHUr|wtJKg{Z1?`U%6-!Y)`yG%O zDM9PYDw>nxUHX+2&EQIGW;~n{w7#sO$5XuU_fqr($4k+ZY$G2M8#7jew$q z1QfkaK+zin6un76(OU!*y-h&TAp(ltA)x480*c-vpy)6GMeh?(^Z@}y9};{;kEXa? z4Uo_m_UEo2lcM3S8Anor)|XZEX^MCDk5cp*$4k-YY$^JJEk$3lrRXcR6n)K>qHowz z^etP8zGF+#_iPmXKtR!t1Qh*5K+(?x6#YU#(XRv){YF61?*tSbC7|dS0Y!fhQ1mAO zMaKy!Izd3uUj!8WO+e8<1Qa=``m`NI0RoDu5K!b2P!vP(6@8rIE;T?x8|=?re>JU&=mw=*r1QcZwP*k6Qq6P#MH6);@ z5dlSw2`FkpKv7cyikcBn)STce3Z}Zx8X%!b_6v=1ss3mB9qdocwnzK+#zQ6!j;dsE~l7 z0R$8k5qw20Q{ANBjH1K#n;xyCsK9=7U7Q-UzO16sRIk-hDJtW5DJo}6(O|X|4Pi^s zP_`5eV@uI+wiKPsmZA}CDLRLZqLBm?RS-~gE&)ZO2q+p&K+zZiipCO9R7pV5c?1-V zBcNzJ0YwuCD4Iw>(If(jCKFIJg@B@|1QbmpplCV)MKcH}nn^&>EP}6SP^w#EfQ0hw z52lq!(aToR?9`z3Wfjd&^=ADcMGH7yiWah^Xc1eA7PF=3e6|!VVN1~kY$;mGmZA&U zQgjg;Mau{%T24UG3Id8QCZK2~0Y#S(P;@B)MXLxXx{QFL)dUn>PC(HW1QcCKK+zfk ziq;ZPw2pwH^#l}MML^L80*bCCplBljMb{8~MRQZ#YYdQ3OZ!f2o)nF@Up%@tHE4ZV zMc1Wz4<47ItsE~!+t^aHoh?Pzv!&<;wiMmSmZBYODY}U*MK`mh=oU7Lb`nsui-4kA z2`IXafTG<56x~ih(H#U7-AO>vT?7=}O+e8-1Qgv%K+$~!6zw6P=zao<_7YI^00Bi0 z5>WII0YwiJQ1l1^MUN7EMVnLI4-Ak{TQj{aQgnm;AnCExp!H=HJ(cSH^OqDo&GAyS zk1a*du%+l(wiG?bmZJS^DSDnQMK7?W=tZ^^y~IY*%LEj?LO{{01QZ=0py)LMiVhM` z^g01WZxB%QCILln5m59t0Y!%hD0+v0qIU@>dXIpj!vqw)Pe9QJ1QdNpK+zEbiasKs z=wpJf=!sOf(cebVcKdy_C#5LXevtG@YS8+!ioQto@*H~x=I5@z} zPXdaL6Hs)5fTF($DEga#qJIb|GXI*?W^*US1W*(ppr{G~MJ@qFF$5HO1Qf**P!uHi ziatwqCmJB31@_;K{alLH+jnnqp`i6;6(xnd%c@9GGRI3%3R{X&*-{i@OHmqIiqhFq zRFy47)!0%LW=m0ojiTxV6xAT0s3rkLwFoH6AfTu=0Y!BPD5^_9Q9S~RG6^WEPe4%v z0*V?EP}GQkqQ(RiH6fs=DFH>z2qkpG$f zV*9PxR-vHvWfipvd9TGtQCp6eqIPU4YR{IU4s0pv$d;l`Y$@u@mZC0fDeB6WqHb&y zbtj;x2LVNA5>V8WfTCUm6y*?5)SG~!Tmp*v5KxpyKv6ycMSTe<>PJ9P0Rcs45m3~h zfTBVIiUtr+R75~gF#$yb2`Cyw@D*i++}{n5&@}sfv}`FVwBL;_2?eb$t7ve@s~(i1 zAsjD7L)lU^j4egO*-~^iTZ%@orRW^C6pds{Q3YFy&Sj%$6aht}2`CyvK+#wNiYf^x zI*)*&aRd~NC!lBo0YwuDD4Ik-(PRROrVvmxm4KpY1QbmtplAjGMKcK~nngg-Yyyhr z5KuIi;43N%x!nzrP@esX*>WkmC*6#Bp`i6;6)g&R=fq3VVvd)h^Vw3gge^rEu%&1z zTZ%4ZOVLGaDO$#sqUCHUTERxq#RL?sB%tUL0*WprplB5VMVAp!w3>jT%LypDf`Fnc z2`E}aK+#$Piq;WOw4Q*Xs|YCCKtR#e1Qcx~py(O`imoM~XcGZNn+d+61tIq$10-}u zrh&6iiYD4G9&HH)tuL!+d&s*nQHrkTcqzJpEk!r7rDz9Rif&>{(amfrx`i!8JK0jS zi!DXBvQcy!0Y$qBD7u}1qB{sEx|4vSy9g+{n}DKw2q?OjfTH^dDB43n(ftGz?Iob- z0RoC1B%tUa0*W3cpy&|-iXJ7P=rIC{9w(sa34*U^YslSifP{+exAC`0QD^%XLY@o- ztuL$SnUMEYvJ^eb@ly00TZ;CxrRaIK6urQfq8Hgx^b%W&US>6#YX$k&~uR+ffuCpr{G~MJ@qFF$5HO1Qf**P!uGfD2{-l zcmj$N2)?2(LvEP?5~^l@djBga%C&zVEio-00Y!xb z6b&GtsEB}~VgiZ=5>PaVfT9utib@G6DkJ!c+NQZj43JQ+{p7x#6n$qEm8S)*FRN%+ znir@pMZ-B>iq2+B(FnE_ox_%*k!&fdU`x@tY$+PWmZH&YDH_8@(O3eCDhVh$kAR|a z1Qd-YplAXCMH2}qnnXa+WCDt&5KuIgfTC#x6ip|fXa)gAGYKe~ML^MP0*dAkP&Ai- zqIm=q%_pE}0l`-^B+YGNfQ0tikFJMG(YpF(EKCbpUslnQG_P+>DY}5;rD!QziY{bJ z(M4=2TE>>5PC(HW1QcCKK+zfk ziq;ZPw2pwH^#l}MML^L80*bCCplBljMb{8ebS(izn+Pb{OhC~V0*bC9plB<>SF||I zoos-Fez(8B=zJ;q#*S@iLF>yZx-reWJVT0haJ&@V#FnC)*-~^1TZ(qFrDzvhif&~~ z(QRxg+Rc`t+u10(gMgwt2`IXYfTFtzD7uG$qI(G_x{rXOJp>fpPe9RL0*W3Wpy)vY ziXI}M=wSki9wDIUQ38q{BcSMU0*am>py){gik>2%=xKtl==wDG9s?xQBFVtHL5k+v zFJ$ja3tC@R(f%~=^*U1YJjYAX3v4NRku60pv8Cu`wiLa>mZDeLQgnbVMX#}?=pY+K zuM<%81_4EH5>WIO0Yz^UP;`iZqIU==dY6Er_XsFDOhD251QdNhK+%T;6dfU;=pzD( zJ|>{(69S4pC7|dt0*XE-py&$%ioPWHik?k#j~O5#FT=ojPKxH(zt#9vTG0BkioQ$p zYGz8&_Z%-pKd`0fN46CG#FnC;*;4ciTZ(>VOVMv^Df*o)MMv2vIz~Xz9|RQrNkGwY z0*X!$Q1ll8MSl}e^bY|=PP#sAM^S))qACOwxdar&5K!b1P!vl*QILS5I0A~|2`EY+ zpeT`mq9g)}k_o<|Z_?Z|4Uo`^Gy~^bDJrtx4oOK5T3=RCdb(H9K#HnzycAVqOHr6D zMG>|XRcA|44Ym~3WJ^&kwiIQsrKmO=MRf=$s!KpoJpzg{2`H*hKv4q%iW(A7)QEth z#sm~KA)u%!0Y%LSC~8hXQ40c!&LE(uB>_dP2qUn;J<`XO5SmE^I04%9f&TY$@u_mZBbPDLRua zMLpS4)Qc@eIcya5CZH&nfTBJG6y*_6lutlWUjmBy5l~b>K+#zQ6!j;dsE~l70R$8k z5l~c2K+!+~iUtu-R6;;eDFH=g1QeAMP&Al;q9FudQHON*1p_3s$$smsqZI9qe!`X> zw7#sO5$WDHO{C}?j+dg5Y$>W>OVPP(DH_F=qS0(A8pD>Nv1}=-WJ}R`Y!r_ zJ^@7w2q;=eK+z%siWU=mMZ?qGP*bC*!2V#`*;2IM{;kII(}UKRRdivx*QU7?UBvNH zw2Uo9%h^)2f-OZCv!!SyTZ%4WOVOolDO$yrqRZGQT1`OFgP;?CeMb{Egw26SC%>)!}A)x3w0*ba0P_&JJqU{6} zT~F{8U6Ae$Hb6o<%=DH@(GL47v2I8YT3=2zr;67w{`!^yC)~<>)a`_e&99@43C}R! zC5a2KH}43O!h6gIRiW_P=IN|jI3waXHNv9|%G%*u%nwjzhQBi(Wi<-7Gk^KES$IKx z$7vaU+<@aOGK! zGdp}+q2tUC|5W5Si^H7;InL7X`K6AtJp6RI<6IJsAL=-(!^OiLXH9s+2*bhFfr$N?%SQqc`$Kb21S0mQp7sSI_QzKC2O{?8 z4qggG>^F`N1S0l3e{TdL_FFfH0ulSQ_rrmR{o?77K*WCa>(fBQe);0dK*WCj`E4L# zKY{o$5V0Qt{u+qbcj3nZ5&Il`BH$#XrI`oT4*wxneN0VrXSPeM8Z>vR`LDZY=9Z_j z15S-Y4eV=LH#M&@|C)UCzZ!p6wXKhBXPVO1{9hw2dJe;FTW7Yh zX5Vf8uemkDv<@j(nwR6uBih^)POXk9=Fg7N=G5w8M<Bx@<3~yeC97xyE_?km23JrHtnIWAHQ{> zlW~!HHYdNJBxR73VQ(;dq5U}d>en_LTHs`CQm^3Tx4pBho|AF2@?3Jwmyew7)Vasx zSIxO(e5}`R@LwO(tA8VNRIItR?S<_0YarXnuwRC^=}|wq36ASzTxH^66Myn!Y}(6* z-}!xh?Z6-}>Gl0*kE$IgiB0=y--QQED)o}QzbBvXWIUo{nr20BhS;<<$3NbAfjK5N z?Soa9KX`uhptXB1xp|>EC^qfHmpdO=;$*Zi_kz8o5gc{r#b3R@AbQlHPfn~fFPV$_ z=CV82nB&bwt(WML0l;~(TDRo%6(dGwgiA9?6fbN=R-1Fx@p#lL!uw)QS_ zGCnuQd}WS#h6~!b=8I>|nVL80=(mfqqsQE~=iu}9a$?htZa)6td?zE$0JaAm<$|{S zuzFJTn6~fkH|JjBCG9=-w)yAJ%vF19-IMv|?a>h}%u!K01G?p>MvwTZcugdFDKGAS ze4qc;WdE}##>wbs4zX{|IUExE?wOPAA!)Zid9*xw$mWAvS1gKN%2o45S93D1)}^fF zkm9_ybIl>KX_sGd>%Hd8%@rGc$Nin6Z_CD|yACdP>fWPcqStDabGUKz^xMBUvU5rF z^iK_cuwC@@FMj#M@&%4l?|^v^YyXdJ>?YKEG~IFR|FLgXiLDpPG|%tm|JW*SY`rb! z@oN8%jd5e0Kw6-2O4UR+B_pN0dRib<-EpckauO5IG|6$?h~uVoP3)G~C9%Lfg~aGJ z_N%ZR99v>z0&dEgiHYXb{>cI+2Ai3qYMXcTanTpdQ&W8O1@p*G&>4FE878Khi?ZjF zR5g&8`0qI+Cp&H&mz$WFoS2l@*_>ZW_0vw3YEE^^wF_zLywh}+X4)&2uCt83_TRIt zsQw&(VGWXir~a|FEa1 z;;b$E&y)DuybmxZEVX|ej9%%%_K&){jM8oPC3`smXD}CMFTC{RTT`WqegEK}*+TPT z6(@U}{d2MTKh}xMoaxlwW?#O<{O>u%cG~mwuT}QRv#D*)!JNYUXI`oQ>}gK@@6>%q zf_a!YubV@v1dgX9I|1{bIjwyYTDQ)cIV$VCS<|y-%^Z_8vtrhm%8KbTr_HV$GrMwZ z)|i6>YL@Y-M7rsne!bwyGR8dP1u<*{$2PvafD!UVYlDvL;L&GkMO~%B(4) z#*CjZ_5b&)F>ArBQ*ViJa^TxGb>x2ye;O>o*BJK{99z;%xM$NZ9Xfj zbo!{7lk(?Gttc~Z%eaA)=gg`o$>}(t19y{oWB)%q_x~pd=8l?OY3~ci5u;8W&ucx# zDytYdneJ z?Fwf$@Y3s=3;o}IEA3lXzkyfP9+Yk0jFUIbfB!~#>E_L<@72%ts^$fi+k?bsUjm(Ye&dW5nb4T;SeCvXn`9J<_?4@V?*Vl3-VypT0#>sW`23|%Tld`;8CM0uzR<(C)s@GgdqqDVnbz5_?aKmhOVe4$KMGJcdE$Vs6 zZhWSfVcvLqKC!jDTK3JiFV-|KF7RKhVP0GqeNh+01^$nJW|^y4)vIOBKDI~n+S)7G z#9YZxrk56d)6MOWomJOs*~qJ#VUmBt{QGD9=na*I>+1fS)KYI!blP)jYfqNtHOOgc z&fxU(sUPsd=HzZQFU|fD8}jU9#BJbLbAi!mu2S?=r|eeIleh5ff!OH<(d{-rO15U%|2E9&u1Dv z;IuPMYv|Rh6TM!XS@h5PUcGv@+RLcw)wM5kaampqb8*!&%@e4b+ z?SoPmoa$e2Bi)?Qndybv8sTn|xvu6BSl?@w?bWgm$ohJm=-$)=vYC#JPWy0b8-3rB z+|jG;Kj_TUthwOi4rWImdD`vGjz0YSUE4mE|BqhuAA-%yvqfEVsNSIe{z{n#XB~3` z*n6sF1FxRNuG9awqO0^WAD`xz4y?#4DXAzZ8k|#D(5E7&q;L6vyrMFPR}9E2EzRkh zS5a16Tv1qD)YmD=>s!$#C%50pQ{GE^?RgC`kggGUB zDvFBB%!y0$O3L#3oP5n$1I?M17nPO|99V2$Q8BP!XkKAOesRfwoHG9s%~_p(^4^8T zx&15p{Vd8Gr3%{BDTsl7Q3w}rj#c_lfer(APxw*jSnD|(mb=bQ5{Ef}76@{s@XmK6-J zw`TM-_Ll6Oed-l0D5@yug1hL-waGv2B)KKS29_0@H@UE|VqkGWQCXheg`L|P-lLxlRJ>|%Pl0g-{jj=ujrT&F+Tl!~d&n$YkRTLH! z^*?#54JpVksK^-@y_UJfMMZhJR!dY~etUa^MPKYA5~bz2xkl;9qaiz}Jg+>jBH!Fn zCto!%r=*~4*vV;856CGRrn~OnvxweprNyPuYtYB2K6wQ?L@%GWLZ{1bV;&zBrN#OA z6{nrJO_$S7otslsQC5;uR63xbEPBo*c{zQCMcSn_JPQcYz-Axu-oWqfaw^3Uc~Z6qlC`EHA4VTwGXY9!n?Bf=7mZg0W9U z_G#>tM{1wE!3E|so!;f8{w;1EC#OC)`41}#+uY#xfo^Y`Qw}c~Y98Jd#e?%o@(YWH z{O5(16!ks%6l#p+3^;j$f`R6VO?US|^VD+cb8GZXDm5xjK4G>!d4u&n<;Jmh*1s3+ z+dt*i=1ws;Nk!h!+`PO#r(9*-Am-V&EXO=s^v@esk)KmwAMxCuI)(iV&|J0R@)Glc zdA#Kp7Ucf>9v~{#KCzv=>DshC`CvB>d;cyskHxWbrc7CI^1P!DjlAN5(;q@yvUy4# zP+Vf~4*Q(xpGDi~gJtrxspB%u6Iish=j_{<7dY13hNZ>-zRR-j0#3e8&%q^mg?Z8E zX?tVko$koLr|sKp?#zOG|3>kzLB~@rCHfp>?;QJV7k$sBYk8U*o&YLxa&yZ|a&q-_ zcJli4Gw<_;qPcfYeF&MGil^Sf;!-_`JDz5L|N9h>n_FDb&pb_?Jb>F~Kye@c+MAC6PQEfXuduMZFsH;I?^{r6 zJll6$ydkLKG4Ef;Y;$<@O+4)hyu7q`^j&vFX+QIEihoM;bjB0gDHk~)&pcJ>0~jvJ zo?jdDjOibj7j-me>ZxzOJ%xEsaPo@xY1>Ed9!v6y`WUUJJQtt5gL9)F2+54O6{n7? ztf-ticEYHs751@o^2`bf3-kKs6zU;o-sAT%kNJP!F4u@@OVlo=U%ld?DPygQKRdab_AJ9X{bymjy%Uib~aeu4Arb*jC+5_Rhwe>;l5 z7PhoIq)Y1pufo`EmwBbzd_3blH@K@hx5#Q?uL*e%Uj8eDTh)U1IM&a&$9eP%YzVir z=R*GD&swy~Y~MaJZ!O&YW7}EWE%uC!-&Og~>WqxIj#eGIrDrv2lCU!J>a>E*hdVhfEyWq?T2|bF7AwVrlTC(E}z98#B7b1UnFH zbAojPZTlrJ$8TbTLjK~9eemYuw%y|oWQz_t-RvbO?zZq&cHTRbZK!27%Wjw5D}PJ5 zmc8t{Md}oK@yvgwyQfPYxqP|y?qaV2U2P-Ny-Vkvfk!RAH3T{&%+x7&4jfUWM#<2}+H)hP(j8J^k{@1z`dP6R> z&D-8Csaa0Xe=U*K&R*~B9n`%Z#qXQoHMOsMlXj0*My=Xf@4OdVyTkJ?CjVY?+h=`s zR|QMhyJGx=J)A*duT%w|F7d}Tf1m7(O>Mo_6@F`|YnL>ruRD@HX#Du#GHn;_KUOAq zVYX+kTdQEBGsAW@SU2uP~bq_nrkk!^+9fMm`=t%;0w;hsqe^VCR8UDZQcD2lI znNxV5Fkeq|+kbK7y4t5Fd6%EJ@$m0wgY6>Qoi@Tf8S>5^-0E%}GP|2~x67ONodS1i zW;ffRwoR>qJJ4?Ph`TP3)5>;0f^C(&Z^XH}?a`bL?!_Sf2AuJK{jQ!kwnrvF`8#5T z_phA6Jm{=QmyX$ewa@Gx5BBRa^DfO^<+)(DX`}0~tyZ1Nu#Nh>^($}>bnKkdI@|X2 z?4jsj?`3urfvb!YaVz4OWZPzEFT>EcuYInUe@r98wwv7*jziww0~hCB z#|na@hfT}O=5{#djQ89)3AYZdOn%bG;2_*bW0X)b5kK+rVaU!KXmnb5{J0 zV;$VOo$)rE*~J|i%R8!Kf$&D#&lY!*LAmiLVUcWdVsUH@}?IsUrH4zpX6U|%bH zbm9GW+j_B^!|K_NqwSq#XJyCVcRFU;+fMvO*qcXi!k)N=&K?{>%xY~rv@P1j&tm(t zc^8-WL~7ZiZ#O%JW%sKtP?u*%u(&hr6-6iAE}2$1|B`Gky^DLn%m?ev@}JwOJkEuV z$`#sV&f5fMr!&|`;$G0bTlgunJa?*ruerCJkxB0IsYDV$7JINOWdZ2 z9U$o2DlZ%I|AL>LT8XWRp}Do|)o*P-I@5C4=-iQACg~t{aNsxpz3X4E zMj7ldWVi#TTxr2u)-t=DZO|1wHjuwb)1^z6KC&rvcVQf}cCb@h8e@V@`}oj%YN1tP z1@d0a^X}IIuWxQQku!1?!Sf;Stu}r)7Cguq_wrxw)WM5&-cd0wH~v8kFAkLM(eKS zw@sM>+c9D;Qh8|<)gh4vwUwu<6gEPM_Szy1QR`g#fkn^Ad3GVS@# zwvdSOQC~)I05*Ox?s#YXM6hknHM>{(!f#@EPuzmfwO~!`BI3{cy!#`oU1s}^1-1YJ zc1UO{O2FVOBtcEJynSl!@e$L}_~OXK%n;hl&4i?Gi>*}!9+ z*_rFot&4q(rJd=29m{lwG0*tiB7c|4-gokDo_%1h&%N9Vxjmh{-7&7wZ7{^&`~GX! z*J*Lw*qw8i(o(l7!w!VyT@klFI22mo^Z#I1BYt-j+<=YmEcUR^bls=gIr^BERSJ&5 zyU+2?e4B7@f9_LoUe@>&l_i_C%k0qBp0X|M@Yxw#SMH{qdG`E=qFs)CQfDt9c4RfP zLxIC|?(rym=q1?02{!l(y}`zBWBwu6;Nt~WEPvas(Eg0Oc%$FVZWin2E+*I?iJ#)d zIXJ4>w=a9sTyTNc`qrJ>+JhB5`LgYS&p%w(Bhz-+dGS1BNq3ycy}btaPyT^XcgQjC zta-<#-5y}8&TiNHjJvncKBw~(m+$tCxDZw?D>KXP>6U%tn+G9x_52Kj+g;LTT-K<8 z!AnnYwAI}e1$UDIIR!Rc+zwf=fIGhE&K|rzaOLqQewY9Cp{DLc)-Z3QD%ibomzLoU zLvms9H<%8Y`9GcD9>z28kB)uwK0>}iOhu?wR#xNmYVMGJ=J-+REk^YpG;pAOLf4g_C66EF=V!z({NKm? zLuvNY!vENp{RYGIB57xZ>bf5v)|dOa`DR6`+>kssdZRxt=_c>y#9Jb_CfpIuDpD)* zYdEDym1e0q@qa_1%tp3QuKV%yP}qK_Gvqa_(Y~hbmUIXu75CdGM^d7(#FF7s;nI(23ztu*Cg|_=NO}6^XB1eh~@TuaXq_vS0o!klgPwl+rJ41iu>*v)fyvz&VQ9>85Ao z4rk=vXJmf1JlG_wGBH%eo}&M27wJDf&dh&@atHnLlY74^m}=Ygx^+n@6$7D`HE>SaMOORXT9bH_Ve*BZ?VVQ&9B|GU!h5~ zhuO^wG@H9=-(RS_TGM_hDwJRkse9fe*q!UFxM?>bKJB+OLkR}1qMP>6R#Weu6YhNV zHJfNQ)9k3}ej~@7Z-A!zTj+-c9>O+W0J?>HgxE>nmuUuX(X%hGqlJCYo8A*_t_; z-88S#%+(yCIZAVa=2XpDnsYU8)x1-4iRJ^ED>PSWuF-s6^A*iEG~d$vK=WhGFEtNn z9@adjd0Nw6c;oj|lDUlEkD4Vl&(*A?d7)-4%?6s6YqrpAr`bibmu9Z!P|Y!#lQm~( z-k^D_=0eSTH6PY|Omns7^O_qpH*3DD`H|+QnqO%i)cjHNgytWb3HCg7_fN8BG0oDN zDlX)J71b+3C*&a6*a4AUZPoFvx%mA{d1So zR~_e+BA`kvNYr}>KJCe3#=w`=a!+^hMm z<`K>n)hlh z*L+fQo#v~WTQxt_{8V$l=3&iWH2>7}>rXHiXMl zHJ`QLkahWW&C~V^t1f%xf_Zs`V7Aq~p<vC&+JT{$4N0zHPX;<(f7OW_!&W8wYuj=C;d% z{F!F#iXd0e?3o$lL7ER{1^G$MZ(0QTnC3;TgWN!KY?~m@(0rj?kT+}oX&aPoJ(F{S z*{oAAb2M-266D32AJ_($JO3A&C3^;!qIdOWB=V-oc8{qEtzNHzO6XdfrTV5aJE}FN^4f4I3JLU!XE6sCm z3G(@xeQpc#2+c?C2=X(UhZh9-SIt_Bg4{%N^5P(0ueo7Kkl)cvxG%^>HCrzYayQL8 z9t`sRn!6qj@_x;-D}r2Av){@fkJ5bfu^>OEd1O_Pf77h}RFJRGoU%H|b2VRE8|3#i z6Q2umam_Z*2f2slf)|7QfaWK*q3<4_1DfY;2=axR{a*|67|q8w2Kjl-pEd>g56!x7 z202r6+FL=Mr@8T+AiuAfv@OUbG~0a;UfY}(mZ}5$p2_I{58leG-v)6>lO%C!T&DHjYklgoQ(L7;0axRC91hcX2 zNW0uhbGH4BB$sd3+-iT{#^s%wY4%r>TrQ*8*>(h7?yGr^{T(HjS8DFHKd9vL51Lid zgPfr`yi$;_(Og?4$ggUivOl`ymXA~o=4BTKGh1`H{Vg;1{WY2|yXl2O?ro9Zt zFaIme1Dc05?PVwaefPJ$-1??zx<51J@;RFJ^oZwbnsqee$6M@t@%zv2JbMV@=d%%? zwwn~6Unc~!q|0{ao})fgbHdb76Lb69oH#z1LpfzXHa;;_)BT)wsAm5O6GAoZC(CQP zvgZFhdKf>;K=(sF_IbzPF}8I4bZ-Ct;|EO+E+A;^Z>SWEx#Qh0QRpgybNss*>HY$W zF45L8RMY)kjY0N%O9ifV@c7(OcBahE?Q7;voH%}1|49?=V*metooi>cyEgBraNRQ& zwYxF?Rnh)+=Zgff&~bKGx$n8Js`g*h{`>zrUoAV&nb%wJ@7%b@(S237|B~&$ruLuv zYB(YsT5HpGSKMC~iT~%WuZ#W1I@rn3STpjgJ=gf+lxW4$`7AQFBo==>1=gVjq4z(&!aMC^h3f_*fGs5=g3WMu)J=Z(iPP2@i z3{7bi4yC&j`r>=jEf>7JwKMGxV_N5KhwU2XUEU%)%`$c}bdO!0J0D+sZ@v`;FK=Uk z%d=g}yvti@r&-2b#^ZK*&$<^eeeu0zmJ43qcDp=xzq<7+YX5P2pRvYCzSabr?t0zVoAzJ9_4~BI?JZ&7 zWBop{(`I?Bjo@ooIMkTaHn}c0d9Ju`UuNf9U}b4L?Ouc2<+=OaT_?{CI~m$GJRBPC zPUwrvGm?eQ_nocZLC$28^X2`0o?$h|T#}xip3$II{f4z_H>};rPS>iHQQ+VD_3Oq{ zy+-xzjOqPSX0>S7GWhdR!3BryXg`a$Xj)sfmoVXw@=jiO@oD;L7 zp{fZ(SGV12=YKkT>**u4o^E6R?t99beG8syz4i2Y8~^$B?|*F0-gX=( z=H#5{HEw0wrFP!L;&#qjJ9O!lhc3z9bUKvrk@A3{i`u+lneQ(fI=`)bzc{y`>8ZUL z2Zv@I-#6aYIJfnwePcJDK2j{_#H?`6iO{7vCz^K8I^J(u>r?%vTAyzJh1~aV%Fa5T z+tZ!0|JHtWdgQZN$FJ)XoF4eBO?OV~d%M&9+-dvoVf$}^a{Awu?3BB#^pHE{E+>6L zo2=t2db?BO+w`pJrtiL&KHL7?mu~l2!sod;C%ScZ-S9R^$7Z**Q?rv!t~uN0KKpN@ z-Phv^-q(}U-F@e`?ANwmo80VNyEjAQT;u+0dc6PGK5hE6ZEN>>V%YB6^sT42)Z%`t zJgi0hej6~%-FqwI{~n0{%RSlpc;(6!hr9bSH~#Ok_`mz(|F*HmU|+HDv8I{flera3 z^h+IjPx#MWIVU#uuxqVvk9^bC$Df~2z0HTYZ=6oF|F(zTuiGG!b-WyzI_gZZ;+GJ$cZhbJ<-L4EvwJo{R<|`poIo9s$ z+%2cKXB>#z89S$V#iqx*j!&$-f5;YdJYdK!S-Bv-Or+)ct+&{1cFRXvRxWV5^}f*S zp<-t@J*#Yyboa!uXX)(FO`(R_7d7j8=U>NfEc@uaH(tE>OM5LzoW1YXP{U0-L&Y}Q zd^i%GeQZk65gYe>bZzb>j~p!hV&%2=L~Q!vyrcG#5}n;5Z9(YX_0_JN{zAjIUivmX zx80x?e|Ybvubg)Nw_Vm;ICNLB4VPZ({sigV)k9u!e_M2;UGBd5p@whl45hCuuzo8F zoL*Mo^g{(sKah7ip|ah|@PHxic2;Zo>UXE-+cUG2PMtWX#F!JSrY~x<$UP@b#=Zr= z^X&mwmrVD-HaT&{*5!*&S*0;d!~K&$XK_&Ju8jtFy3Av5-Ymr z{+X9GsqN%8le4cWbXiXOgfe!&mHDWE{p%WKmKpv zzwf`aKlC5kTl`G+vEMNaj#2T?3FRA?H0R7nzhNw&a%h# zNI!Sq%siOcwpp8I*0|Kv9_0=8{QV;F&s|rvPdRi&+sgm>_>_x3KIQ)B<5RnBoi=r{ z>*n33=T>!>?jE69_Bb5bcuAXD*|qW>pPGjnpUhe5{;=(BL%sXmU#u0D)oB5)0xkq$1C(~@#sT6+Vtx3YLAEB7?D}? z^qP@Zm;7mI#XFKh$&3137qbQS*>m=_CF}0~VSMLT8@IeSchT``HK$!x>C?~lHG1jT z%Je$VueTUkp{Z;&ga{)sa7l9A}S-yTUw z^cUJbV&oHhYmQVek!fd-%t*I?YL)D2r@i_1PtrJBA3xD;A||#i;{Il{ztL@*_?2u+ zB$CUM7v(xAL>+D`U&);b0EbpIh>rlZz*P3*Hg&Vq{n?i5nGl_8SF|A^ zTFutwyGZmcv+#W+y3jW34@aVF?J|FeM2nfbBa!GfyI+2cM0ePo^pkzh?v0-#(OXT; z(MU96*KjNn9c0(nE-{*G_fh-AXaig84vEp3_UPv%Mw{D(bxe#_wM*%g7|pcn>zo+v zYokk|{XJa!Yw3y6qP9S{#AqKg+C4Ga#2(uoiP72ytY>2M4byOCV)SXduwIGLn)bL{ zl^E@54_oiVXmzu*HZeNUR-&XAea>!CDKEOiR$_`5ZEyF|R4=;NE^L|?b$?<1OE3DG zUFIGyTHEf(yl`m>$$BR_iF7T@7V zZNDqD(~q9AhkTbG-D9itu^;`;?uk$Q=r${N+X8lrKJ}ySqq)!g=u@`3>r%+X7! z(dBkwFQ-P2*fqS88ok!oK3p_f))Xx(8a-(%zr1L4xUJHPqS12pa6D2pTHY>mWzpy< zJIkX*qvI^yR3dt{J(@R{h;FdOi&c&OXdC>+t44>}tsPrB`navjxYE%}ZOz7)j!v+v zolrXZi=A^~>F6_dXH6;{ebgSR$#xdIhHFYk7n|5ArK9d|IZrJe9b;Ojm5%;u5An67 zqu1GbPA?tZY`0-X>1ZEY!I`C_-`nD|N=I+7J92jE=&L%%#y! z?82HYjaIRBX}&c2r`@eBmPXxYsx6mB?Fee9)zWBhyC*tsj+U`&=(IU{qn)MS;po@) z49Gnk9bl{5|8R7WnHX?5`iR|zfrq1WZIuQcj^@~H7<@Q7*{*NM;pBt%y|Kl^q2!3w%%w>_?N-HDBM<{RCK?`>V?xf4b0%y;&+6BFzfFLWo|pO0VU zPSmj*c$Yizo!#!m?nH09im3za#C>+xO>-ww?Q-0{R`PLs48!h3Z9|aYPPDLVcR$RR z+}*As(VaMDccbS{%rO)8r>;ZE9o_4&J5k4)s5`OBt}EG{c+nn+6nCP!U2>{BvD?m* z=1%0=eQkf(H{*oPPT1|UTVW^MPlP17 z6YK4ExpO5CH*Mkg3A@7++=z@*#l zp*}0o^+giB3%n*~tZ1`ZA+M_buWl7AW`w+IisdcV4tWMF-vwpFXAT-;?_xBAM(T(*^Kpj^~tTf2tJMO?PkYovUZ%eH=vmD4QO zw)MMIIn`xbzsr5L!QI~D~u2A+}w)JbOoaC~tU#7C>vaMe;uNgtS+bkPeCxlA|ag9Tg>{lcI!lR+Nw~iW1UQQ9`;YBBZ-A zLV748q^B}Mu2e=yFJ**WrHqi?$_Tky86ka?5zlg$pp1}#$_N>x zjF7>~2pOV`kfF*58K#Vo;mQaZp&SUwj?A&gzxWn=1@qbjLZ;elyEoEza-5K{-W=l- z7cx$ZO2~Lc37McMArloPWRjwUOjeYTYZN79ilT%}Rg{oviU_$@86ne^5i&y=Av2W` zGD{gDvy~AtM;Rg4DI?^1WrWdJ67s5|guJFG zA+IY+$VNp8c|%b`HYrNTWm%LUt-6WS25RK2}D^C&~!ft&EUQl@aopGD1FA4uq_a z9J0s1cv0Jk^E@#;`%cJD;EZb&z zGWlG~wppG+E^FB~%Tvi^EZb&z8u=W{wpo4_xwK{5EH6Sn+p^oQDN13#bQRyRDMnG! z6}F1SDN4A))-gsAbA_#B35w#bu(d2nQOp&#nx!a;y294;Y>FbTuoW#$ah5A=P0yi7 zv%>A+l%YsQSJmJ_U*zP@t$G1&SI`pr|ngiY}!<(Pb1UYC?gc%PCNF1qF(lQlKc40!7UzP?SZ1 zqUIDRYC(abmJ}#zMS-H$6e!B32ozNfNA5Ntu~~Km$g3trOYC@#*Cy;cUrtenu=k?D ziYv-tc`52hmZDB%De6p?qAp}9>PnWPZe%IyPL`q`WGU)NM$wfNDC$LlqN^xS)SCiD zS5u&<4+V<)QlO|G1&VShP}H9SMFS{MG>`&CgD6lmm;yyZC{Q$%0!70pP&AwZMI$Is zG?D^EqbN``nj%otE*$yNfW)4%qjg?;DcWS4INq4B?|eB$6T;qKb}TZkXd=r?(Im1I zO(sjxHDoE8LYAVbWGR|PmZEFPQZ$_`MKj1Knn{78SrjOmO@X306ezlm0!7zTpy&n) z6wReT(Tx-+nn!`6ng%l`S zL=h+&7mif2H?vq>x8Xcqitey?GViXi?|eB$_k_JH+aZrDx|ijp=svO(-A|UHrDQ33 zfGkB1lBMV&vJ^c`mZD{3DOyfO(FzI_Jwkz^l@us?lmbPMQK0B?3KXrPK+zKvD0-3t zMNd(n=xGWRt)@WH8VVGxr9ja$6exO@0!7bJplBThik_!H(F+tPdXWM}>nQ?7cZVZG z4M^-ew_UVEib}`##lpVxQNbYzh>Wra;j-6eub~fugb$C_0w{MdwkVs2l}~%2S}I0tJfFDNt0A0!5W5 zP*j-$MO7$JbUp>IMHf(@s47LE$V-ScHXyM&_JO#Ulo0IcZ?m5_@Tw*F&X-eEJ;A%G zniSPwc`2$%mZD3@QdEm9MHyr%s!f)nI%FxTOO~Q~WGSjoMo|L_6g8wkQ6mZzHKst( zr4%T-i~>bXC{T1c1&XeqKv7c)6lGGNs2K%{vM5m0oB~BHC{War0!6JTP}G_NMcEW6 zYD0mdwiGC8M-eExC?PW2fW-FO&z^V}OVMgOAnmnJ@SQKGs8fQs>>?@Z%<@vyg)Bu~ z$x_sfEJfYPQq+SiMLo$d(KNCYT}zgt z>0~LIL6)MKWGR|OmZI5Y6wRSP(RCCkx}E|>H&CExE(MBiq(IR;3KZQ$fufr!P;?6g zif*Mq(QOncx}5?=cTk{cJ_U*vP@w2e3KT7*K+z%!6x~IEqQw*_x|Ksz zzk1?LlA;#wg=tBG?|eB$_a}HYE|H?8EH6b5kfrEBvJ^c;mZFErQnZXLMa#)jw1O-} zkC3HkB^gDJQlRKD3KTs~fudCuD0+edMNd+o=qU;mJxzh4)f6aNLxG~T6exOz0!7bK zpy)XY6s@B`(eo52dVvB(FH)drJq3zhqCnBh6exOyB2aX1LZq_+iJfgfnc>|hMb+#F zdAtn?zVqc2ZA|bcWJu8)EH6cy$WpYKEJa($QuHQSinfxa=q<7oy-k*)cgRxoE*VAd zQJ`oW1&ZFMK+y*jDEg2BMcXM*^brM$c2J;bCk2XjQK0B!3KV@pfuh|MDEgEFMW0ci z=yM7beL;buFDX#8hXO@=DNytk1&a1j1d3iuh}>g9Vwc-tYVUO^>S0^e-u?vN`ErWB zP4Hf-BSi;UUWyKprRY1d6n#&YqQhh<`hhG(N61q2BUy@mB1_TFWE35xK+!P@6dk8P z(JvGzIzfS=lN2aAMS-GUDNuBp0!6=3py+oB6#YSgqCY86^cMw+{-!|DKNKhmMYP+F zqA&%D5-3m0~DEJZ!YQq+?yMOTugs25p^t|CiOZ?Y6! zO_riQWEAzKKv6#m6y;K&s6PdY22h}AAO(sBQJ`or1&W4HplB!siiT03XgCFmMo^$= zBn65_QJ`ov1&YQ{plB=wipEi(XgmdqCQzVgB1NF6b0o6XfW#KsFD-dpr07z22y#-y zcfOpWsS)p^%cN);%S+L2Y@trTH=(~uwB1?+CXL%_)OqQY_$WnBKEJZ((rRXQJ z6#Yz=qN8LfI!2bF<75>5LV=RDpH`R5(SDXQ=q5{1&Yq6 zK+y#hD5^?ae^N)g?<&J+c(lCreQSvJ^EWOHm`T6g4JG(WPW5x{QpXCKM>T zoB~BxP@t$O1&T5$P}Gb9MOhRmYEFTo78EFINr9qP6ewyU$1&TUSpr{iCiaJvSifScBx*Cw!QTKD#8B#RVg)WJ{^W_xvNc1MPk)oa~ zFGW|9rKlHKimoC{QE##oT}_svK4dBCOO~R3WGTueqo_XxiUv@iXdnfO22r4BFa?T+ zP@rfi1&W4IplCP+ibhbNXe0%SMp2+>GzE&rP@rfm1&YQ|plCb=iY8E?Xd(rQCQ+bh zG6jmRp$HUpON`uSKw=NN4eIVvw9YA-lIS~MPSNy4@0E5^G=t@(XeL>TW|5_6Hd%`1 zkfrE4vJ_oUmZBTTQZ$z=MK_XBG>-yBH&LMIW(pMDLV==NDNuA91&VH`K+zo(D4I`! zq6HKvx|0G$3n@^vhyq1-QJ`os1&Z#bK+zHk6x~CCqI)S&bRPwZ?x#S}Qi?#)w8Y3h z0}}hqqIazn^>T+GA4v3_FQ;f(q8HAQqU9_vMJvcs^axpsR+6RYQL+?0MwX(-$x^h6 zEJaU{rRYgAik_lC(bE(tT1|nXH54dXOM#+iC{Xk)1&W@dK+!r16g^LYq8BJo^dbd{ z)>EM9B?=V1Oo5_TC{VP40!6P#NL#m%rpy!5`E{(Df%JN zySB}>sUvJ@RBOVKZ6DLO%xqLXA4ouWX|uM{XcO@X4{ zC{Xk}1&aQlK+&HRDEf;6MSoME=pPCc*{@~aZ+CEF7)4LV==Gia^o#iIHawNNj*RTzy!IzIJ>1X`b(VIYq@hZ)Z0tD$ep! z6eCMf39=NGBuh~#vJ{<7mZH*RDLRKNMPVtgHLMw4z?Hr{BXJ$jP25m!bw_DQZZTqDEvX zYD|`*OUY7n8Ci;&kfrEyvJ_oGMp07=6lGGNs2K%{vM5m0oB~BHC{War0!6JTP}G_N zMcEW6YD0mdwiGC8M}eaD6e#LIfubA=6m_IPQ6~x%b*4a37YY=0r9e?Pia=2vFLJp7 zi8XXTcU@PCX1Ie#-96v=a*BF+Uf*6)bQQ}>QE##oT}_svK4dBCOO~R3WGTueOHqHa z6b&Ft(Lgea22r4BFa?T+P@rfi1&W4IplCP+ibhbNXe0%SMp2+>GzE&rP@rfm1&YQ| zplCb=iY8E?Xd(rQCQ+bhG6jmRp+M0T3KUJHK+!acKv7RGa)SYhHFQ6BeWet=?f!bz zwVv;MIYqNPZ)I;On$7Z3G>0rj*O8^@da@MVK$fDpWGT9lEJgFkQgjnpif$&O=oShT z-AaL?+bB?UI|YjFpg_@l3KT7%K+&BPC|XE?qD2%ax{Cruiz!faHwB88P@w1@3KZQ- zfuj2;P;@^9ik4EK=m828JxGC~hbRI?GrY*V1|(M7{oM6TDH>Va!o!~Ld^tsrc-{|v zq-Z6}OVOibDSC`7MURuEXcbwCo*+xnlVmA+iY!G>lci`i8AWR-P_&i;MbA*6=vfLB zJx76}brdLio&rTLP@w2V3KXrUK+#JSD0-O!MXykxXafa`UZp_MYZNGYodQK0DNytV z1&TINplCA%indS$ik5qkVtq}~4)^l2LW*v3pMbpS`OcS9^p59c!G zS&H5#OVI~pDf*BsMcc_z^buK#c95lLCmBV%C{Xk<1&ThQK+$dr6n#p8qR%K$^f?8J zzMw$SmlP=4LxG~b6e#+N0!8~MP_&-{MPE~(=l}(ZzM(+Tw-hKkNP(h56e#+R0!80b z1d87BBHay0Y^yua__h>`ErU%Bzdn6lA@9Xl_5(}S+W$JOO~SZ$Wl~} zjH2=sD5^k#qI3!rRir>sB?=T(ra(~@3KX4Bfuaj2P*jxyMb#)!bRh+bE}}ru#S|#2 zPJyBt6ey}mfuc(&P*jToMHv(*s!f5SIuwDT;z^OO4M=QKy1|Jh1$+A2+&fy`B;WaR ziW(+)k)cx5h~=fIFs|WGQMwmZHnaQgj7bikgz8D3dHj&B!RqqCin|3KX@V zKv7Ey6t$v2QELhmWmBN24F!tYQlO|E1&Z2Jpr``{igGAW)R6*3ohVS$nF2*!C{Wau z0!7^@P}H3QMLj4`)RQ7mR6i+F&49!{aBpG_r0B3a1bJnW?|eB$S0{Pd!=C z6x~FYqMON5bPHLEZY4|6ZDbVPPJyC3C{Q$?0!0fbP;@5+iWX9!Xb}a9?xH}^VhR-9 zO@X2%6ezlf0!8;ypy)md6x~mOqNNlldVm5&4^p7$Aqo^dOo5_h6ewCw5h$9S6j^6L zVx=k@oHnKq4JOzqgpg_@!6ewCxfuffvQ1mhdie8~W(FO_>y-I8<5zYp22xkiY|9Q zZ1i@L?|eB$+mgI<$4SxqEH6bLkfrEDvJ`D6OVLMUDcV7nqMc+Z+C`S4kI7Q>2^mGZ zDNyt&1&ThSK+)$EDEfi|MPE{&Xb%O7_EMneD+(0tqd?Jq3KV@!fuaKxDEfv1Mc-1O z=pY4(4pE@!I|>wiPl2Mt6e#+E0!2qC0!8m8MVcCr*nRGEwD+XwhKPk9lYHmPDLR(q zO@X3+ zC{PsgwcC!OFa?SdC{PrkKv5zEiaZJwB~hTrr$AAZ0!7IbC`zF~Q7Q$B(kM`L76pom zP@t$N1&WGMpr|-Spy=nM$c+Xh_OAOJ?WhzTb-&^m^L^*bDLUKt9-AaZrCDBz&LK-t z8L||WB}>t{WGOn2EJfwWQdFKSMHR?WlukxbMG6#EqCin)3KUhLK+*XWD7t_GMO7(K zRE+{f7gC_;A_^2;Oo5{66ey}efufoeD7u6KMYSkUltF=_+7u|NLxG~Y6ey}kfui~p zfufRrWSaqr&2xu{O8LQ_erxxR*1-NBr{>Eky43f6yhe&HV|giRLYAV-$x?I$S&EvH zr6`juMa{@kltq@J=42^qK}Jza3KX@XKv8Q76lGJOs0{^*+ESpX9R-ToQ=q5=1&VSg zP}GqEMV%;6)R_WBT_{l0l>$ZGC{Wa$0!2M2P}GwGMORXws22r_uA&GOHS!~|DW+(K zdo5}#MPE5Zy?x*La*F!-UY%)Dl*{r`)SoOx1ISV|kSs-m$Wkl$FqHz=`8c%_u2^1)rNP(hB6eyZZfud_DP&9=C zMN=tIG>rm9*HWNpIt7YmP@rfg1&U@-plCKlps0@@>1jY>W!(p`eWmF8bPIEQ-}!Qi z=K9{$=~8qf%S+KbvJ~A!mZF=fuf}pD0+YbMGsP-=phOeJxqb3 zWfUk{PJyBo6exOx0!1q+0!7#Rkp~S(Y>GQXbb}NvbjPkA^?m2dDSE>9UY{vNPqMre zJw=wHr^!;Znk+?Y$WpYHEJe?drRZ6*6g@|lqIF~xJx_t67bsBlA_a=pQ=sT23KYFe zfudI^P_%&pMXyqz=rsxyy-tCmjT9()g91gHC{VPS0!3RWQ1m7Rindaq=q(Bqy-k6l zcPLQwE=8c|aX<2n0g3(W{(jLaDcb9f7rp2E&X-g4q3?Nfq-Z30aDElcnfWvJ`zrM$zXKDEfi|MPE{&Xb%O7_EMneD+(0tqd?Jq3KV@! zfuaKxDEfv1Mc-1O=pY4(4pE@!I|>wiPl2Mt6e#+E0!2qCQ1l}OihiO%(a#itqWAsC zMFu3ct%Sk(K#Hz)Kgxg9_nj}N=!EaJyW83S=otCreR9vJ_P!OHpMqimFhc z=zIzkT|j}NsuU=yMuDOWDNu9~1&S`FKv8uH6xEV=3KZ3$ zKv7)^6xE|ZQGE&&HK0IILkbi%q6id~jz(TEAhDKJ49+>xU{AlM`%R+8QQ!G;iY||O zyXQ&K6)Z1BP03P}NtU8!WGTubOHp&O6ty5rQA@HEwIWMVYch(mDNxjg0!3{pP}GhB zMeQk2)PVv;ITR@BNP(hG6e#LUfub%HDC$aqqHYu@>P~^89uz3*Nr9p(DNxjl0!3F* zpr|(mims+WQ6Gvx(Ph!dp9UmW)$Qpwk)nr6S?C+}oiC?oK-4RDixdrHc_|u1mZHIA zDH=kSqM>9d8b+3);bbWqL6)MCWGNa&M$u>r6pf)k(O3!;jiW%(cnTCvpg_??3KUJE zK+$9h6kS7sqA3(8no5D9X%r~BmI6i7DNrG-l0IzyA&vTj{-&8C{Xl1MWE=(XygL}5}Ob;I8RB@5%+6FA4GlU z%PHCs^?qI;MLStuiguBu=wq@JeL|L^-DD~Hlq^M`k)`N!vJ`zmmZC4oDB44TqP-L- z`icTY`zTPfp8`c+Q=sSo1&Y3*K+(4pC^|@iqC*rY`i=rc-&3IIFa?T!pg_?P3KacF zfuf%%Q1mkeijGpC=okfxj#C7Rwnrl+?=(eExSzZJNQ!#8UkLdn>N{Uf(XUaj-XbYF z&GJ(88(E5eCri;EWGVWSEJc5jrRZ<66#YY%qENE-+odQ>Mo|I{1&Yq1Kv5A26cwdFQ85Y>6{kQ^i~>a^C{R?A0!5`L zP;@p0ib_)iicUr&y$nd~m2`u1N{S9RMdu{@&X-ekUb1)XVks)e@={cuEJYQ_Qj|`X zqKafGszjEe%48|3LYAWQ$x?Iy8AVkoP*jZqMHf<_=pqUfT}*+Z>J%udL4l&06ezlc z0!6hbP?SM|qS_QFszZUIx)dm?M}eaH6ewyyfue>KC~8E3qQ(>`x|9M%mr(?Y$|gr1 zHXyOH-Jjb(H#ykT-|0S7Ym)3cUrteGviHUkDQd>@Qj|rOqUK~NYC)EwmSibvMV6x0 zWGTufOHmuL6tyLzs2v50+EbvY0|kn5C{Waq0!5uDP}G?MMO`RR)Rh87-6&AhodQKY zC{Was0!3F+pr{uGimswSQEv(qT}^?aJ`^bGOM#+(6e!B22oznB964w}Vy)cEPg5!C zW#9AqC;QHqQ#3f)^Y4?QAuKONL&;J!j4VaN$x<|eEJY*9QZ$MzMWe}5G=?liW63BQ zM}ea86eyZNfue~ND4IlpqRA8}x`qNpQz%e0l>$Z6C{T1Q1&XFqplAjKie^%vXch&E zW>cVO4h4#?qd?L16ezlZ0!4EvP;?_jplD!nq`Co#rIs}~gQTdgdo7xm>^omh(XGi| z`=wHJ8_P@4?PMvsgDge!$x^g{EJb&crD!2piWZTj=q|DpEheMrZVD7Fp+M0+6ezlv z0!8;xpy+-I6fLDd(E}7HdXNG|4^g1#VG0y2qd?Je3KXrNK+z)t$a(`3tKfd_dW{r);uL+9>^omh(Z|W&XAeu!CoC^TyU9}YDOrj>BTLce zWGVWBEJa_ErDzXXiuRJF=qoac_EDf{KLv`ura;jF3KV@qfue6IP;`(2MTaO*^c@9? zzNbLZVG0!eK!Kto6e#+U0!2Sjpy+1`6dk2N(J=}X9j8FiFBB*`L4l%^6oI0h$&tSe zNUWqgT)j(*`n!#!Q^~&b{VDHMSrlo6#Yq-qQA&e^fy_G{vk_IC`EhjQWPdj zQ36?tB4jB_B%{cqKv5C}ihK$bMJZ5}Oo5^l3KXSMpeT(3MQ2fP~^89uz3*Nr9p(DNxjl0!3F*pr|(mims+WQ6CBv^`$^jKMEA(QlO|m z1&RhxplBdPpr~0&WV->0-R0iIvZSc3`^k_&DZcaN6b(!9j;)fS;VdsjBgj%Tk}O4| z$Wk<#EJb6;QZ$wrm9*HWNp zIt7YmP@rfg1&U@-plCJ)isn$D=sF4%T~C3c8z@jTmjXpMQlMxa1&VH>K+(+Q1m_piaww~(T5Z$+D?I@k0?;Ig91f6DFQ{$q(qh*kk~1=bN{RqEpm!>rTEU5 zQ}k(yw|T7;ea7-q^f_6Iz937{mt-m0LzbewWGVWJEJgdsQna5eMPHLqbbtay-%z0F zTM85%q(IRj3KV@ufuipzP;{6AML$rW=m-UhexyLrPZTKnnF2*eDNuBb0!7CuQ1lB0 zicV0V=p+S-PEnxfR|*uJrU(>$k`npOfW+Q(zxJ_PiW>PAeoOJ4FQ@3Q6fgNXDf*k` zrRX2B6opc?=PpHIvJ@qdr6@v{qC~P3d1NU{B1@4^Mp2XkMadK>N})heDg}ztC{T13 z1&WGLpr|MXii%O7s5k|RViYJUL4l%@6euc1fugf1P*j=%MdwhUs0;;)%2J@{TnZGO zM}eYp6oH~YQX(}CNUTL=gY%~pCA))1g7ByMU`1zimH&M=zOviT|kzi zs$?muMwX%r$x?I?S&A+uOHp+)ifT}xs3rx9E}=kCEeaH6P@t$b1&ZoWpr|edit16I zs6GXX8c?99Aq9#WQJ|`&CgD6lmm;yyZC;~+-QX?-Lkl1?nL$WQUDCT}4 zWN51Id^trUQ@t-$AqQOVQnADOy67qI<|vbT3(o?juXl{bUp^r9jaG6exO-0!0r| zpy*)=6fL7b(Q*nDt)M{BBNQlFNr9qADNytn1&SW0K+!4+6g@$Kq9-X(^b`e(o~A(2 zY6=vsp+M1E3KTs<5h$9U8fj@jV(+>Q>IG7?yOf1zQ+?;lDS9E*8}gbIy~y%Xw4N+Q zFOj9_WwI2#LYATpWGQ-;EJd%8rRa6C6m2A<=nV=KZK6QYW(pK-p+M1_6e!wCfugr4 zQ1mthir%3>(Yq8VdXEA{+bB@`O`h@~TCn!*Kk^)7iC{Xk(1&U5npy)RW6#Y(tqCY4CMW3Zcb{LS@ zC+=|d=TdZic?*B0`p%bA6iV}c*(62bH0{YtQ36?tB4jB_BukM;mZBuG6!~N+ijt)$ znJh&qWE7=RpeT(3MQ2fH#vHk+dJ-0`A+q^OP~RWZ$X zzMP`-)4WD+O3?)@FGW?!QdEsBMHiB#=pwQdT}+mu>SQUZL6)MLWGT9YjG|f;D9WHf zQEdto)uBL9T?!P{qd-x83KTVq6g8qiQDX`eT}pwX%P3IPgaSpEQ=sSy3KTV^ zKv52O(mmf8U>23r9jbi3KY$tK+#MJ6wRVQ(QFD7&7nZi zbrdMNo&rTTP@rfo1&VH@K+!x36x~FDqMIpDbPENFZlyrcZ4@ZFodQL7P@rf&MWAR@ zTI8?+iH&eScRgB)Rysus(tPL3DY`4oOWh_#i&(IK)FeMd&o_Y^2POo5^w zC{T2S0!2Skpy($G6#YzrqN5ZjI!1w_;}j_Rg#twbOUWc9pR3Pnz$1IYp7Pyghb2yJWLk zAusW)!h8B2S&EX#Qsk4RC`y*1WU>^ckfkV8fPfT&S9`mMEVJ)KVQyytxX|DNlAzyJFBy3(tjr)uxo zwd<~3wRcrl!eM}-W-vfea~Png1q@JRhXINlFhEgD7@(*X3{cb>1}JI+0~ED|0g57E zfTDIVKv5(NP!t6N6h*@TMeSjj6zPE$zavCZF+XbU7ijj;RyQNjA<)WvF-4sNjrJc1 zMO~0y+M=$|LQywpp{P5wP!t0#6vaXdMRCwVQ9QIzlmIOhB|?LuBp9Hm2Mkcu69y>i z1p^fIh5?HDzyL*kVSu8mVSu83FhEg%7@%kX3{Z3p3{Z3}3{W%>1}JjE07c0#Kv4<| zP?QP-6s5rcMd>g=(I6P0Cg`z@ep{NL2C>jDS6b*$2MZ;i#qTw(=(Fhoz=sFmn z=z18S=mr>|=tdZz$O8iujf4S;ieZ4F5*VPU6b2|Ng8_=lVSu7hFhJ307@(*E1}GW> z0~Fl^0~C#g0gA@K07c_rm=w7KElUWHuy^Ci&aEzm;I3}{evD-2LH69y={4F)Kh1p^e# zh5?G^zyL*aVSu7}FhJ3K7@+8O7@%kY3{bQX1}M4%1}M4{1}Itt0~9TW0gCQ|0g9Hu z07ZAh07Xk-fTCqEK+$p-CPfniEk_BEuw8r-n!F3B4bY%yBMeZq2?i+I3%=sg&q=zSQV=m-o@bQA_C`Tzzf`Va;vItBw2 zeFOs(eGCH>eF6g%9ftvmK80aY^kSf8BmolEoZol-l2G(6-wydK(8_!P!tLS6otV6Md2_& zQ8O5zs5uN!)B*-5vcmvH4j7=QB@9s13I-@@4FeRlfdPuz!T?1PFhEf|7@#N;1}KVx z0g9qwfTH#=Kv4%6pr|7ZP;?axlOq2h%Q*rh>>ciw89`=Gzk**C+9}A&d@)7cf{eg# zgre?9FBHW<3q`TeLQx#FP!ta>6eU0lMTyWtQ4+LJ)B{>5>In^sdcgoiyyf?D7qd7D7pa#D7p~_ zDDuDnMI&K=qGA}Js00QmDun@x%3y$^au}d!6bw)_8U`q;fB}lezyL)z!2m^LVSu7> zFhJ3G7@(*U1}K^U0~Ae!VN#S6WSL5Ugk2Ls;N%KL-S`g3q#!Hv#S~2rGS+-26iq>T zq3C94p=c_!P&5r%D4Gr}6x{+X6wQDZif)A#ie^F!MYlnNqFFFN(QFu?XbuceG#3Ua zng;_E&4&SsZifMi7Qg^S3t@nwJ79pKJ7IvLMKD0oVi=(4E*PL_2@FtlHw;j;6b2|- z1_Kl=hXIOKzyL)nVSu7lFieW7gDkrUkg)cA5~~r4#;Xonkd^sjitYsY0+5jySZG;wzHbDzTo1sC`Loh(m!!SV6BQQYG78s!D zQ5c};F&Lm|D-2NdI1Etq1PoC0Bn(jW6bw+b4F)KB8U`qO1_mg476vHV4g(bJfB}l0 zg8_=3hXIOq!T?1tzyL)r!Z0aX9c1x8M-+wfsN));DAkX|OF>rViz#|F$msZkP_!HA zg`z#sLeXAmp=ckpP_!RfD0&TAD0&@QD0%~0D0&lGC^`TQir#_&iVng6MTcO3qPJmy zqIY0`qIY3{qQfvi(R(mJ(fcq!(GeJ+=qL+K-F8rIefAT?GRab%FtkI>P`(U0|3LS%WPf5+Gp@@j#<3*zD;a;33Ga!B*yrDT)m?e!V0V z#UZ^=6b~&FB|r;BiO@n(60}g%16nBR2`v=$f)bjF;6x{>^6pe)eipIeJMdM+BqDmN`XaWpS zG!X_UngjzBRlxv7)i6wo1_xV82#~NZ_`$S%p~#=R{WZZ>=8Gws8f?t{O(>d%^g_{e zXrbs9XrX8Zv`};_v`{n?S}3{=S}2+YEfmd$7K-LTgQB@GK+!xHplCh}P;@&CP_zIB zC|U>u6x{&>6x|5}6fJ@QiWb8FMR&mfMN43SqPt;$qNOlE(J~mIXgLf}v;qbwS_uOb zt%3oH?tuY{?u7x0R>LqUni6c;LV$$r=9AdXLeV;=Xicz{`C^J52sRG3q=n@3q_AWgQ6`kK+&TxK+$6`K+#qhpy+WJ zpy&x0py){$py(+WplBNmQ1mnmQ1lE8Q1mPeP_!KeDB1x76g>w66g>|E6zzloie7*L zie7{Pie7>Nie82Rie7*P(@?H=u>0H=%{11JFXzThKz$L1>}q5Hu)y8wMzP2L>p57X~Og37@+7&7@+7R43nbW!ImBbNLU;{n6^hKO5`U)z6!Q7Urf=r!A6nB8PIdr zr;%PL`VLwsIs+{forM;P&Or-B-$M&UKR^pbKSB#d=b?q73(%nGA`DRU6AVyv2?i+o z83ri&1qLYk6$U7(g#n6wg8_eP~iEyT)vF-1*7jQjnB zqClhIefAT?GRab%Ftk zI>P`(U0{Hst}sARHyEI(I}DSe#vzv71W4FDd@0l<#O&#R#}vhcSeY-TC?Ul7(qAY_ zM0%kp30f%X0WB2ugcgc=K?_B_p@pJ8&_YpPXrbt8XrZVdG$`s10~8H_0gA4H0gA4L z0g48~07Xt1pePvzC`y3=ic(>KqBIzwC>;hU8UzCrWxxPME*PLF69y=9!vIBDFhEf@ z3{aE<0~F=L07ZE)K+#|rCPi@}mH>k&x`pqf#S2Bl_-<@|h?V(biiU(3ovcF9P^1@% zhCvHO!=Z(u5zs=>bjF;6x{>^6pe)eipIeJMdM+BqDmN`XaWpSG!X_UngjzBRlxv7 z)i6L&4Gd5;83rht0>h-JFvOBYfP_86_tA=kqAc$A-yC9PzL=t0LX7c^grXTpFBIJh zEfmd!7K(0z7K&y;3q`Y`g`zpoLeX4kp=choP&6MJ6x|L36fJ-OiWb5EMR&jeMR&pg zMT=m7qQx*k(Oob=(GnP-=x!LGXekU(vA;9t6+eldtiW~dtrd0 z)i6NO8W^DHJ{X|rei$Z2(?TrE36QX#A_<)7LXkf|%D*qCrZn+Qc4kX|U- z2rU$Cf)LkmTZKnq1%poOAGp@pKyph3}A7@+8J7@+707@+7$7@+7W z7@%ky3{dnm3{dn83{dne3{bQk1}NGA0~9?60~9?E0~GCq0g7IL0g7IP0g7IN0g7IR z0g7IM0g86P07b9D07biDm=rx2V)=*w3Crc%`0IqCH<+S5Ay(##DS9o$_$^Qk6?hJk70nKPhfze<1j$cr!YX#XD~p~=P*Fg7cfB42^gU0 zOBkT&Bn(jW6%0`HH4ISn4Gfc_eIb^JAf||ii1rIbi}-HrsSqpk#T1K#?B|P-KAtiu_@KA_E2} z3V;EMtS~^44F)J`1OpT`hG9~4I>b^&fQ04n)BE2EMV>$sO+u~A7gH1*YRnH4ib9ZH zC<=uZio&3UqHt)Ts2Q|S)ErtUY5^@2*`b9Z2eeSs5*ie>f&q$J!vIBXV1S~wFhEfR z3{cb#1}KVz0g9qvfTCy^pr}0zP}BhiDC!6U6kP=a6m^0DiaNspMO|QkqOLGNQ8yT% zs5=Z$6axbk#liqZaWG7Z0z)m25g=ht83ayHsM*sW%A=0)p;qRLDe4hw9Bd{O^+bB1 zs28+Q)EinT>H{ql^@SFSu7(zh`augt{h@`T0nkFxHPE2wS{R^cAPi9CgaL|@VSu6( z7@#N>1}I8{0gBRLfTBS#Kv4z^P~?IEiZWqL6W`!33bis{OwsUABh)SwjX-*#=sIYj z=z3_O=muz^=tgLv$OA1Djf578ilK#~5@?~Q6dDwj!2m_&FhJ2L7@%l03{X@70~C#c z0g7&d0gA@L07c_qfTHm*Kv5+OP&5GsD4GZZ6itEwimG6MqG}kRs0IconhXOJO@RT5 zZiWGhrosS4(_oks4Gp#QB0$2P=d0^sLea4(64OJi%okHMGt?N`QYg9&>4l1Kx?6BGtvu14?zn> z4?_z@k3b7WTcCxaN1=tH$DoCxt7@%k$43nY_p_aV_NLZhy1kOgGXdWZAKh(;6F-32N8eg>)iVh&XQ1lkG zP;?MlC^`f!6uk{C6ukp26uk>A6di^Zir#}3ir$9?MMq$OqN6ZC(FZU<(T6ZV(J>gH z=pz`Q=wle5=o1*A=r{~e^eGHb^cf6L^f?Sr^aTu1bOHt_`Vs~xItc?5eFXy)eGLN? zeFFm&oq_?1zJ&pbPQx%MdOg%)iy(@sS`#>L2t~8`SB>9=TA44V==)HkOQcZr1JVmc zKSB#d=b?q73(!K*MQEYuCupJQ60}hCGqh0j3$#%5D>Nvog#n6wg8_r07VfnKv6pwpePas zD2jpsilSkFqV_OAQ3n{Hs3QzebQKIx)CmSC>I?%Eb%6njy21cO-C%&C?l3@63=B{d z3j-9z!2m_^FhEfP3{aE^!=xxA%(9XI3A=^6WuakaPya!J$4CmZGG9zl?=WLW2cf7B z(hEg>p@pKWp@pJ;&_YpvXrX8Tv`};nv`};{v`{n@peO|fC`yF^iqc?! zqI4LbXb=oglmP=2xnO{zOcjii%)>q9HIq(NGvBMLokTpAaBnJ@}?aFQMph)nN;>GG9#5^iOKYL|8SNWA-Cfu01L&$- zvwP@uwEp(lbeF_t-$W@t%-)S2y>-|pQ4VeF&(i~xk@kPkRaOUk z3jK$g&h|T^G_AY+UAo;8Z*P8;ruDF2*ICp0*f(_5wEp&QyKCA&drX|BrP`|#G%dsa zLXxIs+5hUPX?gavKAKi&Uv#ym4YR-3U(>F)+ppEMk@g#$npS4tl%i=B_V3a(ZJa$W zL(?YOCueF}js2x8O`B@hb2V*-eb8V{n`OVNK-1>gj}&RzLVL?$nzq>P8KG%Q?GIhA zX)En#Z`8Ea_Jm?hTWi0$RMXbmUn$qL&2~$LrfspiZql^J?RSsUv~BheDm87pz4atb z+i5SZ*0h)Hk4)CI-S+Qq*0lZhr0JUWrhVEBO*>?Nb*82rwi~lG?Wo;7SJOVSFPpDv zpW2Tt(6kfwws&gU*Y?uIns(a$=n_pkXa8}jrk%IbJIr(K{s+HInJpgYPRqMe{Swmw38L3dnuly-ye=>0hD2i?K{ z&Ax-~;D1NnS$FXNlkToN_#Xnt>kj^pu03=I|4Yt3x`Y3xVt?Ji{}gYa?%@Awma04W z-%@4h4*tJFS-OM&F-)HB;Q#DVs5|&yGYr!m{BHg0bqBv3eWdQ-w_BI#4t_mxh3??@ z%Z}3>{DRPlx`W^FSfe}m6@6262ft%&hVI~(WX;kY{FbA6x`SU+vru>Ndqx)P4t`O@ zQr*G7^k1nv_@~;dbqD{}cCGHeG5T9eaAx zAolXeNv6LxS!p@s72i$Mv}3ic^w+jY8(OYs5PMqNk{}YjM2un4Tg10?$m)H92uxb+ zGb*CqSLO_gAaS*bnXO3l6EUAfe-XpD^aDf$wkL6o2!Fb&(XSP8lo|znpeZ6&)5>@Q z&&TLmJ3Y^6+HKXR6Wi&7ji#=y$%XCo{D9D9e;j;%YCF9kAoRXNr?yYkB97{sHkQ)( z$Eq}bwkcY~De|V0*T?h%Lht=y$?RJwqkzyaKVQ0ICgo%_-Tm2nWEB`qFH8*{t3{rn zH1jD<#9k^MC!TC3HbM`*wQ7V)`@+EmTWH->ip%FtzA!^2UbD0Fa4q5;O2Y+zRMIpJ zdAVOdmFB4<>o?u1);GQ5HwCKT^Hq? zRsO&)-Med%iz&@IF2lo;xI?@^vv*NwxGF>OV?zh4s&7;^V2G;vR(l>P5J$c4}P1j@_FLZO{b=5ksnc-$GHr94RZq?LE?3L z#yVBv5e2UdRb_a1-Ox-`{4MQ`ki*_{36z!@ezAavJL z@9&^u$5NWtY5AyhNlXa?LU(+3>JwTU72v`{kx44$$9uj#V5a=NcHy2|H7$Bjq^9v- zfS)BG`cpdf^It$mOXKJwa``X7LURUFW5j;}7yJUEhlXn!{{?(NVk0#&{1@;miCuKn zz<&X!Nqk5y{{{F{2HVKxzkqN30yI5T?-&%`#1hmxsK_3whuAgEuY=a4$u(qYnx%zi z3A(yTzb1W~xM(f@GKU&Qqo>ABfWK}Dx~54Jnr$wolWFZtsoKyQY-)n`Mk6&rHPToz zG|UW}=(;PMlQfN@?BXa%U@)zma}EmEn>4A*GdNJQ*ie!tO#+)VZPJGp53$!#}SvS;|r^D3MWD4tpRKl-KM~6SQqDd-$yL+Lrz47YD6k z^=n(AAe~ye!bA12fPs#ClUwq7TN^$J{Or#sQ=PXV&%1fzwe`)It25$`IXdmH1XW}0 z?wq4*evW0y)W}ED42@@KS`?Ncpkg&HPGyiP32ly6|Fe{&uH|vKOpT7e_LH8sj;H+S z(4!d~_{3<=sGrtXQ2}W2!5r4}=|?N%fGh{AECW=QgE=grI-_McoS;9>eegOp#V28{ z&^K#L)5(u!<#Ry3`9AsPbG|5Q{yL*_|%gZKLl~?=B zPX!NlUKvFVd5J%zL_qw~g1uJ+_Rdu8{;ZlaC-59a>= z27)QYHRZf7G)*w--D^y2DO2VtD<4%nd0dUBX4=H^>evc~mq;iZQ&~fT4ou?DQ#xV% z_z9Js;)!F(Bd!Zl(mYfvr76lMkB%wuIfmC|S{nW6z)%N+B}q4o@PGO-^Z?5!-DqxU z6>He~8%DtOMp%FzA3;-bMtA_FrAQ9Ncxoy1=0+0^!A2AZ@|BFG*@?7R3nM(rXw}*X zXCuyNMf1ZW|BK16fM&d=C?hJMxe?x0E%|S+tXX_af)O5Pw6{!)G{T~c@OGS@$`IB@ zO*A*cRE`17j4-u50pUiNS_WHGw}lZ@Qd^|aD8TZY*59y`Y7u92j5h3T$%`{ukkJSg z5NuXJN2vfMV`+Ax(U}(GL=pea!n~6I%)%{bL+vp}3o1!>DSk8WM0{d=oMkeX7n@Zt zTAD{%#$GYk(k#|84sLi%gTz-DTv_#UZJ=pS)nDKWL+@;viuLJ+y|dB6GL?4^avdPM zq+xWE--4^Pg=M;#zGHyhXwk(dX`I@@LnE&P?7SE=ujZHuW<8 zH!)FrzN2AptrD|p6fi(ag?J6q)!g{!rD{RjW#{ceiYud8oB>7$Is#f`(4x`xGVS0C zFjsD(s#H7GF>PhXc%uauFseayVGsPvYWo)jY!PL2Xm8m6t^)t9Vm6|J@E(aWjQG*2 zg`%dwJiNW_R^3q@*x%f?DB3nYIvZ|P{Z;tF<11zojQ==Sibcr@vwh(Sc~$!kLI*ql`MqmVv zns}oXA5*+xt@`nVUorI|(hKrDY5DmcSI!V;mMhic%pX*got9ImVMcaZL4k8nnx`-~ z*OQf-Gf2x%8{|oFret`RNGU8RqVy@b*?C!Mg|uW*j!TwHPs#9<)Gg@DPxa*F7Sh56 zY59d|sopu6d6a2UPC-##UM|n@JBRAh%I;oHEigR*31x3jPDfup5EIqd8Y0HlBN4>cv@iw>erK(G2BD@I-B-#inGv_n`72fUvI*M6rYr?{K1}N zVl35FV6F^xX=cfpsomzua^<+awKmk1?(#VER4G$(b8^yBm=;A|dJnEJHJK_%6cnYT z5T)MKKz49ZT2Y!OoodQEE6W40X0MXSnRTx-8UgE66QSB}gTzy#?s0){m`_ z<H zjdkW0q<9JnbE!_#2uIn6X5G}w#OHYOZm`hf%u;Li8aMJRvr&a9Zbq1gk@j#k(mipecs$$uKaYTCoLt#laTC^ z!#t(lp{SacRF`v*C%33Duc**7BsZ&&jvsFpI2yQ7;pT^%E}x?_HEoECdZ5Wg1!gVN zvEkbunTHa?OqI+BH`j+x^88_RNPBXJq~)h)G7469{9ju0(IeCHqto@2I*WsA^61nN2%{s>YKxEF~>1)u-rEG1Sr) zI;o{_rw#X{J6(LVV_(V=+(V}#<`(7C1RZPXS+112)?d-ejheR#6B4}#Ivw&FHFuP* zprSajXRizzyKz;HsVSITqLob^KYp5bUFtAN%XQU1oKO;Kp0jiFc{g$UX&&2&>cAN{ zp>lL2HD=1|!K}S`h1xL@FvhscBPw@ zWUi%`&stP_#5;{!K6RFpQr6=Mje*CRl2VlKOp&I|Tb>L${|$B0h8DWA(`c`$Joy?2C+cLevzC8shD*O&`Oi@oph=fq}%NS3|)h5+=)oI*QkU`fh=91LRp~3T6Wp)}h zVRA8pHL1Ntt*4nTO>s22(s%QD2|6oy3!a*oDyPc)w479;)u&zd?%))4Q6$VzEmn>$ z_mo$bjVZ45@Ui60%$1duHprPJha8>#Q>hK8JN+r%y=N+)y`0de9`S-o2Ib^)@s*0r zqMh4-2^Tku4H_cfiwkNB)FG^@$9rTX^sJW=4j=3-pYyz{GPSs-*yAprR!F0i-p&2n z^IaW5S*f|IiS?ddWN({0hngGNsR;>k8l%&?H*XyE@t)Mdg`U(5^UPlVGN6~w^3q~u zQ=3$juTEI1RZORyGP$1jWaooTA8-zI`KkygxP}l1KdG z`y}>=>|9kouDrOqyh~)v_|l1!2b4~zswtluGd?MajGBtc<4Y)x8aJW1CWdYo44_t^ zj15|H)Wj)0W2z^{lqK{cr?{%LVgTJgn9?U^eC&9-1JSLldSbUx6C-0rN5skUnoV*~`@l0nQY9k8if|Sqd-UYBvRnMtzSJN?heJ+;4jIyDi+Q;7bP=^%~5J40Zg{bqbL(CTqfki3w&%yrL}iPT2LXkFzPK zmrkQq!H=DXT&+<9}XD~#EU=clD` zsmx2)1nQ)!BxcvPfNm(&U2yWbsO}1ly0vnIayR|I^X4G#Et)rl)J~>V$jZ2ft}MES zR}*H(Rax=grOYW*qR&OBx`d{lmRtZ*Lt^GemF83HJ_-1mmYPL{oLaQ53+nAV_mW)9 zUL)3Oo-op~^L)C3DLgpgdwSw>`}SlrhSK;)ikn(!bBpR7k~p;Zs>r)PVfuE{|BDV` zx+^`mes8r7h*W2ax|de(tmbXpuRQjs^G=mEmJdB|am=kQ%5e^%Ba1uZ-Z?&%>MWwJ zK3(|vcJ29M4OM57If%MR=9QCohB_Sh>Nq!tn;vyJknms5l>?LdjRH_zcd>pikm>dw zNGM1_p35V>dEOuBeLB6l(HRFBC)9OQ=^9$rmOxz$Z~1&`ATK{R!$tj3+7&r;?M>qw zSfxUQ3&NPV=puLo!Qk=GUE#XXmIS(r=M{Jxp!oO%O?6|ueHmoOt)?$<@PSRbGnIN) z4SL`T2`N3+1gA5~}-h3XD`R{r-B(=O` z@@Q3~+%ZHU`A~Ewn{1gw*O-GXOsD=Hb&WmgSz z2&QYIG#U?~QCqn>q@@#h$Xk`l9LUdh4)dhs6w3L^3NT}BWc}EC1M{iyFLg(#bO9iX3YPDK4<7$;=LA;aPn^YE$!lKmb z{7V23yeV|7{rznbbCkL6baX{qlfXR?l{b&rB5&U!r@OM~8qIg`q3$ZBpddx=57ny& z5DX$|lvOSsCYXH#6%x(UWW6Gx0N%FRTVXz}7xzN3AXZ`0?mc^|E%F^zRUrJ`$=7U( zy~A$ESKal&p%0UHYkra0jB%q2Uz%vzr}YPJeL7M!;G?S9>>@Qth>f5&k4{O_U68vu z=z;aF$0AbDH7e1aN>?X7mo1p-z2}4zrrDoSb;Dz;s-tG^d>+|Fp?r6Ky_+<$nMFD7 zoZO*iEuhQ9qx_t&*%Lud$uyQtckI;N6g8XsLzwAvsZejUMimc3j%wxLatgV1NhwSM0NS2t?Kv;(|lSH~Wmv?Q`PSX^ zs=M@0=;3YMaA+j(;HO!%daa2wkFL;%QOCO;%lyDust{i7+|`++;F^8T^FT0 zeJ?tY0*i76KT!mU`OOwMxV zxaj~+qj9wc*F?N24HvK5FAB2-l;!IV)jeS%k+9DPPL77Bemvz z2^6gEimYBQgtMmup@=pMW#eqjUWA%LqiYU^dOYa(B4eL6JR{#tJIg#2U9{tedH2px zC-tq-lr~7oLpprgH0#G4Po*Lx@K~gGQQW{${kB2*+)Hjyz4dyE%#%6}xJQFbP_z_h z3e|MFN1gUHUOgU!KqrUEl4H`hM`PmRa}~mUC$qWY@kOpKvx&eO)v;gj&u)QA&7oM{ zD&P>J=ehdu3;tQdAv6qxju3BsLR9LJ418x-E!vhULhoy!>Cx4 z8XDXhsoyn9r$I>cD)?y(ZBR%Rj$A zKtF7tpF3!O(T9FVG9##Ipw_|XhY|d{h~%Koa~scVG~af+bwR*F;|~8jEsOk?=$f-H zEm+JyH_-Grnl$>vWXDo>Ax8@cwPrW6G`5BLH`ANzc8f!AskhQw>uvN1zi6F)U3bOD z*Yejc{N=lVg&&Id`B>!F9I!0>OuWy>LeIm~kCuEs{u=$dQj7F1X3pQ{qj`P?{V>V= z)csC`wMFyJP_r%GUxb=VTQvHCme0qc)&Gf&MWdf-`Ft!I{Q}kJV^O86Gb|eYfXC-! z(dgwlJ|BxlKh!79wZi)+jJCJC&-@UYzPf?VZlJGgpvN@O6B=mxVVd{D`7iP+`tcP_ zuW6tkX`u021amyQLygvX;5+L(Uow2OXA!TK$ZwA`N@ zX}QM47RMG6J5%(dpM*UpdauNHBz_|Cl*Ef1>32?D2}RDgiX-JWk0Y&*f6m#sHT}*{ z^e&lySTz6CvN8SeX&3zrgqJ_Wk^WI>nEB&7tpi8$yK?NI(5l^LtAiATdRvOJc6XB8k^YES5N0;&_SG5~oSLP2zlsizF_Sc(23o|hf2q#t8%Ye2XqOlvv7^N95|boeEzv14Lt?JPArfzp zSSE3-#43r?B+in!K;jaKt0b> zGZKH2cv+%BCoJCHAc=N~krKN|OqAG9VyeV!i9;lMBvweAByqaLxe^ykTqW^AiH}I! zCh-M{dnF!}cvRwN5>H9|QDUt`ov!bA`x;AZCNW9kAiDJA`2`Zk(7BuSWQmLD(v$VQ z5}%-RHtQE8zDp-~*2g7Ypi58I|B%>=t~pqzNSr~}Jgo1KxRJ14 zOub0re!8mT`R_?=OcyMy?Gp3)nED2Z_t1qj&)+2R)BdLZPGa=6rjCOa*v461{T@vS%n)+^uZIrxO>Imy<2BRG=$1Hd zhN+iHd~2quk4X%fZR)lXhs-r~sl>JOP5r3ElM77!qr}d4n!2aN%EhL>MdJ1)rrsm* z_ob$`E;Hl66=uwqc>5|-uaJ1?UQ>T8G3-85x05(*t*Of;KKP)iw@Unay{Ruq?7GR+ zy(Lb3$kew=eC`ob?~{1>QBya1%#6v8n=x17!Y56=O5!`)OnqEpvu8~mC2_enRxx!2T9_L(vDH8T#Dc;_3YzE|Sm z1E&5=Vv9qjZZGlrcT7D-;>N?KeoEqLdiNHW_h*T*ADFtI#F}HKo-Ogkk4^oCMD0^k z2TDx;+|&gU7oRZo8j0_pH1!t}9p9L`qr@A(HT77Do4+&l(-O~|HTAC&<9{&q0Etu1 zn|iLqm+8%4ynP2G`u%L`V2K&Onz~5hlHW{yzr>@|!Q%8^N^JF~sXIv=NuwG(f4szp z{Y?F=#B=lpF`oaM#6;?#vA$N~RC=cv>-iFQ(aXhHAC%}HWa?0fnIWbgDsd^jcZ`>R zK;nn=0y5TLNo+%JB4gb}VhMEwSx=C-h2BlZdWXax=p|*W|B%=t($r3g)1ytjK;mwC ze;F_Tw#0x=rVf{w)y34qB|by%2jt~nm3UC%ha3$}`$qJ6j!o&sb`pOR-=AIs#=cFW zLt-0=Q5-4%Sc&~4W=JfOSR!$P#2FIrka&;8O%k_Be1#*G^MXW!1_xR9m6$AXip0kx z?vePh#Pbqu^m;2!-%et0i8&I>C00t@AaRGp?<8K7*pc1?rOG35yu>LIw@Ca{;(3W3 zXaIoI#YpsUq9#@m`7RC2p4Zgv6&Mz9?~*#5W`!lxWlF zxTEsXu2(T!qFrK?#EufXON^J8Cy`&%!}(k%kuDRI9wm`Z^Ger9q|>s}w@I8UkxrM& zUm|g}#I+LXbfM-yFL9SdYTlK9NaA6M$0Qz?7{IZyIabN#dHmP{h&y3Ajhtg}E z#Mff0r;V>EE}>XcWyT6j(F650S}Z@ouEmyAS8K8K%zZ4IvF4!Sl_Q&Ki86lpi0ZRrwS%z3I^FfP7_f75~0O)?hAir8ACS<|8>$5w%!;MNB#Uq|0ZmqpFI> z(?ZVt?AYR(nyN7+lWQp3|BX*;T2`k&u225-FoXA-s!@HIA70L4$}5)RdHm@_f6U^) zT8_DExL)6PHt~Ms4|Cdx{sz(?e>zO0R~=HM?u**jyd1ADpZ-t=n$-GO=_R3bY~X{b z95Q_KYc`2qp+|gheq0C0??#$N8k*Fa_N8~o`52g-*kHLouGY2hIe~nz+&I#{>%Bau zZadh=digj)8qVT$KV6ID3He~&Eu?+(J2zKXevrihD)Et!GkfuCkevsdKlD_#hou{k)#N`X7KWy(dn&vdj1Ai(r zbS=DJT4!% zohTn&<}u3?DX7mt%I|6jidYv%94kC~1}%4Psj)P z5t8+m>p3ng z$i}y&Wu=?1LNhbgY4jiYvePU``G(mhbky^_X11)Y#roYQSgY>J~ ztLJ+yaGbjHChgpf)281Lx8;p*C?m73>E%(BP1DcGxXw3sGX3;`*SVe6ZP(HqKR@GF zHvOz$Q?Pu()7g$}4*td~w4CJ#FO}PJq_V8rS=o$A&cSAlB<1gK@T0$e{#G7dwv6Jh z?%_^a+_Igg^1d0?M%Sp`H^bWK z0@V9vSlinyr7Zd4tnpbv3tO~o`u@M~B>d068u35- zPQw4@w+2rBH{TlA@NIw$-oN=aKzZ^MUv)p%kl&Ez74y?K+0~=X=Q9(`AP-urr@-qyG$zl@YhKfQ9>4D41A4UY zKlZbSD~lsP95vr0;qx=A|I7~>nOE}(Xz%9pSy)wp_qi}{Rq%6-c>1mGae7Xm@<`OY zzd@5~3sy9dI%?(o!VK@TkSaUQ$@gUd|BVk;@nx>>b5-1@#E08v6n>k zd=2@@qVpscNi3D9#$RZ;Nut%b3+Z{Hmr8t4;-eC`aimL^S4F?Yk;YHnk$6P>&qbe< zNW;vkyq6^Mg)x^uNFoi3D&1LPPl?GAb0uCcag4+%5~-W1%C%17yW*=$eOixtE`{O= z@tIEE4x2>oOR}b2q9R|JvyPG2Ln8M9*;o6E5;GU9`NI+UUe8x#q-ocx=b`wxP|N+d zj2qQa<}-%#f8@x~|D(!kMIxMw;GNT6#its+?jt?)xf6P!J{SjK;&-FC* zosWUZJo0_>OQrm1DC&xFqmi^6($J*F&o{lo6Y{~lD$MFzU6DG>aieit)mrL}8^wHAoBOK!NbSzz7Uv^u&hzVMHBTS(izRGd?Yzi} zXlr`Y^nJCq+52k!qn^*)S9>Dz2u*2S|M+BBbl-}nbN1D0p*-(tHSfb({{*euAD>K% z5sdg$b7=}WX9{Y+8%cJ&wcSk%Ime~;)B}r_b~eQPuSr8qISme*K1G2f7~F4 z_3rhV8(bSQ4*2Ad-~IqC^?-YM&Vkzf@mQy()|q~>B|LS^uJT z^D`@`44t>px;DICdsthVG1vWi?S9RAVOCRGV(II(-A~YV(Jel-ka=dQn6aUd^Gpc?t+8Gw5Ik=MuxTTlYX$I()FH{{c!EP_>lNLwOYd5 z2_w@u?wi2hhihjk_sn~xl*|1Ma%tB7V95>MJl?0gLJ~RE`?a<4B`TNqYcH$x?~}`O zPQN!eGrZzK$>&IMP9~?~`p>v%ZGWtGUg%!hJI87lN?a^)sfu~7y|pJo!bc9IJg`Ma ziU(c{ZXZ6fA9-uM`3}5TlC+m{&OJXXWpC}__>7A?s`paOCwkYHd@-EXw=y&)$6VuT zS<_mH>s9PYYurz3Osd%T)4%Xg7{HfS-;hmICKYwD`ba6#eOlFKLmPaoC%Dptp z@>4PGtw}$P@%U*M#xCgM?vmNn)m6>qC46;$bQgC}F74ka+OP4)q#jHr=B2lHcgXDE z>X`9{P&BOl8?;2UThDoem`gdKg|rxWLepohx9GDH+r_{6#S;nZdX}vY8THyq?O=T7 z;e7{_ZgPFI^=a*@4}bQz(UI@a1}<25!f%$JJ}a&1Qf=FZ8{+<2Gk%5r^P}B*yx;EL zrxR0Ndet@Z*YY!8zSW}ep{I+7R{C9jYTFz3s*I)nO`Gb|2iS~{3-;`6`@$KF$4XPb*KdHP9op>v9FLj-mH1b!q zhDY6xxgN{hDr-noYZ!R(wxp#lUc!6C4I!?RHfAi!e5ZI%?Fp^PNH3)~&gztV$>EIwR91c##Simu4Kcvz<+I;w<^@TiUI`=t7g z9;1Bqy-|IiRNv7zDPMhWRNp7ncl220tM85K`=t7g9;bZuy-|IiRNv9#m9M@xs_&EP zJGxT&>U*R5KB>N=Cn#TiZ&cqW)we5icuB!c_xoKw>Tx%VT2Yen%joLVocDM;6R;1C zQj0UpMf)J(D78sLxgDmdh4E%wEODvCl@eD=Tq|+C#LW`7NPJx4Hi_FM?v(hl#N872 zOMFw}A&G}29+mi!#7`xjh%Y>$y_(f@iC)lsTb8H&0?)$Mn_qkJnT{W~>3Zie{fV2K zUlr1Qj{jG8zxeBx8>Vi|@8*0a>)g9lEl&^StBSd)I;O^w(fcN_?o~6 zyNx?gJ?EY|pWD`^^ceVD;jO<$=M}rZJVEV+PCd8#{5y0!)F?aY#Br^US+`$H*-uM6 zC-J<*OA>1(UY4jOnCbl`+9WoW7$UKmM2EyS5+fyckl0ybcZu;5dr0gfvA@KD5>q8+ zNX(L$C$UiCFp1Yo94WC(Vui$U5+_QmkvLW2jHpNHjI2dHTVlEJQ;OwhBkAEx%f+w4 zxiuRWO>Ik-*|wjEKPqke2Gv^ZmlkZDYaLxFtXCejE{T!tqeo^$ex+KMweGc<54avs z^D5L;!u{l|6=zuVUGBSb_S2bTKedlIa_&`2Q;AgjxYD)Cy(;q_Z|)u2Cywk8X|})1 z+{-hUyH==qsVetn?q%dGSI)5L$?hpvlzp+9hqB-4y3@TVbCEaq4peqc%D%w8AakK> zp_&(|a=)FN1>&S$JZ!l=b7RR3nWfYgtfRId_tMVN5w3y~_e~Fyn&lpv>83erX*%_n zJ>m58Tbi?))Gh8jHD`@V6Qy&ytc>@H3rbQ{n=-Nd0dfQdzF3T);l`D^~l%hjuySUXi_e$=iB?WP+++4b0QQh3# zvl`|%v|fHi?xM^gt|8w1LREfA-u#{`Xsz<&?Hd+lcRQ}gFQZ<5>F)H*LG+SUW{k@h zrt<4A`K43cT2+2rM;WBLyQWh+#OLXA>(4)owk7iG2lS{<$L^Z;VlCf#Tr3a?|e(H`D&z-yBr)O)7vNgN>oE6J!|FJCOPd%~coKa&^ z-W^!_+<;EeE9W#mP_U+f;dB!ZjfWgFi?+eyDAX-*j#l+eAGbxqo|jOvD5CS&zp)+>G1VqKA@G zy3Sd5w(;t(|9Ec0+Eb5ZEGq#STilO$xp>&U*-OP{_Xb55SbIRtG55uT?)!39lsxF= z1xML^s_t==t#+@@T;p2f-5<^9DAVL98y3C9ea98Y(cSg-CmqL`OI%C5>6_F3>>$U{ zu;`iYX;&QO^XjeNWHgc54fDvRYXr-<%xXG*n1Jc7o7~GvD%3XKM|!loTx}trfy><` zSp_Afbga;o?GV1M^|w!OPt2U?nw0TvG4sV&vtJeOuRUD+)tDRUYWCu6_r>)yrghp+ zS14oLV=`}Y-IPJo>dJ?g&v%c`+*C5!RpG8sWsHm-cyUfrM$XBS(vj5_!?nvFd`Rc= zqReh1IgWIVRne2NRmE$v&Z^k0nCFgF-&@u9S@qqmMEUA_tNK2xzPptwUwv;?-)Gf# zw=(6c@2%?ltorU&u6*^qRehgT-`z$jUwv;?-)Gf#x6#U1-&@u9+0oCG_+99hpXm1c zdB19{qiIY1k}j51k1VYiLECwh&I;Y!uhq_q6Jz_v9cg?#;+c(6F_~|^{LR93^ZWmN=C`D)H_Tmp zxF%sw=bwHpe<`8Uo$Ib0l-MWm&K&=JV}70Py02zK;Ksn_T-MiWS4s(2OI#~)y~NED zw@7?k;x>ufCGM2?vc%mI_e*?J;vtELB_5Udk;G3Wo{;#p#M2VbNjxv{lEhkxmnCXZ z=JxqZv`K6#F+^fBi4KWvBt}Z?AhEN=?h@lA_K?^|VtbLqb$n^R%# z@XT;mGj#+HY#$^`end-tQJXi*Tqe*Rlo{j-mSv30*Hvzxs%7G5eemsbgSJNTHSDSH zUYNA((7FrrzdQBhsSjRWx#sGQ?|1N9e6efMh80szF1yN4qknQve?Rr1e;=#{mHc%l zjUhHoraK+q@TjEEhn}>VN8@eue9vqezoO@R4$y58dcNoTC>qQvi>7Js^F1qQ{LXTe zM!f2t?^)c6l+8H9rpr(O?S$EL# zjjjC9OB3rebWfnEb#Wy9h}e37hT(#&pG43@ZPsG?4za#ZONLrIw58!Y>%Fv{;noeb zOf%~q8i;Fdb+)6STkCNeJ-1tjx2GPywH-~jw9cfOYh~R<)2*!|Y3#3!^*dTJ!rGC_ z(9Ze>&5g7kqBTZY+tXU2tshZt?X7Rok{ztsbbF+u^$g`!W?ey*T5hfCK>st{T1L;L z9I$>%Wq!-roNj3xv`(SX!9&*0w7qXzf1xGcvF)YW=&svhX=O3GZ5b^UtJ_kk#^ZEb z4=PQ(ZnIHXs@u9yjW5$}8B~-Nx@{iS-AdiIm8xr%ZhN29J-Y2#sYT;)Gu6xY7TZj!j2|qv+o(2vwAeyu z!_Hf57Fxpvi)|IHA?3bjqta%r2TT8zik-p zw(I?EQN+$Re_IU|qM2dy&=xf}Y(Z2LQw>`-)zUP>wu&;FZrJ{yl6^{w^8C!Ob)t&= zoJ<1k3&R#iyW<1}D&Uuf?QN>1lZK6d$9ULk`oorQnICQd&p{<>0x5ZFdCfRNMsAN@kTRU29wcYkPEm>o?JxrA~*=~E6 zcGVPGgw}Ag-PW1*!&JNN9;(4pp0?puyNzF_Fw<@e zqguMnZY!pWoJDyO6SM8Ml~jmlNJu)i6UAilqX_n_wqTZ(Ne0h zaGtnKD{aOT%W0FF^TZ`u7nizGH`)dC(+#cB7Am|SPh`<5_!TsbUZR80pC<@%+6tQB zU&#mX#1ph#yi}t>M4QeNMO5K_JaL-#1*g**Z={U;D|O3y(sb(EPitzT9x`p}Z(L=> z5L1E4@tV=8#r>Q>Z$~mgGdhcmAepEcT|~AenWPzAMYbW?Lo>RGY)!JKW^@FC?+DZ1+jChePNG4FR5=1v=P31}y-HbIAEJ<`YYbsd}(P6Bq zXgx)TvZk{25*@;t3fEh7Fl#DZAJIXqsd#-w2ePK}T`jsP=|n1DKhaHCQ~COfZp@m> zH$ZeF)>OW0MB7+X`K}dhWliN9C^~>OmCq^KU`^#q7VXcP%9kRV-u{!ENaafv?MFI^ z%9kcuXHDfx7ft&*$lvH-$))`tJeu$^IyPefg3nMJU<|Ux(1A~{KQP=zE+M4|$&#c( zNVZ5JBuAtWk}FaO$rCAr3>GPbAR)M6Q#CLwoGTW*ZAGC54hL}L=+qX?NKNrjLq zkwQqdNFk&~q!2P$q!2Piq!4nmNFijZNFijJNFijpNDy+1Xb>_(Gzhs>Gzgg~8id>? z8idRe4MJv%1|f4qgOItRLC8GOAY{I15OTX{5VAlt2w5l^gxnz-gxo0_ge(#bLKce# zA$N%eAxlJqkh?{LkfowcLMkmQX#WSVp(`C@f=S45x>_=pS(zLrWR{tphJ3mIdjNytSqjOVOO4ioaCv4bv>6d^B3 zQX%AJkwVBTB88A$B88AwMG7IiMG7H%L<%8$MG7JNL<%AMMS_smM1zpmMT3wxM1znw zMT3w7qCv=8qCv<((IDiIXb|$YXb|#_Xb|$QXb^H(GzfW5GzfWLGzd8&8iX7b4MIK; z4MIK?4ML8I1|c7b1|c7d1|gq_HVN5jIY#?G_$9h%HC`|Y*+Q4|#&Ii?!-RZc9HXmw zMaT(BDujF~QV2OIQV97J94T|h})_J1Fr+1cL?vA`^{D-w!=T`0ELt=Qcy*xjgzC?J~8yg!~YjkRM|c@>6U=evVDZ zFR=-k9h;C}V-xaQY(jpIO~@ay3HdWNA%Ddt> z`|q+^dJt56G*?J%Z2s@*S+h*1)Y4cqre8Fk{t@b$AI%iyIK4pH>27b6J%8HiZh6)2 zop!og-p=locDh^M-tL)px?A4C?vZx7Ti(&0FYR=Bp%^_XGn$RtWbQN2Kd2&eCv8&KEhjb<95n6Ic*Rq>X%OPFOR-sD{>3X&aopVT6 zbY7uT4(Xb97n)PZk8tJ_I_8kBX%C@84(Xcq6x!#Iu4yl!T@LA*_76yUcKQhk$UKcjL%Fhc0#f@n z|Kn3B*A;D(o?0jtE>|`=759g23aL(z_QDB8)UXlH?< zT?C4D6)4(GplEl2qCEtP_7o`EOQ2|Pfuel`iuM&K+E1Wpe}SR{1d0X=6b%t5I#8hK zAc3NT1&R(4C^}T2=rEzKXi&K_BLS&RO3%&}n}?!}($}Ek@NzZ#%8HII7vH7l9_K1L z#`#cmtR0GuvqRDGb|^Z*4n-&0q39$#6rF5`qM>#uI>n~wRDq(?1d4_U6rC`-*I z9g4==q39Yr6iu*0(Y1Ccy3VHPdV!)F1d47HD7s0Y=w^YUi2_Bp2o&8aP;{F>(IkPQ z$pS^U3l!ZUP&7rL=uUy6sRBiJ2^8HeP;`$#(Y*pi(*%m{6Y7dCD_3?(Kx+Twr+zOF zMNiCqELN^&Us=(^<>JKjy3AZfk2oKS9<@W!V|FN-Zik}B?NIcD9g3c`L(x-qD0Xiaro1`cSAVdazs>pMcaZ%WxhFMW>~g#fp#0)$A)P`m9_$ znw|!ltLSs*L(xn-6n$ZbqA%@G^pzcozP3ZrH+Crc)(%DgvqRA=o1*UoioO>p`az)R zM}eZB1d4tZDEdX9XtqGnuL4EC2^9SU4`Sr(WWr3mwp|0qYa%E-$QrkMc4qALlQGR`@(ooI5vZ883Q7jUQ+BqMJ+S{S1 zgB^-G+M%e~4n>{pP}JEDMP2MrRI@`-i%n5ifueZ?in<9DwF(rq2^7sMP}E(ZXg-0W z9s)%@1&VqJ6!jJ;nqQ!30fC}E0!0f76fGoB)K{RWpFq*Vg0Dr32oxyh zutU)bb|_lW4n-^36s;^!w2DB{sscr;2^6g^P&81WXbpj)H3f>+5-3_*plBU|qICs| z))OdNU!Z6MfuaosiZ&7`+E}1y6M>>l1&THkC>kWx6)n+FIU)h6y_MdxQY;yY&dX08 zZQfALzOtgN8;XmT2u0gCABwiML(z72DB9i*MLXD`Xh%B~?PQ0do$XMxiyew~wJF+7 zplEl2qCEtP_7o`EOQ2|Pfuel`iuM&K+E1Wpe}SR{1d0X=6b%t5I#8hKAc3NT1&R(4 zC^}T2=rDnz!v%_t5GXoQs4LpCp>l5mQk$IK7*uQ(iZ;ssydBk0&Azgt;~I*$(>Hd{ zy^^P%VjI~1L0hoY10P;{~#iiX;u=oC8?ooa`o)9g?*%%UjSwh0 zQ=sT9fufNDMP~~Xog+|mu0YXw0!5<)iq01(xu0!0@I6kRM(G)AE45`m&i z1&S^c>WYqOsQi9|;tFEKu}`P*?OwL*?uQr1oukGj8!{C>oRB-SKHdHT%kn zzGx_J84!xTbUqY)Wrw1#?NIcM9g4oSL(%{2P&CU9Mc>(>=zBX9{a{n{qd?J50!2Ry z6#XJlG+UtPSAnA61d4taDEdR7=ud&7zXXc@7AX2hpy*$LqW=Vn<_Hv(D)F$LqOw3y zgFsP5pr}!xs1WLkK5wYJlz`MuOs{YhGec32{1jwUrJ8+ZMI9=|4=aYEj?RaoW;+yh zvO`g4I}~-XLs88RMJ;wH>S~9gdF)Ws&8DbTpr}otXkLM$?gB;g2^94ZDC#Lt)JveK zw?NVS0!0f56!j4(T2P>9A%UX40!94|0K5GdMGs4H5!QrRT|scn`=739g6m_DcVz@XfJ`H zy#qJspA4i+dnM4;$Ufuh3%iVhbjIzpi6 zNP(iG1d5IpC^|-{E83<~nUH|g*39>dwhcwA=cgc#tyHtGtmwo_F@0btI?4G^bg~_a zhT5U%6gw21YKNlJ>`*k!4n?Qip=h`riq5bp8X-`0ra;kI0!1SQip~}&I!B=BT!EtV z1d2up6rC?nbb&z8g#tyR1&S^bD7sjnXpBJ7B?3j43KU%?P;|LK(G>zkR|<7S$5$#} zCLpz~^Bw9FLeUmk(N&dd_LUWluN2j_LeVwOhoT8~D7w}TMc3J(=z2R8-C&2J8|_eZ zlO2j~wnNcGo1$9;if$Dsx=o;Hl0ea9fuh?5itZ37nj%nir$EtEfug$vitZLDx<{bs zUV)-%0!8-;6x}aS^ngIog91el2^2jnQ1pmUS2V6tStWZdUDn}(CwJG_n){lpxb<(@jikX#a_LUWVT`9(_7mB`dJ`{ax zhob-4p=g#JioUZ$(f4*J`oRuGKiZ+_Cp#4VY*X}$K+$Z0qF)7yeiJDAU7+X>fucVJ zivAKP`dgsrAAzEO1&aO?D4HWsRBDWe?G%*-iW&rpDgs4~0!4*DQIkMXRiLPyP*?P2 zrE*^aQk$J0+gHY7j`B2ow4n;LP6t&o)sH+`{=CMOj zH#-!y+M%e;4n_0Y6m=IUnoppphd@zJfuddlMZE=z<`*bhK%l6PK+%E%MGFZO^%W@U zCs4GoK+z%sMT-g)EhbR3xIobo0!2#-6fGrCw6suH)UmPhUjkCQI(=ty(cD;nq<>oe zzSLzJtJzmpw0vW+z{a6yfb*ef1v?b2XosSe>`=6_9g0@5L(!^sC|b=9MXTGPXrN8e z8UjUY3KXp+P_(u{(K-S}>k1UDCs4G$K+y&QMH>nfZ6r{%u|Ux#0!5n&6m2F@G)SOm zbAh5Q1d6s4DB4P(XlsF@ZG^g_{*9IO6Oh`E`F+>Rg`y#OY};7PzOten8;kun4MjUS zABuLiL(wjFDB9HyMZ4LdXm>jl?O}(aJ?&7mmmP}swkg_2plDx#qWuJl_7^BRK%i)_ zK+zC^q5}nr4iYFjSfJ<-fuchNiVhPfI$WUW2!Wy_1&WRmC^}l8=oo>bV+D$i6DT@f zs4LpOv2tz#QhO%fq23`B-JKPk&{)mBvZA4l#chK^(J9V{qEqcqbebKChS{O$bUPFc zw?okxb|@NQhoUp>P;{0}(MW-!vjvLI5hyxWpy)h-qEP}x=L-~FAW(FnK+$M{qKgEI zE*2;nBT#gSK+&ZFMVAQ_T`o{`g+S4j0!3E|6pa-q8Yk2hozz%)B>}1ZnPzcvDB2}I z1$lL2HT%knu5B!S+9DKP=X@x--VQ}K*rDh~I~3hyhoYP9P&CmFMYq_Y=vF%v-DXoX zNuX%5K+)|2MRy1kO%W)%Q=n+7K+#fuj2aitZOEdO)D)L4l%& z1d1LOD0)Po=uv^9#{`O|3w1@;G*;TSOp5-=Z*QCsin`>NLmqFeW?xy+(~ZT-TZf`& zoDW6M+M(z?Tg3)$NXN$=AxQ?Wkt23cw+ld)Z%<7>S~9gdF)Ws%??Gab|`AIL(#l; zDC%y9qWSDl)WfEzr$A9Jfui05Me_?3Eg(?TN1$jyfue;3iuwu^^%E#sSfFSTfucnP ziWUW`Wd(}*3w1@Ei^|stNNtn+#vMe7R`Z6Hvzp+M0_0!14O6m23(2?9kY3KX3r)D`Vi zRE|kNYW?&3u6GVao2MV`S)5!{v#+e^w4%6lw@@_9`A~Ga9g2qAq38@d6pgS$(V2EA zI?E14BkfRhwjGMju_-!Npy)h-qEP}x=L-~FAW(FnK+$M{qKgEIE*2;nBT#gSK+&ZF zMVAQ_T`o{`g+S4j0!3E|6pa-q8YfV6wLsB$fud`Kx}sBx$^!{Vt#^Lk^{Js~PF6Ib zsAgYT(G5lM{vM&|M(0D(O?D`{*$zb$?ND@!9g1$XL(y$^D4Jx4qRDnBy4|Me4uPU6 z0!4QU6ipQGp16g}^JD0;yT zMKkPB^r9V#Ua~{c%XTPw#STTU+M(z*I~2WcQ}l*F(VGHAZwVB=El~81K+(GbMehj| zy)RJofk4rR0!1GQ6n!jE^oc;xrvgQv2^4)UP&8AZ=nH|OF9nLe5-9pwpy(T+uIQPf zvS9*JdpbYS_-rUjzx5+MU@NNGS61|WQ4HQU6#d|QDEiS3ML*f0=w~|={bGlr*>))U z)ec3!*`ernI~4t4Q}m}m(O&{Ze+v}-BT)3OK+%5!MRNp-N=@;wouaZpQG-BHMWCor zpr{ZiY7!`_3KX>yC~7ZI)Ip%Aqd-x!Kv5@wqRv8H(X65}Dgmi&niYK)ik{8)uDdi< zv#+dZo~B~*{-LOw^P#BK4n=KtD4N#}McwUCG@l)cdf1_;ryYuV*`cVnP0{=UMGFWN z^${pqP@rfbfug`Nr9rJ1d5gxC|X9KXjy@x z{sKkI2^1|aP&7cOD{5(~yq18}#`j5Zx;E7x>F=5UMO&e%ntf$Ot27nA3=T!BIvTE`AW>)I5pCs4G$K+y&QMH>nfZ6r{%u|Ux# z0!5n&6m2F@G)SOmbAh5Q1d6s4DB4P(XlsF@Z3K$86)4(HplEx6q8$W^b`&VuNvJDY zsj1R^NK*7t{zq)(Q1oqn3UcSBYW9^C?cP+ZdQd3Z!}(COryYv+vP03{b|~7%4n_Og zp=dul6zy+^q66$uG}xwSh(OVS0!0T26df#3bcjIFp#nvR2^1YJP;`Vq(UAg0M+p=i zEl_lfK+&-RMaKyg9WPLHf?RQWamshv|KI5&l&!}6Pro^7gTUs=(NrlRAKq3A{DL(xliD0aBh8>FDv_sKbHbrj>6ul!*^sYeBdjdu83lx1IQ1qcd(MJMB9}5(HB2e_H zK+$IcMV|{4%@ip5LZIkNfugSjioO;o`bMDWTY;kg2^7r|>WZFks`O7lY8U3$(Ow8e zBPwZp*Hq2EvZ9}wimi_hML#u{c4Az-|SHIyB&)DutU+Gb}0JG4n=?4 z6#XMm^shkCe*#5w1d2-4c-T%+S)iyvpr|5Hl-?3if5o1nLZGNgpr|TP)J~wNy+Bb1 zfufEAMa=?5odk+H3lwz`D5?n*wFq@ZKQvX2OF(MJr5|lw{1}SH>|2}o^deu}8IT7RT}LjD(R`=769f~%vDcVq=Xd{85jRlG}5h&VJplCCJqCo;hn+p_e zAyBlXK+#qLMOzCLZ6i>$tw7Os0!7;k6zw2Tw4*@LP69``V#sKRXodZ-=4->`*k=4n;%k zP;{UjiVm_VI#{6S5P_mY1&R(6C^}rA=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZCg% zfua)yicS(JI$5A-s6f#v0!60^6rCneG)$-~+M`<8I030m&ab2G8H&0tn8xYVYW9^C zomnjo92$zway}G|v_sL^b|^Z>4n^nMq3Aq26pgY&(fM{Ly1))a7upn!7AU$%py*zRmk1PHDo}KpK+)v_MOO$ET`5p>l|a#0fueB&MOOUC+D~F|5&YN zUs=)YYO(qmq3BoVL(y+`DEi$FMSs|#=ubNo{bh%uzwJ=;j~$BswL{T=Hbrv;ic0O` zAvZ;3fuaV1qKZIKqd-w1P}C$)R23*{Cs5R0ps0gDQAdHIW`Uwk0!5t#in<6C)dY%K z1d6%}6wM=0)J>=>`ng)!D*>sk+C9PfB^3RU6}7gjW?xy+eC>+U&kRL9oDW4k?NHRq z4n@7~P&B_CiWaa#Q6D=LEog_Lh3rt&*QThSK+(biMT-a&EhyUI-o zNNsq(1gCqu`Xl}M@^=!g)~=d;WkqYYE1nq{iq>*I6s>KCqIK+0w5}bB*0V#=`gSPV zzz#(l+M#G8I}~kfQ?!Xd(WU}Ln+X&R5-8eSplAz$qAdlAwh}1XTA*kffud~%inbFd z+Fqb&2Z5p;1&VeODB4+|XcvK^T?LAE6DZnUplA=Fu4rJp%B%#W_IhiAvqmV|ERQ|g zRkN?GXy0~4r*lKme$I!Y{q0b6fE|hk+o5QP9f}ULL(xHYC_2~knIbc#UHsRBi( z2^0+zC^}uBXt+Sp8A4sr-t8*OCm^*)dn7pfgrZql(TH}{>?Wa>4 zS2-a8sZE(b!5JBfe#&=}ZfRG|zOtgp?TRZe2t~I$ABygYlos~HbwUd6x}aS^ngIog91el2^2jnQ1pmE(W3%Ij|mh_7btpMpy&yK zq9+B4o)Rc}TA=6|fud&xik=fFdS0OD1%aX&0!1$hbw#(et2~l`)P}T6a3+PKPxH4G zz0|InePuGl`>tONMQ`S}to_ointf$OzqczE9utcG za6T0MX@{b}>`?T#9g6<3L(#u>DEiM1MRV*>RB9iO+e1;=rl>)ns3K6*C{R=g6g3GH zRRxOL2^6&#DC!_k)KQ?QS)izsKv8FbqAmhOHG!fQfugPgMe_(0brUFR6)0*GD4JKO zEBduvWzz(tHnUHH^IIqyl3xz#-oBcBWktQ(7YAP&ih4UAisrXN(E@fT>SKqZ1?^C@ zkR6Kp+M%eQ9f}sVL(w8OMT-g)EhbR3xIobo0!2#-6fGrCw6s9cG6F@*3KaDhC|XXS zXnBF60RlxU2o$X-P_&Xj(aHivs|XaWDp0hVK+);~MFWMpq8{xlqZ5!?TmEtTJ=@nG z=^xON#v1Lb*;iJyPW$4{%R|w+&WED)>`=769f~%vL(ztIDB8#lMH}0pXcIdWZEA<2 z&1{MW2^4KEP_%_W(Ut;5TL~0xEl{+LK+(1WMcWA!Z7)!?gFw-a0!2Fs6zwcfw2MH| zt^!572^8%vP_&0Y(VhZDdkGZnEz}jQ)xPpp0#bW2|0A|`DB30cS+P(1YW9^C9nik` z{mM`@*!fU2#12IV+M(zmI}{ykhoVF5P;{sriVm|w(cyL|I>M&tNP(iG1d5IpC^|-< z=vaZG;{=M17brSGpy)(_qLT!QP8KK{Do}KaK+&lJMW+cA4HGCjU7%>VK+zcjMI!`? z&J-v*OQWW@(U->=(sXdmTu6`pFeVp$k{noykePu;|wJ*9{ABz5VJ{0|9hoXP& zQ1qW2issm%sMH}Ixrd^%9f}(4P*kx)QKL;!AyCvLP*fEtY9~))W`Wyw4fb|7P3Q8Upo}_vqRCsb|_lJ4n>RF zp=dEX6fJI3w1hy>k^)6b2^1|YP_&Fd(Xs+X{RN7a6DV3kxfNDoQUX%zmf_6bq5epJS{`e6sAgYT z(fS>Vu{VdJ4V(`}8``00BRdprY=@#v>`=6+9f~%yL(w2R6m4#YqAhHSwiGDZN}yxu>_`-*L9g2>yL(!3TC_2gxMMv8d9V1Y5tU%Fm0!7CQ6rCVYbfQ4fNdiSD z3lt3%C^|);=v0BC(*%l!2^5_!P&8bi=nR3P5duYL3KX3sP&87Y=xl+abA-C0!5u11 zw#R zq3AL@6kTqIqAP5Qt`sP`N}y=0K+!mXqN@dp#tRf(BTzI!py*nGqU!{Tt`{h}L7?bH zfufrPif$GtnkZ0oi$Kw>0!6n86ipH+nk-OsyHHm&szYT^0#a+r@4G%f6fKdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6DWFKpy&mGq8S23FA5aBBvACS zK+!7#MXw4Jy(Uofx=>eiXNStg2}tdn{NR3SC^|bUdZR-%`^t*m=}_D?B^15ud?p|0qy z4wZKjklIuE+dke7Maxvv__ISb`^t*`?NIzVH5C2ld?=b@hoVx)c;p_6%62GfutQPB z4n>W2C@Snw)MSUEs!dTlfui;TMI8i+Itmmu3lwz{DC#Uw)J34ECQ#HOP}EhRXdZ#0 zZURNE0!3{CMe_<2br&d_PoSuWKv7SDqFw?;y@k4>zdKaszbh#^y>Ei^Pbj)4KY28N z$7=SK6)n`USnHlp)Yth?)Xxq@3)`V+5jzwuYKNl5>`=709g3E)L(!6UC|b& zWdw?r6)5U2P_&#t(eeUC0|bgz5GYzvplBt5qLl@TRuL##RiJ1!fuhv~iUtZ4tszjf zra;kJ0!3>J6s;prw60KB)Td)*zXYTVbNLea*~ zhoVjFP_(HXiZ-)D(I7h%ZElC6E$mRVr5%d4vP03Smq5|p0!8}>6zwZew4XrH{sKh@2owz# z>WVh#Sh+O;soj@#Rq3AL@6kTqIqAToBbfq1NuChbX zSev480!3E~6pa@sx<;UAfOWv9eMEQhPMtp&lKI&dB$Rrgp4mUs=(;9g7_w z2}RSK4@LLcq3C`)6g^;vq6h6z^pG8j9=1c#BX%fy)DA_D*%VC|D0*C==m~+MCk2Y0 z5-56Fpy(NaqGtt)o)ai~UZCg&fub1#MK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd z3KYF1)D_*`u`)CPsWs$h9q$Q6jrj}H+a0UfS61|X$KvY8LeU4#hoTSdQ1p=Wbd&Sb01Fsm;kx zSHBmEF3*bo=~&IavZ7LR@%iJSsN5Wn(|9f~S;C~CArQDKLoCOZ^W?NHRt4n^(l zP}ISusG~qpvp`WNfuha=MO_4nY63+q0!3W~islh0>LyUsDp1rWP&BVVQFno&`2>o3 z2o&`cDC#9p)LWoveu1I|1d93ybw&Smth9R~De9G@XfZn!EpCURCG1eNq#cTuvP03*b|_lL4n@n_6!jMrpfj*rDiHI}{yfhoa-{ zP;`PFicYjCI!U1DWPzfg0!60?6rCzibecfXFoB}e1&W3X6rCYZG(w>0Oo5`a1d2uq z6rC+lbdEsLxdKJ!2^5VIC^}!D=mLSF3x&F(Lz^q_B_Oqf^ZTw33q?2PCyz!qSF^9I z=#u8*?-xSRrOt<<%j{5exgCnGutU+6b||{a4n?6g?wQ^sGS9a{@)r3lzN| zP&7lJ=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U7@aMT65)q z1f*8ZKV$a3P;^;`G~R2jW?xy+N6p2^S3=Rp&WEB;>`?Tn9g04)L(%7UD4J=9qA%=F z^ran&zOqBn*EU7p2o!xQQ1m~6qFDk(-w70bFHrP@K+%r^ML!7?{VY)Qi$KwAfudgp zihdI)`dy&t4}qdT1&aO>DEeEV=pTWie+7#E6Y7dSXs%33Kx!TGvyLBzqMheSV@`85 z`^t(cor)LJ^Vwb3?O!SyJN^HU^b0!_HQAx4YKNkBb|`9ZhoTO4DC%g3qGmf3b+Rey zEKt-%pr|HL)FM#SRiJ1dfue2#MXdrwZ30E}3KVr0D4I{8sE0sNPl2Ld0!6(Aislz6 zT0o$vk3i9a0!0f66!jJAiprfTKPMoyLHVuL4V~(b(Rz1FqhF_L_LUVa)~T51%}}(s z^YOK42|E-mX@{bv>`=6{9g3E*L(#H!DC%#AqUG#Rw7gBx0D+=wN}OLj;Nr73zvM>r^>40ja%|UjZ2u zihj$lqaD_%ntf$OM|CQ$c{dat?R+RY#tuct+M(z;I}{ynhoTegP;{alicYda(aClw z8fsH?ia^n+0!60@6b%z7I$fY>xIobv0!1SPip~@$I!mBvq(ITx0!8Nt6rC$jbe=%b zD1oB$1&S^ZD7sLfXtY4lMFK?^3w1?DbgDd=fYjE@Uw)1ZMSpinV@#)N_LUV~-l_QF z{ZMp;^P%WUI}}}IhoZ4|C>m#nqO0vtG~NzH*Vv(Gf*p#kwJEwzpy+ymq8kK?ZWJiG zNucOvfue~5MYjkP-6~LYn?TVdfuhL*MYjtS-62pkMWEpy*kFqUQvPo);*3L7-@cK+%f=MK1{yy)01l zia^n;0!6P06umA`^oBsun*v2|2^768Q1p&K(Ypdg?+FyWFHrP>P*?Oor^;3dNNxJO z3C@F|=%)N~$cLS(*;iKdX{X}IPeRdW&WEDU?NBt+4n<$sq3BCH6n$lfqOa{x^o<>g zzO_Tq|7?n82^4)NQ1rb((GLPeKMEB6BvACTK+!J(MY9EpeibPCO`zy^fucVIivAQR z`b(hbZ-JtJ1d9F@DEd#JXpTTpsdGFqr>HE{6@A>Pa#;dW`!v5v_LESwbACCbp>s9+ z%8Hsg7t=lqMOEiRQ9C;nwYNi22RjsXv_ny|9f~^Hp{TPRin`dLsAf~tB2d&-plBX} zqHY33tpY`D0!8x*6m=IUnoppphd@zJfuddlMZE=z<`*bhK%l6PK+%E%MGFZO^%W@U zCs4GoK+z&XT~TA_$_EKZ?WBB%y69Ygq`!OqQK5@=u4Z3Z(UP5ue`kiGrJN5%OWUDn z89Nj$Ylou#b|_lT4n@n`p=f{|idL{g(TX-jD+v^>EKszHK+&oKMXL!Etu9bBP@rfH zfuc19iq;Y+T3euK9f6{C1&Y=aC|X~jXaj+w4F!re5-8eOplB0;qD=*gHWTWK7VlhH z=!>MNTmC6nON62|^UEQFI#;u=tZ1vw#d=?bqOF||Mcde+Xj?lJZD)s~?d?#sgB^-? zv_sKOb|~7}4n@1z6zwWdw3|TD?gB-72o&upP_&mo(cS_@`v?^6D^RqbK+*mJMF$8J z4HhUGB2aXoK+!=0MF$HM9U@S4s6f$S0!4=l6dfVd6>ZVEG9&@1Z8Lv@vt=milV1Tj zvU4^2%8HKdT%7YwC_2vhP;|T`=2C)=TDs2z$ca) zHi4o^0!5Prif$Jux4nU4f$a1d84lDEdI4=tF^`j|7T77V3%~?p#?d0jX`&C&76n6zx(; z?iYkv+! z9h?tE9qmxmY=@#wb|~s>hoUZaD5}|^sKpLNUF}dbk4;fGfudG{qBen|c?F8P3lz;K zP}D=9sHZ?tFM*=o0!8x+6fGc7)JLFbL4l%$1d93!6!jA*T3DcH5rLvb1&S6EC|X>o zE2?&>Je`2lhUX_5+jXfw(mx`khGw1z;@ngT^@2^6g@P_&Lf(YgXf z>j@OCFHp3BK+%Q*MH>keZ7fiEA=qcFu>Q?d?#sgB^-?v_sKOb|~7}4n@1zp=eh-6zyh* zqTOwZ_7EuAQ=n)sfug+yiuMsG+E<`xKY^nC1&R(3C>ktKG(@22K!Kuz1d0w8C^|%- z=um;8!vu;B7brSHpy)_}qN4`=2C)=TDs2z$Mq6oe}|&+&WECF>`*kp4n^16 zq3Ak06kTtJq8sc`bfX=LZn8ts%{E071&VGFD7sak=r)0(NdiTa1&VGLD7r(SXo^75 zodQKu1&ZzxD7ssq=pKQhdj*Q72^8HYP;|dQ(E|cS4+<1LBvACQP**gzOXZ^kq_%vT z#kf#(f4-CSNSA8%l@&eSrI_`*krrsze1qL&1UUKS{NMWE?Us7Y4qOw3y zgFsP5pr}!xs1PV>5-6$)bwyuvsT`Dm)V|EGqkS2QUdsQxwX0RLudJxKR-D%miaI$T ziaOh&sEZwnYIZ1Uu|rW;I~2`hhoWwFC~CDsQJYQCyaGkt1&ZbqDC!|l)Kj3Smq1Z( zfui{ZiWU$k>LXCJpg_?=0!4iViuwr@Ei6#9h(OVz0!51n6fG`Lw1hy>k^)6b33Wvs zYLzJoNbTu-SEysH{z(6u`O;XrR?WV$qUCDEtBs*(dFMmX06P?|V27d=?NGFm9g0@A zL(wXBC|cDHMXTANXmy*SfdWNq2o$X;P_&jn(b@t<>j)IBD^RqaK+*aFMH>hdZ75K* zkwDSL0!5n$6m2R{w3$HBAc3OI1&X#1DB4n>Xe)uDt%bUxWown+5|G*v`E|7Zp=k5` zYV0<(YW9^C?NBS`t%jlI~46=hoW8WP_&yJigvd{(H?dv+S3k2d)XB2 zEl{+NK+(PeMf(X9?JrPtfI!h;fubP-MF$EL9VAe6ut3ov0!4=k6dfi|bhtp#5duX= z3KShBP;|6F(J=x=#|ji3C)5>fSE~$6Kx$L->uB4DqK~_#aeS?sePu-_*NWZShoYg* zhoV#LP;{yticYgb(J(s{oo`-*3P0?8bMI!}@&K4*-N1*6jfui#S zibe?(oi9*yfk4rP0!5<*iY^i;x>%rSj6l&P0!5b!6kR4zbh$v$6#_+93KU%>P&8Jk zD>|`O8J>XDdM%jXoD_=A$xj}Qt5vhFtY|{5xV~d3y4Lwnbe$cFuD3(c4R$EH(GEp7 z*`erWI}}Z{L(wgED7w|A=r)0(NdiTa1&VGLD7r(SXo^75odQKu1&ZzxD7ssq=pKQh zdj*Q72^8HYP;|dQ(E|cS4+<1LBvACQK+z)tMUM&;Jtou@jjvUnO+ac}=9lrW2}OhQ zH-t>DRkN?G=&4%qO{Y-wwDY0p89Nj`Yloue>`?T)9g1GCL(vR76uoGNqL=JY^s-IS zD*{EY3KYF2Q1rS$(HjCqZweH>B~bLXK+!t_Mehm}y(dugzCh6j0!1GR6n!L6^szwE zCjv#E3KV@NQ1rP#(M*A&FNC_HCu)_>os*&&`6;3&L(zHp)z~j<)$A)P`nFaqTMI@1 zb3PQ!vP02#b}0JZ4n;rMq3B0D6#Zm}qMz+h^ot#eX4@3~Dp2&BK+*34MSlns{V7oN zmq5|q0!9A_6#Xku^q)Y{9D$-zOFV3+s4P&_AW&2hC~6caDg=s}1d6HxMePKN+6xqQ z5bBD)u2r^6Kx*gackh1_iU#KIN9)*9&AzgtE-l5eT|-gL`B2nihoY`_D4NF(McwRB z)M|&KHair}Yloulb|{+9rl^NNQBQ%QUIInE1&ZbuC|W?EsE?$tw7OsLS51FEtO9aklOnB!To?x)R_Ny+rFimePu;Ew-n`h zL(wkIhoW8WP_&yJigvd{(H?dv+S3k2d)c9AZ#xw2V~3)BZHo32DB543=m3GD!2(4? z1d0w6C^|@>=wN}OLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o5 z1d2`+>WX%3sVtI!)TZTo*E@xx(n4vR)Kbm9vZ7O4ijC$AMW;C*iiX*t=yW?24Yxzl z8FnZdVTYnK?ND@<9g0TUq3CRzqH_d_&J`#+PoQX&K+*XEMHdJZT_{jATA=76fuf5A zipB^OT_R9)sX)EsRiNlDfug$witZ68x>ulRnn2Ng0!8-=6g?nN^q@e|Ljpw) z3lu#fQ1qxk(PIKd(*=qi7bto{s4Kd*r7|@Esr7A6aIOnQC*~)zpKPgSUs=(!Eye4- zL(y~2hoa~0Q1pTwie}iM=tVmey<~@?m+esWiXDnxwL{TsHbt)s6ulu(^rk@3TLMLI z3lzO0Q1q@q(R%_#?+X-tAW-z7K+#76MIQ?keIiiwsX)WZFjsr-?E)Q;+z;5-wGj?3TG_)SYS`^t*GYboaI6N zihj03(Jyu=nr(-oU+qxzn;nXNw<-EVpy*G5qQ3-+{uU_uN1*6mfujEeislFumAb~m zc8baZMGXQ)6@j8gfucg7s7auxDp1r;ps2k-Q3rvdjsiu^0!5vKx}yKJRMt#DYExSh zoLQmh!TfSa=dRW4D=X^Swb*l^P&AM8p{Sc3idyYZ)MkgGdF@ct-3~?b*`cV19g2F| zp{SQlQE!2w`2~s=5Gd*+P_&>x(Lw@6eFcj82^1|XP_&3Z(V_xHiwP7hE>N_DK+%!{ zMN0`3EiF*Aj6l({0!94=ik1^7T3)Cts&%c5NI+^k<%eZ0UF(nZ$0t0+fUec-D=S*L zYjI=0P_&Bkp=eb*6s=~5qSftCG|&!3YuKS^O*<5=Wrw1*?NGFiP0_jnMe7L^tuIit zfk4rQ0!14M6m2X}w245`rUFHq2^0+yDB4`0XbXX&Ed`3U5-8eQplBO`qHP6=wi77Y zUZ7|PfubFSx}p`kR-R8lYWL@t&Q=OVljc5P>srmevZCF(7XMo$6z%SODB8mgMSI$z zXfHby?QMsmee6)QuN{i^vqRDTb|^Z)rf9H0(GY>60|kl>5-2)Ypy&{RqC*9W4ihLk zT%hO(fubV?ijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5-2)ZplGO2SF}slN^Q}k zXheQv+ODDK+5BCNr*y4mUs=)VU5n)w4@JYB4@GC#p=g91iq5n{(OGsV8fk~3v+YoH zjvb25wL{T)HbtWZiq01(xu0!0@I6kRM(G)AE45`m&i1&S^cD7svr=n8?N zD+P+K5-1ugP&7`U=xTwY@d8EH2oy~aD7sdtD>|)fWrqZ$c0-!Quu$}I{*hSMb**M! zrEaB$qHp_amnxT9mrnP(ORZa`A4l8RdSrT)q+RQn^bcWk>pkgCRju{y^yREuYtQt9 zv%9zMoly2_y*a&svQO)G>0Va9)&c1^)GXF|;)12pQmv1sms|R`7K@ZhE3|I5SgEv1 z>qSeHN&{QpUaC}DyS4YSrPBJX`z}{1ZQOdxfKq8t>kliIN?WzAxJs$CUF*rKl}bCc zP9In*?bcddt5n*nb@O#frTtpRtXC=xX?=HtQt6P^1vV~~j%eL~(^Bb}*4qY^N+-1b zv_+{jv~}gJOQm70r)*m)jc9#h`%>xb*7iG@9$A6UD3MW z-lfvG*1`LhN)uWq?_Vn2(E7{ZQfXrAst1)ylUh$Zq*R*H`qW{i(%r2ck1Un$Yu){zYZ&v-e_I@j8f^H*3-`{ zl|E>FW@M@KNo%KbOQo5u+m0%gzHYtpf>LQ#>&K%@r5{@t9#bmKZaw(YQt6M@J1;Ml z{%QOD%JlIsx2-WQzeTp~jPdDjpxpM{g!ETXZtHS=`a3AMZGU6>ODMOEy*d3Yl-oYN zCH*y&+ZLUa{vOJ0`M25kE4SreN4{9OE&o30rOIvj7XtS$x8>jHx7^0#VVQEtoMYdfyo zmcLnYLb)w}x7!Wnw*2i%6U%M+`%Na5+wwOIOeweJcYNPnZp&}ky|3Js-*fp;xh=nG z?y+)Pe%I5J<+l8`m1oOs`F#g7%5C|D<5$XU`IWyn%5C|jn|I1>`MLKG%5C|{(@)B6 z`Pr|T<+l9v#n9e)GO6O!U{l6WNufeMEC%ev{#%eK6O`pi+)nlBQ$G{ky=c}+rjFtMPv1W|Mbcd$A zR*aL=*Msuf_0cnZww3bjd~oS<(z#VbyAw-2(`Qs^aB4r)ThV;LQL-bbV}$D}ho)91t73v6EI|6Sniae?d9TT{!h z8SmVFTDruhmgk=_dU1@#7Dt3rhc!d+&Hy!`#!CO}zB{lS@56ONa6Yci#G;e9dRaqQy{}7oV!m>> zr~i^a91~pV17BSB+$rfoi{?H1j@)zZb=!8SDTC%-x3i~>o;w-o+{pcI%nxtEK(}XD(rR$k)WqI=Pt#dDF+#3@gI;GU}jdbYobV+ku zQms5U|FZ)Gk0mwYQn*8jYzWzI9_PdaJtWnTW(r1R5%OCP!yroB5ZUCs2N zTlUTVLrOgtN{8~z99KV7=`bVR%w^(|Uh%(l(QE50HTQxhOuuAy{Z?MnW2=Sd-pcvzD_2Tq@~!;B1F zA64qPM>>*k<+6@^T)QOQ$^%lKdn=EMi#)Xc=jk)#t8?zILz{lh4=-igO)VFFboM*x z_NH6eY5bChlzNUxhw`l)UO!anFfm=Z(Q!%BT+%C#Pd+zYr}UTk#Mi^7W@<(AcBlNl z(A=9j{Nd|ANuT>yq(k{;&TvW3rc1gmJx`oJ@}=eDX3l88`G9mmMe|jS{nAG%U87mk zAD@=5QPatv-*)zlYN_WV>C9aF&h(jib-JBTr#$y|z806cL;cU2S}yzbyJ_`Lglq4+ zZcmoZCvX4eO%Ibm-N#kk50&!R5WjY zaoYlOuil*>Ka+u^57=Kj?6`gUG)!mm&7A6T5|vWAN0o2omoDd#v)-ScKVIqctgZQP=MrlDQGQqMtgIcK<>zh1m~ zT>Wx(nSFH@n?8WoPPl6BUqQ=rBPLHjwbXN)bSU4*%U#g=iCyN)ULn|pokefRgPPAm01DILkT@zXfcd{OPcbQ_1KJoh$U5Et2Nh0w9k zCBr++y~yQP9G*XHMf1M*uCeIckJ^Fjy}Wj*=lFCY-@;|(69zG8t+@fY3=Oibxuvi%2S&bW&)dAwVD?1WW<~Dx!j-qJp5J zq7*we#D${o!t*VS^OX4V+^Og@nhr+HXch>sis@Sx@V!!HN9- z;1jmP*UlI%Ly_#myYE>qXNICicKf!nggqk1NNl!ml1wNUf9L#;aUs$mY1%tiefxzS z%7#R|(%e*ed({s!Tp8`SP7^!6t>=0k$9g7m{)h2*wKVDHUQrXROI8Wm?&(;@a@+18h^nz>w!4sM6Bnx(A9o-BUhYQp4}K{w|$J3lP)@#hae zYA}zya>I3cvIvV@zwo!c+S76b-I_Gmh2R zL+oX)=3T7jRy#i|^5ZQJzi$u!#=dm9Zjse^ih7-CR&!*}s(WRW`vR+Z*p@MeScqKc zDdsP6J$ArqB(d3?b~2$&`y0#1&@)Lg-Ng3&ad>}yc=Jtq;th*@@Vo0S*KG`oykqMv zm&&0k8~Od$5B@mM)&4purPo)5EVcTo!}rQCC#7Ec`GyzuXm*;ci;dIMhV;zizb-xB z)$s-?v{zSk7uI<-OCS0E#t-c|dhO*K7s}eD^ueE#2T5tCNo~^B9&##>>r8Fu7F)(? za>lUU1I!8^e*K=~dQNeg#D-lY$B7hadS!m7tG!+xekO!(3wa z%GY-2Z&*h$kIIDphP4s1PA{JGO){asVO_=CDK+VDSg0q=<&JcBZx+?q)2w~7 z(&$KcM6}Bl(#_Sl@eqkzE>CNhr`e#!r!^kf*dHbLjhG|nBB!rQldw>?r`eFkjb*l7 z%q^j}hm`6dTM}+29GA;yCgf_r5h`?Sg^iobsuYG*)a421dK))x+PF#M z0a9PH=mtwQm!*PQ7Xgd9BT=PTZBz?XY39~f8HFmbR7)x3)VHHmQ`t&gb89mpTM`}b zKBFzydU9KTRHVB_*w8jNrnc3Uv~hx36cYVJs&r@DK7Y*G1!vk*?XS4RExRHqN^9wG z5aM%Vd#CwU%&=RJl=pLtPgvxM;Ob6$#~`t|RWk)jBmwex)82z0o_oa8u=2Q{`}#1*mfPYMokPW|XLKUBg$`ucCfRdPg@yMXPqZ zN>yyVMJnc|*j36BA#!mpn{0lx8$w)(tFuJ2<=5j1k6FD$CbUz;3=OnVmtqZacPyp! zM=m{C#wW+=?0A{oU{=DEstMC(O{_?m zUOu66O4a}JX4K5B3GRu>l?f@;6K74Snvpi6x*{&n7jtT>O_$gnDXg9`Rr(`aTP7Dyn^jX*l+rJ+FL#q{?0>NK{}~8om)BP4zL2BYV$^?N`~)SvY+}Wv z@>$br%WCJ&tf+~vRCWb~iBqa-#mLR8;8!+b#`Nhks>;e|PLWKoE>6oRlTMkCW^&17 z&?BBxbX7KTId1uudIjH;>~@@}fAr(H!#tDSPAgB_cqe?Y(&?{O5;eqWktDt2nU`(0PI@I#3u}i3 z_mgdR_mi9!o_Vr8rvGfm+J2PzZpWw1ZsRn!o!K3oX>7ci86q9pL*fvrJ6bgcal(Hy zcC-@D?08$7r%{a4!BnqN3!Rc}FoD~N@idi&i*bi_<^GN_7W-Q_t9M|x*v+!L#R-$$ zQo#I4Uz`IGA|8lY+DqWnIKd$7Tf;Qw| zEM<>Qjw00De{BO}`pSVn*B;LQ>Q-te2FA?>o2LVB;5d39a6oZ9=_I`qF2{YCr|ICy z36q^@@vUQ>?p>Vdj*=!gttIer2>b`fnXI6#E|%j&`?XMlsm3SAsg{z4QN?b_;81LH{fJBvud+2BPJ9rn{hGiLgEP zPrKYK=Gp3!(cAOfMRsr6Y>UZ;21Q|VOq%`ie~N~TiTXdR#s7QsY->62l&Qdhyv%gt ze|Ibo9)%MOt3qmPGm$X)^#8f@#Q(~=TZcvIc_hL4myTAan;fHh4*M&Iw$lwKyuY^a zf2wBL#K6E}PvZZ9_Waex>o_O$bnjMw7L&s~nAd+g>gg56pOa%R4D8wUuQy0eTmQ}L zod4TeVUCGzAs4pddFWrk!}L0eY7&52^G4iaw+=R_pF^1G6 zrXIb5?&OgxXyL)J(HWYg1Sdl@Nv%&z7u&_nWJpewDSKibw8;OTv|#@Ke)tdf!|6_Y z0lP;Rr+p`38dq6=K6bhLIuV{L<_&h-o?}kD;_dlye*EOWUO~&=Qgop_;+Mxscbq@i z-X+M@aI{`JH@v_*;Xy}4?~wNL9$98_VOd5|QJFt~L`tqdy)30@SZQ8Heu;}S@-m8x zQ-)=fl@t_|p>Er>yE6y({D=tkfPAl^3VwnY{`RQh{{sXd%4s6iOqKx9g z0%@VGsgEqfzRM!<>$p{qr!La{|3K(x2%sODQz1Oe@IG&qz~R40)M- zw8P9~I*=$XO-mC>1Eq=V@Y0OZjIvDWslcqllp=r0=zvwI^HTChW7pMJVRl<_L9uB; zx=0p4(bruw-l@*s1NS|g1j@XB`ZyHn*bUXz%81$s%nl+ad6lUZH<`L!8 zBLA?gl6>jWvf_-A5dds<9Mjz7KK97zYu0F1p2)}?OePY9v9AVTW|DMYpfbXmcOjH1lkf{`b#v?zaAVAvF{ zQt|=|_zPt)!!9nA;UsuGHJel{Bm@S@-hmEF4eA`-LG`P)ya&ye9U)y(mN6K5KHJ=&(gGl(ju9VV=Ob*pH@HW8%lLB3v^vl@4x{r zhq|j^R&9EDZFyNq#T+}#B+0=zan|(da|0_f$3{khzu_^&X2_VFS5Tz;Mh8uMK=(FB z%d{C)lVfBAGg%*5m)ZCvnP6Gz(BgvnbC#Y10`o8k7iHvTn1NagXEcP$?sn|}*|Yvk z+e3CO{esqF1|i*3I^3C48(P@_B8~uMDQRh?MJZ_*&jRhql9S%Z6xq-ce_n>{GE>KZ zz%EYhtc-zB^Ev=v|OU9`{0rpK^LAq_dTml4U zre);jmgc4u3Gu`H#R9jUx40psiUWXcW1vDdkmVdMpJh^XKMf3`@zyAt$H&bQu8Z&v}OT!09PyFDDIXKs->%lA409 zxYD^owSOCMfRmY!u#;tkLE{eqUqIF%zQ`1NHlz zYaf=9mzPq%b|FzNu-F}Pq?(o1AI(WghKgbNr7>v(2gc|}*W#06^uue31A6y~=}}!V zt)jf9;*^-U=@VwoI(@>7>e`AqanqBNC8({OHGRD3q-itCYvbgTZ>P(#KT!i&a?;G% zedB6o#!XD>CrNqrgv!(9qj0ka#7&Q%E+3{lbz;rTQzy-giJKe~SI|2qPCjFG`UGh} z+@$FhH8tgvE8?bAR86j}JUvk&du+uiA>y|%uD@zx#T-*b za)Uv%{)pGZCV*Z&!E%<7v7kh*HucmUSb%%c+!odETsgMVbNJvWT-N4ClAxkCo4-CPwI|7x~_nBV8m7(Ko2{~7q3E9~; zknt;M*fM*){#NaTD{zc}4Nn+-q^628{ghutb+xTi?%e*QF?P5v%1F~z+3V6IxdSyt z8s4|+*{1#iOzu{3H0s^A*>0IYq_@W=k_%`vVecAElo(h_4p}qPCLBtGt_aO_tlaM4 zf{e>2$;JisPEY~8z?1>Ypkb=6zYh%D!1lvh?X4TvY6tL)yh6DjtKY$i0}|`IOrIA7 zpFDJHf^ROfM#>|Jv>X{p?RGXeka$4oHA|pMhQW8v|HVC8ra!Zw;SFRxQ|T#b=JT5+ z@_Eld{eeOFk4KE$PfHh`qX$f2aoY!_`6(mhc+mUfz?`5iPAQeUZ@DZBzT4JIDR!jg zX_(x(*z20W3V~J0SL4&s0Rv*3bOoiizvGyU#^VhkpowmR{u!JU*eZb z)G-1>S($tgx&8r2l3ZiU3e0Uq;NF52=;#)V7;}P>nUXF~YfiWgHW29M4-@hOmoD`; zNa;9PCdustH%)pW&}v>JH#h{e2s_XtCfde>}VNnFsV0l*qHj7JR?o!ijayezYP43}>dRfnvdLvU-JknnxbAnF1yxB{te{7H>!?~-b zQZBFpx6OKMXI3ERaxE;B3WxRXom`X189x#pRRUd+gIhO%KPe*2J5@C+=* z&XHS)(%ky%6g?_<=@Wc~8+g>yn~!?*CXgM)%JfpjHPsA}+C;qv<08Q~4DtxopC&_% z4E-ghp8`u2%bl(~8Nl5?`z`2CHvV0IsE}SUe%55uqk2EbM(Popl4{wqkC{1#TbL=g zX>vzfmYJJUTwjiJOAD23eN@0F=qKDw1@=u^W?KDzNzw<|ToWFE;KVAum}H;AYlj9u z%r>`sCk!w37oX`F|KRddckt*8d+W=4zJ^1D!Yfxd8S(@}9U zsIs*D5}b2_A2*w({qYQH@6NcLfyZ*D%KGQlN%9me_)w~U+M^q54+1kpu%f^{z1A4$ z#$et8H^t~%^GMmORt|`N=N}jGZWcqXE@-X;0MExaEad8^nA8OFSJSs@JJY~g| z$_#t^V5GM_LpNv=8xR=(1A8K9MATbTF345bBPej##F>HjoOrIbw>+kA^f9ZsiL*OjpYXEo;GN&#O&V-wX?{+A!ARQ+ zysOfu{93QQWnoRJ@=ROau`}q?4w+>Y5L^UOxP=Twnj((h9|YaVHtcRnUZonqrl7C(I-ACHP>dDDZv*$EWt&!B|*14a^^+P+tZWIw)Z7mWud*; zmj{J`J~Ld&7{kX#^>4Pw0l^&^*rmZl){n{hpgj1^E4I^aujw!8XVY;F?>_3QkoQ-4 z70AZ&{;#;SSl%+j{r4XpmFiQ{6W$i7-w54`|y z3bRS}fxo_kc;b0N&wu)!JI6J?XUmeQxheTMa-?U-GrAKl$aGUqT)ckAc3uC4@ zI@?F7Wo5h_XT?E-eO6J9>@0f>`en!0KNB38B6s{8b5AI#kDc`VYWt`DX{jRgro}ZZD9hQ=XV>0-5%Hndu zdeidK8$7wvdtJLH&~tXUU?a>pQ2dYHNkwO}rGcv}duL>-)u)`S%$%R{Q|dnxp}X^h z_Q{DS@V=#XG0!~pb=Vy?vY;pjXU)LXMUs7H%SC1E;d?C&Z`Cs89dq90=qEW`!_v|Q z#q`kk6H=I+6W!}rf7CTpjUg^0iM81t6WuPoou78T}a?5vHx|{)VdGT@& zlkWZu;JXoQ z>cKZ1a2b#O!FbS*NB&q`zSt$`C)6e1O5zF)EN15~3GzDs9{Cm!`(x)9%J&b_>-4AJD?5UI9eL!LL2RKXihB<^=!B30}U9Gw`GBQlErd5bvs zw44-lTKs6)vX4Nk86|wNURJ+PI0m0X)N;&;L2QAk`Rmyczm2y4dd#g&hA@E~V zrQCQ`DOZJjfvS{S0>464%H1Z1kksqOxhs+1tSaU1g1=u?%58$rm#-AlawAlw+;~-4 zU#)64*&fWl3-dQ({&vj&4)cG){16!;w0uidDL-GvDy{!ARjL0vRhhp|Rpvj7`8zQG zEzIAK`M+U)m<()MUcPn6lpC)q^<1MWyy^FGHR>+)B3~k7qRt;A<4B{Ev!NG47ecRsUI)Dix(0eT^g-xj(9O{2p)W(<+HFPd?0rYa{ zHPGv!tDv_-^?ak-^DuN1^f~Ab=xb2@VqIPSL+F0!SI|SyW6ChZ#5p*rO+#(%b@yQv%36h=v~kUppQbI zhHiuIgzkdA2mKiOH|RIeBhX)2x7_n+`x-%8 zLc2oy%k_%RPlJw@>kIW2(DUWIul{oAt#T`({$A*Fa)MX?3iMOC(NO;_^dy;9pA4NQ z-=U{|E_9=ONxS;zpmlQ1pdL$91>{f*FFRn~t5ZGEowU7=%Zte*m1H_Q5mpa>(7DSagFs4 zLl4RYuD16WG;z80r$c97Z~djv%{N-V6B=@}_06GKtE?}DUUQrEw?KEVvHnwNyW6cl z89MGx>!(BSy4(6kpx@kU{m;Y1!TMLAp^sP}3C(`Y`jOD3Pgs8| z^j*2o*Z%no+F`Txr$EO)YyAx9JzK1Q4Eo(R>wkszdBOS==)4!LzZ|+{r}eKv!(O#M z3Yz=6^`oKJ?XrF~bkAGX{|(yd9qUhpPJGY$bD`_sxBdy}p%1P9JG9@&)~7))*k}C} z&~5vze*+r+H|twL^S`wIOz4WQtX~WL;A`u@gvNYleH?VsA?s_P_aC9{?FE51>G(;Si1b1&_=&m9}O*(r(8P!Ea(mLO|0r~hwhdCsG|NWXcxIb zQ=b5>^jSX(`e0-0pN1Zl8#!Ix-OTEs2&==O3tCuzHFQTy>)(bpiMGBiv`B6QwZ1aw zO8H+c>hFYpEdR7c{nyZLG1ezRr*^UaJm`jQ);|ONN&c~mmiL@&b?_-x{m^yt|B`h6 zL(r#G9hYk-{BG42@~?oPA0a;g{|)p9li zLeGJ&hCTxQ68am|EC1j?>p2Zt09^=O34H~+ANn=4qx^#a(|%|LbT0Hh=r-sp(BGg@ z@; z9{M757j!rDBj~5lgV67w5iS{jWjo}Np3(MDxm-71F2jxXgeF1zLI*>KLbIXyP`S)B z<;OxNKqo^lhh7D}4tfLhR_I#jeb9%Xk3*k=Zil`EeFOS7^jqi;&^qXGsK;&FE2k6F z?q<*yP#JbjF2j*g!O`eIXeu-lS^zDE%59x1L^_@QF4mNn+jpa%hFCTGBU;8Q`0>>hvu$-Yk#7tSw&m6O*Lql?UE+_)H2uDB)F>@>#p~Bd%Ll20E1FbYK3x_{ zDawm4udS_~GJaOARQp$dlv(NCz`J&RPADi{YJOtnRhRQv>pF2cou@x1%Wt^+{*5ki}}^{mCG;NAd{|8IsYD$r=k8POWdc{IZNpx_*_fuYWlx;N(RoEcZgL+ckkRgXWzt)4}WA zb&p&A#hzWS=3MVJL1kpp)g#~SiqQ%DuxhzQYEa+M_3{rQCDVRsEWfO8txU6wOuDk9 zK3$GKoTp<&aQg~_>XXMGf%+biX_nDCMoE4B6e9d^o{llW^^KGIv|qJ-&E=Qvdrqdc zjPjsA*GzG{uIy%~^;PHT@5@jw*XA0xOUFz8a5=d(XwbfivfKbJB&zGxA05+z+gBO1 zy@EraeV@y;usl=5{H&7t2GNM>di6(@$BOzrvfNAwWEgU_lV4r0_Pef=$A(P0vX;4B za(fZ@VSSO31TQy7+IKXtRQ-DSUG(GQXC%bPPg4KHeghJF59mEmrV|sBf?oUe>!WVK zz=6GW$#IP?%E-;M|0=;&?3Q<=xPDFc+-aO+kM$m|wlbo|eN|VmCI8*JO-WIQI)$ek zI(xyepFGJs>J}zecJ*d9$!wLmqb~g79d)5en{sy4?Mr-Drd+4~`oXBKgDQ8_xngzB zMl2^MRZPvmf+7lqJh;)kJ@D4)06bQTI(^L|1(sC9k1L>vBG+ zTX3D${{9Iytj$@Qz0SWbYiCdmMO}BwQn%$S&)-?MJbAR8J>S8vYB@>Jg9KEAu)=$7K=%Ug7vpC2~v`SCNdcA@QW zibf=DsdFX0Syz|1EY(gOPqgYXa}K;YAv>z_Hq`QV`Ow4TlebB^fftC^U&|JQ^6eViU`-vMF-B8mjoW37$(1*|pFc8m@-L=OhGZWp zAL1X9b4Hf#?}DQXJV(l<*UvpN<;)P*4;hya${Cb>n*TI2SCgmXq%U}NGmGpPF+|u*C zdGot>eD3p(sXJ#*&z_bzXG~0Jc&O|0#rr}$azC+X@jlmr5ch(NCQDtbH-7WM;m@yn zedKpJPp!=P>52HOZ_GOL5%;2{7nIE2dDd%ZU6a1|=VfCT|5R~S?AxJFjJYPXNfUS1 z*9M(jSbp9I&ZzS)e(TAEkQiyhi_gcoZ|`%-Q1{x-t!~W>nbr66YajP?b-Rkk-TC|d zM<#r}=Fy0=+|p!MXV=gz=;fT5x;@Y4Je&QT|2dP5>iVMe$1^$4=D!$p+&*pQbvap& z4lS`M`$_+kIZv7N$((|tJ!dA5J7)UkiJT|0H~BZA{z0bxp@)A@UZ1T?1n4akHj_8_ z@5tX(Zuv{L^c`BzM2?Wr1xMRNe^Pf~|Bkv2OYfF(;+uVUXW#9YV|~lrS;x#ijEGJ9 zX>#?7oFB&PUY8>=*46XZ54u#2ik0Inc6{YE`Ks$G^>x2_?J~v8F|X^)>wfdvWva=| z>pJtg-@JA?$K>X9oq64FUb{>)xp`e@UiX{VF4IkJUe}q|{pPhxmC4QPI`g{Uympyk za`U>*yzV!zyXzLj=$zek3!#glOQ1`kE1)Z(tDtM3cR=rf-VfaXeH6M0x*56!x*hrw z^i}9C=x*p9=w9eP=;zP_&~KoJphux~(BnosWj|jR8u@(Pz8IbvPBk=jChi*JJspR5*FKy{w zc-~j5?i;uE`Yw7L=`nrp+fTYDeblYsu>*^Kz9nMB3s0RicCH>vr-l9e%-tKNhTPYs z>5UzJOuuxW9QV2L6MuX6$~!OGSorKr|Aw`1t`~m##iP3? z9J=s{5%+I+^@roXj#)DF-rr{(JG%JY@k@QTm##nWzAQ(_mX><;>2W?LW_C5nX4?nYQOlZcV|_Yl=sk z_G+s}#g5Dw@rT-`HmI#Kr!sqre~QUkbRBQb+pH~1wm#F;rrTAVlV-M2w`+LLP}64J zo`RgyO|Dy${?pc|fk9i-Kd0Xx)}P#9{khq>IeGp(lcnXjV!DoN+12iuQC)iEoRq&^ zj_K_|XV!GHB*(UhuKlvpV|tIX?ff;^JE!DCn|5eFoSf4#zj%Dj)YTz!{ZyjY zPodGtImy|5{C#kC3|v2@9GNm!uAi1)QgF0S?)h^5{$@+BoVe^bf4p2@e`C(h_KIfY zJ{|XT{F~P+&7D>mQeAPd|JNU#`*EL}R`(sCW8a=@$3Oo1rM}9u-rPHIk8fKcZDsBbcN{n*|W6ySL43VShS(d$2Z5n+I+WO_vkf> zH+ExHQSJTDg#PM&FY|#TO@7L{ciw@=^6xpYboSy&&Cf5=@$;6cQ%m|UAKtj4ED#_}=CJe4%?m!t{Z=-dVRl`!oM%ruSmH3_To@{Aupt@ipTnRE~BX ze@DmAk8^sCQ~k(4)#%==^+w;zKWMaPxz3$xUe}w~gXXp8c$1sg_2%`UdF?sDY>&@#y^V)Ng$<6C}^Lo&{_MB{T^Sa)=9yG5n$n}8E zc|ooRtS*Kwfi8uvfUbnDg06wy0lf!$KXe21QRpVMV`T5XE4^_}&I|IYQ&ape$T6i;m02&; zg`24t>Y6|!pe>`&A(*% zbv+Ze-unB;AMVs~)p_S8ee=Upw?Fs&Z)b$ReP`<9m-ipA?seT$FVt;E z`In%tLU%!TL-#=ULia&GhaP}_13d&i3ax`4k8NvM8rro@_6~V&v3$yhp>poZeC9yi zwFQUVZR}KwoT%(5e@io}4DH$sOYV^+KdCERV3%o{(=5B0zd4q1u*@fBnZyO}d^zyj zp<}fV<~H7b%8PgWaPE*k0~Q_ZFg-D$AY|)XGY3;GFhhb@!`XCdzJi{;r-NQkqpm5O(TEbE!rMW*xG5~eTSe0f~w4ZT1nLvxz7@yg@TE&8A<{BC(n<_`Z-9%_Z?gFX3A zvLjo{GT~drIpJ^1!>h1xk2KjEewnNzJbbC-zVOFn`9|TRq=v@f8|49glknsi`Gj!z z&PMV%wD5~N$6Fab&CT1F}r(@TKzP zF**R*mo{_`Un6s4!fRxWvEg6H zr>we!?~&TNhQBOJb_>sI=5lopKPa_L3|}riTM=H}O+Nh}-d5VMGyF?w^UL9_^@O?YmF9>w35EEpa!veUC`D-RSmhkXlx{eZ6D_H@SVIW!}vq z(xhA5zEfnYj=FtS(%2u}zLNx_pWMF3W$nk@zOK?+b#7l9nKvrLC;toBwK>H1v^4pE z$5$nd_{!tEP@WMV^!VMIsdN60+s*O3wmV535Pl>+DJP~QVm*_cpYTiGvXhWbXyZW|lwixqY@ zg!*cw5iK3x0NEn>e}v7XC+0Z5Jn5ymjxSqw=RC*vtF&yd^i7sElppkslID&-=&KMWCLHwT$Tmzo z=o>FhsyOINmu;AI(C3p@Pd?b_YMD1P((P(=gV1}fPI#njwN5OT-Cm;;hoyzJIuRup z&eDl%q#I}J#4xF4f$Y*ob+YiqI*}pu=)1{{&XYsbyiI6^1lWq(BK zM4aqiJux*}Dm@mZ6USwxEp_5L+2mF_aa7i&t!{Lx>;ifJ-qq+HX?%!IxMdak_l%96 zmV+=jxj9UK-aQzPWm7-2nJz>ZN%D;hUq>B3}OF z&N&Ufv3hCWVE9JrrG2Nv`_xPOhQNobm-d|j?^Q4D8www$UfP!e@2HpdrNW1*m-eN> zd(=z&(&0nICrkS>;N9w_eVOpGubYQD-8?0-|05;~K2G zLMFqLkV<$GG6kN5Oob;Q=fGP+{GQpe|071qh~;EkLJDOpccyuj93^C?Gh6U6gq(|_ zAfy@=gw()-kXl#}G7A=j%!UOa=fQ%IIj|sPE-VO{2TMZEhbJKyz>|;*;YrARcoK3E zJPBClaNc{NytKY60!)Mgj@zsLN13VA&cQj$QAG;!~zXN4u?umsNIUL{8fdCGZ8E|Lr(PopRZ*$fLp zo`D4+&%%O`=U_p|7FZCn6&8eSg9Rba!-A0Quq5OKcoMP$o`k#zPeNXTCm}oGNyy9a zB;*x%67niM33&~kguD(40WAK^*JPw*t<7(5B7gC`+B!;_F-;7Q1@@Fe6oJPG+b zJPG*?o`n1kZwdLx^SkW-h(U4_dLm)oo8xLSldp>8KePC`+7H{-Zby0dt> z>D!8z%kn1lZN$rEc~kmm z@p4(-jJ~yay{~D`K)zAM+}K1gXsLlTF_J-)2GYhB3|eR)jf`Rtse!bzC4&eJq?xT4 zG}l1d*_uH!4Wyyb44P^nEp5Y~i3ECw)0RPF4WuvIF=(WLw6r|~p9a#>4h+IIkd}62 z;MG7{+KEA!2GY{b3>*!lr7;XbHISCZGVo|1E$zY}L;}6n>B_*ZfwZ(60|BIEs1xG$ zWC$RU2leFRaa)RhR*Jg2y^5Dobc)-VBtws(s3*&VqEqQXQ7?K>6h{w=;^{$A0zD{7 zqz6Sw^q{CWJt#`1Cq;c2kfOc}NKroqq^LgwQZ#@8DH_Ot6b)iPicVudiUueS1LTI>P;?W^gQA=1LD4PrplB66D7uv%6x~J-idNHu zqBZoOXe~V`T1QWcZf8J>?qEQQ?qooU?qWcS?q)!W?qNWR?qxuV)-xbQ_c0(v_cI_x z4=^A_4>BM{4>2G`8yJwHhZ&HfjSNW9BMeBeqqHh_HqVE`xqVE}yqC*Tw(GLtr(P0Lp=m-N+bd&)p`jG)C z`iTK4I>vw$)iEGNKQkajzc3(0zcL_2#~F~KzcV03zcC<1zcV03@+ZmmZADV#Wnar7$#4MpKB4~l&Bpr{c&C~8a(iki@a zqNenqs2M#dYEBP|BIrR;Bt0o=!GIJ+F(5@P8IYn@3`kLH2BavO0V!(3fE2Z5K#JNi zAVuvNkfII@NKr=yq^J`EQq-9NDT-l0ieed%qAmpQ7Gm%8Z;{UzI6XqV%9m2qE5s@60gB>S9u&pXgQ5g_P?SgyijwF- zQEz%sluQqb`p|=-zVx7|A3Z7R&wvySU_gonG9X2R7?7gV7?7gD3`o)G3`o%s2Bhc= z2Bc^x15%X2fE1-NAVp~mNKrZiQk21f6lF3XMZ*}7qAUia$j^WjWiuc}ISfcqE(1$Z z&k)Zn0VMKW`OJ!QDk!>2A0Fj}c$F`uXn2ToLr+jt#PXo1m>v|B(1W5P&9@f6rD*=ipDY^MQ1S}MQ1Z0MP&>~(KrUAsGI>Q8qa_fO<+KZCNdyJ z6%0txBnG5tG6Pan$$%71VL*zeG9X3gFd#+K7?7gr3`kKG15z}D0V$fvfE1m}z*1BY z;(1yCiM&ic7~~X!qG5V^s}AuhUrN#J5NEIab-p>HoyYQ^XbwFnnoAFg=Fx+q^XWm+ z1@xfkLV8d%pB@xlL=TD<(37Hz8IYn&7?7e%8IYod3`o%;2BhdR2Bhe62Bc^)15$Ja z15$J)15$Jq15&hv0V%qg0V%qM0V%qc0V!I_fD|obK#HzoK#G<#AVn(}kfQ4ukfIwH zSc+;xJnlH5Xq7&7oCS&o>A-Yjh*$Yiif##Ux+H+2RV)vRZlwoBx6y;5)%2if4LvAY zOAm_H(SxGf=|RyQ^q}ZYdQx;315$K115$Jk15$J^15&h}0V%qV0V%ql0V#Tb0V#Tr z0V#Tj0V&$RfD}ERlby>Eg?>25-8fr@}OuNJt%sf9u#e-2SqQ? zgQ6Yupy)+Q5OcJs4D|f)Qtft>dt@^oy33?oy>p~^$)!`=|6vcVO6nebMmr_*XaTW{$MWrkcibl|bqLK8VXcRpt8ch$1#?XVJ zGwDImSb9)&7Ck6Bo1PSvF(5_b7?7fJ2Bc^_15z}B0V$fufD~0QAVrfHkfO;9NKqvN zQZ$7DDVoZF6rIC>6is75il#FlMO6$)(F_KpXeI+vbS?u@RLy`C)i5AMwG1ppMIO(c z0!ZW#y)G&SMW^W_$XOn*@}(5b^*B2QgQ9sX4~ovG2SpdqgQ5%RLD77AP;?PJC|W=d ziY}%HMVHWnqD$#X(Lx5KXb}TabQuFubU6c3w3q=Yx`F{Ix{?7Yx{3iQTEc)7UCn?L zUBiGBUCV$JEoDH8mN6hj*D)YP%NdZO6%0tx^$bYS4Gc)pjSNW9N(Q9pCI*(G^E{rf z1(3+$dOBM{4>2G`8yJwHhZ&HfjSNW9 zBMeBkuFg+3`o&03`o(h3`o&& z2Bhfk3`o&$3`o)M3`mhH6u0f9$jyKhg)ksR9tNZ+lmRJn7?7ec2BgT#fE0x@uoQja z@jN4dL_VRPFZvP`T`BM7JHAk_@}(5X-*|kS0g9TjJSb{T4~in_K~W?JI)QTPywWbF}(e$LK4FgitmH{bh$AA>IXF!TNFd#)88IYn*3`kLD2Bav40V#@Q zK#ICBAVpmnkfLr3NKtnNr066Dr08S@q^Ji2QgjLfQq+?HDLRz_DeA?56vZ*H6g3X@ zcrt~eTjej4ohG67PX8kPyVUqlukxi7^_IVB&H_crEDwtM(1W7B^q{C8Jt*o=4~hoR zgQ9`-plA?1C_0TE6b+^)MW-_$MMD^nqB9tfqM-~(Q3?Z6l*)hl)5qD}Y2+ z=>_!&P&7p;niJ|(zLcU1LY)n{py)!D2SxMgLD5C@plAU-D7u&)6kS3OiY}!GMGNUc z(IR?KbQwJll!t&F|{kRp9MWLv0L`BI8@ggS$VgQ6E%9u&Pq4~llugQAz|LD4Jppy*Y4Q1lu-D0-b9 z6um(YigwYHqBj|kqPG~3qPH24qTLKg(K`%C(Yp*t(R&O?(H;h*=zRvH=mQ3%=tBmi zXfFd&^brG6^f3cc^a%q}w2uKP`ji1F+RuO#ea3(kea?Us{fz-B`htO_XnUxqTmXsu zS^j9qc>xslY9i*#P_Oc(6n!1)Tv7~*zF~P#^esIo`i>qHeNPXH4$*_6ALv2RVR}$> zgdP+fr3Xbn(vzZ}7?7f43`kKO15)%e15)%015)%W15$LH0V(=B15)%G15)%m15zY^ zmTf;IPm0_ONKps_QsiMkib5HXB8LGf3S&TuybMTDI0I7TV?c@;F(5^a8CZ(G3iaGA zfJ9Ev$JGZx(MG+~Z{m2BFQq8Lab79~MUgBIidxWvq9}S$)RG<)wW0?_t?5BgG(9M4 zLl27D(u1OQ^rWag15(t10V(RpfE0CNK#DpuAVo0@NKq^UQq+Y3DeB6A6m?@jin=o( zMJF*JMJF>LMLighqEi@W@hV?RQD4VtHVPE=V|h^2pB@wqpa(?*=|RyTdQfy4Jt!JX4~kBw z2Sr2ZLD3oXq-ZDuQk24g6s0mCMQIF3Q91)sl)-=$WilW|!x)gFEC!^=&wvzVGayAd z3`kKf15%X7fE493AVmcXNKqjJQZ$?aDJo(>ii#PKq7nwAsFZ=FDB1BO3m}ot=;yBc zfTC)Bcr?QCDql*`7{@6Y1B%XMc~CT#9u%EL4~ovF2SsJ{plBRDC@QB1MdRr~(FA%> zG?AVZRWKk$lNgYq$qYzQB?D44g#js=%77G|!+;b`V?c_gGayA(3`o%o2Bc^v15$J@ z15#AYfE3j*AVswdNYN|?q-Zt+Qgj{zQZ$DFDVocG6wPB`DH`Q?<_aK@iTb(g(V!?# zzS`3{-|;G6O3_7*bMshGw1DM7(Z%$j=n{HRbSXV3T1XFy7SV&E%jiMT<@BIvF+C`{ zf}Rvz$$%7H#eftoVL*zmW*+z!ee|H{etJ;!06i#r zke(Dh#DElSU_gor&%<`b<6?#zgDm^HAjUE)eP7jLSpa(^}=t0q&^q}Z1dQkK> zJt^AFfE2yMfE2yUfE2yQfE4XvK#JaHK#D$KK#D$OK#KMJ_!1~` zyTu%IyvmnS^qu2On*fTwXL(R`h#nOEKo5!z(}SWT^q}Y{Jt+E-9u)mV4~mY_gQ7Zm zQuH$eQuGT0QuHeWQgoaFDf&ADQuG@GQuI3mQsfH5Z96G)GayAF3`miO0VxV)K#Cj& zq$rF5De^KPMd1uck&gi>YQ%sPHD*AHnlKs4!<^1t@CC@}Q^{Jt%5T4~nAcK~WoeP}G(l6t$xVMeXT9Q3rZZ)RCSP zbz(q@Ix`?eF$_piECW*1g#jt*%77GgV?c_!GayALF(5@JGayAh7?7e<7?7f#3`o(b z3`kKg2BavC0V#@SK#CF=kfKBeq$r62DeBFD6eTmT6h(%4-V;C~Ghzgs7Gd^Izf8|) zeZsuTmr^t!%&D6UiUzVgC>lf$icX^kMT6-<(dqP{Xb3$hI)fe*4W$P~DfFNym7Wx( zF(5_h3`kK115%X9fD{d5K#H;$kRm?=Qk2br6y-1=MY#+}Q62+Ql+S<^6)+%0g$zj1 za0aBPhyf`oWyj%r}?qPXQbT2(9T2Bv(?xP1q_tS%-2k1f3gY=;2A$m}>fgTh+Oizk7G9X2d zFd#*bG9X2dF(5^cGayAzFd#*n7?7eT8IYo<7?7f;8IYpQ3`o&43`o(l3`o&)3`o%y z2Bc^!15&h&0V#T(0V&$ffE2yJfE4XuK#E>uU@5vY%=5hf5_yFq;M@g@TIq+4UJCOn zUrN!dVNS%kpy)N02Su;bgQ7R+LD4RHQ1m7}D0+(?6unIkigwe3qIc*)(Yy4d=sgCc zXb%HY^gaVp^Z^4>^dSRMw3h)X`iKE3`j`PJ`h)=~+Q)zteae6o?PoxWK4UFe5eZhbfeaV0n9biC;zG6U%4l*D`Uo#*@-!QNgy&UH0D}Y2^tM8+|0*V%T#C#j( zRlby>AHtjwHK6D)%Y&jL^q}Y{Jt+E-9u)mV4~mY_gQ7ZmQ1mlBDEfsS6#Yt1ijFfN zMSo{Nihg52ihgH6idA}<3{6wZJY`52I* zMhr+%V+N$C2?J8plmRJf#()$xXF!S~7?7e!29~1l!#w8;Adv;~)z;1-P_#<_#Ic3f zt9&U%t-a2wS)eGIKP}Gqg6m_BpMV;wEQ4BpPie*5G zx-cL`T^W#~ZVX6KcLt>BBnG7DWCosU0#efvWF(5_p3`kJ| z15%X8fD|P$AVs|ykfLM;q^J)AQq-3LDeA|-QqZMJe>4D3u-*rO|_;bb3&fK~IV@8IYo3 z3`kKH15)H?K#H;%kfIz0q$rmGDavC&it-tdq5=k_sE`3E8qRs7v#qH$iQ z$2?F}&hnsWJUu9yKo5#0(u1N3dQdcp9u!Tc2St_iplAv`D4I%7iq2s`il#9jMbjCO zqACWYXa)mPG?M`-I+p<{s%AinY8a5BS_Y(O76Vc=n*k|0j{zx~!+;dcWk8DNF(5_f zGayA5Fd#)2G9X3s8IYoj7?7d`3@k-wdp&sqNaO?hK3W+ldNM}L#a^%Sr4%jlI#m~d zqRUtw6kSdaiWbv@qATb@(UtU|=qh?pw1gfMT}=;)uAv7-*V2=sr3^^XG6tmRItHX@ zIRjF(f&nSIo&hPkfdMJHkpU@M$$%8y#DEmt%zzZ#!hjU5VnB*+Wk8B)Z55r{A$ppyI4NXyj5IPD-NP$Qi zDN;luLTJ*Y3D{6U5fQOs7dv)DY}l}3MZ~VC*s&}2e(rle_cfWI@B6*)SI+;O_5HI} z);+&#_Ot7?%d=;)<1AVi4!$meM4r`e@84h+y{-3)o(YH5FSY3TaOjsMX3;j z&7$pOv*<;#S@aUwEP9!27QI3?i(Vz0MX!;~qSwh-^acQn-UMLL4geOt1;C=W0a)}7 z0E>14u;^U?7QF|+qW1w<^Z@{iJ_KOVM*uAP7=T5)09f=10E<2aV9{p)EczUPMPC50 z=t}?=eFbn9Jr@q{b&^;#vZ;u()hz0vAI*Lp4y#{k(Rbm{kWPW_-P5>02cKJV9@}8vnZMvyh#L!oZLyo zX_4r9`YrV@i4I5%t6yr-;Kb0grF#8EGiX%wHAu*J>!YrCdd$XvHY!*!-n?;k!X3-R~Su~Yw7EL3YMMsg%qUmI_Xa*UJW&*Hi z766N81F-0502a*wV9{Iv7R>`-(R=_FEdXHAF#s%D2*9F604!Pzz@lRTSaci!i;f3i z(Fp)7IuU?HO8{7O5&(-%24K-C0B6zo#9%)WBr>U$h;yV_^tf8IG%>7xsYS~ZL!(!k zMW@r=ELuS}i_RdMMJvf>(V1kkXcgHkI*V);ttOjAXOqpMbI4e9E&z+p17Okl04%xy zfJJKnSacx(i!K6S(Zv8Px&(klmjbZpG5{7`4#1)-09dpZfJIjVu;?lP7F`X%qH6$H zbS(gjt^;7v^#Ckd2XGdhnixD@1c}tO6LC&6i@wo|q#F{$>X%w{OJeBqRc6txv^R@x zBb!C*$!5{*WV2`k*(|z)Y!+=Kn?-k$&7!-=X3^bbEV>7PMfU=*XcGX7?gL=a{QxX_ z0Dwgg0I02XZqV9~<>EP4chMUMio=rI5mJr2O4CjeNq1%O3Q0Q02VzBz@ldW zSoACai=G2Gi*8B`J}QDlrX-3uH=9N8>Yo*DO$@7FYSH$@&m-vF>^ zH^5o6EissMwpdiF-`;=0EP7eLvi5CaSp8CqeoPGQcdl9V6Yb5SpUGy?FJ!amSF&03 z8`&)Soop8UK{kv2B%4KElJ(ooq5v6-8Ue5<2*9Go04xdtuqXk5MPUFIB?7Q034le( z04z!YU{NXni_!pCln%h6CIBqT0ANuBfJK=AENTkCqGkXrY7W4nEC3co0nVcD6NBX< zNaT!c5$6Z9Xo`Lu(jqCWeyK%ml0vi3H;dZR-YjZIHjDNmn?>1Vv#34UEb2fui#n3c zqE2M9s599t+MA3;`v9=03jmAu1z^#B04&-cfJI#aSkw)GMcn~dlmoz`9sn%L1z=H6 z02cKEU{P-X7WDyOQC|QS^#fp0e*hK@0ASGp04zEXfJFlV&Z1UH!Sh9sNR~cszjc!9 z=}(GC7?c!Nztp0EpzEGi_MMMY$@Xc*Zn8csHgipgft!DO>& z1R0A;09aHCz@jn$7L^0Ar~-gRBLP@c3BaN%02WmPu&4%rMTY>eXcPd8Mgy>D3;>J9 z0%02Yk{V9{X!EIJ&3MYRAdIs$-2;{nd1gOY-8iXf54^dvUKEE+5Cg^o-Lt6yr- zq@>Vq7nwzqX>S%yA)7^0$!5_svRQN#*({n)Hj8GE&7zrPvuGCCESgQmqN4#=GzWl1 za{*X14}eAU0a&yEfJMguuxKFwixvT}XfXhbjs;-RaR4kj9)LwB0I=vp02VC)V9`kc zEIJv0MW+C;Xej`TmI1KnRDiQ+Vp6dE#bVJ0eNu6qS+qsZXs0EG)i1T^jHJ-eOUi5&7$+kSabmZi`D?J=t2M%T?D|Q zivd`42>^>O1z^!-04%y3fJIjTuxKp+i>?G<(NzE}x*C8**8s5SS^ySZ2f(810a&yS zfJHX|u;@kr7TpAJ7M-3HoGgMw3iXeNR+vQ@`kDUCNn!O%En1%xT7J1%bUW?Mq77uT z=nk@3w2^EU-AOi!?joB-cazPcd&p+dy=1d!6B&!{17Okp04#a{fJF}iu;?KG7HtM# z(Zc{NdIW$)j{>mhF#r}l4#1)(09dpIfJILNu;?iO7CjBXqGteD^eh02oRsa?~ z55S^r0B6yyNx@r0kVrHA-t}!}(NwkQg`}|hr53%M6xzDhEP93ZX3?u;v*Fw&5%%XSnBI$>uu==GI{gM=FcC}gbEA7pq-^gas?_{&+53*VGC)q6W zlC9@%76r&=Q6sWh6eOEPjmcOP0$@=B0E@x^EJ_4mQ4#=)k^xwh0>GkF02ZYIuqYjX zMNI%$lmWn^2mp&R0a(-&fJMy!SkxSVMOgqWiUP2x1ptd$061hfi zH2!QBCFx^mS|^9qFSTf|!(W>E*SS=5ni7Ih+&__3z zMbl_+79B-4i>8y!q8VhfXeQY#nngB?W|PgLqseB`9I{z7myAX809Z61fJF-cSab{k zixvW~Xb}L576Y*8SO69s2f(7^0a$bb0E04!P#z@pOu&Z5c5!IT@tqC@l(kSS)-82uZN70F@sOD$TJ9O`KHS#%EBEIOBL7M({ni_RyTMHi6GqBUf*=t43UT?D|Qivd`42>^>O1z^!-04%y3 zfJIjTuxKp+i>?G<(NzE}x*C8**8s5SS^ySZ2f(810a&ySfJHX|u;@kr7TpBEqMHF& zbPE8BZUs1tRwf5WiXf2${oeJNW>IIoNV+XKtbVCQcO-}A+-eqWq`g^mC)q5zi)mhF#r}l z4#1)(09dpIfJILNu;?iO7CjBXqGteD^eh02oRsa?~55S^r04#a|fJNH@So9*m zS#*1HaE%BOIbA#V8_c5RYSBx{Vf9NbdM!D0&w8`yb=sRnZ;;KRH_2wv4zgMF7TGL% zn`{=nLpFcK|H<9)LwZ0I=vs02ciOa2CCi9DGXz zi9D`<_VKD&)IBWW=j5>Zr56339QtE}S@Z|(&7wcaW|5a-J$JJxKsJjSkI zHj6@JvnYXV7KO=JlnB70BmfpA1F$FsfJLbQEJ_1lQ91yNngFmU1As*l02XBeu&5~j zi<$wjs5t6Bu&6r#i*f*1)B}J;xd1Hc3BaOW04(Yaz@k0?Eb0ruqJ97@>JPx80RSvI0DwgY z0%cbi4SX>S%4lg*-o$!5_AvRPC@Hj7HhW>Fd0EGj3PMHOVTXe1enDgjtj1;Cr~7L5X6(P#h`jR9cMSO69s3c#Xq04zETfJKJ`u&5S*MMnUzXgmOmjs#%Q z1OOII1Yl7e0E;F8uxK*CSyY%3yiEj&)as|PMP^Z%{z1r;l(71x7EMnHZM)Yjnn8QB zXeQY#nngB?W|PgLqseB`9I{z7muwczBb!C@$!5_4G8P>Jz@mi!ELsG>qQw9#Iu?LM z#{sbDcmNii0KlRX0a&yIfJG+(u;^p}7M%jXqNM;VS_Z(PQvq0X8UTxy1F-0H02ZwP zV9^->ELsV07EMbDelLPVw(DP5A7vJ8m-j+vri9fmwdm}WP}cos(K)m?i_RsRMdy*t zqVvgS(FJ6)Xbsscx{z!ZT|_pEE+(5rmyogOQUDfR2Ed}r0a$be0E^ZFu;@wv7F`9v zqN@Q|bPWKDt_5JxbpR~79)Lyb09bSb0E=z}V9`wgEV>zhMYjO3=vDw0-3Gv-^#Clo z9pEfFD~j{&ggaR3%Q0l=ay04#bEfJILM zu;^(37Ci&NqGthE^c(<-wgRx|c>oq|17Oh$04&-Lz@ircSo9JAi(Up`(JKIF(Z-bE zNg_z(ZvAuEJI$gkdSH4rC9Hm_MQ^5ruG(xC?V!C`^cLAHdYfz(y+byOc9PAacgbea zdt|fdeX?2f0og42kc>qi0kG&}02b{6V9_T4Ecz6HMV|q%=yL!TeF4CtF9BHe6#$FA z24K-Q04&-Kz@l#fSo9qLi@pb7(GLJD`VoLdKLN1lX8;!c0>GkQ0nVb=Q-WJWkjQm< zyZQ~YXly$PzomrLFSW=^4effwEDEGrPu?tQL^g|pWV5I-*(?f?&7uUdSrjIlMTumy zD2Z$qC6loz1%O4V04z!aU{N{%i<$tiCW z3jh|i1Yl7s02Z|dU{M6RvuJ;^S=5zm7Ih<=Mcv6}Q4Sf4dH}E} z7l1`Q0a(-vfJMClSkwoAMSTHS)DM6~{Q+1s0DwgY0I=vl02U1dV9_7|77Yeq(Ln$# z8UnzgJOCCA1z=G=0E-F$SX2mb7IjPwR*4{yLj6inr&QO|@1P&e7Nv&OFSY34)X=;w zX3+@Rn?)sLv#6A87L}3BqH?lXR6#b2Mv~2& zGzNf0V*yxnC;*Gb0kG&W02Un%z@l0J799b=qVWJMIud|I698B=5r9Q?04$mWz@o_j zESdtqqNxBZng(zd4NnbTB!Wbq?jYh6n?;Z6-^L!58dks5qFJe-O;4FcvuSS@9Zfci z=8(;zxn#3w9@#9KPd1Adkj^>u0$|a}04zEMfJI9IShNg)MW+I==rjNpEeBxH=>RNR0l=a&09dpVfJJ8luxJ$k zi_QW#i)N$--w{C~N9p&jXPQMNdh=*?YFPbJi_S|8dC!_f=hNOSx`1pJts$F57n04Q zi^yit#bmSS60%uzDcLN#jBFNNPR61u09dpZfJIjVu;?lP7F`X%qH6$HbS(gjt^;7v z^#Ckd2f(5m09bS*0E=z{VA0J0EV>1NMYjU5=r#Zrtp{My?Eoy=0KlR<09dpU;4C^P zHP~4MiOkUNU7u?f&C`!&?@SG=Uux04siC5+X3-|vn??7L&7%9sX3+y=v*Gjt0a)}D0E?amV9_%GEP57zMb81S zXe$7Vo(EvjHUJjA0KlT{04#bDfJH9>u;^s~7QF(%qE`V}^cnz*UI#df?oJIJC4xlW z&|5_Jm_-*POL!wStbVCQZ>NSe02ciYz@k3@&Y~Tu!P`ZUNV48_e9J5v z(^SHrsbTd?EefWEw#)tOrbBypp~h(qd-@@=S(HFFi^62HD3NRyC6UddWU^V5LN<$1 z$!1X+8H>^ZSkwf7MHv7riU6=E6M#ic0a(-wfJMy#Sd<08q9_21S^%)9B>;XH^}@v>R8FYWDEv>(|l+MjF|btRic-N`;9R$FlApk7O17Oim z02bu~u&4llMTGz?Dgt29FaQ<}2RMuNP74kaK_a!Mdf6(sDf-3jU<~zm1MK1ifk5Dlg*+UvRQNp*(@4G#-h;xEE)sAqOkxhIuw9K z;{aH67yye72VhYx0E>_nhwCC831R|h_v7-B1q&E{oZwnS@gVKB+X0S(IBb!C@ z$!5_4vRQNt*(_Q}Hj5UK&7#F*v*=i|S#%s3i;f3i(Fp)7IuU?HO8{7O5&(-%24K-C z04!Pxz@lXUEIJi{MW+FX%xyCN1>on`Y64v^R?`BAZ1Qlg*+_$Y#-{ zWV7fpvRQOF*(|z(Y!1NMYjU5=r#Zrtp{My?Eoy=0KlR<09dpUfJJu#u;?xT7TpbS7M-6K zY_dZv`b3XK7nns4r%SjeEv$a2MfazLdc18GJwSW2=s~hs^bpxB+DtZ!9wwVbkC4rx zN6BW4S+>2 z0I+B~0E=D(V9`qeEP5G$MXvy`=v4p~y#~Od*8y1c1^|oR1Ypq)fU{^*TChe0i98$? zaqi=~NIwpFD=n;ksYUOmg%<2Ii{7KXS@b^HEc$?K7JW!Ii#{ToMIV#RqFrRO=o7M8 z^eNda`izW4p98Sy3jh{<3BaPS09f=j0E@l>V9{;>7JUoAqVE7$^gRHJegI(6j{q$C z34ldE1F+~902ciUz@py(SoAvpi~ay$(VqY;^3ttijzs~0v*?|);3XnR`t?2 zjD8%_C_SuxsYMCtq5I!6i^8-wixSCZQ4-lKN+z2{DP*%Km24KJkHxr^jsPs`1i+%s04&-Y;4EsK9(-2>iB#zYbtv8S^bgZVh3=CcR=?Du z{nJB@J~WHE(%vlUMmCGOlg*+WvRTxFY!>B`&7z)Uv#1x@Eb2`*i~5kUs4oDE`T?-0 zKLCpc0I=u)02Unxz@mWwEE)vBqQL+xItYM8LjYKm2f(7C04&M}U{L`8iwXf)R0P1H zVE`-|4#1*f02Un#z@iZVXVJdt!F@!K$bI_J*?wlxVEs6xBt5KtsYMm(q2V8!MI&i% z7FCkXqAIdkR82OEYRG2MA!M^?6xl2qO*V_hkjb z02VC=VA1ISELs7;qB8(kv=V?tX9BQj6#$FQ0$|Z<02ZAMz@l>iSadD`i_QaJ(fI&p z(cJXl9U@4ig`ULbnMED+8?zUrht)5&=;HLyOP`rVm(boUx|D1dT}C#GE+?BsSCGx3 zwPdsCO0rpW71=Dhnrs$bL&lS@am$EP9-57Ck{W zi?)!>q9@5_(NknBdK!R5&j7IKSpXJ22f(7O04#bQfJNH?So8t_i?#!>=tTe)y#&Cb zmjPJx3IK~<1z^!@04#bPfJJWru;@(y7VQ9F(OUp4dK-X6?*N=d52ObV5X&36 zG>gUtCG1QOt6yr-2kD_BzBY?Kq`g`65!o#Im~0m9BAZ2@kjPGV9_rCEcz9I zMZW>C=yw1X{Q!vt1~`k}OAjs+K_cht_paYJi$?2L z)X%xS)FgD>ZnG$v_GVEE*(^#Wn?-44vnZWx7BwN8MHytXC_*-iGRbC9Q!*Ac z17J~e02XBduqX<^q80!wY6-xiRsbw&4Zxx{04!Y7fAo4gf6b z2*9FF04(YZz@ohYShNoSi@E@?XkUP{DBL9Yj0h4rS#LBZHgP@u+4_yy{hEZ;FSV$9 zlhEhinMFCYH;a0Z&7xegS=5tk7WE>VMZL*pQ6I8d)R$})^&^`_{mED~0DwgY0I=vl z02U1dV9_7|77Yeq(Ln$#8UnzgJOCCA1z=G=0E-F$SX2nWq9Onm4Fh1&Z~zt+1F+~| z02Yk^U{MJGi%J1lR0ePsb!`%id@mM#s~>uFGmHA@)pdE3u==GIRW%9q{Lw6`roCBI zLpF;JA)7^`$Y#-KvRO2SY!;0rn?;9`&7yH+v*<7~799@2qFMkJ9Ra|i@c=A35`aY$ z09Z5;fJJoxESdzsqR9X(ngYP0sQ@gR2Ed}D09Z5~fJHL^STqxWMY8}{G#h|LM+2~E z4gibh0-Qx7n*>LRAd!js#k5MZ=uNd~UX!r;r4}u05?c7PS+t1uX3=7@S#&JfEIN*C z79CGEi%uY$MJJNYq9tUr=p?dPbTS!>P61%iQUDe$17Ojq04zEUfJMszSado7i&g-z z=nMcBtps4vnE)(W1;C=S09dpdfJJ8mu;?5B7M%;gqVoV)bUpx!E&yQB8UPku2yhlH zXcD|k1c^-6lh`q4(E`1BbWxMA`lS|K)+F@cuV&HZv^R^cAe%*N$!5`&WV7fhvRQOB z*(|z-Y!+QhHjAz!n?=`?v1lCti*5j5(TxBsx(R?qHv_Qf762CA3c#Y<09dphfJL_h zuxJASi|znm(MA9k-3h>=y8u{pHvo(70btR+04&-Bz@qyASad%Ciyi~&|qDPv98vkJyJxY7C=rOWc^f=ipdV*{gZ6TXQPm;}|r^sf} z(`2*g8M0aQEE$WQ17Ois02VzDz@lvcEP4TeMcV;b^dbO@UIJjz%K$8T1%O4b0c z02aLtz@j$*So9_Ui*^98=q&&iy$!&kcK}$l6M#kU0kfU{_Glis_=ri#{QnMW2$*qR+@?(dT5d=nJx0^d;FW`ig88 zeN8rtz9D1LZU7d23&5i909f=r0E>PAV9}2NEcyw6MLz?u=obJM{R+UM-vC(jI{=IR z0ASId04(w{tlN%70RR>?0$@=PfJKb~SQG+aQ33#q!T@K{hfRXBM3Bgt`hR0TGK;qA z=`ArMtbVCQsTrZwjm)An+M7k`WV5IV*(}N+n?(__S(HgOi<*+nqGn{Xs5#jz$|7S? z6o5r709e!#fJLnUSkxMTMQs3B)E0n6?EqM`7XXX00a(-?fJGeuSkw`KMV$ax)ER(9 zdjqg&9{?700btR-04&-MfJOTQu&67*S(Ka+yi){;%+O1rlnmF?U#%a_cFPE>Uuscq zM(CBsW>HVtn?=3IW>IglS=5JY7WE~YMg7QTQGc>oG=OXt9Y8jV4kTmIKmZmE0$|Z# z02Untz@i}lEXo65(NF*u04yp3V9_uD77YhrQ856E4hCS+2mlt90I;YO zfJJ2hEGh?JQ3U{tMgp8gIT^uUMUcpB{T!`_SyZZ@##Uy8)i1T^kc?29uvs*U_GZy& zvRO2SY!;0rn?;9`&7yH+v*<9gS#&trEUG1&MMsdaXgmOmjs#%Q1OOII1Yl7e0E;F8 zuxK&>i>3guXet1UrU9_%C;%2s2Vl_*02a*zV9_i97R?4=(a``bnghV1xd1Gh2f(8F z04!Pna28c(1oK3Y$YlM-Y>ip;PNsxoGQ#SYT6AoN{LekJ=s4P&MaPrPq7%qw(TQZU zXbIUYI*Du+olG{1P9d8`OUY)@GBOsO3c#Y%09dpffJLVRuxJGUi_QRG(MkXooe99A zRRAnH3xGwd0a$c40E^B6V9~h%EIJQ>Mdt&s=mG#1tpQ-sg#awN2!KTw1F+~4fU{^( zM({KdB=Tssh_l!%I$dubU78VAztp0&8KHG4X3>?jH;b+!n?+ZX&7y0_X3@1|v*NF zbSD6d?gC)Z-2g1Q2Y^NQ0WGvbSz@irbShO90MK1!d=p_Iay$ryjR{&V_DgcXK17OkX04#a~fJJWt zuxJMWi{1iY(c1tldIx|-I{{eqE&z+(17Okn04(|dfJGkyoJEgj1e>OdMbGLjqQ}gl zGxXEgk21pQms<2`MyPj&S@aq0&7#lAX3-a9v*=5*S@adzEc%*k7JWlDi*}REqHoD& z(RXAl`W}EqKLD`kM*tT61i+%70a)}40E>PFV9{>?EczXQMSlRW=uZF^$v=U1Ru==GIHHm~4XPQMBv^R?)WV0xfY!)>on?=pYW>IspS(HUKi=t$+s0G<9YDvbT zRsbw&4Zxx{04!Y7fAo4gf6b2*9FF04(YZz@ohYShNoSi@E@? zXkP#p?FYc3{Q+3i6@W$E09e!=fJHd~XHi-tc!dZOxjrP~q(@v&zqj6X>=6m8UuseB zNN962v#1a4&7!_!v#1~0Eb31-iw2O*q65fg(Sc;MXdu}v8bmgW29vSqAOIE(0bo%c z0E>nKuqYpZMFjvXDgzNSadJ|i$(yjs04sTr2s4{17J}(0E;RB zSTquVMU?<7ssdn9HNaWaGZOqz1c?-A=f0O&)L2h%HIcCTr525egc71=(OBA>MTe5j zqH$!i=rFQbbU4{8swJC6N07~;@no~;NU~Wpfs92H0a#QAz@kY2ESe0!qA36@nhL<8 zX#gxb3V=n^0a!ExfJHL_STqZOMY91|bTj~q<^Zs0E&z+>0kCL30E-p?u;>^77A*u| z(ISAeXjCM)zX%e!Td%H1n?={Rm#{bzR=?Du6C$CKmS)k3v^R^EkjJ02W;gz@ke4Sac}>i!K9T(d7VV(Q%RB z(IQCXM}2PYCE)@IQ)v^R^cC7VUpk#02bW^z@obWSac5n zi|z$r(Ix;E-3P#;`vF+=004^~1Ypra04&-Jz@mo%So8=0iyj3yi>{0W?-oHK9aBY| ztIVQBdL#R>NLc++i=K>xUTbR>JwGEc$_L7X3)Z zqMra*^fLg9egR<7uK+Ci4S+?z1F+~102ciTz#=cxy6spL0ANug02T!SSkxGRMIitd zB>=D}48Wp902Ui{ZflE zGeZ+Qm_FT|EQ*rNq84Pcs3qAfYDG4ST9eJ9He@Vn3&5gw04&-I zfJNB=ENTzHq7DEo>IlH1P5>(FC$tG?8o;)sfAjNn|XV48Wo(04$mcz@ljYEIJB+MbiOTGy{M|GXYpM z3xGwl0a$c20E^}TuxKs-i{=5aXg&ao767p57yuS61Ypr302VCV z7XYwm4FHQS1Yprc04%x~fJK)8u;@|%7F`CwqRRnTbOiv5)&j8TN`SNI#LVEKB1q&K ziJ>KC(L4G`tgAA^>X+BtYZU63bY0hgm(^3Qy1lGwc^qxytOfEZNn+N8aw1I4+9VfM z8Cg5zaMmmUl%5I^=j>LDrO9&l{d~YcJ0$$@;F3=T&4K(BJc_vz8p- zd84zQ80dN9vQiK7yd$zI^E_{2)`j_=Hzn)sLeHC?)oHlr&CZ&3u;wK&$~2h z`UKBgo3)|N^RCJIX|m_7%Njh*^KQ;sI^FZuXFWaB^EPH>9PN4cWF0cs^X|{ObiU_p z&U)_{&wDJZ%VN)aGHd2>p7(6l#uGemTh=d2JnyBfA*XoWYgwl*^Sm8d&z|OaJF_xZ zc-{wDqgQ&~uB^*fdEVz)AFTGgue0_$*Ym#1nti_K{gidr8qfPJ`rAda{sYmWm+EJ2 z(dC!R76?SQu9Zy?h&H=gwm~2|_FCBpf#}-nWh(@tAKf6EArS3)vuuYzRR5cOr$AKy z9eI~PRR5oJ*FaSNA#jgCRR5!E??6=lC1?LYRR5>qz(7?0Dc+Dk^s3FWK>|_zw^YLe zQT@L{C4s2^W0;CSRR6O_bs(z$nqhPxs?XLR7l`V^(T@m3_373V15tfE@svPRpD#N- z5Y-2S&JINN36JvvQGG<;!a#JvPT4$xs6HfXNg%3EIa(Ts>SJn_2cr6%k(Gg{J}6>! zAgX`qe_kM}f2w_9AgX_Bdubr5e=NB+5Y@kSyCx9TKUZ28i0a>)+#HDN9}KJyMD-ir z8v{}O%I-aZsD9`2{y-v zUJFF^-usR~RBxW{3`F(r*9U>9-oDrsh-&}y^FUNP5MKwPdIk7hAgZVEp8`=m2LBfD zQU*t4$GXPtaxET|Jtfd9rA1gas{EA5dx1+I>=W=>&XRpA&}*o^PIqs5ElXwp3G_Ow zs|+occ~j-LWqoc!)k%oR2 zrt3WPPZuX;u-Q5X1MHo4?Iavvp|kABfdegc)iBUPsm{V63w=9E7;K@jT+jp#vT&>% z4+2A6Xd`=@_n0i(=57J6ZJ?r2;;~*E*`vG{gnjE+DD{&4UR~TaFft+X%;~S6dR*H; zWhipqbvGW;Hc%BxJ!;c^5wG2BY4Wx-X(PLXKfa9a_2awM##i82D7DAJvDq@dQ0nX% z2TzyLB}6{BZ~4fgWC)BV=iQlJ_ofC?Rs; zn%5sX)}O)MPu=#N&R|01iVruudb~fzS9jdDU6$$uYxNX!@zi0@9p=x)>f@>x_-)?& z=+t!!{iW)D=9=MNyOX6!sISb#Dr+0g@s}zgvh>SOcgv8nN>`6|}k<0*3}l)C-ioJRg=maTv53>l$}X4@lgy{I!DO6~aE z0sDAu-muZs(Pqn|vR&G}Cpc5*?MoZymCW0nPd>C!*G4Gy>fR?0k#UAnFDq&^-ydb* z%DtLe<6zS)tS;t~|ekzmPv}|8|FnBs28n=FS!V3{9#& zsjt`O2Wg_Ks+cA>ym+rHqbJ`X@s}}GUg#EI#`~N09=AwmEpq1zYfAhvPI{|Txr{L( za>Q#99%cxvaV=gVf3wY8z*!P)+ZURiOi^WoVYtLJ)c z=E?4<3)$T@38jvBsi!RDaf1DYTrMwkA&+8|?>_h9wK~d#$QfU)x!@VTfH8&pPmhi~cN&c$({>vA)EcDteOmd4D zkp+{ZNho!3*L+#TC4&7$Tq!Sf5leahqAU9J_eYsOrO_OJly4pVc5i=_AHMX?>nC_^ zE|w;`gh#k0x))t%V>y?xT(~`4>5t{G7j_Kr$FlX5q$&PbUb|w&9kP5kOA}qb>s^yZ zi9@_L_t-+H2y0-)@T4r`6lpa;=B~)Ka;~0Z zlRC`7P^#PSFJ@BL*`zM!{i0jGmAMvMmi}JP(j5I<#! zc73+#k;Pt{-qJ>wD9g3ctyW=^>BeZB{-c@9Bx`c8d*4@ituUSR363R19(n(b^=^Ot zaMR~2Wbcw`_d9oFiocAPOq*8iwRu+B=-F!n(+Moenc>gwl5@_!US~HUvf=K#e)o@K zsn3nQ^#rfoHfd8Nv)g7>s+-_9Oz_VKzS=5#iY)AnJC}axw%;F1x1Q&$xOeTV7s%4i zl+(D*=HBuv+9yQ5d2jt$?$EjT{+YU~Bt$lC`NN-NLgej>PyT+9*Je|O=T*rx52exF zUoZdOP3qcZuRq|{>wqtYjPuv)AAhdBQ1xwO&WgouP|WlZ{;&^Vaj z1tNjY=}l9D>8;aiqLDyG)bkp3@={U;3-Y{RmKRJvAmzZ60V%~z<>K7l(T}?NcuErX z_Di^NAecTlB}ImELkHxggfjVw@-|03jh$^HvD6sFjCLvFmOO=OBXy0oT&l$820 zq^EhoL?)k-l9rO1(qG2cB-&u83>hkJCL7Tp5}wPdRMv@C8K31lV=X|ZN#OPxr|P~03firzg`)@rNXe`T%X znXaier=J{~TsPl5B%$iY`Gk$vA!kq5YXH6JC zJ!kHe@pI~O=G4usn>&7PPF>I1x%1{voH{FK-mF>ECrlYXb>`fh$rC2jj-N9lC$~p! zuiBnHdgj*V_E6YOV7HmGX4ZA98-L`~Zn-_W_v)r^cbB&typ=O`=7j0gfC?JpcR`G+q0-;dTfAkXyBm^f1Ld}CMyN417hBC`SO-n+dgyBs?O%tSD zLQbq^`gyR|sBxfqC`C(?Pf4RzWp)HM6=8i(5JNc=_}|H(L-Cj_!( zZ0$o$i*+nHIUzUk5mpD;ObzmL`wpSZt}Q74Vt4<| zMzT)32yP@ZAJq!Z`A=e9{f&YPy1TK-l}xCOKYB%(`pRt~onCe@O*W&jKtgPDW&6=K zxo+g1v5k_M&~z`iT)LuVIhzJTofDe7Wt1`eYYXY-Z;{R4KDH9-m)5<%(BALzm-qkq zN@^Ed)~5fZWp(Z#Bz5q=D0pTvY8 zC@CSBHgIyzeIfzYhQRRoTZvQ56eK?MmUF@8)s4sM~>b=Z*=VGkK8iykgs5Ep0TSS%clEbNp^3 zr*GMfWK)Qx-Qz7yO8DQmW&XDssmtA2Ebx!fqS1fRPdkOg3)(&=XeT*_>O23!u{jX> z_Xf5z-oG~H|EYm<{F(lDPh$V(lK!jfP&ceySLhu5XAd}kdrja@*#G~V6Fo|H`k&hR z|K^zgUtW8EcjE9*!~aD`^pN2$8yoKPPLcn!>)O9)%#L+o6FT`bl_a}@UNqaaUH#=( zPN;+Uk(wP!(`)lktAs$#Uh-Nm23r;Di=3QBwemV4&_2|qN2pa>VeK_awF8g#DdZG=r)l;pu)TyNf4^omBPX;R)T2HzJANHF)Bo~deYuo+5^0K2$ zxt$xs|F)Moq1Y1t-Joj+%z)&FgOsKma+Jmp2(0%g1K7wXFrRh}x?ZyQkI(DGDNh6mxQ9Tnk>{#w` z`y``hqt@~fQ&Ck#ZDD0)ZE@Klc_qaKwRx4pYDx>ssy*H)Ev%}_8&+6bU0z;WQeHO9 zt1KK=o12$EJT^prbybbD&o3{nC@HL#A#2KtZMdTR;k8HB513b3P+L}BEdy5-R#q1l z#NIi$LPlCsR#j6`QLb;)RuqpeEU7IjuPn{0c2ks5H5`0sNqPQ=+Je05yxOvw(xHWw zx*X+|Zs=b9<0o8JURzZ&v?{-{SO+UAuPH0=2kX~=xL*e}n9a(hk#3fyS=_(SWQ6~!%hVfAp) zfhkc{lbCxFUX@>4Rb4LYv`}=kZRplbgOSATPq76yd-6*BDc6=)6qd!_L*=2B z#lwbIm&qEfttzap)_s{t7v-0X@MpJIZ@1_4@u%odya&kNnS3M)+qUX&Z|2JCi;bXthT(Sx}v7K_K@LQY@cP4y~zjYgzV<_~Vh=l~iU~$+~mv`iN^@Ia+q<+VVpRD~n3XN9{S$%Ccdx z!=`wZR~j3jxIzwQwuvj`a1wt!^%tp1Oo$yMd&XAS(72VO8>oKL&iA;tWkbj+sVy9x zUszZWH_Ns{! zs>|&e+red5_sZwbD;Pg-d~J2zLU)+Sm7Q_o{24PA#U|wM8-?Y?4fi2tLypO%<(0Z^ z^q}c>=$`)GGJV#}$=PxQ^I311mcQ`1@`ARqLaWN_&slm7h`nbA;mX32LjORmjSCw} zu&ChT->5a;h z1+6YFEtE~>kE4HVljp}xutGLiRb{?Nm6u;#e26;%^^H64v4_f;dRUo%miAXoFBwE% z3vCXJ2W3y>ihzPR7*VwsFX0v_(nds2UJUPFcPdY`}I`R9HtSXMZ zCFNDNNB56SP&R{GgF|^y=x^}3Qzy@?o0u)%G?^2doXTBZB%>2a>W|m;$AkR*^4j5Y zoQgGI-ISIWxVe{0fY_V)g(W35C3%%%{IKFGkz3DOEC^O{0C4lzLz?@G*x(3WQ#I5- zch^=8mkSj)q#WBg%Ee8xv`~&)b_K(fbbPsT$aL)reUIkPj9+{mLQVy-887HrVCTom z!m+rat$m5@0jYjNh}y4t##6Q_=!S*!a}Y-GhHC56NCN^F;tQ+|OQ0P4?q zzVETqQ`}b0?ccz7Q)Re}Dej7^fW?xHyN46SdMw=IC=`E1A%_Bg7xq_AY|qH;(_lpG zK5VVHlY0Yk{`S;X?@dWTxqnoRok?sPyGTPq|K+Txrd#q`;dfXLoiR=UQ+nuQo%PTF-tDm}L0)4%t)viPrDUxw*a-!^ z^9Kyb)^C1w&&}5Fe)Z_zvv+ovId#+P#?P(WH@n-63A5)9nlNk5yt;+mX7uVMVBVDZ zGmexxY5J`3^Sa3w#|Fv1KT&}UIcfHSKHcWd?lv*EuaNO`CQKP5-y~bmzuS!NGvvEy z`%j!Zd;dwZv%5{s?pEG2yPJGPY0w0jfo_v#)XkkcesW#6>2)(F&zmx+hak6abyGtm z>AIXZb=J&obLC51Qs)YrC}*))_7|~V1MmE8?oKLt(e7`+!m{!jIrR9xHoUx!otfkc zEpKRXN%7eFOXMDMxGkRPpEXC+Eh?Tlv2LM1ie3#4qV;>c?lv*?>J65&j2sK9Mv)`}Ycsap4*04{aJqEo#D3&gPyOMCr z?aMc{WY(17mwaZjYV~ zlI#~URBpf6Ay_s?Y^3$;OfTVTZN<43a<24W$i{X+j$d(yEq|-mch&Z|0=FYz!xKht z8B<-Yeo3xw&Kx&R>AC&Q%(%mKWnsR~mAfv@l^&?yq+!2R&o=cJVA5N)y-|DL{&LF; zL)ty|kz7FgFI=zDM?GRg$u8@^=?I6?xGO^cI##+nc0tDQxw3F^YbUOOUSP@r%U8o6 zb$vfD)`9J7Q*~W8rs@vhg{2kJAFJQMJ^J^kUuAl~ApYc`OB3I@96m~JN#u`^BdJ@? z20IcvgkH16MhT4XIscPBT2XOPdBYB5y;B8w`To}*tL5vGvGKr1veCW%0djy_8}_I-iC~&&6HW#NO~F)@#@DGCg4U zC+pmQ`mXF;x;sf%&a|rU!8PodshKhTnUSiB;#%uq>uBf@=EcS)X9h;Bmq9iSxx%$q zxzYiM&0pLasHiL-UMyWi*%W1RWh}QGm}GwaEv4e>V!1>eD>Bs9%J+EdZ-C^=HMUH^ z?^eY67K}iTZt;r25v3@vKN`jUcCyTs?gWb_Yauq*TqHNx z1$4#d`>Tq1(0SYAWS&>0cg|urU1X1njWpI}%Ny$7LyNr;w<0SGtN-?D+CM(hx7Kav zdSbo|azP`@z&uIEQaWtK`NjSzs3K3!K>kp29&s;Z|738tHm0W!-&1qUYgBi{g|W|U!_OOdM|a5zrA#2<2JZc*WfBT zc2!P4)ODL!3${ud?wM>We|^Yxl3O3rIg48#dJ@zgN^RAs;%a#(?u<$=F1P-EK&~98 zy}485$|=?#);^m*0Xa$gFSL)Qz;&hkx8imvxrVM^LwcXqznP*}DRKj$c357qyL%_z z#Rg;LNZ+8Qr2Ya#b?2HU{?ave52q*haI|;FiehAX4dPAnk9|6e+PPwo_@02=8!gV4 zV~8BntNry98>&jWu+rtXZhdUM`4J)UhnR$m5Q6$|o>Cx5}mE={`x8vQK3f%$p zRsna=_vlTtyiB(p1uDc7b>plKvw%^^`r0=n;UPjDm#dpXxq~4$SKW1<@1@?E_FuUB?WK96YxB#h?VJ;TyV;+$zn(!| z?~LV)-Inu5S%2R;SMH+4?{W2advsylzS7_r733CoiBUi-+y}HZU)z%u>Nv1%GJJvKW@FT%DCfaxv02A zuHxcv7t~+5R8{5M$2bkv1M(uH+zhn~idpU|-!DDgiL}8iF$1xqd2EHn9pAJE$$(74 zi5@$@`b!jl6Vw;s?@rI|U|oNsEY?Bj)uUf*D*i_`94eT!Zsf`uci7W|G~5p9vV|Mo zb&cyF$qgHSrOWC4uY$2ia*UKym~{i}BN%#CuA9OXX(3m!;(CExzrh!I*~1jcECp&Ho6* ze_Q)Gycu_C(cr#|KYMydSYK!_$On3_(|_Ua$LdS^J-P9>Ic=%r|_EDw8$DlVTI?|DblztSqoi@%Ja z1%v9G#Pv$#1Ziv6okjF**L`4;74Di`?&rnUi*J$~Rk*uT|CxyF0&J|Q{+O)y zv*SNwVm{sS`s+*9rN81Db`t7GAs>TsO~=gAO{=P@l25j*oBWqMntC&Hk54b^{ghKp zoUOS%>N}9~DY|_yrn9I0n^?Dt>FcF{e~$aRF0M+W*3oU#u@u=d=E_a6*!pE%xZ9&~ zUkY%24S(gtU%~pF!cp=;uYS~BZlB#UOYXkBe$cn)nL*Eg`q4N?GCo?R<;O>d1Z08>~!liyy4=yIPQwS!5P+H#`@c_?jwi) z&c6!gkBa@j24#usF9#d+lytsj*Q$~A#X{@+xt@;yiUYm7m0DX%cbpN&oi~P8jt~pn z&Rr}<)!!2wl_x!Z4&QsU)Z0#as&*^B{%)+^*NhFyhdzGaa#*GI~w5JvGhiqmbT z(-M}4PH(&-ct)dD0WWWW3^ZQ=E4&#mKrg7T-<@{qH* zpT?d%qQFax4d&k89GCU|$K;_H?#I1fZ4Xb=XC&zRFWI9VH0$`6>WcG!-1`|ikY#;; zU|iOhZDLO|sDHwN4jz=ph{XTMBNF1Hyf4pii2Dh8u^I7caF3-8dh+1JxSyaGo3ITp zPq2vl33{1vN#{qNktsyix^DkWS>6NUhR|gx-6J2mN1nPzK4y=+Y>#~I9{I{W@@;$M z2lmL%?2%vJBlBnW{sFtwJg?J4J5B$GcSHW>6XN*OeQw<8{%<~bj9s|yd0`NL8LM~k z>&MyaFPFIS?=`p>mfly#{BVaviyqWx3#wSyibk)qP2tPJtF&-j_+x$9X;>}E3p;l?PRI9W*N2|2E-10SArQLeV z^JLf2cE@RzcFVO&y9=~RyQ?g((<<#YS{@<~meO{^wMx5ctAGGY_E~L)Vm`dS@i zb*R+}tNMf&9d3fvX;zQ6dZN{(R##iS&gwl@AGG?I)u*j)v-*nF9ai77y36X9R^{QG z{`~x6RS#M^fBs`N=~pTHR=Mlhw^upRoF@)fcV4Vf9_B zyR3d?^#`lJTh#|`>hh*o&9vImYPQvVtai8B$Lc_<`Bo3MI@0QBtF=}qS)E~Zp4DTm z>Juz=eonW#+Ugpsms`Eosy?$)hrh$B9=|j{Z1qX2&s){wn!f**)eo$GW_7pKpRLNt z(jPu-HQj1+t8J`yw7Q?wT&w-99%Qx1YN^#~tA|=W(&|*Jv#lOu^#rTStgf_ruGNdJ zUTJlm)!VGzW%U88k6C@j>UOKITit2(W2;|U{obk`=XHGs8@rlpHDa}e)xE6h11)v< zZdQ9+J<#eq^t2?Z|Z}n5F-&p<0>Yr8rftTwaS+G+=@`^+2lyR!glOVzt)l6st#D zU2OFft1GRZZ}oDk`tK)oyR5f*uhmDaK4bMIt8ZET$m&;Cf3g~o6P1oH*=kd(ZLD^- z+TChDt3#|7TdlNusMU#9XINce^+c=sOj4ch*;X&MdbQP?t=?(%L91J=ZnOHj)%UD^ zX7xL(zgta^K7>xMiPe@?yI374*Bko&aI1&Q`Cjuht4pLKp?Rg%tK`yN^Q~4NlXJc1 zZB{>$3wO=Ct?nX7^9fe(mZzv`e$49ca?PPxuNk%G%e98q3ah8LcliRV z&v$frht=kLyWGL*p>lzt?Wb71azB@Ewfb>am%p>xO)f-q_yerY&2@Q+)q8un{Djp% z`?#Fi*VV%Qu2xz-Lpm-xz6-6sFwo_+&3{H(l@YJyyTD!R0@! z_Pg2T0;|X0>hcP!kFIxlo7JQ{T+Xsuey7Xhte$_j%U4-_^In&CS#5v6%iXO`e$eH4 zR&Uwt@+Pa_KH{?XsH+1WceTjsiCbJ=Y4!1^T;6Uqq_g+U12-Z{O|mgI0f(4wTM+ zTRr7xmseYT>Q|RvvD)Mhm)lsakq(%S??|hc$b&#Nue17YW0$|Qx{v%H0e!!>)fw{d z5;QNidPj=Oo2~vV|3E?CPe^z5pbS?_tS*y|p1yyM)n}Ty{F>E>{F4QJzn#@l^4}IT zPqccO{M!Z1H(GsP{{MpJudVKz?Q&nMvpTqZoYgy}L#e|*V)fU(T~6G`)jauU4f=kW z)$6;uywU1IT0`=bRm-ny&6NI#)%T2lVfh=YKNt_lqx5z7kkw?ZGQH-OTUu>re1EI` ztrl9Xv|4L*y46KiPqlik)wNb{(JJ%*u+{IZ{%$oQH-Gj0LaSv~$6H-v^=YdwT1}J( z@@u=+R?DqUvO3G^RaWn|`k7VvHza=hURDpbT4nWAtCv{aX7xj>E##T;I{h50{jE;7 zy2R>6t4~_})oNx>n}4fiR>xaC&+0m>JFI?d^*5_M<(cL>AH%F3ZgsNNORTQ9y2a`? ztBrfR_ED?dt@g7z!s>}u@34Bm)!kP2k>_>me2lYtmet3#if>O@-EQ?2tM6ES-|FX9 zzqb0b)!(fq$c-2sU$WJvR-;z4t#-27&1$aI1FR0VI?U<_tJPLVTTS=mcqYpwyO3X7 zT9wOTKX+w8&&|Duf!QEsB3PIR zs0b#aAQsqNAlM1mh27ZQ-Q8W-t=Qd)g@Iz9|DXN4p5^ntXRUKsOWEHKbMLul=3*w_8Zr0D~W=}&?r}VD{#qsHV^(09WAyG{?3zzzGEg# zXy}{1SEg@{ed~9A|9{?vKkI<8`6-C$q1Em8NY^#%^5`*R#*f>les%Sd{(k5G&e7xZ zH;2V5tiQznU3SfXJ9AuPI^%}E`7ixVPpJIw6>UF$^ls^eR#|_YzN05j9KX|;y(gxt z{r~$T-Hn|7G_Bvan~zyK|L;FP(z|rlkKXD3`Q!Wxqj(o z{?FI@-@k!7e@yd_#nXQ+>AxZAzx-qI$?2$cQt7vCdgQ47Uw(a~(|^t(U2K@tIkoir z&JUNiO5uN9-zkj^L%P(jFZ;^ZnXhlR^q*tW#fFbpZ)|wwKf%RA|BsiuZH>nC&r#(g z>OWjOFwOtI-d!(GuQ&Z-emipadMBsLj!73AzDR$sd9QpSe)zR?6XJhe-wjtZ&iZ|k zudg-z=lU*9mmQNXHndx-{&M+p{^8g1@A?0p-vj@-zI6A%|6Jeg|2ZaIZ0Me@Z|^zt zrTP!ocXOKmy}swu_2u_#KEGP}&-p!^F6U#ihy3G&ag7bfFHpan|DS&?|MzVC?B%+p zJGIwL%?~g4W(xVTAKRvv8)T%P^Xtt&UQ7S|_xz^*=j}}#{^$HYOP7=7J=0IKew>r8 zFMl5P!|TdF`@NEXZEAYCJyS@Zh8ps_C%@iK>A(Cs{oY6y8&*51u_1qc^uzTfzW?jx zK1=79ACK_E%f;XDJ*a=*J(ld1e)M0q-@rlr1`HZ7I9=}7um6AkKXBmEy?PB^W?=sT z`2~Az+y2mDYY(sg#rE}UZA_2YxZYeo+iTV;>Yo!9PH#*1h9$n9zUmRT{QKKK|2Fh) zoPX@vV@HfzbIQy?jZ-d-a$;Z#iW8?USa=oYe2~F`w?R-R^S~ zkN^D0LVrvhHNDzl#7~vVs9*LRGvufB2XDN_l$m26*?7d1nMZb-GINFAQ)V99Z_3Q( zQ}b(>G<>}g`RB&r>yBugRhov69MN!EZts8H(7Q5x$nbo5&9#QEla5QTz4_EBGpF=> zeP(n2hQ@rvLXJmM`~SZA8ADk7^!1G_HM>|GD-d|LfX&&ARp# zX1!GN@a5yBm;0ZWPS2kE&$-lJdX=9Vn;PcddD|yuzTE%%oz816r}i7wYyLsQpP2bT z|H>^7el`7wQNL6tjQaK8@r#YPF1^$WaV`tTwfFg-YhUR9<=ThLU#7R^f&QoO^ltNC zQwI%?YfS%ao6G5+GaRz>q_bxnSafP=Jgl+dp~rW*cFa1nKXmXZjVBy<_f~-4 z{_*?ce%$1_KHt4HVdN4Q_xbRd_FoL${K@O4_ju@=ACFk(#1ppaHQ%?ZzE%0+q;WS7 z+Uels7HUc=UVWqGt#6h*yX$~M{@h~Pq32wEMf%#e{(Gspaf1%&v9RU3H8jk~zq|kQ zqp7joXYWjWCR4ty)v07fAzFKN-F7h{lG&Pqq(x35_Hxkdv;$2orFJ9@?EB&uu*A3I< zB7Z&8ZfN=}Q#K!zE;g^#)}>72k^K9!JSzR}ZY-ZjzZaWQOb31@mL=ydhf^1Rer%G1-!w=eSpO0DH%>FbIP<*)Omf6b(Pt$jm7Te)J-d?)Nj z>Fc;oKXrSQZ_by#L@D1$ zZ{-~2&gYojpk1`G|Ru!YaCa;pDsUL&XvyLnexkY&d-+J(w9Zgl^dqdD$keg z(%bt&IWfKV7ps?~_r~Il)l<`HEs=goFV(lPI$wH^FWFfACY@Qo#_GfAr&AiMAEl#C zZLDsZPUZB*>g4pkJEO6BeR_AD*;suqt+N`d52kn9*^SkFH~u+|)w9y6oZDF4F8$hh zjn(`wXP)0!{XD&*UmB||>5ZGwSj`W}{MuL@pW<(g)i2W9H!~fVPHfYr>MH3KJ4@>WjA1c-F z)7vn;Qq2zy{aC5aOs`?>=4v&a#5&E@Wz$)YY_1-XKKi4YtE;9fTerD-Upl4rnydMr zSzo`on(y-7pt-tadVL!B=^5 zt}d27E?YELH%%Y5Ez?SNZfUMgOefK`sP2*8qHaZX|8x@j71jJ8%Kk-l;q>7=pr~%2 z;(JB)xOAQG7uEjh9r-~~ZB1AGVNvav-jt7u>bdCzKQ5}vrg!TnMfJdRE-#nW@6$`Z zQdZARhre1@2c=j0T3P)yeaNSl)%VjWyfa#W%adm_}gXm zgmk+1v{t(((f77iFHKi=Uu*Ty^cwDOtsaorUQ(;Rl1yG&tKOPU{<2!NcRHoZYt^ag zrz>jJp6NQTtW~c}*LhW~x>s7qcBxKJZ_#mGs`sbEJN2n9g9@L|HS$Z1|?opjHo!}uost2XR5A9LiD7_;m^{C#J zOdQsuIzFAmkPE6~)2m(Og6bRT%7$K0Ju|&qSG%Bka<7JlVHZ?u=^Zlsf@;1gvib$p zEz)~p-N&mpq+eU_@#-Aur){TIFG`=hMo+7bNvAtzT6J79vE8)l7U^vmJFPl4ozl2z z)sg9K*nV2|%k=tonAUP(`n5efH#W3fmGthFFLX@Dj?WiHrFYVVe4#15%*1?Qp2TqP zd?EkyiTmUW3#PYyQu>g#+>u`RuzX>obUla9x{!V|9+5AsH(z?XO1_YvKXz2UutB1J zbiVLaI+tVeh4JaVcIr0i!W-!=J}qCEJDu(6`NEUwEjuG$$Pd+@nJ;unuVVl0(uIxF zyY7H|p?$iZ{54g}wDd7-%on~+=bZmcXn8Ar1o9K;TJk>#-kdMYNbklXUl^2rlcaxq zs-dNK`bd=d!n6dbnlD_NURO)LaCiDZw9gk7PuJXB8jnO55cNcc-^2zf{X+ zNn85Y-5Of9N$>EceBt7Bs`bvYieyS7ApEAO&x~zYbg43 zKR>@{WBM2KhW2kL7LM67%>fO?A~EMlbE$@6(U^0mxpYIZSj@T7T&AH|Jm#Ef4ovsR z#hfF}WgCjVF=tP6P(!g~%pPeDZYcW2?4D--bXxsmcgs7S*MQhv^G+wWRO~K!r!!kR z_H22lQ(Go>=e*Oo4UF9>?{sp@#;)a^&Tdfbw!G8n4UXM0?{t34#qN;yfOLM#$8OC# zo!<(v+vlCmZ^hUxd8hMRDRwpQbbc$xF7r<3Hzanuywmxu61&Jdo!`*d&3UKuTQzni z?{t2v#coP_sdRqBVmIcU&Tn|^^s(;PTr5yoBYpha_D^t%1-oVdZTX*VD^@T2q~G#c z$Xdl33DYbgYsaA>WSy8HWMs?`GAd>WSvO_~SubV?SwCh7*&t>J*)V1Z*(fF<8^;KViU4?Y(ln(O~{t93E3((AzQ~LWSiK8Y#W=9(Xj~`6Pu9jViPhpHX-9; z6S945LUxEv$d0iI*(o+5JI5wum)Lb7YgBegAOE&x(&wsT&AN~d>9csTYnkO_A$u0P zBtEl*>=lQGknu4?$b^_7WMa$^vUki7vQNwqvTw`~vR}*)vVY7FazIQ%4vbC6L9q!r zI5r`N#3tm>*n~`qO~_%f2{}AAAxFd}=_NWVaAPYIQ%yP1jGmDebpLw%{ zoE3+Lkh5ckkaJ>&kaJ^(kn>`Okn>}PkPBjlkPBmmkc(o5kc(pya!G7LE{#pdWw8ml zJT@U$#3tm**o0gan~qY(j30 zO~`Gr3AsHsA$P@IWA>_fBA>^T$A>`qhA>@&mA>`4RA>^@`A>{FxA!JHSLY|0C$dj=Nc`7y`Psb+Y znb?Fp8=H{lViWRwY(id$O~{L}33(|tAuq=!B*o3?p zn~=9+6Y_R!Lf(m87jjSKmGtp%8=t;hE$*!gxhH)gU%XppIa$bu#VhIS_*p_eibF%l z$1y|5Cox0Fr!hmwXE8&_=P^Ub7coP~moY=gS207#*D(p17MqZ7ViWRhY(l<^P007L z3Hc#5A=6_M@?&g5eu_=V&#?*lB{m^5ViWRfY(jpEO~}mHg!~?xkUwG*@@H&9{)$b= z-?0h#CpIDf#;yx_zw%4^__wW@ZvGS>%o0*tKVMGwmt{H)otlg0^e;lDKZH8xTQfyt z96fK^>C4`BcF(lam*u5BPul6r@~S;|+Ud*k7JII=)0gG#?K#sGcA-NG`4-L`LTe7`Oy?BZ=a9~HE}AXUbLpsx5LURu3OnVFI+q!1m)R|9cN+I9YnO{i%TJfwK zI|~R2$ZX9;Q)6Yh1f;flzKK(5tSf3scPbPMHkO%JRMWAS?K+&oKMXL!E4HGCDE>N_(K+y<+qBVrNqCSn4NeM`8 zP`*29;ZT&n9jaKfvCO`*qLGcor3uz7MWY-aiq^G5(Ry|$THg*u8`z;}Lpv00WQU@S z?NGFd9f~%!DcVe+Xmf$0Ed+|T6e!wCplEA>qHP3wdJeh#hwoCWR73+ke1=HuCVvoi$ z`^t(YG!|c`dmU#fn&|jYw6`6K_OV0JzIG_u&kjZV+o9+HI}{yghoXb*P;{_O(IEmw zhYA!;5-2)Mpy+Ucq9X)~jua?5N}%XyfudssijEa1I!>VIc!8o51d2`+C^|`?XtF@j z$pS^E2o#+vP;{C=(dj~6(O!*}4(SiG+S&OF=kcNF$E@g##xncLiq2^)mPn60%u;l& z<3rJTb|^aE4n-H(q3A+86kTM8qKoZNbcr2`F116^Wi~~Z3lv=;P;{k0(NzLPR|^zf zBT#g$K+$yqMb`@y-5^kOqd?J30!23q6x||FbgMwoZ30EN3l!ZUP;{q2(Om*XcMBBV zBh(e0)mT|S0jV9Bzb-mE6df?@wpe4CePu-tHWm}oLn^ZrJ>>XM^spU@9^p-%;+X6-J2o$|5Q1qTa(fdMO(fy5;a}to+IvLIb zq3F=`fLQTCW0`$rMV~Yl_ohd(W-0pA@uBE5I~09xhoUd+Q1qo8ioUW#(bsk;nr4Th zZ|qR?txeH)0!7~o6#XDjG+m(RM}eZB1d4tZDEdX9Xof)1uL4EC2^7r~DEeKX=nsLS zKLv{Z5-9pxpy(fgqJIU7(sP*W4=YmCC{WZS)D?ZySot6UsokF_6(5J9!}8-(m8LTL z%8JUS;@<^BQPuIGsKpLN?d?$1YKNi@b|~s-hoUw+6xHld)X5G-oo$L{6DaB;P}EhR zsGC4hcY&fF0!6b66wM(}G^aq(TmnUN3lz;GP}EbPXkLM$UIInE1&ZbqD4JiOXaRwu z1qF&05-92;)D;y?l?4_`ik3bLYSOwTMR7H%rDudHbCrefH_p=b%mhoZiA zC|c4EMg8nh)ZY$81ME<=lpTtewnNb}b|@NXQ?#r=(IA1M!2(6g2^1|aP_%+T(TV~^ zD+v^>EKoE=plB6=qM-sss|pmYCQvj?plG;2(dq(4BLs@p5GYzxplB_DqP2y(qD7l3 zJ0~EukJ7VDip4_Fq4|-Eb(+fTD=S*BsW@TLP_(||L(v9yDB92tMH|_nXk$ARZDNO_ zP3=&$nH`EYw?okuHbq+s6m2C?w6#FdHUdT43KWeNC>kSBw4FfFSb?H(0!7;k6zw2T zw4*@LP69EyOC^}rA=m>$LBL#|%5-2)apy(KZqGJV$juR+4UZCg%fua)yicS(Jnk-OsvOv)( z0!60^6rCnebh<#%83ILT3KX3s)D=x^s{ERO)UL|+I_@2cR?DB5&TcBRudL|&rlQA^ zq38m~hoTGZP;`+UiY~T8(Is{$y3`Ium)W7{ayt}VVTYnCZHlfED7spp=o*2dYXyp~ z6DYb~py&pHq8kN@ZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssq=pKQhdj*Q_ z6DYc0s4F_Rsj@->Qfp1m%qY$aMfoX!#RE-c_LUVq(o}5KKNLOc_)zqi9f}^eL(vpF z6g^>wq9^T8^pqWnp0-2LGj=F?)~4t=fuiRHie3;XdQqV0C4r)s1&Uq~D0)?(=rw_& zsRBi>3lzN}Q1qri(OUvVZwnN?BT)3NK+$^wMehp~eIQWup+M0`LS4~AO_jqFklG*V zX}HD1q3ECd?2eC{%IqsE`n;*Qe5p|Mh2ulfmv$)n$__<@=m(pk=>kPR3Kab$Q1r7v(Jul;GX#o$6)5^mplGH*(eDC9e+U%)DNyv6K+)d< zMgIsC{VPz^P>GxE6g3JIH3<||1d5skiVC5w=+mak(+NneUwVY2_$(CNm`A%xnSEtN z?JLFC%Y>p<$A_X0b|~s-hoUw+6xHld)X5G-o$XLGn;nX}*rBMaO;I<2qV57kJp_to z7bu!TplD8kqPYZ$<`yWLN1&*uK+(JcMZE-ydJ7cICr~uMK+ysMMGFcPEhJFXN1$k7 zfucnOiWU{>imH`L+rXq~M!t)vrBc78-=Qgu#VTd?l@%>nDV7`*iuyS|6!o`5(EvLX zEoFzIrR`9(j2(&w+M#G!I}{DFL(yQHqU8jNmKP{mL7-?wfufZJidGgV8X{1%ia^m& zfudCfidGXS8YWOQT%c%mfua!tMQaEYttn8nmO#fEm5g#n1Iw; z@~5A^p=gQp4Hm_^l`{LviZ-kidoLG?HgbF@+Sm?7o7kafQ#%xGW{0B9?NGFZ9g4QJ zL(x`tDB9YlXd8i|Z3T)(3lxnJDB4b-XskfdIDw+=1&VeMDB4k=XeWW9odt?^5h&VK zplCONqTL0G_7EuAQ=n)sfuivOMH2*yCJJ>$>sKo0B_Oqt`Rk$$LQ(z;9E-gxW%iX7 z?O!SGUm+A7;P_BFBp=gpFiVm|w(cyL|I>M&tNP(iG1d5Ip zC^|-<=vaZG;{=M17brSGpy)(_qLT!QCJPjuEKqccK+&lJMW+cAoi0#xhCtDo0!3#D z6rC+lbdEsLxk6phzLm;H2}tdw`~~%Xp=e}QbY7**zOtf=Dn;YUq3B}AhoVdDP;{vs ziY~K5(dBk1y21`cSK6WIDmxTiZHJ<3Y>KWGD7sFd=z4*o8w84O6ezk$py+0SqFV%t zZWSoHO`zy@fucJEitZFBx=WzwZh@kE1d8qzD7sIe=zf8s2Ly^96exN~s4KdlQduYg zshyl3jlD1w^+}Jy77tg->?=na9QHwB8`5-56Gpy(Ze zqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>ng}S0gE0tXnklGIUsn(B$qV>|V(~8e3 zW%iX7eN`z=S~V1X?f6hM%??H1*rDiKI~09qhobN8Q1pWxil*D4=tnyg{bW=0vp~@= z0!1?fihdO+`c0r{ra;l}0!4oa6#Xes^p`-<-vUMd2o(J*P}I;IH`^&{6ewyED5?k) zH479K0!8fvib{c^s!&(-MWu3E0#cihpI`K4C|V~!0@Bi4W?xxR`fk+MhJ~Uw$A_Yt z9f~^Hp{TPRie|GzQ5QQDb+toLH#-z{w?k16o1)nTisld~np2=?E`g%C1&ZboDC#Lt zG_OEWFM*=o0!8x)6wNPCw17a-f&xVg2^94aC|X#cXc2*;MFol$6DV3-plAu9uBf%S zGBW|GU7fx&x#-Ybzooxb{=U?{&1LqL6%A-E<`@x*mU4V3TG|dp%h;i4pdE^qwL{S$ zI}{DJL(y_}C|ceQMJw18tte2ml0ebQ0!2dvidGRQ8Y)nTeoB`eymxy-(@qJx@?E7uN12Rl9# z9b$)~L+wyB$qq$_*`ergI}{yZhoU3xP;`_XijKA^I!2)ASb?JB1d5IqC^|u)=tO~{ zlLU$;3lyC!P;`nw(WwGOrwJ6DE>LuaK+%~3MP~^Voh?vwjzH150!8Nu6rC?nbb(M; zbU<_E*#xBadz!_8p{R4d3-ZF|GW*JkE^RKp85xQ$b9^Ye+zv%o*rDi3I}}}IhoY

YAmZDm0DXPtuqB?98)g_>)9sx!52`FknKv6>iiW(76bQl3ehZ9hA1OY|a z1QazUpr{D}MNJ7PYDPd&a{`KvB%tUh0*YD?P}GuuqE-YHwI-mb4IxyNmGJW%ka%El z;)(Dx{U`0iTTUWozD!YmA{h0z6t(00Qq-O;MIG2u)R8Sko!C;;nJqOnx!F$5I#B%r7l0Y$wDDC$E%QC|Xz`VmmnpMatP1QZPQMS}?_ z8bUzPu>=$iC7@^+0Y$?JC>lXP(MSS{MiD|qxe0%f0}?;p?u+uIC}JPcMkiwC%M^`I z1Q&UB0eN0@0_T^aiEJr4jx9x#*iv*nTZ$&LrRW5<6rISHq5`%Qoy0~_Apu2G2q>CL zK+!Y;ii!v*nodB`3<8Q~5>PaYfTGz16rD^!(HsJb<`PgekAR|L0*dAnP_%%6q7nj% zN(m?`BcNy@0Y!@lp`x(~f4>6~zt_HXHcpD_+GqNwBx2^v6rGv~-bs_9Wt?A%PGd{a z>1-)l&X%Gx*iy8DEk$RtrD!EvidM0uXf+!}YX~Shi-4lF1QeZ3K+!q^iq0XRXgvW% z=Mqq~fqrtOKC`7%Y9CxWK#uY*Y47wzQyQgj7digvN3=t{N}?Pg2S zRctA`nk_}wu%+l)wiI2*M$z>I6zw6P=mr9cZX}@SCIX6XCZOmR0*Y=Wpy)ONiuMvv zbUOh>cMwo?Cjmuw5m0nD0Y&!^P_&PLqWuIE-Ah2xeFPNUPe9QFgiz6C34f3S5^rL6 zKRcvozkNh|FcC9frs&Z`Fe@fSk8yq}dYmmqPq3xvNwyR{#g?L{*;4cjTZ*1#OVM*| zDSDobq8A7#dXa#lmk20&nSi2K2q=1$fTGt3D0-cMq5}jJy+J_Hn*|LrUvYjZ`kF08->{|VTecK^$CjdlY$^JlEk!@DrRYbt6#c|T(a!`F{X#&| zuLKkwBB1Cu0*Zbopy&?*ivA>^=r00_{wAR49|DTJq&{s&QG|e^Gy;lz0*ayp6a@qn zr4vvTBcLdQfTBzSin0iyqR$ilD-KA!*v;q{QglJ;6Sic`e3_!^$>8U>6eT#n6eZbG zRD&%=HQ7>Bi!DX9*-})8Ek$+NQdEyEMfKSzYCu3yLjsB#5m0m(0Y!%sP;>+VMcD)t zH71~_2?0e-2`FktKv8o7ijE|p=qLh;S`bjwl7OOC1QfLcN(xW7sI_NkCCA0*ZPQP}GNjqP_$a^&_CDKLJGp2q+pzK+zxqiUt!< zG=zYnV+kl4Nviq0jV zXafO78wn`dL_pDI0*cNfpy+%8iY_3aXbS;F7ZOl(5dlS82`IXlfTC>#6kS3<(RKog zE+wGoGD4_mSmTigqP~s{yEk)O{rRaLL6zyS4(G6@A-AF*uO#~F(OhC~s1Qgv$K+$ak6zwIT=yn2%?jWG( zP6CSVBB1DQ0*dY-plBZfMf(XTx|e{W`v@qypMatV2q=1xfTD*8D0-L>D%zR!+c_Zd z!S>VpS4dFUDf%WETwGs@zUBN<^c`D@4zi`_d$tt)z?PyP*;4cqTZ(>WOVKZEDf*R-qC*4} z{YF61?*tV6K|s-;1Qh*6K+)d>6#YX$kyk^XwxcLQKv5b2MLq#VQ38qr0*cZJD2fqK zltDmICILlR1Qf*yD5^q0QB^{y=&PiEp92!lwfmy4rD(BzM5|UKX1+{OjT*sw4W+0i z=a-^dY$>YEmZCarDXPnsqIzs8s?V0925c#6$d;l;Y!n?vK+)j@6dgf8Q8ocZjR`1f zLO@Yd0*aauP}H1&q9X|?I*Ndz76cTvB%r7j0Y$9|C~8AMQ4Rq`Z3!sKC7>vefTDZ? zirNuEMTr`Iw2@Qvx_uB!)(Ah--{|l}+t-MhFH_XHM$r6lDeA)crKl@gin_6-=xDYS zb!SUa54IE?!PaZfTH096pbLDXe0qeqX;M(O+e8Y0*b~GP&AH!qVWV2O(2AdI@a)qI3V%X z2B(u0&9(cYi8W&8%M?wn5uBVYMJI56DLRoYMFngrI*Bbsg={IB!j__`Y$=+?mZBoI z6isKNXa)gAGYKe~ML^MP0*X#1plA*OMRN%#nnyrUF#$#M2`E}XKv4++MWqB3l@U<1 zkbt5^1QeY@K+$3Xik1*iw3L9NQwbPK;rkhx z+DJgrCIX5!6Hs&>0Y&E%P;>zSMOz3cx{!dPiwG#%Nyk(|^Sthf2}gQfuf(M-Jg;BkqgI|bDA6*< z^M)phb3Jcl;`V&c8=Lr}z2{9#^zP(&lM`ok@w}4~&vx^?X^EOWJa1;=xSpOjC$Xcq z=gm)i(%19K60HY#-r~f9L7ulPapw@vJ0tPeP|sVH=sUvm)+Wv#<$3E9&yVrEO^Mp$ zJ@10V@e@67Yhvdl&)c5(Y_jKFp2#Wiyeku>g`Rg!;_j)Qw}l<=s(l*_9o7m z?Rj@4UYz53`xAAGJ@0|U2@5>$k;JZ2&wC>A#X`?}CXws@NsJc~3zvG{D~Wx}Jnujv zvfT6DP7GY(dG9CAUFmrrCthCdd7mfhul2mI69wx$?_gs0de8eQ@zn;;JCw-Z?0J7C zPdVSc{UgbHx40W1lJvK_TOg7gyv^MNk>tkh?ly=dU%kxT2$5vNo$gkMBnx-Bn<0|C zdbhhBB1!w#?3+cB_Ro>Gh$QXblWr49+CK=K7fIT`=-MHYw11MbOC)LkregO<(*9Ar zUXi5zt7iQoN&9E121Szg?+Oi#B<&xD85v31zw9wKlC*!CVPYg{f4BbRNYegt^phe< z``fLjMUwW{6VHq!?eCYJ6G_@%5IR4Sw7=o8ERwXpqHl2|X@AGsvPjbYlB_c#N&8!l zRz;Ezzwd6LNYehEk@b+#gBW56wLgN!m|6JrYUUkF7ir zN!rgHJQGRUH;!M3B<(wYuSAmet(yapqu46T8?ro6z zZPGdpuNUc*YF?dYc7o0tpV}pKskYLcz^n77dl!y$)pM?NS1Qs?<7qq3(Hbw==&mu^ zu5}NMU)+5|AnW;eC|{`x2-re zb;hr*s6EAY0bQN{1}%!&#&Y8)w;!xj(3d@uIX+*J;&X6K}XL@dUbbNdm>gd z5|4+cjJTOm)$=nrV?16pUM1eey_GZT{_9j(?o^d7KCT&rFRh9$(oMU_s=CP3b1N>g znl4hOs_xDdR9uflRd+S*B_~r)*lVs=NiU>k+epv)T#2LVCnGh|d)2$BPknodwSr1l zFRkvKecT(Tc8CAj>Qrux+zYFF_L&j)hRv^Omr`%tnGr9o-sV2_Jg>fchG)<4yawTE zw)ClQt6^KOXZ`N==T%Ex6?feX=70RLcZrBM(hjpzPmZ<2oYa$(?O;Tr-j9)yJM1a< zZs$%u)(-YA7CytB>VN!kx3fFpC_C6!wdA3--~vXcE}&WJlE>MBYcqO>J5}mWS|s8wApA4M9n!qK9d@)=D$VP#<1u$U;Qn*3 zj$Nu}+ec@6CHZ5gsr;w%e#4#2_X^!v(jtFUtLjDEA9q^!U!-l@+>*lF z>80~?OG~EamK2muEh?B_Qe0LvwXA4b?$nYc^UI1YOf8zWu%xK8((~-}?$lj#=a6Ui*wt~DV|z5C%1HFVM$SLNzuHb(!$c*qILzPWecaxD$Xq{ zE}k=WX5p-PrMWYvPAw=bnVXxRSJ1woU0%EVg8V#-IWFeRE1p-BQ&c!*R!)9i+x9v3 z?6&UN|9V#Lta(%CESy%9JGXG^%vtmPf4>@~OG+!hC1%Xb?Oif$;jDSZeTz$qa?0Np zi_1z-u&l`5 zTArsHx_yU*ZKs-pf@ww53m48QD=1qszo@kBOylKlt7)_5mATC6ZrMp1`&TocIv6@@+Y&i({qCw z>5-tOJLCjGdSkb0<>s~yY98TM_`LsqY~mipMrsFfJGj52!w&AUQnRf)d%Gap&7fIO zvr+28YT8Qg5&Y+|w&h5W=pHn08f2y}rDmAZP7^rpPAv)yUS-`MVE z)!XF=d%HJIyQMe<$G+uHcIu*2cIZOu&6)E$gwN~WSEtE$C!RI5xOjfPH>~%> zg1*DYwhJ%2A7|-U{_;AL+E={XcI7X(Z>5XW6>P^DI+dTQYw9{JoL4$)#=N3w+3uY$ z_2T;KdgTw`Qrr`~n*GaPk9>D!Qm60gPF7Ih&fUIUL3j!I?uBuN0bE*dU0R=tOK@)i zcd}^<=gwUcUXo7RK__)*;bMC0S)I$1d(-kvcYEl`4!pE}6>k>z#?W)!l@H&b?oz@h zDqWe*oYlPj<9(~Ktk>8gW<*vBSVHPTV$ok*9qwZHU zW#NqQwQ;wEds*(jztT;i>(Qa&s=1pzJbC%+g0H-aSEXzD)y{Wxy<__ySJ1oP=+yb# zEvnbZ$<s;mqA;sTW|d{x=^e@Hiv<@RNE6b}vcq zVtUJ!U;qB8>o?op4O7p`)0K4Z6?$F!l)u*Y{+~Kg@A9+f_k&h@J+IsvuU>wa@{7u^ z;0!GxUB}spp4h$gg-4RWj9Cm&ffMa5_OD;cPC+jnwT zq=G*8r|zv4UO#)bU64EKCFi^MhE(EqboXC+R{Qcdp?gDc@(Kyu$lS)|w`&*o_A4&e z>%i!|e6+E9CM9R*0tcMIqeE3N^zv3m>YdF8jIy9vUVP+`N}O}SI0EVqsao!m`4Gu|XAl;k^BlI`4vjI3G>}6le%#C5FvHsCdzlDxl`P6`kdmzvK;qmSr2!!O|#%mIeq@3jya|CbEf5Y za;30j>dYSQ^Rz`>a^|+3>ps(KJ*{+p>*@2eb7o}cjA)mg<379SG1Xmxoau9mN=pl8 z6y?k*nm40tW{*6V!bdK&k<;NOoGcwAfYuogo0@N2|?G3Ac|@_7_n@rbnIfoR3!Q1^%yO5uBqUA=Pi zJcg}!cvbno zey_Dc0@sCc~S?&MMzQSoT8{5A|9 za(V;%_U)G4!rqN~m(0!XKX*#ev}x`^`&hoRk$TVKD;6#P`}>*uLX3Td>mT>Wec5bT zwJKG;7L~q`V_(PVQ?1^r^wq(d=vn^Sv<;E8HCfL+@%UqpK2psa5bxd9ow(4xMB+tq z-IGC=oMCN;^&ULjOHamzW%^keHKMg5wIg-?dXf5(29bu5Mv=qQnnc>#SAhQGPvsQ# zzW=B4v;FcfScTQsSD-kJZ(k*-^v8E!A+WEoRs4y1NjF-QzmSTrUD;`TFZIRo@{{|X z`=V>5KfdR_`&8+V@BRBrhVGkUm7Z&tSN%V>z4VGdzURIQS?Q1O*_ZPw{`g*P&wWQL z^;+9)P{X}G9V(vfCEU|}{$r2)kIh#|!pFJI%DiUN^zrZiUX2WQ{j%JZt>=!1*LGi|c0J9$S!YLgBiL(hNB6AMvA!MMGaK8{z1hs0 zJ>UG;(S5%yb#&ilOC9a?v~I7T9mnbDzL1pK_GMY?3v^tr<0>6D>9|YBJKa}^?DP-o zXkVYS{fUl$xL3e-%zXvlj)%F|#f~j??CEZL+sEoy=w1igb9KDR-SoC^)A4Kf2C)5` zj_usr%63m37rSp%*j}yUeeNsQwx8B9+A!Qn9f!DYY1;EA=(y>Ka9^t9Ywite&;Llr zM$N+AQpYJrhPznDYupWBr@vjtZ(D`?4;?$?guAznOWh4+r$0-_2lB)Htd8jpsy)A^ zjzirIYWp}H&+8KI9XcN97Vb}UJlx&zcKX&jPU{)&1v*~WJKT5bc(8A{|I)G3fN=NK zaoM17pRMCVL&E*Mjv2$kU0cWDBf@>Wju(sy_f8$(924%(bj%(f?i?MbPYiddj(aAB z`)(b7aNkt3*Y6)4yA*`GzmBIDhWi{HA92v_^e^g|H9g#QbsRY}+$ZRG;p}kl((!Hg zb$vVk7dkd64tK7OGZ%z=p^i6}hI^lmKP?P*WKnqRwm3Wv)bWg^;XYT#$CicrWgV+5 z4|jbXN3RHXfsR{OhI_Y;@2(E_S2{LZ8}57^XRizQDLUS~KHT@}_{)ZH`y0b!_s!vP zu#RV*AMTAhKCva-uj*KBYq%TgICfjO3w7MKJ=|C8_`dr-xV?S9(ecQg;clq*L6(X67Iuv9DiH5r|P)<_HbXT zLdd^hvm9=y>^O;l4q~PrnHFk2<#bI^11# zEcrIv%XPf#V7MRE@$VnP9se;r_WLiI|OSQZQS3LWopKdxZse_TiRBO$3>RmTDD2N>-6 zV{}~azQ1YvVjW*{Khj|PJss=0pKY++T*njL4>{OAS;s5gPdnJYMaM7Qk3HD_RmVK{ z^AEOr=(s35+$(k5@4hE%&woiCzAS?iIeztz%Ce-G|@Q^M~j- zO-J`(D%IVGpVYBb$E7-+uA{rVPd$IVj=OcdR>zxl+^ge09q-riNgbcn@f95p=;+?f zQkVaWj_%zfwcWcx>X@aYW1QNKXXa}%W4{2+$ZTOX||Nh85b;@b> z#ees`m+8gsLQ+o`PMK0tv?#osu()rHSDu9>h4W?<=_Q4y_@8BtePdgf=&q{QcB=bE zY?1p0QKgqUy`*riJ5le^!`c>>m6gnzvarlu?Ei;9=FGim%Rduy4_Vb#B3`yV zp+7utrQ4M+ugbCR=Qmxm*TX(b=JK|=r#X*%(re}}&rZi5o_C=Ol`pSRrOT`8p2y|w zaZhs|yNnL*^4_s$>JQJm#_h_N*T!9*-A;D>+`DD@<=y3;w)2<=`;*L%c&FH%qW;+P z?7xR~U}*`;Pn1nV;_t zsXvKhB3?I!JMyyZ$oq;td#F3zNiN#`xqZ%VFE`=-vzN*HkbBbG(=+0oXiw-5mzQ+A z^6C1y>-P;Oaz{?bPjz%EY+Ib0ot>TEIj>WfymnpMb#_nZ<>goUf2U3zva`E%=-j@O zJ6(46NmKxSWtMu5%*OAF4s!EfvFXQ_X#b$`tCh%Z`0aC^7cM-D4PG|Eh7$k zRbFyWd9D9=)1R5hd+3mtKk`tO?p3~zRtcZZ=w8@Ad@9=Aj-MUyng>IJV;?yb9Tf}- z2B#0o+yBq6f8X!j?EC@B+UeUhU zyYgGvUCFda`f2txfk?*1?%_jPT2Ry7Y-wq+vt9J-xK|);SiNC(x@eH&p5tF_ry5cJ zq*RL4w3QKbaqs$R8L<}bEgp>q_7%#sXzWFI5`bvy=XtL)>!v+;6BZ< z7yWF^-EBl|#G=t71N#B$4EtLekJ4}69pPra7j2<=xSQ>~XiLq*+-&duWf09qZg%jZ ztu-6E+0oqrXf|-Oll#j>HS4?C*^9Q-tmkGIFPf`a*Uhf(?+Ecg5Ok*R<`fSqJSJw%t|hsGYR!u3IPVgl%`_I%`+A?XF!H?P|8&)$6KV)wa8S z-L$K?-OgRVqqXC<-Sz9Pon_lyzaH9|w%zqRMmxi{yM8^jW47J(>!qD;+g-oj+JS9% z{rYG}ZM*B&SKEChvQImA{rYLAx!vAfzy8|pzN}Ascl`!vyW2lA8g1r3?{5FBEvBe> z>UYPoW;q|xfw3Fh2~5bbf&FlOO2|;1RYHboO2}|c2^pa&AtN;Yg2+6bAUjgXnz2$`jgklES@IaxatGT8s#-Tqn6xVxL^kWk2McRv-K z6Eis`WPXtP#S6O+S)j8@NQtI|lxj*ynWls+)Rd4#ni6t~ri3ikl#nHw60%eiA*X61 zWSKTXPSZxn>DmZcu8oj0v=OpG8zE(BHfkeelXfU%o^O9YP*xZBVJBJ~3VF-Xh;ELV922r7uwTka z-G^MLvr5QCni8^AQ$jA*l#p$j5^{;AglyN8kV`csyXd`5o zHbSn{M#ye$gj}VKkgK&3a*Z}ZuGL1!b=nBIUK=5Mv=MTHHbQRHM#xRt2)S7sA-8BF z1KIDQ>i2IktyyzVQoAu8oi8HbS1# zM#$6J2zf>uADSPAwOv&nldn-UTa>^{Vc#Eg#pW^ptU*spq~{+{O`qI2svi__Wq&Egnazge8Y z)^8SPvh|zAS#14gah$E+EUv=VZx&Z&>o<$5vH8v7>I8nXI6>eyi<1O?v$zI<-z=_4 z;5UnF5%|sG+5~>HxDJ8eEUru7H;d~L_|4+_1b(x)0fFBvZb;xaiyIO6&Emrd{ATgt z1b(yl2m-%ZoK4_2iyIU8&Eh5mezUkKf!{1{MsPr?McuCl_zyTB@f+>oi603SMNL%m zNX&SdqLz`sepNW7s1@gzqSkCFYQvVI9JUm-WlK>mTZ;17Qk2h@qIPU4YR^Vd2Lg&Z z5>V8MfTGR>6m=n>s4D?Q-3TZ;nt-D21Qhikpy(I^ih2@I)QfR=nquEk4hAl;7*-|u)Ek)zmQZ#`rMHAU5I*x#%Ndy!fPe9RR0*X!`py)&b ziV6rQI*EXyLIR4W5KuIgfTC#x6crIrG@XE=83Yu~B%o*(0Y$S3C_0&dqB#T<%_X2{ z9wAgTG~y3+K;nDdj1H5cfkvu05;I?>s5BDTUsaG&RL1$GXdzpQ7O|!16t)yCW=qi$ zwiGR8OVO!pDO$#sqSM$YI-P)`LR7+V$Lr`+t^Zc30sP`v!&=#wiI2)mZBYODY~33MLXG2 zbOjqly9g+{l7OP!1QcCGK+)9%6kS6=(X|8=T}MFC^#l~{A)x360*Y=Vpy(z7if$&L z=oSKsZY7}THUf(F5>RwI0Y!HZP;@5&MRyTGMHfc=0}e>M&>m1gX(cO`l`7%ZK zMgse*Qc{ZUuQ1l%EMF$Be`ksKI z9|$P=k$|F~2q^lQfTCXrDEgIvqC*4}{YF61?*tV6K|s-;1Qh*6K+)d>6#YX$k(XBf zS$@^j_oE^N6r~YDMej%aX%0yIBKM8c=m%0{KWZKI(_-e!6vfg4`>UE#iZVFA6lJod zD2pvcakdmyVM|d}wiH!kOHp;U6eZYFlw_l*1_4Di2`H*XKv8W1is}$hRF{CFdIS{J zC!nYS0Ywc7C~8DN(P0D>9Zo>e5d;)v6HwHcfTAV@6g4HFs2Kr8%?aEW9Z5jZQG`&D z`|EYCb3o!3+7}el)56d6588cEi?o>eGDU6D0{g4JQi^gozZA7)OHnRcit^Y}l+Tu; zc5EqX&z7PNY$@uplApIMaL3QG?Wl3YL(_6bU@-g-B0&K zTT78|pXm=viQZ$Jz zMaQ#IG?{>+69_0ek$|EC0*X!|ps0|5qA3IvO(mdc8UaN`1QbmtplAjGMKcK~nngg- zYyyf-CZK2z0Y!5OD4It=Q858U^9d+gKnN9$Nb@^6Ao109Uo=vRmf1(NlC+rlGDVBh z0{g25Q;JUE{8F@-Ek#S%QnZvUMW?c*Xc=3IPGd{a>1-)l&X%Gx*eF^-K+%~56s;tn zXcYlPs|hGtLqO441Qe|$py+G@iq;WObPfSU>j@}2mw=)T1Qcx~plA~TMVkpII*)*& z^9d-rfPkVc1QcCJ2o;s3`O6%T_$d1l(LyP@!|sbNN{g8f( zBZP`BPV*mfK;oMs4$d|yDzW>b{b@1tWr`k13+%5tO(}Yi^Gne~Y$K+$sq6g^Ks(F+6=y+}aOO9T|XOhC~q z1QfkWK+$Ui6unMB(E$RA-XNgpO#+JEBB1DP0*c-tpy*u!iryoj=zT({=)N>RqqQlr z&-Cw?q9S{A{XtsHe3_z8(gORda#M;v<@{3g8C!}zXG_r+Y$^JZEk$3krRZz66n(>% zqHoz!^c@>T2MH+po`9ks2q^lIfTEuWDEgUzqF)Fo`jvp9Lj)B4MnKW;1Qh*2K+&HB z6#Yd&(cc6V{X;;J`#I!G+|B5|qwa1%`?1pq0Yzy96!`=cMF}Vh2%(~n(){5LNZfwr zJo>Q|9kh||$IO>0%JKvItCmxW;+$WKs<5S~DqD)Gv8AXwTZ$5FDN3@Xs0Le#YOV zfTCsu6g4NH=tu&Jjv}C_1p!4Z2`Fks2o+`c{sj(5e2V?JP^KS#rvItk7q#|d=F1f2 z`hopb-6=(RoL`Fa*;3SwEk*6wQq+MhMIG5v)QK%co!L^#}H7|lYpXL1Qhiqpr{W4MSTe<>PJ9Pe*%gI5KuIbfTBSJ6b&YzXb1sC#}ZI9 zlz^gP1QZP?plAdkRFvcUZ#p3HOYEUgTNK%S(MUgLzD&_rKd`^*J*8+I=a-`KY$=++ zmZFJlDLRfVMU&W4bUa&%CbOmJ1hy2N$VO2C0YxVfP*g}j(G&uTrV>yzjew#e0*a;+ zP&9*pqL~B~%_5*^HUUK^6HqjVfTFns6wM=`sF;AF`2-X#AfTv(fTB_YipmI~qS3ye z-N7k}+uhF?DcWIQ$X@8j%$F%z;s?DuNzqcyFGZ)arDz#jicVuo(dld{TF#cDGuTqJ zf-Oa7vZZJx8%3)KC|XTG(Ha7Z&LW^_EdfPm6Hv5{fTD8j@~@LqO3D1Qgv!K+#PE6x~cf(JcfN-AX{wZ3GnUC7|eb0*dY+py*BlitZwy z=xzdv?jfLP9|1-C2`IXkfTH^dp`z`+zsCWIk1$1-O3?%x_xmyPWr`m51N)~+Qi>ko z{8IENTZ$fIOVQ(ODSCn}MNhJ&=qa`oJLtNzq`tFZ$SznJ-iHxgXd+b(2!`1?QKdFWFM`6}PXdbmBB1DR0*d}2pva5r({>a^2q;P;pvWhnC`v$4KtNGC0YxzaiZTeHqECIl zivtqxYG1DYOo~pmN7tFrnE5hARilCZQ%NaB)i}QtRcA|4f-OZ!wiMN1OHoa>6xCu& zQEj#q)nQ9fT{ep95l~d0fT9Kj6g4EEs1X50hY?V8H~~dR5Kxp&Kv81?ikc8m)Rcgt zW&{*9C!pv^0*a0zpr{1_MJ)*^YDGX%YXXYe5Kxpu2o=Sn{^<@#e2U!{Rf&e5>7Q$l zuG>aq=F1ediw5>jZKV{o=loLCfh|QH*;3SrEk&K#Qq+YlMP1oa)Qv4gN3*4Sy(HivF^%I*ym3m3CjWI2towrf69-uz%_=rRX%yFGZ)brD!=@iq2q5 z(F(Q{oynG>m24?m#g?MgY$;m9M$uUW6s;wo=xhRt))7#24gp2$2`D<3fT9fq6m2A+ zXcGZNn+Yg7kAR}{2`IXNfTAq~6kSL_(M1FlZ6%=SVgib`5m0mq0Y%#hp`xWxf20Ev z?_fW7eX0~?xnFpVUK)*=FH^KL8rVM-nNoBG=a-^gY$>{uEk(Q8Qgjttimql$(KT!- zx|S_P*RiGOdNzvo5Kwdj0Yx_wP;?UkMK=>rbPEARw-Qiv8v#Xo2`IXqfTBAHD7uq? zqPqwvx|@Kadk84nM?lej0*dY>py)mVitZ<%=m7$X9wdZ{c0~OP9gz5Ic3*V46fLli zXb(kW=F1d477gs58civBobyZ36KpAZk}X9~v8Cu~wiG?XmZE3bQuG{Kik@dn(F<%8 zy+}aOO9T|XOhC~q1QfkWK+$Ui6unMB(E$RA-XNgpO#+JEBB1DP0*c-tpy*u!iryoj z=zRi;J|LjzLjsCEBB1DF0*XE%py*RVsOXWX|F#1X?_nRr9+jef_L=@?(U|!%MPEe& z`=@GCioWLjQuGa5ioRt_(RXYqI>?ry@7YrH16zuIWJ}RcY$^JgjiO%&DEgIvqC*4} z{YF61?*tV6K|s-;1Qh*6K+)d>6#YX$kr(LGb`(VjC`u!s$S0sEN?2y0AZETyQ6dQJpE^z{N^*WFs==0` znrtbm#g?MlY$>Y4mZG|BDXPboqWWwpYQRQOLjsB#5m0m(0Y!%sP;>+VMcD)tH71~_ z2?0e-2`FktKv8o7ijE|p=qLh;S`bjwl7OOC1QfLd8h?F9M2s6HwHLfTF$x6!jyZs6PQk0|+P@NI=mb0*VF`P&9;q zqGJgt8cIOXFanB(6HqjQfTEEE6pbRFXfy#uV+bf3OF+>$La3;H;NR$g#0O1m77$QWLO@X|0Yzm5 z6fGp6Xb}NLrw~xIn1G@s1QabLgo-8x{!b1_{84)-bet3|u?I<~1~Kzxik1gK?eS7{ z2IrTe6>KRwlPyIn*;2HMEk&!@QnZFGMQ5?4Xf0cc&Ss-%9RWq>5Ky$9fTD8=DB3_k z(MAG_HW5&?nSi462q-$AfT9ZsDB40m(S-yQT|_|9RsxDHCZK2=0Y#S(P_&(ZqDu)V zx{QFL9fVNPX@TF(0f|qvPs>i1qF?R4=<*de~ zkoYO~P-vGFJ?@?teKd%fFH`hn5bT^JMNe^lDSDbMMbEIM=vlTDJ;#=!=h;&90$Yk+ zWJ}RYY$a^2q;P;pvWhnC`v$4KtNGC0YxzaiZTc& z$|RsDi-4jy0Yy~^D5^?8Q8hxS=+VMcD)tH71~_2?0e- z2`FktKv8o7ijE|p=qLh;S`bjwl7OOC1QfLEUPk9qrTp4(T!TWs16_2c?Bl)Rpr~Q8%^}9nF@a?rbUQ z!Iq+9*izJ!Ek(W9Qq-F*MSa*P>PtXTKLU#S6HqjOfTDo}6b&MvXfOdqLkK83mVlz6 z1QZP;plCP&MI#6(8c9IWC<2N`6HqjUfTFPk6pbUGXgmQ$69_1pNC*{mO82)qAo1n) zL9DYB-DBSlIW9eBzD&^x>A~GorRYS?FGU4xDLRQQMTKlBn!=W%scb2l#+ITYwiHcg zOVJEAie?f}G>d?u*#s1wOhC~b0*dAmP&AK#qGAGy<`Yn~fPkVB0*XorC@LeMXdwYb ziwGz>g@B^P1QabHplB%pMW+%_w2XkF(+HuWQ}j%FaL#NgdY1D`(Q|AmdY&ysFR-QPMYa^Z z#FnC$*;4chTZ&#~OVMj=6unMB(E$RA-XNgpO#+JEBB1DP0*c-tpy*u!iryoj=zRi; zJ|LjzLjsCEBB1DF0*XE%py*QqiasNt=yL*!z969JO9G0%BB1DNLa6AebpK`tB>ts+ zM0;9_+`lg7K4D9bnJ-iHeR}ZX94Y#N^Gnf>Y$^JQEk!@GrRW#76#dGUqC;#c`i(6` zzq6(24>pSaB%tUo0*d}7py(e0ioBRUZAVdrfTA=4ihKf!q68EL1QewcP!uDeD1(5a zOah9s2q=mZP*jD0qN)TGRU@FNIsruq0*aD^P|TfTC6e6tyOxs0{%{IRq57C7>vmfTBDCit-64YDYj( zdjg6&5Kz>SfTB)>P*JUz-`xR;kFn46YsbRR^qbme`kiAj^JR*Tjs+(ykfQFKUy6FL zrRW&86!m0FQ7^U>^=3;^AGQ?rWlK>%wiNYeqi6sDMFR;a8bmJU5Kwe10YyUz zC>lmU(QpEaMi5Xml7OO71Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTH6FD4Ik-(eZ>( zQP-G%rUMdx*Ue}*DZ13|izdfn=F1eF6bp8hN>L%_m!c_bDVoZbqG@a?Dq>5~bhZ@D zU`x?VwiL}`OVMmLicTh=Xbu5Ia|tM#M?g_A0Y&o(C|W>3Q3(M>r34g}5m2;{fTBeN z6rDmq(P9FMmJm?1lz^gB2`E}dK+$Og6rD~$(Q*Qc&LD(}PK^0aI3V#>_Gwvx6iu)X zZ!2Ok^JR)w$AT{wO3@n5FGXjurD!c%iq2+B(K@yiox_%*^=v6Rmn}sb*iy8SjiOBi z6m2G;=sW_7&L^Pg0s@M*5Kwd>0Yw)PP_&hRqKgSA+D1UpB?J_0C!pw30*WppplAmH zMVAv$w3C3MD+nmsML^M&1QhKigo;+i{A!DwqMdF=S4q*c_E7t(Sj>ExqU&No?qVsr zp7Tr59<~(Sz?PyL*-~^9TZ(RGOVKTCDY}&{MYpk~XfGQ@w-Zow2LVNQ5>Rv(0Y!Hc zP;?IgMf(US+D|~yy#y59M?lg21Qb0$K+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qb0% zK+%%~6g@=<6#EM~q;(etrj;ZiAjf%8kzi)<-+i7iDh zv!&=2wiLa}mZI0#QuI1oiVm=)=nXcC-Xx&tEdq+(CZOmY0*c-xpy)jUiry!n=mP?Z zJ|v*%BLa#(CZOmO0*XE*py)FKiasZx=nDdhz9gXND*}qXCZOmW0*byRpy)e7sOZ_4 zzs&)OPqK$X&q>k4c3*Tb7BgR_=%-k)ZQl&5Gwj1=D+WN#4oe2I{qj{wT)Em zjF|Z{MfEd+$Z{!a!1<-9AzO+Xv8CuRwiF%CmZBrrQk2b>qQ-0~YQmPHrfd{7BcP}` z0Yyg=P;?XlMJ)&@YDqv*D*}pI6HwHKfTA1%irNxTluJNS9sx!91QfL+pr}0oMI8tz z>PSFQCjyE(6HwHJfTFI1P*L3s|40WUzQBG+wq8c~nf@^Qh}JD5X1+|(F&V+Y6;jlb z^Gi`LwiNYdOHm)T6!m3GQ9rg6^=C`b0JanjWJ}Q?Hi`xlP&9;qqGJgt8cIOXFanB( z6HqjQfTEEE6pbRFXfy#uV+bf3OF+>$0*b~HP&9#nqKO0)9Y;XXBm#<#C!lCD0YxVe zP;??8RMb7gpW}eUOASsBDOzp!MFkl#^JR*rW(4Q1l%i>zUy6#@QZ$_{MKjn^G?Ohw zv)EEJn=M5rv!!SbTZ-ngQ8bT$qGAGy<`Yn~fPkVB0*XorC@LeMXdwYbiwGz>g@B^P z1QabHplB%pMW+%_w2XkF(+DU!oq(d{1QeY?K+y^Uiq0gUXeA+3RG8u4>VU-S+e4u# zQqniq2t6(R#KNoy(S@4Qwge$d;l_Y$@8zmZJ06 zC_0~jq6-Kp+Co6lg#;8`L_pD20*WpsplBNbMVAmzw4H#WO9?2tjDVsY1QcCPK+#SD zimo7_XcqxRR}xUPn}DLL2q?OmfTC*%p`tYz{vih>eq+SJIZKK<7^!PBV&=;f-H;K~ zUn@m7a(*egi7iDpv!&=3wiMmUmZIC(QnZ&XMYpr1=nl3N-N{DLT?7=}O+e8-1QhKf zplCkWII0YwiJQ1l1^MUN6t^cVp}j}uVz1OY`)5>WIM z0Yy&}Q1lD|Mb8pKMb~He$2cJI;ciCvNKxEAqCJ-pGhe3YrHr6pofN&y`K9O;wiLa} zmZI0#QuI1oiVm=)=nb|My~&oMx7bqjHXB9n5K#0k0Y&c-Q1m_lMIR7Q^dSL79}!UW zF#$!N5K#0f0Y#q?Q1m$gMPCq5^d$jBUlCCBH33E65K#0j0Y%>tP;`)hqVEYP`hgHC zdLhGK<$$<59|z|}DcWUU$o?@SX1+|(uNlGa^-^?*^GnfhY$^JkEk%E@rRYz#6#d1P zqQBWv^bcE#yi9%GE=3VGiqZ%u@(C!45>ONnP?SzUQH+413<8QW2`I`UpeRm2Q56D; zsuECCjew%+1QaC*C`uAgRD*z`ngkTpBA}=?0Y!BPD5^^c75$vyKjnbLXWQM+FH#h- zQ7PSFQCjyE( z6HwHJfTFGh6m=t@=x73px)VZ04Kn@2MyKfdbO)zlX84)@dp3Gx#>|%~>YW+nZl;c(Fg*HMiNjo zih!cg1Qd-SplB=sMdJu48c#sc1OkdC5>Rv;0Y#GtC_0{iqR9jloj^d*i3AiC5Kwdy z0Y!y`P*KlJf4l<{A8mI(y`-pB>JzrinE5hA(=&rp&X=MYoL`D&vZZJiTZ(40rRZd~ z6wP5v(Ok9^&0|YZF_dN2q;=jK+zgPsAyWIzuf_e53swR zA}MNaKWubXX3Tt&GXjb}C!pvH0*byQpy(?CioPbG=oWI#0YyI$Q1l}KML!Wx z^fMt;^m3*@&jE>#FgUMB(bpMn{E`_nU#95y%wXeoDf)x+OVOWfDf){oMSruU=pVKe zd0G0*U5X-XDN18Ykuoq0Y&Kq6vYTA${?U9lYpWu0*c}U6jdRhs44+P)d(o6 zPC!wDfTAP;MKuU0s!2dmEdq*a6Hru#fTFqt6xAc3s6GKj4G5v4Lz(_w2P9r-kBfej zqIQ8B4YOkA%M=}v6})P$dU7Xpg9 z5>V8QfTE)bDC$l?Q4a!&jv=6^Cm~dHSeF000}_weU*&jsR`{9z2Xd*P5XaHM^2C}7S5L=1{v!!SVTZ)clOVLoa6b)lb(Qr13Mi5Xml7OO71Qd-X zplA#MMPmsl8b?6Ucmj$h5KuIcfTH6FD4Ik-(eVTnO(vk|1OkdqB%r8(fTEKKC@LhN zXbJ&EQwb=VMhF%4$?|(SAaVPfilTj`=vo^^Suyivie_a6g}bC^Hs_b3li5-cO&p06Q!j!n z&M!r8vZd%PwiLb1mZEpqQuHocir!;O(fe#E`hYD(AF@&O5dlRX6HxRC0Y#q@Q1lrA zMV}K;^aTM$UlLIC6#+$G6HxRG0Y%>uQ1l%EMF$Be`ksKI9|$P=k$|F~2q^lQfTCXr zDEgIvqC2L-*-{i`OHsgpyAfPCdfTAn{isA$mRUx3LDgi~+2q>yfKv9B# zq9g%DH3%rGNkCC80*Y!AP*jJ2qPheW)gz#&J^@7y2qW^5^H&X%Gh*-~^ATZ&q+rKlxaidwOy zs5M)P+OScSLqJhm0*Z18D9R(CD4&3$b_5i)C!nYU0Yx1NDC$H&QD*{*x)4y*m4Kpd z1QZ=jKv8!Bih2-GbPNGSJqal4MLOv{;YjBwsAcCO#dFcFX|hQ znJ-f`FdhWANYNn9FGYjdQZ$4uMaQzGXee8XhOwn+I9rNFu%&1uTZ%@pQ8b!>qA>&% zjU}LH905h+2`HLCK+!}3ijE_oXc7TM#}iOAnSi1b2q-#{fT98dicTV+sE~l7DFhTv zC7@^;0Yyaw6ip|fXa*rv)IaXGazNru>^mR>r05*?yy(n$%zT-mIq~4w+oWhN=a-^+ zY$+;cOVNC`6fIy&Q3+d$O4(9W#+IUmY$;mAM$st*6fGv8XbAyDO9?1Cm4KpU1QeY{ zK+)+06fGy9=nMjiRuE8hCILk&2`E}cK+$Rfiq;TNbQS?cYY8Yin}DKq1QeY^K+$?a zsAzWFpYMRgm)f`SPnM!N_8{rpc+7m6qRsJO^X*b}9_N>$^Vw2#0b7c;u%+liwiI2& zmZGg}DY}>~Mcdd?bO{?p+X*PT^#2fd-_cRkZQu6y&YsN-Ov(%aLMIfZrqQc}-a9BF z8bSyJ1OiDwK$Nb42q+d*R1_>IC>9hIm1;#nK@k*1u>hiUjDqleQ1lW3MK2Rjw2^?KR|uY>WkKf+0TMiGz5}vc73G?b zXs-tS#+Om_M$kR*rYd@q%d4WzY*q9YTNS;{Rz>fyRnZoJ^(KeAQPPi$3ml&y+>W~-uK*eLpyfTG_BC^|+!(QyKb zP7qM^I{`%}2`Ku5fTBMMC^|(z(P;vT&Ja*^mVlyj1QeYopy&btMHdMu`ip>~LIR5Z zCZOma0*WpXJVghCPDcR}ykx#abVwDAGNdjC{l=G3WJSAKTU3!9t)I!OqA0d1a@eZK z$5uryTNRaJt0F&J6$RL;s5Dy@m0_bONI+3E0Yxzc6vYxy6h}Z&h=8In0YzmAD2gYb zs2l-BlXPQ6>RJBMB(VBA{p#0Y%va z6pbdJXbb^GIRq4qC7@^=!Bf;d+9|h96uIWBjy+V7`3Glww?_MoFQX_o+HJN&6;0yu zs%SD>73Hy2Q9fH06|hy&6t*gw%2q|Uu~pGDwkn#=M$rrcif$*MXeI$gcMwo?CjmvX z2q>COK+zlmislkfG>?Fy`2-X#AfV_j0*dY?plBfhMT-b1T1-IEJp>djA)x490*aOr zP_&HTDVh-N3=<&1uI35#L{&7@jOEdOTD%#3cMcde_ zXggaK?O>y5Cjmvf2q^l1fT9lxDEf$iqK^qE`h?Z$>-63Xou9^X_M}Dyl9o^Bs!z z8(&7z_wxU<{zMi1z~xoZ5wV< zogkp-cLIt|5>WI90Y!fjP;`obqSFKvogtv;ECEI52q-#FK+y#PiY^jR^cMj|g#;A+ zO+e8<1QcB&py)CIMgI~|bcNt4`YzgOBtU{G=Bti}Rnd*+GySX4e&fq1a$?**yH$}d z=088vciF0_6k8Sf*{UeORz;=Rs;CTG6$ROvdfT9oqMPUMp$`Vi% zPe4&Q0*cBLP*j0{q67kpDiTmsiGZTY1Qb;vpr|SVMb!u>s!l*r4FZZ12`H*bKv69M zifR))MRtsnCqROG44kMK?{lOeqIM*@mE5m3~bfTAu06m=z_s2c%A-3gweYh#?v0wh@9 zz^SW>V$6rP9x;C7%P8s-;~w0riu!VSRn(8Iiu$uv(Ezq88pu{fgV?HQFk2N3VXLC+ z*{bLUHj0K4P;?^!MZ*Xvx`}|I;RF=jOhC~s1QcZuP&9&oqD%scMiNkzML^Lg0*bN; zC>l*b(HH`XatJ6IOF+>$0*Y=WplCb+MH2{~qFyo16#)`_*1Rw3t%}T-iF^}d{Kl72 zlo#XH*r$r}xx6YWV5_1jY*jRst%`1AtD5& z=y?K)))7$j0s%!Y5>T|BfT9fq6um@1(aQuBZ6u)R6#|N0C7|dv0*YQIplA~TMQ;#L z^d`Ym^k9s$SbzjSF<*6jNEQ8VKGWYE<2SyHqAfA*iw9KEyIfusy~kEX@3U3WR<T|8fTGU`DEgd$qCEr@ z?Iob-3j&J1B%o*?0Y&=>DEf+kqOS=kIzT|tHv|+NB%tUJ0Y%>uQ1l(aQ}lL>vsZuw zzcBB9-cdyr&38Z!$M}seqv*#N_sl_6^b?m?MMv4H=x4Sn`h~5Eer2no-`J|?7+Vz` zXRD$UY*q9-8$~AxDEfndqCW{JIz>RyX#$GQ5KwfMfTD8*6rCra=mG&n7YQi(i-4j+ z0*d}7py(e0iY^gQbeVvne+ekMLO{_~0*b6y{lpwaHo;T$LyS}5kSKb?ye~SUiq4w9 zJ{uM5H@=LbQn7A}?^KbW%d4UQTNRaNtD-V&RTN~aqG+}%ieamwShgyPW2>SN8%1FP zipmmD6i+}=IRc8x6HruvfT9EfiYgLNREdD1$^;ZuA)u%#0Y%jaD5_3CQ4Io$5(y}( zNkCC80*Y!AP*jJ2qH72!x|ZN6^2IvC1xWA}1ILZ^KGTOnwJ zPXda15j;ipW1Xi3NbtD%s$&CH^qV2oJJxS}8AbhL-5p0%(Eu*5iUzV((IB=e8q8Kj zL)fb5dbTRMfvt*$vQ^QIY*jRjjiQ?fC>l;c(ai)D-9kW71_4DQ2q?-VplBokMOg$C zjUu2Zn}DLx1Qd-SpeTocqOk-NjU%AwRsxE~6HqjPfTD>66y*|7G>PCT>Kp4E6ClBK z^Y^a%siOJj+4baDzwu=hO^J0&A5}$Dxx6a6jjf8Nu~pG@wkn#zRz)fqjV^S zBB1CE0*c-wplCAzMQ;&M^ftj$v@+Hy5Fo*O%~u^CQAJ10`=WPZ{l=G3^nR@S;BTsE zE0qE84Y`jmj8-2@bUMnKW$ z1QhKdplB}vMPCq5^d$jB`v@r7Pe9RE1QdNuK+ypLioPMB=pX?_hX^S8mVlz~2q-#C zK+*RE6#YQ(6ulekye&Y2HOy0?_f*j@=C98liS-*_M$yl)?zhKP(Jx$H75&OqMZd9C z(J{6vI?h%_C)ld!ceW}z$yP;wuvO8YY!sa$py)IKMP~>oI!i#&IRc8#6Hs)4fTD{8 z6#Yd&Q6T|Ee-lvj4*^A&2q?NtK+(Sh6kQ>p=qdq4R-As?jv||Yq9_8290H1b1W(aV zv5s{@6m2zdj;f*=hLjuUH@=Lb(s6Fhld7l;msdqWwknEdtD+dTDvD*RqByoH3b9pD zn5~M+vQ<$$8%5;^C@N1tQ3V2u5(p@&NI+2~0*WdVP*jD0qN)TGRU@FNIsrvB2q;P< zpr|GRMYRYhs!c#q9RiB3A)x450*dMqP*jhAqWT0+kw4DqDnNqk&38Zoao%V8j~Y@9 z;{3*!QIs6#j`>p+rEqywl*(2`X>3*0n5~MMuvJl0wkm4IRz=O(s;C896}4oes1*T4 ztqCY_M$w=+cf)B_G?>e) zq9JTmbUj-Y-N05wL)oh6Mz$&%##Ti)u~pG@~UVCTNT~TRz)+}s^|{3 zD!P-cie|A@(QLLVn!{E_bJ-}GM?leh0*V$8P;?goMRyZWw2*+JMFbQrCZOmZ0*aOp zP;@T=MN0`NT1G(8asrC(BcSMh0*Y1;Q1k!+MGq2C^bi3>4--(dlHe(t8s}6zCyMSi z-$%Pm6@B8$cqGnmd>KWL$GNR8sG=vhyefKWIC0Y$G8Q1luBMXwW3 zw26SCHwY+tlYpYl1QfkRK+)R-6um=0(G~)V-X(a79*c8s5g@^)=6%sBRkYN6czZ9- zZ+sa=+vD6>f2pD!TwWFJWUHcGY*q9DTNQoCRz)ANRnf<6RrCp46@AK9MZ4K3`iy|0 z&j~2nLqO490*byMpy*2iiuMsuw4Z>YuLvmmnt-AM1QdNkK+!=0iVhJ_^eq8J-w{xB zn1G`12`Ku3fTAM=6#Ym*(N6?V(bhO;tpEx3FrSufQ$@?ommrVE`He55=(jj`*Waq> z7?)Q?$Jwgr1X~sT&Q?Vy*{bLdwkrCQt%^>uRncj-DmueP(OCkD&Jj>_o`9kY1QcB) zpy)3GiV6uR`kR2Fe+VeLL_pDH0*d}6py&z#MOO(ZvO@Z4JBn-qilPW8atJ8$5m4k3 zP*jS5B0s@X^h=y`LVyHw%m=YwRna{2z9^^g5l~d0fT9Kj6g4EEs1dQ6w?0D`9|CFD#MAi;~~*>x(4%sZxmA;0lu z6kQ*3AGXXDq*}fkxV$PF%2q`;vQ^PAwko=bt%`=TRng6CRdfqm6=kqh(Fit*G6^Ue zNkCB+0Y#$-D9R?FXfy#uV+bh9A)sh10Y&2oD7uw^qVWV2O(39XA^}CY1QbmoplC7y zMR^1i;&K3a@+-bgbHbfQ0n9uZY3;B&Nqv-aKdpJrJ&E)c` z=nl3jx|6MnX0cV#Y_=+z!&XIe*{WzBTNTY`tD*&L6x~HY(cJ_TEhM055dlSu2`IXU zfTAS?6x~Ze(NY46mJv|2oPeVH2q?OrfT9%y6g@yd(SrmOJw!m!!vqwqB%tUK0*W3b zpy)Azr)YY}iE>0yf%!t?3{~{Hd0(_D)fqjV^SBB1CE0*c-wplCAzMQ;&M^fm!S?+{S5g@B@W2`GAxfTH&aDB4Q!6g?4g zx(kqCMf2|GNmaDpe2%s)F9|5xM?lej0*byOpy+D?iVhG^^bG+;2MH)TL_pEE z1QdNoK+$0WioPeH=m!Fdju24vBLPJ}5m0oLfTEuXDEfuqDcTWomI{#Ib>@B1PF1wV zJiGoiU_Y*kc&t%?%Zs;DAc6;)!Rs4@XXRR}1mNn!cOIAQS`m}s$*=}`%HhOd0&(o_8VVDQPZ&7CRPqbs?arD*;8_ z2q@}KKv53@ih2@I)QfgL(?kg(tQGKy{tyK_RSXc(7QMK`fk(QvjZx|ywtZegpU47Ms7!B$0? zY*jRpt%|bPC>ljTQ8ocZqX{S)LqJgu0Yzg8C>lpV(X9j&jVGXJ0s%!62`I`XplA{S zMUx3A$|ImCpMatQ0*a;(P&Ac*qT2{4nnpm;bb_bohOqOj0156i?~8`2BFlV4n-TUK zUq;cLVfVwbs%RFMS4Fegs%Q>d70qRkL_pEQ1Qe|#py&|- ziXJ7P=rIC{RuNG2H~~dZ5IjXQ!_G+o60C3D{oJ97)|v5S*l&CpMQg%tOnFtbmdmT6 zXV|LfS+**Aj;)HGXRD%hY*q9ETNS;?Rz>UCs%QfnMK2Lh^fCcO8wn_Sg@B@02`GAv zfTGt4DB46o(HjI5y-7gPW&(=dBB1DP0*c-tplAyLMeh<&^d134?-Nk8m4Kpc1Qcy2 zplAodQ}k5WX)Hj3{mtLre_9n?Fy9W@8TK1rM$t!McTj>V`k2eBqEFbW=u@^T+Rau) zpRrZZ=WJE9hpmeCvQ^O+Y*q9n8%6sFDB4dz(N_c%eN8~o0RoD?A)x3W0Y!%hDEgLw zqVEVOI!r*(_XHIEKtRzE0*Zblpy($8ijERc^fLiPzYtLLD*;8n5m0oD;3@hb>`W6N zL7(~Ip$}EjKk_o)@vz_cGK&5PyN^^-MSpU6RdkB2icYgt(HXWXI?Gl?=h&*~JX;lA zV5_2wY*q9Z8%2c#6#Y#=(LV$fT_T|9G66;Z5>Rx7fTF7e6j^2U({>cu1QbOPP~;F$ z1uvJk4TNPDgtD;J5RaBX+imI?xQB^jIsu56B zoq(bm1QaC_P*jtEqFMwL)h3{*4gp2i5Kwe20Y!BQD5^(5QGEi68W2#_kbt5_1QaC^ zP?StSQ3?S?sRR_I5m3~a;3*1~b$nGt(W~YOb-1kenf?O7<7-mZZ+sa=Ey}vrR98hU zxx6ZB#a2bF*{Y}wTNSlstD<&nRdgL&6}4xpqI9+@>cB=(M*@mE5m3~bfTAu06m=z_ zs2c%A-3ch_K|oPY0*ZPOP}G}%qCNx^^(COF9|1-E2`CysK+!+~iUtu-G?;**Ap{g% zPe9QP1W!@3vQAF{5^QMTG*?9d^S)?kS-h>WZszi;=oYpr%3!Oa z5o}eI$yP-p*{Udut%^pmRZ%uu6^&-2Xbb^GIRq4qC7@^=0Y$eGP&A%^q6q{PO(dWw zmw=*41QbmspeT=kqI?313J55gLO{_}0*Y=UplBKaMbil=nn6I(?F1CfBzTI3m35X2 zkYJYin;|!;qL!%EjW45UPFeSrTB>L+msdse*s5qgTNN!}tD?Kus_1UEDq6@^ zMT^*~XfazA-NQ!F5(0|uC7@_20Y%FQC|XWH(R~CI-A_Q#3Id8AAfV_$0*W3Ypy*)& zidGU(^aue(j}lPy7y(7A2q=1-fTAY|D0-5BqSXWxJw@;o%_{4BEkJ_5%Jj`vMW@Vo zx~$*$vf`{LU+vO0ueGhv2Kkn)720FKh0e%#Yy+Wq`D`va)J(n!7Yf}FV_D@wkHuM5 z#n6vo%c>fxTh6i)LlY`kR-Mpm6)me?=6V*mNhLjxw~b}487UYvSx?=?QL1} zL!J6r*22)D0hYBSv}cfIEf1By-m)GD-89s)R)(G$W?8F3zYVvn)uE&e%UT=C&$O)P zLvLkS*80%ZY|Gjh>XKtwuZQj#XIYy=UyQe`Eun;5%i0>cd9r2g46VtxtdBy+r&!kR zP>TF7G4_V0%&@Hep?79l);A%0mSuex>Ndx+j)d-=XIVdo_ARiiW1&h5E$d_`W3gqO z4n4EPvd)KoUus!}p|txf>vH(E6>|UE;ddXD2fz+HE9DWe!#y6AhrkXmTP2Ty9scSG zc@XSym8axUu)~>a>iH~Ttv*!=Iv>)B!R|C4THht2;GIMoiD|D$VD zJ8b@!oGtCJ`F|?5wZrCrikEJO&HvS`vmG}7TdMAM*!+KmdfVYsTjepa!{-0&G1v~9 z|24x1WQWba@K|7n%|FpM z%?_J?V{N7#HvdT0Y&&fJm81D~c*hZWgzT{ScSe@jVe=0~EVskvC;cC=!{$e|SK49o zv$m`3u=!!h)ppqYwA)%cY<^tnc{^-=-ekQUHa{@1(GHux@%_3THh*PzvmG{n=W>f3 zHh*bus~t9f>uIMQHh*p9BRg#V-ob7=Y`$^4*AAQS{Oz~H=36)4*kSXv_wVem`Qqsj zJ8ZuC^|Ku|U%ohIht21oC+)EL1md(EHqQXh+hOw|ywDDt_raHKt869nwf(i;AG!E0 zt~{7c_==foj>!Bh9MN)|{b*j%DT=TE@NZ5i!!{B3UIbvnK(Bcr{J(dHJUdm};qJXz*#s%ZBw6<+`Ti|Olvr-J3gwhp!lwhH!$m%B<|5|9fwvrH)!C+9UM{PA`$=$+G+8Hll*02d4f zV}jAamU4fTPWX>=m63CmxcZ<@*L!WzdX+NGRmSL5MqXNcm9cu2dagLRkXw8^LNRhP z&1()vPKbrF`X=csiBGoMSK>z0trWJ)mP)VqaK}pKHI{Qr+`OoSH#^FmQ@-hcw+ba& zRe5Czi{{#L$3EDxQkq;%#l>@NE2`ps9V^P6pKP_S)V9*Z*vPAt+hC~ZuaF#Vc@HcH zBh_b}v->}(FDp72g|;=o95~Z}qBBLwi_9-`6;W2|lh?^HU4GlvaQScKS5^71`S?=o z-n*hm(*Kw%=GSx~?O2&|ktq98Y>Z{gFL{}9nw*@Hmzgp;e^N?*URFw8Mt)Xy#-zO5 zg6yn<>`^IMdDABq#}WsXnD&&kZoPRYxjn4O=QpOW1;BfntEsIj>z1-ZH7vvM-WPRvgkla-Z`nKvON zEj6P_M&s1RX&Gs$CMHQtnwUE=J1IMJ=e|mn&dtyvZN{75rQ^ror?Ub9Bom6yROe@HX+$G*U(myYEoZRR6DT5|u z=H1$L%EXMp^0tiWKYmJn#=s8E`!xICc$lVU7G#@y%d+%=Zqht6Im@CMva|VAVc^J>eMAeZev!b+zAtMCrXp|J!lzguGdSJd|+@RG@T~4 z>&E|2zufpzwre|MlHGWxQljgYN^#4}`6Y%D-O}!w7r=ed1+Ls z#*rK)7jWgpQO@*4H^H2!t1nL}dU>PB%cmuKFK_-|FZV8go4(vB?Y;gexkcs`o7WJz z;$-*Q$aJPAyXDO(ea)rpQciSYuW)3Qv7-w7row2C9YC$U}G-Oyy#r5BDZPE#Qd>iCT5RH6daLP*GX?z zT34<`PVi=SDSA87E1Qzd7JWzJ7{Q8bOYoLExP8SSJIT%(Yg4}kh?(7C^y-=8|7NO6D4j!3oa^mUgU*x z$Li&p63qH3T(z03)veTSkxmS{LSj(+r% ziCJl>Y2I1Vitm&Xk97;Z1|AQOk-5&6#rK%ppWbye=JgdjNGpbrRziY2Ncw7v?wZI$ z5xHF*vhy1^Yu+tuLg(zrGm{~cM#)E>4jnoVnxgMiJL)~eW7VqYTI5mCySn)O84qN$ z;+yOtiQG5EF49WC@Id@;K5gPzm-oRq@~WH5y-@t;f%mg%h&3-Z=aZwpO=5qH5T6jfXO|iFDrs153ctbiebw8 zE;(1^$|EllHF_!en4_nP-Vj0WU0&X8Tk@PW&%0OByn}wgEq0bx46TTNu`l^pF4v!* zlbcsi^x>0-&e)AS=tYlr(Fc0@V;Z>)<}rx?k$b~CQG!76L!MUrn5Pv#=sY56a$_SG zmS+NyBlmck{K@dHwZsEj{P@W$*ZU?-p1XKwly?q#qUbJ66G?i$5+4xK^b+!@7T>{g zs$1V7iJe-tN;FUJlhYE-6a3VcjhiOc%gY|0otd9qKQU=S)}$%zvg97io|ZJBNfQYL zIa4N#l;h~}xtRq?^4UQB_@qYOzPJ-F-e}}w#$+mkTiNic7A^5nCztS*%QYU4k)u|dv}FAS@2F2lQkbZ^vyOL|EG^~9?KFRiHq!s-NXRy(>&l2De}=kZ&vXmw{_l+DxATZ`WD@hr6XnPTx1#kAu0iuf*i@Qa?37CqN2 zdRkfH4^r_ThvFxNJl5V*Li45+J%--%N~>F^POTH`nLj!m@+Ks9nJ_YY)F^pAKA2Cc zBY&FsWV!zT{AWwP8Y*7~xGKNoYa26Tqhl=j>PFEo^A&_nv4Qzf3+&OmcE(yAT1m(> zpNv~}ikx&?CiO|~)1gOSt5n$Er?gWhP}Wz@E^j9|741rPWxI-9)vg{@%TD&bo>6qY z=0wTlv(8*C`9kMEUTVH_;eD-x^El@7(GtHL`CL@K%vIu-&kD;LT2%Pzpcfn~@`c2r zmpYbwDXhdV$C9tqm-yvaCBML9ZjXHRzQiv_zV2W0mlJvI#l^AY>qjMiIab*c%UoZ1 zOTPLad8^HRURK_o7A4MMz7WLc+TL@7It5mpQTkl%|NfllKc3FX)eMy1)#c`xdmu{Q zO!N3h$(?8JFLNxfNBI(?6(ujMX^!&d*3)htcXK}Zov80@-pMGvt9X=f7KzThqM#nI20u^>(}-d&>iA&VQpG?{DetC-wMEYj6Le$LjLHoAWo+ z2YRvZ!gm0_MYC}qsKrWZA+X;H?pX2SD_4v>@Z?Dngck&0{T>iKoYvp=7MUOd?y*)*bFXemt9X+0( z;%$4XcWgb)J9g9K>>1v^SC1de^!7eIM$htgB|Q$D-KJVB=k8@Xedzl_TdeGZn=`nVtx2x!J@T1<& z)Z?S8y#1UWk38Y+KlFI*Q{HZ($MI{tJzbBlKI858^;r0vx83Kx<8?21$6k7zzuw#T z>G6}7ynR5Ap;x?JO^?^V=Ity!uG-}7b$a~iO>dvlW4*V%-As=Yw|M(@J-+^)x3}r> zpRL~ZZ}X1nJG^5bJ>Ip;+bi_A`$KOZ)MMFCyj??&Lw9>STaQnC?(G-#`14+GpV4E3 zeco=N$4Os#`wl(6alqR<^mzH8w@V-Ljvc@Aj{Wqw@Oy7RsK?Kbc>7yDmOJY0ntB}e zi?_$jFl_`DuB>2bRr_vrCEJs#KN zMLjz5y<2m8L*^*AvxDv~dX%Rvksi=voF3!#SYMCw;X86Z`LG;0w$x)^J(}ll=K6=} z@fJOnGDo@ckZw6d&d2MWWS&RK<>cv%6(z5{BIirapFW`=bEK7=Uy$b=b2ufRZx>j} z<`Y~id1QXRl`NlonXBHIXjU73q zK(6-x>o0j4Cx7z1=gHm4tRU*_>NzZ%K!((*f9ew$wv+uD)quOO$*dCYI~`firr+y*&mt(M)X}@a{>Lu`EHY4^7St7Vp}7m znb&JNuXnMW<}z~9`d+Rt(VWmhU5l?TMqbACy)37>jJb~32DWtv4|a){y(p(kUSCMA&pb}%_L=tyT;Dr# z+FYOUV1C_`WLpEHz0>Bu=4Iyh2YTduhg;c^zuzJ`@{9AyhvEOYef3(~5kq>m$m=zy z_sH*(x36M}x7WO{;`SYp)AHs`l0)RzV7b253^|(DYkrv{e^$(1F6T>^m>{RkXTj$B z%>8a&XNkMZ+S|sqx=7;}*B6#h@_hB=_MPTTa^!qP-`^gcoSTxEn3&cgwRy|b#w{DS zkkhHDX(j&Kym`~a#8$1+S~ZsQB_@t2GpkGQuHIje@UGaF&wjaHQg7W%?g z{Y!^#%9)+Gz0gYQb$0fk?S&^(XVo_U?R9o_WaXZ|>hwEbF>G2+?UlXdn7;PR$x$`i znp4{gk62%1ZZGtu-QR1OyzEG-yp}Yp;iW@znNYveR-oVM*`@oP4#oC5d*t?h=VzBG z^VkoCOSV_Zxx1&_inP0X-Q8oST(kV1?VNeGlib$jM>1t?l;20>_g1f1XX>V}xzHqj z^@ZnB*IekG|4qxQe_gq{v#{#worQbn936X8ly&BnIi1dymTNef+VA|ZCULdAQ`b6^ zdQ9prr$h2PF;`yOk>wM69?hKC>p!nys9eLP+5OJHntyXo^Y+NS6L~wjTnsvCIdcDm zC*_RnAxC>icX>NQ@gtm^C+y4n`<>r9sDF2YwEkboVUOX}>rC0kN z={-Lvth)7s!jqHiwmal)mfwl;+xqK^^s^&VTlKiM=Z-?3y`ykvh_}zY26JocN8ZM< zk^ioX{P%cH&tvA%|Rk!=8%(^}6_1GnE zr@2?~h_XZLz!>7MjOR!isC%8RWfR$z_2?(l|jgEq9=O;Gw(Z+mWnKAu`CX!y%b%6`a|W&%9J8o>xw0Go+L-%o zsWbPL*+0iw(qzcqHocsmkJjszcA{Zo)AX~MP2|r?TKdHWPCs$EHkErv9;M0M&c?^L zH1~)-E%M*Zk^dG({@bOyJZ^HY>=X|jdKNvpMUUHcJ=*l!FOMzvTpJ$QTjX(T8>(#{ zwBSHsU#m9e6IN-eU#5XP_D@NTHftCjp94V*_~F2@}JalgXOflO#V}F5| z^@@%6%h+l@?)ZO_tF!&JYrIdzA)>*Ms7n5|F`neM1O|7#+v@u=O>Xli{_^rv|5N`fa@%(Mv*hjl%)e63`FY@9xi=cwfv4qW zCE0=dePs0c7z>9KsJ!l8a zUwwVZ4!kCJ+rxHXqg=~MJMg)@@sHSn8|7t>+JQ@Q^B%JU<>jq9ZwErMF4%!<<)i&Y zJ1|dP`(Jh-PA*Vr2i}$&HZ&^GMPAXCsK79 ztUl=k7RvqdhZDG8?uI@`jyu0*<_fGftqMyxQKrKzn($eSCoya;y9L z0(Z)z-_I9lC0Ewp7dR?s86f{x8F||W`T|LE7~~7olGis_qFi8zFEB`qUhfP1DEI3P zzJUBCS!<{-ut;3q=nHI+D;wquRF}u)CSPEvJZ!^#ftq4xqc2b(H=>*y$d|XMyc^gk zH)5I_=p*;ibT`mS9?ltV;BkrHxq&5eorm2(UAZH_cLP=Bs()|;Uw`H$C@P(Z73x8m*T>MLapryRpeg42jdC2$s1Bc}%edP~4FZaaP{=jaD z2mFB_UYf3_3q`a9^69SGr;I}0N zvgF~PmJoPI?!oB^ffSKDBO&mqJjAyr1g?|YIWr;fjJyqZBm}C<4ZKs9TzpnSV5r=Y zvl9Yui-|c2fjx2~(pLpW$*b+KD)6;jS;tj@vvRj~UKQA!XjxrW1>)om>AET)e`DS1 zwkj|{?uq_80$<6?2J8rQl*5P3doTtE?Fz=$Km=jCo zZk%dP%#~}IEe~nwU2^6*=EP{Zp1J14t8z!oGbg6hlE3b6PJAej!2)w)l-&JynG@g3 zZMoZ=*durPeHn71iJZ9KoTwqUc7-`{O5U;u%!y<2c0XuN)R9*)Jxfjule=z)IT87E zMBd|@g5ZoWBJx`NyupE>cn+>Nd|(L?@_$lpVkD>Uzi&526_ zDPT^llh;++oOn|nh%)9xBe~|FIq{@iD%zZ=DfhMfT}i8SAGuVlIbr@^ym98lM{?$n zIWbnw6E-KN%EMdMocL7kG4lbdbQdY*%!$wBK`w7joR`;SZguI3^6<%*WUSIX<;F*u z6XoPpm~SbTzFGbh`OFE?EpLUKSSqiylsU0M-Y#>l(!)iYZB7i7J3PvqxGZnGxtvvI zoLrG_qV24fEg$+`k=GRTEt3)LbFX!ix4usA2g%$9 zI=!DGa~taPevHg*q|^H;GB-)5_d{fEvQF=3$lMg2-j9&EsXFy1$lNsD`U7NcW8M1m zV{Q}O`r~76Q{DR0V{S9u`om*xbKUy0V{QxG`lDlROWpdDV{R+m`h#O`Yu);DV{RMW z`eS2mTiyCoV{SX$`a@&xb-MLu#@zP0^+(3sblv(BV{QlC`U7KbN8S4KVs0nh`r~45 zXWjbKVs01R`om&wSKadX$NJnlPCt44<7NsU_nOGhKF7_FKh|zHf0F#cH$r;3{e)CR zNN>HU3hAR$h4j^_Li*`cA^ml#kO4YX$UvPcWROl3GFYby8KM&**Xu^e4Z0CBR5wCy z)Qyl~x)E}dZiEcijgXslBjgs{2+7cmkP*5OlBpXZBXuJrOE*GB=|)JlZiI~1jgT?A z5t5@DA!BtTWSnk<+^X9X(!-f7kAK|#@*d0W=?SSO@5|lsej~>SndD9uJ`o|4^`a^y zPp1mW*Qr7ZbgGakI#tM2ohsxuohoFSP8Bj;rwW;&6Ct!8QlnZ zRyRVP(~Xelbt7b*ZiKv`8zC?1M#y^I2-%<;Aus7h$jiDBvQaleUeS$^S9K%gHQfk# zT{l8D>Gp)Ia5l-~ANQ&}wQ(Qtg#0MMeZz0$7$I-Fo8(DSM94dOQ5CX9rwVyjrwVyb zrwVyrrwZAsQ-y5PsY15vR3STbs*s&J5wc4+LO#%qkPmeuqf{P-3ZyM8zEolM#z`C5wcG=LiX!M$XB`%^0jV+9MFxBZ*(K%pl*a5 z((MV^>>QBCKW>jaX?5T7gnTSd=iP7pMvf8kgL^wV>(sHah(V`p&KE;>qf{)-3a+ZH$wi@jgV8i5pr5LLeA($ z$XVS8Ij0*T=XE3Gf^LLd)Qyn8bR(otH$wi_jgWtIBjl29gk08*kbiX}arWl zm(qg z+|UF zG}L^G!yYAfTut0Y#k%DC$f=Q5OP=x)M;-jew%=1Qhikc#7)U&Rqf|)Wv*Jsh%pDE?-q~ zd)j{E%P8t=yUz)%h@yU6UKRCctD*sHRWy*TiUzS&(O|YJ8p2jZ*Rxg84Qy33l#QYr z2`CyyK+#PE6b&b!=wM8>>=q!Q0{QBk+ea16mG?nzuI)FzjG}zo{X@R? z7*SNfCOK+zlm zislkfG>?Fy`2-X#AfV_j0*dY?plBfhMT-b1T1-IEJp>djA)x490*aOrP_&GIqU8h> z-A6#t{R9-PAb5%<+fG^eU=})Wo;c^JqP}K4VEc_PqiCh=Hj(c?L=-*3OF+>x1Qb0>K+$sq6g^Ks(K-T( zULc_8MFNV}6Hv5)fTEWOD0-QIqKyO;y+T0Is{|CiMnKW)1Qcx|py&+(iryrkXfwf6 z^pNcg6(FG{=6TV>s^~!Eb1~a*d>KXW+U|7u)>cH(dt6=>z0X!fTiL2;8(S4^XRD$e zY*nh2`KuEfTGU{DB43n(Ov?Iz969J zO9G1a5m2~^n5m59k0Y%>tP;{8!DSF3to)93R7Yv*& zs%VycTg?65_8VVD(NDJfzI;C`qUb1>S4BUwRnaeORrD)c75&CmMaS5x=r~&yonWh? z-`T3@BpXG45K#0d0Y#?>C^}6*(HR1Y&Js{`j)0=`1QcB$py(n2MSl@cR7gP4-vku> zLqO3b0*WpZQ1mYWMOO$Yx=KKi6{VkdqsS(pD2m`II$}FN3y{z`q2&IkisqZ|PdQP3 zyZKv5+EiYgOORE2<|sst2OBcP}{0YxP#`m5#d7r6DJ{Kl72)F{gBRZkTq zad}mg%vMDyY*m!XRz+!SRn(ZRikh%hQB$@mYQ|PY&DkhwK|oPU0*YD@P}G`$qBaB+ zwI!ga9RWqx5m3~gfTDB)iaHQb)RBOqP6QNnCZMPb0YzO2DC$N)QFj80dJs_5lYpXL z1Qhiqc#0ZCIg7hmC!pwN0*Y=SpeTcYq7eiXWfD*{l7ONt0*Xcv zP?SwT(P#pS#t=}HLqO430*b~FP;@H+MdJx5nm|C&L;{L(2`HLGK+$A^r>I|)^M(Kk zZIizk-$yP;o zuvO8WY*jRit%_!|Q8b5uqPYYV%_E>_J^@7w2q?OXfTFtzC|XEB(INth786i(4*^9> z2q?OjfTE=Y6fGm5XgL8z_YqKZKLJH62q=1hfT9NpD0+zCDJqC^E(?&*D)UvxDXOTo zdB^l{l;8L=iXMw{tEH%-Ra{;bJKtR!p1Qe|&plAaDMK2Lh^fCcO8wn_Sg@B@02`GAvfTGt4 zDB46o(HjI5y-7gPW&(=dBB1DP0*c-tc#0m0aykl-&=vFL>PJVp$q8)5iw3DrhcCl5_2W(aJAzKxF#8yQgvsKY2Y!rP;K+$djiasNt z=yL*!_7G6Cmw=)#2q^lJfTDc_6zwOV=qmz>z9yjP00Bkc5KwfGfTBYL6n#rT(RTzC z9VVdYdjg7nAfV_7!Bg~Jl(SHPgs#Y6#&zFUMa|?{wfkd~-}o|$eu;9|HBm*sa(Pws z8(S3}W2>U$Y*loEt%`nUtD=)^RrCj275&LpMW@&(I!!>)83KyV5>RxGfTHsR6kQ;o z=pq3{e-ThrNI=ow1Qh*4K+z=viY^mS^e+KLR|qJ&N2qG zTNSlntD=@{Rn&@&qSgcywIQIWEdfRC2q?OafTH#U6r~eT)PaDajsz5SBA}=<0YzO1 zDC$Z;Q8xmLx)V^;gMgx*1Qhimpr|(iMSTb;>PtXTKZ2(y$#I4WkWgjw?k8ClB{?$s zJAUKKC>rdzx3^YBL%6&ux}L3yZeXjTp=?!jBU=>>W2>T@*s5qaTNT~RRze|uH*B$ro3tJ$jPDYhzlnyre~ zuvO7owkmptt%{yytD@)Fs_1z(iq;WO^a24zFA`9+o`9ka1QfkQK+($t6m2A+=oJEr zUL~ODH3EuWC!lB(0Yz^RQ1m7NMVkpIdW(Rfw+SeEhk&9j1QfkXK+$^yPthvJX(T{G zC(UT z0*cNPP;`NSqKgC+{Y5}gApu2y6HxRI0Y#SxD7s8Q(Z2)~T_K?8Dgi~7Pd{x(kxf8R z6ahsJ0YyFnid+JUN)b@xC!i=m@D%;(IGY7XXukRTMZc+{spdN%rG0+m%P5NRxd*$b zqF64kisIO+D8yDpVYVtN%T`74Y*kc_t%}OCRZ#`DDoS9Zs3HMHl?W)ROh8c;0*a~< zP*jb8qUr<`)gYiKk$|F_1QgXGpr|$hMRf=$x`u$FYY8Z-OF&UQ0*dMrP}G2cqJ{(% zH6oxWiQp*;`kX5QB=oraWU?FW^FGsm+x%Q=vd?dP8AXkKZjJ7$s0o)>MNQeNs2N)o zHD{}$7Hn12lC6qbu~kuPwkm4FRz+>uC~8MQ(RBnAwI`q`oq(ba1Qc~7pr{i8MV$#K z>Ow$KR|1N<5m3~ffTA7*6!j#as22f6y$LAlLqJhq0*d+(P}HA*q5%XH4J3GqQhiQm z0TSA5{@!((DoQnDkk4;?8AUhv-0YsJXegIgMK`il(J;0ux{0ldhO<@C&1_Y43tJUs zuvO6rwkpbGqi7@nMOg$CjUu2Zn}DLx1Qd-SpeTocqOk-NjU%AwRsxE~6HqjPfTD>6 z6y*|7G>L$s$pjST5m1y*Kv4k!MN}D!P-cie|A@(QLLVn!{E_bJ?nB9$OX7XRD$GY*lm@8%1{$P_&SM zqD2H0EheDo9s-J%5Kwe40Yys*C|X89(Q*Qc?jxY+egcYC5K#000YwiIQ1lQ1MGq5D zw32|LM+hi-lz^hg2q;=b@D$DPIeP_2=x>?s?W(Aj`4Z&gKELs06g}m0&-7JAPjh)y zw1%yU*0NR6Gi+7#EL#;l$5utpvsKYLwkmpot%_b`qi8(=MH>hxdWnFdmkB7^NI=mm z1QfkWK+$Ui6unMB(Ix_l-XNgpO#+HG6HxRP0Yz^UQ1lJ~MOz3cdY6Er_XsF@pMavR z1Qcx}c#59%ITiYeqI2f2H?CGi<;=H3w)_0Xmr?YA&uuY46@AF%RnbRmRrE1i6@9{1 zMW3=&(QdXX`i!lLK4+_z9yjP00Bkc5KwfG zfTBYL6n#rT(RTzC9VVdYdjg7nAfV_70YyI&Q1lZ4MMnuJ`k8>DUkE7rmEbAb>2rn) zkWjSwAht^trA5p5&F441jH2It?j3_v(Mc|^ivD1$qCeTH=oDKOoo1_|Gi+6KmaU4; zu~pG|wko>7M$ttAivA*?sE~l7zX>S%hk&9>1QcB+py*!$imnh)bd`W2`LXQBTe zXZq2u-}o|$Law`Gh$;$mc~w-Ft%~B=s;C@W6_sbJq6%zPl)zR+71^q&5?d8jW}~PI z0Yy~_D5^$4QFQ`}Y7kJANI+3d0*Y!8P*j_MqB;Z=T|+?8wFDH^C7`Gt0Y&u*C~81J zQ9}ZX8WB*GL_kq80YxbU6r~b8MX|1POn`)Xn7^17=X#&%Cz!uJo96nBFQcfL>y{p> zikfqIRn&s5idwQ&Q7g78YRy(fZP==)En5|}W2>U;*s7>K8%5~^6m=k=s3QSIod_uE zOh8c=0*bm4P}GfpqV5C~^&p_ACjmvh2q@}JKv5q8iuw{z)Q^Co{sa^aAfRX<0Y!rd zC>l&a(GY^CsEO+&3y@HufzwnK<(V%YUGMshFQaIf>-HO_if-cas%SV{72V8MMYph3 zQ3hKTjbN*yOtvZ-$yP;KY*jRhjiPJPabfTCLoC>l>d(F6jD zCK6DTOF+>i0*WRRP?SeNQ9c1h1q2jLA)sg~0Y$eFP&AEzqUi(_%^-M+hPqCH012g< zzjuA3Dtbu%Ay4;q*Kd3oMYCM@!QrZCHkVgLbJ(hAE?X7NW2>V1Y*n;?t%~kqtD?Kv zs%Rlw6)j?;XfXjr_YhFDgn*)Z2`E}hK+!S+ik1^lbRPjl_Y+XGf`Fn22q=1xfTD*8 zD0-NHqLl;`JwiayqXZN^MnKUj0*W3dpy&w#ik>8Ritccow*^S3viys9?wzWrby&t~ z*Kd3oMQdI6+gnu8GhAL3JZ+)zF-&f8fv#0*1?3pB{ z5l|E(peUVyq6`9xG6^WkBA_UnfTA1%igF2|qA&dDCI=+m+7x{$MUU94>sDzo^JR+K zr1@7iN>N+3m!f=TDM~O)Q9EWSYR@c19hjx4BeN8BVwR%L%u>{a8AV+QDB6aAqHY8f zbtj;x2LVMr2`K7CKv8c3inb-7XgdOm`Vdgmmw=+}2`JiufTDf`6!j;dXaE641q2ig zB%r8}fTBSJ6b&YXit^H;&p9CR!fp;u>$GrB|8#ps8+8Ul)H2`H)~ps1dJqA3IvO(mdc8X;6P zEG^o8o>TOcJ&6sMqR;Ft$mwY@^JR*5PxD9aEk%2#`7Tv=EiC@yn!P!lU z3hYPL)}_VFmnk|p%|CE~6m4L8DLRB%iVkI#qQjV_Xd|-}9nLI8M=(p#k<3zb6tfg< zVn)%?1QZ=ZK+&-T6m2G;=r{t3jwhh#1OkdqB%tUd0*X#1py(6=icTe<=rjU~PA8z~ z3<8SIB%tUl0*cNiplAyLMduJubS?o!=Mh3h>(inaI3V$N?5Fn+lA^Wtz;u3E%zT-m zi_`oE7fI12Y%fKZGE32A%u;kYvlLyyEJar`OVL%#Qgk)56kWqCMb|Q;=sE(5t|y@A z1_Fw1B%tUf0*Y=Xpy(C?if$#K=r#h1ZYQAV4g!kqB%tUn0*dY?py(a~itZ(#=sp69 z?kAw=0RoC1B%tUa0*W3cgo-Xqi+<*S#EQ1mGQMV}E+ z^f>`VUl2k?kEKNiIw0|5?Q^uprRb2T8@^17nJ-iHZJIxMnG}7;_EPjcvlRWnEJZ&u zOVLlvQuH&k6#c?1MZYpj(QnLB^gA<({ve>}PXdbmBB1DR0*bttcH2=DA)u%Q0Yy;) zirkMxgrC@>$S0sEjew#U0Y&Kq6lD-llu1BQ76C=s1Qg{EP?SqRQ7Zz9;sg}s5kf^@ zr$tvfAn_yJpSJeDk)mttR~%c%V&=;fC1U<5E2O9$+e=YQ6w?00N2%2q+pzKv5w9MS}<^8caaZ5CV#Z5>PaZ5GraLi{9aY#MjzeMES9B zPe03^(T2xj=F1fA81vuUPl`sfy%ddMmZF`QrD!a(6z$9`MMca~G>%z{ikYRTgjtG8 znNd_mK+$*tiY5?HR8BzAE(8=!B%r8*fTBqR6jc&XR7F5hH33DF2`H)|ps1FBqB;VK z>Io>CLO{_}0*a;)P&A!@q8S7f?Met0jf_QGta6IR*kjQsDLTUx?G}rfFH^K<%3(Lw@>77pLZf-az7BgR_=+Kxyf2|Z9#`aRQky(lkXO^NP zn5F1QW+^&~S&B9>OVQEHQgjTn6dlWqqRj*p9Y;XX@dOl|KtR!n1QeY_K+(wr6rDmq z(WwL!okl>>=>!y=K|s-&1QeY`K+)L*6m21(=o|uy&LyDeJOYZ&C!pv80*Wpqgo-xA zqQ^KO@y_-Z(IHZ_r@eQ5Q7mS@OwnaA|LS#8bUE8g(G|>6bS1MCUBxU#S2Ih|HOx|U zEwdC|$1FwHGfUA8%qY5%fTEiSD7u+|qFV?kx|M*U+XyJSoq(b{2q?OffTFtyD7u?~ zqI(D^x|e{W`v@qypMatV2q=1xfTD*8D0-NHqDKfQdX#{o#|WXKOJdO%9FX|^_S5^9 zO3_>Pe$nHxnE5hAPsjWp*GtheY%fL6GE32O%u@6`vlP9+EJZIeOVLZrQuH#j6urVM zMXxfW=rsb0UMHaF4FZbZB%tUm0*c-ypy(X}iryul=sg08-Y1~w0|JUZB%tUc0*XE+ zpy(3VwMLQnk6m4qb;5;Qo#rC88-^60( z%M|?(^LN}JML)8=6#c|3ML#o3(J#zW^eeLz{l+XszcWkGAIwtpC$kj&#f+lA2`KW? zwabm72mwVc2q=mYP}GuuBARJSp*bi6Ht^xKv6CMMXd-Z ziW5+jM?g_)0*cxYP}G(XD*7%K-O~Yy&uH)9d@n`!n4If*RC!lBw0Yy^@D4Iq<(R2ceW)M)cD*;8j5m2-{0Y!TdLPev~qhB~6@sINz zoH0_=U_(QC%zT-mS?PYxky139?WL%ZS&HT`OVM0rDVoPDMe~`ZXm4gI+J{++7BEZE zLS_^#BA{q70Yys)DB72RqNM~BEhC_4IRQm02q;=fK+%2#6s;nlXf**vYX~UXpMavZ z1QZ=WK+!q^iVh^8XgvW%2N6(oFabpy2%(~x>Cr(BNPJ^Q2WKxS^6br{L(*gB%M=}+ z?$>UTq9fQ|ijHKKqNA9lXcMy(9nCC7$1qFLvCLAmnOTaCW0s=hnNf5C0YxVgP;?Rj zMJE$bbP54QrxH+f8UaP86Hs&p0YzsLP;?dnMQ0OGw1t48a|kFpmw=-42q-$AfT9Zs zD7uhqFV?kx|M*U+XyJSoq(b{2q?Of zfTFtyD7u?~qI(D^x|e{W`v@qypMatV2q=1xfTD*8D0-NHqDKfQdX#{o#|S8ToPeSy z2q=1z5GuMnJ$jb|5}%ju;9Ma^@7k{wJ(V6aU#94}bpP$mQuI9AOVJC=QuHFT6urbO zMK3c;(JRbS^eVFyy~Zp>uQN;08_XzrlYpYP2q=1+fTDK@D0-KGqW1_WdY^!z4+tpw zkbt6(2q^lPfTB+bDEgFuqR$8@`ka8GF9<05l7OPG2q^lRfTC{*DEgLwqVEWyqG!^h zEst}GmfFu^c%Aj{mv{!e=tkYpUhJ9 z7qb-o%`8P;hW6W~D8h`Q76cSU2`FkwK#@;CQ5pe7F#?Lx2`I`SpeU1oqAUW6vI!{4 zA)qLifTC6e6vYWB$|IntH33C!2q$v z{iS&F(dOHmJIDeB2AMZK7%s5i3|ZOe?J z?FcC9LqJhq0*baLplAmIiuw^y)SrN&0R$8k5KuIbfTBVIiUtu-G?;**Ap{f+C7@^+ z0Y$?JC>lXP(MSS{MiEf7BLPLD38A8n8PUxSNIYSGZogATxTk+^o*Tww#LSl|D$4M$ zJw=MfvAq-(GfPnkvlNvwOHmoK6pd$=q6y4WRL(3#yD&@9L}nCK5KuIUfTBtQimC`G zswSXlG66+31QgX0P*g`iQ9S`gQwS)UNs<}pjrd}b-y zn^}tXVV0r=%u=+FS&9}hOVMIxDO$peqJ0S{T1r6CG6IU06Hv5*fTEQI6zxYq(JBIp zRufRPhJd2|2`E}iK+ypN6s;qm=s*IB))P>45CKI86Hv5)fTBYPC_0pYqQeNGqS+bI z&Zj#?&)aTUqZGBU$D)lHG4o}Lj>_=IoGC?{*j|c`W|pF3n5F1gW+~dtEJepLOVRPn zQgi~d6rIQ{MJF+%=wt$lP9dP^R04`lBcSMX0*cNcpy*5jiq0aS=xhRtwh&Ns4gp2y z5>Rv=0Y&E%P;>zSMHdoKbP)kX7ZXr)2?0fy5>Rv*0Y#S+LPbYpME7z);-&V>Lq|%{ zMEgwtij0`~GDX*9_#4iaqHEb+imqdpqU)KZ=musfx{+CmZeo_Ao0+BP7G^2Bm05~z zV@A>K1QgvtK+&B96x~HY(cJ_T-9tdpy#y59M?lg21Qb0$K+%H)6g@;h(Zd83Jwiay zqXZN^MnKWy1Qb0%K+%%~6g@>i(bEJJJwpf;U6m2N!~u!7wV%7bT8b_(MbBo$%$F&8 zF~fiK94UHW7eL_IdrvwyzMnKW$1QdNiK+%^36n#ZN(bohNeM3Oe zw*(Y@M?lf{1Qh*1K+%tcP|@=l(XSkk_zU)-#|u*QlD$a!DI;dSOwn%{eyj7P=y$f4 zqCc3W=uc)T`iohL{$`dUFH?K&QWRm9q87|j6lIp8mdq&f2`EYS*yKv6aUML7f%me)^ljT(T)TZjV7RI3;{(u5l}Ri5Gv}D8C~Om#PbYJ z*UWHF{|*~=&WxEaQ&f`apK-Aim9o7Ql`%`vcxEY@z$``O%u=)qvlLBamZAz~DVoGA zMU~7bsv@AMnt-Co1QgW}P*h7mQ5^wA^#l}6A)sg~0Y%dYD4I?{(F_8Lb|s)_Hv)=w zC!lB#0*V?4DB6>NqL~B~?L|P*ECPyV6GBDfGNbo6Ao0EIjmBar+A-S=jhQj?Ws2r! z`tM#UMSHWo6z#(-MGKgvXd$x{En=3U#mrK)gjtIAWtO6)%u=+B8AZzpC|W^4(Mke} z_9LKZ6#+%72`E}aK+*mL6s;wo=l}wW))7#2AOS_|2`D;Y}RZ?^V+e^`n%u;j{vlQLTEJe34 zOVO>&Qgj=$6y44&MRzbu(VfgFx{H9Ky9p?|hk&Ac2`IXcfTH^eD0+Z^q6Y~mdWe9c zhY2Wpgn*()2`GAufTG6tQ1m?kML!Tw^dkX9KM_#$GXX`v5JE*SWkz3dK;jSDuYJ5MMFV1P z_%$UfTBzSin0hO$|j&Fhk&A70*YD@P!uPiD35@m)&vx_A)u%&0Y&))6eS2KYDYj( zdjg6&5Kz>SfTB(W6m=$`s0$%f^m}Hs>-A1i&z=s>A5!$Fy?N9%D`vh-QI9Nt?2S^? zlkKIb7qb-gW|pFDnWbnuW-02!EJb~prD%I*DcXTqiuy65s6PQk0|+Q8AfRX<0Y!xb z6b&MvXfOdqLkK7uNl#Z(ar=E z6%kN0ju0y9mKB}tfW!~%=HPVC3itFsu|H;1oE0-)rf7VYf9TCpG=c4y2plAvKMNqDBIW<`7Ucmk=r{&5B;; zfW+6^r?F*H^o>0*&C80JFH^K2%YXbjplB5VMXL!YT0=n5{sa`QC7|d40*clVP;?*xMe7MDI*5Rxg9#|w zKtRzU1QZ=gK+$0Y6m2A+=x_pxjv%1uNCJwEBA{p!Ayl+?R`eSOB)-Ld!+IYndd_{% zKRPRBzD&_^S$^IfQgl4qOVJ6;QgkA-6rIE@MJF>$(J9PQbSkqHoyIIhr!z~@8O$g; zlYpYL2q-$6fTAq~6rDpr(YXW^oku{?`2-YQKtR!j1QcCFK+(kn6kS3<(WL|wT}D9B zB)=s5z4 zo+qH_1ptHFI_!;7bfP^ly_^*@U#95wEdQ)~r05N{m!dbB zrRXhYDSDe(ir!(CqIa34=sjjBdY@T}K46xj51CQ)5dlRX6HxRC0Y#q@Q1lrAMV}K; z^aTM$UlLIC6#+$G6HxRG0Y%>uQ1l%EMc)%p^aBA!KN3*%69Gj(6HxRE0Y$$OQ1lxC zMZXh5MXzQ>?{h%n$J^W0uSwB%UET0UR?K{vA}`y2|2`>-WNS}eidryBQIuJVS~5$K z&n!i0%u*C%mZEfKDav4$qD*EKWf4%6O+Zl&0Y$k46tyCtC{9389sxzI2`FkqKv7!) zit-64N)S-gj)0=}1Qc~3pr|7OMV$yJ>P$dU7Xpg95>T`a0Y%*ip`yRCqUrZLMV;;a zqQ9l+CsWitJ7&I2QSWTO?}JjbE!#`ccFa=LhgpjHGE33+%u=)ivlR7XmZJX5QZ#^B ziVB!fG?0LzLIR2g5l}RkfTAG;6b&VyXcz%S!wD!FK|s++0*XcvP_!cfMWYEQ8bd(Q zP6QNlpVQ858UB?J_e5<*2iv!j&`NPM*YNKvosa8G|9`)IZ-J7&I2 z(JtBk;)kVZBHK$*1+x@QVwR#xW+|#-mZEBADVoeIMK#P)RLd+yb<8NLC!lBw0Yy^@ zD4Iq<(R2ceW)M)cD*;8j5m2-{0Y!TdP}D#`(Vhep%_N{`F9M2Y5l}RnfTBhMisled zG?##)c?1;AC!lC=La1m$cJxFCB)-7jA}W`n59|+!?2{ccU#4hrwtwTJQnZBarD$Jf zDO$=bMa!6_XgRYKtzed-mCRDKAF~v#VwR%S%qUtzK+*mL6s;wo=l}wW))7#2AOS_| z2`D;n};rs&pezvw9`x{d9n=yql)x`SDY?qrstyO^cuZe}UEhgpj5 zWtO7*n5F1`W)wX@K+%H)6g@;h(Zd83JwiayqXZN^MnKWy1Qb0%K+%%~6g@>i(bEJJ zJwrgzvjh}9M?lf@1QfkMK+%f?6um@1(aQuBy+T0ItAtR|&Dqg84oE!T{!GX%QnVq{ z4X&GXjb}C!pvH0*byQpy(?CioPbG=ocDN19Oq8PIjr87%W2D21pGD}ewvlL}BOHmFpigF1kYDGX% zoPeS{0*YD_P}GKiqP7GSWqUmq zZO<%4J1|R8KV~WF&n!g)n5C$IS&9ZSOHm=S6b)iV(O?3Kh7eFRlz^gP1QZP?plAdE zMI#9)8bv_Sjsz5qCZK2x0Yy6zP&Af+qMZpSDk7k0905he1QeAJP*h4lQ5gY6;|VC5 zKnN9Wn-d-3fW$Aco%`*i=v`A(o)a@)rf5=*KmBDXs$_d9s$!O+YGx^#%q&GU%u-a# zEJbz9QdG|@MN^oiXeu*`rV&syoq(bl1QhK`K+$dl6zxtx(H;a8H4sp=Cjmt>2`Ji& zfTCFh6wM}}sF8r8IRq5VC7@^?0Y&o(DB7EVqJ0P`T0lV2LPDr$Vor3O0}?;ke(t(L ziZbm*(xRN0`7%XIbNnr@O3^a5m!jp&QnZ3uidHg9(SFQQw2E1ZRx?Y{8fGclpIM65 zGNb4K0*clVP;?*xMe7MDI*5Rxg9#|wKtRzU1QZ=gK+$0Y6m2A+=x_pxjv%1uNCJwE zBA{p!0Yyg>P;?9dMaL3Qw3&dS;|M4^o)9Wpk`sNv0g11(ho60=$jf!Z2{|$IWr|M8 z@jrZBicV#FDLRc=icV*iqBEGK=uBoQI*VC~&SsXPEzDAM4zm=U%Z#G)2q-$AfT9Zs zD7uhqN@lfx|)EZYX~U1mVlz`2q?Oq zfT9}+D7uk=qMHaPx|t9vIw>cb`G!;Uiai#cEJe4NqFZue=F1e_k>l_1mK5E|_EK~g zvlQLUEJgP)OVPc|Qgk1)6y47(MGr7b(SyuV^bj+O9wwmZ5dw-HC7|dr0*W3dpy&w# zik>8(=qUnCW0s=NnNjow0YzUDQ1lf6MPCz8^bG+;-x5&t9RWq(6HxR6 z0YyI&Q1lZ4ML!cz^a}w+zYpVQsm#hFo*M?g_)0*cxYP}G)yqI?315(E^rBcP}~0Yx1MDC$T+Q6~b5IulUT zg@B^21QcyUKv6dWin|%~+9B8f^8+dB$M#axpIM3qFiTMZvlI(9xVgiav2q-Eg zps0+1qVWV2O(3ACoPeTT2q>CJ2o?3sjrRD^DSE>`I@?}~cCwE{Dsp4y%M?}T`o$kh z(PXxlq8er?s%4gd?u*#s0d5>PaUfTFns6wM=`Xg&c&dlOK!4*^9B2q;=eK+z%s ziWU=4w1f~Us?3efb3o$n*^f6?Nl}h{0V6rD&w(Mg0*(X!m= zRSrnJy*-I7m!do)b#iXZe3_!tbN#13m!dP+UW(3SmZGzmrRZ#CDcZs;MdvU}(Yef0 zbRM%5ozE;q7cisfLIR2|BB1DE0*Wpnpy*NpiY_Cd=yC#zt{|Z3N&icZaq{@{SbU$vjRK23^B zTDal%+?e??MR(`=`Cm!VJ!~&U_cBY-eaupHKeH4)z$`@%GE31z%u@6)vlKnTEJcqp zqv$aLiXJDR=m`Rfo+O~?DFTX~CZOmU0*am`py)XQik>H+=mi3bUL>ICB?5|GCZOmQ z0*YQGpy)LMie4w6=nVpj-Xx&tEdq+(CWMOa%#Dt6K;p02&t2aoMKhvqcqcbzzD&^v zx&E%-NYRIEFGU|QOVP*7QuGP46n)ApMV~QC(dW!k^aZmNeaS3EUooTTYXXYCA)x46 z0*byPpy+!7ihdxV=tlyIej=dgX99|TA)x420*Zbkpy+o3ivA#==uZNQ{vx30Zvu+E zR@!YxQG|e^76cSU2`Fkw2o=4T8(r^!#80xHyMAAarrD3I`K@B+%M@j_^3VNFiZa<= zin5rcD4SV|a+swkmsyHhF-uXLS&H(QrKmNt6t!VSQCk9v@(CzP5Kz>PfTH#U6m=k= zs3QSIod_uEOh8c=0*bm4P_zvJMcoJ}>P|pW4+4sM5>V8OfTG?66m3gD(RKtB^&z0B zFCkPEYZZOS0g11+HyYDhg?swP*-y-F-zsLlOwoW={>MK^Q32aa(LiP?DrAU+t9SJBJO+e8Y0*ZDbplB=sMLQEvR7610 zI0A}_2`DNdps199qA~)C#uHF9fq5G=*7;rZP*>G-fH9&MZYUn5Ae}W+~c@ zS&DXNM$sMw6g3b~v?l>YGYKf#i-4k81Qg9Cps106qB#T<%_X2{9sx!32`Ji|fTDc} zC|W>3(Lw@>77A)x3` z0*VeJplBljMTZkmbOZrKM-otU6aht>2q-$5fTCjvC_0vaqRj*p9Y;XX@dOl|KtR!n z1QeY_K+(wr6rDmq(W!(`(aKiQQyq}_;r1l9pA;3_@1vd8DrUY+(OIqhTYs0Lv)NvX zwlGW4Im}XYF0&M!$1FwXGfUA0%u;kAvlLy#EJYVHqv#R>iY_If=rRI|E+?Sq3Id9* zB%tUj0*bCCpy(O`imoM~=sE(5t|y@A1_Fw1B%tUf0*Y=Xpy(C?if$#K=r#h1ZYQAV z4g!kqB!r62Xcc|S0f`TCqkpCpU1Kkj?rIe?U#953R{r0AO40pnFGUY9OVNYOQuGkB z6g|u=MUOB`(WA^#^cb@gJ5&=y?K)ULc_8 zMFNUmBB1DH0*YQCpy*Wsie4k2=yd{$-XNgpO#+JEBB1DP0*c-tpy*u!iryoHitcF@ z?e&*a^tFACcCQq*wHHb6w~CoBQ}l5wztpoMa6fnb3ENB2r_56H8M739&MZY=FiX*w z%u@6fvlM;JEJfciOVPK?DEf|oqVEYP`hkF=9|iGZS?2`Ku7fTCXsDEf_nqTdN9 z`h$R?KM5%Mi-4lP2`F;^HK{Y)jnp!Nq6h&+EeI%z5>V8VfFhrOqBH`EVuVo9hpnP} zJ0S6^?7tiPkraJxPjBh*nE5hA*>V4<7E+YM_EMC~EJdxDr6|rUMS09p)S6j}+AvE| zTV^TBXO^M_Gm6>~P}H7)q7DQUbtIsu69Gk?2`K79Kv7o$inbx3s2c%A-3ch_K|oPY z0*ZPOP}G}%qHPH%+KzytJ_Ho?C7@_~0*ZDZpr{`qRFoNyUgLnoN7+lEta!Mmf31Bq z+dm#NU#6%q?myd7iUzU06b)vUq9M#uG?ZD2hA~UgaAqkQ!7N21nWbnHvlQ*fjH1y5 z6pbOEXeR=S#u8ApGXX_K1Qd-Ups1LDq7nj%N(m?`BcNzJ0YwuCC@LqQXcq#CCK6Co zK|s+Y0*WdLD5@f$sG5MH$%If*K|K1C0}@|ipQ8c zil#A3(R5}hn!zkZyE04BZp>1&JF^t+!7N1$%u=)`Gm2&sP_!2TMY9MfnoU4aBLPKo z2q>CMK+!w`islngv^N1o`w&pHfPkWf1QabIplC4xMN0@M+LwT$r34f$BcNzG0Yxha zC|XGf71hO~qaBd=8vBXadMWB?yZ!scW9G{g?H~7d&yb?EY%fIzFiX)oW+^(5S&G&( zOVL5hQgkr06m4LZqC=Ra=ul=99Y#RWMgocsC!pvE0*a0#py((9iZ&5YbTk1)#}H6- zECEHE2`D;_fTH6GC^~_Fq7w-yI*EXylL;s~g@B?{2`D;^fTGh0C^~}>Dq0_cO5m0nB0Y%pkP;@N;Mb{BfbUgt@HxN*CBLPJ>5m0n9 z0Y$eEP;@H+MYj=9bUOh>cMwo?Cjmuw5m0nD0Y&!^LPclCqmMWs@hbZme~T1tv|k9h zHy$%zrs%=A|7ngCJ;e4>^f0p&J;E$Sk1|WqW6V5&=y?K)ULc_8MFNUmBB1DH0*YQCpy*Wsie4k2=yd{$-XNgpO#+JEBB1DP z0*c-tpy*u!iryoj=zRi;J|LjzLqe$N{&+Mu*D1Q+-XeNHijJ~RV?T<=%$F(pEbbS? zrRa0Em!dD2rRYm$Df)_8ioRx+qHma`=v!tf`i@zOzGs%AADB_}BLPJ}5m59q0Y$$M zQ1mMSMZXbH^g97Xe-KdgCjmu&5m59u0YzS(cH2=DA)u%Q0Yy;)idqs-{zS&BL^qo^YRMV$yJ>P$dU7Xpg95>T`a0Y%*iDC$l? zQ4a!&dJ<67i-4lu1QcycK+$#t6!jsXs4oFU+Y?Z<0|7<-2q@}LK+ymKiV6s!qMW?w z=?+NzV&B2Z%?tPRN7}oN1M_0$%M=aC^KWk}MMK$MiiR;u(Qsxd8o?|@BblXW6tfiV z$Sg&pnWbn9vlQ*bjH0mw6zxnvQ4s+};|M4!CZMQ66jcyVG>L$sN&y1plC7yMKuHz)e=xtM+g-S%8S0^fW!-J=YFsh{ceit z^J3=96iv_bBkiPU2HQ)~uFO)j8?zMc&MZZHFiTMbvlQ*gEJZV!rD!i^DVoKMqS*u# zH4;!Xhk&BF1Qg99plCh;MSBxav=0GA3kWD$NI=md0*V$BP_%@AqJ0S{T1r6CG6IU0 z6Hv5*fTEQI6zxYq(JBIpRue)+Q}d$RIw0|z?bY=(DLSva8`k8-%$F%zm*Rv$0Y#e#C_0*e zqGJdsI+lQ<%>)!3M?lf>1QeY>K+%Z=6rDss(a8i9okBp-sRR_AMnKW&1QeY?K+%~5 z6rDvt(b6bR{#2t|Fl5Y66O`A)x450*bC9py+x6if$mF=tcsH zZX%%QW&(3tMSvknE5hAU*`E8x=GPjY%fJ$GfUAo%u@6%vlM;DEJfclOVJO^QuHIU6#c|3 zML#p6=obQtekGvjHv)=&C!pvL0*d}5py)3GivA{`$ZM_Lb`(VjC~84KQIvq9mIM^} z1QewaP!uDeD4l?!3<8QW2`I`UpeUPwq8vh~=<~ejP7X-?%RC3?3n|)QABW_&j+rl0 z)Vj6b&_jyau)P$uWtO6RW+_TAOHn&!DQeFwMID%>s3Wr!bz+vH&dez4LO@Yh0*baF zpr{)GMcoM~>OnwJPXda15m3~dfTC>)DB6yIqCNx^^(CNadjg7fAfTup0Y&`@C>lUO zQ2_x(0|_W9B%o*zAygD^9X-SWiC5XXj(M%aJ^iyC9)ED_nE5hA!(00o_L8CzY%fJ4 znWbnHvlQ*fEJdT4rDzPZ6z#+;MPr$zXlG_ADq=>_I0A}_2`DNdps199qA~)C#uHF9 zfqqO9&OsXdR7j=M-INKbW?w z6g^_U)p$VbnE5hA2etMK`%2NlY%fI{n5F0tW+^(9S&9y0mZFW!Qgk@86dl1VMMpAA z(NWAO+C)In(F7D7LqO571Qcy1py)UPijF6s=mY|aP9&h{Bm#;~CZOmP0*X#0py)IL zicTk>=nMji&Lp7dECPzoCZK2w0Y&E!P;@RKRCHkL=oAMeet{eP^-}b`{Yk9zTF1gO=fCV8&f4a8a(@%D zef~^`vUC2$?guEl<$vj3W%bG*?0)&SPyXuep4Tt`ZufD^z|v-3|V_Plxdua=UtLNa&OPOBLBbzo_9_DgNr=xhWxC3J@1zM$;&+Nj{H+rc-}qvZ|>)L59Ie; z<9Uzd&tL0#Pvl>{&hwth|8c$Ny^z1-2G4sX|DZ!X?~VM2H+tSX`8h{=-Us=$n>_E6 z{L_x{yf5+cpx*dIsVGm@~sZaq7aus=^cFOsmoFS{U; zus;yGB$BYd@VGpZus_kaDw43jv9>mnus@QuK9aD%a&$-}VSlFP@JPb`&d8=n!v0Xi z=19VR)BnUs!hTiz)JVd9*Y?av!hTuuoJhic+wFo#!hT)pl1RdS-{gu&!hT`knn=Qa z;`@e3!hU4;mPo>W=JJk6!hUG(o=C!e>gj<qc6B%A;H)+=ccZ$0@3;@IBWJEJh?HdTZCZ`BL}44$r$??8wmEW8Lxm>gG?~|2meqa}XI8G_T`C8-{DR*xl13 zBXXT*cd*OdC5w#IcRqK&LlzmOp{%1DcGNJ*hS3am7RG3JrH31K($Lbq7>bP5aHd`I zox`Ei7w*LDI_fYW;$&B+vV`a4|YoH z!)^TRBgVFE9c=RY(GMKEI@sizpRZXQY*KT6U5?l3Jh#cwZj&3>`vL8Oy&y*MZHdMM8lK$l(Tl~N5?(nE{3~6&-}FhPdjUAd7oVI;g|ad z8~t+f2W`Agqnwq~-3fKJ|3#|(?7l6(t9RS@*(;xaIwRQR<}Z%i;LfBwor``td5qU- zg4@K-TQ!?py4%>DgOmB~)K9Mp&)bbRUH(V7&2FuZ80vM|TiXOz^bsE%e#e2qX)Idz zo;xvjjotsn70ZH?`1-Y9=6GJ$XgANZ|E0Bvrggo{S+W16wRA(CtMg+J&pRHqR zvumo;5eG-yO;Om!j-~UF2S>aX?T;Jh?rdH7hPz1zcw;+^?yxAAYtZ|*f5TjKvTWJO z-P0o8R9l8P*)6^ABh_2%tK;4O+&665!?6m#VPCCx|8w84<(=d={_Rx4wta9~lWnPV zcejXFZwse2IXJD+!BN)R!f8$3(sWw&si!r0OUh|Q+}Td~=N_!w3DnrKcW}9;*urVm zq@322)YGa-Ijt$Fr&W`BTEXcI2~MHb7A}14KMrJvyvbe27T$5eYGg?pSEvltF~`xtF~{Mvb{UT@Lvlr(jvHu!~YMW-LNgZfm_nuH|&3Wo$0>zy`7hP zowwMRiC`RSqn*kDHZDu~o*mvDdStY8V5BjTfSoU{KW;!7cX8gYu?QHiq*%7cO4ZFmuU# z*Bsv3;?f3pt;{M8x@+!1AD{E>w8G^15%*_hO?q^2#P{3$r+=7txP$0(Tr~Hs@X54 zq!pxfaLEpyya?U5I#-;#t=H~XCJ)Hj?&{8ddN)5KEt)ghPq-n&T_J8A*wuYi;J(V= z!O!UBCpv4i0~DmS^%KGO)7tonZCvR-M%xzn?SkVd@O!v5J2>JoqZMa_S4*q#7VWKD zG#CfCBN=3;=J(mbZ)cl@$CT*qx3d!{@O!!MCAtJ(hG(-!vt#R(dTh469b3fjH84D< z|MkGZw%z>X8F3dkEi$NIcfVIpKM`GH$JSk!kJYZ3;HuF2UyomBW?(@<7r$5Ut&ei+ zqv9m~H%D18uzzqSJEfe(t&i`2bv%B@qJC~eJD#TPJ4E~(ceO^_`Wd#Q#r=-9_6Vyx zU@*GtAvjdZY&UH*ZF|3it?p_H#z@+>frCVW-@Aw3F7>9={pG*GXgARBZRk^MWVm}} zs4ZN3x#JISEiQtobdNHrm+60D=U+Ma8BS6^yPC~>e>={mQ`yRVj@_B&`kmZ0)2D~u zsjHvEBSIT@O}GcMKDM~;24gorGIX>%Nc8n}EyhNIt#aIbu%r8a-+_L|e{S73b?X6c z%R%nI?F#%p(KQ47PTgE6(6Nm9$7;u#!r* z`W-vDqv^iY(Ik(~jwt_sI3B;Ni3^U0?F#%Z5kJpu?8Jqn;(k{fdxX_pu3&WMH8@nt zY}bj2>tZV)ow&Jn7E{l2(`jvW6}S!m=kwgh-5_03F1hYo|9-RDHD-^3UEFQd%kR=T z*pA??ysf^>aTk9ZJ52OtZ`%I@J#7d1Zoe~lqiiqblF$ok519j>f+Lc?B72P~>7X{fBKa|f<1t*I+5 zNq%RSYImgdm9_QN)m8S5hU)TZr4cUfWN7ek`<0`6(CpMH6)fF{V)=wH& zT4R@^swO=2;1Q`OTv^pnTR*P0xTf3=R#sJCSrQy<_=pL?ItSPOnu5#xvJfXj!OIAL~uFc>uc1?~On0iLbD;w%L z;gLFXg=NhSQd~2=x~|GyZ8-_K{|YqTiwgM!Gju>2bZ9v+2-Ra+-tj< zvfySYtt@h5iC0xt+fY;z9?j6;(00zsQZ9ID-2|@RhUy8^8{BO@$=%AuMRny>mErX? zGPz-4amtqEHIp00Ib$W|wc&|zU4}<#M;6>{4He~;6O-54)bg_OhN9}=TozYVR+bi< zmOx(F5WB*HFH1zCw!XO7DNSw-*~#^#^`#AE?wU$|tGcMByl#4OG}M!dDyQqFYdVVH zW~;5L4bDM{Q=L2mLxa=jQs{7Hh3@{*P+L`2*3j(0g(I6Cy11yap{}N=vUXB=U2x1b zr9~yvg9|gR8Q7ZIB6mc=P3^8=!R9opYKt3c>#E#!TIx9JHVm(uW=E28e@b3p=_#rR zPPw6~y0kL+Jt&W>DIY(fuF_qj4Yj3pb#`Coq|1scCI)AB@R0DHGc-8G;KT=#f;&@? z9AVv7BlOKecl9NYt-QRZtf-;1xVWKkT)FP%#m(-D!9z<)dC~ZWs`|R>`nrZGRTXva z{*yck?hW>!Vh=y|(3NuUEGeB*?sjIz)z^mCvb%4jJ|2a4CBy8lWV>_Q^^vl9%`|tH zZm614T2oe0HFfI~t*IQJeAslZiY6rwP+sjG%ybi1yN8q1$J5{<)jA2u2gyOnD{NfK zm18$h(@BTkQ@-tP2zQknI4UXfB(%=SP zHh=D-#@XH6yHZP&Cug{;%G}X8Bu$UkO^*k~#Z?Ux+~ZVo1FoA%RVCrMcP{~w-z+Yz zsHm?fs&V4Sm)APn_PoUfK@|@G;dvbBHV-ahvq$jy+Ht{icSG$2_d+E+q*Y!o3wC5Gv0DB!5ve|%c~MDgS#cS0#I%b zd|N%_q`rJ`_xs@f8eA92yFua5W=F(*g$tANOdcpHUlcs}*#Fg4G%iYBUH|&L)`X^_ zq$+qwO+Jn21`clz_Xwlgv9M52SMKRMdEDI52R4*Uu4^cn5I%!9f4U!*a(F#RO>z%I z^)|9_*~9-U2}1>J~sl z%FEyicSmUQz_}P-G-*;%@?6;U<6dQPwYa-$a8)(kr3(uKE#oWeyA_Wd+0EW69#GiL z-YgzCV$hIoeU>&ZXq>sMv2VBj3ui4^F=p1{rOO*v^_kpEqWpOW_@?zsYgaoE3{^EuX)5 zQU7J`U0=5@b8WVRl$?W$IJ}w1;IR@J-5pTKeW8aqX0QL4)1)0KPK zRy3}>qI^cv>*j&(G1!h`aI;6!rn|k}ostBbB)g{?_kd96UUJ&=ck%$-iow27(~axy zbH(n}z_=o}!=y)4J5BdmKRo-xo8-G^`LH$LF|pkSdy!D?_6x$76XE3!@XfDSym(2W z7c7JRabB7|J2!g;Jjor?xTT zfaK9MT}$@LtwC2+xP^O)48CwTZy4MoS<2lfxSgB!(6)Nvt;fRV&l5x3F*P>W+vtr; zmxjmbcG&*q%!H59?w)MtDttLw=yp7VO`7kn+LKJv>n^vGs{5bqbO%?v`$Ea~ii6}{ zHwRyYJBvXYm^@VY)&I>8ocO#d{Gfq{>6Dk2!3$!y-=tS|?qMQ4pYG~PxxQ02uveXaS3VtcD0^{L3Nk<|Ut2~*v>8O0Ob<8XLg zHM{$9H?o&I$y<_`y3_q%cJIo{%c`31dp5Z&DJl*=WT|r>$|R3J`5NV)_cOOE?yj_b z>~5AkczCJnD~qPMdy(y0C%=<&r54q@9e4MNE_FxUUWIYhg(k7q zR#n==Oz_lS_+P)PyQJF-6wRiczvlaNraO5T;*8W*mp5qN+-?u{C5w{B=AKVDVtWOp z({L}2^;MzUcSxSUlxv{6rfNdD+q-l(MWuVzbnjMhk^vDrBgUlMy}F&@Ff=r{j|-dL zJ1KN8&)o?GdnC!-5{|$g6H|%Nfl^jf;@;@l>iIlCV5d6XSx>$YYTCCd(Nk=p+Y{lU zxoaVLu6cc(iaror99&hL2Rm z^@Vuw7|U+Cos)1UE;vu_<&e7!oF}(W>h|@@i_3#2uIeK9ycHbEJ^O@Txcg_bgNN@( z7Ef^d%B2;-LENr#^5~NHm$Io1_3kY(cV+4bb$sp(F|I-Pz@aZ~2T$j+>6qLb0JZjr z+vL&?@~aIdby>%;BWrCcBO)M-06 z4YgCt>)dxzo`=~1ENpr!q0l|%d&}mz*IUV5Y1`ckPQX322VdCkorQ2OEcjN+9m>5T zZ@Px;E#BaL7<(<_-g{^mUsN8x@#own55|?__B84%nqIaTcV79VzVJ=H{WFNSe{9E) zD~cntS1#V(!DFADMcXgqAgTKm?rqibV)q#09@FcB>nVAtTDSM>-Yw8O0$gt?KQZxt z>*oYY8uwZ;H@HS^ACEI>cg3P{p{?+(XTHNFEOWbVZZEf?tfHv4X*<4KUv0AO?E~Ib z-)g5TdD|416*t{3h4$t)r=&MU!sp1~h7RAEw=YxQ;12c*1uNy%Y|~BI^un~H^gp~b zwOf07X}E99eq!?n0+Y-h4X*)%Gi7gG2VaD5$WJPo)=*qor)QSb_oIXJ`OoLca1V|P zoqXReILf9swhP_cY^nFFrniIal85(*W{*V4oqjvU``3IXGD!&YPad z!Z(oZo3^(Y9LU~HskJ-s9Eag$m_AWUf zClRVoK8ps|R_eQ?0fc{h5)L1dlkcQ)yuqh8JOmK!X053YAI|K-m#&9ucbhhUBQ|As z$-RdY+=T9F`=6w^5bm+hJvC_;L7&R7pEbPMhHT+pojTnm?sZAZ3l_ea{OpJ)&Tt*4y!h`ygB|aN`6`3mk=?un_csK#FMIs5MA#ecegrMy3@b6gm{xoSrn?tO82-Fy9dg%Z4a z;O+k4^iv*z1vPw0lYEcT-Aj30B1n9SR~Wvv8XS$ilNo#wz8vP1?SZ!W6H4;#m3of| z&xt#V;NF?MK8h=fCRL|A8;3mX^Ef-+rVpl?UeFf~Nj`|dzR=#Q49{A#M~b3q_quzU z+mUVtIOXhx*F$*6;PT+xaJr9xw|>Vmche_o%(qa7d*T=f~(VA)xq`J{8fF^QMivhc@f5$WxuMnzSez; zrTyA}yn$)&U2gSBMR;w7Z>$W|bsJ7idwlK_bA1SAXU}#>lKV-VzCEi4Pgno8Pim$N zCHq-+EM>Zkh3>ttVW6*RL zP2IT(^=x&z#gj^!y+LGqp5ZN_Yc72B;7kM$3$_30vrb)^oYUm%rf@$cI9hu{k|PVA zohpl(ermyP&aKX$d)i5UvS?Q^&pS=W5#C@^t7<0dMQQSNL!o=U>8=M3>K=;tK&1JO zQEslwJMI+sT zX4;RXdlC10nVvtQ|D*wKAEMGr%Zp9Qh-Rj@ZrL`HA88kDAL$V380i%09O>GkN5uU$ z(?9;Drk38ff2STGYCk-k@-M2N`X@#0XQxyCMcvO$yI&Sc`Pb5Ozk=r768^G)`zrjt z{q{llFZ}-cJZGu>|`mDuX~9IbYZw{TaZ*=*r1kllW^x=n($gRSmH?ry8QI{T=bLpz-PzLBkC zw2sqSt+ih3EUkNM-B;^@S`X2>S?jr4uh)93*1NU3Uw{ox_i?SyYJFMjn_A!3>VAPW zIQ-XIf7I%JK{e?18!C1=>@TR>>V5$=Slei|zm#Qt8?C*y?x3|$>u{}Ov=(bE*IK2u zUhA$}XKJ0Rb)nW}T32g5Q0t*ukJ5Ua)>E{erS*KR_PeEa{;$@0qt@HC-mCRttxsuv zQR^F8-`Dz?)^D}`qSZaP1*end`~}ye*0x$ZY3-r4uhxNDhilzQYpK=>t+iTbXq~Bb zp4P=$S86>#tNkXaou8w$9qlC@)cS+g z-?g@I_e(oJ8Cv67+iC5pwYS!OS_f+#rL{=w1g%wCr)b?>>ujz2XkDsxwbu1oH)=gb z>q%PA)OxE}^(Rz{AE4ALB z^>(fIX?;}dGg@EP`j*xYwSJ-Xd#%4|jksS^vdfjOwUyR{)-GCmY3;9dnAWjcCup6l zb%xeiS{G>_sjaoNrJx%L*S})gngVsB>KBV<&t*>Z(SLaXt$no)(z>J860MW8PSM(+b)MFJwXV^+LF*>1Cuu!f>&05H(R!=a`?Nl;^#!eO zYW+y-*IIwk>i(;1!R5=;+E!~%t;5|*AiMmo)fu;ZJh^-T9m#x`H7^}T-K{I%9T?uCebf2h_) zh2gxv)*IXlHv9g)T7MfF&N27G#rn=8!gZ3?!$yVk30j{R9nP<6Z9O)ex6wMSD4ZL$ zo?RTymuvl?G@QTHy8VQ39x>!UJXh;EyM^md0>?Q0rfF z!#QhSxR&f4u9LMMxgeZR(fZ7yaDG#3V&8D?sdcwy;XGgKc`L&CYOSB_7tTLw9k3>x zchtIkZ8#sK^|p24{IFK3z3vL<#ab`9C!BB8`qh2m{JYj64~BD* z)-?}@^G2=rJQ~hVYE640oZD!vcq*KyYd!v%aNeTz75Ddb?EHSHwd;%Fyo1)+FNgEK zS}%JwoNw0pjr$usw*8-4hrJcf#ah?C6V69yz3;tnep+k#hvA&BwesU|-c{>~pN8|f zT3`D-oIlpu?W=I^uXWBh;k-=i74EP5*!jCv>vund^WR!W{2b1uTG#y=&PQo|!0lk! z_Rng~{41Q>X{~neIoS7i*Lt%1<3Ki_ul0?V;ryxA9&QKCzF(kqUPd^t(0Y~o148!w z+qM4ScI0f1rfR3tc*fpHV&d%QHFqF^<9g*Iv^xi?L^xmZR-Vs!a z6ln@lR78ph0s=}EQ9-0C(gdW53P=@%^S+tq{+9oD&ROTUmhO3OW=|%Q3zA7f4DBL1 z_R1dG!*tx3GqiW<_`v+IB744*Cv+_TLg-jq#}(#hfZ1Q)pyTKE=!S(I(mr92vF3Td zj_1^`Yv0oGj`~yWumYj;TzfRPpF%sej_K8NYUkClfO=`|@;X*luczHe$7brCbnK_& zXdS2PxIo91I&Rc)myX})cv{CR_Gli54Ca$w_Sitj2|8}k@urTM&5z)**K4ff1bZ~E z_Y@sx>iCw9OLSbOV|+J|*KspC&NKGyLc9qrG6u=h7g z$CNsz(J@KKoH`cLv6znKbgZaj9Ubit(y_POO2@W3M%u?a+Wfxcao5p24NSiNC0);c zzA`+e`H4haui&5&uMY0mDXie2!2?6b9$Yftl|DGEp#3)Ru!5Zi4GJr0zHz;vjRpT7 zUu#UhVi)_3Kjup)-TIl^NWR>$Q>TGlhlXw@RLoCh`SbG1fs4cb>w2R~2EtzDLHpOQ*|*5QU+&XUfw2DOdiLeo&dZ(p zuXD`BuZl&8DCZ?@X^=^2lgc|!EO-|ZeXWt{g@xDj< zla4=%s2rC6$(bHGH`clEsL#HXukL#kma=j3f9E9s_n7@}wteP$tLyE1baD5IM-fHB zUVL(<;q5?d!`tIy8s1Bnq2aypQ4Md0`A&~zb@o3BE3&NavfBF}-74(d@v1uagO0hp z+j)?`>i$O;H!iNV|52vp&mTT}ZjQ6}KRP<$a?e-7!|vpoIIr&fS6ESj^zJ7N&auS zp0+fo!)r0BXWiP#*GcYAlK)$-mn|L5Yjv@3t-CpLr0NjUV{zc=iH7%fw=plTxOqEN zs&#kEpbB;NJj%3tk9k||d2}>v&%a-8uco0}?NvPa5qgq*i&gHX%2B$vx$VH-NBdKx z>X4(yzP~DUUlRB``Ic+etyQO1?b`P3mHb$kx3Y7&qj`-6T<+Q4ycNn#s9LvboocnK z)v}LNl?SPus&z6oG>=nK74y39Ps-7uT#tpJd-?K9bt~4XSi4fKryaTOOLY#K>!het zu0yIGi*&7q_geQaQ#YpeiH_#&XYSL*!awM3TdYT)DWbDb&Ys04vtvRq^zjDu7EH1G5>UR|yKH66N^=Z$?G#GYe zZG+6Srpz?I=_+lVcH8{%;g7E#J3FlS)S?AfrY~2o(F;#@bj$SRA6s|dxi_re)G|+U zegF9UTNTW+MSp_p`(djOZaI|rTba%K@4Y#9LDPF{T|X*pd|1SI^QXi3MYWGk;dT79 zN2~wwI{wwe{vNY$`O0~kB$>ByhCrj zI_YYs(>0ubT_bh<71ykni{`Pn2J*CAT;uYzhAsTHO`LjH)~|ndt9j-!QK@eh*j1|Zq-;ThAn%5szrWEl;pa^&a}*ku_luF{=N*QXE)vlD ztcXAx^ISG|g!yFhA^TqRU;l&$BIlcTuHgayE%W{*JltKE#vZ(F*~~kULfOsb`swPM z>xW0UQ_TlC&IR*KExcj+4#~;Ol))_Dy>FxMO*YToA|hP-cNfAVyzJ(NoKxoAfRjH} zWpj0BK$7`S;nXji%kC`mpU9r(y}1`L+FXpN8*hJhu(#X3AM`ev_o4ysu6dsqZlXEK z>tx;!MtH}}9d*6q=6ztKm)hK0&zov)-uK=!J<8i{t{?50KZ?U*yd~!2_E@h)lKBF( zcg1{&5${#YVm^5Au9@eRDZF#$nkl_6GMT5HUMKT!kM1nvYh}cx%ly(|SY9 zN4JSy&K%~$6mNrhEz^6Q%p;e{;&B=2qW60>=0 z%uC7c{bg<~hqvBbGpEoaSe0d(X_R9rCW3`}~cU#(dcM ztvA8E_x{c+W?tXJ-X3$!BmQCYXygz03(egs5b)=iYZVOm4b3B7DB$lm_pGq_HFKC9 z@Z-!QJ}2PkH+N-jz#nEFyLkbBt$DcS2mAwOEifmThwbfvztP;v!hrwKyz+|zem(PR zivxa2bC;F`{9EP)-3$0B%qw?4;O90UeLM*GBTRf4@N1eA9tHf%=8m-t_tTgcv@_iQ z%G~Aaj^D!Ei5rf;(0mAa(;Uog{^s~;jk{ZpzuP=6zdL>>^I-hp_#c`_<4?!WXkM|~ zj_;V4aL4hVo0m{8!f$3CqxunkDRZwIMEGOPTfbq1pWobAqX<8vxs}Ed{sr^$nnd{j zm_ySDzmj=*FGu(Z=7eSuehp)^d4zx3ylq=V`1uU5mJxnqj=NNdAqz4 z;kPtzwl)!dQDbLggg@BaiPWxN)x1V&T>mR`Cx*Lzee)=daQ#B&%{kKbKQ-~J>wji$ z^PKCKHV@=^*S}(*U2y%f=FM@@_5U`H*)OiY&^$_)T)&ICFGoH9zPaWPo`2Pxe$4aD z$K+whJ^z7ulb`VXbLK9c^!(xGkvQe~-7keno=+x4BCz6a01Nm0p$LXEC?AI>Dc9 z9+3AF`~haYmdbxI3m%1ZcZPW=>KWn#G?}Z zq2_*$PV{$}*I`Ve|A+B8Hqk$4P9K-(k2VkF_(Xq(dBr9q`pe9nsI=7YVqR?JrT!^% zV^x;=d(FdIZK;1dDJ-n|Qa`~wAT^fy<};FEHJAFG%p=igpC4ylLgRh@NOP4AH~oR; zC3L*$_cV96(@nptG12*^U);P7U2ghg%w6hw({E;8hi*6h)aG7yzZo^u{96B%fv~7? zM(+T7A+Q*U-t+B+Tjp^e(b-(cXYSZYdm*K{9rH(KSd{&8Z@^yIYhEw=J|L=$ zdFl2W(xR@KTaK_7&YOqPwHGoP6Xqvaheg%0e-7IVhYcj(URYyZR+PQ4)x061?S=g2 zmSgON0p_e&d*P0G1!Cv^8VYzv|?6smg8EpZ3p}%>+!|jFd%w4tTg+-S)_cfw#z*%l~%q;Vt z!scxnJK9{xYTgG%W;PF7T!iiM5pHg`f-#m*rEr*=NB?)RtY#JobMtCuF|%lx`+{a> zGmC|}`7|?`Sv<^rQ8S~NCBoeNniRuSzqcANWER6DiZ=8hH9PGz^bXT`OHcAL9aLOZ41=DwBGPGPsXbEUKs>^AqV zw06AR=I)izjJqt+doBw z`2nl#&D%faM8nC=mHhw5O4;B1Hg{`!6$~0Hq^{fE5K9(PPp3*qeN72zpeZ2@H6^5x zri3)sl#nKx64F#tLSELCkY<_)X|9cs7TO4Dsg00U+6ZZ_jgVKg5zUHbUOeM#!7m2$`vkkXhOYnXMfX($`sO-u@}am=Dd|ejy?I ztdKdLm1Bj>cUPKszsW)t=u`=LTT?<7YD&l=O$k}7DIrTVC1k0lguJ6EA@6ER$TCfY zEZ0WJd)f$Dp^cE0+6Y;tjgZya2zg%{As=WXYD&m%O$phfDIt3`C1jtbgzVQu$N_DHe5H+$ zgW3rBS{osUv=Q=+HbTDDM#y*C2sx~ckR#d%`Cc0#N3{|1gEm5rX(QygHbPElBjltu zLQZKTk4)s&E{ni6tNQ$nt5O2`dOgxu6d$Zy&RxuuPe-?b6) zhc-g~)JDi{ZG_y>M#x=lg#4wAkbBw)xv!0o2igdEsEv?E+6Z~9jgY^!5%NSEAy2gt z@{cw`o@pcGxpqj%IValSNSVVtDRR#z3kkkxFPqPzSvp~@`JDu6) z!}2(GqS@xd@_2Syv+eVm1cLdCL&;BUQV>$xVD4f{LMj`~eGC$UHkdn^ijdLE-W+X(}VD4!q zf^UPlr?rBznYlFF`NrVU+%stIUaBML5G&>>O1p8bk2O(gCxu-b^ z21uF+H$31pGC+b2>{A>k5K?r>D#{h`EHA6*g@8N2{Lz!FC?Drb(Ti*;%FmXf0&FQN z$d;l)Y$+Kv8J|ipmgBRF;6Eas(8WC!nYT z0YxtnP*jnCqDll5RVJXQ3IRn`2`H*YKv8u9ifRy0RFiPkRS zHv)>f6HwHHfTErR6!jvYs5b#ceF!Lem4KqYgpi_o0mpvEFIdBTw$80DMNQ0yIBvgy zXMI^kg97e9=5vwBiUxDO6b)fZ(NMM&4P#5uaJCeUU`x?RwiJzGOVMby6pdk{XePaYfTGz16wM)^=q&<@<`P1R1_Ye!=ABt^zx}{@pcG}XV_v|szO15!0k^98dPK6K zMVv21i`i1Nge^r&*;4clTZ-OgOVKj66fI{<(R*wuTERxqN&<>j5m2<6fTH&aDEfea zq7MluT0=n5M+6kDC7|eI0*clVP_&+aq74KTZ6u)R69S4h5m59g0Y#e$DB40m(Psn{ zZ6%;+8zH1V-6f#tF9M405m0oWfT9Nk6g?!M=n(-$ zj|nLHn}DJx1Qb0bpy(e0ik=Zr^qhdAu<-vp%MU$A3lLBgP6#Qw7;x?xAi+%blZC%X z(PI1cDJR^szN{iI+)a~PihRzOqA0c$MYE+ShAl<0Y$=LkOHn*qiW1mTl!7fqDcL9r z5>S+ifTGj{6r~}cC@ld+i3Aj-BcLcf0Yw=ID9T7cQ6>V4G80ggg@B^01QaC^P?U{; zqU;0|e-;n}DJ`gpeXP+$n2-1dEw3h`W*Dp=bL0&G#F)dBZ*H%PPtr z?!J;&iVASP6cuDkQ6aVz6=q9O5w;W+WlK>pwiFd-OHm276qRJ7s1yN3r3ol1LqJhk z0*cBJP*k3Pq6!2Qy+lA!MFNT{5l~c_fTAh{6jddls2Tx9)d?u7K|oPW0*Y!8P*j_M zqB;Z=)g_>)9wDSCU$`^g00~|*-+SV|C`Ip^Pe{AOnwJPXda15m3~dfTBJG6unA7QC|Xz`VmmnpMatPgpi_! z;m%hENN|q%Mj^M66b0?Ow}IiF^<@t9(co|=wt!JI%YN2z zh!oYee=xlr?pa?}(UNetKp`nw%K1|C4qJ-eWlPaAwiGRAOVN95DO$mnqLpkZTE&*4 z)oc{KPe9QJ1QdNpK+zfkiasKsXe|Ln9}`ftj)0=|1Qcx`plBljMV}B*w26SCPYEd6 zOhC~V0*XE(plB-rMcW7{+D<^x=L8h(AcPbx3U`_qAi+%LJ2TwHQdH1eTuZ`dgMmVlz~2q-#C zK+zEbioPeH=qLe2KM+uKjDVu!1QeYhpy(t4MW+ZTI!!>)j|3F`L_pCQ0*Zbnpy(_C zMdt`8I!{2+1ppv!$p6TZ&4urKl8Jib}Jks02q@}EKv5?GiaHZe z)P;bet^^cyBcP}|0YyCsDC$W-Q7;0DdJ|C8hk&A22`K7IKv6#eiuw~!G=PAjfdmu{ zBA{q6A*85@<7_lQg4ylIMNOrsoc$E!5XZB=tfCQ)`$Kst8p-)mG>R=nquEk4hAl;7 z*-|u)Ek)zmQZ#`rMHAUlG>MI($pjQlA)sg~0Y%dYD0+>6qUi(_%^;xYbpndsAfV_? z0*Yo5P&A8xqS*u#%^{%ZEdq+>5>PacfTH;X6fGd2=xqXu77|djh!9dV%yAwVAi+%b z1M1;Y)W9lQ?0D9fRrIdoCRUW9Wt=ZX%h^)&9$Si5u%&1vTZ&e(rD!!Ibb)}P ziv$$?LO{_a0*WpZLW=e{&O`$wSjm2q>|QC#XTCelz2bP*msND#aaUHAq8pqqMK{?} z^c!1>Zn354ceWJ$!Iq*w*-~_yEk$?OQgoM%qQ3|zx<^3KeFBOe5K#1xfTBkP6g?)O z=x+jwo)A#inO0*b;3C~^oWiXfoKC7>vhfFh58BA*aa zbk%XbHb8v%ajNxCr+~bt#JHd?`v`OHm586s2TKQIIV~sn}AK znk_|X*iw|1Ek%iJ6s04eC_Mp183-uKNI+300*W#dP?Uv$qO1fIB@s}Rjew%;1Qg{U zpeQE+MY#wl%1uB~9s-K;5>WI40Y&);D0-2AqWlCD6(EEZ#Y8yqHH@O!=5Hpuu@RwX z`ZMg`OD!1TSzlIBQS)TKmJ}7^d?_lYY$+yeKv5k6is}+j zRF8n7`UDg;AfTur0Y!}nC~8bVQ4>N)QQ-*ZWdkHQ!#>k5B1MnPcgng=BRuQNDryno z4yhwWEjeF`TCt_5HCu{aVM|dPwiLBxOHn(v6t!ndQ3tjZb!4Nc69Gk?2`K79Kv7o$ zin31&ca#*}vx?q{@T@PZ=)DLx&`^q2aK03+WJ}R1wiK;qOVRsmDf)mdMIW-IXboG6 zK4MGJS~iM4CZK2?0Y&QxDB3_k(MAG_J|UoJ69Gk^5>T|6fTAq~6n#cO(N+SAwh>UY zoq(dx2`Jh@K+#SDigpoD^aTM$UlLHXn}DJ{gpi_T5l(IcB$$|B;4GJ-eD*tL_eOZu zmsRvtgj=(*6dmMzDf*f%MTgi@^bK2zzGX|%cWfy-%$A}fY$^JlEk#G!DEfhbqGJRU z9VejZ1OY`S2`D;6K+$Oeihd-Z=qCb-&Ja-aGXX_s2`D;8K+$;uiY^dPbdi9fUkE6= zL_pDH0*bB>Q1mMSMOO(SMf)S1J_bneg#A$HfE3k?HRD=@XMI^kzeTujHkG1VoG(Sc zv!&<{wiNxzmZIBiDZ0a!qPuJ<`im_^_t;W&pN*mi1Qb0apy&|+MUM$6`kR2FCj=Bd zC7|dZ0*amyQ1qODBJmzW1QB7mX*0Y%{i6gdPGMG#Qr5>OOLK#@m4kxxKT6ahui z1Qf*(LW*ugIGYTRU}yX3>YGw@%0APNbv^6LDoWwH$D2t}O3s&}AX|!3v85Df}0fsLY!1QcZ=peQo|MOg?a%1S^{5&=co2q?-Ql#fTF^LkfM0kd1QbDTib6; zOK?Na^sm`ZWEXKg>&q%C;kxNtN>NG9m!eW^DJspDqB3kLD$ACla%?Fo&z7PJY$6&-${8 zTDxxh)>8Be=Sxu=wiLBxOHn(v6t!ndQ3tjZb!1CXC$&o z2q+p(K+y;SibfJbidwqPWCJ8v*nZ!2D=F$`e|ps@*R#H?qH(Ufx{VZ#=X@!ez?Pzk zY$=+=mZHgQDVoBTqN!{tn#Pu**Vs}tosFUy1QfkaK+zin6un76(M$r0W)V;{n}DJ@ z1QfkRK+#+RislheG@pQ?1q2kmO+e8?0*V$9P_&qUq9p_rEhV7n9RiBpC7@^-A*5)G z>wIH?1WViRyB;e=(J9SX?t0djRkX@=e`_a2t2tka-e*hE2W%<&kS#@P*i!TnTZ-1Q zrRZa}6s==R(RwzDHV{y>k$|F42q@Y_K+&fJ6m2G;XbS;FpAk^Bm4Kpc1Qcy2py+b~ zigplCw3C3MT?7<;K|s-$1QhKiplA;PMSBS-+DAaqenLpm3fD=|-YDvC|M*!cMY-)) zKn}Q`^<@Zm!fakQuG~LiVm}-=m=YizGq9(QMMHQz?Pz8Y$-aRxFfTHUJ6x|?%6diP(<_1WxLnZ^~Ybgo@%(&@#)|XZEhwBdOEJc5E zz7*YNOVJ&+6y0S@(O+ySy2qBH`)nzCz?PziY$GO(p6BU_3xv85<88%0?ND9TDeQ4#?~*$61gPC!u(0*Z1HP?U>+qTB=&MP=DiRE{l0<=IkHfh|QZv8AXYTZ$^NrKmDn zimI?tRF#0DY6KKjC!nYX0Yx>JU&=mw=*r1QgXLpr`=>MGXlkYD7R$ zV*-kr5Kz>VfTEWPC~8JPQF8){S`bjwk`Picp0!&TJ{_!j_`0Y$@u-mZI)#6!jpWs3!qMy$C4k zO+Zl}0*YQGpr|haMg0gU>Q6w?00N2z5>PaVfTFLW#yIA4k;v!!SX zTZ*Q#rDz&kie6(&(R8*H&0tH>>uf1{gN>p$2`HLLK+!A$ie?i~G>3qqw+JYjOF+>) z0*dAnP_%%6qPGbsT1Y_AA_9sQ6Hv5-fTE=Y6um=0(Ypi`EhC_4IRQoQ5m2;(5K=Tg z(%Ec)1fy~oI1{93wEcr=Wu#|)Sw$a2x+nWe(TAKbMQhkn^buQ%*0QDOW408nV@uI` zwiIn(OVLKQ6n(-*(Ix_lJ|&=NGXX_g2q^lDfTFDg6m27*XgdK#pA%5DgMgx)1QhKe zpy&$%ioPVEXg2{xdk84nOF+>+0*dw%P;`KRqOS-jI!Fj9S{>>9ZGZ%)y9UntQuL$! zzbbqk=~-V^(RYz<#sN}vnDeFR2wRH2XG_shwiNxqmZD>9DLT%Uq7!T>I?0xzQ*0ES zCZOm?0*Zbjpy&(%ML!czbe4dka|9HfC!pv80Yw)HDEftfqDur6T_&LD3IRpG5>RxN zfTC*z6kR8v=mr5rHwh^Ejew$Cgpi_dBArSGNN~CRI@-5VG}$rZ_ejtBvWo6Rx*Z2e z(Ou4$qQBTubdN1X_t{ePfGtH2*;4d~Ek%#nQuH@lik`4h^pt?2e+VdgMnKVX0*b;s zJ#9x(fPkWK0*V|0iXsRoatSDkB%sJ6pvWhnD2jlhXab622q=mrpeT-jqId#|5(p?t zK|oPTLP*h{kfpJ>MoLjf&X=N2Y$@u@mZC0fDeB6WqHb&{>duy;9&9P<$(EvCY!vk-pr{W4 zMXwT2)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eFRlz^gP1QZP?plAdEMI#9)8bv_S zXab7H5KuIhfTD2(6pbf@6t(l5mIg?0oBcXkdnr1XWX1%~v%ajNDV{rGv=mL{d?}j7 zmZI0#QZ$_{MKjn^^g3IL-e617n`|kX$(Ev7Y!uBVplA*OMQ;&MG?##)c?1;AC!lBn z0Yz^UP_&SMqD2H0EheC72?0e*2`GApfTDK^C|X89(Q*Qc-XoxB1p!4X2`E}cK+$SK zNYNzEdDj352JNSaCQDIa`?>4)J#6m2J<=yL*!b`VgslYpXK1QdNiK+%^3 z6zwLUXb%BJdkHAoM?lej0*Ve0Q1lf6MF$Be`kH{ELj)9kLkKDQ&~vUBAi-<)=NGM! zqVx9iMc;a!^<@=(@44;-DLTseQuG5`ijJ|R=r~)7POzouBwLD3v8CuVTZ(>UOVLkk z6rCZU=w||o&Js{`j)0=`1QcB$py(n2MZXYGbcukX%LEi%A)x420*bB@P;`xeqU!_{ z-5{XoCILmi5m0oCfTG_CDEfndqCW{CMTb2np8*nVlghw3B1LKJmu7E!p7muF-SgbK zlceZA=S$H8wiG>NOVJ~?6g_53(cf$-dcu~Xr)(+uhb=|V*eH5VKv9^lr|l>T5Kt6O zK#@a0Q3L@+E&)Z61QdA$6!`=cMG;UGO+Zl$0Y$L{6vYux6i+}=0s%!S2q;QPKv9r@ zqErMFr6zF)6=A=BIip{CAJh*W=l~OwiH!mOHnnp6jf(SQ4O{f z)nrRiEjEg36Hru#fTFqt6xAc3s6GKj4G1V|NI+2|0*V?FP}GEgqNW5Cy-Yw+GXjd5 z6HwHGfTETJ6tyCts5JpauMkkwhJd2B1QfL+gcOzcou>v!aBCU^r-Bp}vZKB4SzlIB zXWz{{LyEd^z7%z3OHntr6m@4yQ4h8h^<+y?FSZo*W=l~YwiLa}Mp0h^iuw^y)SrN& z0R$8cB%o*z0Y!reC>laQ(NF@4h7nLSoPeSc1Qd-VplB2UMWYEQ8bd(QSOSX15l}Rq zfT9Tm6ipj5m2<6fTH&aDEfeaq7MlnMN@s} zH3KA=*M7QsniQR}A0(~uJ?qOVTIaiKW=hd|&X=MMY$@8vmZDGCQnZOJMW3>zXfs=i zwy>q>Gqx0MWus^t0Y%#hDEgd$q8$Vj?IfUR7Xd|I5K#0b0Y$qBDB43n(Ov?I_7PCD zpMatR1QdNmK+!=0ioPbG=nw%#-w;srEdfQ}5m0oP5K^?(ca9h!!4bZJ^RX12uz#)S zi0@fnR?#uv{d2Yy9p`*0I>DBrlWZwE#g?MeY$^JYEk!@ErRWS>ihgEG(OEW%&Jj>_ zo`9kY1QcB)py(F@iY^gQbeVvnD+Cn%Necx$qfCM)r88{E5XoCH6NV+J``m%~LMY*HqOHpRdm!d3eDay*0q9nEyWn)WG zcD5AdU`tU>wiM-JOHpn%it-Rpl$U^_7YHcIM?lew1Qg{bpr`-=MFj~cDnvk0VFHSZ z5KvT}sD zit4gaRF8n7`UDg;AfTur0Y!}nC~8bVQ4<1+ni5d-G66-+2qH zCZK2t0YyUzC>lmU(QpEaMi5Xml7OO71Qd-XplA#MMPmsl8b?6Ucmj$h5KuIcfTBqR z6ip_eXbJ&EQwbqOU80=)21sy;{Yk}LrRbP_k2WpJv%ajN*Q4C}OQq-y&X=M$*-|u< zEk(1~QZ$<_MRV9v^cGu+=CY+|9$Sj$vr)8wfTFhvC|XEB(INth786jkgn*)@1QfkP zK+(Gd6fGm5XgL8z?-5Y6f`Fox1Qe|zplCG#Meh?(^Z@}y9}-ZshJd1v2q;=h2q~H# zT|8fTBGF6zwITXdeMZ`w1vIKtRz~ z1QZ=4py+D?iVhJ_^bG+;-x5&t9RWp$2`D;3K+*RE6dfgm6s?bPwizJ7T=x5}H%QT7 ztLTR)&-${8PDZ&uEtjHGoG(SE*;4c)TZ(>SOVJs&6#dMWqO)u%I>(lx^K2=)z(&zU z0*Zbipy(0-MVAREx-6f#tF9M405m0oW5K?qJ%6Vph1XtNlSD%ogF#8_uL6m2GSw(+Gxmj0A z(G$*>qNi*r`iCt=&)8D*oGnFR(R$`CMFF-Hg|nr|VM|d28$~VwMUey)c?1;s1QbOP zP!vr-Q49e^u>=&w5l|FQKv4n#MJWgF>KLJGr2q-E@Kv5wAiV71@RD^({q68Eb zBcP}_0YxPUC@M)nQ7Hn7N)u32hJd271QeAcpr||nMHL7rdWnFdiiD7&%+bya10-0; z!pRaHdZvHOj!My<^<@=Ri+0z3AVt+VUy5q5rKl!bifXZ?s5V=Q>aeA#E?bJ~v8AX! zTZ$U6QPhxtqDBN1H71~_2?0e-2`GA*fTCsu6g4NHs09HSfTB(W6m=$`s0$&as7kbR)Bp(O9`ogrPLJ?qOV z>KX0cStCWgIA4l-v!$pHTZ&#~OHp686!l|EQGd1+4PZ;rK(-VOVxwp<0YyUyC>lyY z(J%svh7(XUf`Fot1Qd-TplCD!MPmpk8cRUYI0A~s6HqjPfTD>66ip(aXfgpsQwS)U zNBA)sg}0Y&c+Q1mVVMau{% zT24UGdju4%AfRX^0Y$3_C|XTG(fb4xeLz6bhXfR@A)x3Z0*clWQ1meYMe7JCT2BZm zdL!CtV}Jy+#Tz(pN>MKRLDGh3&-${8K8<$Ate2wAoG(RN*i!TvTZ*=_rDz*ling<* z=ySFd?O;pMPPP>7Vx#B_0*byQplCM%MSBP++DkyuJ_3sN6Hs)3fTFJmC^|?$(bohN z9U`FU8v=^HC7|d#0*Ve3P;`WVqVEYPI!Zv%4+In)BcSLwA*AS&XlI215}aqB+;5Vi zQC883XwUkxihhiC_idD-pEzHN&akEEXSNibWlPaHwiKObOVI_k6kTLX(JyQ%y2M7& zWde$>5K#0h0Yz5{D7r>K(RBifZV*s(lYpY%2q?NmK+*366#YR!(Vqkq-6o*u4gp1X z2`KuDfTDW@6x}DF=m7ym4+$uGLWxQ z6g}g7DSFP9qOce}bC;q3TZ+QjQsl6uD1t3TE?bHs*;3@OQREX)6h%N$Gyz311Qf** zP!vZ%Q9J=f2?P|SAfPBE0YyOqic%3!l$wB|Gz1i-C7>vgfTDB+6s0GiC<6gS83`!L zL_kqyLP*h*Xs4h75-gL$zYCmZExWDXPzwq6Ta!YRHzN zMr8(YED2=3j&H-5>V8NfTGp}6um+~Q5yn^+7eLIj)0=} z1Qc~3pr|7OMV$yJ>P$dU7Xpg95>V8QfTHe%kfQ1_&gTY5u$KL5Yz--jw0|L_M~r8E zSw($f+@H5g(W{&Gi{n=79fGtG>*-|u!Ek%RbQZ$4uMMK#r8b(0TZ~}@( z5KuIdfTB?Z6pbdJXbb^GV+kl4M?led0*WROP&AQ%qDcf4O(vjd3IRn^2`HLIK+$Ui z6ip|fXa)gAuM<%81|g)VSBw+(xluIV{tfHiQgqDxn)_yqXMI^kb7I_VJEiC?&X=OO zY$=+@mZJG=DO$jmqPN*nw2&=Di`Y`Mm@P$1*eF^`K+!t{6unD8(J}&xmJ?9)9sxxw z2q;=fK+!4!idGX)^gaPa9}rOVApu2e2q^l9fTFbo6n#uU(K-T())P>)fqTicS(xbczsCv^mCk!vF~`wSOIU zixkbUe=wbn@vJYa=;s)B-EJv5%lT4tjx9y!*-~_YEkzgEQuGU3iY~FG=rUW1uCS%( zS2l{S5>RxFfTHUJ6x|@8=q3S0zY$P$i-4lv2`Ku5fTBMMD7sBR(H#Pc?h;V+7Xd~0 z2q?NwK+yvNiXIYB^oW3>#{?ApO+e8TLP*h1G0rgqB-r16y84V1WzJ&8(-_bCvWmiD z-M{uqQ6N^&v-l7ONh0Y#|@C`wI0Q5ph@(h^XVNI+3K0*cZTP?UjyqKpI-Wg?&`GXX_e z2q?-*Kv5DQr07|UlWw0;l*xX+=(!Xfwu-XFde)a!lq=RPb3lr6bG{ViVM|e7wiLa< zmZE%YDSDADMfurMRDdl-1=&(mh>fDc1QZn^pr|MTMa2jxDo#LA2?B~r5>Ql%fTGd_ z6qO;Ms4M|RQl)fTHSzkfI#1PCEl6 z*uj3^bd*O7G=MEd1KCnEh%H5f*-|uwEk#4wQZ$S$MZ?)rG=hzykpvWt zBA{qA0Yzg7C>l#Z(KrH%#uHF9fqnnFJKgB7_vZ8tdFNK!UyP_g(juq7wF#N3&x+>&q&d7wg7+Cq?r) zUy2s6rRZ(86fI;+(IU1KEoMv661EgAWlPaJY$QF18eX z!Iq*g*;2HdEk%3SQnZ&XMf=z&+D|~y0RoD?BB1CX0YzUEP;`iZqHhQ&`j&vA?+7S5 zOhC~Q0*byTpy((8ML!Twbc}$a;{+6)AfV_Z0Y#?>C^}6*(T@Za{X_^U+8XN&H9&&D z+D{Q}lcEoz%{UY5SzlJs`B?Yuqf&H%^QGt_TZ(>ROVK5^6kTRZ(G|87{mPc2t86K{ z#+IV%Y!uxfpy(z6MZXbHbc=wZ-w7!CgMgwx2`IWvK+zonitZ9n^cMj|_XsGuPe9QF z0*W3IQ1pm^qQ?Xj{Y^m869S5!5>WIH0Y%RUAw_3not*|q@E`llAm^m0ODZ#-$9mS6 zRpi9E=gjA`Q&%Y*=0?Q*&u98BTZ$stQsl9v$Y)DY6kCd-*-{k4mZDg;6veSo6i+}= z0s%!S2q;QPK#}>u%}dOy9uYuMDgug96Ht_ffTFYn6eSW+l#YO+^aK=TAfPBC0Y#Yz zD9TJgQ5FJNs5AjZWe6xLOF&UM0*cBLP*j0{qL&CLsz^XlB?5{n6HruzfTF4d6jdXj zs5${fH3%rGNkCC8LP$~WIH#5Y5*%)y+~<*^PpqQaah~;M71fV(d!Ck}2AnTN4cSuE zh%H5p*;3SmEk#Y)QuH!gikh*ds5x7TTCh>nl7OOC1QfLirNrR)Rusvb_5i) zC!nYU0Yx1NDC$H&QD*{*x)4y*m4Kpd1Qc~Apr{7{MLh{9>P0|NZvu+?5K#0gA*85o zoHNq^3HGqxcU@14&e#u<`o?+ImsK<{&fV~n6b<5hDH_a{q9JT48p@WUVQeWH&X%GP zY$+PamZDK?DH_d2(HH`X#u898j)0=^1QbmmplBiiMUx09noK~^6atE-5>PaafTGt3 zD4I?{(F_8LUMHaF4FZbZB%o*}0Y$S2D4I<`(HsJb-Xeq)^^bE-7$Ct0_K%+dQj|8{ zjJa{1^<@>k9p~QvS&9~Nz7#EDOVMJs6fI#((NeY)y~CEGciB?3j4egW*;4c#8$~M! zC|XHC(JBIpRufS4J^@7^5K#0X0Yz&FDEf$iqO}AReM~^nIs%H;6Hv5)fTE2A6n#QK z(Ix_lJ|&=NGXX_g2q^lDfTFF0kfQljM_5>WIt0Y!%hDEfwgqHhT( z`i_92!vqu^A)x4c0*a0jQ1k-RxCfTGg`6#Ym*(N6>vogtv; zX99}O5<-eTk8?U0Ai>p%2F?yCI%vNfaxTuZzO15O;@k-rrRWmpOVMSv6kTCU(XVVN zy2_TKYiudH&X%GZY$>|QmZIO-D7r;J(eDHl{Xsy{p9B=$CZOmJ0Y!HSDEfv0Rcr12`G9*K+$6YivA{`=m`NuPYEdchk&AI1Qb0dpeQU}&sk9vAcPcMh;!aI zK!S_xH_2Xr|!^<@=B#=8eENs-6-QslFxD2gpb(QGM-VM|dgTZ-b?QWVdY zq6D@SrC_5dB>_c20*X=*P?Va0qBH~)r6r&!k$|Ff1QewwpeO?YMHvYw%0xg>W&(<` z5KxqrfTAPG!oiDl|{L zXMI^kFUGrZze-Vl&X=MBY$+qrKkm4idwRzs1;j^TC-8~3IRoJ2q*-|uyEk$G5QZ$Z@qVWV2O(39XA^}B{2q>CNK+zNeil!1!G>w3w*9a(@PC(HN z0*YQIpy&+(iryrkXeI$gvj`}fO+e8c0*c-uplB`uMe_(KnokHR8Wit*VSof*uRyX#$FVB%tUg0*cNMQ1mkaMP~^p zI!8d!c>;E`S$y+FH2EN`z>p3f@ghMMNtXvCwHYNn)9V7hAl<0Y$=LkOHn*qiW1mTl!7fq zDcMpKWJ^&hHi}XcP?Uy%qO=4QB@$4Sj)0={1QcZ;peQ2&MVSaF%1l5}76OX05>S*x zKv6aVin0?>l!JhxoCFl*BA_TY0Y!NTD9TGf(F=r-A}_%?Wq<_Vv7c!46GG4QTiNfJ z&6nU=Ush4U1oz=RDJsPIQdF2NMMcq zbs?arD*;8_2q@}KKv53@ih2@I)Qf`O9RWq_2`Jh?K+#45iasHrXcGZNpAt~CnSi1#1QdNn zK+#qLinb9@w4H#W&j~2nK|s+?0*ZDKLW-6oIDZ%*!J=lmOQq7FAi*!~*U|P!Q9k>fA(s<8>&q&-mf$uEvo~PA@A^9DOVJIs z6y0P?(Qj-iy2X~F-`P_12V08%WJ}R)wiMlAqv$RHMSl@cbdP|d`vep{AfV_W0Y#4p zD0)ml(cc6VJt3gzDFH?Q5K#1tfTHIF6osYG({>aE2q+3CpvWPhD1v|@mw=*30*X9B zNYSqe&PW3!I5dNSb5)AA+IMe$3eWnoiegi^OTwinj`O7`o-IWQY$-~?mZFqwDGIWs zC>2|ZQnRHf4O@!RvQd;sKv6mZiqaEMl!1Vvj06;ABA_TU0YzB|D9TDeQ4#?~*$61g zPC!u(0*Z1HP?U>+qTB=&^4Axh3$tzF)2dN z^hek)%@#=ESzlIBkreJP5mHo?^QEX5TZ)RarKkj3ib}Gjs1#d@O0%V?3|orIvZbgT z8%5;_D5^j}(MtprRV1LO5&=b(2`H*UKv7i!imDM%RGomL8Uz&8B%r7k0Y$Y5D5^t1 zQC$Lx>Jd;>pMatU1QazSpr{c6MU4p|MTJs0k*-lR!G0aBuoShkUyW^&!n3}tqUI^w zJf0M_;Cv}+$(Ev4Y$PkRSHv)>f6HwHHfTErR6!jvYs5b#ceF!Lem4KqY1Qhinpr}6qMFR*Z`d`Go1$Y!^ z+rK@V&16H6k{}5lT4-qtgaAcaXd5Ds5|R)BswssaEmoxNM%~@r-QC^Y-Q8Wk>zetU zn+?zNyzlcJ-~T)QdmQ1~-?=lh_s*Pi&)l=ZasU>s0ASHd02ZwRV9_ps*rKMc$r=-+ zpvFHj+boMdFR-v{*OdF^7VX(JT--qx?Zy1EXm7GC+J`KQ_9e@r{m8Otf3hq(fGmp+ zB+H_M$g=2QG8P>Iz@pUvEIJf`MTY^f=x_iQ9Ra|iBLP@+6ab5k24K-K04zEdfJMgv zu;_RI7M%dVq7wmFbP@oIP6lAnDF7@w6@W#j0kG(F02ZAAh%MT^Yw~y#q~Mcc6K4-u zbfRB8IBA%c6_Ovgl&6EV_g&i!LS0qRYs# z=yEa^T>-$ND*;$^6#$E_24K-O04%x|fJN5ADk}Qj!BFmzu$+GAfG8R1x zz@p~>SoAyqi(UX=(Te~qdI^9*JS@LX3b(T`*-`U!wVKLfDn z7XTLh3c#Y@09f=p0E_+rV9}odEcy$8MSlaZ=pO(U1^F7bV^IQtMOgqWN&>Jb8-PV2 z0E=<}Sd;=_Q7!Q0tLJ;<`CCs`I1l4Vg5Sr+voV^MDa7WDyOQC|QS^#fp0e*hK@ z0ANuu0E-3!uxM=n7OexoqCo&G8Vtaqbpcqk9srAm0I+C%02XZkz@iNSSTq!XMZ*AC zG#r3MC4ktX&iTp9O^||1LKCM;emv5z^Q(>{@>A}YTQoX9e4@K7+KBmO(HOEU8cUW% z)|vMk!3 zEQ@B7Wzh~~Su}@?MRNgI)C$0&c>pY$55S@Y04!Pvz@i-iShN!WixvT}XfXhbmH@D5 zDFBO>0kCLi02VC=V9^Qy7Oeze(JBBI?E=7}T>)6M8vu)T2gDZ5%ukLnK?-j1v+G&1 z=!t1%ttQK& zL&;cl7yye72Vl_=04zEZfJH|Eu;^$2799h?qGJJAbQ}PSjt5}T2>>iQ5r9P}0kG&~ z02ZABz@k$DSaccyi%th%(HQ_NIun3JX92M2Y(Q+$UirzrOpt=lQzp*dvgjQT=j5l{ zFSqD|{P3(kvgktQmqizmWzofCS#$|m7F|k~MVFCf(dA@WbOl)!T}hTjSCO&kY5*2p z1Hhtd0a$b$0E?~%V9^Z#EV>bZMK=Mk=w<*G-2%X(TLD;f8vu)L2Vl`104%x_fJJu! zu;^|87Tp8DqI&^YbRPhV?gwDe1Ay3~^YWATn;-?7b~16!mqmyBh3p6OQ|^~r^k{zg zK|fja81u`b$H}tj39>ADk}Qj!BFmzu$+GAfvMhR*EQ_8a%cAGWSo8t_i(Uj^(Mtd< zdKrL4uK=*CQI>xPa*Mvo57#f2MPD<& zEc%8li@qhxqVLGE=zFp(`hhHqek9AHpUAT4XR<8%g^WeN0e02ciYz@k3@So9|V zi~a&&(cb_p`UikTL4k(tSd;)@Q5FD;k^n5q24GPLz@i)g7Nr1KlncP34gf6517J}{ z02XxuU{Pm4Y|$6_$yyVn;I4cV=Sx}C>~Dv3DM-0rZc#x&xO8n<)Q$ONQFpQ|>Oq!8 zJ;}1DkSvRe$g-#xSr+vs%c4GHS=5(|Mg0I+)E|IF0{~c548Wp+04!P?fJN&7uxJnf ziv|O*Xk7pntp~uOApk5|AAm(00I+C702U1eV9_uD77YhrQ3(KxMgXv=6o5q|0kK70 z3z8?AAO$OYSe9Q9kMz$rdBRZzDfi1Q8e0(FG)NYWV}4mQo-B(tCd;Bt$g*exSr$zs z%c4!mvS>51EZUqbi^|AYGzox3)|vMk!3EQ@B7Wzh~~Su}?%i{_GLQ7c&% z%_C#cd;k_L0ASHV02b{Cz@nW1ShNU$MT-Ggv;=@fO95E441h&D1F&d00E<=tuxKR! zi&g=!Xcqt$?Fzu6-2hm$I{=IJ0ASIc04&-I5L>iWL9%!~vuLq@Fl}pD^r(NUaqohZ z`{fqxUl5k9FN+Rfepz%NSr#2cmPH4XWzivIS+trgiw-5rqQl6t=y0+uI)aQvM*^_u zC;%264Zxyf09bS^0E>WKN|%>ePQLeAZRK)V&fo~RruV5AlRm`aI+xTzHr;J zAedWtL3t1?DEzE42o@EVObLQzg{!s*f|Z4L)C9q9g^9W#*sE~z^dQ);@TkThIH>T2 z<{&t>LEQ7S3J~1a}r*vMLDfE&OWNAb7BF)E+_bXyNXA z1;LYr_v{k{&lZOJ2f>SlQx6P+R|}6jI0)V>d}VbIyj$4s@F4iGaL$oI@M+;?M+d=| zh2I<-1m6~JbV3mPSh(j&LGWwgeWwJ$pGB$DZT%;Trk&|OqFi*s*|r4|MX#M}n;=m% z-~!tQiK5nvY$GI!uDHauLZaxq%WN|wipE}P+aXcp|C{}wM3Mh@C!}zf8XTFM3H}C;Mzoyf8zVbM3H}F z_tr#_f9CSeM3H}J?%qU^f9mPMM3H}N<2>&%vc^)TNYY8^W71NpwCNr{>Z4Y_K00MiEe!k zw|y@$YMQfpBa`f}Pe&UbCq^xBW*auR!v6YRnAj=#X~h9!djiTa%Uk6t|Fwtf32riYzAUcGwT{)vX1{0CmR>V`e~CmM6|ue|i} zKlcp!nO@OMgNJLTw-0+@wM{WSC;yiHAAMVmgrz#j={a=tO zO$7a>Xx>Yi_v0rg)ggY~uu!|P+ZOn4= z&pP|$A9st|uk{A=Kt};o$>SSy7Z9o z(evH1|09>|8}vI{vz*M+oP5c1@5HP7!Ow0vbN6UPo$~T0{;I8&7ajA;Q+oyd{!GRz z{PK9Ntlfg3-x&L3hHr$sGuR}t=QCKX*vA=cE3w}**x6!TY?)?Hv{A1$<{PyvW;yv! zK6=Mb-rBHJ?iCHmXpMfbx^8B)PS%@sx^2`OZI*$)LZ8*Vd&l#Jo!-7{r(V&l!|vK* z*y{aU7wjM8ivLu=#Z`g-> z2gP}|SNj~+;IPxKL+*~-cKrqG_|!T1pS^I`t8QFQ{-tk!{kI)B25wRu1pb$kmCPCV zz8!r1FK2KvZ(y}i|I10*Bd6QW?0-4GWaSKe(2majm-DHGo9&MO<$Pk{X`96Va- zK_WjfxJ$Q=$u51mG#BP4x)ugO)}Wwc$4w0dL9%C%?6PskO*)S6Sl!JIHhRQ5pm3wW zNltbm*=5s?9qr+GvV_6Z5Sy#7JzZ{e$6jrR=#KRcd0Jo?FR)`GQQggF=`_$5S7Nht zUdx``m)xaWqGQLlWvkhXKScGb5V51UR$rx8PB;{uL<_a{@%kAoAsh0>-DPcmY*od z*}UkKNxl4e`-B-YWEI{r$<}$_%!T->>vz}z3EMWM(c0;M_yLI^tLV5%)^QH72LgY< z4&_W^iVP3@sh4z#p4FNjw7=Pzf*ttky*zKeW(Pkc>d*0euiBqI;KdI%@dFw2CakN; zxNU6r6Tx&ZW4ucbW_nqmMNU7*@A+cw0WWVxcc**#+x~p%)6emH(Sa?PnX%;bU3-l- zdxMvFNi*7()Zj~s=bga}eeI65!EW}LZazuoEi><72hwElg3XeZ_@hhbAYnI~*8UR1 zhnFm$T{3UQvXT|c=aejOSuv-zW!dtjD_iHRY@J&&XZh~SRxWigr*-bC<*h3+9`osK z>hUGZmM>hqaOJ{XT7!}WOBc76%wE*GTgmW6OXtj9RI*~h?B%T`%UhSUu9&@|q;+J= zij}M8E?io&a_Q1Va~8~AxMW4i{5f-4W-nh{QaYk#RLjT_BTHLKM>rg2aM+TiOInAu z&fa0+u+kC3M-B6bhug#L9x7S5WX_^hb6ZOm&z`ej;gbLB%~-Mfip(`Je?dvv^0})P zE?HW>bb0Hr^t#w>@;R{?|Ghyz+ zB`Yo1G1L5OnX`29;-yPkW-nW4%)D+auWYfkGN(M^#!PVhT^y@rRm6T&cOo3J1!G2HGyRBaw&DbrPaiTrq3z!)8w%RT8p^|W5PWP~&|9`Xif}HLp zB_qOaCE+^B-R&9eY5GLZ5;bp7SkTu~PLHr)a&*U*J2bk}Ei8y$2QQ>V?I{WSTYGYg z!wxyg&J)6(7CNjG_Uvc5#9GyJXmqDr*mHp2DTybr)lujZT3y>}pS8nI{lm^V$=(y} z)pZNkUpws6&vHrhT067Sy2UGPeXX=84!6lhhJ9?Np##G82Zeq5YQAn^p8@}G7SYez z(Rpgvr`l(-cG_Al8RqwG(Y+%Wb{G-0x~DZhdNFz}+N5j6tsAV?MRB;j#F1eyf2mW$ z!s=)Z#4o*P$-r>%+F@beXeC5z&0cO?|JMb^>u#df;hJ^RaIimN)Q)w+|J*EJ%Aoba z!sPD0@z^43E^VS3Mcvew+k?dp%6zrHn32)sh4xZx9S$B5_Ux0fY+fMszj~oP2eFo- z2Cr)k-lKhkdzxp3?ip=l`D_2@woXX5wS!F^Z<+Kf&2+OP=qUZ}48Jlccxk>|FuWoMF#Bhi;zPHQ&UoD}J%~|66N7RUcCcatw z-|r{u+T^}-`SWSz|4%zr+r(LOyT|MDznlEOT6S-1ezb@A$_V=m413#pS${;>+qZAq zi(2zVM!V*J(|+HhdrvG0hm2_J6?|>k6Gdz7zggiW-Y##GZ*yj(MgQxov=&&85_dy( zf8u|*@0+w;XEo3cDLw27leg~kf4@VFn!jbV*4OM1yXGWs-*-ZoNdBG}9_=Ol^c zkC12=(uPf+ry$A+&abnwsW@c8`kJ&x{k~mYUi3&jrA>+4Gk^T zwKK|Usw-N`8YVYStE_Dbcwky(V`JIm%9f_Ox|W){+Q~sf<>Z#qvhpeEDaxA~n{EE` zx@q+_l}$Efb8WSzt16$;vP0X1WepWAwRKH4absmeQ)NZ^kuBOKtPCNtF%$I_etYsYi{=eB#==md55u zjpYs1K3P>=b8SU5+1PPYqB_1^GaD)!>+7tA@sdW{G^`76du2meV@AtaZ_^qlw@hlT zs6lP*&SGt-2{%azkZV#g@^Fnbc0$hQ=~mP_(IS1xsw6v#znc zrLn2b)@h~bsBIXpn|2Gy*q_obSoW0FM97;GK$hKi+j^?41>rGpcQ*GO4*SUdy&` zWcEk#uH-V?O7@-G*GIQZmFA5*-%weH*?J=ZK$1`?l#SPp08>sE6W8X6#whdvcq@{9Jd1YlqMw7KdtcPtXvmRn< z<(4f~W!1iyvkf(ckKn9nbJIJD?OXe3_rxmf$EWXt4Ft4q{#=5q{ zlz02-$JFmORMu2ReY3Bu%Jv?`TiRc#-Q}wh;+e*>rwXPVs(U{3|7FV=J z7m})%EL_>RD&t_y&QWVUK(h{p_9D`+vfP?9siDjc_!7+9W7{rs2eTDPXIxX)s9k(q zx;eIy;`KX;JC%_RD;CaQ(mJ=;u0btNKb_lNS7nPch1xpswhp4aysl-6bzJEgSaZ|r zD&p4LIYIit^2(Z;=9;nw+XW_9H=6B!AmfGL96dtZ#t}Aq^b*^3>CKIkqJw!$;}kn{ ziKn#Aj&3jGDW_FhN2XI6p2?S2YJF%tUu9(3swJ5(->0x+L%QJ=BP(>kY^bcQFqboW z=k(?;k4}wbl&!@j^IKb5m&{!_dr6D$Y3YSk*VI%_F00WFY3BeH)+4kX1f#tneZ0!p z%BADl?GNfvrr44)PQfa8S+;T4aH85f$2Gd8%u@{OD54!aT0QCgrgWor3u5PDYh@hm ztCv*FUOBsEYU}Pzc1+_I&4LKW|gg)#wi)SH5S*DZRw|$Iv&Tn@Vr$^ z=8PCUN;`C%Mys{$Bu(4C#yV&FXPg|@*xt})0M9XTe0f+PurS zVT*?^w(Hd!&Rwx=!+Fb!hs`e@RyVSEm|ex3IL8_=Y~JG56)R@XZymO%b;* z6z^rjypyryYj5SkrAvmbunWCbR~VaX5~XwW634bPFxuwv!NkUhy*7jGXk@)YlbwkA zQ9V5YTQM3jwQXG6%d8KtnN()OD0QpeY#RZ@%^%xlydC>v)_%C+g9$%%sJ78Ue3B8r z?nu6cHA|N+D-EJD@?YB0?f~BIym*=|X;R&+OsmI?`Z=#Fjd7+6o1(Sb!sic32Ah4 z9j%bjwxre;zmDFze0jV~8`S-q#>5?WLuI+QDn4Z`wZUmLOFX1)v^N~uPBi`K({_et z!&&WAt|Bp_N!td9>5=UiEhQe)@vL!2UOBBkW1v>(2?4k9{C zm;R5BYWJ~Godjwd%(Wk*xr6C5B^uILU)`dywr>x{hGprc*^z(+`w5Vq!_Itluha$x z>Gox;f%=BJDb+Swv`tZKXUul>fv1cV@rJl2)pl~amC4Z3V(;y>T?;9-b8mZsXt3Xq3S;>c8~aw)M3dOiH@&#@{!%rw zrP(fV*~-)cwLH7P#TvAZLw9}jrdGBs$p-X|-Y>R!>6851lU6ovyNh=1&Y#og%#_Z8SBFjdOkL3X`ETzWRGMVK^fhZwp|)1wVpXxvB1uh z(&OZ4EN8E))DFtg6Zq)NpD`XpMbDkFL)qDL+Zysqw$XJJKP$0o2`!V$s^bfJ=3RO+ zR*sDdnrqrlI9zwmVKPru)0cBbayiGxb*v~B=I0#2j#1y|P4r@sO}x%DB| zr#D6GDLqxA4Q=gGfQI|5w~UWB{GWPLzoK=ARr8}Y>O(Xd>APatq}Z+aQZkS53af17 zWrNg~s+zLKw)uFpx!%q8YXe**Ut@rj-Zte`O1{YKkaWJTqFIFIxVyk%um5Dmb6nT+MycK~j%ovT#Zbql+Ss*mi|9X6k$6CDD^!2xBk!=^KOYL%5=Kj=njmKYcyeG8lfzo4j zUt)S)W=fYH>}mx^*N&s7r5kTMfW;Sr{XrksMHBf|QCb}xaZLb|x7_x%fB!Z`eATz@ zaP%*IO{tFzqGkIPRF<9DbOaf0c`uW4)gpoOD93_gNStjcqq0bJ+Q* zd0t^>CK;zJJeYnrh(l*Q;)vFgUk#1MP_YJn?UmP+sX@E9PxOMDYp2%M&5YLvgBrj7 z?#qqG3M^@oU2V4a(xUe{qKAFN!h;zn4ehR=M9nMJF~`R<5%8;<(Vh4Ttlwn>Q<`~U zQ%m)W=vB6JaOsFAjb9tRi+0D1YozVR9h~PxPiz|?-S%iNw8K|ZS%aS#+MZ%3A^&M_ z%(z6WS5+EcU-iYtBPp6^SNL@v6P;slkw1F=jDA{L$0t7N3z4=@bM~T+lK1XPEBYHOUmRm#a8YlHDyV{@au`=#;o zzg*h%tD0-P-H~~*WkkD6FKr`Bd#7D*o_VW$;FBJY@%(-k5gi`?-PqTybgdcB`BJLX zg_YXXvGn$0EyveMGd?&F4??2Vo_T5;jTUFxo5B8ec%9zgrAhIndcS_N<{`!po&NSY z9U*VOGUue4vf8QEHB{O)wKdMW{H3fpdE17msk68HtfR8auVu9v*Y14lw7>QekA32y zK)Zu;^cvf)%f|0Q(6F|%zIG!WU%c&N&Gxcrn=d9FsYLha&f`m;EiDYES#ZYDVM@bP z+gR~VUTqtGR(k8qEVB_io%9-W`h_AtG{@_w?dqvthfGh(+cnYHaB_o>#MfB8?M9>S zQ`AHGsELKpwDPiYThmo7(Wyn?PtS)R7)ZHU+S@ZnO|dQ+XF5JUi#tNUw&<%X?tFO0 zs8?zHPj826&C#s%Sy(*UiMFO+f@ERQ(W|zs?XwKN?bcig^)2Z)AANmtTxwfJyme;Q zHB8kpHGS?;8ec+XQtQHaBc%QCtI94wGIH@xU<8xP%Qr3_;urhNmM<=@T)ac;+`0Dd zT@#-okFNjo>G1Xc^Sc2-C;Qm@KX$Y47VOofQ|Dk%#z*G;6Z4b03^_3GpbiJ;9+Fy} zb7**2_TkARvW~Vd){M6aXZr`ygM@uYGYH2Gn>O4AB(*_Kerj5WWL|DTcK1Y&L}9Wh z(JRqA(I?S2(LZbLgnh&5Uv8NwJNWLO%n6eIap{a(QlIk&CH>RV8MmZ;Qrf<>l5xup z>|1QXm+{vF>|Xr%mFd~y$NQ$gEztH20$)fnuy3qn+>+^U-o-E(*w=6}Zponi*DjKQ zeLpYbmJIBhei^r9)Vem14D3rC8MkC$zs#O-O9u9ZXv@AlvBxcvri>`5L)# zjXZmeymXDc_Zs=YHS%$5WIlx+9|{Mp3<1eKpsd^5u>+g}iR6x`pZt)zek4^lH!VUslVruV+4~ z{GnI-N=uGy->6!ybyU$*&DN(hi1z9HjK(D6P5OLoxeY!EK6ICav)~hzF z&QaY_b!XLmRS!}H&s7S{ap1s)n8Suvyaw8 zj(h9tQMJ2jAJw&0*H;~(I#zX4)k@VG)kf8=RA;L$P+h9Ji|XF02dN&Rdc5jss^_X+ zqI$LJO{#aQKA`%z>T{~Es=lN8vFcZ<(SB^};}7L5+n;^?bWrW8TBzDzb+GDC)lsS& ztCp!wQLR&*p}MW=T-BXam#glsx}WN5)uUBUQaw}k0@ce^uT#BM^&ZuSRi9FQQS}Yg z_f#ux0byDr7+FNy?>JZfuRsSNe&o@!ELUpQYgX)&5+pEr3U81^5 zbuZNeRS#D^PW4pPb5t)@y-L-;0qpI$L-l^u$5j1`!T$Iws&A`)r23`m530YbCafR# z`Epg)QtheQPj!&$Fx4@to2gDwovyl->KxTYs;gA@QC+QitmC^ zqx!1qd#azS{-FA&YG|iS{(8Hp7OEDjuCF>$braPJ)oH3TR9jRRsP3$~hw6cNl#tswV7r75w$(sdiT#r8?P83H|X#)rEHK_Pk2< z2sUVZZ==m?zF?Md@xmwa)m;1K z2G2cIYX`)6Yt<76#`!$e*Vl>jC#uEk#(9|PJUhYg<*iV?a)UVEruzNRIRB$M&Q3&p z`byP(O5=Ql>Vu=={G4i@ov`@yg{t-A;=HZu$@bM_fBXW~Hz&mTGu5>>i*t$Ug0eWT zQoXu7&UdK(SQ+O;Ra`f=0hTY{K2sFc{kDkfQK}Eu#Q6o)PIYnarP?q(&Mm5^HpclP z)wk`0%a{L!>Y!P1E>+!et2pnfdhIrGzDxDz?c$tliR*;fajjN8U{0KmQGK*E&M&EU zSrF$ws!cn_dA925i{gBV>bpzg{FUmuJI8sH>Y^2Kwy*g{uj~3%alJ?N*InZr?iSZg z_lWCM)r0nm^Kq(=?-S=&RJ-mU=YFa)4vh00)iV!{^JS{?SqB!rZdh;c5en9ol%i`SO^0-dAGOl&1hh81$lT@F+HqLLTcE2Ic z168-WDbDj%&%GtiSE+t%C;IO152{1&jPrQa<#)${W>|=3$OSR{dab8Dto2TQvQ1$$0<9vOI9{db(#Q{CRK zHu&RX+GZ{!MkH4bc4Y%~W@@-&FE^uajLp_vz14ec671$@2%QeeIW+Jg=|1gAD{dFIBzNew)ejO{!npk2HDyLv?g#syXY$xtnUu`f=V;^?Lh#AfNso)hAS6_8JDkN6O!N?PNdfrTUwA zw*3r}^IX-=UTt|r%6(M_iVs)aM0JX4v+542OI7z$Jxujv)eBUwRlUorwfB3~b?xGv z=Z#ettL~zDnd)7t->LqtI^2G=$LF7|dWz~5s`seAp!$jGAF6BFuj}~ylT@dw?xT9G z>U&;oeSM_*wd(h(f2jVWnrjyZeELqRJyd(CuC2PRYKiJ7)!e}L7i*VovZ!`bEmR$- zI#_k6>Il_()h5-gRqgN|EpMKx9iF4SQq>NpQQlYeKvg@;Mf_;hQ&rDYwQfFo{1(-_ zRjpf&xOKBpeMyyn>t?dNJD zUBEs2F#5`1xPSUP7{0@b6~S=(y!vp5!{bYP|LIC%G~HbP(2%`LGH@t;56Ec>Gkb~m`tmNmil4{qFRGLX5v z{T3yHbIlQ7p05L6rY~=<{V|W-4c;A-2;Rs5+}&l3>FyYp2<)($zA@c$Bbm=zypR1f zpD}-4=REJhcAt6dZgBqiL{RK^bmOu8EoUyTt6lW-{lS-K!@TtJeBWapyBpkZ%k$~D z@z{w5GM87Ju{?hVf%e%cUc2QzZ_C@q_C;chjVwyCw6t$e&VBegCfy z2KWE^Zr5(xcUy2q;?EcBe!RE2p}2V9lftFj>}tDtR&HuP z+X~s)p?|95&e^Zl2 z1ljB9|120_u{6jYqS)W!$RK-t#eNn?1=$-Y_O&=V$lg$~kHw9G?4gRiEshDYhbi{5 zI5x;0u2^JoT##L&SZHy4kUc`Nr^QlhR;h9i&(^My%H2I%!$v80^K2~}tz6*QnzoU0 zzGrLO80D^>t#MigGvo&wLa%a!hzKxYTSsrQa+eEpeXKUXCUzKO~m zJX`xVRnGNn?b}Q_<=NV|xpIzYYhRgi=-JvgNjclIwXa+`>Dk&>p`2xTl(nx?IpNvb zSEXzkhU}yq z8&aM8!nS{h3$3Hc-Xb<+k@Zm7i&Acm8?r3?!XAta*;%v7kmZUpWQC#(S*a*PRw>Gm zT@+==u8J~bH$@q;yP^!)LlHyvRK}3Klrdy)WenLz8AJ9}#*qD#F=T&b3^_mLdKD`Utd${2E~GKO5H zj3JjRW5^ZC7;>dDhFqnLAy+G7$Ti9sa;-9kT&Ij7*DGVl4ayjDqcVovq#PS^LbAlR ze}_H24>>V5qJ=lriK{Wej;t8ABdd#*inJG2}^Q40%c!L!MT~kY|)J z#_@7nCvNMP&?mNf|?4R>qK5lriL0Wej;u8AD!Ijt#jrIo-B@hoAi1 z5koOg3$OnotUn@{ytp`B+hge4;2r zK2?+I5CLv$GT7Nj4ns69m%~c+i7_xa*<^_E$>V&v}~v4UC2Ex`?zK;Ko1Aj!mfbs4y=j! zfNl<~jRk-L2iC}LfP4qm%I<)!4y>6y0Bbq0cJ>5xabOKC1ax*_EiD3cGT1Opwmm*;$F??IuWGj(07|L~K!x8#OqQa=qN5^%J3gRv@xy1Ll`S z8~vWlORRXZ63V=nE0a!Ez zfJN1S*rN3k(dUTsE_QK-$fAL+)E0@9`{fqZCc=SssVuUnj`?L#Jy{k_C(EJ+vMg#O z%c3T-ENUjpq8VgaG?OfgW|6UIO8^#a1;C=M0a&yR0E@N-V9|B}ENTH@(e?l=nhn6B z9ROG~2Y^L$0a(-uz@m8oESe9%q6GjfS_r_R9RXOh699`A0kCK>0E?CYVvA}L$tn{h zFUKy{Wlxhu)vnZ1`$$wlY|)BDINvTZM;5JQep$4NEQ@v_%c5P$vS>H5EZUtci}oPP zqCLs7XfLuX+MA3;`v9E2f(8J0a$bZ0E-R;V9`MUEIJr~MTY>eXf*(f4h3M* zVE`;T9Dqef0I=vt02Unuz@no8Sab{ki;e|g(QyDQIv#*UCjerLc1|RZG(qzAu#tB5 za#?hGG|oz-+%NBoPECYY+1rMZMW->pEIOSmi_Rd+qBF^|=q$1?mMK=Jj=tck*-2}j*n*msK3jm951;iGeoJc-zg5-_&;nyj$Xgjy) zwnWPPa*OUtgg^9_MRzm5EV_p*i|!@MqWj3Q=zg*+dVnm89wf`6hsd(%VX`cGgp5Ux z0Y02VzCz@jGrSo9l>Gkw_NVJMekU-WS~|i~jVhf^R2M?w4Ei zej*%ipPY^Qq7Rr~7JW#TMIVu6(Z^(2^a)uOeM*)^pOIzJ=VV#*1z8q-NyehD09f=j z0E@l>V9~b#Ecyo}7X1mp zqQ3xG^fv&D{sCZ7kd+?g$78ev0E@B!u|@ADlG~Xed5_s=9>!iNURqG8N0 zi-wbBQ3+WVjUdaSQnD->NtQ*U$g*fOSr%34Gzox37CV9S6yx2IiMVjbvHWM3zO( zWLY$WEQ@B6Wzj6MEZUMRi?$-mqOHkTv<(1@wgq6(b^t7D0btSg04$mfz@i-hSTqNK zMRNgI)C$0&c>pY$55S@Y04!Pvz@i-iShN!WixvT}XfXhbmH@D5DFBO>0kCLiKx|Q6 zR&s<1lDDn*MfI|%$&YBuvr_JtTeM47IDK7Nv@7$=qTR@{Xm_$K+Jh{M_9V-qy~wg? zZ?Y`fhb)WsCCj4y$XK*L0E-R)V9|j9EIJ5)MF#`0=nw!Ftp;Gxp#Us841h(41F+}_ z02Unyz@no7SadW1i;e+c(Xjw5Iu3wE#{;nF1OOJD2*9F~09bS~Ahu{_R&o~;B(Kpg z5v`I%UHq!!DOoA^%Pl%1D?DY0EIO0?G<(NzE}x*C8**8s5SS^ySZ2f(81 z0a$bc0E=z}V9`wgEV>zhMYjO3=vDw0-3Gv-+W}Z~2OzfSw5;TvCP?1b` z8UTx42Vl_~04#bFfJJWsu;^_77QF+&qIUtYMR#WGkQ0a)}K0E>PHV9_4{Ecz3GMSlUX=x+cP{R6-v z`;V&6u+3=isN1C)e>XM(z@jVw79{~#lnub55D;7RK~{2#36gic_eCGdqDg*sos&$t zUv5!eGF(_9i#jsDEb2s-MV-mAs0&#ZtwokaUCFX2pDc?C$g-##Sr&CCV^I$P7WD*R zQ6T_}iU3&D3xGwv0a(-rfJJ=)Skw=IMg0L-Gys4_#Q-cC2*9GX0a&yS0E-3zuxKy< zi`E5T(Ru(Z8Unzg^#NG40U)+0H<>)z1j)PIPlY-p34Gzox3@PEZT}Ji?$}qqHV~sXj`%@+K!AxEdVUq9)Lx&0a&yH0E^}TuxKs-i&_C#G!KA9 z^8r}20Dwgc0a&yn0E>14V9_D~7A*!~(Gma_Ed^lFG5{9s48Wr004!Poz@n9a*rJAH zviE4SsIzxJjk4%DzmUBunR36}qTQ3>CSzpL9?UO`_9V-qy~wg?Z?Y`fhb)WsCCj4y z$g*gEvMf4)EQ<~#W6?nXEIJr~MTY>eXf*(f4h3M*VE`;T9Dqef0I=vt02Unuz@no8 zSab{ki;e|g(QyDQIv#*UCjhYML;x0@1i+$`0a$bj0E;=A0$|bA04%x&fJN5=u;@Af7F`d(q8k8MbRz(Z zZUSJ@%>XRA1%O4j0d02bX2z@j?Fj*EoLY763l4a3jWLfk$Sr$D(mPJpJWzkb) zEP5J%Mb7}R=ve?3JqN&|=K)ys0sxC%1Ypri04#bLfJLtWu;^6)7QF_*qSpaf^acQn z-UMLLTL3J28-PXc0I=v?02aLmz@qm7So8rPw&=cO@=FsW?`*&7c)u)~>V46N$&~x$ z7JZrwJKHy0Ba1#`ep&Q6Sr&akmPKEZWzkn;S@bno7JWmOMc`S9{?8F=ey%!I~FAX zSd<08q9g!|vH@5W0!N17mc`}hgnJVv9OvCwDVJ^5%M9)G0e2>EGjL*Tb_@?w4CMGCMr2Ocsq|epxh{ zEQ>ZG%c3!4Su~a`i^h><(Ri{f+L$bhHX+NR31lpq2*9FE0a&yd0E;#UU{M(WizWfE zs2qSr6#y)%1Yl7W0E;FAuxJVZi>d)wv;_c*rUJ0227pD=09aHDz@j<;7S#i=XgUCk z8UV3HBeIisn;?1ib7l790iK1TmTle0X48Wo#04!Pxz@lXUEZP}>MauzLv;u%dD*;%v3V=ns0I+CRKx|QSb~3xd zESl!;fXt9ZH+f&QTXxF*a*OuL4hL7sqP>}47VSfpMf;Lv(SBrEv_DxE9YB^v2a;vc zL1bBUFj*EILdK%i04zEbfJKJ^u;_3A799b=q9XxVbQA!Kjs{@SF#s$&7Jx;^0kG(J z02ZA9z@ifYSacEqi%te$(J25dIu(FLrvb3&bO08e0l=a&0kK7UWGA;ULGn8J=dSmZ zMeqB^M9#`ixnFM4dD-DkQ)JQk%rA>BAj_f)$+GAovMjooEQ>B7%c4ukvgk6hEV`U5 zi>@GJ(Ukx!x(a|rR|Bx<8UPku3&5i509bTA0E=z_V9|{LEV>DRMK=Sm=oSDL-3q{> z+W=T}I{=IB0ASIb04%x-fJJu$u;?BD7TpWLqWb``MdxHEk2OK^*7d&VTv_yhpIzUd zopQh2qKC7?>$Z?Zk1)S1dXy}S9wW=5$H}tj39>ADk}Qj!BFmzu$+GAfvMhR*j784@ zu;_UJ7QFz#q89;J^b!DzUIt*%D*!Bd6@W#r0kG(G02aLgz@j$+So9VEi{1uc(K`Sv zdKZ92?*XvreE=4H0KlRT0a)}A0E<2b#1=i6oqX8@$vfT;Vh_opyL_boNp{Npa*Mvm z4u7eUMPD+%Ec%Kpi@qkyqHoBu=v%TZ`i?A%z9-9~AIP%kN3tyXiHt=*1F+~902ciU zz@py(SoAvpi~ay$(VqY;`U`+Xe*>`S9{?5wp@!{PlmK8+766Nq04&M|U{MIbq8tDg zr2trz3&5fd04&M_U{OavY|&@g$-dLfq9go>_PH$j(vN7J!j${v7Ih87iFL9lpZR4` z0a+GxBg>-hWLeaMEQ@-QWlP^O?J^(E03&5g&04(Ycz@h;FEGh^bCh61o?7yyfg1F)zB zfJGw!u|-|NjWN0$|Z(02WOF zU{N&yi?#q@(Nq8y)c~+)8UTxG0a#QAz@mBp7EK3WQ3C*r8Ua|;1i+$ZKy1;dFnOs7 zl2`2A&uCe6mWLT(%KdVSwhF_?8fDSe%rA?!AD07VSWm zMRUlqXf7FxS^-!z4}eAU0a&yEfJF-dShOPmi*^EF(INmAEe2rG5z^!K02b{G zz@p^x0LD*%gj17Oka04&-A5L+}WOnz;G>iQ5r9P}0kG&~02ZABz@k$D zSaccyi%th%(HQ_NIun3JX92M2YycLW1Bfl!J4}u?LGmv5Vc9;i=o#;e&J9!Ums@mU z7&gz6MHex@EV`I1i!LF{qD#rL=rXb_x|}SFt{}^zE6K9xDzYrPnv6x)0I=v<02W;b zz@qB`Sabsbi*5v9(M

-U2*3VL(v4shoXsgD4Jx4q8;r}w38i*CflKCiXDok+M#Hg9g3#g6zwcfG((_h zra;jwfuh+0MY{+T?J7{Tn?TX-0!4cW6zwTcw3k59-U3DY2o&urP_&;w(f$HO2M81$ zC{T2eK+(YhMTZDAMPu6)PRW3j2c?^zaiM6T>~2!sq3ue^S5kCjyW*`UhoYk#ABv8) zL(wsIC_2^-MaS8p=y*F6onVKe6YWrRk{yapwkbMApy*VAqSFM5P8TRTL!jtPfugen zip~}&I!B=BT!EtV1d7fVD7rwP=t6;_iv)@;7AU$zpy*P8qRRw|E*B`eLZIkMp{D5Y zc7?YxAmw4%tUDqUt(hM7U)8RZd?iKKwJZL8YACwi@uBDjI~3h$hoYP8P;|2$if*w( z(XDnUy3Gznx7(rU4x6Go1&ZzxD7ssq=pKQhdj*Q_6DYc0py&aCq6YeSfJ<; zfuctRiXIavdR(CB34x*~1&W>$D0*6;=ox{cX9bF$6KaaCX;)b6v`o50Z`L($vm zG1~L(O37DJ^m4o6kTXKjD~=CEuiByLH9Hi&Zik{b>`?Tk9g5zvL($uID0;^ZMeo`a zy(dugzCh6j0!1GR6n!L6^szwECjv#E3KV@NQ1rP#(H8Mc)b( zeJ4=#y+F|q0!2Rx6#XPn^s`V?^kTch#0*Gz>jdYeQ1oH?*6c6sO37DJ^hdkm;b(=S zKOG;6{<1^S-*zba#|}mR+My^{jz{jHC~t?NHg+f~*rBM-rl=@TR4-6e5-4gbP}EMK zs4P&_AW+m^ps0gDQKLXnMWCoEP}C$))KQ?QlR(it0!5t#islt4nopo;eu1Jc0!0f5 zHATO*D_oNSDQ}VP7yTZJ)+%OW!E!12N{SXO7oR;R6m@lcDC%a1qQ&e`w74CLmas$7 zl6ELs$__P}EbPsFy%dvp`XAfucSFMSTT| z`Uw>E7bsd$plE~}b7ARUpplFal(W(MPs|htl3zrK&WkAZmrJJ8c%C$%O zucfhixs-e*MMKNQ&gX}sVU7<)!|hPCrX7k#*r8}GI~1*LhoW`tP_(Wciq^A3(fT$; z8weC_C{VPKK+#BnqKyTLHW4V=RG?@xfuhX?inb6a+ESosD}kb|1&X#2DB4z_Xgh(T zQ36HV3lxnODB3}wXpBJ7SfQq9jdEe73`jZsq@ubZq3H57#+6ISS5h>oT-^G?P_(1t zL(xulD4J}CqA7MLnrerlX?7@@Zik|s?NBts4n;FqJspA4i+dnM4;$Ufuh3%iVhcQ ziYAl``(;4N&!(H7iJ|C)bSLSEaw+*rijFB4&%Zbn9qaf|betWEj<-Y633ezt(GEo? z*`erUI~1K_hoV#MP;{D2(dhz3X9yIXDNuBlK+)L(Mdt_S~3j}Ap$ z(`-*49g6OP}EbPsFy%dvp`XAfucSFMSTT|`Uw>E7bsd$plE~}b7ARUp zplFal(W(MPs|ggXE>JXBplA)Drl@N};hhXf`StYO*lrEANBY;N+oB;2rQ|CqTC<_} z?{%SQgyTceT6QQ}+YUwR*r8}$I~1*FhobfEP_%&^iZ--E(MC2!BL#{!7AV?8plDNp zqRj+~HWw(`LZE0%fugMhinbOg+D4#gTY;kO1d2up6m2h1G+Ll&2Z5q70!3p5ipB{P zjTb1IAk-8MYbY#neWs{O`VPqOP;_MWvbu>4rQ|Cqn%qzvc4H`-;`mTB)ec3|>`*k_ z4n;fLp=gF3ie}oOXqFv{X4|1?7n`D81&VePDB4}1Xb*v+Jq3#P5-8eRplBa~qJ0I5 z_7f=DU!dp!fuaKiiVhMeI#{6S5P_mY1&R(6C^}rA=m>$LBL#|%5^9QeY$)uQ0V(gC zzKy?ADB3OEyFR+1lzb&c$2Sy@yg3w|;P_B z(Jc+d=Wh)~w>mx)-DZcP+wD+vhaHOUv_sKdb||{r4n_Caq3B*a6y0Z2biY8+0|G@4 z3KTsgQ1q}s(IWyyj|vn$CQ$UaK+zKdMNbM8Jta`|v_R1_0!7aX6g?+U^t?dP3j#$i z3KYF0Q1r4u(JMkt(M=77Uos%&{t3>_q3EJ?Tl8u}Dfvo@-fSq&cSk6C%kiP;Z95db zV~3)5?NIcd9g5z!L(vCzDEiP2MIYIr=wq9rPXvlS6)5^lpy+dfqAvuBz7#0>N}%X# zfue5&ioO*n`c9zedx4@K1d4tXDEdjD=x2eVUj&MN6)5^mpy+pjqCW(R{uFA8UT-L@ zk^w1ynx1uhBNT0&Nd47NO1_e!T>Ij-cZH&S`*pQ z7bxl?P_%$R(Sia+3kei0EKszFK+&QCMO}rOqJJ6+2V_9Xb?GtMzoDpi_OiNe?Mum5 zQnY0I;)VBwqNN-kik7xR(K2=@TGkFl%h{o5c{>!XV27gab|~s$hoYV~MZE-yngxn_ z3l#McDC#Rv)K8$Ozd+H70!0G^iUtZ4tt3#ivOv))0!4!aidGdUT1}v6b%CP60!3>G z6b%t58Y)mUOsFYZynW%Z3`qH%bX&AU``RP@KJBwHynQM8N{ZHQU;O;OP_&NYL(#f+ zC|b`BMeEz4XahSGZD@z0jqFe~(hfx%+o5O^o1#qxiZ&A{+FYP$3xT371&X#3DB4<} zXd8i|Z3T+96DS%bP_(^3(P)999R!NT2o#MKC>keFG+v-+fwti#;C=wN}O zLj;Nr6(~APpy+Ucq9X)~jua?5N}%XyfudssijEa(il($LY?1*fk4$%{r-q`jX&l$S zlzb&cC$%rmemE4J?D$Z0iXDnhwL{Tqb|^aC4n=3!q3BFI6rE*a&Qyite*R(fxKPdcY1v584zxBvACQK+z)tMUM&;Jtk1}xIobp z0!2>>6g?$S^t3?HGXh1=3KTsjQ1rY&(F+1aFA5aBBvACSK+!7#MXw4Jy(Uofx=>Se zYx}}`8Iba->E`FQP_#()vbs0gmy)lf=$-b({1c(*UB`!__v}#gz8#7_utU*@b}0JD z4n-f^q39Dk6n$!kqR(uKJ{KtZLZIkNfugSjioO;o`bMDWTY;kQ1d6^FDEdL5=tqH~ zp9G427AX2fpy*eDqTd9HeitbEL!jtSfug?zivAWT`bVfKdaHe5sSHT@@$^0Yw?ol} z>5=}w?Mum5QdH6m_sE zY7{7{2ozNXikbw9ItmnZ5-6HSps2Gz(Yyjh^9dBqFHqD)plAVsq6Gzt77{30SfFST zfucnPinK+!OPqTvEXYYG&N z5Ne8+>QJ~L15#c#!C5*KbxB{|*6L77zLKK#Iuu`gE)=cr_)xTg9f~%zL(xWdC>m*p zqK)lPw22*xHnl_1W_Bpr+@@#?fub!1inbCc+FGD!8-b#21&X#4C>kYDw7o#lXn~>~ z1d7H86pa-q8YfURUZ7}#K+!~jqDcZpI|>x-Bv3S2plFIvQ?yQp!fzRn^4aOOXx&hh zo+hfB+M$$uB}Fqj6uZ0_ie@@K6wR_j(QG>u?P7wWM2^1YKP;`P&Q#8FpVbu&sdH(dQ!bt{sZbvqRDOHboZ*6kRA#bdf;O#R5f_ z2ozl^P;{9<(d7a~R|phcDNuBkK+)9#Mb`)vT`N#@oj}p`0!23n6x}FLbdx~Q%>qTY z2o&8a)D)fEp>R+Jr2JZX*71~3^g(*0e_MxA@|6_b)uDLttD)#_$A_YO>`-*C9g6O= zL(%`?Tv9g04&L(!*pDEiC}MW5TD z=nFd(eQ8tll|a$g0!7~l6n!gD^qoM__X0&f2o(J&Q1p{P(a!=!zX%llDp2&BK+*34 zMSlns{V7oNmq5|q0!9A_6#XkulxvI!<`m_Hnxc0*6sm7ziXKY0Mel{8f6}*R+ccJv zucWBHvDo}pC@MKV6t%TOQ9C;nmF-Z}V27gib|~s#hoVM16jkg{RJAE;5-92@P}E7F zXdZ#0&H_dA3KY#JP&B_lQ5S)t1q6x~6ewCqplD%%qD2IX78NM!Dp1r-plC6HqQwP@ zmJldfQlMxlp{A&=v9MVNqT8Fhel|t@1&US_C>kJ8G*F;uC4r)q1&US?C>kVC zw5mYSY63;83lt3&C|X0HXox`3P=TUh0!70Giq;e;8X-`$mO#0MqAOlifG5x*k4MNeL>E89ujiux( zDVp6_EPNP>c5!?t+SLw4yV;>=cRLjAVTYnU?NGFr9g6n0L(x8VDB9PiXg`6X{RN5+ z5GXoOpy(ihqJssB4iP9iRG{cEfuh3&ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C*;{}RN z5GXoPpy(ulqLYQ1qM40_WilY;E7EPztWflOdf0zTV=4Jciq2>(uJv&!I@9r?=qx)F zoo$DrbL>!bt{sZbvqRDOb||{Q4n-H*q39x;qKgHJE)giYRG{cGfuhR=imnhSx>BI% zDuJS_1&Xc_D7sdl=sJO->jjE#5GcA)py(!nqMHSZZV@QDRiNlLfuh?5itZ3MW5QC=rcPMeQt-MFYHkCr5%dCvP03=b}0JBrs!LN zqVEKXz85I^L7?bIfuf%TihdR-`bD7VSAnA61d4taDEdR7=ud&7zXXc@7AX2hpy*$L zqFf~&wo{ZBC~6~6R1het6KaY+Xe|7Z0V%(f;CvX04oRenl~VGR6t$}q7yK#|l^q|7 z8thQi-VQ|_>`>HbhoXudimG-fYO+I7M>`aCvMHKJps2Gz(Yyjh^9dBqFHqD)plAVs zq6Gzt77{30SfFSTfucnPinI6paulT1%j4ZGob71d7%bC|XaTXnmokXoX7QkPJxqrSurBdnhUkeFG+v-+fTMJEarog`3nvOv)(0!60^6rCp26zx(e zbo?<>bYl8G+ODDKo?3W1_41&Xc`D7spp=o*2dYXyp~6DYb~py&pHq8kN@ zZW1WES)k|^fudUlif$7qx?P~?4uPUO1&ZzxD7ssyDLS)K*dhZ`?wf9l&I&~br!Q~! zR7%NLQuIKjxcjf6=t0MaqKE8I^spU@9hoYx!ik=oI zdPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9| zdPkt>U4f$a1d84lDEdICDY~yxI41*A-ZnifyFU~inx2CEuu@9ClA=#5#e07bMV~o7 z6n$=oqA%=F^ran&zOqBn*LEoS#tuc_+M(z>I~09yQ}lyC(T@T}KM555EKu}|K+&%P zMZXCY{Vq`Shd|Mv0!4ob6#Xqw^p8N%zXC9A%UWW1&S6CC|XpYsH;FxH-VzX z1d0|HC|W|GXi0&hr38wW7ARUqplDfvqU8jNmKP{mL8vJzR}0H!K*}Gs%iuIrYmfAw zPG8=-S4+uPQq){6uJcbQ>h1VY)W;4*eeF=x&kjZX?NGF$9f}6np=h8TidM2i(aJVO zs|XYg5-3_#plCILqSXb81`8CeAy70#plGN-(J+Cc;Q~c#3KWeHC|XOPXl;R_bp(pm z6)0LyplE%8q74L!HWVn@NT@05SuIS@fRsC=+oE2f=*BcgR!hlOQnXpMcziCsfnK?~ z%^e?#wy;CdmUbxG$__ul3dv|xIqziYLWd?iJDR*SE;2}OH3J{0Y3hoXJ#P_(ZdiuSWZ z(f)QQI=~J^2il?NAUhNtY*TcIK+&NBMTZF#9WGFGgh0`e0!2p&6df&4bc{gJu>wWM z2^1YKP;`Po(TM^@CkYgtEKqccK+&lJMW+cAoi0#xhCtDoLQT=`)xuvHkn&FHiN-xb z(Pinj=&Wif`AUk;s}>i|ejG&0ZPEFT4@DQ)q3A+86kTM8qKoZNbcr2`F116^Wp*gK z+zv%o*c4qUP;`|*(bWP)*9a6{D^PTuK+*LAMK=f(-6&9WlR(kU0!6n76x}LNbellY z?E*!22o&8ZP;{3-(cJJQ+6nN+73m}*rDiIo1*6gik=rJdO@J* zMS-H11d3i3D0)Sp=v9HD*93}Q7bto|py*A3qPGN!-WDi&N1*6kfui>WiryC}`aq!Q zLxG}?1d2WuYKk7L77ojRl>4RIqK87!_37UAC)HB&l@xtZEneO(6n*LVQ1q1@ioUi( z(KmJ|`qmCb-`Sz)dpi{UV27d~?NIcSP0`N+MZX9X{VGuOn?TX;0!4oa6#Xes^p`-< z-vUMd2o(J*P?T$mhwT*Q1&Z1T6cq%D>I9040!8%#MJ0ivwgN@%1d7T+P0?r7!ZR6= z^0aK$eIAO&r$_n?O{L^3DXKITzikLbRmX>-COZ^$v_nxRI~2`hhoa7QD4N#}Mf2IA zXns2sb+IX0K%i(rfue;3iWU|qT122|QGuea0!7^fiWUW`Wd(|s6DV37v_sKKb|_le4n?cjp=gjDidMBLT1}v6b%CP6 z0!3>G6b%t58Y)mUOrU7EK+&24MI!`?))FXMTcBtifueNkkHw6Q?ZCPGb7@20|58IbZ~=`mWLP}DEoyWX^^lzb&cTQ(KVIc!8o51d2`+C^|`?=wyMS zQv`}m6(~AQpy+ggqB8`F&J-v*OQ7g%fueJSnxeg$3ZG;^%B!cFpS?rT*=d~HR7$>* zq6?dfrOu(~BFBfKi|tT!i5-eAwL{Tmb||{s4n2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+py)1vqPqo(?hz=uSD@%V zfuj2biXIRsdQhk-I=`u~LI$L~X8POv7lfj((rwX0O{L^3DSE7_xZZrB=yAt~q9^Q7 z^rRh%p0Y#H({?C&#tuc#+M(z4>Rk-e<$^QKbrl@xv5R6MauDEh|nq3ByX6n$rhqVMfc^n)FWezZf; zPj)E!*$zd&*rDiGo1)(YihdU;`a_`TPl2Mp1d9F^DEddB=wE@NT*r9WPElTW`Wd(|s6DV3Mhh1RXY~`$$*qEPfrmwb*w$oKQY5o*QaAC`AUjb>{wiMkx(?i z@u6s-9g0@6L($51C|bo1MT6{6w5lD7RUJm^Y*Vy`K+zC^qM-ss!vu zP&7iIXf1)FwFQdS5hz+$plCgTqV)xeHV`PqgZ6Z*#sX){X@~B>9%N#j-}))DcYuEaa{HriCeypwyons(ROwy8fAx~?d?!B z+73lK*r8~Q9g4=plC;dqMZbaCJPiz5h$7}P&7@TXu3er z&H_a<1d3(~6wMMSnk`VYi$Kw?0!6zC6zwihw1+^^o&rUC2{lDqbu1i_0Vz*QfA4zh zP;^Q9^0s%!Qu37)?ccF@FAq3Ccs6dhrQ zq9bjJjuI$3TA=6{fudstijET~I$ogY1c9Ox1&U4*C^}i7=oEpXQw54n6DT@epy&*N zqB8}G&Jrj(TcGG1fueH-ip~=#I$x+M+P7ojxeQ48lWf-Q7mB`36zU%uU0ndkju?eIk}R{&0l%5DVJNQ z(runxu4`q&yt&*Gm8<8^<(8@ZxIiwqLS^8>xm>TxzKiB^eJc-l%jE`C8kWfAR;g^X zR4%uA<mC4$0+aRhAr{%k5U#X+$o!SLOP(bGiL0 zzpk6h9aI^#K`wV#<-m<{xuYtNZ=A~=SE+24%bir&bcw91)V<#K0L-rpvdJFl|z zs9f%%%9PQ$++~#;$K-NXRem3r%UxGlZDKBWQ{~_tbGh3pPfpI|?y59R%jNE?Y`$|Y z_fX~RnYr9!l@Dj@nZr&@Gd#&>4KDpdmmBIVxa_?0RJusL1 zsPgo|x!h-!PKV`kUsbj|BA5HFa_&*N+)tH{kIChJt1N$fF85b;=M%HbKVQA|sUp@cg?0U#o({Hn1 zB416vj(nMXHT^#674p^e3xRv(tLZno_RUw*ujCw%ucqIrxJtg7ektDS`D*&DW<&GU z^lPa`8D$d%~#Wp zC!UzErk^i6IbTgbAar`ZntsCLtb8^7h`!zO)$}vg_R3e&56RjuUrj&d=%9S{?)S25 zC|^xKXXL1SHT|H7`{P;Tm(J%p z9hbdIzF*_9DR;``c@gt*sj4sd6?}i!nZ(gVk$ep2lpXGufE^uXBFG`lgr8JM^8sI_Ed4 zZ~FY$&o1AybADv8{e~azwSMRP#>MtG&3jNjH_yoIn3>t@cdH$f@0FY9kw|^#q^^w|pD}65q*;@88JFuhaoUt|Jx5O-w_DF1lc$XtJ-O%1iKAzX z>p5fG)NwOM&+Iv__o$h(W{;gTt>>(1(Znb!k7dG!lV{HyHF9wO_4@s9Tur--o;5CATDe^9iXK0E>X=@A`}P=ZwfppOGkZ)-!m_Jt?4+r)vXR|1Z9HVysO)Tx88U6klxb75mZ<_}QhL+1 zl*?|wi!C|}ee%U(r~m1{V!pmGA$x^Fm#*~_iXH3oJ-aX7eT8DNzGtyhedl7wg`#pKj|BoL=^9tSmmp_bRF*^%uWgk@bVRWqT)N(1!xf1^0FN<{5bo-A>G2gAt zBH2yO$YE=a8s2L}E}b?H=rv;04z)k_?>py@{f5l>WB&p1ntcaogB{$fZ|!BnhQ#YM zXRkbI-D%UNH|N$Hyv3*?>u=J#_O^#Qq~DzPx1!Xi_5Jpq^L~fS^(NyC_I5!3Ij=Ra z#*uxUjlmICoO5=vi+9fZ zne#6DdXGa}FPiKEiC4@%fZBzcy_MP@<~lO-D z=VQp6BbtYJSJ@elBa(-?zP$Wz-KY*7x5MlSx$G;^)CuE8jhi}l(&(w9CQq9>q4oi0 zS5WruvzzX@uAw+WXcHF)UAmgBN3IzGq@ zbo^=Pe;k=hXQ^w;|NUR+np@Av8sQ4R>}qUz2fWP@Rr8xZ5r?%Ly<_^^X?fLN@g_3L zaZc8lbDq*CZObbSZas5DS?Ciln}fqUZyqq`O*Oar;{})IR*>085$_t3IUKUvhn6$Y z+^VZN<5g?Dys#Bq^Ke&9t25VD_CeH+^M`b`wA?nuRXgX?s<~IMmKS6%yq^0&(6sI=6%Pw>)Cpbq?Npz*X(+z zeemghr*oN|&bbyM5t7}M#f$pPxqh-s*{io2!-t+ZVg_Va&a^q77p+&gFFxr;D&Aan zj5nNNuU$XcyKVVHb}@U|oU@d@udJn8?M%nt?;s&r|h*_-gwK4GB|Nm_N6BNH0J}!P}h#nZlBW)<&4^; z(p)=^S;oV9s`x2hL{h1S|&6qXkt7azIxv1UF&AGnke0|S8BU@f2T_-I( zvrD7)hq(x}UggcL*Lid6mF^m8&dzMh!Py;vmQ$B_bN0zmd#iI@p{>_n_Riz7Y0mDl z)Lt?BO}h>mIIwGabkn1`YkGXsYe4V5 zU6+|LZt}R%Gsi94wfmGY(`OGFlU-utcI!T+PoFHznmBvP4%zAW$YhC~8kAiv zV^hdpbNuvO`gNZ2q_|q-j&T&&(dE zWT!K;Hg@!^(Q|g~qR8$Q)c(*)wz<`8;`l#(A*->R>x=Cidzsyqx7m7MF=~8_{MX-d^fva+Ik>J$9izbD;Gu zpDVca4&R(Bu6D06x8{%`D|KBaeZCByF{SIUDLafCJ2t!Ty@@9hT0Vt5L9p!q{0Wsk z@6kT{-@n;^+0!k1HD*r(rKeN;m!38m+&KS%^#>IXt~;b~Xq#j5xxoXomyS-)Lgey2 zvp*IGbYHK>dV|+mKUd#WTCZK9+_q!gJo(P~`3m#ryW|(hFPL8_zetW*Yf1aB{uKHgu@081)25k8# z)8*VTJHJcL^&085`~27bzn-aBVpeX6vH$&`=RfYNW!nGy-hB2?x3jlf?wHH1pH8!9 z+a8G1Kcc5grcL@bN;=Ix%=D3@)6Q|)C7os$N4IpEz0xw#lZW(r*>^%(PP6ZSw4AOH zryIuUrg54*_tNt69piN8INdi+4~o;{;`G8ey*_(JCB2`!M0MgE9 z&n~Ca`Ld5Coh}}y>3PGnhsEjE*`L#%5U1y5S7q8)$LS~81(5cSak@eVEA4@CIwSjb zQri2*>22AwmT5m6r~fQa+YJlWPKRdSY)UWRC{B-9w6;%;)911aHog4qIGuNi+Fm?P zw^^#TC&lRn*%gpp|JpeHY`NP0IZk_YukDrNbXImnrPtp-PVZ>0?MLG@*SEGi#Od(t z3Qe!Sahx7Cptets(-&5%?RVpJ{_KiRufJrRZns)(?-ZvO4X*9$ zgW`0T5w(3_oZhu|Z9g8TZPu&pN}P_^ptd)S(_=QO?K9)_rHyO*{Wx7Dm+j4`Y8F zCB?n4VY>`HO~W)EB}&{$fCzDS;_iXCCqUfY-QC^Y-QC^Y-Tl-r^<3ZD?|1$iu+%J@&2lcsY*TzuxQQc*248J~zkL4zBmdIZkm{y=TdB z(*S3INM>*aXT zS@k|Y$2ZQY_oq1yKEK|x<+%BU^&Xq!RTtO$_8fn>wBG;bIO2+WFPY;$SJnH-93Q%- z-p}XQb$z`j%5miz>%Bpar`%lc3v+zy)_Q-QGd#~Ov=h*kddQY0; z>L1s8RE}qSTJKA9eDCvmf1Ts>U)6hfj@y1y@7;5};k$a@o8xak)Vuj(eO&10`nY_K z2mM;_<8yqXdL_90|9dsZ{(seb@*LOvr{0_7cvkhSp}ha)Iet*RT3q(GInG$U>QMGv zId0#o_ntZ4RK1W~-hO|Me^jq1m))xVm9BDJq&u6M#J+0{0 zy>IpH66xKBjNN^^aid08$8lro>TYZsz^Bt;F{`>i;(WA#~wo83h%9!$uF(0T-|KDZX^3q~HMD<9z4cVl69c;7e zOaK4#%WOVo)OOW7ExPIoLq?4oH)gBRJCCbA?Ek+%s;5eo?&`JgoKQU#`9D9Zzg7SJ zn5z2U@_vnamZvWN=SO*4`7uNFSM|64|L6P7QN7Rq``6vr2dUmxey_@pS*yRQr<2_l zss1WIE?Tgo+u-V0e(%crl)uWaw@mfd|D0ZZr%3g@tMcH7pDj^^|NVFmRUdEdDwK~` z{vP;vt5-jFPW97n6U@|6eSb^&S^dLLtEU$K=lyn?xqf{A@An&Bh5!9^CtJGXKcD5- zE#0rXd-Zc4yZULjgQxk8ytW@eVF;%nxrn zwA%ms@fN5)Uitf49$)p3+W+(MPOW}k&MCit<;V21cXV5*cm4D7zvXS^uM2YYew)tU z(QUb^`QiPptwQ;^AJ|L@~l;(z}C4#@kJ$9q@xS7mg^>hRx>_o|OK zpHUtCTII-gdGllobX4E)RNs5~c>Swheof}f`>kJjS*rXbKYYA$&i}sO>eb_W$~#p@ z@Atnif{z%o!|c_|3UiN`W7vpc!v|MiKbT|a|NQUVbI&<=@Q68w&NFOq`LS`=zDtf= zs{SsD`U7`VcZ5D}DIYEI-)heJ-%Sn_J8G9Qn|1ol`yZ+k11o^jqi9 zZnOOPMz<~h{q>)JANs9Z_1#w0quZ}r{|OiAIYUSOes^{>s{iA?KdC;@x&QljsoLE; zdXzr}sC!4xeY&bc_vUY{a%k;Z#m3m`0d!ws;uXsKbv6f9zafpI%6qLeXygA<>$mE| zcJJAoy!uD2d(YPC)!(ts&Sv?tQ1{N(^VPdFCaB)MG3$7XmY+{py}2>R_~jqP=CS4c zjvhBuzgUmXGFqLT(>JfK9$e4zXP?cGf1hQ_Y7XtzIb-G&)g0EXbEeG6t2w;-^Y$|* ztLB{DI%mn8w3>5u>zp-nl4{Of{gHi{gQ_`Cx6UD%6IXLYx6au!C#vSW)xY(hIbk)2 zRu5}v_5@{Dk84==_+?iQY;Yw0k8SSk{$*DWZl3IZWmk`G zM0Ve@tA{slcAv7V$2VVg?`jXL9^d@g?Xs)Kw?KAR+12A)FuPaT)#FNr>p;sj1?;%olCc_uHK;tS-$yfbpiQL$jF=;AuD7? z$cmW}vQlP*tehDkt7JyVs+ke8T4sc-o*5x)WD>GwHX&tz$N zel{T+WD~MsHX$2j6S8qOA)~Sh8J$hYCfS5+noY=N*@SGKO~@A6glw5j$X3~eY@JQW zHrch1WgFjDzyDp=SC^a4%S5 zWarEX*(EbVcFl~C-7+I&_sj^{Ba@IlvkBQNn~=S;3E3x`kbScW*)N-r{j&)XOkldG%?hbB9{U$nsg~_*Riqgq++Qull6*pO8~>YJ{Ac86l@-M#$-z5pqUmgq)cf zA!lVq$k~|@a!zK1oSR9=dD(=VpH0XG*@Rq}O~^&rgj}3W$R*i?T$)YDW!Z#Wo=wOV z*@Rq~O~_T*gj}6X$Tiu7T$@eEb=ibmpH0XO*@WDfO~_5zgxs863puedSM~efby&HE zoKy?>sr>wwR*_SL+|ew57TJG7?#!tXa#v=A+?^RA_hd%My_pemUuJ~dpBW(!WJbt? znGy0(CLs@J6Y@wlA&+Jg@>n(@k7pC|L^dH$W)t#MHX%=E6Y@+pA(__uV)kTMs_Xaw#Hi3?|)bMl0)b1wUFz|HRR1! zkyC`c+gz)BXE%n11`GeSPkB;<>1 zLcYu<~=kpKL<@&8~&K-Poi0{qK6XJok9#KOyZe$~B~V>8#M{*1NN_ zv!i)tzv^DQ+|4vQa`u$fuAcVxu&1bY^|ZWYPhRcnX?ah3vT9dP%X`_AR=avy-epfx z?doZH+a6Ty>S=jzd*W(WPs{t*6IHu5u-fImrk^lD3DqO)FN|M8^$-ULF|o-m+<>QRm_^e>@$m=g&7N~j*^ghJmEss}oe(5Hmzkxnf1u0pxP86>nz zs2=GgLRSgZBb`*}RYLVhClh*>P(9Mgg;ojGBb`F%Q9|`drxcncRF8D9&{;zDNT(92 z7qtJo)tOr8UWIb6GmX$uLiI?e6)GToJ3G5~H14Z_w5KeWmPSXd==1WtWx9@5;Z+pP z)X{vu`clMyie`3x6wP8s(X4h9&1Of@5Ic%yx1(qdJBo(dQ8dhsqTx10a|#sAB~UcC zK+!w`MI!`?<`pQKPoQXifuaQjiWU?oT1cR1VS%DW1d0|FC|XRQXmNp}B?O9=6ewCs zplE4kdhUyD{|0!C@`BAj8 z9Yw3yQM9TZMXT9Sw7MNdYuHh=rX59V*-^B%P0>06Me7O_ttU{lzCh6i0!14N6m29> zw6Q?ZD1oBU0!5n$6m2R{w3$HB<^n}q2o!B8P_&gm(bfV*+XxhGD^RqZK+*O>t!QLN zV`K%SeN#0%SBRon3#lDCTE$mUG`6F;-Gosz&iPTavmHgd*ip2r9Ywp@QM9`qMSIv$ zw5J_Kd)ZO6w@uML0!8}@6zwNaw7)>n0Rlw_3KShAP;{_B(IEmwhYA!OCQx*^K+zEb zMMnx09VJk7v_R1@0!7CP6dfl}bi6>(2?9kY3bmr0IvOWbK-z~^ciNp}qUh59?z1{t z#aB^uT1WH7>IJ(0u0^LiKZ?$lg*I)S3=1&VGED7sOg z=q7=pn+1w)5h%JQS`7KMUU7~^r%hIV**8w3lu#eQ1qlg(Nh9NPYV=1 zBT)3LK+$soMb8Tqy&zEZqCnA00!1$i6ulx)^r}G7YXU{D3lzN}Q1qri(OUvVZws}e zJ3AUvRIi1%w=UPByQ1jb^6dJZj#lwi6n)UqT)6sP!vC&CA38sZKC+|eV>^mIv7_iy zJBmKDqv&%xioUR;=u10_zOpI$TA=6~fue5(ioO#l`d*;u2Z5p=1&V$WDEe8T=of*a zUj>SO6Day!py&^QqCW+S{t_tqTcGG4fuer}in?|Gf9~?@d$bOLqV7Vi=)I1{rWKI( zE9JXQ-jAa9%C)G`y;Xb_MXm15gQtw5p3aY=UUn39*-_NCqo}tXMSbij>T5?)KRb&0 z+fg*Yrf8r*(Rczy;|ml`AW$@+K+!}3MH34Y4H77tM4)I=fuhL-iY6B*nnIvxN`a!m z0!32^6iqEqG>t&fv;sxb39d!c3lz;D)QYM<*y4%`NPExn1;rlS>pT6I%e836?ycgh zD4Ml<^U0~AXg23Z(GWX|X1Akg4m*m5+EFyjj-ugq6wPTz(Oh;E&23XOk3i7~fueZ@ zisln2nqQ!30fC|g1&S6DC|X#cXc2*;MFol$6DV3-plAt!q9p~2mJ%phTA*kdfudyv zik1^7T3(=Nq);oGxqIWg3P^kE>br9~XNjWitCu}HSLog+=3tsF(8%4f7O-CM<1QM60<=33K7(XP&qqTTE$+TD(#J?tpj(~hFO>?qpX zj-q|+DB9PKqWx@&_7^BRK%nSAfue&1iVhYiIz*u8P=TVu1d0w9C^|x*=tzO0qXdeM z7AQJKpy*hEqT>XLju$98L7?bFfufTHicS_NIz^}zjqBdns{+!VyL^dg=O~(?eAV&P z?ycghC_1xy^XwU;=q%?)(b;wsonuGQxpowtXGhWbb`)J;N703L6kTLT(Zx1Jmk1PH zDo}KpK+)v_MOO$ET`5p>l|a$e0!7yd6kRJ&be%xa^#VmV2o&8YP;`?((ai!yw+Iy7 zDo}KrK+)|2MRy1k-6_JBl8$qv%mPiXOA0=y5xWp0Fu;QlRK5fug4cik=ZDdRCz5If0_* z1&Uq}D0)$#=p})omj#Mm5h!|9py)M$qSpnA-Vi8yQ=sTAfugqsirx_@dRL(6J)u@~ zPxnU8St><8mplD?qiDJE?E3xgt>UXF`nY>@rrDzC6X!?Kr*;&5W=GNIb`*VKN70vd z6n$k!(bskqePc(_w>CxJ2^4)VQ1pX9(T@T}KM555EKu}|K+&%PMZXCY{Vq`Shd|Mv z0!4ob6#Xqw^p8N%zXCv-5V=b zK-zbgYtcthv|f33-J{VezKWu*MstVRqp0otDC%uTQ6D>s`r1*{&yJ%0b`%Y;qiCQV zMdR5~G`>yI1Oi193KUHwP&BbX(IA1MNd$@}6)2iaplEV|qA3K5rW7a|EKoF+K+)6! zMbiirO)F3|oj}p_0!1?j6wN45G?PHl%tEcGXQOda1*H9Ac`DSaQQzr5S*}I1G+M=1 zQ8as_dGpXHn#1`~G}MlwVRjS^x1(rIJBsGAqiAkBisrGSXoMX_^V$^6Cr~uMK+ysM zMGFcPEhJF1ut3ow0!51o6fGuDw75Xg5&}g_3KT6RP_(o_(J}%>%L)`NCs4G!K+#Bn zq7?*+Rum{&NvIXg)@Zy@0cr17o(c_#qE*VZXyrz$_$rE4Z#4fL9z|<7KZ@40qi8KV ziq^KHXdOF>*0rN(Jv)llx1(qSJBl{6DcVS&Xk&q*Q36Gy1&THiDB4t@XfuJL%>|0K z5GdMGplB!E;uM zzN@}xv2(R3dZ&CLd*?>0_$rEaZ!{O3JBs#jeiZF#N6}t(6zy$C(LQz*?Q2KTes&b? zZ%5Gqb`%|GQ*@9((ZK>mhX@oMDo}KoK+)j>MMnq}9Vt+Blt9tZ0!7CN6dfy2beurZ z@d8CB2o#+tP;`<&(a8curwA0CDo}KqK+)+!t!URqWAh3~d!=$M+AWF}DWB2KXtav2 zqUfAP^Ux7dbguKG=sY`$&bOoJ0y~N>w4>-EJBlv0qv#SliY~RI=rWt4%LR(A5GcA* zpy(=rqN@dpt`R7@R-ouQfuidLif#}nx>2C$CV`@x1&VGFD7sak=r)0(+Xag55GcA+ zpy)1vqPqo(?h$H5XEhpERY2Nv7DZ=A(E?@M+h`SEMbU$e=F`=`+WFtBu@5;viXOJ3 z=n*@L9<`(BF*}MLx1;C@JBpsPqv$C+ik`M9dPbn=S%ISG1d5&)D0)Gl=tY5|mjsGl z7ASf}py*YBqSpk9UKc2OL!jtQfugqriry9|dPkt>U4f$a1d84lDEdI4=tH4abbq7q zLj|OLMER=Y15q@jT#G(xw2H5y=(9$1yal7^bLU6V7j_hVX-Cmlb`*VWN6|NS6n$$) z(RX$feQ!t64>m!R)M0~gj!L%v$0PFq`h*v7WM9|@ARK4&#s4bwu-N!Xjo_S+(n~kxbvfE zPCJU`vZH8jJBsG9qiBR3Mf2KGG@l(s^V?ChfKAbY0!0f66fG=Jw1_~_q5?&W2^1|Z zP_%?V(UJm1O9>P$El{+KK+&=SMau~kEiX_sQlMxBfua=!idGURT3MiI6@j8vg<8=Z zosEYoAngOI**P?dmM#~j)jC_nS5dT9XY=F5qiAjCN6|WV6s>DV(Ry|it#3!s26hx} zXh+dTb`))FN6{#oqR|3Hn+OzbDp0hUK+)y`MOz3IZ7EQ+l|a$f0!7;h6m2U|w4FfF z_5wva2o&uoP_&ak(HMcEu>wWo1d4VRDB4A!Xjh?Dv_@y6Yl%wH=<*84no;yXxfbo# z*($z@qP;qsvn&-wdpkdh_OYXAUptESv!iH#JBkjlqv$|8iVm`)=wLgF4zVdZRG{cE zfuh3&ijEK{I#QtMD1oA*1&WRlC^}Z4=s1C*;{}RN5GXoPpy(ulqLT%RP7x?NRiNlJ zfuhp|ip~%yI#ZzNETLAkM`vT@3P^iU`M&Etqv+f6Z6arPwu-N!=={#+PRm5m1=y;7J;H$1&VGHD7sys=njFRI|YjF5-7S`py(cfqI(63?h`1wU#JzG z+u1m!0@9wpT#L?&qPNPk>jyep#aB`ENN4lb<)Y|O=SR_Fb`(8sN6`~@6g_E2(NlI5 zJ#9zPGjA33lx1K)QTSJY`j$gX`fp@i9H-e=aoDC zPdi)1S5fq3XY=ooQS_Dbqv&fpioUU<=vzCAzO$p~dpnALu%qZlJBog?qv&UwqF)4x zeibPCO`zy^fucVIivAQR`b(hbZ-JtJ1d9F@DC*YCZ97FB0!7^giW&k%odQKofubG) zMJ<7%o&rU^1d6%@irPZ0==09T)GJhqPAi|$zKEjV%V)IS%~tVM6!mX57hfrg1~@;8 z2HH_Ho*hNw+fg)u9Yqt`Q8bYqMHAamG{}ykNo6*#(N`5Nbtz zn~g0iAnpF;`>y*n>pT4w%Y|uZvsHW*MRPTqhp!Svb2~qZ=CPw_gdIim+EFy09Yyoo zQM7;^MGM+dw2&P|3)>VeB2cubK+$3XMT-j*Eg?{}q(IS90!2#;6fGlAw5&kUasoxm z3lxnMC|W_FXhngdl>~}b7ARUpplDTrqSXY7Ru?E*L#P!EZ#J%}fV5{Tm!CPK=!!Dd zY_^K8qG;V_^V!v+Xg%jg(fW22ZD2>yhISNfWJl4)b`*`WqiD1pMVr`Bw5d(eW&%Z< z3lwc3P_(5$(N+RQTMHCzBT%%hK+$#rMcWG$?I2LJqd?J40!3p4ipB~QjT0!^S)gba zfudanigpty+FhV%5204HcC+zQ1*CmNc`CF{6x~*?MSC_|#aB_ZZ?ieUno+c$^P^~g zJBkjlqv$|8iVm`)=wLgF4zZ)?P&fub`6ip~@$I!mDFY=NS41d7fTYDIfD z8}n5_+BcWmvVEfHt#U0ouh}ZTilU2}&GpufqKlm$MVHu7bg3Ohm)TKtxgAAU*im$) z9Yt5!QFOH(Mc3FAT`N#@oj}p`0!23n6x}FLbdx~Q%>qTY2o&8aP;{F>(d`07cL)^S zDNuBmK+)X-MfV64-78RZpFq+50!0r96g?i;;Sh7rrG>-{V4j@`BC(p z9Yx>UQS^fyML*h6^phP$Kig6CiycM3+EMhIP0{ZHMSlns{V7oNmq5|q0!9A_6#Xku z)U8Ku+bQZ0DC#ay)DS4@6ewy66!j1&Y6%qe6e#K?P}C(*)D|e}El|`)ps24JXwK+#ZvqG19>!-ZPWfF6xiDb zx$U2`N2~ZMibnKkjvW<6^Ey9@=Ch+{emja5u%l=}JBk*vqiA6}iWae>Xi+6T3VoJ8G)i@1&WpvC|X{iXrw^V3Iatd3KXp*P_(i@(JBH(s|pmY zCQ!7xK+zfkMQaKattC*jwoogYyGP@+3P}5-^1NuCD4M2>b$YalucBy!9?jb~iJ}di zA4MD4QM9ogMWgH}8f{0>CUz8UYDdv#b`))HN6{8GMOz9KZ6#2&wLsA}0!7;j6m2I^ zw7o#l4gy6x3KZ=mP&7uMXskfdIDw*_1&VeNDB4w^Xg7hP-35yF5GdMHplC0FqP>M$ z(Rw`^?^HnAmzVD^T0e@8DWB2y>Cq~_ilPI0H2>W!iVk#s6dhzo(ZO~U9b!k(p>`A< zW=GNCb`%|9N70dX6dh$#bhJRxF#<)$3KShDP;|UN(Fp=YCkhmuBv5p+K+!1zMW+fB zohDFpx?pe0j-qSqD7w~;qU-D^y56Sf z27#g*1&VGGD7smo=oW#ZTLp@46DYb}py&>PqB{kO?h+`vTcGG3fuef_itZCAx?iB^ z0fC|i1&SULD0*0+=n;XUM}=C^#XTBZS3ufb=na9QHwB8` z5-56Gpy(ZeqIU&~-V-Q#U!dp%fuauuiaru3`dFao6M>>n1&TfsDEeHW=nH|OF9nLe z5^6?dIfui05MSTQ{`U({F6DaC0P&7cO6@A;I@k<4y{bsrRd>2Li z%V)HKtyb|>6iwJ_PP9W5P2~J2n%It_L3R{PVn@-Wb`(u!N73YV6is1A(Uf)+4Ynzo zN}y8O_7LYs(V=z}9cD+-;dT@qVMo!Cb`%|DN72!C6dhwn z(Xlo~#|ac2FHm%XK+%Z;MJEXqoh(pvia^n+0!60@6rCHH|V%8sI|?I^m&j-qSrD7wy$qU-G_y1|a38|^5%$)@OLfudUkif$Dsx=oucGMLR&(b)qUbs2N73_k6un?a(TjEz zy<|tx%XSpKVn@-db`-s4N73sxMQ;ccy(v)imO#N(Z>Qsp9mCvDp2&9K+)#{MPCRMeJN1%l|a$g0!7~l6n!hyik@yY&ZvO2pDc== ziK6SvwdlK6tN1F4erh%E+$)NHc77E7Vn@-hb`K+*U@t>}kVqqW*|BdF zP2&70n$(V>$?Pba+>W9t>?oSjj-tVK6isDE(bRSnO=D9utw7Oq0!7mc6wM$|G^0S# zOaetS3lz;FP&BJR(QE=mLj;Ou7bu!TplGN-(J+Cc;Q~c-3KY#HP&Btd(L4f0BLs@( z6>3Ej^=wRE0cl@XUICf7XMLwXtb9hBuV<_HDvB2B*<5=6C|cP0QM8C1MT^=|w3r=5 zi`!AOgdIgo+EKKW9YssqQM8Or(Xs+X%Lx=MFHkg6plAhwq7?;-RuU*$S)gbYfudCf zidGXST3w)M4S}LH1&Y=ZC|X;fXdQu~bp?vn6DV3=plAbuq78*w(E>di+g3o@YZo{R zM$tFrTC`EmR`FF7ZPK%O^np>dsq>>~Gdqelx1(qaJBqfnqi8ETing|+Xd63Z zJDZ~I1&VeMDB4k=XeWW9F#<(n1&YQA6zwcfw2MH|t^!572^8%vP_&0Y(VhZDdkGZn zEl{+NK+(PeMf(X9?JrPtfI!iKLak_2&&CZEkoG_2tB#|iXvRY7pq{Pbt0+3GXY<8_ zqv&wwN6`^>6dh?t(NT639c@R^F?JLkYe&&>b`%|NN6`s3MJEarog`3nvOv)(0!60^ z6rCnebh<#%83ILT3KX3sP;|CH(K!M|=L!^^Cs1_0K+y#PMHdPbT_jL+u|Ux!0!5b! z6kR6NiVo@7_^krc9#sCAkVB(rP<}9Ywd;QFNSFC2| zRZ+B8`Hc2V&sOnO6ur>1xzQ0(^rG{l=p{RfUbds?6+4PvwWH`YJBnVnqv#Dgir%!N z=q;O~w*`vc5h!|Bpy)k;qW1-gJ`gDSP@w1|fufHEiarr2`c$CkGl8Pd1&Y29DEd;M z=qrJuuLX*}5h(grpy)e+qVENYeh_L!&-H8^Q~{|jJ{6qjqo`+js{LcnR`FF7{o1p6 z@ljFqoAaaScRPyyu%qZtJBt3Yqv&rtivF>q=wCaEy7kI^dlYrp6m=IUY6ui{3KTU3 zih2kXwFHWK3KaDcDC!a@Y6}$g7AWc?P}EnTsGmSle}SR_0!0G_ipCQt8egDj0)e6l z1&SsTYDGWyY&=l`X}?)6KfgrLm@+2r)hfP!R)M0~1d4_T6wNMBG>1UZ zP=TUh0!70Gislq3noFQ)Zh@kC1d2uo6wND8G@n4x`~pP_2(_X~dNukVTPZrOM+Iln zUiF>+LuD-3t5tjzMT_=o4n01K7IS_SEpA8A5_S|VX-Cmgb`&jbN6|8N6fJ8<(Q+5-3_*plBU|qICs| z))OdNU!Z6MfuaosiZ&7`+E}1ylu#>LxL0G%3P}6Ga`{;#iu#pj*Q0y2im#$*^Ipwe zPmH21oF7G7+EKKX9YtH)QM8R6Mcdj@w4EJA+uKpJgB?XX+7#_1P&7uMXskfdIDw*_ z1&VeNDB4w^Xg7hP-35yF5GdMHplC0FqP+!*_7N!BSDVeM)hfPdCl_0Er?8|)~$(T<{<>?pd~j-p%aD7w{-qTB2!y4{YV zJ8X*X6ezk&py+OaqI(32?iDDyPoU_2fuaWliXIdwdPtz?VS%DY1d1LND0)nw=y8Ff zCj^R~6exO1py+9VqGtq(o)sv1PN)@K)2lIK1*Cmm`9kBhQ8Z(@M|-|ktN1F4UhdUg z_KYZc#raY6svSkI*-`Ym9Yt^0QS_!AMQ_A33lx1KQ1q!l(Psihp9>UyAyD+CK+#tMMPCaPeIroxtw7Ot0!7~o6#XDj^rJx0 zPXa|h3$>ybdo{MNfV6Ka-=+3a6g}Uw8o%^v6<&OM4c>?rDPM^VF$qE4Hlra(~-fufc`QBQ%QUIIm30!3|sqTT{UeFTd7 z3KaDdDC#dzG(ezepg_@h0!8Bs6ipydG@(GzL;^(<3lt3!D4Im575&z$aZ?4Py;ON# z^m`PYRIWvncD0JHqG-yl=F8_q(O~CC(NuO6O>IZfGM$nTE$mUv_w~P z((|KeN#{q=Qg#$AZAZ~Eb`&jZN6~V26fJK@(MUUrR+CZRaLxG}=1d28mC>kYDG+Ll& z6M>>lg<8>KU5!O5Ano!e6?HBiMVFVcSy!w0DvGx1YL2=vinexs6m4Ti(YAIJZD&W( z_I4EQU`Nr8b`@qyo~uyIg*@ zjH1cQXS5@_TE$mUbWB(C(uS{by0ckH?zR-Ad6zyH^^snt|6<9ciK^OmmNiS+Z5d+P;{?A(R~6%_X`v~ zAW-z6K+!`2MGp%UJt9!_s6f$U0!5Dt6g?qO^rS%1QvyX#3lu#gQ1q-o(Q^Vt&kGd2 zAW-z8P%FB=t1uL_aB8pyjeiXf7N70*h6uo6f z(c5+uy<~4m#@ZE-_NW5q z)hODie0ux6t5tjzMSpiScfTr%{&9X3{cA^2w|4H_qo~7wRhPSI`^Uq#W>?dHAL zMA0v zMe7R`Z6Hvzp+M0_0!14O6pa!n8ZA(?i9pe&0!5n%6m2e0w1rSBTC&}kxdPH|l~+KP zilQT{w{>pWZWUie(YEd8@;64&cFvEY?d>Sq!H%LG?I_yGj-oMk6pgi`Xq+8IJKIsT zi%rq40!6zC6zwihw1+^^o&rUC2^8%uP_&Og(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3E zh(OVy0!4=j6df*5bc8_Bkpe|W3ALiF+l?J7AnlFH%lO+w(evfykfYnJ;;Se+zTG_j z<|sPB`B8MD9YrVEQFO8$MW@(NbgCUir`b_-x*bJl*im$*P0?8bMP~~Xog+|mu0YXw z0!8Nw6kQ-tbfG}eMFK?^3lv=g6-q4eeI(RTSOQZoYbJ6y56lD7wv#qTB5#y2Fm5 zJMAdC%Z{SE?I^m(j-q?*D7w$4=zf8s2Ly^96exN~py*+NqDKUZ9u+8hOrYp-fubh_ zik=iGdP<<^X@R0=1d5&&D0)ty=y`#n7X*r46exO0py*|RqF01k(M|2fUlow{v<1%1 zQS^7Y7QNbT6<bCbKG zsH1o8khGG@d}w_yR=}2oy~yP&AQ1(Zm8pg9M5u5h$8eplC9IqR9n{rVuEaQlMzC zP%HYU-8ifQ(jHa5WA@)D8dklnbE@90;;Sf{u6OhDd!lH1=SR^Db`;HMN6}1n6wPc$ z(JXcp&1y%{Y<3h4v7=~qo1!@ciiQdl4HGCDE>JY5K+#+RMRN-j%_C4WLZE0~fui{Y zislz6T0o#^L4l%$1d0|GC|X3IXi?m5%j-r+9C|cQ$qE+lDTGfuC)$Ax* z-KJ;_fuc19iq;Y+T3euK9f6{C1&Y=aC|X~jXaj+w4F!re5-8eOplFmp(P)99O$3TI z6)4(FplEY}qAdi9wiGDZN}yYdkYlp zBT%%jK+%2zMf(dB9UxG2pg_?<0!0T46dfW^bf`elVFE>m3ltq8P;{g~(NO|LM++1k zBT#g#P%GN5cVpcONc+n2gnIiZy1R_ydbf(NqUfaF%{?EEqLZB;MW@(NbgCUir`b_- zx*bJl*im$*9Ytr^QFOK)Md#QQohwjuo95jaDEisX-Cmrb`;%hN6|fY6y0k_(S3Fl-ET+H19lWW zXjAl%K+(ejMUMy+Jt|Q2m_X6v0!2><6g??W^prr+(*i}$2oyalQ1qNY(enaDF9;O9 zC{Xm0K+($rMXv}Hy(&=jnn2O(Lapf5-i=QxAnjAj<>$62nxcAJ=Nr9S#aB`EPW9ij zejfUJK+zWhMPCXOeI-!z zwLsA~0!7~n6n!U9^u0jQ4+2F$3Kab$Q1r7v(Jul;zX}xnCQ$UdK+zupMSltu{UuQJ zw?NT9Lapen-i=u+AnozXR~_GuqJ_$x{=dCj#aB_(=+j)`sVM5~^MCL3n|2iSu%oDD zM^R5Zih9{m)MZCe+m52%b`sH0C~Oa-KUQ-RaH zPkoOzUiG%lY5TN_ucBziKFt%KiK3aDpKH;~b`;HGN71Zy6wPKw(GWX|X1Akg4m*m5 z+EFyjrf9f8(VPNBa|sm9El@O%K+y<+qIm_1<`XEIU!Z6KfuaQkiWU+mT3DcH5rLvb z1&S6EC|X>gXbFL$B?XF>5-3_)plBJPRy2K|#%&dl_DluN3{fqVc0#Ra`96(*Dj@A6%e81^6qPR%b#C9MReTjiWBN3wd@+i~IzNiW*-^B!9Ywp? zQM9WaMZ4Kiw7VTed)QI5ryWIm*%a+9P_&Og(Y^vj`w0~7FHm%VK+%B$MF$BK9V}3E zh(OVy0!4=j6df*5bc8_Bkpe|W2^1YIP;`ty(Xj$W#|ac2FHm%XP%GN8Ph*J+NV`Y* zs^d;kbY8g@o!F;Ud=*8f_GxbRaul8B{3trzj-oT{C_2-QqO?k_lrsx8Jq6-CzE)poZSfJ<3W1_41&Xc`D7spp=o*2dYXyp~ z6DYb~py&pHq8kN@ZW1WES)k|^fudW5TG7dU8b?$>+H;lfbvz}Co-23yxAkciUq#Vf zeVSLk8bxJBl8$DSA|(=rMt!#|4U> z5GZ<5py(-qqNfFlo)IW|R-ouPfuiRHie3;XdQqV0C4r)s1&Uq~D0)?(=rw_&*9D5+ z5GZ<6py(~3R&+<7#&Z>r_VDt3*LOzIpXI{zcAr-9RTRD7r}_QsQS^cHqv%6BiaxTV z=wmyIKCz?dQ#*=2v!m#9JBq%rqv%VUqOSysz7{C@Mxf|hfuipOioO>p`az)RM}eZB z1d4tZDEdX9=vRTF-vo+&7byBepy*G5qQ3-+{uU_uN1*6mfue4Gb7M|Xhfphew@+ij zH!4L_m21&^QM6Y1jMlwxtN1F4dh~71^HvnKoF7F!?I`MHM^Tp@MQuBZdfQRd$Bv@D zb`fdWP22^5VlP&9!+(S!m;6A2VeEKoE^plA|-qDcjcCKD){T%c$Q zfubn|iUtc5O(jq?wLsA{0!7mb6ip{kG`&zO>g?NCzXH;pq`+zRt?%@!XWG>bTi;gk zRTRzAx4HK_Q8cUbqi8leiiX%xG`k%|bJ$Td)Q+NIb`%Y_qi9Y$isrH@np>b~9)Y3} z0!8x*6wN14G`~R60s=(~3KT6QP_(c>(INsxiwYDiCQ!7vK+zHcMN0}4EhSL2v_R1^ z0!7OT6fGxEw7gI&nyGK&f(l6cnetV~nWJcAAvLmZtN1F4R_@z;@VzKn#raXRsvSkE z*-^B*9Yt%{QM9HVMQhnnw6+~Z>)27Wu1(Q;0!8Z!6m1|-w4p%JMgm0}3lxnKC>kwL zw245`rUFHq2^4KEP_%_W(Ut;5TL~0xEl{+LK+(1WMcWA!Z7)!?gFw-aLak`UzKzc+ zAnobO_g$|PMO&3;*E{uX6<?pd>j-rcfiY^u?x!ba&sz z9TkxFag7SjJyEn~8SnLN6<N z=r4hyzXgi^5h(gspr~8F+_qEHAyCv^pr|2G)G5@8KIq%%_C=*=Xo2%#6n$7mvtO(D zDvEmbYfkl56m>a2irRJ*^|qs^j~zvQ?I`MJM^S$}iU!zGG|-Ns@ob957bu!QplCvY zqKO2GCKf0fBv3SoK+&WEMUx2>O)gM0g+S4i0!4!bil!1Mnp&V}8iAr|1&XEO1{*Q8aVER`FF74e8h1;+rU%-T6^8haE*j z?I;>%N6~OQisrPVXf8X7=C-3~9y^Lg*c8nxP&A)F(fk5M3kVb~C{VPJK+(biMT-a& zEhC|ce5QM85~MQhqow3Z!3Yuiz@jvYno+EKKg z9YyQgQM7?g(S`y=8wnI`EKoE`plGx}(Ix^#n+gcB|?I^m)j-re0D7wUsqDyUxE)yuaT%hO*fubt~imnnUx>}&<8iAr~ z1&Xc{D7s#t=mvqJ8wHAP5-7S^py(EXqFV)uZWAcFU7+X=fucJFitZ99x?89fo!PIk zVFjdpe7P2#6-8sqXS93zwTiEz=z)ICeSeLj2b~{957|-lupLE@*irPT9Yv4XQS`VS zMNimK^rRg{PuUbbEl~7~K+&@TMb8NoJugu7fDuV3S$3P}5o@`U>SDB8JPi$3hv zD!z)MPy00={ymC5bAA+kZb#7kkHw1PmUXFTC;!i)NbVi%+alLE$2tk+IAGJV@J`tb`-5=N74Fr6m4Kf(S~*uZDdE$#x_Nx z1d2ur6m23bH_$rF_?B9I5dlc>E z{3zPnj-q|+DB9PKqW$bB+TV_%1MDa|(2k;m>?k_ersxoXqC*9W4ihLkT%hO(fubV? zijEQ}I$EIU7=fZ=1&WRnC^}xC=mdeH69tM+5-2)Zpy(8VqEiKmP7^3PU7+X;fub{o zTG8(P8{Hd~qS57R*Ly_KkL6l)R{vJ#tU1Uem#dZ{3 zVn@-Xb`)J^N73bW6kTCcbfrMiRRTp<3lv==P;{+8(RBhv*9#QgAW(FpK+#PCMK=o+ z-6BwQt3c6h0!6nA6x|_Ebf-YkT>?dS3l!ZWP;{?A(S1U#=$!tIWhx-;1Iy*-+$g%e z+@sy!zg2t{MGyCHZqorr+fnp{9Ys&tQS_7@MNivN^o$)v&)O6{ zCs6dfK+y{VMK1~zy(CcdvOv)*0!6P16ul-;^twRN8v;dd3KYF1Q1rGy(K`Y~?+O&X zCs6dhK+y*RMIQ#_^sOC5-`P?0y&XkA*irPO9YsIc6#Xnv^ou~zuL4EC2^9S=<04X~qVpdCfy*-5h$8eplC9IqR9n{rVuEaQlMzCK+#kJMNKYe&(1b`;HTN6`Xy6fI~+(Ly#w z3kwu2B2cubK+$3XMT-j*Eg?{}q(IS90!2#;6fGlAw5&kUasoxm3lxnMC|W_FXhngd zl>~}b7ARUpplDTrqSXY7Ru^hT!v-`qu7I@rmwU9~QM6xqcD=@cR`FF7tuvsxfBz_2 z*ZEPjo*hN&+flTE9Yq`3QM8dAMH|~uG|G;m(RLJVVpFuKK+$FbMVkv0Z6Q#!r9jbE z0!3R36m26=w5>qVb^=A)3l!}jP_&~!(M|$IV+4xE3KWeKDB4+|XcvK^T?LAE6DZnU zs1>a>pm9kBq&-`?7OfpcAD1sd?lGWMd=*9e3}`+&FpBndeiZFzN74Rv6dhnk(Sddp z9b`w*!FCiKVn@-Tb`%|EQ*^jM(GdbgM+y`jB~WyK+!out!S?Sjjt*o?IX+OXYVNb ztc-I9w2H5y=)wWbJ`+UIMb3|+i|r`7#Ezm%?I^m;j-t!$D7wOqqATqvy2_5Ct8I#| z5h%J=py)b*qU!~UZV)KCQK0B1fufrQif$1ox>ca)Hi4qs1&ZzvD7sUi=q`bxy9J8w z5h%J>py)nH-gQDmg=SR`Eb`*VQN746o6#ZaF z(T{c%{bWbc&vq33Vn@-hHbuV)6#Xtx^oKyvp8`dH2^9S;Q1p*L(Z2#k-3I2iouUqb zqV57k4S}Lgfug2BQ4fKlmOxQYfuddlMO^|#ZGocR0!4jr06q6zFMn$V7-iR>tv*p8w>b`(uwN71Bq6isGR zG`T?06aqz43KR_%D4I&3Xlj9?X#|R<6)2icplEu5q8S8=W)vuzNuX$EfudOiie?ok znoXc+h(OWo0!4EO6b%(98Ya|=`VVY$PF5*8wS0+az`*)W|GRQ68a}X9d=*9W3~Wv} zMHG#2eiY4XN6~zC6wPl((E@f9Eoev4LUt4_Y)8=|b`&jYQ?!^s(c%I{O9&J#DNwYO zK+)0yMau{jEh|v8oIug?0!1SQidGOPT2Y{AC4r)q1&US?C|XsZXf=VN)dh;y5GYzx zplB_jRy5bZ#&Q*q_F)Ci+)=c3xfZQGuvL5&Me7f2ZZkNFHgJ9vZD>c)Ms^f!Y)8>3 zJBmizQM8F2MVs1Dw3!`6o7)s^AyBlXK+#qLMOzCLZ6i>$tw7Os0!7;k6zw2Tw4*@L zP69<^1d7HA6pa%o+F77z7lEQ(1&VePDB4}1Xb*v+Jq3#P5^6>34s0A(0ck&0?)2A- zqLa#}x4j3pim#$*|AEcxr;efnoF7F8+EH|n9YqJ*QFMqMMTgo^beJ7QhucwfgdIgk z+7ulnP;|6F(J=x=#|ji3Cs1^}K+y>TMJEarog`3nvOv)(0!60^6rCnebh<#%83ILT z3KX3sP;|CH(K!M|=L!^^Cs1_0P%GMZVB?hvNc;ao+X=OMdAFuv+pa( z^StX_=lt=mby!Px?km~Jkoho~NeJm}w?&JjXpoIttH#WiSH(+<9+lbXn249S$9+!Q zOT1y=5LfHS)YpiDVPc>zX+27|-jGxT&e<^+|kjoaYTl zG;8U3gA&E9Ja1THOTOogOdM?Md7~0NJ9ysc#KoOFZ%pF#E}l0&QLUTjO-h{J-Seg; zZt3ZHGZSC+_Pnx0^M0N;H!*8~=PgJ)a-!!gO8h&>^Oh!h5B0odiAzrQycLNzMtI&8 zi5jPR-ZhCcM|s|=#JV#)Z%tzFXwO@lXj$NSw5ei6<6# z-usEjLeJZs=)c(W_9QM_;(1>t-oDWDzDd+s=6T;I3YL4`{=|kAp7&egyURWAKqCK2 z&-*8N&eiVyA4xuSt-AsuNq?2Q1|rFUtKC%)Nv>Suu7gN&*Uj!qh$QQ-bJs#7S-9R^ z4Uy!=4eok~B<-i!H;E+e$B{RUB<<%(w}>R|2LiW_B<&}a~M{;(GB<*J^c8w(M zhvM~!B<-h~^@$|y$5IW5B<<%44T>ax+Ul;8NYZ|?$H++1el)|VNYego{n3%6{p09k zB1!w#t;a`__RkYfiX`pdmz@?#+CLCFGm^A_;jt`|w11*+ZX{{{#@d2N(*BXGMUkZa zD@RKs$>;aDYbcVme`jPxBx(Op#1)aGeW(95k)(aA_NqwIzSnk5Bx&C)xi*rt?{>Q_ zlC*DEx+9Xb?>E^LN!m9I+#gBW-}v4fN!nl8eKeA^zjOIyBx!$XZfhiIf9q*mBx!$b z<>g4y{@%g%NYcJ=yfc!tul&6eN!pig-j5{hbMLz&N&DpKo=DO@`}JicX`jCMCX%$r zpWjE4_5fmkBx&~me~TpTL->J6(r$zQiFj2H* zXRLY$_opk;w!XWnJoi-USB>*yuC>oyX{(0Q=tVkcG_vP()HvX~(J6OH>c!T(Ka-Kp zdd@ocRw7+A9drGZjBvH%r(wca2_mhSFT+j1sdVX$~`0?@1@qyLcZ&c68 za3{C-tfW_QFKbW4szu`Q@FgQ|X5@H&1}DbjIq~dxC-)o8to0u+mE~Tl(yNba2H{)F z)~j^WUS*D6W$L*VuQFG!QZH4-ofK4Djzo^TnD&;FsV4%@tE%6U-bl5)NcTEih-2#{ zBURIT)V{t~9eaz_gGv`Kt=1#G+&ia6yGrdy_lj#?azVsPM)KXu*UIy{*XdekMsDi$ zxi?@}uznrkjuCH|9Sl*_`!zD`7Cp~9(mi1}*%g$+mr5o5&(7l4$L@uFZ@l||TI67E zju&yi-1AIDUS6w`!d4SXXSOOW8P}?$pmbbO!OW84vZ8TiMdMqIE15U5tk}Z1qVcm! zib^Xz&tBfWbmvwxOD0dBTsC=5k=JTc@${lrh0}`Ww#u7UJg#tBtI|n@B}J`Die?m* z7M8XuYEw{JHhcW!;#OtF#nZ-3Dx5r{wAI9M;|dB(rnky(UC_3mP3t!K1^KNlwsf)O zjN%zZEsF}rPHvgsI0C_J2I9)#MrDrp+E-)M|R+xJi>|{QrJ2O6QeUeosuC z)T(F6_}PFU7p5dCi9Rti{d(~m`+|6x}(&@L21VOd`?N?AO zJrYFxi4B9Q{t*p>Y7K%Qy<1S##UQ=4yKfSy5yb7_{^bQbxSpDM?%8dE8tD;tN?s6Y zl@>V8!~6Cx=+}CHXUF_btp^m04WI1LuKdaNz005M&`B@Zt`n^%C%0}FKCf?Yy-dD) z;mL!Fi)ZG0gL{rD=sjd)oA7n_;gt5}Z?7Y%ZN=MdQ~q{)S9+DYfNeOTL-|W}PF<$i zGfF2t?DH=O_qUUZxXG|Ta^Z}EX~i=p zhQC2~1-UoxZgVPKL%L|~DlV;~7QT4-Zx7S0D}HyK%YP^N?vIOiQs2`HdiEKfI?r9v z`c1k&EqbcYf1K&rMQWJ(-~SMuUvWWt$rb$E)tGt%cqTqdZC^b7p{-Hx_b`qpP%aGFnGiHoyuQLeuX`(KqbEdqx&7`%>tyH zg1g~Ky^;J1S^17u*jn?<3T*lPxLPWVaZS13KzJTc*j1AHlUs4My4yirlzewtcrw4@ zy;14P?Woha0zxd>d_eV-;6?e#JGPU+JoM*G_m!#g)u;kl#zcce@7c zEp;xxyzc$0i(7GX*jBHpeZ}Poulm&Qy5ic-uXJ@+x|%z<(<=;eW15c^d$zqIcPxKL z@dkDA+--}V)wcXy=-v^$c*PaZb;?y*el>P-uc^2kYQ=TJhZ?)p(5rLj@QR(l@LlNM zZ0ZU3p5S@q7s6_mG}f zeqFk&AbblIHr(xnd#ThbPd&?Bw>rz+_Uozg--vS;p6_lj?Ut(~e6Qq(2Ypnn(2!rj zp~8LA8E?V8Ze-2UiM9 z#!c$x?sw1W)N*>>ba&6a`S{YA%_q!k*m7dSmP6Y#Z0YVQb{pp|K+6f!i%LriClHo164%Tjlj*Bwh;8(&yfSiZw|h5IlaK2bq7zrw6> z{NFyZge)t4^eeaL?5194#XUpQXz$~SJBSr`3-d$ZDJkyOSQo3}$_SO0e`rggE-3iV zkGtG2t+-nX8@qQiwBLyGkEi+E3$3_ES#d|Q;(nyNM+%?tPk~*$a>v{Ut+)qQ=?)xs zK`ZX9@dqNG8(O<37ruuiGQ7){dKcK8P~9(0{Z_+2e&xS?{O_u+ z)Qub&sh`$3l4lRt|La%f6!m^ST>06)J*2Dj%hx9iNWMLytMtovkLHqS=zwc7pCtPvOJLdW$wK4PEXac}2&9Y1haneDH1Jm`J{wqx#dgLbUvelK=x zrek+^71=&X$3pjeusvPJ+uc=U`ym~_ckck(f9cr9fwA3P$GPqc1hy~K@#)&(eoe<{ z-Eb#$Jkfpmz+V0|9j|B*?wfRc*S%xy`CsUGWRq|=({b!E;V#zk4tE9E%Wu)~$K%3% zP{(#H!`)NI`RW$9E6+EFJIa8SY1P+}}Ig|LWMGU$}egxL`oIFVXS26T|(6jv0f)T|>tqL&JTh zj@O(V?sYnTI3nD8b!>QQxLfKtVN|$Fb=-7DxF6H;m(k%qtYfEwaQD^m{K9Zws^c~X z-QFK>>X3H3gaIe>K_q1^D)3I@JxLfHsX;!#r>v(TzxS!DRx7p#2 z%n6TO=7z`qIxd)-iiwxa;URd~vu7bX>J0+#7WK=dS!SVsN)4!hkK=tFJBw(T{`Bj3U^%{N3ITcp^mH9 zgnOfodu|T*4>}&RF5GQ(oVGsP^K^W0L%5&O@xaD#2X}Eq#Uuj7m-!+oxfo1YH%vpW90HQcdh z!()%})A8Z=!u`CC|G2NN*`J@x55r@x-QjVlj>|p?_q96i*c0xLbgceGxEtws##iB< zsN>qb;l4-5ulI%fR~=h?AMVaNmi!p*g*raEKin_qc*uPL&n|EL*YMcq_wabKj?4cH z_w_pNbYI)Em;YGDn*W6RC>=*13io6kZ*?F2?d9*&@f-K`Kij|S=ssPX+Q;iy=Ds3m z&tI(LKQs#(XpD2>2`F_OlZ49>g74F)b8K7*X!AdM>g=4+E(z259 zIEkm+W8N|^&mLrYd1FgUy*&4@IL~6SKa5gCltF=Qco9-9a~Z~Cp;@G z?(18XXJLumZPe=xU*dn3Y4+7Ay+(Jzyu5MlODRR}GyIj_>V%TQ>F$Mk4j-IXSXNdt zdF<>m_iFz?|8jSwoc{2>s-5KSs{F?<_pVF*YUKWJFXxBzf4rPM&wd^2{2uV=4unbay@etQ%Q?HJ@<($+wu_bm=#-MEnqK&p4*wgx*1JQi1`N0ppNr(SDba>kVFOqm_kr!Fy zC2ID_aDQgP_jfenyWe>Bb?!#ESLOGTd+lkF^r`mvF_Lk<`%sgX795D#A$E?7eoc1) z(gxRdk4M~>bc3o6kiWuSYG|D?sT4clUTs=NP|y9*P0NUNb?>ogG_cPrrA1?Jx)r?c+qB>_1tXh{>669Bi(H0MVo8Zb+f$}ZJ~LDn;qOg`leaO&5m9)PqVh0oxEr( z&021DcHcLyS<}sYcd_!dYuI*|tBrPb+wOw3)vjjSU9xuCRc*VA)?Pbl+g-K}+6mk4 z!gbWHV%uH1PTIM)-NoyyonzZwzAoC?Zntrl?|ALFZFl*)YG>JYm#>?4rfqlmPSDP< z?Ji$;?U-$M`Fd!l+jf_)r*>f5UA|u0QQPkF_11QuUFy}wUA{irX>PZ5m#?q3yDjR~ z)?L1S+V1+#j7FRIZ@B9}Yn>@NI`wz@vxYby(f+Y}+zXhHlLGrok0~L8bgG05)|8MT zni4WpQ$mJmO32BY5;9y<56SWaCNgE-PwGlE!8zED* zLm>nGpWXGJ^?RxtbC(Pg6qXYa--aZGE2svLHAq%w;vPc^ti?tDQfi^;xXd`5) zHbO4cM#x3l2)S4rA8*+6cK^8zC#T5psogC}f6T&D~^V z)pH+qqQ#+*pB#9e+6cKz8zFaV zBV>~{LhjK<$i3PKxlbD*_iH2M0d0glsEv?^v=Opd8zEb?Lm^lD?cMdCwajiqt_g+w zW=}sHGdU*Y@xcBfeM-m^I#oiR)Rd5?G$rI|O$m8MQ$n_CO31UC67rm;ggmb)A=@+& z@`5%(Uerd&OWFu|SsNj*Xd~oRZG^n0jgaly2zgx_Av?4Y@`g4-c4{N!O>Km{rHzoc zwGr};HbQo3BjjCeguJJXkoUC_@_{x&KGY6{JnEn3uKz6ilt%QiP{;_oPx4XBBHbM?)Bjhh_g#4|I zkb~L?`9~We|7s)TkTyaNYllKU_UF6nKkEg%@9{}WNc>y74e=r|qhsIk6^#V;EjX!v z3pj}AY<@s-QwJHDzA z_>Qjxf$#WA68MgQld1is^|7J={hs!iZKzUmP8j;|vK ze8*Q^0^jjMQf$#WgMBqEV8WZ@AucHWj$5#`A1Ckq! zrbYa%4oLhtyL;kCLPh)Re#_C3nDH`2%_4z)3s*|fahxwj&Dm1af-OZY*;16pmZDZ{ zDQeA@qI|X#wP8z9TQ-W?5m3~gfT9ir6m=w^s1pH2oe3!FLO{{+1Qc~8pr{)GMJEtY z)SZB$9t0HiB%r7l0Y$wDDC$E%QC|Xz`VmmnpMatP1QZPT1QbmmplBii zMUx09noK~^6atE-5>PaafTHOH6wM%niUvjeK@LcKvzyVuQq;mo6-Q#`%M_JH0{a%y zl%g`um!jEhDVoEUqI1|%G?y(!^Vm`}pDjh_vZZJNTZ+zOqv(7BiWU-3w1|MB#RL>x zKtRzF0*aOrP;?;yMHdlJbTI)%%LpjCgn**u1QcCLK+y^UiY_Cd=yC#zRuWKj1p!4@ z5>Rv%0Yz66LPfJ8{#6c0{5bbWJ6a+|8&i+7A~Ex2idIDe`xfMsq8m70idM6w=ti~_ ztzk>iO>8N;nJq=Pu%&1%TZ-1PrRY{Riq;cQbQ=Lh8we=6oq(c^1QgvtK+&B96x~HY z(cJ_TZ6cuP9s-K)C7|d&0*dY@py&YtiXJ4O=ph1%HWN^^g@B@m2`GAmfTBkUp`z;| z{`(F{yq|sQ_j)OsYKk6<#LSl|dMXmwx3H%aJlsOX7^U*COgJ)UE?MNdl6 zr*`l9lSs^bnWE1lf&CK*DMep!z7&1QmZGoNQuH-jiuSUl=o_{a?PE*Pw`?i;jx9ys zvr+T|0YyI&Q1lZ4Mf(XT`k8>DUkE7rm4Kq(2q^lUfTBMLDEgCtq5}jJ{Y600-vksL zB%tUY0*d}6py&_*MTZF}^3uv5<>#cn9u*;=D2)&*+7t1|J0S6S?hB{U&!lLN-4^+2 zG4o}LVrhZ>6B;Q+8JsUgnQSS_VoOn+Ek)UEDav6>Q7&7Gs<5Rf!Iq*V8%0$KD5^$4 zQFQ`}Y7kIVlYpXH1QgXKpr{T3MMn@&RF{CFBMB&~M?g`10*V?CP}GosqDBN1H720w zC<2O_5Kwe9f!m^E2q-$15Go4N{JR{G___88#q_lBk^U~bEozz;Ghe2tMOtA01WQU$ zOU{>~Jhl|IVoOnLwiM;FrKk;CirTWJs2y91+Owso0~P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_WPk$|F; z2q+pv2o)Wd=I?hv;*H(k&WSdcqNF|2ADk95U#95fw7~uepOm8EoG(Qq*itl-Ek&oW zrRY?)6rIMFqET!qI-M;=XRxK{Og4%}6Hs&(0YzsMP*gxb(HH`X3JEA0OF+>$0*b~H zP*g-f(F6jDCK6CIiGZTX1QbmnplB)qMbii_cO5m0nB0Y%pkP;@N;Mb{BRMP+IJ0tY1C!9GPaTZ&$_+oJ2! zV&=;f-Ix~GKOvSRv(0Y!HcP_&7FqI(D^x|e{W`v@qypMatV2q=1xfTD*8DB4Uw(G~)V z9wwmZ5dw-HC7|dr0*W3dpy&xgsOW|?|2YRFesjdZSuI7U*=^C2X)*IWIe0Yz^SQ1mtdMeh($w2OeEcL^wZkAR~02`Ku2fT9lxDEf$iqTK`(eM~^n zCj=CIN6dfd>=pO=#{w1L35CKJp2`F-Z5BWxSHM*~;yDQNC+G&JAwWJ^(1wiH!kOHp+;ifRy0RFiRfTBhO6g4KG=qLh;nh;QQGyz4&5Kwe10Yyy-C~8JP(Q$-OQHJkdsirTQHs4ZKH+OegmJzI)8u%)OY zTZ%fdrKmF-MO_FeI-Y={t^^cyBcSL60*bm5P}GBfqMig4^&+6CHvvU`2q@}HKv6#e ziuw~!G=PAjfdmwtNI=m^1QZP-plC1wMMDTE8cGNiweKzl&X=N7*-~^GTZ%@prRa3F6rI7AqBGf2G@30%XR)Q|Y&MDt2q+pu zKv5w9MPmsl8b?6Ucmj%w2q>CBK+!}3iY5_IG?{>+DFhTvC7@^;0Y%dZD4Ib)Q858U zGYKe~MLLqO5B1QcCIK+*LC6s;nl z=mtWl=p5gl;DE%3+HKKXDe7S#(N_C0^JR)|_5=GTz*DzHw{X4`tz}EmI<^$u%9f(_ zY$>{pEkzsHQgl08iZ-&P=ngiD?j)e-E&__~CZK2&0Y&!^P;@T=MfVX-d}$<=Jh~mwwEA znWAs}z(H{g9{YgO40RoEtBB1DR0*Ve2Q1lN0MgI~|bcleW!vqw0Q9W!&QG|e^Gy;lz z0*ayp6a@qnr4vvTBcLdQ5GwlG_d7Wt@hb+8QiQT)-jK<8DDawfk_9HA(igGz$ zimI@sD8ZJZBwLEAvZbgRTZ*c)rKkp5ifXc@s1_SVwFxMyLqO3H1QgXJpy)^fis}(i zRG)yN1_Tr}B%r7f0Y!}oC_0LOq9z0s9Zf*dF$5GHOF&Um0*aauP;?vtMa>B)YC%9z zOG2n99`(<6K;pyfwkSIqKGH9?d)IlqSK;*{Ro|uqEVbLMW?f+=nS?LoynG>(QGL?i!DWGv!$qjEk$G4 zQdG!B(O3eC#t~37o`9kv0*WROP&AQ%qDcf4O(vjd3IRn^2`HLIK+$vpie?Z{R7^n8 zOah8#5l~b@Kv5|HMP&pO%_g8|4gp2y5JE+#ME$HjPElZA0XbEQitM&%ZZu}TOwod9 zU_XK>rRY4)m!k98QnZjQMT^){w3sbL7qF#h30sPmvZd%kwiI2&M$yFt6fGm5=n?{o zmJ?8PDFH<*2q?OYfTGI@C|XHC(G>&~T}eRERRk1WO+e8#1QcCMK+$ys6kSh1(JBIp zZXlp&H33C85>T{;5GtA<^@lki@jCYRuFsXCpX{%R+!T$OFH^KG8rYBUN-4UP^QCA# zTZ(RDOVI|l6y462qK#}Rx`Qo6ce17EF18fi%|_8C0*dY-py*x#itZzz=zao<9w4CT zK>~^%BA{q90YzH~D0-NHqDKfQdX#{o#|S8ToPeSy2q=1zfTE`eD0-TJqGt#w+Dbst zvxHF5Em8kE2PFQ9eFbE#6fLxmXwOAs=F1el7!B-4z@-$u#Q9S6GFysXVN21gY$WIJ0Y$qBDEgRyqE84Y`jmj8Jp>eeMnKW$1QdNiK+%^36n#ZN(bt4f(YC0++X0F9 zvJYY}NYPq*q`x;BGhe3YyJ%oPLNKN1d(M}lAJ|g#BU_4oVoT9}wiNx$mZD$SQuHfZ zihg5D(eG>&{Xsy{p9B;gAfV_k0*d}7py(h0MgI^`^e+KLhX^P-OhAzr=wUmGA_Nqr z5m4k4P!uJgC?KFHoq(bk0Yw=E6lD@nltn;MoDeG77xfztc8XTnN3?IH=r8+-mL0^* zmnljFf&B=|l%gc(OHoy}6jftOQFXQy)nH3eO|}%(VoOnNwiMN2OVJT*6xAi5=tu&J z>Jd;>pMatU1QazSpr{c6MU4q4I*NdzCIl26O+e8x1QZ=hKv7cyikcBnbQ}Ri%?T)K zK|oPU0*dkoC~8GOQENh|C^zsYIUwEO+WJ}RlwiJzHOVM~Xii!v*nm|C&L;{K?5l}RlfTAe`6ip?dXc_@U(+Mb=K|oP4 z0Yx(jD4In;Q3(M>r34g}5l}RnfTB4B6rDpr(Od$G<`GadpAae<75Kk7Ao08GuF&aH zbf(=&IyZ=!FH^KI2<%5FrxY#Xd?{MYmZA&TQnZ9EMN8RIbRk=cE@Dg3#cU~B#+IT> z*eF^~K+&ZH6s;hj=rRI|E+?R9B>_cO5Kwd_0Yz64P;@l`Mb{8ebS(iz*AY;3Jpo0l z2q?ONfTGm|6x~Qb(Ha7ZZX%%QW&(y+8}1WOwnyY zU_XL8rDy}^OVRCYDcZ=EqC419bSGPi?qW;P-E1k^#FnCa*iv*a8%6gKP;@^5MGp{A z^dJF64-rtbnSi1#1Qb0?K+z)v6g^5n(PIP@Jx)N;69g1JNkGw41Qb0@K+!V<6m2D- z=ve}ao+F^>c>;>I5kf_`2L2)kB)-t@3ayu-m)!HBF9b33Wr|)20{ao}DMhbxz7)O2 zmZI%!DSDkPMLXD1^afjscCw}DO|}%h#g?MC*(iF4fTCRl6unD8(R&0Gy-z^V2Lu#- zNI=m?1QhKipy*=)iasHr=u-lU_7G6?839F~6HxR80YzUDQ1lf6MPCz8w3mRQZwM&b zM+gf0*Ve3P~@fSVLOT<1Qewa zP~;O(6eXZ2AfPCnfT9=yMHvJXWfD-7MLaeBg2(}c}WlPbKY$>Y8 zMp1nNiW(45)R2IpMg$Z!CZOmj0*aatP;@i_MaK|ObSwcyO$jJ!MnKVV1QazVpr{1_ zMJ)*^$|Int6#+%92`I`Zpr{Q2MQsV8qGY;1+yRL{X!owGriYL8Yum&AcIh$mWr{kb z2c?Bl)S2_8s0&+)j%Q0zSGE*&V@uHqY$@u_mZBbPDeB3VqF!ti^(LUG4*^Ae2`K7E zKv91JiUtr+G?0Lz6A36fiGZR(1QZP>plApIMMDWF8b(0T$pjP)C!lBq0YxJTC_06J zqEiVdI*ov$QG`%Yhjf3H0}{X3K8SUcq8IJUA*ZLu%$F%TD?NB@oD`kS`BGHCmZC9i zDJo=3(O9+=jblsEc(xQ3v88ANTZ$&KQ8bBwqR9jlO(CFYDgi~)2q>CPK+y~Wii!y+ znn^&>ECPy32q-Egps0+1qS*u#%^{%Z90H2w5>PacfTH;X6rD>z(E1gGdzyDeHQMGaFA z*wSO>%M@))5Bg4$qB}TWitc1f(OqmQx|=OUo7hrx4_k`vWlPb0Y$>{*EkzHoQS=}I zMGp~Bw3&dSEd&%jOhC~i1Qb0=K+$6a6g^Hr(Gvs|JxM^(Qv?(}O+e8z1Qcy0py*iw zik>5&=y?K)wh>VD0s%!Y5>WIKAyl*>-Jjxs#Ix*EM7K-PQoAjBIXz~+OwsoA;L<5l z^g8ED(GIp0y}_2Eoop$3lPyJWv8Cv3wiLa?mZDv3DSDTUqW1_WdY^!z4+tpwkbt6( z2q@Z3K+(qp6n#QK(We9y?IED(GXjb}C!pvH0*byQpy(?CioPbGXfFXp-w;r=kAR|Y z2`KuGfTHgSp`usQ{req|`0Mr&?KLUtW)J&+NROE>Q}lCs@a8lr`i1kQ=vTHB{l=D} z-`P_12V08%WJ}QjwiNxvmZHDeQgo1wqJIb|`j>#BLj)8ZCZNcR>0vvHA_Nqr5m4k4 zP!uJgC?KFHoq(bk0Yw=E6lD@nltn;MoPeTi0*Z17D9R>HZ%M zNcS(IRGTeDb=XpL1Y3&gvZd%qwiMN4OHqBc z6g6N=QA0M08WB*`n1G_A2qm|vlL;sqPC(HJ0*XcwP;?3bMW+%_ zbQ%FgqX;NEoq(b<2q-#}5Gv{%^Dl5f;_k;ayC20TMR(e5(dbyre3_y#v0#0v6cuv5 z6pdv|(Kxmgjb}?y5nGBTu%&1sTZ$&JrD!r+il(qpG?jp&X#^BaC!lBs0Y$|G6wM@{ zXchrQB?J_e5>Qk|K+$XhisledbPfSUa|tM#M?leh0*cNhplAUBMduMvbUpz^3kfJ% zLyz7*}`d?|X9Ek$p!rRZ(86urZiqFrn$dY3Il@3E!meYO;Rz(&!B1QdNl zK+$djiasWw=o12pJ|&=N4*^A=5m59w0YzUBQ1m4MMPCt6^fduRdkHA|hJd1d1QdNs zK+$&u6n#%X(GLU^{YXI3PlQm>>oI?|0}`KMcZGIH(F1l{v_BRzU#94{Sn$LGDf*rB zrRWc~6#dDTq62Ix`im_^f3v0NAX|$5VN21!Y$-a#M$uscio6UxY)4UqfTA=4ihKf! zq68EL1QewcP!uDeD1(5aOah9s2q=mZP?SwTQ4Rq`xdaqdA)qKhKv9x_qN)TGRU@FN zIw4f_OU&QnfW(*BXB~f)qGm>_Mn=qhnW8!wL1dv69l`lhRF^G9N3x};9$Sj)v!$p3 zTZ$U8rKk~GiW;+}=qNUdnh;QQGyz4&5Kwe10Yyy-C~8JP(QyP6H7B5`1p!4Z2`I`V zpr{oAMXd=a$|sa zgpc&w*hjQ388P!^icZJ~`Y)EE?wl`0J=jvzlPyKP*izJ+Ek%9UQq-3%Mg7=P)SoRy z1K21UNI=nv1QeY_K+zxqiUt!yuDH@j% zT((4t#&f_J^@AN5>T{&fTHsVC_0~jqJ;z$Eh3<3 zF#$yv5Ky#)5GpFn@E>$Q;)m?Bj$@^$sgYWm5i?(=Xjw+^_JvY(3Fk}Ea<&v*%9f%P zY$>{oEk&2JrD!EvimqTw(Uoi|x{8gWs|hH&hJd1L2`IXbfTHUOC|X58(G3I?ttO!8 zMgoe~5Kwdz0Yx_xP;?6cMQaHtT1P<9tppUUC!pvy0*W>eP;@&1MH>kyx`PlZx+udx z;DE%Rj5s(KOHm!WcYS9@%zT-mdoqGL%cSUD&X=P5*iv*qTZ$fFOVNXDDSC)4MVr}D zw1q8253{A{5jKh*C7|dr0*W3dpy&w#ik>8(=qUnWIk0Y%RdQ1m6qU{6}y-o-f-JRi|;DE%3xEb9fMGfpD z+K!Bv`7%XsWdsGwrRZ(Wm!fyrQnZULMenku=smU+z0a1S57<)lAzO+*VoT9(Hi|wb zpy(3IRQmq5K#0b0YzUCQ1mqcMSBS-`i6j_eFPMJOF+?g1QdNw zK+z8b6#Ym*(N6>v?I)n=$~C7`Go0Y%3VP}H1&q80=cwIrY@kAR|91QfL< zpeUb!qBaB+wI!ga9RWq{2`K77Kv72miaHTc)R};yE(8=EPe4&uLa6A7Oh2*GDY_!v z!Ks@WKGNT2qg!Uoe3_!2nL+-QQq+s{rKmSsiu$mns4rWJ`mv>`KU<0hu%&1qTZ&F( zOVLSe6b&MvXfOdqLkK7uNCZK2z0Y&E!P&Ai-qIm=q%_pGfTmp&~5Kwd;0Y&E%P_&SMqD2H0EheDo0s@Mb z5Ky#~fT9ZtD7uIcDjJ{ZuW>-)&F$u=NQ$!TVgJRMG4o}LF3k*{x>kx-aK02>#+IVX z*;2HUEk#$brRYkw6kWxZqN~|bbPZdIu4SX>Is%HWC!lB*0Yx_uP_&wWq8kY)T0=n5 zO#~F(OhC~s1Qe|$plBTdMYj@Aw4Q*X+XyJyKtR#$1Qcx~py&<)itZ$!=q>_^?k0qa zF3I#icR=EO-Ha}mqW<=6g|NCQuH8OiXLK1(Pp+3ZDC8%!)z&f zge^snvZd%TwiG?iM$r=l6g^2m(NhEzJxxH-GXxZEC7|e80*am^py+u5inb9@^a24z zFA`An5&=ao6HxRD0Y$G8Q1luBMcWA|dYyox9Rw7;K|s+?La6B8OuwlE5?^bdXuMB~ zUbDw&Z)V2Kmnqtn84O%4MelOH6urlmqW9TS^Z{FnK4eSLM{FtD&6c8%*;4cgTZ%qq zqi7ESMV}E+^f>`VUl36AB>_cW5m59s0Y!TWDEfwgqJ0DueM>;mcLWrDPe9QR1Qh*9 zK+#VG6zwOV=w||oej%XfR|1NDBcSMaLa6BNOn-(05ZbKWr)bmn}ty*iv+uEk$0I9=S_Vge^sBY$@{DQWRyQC?KFHoq(bk0Yw=E z6lD@nltn;MoPeTi0*Z17D9R(a~%vI)*Jp$FilUDO-w~u~Bp!0Y%LTC~84KQA+}f@(3tuMLOw%#@dOlgC7`Gq0YxVeP}H3eDyo;||LuUp zzqXs7`dQ&4{TFTY$cmXSQ`9FbsJl*z`f|P$^f3_42U`x?JwiKPnmZFo`QZ$Gy zMT6N=G=zw zDVm%W6t0(|DV#4wQ`u59jV(pf*-|uvEk(s_DVoWaqFHPyDq%}eDH}y)1Qg9CplA*O zMduJuG?##)c?1;AC!pwD0*V$8P;?#vMduSxw2*+JMFbQrCZOm70*aOpP_&eQq6-Nq zx`=?HiwP)NMnKUegiz7MEdL@0B>t4${7jOft#&7Ac~;DPnWD?Hf{h!bXeH-M(G_ed zx{@tLSFxq&YPJ+z!vT?7=}O+e8m0*dY-py*yg zsAxr&zuf_e_qR_pUM58i?UDX{SuyiviXO@ee%L5Qn>k;Kwy>q>VYU=K!j_^(*;4cv zTZ$fMOVJZ-DSDDEMNhF&^fUoQ&k#_wm4KpW2`GAwfTHIKDB4Cq(F+6=y+}aOO9T|X zOhC~q1QfkWK+$Ui6m2J<=yd{$b`VhX1_4Do2`GA#fTFhuD0-U^DtaKxuX=}5lwp5+ z|3N9*l6t_F6*FI^=>4pq?Ojsz0q0B6hiobOh%H6C*;4c|TZ%qmOVOunDcZx9qR-e; z^f?_cW5m59s0Y!TWDEfwgqJ0DueM>;mcLWrDPe9QR1Qh*9K+#VG6zwOV z=w||oej%XfR|1NDBcSMa0*d}1py*EmiVhG$Mek<$qa2WU)E<_-Cq)JJ;q9-inE5hA z|7HdAHc8PT&X=OYY$@{MdgLxe5w;Yiv8BjoOHq_9MFCri(%DiJW1}d8fTBzSin0hO ziW5+jO+Zl&0Y$k46jdRhC_z9`l7OPB1Qb;xpr|?lMKuU0s!2dmEdq*a6Hru#fTAM^ zD5^_9(UAlc)gy$84rci`J0S7T?1R`pQgoerUbKEZX1+{O<9P7Qy;5`(=Sxu&wiF%B zmZD?WQgkd^ikh;es2N*|j$=zvbG8(M)B~G{w;P})H@zCU#6&kJP00;q5+&QMFZJVbRt`dPGU>ZAhr|@W=qi! zwiFFzOVKd46rIdQ(QpEaMi5Xml7OO92q-$0fTGg~C>ljT(dh&fok2j+nFJJ#CZOmn z0*cNips0X=qA>&%6%tT1mVlyh1Qd-Yps0v|q6q{PO(cYh`o{g^9FTa-z5>!uiY|4} zi%yEi%$F&e77tE(NQ$O&z7)-1OHnafie|ERf@{&-t}einE5hASH^=Yw@A@d zoG(RJv!&=7wiI2@X(H@M)%$F&8I3B$Bh!j1-`BL;KTZ$fIOVQ(O zDSCn}MNhJ&=qa`oJyf+^rLm>RXG>9(EkyxaiqhFq6k|(K23v|U*;16nMp2xAqHF?+ zatJ8OC7`GZ0YwP{ijo8rRVARP8UaPs2`H*TKv7KsifR#1RGWaJIs_CQK|oPm0*a0# zpr{@JMfC|NYCu3yLqe$NP~2bUfVdxs?%*7jqBib%(MH)Z^JR*T&JON;T8fV0d?`AX zEk#Y)Qq+tsMaQwFs5x7TTCk<4C0mN}*izJrjiS~B6y+08)P{hfwgeQlBcP}~0Yx1M zDC$T+Q6~b5IulUTg@B^t2`K7HKv6dWicTP)s5=2gJqRf3NkCCA0*ZPQP}GNjqP~Ps z(NWp{4hJN@%WjLBWQULRkIQzWUv|uVnW7W3gP*oa(Mg;yMT6K(9x@dOkV5l}RNfTD>66ip(aXfgpsQwX7=0oi`_XPu(JKI=G8 zitHbpiB8RqnJ-gRoE@}(UW#UNz7)-3OHm11ib~m1RK}K~*=#AA!Rvz0Yw)RP_&GI zqDu%UT24UGr34hMAfV_n0*WptplBr_R5U%?Kf?iu53xJcGo)yYjVrQa=F1dalO3G< zf)riL`BHQpTZ*n{OVKK}6y3mgP;>_YMRyWVbQb|dcN0*wiGZSe2q?OjfTH^dD7v43q6Y{l zdXRvkhX^RzOb8WSmF=%}K;mQUvyN9w(HAzhWXH^xDS9kBc=jbJdYtp6=n1wIJ;|1$ zr`S^TG+T6 zqU{6}y-q;U4g!kaAfRX`0Yz^TQ1li7MQ;;O^bP?fs0CY!TC$}mk1a*5*izJ*Ek*fkDQd$;QCk9v+7VFHo`9kb1Qc~7 zpr{i8MV$#K>Ow%#@dOlgC7`Gq0YxVeP}H4(q8k1pC$pt! zI9rNFu%&1uTZ&F$OVO!pDLRdfqEQ4ColZc}83YuaNkGwP0*cNepy+G@iV6rQ8bd%) zApu2W2`CyzK+$*tii!v*nm|C&L;{K?5l}RlfTAe`6ip?dXc_@U(+Q!XlXCn+4oLh` zyDb_dMfPc;=!~40`7%W%IYEQBrKptirKpT8MYGvbG>0uk=dh({E?bJ`v88A}TZ+zQ zOVI*0iq0dT=zIc-77|djh=8KS1QcCBK+zHcik1>kbRhvn7ZFf&F#$!(2q?OQfTHCD z6kSR{(Fy{JE+e4masrB05>Rvn0Yz65P;?a`R5UZk@8f{P)9tg4v!tlE-4)0r|m4Kr41Qgvy zK+y&Qif$*MXd?kdcMwo?Cjmuw5m0nD0Y#e#D7uG$qI(G_x{rXO`w1v|fPkV02`GAq zfTGO=6m21(=wSki9wCH^uFdh6J0S7*?X!;8NzqPwr2lA6%zT-mCv$?k-;<)JIA4mM zW=qjCY$@8xmZE3bQuG{Kik@dn(Kfaey}*{D7uhI!iGZS)2`GAnfTC9kD0+>6qU{6} zy-q;U4g!kaAfRX`0Yz^TQ1li7MQ;;O^bP?DUkE7rm4Kq(2q^lU zfTBMLDEgCtq5}jJ{Y600-vksLB%tUY0*d}6py&_*MTZF}@^baS97PdAsOZxizvhQd z(Kfp++9O4O+m~k3a%1Mp6s6||9d}DnjPs=^gDpjwY$?iOOHrIHMcHgA%3(`UE?bJK zu%#%$Mp2T0qN)TGRU@FNIsrvB2q>yaKv69MifR*3REL0~BM2y}OF+?)1QgXHpr}3p zMGXijYDhp)BLa#V6Hs&%0Yyy+C_0*eqGJf5qG+x^+5w3_WpIMr@R7c|r|llF<;KjH zDQcb@ocDn-FB)-Ew>v)_L{bZyD<;KjHDH@g=JikYZPUd_m8qSuY z5o{?M$(Ev1*iv*VTZ&F&OVKE{6rIkNqBGbiI+K8+(F7EoML^Nn1QZnzP&9^sqCx_S z#u898j)0=^1QZn!P&9#nqKO0)O(LLZG66+X2q>CLK+!Y;il!4#G=qSmVgib05<*2o za{X@{koeK|_pXOZ(PX=KJu5e6zD&{V+#vG{DVoFiQgjYmisrJVXdYXN=Ch^fT(%S~ zU`x??Y$-aQEkz62C|X27(P9FME+C+22?0e*2`IXdfTD{CD7u({qGbdWT|z+7asrAj zC7@^p0Y#S)P;@x~MJov?x`KeBD+wsNih!c42`IXTfTC*&p`y}UKhFV)ud>^sGAY_` z_pYzYjhQb~v^qB!`jr&j$oW#VhAl-mv8Cu{wiMmMmZG(6DO$&tqFdQgw4Nf*)QuKn|7Cn(0Ghe3YncU#o zy;8K5^QGunwiG?bmZIm`QnZaNMK7?W=tZ^^y~LKHm)TPE3L8bQ5>WIS0Y%#hD0-cM zq8$Vjy+J_HP6CSFB%tUm0*c-ypy(X}igpoD^ezEK?-5Y+J^@7^5K#0X0Yx7XP_&zX zqK^qE`hdLnBA{qL0YyI(Q1lA{MZXeI^cw+1zY|dO z2LVNY5>Rx2fTF($DEga#qJsn!{X;;}zXTK=BB1Cn0YzRFJ#0r&gn*(n0*ZVBilT&2 z(dW6o_pMX(j=}jtiY_uzL6w;KGDVqHf=1s=$~C7`GoAygEr;`ehv;;ZehP)3#Tk^a3# z>bNQ~^JR+isss~%l%iIgFGa1{Qk2h@qBd+PYRi_Qc5EqX&z7PNY$@uKv8!Bih2-G)RTasUIY~NCZMPf0Y!ZYDC$Q*QGWu81`tp* zkbt5S2`D;=fTBSJ6b&YzXb2%x)S`;N!U2gtXOGcZO3|;W2W(Yh=F1d~s1n?>Uy4R@ zz7(CpmZDSHQgj+yibk=e=ybLeoxzr(Gucu!nk_|Vu~Bq30YwD_6pbOEsE~l7u>=&2 zBcNzJ0Yyaw6ipzYXd(eclL#o9OhC~T0*a;*P&AEzqUi(_%^;wtn1G_01Qg98ps0j^ zqEbSr=;SK?TMkHkj(zTWxD>Ur+oG~6G4o}L=2i)Q{Y8rAalRDIXG_t!Y$;m6mZJ06 zQgl9BiWah^Xc1eA7PF=30yc`45Ky#~fT9ZtD7uJ%qKgSAT1G(8B?J^LC!pw30*Y1; zP;?mqMVAv$w32|LD+nmMl7OPC2q?OmfTC*%D7uz_qU#7Kx}JcdRfJH{oGO0pU!9_r z_I0##q$txK_TNw?X1+|(O;v)1V(QRxg+Q62g z+u2gIk&U7|2q?OffTFtyD7u?~qD=%8-9tdpy#y59M?lg21Qb0$K+%H)6g@;h(PjdQ zw){WD-FI|U_1=d4J=wD}$t1u`=vAtMln{EAUZsPIiiQB8Lx2PXL;*nsL_kGBKoPNb zRK$YVu=id-#oka+M6tp9`)1!)l5?K*toQxnS?kSO=j_~9vL{34!(=8wAfV_W0*ZDK zQ1mbXMUN0r^e6#Ej}cI`n}DLn38A9R75sA@kc>8VU$jMv3hgV}o(eJZWs07z5G?*f zik{(oDcZ}HqG#Ds^c-7?o@YzZ3v4NRku60pv8Cu`wiLa>M$xMT6um}3(dz^hy+J_H zn*WIf z0Y!fiQ1mweMgI^`^e+KL#|S7oPC${D(9?DlMF=QLA)v@7peRZ}Q9wXZDgi|?La6Ag z3jX&FNXEdx!TDN>Cfj{cS|Vn?Oi^Yc$oNN!%5lCFm1j#)1-29=*iw{aOHmeEiYl_D zs1jR>Dzl}i3L8aL2`H*YKv8u9ifRy0RFieoF@=Nl`1#m!j5eDQd%(qPA=)YR8tM_G~HYz?PzpY$@u*mZHvV6m=n> zs4D?Qrw~xojew%=1Qhikpr|JSMZE|p>PV8SfTI2c6b&GtXdnSarxH*! zh=8KO1QZP+plB!oMZ*Xv8cqlmWheZ34oJq|_UO8$6dkiWrV)vl`7%YPCxQ*0T|i4O zdIsl9(P*|5oynG>v)EE}Hd~6uu%+l6wiKPqmZDs?6pdx0D35@maRd~NC!lBo0Y&)) z6ipEoMv6 z61EgAWlPaTY$;mCmZIfsDY}@AqDu%Ux|D#T6$BKmB%o*&0Y#S)P_&wWqRR;=T0=n5 zS^|pJ5m0mm0Yz65P;?amMe7MDx|)EZYX~UXKtRz(0*bCBplA~TMVkqsq6G;*#dnIv z+4rs&O3`7vFWQobnJ-gxLn3J4{yK=_`=V`}FGV-9rD!`_if&>{(amfrx`i!8x3Z<^ zHntSq&X%G(*eJS_fTFtyD7u?~qI(D^x|e{W`v@r7K|s;{1Qb0$K+%H)6zwFS=ph1% zb`enYFabr65K#0e0Y#4yP_&zXqQ?m++CxCm69g1JNeC5PpYZ!TAQ>mx-OpAjdc>Zi zJ(Y-=FH`hvBA61BqUShYik@dn(F<%TdXX(fFR`WQWwsQ(!j_^}*;4cxTZ&$1qv#C+ ziryrk=q&<@-X@^v9RiBpC7|d%0*c-zpy&eviasQu=pzD(_7PCDpMau|2`Ku6fTB+c zC^|qu(Psn{eNI5p7X%c2NkGw8giz5l34e_PlF`8Ki}p&<4tsR{bs}cIOwsp=;NEm8 z`hoMM=pb8)eq>A0Pi!grnJqVOVMGr6#d3V(GdcQekY*l4+4sg5>WIf z0Y!fiQ1mweMgI^`^e+KL#|S7oPC${D)YEnpMF=QLA)v@7peRZ}Q9wXZDgi|?0*cZI zC`u=wC{73!eVg##aX>N(+>CxFMWgJQenv88zD!YtWN;)yiV~bJMM<_4WwE8GB3p_o zv8AXoTZ*c%rKl=fimI`ts5%=(H3%rGNkCC80*Y!AP*jJ2q7w)xs!KpoJpzjA6HwHE zfTD&36g48C=tKgFP9mVFF#$zQ2q-$4fTE@Z6g4BDs5t>eEeI&eCWMO0CH)$iPSMx) zUB~jt@R|NCc3;#o88cs|s7*5HTwaRWa=sL`V@pwcwiI<>OHoI*6m?=tQD?Rkbzw_U zSGE+L!bVXy0*bm5P}GBfqMig4^&+6CHvvU`2q@}HKv6#eiuw~!G=PAjfdmwtN|%~ zIx`t8O-RvMoG(RZv!!SZTZ+zMOVPP(DavI_(O9+=<*}t`99xRUvr#mGfTDZ?iY5|J zG>L$s$pjQlA)sg~0Y%dYD4I?{(F_8LW)e_TKtRzf0*Yo6P&9{tqCx_SiU=s0OF+>) z0*cNfplCh;MGFX_qBD~IEe=S=8+KnbT8h51Z$U0h#>|%~x-c0$pCv_$IbVvFu%&1z zTZ%4XOVKj66fI{<(Zy^jx`Zu7m$Id31sg>x2`E}cK+$Cc6s;zp=yC#z)(}v%mVlyl z1QcCCK+%;16kSC?(Ru=kt|p-98Ul(o5Ky#{fTC*&DB46o(PjdQwh&Ns9RWqx6GBCc zlKw#lB%_7h{aheLm)Y2wjF~S}v^^P=t1Lw~alRDY%$A~C*iv*WTZ(RDOVRCYDY}C# zMR&5L=q|Pt-OWbPJp>fpOF+?m1QhKcpy+-AiXI@K=s^OCb`ntZ5CKKI2q=1(fTBkT zD0-BDqQ?j*+D$;w;{+7#A)x390*am_py(+Aik>E*=ovz&Xj{^6<$z?gwLiUoqZEB) z_eFb?G4o}LUPuNbt4h&}oG(Q$v8Cu`wiLa>mZDeLQuG>Iie6_+(Hm?jdXp_hZ?RGI zHUUNN5K#0k0Y&c-Q1m_lMIR7Q^dSL79}!TrkAR~61QdNtK+z`z6n#oS(E$RAJ|m#$ za{`LKAfV_=0*byOpy+D?ioPMB=vzXl=((gn-vP<^#-8avFGYX3w?)58#>|%~`Y{VOVMGr6#d4Qq9bf6`kgIBf3Q(>lz^f?2`KuDfTF(% zDEfzhqJIe}Iz~XzaRQ3GEIn;UQG|e^6atET0*ayp6a@qnr4mpSBcLdafTDB)isA$m zWe`x5NkCCKLa6A6q`$`j$*5`fMF*v*nteqppA|D-rYI{b__U@JRpfjrs>GI}%4{jB z!j__{Y$>Y7mZIuxDXPJiqMB?es>Mc8Z32qw5Kwdi0Y!BQD5^(5QGEi68W2#_kbt5_ z1QeY}K+#DA6g4KGs0jf@ClgTAlz^gU1QazVpr{1_McD)twIrY@hk&A1giui;%a7J_ ziZ}_1GySU^o@nc=nE5hA?X!YLb)={R=SxvXwiI<@OHpUG6m?-sQCGGUox+x) zZfq&)&X%GcY!vk*pr{uCMZF0q>O(+LUjmBy5m3~hfT95e6b&Sx=u`rV1`$v+n1G@o z1QZP=plBEYMZ*aw8bLtONCJvR5m0m*0Y#@1P;>?%RMa-hALxK&G&MNwq^O+T7mdz} znJ-f`CM%fc{zc;ApQD|_`BHQ)TZ(eoQZ$w=MR{x~8poER@oXuYz?PzXwiHcdqi7NV zMUx3AnnFO)R04{o5l}RpfT9@$6wM@{sDOZ?Sp*c#CZK2z0Y!xb6crIrG?##)c?1-l zM?leh0*V$8P_&SMqVowTT0{sHot5RUb3iht*`EwKTZ-1(m$wVDV&=;fEzJsc)R&@* zIA4mEv88A^TZ%4bOVK54DY}#`MJw1+w301FtJqR>85>2b2`IXpfTA@76s;woXdMAX zR}fHiB>_cO5m2wWcxq|0aOMI5}yjqEqDtTVr#EdGQ*D&!wHP36D__K!R zHA{4>?RhN|7oXsHZ4xin^Slm;WJAyEk~rf;&+DGJuCeF!PJD5)=k-rCY3_N05(U|w zH!QI;$MZ%d{%-AgqZ2*adES`Br5!wPY~s~Uo;M*;v8(4zPMq1z^QI@Z_VBz}iLZKj zUQwcHU(cJLnBCv=7A1BK^t>gBe+PNq@wBC8{I7sNe&r6_D?g6jwJ2x)*ll|+Fy=7Hj=cz-FiYK zX@5QOZX zyM-c2`+G)KN0RmzMXZY??Z5P2A4%GOs=YCiwExz2OC)LkvE&Vrr2W@!H${^6pDW!K zN!ovJa#tj2|G~h0k)-{J?*}7E`y;y#N0RnuE_X+g_J`)4j3n((J?)Jo?T@Xz5J}pf zJ9s6Mv>zP55lPxl{@#fs?MF8sM3VNs_x+Kiee?7{Bx&FM`ZAKVZ(n>HN!s(zgOQ{? zfjAUN+9SZ<+xJGDdkWySBd-Tj`7bktk6xsMX* zq_NA+>8!EGMi-3{c8$7fl(S1aMdQ)98{IS}+BN7Njw*HBuq*CW-R$li?0-QcKkh}6 zkw)b!X87f6mOrg(GLoq3c_|IO4EHY!`{g~)uj2XTJ7sjv=$J8}qWgvFEotuLww{&L z3hsUFl~~0{Mn?Fa5jWGyd43uvW@MDh$js>Aexd1A|Kq*l?!C%fe1>KaezZ(oq?>k; z<#dt7Z!NvZ^14X9R|R)cPU^lQ{ zYPe&>8)gSX6!i{AhHcf`yjt!RyUQ-66uwt+(*N06ynO85+4m;6|4)hhUA~+baWC#| zrlLiQ>^XVa6ANc$7tR@mz|<`?D_X6Luc zEi9TlVM;-EQ9;4<@ssnW%q+~FG=6+;-kcfPIW2Qr=eBCuDknFmrN!nhHlJBAGrxI$ z-nc2vb6U1&-Q3>X!oB%F-jqFM=J@GzC*)_($QwU-%FO@YuSVg5!m^)mhlqTHedv+@gDOg3Te=9(~N zW|152PGe-RKDq8{j_*}4V@APD*WCRWV5Znbhskqyw?VN^zjY)CD*kUTLB-Ta5b-C~ z4YK?ib%Tm01VL)oAj`!dwWWJ(5~&A){J_m))CF+LnC0_N3OOAGcM>$L&?-B6S5@aYDP2_v%=Do#xIgoHA)< z{)D>jvtRt-dg*%Q^yO0AEBrG1l>9n!+?6SQ|Bmk6a&z6;ty|@WmyqK=7$@}Q(t7C9 zdX`>-`wX~un=p6Aj0NE(>3!SSyXG1Ku?as7J@n@GC0ECNdP_b|$%kyiN986^?o(O(M)zsfd2LHB%w0P^Xe+&c>(cAdtK^KFUVJEb#dU^x zD0A2KfAt%-cmBA!lRS4XH*->cZvM;(Q}Sl!PA`}_Df|Vx8_0clcehaH7SdH~Q+jQk zhVb1>etEEKS^BH%Sn?~$aiYCb`<$8EqxXp7^V|)sU!()A*LwfQnVwyxy2bzZKhWir zUXh-11wVH)7JmS|m52)c+Hb@@#b-~o-#f+c+EN$cDC?T^EV)kho3{9!dX!$d-tOk^ zF`{2iaW8?v2hQnGaxpoj_OJq#oKlSLSD+6IkP-^+zM=SolH&WN(wo)YRq3kaxa-2JIi;VCGB<8}oz4vqy0HuFQ2MEIpUCiI zwBm!6-tal4w|q{So8H|z;VGpzGPglaPyO2M7O;=hvE=%?&#$g-={;6!T~gc9>l5De z|Cf&~^w6aAD^~HRw3Jd#8B1jhwR6|46gYRLIZ(7W+XcB}$*sVzM!$A<$E7#5F1dZ& zXPI{|RRtKllo;vYE~%j8cR}e5&X*dyOVY);bGTr~JG_0|hb?}^eVTb&$yIV6%Qd@C z9_7Ah>-{;=-Ppy&1QmY;3%_vnDLLESyt>5FYXBhk8PeNIpt##N{0OD++?|noui^_Y zev^Zvv)mUJy;kxIaj3)d-Mz8hEzSu)D>>moUsX$~<&;`0;ay71eZh8@UpTp7PEpC% zNGF+V5#Hz}w|B``bN73&_+9KaDHh~D8{sQu2$bIBIiNcNLxB1Xkb(_0~ie1OME6{x6jQqmFyh-`Zr{~X{R5ZD3OP9h&GtKQ* zcgubk7fmUc*}Tv_!? zk}uXdJPIv+L|OVkvh;DJdqfJK@OOb-y%NVf1}%MfSmx0o4?#;G3i2BwhkJ2*m>7PB zBr<$FSo|rl2cddgTKr25fBTjE^7-vnf*RBIV02o^Js^)cOCJfAJ`hBA$xUDUsMG!W za!MXRmONH0^V_KOH$&+oJ#OjJ$9W~UVEACs>({GSr@D>pH%^Z^GwSx4F)n|?1ox18 z6wghIe=qTzv&sMdJIkJCXS)9#cP|kyWl{Oea-RDRX~~N{74KO-ZF$O?h}WZ|8+rDO z){D6BetJQN=7U=d?lEA9mzs z%BHCI%ki>r_U$QMnHOK*Fd+H%jIPX!@1D&i%WV7Bg8drY_iy#Wcdf$dd&S@2;*IXo z+&6j3y!f8`4sw|n-z)pw4f}S4`>t}C7vFt9y6lVpU)RR>+&4_hy!c*LnPrz(*>m4+ zDgIU4=R3-J5Uxcl(-D^9U*jN8$Dx63|X zcC4&pbvwE@*0ZDg$pzG?K)?t6oFtnGd+c5I?!H+K`+K2^s&_iL~{ zL&sa(O=SB49S^!sfbBnZY~{e%?xy2>_X7gk7wfpETDV`iA?%xL?&VwN1Dy>Nv>Vp!WV}>Ud>`aBtP|gHGZ8O2<0xhPU@`s^f%i;hwGI9X-Om zOUFaK!u_v~?fQnhmyV12hkK=tPY(?D>pG?l4tHf8hYSt(**dNt9`0>Ael#-N-{@HP z^l&%VapLH37wUM|S>b*}$6v>U`?!uBa>Lz6#|!hqeVLAX9d!GAys2Y+Vz{g7IBasb z&(ZOkso~zPw%taq{eN&(-ms!f-#P<8O1r9hny%JIxP|{d8QiFx;2x z_}rp!zpZ2D;&4~jam3Pa=jym|S-5Z3@so?g{ezATSA;u9$EmBreV&f@tq%9&I{v;U z-2U3|*yW1wI6%jXt_t^B9bdRQ-0$jGeq*?6>Nsjsxbt+}v?biP>UiM#aQ~>|iQB^6 zTF2?z!@WSq`)>~S6FMHfHQd2%;qjC^!sDqrF25_>SLpcCJ>h;|$Hb0s*Vgg$2f{sG z$1OX-gZFa6hHvUr&ZR_EdQ6{!Dlrtm7rmhWjcV zUwJ;-gG%aPQNx(ih>br{h^)g?o~YH+&QByLJ5fyKo=Y zvDv|JchqstPvKsyc)d?&p8DkLc*WU0l37>saJ|B4}@4s^g>XM}xMX*U|m> zwRo4)v9J4Kp}l>ij;q~I4Q*em<6G{>hqgb}v6}liqU}aHp6h;~XnUHDH@TlI+TNk# z_wGlGw*SzvrTbZJ39uR*GGGp9pmojx;mbz zK2gU)9hc~MxsIE3yj8~sb$m+4*L2*cF!t3WAjuiJa9V_TqQO8s} zx;G}Y-J$sXIj_(j-?+PL z^oNgC?Iib5^*=p8J1$KR=xR+M3>%bV;jufGd+ zdFF`A8|7Z-9QUd>-Cfq$GJ#j!Ly!M>zgHSZ{^NNB?>El9U)hg)U$2N)*ERdN*7>+| z-Rqp=UiE%)msi(b(F<>z?RMGAd&6Cx`M1lnXHHz+3imqaxL3VolkolQb$j7$%iZf` zFYiE^%PZ&J#^t#${UztPSG{`f@;(DenYUfzUN3ujhur1a?PS-_e*bcLx475sI+zE0 zNof}G+Gd8Y+yC3!?0@b{`hUD%`wkIrpliJFetTT7*Lhj)-mfvk9qr@Vi~AD)AJ^|_ znP0EnuW?Twc=cvhSDHJL2u*o!pW4EAte!ZOaw~+3rUY?K-q<)uC1Ey6zhgEpy8J zf4g>V>elVh#(ig`uDy(nFYYs_Z}^k_@Ph3##pPOg!F^2k5`^~&jlJr2&sl%yp(P^| zJA(nKgZ3WnklcIpP~Gu)$NxBXeDBfBNaFFSOEw(w5>>j#-S3z1a~+NN?iZa|;4bNk zvY#QhQzEI;?73qk?LzluCM6{}8nZ*}JQw{!_rX&JS98xr+>djEEQiNmZSOU-`q<(W zJL)brB`v7!e%q#`#V&K7t!Ol`?hx%S!>Y`bgMLA$(dclA1Im$U7zUnlKM zw_CaE*I7Hmw!3~^wBxqj_3NsgZrfeIQ?%1;yX)6YJ7(KmzwX+pw%zsXp&i(E*RQ8` z)V8~Ry|jJX?)vrCPI0@nyMBGNBevc3>#OY;q(!3*{TJQspMK2zG%Eg+{OLoSjA*~u zt?nI6$f?1Lj&iY(K{{1J25U;l5KRdgswpAEG$mxXri6^pl#r2{5;96tLQc~}$m!Y$ zIYS#EqqPxorZz&((niSH+6Wn=jgWJ+5pu3JLUOecGFBTQdD;jWr;U*D+6bATjgWk8 zgiO>%$RurqOx8xo6m5h|)kerP?NG=7{|9&br|)ogG|_>fkkRfQDmp!8a!kmq;0O1{ zVj;72s)WqZl#oJA2`SQ)khz)?GEY-N&eN2T`I-{4KvO~%Y9i!(ZGX(MF0HbO4eM#v@F2)R@nAuF^IvQir%tF#evnKnXJYa`@x zZG^1RM#x%igsjsJh0OHJxx0+?+U^TZv>+66irt@F5i>a^(Ug$uG$rJEO$phmiI5w#5wcAiAvbCxWV<#(Zqi1`&DsdL zMH?ZvY9r(}ZG_yejgULE5pt(CLhjN=$lclqxknoz_i7{LK5c~T&_>Ap+6Z|-8zB#B zBV?y`DC8YfDwGnbi8zH}FBji_YgdEmJ$Zy&R zIiih_-?b6)hc-fvY9r)NZG`-#jgY^!5%P~VLjKi8$T4k%9M=woeC!vw+dutTd+hN^ zv5@%pb|2zJVn)Zyh(@E4;A;2uI@6xb1QDHmg4^z4Zz{Wv+wNg`j9uGp_pm&TUCV9v zusoez({1;#JkGA+wtHBf!LIJMdsv>yuI9FTSYD1@)ou5%yga*#+xEPs0->@6cMTJS zN*3HzOcE+uaMv-5kY&ML$%=%e1$Qkg5fT>M)vQdYV8LC_DunVD+!d`#C}+W4(`tlF z7wj2MbwY*(cTH;$;uhRBtw~6?;I3&cLYf74O=}Zk7Th(hLrAsYuIUMcz=FG`bqP@m z?wZyk_!itXtxrgC!Jg|hAVe&!aZfO*W881`R zBogd%-+(AqbTa2lQB$@QHDgOrbG8(Wp35x>&ziW*B%Gb1%H5;I?>XhRv&0YzsMP&9^sqH_o+I+uW=Tmp*5 z5>S*!K+!k?ipCRAG=YGkd;*Fl5>PaWfTGC+6ip$ZXet3k(+DV6ct8-N$#7*#rH);oG(Rl*-|u*Ek)6m4Tm z(T!{rZ6~1UCIX6XCZOmR0*Y=Wpy)ONif$*M=nevk?j)e-E&__~CZOmZ0*dY>py)mV zigplCbUy(_4-ioFAOS@?2`GAqfTCRl6g^A`6DEODS9LlGhe3Y z@knsEh7|4Ld?|W@Ek#eVrRXWP6g|zBqG#Arw3jVK&$6ZHIkpr%&qmP;1QfkUK+#JC z6unG9(JKTLy-GmQYXlU%PC(Hc1QfkVK+#(S6unJA(K`eby-PsRdju4{Pe9QJ1QdNp zK+#786zwCRXg>i(9}_}Fk45}y?kDQ;sditqTZ%rlN7tW3V&=;feI5xqx<9d4d|&hh z=S$I-Y$^JREk$3mrRW>B6n)E^^g5l~d0fT9Kj6g4EEs1bqtq7w-yI*AY}3R3)= z9FX|=_6^0SfTB(W6m=$`s0#r_T?r^Ug@B@N1Qc~Apr{7{MLh{9 z>P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_WPm4Ko_giz7RDgO5kNW8xLGda$(Eu~Y$-a8Ek&oZrRWT{6pdy}(V1*1I*TnuXR}c> zhJd1T2q-$2fTCOiipCO9lt)0(I0A~s6HqjPfTDZ?iY5|JG>L$s$pjQlA)sg~0Y%dY zD4I?{(F_8LW)e_TKtRzf0*Yo6LPbMU{FV+#e5&0S4U?ig`-(OvC1$=%(Y%yk_=!?< z9_LHZe6|!VU`x?LwiKPumZC*$DY}3yMHjNAXfa!gmatK@lz^g(2q;=cK+$pniY_Lg z=n?{oE+wF71p!4X2`E}cK+$Cc6s;zp=yC#z)(}v%mVlyl1QcCCK+%;16kSC?(Ru=k zt|p-98bYY3D8--WfW+I`w}|FSQFZ&S~DY~95MO)cY zbOT$8wy~w?Mz$1fXG_sdY$>{#jiOr!D7uw^qT2{4x}AWcI|wMclYpYT2q?OnfTDW{ zD7u$`qWcIa+Cf0k{R9*}KtR!h1QhKgpy(k2igpoD^e_QMj}TDwC;>%}5kf`Rrue%Z zkob@GUB^vQbcWp*?M{iAFH`hnO7QW?QuGw(OVQJ8DSC!2MSIy&^ekJ7o?}bV^K2=4 zfh|QZvZd%HHi}**py(9>ie4q4=rsb0UMHaF4FZbZB%tUm0*c-ypy(X}iryul=sg08 z-Y1~w0|JUZB%tUc0*dw#P_&N%2#fIz>n9nf?<}G|(Ph zf0hz6U#94*l%PR#Df*i8rRW>B6n)ERxEfTH6B z6uG~gZnL`?-A~lrw`%OCu@M4_QV1yW2`GvZP!teCMPH=&{T-0_<91*4r4$XeN7t!- z%zT-mxF1Z(mZA*Km!eFz6qRF3QF*o$RbWd|f-OZ!wiIQtrKloXiYl>DRGEOHDg+c& zC7`Gp0Y%jbD5^m~QB4AhY7tOWn}DJ^1QeY>Kv7)+is}(iRG)yN1_Tr}B%r7f0YxVg zP;?RjMU4q4YC=HK$%If*n(wc1K;m!PL!op(e5U`h-4`|WW9G{gW&6RsIa1V;^Q9<< zEk&)^Qq-C)MQzwp)Rrwp?buS(o-IWk*izJyjiOEj6m=$`s0#r_T?r^Ug@B@N1Qc~A zpr{7{MLh{9>P0|NZvu+?5Kz>YfTDf`6!j;dXaE640|_WPm4Ko_1QZP>plApIMMDXp zqUOH;jsp^3Vh@E{NKr4lFB;~@%$F$|%ZJeS*?$0bnM@rEr z_Kobhe$0HCq6L1?xt$a(TZ%4ZOVMJs6fI#((NeY)UBs56Wo#5J zC!pwJ0*Wpnpy*NpidGO%w32|LRRk1WMnKVO0*WptplA&NMQaHtT1P<96$BJrNkGw6 z1Qe|&py+A>imoA`XafO78wn`7mJljB&-ceVAn~DgUo>Bey4zQ@O@7RLnWF3cU}*;_ z+RFJ-bOT$8wy~w?Mz$1fXG_sdY$>{#Ek(DmrRY|+6y3%~(d`5j-9bRnodgu!ML^Nr z1QgvvK+(Mf6x~Na(GCKN?kAw=0RoC1B%o*~0YwiHP_&DHqK646dW3+YM+qo;jDVuu z1Qb0^K+zsTsA!At-{OG8+nA#3q^OIHC;XWCGDXk$!Sn7v=q&ze>|V~7qG#Ds^c-7? zo@YzZ3v4NRku60pv8Cu`wiLa>mZDeLD0+>6qSpy1dV_$XHwh?ui-4lH2`GApfTDK^ zD0+{8qW1|X`hb9<4+$vxh=8Jf1QhKjpy*=)iasHr=u-lU4iHfE839F~6HxR8Ayo8~ z?;mtP;;Zbtj!#Qb3%f7+(vO)hQ}nGLlyiSePqCu!IA4msXG_r!Y$-a(mZBfoQuGsB zihgEG(IK`J{lb=_U)d-+OhD0Z1QZ=1py+o3ivA#==qLe2e-cpi7Xd|o6HxRI0Y(23 zP;`udqT>VK5a))gn*(H0*ZVBilPJ*1q2kO5>ON)peT(HD*D>@TR9-{mG*%8 z8!7t0p7y6lW9G{gm5T-=yGc=b&X=MJY$-~xr6|dkqAa!)Rb)$1CAJh*W=l~OwiH!m zqo^7IMb!x?szE?eO#+H)5l~c{fTB7C6rDgoQC$Lx>Jd;>pMatU1QazSpr{c6MJEza zbP@qYjR`1fLO{{U1QazTpr{!EMa>DJqKv3N-vNmav-_gVX!uP36?=5uA{sMarl?gk zxVDEBwdQ;&YQvVIwrnYC$Cje@Y$@u%mZFYqDeAcU1*R|1MoA)u%m0Y%*j zDC$8#QBMMjdJ$06n}DJ|1Qhippr{`KMg0jV8bCnNKmv+RC7@^!0Y!reC>laQ(NF@4 zh7nLSoPeScgiuk-sK3Vni63w?nj=LW?T%?=G-kd`(HYU;(_T_En)9XTOtuuA#g?M8 z*-|uyEk)s|Xe?Wb^4KUEM?led0*WROP?S$V(L@4@CJ|6HnSi1x1Qbmr zplBKaMbil=nn6I(Oah7u2q>CGK+$XhisledR7gNk5dlSW2`HLJK+$=GP|;~oKib*_(U|!%MT??AqrOsf0q0B6g={HW%$A}hY$;mGmZFQ;QnZXMMa$Vz zbTM0sE@7kSQUZ!r5Ky#|fTC3d6kSF@(P{#UE+?R94FN@K2`E}eK+zQh6kSO`(NzQ# zttX)9Y66O`A)sgj0Yw`LD7uz_qD=%8Z6=^-3n5grFzOF3Qgkz0if&;`(XDJLx{WPGx3i__4z?8C$wtv#1Qgv( zK+!z}6x~Ze(R~CI?I57&egcXfAfV_$0*ZDLQ1lQ1MY{+ndYFKsM+hi-lz^hg2q@Z3 zK+)p_6zw6P=m`Rfo+O~?DMF}dYt&!ofW$l7ebEh4^qM`oemWX6U#94}Xs~0T6g|)R zQuG2_ie6+((MxP8dYLUnudt=)Rkjqp#+IVj*;4cd8%1vtQ1li7MQ;;O^bP?nBKE8l-C)o3zlp}omnr%o8vHRxiVkwV6#dASqMz7O^fOzE z4zZ=^7q%4r%9f(TY$^JUEk#GzDEgg%qCW^II!Zv%p9B>BML^Nt1Qh*4K+(Sh6dfa= z=r{pIUZAJ#D2fnJltMs}Pe4(WfTDnaqErHkVgwYW5m1y)KvA54q6|W)=)0(2Yp_$a z(Y~U6FGYXaSG3F^X1+{OA_%$;m7*l)OHmeEiYl_Ds1jR>Dzl}i3R{Y*vZbgRTZ*c) zrKkoQMKuX1szpFiZ32qw5Kwdi0Y!BQD5^(5QGEi68W2#_kbt5_1QeY}K+#DA6g4KG zs0jf@ClgTAlz^gU1QazVpr{1_McD)twIqa!$_M^92PB@bKX+Xr2%qT>u{)-mAZETy zQQII`He8C@alRC_XG>8BwiI<_OHn7b6m@1xQ5Uupb!AJ@DQqd~#zs+h0*ZPNP}Gxv zqFw|P^(LUG4*^Ae2`K7EKv91JiUtr+G?0LzQwb;ioW7$%a$CjdTY$+PgmZAx46y+08G?9R!Ndy#4CZK2v0Yy^@D4Iq<(R2ce zW)M&`lYpWE0*Yo4P&Au>qB#T<6%tTXL_pD80*dAlP;?#vMe_+LT0lV2LPDr$bm0Hw zfW+^xheBsc(ZhCMbbb&sU#4hr5L7r_ik5J`6fI>-(M4=2TE>>5S~3ebEg; z%zT-mn}Xo9(Nc6X=S$HoY$>{xEk(DnrRa9H6y3p=qC44AbQfES?q*BTJ!}-+OF+?m z1QhKcpy+-AiXI@K=s^OCb`ntZ5CKKI2q=1(fTBkTD0-BDqQ?j*+D$;w;{+7#A)x39 z0*am_py(+Aik>E*=otcv_7XxxHwOMf2PD4Vp6PFwqJ~E5*&t@VOwo%$u=y-0dWrL; z=w-GPy~38FSJ_hZ8e589XG_r=Y$twiH!oOHmEB6xC!)Q7yI< z)n=op4gp0c5KvT?fTDT?6xAo7r~v^*4GAb}L_pDr1QeY_Kv81?ikc8mbTR=&O$jJ! zMnF+>0*YD?P?SwTQA+}fatJ7DMLJM^2;`iI5>#Wr9nSM2U+TSKMX1+{O zhtyz3o)mTDd@1V0mZHvVDeA(OqONQyI)yDo-Plspoh?N@*izJ!jiO!z6!j*cs1E@} zeF-S)M?g`30*VF@P&AN$qEiVd8bmJU5KuIffTCdp6b&b!XaoU8BMB%PML^MM z1QeZ4K+zcl6pbc?irS_6S2`f^FYR$rdnsyQ^QCAR=S$IYwiI2=mZD48QgkU>idL|tXeC>U zR`)BML^Md0*bCCpy(O`iZ&2Xw2^?K zYY8aYL_pDI0*bZ}P;?yuMb{Hhw3UFO8we=cMnKVxgiz6vRKLzdr>KiPpk69P7Zg8X zOO2T?Q*>);&~365-NyM+bURy$?qEyNoop$(i!DWWv!&=BwiMmVmZJOEQnZ7OqWcLb zdVqkU2MH+JNkGv<1QhKepy*)&iXI`L=urZS9wVS=HvvVD6Hv5=fTAY|D0-5BqNfNb zdYXWuX9y_TOF+@H1Qb0-K+*GrP|?k){sadk9=C51-6BQH?Y`)R)R_4)MX#g=7f+R< zS2uf1{gDpjGvZd%PwiLb1mZEpqQuHocir!DEgRyqE84Y`jmj80|XR(MnKW$1QdNiK+%^36n#ZN(bohNeM3Oew*(Y@M?lf{ z1Qh*1K+!=$sOY6s{|*Nv{;GXNds&J$+0*_XQ)A}K6#bGKygXfse&u{AI?R@$-`G-g zge^tCv!&<{wiF#@OVOWfDf){oMSrtV^bY|={}NDijDVu!1QdBOJ#9x(gn*(H0*ZVB zilPJ*1q2kO5>ON)peT)iqI3d^;sg|B5Kxp!Kv6jYipmpERDpn^1OY`!La6BHRR53z z65nTcKZm3!VPDa*Vlne&imJqdWPub_<$Nis#+IV$Y$>Y2mZF+$DXPVmqS|aJs>7C| z6WCHzmyM!&1QgXLpr`=>MGXlkYD7TMi3Aj#L_kqv0*aatP;@c@MNJ7PYDPd&a{`K5 z5Kxp&Kv7EqigE}jYDGX%YXXYe5Kz>XfTDJUP*J6r-_8Mvcd%#rm1E&E{ZxCV-#!*I zU#6&YEI4Df6m{WzDeB6WqEpyX)Qv4g-PuyqgDpip*;3StEk(WAQq+fyqP_$a^&_CD zKLJGp2q+pzK+&lL6b&MvXfOdqLkK7uNC|;{U4g63&;ROW9Jif-OZW*;2HMEk&2H zrD!!f zP_&tVqAdgzT}MFC^#l}cC7|dA0*bZ~P;?^!McWA|x`}|In+c(!WidZ(o>S!hL3J;> zT#6pEhuXKqV&=;f-4P3#%$K4&IbVwIVoTB8Y$>{jEk*aTrRYAk6zyP3(fw>GdVnoO z53*6TlYpX!2q@Y`K+(el6g@&f(W3+uJw`y$ZUTxPC!lB#0Yy&`Q1m1LMNbh>^fUoQ z&k#_wmw=*Y2`GAwfTHIKD0+c_q8AA$dWjG!x-I4paX{kjdQuG#Eir!{R(K~D@dY3Il@3E!meYO;Rz?Py9*(mymfTDc_6zwOV z=wkwkJ|Up!Qv!+(5K#0P0Y#q^Q1k@>MPCw7^c4X`UlUOD4FN^p5>WIV0Y%>vQ1k-< zMF$Be`jLR5p9m=WnGh;^HRi8(K;n;^qSvHohus$)ip9*ADf%rI>|7*8M>t=KerHS3 zA8aW)%9f%(*;4cuTZ;Z>OVK}UDf*W!MaS4EI!-{5m!_xfD2fnJltMs}Pe4(WfTDna zqErHkVgwYW5m1y)KvA54q6`9xG6^UuM?g_|0*WdSP?R8`C`mw376C;S2`H*W2o?Pr z^FMMx;>+y2j)$dazLBb&7BgR_sCruP_k~hagY%`RCR>VXv8AXsTZ-zirRW5<6xC%* zQ9ZU4)n`jl12&2p5>V8LfT9x#C_0INqQ(RiH6ftrWCDts5>V8PfTHFE6ty6rD4T$y zmIM^#5Kz>LfTGp}6ty9ss4W3S?FcApPe4%z0*X2kLPb^6{JM*sqWkP8Al1^sXZo$| zD_Wcf_zzHBM#$Cjf0Y!nS3 zplBcgMW+%_G>Cwr!2}cyA)sg|0Y$?IC>l;c(Fg*HMiNjoih!ci2q-$8fTA-9C>l*b z(U}Akokc*=*#s1gA)x3S0*cNhgo?VP`4b(G_-KRERf>MH`=Z>mnE5hAaMVGUs zXboG6*0QB&9b1a7U`x@JY!qEZK+$>vimoQ0=o$iwHV{y>k$|FW2`Jh`K+$Fbinb6? zbR7Xj*Aq~*m4Kof2q@Y{K+%l^6m2J<=q3V+ZYH4U76OWHC7|dwLa6AHH2+rzB%Wb^ zO~|EERNWq3-<}pTU#95pw4mY&DY}RArRZL^6y3*`q8)50x}PmY53r@^LADg_WJ}RQ zY$@8sM$y9r6g@&f(W3+uJw`y$ZUTxPC!lB#0Yy&`Q1m1LMNbh>^fUoQ&k#_wmw=*Y z2`GAwfTHIKD0+c_q8AA$dWnFdmkB6(g@B@038A7p)BFw&NPLK!(YvH*rhP?wEiGog zOwn6u!I`V1=xxrIqIcL*^e$V9-eXJA`)n!tfGtHIvZd%FwiNASOVNHdiasWw=o12p zJ|&>&00Bjx5m59w0YzUBQ1m4MMPCt6^fduR-w;srEdfQ}5m59!0YyI$P;`)hq8|w; z`iX#|p9v^BL_pCm1Qh*B2o=4N=3nT5xUXjp&YMz{W)HOwr^U>dDf%NV*t%MZj&i;f z{mGW1zt~drH(QGSVN21!Y$-a%mZIZqDe}_wyj_YSY!sysP~;O(6eXZ2AfPCffT9=y zMQH>Sr4vvTC!i>UfTBzSipmjCRGxsM3Ir4-2q;PtP?SYLQAGlZDiKgrnSi1y1Qb;z zgo=)&`FkCZ_&&S)`CW=8*r=8sGhe2tR(kN&8Y!yH`BGGeEk!4=rKm1jit4eYs6JbY z8nC6PAzO+Xv8CulHi}Lnpr|ncMNJ4OI+=i?rUVo0Yz;HC~8YUQ9A;P+7nRJfqlyY(J%svh7(XUf`Fot1Qd-Tpy)ILicTk>=nMjiMiWqUCILlf5m0nC z0Yzg7C_0CLqH_r-$|ay^ECEG%giukpbbpuw65nZeKi#FMf<3w(mmV`;rf6b%F#9Sg zn#B21G?^_$Q`k~8l`Tcn*itl|Ek!ffQZ$n-MFngrn#D%ZYyyhr5KvS|Kv59^MRN%# znnys{$jiPG^DB3_k(MAG_t|g#o69Gk=2`Jh^K+$ys6kSh1 z(N+SAZXlp&8v#W(5>T|AfTEiSD7u+|qFV?kx|M*U+XyJSoq(b{2q?Of5Gq=k?(cU% z;(gqVu9Bjg><=5=l^!!+rs%%(;NJ~Ww1e}d=zg{oJ;0Wt2ia1zlPyILv88AiTZ$fL zOVJ~2DSDKRqQ?j*+D$;w;{+7#A)x390*am_py(+Aik>E*=otcv_7YI^ECEH&5m59z z0YxtmQ1l`JMK2Lh^fCcOuMkl5Dgi~W5m59x0Yz^RLPhta`}H?EMK{WIb0YyI%Q1mka zMTZC|`h|d^UkNBWOhD0Z1QZ=1go@ry_a{3b@dxcssl6jbZ`zM$e@~B@FH`hada!bf z6#dQlQuGg7ivDFw(J{6Z9cN3C7uPd)DT=VAD1|LWK3j^SY!n3q6r~bS6eFN0jew$b z0*c}U6lD-llu1BQIRc8x6HruvfT9EeMM(mRvIr=uNI+2~0*WdVP*jD0qN)TGRU@FN zIsrvB2%(~*>Ha+qNW8B-F8Wi7*4uqi&3MdwnW7Wo!RyycQC-fLqIzs8s?V0925c#6 z$d;l;Y$-aCEk!4>rKmAmikh%dbTR=&O$jJ!MnF+>0*YD?P?SwTQA+}fatJ7DMLm|v;RFl>d(F8)MsAt^okbt7a1QabHplB%pMHdlJw2XkFU{KX1+|(ns~77W+__B`BJowEk#$b zrRYkw6kWxZqV;Skx|%IT*RZ8%16ztVvQcy`0Y#e#DB4Uw(G~)Vt|Or6dIE~J5>Rvl z0Y%#gD7uk=qU{6}-9$jq%>)$PLO{{21QgvyK+)|46x~5U(VYYo-9H+=mi3b zUL>ICB?5|GCZOmQ0*YQGpy)LMie4w6=nVpj-Xx&tEdq+(CWMN1#Qn_MoT4-APlntt zMOk)V^iDixzD&^v@u2w~QuHC`OVLMcDcZ-DqWx?s`j{<6pRlFqQ??WxU`x?wY$^Jj zjiN6IDEg9sqOS-j`kH{EZwM&*mVlz~2q^lVfTAA=C^|?$(T@Za{X{^~&jb`5BB1CO z0*Zbmpy)6GMZXbHbcBGS-w7!CgMgx=giz6YaessZ63;U@?@LjxeR=yc9y4F2=-+ry zc$X9%<9sPP&XyuCL(kl$D8iPa6t)!kY$=Mer6^!aQ7T)CVr&$p5m1y)KvA54q6`9x zG6^UuM?g_|0*WdSP?R8`C`mw376C;S2`H*WKv87^imDJ$RF#0DY6KKjC!nYX0Yx0Yz;HC~8YU zQ9A;P+7nRJfqPkS-DFhUCBcP}|0YyCsDC$WF71hn~KXE|f zr`Y47dKuv}{jGLi)GH%qzD!ZSjNtfvQq-UGrDyj5m0m)0Y$3`p`xi7{!|Afo@+nGpC(0b+K)pn&xn~XQ*=c}aM?~Nx{~vy z=qk1pt!GQo)odxchAl-K*iy8SEk)O|rDzjdiZ-)Rw1t48>j)^io`9mQ1QgvsK+!e= zif$yJXgdK#HxW>DGXX`n5Kwe00Y$eFP;@&1MRyQTbSD8tcM(u@HvvWW5Kwe40Y&!_ zP_%;(Dq5T2-{*kD-?yKDtdpWq_7&~^jF|Z{MGs{JZ|;(!U7RmP53{A{5w;XP%9f(X z*iy8cEk%#BrDzXZik@Ig(UWWxJw-s#(*zVfLqO490*am`py)XQik>H+=mi3bUL>IC zB?5|GCZOmQ0*YQGpy)LMie4w6=nVpj-Xx&tEdq+(CZOmY0*c-xpy)k9sOZ5A|91x@ z-q7Iel%jv_zUcjonE5hA`!a&6k4n*g&X=N(*;4cgTZ%qqOVI(g6n(~)qR-h<^aWdr zzGO?$S8No0O+e8%1QdNsK+$&u6n#%X(GLU^9VDRWM*@m|BB1DJ0*Ve1Q1lA{MZXeI zbeMpm-v}r=LO{{)1Qh*2K+#bGivA>^=r00_{w9QqKFsjDI3V#)?9uf{QZ&Fw{gV+h zU#7^*49?jtMUhNBlb50twiNknDT=bCC}2xbDqD(TY$-}(OHn#oisEb(We`x5NkCCK z0*cBLP*j0{q67g&Ndk(p2q>yZKv5+EiYgOORE2<|sst2OBcP}{0Yxyc2o)X6@Go*e;v?-(%pRAbR_<-ldYLivWr`YQ2HW>Y(TSWdMJKVP zs4-iLny{tlWVRGFWlK>rwiGpIOHm896lJqf)RKUr90H135m3~cfTA`86tyLws2u@C z?FlIAKtNGP0*X2jP}G@#qAmm!btRza6atF65m3~ffTA7*6!j#as22f6y$LAlLkJZ$ z$n;-uK;rM(eNn^A@R|O}nQrvWjF~S}G%z#x?nx;+mGh-&5L=1{v!!SVTZ)FVrDzyi ziiWeLXark|MzW=76dOgS5m0nG0YzsJP&Ar=qB997I*Wj!vk52~LqO3v1QeZ1Kv6CM zMPmsl$|Im?905h+2`HLCKv6ycMH2}qnnXa+WCDt&5KuIg5Gv}Q>6d@XDH>-#IvXHG z@4B}|r)9>>mnka946>h*qFJ0TMYGvbG>0ukg={G*VoT9nwiL}{OVN33DVoogq6KUe zEhM1md;*FV5m0mi0Yw)QP_&qUq9p_rEhV7nA_9t*5m2<8fTD{DD7u7zqDu)VT0ub3 zN&<>j5m0m)0Y$3`D7u`0qBR5*ttEttW@P%K9FX{(_JDe(6g_TZU1rRDnWFWX!Q5x1 z=xWZFqHEYvw1F)}8`)BHEnA8T|A zfTEiSD7u+|qFV?k`hSSK@93!NxNY})vS(+Kfn+A3cMuSe8ahbtDj)(1DjEWW4uK>f zAc_hqB2q*}5k+iRu!GpUVnId4-canKqKIO{^ZU-euOvRtde=FBylWlS(w+NCb~0o> zOlA@iwh&Ns8v#YP6Hs&q0Y!HbP_&hRqPqwvx|@Kadk84Hmw=-C2q?OrfT9NoDB4B{ z6WIV0Y%>vP_&f-~Qq;>H>Hk|fX1+|3 zpA`(=B}LJ!|31^^g5l~d0fT9Kj6g4EE zs1X50M-foem=G$8Wcf24koY!(la>`eMyukU7j2RiGhe2tc~)@QYf{vL^L1Nv3|op? zvZbgMTZ&qOw$KR|1N<5m3~f zfTCjwDC$8#QBMMjdJ$06n}DJ|1Qhippr{`KMg0jV8bCnNKmv*e5l}RkfTAIUP|?v@ z{{0R}yoJGOCPl^e;qADrnE5hA!?J?6c1zK4&X=MS*-|uuEk!4>rD!Buibk=eXf#`j zPG(EdDQqbk!$#3q0*X#0py)ILicTk>XdD4WXAn?yCILnH1Qd-Yps0X=q6q{PO(dXb z5&=bp1QbmsplAvKMN~3k!ue8E%9f&eY$=-0mZG!RQnY|AMGM(dw1_Q5XS1bfF&jna5Kwe3 z0Yys)C_0aTqVowTx`2S9r34f$BcSL)0*Wpopy*-(ik1^lbO`}PD+nmMlz^g@1QcCH zK+!4!idGX)w1$A9wFDGhP6!pv$?|(SAn|njtm9lMy1{OX)@8-amnmAG7390mA*Fuy z{?(i>Mc1&UXaie{u4PNnMz$1P$Cje&*;2HLEk!r5rD!u7MK=;qbQ1wZHxp2F3jsy9 z5>T{-fTG(7D7u}1qB{sEx|4vStppU^ML^Nr1QgvvK+(Mf6x~Na(ftGzJwQOwHUf&a z6HxRZ0Yy6qp`t6Z{ACVEyqW!7$E&1hw>{E-C@W^ZOwnUm!7cAf(c_#iMNhD$=t;H| zJ;j!yr`b~U3|oqxWlPa>Y$WIJAyo88 zmjAK?67OJt@A^?G`pa&ZKF*4nFH`hcR`C7%QuI0JOVK{I6n(*#qA%G}^c7o*zGh3& zH*6{TmMul!v8CvHHj4HWQ1k-5K#0d0Y!fiQ1mweMgI^`bcBGSe+ek^vh~0mMG-=%=+i7e`GHeZ#cqrC zO3@hmh?bTeGhe1CJv+$zNQz>dFGU$_DavF^QJgJBmDo~LnJqR zfTBhO6dgrCQDXv%nh;Rblz^h638A8BwttEP60dD=g6!~-zPqRG9qIPU4%417Wd$tsHU`tU)wiI<@qo^|hMO_Fe>PkRSHv)>f z6Hs(40YyCsDC$W-Q7;0DdJ|C8hk&BK1Qhinpr}6qMFR*Z8c0CVAOea86HqjSfTH6F zC_0{iq7w+Aq88cyMh7JRntj&s7%3WRq=sh4%$F$|ksUm~SBg&Jd?^~qmZDK?DH_d| zqLbNDbP8LF#;~PmEL)0BWlPa%Y!sbNK+!k?iq0UQ=u85N@(Cy!Pe4%t0YwuCD4Iw> z(If(j3JEBhOhC~T0*a;*P&AEzqUi(_%^;v?CILmW2q>COKv59^MRN$DqT$*8=MG4` zsr|j{6QyXH-MgNf9W!61XkK>U?~|hWoG(RZv88AMTZ$I4rDzdbiq2+B(PFj~ox_%* zbJ8N;fh|Rw*-~^PTZ(RCOVQ126x~8V(X9j& zZ6ToOHUf%nC!pvK0*dY=plB-rMRyTUbT`t_GddF@nZX|<26$ByxkT(njJG=rs&D+VD;Bh^c3ey z(bH@xdWJ1U&$6ZHIkpr%&z7PW*iy8UEk!S~rRXI#ie4t5=oJErb`enYDgi~W5m59x z0Y$qBD0+i{qBjXBdW(RfJp>fJO+e8*1QfkXK+$^y6unPC(FX(+eMmsjM+6joOhC~m z1QdNr2o*h^?Qe5H;urW1&J$8J#Kzw2nE5hAUt|Ywe=9{_a=sLO#g?M4*;4ckTZ+DA zOVM|1Df*r*Mf=%O^aERpeq^KQCjyEN5K#0p0Y$$MP;`)hqF)IpIz&LxZv+(mPC(IN z0*d}1py*EmivA*?=x+jw{vn{~2mwX^5>VtN^spU85dwx!X z#s+7f6z#JSBx2^v6lErYI{T$4&iPVQi7iEy*;16nmZEI76eZYFlw?a$4qJ+H*-})6 zjiRaq6jdXjs5${fH3%rGNkCC80*Y!AP*jJ2qPheW)gz#&J^@7y2qHCZK2t0Y%3VP;@*2MJEtY zG?aj%VFVNnCxnVxCH#vVkoYt97_GGw9ZWr7OT^5VDH@dswj7Y6(VQPaYfTGz16crIrG>3qqxdapy6Hrt_2o;@_@OL>N z@#pQ!_#>t0T)QnQO~lNXDO!*Se)vU-7IMB6En-X2*=#9V%$A~a*iv*ZTZ)#jrRY4i z6rInOq6^q4T1r6CG6IS&B%tUb0*WpsplCS(MVAmzw1R-5O9?1iNkGwM1Qe|zplCG# zMQaEsT1!CD^J&}l+FH`hPB3Ssl6g|uN zQuG{Kik@dn(F<%T+R2up7uizu5?hL1W=qj4Y$@8sM$xMT6um}3(dz^h?Ixh;4FZbZ zB%tUm0*dw!Q1mtdMeh($^ezEK?-5Y+J^@7^5K#0X0Yx7XQ1meYMV}B*^eF*FdkHA| zjDVug38A8=68`lLNPMe3EPGmt=Gkr0zC_G?nWC=~!IOVT(KnngMc=Ze=sUI)eb1Jn z{cI`vfh|QpvZd%JwiF#;OVQ746#YU#(Ln-=ekGvj5CKKM5m59y0Y!%iDEfndqCW{J z`ip>~zX>S%hk&9Z1Qh*CK#`Z!!*&!!2q;P;pvWhnC`v$4KtNGC0Yx!FsOZat|Ahk* z-x4@DUrEtayDiE{#>|%~s+0*YD?P;?9dMJ)*^YDEYY#gqOq4oLisOb4e@GJK?8*X~`nPR7ia zDauO*CmfNY_M9(89oSOTku61?*izJ)Ek#|}Qq+|#Mcvp^)SWFw$Ffn>gMgx*1Qhim zpr|(iMSTb;>PtXTKLU#S6HqjOfTDo}6b&MvXfOdqLkK83j)0=$2`D;&fTE!U6b&Pw zXgC2yClXLJf`Fov2%)03Nq>$55+7@~MeU^Mh>elSnE5hArzC^5p1p#0UUUrSOVL=i z6rIYJqSM$?bUIs##<8X747L=V$(EvgwiJzLqo{y@q6q{PO(dXb5&=bp1QbmsplAvK zMNq-ZhcOVK%ODLR)eMN8OHbRJuZ&Sy)} z1#Br=%9f&KY$>{sjiQSPD7u({qU8h>T|z+73Id8QC7@^}0Y#S)P_&AGqSXWxts$Uj zEdfQB6Hv5{fTAl1D7un>qN@lfT2DaH)dUn>LqO360*bCBgo+j>{l6WM_yqgh^&%-c zXtzZhlQHvUif%{-^#Uo{%=uDuBU_4YVoTA@Y$>{hEk(DorDzLVif&^|(d}$0x`U0P zI|(S-NKL;c}&u)G;Nzudh813m~%zT-m=aa$2 zm=wLh`BJo#Ek!S~rRXKL6ur!rqF2~bw2Li8ud=1+HMSJJ&PLI00*c-spy*8kiryli zXb%BJZxc}T4gp2)5>WIW0Y&cT|4fTGU`DEgd$ zqJ0DueL+CcmxNH!vq^us0}^j+w?)rMk!Pg7O2*8WDf%uM+@2{#-*dhc?Pp8T4{Ry= zku60(v8Ct$TZ(>WOVKZEDLTlOqF>o4Iz&LxZv+(mPC(IN0*d}1py*EmivA*?=x+jw z{vn{~2mwX^5>Vvj=wUmGA_Nqr5m4k4P!uJgC?KFHoq(bk0Yw=E6lD@n6eom=zDfG8 zIUsTSF4*X|QZ(8g=~v2$nJ-h6$O(R`Bt=Qim!cfD6y>s|s0v$(s^^g5l~d0fT9Kj6g4EEs1X50M-foen1G@t1QazTpy+4< zikcBn)SQ5#76cR>LqJhW0*YD@P}G`$qBaB+wIzg#vU2>Ym7Svg_7#xqobZwUA%`d0 zE+=NbOi{<2pi{OKb>e&}>dcm+E^I04%9f&TY$@u_mZD?XQq+SjMLpS4)QgRx-UJl& zA)u%)0Y&`?DC$o@(EtL91`<#-h=8KO1QZP+py)UPijF6s=mY|ah7wRTjDVuy1QeY} zK+y;SicTV+Xe0qeqX;M(O$ZgW&+$)lK;lVzjMhPl&a->hC+Eb>mnk|mCpbGPMW=DT z6rIkNqH$~~I)g1mXR@UzpDjh>*-})%mZAx4DVoSe(If(j3JEBhOhC~T0*a;*P&AEz zqUi(_%^;v?CILmW2q>COKv59^MRN!!noB@YF#$y-1QeALP&AK#qWJ_Aokc*=0s@K_ z5<*2|a{L<{ka%mmEgCCDU)rZ27v;pvmnk|oCwMwnik5J`6rIPGqVw5ObOBq6ma?U2 z8C!}jWJ}RSY$>{!Ek(=OD7u7zq7?)bT}nXFN&<>5BcNy%0Y$3`C|W~6(OLqEE+?R9 z9RWpG5Kwd_0Yz64P_&+aqN@ogx`u$F4FnWjOF+>^0*bC9py+x+sAzGH|CIw0ztnDi z&XJ;TY;4MjnJ-gxQ%(@8CPg=Mz7*ZUmZDqPQnZCFMYpk~=ytXg-NBZkJK0jSl`Tbg zu~Bq40Y&!^P;@T=MfVXpy){gik>2%=xG9qo*|&6n$W~MbG8L%$F&8 zF((*SLyBJFd?|XFEk&=erDzvhie6<)(Q9ledYvsryV+9o23v~WWTWUU0*dw!Q1mtd zMeh($^ezEK?-5Y+J^@7^5K#0X0Yx7XQ1meYMV}B*^eF*FdkHA|jDVug2`Jh}K+zWj z6n#lR(N_c%eN8~oH-u2p3pswV0}}t*9_jCtqA?Cn^xK@6`7%X6{H0 zm!hB8QgnbVML)Bp=ohvW9b`+~zX>S% zhk&9Z1Qh*CK#`ZLhwUhe5KxpxK#@;CQIvq9fPkWO0*Yb;6lD-llu1BQoPeTA1Qb;! zpeTzFD*8Uhf5-ue*Rk88{Zcf~KB8sk#>|%~%FPYluOmfOIA4mYvZbgRTZ*c)rKkp5 zifXc@s1{p_YO|%N4qJ-qvQbozfTH>Y6g42As38GGjR+_@ih!cV1QazPpr|PUMMo1* z)Qo_l<^&YAAfV_N0*YD^P}GWmqSgcywIQIWEdfRC2q?-Upr}0|RFus1k2oOl_4X;E zoZRq{{^xdE)FC%!zD!Y<+@L{yDeB7kQq+wtMcvs_bSztnda$LaCtHeov8AXtTZ;Oy zrKm3(Mg0gU>Q6w?00N2z5>PaVfTFPaZfTH096rD&w z(Fg*HP9mUaBmqUE2q+p&K+(wr6rDmq(HKIgs8g;#zyXObH#nW8Xu91Njm?djFH3(Lw@> z77}WZgA&OQgi|5OVLuc6fI** z(S>X&x`-`B7qg{kIa`V@VN1~pwiI2;M$t+FiY_CdXcYlPs|hGtLqO450*WptplBTd zMOP3|bR_{rR}oOOo`9mO2`IXTfT9fq6kSU|(MAG_t|Or6dIE|z5m0mk0Y#e$p`scq9DdEUmv zXX8BYhD5V`&$~G>tHASaOFS^q^R_1bDD=F06TPQ;-nPVr(>?E@#49sB@3BNqk>@>? z7&F)No=aR;;(0G7_RaIWU5OS8Ja2cRXp!gbNo-&2dG96uI@j|)O7uP7^Y$h#Ug~*Y zBwoGH^S((`S?+oJ6Q{25yaS0%D?RVm#Fwi)?{K2!TF?7CId`3V|3{KLu5?#GB>B&J zcMU|6{WrL)AdN!m|2S{6w@zSmttk)-{ck(H68 z{h)|7k)(a6{}qv>eXI7>k)(aE?Z!ybzFG2yNYcLB?dC|*zFq0INYcLFWNRd8-!O1* zBx!%+ds`%Fe`WWfNYeh!}|0t5QPoD0LB<-_bUqq7j>5Fe7NqhXcKa#Wu5CFoY=MLN`5?TULU^{eW+ z?n?rZPTAJHs!pR9>8#Pnp3_C+u)V^r*-KL|c9Z)v8R@3yY<6!Y(p_VRopY?l6E=Ei z+!Jx5r^YyYZM`%eiM!ETW3pX>KH;cV+uoYH;MF4|{DYAZo>${LcPnB41x@|97s-h< z&8||(&#sewa*Z5k$@9{hc$F&ka>?`j>Ykt7z0$Fjx>Y)^iu(=gIT`NcPM($YDv?T+ z!WW3R8O!qg3|_ucrL0PoD|L0h&x{)Xd8thIQWainTr&vYNF}{WH|vnI< z-uwDh%N--$2s@aksOPSZO?sYJ*F9mk-sP&omr5o5&(7l4v+jj`Z<70eTI8?nEHC1I zx#t;>Hf`D#7qp#RGN)}x@x->p`6Uwz^XC*7l@?AcEu7SLV)4Q`r9~Dd7EYR1Tv$@! zdG_+|rMtDAQ#@_fw9;ww3%#~ei)IzJEtpxjplzF(MH35Vwk?@jP+ZuyxNvr1NkK{5 z!uI(krSm3DD{5O>R5Wwq)PiZVOWIDEI5EGVcvjoIcKIFh+qY| z*t)P_!nD?T?b>u`ZO?Awp8cO^wVgJ5;>>xI3fs;qm^gLX?El{{M#;jGitmXjQ``0} zo-}XT?4tff#f7cQ-WLl>i&O8C@I5l3xM;e2pO>^9HK(9>#-Mq#^GCbi%ajo_=auA- z?Av)*r~eyQ)BJ+cLVIs{UU)@Mo;Q19yH4%eOf(AllL{vn%$r%7U%GHkVM&{*Cd^%3 zlcvosb;I3$jOsry-(Ad!{flPJDw^$@yGaAgG<(%y^4u+NkkaXQhy+2E|I@D^H@!-u zAmSIc399(D8U{i72`;%a(%b6TD5&Okl{P`7ZCc>ajvP2Re^9$2o*nbLwi}W^A$+oP z$Fe6o^)Gv}b634&$F8)#oZPNs_`HGr^)h+xg{KWIDw>n$4eL8LzyI*j?Y;k-e>C(b ztNb0F`aKNb@^mWu&2%AkDF02hFZ)gPuW)(wyKm14oy%UTTk1DFZ+6MFDYFYFHFQ^C z>iyJTzv;X|ycYKa@56y*@1#6;VNx&O&AnKDzB{`^`~2`Vm+i;kxJtL!zGy^)T*jREEF4EHY33%ZLOUjOd3gilns z2wgbUz4KDfbnjT5*QxB4xy!>FZLgQ_P<}c3mz|NjhTZ~ZABP&i@U z6wlo>&Yn`3UpRZxw1V0BGmBamS0+T{f94J_S*wmyYk;% zx3b?!p8EshoiOm!{JsN5rp|L$t$vg4&xf8G@Sih1yGRXF|NCFe^2#qrKS=_dyBfWb z`F1;^KM1Kehqp3OpbIS3yN_Mw{x+r<>vhZYH`Fo?nRoz9Wb9ID@>=kw`e^Qle# z@@qS8-)Xb#`y?!!a) zgu6acPuP{5`UuuOH3ycR?XCg6#_~(Rb?n|ldS2Oe>8^tC6_?v^w;t}LQm;JqEO*`N zEO*5GcRO^UAODyz(oZYs4;W>SW&KyvOsL-|)3o zxI)XXKljGHF)^R4f}WN*3j+^ zx5;a0_lMhcZQrqB^Wwspg#{&rEgH6-HF3_oo)g`BtZ+f=SsgmKP&#$qtO@Qod1g^T zX=`_9x~IEZCRuPVIeE_fPOVGkw4RjL*_DFgiBo&Jd)M>3ww~2ymb-u6a#G2hmXqf+ zY(1r6>l52IZ0+t4_MGT0KC~R>Tng`Sw6<&AExU~`omMov zb&0!U>y9O^O)4lYDBIz?!hO&VpC~7rS8mog{+~Y1ge)t3EG)CkvM`7-lmftOfjosHdanPu;kFIoXCX zSAJiw{H~t6M+%?tPk~*$GRNFaEWZa=;SL=463g$c@dqN08(O<37ruuiGQ7){dKcLJ zMBQ~v{Z_+2er3OX{fdxX*`{{jx{f1F|!grLBs1eY?3)U=LcoNL%-0(6#ljHpBWJ zH{46li4Dv2;~BZps*!4u8h*`4tw`-iok-nC{j{SZZR|1m|M*ogMZKT@t@v!;9<^2Y zKP^^D$}enT_n| zetUK~?D=**+tGa{J9TuQzfK+d>F7R{mf9!l=pKTn_H-TR>bOM5Wje0W@g^Pbv(MqU zxAVA;Z@H_?_NO`?a=!uF5%-xuJJxW&7dtlA(LTpyd!UY|yWfNDDLUTZt|Hra>G+j< z2iQKSV=D*7b~hc1-8;_q5*;6MpVqSdypBiQXB2H$suLauxGxsiK1s(F4Z^)%$KCE7 zYtR2!$LdYO-B`zQM~8cwjyJk1z+V0y9ltpy+=p~*(>mP8>R9ToD0}(yb$lc*+&gvj zI)*z-$3gB2wU-~I4U#Q~~4!XTRUePf+Iovrq9zQkQV{}|IJ>1vn z_|D95@6)kvQMg;^IALzMi*&rLB;4C|{Bd5m|I)GJf^hfManYi1U##O(i^Kh@j_FIn zT}8*C=ZE`L9WP%R?oB$rcVW1{)Up2ZaJSTP(u#1;)$xv%;ohO+fmPxDN5{@60yc*VwWZ`Sbx_Z23)e!kYR;pT9+)^YMp;V#i} z>n-7aSjS(sg!^9|yWSD*fjXYMHQbl#_}ty$enZFjec`U5)7P2aOdeb{q1m{rQ^NthWl|He|taN{s-Z)$4BAu zI2|weB;2cYd~t8M-_|jEU%2b&IQq+Q7wEX*>u_(;aqqX`{z1p1_lLWKjx&D@_d*@- zKM?LGbv*38TxXtwgW<8)q40Quj>~=z_gWoa{v+J)>X`gH-1T%kbTK;^tac4 zyN;i`ulCvgNyp~ylh3w0={Vbc{m=H0^ zyMN3Qco95m{43eKRhce?n_t|XF;*uZPe=xU*dn4nf3)Jy+(Jz zyfzcvS4#@rXW%Qm)yc&Lv)l{y9XYH`L1}66v; z?p>Gq)yVzdUd|8a|9Uxlp8aa({yfL_{CELT&Vc^hPu}`#07hO=7`rf+C9xV z?n!UDdtDPN1fFzvJ^u4@uQreT=WzrtH^IGJ#kYHf`)f4~U9-1qowqyBJ>;v~A{_XAs{8m-^+S8leoA%pPwLi|mYCAuYKG?m=^l0?x!2Z%& z%ziRfGkv#112^-$Xmic_ZnpQLEi~)7*}?rZcFnqOcJ!hxHS4(9$&0qqtnFrJ_XFKD zYq{CQi?-3M>1J0i+E%lMo88>^glkrJGtXVDJnd?>-Q{YpUDdX`U>&rp*mjq!qjs)s zchNd&=h$|at+RI0w!3g$v=g@7rR%DlZQEVEZrWM4-R0}9UD@sS?(!Y0UCFk)d_A<| zw%z6Hshw%tUA|u08MfW!>#ZHL?Ji#*?R4Aj^7YjYY`e?XPdjScUB3R>zHN8;256_b z-N9YHf!Yza)CBN zmTDtpnKnW$)JDif+6cK=8zIZJ5psz(LRM%awGncM zHbU;yM#xregxsZ#kh`@Ja*sAb?$t)fecA}QUmGD0Xd`5sHbS;*heFo*ZQb>sS+6ehk8zDbwBjkWKLVngp$S>LmIjD`0U$qf(NE;!)X(Qx!ZG;@wM#vx9 z2>DYRA%AHj(UG70dXY0GU(%JfMt{7Y2&6UB{cXMU3_1#=?w!WLI5?kNRRhg~t=E`F0yScL2 zd^cBuz;|;c34AwK4uS9H$|dmKTvZ5sH&;~x-_2Exz;|<1C-B`|H3)n+S4{%n%~gxQ zcXQPy@ZDT>2z)nJT>{_DRgb`TbJZvC-CPX_d^cA^0^iNmh`@Jq9Yx@~xf&DrZmuQ- z2P7*RO^f)CI3V#m?Cyyl2^F2=9#==3MqzwiM;DrKmkyiaM}S)RBOqP6QNnCZMPb0YzO2DC$N)QFj80jwPU|2LVMr z2`K7CKv8c3iuw>x)R%ywegqWtC!lBm0Yw7|C>lgS(O?3Kh7eG693fQHERy#j)0;w2q-#}fTDZ?ipCRAR6sz{1OkdC5>PaWfTBVIiY60K zG=+eosRR^FBcNzH0Yx(iD4Iz?(JTUrW)nh1LnHnm2PFQuo6%uXRL@8ixxZ>+pDlHY zN+N-MduU2gDd$VkJhl|gXG_spY$;m6mZF7hDO$vqqO;jjw3sbL=de+9E&)YL2q-#_ zfTHsWD7t`vqNM~BEhC`lLIR2|BB1DE0*aOsP;?0aMJos>x|D#Tl>`)BMnKUj0*Y1> zP_%}CqO}ART~0vJIzp&uZp2^dfW+&%N7~V1De94WoE3?gFH>}NB(QHUPAR&E^QCA5 zTZ*n_OVLKQ6kW%bqU+gGw23W6H?XB>Gh2#oWTWUN0*Y=Xpy(C?if$#KXbS;Fw-Hcu zI{`&^5Kwd{0YzI0D7uS)qPqzwx`%+GdkHAIkAR~42`GAifTC>#6m2J<=s^OCb`VhX z5Fu1_Rm6YO0f~QTaMnwaeI+pZa3p5FOwr?!z`i{_rRWLHm!c=xQuGvCik@am(KBo* zdX_Ck&#|TGdA1b2z?Pz&Y!tmnK+#JC6unG9(JKTL?INJ)RRW4$BcSMY0*ZDMQ1k`? zMQ;*N^cDd{dk83cn}DKs2q=1&fTH&ZD0-iOq7Mit`jCL4j|eFGm=G#@G~(BEUrCSu zYY*HXlcLnWQTItCX1+|(=aImEyg^FQKF*h-FW6G_C0mNVVoTB2Y$^JNEk)n5rRY1h z6n)Q@qWx?X{Xjs`j|3F`L_pC20*Zbnpy(F@iVhM`^eX{HhX^S8jew%x2`D;DK+zur z6#Yp+(O(1<{Y^m8KLivVA)x4A0*bt}vPb!qQ(upY5Kxpx2o>#(_-8sG@fq$bo6*mt zDD`jD`DropWr|{Hf&F-ll%fpIm!eFz6vf$6REaG`mDy61#g?LMwiG4UQj}y%Q4SkL zxdaqdA)u%#0Y%jaD5_3CQ4Io$Y7$UXi-4lq1QgXFpr|eZMfC_Ms!u>s0|JT~5>V8L zfTE)aC~8bVQ4<1+ni9AzI+}o@W`s~tkmld)fW#B-tMAeDwD6JsG<&4qJS}FvOi`<} zz<#_+N>OXhm!dXoDQe4>qIPU4%417Wd$tsHU`tU)wiI<@OHpSwinHCZK2t0Y%3V zP;@*2MJEtYG?Wl3IwsBk&H;(X-QUHDwv?jE_DFwNTFiWzqLb1B`|&&}MI$+1ibk=e zXf#`jPG(EdDQqbk!}FTCm>zMZc7yjhrt<*RiGOdbSj8VoT8tY$@8zmZBTkQgjnrif(30 z(JgEg-AX{w76OWHBcSMZ0*dY+py*BlinbC^bQb|dcN0)_4*^B@5>Rv>0Y&!{Q1k!+ zMcW7{+D<^xg9H@qAfV_W0*W3cpy&|-iXJ6|implXA9FzB*F+qg4N|nT$-Ccq9 z*G?k@6r~YRuEgo^g1`9mC#_%ypM`a+8Su#xV^%$F&O`+@y<%ao!@oG(R{ z*;16nmZEI76eZYFlw?a$4qJ+H*-})6Ek#w?D5^$4QFQ`}Y7kIVlYpXH1QgXKpr{T3 zMRf@%sz*RkeFBOa5Kz>RfTBhO6dgrCQDXv%nh;Rblz^h62`FktKv8o7idqm*bPOR> zl;QiU9FX|ScJDgV4O(+LUjmBy5m3~hfT95e z6b&SxXb=HKg9#`aLO{`R1QZ=lK+y>V6b&VyXcz%S!wD!lkq|0s?fZKika#uwqDLDk z`pIsKM))!FWr{}of&F;hl%kV4Uy4p)OVJp%6pdv|(Wz`HI*lzwr?aJK99xRcU`x@N zY!u}aP&A%^q5=YnCJ<0Gk$|E}1QZn#P&Ao^*ldjzD&_VKd>Lq zoKm!i^QGu)wiGR9OVK%ODLR)eMN8OHbRJuZ&Sy)}1#Br=%0|&L0*Wpqpy(n3iY_Lg zXgL8zmk?02f`Fn+2`E}gK+$Cc6s;nlXf**vYX~S>OF+@(1Qe|!py&z$imoJ}=qdt= z))P>4H33D}5JE*~`TlqZB>siLSs+DwjMN4{X1+|(^?qPK-aDme6X#3O4Qwge%$A}X z*-~^9TZ(RGOVKTCDY}&{MO)ZXbQ>E*w-Zow2LVNQ5>T|2fTFtyD7u?~qI(D^x|e{W z`v@qypMatV2q@Y{K+$#riXJ4OXa@mB4-ruGFabr65K#0e0Y#4yQ1mzfMNbeyMH_wp zRtF^hk}0}Qir%pCq#rY1rs!EeupbYfQuG|>OVRUeDSCk|MLXG2^deh|USdnp%WNrn zg)K$9*i!T=8%3`XQ1m(hMY{=m-Ht{}NE-MfI>9MG*pu z(g-N>2`GvZP!teQlukfVjDVsHLa68~-*4}L#5>uitG||_Wp?j6Ga55rrYI{K*gsE^ zQk2d4Qj}mzQIai1IczD)WlK>NwiH!mOHnnp6jf(SQ4KbVY7$UXi-4lq1QgXFpr|eZ zMfC_Ms!u>s0|JT~5>V8LfTE)aC~8bVQ4<1+ni5cSGyz4;2qo!A4O}0*ZPOP}G}%qCNx^^(COF9|1-E2`CysK+!+~ ziUtu-G?;**Ap{g1M?lf>1QeY>K+#YFiiQzTG@O8<6A369K|s+-1Qd-Vgo@fl{U;od z_)0gUc~bPH-4>0C#>|%~8WRodpT|kv7LDb6DLR!cMW?Z)=ybLejblsE8Eh#!lPyL0 zY$+PgmZAbSiY5?HG?9R!Ndy!X5>PamfTAe`6ip?dXc_@U(+Mb=K|s+=0*Yo4P&Au> zq9Ou{<`7Ucmw=*T0*XoqC@LkOXdVGY^9d+Aix4V0IqF9TI7PqP-*r4iipHcKutj6$ z%M>k+2KLV@r4*gR`BHQ)TZ)#jrRY4i6rInOq6^qkw3IDH%h*zMAzO+rVx#C{0*aOs zP;?0aMJos>x|D#Tl>`)BMnKUj0*Y1>P_%}CqO}ART~0vJIs%HWAfV_<0*bC8plCe- zMOPD0bPWMT8we=6mVly-giz6v*;lEw#V0c3m`PzD&{PXkh<5S4z>1 zoG(Q;v8Cu{wiMmMmZDqPQnZCFMYpk~=ytXg-NBZkJJ~4ON zY$|%~`aT-iKM$Bvw4d{(=m)kG{m7Q0pV(4#fGtHov!&=4 zwiF#?OVO`vDLTYP(QgD4{Z2s9VFHT&AfV_^0*d}3py+P`ivA&>=m-Ht{}NE-1$x+y zq6h&+X#^Dc1QbOHC<+KDN++NwMnF*p0Y#Yv6vYWBszeACeH-=b4s(iH+gD@1lcLM) zBUNwiH!mOHnnp6jf(SQ4O{f)nrRiEw&WZW}~PM z0Y!BQD5^(5QGEi68W2#_kbt5_1QZ=bKv81?ikc8m)RcgtqX{T#MnF+>0*YD?P;?9d zMJ)*^YDGX%YXXYe5Kz>XfTDJUP*HZ^PjEouhwYJmA_yPp@3X&blo!OzmnrHL1oqF9 zrWAGNd@1U}mZGj~DeA_SqV8-dI+iU(J=jvzlPyKP*izJ+jiNpT6!j&bs2>4E{Rt=< zKtRzz0*VF^P&Al;q9Ftn9Y;XX@dOl|KtRz@0*ZzaP&Ax?q7w-y8bLtONdy#)B%o*% z0Y#$;C_0%CD(VpUw>cp3XY979qZIYB+oDr~nE5hArv-ui^R_8Pr*pm(jblsE8Eh#! zlPyL0Y$+PgmZAc-6ir}D(L}ZsO=6>{kbt7e1QbmnplB)qMbiiPaY zfTGz16crIrG>3qqxdapy6Hrt_Kv5|HMe_(KnomH{Sp*alVAZETy(UKsre;zrd=seDsqVw5ObOBq6ma?U28C!}jWJ}RSY$>{! zEk(=OQgjI$MJos>x|D#Tl>`)BMnKUj0*Y1>P_%}CqO}ART~0vJIs%HWAfV_<0*bC8 zplCe-MOPD0bPWMT8we=6mVly-1QcCIK+*LC6m24eip~lAjt)q?z#f*JD@Akcw&;c+ zX1+|(%|T%Qymm^_Eu1e!x3Z;Z3tNhAV@uKPY$>{fEk$>-rD!W#itb`d(cNqm-9tdp zy#y59M?lg21Qb0$K+!e=inbF_^dJF6I|wLxh=8Jp2`GAmfTBkUD0+;5qQ?m+dV+wW zCkZHeih!c02`GAofTCv!D0+?%D!MW77dasDxpr6RCMnwOo)>*Sh?y@_^imMmKhK_0 z^fKp5(JO2z+QpWlSJ_hZ8e589XG_s;wiLa=mZCS=QuG!ZMSBP+dYgcvcL*qYmw=-8 z2q=1=fT9lwDEg3qqK^nD`j~*CPY5Xblz^hW1QdNnK+)#}6zwCR=nDdhz9gXND*}qX zCZOmW0*byRgo<_s{!3Z0Xq6h&+X#^Dc1QbOHC<+KDN++NwMnF*p0Y#Yv6vYWBszg9hWde$_2q?-Xgo^eD ze)<_sk$v4Y`hyfLwY%Dh^qBcFMOD&+X8BT7mGh;j8e590v!$p8TZ(G3rKlELifXf^ zs193->awM%9vemV2`FknKv6>iiW(76bQA$ajR`1fLO@Yd0*a0%pr{!EMa>B)YC%BJ zF$5H~B%r7j0Y$9|C~8AMQCk9v+7VEcM?g_~0*X2iLPa_0{!j-bKFID}=cb2`^zGk@ zi*`(pnJ-h+H9eSBAVu9cUy8c3rRZ3;6!ll!$6?IPcFLyxV3+;ng7b)6iUk*7nJ!Za4(HZH%0~4j_ zOwO00e6|#gXG>85TZ$&IrD!5siYBq8sE{p1li5- zECPyV6Hrt{K+zlmislkfR7^lo2?0f=1Qg99plCh;MQ0IEw19x3g#;8WBB1DO0*V$B zP;?F0b6>^e3_yx=|S(QQgj>VOVRCYDY}C#MR&5LXe(Qa?qW;P-E1kkhb=|- zvZd%gHj3^ipy&Ytinb9@w4H#W2MH+JK|s+%1Qb0?K+z)v6g^5n(PIP@Jx)N;69g1J zNkGw41Qb0@K+!V<6g^8o(Q^b8Jx@T<3j`GHB!r4?N%to?An{Fh^K+{d)w1zoddz&8 zqFw31h0~?zRnC{9*Vt0@I$Mf%v!&<_wiLa|mZG=VQnZIHMQ^jE=p8nS-X);uJpzi} zC!pv90*XE)py(q4iasWw=o12pJ|&=NF9AiL5m59w0Y&==DEfkcqAv+3`ig*}uL&sn zhJd1P2`KuGfTHgSDB4d56}_D9-{FA7x7$awSEOi=J?#G>J!Za4(a-6@D>J3&7tWWW zgKR1Kl`Tbw*i!TxTZ(>XOVMGr6#c=LqCeSE^cNdNe-lvj4*^9-2q^lOfFduZhwUhe z5KxpxK#@;CQIvq9fPkWO0*Yb;6lD-llu1BQoPeTA1Qb;!peT!gqHF?+5(E?_2`I`T zgo=Jj_YXKA@i}($b3lqV+r8`DSj>ExqUy0Ar$~xwaK04PWJ^&kwiMN7OHm!R6xC%* zQ9ZU4)n`jl1GW@3WTU7N0Yyg z^nbJ)rY^CV`7%Yv#)2_(rKktzOHog@6!l_DQE#>s^1QeY>K+#YFiiQzTG@O8<6A369K|s+-1Qd-VplB2UMWYEQ zI+=i?QwS&;LqO430*X#0py)ILicTklin_)8#STdPYd53arD(m~7LAL=%$F$|9}BK4 zk)i_5m!b)5DVoTZqDgEiDr8I1WVRGdVN20ewiHccOVM;Tie?Z{G?Rd$Sp*c#CZMQ@ zfTB4B6wM`|sF;AF5(0`!2`HLJK+${xiq0aSXaNC53kfJ%L_pEm1QabMpy(U|iq0jV zXbAyD=Mh3hXU6{`BHQ-TZ)#m zrRWm26s=%O(WPuDTFI88%h*!1iY-N}*(h2=K+#$PiY_OhXdMAXR}fHiB>_cO5m2fP;>(UMVkpIx{-jQn+PbnnSi2O2%(~- zF+XFzQ*?)$(PdI}lYK2LVM75m59n0Y#4xQ1mDPMUN3s^f&=UPY_V_BmqTF z5m59r0Y%RcQ1mPTMb8mX^gIDYFAz|)lYpWZ2`GArfTEWPp`zPj{%{8*{iN(y9DSAB?6fKgX-JCB)Z?L84O|}%h#g?KyY$JWLzXTL{8G6``q6h&+ zX#^Dc1QbOHC<+KDN++NwMnF*p0Y#Yv6vYWBszg9hWde$_2q?-XpeR8=QIde790H1R z2`H*UKv7jfsOXoN|A7M%uVH^N?VuFp7^!L*G4o}LYGnj}ohwDPIbVwEu%)OjTZ-zj zrKmnziW;z`s3BX58nLD5D7F+eW}~PH0Yyy-C_0*eqGkjXH7B5`1p!6J5Kz>TfTC6e z6tyOxs0{%{Z3!r9M?g^?0Y&WzDC$5!QAYxbIuTIRnSi1$1Qc~8pr{)mR8%9wZ@9!M z8fbq>wq{27NPnl@yY8M5Ghe2tS4PnHd@1V9`BKz}Ek%9VQq+$vMg7@QG=MEd1KCnE zh%H5f*-|uwjiTcSC_0{iq7w)x8cIOXFanB(6Hs&_0YxJSC_0INqLBm?jUu3EGyz2? z6Hs&t0Yzg7C>l#Z(WwL!okl>>=>!ywBcSLE0*cNggo=7(_>&!w_zwoBrxY!*+oJr8 znE5hA6ElK~mrBtj&X=M>wiHcfOVJdz6isDI(KNOcO=nBd47L=_WJ}R3Hi~8wP*g-f z(HsJb<`Pg;Oh8cy0Y#+*6wM=`Xg&c&XAw}efPkWf1QabIpy+G@iWU=4bPfSU=Mqq~ zgn**+2q-$AfT9ZsC|XJg6%}OoTOE-2<#7jRf)qV&q?TpG%$F%zo)Nryp%h)h`BJok zEk&2IrD!EviY{YI(JHnSt!7Kn8nzUzWlPcJY!s~{py&z$imoJ}=qdt=))P>4H33D} z5Ky#%fTC*&DB4Is(RBnAT~9#KCIX6XAfRY70Yx_wP;?UkMK=>rbPEARw-Qjag@B^l z2%(~jGW=g0koXS!(%HpQ6t{cVw`au6mnpg{BdD@mitgroDY}O(Mfb9$=sva--OrYy z2iQ`yjV(pn*;4c%TZ(qDQS=Z2MGq5D^aue(j}lPy7y(6(6HxR70Yy&|Q1lc5MNbn@ z^b7$-&k|7d905ho6HxR50Yy6rD0-2AqL&CLdYOQtR|qKDML^N3giz6)8Gcs>BtFK? z=vFC;*+;b3GGgY-6up@doVr4a-r{^I+QXKjx7kwk4qJ-eWlPa}Y$W7eL_Idrvw!3C7|dt0*XE-plBZfMPCq5^d$jBUlCCBH33E65K#0j0Y%>t zQ1m?kMf(XT`hkF=9|iGZR51Qh*DK+!LRP|@xT|6B*eeLQn;-jJf}>=W4sGh*h; z6#bqNY+5NrhdE!0{$NYdpKK}mi!DWev!&=CwiF#V8RfTBDCirN!U)PaDajsz5SBA}=<0YzO1DC$Z;Q8xmLx)V@zECEG52%)0d znSOk=Q`FS%P}j)}AL*Z(dcc+$Ghe2tZ)VVPtrYd+d@1VBmZAY{DH_O@qCspa8qAiW zA#5o+jx9yUv!&<+Hj0K4P&AByqTvJ-ok&2@2m*>uBA{p_0Y#$-C>l*b(a8i9okBp- z7y^pM5>Rw10Y#?~P;@#0MdJu4I)i|sGYKflC!lCN0YwFbP*Lwpe}n@PA8xlreWb{< zd)E^(W9G{gP0kGFu9KoEoG(RF*-|u(Ek)DWQZ$1tMKjq_G>a`ov)NKq#FnBtY!uBU zps1LDq7nj%N(m^MM?leh0*cNeplAUBMGFZiT0}t6*#s0VCZOmX0*cNhplAsJMduMv zbUpz^7Z6ailz^gT1QcCJK+#2nP|>7J|0)M0{*-;zu~3Sxx4&$3ac0bXnW9TGgB@2& z(MryjqRZG)w2Cc7tJzYthAl;F*-~^lTZ-1PrRWN_6kW+i(NzQ#ttX)9Y66O`A)sgj z0Y%pmP_&VNqU#7Kx}JcdO#~F(KtR!E0*Y=Vpy(z7if$&L=oSKsZY7{-3jsy95m0nH z0Y!HZP;@6DRCGzE|B(X{ALwRug%pjjhy7bKW9G{g-J2QwvtEks<9sQ)pDjfXu%&1l zTZ*=`rRYJn6zyP3(L-!0dYCOmkFZhnC;>%}5m59v0Yy&`Q1t&0ci+)b)qNZ8_hiq` zz@*HCA|QxCP(exv9i%r=nlwcPLV(Z&0wf?H76cR&6~%&zD57FT>{w8&prWE!u%p<; ziU=se`F&^KSCZ#>*SpU7<6Y~pmhRkFvXde6VKS4D@H_!Un+Yg-fq&5m59c0YzUCP_&zXqOS=k`i6j_ZwV;+j)0=?2`Ku3fTAA>DEf(jqCEr@ z{Y*g7F9a0*NyfK+#bI z6xAT0s3rkLwFoFWnh+{FP}yJafW$ws`$Y$(sF97@@tFBCMaRa2w^vJ1F6T>8J+>4b z$Cje{Y$PSFQCjyE(6HwHJ5Gpz* z?*Hk4#OK+~Pu+Osox+x)K5QvEl`Tc5v8AXl zTZ;OzrKmq!iUzPzG?0Lz(+MaVL_pDC0*ZzZP&AZ)qG1FSok2j+nFJIKC!pvo0*cNi zpy(U|ibfDnG?IX#Q3Mnf5KuIlfTBVIipCI7G?sv(afDD&_qgA|0g2mp*-|u(Ek(s_DVolfq8V%{n#q=;5;lrT2`HLH zK+$Xhiq0dTXbu5Ia|tM#M?lf}1Qg9Dpy&buiY_Fe=pq7&E+(L80Rcsq5Ky#`fTBeN z6fGv8=u!fTE+e352?0e*38A71asOfmBtFP)ekP*G?j&6vkC`u1bX7c9bC(od&G}Na zoGnGyu%+l)wiK;kOVM>~DY~95MK`de=ti~_tz@IRv>0Y&!{Q1k!+MGq2C zw4M+uS{Ceihd%XXb%BJKNC>&3jsyH5>WIT z0Y$$PQ1k}@MSBS-`jdd7eFPN!ML^Mh0*Ve0LPa0M{lN}M{4ay^p%m@4PaYkN$IO>0 z`ZpewJRn7fIbVv7u%*b$&?9##im;_9jV(n!TZ*D=DGJz9l+Ko-7#l^E2q>ydKvA54 zq6`9xG6^WkBA_UnfT9EeMM(mRatJ7@LO@Yf0*a~;P*k0OqN4~XszE?eO#+H)5m0nA z0Y$Y5D5^t1(J_Qj(LZs2r2`WG)INwElA_z(^P+V#V&=;f9hVV2wO)$qbG{TcU`x^Q zY$-Z{Ek!4?rKllWiW;${=p?ojHD*gu6E=#P5>V8PfTBDCikcHplutlW3j&H-5>V8N zfTGp}6ty9ss4W3S?FcApPe4%z0*X#1pr|7OMV$yJ>P$dU7Xpg95>V8QfTHe%P*HA% z|G5Ja-(p{lt(Or#(r;;ZwR>d5%$F%TB_lYpL5litz7(CxmZHlaQ(NF@4h7nM71_4E95>PapfTFVqC_0;fqH_o+8bLtO zNCJvR5l~b>K+$LdiV6uR8bd(QSOSX15l~b_K+$*tiY5?3MZGfo1`j($tL!g>^p>LQ z-1DLnGh*h;6ivwpdOa#dQ#oIXrm>}{m@P%q*-|uvEk!fgQdGj0qEfaL&0NPLRj7A=>e@9p08BN;LCWs0822;O;8ik{?rDcZ=EqNmtW z^fX(Fo?%PTvur8a#FnDx*i!U7TZ%TbQS<@T{-fTFDg z6um}3(dz^hy+J_HHUf&?B%tUm0*c-yplCY*Meh($^ezEKI|wLxkAR~02`Ku25Gr~s z!~e?xi9cm<9+#qPQxDiOV&=;feUcH>cv^}+<$Njnj4efeihd%XXb%BJKNC>&3jsyH5>WIT0Y$$P zQ1k}@MSBS-`jdd7eFPN!ML^Mh0*Ve0P;`)hqQ40!`iBrI`Y6Ni=zzpuwa+?!EJdFg zsY4kt^JR*>%wXiRQWVM5BY7!GV@r|GmZB(IiUPJ2rL(0d#+IT=Y$>YDmZCTtMHvJX zWfD-7ML=(55<*3XGyF>&koX?^tm6?WYT=$2t(O@yU#95z%wX+vQgj06 zOVNpJDQd`;qDE{fI*BbsjoDJvge^r)*;3SuEk${36g4NHD4&3$76cTvB%r7j0Y$9| zC~8AMQCk9v+7VFHo`9kb1QeZ2Kv72miaHTc)R};yE(8>HC7`Gq0Y%*jDC$8#QBMMj zdJ#fJ^)vmg4oG~H-4->-3?J!N$#kQ4X3TtiA2v%-U(T1Jerze~&z7PAY$+PZ zmZH1V&-6lL3I z9Z!{_1@3v#b2DS+%M=x726-<@(R9w2q8V%{n#q=;61EhTvZZJiTZ(40rRY4i6wP5v z(Ofo)<`GbIJ^@AZ2`IXNfT9ZtD7uJ%qKgSAT0lV2B?J^LB%o*!0Y!@mD7ut@qRR*< zT0%h4QUZ!DC!pvG0*aOqP;?~$MOP6}bTuJVG&R#7>VU+%+8yd?QZ(4c^30g|GDX*A z2D4s~qU$+dif&*_(T!{=TFI88o7hrxGh2#oVN1~}wiMmUmZH^c6x~KZ(d`5jts$W3 z4g!kS5>Rv}0Y!HaP;@r|Me7JCx`%+GdkHAIkAR~42`GAifT9NpC|XZI(L)3jZ6KiN zVFHRCA)x3{0*W3Zgo>`s^lx@R;`{88{t79YlX}3G88cs|=&8)$nJrTEH0MjvGi)h( zmMuk_*i!TyTZ*1%OVMVw6urQfq8Hgx^b#9IFB4Go3IRp05>T{-fTFDg6um}3(dz^h zy+J_HHUf&?B%tUm0*c-yplCY*Meh($^ezEKI|wLxkAR~02`Ku2fT9lxDB4Lt(MN<( z(UY0}E(avu#BP2zN>N?+yy(Z7G4o}LKF zqHowz^etP8zGF+#_iPmXKtR!t1Qh*5K+zroihd@b=obQtekGvjHv)=&C!pvL0*dw$ zQ1mAOMf(US`ip>~{R9*pAfV_V0Y!fkQ1lN0MTZC|`j>#B!-P=LrS*wKv5L}imDP&RE>b5>I4)WMLT$?~T-An`u-1=zH#@G)9d_q=F>teE*SMGdop zE8mi$Mx3wPqLbKC)R-+rP1sV@lr2Tg*iw|omZIitDavO{Q42PTS`tvyih!cl1QfL) zpr|bYMePVEYEM8>2Lg&tCZMPz0Y#k%DC$f=Q5OP=x)M;-jew%=1Qhikpr|JSMZE|p z>P~Q~h7(Y976ClvX(I^6n z3J53~O+Zm00Yzg7C>l#Z(KrH%iU=qgPe9QG0*WRQP&A2vqR9jlol8K`6atE-5<*3N zv-|@NNc>p4E$Sylc6TT`Eh}ceOwr7&pwkbt6#2q?OkfT9Hi6kS3<(Lw@>77Rv%0Yz66P_&$YqH72!x|R?snx5r%c0l6$;||UYDQa!E zMJuvm=F1e_m=zSfFGVXkUy5#GOVQ12DY}I%MXT6SbSqnmR_^?k1pU9RWr65Kwe40Y&!_P;@^5MGp{A^dJF6>j@}&h=8IE1Qb0? zK+z)v6g^5n(PIP@Jx)N;69g1JNeC5PpXD!dK;k>>vyL}NQIXxd-k23LU#95Utl+K> zrDzl9OVM*|DSDnQMVr}D^a5LoUSvzrOKd56nJq=Hu%+l#Hj1_oP_&hRqSpv0dYyox zHwY-&MnKV<1QfkRK+)R-6m2J<=p6!z-X)-D2LVOz5m59#0Yx7WQ1l@IMLP*7`iOv{ zj|nLHgn*(?38A8=v;5Z`koZ=+`FTc)cH5UjKFf-kFH`hoR`AnDQuGz)OVMt&6n)K> zqHowz^etP8zGF+#_iQQpfh|QpvZd%JHj4HTQ1mkaMZXYG^eX{HzY$RMI{`(15Ky$2 zfTBMMDB4Fr(O(10YMdRM_qh}`;e07-%9f&LY$?iPOHp&S6y>v}s0CY!TC%0661Qc~5pr|teMO_Fe>PkRSHv)>f6HwHHfTErR6!jvY zs5b#crw~xohk&9}2`D;^fTF&HP*J07f0Y9gA8TI$IZ2AXG*bPtW9G{got_PaTfTFPk6pbUGsEB}~@dOl2AfRX>0Y#GtD4I+_(YXW^O(CFYDgi~)2q-Eh zplCWFR5T#l|H=W0KV^UKdY}{?Hc~UPW9G{g&B_k^-BL80^QGuKwiL}_OVM1m6wPBx z(fMpCn$MP^3)oV0AzO+rVx#C{0*V$8P;?0aMGFZiT0}t6VgiaTC7|ds0*aOpP_&eQ zqRR;=x`KeBWdsymNkGw61QcCOK+$pnimoA`=vo4bRuE8h9RWqx6GBBL*?vO@B;M5E zluFS~yLWv{(Ek$eCQgjDfiq^8F z=uS3@?joS*ZUTzd5m0mw0Y&!`P;?&wMfVd>^Z)@x4-!zco`9l<2q@Y>K+(el6g@&f z(W3+uJw`y$;{+5vK|s-y1Qcx~py(+Aik>EfidJU((;Sd^x_#F1CMi1G9_c@m9W!61 z==tp6>hGjzGv`au3v4NRku60pv8Cu`wiLa>mZDeLQnZCFMO)cY^covQuM<%81_4Fe z2q=1!fTFhuD0-WKqU{6}y+c6Jy95;NAfV_y0*c-zpy&eviasQuXeR+h9}!UWF#$!N z5K#0f0Y#q?Q1m$gMPCp?MVqqy#~hG&ZM!S<9QTXtug~tvj+rl0^mTUd{tr_04d+YI zw`?i;jx9ysv!&<~{R9*pAfV_V0Y!fkQ1lN0MTZC|`j>#B!vqu^A)v@h=wUmGA_Nqr5m4k4 zP!uJEioVMB|8_v)&l;TFQdDZBf<(-GnWD;xp!OaqigUgcWw50vlPyJAY$?iSOHqO? zMM<_4<*=ow3R{Y*vQboxfTHRI6dgrCQ4Io$Y7$UXi-4k|2`H*fKv5k6ijE+B1ckpyQ6A?@QFFEw<+G)z1zU<*vZbgMTZ&qOw$KR|1N<5m3~ffTA7*6!j#as22f6y$L8fg@B?y z1QeZ0K+$Og6!j&bs2>4E{Rt=u61-=rS7v6EX8;iiRYDb-zi` zP|la4VQeWngDpj8vZZJ^TZ+zNOVQbEDLRKOMI+c!G?I;?Q3Mnf5KuIlfTBVIipCI7 zG?sv(aRd|<5l}RqfT9Tm6ip~MGM$cbO{?p3kfJ%L_pDE0*Wprpy)CJik1*iw3L9N%LypDf`FoB z1QcCKK+#nM6kSa~(Q*Qct|6f4S^|nz5Kwd-0Y%pnP;>(UMK=;qw2}}inw{{g>~)G3 z*w@j{lcLpu8#g6l=F1e_nh09%lcLp}FGaVprRa9H6s=)P(H(3lTFaKAJK0in7h8(% zW=qjJHj3^cpy*x#itZzz=zao<9w4CTK>~`_6HxRJ0Yw`KD0-NHqDKfQdX#{o#|S8T zoPeSy2q=1zfTE2A6g@>i(bEJJJwrgzvjh}vB7}-=N%+GZka#D%Em|c-G5d)2Tq0(^ zOwo&pVD5e?dWrL;=w-GPy~38FSJ_gug)K!}*;4cxTZ&$1OVJx_DcZ(H(VGMmy+uIL z+XNJCC!pvZ0*c-xplAmHMeh+%^gaPa9}rOVApu1@2`KuAfTE8HDEfqeqE87Z`iy|0 z&j~2{f`Fo31QdNqK+#u(P|@auzuEzb_p*m&FGx|`J_Wfu5i?(==(|Ml{6Q)Dp7W*X z2euUb$d;m?*iy8IEk!@GrRW#76#dGUqTkq3^gA0xe-Kc#mw=)_2`Jh}K+#_W6zwOV z=l}sl2MH+pn}DK!2q-#4K+(Sh6dfj@=m-HtUQ!R+Q4}GdD2;$3pMat$0Yw1;Md<_- z#R#FIZxa634oJMCeGvOriVoSALn=F1diCWGLR6lHO~6lJreD8ZJZBwLDd*iux5 zEk#w?QdEsCMb+6-bQBv!H3%rGNkCC80*a0%pr|$hMRf=$I);Fvx&#y*OF&UB0Y&u) zC_0XSqWT0BH6Wnqcmj$}AfV_(0*V?EP}GQkqLT;6GEscp7c+0K;lIPCnFg? z(%)(y-kK(3=F1f2CxgC+rKknxOHoU<6t!YYQERpowP8z9TecLnV@pwcwiI<>OVP<} z6m=w^s1pH2oe3!FLO@Yh0*bm3P}H4(q8Xb>S(l$Z3UJ0S6&?cQ~BDOzDSOoNj#^JR+8NCww< z_6nMN(K9(;iiWeL=q$Droz0e_bJ$Wef-OZO*-|u$Eky-vDH_d2Q6T|EV+bf3OF+>$ z0*Zl>d(F6jDCK6CIiGZTX1QeZ1K+zNeil!1!G>w3wVgib$6HqjRfTEcM6qOKA zR7yb6ECPyV6GBBpll~J9NW8Os>1>!39c7R7&r8P4mnk|w8GM)~Me{jdiY{PF(S>X& zx`-`B7qg{k0b7bLVN20MwiGR5OVMIBiY_If=rRI|mJm?1lz^hk2`IXPfTCpt6kSO` z(NzQ#T}?pIasrC3A)x450*Y1;P;?yuMb{HhbOQlJHxf{^l7OO{2q?OlfTCLnp`y7- z|BwR`Kg~XOJx_|3*lp3OWXyb-qT7?fF@Y4V;e08&gDpjC*-~^TTZ-;tOVQnIDO$&t zqI=jhxdYFKsM+hi-lz^hg2q=1-fTAY| zD0-5BqKyO;Jw-s#(*zVfLqO591Qcx|py)XQik>H+Xfq*Hv^wc`cR=Fx?B?e-DH>pp z(OyW#%$F&8B^iv3NztpEFGX9}QnZyVMX#}?=ykRfy}_2EZEPuelPyJWv8Cv3Hj1_r zQ1lJ~Meh<&w1a@6_XsF@pMatd2q^lHfTEoQ6n#WM(Z>W7eL_IdrvwyzMnKW$1QdNi zK+!G&ioPVE=qmz>b`wzaH33E65JE*SCH*B1NW7Ze7QHM*57@oyZ<8_eWr}`G2KQE$ zqMtZliuSOj=x4SR{lb=_U)fUh8(WHgXG_r^Y$@8ymZCq|DB4Fr(O(1m`s0v$(s6xCv*=x73pY7ycK+&-T6y*|7RF8n7;|M6K zPe4%v0*a0&py&hwicTb;s38GGjR+_@iGZTU1QazPpr|PUMa>8($|Hn|vU2=tnNHD8 z`>bPjPWVWFjolVC&xx5YQ`9OaXzhMXR_ZZYYtEOVHf$+s%a)>cY$Xb=HKg9#`aLO{__La3-kj(@fT62Hst3bmA?>UQsX zSWe7*nWD3Dg7cG7bT;Qp(K&1>8o`#Lk!&d%#g?K1wiJzKOHm|Xe=8=;|M4! zBA{qI0YwuCD4Iw>(If(jCKFI}E&)YT2q>CLK+!Y;ii!y+nodB`3<8Q~5>Qk^Kv5|H zMY9MfnoU5_c?1;AA)sh3Ayjl`j(@uY5`WHai-t?lT>FSNFDGWcOwolo!3$NS=pxRS zqKny5w16!|m$0R1AzO+Tv88A+TZ%4aOVMR)DO$ot(NY46E+?Sq3Id9j5m0m`0Yz64 zP;@l`Mau~&x`u$FYY8Y?K|s-U1QcCQK+z2Z6x~Qb(Mke}ZX%%QW&(hxdYFKsM+hi-lz^hg2q=1-fTAY|D0-5B zqKyO;Jw-s#(*zVfLqO591Qcx|py)XQik>H+XfpvtFAz}lA^}A&5kf_4a{ML^NPK{s z(L1DQn%x$?oD(x&rf6$U(7%Qhy~g=c^g3IL-e617HntSK$(EwG*i!U1TZ*=`rRW{D z6urwv(GCKN-XoyseFBO;AfV_&0*ZDLQ1lT2MIRGT^a%k)pAt~?839F~6HxR80Y$qA zDEg9sqOS-j+D$;w*8~)OLqO5D1QdNoK+*SvP|>S7{!9lX{CuY7( z(a$--ids_i3+GGGuWTv$jV(pLv!&<{wiNAUOVOWfDcZ-DqQBTuw4aTl0|XQuB%tVT z0*d}2py&_*MgI~|beMpmBLozARrIhOMG*pu(g-N>2`GvZP!teQlukfVjDVs_1Qb;! zpeRm2Q3e4;nFJJN5kf^j<@g&NkoX4s3dkNQirYuD>?$$yWs0g)2|lVVMO8UpimI`t zs5)DUj$%tu4Ym~3WJ^&kwiF%BmZI8hDXPOp(J=%R)g_?lSOSW22`H*ZK+$mo6xAo7 zr~v^*#}iO=0s%!Q5>V8TfTBhO6rDssQDXv%nh;Rblz^gU1Qg{FP}H1&qI?31S`b1- z$twO~2PEFu{$g5AmGF`NRd!p{vP#T+nWDB;f@AASQ9I6;qV{Yl>cEzwli5<#ku61? z*izJ)Ek#|}Qq+|#Mcvpa>P|pW4+4sM5>V8OfTG?66rDmqQ6B<|P9>n|Gy;nH5>V8S zfTI2c6b&GtXdnSarxQ>#h=8KO1QZP+plB!oMZ*XvI)i|sGYO%h)>ZtT4oJL}!D%B! zN9+sy!>h#1mnj-iB`C_3qLG|0MWfhKRKS*^(QGLyWJ}Q)wiJzJOVK#C6cw?hXgnK5 z69_1pNI=mf0*WRRP;@Q2`HLQK+y~Wie?f}R6;;eDFH>Z2q>CO zK+$;w6wM)^Xf6Ro^9U$9pMawIgiz7hRs72xkoZW0bB+`>v~QHXpi0bqnW6<%g8Pq? zqDwemiWah^Xc1eA7PF=3QnnOb#+ITbY$;mGmZHnqQgj6yMau{%x{`pRs|YB%nt-C^ z1QcCEK+&}X6s;hj=sE(5t|y@A1_Fw1B%o*|0Yx_vP;@f^MYj-8w2FYDTL~yyO+e9Y z1Qgv)K+zgPsOX|9{&oi>{;QkOi>2s*jXSEu%$Jw#rA6yku6;tpORRHWvh@3DT_U4_=XFdBI>Gb0CT?u#c|8-Ko#c6a67`#UUcbbo zJkL8l@ld|!4NdH8>3PEwC%5su5s3xuJa2SjO9#&zm&oemc@q;ux_I7{#7*5iZ+ha3 z9-dd4IKH>%%}Jcw$MfbV9zM7(4=Xr|~od$Z|lElJ6p0_OV+7QoMo=BYGdDkU| z4fnj2iCfP0yj6)WM|j@ti4zMv@6N>3LeIM=@#t93dmwSJ$n!QNx=i%E#}bPtd)~&x z8&f>**+fpU=WR}$Im7c_PTX4Jd0P{^XL;VXM58&Lw>?oj&-30(JU-v^b|(J0(DOb` zbX(wgyAqcz^t`VVZ!Y${?-Ny*c;24GS(kg>Z;9KMdETFiZ?5vZ1Bu4hc;2Dpj1}(v zA4xuWy}JS;$$xKj*FYrM<7RgiM3PHax$7X3e0#OK5+cd!YuvRENuIOTT@8`sn!DWf z5J}pfRi>|FAN&6=`+eMQ0Zz^_-B<&x?>l#Vg zziQSqlC*!8s!t?o|E^HKNb-lx?mCGi?O*m78cEte%`iNYw4bd%B9gQpjy^h)w4ZK0 zE|Rn#PdqV_w4X0KC6crs5IQ}Qw4d-;8cEuZ=$jKs+Rs>qEFSR`qGWp`sFX@BSP*+|m<(%j}q(*D-d%aNr0wUw=rr2V~v zZIPsX;dpx_X0N8y*u9p!hFVp)aCO|P@ank#>?YFv{!{qN$IR{lZx|7i;Jg>ome<&T1no7v11DgXHLz_Z(h){phfc*`33pS zEjD$r>9pc$MNNwe$4qLP-@IANruOV+?%DtGth`Cn#!i_vt|)J6;n<0jrv3kZF-qo^ zRD4fNn3&gX=D1mtrWN-no>|ni?0qq(bY|*Z623=HpIJQFz0XVXhD3WoIPRp2h>*dE1Grxs6h&G5O~vLHp#Zy5=Ks{h-sph|kx zplZD)L6F|pJ?&mJJuj&0j*+~yzy(1t&HH$E%x~AcPr;b*$u_OZo^0Kt?8!Fm z^pdUG(YkSR^HzFZFFnz#heEzPYf``B;_3Nb|8BzzdJGuaB77q~Ik$D$8*WQ#S$+Xp zlwE)x6<(z-X$wwhQ}$BrQx|U5w30~^rWK9Lb??X2o9n>^?9FR&Pw@NgRrVXocNZr0 z^6lM=6%@F$Tec_&UqiloW1P^N*Vaw1t$X=vaPJEDV&i5_ojNysO?uf@yy0#NZOblz zd(W1==CU`^inr0T{GH+61$seuk;8YRdoAG;6)r+sPId3R)HB^XR_C=Ydu8tO@J3tc zm%h9U*qPZ(O zeDSj13#yuz|5n`(*X!Hstb%Sm2dB<+*Q0(%&a0m4`5$L`Q;Mfe$W8t4f0)WI zzaZVk23_tt^9C2#pI!ZF=gsMNSN1k~rC!Hm`va1CR&%`~=T(=dd)XzkKccA@>Q;7o zeowCcmU>>9htx$#{lPAKRr%%QAcBzma)a*oqBo6;G6C+^Ap8xKgUWZJ!q%K;mK)3O z%@tHmi|fq&Cc^W0!mgauEm8Ru>~5TNQS#ko;mQ2+_eh1Sxvfs;st5(yD{NQ(?sD(U z@NKlxXLSB)ot7bDc8siTRvj!+4hRuvFshC#MS0*QuM5rW$!}wj^M@1uXwIguF|rr zv7LMW6_;TxzfQ_-{~Z;*I(H7QxE(~?n@wFt_nzQ+Wf#f4E!XUi%ux5CFnpK0j|1To z?)peQVOMhMqe=Kd#C^2U>v7kBo+`ftT*vM`r011gm+mSEUvaq&cgx{kD)q`!&vMtT z&T=>MdaCR<;@pMjyW2_6-KCltzE|?YgFeEQYsfF>P$sZkf%_=xUVq8N;+dsoAFmuX zE=72ymtEgwA6eZWlhljYbz)aMAG-1@2q?eC^UJUD{POFZDKEJ4G6mJ~J0Z8~-A^jV$8x_4O7oTgJ-wsfI%;;gA-+;RMr z;=`(K^Lx(m>B{M4e7lEMi^O{Wx1n@~EjQ*)QXI~GmtN_Wd{-b*JH zPitD@?nk;~iEHBuOAE_(_^xmtoWm!|#oA4`e%q$;fBO&^{xF-b2bhu;z2m zu>8(l`F*! zRCcGb?A~J89m5KLG|T^hmEWyHPx+m?G8N%HL+_LxJv!tzv_Fj9W=_rRHFZqUxN+_t z^-vx}rv7~L;IPsE{-@Q;bdOk$xL*-3ZGN_U9B-Rnx$cQ>?cM(h?eV4;$#YKz?V9#) z*1y}S1HAN{SpUj?yi%2DwMg|y4ZmijR^;eN?MR(S-L&H(&FtayfBmYMqTcUEDn8q{ z2V50?`Fc1{^6l|fgmb#$K*@zUI9LF(Djy--7SyT0t@+-Gc4NB4Q! z)Umscr|URONB1Z=_58^?y3eMj_C-1_(s8+tYju3sK8@nu&L$mqxZj%XFLbnj7u0sd zz02)b!~I_DSYOBX?y}qNrQPxnc2d;TCDFF!WiH|n_Ey<_e9pXqp1gK*c^al{GXo}}X) z?h3G%e@MsgPYU-w9h)@`_sKezx+}_Feu0ip=ZAZXj$W&9XX)76U7_~!Lv&o$F5EZi z_-==Af1zVdcg5SwAFt!6F5x~`$2+@)`(Yh_>=Ew$IyUbe?oK++?i22XIzD?^xL?yT zt$(-^I`$bD?qND!H7MM-==k1{aDS=e(PxDFL>)&D5BF3Z?>;-+kLtK*M7R&?*rFiZ zU38pN81BV7KIfp@`{NBAqvOM!qvL54!+oZX%O{8XRvkZ>67JnP)+r8mBOS-g2zRlL z_mqVDaUFk|74Cm@Y&9p`-E^EcFWi^uxOslK-_$YvqHtH$vEPDlpQYoq3&VYzjyo5J z`x_nWE(v#I9micB?io7Xw=CRG>iFAL;r>_0HrIr^hmP}CgnOxuFJ2$+w{@(vGTha5 z9B^~E&(ZO^RpDNvq><3wJLa zFMJ@}SLpci`f$IaWBlQ8*U<6wN5ef*#~U6G_gWo4eKOoX=y=@I;m*@>;cj%b;dbn%pICxvQ3v^uhR=Drd@$>EB z{z=CMJHnl>$r7SxZl??dv~~N z>p1kAa2M)$^LOE1r{ga7B`5RnvyLb133p2!r~DG`xjH`bTezRs@qqiXl${^!4Ue7o zg~z@+F4`aNYjk}5V7NcjF?lH5$LM&*;c$=Dah3b1Zm<7d9lvs4)w2Dojt$+Xgl)Ih zahm%&m+kX)e9V2p%k~R8{_Vc-Pgiwuh4Ou`=Xfbk94f! zzB*?6SRIGEFO%6W(s8x>dYSF}b^O|W;mr2$I-cadf@Zs|j?;6)eSwZoxUZ?%^Iy`j zj{6F=?M6B_w`1UWCu{f7ahQ%{bS&0!zK%DuM^#W?%n?X`f^R&%l!A-&2^1mc0Jjzp6)+h zx9y?szn$(n<`++Ob-~?b^z3NAnzWC2HC?Fcp0=ysUY}jA)7^iZ$u3hzB{O>dG_CG9eKIVZ6n@kdKo+La`)?Lp0&iiTrR^M?d{sHb?(24mv2gi->cS!xZ$GyG|40p7*YrpJR;oabUZEx2_`*WV-{tG~x0M%iM_#Vt!?hO8iu3Z@HgD6ed5d-}TIRY(*v<1R{J%|`R=K(D zTD5H3Cf9zAj$hQPU+?g1%;77JxJPNcUMm}VrB)FB*=*?5a*t$_k6*GOvi!*Y!$%_Z zy|vR2wvY`crrT06(KyKHT=leXQ3Ypb2G?JiwA?QGlb;E6O!zMk4?Znt!oua|bjw!3`2wH<>>(P#tzHFy12PW`*s z$EW^Ycjb{zM)Z`J-ENqWzJdM4x0H~6I#ojYYf8ufO$iyODIuq8O2{Bh2^p*@Awx7J zWT>Wu4AVr&8QKUrQyU?}wGncbHbTzUM#wqZ2pOS`kdfL58KsSo0&Rqh)<#I7HbTZ| zBV?>LLdIz$q(~bfL)0B`oni4WsQ$prxBIJB+ zgv{4Q$OYO6xlkJ+7ilBpVr_&h&_>85+6Y;wjgUp!2wAL+kV~}@a+x+lmS`hnsWw6` z*G9+{+6Y;ujgTv~5ptC_Lax?E$a3va$TUC8-DFfweRD{0DCB^n5xpj6a!knef&GQq zl#m;As)XFADIqI0CFCYe3AtHQLT=HNkX4!za;v6Jy zhBiXBX(QxKZG^m~jgYss5wcwyA@67-Dn$6tdADn2;|5`-}D|A-i;{gnX$fAzx`q$Zkyu z`C3y#zR{GBZ#5<4J534sUQ7^$B%6hw5kzUwEQt?&AYvGrX)mDu{O zpUP}~*H4_S@A}DL>$`q3+4`=ZEVjPuC!5W8{Uiu{*H4nbcm3oL_^zKS1itI1DuM6% zsYc+teyS7ruAid_eAiD60^jvhlfZZV)FSX*KSvYzuAkZjzU!wBf$#b`hQN3I)Ftp; zKgSaIuAf{2-}O_Ez<2!|N8r1D>J#{`p9Ta6Br6(Ci}+7FAn`Zs?uj1>743Hql%vN- zV#do9HHrlGZ9FMOCvmrwiM;DrKmYuit^b~)PgNVE!ik)MLD8*H$@Gl=vyOoS|nz^OwoWyVBZFoQZ$hB zrRa3F6b)ia(O|X|4Pi^sP_`5eV@uH)Y$-aEEk(oGC_0OPqO%DoI){Lw5d;*CB%o*% z0YwD_6pbdJsE~l7F$5HiC7@^=0Yyaw6pbgKXaWI66A37qL_pDG0*cNhplAvKMN3TfsDqIzc7IjF`7%W%k-)x{hEk&!?Qgka@idM6w=r*<#-OiSx zHEb!mgN>rK1Qgv#K+# z8weVDCILln5m59t0Y%#hD0+v0qIU@>+Cf0kdju4{Pe9QJ1QdNpK+#SD ziasKs=wkwkJ|Up!Qv!-UBZP{ciTE|$SG(gSc3bqU6#Z=Xu0M~&%$F(pDiYYY!KW1M z=6osonk_}&u%+l*wiJEGmZI<3QuG5`ihg8E(NAnC+QUZC&jb|xLO{{41Qh*7K+*36 z6#YR!(Ov?I{v@Di9|1*w5m2=x+jw{vn{~5CKL15>RxQfTAM=6nSZ7 zkMc89Uyq6qP?Sap743@nqa2X7vYR#6SHf$8NC7`Gs0Y&WzDC$5!(a8i9btIsu69Gk?2`K79Kv7o$in2`HLQK+z0BsAyoC-`oL-&#~L0)1_#-eMFm?7BgR_Xm(m) zKL#kJ=seDsqB(3Sn#-1=d2A^vmKClPx}L;(RH(l`Tc9 z*-~^HTZ(RHOVJv(6y3p=qP1)(x|1zMcd=1)HvvWK2q?OTfTDW|D7ue;qWcLbdVqkU z2MH)zPe9Q_1Qcx`py*)&iXI`L=urZS9wVUWaRQ2-AfV_;0*W>gQ1lc5MNbn@^b8?X zbW@uDtOF9iDdOPVEJfq(w&>ZknE5hAo6`dOF=VORq8B({ie6+((MxP8dYLUnudt=) zRkjpuVN20gwiLa_mZI0$D0+i{qHP2ey-7gPTLcunO+e9h0*c-tpy*u!igplC^d134 z?-Nk;0RcrH5>T|0fTE8GDEgRyqE84Y`jmj8&j={`oPeS)2q@Y`2o*h-=BG7wilX)y z?RhC0ZuhRgOpBQ>Q}j(*P`{}Zearb$^c`D@zGq9(4{Ry=ku60(v88AaTZ(>WOVKZE zDf*R-qTdK8`kjEHKL{w=OF+?|1QhKfpy)3GiuMywbbx@Og9H@)O+e8<1QZ=2py*!$ ziVhP{bcBE+_k+!DaaW`Jin_ZQu)lU1A)qLYfFhrOq9_4H0U=bhJI(LofW#-+ZPC|K zbkIh+A2VO3DDDULV-QofMH!qgMVV|V%3@1VHd~4kY$-~zr6`9jMOD~RRFy47)z~Pi zPC(I71QgXEpr|GRMYRYhI+}o@+5{BUA)x3O0*dMqP;@K-MY#kN)gz$jI0B056HwHE zfTH6GC^~_Fq7w-yYDhp)BLa#}B7}-6`TkW7NW7=ryRPhqkMuvX+oHyP%zT-mJU_4> zqnT3Fob#n9pDjf#*izJzEk&)^Qq-C)MQzwp)Rrwp?buS(o{gdo1QeZ2Kv72miaHTc z)R};yE(8>HC7`Gq0Y%*jDC$8#QBMMjdJ$06n}DKI2q@}9K+&lL6rDyuQC|Xz`Vmmn zpMatP1QZPK_{(BBc{A#-^)J%$gwcDc8{h0YOMMM3-ehh0$(J;=JqBGc1bS7Jh zhO?#UEVdM#&6c8b*itltEkz^QQZ$N~ zMGM$cbO~FE7P3*ah=8KS1QcCLK+$Cc6fGg3Xej|jmlIHQ1p!6N2q?OefTF7iD7u<} zqU8h>T|+?8wFDHcAfV_v0*bCDpy&nyif$yJXe9wfHxWWb=lT9<2P8hqZj0tfk^O|) z=*@o2e3_!veqcWaI;H3~&X=Ow*;2HIEk$>*rD!c%itc1f(OqmQx|=OU>)29s4;w}I z5>Rv>0Y&!{Q1k!+MGq2Cw4Q*XhX^RzKtR#M1Qb0&K+&TF6g@^j(c=UZJwZUxlLQoP zB%tUi0*am{py(L_ik>B)XcGZN&k;gJt9<`%2PEFZ6x}LCeQiAN$IO>0ddUy$$B3sC zz0CPi^a@*wUS&(s7Pb^^WlPa(Y$} zsRw30Y$k46xAc3=r{t3>Jw1Z zfPkXo2`D;&fT9x#C~8PRQ6mD1P9mVFF#$zQ2qt@lI`7%W8BwiKPrmZFYq6m=q? zs51dYT?i=ZNIfTB|gC_0URqP_$a^&_CD zKLJGp2q+pzK+)+06b&MvXfPpE)I91x=YYhQxf#uuqHpZBXh<|>zD&`X(ZK#0mDFv~ zaL$*av)EE}Hd~6$VN1~nwiJzIOVKE{6cwqWRIl{u!Q>q6;`*iY{bJ(M4=2x|l6R z3)oV030sO5vZZJdTZ$I5rRY*NiY_CdXbAyDO9?2toPeS$2q;=cK+%;16kSC?(bWVL zEhnJp8Ul*0C7@^p0Y%plP;@;3MK=&obRz*pD+wsNiGZS;2`IXSfTC4|P|>`of0_dl zZ)kt-`g|$+*FKSbYcyuQOwpQXVE>F$O3@vhFGXwFQgkOmZI0#QuI1oir!#L(Kfaey~&oMx7bqjHd~6evr+U8 z0Y&c;P_%=9qW1_WdY^!z4+tpwkbt6{1QdNlK+(qp6n#QK(We9yeMUgh=L8geK|s+i z0*byQpy(?CigpuF^fduR-w;srEg@9&a@7C80g11-4`Q!K(RzEN|6Md@zD&_i(ZK#0 zxs;+koG(Q`v!&=4wiNx!mZIO-QuI4pivD0r(O$L`{mGW1eQXr{ML^Mh0*Ve0P;`)h zqQ40!`iFp`Lj)B4OF+?K0*a0hP~-)A*p8wI0Yzy96!`=cMF}Vh2q;P?peRN_Q6&P3 zDicr?C!i>U5Gwj1>euP-6s@z5Xg^9(%)T6w8N|$&DM|)`{WF9qMLC==MOD~RRFy47 z)!0&0oh?O2v8AX6TZ(G3rKlELijHQZs5SvbbqFXrhJd2F1QZ=hKv6CMMfC_MI*x#% z`UDg;AfV`Y0*X!`py)&biW(A7)QEthlL#nkOh8c+0*aavP}GcoqC5hMniE1r*?~XC z0g2bOzjvJo!bkce?S?5oh?y@_)H(?4pRr6SYQyka$PCL)}V>HrhBN zh?y@_baoKfKZBZ5bPnfB(FnE_jbuyFD7F+8u%&1;TZ#(VQZ$AwMPu1gG>(m;A_9uW z6HqjPfTD>66ip(aXfgps=Mqpfg@B@|1Qbmpps1LDqUi(_%^;v?CILky1QeALP&A8x zqS*u#oku{?90H2w5>Pac5GooT_`f(H@r`y@=qxGPVz))-2Ql+yiY^KQ`)71hiZ14S zDO$jmqD$CPw2&=Di`Y`Mm@P$@vZd%UwiGR4OVLs`iY_Oh=n4XgmJv{NB>_cO5m0nB z0Y%FRD7uD#qH75#T0ub3bp#Y$Pe9QP1Qgv!K+#G9if$sH=wT|7 zfTG(7p`r@{zm)?LFSLhc7fR8Oc3X6N5Hnw<=*}Rpe}*}w=q}EeqPy8rw2m!B_pqht zUbYn7$Cje|*;4cXTZ$fJOVN5ZiXI}MXafO74--)I2mwWp5>WIQ0Y#4!Q1k==MNbk? zw2^?KrwAx|nt-Bb2q=1%fTB$V6g@{k(enfpZ6=`T1pWIN0Y$qBDEgX!qHhQ&`j&vA?+7URo`9ks2%(}afxp=SiPx~(qODRi#6F_^ z7{tt%Df%S{?4N;8Df*T3rRX=d6#dSYqCePDw3jVKf3l@$A6tt4VoT9}wiF#;qv#+3 zMSl}e^bY|=hX^S8mw=+f1QZ=1pvX(t!*&!!2q;P;pvWhnC`v$4KtNGC0YxzaiYgIM zRGEOHH~~c&1QcZwP?SYLQ8pn|v?uV>M><9Jb=T<6QuMDq>`$b}%$F&unjV~3AVt+U zUy7=;rRXTO6xCo$QBAfK)nZH0(QGNI&6c7%Y$-a1jiR~)6dg-IQ7!>R^#~|Bj)0>2 z1QazOpy+r4icTP)=tKgF8WK>{h=8J#2q_CpI{IBTcyX$mnmwO9!xEiqV}9GMIG2ubTV6tIlsW(dh&f4I-duFabqF2q+p#K+!M)iq0UQ=u85Nh7&?XZPNW~9gz55 zyI<5+ikjFsD?MhuOwq{n;L)*CG>Y@3sDLd+quEka$d;lpY$+PcmZEWNDJo)1(Rj8L zO<<#FA^}B{2q>CNK+(Ab6ip$ZXet3k(+DUkCZK3K0Yx(iD4Iz?Q3(M>r34hsBA{qC z0Y&E#P&9{tqPYYV%_E@bd;*H*6Hs&kAyjluy1&x_i9cz7zi5OM-D)4vE=-S^FH>|$ zdT_8viWYLd6fI&)(PFj~UCNfC%h*!1ge^r&*-~^lTZ*n=OVKhmimoJ}=qdt=t|p*p zIRQo25Kwe20YxhaD7ub-qU#ALx`BYA8wn^{NkGv}1Qgv&K+!D(6s;nl=vD%XRufQk z8v#YP6Hv5fQ1l!DMb8sZw3&dS7YHbNk$|F?2q=1)fTC9jD0-EEqAi3_ z(Ov2OI0qzN%RWVPw-l|g+oG-MG4o}LwxtJ)CriONnP?SzUQH=2a5O?3vQPuIg z@AqV9m}F9BLhnUT=}G7yNJmsas-U7FKxhJiBp@IP2sT6z8;GbNA{JCo5F3h$iX8_U?%j1Qewc zP?SMHQ6>RJF#?L>1QcZv0!2qE_(vU(=y!JWb5x3I*k`ngk%;*+MO7o=tU@WO#`#iI zoh?N**iuxJEk(81QdFBQMRnLxRF^G9_1IEWpN*mh1QeY_Kv6>iiW(76bTR=&rw~wd zDgi}}2`FkpKv7cyikcBn)SQ5#76cTvB%mmpfTA1%igF1kYDGX%YXXYe5Kz>XfTDJU zKvCt0-_8Mv_OVC$RU*M7{mS-8zkMWPzD&_+k?`>8Qq-CArKk&AicV)sQCGGUbz@6W zceWJuU`tU?wiNYZOHpq&iuw>xbOr%MeF-Q!lYpYL2q-$6fTDf`6!j;dXaE64=MYdd zkbt5=1QZP>plApIMMDWF8b(0TxdapqC!lBq0Y&E#P;@>4MHdhPMI9slTn8ljwVTPE zq$p;$MI$2-^JR)gMZ$L!OHn@OOVMby6pdj^(O9+=6|kjf99xRUv!!SPTZ$&KrDzfx zMHdrLG?{>+DFhTvC7`H~fTC#x6ip|fsEB}~Vgiav2q>CCK+#MBiY_6bXchrQvk54g zLqO4`1Qg9Bpy)CJiY_OhXdVGY^9g~Xiz5CD4oGyR!O4@Nv+dK{f=I-CnW8Hr;e+lU zl}&sH{)Ek#S&QnZYXq8kV(T24UGjRX|k zL_pEa1QgvuK+&xP6s;hjXe9wfw-HdZih!cq2`E}kK+zop6x~Tc(Om=-ts$UjEdfP$ z6Hv5{fTDW{C|XYl6fKPSDKnj-2i#0vBt@^WIw0Y%#gD0+f`q9+L`dWwLerwJ%} zhJd2&1Qb0>K+$sq6zw3O=y?K)ULc_8MFNU;5>WIK0YxtpQ1l7`MY{+ndX<2p*9d{4 z`y&1T2PAsbem3@gDOzZ^MXyI9=F1el9SIlCk)qw4FGcULrRZI@6zyS4(O$L`y~mcK z_t{eP0b7bbWJ}RUY!vMypy*=)iuMyw^a%k)pAt~?839EH2q^lTfTAx5C^|?$(U$}i z9U`FUD*}qXCZOmW0*byRpy)dSioPeH=r93AKM+v#BLPK62!WzEBmT_}Nc0ll!FfxH zp0nGcqmhXDGDW{c!dvG`(Q(d~qF>ok^c!1>POzouceWJ$!Iq*w*;4cuTZ;Z>OVK}U z6#Yv;k(Z)}?I;QnP?SVKkxxKTG66+l0*WdSP!u7cD20HcR04{k1QewaP?SzUQ3e4; znFJKY2q=mZP?SYLQAGlZDiKgrnGh&C7V-BvAkpRaRmY#DsFjhbk`ggrrl>|r_|MCw zs3zx2Q7yI<)n-dk9kvwJWlK>#wiMN8OHl*16rIGDqK0e~H6ozsWCDs#A)x3~0*V?F zP}GEgqNW5CH6x&?IRQm22q z2Lg&Z5&}ilQvCY!oTBIKJ0R6lf=Bw@?K4`Zl!*Bm|va|tLKPC(HJ0*cNfpy+%8iY_3aXe0qe7ZOl(5g}02ImI96 zfJDa|oGwzd#%_!9QX=Nd6pcv1QbmpplCV)MMVS@6%$ZYLO{_B0*Yo5P;?0aMY9MfnoU5_90H0i zC7@_70Y#S)P;@x~Me_(KnomH{0s@MzAfRX=AyAZ`;%{_7qUm;5XtWfyH&TmIBIe5! zU6T@i^GYeYmh+`(FDO$#sq8r#!w45zPH?mQ569Gjx6Hs&u z0Y$eGP_%-8qLl;`-9|vsDgugbC!lCG0Y!HZP;@5&MRyTUw1$A9wFDI1O+e8)0*dY- zplCe-MfVa=w1I%4`v`%et5W=94oGyHee3LMDLU0i-JcRMU#94xlyIeMr08MJm!e15 zQnZOJMVr}D^e9`39%D<<7Pb^^WlPcHY$@8tM$r=l6g^2m(NhEzJxxH-GXxZEC!pwA z0*am^plAmHMb8sZ^a24zFA`9+lYpX^2q=1)fTC9jDB49p(W?X$y+%OM>jV_NK|s-) zgh0`QDSihBBs$#9tQ1m?kMTZF}`hkF=9|zQskxT zak~_S*eFUOpvWhnD4BqwFabps2q=mWP?SPIQ7QpNQ38t62q;P?peTcYqD%scVgwY$ z2`I`Upr|4NMU@CBs!Tvp6#|N?5>Ql)5GXpH;_q}oqSxEa&#zKc*GBc!i1{)_wNt}~ zmP%0_&X=OPY$>Y8mZJJ>DQdu$qLbKC)Q~Mjjo4CjGFysHVWa3&0*V?FP}GEgqNW5C zH6x&?IRQm22q2Lg&Z5>V8M zfTGg~DC$fI6xB@iqsyG4yDB(1wNise`g?42NsX8dBU(UTi7q z&6c7*Y$-Z}Ek%9VQgkL;iq2w7(b;Si^&_CDKLJGp2q-#-fTDo}6b&MvXfOdqLkK7u zNU+td_th8YpOrc z0f`pc%}+Nes*`xYmKrf%rf6Jhc=}CJG@kRNXaZY`CbFey5?hKcW=qjzwiHcaOVL!e z6cw_iXc`+u(+MalBA}?4fT9utie?Z{G?Rd$O9&{MML^MP0*dAkP;@B)MRN%#x{QFL z%Lyo&M?leh0*V$8P;>`)BMFM$ycXF z%$F&;E;YRE7Aac7`BHQ}TZ)#lrDz#jif&*_(Q>vF-N=@ro7hrxGh2#oVWa3)0*Y1; zP_&YOqT2{4T17z7?F1C9CZOmJ0*dY=py)0Fiq;TNw3dLPy9p>-M?ld%1Qe|&py*x# ziZ&2XbRPjl_Y+X`00Bi05&}inruzFGkZ5l=lNU?TKzrD~F*RboOwp#)@ZT$>Xfx+a z(W7iBdWHqNfQcdWL|a?F1A(OF+?c1QhKc zpy+u5ie4a~=tTmGb`ntZ5&=ao6HxRD0Y$qAD0-EEqSpv0dYyoxHwY+tlYpYP2q=1+ zfTG=mK+(gg{z)sHqDSltjgLrCdwY!bPHMz_nWFbn!#!6?(fgb)MIW%G=tH&?eZ-cc zeQYWEm@P&7*;4cgTZ%qqOVMX+6dfR-=yL*!z969JAOS^R5>RxAfTFJmDEgX!qHhQ& z`j&vA?+7URo`9mm1Qh*1K+%r`6dfU;=qLe2KM_!LjDVt_2`Ku7fTH7sK+&F5e}V%N z-EMzMZLbu4X5X6qH8o+H6uRy1P1 zOi{gP`0YETs6OXQQ3JLVoy3-+hHNQn#FnCy*-~^0TZ&F)OHpIC6g6R^s3`$O%?K!J zPC!u$0*YD^P?SwTQ4Rq`xdaroBA}=>0Yz;HC~8YUQ9A;P+7nRJfqv)EE}Hd~7Nv8AX#TZ#s-QFIOgMFR;a8bmJU5KuIffTCdp z6rD>z(QpEaMi5YR9sxz?6Hs&k0YxJTD7uh z6wN1~XaNC5R}fINkbt5^1QcCKK+#nM6kSa~(KQ4VT}ucQjgR{C9gyhjcJnhqikjPJ zw8hbg`7%XIqv5sdrDz%FOVJH%DO%2!q8r&#bQ4>OZe~l-Eo>>el`Tap*iy8TjiTEK zC|X58(d`5jttO!84g!kqB%tUn0*clUP_&kSqPqzwT1P<9Jp>f3C!pwF0*W>eP;?&w zMfVd>^Z)@x4-!zck$|Fy2q=1(5GYy_^CqQmS9jn_+26MLlpNHk);OwnV}@Yfrp zXba~{(N?w;JWIS0Y$G9Q1k`?MQ;*N^cDd{Zxc|on}DKs z2q=1&fTBHwK+)!?pMIZH_c;2q^lBfTFJnDEfwgqHhT(`i_92 z?+GY6OhC~O1Qh*9K+zEbijERc^b-L^#|S9;nSi2S2q-#EK+&%R6#Yg((FsDJ=>4ca z*a3-7GdLee(G>gi_Ios9zD&{I(QxrbDf)-=rRZO_6nSZSyfKv4|>ifR&2REvP3+5{BUAq0y4jQT4bkm!EmQgkv~icVom(Wz`HYRs0RCTuBc%9f&LY$VQQ1+5MshX~84?hwQefXIjL3nW8h&!vAiPqQ0Cj zMQ5_5=q$Droz0e_erze~&z7PAY$-a2Eky&_QZ$H-qQL|d4I!XtC;>&o2q-$2fTH09 z6pbLD=sW_7&L^Pg0s@Lg5>Rv@0Yw)PP?SeN(I^6n@(Cy!O+e8Y0*b~GP*gxb(KrH% z#uEZXz0>?go1LPn_8pKuQgpL>Uh;&ri1{)_lheYzACsafoG(RF*-})W<`7VHDFH=u2`IXZfTGI@D4It=(R>1m z77$Q$1p!412`E}bK+%;16kSC?(bWVLT|+?8wFDF`CZOm#0*aOp0!5S3{7DW-bc%f& z|6(cHXWtIFJ}qLtOwsbR@O4|I=tj<$qMO)KbTeCuZedH&t!yb;!Iq+xY$>{pEk&!? zQgk~TMXL!Yx`TkCI|(Sdi-4jv1Qe|$py+M_iq;WObPoYV>j@~jmw=)T1QgvzK+*jK z6g@yd(SrmOZ6u)RAp(jXCZOmM0*W>fP_&s4C|Z{0Z*oAQU)gs+ZjhqU_8INbw21jK zMUSV2-`OTb+c;l}o?uJSlWZw^iY-M?v!&=6wiIn=OVP7zDSD1AMLXCidY*uy7YHbN zk$|F|1QfkQK+($t6um+~(JlgtUL~ODH3EuWC!pvJ0*c-wpy(|EiryxmXg2{x?+{S* zE&)Y*2q@Z1K+$^y6unOf6m3cKe|12jtqsmrDN0W~U`vabFH`h!TDaO%Qna7*rRWp3 z6n)B;qR-e;bbu{IpR=Xt3$_#;WJ}SPY$-a#M$uOU6n#xV(KiGXeM>;mcLWrDPe9RO z0*Zbhpy)>eijELabd-Rip9m;AMnKWe1Qh*3K+$mmihd=a=r;n2P7qM^I{`(15K#0d zAyD*Dn%~(0i5|9l*ZZVsxRLrREn>b*k(VC6@EIuzrR$Nr6eY2x$Y)DYGFytmY$>Y1 zmZAt-ic;88l**Q(C>up-1QewcP?SMHQ6>RJF#?L>1QcZvP*jnCqDll5RVJXQ3IRn` z2`H*YKv8u9ifRy0RFiorKmYuidwLxs3lv9ve_ug zA)qLifTC6e6tyOxs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9okl=WX99}45KweF0YzO2 zDC$N)QFj80dJs_5lYpXL1Qhiq1d1A_`@0;F=s~+JYLp&4((jP&MxXSE`7%XkrH8-W zAw_3%z7+LiOHqHe6b)cY(K&1>8pxKSL2M}+%$A}dY$+PbM$s?=iq0jVXgC2yBM2xu zkAR}{2`IXNfTEEE6kSL_(M1FlV=JQTbrhV1%OetF6o|k-adc=I0qQdlW_KQ+9jq{~wI$Mg0*iux? zmZB226wP2u(M+}!UBZ^4S!^kq%|_820*WprplB`uMVAp!bU6V<^9U%KPe9QE0*bC6 zplBfhMT-b1x{`pRs|YB%nt-Bf2q?OifTG0&6kSI^(GmiRt|y>qDFH>x2!Wz0>Hbg$ zB)Y{O+)tIFmu=jT9x-30=;rkBjF+V77S5NVTiH^yf-OZW*-~^HTZ&e(rRa9H6s=}U z(H(3lx|5Bfy9g*+LqO450*dY?plBTdMfVU;w4Q*XdkHAoKtR!b1Qgv*K+yvP6g@~l z(MAG_9wMOVVFHRCA)sgz0Y#e$D0-BDqQ?j*+Cm5v-I(sLazLVm_EpE5r0AH9t?3c- zWs06m4?q2i6g|cHQuH)iik@Lh(RQ{JJWIS0Y$G9Q1k`?MQ;*N^cDd{Zxc|on}DKs2q=1&fTBGF6zwIT z=sg08-Y1~w0|JUZB%tUcLZE0{x_`g{iLSAmpC_cKu6thczVwLsGDV-JheNMP(Px}5 zMF-eY^f_CKzFv9V4LVX99|TA)x3u0Y$$OQ1lxCMJEU-`kjEHKL{xLlYpYX2q^lS zfTDj0fujBC{wWSfw4r^~@e?WPXOHy%O^=u_Q{-oa&v-+Mk~9AMNI%S$q6%y&im;_9 zg)K#?Y$=Mer6`RpMd@rQ%3z}?lYpWa0Yz~Fin0hOsz^XlB?5{n6HruzfTF4d6jdXj zs5${fH3%rGNkCC80*Y!AP*jJ2qPheW)gz#&J^@7y2q-#-v2w(q}6gA;|-4-=vOHnhn6g6i{Q46*dwPZ_CHd~5v*iw|s zmZDZ{6tyOxs0{%{Z3!r9M?g_~0*X2iP}GrtqD}-9okl=WX99}45KweF0YzO2DC$N) zQFj80dJs_5lYpXL1Qhiqpr{W4MQ0FD)Rzz_Iwiw@)B%Y$F*v76(WUn3?aYjb`7%ZQ zGs1h^za^Xa`>qFYz7(CqmZE`dDH_CD{#+IUU*-|u|jiM0*6rD#v z(fI@vT|hw5NCJv3B%tUb0*dkoC>ljTQ9c1hqX{S)LqO430*VRlpV(Rc!iCJ<0G zk$|E}1QcCNK+$9Zilz_(MQ3ODCmfLIZFXDKPm1jBQ1aA_i1{)_MH%55d!(qC^QEYS zEk!ffQZ$n-MVGLpXck+FX0xSe4qJ*YWlPaqHi|AIpy+Y}islheG@pQ?1q2jbK|s+$ z0*V$9P;?~$MOP6}bTt7**AP&2EdfP~2`IXbfTAS?6kSh1(NY46mJv{N0|7pzg9?VK+~&$6ZHIkpt-U`x^SY$ugcjJ?ci1{)_ zpJ#->|453y;Cv}M$d;ln*-~_fEk$3krRZz66n(>%qHoz!^c`D@zGtK8FabqB5K#0Z z0Yyg$C^||&(N6>v9V4LVX99|TA)x3u0Y$$OQ1lxCMJEU-`kjEHKL{xLlYpYX2q^lS zfTDj0DEgOxA}>=9%uy5~1d2Y(@ZVPY$=MfQIthMQAGlZDiKgrnSi1y1Qb;zpr{%F zMb!x?szE?eO#+H)5l~c{fTB7C6xAi5s2%}D^$93yKtRz+1QazSpr{c6MJE$bbP6F* zl$`0G>wrWX8k}%u@JQd?({>NoG9%{86gA5XU-GFGHRpUOYQdJGmTW1?W=l~HTZ(eo zQq+nqMXlLV)P^lZZP_SlM?g_~0*X2iP}GrtqD}-9okl=WX99}45KweF0YzO2DC$N) zQFj80dJs_5lYpXL1Qhiqpr{W4MQ0FD)R%ywGYKdIVc)v>7* z4Kq^xG9%{86b;M_Z$BVKgE(J`2D7DT2wRGVvZZJkTZ+zQOVMz)6pdg@(RpksI-iZA z3kWD0NkGws1QcCFKv5n6MWYBP$|s;`Gyz3p2q+p$Kv4k!MdJu48c#sc1OkdC5>PaW zfTD{DD4I+_(G&uTrV>z8NI=mvLZE0srvHTl5^ZgN?)n@lnq~K{r)NgYmnoW&8TJoK z(M-;lqD$CPG>a`ov)NKKhb={yvZZJ)TZ%4YOVQ1m77$Q$1p!412`E}b zK+%;16kSC?(bWVLT|+?8wFDF`CZOm#0*aOpP;@;3MN0`NT1G(84FnV|C!pv?0*Y=T zpy*}-if$nUii$J+#tukygWVRDNYOv`u>aP~i1{)_t1`o99+INlIbVuav!&<`wiMmT zmZH1ZQnZFGMQhnobT?ay*0H7N9yW^B6Hs(70Yw`KD7ue;qWcLbdVqkU2MH+JNI=m; z1Qb0?K+z)v6m24)Xfpvtj}lPy7y(6F2q@Z0K+)p_6m27*=m`Rfo+O~?DMFxVWu`yX z0g2AHuR7i)MSJbG=;_Re`7%Y%Wrml1Ek!#xUy7b*OVJB#DSDADMLXG2^b%W&US>WIJ0Y&==DEgRyqWuIEeL_IdrvwyzMhFyb&-AxAAkogggY&EuCD}NT z88Kg`=*!ITd*4dYA%bHCu|lVN21sY$^JVEk)n6rRXqQihf{A(T{8t9U-9T zC;>%35m0oDfTEuXDEftfqT>V<{YpU5Zv+&bAfV`X0*d}1py*EmivA*?=x+jw{vn{~ zUjmA}m>#yHC`3R}5&=a%0Y%A#K+zYO{vQrV^b`Br9u7*;Ev6_Oi8^Sp*cFO+ZmU0*d+*P&9xLC~6+_uW~@5yX`Sr z3n>a2sdHix^JR*L#KIenO3_fxm!e^8DLR)eMZ?)rG=eQf=dq>ee6|!_z?PzsY$>{s zjiQSPD9R(CXcPfO`2-Y=CZK2x0Yzg8C@LVJXdD4W;|VC5KtRz%0*WRPP;@Z?MUx3A znnFO)R04_$2`HLIK+$vpii!v*DkcPq2F3h09FXXA``YzjDe7RiMJ2I_`7%YbV&NZ- zNzrW1m!dgrDY}#`MRVCwbQxQUE@w;8Jhl|gXG_rnwiI2#M$tk7iWU)2bR_{rR}oNj zH33D}5Kwe20Y!@mD7ub-q9p_rT~9#KQUZ#W5m0mk0Y%FRD7uk=qMHaPx|x8YTL>t+ zm4KoZ1Qe|#1d3+H{E9z2MSt2C8ZVKe>h`ezwphe`nW8&l;nv5c=uXa;qPy5qw1zE3 zYuQqCH(QF0*W3Ypy*)&iXI`L zXcGZNn+Yg-lz^hg2q@Y@K+#qLiXJDRXd3}VPY_V_BmqTF5m59r0Y%RcP_&&8D7ro7 zk8nVuUF^1KwG=I|PjAo0BIe5!y$}n}{!NNr`OKLJIb5K#0f0Y#q?P;`KRqR$B^`hpNB+7a{bbU>ox>|xpSQnbi! ziw?#j=F1d)9ScAAyA*xH`BL;PTZ+D8OVRgiDLTxSq952&^dnn}jLZB!b_nSH((a%yHoV0lGNPm}odTSAnm@iY58xNoTj}*1yd?{+pmZCOnDQe4> zqIPU4YR{IU4s0pv$d;l`Y$-a8jiSy36m=n>=yU>#x)M;-jew%=1Qhikpr|JSMZE|p z>Pl>d(F6jDCK6CIiGZSu2`HLOK+zNe zil!1!R7gP4Gy;mI6Hrt{Kv6LPMI{6j%^;v?CLvHXH10p{fJC3LZ=DU3qN?^t|B`sb ze3_z4Rv#0Yx_xP;?6cMYj@A zw1R-5l>`*sMnKUj0*Y=Y1d3+I{l6TL=rsF6;~XhUvfHB7@rd~{MQh^WI$~_45>WII0YwiJQ1l1^MVkmH z+Dt&vqXZN^MnKUP0*ba0Q1mzfMcW7{dV+wWCkZHeih!c02`GAofTHaL6g^8o(Q^b8 z?H~k-?u`3A9FS-OyZO0``$eYc`FO;9nWC5C;V}^@dYSX3=oPjU?P5#Ot86KHjV(p5 zv!&<_wiLa|mZG=VQuH<(MY{Tihd`c=nn#l{v@F2F9M4GCZOma0*d}6pvcS8!*&#f2q;P- zpvWhnD4BqwFabps2q=mWP?SPIQ7QpNQ9_{To4Eg$0}`F(X7aaEG}<2Nr)5RVmnn*6 zg^#33QJnLoD2pvc71>f$i7iEy*-})6Ek#w?QdEsCMb+6-RD+G8ngkTpBA}=?0Y!BP zD5^_9Q9S~R>Jw1ZfPkWt2qnIF#$zQ2qLKO2P88qc%;A9Zi{lVBIe5!waE&%b$?A(;xSrV&X=Ng zY$Jqal4ML?XMSTeHCZK2t0YyUz zfudGf{`n3_w4OaiYb`~~>|y_~tcdwCMdxLOFO5sl`J69B7qF#hBwLCuWJ}RSY$?iP zOVKE{6y>v}Xf#`j#;{Q|mVlxH0*b~FP&A%^q6q{PO(dXb5&=aQ6HqjnfTAe`6ip?d zsE~l7X#^BaC!nZ^fTCgoib@D5nn6I(Oah87A)sg$0Y$S3fuiAA{u&1)+Rko^Mo7`m z_9e(USrPMPiZ0IzKVMOb=5f9h&1Xx|0=5)g!Iq+hY$;mAmZB@!Qgjttimql$(KT!o zT}wdGVgib;BcNyr0Y%pnP_&eQqGbdW-9SLmasrBOB%tUf0*Y=Xpy(C?if$#KXaxa9 zD+wsNjew$61Qgv)K+$RfitZqw=uSeQXl|DOl>-u8Wj8;UNzrdM?#haoFH^KGD;%jJ zMfY&N6s>1V(Y`VUl34qkbt5u2`D;5K+#tO6n#xV(Km!Z(aTwW zkpmJvZjba|ks{yWN&Yq~V!lk#4_V=xYDm$KoG(R3*iv+qEk!@ErRW%2ihgEG(JyQ% zI?k4&U)fUh8yiI@2q^lUfTBMLDEgCtqQ3|z`kR2Fe+Vf0mw+O#q8_%RC`3R}5&=a% z0Y%9K6om;Wsz5+dgn*(H0*X=zD2ftLltw^NIsru)gh0{vS^g6aNVKW_B++3hT4bNm zGAl;Rmno`PG5k?2DXPTzQdF5OMOD~RRFy47)!0&0oh?N**iuxJEk(81QdFCbqB;Z= z)g_>)9sx!52`FknK+#DA6g4EEs1X50ClgR~3IRo@5>V8bfTAV@6g4HFs2Kr8%?T)K zK|oPU0*bN;D9RzAD3^euR)j!NyrTb)0}@?tUn0t?7(CKnYPUtLD@M$hDQaIaT(7Pa zb>Ms{>d2O&PHZVUjV(o;*;3SnEk&oZrKl@gin_6-s5=`)JqRf3NkCCA0*ZPQP}GNj zqB966>PtY;nFJJ_ML^Nn1Qhinpr}6qMFR*ZI){Lwfdmu{BA{q60YyUyC>lyY(J%sv z&LyB|I3ZBfwxZw50g1LTIPIipw%rzus2DL{rf6iva6x@3x{&jw=pwch<*}t`6kCe& z*-|u`Ek$G4QZ$w=MFngr8plS_cmj$h5KuIcfTBqR6kSX}(PRROrVvmxm4Ko`0*a;) zP&A!@q9Ou{iU}wxA)sgm0Yx(jD7u7zqFDqK%_g8|4gp1%5>Pak5GXpoqQBSyiN0fx z^e>R2yY184Wfddl%M>lB7=G|1DY}C5rD!2riWae@=t{N}UB#B7tJzX?4O@z?WlPaw zwiI2*M$r-iimoT1Xej|j%LpjCfqRv- z0Y$3_D7u}1qSXWx-9bRnodgu!ML^LS0*clW0!8yG`nw&F=n*%Q=S$HE8+TWXm@hBW zOG<8-TI-aM7u(>zW$VRWHE^---FIwLVj1qyTzV|q-8GNL24#3&<=8DT&#NB$ILq^D z#~M`jy!x^6RXwj!?4jzO*EsfbP0wo{>sZJ0a$@u9d0v~?OAS1)LoBV4=XH(^I>qz4 z#a1--yk4ER zO>E&H&s!3Eb%^KP5R0Abc{j&~jqtpcvD?r0yw$PKM|$3x*r|D*cTa3ezUSQ+du)v7 zZH)b1;CY*3T_yth2nOIh#=k16MpYC}(V|NsL-mcie8J_n>tjR3T z+Z`*M<9T~yTjzS-hp|5|_q_eF?h8EcKi5JnwMqyv3e(G62+!YXt|GmOp1EF}&RqiSX#jjoMu7gng?K|C- z5Q>#l`R{DO7vY6!*Gu6Nf%C~p6neWOs^{yFl-p}75f(#=D0`v-w@LUH>SUE74> z_D^zl2*vH+RO}pz+dqoeEflwZ)vQ-2ZvQM*-%#BCU7>!V__sUUbrOo(zw9wI6t{nx zVMHiyf4Ba~P~84<^iiR>{q5FcLvj1-i6?~O_V>$94#n*+2%Q#++u!h55{lbj(Kjm; zx4&a;ZYXYlN!I*O-2RrMMWOii1MV6M#qIAISrUrdUlegeC~iOLe{(2qKdQYl6t|zX zT^)+s4@<5I#qFov?g_>1$Cd62#qH-!HiqK%0|T2var+bBTS9UBBfC$8;`V1Qp9#h7 z56$fe#qCc$?F_~3kFD$q#qG}>yb+4qH;#9Q;`W`ty`i{$>*m8y+`jg{KNPnwo*oFr z?WtJKx~?h3W8v&@ymv)r-r_3pG#+e~X-Wv9*ywbRJ4=d{;2 zWT$q>be!CaZFavWLml;;P3~2NI%&LY=bWbTrj5=T7lhpCqEXd%<8+N(Q8&73IOSfb zTQI7)XLxqOtGeIiURC!*wa`F+d5L?2)#tg_VE=^=Csn9^k9%+JzwpU^)C*;WPR^{9 z=4aN*99AvM3G=+9MqXOl=`MMmU)A$7JEfhL)-mnOO6~)u=cKrk+j>?iR0^e~1uqbC zGm_!?DZG4IT1HxWS_k*ur&RmTOQpJ(D)(BWn&IG$r0G?18na+`9kwtK}@uD!x33gx<&uj-z3A4Yq!+G1CesxR;1Zepvq^t#sQTw`ix;?20X z>#miuU+&i0ksoLWchl)5dCN=eX#A4A%SzlK@vFA`zunZkkA33*_CI@>^1sUOkh_w7 zZ>&2dDfDM%h8J?b+{>D#mMyc3^0UVkPs=VY8k1d=S3IU5Z(31dNx_(sg0b0Sie^tM zDYP)AVC;;dg5q+|vzK=--7$Mw(ZneeOD4`N@UkZqPASOFpIk62yXEAZ)-CMWE#0&K^Q`QNQ^!o6F}5IkO8%G$6Q}DE(N>Dk(~QNP>^Zz@oxQ?qgn@J!D#b(ZzjcOwAkW z-k0$MC(kI(8{EBJ|F-`(uBMs!B?b1;^1R@R9yep^n4Gq)T8=Rad1DL4<4U1KLsEpfvM8q%|Op1YW1dKONZQaIH$hYv6l?NtZKb2roBgigP8C>*Zz zfBF>;Rq)4$T86`ZjrtX`!xbxp!j;{jUN~H#LAbJ8m2$%s>t;7kY)A24Lr&kk(ZQ4L+LS)owrA;+ z?KGY?$p!4gYjIET{`M|?hjQJ8 zNxXbV_hNZ@?(EjB@`Bfp>)seA^x?I2*K6xh_8Q!W!oAqo8B?ar4qlU9wheE%yF&ZY z3*bJorLVd4jkMuy^eX#cxDSC|&|T!2QTqV_kq=UZA)L7yF9$n zR(ko?WtXF8=^42_?M>wwb^YcD-ky6mbiTnTcRTlg>vwmrg3&X^d+sK2>iB}Zf~jLC z=10{ES?6Nxz!Hbu^v#`r4dtW=2z9+ekws&^#^YXg) z8k{)KUD0|c9cVq(>py3Dc9H5Q{`bG3%PqSgJ>&|0?n?d72Q`;Br}wV(ZS+pOj{lpV zlk_RA?3T`c`{(HLx!)&xH+z)6!*x6Hl!@aWBAF`>?0mAeHBJ|<;|bDiR#iu}Zp`$o)}zL2+}m=^Zs3Nx&-1~D+%^{jK56Eb6Hs=I=ayaNxnT_?K z=WR{iU~X{bCVq>Q#ax}?uGF%RuY2l@0mJI|?AWos-Lr0)Ti@#RX03x0o_!+Ket^+y|^+R*NaETf0y)VaAlv?l^98VSY&qcgMVoyH>_p za4$J-+RU~sil?<0o7>Kn{Gu@vy10AlGdr}H(sGKsuitEJ@w8^+rqypTzJ7~yTGemi z?p$^m<1RppaZ?J4i}S}9w3u8lb$rQ$E;%j*cWGMKmF||^ewR!voZ6z;-AQ)GV%Nsz zm*ki3;6vf=76ea}iM1PVz1ybo|Ma;lP+9KtYbiZPH}N{l?k5_?goM)9Ty`fhH}GxG z&UH7*x>#jbMu5EZlV`$oUfzE{vvV)C>`p3d?B3KleTI~N#?IwFY1!S%vU`(dcP8E4 zQuqYF3GCu==QWo*qGk6H%iTrferVbKL4H3N&*0tTjwyzNJB5i4f!!0;ozuj-8vO1n zefRm@R*D+ac8~Pp(i=eTc$VEcEW2-r?$WEi^sZ;=eah0ikL7+FmHlQYyYt62U3O=$ z^coEAKYC~M?AfV)WBZNMy=Y4P-cv>wj2-LlcMs*!Y~uG4k5ZfbpMPiB1NC(G-@opc z`_jPNO!xH+dr;3Wd+^>pGi6cI(opxz_<5P`ODkUYj_!Z?_E^{pWxFTC9a{8n*}wal z1H1}Zk^ZTEG^Jv461&knPF( z|9*|c_uSX9%l-1bSh;1d|G$^U_uQ9Y%Kh@aishEQd=<}qEhq6_+sD14yZk4Ydx^Mv zy7m9q|J&o|MkQXOvH!V`>pnS^dl-@X|8&9|P8 z8+2T!<7WF3l6yPbb=>2wTHBxLc-*}MwnOf#mUgV>-WNMI)X~1&WxKbI7r6Jq_IMrF zxU16kLppxtJ^;3V*0H(!7}@TqW0Cu!rtNt;KH=#TSAf0zBRYQ5G}y;=Y}q2%r|DSYt|)u? z1v);J8|+tf^x6bFL&rYu3bmIXqT>?x)j->~>G*D^V1K4#b$7+v^H0|CqOQTdSjT(1 z2Ya)Q-}MakZ#w4m33eA9XZ8*DLLHwuE7-5+SKou%Vh z6M{Wl#~UUE`wku7pB(IiI@T@>b`u>(PY-sXj`tM@d#jE=&ItCOI<}b=?Cv_wnG@`* zb=)yG*l+4sVP3E+>DX^Uu+P)+#)ZMYOUDnd4E7-%>s}M=W;%{t9PH^jKCmR%+jKm- zG}wRZ*lu~Sd+Ip%reI&I;|sS0`)wUlRtCF@jssQ&`vM(rULEYUI_`7d4YTX#YaQ#a z4R#A1$E^!?v5p(p2m47Kk8KF{zdCk!AlSWiynJJ@uhVho!@+(>$LQu@SJQFeW5K>q z$6L1sd!3H^w*~uK9Zz~H*x5QxcqZ60bbR>PU_Y(nFFS%AdOkRIdNDYjq2v6Qf_=S? zFTWD(Jvyep7VH{24t^upc{;9qE7p-yI(=qd4uxsf!^iZ(#bzJpzus7&<;M-vTpyMfr zgWX!k$v*~rwvLY;4fb<7o;Vil@Xx{V^y9(tY#kT<7VPCZzUIE`Xz$+#I>!GBb{!qh z{U_LCbX@K3CD_Z~uj3c)JCnAL=-AkO?b~)+9j8WueW{LH+&3-l`OoY4hx_iO?TGvF zAv<<+-^R3Ke;u!K-_Nvtla6n=Z*1EBNXLrqJDj%b={UlDtJ8LYj(586dD?zZ$1mMC zKW+b{V^jBCP}}WwoK`>Bm+AQUNx^$pqD_jLS1$0K%hZ~ugjQTP2#yL_2CR@1STjuq^FjC*-^ z5fjHO9joZ*?iM6^1054DpW?n@sO=7k=exT*iDR+d4|1>1-5v3gV(z